/*===- TableGen'erated file -------------------------------------*- C++ -*-===*\
|*                                                                            *|
|* Global Instruction Selector for the AMDGPU target                          *|
|*                                                                            *|
|* Automatically generated file, do not edit!                                 *|
|*                                                                            *|
\*===----------------------------------------------------------------------===*/

#ifdef GET_GLOBALISEL_PREDICATE_BITSET
const unsigned MAX_SUBTARGET_PREDICATES = 104;
using PredicateBitset = llvm::Bitset<MAX_SUBTARGET_PREDICATES>;
#endif // ifdef GET_GLOBALISEL_PREDICATE_BITSET

#ifdef GET_GLOBALISEL_TEMPORARIES_DECL
  mutable MatcherState State;
  typedef ComplexRendererFns(AMDGPUInstructionSelector::*ComplexMatcherMemFn)(MachineOperand &) const;
  typedef void(AMDGPUInstructionSelector::*CustomRendererFn)(MachineInstrBuilder &, const MachineInstr &, int) const;
  const ExecInfoTy<PredicateBitset, ComplexMatcherMemFn, CustomRendererFn> ExecInfo;
  static AMDGPUInstructionSelector::ComplexMatcherMemFn ComplexPredicateFns[];
  static AMDGPUInstructionSelector::CustomRendererFn CustomRenderers[];
  bool testImmPredicate_I64(unsigned PredicateID, int64_t Imm) const override;
  bool testImmPredicate_APInt(unsigned PredicateID, const APInt &Imm) const override;
  bool testImmPredicate_APFloat(unsigned PredicateID, const APFloat &Imm) const override;
  const uint8_t *getMatchTable() const override;
  bool testMIPredicate_MI(unsigned PredicateID, const MachineInstr &MI, const MatcherState &State) const override;
  bool testSimplePredicate(unsigned PredicateID) const override;
  void runCustomAction(unsigned FnID, const MatcherState &State, NewMIVector &OutMIs) const override;
#endif // ifdef GET_GLOBALISEL_TEMPORARIES_DECL

#ifdef GET_GLOBALISEL_TEMPORARIES_INIT
, State(6),
ExecInfo(TypeObjects, NumTypeObjects, FeatureBitsets, ComplexPredicateFns, CustomRenderers)
#endif // ifdef GET_GLOBALISEL_TEMPORARIES_INIT

#ifdef GET_GLOBALISEL_IMPL
// LLT Objects.
enum {
  GILLT_p0s64,
  GILLT_p1s64,
  GILLT_p2s32,
  GILLT_p3s32,
  GILLT_p4s64,
  GILLT_p5s32,
  GILLT_p6s32,
  GILLT_s1,
  GILLT_s16,
  GILLT_s32,
  GILLT_s64,
  GILLT_v2s16,
  GILLT_v2s32,
  GILLT_v2s64,
  GILLT_v3s32,
  GILLT_v3s64,
  GILLT_v4s16,
  GILLT_v4s32,
  GILLT_v4s64,
  GILLT_v5s32,
  GILLT_v6s32,
  GILLT_v7s32,
  GILLT_v8s16,
  GILLT_v8s32,
  GILLT_v8s64,
  GILLT_v9s32,
  GILLT_v10s32,
  GILLT_v11s32,
  GILLT_v12s32,
  GILLT_v16s16,
  GILLT_v16s32,
  GILLT_v16s64,
  GILLT_v32s16,
  GILLT_v32s32,
};
const static size_t NumTypeObjects = 34;
const static LLT TypeObjects[] = {
  LLT::pointer(0, 64),
  LLT::pointer(1, 64),
  LLT::pointer(2, 32),
  LLT::pointer(3, 32),
  LLT::pointer(4, 64),
  LLT::pointer(5, 32),
  LLT::pointer(6, 32),
  LLT::scalar(1),
  LLT::scalar(16),
  LLT::scalar(32),
  LLT::scalar(64),
  LLT::vector(ElementCount::getFixed(2), 16),
  LLT::vector(ElementCount::getFixed(2), 32),
  LLT::vector(ElementCount::getFixed(2), 64),
  LLT::vector(ElementCount::getFixed(3), 32),
  LLT::vector(ElementCount::getFixed(3), 64),
  LLT::vector(ElementCount::getFixed(4), 16),
  LLT::vector(ElementCount::getFixed(4), 32),
  LLT::vector(ElementCount::getFixed(4), 64),
  LLT::vector(ElementCount::getFixed(5), 32),
  LLT::vector(ElementCount::getFixed(6), 32),
  LLT::vector(ElementCount::getFixed(7), 32),
  LLT::vector(ElementCount::getFixed(8), 16),
  LLT::vector(ElementCount::getFixed(8), 32),
  LLT::vector(ElementCount::getFixed(8), 64),
  LLT::vector(ElementCount::getFixed(9), 32),
  LLT::vector(ElementCount::getFixed(10), 32),
  LLT::vector(ElementCount::getFixed(11), 32),
  LLT::vector(ElementCount::getFixed(12), 32),
  LLT::vector(ElementCount::getFixed(16), 16),
  LLT::vector(ElementCount::getFixed(16), 32),
  LLT::vector(ElementCount::getFixed(16), 64),
  LLT::vector(ElementCount::getFixed(32), 16),
  LLT::vector(ElementCount::getFixed(32), 32),
};

// Bits for subtarget features that participate in instruction matching.
enum SubtargetFeatureBits : uint8_t {
  Feature_isGFX6Bit = 39,
  Feature_isGFX6GFX7Bit = 6,
  Feature_isGFX6GFX7GFX10Bit = 88,
  Feature_isGFX6GFX7GFX10PlusBit = 87,
  Feature_isGFX7OnlyBit = 66,
  Feature_isGFX7GFX8GFX9Bit = 34,
  Feature_isGFX6GFX7GFX8GFX9Bit = 53,
  Feature_isGFX6GFX7GFX8GFX9GFX10Bit = 101,
  Feature_isNotGFX12PlusBit = 17,
  Feature_isGFX8GFX9GFX10GFX11Bit = 18,
  Feature_isGFX7PlusBit = 10,
  Feature_isGFX8PlusBit = 4,
  Feature_isGFX8OnlyBit = 19,
  Feature_isGFX9PlusBit = 0,
  Feature_isNotGFX9PlusBit = 45,
  Feature_isGFX9OnlyBit = 47,
  Feature_isGFX90APlusBit = 30,
  Feature_isNotGFX90APlusBit = 20,
  Feature_isGFX908orGFX90ABit = 29,
  Feature_isGFX940PlusBit = 31,
  Feature_isGFX8GFX9Bit = 13,
  Feature_isGFX10OnlyBit = 49,
  Feature_isGFX10PlusBit = 5,
  Feature_isGFX10GFX11Bit = 76,
  Feature_isGFX11OnlyBit = 50,
  Feature_isGFX11PlusBit = 1,
  Feature_isGFX12OnlyBit = 51,
  Feature_isGFX12PlusBit = 3,
  Feature_HasFlatAddressSpaceBit = 68,
  Feature_HasFlatGlobalInstsBit = 72,
  Feature_HasFlatScratchInstsBit = 74,
  Feature_HasD16LoadStoreBit = 70,
  Feature_HasFlatScratchSVSModeBit = 75,
  Feature_HasGFX10_BEncodingBit = 38,
  Feature_HasUnpackedD16VMemBit = 85,
  Feature_HasPackedD16VMemBit = 86,
  Feature_HasUnrestrictedSOffsetBit = 84,
  Feature_D16PreservesUnusedBitsBit = 71,
  Feature_LDSRequiresM0InitBit = 97,
  Feature_NotLDSRequiresM0InitBit = 98,
  Feature_HasLDSFPAtomicAddBit = 102,
  Feature_HasAddNoCarryInstsBit = 52,
  Feature_NotHasAddNoCarryInstsBit = 96,
  Feature_Has16BitInstsBit = 7,
  Feature_HasTrue16BitInstsBit = 9,
  Feature_NotHasTrue16BitInstsBit = 8,
  Feature_UseRealTrue16InstsBit = 11,
  Feature_UseFakeTrue16InstsBit = 12,
  Feature_HasVOP3PInstsBit = 61,
  Feature_HasMinMaxDenormModesBit = 90,
  Feature_NotHasMinMaxDenormModesBit = 92,
  Feature_HasPackedFP32OpsBit = 32,
  Feature_HasIntClampBit = 58,
  Feature_HasMadMixInstsBit = 62,
  Feature_HasScalarStoresBit = 35,
  Feature_has16BankLDSBit = 40,
  Feature_has32BankLDSBit = 21,
  Feature_HasFmaMixInstsBit = 64,
  Feature_HasDLInstsBit = 14,
  Feature_HasFmacF64InstBit = 95,
  Feature_HasDot1InstsBit = 27,
  Feature_HasDot2InstsBit = 24,
  Feature_HasDot3InstsBit = 57,
  Feature_HasDot4InstsBit = 56,
  Feature_HasDot5InstsBit = 54,
  Feature_HasDot6InstsBit = 55,
  Feature_HasDot7InstsBit = 26,
  Feature_HasDot8InstsBit = 65,
  Feature_HasDot9InstsBit = 22,
  Feature_HasDot10InstsBit = 25,
  Feature_HasGetWaveIdInstBit = 37,
  Feature_HasMAIInstsBit = 28,
  Feature_HasSMemRealTimeBit = 36,
  Feature_HasSMemTimeInstBit = 33,
  Feature_HasShaderCyclesRegisterBit = 67,
  Feature_HasShaderCyclesHiLoRegistersBit = 41,
  Feature_HasMadMacF32InstsBit = 15,
  Feature_HasFmaLegacy32Bit = 16,
  Feature_HasAtomicDsPkAdd16InstsBit = 103,
  Feature_HasAtomicFlatPkAdd16InstsBit = 82,
  Feature_HasAtomicFaddRtnInstsBit = 79,
  Feature_HasAtomicFaddNoRtnInstsBit = 77,
  Feature_HasAtomicBufferGlobalPkAddF16NoRtnInstsBit = 78,
  Feature_HasAtomicBufferGlobalPkAddF16InstsBit = 80,
  Feature_HasAtomicGlobalPkAddBF16InstBit = 83,
  Feature_HasFlatAtomicFaddF32InstBit = 81,
  Feature_EnableLateCFGStructurizeBit = 42,
  Feature_EnableFlatScratchBit = 73,
  Feature_DisableFlatScratchBit = 89,
  Feature_HasUnalignedAccessModeBit = 99,
  Feature_HasMADIntraFwdBugBit = 60,
  Feature_HasNotMADIntraFwdBugBit = 59,
  Feature_HasSALUFloatInstsBit = 2,
  Feature_HasPseudoScalarTransBit = 23,
  Feature_HasGDSBit = 100,
  Feature_HasCvtFP8VOP1BugBit = 46,
  Feature_HasNoCvtFP8VOP1BugBit = 48,
  Feature_HasAtomicCSubNoRtnInstsBit = 69,
  Feature_FalsePredicateBit = 91,
  Feature_FP16DenormalsBit = 94,
  Feature_FP64DenormalsBit = 93,
  Feature_NoFP32DenormalsBit = 63,
  Feature_isWave32Bit = 43,
  Feature_isWave64Bit = 44,
};

PredicateBitset AMDGPUInstructionSelector::
computeAvailableModuleFeatures(const AMDGPUSubtarget *Subtarget) const {
  PredicateBitset Features;
  if (Subtarget->getGeneration() == AMDGPUSubtarget::SOUTHERN_ISLANDS)
    Features.set(Feature_isGFX6Bit);
  if (Subtarget->getGeneration() == AMDGPUSubtarget::SOUTHERN_ISLANDS ||Subtarget->getGeneration() == AMDGPUSubtarget::SEA_ISLANDS)
    Features.set(Feature_isGFX6GFX7Bit);
  if (Subtarget->getGeneration() == AMDGPUSubtarget::SOUTHERN_ISLANDS ||Subtarget->getGeneration() == AMDGPUSubtarget::SEA_ISLANDS ||Subtarget->getGeneration() == AMDGPUSubtarget::GFX10)
    Features.set(Feature_isGFX6GFX7GFX10Bit);
  if (Subtarget->getGeneration() == AMDGPUSubtarget::SOUTHERN_ISLANDS ||Subtarget->getGeneration() == AMDGPUSubtarget::SEA_ISLANDS ||Subtarget->getGeneration() >= AMDGPUSubtarget::GFX10)
    Features.set(Feature_isGFX6GFX7GFX10PlusBit);
  if (Subtarget->getGeneration() == AMDGPUSubtarget::SEA_ISLANDS)
    Features.set(Feature_isGFX7OnlyBit);
  if (Subtarget->getGeneration() == AMDGPUSubtarget::SEA_ISLANDS ||Subtarget->getGeneration() == AMDGPUSubtarget::VOLCANIC_ISLANDS ||Subtarget->getGeneration() == AMDGPUSubtarget::GFX9)
    Features.set(Feature_isGFX7GFX8GFX9Bit);
  if (Subtarget->getGeneration() == AMDGPUSubtarget::SOUTHERN_ISLANDS ||Subtarget->getGeneration() == AMDGPUSubtarget::SEA_ISLANDS ||Subtarget->getGeneration() == AMDGPUSubtarget::VOLCANIC_ISLANDS ||Subtarget->getGeneration() == AMDGPUSubtarget::GFX9)
    Features.set(Feature_isGFX6GFX7GFX8GFX9Bit);
  if (Subtarget->getGeneration() == AMDGPUSubtarget::SOUTHERN_ISLANDS ||Subtarget->getGeneration() == AMDGPUSubtarget::SEA_ISLANDS ||Subtarget->getGeneration() == AMDGPUSubtarget::VOLCANIC_ISLANDS ||Subtarget->getGeneration() == AMDGPUSubtarget::GFX9 ||Subtarget->getGeneration() == AMDGPUSubtarget::GFX10)
    Features.set(Feature_isGFX6GFX7GFX8GFX9GFX10Bit);
  if (Subtarget->getGeneration() <= AMDGPUSubtarget::GFX11)
    Features.set(Feature_isNotGFX12PlusBit);
  if (Subtarget->getGeneration() == AMDGPUSubtarget::VOLCANIC_ISLANDS ||Subtarget->getGeneration() == AMDGPUSubtarget::GFX9 ||Subtarget->getGeneration() == AMDGPUSubtarget::GFX10 ||Subtarget->getGeneration() == AMDGPUSubtarget::GFX11)
    Features.set(Feature_isGFX8GFX9GFX10GFX11Bit);
  if (Subtarget->getGeneration() >= AMDGPUSubtarget::SEA_ISLANDS)
    Features.set(Feature_isGFX7PlusBit);
  if (Subtarget->getGeneration() >= AMDGPUSubtarget::VOLCANIC_ISLANDS)
    Features.set(Feature_isGFX8PlusBit);
  if (Subtarget->getGeneration() ==AMDGPUSubtarget::VOLCANIC_ISLANDS)
    Features.set(Feature_isGFX8OnlyBit);
  if (Subtarget->getGeneration() >= AMDGPUSubtarget::GFX9)
    Features.set(Feature_isGFX9PlusBit);
  if (Subtarget->getGeneration() < AMDGPUSubtarget::GFX9)
    Features.set(Feature_isNotGFX9PlusBit);
  if (Subtarget->getGeneration() == AMDGPUSubtarget::GFX9)
    Features.set(Feature_isGFX9OnlyBit);
  if (Subtarget->hasGFX90AInsts())
    Features.set(Feature_isGFX90APlusBit);
  if (!Subtarget->hasGFX90AInsts())
    Features.set(Feature_isNotGFX90APlusBit);
  if (Subtarget->hasMAIInsts() && !Subtarget->hasGFX940Insts())
    Features.set(Feature_isGFX908orGFX90ABit);
  if (Subtarget->hasGFX940Insts())
    Features.set(Feature_isGFX940PlusBit);
  if (Subtarget->getGeneration() == AMDGPUSubtarget::VOLCANIC_ISLANDS ||Subtarget->getGeneration() == AMDGPUSubtarget::GFX9)
    Features.set(Feature_isGFX8GFX9Bit);
  if (Subtarget->getGeneration() == AMDGPUSubtarget::GFX10)
    Features.set(Feature_isGFX10OnlyBit);
  if (Subtarget->getGeneration() >= AMDGPUSubtarget::GFX10)
    Features.set(Feature_isGFX10PlusBit);
  if (Subtarget->getGeneration() == AMDGPUSubtarget::GFX10 ||Subtarget->getGeneration() == AMDGPUSubtarget::GFX11)
    Features.set(Feature_isGFX10GFX11Bit);
  if (Subtarget->getGeneration() == AMDGPUSubtarget::GFX11)
    Features.set(Feature_isGFX11OnlyBit);
  if (Subtarget->getGeneration() >= AMDGPUSubtarget::GFX11)
    Features.set(Feature_isGFX11PlusBit);
  if (Subtarget->getGeneration() == AMDGPUSubtarget::GFX12)
    Features.set(Feature_isGFX12OnlyBit);
  if (Subtarget->getGeneration() >= AMDGPUSubtarget::GFX12)
    Features.set(Feature_isGFX12PlusBit);
  if (Subtarget->hasFlatAddressSpace())
    Features.set(Feature_HasFlatAddressSpaceBit);
  if (Subtarget->hasFlatGlobalInsts())
    Features.set(Feature_HasFlatGlobalInstsBit);
  if (Subtarget->hasFlatScratchInsts())
    Features.set(Feature_HasFlatScratchInstsBit);
  if (Subtarget->hasD16LoadStore())
    Features.set(Feature_HasD16LoadStoreBit);
  if (Subtarget->hasFlatScratchSVSMode())
    Features.set(Feature_HasFlatScratchSVSModeBit);
  if (Subtarget->hasGFX10_BEncoding())
    Features.set(Feature_HasGFX10_BEncodingBit);
  if (Subtarget->hasUnpackedD16VMem())
    Features.set(Feature_HasUnpackedD16VMemBit);
  if (!Subtarget->hasUnpackedD16VMem())
    Features.set(Feature_HasPackedD16VMemBit);
  if (!Subtarget->hasRestrictedSOffset())
    Features.set(Feature_HasUnrestrictedSOffsetBit);
  if (Subtarget->d16PreservesUnusedBits())
    Features.set(Feature_D16PreservesUnusedBitsBit);
  if (Subtarget->ldsRequiresM0Init())
    Features.set(Feature_LDSRequiresM0InitBit);
  if (!Subtarget->ldsRequiresM0Init())
    Features.set(Feature_NotLDSRequiresM0InitBit);
  if (Subtarget->hasLDSFPAtomicAdd())
    Features.set(Feature_HasLDSFPAtomicAddBit);
  if (Subtarget->hasAddNoCarry())
    Features.set(Feature_HasAddNoCarryInstsBit);
  if (!Subtarget->hasAddNoCarry())
    Features.set(Feature_NotHasAddNoCarryInstsBit);
  if (Subtarget->has16BitInsts())
    Features.set(Feature_Has16BitInstsBit);
  if (Subtarget->hasTrue16BitInsts())
    Features.set(Feature_HasTrue16BitInstsBit);
  if (!Subtarget->hasTrue16BitInsts())
    Features.set(Feature_NotHasTrue16BitInstsBit);
  if (Subtarget->useRealTrue16Insts())
    Features.set(Feature_UseRealTrue16InstsBit);
  if (Subtarget->hasTrue16BitInsts() && !Subtarget->useRealTrue16Insts())
    Features.set(Feature_UseFakeTrue16InstsBit);
  if (Subtarget->hasVOP3PInsts())
    Features.set(Feature_HasVOP3PInstsBit);
  if (Subtarget->supportsMinMaxDenormModes())
    Features.set(Feature_HasMinMaxDenormModesBit);
  if (!Subtarget->supportsMinMaxDenormModes())
    Features.set(Feature_NotHasMinMaxDenormModesBit);
  if (Subtarget->hasPackedFP32Ops())
    Features.set(Feature_HasPackedFP32OpsBit);
  if (Subtarget->hasIntClamp())
    Features.set(Feature_HasIntClampBit);
  if (Subtarget->hasMadMixInsts())
    Features.set(Feature_HasMadMixInstsBit);
  if (Subtarget->hasScalarStores())
    Features.set(Feature_HasScalarStoresBit);
  if (Subtarget->getLDSBankCount() == 16)
    Features.set(Feature_has16BankLDSBit);
  if (Subtarget->getLDSBankCount() == 32)
    Features.set(Feature_has32BankLDSBit);
  if (Subtarget->hasFmaMixInsts())
    Features.set(Feature_HasFmaMixInstsBit);
  if (Subtarget->hasDLInsts())
    Features.set(Feature_HasDLInstsBit);
  if (Subtarget->hasFmacF64Inst())
    Features.set(Feature_HasFmacF64InstBit);
  if (Subtarget->hasDot1Insts())
    Features.set(Feature_HasDot1InstsBit);
  if (Subtarget->hasDot2Insts())
    Features.set(Feature_HasDot2InstsBit);
  if (Subtarget->hasDot3Insts())
    Features.set(Feature_HasDot3InstsBit);
  if (Subtarget->hasDot4Insts())
    Features.set(Feature_HasDot4InstsBit);
  if (Subtarget->hasDot5Insts())
    Features.set(Feature_HasDot5InstsBit);
  if (Subtarget->hasDot6Insts())
    Features.set(Feature_HasDot6InstsBit);
  if (Subtarget->hasDot7Insts())
    Features.set(Feature_HasDot7InstsBit);
  if (Subtarget->hasDot8Insts())
    Features.set(Feature_HasDot8InstsBit);
  if (Subtarget->hasDot9Insts())
    Features.set(Feature_HasDot9InstsBit);
  if (Subtarget->hasDot10Insts())
    Features.set(Feature_HasDot10InstsBit);
  if (Subtarget->hasGetWaveIdInst())
    Features.set(Feature_HasGetWaveIdInstBit);
  if (Subtarget->hasMAIInsts())
    Features.set(Feature_HasMAIInstsBit);
  if (Subtarget->hasSMemRealTime())
    Features.set(Feature_HasSMemRealTimeBit);
  if (Subtarget->hasSMemTimeInst())
    Features.set(Feature_HasSMemTimeInstBit);
  if (Subtarget->hasShaderCyclesRegister())
    Features.set(Feature_HasShaderCyclesRegisterBit);
  if (Subtarget->hasShaderCyclesHiLoRegisters())
    Features.set(Feature_HasShaderCyclesHiLoRegistersBit);
  if (Subtarget->hasMadMacF32Insts())
    Features.set(Feature_HasMadMacF32InstsBit);
  if (Subtarget->hasGFX10_3Insts())
    Features.set(Feature_HasFmaLegacy32Bit);
  if (Subtarget->hasAtomicDsPkAdd16Insts())
    Features.set(Feature_HasAtomicDsPkAdd16InstsBit);
  if (Subtarget->hasAtomicFlatPkAdd16Insts())
    Features.set(Feature_HasAtomicFlatPkAdd16InstsBit);
  if (Subtarget->hasAtomicFaddRtnInsts())
    Features.set(Feature_HasAtomicFaddRtnInstsBit);
  if (Subtarget->hasAtomicFaddNoRtnInsts())
    Features.set(Feature_HasAtomicFaddNoRtnInstsBit);
  if (Subtarget->hasAtomicBufferGlobalPkAddF16NoRtnInsts() || Subtarget->hasAtomicBufferGlobalPkAddF16Insts())
    Features.set(Feature_HasAtomicBufferGlobalPkAddF16NoRtnInstsBit);
  if (Subtarget->hasAtomicBufferGlobalPkAddF16Insts())
    Features.set(Feature_HasAtomicBufferGlobalPkAddF16InstsBit);
  if (Subtarget->hasAtomicGlobalPkAddBF16Inst())
    Features.set(Feature_HasAtomicGlobalPkAddBF16InstBit);
  if (Subtarget->hasFlatAtomicFaddF32Inst())
    Features.set(Feature_HasFlatAtomicFaddF32InstBit);
  if (EnableLateStructurizeCFG)
    Features.set(Feature_EnableLateCFGStructurizeBit);
  if (Subtarget->enableFlatScratch())
    Features.set(Feature_EnableFlatScratchBit);
  if (!Subtarget->enableFlatScratch())
    Features.set(Feature_DisableFlatScratchBit);
  if (Subtarget->hasUnalignedAccessMode())
    Features.set(Feature_HasUnalignedAccessModeBit);
  if (Subtarget->hasMADIntraFwdBug())
    Features.set(Feature_HasMADIntraFwdBugBit);
  if (!Subtarget->hasMADIntraFwdBug())
    Features.set(Feature_HasNotMADIntraFwdBugBit);
  if (Subtarget->hasSALUFloatInsts())
    Features.set(Feature_HasSALUFloatInstsBit);
  if (Subtarget->hasPseudoScalarTrans())
    Features.set(Feature_HasPseudoScalarTransBit);
  if (Subtarget->hasGDS())
    Features.set(Feature_HasGDSBit);
  if (Subtarget->hasCvtFP8VOP1Bug())
    Features.set(Feature_HasCvtFP8VOP1BugBit);
  if (!Subtarget->hasCvtFP8VOP1Bug())
    Features.set(Feature_HasNoCvtFP8VOP1BugBit);
  if (Subtarget->hasAtomicCSubNoRtnInsts())
    Features.set(Feature_HasAtomicCSubNoRtnInstsBit);
  if (false)
    Features.set(Feature_FalsePredicateBit);
  if (Subtarget->getWavefrontSize() == 32)
    Features.set(Feature_isWave32Bit);
  if (Subtarget->getWavefrontSize() == 64)
    Features.set(Feature_isWave64Bit);
  return Features;
}

void AMDGPUInstructionSelector::setupGeneratedPerFunctionState(MachineFunction &MF) {
  AvailableFunctionFeatures = computeAvailableFunctionFeatures((const AMDGPUSubtarget *)&MF.getSubtarget(), &MF);
}
PredicateBitset AMDGPUInstructionSelector::
computeAvailableFunctionFeatures(const AMDGPUSubtarget *Subtarget, const MachineFunction *MF) const {
  PredicateBitset Features;
  if (MF->getInfo<SIMachineFunctionInfo>()->getMode().FP64FP16Denormals != DenormalMode::getPreserveSign())
    Features.set(Feature_FP16DenormalsBit);
  if (MF->getInfo<SIMachineFunctionInfo>()->getMode().FP64FP16Denormals != DenormalMode::getPreserveSign())
    Features.set(Feature_FP64DenormalsBit);
  if (MF->getInfo<SIMachineFunctionInfo>()->getMode().FP32Denormals == DenormalMode::getPreserveSign())
    Features.set(Feature_NoFP32DenormalsBit);
  return Features;
}

// Feature bitsets.
enum {
  GIFBS_Invalid,
  GIFBS_DisableFlatScratch,
  GIFBS_Has16BitInsts,
  GIFBS_HasAddNoCarryInsts,
  GIFBS_HasAtomicBufferGlobalPkAddF16Insts,
  GIFBS_HasAtomicBufferGlobalPkAddF16NoRtnInsts,
  GIFBS_HasAtomicCSubNoRtnInsts,
  GIFBS_HasAtomicDsPkAdd16Insts,
  GIFBS_HasAtomicFaddNoRtnInsts,
  GIFBS_HasAtomicFaddRtnInsts,
  GIFBS_HasAtomicFlatPkAdd16Insts,
  GIFBS_HasAtomicGlobalPkAddBF16Inst,
  GIFBS_HasD16LoadStore,
  GIFBS_HasDLInsts,
  GIFBS_HasDot10Insts,
  GIFBS_HasDot1Insts,
  GIFBS_HasDot2Insts,
  GIFBS_HasDot3Insts,
  GIFBS_HasDot4Insts,
  GIFBS_HasDot5Insts,
  GIFBS_HasDot6Insts,
  GIFBS_HasDot7Insts,
  GIFBS_HasDot8Insts,
  GIFBS_HasDot9Insts,
  GIFBS_HasFlatAddressSpace,
  GIFBS_HasFlatAtomicFaddF32Inst,
  GIFBS_HasFlatGlobalInsts,
  GIFBS_HasFmaLegacy32,
  GIFBS_HasFmaMixInsts,
  GIFBS_HasFmacF64Inst,
  GIFBS_HasGDS,
  GIFBS_HasGFX10_BEncoding,
  GIFBS_HasGetWaveIdInst,
  GIFBS_HasIntClamp,
  GIFBS_HasMAIInsts,
  GIFBS_HasMadMacF32Insts,
  GIFBS_HasMinMaxDenormModes,
  GIFBS_HasPackedD16VMem,
  GIFBS_HasPackedFP32Ops,
  GIFBS_HasPseudoScalarTrans,
  GIFBS_HasSALUFloatInsts,
  GIFBS_HasSMemRealTime,
  GIFBS_HasSMemTimeInst,
  GIFBS_HasShaderCyclesHiLoRegisters,
  GIFBS_HasShaderCyclesRegister,
  GIFBS_HasTrue16BitInsts,
  GIFBS_HasUnpackedD16VMem,
  GIFBS_HasUnrestrictedSOffset,
  GIFBS_HasVOP3PInsts,
  GIFBS_LDSRequiresM0Init,
  GIFBS_NotHasAddNoCarryInsts,
  GIFBS_NotHasTrue16BitInsts,
  GIFBS_NotLDSRequiresM0Init,
  GIFBS_UseFakeTrue16Insts,
  GIFBS_UseRealTrue16Insts,
  GIFBS_isGFX10GFX11,
  GIFBS_isGFX10Only,
  GIFBS_isGFX10Plus,
  GIFBS_isGFX11Only,
  GIFBS_isGFX11Plus,
  GIFBS_isGFX12Only,
  GIFBS_isGFX12Plus,
  GIFBS_isGFX6,
  GIFBS_isGFX6GFX7,
  GIFBS_isGFX6GFX7GFX10,
  GIFBS_isGFX6GFX7GFX10Plus,
  GIFBS_isGFX6GFX7GFX8GFX9,
  GIFBS_isGFX7GFX8GFX9,
  GIFBS_isGFX7Only,
  GIFBS_isGFX7Plus,
  GIFBS_isGFX8GFX9,
  GIFBS_isGFX8GFX9GFX10GFX11,
  GIFBS_isGFX8Plus,
  GIFBS_isGFX908orGFX90A,
  GIFBS_isGFX90APlus,
  GIFBS_isGFX940Plus,
  GIFBS_isGFX9Only,
  GIFBS_isGFX9Plus,
  GIFBS_isNotGFX12Plus,
  GIFBS_isNotGFX90APlus,
  GIFBS_isNotGFX9Plus,
  GIFBS_isWave32,
  GIFBS_isWave64,
  GIFBS_DisableFlatScratch_HasD16LoadStore,
  GIFBS_DisableFlatScratch_HasUnrestrictedSOffset,
  GIFBS_EnableFlatScratch_HasFlatScratchInsts,
  GIFBS_FP16Denormals_NotHasMinMaxDenormModes,
  GIFBS_FalsePredicate_NotHasMinMaxDenormModes,
  GIFBS_Has16BitInsts_HasIntClamp,
  GIFBS_Has16BitInsts_HasTrue16BitInsts,
  GIFBS_Has16BitInsts_HasUnrestrictedSOffset,
  GIFBS_Has16BitInsts_NotHasTrue16BitInsts,
  GIFBS_Has16BitInsts_isGFX6GFX7GFX8GFX9,
  GIFBS_Has16BitInsts_isGFX8GFX9,
  GIFBS_Has16BitInsts_isGFX8Only,
  GIFBS_Has16BitInsts_isNotGFX90APlus,
  GIFBS_HasAddNoCarryInsts_HasIntClamp,
  GIFBS_HasAtomicBufferGlobalPkAddF16Insts_isGFX12Plus,
  GIFBS_HasAtomicBufferGlobalPkAddF16Insts_isGFX9Only,
  GIFBS_HasAtomicBufferGlobalPkAddF16NoRtnInsts_isGFX12Plus,
  GIFBS_HasAtomicBufferGlobalPkAddF16NoRtnInsts_isGFX9Only,
  GIFBS_HasAtomicCSubNoRtnInsts_isGFX12Plus,
  GIFBS_HasAtomicFaddNoRtnInsts_HasUnrestrictedSOffset,
  GIFBS_HasAtomicFaddRtnInsts_HasUnrestrictedSOffset,
  GIFBS_HasCvtFP8VOP1Bug_isGFX9Only,
  GIFBS_HasFlatAddressSpace_isGFX12Plus,
  GIFBS_HasFlatGlobalInsts_isGFX12Plus,
  GIFBS_HasGDS_HasLDSFPAtomicAdd,
  GIFBS_HasGDS_isGFX11Plus,
  GIFBS_HasGDS_isGFX6GFX7GFX8GFX9GFX10,
  GIFBS_HasLDSFPAtomicAdd_LDSRequiresM0Init,
  GIFBS_HasLDSFPAtomicAdd_NotLDSRequiresM0Init,
  GIFBS_HasMadMacF32Insts_NoFP32Denormals,
  GIFBS_HasMadMixInsts_NoFP32Denormals,
  GIFBS_HasMinMaxDenormModes_isGFX12Plus,
  GIFBS_HasMinMaxDenormModes_isNotGFX12Plus,
  GIFBS_HasNoCvtFP8VOP1Bug_isGFX9Only,
  GIFBS_HasPackedD16VMem_HasUnrestrictedSOffset,
  GIFBS_HasScalarStores_isGFX8Plus,
  GIFBS_HasTrue16BitInsts_isGFX10Plus,
  GIFBS_HasUnalignedAccessMode_LDSRequiresM0Init,
  GIFBS_HasUnalignedAccessMode_NotLDSRequiresM0Init,
  GIFBS_HasUnrestrictedSOffset_isGFX90APlus,
  GIFBS_LDSRequiresM0Init_isGFX6GFX7GFX8GFX9GFX10,
  GIFBS_LDSRequiresM0Init_isGFX7Plus,
  GIFBS_NotHasTrue16BitInsts_isGFX10Plus,
  GIFBS_NotLDSRequiresM0Init_isGFX6GFX7GFX8GFX9GFX10,
  GIFBS_NotLDSRequiresM0Init_isGFX7Plus,
  GIFBS_has16BankLDS_isNotGFX90APlus,
  GIFBS_has32BankLDS_isNotGFX90APlus,
  GIFBS_isGFX11Only_isWave32,
  GIFBS_isGFX11Only_isWave64,
  GIFBS_isGFX12Plus_isWave32,
  GIFBS_isGFX12Plus_isWave64,
  GIFBS_DisableFlatScratch_HasD16LoadStore_HasUnrestrictedSOffset,
  GIFBS_EnableFlatScratch_HasD16LoadStore_HasFlatScratchInsts,
  GIFBS_EnableFlatScratch_HasFlatScratchInsts_HasFlatScratchSVSMode,
  GIFBS_FP64Denormals_NotHasMinMaxDenormModes_isGFX12Plus,
  GIFBS_FP64Denormals_NotHasMinMaxDenormModes_isNotGFX12Plus,
  GIFBS_Has16BitInsts_HasMinMaxDenormModes_HasTrue16BitInsts,
  GIFBS_Has16BitInsts_HasMinMaxDenormModes_NotHasTrue16BitInsts,
  GIFBS_Has16BitInsts_has32BankLDS_isNotGFX90APlus,
  GIFBS_HasMadMacF32Insts_NoFP32Denormals_isGFX6GFX7GFX10,
  GIFBS_EnableFlatScratch_HasD16LoadStore_HasFlatScratchInsts_HasFlatScratchSVSMode,
  GIFBS_FP16Denormals_Has16BitInsts_HasTrue16BitInsts_NotHasMinMaxDenormModes,
  GIFBS_FP16Denormals_Has16BitInsts_NotHasMinMaxDenormModes_NotHasTrue16BitInsts,
};
constexpr static PredicateBitset FeatureBitsets[] {
  {}, // GIFBS_Invalid
  {Feature_DisableFlatScratchBit, },
  {Feature_Has16BitInstsBit, },
  {Feature_HasAddNoCarryInstsBit, },
  {Feature_HasAtomicBufferGlobalPkAddF16InstsBit, },
  {Feature_HasAtomicBufferGlobalPkAddF16NoRtnInstsBit, },
  {Feature_HasAtomicCSubNoRtnInstsBit, },
  {Feature_HasAtomicDsPkAdd16InstsBit, },
  {Feature_HasAtomicFaddNoRtnInstsBit, },
  {Feature_HasAtomicFaddRtnInstsBit, },
  {Feature_HasAtomicFlatPkAdd16InstsBit, },
  {Feature_HasAtomicGlobalPkAddBF16InstBit, },
  {Feature_HasD16LoadStoreBit, },
  {Feature_HasDLInstsBit, },
  {Feature_HasDot10InstsBit, },
  {Feature_HasDot1InstsBit, },
  {Feature_HasDot2InstsBit, },
  {Feature_HasDot3InstsBit, },
  {Feature_HasDot4InstsBit, },
  {Feature_HasDot5InstsBit, },
  {Feature_HasDot6InstsBit, },
  {Feature_HasDot7InstsBit, },
  {Feature_HasDot8InstsBit, },
  {Feature_HasDot9InstsBit, },
  {Feature_HasFlatAddressSpaceBit, },
  {Feature_HasFlatAtomicFaddF32InstBit, },
  {Feature_HasFlatGlobalInstsBit, },
  {Feature_HasFmaLegacy32Bit, },
  {Feature_HasFmaMixInstsBit, },
  {Feature_HasFmacF64InstBit, },
  {Feature_HasGDSBit, },
  {Feature_HasGFX10_BEncodingBit, },
  {Feature_HasGetWaveIdInstBit, },
  {Feature_HasIntClampBit, },
  {Feature_HasMAIInstsBit, },
  {Feature_HasMadMacF32InstsBit, },
  {Feature_HasMinMaxDenormModesBit, },
  {Feature_HasPackedD16VMemBit, },
  {Feature_HasPackedFP32OpsBit, },
  {Feature_HasPseudoScalarTransBit, },
  {Feature_HasSALUFloatInstsBit, },
  {Feature_HasSMemRealTimeBit, },
  {Feature_HasSMemTimeInstBit, },
  {Feature_HasShaderCyclesHiLoRegistersBit, },
  {Feature_HasShaderCyclesRegisterBit, },
  {Feature_HasTrue16BitInstsBit, },
  {Feature_HasUnpackedD16VMemBit, },
  {Feature_HasUnrestrictedSOffsetBit, },
  {Feature_HasVOP3PInstsBit, },
  {Feature_LDSRequiresM0InitBit, },
  {Feature_NotHasAddNoCarryInstsBit, },
  {Feature_NotHasTrue16BitInstsBit, },
  {Feature_NotLDSRequiresM0InitBit, },
  {Feature_UseFakeTrue16InstsBit, },
  {Feature_UseRealTrue16InstsBit, },
  {Feature_isGFX10GFX11Bit, },
  {Feature_isGFX10OnlyBit, },
  {Feature_isGFX10PlusBit, },
  {Feature_isGFX11OnlyBit, },
  {Feature_isGFX11PlusBit, },
  {Feature_isGFX12OnlyBit, },
  {Feature_isGFX12PlusBit, },
  {Feature_isGFX6Bit, },
  {Feature_isGFX6GFX7Bit, },
  {Feature_isGFX6GFX7GFX10Bit, },
  {Feature_isGFX6GFX7GFX10PlusBit, },
  {Feature_isGFX6GFX7GFX8GFX9Bit, },
  {Feature_isGFX7GFX8GFX9Bit, },
  {Feature_isGFX7OnlyBit, },
  {Feature_isGFX7PlusBit, },
  {Feature_isGFX8GFX9Bit, },
  {Feature_isGFX8GFX9GFX10GFX11Bit, },
  {Feature_isGFX8PlusBit, },
  {Feature_isGFX908orGFX90ABit, },
  {Feature_isGFX90APlusBit, },
  {Feature_isGFX940PlusBit, },
  {Feature_isGFX9OnlyBit, },
  {Feature_isGFX9PlusBit, },
  {Feature_isNotGFX12PlusBit, },
  {Feature_isNotGFX90APlusBit, },
  {Feature_isNotGFX9PlusBit, },
  {Feature_isWave32Bit, },
  {Feature_isWave64Bit, },
  {Feature_DisableFlatScratchBit, Feature_HasD16LoadStoreBit, },
  {Feature_DisableFlatScratchBit, Feature_HasUnrestrictedSOffsetBit, },
  {Feature_EnableFlatScratchBit, Feature_HasFlatScratchInstsBit, },
  {Feature_FP16DenormalsBit, Feature_NotHasMinMaxDenormModesBit, },
  {Feature_FalsePredicateBit, Feature_NotHasMinMaxDenormModesBit, },
  {Feature_Has16BitInstsBit, Feature_HasIntClampBit, },
  {Feature_Has16BitInstsBit, Feature_HasTrue16BitInstsBit, },
  {Feature_Has16BitInstsBit, Feature_HasUnrestrictedSOffsetBit, },
  {Feature_Has16BitInstsBit, Feature_NotHasTrue16BitInstsBit, },
  {Feature_Has16BitInstsBit, Feature_isGFX6GFX7GFX8GFX9Bit, },
  {Feature_Has16BitInstsBit, Feature_isGFX8GFX9Bit, },
  {Feature_Has16BitInstsBit, Feature_isGFX8OnlyBit, },
  {Feature_Has16BitInstsBit, Feature_isNotGFX90APlusBit, },
  {Feature_HasAddNoCarryInstsBit, Feature_HasIntClampBit, },
  {Feature_HasAtomicBufferGlobalPkAddF16InstsBit, Feature_isGFX12PlusBit, },
  {Feature_HasAtomicBufferGlobalPkAddF16InstsBit, Feature_isGFX9OnlyBit, },
  {Feature_HasAtomicBufferGlobalPkAddF16NoRtnInstsBit, Feature_isGFX12PlusBit, },
  {Feature_HasAtomicBufferGlobalPkAddF16NoRtnInstsBit, Feature_isGFX9OnlyBit, },
  {Feature_HasAtomicCSubNoRtnInstsBit, Feature_isGFX12PlusBit, },
  {Feature_HasAtomicFaddNoRtnInstsBit, Feature_HasUnrestrictedSOffsetBit, },
  {Feature_HasAtomicFaddRtnInstsBit, Feature_HasUnrestrictedSOffsetBit, },
  {Feature_HasCvtFP8VOP1BugBit, Feature_isGFX9OnlyBit, },
  {Feature_HasFlatAddressSpaceBit, Feature_isGFX12PlusBit, },
  {Feature_HasFlatGlobalInstsBit, Feature_isGFX12PlusBit, },
  {Feature_HasGDSBit, Feature_HasLDSFPAtomicAddBit, },
  {Feature_HasGDSBit, Feature_isGFX11PlusBit, },
  {Feature_HasGDSBit, Feature_isGFX6GFX7GFX8GFX9GFX10Bit, },
  {Feature_HasLDSFPAtomicAddBit, Feature_LDSRequiresM0InitBit, },
  {Feature_HasLDSFPAtomicAddBit, Feature_NotLDSRequiresM0InitBit, },
  {Feature_HasMadMacF32InstsBit, Feature_NoFP32DenormalsBit, },
  {Feature_HasMadMixInstsBit, Feature_NoFP32DenormalsBit, },
  {Feature_HasMinMaxDenormModesBit, Feature_isGFX12PlusBit, },
  {Feature_HasMinMaxDenormModesBit, Feature_isNotGFX12PlusBit, },
  {Feature_HasNoCvtFP8VOP1BugBit, Feature_isGFX9OnlyBit, },
  {Feature_HasPackedD16VMemBit, Feature_HasUnrestrictedSOffsetBit, },
  {Feature_HasScalarStoresBit, Feature_isGFX8PlusBit, },
  {Feature_HasTrue16BitInstsBit, Feature_isGFX10PlusBit, },
  {Feature_HasUnalignedAccessModeBit, Feature_LDSRequiresM0InitBit, },
  {Feature_HasUnalignedAccessModeBit, Feature_NotLDSRequiresM0InitBit, },
  {Feature_HasUnrestrictedSOffsetBit, Feature_isGFX90APlusBit, },
  {Feature_LDSRequiresM0InitBit, Feature_isGFX6GFX7GFX8GFX9GFX10Bit, },
  {Feature_LDSRequiresM0InitBit, Feature_isGFX7PlusBit, },
  {Feature_NotHasTrue16BitInstsBit, Feature_isGFX10PlusBit, },
  {Feature_NotLDSRequiresM0InitBit, Feature_isGFX6GFX7GFX8GFX9GFX10Bit, },
  {Feature_NotLDSRequiresM0InitBit, Feature_isGFX7PlusBit, },
  {Feature_has16BankLDSBit, Feature_isNotGFX90APlusBit, },
  {Feature_has32BankLDSBit, Feature_isNotGFX90APlusBit, },
  {Feature_isGFX11OnlyBit, Feature_isWave32Bit, },
  {Feature_isGFX11OnlyBit, Feature_isWave64Bit, },
  {Feature_isGFX12PlusBit, Feature_isWave32Bit, },
  {Feature_isGFX12PlusBit, Feature_isWave64Bit, },
  {Feature_DisableFlatScratchBit, Feature_HasD16LoadStoreBit, Feature_HasUnrestrictedSOffsetBit, },
  {Feature_EnableFlatScratchBit, Feature_HasD16LoadStoreBit, Feature_HasFlatScratchInstsBit, },
  {Feature_EnableFlatScratchBit, Feature_HasFlatScratchInstsBit, Feature_HasFlatScratchSVSModeBit, },
  {Feature_FP64DenormalsBit, Feature_NotHasMinMaxDenormModesBit, Feature_isGFX12PlusBit, },
  {Feature_FP64DenormalsBit, Feature_NotHasMinMaxDenormModesBit, Feature_isNotGFX12PlusBit, },
  {Feature_Has16BitInstsBit, Feature_HasMinMaxDenormModesBit, Feature_HasTrue16BitInstsBit, },
  {Feature_Has16BitInstsBit, Feature_HasMinMaxDenormModesBit, Feature_NotHasTrue16BitInstsBit, },
  {Feature_Has16BitInstsBit, Feature_has32BankLDSBit, Feature_isNotGFX90APlusBit, },
  {Feature_HasMadMacF32InstsBit, Feature_NoFP32DenormalsBit, Feature_isGFX6GFX7GFX10Bit, },
  {Feature_EnableFlatScratchBit, Feature_HasD16LoadStoreBit, Feature_HasFlatScratchInstsBit, Feature_HasFlatScratchSVSModeBit, },
  {Feature_FP16DenormalsBit, Feature_Has16BitInstsBit, Feature_HasTrue16BitInstsBit, Feature_NotHasMinMaxDenormModesBit, },
  {Feature_FP16DenormalsBit, Feature_Has16BitInstsBit, Feature_NotHasMinMaxDenormModesBit, Feature_NotHasTrue16BitInstsBit, },
};

// ComplexPattern predicates.
enum {
  GICP_Invalid,
  GICP_gi_buf_soffset,
  GICP_gi_ds_128bit_8byte_aligned,
  GICP_gi_ds_1addr_1offset,
  GICP_gi_ds_64bit_4byte_aligned,
  GICP_gi_flat_offset,
  GICP_gi_flat_scratch_offset,
  GICP_gi_flat_scratch_saddr,
  GICP_gi_flat_scratch_svaddr,
  GICP_gi_global_offset,
  GICP_gi_global_saddr,
  GICP_gi_mubuf_addr64,
  GICP_gi_mubuf_offset,
  GICP_gi_mubuf_scratch_offen,
  GICP_gi_mubuf_scratch_offset,
  GICP_gi_smrd_buffer_imm,
  GICP_gi_smrd_buffer_imm32,
  GICP_gi_smrd_buffer_sgpr_imm,
  GICP_gi_smrd_imm,
  GICP_gi_smrd_imm32,
  GICP_gi_smrd_sgpr,
  GICP_gi_smrd_sgpr_imm,
  GICP_gi_swmmacindex16,
  GICP_gi_swmmacindex8,
  GICP_gi_vcsrc,
  GICP_gi_vinterpmods,
  GICP_gi_vinterpmods_hi,
  GICP_gi_vop3_mad_mix_mods,
  GICP_gi_vop3_mad_mix_mods_ext,
  GICP_gi_vop3_no_mods,
  GICP_gi_vop3mods,
  GICP_gi_vop3mods0,
  GICP_gi_vop3modsnoncanonicalizing,
  GICP_gi_vop3omods,
  GICP_gi_vop3opsel,
  GICP_gi_vop3opselmods,
  GICP_gi_vop3pmods,
  GICP_gi_vop3pmodsdot,
  GICP_gi_vop3pmodsneg,
  GICP_gi_vsrc0,
  GICP_gi_wmmamods,
  GICP_gi_wmmamodsf16Neg,
  GICP_gi_wmmamodsf16NegAbs,
  GICP_gi_wmmaopselvop3pmods,
  GICP_gi_wmmavisrc,
};
// See constructor for table contents

AMDGPUInstructionSelector::ComplexMatcherMemFn
AMDGPUInstructionSelector::ComplexPredicateFns[] = {
  nullptr, // GICP_Invalid
  &AMDGPUInstructionSelector::selectBUFSOffset, // gi_buf_soffset
  &AMDGPUInstructionSelector::selectDS128Bit8ByteAligned, // gi_ds_128bit_8byte_aligned
  &AMDGPUInstructionSelector::selectDS1Addr1Offset, // gi_ds_1addr_1offset
  &AMDGPUInstructionSelector::selectDS64Bit4ByteAligned, // gi_ds_64bit_4byte_aligned
  &AMDGPUInstructionSelector::selectFlatOffset, // gi_flat_offset
  &AMDGPUInstructionSelector::selectScratchOffset, // gi_flat_scratch_offset
  &AMDGPUInstructionSelector::selectScratchSAddr, // gi_flat_scratch_saddr
  &AMDGPUInstructionSelector::selectScratchSVAddr, // gi_flat_scratch_svaddr
  &AMDGPUInstructionSelector::selectGlobalOffset, // gi_global_offset
  &AMDGPUInstructionSelector::selectGlobalSAddr, // gi_global_saddr
  &AMDGPUInstructionSelector::selectMUBUFAddr64, // gi_mubuf_addr64
  &AMDGPUInstructionSelector::selectMUBUFOffset, // gi_mubuf_offset
  &AMDGPUInstructionSelector::selectMUBUFScratchOffen, // gi_mubuf_scratch_offen
  &AMDGPUInstructionSelector::selectMUBUFScratchOffset, // gi_mubuf_scratch_offset
  &AMDGPUInstructionSelector::selectSMRDBufferImm, // gi_smrd_buffer_imm
  &AMDGPUInstructionSelector::selectSMRDBufferImm32, // gi_smrd_buffer_imm32
  &AMDGPUInstructionSelector::selectSMRDBufferSgprImm, // gi_smrd_buffer_sgpr_imm
  &AMDGPUInstructionSelector::selectSmrdImm, // gi_smrd_imm
  &AMDGPUInstructionSelector::selectSmrdImm32, // gi_smrd_imm32
  &AMDGPUInstructionSelector::selectSmrdSgpr, // gi_smrd_sgpr
  &AMDGPUInstructionSelector::selectSmrdSgprImm, // gi_smrd_sgpr_imm
  &AMDGPUInstructionSelector::selectSWMMACIndex16, // gi_swmmacindex16
  &AMDGPUInstructionSelector::selectSWMMACIndex8, // gi_swmmacindex8
  &AMDGPUInstructionSelector::selectVCSRC, // gi_vcsrc
  &AMDGPUInstructionSelector::selectVINTERPMods, // gi_vinterpmods
  &AMDGPUInstructionSelector::selectVINTERPModsHi, // gi_vinterpmods_hi
  &AMDGPUInstructionSelector::selectVOP3PMadMixMods, // gi_vop3_mad_mix_mods
  &AMDGPUInstructionSelector::selectVOP3PMadMixModsExt, // gi_vop3_mad_mix_mods_ext
  &AMDGPUInstructionSelector::selectVOP3NoMods, // gi_vop3_no_mods
  &AMDGPUInstructionSelector::selectVOP3Mods, // gi_vop3mods
  &AMDGPUInstructionSelector::selectVOP3Mods0, // gi_vop3mods0
  &AMDGPUInstructionSelector::selectVOP3ModsNonCanonicalizing, // gi_vop3modsnoncanonicalizing
  &AMDGPUInstructionSelector::selectVOP3OMods, // gi_vop3omods
  &AMDGPUInstructionSelector::selectVOP3OpSelMods, // gi_vop3opsel
  &AMDGPUInstructionSelector::selectVOP3OpSelMods, // gi_vop3opselmods
  &AMDGPUInstructionSelector::selectVOP3PMods, // gi_vop3pmods
  &AMDGPUInstructionSelector::selectVOP3PModsDOT, // gi_vop3pmodsdot
  &AMDGPUInstructionSelector::selectVOP3PModsNeg, // gi_vop3pmodsneg
  &AMDGPUInstructionSelector::selectVSRC0, // gi_vsrc0
  &AMDGPUInstructionSelector::selectWMMAModsF32NegAbs, // gi_wmmamods
  &AMDGPUInstructionSelector::selectWMMAModsF16Neg, // gi_wmmamodsf16Neg
  &AMDGPUInstructionSelector::selectWMMAModsF16NegAbs, // gi_wmmamodsf16NegAbs
  &AMDGPUInstructionSelector::selectWMMAOpSelVOP3PMods, // gi_wmmaopselvop3pmods
  &AMDGPUInstructionSelector::selectWMMAVISrc, // gi_wmmavisrc
};

// PatFrag predicates.
enum {
  GICXXPred_MI_Predicate_AMDGPUmul_i24_oneuse = GICXXPred_Invalid + 1,
  GICXXPred_MI_Predicate_AMDGPUmul_u24_oneuse,
  GICXXPred_MI_Predicate_NonACAMDGPUmul_i24_oneuse,
  GICXXPred_MI_Predicate_NonACAMDGPUmul_u24_oneuse,
  GICXXPred_MI_Predicate_NonACAdd_oneuse,
  GICXXPred_MI_Predicate_add_oneuse,
  GICXXPred_MI_Predicate_and_oneuse,
  GICXXPred_MI_Predicate_anonymous_17562,
  GICXXPred_MI_Predicate_anonymous_17567,
  GICXXPred_MI_Predicate_anonymous_17568,
  GICXXPred_MI_Predicate_anonymous_17569,
  GICXXPred_MI_Predicate_anonymous_17570,
  GICXXPred_MI_Predicate_anonymous_17571,
  GICXXPred_MI_Predicate_anonymous_17577,
  GICXXPred_MI_Predicate_anonymous_17590,
  GICXXPred_MI_Predicate_anonymous_17594,
  GICXXPred_MI_Predicate_anonymous_17595,
  GICXXPred_MI_Predicate_anonymous_17596,
  GICXXPred_MI_Predicate_anonymous_17597,
  GICXXPred_MI_Predicate_anonymous_17598,
  GICXXPred_MI_Predicate_anonymous_17599,
  GICXXPred_MI_Predicate_anonymous_17600,
  GICXXPred_MI_Predicate_anonymous_17601,
  GICXXPred_MI_Predicate_anonymous_17602,
  GICXXPred_MI_Predicate_anonymous_17603,
  GICXXPred_MI_Predicate_anonymous_17604,
  GICXXPred_MI_Predicate_anonymous_17605,
  GICXXPred_MI_Predicate_anonymous_17606,
  GICXXPred_MI_Predicate_anonymous_17607,
  GICXXPred_MI_Predicate_anonymous_17608,
  GICXXPred_MI_Predicate_anonymous_17609,
  GICXXPred_MI_Predicate_anonymous_17610,
  GICXXPred_MI_Predicate_anonymous_17614,
  GICXXPred_MI_Predicate_anonymous_17615,
  GICXXPred_MI_Predicate_anonymous_17616,
  GICXXPred_MI_Predicate_anonymous_17617,
  GICXXPred_MI_Predicate_anonymous_17618,
  GICXXPred_MI_Predicate_anonymous_17619,
  GICXXPred_MI_Predicate_anonymous_17620,
  GICXXPred_MI_Predicate_anonymous_17621,
  GICXXPred_MI_Predicate_anonymous_17622,
  GICXXPred_MI_Predicate_anonymous_17623,
  GICXXPred_MI_Predicate_anonymous_17624,
  GICXXPred_MI_Predicate_anonymous_17628,
  GICXXPred_MI_Predicate_anonymous_17629,
  GICXXPred_MI_Predicate_anonymous_17630,
  GICXXPred_MI_Predicate_anonymous_17631,
  GICXXPred_MI_Predicate_anonymous_17632,
  GICXXPred_MI_Predicate_anonymous_17633,
  GICXXPred_MI_Predicate_anonymous_17634,
  GICXXPred_MI_Predicate_anonymous_17635,
  GICXXPred_MI_Predicate_anonymous_17636,
  GICXXPred_MI_Predicate_anonymous_17637,
  GICXXPred_MI_Predicate_anonymous_17638,
  GICXXPred_MI_Predicate_anonymous_17642,
  GICXXPred_MI_Predicate_anonymous_17658,
  GICXXPred_MI_Predicate_anonymous_17677,
  GICXXPred_MI_Predicate_anonymous_17683,
  GICXXPred_MI_Predicate_anonymous_21180,
  GICXXPred_MI_Predicate_anonymous_22539,
  GICXXPred_MI_Predicate_anonymous_22541,
  GICXXPred_MI_Predicate_anonymous_22543,
  GICXXPred_MI_Predicate_anonymous_22545,
  GICXXPred_MI_Predicate_anonymous_22547,
  GICXXPred_MI_Predicate_anonymous_22551,
  GICXXPred_MI_Predicate_anonymous_22553,
  GICXXPred_MI_Predicate_anonymous_22555,
  GICXXPred_MI_Predicate_anonymous_22557,
  GICXXPred_MI_Predicate_anonymous_22559,
  GICXXPred_MI_Predicate_anonymous_22759,
  GICXXPred_MI_Predicate_anonymous_22761,
  GICXXPred_MI_Predicate_anonymous_23209,
  GICXXPred_MI_Predicate_anonymous_23219,
  GICXXPred_MI_Predicate_anonymous_23222,
  GICXXPred_MI_Predicate_anonymous_23313,
  GICXXPred_MI_Predicate_anonymous_23602,
  GICXXPred_MI_Predicate_anonymous_23603,
  GICXXPred_MI_Predicate_anonymous_23605,
  GICXXPred_MI_Predicate_anonymous_23606,
  GICXXPred_MI_Predicate_anonymous_23608,
  GICXXPred_MI_Predicate_anonymous_23610,
  GICXXPred_MI_Predicate_anonymous_23611,
  GICXXPred_MI_Predicate_anonymous_23613,
  GICXXPred_MI_Predicate_anonymous_23615,
  GICXXPred_MI_Predicate_anonymous_23616,
  GICXXPred_MI_Predicate_anonymous_23618,
  GICXXPred_MI_Predicate_anonymous_23619,
  GICXXPred_MI_Predicate_anonymous_23621,
  GICXXPred_MI_Predicate_anonymous_23622,
  GICXXPred_MI_Predicate_anonymous_23625,
  GICXXPred_MI_Predicate_anonymous_23626,
  GICXXPred_MI_Predicate_anonymous_23633,
  GICXXPred_MI_Predicate_anonymous_23634,
  GICXXPred_MI_Predicate_anonymous_23670,
  GICXXPred_MI_Predicate_anonymous_23764,
  GICXXPred_MI_Predicate_anonymous_23770,
  GICXXPred_MI_Predicate_anonymous_23772,
  GICXXPred_MI_Predicate_anonymous_23774,
  GICXXPred_MI_Predicate_anonymous_23776,
  GICXXPred_MI_Predicate_anonymous_23778,
  GICXXPred_MI_Predicate_anonymous_23780,
  GICXXPred_MI_Predicate_anonymous_24726,
  GICXXPred_MI_Predicate_anonymous_24728,
  GICXXPred_MI_Predicate_anonymous_24732,
  GICXXPred_MI_Predicate_anonymous_24734,
  GICXXPred_MI_Predicate_anonymous_24736,
  GICXXPred_MI_Predicate_anonymous_24738,
  GICXXPred_MI_Predicate_anonymous_24742,
  GICXXPred_MI_Predicate_anonymous_24744,
  GICXXPred_MI_Predicate_anonymous_24746,
  GICXXPred_MI_Predicate_anonymous_24748,
  GICXXPred_MI_Predicate_anonymous_24750,
  GICXXPred_MI_Predicate_anonymous_24752,
  GICXXPred_MI_Predicate_anonymous_24754,
  GICXXPred_MI_Predicate_anonymous_24756,
  GICXXPred_MI_Predicate_anonymous_24760,
  GICXXPred_MI_Predicate_anonymous_24762,
  GICXXPred_MI_Predicate_anonymous_24764,
  GICXXPred_MI_Predicate_anonymous_24766,
  GICXXPred_MI_Predicate_anonymous_24770,
  GICXXPred_MI_Predicate_anonymous_24772,
  GICXXPred_MI_Predicate_anonymous_24776,
  GICXXPred_MI_Predicate_anonymous_24778,
  GICXXPred_MI_Predicate_anonymous_24780,
  GICXXPred_MI_Predicate_anonymous_24782,
  GICXXPred_MI_Predicate_anonymous_24786,
  GICXXPred_MI_Predicate_anonymous_24788,
  GICXXPred_MI_Predicate_anonymous_24790,
  GICXXPred_MI_Predicate_anonymous_24792,
  GICXXPred_MI_Predicate_anonymous_24794,
  GICXXPred_MI_Predicate_anonymous_24796,
  GICXXPred_MI_Predicate_anonymous_24798,
  GICXXPred_MI_Predicate_anonymous_24800,
  GICXXPred_MI_Predicate_anonymous_24804,
  GICXXPred_MI_Predicate_anonymous_24806,
  GICXXPred_MI_Predicate_anonymous_24808,
  GICXXPred_MI_Predicate_anonymous_24810,
  GICXXPred_MI_Predicate_anonymous_24814,
  GICXXPred_MI_Predicate_anonymous_24816,
  GICXXPred_MI_Predicate_anonymous_24818,
  GICXXPred_MI_Predicate_anonymous_24820,
  GICXXPred_MI_Predicate_anonymous_24824,
  GICXXPred_MI_Predicate_anonymous_24826,
  GICXXPred_MI_Predicate_anonymous_24830,
  GICXXPred_MI_Predicate_anonymous_24832,
  GICXXPred_MI_Predicate_anonymous_24834,
  GICXXPred_MI_Predicate_anonymous_24836,
  GICXXPred_MI_Predicate_anonymous_24838,
  GICXXPred_MI_Predicate_anonymous_24840,
  GICXXPred_MI_Predicate_anonymous_24842,
  GICXXPred_MI_Predicate_anonymous_24844,
  GICXXPred_MI_Predicate_anonymous_24848,
  GICXXPred_MI_Predicate_anonymous_24850,
  GICXXPred_MI_Predicate_anonymous_24852,
  GICXXPred_MI_Predicate_anonymous_24854,
  GICXXPred_MI_Predicate_anonymous_24858,
  GICXXPred_MI_Predicate_anonymous_24860,
  GICXXPred_MI_Predicate_anonymous_24862,
  GICXXPred_MI_Predicate_anonymous_24864,
  GICXXPred_MI_Predicate_anonymous_24866,
  GICXXPred_MI_Predicate_anonymous_24868,
  GICXXPred_MI_Predicate_anonymous_24872,
  GICXXPred_MI_Predicate_anonymous_24874,
  GICXXPred_MI_Predicate_anonymous_24876,
  GICXXPred_MI_Predicate_anonymous_24878,
  GICXXPred_MI_Predicate_anonymous_24880,
  GICXXPred_MI_Predicate_anonymous_24882,
  GICXXPred_MI_Predicate_anonymous_24884,
  GICXXPred_MI_Predicate_anonymous_24886,
  GICXXPred_MI_Predicate_anonymous_24888,
  GICXXPred_MI_Predicate_anonymous_24890,
  GICXXPred_MI_Predicate_anonymous_24894,
  GICXXPred_MI_Predicate_anonymous_24896,
  GICXXPred_MI_Predicate_anonymous_24898,
  GICXXPred_MI_Predicate_anonymous_24900,
  GICXXPred_MI_Predicate_anonymous_24902,
  GICXXPred_MI_Predicate_anonymous_24904,
  GICXXPred_MI_Predicate_anonymous_24906,
  GICXXPred_MI_Predicate_anonymous_24908,
  GICXXPred_MI_Predicate_anonymous_34681,
  GICXXPred_MI_Predicate_anonymous_34988,
  GICXXPred_MI_Predicate_anonymous_34990,
  GICXXPred_MI_Predicate_anonymous_35018,
  GICXXPred_MI_Predicate_anonymous_35193,
  GICXXPred_MI_Predicate_anonymous_35196,
  GICXXPred_MI_Predicate_anonymous_35201,
  GICXXPred_MI_Predicate_anonymous_35205,
  GICXXPred_MI_Predicate_anonymous_35286,
  GICXXPred_MI_Predicate_anonymous_35288,
  GICXXPred_MI_Predicate_anonymous_35316,
  GICXXPred_MI_Predicate_anonymous_35335,
  GICXXPred_MI_Predicate_anonymous_35337,
  GICXXPred_MI_Predicate_anonymous_35345,
  GICXXPred_MI_Predicate_anonymous_35347,
  GICXXPred_MI_Predicate_anonymous_35362,
  GICXXPred_MI_Predicate_anonymous_35366,
  GICXXPred_MI_Predicate_anonymous_35368,
  GICXXPred_MI_Predicate_anonymous_35370,
  GICXXPred_MI_Predicate_csh_mask_16,
  GICXXPred_MI_Predicate_csh_mask_32,
  GICXXPred_MI_Predicate_csh_mask_64,
  GICXXPred_MI_Predicate_cshl_16_oneuse,
  GICXXPred_MI_Predicate_cshl_32_oneuse,
  GICXXPred_MI_Predicate_cshl_64_oneuse,
  GICXXPred_MI_Predicate_csra_16_oneuse,
  GICXXPred_MI_Predicate_csra_32_oneuse,
  GICXXPred_MI_Predicate_csra_64_oneuse,
  GICXXPred_MI_Predicate_csrl_16_oneuse,
  GICXXPred_MI_Predicate_csrl_32_oneuse,
  GICXXPred_MI_Predicate_csrl_64_oneuse,
  GICXXPred_MI_Predicate_fmaximum_oneuse,
  GICXXPred_MI_Predicate_fmaxnum_ieee_oneuse,
  GICXXPred_MI_Predicate_fmaxnum_like_nnan,
  GICXXPred_MI_Predicate_fmaxnum_oneuse,
  GICXXPred_MI_Predicate_fminimum_oneuse,
  GICXXPred_MI_Predicate_fminnum_ieee_oneuse,
  GICXXPred_MI_Predicate_fminnum_like_nnan,
  GICXXPred_MI_Predicate_fminnum_oneuse,
  GICXXPred_MI_Predicate_load_align_less_than_4_local,
  GICXXPred_MI_Predicate_load_align_less_than_4_local_m0,
  GICXXPred_MI_Predicate_not_oneuse,
  GICXXPred_MI_Predicate_or_oneuse,
  GICXXPred_MI_Predicate_select_oneuse,
  GICXXPred_MI_Predicate_shl1_add,
  GICXXPred_MI_Predicate_shl2_add,
  GICXXPred_MI_Predicate_shl3_add,
  GICXXPred_MI_Predicate_shl4_add,
  GICXXPred_MI_Predicate_shl_0_to_4,
  GICXXPred_MI_Predicate_shl_oneuse,
  GICXXPred_MI_Predicate_smax_oneuse,
  GICXXPred_MI_Predicate_smin_oneuse,
  GICXXPred_MI_Predicate_smrd_extloadi8,
  GICXXPred_MI_Predicate_smrd_extloadi16,
  GICXXPred_MI_Predicate_smrd_load,
  GICXXPred_MI_Predicate_smrd_prefetch,
  GICXXPred_MI_Predicate_smrd_sextloadi8,
  GICXXPred_MI_Predicate_smrd_sextloadi16,
  GICXXPred_MI_Predicate_smrd_zextloadi8,
  GICXXPred_MI_Predicate_smrd_zextloadi16,
  GICXXPred_MI_Predicate_srl_oneuse,
  GICXXPred_MI_Predicate_store_align_less_than_4_local,
  GICXXPred_MI_Predicate_store_align_less_than_4_local_m0,
  GICXXPred_MI_Predicate_sub_oneuse,
  GICXXPred_MI_Predicate_umax_oneuse,
  GICXXPred_MI_Predicate_umin_oneuse,
  GICXXPred_MI_Predicate_xor_oneuse,
};
bool AMDGPUInstructionSelector::testMIPredicate_MI(unsigned PredicateID, const MachineInstr & MI, const MatcherState &State) const {
  const MachineFunction &MF = *MI.getParent()->getParent();
  const MachineRegisterInfo &MRI = MF.getRegInfo();
  const auto &Operands = State.RecordedOperands;
  (void)Operands;
  (void)MRI;
  switch (PredicateID) {
  case GICXXPred_MI_Predicate_AMDGPUmul_i24_oneuse: {
    
        return MRI.hasOneNonDBGUse(MI.getOperand(0).getReg());
      
  }
  case GICXXPred_MI_Predicate_AMDGPUmul_u24_oneuse: {
    
        return MRI.hasOneNonDBGUse(MI.getOperand(0).getReg());
      
  }
  case GICXXPred_MI_Predicate_NonACAMDGPUmul_i24_oneuse: {
    
        return MRI.hasOneNonDBGUse(MI.getOperand(0).getReg());
      
  }
  case GICXXPred_MI_Predicate_NonACAMDGPUmul_u24_oneuse: {
    
        return MRI.hasOneNonDBGUse(MI.getOperand(0).getReg());
      
  }
  case GICXXPred_MI_Predicate_NonACAdd_oneuse: {
    
        return MRI.hasOneNonDBGUse(MI.getOperand(0).getReg());
      
  }
  case GICXXPred_MI_Predicate_add_oneuse: {
    
        return MRI.hasOneNonDBGUse(MI.getOperand(0).getReg());
      
  }
  case GICXXPred_MI_Predicate_and_oneuse: {
    
        return MRI.hasOneNonDBGUse(MI.getOperand(0).getReg());
      
  }
  case GICXXPred_MI_Predicate_anonymous_17562: {
    return true;
  }
  case GICXXPred_MI_Predicate_anonymous_17567: {
    return true;
  }
  case GICXXPred_MI_Predicate_anonymous_17568: {
    return true;
  }
  case GICXXPred_MI_Predicate_anonymous_17569: {
    return true;
  }
  case GICXXPred_MI_Predicate_anonymous_17570: {
    return true;
  }
  case GICXXPred_MI_Predicate_anonymous_17571: {
    return true;
  }
  case GICXXPred_MI_Predicate_anonymous_17577: {
    return true;
  }
  case GICXXPred_MI_Predicate_anonymous_17590: {
    return true;
  }
  case GICXXPred_MI_Predicate_anonymous_17594: {
    return true;
  }
  case GICXXPred_MI_Predicate_anonymous_17595: {
    return true;
  }
  case GICXXPred_MI_Predicate_anonymous_17596: {
    return true;
  }
  case GICXXPred_MI_Predicate_anonymous_17597: {
    return true;
  }
  case GICXXPred_MI_Predicate_anonymous_17598: {
    return true;
  }
  case GICXXPred_MI_Predicate_anonymous_17599: {
    return true;
  }
  case GICXXPred_MI_Predicate_anonymous_17600: {
    return true;
  }
  case GICXXPred_MI_Predicate_anonymous_17601: {
    return true;
  }
  case GICXXPred_MI_Predicate_anonymous_17602: {
    return true;
  }
  case GICXXPred_MI_Predicate_anonymous_17603: {
    return true;
  }
  case GICXXPred_MI_Predicate_anonymous_17604: {
    return true;
  }
  case GICXXPred_MI_Predicate_anonymous_17605: {
    return true;
  }
  case GICXXPred_MI_Predicate_anonymous_17606: {
    return true;
  }
  case GICXXPred_MI_Predicate_anonymous_17607: {
    return true;
  }
  case GICXXPred_MI_Predicate_anonymous_17608: {
    return true;
  }
  case GICXXPred_MI_Predicate_anonymous_17609: {
    return true;
  }
  case GICXXPred_MI_Predicate_anonymous_17610: {
    return true;
  }
  case GICXXPred_MI_Predicate_anonymous_17614: {
    return true;
  }
  case GICXXPred_MI_Predicate_anonymous_17615: {
    return true;
  }
  case GICXXPred_MI_Predicate_anonymous_17616: {
    return true;
  }
  case GICXXPred_MI_Predicate_anonymous_17617: {
    return true;
  }
  case GICXXPred_MI_Predicate_anonymous_17618: {
    return true;
  }
  case GICXXPred_MI_Predicate_anonymous_17619: {
    return true;
  }
  case GICXXPred_MI_Predicate_anonymous_17620: {
    return true;
  }
  case GICXXPred_MI_Predicate_anonymous_17621: {
    return true;
  }
  case GICXXPred_MI_Predicate_anonymous_17622: {
    return true;
  }
  case GICXXPred_MI_Predicate_anonymous_17623: {
    return true;
  }
  case GICXXPred_MI_Predicate_anonymous_17624: {
    return true;
  }
  case GICXXPred_MI_Predicate_anonymous_17628: {
    return true;
  }
  case GICXXPred_MI_Predicate_anonymous_17629: {
    return true;
  }
  case GICXXPred_MI_Predicate_anonymous_17630: {
    return true;
  }
  case GICXXPred_MI_Predicate_anonymous_17631: {
    return true;
  }
  case GICXXPred_MI_Predicate_anonymous_17632: {
    return true;
  }
  case GICXXPred_MI_Predicate_anonymous_17633: {
    return true;
  }
  case GICXXPred_MI_Predicate_anonymous_17634: {
    return true;
  }
  case GICXXPred_MI_Predicate_anonymous_17635: {
    return true;
  }
  case GICXXPred_MI_Predicate_anonymous_17636: {
    return true;
  }
  case GICXXPred_MI_Predicate_anonymous_17637: {
    return true;
  }
  case GICXXPred_MI_Predicate_anonymous_17638: {
    return true;
  }
  case GICXXPred_MI_Predicate_anonymous_17642: {
    return true;
  }
  case GICXXPred_MI_Predicate_anonymous_17658: {
    return true;
  }
  case GICXXPred_MI_Predicate_anonymous_17677: {
    return true;
  }
  case GICXXPred_MI_Predicate_anonymous_17683: {
    return true;
  }
  case GICXXPred_MI_Predicate_anonymous_21180: {
    return true;
  }
  case GICXXPred_MI_Predicate_anonymous_22539: {
    return true;
  }
  case GICXXPred_MI_Predicate_anonymous_22541: {
    return true;
  }
  case GICXXPred_MI_Predicate_anonymous_22543: {
    return true;
  }
  case GICXXPred_MI_Predicate_anonymous_22545: {
    return true;
  }
  case GICXXPred_MI_Predicate_anonymous_22547: {
    return true;
  }
  case GICXXPred_MI_Predicate_anonymous_22551: {
    return true;
  }
  case GICXXPred_MI_Predicate_anonymous_22553: {
    return true;
  }
  case GICXXPred_MI_Predicate_anonymous_22555: {
    return true;
  }
  case GICXXPred_MI_Predicate_anonymous_22557: {
    return true;
  }
  case GICXXPred_MI_Predicate_anonymous_22559: {
    return true;
  }
  case GICXXPred_MI_Predicate_anonymous_22759: {
    return true;
  }
  case GICXXPred_MI_Predicate_anonymous_22761: {
    return true;
  }
  case GICXXPred_MI_Predicate_anonymous_23209: {
    return true;
  }
  case GICXXPred_MI_Predicate_anonymous_23219: {
    return true;
  }
  case GICXXPred_MI_Predicate_anonymous_23222: {
    return true;
  }
  case GICXXPred_MI_Predicate_anonymous_23313: {
    return true;
  }
  case GICXXPred_MI_Predicate_anonymous_23602: {
    
        const int ConstantBusLimit = Subtarget->getConstantBusLimit(AMDGPU::V_ADD3_U32_e64);
        int ConstantBusUses = 0;
        for (unsigned i = 0; i < 3; ++i) {
          const RegisterBank *RegBank = RBI.getRegBank(Operands[i]->getReg(), MRI, TRI);
          if (RegBank->getID() == AMDGPU::SGPRRegBankID) {
            if (++ConstantBusUses > ConstantBusLimit)
              return false;
          }
        }
        return true;
      
    llvm_unreachable("anonymous_23602 should have returned");
  }
  case GICXXPred_MI_Predicate_anonymous_23603: {
    
        return MRI.hasOneNonDBGUse(MI.getOperand(0).getReg());
      
  }
  case GICXXPred_MI_Predicate_anonymous_23605: {
    
        const int ConstantBusLimit = Subtarget->getConstantBusLimit(AMDGPU::V_ADD3_U32_e64);
        int ConstantBusUses = 0;
        for (unsigned i = 0; i < 3; ++i) {
          const RegisterBank *RegBank = RBI.getRegBank(Operands[i]->getReg(), MRI, TRI);
          if (RegBank->getID() == AMDGPU::SGPRRegBankID) {
            if (++ConstantBusUses > ConstantBusLimit)
              return false;
          }
        }
        return true;
      
    llvm_unreachable("anonymous_23605 should have returned");
  }
  case GICXXPred_MI_Predicate_anonymous_23606: {
    
        return MRI.hasOneNonDBGUse(MI.getOperand(0).getReg());
      
  }
  case GICXXPred_MI_Predicate_anonymous_23608: {
    
        const int ConstantBusLimit = Subtarget->getConstantBusLimit(AMDGPU::V_ADD3_U32_e64);
        int ConstantBusUses = 0;
        for (unsigned i = 0; i < 3; ++i) {
          const RegisterBank *RegBank = RBI.getRegBank(Operands[i]->getReg(), MRI, TRI);
          if (RegBank->getID() == AMDGPU::SGPRRegBankID) {
            if (++ConstantBusUses > ConstantBusLimit)
              return false;
          }
        }
        return true;
      
    llvm_unreachable("anonymous_23608 should have returned");
  }
  case GICXXPred_MI_Predicate_anonymous_23610: {
    
        const int ConstantBusLimit = Subtarget->getConstantBusLimit(AMDGPU::V_ADD3_U32_e64);
        int ConstantBusUses = 0;
        for (unsigned i = 0; i < 3; ++i) {
          const RegisterBank *RegBank = RBI.getRegBank(Operands[i]->getReg(), MRI, TRI);
          if (RegBank->getID() == AMDGPU::SGPRRegBankID) {
            if (++ConstantBusUses > ConstantBusLimit)
              return false;
          }
        }
        return true;
      
    llvm_unreachable("anonymous_23610 should have returned");
  }
  case GICXXPred_MI_Predicate_anonymous_23611: {
    
        return MRI.hasOneNonDBGUse(MI.getOperand(0).getReg());
      
  }
  case GICXXPred_MI_Predicate_anonymous_23613: {
    
        const int ConstantBusLimit = Subtarget->getConstantBusLimit(AMDGPU::V_ADD3_U32_e64);
        int ConstantBusUses = 0;
        for (unsigned i = 0; i < 3; ++i) {
          const RegisterBank *RegBank = RBI.getRegBank(Operands[i]->getReg(), MRI, TRI);
          if (RegBank->getID() == AMDGPU::SGPRRegBankID) {
            if (++ConstantBusUses > ConstantBusLimit)
              return false;
          }
        }
        return true;
      
    llvm_unreachable("anonymous_23613 should have returned");
  }
  case GICXXPred_MI_Predicate_anonymous_23615: {
    
        const int ConstantBusLimit = Subtarget->getConstantBusLimit(AMDGPU::V_ADD3_U32_e64);
        int ConstantBusUses = 0;
        for (unsigned i = 0; i < 3; ++i) {
          const RegisterBank *RegBank = RBI.getRegBank(Operands[i]->getReg(), MRI, TRI);
          if (RegBank->getID() == AMDGPU::SGPRRegBankID) {
            if (++ConstantBusUses > ConstantBusLimit)
              return false;
          }
        }
        return true;
      
    llvm_unreachable("anonymous_23615 should have returned");
  }
  case GICXXPred_MI_Predicate_anonymous_23616: {
    
        return MRI.hasOneNonDBGUse(MI.getOperand(0).getReg());
      
  }
  case GICXXPred_MI_Predicate_anonymous_23618: {
    
        const int ConstantBusLimit = Subtarget->getConstantBusLimit(AMDGPU::V_ADD3_U32_e64);
        int ConstantBusUses = 0;
        for (unsigned i = 0; i < 3; ++i) {
          const RegisterBank *RegBank = RBI.getRegBank(Operands[i]->getReg(), MRI, TRI);
          if (RegBank->getID() == AMDGPU::SGPRRegBankID) {
            if (++ConstantBusUses > ConstantBusLimit)
              return false;
          }
        }
        return true;
      
    llvm_unreachable("anonymous_23618 should have returned");
  }
  case GICXXPred_MI_Predicate_anonymous_23619: {
    
        return MRI.hasOneNonDBGUse(MI.getOperand(0).getReg());
      
  }
  case GICXXPred_MI_Predicate_anonymous_23621: {
    
        const int ConstantBusLimit = Subtarget->getConstantBusLimit(AMDGPU::V_ADD3_U32_e64);
        int ConstantBusUses = 0;
        for (unsigned i = 0; i < 3; ++i) {
          const RegisterBank *RegBank = RBI.getRegBank(Operands[i]->getReg(), MRI, TRI);
          if (RegBank->getID() == AMDGPU::SGPRRegBankID) {
            if (++ConstantBusUses > ConstantBusLimit)
              return false;
          }
        }
        return true;
      
    llvm_unreachable("anonymous_23621 should have returned");
  }
  case GICXXPred_MI_Predicate_anonymous_23622: {
    
        return MRI.hasOneNonDBGUse(MI.getOperand(0).getReg());
      
  }
  case GICXXPred_MI_Predicate_anonymous_23625: {
    
        const int ConstantBusLimit = Subtarget->getConstantBusLimit(AMDGPU::V_ADD3_U32_e64);
        int ConstantBusUses = 0;
        for (unsigned i = 0; i < 3; ++i) {
          const RegisterBank *RegBank = RBI.getRegBank(Operands[i]->getReg(), MRI, TRI);
          if (RegBank->getID() == AMDGPU::SGPRRegBankID) {
            if (++ConstantBusUses > ConstantBusLimit)
              return false;
          }
        }
        return true;
      
    llvm_unreachable("anonymous_23625 should have returned");
  }
  case GICXXPred_MI_Predicate_anonymous_23626: {
    
        return MRI.hasOneNonDBGUse(MI.getOperand(0).getReg());
      
  }
  case GICXXPred_MI_Predicate_anonymous_23633: {
    
        const int ConstantBusLimit = Subtarget->getConstantBusLimit(AMDGPU::V_ADD3_U32_e64);
        int ConstantBusUses = 0;
        for (unsigned i = 0; i < 3; ++i) {
          const RegisterBank *RegBank = RBI.getRegBank(Operands[i]->getReg(), MRI, TRI);
          if (RegBank->getID() == AMDGPU::SGPRRegBankID) {
            if (++ConstantBusUses > ConstantBusLimit)
              return false;
          }
        }
        return true;
      
    llvm_unreachable("anonymous_23633 should have returned");
  }
  case GICXXPred_MI_Predicate_anonymous_23634: {
    
        return MRI.hasOneNonDBGUse(MI.getOperand(0).getReg());
      
  }
  case GICXXPred_MI_Predicate_anonymous_23670: {
    
        const int ConstantBusLimit = Subtarget->getConstantBusLimit(AMDGPU::V_ADD3_U32_e64);
        int ConstantBusUses = 0;
        for (unsigned i = 0; i < 3; ++i) {
          const RegisterBank *RegBank = RBI.getRegBank(Operands[i]->getReg(), MRI, TRI);
          if (RegBank->getID() == AMDGPU::SGPRRegBankID) {
            if (++ConstantBusUses > ConstantBusLimit)
              return false;
          }
        }
        return true;
      
    llvm_unreachable("anonymous_23670 should have returned");
  }
  case GICXXPred_MI_Predicate_anonymous_23764: {
    return true;
  }
  case GICXXPred_MI_Predicate_anonymous_23770: {
    return true;
  }
  case GICXXPred_MI_Predicate_anonymous_23772: {
    return true;
  }
  case GICXXPred_MI_Predicate_anonymous_23774: {
    return true;
  }
  case GICXXPred_MI_Predicate_anonymous_23776: {
    return true;
  }
  case GICXXPred_MI_Predicate_anonymous_23778: {
    return true;
  }
  case GICXXPred_MI_Predicate_anonymous_23780: {
    return true;
  }
  case GICXXPred_MI_Predicate_anonymous_24726: {
    
      return MF.getInfo<SIMachineFunctionInfo>()->mayNeedAGPRs();
    
  }
  case GICXXPred_MI_Predicate_anonymous_24728: {
    
      return !MF.getInfo<SIMachineFunctionInfo>()->mayNeedAGPRs();
    
  }
  case GICXXPred_MI_Predicate_anonymous_24732: {
    
      return MF.getInfo<SIMachineFunctionInfo>()->mayNeedAGPRs();
    
  }
  case GICXXPred_MI_Predicate_anonymous_24734: {
    
      return !MF.getInfo<SIMachineFunctionInfo>()->mayNeedAGPRs();
    
  }
  case GICXXPred_MI_Predicate_anonymous_24736: {
    
      return MF.getInfo<SIMachineFunctionInfo>()->mayNeedAGPRs();
    
  }
  case GICXXPred_MI_Predicate_anonymous_24738: {
    
      return !MF.getInfo<SIMachineFunctionInfo>()->mayNeedAGPRs();
    
  }
  case GICXXPred_MI_Predicate_anonymous_24742: {
    
      return MF.getInfo<SIMachineFunctionInfo>()->mayNeedAGPRs();
    
  }
  case GICXXPred_MI_Predicate_anonymous_24744: {
    
      return !MF.getInfo<SIMachineFunctionInfo>()->mayNeedAGPRs();
    
  }
  case GICXXPred_MI_Predicate_anonymous_24746: {
    
      return MF.getInfo<SIMachineFunctionInfo>()->mayNeedAGPRs();
    
  }
  case GICXXPred_MI_Predicate_anonymous_24748: {
    
      return !MF.getInfo<SIMachineFunctionInfo>()->mayNeedAGPRs();
    
  }
  case GICXXPred_MI_Predicate_anonymous_24750: {
    
      return MF.getInfo<SIMachineFunctionInfo>()->mayNeedAGPRs();
    
  }
  case GICXXPred_MI_Predicate_anonymous_24752: {
    
      return !MF.getInfo<SIMachineFunctionInfo>()->mayNeedAGPRs();
    
  }
  case GICXXPred_MI_Predicate_anonymous_24754: {
    
      return MF.getInfo<SIMachineFunctionInfo>()->mayNeedAGPRs();
    
  }
  case GICXXPred_MI_Predicate_anonymous_24756: {
    
      return !MF.getInfo<SIMachineFunctionInfo>()->mayNeedAGPRs();
    
  }
  case GICXXPred_MI_Predicate_anonymous_24760: {
    
      return MF.getInfo<SIMachineFunctionInfo>()->mayNeedAGPRs();
    
  }
  case GICXXPred_MI_Predicate_anonymous_24762: {
    
      return !MF.getInfo<SIMachineFunctionInfo>()->mayNeedAGPRs();
    
  }
  case GICXXPred_MI_Predicate_anonymous_24764: {
    
      return MF.getInfo<SIMachineFunctionInfo>()->mayNeedAGPRs();
    
  }
  case GICXXPred_MI_Predicate_anonymous_24766: {
    
      return !MF.getInfo<SIMachineFunctionInfo>()->mayNeedAGPRs();
    
  }
  case GICXXPred_MI_Predicate_anonymous_24770: {
    
      return MF.getInfo<SIMachineFunctionInfo>()->mayNeedAGPRs();
    
  }
  case GICXXPred_MI_Predicate_anonymous_24772: {
    
      return !MF.getInfo<SIMachineFunctionInfo>()->mayNeedAGPRs();
    
  }
  case GICXXPred_MI_Predicate_anonymous_24776: {
    
      return MF.getInfo<SIMachineFunctionInfo>()->mayNeedAGPRs();
    
  }
  case GICXXPred_MI_Predicate_anonymous_24778: {
    
      return !MF.getInfo<SIMachineFunctionInfo>()->mayNeedAGPRs();
    
  }
  case GICXXPred_MI_Predicate_anonymous_24780: {
    
      return MF.getInfo<SIMachineFunctionInfo>()->mayNeedAGPRs();
    
  }
  case GICXXPred_MI_Predicate_anonymous_24782: {
    
      return !MF.getInfo<SIMachineFunctionInfo>()->mayNeedAGPRs();
    
  }
  case GICXXPred_MI_Predicate_anonymous_24786: {
    
      return MF.getInfo<SIMachineFunctionInfo>()->mayNeedAGPRs();
    
  }
  case GICXXPred_MI_Predicate_anonymous_24788: {
    
      return !MF.getInfo<SIMachineFunctionInfo>()->mayNeedAGPRs();
    
  }
  case GICXXPred_MI_Predicate_anonymous_24790: {
    
      return MF.getInfo<SIMachineFunctionInfo>()->mayNeedAGPRs();
    
  }
  case GICXXPred_MI_Predicate_anonymous_24792: {
    
      return !MF.getInfo<SIMachineFunctionInfo>()->mayNeedAGPRs();
    
  }
  case GICXXPred_MI_Predicate_anonymous_24794: {
    
      return MF.getInfo<SIMachineFunctionInfo>()->mayNeedAGPRs();
    
  }
  case GICXXPred_MI_Predicate_anonymous_24796: {
    
      return !MF.getInfo<SIMachineFunctionInfo>()->mayNeedAGPRs();
    
  }
  case GICXXPred_MI_Predicate_anonymous_24798: {
    
      return MF.getInfo<SIMachineFunctionInfo>()->mayNeedAGPRs();
    
  }
  case GICXXPred_MI_Predicate_anonymous_24800: {
    
      return !MF.getInfo<SIMachineFunctionInfo>()->mayNeedAGPRs();
    
  }
  case GICXXPred_MI_Predicate_anonymous_24804: {
    
      return MF.getInfo<SIMachineFunctionInfo>()->mayNeedAGPRs();
    
  }
  case GICXXPred_MI_Predicate_anonymous_24806: {
    
      return !MF.getInfo<SIMachineFunctionInfo>()->mayNeedAGPRs();
    
  }
  case GICXXPred_MI_Predicate_anonymous_24808: {
    
      return MF.getInfo<SIMachineFunctionInfo>()->mayNeedAGPRs();
    
  }
  case GICXXPred_MI_Predicate_anonymous_24810: {
    
      return !MF.getInfo<SIMachineFunctionInfo>()->mayNeedAGPRs();
    
  }
  case GICXXPred_MI_Predicate_anonymous_24814: {
    
      return MF.getInfo<SIMachineFunctionInfo>()->mayNeedAGPRs();
    
  }
  case GICXXPred_MI_Predicate_anonymous_24816: {
    
      return !MF.getInfo<SIMachineFunctionInfo>()->mayNeedAGPRs();
    
  }
  case GICXXPred_MI_Predicate_anonymous_24818: {
    
      return MF.getInfo<SIMachineFunctionInfo>()->mayNeedAGPRs();
    
  }
  case GICXXPred_MI_Predicate_anonymous_24820: {
    
      return !MF.getInfo<SIMachineFunctionInfo>()->mayNeedAGPRs();
    
  }
  case GICXXPred_MI_Predicate_anonymous_24824: {
    
      return MF.getInfo<SIMachineFunctionInfo>()->mayNeedAGPRs();
    
  }
  case GICXXPred_MI_Predicate_anonymous_24826: {
    
      return !MF.getInfo<SIMachineFunctionInfo>()->mayNeedAGPRs();
    
  }
  case GICXXPred_MI_Predicate_anonymous_24830: {
    
      return MF.getInfo<SIMachineFunctionInfo>()->mayNeedAGPRs();
    
  }
  case GICXXPred_MI_Predicate_anonymous_24832: {
    
      return !MF.getInfo<SIMachineFunctionInfo>()->mayNeedAGPRs();
    
  }
  case GICXXPred_MI_Predicate_anonymous_24834: {
    
      return MF.getInfo<SIMachineFunctionInfo>()->mayNeedAGPRs();
    
  }
  case GICXXPred_MI_Predicate_anonymous_24836: {
    
      return !MF.getInfo<SIMachineFunctionInfo>()->mayNeedAGPRs();
    
  }
  case GICXXPred_MI_Predicate_anonymous_24838: {
    
      return MF.getInfo<SIMachineFunctionInfo>()->mayNeedAGPRs();
    
  }
  case GICXXPred_MI_Predicate_anonymous_24840: {
    
      return !MF.getInfo<SIMachineFunctionInfo>()->mayNeedAGPRs();
    
  }
  case GICXXPred_MI_Predicate_anonymous_24842: {
    
      return MF.getInfo<SIMachineFunctionInfo>()->mayNeedAGPRs();
    
  }
  case GICXXPred_MI_Predicate_anonymous_24844: {
    
      return !MF.getInfo<SIMachineFunctionInfo>()->mayNeedAGPRs();
    
  }
  case GICXXPred_MI_Predicate_anonymous_24848: {
    
      return MF.getInfo<SIMachineFunctionInfo>()->mayNeedAGPRs();
    
  }
  case GICXXPred_MI_Predicate_anonymous_24850: {
    
      return !MF.getInfo<SIMachineFunctionInfo>()->mayNeedAGPRs();
    
  }
  case GICXXPred_MI_Predicate_anonymous_24852: {
    
      return MF.getInfo<SIMachineFunctionInfo>()->mayNeedAGPRs();
    
  }
  case GICXXPred_MI_Predicate_anonymous_24854: {
    
      return !MF.getInfo<SIMachineFunctionInfo>()->mayNeedAGPRs();
    
  }
  case GICXXPred_MI_Predicate_anonymous_24858: {
    
      return MF.getInfo<SIMachineFunctionInfo>()->mayNeedAGPRs();
    
  }
  case GICXXPred_MI_Predicate_anonymous_24860: {
    
      return !MF.getInfo<SIMachineFunctionInfo>()->mayNeedAGPRs();
    
  }
  case GICXXPred_MI_Predicate_anonymous_24862: {
    
      return MF.getInfo<SIMachineFunctionInfo>()->mayNeedAGPRs();
    
  }
  case GICXXPred_MI_Predicate_anonymous_24864: {
    
      return !MF.getInfo<SIMachineFunctionInfo>()->mayNeedAGPRs();
    
  }
  case GICXXPred_MI_Predicate_anonymous_24866: {
    
      return MF.getInfo<SIMachineFunctionInfo>()->mayNeedAGPRs();
    
  }
  case GICXXPred_MI_Predicate_anonymous_24868: {
    
      return !MF.getInfo<SIMachineFunctionInfo>()->mayNeedAGPRs();
    
  }
  case GICXXPred_MI_Predicate_anonymous_24872: {
    
      return MF.getInfo<SIMachineFunctionInfo>()->mayNeedAGPRs();
    
  }
  case GICXXPred_MI_Predicate_anonymous_24874: {
    
      return !MF.getInfo<SIMachineFunctionInfo>()->mayNeedAGPRs();
    
  }
  case GICXXPred_MI_Predicate_anonymous_24876: {
    
      return MF.getInfo<SIMachineFunctionInfo>()->mayNeedAGPRs();
    
  }
  case GICXXPred_MI_Predicate_anonymous_24878: {
    
      return !MF.getInfo<SIMachineFunctionInfo>()->mayNeedAGPRs();
    
  }
  case GICXXPred_MI_Predicate_anonymous_24880: {
    
      return MF.getInfo<SIMachineFunctionInfo>()->mayNeedAGPRs();
    
  }
  case GICXXPred_MI_Predicate_anonymous_24882: {
    
      return !MF.getInfo<SIMachineFunctionInfo>()->mayNeedAGPRs();
    
  }
  case GICXXPred_MI_Predicate_anonymous_24884: {
    
      return MF.getInfo<SIMachineFunctionInfo>()->mayNeedAGPRs();
    
  }
  case GICXXPred_MI_Predicate_anonymous_24886: {
    
      return !MF.getInfo<SIMachineFunctionInfo>()->mayNeedAGPRs();
    
  }
  case GICXXPred_MI_Predicate_anonymous_24888: {
    
      return MF.getInfo<SIMachineFunctionInfo>()->mayNeedAGPRs();
    
  }
  case GICXXPred_MI_Predicate_anonymous_24890: {
    
      return !MF.getInfo<SIMachineFunctionInfo>()->mayNeedAGPRs();
    
  }
  case GICXXPred_MI_Predicate_anonymous_24894: {
    
      return MF.getInfo<SIMachineFunctionInfo>()->mayNeedAGPRs();
    
  }
  case GICXXPred_MI_Predicate_anonymous_24896: {
    
      return !MF.getInfo<SIMachineFunctionInfo>()->mayNeedAGPRs();
    
  }
  case GICXXPred_MI_Predicate_anonymous_24898: {
    
      return MF.getInfo<SIMachineFunctionInfo>()->mayNeedAGPRs();
    
  }
  case GICXXPred_MI_Predicate_anonymous_24900: {
    
      return !MF.getInfo<SIMachineFunctionInfo>()->mayNeedAGPRs();
    
  }
  case GICXXPred_MI_Predicate_anonymous_24902: {
    
      return MF.getInfo<SIMachineFunctionInfo>()->mayNeedAGPRs();
    
  }
  case GICXXPred_MI_Predicate_anonymous_24904: {
    
      return !MF.getInfo<SIMachineFunctionInfo>()->mayNeedAGPRs();
    
  }
  case GICXXPred_MI_Predicate_anonymous_24906: {
    
      return MF.getInfo<SIMachineFunctionInfo>()->mayNeedAGPRs();
    
  }
  case GICXXPred_MI_Predicate_anonymous_24908: {
    
      return !MF.getInfo<SIMachineFunctionInfo>()->mayNeedAGPRs();
    
  }
  case GICXXPred_MI_Predicate_anonymous_34681: {
    return true;
  }
  case GICXXPred_MI_Predicate_anonymous_34988: {
    return true;
  }
  case GICXXPred_MI_Predicate_anonymous_34990: {
    return true;
  }
  case GICXXPred_MI_Predicate_anonymous_35018: {
    return true;
  }
  case GICXXPred_MI_Predicate_anonymous_35193: {
    return true;
  }
  case GICXXPred_MI_Predicate_anonymous_35196: {
    return true;
  }
  case GICXXPred_MI_Predicate_anonymous_35201: {
    return true;
  }
  case GICXXPred_MI_Predicate_anonymous_35205: {
    return true;
  }
  case GICXXPred_MI_Predicate_anonymous_35286: {
    return true;
  }
  case GICXXPred_MI_Predicate_anonymous_35288: {
    return true;
  }
  case GICXXPred_MI_Predicate_anonymous_35316: {
    
        const SITargetLowering *TLI = static_cast<const SITargetLowering *>(
          MF.getSubtarget().getTargetLowering());
    
        return TLI->isCanonicalized(MI.getOperand(1).getReg(), const_cast<MachineFunction&>(MF)) &&
          TLI->isCanonicalized(MI.getOperand(2).getReg(), const_cast<MachineFunction&>(MF));
      
    llvm_unreachable("anonymous_35316 should have returned");
  }
  case GICXXPred_MI_Predicate_anonymous_35335: {
    return true;
  }
  case GICXXPred_MI_Predicate_anonymous_35337: {
    return true;
  }
  case GICXXPred_MI_Predicate_anonymous_35345: {
    return true;
  }
  case GICXXPred_MI_Predicate_anonymous_35347: {
    return true;
  }
  case GICXXPred_MI_Predicate_anonymous_35362: {
    return true;
  }
  case GICXXPred_MI_Predicate_anonymous_35366: {
    return true;
  }
  case GICXXPred_MI_Predicate_anonymous_35368: {
    return true;
  }
  case GICXXPred_MI_Predicate_anonymous_35370: {
    return true;
  }
  case GICXXPred_MI_Predicate_csh_mask_16: {
     return isUnneededShiftMask(MI, 4); 
  }
  case GICXXPred_MI_Predicate_csh_mask_32: {
     return isUnneededShiftMask(MI, 5); 
  }
  case GICXXPred_MI_Predicate_csh_mask_64: {
     return isUnneededShiftMask(MI, 6); 
  }
  case GICXXPred_MI_Predicate_cshl_16_oneuse: {
    
        return MRI.hasOneNonDBGUse(MI.getOperand(0).getReg());
      
  }
  case GICXXPred_MI_Predicate_cshl_32_oneuse: {
    
        return MRI.hasOneNonDBGUse(MI.getOperand(0).getReg());
      
  }
  case GICXXPred_MI_Predicate_cshl_64_oneuse: {
    
        return MRI.hasOneNonDBGUse(MI.getOperand(0).getReg());
      
  }
  case GICXXPred_MI_Predicate_csra_16_oneuse: {
    
        return MRI.hasOneNonDBGUse(MI.getOperand(0).getReg());
      
  }
  case GICXXPred_MI_Predicate_csra_32_oneuse: {
    
        return MRI.hasOneNonDBGUse(MI.getOperand(0).getReg());
      
  }
  case GICXXPred_MI_Predicate_csra_64_oneuse: {
    
        return MRI.hasOneNonDBGUse(MI.getOperand(0).getReg());
      
  }
  case GICXXPred_MI_Predicate_csrl_16_oneuse: {
    
        return MRI.hasOneNonDBGUse(MI.getOperand(0).getReg());
      
  }
  case GICXXPred_MI_Predicate_csrl_32_oneuse: {
    
        return MRI.hasOneNonDBGUse(MI.getOperand(0).getReg());
      
  }
  case GICXXPred_MI_Predicate_csrl_64_oneuse: {
    
        return MRI.hasOneNonDBGUse(MI.getOperand(0).getReg());
      
  }
  case GICXXPred_MI_Predicate_fmaximum_oneuse: {
    
        return MRI.hasOneNonDBGUse(MI.getOperand(0).getReg());
      
  }
  case GICXXPred_MI_Predicate_fmaxnum_ieee_oneuse: {
    
        return MRI.hasOneNonDBGUse(MI.getOperand(0).getReg());
      
  }
  case GICXXPred_MI_Predicate_fmaxnum_like_nnan: {
    
        return isKnownNeverNaN(MI.getOperand(0).getReg(), MRI);
      
  }
  case GICXXPred_MI_Predicate_fmaxnum_oneuse: {
    
        return MRI.hasOneNonDBGUse(MI.getOperand(0).getReg());
      
  }
  case GICXXPred_MI_Predicate_fminimum_oneuse: {
    
        return MRI.hasOneNonDBGUse(MI.getOperand(0).getReg());
      
  }
  case GICXXPred_MI_Predicate_fminnum_ieee_oneuse: {
    
        return MRI.hasOneNonDBGUse(MI.getOperand(0).getReg());
      
  }
  case GICXXPred_MI_Predicate_fminnum_like_nnan: {
    
        return isKnownNeverNaN(MI.getOperand(0).getReg(), MRI);
      
  }
  case GICXXPred_MI_Predicate_fminnum_oneuse: {
    
        return MRI.hasOneNonDBGUse(MI.getOperand(0).getReg());
      
  }
  case GICXXPred_MI_Predicate_load_align_less_than_4_local: {
    return (*MI.memoperands_begin())->getAlign() < 4;
  }
  case GICXXPred_MI_Predicate_load_align_less_than_4_local_m0: {
    return (*MI.memoperands_begin())->getAlign() < 4;
  }
  case GICXXPred_MI_Predicate_not_oneuse: {
    
        return MRI.hasOneNonDBGUse(MI.getOperand(0).getReg());
      
  }
  case GICXXPred_MI_Predicate_or_oneuse: {
    
        return MRI.hasOneNonDBGUse(MI.getOperand(0).getReg());
      
  }
  case GICXXPred_MI_Predicate_select_oneuse: {
    
        return MRI.hasOneNonDBGUse(MI.getOperand(0).getReg());
      
  }
  case GICXXPred_MI_Predicate_shl1_add: {
    return true;
  }
  case GICXXPred_MI_Predicate_shl2_add: {
    return true;
  }
  case GICXXPred_MI_Predicate_shl3_add: {
    return true;
  }
  case GICXXPred_MI_Predicate_shl4_add: {
    return true;
  }
  case GICXXPred_MI_Predicate_shl_0_to_4: {
    
        int64_t Imm = 0;
        if (!mi_match(MI.getOperand(2).getReg(), MRI, m_ICst(Imm)) &&
            !mi_match(MI.getOperand(2).getReg(), MRI, m_Copy(m_ICst(Imm))))
          return false;
        return (uint64_t)Imm <= 4;
      
    llvm_unreachable("shl_0_to_4 should have returned");
  }
  case GICXXPred_MI_Predicate_shl_oneuse: {
    
        return MRI.hasOneNonDBGUse(MI.getOperand(0).getReg());
      
  }
  case GICXXPred_MI_Predicate_smax_oneuse: {
    
        return MRI.hasOneNonDBGUse(MI.getOperand(0).getReg());
      
  }
  case GICXXPred_MI_Predicate_smin_oneuse: {
    
        return MRI.hasOneNonDBGUse(MI.getOperand(0).getReg());
      
  }
  case GICXXPred_MI_Predicate_smrd_extloadi8: {
    
        if (!MI.hasOneMemOperand())
          return false;
        if (!isInstrUniform(MI))
          return false;
    
        // FIXME: We should probably be caching this.
        SmallVector<GEPInfo, 4> AddrInfo;
        getAddrModeInfo(MI, MRI, AddrInfo);
    
        if (hasVgprParts(AddrInfo))
          return false;
        return true;
      
    llvm_unreachable("smrd_extloadi8 should have returned");
  }
  case GICXXPred_MI_Predicate_smrd_extloadi16: {
    
        if (!MI.hasOneMemOperand())
          return false;
        if (!isInstrUniform(MI))
          return false;
    
        // FIXME: We should probably be caching this.
        SmallVector<GEPInfo, 4> AddrInfo;
        getAddrModeInfo(MI, MRI, AddrInfo);
    
        if (hasVgprParts(AddrInfo))
          return false;
        return true;
      
    llvm_unreachable("smrd_extloadi16 should have returned");
  }
  case GICXXPred_MI_Predicate_smrd_load: {
    
        if (!MI.hasOneMemOperand())
          return false;
        if (!isInstrUniform(MI))
          return false;
    
        // FIXME: We should probably be caching this.
        SmallVector<GEPInfo, 4> AddrInfo;
        getAddrModeInfo(MI, MRI, AddrInfo);
    
        if (hasVgprParts(AddrInfo))
          return false;
        return true;
      
    llvm_unreachable("smrd_load should have returned");
  }
  case GICXXPred_MI_Predicate_smrd_prefetch: {
    
        return isInstrUniform(MI);
      
  }
  case GICXXPred_MI_Predicate_smrd_sextloadi8: {
    
        if (!MI.hasOneMemOperand())
          return false;
        if (!isInstrUniform(MI))
          return false;
    
        // FIXME: We should probably be caching this.
        SmallVector<GEPInfo, 4> AddrInfo;
        getAddrModeInfo(MI, MRI, AddrInfo);
    
        if (hasVgprParts(AddrInfo))
          return false;
        return true;
      
    llvm_unreachable("smrd_sextloadi8 should have returned");
  }
  case GICXXPred_MI_Predicate_smrd_sextloadi16: {
    
        if (!MI.hasOneMemOperand())
          return false;
        if (!isInstrUniform(MI))
          return false;
    
        // FIXME: We should probably be caching this.
        SmallVector<GEPInfo, 4> AddrInfo;
        getAddrModeInfo(MI, MRI, AddrInfo);
    
        if (hasVgprParts(AddrInfo))
          return false;
        return true;
      
    llvm_unreachable("smrd_sextloadi16 should have returned");
  }
  case GICXXPred_MI_Predicate_smrd_zextloadi8: {
    
        if (!MI.hasOneMemOperand())
          return false;
        if (!isInstrUniform(MI))
          return false;
    
        // FIXME: We should probably be caching this.
        SmallVector<GEPInfo, 4> AddrInfo;
        getAddrModeInfo(MI, MRI, AddrInfo);
    
        if (hasVgprParts(AddrInfo))
          return false;
        return true;
      
    llvm_unreachable("smrd_zextloadi8 should have returned");
  }
  case GICXXPred_MI_Predicate_smrd_zextloadi16: {
    
        if (!MI.hasOneMemOperand())
          return false;
        if (!isInstrUniform(MI))
          return false;
    
        // FIXME: We should probably be caching this.
        SmallVector<GEPInfo, 4> AddrInfo;
        getAddrModeInfo(MI, MRI, AddrInfo);
    
        if (hasVgprParts(AddrInfo))
          return false;
        return true;
      
    llvm_unreachable("smrd_zextloadi16 should have returned");
  }
  case GICXXPred_MI_Predicate_srl_oneuse: {
    
        return MRI.hasOneNonDBGUse(MI.getOperand(0).getReg());
      
  }
  case GICXXPred_MI_Predicate_store_align_less_than_4_local: {
    return (*MI.memoperands_begin())->getAlign() < 4;
  }
  case GICXXPred_MI_Predicate_store_align_less_than_4_local_m0: {
    return (*MI.memoperands_begin())->getAlign() < 4;
  }
  case GICXXPred_MI_Predicate_sub_oneuse: {
    
        return MRI.hasOneNonDBGUse(MI.getOperand(0).getReg());
      
  }
  case GICXXPred_MI_Predicate_umax_oneuse: {
    
        return MRI.hasOneNonDBGUse(MI.getOperand(0).getReg());
      
  }
  case GICXXPred_MI_Predicate_umin_oneuse: {
    
        return MRI.hasOneNonDBGUse(MI.getOperand(0).getReg());
      
  }
  case GICXXPred_MI_Predicate_xor_oneuse: {
    
        return MRI.hasOneNonDBGUse(MI.getOperand(0).getReg());
      
  }
  }
  llvm_unreachable("Unknown predicate");
  return false;
}
// PatFrag predicates.
enum {
  GICXXPred_I64_Predicate_IMMZeroBasedBitfieldMask = GICXXPred_Invalid + 1,
  GICXXPred_I64_Predicate_InlineImm16,
  GICXXPred_I64_Predicate_InlineImm32,
  GICXXPred_I64_Predicate_InlineImm64,
  GICXXPred_I64_Predicate_NegSubInlineConst32,
  GICXXPred_I64_Predicate_NegSubInlineIntConst16,
  GICXXPred_I64_Predicate_SIMM16bit,
  GICXXPred_I64_Predicate_ShiftAmt32Imm,
  GICXXPred_I64_Predicate_i32imm_one,
  GICXXPred_I64_Predicate_i32imm_zero,
  GICXXPred_I64_Predicate_i64imm_32bit,
};
bool AMDGPUInstructionSelector::testImmPredicate_I64(unsigned PredicateID, int64_t Imm) const {
  switch (PredicateID) {
  case GICXXPred_I64_Predicate_IMMZeroBasedBitfieldMask: {
    
      return isMask_32(Imm);
    
  }
  case GICXXPred_I64_Predicate_InlineImm16: {
    
      return isInlineImmediate16(Imm);
    
  }
  case GICXXPred_I64_Predicate_InlineImm32: {
    
      return isInlineImmediate32(Imm);
    
  }
  case GICXXPred_I64_Predicate_InlineImm64: {
    
      return isInlineImmediate64(Imm);
    
  }
  case GICXXPred_I64_Predicate_NegSubInlineConst32: {
    
      return Imm < -16 && Imm >= -64;
    
  }
  case GICXXPred_I64_Predicate_NegSubInlineIntConst16: {
    
      return Imm < -16 && Imm >= -64;
    
  }
  case GICXXPred_I64_Predicate_SIMM16bit: {
    return isInt<16>(Imm) || isUInt<16>(Imm);
  }
  case GICXXPred_I64_Predicate_ShiftAmt32Imm: {
    
      return Imm < 32;
    
  }
  case GICXXPred_I64_Predicate_i32imm_one: {
    
      return Imm == 1;
    
  }
  case GICXXPred_I64_Predicate_i32imm_zero: {
    
      return Imm == 0;
    
  }
  case GICXXPred_I64_Predicate_i64imm_32bit: {
    
      return (Imm & 0xffffffffULL) == static_cast<uint64_t>(Imm);
    
  }
  }
  llvm_unreachable("Unknown predicate");
  return false;
}
// PatFrag predicates.
enum {
  GICXXPred_APFloat_Predicate_InlineImmFP32 = GICXXPred_Invalid + 1,
  GICXXPred_APFloat_Predicate_InlineImmFP64,
  GICXXPred_APFloat_Predicate_fpimm_neg_pow2_prefer_ldexp_f64,
  GICXXPred_APFloat_Predicate_fpimm_pos_pow2_prefer_ldexp_f64,
};
bool AMDGPUInstructionSelector::testImmPredicate_APFloat(unsigned PredicateID, const APFloat & Imm) const {
  switch (PredicateID) {
  case GICXXPred_APFloat_Predicate_InlineImmFP32: {
    
      return isInlineImmediate(Imm);
    
  }
  case GICXXPred_APFloat_Predicate_InlineImmFP64: {
    
      return isInlineImmediate(Imm);
    
  }
  case GICXXPred_APFloat_Predicate_fpimm_neg_pow2_prefer_ldexp_f64: {
    
        if (!Imm.isNegative())
          return false;
        int Exp = Imm.getExactLog2Abs();
        // Prefer leaving the FP inline immediates as they are.
        // 0.5, 1.0, 2.0, 4.0
    
        // For f64 ldexp is always better than materializing a 64-bit
        // constant.
        return Exp != INT_MIN && (Exp < -1 || Exp > 2);
      
    llvm_unreachable("fpimm_neg_pow2_prefer_ldexp_f64 should have returned");
  }
  case GICXXPred_APFloat_Predicate_fpimm_pos_pow2_prefer_ldexp_f64: {
    
        if (Imm.isNegative())
          return false;
    
        int Exp = Imm.getExactLog2Abs();
        // Prefer leaving the FP inline immediates as they are.
        // 0.5, 1.0, 2.0, 4.0
    
        // For f64 ldexp is always better than materializing a 64-bit
        // constant.
        return Exp != INT_MIN && (Exp < -1 || Exp > 2);
      
    llvm_unreachable("fpimm_pos_pow2_prefer_ldexp_f64 should have returned");
  }
  }
  llvm_unreachable("Unknown predicate");
  return false;
}
// PatFrag predicates.
bool AMDGPUInstructionSelector::testImmPredicate_APInt(unsigned PredicateID, const APInt & Imm) const {
  llvm_unreachable("Unknown predicate");
  return false;
}
bool AMDGPUInstructionSelector::testSimplePredicate(unsigned) const {
    llvm_unreachable("AMDGPUInstructionSelector does not support simple predicates!");
  return false;
}
// Custom renderers.
enum {
  GICR_Invalid,
  GICR_renderBitcastImm,
  GICR_renderExtractCPol,
  GICR_renderExtractCpolSetGLC,
  GICR_renderExtractSWZ,
  GICR_renderFPPow2ToExponent,
  GICR_renderFrameIndex,
  GICR_renderNegateImm,
  GICR_renderOpSelTImm,
  GICR_renderPopcntImm,
  GICR_renderTruncTImm,
};
AMDGPUInstructionSelector::CustomRendererFn
AMDGPUInstructionSelector::CustomRenderers[] = {
  nullptr, // GICR_Invalid
  &AMDGPUInstructionSelector::renderBitcastImm,
  &AMDGPUInstructionSelector::renderExtractCPol,
  &AMDGPUInstructionSelector::renderExtractCpolSetGLC,
  &AMDGPUInstructionSelector::renderExtractSWZ,
  &AMDGPUInstructionSelector::renderFPPow2ToExponent,
  &AMDGPUInstructionSelector::renderFrameIndex,
  &AMDGPUInstructionSelector::renderNegateImm,
  &AMDGPUInstructionSelector::renderOpSelTImm,
  &AMDGPUInstructionSelector::renderPopcntImm,
  &AMDGPUInstructionSelector::renderTruncTImm,
};

bool AMDGPUInstructionSelector::selectImpl(MachineInstr &I, CodeGenCoverage &CoverageInfo) const {
  const PredicateBitset AvailableFeatures = getAvailableFeatures();
  MachineIRBuilder B(I);
  State.MIs.clear();
  State.MIs.push_back(&I);

  if (executeMatchTable(*this, State, ExecInfo, B, getMatchTable(), TII, MF->getRegInfo(), TRI, RBI, AvailableFeatures, &CoverageInfo)) {
    return true;
  }

  return false;
}

void AMDGPUInstructionSelector::runCustomAction(unsigned, const MatcherState&, NewMIVector &) const {
    llvm_unreachable("AMDGPUInstructionSelector does not support custom C++ actions!");
}
#if __BYTE_ORDER__ == __ORDER_LITTLE_ENDIAN__
#define GIMT_Encode2(Val) uint8_t(Val), uint8_t((uint16_t)Val >> 8)
#define GIMT_Encode4(Val) uint8_t(Val), uint8_t((uint32_t)Val >> 8), uint8_t((uint32_t)Val >> 16), uint8_t((uint32_t)Val >> 24)
#define GIMT_Encode8(Val) uint8_t(Val), uint8_t((uint64_t)Val >> 8), uint8_t((uint64_t)Val >> 16), uint8_t((uint64_t)Val >> 24),  uint8_t((uint64_t)Val >> 32), uint8_t((uint64_t)Val >> 40), uint8_t((uint64_t)Val >> 48), uint8_t((uint64_t)Val >> 56)
#else
#define GIMT_Encode2(Val) uint8_t((uint16_t)Val >> 8), uint8_t(Val)
#define GIMT_Encode4(Val) uint8_t((uint32_t)Val >> 24), uint8_t((uint32_t)Val >> 16), uint8_t((uint32_t)Val >> 8), uint8_t(Val)
#define GIMT_Encode8(Val) uint8_t((uint64_t)Val >> 56), uint8_t((uint64_t)Val >> 48), uint8_t((uint64_t)Val >> 40), uint8_t((uint64_t)Val >> 32),  uint8_t((uint64_t)Val >> 24), uint8_t((uint64_t)Val >> 16), uint8_t((uint64_t)Val >> 8), uint8_t(Val)
#endif
const uint8_t *AMDGPUInstructionSelector::getMatchTable() const {
  constexpr static uint8_t MatchTable0[] = {
    GIM_SwitchOpcode, /*MI*/0, /*[*/GIMT_Encode2(47), GIMT_Encode2(3679), /*)*//*default:*//*Label 162*/ GIMT_Encode4(549501),
    /*TargetOpcode::G_ADD*//*Label 0*/ GIMT_Encode4(14538),
    /*TargetOpcode::G_SUB*//*Label 1*/ GIMT_Encode4(17047),
    /*TargetOpcode::G_MUL*//*Label 2*/ GIMT_Encode4(17634), GIMT_Encode4(0), GIMT_Encode4(0), GIMT_Encode4(0), GIMT_Encode4(0), GIMT_Encode4(0), GIMT_Encode4(0),
    /*TargetOpcode::G_AND*//*Label 3*/ GIMT_Encode4(17960),
    /*TargetOpcode::G_OR*//*Label 4*/ GIMT_Encode4(19110),
    /*TargetOpcode::G_XOR*//*Label 5*/ GIMT_Encode4(34374), GIMT_Encode4(0), GIMT_Encode4(0),
    /*TargetOpcode::G_FRAME_INDEX*//*Label 6*/ GIMT_Encode4(39050), GIMT_Encode4(0), GIMT_Encode4(0), GIMT_Encode4(0), GIMT_Encode4(0), GIMT_Encode4(0), GIMT_Encode4(0),
    /*TargetOpcode::G_BUILD_VECTOR*//*Label 7*/ GIMT_Encode4(39117), GIMT_Encode4(0), GIMT_Encode4(0), GIMT_Encode4(0), GIMT_Encode4(0),
    /*TargetOpcode::G_BITCAST*//*Label 8*/ GIMT_Encode4(41817), GIMT_Encode4(0), GIMT_Encode4(0), GIMT_Encode4(0),
    /*TargetOpcode::G_INTRINSIC_TRUNC*//*Label 9*/ GIMT_Encode4(53148), GIMT_Encode4(0), GIMT_Encode4(0),
    /*TargetOpcode::G_INTRINSIC_ROUNDEVEN*//*Label 10*/ GIMT_Encode4(53519),
    /*TargetOpcode::G_READCYCLECOUNTER*//*Label 11*/ GIMT_Encode4(53890),
    /*TargetOpcode::G_LOAD*//*Label 12*/ GIMT_Encode4(54042),
    /*TargetOpcode::G_SEXTLOAD*//*Label 13*/ GIMT_Encode4(109905),
    /*TargetOpcode::G_ZEXTLOAD*//*Label 14*/ GIMT_Encode4(114297), GIMT_Encode4(0), GIMT_Encode4(0), GIMT_Encode4(0),
    /*TargetOpcode::G_STORE*//*Label 15*/ GIMT_Encode4(118551), GIMT_Encode4(0), GIMT_Encode4(0),
    /*TargetOpcode::G_ATOMIC_CMPXCHG*//*Label 16*/ GIMT_Encode4(157753),
    /*TargetOpcode::G_ATOMICRMW_XCHG*//*Label 17*/ GIMT_Encode4(159073),
    /*TargetOpcode::G_ATOMICRMW_ADD*//*Label 18*/ GIMT_Encode4(161581),
    /*TargetOpcode::G_ATOMICRMW_SUB*//*Label 19*/ GIMT_Encode4(164425),
    /*TargetOpcode::G_ATOMICRMW_AND*//*Label 20*/ GIMT_Encode4(167269), GIMT_Encode4(0),
    /*TargetOpcode::G_ATOMICRMW_OR*//*Label 21*/ GIMT_Encode4(170113),
    /*TargetOpcode::G_ATOMICRMW_XOR*//*Label 22*/ GIMT_Encode4(172957),
    /*TargetOpcode::G_ATOMICRMW_MAX*//*Label 23*/ GIMT_Encode4(175801),
    /*TargetOpcode::G_ATOMICRMW_MIN*//*Label 24*/ GIMT_Encode4(178645),
    /*TargetOpcode::G_ATOMICRMW_UMAX*//*Label 25*/ GIMT_Encode4(181489),
    /*TargetOpcode::G_ATOMICRMW_UMIN*//*Label 26*/ GIMT_Encode4(184333),
    /*TargetOpcode::G_ATOMICRMW_FADD*//*Label 27*/ GIMT_Encode4(187177), GIMT_Encode4(0), GIMT_Encode4(0), GIMT_Encode4(0),
    /*TargetOpcode::G_ATOMICRMW_UINC_WRAP*//*Label 28*/ GIMT_Encode4(188586),
    /*TargetOpcode::G_ATOMICRMW_UDEC_WRAP*//*Label 29*/ GIMT_Encode4(191430),
    /*TargetOpcode::G_FENCE*//*Label 30*/ GIMT_Encode4(194274),
    /*TargetOpcode::G_PREFETCH*//*Label 31*/ GIMT_Encode4(194294), GIMT_Encode4(0), GIMT_Encode4(0), GIMT_Encode4(0),
    /*TargetOpcode::G_INTRINSIC*//*Label 32*/ GIMT_Encode4(194762),
    /*TargetOpcode::G_INTRINSIC_W_SIDE_EFFECTS*//*Label 33*/ GIMT_Encode4(209911),
    /*TargetOpcode::G_INTRINSIC_CONVERGENT*//*Label 34*/ GIMT_Encode4(220671),
    /*TargetOpcode::G_INTRINSIC_CONVERGENT_W_SIDE_EFFECTS*//*Label 35*/ GIMT_Encode4(238120),
    /*TargetOpcode::G_ANYEXT*//*Label 36*/ GIMT_Encode4(239534),
    /*TargetOpcode::G_TRUNC*//*Label 37*/ GIMT_Encode4(239906),
    /*TargetOpcode::G_CONSTANT*//*Label 38*/ GIMT_Encode4(240046),
    /*TargetOpcode::G_FCONSTANT*//*Label 39*/ GIMT_Encode4(240181), GIMT_Encode4(0), GIMT_Encode4(0),
    /*TargetOpcode::G_SEXT*//*Label 40*/ GIMT_Encode4(240288), GIMT_Encode4(0),
    /*TargetOpcode::G_ZEXT*//*Label 41*/ GIMT_Encode4(240904),
    /*TargetOpcode::G_SHL*//*Label 42*/ GIMT_Encode4(242578),
    /*TargetOpcode::G_LSHR*//*Label 43*/ GIMT_Encode4(243994),
    /*TargetOpcode::G_ASHR*//*Label 44*/ GIMT_Encode4(245126), GIMT_Encode4(0),
    /*TargetOpcode::G_FSHR*//*Label 45*/ GIMT_Encode4(246258),
    /*TargetOpcode::G_ROTR*//*Label 46*/ GIMT_Encode4(246318), GIMT_Encode4(0),
    /*TargetOpcode::G_ICMP*//*Label 47*/ GIMT_Encode4(246366),
    /*TargetOpcode::G_FCMP*//*Label 48*/ GIMT_Encode4(247799),
    /*TargetOpcode::G_SELECT*//*Label 49*/ GIMT_Encode4(251437), GIMT_Encode4(0), GIMT_Encode4(0), GIMT_Encode4(0), GIMT_Encode4(0), GIMT_Encode4(0), GIMT_Encode4(0), GIMT_Encode4(0), GIMT_Encode4(0), GIMT_Encode4(0), GIMT_Encode4(0),
    /*TargetOpcode::G_UMULH*//*Label 50*/ GIMT_Encode4(251689),
    /*TargetOpcode::G_SMULH*//*Label 51*/ GIMT_Encode4(251822),
    /*TargetOpcode::G_UADDSAT*//*Label 52*/ GIMT_Encode4(251955),
    /*TargetOpcode::G_SADDSAT*//*Label 53*/ GIMT_Encode4(252272),
    /*TargetOpcode::G_USUBSAT*//*Label 54*/ GIMT_Encode4(252505),
    /*TargetOpcode::G_SSUBSAT*//*Label 55*/ GIMT_Encode4(252822), GIMT_Encode4(0), GIMT_Encode4(0), GIMT_Encode4(0), GIMT_Encode4(0), GIMT_Encode4(0), GIMT_Encode4(0), GIMT_Encode4(0), GIMT_Encode4(0), GIMT_Encode4(0), GIMT_Encode4(0),
    /*TargetOpcode::G_FADD*//*Label 56*/ GIMT_Encode4(253055),
    /*TargetOpcode::G_FSUB*//*Label 57*/ GIMT_Encode4(254618),
    /*TargetOpcode::G_FMUL*//*Label 58*/ GIMT_Encode4(255023),
    /*TargetOpcode::G_FMA*//*Label 59*/ GIMT_Encode4(256630),
    /*TargetOpcode::G_FMAD*//*Label 60*/ GIMT_Encode4(258427), GIMT_Encode4(0), GIMT_Encode4(0),
    /*TargetOpcode::G_FPOW*//*Label 61*/ GIMT_Encode4(259453), GIMT_Encode4(0), GIMT_Encode4(0),
    /*TargetOpcode::G_FEXP2*//*Label 62*/ GIMT_Encode4(259581), GIMT_Encode4(0), GIMT_Encode4(0),
    /*TargetOpcode::G_FLOG2*//*Label 63*/ GIMT_Encode4(259832), GIMT_Encode4(0),
    /*TargetOpcode::G_FLDEXP*//*Label 64*/ GIMT_Encode4(260083), GIMT_Encode4(0),
    /*TargetOpcode::G_FNEG*//*Label 65*/ GIMT_Encode4(260409),
    /*TargetOpcode::G_FPEXT*//*Label 66*/ GIMT_Encode4(261815),
    /*TargetOpcode::G_FPTRUNC*//*Label 67*/ GIMT_Encode4(262156),
    /*TargetOpcode::G_FPTOSI*//*Label 68*/ GIMT_Encode4(262847),
    /*TargetOpcode::G_FPTOUI*//*Label 69*/ GIMT_Encode4(263492),
    /*TargetOpcode::G_SITOFP*//*Label 70*/ GIMT_Encode4(264137),
    /*TargetOpcode::G_UITOFP*//*Label 71*/ GIMT_Encode4(264769),
    /*TargetOpcode::G_FABS*//*Label 72*/ GIMT_Encode4(265401),
    /*TargetOpcode::G_FCOPYSIGN*//*Label 73*/ GIMT_Encode4(265995),
    /*TargetOpcode::G_IS_FPCLASS*//*Label 74*/ GIMT_Encode4(266640),
    /*TargetOpcode::G_FCANONICALIZE*//*Label 75*/ GIMT_Encode4(266937),
    /*TargetOpcode::G_FMINNUM*//*Label 76*/ GIMT_Encode4(268273),
    /*TargetOpcode::G_FMAXNUM*//*Label 77*/ GIMT_Encode4(288084),
    /*TargetOpcode::G_FMINNUM_IEEE*//*Label 78*/ GIMT_Encode4(326583),
    /*TargetOpcode::G_FMAXNUM_IEEE*//*Label 79*/ GIMT_Encode4(346394),
    /*TargetOpcode::G_FMINIMUM*//*Label 80*/ GIMT_Encode4(384893),
    /*TargetOpcode::G_FMAXIMUM*//*Label 81*/ GIMT_Encode4(385993), GIMT_Encode4(0), GIMT_Encode4(0), GIMT_Encode4(0),
    /*TargetOpcode::G_GET_FPMODE*//*Label 82*/ GIMT_Encode4(387093), GIMT_Encode4(0), GIMT_Encode4(0),
    /*TargetOpcode::G_PTR_ADD*//*Label 83*/ GIMT_Encode4(387231), GIMT_Encode4(0),
    /*TargetOpcode::G_SMIN*//*Label 84*/ GIMT_Encode4(387320),
    /*TargetOpcode::G_SMAX*//*Label 85*/ GIMT_Encode4(390802),
    /*TargetOpcode::G_UMIN*//*Label 86*/ GIMT_Encode4(394482),
    /*TargetOpcode::G_UMAX*//*Label 87*/ GIMT_Encode4(397964),
    /*TargetOpcode::G_ABS*//*Label 88*/ GIMT_Encode4(401446), GIMT_Encode4(0), GIMT_Encode4(0),
    /*TargetOpcode::G_BR*//*Label 89*/ GIMT_Encode4(401605), GIMT_Encode4(0), GIMT_Encode4(0), GIMT_Encode4(0), GIMT_Encode4(0), GIMT_Encode4(0),
    /*TargetOpcode::G_CTTZ_ZERO_UNDEF*//*Label 90*/ GIMT_Encode4(401641), GIMT_Encode4(0),
    /*TargetOpcode::G_CTLZ_ZERO_UNDEF*//*Label 91*/ GIMT_Encode4(401752),
    /*TargetOpcode::G_CTPOP*//*Label 92*/ GIMT_Encode4(401867),
    /*TargetOpcode::G_BSWAP*//*Label 93*/ GIMT_Encode4(401993),
    /*TargetOpcode::G_BITREVERSE*//*Label 94*/ GIMT_Encode4(402988),
    /*TargetOpcode::G_FCEIL*//*Label 95*/ GIMT_Encode4(403255), GIMT_Encode4(0), GIMT_Encode4(0),
    /*TargetOpcode::G_FSQRT*//*Label 96*/ GIMT_Encode4(403626),
    /*TargetOpcode::G_FFLOOR*//*Label 97*/ GIMT_Encode4(403955), GIMT_Encode4(0), GIMT_Encode4(0), GIMT_Encode4(0), GIMT_Encode4(0), GIMT_Encode4(0), GIMT_Encode4(0), GIMT_Encode4(0), GIMT_Encode4(0),
    /*TargetOpcode::G_STRICT_FADD*//*Label 98*/ GIMT_Encode4(404518),
    /*TargetOpcode::G_STRICT_FSUB*//*Label 99*/ GIMT_Encode4(405657),
    /*TargetOpcode::G_STRICT_FMUL*//*Label 100*/ GIMT_Encode4(406062), GIMT_Encode4(0), GIMT_Encode4(0),
    /*TargetOpcode::G_STRICT_FMA*//*Label 101*/ GIMT_Encode4(407539), GIMT_Encode4(0),
    /*TargetOpcode::G_STRICT_FLDEXP*//*Label 102*/ GIMT_Encode4(408514), GIMT_Encode4(0), GIMT_Encode4(0), GIMT_Encode4(0), GIMT_Encode4(0), GIMT_Encode4(0), GIMT_Encode4(0), GIMT_Encode4(0), GIMT_Encode4(0), GIMT_Encode4(0), GIMT_Encode4(0), GIMT_Encode4(0), GIMT_Encode4(0), GIMT_Encode4(0), GIMT_Encode4(0), GIMT_Encode4(0), GIMT_Encode4(0), GIMT_Encode4(0), GIMT_Encode4(0), GIMT_Encode4(0), GIMT_Encode4(0), GIMT_Encode4(0), GIMT_Encode4(0), GIMT_Encode4(0), GIMT_Encode4(0), GIMT_Encode4(0), GIMT_Encode4(0), GIMT_Encode4(0), GIMT_Encode4(0), GIMT_Encode4(0), GIMT_Encode4(0), GIMT_Encode4(0), GIMT_Encode4(0), GIMT_Encode4(0), GIMT_Encode4(0), GIMT_Encode4(0), GIMT_Encode4(0), GIMT_Encode4(0), GIMT_Encode4(0), GIMT_Encode4(0), GIMT_Encode4(0), GIMT_Encode4(0), GIMT_Encode4(0), GIMT_Encode4(0), GIMT_Encode4(0), GIMT_Encode4(0), GIMT_Encode4(0), GIMT_Encode4(0), GIMT_Encode4(0), GIMT_Encode4(0), GIMT_Encode4(0), GIMT_Encode4(0), GIMT_Encode4(0), GIMT_Encode4(0), GIMT_Encode4(0), GIMT_Encode4(0), GIMT_Encode4(0), GIMT_Encode4(0), GIMT_Encode4(0), GIMT_Encode4(0), GIMT_Encode4(0), GIMT_Encode4(0), GIMT_Encode4(0), GIMT_Encode4(0), GIMT_Encode4(0), GIMT_Encode4(0), GIMT_Encode4(0), GIMT_Encode4(0), GIMT_Encode4(0), GIMT_Encode4(0), GIMT_Encode4(0), GIMT_Encode4(0), GIMT_Encode4(0), GIMT_Encode4(0), GIMT_Encode4(0), GIMT_Encode4(0), GIMT_Encode4(0), GIMT_Encode4(0), GIMT_Encode4(0), GIMT_Encode4(0), GIMT_Encode4(0), GIMT_Encode4(0), GIMT_Encode4(0), GIMT_Encode4(0), GIMT_Encode4(0), GIMT_Encode4(0), GIMT_Encode4(0), GIMT_Encode4(0), GIMT_Encode4(0), GIMT_Encode4(0), GIMT_Encode4(0), GIMT_Encode4(0), GIMT_Encode4(0), GIMT_Encode4(0), GIMT_Encode4(0), GIMT_Encode4(0), GIMT_Encode4(0), GIMT_Encode4(0), GIMT_Encode4(0), GIMT_Encode4(0), GIMT_Encode4(0), GIMT_Encode4(0), GIMT_Encode4(0), GIMT_Encode4(0), GIMT_Encode4(0), GIMT_Encode4(0), GIMT_Encode4(0), GIMT_Encode4(0), GIMT_Encode4(0), GIMT_Encode4(0), GIMT_Encode4(0), GIMT_Encode4(0), GIMT_Encode4(0), GIMT_Encode4(0), GIMT_Encode4(0), GIMT_Encode4(0), GIMT_Encode4(0), GIMT_Encode4(0), GIMT_Encode4(0), GIMT_Encode4(0), GIMT_Encode4(0), GIMT_Encode4(0), GIMT_Encode4(0), GIMT_Encode4(0), GIMT_Encode4(0), GIMT_Encode4(0), GIMT_Encode4(0), GIMT_Encode4(0), GIMT_Encode4(0), GIMT_Encode4(0), GIMT_Encode4(0), GIMT_Encode4(0), GIMT_Encode4(0), GIMT_Encode4(0), GIMT_Encode4(0), GIMT_Encode4(0), GIMT_Encode4(0), GIMT_Encode4(0), GIMT_Encode4(0), GIMT_Encode4(0), GIMT_Encode4(0), GIMT_Encode4(0), GIMT_Encode4(0), GIMT_Encode4(0), GIMT_Encode4(0), GIMT_Encode4(0), GIMT_Encode4(0), GIMT_Encode4(0), GIMT_Encode4(0), GIMT_Encode4(0), GIMT_Encode4(0), GIMT_Encode4(0), GIMT_Encode4(0), GIMT_Encode4(0), GIMT_Encode4(0), GIMT_Encode4(0), GIMT_Encode4(0), GIMT_Encode4(0), GIMT_Encode4(0), GIMT_Encode4(0), GIMT_Encode4(0), GIMT_Encode4(0), GIMT_Encode4(0), GIMT_Encode4(0), GIMT_Encode4(0), GIMT_Encode4(0), GIMT_Encode4(0), GIMT_Encode4(0), GIMT_Encode4(0), GIMT_Encode4(0), GIMT_Encode4(0), GIMT_Encode4(0), GIMT_Encode4(0), GIMT_Encode4(0), GIMT_Encode4(0), GIMT_Encode4(0), GIMT_Encode4(0), GIMT_Encode4(0), GIMT_Encode4(0), GIMT_Encode4(0), GIMT_Encode4(0), GIMT_Encode4(0), GIMT_Encode4(0), GIMT_Encode4(0), GIMT_Encode4(0), GIMT_Encode4(0), GIMT_Encode4(0), GIMT_Encode4(0), GIMT_Encode4(0), GIMT_Encode4(0), GIMT_Encode4(0), GIMT_Encode4(0), GIMT_Encode4(0), GIMT_Encode4(0), GIMT_Encode4(0), GIMT_Encode4(0), GIMT_Encode4(0), GIMT_Encode4(0), GIMT_Encode4(0), GIMT_Encode4(0), GIMT_Encode4(0), GIMT_Encode4(0), GIMT_Encode4(0), GIMT_Encode4(0), GIMT_Encode4(0), GIMT_Encode4(0), GIMT_Encode4(0), GIMT_Encode4(0), GIMT_Encode4(0), GIMT_Encode4(0), GIMT_Encode4(0), GIMT_Encode4(0), GIMT_Encode4(0), GIMT_Encode4(0), GIMT_Encode4(0), GIMT_Encode4(0), GIMT_Encode4(0), GIMT_Encode4(0), GIMT_Encode4(0), GIMT_Encode4(0), GIMT_Encode4(0), GIMT_Encode4(0), GIMT_Encode4(0), GIMT_Encode4(0), GIMT_Encode4(0), GIMT_Encode4(0), GIMT_Encode4(0), GIMT_Encode4(0), GIMT_Encode4(0), GIMT_Encode4(0), GIMT_Encode4(0), GIMT_Encode4(0), GIMT_Encode4(0), GIMT_Encode4(0), GIMT_Encode4(0), GIMT_Encode4(0), GIMT_Encode4(0), GIMT_Encode4(0), GIMT_Encode4(0), GIMT_Encode4(0), GIMT_Encode4(0), GIMT_Encode4(0), GIMT_Encode4(0), GIMT_Encode4(0), GIMT_Encode4(0), GIMT_Encode4(0), GIMT_Encode4(0), GIMT_Encode4(0), GIMT_Encode4(0), GIMT_Encode4(0), GIMT_Encode4(0), GIMT_Encode4(0), GIMT_Encode4(0), GIMT_Encode4(0), GIMT_Encode4(0), GIMT_Encode4(0), GIMT_Encode4(0), GIMT_Encode4(0), GIMT_Encode4(0), GIMT_Encode4(0), GIMT_Encode4(0), GIMT_Encode4(0), GIMT_Encode4(0), GIMT_Encode4(0), GIMT_Encode4(0), GIMT_Encode4(0), GIMT_Encode4(0), GIMT_Encode4(0), GIMT_Encode4(0), GIMT_Encode4(0), GIMT_Encode4(0), GIMT_Encode4(0), GIMT_Encode4(0), GIMT_Encode4(0), GIMT_Encode4(0), GIMT_Encode4(0), GIMT_Encode4(0), GIMT_Encode4(0), GIMT_Encode4(0), GIMT_Encode4(0), GIMT_Encode4(0), GIMT_Encode4(0), GIMT_Encode4(0), GIMT_Encode4(0), GIMT_Encode4(0), GIMT_Encode4(0), GIMT_Encode4(0), GIMT_Encode4(0), GIMT_Encode4(0), GIMT_Encode4(0), GIMT_Encode4(0), GIMT_Encode4(0), GIMT_Encode4(0), GIMT_Encode4(0), GIMT_Encode4(0), GIMT_Encode4(0), GIMT_Encode4(0), GIMT_Encode4(0), GIMT_Encode4(0), GIMT_Encode4(0), GIMT_Encode4(0), GIMT_Encode4(0), GIMT_Encode4(0), GIMT_Encode4(0), GIMT_Encode4(0), GIMT_Encode4(0), GIMT_Encode4(0), GIMT_Encode4(0), GIMT_Encode4(0), GIMT_Encode4(0), GIMT_Encode4(0), GIMT_Encode4(0), GIMT_Encode4(0), GIMT_Encode4(0), GIMT_Encode4(0), GIMT_Encode4(0), GIMT_Encode4(0), GIMT_Encode4(0), GIMT_Encode4(0), GIMT_Encode4(0), GIMT_Encode4(0), GIMT_Encode4(0), GIMT_Encode4(0), GIMT_Encode4(0), GIMT_Encode4(0), GIMT_Encode4(0), GIMT_Encode4(0), GIMT_Encode4(0), GIMT_Encode4(0), GIMT_Encode4(0), GIMT_Encode4(0), GIMT_Encode4(0), GIMT_Encode4(0), GIMT_Encode4(0), GIMT_Encode4(0), GIMT_Encode4(0), GIMT_Encode4(0), GIMT_Encode4(0), GIMT_Encode4(0), GIMT_Encode4(0), GIMT_Encode4(0), GIMT_Encode4(0), GIMT_Encode4(0), GIMT_Encode4(0), GIMT_Encode4(0), GIMT_Encode4(0), GIMT_Encode4(0), GIMT_Encode4(0), GIMT_Encode4(0), GIMT_Encode4(0), GIMT_Encode4(0), GIMT_Encode4(0), GIMT_Encode4(0), GIMT_Encode4(0), GIMT_Encode4(0), GIMT_Encode4(0), GIMT_Encode4(0), GIMT_Encode4(0), GIMT_Encode4(0), GIMT_Encode4(0), GIMT_Encode4(0), GIMT_Encode4(0), GIMT_Encode4(0), GIMT_Encode4(0), GIMT_Encode4(0), GIMT_Encode4(0), GIMT_Encode4(0), GIMT_Encode4(0), GIMT_Encode4(0), GIMT_Encode4(0), GIMT_Encode4(0), GIMT_Encode4(0), GIMT_Encode4(0), GIMT_Encode4(0), GIMT_Encode4(0), GIMT_Encode4(0), GIMT_Encode4(0), GIMT_Encode4(0), GIMT_Encode4(0), GIMT_Encode4(0), GIMT_Encode4(0), GIMT_Encode4(0), GIMT_Encode4(0), GIMT_Encode4(0), GIMT_Encode4(0), GIMT_Encode4(0), GIMT_Encode4(0), GIMT_Encode4(0), GIMT_Encode4(0), GIMT_Encode4(0), GIMT_Encode4(0), GIMT_Encode4(0), GIMT_Encode4(0), GIMT_Encode4(0), GIMT_Encode4(0), GIMT_Encode4(0), GIMT_Encode4(0), GIMT_Encode4(0), GIMT_Encode4(0), GIMT_Encode4(0), GIMT_Encode4(0), GIMT_Encode4(0), GIMT_Encode4(0), GIMT_Encode4(0), GIMT_Encode4(0), GIMT_Encode4(0), GIMT_Encode4(0), GIMT_Encode4(0), GIMT_Encode4(0), GIMT_Encode4(0), GIMT_Encode4(0), GIMT_Encode4(0), GIMT_Encode4(0), GIMT_Encode4(0), GIMT_Encode4(0), GIMT_Encode4(0), GIMT_Encode4(0), GIMT_Encode4(0), GIMT_Encode4(0), GIMT_Encode4(0), GIMT_Encode4(0), GIMT_Encode4(0), GIMT_Encode4(0), GIMT_Encode4(0), GIMT_Encode4(0), GIMT_Encode4(0), GIMT_Encode4(0), GIMT_Encode4(0), GIMT_Encode4(0), GIMT_Encode4(0), GIMT_Encode4(0), GIMT_Encode4(0), GIMT_Encode4(0), GIMT_Encode4(0), GIMT_Encode4(0), GIMT_Encode4(0), GIMT_Encode4(0), GIMT_Encode4(0), GIMT_Encode4(0), GIMT_Encode4(0), GIMT_Encode4(0), GIMT_Encode4(0), GIMT_Encode4(0), GIMT_Encode4(0), GIMT_Encode4(0), GIMT_Encode4(0), GIMT_Encode4(0), GIMT_Encode4(0), GIMT_Encode4(0), GIMT_Encode4(0), GIMT_Encode4(0), GIMT_Encode4(0), GIMT_Encode4(0), GIMT_Encode4(0), GIMT_Encode4(0), GIMT_Encode4(0), GIMT_Encode4(0), GIMT_Encode4(0), GIMT_Encode4(0), GIMT_Encode4(0), GIMT_Encode4(0), GIMT_Encode4(0), GIMT_Encode4(0), GIMT_Encode4(0), GIMT_Encode4(0), GIMT_Encode4(0), GIMT_Encode4(0), GIMT_Encode4(0), GIMT_Encode4(0), GIMT_Encode4(0), GIMT_Encode4(0), GIMT_Encode4(0), GIMT_Encode4(0), GIMT_Encode4(0), GIMT_Encode4(0), GIMT_Encode4(0), GIMT_Encode4(0), GIMT_Encode4(0), GIMT_Encode4(0), GIMT_Encode4(0), GIMT_Encode4(0), GIMT_Encode4(0), GIMT_Encode4(0), GIMT_Encode4(0), GIMT_Encode4(0), GIMT_Encode4(0), GIMT_Encode4(0), GIMT_Encode4(0), GIMT_Encode4(0), GIMT_Encode4(0), GIMT_Encode4(0), GIMT_Encode4(0), GIMT_Encode4(0), GIMT_Encode4(0), GIMT_Encode4(0), GIMT_Encode4(0), GIMT_Encode4(0), GIMT_Encode4(0), GIMT_Encode4(0), GIMT_Encode4(0), GIMT_Encode4(0), GIMT_Encode4(0), GIMT_Encode4(0), GIMT_Encode4(0), GIMT_Encode4(0), GIMT_Encode4(0), GIMT_Encode4(0), GIMT_Encode4(0), GIMT_Encode4(0), GIMT_Encode4(0), GIMT_Encode4(0), GIMT_Encode4(0), GIMT_Encode4(0), GIMT_Encode4(0), GIMT_Encode4(0), GIMT_Encode4(0), GIMT_Encode4(0), GIMT_Encode4(0), GIMT_Encode4(0), GIMT_Encode4(0), GIMT_Encode4(0), GIMT_Encode4(0), GIMT_Encode4(0), GIMT_Encode4(0), GIMT_Encode4(0), GIMT_Encode4(0), GIMT_Encode4(0), GIMT_Encode4(0), GIMT_Encode4(0), GIMT_Encode4(0), GIMT_Encode4(0), GIMT_Encode4(0), GIMT_Encode4(0), GIMT_Encode4(0), GIMT_Encode4(0), GIMT_Encode4(0), GIMT_Encode4(0), GIMT_Encode4(0), GIMT_Encode4(0), GIMT_Encode4(0), GIMT_Encode4(0), GIMT_Encode4(0), GIMT_Encode4(0), GIMT_Encode4(0), GIMT_Encode4(0), GIMT_Encode4(0), GIMT_Encode4(0), GIMT_Encode4(0), GIMT_Encode4(0), GIMT_Encode4(0), GIMT_Encode4(0), GIMT_Encode4(0), GIMT_Encode4(0), GIMT_Encode4(0), GIMT_Encode4(0), GIMT_Encode4(0), GIMT_Encode4(0), GIMT_Encode4(0), GIMT_Encode4(0), GIMT_Encode4(0), GIMT_Encode4(0), GIMT_Encode4(0), GIMT_Encode4(0), GIMT_Encode4(0), GIMT_Encode4(0), GIMT_Encode4(0), GIMT_Encode4(0), GIMT_Encode4(0), GIMT_Encode4(0), GIMT_Encode4(0), GIMT_Encode4(0), GIMT_Encode4(0), GIMT_Encode4(0), GIMT_Encode4(0), GIMT_Encode4(0), GIMT_Encode4(0), GIMT_Encode4(0), GIMT_Encode4(0), GIMT_Encode4(0), GIMT_Encode4(0), GIMT_Encode4(0), GIMT_Encode4(0), GIMT_Encode4(0), GIMT_Encode4(0), GIMT_Encode4(0), GIMT_Encode4(0), GIMT_Encode4(0), GIMT_Encode4(0), GIMT_Encode4(0), GIMT_Encode4(0), GIMT_Encode4(0), GIMT_Encode4(0), GIMT_Encode4(0), GIMT_Encode4(0), GIMT_Encode4(0), GIMT_Encode4(0), GIMT_Encode4(0), GIMT_Encode4(0), GIMT_Encode4(0), GIMT_Encode4(0), GIMT_Encode4(0), GIMT_Encode4(0), GIMT_Encode4(0), GIMT_Encode4(0), GIMT_Encode4(0), GIMT_Encode4(0), GIMT_Encode4(0), GIMT_Encode4(0), GIMT_Encode4(0), GIMT_Encode4(0), GIMT_Encode4(0), GIMT_Encode4(0), GIMT_Encode4(0), GIMT_Encode4(0), GIMT_Encode4(0), GIMT_Encode4(0), GIMT_Encode4(0), GIMT_Encode4(0), GIMT_Encode4(0), GIMT_Encode4(0), GIMT_Encode4(0), GIMT_Encode4(0), GIMT_Encode4(0), GIMT_Encode4(0), GIMT_Encode4(0), GIMT_Encode4(0), GIMT_Encode4(0), GIMT_Encode4(0), GIMT_Encode4(0), GIMT_Encode4(0), GIMT_Encode4(0), GIMT_Encode4(0), GIMT_Encode4(0), GIMT_Encode4(0), GIMT_Encode4(0), GIMT_Encode4(0), GIMT_Encode4(0), GIMT_Encode4(0), GIMT_Encode4(0), GIMT_Encode4(0), GIMT_Encode4(0), GIMT_Encode4(0), GIMT_Encode4(0), GIMT_Encode4(0), GIMT_Encode4(0), GIMT_Encode4(0), GIMT_Encode4(0), GIMT_Encode4(0), GIMT_Encode4(0), GIMT_Encode4(0), GIMT_Encode4(0), GIMT_Encode4(0), GIMT_Encode4(0), GIMT_Encode4(0), GIMT_Encode4(0), GIMT_Encode4(0), GIMT_Encode4(0), GIMT_Encode4(0), GIMT_Encode4(0), GIMT_Encode4(0), GIMT_Encode4(0), GIMT_Encode4(0), GIMT_Encode4(0), GIMT_Encode4(0), GIMT_Encode4(0), GIMT_Encode4(0), GIMT_Encode4(0), GIMT_Encode4(0), GIMT_Encode4(0), GIMT_Encode4(0), GIMT_Encode4(0), GIMT_Encode4(0), GIMT_Encode4(0), GIMT_Encode4(0), GIMT_Encode4(0), GIMT_Encode4(0), GIMT_Encode4(0), GIMT_Encode4(0), GIMT_Encode4(0), GIMT_Encode4(0), GIMT_Encode4(0), GIMT_Encode4(0), GIMT_Encode4(0), GIMT_Encode4(0), GIMT_Encode4(0), GIMT_Encode4(0), GIMT_Encode4(0), GIMT_Encode4(0), GIMT_Encode4(0), GIMT_Encode4(0), GIMT_Encode4(0), GIMT_Encode4(0), GIMT_Encode4(0), GIMT_Encode4(0), GIMT_Encode4(0), GIMT_Encode4(0), GIMT_Encode4(0), GIMT_Encode4(0), GIMT_Encode4(0), GIMT_Encode4(0), GIMT_Encode4(0), GIMT_Encode4(0), GIMT_Encode4(0), GIMT_Encode4(0), GIMT_Encode4(0), GIMT_Encode4(0), GIMT_Encode4(0), GIMT_Encode4(0), GIMT_Encode4(0), GIMT_Encode4(0), GIMT_Encode4(0), GIMT_Encode4(0), GIMT_Encode4(0), GIMT_Encode4(0), GIMT_Encode4(0), GIMT_Encode4(0), GIMT_Encode4(0), GIMT_Encode4(0), GIMT_Encode4(0), GIMT_Encode4(0), GIMT_Encode4(0), GIMT_Encode4(0), GIMT_Encode4(0), GIMT_Encode4(0), GIMT_Encode4(0), GIMT_Encode4(0), GIMT_Encode4(0), GIMT_Encode4(0), GIMT_Encode4(0), GIMT_Encode4(0), GIMT_Encode4(0), GIMT_Encode4(0), GIMT_Encode4(0), GIMT_Encode4(0), GIMT_Encode4(0), GIMT_Encode4(0), GIMT_Encode4(0), GIMT_Encode4(0), GIMT_Encode4(0), GIMT_Encode4(0), GIMT_Encode4(0), GIMT_Encode4(0), GIMT_Encode4(0), GIMT_Encode4(0), GIMT_Encode4(0), GIMT_Encode4(0), GIMT_Encode4(0), GIMT_Encode4(0), GIMT_Encode4(0), GIMT_Encode4(0), GIMT_Encode4(0), GIMT_Encode4(0), GIMT_Encode4(0), GIMT_Encode4(0), GIMT_Encode4(0), GIMT_Encode4(0), GIMT_Encode4(0), GIMT_Encode4(0), GIMT_Encode4(0), GIMT_Encode4(0), GIMT_Encode4(0), GIMT_Encode4(0), GIMT_Encode4(0), GIMT_Encode4(0), GIMT_Encode4(0), GIMT_Encode4(0), GIMT_Encode4(0), GIMT_Encode4(0), GIMT_Encode4(0), GIMT_Encode4(0), GIMT_Encode4(0), GIMT_Encode4(0), GIMT_Encode4(0), GIMT_Encode4(0), GIMT_Encode4(0), GIMT_Encode4(0), GIMT_Encode4(0), GIMT_Encode4(0), GIMT_Encode4(0), GIMT_Encode4(0), GIMT_Encode4(0), GIMT_Encode4(0), GIMT_Encode4(0), GIMT_Encode4(0), GIMT_Encode4(0), GIMT_Encode4(0), GIMT_Encode4(0), GIMT_Encode4(0), GIMT_Encode4(0), GIMT_Encode4(0), GIMT_Encode4(0), GIMT_Encode4(0), GIMT_Encode4(0), GIMT_Encode4(0), GIMT_Encode4(0), GIMT_Encode4(0), GIMT_Encode4(0), GIMT_Encode4(0), GIMT_Encode4(0), GIMT_Encode4(0), GIMT_Encode4(0), GIMT_Encode4(0), GIMT_Encode4(0), GIMT_Encode4(0), GIMT_Encode4(0), GIMT_Encode4(0), GIMT_Encode4(0), GIMT_Encode4(0), GIMT_Encode4(0), GIMT_Encode4(0), GIMT_Encode4(0), GIMT_Encode4(0), GIMT_Encode4(0), GIMT_Encode4(0), GIMT_Encode4(0), GIMT_Encode4(0), GIMT_Encode4(0), GIMT_Encode4(0), GIMT_Encode4(0), GIMT_Encode4(0), GIMT_Encode4(0), GIMT_Encode4(0), GIMT_Encode4(0), GIMT_Encode4(0), GIMT_Encode4(0), GIMT_Encode4(0), GIMT_Encode4(0), GIMT_Encode4(0), GIMT_Encode4(0), GIMT_Encode4(0), GIMT_Encode4(0), GIMT_Encode4(0), GIMT_Encode4(0), GIMT_Encode4(0), GIMT_Encode4(0), GIMT_Encode4(0), GIMT_Encode4(0), GIMT_Encode4(0), GIMT_Encode4(0), GIMT_Encode4(0), GIMT_Encode4(0), GIMT_Encode4(0), GIMT_Encode4(0), GIMT_Encode4(0), GIMT_Encode4(0), GIMT_Encode4(0), GIMT_Encode4(0), GIMT_Encode4(0), GIMT_Encode4(0), GIMT_Encode4(0), GIMT_Encode4(0), GIMT_Encode4(0), GIMT_Encode4(0), GIMT_Encode4(0), GIMT_Encode4(0), GIMT_Encode4(0), GIMT_Encode4(0), GIMT_Encode4(0), GIMT_Encode4(0), GIMT_Encode4(0), GIMT_Encode4(0), GIMT_Encode4(0), GIMT_Encode4(0), GIMT_Encode4(0), GIMT_Encode4(0), GIMT_Encode4(0), GIMT_Encode4(0), GIMT_Encode4(0), GIMT_Encode4(0), GIMT_Encode4(0), GIMT_Encode4(0), GIMT_Encode4(0), GIMT_Encode4(0), GIMT_Encode4(0), GIMT_Encode4(0), GIMT_Encode4(0), GIMT_Encode4(0), GIMT_Encode4(0), GIMT_Encode4(0), GIMT_Encode4(0), GIMT_Encode4(0), GIMT_Encode4(0), GIMT_Encode4(0), GIMT_Encode4(0), GIMT_Encode4(0), GIMT_Encode4(0), GIMT_Encode4(0), GIMT_Encode4(0), GIMT_Encode4(0), GIMT_Encode4(0), GIMT_Encode4(0), GIMT_Encode4(0), GIMT_Encode4(0), GIMT_Encode4(0), GIMT_Encode4(0), GIMT_Encode4(0), GIMT_Encode4(0), GIMT_Encode4(0), GIMT_Encode4(0), GIMT_Encode4(0), GIMT_Encode4(0), GIMT_Encode4(0), GIMT_Encode4(0), GIMT_Encode4(0), GIMT_Encode4(0), GIMT_Encode4(0), GIMT_Encode4(0), GIMT_Encode4(0), GIMT_Encode4(0), GIMT_Encode4(0), GIMT_Encode4(0), GIMT_Encode4(0), GIMT_Encode4(0), GIMT_Encode4(0), GIMT_Encode4(0), GIMT_Encode4(0), GIMT_Encode4(0), GIMT_Encode4(0), GIMT_Encode4(0), GIMT_Encode4(0), GIMT_Encode4(0), GIMT_Encode4(0), GIMT_Encode4(0), GIMT_Encode4(0), GIMT_Encode4(0), GIMT_Encode4(0), GIMT_Encode4(0), GIMT_Encode4(0), GIMT_Encode4(0), GIMT_Encode4(0), GIMT_Encode4(0), GIMT_Encode4(0), GIMT_Encode4(0), GIMT_Encode4(0), GIMT_Encode4(0), GIMT_Encode4(0), GIMT_Encode4(0), GIMT_Encode4(0), GIMT_Encode4(0), GIMT_Encode4(0), GIMT_Encode4(0), GIMT_Encode4(0), GIMT_Encode4(0), GIMT_Encode4(0), GIMT_Encode4(0), GIMT_Encode4(0), GIMT_Encode4(0), GIMT_Encode4(0), GIMT_Encode4(0), GIMT_Encode4(0), GIMT_Encode4(0), GIMT_Encode4(0), GIMT_Encode4(0), GIMT_Encode4(0), GIMT_Encode4(0), GIMT_Encode4(0), GIMT_Encode4(0), GIMT_Encode4(0), GIMT_Encode4(0), GIMT_Encode4(0), GIMT_Encode4(0), GIMT_Encode4(0), GIMT_Encode4(0), GIMT_Encode4(0), GIMT_Encode4(0), GIMT_Encode4(0), GIMT_Encode4(0), GIMT_Encode4(0), GIMT_Encode4(0), GIMT_Encode4(0), GIMT_Encode4(0), GIMT_Encode4(0), GIMT_Encode4(0), GIMT_Encode4(0), GIMT_Encode4(0), GIMT_Encode4(0), GIMT_Encode4(0), GIMT_Encode4(0), GIMT_Encode4(0), GIMT_Encode4(0), GIMT_Encode4(0), GIMT_Encode4(0), GIMT_Encode4(0), GIMT_Encode4(0), GIMT_Encode4(0), GIMT_Encode4(0), GIMT_Encode4(0), GIMT_Encode4(0), GIMT_Encode4(0), GIMT_Encode4(0), GIMT_Encode4(0), GIMT_Encode4(0), GIMT_Encode4(0), GIMT_Encode4(0), GIMT_Encode4(0), GIMT_Encode4(0), GIMT_Encode4(0), GIMT_Encode4(0), GIMT_Encode4(0), GIMT_Encode4(0), GIMT_Encode4(0), GIMT_Encode4(0), GIMT_Encode4(0), GIMT_Encode4(0), GIMT_Encode4(0), GIMT_Encode4(0), GIMT_Encode4(0), GIMT_Encode4(0), GIMT_Encode4(0), GIMT_Encode4(0), GIMT_Encode4(0), GIMT_Encode4(0), GIMT_Encode4(0), GIMT_Encode4(0), GIMT_Encode4(0), GIMT_Encode4(0), GIMT_Encode4(0), GIMT_Encode4(0), GIMT_Encode4(0), GIMT_Encode4(0), GIMT_Encode4(0), GIMT_Encode4(0), GIMT_Encode4(0), GIMT_Encode4(0), GIMT_Encode4(0), GIMT_Encode4(0), GIMT_Encode4(0), GIMT_Encode4(0), GIMT_Encode4(0), GIMT_Encode4(0), GIMT_Encode4(0), GIMT_Encode4(0), GIMT_Encode4(0), GIMT_Encode4(0), GIMT_Encode4(0), GIMT_Encode4(0), GIMT_Encode4(0), GIMT_Encode4(0), GIMT_Encode4(0), GIMT_Encode4(0), GIMT_Encode4(0), GIMT_Encode4(0), GIMT_Encode4(0), GIMT_Encode4(0), GIMT_Encode4(0), GIMT_Encode4(0), GIMT_Encode4(0), GIMT_Encode4(0), GIMT_Encode4(0), GIMT_Encode4(0), GIMT_Encode4(0), GIMT_Encode4(0), GIMT_Encode4(0), GIMT_Encode4(0), GIMT_Encode4(0), GIMT_Encode4(0), GIMT_Encode4(0), GIMT_Encode4(0), GIMT_Encode4(0), GIMT_Encode4(0), GIMT_Encode4(0), GIMT_Encode4(0), GIMT_Encode4(0), GIMT_Encode4(0), GIMT_Encode4(0), GIMT_Encode4(0), GIMT_Encode4(0), GIMT_Encode4(0), GIMT_Encode4(0), GIMT_Encode4(0), GIMT_Encode4(0), GIMT_Encode4(0), GIMT_Encode4(0), GIMT_Encode4(0), GIMT_Encode4(0), GIMT_Encode4(0), GIMT_Encode4(0), GIMT_Encode4(0), GIMT_Encode4(0), GIMT_Encode4(0), GIMT_Encode4(0), GIMT_Encode4(0), GIMT_Encode4(0), GIMT_Encode4(0), GIMT_Encode4(0), GIMT_Encode4(0), GIMT_Encode4(0), GIMT_Encode4(0), GIMT_Encode4(0), GIMT_Encode4(0), GIMT_Encode4(0), GIMT_Encode4(0), GIMT_Encode4(0), GIMT_Encode4(0), GIMT_Encode4(0), GIMT_Encode4(0), GIMT_Encode4(0), GIMT_Encode4(0), GIMT_Encode4(0), GIMT_Encode4(0), GIMT_Encode4(0), GIMT_Encode4(0), GIMT_Encode4(0), GIMT_Encode4(0), GIMT_Encode4(0), GIMT_Encode4(0), GIMT_Encode4(0), GIMT_Encode4(0), GIMT_Encode4(0), GIMT_Encode4(0), GIMT_Encode4(0), GIMT_Encode4(0), GIMT_Encode4(0), GIMT_Encode4(0), GIMT_Encode4(0), GIMT_Encode4(0), GIMT_Encode4(0), GIMT_Encode4(0), GIMT_Encode4(0), GIMT_Encode4(0), GIMT_Encode4(0), GIMT_Encode4(0), GIMT_Encode4(0), GIMT_Encode4(0), GIMT_Encode4(0), GIMT_Encode4(0), GIMT_Encode4(0), GIMT_Encode4(0), GIMT_Encode4(0), GIMT_Encode4(0), GIMT_Encode4(0), GIMT_Encode4(0), GIMT_Encode4(0), GIMT_Encode4(0), GIMT_Encode4(0), GIMT_Encode4(0), GIMT_Encode4(0), GIMT_Encode4(0), GIMT_Encode4(0), GIMT_Encode4(0), GIMT_Encode4(0), GIMT_Encode4(0), GIMT_Encode4(0), GIMT_Encode4(0), GIMT_Encode4(0), GIMT_Encode4(0), GIMT_Encode4(0), GIMT_Encode4(0), GIMT_Encode4(0), GIMT_Encode4(0), GIMT_Encode4(0), GIMT_Encode4(0), GIMT_Encode4(0), GIMT_Encode4(0), GIMT_Encode4(0), GIMT_Encode4(0), GIMT_Encode4(0), GIMT_Encode4(0), GIMT_Encode4(0), GIMT_Encode4(0), GIMT_Encode4(0), GIMT_Encode4(0), GIMT_Encode4(0), GIMT_Encode4(0), GIMT_Encode4(0), GIMT_Encode4(0), GIMT_Encode4(0), GIMT_Encode4(0), GIMT_Encode4(0), GIMT_Encode4(0), GIMT_Encode4(0), GIMT_Encode4(0), GIMT_Encode4(0), GIMT_Encode4(0), GIMT_Encode4(0), GIMT_Encode4(0), GIMT_Encode4(0), GIMT_Encode4(0), GIMT_Encode4(0), GIMT_Encode4(0), GIMT_Encode4(0), GIMT_Encode4(0), GIMT_Encode4(0), GIMT_Encode4(0), GIMT_Encode4(0), GIMT_Encode4(0), GIMT_Encode4(0), GIMT_Encode4(0), GIMT_Encode4(0), GIMT_Encode4(0), GIMT_Encode4(0), GIMT_Encode4(0), GIMT_Encode4(0), GIMT_Encode4(0), GIMT_Encode4(0), GIMT_Encode4(0), GIMT_Encode4(0), GIMT_Encode4(0), GIMT_Encode4(0), GIMT_Encode4(0), GIMT_Encode4(0), GIMT_Encode4(0), GIMT_Encode4(0), GIMT_Encode4(0), GIMT_Encode4(0), GIMT_Encode4(0), GIMT_Encode4(0), GIMT_Encode4(0), GIMT_Encode4(0), GIMT_Encode4(0), GIMT_Encode4(0), GIMT_Encode4(0), GIMT_Encode4(0), GIMT_Encode4(0), GIMT_Encode4(0), GIMT_Encode4(0), GIMT_Encode4(0), GIMT_Encode4(0), GIMT_Encode4(0), GIMT_Encode4(0), GIMT_Encode4(0), GIMT_Encode4(0), GIMT_Encode4(0), GIMT_Encode4(0), GIMT_Encode4(0), GIMT_Encode4(0), GIMT_Encode4(0), GIMT_Encode4(0), GIMT_Encode4(0), GIMT_Encode4(0), GIMT_Encode4(0), GIMT_Encode4(0), GIMT_Encode4(0), GIMT_Encode4(0), GIMT_Encode4(0), GIMT_Encode4(0), GIMT_Encode4(0), GIMT_Encode4(0), GIMT_Encode4(0), GIMT_Encode4(0), GIMT_Encode4(0), GIMT_Encode4(0), GIMT_Encode4(0), GIMT_Encode4(0), GIMT_Encode4(0), GIMT_Encode4(0), GIMT_Encode4(0), GIMT_Encode4(0), GIMT_Encode4(0), GIMT_Encode4(0), GIMT_Encode4(0), GIMT_Encode4(0), GIMT_Encode4(0), GIMT_Encode4(0), GIMT_Encode4(0), GIMT_Encode4(0), GIMT_Encode4(0), GIMT_Encode4(0), GIMT_Encode4(0), GIMT_Encode4(0), GIMT_Encode4(0), GIMT_Encode4(0), GIMT_Encode4(0), GIMT_Encode4(0), GIMT_Encode4(0), GIMT_Encode4(0), GIMT_Encode4(0), GIMT_Encode4(0), GIMT_Encode4(0), GIMT_Encode4(0), GIMT_Encode4(0), GIMT_Encode4(0), GIMT_Encode4(0), GIMT_Encode4(0), GIMT_Encode4(0), GIMT_Encode4(0), GIMT_Encode4(0), GIMT_Encode4(0), GIMT_Encode4(0), GIMT_Encode4(0), GIMT_Encode4(0), GIMT_Encode4(0), GIMT_Encode4(0), GIMT_Encode4(0), GIMT_Encode4(0), GIMT_Encode4(0), GIMT_Encode4(0), GIMT_Encode4(0), GIMT_Encode4(0), GIMT_Encode4(0), GIMT_Encode4(0), GIMT_Encode4(0), GIMT_Encode4(0), GIMT_Encode4(0), GIMT_Encode4(0), GIMT_Encode4(0), GIMT_Encode4(0), GIMT_Encode4(0), GIMT_Encode4(0), GIMT_Encode4(0), GIMT_Encode4(0), GIMT_Encode4(0), GIMT_Encode4(0), GIMT_Encode4(0), GIMT_Encode4(0), GIMT_Encode4(0), GIMT_Encode4(0), GIMT_Encode4(0), GIMT_Encode4(0), GIMT_Encode4(0), GIMT_Encode4(0), GIMT_Encode4(0), GIMT_Encode4(0), GIMT_Encode4(0), GIMT_Encode4(0), GIMT_Encode4(0), GIMT_Encode4(0), GIMT_Encode4(0), GIMT_Encode4(0), GIMT_Encode4(0), GIMT_Encode4(0), GIMT_Encode4(0), GIMT_Encode4(0), GIMT_Encode4(0), GIMT_Encode4(0), GIMT_Encode4(0), GIMT_Encode4(0), GIMT_Encode4(0), GIMT_Encode4(0), GIMT_Encode4(0), GIMT_Encode4(0), GIMT_Encode4(0), GIMT_Encode4(0), GIMT_Encode4(0), GIMT_Encode4(0), GIMT_Encode4(0), GIMT_Encode4(0), GIMT_Encode4(0), GIMT_Encode4(0), GIMT_Encode4(0), GIMT_Encode4(0), GIMT_Encode4(0), GIMT_Encode4(0), GIMT_Encode4(0), GIMT_Encode4(0), GIMT_Encode4(0), GIMT_Encode4(0), GIMT_Encode4(0), GIMT_Encode4(0), GIMT_Encode4(0), GIMT_Encode4(0), GIMT_Encode4(0), GIMT_Encode4(0), GIMT_Encode4(0), GIMT_Encode4(0), GIMT_Encode4(0), GIMT_Encode4(0), GIMT_Encode4(0), GIMT_Encode4(0), GIMT_Encode4(0), GIMT_Encode4(0), GIMT_Encode4(0), GIMT_Encode4(0), GIMT_Encode4(0), GIMT_Encode4(0), GIMT_Encode4(0), GIMT_Encode4(0), GIMT_Encode4(0), GIMT_Encode4(0), GIMT_Encode4(0), GIMT_Encode4(0), GIMT_Encode4(0), GIMT_Encode4(0), GIMT_Encode4(0), GIMT_Encode4(0), GIMT_Encode4(0), GIMT_Encode4(0), GIMT_Encode4(0), GIMT_Encode4(0), GIMT_Encode4(0), GIMT_Encode4(0), GIMT_Encode4(0), GIMT_Encode4(0), GIMT_Encode4(0), GIMT_Encode4(0), GIMT_Encode4(0), GIMT_Encode4(0), GIMT_Encode4(0), GIMT_Encode4(0), GIMT_Encode4(0), GIMT_Encode4(0), GIMT_Encode4(0), GIMT_Encode4(0), GIMT_Encode4(0), GIMT_Encode4(0), GIMT_Encode4(0), GIMT_Encode4(0), GIMT_Encode4(0), GIMT_Encode4(0), GIMT_Encode4(0), GIMT_Encode4(0), GIMT_Encode4(0), GIMT_Encode4(0), GIMT_Encode4(0), GIMT_Encode4(0), GIMT_Encode4(0), GIMT_Encode4(0), GIMT_Encode4(0), GIMT_Encode4(0), GIMT_Encode4(0), GIMT_Encode4(0), GIMT_Encode4(0), GIMT_Encode4(0), GIMT_Encode4(0), GIMT_Encode4(0), GIMT_Encode4(0), GIMT_Encode4(0), GIMT_Encode4(0), GIMT_Encode4(0), GIMT_Encode4(0), GIMT_Encode4(0), GIMT_Encode4(0), GIMT_Encode4(0), GIMT_Encode4(0), GIMT_Encode4(0), GIMT_Encode4(0), GIMT_Encode4(0), GIMT_Encode4(0), GIMT_Encode4(0), GIMT_Encode4(0), GIMT_Encode4(0), GIMT_Encode4(0), GIMT_Encode4(0), GIMT_Encode4(0), GIMT_Encode4(0), GIMT_Encode4(0), GIMT_Encode4(0), GIMT_Encode4(0), GIMT_Encode4(0), GIMT_Encode4(0), GIMT_Encode4(0), GIMT_Encode4(0), GIMT_Encode4(0), GIMT_Encode4(0), GIMT_Encode4(0), GIMT_Encode4(0), GIMT_Encode4(0), GIMT_Encode4(0), GIMT_Encode4(0), GIMT_Encode4(0), GIMT_Encode4(0), GIMT_Encode4(0), GIMT_Encode4(0), GIMT_Encode4(0), GIMT_Encode4(0), GIMT_Encode4(0), GIMT_Encode4(0), GIMT_Encode4(0), GIMT_Encode4(0), GIMT_Encode4(0), GIMT_Encode4(0), GIMT_Encode4(0), GIMT_Encode4(0), GIMT_Encode4(0), GIMT_Encode4(0), GIMT_Encode4(0), GIMT_Encode4(0), GIMT_Encode4(0), GIMT_Encode4(0), GIMT_Encode4(0), GIMT_Encode4(0), GIMT_Encode4(0), GIMT_Encode4(0), GIMT_Encode4(0), GIMT_Encode4(0), GIMT_Encode4(0), GIMT_Encode4(0), GIMT_Encode4(0), GIMT_Encode4(0), GIMT_Encode4(0), GIMT_Encode4(0), GIMT_Encode4(0), GIMT_Encode4(0), GIMT_Encode4(0), GIMT_Encode4(0), GIMT_Encode4(0), GIMT_Encode4(0), GIMT_Encode4(0), GIMT_Encode4(0), GIMT_Encode4(0), GIMT_Encode4(0), GIMT_Encode4(0), GIMT_Encode4(0), GIMT_Encode4(0), GIMT_Encode4(0), GIMT_Encode4(0), GIMT_Encode4(0), GIMT_Encode4(0), GIMT_Encode4(0), GIMT_Encode4(0), GIMT_Encode4(0), GIMT_Encode4(0), GIMT_Encode4(0), GIMT_Encode4(0), GIMT_Encode4(0), GIMT_Encode4(0), GIMT_Encode4(0), GIMT_Encode4(0), GIMT_Encode4(0), GIMT_Encode4(0), GIMT_Encode4(0), GIMT_Encode4(0), GIMT_Encode4(0), GIMT_Encode4(0), GIMT_Encode4(0), GIMT_Encode4(0), GIMT_Encode4(0), GIMT_Encode4(0), GIMT_Encode4(0), GIMT_Encode4(0), GIMT_Encode4(0), GIMT_Encode4(0), GIMT_Encode4(0), GIMT_Encode4(0), GIMT_Encode4(0), GIMT_Encode4(0), GIMT_Encode4(0), GIMT_Encode4(0), GIMT_Encode4(0), GIMT_Encode4(0), GIMT_Encode4(0), GIMT_Encode4(0), GIMT_Encode4(0), GIMT_Encode4(0), GIMT_Encode4(0), GIMT_Encode4(0), GIMT_Encode4(0), GIMT_Encode4(0), GIMT_Encode4(0), GIMT_Encode4(0), GIMT_Encode4(0), GIMT_Encode4(0), GIMT_Encode4(0), GIMT_Encode4(0), GIMT_Encode4(0), GIMT_Encode4(0), GIMT_Encode4(0), GIMT_Encode4(0), GIMT_Encode4(0), GIMT_Encode4(0), GIMT_Encode4(0), GIMT_Encode4(0), GIMT_Encode4(0), GIMT_Encode4(0), GIMT_Encode4(0), GIMT_Encode4(0), GIMT_Encode4(0), GIMT_Encode4(0), GIMT_Encode4(0), GIMT_Encode4(0), GIMT_Encode4(0), GIMT_Encode4(0), GIMT_Encode4(0), GIMT_Encode4(0), GIMT_Encode4(0), GIMT_Encode4(0), GIMT_Encode4(0), GIMT_Encode4(0), GIMT_Encode4(0), GIMT_Encode4(0), GIMT_Encode4(0), GIMT_Encode4(0), GIMT_Encode4(0), GIMT_Encode4(0), GIMT_Encode4(0), GIMT_Encode4(0), GIMT_Encode4(0), GIMT_Encode4(0), GIMT_Encode4(0), GIMT_Encode4(0), GIMT_Encode4(0), GIMT_Encode4(0), GIMT_Encode4(0), GIMT_Encode4(0), GIMT_Encode4(0), GIMT_Encode4(0), GIMT_Encode4(0), GIMT_Encode4(0), GIMT_Encode4(0), GIMT_Encode4(0), GIMT_Encode4(0), GIMT_Encode4(0), GIMT_Encode4(0), GIMT_Encode4(0), GIMT_Encode4(0), GIMT_Encode4(0), GIMT_Encode4(0), GIMT_Encode4(0), GIMT_Encode4(0), GIMT_Encode4(0), GIMT_Encode4(0), GIMT_Encode4(0), GIMT_Encode4(0), GIMT_Encode4(0), GIMT_Encode4(0), GIMT_Encode4(0), GIMT_Encode4(0), GIMT_Encode4(0), GIMT_Encode4(0), GIMT_Encode4(0), GIMT_Encode4(0), GIMT_Encode4(0), GIMT_Encode4(0), GIMT_Encode4(0), GIMT_Encode4(0), GIMT_Encode4(0), GIMT_Encode4(0), GIMT_Encode4(0), GIMT_Encode4(0), GIMT_Encode4(0), GIMT_Encode4(0), GIMT_Encode4(0), GIMT_Encode4(0), GIMT_Encode4(0), GIMT_Encode4(0), GIMT_Encode4(0), GIMT_Encode4(0), GIMT_Encode4(0), GIMT_Encode4(0), GIMT_Encode4(0), GIMT_Encode4(0), GIMT_Encode4(0), GIMT_Encode4(0), GIMT_Encode4(0), GIMT_Encode4(0), GIMT_Encode4(0), GIMT_Encode4(0), GIMT_Encode4(0), GIMT_Encode4(0), GIMT_Encode4(0), GIMT_Encode4(0), GIMT_Encode4(0), GIMT_Encode4(0), GIMT_Encode4(0), GIMT_Encode4(0), GIMT_Encode4(0), GIMT_Encode4(0), GIMT_Encode4(0), GIMT_Encode4(0), GIMT_Encode4(0), GIMT_Encode4(0), GIMT_Encode4(0), GIMT_Encode4(0), GIMT_Encode4(0), GIMT_Encode4(0), GIMT_Encode4(0), GIMT_Encode4(0), GIMT_Encode4(0), GIMT_Encode4(0), GIMT_Encode4(0), GIMT_Encode4(0), GIMT_Encode4(0), GIMT_Encode4(0), GIMT_Encode4(0), GIMT_Encode4(0), GIMT_Encode4(0), GIMT_Encode4(0), GIMT_Encode4(0), GIMT_Encode4(0), GIMT_Encode4(0), GIMT_Encode4(0), GIMT_Encode4(0), GIMT_Encode4(0), GIMT_Encode4(0), GIMT_Encode4(0), GIMT_Encode4(0), GIMT_Encode4(0), GIMT_Encode4(0), GIMT_Encode4(0), GIMT_Encode4(0), GIMT_Encode4(0), GIMT_Encode4(0), GIMT_Encode4(0), GIMT_Encode4(0), GIMT_Encode4(0), GIMT_Encode4(0), GIMT_Encode4(0), GIMT_Encode4(0), GIMT_Encode4(0), GIMT_Encode4(0), GIMT_Encode4(0), GIMT_Encode4(0), GIMT_Encode4(0), GIMT_Encode4(0), GIMT_Encode4(0), GIMT_Encode4(0), GIMT_Encode4(0), GIMT_Encode4(0), GIMT_Encode4(0), GIMT_Encode4(0), GIMT_Encode4(0), GIMT_Encode4(0), GIMT_Encode4(0), GIMT_Encode4(0), GIMT_Encode4(0), GIMT_Encode4(0), GIMT_Encode4(0), GIMT_Encode4(0), GIMT_Encode4(0), GIMT_Encode4(0), GIMT_Encode4(0), GIMT_Encode4(0), GIMT_Encode4(0), GIMT_Encode4(0), GIMT_Encode4(0), GIMT_Encode4(0), GIMT_Encode4(0), GIMT_Encode4(0), GIMT_Encode4(0), GIMT_Encode4(0), GIMT_Encode4(0), GIMT_Encode4(0), GIMT_Encode4(0), GIMT_Encode4(0), GIMT_Encode4(0), GIMT_Encode4(0), GIMT_Encode4(0), GIMT_Encode4(0), GIMT_Encode4(0), GIMT_Encode4(0), GIMT_Encode4(0), GIMT_Encode4(0), GIMT_Encode4(0), GIMT_Encode4(0), GIMT_Encode4(0), GIMT_Encode4(0), GIMT_Encode4(0), GIMT_Encode4(0), GIMT_Encode4(0), GIMT_Encode4(0), GIMT_Encode4(0), GIMT_Encode4(0), GIMT_Encode4(0), GIMT_Encode4(0), GIMT_Encode4(0), GIMT_Encode4(0), GIMT_Encode4(0), GIMT_Encode4(0), GIMT_Encode4(0), GIMT_Encode4(0), GIMT_Encode4(0), GIMT_Encode4(0), GIMT_Encode4(0), GIMT_Encode4(0), GIMT_Encode4(0), GIMT_Encode4(0), GIMT_Encode4(0), GIMT_Encode4(0), GIMT_Encode4(0), GIMT_Encode4(0), GIMT_Encode4(0), GIMT_Encode4(0), GIMT_Encode4(0), GIMT_Encode4(0), GIMT_Encode4(0), GIMT_Encode4(0), GIMT_Encode4(0), GIMT_Encode4(0), GIMT_Encode4(0), GIMT_Encode4(0), GIMT_Encode4(0), GIMT_Encode4(0), GIMT_Encode4(0), GIMT_Encode4(0), GIMT_Encode4(0), GIMT_Encode4(0), GIMT_Encode4(0), GIMT_Encode4(0), GIMT_Encode4(0), GIMT_Encode4(0), GIMT_Encode4(0), GIMT_Encode4(0), GIMT_Encode4(0), GIMT_Encode4(0), GIMT_Encode4(0), GIMT_Encode4(0), GIMT_Encode4(0), GIMT_Encode4(0), GIMT_Encode4(0), GIMT_Encode4(0), GIMT_Encode4(0), GIMT_Encode4(0), GIMT_Encode4(0), GIMT_Encode4(0), GIMT_Encode4(0), GIMT_Encode4(0), GIMT_Encode4(0), GIMT_Encode4(0), GIMT_Encode4(0), GIMT_Encode4(0), GIMT_Encode4(0), GIMT_Encode4(0), GIMT_Encode4(0), GIMT_Encode4(0), GIMT_Encode4(0), GIMT_Encode4(0), GIMT_Encode4(0), GIMT_Encode4(0), GIMT_Encode4(0), GIMT_Encode4(0), GIMT_Encode4(0), GIMT_Encode4(0), GIMT_Encode4(0), GIMT_Encode4(0), GIMT_Encode4(0), GIMT_Encode4(0), GIMT_Encode4(0), GIMT_Encode4(0), GIMT_Encode4(0), GIMT_Encode4(0), GIMT_Encode4(0), GIMT_Encode4(0), GIMT_Encode4(0), GIMT_Encode4(0), GIMT_Encode4(0), GIMT_Encode4(0), GIMT_Encode4(0), GIMT_Encode4(0), GIMT_Encode4(0), GIMT_Encode4(0), GIMT_Encode4(0), GIMT_Encode4(0), GIMT_Encode4(0), GIMT_Encode4(0), GIMT_Encode4(0), GIMT_Encode4(0), GIMT_Encode4(0), GIMT_Encode4(0), GIMT_Encode4(0), GIMT_Encode4(0), GIMT_Encode4(0), GIMT_Encode4(0), GIMT_Encode4(0), GIMT_Encode4(0), GIMT_Encode4(0), GIMT_Encode4(0), GIMT_Encode4(0), GIMT_Encode4(0), GIMT_Encode4(0), GIMT_Encode4(0), GIMT_Encode4(0), GIMT_Encode4(0), GIMT_Encode4(0), GIMT_Encode4(0), GIMT_Encode4(0), GIMT_Encode4(0), GIMT_Encode4(0), GIMT_Encode4(0), GIMT_Encode4(0), GIMT_Encode4(0), GIMT_Encode4(0), GIMT_Encode4(0), GIMT_Encode4(0), GIMT_Encode4(0), GIMT_Encode4(0), GIMT_Encode4(0), GIMT_Encode4(0), GIMT_Encode4(0), GIMT_Encode4(0), GIMT_Encode4(0), GIMT_Encode4(0), GIMT_Encode4(0), GIMT_Encode4(0), GIMT_Encode4(0), GIMT_Encode4(0), GIMT_Encode4(0), GIMT_Encode4(0), GIMT_Encode4(0), GIMT_Encode4(0), GIMT_Encode4(0), GIMT_Encode4(0), GIMT_Encode4(0), GIMT_Encode4(0), GIMT_Encode4(0), GIMT_Encode4(0), GIMT_Encode4(0), GIMT_Encode4(0), GIMT_Encode4(0), GIMT_Encode4(0), GIMT_Encode4(0), GIMT_Encode4(0), GIMT_Encode4(0), GIMT_Encode4(0), GIMT_Encode4(0), GIMT_Encode4(0), GIMT_Encode4(0), GIMT_Encode4(0), GIMT_Encode4(0), GIMT_Encode4(0), GIMT_Encode4(0), GIMT_Encode4(0), GIMT_Encode4(0), GIMT_Encode4(0), GIMT_Encode4(0), GIMT_Encode4(0), GIMT_Encode4(0), GIMT_Encode4(0), GIMT_Encode4(0), GIMT_Encode4(0), GIMT_Encode4(0), GIMT_Encode4(0), GIMT_Encode4(0), GIMT_Encode4(0), GIMT_Encode4(0), GIMT_Encode4(0), GIMT_Encode4(0), GIMT_Encode4(0), GIMT_Encode4(0), GIMT_Encode4(0), GIMT_Encode4(0), GIMT_Encode4(0), GIMT_Encode4(0), GIMT_Encode4(0), GIMT_Encode4(0), GIMT_Encode4(0), GIMT_Encode4(0), GIMT_Encode4(0), GIMT_Encode4(0), GIMT_Encode4(0), GIMT_Encode4(0), GIMT_Encode4(0), GIMT_Encode4(0), GIMT_Encode4(0), GIMT_Encode4(0), GIMT_Encode4(0), GIMT_Encode4(0), GIMT_Encode4(0), GIMT_Encode4(0), GIMT_Encode4(0), GIMT_Encode4(0), GIMT_Encode4(0), GIMT_Encode4(0), GIMT_Encode4(0), GIMT_Encode4(0), GIMT_Encode4(0), GIMT_Encode4(0), GIMT_Encode4(0), GIMT_Encode4(0), GIMT_Encode4(0), GIMT_Encode4(0), GIMT_Encode4(0), GIMT_Encode4(0), GIMT_Encode4(0), GIMT_Encode4(0), GIMT_Encode4(0), GIMT_Encode4(0), GIMT_Encode4(0), GIMT_Encode4(0), GIMT_Encode4(0), GIMT_Encode4(0), GIMT_Encode4(0), GIMT_Encode4(0), GIMT_Encode4(0), GIMT_Encode4(0), GIMT_Encode4(0), GIMT_Encode4(0), GIMT_Encode4(0), GIMT_Encode4(0), GIMT_Encode4(0), GIMT_Encode4(0), GIMT_Encode4(0), GIMT_Encode4(0), GIMT_Encode4(0), GIMT_Encode4(0), GIMT_Encode4(0), GIMT_Encode4(0), GIMT_Encode4(0), GIMT_Encode4(0), GIMT_Encode4(0), GIMT_Encode4(0), GIMT_Encode4(0), GIMT_Encode4(0), GIMT_Encode4(0), GIMT_Encode4(0), GIMT_Encode4(0), GIMT_Encode4(0), GIMT_Encode4(0), GIMT_Encode4(0), GIMT_Encode4(0), GIMT_Encode4(0), GIMT_Encode4(0), GIMT_Encode4(0), GIMT_Encode4(0), GIMT_Encode4(0), GIMT_Encode4(0), GIMT_Encode4(0), GIMT_Encode4(0), GIMT_Encode4(0), GIMT_Encode4(0), GIMT_Encode4(0), GIMT_Encode4(0), GIMT_Encode4(0), GIMT_Encode4(0), GIMT_Encode4(0), GIMT_Encode4(0), GIMT_Encode4(0), GIMT_Encode4(0), GIMT_Encode4(0), GIMT_Encode4(0), GIMT_Encode4(0), GIMT_Encode4(0), GIMT_Encode4(0), GIMT_Encode4(0), GIMT_Encode4(0), GIMT_Encode4(0), GIMT_Encode4(0), GIMT_Encode4(0), GIMT_Encode4(0), GIMT_Encode4(0), GIMT_Encode4(0), GIMT_Encode4(0), GIMT_Encode4(0), GIMT_Encode4(0), GIMT_Encode4(0), GIMT_Encode4(0), GIMT_Encode4(0), GIMT_Encode4(0), GIMT_Encode4(0), GIMT_Encode4(0), GIMT_Encode4(0), GIMT_Encode4(0), GIMT_Encode4(0), GIMT_Encode4(0), GIMT_Encode4(0), GIMT_Encode4(0), GIMT_Encode4(0), GIMT_Encode4(0), GIMT_Encode4(0), GIMT_Encode4(0), GIMT_Encode4(0), GIMT_Encode4(0), GIMT_Encode4(0), GIMT_Encode4(0), GIMT_Encode4(0), GIMT_Encode4(0), GIMT_Encode4(0), GIMT_Encode4(0), GIMT_Encode4(0), GIMT_Encode4(0), GIMT_Encode4(0), GIMT_Encode4(0), GIMT_Encode4(0), GIMT_Encode4(0), GIMT_Encode4(0), GIMT_Encode4(0), GIMT_Encode4(0), GIMT_Encode4(0), GIMT_Encode4(0), GIMT_Encode4(0), GIMT_Encode4(0), GIMT_Encode4(0), GIMT_Encode4(0), GIMT_Encode4(0), GIMT_Encode4(0), GIMT_Encode4(0), GIMT_Encode4(0), GIMT_Encode4(0), GIMT_Encode4(0), GIMT_Encode4(0), GIMT_Encode4(0), GIMT_Encode4(0), GIMT_Encode4(0), GIMT_Encode4(0), GIMT_Encode4(0), GIMT_Encode4(0), GIMT_Encode4(0), GIMT_Encode4(0), GIMT_Encode4(0), GIMT_Encode4(0), GIMT_Encode4(0), GIMT_Encode4(0), GIMT_Encode4(0), GIMT_Encode4(0), GIMT_Encode4(0), GIMT_Encode4(0), GIMT_Encode4(0), GIMT_Encode4(0), GIMT_Encode4(0), GIMT_Encode4(0), GIMT_Encode4(0), GIMT_Encode4(0), GIMT_Encode4(0), GIMT_Encode4(0), GIMT_Encode4(0), GIMT_Encode4(0), GIMT_Encode4(0), GIMT_Encode4(0), GIMT_Encode4(0), GIMT_Encode4(0), GIMT_Encode4(0), GIMT_Encode4(0), GIMT_Encode4(0), GIMT_Encode4(0), GIMT_Encode4(0), GIMT_Encode4(0), GIMT_Encode4(0), GIMT_Encode4(0), GIMT_Encode4(0), GIMT_Encode4(0), GIMT_Encode4(0), GIMT_Encode4(0), GIMT_Encode4(0), GIMT_Encode4(0), GIMT_Encode4(0), GIMT_Encode4(0), GIMT_Encode4(0), GIMT_Encode4(0), GIMT_Encode4(0), GIMT_Encode4(0), GIMT_Encode4(0), GIMT_Encode4(0), GIMT_Encode4(0), GIMT_Encode4(0), GIMT_Encode4(0), GIMT_Encode4(0), GIMT_Encode4(0), GIMT_Encode4(0), GIMT_Encode4(0), GIMT_Encode4(0), GIMT_Encode4(0), GIMT_Encode4(0), GIMT_Encode4(0), GIMT_Encode4(0), GIMT_Encode4(0), GIMT_Encode4(0), GIMT_Encode4(0), GIMT_Encode4(0), GIMT_Encode4(0), GIMT_Encode4(0), GIMT_Encode4(0), GIMT_Encode4(0), GIMT_Encode4(0), GIMT_Encode4(0), GIMT_Encode4(0), GIMT_Encode4(0), GIMT_Encode4(0), GIMT_Encode4(0), GIMT_Encode4(0), GIMT_Encode4(0), GIMT_Encode4(0), GIMT_Encode4(0), GIMT_Encode4(0), GIMT_Encode4(0), GIMT_Encode4(0), GIMT_Encode4(0), GIMT_Encode4(0), GIMT_Encode4(0), GIMT_Encode4(0), GIMT_Encode4(0), GIMT_Encode4(0), GIMT_Encode4(0), GIMT_Encode4(0), GIMT_Encode4(0), GIMT_Encode4(0), GIMT_Encode4(0), GIMT_Encode4(0), GIMT_Encode4(0), GIMT_Encode4(0), GIMT_Encode4(0), GIMT_Encode4(0), GIMT_Encode4(0), GIMT_Encode4(0), GIMT_Encode4(0), GIMT_Encode4(0), GIMT_Encode4(0), GIMT_Encode4(0), GIMT_Encode4(0), GIMT_Encode4(0), GIMT_Encode4(0), GIMT_Encode4(0), GIMT_Encode4(0), GIMT_Encode4(0), GIMT_Encode4(0), GIMT_Encode4(0), GIMT_Encode4(0), GIMT_Encode4(0), GIMT_Encode4(0), GIMT_Encode4(0), GIMT_Encode4(0), GIMT_Encode4(0), GIMT_Encode4(0), GIMT_Encode4(0), GIMT_Encode4(0), GIMT_Encode4(0), GIMT_Encode4(0), GIMT_Encode4(0), GIMT_Encode4(0), GIMT_Encode4(0), GIMT_Encode4(0), GIMT_Encode4(0), GIMT_Encode4(0), GIMT_Encode4(0), GIMT_Encode4(0), GIMT_Encode4(0), GIMT_Encode4(0), GIMT_Encode4(0), GIMT_Encode4(0), GIMT_Encode4(0), GIMT_Encode4(0), GIMT_Encode4(0), GIMT_Encode4(0), GIMT_Encode4(0), GIMT_Encode4(0), GIMT_Encode4(0), GIMT_Encode4(0), GIMT_Encode4(0), GIMT_Encode4(0), GIMT_Encode4(0), GIMT_Encode4(0), GIMT_Encode4(0), GIMT_Encode4(0), GIMT_Encode4(0), GIMT_Encode4(0), GIMT_Encode4(0), GIMT_Encode4(0), GIMT_Encode4(0), GIMT_Encode4(0), GIMT_Encode4(0), GIMT_Encode4(0), GIMT_Encode4(0), GIMT_Encode4(0), GIMT_Encode4(0), GIMT_Encode4(0), GIMT_Encode4(0), GIMT_Encode4(0), GIMT_Encode4(0), GIMT_Encode4(0), GIMT_Encode4(0), GIMT_Encode4(0), GIMT_Encode4(0), GIMT_Encode4(0), GIMT_Encode4(0), GIMT_Encode4(0), GIMT_Encode4(0), GIMT_Encode4(0), GIMT_Encode4(0), GIMT_Encode4(0), GIMT_Encode4(0), GIMT_Encode4(0), GIMT_Encode4(0), GIMT_Encode4(0), GIMT_Encode4(0), GIMT_Encode4(0), GIMT_Encode4(0), GIMT_Encode4(0), GIMT_Encode4(0), GIMT_Encode4(0), GIMT_Encode4(0), GIMT_Encode4(0), GIMT_Encode4(0), GIMT_Encode4(0), GIMT_Encode4(0), GIMT_Encode4(0), GIMT_Encode4(0), GIMT_Encode4(0), GIMT_Encode4(0), GIMT_Encode4(0), GIMT_Encode4(0), GIMT_Encode4(0), GIMT_Encode4(0), GIMT_Encode4(0), GIMT_Encode4(0), GIMT_Encode4(0), GIMT_Encode4(0), GIMT_Encode4(0), GIMT_Encode4(0), GIMT_Encode4(0), GIMT_Encode4(0), GIMT_Encode4(0), GIMT_Encode4(0), GIMT_Encode4(0), GIMT_Encode4(0), GIMT_Encode4(0), GIMT_Encode4(0), GIMT_Encode4(0), GIMT_Encode4(0), GIMT_Encode4(0), GIMT_Encode4(0), GIMT_Encode4(0), GIMT_Encode4(0), GIMT_Encode4(0), GIMT_Encode4(0), GIMT_Encode4(0), GIMT_Encode4(0), GIMT_Encode4(0), GIMT_Encode4(0), GIMT_Encode4(0), GIMT_Encode4(0), GIMT_Encode4(0), GIMT_Encode4(0), GIMT_Encode4(0), GIMT_Encode4(0), GIMT_Encode4(0), GIMT_Encode4(0), GIMT_Encode4(0), GIMT_Encode4(0), GIMT_Encode4(0), GIMT_Encode4(0), GIMT_Encode4(0), GIMT_Encode4(0), GIMT_Encode4(0), GIMT_Encode4(0), GIMT_Encode4(0), GIMT_Encode4(0), GIMT_Encode4(0), GIMT_Encode4(0), GIMT_Encode4(0), GIMT_Encode4(0), GIMT_Encode4(0), GIMT_Encode4(0), GIMT_Encode4(0), GIMT_Encode4(0), GIMT_Encode4(0), GIMT_Encode4(0), GIMT_Encode4(0), GIMT_Encode4(0), GIMT_Encode4(0), GIMT_Encode4(0), GIMT_Encode4(0), GIMT_Encode4(0), GIMT_Encode4(0), GIMT_Encode4(0), GIMT_Encode4(0), GIMT_Encode4(0), GIMT_Encode4(0), GIMT_Encode4(0), GIMT_Encode4(0), GIMT_Encode4(0), GIMT_Encode4(0), GIMT_Encode4(0), GIMT_Encode4(0), GIMT_Encode4(0), GIMT_Encode4(0), GIMT_Encode4(0), GIMT_Encode4(0), GIMT_Encode4(0), GIMT_Encode4(0), GIMT_Encode4(0), GIMT_Encode4(0), GIMT_Encode4(0), GIMT_Encode4(0), GIMT_Encode4(0), GIMT_Encode4(0), GIMT_Encode4(0), GIMT_Encode4(0), GIMT_Encode4(0), GIMT_Encode4(0), GIMT_Encode4(0), GIMT_Encode4(0), GIMT_Encode4(0), GIMT_Encode4(0), GIMT_Encode4(0), GIMT_Encode4(0), GIMT_Encode4(0), GIMT_Encode4(0), GIMT_Encode4(0), GIMT_Encode4(0), GIMT_Encode4(0), GIMT_Encode4(0), GIMT_Encode4(0), GIMT_Encode4(0), GIMT_Encode4(0), GIMT_Encode4(0), GIMT_Encode4(0), GIMT_Encode4(0), GIMT_Encode4(0), GIMT_Encode4(0), GIMT_Encode4(0), GIMT_Encode4(0), GIMT_Encode4(0), GIMT_Encode4(0), GIMT_Encode4(0), GIMT_Encode4(0), GIMT_Encode4(0), GIMT_Encode4(0), GIMT_Encode4(0), GIMT_Encode4(0), GIMT_Encode4(0), GIMT_Encode4(0), GIMT_Encode4(0), GIMT_Encode4(0), GIMT_Encode4(0), GIMT_Encode4(0), GIMT_Encode4(0), GIMT_Encode4(0), GIMT_Encode4(0), GIMT_Encode4(0), GIMT_Encode4(0), GIMT_Encode4(0), GIMT_Encode4(0), GIMT_Encode4(0), GIMT_Encode4(0), GIMT_Encode4(0), GIMT_Encode4(0), GIMT_Encode4(0), GIMT_Encode4(0), GIMT_Encode4(0), GIMT_Encode4(0), GIMT_Encode4(0), GIMT_Encode4(0), GIMT_Encode4(0), GIMT_Encode4(0), GIMT_Encode4(0), GIMT_Encode4(0), GIMT_Encode4(0), GIMT_Encode4(0), GIMT_Encode4(0), GIMT_Encode4(0), GIMT_Encode4(0), GIMT_Encode4(0), GIMT_Encode4(0), GIMT_Encode4(0), GIMT_Encode4(0), GIMT_Encode4(0), GIMT_Encode4(0), GIMT_Encode4(0), GIMT_Encode4(0), GIMT_Encode4(0), GIMT_Encode4(0), GIMT_Encode4(0), GIMT_Encode4(0), GIMT_Encode4(0), GIMT_Encode4(0), GIMT_Encode4(0), GIMT_Encode4(0), GIMT_Encode4(0), GIMT_Encode4(0), GIMT_Encode4(0), GIMT_Encode4(0), GIMT_Encode4(0), GIMT_Encode4(0), GIMT_Encode4(0), GIMT_Encode4(0), GIMT_Encode4(0), GIMT_Encode4(0), GIMT_Encode4(0), GIMT_Encode4(0), GIMT_Encode4(0), GIMT_Encode4(0), GIMT_Encode4(0), GIMT_Encode4(0), GIMT_Encode4(0), GIMT_Encode4(0), GIMT_Encode4(0), GIMT_Encode4(0), GIMT_Encode4(0), GIMT_Encode4(0), GIMT_Encode4(0), GIMT_Encode4(0), GIMT_Encode4(0), GIMT_Encode4(0), GIMT_Encode4(0), GIMT_Encode4(0), GIMT_Encode4(0), GIMT_Encode4(0), GIMT_Encode4(0), GIMT_Encode4(0), GIMT_Encode4(0), GIMT_Encode4(0), GIMT_Encode4(0), GIMT_Encode4(0), GIMT_Encode4(0), GIMT_Encode4(0), GIMT_Encode4(0), GIMT_Encode4(0), GIMT_Encode4(0), GIMT_Encode4(0), GIMT_Encode4(0), GIMT_Encode4(0), GIMT_Encode4(0), GIMT_Encode4(0), GIMT_Encode4(0), GIMT_Encode4(0), GIMT_Encode4(0), GIMT_Encode4(0), GIMT_Encode4(0), GIMT_Encode4(0), GIMT_Encode4(0), GIMT_Encode4(0), GIMT_Encode4(0), GIMT_Encode4(0), GIMT_Encode4(0), GIMT_Encode4(0), GIMT_Encode4(0), GIMT_Encode4(0), GIMT_Encode4(0), GIMT_Encode4(0), GIMT_Encode4(0), GIMT_Encode4(0), GIMT_Encode4(0), GIMT_Encode4(0), GIMT_Encode4(0), GIMT_Encode4(0), GIMT_Encode4(0), GIMT_Encode4(0), GIMT_Encode4(0), GIMT_Encode4(0), GIMT_Encode4(0), GIMT_Encode4(0), GIMT_Encode4(0), GIMT_Encode4(0), GIMT_Encode4(0), GIMT_Encode4(0), GIMT_Encode4(0), GIMT_Encode4(0), GIMT_Encode4(0), GIMT_Encode4(0), GIMT_Encode4(0), GIMT_Encode4(0), GIMT_Encode4(0), GIMT_Encode4(0), GIMT_Encode4(0), GIMT_Encode4(0), GIMT_Encode4(0), GIMT_Encode4(0), GIMT_Encode4(0), GIMT_Encode4(0), GIMT_Encode4(0), GIMT_Encode4(0), GIMT_Encode4(0), GIMT_Encode4(0), GIMT_Encode4(0), GIMT_Encode4(0), GIMT_Encode4(0), GIMT_Encode4(0), GIMT_Encode4(0), GIMT_Encode4(0), GIMT_Encode4(0), GIMT_Encode4(0), GIMT_Encode4(0), GIMT_Encode4(0), GIMT_Encode4(0), GIMT_Encode4(0), GIMT_Encode4(0), GIMT_Encode4(0), GIMT_Encode4(0), GIMT_Encode4(0), GIMT_Encode4(0), GIMT_Encode4(0), GIMT_Encode4(0), GIMT_Encode4(0), GIMT_Encode4(0), GIMT_Encode4(0), GIMT_Encode4(0), GIMT_Encode4(0), GIMT_Encode4(0), GIMT_Encode4(0), GIMT_Encode4(0), GIMT_Encode4(0), GIMT_Encode4(0), GIMT_Encode4(0), GIMT_Encode4(0), GIMT_Encode4(0), GIMT_Encode4(0), GIMT_Encode4(0), GIMT_Encode4(0), GIMT_Encode4(0), GIMT_Encode4(0), GIMT_Encode4(0), GIMT_Encode4(0), GIMT_Encode4(0), GIMT_Encode4(0), GIMT_Encode4(0), GIMT_Encode4(0), GIMT_Encode4(0), GIMT_Encode4(0), GIMT_Encode4(0), GIMT_Encode4(0), GIMT_Encode4(0), GIMT_Encode4(0), GIMT_Encode4(0), GIMT_Encode4(0), GIMT_Encode4(0), GIMT_Encode4(0), GIMT_Encode4(0), GIMT_Encode4(0), GIMT_Encode4(0), GIMT_Encode4(0), GIMT_Encode4(0), GIMT_Encode4(0), GIMT_Encode4(0), GIMT_Encode4(0), GIMT_Encode4(0), GIMT_Encode4(0), GIMT_Encode4(0), GIMT_Encode4(0), GIMT_Encode4(0), GIMT_Encode4(0), GIMT_Encode4(0), GIMT_Encode4(0), GIMT_Encode4(0), GIMT_Encode4(0), GIMT_Encode4(0), GIMT_Encode4(0), GIMT_Encode4(0), GIMT_Encode4(0), GIMT_Encode4(0), GIMT_Encode4(0), GIMT_Encode4(0), GIMT_Encode4(0), GIMT_Encode4(0), GIMT_Encode4(0), GIMT_Encode4(0), GIMT_Encode4(0), GIMT_Encode4(0), GIMT_Encode4(0), GIMT_Encode4(0), GIMT_Encode4(0), GIMT_Encode4(0), GIMT_Encode4(0), GIMT_Encode4(0), GIMT_Encode4(0), GIMT_Encode4(0), GIMT_Encode4(0), GIMT_Encode4(0), GIMT_Encode4(0), GIMT_Encode4(0), GIMT_Encode4(0), GIMT_Encode4(0), GIMT_Encode4(0), GIMT_Encode4(0), GIMT_Encode4(0), GIMT_Encode4(0), GIMT_Encode4(0), GIMT_Encode4(0), GIMT_Encode4(0), GIMT_Encode4(0), GIMT_Encode4(0), GIMT_Encode4(0), GIMT_Encode4(0), GIMT_Encode4(0), GIMT_Encode4(0), GIMT_Encode4(0), GIMT_Encode4(0), GIMT_Encode4(0), GIMT_Encode4(0), GIMT_Encode4(0), GIMT_Encode4(0), GIMT_Encode4(0), GIMT_Encode4(0), GIMT_Encode4(0), GIMT_Encode4(0), GIMT_Encode4(0), GIMT_Encode4(0), GIMT_Encode4(0), GIMT_Encode4(0), GIMT_Encode4(0), GIMT_Encode4(0), GIMT_Encode4(0), GIMT_Encode4(0), GIMT_Encode4(0), GIMT_Encode4(0), GIMT_Encode4(0), GIMT_Encode4(0), GIMT_Encode4(0), GIMT_Encode4(0), GIMT_Encode4(0), GIMT_Encode4(0), GIMT_Encode4(0), GIMT_Encode4(0), GIMT_Encode4(0), GIMT_Encode4(0), GIMT_Encode4(0), GIMT_Encode4(0), GIMT_Encode4(0), GIMT_Encode4(0), GIMT_Encode4(0), GIMT_Encode4(0), GIMT_Encode4(0), GIMT_Encode4(0), GIMT_Encode4(0), GIMT_Encode4(0), GIMT_Encode4(0), GIMT_Encode4(0), GIMT_Encode4(0), GIMT_Encode4(0), GIMT_Encode4(0), GIMT_Encode4(0), GIMT_Encode4(0), GIMT_Encode4(0), GIMT_Encode4(0), GIMT_Encode4(0), GIMT_Encode4(0), GIMT_Encode4(0), GIMT_Encode4(0), GIMT_Encode4(0), GIMT_Encode4(0), GIMT_Encode4(0), GIMT_Encode4(0), GIMT_Encode4(0), GIMT_Encode4(0), GIMT_Encode4(0), GIMT_Encode4(0), GIMT_Encode4(0), GIMT_Encode4(0), GIMT_Encode4(0), GIMT_Encode4(0), GIMT_Encode4(0), GIMT_Encode4(0), GIMT_Encode4(0), GIMT_Encode4(0), GIMT_Encode4(0), GIMT_Encode4(0), GIMT_Encode4(0), GIMT_Encode4(0), GIMT_Encode4(0), GIMT_Encode4(0), GIMT_Encode4(0), GIMT_Encode4(0), GIMT_Encode4(0), GIMT_Encode4(0), GIMT_Encode4(0), GIMT_Encode4(0), GIMT_Encode4(0), GIMT_Encode4(0), GIMT_Encode4(0), GIMT_Encode4(0), GIMT_Encode4(0), GIMT_Encode4(0), GIMT_Encode4(0), GIMT_Encode4(0), GIMT_Encode4(0), GIMT_Encode4(0), GIMT_Encode4(0), GIMT_Encode4(0), GIMT_Encode4(0), GIMT_Encode4(0), GIMT_Encode4(0), GIMT_Encode4(0), GIMT_Encode4(0), GIMT_Encode4(0), GIMT_Encode4(0), GIMT_Encode4(0), GIMT_Encode4(0), GIMT_Encode4(0), GIMT_Encode4(0), GIMT_Encode4(0), GIMT_Encode4(0), GIMT_Encode4(0), GIMT_Encode4(0), GIMT_Encode4(0), GIMT_Encode4(0), GIMT_Encode4(0), GIMT_Encode4(0), GIMT_Encode4(0), GIMT_Encode4(0), GIMT_Encode4(0), GIMT_Encode4(0), GIMT_Encode4(0), GIMT_Encode4(0), GIMT_Encode4(0), GIMT_Encode4(0), GIMT_Encode4(0), GIMT_Encode4(0), GIMT_Encode4(0), GIMT_Encode4(0), GIMT_Encode4(0), GIMT_Encode4(0), GIMT_Encode4(0), GIMT_Encode4(0), GIMT_Encode4(0), GIMT_Encode4(0), GIMT_Encode4(0), GIMT_Encode4(0), GIMT_Encode4(0), GIMT_Encode4(0), GIMT_Encode4(0), GIMT_Encode4(0), GIMT_Encode4(0), GIMT_Encode4(0), GIMT_Encode4(0), GIMT_Encode4(0), GIMT_Encode4(0), GIMT_Encode4(0), GIMT_Encode4(0), GIMT_Encode4(0), GIMT_Encode4(0), GIMT_Encode4(0), GIMT_Encode4(0), GIMT_Encode4(0), GIMT_Encode4(0), GIMT_Encode4(0), GIMT_Encode4(0), GIMT_Encode4(0), GIMT_Encode4(0), GIMT_Encode4(0), GIMT_Encode4(0), GIMT_Encode4(0), GIMT_Encode4(0), GIMT_Encode4(0), GIMT_Encode4(0), GIMT_Encode4(0), GIMT_Encode4(0), GIMT_Encode4(0), GIMT_Encode4(0), GIMT_Encode4(0), GIMT_Encode4(0), GIMT_Encode4(0), GIMT_Encode4(0), GIMT_Encode4(0), GIMT_Encode4(0), GIMT_Encode4(0), GIMT_Encode4(0), GIMT_Encode4(0), GIMT_Encode4(0), GIMT_Encode4(0), GIMT_Encode4(0), GIMT_Encode4(0), GIMT_Encode4(0), GIMT_Encode4(0), GIMT_Encode4(0), GIMT_Encode4(0), GIMT_Encode4(0), GIMT_Encode4(0), GIMT_Encode4(0), GIMT_Encode4(0), GIMT_Encode4(0), GIMT_Encode4(0), GIMT_Encode4(0), GIMT_Encode4(0), GIMT_Encode4(0), GIMT_Encode4(0), GIMT_Encode4(0), GIMT_Encode4(0), GIMT_Encode4(0), GIMT_Encode4(0), GIMT_Encode4(0), GIMT_Encode4(0), GIMT_Encode4(0), GIMT_Encode4(0), GIMT_Encode4(0), GIMT_Encode4(0), GIMT_Encode4(0), GIMT_Encode4(0), GIMT_Encode4(0), GIMT_Encode4(0), GIMT_Encode4(0), GIMT_Encode4(0), GIMT_Encode4(0), GIMT_Encode4(0), GIMT_Encode4(0), GIMT_Encode4(0), GIMT_Encode4(0), GIMT_Encode4(0), GIMT_Encode4(0), GIMT_Encode4(0), GIMT_Encode4(0), GIMT_Encode4(0), GIMT_Encode4(0), GIMT_Encode4(0), GIMT_Encode4(0), GIMT_Encode4(0), GIMT_Encode4(0), GIMT_Encode4(0), GIMT_Encode4(0), GIMT_Encode4(0), GIMT_Encode4(0), GIMT_Encode4(0), GIMT_Encode4(0), GIMT_Encode4(0), GIMT_Encode4(0), GIMT_Encode4(0), GIMT_Encode4(0), GIMT_Encode4(0), GIMT_Encode4(0), GIMT_Encode4(0), GIMT_Encode4(0), GIMT_Encode4(0), GIMT_Encode4(0), GIMT_Encode4(0), GIMT_Encode4(0), GIMT_Encode4(0), GIMT_Encode4(0), GIMT_Encode4(0), GIMT_Encode4(0), GIMT_Encode4(0), GIMT_Encode4(0), GIMT_Encode4(0), GIMT_Encode4(0), GIMT_Encode4(0), GIMT_Encode4(0), GIMT_Encode4(0), GIMT_Encode4(0), GIMT_Encode4(0), GIMT_Encode4(0), GIMT_Encode4(0), GIMT_Encode4(0), GIMT_Encode4(0), GIMT_Encode4(0), GIMT_Encode4(0), GIMT_Encode4(0), GIMT_Encode4(0), GIMT_Encode4(0), GIMT_Encode4(0), GIMT_Encode4(0), GIMT_Encode4(0), GIMT_Encode4(0), GIMT_Encode4(0), GIMT_Encode4(0), GIMT_Encode4(0), GIMT_Encode4(0), GIMT_Encode4(0), GIMT_Encode4(0), GIMT_Encode4(0), GIMT_Encode4(0), GIMT_Encode4(0), GIMT_Encode4(0), GIMT_Encode4(0), GIMT_Encode4(0), GIMT_Encode4(0), GIMT_Encode4(0), GIMT_Encode4(0), GIMT_Encode4(0), GIMT_Encode4(0), GIMT_Encode4(0), GIMT_Encode4(0), GIMT_Encode4(0), GIMT_Encode4(0), GIMT_Encode4(0), GIMT_Encode4(0), GIMT_Encode4(0), GIMT_Encode4(0), GIMT_Encode4(0), GIMT_Encode4(0), GIMT_Encode4(0), GIMT_Encode4(0), GIMT_Encode4(0), GIMT_Encode4(0), GIMT_Encode4(0), GIMT_Encode4(0), GIMT_Encode4(0), GIMT_Encode4(0), GIMT_Encode4(0), GIMT_Encode4(0), GIMT_Encode4(0), GIMT_Encode4(0), GIMT_Encode4(0), GIMT_Encode4(0), GIMT_Encode4(0), GIMT_Encode4(0), GIMT_Encode4(0), GIMT_Encode4(0), GIMT_Encode4(0), GIMT_Encode4(0), GIMT_Encode4(0), GIMT_Encode4(0), GIMT_Encode4(0), GIMT_Encode4(0), GIMT_Encode4(0), GIMT_Encode4(0), GIMT_Encode4(0), GIMT_Encode4(0), GIMT_Encode4(0), GIMT_Encode4(0), GIMT_Encode4(0), GIMT_Encode4(0), GIMT_Encode4(0), GIMT_Encode4(0), GIMT_Encode4(0), GIMT_Encode4(0), GIMT_Encode4(0), GIMT_Encode4(0), GIMT_Encode4(0), GIMT_Encode4(0), GIMT_Encode4(0), GIMT_Encode4(0), GIMT_Encode4(0), GIMT_Encode4(0), GIMT_Encode4(0), GIMT_Encode4(0), GIMT_Encode4(0), GIMT_Encode4(0), GIMT_Encode4(0), GIMT_Encode4(0), GIMT_Encode4(0), GIMT_Encode4(0), GIMT_Encode4(0), GIMT_Encode4(0), GIMT_Encode4(0), GIMT_Encode4(0), GIMT_Encode4(0), GIMT_Encode4(0), GIMT_Encode4(0), GIMT_Encode4(0), GIMT_Encode4(0), GIMT_Encode4(0), GIMT_Encode4(0), GIMT_Encode4(0), GIMT_Encode4(0), GIMT_Encode4(0), GIMT_Encode4(0), GIMT_Encode4(0), GIMT_Encode4(0), GIMT_Encode4(0), GIMT_Encode4(0), GIMT_Encode4(0), GIMT_Encode4(0), GIMT_Encode4(0), GIMT_Encode4(0), GIMT_Encode4(0), GIMT_Encode4(0), GIMT_Encode4(0), GIMT_Encode4(0), GIMT_Encode4(0), GIMT_Encode4(0), GIMT_Encode4(0), GIMT_Encode4(0), GIMT_Encode4(0), GIMT_Encode4(0), GIMT_Encode4(0), GIMT_Encode4(0), GIMT_Encode4(0), GIMT_Encode4(0), GIMT_Encode4(0), GIMT_Encode4(0), GIMT_Encode4(0), GIMT_Encode4(0), GIMT_Encode4(0), GIMT_Encode4(0), GIMT_Encode4(0), GIMT_Encode4(0), GIMT_Encode4(0), GIMT_Encode4(0), GIMT_Encode4(0), GIMT_Encode4(0), GIMT_Encode4(0), GIMT_Encode4(0), GIMT_Encode4(0), GIMT_Encode4(0), GIMT_Encode4(0), GIMT_Encode4(0), GIMT_Encode4(0), GIMT_Encode4(0), GIMT_Encode4(0), GIMT_Encode4(0), GIMT_Encode4(0), GIMT_Encode4(0), GIMT_Encode4(0), GIMT_Encode4(0), GIMT_Encode4(0), GIMT_Encode4(0), GIMT_Encode4(0), GIMT_Encode4(0), GIMT_Encode4(0), GIMT_Encode4(0), GIMT_Encode4(0), GIMT_Encode4(0), GIMT_Encode4(0), GIMT_Encode4(0), GIMT_Encode4(0), GIMT_Encode4(0), GIMT_Encode4(0), GIMT_Encode4(0), GIMT_Encode4(0), GIMT_Encode4(0), GIMT_Encode4(0), GIMT_Encode4(0), GIMT_Encode4(0), GIMT_Encode4(0), GIMT_Encode4(0), GIMT_Encode4(0), GIMT_Encode4(0), GIMT_Encode4(0), GIMT_Encode4(0), GIMT_Encode4(0), GIMT_Encode4(0), GIMT_Encode4(0), GIMT_Encode4(0), GIMT_Encode4(0), GIMT_Encode4(0), GIMT_Encode4(0), GIMT_Encode4(0), GIMT_Encode4(0), GIMT_Encode4(0), GIMT_Encode4(0), GIMT_Encode4(0), GIMT_Encode4(0), GIMT_Encode4(0), GIMT_Encode4(0), GIMT_Encode4(0), GIMT_Encode4(0), GIMT_Encode4(0), GIMT_Encode4(0), GIMT_Encode4(0), GIMT_Encode4(0), GIMT_Encode4(0), GIMT_Encode4(0), GIMT_Encode4(0), GIMT_Encode4(0), GIMT_Encode4(0), GIMT_Encode4(0), GIMT_Encode4(0), GIMT_Encode4(0), GIMT_Encode4(0), GIMT_Encode4(0), GIMT_Encode4(0), GIMT_Encode4(0), GIMT_Encode4(0), GIMT_Encode4(0), GIMT_Encode4(0), GIMT_Encode4(0), GIMT_Encode4(0), GIMT_Encode4(0), GIMT_Encode4(0), GIMT_Encode4(0), GIMT_Encode4(0), GIMT_Encode4(0), GIMT_Encode4(0), GIMT_Encode4(0), GIMT_Encode4(0), GIMT_Encode4(0), GIMT_Encode4(0), GIMT_Encode4(0), GIMT_Encode4(0), GIMT_Encode4(0), GIMT_Encode4(0), GIMT_Encode4(0), GIMT_Encode4(0), GIMT_Encode4(0), GIMT_Encode4(0), GIMT_Encode4(0), GIMT_Encode4(0), GIMT_Encode4(0), GIMT_Encode4(0), GIMT_Encode4(0), GIMT_Encode4(0), GIMT_Encode4(0), GIMT_Encode4(0), GIMT_Encode4(0), GIMT_Encode4(0), GIMT_Encode4(0), GIMT_Encode4(0), GIMT_Encode4(0), GIMT_Encode4(0), GIMT_Encode4(0), GIMT_Encode4(0), GIMT_Encode4(0), GIMT_Encode4(0), GIMT_Encode4(0), GIMT_Encode4(0), GIMT_Encode4(0), GIMT_Encode4(0), GIMT_Encode4(0), GIMT_Encode4(0), GIMT_Encode4(0), GIMT_Encode4(0), GIMT_Encode4(0), GIMT_Encode4(0), GIMT_Encode4(0), GIMT_Encode4(0), GIMT_Encode4(0), GIMT_Encode4(0), GIMT_Encode4(0), GIMT_Encode4(0), GIMT_Encode4(0), GIMT_Encode4(0), GIMT_Encode4(0), GIMT_Encode4(0), GIMT_Encode4(0), GIMT_Encode4(0), GIMT_Encode4(0), GIMT_Encode4(0), GIMT_Encode4(0), GIMT_Encode4(0), GIMT_Encode4(0), GIMT_Encode4(0), GIMT_Encode4(0), GIMT_Encode4(0), GIMT_Encode4(0), GIMT_Encode4(0), GIMT_Encode4(0), GIMT_Encode4(0), GIMT_Encode4(0), GIMT_Encode4(0), GIMT_Encode4(0), GIMT_Encode4(0), GIMT_Encode4(0), GIMT_Encode4(0), GIMT_Encode4(0), GIMT_Encode4(0), GIMT_Encode4(0), GIMT_Encode4(0), GIMT_Encode4(0), GIMT_Encode4(0), GIMT_Encode4(0), GIMT_Encode4(0), GIMT_Encode4(0), GIMT_Encode4(0), GIMT_Encode4(0), GIMT_Encode4(0), GIMT_Encode4(0), GIMT_Encode4(0), GIMT_Encode4(0), GIMT_Encode4(0), GIMT_Encode4(0), GIMT_Encode4(0), GIMT_Encode4(0), GIMT_Encode4(0), GIMT_Encode4(0), GIMT_Encode4(0), GIMT_Encode4(0), GIMT_Encode4(0), GIMT_Encode4(0), GIMT_Encode4(0), GIMT_Encode4(0), GIMT_Encode4(0), GIMT_Encode4(0), GIMT_Encode4(0), GIMT_Encode4(0), GIMT_Encode4(0), GIMT_Encode4(0), GIMT_Encode4(0), GIMT_Encode4(0), GIMT_Encode4(0), GIMT_Encode4(0), GIMT_Encode4(0), GIMT_Encode4(0), GIMT_Encode4(0), GIMT_Encode4(0), GIMT_Encode4(0), GIMT_Encode4(0), GIMT_Encode4(0), GIMT_Encode4(0), GIMT_Encode4(0), GIMT_Encode4(0), GIMT_Encode4(0), GIMT_Encode4(0), GIMT_Encode4(0), GIMT_Encode4(0), GIMT_Encode4(0), GIMT_Encode4(0), GIMT_Encode4(0), GIMT_Encode4(0), GIMT_Encode4(0), GIMT_Encode4(0), GIMT_Encode4(0), GIMT_Encode4(0), GIMT_Encode4(0), GIMT_Encode4(0), GIMT_Encode4(0), GIMT_Encode4(0), GIMT_Encode4(0), GIMT_Encode4(0), GIMT_Encode4(0), GIMT_Encode4(0), GIMT_Encode4(0), GIMT_Encode4(0), GIMT_Encode4(0), GIMT_Encode4(0), GIMT_Encode4(0), GIMT_Encode4(0), GIMT_Encode4(0), GIMT_Encode4(0), GIMT_Encode4(0), GIMT_Encode4(0), GIMT_Encode4(0), GIMT_Encode4(0), GIMT_Encode4(0), GIMT_Encode4(0), GIMT_Encode4(0), GIMT_Encode4(0), GIMT_Encode4(0), GIMT_Encode4(0), GIMT_Encode4(0), GIMT_Encode4(0), GIMT_Encode4(0), GIMT_Encode4(0), GIMT_Encode4(0), GIMT_Encode4(0), GIMT_Encode4(0), GIMT_Encode4(0), GIMT_Encode4(0), GIMT_Encode4(0), GIMT_Encode4(0), GIMT_Encode4(0), GIMT_Encode4(0), GIMT_Encode4(0), GIMT_Encode4(0), GIMT_Encode4(0), GIMT_Encode4(0), GIMT_Encode4(0), GIMT_Encode4(0), GIMT_Encode4(0), GIMT_Encode4(0), GIMT_Encode4(0), GIMT_Encode4(0), GIMT_Encode4(0), GIMT_Encode4(0), GIMT_Encode4(0), GIMT_Encode4(0), GIMT_Encode4(0), GIMT_Encode4(0), GIMT_Encode4(0), GIMT_Encode4(0), GIMT_Encode4(0), GIMT_Encode4(0), GIMT_Encode4(0), GIMT_Encode4(0), GIMT_Encode4(0), GIMT_Encode4(0), GIMT_Encode4(0), GIMT_Encode4(0), GIMT_Encode4(0), GIMT_Encode4(0), GIMT_Encode4(0), GIMT_Encode4(0), GIMT_Encode4(0), GIMT_Encode4(0), GIMT_Encode4(0), GIMT_Encode4(0), GIMT_Encode4(0), GIMT_Encode4(0), GIMT_Encode4(0), GIMT_Encode4(0), GIMT_Encode4(0), GIMT_Encode4(0), GIMT_Encode4(0), GIMT_Encode4(0), GIMT_Encode4(0), GIMT_Encode4(0), GIMT_Encode4(0), GIMT_Encode4(0), GIMT_Encode4(0), GIMT_Encode4(0), GIMT_Encode4(0), GIMT_Encode4(0), GIMT_Encode4(0), GIMT_Encode4(0), GIMT_Encode4(0), GIMT_Encode4(0), GIMT_Encode4(0), GIMT_Encode4(0), GIMT_Encode4(0), GIMT_Encode4(0), GIMT_Encode4(0), GIMT_Encode4(0), GIMT_Encode4(0), GIMT_Encode4(0), GIMT_Encode4(0), GIMT_Encode4(0), GIMT_Encode4(0), GIMT_Encode4(0), GIMT_Encode4(0), GIMT_Encode4(0), GIMT_Encode4(0), GIMT_Encode4(0), GIMT_Encode4(0), GIMT_Encode4(0), GIMT_Encode4(0), GIMT_Encode4(0), GIMT_Encode4(0), GIMT_Encode4(0), GIMT_Encode4(0), GIMT_Encode4(0), GIMT_Encode4(0), GIMT_Encode4(0),
    /*AMDGPU::G_AMDGPU_ATOMIC_CMPXCHG*//*Label 103*/ GIMT_Encode4(408840),
    /*AMDGPU::G_AMDGPU_ATOMIC_FMAX*//*Label 104*/ GIMT_Encode4(411338),
    /*AMDGPU::G_AMDGPU_ATOMIC_FMIN*//*Label 105*/ GIMT_Encode4(413237),
    /*AMDGPU::G_AMDGPU_BUFFER_ATOMIC_ADD*//*Label 106*/ GIMT_Encode4(415136),
    /*AMDGPU::G_AMDGPU_BUFFER_ATOMIC_AND*//*Label 107*/ GIMT_Encode4(417930),
    /*AMDGPU::G_AMDGPU_BUFFER_ATOMIC_CMPSWAP*//*Label 108*/ GIMT_Encode4(420724),
    /*AMDGPU::G_AMDGPU_BUFFER_ATOMIC_COND_SUB_U32*//*Label 109*/ GIMT_Encode4(425270),
    /*AMDGPU::G_AMDGPU_BUFFER_ATOMIC_DEC*//*Label 110*/ GIMT_Encode4(425993),
    /*AMDGPU::G_AMDGPU_BUFFER_ATOMIC_FADD*//*Label 111*/ GIMT_Encode4(428787),
    /*AMDGPU::G_AMDGPU_BUFFER_ATOMIC_FADD_BF16*//*Label 112*/ GIMT_Encode4(433044),
    /*AMDGPU::G_AMDGPU_BUFFER_ATOMIC_FMAX*//*Label 113*/ GIMT_Encode4(433767),
    /*AMDGPU::G_AMDGPU_BUFFER_ATOMIC_FMIN*//*Label 114*/ GIMT_Encode4(437993),
    /*AMDGPU::G_AMDGPU_BUFFER_ATOMIC_INC*//*Label 115*/ GIMT_Encode4(442219),
    /*AMDGPU::G_AMDGPU_BUFFER_ATOMIC_OR*//*Label 116*/ GIMT_Encode4(445013),
    /*AMDGPU::G_AMDGPU_BUFFER_ATOMIC_SMAX*//*Label 117*/ GIMT_Encode4(447807),
    /*AMDGPU::G_AMDGPU_BUFFER_ATOMIC_SMIN*//*Label 118*/ GIMT_Encode4(450601),
    /*AMDGPU::G_AMDGPU_BUFFER_ATOMIC_SUB*//*Label 119*/ GIMT_Encode4(453395),
    /*AMDGPU::G_AMDGPU_BUFFER_ATOMIC_SWAP*//*Label 120*/ GIMT_Encode4(456189),
    /*AMDGPU::G_AMDGPU_BUFFER_ATOMIC_UMAX*//*Label 121*/ GIMT_Encode4(460343),
    /*AMDGPU::G_AMDGPU_BUFFER_ATOMIC_UMIN*//*Label 122*/ GIMT_Encode4(463137),
    /*AMDGPU::G_AMDGPU_BUFFER_ATOMIC_XOR*//*Label 123*/ GIMT_Encode4(465931),
    /*AMDGPU::G_AMDGPU_BUFFER_LOAD*//*Label 124*/ GIMT_Encode4(468725),
    /*AMDGPU::G_AMDGPU_BUFFER_LOAD_FORMAT*//*Label 125*/ GIMT_Encode4(477149),
    /*AMDGPU::G_AMDGPU_BUFFER_LOAD_FORMAT_D16*//*Label 126*/ GIMT_Encode4(482781),
    /*AMDGPU::G_AMDGPU_BUFFER_LOAD_FORMAT_TFE*//*Label 127*/ GIMT_Encode4(491648),
    /*AMDGPU::G_AMDGPU_BUFFER_LOAD_SBYTE*//*Label 128*/ GIMT_Encode4(494540),
    /*AMDGPU::G_AMDGPU_BUFFER_LOAD_SSHORT*//*Label 129*/ GIMT_Encode4(495240),
    /*AMDGPU::G_AMDGPU_BUFFER_LOAD_UBYTE*//*Label 130*/ GIMT_Encode4(495940),
    /*AMDGPU::G_AMDGPU_BUFFER_LOAD_USHORT*//*Label 131*/ GIMT_Encode4(496640),
    /*AMDGPU::G_AMDGPU_BUFFER_STORE*//*Label 132*/ GIMT_Encode4(497340),
    /*AMDGPU::G_AMDGPU_BUFFER_STORE_BYTE*//*Label 133*/ GIMT_Encode4(505734),
    /*AMDGPU::G_AMDGPU_BUFFER_STORE_FORMAT*//*Label 134*/ GIMT_Encode4(506429),
    /*AMDGPU::G_AMDGPU_BUFFER_STORE_FORMAT_D16*//*Label 135*/ GIMT_Encode4(512041),
    /*AMDGPU::G_AMDGPU_BUFFER_STORE_SHORT*//*Label 136*/ GIMT_Encode4(519214),
    /*AMDGPU::G_AMDGPU_CLAMP*//*Label 137*/ GIMT_Encode4(519909),
    /*AMDGPU::G_AMDGPU_CVT_F32_UBYTE0*//*Label 138*/ GIMT_Encode4(520925),
    /*AMDGPU::G_AMDGPU_CVT_F32_UBYTE1*//*Label 139*/ GIMT_Encode4(520979),
    /*AMDGPU::G_AMDGPU_CVT_F32_UBYTE2*//*Label 140*/ GIMT_Encode4(521033),
    /*AMDGPU::G_AMDGPU_CVT_F32_UBYTE3*//*Label 141*/ GIMT_Encode4(521087),
    /*AMDGPU::G_AMDGPU_CVT_PK_I16_I32*//*Label 142*/ GIMT_Encode4(521141),
    /*AMDGPU::G_AMDGPU_FFBH_U32*//*Label 143*/ GIMT_Encode4(521176),
    /*AMDGPU::G_AMDGPU_FFBL_B32*//*Label 144*/ GIMT_Encode4(521291),
    /*AMDGPU::G_AMDGPU_FMAX_LEGACY*//*Label 145*/ GIMT_Encode4(521402),
    /*AMDGPU::G_AMDGPU_FMED3*//*Label 146*/ GIMT_Encode4(521485),
    /*AMDGPU::G_AMDGPU_FMIN_LEGACY*//*Label 147*/ GIMT_Encode4(521701), GIMT_Encode4(0), GIMT_Encode4(0), GIMT_Encode4(0), GIMT_Encode4(0), GIMT_Encode4(0), GIMT_Encode4(0), GIMT_Encode4(0),
    /*AMDGPU::G_AMDGPU_RCP_IFLAG*//*Label 148*/ GIMT_Encode4(521784),
    /*AMDGPU::G_AMDGPU_SMED3*//*Label 149*/ GIMT_Encode4(521843),
    /*AMDGPU::G_AMDGPU_S_BUFFER_LOAD*//*Label 150*/ GIMT_Encode4(522015),
    /*AMDGPU::G_AMDGPU_S_BUFFER_LOAD_SBYTE*//*Label 151*/ GIMT_Encode4(524847),
    /*AMDGPU::G_AMDGPU_S_BUFFER_LOAD_SSHORT*//*Label 152*/ GIMT_Encode4(525015),
    /*AMDGPU::G_AMDGPU_S_BUFFER_LOAD_UBYTE*//*Label 153*/ GIMT_Encode4(525183),
    /*AMDGPU::G_AMDGPU_S_BUFFER_LOAD_USHORT*//*Label 154*/ GIMT_Encode4(525351), GIMT_Encode4(0), GIMT_Encode4(0),
    /*AMDGPU::G_AMDGPU_TBUFFER_LOAD_FORMAT*//*Label 155*/ GIMT_Encode4(525519),
    /*AMDGPU::G_AMDGPU_TBUFFER_LOAD_FORMAT_D16*//*Label 156*/ GIMT_Encode4(531727),
    /*AMDGPU::G_AMDGPU_TBUFFER_STORE_FORMAT*//*Label 157*/ GIMT_Encode4(537866),
    /*AMDGPU::G_AMDGPU_TBUFFER_STORE_FORMAT_D16*//*Label 158*/ GIMT_Encode4(544054),
    /*AMDGPU::G_AMDGPU_UMED3*//*Label 159*/ GIMT_Encode4(549259), GIMT_Encode4(0),
    /*AMDGPU::G_FPTRUNC_ROUND_DOWNWARD*//*Label 160*/ GIMT_Encode4(549431),
    /*AMDGPU::G_FPTRUNC_ROUND_UPWARD*//*Label 161*/ GIMT_Encode4(549466),
    // Label 0: @14538
    GIM_SwitchType, /*MI*/0, /*Op*/0, /*[*/GIMT_Encode2(7), GIMT_Encode2(12), /*)*//*default:*//*Label 168*/ GIMT_Encode4(17046),
    /*GILLT_s1*//*Label 163*/ GIMT_Encode4(14569),
    /*GILLT_s16*//*Label 164*/ GIMT_Encode4(14712),
    /*GILLT_s32*//*Label 165*/ GIMT_Encode4(15036),
    /*GILLT_s64*//*Label 166*/ GIMT_Encode4(16730),
    /*GILLT_v2s16*//*Label 167*/ GIMT_Encode4(16965),
    // Label 163: @14569
    GIM_Try, /*On fail goto*//*Label 169*/ GIMT_Encode4(14711),
      GIM_CheckType, /*MI*/0, /*Op*/1, /*Type*/GILLT_s1,
      GIM_CheckType, /*MI*/0, /*Op*/2, /*Type*/GILLT_s1,
      GIM_Try, /*On fail goto*//*Label 170*/ GIMT_Encode4(14619), // Rule ID 6359 //
        GIM_CheckFeatures, GIMT_Encode2(GIFBS_isWave64),
        GIM_CheckRegBankForClass, /*MI*/0, /*Op*/0, /*RC*/GIMT_Encode2(AMDGPU::SReg_64RegClassID),
        GIM_CheckConstantInt8, /*MI*/0, /*Op*/2, uint8_t(-1),
        // (add:{ *:[i1] } i1:{ *:[i1] }:$src0, -1:{ *:[i1] })  =>  (S_NOT_B64:{ *:[i1] }:{ *:[i1] } ?:{ *:[i1] }:$src0)
        GIR_BuildMI, /*InsnID*/0, /*Opcode*/GIMT_Encode2(AMDGPU::S_NOT_B64),
        GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/0, // DstI[sdst]
        GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/1, // src0
        GIR_SetImplicitDefDead, /*InsnID*/0, /*OpIdx for AMDGPU::SCC*/0,
        GIR_ConstrainSelectedInstOperands, /*InsnID*/0,
        GIR_EraseFromParent, /*InsnID*/0,
        // GIR_Coverage, 6359,
        GIR_Done,
      // Label 170: @14619
      GIM_Try, /*On fail goto*//*Label 171*/ GIMT_Encode4(14656), // Rule ID 6366 //
        GIM_CheckFeatures, GIMT_Encode2(GIFBS_isWave32),
        GIM_CheckRegBankForClass, /*MI*/0, /*Op*/0, /*RC*/GIMT_Encode2(AMDGPU::SReg_32RegClassID),
        GIM_CheckConstantInt8, /*MI*/0, /*Op*/2, uint8_t(-1),
        // (add:{ *:[i1] } i1:{ *:[i1] }:$src0, -1:{ *:[i1] })  =>  (S_NOT_B32:{ *:[i1] }:{ *:[i1] } ?:{ *:[i1] }:$src0)
        GIR_BuildMI, /*InsnID*/0, /*Opcode*/GIMT_Encode2(AMDGPU::S_NOT_B32),
        GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/0, // DstI[sdst]
        GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/1, // src0
        GIR_SetImplicitDefDead, /*InsnID*/0, /*OpIdx for AMDGPU::SCC*/0,
        GIR_ConstrainSelectedInstOperands, /*InsnID*/0,
        GIR_EraseFromParent, /*InsnID*/0,
        // GIR_Coverage, 6366,
        GIR_Done,
      // Label 171: @14656
      GIM_Try, /*On fail goto*//*Label 172*/ GIMT_Encode4(14683), // Rule ID 6357 //
        GIM_CheckFeatures, GIMT_Encode2(GIFBS_isWave64),
        GIM_CheckRegBankForClass, /*MI*/0, /*Op*/0, /*RC*/GIMT_Encode2(AMDGPU::SReg_64RegClassID),
        // (add:{ *:[i1] } i1:{ *:[i1] }:$src0, i1:{ *:[i1] }:$src1)  =>  (S_XOR_B64:{ *:[i1] }:{ *:[i1] } ?:{ *:[i1] }:$src0, ?:{ *:[i1] }:$src1)
        GIR_MutateOpcode, /*InsnID*/0, /*RecycleInsnID*/0, /*Opcode*/GIMT_Encode2(AMDGPU::S_XOR_B64),
        GIR_AddImplicitDef, /*InsnID*/0, GIMT_Encode2(AMDGPU::SCC), GIMT_Encode2(RegState::Dead),
        GIR_ConstrainSelectedInstOperands, /*InsnID*/0,
        // GIR_Coverage, 6357,
        GIR_Done,
      // Label 172: @14683
      GIM_Try, /*On fail goto*//*Label 173*/ GIMT_Encode4(14710), // Rule ID 6364 //
        GIM_CheckFeatures, GIMT_Encode2(GIFBS_isWave32),
        GIM_CheckRegBankForClass, /*MI*/0, /*Op*/0, /*RC*/GIMT_Encode2(AMDGPU::SReg_32RegClassID),
        // (add:{ *:[i1] } i1:{ *:[i1] }:$src0, i1:{ *:[i1] }:$src1)  =>  (S_XOR_B32:{ *:[i1] }:{ *:[i1] } ?:{ *:[i1] }:$src0, ?:{ *:[i1] }:$src1)
        GIR_MutateOpcode, /*InsnID*/0, /*RecycleInsnID*/0, /*Opcode*/GIMT_Encode2(AMDGPU::S_XOR_B32),
        GIR_AddImplicitDef, /*InsnID*/0, GIMT_Encode2(AMDGPU::SCC), GIMT_Encode2(RegState::Dead),
        GIR_ConstrainSelectedInstOperands, /*InsnID*/0,
        // GIR_Coverage, 6364,
        GIR_Done,
      // Label 173: @14710
      GIM_Reject,
    // Label 169: @14711
    GIM_Reject,
    // Label 164: @14712
    GIM_Try, /*On fail goto*//*Label 174*/ GIMT_Encode4(15035),
      GIM_CheckType, /*MI*/0, /*Op*/1, /*Type*/GILLT_s16,
      GIM_CheckType, /*MI*/0, /*Op*/2, /*Type*/GILLT_s16,
      GIM_CheckRegBankForClass, /*MI*/0, /*Op*/0, /*RC*/GIMT_Encode2(AMDGPU::VGPR_32RegClassID),
      GIM_Try, /*On fail goto*//*Label 175*/ GIMT_Encode4(14777), // Rule ID 2132 //
        GIM_CheckFeatures, GIMT_Encode2(GIFBS_Has16BitInsts_isGFX8GFX9),
        GIM_RecordInsn, /*DefineMI*/1, /*MI*/0, /*OpIdx*/2, // MIs[1]
        GIM_CheckOpcode, /*MI*/1, GIMT_Encode2(TargetOpcode::G_CONSTANT),
        GIM_CheckI64ImmPredicate, /*MI*/1, /*Predicate*/GIMT_Encode2(GICXXPred_I64_Predicate_NegSubInlineIntConst16),
        // MIs[1] Operand 1
        // No operand predicates
        GIM_CheckIsSafeToFold, /*InsnID*/1,
        // (add:{ *:[i16] } i16:{ *:[i16] }:$src0, (imm:{ *:[i16] })<<P:Predicate_NegSubInlineIntConst16>><<X:NegateImm>>:$src1)  =>  (V_SUB_U16_e64:{ *:[i16] } VSrc_b16:{ *:[i16] }:$src0, (NegateImm:{ *:[i16 i32 bf16 f16 f32 v2i16 v2f16 v2bf16] } (imm:{ *:[i16] })<<P:Predicate_NegSubInlineIntConst16>>:$src1))
        GIR_BuildMI, /*InsnID*/0, /*Opcode*/GIMT_Encode2(AMDGPU::V_SUB_U16_e64),
        GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/0, // DstI[vdst]
        GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/1, // src0
        GIR_CustomRenderer, /*InsnID*/0, /*OldInsnID*/1, /*Renderer*/GIMT_Encode2(GICR_renderNegateImm), // src1
        GIR_AddImm8, /*InsnID*/0, /*Imm*/0,
        GIR_ConstrainSelectedInstOperands, /*InsnID*/0,
        GIR_EraseFromParent, /*InsnID*/0,
        // GIR_Coverage, 2132,
        GIR_Done,
      // Label 175: @14777
      GIM_Try, /*On fail goto*//*Label 176*/ GIMT_Encode4(14833), // Rule ID 2215 //
        GIM_CheckFeatures, GIMT_Encode2(GIFBS_isGFX10Plus),
        GIM_RecordInsn, /*DefineMI*/1, /*MI*/0, /*OpIdx*/2, // MIs[1]
        GIM_CheckOpcode, /*MI*/1, GIMT_Encode2(TargetOpcode::G_CONSTANT),
        GIM_CheckI64ImmPredicate, /*MI*/1, /*Predicate*/GIMT_Encode2(GICXXPred_I64_Predicate_NegSubInlineIntConst16),
        // MIs[1] Operand 1
        // No operand predicates
        GIM_CheckIsSafeToFold, /*InsnID*/1,
        // (add:{ *:[i16] } i16:{ *:[i16] }:$src0, (imm:{ *:[i16] })<<P:Predicate_NegSubInlineIntConst16>><<X:NegateImm>>:$src1)  =>  (V_SUB_NC_U16_e64:{ *:[i16] } 0:{ *:[i32] }, VSrc_b16:{ *:[i16] }:$src0, 0:{ *:[i32] }, (NegateImm:{ *:[i16 i32 bf16 f16 f32 v2i16 v2f16 v2bf16] } (imm:{ *:[i16] })<<P:Predicate_NegSubInlineIntConst16>>:$src1), 0:{ *:[i1] }, 0:{ *:[i32] })
        GIR_BuildMI, /*InsnID*/0, /*Opcode*/GIMT_Encode2(AMDGPU::V_SUB_NC_U16_e64),
        GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/0, // DstI[vdst]
        GIR_AddImm8, /*InsnID*/0, /*Imm*/0,
        GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/1, // src0
        GIR_AddImm8, /*InsnID*/0, /*Imm*/0,
        GIR_CustomRenderer, /*InsnID*/0, /*OldInsnID*/1, /*Renderer*/GIMT_Encode2(GICR_renderNegateImm), // src1
        GIR_AddImm8, /*InsnID*/0, /*Imm*/0,
        GIR_AddImm8, /*InsnID*/0, /*Imm*/0,
        GIR_ConstrainSelectedInstOperands, /*InsnID*/0,
        GIR_EraseFromParent, /*InsnID*/0,
        // GIR_Coverage, 2215,
        GIR_Done,
      // Label 176: @14833
      GIM_Try, /*On fail goto*//*Label 177*/ GIMT_Encode4(14887), // Rule ID 2170 //
        GIM_CheckFeatures, GIMT_Encode2(GIFBS_Has16BitInsts_isGFX6GFX7GFX8GFX9),
        GIM_RecordInsn, /*DefineMI*/1, /*MI*/0, /*OpIdx*/1, // MIs[1]
        GIM_CheckOpcode, /*MI*/1, GIMT_Encode2(TargetOpcode::G_MUL),
        GIM_CheckType, /*MI*/1, /*Op*/1, /*Type*/GILLT_s16,
        GIM_CheckType, /*MI*/1, /*Op*/2, /*Type*/GILLT_s16,
        GIM_CheckIsSafeToFold, /*InsnID*/1,
        // (add:{ *:[i16] } (mul:{ *:[i16] } i16:{ *:[i16] }:$src0, i16:{ *:[i16] }:$src1), i16:{ *:[i16] }:$src2)  =>  (V_MAD_U16_e64:{ *:[i16] } i16:{ *:[i16] }:$src0, i16:{ *:[i16] }:$src1, i16:{ *:[i16] }:$src2, 0:{ *:[i1] })
        GIR_BuildMI, /*InsnID*/0, /*Opcode*/GIMT_Encode2(AMDGPU::V_MAD_U16_e64),
        GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/0, // DstI[vdst]
        GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/1, /*OpIdx*/1, // src0
        GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/1, /*OpIdx*/2, // src1
        GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/2, // src2
        GIR_AddImm8, /*InsnID*/0, /*Imm*/0,
        GIR_ConstrainSelectedInstOperands, /*InsnID*/0,
        GIR_EraseFromParent, /*InsnID*/0,
        // GIR_Coverage, 2170,
        GIR_Done,
      // Label 177: @14887
      GIM_Try, /*On fail goto*//*Label 178*/ GIMT_Encode4(14941), // Rule ID 7207 //
        GIM_CheckFeatures, GIMT_Encode2(GIFBS_Has16BitInsts_isGFX6GFX7GFX8GFX9),
        GIM_RecordInsn, /*DefineMI*/1, /*MI*/0, /*OpIdx*/2, // MIs[1]
        GIM_CheckOpcode, /*MI*/1, GIMT_Encode2(TargetOpcode::G_MUL),
        GIM_CheckType, /*MI*/1, /*Op*/1, /*Type*/GILLT_s16,
        GIM_CheckType, /*MI*/1, /*Op*/2, /*Type*/GILLT_s16,
        GIM_CheckIsSafeToFold, /*InsnID*/1,
        // (add:{ *:[i16] } i16:{ *:[i16] }:$src2, (mul:{ *:[i16] } i16:{ *:[i16] }:$src0, i16:{ *:[i16] }:$src1))  =>  (V_MAD_U16_e64:{ *:[i16] } i16:{ *:[i16] }:$src0, i16:{ *:[i16] }:$src1, i16:{ *:[i16] }:$src2, 0:{ *:[i1] })
        GIR_BuildMI, /*InsnID*/0, /*Opcode*/GIMT_Encode2(AMDGPU::V_MAD_U16_e64),
        GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/0, // DstI[vdst]
        GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/1, /*OpIdx*/1, // src0
        GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/1, /*OpIdx*/2, // src1
        GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/1, // src2
        GIR_AddImm8, /*InsnID*/0, /*Imm*/0,
        GIR_ConstrainSelectedInstOperands, /*InsnID*/0,
        GIR_EraseFromParent, /*InsnID*/0,
        // GIR_Coverage, 7207,
        GIR_Done,
      // Label 178: @14941
      GIM_Try, /*On fail goto*//*Label 179*/ GIMT_Encode4(15002), // Rule ID 944 //
        GIM_CheckFeatures, GIMT_Encode2(GIFBS_isGFX10Plus),
        GIM_CheckComplexPattern, /*MI*/0, /*Op*/1, /*Renderer*/GIMT_Encode2(0), GIMT_Encode2(GICP_gi_vop3opselmods),
        GIM_CheckComplexPattern, /*MI*/0, /*Op*/2, /*Renderer*/GIMT_Encode2(1), GIMT_Encode2(GICP_gi_vop3opselmods),
        // (add:{ *:[i16] } (VOP3OpSelMods:{ *:[i16] } i16:{ *:[i16] }:$src0, i32:{ *:[i32] }:$src0_modifiers), (VOP3OpSelMods:{ *:[i16] } i16:{ *:[i16] }:$src1, i32:{ *:[i32] }:$src1_modifiers))  =>  (V_ADD_NC_U16_e64:{ *:[i16] } i32:{ *:[i32] }:$src0_modifiers, i16:{ *:[i16] }:$src0, i32:{ *:[i32] }:$src1_modifiers, i16:{ *:[i16] }:$src1)
        GIR_BuildMI, /*InsnID*/0, /*Opcode*/GIMT_Encode2(AMDGPU::V_ADD_NC_U16_e64),
        GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/0, // DstI[vdst]
        GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/1, // src0_modifiers
        GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/0, // src0
        GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(1), /*SubOperand*/1, // src1_modifiers
        GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(1), /*SubOperand*/0, // src1
        GIR_AddImm8, /*InsnID*/0, /*Imm*/0,
        GIR_AddImm8, /*InsnID*/0, /*Imm*/0,
        GIR_ConstrainSelectedInstOperands, /*InsnID*/0,
        GIR_EraseFromParent, /*InsnID*/0,
        // GIR_Coverage, 944,
        GIR_Done,
      // Label 179: @15002
      GIM_Try, /*On fail goto*//*Label 180*/ GIMT_Encode4(15034), // Rule ID 836 //
        GIM_CheckFeatures, GIMT_Encode2(GIFBS_isGFX8GFX9),
        // (add:{ *:[i16] } i16:{ *:[i16] }:$src0, i16:{ *:[i16] }:$src1)  =>  (V_ADD_U16_e64:{ *:[i16] } i16:{ *:[i16] }:$src0, i16:{ *:[i16] }:$src1)
        GIR_BuildMI, /*InsnID*/0, /*Opcode*/GIMT_Encode2(AMDGPU::V_ADD_U16_e64),
        GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/0, // DstI[vdst]
        GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/1, // src0
        GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/2, // src1
        GIR_AddImm8, /*InsnID*/0, /*Imm*/0,
        GIR_ConstrainSelectedInstOperands, /*InsnID*/0,
        GIR_EraseFromParent, /*InsnID*/0,
        // GIR_Coverage, 836,
        GIR_Done,
      // Label 180: @15034
      GIM_Reject,
    // Label 174: @15035
    GIM_Reject,
    // Label 165: @15036
    GIM_Try, /*On fail goto*//*Label 181*/ GIMT_Encode4(16729),
      GIM_CheckType, /*MI*/0, /*Op*/1, /*Type*/GILLT_s32,
      GIM_CheckType, /*MI*/0, /*Op*/2, /*Type*/GILLT_s32,
      GIM_Try, /*On fail goto*//*Label 182*/ GIMT_Encode4(15157), // Rule ID 2185 //
        GIM_CheckFeatures, GIMT_Encode2(GIFBS_isGFX9Plus),
        GIM_CheckRegBankForClass, /*MI*/0, /*Op*/0, /*RC*/GIMT_Encode2(AMDGPU::VGPR_32RegClassID),
        GIM_RecordInsn, /*DefineMI*/1, /*MI*/0, /*OpIdx*/1, // MIs[1]
        GIM_CheckOpcode, /*MI*/1, GIMT_Encode2(TargetOpcode::G_SHL),
        GIM_CheckType, /*MI*/1, /*Op*/1, /*Type*/GILLT_s32,
        GIM_CheckType, /*MI*/1, /*Op*/2, /*Type*/GILLT_s32,
        GIM_RecordNamedOperand, /*MI*/1, /*Op*/1, /*StoreIdx*/0, // Name : pred:1:x
        GIM_RecordInsn, /*DefineMI*/2, /*MI*/1, /*OpIdx*/2, // MIs[2]
        GIM_CheckOpcode, /*MI*/2, GIMT_Encode2(TargetOpcode::G_AND),
        GIM_CheckType, /*MI*/2, /*Op*/1, /*Type*/GILLT_s32,
        GIM_CheckType, /*MI*/2, /*Op*/2, /*Type*/GILLT_s32,
        GIM_RecordNamedOperand, /*MI*/2, /*Op*/1, /*StoreIdx*/1, // Name : pred:1:y
        GIM_RecordInsn, /*DefineMI*/3, /*MI*/2, /*OpIdx*/2, // MIs[3]
        GIM_CheckOpcode, /*MI*/3, GIMT_Encode2(TargetOpcode::G_CONSTANT),
        // MIs[3] Operand 1
        // No operand predicates
        GIM_CheckCxxInsnPredicate, /*MI*/2, /*FnId*/GIMT_Encode2(GICXXPred_MI_Predicate_csh_mask_32),
        GIM_CheckCxxInsnPredicate, /*MI*/1, /*FnId*/GIMT_Encode2(GICXXPred_MI_Predicate_anonymous_23603),
        GIM_RecordNamedOperand, /*MI*/0, /*Op*/2, /*StoreIdx*/2, // Name : pred:1:z
        GIM_CheckCxxInsnPredicate, /*MI*/0, /*FnId*/GIMT_Encode2(GICXXPred_MI_Predicate_anonymous_23602),
        GIM_CheckIsSafeToFold, /*InsnID*/1,
        GIM_CheckIsSafeToFold, /*InsnID*/2,
        GIM_CheckIsSafeToFold, /*InsnID*/3,
        // (add:{ *:[i32] } (shl:{ *:[i32] } i32:{ *:[i32] }:$src0:$pred:1:x, (and:{ *:[i32] } i32:{ *:[i32] }:$src1:$pred:1:y, (imm:{ *:[i32] }))<<P:Predicate_csh_mask_32>>)<<P:Predicate_anonymous_23603>>, i32:{ *:[i32] }:$src2:$pred:1:z)<<P:1:Predicate_anonymous_23602>>  =>  (V_LSHL_ADD_U32_e64:{ *:[i32] } VSrc_b32:{ *:[i32] }:$src0, VSrc_b32:{ *:[i32] }:$src1, VSrc_b32:{ *:[i32] }:$src2)
        GIR_BuildMI, /*InsnID*/0, /*Opcode*/GIMT_Encode2(AMDGPU::V_LSHL_ADD_U32_e64),
        GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/0, // DstI[vdst]
        GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/1, /*OpIdx*/1, // src0
        GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/2, /*OpIdx*/1, // src1
        GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/2, // src2
        GIR_ConstrainSelectedInstOperands, /*InsnID*/0,
        GIR_EraseFromParent, /*InsnID*/0,
        // GIR_Coverage, 2185,
        GIR_Done,
      // Label 182: @15157
      GIM_Try, /*On fail goto*//*Label 183*/ GIMT_Encode4(15265), // Rule ID 7210 //
        GIM_CheckFeatures, GIMT_Encode2(GIFBS_isGFX9Plus),
        GIM_CheckRegBankForClass, /*MI*/0, /*Op*/0, /*RC*/GIMT_Encode2(AMDGPU::VGPR_32RegClassID),
        GIM_RecordNamedOperand, /*MI*/0, /*Op*/1, /*StoreIdx*/2, // Name : pred:1:z
        GIM_RecordInsn, /*DefineMI*/1, /*MI*/0, /*OpIdx*/2, // MIs[1]
        GIM_CheckOpcode, /*MI*/1, GIMT_Encode2(TargetOpcode::G_SHL),
        GIM_CheckType, /*MI*/1, /*Op*/1, /*Type*/GILLT_s32,
        GIM_CheckType, /*MI*/1, /*Op*/2, /*Type*/GILLT_s32,
        GIM_RecordNamedOperand, /*MI*/1, /*Op*/1, /*StoreIdx*/0, // Name : pred:1:x
        GIM_RecordInsn, /*DefineMI*/2, /*MI*/1, /*OpIdx*/2, // MIs[2]
        GIM_CheckOpcode, /*MI*/2, GIMT_Encode2(TargetOpcode::G_AND),
        GIM_CheckType, /*MI*/2, /*Op*/1, /*Type*/GILLT_s32,
        GIM_CheckType, /*MI*/2, /*Op*/2, /*Type*/GILLT_s32,
        GIM_RecordNamedOperand, /*MI*/2, /*Op*/1, /*StoreIdx*/1, // Name : pred:1:y
        GIM_RecordInsn, /*DefineMI*/3, /*MI*/2, /*OpIdx*/2, // MIs[3]
        GIM_CheckOpcode, /*MI*/3, GIMT_Encode2(TargetOpcode::G_CONSTANT),
        // MIs[3] Operand 1
        // No operand predicates
        GIM_CheckCxxInsnPredicate, /*MI*/2, /*FnId*/GIMT_Encode2(GICXXPred_MI_Predicate_csh_mask_32),
        GIM_CheckCxxInsnPredicate, /*MI*/1, /*FnId*/GIMT_Encode2(GICXXPred_MI_Predicate_anonymous_23603),
        GIM_CheckCxxInsnPredicate, /*MI*/0, /*FnId*/GIMT_Encode2(GICXXPred_MI_Predicate_anonymous_23602),
        GIM_CheckIsSafeToFold, /*InsnID*/1,
        GIM_CheckIsSafeToFold, /*InsnID*/2,
        GIM_CheckIsSafeToFold, /*InsnID*/3,
        // (add:{ *:[i32] } i32:{ *:[i32] }:$src2:$pred:1:z, (shl:{ *:[i32] } i32:{ *:[i32] }:$src0:$pred:1:x, (and:{ *:[i32] } i32:{ *:[i32] }:$src1:$pred:1:y, (imm:{ *:[i32] }))<<P:Predicate_csh_mask_32>>)<<P:Predicate_anonymous_23603>>)<<P:1:Predicate_anonymous_23602>>  =>  (V_LSHL_ADD_U32_e64:{ *:[i32] } VSrc_b32:{ *:[i32] }:$src0, VSrc_b32:{ *:[i32] }:$src1, VSrc_b32:{ *:[i32] }:$src2)
        GIR_BuildMI, /*InsnID*/0, /*Opcode*/GIMT_Encode2(AMDGPU::V_LSHL_ADD_U32_e64),
        GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/0, // DstI[vdst]
        GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/1, /*OpIdx*/1, // src0
        GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/2, /*OpIdx*/1, // src1
        GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/1, // src2
        GIR_ConstrainSelectedInstOperands, /*InsnID*/0,
        GIR_EraseFromParent, /*InsnID*/0,
        // GIR_Coverage, 7210,
        GIR_Done,
      // Label 183: @15265
      GIM_Try, /*On fail goto*//*Label 184*/ GIMT_Encode4(15342), // Rule ID 84 //
        GIM_CheckFeatures, GIMT_Encode2(GIFBS_isGFX9Plus),
        GIM_CheckRegBankForClass, /*MI*/0, /*Op*/0, /*RC*/GIMT_Encode2(AMDGPU::SReg_32RegClassID),
        GIM_RecordInsn, /*DefineMI*/1, /*MI*/0, /*OpIdx*/1, // MIs[1]
        GIM_CheckOpcode, /*MI*/1, GIMT_Encode2(TargetOpcode::G_SHL),
        GIM_CheckType, /*MI*/1, /*Op*/1, /*Type*/GILLT_s32,
        GIM_CheckType, /*MI*/1, /*Op*/2, /*Type*/GILLT_s32,
        GIM_CheckRegBankForClass, /*MI*/1, /*Op*/1, /*RC*/GIMT_Encode2(AMDGPU::SReg_32RegClassID),
        GIM_CheckConstantInt8, /*MI*/1, /*Op*/2, 1,
        GIM_CheckCxxInsnPredicate, /*MI*/1, /*FnId*/GIMT_Encode2(GICXXPred_MI_Predicate_shl_oneuse),
        GIM_CheckRegBankForClass, /*MI*/0, /*Op*/2, /*RC*/GIMT_Encode2(AMDGPU::SReg_32RegClassID),
        GIM_CheckCxxInsnPredicate, /*MI*/0, /*FnId*/GIMT_Encode2(GICXXPred_MI_Predicate_shl1_add),
        GIM_CheckIsSafeToFold, /*InsnID*/1,
        // (add:{ *:[i32] } (shl:{ *:[i32] } SSrc_b32:{ *:[i32] }:$src0, 1:{ *:[i32] })<<P:Predicate_shl_oneuse>>, SSrc_b32:{ *:[i32] }:$src1)<<P:Predicate_shl1_add>>  =>  (S_LSHL1_ADD_U32:{ *:[i32] }:{ *:[i1] } SSrc_b32:{ *:[i32] }:$src0, SSrc_b32:{ *:[i32] }:$src1)
        GIR_BuildMI, /*InsnID*/0, /*Opcode*/GIMT_Encode2(AMDGPU::S_LSHL1_ADD_U32),
        GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/0, // DstI[sdst]
        GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/1, /*OpIdx*/1, // src0
        GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/2, // src1
        GIR_SetImplicitDefDead, /*InsnID*/0, /*OpIdx for AMDGPU::SCC*/0,
        GIR_ConstrainSelectedInstOperands, /*InsnID*/0,
        GIR_EraseFromParent, /*InsnID*/0,
        // GIR_Coverage, 84,
        GIR_Done,
      // Label 184: @15342
      GIM_Try, /*On fail goto*//*Label 185*/ GIMT_Encode4(15419), // Rule ID 85 //
        GIM_CheckFeatures, GIMT_Encode2(GIFBS_isGFX9Plus),
        GIM_CheckRegBankForClass, /*MI*/0, /*Op*/0, /*RC*/GIMT_Encode2(AMDGPU::SReg_32RegClassID),
        GIM_RecordInsn, /*DefineMI*/1, /*MI*/0, /*OpIdx*/1, // MIs[1]
        GIM_CheckOpcode, /*MI*/1, GIMT_Encode2(TargetOpcode::G_SHL),
        GIM_CheckType, /*MI*/1, /*Op*/1, /*Type*/GILLT_s32,
        GIM_CheckType, /*MI*/1, /*Op*/2, /*Type*/GILLT_s32,
        GIM_CheckRegBankForClass, /*MI*/1, /*Op*/1, /*RC*/GIMT_Encode2(AMDGPU::SReg_32RegClassID),
        GIM_CheckConstantInt8, /*MI*/1, /*Op*/2, 2,
        GIM_CheckCxxInsnPredicate, /*MI*/1, /*FnId*/GIMT_Encode2(GICXXPred_MI_Predicate_shl_oneuse),
        GIM_CheckRegBankForClass, /*MI*/0, /*Op*/2, /*RC*/GIMT_Encode2(AMDGPU::SReg_32RegClassID),
        GIM_CheckCxxInsnPredicate, /*MI*/0, /*FnId*/GIMT_Encode2(GICXXPred_MI_Predicate_shl2_add),
        GIM_CheckIsSafeToFold, /*InsnID*/1,
        // (add:{ *:[i32] } (shl:{ *:[i32] } SSrc_b32:{ *:[i32] }:$src0, 2:{ *:[i32] })<<P:Predicate_shl_oneuse>>, SSrc_b32:{ *:[i32] }:$src1)<<P:Predicate_shl2_add>>  =>  (S_LSHL2_ADD_U32:{ *:[i32] }:{ *:[i1] } SSrc_b32:{ *:[i32] }:$src0, SSrc_b32:{ *:[i32] }:$src1)
        GIR_BuildMI, /*InsnID*/0, /*Opcode*/GIMT_Encode2(AMDGPU::S_LSHL2_ADD_U32),
        GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/0, // DstI[sdst]
        GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/1, /*OpIdx*/1, // src0
        GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/2, // src1
        GIR_SetImplicitDefDead, /*InsnID*/0, /*OpIdx for AMDGPU::SCC*/0,
        GIR_ConstrainSelectedInstOperands, /*InsnID*/0,
        GIR_EraseFromParent, /*InsnID*/0,
        // GIR_Coverage, 85,
        GIR_Done,
      // Label 185: @15419
      GIM_Try, /*On fail goto*//*Label 186*/ GIMT_Encode4(15496), // Rule ID 86 //
        GIM_CheckFeatures, GIMT_Encode2(GIFBS_isGFX9Plus),
        GIM_CheckRegBankForClass, /*MI*/0, /*Op*/0, /*RC*/GIMT_Encode2(AMDGPU::SReg_32RegClassID),
        GIM_RecordInsn, /*DefineMI*/1, /*MI*/0, /*OpIdx*/1, // MIs[1]
        GIM_CheckOpcode, /*MI*/1, GIMT_Encode2(TargetOpcode::G_SHL),
        GIM_CheckType, /*MI*/1, /*Op*/1, /*Type*/GILLT_s32,
        GIM_CheckType, /*MI*/1, /*Op*/2, /*Type*/GILLT_s32,
        GIM_CheckRegBankForClass, /*MI*/1, /*Op*/1, /*RC*/GIMT_Encode2(AMDGPU::SReg_32RegClassID),
        GIM_CheckConstantInt8, /*MI*/1, /*Op*/2, 3,
        GIM_CheckCxxInsnPredicate, /*MI*/1, /*FnId*/GIMT_Encode2(GICXXPred_MI_Predicate_shl_oneuse),
        GIM_CheckRegBankForClass, /*MI*/0, /*Op*/2, /*RC*/GIMT_Encode2(AMDGPU::SReg_32RegClassID),
        GIM_CheckCxxInsnPredicate, /*MI*/0, /*FnId*/GIMT_Encode2(GICXXPred_MI_Predicate_shl3_add),
        GIM_CheckIsSafeToFold, /*InsnID*/1,
        // (add:{ *:[i32] } (shl:{ *:[i32] } SSrc_b32:{ *:[i32] }:$src0, 3:{ *:[i32] })<<P:Predicate_shl_oneuse>>, SSrc_b32:{ *:[i32] }:$src1)<<P:Predicate_shl3_add>>  =>  (S_LSHL3_ADD_U32:{ *:[i32] }:{ *:[i1] } SSrc_b32:{ *:[i32] }:$src0, SSrc_b32:{ *:[i32] }:$src1)
        GIR_BuildMI, /*InsnID*/0, /*Opcode*/GIMT_Encode2(AMDGPU::S_LSHL3_ADD_U32),
        GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/0, // DstI[sdst]
        GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/1, /*OpIdx*/1, // src0
        GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/2, // src1
        GIR_SetImplicitDefDead, /*InsnID*/0, /*OpIdx for AMDGPU::SCC*/0,
        GIR_ConstrainSelectedInstOperands, /*InsnID*/0,
        GIR_EraseFromParent, /*InsnID*/0,
        // GIR_Coverage, 86,
        GIR_Done,
      // Label 186: @15496
      GIM_Try, /*On fail goto*//*Label 187*/ GIMT_Encode4(15573), // Rule ID 87 //
        GIM_CheckFeatures, GIMT_Encode2(GIFBS_isGFX9Plus),
        GIM_CheckRegBankForClass, /*MI*/0, /*Op*/0, /*RC*/GIMT_Encode2(AMDGPU::SReg_32RegClassID),
        GIM_RecordInsn, /*DefineMI*/1, /*MI*/0, /*OpIdx*/1, // MIs[1]
        GIM_CheckOpcode, /*MI*/1, GIMT_Encode2(TargetOpcode::G_SHL),
        GIM_CheckType, /*MI*/1, /*Op*/1, /*Type*/GILLT_s32,
        GIM_CheckType, /*MI*/1, /*Op*/2, /*Type*/GILLT_s32,
        GIM_CheckRegBankForClass, /*MI*/1, /*Op*/1, /*RC*/GIMT_Encode2(AMDGPU::SReg_32RegClassID),
        GIM_CheckConstantInt8, /*MI*/1, /*Op*/2, 4,
        GIM_CheckCxxInsnPredicate, /*MI*/1, /*FnId*/GIMT_Encode2(GICXXPred_MI_Predicate_shl_oneuse),
        GIM_CheckRegBankForClass, /*MI*/0, /*Op*/2, /*RC*/GIMT_Encode2(AMDGPU::SReg_32RegClassID),
        GIM_CheckCxxInsnPredicate, /*MI*/0, /*FnId*/GIMT_Encode2(GICXXPred_MI_Predicate_shl4_add),
        GIM_CheckIsSafeToFold, /*InsnID*/1,
        // (add:{ *:[i32] } (shl:{ *:[i32] } SSrc_b32:{ *:[i32] }:$src0, 4:{ *:[i32] })<<P:Predicate_shl_oneuse>>, SSrc_b32:{ *:[i32] }:$src1)<<P:Predicate_shl4_add>>  =>  (S_LSHL4_ADD_U32:{ *:[i32] }:{ *:[i1] } SSrc_b32:{ *:[i32] }:$src0, SSrc_b32:{ *:[i32] }:$src1)
        GIR_BuildMI, /*InsnID*/0, /*Opcode*/GIMT_Encode2(AMDGPU::S_LSHL4_ADD_U32),
        GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/0, // DstI[sdst]
        GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/1, /*OpIdx*/1, // src0
        GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/2, // src1
        GIR_SetImplicitDefDead, /*InsnID*/0, /*OpIdx for AMDGPU::SCC*/0,
        GIR_ConstrainSelectedInstOperands, /*InsnID*/0,
        GIR_EraseFromParent, /*InsnID*/0,
        // GIR_Coverage, 87,
        GIR_Done,
      // Label 187: @15573
      GIM_Try, /*On fail goto*//*Label 188*/ GIMT_Encode4(15650), // Rule ID 7120 //
        GIM_CheckFeatures, GIMT_Encode2(GIFBS_isGFX9Plus),
        GIM_CheckRegBankForClass, /*MI*/0, /*Op*/0, /*RC*/GIMT_Encode2(AMDGPU::SReg_32RegClassID),
        GIM_CheckRegBankForClass, /*MI*/0, /*Op*/1, /*RC*/GIMT_Encode2(AMDGPU::SReg_32RegClassID),
        GIM_RecordInsn, /*DefineMI*/1, /*MI*/0, /*OpIdx*/2, // MIs[1]
        GIM_CheckOpcode, /*MI*/1, GIMT_Encode2(TargetOpcode::G_SHL),
        GIM_CheckType, /*MI*/1, /*Op*/1, /*Type*/GILLT_s32,
        GIM_CheckType, /*MI*/1, /*Op*/2, /*Type*/GILLT_s32,
        GIM_CheckRegBankForClass, /*MI*/1, /*Op*/1, /*RC*/GIMT_Encode2(AMDGPU::SReg_32RegClassID),
        GIM_CheckConstantInt8, /*MI*/1, /*Op*/2, 1,
        GIM_CheckCxxInsnPredicate, /*MI*/1, /*FnId*/GIMT_Encode2(GICXXPred_MI_Predicate_shl_oneuse),
        GIM_CheckCxxInsnPredicate, /*MI*/0, /*FnId*/GIMT_Encode2(GICXXPred_MI_Predicate_shl1_add),
        GIM_CheckIsSafeToFold, /*InsnID*/1,
        // (add:{ *:[i32] } SSrc_b32:{ *:[i32] }:$src1, (shl:{ *:[i32] } SSrc_b32:{ *:[i32] }:$src0, 1:{ *:[i32] })<<P:Predicate_shl_oneuse>>)<<P:Predicate_shl1_add>>  =>  (S_LSHL1_ADD_U32:{ *:[i32] }:{ *:[i1] } SSrc_b32:{ *:[i32] }:$src0, SSrc_b32:{ *:[i32] }:$src1)
        GIR_BuildMI, /*InsnID*/0, /*Opcode*/GIMT_Encode2(AMDGPU::S_LSHL1_ADD_U32),
        GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/0, // DstI[sdst]
        GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/1, /*OpIdx*/1, // src0
        GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/1, // src1
        GIR_SetImplicitDefDead, /*InsnID*/0, /*OpIdx for AMDGPU::SCC*/0,
        GIR_ConstrainSelectedInstOperands, /*InsnID*/0,
        GIR_EraseFromParent, /*InsnID*/0,
        // GIR_Coverage, 7120,
        GIR_Done,
      // Label 188: @15650
      GIM_Try, /*On fail goto*//*Label 189*/ GIMT_Encode4(15727), // Rule ID 7121 //
        GIM_CheckFeatures, GIMT_Encode2(GIFBS_isGFX9Plus),
        GIM_CheckRegBankForClass, /*MI*/0, /*Op*/0, /*RC*/GIMT_Encode2(AMDGPU::SReg_32RegClassID),
        GIM_CheckRegBankForClass, /*MI*/0, /*Op*/1, /*RC*/GIMT_Encode2(AMDGPU::SReg_32RegClassID),
        GIM_RecordInsn, /*DefineMI*/1, /*MI*/0, /*OpIdx*/2, // MIs[1]
        GIM_CheckOpcode, /*MI*/1, GIMT_Encode2(TargetOpcode::G_SHL),
        GIM_CheckType, /*MI*/1, /*Op*/1, /*Type*/GILLT_s32,
        GIM_CheckType, /*MI*/1, /*Op*/2, /*Type*/GILLT_s32,
        GIM_CheckRegBankForClass, /*MI*/1, /*Op*/1, /*RC*/GIMT_Encode2(AMDGPU::SReg_32RegClassID),
        GIM_CheckConstantInt8, /*MI*/1, /*Op*/2, 2,
        GIM_CheckCxxInsnPredicate, /*MI*/1, /*FnId*/GIMT_Encode2(GICXXPred_MI_Predicate_shl_oneuse),
        GIM_CheckCxxInsnPredicate, /*MI*/0, /*FnId*/GIMT_Encode2(GICXXPred_MI_Predicate_shl2_add),
        GIM_CheckIsSafeToFold, /*InsnID*/1,
        // (add:{ *:[i32] } SSrc_b32:{ *:[i32] }:$src1, (shl:{ *:[i32] } SSrc_b32:{ *:[i32] }:$src0, 2:{ *:[i32] })<<P:Predicate_shl_oneuse>>)<<P:Predicate_shl2_add>>  =>  (S_LSHL2_ADD_U32:{ *:[i32] }:{ *:[i1] } SSrc_b32:{ *:[i32] }:$src0, SSrc_b32:{ *:[i32] }:$src1)
        GIR_BuildMI, /*InsnID*/0, /*Opcode*/GIMT_Encode2(AMDGPU::S_LSHL2_ADD_U32),
        GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/0, // DstI[sdst]
        GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/1, /*OpIdx*/1, // src0
        GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/1, // src1
        GIR_SetImplicitDefDead, /*InsnID*/0, /*OpIdx for AMDGPU::SCC*/0,
        GIR_ConstrainSelectedInstOperands, /*InsnID*/0,
        GIR_EraseFromParent, /*InsnID*/0,
        // GIR_Coverage, 7121,
        GIR_Done,
      // Label 189: @15727
      GIM_Try, /*On fail goto*//*Label 190*/ GIMT_Encode4(15804), // Rule ID 7122 //
        GIM_CheckFeatures, GIMT_Encode2(GIFBS_isGFX9Plus),
        GIM_CheckRegBankForClass, /*MI*/0, /*Op*/0, /*RC*/GIMT_Encode2(AMDGPU::SReg_32RegClassID),
        GIM_CheckRegBankForClass, /*MI*/0, /*Op*/1, /*RC*/GIMT_Encode2(AMDGPU::SReg_32RegClassID),
        GIM_RecordInsn, /*DefineMI*/1, /*MI*/0, /*OpIdx*/2, // MIs[1]
        GIM_CheckOpcode, /*MI*/1, GIMT_Encode2(TargetOpcode::G_SHL),
        GIM_CheckType, /*MI*/1, /*Op*/1, /*Type*/GILLT_s32,
        GIM_CheckType, /*MI*/1, /*Op*/2, /*Type*/GILLT_s32,
        GIM_CheckRegBankForClass, /*MI*/1, /*Op*/1, /*RC*/GIMT_Encode2(AMDGPU::SReg_32RegClassID),
        GIM_CheckConstantInt8, /*MI*/1, /*Op*/2, 3,
        GIM_CheckCxxInsnPredicate, /*MI*/1, /*FnId*/GIMT_Encode2(GICXXPred_MI_Predicate_shl_oneuse),
        GIM_CheckCxxInsnPredicate, /*MI*/0, /*FnId*/GIMT_Encode2(GICXXPred_MI_Predicate_shl3_add),
        GIM_CheckIsSafeToFold, /*InsnID*/1,
        // (add:{ *:[i32] } SSrc_b32:{ *:[i32] }:$src1, (shl:{ *:[i32] } SSrc_b32:{ *:[i32] }:$src0, 3:{ *:[i32] })<<P:Predicate_shl_oneuse>>)<<P:Predicate_shl3_add>>  =>  (S_LSHL3_ADD_U32:{ *:[i32] }:{ *:[i1] } SSrc_b32:{ *:[i32] }:$src0, SSrc_b32:{ *:[i32] }:$src1)
        GIR_BuildMI, /*InsnID*/0, /*Opcode*/GIMT_Encode2(AMDGPU::S_LSHL3_ADD_U32),
        GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/0, // DstI[sdst]
        GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/1, /*OpIdx*/1, // src0
        GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/1, // src1
        GIR_SetImplicitDefDead, /*InsnID*/0, /*OpIdx for AMDGPU::SCC*/0,
        GIR_ConstrainSelectedInstOperands, /*InsnID*/0,
        GIR_EraseFromParent, /*InsnID*/0,
        // GIR_Coverage, 7122,
        GIR_Done,
      // Label 190: @15804
      GIM_Try, /*On fail goto*//*Label 191*/ GIMT_Encode4(15881), // Rule ID 7123 //
        GIM_CheckFeatures, GIMT_Encode2(GIFBS_isGFX9Plus),
        GIM_CheckRegBankForClass, /*MI*/0, /*Op*/0, /*RC*/GIMT_Encode2(AMDGPU::SReg_32RegClassID),
        GIM_CheckRegBankForClass, /*MI*/0, /*Op*/1, /*RC*/GIMT_Encode2(AMDGPU::SReg_32RegClassID),
        GIM_RecordInsn, /*DefineMI*/1, /*MI*/0, /*OpIdx*/2, // MIs[1]
        GIM_CheckOpcode, /*MI*/1, GIMT_Encode2(TargetOpcode::G_SHL),
        GIM_CheckType, /*MI*/1, /*Op*/1, /*Type*/GILLT_s32,
        GIM_CheckType, /*MI*/1, /*Op*/2, /*Type*/GILLT_s32,
        GIM_CheckRegBankForClass, /*MI*/1, /*Op*/1, /*RC*/GIMT_Encode2(AMDGPU::SReg_32RegClassID),
        GIM_CheckConstantInt8, /*MI*/1, /*Op*/2, 4,
        GIM_CheckCxxInsnPredicate, /*MI*/1, /*FnId*/GIMT_Encode2(GICXXPred_MI_Predicate_shl_oneuse),
        GIM_CheckCxxInsnPredicate, /*MI*/0, /*FnId*/GIMT_Encode2(GICXXPred_MI_Predicate_shl4_add),
        GIM_CheckIsSafeToFold, /*InsnID*/1,
        // (add:{ *:[i32] } SSrc_b32:{ *:[i32] }:$src1, (shl:{ *:[i32] } SSrc_b32:{ *:[i32] }:$src0, 4:{ *:[i32] })<<P:Predicate_shl_oneuse>>)<<P:Predicate_shl4_add>>  =>  (S_LSHL4_ADD_U32:{ *:[i32] }:{ *:[i1] } SSrc_b32:{ *:[i32] }:$src0, SSrc_b32:{ *:[i32] }:$src1)
        GIR_BuildMI, /*InsnID*/0, /*Opcode*/GIMT_Encode2(AMDGPU::S_LSHL4_ADD_U32),
        GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/0, // DstI[sdst]
        GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/1, /*OpIdx*/1, // src0
        GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/1, // src1
        GIR_SetImplicitDefDead, /*InsnID*/0, /*OpIdx for AMDGPU::SCC*/0,
        GIR_ConstrainSelectedInstOperands, /*InsnID*/0,
        GIR_EraseFromParent, /*InsnID*/0,
        // GIR_Coverage, 7123,
        GIR_Done,
      // Label 191: @15881
      GIM_Try, /*On fail goto*//*Label 192*/ GIMT_Encode4(15957), // Rule ID 2188 //
        GIM_CheckFeatures, GIMT_Encode2(GIFBS_isGFX9Plus),
        GIM_CheckRegBankForClass, /*MI*/0, /*Op*/0, /*RC*/GIMT_Encode2(AMDGPU::VGPR_32RegClassID),
        GIM_RecordInsn, /*DefineMI*/1, /*MI*/0, /*OpIdx*/1, // MIs[1]
        GIM_CheckOpcode, /*MI*/1, GIMT_Encode2(TargetOpcode::G_ADD),
        GIM_CheckType, /*MI*/1, /*Op*/1, /*Type*/GILLT_s32,
        GIM_CheckType, /*MI*/1, /*Op*/2, /*Type*/GILLT_s32,
        GIM_RecordNamedOperand, /*MI*/1, /*Op*/1, /*StoreIdx*/0, // Name : pred:3:x
        GIM_RecordNamedOperand, /*MI*/1, /*Op*/2, /*StoreIdx*/1, // Name : pred:3:y
        GIM_CheckCxxInsnPredicate, /*MI*/1, /*FnId*/GIMT_Encode2(GICXXPred_MI_Predicate_anonymous_23606),
        GIM_RecordNamedOperand, /*MI*/0, /*Op*/2, /*StoreIdx*/2, // Name : pred:3:z
        GIM_CheckCxxInsnPredicate, /*MI*/0, /*FnId*/GIMT_Encode2(GICXXPred_MI_Predicate_anonymous_23608),
        GIM_CheckIsSafeToFold, /*InsnID*/1,
        // (add:{ *:[i32] } (add:{ *:[i32] } i32:{ *:[i32] }:$src0:$pred:3:x, i32:{ *:[i32] }:$src1:$pred:3:y)<<P:Predicate_anonymous_23606>>, i32:{ *:[i32] }:$src2:$pred:3:z)<<P:3:Predicate_anonymous_23608>>  =>  (V_ADD3_U32_e64:{ *:[i32] } VSrc_b32:{ *:[i32] }:$src0, VSrc_b32:{ *:[i32] }:$src1, VSrc_b32:{ *:[i32] }:$src2)
        GIR_BuildMI, /*InsnID*/0, /*Opcode*/GIMT_Encode2(AMDGPU::V_ADD3_U32_e64),
        GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/0, // DstI[vdst]
        GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/1, /*OpIdx*/1, // src0
        GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/1, /*OpIdx*/2, // src1
        GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/2, // src2
        GIR_ConstrainSelectedInstOperands, /*InsnID*/0,
        GIR_EraseFromParent, /*InsnID*/0,
        // GIR_Coverage, 2188,
        GIR_Done,
      // Label 192: @15957
      GIM_Try, /*On fail goto*//*Label 193*/ GIMT_Encode4(16033), // Rule ID 2184 //
        GIM_CheckFeatures, GIMT_Encode2(GIFBS_isGFX9Plus),
        GIM_CheckRegBankForClass, /*MI*/0, /*Op*/0, /*RC*/GIMT_Encode2(AMDGPU::VGPR_32RegClassID),
        GIM_RecordInsn, /*DefineMI*/1, /*MI*/0, /*OpIdx*/1, // MIs[1]
        GIM_CheckOpcode, /*MI*/1, GIMT_Encode2(TargetOpcode::G_SHL),
        GIM_CheckType, /*MI*/1, /*Op*/1, /*Type*/GILLT_s32,
        GIM_CheckType, /*MI*/1, /*Op*/2, /*Type*/GILLT_s32,
        GIM_RecordNamedOperand, /*MI*/1, /*Op*/1, /*StoreIdx*/0, // Name : pred:1:x
        GIM_RecordNamedOperand, /*MI*/1, /*Op*/2, /*StoreIdx*/1, // Name : pred:1:y
        GIM_CheckCxxInsnPredicate, /*MI*/1, /*FnId*/GIMT_Encode2(GICXXPred_MI_Predicate_anonymous_23603),
        GIM_RecordNamedOperand, /*MI*/0, /*Op*/2, /*StoreIdx*/2, // Name : pred:1:z
        GIM_CheckCxxInsnPredicate, /*MI*/0, /*FnId*/GIMT_Encode2(GICXXPred_MI_Predicate_anonymous_23602),
        GIM_CheckIsSafeToFold, /*InsnID*/1,
        // (add:{ *:[i32] } (shl:{ *:[i32] } i32:{ *:[i32] }:$src0:$pred:1:x, i32:{ *:[i32] }:$src1:$pred:1:y)<<P:Predicate_anonymous_23603>>, i32:{ *:[i32] }:$src2:$pred:1:z)<<P:1:Predicate_anonymous_23602>>  =>  (V_LSHL_ADD_U32_e64:{ *:[i32] } VSrc_b32:{ *:[i32] }:$src0, VSrc_b32:{ *:[i32] }:$src1, VSrc_b32:{ *:[i32] }:$src2)
        GIR_BuildMI, /*InsnID*/0, /*Opcode*/GIMT_Encode2(AMDGPU::V_LSHL_ADD_U32_e64),
        GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/0, // DstI[vdst]
        GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/1, /*OpIdx*/1, // src0
        GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/1, /*OpIdx*/2, // src1
        GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/2, // src2
        GIR_ConstrainSelectedInstOperands, /*InsnID*/0,
        GIR_EraseFromParent, /*InsnID*/0,
        // GIR_Coverage, 2184,
        GIR_Done,
      // Label 193: @16033
      GIM_Try, /*On fail goto*//*Label 194*/ GIMT_Encode4(16109), // Rule ID 2194 //
        GIM_CheckFeatures, GIMT_Encode2(GIFBS_isGFX9Plus),
        GIM_CheckRegBankForClass, /*MI*/0, /*Op*/0, /*RC*/GIMT_Encode2(AMDGPU::VGPR_32RegClassID),
        GIM_RecordInsn, /*DefineMI*/1, /*MI*/0, /*OpIdx*/1, // MIs[1]
        GIM_CheckOpcode, /*MI*/1, GIMT_Encode2(TargetOpcode::G_XOR),
        GIM_CheckType, /*MI*/1, /*Op*/1, /*Type*/GILLT_s32,
        GIM_CheckType, /*MI*/1, /*Op*/2, /*Type*/GILLT_s32,
        GIM_RecordNamedOperand, /*MI*/1, /*Op*/1, /*StoreIdx*/0, // Name : pred:8:x
        GIM_RecordNamedOperand, /*MI*/1, /*Op*/2, /*StoreIdx*/1, // Name : pred:8:y
        GIM_CheckCxxInsnPredicate, /*MI*/1, /*FnId*/GIMT_Encode2(GICXXPred_MI_Predicate_anonymous_23622),
        GIM_RecordNamedOperand, /*MI*/0, /*Op*/2, /*StoreIdx*/2, // Name : pred:8:z
        GIM_CheckCxxInsnPredicate, /*MI*/0, /*FnId*/GIMT_Encode2(GICXXPred_MI_Predicate_anonymous_23621),
        GIM_CheckIsSafeToFold, /*InsnID*/1,
        // (add:{ *:[i32] } (xor:{ *:[i32] } i32:{ *:[i32] }:$src0:$pred:8:x, i32:{ *:[i32] }:$src1:$pred:8:y)<<P:Predicate_anonymous_23622>>, i32:{ *:[i32] }:$src2:$pred:8:z)<<P:8:Predicate_anonymous_23621>>  =>  (V_XAD_U32_e64:{ *:[i32] } VSrc_b32:{ *:[i32] }:$src0, VSrc_b32:{ *:[i32] }:$src1, VSrc_b32:{ *:[i32] }:$src2)
        GIR_BuildMI, /*InsnID*/0, /*Opcode*/GIMT_Encode2(AMDGPU::V_XAD_U32_e64),
        GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/0, // DstI[vdst]
        GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/1, /*OpIdx*/1, // src0
        GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/1, /*OpIdx*/2, // src1
        GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/2, // src2
        GIR_ConstrainSelectedInstOperands, /*InsnID*/0,
        GIR_EraseFromParent, /*InsnID*/0,
        // GIR_Coverage, 2194,
        GIR_Done,
      // Label 194: @16109
      GIM_Try, /*On fail goto*//*Label 195*/ GIMT_Encode4(16185), // Rule ID 7211 //
        GIM_CheckFeatures, GIMT_Encode2(GIFBS_isGFX9Plus),
        GIM_CheckRegBankForClass, /*MI*/0, /*Op*/0, /*RC*/GIMT_Encode2(AMDGPU::VGPR_32RegClassID),
        GIM_RecordNamedOperand, /*MI*/0, /*Op*/1, /*StoreIdx*/2, // Name : pred:3:z
        GIM_RecordInsn, /*DefineMI*/1, /*MI*/0, /*OpIdx*/2, // MIs[1]
        GIM_CheckOpcode, /*MI*/1, GIMT_Encode2(TargetOpcode::G_ADD),
        GIM_CheckType, /*MI*/1, /*Op*/1, /*Type*/GILLT_s32,
        GIM_CheckType, /*MI*/1, /*Op*/2, /*Type*/GILLT_s32,
        GIM_RecordNamedOperand, /*MI*/1, /*Op*/1, /*StoreIdx*/0, // Name : pred:3:x
        GIM_RecordNamedOperand, /*MI*/1, /*Op*/2, /*StoreIdx*/1, // Name : pred:3:y
        GIM_CheckCxxInsnPredicate, /*MI*/1, /*FnId*/GIMT_Encode2(GICXXPred_MI_Predicate_anonymous_23606),
        GIM_CheckCxxInsnPredicate, /*MI*/0, /*FnId*/GIMT_Encode2(GICXXPred_MI_Predicate_anonymous_23608),
        GIM_CheckIsSafeToFold, /*InsnID*/1,
        // (add:{ *:[i32] } i32:{ *:[i32] }:$src2:$pred:3:z, (add:{ *:[i32] } i32:{ *:[i32] }:$src0:$pred:3:x, i32:{ *:[i32] }:$src1:$pred:3:y)<<P:Predicate_anonymous_23606>>)<<P:3:Predicate_anonymous_23608>>  =>  (V_ADD3_U32_e64:{ *:[i32] } VSrc_b32:{ *:[i32] }:$src0, VSrc_b32:{ *:[i32] }:$src1, VSrc_b32:{ *:[i32] }:$src2)
        GIR_BuildMI, /*InsnID*/0, /*Opcode*/GIMT_Encode2(AMDGPU::V_ADD3_U32_e64),
        GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/0, // DstI[vdst]
        GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/1, /*OpIdx*/1, // src0
        GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/1, /*OpIdx*/2, // src1
        GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/1, // src2
        GIR_ConstrainSelectedInstOperands, /*InsnID*/0,
        GIR_EraseFromParent, /*InsnID*/0,
        // GIR_Coverage, 7211,
        GIR_Done,
      // Label 195: @16185
      GIM_Try, /*On fail goto*//*Label 196*/ GIMT_Encode4(16261), // Rule ID 7209 //
        GIM_CheckFeatures, GIMT_Encode2(GIFBS_isGFX9Plus),
        GIM_CheckRegBankForClass, /*MI*/0, /*Op*/0, /*RC*/GIMT_Encode2(AMDGPU::VGPR_32RegClassID),
        GIM_RecordNamedOperand, /*MI*/0, /*Op*/1, /*StoreIdx*/2, // Name : pred:1:z
        GIM_RecordInsn, /*DefineMI*/1, /*MI*/0, /*OpIdx*/2, // MIs[1]
        GIM_CheckOpcode, /*MI*/1, GIMT_Encode2(TargetOpcode::G_SHL),
        GIM_CheckType, /*MI*/1, /*Op*/1, /*Type*/GILLT_s32,
        GIM_CheckType, /*MI*/1, /*Op*/2, /*Type*/GILLT_s32,
        GIM_RecordNamedOperand, /*MI*/1, /*Op*/1, /*StoreIdx*/0, // Name : pred:1:x
        GIM_RecordNamedOperand, /*MI*/1, /*Op*/2, /*StoreIdx*/1, // Name : pred:1:y
        GIM_CheckCxxInsnPredicate, /*MI*/1, /*FnId*/GIMT_Encode2(GICXXPred_MI_Predicate_anonymous_23603),
        GIM_CheckCxxInsnPredicate, /*MI*/0, /*FnId*/GIMT_Encode2(GICXXPred_MI_Predicate_anonymous_23602),
        GIM_CheckIsSafeToFold, /*InsnID*/1,
        // (add:{ *:[i32] } i32:{ *:[i32] }:$src2:$pred:1:z, (shl:{ *:[i32] } i32:{ *:[i32] }:$src0:$pred:1:x, i32:{ *:[i32] }:$src1:$pred:1:y)<<P:Predicate_anonymous_23603>>)<<P:1:Predicate_anonymous_23602>>  =>  (V_LSHL_ADD_U32_e64:{ *:[i32] } VSrc_b32:{ *:[i32] }:$src0, VSrc_b32:{ *:[i32] }:$src1, VSrc_b32:{ *:[i32] }:$src2)
        GIR_BuildMI, /*InsnID*/0, /*Opcode*/GIMT_Encode2(AMDGPU::V_LSHL_ADD_U32_e64),
        GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/0, // DstI[vdst]
        GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/1, /*OpIdx*/1, // src0
        GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/1, /*OpIdx*/2, // src1
        GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/1, // src2
        GIR_ConstrainSelectedInstOperands, /*InsnID*/0,
        GIR_EraseFromParent, /*InsnID*/0,
        // GIR_Coverage, 7209,
        GIR_Done,
      // Label 196: @16261
      GIM_Try, /*On fail goto*//*Label 197*/ GIMT_Encode4(16337), // Rule ID 7216 //
        GIM_CheckFeatures, GIMT_Encode2(GIFBS_isGFX9Plus),
        GIM_CheckRegBankForClass, /*MI*/0, /*Op*/0, /*RC*/GIMT_Encode2(AMDGPU::VGPR_32RegClassID),
        GIM_RecordNamedOperand, /*MI*/0, /*Op*/1, /*StoreIdx*/2, // Name : pred:8:z
        GIM_RecordInsn, /*DefineMI*/1, /*MI*/0, /*OpIdx*/2, // MIs[1]
        GIM_CheckOpcode, /*MI*/1, GIMT_Encode2(TargetOpcode::G_XOR),
        GIM_CheckType, /*MI*/1, /*Op*/1, /*Type*/GILLT_s32,
        GIM_CheckType, /*MI*/1, /*Op*/2, /*Type*/GILLT_s32,
        GIM_RecordNamedOperand, /*MI*/1, /*Op*/1, /*StoreIdx*/0, // Name : pred:8:x
        GIM_RecordNamedOperand, /*MI*/1, /*Op*/2, /*StoreIdx*/1, // Name : pred:8:y
        GIM_CheckCxxInsnPredicate, /*MI*/1, /*FnId*/GIMT_Encode2(GICXXPred_MI_Predicate_anonymous_23622),
        GIM_CheckCxxInsnPredicate, /*MI*/0, /*FnId*/GIMT_Encode2(GICXXPred_MI_Predicate_anonymous_23621),
        GIM_CheckIsSafeToFold, /*InsnID*/1,
        // (add:{ *:[i32] } i32:{ *:[i32] }:$src2:$pred:8:z, (xor:{ *:[i32] } i32:{ *:[i32] }:$src0:$pred:8:x, i32:{ *:[i32] }:$src1:$pred:8:y)<<P:Predicate_anonymous_23622>>)<<P:8:Predicate_anonymous_23621>>  =>  (V_XAD_U32_e64:{ *:[i32] } VSrc_b32:{ *:[i32] }:$src0, VSrc_b32:{ *:[i32] }:$src1, VSrc_b32:{ *:[i32] }:$src2)
        GIR_BuildMI, /*InsnID*/0, /*Opcode*/GIMT_Encode2(AMDGPU::V_XAD_U32_e64),
        GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/0, // DstI[vdst]
        GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/1, /*OpIdx*/1, // src0
        GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/1, /*OpIdx*/2, // src1
        GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/1, // src2
        GIR_ConstrainSelectedInstOperands, /*InsnID*/0,
        GIR_EraseFromParent, /*InsnID*/0,
        // GIR_Coverage, 7216,
        GIR_Done,
      // Label 197: @16337
      GIM_Try, /*On fail goto*//*Label 198*/ GIMT_Encode4(16390), // Rule ID 6462 //
        GIM_CheckRegBankForClass, /*MI*/0, /*Op*/0, /*RC*/GIMT_Encode2(AMDGPU::SReg_32RegClassID),
        GIM_RecordInsn, /*DefineMI*/1, /*MI*/0, /*OpIdx*/2, // MIs[1]
        GIM_CheckOpcode, /*MI*/1, GIMT_Encode2(TargetOpcode::G_CONSTANT),
        GIM_CheckI64ImmPredicate, /*MI*/1, /*Predicate*/GIMT_Encode2(GICXXPred_I64_Predicate_NegSubInlineConst32),
        // MIs[1] Operand 1
        // No operand predicates
        GIM_CheckCxxInsnPredicate, /*MI*/0, /*FnId*/GIMT_Encode2(GICXXPred_MI_Predicate_anonymous_17603),
        GIM_CheckIsSafeToFold, /*InsnID*/1,
        // (add:{ *:[i32] } i32:{ *:[i32] }:$src0, (imm:{ *:[i32] })<<P:Predicate_NegSubInlineConst32>><<X:NegateImm>>:$src1)<<P:Predicate_anonymous_17603>>  =>  (S_SUB_I32:{ *:[i32] }:{ *:[i1] } SReg_32:{ *:[i32] }:$src0, (NegateImm:{ *:[i1 i16 i32 bf16 f16 f32 v2i16 v2f16 v2bf16] } (imm:{ *:[i32] })<<P:Predicate_NegSubInlineConst32>>:$src1))
        GIR_BuildMI, /*InsnID*/0, /*Opcode*/GIMT_Encode2(AMDGPU::S_SUB_I32),
        GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/0, // DstI[sdst]
        GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/1, // src0
        GIR_CustomRenderer, /*InsnID*/0, /*OldInsnID*/1, /*Renderer*/GIMT_Encode2(GICR_renderNegateImm), // src1
        GIR_SetImplicitDefDead, /*InsnID*/0, /*OpIdx for AMDGPU::SCC*/0,
        GIR_ConstrainSelectedInstOperands, /*InsnID*/0,
        GIR_EraseFromParent, /*InsnID*/0,
        // GIR_Coverage, 6462,
        GIR_Done,
      // Label 198: @16390
      GIM_Try, /*On fail goto*//*Label 199*/ GIMT_Encode4(16446), // Rule ID 6463 //
        GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasAddNoCarryInsts),
        GIM_CheckRegBankForClass, /*MI*/0, /*Op*/0, /*RC*/GIMT_Encode2(AMDGPU::VGPR_32RegClassID),
        GIM_RecordInsn, /*DefineMI*/1, /*MI*/0, /*OpIdx*/2, // MIs[1]
        GIM_CheckOpcode, /*MI*/1, GIMT_Encode2(TargetOpcode::G_CONSTANT),
        GIM_CheckI64ImmPredicate, /*MI*/1, /*Predicate*/GIMT_Encode2(GICXXPred_I64_Predicate_NegSubInlineConst32),
        // MIs[1] Operand 1
        // No operand predicates
        GIM_CheckCxxInsnPredicate, /*MI*/0, /*FnId*/GIMT_Encode2(GICXXPred_MI_Predicate_anonymous_22545),
        GIM_CheckIsSafeToFold, /*InsnID*/1,
        // (add:{ *:[i32] } i32:{ *:[i32] }:$src0, (imm:{ *:[i32] })<<P:Predicate_NegSubInlineConst32>><<X:NegateImm>>:$src1)<<P:Predicate_anonymous_22545>>  =>  (V_SUB_U32_e64:{ *:[i32] } VS_32:{ *:[i32] }:$src0, (NegateImm:{ *:[i16 i32 bf16 f16 f32 v2i16 v2f16 v2bf16] } (imm:{ *:[i32] })<<P:Predicate_NegSubInlineConst32>>:$src1))
        GIR_BuildMI, /*InsnID*/0, /*Opcode*/GIMT_Encode2(AMDGPU::V_SUB_U32_e64),
        GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/0, // DstI[vdst]
        GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/1, // src0
        GIR_CustomRenderer, /*InsnID*/0, /*OldInsnID*/1, /*Renderer*/GIMT_Encode2(GICR_renderNegateImm), // src1
        GIR_AddImm8, /*InsnID*/0, /*Imm*/0,
        GIR_ConstrainSelectedInstOperands, /*InsnID*/0,
        GIR_EraseFromParent, /*InsnID*/0,
        // GIR_Coverage, 6463,
        GIR_Done,
      // Label 199: @16446
      GIM_Try, /*On fail goto*//*Label 200*/ GIMT_Encode4(16510), // Rule ID 6464 //
        GIM_CheckFeatures, GIMT_Encode2(GIFBS_NotHasAddNoCarryInsts),
        GIM_CheckRegBankForClass, /*MI*/0, /*Op*/0, /*RC*/GIMT_Encode2(AMDGPU::VGPR_32RegClassID),
        GIM_RecordInsn, /*DefineMI*/1, /*MI*/0, /*OpIdx*/2, // MIs[1]
        GIM_CheckOpcode, /*MI*/1, GIMT_Encode2(TargetOpcode::G_CONSTANT),
        GIM_CheckI64ImmPredicate, /*MI*/1, /*Predicate*/GIMT_Encode2(GICXXPred_I64_Predicate_NegSubInlineConst32),
        // MIs[1] Operand 1
        // No operand predicates
        GIM_CheckCxxInsnPredicate, /*MI*/0, /*FnId*/GIMT_Encode2(GICXXPred_MI_Predicate_anonymous_22545),
        GIM_CheckIsSafeToFold, /*InsnID*/1,
        // (add:{ *:[i32] } i32:{ *:[i32] }:$src0, (imm:{ *:[i32] })<<P:Predicate_NegSubInlineConst32>><<X:NegateImm>>:$src1)<<P:Predicate_anonymous_22545>>  =>  (V_SUB_CO_U32_e64:{ *:[i32] }:{ *:[i1] } VS_32:{ *:[i32] }:$src0, (NegateImm:{ *:[i16 i32 bf16 f16 f32 v2i16 v2f16 v2bf16] } (imm:{ *:[i32] })<<P:Predicate_NegSubInlineConst32>>:$src1))
        GIR_MakeTempReg, /*TempRegID*/0, /*TypeID*/GILLT_s1,
        GIR_BuildMI, /*InsnID*/0, /*Opcode*/GIMT_Encode2(AMDGPU::V_SUB_CO_U32_e64),
        GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/0, // DstI[vdst]
        GIR_AddTempRegister, /*InsnID*/0, /*TempRegID*/0, /*TempRegFlags*/GIMT_Encode2(RegState::Define|RegState::Dead),
        GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/1, // src0
        GIR_CustomRenderer, /*InsnID*/0, /*OldInsnID*/1, /*Renderer*/GIMT_Encode2(GICR_renderNegateImm), // src1
        GIR_AddImm8, /*InsnID*/0, /*Imm*/0,
        GIR_ConstrainSelectedInstOperands, /*InsnID*/0,
        GIR_EraseFromParent, /*InsnID*/0,
        // GIR_Coverage, 6464,
        GIR_Done,
      // Label 200: @16510
      GIM_Try, /*On fail goto*//*Label 201*/ GIMT_Encode4(16548), // Rule ID 45 //
        GIM_CheckRegBankForClass, /*MI*/0, /*Op*/0, /*RC*/GIMT_Encode2(AMDGPU::SReg_32RegClassID),
        GIM_CheckRegBankForClass, /*MI*/0, /*Op*/1, /*RC*/GIMT_Encode2(AMDGPU::SReg_32RegClassID),
        GIM_CheckRegBankForClass, /*MI*/0, /*Op*/2, /*RC*/GIMT_Encode2(AMDGPU::SReg_32RegClassID),
        GIM_CheckCxxInsnPredicate, /*MI*/0, /*FnId*/GIMT_Encode2(GICXXPred_MI_Predicate_anonymous_17603),
        // (add:{ *:[i32] } SSrc_b32:{ *:[i32] }:$src0, SSrc_b32:{ *:[i32] }:$src1)<<P:Predicate_anonymous_17603>>  =>  (S_ADD_I32:{ *:[i32] }:{ *:[i1] } SSrc_b32:{ *:[i32] }:$src0, SSrc_b32:{ *:[i32] }:$src1)
        GIR_MutateOpcode, /*InsnID*/0, /*RecycleInsnID*/0, /*Opcode*/GIMT_Encode2(AMDGPU::S_ADD_I32),
        GIR_AddImplicitDef, /*InsnID*/0, GIMT_Encode2(AMDGPU::SCC), GIMT_Encode2(RegState::Dead),
        GIR_ConstrainSelectedInstOperands, /*InsnID*/0,
        // GIR_Coverage, 45,
        GIR_Done,
      // Label 201: @16548
      GIM_Try, /*On fail goto*//*Label 202*/ GIMT_Encode4(16589), // Rule ID 2098 //
        GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasAddNoCarryInsts),
        GIM_CheckRegBankForClass, /*MI*/0, /*Op*/0, /*RC*/GIMT_Encode2(AMDGPU::VGPR_32RegClassID),
        GIM_CheckCxxInsnPredicate, /*MI*/0, /*FnId*/GIMT_Encode2(GICXXPred_MI_Predicate_anonymous_22545),
        // (add:{ *:[i32] } i32:{ *:[i32] }:$src0, i32:{ *:[i32] }:$src1)<<P:Predicate_anonymous_22545>>  =>  (V_ADD_U32_e64:{ *:[i32] } ?:{ *:[i32] }:$src0, ?:{ *:[i32] }:$src1, 0:{ *:[i1] })
        GIR_BuildMI, /*InsnID*/0, /*Opcode*/GIMT_Encode2(AMDGPU::V_ADD_U32_e64),
        GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/0, // DstI[vdst]
        GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/1, // src0
        GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/2, // src1
        GIR_AddImm8, /*InsnID*/0, /*Imm*/0,
        GIR_ConstrainSelectedInstOperands, /*InsnID*/0,
        GIR_EraseFromParent, /*InsnID*/0,
        // GIR_Coverage, 2098,
        GIR_Done,
      // Label 202: @16589
      GIM_Try, /*On fail goto*//*Label 203*/ GIMT_Encode4(16638), // Rule ID 2100 //
        GIM_CheckFeatures, GIMT_Encode2(GIFBS_isGFX6GFX7GFX8GFX9),
        GIM_CheckRegBankForClass, /*MI*/0, /*Op*/0, /*RC*/GIMT_Encode2(AMDGPU::VGPR_32RegClassID),
        GIM_CheckCxxInsnPredicate, /*MI*/0, /*FnId*/GIMT_Encode2(GICXXPred_MI_Predicate_anonymous_22545),
        // (add:{ *:[i32] } i32:{ *:[i32] }:$src0, i32:{ *:[i32] }:$src1)<<P:Predicate_anonymous_22545>>  =>  (V_ADD_CO_U32_e64:{ *:[i32] }:{ *:[i1] } ?:{ *:[i32] }:$src0, ?:{ *:[i32] }:$src1, 0:{ *:[i1] })
        GIR_MakeTempReg, /*TempRegID*/0, /*TypeID*/GILLT_s1,
        GIR_BuildMI, /*InsnID*/0, /*Opcode*/GIMT_Encode2(AMDGPU::V_ADD_CO_U32_e64),
        GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/0, // DstI[vdst]
        GIR_AddTempRegister, /*InsnID*/0, /*TempRegID*/0, /*TempRegFlags*/GIMT_Encode2(RegState::Define|RegState::Dead),
        GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/1, // src0
        GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/2, // src1
        GIR_AddImm8, /*InsnID*/0, /*Imm*/0,
        GIR_ConstrainSelectedInstOperands, /*InsnID*/0,
        GIR_EraseFromParent, /*InsnID*/0,
        // GIR_Coverage, 2100,
        GIR_Done,
      // Label 203: @16638
      GIM_Try, /*On fail goto*//*Label 204*/ GIMT_Encode4(16683), // Rule ID 758 //
        GIM_CheckRegBankForClass, /*MI*/0, /*Op*/0, /*RC*/GIMT_Encode2(AMDGPU::VGPR_32RegClassID),
        GIM_RecordInsn, /*DefineMI*/1, /*MI*/0, /*OpIdx*/1, // MIs[1]
        GIM_CheckOpcode, /*MI*/1, GIMT_Encode2(TargetOpcode::G_CTPOP),
        GIM_CheckType, /*MI*/1, /*Op*/1, /*Type*/GILLT_s32,
        GIM_CheckIsSafeToFold, /*InsnID*/1,
        // (add:{ *:[i32] } (ctpop:{ *:[i32] } i32:{ *:[i32] }:$src0), i32:{ *:[i32] }:$src1)  =>  (V_BCNT_U32_B32_e64:{ *:[i32] } i32:{ *:[i32] }:$src0, i32:{ *:[i32] }:$src1)
        GIR_BuildMI, /*InsnID*/0, /*Opcode*/GIMT_Encode2(AMDGPU::V_BCNT_U32_B32_e64),
        GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/0, // DstI[vdst]
        GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/1, /*OpIdx*/1, // src0
        GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/2, // src1
        GIR_ConstrainSelectedInstOperands, /*InsnID*/0,
        GIR_EraseFromParent, /*InsnID*/0,
        // GIR_Coverage, 758,
        GIR_Done,
      // Label 204: @16683
      GIM_Try, /*On fail goto*//*Label 205*/ GIMT_Encode4(16728), // Rule ID 7135 //
        GIM_CheckRegBankForClass, /*MI*/0, /*Op*/0, /*RC*/GIMT_Encode2(AMDGPU::VGPR_32RegClassID),
        GIM_RecordInsn, /*DefineMI*/1, /*MI*/0, /*OpIdx*/2, // MIs[1]
        GIM_CheckOpcode, /*MI*/1, GIMT_Encode2(TargetOpcode::G_CTPOP),
        GIM_CheckType, /*MI*/1, /*Op*/1, /*Type*/GILLT_s32,
        GIM_CheckIsSafeToFold, /*InsnID*/1,
        // (add:{ *:[i32] } i32:{ *:[i32] }:$src1, (ctpop:{ *:[i32] } i32:{ *:[i32] }:$src0))  =>  (V_BCNT_U32_B32_e64:{ *:[i32] } i32:{ *:[i32] }:$src0, i32:{ *:[i32] }:$src1)
        GIR_BuildMI, /*InsnID*/0, /*Opcode*/GIMT_Encode2(AMDGPU::V_BCNT_U32_B32_e64),
        GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/0, // DstI[vdst]
        GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/1, /*OpIdx*/1, // src0
        GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/1, // src1
        GIR_ConstrainSelectedInstOperands, /*InsnID*/0,
        GIR_EraseFromParent, /*InsnID*/0,
        // GIR_Coverage, 7135,
        GIR_Done,
      // Label 205: @16728
      GIM_Reject,
    // Label 181: @16729
    GIM_Reject,
    // Label 166: @16730
    GIM_Try, /*On fail goto*//*Label 206*/ GIMT_Encode4(16964),
      GIM_CheckType, /*MI*/0, /*Op*/1, /*Type*/GILLT_s64,
      GIM_CheckType, /*MI*/0, /*Op*/2, /*Type*/GILLT_s64,
      GIM_Try, /*On fail goto*//*Label 207*/ GIMT_Encode4(16823), // Rule ID 2196 //
        GIM_CheckFeatures, GIMT_Encode2(GIFBS_isGFX940Plus),
        GIM_CheckRegBankForClass, /*MI*/0, /*Op*/0, /*RC*/GIMT_Encode2(AMDGPU::VReg_64RegClassID),
        GIM_RecordInsn, /*DefineMI*/1, /*MI*/0, /*OpIdx*/1, // MIs[1]
        GIM_CheckOpcode, /*MI*/1, GIMT_Encode2(TargetOpcode::G_SHL),
        GIM_CheckType, /*MI*/1, /*Op*/1, /*Type*/GILLT_s64,
        GIM_CheckType, /*MI*/1, /*Op*/2, /*Type*/GILLT_s32,
        GIM_RecordNamedOperand, /*MI*/1, /*Op*/1, /*StoreIdx*/0, // Name : pred:9:x
        GIM_RecordNamedOperand, /*MI*/1, /*Op*/2, /*StoreIdx*/1, // Name : pred:9:y
        GIM_CheckCxxInsnPredicate, /*MI*/1, /*FnId*/GIMT_Encode2(GICXXPred_MI_Predicate_shl_0_to_4),
        GIM_CheckCxxInsnPredicate, /*MI*/1, /*FnId*/GIMT_Encode2(GICXXPred_MI_Predicate_anonymous_23626),
        GIM_RecordNamedOperand, /*MI*/0, /*Op*/2, /*StoreIdx*/2, // Name : pred:9:z
        GIM_CheckCxxInsnPredicate, /*MI*/0, /*FnId*/GIMT_Encode2(GICXXPred_MI_Predicate_anonymous_23625),
        GIM_CheckIsSafeToFold, /*InsnID*/1,
        // (add:{ *:[i64] } (shl:{ *:[i64] } i64:{ *:[i64] }:$src0:$pred:9:x, i32:{ *:[i32] }:$src1:$pred:9:y)<<P:Predicate_shl_0_to_4>><<P:Predicate_anonymous_23626>>, i64:{ *:[i64] }:$src2:$pred:9:z)<<P:9:Predicate_anonymous_23625>>  =>  (V_LSHL_ADD_U64_e64:{ *:[i64] } VSrc_b64:{ *:[i64] }:$src0, VSrc_b32:{ *:[i32] }:$src1, VSrc_b64:{ *:[i64] }:$src2)
        GIR_BuildMI, /*InsnID*/0, /*Opcode*/GIMT_Encode2(AMDGPU::V_LSHL_ADD_U64_e64),
        GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/0, // DstI[vdst]
        GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/1, /*OpIdx*/1, // src0
        GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/1, /*OpIdx*/2, // src1
        GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/2, // src2
        GIR_ConstrainSelectedInstOperands, /*InsnID*/0,
        GIR_EraseFromParent, /*InsnID*/0,
        // GIR_Coverage, 2196,
        GIR_Done,
      // Label 207: @16823
      GIM_Try, /*On fail goto*//*Label 208*/ GIMT_Encode4(16903), // Rule ID 7217 //
        GIM_CheckFeatures, GIMT_Encode2(GIFBS_isGFX940Plus),
        GIM_CheckRegBankForClass, /*MI*/0, /*Op*/0, /*RC*/GIMT_Encode2(AMDGPU::VReg_64RegClassID),
        GIM_RecordNamedOperand, /*MI*/0, /*Op*/1, /*StoreIdx*/2, // Name : pred:9:z
        GIM_RecordInsn, /*DefineMI*/1, /*MI*/0, /*OpIdx*/2, // MIs[1]
        GIM_CheckOpcode, /*MI*/1, GIMT_Encode2(TargetOpcode::G_SHL),
        GIM_CheckType, /*MI*/1, /*Op*/1, /*Type*/GILLT_s64,
        GIM_CheckType, /*MI*/1, /*Op*/2, /*Type*/GILLT_s32,
        GIM_RecordNamedOperand, /*MI*/1, /*Op*/1, /*StoreIdx*/0, // Name : pred:9:x
        GIM_RecordNamedOperand, /*MI*/1, /*Op*/2, /*StoreIdx*/1, // Name : pred:9:y
        GIM_CheckCxxInsnPredicate, /*MI*/1, /*FnId*/GIMT_Encode2(GICXXPred_MI_Predicate_shl_0_to_4),
        GIM_CheckCxxInsnPredicate, /*MI*/1, /*FnId*/GIMT_Encode2(GICXXPred_MI_Predicate_anonymous_23626),
        GIM_CheckCxxInsnPredicate, /*MI*/0, /*FnId*/GIMT_Encode2(GICXXPred_MI_Predicate_anonymous_23625),
        GIM_CheckIsSafeToFold, /*InsnID*/1,
        // (add:{ *:[i64] } i64:{ *:[i64] }:$src2:$pred:9:z, (shl:{ *:[i64] } i64:{ *:[i64] }:$src0:$pred:9:x, i32:{ *:[i32] }:$src1:$pred:9:y)<<P:Predicate_shl_0_to_4>><<P:Predicate_anonymous_23626>>)<<P:9:Predicate_anonymous_23625>>  =>  (V_LSHL_ADD_U64_e64:{ *:[i64] } VSrc_b64:{ *:[i64] }:$src0, VSrc_b32:{ *:[i32] }:$src1, VSrc_b64:{ *:[i64] }:$src2)
        GIR_BuildMI, /*InsnID*/0, /*Opcode*/GIMT_Encode2(AMDGPU::V_LSHL_ADD_U64_e64),
        GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/0, // DstI[vdst]
        GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/1, /*OpIdx*/1, // src0
        GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/1, /*OpIdx*/2, // src1
        GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/1, // src2
        GIR_ConstrainSelectedInstOperands, /*InsnID*/0,
        GIR_EraseFromParent, /*InsnID*/0,
        // GIR_Coverage, 7217,
        GIR_Done,
      // Label 208: @16903
      GIM_Try, /*On fail goto*//*Label 209*/ GIMT_Encode4(16935), // Rule ID 1116 //
        GIM_CheckRegBankForClass, /*MI*/0, /*Op*/0, /*RC*/GIMT_Encode2(AMDGPU::VReg_64RegClassID),
        GIM_CheckCxxInsnPredicate, /*MI*/0, /*FnId*/GIMT_Encode2(GICXXPred_MI_Predicate_anonymous_22545),
        // (add:{ *:[i64] } i64:{ *:[i64] }:$src0, i64:{ *:[i64] }:$src1)<<P:Predicate_anonymous_22545>>  =>  (V_ADD_U64_PSEUDO:{ *:[i64] } i64:{ *:[i64] }:$src0, i64:{ *:[i64] }:$src1)
        GIR_MutateOpcode, /*InsnID*/0, /*RecycleInsnID*/0, /*Opcode*/GIMT_Encode2(AMDGPU::V_ADD_U64_PSEUDO),
        GIR_AddImplicitDef, /*InsnID*/0, GIMT_Encode2(AMDGPU::VCC), GIMT_Encode2(RegState::Dead),
        GIR_AddImplicitUse, /*InsnID*/0, GIMT_Encode2(AMDGPU::EXEC),
        GIR_ConstrainSelectedInstOperands, /*InsnID*/0,
        // GIR_Coverage, 1116,
        GIR_Done,
      // Label 209: @16935
      GIM_Try, /*On fail goto*//*Label 210*/ GIMT_Encode4(16963), // Rule ID 1118 //
        GIM_CheckRegBankForClass, /*MI*/0, /*Op*/0, /*RC*/GIMT_Encode2(AMDGPU::SReg_64RegClassID),
        GIM_CheckCxxInsnPredicate, /*MI*/0, /*FnId*/GIMT_Encode2(GICXXPred_MI_Predicate_anonymous_17603),
        // (add:{ *:[i64] } i64:{ *:[i64] }:$src0, i64:{ *:[i64] }:$src1)<<P:Predicate_anonymous_17603>>  =>  (S_ADD_U64_PSEUDO:{ *:[i64] }:{ *:[i1] } i64:{ *:[i64] }:$src0, i64:{ *:[i64] }:$src1)
        GIR_MutateOpcode, /*InsnID*/0, /*RecycleInsnID*/0, /*Opcode*/GIMT_Encode2(AMDGPU::S_ADD_U64_PSEUDO),
        GIR_AddImplicitDef, /*InsnID*/0, GIMT_Encode2(AMDGPU::SCC), GIMT_Encode2(RegState::Dead),
        GIR_ConstrainSelectedInstOperands, /*InsnID*/0,
        // GIR_Coverage, 1118,
        GIR_Done,
      // Label 210: @16963
      GIM_Reject,
    // Label 206: @16964
    GIM_Reject,
    // Label 167: @16965
    GIM_Try, /*On fail goto*//*Label 211*/ GIMT_Encode4(17045), // Rule ID 968 //
      GIM_CheckType, /*MI*/0, /*Op*/1, /*Type*/GILLT_v2s16,
      GIM_CheckType, /*MI*/0, /*Op*/2, /*Type*/GILLT_v2s16,
      GIM_CheckRegBankForClass, /*MI*/0, /*Op*/0, /*RC*/GIMT_Encode2(AMDGPU::VGPR_32RegClassID),
      GIM_CheckComplexPattern, /*MI*/0, /*Op*/1, /*Renderer*/GIMT_Encode2(0), GIMT_Encode2(GICP_gi_vop3pmods),
      GIM_CheckComplexPattern, /*MI*/0, /*Op*/2, /*Renderer*/GIMT_Encode2(1), GIMT_Encode2(GICP_gi_vop3pmods),
      // (add:{ *:[v2i16] } (VOP3PMods:{ *:[v2i16] } v2i16:{ *:[v2i16] }:$src0, i32:{ *:[i32] }:$src0_modifiers), (VOP3PMods:{ *:[v2i16] } v2i16:{ *:[v2i16] }:$src1, i32:{ *:[i32] }:$src1_modifiers))  =>  (V_PK_ADD_U16:{ *:[v2i16] } i32:{ *:[i32] }:$src0_modifiers, v2i16:{ *:[v2i16] }:$src0, i32:{ *:[i32] }:$src1_modifiers, v2i16:{ *:[v2i16] }:$src1)
      GIR_BuildMI, /*InsnID*/0, /*Opcode*/GIMT_Encode2(AMDGPU::V_PK_ADD_U16),
      GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/0, // DstI[vdst]
      GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/1, // src0_modifiers
      GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/0, // src0
      GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(1), /*SubOperand*/1, // src1_modifiers
      GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(1), /*SubOperand*/0, // src1
      GIR_AddImm8, /*InsnID*/0, /*Imm*/0,
      GIR_AddImm8, /*InsnID*/0, /*Imm*/0,
      GIR_AddImm8, /*InsnID*/0, /*Imm*/0,
      GIR_AddImm8, /*InsnID*/0, /*Imm*/0,
      GIR_AddImm8, /*InsnID*/0, /*Imm*/0,
      GIR_ConstrainSelectedInstOperands, /*InsnID*/0,
      GIR_EraseFromParent, /*InsnID*/0,
      // GIR_Coverage, 968,
      GIR_Done,
    // Label 211: @17045
    GIM_Reject,
    // Label 168: @17046
    GIM_Reject,
    // Label 1: @17047
    GIM_SwitchType, /*MI*/0, /*Op*/0, /*[*/GIMT_Encode2(7), GIMT_Encode2(12), /*)*//*default:*//*Label 217*/ GIMT_Encode4(17633),
    /*GILLT_s1*//*Label 212*/ GIMT_Encode4(17078),
    /*GILLT_s16*//*Label 213*/ GIMT_Encode4(17221),
    /*GILLT_s32*//*Label 214*/ GIMT_Encode4(17334),
    /*GILLT_s64*//*Label 215*/ GIMT_Encode4(17477),
    /*GILLT_v2s16*//*Label 216*/ GIMT_Encode4(17552),
    // Label 212: @17078
    GIM_Try, /*On fail goto*//*Label 218*/ GIMT_Encode4(17220),
      GIM_CheckType, /*MI*/0, /*Op*/1, /*Type*/GILLT_s1,
      GIM_CheckType, /*MI*/0, /*Op*/2, /*Type*/GILLT_s1,
      GIM_Try, /*On fail goto*//*Label 219*/ GIMT_Encode4(17128), // Rule ID 6360 //
        GIM_CheckFeatures, GIMT_Encode2(GIFBS_isWave64),
        GIM_CheckRegBankForClass, /*MI*/0, /*Op*/0, /*RC*/GIMT_Encode2(AMDGPU::SReg_64RegClassID),
        GIM_CheckConstantInt8, /*MI*/0, /*Op*/2, uint8_t(-1),
        // (sub:{ *:[i1] } i1:{ *:[i1] }:$src0, -1:{ *:[i1] })  =>  (S_NOT_B64:{ *:[i1] }:{ *:[i1] } ?:{ *:[i1] }:$src0)
        GIR_BuildMI, /*InsnID*/0, /*Opcode*/GIMT_Encode2(AMDGPU::S_NOT_B64),
        GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/0, // DstI[sdst]
        GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/1, // src0
        GIR_SetImplicitDefDead, /*InsnID*/0, /*OpIdx for AMDGPU::SCC*/0,
        GIR_ConstrainSelectedInstOperands, /*InsnID*/0,
        GIR_EraseFromParent, /*InsnID*/0,
        // GIR_Coverage, 6360,
        GIR_Done,
      // Label 219: @17128
      GIM_Try, /*On fail goto*//*Label 220*/ GIMT_Encode4(17165), // Rule ID 6367 //
        GIM_CheckFeatures, GIMT_Encode2(GIFBS_isWave32),
        GIM_CheckRegBankForClass, /*MI*/0, /*Op*/0, /*RC*/GIMT_Encode2(AMDGPU::SReg_32RegClassID),
        GIM_CheckConstantInt8, /*MI*/0, /*Op*/2, uint8_t(-1),
        // (sub:{ *:[i1] } i1:{ *:[i1] }:$src0, -1:{ *:[i1] })  =>  (S_NOT_B32:{ *:[i1] }:{ *:[i1] } ?:{ *:[i1] }:$src0)
        GIR_BuildMI, /*InsnID*/0, /*Opcode*/GIMT_Encode2(AMDGPU::S_NOT_B32),
        GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/0, // DstI[sdst]
        GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/1, // src0
        GIR_SetImplicitDefDead, /*InsnID*/0, /*OpIdx for AMDGPU::SCC*/0,
        GIR_ConstrainSelectedInstOperands, /*InsnID*/0,
        GIR_EraseFromParent, /*InsnID*/0,
        // GIR_Coverage, 6367,
        GIR_Done,
      // Label 220: @17165
      GIM_Try, /*On fail goto*//*Label 221*/ GIMT_Encode4(17192), // Rule ID 6358 //
        GIM_CheckFeatures, GIMT_Encode2(GIFBS_isWave64),
        GIM_CheckRegBankForClass, /*MI*/0, /*Op*/0, /*RC*/GIMT_Encode2(AMDGPU::SReg_64RegClassID),
        // (sub:{ *:[i1] } i1:{ *:[i1] }:$src0, i1:{ *:[i1] }:$src1)  =>  (S_XOR_B64:{ *:[i1] }:{ *:[i1] } ?:{ *:[i1] }:$src0, ?:{ *:[i1] }:$src1)
        GIR_MutateOpcode, /*InsnID*/0, /*RecycleInsnID*/0, /*Opcode*/GIMT_Encode2(AMDGPU::S_XOR_B64),
        GIR_AddImplicitDef, /*InsnID*/0, GIMT_Encode2(AMDGPU::SCC), GIMT_Encode2(RegState::Dead),
        GIR_ConstrainSelectedInstOperands, /*InsnID*/0,
        // GIR_Coverage, 6358,
        GIR_Done,
      // Label 221: @17192
      GIM_Try, /*On fail goto*//*Label 222*/ GIMT_Encode4(17219), // Rule ID 6365 //
        GIM_CheckFeatures, GIMT_Encode2(GIFBS_isWave32),
        GIM_CheckRegBankForClass, /*MI*/0, /*Op*/0, /*RC*/GIMT_Encode2(AMDGPU::SReg_32RegClassID),
        // (sub:{ *:[i1] } i1:{ *:[i1] }:$src0, i1:{ *:[i1] }:$src1)  =>  (S_XOR_B32:{ *:[i1] }:{ *:[i1] } ?:{ *:[i1] }:$src0, ?:{ *:[i1] }:$src1)
        GIR_MutateOpcode, /*InsnID*/0, /*RecycleInsnID*/0, /*Opcode*/GIMT_Encode2(AMDGPU::S_XOR_B32),
        GIR_AddImplicitDef, /*InsnID*/0, GIMT_Encode2(AMDGPU::SCC), GIMT_Encode2(RegState::Dead),
        GIR_ConstrainSelectedInstOperands, /*InsnID*/0,
        // GIR_Coverage, 6365,
        GIR_Done,
      // Label 222: @17219
      GIM_Reject,
    // Label 218: @17220
    GIM_Reject,
    // Label 213: @17221
    GIM_Try, /*On fail goto*//*Label 223*/ GIMT_Encode4(17333),
      GIM_CheckType, /*MI*/0, /*Op*/1, /*Type*/GILLT_s16,
      GIM_CheckType, /*MI*/0, /*Op*/2, /*Type*/GILLT_s16,
      GIM_CheckRegBankForClass, /*MI*/0, /*Op*/0, /*RC*/GIMT_Encode2(AMDGPU::VGPR_32RegClassID),
      GIM_Try, /*On fail goto*//*Label 224*/ GIMT_Encode4(17300), // Rule ID 945 //
        GIM_CheckFeatures, GIMT_Encode2(GIFBS_isGFX10Plus),
        GIM_CheckComplexPattern, /*MI*/0, /*Op*/1, /*Renderer*/GIMT_Encode2(0), GIMT_Encode2(GICP_gi_vop3opselmods),
        GIM_CheckComplexPattern, /*MI*/0, /*Op*/2, /*Renderer*/GIMT_Encode2(1), GIMT_Encode2(GICP_gi_vop3opselmods),
        // (sub:{ *:[i16] } (VOP3OpSelMods:{ *:[i16] } i16:{ *:[i16] }:$src0, i32:{ *:[i32] }:$src0_modifiers), (VOP3OpSelMods:{ *:[i16] } i16:{ *:[i16] }:$src1, i32:{ *:[i32] }:$src1_modifiers))  =>  (V_SUB_NC_U16_e64:{ *:[i16] } i32:{ *:[i32] }:$src0_modifiers, i16:{ *:[i16] }:$src0, i32:{ *:[i32] }:$src1_modifiers, i16:{ *:[i16] }:$src1)
        GIR_BuildMI, /*InsnID*/0, /*Opcode*/GIMT_Encode2(AMDGPU::V_SUB_NC_U16_e64),
        GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/0, // DstI[vdst]
        GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/1, // src0_modifiers
        GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/0, // src0
        GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(1), /*SubOperand*/1, // src1_modifiers
        GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(1), /*SubOperand*/0, // src1
        GIR_AddImm8, /*InsnID*/0, /*Imm*/0,
        GIR_AddImm8, /*InsnID*/0, /*Imm*/0,
        GIR_ConstrainSelectedInstOperands, /*InsnID*/0,
        GIR_EraseFromParent, /*InsnID*/0,
        // GIR_Coverage, 945,
        GIR_Done,
      // Label 224: @17300
      GIM_Try, /*On fail goto*//*Label 225*/ GIMT_Encode4(17332), // Rule ID 837 //
        GIM_CheckFeatures, GIMT_Encode2(GIFBS_isGFX8GFX9),
        // (sub:{ *:[i16] } i16:{ *:[i16] }:$src0, i16:{ *:[i16] }:$src1)  =>  (V_SUB_U16_e64:{ *:[i16] } i16:{ *:[i16] }:$src0, i16:{ *:[i16] }:$src1)
        GIR_BuildMI, /*InsnID*/0, /*Opcode*/GIMT_Encode2(AMDGPU::V_SUB_U16_e64),
        GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/0, // DstI[vdst]
        GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/1, // src0
        GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/2, // src1
        GIR_AddImm8, /*InsnID*/0, /*Imm*/0,
        GIR_ConstrainSelectedInstOperands, /*InsnID*/0,
        GIR_EraseFromParent, /*InsnID*/0,
        // GIR_Coverage, 837,
        GIR_Done,
      // Label 225: @17332
      GIM_Reject,
    // Label 223: @17333
    GIM_Reject,
    // Label 214: @17334
    GIM_Try, /*On fail goto*//*Label 226*/ GIMT_Encode4(17476),
      GIM_CheckType, /*MI*/0, /*Op*/1, /*Type*/GILLT_s32,
      GIM_CheckType, /*MI*/0, /*Op*/2, /*Type*/GILLT_s32,
      GIM_Try, /*On fail goto*//*Label 227*/ GIMT_Encode4(17385), // Rule ID 46 //
        GIM_CheckRegBankForClass, /*MI*/0, /*Op*/0, /*RC*/GIMT_Encode2(AMDGPU::SReg_32RegClassID),
        GIM_CheckRegBankForClass, /*MI*/0, /*Op*/1, /*RC*/GIMT_Encode2(AMDGPU::SReg_32RegClassID),
        GIM_CheckRegBankForClass, /*MI*/0, /*Op*/2, /*RC*/GIMT_Encode2(AMDGPU::SReg_32RegClassID),
        GIM_CheckCxxInsnPredicate, /*MI*/0, /*FnId*/GIMT_Encode2(GICXXPred_MI_Predicate_anonymous_17604),
        // (sub:{ *:[i32] } SSrc_b32:{ *:[i32] }:$src0, SSrc_b32:{ *:[i32] }:$src1)<<P:Predicate_anonymous_17604>>  =>  (S_SUB_I32:{ *:[i32] }:{ *:[i1] } SSrc_b32:{ *:[i32] }:$src0, SSrc_b32:{ *:[i32] }:$src1)
        GIR_MutateOpcode, /*InsnID*/0, /*RecycleInsnID*/0, /*Opcode*/GIMT_Encode2(AMDGPU::S_SUB_I32),
        GIR_AddImplicitDef, /*InsnID*/0, GIMT_Encode2(AMDGPU::SCC), GIMT_Encode2(RegState::Dead),
        GIR_ConstrainSelectedInstOperands, /*InsnID*/0,
        // GIR_Coverage, 46,
        GIR_Done,
      // Label 227: @17385
      GIM_Try, /*On fail goto*//*Label 228*/ GIMT_Encode4(17426), // Rule ID 2099 //
        GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasAddNoCarryInsts),
        GIM_CheckRegBankForClass, /*MI*/0, /*Op*/0, /*RC*/GIMT_Encode2(AMDGPU::VGPR_32RegClassID),
        GIM_CheckCxxInsnPredicate, /*MI*/0, /*FnId*/GIMT_Encode2(GICXXPred_MI_Predicate_anonymous_22547),
        // (sub:{ *:[i32] } i32:{ *:[i32] }:$src0, i32:{ *:[i32] }:$src1)<<P:Predicate_anonymous_22547>>  =>  (V_SUB_U32_e64:{ *:[i32] } ?:{ *:[i32] }:$src0, ?:{ *:[i32] }:$src1, 0:{ *:[i1] })
        GIR_BuildMI, /*InsnID*/0, /*Opcode*/GIMT_Encode2(AMDGPU::V_SUB_U32_e64),
        GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/0, // DstI[vdst]
        GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/1, // src0
        GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/2, // src1
        GIR_AddImm8, /*InsnID*/0, /*Imm*/0,
        GIR_ConstrainSelectedInstOperands, /*InsnID*/0,
        GIR_EraseFromParent, /*InsnID*/0,
        // GIR_Coverage, 2099,
        GIR_Done,
      // Label 228: @17426
      GIM_Try, /*On fail goto*//*Label 229*/ GIMT_Encode4(17475), // Rule ID 2101 //
        GIM_CheckFeatures, GIMT_Encode2(GIFBS_isGFX6GFX7GFX8GFX9),
        GIM_CheckRegBankForClass, /*MI*/0, /*Op*/0, /*RC*/GIMT_Encode2(AMDGPU::VGPR_32RegClassID),
        GIM_CheckCxxInsnPredicate, /*MI*/0, /*FnId*/GIMT_Encode2(GICXXPred_MI_Predicate_anonymous_22547),
        // (sub:{ *:[i32] } i32:{ *:[i32] }:$src0, i32:{ *:[i32] }:$src1)<<P:Predicate_anonymous_22547>>  =>  (V_SUB_CO_U32_e64:{ *:[i32] }:{ *:[i1] } ?:{ *:[i32] }:$src0, ?:{ *:[i32] }:$src1, 0:{ *:[i1] })
        GIR_MakeTempReg, /*TempRegID*/0, /*TypeID*/GILLT_s1,
        GIR_BuildMI, /*InsnID*/0, /*Opcode*/GIMT_Encode2(AMDGPU::V_SUB_CO_U32_e64),
        GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/0, // DstI[vdst]
        GIR_AddTempRegister, /*InsnID*/0, /*TempRegID*/0, /*TempRegFlags*/GIMT_Encode2(RegState::Define|RegState::Dead),
        GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/1, // src0
        GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/2, // src1
        GIR_AddImm8, /*InsnID*/0, /*Imm*/0,
        GIR_ConstrainSelectedInstOperands, /*InsnID*/0,
        GIR_EraseFromParent, /*InsnID*/0,
        // GIR_Coverage, 2101,
        GIR_Done,
      // Label 229: @17475
      GIM_Reject,
    // Label 226: @17476
    GIM_Reject,
    // Label 215: @17477
    GIM_Try, /*On fail goto*//*Label 230*/ GIMT_Encode4(17551),
      GIM_CheckType, /*MI*/0, /*Op*/1, /*Type*/GILLT_s64,
      GIM_CheckType, /*MI*/0, /*Op*/2, /*Type*/GILLT_s64,
      GIM_Try, /*On fail goto*//*Label 231*/ GIMT_Encode4(17522), // Rule ID 1117 //
        GIM_CheckRegBankForClass, /*MI*/0, /*Op*/0, /*RC*/GIMT_Encode2(AMDGPU::VReg_64RegClassID),
        GIM_CheckCxxInsnPredicate, /*MI*/0, /*FnId*/GIMT_Encode2(GICXXPred_MI_Predicate_anonymous_22547),
        // (sub:{ *:[i64] } i64:{ *:[i64] }:$src0, i64:{ *:[i64] }:$src1)<<P:Predicate_anonymous_22547>>  =>  (V_SUB_U64_PSEUDO:{ *:[i64] } i64:{ *:[i64] }:$src0, i64:{ *:[i64] }:$src1)
        GIR_MutateOpcode, /*InsnID*/0, /*RecycleInsnID*/0, /*Opcode*/GIMT_Encode2(AMDGPU::V_SUB_U64_PSEUDO),
        GIR_AddImplicitDef, /*InsnID*/0, GIMT_Encode2(AMDGPU::VCC), GIMT_Encode2(RegState::Dead),
        GIR_AddImplicitUse, /*InsnID*/0, GIMT_Encode2(AMDGPU::EXEC),
        GIR_ConstrainSelectedInstOperands, /*InsnID*/0,
        // GIR_Coverage, 1117,
        GIR_Done,
      // Label 231: @17522
      GIM_Try, /*On fail goto*//*Label 232*/ GIMT_Encode4(17550), // Rule ID 1119 //
        GIM_CheckRegBankForClass, /*MI*/0, /*Op*/0, /*RC*/GIMT_Encode2(AMDGPU::SReg_64RegClassID),
        GIM_CheckCxxInsnPredicate, /*MI*/0, /*FnId*/GIMT_Encode2(GICXXPred_MI_Predicate_anonymous_17604),
        // (sub:{ *:[i64] } i64:{ *:[i64] }:$src0, i64:{ *:[i64] }:$src1)<<P:Predicate_anonymous_17604>>  =>  (S_SUB_U64_PSEUDO:{ *:[i64] }:{ *:[i1] } i64:{ *:[i64] }:$src0, i64:{ *:[i64] }:$src1)
        GIR_MutateOpcode, /*InsnID*/0, /*RecycleInsnID*/0, /*Opcode*/GIMT_Encode2(AMDGPU::S_SUB_U64_PSEUDO),
        GIR_AddImplicitDef, /*InsnID*/0, GIMT_Encode2(AMDGPU::SCC), GIMT_Encode2(RegState::Dead),
        GIR_ConstrainSelectedInstOperands, /*InsnID*/0,
        // GIR_Coverage, 1119,
        GIR_Done,
      // Label 232: @17550
      GIM_Reject,
    // Label 230: @17551
    GIM_Reject,
    // Label 216: @17552
    GIM_Try, /*On fail goto*//*Label 233*/ GIMT_Encode4(17632), // Rule ID 976 //
      GIM_CheckType, /*MI*/0, /*Op*/1, /*Type*/GILLT_v2s16,
      GIM_CheckType, /*MI*/0, /*Op*/2, /*Type*/GILLT_v2s16,
      GIM_CheckRegBankForClass, /*MI*/0, /*Op*/0, /*RC*/GIMT_Encode2(AMDGPU::VGPR_32RegClassID),
      GIM_CheckComplexPattern, /*MI*/0, /*Op*/1, /*Renderer*/GIMT_Encode2(0), GIMT_Encode2(GICP_gi_vop3pmods),
      GIM_CheckComplexPattern, /*MI*/0, /*Op*/2, /*Renderer*/GIMT_Encode2(1), GIMT_Encode2(GICP_gi_vop3pmods),
      // (sub:{ *:[v2i16] } (VOP3PMods:{ *:[v2i16] } v2i16:{ *:[v2i16] }:$src0, i32:{ *:[i32] }:$src0_modifiers), (VOP3PMods:{ *:[v2i16] } v2i16:{ *:[v2i16] }:$src1, i32:{ *:[i32] }:$src1_modifiers))  =>  (V_PK_SUB_I16:{ *:[v2i16] } i32:{ *:[i32] }:$src0_modifiers, v2i16:{ *:[v2i16] }:$src0, i32:{ *:[i32] }:$src1_modifiers, v2i16:{ *:[v2i16] }:$src1)
      GIR_BuildMI, /*InsnID*/0, /*Opcode*/GIMT_Encode2(AMDGPU::V_PK_SUB_I16),
      GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/0, // DstI[vdst]
      GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/1, // src0_modifiers
      GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/0, // src0
      GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(1), /*SubOperand*/1, // src1_modifiers
      GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(1), /*SubOperand*/0, // src1
      GIR_AddImm8, /*InsnID*/0, /*Imm*/0,
      GIR_AddImm8, /*InsnID*/0, /*Imm*/0,
      GIR_AddImm8, /*InsnID*/0, /*Imm*/0,
      GIR_AddImm8, /*InsnID*/0, /*Imm*/0,
      GIR_AddImm8, /*InsnID*/0, /*Imm*/0,
      GIR_ConstrainSelectedInstOperands, /*InsnID*/0,
      GIR_EraseFromParent, /*InsnID*/0,
      // GIR_Coverage, 976,
      GIR_Done,
    // Label 233: @17632
    GIM_Reject,
    // Label 217: @17633
    GIM_Reject,
    // Label 2: @17634
    GIM_SwitchType, /*MI*/0, /*Op*/0, /*[*/GIMT_Encode2(8), GIMT_Encode2(12), /*)*//*default:*//*Label 238*/ GIMT_Encode4(17959),
    /*GILLT_s16*//*Label 234*/ GIMT_Encode4(17661),
    /*GILLT_s32*//*Label 235*/ GIMT_Encode4(17721),
    /*GILLT_s64*//*Label 236*/ GIMT_Encode4(17844),
    /*GILLT_v2s16*//*Label 237*/ GIMT_Encode4(17878),
    // Label 234: @17661
    GIM_Try, /*On fail goto*//*Label 239*/ GIMT_Encode4(17720),
      GIM_CheckType, /*MI*/0, /*Op*/1, /*Type*/GILLT_s16,
      GIM_CheckType, /*MI*/0, /*Op*/2, /*Type*/GILLT_s16,
      GIM_CheckRegBankForClass, /*MI*/0, /*Op*/0, /*RC*/GIMT_Encode2(AMDGPU::VGPR_32RegClassID),
      GIM_Try, /*On fail goto*//*Label 240*/ GIMT_Encode4(17699), // Rule ID 811 //
        GIM_CheckFeatures, GIMT_Encode2(GIFBS_Has16BitInsts_NotHasTrue16BitInsts),
        // (mul:{ *:[i16] } i16:{ *:[i16] }:$src0, i16:{ *:[i16] }:$src1)  =>  (V_MUL_LO_U16_e64:{ *:[i16] } i16:{ *:[i16] }:$src0, i16:{ *:[i16] }:$src1)
        GIR_MutateOpcode, /*InsnID*/0, /*RecycleInsnID*/0, /*Opcode*/GIMT_Encode2(AMDGPU::V_MUL_LO_U16_e64),
        GIR_AddImplicitUse, /*InsnID*/0, GIMT_Encode2(AMDGPU::EXEC),
        GIR_ConstrainSelectedInstOperands, /*InsnID*/0,
        // GIR_Coverage, 811,
        GIR_Done,
      // Label 240: @17699
      GIM_Try, /*On fail goto*//*Label 241*/ GIMT_Encode4(17719), // Rule ID 812 //
        GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasTrue16BitInsts),
        // (mul:{ *:[i16] } i16:{ *:[i16] }:$src0, i16:{ *:[i16] }:$src1)  =>  (V_MUL_LO_U16_t16_e64:{ *:[i16] } i16:{ *:[i16] }:$src0, i16:{ *:[i16] }:$src1)
        GIR_MutateOpcode, /*InsnID*/0, /*RecycleInsnID*/0, /*Opcode*/GIMT_Encode2(AMDGPU::V_MUL_LO_U16_t16_e64),
        GIR_AddImplicitUse, /*InsnID*/0, GIMT_Encode2(AMDGPU::EXEC),
        GIR_ConstrainSelectedInstOperands, /*InsnID*/0,
        // GIR_Coverage, 812,
        GIR_Done,
      // Label 241: @17719
      GIM_Reject,
    // Label 239: @17720
    GIM_Reject,
    // Label 235: @17721
    GIM_Try, /*On fail goto*//*Label 242*/ GIMT_Encode4(17843),
      GIM_CheckType, /*MI*/0, /*Op*/1, /*Type*/GILLT_s32,
      GIM_CheckType, /*MI*/0, /*Op*/2, /*Type*/GILLT_s32,
      GIM_Try, /*On fail goto*//*Label 243*/ GIMT_Encode4(17756), // Rule ID 83 //
        GIM_CheckRegBankForClass, /*MI*/0, /*Op*/0, /*RC*/GIMT_Encode2(AMDGPU::SReg_32RegClassID),
        GIM_CheckCxxInsnPredicate, /*MI*/0, /*FnId*/GIMT_Encode2(GICXXPred_MI_Predicate_anonymous_17614),
        // (mul:{ *:[i32] } i32:{ *:[i32] }:$src0, i32:{ *:[i32] }:$src1)<<P:Predicate_anonymous_17614>>  =>  (S_MUL_I32:{ *:[i32] } i32:{ *:[i32] }:$src0, i32:{ *:[i32] }:$src1)
        GIR_MutateOpcode, /*InsnID*/0, /*RecycleInsnID*/0, /*Opcode*/GIMT_Encode2(AMDGPU::S_MUL_I32),
        GIR_ConstrainSelectedInstOperands, /*InsnID*/0,
        // GIR_Coverage, 83,
        GIR_Done,
      // Label 243: @17756
      GIM_Try, /*On fail goto*//*Label 244*/ GIMT_Encode4(17799), // Rule ID 865 //
        GIM_CheckRegBankForClass, /*MI*/0, /*Op*/0, /*RC*/GIMT_Encode2(AMDGPU::VGPR_32RegClassID),
        GIM_CheckCxxInsnPredicate, /*MI*/0, /*FnId*/GIMT_Encode2(GICXXPred_MI_Predicate_anonymous_23209),
        GIM_CheckComplexPattern, /*MI*/0, /*Op*/1, /*Renderer*/GIMT_Encode2(0), GIMT_Encode2(GICP_gi_vop3mods0),
        // (mul:{ *:[i32] } (VOP3Mods0:{ *:[i32] } i32:{ *:[i32] }:$src0), i32:{ *:[i32] }:$src1)<<P:Predicate_anonymous_23209>>  =>  (V_MUL_LO_U32_e64:{ *:[i32] } i32:{ *:[i32] }:$src0, i32:{ *:[i32] }:$src1)
        GIR_BuildMI, /*InsnID*/0, /*Opcode*/GIMT_Encode2(AMDGPU::V_MUL_LO_U32_e64),
        GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/0, // DstI[vdst]
        GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/0, // src0
        GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/2, // src1
        GIR_ConstrainSelectedInstOperands, /*InsnID*/0,
        GIR_EraseFromParent, /*InsnID*/0,
        // GIR_Coverage, 865,
        GIR_Done,
      // Label 244: @17799
      GIM_Try, /*On fail goto*//*Label 245*/ GIMT_Encode4(17842), // Rule ID 7183 //
        GIM_CheckRegBankForClass, /*MI*/0, /*Op*/0, /*RC*/GIMT_Encode2(AMDGPU::VGPR_32RegClassID),
        GIM_CheckCxxInsnPredicate, /*MI*/0, /*FnId*/GIMT_Encode2(GICXXPred_MI_Predicate_anonymous_23209),
        GIM_CheckComplexPattern, /*MI*/0, /*Op*/2, /*Renderer*/GIMT_Encode2(0), GIMT_Encode2(GICP_gi_vop3mods0),
        // (mul:{ *:[i32] } i32:{ *:[i32] }:$src1, (VOP3Mods0:{ *:[i32] } i32:{ *:[i32] }:$src0))<<P:Predicate_anonymous_23209>>  =>  (V_MUL_LO_U32_e64:{ *:[i32] } i32:{ *:[i32] }:$src0, i32:{ *:[i32] }:$src1)
        GIR_BuildMI, /*InsnID*/0, /*Opcode*/GIMT_Encode2(AMDGPU::V_MUL_LO_U32_e64),
        GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/0, // DstI[vdst]
        GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/0, // src0
        GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/1, // src1
        GIR_ConstrainSelectedInstOperands, /*InsnID*/0,
        GIR_EraseFromParent, /*InsnID*/0,
        // GIR_Coverage, 7183,
        GIR_Done,
      // Label 245: @17842
      GIM_Reject,
    // Label 242: @17843
    GIM_Reject,
    // Label 236: @17844
    GIM_Try, /*On fail goto*//*Label 246*/ GIMT_Encode4(17877), // Rule ID 53 //
      GIM_CheckFeatures, GIMT_Encode2(GIFBS_isGFX12Plus),
      GIM_CheckType, /*MI*/0, /*Op*/1, /*Type*/GILLT_s64,
      GIM_CheckType, /*MI*/0, /*Op*/2, /*Type*/GILLT_s64,
      GIM_CheckRegBankForClass, /*MI*/0, /*Op*/0, /*RC*/GIMT_Encode2(AMDGPU::SReg_64RegClassID),
      GIM_CheckCxxInsnPredicate, /*MI*/0, /*FnId*/GIMT_Encode2(GICXXPred_MI_Predicate_anonymous_17614),
      // (mul:{ *:[i64] } i64:{ *:[i64] }:$src0, i64:{ *:[i64] }:$src1)<<P:Predicate_anonymous_17614>>  =>  (S_MUL_U64:{ *:[i64] } i64:{ *:[i64] }:$src0, i64:{ *:[i64] }:$src1)
      GIR_MutateOpcode, /*InsnID*/0, /*RecycleInsnID*/0, /*Opcode*/GIMT_Encode2(AMDGPU::S_MUL_U64),
      GIR_ConstrainSelectedInstOperands, /*InsnID*/0,
      // GIR_Coverage, 53,
      GIR_Done,
    // Label 246: @17877
    GIM_Reject,
    // Label 237: @17878
    GIM_Try, /*On fail goto*//*Label 247*/ GIMT_Encode4(17958), // Rule ID 969 //
      GIM_CheckType, /*MI*/0, /*Op*/1, /*Type*/GILLT_v2s16,
      GIM_CheckType, /*MI*/0, /*Op*/2, /*Type*/GILLT_v2s16,
      GIM_CheckRegBankForClass, /*MI*/0, /*Op*/0, /*RC*/GIMT_Encode2(AMDGPU::VGPR_32RegClassID),
      GIM_CheckComplexPattern, /*MI*/0, /*Op*/1, /*Renderer*/GIMT_Encode2(0), GIMT_Encode2(GICP_gi_vop3pmods),
      GIM_CheckComplexPattern, /*MI*/0, /*Op*/2, /*Renderer*/GIMT_Encode2(1), GIMT_Encode2(GICP_gi_vop3pmods),
      // (mul:{ *:[v2i16] } (VOP3PMods:{ *:[v2i16] } v2i16:{ *:[v2i16] }:$src0, i32:{ *:[i32] }:$src0_modifiers), (VOP3PMods:{ *:[v2i16] } v2i16:{ *:[v2i16] }:$src1, i32:{ *:[i32] }:$src1_modifiers))  =>  (V_PK_MUL_LO_U16:{ *:[v2i16] } i32:{ *:[i32] }:$src0_modifiers, v2i16:{ *:[v2i16] }:$src0, i32:{ *:[i32] }:$src1_modifiers, v2i16:{ *:[v2i16] }:$src1)
      GIR_BuildMI, /*InsnID*/0, /*Opcode*/GIMT_Encode2(AMDGPU::V_PK_MUL_LO_U16),
      GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/0, // DstI[vdst]
      GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/1, // src0_modifiers
      GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/0, // src0
      GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(1), /*SubOperand*/1, // src1_modifiers
      GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(1), /*SubOperand*/0, // src1
      GIR_AddImm8, /*InsnID*/0, /*Imm*/0,
      GIR_AddImm8, /*InsnID*/0, /*Imm*/0,
      GIR_AddImm8, /*InsnID*/0, /*Imm*/0,
      GIR_AddImm8, /*InsnID*/0, /*Imm*/0,
      GIR_AddImm8, /*InsnID*/0, /*Imm*/0,
      GIR_ConstrainSelectedInstOperands, /*InsnID*/0,
      GIR_EraseFromParent, /*InsnID*/0,
      // GIR_Coverage, 969,
      GIR_Done,
    // Label 247: @17958
    GIM_Reject,
    // Label 238: @17959
    GIM_Reject,
    // Label 3: @17960
    GIM_SwitchType, /*MI*/0, /*Op*/0, /*[*/GIMT_Encode2(7), GIMT_Encode2(17), /*)*//*default:*//*Label 255*/ GIMT_Encode4(19109),
    /*GILLT_s1*//*Label 248*/ GIMT_Encode4(18011),
    /*GILLT_s16*//*Label 249*/ GIMT_Encode4(18080),
    /*GILLT_s32*//*Label 250*/ GIMT_Encode4(18270),
    /*GILLT_s64*//*Label 251*/ GIMT_Encode4(18463),
    /*GILLT_v2s16*//*Label 252*/ GIMT_Encode4(18616),
    /*GILLT_v2s32*//*Label 253*/ GIMT_Encode4(18801), GIMT_Encode4(0), GIMT_Encode4(0), GIMT_Encode4(0),
    /*GILLT_v4s16*//*Label 254*/ GIMT_Encode4(18955),
    // Label 248: @18011
    GIM_Try, /*On fail goto*//*Label 256*/ GIMT_Encode4(18079),
      GIM_CheckType, /*MI*/0, /*Op*/1, /*Type*/GILLT_s1,
      GIM_CheckType, /*MI*/0, /*Op*/2, /*Type*/GILLT_s1,
      GIM_Try, /*On fail goto*//*Label 257*/ GIMT_Encode4(18051), // Rule ID 6354 //
        GIM_CheckFeatures, GIMT_Encode2(GIFBS_isWave64),
        GIM_CheckRegBankForClass, /*MI*/0, /*Op*/0, /*RC*/GIMT_Encode2(AMDGPU::SReg_64RegClassID),
        // (and:{ *:[i1] } i1:{ *:[i1] }:$src0, i1:{ *:[i1] }:$src1)  =>  (S_AND_B64:{ *:[i1] }:{ *:[i1] } ?:{ *:[i1] }:$src0, ?:{ *:[i1] }:$src1)
        GIR_MutateOpcode, /*InsnID*/0, /*RecycleInsnID*/0, /*Opcode*/GIMT_Encode2(AMDGPU::S_AND_B64),
        GIR_AddImplicitDef, /*InsnID*/0, GIMT_Encode2(AMDGPU::SCC), GIMT_Encode2(RegState::Dead),
        GIR_ConstrainSelectedInstOperands, /*InsnID*/0,
        // GIR_Coverage, 6354,
        GIR_Done,
      // Label 257: @18051
      GIM_Try, /*On fail goto*//*Label 258*/ GIMT_Encode4(18078), // Rule ID 6361 //
        GIM_CheckFeatures, GIMT_Encode2(GIFBS_isWave32),
        GIM_CheckRegBankForClass, /*MI*/0, /*Op*/0, /*RC*/GIMT_Encode2(AMDGPU::SReg_32RegClassID),
        // (and:{ *:[i1] } i1:{ *:[i1] }:$src0, i1:{ *:[i1] }:$src1)  =>  (S_AND_B32:{ *:[i1] }:{ *:[i1] } ?:{ *:[i1] }:$src0, ?:{ *:[i1] }:$src1)
        GIR_MutateOpcode, /*InsnID*/0, /*RecycleInsnID*/0, /*Opcode*/GIMT_Encode2(AMDGPU::S_AND_B32),
        GIR_AddImplicitDef, /*InsnID*/0, GIMT_Encode2(AMDGPU::SCC), GIMT_Encode2(RegState::Dead),
        GIR_ConstrainSelectedInstOperands, /*InsnID*/0,
        // GIR_Coverage, 6361,
        GIR_Done,
      // Label 258: @18078
      GIM_Reject,
    // Label 256: @18079
    GIM_Reject,
    // Label 249: @18080
    GIM_Try, /*On fail goto*//*Label 259*/ GIMT_Encode4(18269),
      GIM_CheckType, /*MI*/0, /*Op*/1, /*Type*/GILLT_s16,
      GIM_CheckType, /*MI*/0, /*Op*/2, /*Type*/GILLT_s16,
      GIM_Try, /*On fail goto*//*Label 260*/ GIMT_Encode4(18157), // Rule ID 7196 //
        GIM_CheckRegBankForClass, /*MI*/0, /*Op*/0, /*RC*/GIMT_Encode2(AMDGPU::SReg_32RegClassID),
        GIM_RecordInsn, /*DefineMI*/1, /*MI*/0, /*OpIdx*/1, // MIs[1]
        GIM_CheckOpcode, /*MI*/1, GIMT_Encode2(TargetOpcode::G_XOR),
        GIM_CheckType, /*MI*/1, /*Op*/1, /*Type*/GILLT_s16,
        GIM_CheckType, /*MI*/1, /*Op*/2, /*Type*/GILLT_s16,
        GIM_CheckConstantInt8, /*MI*/1, /*Op*/2, uint8_t(-1),
        GIM_CheckCxxInsnPredicate, /*MI*/1, /*FnId*/GIMT_Encode2(GICXXPred_MI_Predicate_anonymous_17562),
        GIM_CheckCxxInsnPredicate, /*MI*/0, /*FnId*/GIMT_Encode2(GICXXPred_MI_Predicate_anonymous_17615),
        GIM_CheckIsSafeToFold, /*InsnID*/1,
        // (and:{ *:[i16] } (xor:{ *:[i16] } i16:{ *:[i16] }:$src1, -1:{ *:[i16] })<<P:Predicate_anonymous_17562>>, i16:{ *:[i16] }:$src0)<<P:Predicate_anonymous_17615>>  =>  (S_ANDN2_B32:{ *:[i16] }:{ *:[i1] } SSrc_b32:{ *:[i16] }:$src0, SSrc_b32:{ *:[i16] }:$src1)
        GIR_BuildMI, /*InsnID*/0, /*Opcode*/GIMT_Encode2(AMDGPU::S_ANDN2_B32),
        GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/0, // DstI[sdst]
        GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/2, // src0
        GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/1, /*OpIdx*/1, // src1
        GIR_SetImplicitDefDead, /*InsnID*/0, /*OpIdx for AMDGPU::SCC*/0,
        GIR_ConstrainSelectedInstOperands, /*InsnID*/0,
        GIR_EraseFromParent, /*InsnID*/0,
        // GIR_Coverage, 7196,
        GIR_Done,
      // Label 260: @18157
      GIM_Try, /*On fail goto*//*Label 261*/ GIMT_Encode4(18221), // Rule ID 1658 //
        GIM_CheckRegBankForClass, /*MI*/0, /*Op*/0, /*RC*/GIMT_Encode2(AMDGPU::SReg_32RegClassID),
        GIM_RecordInsn, /*DefineMI*/1, /*MI*/0, /*OpIdx*/2, // MIs[1]
        GIM_CheckOpcode, /*MI*/1, GIMT_Encode2(TargetOpcode::G_XOR),
        GIM_CheckType, /*MI*/1, /*Op*/1, /*Type*/GILLT_s16,
        GIM_CheckType, /*MI*/1, /*Op*/2, /*Type*/GILLT_s16,
        GIM_CheckConstantInt8, /*MI*/1, /*Op*/2, uint8_t(-1),
        GIM_CheckCxxInsnPredicate, /*MI*/1, /*FnId*/GIMT_Encode2(GICXXPred_MI_Predicate_anonymous_17562),
        GIM_CheckCxxInsnPredicate, /*MI*/0, /*FnId*/GIMT_Encode2(GICXXPred_MI_Predicate_anonymous_17615),
        GIM_CheckIsSafeToFold, /*InsnID*/1,
        // (and:{ *:[i16] } i16:{ *:[i16] }:$src0, (xor:{ *:[i16] } i16:{ *:[i16] }:$src1, -1:{ *:[i16] })<<P:Predicate_anonymous_17562>>)<<P:Predicate_anonymous_17615>>  =>  (S_ANDN2_B32:{ *:[i16] }:{ *:[i1] } SSrc_b32:{ *:[i16] }:$src0, SSrc_b32:{ *:[i16] }:$src1)
        GIR_BuildMI, /*InsnID*/0, /*Opcode*/GIMT_Encode2(AMDGPU::S_ANDN2_B32),
        GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/0, // DstI[sdst]
        GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/1, // src0
        GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/1, /*OpIdx*/1, // src1
        GIR_SetImplicitDefDead, /*InsnID*/0, /*OpIdx for AMDGPU::SCC*/0,
        GIR_ConstrainSelectedInstOperands, /*InsnID*/0,
        GIR_EraseFromParent, /*InsnID*/0,
        // GIR_Coverage, 1658,
        GIR_Done,
      // Label 261: @18221
      GIM_Try, /*On fail goto*//*Label 262*/ GIMT_Encode4(18243), // Rule ID 2126 //
        GIM_CheckRegBankForClass, /*MI*/0, /*Op*/0, /*RC*/GIMT_Encode2(AMDGPU::VGPR_32RegClassID),
        // (and:{ *:[i16] } i16:{ *:[i16] }:$src0, i16:{ *:[i16] }:$src1)  =>  (V_AND_B32_e64:{ *:[i16] } VSrc_b32:{ *:[i16] }:$src0, VSrc_b32:{ *:[i16] }:$src1)
        GIR_MutateOpcode, /*InsnID*/0, /*RecycleInsnID*/0, /*Opcode*/GIMT_Encode2(AMDGPU::V_AND_B32_e64),
        GIR_AddImplicitUse, /*InsnID*/0, GIMT_Encode2(AMDGPU::EXEC),
        GIR_ConstrainSelectedInstOperands, /*InsnID*/0,
        // GIR_Coverage, 2126,
        GIR_Done,
      // Label 262: @18243
      GIM_Try, /*On fail goto*//*Label 263*/ GIMT_Encode4(18268), // Rule ID 833 //
        GIM_CheckFeatures, GIMT_Encode2(GIFBS_isGFX11Plus),
        GIM_CheckRegBankForClass, /*MI*/0, /*Op*/0, /*RC*/GIMT_Encode2(AMDGPU::VGPR_32RegClassID),
        // (and:{ *:[i16] } i16:{ *:[i16] }:$src0, i16:{ *:[i16] }:$src1)  =>  (V_AND_B16_t16_e64:{ *:[i16] } i16:{ *:[i16] }:$src0, i16:{ *:[i16] }:$src1)
        GIR_MutateOpcode, /*InsnID*/0, /*RecycleInsnID*/0, /*Opcode*/GIMT_Encode2(AMDGPU::V_AND_B16_t16_e64),
        GIR_AddImplicitUse, /*InsnID*/0, GIMT_Encode2(AMDGPU::EXEC),
        GIR_ConstrainSelectedInstOperands, /*InsnID*/0,
        // GIR_Coverage, 833,
        GIR_Done,
      // Label 263: @18268
      GIM_Reject,
    // Label 259: @18269
    GIM_Reject,
    // Label 250: @18270
    GIM_Try, /*On fail goto*//*Label 264*/ GIMT_Encode4(18462),
      GIM_CheckType, /*MI*/0, /*Op*/1, /*Type*/GILLT_s32,
      GIM_CheckType, /*MI*/0, /*Op*/2, /*Type*/GILLT_s32,
      GIM_Try, /*On fail goto*//*Label 265*/ GIMT_Encode4(18347), // Rule ID 7116 //
        GIM_CheckRegBankForClass, /*MI*/0, /*Op*/0, /*RC*/GIMT_Encode2(AMDGPU::SReg_32RegClassID),
        GIM_RecordInsn, /*DefineMI*/1, /*MI*/0, /*OpIdx*/1, // MIs[1]
        GIM_CheckOpcode, /*MI*/1, GIMT_Encode2(TargetOpcode::G_XOR),
        GIM_CheckType, /*MI*/1, /*Op*/1, /*Type*/GILLT_s32,
        GIM_CheckType, /*MI*/1, /*Op*/2, /*Type*/GILLT_s32,
        GIM_CheckConstantInt8, /*MI*/1, /*Op*/2, uint8_t(-1),
        GIM_CheckCxxInsnPredicate, /*MI*/1, /*FnId*/GIMT_Encode2(GICXXPred_MI_Predicate_anonymous_17562),
        GIM_CheckCxxInsnPredicate, /*MI*/0, /*FnId*/GIMT_Encode2(GICXXPred_MI_Predicate_anonymous_17615),
        GIM_CheckIsSafeToFold, /*InsnID*/1,
        // (and:{ *:[i32] } (xor:{ *:[i32] } i32:{ *:[i32] }:$src1, -1:{ *:[i32] })<<P:Predicate_anonymous_17562>>, i32:{ *:[i32] }:$src0)<<P:Predicate_anonymous_17615>>  =>  (S_ANDN2_B32:{ *:[i32] }:{ *:[i1] } i32:{ *:[i32] }:$src0, i32:{ *:[i32] }:$src1)
        GIR_BuildMI, /*InsnID*/0, /*Opcode*/GIMT_Encode2(AMDGPU::S_ANDN2_B32),
        GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/0, // DstI[sdst]
        GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/2, // src0
        GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/1, /*OpIdx*/1, // src1
        GIR_SetImplicitDefDead, /*InsnID*/0, /*OpIdx for AMDGPU::SCC*/0,
        GIR_ConstrainSelectedInstOperands, /*InsnID*/0,
        GIR_EraseFromParent, /*InsnID*/0,
        // GIR_Coverage, 7116,
        GIR_Done,
      // Label 265: @18347
      GIM_Try, /*On fail goto*//*Label 266*/ GIMT_Encode4(18411), // Rule ID 66 //
        GIM_CheckRegBankForClass, /*MI*/0, /*Op*/0, /*RC*/GIMT_Encode2(AMDGPU::SReg_32RegClassID),
        GIM_RecordInsn, /*DefineMI*/1, /*MI*/0, /*OpIdx*/2, // MIs[1]
        GIM_CheckOpcode, /*MI*/1, GIMT_Encode2(TargetOpcode::G_XOR),
        GIM_CheckType, /*MI*/1, /*Op*/1, /*Type*/GILLT_s32,
        GIM_CheckType, /*MI*/1, /*Op*/2, /*Type*/GILLT_s32,
        GIM_CheckConstantInt8, /*MI*/1, /*Op*/2, uint8_t(-1),
        GIM_CheckCxxInsnPredicate, /*MI*/1, /*FnId*/GIMT_Encode2(GICXXPred_MI_Predicate_anonymous_17562),
        GIM_CheckCxxInsnPredicate, /*MI*/0, /*FnId*/GIMT_Encode2(GICXXPred_MI_Predicate_anonymous_17615),
        GIM_CheckIsSafeToFold, /*InsnID*/1,
        // (and:{ *:[i32] } i32:{ *:[i32] }:$src0, (xor:{ *:[i32] } i32:{ *:[i32] }:$src1, -1:{ *:[i32] })<<P:Predicate_anonymous_17562>>)<<P:Predicate_anonymous_17615>>  =>  (S_ANDN2_B32:{ *:[i32] }:{ *:[i1] } i32:{ *:[i32] }:$src0, i32:{ *:[i32] }:$src1)
        GIR_BuildMI, /*InsnID*/0, /*Opcode*/GIMT_Encode2(AMDGPU::S_ANDN2_B32),
        GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/0, // DstI[sdst]
        GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/1, // src0
        GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/1, /*OpIdx*/1, // src1
        GIR_SetImplicitDefDead, /*InsnID*/0, /*OpIdx for AMDGPU::SCC*/0,
        GIR_ConstrainSelectedInstOperands, /*InsnID*/0,
        GIR_EraseFromParent, /*InsnID*/0,
        // GIR_Coverage, 66,
        GIR_Done,
      // Label 266: @18411
      GIM_Try, /*On fail goto*//*Label 267*/ GIMT_Encode4(18439), // Rule ID 54 //
        GIM_CheckRegBankForClass, /*MI*/0, /*Op*/0, /*RC*/GIMT_Encode2(AMDGPU::SReg_32RegClassID),
        GIM_CheckCxxInsnPredicate, /*MI*/0, /*FnId*/GIMT_Encode2(GICXXPred_MI_Predicate_anonymous_17615),
        // (and:{ *:[i32] } i32:{ *:[i32] }:$src0, i32:{ *:[i32] }:$src1)<<P:Predicate_anonymous_17615>>  =>  (S_AND_B32:{ *:[i32] }:{ *:[i1] } i32:{ *:[i32] }:$src0, i32:{ *:[i32] }:$src1)
        GIR_MutateOpcode, /*InsnID*/0, /*RecycleInsnID*/0, /*Opcode*/GIMT_Encode2(AMDGPU::S_AND_B32),
        GIR_AddImplicitDef, /*InsnID*/0, GIMT_Encode2(AMDGPU::SCC), GIMT_Encode2(RegState::Dead),
        GIR_ConstrainSelectedInstOperands, /*InsnID*/0,
        // GIR_Coverage, 54,
        GIR_Done,
      // Label 267: @18439
      GIM_Try, /*On fail goto*//*Label 268*/ GIMT_Encode4(18461), // Rule ID 753 //
        GIM_CheckRegBankForClass, /*MI*/0, /*Op*/0, /*RC*/GIMT_Encode2(AMDGPU::VGPR_32RegClassID),
        // (and:{ *:[i32] } i32:{ *:[i32] }:$src0, i32:{ *:[i32] }:$src1)  =>  (V_AND_B32_e64:{ *:[i32] } i32:{ *:[i32] }:$src0, i32:{ *:[i32] }:$src1)
        GIR_MutateOpcode, /*InsnID*/0, /*RecycleInsnID*/0, /*Opcode*/GIMT_Encode2(AMDGPU::V_AND_B32_e64),
        GIR_AddImplicitUse, /*InsnID*/0, GIMT_Encode2(AMDGPU::EXEC),
        GIR_ConstrainSelectedInstOperands, /*InsnID*/0,
        // GIR_Coverage, 753,
        GIR_Done,
      // Label 268: @18461
      GIM_Reject,
    // Label 264: @18462
    GIM_Reject,
    // Label 251: @18463
    GIM_Try, /*On fail goto*//*Label 269*/ GIMT_Encode4(18615),
      GIM_CheckType, /*MI*/0, /*Op*/1, /*Type*/GILLT_s64,
      GIM_CheckType, /*MI*/0, /*Op*/2, /*Type*/GILLT_s64,
      GIM_CheckCxxInsnPredicate, /*MI*/0, /*FnId*/GIMT_Encode2(GICXXPred_MI_Predicate_anonymous_17615),
      GIM_CheckRegBankForClass, /*MI*/0, /*Op*/0, /*RC*/GIMT_Encode2(AMDGPU::SReg_64RegClassID),
      GIM_Try, /*On fail goto*//*Label 270*/ GIMT_Encode4(18540), // Rule ID 7117 //
        GIM_RecordInsn, /*DefineMI*/1, /*MI*/0, /*OpIdx*/1, // MIs[1]
        GIM_CheckOpcode, /*MI*/1, GIMT_Encode2(TargetOpcode::G_XOR),
        GIM_CheckType, /*MI*/1, /*Op*/1, /*Type*/GILLT_s64,
        GIM_CheckType, /*MI*/1, /*Op*/2, /*Type*/GILLT_s64,
        GIM_CheckConstantInt8, /*MI*/1, /*Op*/2, uint8_t(-1),
        GIM_CheckCxxInsnPredicate, /*MI*/1, /*FnId*/GIMT_Encode2(GICXXPred_MI_Predicate_anonymous_17562),
        GIM_CheckIsSafeToFold, /*InsnID*/1,
        // (and:{ *:[i64] } (xor:{ *:[i64] } i64:{ *:[i64] }:$src1, -1:{ *:[i64] })<<P:Predicate_anonymous_17562>>, i64:{ *:[i64] }:$src0)<<P:Predicate_anonymous_17615>>  =>  (S_ANDN2_B64:{ *:[i64] }:{ *:[i1] } i64:{ *:[i64] }:$src0, i64:{ *:[i64] }:$src1)
        GIR_BuildMI, /*InsnID*/0, /*Opcode*/GIMT_Encode2(AMDGPU::S_ANDN2_B64),
        GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/0, // DstI[sdst]
        GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/2, // src0
        GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/1, /*OpIdx*/1, // src1
        GIR_SetImplicitDefDead, /*InsnID*/0, /*OpIdx for AMDGPU::SCC*/0,
        GIR_ConstrainSelectedInstOperands, /*InsnID*/0,
        GIR_EraseFromParent, /*InsnID*/0,
        // GIR_Coverage, 7117,
        GIR_Done,
      // Label 270: @18540
      GIM_Try, /*On fail goto*//*Label 271*/ GIMT_Encode4(18595), // Rule ID 67 //
        GIM_RecordInsn, /*DefineMI*/1, /*MI*/0, /*OpIdx*/2, // MIs[1]
        GIM_CheckOpcode, /*MI*/1, GIMT_Encode2(TargetOpcode::G_XOR),
        GIM_CheckType, /*MI*/1, /*Op*/1, /*Type*/GILLT_s64,
        GIM_CheckType, /*MI*/1, /*Op*/2, /*Type*/GILLT_s64,
        GIM_CheckConstantInt8, /*MI*/1, /*Op*/2, uint8_t(-1),
        GIM_CheckCxxInsnPredicate, /*MI*/1, /*FnId*/GIMT_Encode2(GICXXPred_MI_Predicate_anonymous_17562),
        GIM_CheckIsSafeToFold, /*InsnID*/1,
        // (and:{ *:[i64] } i64:{ *:[i64] }:$src0, (xor:{ *:[i64] } i64:{ *:[i64] }:$src1, -1:{ *:[i64] })<<P:Predicate_anonymous_17562>>)<<P:Predicate_anonymous_17615>>  =>  (S_ANDN2_B64:{ *:[i64] }:{ *:[i1] } i64:{ *:[i64] }:$src0, i64:{ *:[i64] }:$src1)
        GIR_BuildMI, /*InsnID*/0, /*Opcode*/GIMT_Encode2(AMDGPU::S_ANDN2_B64),
        GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/0, // DstI[sdst]
        GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/1, // src0
        GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/1, /*OpIdx*/1, // src1
        GIR_SetImplicitDefDead, /*InsnID*/0, /*OpIdx for AMDGPU::SCC*/0,
        GIR_ConstrainSelectedInstOperands, /*InsnID*/0,
        GIR_EraseFromParent, /*InsnID*/0,
        // GIR_Coverage, 67,
        GIR_Done,
      // Label 271: @18595
      GIM_Try, /*On fail goto*//*Label 272*/ GIMT_Encode4(18614), // Rule ID 55 //
        // (and:{ *:[i64] } i64:{ *:[i64] }:$src0, i64:{ *:[i64] }:$src1)<<P:Predicate_anonymous_17615>>  =>  (S_AND_B64:{ *:[i64] }:{ *:[i1] } i64:{ *:[i64] }:$src0, i64:{ *:[i64] }:$src1)
        GIR_MutateOpcode, /*InsnID*/0, /*RecycleInsnID*/0, /*Opcode*/GIMT_Encode2(AMDGPU::S_AND_B64),
        GIR_AddImplicitDef, /*InsnID*/0, GIMT_Encode2(AMDGPU::SCC), GIMT_Encode2(RegState::Dead),
        GIR_ConstrainSelectedInstOperands, /*InsnID*/0,
        // GIR_Coverage, 55,
        GIR_Done,
      // Label 272: @18614
      GIM_Reject,
    // Label 269: @18615
    GIM_Reject,
    // Label 252: @18616
    GIM_Try, /*On fail goto*//*Label 273*/ GIMT_Encode4(18800),
      GIM_CheckType, /*MI*/0, /*Op*/1, /*Type*/GILLT_v2s16,
      GIM_CheckType, /*MI*/0, /*Op*/2, /*Type*/GILLT_v2s16,
      GIM_Try, /*On fail goto*//*Label 274*/ GIMT_Encode4(18703), // Rule ID 7197 //
        GIM_CheckRegBankForClass, /*MI*/0, /*Op*/0, /*RC*/GIMT_Encode2(AMDGPU::SReg_32RegClassID),
        GIM_RecordInsn, /*DefineMI*/1, /*MI*/0, /*OpIdx*/1, // MIs[1]
        GIM_CheckOpcode, /*MI*/1, GIMT_Encode2(TargetOpcode::G_XOR),
        GIM_CheckType, /*MI*/1, /*Op*/1, /*Type*/GILLT_v2s16,
        GIM_CheckType, /*MI*/1, /*Op*/2, /*Type*/GILLT_v2s16,
        GIM_RecordInsn, /*DefineMI*/2, /*MI*/1, /*OpIdx*/2, // MIs[2]
        GIM_CheckOpcodeIsEither, /*MI*/2, GIMT_Encode2(TargetOpcode::G_BUILD_VECTOR), GIMT_Encode2(TargetOpcode::G_BUILD_VECTOR_TRUNC),
        GIM_CheckIsBuildVectorAllOnes, /*MI*/2,
        GIM_CheckCxxInsnPredicate, /*MI*/1, /*FnId*/GIMT_Encode2(GICXXPred_MI_Predicate_anonymous_17683),
        GIM_CheckCxxInsnPredicate, /*MI*/0, /*FnId*/GIMT_Encode2(GICXXPred_MI_Predicate_anonymous_17615),
        GIM_CheckIsSafeToFold, /*InsnID*/1,
        GIM_CheckIsSafeToFold, /*InsnID*/2,
        // (and:{ *:[v2i16] } (xor:{ *:[v2i16] } v2i16:{ *:[v2i16] }:$src1, immAllOnesV:{ *:[v2i16] })<<P:Predicate_anonymous_17683>>, v2i16:{ *:[v2i16] }:$src0)<<P:Predicate_anonymous_17615>>  =>  (S_ANDN2_B32:{ *:[v2i16] }:{ *:[i1] } SSrc_b32:{ *:[v2i16] }:$src0, SSrc_b32:{ *:[v2i16] }:$src1)
        GIR_BuildMI, /*InsnID*/0, /*Opcode*/GIMT_Encode2(AMDGPU::S_ANDN2_B32),
        GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/0, // DstI[sdst]
        GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/2, // src0
        GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/1, /*OpIdx*/1, // src1
        GIR_SetImplicitDefDead, /*InsnID*/0, /*OpIdx for AMDGPU::SCC*/0,
        GIR_ConstrainSelectedInstOperands, /*InsnID*/0,
        GIR_EraseFromParent, /*InsnID*/0,
        // GIR_Coverage, 7197,
        GIR_Done,
      // Label 274: @18703
      GIM_Try, /*On fail goto*//*Label 275*/ GIMT_Encode4(18777), // Rule ID 1659 //
        GIM_CheckRegBankForClass, /*MI*/0, /*Op*/0, /*RC*/GIMT_Encode2(AMDGPU::SReg_32RegClassID),
        GIM_RecordInsn, /*DefineMI*/1, /*MI*/0, /*OpIdx*/2, // MIs[1]
        GIM_CheckOpcode, /*MI*/1, GIMT_Encode2(TargetOpcode::G_XOR),
        GIM_CheckType, /*MI*/1, /*Op*/1, /*Type*/GILLT_v2s16,
        GIM_CheckType, /*MI*/1, /*Op*/2, /*Type*/GILLT_v2s16,
        GIM_RecordInsn, /*DefineMI*/2, /*MI*/1, /*OpIdx*/2, // MIs[2]
        GIM_CheckOpcodeIsEither, /*MI*/2, GIMT_Encode2(TargetOpcode::G_BUILD_VECTOR), GIMT_Encode2(TargetOpcode::G_BUILD_VECTOR_TRUNC),
        GIM_CheckIsBuildVectorAllOnes, /*MI*/2,
        GIM_CheckCxxInsnPredicate, /*MI*/1, /*FnId*/GIMT_Encode2(GICXXPred_MI_Predicate_anonymous_17683),
        GIM_CheckCxxInsnPredicate, /*MI*/0, /*FnId*/GIMT_Encode2(GICXXPred_MI_Predicate_anonymous_17615),
        GIM_CheckIsSafeToFold, /*InsnID*/1,
        GIM_CheckIsSafeToFold, /*InsnID*/2,
        // (and:{ *:[v2i16] } v2i16:{ *:[v2i16] }:$src0, (xor:{ *:[v2i16] } v2i16:{ *:[v2i16] }:$src1, immAllOnesV:{ *:[v2i16] })<<P:Predicate_anonymous_17683>>)<<P:Predicate_anonymous_17615>>  =>  (S_ANDN2_B32:{ *:[v2i16] }:{ *:[i1] } SSrc_b32:{ *:[v2i16] }:$src0, SSrc_b32:{ *:[v2i16] }:$src1)
        GIR_BuildMI, /*InsnID*/0, /*Opcode*/GIMT_Encode2(AMDGPU::S_ANDN2_B32),
        GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/0, // DstI[sdst]
        GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/1, // src0
        GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/1, /*OpIdx*/1, // src1
        GIR_SetImplicitDefDead, /*InsnID*/0, /*OpIdx for AMDGPU::SCC*/0,
        GIR_ConstrainSelectedInstOperands, /*InsnID*/0,
        GIR_EraseFromParent, /*InsnID*/0,
        // GIR_Coverage, 1659,
        GIR_Done,
      // Label 275: @18777
      GIM_Try, /*On fail goto*//*Label 276*/ GIMT_Encode4(18799), // Rule ID 2129 //
        GIM_CheckRegBankForClass, /*MI*/0, /*Op*/0, /*RC*/GIMT_Encode2(AMDGPU::VGPR_32RegClassID),
        // (and:{ *:[v2i16] } v2i16:{ *:[v2i16] }:$src0, v2i16:{ *:[v2i16] }:$src1)  =>  (V_AND_B32_e64:{ *:[v2i16] } VSrc_b32:{ *:[v2i16] }:$src0, VSrc_b32:{ *:[v2i16] }:$src1)
        GIR_MutateOpcode, /*InsnID*/0, /*RecycleInsnID*/0, /*Opcode*/GIMT_Encode2(AMDGPU::V_AND_B32_e64),
        GIR_AddImplicitUse, /*InsnID*/0, GIMT_Encode2(AMDGPU::EXEC),
        GIR_ConstrainSelectedInstOperands, /*InsnID*/0,
        // GIR_Coverage, 2129,
        GIR_Done,
      // Label 276: @18799
      GIM_Reject,
    // Label 273: @18800
    GIM_Reject,
    // Label 253: @18801
    GIM_Try, /*On fail goto*//*Label 277*/ GIMT_Encode4(18954),
      GIM_CheckType, /*MI*/0, /*Op*/1, /*Type*/GILLT_v2s32,
      GIM_CheckType, /*MI*/0, /*Op*/2, /*Type*/GILLT_v2s32,
      GIM_CheckCxxInsnPredicate, /*MI*/0, /*FnId*/GIMT_Encode2(GICXXPred_MI_Predicate_anonymous_17615),
      GIM_CheckRegBankForClass, /*MI*/0, /*Op*/0, /*RC*/GIMT_Encode2(AMDGPU::SReg_64RegClassID),
      GIM_Try, /*On fail goto*//*Label 278*/ GIMT_Encode4(18888), // Rule ID 7199 //
        GIM_RecordInsn, /*DefineMI*/1, /*MI*/0, /*OpIdx*/1, // MIs[1]
        GIM_CheckOpcode, /*MI*/1, GIMT_Encode2(TargetOpcode::G_XOR),
        GIM_CheckType, /*MI*/1, /*Op*/1, /*Type*/GILLT_v2s32,
        GIM_CheckType, /*MI*/1, /*Op*/2, /*Type*/GILLT_v2s32,
        GIM_RecordInsn, /*DefineMI*/2, /*MI*/1, /*OpIdx*/2, // MIs[2]
        GIM_CheckOpcodeIsEither, /*MI*/2, GIMT_Encode2(TargetOpcode::G_BUILD_VECTOR), GIMT_Encode2(TargetOpcode::G_BUILD_VECTOR_TRUNC),
        GIM_CheckIsBuildVectorAllOnes, /*MI*/2,
        GIM_CheckCxxInsnPredicate, /*MI*/1, /*FnId*/GIMT_Encode2(GICXXPred_MI_Predicate_anonymous_17683),
        GIM_CheckIsSafeToFold, /*InsnID*/1,
        GIM_CheckIsSafeToFold, /*InsnID*/2,
        // (and:{ *:[v2i32] } (xor:{ *:[v2i32] } v2i32:{ *:[v2i32] }:$src1, immAllOnesV:{ *:[v2i32] })<<P:Predicate_anonymous_17683>>, v2i32:{ *:[v2i32] }:$src0)<<P:Predicate_anonymous_17615>>  =>  (S_ANDN2_B64:{ *:[v2i32] }:{ *:[i1] } SSrc_b64:{ *:[v2i32] }:$src0, SSrc_b64:{ *:[v2i32] }:$src1)
        GIR_BuildMI, /*InsnID*/0, /*Opcode*/GIMT_Encode2(AMDGPU::S_ANDN2_B64),
        GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/0, // DstI[sdst]
        GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/2, // src0
        GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/1, /*OpIdx*/1, // src1
        GIR_SetImplicitDefDead, /*InsnID*/0, /*OpIdx for AMDGPU::SCC*/0,
        GIR_ConstrainSelectedInstOperands, /*InsnID*/0,
        GIR_EraseFromParent, /*InsnID*/0,
        // GIR_Coverage, 7199,
        GIR_Done,
      // Label 278: @18888
      GIM_Try, /*On fail goto*//*Label 279*/ GIMT_Encode4(18953), // Rule ID 1661 //
        GIM_RecordInsn, /*DefineMI*/1, /*MI*/0, /*OpIdx*/2, // MIs[1]
        GIM_CheckOpcode, /*MI*/1, GIMT_Encode2(TargetOpcode::G_XOR),
        GIM_CheckType, /*MI*/1, /*Op*/1, /*Type*/GILLT_v2s32,
        GIM_CheckType, /*MI*/1, /*Op*/2, /*Type*/GILLT_v2s32,
        GIM_RecordInsn, /*DefineMI*/2, /*MI*/1, /*OpIdx*/2, // MIs[2]
        GIM_CheckOpcodeIsEither, /*MI*/2, GIMT_Encode2(TargetOpcode::G_BUILD_VECTOR), GIMT_Encode2(TargetOpcode::G_BUILD_VECTOR_TRUNC),
        GIM_CheckIsBuildVectorAllOnes, /*MI*/2,
        GIM_CheckCxxInsnPredicate, /*MI*/1, /*FnId*/GIMT_Encode2(GICXXPred_MI_Predicate_anonymous_17683),
        GIM_CheckIsSafeToFold, /*InsnID*/1,
        GIM_CheckIsSafeToFold, /*InsnID*/2,
        // (and:{ *:[v2i32] } v2i32:{ *:[v2i32] }:$src0, (xor:{ *:[v2i32] } v2i32:{ *:[v2i32] }:$src1, immAllOnesV:{ *:[v2i32] })<<P:Predicate_anonymous_17683>>)<<P:Predicate_anonymous_17615>>  =>  (S_ANDN2_B64:{ *:[v2i32] }:{ *:[i1] } SSrc_b64:{ *:[v2i32] }:$src0, SSrc_b64:{ *:[v2i32] }:$src1)
        GIR_BuildMI, /*InsnID*/0, /*Opcode*/GIMT_Encode2(AMDGPU::S_ANDN2_B64),
        GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/0, // DstI[sdst]
        GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/1, // src0
        GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/1, /*OpIdx*/1, // src1
        GIR_SetImplicitDefDead, /*InsnID*/0, /*OpIdx for AMDGPU::SCC*/0,
        GIR_ConstrainSelectedInstOperands, /*InsnID*/0,
        GIR_EraseFromParent, /*InsnID*/0,
        // GIR_Coverage, 1661,
        GIR_Done,
      // Label 279: @18953
      GIM_Reject,
    // Label 277: @18954
    GIM_Reject,
    // Label 254: @18955
    GIM_Try, /*On fail goto*//*Label 280*/ GIMT_Encode4(19108),
      GIM_CheckType, /*MI*/0, /*Op*/1, /*Type*/GILLT_v4s16,
      GIM_CheckType, /*MI*/0, /*Op*/2, /*Type*/GILLT_v4s16,
      GIM_CheckCxxInsnPredicate, /*MI*/0, /*FnId*/GIMT_Encode2(GICXXPred_MI_Predicate_anonymous_17615),
      GIM_CheckRegBankForClass, /*MI*/0, /*Op*/0, /*RC*/GIMT_Encode2(AMDGPU::SReg_64RegClassID),
      GIM_Try, /*On fail goto*//*Label 281*/ GIMT_Encode4(19042), // Rule ID 7198 //
        GIM_RecordInsn, /*DefineMI*/1, /*MI*/0, /*OpIdx*/1, // MIs[1]
        GIM_CheckOpcode, /*MI*/1, GIMT_Encode2(TargetOpcode::G_XOR),
        GIM_CheckType, /*MI*/1, /*Op*/1, /*Type*/GILLT_v4s16,
        GIM_CheckType, /*MI*/1, /*Op*/2, /*Type*/GILLT_v4s16,
        GIM_RecordInsn, /*DefineMI*/2, /*MI*/1, /*OpIdx*/2, // MIs[2]
        GIM_CheckOpcodeIsEither, /*MI*/2, GIMT_Encode2(TargetOpcode::G_BUILD_VECTOR), GIMT_Encode2(TargetOpcode::G_BUILD_VECTOR_TRUNC),
        GIM_CheckIsBuildVectorAllOnes, /*MI*/2,
        GIM_CheckCxxInsnPredicate, /*MI*/1, /*FnId*/GIMT_Encode2(GICXXPred_MI_Predicate_anonymous_17683),
        GIM_CheckIsSafeToFold, /*InsnID*/1,
        GIM_CheckIsSafeToFold, /*InsnID*/2,
        // (and:{ *:[v4i16] } (xor:{ *:[v4i16] } v4i16:{ *:[v4i16] }:$src1, immAllOnesV:{ *:[v4i16] })<<P:Predicate_anonymous_17683>>, v4i16:{ *:[v4i16] }:$src0)<<P:Predicate_anonymous_17615>>  =>  (S_ANDN2_B64:{ *:[v4i16] }:{ *:[i1] } SSrc_b64:{ *:[v4i16] }:$src0, SSrc_b64:{ *:[v4i16] }:$src1)
        GIR_BuildMI, /*InsnID*/0, /*Opcode*/GIMT_Encode2(AMDGPU::S_ANDN2_B64),
        GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/0, // DstI[sdst]
        GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/2, // src0
        GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/1, /*OpIdx*/1, // src1
        GIR_SetImplicitDefDead, /*InsnID*/0, /*OpIdx for AMDGPU::SCC*/0,
        GIR_ConstrainSelectedInstOperands, /*InsnID*/0,
        GIR_EraseFromParent, /*InsnID*/0,
        // GIR_Coverage, 7198,
        GIR_Done,
      // Label 281: @19042
      GIM_Try, /*On fail goto*//*Label 282*/ GIMT_Encode4(19107), // Rule ID 1660 //
        GIM_RecordInsn, /*DefineMI*/1, /*MI*/0, /*OpIdx*/2, // MIs[1]
        GIM_CheckOpcode, /*MI*/1, GIMT_Encode2(TargetOpcode::G_XOR),
        GIM_CheckType, /*MI*/1, /*Op*/1, /*Type*/GILLT_v4s16,
        GIM_CheckType, /*MI*/1, /*Op*/2, /*Type*/GILLT_v4s16,
        GIM_RecordInsn, /*DefineMI*/2, /*MI*/1, /*OpIdx*/2, // MIs[2]
        GIM_CheckOpcodeIsEither, /*MI*/2, GIMT_Encode2(TargetOpcode::G_BUILD_VECTOR), GIMT_Encode2(TargetOpcode::G_BUILD_VECTOR_TRUNC),
        GIM_CheckIsBuildVectorAllOnes, /*MI*/2,
        GIM_CheckCxxInsnPredicate, /*MI*/1, /*FnId*/GIMT_Encode2(GICXXPred_MI_Predicate_anonymous_17683),
        GIM_CheckIsSafeToFold, /*InsnID*/1,
        GIM_CheckIsSafeToFold, /*InsnID*/2,
        // (and:{ *:[v4i16] } v4i16:{ *:[v4i16] }:$src0, (xor:{ *:[v4i16] } v4i16:{ *:[v4i16] }:$src1, immAllOnesV:{ *:[v4i16] })<<P:Predicate_anonymous_17683>>)<<P:Predicate_anonymous_17615>>  =>  (S_ANDN2_B64:{ *:[v4i16] }:{ *:[i1] } SSrc_b64:{ *:[v4i16] }:$src0, SSrc_b64:{ *:[v4i16] }:$src1)
        GIR_BuildMI, /*InsnID*/0, /*Opcode*/GIMT_Encode2(AMDGPU::S_ANDN2_B64),
        GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/0, // DstI[sdst]
        GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/1, // src0
        GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/1, /*OpIdx*/1, // src1
        GIR_SetImplicitDefDead, /*InsnID*/0, /*OpIdx for AMDGPU::SCC*/0,
        GIR_ConstrainSelectedInstOperands, /*InsnID*/0,
        GIR_EraseFromParent, /*InsnID*/0,
        // GIR_Coverage, 1660,
        GIR_Done,
      // Label 282: @19107
      GIM_Reject,
    // Label 280: @19108
    GIM_Reject,
    // Label 255: @19109
    GIM_Reject,
    // Label 4: @19110
    GIM_SwitchType, /*MI*/0, /*Op*/0, /*[*/GIMT_Encode2(7), GIMT_Encode2(17), /*)*//*default:*//*Label 290*/ GIMT_Encode4(34373),
    /*GILLT_s1*//*Label 283*/ GIMT_Encode4(19161),
    /*GILLT_s16*//*Label 284*/ GIMT_Encode4(19230),
    /*GILLT_s32*//*Label 285*/ GIMT_Encode4(19420),
    /*GILLT_s64*//*Label 286*/ GIMT_Encode4(24421),
    /*GILLT_v2s16*//*Label 287*/ GIMT_Encode4(33880),
    /*GILLT_v2s32*//*Label 288*/ GIMT_Encode4(34065), GIMT_Encode4(0), GIMT_Encode4(0), GIMT_Encode4(0),
    /*GILLT_v4s16*//*Label 289*/ GIMT_Encode4(34219),
    // Label 283: @19161
    GIM_Try, /*On fail goto*//*Label 291*/ GIMT_Encode4(19229),
      GIM_CheckType, /*MI*/0, /*Op*/1, /*Type*/GILLT_s1,
      GIM_CheckType, /*MI*/0, /*Op*/2, /*Type*/GILLT_s1,
      GIM_Try, /*On fail goto*//*Label 292*/ GIMT_Encode4(19201), // Rule ID 6355 //
        GIM_CheckFeatures, GIMT_Encode2(GIFBS_isWave64),
        GIM_CheckRegBankForClass, /*MI*/0, /*Op*/0, /*RC*/GIMT_Encode2(AMDGPU::SReg_64RegClassID),
        // (or:{ *:[i1] } i1:{ *:[i1] }:$src0, i1:{ *:[i1] }:$src1)  =>  (S_OR_B64:{ *:[i1] }:{ *:[i1] } ?:{ *:[i1] }:$src0, ?:{ *:[i1] }:$src1)
        GIR_MutateOpcode, /*InsnID*/0, /*RecycleInsnID*/0, /*Opcode*/GIMT_Encode2(AMDGPU::S_OR_B64),
        GIR_AddImplicitDef, /*InsnID*/0, GIMT_Encode2(AMDGPU::SCC), GIMT_Encode2(RegState::Dead),
        GIR_ConstrainSelectedInstOperands, /*InsnID*/0,
        // GIR_Coverage, 6355,
        GIR_Done,
      // Label 292: @19201
      GIM_Try, /*On fail goto*//*Label 293*/ GIMT_Encode4(19228), // Rule ID 6362 //
        GIM_CheckFeatures, GIMT_Encode2(GIFBS_isWave32),
        GIM_CheckRegBankForClass, /*MI*/0, /*Op*/0, /*RC*/GIMT_Encode2(AMDGPU::SReg_32RegClassID),
        // (or:{ *:[i1] } i1:{ *:[i1] }:$src0, i1:{ *:[i1] }:$src1)  =>  (S_OR_B32:{ *:[i1] }:{ *:[i1] } ?:{ *:[i1] }:$src0, ?:{ *:[i1] }:$src1)
        GIR_MutateOpcode, /*InsnID*/0, /*RecycleInsnID*/0, /*Opcode*/GIMT_Encode2(AMDGPU::S_OR_B32),
        GIR_AddImplicitDef, /*InsnID*/0, GIMT_Encode2(AMDGPU::SCC), GIMT_Encode2(RegState::Dead),
        GIR_ConstrainSelectedInstOperands, /*InsnID*/0,
        // GIR_Coverage, 6362,
        GIR_Done,
      // Label 293: @19228
      GIM_Reject,
    // Label 291: @19229
    GIM_Reject,
    // Label 284: @19230
    GIM_Try, /*On fail goto*//*Label 294*/ GIMT_Encode4(19419),
      GIM_CheckType, /*MI*/0, /*Op*/1, /*Type*/GILLT_s16,
      GIM_CheckType, /*MI*/0, /*Op*/2, /*Type*/GILLT_s16,
      GIM_Try, /*On fail goto*//*Label 295*/ GIMT_Encode4(19307), // Rule ID 7200 //
        GIM_CheckRegBankForClass, /*MI*/0, /*Op*/0, /*RC*/GIMT_Encode2(AMDGPU::SReg_32RegClassID),
        GIM_RecordInsn, /*DefineMI*/1, /*MI*/0, /*OpIdx*/1, // MIs[1]
        GIM_CheckOpcode, /*MI*/1, GIMT_Encode2(TargetOpcode::G_XOR),
        GIM_CheckType, /*MI*/1, /*Op*/1, /*Type*/GILLT_s16,
        GIM_CheckType, /*MI*/1, /*Op*/2, /*Type*/GILLT_s16,
        GIM_CheckConstantInt8, /*MI*/1, /*Op*/2, uint8_t(-1),
        GIM_CheckCxxInsnPredicate, /*MI*/1, /*FnId*/GIMT_Encode2(GICXXPred_MI_Predicate_anonymous_17562),
        GIM_CheckCxxInsnPredicate, /*MI*/0, /*FnId*/GIMT_Encode2(GICXXPred_MI_Predicate_anonymous_17616),
        GIM_CheckIsSafeToFold, /*InsnID*/1,
        // (or:{ *:[i16] } (xor:{ *:[i16] } i16:{ *:[i16] }:$src1, -1:{ *:[i16] })<<P:Predicate_anonymous_17562>>, i16:{ *:[i16] }:$src0)<<P:Predicate_anonymous_17616>>  =>  (S_ORN2_B32:{ *:[i16] }:{ *:[i1] } SSrc_b32:{ *:[i16] }:$src0, SSrc_b32:{ *:[i16] }:$src1)
        GIR_BuildMI, /*InsnID*/0, /*Opcode*/GIMT_Encode2(AMDGPU::S_ORN2_B32),
        GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/0, // DstI[sdst]
        GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/2, // src0
        GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/1, /*OpIdx*/1, // src1
        GIR_SetImplicitDefDead, /*InsnID*/0, /*OpIdx for AMDGPU::SCC*/0,
        GIR_ConstrainSelectedInstOperands, /*InsnID*/0,
        GIR_EraseFromParent, /*InsnID*/0,
        // GIR_Coverage, 7200,
        GIR_Done,
      // Label 295: @19307
      GIM_Try, /*On fail goto*//*Label 296*/ GIMT_Encode4(19371), // Rule ID 1662 //
        GIM_CheckRegBankForClass, /*MI*/0, /*Op*/0, /*RC*/GIMT_Encode2(AMDGPU::SReg_32RegClassID),
        GIM_RecordInsn, /*DefineMI*/1, /*MI*/0, /*OpIdx*/2, // MIs[1]
        GIM_CheckOpcode, /*MI*/1, GIMT_Encode2(TargetOpcode::G_XOR),
        GIM_CheckType, /*MI*/1, /*Op*/1, /*Type*/GILLT_s16,
        GIM_CheckType, /*MI*/1, /*Op*/2, /*Type*/GILLT_s16,
        GIM_CheckConstantInt8, /*MI*/1, /*Op*/2, uint8_t(-1),
        GIM_CheckCxxInsnPredicate, /*MI*/1, /*FnId*/GIMT_Encode2(GICXXPred_MI_Predicate_anonymous_17562),
        GIM_CheckCxxInsnPredicate, /*MI*/0, /*FnId*/GIMT_Encode2(GICXXPred_MI_Predicate_anonymous_17616),
        GIM_CheckIsSafeToFold, /*InsnID*/1,
        // (or:{ *:[i16] } i16:{ *:[i16] }:$src0, (xor:{ *:[i16] } i16:{ *:[i16] }:$src1, -1:{ *:[i16] })<<P:Predicate_anonymous_17562>>)<<P:Predicate_anonymous_17616>>  =>  (S_ORN2_B32:{ *:[i16] }:{ *:[i1] } SSrc_b32:{ *:[i16] }:$src0, SSrc_b32:{ *:[i16] }:$src1)
        GIR_BuildMI, /*InsnID*/0, /*Opcode*/GIMT_Encode2(AMDGPU::S_ORN2_B32),
        GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/0, // DstI[sdst]
        GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/1, // src0
        GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/1, /*OpIdx*/1, // src1
        GIR_SetImplicitDefDead, /*InsnID*/0, /*OpIdx for AMDGPU::SCC*/0,
        GIR_ConstrainSelectedInstOperands, /*InsnID*/0,
        GIR_EraseFromParent, /*InsnID*/0,
        // GIR_Coverage, 1662,
        GIR_Done,
      // Label 296: @19371
      GIM_Try, /*On fail goto*//*Label 297*/ GIMT_Encode4(19393), // Rule ID 2127 //
        GIM_CheckRegBankForClass, /*MI*/0, /*Op*/0, /*RC*/GIMT_Encode2(AMDGPU::VGPR_32RegClassID),
        // (or:{ *:[i16] } i16:{ *:[i16] }:$src0, i16:{ *:[i16] }:$src1)  =>  (V_OR_B32_e64:{ *:[i16] } VSrc_b32:{ *:[i16] }:$src0, VSrc_b32:{ *:[i16] }:$src1)
        GIR_MutateOpcode, /*InsnID*/0, /*RecycleInsnID*/0, /*Opcode*/GIMT_Encode2(AMDGPU::V_OR_B32_e64),
        GIR_AddImplicitUse, /*InsnID*/0, GIMT_Encode2(AMDGPU::EXEC),
        GIR_ConstrainSelectedInstOperands, /*InsnID*/0,
        // GIR_Coverage, 2127,
        GIR_Done,
      // Label 297: @19393
      GIM_Try, /*On fail goto*//*Label 298*/ GIMT_Encode4(19418), // Rule ID 834 //
        GIM_CheckFeatures, GIMT_Encode2(GIFBS_isGFX11Plus),
        GIM_CheckRegBankForClass, /*MI*/0, /*Op*/0, /*RC*/GIMT_Encode2(AMDGPU::VGPR_32RegClassID),
        // (or:{ *:[i16] } i16:{ *:[i16] }:$src0, i16:{ *:[i16] }:$src1)  =>  (V_OR_B16_t16_e64:{ *:[i16] } i16:{ *:[i16] }:$src0, i16:{ *:[i16] }:$src1)
        GIR_MutateOpcode, /*InsnID*/0, /*RecycleInsnID*/0, /*Opcode*/GIMT_Encode2(AMDGPU::V_OR_B16_t16_e64),
        GIR_AddImplicitUse, /*InsnID*/0, GIMT_Encode2(AMDGPU::EXEC),
        GIR_ConstrainSelectedInstOperands, /*InsnID*/0,
        // GIR_Coverage, 834,
        GIR_Done,
      // Label 298: @19418
      GIM_Reject,
    // Label 294: @19419
    GIM_Reject,
    // Label 285: @19420
    GIM_Try, /*On fail goto*//*Label 299*/ GIMT_Encode4(24420),
      GIM_CheckType, /*MI*/0, /*Op*/1, /*Type*/GILLT_s32,
      GIM_CheckType, /*MI*/0, /*Op*/2, /*Type*/GILLT_s32,
      GIM_Try, /*On fail goto*//*Label 300*/ GIMT_Encode4(19582), // Rule ID 9876 //
        GIM_CheckRegBankForClass, /*MI*/0, /*Op*/0, /*RC*/GIMT_Encode2(AMDGPU::VGPR_32RegClassID),
        GIM_RecordInsnIgnoreCopies, /*DefineMI*/1, /*MI*/0, /*OpIdx*/1, // MIs[1]
        GIM_CheckOpcode, /*MI*/1, GIMT_Encode2(TargetOpcode::G_AND),
        GIM_CheckType, /*MI*/1, /*Op*/1, /*Type*/GILLT_s32,
        GIM_CheckType, /*MI*/1, /*Op*/2, /*Type*/GILLT_s32,
        GIM_RecordInsnIgnoreCopies, /*DefineMI*/2, /*MI*/1, /*OpIdx*/1, // MIs[2]
        GIM_CheckOpcode, /*MI*/2, GIMT_Encode2(TargetOpcode::G_XOR),
        GIM_CheckType, /*MI*/2, /*Op*/1, /*Type*/GILLT_s32,
        GIM_CheckType, /*MI*/2, /*Op*/2, /*Type*/GILLT_s32,
        GIM_CheckConstantInt8, /*MI*/2, /*Op*/2, uint8_t(-1),
        GIM_RecordInsnIgnoreCopies, /*DefineMI*/3, /*MI*/0, /*OpIdx*/2, // MIs[3]
        GIM_CheckOpcode, /*MI*/3, GIMT_Encode2(TargetOpcode::G_AND),
        GIM_CheckType, /*MI*/3, /*Op*/2, /*Type*/GILLT_s32,
        // MIs[3] x
        GIM_CheckIsSameOperandIgnoreCopies, /*MI*/3, /*OpIdx*/1, /*OtherMI*/2, /*OtherOpIdx*/1,
        GIM_CheckCxxInsnPredicate, /*MI*/0, /*FnId*/GIMT_Encode2(GICXXPred_MI_Predicate_anonymous_22557),
        GIM_CheckIsSafeToFold, /*InsnID*/1,
        GIM_CheckIsSafeToFold, /*InsnID*/2,
        GIM_CheckIsSafeToFold, /*InsnID*/3,
        // (or:{ *:[i32] } (and:{ *:[i32] } (xor:{ *:[i32] } i32:{ *:[i32] }:$x, -1:{ *:[i32] }), i32:{ *:[i32] }:$z), (and:{ *:[i32] } i32:{ *:[i32] }:$x, i32:{ *:[i32] }:$y))<<P:Predicate_anonymous_22557>>  =>  (V_BFI_B32_e64:{ *:[i32] } (COPY_TO_REGCLASS:{ *:[i16] } VSrc_b32:{ *:[i32] }:$x, VGPR_32:{ *:[i32] }), (COPY_TO_REGCLASS:{ *:[i16] } VSrc_b32:{ *:[i32] }:$y, VGPR_32:{ *:[i32] }), (COPY_TO_REGCLASS:{ *:[i16] } VSrc_b32:{ *:[i32] }:$z, VGPR_32:{ *:[i32] }))
        GIR_MakeTempReg, /*TempRegID*/0, /*TypeID*/GILLT_s16,
        GIR_MakeTempReg, /*TempRegID*/1, /*TypeID*/GILLT_s16,
        GIR_MakeTempReg, /*TempRegID*/2, /*TypeID*/GILLT_s16,
        GIR_BuildMI, /*InsnID*/3, /*Opcode*/GIMT_Encode2(TargetOpcode::COPY),
        GIR_AddTempRegister, /*InsnID*/3, /*TempRegID*/2, /*TempRegFlags*/GIMT_Encode2(RegState::Define),
        GIR_Copy, /*NewInsnID*/3, /*OldInsnID*/1, /*OpIdx*/2, // z
        GIR_ConstrainSelectedInstOperands, /*InsnID*/3,
        GIR_BuildMI, /*InsnID*/2, /*Opcode*/GIMT_Encode2(TargetOpcode::COPY),
        GIR_AddTempRegister, /*InsnID*/2, /*TempRegID*/1, /*TempRegFlags*/GIMT_Encode2(RegState::Define),
        GIR_Copy, /*NewInsnID*/2, /*OldInsnID*/3, /*OpIdx*/2, // y
        GIR_ConstrainSelectedInstOperands, /*InsnID*/2,
        GIR_BuildMI, /*InsnID*/1, /*Opcode*/GIMT_Encode2(TargetOpcode::COPY),
        GIR_AddTempRegister, /*InsnID*/1, /*TempRegID*/0, /*TempRegFlags*/GIMT_Encode2(RegState::Define),
        GIR_Copy, /*NewInsnID*/1, /*OldInsnID*/2, /*OpIdx*/1, // x
        GIR_ConstrainSelectedInstOperands, /*InsnID*/1,
        GIR_BuildMI, /*InsnID*/0, /*Opcode*/GIMT_Encode2(AMDGPU::V_BFI_B32_e64),
        GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/0, // DstI[vdst]
        GIR_AddSimpleTempRegister, /*InsnID*/0, /*TempRegID*/0,
        GIR_AddSimpleTempRegister, /*InsnID*/0, /*TempRegID*/1,
        GIR_AddSimpleTempRegister, /*InsnID*/0, /*TempRegID*/2,
        GIR_ConstrainSelectedInstOperands, /*InsnID*/0,
        GIR_EraseFromParent, /*InsnID*/0,
        // GIR_Coverage, 9876,
        GIR_Done,
      // Label 300: @19582
      GIM_Try, /*On fail goto*//*Label 301*/ GIMT_Encode4(19731), // Rule ID 9875 //
        GIM_CheckRegBankForClass, /*MI*/0, /*Op*/0, /*RC*/GIMT_Encode2(AMDGPU::VGPR_32RegClassID),
        GIM_RecordInsnIgnoreCopies, /*DefineMI*/1, /*MI*/0, /*OpIdx*/1, // MIs[1]
        GIM_CheckOpcode, /*MI*/1, GIMT_Encode2(TargetOpcode::G_AND),
        GIM_CheckType, /*MI*/1, /*Op*/1, /*Type*/GILLT_s32,
        GIM_CheckType, /*MI*/1, /*Op*/2, /*Type*/GILLT_s32,
        GIM_RecordInsnIgnoreCopies, /*DefineMI*/2, /*MI*/1, /*OpIdx*/1, // MIs[2]
        GIM_CheckOpcode, /*MI*/2, GIMT_Encode2(TargetOpcode::G_XOR),
        GIM_CheckType, /*MI*/2, /*Op*/1, /*Type*/GILLT_s32,
        GIM_CheckType, /*MI*/2, /*Op*/2, /*Type*/GILLT_s32,
        GIM_CheckConstantInt8, /*MI*/2, /*Op*/2, uint8_t(-1),
        GIM_RecordInsnIgnoreCopies, /*DefineMI*/3, /*MI*/0, /*OpIdx*/2, // MIs[3]
        GIM_CheckOpcode, /*MI*/3, GIMT_Encode2(TargetOpcode::G_AND),
        GIM_CheckType, /*MI*/3, /*Op*/1, /*Type*/GILLT_s32,
        // MIs[3] x
        GIM_CheckIsSameOperandIgnoreCopies, /*MI*/3, /*OpIdx*/2, /*OtherMI*/2, /*OtherOpIdx*/1,
        GIM_CheckCxxInsnPredicate, /*MI*/0, /*FnId*/GIMT_Encode2(GICXXPred_MI_Predicate_anonymous_22557),
        GIM_CheckIsSafeToFold, /*InsnID*/1,
        GIM_CheckIsSafeToFold, /*InsnID*/2,
        GIM_CheckIsSafeToFold, /*InsnID*/3,
        // (or:{ *:[i32] } (and:{ *:[i32] } (xor:{ *:[i32] } i32:{ *:[i32] }:$x, -1:{ *:[i32] }), i32:{ *:[i32] }:$z), (and:{ *:[i32] } i32:{ *:[i32] }:$y, i32:{ *:[i32] }:$x))<<P:Predicate_anonymous_22557>>  =>  (V_BFI_B32_e64:{ *:[i32] } (COPY_TO_REGCLASS:{ *:[i16] } VSrc_b32:{ *:[i32] }:$x, VGPR_32:{ *:[i32] }), (COPY_TO_REGCLASS:{ *:[i16] } VSrc_b32:{ *:[i32] }:$y, VGPR_32:{ *:[i32] }), (COPY_TO_REGCLASS:{ *:[i16] } VSrc_b32:{ *:[i32] }:$z, VGPR_32:{ *:[i32] }))
        GIR_MakeTempReg, /*TempRegID*/0, /*TypeID*/GILLT_s16,
        GIR_MakeTempReg, /*TempRegID*/1, /*TypeID*/GILLT_s16,
        GIR_MakeTempReg, /*TempRegID*/2, /*TypeID*/GILLT_s16,
        GIR_BuildMI, /*InsnID*/3, /*Opcode*/GIMT_Encode2(TargetOpcode::COPY),
        GIR_AddTempRegister, /*InsnID*/3, /*TempRegID*/2, /*TempRegFlags*/GIMT_Encode2(RegState::Define),
        GIR_Copy, /*NewInsnID*/3, /*OldInsnID*/1, /*OpIdx*/2, // z
        GIR_ConstrainSelectedInstOperands, /*InsnID*/3,
        GIR_BuildMI, /*InsnID*/2, /*Opcode*/GIMT_Encode2(TargetOpcode::COPY),
        GIR_AddTempRegister, /*InsnID*/2, /*TempRegID*/1, /*TempRegFlags*/GIMT_Encode2(RegState::Define),
        GIR_Copy, /*NewInsnID*/2, /*OldInsnID*/3, /*OpIdx*/1, // y
        GIR_ConstrainSelectedInstOperands, /*InsnID*/2,
        GIR_BuildMI, /*InsnID*/1, /*Opcode*/GIMT_Encode2(TargetOpcode::COPY),
        GIR_AddTempRegister, /*InsnID*/1, /*TempRegID*/0, /*TempRegFlags*/GIMT_Encode2(RegState::Define),
        GIR_Copy, /*NewInsnID*/1, /*OldInsnID*/2, /*OpIdx*/1, // x
        GIR_ConstrainSelectedInstOperands, /*InsnID*/1,
        GIR_BuildMI, /*InsnID*/0, /*Opcode*/GIMT_Encode2(AMDGPU::V_BFI_B32_e64),
        GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/0, // DstI[vdst]
        GIR_AddSimpleTempRegister, /*InsnID*/0, /*TempRegID*/0,
        GIR_AddSimpleTempRegister, /*InsnID*/0, /*TempRegID*/1,
        GIR_AddSimpleTempRegister, /*InsnID*/0, /*TempRegID*/2,
        GIR_ConstrainSelectedInstOperands, /*InsnID*/0,
        GIR_EraseFromParent, /*InsnID*/0,
        // GIR_Coverage, 9875,
        GIR_Done,
      // Label 301: @19731
      GIM_Try, /*On fail goto*//*Label 302*/ GIMT_Encode4(19880), // Rule ID 9874 //
        GIM_CheckRegBankForClass, /*MI*/0, /*Op*/0, /*RC*/GIMT_Encode2(AMDGPU::VGPR_32RegClassID),
        GIM_RecordInsnIgnoreCopies, /*DefineMI*/1, /*MI*/0, /*OpIdx*/1, // MIs[1]
        GIM_CheckOpcode, /*MI*/1, GIMT_Encode2(TargetOpcode::G_AND),
        GIM_CheckType, /*MI*/1, /*Op*/1, /*Type*/GILLT_s32,
        GIM_CheckType, /*MI*/1, /*Op*/2, /*Type*/GILLT_s32,
        GIM_RecordInsnIgnoreCopies, /*DefineMI*/2, /*MI*/1, /*OpIdx*/2, // MIs[2]
        GIM_CheckOpcode, /*MI*/2, GIMT_Encode2(TargetOpcode::G_XOR),
        GIM_CheckType, /*MI*/2, /*Op*/1, /*Type*/GILLT_s32,
        GIM_CheckType, /*MI*/2, /*Op*/2, /*Type*/GILLT_s32,
        GIM_CheckConstantInt8, /*MI*/2, /*Op*/2, uint8_t(-1),
        GIM_RecordInsnIgnoreCopies, /*DefineMI*/3, /*MI*/0, /*OpIdx*/2, // MIs[3]
        GIM_CheckOpcode, /*MI*/3, GIMT_Encode2(TargetOpcode::G_AND),
        GIM_CheckType, /*MI*/3, /*Op*/2, /*Type*/GILLT_s32,
        // MIs[3] x
        GIM_CheckIsSameOperandIgnoreCopies, /*MI*/3, /*OpIdx*/1, /*OtherMI*/2, /*OtherOpIdx*/1,
        GIM_CheckCxxInsnPredicate, /*MI*/0, /*FnId*/GIMT_Encode2(GICXXPred_MI_Predicate_anonymous_22557),
        GIM_CheckIsSafeToFold, /*InsnID*/1,
        GIM_CheckIsSafeToFold, /*InsnID*/2,
        GIM_CheckIsSafeToFold, /*InsnID*/3,
        // (or:{ *:[i32] } (and:{ *:[i32] } i32:{ *:[i32] }:$z, (xor:{ *:[i32] } i32:{ *:[i32] }:$x, -1:{ *:[i32] })), (and:{ *:[i32] } i32:{ *:[i32] }:$x, i32:{ *:[i32] }:$y))<<P:Predicate_anonymous_22557>>  =>  (V_BFI_B32_e64:{ *:[i32] } (COPY_TO_REGCLASS:{ *:[i16] } VSrc_b32:{ *:[i32] }:$x, VGPR_32:{ *:[i32] }), (COPY_TO_REGCLASS:{ *:[i16] } VSrc_b32:{ *:[i32] }:$y, VGPR_32:{ *:[i32] }), (COPY_TO_REGCLASS:{ *:[i16] } VSrc_b32:{ *:[i32] }:$z, VGPR_32:{ *:[i32] }))
        GIR_MakeTempReg, /*TempRegID*/0, /*TypeID*/GILLT_s16,
        GIR_MakeTempReg, /*TempRegID*/1, /*TypeID*/GILLT_s16,
        GIR_MakeTempReg, /*TempRegID*/2, /*TypeID*/GILLT_s16,
        GIR_BuildMI, /*InsnID*/3, /*Opcode*/GIMT_Encode2(TargetOpcode::COPY),
        GIR_AddTempRegister, /*InsnID*/3, /*TempRegID*/2, /*TempRegFlags*/GIMT_Encode2(RegState::Define),
        GIR_Copy, /*NewInsnID*/3, /*OldInsnID*/1, /*OpIdx*/1, // z
        GIR_ConstrainSelectedInstOperands, /*InsnID*/3,
        GIR_BuildMI, /*InsnID*/2, /*Opcode*/GIMT_Encode2(TargetOpcode::COPY),
        GIR_AddTempRegister, /*InsnID*/2, /*TempRegID*/1, /*TempRegFlags*/GIMT_Encode2(RegState::Define),
        GIR_Copy, /*NewInsnID*/2, /*OldInsnID*/3, /*OpIdx*/2, // y
        GIR_ConstrainSelectedInstOperands, /*InsnID*/2,
        GIR_BuildMI, /*InsnID*/1, /*Opcode*/GIMT_Encode2(TargetOpcode::COPY),
        GIR_AddTempRegister, /*InsnID*/1, /*TempRegID*/0, /*TempRegFlags*/GIMT_Encode2(RegState::Define),
        GIR_Copy, /*NewInsnID*/1, /*OldInsnID*/2, /*OpIdx*/1, // x
        GIR_ConstrainSelectedInstOperands, /*InsnID*/1,
        GIR_BuildMI, /*InsnID*/0, /*Opcode*/GIMT_Encode2(AMDGPU::V_BFI_B32_e64),
        GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/0, // DstI[vdst]
        GIR_AddSimpleTempRegister, /*InsnID*/0, /*TempRegID*/0,
        GIR_AddSimpleTempRegister, /*InsnID*/0, /*TempRegID*/1,
        GIR_AddSimpleTempRegister, /*InsnID*/0, /*TempRegID*/2,
        GIR_ConstrainSelectedInstOperands, /*InsnID*/0,
        GIR_EraseFromParent, /*InsnID*/0,
        // GIR_Coverage, 9874,
        GIR_Done,
      // Label 302: @19880
      GIM_Try, /*On fail goto*//*Label 303*/ GIMT_Encode4(20029), // Rule ID 9873 //
        GIM_CheckRegBankForClass, /*MI*/0, /*Op*/0, /*RC*/GIMT_Encode2(AMDGPU::VGPR_32RegClassID),
        GIM_RecordInsnIgnoreCopies, /*DefineMI*/1, /*MI*/0, /*OpIdx*/1, // MIs[1]
        GIM_CheckOpcode, /*MI*/1, GIMT_Encode2(TargetOpcode::G_AND),
        GIM_CheckType, /*MI*/1, /*Op*/1, /*Type*/GILLT_s32,
        GIM_CheckType, /*MI*/1, /*Op*/2, /*Type*/GILLT_s32,
        GIM_RecordInsnIgnoreCopies, /*DefineMI*/2, /*MI*/1, /*OpIdx*/2, // MIs[2]
        GIM_CheckOpcode, /*MI*/2, GIMT_Encode2(TargetOpcode::G_XOR),
        GIM_CheckType, /*MI*/2, /*Op*/1, /*Type*/GILLT_s32,
        GIM_CheckType, /*MI*/2, /*Op*/2, /*Type*/GILLT_s32,
        GIM_CheckConstantInt8, /*MI*/2, /*Op*/2, uint8_t(-1),
        GIM_RecordInsnIgnoreCopies, /*DefineMI*/3, /*MI*/0, /*OpIdx*/2, // MIs[3]
        GIM_CheckOpcode, /*MI*/3, GIMT_Encode2(TargetOpcode::G_AND),
        GIM_CheckType, /*MI*/3, /*Op*/1, /*Type*/GILLT_s32,
        // MIs[3] x
        GIM_CheckIsSameOperandIgnoreCopies, /*MI*/3, /*OpIdx*/2, /*OtherMI*/2, /*OtherOpIdx*/1,
        GIM_CheckCxxInsnPredicate, /*MI*/0, /*FnId*/GIMT_Encode2(GICXXPred_MI_Predicate_anonymous_22557),
        GIM_CheckIsSafeToFold, /*InsnID*/1,
        GIM_CheckIsSafeToFold, /*InsnID*/2,
        GIM_CheckIsSafeToFold, /*InsnID*/3,
        // (or:{ *:[i32] } (and:{ *:[i32] } i32:{ *:[i32] }:$z, (xor:{ *:[i32] } i32:{ *:[i32] }:$x, -1:{ *:[i32] })), (and:{ *:[i32] } i32:{ *:[i32] }:$y, i32:{ *:[i32] }:$x))<<P:Predicate_anonymous_22557>>  =>  (V_BFI_B32_e64:{ *:[i32] } (COPY_TO_REGCLASS:{ *:[i16] } VSrc_b32:{ *:[i32] }:$x, VGPR_32:{ *:[i32] }), (COPY_TO_REGCLASS:{ *:[i16] } VSrc_b32:{ *:[i32] }:$y, VGPR_32:{ *:[i32] }), (COPY_TO_REGCLASS:{ *:[i16] } VSrc_b32:{ *:[i32] }:$z, VGPR_32:{ *:[i32] }))
        GIR_MakeTempReg, /*TempRegID*/0, /*TypeID*/GILLT_s16,
        GIR_MakeTempReg, /*TempRegID*/1, /*TypeID*/GILLT_s16,
        GIR_MakeTempReg, /*TempRegID*/2, /*TypeID*/GILLT_s16,
        GIR_BuildMI, /*InsnID*/3, /*Opcode*/GIMT_Encode2(TargetOpcode::COPY),
        GIR_AddTempRegister, /*InsnID*/3, /*TempRegID*/2, /*TempRegFlags*/GIMT_Encode2(RegState::Define),
        GIR_Copy, /*NewInsnID*/3, /*OldInsnID*/1, /*OpIdx*/1, // z
        GIR_ConstrainSelectedInstOperands, /*InsnID*/3,
        GIR_BuildMI, /*InsnID*/2, /*Opcode*/GIMT_Encode2(TargetOpcode::COPY),
        GIR_AddTempRegister, /*InsnID*/2, /*TempRegID*/1, /*TempRegFlags*/GIMT_Encode2(RegState::Define),
        GIR_Copy, /*NewInsnID*/2, /*OldInsnID*/3, /*OpIdx*/1, // y
        GIR_ConstrainSelectedInstOperands, /*InsnID*/2,
        GIR_BuildMI, /*InsnID*/1, /*Opcode*/GIMT_Encode2(TargetOpcode::COPY),
        GIR_AddTempRegister, /*InsnID*/1, /*TempRegID*/0, /*TempRegFlags*/GIMT_Encode2(RegState::Define),
        GIR_Copy, /*NewInsnID*/1, /*OldInsnID*/2, /*OpIdx*/1, // x
        GIR_ConstrainSelectedInstOperands, /*InsnID*/1,
        GIR_BuildMI, /*InsnID*/0, /*Opcode*/GIMT_Encode2(AMDGPU::V_BFI_B32_e64),
        GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/0, // DstI[vdst]
        GIR_AddSimpleTempRegister, /*InsnID*/0, /*TempRegID*/0,
        GIR_AddSimpleTempRegister, /*InsnID*/0, /*TempRegID*/1,
        GIR_AddSimpleTempRegister, /*InsnID*/0, /*TempRegID*/2,
        GIR_ConstrainSelectedInstOperands, /*InsnID*/0,
        GIR_EraseFromParent, /*InsnID*/0,
        // GIR_Coverage, 9873,
        GIR_Done,
      // Label 303: @20029
      GIM_Try, /*On fail goto*//*Label 304*/ GIMT_Encode4(20178), // Rule ID 9870 //
        GIM_CheckRegBankForClass, /*MI*/0, /*Op*/0, /*RC*/GIMT_Encode2(AMDGPU::VGPR_32RegClassID),
        GIM_RecordInsnIgnoreCopies, /*DefineMI*/1, /*MI*/0, /*OpIdx*/1, // MIs[1]
        GIM_CheckOpcode, /*MI*/1, GIMT_Encode2(TargetOpcode::G_AND),
        GIM_CheckType, /*MI*/1, /*Op*/1, /*Type*/GILLT_s32,
        GIM_CheckType, /*MI*/1, /*Op*/2, /*Type*/GILLT_s32,
        GIM_RecordInsnIgnoreCopies, /*DefineMI*/2, /*MI*/0, /*OpIdx*/2, // MIs[2]
        GIM_CheckOpcode, /*MI*/2, GIMT_Encode2(TargetOpcode::G_AND),
        GIM_CheckType, /*MI*/2, /*Op*/1, /*Type*/GILLT_s32,
        GIM_CheckType, /*MI*/2, /*Op*/2, /*Type*/GILLT_s32,
        GIM_RecordInsnIgnoreCopies, /*DefineMI*/3, /*MI*/2, /*OpIdx*/1, // MIs[3]
        GIM_CheckOpcode, /*MI*/3, GIMT_Encode2(TargetOpcode::G_XOR),
        GIM_CheckType, /*MI*/3, /*Op*/2, /*Type*/GILLT_s32,
        // MIs[3] x
        GIM_CheckIsSameOperandIgnoreCopies, /*MI*/3, /*OpIdx*/1, /*OtherMI*/1, /*OtherOpIdx*/2,
        GIM_CheckConstantInt8, /*MI*/3, /*Op*/2, uint8_t(-1),
        GIM_CheckCxxInsnPredicate, /*MI*/0, /*FnId*/GIMT_Encode2(GICXXPred_MI_Predicate_anonymous_22557),
        GIM_CheckIsSafeToFold, /*InsnID*/1,
        GIM_CheckIsSafeToFold, /*InsnID*/2,
        GIM_CheckIsSafeToFold, /*InsnID*/3,
        // (or:{ *:[i32] } (and:{ *:[i32] } i32:{ *:[i32] }:$y, i32:{ *:[i32] }:$x), (and:{ *:[i32] } (xor:{ *:[i32] } i32:{ *:[i32] }:$x, -1:{ *:[i32] }), i32:{ *:[i32] }:$z))<<P:Predicate_anonymous_22557>>  =>  (V_BFI_B32_e64:{ *:[i32] } (COPY_TO_REGCLASS:{ *:[i16] } VSrc_b32:{ *:[i32] }:$x, VGPR_32:{ *:[i32] }), (COPY_TO_REGCLASS:{ *:[i16] } VSrc_b32:{ *:[i32] }:$y, VGPR_32:{ *:[i32] }), (COPY_TO_REGCLASS:{ *:[i16] } VSrc_b32:{ *:[i32] }:$z, VGPR_32:{ *:[i32] }))
        GIR_MakeTempReg, /*TempRegID*/0, /*TypeID*/GILLT_s16,
        GIR_MakeTempReg, /*TempRegID*/1, /*TypeID*/GILLT_s16,
        GIR_MakeTempReg, /*TempRegID*/2, /*TypeID*/GILLT_s16,
        GIR_BuildMI, /*InsnID*/3, /*Opcode*/GIMT_Encode2(TargetOpcode::COPY),
        GIR_AddTempRegister, /*InsnID*/3, /*TempRegID*/2, /*TempRegFlags*/GIMT_Encode2(RegState::Define),
        GIR_Copy, /*NewInsnID*/3, /*OldInsnID*/2, /*OpIdx*/2, // z
        GIR_ConstrainSelectedInstOperands, /*InsnID*/3,
        GIR_BuildMI, /*InsnID*/2, /*Opcode*/GIMT_Encode2(TargetOpcode::COPY),
        GIR_AddTempRegister, /*InsnID*/2, /*TempRegID*/1, /*TempRegFlags*/GIMT_Encode2(RegState::Define),
        GIR_Copy, /*NewInsnID*/2, /*OldInsnID*/1, /*OpIdx*/1, // y
        GIR_ConstrainSelectedInstOperands, /*InsnID*/2,
        GIR_BuildMI, /*InsnID*/1, /*Opcode*/GIMT_Encode2(TargetOpcode::COPY),
        GIR_AddTempRegister, /*InsnID*/1, /*TempRegID*/0, /*TempRegFlags*/GIMT_Encode2(RegState::Define),
        GIR_Copy, /*NewInsnID*/1, /*OldInsnID*/1, /*OpIdx*/2, // x
        GIR_ConstrainSelectedInstOperands, /*InsnID*/1,
        GIR_BuildMI, /*InsnID*/0, /*Opcode*/GIMT_Encode2(AMDGPU::V_BFI_B32_e64),
        GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/0, // DstI[vdst]
        GIR_AddSimpleTempRegister, /*InsnID*/0, /*TempRegID*/0,
        GIR_AddSimpleTempRegister, /*InsnID*/0, /*TempRegID*/1,
        GIR_AddSimpleTempRegister, /*InsnID*/0, /*TempRegID*/2,
        GIR_ConstrainSelectedInstOperands, /*InsnID*/0,
        GIR_EraseFromParent, /*InsnID*/0,
        // GIR_Coverage, 9870,
        GIR_Done,
      // Label 304: @20178
      GIM_Try, /*On fail goto*//*Label 305*/ GIMT_Encode4(20327), // Rule ID 9872 //
        GIM_CheckRegBankForClass, /*MI*/0, /*Op*/0, /*RC*/GIMT_Encode2(AMDGPU::VGPR_32RegClassID),
        GIM_RecordInsnIgnoreCopies, /*DefineMI*/1, /*MI*/0, /*OpIdx*/1, // MIs[1]
        GIM_CheckOpcode, /*MI*/1, GIMT_Encode2(TargetOpcode::G_AND),
        GIM_CheckType, /*MI*/1, /*Op*/1, /*Type*/GILLT_s32,
        GIM_CheckType, /*MI*/1, /*Op*/2, /*Type*/GILLT_s32,
        GIM_RecordInsnIgnoreCopies, /*DefineMI*/2, /*MI*/0, /*OpIdx*/2, // MIs[2]
        GIM_CheckOpcode, /*MI*/2, GIMT_Encode2(TargetOpcode::G_AND),
        GIM_CheckType, /*MI*/2, /*Op*/1, /*Type*/GILLT_s32,
        GIM_CheckType, /*MI*/2, /*Op*/2, /*Type*/GILLT_s32,
        GIM_RecordInsnIgnoreCopies, /*DefineMI*/3, /*MI*/2, /*OpIdx*/1, // MIs[3]
        GIM_CheckOpcode, /*MI*/3, GIMT_Encode2(TargetOpcode::G_XOR),
        GIM_CheckType, /*MI*/3, /*Op*/2, /*Type*/GILLT_s32,
        // MIs[3] x
        GIM_CheckIsSameOperandIgnoreCopies, /*MI*/3, /*OpIdx*/1, /*OtherMI*/1, /*OtherOpIdx*/1,
        GIM_CheckConstantInt8, /*MI*/3, /*Op*/2, uint8_t(-1),
        GIM_CheckCxxInsnPredicate, /*MI*/0, /*FnId*/GIMT_Encode2(GICXXPred_MI_Predicate_anonymous_22557),
        GIM_CheckIsSafeToFold, /*InsnID*/1,
        GIM_CheckIsSafeToFold, /*InsnID*/2,
        GIM_CheckIsSafeToFold, /*InsnID*/3,
        // (or:{ *:[i32] } (and:{ *:[i32] } i32:{ *:[i32] }:$x, i32:{ *:[i32] }:$y), (and:{ *:[i32] } (xor:{ *:[i32] } i32:{ *:[i32] }:$x, -1:{ *:[i32] }), i32:{ *:[i32] }:$z))<<P:Predicate_anonymous_22557>>  =>  (V_BFI_B32_e64:{ *:[i32] } (COPY_TO_REGCLASS:{ *:[i16] } VSrc_b32:{ *:[i32] }:$x, VGPR_32:{ *:[i32] }), (COPY_TO_REGCLASS:{ *:[i16] } VSrc_b32:{ *:[i32] }:$y, VGPR_32:{ *:[i32] }), (COPY_TO_REGCLASS:{ *:[i16] } VSrc_b32:{ *:[i32] }:$z, VGPR_32:{ *:[i32] }))
        GIR_MakeTempReg, /*TempRegID*/0, /*TypeID*/GILLT_s16,
        GIR_MakeTempReg, /*TempRegID*/1, /*TypeID*/GILLT_s16,
        GIR_MakeTempReg, /*TempRegID*/2, /*TypeID*/GILLT_s16,
        GIR_BuildMI, /*InsnID*/3, /*Opcode*/GIMT_Encode2(TargetOpcode::COPY),
        GIR_AddTempRegister, /*InsnID*/3, /*TempRegID*/2, /*TempRegFlags*/GIMT_Encode2(RegState::Define),
        GIR_Copy, /*NewInsnID*/3, /*OldInsnID*/2, /*OpIdx*/2, // z
        GIR_ConstrainSelectedInstOperands, /*InsnID*/3,
        GIR_BuildMI, /*InsnID*/2, /*Opcode*/GIMT_Encode2(TargetOpcode::COPY),
        GIR_AddTempRegister, /*InsnID*/2, /*TempRegID*/1, /*TempRegFlags*/GIMT_Encode2(RegState::Define),
        GIR_Copy, /*NewInsnID*/2, /*OldInsnID*/1, /*OpIdx*/2, // y
        GIR_ConstrainSelectedInstOperands, /*InsnID*/2,
        GIR_BuildMI, /*InsnID*/1, /*Opcode*/GIMT_Encode2(TargetOpcode::COPY),
        GIR_AddTempRegister, /*InsnID*/1, /*TempRegID*/0, /*TempRegFlags*/GIMT_Encode2(RegState::Define),
        GIR_Copy, /*NewInsnID*/1, /*OldInsnID*/1, /*OpIdx*/1, // x
        GIR_ConstrainSelectedInstOperands, /*InsnID*/1,
        GIR_BuildMI, /*InsnID*/0, /*Opcode*/GIMT_Encode2(AMDGPU::V_BFI_B32_e64),
        GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/0, // DstI[vdst]
        GIR_AddSimpleTempRegister, /*InsnID*/0, /*TempRegID*/0,
        GIR_AddSimpleTempRegister, /*InsnID*/0, /*TempRegID*/1,
        GIR_AddSimpleTempRegister, /*InsnID*/0, /*TempRegID*/2,
        GIR_ConstrainSelectedInstOperands, /*InsnID*/0,
        GIR_EraseFromParent, /*InsnID*/0,
        // GIR_Coverage, 9872,
        GIR_Done,
      // Label 305: @20327
      GIM_Try, /*On fail goto*//*Label 306*/ GIMT_Encode4(20476), // Rule ID 6273 //
        GIM_CheckRegBankForClass, /*MI*/0, /*Op*/0, /*RC*/GIMT_Encode2(AMDGPU::VGPR_32RegClassID),
        GIM_RecordInsnIgnoreCopies, /*DefineMI*/1, /*MI*/0, /*OpIdx*/1, // MIs[1]
        GIM_CheckOpcode, /*MI*/1, GIMT_Encode2(TargetOpcode::G_AND),
        GIM_CheckType, /*MI*/1, /*Op*/1, /*Type*/GILLT_s32,
        GIM_CheckType, /*MI*/1, /*Op*/2, /*Type*/GILLT_s32,
        GIM_RecordInsnIgnoreCopies, /*DefineMI*/2, /*MI*/0, /*OpIdx*/2, // MIs[2]
        GIM_CheckOpcode, /*MI*/2, GIMT_Encode2(TargetOpcode::G_AND),
        GIM_CheckType, /*MI*/2, /*Op*/1, /*Type*/GILLT_s32,
        GIM_CheckType, /*MI*/2, /*Op*/2, /*Type*/GILLT_s32,
        GIM_RecordInsnIgnoreCopies, /*DefineMI*/3, /*MI*/2, /*OpIdx*/2, // MIs[3]
        GIM_CheckOpcode, /*MI*/3, GIMT_Encode2(TargetOpcode::G_XOR),
        GIM_CheckType, /*MI*/3, /*Op*/2, /*Type*/GILLT_s32,
        // MIs[3] x
        GIM_CheckIsSameOperandIgnoreCopies, /*MI*/3, /*OpIdx*/1, /*OtherMI*/1, /*OtherOpIdx*/2,
        GIM_CheckConstantInt8, /*MI*/3, /*Op*/2, uint8_t(-1),
        GIM_CheckCxxInsnPredicate, /*MI*/0, /*FnId*/GIMT_Encode2(GICXXPred_MI_Predicate_anonymous_22557),
        GIM_CheckIsSafeToFold, /*InsnID*/1,
        GIM_CheckIsSafeToFold, /*InsnID*/2,
        GIM_CheckIsSafeToFold, /*InsnID*/3,
        // (or:{ *:[i32] } (and:{ *:[i32] } i32:{ *:[i32] }:$y, i32:{ *:[i32] }:$x), (and:{ *:[i32] } i32:{ *:[i32] }:$z, (xor:{ *:[i32] } i32:{ *:[i32] }:$x, -1:{ *:[i32] })))<<P:Predicate_anonymous_22557>>  =>  (V_BFI_B32_e64:{ *:[i32] } (COPY_TO_REGCLASS:{ *:[i16] } VSrc_b32:{ *:[i32] }:$x, VGPR_32:{ *:[i32] }), (COPY_TO_REGCLASS:{ *:[i16] } VSrc_b32:{ *:[i32] }:$y, VGPR_32:{ *:[i32] }), (COPY_TO_REGCLASS:{ *:[i16] } VSrc_b32:{ *:[i32] }:$z, VGPR_32:{ *:[i32] }))
        GIR_MakeTempReg, /*TempRegID*/0, /*TypeID*/GILLT_s16,
        GIR_MakeTempReg, /*TempRegID*/1, /*TypeID*/GILLT_s16,
        GIR_MakeTempReg, /*TempRegID*/2, /*TypeID*/GILLT_s16,
        GIR_BuildMI, /*InsnID*/3, /*Opcode*/GIMT_Encode2(TargetOpcode::COPY),
        GIR_AddTempRegister, /*InsnID*/3, /*TempRegID*/2, /*TempRegFlags*/GIMT_Encode2(RegState::Define),
        GIR_Copy, /*NewInsnID*/3, /*OldInsnID*/2, /*OpIdx*/1, // z
        GIR_ConstrainSelectedInstOperands, /*InsnID*/3,
        GIR_BuildMI, /*InsnID*/2, /*Opcode*/GIMT_Encode2(TargetOpcode::COPY),
        GIR_AddTempRegister, /*InsnID*/2, /*TempRegID*/1, /*TempRegFlags*/GIMT_Encode2(RegState::Define),
        GIR_Copy, /*NewInsnID*/2, /*OldInsnID*/1, /*OpIdx*/1, // y
        GIR_ConstrainSelectedInstOperands, /*InsnID*/2,
        GIR_BuildMI, /*InsnID*/1, /*Opcode*/GIMT_Encode2(TargetOpcode::COPY),
        GIR_AddTempRegister, /*InsnID*/1, /*TempRegID*/0, /*TempRegFlags*/GIMT_Encode2(RegState::Define),
        GIR_Copy, /*NewInsnID*/1, /*OldInsnID*/1, /*OpIdx*/2, // x
        GIR_ConstrainSelectedInstOperands, /*InsnID*/1,
        GIR_BuildMI, /*InsnID*/0, /*Opcode*/GIMT_Encode2(AMDGPU::V_BFI_B32_e64),
        GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/0, // DstI[vdst]
        GIR_AddSimpleTempRegister, /*InsnID*/0, /*TempRegID*/0,
        GIR_AddSimpleTempRegister, /*InsnID*/0, /*TempRegID*/1,
        GIR_AddSimpleTempRegister, /*InsnID*/0, /*TempRegID*/2,
        GIR_ConstrainSelectedInstOperands, /*InsnID*/0,
        GIR_EraseFromParent, /*InsnID*/0,
        // GIR_Coverage, 6273,
        GIR_Done,
      // Label 306: @20476
      GIM_Try, /*On fail goto*//*Label 307*/ GIMT_Encode4(20625), // Rule ID 9871 //
        GIM_CheckRegBankForClass, /*MI*/0, /*Op*/0, /*RC*/GIMT_Encode2(AMDGPU::VGPR_32RegClassID),
        GIM_RecordInsnIgnoreCopies, /*DefineMI*/1, /*MI*/0, /*OpIdx*/1, // MIs[1]
        GIM_CheckOpcode, /*MI*/1, GIMT_Encode2(TargetOpcode::G_AND),
        GIM_CheckType, /*MI*/1, /*Op*/1, /*Type*/GILLT_s32,
        GIM_CheckType, /*MI*/1, /*Op*/2, /*Type*/GILLT_s32,
        GIM_RecordInsnIgnoreCopies, /*DefineMI*/2, /*MI*/0, /*OpIdx*/2, // MIs[2]
        GIM_CheckOpcode, /*MI*/2, GIMT_Encode2(TargetOpcode::G_AND),
        GIM_CheckType, /*MI*/2, /*Op*/1, /*Type*/GILLT_s32,
        GIM_CheckType, /*MI*/2, /*Op*/2, /*Type*/GILLT_s32,
        GIM_RecordInsnIgnoreCopies, /*DefineMI*/3, /*MI*/2, /*OpIdx*/2, // MIs[3]
        GIM_CheckOpcode, /*MI*/3, GIMT_Encode2(TargetOpcode::G_XOR),
        GIM_CheckType, /*MI*/3, /*Op*/2, /*Type*/GILLT_s32,
        // MIs[3] x
        GIM_CheckIsSameOperandIgnoreCopies, /*MI*/3, /*OpIdx*/1, /*OtherMI*/1, /*OtherOpIdx*/1,
        GIM_CheckConstantInt8, /*MI*/3, /*Op*/2, uint8_t(-1),
        GIM_CheckCxxInsnPredicate, /*MI*/0, /*FnId*/GIMT_Encode2(GICXXPred_MI_Predicate_anonymous_22557),
        GIM_CheckIsSafeToFold, /*InsnID*/1,
        GIM_CheckIsSafeToFold, /*InsnID*/2,
        GIM_CheckIsSafeToFold, /*InsnID*/3,
        // (or:{ *:[i32] } (and:{ *:[i32] } i32:{ *:[i32] }:$x, i32:{ *:[i32] }:$y), (and:{ *:[i32] } i32:{ *:[i32] }:$z, (xor:{ *:[i32] } i32:{ *:[i32] }:$x, -1:{ *:[i32] })))<<P:Predicate_anonymous_22557>>  =>  (V_BFI_B32_e64:{ *:[i32] } (COPY_TO_REGCLASS:{ *:[i16] } VSrc_b32:{ *:[i32] }:$x, VGPR_32:{ *:[i32] }), (COPY_TO_REGCLASS:{ *:[i16] } VSrc_b32:{ *:[i32] }:$y, VGPR_32:{ *:[i32] }), (COPY_TO_REGCLASS:{ *:[i16] } VSrc_b32:{ *:[i32] }:$z, VGPR_32:{ *:[i32] }))
        GIR_MakeTempReg, /*TempRegID*/0, /*TypeID*/GILLT_s16,
        GIR_MakeTempReg, /*TempRegID*/1, /*TypeID*/GILLT_s16,
        GIR_MakeTempReg, /*TempRegID*/2, /*TypeID*/GILLT_s16,
        GIR_BuildMI, /*InsnID*/3, /*Opcode*/GIMT_Encode2(TargetOpcode::COPY),
        GIR_AddTempRegister, /*InsnID*/3, /*TempRegID*/2, /*TempRegFlags*/GIMT_Encode2(RegState::Define),
        GIR_Copy, /*NewInsnID*/3, /*OldInsnID*/2, /*OpIdx*/1, // z
        GIR_ConstrainSelectedInstOperands, /*InsnID*/3,
        GIR_BuildMI, /*InsnID*/2, /*Opcode*/GIMT_Encode2(TargetOpcode::COPY),
        GIR_AddTempRegister, /*InsnID*/2, /*TempRegID*/1, /*TempRegFlags*/GIMT_Encode2(RegState::Define),
        GIR_Copy, /*NewInsnID*/2, /*OldInsnID*/1, /*OpIdx*/2, // y
        GIR_ConstrainSelectedInstOperands, /*InsnID*/2,
        GIR_BuildMI, /*InsnID*/1, /*Opcode*/GIMT_Encode2(TargetOpcode::COPY),
        GIR_AddTempRegister, /*InsnID*/1, /*TempRegID*/0, /*TempRegFlags*/GIMT_Encode2(RegState::Define),
        GIR_Copy, /*NewInsnID*/1, /*OldInsnID*/1, /*OpIdx*/1, // x
        GIR_ConstrainSelectedInstOperands, /*InsnID*/1,
        GIR_BuildMI, /*InsnID*/0, /*Opcode*/GIMT_Encode2(AMDGPU::V_BFI_B32_e64),
        GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/0, // DstI[vdst]
        GIR_AddSimpleTempRegister, /*InsnID*/0, /*TempRegID*/0,
        GIR_AddSimpleTempRegister, /*InsnID*/0, /*TempRegID*/1,
        GIR_AddSimpleTempRegister, /*InsnID*/0, /*TempRegID*/2,
        GIR_ConstrainSelectedInstOperands, /*InsnID*/0,
        GIR_EraseFromParent, /*InsnID*/0,
        // GIR_Coverage, 9871,
        GIR_Done,
      // Label 307: @20625
      GIM_Try, /*On fail goto*//*Label 308*/ GIMT_Encode4(20733), // Rule ID 2191 //
        GIM_CheckFeatures, GIMT_Encode2(GIFBS_isGFX9Plus),
        GIM_CheckRegBankForClass, /*MI*/0, /*Op*/0, /*RC*/GIMT_Encode2(AMDGPU::VGPR_32RegClassID),
        GIM_RecordInsn, /*DefineMI*/1, /*MI*/0, /*OpIdx*/1, // MIs[1]
        GIM_CheckOpcode, /*MI*/1, GIMT_Encode2(TargetOpcode::G_SHL),
        GIM_CheckType, /*MI*/1, /*Op*/1, /*Type*/GILLT_s32,
        GIM_CheckType, /*MI*/1, /*Op*/2, /*Type*/GILLT_s32,
        GIM_RecordNamedOperand, /*MI*/1, /*Op*/1, /*StoreIdx*/0, // Name : pred:5:x
        GIM_RecordInsn, /*DefineMI*/2, /*MI*/1, /*OpIdx*/2, // MIs[2]
        GIM_CheckOpcode, /*MI*/2, GIMT_Encode2(TargetOpcode::G_AND),
        GIM_CheckType, /*MI*/2, /*Op*/1, /*Type*/GILLT_s32,
        GIM_CheckType, /*MI*/2, /*Op*/2, /*Type*/GILLT_s32,
        GIM_RecordNamedOperand, /*MI*/2, /*Op*/1, /*StoreIdx*/1, // Name : pred:5:y
        GIM_RecordInsn, /*DefineMI*/3, /*MI*/2, /*OpIdx*/2, // MIs[3]
        GIM_CheckOpcode, /*MI*/3, GIMT_Encode2(TargetOpcode::G_CONSTANT),
        // MIs[3] Operand 1
        // No operand predicates
        GIM_CheckCxxInsnPredicate, /*MI*/2, /*FnId*/GIMT_Encode2(GICXXPred_MI_Predicate_csh_mask_32),
        GIM_CheckCxxInsnPredicate, /*MI*/1, /*FnId*/GIMT_Encode2(GICXXPred_MI_Predicate_anonymous_23603),
        GIM_RecordNamedOperand, /*MI*/0, /*Op*/2, /*StoreIdx*/2, // Name : pred:5:z
        GIM_CheckCxxInsnPredicate, /*MI*/0, /*FnId*/GIMT_Encode2(GICXXPred_MI_Predicate_anonymous_23613),
        GIM_CheckIsSafeToFold, /*InsnID*/1,
        GIM_CheckIsSafeToFold, /*InsnID*/2,
        GIM_CheckIsSafeToFold, /*InsnID*/3,
        // (or:{ *:[i32] } (shl:{ *:[i32] } i32:{ *:[i32] }:$src0:$pred:5:x, (and:{ *:[i32] } i32:{ *:[i32] }:$src1:$pred:5:y, (imm:{ *:[i32] }))<<P:Predicate_csh_mask_32>>)<<P:Predicate_anonymous_23603>>, i32:{ *:[i32] }:$src2:$pred:5:z)<<P:5:Predicate_anonymous_23613>>  =>  (V_LSHL_OR_B32_e64:{ *:[i32] } VSrc_b32:{ *:[i32] }:$src0, VSrc_b32:{ *:[i32] }:$src1, VSrc_b32:{ *:[i32] }:$src2)
        GIR_BuildMI, /*InsnID*/0, /*Opcode*/GIMT_Encode2(AMDGPU::V_LSHL_OR_B32_e64),
        GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/0, // DstI[vdst]
        GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/1, /*OpIdx*/1, // src0
        GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/2, /*OpIdx*/1, // src1
        GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/2, // src2
        GIR_ConstrainSelectedInstOperands, /*InsnID*/0,
        GIR_EraseFromParent, /*InsnID*/0,
        // GIR_Coverage, 2191,
        GIR_Done,
      // Label 308: @20733
      GIM_Try, /*On fail goto*//*Label 309*/ GIMT_Encode4(20841), // Rule ID 7213 //
        GIM_CheckFeatures, GIMT_Encode2(GIFBS_isGFX9Plus),
        GIM_CheckRegBankForClass, /*MI*/0, /*Op*/0, /*RC*/GIMT_Encode2(AMDGPU::VGPR_32RegClassID),
        GIM_RecordNamedOperand, /*MI*/0, /*Op*/1, /*StoreIdx*/2, // Name : pred:5:z
        GIM_RecordInsn, /*DefineMI*/1, /*MI*/0, /*OpIdx*/2, // MIs[1]
        GIM_CheckOpcode, /*MI*/1, GIMT_Encode2(TargetOpcode::G_SHL),
        GIM_CheckType, /*MI*/1, /*Op*/1, /*Type*/GILLT_s32,
        GIM_CheckType, /*MI*/1, /*Op*/2, /*Type*/GILLT_s32,
        GIM_RecordNamedOperand, /*MI*/1, /*Op*/1, /*StoreIdx*/0, // Name : pred:5:x
        GIM_RecordInsn, /*DefineMI*/2, /*MI*/1, /*OpIdx*/2, // MIs[2]
        GIM_CheckOpcode, /*MI*/2, GIMT_Encode2(TargetOpcode::G_AND),
        GIM_CheckType, /*MI*/2, /*Op*/1, /*Type*/GILLT_s32,
        GIM_CheckType, /*MI*/2, /*Op*/2, /*Type*/GILLT_s32,
        GIM_RecordNamedOperand, /*MI*/2, /*Op*/1, /*StoreIdx*/1, // Name : pred:5:y
        GIM_RecordInsn, /*DefineMI*/3, /*MI*/2, /*OpIdx*/2, // MIs[3]
        GIM_CheckOpcode, /*MI*/3, GIMT_Encode2(TargetOpcode::G_CONSTANT),
        // MIs[3] Operand 1
        // No operand predicates
        GIM_CheckCxxInsnPredicate, /*MI*/2, /*FnId*/GIMT_Encode2(GICXXPred_MI_Predicate_csh_mask_32),
        GIM_CheckCxxInsnPredicate, /*MI*/1, /*FnId*/GIMT_Encode2(GICXXPred_MI_Predicate_anonymous_23603),
        GIM_CheckCxxInsnPredicate, /*MI*/0, /*FnId*/GIMT_Encode2(GICXXPred_MI_Predicate_anonymous_23613),
        GIM_CheckIsSafeToFold, /*InsnID*/1,
        GIM_CheckIsSafeToFold, /*InsnID*/2,
        GIM_CheckIsSafeToFold, /*InsnID*/3,
        // (or:{ *:[i32] } i32:{ *:[i32] }:$src2:$pred:5:z, (shl:{ *:[i32] } i32:{ *:[i32] }:$src0:$pred:5:x, (and:{ *:[i32] } i32:{ *:[i32] }:$src1:$pred:5:y, (imm:{ *:[i32] }))<<P:Predicate_csh_mask_32>>)<<P:Predicate_anonymous_23603>>)<<P:5:Predicate_anonymous_23613>>  =>  (V_LSHL_OR_B32_e64:{ *:[i32] } VSrc_b32:{ *:[i32] }:$src0, VSrc_b32:{ *:[i32] }:$src1, VSrc_b32:{ *:[i32] }:$src2)
        GIR_BuildMI, /*InsnID*/0, /*Opcode*/GIMT_Encode2(AMDGPU::V_LSHL_OR_B32_e64),
        GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/0, // DstI[vdst]
        GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/1, /*OpIdx*/1, // src0
        GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/2, /*OpIdx*/1, // src1
        GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/1, // src2
        GIR_ConstrainSelectedInstOperands, /*InsnID*/0,
        GIR_EraseFromParent, /*InsnID*/0,
        // GIR_Coverage, 7213,
        GIR_Done,
      // Label 309: @20841
      GIM_Try, /*On fail goto*//*Label 310*/ GIMT_Encode4(21025), // Rule ID 9921 //
        GIM_CheckRegBankForClass, /*MI*/0, /*Op*/0, /*RC*/GIMT_Encode2(AMDGPU::VGPR_32RegClassID),
        GIM_RecordInsnIgnoreCopies, /*DefineMI*/1, /*MI*/0, /*OpIdx*/1, // MIs[1]
        GIM_CheckOpcode, /*MI*/1, GIMT_Encode2(TargetOpcode::G_AND),
        GIM_CheckType, /*MI*/1, /*Op*/1, /*Type*/GILLT_s32,
        GIM_CheckType, /*MI*/1, /*Op*/2, /*Type*/GILLT_s32,
        GIM_RecordInsnIgnoreCopies, /*DefineMI*/2, /*MI*/1, /*OpIdx*/1, // MIs[2]
        GIM_CheckOpcode, /*MI*/2, GIMT_Encode2(TargetOpcode::G_OR),
        GIM_CheckType, /*MI*/2, /*Op*/1, /*Type*/GILLT_s32,
        GIM_CheckType, /*MI*/2, /*Op*/2, /*Type*/GILLT_s32,
        GIM_RecordInsnIgnoreCopies, /*DefineMI*/3, /*MI*/0, /*OpIdx*/2, // MIs[3]
        GIM_CheckOpcode, /*MI*/3, GIMT_Encode2(TargetOpcode::G_AND),
        // MIs[3] x
        GIM_CheckIsSameOperandIgnoreCopies, /*MI*/3, /*OpIdx*/1, /*OtherMI*/2, /*OtherOpIdx*/1,
        // MIs[3] z
        GIM_CheckIsSameOperandIgnoreCopies, /*MI*/3, /*OpIdx*/2, /*OtherMI*/2, /*OtherOpIdx*/2,
        GIM_CheckCxxInsnPredicate, /*MI*/0, /*FnId*/GIMT_Encode2(GICXXPred_MI_Predicate_anonymous_22557),
        GIM_CheckIsSafeToFold, /*InsnID*/1,
        GIM_CheckIsSafeToFold, /*InsnID*/2,
        GIM_CheckIsSafeToFold, /*InsnID*/3,
        // (or:{ *:[i32] } (and:{ *:[i32] } (or:{ *:[i32] } i32:{ *:[i32] }:$x, i32:{ *:[i32] }:$z), i32:{ *:[i32] }:$y), (and:{ *:[i32] } i32:{ *:[i32] }:$x, i32:{ *:[i32] }:$z))<<P:Predicate_anonymous_22557>>  =>  (V_BFI_B32_e64:{ *:[i32] } (V_XOR_B32_e64:{ *:[i16] } (COPY_TO_REGCLASS:{ *:[i16] } VSrc_b32:{ *:[i32] }:$x, VGPR_32:{ *:[i32] }), (COPY_TO_REGCLASS:{ *:[i16] } VSrc_b32:{ *:[i32] }:$y, VGPR_32:{ *:[i32] })), (COPY_TO_REGCLASS:{ *:[i16] } VSrc_b32:{ *:[i32] }:$z, VGPR_32:{ *:[i32] }), (COPY_TO_REGCLASS:{ *:[i16] } VSrc_b32:{ *:[i32] }:$y, VGPR_32:{ *:[i32] }))
        GIR_MakeTempReg, /*TempRegID*/0, /*TypeID*/GILLT_s16,
        GIR_MakeTempReg, /*TempRegID*/1, /*TypeID*/GILLT_s16,
        GIR_MakeTempReg, /*TempRegID*/2, /*TypeID*/GILLT_s16,
        GIR_MakeTempReg, /*TempRegID*/3, /*TypeID*/GILLT_s16,
        GIR_MakeTempReg, /*TempRegID*/4, /*TypeID*/GILLT_s16,
        GIR_BuildMI, /*InsnID*/5, /*Opcode*/GIMT_Encode2(TargetOpcode::COPY),
        GIR_AddTempRegister, /*InsnID*/5, /*TempRegID*/4, /*TempRegFlags*/GIMT_Encode2(RegState::Define),
        GIR_Copy, /*NewInsnID*/5, /*OldInsnID*/1, /*OpIdx*/2, // y
        GIR_ConstrainSelectedInstOperands, /*InsnID*/5,
        GIR_BuildMI, /*InsnID*/4, /*Opcode*/GIMT_Encode2(TargetOpcode::COPY),
        GIR_AddTempRegister, /*InsnID*/4, /*TempRegID*/3, /*TempRegFlags*/GIMT_Encode2(RegState::Define),
        GIR_Copy, /*NewInsnID*/4, /*OldInsnID*/2, /*OpIdx*/2, // z
        GIR_ConstrainSelectedInstOperands, /*InsnID*/4,
        GIR_BuildMI, /*InsnID*/3, /*Opcode*/GIMT_Encode2(TargetOpcode::COPY),
        GIR_AddTempRegister, /*InsnID*/3, /*TempRegID*/2, /*TempRegFlags*/GIMT_Encode2(RegState::Define),
        GIR_Copy, /*NewInsnID*/3, /*OldInsnID*/1, /*OpIdx*/2, // y
        GIR_ConstrainSelectedInstOperands, /*InsnID*/3,
        GIR_BuildMI, /*InsnID*/2, /*Opcode*/GIMT_Encode2(TargetOpcode::COPY),
        GIR_AddTempRegister, /*InsnID*/2, /*TempRegID*/1, /*TempRegFlags*/GIMT_Encode2(RegState::Define),
        GIR_Copy, /*NewInsnID*/2, /*OldInsnID*/2, /*OpIdx*/1, // x
        GIR_ConstrainSelectedInstOperands, /*InsnID*/2,
        GIR_BuildMI, /*InsnID*/1, /*Opcode*/GIMT_Encode2(AMDGPU::V_XOR_B32_e64),
        GIR_AddTempRegister, /*InsnID*/1, /*TempRegID*/0, /*TempRegFlags*/GIMT_Encode2(RegState::Define),
        GIR_AddSimpleTempRegister, /*InsnID*/1, /*TempRegID*/1,
        GIR_AddSimpleTempRegister, /*InsnID*/1, /*TempRegID*/2,
        GIR_ConstrainSelectedInstOperands, /*InsnID*/1,
        GIR_BuildMI, /*InsnID*/0, /*Opcode*/GIMT_Encode2(AMDGPU::V_BFI_B32_e64),
        GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/0, // DstI[vdst]
        GIR_AddSimpleTempRegister, /*InsnID*/0, /*TempRegID*/0,
        GIR_AddSimpleTempRegister, /*InsnID*/0, /*TempRegID*/3,
        GIR_AddSimpleTempRegister, /*InsnID*/0, /*TempRegID*/4,
        GIR_ConstrainSelectedInstOperands, /*InsnID*/0,
        GIR_EraseFromParent, /*InsnID*/0,
        // GIR_Coverage, 9921,
        GIR_Done,
      // Label 310: @21025
      GIM_Try, /*On fail goto*//*Label 311*/ GIMT_Encode4(21209), // Rule ID 9922 //
        GIM_CheckRegBankForClass, /*MI*/0, /*Op*/0, /*RC*/GIMT_Encode2(AMDGPU::VGPR_32RegClassID),
        GIM_RecordInsnIgnoreCopies, /*DefineMI*/1, /*MI*/0, /*OpIdx*/1, // MIs[1]
        GIM_CheckOpcode, /*MI*/1, GIMT_Encode2(TargetOpcode::G_AND),
        GIM_CheckType, /*MI*/1, /*Op*/1, /*Type*/GILLT_s32,
        GIM_CheckType, /*MI*/1, /*Op*/2, /*Type*/GILLT_s32,
        GIM_RecordInsnIgnoreCopies, /*DefineMI*/2, /*MI*/1, /*OpIdx*/1, // MIs[2]
        GIM_CheckOpcode, /*MI*/2, GIMT_Encode2(TargetOpcode::G_OR),
        GIM_CheckType, /*MI*/2, /*Op*/1, /*Type*/GILLT_s32,
        GIM_CheckType, /*MI*/2, /*Op*/2, /*Type*/GILLT_s32,
        GIM_RecordInsnIgnoreCopies, /*DefineMI*/3, /*MI*/0, /*OpIdx*/2, // MIs[3]
        GIM_CheckOpcode, /*MI*/3, GIMT_Encode2(TargetOpcode::G_AND),
        // MIs[3] z
        GIM_CheckIsSameOperandIgnoreCopies, /*MI*/3, /*OpIdx*/1, /*OtherMI*/2, /*OtherOpIdx*/2,
        // MIs[3] x
        GIM_CheckIsSameOperandIgnoreCopies, /*MI*/3, /*OpIdx*/2, /*OtherMI*/2, /*OtherOpIdx*/1,
        GIM_CheckCxxInsnPredicate, /*MI*/0, /*FnId*/GIMT_Encode2(GICXXPred_MI_Predicate_anonymous_22557),
        GIM_CheckIsSafeToFold, /*InsnID*/1,
        GIM_CheckIsSafeToFold, /*InsnID*/2,
        GIM_CheckIsSafeToFold, /*InsnID*/3,
        // (or:{ *:[i32] } (and:{ *:[i32] } (or:{ *:[i32] } i32:{ *:[i32] }:$x, i32:{ *:[i32] }:$z), i32:{ *:[i32] }:$y), (and:{ *:[i32] } i32:{ *:[i32] }:$z, i32:{ *:[i32] }:$x))<<P:Predicate_anonymous_22557>>  =>  (V_BFI_B32_e64:{ *:[i32] } (V_XOR_B32_e64:{ *:[i16] } (COPY_TO_REGCLASS:{ *:[i16] } VSrc_b32:{ *:[i32] }:$x, VGPR_32:{ *:[i32] }), (COPY_TO_REGCLASS:{ *:[i16] } VSrc_b32:{ *:[i32] }:$y, VGPR_32:{ *:[i32] })), (COPY_TO_REGCLASS:{ *:[i16] } VSrc_b32:{ *:[i32] }:$z, VGPR_32:{ *:[i32] }), (COPY_TO_REGCLASS:{ *:[i16] } VSrc_b32:{ *:[i32] }:$y, VGPR_32:{ *:[i32] }))
        GIR_MakeTempReg, /*TempRegID*/0, /*TypeID*/GILLT_s16,
        GIR_MakeTempReg, /*TempRegID*/1, /*TypeID*/GILLT_s16,
        GIR_MakeTempReg, /*TempRegID*/2, /*TypeID*/GILLT_s16,
        GIR_MakeTempReg, /*TempRegID*/3, /*TypeID*/GILLT_s16,
        GIR_MakeTempReg, /*TempRegID*/4, /*TypeID*/GILLT_s16,
        GIR_BuildMI, /*InsnID*/5, /*Opcode*/GIMT_Encode2(TargetOpcode::COPY),
        GIR_AddTempRegister, /*InsnID*/5, /*TempRegID*/4, /*TempRegFlags*/GIMT_Encode2(RegState::Define),
        GIR_Copy, /*NewInsnID*/5, /*OldInsnID*/1, /*OpIdx*/2, // y
        GIR_ConstrainSelectedInstOperands, /*InsnID*/5,
        GIR_BuildMI, /*InsnID*/4, /*Opcode*/GIMT_Encode2(TargetOpcode::COPY),
        GIR_AddTempRegister, /*InsnID*/4, /*TempRegID*/3, /*TempRegFlags*/GIMT_Encode2(RegState::Define),
        GIR_Copy, /*NewInsnID*/4, /*OldInsnID*/2, /*OpIdx*/2, // z
        GIR_ConstrainSelectedInstOperands, /*InsnID*/4,
        GIR_BuildMI, /*InsnID*/3, /*Opcode*/GIMT_Encode2(TargetOpcode::COPY),
        GIR_AddTempRegister, /*InsnID*/3, /*TempRegID*/2, /*TempRegFlags*/GIMT_Encode2(RegState::Define),
        GIR_Copy, /*NewInsnID*/3, /*OldInsnID*/1, /*OpIdx*/2, // y
        GIR_ConstrainSelectedInstOperands, /*InsnID*/3,
        GIR_BuildMI, /*InsnID*/2, /*Opcode*/GIMT_Encode2(TargetOpcode::COPY),
        GIR_AddTempRegister, /*InsnID*/2, /*TempRegID*/1, /*TempRegFlags*/GIMT_Encode2(RegState::Define),
        GIR_Copy, /*NewInsnID*/2, /*OldInsnID*/2, /*OpIdx*/1, // x
        GIR_ConstrainSelectedInstOperands, /*InsnID*/2,
        GIR_BuildMI, /*InsnID*/1, /*Opcode*/GIMT_Encode2(AMDGPU::V_XOR_B32_e64),
        GIR_AddTempRegister, /*InsnID*/1, /*TempRegID*/0, /*TempRegFlags*/GIMT_Encode2(RegState::Define),
        GIR_AddSimpleTempRegister, /*InsnID*/1, /*TempRegID*/1,
        GIR_AddSimpleTempRegister, /*InsnID*/1, /*TempRegID*/2,
        GIR_ConstrainSelectedInstOperands, /*InsnID*/1,
        GIR_BuildMI, /*InsnID*/0, /*Opcode*/GIMT_Encode2(AMDGPU::V_BFI_B32_e64),
        GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/0, // DstI[vdst]
        GIR_AddSimpleTempRegister, /*InsnID*/0, /*TempRegID*/0,
        GIR_AddSimpleTempRegister, /*InsnID*/0, /*TempRegID*/3,
        GIR_AddSimpleTempRegister, /*InsnID*/0, /*TempRegID*/4,
        GIR_ConstrainSelectedInstOperands, /*InsnID*/0,
        GIR_EraseFromParent, /*InsnID*/0,
        // GIR_Coverage, 9922,
        GIR_Done,
      // Label 311: @21209
      GIM_Try, /*On fail goto*//*Label 312*/ GIMT_Encode4(21393), // Rule ID 9923 //
        GIM_CheckRegBankForClass, /*MI*/0, /*Op*/0, /*RC*/GIMT_Encode2(AMDGPU::VGPR_32RegClassID),
        GIM_RecordInsnIgnoreCopies, /*DefineMI*/1, /*MI*/0, /*OpIdx*/1, // MIs[1]
        GIM_CheckOpcode, /*MI*/1, GIMT_Encode2(TargetOpcode::G_AND),
        GIM_CheckType, /*MI*/1, /*Op*/1, /*Type*/GILLT_s32,
        GIM_CheckType, /*MI*/1, /*Op*/2, /*Type*/GILLT_s32,
        GIM_RecordInsnIgnoreCopies, /*DefineMI*/2, /*MI*/1, /*OpIdx*/1, // MIs[2]
        GIM_CheckOpcode, /*MI*/2, GIMT_Encode2(TargetOpcode::G_OR),
        GIM_CheckType, /*MI*/2, /*Op*/1, /*Type*/GILLT_s32,
        GIM_CheckType, /*MI*/2, /*Op*/2, /*Type*/GILLT_s32,
        GIM_RecordInsnIgnoreCopies, /*DefineMI*/3, /*MI*/0, /*OpIdx*/2, // MIs[3]
        GIM_CheckOpcode, /*MI*/3, GIMT_Encode2(TargetOpcode::G_AND),
        // MIs[3] x
        GIM_CheckIsSameOperandIgnoreCopies, /*MI*/3, /*OpIdx*/1, /*OtherMI*/2, /*OtherOpIdx*/2,
        // MIs[3] z
        GIM_CheckIsSameOperandIgnoreCopies, /*MI*/3, /*OpIdx*/2, /*OtherMI*/2, /*OtherOpIdx*/1,
        GIM_CheckCxxInsnPredicate, /*MI*/0, /*FnId*/GIMT_Encode2(GICXXPred_MI_Predicate_anonymous_22557),
        GIM_CheckIsSafeToFold, /*InsnID*/1,
        GIM_CheckIsSafeToFold, /*InsnID*/2,
        GIM_CheckIsSafeToFold, /*InsnID*/3,
        // (or:{ *:[i32] } (and:{ *:[i32] } (or:{ *:[i32] } i32:{ *:[i32] }:$z, i32:{ *:[i32] }:$x), i32:{ *:[i32] }:$y), (and:{ *:[i32] } i32:{ *:[i32] }:$x, i32:{ *:[i32] }:$z))<<P:Predicate_anonymous_22557>>  =>  (V_BFI_B32_e64:{ *:[i32] } (V_XOR_B32_e64:{ *:[i16] } (COPY_TO_REGCLASS:{ *:[i16] } VSrc_b32:{ *:[i32] }:$x, VGPR_32:{ *:[i32] }), (COPY_TO_REGCLASS:{ *:[i16] } VSrc_b32:{ *:[i32] }:$y, VGPR_32:{ *:[i32] })), (COPY_TO_REGCLASS:{ *:[i16] } VSrc_b32:{ *:[i32] }:$z, VGPR_32:{ *:[i32] }), (COPY_TO_REGCLASS:{ *:[i16] } VSrc_b32:{ *:[i32] }:$y, VGPR_32:{ *:[i32] }))
        GIR_MakeTempReg, /*TempRegID*/0, /*TypeID*/GILLT_s16,
        GIR_MakeTempReg, /*TempRegID*/1, /*TypeID*/GILLT_s16,
        GIR_MakeTempReg, /*TempRegID*/2, /*TypeID*/GILLT_s16,
        GIR_MakeTempReg, /*TempRegID*/3, /*TypeID*/GILLT_s16,
        GIR_MakeTempReg, /*TempRegID*/4, /*TypeID*/GILLT_s16,
        GIR_BuildMI, /*InsnID*/5, /*Opcode*/GIMT_Encode2(TargetOpcode::COPY),
        GIR_AddTempRegister, /*InsnID*/5, /*TempRegID*/4, /*TempRegFlags*/GIMT_Encode2(RegState::Define),
        GIR_Copy, /*NewInsnID*/5, /*OldInsnID*/1, /*OpIdx*/2, // y
        GIR_ConstrainSelectedInstOperands, /*InsnID*/5,
        GIR_BuildMI, /*InsnID*/4, /*Opcode*/GIMT_Encode2(TargetOpcode::COPY),
        GIR_AddTempRegister, /*InsnID*/4, /*TempRegID*/3, /*TempRegFlags*/GIMT_Encode2(RegState::Define),
        GIR_Copy, /*NewInsnID*/4, /*OldInsnID*/2, /*OpIdx*/1, // z
        GIR_ConstrainSelectedInstOperands, /*InsnID*/4,
        GIR_BuildMI, /*InsnID*/3, /*Opcode*/GIMT_Encode2(TargetOpcode::COPY),
        GIR_AddTempRegister, /*InsnID*/3, /*TempRegID*/2, /*TempRegFlags*/GIMT_Encode2(RegState::Define),
        GIR_Copy, /*NewInsnID*/3, /*OldInsnID*/1, /*OpIdx*/2, // y
        GIR_ConstrainSelectedInstOperands, /*InsnID*/3,
        GIR_BuildMI, /*InsnID*/2, /*Opcode*/GIMT_Encode2(TargetOpcode::COPY),
        GIR_AddTempRegister, /*InsnID*/2, /*TempRegID*/1, /*TempRegFlags*/GIMT_Encode2(RegState::Define),
        GIR_Copy, /*NewInsnID*/2, /*OldInsnID*/2, /*OpIdx*/2, // x
        GIR_ConstrainSelectedInstOperands, /*InsnID*/2,
        GIR_BuildMI, /*InsnID*/1, /*Opcode*/GIMT_Encode2(AMDGPU::V_XOR_B32_e64),
        GIR_AddTempRegister, /*InsnID*/1, /*TempRegID*/0, /*TempRegFlags*/GIMT_Encode2(RegState::Define),
        GIR_AddSimpleTempRegister, /*InsnID*/1, /*TempRegID*/1,
        GIR_AddSimpleTempRegister, /*InsnID*/1, /*TempRegID*/2,
        GIR_ConstrainSelectedInstOperands, /*InsnID*/1,
        GIR_BuildMI, /*InsnID*/0, /*Opcode*/GIMT_Encode2(AMDGPU::V_BFI_B32_e64),
        GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/0, // DstI[vdst]
        GIR_AddSimpleTempRegister, /*InsnID*/0, /*TempRegID*/0,
        GIR_AddSimpleTempRegister, /*InsnID*/0, /*TempRegID*/3,
        GIR_AddSimpleTempRegister, /*InsnID*/0, /*TempRegID*/4,
        GIR_ConstrainSelectedInstOperands, /*InsnID*/0,
        GIR_EraseFromParent, /*InsnID*/0,
        // GIR_Coverage, 9923,
        GIR_Done,
      // Label 312: @21393
      GIM_Try, /*On fail goto*//*Label 313*/ GIMT_Encode4(21577), // Rule ID 9924 //
        GIM_CheckRegBankForClass, /*MI*/0, /*Op*/0, /*RC*/GIMT_Encode2(AMDGPU::VGPR_32RegClassID),
        GIM_RecordInsnIgnoreCopies, /*DefineMI*/1, /*MI*/0, /*OpIdx*/1, // MIs[1]
        GIM_CheckOpcode, /*MI*/1, GIMT_Encode2(TargetOpcode::G_AND),
        GIM_CheckType, /*MI*/1, /*Op*/1, /*Type*/GILLT_s32,
        GIM_CheckType, /*MI*/1, /*Op*/2, /*Type*/GILLT_s32,
        GIM_RecordInsnIgnoreCopies, /*DefineMI*/2, /*MI*/1, /*OpIdx*/1, // MIs[2]
        GIM_CheckOpcode, /*MI*/2, GIMT_Encode2(TargetOpcode::G_OR),
        GIM_CheckType, /*MI*/2, /*Op*/1, /*Type*/GILLT_s32,
        GIM_CheckType, /*MI*/2, /*Op*/2, /*Type*/GILLT_s32,
        GIM_RecordInsnIgnoreCopies, /*DefineMI*/3, /*MI*/0, /*OpIdx*/2, // MIs[3]
        GIM_CheckOpcode, /*MI*/3, GIMT_Encode2(TargetOpcode::G_AND),
        // MIs[3] z
        GIM_CheckIsSameOperandIgnoreCopies, /*MI*/3, /*OpIdx*/1, /*OtherMI*/2, /*OtherOpIdx*/1,
        // MIs[3] x
        GIM_CheckIsSameOperandIgnoreCopies, /*MI*/3, /*OpIdx*/2, /*OtherMI*/2, /*OtherOpIdx*/2,
        GIM_CheckCxxInsnPredicate, /*MI*/0, /*FnId*/GIMT_Encode2(GICXXPred_MI_Predicate_anonymous_22557),
        GIM_CheckIsSafeToFold, /*InsnID*/1,
        GIM_CheckIsSafeToFold, /*InsnID*/2,
        GIM_CheckIsSafeToFold, /*InsnID*/3,
        // (or:{ *:[i32] } (and:{ *:[i32] } (or:{ *:[i32] } i32:{ *:[i32] }:$z, i32:{ *:[i32] }:$x), i32:{ *:[i32] }:$y), (and:{ *:[i32] } i32:{ *:[i32] }:$z, i32:{ *:[i32] }:$x))<<P:Predicate_anonymous_22557>>  =>  (V_BFI_B32_e64:{ *:[i32] } (V_XOR_B32_e64:{ *:[i16] } (COPY_TO_REGCLASS:{ *:[i16] } VSrc_b32:{ *:[i32] }:$x, VGPR_32:{ *:[i32] }), (COPY_TO_REGCLASS:{ *:[i16] } VSrc_b32:{ *:[i32] }:$y, VGPR_32:{ *:[i32] })), (COPY_TO_REGCLASS:{ *:[i16] } VSrc_b32:{ *:[i32] }:$z, VGPR_32:{ *:[i32] }), (COPY_TO_REGCLASS:{ *:[i16] } VSrc_b32:{ *:[i32] }:$y, VGPR_32:{ *:[i32] }))
        GIR_MakeTempReg, /*TempRegID*/0, /*TypeID*/GILLT_s16,
        GIR_MakeTempReg, /*TempRegID*/1, /*TypeID*/GILLT_s16,
        GIR_MakeTempReg, /*TempRegID*/2, /*TypeID*/GILLT_s16,
        GIR_MakeTempReg, /*TempRegID*/3, /*TypeID*/GILLT_s16,
        GIR_MakeTempReg, /*TempRegID*/4, /*TypeID*/GILLT_s16,
        GIR_BuildMI, /*InsnID*/5, /*Opcode*/GIMT_Encode2(TargetOpcode::COPY),
        GIR_AddTempRegister, /*InsnID*/5, /*TempRegID*/4, /*TempRegFlags*/GIMT_Encode2(RegState::Define),
        GIR_Copy, /*NewInsnID*/5, /*OldInsnID*/1, /*OpIdx*/2, // y
        GIR_ConstrainSelectedInstOperands, /*InsnID*/5,
        GIR_BuildMI, /*InsnID*/4, /*Opcode*/GIMT_Encode2(TargetOpcode::COPY),
        GIR_AddTempRegister, /*InsnID*/4, /*TempRegID*/3, /*TempRegFlags*/GIMT_Encode2(RegState::Define),
        GIR_Copy, /*NewInsnID*/4, /*OldInsnID*/2, /*OpIdx*/1, // z
        GIR_ConstrainSelectedInstOperands, /*InsnID*/4,
        GIR_BuildMI, /*InsnID*/3, /*Opcode*/GIMT_Encode2(TargetOpcode::COPY),
        GIR_AddTempRegister, /*InsnID*/3, /*TempRegID*/2, /*TempRegFlags*/GIMT_Encode2(RegState::Define),
        GIR_Copy, /*NewInsnID*/3, /*OldInsnID*/1, /*OpIdx*/2, // y
        GIR_ConstrainSelectedInstOperands, /*InsnID*/3,
        GIR_BuildMI, /*InsnID*/2, /*Opcode*/GIMT_Encode2(TargetOpcode::COPY),
        GIR_AddTempRegister, /*InsnID*/2, /*TempRegID*/1, /*TempRegFlags*/GIMT_Encode2(RegState::Define),
        GIR_Copy, /*NewInsnID*/2, /*OldInsnID*/2, /*OpIdx*/2, // x
        GIR_ConstrainSelectedInstOperands, /*InsnID*/2,
        GIR_BuildMI, /*InsnID*/1, /*Opcode*/GIMT_Encode2(AMDGPU::V_XOR_B32_e64),
        GIR_AddTempRegister, /*InsnID*/1, /*TempRegID*/0, /*TempRegFlags*/GIMT_Encode2(RegState::Define),
        GIR_AddSimpleTempRegister, /*InsnID*/1, /*TempRegID*/1,
        GIR_AddSimpleTempRegister, /*InsnID*/1, /*TempRegID*/2,
        GIR_ConstrainSelectedInstOperands, /*InsnID*/1,
        GIR_BuildMI, /*InsnID*/0, /*Opcode*/GIMT_Encode2(AMDGPU::V_BFI_B32_e64),
        GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/0, // DstI[vdst]
        GIR_AddSimpleTempRegister, /*InsnID*/0, /*TempRegID*/0,
        GIR_AddSimpleTempRegister, /*InsnID*/0, /*TempRegID*/3,
        GIR_AddSimpleTempRegister, /*InsnID*/0, /*TempRegID*/4,
        GIR_ConstrainSelectedInstOperands, /*InsnID*/0,
        GIR_EraseFromParent, /*InsnID*/0,
        // GIR_Coverage, 9924,
        GIR_Done,
      // Label 313: @21577
      GIM_Try, /*On fail goto*//*Label 314*/ GIMT_Encode4(21761), // Rule ID 9917 //
        GIM_CheckRegBankForClass, /*MI*/0, /*Op*/0, /*RC*/GIMT_Encode2(AMDGPU::VGPR_32RegClassID),
        GIM_RecordInsnIgnoreCopies, /*DefineMI*/1, /*MI*/0, /*OpIdx*/1, // MIs[1]
        GIM_CheckOpcode, /*MI*/1, GIMT_Encode2(TargetOpcode::G_AND),
        GIM_CheckType, /*MI*/1, /*Op*/1, /*Type*/GILLT_s32,
        GIM_CheckType, /*MI*/1, /*Op*/2, /*Type*/GILLT_s32,
        GIM_RecordInsnIgnoreCopies, /*DefineMI*/2, /*MI*/1, /*OpIdx*/2, // MIs[2]
        GIM_CheckOpcode, /*MI*/2, GIMT_Encode2(TargetOpcode::G_OR),
        GIM_CheckType, /*MI*/2, /*Op*/1, /*Type*/GILLT_s32,
        GIM_CheckType, /*MI*/2, /*Op*/2, /*Type*/GILLT_s32,
        GIM_RecordInsnIgnoreCopies, /*DefineMI*/3, /*MI*/0, /*OpIdx*/2, // MIs[3]
        GIM_CheckOpcode, /*MI*/3, GIMT_Encode2(TargetOpcode::G_AND),
        // MIs[3] x
        GIM_CheckIsSameOperandIgnoreCopies, /*MI*/3, /*OpIdx*/1, /*OtherMI*/2, /*OtherOpIdx*/1,
        // MIs[3] z
        GIM_CheckIsSameOperandIgnoreCopies, /*MI*/3, /*OpIdx*/2, /*OtherMI*/2, /*OtherOpIdx*/2,
        GIM_CheckCxxInsnPredicate, /*MI*/0, /*FnId*/GIMT_Encode2(GICXXPred_MI_Predicate_anonymous_22557),
        GIM_CheckIsSafeToFold, /*InsnID*/1,
        GIM_CheckIsSafeToFold, /*InsnID*/2,
        GIM_CheckIsSafeToFold, /*InsnID*/3,
        // (or:{ *:[i32] } (and:{ *:[i32] } i32:{ *:[i32] }:$y, (or:{ *:[i32] } i32:{ *:[i32] }:$x, i32:{ *:[i32] }:$z)), (and:{ *:[i32] } i32:{ *:[i32] }:$x, i32:{ *:[i32] }:$z))<<P:Predicate_anonymous_22557>>  =>  (V_BFI_B32_e64:{ *:[i32] } (V_XOR_B32_e64:{ *:[i16] } (COPY_TO_REGCLASS:{ *:[i16] } VSrc_b32:{ *:[i32] }:$x, VGPR_32:{ *:[i32] }), (COPY_TO_REGCLASS:{ *:[i16] } VSrc_b32:{ *:[i32] }:$y, VGPR_32:{ *:[i32] })), (COPY_TO_REGCLASS:{ *:[i16] } VSrc_b32:{ *:[i32] }:$z, VGPR_32:{ *:[i32] }), (COPY_TO_REGCLASS:{ *:[i16] } VSrc_b32:{ *:[i32] }:$y, VGPR_32:{ *:[i32] }))
        GIR_MakeTempReg, /*TempRegID*/0, /*TypeID*/GILLT_s16,
        GIR_MakeTempReg, /*TempRegID*/1, /*TypeID*/GILLT_s16,
        GIR_MakeTempReg, /*TempRegID*/2, /*TypeID*/GILLT_s16,
        GIR_MakeTempReg, /*TempRegID*/3, /*TypeID*/GILLT_s16,
        GIR_MakeTempReg, /*TempRegID*/4, /*TypeID*/GILLT_s16,
        GIR_BuildMI, /*InsnID*/5, /*Opcode*/GIMT_Encode2(TargetOpcode::COPY),
        GIR_AddTempRegister, /*InsnID*/5, /*TempRegID*/4, /*TempRegFlags*/GIMT_Encode2(RegState::Define),
        GIR_Copy, /*NewInsnID*/5, /*OldInsnID*/1, /*OpIdx*/1, // y
        GIR_ConstrainSelectedInstOperands, /*InsnID*/5,
        GIR_BuildMI, /*InsnID*/4, /*Opcode*/GIMT_Encode2(TargetOpcode::COPY),
        GIR_AddTempRegister, /*InsnID*/4, /*TempRegID*/3, /*TempRegFlags*/GIMT_Encode2(RegState::Define),
        GIR_Copy, /*NewInsnID*/4, /*OldInsnID*/2, /*OpIdx*/2, // z
        GIR_ConstrainSelectedInstOperands, /*InsnID*/4,
        GIR_BuildMI, /*InsnID*/3, /*Opcode*/GIMT_Encode2(TargetOpcode::COPY),
        GIR_AddTempRegister, /*InsnID*/3, /*TempRegID*/2, /*TempRegFlags*/GIMT_Encode2(RegState::Define),
        GIR_Copy, /*NewInsnID*/3, /*OldInsnID*/1, /*OpIdx*/1, // y
        GIR_ConstrainSelectedInstOperands, /*InsnID*/3,
        GIR_BuildMI, /*InsnID*/2, /*Opcode*/GIMT_Encode2(TargetOpcode::COPY),
        GIR_AddTempRegister, /*InsnID*/2, /*TempRegID*/1, /*TempRegFlags*/GIMT_Encode2(RegState::Define),
        GIR_Copy, /*NewInsnID*/2, /*OldInsnID*/2, /*OpIdx*/1, // x
        GIR_ConstrainSelectedInstOperands, /*InsnID*/2,
        GIR_BuildMI, /*InsnID*/1, /*Opcode*/GIMT_Encode2(AMDGPU::V_XOR_B32_e64),
        GIR_AddTempRegister, /*InsnID*/1, /*TempRegID*/0, /*TempRegFlags*/GIMT_Encode2(RegState::Define),
        GIR_AddSimpleTempRegister, /*InsnID*/1, /*TempRegID*/1,
        GIR_AddSimpleTempRegister, /*InsnID*/1, /*TempRegID*/2,
        GIR_ConstrainSelectedInstOperands, /*InsnID*/1,
        GIR_BuildMI, /*InsnID*/0, /*Opcode*/GIMT_Encode2(AMDGPU::V_BFI_B32_e64),
        GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/0, // DstI[vdst]
        GIR_AddSimpleTempRegister, /*InsnID*/0, /*TempRegID*/0,
        GIR_AddSimpleTempRegister, /*InsnID*/0, /*TempRegID*/3,
        GIR_AddSimpleTempRegister, /*InsnID*/0, /*TempRegID*/4,
        GIR_ConstrainSelectedInstOperands, /*InsnID*/0,
        GIR_EraseFromParent, /*InsnID*/0,
        // GIR_Coverage, 9917,
        GIR_Done,
      // Label 314: @21761
      GIM_Try, /*On fail goto*//*Label 315*/ GIMT_Encode4(21945), // Rule ID 9918 //
        GIM_CheckRegBankForClass, /*MI*/0, /*Op*/0, /*RC*/GIMT_Encode2(AMDGPU::VGPR_32RegClassID),
        GIM_RecordInsnIgnoreCopies, /*DefineMI*/1, /*MI*/0, /*OpIdx*/1, // MIs[1]
        GIM_CheckOpcode, /*MI*/1, GIMT_Encode2(TargetOpcode::G_AND),
        GIM_CheckType, /*MI*/1, /*Op*/1, /*Type*/GILLT_s32,
        GIM_CheckType, /*MI*/1, /*Op*/2, /*Type*/GILLT_s32,
        GIM_RecordInsnIgnoreCopies, /*DefineMI*/2, /*MI*/1, /*OpIdx*/2, // MIs[2]
        GIM_CheckOpcode, /*MI*/2, GIMT_Encode2(TargetOpcode::G_OR),
        GIM_CheckType, /*MI*/2, /*Op*/1, /*Type*/GILLT_s32,
        GIM_CheckType, /*MI*/2, /*Op*/2, /*Type*/GILLT_s32,
        GIM_RecordInsnIgnoreCopies, /*DefineMI*/3, /*MI*/0, /*OpIdx*/2, // MIs[3]
        GIM_CheckOpcode, /*MI*/3, GIMT_Encode2(TargetOpcode::G_AND),
        // MIs[3] z
        GIM_CheckIsSameOperandIgnoreCopies, /*MI*/3, /*OpIdx*/1, /*OtherMI*/2, /*OtherOpIdx*/2,
        // MIs[3] x
        GIM_CheckIsSameOperandIgnoreCopies, /*MI*/3, /*OpIdx*/2, /*OtherMI*/2, /*OtherOpIdx*/1,
        GIM_CheckCxxInsnPredicate, /*MI*/0, /*FnId*/GIMT_Encode2(GICXXPred_MI_Predicate_anonymous_22557),
        GIM_CheckIsSafeToFold, /*InsnID*/1,
        GIM_CheckIsSafeToFold, /*InsnID*/2,
        GIM_CheckIsSafeToFold, /*InsnID*/3,
        // (or:{ *:[i32] } (and:{ *:[i32] } i32:{ *:[i32] }:$y, (or:{ *:[i32] } i32:{ *:[i32] }:$x, i32:{ *:[i32] }:$z)), (and:{ *:[i32] } i32:{ *:[i32] }:$z, i32:{ *:[i32] }:$x))<<P:Predicate_anonymous_22557>>  =>  (V_BFI_B32_e64:{ *:[i32] } (V_XOR_B32_e64:{ *:[i16] } (COPY_TO_REGCLASS:{ *:[i16] } VSrc_b32:{ *:[i32] }:$x, VGPR_32:{ *:[i32] }), (COPY_TO_REGCLASS:{ *:[i16] } VSrc_b32:{ *:[i32] }:$y, VGPR_32:{ *:[i32] })), (COPY_TO_REGCLASS:{ *:[i16] } VSrc_b32:{ *:[i32] }:$z, VGPR_32:{ *:[i32] }), (COPY_TO_REGCLASS:{ *:[i16] } VSrc_b32:{ *:[i32] }:$y, VGPR_32:{ *:[i32] }))
        GIR_MakeTempReg, /*TempRegID*/0, /*TypeID*/GILLT_s16,
        GIR_MakeTempReg, /*TempRegID*/1, /*TypeID*/GILLT_s16,
        GIR_MakeTempReg, /*TempRegID*/2, /*TypeID*/GILLT_s16,
        GIR_MakeTempReg, /*TempRegID*/3, /*TypeID*/GILLT_s16,
        GIR_MakeTempReg, /*TempRegID*/4, /*TypeID*/GILLT_s16,
        GIR_BuildMI, /*InsnID*/5, /*Opcode*/GIMT_Encode2(TargetOpcode::COPY),
        GIR_AddTempRegister, /*InsnID*/5, /*TempRegID*/4, /*TempRegFlags*/GIMT_Encode2(RegState::Define),
        GIR_Copy, /*NewInsnID*/5, /*OldInsnID*/1, /*OpIdx*/1, // y
        GIR_ConstrainSelectedInstOperands, /*InsnID*/5,
        GIR_BuildMI, /*InsnID*/4, /*Opcode*/GIMT_Encode2(TargetOpcode::COPY),
        GIR_AddTempRegister, /*InsnID*/4, /*TempRegID*/3, /*TempRegFlags*/GIMT_Encode2(RegState::Define),
        GIR_Copy, /*NewInsnID*/4, /*OldInsnID*/2, /*OpIdx*/2, // z
        GIR_ConstrainSelectedInstOperands, /*InsnID*/4,
        GIR_BuildMI, /*InsnID*/3, /*Opcode*/GIMT_Encode2(TargetOpcode::COPY),
        GIR_AddTempRegister, /*InsnID*/3, /*TempRegID*/2, /*TempRegFlags*/GIMT_Encode2(RegState::Define),
        GIR_Copy, /*NewInsnID*/3, /*OldInsnID*/1, /*OpIdx*/1, // y
        GIR_ConstrainSelectedInstOperands, /*InsnID*/3,
        GIR_BuildMI, /*InsnID*/2, /*Opcode*/GIMT_Encode2(TargetOpcode::COPY),
        GIR_AddTempRegister, /*InsnID*/2, /*TempRegID*/1, /*TempRegFlags*/GIMT_Encode2(RegState::Define),
        GIR_Copy, /*NewInsnID*/2, /*OldInsnID*/2, /*OpIdx*/1, // x
        GIR_ConstrainSelectedInstOperands, /*InsnID*/2,
        GIR_BuildMI, /*InsnID*/1, /*Opcode*/GIMT_Encode2(AMDGPU::V_XOR_B32_e64),
        GIR_AddTempRegister, /*InsnID*/1, /*TempRegID*/0, /*TempRegFlags*/GIMT_Encode2(RegState::Define),
        GIR_AddSimpleTempRegister, /*InsnID*/1, /*TempRegID*/1,
        GIR_AddSimpleTempRegister, /*InsnID*/1, /*TempRegID*/2,
        GIR_ConstrainSelectedInstOperands, /*InsnID*/1,
        GIR_BuildMI, /*InsnID*/0, /*Opcode*/GIMT_Encode2(AMDGPU::V_BFI_B32_e64),
        GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/0, // DstI[vdst]
        GIR_AddSimpleTempRegister, /*InsnID*/0, /*TempRegID*/0,
        GIR_AddSimpleTempRegister, /*InsnID*/0, /*TempRegID*/3,
        GIR_AddSimpleTempRegister, /*InsnID*/0, /*TempRegID*/4,
        GIR_ConstrainSelectedInstOperands, /*InsnID*/0,
        GIR_EraseFromParent, /*InsnID*/0,
        // GIR_Coverage, 9918,
        GIR_Done,
      // Label 315: @21945
      GIM_Try, /*On fail goto*//*Label 316*/ GIMT_Encode4(22129), // Rule ID 9919 //
        GIM_CheckRegBankForClass, /*MI*/0, /*Op*/0, /*RC*/GIMT_Encode2(AMDGPU::VGPR_32RegClassID),
        GIM_RecordInsnIgnoreCopies, /*DefineMI*/1, /*MI*/0, /*OpIdx*/1, // MIs[1]
        GIM_CheckOpcode, /*MI*/1, GIMT_Encode2(TargetOpcode::G_AND),
        GIM_CheckType, /*MI*/1, /*Op*/1, /*Type*/GILLT_s32,
        GIM_CheckType, /*MI*/1, /*Op*/2, /*Type*/GILLT_s32,
        GIM_RecordInsnIgnoreCopies, /*DefineMI*/2, /*MI*/1, /*OpIdx*/2, // MIs[2]
        GIM_CheckOpcode, /*MI*/2, GIMT_Encode2(TargetOpcode::G_OR),
        GIM_CheckType, /*MI*/2, /*Op*/1, /*Type*/GILLT_s32,
        GIM_CheckType, /*MI*/2, /*Op*/2, /*Type*/GILLT_s32,
        GIM_RecordInsnIgnoreCopies, /*DefineMI*/3, /*MI*/0, /*OpIdx*/2, // MIs[3]
        GIM_CheckOpcode, /*MI*/3, GIMT_Encode2(TargetOpcode::G_AND),
        // MIs[3] x
        GIM_CheckIsSameOperandIgnoreCopies, /*MI*/3, /*OpIdx*/1, /*OtherMI*/2, /*OtherOpIdx*/2,
        // MIs[3] z
        GIM_CheckIsSameOperandIgnoreCopies, /*MI*/3, /*OpIdx*/2, /*OtherMI*/2, /*OtherOpIdx*/1,
        GIM_CheckCxxInsnPredicate, /*MI*/0, /*FnId*/GIMT_Encode2(GICXXPred_MI_Predicate_anonymous_22557),
        GIM_CheckIsSafeToFold, /*InsnID*/1,
        GIM_CheckIsSafeToFold, /*InsnID*/2,
        GIM_CheckIsSafeToFold, /*InsnID*/3,
        // (or:{ *:[i32] } (and:{ *:[i32] } i32:{ *:[i32] }:$y, (or:{ *:[i32] } i32:{ *:[i32] }:$z, i32:{ *:[i32] }:$x)), (and:{ *:[i32] } i32:{ *:[i32] }:$x, i32:{ *:[i32] }:$z))<<P:Predicate_anonymous_22557>>  =>  (V_BFI_B32_e64:{ *:[i32] } (V_XOR_B32_e64:{ *:[i16] } (COPY_TO_REGCLASS:{ *:[i16] } VSrc_b32:{ *:[i32] }:$x, VGPR_32:{ *:[i32] }), (COPY_TO_REGCLASS:{ *:[i16] } VSrc_b32:{ *:[i32] }:$y, VGPR_32:{ *:[i32] })), (COPY_TO_REGCLASS:{ *:[i16] } VSrc_b32:{ *:[i32] }:$z, VGPR_32:{ *:[i32] }), (COPY_TO_REGCLASS:{ *:[i16] } VSrc_b32:{ *:[i32] }:$y, VGPR_32:{ *:[i32] }))
        GIR_MakeTempReg, /*TempRegID*/0, /*TypeID*/GILLT_s16,
        GIR_MakeTempReg, /*TempRegID*/1, /*TypeID*/GILLT_s16,
        GIR_MakeTempReg, /*TempRegID*/2, /*TypeID*/GILLT_s16,
        GIR_MakeTempReg, /*TempRegID*/3, /*TypeID*/GILLT_s16,
        GIR_MakeTempReg, /*TempRegID*/4, /*TypeID*/GILLT_s16,
        GIR_BuildMI, /*InsnID*/5, /*Opcode*/GIMT_Encode2(TargetOpcode::COPY),
        GIR_AddTempRegister, /*InsnID*/5, /*TempRegID*/4, /*TempRegFlags*/GIMT_Encode2(RegState::Define),
        GIR_Copy, /*NewInsnID*/5, /*OldInsnID*/1, /*OpIdx*/1, // y
        GIR_ConstrainSelectedInstOperands, /*InsnID*/5,
        GIR_BuildMI, /*InsnID*/4, /*Opcode*/GIMT_Encode2(TargetOpcode::COPY),
        GIR_AddTempRegister, /*InsnID*/4, /*TempRegID*/3, /*TempRegFlags*/GIMT_Encode2(RegState::Define),
        GIR_Copy, /*NewInsnID*/4, /*OldInsnID*/2, /*OpIdx*/1, // z
        GIR_ConstrainSelectedInstOperands, /*InsnID*/4,
        GIR_BuildMI, /*InsnID*/3, /*Opcode*/GIMT_Encode2(TargetOpcode::COPY),
        GIR_AddTempRegister, /*InsnID*/3, /*TempRegID*/2, /*TempRegFlags*/GIMT_Encode2(RegState::Define),
        GIR_Copy, /*NewInsnID*/3, /*OldInsnID*/1, /*OpIdx*/1, // y
        GIR_ConstrainSelectedInstOperands, /*InsnID*/3,
        GIR_BuildMI, /*InsnID*/2, /*Opcode*/GIMT_Encode2(TargetOpcode::COPY),
        GIR_AddTempRegister, /*InsnID*/2, /*TempRegID*/1, /*TempRegFlags*/GIMT_Encode2(RegState::Define),
        GIR_Copy, /*NewInsnID*/2, /*OldInsnID*/2, /*OpIdx*/2, // x
        GIR_ConstrainSelectedInstOperands, /*InsnID*/2,
        GIR_BuildMI, /*InsnID*/1, /*Opcode*/GIMT_Encode2(AMDGPU::V_XOR_B32_e64),
        GIR_AddTempRegister, /*InsnID*/1, /*TempRegID*/0, /*TempRegFlags*/GIMT_Encode2(RegState::Define),
        GIR_AddSimpleTempRegister, /*InsnID*/1, /*TempRegID*/1,
        GIR_AddSimpleTempRegister, /*InsnID*/1, /*TempRegID*/2,
        GIR_ConstrainSelectedInstOperands, /*InsnID*/1,
        GIR_BuildMI, /*InsnID*/0, /*Opcode*/GIMT_Encode2(AMDGPU::V_BFI_B32_e64),
        GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/0, // DstI[vdst]
        GIR_AddSimpleTempRegister, /*InsnID*/0, /*TempRegID*/0,
        GIR_AddSimpleTempRegister, /*InsnID*/0, /*TempRegID*/3,
        GIR_AddSimpleTempRegister, /*InsnID*/0, /*TempRegID*/4,
        GIR_ConstrainSelectedInstOperands, /*InsnID*/0,
        GIR_EraseFromParent, /*InsnID*/0,
        // GIR_Coverage, 9919,
        GIR_Done,
      // Label 316: @22129
      GIM_Try, /*On fail goto*//*Label 317*/ GIMT_Encode4(22313), // Rule ID 9920 //
        GIM_CheckRegBankForClass, /*MI*/0, /*Op*/0, /*RC*/GIMT_Encode2(AMDGPU::VGPR_32RegClassID),
        GIM_RecordInsnIgnoreCopies, /*DefineMI*/1, /*MI*/0, /*OpIdx*/1, // MIs[1]
        GIM_CheckOpcode, /*MI*/1, GIMT_Encode2(TargetOpcode::G_AND),
        GIM_CheckType, /*MI*/1, /*Op*/1, /*Type*/GILLT_s32,
        GIM_CheckType, /*MI*/1, /*Op*/2, /*Type*/GILLT_s32,
        GIM_RecordInsnIgnoreCopies, /*DefineMI*/2, /*MI*/1, /*OpIdx*/2, // MIs[2]
        GIM_CheckOpcode, /*MI*/2, GIMT_Encode2(TargetOpcode::G_OR),
        GIM_CheckType, /*MI*/2, /*Op*/1, /*Type*/GILLT_s32,
        GIM_CheckType, /*MI*/2, /*Op*/2, /*Type*/GILLT_s32,
        GIM_RecordInsnIgnoreCopies, /*DefineMI*/3, /*MI*/0, /*OpIdx*/2, // MIs[3]
        GIM_CheckOpcode, /*MI*/3, GIMT_Encode2(TargetOpcode::G_AND),
        // MIs[3] z
        GIM_CheckIsSameOperandIgnoreCopies, /*MI*/3, /*OpIdx*/1, /*OtherMI*/2, /*OtherOpIdx*/1,
        // MIs[3] x
        GIM_CheckIsSameOperandIgnoreCopies, /*MI*/3, /*OpIdx*/2, /*OtherMI*/2, /*OtherOpIdx*/2,
        GIM_CheckCxxInsnPredicate, /*MI*/0, /*FnId*/GIMT_Encode2(GICXXPred_MI_Predicate_anonymous_22557),
        GIM_CheckIsSafeToFold, /*InsnID*/1,
        GIM_CheckIsSafeToFold, /*InsnID*/2,
        GIM_CheckIsSafeToFold, /*InsnID*/3,
        // (or:{ *:[i32] } (and:{ *:[i32] } i32:{ *:[i32] }:$y, (or:{ *:[i32] } i32:{ *:[i32] }:$z, i32:{ *:[i32] }:$x)), (and:{ *:[i32] } i32:{ *:[i32] }:$z, i32:{ *:[i32] }:$x))<<P:Predicate_anonymous_22557>>  =>  (V_BFI_B32_e64:{ *:[i32] } (V_XOR_B32_e64:{ *:[i16] } (COPY_TO_REGCLASS:{ *:[i16] } VSrc_b32:{ *:[i32] }:$x, VGPR_32:{ *:[i32] }), (COPY_TO_REGCLASS:{ *:[i16] } VSrc_b32:{ *:[i32] }:$y, VGPR_32:{ *:[i32] })), (COPY_TO_REGCLASS:{ *:[i16] } VSrc_b32:{ *:[i32] }:$z, VGPR_32:{ *:[i32] }), (COPY_TO_REGCLASS:{ *:[i16] } VSrc_b32:{ *:[i32] }:$y, VGPR_32:{ *:[i32] }))
        GIR_MakeTempReg, /*TempRegID*/0, /*TypeID*/GILLT_s16,
        GIR_MakeTempReg, /*TempRegID*/1, /*TypeID*/GILLT_s16,
        GIR_MakeTempReg, /*TempRegID*/2, /*TypeID*/GILLT_s16,
        GIR_MakeTempReg, /*TempRegID*/3, /*TypeID*/GILLT_s16,
        GIR_MakeTempReg, /*TempRegID*/4, /*TypeID*/GILLT_s16,
        GIR_BuildMI, /*InsnID*/5, /*Opcode*/GIMT_Encode2(TargetOpcode::COPY),
        GIR_AddTempRegister, /*InsnID*/5, /*TempRegID*/4, /*TempRegFlags*/GIMT_Encode2(RegState::Define),
        GIR_Copy, /*NewInsnID*/5, /*OldInsnID*/1, /*OpIdx*/1, // y
        GIR_ConstrainSelectedInstOperands, /*InsnID*/5,
        GIR_BuildMI, /*InsnID*/4, /*Opcode*/GIMT_Encode2(TargetOpcode::COPY),
        GIR_AddTempRegister, /*InsnID*/4, /*TempRegID*/3, /*TempRegFlags*/GIMT_Encode2(RegState::Define),
        GIR_Copy, /*NewInsnID*/4, /*OldInsnID*/2, /*OpIdx*/1, // z
        GIR_ConstrainSelectedInstOperands, /*InsnID*/4,
        GIR_BuildMI, /*InsnID*/3, /*Opcode*/GIMT_Encode2(TargetOpcode::COPY),
        GIR_AddTempRegister, /*InsnID*/3, /*TempRegID*/2, /*TempRegFlags*/GIMT_Encode2(RegState::Define),
        GIR_Copy, /*NewInsnID*/3, /*OldInsnID*/1, /*OpIdx*/1, // y
        GIR_ConstrainSelectedInstOperands, /*InsnID*/3,
        GIR_BuildMI, /*InsnID*/2, /*Opcode*/GIMT_Encode2(TargetOpcode::COPY),
        GIR_AddTempRegister, /*InsnID*/2, /*TempRegID*/1, /*TempRegFlags*/GIMT_Encode2(RegState::Define),
        GIR_Copy, /*NewInsnID*/2, /*OldInsnID*/2, /*OpIdx*/2, // x
        GIR_ConstrainSelectedInstOperands, /*InsnID*/2,
        GIR_BuildMI, /*InsnID*/1, /*Opcode*/GIMT_Encode2(AMDGPU::V_XOR_B32_e64),
        GIR_AddTempRegister, /*InsnID*/1, /*TempRegID*/0, /*TempRegFlags*/GIMT_Encode2(RegState::Define),
        GIR_AddSimpleTempRegister, /*InsnID*/1, /*TempRegID*/1,
        GIR_AddSimpleTempRegister, /*InsnID*/1, /*TempRegID*/2,
        GIR_ConstrainSelectedInstOperands, /*InsnID*/1,
        GIR_BuildMI, /*InsnID*/0, /*Opcode*/GIMT_Encode2(AMDGPU::V_BFI_B32_e64),
        GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/0, // DstI[vdst]
        GIR_AddSimpleTempRegister, /*InsnID*/0, /*TempRegID*/0,
        GIR_AddSimpleTempRegister, /*InsnID*/0, /*TempRegID*/3,
        GIR_AddSimpleTempRegister, /*InsnID*/0, /*TempRegID*/4,
        GIR_ConstrainSelectedInstOperands, /*InsnID*/0,
        GIR_EraseFromParent, /*InsnID*/0,
        // GIR_Coverage, 9920,
        GIR_Done,
      // Label 317: @22313
      GIM_Try, /*On fail goto*//*Label 318*/ GIMT_Encode4(22497), // Rule ID 9911 //
        GIM_CheckRegBankForClass, /*MI*/0, /*Op*/0, /*RC*/GIMT_Encode2(AMDGPU::VGPR_32RegClassID),
        GIM_RecordInsnIgnoreCopies, /*DefineMI*/1, /*MI*/0, /*OpIdx*/1, // MIs[1]
        GIM_CheckOpcode, /*MI*/1, GIMT_Encode2(TargetOpcode::G_AND),
        GIM_CheckType, /*MI*/1, /*Op*/1, /*Type*/GILLT_s32,
        GIM_CheckType, /*MI*/1, /*Op*/2, /*Type*/GILLT_s32,
        GIM_RecordInsnIgnoreCopies, /*DefineMI*/2, /*MI*/0, /*OpIdx*/2, // MIs[2]
        GIM_CheckOpcode, /*MI*/2, GIMT_Encode2(TargetOpcode::G_AND),
        GIM_CheckType, /*MI*/2, /*Op*/1, /*Type*/GILLT_s32,
        GIM_CheckType, /*MI*/2, /*Op*/2, /*Type*/GILLT_s32,
        GIM_RecordInsnIgnoreCopies, /*DefineMI*/3, /*MI*/2, /*OpIdx*/1, // MIs[3]
        GIM_CheckOpcode, /*MI*/3, GIMT_Encode2(TargetOpcode::G_OR),
        // MIs[3] x
        GIM_CheckIsSameOperandIgnoreCopies, /*MI*/3, /*OpIdx*/1, /*OtherMI*/1, /*OtherOpIdx*/1,
        // MIs[3] z
        GIM_CheckIsSameOperandIgnoreCopies, /*MI*/3, /*OpIdx*/2, /*OtherMI*/1, /*OtherOpIdx*/2,
        GIM_CheckCxxInsnPredicate, /*MI*/0, /*FnId*/GIMT_Encode2(GICXXPred_MI_Predicate_anonymous_22557),
        GIM_CheckIsSafeToFold, /*InsnID*/1,
        GIM_CheckIsSafeToFold, /*InsnID*/2,
        GIM_CheckIsSafeToFold, /*InsnID*/3,
        // (or:{ *:[i32] } (and:{ *:[i32] } i32:{ *:[i32] }:$x, i32:{ *:[i32] }:$z), (and:{ *:[i32] } (or:{ *:[i32] } i32:{ *:[i32] }:$x, i32:{ *:[i32] }:$z), i32:{ *:[i32] }:$y))<<P:Predicate_anonymous_22557>>  =>  (V_BFI_B32_e64:{ *:[i32] } (V_XOR_B32_e64:{ *:[i16] } (COPY_TO_REGCLASS:{ *:[i16] } VSrc_b32:{ *:[i32] }:$x, VGPR_32:{ *:[i32] }), (COPY_TO_REGCLASS:{ *:[i16] } VSrc_b32:{ *:[i32] }:$y, VGPR_32:{ *:[i32] })), (COPY_TO_REGCLASS:{ *:[i16] } VSrc_b32:{ *:[i32] }:$z, VGPR_32:{ *:[i32] }), (COPY_TO_REGCLASS:{ *:[i16] } VSrc_b32:{ *:[i32] }:$y, VGPR_32:{ *:[i32] }))
        GIR_MakeTempReg, /*TempRegID*/0, /*TypeID*/GILLT_s16,
        GIR_MakeTempReg, /*TempRegID*/1, /*TypeID*/GILLT_s16,
        GIR_MakeTempReg, /*TempRegID*/2, /*TypeID*/GILLT_s16,
        GIR_MakeTempReg, /*TempRegID*/3, /*TypeID*/GILLT_s16,
        GIR_MakeTempReg, /*TempRegID*/4, /*TypeID*/GILLT_s16,
        GIR_BuildMI, /*InsnID*/5, /*Opcode*/GIMT_Encode2(TargetOpcode::COPY),
        GIR_AddTempRegister, /*InsnID*/5, /*TempRegID*/4, /*TempRegFlags*/GIMT_Encode2(RegState::Define),
        GIR_Copy, /*NewInsnID*/5, /*OldInsnID*/2, /*OpIdx*/2, // y
        GIR_ConstrainSelectedInstOperands, /*InsnID*/5,
        GIR_BuildMI, /*InsnID*/4, /*Opcode*/GIMT_Encode2(TargetOpcode::COPY),
        GIR_AddTempRegister, /*InsnID*/4, /*TempRegID*/3, /*TempRegFlags*/GIMT_Encode2(RegState::Define),
        GIR_Copy, /*NewInsnID*/4, /*OldInsnID*/1, /*OpIdx*/2, // z
        GIR_ConstrainSelectedInstOperands, /*InsnID*/4,
        GIR_BuildMI, /*InsnID*/3, /*Opcode*/GIMT_Encode2(TargetOpcode::COPY),
        GIR_AddTempRegister, /*InsnID*/3, /*TempRegID*/2, /*TempRegFlags*/GIMT_Encode2(RegState::Define),
        GIR_Copy, /*NewInsnID*/3, /*OldInsnID*/2, /*OpIdx*/2, // y
        GIR_ConstrainSelectedInstOperands, /*InsnID*/3,
        GIR_BuildMI, /*InsnID*/2, /*Opcode*/GIMT_Encode2(TargetOpcode::COPY),
        GIR_AddTempRegister, /*InsnID*/2, /*TempRegID*/1, /*TempRegFlags*/GIMT_Encode2(RegState::Define),
        GIR_Copy, /*NewInsnID*/2, /*OldInsnID*/1, /*OpIdx*/1, // x
        GIR_ConstrainSelectedInstOperands, /*InsnID*/2,
        GIR_BuildMI, /*InsnID*/1, /*Opcode*/GIMT_Encode2(AMDGPU::V_XOR_B32_e64),
        GIR_AddTempRegister, /*InsnID*/1, /*TempRegID*/0, /*TempRegFlags*/GIMT_Encode2(RegState::Define),
        GIR_AddSimpleTempRegister, /*InsnID*/1, /*TempRegID*/1,
        GIR_AddSimpleTempRegister, /*InsnID*/1, /*TempRegID*/2,
        GIR_ConstrainSelectedInstOperands, /*InsnID*/1,
        GIR_BuildMI, /*InsnID*/0, /*Opcode*/GIMT_Encode2(AMDGPU::V_BFI_B32_e64),
        GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/0, // DstI[vdst]
        GIR_AddSimpleTempRegister, /*InsnID*/0, /*TempRegID*/0,
        GIR_AddSimpleTempRegister, /*InsnID*/0, /*TempRegID*/3,
        GIR_AddSimpleTempRegister, /*InsnID*/0, /*TempRegID*/4,
        GIR_ConstrainSelectedInstOperands, /*InsnID*/0,
        GIR_EraseFromParent, /*InsnID*/0,
        // GIR_Coverage, 9911,
        GIR_Done,
      // Label 318: @22497
      GIM_Try, /*On fail goto*//*Label 319*/ GIMT_Encode4(22681), // Rule ID 9912 //
        GIM_CheckRegBankForClass, /*MI*/0, /*Op*/0, /*RC*/GIMT_Encode2(AMDGPU::VGPR_32RegClassID),
        GIM_RecordInsnIgnoreCopies, /*DefineMI*/1, /*MI*/0, /*OpIdx*/1, // MIs[1]
        GIM_CheckOpcode, /*MI*/1, GIMT_Encode2(TargetOpcode::G_AND),
        GIM_CheckType, /*MI*/1, /*Op*/1, /*Type*/GILLT_s32,
        GIM_CheckType, /*MI*/1, /*Op*/2, /*Type*/GILLT_s32,
        GIM_RecordInsnIgnoreCopies, /*DefineMI*/2, /*MI*/0, /*OpIdx*/2, // MIs[2]
        GIM_CheckOpcode, /*MI*/2, GIMT_Encode2(TargetOpcode::G_AND),
        GIM_CheckType, /*MI*/2, /*Op*/1, /*Type*/GILLT_s32,
        GIM_CheckType, /*MI*/2, /*Op*/2, /*Type*/GILLT_s32,
        GIM_RecordInsnIgnoreCopies, /*DefineMI*/3, /*MI*/2, /*OpIdx*/1, // MIs[3]
        GIM_CheckOpcode, /*MI*/3, GIMT_Encode2(TargetOpcode::G_OR),
        // MIs[3] z
        GIM_CheckIsSameOperandIgnoreCopies, /*MI*/3, /*OpIdx*/1, /*OtherMI*/1, /*OtherOpIdx*/2,
        // MIs[3] x
        GIM_CheckIsSameOperandIgnoreCopies, /*MI*/3, /*OpIdx*/2, /*OtherMI*/1, /*OtherOpIdx*/1,
        GIM_CheckCxxInsnPredicate, /*MI*/0, /*FnId*/GIMT_Encode2(GICXXPred_MI_Predicate_anonymous_22557),
        GIM_CheckIsSafeToFold, /*InsnID*/1,
        GIM_CheckIsSafeToFold, /*InsnID*/2,
        GIM_CheckIsSafeToFold, /*InsnID*/3,
        // (or:{ *:[i32] } (and:{ *:[i32] } i32:{ *:[i32] }:$x, i32:{ *:[i32] }:$z), (and:{ *:[i32] } (or:{ *:[i32] } i32:{ *:[i32] }:$z, i32:{ *:[i32] }:$x), i32:{ *:[i32] }:$y))<<P:Predicate_anonymous_22557>>  =>  (V_BFI_B32_e64:{ *:[i32] } (V_XOR_B32_e64:{ *:[i16] } (COPY_TO_REGCLASS:{ *:[i16] } VSrc_b32:{ *:[i32] }:$x, VGPR_32:{ *:[i32] }), (COPY_TO_REGCLASS:{ *:[i16] } VSrc_b32:{ *:[i32] }:$y, VGPR_32:{ *:[i32] })), (COPY_TO_REGCLASS:{ *:[i16] } VSrc_b32:{ *:[i32] }:$z, VGPR_32:{ *:[i32] }), (COPY_TO_REGCLASS:{ *:[i16] } VSrc_b32:{ *:[i32] }:$y, VGPR_32:{ *:[i32] }))
        GIR_MakeTempReg, /*TempRegID*/0, /*TypeID*/GILLT_s16,
        GIR_MakeTempReg, /*TempRegID*/1, /*TypeID*/GILLT_s16,
        GIR_MakeTempReg, /*TempRegID*/2, /*TypeID*/GILLT_s16,
        GIR_MakeTempReg, /*TempRegID*/3, /*TypeID*/GILLT_s16,
        GIR_MakeTempReg, /*TempRegID*/4, /*TypeID*/GILLT_s16,
        GIR_BuildMI, /*InsnID*/5, /*Opcode*/GIMT_Encode2(TargetOpcode::COPY),
        GIR_AddTempRegister, /*InsnID*/5, /*TempRegID*/4, /*TempRegFlags*/GIMT_Encode2(RegState::Define),
        GIR_Copy, /*NewInsnID*/5, /*OldInsnID*/2, /*OpIdx*/2, // y
        GIR_ConstrainSelectedInstOperands, /*InsnID*/5,
        GIR_BuildMI, /*InsnID*/4, /*Opcode*/GIMT_Encode2(TargetOpcode::COPY),
        GIR_AddTempRegister, /*InsnID*/4, /*TempRegID*/3, /*TempRegFlags*/GIMT_Encode2(RegState::Define),
        GIR_Copy, /*NewInsnID*/4, /*OldInsnID*/1, /*OpIdx*/2, // z
        GIR_ConstrainSelectedInstOperands, /*InsnID*/4,
        GIR_BuildMI, /*InsnID*/3, /*Opcode*/GIMT_Encode2(TargetOpcode::COPY),
        GIR_AddTempRegister, /*InsnID*/3, /*TempRegID*/2, /*TempRegFlags*/GIMT_Encode2(RegState::Define),
        GIR_Copy, /*NewInsnID*/3, /*OldInsnID*/2, /*OpIdx*/2, // y
        GIR_ConstrainSelectedInstOperands, /*InsnID*/3,
        GIR_BuildMI, /*InsnID*/2, /*Opcode*/GIMT_Encode2(TargetOpcode::COPY),
        GIR_AddTempRegister, /*InsnID*/2, /*TempRegID*/1, /*TempRegFlags*/GIMT_Encode2(RegState::Define),
        GIR_Copy, /*NewInsnID*/2, /*OldInsnID*/1, /*OpIdx*/1, // x
        GIR_ConstrainSelectedInstOperands, /*InsnID*/2,
        GIR_BuildMI, /*InsnID*/1, /*Opcode*/GIMT_Encode2(AMDGPU::V_XOR_B32_e64),
        GIR_AddTempRegister, /*InsnID*/1, /*TempRegID*/0, /*TempRegFlags*/GIMT_Encode2(RegState::Define),
        GIR_AddSimpleTempRegister, /*InsnID*/1, /*TempRegID*/1,
        GIR_AddSimpleTempRegister, /*InsnID*/1, /*TempRegID*/2,
        GIR_ConstrainSelectedInstOperands, /*InsnID*/1,
        GIR_BuildMI, /*InsnID*/0, /*Opcode*/GIMT_Encode2(AMDGPU::V_BFI_B32_e64),
        GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/0, // DstI[vdst]
        GIR_AddSimpleTempRegister, /*InsnID*/0, /*TempRegID*/0,
        GIR_AddSimpleTempRegister, /*InsnID*/0, /*TempRegID*/3,
        GIR_AddSimpleTempRegister, /*InsnID*/0, /*TempRegID*/4,
        GIR_ConstrainSelectedInstOperands, /*InsnID*/0,
        GIR_EraseFromParent, /*InsnID*/0,
        // GIR_Coverage, 9912,
        GIR_Done,
      // Label 319: @22681
      GIM_Try, /*On fail goto*//*Label 320*/ GIMT_Encode4(22865), // Rule ID 9915 //
        GIM_CheckRegBankForClass, /*MI*/0, /*Op*/0, /*RC*/GIMT_Encode2(AMDGPU::VGPR_32RegClassID),
        GIM_RecordInsnIgnoreCopies, /*DefineMI*/1, /*MI*/0, /*OpIdx*/1, // MIs[1]
        GIM_CheckOpcode, /*MI*/1, GIMT_Encode2(TargetOpcode::G_AND),
        GIM_CheckType, /*MI*/1, /*Op*/1, /*Type*/GILLT_s32,
        GIM_CheckType, /*MI*/1, /*Op*/2, /*Type*/GILLT_s32,
        GIM_RecordInsnIgnoreCopies, /*DefineMI*/2, /*MI*/0, /*OpIdx*/2, // MIs[2]
        GIM_CheckOpcode, /*MI*/2, GIMT_Encode2(TargetOpcode::G_AND),
        GIM_CheckType, /*MI*/2, /*Op*/1, /*Type*/GILLT_s32,
        GIM_CheckType, /*MI*/2, /*Op*/2, /*Type*/GILLT_s32,
        GIM_RecordInsnIgnoreCopies, /*DefineMI*/3, /*MI*/2, /*OpIdx*/1, // MIs[3]
        GIM_CheckOpcode, /*MI*/3, GIMT_Encode2(TargetOpcode::G_OR),
        // MIs[3] x
        GIM_CheckIsSameOperandIgnoreCopies, /*MI*/3, /*OpIdx*/1, /*OtherMI*/1, /*OtherOpIdx*/2,
        // MIs[3] z
        GIM_CheckIsSameOperandIgnoreCopies, /*MI*/3, /*OpIdx*/2, /*OtherMI*/1, /*OtherOpIdx*/1,
        GIM_CheckCxxInsnPredicate, /*MI*/0, /*FnId*/GIMT_Encode2(GICXXPred_MI_Predicate_anonymous_22557),
        GIM_CheckIsSafeToFold, /*InsnID*/1,
        GIM_CheckIsSafeToFold, /*InsnID*/2,
        GIM_CheckIsSafeToFold, /*InsnID*/3,
        // (or:{ *:[i32] } (and:{ *:[i32] } i32:{ *:[i32] }:$z, i32:{ *:[i32] }:$x), (and:{ *:[i32] } (or:{ *:[i32] } i32:{ *:[i32] }:$x, i32:{ *:[i32] }:$z), i32:{ *:[i32] }:$y))<<P:Predicate_anonymous_22557>>  =>  (V_BFI_B32_e64:{ *:[i32] } (V_XOR_B32_e64:{ *:[i16] } (COPY_TO_REGCLASS:{ *:[i16] } VSrc_b32:{ *:[i32] }:$x, VGPR_32:{ *:[i32] }), (COPY_TO_REGCLASS:{ *:[i16] } VSrc_b32:{ *:[i32] }:$y, VGPR_32:{ *:[i32] })), (COPY_TO_REGCLASS:{ *:[i16] } VSrc_b32:{ *:[i32] }:$z, VGPR_32:{ *:[i32] }), (COPY_TO_REGCLASS:{ *:[i16] } VSrc_b32:{ *:[i32] }:$y, VGPR_32:{ *:[i32] }))
        GIR_MakeTempReg, /*TempRegID*/0, /*TypeID*/GILLT_s16,
        GIR_MakeTempReg, /*TempRegID*/1, /*TypeID*/GILLT_s16,
        GIR_MakeTempReg, /*TempRegID*/2, /*TypeID*/GILLT_s16,
        GIR_MakeTempReg, /*TempRegID*/3, /*TypeID*/GILLT_s16,
        GIR_MakeTempReg, /*TempRegID*/4, /*TypeID*/GILLT_s16,
        GIR_BuildMI, /*InsnID*/5, /*Opcode*/GIMT_Encode2(TargetOpcode::COPY),
        GIR_AddTempRegister, /*InsnID*/5, /*TempRegID*/4, /*TempRegFlags*/GIMT_Encode2(RegState::Define),
        GIR_Copy, /*NewInsnID*/5, /*OldInsnID*/2, /*OpIdx*/2, // y
        GIR_ConstrainSelectedInstOperands, /*InsnID*/5,
        GIR_BuildMI, /*InsnID*/4, /*Opcode*/GIMT_Encode2(TargetOpcode::COPY),
        GIR_AddTempRegister, /*InsnID*/4, /*TempRegID*/3, /*TempRegFlags*/GIMT_Encode2(RegState::Define),
        GIR_Copy, /*NewInsnID*/4, /*OldInsnID*/1, /*OpIdx*/1, // z
        GIR_ConstrainSelectedInstOperands, /*InsnID*/4,
        GIR_BuildMI, /*InsnID*/3, /*Opcode*/GIMT_Encode2(TargetOpcode::COPY),
        GIR_AddTempRegister, /*InsnID*/3, /*TempRegID*/2, /*TempRegFlags*/GIMT_Encode2(RegState::Define),
        GIR_Copy, /*NewInsnID*/3, /*OldInsnID*/2, /*OpIdx*/2, // y
        GIR_ConstrainSelectedInstOperands, /*InsnID*/3,
        GIR_BuildMI, /*InsnID*/2, /*Opcode*/GIMT_Encode2(TargetOpcode::COPY),
        GIR_AddTempRegister, /*InsnID*/2, /*TempRegID*/1, /*TempRegFlags*/GIMT_Encode2(RegState::Define),
        GIR_Copy, /*NewInsnID*/2, /*OldInsnID*/1, /*OpIdx*/2, // x
        GIR_ConstrainSelectedInstOperands, /*InsnID*/2,
        GIR_BuildMI, /*InsnID*/1, /*Opcode*/GIMT_Encode2(AMDGPU::V_XOR_B32_e64),
        GIR_AddTempRegister, /*InsnID*/1, /*TempRegID*/0, /*TempRegFlags*/GIMT_Encode2(RegState::Define),
        GIR_AddSimpleTempRegister, /*InsnID*/1, /*TempRegID*/1,
        GIR_AddSimpleTempRegister, /*InsnID*/1, /*TempRegID*/2,
        GIR_ConstrainSelectedInstOperands, /*InsnID*/1,
        GIR_BuildMI, /*InsnID*/0, /*Opcode*/GIMT_Encode2(AMDGPU::V_BFI_B32_e64),
        GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/0, // DstI[vdst]
        GIR_AddSimpleTempRegister, /*InsnID*/0, /*TempRegID*/0,
        GIR_AddSimpleTempRegister, /*InsnID*/0, /*TempRegID*/3,
        GIR_AddSimpleTempRegister, /*InsnID*/0, /*TempRegID*/4,
        GIR_ConstrainSelectedInstOperands, /*InsnID*/0,
        GIR_EraseFromParent, /*InsnID*/0,
        // GIR_Coverage, 9915,
        GIR_Done,
      // Label 320: @22865
      GIM_Try, /*On fail goto*//*Label 321*/ GIMT_Encode4(23049), // Rule ID 9916 //
        GIM_CheckRegBankForClass, /*MI*/0, /*Op*/0, /*RC*/GIMT_Encode2(AMDGPU::VGPR_32RegClassID),
        GIM_RecordInsnIgnoreCopies, /*DefineMI*/1, /*MI*/0, /*OpIdx*/1, // MIs[1]
        GIM_CheckOpcode, /*MI*/1, GIMT_Encode2(TargetOpcode::G_AND),
        GIM_CheckType, /*MI*/1, /*Op*/1, /*Type*/GILLT_s32,
        GIM_CheckType, /*MI*/1, /*Op*/2, /*Type*/GILLT_s32,
        GIM_RecordInsnIgnoreCopies, /*DefineMI*/2, /*MI*/0, /*OpIdx*/2, // MIs[2]
        GIM_CheckOpcode, /*MI*/2, GIMT_Encode2(TargetOpcode::G_AND),
        GIM_CheckType, /*MI*/2, /*Op*/1, /*Type*/GILLT_s32,
        GIM_CheckType, /*MI*/2, /*Op*/2, /*Type*/GILLT_s32,
        GIM_RecordInsnIgnoreCopies, /*DefineMI*/3, /*MI*/2, /*OpIdx*/1, // MIs[3]
        GIM_CheckOpcode, /*MI*/3, GIMT_Encode2(TargetOpcode::G_OR),
        // MIs[3] z
        GIM_CheckIsSameOperandIgnoreCopies, /*MI*/3, /*OpIdx*/1, /*OtherMI*/1, /*OtherOpIdx*/1,
        // MIs[3] x
        GIM_CheckIsSameOperandIgnoreCopies, /*MI*/3, /*OpIdx*/2, /*OtherMI*/1, /*OtherOpIdx*/2,
        GIM_CheckCxxInsnPredicate, /*MI*/0, /*FnId*/GIMT_Encode2(GICXXPred_MI_Predicate_anonymous_22557),
        GIM_CheckIsSafeToFold, /*InsnID*/1,
        GIM_CheckIsSafeToFold, /*InsnID*/2,
        GIM_CheckIsSafeToFold, /*InsnID*/3,
        // (or:{ *:[i32] } (and:{ *:[i32] } i32:{ *:[i32] }:$z, i32:{ *:[i32] }:$x), (and:{ *:[i32] } (or:{ *:[i32] } i32:{ *:[i32] }:$z, i32:{ *:[i32] }:$x), i32:{ *:[i32] }:$y))<<P:Predicate_anonymous_22557>>  =>  (V_BFI_B32_e64:{ *:[i32] } (V_XOR_B32_e64:{ *:[i16] } (COPY_TO_REGCLASS:{ *:[i16] } VSrc_b32:{ *:[i32] }:$x, VGPR_32:{ *:[i32] }), (COPY_TO_REGCLASS:{ *:[i16] } VSrc_b32:{ *:[i32] }:$y, VGPR_32:{ *:[i32] })), (COPY_TO_REGCLASS:{ *:[i16] } VSrc_b32:{ *:[i32] }:$z, VGPR_32:{ *:[i32] }), (COPY_TO_REGCLASS:{ *:[i16] } VSrc_b32:{ *:[i32] }:$y, VGPR_32:{ *:[i32] }))
        GIR_MakeTempReg, /*TempRegID*/0, /*TypeID*/GILLT_s16,
        GIR_MakeTempReg, /*TempRegID*/1, /*TypeID*/GILLT_s16,
        GIR_MakeTempReg, /*TempRegID*/2, /*TypeID*/GILLT_s16,
        GIR_MakeTempReg, /*TempRegID*/3, /*TypeID*/GILLT_s16,
        GIR_MakeTempReg, /*TempRegID*/4, /*TypeID*/GILLT_s16,
        GIR_BuildMI, /*InsnID*/5, /*Opcode*/GIMT_Encode2(TargetOpcode::COPY),
        GIR_AddTempRegister, /*InsnID*/5, /*TempRegID*/4, /*TempRegFlags*/GIMT_Encode2(RegState::Define),
        GIR_Copy, /*NewInsnID*/5, /*OldInsnID*/2, /*OpIdx*/2, // y
        GIR_ConstrainSelectedInstOperands, /*InsnID*/5,
        GIR_BuildMI, /*InsnID*/4, /*Opcode*/GIMT_Encode2(TargetOpcode::COPY),
        GIR_AddTempRegister, /*InsnID*/4, /*TempRegID*/3, /*TempRegFlags*/GIMT_Encode2(RegState::Define),
        GIR_Copy, /*NewInsnID*/4, /*OldInsnID*/1, /*OpIdx*/1, // z
        GIR_ConstrainSelectedInstOperands, /*InsnID*/4,
        GIR_BuildMI, /*InsnID*/3, /*Opcode*/GIMT_Encode2(TargetOpcode::COPY),
        GIR_AddTempRegister, /*InsnID*/3, /*TempRegID*/2, /*TempRegFlags*/GIMT_Encode2(RegState::Define),
        GIR_Copy, /*NewInsnID*/3, /*OldInsnID*/2, /*OpIdx*/2, // y
        GIR_ConstrainSelectedInstOperands, /*InsnID*/3,
        GIR_BuildMI, /*InsnID*/2, /*Opcode*/GIMT_Encode2(TargetOpcode::COPY),
        GIR_AddTempRegister, /*InsnID*/2, /*TempRegID*/1, /*TempRegFlags*/GIMT_Encode2(RegState::Define),
        GIR_Copy, /*NewInsnID*/2, /*OldInsnID*/1, /*OpIdx*/2, // x
        GIR_ConstrainSelectedInstOperands, /*InsnID*/2,
        GIR_BuildMI, /*InsnID*/1, /*Opcode*/GIMT_Encode2(AMDGPU::V_XOR_B32_e64),
        GIR_AddTempRegister, /*InsnID*/1, /*TempRegID*/0, /*TempRegFlags*/GIMT_Encode2(RegState::Define),
        GIR_AddSimpleTempRegister, /*InsnID*/1, /*TempRegID*/1,
        GIR_AddSimpleTempRegister, /*InsnID*/1, /*TempRegID*/2,
        GIR_ConstrainSelectedInstOperands, /*InsnID*/1,
        GIR_BuildMI, /*InsnID*/0, /*Opcode*/GIMT_Encode2(AMDGPU::V_BFI_B32_e64),
        GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/0, // DstI[vdst]
        GIR_AddSimpleTempRegister, /*InsnID*/0, /*TempRegID*/0,
        GIR_AddSimpleTempRegister, /*InsnID*/0, /*TempRegID*/3,
        GIR_AddSimpleTempRegister, /*InsnID*/0, /*TempRegID*/4,
        GIR_ConstrainSelectedInstOperands, /*InsnID*/0,
        GIR_EraseFromParent, /*InsnID*/0,
        // GIR_Coverage, 9916,
        GIR_Done,
      // Label 321: @23049
      GIM_Try, /*On fail goto*//*Label 322*/ GIMT_Encode4(23233), // Rule ID 6476 //
        GIM_CheckRegBankForClass, /*MI*/0, /*Op*/0, /*RC*/GIMT_Encode2(AMDGPU::VGPR_32RegClassID),
        GIM_RecordInsnIgnoreCopies, /*DefineMI*/1, /*MI*/0, /*OpIdx*/1, // MIs[1]
        GIM_CheckOpcode, /*MI*/1, GIMT_Encode2(TargetOpcode::G_AND),
        GIM_CheckType, /*MI*/1, /*Op*/1, /*Type*/GILLT_s32,
        GIM_CheckType, /*MI*/1, /*Op*/2, /*Type*/GILLT_s32,
        GIM_RecordInsnIgnoreCopies, /*DefineMI*/2, /*MI*/0, /*OpIdx*/2, // MIs[2]
        GIM_CheckOpcode, /*MI*/2, GIMT_Encode2(TargetOpcode::G_AND),
        GIM_CheckType, /*MI*/2, /*Op*/1, /*Type*/GILLT_s32,
        GIM_CheckType, /*MI*/2, /*Op*/2, /*Type*/GILLT_s32,
        GIM_RecordInsnIgnoreCopies, /*DefineMI*/3, /*MI*/2, /*OpIdx*/2, // MIs[3]
        GIM_CheckOpcode, /*MI*/3, GIMT_Encode2(TargetOpcode::G_OR),
        // MIs[3] x
        GIM_CheckIsSameOperandIgnoreCopies, /*MI*/3, /*OpIdx*/1, /*OtherMI*/1, /*OtherOpIdx*/1,
        // MIs[3] z
        GIM_CheckIsSameOperandIgnoreCopies, /*MI*/3, /*OpIdx*/2, /*OtherMI*/1, /*OtherOpIdx*/2,
        GIM_CheckCxxInsnPredicate, /*MI*/0, /*FnId*/GIMT_Encode2(GICXXPred_MI_Predicate_anonymous_22557),
        GIM_CheckIsSafeToFold, /*InsnID*/1,
        GIM_CheckIsSafeToFold, /*InsnID*/2,
        GIM_CheckIsSafeToFold, /*InsnID*/3,
        // (or:{ *:[i32] } (and:{ *:[i32] } i32:{ *:[i32] }:$x, i32:{ *:[i32] }:$z), (and:{ *:[i32] } i32:{ *:[i32] }:$y, (or:{ *:[i32] } i32:{ *:[i32] }:$x, i32:{ *:[i32] }:$z)))<<P:Predicate_anonymous_22557>>  =>  (V_BFI_B32_e64:{ *:[i32] } (V_XOR_B32_e64:{ *:[i16] } (COPY_TO_REGCLASS:{ *:[i16] } VSrc_b32:{ *:[i32] }:$x, VGPR_32:{ *:[i32] }), (COPY_TO_REGCLASS:{ *:[i16] } VSrc_b32:{ *:[i32] }:$y, VGPR_32:{ *:[i32] })), (COPY_TO_REGCLASS:{ *:[i16] } VSrc_b32:{ *:[i32] }:$z, VGPR_32:{ *:[i32] }), (COPY_TO_REGCLASS:{ *:[i16] } VSrc_b32:{ *:[i32] }:$y, VGPR_32:{ *:[i32] }))
        GIR_MakeTempReg, /*TempRegID*/0, /*TypeID*/GILLT_s16,
        GIR_MakeTempReg, /*TempRegID*/1, /*TypeID*/GILLT_s16,
        GIR_MakeTempReg, /*TempRegID*/2, /*TypeID*/GILLT_s16,
        GIR_MakeTempReg, /*TempRegID*/3, /*TypeID*/GILLT_s16,
        GIR_MakeTempReg, /*TempRegID*/4, /*TypeID*/GILLT_s16,
        GIR_BuildMI, /*InsnID*/5, /*Opcode*/GIMT_Encode2(TargetOpcode::COPY),
        GIR_AddTempRegister, /*InsnID*/5, /*TempRegID*/4, /*TempRegFlags*/GIMT_Encode2(RegState::Define),
        GIR_Copy, /*NewInsnID*/5, /*OldInsnID*/2, /*OpIdx*/1, // y
        GIR_ConstrainSelectedInstOperands, /*InsnID*/5,
        GIR_BuildMI, /*InsnID*/4, /*Opcode*/GIMT_Encode2(TargetOpcode::COPY),
        GIR_AddTempRegister, /*InsnID*/4, /*TempRegID*/3, /*TempRegFlags*/GIMT_Encode2(RegState::Define),
        GIR_Copy, /*NewInsnID*/4, /*OldInsnID*/1, /*OpIdx*/2, // z
        GIR_ConstrainSelectedInstOperands, /*InsnID*/4,
        GIR_BuildMI, /*InsnID*/3, /*Opcode*/GIMT_Encode2(TargetOpcode::COPY),
        GIR_AddTempRegister, /*InsnID*/3, /*TempRegID*/2, /*TempRegFlags*/GIMT_Encode2(RegState::Define),
        GIR_Copy, /*NewInsnID*/3, /*OldInsnID*/2, /*OpIdx*/1, // y
        GIR_ConstrainSelectedInstOperands, /*InsnID*/3,
        GIR_BuildMI, /*InsnID*/2, /*Opcode*/GIMT_Encode2(TargetOpcode::COPY),
        GIR_AddTempRegister, /*InsnID*/2, /*TempRegID*/1, /*TempRegFlags*/GIMT_Encode2(RegState::Define),
        GIR_Copy, /*NewInsnID*/2, /*OldInsnID*/1, /*OpIdx*/1, // x
        GIR_ConstrainSelectedInstOperands, /*InsnID*/2,
        GIR_BuildMI, /*InsnID*/1, /*Opcode*/GIMT_Encode2(AMDGPU::V_XOR_B32_e64),
        GIR_AddTempRegister, /*InsnID*/1, /*TempRegID*/0, /*TempRegFlags*/GIMT_Encode2(RegState::Define),
        GIR_AddSimpleTempRegister, /*InsnID*/1, /*TempRegID*/1,
        GIR_AddSimpleTempRegister, /*InsnID*/1, /*TempRegID*/2,
        GIR_ConstrainSelectedInstOperands, /*InsnID*/1,
        GIR_BuildMI, /*InsnID*/0, /*Opcode*/GIMT_Encode2(AMDGPU::V_BFI_B32_e64),
        GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/0, // DstI[vdst]
        GIR_AddSimpleTempRegister, /*InsnID*/0, /*TempRegID*/0,
        GIR_AddSimpleTempRegister, /*InsnID*/0, /*TempRegID*/3,
        GIR_AddSimpleTempRegister, /*InsnID*/0, /*TempRegID*/4,
        GIR_ConstrainSelectedInstOperands, /*InsnID*/0,
        GIR_EraseFromParent, /*InsnID*/0,
        // GIR_Coverage, 6476,
        GIR_Done,
      // Label 322: @23233
      GIM_Try, /*On fail goto*//*Label 323*/ GIMT_Encode4(23417), // Rule ID 9910 //
        GIM_CheckRegBankForClass, /*MI*/0, /*Op*/0, /*RC*/GIMT_Encode2(AMDGPU::VGPR_32RegClassID),
        GIM_RecordInsnIgnoreCopies, /*DefineMI*/1, /*MI*/0, /*OpIdx*/1, // MIs[1]
        GIM_CheckOpcode, /*MI*/1, GIMT_Encode2(TargetOpcode::G_AND),
        GIM_CheckType, /*MI*/1, /*Op*/1, /*Type*/GILLT_s32,
        GIM_CheckType, /*MI*/1, /*Op*/2, /*Type*/GILLT_s32,
        GIM_RecordInsnIgnoreCopies, /*DefineMI*/2, /*MI*/0, /*OpIdx*/2, // MIs[2]
        GIM_CheckOpcode, /*MI*/2, GIMT_Encode2(TargetOpcode::G_AND),
        GIM_CheckType, /*MI*/2, /*Op*/1, /*Type*/GILLT_s32,
        GIM_CheckType, /*MI*/2, /*Op*/2, /*Type*/GILLT_s32,
        GIM_RecordInsnIgnoreCopies, /*DefineMI*/3, /*MI*/2, /*OpIdx*/2, // MIs[3]
        GIM_CheckOpcode, /*MI*/3, GIMT_Encode2(TargetOpcode::G_OR),
        // MIs[3] z
        GIM_CheckIsSameOperandIgnoreCopies, /*MI*/3, /*OpIdx*/1, /*OtherMI*/1, /*OtherOpIdx*/2,
        // MIs[3] x
        GIM_CheckIsSameOperandIgnoreCopies, /*MI*/3, /*OpIdx*/2, /*OtherMI*/1, /*OtherOpIdx*/1,
        GIM_CheckCxxInsnPredicate, /*MI*/0, /*FnId*/GIMT_Encode2(GICXXPred_MI_Predicate_anonymous_22557),
        GIM_CheckIsSafeToFold, /*InsnID*/1,
        GIM_CheckIsSafeToFold, /*InsnID*/2,
        GIM_CheckIsSafeToFold, /*InsnID*/3,
        // (or:{ *:[i32] } (and:{ *:[i32] } i32:{ *:[i32] }:$x, i32:{ *:[i32] }:$z), (and:{ *:[i32] } i32:{ *:[i32] }:$y, (or:{ *:[i32] } i32:{ *:[i32] }:$z, i32:{ *:[i32] }:$x)))<<P:Predicate_anonymous_22557>>  =>  (V_BFI_B32_e64:{ *:[i32] } (V_XOR_B32_e64:{ *:[i16] } (COPY_TO_REGCLASS:{ *:[i16] } VSrc_b32:{ *:[i32] }:$x, VGPR_32:{ *:[i32] }), (COPY_TO_REGCLASS:{ *:[i16] } VSrc_b32:{ *:[i32] }:$y, VGPR_32:{ *:[i32] })), (COPY_TO_REGCLASS:{ *:[i16] } VSrc_b32:{ *:[i32] }:$z, VGPR_32:{ *:[i32] }), (COPY_TO_REGCLASS:{ *:[i16] } VSrc_b32:{ *:[i32] }:$y, VGPR_32:{ *:[i32] }))
        GIR_MakeTempReg, /*TempRegID*/0, /*TypeID*/GILLT_s16,
        GIR_MakeTempReg, /*TempRegID*/1, /*TypeID*/GILLT_s16,
        GIR_MakeTempReg, /*TempRegID*/2, /*TypeID*/GILLT_s16,
        GIR_MakeTempReg, /*TempRegID*/3, /*TypeID*/GILLT_s16,
        GIR_MakeTempReg, /*TempRegID*/4, /*TypeID*/GILLT_s16,
        GIR_BuildMI, /*InsnID*/5, /*Opcode*/GIMT_Encode2(TargetOpcode::COPY),
        GIR_AddTempRegister, /*InsnID*/5, /*TempRegID*/4, /*TempRegFlags*/GIMT_Encode2(RegState::Define),
        GIR_Copy, /*NewInsnID*/5, /*OldInsnID*/2, /*OpIdx*/1, // y
        GIR_ConstrainSelectedInstOperands, /*InsnID*/5,
        GIR_BuildMI, /*InsnID*/4, /*Opcode*/GIMT_Encode2(TargetOpcode::COPY),
        GIR_AddTempRegister, /*InsnID*/4, /*TempRegID*/3, /*TempRegFlags*/GIMT_Encode2(RegState::Define),
        GIR_Copy, /*NewInsnID*/4, /*OldInsnID*/1, /*OpIdx*/2, // z
        GIR_ConstrainSelectedInstOperands, /*InsnID*/4,
        GIR_BuildMI, /*InsnID*/3, /*Opcode*/GIMT_Encode2(TargetOpcode::COPY),
        GIR_AddTempRegister, /*InsnID*/3, /*TempRegID*/2, /*TempRegFlags*/GIMT_Encode2(RegState::Define),
        GIR_Copy, /*NewInsnID*/3, /*OldInsnID*/2, /*OpIdx*/1, // y
        GIR_ConstrainSelectedInstOperands, /*InsnID*/3,
        GIR_BuildMI, /*InsnID*/2, /*Opcode*/GIMT_Encode2(TargetOpcode::COPY),
        GIR_AddTempRegister, /*InsnID*/2, /*TempRegID*/1, /*TempRegFlags*/GIMT_Encode2(RegState::Define),
        GIR_Copy, /*NewInsnID*/2, /*OldInsnID*/1, /*OpIdx*/1, // x
        GIR_ConstrainSelectedInstOperands, /*InsnID*/2,
        GIR_BuildMI, /*InsnID*/1, /*Opcode*/GIMT_Encode2(AMDGPU::V_XOR_B32_e64),
        GIR_AddTempRegister, /*InsnID*/1, /*TempRegID*/0, /*TempRegFlags*/GIMT_Encode2(RegState::Define),
        GIR_AddSimpleTempRegister, /*InsnID*/1, /*TempRegID*/1,
        GIR_AddSimpleTempRegister, /*InsnID*/1, /*TempRegID*/2,
        GIR_ConstrainSelectedInstOperands, /*InsnID*/1,
        GIR_BuildMI, /*InsnID*/0, /*Opcode*/GIMT_Encode2(AMDGPU::V_BFI_B32_e64),
        GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/0, // DstI[vdst]
        GIR_AddSimpleTempRegister, /*InsnID*/0, /*TempRegID*/0,
        GIR_AddSimpleTempRegister, /*InsnID*/0, /*TempRegID*/3,
        GIR_AddSimpleTempRegister, /*InsnID*/0, /*TempRegID*/4,
        GIR_ConstrainSelectedInstOperands, /*InsnID*/0,
        GIR_EraseFromParent, /*InsnID*/0,
        // GIR_Coverage, 9910,
        GIR_Done,
      // Label 323: @23417
      GIM_Try, /*On fail goto*//*Label 324*/ GIMT_Encode4(23601), // Rule ID 9913 //
        GIM_CheckRegBankForClass, /*MI*/0, /*Op*/0, /*RC*/GIMT_Encode2(AMDGPU::VGPR_32RegClassID),
        GIM_RecordInsnIgnoreCopies, /*DefineMI*/1, /*MI*/0, /*OpIdx*/1, // MIs[1]
        GIM_CheckOpcode, /*MI*/1, GIMT_Encode2(TargetOpcode::G_AND),
        GIM_CheckType, /*MI*/1, /*Op*/1, /*Type*/GILLT_s32,
        GIM_CheckType, /*MI*/1, /*Op*/2, /*Type*/GILLT_s32,
        GIM_RecordInsnIgnoreCopies, /*DefineMI*/2, /*MI*/0, /*OpIdx*/2, // MIs[2]
        GIM_CheckOpcode, /*MI*/2, GIMT_Encode2(TargetOpcode::G_AND),
        GIM_CheckType, /*MI*/2, /*Op*/1, /*Type*/GILLT_s32,
        GIM_CheckType, /*MI*/2, /*Op*/2, /*Type*/GILLT_s32,
        GIM_RecordInsnIgnoreCopies, /*DefineMI*/3, /*MI*/2, /*OpIdx*/2, // MIs[3]
        GIM_CheckOpcode, /*MI*/3, GIMT_Encode2(TargetOpcode::G_OR),
        // MIs[3] x
        GIM_CheckIsSameOperandIgnoreCopies, /*MI*/3, /*OpIdx*/1, /*OtherMI*/1, /*OtherOpIdx*/2,
        // MIs[3] z
        GIM_CheckIsSameOperandIgnoreCopies, /*MI*/3, /*OpIdx*/2, /*OtherMI*/1, /*OtherOpIdx*/1,
        GIM_CheckCxxInsnPredicate, /*MI*/0, /*FnId*/GIMT_Encode2(GICXXPred_MI_Predicate_anonymous_22557),
        GIM_CheckIsSafeToFold, /*InsnID*/1,
        GIM_CheckIsSafeToFold, /*InsnID*/2,
        GIM_CheckIsSafeToFold, /*InsnID*/3,
        // (or:{ *:[i32] } (and:{ *:[i32] } i32:{ *:[i32] }:$z, i32:{ *:[i32] }:$x), (and:{ *:[i32] } i32:{ *:[i32] }:$y, (or:{ *:[i32] } i32:{ *:[i32] }:$x, i32:{ *:[i32] }:$z)))<<P:Predicate_anonymous_22557>>  =>  (V_BFI_B32_e64:{ *:[i32] } (V_XOR_B32_e64:{ *:[i16] } (COPY_TO_REGCLASS:{ *:[i16] } VSrc_b32:{ *:[i32] }:$x, VGPR_32:{ *:[i32] }), (COPY_TO_REGCLASS:{ *:[i16] } VSrc_b32:{ *:[i32] }:$y, VGPR_32:{ *:[i32] })), (COPY_TO_REGCLASS:{ *:[i16] } VSrc_b32:{ *:[i32] }:$z, VGPR_32:{ *:[i32] }), (COPY_TO_REGCLASS:{ *:[i16] } VSrc_b32:{ *:[i32] }:$y, VGPR_32:{ *:[i32] }))
        GIR_MakeTempReg, /*TempRegID*/0, /*TypeID*/GILLT_s16,
        GIR_MakeTempReg, /*TempRegID*/1, /*TypeID*/GILLT_s16,
        GIR_MakeTempReg, /*TempRegID*/2, /*TypeID*/GILLT_s16,
        GIR_MakeTempReg, /*TempRegID*/3, /*TypeID*/GILLT_s16,
        GIR_MakeTempReg, /*TempRegID*/4, /*TypeID*/GILLT_s16,
        GIR_BuildMI, /*InsnID*/5, /*Opcode*/GIMT_Encode2(TargetOpcode::COPY),
        GIR_AddTempRegister, /*InsnID*/5, /*TempRegID*/4, /*TempRegFlags*/GIMT_Encode2(RegState::Define),
        GIR_Copy, /*NewInsnID*/5, /*OldInsnID*/2, /*OpIdx*/1, // y
        GIR_ConstrainSelectedInstOperands, /*InsnID*/5,
        GIR_BuildMI, /*InsnID*/4, /*Opcode*/GIMT_Encode2(TargetOpcode::COPY),
        GIR_AddTempRegister, /*InsnID*/4, /*TempRegID*/3, /*TempRegFlags*/GIMT_Encode2(RegState::Define),
        GIR_Copy, /*NewInsnID*/4, /*OldInsnID*/1, /*OpIdx*/1, // z
        GIR_ConstrainSelectedInstOperands, /*InsnID*/4,
        GIR_BuildMI, /*InsnID*/3, /*Opcode*/GIMT_Encode2(TargetOpcode::COPY),
        GIR_AddTempRegister, /*InsnID*/3, /*TempRegID*/2, /*TempRegFlags*/GIMT_Encode2(RegState::Define),
        GIR_Copy, /*NewInsnID*/3, /*OldInsnID*/2, /*OpIdx*/1, // y
        GIR_ConstrainSelectedInstOperands, /*InsnID*/3,
        GIR_BuildMI, /*InsnID*/2, /*Opcode*/GIMT_Encode2(TargetOpcode::COPY),
        GIR_AddTempRegister, /*InsnID*/2, /*TempRegID*/1, /*TempRegFlags*/GIMT_Encode2(RegState::Define),
        GIR_Copy, /*NewInsnID*/2, /*OldInsnID*/1, /*OpIdx*/2, // x
        GIR_ConstrainSelectedInstOperands, /*InsnID*/2,
        GIR_BuildMI, /*InsnID*/1, /*Opcode*/GIMT_Encode2(AMDGPU::V_XOR_B32_e64),
        GIR_AddTempRegister, /*InsnID*/1, /*TempRegID*/0, /*TempRegFlags*/GIMT_Encode2(RegState::Define),
        GIR_AddSimpleTempRegister, /*InsnID*/1, /*TempRegID*/1,
        GIR_AddSimpleTempRegister, /*InsnID*/1, /*TempRegID*/2,
        GIR_ConstrainSelectedInstOperands, /*InsnID*/1,
        GIR_BuildMI, /*InsnID*/0, /*Opcode*/GIMT_Encode2(AMDGPU::V_BFI_B32_e64),
        GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/0, // DstI[vdst]
        GIR_AddSimpleTempRegister, /*InsnID*/0, /*TempRegID*/0,
        GIR_AddSimpleTempRegister, /*InsnID*/0, /*TempRegID*/3,
        GIR_AddSimpleTempRegister, /*InsnID*/0, /*TempRegID*/4,
        GIR_ConstrainSelectedInstOperands, /*InsnID*/0,
        GIR_EraseFromParent, /*InsnID*/0,
        // GIR_Coverage, 9913,
        GIR_Done,
      // Label 324: @23601
      GIM_Try, /*On fail goto*//*Label 325*/ GIMT_Encode4(23785), // Rule ID 9914 //
        GIM_CheckRegBankForClass, /*MI*/0, /*Op*/0, /*RC*/GIMT_Encode2(AMDGPU::VGPR_32RegClassID),
        GIM_RecordInsnIgnoreCopies, /*DefineMI*/1, /*MI*/0, /*OpIdx*/1, // MIs[1]
        GIM_CheckOpcode, /*MI*/1, GIMT_Encode2(TargetOpcode::G_AND),
        GIM_CheckType, /*MI*/1, /*Op*/1, /*Type*/GILLT_s32,
        GIM_CheckType, /*MI*/1, /*Op*/2, /*Type*/GILLT_s32,
        GIM_RecordInsnIgnoreCopies, /*DefineMI*/2, /*MI*/0, /*OpIdx*/2, // MIs[2]
        GIM_CheckOpcode, /*MI*/2, GIMT_Encode2(TargetOpcode::G_AND),
        GIM_CheckType, /*MI*/2, /*Op*/1, /*Type*/GILLT_s32,
        GIM_CheckType, /*MI*/2, /*Op*/2, /*Type*/GILLT_s32,
        GIM_RecordInsnIgnoreCopies, /*DefineMI*/3, /*MI*/2, /*OpIdx*/2, // MIs[3]
        GIM_CheckOpcode, /*MI*/3, GIMT_Encode2(TargetOpcode::G_OR),
        // MIs[3] z
        GIM_CheckIsSameOperandIgnoreCopies, /*MI*/3, /*OpIdx*/1, /*OtherMI*/1, /*OtherOpIdx*/1,
        // MIs[3] x
        GIM_CheckIsSameOperandIgnoreCopies, /*MI*/3, /*OpIdx*/2, /*OtherMI*/1, /*OtherOpIdx*/2,
        GIM_CheckCxxInsnPredicate, /*MI*/0, /*FnId*/GIMT_Encode2(GICXXPred_MI_Predicate_anonymous_22557),
        GIM_CheckIsSafeToFold, /*InsnID*/1,
        GIM_CheckIsSafeToFold, /*InsnID*/2,
        GIM_CheckIsSafeToFold, /*InsnID*/3,
        // (or:{ *:[i32] } (and:{ *:[i32] } i32:{ *:[i32] }:$z, i32:{ *:[i32] }:$x), (and:{ *:[i32] } i32:{ *:[i32] }:$y, (or:{ *:[i32] } i32:{ *:[i32] }:$z, i32:{ *:[i32] }:$x)))<<P:Predicate_anonymous_22557>>  =>  (V_BFI_B32_e64:{ *:[i32] } (V_XOR_B32_e64:{ *:[i16] } (COPY_TO_REGCLASS:{ *:[i16] } VSrc_b32:{ *:[i32] }:$x, VGPR_32:{ *:[i32] }), (COPY_TO_REGCLASS:{ *:[i16] } VSrc_b32:{ *:[i32] }:$y, VGPR_32:{ *:[i32] })), (COPY_TO_REGCLASS:{ *:[i16] } VSrc_b32:{ *:[i32] }:$z, VGPR_32:{ *:[i32] }), (COPY_TO_REGCLASS:{ *:[i16] } VSrc_b32:{ *:[i32] }:$y, VGPR_32:{ *:[i32] }))
        GIR_MakeTempReg, /*TempRegID*/0, /*TypeID*/GILLT_s16,
        GIR_MakeTempReg, /*TempRegID*/1, /*TypeID*/GILLT_s16,
        GIR_MakeTempReg, /*TempRegID*/2, /*TypeID*/GILLT_s16,
        GIR_MakeTempReg, /*TempRegID*/3, /*TypeID*/GILLT_s16,
        GIR_MakeTempReg, /*TempRegID*/4, /*TypeID*/GILLT_s16,
        GIR_BuildMI, /*InsnID*/5, /*Opcode*/GIMT_Encode2(TargetOpcode::COPY),
        GIR_AddTempRegister, /*InsnID*/5, /*TempRegID*/4, /*TempRegFlags*/GIMT_Encode2(RegState::Define),
        GIR_Copy, /*NewInsnID*/5, /*OldInsnID*/2, /*OpIdx*/1, // y
        GIR_ConstrainSelectedInstOperands, /*InsnID*/5,
        GIR_BuildMI, /*InsnID*/4, /*Opcode*/GIMT_Encode2(TargetOpcode::COPY),
        GIR_AddTempRegister, /*InsnID*/4, /*TempRegID*/3, /*TempRegFlags*/GIMT_Encode2(RegState::Define),
        GIR_Copy, /*NewInsnID*/4, /*OldInsnID*/1, /*OpIdx*/1, // z
        GIR_ConstrainSelectedInstOperands, /*InsnID*/4,
        GIR_BuildMI, /*InsnID*/3, /*Opcode*/GIMT_Encode2(TargetOpcode::COPY),
        GIR_AddTempRegister, /*InsnID*/3, /*TempRegID*/2, /*TempRegFlags*/GIMT_Encode2(RegState::Define),
        GIR_Copy, /*NewInsnID*/3, /*OldInsnID*/2, /*OpIdx*/1, // y
        GIR_ConstrainSelectedInstOperands, /*InsnID*/3,
        GIR_BuildMI, /*InsnID*/2, /*Opcode*/GIMT_Encode2(TargetOpcode::COPY),
        GIR_AddTempRegister, /*InsnID*/2, /*TempRegID*/1, /*TempRegFlags*/GIMT_Encode2(RegState::Define),
        GIR_Copy, /*NewInsnID*/2, /*OldInsnID*/1, /*OpIdx*/2, // x
        GIR_ConstrainSelectedInstOperands, /*InsnID*/2,
        GIR_BuildMI, /*InsnID*/1, /*Opcode*/GIMT_Encode2(AMDGPU::V_XOR_B32_e64),
        GIR_AddTempRegister, /*InsnID*/1, /*TempRegID*/0, /*TempRegFlags*/GIMT_Encode2(RegState::Define),
        GIR_AddSimpleTempRegister, /*InsnID*/1, /*TempRegID*/1,
        GIR_AddSimpleTempRegister, /*InsnID*/1, /*TempRegID*/2,
        GIR_ConstrainSelectedInstOperands, /*InsnID*/1,
        GIR_BuildMI, /*InsnID*/0, /*Opcode*/GIMT_Encode2(AMDGPU::V_BFI_B32_e64),
        GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/0, // DstI[vdst]
        GIR_AddSimpleTempRegister, /*InsnID*/0, /*TempRegID*/0,
        GIR_AddSimpleTempRegister, /*InsnID*/0, /*TempRegID*/3,
        GIR_AddSimpleTempRegister, /*InsnID*/0, /*TempRegID*/4,
        GIR_ConstrainSelectedInstOperands, /*InsnID*/0,
        GIR_EraseFromParent, /*InsnID*/0,
        // GIR_Coverage, 9914,
        GIR_Done,
      // Label 325: @23785
      GIM_Try, /*On fail goto*//*Label 326*/ GIMT_Encode4(23849), // Rule ID 7118 //
        GIM_CheckRegBankForClass, /*MI*/0, /*Op*/0, /*RC*/GIMT_Encode2(AMDGPU::SReg_32RegClassID),
        GIM_RecordInsn, /*DefineMI*/1, /*MI*/0, /*OpIdx*/1, // MIs[1]
        GIM_CheckOpcode, /*MI*/1, GIMT_Encode2(TargetOpcode::G_XOR),
        GIM_CheckType, /*MI*/1, /*Op*/1, /*Type*/GILLT_s32,
        GIM_CheckType, /*MI*/1, /*Op*/2, /*Type*/GILLT_s32,
        GIM_CheckConstantInt8, /*MI*/1, /*Op*/2, uint8_t(-1),
        GIM_CheckCxxInsnPredicate, /*MI*/1, /*FnId*/GIMT_Encode2(GICXXPred_MI_Predicate_anonymous_17562),
        GIM_CheckCxxInsnPredicate, /*MI*/0, /*FnId*/GIMT_Encode2(GICXXPred_MI_Predicate_anonymous_17616),
        GIM_CheckIsSafeToFold, /*InsnID*/1,
        // (or:{ *:[i32] } (xor:{ *:[i32] } i32:{ *:[i32] }:$src1, -1:{ *:[i32] })<<P:Predicate_anonymous_17562>>, i32:{ *:[i32] }:$src0)<<P:Predicate_anonymous_17616>>  =>  (S_ORN2_B32:{ *:[i32] }:{ *:[i1] } i32:{ *:[i32] }:$src0, i32:{ *:[i32] }:$src1)
        GIR_BuildMI, /*InsnID*/0, /*Opcode*/GIMT_Encode2(AMDGPU::S_ORN2_B32),
        GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/0, // DstI[sdst]
        GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/2, // src0
        GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/1, /*OpIdx*/1, // src1
        GIR_SetImplicitDefDead, /*InsnID*/0, /*OpIdx for AMDGPU::SCC*/0,
        GIR_ConstrainSelectedInstOperands, /*InsnID*/0,
        GIR_EraseFromParent, /*InsnID*/0,
        // GIR_Coverage, 7118,
        GIR_Done,
      // Label 326: @23849
      GIM_Try, /*On fail goto*//*Label 327*/ GIMT_Encode4(23913), // Rule ID 68 //
        GIM_CheckRegBankForClass, /*MI*/0, /*Op*/0, /*RC*/GIMT_Encode2(AMDGPU::SReg_32RegClassID),
        GIM_RecordInsn, /*DefineMI*/1, /*MI*/0, /*OpIdx*/2, // MIs[1]
        GIM_CheckOpcode, /*MI*/1, GIMT_Encode2(TargetOpcode::G_XOR),
        GIM_CheckType, /*MI*/1, /*Op*/1, /*Type*/GILLT_s32,
        GIM_CheckType, /*MI*/1, /*Op*/2, /*Type*/GILLT_s32,
        GIM_CheckConstantInt8, /*MI*/1, /*Op*/2, uint8_t(-1),
        GIM_CheckCxxInsnPredicate, /*MI*/1, /*FnId*/GIMT_Encode2(GICXXPred_MI_Predicate_anonymous_17562),
        GIM_CheckCxxInsnPredicate, /*MI*/0, /*FnId*/GIMT_Encode2(GICXXPred_MI_Predicate_anonymous_17616),
        GIM_CheckIsSafeToFold, /*InsnID*/1,
        // (or:{ *:[i32] } i32:{ *:[i32] }:$src0, (xor:{ *:[i32] } i32:{ *:[i32] }:$src1, -1:{ *:[i32] })<<P:Predicate_anonymous_17562>>)<<P:Predicate_anonymous_17616>>  =>  (S_ORN2_B32:{ *:[i32] }:{ *:[i1] } i32:{ *:[i32] }:$src0, i32:{ *:[i32] }:$src1)
        GIR_BuildMI, /*InsnID*/0, /*Opcode*/GIMT_Encode2(AMDGPU::S_ORN2_B32),
        GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/0, // DstI[sdst]
        GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/1, // src0
        GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/1, /*OpIdx*/1, // src1
        GIR_SetImplicitDefDead, /*InsnID*/0, /*OpIdx for AMDGPU::SCC*/0,
        GIR_ConstrainSelectedInstOperands, /*InsnID*/0,
        GIR_EraseFromParent, /*InsnID*/0,
        // GIR_Coverage, 68,
        GIR_Done,
      // Label 327: @23913
      GIM_Try, /*On fail goto*//*Label 328*/ GIMT_Encode4(23989), // Rule ID 2192 //
        GIM_CheckFeatures, GIMT_Encode2(GIFBS_isGFX9Plus),
        GIM_CheckRegBankForClass, /*MI*/0, /*Op*/0, /*RC*/GIMT_Encode2(AMDGPU::VGPR_32RegClassID),
        GIM_RecordInsn, /*DefineMI*/1, /*MI*/0, /*OpIdx*/1, // MIs[1]
        GIM_CheckOpcode, /*MI*/1, GIMT_Encode2(TargetOpcode::G_AND),
        GIM_CheckType, /*MI*/1, /*Op*/1, /*Type*/GILLT_s32,
        GIM_CheckType, /*MI*/1, /*Op*/2, /*Type*/GILLT_s32,
        GIM_RecordNamedOperand, /*MI*/1, /*Op*/1, /*StoreIdx*/0, // Name : pred:6:x
        GIM_RecordNamedOperand, /*MI*/1, /*Op*/2, /*StoreIdx*/1, // Name : pred:6:y
        GIM_CheckCxxInsnPredicate, /*MI*/1, /*FnId*/GIMT_Encode2(GICXXPred_MI_Predicate_anonymous_23616),
        GIM_RecordNamedOperand, /*MI*/0, /*Op*/2, /*StoreIdx*/2, // Name : pred:6:z
        GIM_CheckCxxInsnPredicate, /*MI*/0, /*FnId*/GIMT_Encode2(GICXXPred_MI_Predicate_anonymous_23615),
        GIM_CheckIsSafeToFold, /*InsnID*/1,
        // (or:{ *:[i32] } (and:{ *:[i32] } i32:{ *:[i32] }:$src0:$pred:6:x, i32:{ *:[i32] }:$src1:$pred:6:y)<<P:Predicate_anonymous_23616>>, i32:{ *:[i32] }:$src2:$pred:6:z)<<P:6:Predicate_anonymous_23615>>  =>  (V_AND_OR_B32_e64:{ *:[i32] } VSrc_b32:{ *:[i32] }:$src0, VSrc_b32:{ *:[i32] }:$src1, VSrc_b32:{ *:[i32] }:$src2)
        GIR_BuildMI, /*InsnID*/0, /*Opcode*/GIMT_Encode2(AMDGPU::V_AND_OR_B32_e64),
        GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/0, // DstI[vdst]
        GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/1, /*OpIdx*/1, // src0
        GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/1, /*OpIdx*/2, // src1
        GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/2, // src2
        GIR_ConstrainSelectedInstOperands, /*InsnID*/0,
        GIR_EraseFromParent, /*InsnID*/0,
        // GIR_Coverage, 2192,
        GIR_Done,
      // Label 328: @23989
      GIM_Try, /*On fail goto*//*Label 329*/ GIMT_Encode4(24065), // Rule ID 2193 //
        GIM_CheckFeatures, GIMT_Encode2(GIFBS_isGFX9Plus),
        GIM_CheckRegBankForClass, /*MI*/0, /*Op*/0, /*RC*/GIMT_Encode2(AMDGPU::VGPR_32RegClassID),
        GIM_RecordInsn, /*DefineMI*/1, /*MI*/0, /*OpIdx*/1, // MIs[1]
        GIM_CheckOpcode, /*MI*/1, GIMT_Encode2(TargetOpcode::G_OR),
        GIM_CheckType, /*MI*/1, /*Op*/1, /*Type*/GILLT_s32,
        GIM_CheckType, /*MI*/1, /*Op*/2, /*Type*/GILLT_s32,
        GIM_RecordNamedOperand, /*MI*/1, /*Op*/1, /*StoreIdx*/0, // Name : pred:7:x
        GIM_RecordNamedOperand, /*MI*/1, /*Op*/2, /*StoreIdx*/1, // Name : pred:7:y
        GIM_CheckCxxInsnPredicate, /*MI*/1, /*FnId*/GIMT_Encode2(GICXXPred_MI_Predicate_anonymous_23619),
        GIM_RecordNamedOperand, /*MI*/0, /*Op*/2, /*StoreIdx*/2, // Name : pred:7:z
        GIM_CheckCxxInsnPredicate, /*MI*/0, /*FnId*/GIMT_Encode2(GICXXPred_MI_Predicate_anonymous_23618),
        GIM_CheckIsSafeToFold, /*InsnID*/1,
        // (or:{ *:[i32] } (or:{ *:[i32] } i32:{ *:[i32] }:$src0:$pred:7:x, i32:{ *:[i32] }:$src1:$pred:7:y)<<P:Predicate_anonymous_23619>>, i32:{ *:[i32] }:$src2:$pred:7:z)<<P:7:Predicate_anonymous_23618>>  =>  (V_OR3_B32_e64:{ *:[i32] } VSrc_b32:{ *:[i32] }:$src0, VSrc_b32:{ *:[i32] }:$src1, VSrc_b32:{ *:[i32] }:$src2)
        GIR_BuildMI, /*InsnID*/0, /*Opcode*/GIMT_Encode2(AMDGPU::V_OR3_B32_e64),
        GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/0, // DstI[vdst]
        GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/1, /*OpIdx*/1, // src0
        GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/1, /*OpIdx*/2, // src1
        GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/2, // src2
        GIR_ConstrainSelectedInstOperands, /*InsnID*/0,
        GIR_EraseFromParent, /*InsnID*/0,
        // GIR_Coverage, 2193,
        GIR_Done,
      // Label 329: @24065
      GIM_Try, /*On fail goto*//*Label 330*/ GIMT_Encode4(24141), // Rule ID 2190 //
        GIM_CheckFeatures, GIMT_Encode2(GIFBS_isGFX9Plus),
        GIM_CheckRegBankForClass, /*MI*/0, /*Op*/0, /*RC*/GIMT_Encode2(AMDGPU::VGPR_32RegClassID),
        GIM_RecordInsn, /*DefineMI*/1, /*MI*/0, /*OpIdx*/1, // MIs[1]
        GIM_CheckOpcode, /*MI*/1, GIMT_Encode2(TargetOpcode::G_SHL),
        GIM_CheckType, /*MI*/1, /*Op*/1, /*Type*/GILLT_s32,
        GIM_CheckType, /*MI*/1, /*Op*/2, /*Type*/GILLT_s32,
        GIM_RecordNamedOperand, /*MI*/1, /*Op*/1, /*StoreIdx*/0, // Name : pred:5:x
        GIM_RecordNamedOperand, /*MI*/1, /*Op*/2, /*StoreIdx*/1, // Name : pred:5:y
        GIM_CheckCxxInsnPredicate, /*MI*/1, /*FnId*/GIMT_Encode2(GICXXPred_MI_Predicate_anonymous_23603),
        GIM_RecordNamedOperand, /*MI*/0, /*Op*/2, /*StoreIdx*/2, // Name : pred:5:z
        GIM_CheckCxxInsnPredicate, /*MI*/0, /*FnId*/GIMT_Encode2(GICXXPred_MI_Predicate_anonymous_23613),
        GIM_CheckIsSafeToFold, /*InsnID*/1,
        // (or:{ *:[i32] } (shl:{ *:[i32] } i32:{ *:[i32] }:$src0:$pred:5:x, i32:{ *:[i32] }:$src1:$pred:5:y)<<P:Predicate_anonymous_23603>>, i32:{ *:[i32] }:$src2:$pred:5:z)<<P:5:Predicate_anonymous_23613>>  =>  (V_LSHL_OR_B32_e64:{ *:[i32] } VSrc_b32:{ *:[i32] }:$src0, VSrc_b32:{ *:[i32] }:$src1, VSrc_b32:{ *:[i32] }:$src2)
        GIR_BuildMI, /*InsnID*/0, /*Opcode*/GIMT_Encode2(AMDGPU::V_LSHL_OR_B32_e64),
        GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/0, // DstI[vdst]
        GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/1, /*OpIdx*/1, // src0
        GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/1, /*OpIdx*/2, // src1
        GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/2, // src2
        GIR_ConstrainSelectedInstOperands, /*InsnID*/0,
        GIR_EraseFromParent, /*InsnID*/0,
        // GIR_Coverage, 2190,
        GIR_Done,
      // Label 330: @24141
      GIM_Try, /*On fail goto*//*Label 331*/ GIMT_Encode4(24217), // Rule ID 7214 //
        GIM_CheckFeatures, GIMT_Encode2(GIFBS_isGFX9Plus),
        GIM_CheckRegBankForClass, /*MI*/0, /*Op*/0, /*RC*/GIMT_Encode2(AMDGPU::VGPR_32RegClassID),
        GIM_RecordNamedOperand, /*MI*/0, /*Op*/1, /*StoreIdx*/2, // Name : pred:6:z
        GIM_RecordInsn, /*DefineMI*/1, /*MI*/0, /*OpIdx*/2, // MIs[1]
        GIM_CheckOpcode, /*MI*/1, GIMT_Encode2(TargetOpcode::G_AND),
        GIM_CheckType, /*MI*/1, /*Op*/1, /*Type*/GILLT_s32,
        GIM_CheckType, /*MI*/1, /*Op*/2, /*Type*/GILLT_s32,
        GIM_RecordNamedOperand, /*MI*/1, /*Op*/1, /*StoreIdx*/0, // Name : pred:6:x
        GIM_RecordNamedOperand, /*MI*/1, /*Op*/2, /*StoreIdx*/1, // Name : pred:6:y
        GIM_CheckCxxInsnPredicate, /*MI*/1, /*FnId*/GIMT_Encode2(GICXXPred_MI_Predicate_anonymous_23616),
        GIM_CheckCxxInsnPredicate, /*MI*/0, /*FnId*/GIMT_Encode2(GICXXPred_MI_Predicate_anonymous_23615),
        GIM_CheckIsSafeToFold, /*InsnID*/1,
        // (or:{ *:[i32] } i32:{ *:[i32] }:$src2:$pred:6:z, (and:{ *:[i32] } i32:{ *:[i32] }:$src0:$pred:6:x, i32:{ *:[i32] }:$src1:$pred:6:y)<<P:Predicate_anonymous_23616>>)<<P:6:Predicate_anonymous_23615>>  =>  (V_AND_OR_B32_e64:{ *:[i32] } VSrc_b32:{ *:[i32] }:$src0, VSrc_b32:{ *:[i32] }:$src1, VSrc_b32:{ *:[i32] }:$src2)
        GIR_BuildMI, /*InsnID*/0, /*Opcode*/GIMT_Encode2(AMDGPU::V_AND_OR_B32_e64),
        GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/0, // DstI[vdst]
        GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/1, /*OpIdx*/1, // src0
        GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/1, /*OpIdx*/2, // src1
        GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/1, // src2
        GIR_ConstrainSelectedInstOperands, /*InsnID*/0,
        GIR_EraseFromParent, /*InsnID*/0,
        // GIR_Coverage, 7214,
        GIR_Done,
      // Label 331: @24217
      GIM_Try, /*On fail goto*//*Label 332*/ GIMT_Encode4(24293), // Rule ID 7215 //
        GIM_CheckFeatures, GIMT_Encode2(GIFBS_isGFX9Plus),
        GIM_CheckRegBankForClass, /*MI*/0, /*Op*/0, /*RC*/GIMT_Encode2(AMDGPU::VGPR_32RegClassID),
        GIM_RecordNamedOperand, /*MI*/0, /*Op*/1, /*StoreIdx*/2, // Name : pred:7:z
        GIM_RecordInsn, /*DefineMI*/1, /*MI*/0, /*OpIdx*/2, // MIs[1]
        GIM_CheckOpcode, /*MI*/1, GIMT_Encode2(TargetOpcode::G_OR),
        GIM_CheckType, /*MI*/1, /*Op*/1, /*Type*/GILLT_s32,
        GIM_CheckType, /*MI*/1, /*Op*/2, /*Type*/GILLT_s32,
        GIM_RecordNamedOperand, /*MI*/1, /*Op*/1, /*StoreIdx*/0, // Name : pred:7:x
        GIM_RecordNamedOperand, /*MI*/1, /*Op*/2, /*StoreIdx*/1, // Name : pred:7:y
        GIM_CheckCxxInsnPredicate, /*MI*/1, /*FnId*/GIMT_Encode2(GICXXPred_MI_Predicate_anonymous_23619),
        GIM_CheckCxxInsnPredicate, /*MI*/0, /*FnId*/GIMT_Encode2(GICXXPred_MI_Predicate_anonymous_23618),
        GIM_CheckIsSafeToFold, /*InsnID*/1,
        // (or:{ *:[i32] } i32:{ *:[i32] }:$src2:$pred:7:z, (or:{ *:[i32] } i32:{ *:[i32] }:$src0:$pred:7:x, i32:{ *:[i32] }:$src1:$pred:7:y)<<P:Predicate_anonymous_23619>>)<<P:7:Predicate_anonymous_23618>>  =>  (V_OR3_B32_e64:{ *:[i32] } VSrc_b32:{ *:[i32] }:$src0, VSrc_b32:{ *:[i32] }:$src1, VSrc_b32:{ *:[i32] }:$src2)
        GIR_BuildMI, /*InsnID*/0, /*Opcode*/GIMT_Encode2(AMDGPU::V_OR3_B32_e64),
        GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/0, // DstI[vdst]
        GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/1, /*OpIdx*/1, // src0
        GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/1, /*OpIdx*/2, // src1
        GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/1, // src2
        GIR_ConstrainSelectedInstOperands, /*InsnID*/0,
        GIR_EraseFromParent, /*InsnID*/0,
        // GIR_Coverage, 7215,
        GIR_Done,
      // Label 332: @24293
      GIM_Try, /*On fail goto*//*Label 333*/ GIMT_Encode4(24369), // Rule ID 7212 //
        GIM_CheckFeatures, GIMT_Encode2(GIFBS_isGFX9Plus),
        GIM_CheckRegBankForClass, /*MI*/0, /*Op*/0, /*RC*/GIMT_Encode2(AMDGPU::VGPR_32RegClassID),
        GIM_RecordNamedOperand, /*MI*/0, /*Op*/1, /*StoreIdx*/2, // Name : pred:5:z
        GIM_RecordInsn, /*DefineMI*/1, /*MI*/0, /*OpIdx*/2, // MIs[1]
        GIM_CheckOpcode, /*MI*/1, GIMT_Encode2(TargetOpcode::G_SHL),
        GIM_CheckType, /*MI*/1, /*Op*/1, /*Type*/GILLT_s32,
        GIM_CheckType, /*MI*/1, /*Op*/2, /*Type*/GILLT_s32,
        GIM_RecordNamedOperand, /*MI*/1, /*Op*/1, /*StoreIdx*/0, // Name : pred:5:x
        GIM_RecordNamedOperand, /*MI*/1, /*Op*/2, /*StoreIdx*/1, // Name : pred:5:y
        GIM_CheckCxxInsnPredicate, /*MI*/1, /*FnId*/GIMT_Encode2(GICXXPred_MI_Predicate_anonymous_23603),
        GIM_CheckCxxInsnPredicate, /*MI*/0, /*FnId*/GIMT_Encode2(GICXXPred_MI_Predicate_anonymous_23613),
        GIM_CheckIsSafeToFold, /*InsnID*/1,
        // (or:{ *:[i32] } i32:{ *:[i32] }:$src2:$pred:5:z, (shl:{ *:[i32] } i32:{ *:[i32] }:$src0:$pred:5:x, i32:{ *:[i32] }:$src1:$pred:5:y)<<P:Predicate_anonymous_23603>>)<<P:5:Predicate_anonymous_23613>>  =>  (V_LSHL_OR_B32_e64:{ *:[i32] } VSrc_b32:{ *:[i32] }:$src0, VSrc_b32:{ *:[i32] }:$src1, VSrc_b32:{ *:[i32] }:$src2)
        GIR_BuildMI, /*InsnID*/0, /*Opcode*/GIMT_Encode2(AMDGPU::V_LSHL_OR_B32_e64),
        GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/0, // DstI[vdst]
        GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/1, /*OpIdx*/1, // src0
        GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/1, /*OpIdx*/2, // src1
        GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/1, // src2
        GIR_ConstrainSelectedInstOperands, /*InsnID*/0,
        GIR_EraseFromParent, /*InsnID*/0,
        // GIR_Coverage, 7212,
        GIR_Done,
      // Label 333: @24369
      GIM_Try, /*On fail goto*//*Label 334*/ GIMT_Encode4(24397), // Rule ID 56 //
        GIM_CheckRegBankForClass, /*MI*/0, /*Op*/0, /*RC*/GIMT_Encode2(AMDGPU::SReg_32RegClassID),
        GIM_CheckCxxInsnPredicate, /*MI*/0, /*FnId*/GIMT_Encode2(GICXXPred_MI_Predicate_anonymous_17616),
        // (or:{ *:[i32] } i32:{ *:[i32] }:$src0, i32:{ *:[i32] }:$src1)<<P:Predicate_anonymous_17616>>  =>  (S_OR_B32:{ *:[i32] }:{ *:[i1] } i32:{ *:[i32] }:$src0, i32:{ *:[i32] }:$src1)
        GIR_MutateOpcode, /*InsnID*/0, /*RecycleInsnID*/0, /*Opcode*/GIMT_Encode2(AMDGPU::S_OR_B32),
        GIR_AddImplicitDef, /*InsnID*/0, GIMT_Encode2(AMDGPU::SCC), GIMT_Encode2(RegState::Dead),
        GIR_ConstrainSelectedInstOperands, /*InsnID*/0,
        // GIR_Coverage, 56,
        GIR_Done,
      // Label 334: @24397
      GIM_Try, /*On fail goto*//*Label 335*/ GIMT_Encode4(24419), // Rule ID 754 //
        GIM_CheckRegBankForClass, /*MI*/0, /*Op*/0, /*RC*/GIMT_Encode2(AMDGPU::VGPR_32RegClassID),
        // (or:{ *:[i32] } i32:{ *:[i32] }:$src0, i32:{ *:[i32] }:$src1)  =>  (V_OR_B32_e64:{ *:[i32] } i32:{ *:[i32] }:$src0, i32:{ *:[i32] }:$src1)
        GIR_MutateOpcode, /*InsnID*/0, /*RecycleInsnID*/0, /*Opcode*/GIMT_Encode2(AMDGPU::V_OR_B32_e64),
        GIR_AddImplicitUse, /*InsnID*/0, GIMT_Encode2(AMDGPU::EXEC),
        GIR_ConstrainSelectedInstOperands, /*InsnID*/0,
        // GIR_Coverage, 754,
        GIR_Done,
      // Label 335: @24419
      GIM_Reject,
    // Label 299: @24420
    GIM_Reject,
    // Label 286: @24421
    GIM_Try, /*On fail goto*//*Label 336*/ GIMT_Encode4(33879),
      GIM_CheckType, /*MI*/0, /*Op*/1, /*Type*/GILLT_s64,
      GIM_CheckType, /*MI*/0, /*Op*/2, /*Type*/GILLT_s64,
      GIM_Try, /*On fail goto*//*Label 337*/ GIMT_Encode4(24759), // Rule ID 9884 //
        GIM_CheckRegBankForClass, /*MI*/0, /*Op*/0, /*RC*/GIMT_Encode2(AMDGPU::VReg_64RegClassID),
        GIM_RecordInsnIgnoreCopies, /*DefineMI*/1, /*MI*/0, /*OpIdx*/1, // MIs[1]
        GIM_CheckOpcode, /*MI*/1, GIMT_Encode2(TargetOpcode::G_AND),
        GIM_CheckType, /*MI*/1, /*Op*/1, /*Type*/GILLT_s64,
        GIM_CheckType, /*MI*/1, /*Op*/2, /*Type*/GILLT_s64,
        GIM_RecordInsnIgnoreCopies, /*DefineMI*/2, /*MI*/1, /*OpIdx*/1, // MIs[2]
        GIM_CheckOpcode, /*MI*/2, GIMT_Encode2(TargetOpcode::G_XOR),
        GIM_CheckType, /*MI*/2, /*Op*/1, /*Type*/GILLT_s64,
        GIM_CheckType, /*MI*/2, /*Op*/2, /*Type*/GILLT_s64,
        GIM_CheckConstantInt8, /*MI*/2, /*Op*/2, uint8_t(-1),
        GIM_RecordInsnIgnoreCopies, /*DefineMI*/3, /*MI*/0, /*OpIdx*/2, // MIs[3]
        GIM_CheckOpcode, /*MI*/3, GIMT_Encode2(TargetOpcode::G_AND),
        GIM_CheckType, /*MI*/3, /*Op*/2, /*Type*/GILLT_s64,
        // MIs[3] x
        GIM_CheckIsSameOperandIgnoreCopies, /*MI*/3, /*OpIdx*/1, /*OtherMI*/2, /*OtherOpIdx*/1,
        GIM_CheckCxxInsnPredicate, /*MI*/0, /*FnId*/GIMT_Encode2(GICXXPred_MI_Predicate_anonymous_22557),
        GIM_CheckIsSafeToFold, /*InsnID*/1,
        GIM_CheckIsSafeToFold, /*InsnID*/2,
        GIM_CheckIsSafeToFold, /*InsnID*/3,
        // (or:{ *:[i64] } (and:{ *:[i64] } (xor:{ *:[i64] } i64:{ *:[i64] }:$x, -1:{ *:[i64] }), i64:{ *:[i64] }:$z), (and:{ *:[i64] } i64:{ *:[i64] }:$x, i64:{ *:[i64] }:$y))<<P:Predicate_anonymous_22557>>  =>  (REG_SEQUENCE:{ *:[i64] } VReg_64:{ *:[i32] }, (V_BFI_B32_e64:{ *:[i16] } (EXTRACT_SUBREG:{ *:[i32] } VReg_64:{ *:[i64] }:$x, sub0:{ *:[i32] }), (EXTRACT_SUBREG:{ *:[i32] } VReg_64:{ *:[i64] }:$y, sub0:{ *:[i32] }), (EXTRACT_SUBREG:{ *:[i32] } VReg_64:{ *:[i64] }:$z, sub0:{ *:[i32] })), sub0:{ *:[i32] }, (V_BFI_B32_e64:{ *:[i16] } (EXTRACT_SUBREG:{ *:[i32] } VReg_64:{ *:[i64] }:$x, sub1:{ *:[i32] }), (EXTRACT_SUBREG:{ *:[i32] } VReg_64:{ *:[i64] }:$y, sub1:{ *:[i32] }), (EXTRACT_SUBREG:{ *:[i32] } VReg_64:{ *:[i64] }:$z, sub1:{ *:[i32] })), sub1:{ *:[i32] })
        GIR_MakeTempReg, /*TempRegID*/0, /*TypeID*/GILLT_s16,
        GIR_MakeTempReg, /*TempRegID*/1, /*TypeID*/GILLT_s32,
        GIR_MakeTempReg, /*TempRegID*/2, /*TypeID*/GILLT_s32,
        GIR_MakeTempReg, /*TempRegID*/3, /*TypeID*/GILLT_s32,
        GIR_MakeTempReg, /*TempRegID*/4, /*TypeID*/GILLT_s16,
        GIR_MakeTempReg, /*TempRegID*/5, /*TypeID*/GILLT_s32,
        GIR_MakeTempReg, /*TempRegID*/6, /*TypeID*/GILLT_s32,
        GIR_MakeTempReg, /*TempRegID*/7, /*TypeID*/GILLT_s32,
        GIR_BuildMI, /*InsnID*/8, /*Opcode*/GIMT_Encode2(TargetOpcode::COPY),
        GIR_AddTempRegister, /*InsnID*/8, /*TempRegID*/7, /*TempRegFlags*/GIMT_Encode2(RegState::Define),
        GIR_CopySubReg, /*NewInsnID*/8, /*OldInsnID*/1, /*OpIdx*/2, /*SubRegIdx*/GIMT_Encode2(11), // z
        GIR_ConstrainOperandRC, /*InsnID*/8, /*Op*/0, GIMT_Encode2(AMDGPU::VGPR_32RegClassID),
        GIR_ConstrainOperandRC, /*InsnID*/8, /*Op*/1, GIMT_Encode2(AMDGPU::VReg_64RegClassID),
        GIR_BuildMI, /*InsnID*/7, /*Opcode*/GIMT_Encode2(TargetOpcode::COPY),
        GIR_AddTempRegister, /*InsnID*/7, /*TempRegID*/6, /*TempRegFlags*/GIMT_Encode2(RegState::Define),
        GIR_CopySubReg, /*NewInsnID*/7, /*OldInsnID*/3, /*OpIdx*/2, /*SubRegIdx*/GIMT_Encode2(11), // y
        GIR_ConstrainOperandRC, /*InsnID*/7, /*Op*/0, GIMT_Encode2(AMDGPU::VGPR_32RegClassID),
        GIR_ConstrainOperandRC, /*InsnID*/7, /*Op*/1, GIMT_Encode2(AMDGPU::VReg_64RegClassID),
        GIR_BuildMI, /*InsnID*/6, /*Opcode*/GIMT_Encode2(TargetOpcode::COPY),
        GIR_AddTempRegister, /*InsnID*/6, /*TempRegID*/5, /*TempRegFlags*/GIMT_Encode2(RegState::Define),
        GIR_CopySubReg, /*NewInsnID*/6, /*OldInsnID*/2, /*OpIdx*/1, /*SubRegIdx*/GIMT_Encode2(11), // x
        GIR_ConstrainOperandRC, /*InsnID*/6, /*Op*/0, GIMT_Encode2(AMDGPU::VGPR_32RegClassID),
        GIR_ConstrainOperandRC, /*InsnID*/6, /*Op*/1, GIMT_Encode2(AMDGPU::VReg_64RegClassID),
        GIR_BuildMI, /*InsnID*/5, /*Opcode*/GIMT_Encode2(AMDGPU::V_BFI_B32_e64),
        GIR_AddTempRegister, /*InsnID*/5, /*TempRegID*/4, /*TempRegFlags*/GIMT_Encode2(RegState::Define),
        GIR_AddSimpleTempRegister, /*InsnID*/5, /*TempRegID*/5,
        GIR_AddSimpleTempRegister, /*InsnID*/5, /*TempRegID*/6,
        GIR_AddSimpleTempRegister, /*InsnID*/5, /*TempRegID*/7,
        GIR_ConstrainSelectedInstOperands, /*InsnID*/5,
        GIR_BuildMI, /*InsnID*/4, /*Opcode*/GIMT_Encode2(TargetOpcode::COPY),
        GIR_AddTempRegister, /*InsnID*/4, /*TempRegID*/3, /*TempRegFlags*/GIMT_Encode2(RegState::Define),
        GIR_CopySubReg, /*NewInsnID*/4, /*OldInsnID*/1, /*OpIdx*/2, /*SubRegIdx*/GIMT_Encode2(3), // z
        GIR_ConstrainOperandRC, /*InsnID*/4, /*Op*/0, GIMT_Encode2(AMDGPU::VGPR_32RegClassID),
        GIR_ConstrainOperandRC, /*InsnID*/4, /*Op*/1, GIMT_Encode2(AMDGPU::VReg_64RegClassID),
        GIR_BuildMI, /*InsnID*/3, /*Opcode*/GIMT_Encode2(TargetOpcode::COPY),
        GIR_AddTempRegister, /*InsnID*/3, /*TempRegID*/2, /*TempRegFlags*/GIMT_Encode2(RegState::Define),
        GIR_CopySubReg, /*NewInsnID*/3, /*OldInsnID*/3, /*OpIdx*/2, /*SubRegIdx*/GIMT_Encode2(3), // y
        GIR_ConstrainOperandRC, /*InsnID*/3, /*Op*/0, GIMT_Encode2(AMDGPU::VGPR_32RegClassID),
        GIR_ConstrainOperandRC, /*InsnID*/3, /*Op*/1, GIMT_Encode2(AMDGPU::VReg_64RegClassID),
        GIR_BuildMI, /*InsnID*/2, /*Opcode*/GIMT_Encode2(TargetOpcode::COPY),
        GIR_AddTempRegister, /*InsnID*/2, /*TempRegID*/1, /*TempRegFlags*/GIMT_Encode2(RegState::Define),
        GIR_CopySubReg, /*NewInsnID*/2, /*OldInsnID*/2, /*OpIdx*/1, /*SubRegIdx*/GIMT_Encode2(3), // x
        GIR_ConstrainOperandRC, /*InsnID*/2, /*Op*/0, GIMT_Encode2(AMDGPU::VGPR_32RegClassID),
        GIR_ConstrainOperandRC, /*InsnID*/2, /*Op*/1, GIMT_Encode2(AMDGPU::VReg_64RegClassID),
        GIR_BuildMI, /*InsnID*/1, /*Opcode*/GIMT_Encode2(AMDGPU::V_BFI_B32_e64),
        GIR_AddTempRegister, /*InsnID*/1, /*TempRegID*/0, /*TempRegFlags*/GIMT_Encode2(RegState::Define),
        GIR_AddSimpleTempRegister, /*InsnID*/1, /*TempRegID*/1,
        GIR_AddSimpleTempRegister, /*InsnID*/1, /*TempRegID*/2,
        GIR_AddSimpleTempRegister, /*InsnID*/1, /*TempRegID*/3,
        GIR_ConstrainSelectedInstOperands, /*InsnID*/1,
        GIR_BuildMI, /*InsnID*/0, /*Opcode*/GIMT_Encode2(TargetOpcode::REG_SEQUENCE),
        GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/0, // DstI[dst]
        GIR_AddSimpleTempRegister, /*InsnID*/0, /*TempRegID*/0,
        GIR_AddImm8, /*InsnID*/0, /*SubRegIndex*/3,
        GIR_AddSimpleTempRegister, /*InsnID*/0, /*TempRegID*/4,
        GIR_AddImm8, /*InsnID*/0, /*SubRegIndex*/11,
        GIR_ConstrainOperandRC, /*InsnID*/0, /*Op*/0, GIMT_Encode2(AMDGPU::VReg_64RegClassID),
        GIR_ConstrainOperandRC, /*InsnID*/0, /*Op*/1, GIMT_Encode2(AMDGPU::VGPR_32RegClassID),
        GIR_ConstrainOperandRC, /*InsnID*/0, /*Op*/3, GIMT_Encode2(AMDGPU::VGPR_32RegClassID),
        GIR_EraseFromParent, /*InsnID*/0,
        // GIR_Coverage, 9884,
        GIR_Done,
      // Label 337: @24759
      GIM_Try, /*On fail goto*//*Label 338*/ GIMT_Encode4(25084), // Rule ID 9883 //
        GIM_CheckRegBankForClass, /*MI*/0, /*Op*/0, /*RC*/GIMT_Encode2(AMDGPU::VReg_64RegClassID),
        GIM_RecordInsnIgnoreCopies, /*DefineMI*/1, /*MI*/0, /*OpIdx*/1, // MIs[1]
        GIM_CheckOpcode, /*MI*/1, GIMT_Encode2(TargetOpcode::G_AND),
        GIM_CheckType, /*MI*/1, /*Op*/1, /*Type*/GILLT_s64,
        GIM_CheckType, /*MI*/1, /*Op*/2, /*Type*/GILLT_s64,
        GIM_RecordInsnIgnoreCopies, /*DefineMI*/2, /*MI*/1, /*OpIdx*/1, // MIs[2]
        GIM_CheckOpcode, /*MI*/2, GIMT_Encode2(TargetOpcode::G_XOR),
        GIM_CheckType, /*MI*/2, /*Op*/1, /*Type*/GILLT_s64,
        GIM_CheckType, /*MI*/2, /*Op*/2, /*Type*/GILLT_s64,
        GIM_CheckConstantInt8, /*MI*/2, /*Op*/2, uint8_t(-1),
        GIM_RecordInsnIgnoreCopies, /*DefineMI*/3, /*MI*/0, /*OpIdx*/2, // MIs[3]
        GIM_CheckOpcode, /*MI*/3, GIMT_Encode2(TargetOpcode::G_AND),
        GIM_CheckType, /*MI*/3, /*Op*/1, /*Type*/GILLT_s64,
        // MIs[3] x
        GIM_CheckIsSameOperandIgnoreCopies, /*MI*/3, /*OpIdx*/2, /*OtherMI*/2, /*OtherOpIdx*/1,
        GIM_CheckCxxInsnPredicate, /*MI*/0, /*FnId*/GIMT_Encode2(GICXXPred_MI_Predicate_anonymous_22557),
        GIM_CheckIsSafeToFold, /*InsnID*/1,
        GIM_CheckIsSafeToFold, /*InsnID*/2,
        GIM_CheckIsSafeToFold, /*InsnID*/3,
        // (or:{ *:[i64] } (and:{ *:[i64] } (xor:{ *:[i64] } i64:{ *:[i64] }:$x, -1:{ *:[i64] }), i64:{ *:[i64] }:$z), (and:{ *:[i64] } i64:{ *:[i64] }:$y, i64:{ *:[i64] }:$x))<<P:Predicate_anonymous_22557>>  =>  (REG_SEQUENCE:{ *:[i64] } VReg_64:{ *:[i32] }, (V_BFI_B32_e64:{ *:[i16] } (EXTRACT_SUBREG:{ *:[i32] } VReg_64:{ *:[i64] }:$x, sub0:{ *:[i32] }), (EXTRACT_SUBREG:{ *:[i32] } VReg_64:{ *:[i64] }:$y, sub0:{ *:[i32] }), (EXTRACT_SUBREG:{ *:[i32] } VReg_64:{ *:[i64] }:$z, sub0:{ *:[i32] })), sub0:{ *:[i32] }, (V_BFI_B32_e64:{ *:[i16] } (EXTRACT_SUBREG:{ *:[i32] } VReg_64:{ *:[i64] }:$x, sub1:{ *:[i32] }), (EXTRACT_SUBREG:{ *:[i32] } VReg_64:{ *:[i64] }:$y, sub1:{ *:[i32] }), (EXTRACT_SUBREG:{ *:[i32] } VReg_64:{ *:[i64] }:$z, sub1:{ *:[i32] })), sub1:{ *:[i32] })
        GIR_MakeTempReg, /*TempRegID*/0, /*TypeID*/GILLT_s16,
        GIR_MakeTempReg, /*TempRegID*/1, /*TypeID*/GILLT_s32,
        GIR_MakeTempReg, /*TempRegID*/2, /*TypeID*/GILLT_s32,
        GIR_MakeTempReg, /*TempRegID*/3, /*TypeID*/GILLT_s32,
        GIR_MakeTempReg, /*TempRegID*/4, /*TypeID*/GILLT_s16,
        GIR_MakeTempReg, /*TempRegID*/5, /*TypeID*/GILLT_s32,
        GIR_MakeTempReg, /*TempRegID*/6, /*TypeID*/GILLT_s32,
        GIR_MakeTempReg, /*TempRegID*/7, /*TypeID*/GILLT_s32,
        GIR_BuildMI, /*InsnID*/8, /*Opcode*/GIMT_Encode2(TargetOpcode::COPY),
        GIR_AddTempRegister, /*InsnID*/8, /*TempRegID*/7, /*TempRegFlags*/GIMT_Encode2(RegState::Define),
        GIR_CopySubReg, /*NewInsnID*/8, /*OldInsnID*/1, /*OpIdx*/2, /*SubRegIdx*/GIMT_Encode2(11), // z
        GIR_ConstrainOperandRC, /*InsnID*/8, /*Op*/0, GIMT_Encode2(AMDGPU::VGPR_32RegClassID),
        GIR_ConstrainOperandRC, /*InsnID*/8, /*Op*/1, GIMT_Encode2(AMDGPU::VReg_64RegClassID),
        GIR_BuildMI, /*InsnID*/7, /*Opcode*/GIMT_Encode2(TargetOpcode::COPY),
        GIR_AddTempRegister, /*InsnID*/7, /*TempRegID*/6, /*TempRegFlags*/GIMT_Encode2(RegState::Define),
        GIR_CopySubReg, /*NewInsnID*/7, /*OldInsnID*/3, /*OpIdx*/1, /*SubRegIdx*/GIMT_Encode2(11), // y
        GIR_ConstrainOperandRC, /*InsnID*/7, /*Op*/0, GIMT_Encode2(AMDGPU::VGPR_32RegClassID),
        GIR_ConstrainOperandRC, /*InsnID*/7, /*Op*/1, GIMT_Encode2(AMDGPU::VReg_64RegClassID),
        GIR_BuildMI, /*InsnID*/6, /*Opcode*/GIMT_Encode2(TargetOpcode::COPY),
        GIR_AddTempRegister, /*InsnID*/6, /*TempRegID*/5, /*TempRegFlags*/GIMT_Encode2(RegState::Define),
        GIR_CopySubReg, /*NewInsnID*/6, /*OldInsnID*/2, /*OpIdx*/1, /*SubRegIdx*/GIMT_Encode2(11), // x
        GIR_ConstrainOperandRC, /*InsnID*/6, /*Op*/0, GIMT_Encode2(AMDGPU::VGPR_32RegClassID),
        GIR_ConstrainOperandRC, /*InsnID*/6, /*Op*/1, GIMT_Encode2(AMDGPU::VReg_64RegClassID),
        GIR_BuildMI, /*InsnID*/5, /*Opcode*/GIMT_Encode2(AMDGPU::V_BFI_B32_e64),
        GIR_AddTempRegister, /*InsnID*/5, /*TempRegID*/4, /*TempRegFlags*/GIMT_Encode2(RegState::Define),
        GIR_AddSimpleTempRegister, /*InsnID*/5, /*TempRegID*/5,
        GIR_AddSimpleTempRegister, /*InsnID*/5, /*TempRegID*/6,
        GIR_AddSimpleTempRegister, /*InsnID*/5, /*TempRegID*/7,
        GIR_ConstrainSelectedInstOperands, /*InsnID*/5,
        GIR_BuildMI, /*InsnID*/4, /*Opcode*/GIMT_Encode2(TargetOpcode::COPY),
        GIR_AddTempRegister, /*InsnID*/4, /*TempRegID*/3, /*TempRegFlags*/GIMT_Encode2(RegState::Define),
        GIR_CopySubReg, /*NewInsnID*/4, /*OldInsnID*/1, /*OpIdx*/2, /*SubRegIdx*/GIMT_Encode2(3), // z
        GIR_ConstrainOperandRC, /*InsnID*/4, /*Op*/0, GIMT_Encode2(AMDGPU::VGPR_32RegClassID),
        GIR_ConstrainOperandRC, /*InsnID*/4, /*Op*/1, GIMT_Encode2(AMDGPU::VReg_64RegClassID),
        GIR_BuildMI, /*InsnID*/3, /*Opcode*/GIMT_Encode2(TargetOpcode::COPY),
        GIR_AddTempRegister, /*InsnID*/3, /*TempRegID*/2, /*TempRegFlags*/GIMT_Encode2(RegState::Define),
        GIR_CopySubReg, /*NewInsnID*/3, /*OldInsnID*/3, /*OpIdx*/1, /*SubRegIdx*/GIMT_Encode2(3), // y
        GIR_ConstrainOperandRC, /*InsnID*/3, /*Op*/0, GIMT_Encode2(AMDGPU::VGPR_32RegClassID),
        GIR_ConstrainOperandRC, /*InsnID*/3, /*Op*/1, GIMT_Encode2(AMDGPU::VReg_64RegClassID),
        GIR_BuildMI, /*InsnID*/2, /*Opcode*/GIMT_Encode2(TargetOpcode::COPY),
        GIR_AddTempRegister, /*InsnID*/2, /*TempRegID*/1, /*TempRegFlags*/GIMT_Encode2(RegState::Define),
        GIR_CopySubReg, /*NewInsnID*/2, /*OldInsnID*/2, /*OpIdx*/1, /*SubRegIdx*/GIMT_Encode2(3), // x
        GIR_ConstrainOperandRC, /*InsnID*/2, /*Op*/0, GIMT_Encode2(AMDGPU::VGPR_32RegClassID),
        GIR_ConstrainOperandRC, /*InsnID*/2, /*Op*/1, GIMT_Encode2(AMDGPU::VReg_64RegClassID),
        GIR_BuildMI, /*InsnID*/1, /*Opcode*/GIMT_Encode2(AMDGPU::V_BFI_B32_e64),
        GIR_AddTempRegister, /*InsnID*/1, /*TempRegID*/0, /*TempRegFlags*/GIMT_Encode2(RegState::Define),
        GIR_AddSimpleTempRegister, /*InsnID*/1, /*TempRegID*/1,
        GIR_AddSimpleTempRegister, /*InsnID*/1, /*TempRegID*/2,
        GIR_AddSimpleTempRegister, /*InsnID*/1, /*TempRegID*/3,
        GIR_ConstrainSelectedInstOperands, /*InsnID*/1,
        GIR_BuildMI, /*InsnID*/0, /*Opcode*/GIMT_Encode2(TargetOpcode::REG_SEQUENCE),
        GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/0, // DstI[dst]
        GIR_AddSimpleTempRegister, /*InsnID*/0, /*TempRegID*/0,
        GIR_AddImm8, /*InsnID*/0, /*SubRegIndex*/3,
        GIR_AddSimpleTempRegister, /*InsnID*/0, /*TempRegID*/4,
        GIR_AddImm8, /*InsnID*/0, /*SubRegIndex*/11,
        GIR_ConstrainOperandRC, /*InsnID*/0, /*Op*/0, GIMT_Encode2(AMDGPU::VReg_64RegClassID),
        GIR_ConstrainOperandRC, /*InsnID*/0, /*Op*/1, GIMT_Encode2(AMDGPU::VGPR_32RegClassID),
        GIR_ConstrainOperandRC, /*InsnID*/0, /*Op*/3, GIMT_Encode2(AMDGPU::VGPR_32RegClassID),
        GIR_EraseFromParent, /*InsnID*/0,
        // GIR_Coverage, 9883,
        GIR_Done,
      // Label 338: @25084
      GIM_Try, /*On fail goto*//*Label 339*/ GIMT_Encode4(25409), // Rule ID 9882 //
        GIM_CheckRegBankForClass, /*MI*/0, /*Op*/0, /*RC*/GIMT_Encode2(AMDGPU::VReg_64RegClassID),
        GIM_RecordInsnIgnoreCopies, /*DefineMI*/1, /*MI*/0, /*OpIdx*/1, // MIs[1]
        GIM_CheckOpcode, /*MI*/1, GIMT_Encode2(TargetOpcode::G_AND),
        GIM_CheckType, /*MI*/1, /*Op*/1, /*Type*/GILLT_s64,
        GIM_CheckType, /*MI*/1, /*Op*/2, /*Type*/GILLT_s64,
        GIM_RecordInsnIgnoreCopies, /*DefineMI*/2, /*MI*/1, /*OpIdx*/2, // MIs[2]
        GIM_CheckOpcode, /*MI*/2, GIMT_Encode2(TargetOpcode::G_XOR),
        GIM_CheckType, /*MI*/2, /*Op*/1, /*Type*/GILLT_s64,
        GIM_CheckType, /*MI*/2, /*Op*/2, /*Type*/GILLT_s64,
        GIM_CheckConstantInt8, /*MI*/2, /*Op*/2, uint8_t(-1),
        GIM_RecordInsnIgnoreCopies, /*DefineMI*/3, /*MI*/0, /*OpIdx*/2, // MIs[3]
        GIM_CheckOpcode, /*MI*/3, GIMT_Encode2(TargetOpcode::G_AND),
        GIM_CheckType, /*MI*/3, /*Op*/2, /*Type*/GILLT_s64,
        // MIs[3] x
        GIM_CheckIsSameOperandIgnoreCopies, /*MI*/3, /*OpIdx*/1, /*OtherMI*/2, /*OtherOpIdx*/1,
        GIM_CheckCxxInsnPredicate, /*MI*/0, /*FnId*/GIMT_Encode2(GICXXPred_MI_Predicate_anonymous_22557),
        GIM_CheckIsSafeToFold, /*InsnID*/1,
        GIM_CheckIsSafeToFold, /*InsnID*/2,
        GIM_CheckIsSafeToFold, /*InsnID*/3,
        // (or:{ *:[i64] } (and:{ *:[i64] } i64:{ *:[i64] }:$z, (xor:{ *:[i64] } i64:{ *:[i64] }:$x, -1:{ *:[i64] })), (and:{ *:[i64] } i64:{ *:[i64] }:$x, i64:{ *:[i64] }:$y))<<P:Predicate_anonymous_22557>>  =>  (REG_SEQUENCE:{ *:[i64] } VReg_64:{ *:[i32] }, (V_BFI_B32_e64:{ *:[i16] } (EXTRACT_SUBREG:{ *:[i32] } VReg_64:{ *:[i64] }:$x, sub0:{ *:[i32] }), (EXTRACT_SUBREG:{ *:[i32] } VReg_64:{ *:[i64] }:$y, sub0:{ *:[i32] }), (EXTRACT_SUBREG:{ *:[i32] } VReg_64:{ *:[i64] }:$z, sub0:{ *:[i32] })), sub0:{ *:[i32] }, (V_BFI_B32_e64:{ *:[i16] } (EXTRACT_SUBREG:{ *:[i32] } VReg_64:{ *:[i64] }:$x, sub1:{ *:[i32] }), (EXTRACT_SUBREG:{ *:[i32] } VReg_64:{ *:[i64] }:$y, sub1:{ *:[i32] }), (EXTRACT_SUBREG:{ *:[i32] } VReg_64:{ *:[i64] }:$z, sub1:{ *:[i32] })), sub1:{ *:[i32] })
        GIR_MakeTempReg, /*TempRegID*/0, /*TypeID*/GILLT_s16,
        GIR_MakeTempReg, /*TempRegID*/1, /*TypeID*/GILLT_s32,
        GIR_MakeTempReg, /*TempRegID*/2, /*TypeID*/GILLT_s32,
        GIR_MakeTempReg, /*TempRegID*/3, /*TypeID*/GILLT_s32,
        GIR_MakeTempReg, /*TempRegID*/4, /*TypeID*/GILLT_s16,
        GIR_MakeTempReg, /*TempRegID*/5, /*TypeID*/GILLT_s32,
        GIR_MakeTempReg, /*TempRegID*/6, /*TypeID*/GILLT_s32,
        GIR_MakeTempReg, /*TempRegID*/7, /*TypeID*/GILLT_s32,
        GIR_BuildMI, /*InsnID*/8, /*Opcode*/GIMT_Encode2(TargetOpcode::COPY),
        GIR_AddTempRegister, /*InsnID*/8, /*TempRegID*/7, /*TempRegFlags*/GIMT_Encode2(RegState::Define),
        GIR_CopySubReg, /*NewInsnID*/8, /*OldInsnID*/1, /*OpIdx*/1, /*SubRegIdx*/GIMT_Encode2(11), // z
        GIR_ConstrainOperandRC, /*InsnID*/8, /*Op*/0, GIMT_Encode2(AMDGPU::VGPR_32RegClassID),
        GIR_ConstrainOperandRC, /*InsnID*/8, /*Op*/1, GIMT_Encode2(AMDGPU::VReg_64RegClassID),
        GIR_BuildMI, /*InsnID*/7, /*Opcode*/GIMT_Encode2(TargetOpcode::COPY),
        GIR_AddTempRegister, /*InsnID*/7, /*TempRegID*/6, /*TempRegFlags*/GIMT_Encode2(RegState::Define),
        GIR_CopySubReg, /*NewInsnID*/7, /*OldInsnID*/3, /*OpIdx*/2, /*SubRegIdx*/GIMT_Encode2(11), // y
        GIR_ConstrainOperandRC, /*InsnID*/7, /*Op*/0, GIMT_Encode2(AMDGPU::VGPR_32RegClassID),
        GIR_ConstrainOperandRC, /*InsnID*/7, /*Op*/1, GIMT_Encode2(AMDGPU::VReg_64RegClassID),
        GIR_BuildMI, /*InsnID*/6, /*Opcode*/GIMT_Encode2(TargetOpcode::COPY),
        GIR_AddTempRegister, /*InsnID*/6, /*TempRegID*/5, /*TempRegFlags*/GIMT_Encode2(RegState::Define),
        GIR_CopySubReg, /*NewInsnID*/6, /*OldInsnID*/2, /*OpIdx*/1, /*SubRegIdx*/GIMT_Encode2(11), // x
        GIR_ConstrainOperandRC, /*InsnID*/6, /*Op*/0, GIMT_Encode2(AMDGPU::VGPR_32RegClassID),
        GIR_ConstrainOperandRC, /*InsnID*/6, /*Op*/1, GIMT_Encode2(AMDGPU::VReg_64RegClassID),
        GIR_BuildMI, /*InsnID*/5, /*Opcode*/GIMT_Encode2(AMDGPU::V_BFI_B32_e64),
        GIR_AddTempRegister, /*InsnID*/5, /*TempRegID*/4, /*TempRegFlags*/GIMT_Encode2(RegState::Define),
        GIR_AddSimpleTempRegister, /*InsnID*/5, /*TempRegID*/5,
        GIR_AddSimpleTempRegister, /*InsnID*/5, /*TempRegID*/6,
        GIR_AddSimpleTempRegister, /*InsnID*/5, /*TempRegID*/7,
        GIR_ConstrainSelectedInstOperands, /*InsnID*/5,
        GIR_BuildMI, /*InsnID*/4, /*Opcode*/GIMT_Encode2(TargetOpcode::COPY),
        GIR_AddTempRegister, /*InsnID*/4, /*TempRegID*/3, /*TempRegFlags*/GIMT_Encode2(RegState::Define),
        GIR_CopySubReg, /*NewInsnID*/4, /*OldInsnID*/1, /*OpIdx*/1, /*SubRegIdx*/GIMT_Encode2(3), // z
        GIR_ConstrainOperandRC, /*InsnID*/4, /*Op*/0, GIMT_Encode2(AMDGPU::VGPR_32RegClassID),
        GIR_ConstrainOperandRC, /*InsnID*/4, /*Op*/1, GIMT_Encode2(AMDGPU::VReg_64RegClassID),
        GIR_BuildMI, /*InsnID*/3, /*Opcode*/GIMT_Encode2(TargetOpcode::COPY),
        GIR_AddTempRegister, /*InsnID*/3, /*TempRegID*/2, /*TempRegFlags*/GIMT_Encode2(RegState::Define),
        GIR_CopySubReg, /*NewInsnID*/3, /*OldInsnID*/3, /*OpIdx*/2, /*SubRegIdx*/GIMT_Encode2(3), // y
        GIR_ConstrainOperandRC, /*InsnID*/3, /*Op*/0, GIMT_Encode2(AMDGPU::VGPR_32RegClassID),
        GIR_ConstrainOperandRC, /*InsnID*/3, /*Op*/1, GIMT_Encode2(AMDGPU::VReg_64RegClassID),
        GIR_BuildMI, /*InsnID*/2, /*Opcode*/GIMT_Encode2(TargetOpcode::COPY),
        GIR_AddTempRegister, /*InsnID*/2, /*TempRegID*/1, /*TempRegFlags*/GIMT_Encode2(RegState::Define),
        GIR_CopySubReg, /*NewInsnID*/2, /*OldInsnID*/2, /*OpIdx*/1, /*SubRegIdx*/GIMT_Encode2(3), // x
        GIR_ConstrainOperandRC, /*InsnID*/2, /*Op*/0, GIMT_Encode2(AMDGPU::VGPR_32RegClassID),
        GIR_ConstrainOperandRC, /*InsnID*/2, /*Op*/1, GIMT_Encode2(AMDGPU::VReg_64RegClassID),
        GIR_BuildMI, /*InsnID*/1, /*Opcode*/GIMT_Encode2(AMDGPU::V_BFI_B32_e64),
        GIR_AddTempRegister, /*InsnID*/1, /*TempRegID*/0, /*TempRegFlags*/GIMT_Encode2(RegState::Define),
        GIR_AddSimpleTempRegister, /*InsnID*/1, /*TempRegID*/1,
        GIR_AddSimpleTempRegister, /*InsnID*/1, /*TempRegID*/2,
        GIR_AddSimpleTempRegister, /*InsnID*/1, /*TempRegID*/3,
        GIR_ConstrainSelectedInstOperands, /*InsnID*/1,
        GIR_BuildMI, /*InsnID*/0, /*Opcode*/GIMT_Encode2(TargetOpcode::REG_SEQUENCE),
        GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/0, // DstI[dst]
        GIR_AddSimpleTempRegister, /*InsnID*/0, /*TempRegID*/0,
        GIR_AddImm8, /*InsnID*/0, /*SubRegIndex*/3,
        GIR_AddSimpleTempRegister, /*InsnID*/0, /*TempRegID*/4,
        GIR_AddImm8, /*InsnID*/0, /*SubRegIndex*/11,
        GIR_ConstrainOperandRC, /*InsnID*/0, /*Op*/0, GIMT_Encode2(AMDGPU::VReg_64RegClassID),
        GIR_ConstrainOperandRC, /*InsnID*/0, /*Op*/1, GIMT_Encode2(AMDGPU::VGPR_32RegClassID),
        GIR_ConstrainOperandRC, /*InsnID*/0, /*Op*/3, GIMT_Encode2(AMDGPU::VGPR_32RegClassID),
        GIR_EraseFromParent, /*InsnID*/0,
        // GIR_Coverage, 9882,
        GIR_Done,
      // Label 339: @25409
      GIM_Try, /*On fail goto*//*Label 340*/ GIMT_Encode4(25734), // Rule ID 9881 //
        GIM_CheckRegBankForClass, /*MI*/0, /*Op*/0, /*RC*/GIMT_Encode2(AMDGPU::VReg_64RegClassID),
        GIM_RecordInsnIgnoreCopies, /*DefineMI*/1, /*MI*/0, /*OpIdx*/1, // MIs[1]
        GIM_CheckOpcode, /*MI*/1, GIMT_Encode2(TargetOpcode::G_AND),
        GIM_CheckType, /*MI*/1, /*Op*/1, /*Type*/GILLT_s64,
        GIM_CheckType, /*MI*/1, /*Op*/2, /*Type*/GILLT_s64,
        GIM_RecordInsnIgnoreCopies, /*DefineMI*/2, /*MI*/1, /*OpIdx*/2, // MIs[2]
        GIM_CheckOpcode, /*MI*/2, GIMT_Encode2(TargetOpcode::G_XOR),
        GIM_CheckType, /*MI*/2, /*Op*/1, /*Type*/GILLT_s64,
        GIM_CheckType, /*MI*/2, /*Op*/2, /*Type*/GILLT_s64,
        GIM_CheckConstantInt8, /*MI*/2, /*Op*/2, uint8_t(-1),
        GIM_RecordInsnIgnoreCopies, /*DefineMI*/3, /*MI*/0, /*OpIdx*/2, // MIs[3]
        GIM_CheckOpcode, /*MI*/3, GIMT_Encode2(TargetOpcode::G_AND),
        GIM_CheckType, /*MI*/3, /*Op*/1, /*Type*/GILLT_s64,
        // MIs[3] x
        GIM_CheckIsSameOperandIgnoreCopies, /*MI*/3, /*OpIdx*/2, /*OtherMI*/2, /*OtherOpIdx*/1,
        GIM_CheckCxxInsnPredicate, /*MI*/0, /*FnId*/GIMT_Encode2(GICXXPred_MI_Predicate_anonymous_22557),
        GIM_CheckIsSafeToFold, /*InsnID*/1,
        GIM_CheckIsSafeToFold, /*InsnID*/2,
        GIM_CheckIsSafeToFold, /*InsnID*/3,
        // (or:{ *:[i64] } (and:{ *:[i64] } i64:{ *:[i64] }:$z, (xor:{ *:[i64] } i64:{ *:[i64] }:$x, -1:{ *:[i64] })), (and:{ *:[i64] } i64:{ *:[i64] }:$y, i64:{ *:[i64] }:$x))<<P:Predicate_anonymous_22557>>  =>  (REG_SEQUENCE:{ *:[i64] } VReg_64:{ *:[i32] }, (V_BFI_B32_e64:{ *:[i16] } (EXTRACT_SUBREG:{ *:[i32] } VReg_64:{ *:[i64] }:$x, sub0:{ *:[i32] }), (EXTRACT_SUBREG:{ *:[i32] } VReg_64:{ *:[i64] }:$y, sub0:{ *:[i32] }), (EXTRACT_SUBREG:{ *:[i32] } VReg_64:{ *:[i64] }:$z, sub0:{ *:[i32] })), sub0:{ *:[i32] }, (V_BFI_B32_e64:{ *:[i16] } (EXTRACT_SUBREG:{ *:[i32] } VReg_64:{ *:[i64] }:$x, sub1:{ *:[i32] }), (EXTRACT_SUBREG:{ *:[i32] } VReg_64:{ *:[i64] }:$y, sub1:{ *:[i32] }), (EXTRACT_SUBREG:{ *:[i32] } VReg_64:{ *:[i64] }:$z, sub1:{ *:[i32] })), sub1:{ *:[i32] })
        GIR_MakeTempReg, /*TempRegID*/0, /*TypeID*/GILLT_s16,
        GIR_MakeTempReg, /*TempRegID*/1, /*TypeID*/GILLT_s32,
        GIR_MakeTempReg, /*TempRegID*/2, /*TypeID*/GILLT_s32,
        GIR_MakeTempReg, /*TempRegID*/3, /*TypeID*/GILLT_s32,
        GIR_MakeTempReg, /*TempRegID*/4, /*TypeID*/GILLT_s16,
        GIR_MakeTempReg, /*TempRegID*/5, /*TypeID*/GILLT_s32,
        GIR_MakeTempReg, /*TempRegID*/6, /*TypeID*/GILLT_s32,
        GIR_MakeTempReg, /*TempRegID*/7, /*TypeID*/GILLT_s32,
        GIR_BuildMI, /*InsnID*/8, /*Opcode*/GIMT_Encode2(TargetOpcode::COPY),
        GIR_AddTempRegister, /*InsnID*/8, /*TempRegID*/7, /*TempRegFlags*/GIMT_Encode2(RegState::Define),
        GIR_CopySubReg, /*NewInsnID*/8, /*OldInsnID*/1, /*OpIdx*/1, /*SubRegIdx*/GIMT_Encode2(11), // z
        GIR_ConstrainOperandRC, /*InsnID*/8, /*Op*/0, GIMT_Encode2(AMDGPU::VGPR_32RegClassID),
        GIR_ConstrainOperandRC, /*InsnID*/8, /*Op*/1, GIMT_Encode2(AMDGPU::VReg_64RegClassID),
        GIR_BuildMI, /*InsnID*/7, /*Opcode*/GIMT_Encode2(TargetOpcode::COPY),
        GIR_AddTempRegister, /*InsnID*/7, /*TempRegID*/6, /*TempRegFlags*/GIMT_Encode2(RegState::Define),
        GIR_CopySubReg, /*NewInsnID*/7, /*OldInsnID*/3, /*OpIdx*/1, /*SubRegIdx*/GIMT_Encode2(11), // y
        GIR_ConstrainOperandRC, /*InsnID*/7, /*Op*/0, GIMT_Encode2(AMDGPU::VGPR_32RegClassID),
        GIR_ConstrainOperandRC, /*InsnID*/7, /*Op*/1, GIMT_Encode2(AMDGPU::VReg_64RegClassID),
        GIR_BuildMI, /*InsnID*/6, /*Opcode*/GIMT_Encode2(TargetOpcode::COPY),
        GIR_AddTempRegister, /*InsnID*/6, /*TempRegID*/5, /*TempRegFlags*/GIMT_Encode2(RegState::Define),
        GIR_CopySubReg, /*NewInsnID*/6, /*OldInsnID*/2, /*OpIdx*/1, /*SubRegIdx*/GIMT_Encode2(11), // x
        GIR_ConstrainOperandRC, /*InsnID*/6, /*Op*/0, GIMT_Encode2(AMDGPU::VGPR_32RegClassID),
        GIR_ConstrainOperandRC, /*InsnID*/6, /*Op*/1, GIMT_Encode2(AMDGPU::VReg_64RegClassID),
        GIR_BuildMI, /*InsnID*/5, /*Opcode*/GIMT_Encode2(AMDGPU::V_BFI_B32_e64),
        GIR_AddTempRegister, /*InsnID*/5, /*TempRegID*/4, /*TempRegFlags*/GIMT_Encode2(RegState::Define),
        GIR_AddSimpleTempRegister, /*InsnID*/5, /*TempRegID*/5,
        GIR_AddSimpleTempRegister, /*InsnID*/5, /*TempRegID*/6,
        GIR_AddSimpleTempRegister, /*InsnID*/5, /*TempRegID*/7,
        GIR_ConstrainSelectedInstOperands, /*InsnID*/5,
        GIR_BuildMI, /*InsnID*/4, /*Opcode*/GIMT_Encode2(TargetOpcode::COPY),
        GIR_AddTempRegister, /*InsnID*/4, /*TempRegID*/3, /*TempRegFlags*/GIMT_Encode2(RegState::Define),
        GIR_CopySubReg, /*NewInsnID*/4, /*OldInsnID*/1, /*OpIdx*/1, /*SubRegIdx*/GIMT_Encode2(3), // z
        GIR_ConstrainOperandRC, /*InsnID*/4, /*Op*/0, GIMT_Encode2(AMDGPU::VGPR_32RegClassID),
        GIR_ConstrainOperandRC, /*InsnID*/4, /*Op*/1, GIMT_Encode2(AMDGPU::VReg_64RegClassID),
        GIR_BuildMI, /*InsnID*/3, /*Opcode*/GIMT_Encode2(TargetOpcode::COPY),
        GIR_AddTempRegister, /*InsnID*/3, /*TempRegID*/2, /*TempRegFlags*/GIMT_Encode2(RegState::Define),
        GIR_CopySubReg, /*NewInsnID*/3, /*OldInsnID*/3, /*OpIdx*/1, /*SubRegIdx*/GIMT_Encode2(3), // y
        GIR_ConstrainOperandRC, /*InsnID*/3, /*Op*/0, GIMT_Encode2(AMDGPU::VGPR_32RegClassID),
        GIR_ConstrainOperandRC, /*InsnID*/3, /*Op*/1, GIMT_Encode2(AMDGPU::VReg_64RegClassID),
        GIR_BuildMI, /*InsnID*/2, /*Opcode*/GIMT_Encode2(TargetOpcode::COPY),
        GIR_AddTempRegister, /*InsnID*/2, /*TempRegID*/1, /*TempRegFlags*/GIMT_Encode2(RegState::Define),
        GIR_CopySubReg, /*NewInsnID*/2, /*OldInsnID*/2, /*OpIdx*/1, /*SubRegIdx*/GIMT_Encode2(3), // x
        GIR_ConstrainOperandRC, /*InsnID*/2, /*Op*/0, GIMT_Encode2(AMDGPU::VGPR_32RegClassID),
        GIR_ConstrainOperandRC, /*InsnID*/2, /*Op*/1, GIMT_Encode2(AMDGPU::VReg_64RegClassID),
        GIR_BuildMI, /*InsnID*/1, /*Opcode*/GIMT_Encode2(AMDGPU::V_BFI_B32_e64),
        GIR_AddTempRegister, /*InsnID*/1, /*TempRegID*/0, /*TempRegFlags*/GIMT_Encode2(RegState::Define),
        GIR_AddSimpleTempRegister, /*InsnID*/1, /*TempRegID*/1,
        GIR_AddSimpleTempRegister, /*InsnID*/1, /*TempRegID*/2,
        GIR_AddSimpleTempRegister, /*InsnID*/1, /*TempRegID*/3,
        GIR_ConstrainSelectedInstOperands, /*InsnID*/1,
        GIR_BuildMI, /*InsnID*/0, /*Opcode*/GIMT_Encode2(TargetOpcode::REG_SEQUENCE),
        GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/0, // DstI[dst]
        GIR_AddSimpleTempRegister, /*InsnID*/0, /*TempRegID*/0,
        GIR_AddImm8, /*InsnID*/0, /*SubRegIndex*/3,
        GIR_AddSimpleTempRegister, /*InsnID*/0, /*TempRegID*/4,
        GIR_AddImm8, /*InsnID*/0, /*SubRegIndex*/11,
        GIR_ConstrainOperandRC, /*InsnID*/0, /*Op*/0, GIMT_Encode2(AMDGPU::VReg_64RegClassID),
        GIR_ConstrainOperandRC, /*InsnID*/0, /*Op*/1, GIMT_Encode2(AMDGPU::VGPR_32RegClassID),
        GIR_ConstrainOperandRC, /*InsnID*/0, /*Op*/3, GIMT_Encode2(AMDGPU::VGPR_32RegClassID),
        GIR_EraseFromParent, /*InsnID*/0,
        // GIR_Coverage, 9881,
        GIR_Done,
      // Label 340: @25734
      GIM_Try, /*On fail goto*//*Label 341*/ GIMT_Encode4(26059), // Rule ID 9878 //
        GIM_CheckRegBankForClass, /*MI*/0, /*Op*/0, /*RC*/GIMT_Encode2(AMDGPU::VReg_64RegClassID),
        GIM_RecordInsnIgnoreCopies, /*DefineMI*/1, /*MI*/0, /*OpIdx*/1, // MIs[1]
        GIM_CheckOpcode, /*MI*/1, GIMT_Encode2(TargetOpcode::G_AND),
        GIM_CheckType, /*MI*/1, /*Op*/1, /*Type*/GILLT_s64,
        GIM_CheckType, /*MI*/1, /*Op*/2, /*Type*/GILLT_s64,
        GIM_RecordInsnIgnoreCopies, /*DefineMI*/2, /*MI*/0, /*OpIdx*/2, // MIs[2]
        GIM_CheckOpcode, /*MI*/2, GIMT_Encode2(TargetOpcode::G_AND),
        GIM_CheckType, /*MI*/2, /*Op*/1, /*Type*/GILLT_s64,
        GIM_CheckType, /*MI*/2, /*Op*/2, /*Type*/GILLT_s64,
        GIM_RecordInsnIgnoreCopies, /*DefineMI*/3, /*MI*/2, /*OpIdx*/1, // MIs[3]
        GIM_CheckOpcode, /*MI*/3, GIMT_Encode2(TargetOpcode::G_XOR),
        GIM_CheckType, /*MI*/3, /*Op*/2, /*Type*/GILLT_s64,
        // MIs[3] x
        GIM_CheckIsSameOperandIgnoreCopies, /*MI*/3, /*OpIdx*/1, /*OtherMI*/1, /*OtherOpIdx*/2,
        GIM_CheckConstantInt8, /*MI*/3, /*Op*/2, uint8_t(-1),
        GIM_CheckCxxInsnPredicate, /*MI*/0, /*FnId*/GIMT_Encode2(GICXXPred_MI_Predicate_anonymous_22557),
        GIM_CheckIsSafeToFold, /*InsnID*/1,
        GIM_CheckIsSafeToFold, /*InsnID*/2,
        GIM_CheckIsSafeToFold, /*InsnID*/3,
        // (or:{ *:[i64] } (and:{ *:[i64] } i64:{ *:[i64] }:$y, i64:{ *:[i64] }:$x), (and:{ *:[i64] } (xor:{ *:[i64] } i64:{ *:[i64] }:$x, -1:{ *:[i64] }), i64:{ *:[i64] }:$z))<<P:Predicate_anonymous_22557>>  =>  (REG_SEQUENCE:{ *:[i64] } VReg_64:{ *:[i32] }, (V_BFI_B32_e64:{ *:[i16] } (EXTRACT_SUBREG:{ *:[i32] } VReg_64:{ *:[i64] }:$x, sub0:{ *:[i32] }), (EXTRACT_SUBREG:{ *:[i32] } VReg_64:{ *:[i64] }:$y, sub0:{ *:[i32] }), (EXTRACT_SUBREG:{ *:[i32] } VReg_64:{ *:[i64] }:$z, sub0:{ *:[i32] })), sub0:{ *:[i32] }, (V_BFI_B32_e64:{ *:[i16] } (EXTRACT_SUBREG:{ *:[i32] } VReg_64:{ *:[i64] }:$x, sub1:{ *:[i32] }), (EXTRACT_SUBREG:{ *:[i32] } VReg_64:{ *:[i64] }:$y, sub1:{ *:[i32] }), (EXTRACT_SUBREG:{ *:[i32] } VReg_64:{ *:[i64] }:$z, sub1:{ *:[i32] })), sub1:{ *:[i32] })
        GIR_MakeTempReg, /*TempRegID*/0, /*TypeID*/GILLT_s16,
        GIR_MakeTempReg, /*TempRegID*/1, /*TypeID*/GILLT_s32,
        GIR_MakeTempReg, /*TempRegID*/2, /*TypeID*/GILLT_s32,
        GIR_MakeTempReg, /*TempRegID*/3, /*TypeID*/GILLT_s32,
        GIR_MakeTempReg, /*TempRegID*/4, /*TypeID*/GILLT_s16,
        GIR_MakeTempReg, /*TempRegID*/5, /*TypeID*/GILLT_s32,
        GIR_MakeTempReg, /*TempRegID*/6, /*TypeID*/GILLT_s32,
        GIR_MakeTempReg, /*TempRegID*/7, /*TypeID*/GILLT_s32,
        GIR_BuildMI, /*InsnID*/8, /*Opcode*/GIMT_Encode2(TargetOpcode::COPY),
        GIR_AddTempRegister, /*InsnID*/8, /*TempRegID*/7, /*TempRegFlags*/GIMT_Encode2(RegState::Define),
        GIR_CopySubReg, /*NewInsnID*/8, /*OldInsnID*/2, /*OpIdx*/2, /*SubRegIdx*/GIMT_Encode2(11), // z
        GIR_ConstrainOperandRC, /*InsnID*/8, /*Op*/0, GIMT_Encode2(AMDGPU::VGPR_32RegClassID),
        GIR_ConstrainOperandRC, /*InsnID*/8, /*Op*/1, GIMT_Encode2(AMDGPU::VReg_64RegClassID),
        GIR_BuildMI, /*InsnID*/7, /*Opcode*/GIMT_Encode2(TargetOpcode::COPY),
        GIR_AddTempRegister, /*InsnID*/7, /*TempRegID*/6, /*TempRegFlags*/GIMT_Encode2(RegState::Define),
        GIR_CopySubReg, /*NewInsnID*/7, /*OldInsnID*/1, /*OpIdx*/1, /*SubRegIdx*/GIMT_Encode2(11), // y
        GIR_ConstrainOperandRC, /*InsnID*/7, /*Op*/0, GIMT_Encode2(AMDGPU::VGPR_32RegClassID),
        GIR_ConstrainOperandRC, /*InsnID*/7, /*Op*/1, GIMT_Encode2(AMDGPU::VReg_64RegClassID),
        GIR_BuildMI, /*InsnID*/6, /*Opcode*/GIMT_Encode2(TargetOpcode::COPY),
        GIR_AddTempRegister, /*InsnID*/6, /*TempRegID*/5, /*TempRegFlags*/GIMT_Encode2(RegState::Define),
        GIR_CopySubReg, /*NewInsnID*/6, /*OldInsnID*/1, /*OpIdx*/2, /*SubRegIdx*/GIMT_Encode2(11), // x
        GIR_ConstrainOperandRC, /*InsnID*/6, /*Op*/0, GIMT_Encode2(AMDGPU::VGPR_32RegClassID),
        GIR_ConstrainOperandRC, /*InsnID*/6, /*Op*/1, GIMT_Encode2(AMDGPU::VReg_64RegClassID),
        GIR_BuildMI, /*InsnID*/5, /*Opcode*/GIMT_Encode2(AMDGPU::V_BFI_B32_e64),
        GIR_AddTempRegister, /*InsnID*/5, /*TempRegID*/4, /*TempRegFlags*/GIMT_Encode2(RegState::Define),
        GIR_AddSimpleTempRegister, /*InsnID*/5, /*TempRegID*/5,
        GIR_AddSimpleTempRegister, /*InsnID*/5, /*TempRegID*/6,
        GIR_AddSimpleTempRegister, /*InsnID*/5, /*TempRegID*/7,
        GIR_ConstrainSelectedInstOperands, /*InsnID*/5,
        GIR_BuildMI, /*InsnID*/4, /*Opcode*/GIMT_Encode2(TargetOpcode::COPY),
        GIR_AddTempRegister, /*InsnID*/4, /*TempRegID*/3, /*TempRegFlags*/GIMT_Encode2(RegState::Define),
        GIR_CopySubReg, /*NewInsnID*/4, /*OldInsnID*/2, /*OpIdx*/2, /*SubRegIdx*/GIMT_Encode2(3), // z
        GIR_ConstrainOperandRC, /*InsnID*/4, /*Op*/0, GIMT_Encode2(AMDGPU::VGPR_32RegClassID),
        GIR_ConstrainOperandRC, /*InsnID*/4, /*Op*/1, GIMT_Encode2(AMDGPU::VReg_64RegClassID),
        GIR_BuildMI, /*InsnID*/3, /*Opcode*/GIMT_Encode2(TargetOpcode::COPY),
        GIR_AddTempRegister, /*InsnID*/3, /*TempRegID*/2, /*TempRegFlags*/GIMT_Encode2(RegState::Define),
        GIR_CopySubReg, /*NewInsnID*/3, /*OldInsnID*/1, /*OpIdx*/1, /*SubRegIdx*/GIMT_Encode2(3), // y
        GIR_ConstrainOperandRC, /*InsnID*/3, /*Op*/0, GIMT_Encode2(AMDGPU::VGPR_32RegClassID),
        GIR_ConstrainOperandRC, /*InsnID*/3, /*Op*/1, GIMT_Encode2(AMDGPU::VReg_64RegClassID),
        GIR_BuildMI, /*InsnID*/2, /*Opcode*/GIMT_Encode2(TargetOpcode::COPY),
        GIR_AddTempRegister, /*InsnID*/2, /*TempRegID*/1, /*TempRegFlags*/GIMT_Encode2(RegState::Define),
        GIR_CopySubReg, /*NewInsnID*/2, /*OldInsnID*/1, /*OpIdx*/2, /*SubRegIdx*/GIMT_Encode2(3), // x
        GIR_ConstrainOperandRC, /*InsnID*/2, /*Op*/0, GIMT_Encode2(AMDGPU::VGPR_32RegClassID),
        GIR_ConstrainOperandRC, /*InsnID*/2, /*Op*/1, GIMT_Encode2(AMDGPU::VReg_64RegClassID),
        GIR_BuildMI, /*InsnID*/1, /*Opcode*/GIMT_Encode2(AMDGPU::V_BFI_B32_e64),
        GIR_AddTempRegister, /*InsnID*/1, /*TempRegID*/0, /*TempRegFlags*/GIMT_Encode2(RegState::Define),
        GIR_AddSimpleTempRegister, /*InsnID*/1, /*TempRegID*/1,
        GIR_AddSimpleTempRegister, /*InsnID*/1, /*TempRegID*/2,
        GIR_AddSimpleTempRegister, /*InsnID*/1, /*TempRegID*/3,
        GIR_ConstrainSelectedInstOperands, /*InsnID*/1,
        GIR_BuildMI, /*InsnID*/0, /*Opcode*/GIMT_Encode2(TargetOpcode::REG_SEQUENCE),
        GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/0, // DstI[dst]
        GIR_AddSimpleTempRegister, /*InsnID*/0, /*TempRegID*/0,
        GIR_AddImm8, /*InsnID*/0, /*SubRegIndex*/3,
        GIR_AddSimpleTempRegister, /*InsnID*/0, /*TempRegID*/4,
        GIR_AddImm8, /*InsnID*/0, /*SubRegIndex*/11,
        GIR_ConstrainOperandRC, /*InsnID*/0, /*Op*/0, GIMT_Encode2(AMDGPU::VReg_64RegClassID),
        GIR_ConstrainOperandRC, /*InsnID*/0, /*Op*/1, GIMT_Encode2(AMDGPU::VGPR_32RegClassID),
        GIR_ConstrainOperandRC, /*InsnID*/0, /*Op*/3, GIMT_Encode2(AMDGPU::VGPR_32RegClassID),
        GIR_EraseFromParent, /*InsnID*/0,
        // GIR_Coverage, 9878,
        GIR_Done,
      // Label 341: @26059
      GIM_Try, /*On fail goto*//*Label 342*/ GIMT_Encode4(26384), // Rule ID 9880 //
        GIM_CheckRegBankForClass, /*MI*/0, /*Op*/0, /*RC*/GIMT_Encode2(AMDGPU::VReg_64RegClassID),
        GIM_RecordInsnIgnoreCopies, /*DefineMI*/1, /*MI*/0, /*OpIdx*/1, // MIs[1]
        GIM_CheckOpcode, /*MI*/1, GIMT_Encode2(TargetOpcode::G_AND),
        GIM_CheckType, /*MI*/1, /*Op*/1, /*Type*/GILLT_s64,
        GIM_CheckType, /*MI*/1, /*Op*/2, /*Type*/GILLT_s64,
        GIM_RecordInsnIgnoreCopies, /*DefineMI*/2, /*MI*/0, /*OpIdx*/2, // MIs[2]
        GIM_CheckOpcode, /*MI*/2, GIMT_Encode2(TargetOpcode::G_AND),
        GIM_CheckType, /*MI*/2, /*Op*/1, /*Type*/GILLT_s64,
        GIM_CheckType, /*MI*/2, /*Op*/2, /*Type*/GILLT_s64,
        GIM_RecordInsnIgnoreCopies, /*DefineMI*/3, /*MI*/2, /*OpIdx*/1, // MIs[3]
        GIM_CheckOpcode, /*MI*/3, GIMT_Encode2(TargetOpcode::G_XOR),
        GIM_CheckType, /*MI*/3, /*Op*/2, /*Type*/GILLT_s64,
        // MIs[3] x
        GIM_CheckIsSameOperandIgnoreCopies, /*MI*/3, /*OpIdx*/1, /*OtherMI*/1, /*OtherOpIdx*/1,
        GIM_CheckConstantInt8, /*MI*/3, /*Op*/2, uint8_t(-1),
        GIM_CheckCxxInsnPredicate, /*MI*/0, /*FnId*/GIMT_Encode2(GICXXPred_MI_Predicate_anonymous_22557),
        GIM_CheckIsSafeToFold, /*InsnID*/1,
        GIM_CheckIsSafeToFold, /*InsnID*/2,
        GIM_CheckIsSafeToFold, /*InsnID*/3,
        // (or:{ *:[i64] } (and:{ *:[i64] } i64:{ *:[i64] }:$x, i64:{ *:[i64] }:$y), (and:{ *:[i64] } (xor:{ *:[i64] } i64:{ *:[i64] }:$x, -1:{ *:[i64] }), i64:{ *:[i64] }:$z))<<P:Predicate_anonymous_22557>>  =>  (REG_SEQUENCE:{ *:[i64] } VReg_64:{ *:[i32] }, (V_BFI_B32_e64:{ *:[i16] } (EXTRACT_SUBREG:{ *:[i32] } VReg_64:{ *:[i64] }:$x, sub0:{ *:[i32] }), (EXTRACT_SUBREG:{ *:[i32] } VReg_64:{ *:[i64] }:$y, sub0:{ *:[i32] }), (EXTRACT_SUBREG:{ *:[i32] } VReg_64:{ *:[i64] }:$z, sub0:{ *:[i32] })), sub0:{ *:[i32] }, (V_BFI_B32_e64:{ *:[i16] } (EXTRACT_SUBREG:{ *:[i32] } VReg_64:{ *:[i64] }:$x, sub1:{ *:[i32] }), (EXTRACT_SUBREG:{ *:[i32] } VReg_64:{ *:[i64] }:$y, sub1:{ *:[i32] }), (EXTRACT_SUBREG:{ *:[i32] } VReg_64:{ *:[i64] }:$z, sub1:{ *:[i32] })), sub1:{ *:[i32] })
        GIR_MakeTempReg, /*TempRegID*/0, /*TypeID*/GILLT_s16,
        GIR_MakeTempReg, /*TempRegID*/1, /*TypeID*/GILLT_s32,
        GIR_MakeTempReg, /*TempRegID*/2, /*TypeID*/GILLT_s32,
        GIR_MakeTempReg, /*TempRegID*/3, /*TypeID*/GILLT_s32,
        GIR_MakeTempReg, /*TempRegID*/4, /*TypeID*/GILLT_s16,
        GIR_MakeTempReg, /*TempRegID*/5, /*TypeID*/GILLT_s32,
        GIR_MakeTempReg, /*TempRegID*/6, /*TypeID*/GILLT_s32,
        GIR_MakeTempReg, /*TempRegID*/7, /*TypeID*/GILLT_s32,
        GIR_BuildMI, /*InsnID*/8, /*Opcode*/GIMT_Encode2(TargetOpcode::COPY),
        GIR_AddTempRegister, /*InsnID*/8, /*TempRegID*/7, /*TempRegFlags*/GIMT_Encode2(RegState::Define),
        GIR_CopySubReg, /*NewInsnID*/8, /*OldInsnID*/2, /*OpIdx*/2, /*SubRegIdx*/GIMT_Encode2(11), // z
        GIR_ConstrainOperandRC, /*InsnID*/8, /*Op*/0, GIMT_Encode2(AMDGPU::VGPR_32RegClassID),
        GIR_ConstrainOperandRC, /*InsnID*/8, /*Op*/1, GIMT_Encode2(AMDGPU::VReg_64RegClassID),
        GIR_BuildMI, /*InsnID*/7, /*Opcode*/GIMT_Encode2(TargetOpcode::COPY),
        GIR_AddTempRegister, /*InsnID*/7, /*TempRegID*/6, /*TempRegFlags*/GIMT_Encode2(RegState::Define),
        GIR_CopySubReg, /*NewInsnID*/7, /*OldInsnID*/1, /*OpIdx*/2, /*SubRegIdx*/GIMT_Encode2(11), // y
        GIR_ConstrainOperandRC, /*InsnID*/7, /*Op*/0, GIMT_Encode2(AMDGPU::VGPR_32RegClassID),
        GIR_ConstrainOperandRC, /*InsnID*/7, /*Op*/1, GIMT_Encode2(AMDGPU::VReg_64RegClassID),
        GIR_BuildMI, /*InsnID*/6, /*Opcode*/GIMT_Encode2(TargetOpcode::COPY),
        GIR_AddTempRegister, /*InsnID*/6, /*TempRegID*/5, /*TempRegFlags*/GIMT_Encode2(RegState::Define),
        GIR_CopySubReg, /*NewInsnID*/6, /*OldInsnID*/1, /*OpIdx*/1, /*SubRegIdx*/GIMT_Encode2(11), // x
        GIR_ConstrainOperandRC, /*InsnID*/6, /*Op*/0, GIMT_Encode2(AMDGPU::VGPR_32RegClassID),
        GIR_ConstrainOperandRC, /*InsnID*/6, /*Op*/1, GIMT_Encode2(AMDGPU::VReg_64RegClassID),
        GIR_BuildMI, /*InsnID*/5, /*Opcode*/GIMT_Encode2(AMDGPU::V_BFI_B32_e64),
        GIR_AddTempRegister, /*InsnID*/5, /*TempRegID*/4, /*TempRegFlags*/GIMT_Encode2(RegState::Define),
        GIR_AddSimpleTempRegister, /*InsnID*/5, /*TempRegID*/5,
        GIR_AddSimpleTempRegister, /*InsnID*/5, /*TempRegID*/6,
        GIR_AddSimpleTempRegister, /*InsnID*/5, /*TempRegID*/7,
        GIR_ConstrainSelectedInstOperands, /*InsnID*/5,
        GIR_BuildMI, /*InsnID*/4, /*Opcode*/GIMT_Encode2(TargetOpcode::COPY),
        GIR_AddTempRegister, /*InsnID*/4, /*TempRegID*/3, /*TempRegFlags*/GIMT_Encode2(RegState::Define),
        GIR_CopySubReg, /*NewInsnID*/4, /*OldInsnID*/2, /*OpIdx*/2, /*SubRegIdx*/GIMT_Encode2(3), // z
        GIR_ConstrainOperandRC, /*InsnID*/4, /*Op*/0, GIMT_Encode2(AMDGPU::VGPR_32RegClassID),
        GIR_ConstrainOperandRC, /*InsnID*/4, /*Op*/1, GIMT_Encode2(AMDGPU::VReg_64RegClassID),
        GIR_BuildMI, /*InsnID*/3, /*Opcode*/GIMT_Encode2(TargetOpcode::COPY),
        GIR_AddTempRegister, /*InsnID*/3, /*TempRegID*/2, /*TempRegFlags*/GIMT_Encode2(RegState::Define),
        GIR_CopySubReg, /*NewInsnID*/3, /*OldInsnID*/1, /*OpIdx*/2, /*SubRegIdx*/GIMT_Encode2(3), // y
        GIR_ConstrainOperandRC, /*InsnID*/3, /*Op*/0, GIMT_Encode2(AMDGPU::VGPR_32RegClassID),
        GIR_ConstrainOperandRC, /*InsnID*/3, /*Op*/1, GIMT_Encode2(AMDGPU::VReg_64RegClassID),
        GIR_BuildMI, /*InsnID*/2, /*Opcode*/GIMT_Encode2(TargetOpcode::COPY),
        GIR_AddTempRegister, /*InsnID*/2, /*TempRegID*/1, /*TempRegFlags*/GIMT_Encode2(RegState::Define),
        GIR_CopySubReg, /*NewInsnID*/2, /*OldInsnID*/1, /*OpIdx*/1, /*SubRegIdx*/GIMT_Encode2(3), // x
        GIR_ConstrainOperandRC, /*InsnID*/2, /*Op*/0, GIMT_Encode2(AMDGPU::VGPR_32RegClassID),
        GIR_ConstrainOperandRC, /*InsnID*/2, /*Op*/1, GIMT_Encode2(AMDGPU::VReg_64RegClassID),
        GIR_BuildMI, /*InsnID*/1, /*Opcode*/GIMT_Encode2(AMDGPU::V_BFI_B32_e64),
        GIR_AddTempRegister, /*InsnID*/1, /*TempRegID*/0, /*TempRegFlags*/GIMT_Encode2(RegState::Define),
        GIR_AddSimpleTempRegister, /*InsnID*/1, /*TempRegID*/1,
        GIR_AddSimpleTempRegister, /*InsnID*/1, /*TempRegID*/2,
        GIR_AddSimpleTempRegister, /*InsnID*/1, /*TempRegID*/3,
        GIR_ConstrainSelectedInstOperands, /*InsnID*/1,
        GIR_BuildMI, /*InsnID*/0, /*Opcode*/GIMT_Encode2(TargetOpcode::REG_SEQUENCE),
        GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/0, // DstI[dst]
        GIR_AddSimpleTempRegister, /*InsnID*/0, /*TempRegID*/0,
        GIR_AddImm8, /*InsnID*/0, /*SubRegIndex*/3,
        GIR_AddSimpleTempRegister, /*InsnID*/0, /*TempRegID*/4,
        GIR_AddImm8, /*InsnID*/0, /*SubRegIndex*/11,
        GIR_ConstrainOperandRC, /*InsnID*/0, /*Op*/0, GIMT_Encode2(AMDGPU::VReg_64RegClassID),
        GIR_ConstrainOperandRC, /*InsnID*/0, /*Op*/1, GIMT_Encode2(AMDGPU::VGPR_32RegClassID),
        GIR_ConstrainOperandRC, /*InsnID*/0, /*Op*/3, GIMT_Encode2(AMDGPU::VGPR_32RegClassID),
        GIR_EraseFromParent, /*InsnID*/0,
        // GIR_Coverage, 9880,
        GIR_Done,
      // Label 342: @26384
      GIM_Try, /*On fail goto*//*Label 343*/ GIMT_Encode4(26709), // Rule ID 6275 //
        GIM_CheckRegBankForClass, /*MI*/0, /*Op*/0, /*RC*/GIMT_Encode2(AMDGPU::VReg_64RegClassID),
        GIM_RecordInsnIgnoreCopies, /*DefineMI*/1, /*MI*/0, /*OpIdx*/1, // MIs[1]
        GIM_CheckOpcode, /*MI*/1, GIMT_Encode2(TargetOpcode::G_AND),
        GIM_CheckType, /*MI*/1, /*Op*/1, /*Type*/GILLT_s64,
        GIM_CheckType, /*MI*/1, /*Op*/2, /*Type*/GILLT_s64,
        GIM_RecordInsnIgnoreCopies, /*DefineMI*/2, /*MI*/0, /*OpIdx*/2, // MIs[2]
        GIM_CheckOpcode, /*MI*/2, GIMT_Encode2(TargetOpcode::G_AND),
        GIM_CheckType, /*MI*/2, /*Op*/1, /*Type*/GILLT_s64,
        GIM_CheckType, /*MI*/2, /*Op*/2, /*Type*/GILLT_s64,
        GIM_RecordInsnIgnoreCopies, /*DefineMI*/3, /*MI*/2, /*OpIdx*/2, // MIs[3]
        GIM_CheckOpcode, /*MI*/3, GIMT_Encode2(TargetOpcode::G_XOR),
        GIM_CheckType, /*MI*/3, /*Op*/2, /*Type*/GILLT_s64,
        // MIs[3] x
        GIM_CheckIsSameOperandIgnoreCopies, /*MI*/3, /*OpIdx*/1, /*OtherMI*/1, /*OtherOpIdx*/2,
        GIM_CheckConstantInt8, /*MI*/3, /*Op*/2, uint8_t(-1),
        GIM_CheckCxxInsnPredicate, /*MI*/0, /*FnId*/GIMT_Encode2(GICXXPred_MI_Predicate_anonymous_22557),
        GIM_CheckIsSafeToFold, /*InsnID*/1,
        GIM_CheckIsSafeToFold, /*InsnID*/2,
        GIM_CheckIsSafeToFold, /*InsnID*/3,
        // (or:{ *:[i64] } (and:{ *:[i64] } i64:{ *:[i64] }:$y, i64:{ *:[i64] }:$x), (and:{ *:[i64] } i64:{ *:[i64] }:$z, (xor:{ *:[i64] } i64:{ *:[i64] }:$x, -1:{ *:[i64] })))<<P:Predicate_anonymous_22557>>  =>  (REG_SEQUENCE:{ *:[i64] } VReg_64:{ *:[i32] }, (V_BFI_B32_e64:{ *:[i16] } (EXTRACT_SUBREG:{ *:[i32] } VReg_64:{ *:[i64] }:$x, sub0:{ *:[i32] }), (EXTRACT_SUBREG:{ *:[i32] } VReg_64:{ *:[i64] }:$y, sub0:{ *:[i32] }), (EXTRACT_SUBREG:{ *:[i32] } VReg_64:{ *:[i64] }:$z, sub0:{ *:[i32] })), sub0:{ *:[i32] }, (V_BFI_B32_e64:{ *:[i16] } (EXTRACT_SUBREG:{ *:[i32] } VReg_64:{ *:[i64] }:$x, sub1:{ *:[i32] }), (EXTRACT_SUBREG:{ *:[i32] } VReg_64:{ *:[i64] }:$y, sub1:{ *:[i32] }), (EXTRACT_SUBREG:{ *:[i32] } VReg_64:{ *:[i64] }:$z, sub1:{ *:[i32] })), sub1:{ *:[i32] })
        GIR_MakeTempReg, /*TempRegID*/0, /*TypeID*/GILLT_s16,
        GIR_MakeTempReg, /*TempRegID*/1, /*TypeID*/GILLT_s32,
        GIR_MakeTempReg, /*TempRegID*/2, /*TypeID*/GILLT_s32,
        GIR_MakeTempReg, /*TempRegID*/3, /*TypeID*/GILLT_s32,
        GIR_MakeTempReg, /*TempRegID*/4, /*TypeID*/GILLT_s16,
        GIR_MakeTempReg, /*TempRegID*/5, /*TypeID*/GILLT_s32,
        GIR_MakeTempReg, /*TempRegID*/6, /*TypeID*/GILLT_s32,
        GIR_MakeTempReg, /*TempRegID*/7, /*TypeID*/GILLT_s32,
        GIR_BuildMI, /*InsnID*/8, /*Opcode*/GIMT_Encode2(TargetOpcode::COPY),
        GIR_AddTempRegister, /*InsnID*/8, /*TempRegID*/7, /*TempRegFlags*/GIMT_Encode2(RegState::Define),
        GIR_CopySubReg, /*NewInsnID*/8, /*OldInsnID*/2, /*OpIdx*/1, /*SubRegIdx*/GIMT_Encode2(11), // z
        GIR_ConstrainOperandRC, /*InsnID*/8, /*Op*/0, GIMT_Encode2(AMDGPU::VGPR_32RegClassID),
        GIR_ConstrainOperandRC, /*InsnID*/8, /*Op*/1, GIMT_Encode2(AMDGPU::VReg_64RegClassID),
        GIR_BuildMI, /*InsnID*/7, /*Opcode*/GIMT_Encode2(TargetOpcode::COPY),
        GIR_AddTempRegister, /*InsnID*/7, /*TempRegID*/6, /*TempRegFlags*/GIMT_Encode2(RegState::Define),
        GIR_CopySubReg, /*NewInsnID*/7, /*OldInsnID*/1, /*OpIdx*/1, /*SubRegIdx*/GIMT_Encode2(11), // y
        GIR_ConstrainOperandRC, /*InsnID*/7, /*Op*/0, GIMT_Encode2(AMDGPU::VGPR_32RegClassID),
        GIR_ConstrainOperandRC, /*InsnID*/7, /*Op*/1, GIMT_Encode2(AMDGPU::VReg_64RegClassID),
        GIR_BuildMI, /*InsnID*/6, /*Opcode*/GIMT_Encode2(TargetOpcode::COPY),
        GIR_AddTempRegister, /*InsnID*/6, /*TempRegID*/5, /*TempRegFlags*/GIMT_Encode2(RegState::Define),
        GIR_CopySubReg, /*NewInsnID*/6, /*OldInsnID*/1, /*OpIdx*/2, /*SubRegIdx*/GIMT_Encode2(11), // x
        GIR_ConstrainOperandRC, /*InsnID*/6, /*Op*/0, GIMT_Encode2(AMDGPU::VGPR_32RegClassID),
        GIR_ConstrainOperandRC, /*InsnID*/6, /*Op*/1, GIMT_Encode2(AMDGPU::VReg_64RegClassID),
        GIR_BuildMI, /*InsnID*/5, /*Opcode*/GIMT_Encode2(AMDGPU::V_BFI_B32_e64),
        GIR_AddTempRegister, /*InsnID*/5, /*TempRegID*/4, /*TempRegFlags*/GIMT_Encode2(RegState::Define),
        GIR_AddSimpleTempRegister, /*InsnID*/5, /*TempRegID*/5,
        GIR_AddSimpleTempRegister, /*InsnID*/5, /*TempRegID*/6,
        GIR_AddSimpleTempRegister, /*InsnID*/5, /*TempRegID*/7,
        GIR_ConstrainSelectedInstOperands, /*InsnID*/5,
        GIR_BuildMI, /*InsnID*/4, /*Opcode*/GIMT_Encode2(TargetOpcode::COPY),
        GIR_AddTempRegister, /*InsnID*/4, /*TempRegID*/3, /*TempRegFlags*/GIMT_Encode2(RegState::Define),
        GIR_CopySubReg, /*NewInsnID*/4, /*OldInsnID*/2, /*OpIdx*/1, /*SubRegIdx*/GIMT_Encode2(3), // z
        GIR_ConstrainOperandRC, /*InsnID*/4, /*Op*/0, GIMT_Encode2(AMDGPU::VGPR_32RegClassID),
        GIR_ConstrainOperandRC, /*InsnID*/4, /*Op*/1, GIMT_Encode2(AMDGPU::VReg_64RegClassID),
        GIR_BuildMI, /*InsnID*/3, /*Opcode*/GIMT_Encode2(TargetOpcode::COPY),
        GIR_AddTempRegister, /*InsnID*/3, /*TempRegID*/2, /*TempRegFlags*/GIMT_Encode2(RegState::Define),
        GIR_CopySubReg, /*NewInsnID*/3, /*OldInsnID*/1, /*OpIdx*/1, /*SubRegIdx*/GIMT_Encode2(3), // y
        GIR_ConstrainOperandRC, /*InsnID*/3, /*Op*/0, GIMT_Encode2(AMDGPU::VGPR_32RegClassID),
        GIR_ConstrainOperandRC, /*InsnID*/3, /*Op*/1, GIMT_Encode2(AMDGPU::VReg_64RegClassID),
        GIR_BuildMI, /*InsnID*/2, /*Opcode*/GIMT_Encode2(TargetOpcode::COPY),
        GIR_AddTempRegister, /*InsnID*/2, /*TempRegID*/1, /*TempRegFlags*/GIMT_Encode2(RegState::Define),
        GIR_CopySubReg, /*NewInsnID*/2, /*OldInsnID*/1, /*OpIdx*/2, /*SubRegIdx*/GIMT_Encode2(3), // x
        GIR_ConstrainOperandRC, /*InsnID*/2, /*Op*/0, GIMT_Encode2(AMDGPU::VGPR_32RegClassID),
        GIR_ConstrainOperandRC, /*InsnID*/2, /*Op*/1, GIMT_Encode2(AMDGPU::VReg_64RegClassID),
        GIR_BuildMI, /*InsnID*/1, /*Opcode*/GIMT_Encode2(AMDGPU::V_BFI_B32_e64),
        GIR_AddTempRegister, /*InsnID*/1, /*TempRegID*/0, /*TempRegFlags*/GIMT_Encode2(RegState::Define),
        GIR_AddSimpleTempRegister, /*InsnID*/1, /*TempRegID*/1,
        GIR_AddSimpleTempRegister, /*InsnID*/1, /*TempRegID*/2,
        GIR_AddSimpleTempRegister, /*InsnID*/1, /*TempRegID*/3,
        GIR_ConstrainSelectedInstOperands, /*InsnID*/1,
        GIR_BuildMI, /*InsnID*/0, /*Opcode*/GIMT_Encode2(TargetOpcode::REG_SEQUENCE),
        GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/0, // DstI[dst]
        GIR_AddSimpleTempRegister, /*InsnID*/0, /*TempRegID*/0,
        GIR_AddImm8, /*InsnID*/0, /*SubRegIndex*/3,
        GIR_AddSimpleTempRegister, /*InsnID*/0, /*TempRegID*/4,
        GIR_AddImm8, /*InsnID*/0, /*SubRegIndex*/11,
        GIR_ConstrainOperandRC, /*InsnID*/0, /*Op*/0, GIMT_Encode2(AMDGPU::VReg_64RegClassID),
        GIR_ConstrainOperandRC, /*InsnID*/0, /*Op*/1, GIMT_Encode2(AMDGPU::VGPR_32RegClassID),
        GIR_ConstrainOperandRC, /*InsnID*/0, /*Op*/3, GIMT_Encode2(AMDGPU::VGPR_32RegClassID),
        GIR_EraseFromParent, /*InsnID*/0,
        // GIR_Coverage, 6275,
        GIR_Done,
      // Label 343: @26709
      GIM_Try, /*On fail goto*//*Label 344*/ GIMT_Encode4(27034), // Rule ID 9879 //
        GIM_CheckRegBankForClass, /*MI*/0, /*Op*/0, /*RC*/GIMT_Encode2(AMDGPU::VReg_64RegClassID),
        GIM_RecordInsnIgnoreCopies, /*DefineMI*/1, /*MI*/0, /*OpIdx*/1, // MIs[1]
        GIM_CheckOpcode, /*MI*/1, GIMT_Encode2(TargetOpcode::G_AND),
        GIM_CheckType, /*MI*/1, /*Op*/1, /*Type*/GILLT_s64,
        GIM_CheckType, /*MI*/1, /*Op*/2, /*Type*/GILLT_s64,
        GIM_RecordInsnIgnoreCopies, /*DefineMI*/2, /*MI*/0, /*OpIdx*/2, // MIs[2]
        GIM_CheckOpcode, /*MI*/2, GIMT_Encode2(TargetOpcode::G_AND),
        GIM_CheckType, /*MI*/2, /*Op*/1, /*Type*/GILLT_s64,
        GIM_CheckType, /*MI*/2, /*Op*/2, /*Type*/GILLT_s64,
        GIM_RecordInsnIgnoreCopies, /*DefineMI*/3, /*MI*/2, /*OpIdx*/2, // MIs[3]
        GIM_CheckOpcode, /*MI*/3, GIMT_Encode2(TargetOpcode::G_XOR),
        GIM_CheckType, /*MI*/3, /*Op*/2, /*Type*/GILLT_s64,
        // MIs[3] x
        GIM_CheckIsSameOperandIgnoreCopies, /*MI*/3, /*OpIdx*/1, /*OtherMI*/1, /*OtherOpIdx*/1,
        GIM_CheckConstantInt8, /*MI*/3, /*Op*/2, uint8_t(-1),
        GIM_CheckCxxInsnPredicate, /*MI*/0, /*FnId*/GIMT_Encode2(GICXXPred_MI_Predicate_anonymous_22557),
        GIM_CheckIsSafeToFold, /*InsnID*/1,
        GIM_CheckIsSafeToFold, /*InsnID*/2,
        GIM_CheckIsSafeToFold, /*InsnID*/3,
        // (or:{ *:[i64] } (and:{ *:[i64] } i64:{ *:[i64] }:$x, i64:{ *:[i64] }:$y), (and:{ *:[i64] } i64:{ *:[i64] }:$z, (xor:{ *:[i64] } i64:{ *:[i64] }:$x, -1:{ *:[i64] })))<<P:Predicate_anonymous_22557>>  =>  (REG_SEQUENCE:{ *:[i64] } VReg_64:{ *:[i32] }, (V_BFI_B32_e64:{ *:[i16] } (EXTRACT_SUBREG:{ *:[i32] } VReg_64:{ *:[i64] }:$x, sub0:{ *:[i32] }), (EXTRACT_SUBREG:{ *:[i32] } VReg_64:{ *:[i64] }:$y, sub0:{ *:[i32] }), (EXTRACT_SUBREG:{ *:[i32] } VReg_64:{ *:[i64] }:$z, sub0:{ *:[i32] })), sub0:{ *:[i32] }, (V_BFI_B32_e64:{ *:[i16] } (EXTRACT_SUBREG:{ *:[i32] } VReg_64:{ *:[i64] }:$x, sub1:{ *:[i32] }), (EXTRACT_SUBREG:{ *:[i32] } VReg_64:{ *:[i64] }:$y, sub1:{ *:[i32] }), (EXTRACT_SUBREG:{ *:[i32] } VReg_64:{ *:[i64] }:$z, sub1:{ *:[i32] })), sub1:{ *:[i32] })
        GIR_MakeTempReg, /*TempRegID*/0, /*TypeID*/GILLT_s16,
        GIR_MakeTempReg, /*TempRegID*/1, /*TypeID*/GILLT_s32,
        GIR_MakeTempReg, /*TempRegID*/2, /*TypeID*/GILLT_s32,
        GIR_MakeTempReg, /*TempRegID*/3, /*TypeID*/GILLT_s32,
        GIR_MakeTempReg, /*TempRegID*/4, /*TypeID*/GILLT_s16,
        GIR_MakeTempReg, /*TempRegID*/5, /*TypeID*/GILLT_s32,
        GIR_MakeTempReg, /*TempRegID*/6, /*TypeID*/GILLT_s32,
        GIR_MakeTempReg, /*TempRegID*/7, /*TypeID*/GILLT_s32,
        GIR_BuildMI, /*InsnID*/8, /*Opcode*/GIMT_Encode2(TargetOpcode::COPY),
        GIR_AddTempRegister, /*InsnID*/8, /*TempRegID*/7, /*TempRegFlags*/GIMT_Encode2(RegState::Define),
        GIR_CopySubReg, /*NewInsnID*/8, /*OldInsnID*/2, /*OpIdx*/1, /*SubRegIdx*/GIMT_Encode2(11), // z
        GIR_ConstrainOperandRC, /*InsnID*/8, /*Op*/0, GIMT_Encode2(AMDGPU::VGPR_32RegClassID),
        GIR_ConstrainOperandRC, /*InsnID*/8, /*Op*/1, GIMT_Encode2(AMDGPU::VReg_64RegClassID),
        GIR_BuildMI, /*InsnID*/7, /*Opcode*/GIMT_Encode2(TargetOpcode::COPY),
        GIR_AddTempRegister, /*InsnID*/7, /*TempRegID*/6, /*TempRegFlags*/GIMT_Encode2(RegState::Define),
        GIR_CopySubReg, /*NewInsnID*/7, /*OldInsnID*/1, /*OpIdx*/2, /*SubRegIdx*/GIMT_Encode2(11), // y
        GIR_ConstrainOperandRC, /*InsnID*/7, /*Op*/0, GIMT_Encode2(AMDGPU::VGPR_32RegClassID),
        GIR_ConstrainOperandRC, /*InsnID*/7, /*Op*/1, GIMT_Encode2(AMDGPU::VReg_64RegClassID),
        GIR_BuildMI, /*InsnID*/6, /*Opcode*/GIMT_Encode2(TargetOpcode::COPY),
        GIR_AddTempRegister, /*InsnID*/6, /*TempRegID*/5, /*TempRegFlags*/GIMT_Encode2(RegState::Define),
        GIR_CopySubReg, /*NewInsnID*/6, /*OldInsnID*/1, /*OpIdx*/1, /*SubRegIdx*/GIMT_Encode2(11), // x
        GIR_ConstrainOperandRC, /*InsnID*/6, /*Op*/0, GIMT_Encode2(AMDGPU::VGPR_32RegClassID),
        GIR_ConstrainOperandRC, /*InsnID*/6, /*Op*/1, GIMT_Encode2(AMDGPU::VReg_64RegClassID),
        GIR_BuildMI, /*InsnID*/5, /*Opcode*/GIMT_Encode2(AMDGPU::V_BFI_B32_e64),
        GIR_AddTempRegister, /*InsnID*/5, /*TempRegID*/4, /*TempRegFlags*/GIMT_Encode2(RegState::Define),
        GIR_AddSimpleTempRegister, /*InsnID*/5, /*TempRegID*/5,
        GIR_AddSimpleTempRegister, /*InsnID*/5, /*TempRegID*/6,
        GIR_AddSimpleTempRegister, /*InsnID*/5, /*TempRegID*/7,
        GIR_ConstrainSelectedInstOperands, /*InsnID*/5,
        GIR_BuildMI, /*InsnID*/4, /*Opcode*/GIMT_Encode2(TargetOpcode::COPY),
        GIR_AddTempRegister, /*InsnID*/4, /*TempRegID*/3, /*TempRegFlags*/GIMT_Encode2(RegState::Define),
        GIR_CopySubReg, /*NewInsnID*/4, /*OldInsnID*/2, /*OpIdx*/1, /*SubRegIdx*/GIMT_Encode2(3), // z
        GIR_ConstrainOperandRC, /*InsnID*/4, /*Op*/0, GIMT_Encode2(AMDGPU::VGPR_32RegClassID),
        GIR_ConstrainOperandRC, /*InsnID*/4, /*Op*/1, GIMT_Encode2(AMDGPU::VReg_64RegClassID),
        GIR_BuildMI, /*InsnID*/3, /*Opcode*/GIMT_Encode2(TargetOpcode::COPY),
        GIR_AddTempRegister, /*InsnID*/3, /*TempRegID*/2, /*TempRegFlags*/GIMT_Encode2(RegState::Define),
        GIR_CopySubReg, /*NewInsnID*/3, /*OldInsnID*/1, /*OpIdx*/2, /*SubRegIdx*/GIMT_Encode2(3), // y
        GIR_ConstrainOperandRC, /*InsnID*/3, /*Op*/0, GIMT_Encode2(AMDGPU::VGPR_32RegClassID),
        GIR_ConstrainOperandRC, /*InsnID*/3, /*Op*/1, GIMT_Encode2(AMDGPU::VReg_64RegClassID),
        GIR_BuildMI, /*InsnID*/2, /*Opcode*/GIMT_Encode2(TargetOpcode::COPY),
        GIR_AddTempRegister, /*InsnID*/2, /*TempRegID*/1, /*TempRegFlags*/GIMT_Encode2(RegState::Define),
        GIR_CopySubReg, /*NewInsnID*/2, /*OldInsnID*/1, /*OpIdx*/1, /*SubRegIdx*/GIMT_Encode2(3), // x
        GIR_ConstrainOperandRC, /*InsnID*/2, /*Op*/0, GIMT_Encode2(AMDGPU::VGPR_32RegClassID),
        GIR_ConstrainOperandRC, /*InsnID*/2, /*Op*/1, GIMT_Encode2(AMDGPU::VReg_64RegClassID),
        GIR_BuildMI, /*InsnID*/1, /*Opcode*/GIMT_Encode2(AMDGPU::V_BFI_B32_e64),
        GIR_AddTempRegister, /*InsnID*/1, /*TempRegID*/0, /*TempRegFlags*/GIMT_Encode2(RegState::Define),
        GIR_AddSimpleTempRegister, /*InsnID*/1, /*TempRegID*/1,
        GIR_AddSimpleTempRegister, /*InsnID*/1, /*TempRegID*/2,
        GIR_AddSimpleTempRegister, /*InsnID*/1, /*TempRegID*/3,
        GIR_ConstrainSelectedInstOperands, /*InsnID*/1,
        GIR_BuildMI, /*InsnID*/0, /*Opcode*/GIMT_Encode2(TargetOpcode::REG_SEQUENCE),
        GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/0, // DstI[dst]
        GIR_AddSimpleTempRegister, /*InsnID*/0, /*TempRegID*/0,
        GIR_AddImm8, /*InsnID*/0, /*SubRegIndex*/3,
        GIR_AddSimpleTempRegister, /*InsnID*/0, /*TempRegID*/4,
        GIR_AddImm8, /*InsnID*/0, /*SubRegIndex*/11,
        GIR_ConstrainOperandRC, /*InsnID*/0, /*Op*/0, GIMT_Encode2(AMDGPU::VReg_64RegClassID),
        GIR_ConstrainOperandRC, /*InsnID*/0, /*Op*/1, GIMT_Encode2(AMDGPU::VGPR_32RegClassID),
        GIR_ConstrainOperandRC, /*InsnID*/0, /*Op*/3, GIMT_Encode2(AMDGPU::VGPR_32RegClassID),
        GIR_EraseFromParent, /*InsnID*/0,
        // GIR_Coverage, 9879,
        GIR_Done,
      // Label 344: @27034
      GIM_Try, /*On fail goto*//*Label 345*/ GIMT_Encode4(27452), // Rule ID 9936 //
        GIM_CheckRegBankForClass, /*MI*/0, /*Op*/0, /*RC*/GIMT_Encode2(AMDGPU::VReg_64RegClassID),
        GIM_RecordInsnIgnoreCopies, /*DefineMI*/1, /*MI*/0, /*OpIdx*/1, // MIs[1]
        GIM_CheckOpcode, /*MI*/1, GIMT_Encode2(TargetOpcode::G_AND),
        GIM_CheckType, /*MI*/1, /*Op*/1, /*Type*/GILLT_s64,
        GIM_CheckType, /*MI*/1, /*Op*/2, /*Type*/GILLT_s64,
        GIM_RecordInsnIgnoreCopies, /*DefineMI*/2, /*MI*/1, /*OpIdx*/1, // MIs[2]
        GIM_CheckOpcode, /*MI*/2, GIMT_Encode2(TargetOpcode::G_OR),
        GIM_CheckType, /*MI*/2, /*Op*/1, /*Type*/GILLT_s64,
        GIM_CheckType, /*MI*/2, /*Op*/2, /*Type*/GILLT_s64,
        GIM_RecordInsnIgnoreCopies, /*DefineMI*/3, /*MI*/0, /*OpIdx*/2, // MIs[3]
        GIM_CheckOpcode, /*MI*/3, GIMT_Encode2(TargetOpcode::G_AND),
        // MIs[3] x
        GIM_CheckIsSameOperandIgnoreCopies, /*MI*/3, /*OpIdx*/1, /*OtherMI*/2, /*OtherOpIdx*/1,
        // MIs[3] z
        GIM_CheckIsSameOperandIgnoreCopies, /*MI*/3, /*OpIdx*/2, /*OtherMI*/2, /*OtherOpIdx*/2,
        GIM_CheckCxxInsnPredicate, /*MI*/0, /*FnId*/GIMT_Encode2(GICXXPred_MI_Predicate_anonymous_22557),
        GIM_CheckIsSafeToFold, /*InsnID*/1,
        GIM_CheckIsSafeToFold, /*InsnID*/2,
        GIM_CheckIsSafeToFold, /*InsnID*/3,
        // (or:{ *:[i64] } (and:{ *:[i64] } (or:{ *:[i64] } i64:{ *:[i64] }:$x, i64:{ *:[i64] }:$z), i64:{ *:[i64] }:$y), (and:{ *:[i64] } i64:{ *:[i64] }:$x, i64:{ *:[i64] }:$z))<<P:Predicate_anonymous_22557>>  =>  (REG_SEQUENCE:{ *:[i64] } VReg_64:{ *:[i32] }, (V_BFI_B32_e64:{ *:[i16] } (V_XOR_B32_e64:{ *:[i16] } (EXTRACT_SUBREG:{ *:[i32] } VReg_64:{ *:[i64] }:$x, sub0:{ *:[i32] }), (EXTRACT_SUBREG:{ *:[i32] } VReg_64:{ *:[i64] }:$y, sub0:{ *:[i32] })), (EXTRACT_SUBREG:{ *:[i32] } VReg_64:{ *:[i64] }:$z, sub0:{ *:[i32] }), (EXTRACT_SUBREG:{ *:[i32] } VReg_64:{ *:[i64] }:$y, sub0:{ *:[i32] })), sub0:{ *:[i32] }, (V_BFI_B32_e64:{ *:[i16] } (V_XOR_B32_e64:{ *:[i16] } (EXTRACT_SUBREG:{ *:[i32] } VReg_64:{ *:[i64] }:$x, sub1:{ *:[i32] }), (EXTRACT_SUBREG:{ *:[i32] } VReg_64:{ *:[i64] }:$y, sub1:{ *:[i32] })), (EXTRACT_SUBREG:{ *:[i32] } VReg_64:{ *:[i64] }:$z, sub1:{ *:[i32] }), (EXTRACT_SUBREG:{ *:[i32] } VReg_64:{ *:[i64] }:$y, sub1:{ *:[i32] })), sub1:{ *:[i32] })
        GIR_MakeTempReg, /*TempRegID*/0, /*TypeID*/GILLT_s16,
        GIR_MakeTempReg, /*TempRegID*/1, /*TypeID*/GILLT_s16,
        GIR_MakeTempReg, /*TempRegID*/2, /*TypeID*/GILLT_s32,
        GIR_MakeTempReg, /*TempRegID*/3, /*TypeID*/GILLT_s32,
        GIR_MakeTempReg, /*TempRegID*/4, /*TypeID*/GILLT_s32,
        GIR_MakeTempReg, /*TempRegID*/5, /*TypeID*/GILLT_s32,
        GIR_MakeTempReg, /*TempRegID*/6, /*TypeID*/GILLT_s16,
        GIR_MakeTempReg, /*TempRegID*/7, /*TypeID*/GILLT_s16,
        GIR_MakeTempReg, /*TempRegID*/8, /*TypeID*/GILLT_s32,
        GIR_MakeTempReg, /*TempRegID*/9, /*TypeID*/GILLT_s32,
        GIR_MakeTempReg, /*TempRegID*/10, /*TypeID*/GILLT_s32,
        GIR_MakeTempReg, /*TempRegID*/11, /*TypeID*/GILLT_s32,
        GIR_BuildMI, /*InsnID*/12, /*Opcode*/GIMT_Encode2(TargetOpcode::COPY),
        GIR_AddTempRegister, /*InsnID*/12, /*TempRegID*/11, /*TempRegFlags*/GIMT_Encode2(RegState::Define),
        GIR_CopySubReg, /*NewInsnID*/12, /*OldInsnID*/1, /*OpIdx*/2, /*SubRegIdx*/GIMT_Encode2(11), // y
        GIR_ConstrainOperandRC, /*InsnID*/12, /*Op*/0, GIMT_Encode2(AMDGPU::VGPR_32RegClassID),
        GIR_ConstrainOperandRC, /*InsnID*/12, /*Op*/1, GIMT_Encode2(AMDGPU::VReg_64RegClassID),
        GIR_BuildMI, /*InsnID*/11, /*Opcode*/GIMT_Encode2(TargetOpcode::COPY),
        GIR_AddTempRegister, /*InsnID*/11, /*TempRegID*/10, /*TempRegFlags*/GIMT_Encode2(RegState::Define),
        GIR_CopySubReg, /*NewInsnID*/11, /*OldInsnID*/2, /*OpIdx*/2, /*SubRegIdx*/GIMT_Encode2(11), // z
        GIR_ConstrainOperandRC, /*InsnID*/11, /*Op*/0, GIMT_Encode2(AMDGPU::VGPR_32RegClassID),
        GIR_ConstrainOperandRC, /*InsnID*/11, /*Op*/1, GIMT_Encode2(AMDGPU::VReg_64RegClassID),
        GIR_BuildMI, /*InsnID*/10, /*Opcode*/GIMT_Encode2(TargetOpcode::COPY),
        GIR_AddTempRegister, /*InsnID*/10, /*TempRegID*/9, /*TempRegFlags*/GIMT_Encode2(RegState::Define),
        GIR_CopySubReg, /*NewInsnID*/10, /*OldInsnID*/1, /*OpIdx*/2, /*SubRegIdx*/GIMT_Encode2(11), // y
        GIR_ConstrainOperandRC, /*InsnID*/10, /*Op*/0, GIMT_Encode2(AMDGPU::VGPR_32RegClassID),
        GIR_ConstrainOperandRC, /*InsnID*/10, /*Op*/1, GIMT_Encode2(AMDGPU::VReg_64RegClassID),
        GIR_BuildMI, /*InsnID*/9, /*Opcode*/GIMT_Encode2(TargetOpcode::COPY),
        GIR_AddTempRegister, /*InsnID*/9, /*TempRegID*/8, /*TempRegFlags*/GIMT_Encode2(RegState::Define),
        GIR_CopySubReg, /*NewInsnID*/9, /*OldInsnID*/2, /*OpIdx*/1, /*SubRegIdx*/GIMT_Encode2(11), // x
        GIR_ConstrainOperandRC, /*InsnID*/9, /*Op*/0, GIMT_Encode2(AMDGPU::VGPR_32RegClassID),
        GIR_ConstrainOperandRC, /*InsnID*/9, /*Op*/1, GIMT_Encode2(AMDGPU::VReg_64RegClassID),
        GIR_BuildMI, /*InsnID*/8, /*Opcode*/GIMT_Encode2(AMDGPU::V_XOR_B32_e64),
        GIR_AddTempRegister, /*InsnID*/8, /*TempRegID*/7, /*TempRegFlags*/GIMT_Encode2(RegState::Define),
        GIR_AddSimpleTempRegister, /*InsnID*/8, /*TempRegID*/8,
        GIR_AddSimpleTempRegister, /*InsnID*/8, /*TempRegID*/9,
        GIR_ConstrainSelectedInstOperands, /*InsnID*/8,
        GIR_BuildMI, /*InsnID*/7, /*Opcode*/GIMT_Encode2(AMDGPU::V_BFI_B32_e64),
        GIR_AddTempRegister, /*InsnID*/7, /*TempRegID*/6, /*TempRegFlags*/GIMT_Encode2(RegState::Define),
        GIR_AddSimpleTempRegister, /*InsnID*/7, /*TempRegID*/7,
        GIR_AddSimpleTempRegister, /*InsnID*/7, /*TempRegID*/10,
        GIR_AddSimpleTempRegister, /*InsnID*/7, /*TempRegID*/11,
        GIR_ConstrainSelectedInstOperands, /*InsnID*/7,
        GIR_BuildMI, /*InsnID*/6, /*Opcode*/GIMT_Encode2(TargetOpcode::COPY),
        GIR_AddTempRegister, /*InsnID*/6, /*TempRegID*/5, /*TempRegFlags*/GIMT_Encode2(RegState::Define),
        GIR_CopySubReg, /*NewInsnID*/6, /*OldInsnID*/1, /*OpIdx*/2, /*SubRegIdx*/GIMT_Encode2(3), // y
        GIR_ConstrainOperandRC, /*InsnID*/6, /*Op*/0, GIMT_Encode2(AMDGPU::VGPR_32RegClassID),
        GIR_ConstrainOperandRC, /*InsnID*/6, /*Op*/1, GIMT_Encode2(AMDGPU::VReg_64RegClassID),
        GIR_BuildMI, /*InsnID*/5, /*Opcode*/GIMT_Encode2(TargetOpcode::COPY),
        GIR_AddTempRegister, /*InsnID*/5, /*TempRegID*/4, /*TempRegFlags*/GIMT_Encode2(RegState::Define),
        GIR_CopySubReg, /*NewInsnID*/5, /*OldInsnID*/2, /*OpIdx*/2, /*SubRegIdx*/GIMT_Encode2(3), // z
        GIR_ConstrainOperandRC, /*InsnID*/5, /*Op*/0, GIMT_Encode2(AMDGPU::VGPR_32RegClassID),
        GIR_ConstrainOperandRC, /*InsnID*/5, /*Op*/1, GIMT_Encode2(AMDGPU::VReg_64RegClassID),
        GIR_BuildMI, /*InsnID*/4, /*Opcode*/GIMT_Encode2(TargetOpcode::COPY),
        GIR_AddTempRegister, /*InsnID*/4, /*TempRegID*/3, /*TempRegFlags*/GIMT_Encode2(RegState::Define),
        GIR_CopySubReg, /*NewInsnID*/4, /*OldInsnID*/1, /*OpIdx*/2, /*SubRegIdx*/GIMT_Encode2(3), // y
        GIR_ConstrainOperandRC, /*InsnID*/4, /*Op*/0, GIMT_Encode2(AMDGPU::VGPR_32RegClassID),
        GIR_ConstrainOperandRC, /*InsnID*/4, /*Op*/1, GIMT_Encode2(AMDGPU::VReg_64RegClassID),
        GIR_BuildMI, /*InsnID*/3, /*Opcode*/GIMT_Encode2(TargetOpcode::COPY),
        GIR_AddTempRegister, /*InsnID*/3, /*TempRegID*/2, /*TempRegFlags*/GIMT_Encode2(RegState::Define),
        GIR_CopySubReg, /*NewInsnID*/3, /*OldInsnID*/2, /*OpIdx*/1, /*SubRegIdx*/GIMT_Encode2(3), // x
        GIR_ConstrainOperandRC, /*InsnID*/3, /*Op*/0, GIMT_Encode2(AMDGPU::VGPR_32RegClassID),
        GIR_ConstrainOperandRC, /*InsnID*/3, /*Op*/1, GIMT_Encode2(AMDGPU::VReg_64RegClassID),
        GIR_BuildMI, /*InsnID*/2, /*Opcode*/GIMT_Encode2(AMDGPU::V_XOR_B32_e64),
        GIR_AddTempRegister, /*InsnID*/2, /*TempRegID*/1, /*TempRegFlags*/GIMT_Encode2(RegState::Define),
        GIR_AddSimpleTempRegister, /*InsnID*/2, /*TempRegID*/2,
        GIR_AddSimpleTempRegister, /*InsnID*/2, /*TempRegID*/3,
        GIR_ConstrainSelectedInstOperands, /*InsnID*/2,
        GIR_BuildMI, /*InsnID*/1, /*Opcode*/GIMT_Encode2(AMDGPU::V_BFI_B32_e64),
        GIR_AddTempRegister, /*InsnID*/1, /*TempRegID*/0, /*TempRegFlags*/GIMT_Encode2(RegState::Define),
        GIR_AddSimpleTempRegister, /*InsnID*/1, /*TempRegID*/1,
        GIR_AddSimpleTempRegister, /*InsnID*/1, /*TempRegID*/4,
        GIR_AddSimpleTempRegister, /*InsnID*/1, /*TempRegID*/5,
        GIR_ConstrainSelectedInstOperands, /*InsnID*/1,
        GIR_BuildMI, /*InsnID*/0, /*Opcode*/GIMT_Encode2(TargetOpcode::REG_SEQUENCE),
        GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/0, // DstI[dst]
        GIR_AddSimpleTempRegister, /*InsnID*/0, /*TempRegID*/0,
        GIR_AddImm8, /*InsnID*/0, /*SubRegIndex*/3,
        GIR_AddSimpleTempRegister, /*InsnID*/0, /*TempRegID*/6,
        GIR_AddImm8, /*InsnID*/0, /*SubRegIndex*/11,
        GIR_ConstrainOperandRC, /*InsnID*/0, /*Op*/0, GIMT_Encode2(AMDGPU::VReg_64RegClassID),
        GIR_ConstrainOperandRC, /*InsnID*/0, /*Op*/1, GIMT_Encode2(AMDGPU::VGPR_32RegClassID),
        GIR_ConstrainOperandRC, /*InsnID*/0, /*Op*/3, GIMT_Encode2(AMDGPU::VGPR_32RegClassID),
        GIR_EraseFromParent, /*InsnID*/0,
        // GIR_Coverage, 9936,
        GIR_Done,
      // Label 345: @27452
      GIM_Try, /*On fail goto*//*Label 346*/ GIMT_Encode4(27870), // Rule ID 9937 //
        GIM_CheckRegBankForClass, /*MI*/0, /*Op*/0, /*RC*/GIMT_Encode2(AMDGPU::VReg_64RegClassID),
        GIM_RecordInsnIgnoreCopies, /*DefineMI*/1, /*MI*/0, /*OpIdx*/1, // MIs[1]
        GIM_CheckOpcode, /*MI*/1, GIMT_Encode2(TargetOpcode::G_AND),
        GIM_CheckType, /*MI*/1, /*Op*/1, /*Type*/GILLT_s64,
        GIM_CheckType, /*MI*/1, /*Op*/2, /*Type*/GILLT_s64,
        GIM_RecordInsnIgnoreCopies, /*DefineMI*/2, /*MI*/1, /*OpIdx*/1, // MIs[2]
        GIM_CheckOpcode, /*MI*/2, GIMT_Encode2(TargetOpcode::G_OR),
        GIM_CheckType, /*MI*/2, /*Op*/1, /*Type*/GILLT_s64,
        GIM_CheckType, /*MI*/2, /*Op*/2, /*Type*/GILLT_s64,
        GIM_RecordInsnIgnoreCopies, /*DefineMI*/3, /*MI*/0, /*OpIdx*/2, // MIs[3]
        GIM_CheckOpcode, /*MI*/3, GIMT_Encode2(TargetOpcode::G_AND),
        // MIs[3] z
        GIM_CheckIsSameOperandIgnoreCopies, /*MI*/3, /*OpIdx*/1, /*OtherMI*/2, /*OtherOpIdx*/2,
        // MIs[3] x
        GIM_CheckIsSameOperandIgnoreCopies, /*MI*/3, /*OpIdx*/2, /*OtherMI*/2, /*OtherOpIdx*/1,
        GIM_CheckCxxInsnPredicate, /*MI*/0, /*FnId*/GIMT_Encode2(GICXXPred_MI_Predicate_anonymous_22557),
        GIM_CheckIsSafeToFold, /*InsnID*/1,
        GIM_CheckIsSafeToFold, /*InsnID*/2,
        GIM_CheckIsSafeToFold, /*InsnID*/3,
        // (or:{ *:[i64] } (and:{ *:[i64] } (or:{ *:[i64] } i64:{ *:[i64] }:$x, i64:{ *:[i64] }:$z), i64:{ *:[i64] }:$y), (and:{ *:[i64] } i64:{ *:[i64] }:$z, i64:{ *:[i64] }:$x))<<P:Predicate_anonymous_22557>>  =>  (REG_SEQUENCE:{ *:[i64] } VReg_64:{ *:[i32] }, (V_BFI_B32_e64:{ *:[i16] } (V_XOR_B32_e64:{ *:[i16] } (EXTRACT_SUBREG:{ *:[i32] } VReg_64:{ *:[i64] }:$x, sub0:{ *:[i32] }), (EXTRACT_SUBREG:{ *:[i32] } VReg_64:{ *:[i64] }:$y, sub0:{ *:[i32] })), (EXTRACT_SUBREG:{ *:[i32] } VReg_64:{ *:[i64] }:$z, sub0:{ *:[i32] }), (EXTRACT_SUBREG:{ *:[i32] } VReg_64:{ *:[i64] }:$y, sub0:{ *:[i32] })), sub0:{ *:[i32] }, (V_BFI_B32_e64:{ *:[i16] } (V_XOR_B32_e64:{ *:[i16] } (EXTRACT_SUBREG:{ *:[i32] } VReg_64:{ *:[i64] }:$x, sub1:{ *:[i32] }), (EXTRACT_SUBREG:{ *:[i32] } VReg_64:{ *:[i64] }:$y, sub1:{ *:[i32] })), (EXTRACT_SUBREG:{ *:[i32] } VReg_64:{ *:[i64] }:$z, sub1:{ *:[i32] }), (EXTRACT_SUBREG:{ *:[i32] } VReg_64:{ *:[i64] }:$y, sub1:{ *:[i32] })), sub1:{ *:[i32] })
        GIR_MakeTempReg, /*TempRegID*/0, /*TypeID*/GILLT_s16,
        GIR_MakeTempReg, /*TempRegID*/1, /*TypeID*/GILLT_s16,
        GIR_MakeTempReg, /*TempRegID*/2, /*TypeID*/GILLT_s32,
        GIR_MakeTempReg, /*TempRegID*/3, /*TypeID*/GILLT_s32,
        GIR_MakeTempReg, /*TempRegID*/4, /*TypeID*/GILLT_s32,
        GIR_MakeTempReg, /*TempRegID*/5, /*TypeID*/GILLT_s32,
        GIR_MakeTempReg, /*TempRegID*/6, /*TypeID*/GILLT_s16,
        GIR_MakeTempReg, /*TempRegID*/7, /*TypeID*/GILLT_s16,
        GIR_MakeTempReg, /*TempRegID*/8, /*TypeID*/GILLT_s32,
        GIR_MakeTempReg, /*TempRegID*/9, /*TypeID*/GILLT_s32,
        GIR_MakeTempReg, /*TempRegID*/10, /*TypeID*/GILLT_s32,
        GIR_MakeTempReg, /*TempRegID*/11, /*TypeID*/GILLT_s32,
        GIR_BuildMI, /*InsnID*/12, /*Opcode*/GIMT_Encode2(TargetOpcode::COPY),
        GIR_AddTempRegister, /*InsnID*/12, /*TempRegID*/11, /*TempRegFlags*/GIMT_Encode2(RegState::Define),
        GIR_CopySubReg, /*NewInsnID*/12, /*OldInsnID*/1, /*OpIdx*/2, /*SubRegIdx*/GIMT_Encode2(11), // y
        GIR_ConstrainOperandRC, /*InsnID*/12, /*Op*/0, GIMT_Encode2(AMDGPU::VGPR_32RegClassID),
        GIR_ConstrainOperandRC, /*InsnID*/12, /*Op*/1, GIMT_Encode2(AMDGPU::VReg_64RegClassID),
        GIR_BuildMI, /*InsnID*/11, /*Opcode*/GIMT_Encode2(TargetOpcode::COPY),
        GIR_AddTempRegister, /*InsnID*/11, /*TempRegID*/10, /*TempRegFlags*/GIMT_Encode2(RegState::Define),
        GIR_CopySubReg, /*NewInsnID*/11, /*OldInsnID*/2, /*OpIdx*/2, /*SubRegIdx*/GIMT_Encode2(11), // z
        GIR_ConstrainOperandRC, /*InsnID*/11, /*Op*/0, GIMT_Encode2(AMDGPU::VGPR_32RegClassID),
        GIR_ConstrainOperandRC, /*InsnID*/11, /*Op*/1, GIMT_Encode2(AMDGPU::VReg_64RegClassID),
        GIR_BuildMI, /*InsnID*/10, /*Opcode*/GIMT_Encode2(TargetOpcode::COPY),
        GIR_AddTempRegister, /*InsnID*/10, /*TempRegID*/9, /*TempRegFlags*/GIMT_Encode2(RegState::Define),
        GIR_CopySubReg, /*NewInsnID*/10, /*OldInsnID*/1, /*OpIdx*/2, /*SubRegIdx*/GIMT_Encode2(11), // y
        GIR_ConstrainOperandRC, /*InsnID*/10, /*Op*/0, GIMT_Encode2(AMDGPU::VGPR_32RegClassID),
        GIR_ConstrainOperandRC, /*InsnID*/10, /*Op*/1, GIMT_Encode2(AMDGPU::VReg_64RegClassID),
        GIR_BuildMI, /*InsnID*/9, /*Opcode*/GIMT_Encode2(TargetOpcode::COPY),
        GIR_AddTempRegister, /*InsnID*/9, /*TempRegID*/8, /*TempRegFlags*/GIMT_Encode2(RegState::Define),
        GIR_CopySubReg, /*NewInsnID*/9, /*OldInsnID*/2, /*OpIdx*/1, /*SubRegIdx*/GIMT_Encode2(11), // x
        GIR_ConstrainOperandRC, /*InsnID*/9, /*Op*/0, GIMT_Encode2(AMDGPU::VGPR_32RegClassID),
        GIR_ConstrainOperandRC, /*InsnID*/9, /*Op*/1, GIMT_Encode2(AMDGPU::VReg_64RegClassID),
        GIR_BuildMI, /*InsnID*/8, /*Opcode*/GIMT_Encode2(AMDGPU::V_XOR_B32_e64),
        GIR_AddTempRegister, /*InsnID*/8, /*TempRegID*/7, /*TempRegFlags*/GIMT_Encode2(RegState::Define),
        GIR_AddSimpleTempRegister, /*InsnID*/8, /*TempRegID*/8,
        GIR_AddSimpleTempRegister, /*InsnID*/8, /*TempRegID*/9,
        GIR_ConstrainSelectedInstOperands, /*InsnID*/8,
        GIR_BuildMI, /*InsnID*/7, /*Opcode*/GIMT_Encode2(AMDGPU::V_BFI_B32_e64),
        GIR_AddTempRegister, /*InsnID*/7, /*TempRegID*/6, /*TempRegFlags*/GIMT_Encode2(RegState::Define),
        GIR_AddSimpleTempRegister, /*InsnID*/7, /*TempRegID*/7,
        GIR_AddSimpleTempRegister, /*InsnID*/7, /*TempRegID*/10,
        GIR_AddSimpleTempRegister, /*InsnID*/7, /*TempRegID*/11,
        GIR_ConstrainSelectedInstOperands, /*InsnID*/7,
        GIR_BuildMI, /*InsnID*/6, /*Opcode*/GIMT_Encode2(TargetOpcode::COPY),
        GIR_AddTempRegister, /*InsnID*/6, /*TempRegID*/5, /*TempRegFlags*/GIMT_Encode2(RegState::Define),
        GIR_CopySubReg, /*NewInsnID*/6, /*OldInsnID*/1, /*OpIdx*/2, /*SubRegIdx*/GIMT_Encode2(3), // y
        GIR_ConstrainOperandRC, /*InsnID*/6, /*Op*/0, GIMT_Encode2(AMDGPU::VGPR_32RegClassID),
        GIR_ConstrainOperandRC, /*InsnID*/6, /*Op*/1, GIMT_Encode2(AMDGPU::VReg_64RegClassID),
        GIR_BuildMI, /*InsnID*/5, /*Opcode*/GIMT_Encode2(TargetOpcode::COPY),
        GIR_AddTempRegister, /*InsnID*/5, /*TempRegID*/4, /*TempRegFlags*/GIMT_Encode2(RegState::Define),
        GIR_CopySubReg, /*NewInsnID*/5, /*OldInsnID*/2, /*OpIdx*/2, /*SubRegIdx*/GIMT_Encode2(3), // z
        GIR_ConstrainOperandRC, /*InsnID*/5, /*Op*/0, GIMT_Encode2(AMDGPU::VGPR_32RegClassID),
        GIR_ConstrainOperandRC, /*InsnID*/5, /*Op*/1, GIMT_Encode2(AMDGPU::VReg_64RegClassID),
        GIR_BuildMI, /*InsnID*/4, /*Opcode*/GIMT_Encode2(TargetOpcode::COPY),
        GIR_AddTempRegister, /*InsnID*/4, /*TempRegID*/3, /*TempRegFlags*/GIMT_Encode2(RegState::Define),
        GIR_CopySubReg, /*NewInsnID*/4, /*OldInsnID*/1, /*OpIdx*/2, /*SubRegIdx*/GIMT_Encode2(3), // y
        GIR_ConstrainOperandRC, /*InsnID*/4, /*Op*/0, GIMT_Encode2(AMDGPU::VGPR_32RegClassID),
        GIR_ConstrainOperandRC, /*InsnID*/4, /*Op*/1, GIMT_Encode2(AMDGPU::VReg_64RegClassID),
        GIR_BuildMI, /*InsnID*/3, /*Opcode*/GIMT_Encode2(TargetOpcode::COPY),
        GIR_AddTempRegister, /*InsnID*/3, /*TempRegID*/2, /*TempRegFlags*/GIMT_Encode2(RegState::Define),
        GIR_CopySubReg, /*NewInsnID*/3, /*OldInsnID*/2, /*OpIdx*/1, /*SubRegIdx*/GIMT_Encode2(3), // x
        GIR_ConstrainOperandRC, /*InsnID*/3, /*Op*/0, GIMT_Encode2(AMDGPU::VGPR_32RegClassID),
        GIR_ConstrainOperandRC, /*InsnID*/3, /*Op*/1, GIMT_Encode2(AMDGPU::VReg_64RegClassID),
        GIR_BuildMI, /*InsnID*/2, /*Opcode*/GIMT_Encode2(AMDGPU::V_XOR_B32_e64),
        GIR_AddTempRegister, /*InsnID*/2, /*TempRegID*/1, /*TempRegFlags*/GIMT_Encode2(RegState::Define),
        GIR_AddSimpleTempRegister, /*InsnID*/2, /*TempRegID*/2,
        GIR_AddSimpleTempRegister, /*InsnID*/2, /*TempRegID*/3,
        GIR_ConstrainSelectedInstOperands, /*InsnID*/2,
        GIR_BuildMI, /*InsnID*/1, /*Opcode*/GIMT_Encode2(AMDGPU::V_BFI_B32_e64),
        GIR_AddTempRegister, /*InsnID*/1, /*TempRegID*/0, /*TempRegFlags*/GIMT_Encode2(RegState::Define),
        GIR_AddSimpleTempRegister, /*InsnID*/1, /*TempRegID*/1,
        GIR_AddSimpleTempRegister, /*InsnID*/1, /*TempRegID*/4,
        GIR_AddSimpleTempRegister, /*InsnID*/1, /*TempRegID*/5,
        GIR_ConstrainSelectedInstOperands, /*InsnID*/1,
        GIR_BuildMI, /*InsnID*/0, /*Opcode*/GIMT_Encode2(TargetOpcode::REG_SEQUENCE),
        GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/0, // DstI[dst]
        GIR_AddSimpleTempRegister, /*InsnID*/0, /*TempRegID*/0,
        GIR_AddImm8, /*InsnID*/0, /*SubRegIndex*/3,
        GIR_AddSimpleTempRegister, /*InsnID*/0, /*TempRegID*/6,
        GIR_AddImm8, /*InsnID*/0, /*SubRegIndex*/11,
        GIR_ConstrainOperandRC, /*InsnID*/0, /*Op*/0, GIMT_Encode2(AMDGPU::VReg_64RegClassID),
        GIR_ConstrainOperandRC, /*InsnID*/0, /*Op*/1, GIMT_Encode2(AMDGPU::VGPR_32RegClassID),
        GIR_ConstrainOperandRC, /*InsnID*/0, /*Op*/3, GIMT_Encode2(AMDGPU::VGPR_32RegClassID),
        GIR_EraseFromParent, /*InsnID*/0,
        // GIR_Coverage, 9937,
        GIR_Done,
      // Label 346: @27870
      GIM_Try, /*On fail goto*//*Label 347*/ GIMT_Encode4(28288), // Rule ID 9938 //
        GIM_CheckRegBankForClass, /*MI*/0, /*Op*/0, /*RC*/GIMT_Encode2(AMDGPU::VReg_64RegClassID),
        GIM_RecordInsnIgnoreCopies, /*DefineMI*/1, /*MI*/0, /*OpIdx*/1, // MIs[1]
        GIM_CheckOpcode, /*MI*/1, GIMT_Encode2(TargetOpcode::G_AND),
        GIM_CheckType, /*MI*/1, /*Op*/1, /*Type*/GILLT_s64,
        GIM_CheckType, /*MI*/1, /*Op*/2, /*Type*/GILLT_s64,
        GIM_RecordInsnIgnoreCopies, /*DefineMI*/2, /*MI*/1, /*OpIdx*/1, // MIs[2]
        GIM_CheckOpcode, /*MI*/2, GIMT_Encode2(TargetOpcode::G_OR),
        GIM_CheckType, /*MI*/2, /*Op*/1, /*Type*/GILLT_s64,
        GIM_CheckType, /*MI*/2, /*Op*/2, /*Type*/GILLT_s64,
        GIM_RecordInsnIgnoreCopies, /*DefineMI*/3, /*MI*/0, /*OpIdx*/2, // MIs[3]
        GIM_CheckOpcode, /*MI*/3, GIMT_Encode2(TargetOpcode::G_AND),
        // MIs[3] x
        GIM_CheckIsSameOperandIgnoreCopies, /*MI*/3, /*OpIdx*/1, /*OtherMI*/2, /*OtherOpIdx*/2,
        // MIs[3] z
        GIM_CheckIsSameOperandIgnoreCopies, /*MI*/3, /*OpIdx*/2, /*OtherMI*/2, /*OtherOpIdx*/1,
        GIM_CheckCxxInsnPredicate, /*MI*/0, /*FnId*/GIMT_Encode2(GICXXPred_MI_Predicate_anonymous_22557),
        GIM_CheckIsSafeToFold, /*InsnID*/1,
        GIM_CheckIsSafeToFold, /*InsnID*/2,
        GIM_CheckIsSafeToFold, /*InsnID*/3,
        // (or:{ *:[i64] } (and:{ *:[i64] } (or:{ *:[i64] } i64:{ *:[i64] }:$z, i64:{ *:[i64] }:$x), i64:{ *:[i64] }:$y), (and:{ *:[i64] } i64:{ *:[i64] }:$x, i64:{ *:[i64] }:$z))<<P:Predicate_anonymous_22557>>  =>  (REG_SEQUENCE:{ *:[i64] } VReg_64:{ *:[i32] }, (V_BFI_B32_e64:{ *:[i16] } (V_XOR_B32_e64:{ *:[i16] } (EXTRACT_SUBREG:{ *:[i32] } VReg_64:{ *:[i64] }:$x, sub0:{ *:[i32] }), (EXTRACT_SUBREG:{ *:[i32] } VReg_64:{ *:[i64] }:$y, sub0:{ *:[i32] })), (EXTRACT_SUBREG:{ *:[i32] } VReg_64:{ *:[i64] }:$z, sub0:{ *:[i32] }), (EXTRACT_SUBREG:{ *:[i32] } VReg_64:{ *:[i64] }:$y, sub0:{ *:[i32] })), sub0:{ *:[i32] }, (V_BFI_B32_e64:{ *:[i16] } (V_XOR_B32_e64:{ *:[i16] } (EXTRACT_SUBREG:{ *:[i32] } VReg_64:{ *:[i64] }:$x, sub1:{ *:[i32] }), (EXTRACT_SUBREG:{ *:[i32] } VReg_64:{ *:[i64] }:$y, sub1:{ *:[i32] })), (EXTRACT_SUBREG:{ *:[i32] } VReg_64:{ *:[i64] }:$z, sub1:{ *:[i32] }), (EXTRACT_SUBREG:{ *:[i32] } VReg_64:{ *:[i64] }:$y, sub1:{ *:[i32] })), sub1:{ *:[i32] })
        GIR_MakeTempReg, /*TempRegID*/0, /*TypeID*/GILLT_s16,
        GIR_MakeTempReg, /*TempRegID*/1, /*TypeID*/GILLT_s16,
        GIR_MakeTempReg, /*TempRegID*/2, /*TypeID*/GILLT_s32,
        GIR_MakeTempReg, /*TempRegID*/3, /*TypeID*/GILLT_s32,
        GIR_MakeTempReg, /*TempRegID*/4, /*TypeID*/GILLT_s32,
        GIR_MakeTempReg, /*TempRegID*/5, /*TypeID*/GILLT_s32,
        GIR_MakeTempReg, /*TempRegID*/6, /*TypeID*/GILLT_s16,
        GIR_MakeTempReg, /*TempRegID*/7, /*TypeID*/GILLT_s16,
        GIR_MakeTempReg, /*TempRegID*/8, /*TypeID*/GILLT_s32,
        GIR_MakeTempReg, /*TempRegID*/9, /*TypeID*/GILLT_s32,
        GIR_MakeTempReg, /*TempRegID*/10, /*TypeID*/GILLT_s32,
        GIR_MakeTempReg, /*TempRegID*/11, /*TypeID*/GILLT_s32,
        GIR_BuildMI, /*InsnID*/12, /*Opcode*/GIMT_Encode2(TargetOpcode::COPY),
        GIR_AddTempRegister, /*InsnID*/12, /*TempRegID*/11, /*TempRegFlags*/GIMT_Encode2(RegState::Define),
        GIR_CopySubReg, /*NewInsnID*/12, /*OldInsnID*/1, /*OpIdx*/2, /*SubRegIdx*/GIMT_Encode2(11), // y
        GIR_ConstrainOperandRC, /*InsnID*/12, /*Op*/0, GIMT_Encode2(AMDGPU::VGPR_32RegClassID),
        GIR_ConstrainOperandRC, /*InsnID*/12, /*Op*/1, GIMT_Encode2(AMDGPU::VReg_64RegClassID),
        GIR_BuildMI, /*InsnID*/11, /*Opcode*/GIMT_Encode2(TargetOpcode::COPY),
        GIR_AddTempRegister, /*InsnID*/11, /*TempRegID*/10, /*TempRegFlags*/GIMT_Encode2(RegState::Define),
        GIR_CopySubReg, /*NewInsnID*/11, /*OldInsnID*/2, /*OpIdx*/1, /*SubRegIdx*/GIMT_Encode2(11), // z
        GIR_ConstrainOperandRC, /*InsnID*/11, /*Op*/0, GIMT_Encode2(AMDGPU::VGPR_32RegClassID),
        GIR_ConstrainOperandRC, /*InsnID*/11, /*Op*/1, GIMT_Encode2(AMDGPU::VReg_64RegClassID),
        GIR_BuildMI, /*InsnID*/10, /*Opcode*/GIMT_Encode2(TargetOpcode::COPY),
        GIR_AddTempRegister, /*InsnID*/10, /*TempRegID*/9, /*TempRegFlags*/GIMT_Encode2(RegState::Define),
        GIR_CopySubReg, /*NewInsnID*/10, /*OldInsnID*/1, /*OpIdx*/2, /*SubRegIdx*/GIMT_Encode2(11), // y
        GIR_ConstrainOperandRC, /*InsnID*/10, /*Op*/0, GIMT_Encode2(AMDGPU::VGPR_32RegClassID),
        GIR_ConstrainOperandRC, /*InsnID*/10, /*Op*/1, GIMT_Encode2(AMDGPU::VReg_64RegClassID),
        GIR_BuildMI, /*InsnID*/9, /*Opcode*/GIMT_Encode2(TargetOpcode::COPY),
        GIR_AddTempRegister, /*InsnID*/9, /*TempRegID*/8, /*TempRegFlags*/GIMT_Encode2(RegState::Define),
        GIR_CopySubReg, /*NewInsnID*/9, /*OldInsnID*/2, /*OpIdx*/2, /*SubRegIdx*/GIMT_Encode2(11), // x
        GIR_ConstrainOperandRC, /*InsnID*/9, /*Op*/0, GIMT_Encode2(AMDGPU::VGPR_32RegClassID),
        GIR_ConstrainOperandRC, /*InsnID*/9, /*Op*/1, GIMT_Encode2(AMDGPU::VReg_64RegClassID),
        GIR_BuildMI, /*InsnID*/8, /*Opcode*/GIMT_Encode2(AMDGPU::V_XOR_B32_e64),
        GIR_AddTempRegister, /*InsnID*/8, /*TempRegID*/7, /*TempRegFlags*/GIMT_Encode2(RegState::Define),
        GIR_AddSimpleTempRegister, /*InsnID*/8, /*TempRegID*/8,
        GIR_AddSimpleTempRegister, /*InsnID*/8, /*TempRegID*/9,
        GIR_ConstrainSelectedInstOperands, /*InsnID*/8,
        GIR_BuildMI, /*InsnID*/7, /*Opcode*/GIMT_Encode2(AMDGPU::V_BFI_B32_e64),
        GIR_AddTempRegister, /*InsnID*/7, /*TempRegID*/6, /*TempRegFlags*/GIMT_Encode2(RegState::Define),
        GIR_AddSimpleTempRegister, /*InsnID*/7, /*TempRegID*/7,
        GIR_AddSimpleTempRegister, /*InsnID*/7, /*TempRegID*/10,
        GIR_AddSimpleTempRegister, /*InsnID*/7, /*TempRegID*/11,
        GIR_ConstrainSelectedInstOperands, /*InsnID*/7,
        GIR_BuildMI, /*InsnID*/6, /*Opcode*/GIMT_Encode2(TargetOpcode::COPY),
        GIR_AddTempRegister, /*InsnID*/6, /*TempRegID*/5, /*TempRegFlags*/GIMT_Encode2(RegState::Define),
        GIR_CopySubReg, /*NewInsnID*/6, /*OldInsnID*/1, /*OpIdx*/2, /*SubRegIdx*/GIMT_Encode2(3), // y
        GIR_ConstrainOperandRC, /*InsnID*/6, /*Op*/0, GIMT_Encode2(AMDGPU::VGPR_32RegClassID),
        GIR_ConstrainOperandRC, /*InsnID*/6, /*Op*/1, GIMT_Encode2(AMDGPU::VReg_64RegClassID),
        GIR_BuildMI, /*InsnID*/5, /*Opcode*/GIMT_Encode2(TargetOpcode::COPY),
        GIR_AddTempRegister, /*InsnID*/5, /*TempRegID*/4, /*TempRegFlags*/GIMT_Encode2(RegState::Define),
        GIR_CopySubReg, /*NewInsnID*/5, /*OldInsnID*/2, /*OpIdx*/1, /*SubRegIdx*/GIMT_Encode2(3), // z
        GIR_ConstrainOperandRC, /*InsnID*/5, /*Op*/0, GIMT_Encode2(AMDGPU::VGPR_32RegClassID),
        GIR_ConstrainOperandRC, /*InsnID*/5, /*Op*/1, GIMT_Encode2(AMDGPU::VReg_64RegClassID),
        GIR_BuildMI, /*InsnID*/4, /*Opcode*/GIMT_Encode2(TargetOpcode::COPY),
        GIR_AddTempRegister, /*InsnID*/4, /*TempRegID*/3, /*TempRegFlags*/GIMT_Encode2(RegState::Define),
        GIR_CopySubReg, /*NewInsnID*/4, /*OldInsnID*/1, /*OpIdx*/2, /*SubRegIdx*/GIMT_Encode2(3), // y
        GIR_ConstrainOperandRC, /*InsnID*/4, /*Op*/0, GIMT_Encode2(AMDGPU::VGPR_32RegClassID),
        GIR_ConstrainOperandRC, /*InsnID*/4, /*Op*/1, GIMT_Encode2(AMDGPU::VReg_64RegClassID),
        GIR_BuildMI, /*InsnID*/3, /*Opcode*/GIMT_Encode2(TargetOpcode::COPY),
        GIR_AddTempRegister, /*InsnID*/3, /*TempRegID*/2, /*TempRegFlags*/GIMT_Encode2(RegState::Define),
        GIR_CopySubReg, /*NewInsnID*/3, /*OldInsnID*/2, /*OpIdx*/2, /*SubRegIdx*/GIMT_Encode2(3), // x
        GIR_ConstrainOperandRC, /*InsnID*/3, /*Op*/0, GIMT_Encode2(AMDGPU::VGPR_32RegClassID),
        GIR_ConstrainOperandRC, /*InsnID*/3, /*Op*/1, GIMT_Encode2(AMDGPU::VReg_64RegClassID),
        GIR_BuildMI, /*InsnID*/2, /*Opcode*/GIMT_Encode2(AMDGPU::V_XOR_B32_e64),
        GIR_AddTempRegister, /*InsnID*/2, /*TempRegID*/1, /*TempRegFlags*/GIMT_Encode2(RegState::Define),
        GIR_AddSimpleTempRegister, /*InsnID*/2, /*TempRegID*/2,
        GIR_AddSimpleTempRegister, /*InsnID*/2, /*TempRegID*/3,
        GIR_ConstrainSelectedInstOperands, /*InsnID*/2,
        GIR_BuildMI, /*InsnID*/1, /*Opcode*/GIMT_Encode2(AMDGPU::V_BFI_B32_e64),
        GIR_AddTempRegister, /*InsnID*/1, /*TempRegID*/0, /*TempRegFlags*/GIMT_Encode2(RegState::Define),
        GIR_AddSimpleTempRegister, /*InsnID*/1, /*TempRegID*/1,
        GIR_AddSimpleTempRegister, /*InsnID*/1, /*TempRegID*/4,
        GIR_AddSimpleTempRegister, /*InsnID*/1, /*TempRegID*/5,
        GIR_ConstrainSelectedInstOperands, /*InsnID*/1,
        GIR_BuildMI, /*InsnID*/0, /*Opcode*/GIMT_Encode2(TargetOpcode::REG_SEQUENCE),
        GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/0, // DstI[dst]
        GIR_AddSimpleTempRegister, /*InsnID*/0, /*TempRegID*/0,
        GIR_AddImm8, /*InsnID*/0, /*SubRegIndex*/3,
        GIR_AddSimpleTempRegister, /*InsnID*/0, /*TempRegID*/6,
        GIR_AddImm8, /*InsnID*/0, /*SubRegIndex*/11,
        GIR_ConstrainOperandRC, /*InsnID*/0, /*Op*/0, GIMT_Encode2(AMDGPU::VReg_64RegClassID),
        GIR_ConstrainOperandRC, /*InsnID*/0, /*Op*/1, GIMT_Encode2(AMDGPU::VGPR_32RegClassID),
        GIR_ConstrainOperandRC, /*InsnID*/0, /*Op*/3, GIMT_Encode2(AMDGPU::VGPR_32RegClassID),
        GIR_EraseFromParent, /*InsnID*/0,
        // GIR_Coverage, 9938,
        GIR_Done,
      // Label 347: @28288
      GIM_Try, /*On fail goto*//*Label 348*/ GIMT_Encode4(28706), // Rule ID 9939 //
        GIM_CheckRegBankForClass, /*MI*/0, /*Op*/0, /*RC*/GIMT_Encode2(AMDGPU::VReg_64RegClassID),
        GIM_RecordInsnIgnoreCopies, /*DefineMI*/1, /*MI*/0, /*OpIdx*/1, // MIs[1]
        GIM_CheckOpcode, /*MI*/1, GIMT_Encode2(TargetOpcode::G_AND),
        GIM_CheckType, /*MI*/1, /*Op*/1, /*Type*/GILLT_s64,
        GIM_CheckType, /*MI*/1, /*Op*/2, /*Type*/GILLT_s64,
        GIM_RecordInsnIgnoreCopies, /*DefineMI*/2, /*MI*/1, /*OpIdx*/1, // MIs[2]
        GIM_CheckOpcode, /*MI*/2, GIMT_Encode2(TargetOpcode::G_OR),
        GIM_CheckType, /*MI*/2, /*Op*/1, /*Type*/GILLT_s64,
        GIM_CheckType, /*MI*/2, /*Op*/2, /*Type*/GILLT_s64,
        GIM_RecordInsnIgnoreCopies, /*DefineMI*/3, /*MI*/0, /*OpIdx*/2, // MIs[3]
        GIM_CheckOpcode, /*MI*/3, GIMT_Encode2(TargetOpcode::G_AND),
        // MIs[3] z
        GIM_CheckIsSameOperandIgnoreCopies, /*MI*/3, /*OpIdx*/1, /*OtherMI*/2, /*OtherOpIdx*/1,
        // MIs[3] x
        GIM_CheckIsSameOperandIgnoreCopies, /*MI*/3, /*OpIdx*/2, /*OtherMI*/2, /*OtherOpIdx*/2,
        GIM_CheckCxxInsnPredicate, /*MI*/0, /*FnId*/GIMT_Encode2(GICXXPred_MI_Predicate_anonymous_22557),
        GIM_CheckIsSafeToFold, /*InsnID*/1,
        GIM_CheckIsSafeToFold, /*InsnID*/2,
        GIM_CheckIsSafeToFold, /*InsnID*/3,
        // (or:{ *:[i64] } (and:{ *:[i64] } (or:{ *:[i64] } i64:{ *:[i64] }:$z, i64:{ *:[i64] }:$x), i64:{ *:[i64] }:$y), (and:{ *:[i64] } i64:{ *:[i64] }:$z, i64:{ *:[i64] }:$x))<<P:Predicate_anonymous_22557>>  =>  (REG_SEQUENCE:{ *:[i64] } VReg_64:{ *:[i32] }, (V_BFI_B32_e64:{ *:[i16] } (V_XOR_B32_e64:{ *:[i16] } (EXTRACT_SUBREG:{ *:[i32] } VReg_64:{ *:[i64] }:$x, sub0:{ *:[i32] }), (EXTRACT_SUBREG:{ *:[i32] } VReg_64:{ *:[i64] }:$y, sub0:{ *:[i32] })), (EXTRACT_SUBREG:{ *:[i32] } VReg_64:{ *:[i64] }:$z, sub0:{ *:[i32] }), (EXTRACT_SUBREG:{ *:[i32] } VReg_64:{ *:[i64] }:$y, sub0:{ *:[i32] })), sub0:{ *:[i32] }, (V_BFI_B32_e64:{ *:[i16] } (V_XOR_B32_e64:{ *:[i16] } (EXTRACT_SUBREG:{ *:[i32] } VReg_64:{ *:[i64] }:$x, sub1:{ *:[i32] }), (EXTRACT_SUBREG:{ *:[i32] } VReg_64:{ *:[i64] }:$y, sub1:{ *:[i32] })), (EXTRACT_SUBREG:{ *:[i32] } VReg_64:{ *:[i64] }:$z, sub1:{ *:[i32] }), (EXTRACT_SUBREG:{ *:[i32] } VReg_64:{ *:[i64] }:$y, sub1:{ *:[i32] })), sub1:{ *:[i32] })
        GIR_MakeTempReg, /*TempRegID*/0, /*TypeID*/GILLT_s16,
        GIR_MakeTempReg, /*TempRegID*/1, /*TypeID*/GILLT_s16,
        GIR_MakeTempReg, /*TempRegID*/2, /*TypeID*/GILLT_s32,
        GIR_MakeTempReg, /*TempRegID*/3, /*TypeID*/GILLT_s32,
        GIR_MakeTempReg, /*TempRegID*/4, /*TypeID*/GILLT_s32,
        GIR_MakeTempReg, /*TempRegID*/5, /*TypeID*/GILLT_s32,
        GIR_MakeTempReg, /*TempRegID*/6, /*TypeID*/GILLT_s16,
        GIR_MakeTempReg, /*TempRegID*/7, /*TypeID*/GILLT_s16,
        GIR_MakeTempReg, /*TempRegID*/8, /*TypeID*/GILLT_s32,
        GIR_MakeTempReg, /*TempRegID*/9, /*TypeID*/GILLT_s32,
        GIR_MakeTempReg, /*TempRegID*/10, /*TypeID*/GILLT_s32,
        GIR_MakeTempReg, /*TempRegID*/11, /*TypeID*/GILLT_s32,
        GIR_BuildMI, /*InsnID*/12, /*Opcode*/GIMT_Encode2(TargetOpcode::COPY),
        GIR_AddTempRegister, /*InsnID*/12, /*TempRegID*/11, /*TempRegFlags*/GIMT_Encode2(RegState::Define),
        GIR_CopySubReg, /*NewInsnID*/12, /*OldInsnID*/1, /*OpIdx*/2, /*SubRegIdx*/GIMT_Encode2(11), // y
        GIR_ConstrainOperandRC, /*InsnID*/12, /*Op*/0, GIMT_Encode2(AMDGPU::VGPR_32RegClassID),
        GIR_ConstrainOperandRC, /*InsnID*/12, /*Op*/1, GIMT_Encode2(AMDGPU::VReg_64RegClassID),
        GIR_BuildMI, /*InsnID*/11, /*Opcode*/GIMT_Encode2(TargetOpcode::COPY),
        GIR_AddTempRegister, /*InsnID*/11, /*TempRegID*/10, /*TempRegFlags*/GIMT_Encode2(RegState::Define),
        GIR_CopySubReg, /*NewInsnID*/11, /*OldInsnID*/2, /*OpIdx*/1, /*SubRegIdx*/GIMT_Encode2(11), // z
        GIR_ConstrainOperandRC, /*InsnID*/11, /*Op*/0, GIMT_Encode2(AMDGPU::VGPR_32RegClassID),
        GIR_ConstrainOperandRC, /*InsnID*/11, /*Op*/1, GIMT_Encode2(AMDGPU::VReg_64RegClassID),
        GIR_BuildMI, /*InsnID*/10, /*Opcode*/GIMT_Encode2(TargetOpcode::COPY),
        GIR_AddTempRegister, /*InsnID*/10, /*TempRegID*/9, /*TempRegFlags*/GIMT_Encode2(RegState::Define),
        GIR_CopySubReg, /*NewInsnID*/10, /*OldInsnID*/1, /*OpIdx*/2, /*SubRegIdx*/GIMT_Encode2(11), // y
        GIR_ConstrainOperandRC, /*InsnID*/10, /*Op*/0, GIMT_Encode2(AMDGPU::VGPR_32RegClassID),
        GIR_ConstrainOperandRC, /*InsnID*/10, /*Op*/1, GIMT_Encode2(AMDGPU::VReg_64RegClassID),
        GIR_BuildMI, /*InsnID*/9, /*Opcode*/GIMT_Encode2(TargetOpcode::COPY),
        GIR_AddTempRegister, /*InsnID*/9, /*TempRegID*/8, /*TempRegFlags*/GIMT_Encode2(RegState::Define),
        GIR_CopySubReg, /*NewInsnID*/9, /*OldInsnID*/2, /*OpIdx*/2, /*SubRegIdx*/GIMT_Encode2(11), // x
        GIR_ConstrainOperandRC, /*InsnID*/9, /*Op*/0, GIMT_Encode2(AMDGPU::VGPR_32RegClassID),
        GIR_ConstrainOperandRC, /*InsnID*/9, /*Op*/1, GIMT_Encode2(AMDGPU::VReg_64RegClassID),
        GIR_BuildMI, /*InsnID*/8, /*Opcode*/GIMT_Encode2(AMDGPU::V_XOR_B32_e64),
        GIR_AddTempRegister, /*InsnID*/8, /*TempRegID*/7, /*TempRegFlags*/GIMT_Encode2(RegState::Define),
        GIR_AddSimpleTempRegister, /*InsnID*/8, /*TempRegID*/8,
        GIR_AddSimpleTempRegister, /*InsnID*/8, /*TempRegID*/9,
        GIR_ConstrainSelectedInstOperands, /*InsnID*/8,
        GIR_BuildMI, /*InsnID*/7, /*Opcode*/GIMT_Encode2(AMDGPU::V_BFI_B32_e64),
        GIR_AddTempRegister, /*InsnID*/7, /*TempRegID*/6, /*TempRegFlags*/GIMT_Encode2(RegState::Define),
        GIR_AddSimpleTempRegister, /*InsnID*/7, /*TempRegID*/7,
        GIR_AddSimpleTempRegister, /*InsnID*/7, /*TempRegID*/10,
        GIR_AddSimpleTempRegister, /*InsnID*/7, /*TempRegID*/11,
        GIR_ConstrainSelectedInstOperands, /*InsnID*/7,
        GIR_BuildMI, /*InsnID*/6, /*Opcode*/GIMT_Encode2(TargetOpcode::COPY),
        GIR_AddTempRegister, /*InsnID*/6, /*TempRegID*/5, /*TempRegFlags*/GIMT_Encode2(RegState::Define),
        GIR_CopySubReg, /*NewInsnID*/6, /*OldInsnID*/1, /*OpIdx*/2, /*SubRegIdx*/GIMT_Encode2(3), // y
        GIR_ConstrainOperandRC, /*InsnID*/6, /*Op*/0, GIMT_Encode2(AMDGPU::VGPR_32RegClassID),
        GIR_ConstrainOperandRC, /*InsnID*/6, /*Op*/1, GIMT_Encode2(AMDGPU::VReg_64RegClassID),
        GIR_BuildMI, /*InsnID*/5, /*Opcode*/GIMT_Encode2(TargetOpcode::COPY),
        GIR_AddTempRegister, /*InsnID*/5, /*TempRegID*/4, /*TempRegFlags*/GIMT_Encode2(RegState::Define),
        GIR_CopySubReg, /*NewInsnID*/5, /*OldInsnID*/2, /*OpIdx*/1, /*SubRegIdx*/GIMT_Encode2(3), // z
        GIR_ConstrainOperandRC, /*InsnID*/5, /*Op*/0, GIMT_Encode2(AMDGPU::VGPR_32RegClassID),
        GIR_ConstrainOperandRC, /*InsnID*/5, /*Op*/1, GIMT_Encode2(AMDGPU::VReg_64RegClassID),
        GIR_BuildMI, /*InsnID*/4, /*Opcode*/GIMT_Encode2(TargetOpcode::COPY),
        GIR_AddTempRegister, /*InsnID*/4, /*TempRegID*/3, /*TempRegFlags*/GIMT_Encode2(RegState::Define),
        GIR_CopySubReg, /*NewInsnID*/4, /*OldInsnID*/1, /*OpIdx*/2, /*SubRegIdx*/GIMT_Encode2(3), // y
        GIR_ConstrainOperandRC, /*InsnID*/4, /*Op*/0, GIMT_Encode2(AMDGPU::VGPR_32RegClassID),
        GIR_ConstrainOperandRC, /*InsnID*/4, /*Op*/1, GIMT_Encode2(AMDGPU::VReg_64RegClassID),
        GIR_BuildMI, /*InsnID*/3, /*Opcode*/GIMT_Encode2(TargetOpcode::COPY),
        GIR_AddTempRegister, /*InsnID*/3, /*TempRegID*/2, /*TempRegFlags*/GIMT_Encode2(RegState::Define),
        GIR_CopySubReg, /*NewInsnID*/3, /*OldInsnID*/2, /*OpIdx*/2, /*SubRegIdx*/GIMT_Encode2(3), // x
        GIR_ConstrainOperandRC, /*InsnID*/3, /*Op*/0, GIMT_Encode2(AMDGPU::VGPR_32RegClassID),
        GIR_ConstrainOperandRC, /*InsnID*/3, /*Op*/1, GIMT_Encode2(AMDGPU::VReg_64RegClassID),
        GIR_BuildMI, /*InsnID*/2, /*Opcode*/GIMT_Encode2(AMDGPU::V_XOR_B32_e64),
        GIR_AddTempRegister, /*InsnID*/2, /*TempRegID*/1, /*TempRegFlags*/GIMT_Encode2(RegState::Define),
        GIR_AddSimpleTempRegister, /*InsnID*/2, /*TempRegID*/2,
        GIR_AddSimpleTempRegister, /*InsnID*/2, /*TempRegID*/3,
        GIR_ConstrainSelectedInstOperands, /*InsnID*/2,
        GIR_BuildMI, /*InsnID*/1, /*Opcode*/GIMT_Encode2(AMDGPU::V_BFI_B32_e64),
        GIR_AddTempRegister, /*InsnID*/1, /*TempRegID*/0, /*TempRegFlags*/GIMT_Encode2(RegState::Define),
        GIR_AddSimpleTempRegister, /*InsnID*/1, /*TempRegID*/1,
        GIR_AddSimpleTempRegister, /*InsnID*/1, /*TempRegID*/4,
        GIR_AddSimpleTempRegister, /*InsnID*/1, /*TempRegID*/5,
        GIR_ConstrainSelectedInstOperands, /*InsnID*/1,
        GIR_BuildMI, /*InsnID*/0, /*Opcode*/GIMT_Encode2(TargetOpcode::REG_SEQUENCE),
        GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/0, // DstI[dst]
        GIR_AddSimpleTempRegister, /*InsnID*/0, /*TempRegID*/0,
        GIR_AddImm8, /*InsnID*/0, /*SubRegIndex*/3,
        GIR_AddSimpleTempRegister, /*InsnID*/0, /*TempRegID*/6,
        GIR_AddImm8, /*InsnID*/0, /*SubRegIndex*/11,
        GIR_ConstrainOperandRC, /*InsnID*/0, /*Op*/0, GIMT_Encode2(AMDGPU::VReg_64RegClassID),
        GIR_ConstrainOperandRC, /*InsnID*/0, /*Op*/1, GIMT_Encode2(AMDGPU::VGPR_32RegClassID),
        GIR_ConstrainOperandRC, /*InsnID*/0, /*Op*/3, GIMT_Encode2(AMDGPU::VGPR_32RegClassID),
        GIR_EraseFromParent, /*InsnID*/0,
        // GIR_Coverage, 9939,
        GIR_Done,
      // Label 348: @28706
      GIM_Try, /*On fail goto*//*Label 349*/ GIMT_Encode4(29124), // Rule ID 9932 //
        GIM_CheckRegBankForClass, /*MI*/0, /*Op*/0, /*RC*/GIMT_Encode2(AMDGPU::VReg_64RegClassID),
        GIM_RecordInsnIgnoreCopies, /*DefineMI*/1, /*MI*/0, /*OpIdx*/1, // MIs[1]
        GIM_CheckOpcode, /*MI*/1, GIMT_Encode2(TargetOpcode::G_AND),
        GIM_CheckType, /*MI*/1, /*Op*/1, /*Type*/GILLT_s64,
        GIM_CheckType, /*MI*/1, /*Op*/2, /*Type*/GILLT_s64,
        GIM_RecordInsnIgnoreCopies, /*DefineMI*/2, /*MI*/1, /*OpIdx*/2, // MIs[2]
        GIM_CheckOpcode, /*MI*/2, GIMT_Encode2(TargetOpcode::G_OR),
        GIM_CheckType, /*MI*/2, /*Op*/1, /*Type*/GILLT_s64,
        GIM_CheckType, /*MI*/2, /*Op*/2, /*Type*/GILLT_s64,
        GIM_RecordInsnIgnoreCopies, /*DefineMI*/3, /*MI*/0, /*OpIdx*/2, // MIs[3]
        GIM_CheckOpcode, /*MI*/3, GIMT_Encode2(TargetOpcode::G_AND),
        // MIs[3] x
        GIM_CheckIsSameOperandIgnoreCopies, /*MI*/3, /*OpIdx*/1, /*OtherMI*/2, /*OtherOpIdx*/1,
        // MIs[3] z
        GIM_CheckIsSameOperandIgnoreCopies, /*MI*/3, /*OpIdx*/2, /*OtherMI*/2, /*OtherOpIdx*/2,
        GIM_CheckCxxInsnPredicate, /*MI*/0, /*FnId*/GIMT_Encode2(GICXXPred_MI_Predicate_anonymous_22557),
        GIM_CheckIsSafeToFold, /*InsnID*/1,
        GIM_CheckIsSafeToFold, /*InsnID*/2,
        GIM_CheckIsSafeToFold, /*InsnID*/3,
        // (or:{ *:[i64] } (and:{ *:[i64] } i64:{ *:[i64] }:$y, (or:{ *:[i64] } i64:{ *:[i64] }:$x, i64:{ *:[i64] }:$z)), (and:{ *:[i64] } i64:{ *:[i64] }:$x, i64:{ *:[i64] }:$z))<<P:Predicate_anonymous_22557>>  =>  (REG_SEQUENCE:{ *:[i64] } VReg_64:{ *:[i32] }, (V_BFI_B32_e64:{ *:[i16] } (V_XOR_B32_e64:{ *:[i16] } (EXTRACT_SUBREG:{ *:[i32] } VReg_64:{ *:[i64] }:$x, sub0:{ *:[i32] }), (EXTRACT_SUBREG:{ *:[i32] } VReg_64:{ *:[i64] }:$y, sub0:{ *:[i32] })), (EXTRACT_SUBREG:{ *:[i32] } VReg_64:{ *:[i64] }:$z, sub0:{ *:[i32] }), (EXTRACT_SUBREG:{ *:[i32] } VReg_64:{ *:[i64] }:$y, sub0:{ *:[i32] })), sub0:{ *:[i32] }, (V_BFI_B32_e64:{ *:[i16] } (V_XOR_B32_e64:{ *:[i16] } (EXTRACT_SUBREG:{ *:[i32] } VReg_64:{ *:[i64] }:$x, sub1:{ *:[i32] }), (EXTRACT_SUBREG:{ *:[i32] } VReg_64:{ *:[i64] }:$y, sub1:{ *:[i32] })), (EXTRACT_SUBREG:{ *:[i32] } VReg_64:{ *:[i64] }:$z, sub1:{ *:[i32] }), (EXTRACT_SUBREG:{ *:[i32] } VReg_64:{ *:[i64] }:$y, sub1:{ *:[i32] })), sub1:{ *:[i32] })
        GIR_MakeTempReg, /*TempRegID*/0, /*TypeID*/GILLT_s16,
        GIR_MakeTempReg, /*TempRegID*/1, /*TypeID*/GILLT_s16,
        GIR_MakeTempReg, /*TempRegID*/2, /*TypeID*/GILLT_s32,
        GIR_MakeTempReg, /*TempRegID*/3, /*TypeID*/GILLT_s32,
        GIR_MakeTempReg, /*TempRegID*/4, /*TypeID*/GILLT_s32,
        GIR_MakeTempReg, /*TempRegID*/5, /*TypeID*/GILLT_s32,
        GIR_MakeTempReg, /*TempRegID*/6, /*TypeID*/GILLT_s16,
        GIR_MakeTempReg, /*TempRegID*/7, /*TypeID*/GILLT_s16,
        GIR_MakeTempReg, /*TempRegID*/8, /*TypeID*/GILLT_s32,
        GIR_MakeTempReg, /*TempRegID*/9, /*TypeID*/GILLT_s32,
        GIR_MakeTempReg, /*TempRegID*/10, /*TypeID*/GILLT_s32,
        GIR_MakeTempReg, /*TempRegID*/11, /*TypeID*/GILLT_s32,
        GIR_BuildMI, /*InsnID*/12, /*Opcode*/GIMT_Encode2(TargetOpcode::COPY),
        GIR_AddTempRegister, /*InsnID*/12, /*TempRegID*/11, /*TempRegFlags*/GIMT_Encode2(RegState::Define),
        GIR_CopySubReg, /*NewInsnID*/12, /*OldInsnID*/1, /*OpIdx*/1, /*SubRegIdx*/GIMT_Encode2(11), // y
        GIR_ConstrainOperandRC, /*InsnID*/12, /*Op*/0, GIMT_Encode2(AMDGPU::VGPR_32RegClassID),
        GIR_ConstrainOperandRC, /*InsnID*/12, /*Op*/1, GIMT_Encode2(AMDGPU::VReg_64RegClassID),
        GIR_BuildMI, /*InsnID*/11, /*Opcode*/GIMT_Encode2(TargetOpcode::COPY),
        GIR_AddTempRegister, /*InsnID*/11, /*TempRegID*/10, /*TempRegFlags*/GIMT_Encode2(RegState::Define),
        GIR_CopySubReg, /*NewInsnID*/11, /*OldInsnID*/2, /*OpIdx*/2, /*SubRegIdx*/GIMT_Encode2(11), // z
        GIR_ConstrainOperandRC, /*InsnID*/11, /*Op*/0, GIMT_Encode2(AMDGPU::VGPR_32RegClassID),
        GIR_ConstrainOperandRC, /*InsnID*/11, /*Op*/1, GIMT_Encode2(AMDGPU::VReg_64RegClassID),
        GIR_BuildMI, /*InsnID*/10, /*Opcode*/GIMT_Encode2(TargetOpcode::COPY),
        GIR_AddTempRegister, /*InsnID*/10, /*TempRegID*/9, /*TempRegFlags*/GIMT_Encode2(RegState::Define),
        GIR_CopySubReg, /*NewInsnID*/10, /*OldInsnID*/1, /*OpIdx*/1, /*SubRegIdx*/GIMT_Encode2(11), // y
        GIR_ConstrainOperandRC, /*InsnID*/10, /*Op*/0, GIMT_Encode2(AMDGPU::VGPR_32RegClassID),
        GIR_ConstrainOperandRC, /*InsnID*/10, /*Op*/1, GIMT_Encode2(AMDGPU::VReg_64RegClassID),
        GIR_BuildMI, /*InsnID*/9, /*Opcode*/GIMT_Encode2(TargetOpcode::COPY),
        GIR_AddTempRegister, /*InsnID*/9, /*TempRegID*/8, /*TempRegFlags*/GIMT_Encode2(RegState::Define),
        GIR_CopySubReg, /*NewInsnID*/9, /*OldInsnID*/2, /*OpIdx*/1, /*SubRegIdx*/GIMT_Encode2(11), // x
        GIR_ConstrainOperandRC, /*InsnID*/9, /*Op*/0, GIMT_Encode2(AMDGPU::VGPR_32RegClassID),
        GIR_ConstrainOperandRC, /*InsnID*/9, /*Op*/1, GIMT_Encode2(AMDGPU::VReg_64RegClassID),
        GIR_BuildMI, /*InsnID*/8, /*Opcode*/GIMT_Encode2(AMDGPU::V_XOR_B32_e64),
        GIR_AddTempRegister, /*InsnID*/8, /*TempRegID*/7, /*TempRegFlags*/GIMT_Encode2(RegState::Define),
        GIR_AddSimpleTempRegister, /*InsnID*/8, /*TempRegID*/8,
        GIR_AddSimpleTempRegister, /*InsnID*/8, /*TempRegID*/9,
        GIR_ConstrainSelectedInstOperands, /*InsnID*/8,
        GIR_BuildMI, /*InsnID*/7, /*Opcode*/GIMT_Encode2(AMDGPU::V_BFI_B32_e64),
        GIR_AddTempRegister, /*InsnID*/7, /*TempRegID*/6, /*TempRegFlags*/GIMT_Encode2(RegState::Define),
        GIR_AddSimpleTempRegister, /*InsnID*/7, /*TempRegID*/7,
        GIR_AddSimpleTempRegister, /*InsnID*/7, /*TempRegID*/10,
        GIR_AddSimpleTempRegister, /*InsnID*/7, /*TempRegID*/11,
        GIR_ConstrainSelectedInstOperands, /*InsnID*/7,
        GIR_BuildMI, /*InsnID*/6, /*Opcode*/GIMT_Encode2(TargetOpcode::COPY),
        GIR_AddTempRegister, /*InsnID*/6, /*TempRegID*/5, /*TempRegFlags*/GIMT_Encode2(RegState::Define),
        GIR_CopySubReg, /*NewInsnID*/6, /*OldInsnID*/1, /*OpIdx*/1, /*SubRegIdx*/GIMT_Encode2(3), // y
        GIR_ConstrainOperandRC, /*InsnID*/6, /*Op*/0, GIMT_Encode2(AMDGPU::VGPR_32RegClassID),
        GIR_ConstrainOperandRC, /*InsnID*/6, /*Op*/1, GIMT_Encode2(AMDGPU::VReg_64RegClassID),
        GIR_BuildMI, /*InsnID*/5, /*Opcode*/GIMT_Encode2(TargetOpcode::COPY),
        GIR_AddTempRegister, /*InsnID*/5, /*TempRegID*/4, /*TempRegFlags*/GIMT_Encode2(RegState::Define),
        GIR_CopySubReg, /*NewInsnID*/5, /*OldInsnID*/2, /*OpIdx*/2, /*SubRegIdx*/GIMT_Encode2(3), // z
        GIR_ConstrainOperandRC, /*InsnID*/5, /*Op*/0, GIMT_Encode2(AMDGPU::VGPR_32RegClassID),
        GIR_ConstrainOperandRC, /*InsnID*/5, /*Op*/1, GIMT_Encode2(AMDGPU::VReg_64RegClassID),
        GIR_BuildMI, /*InsnID*/4, /*Opcode*/GIMT_Encode2(TargetOpcode::COPY),
        GIR_AddTempRegister, /*InsnID*/4, /*TempRegID*/3, /*TempRegFlags*/GIMT_Encode2(RegState::Define),
        GIR_CopySubReg, /*NewInsnID*/4, /*OldInsnID*/1, /*OpIdx*/1, /*SubRegIdx*/GIMT_Encode2(3), // y
        GIR_ConstrainOperandRC, /*InsnID*/4, /*Op*/0, GIMT_Encode2(AMDGPU::VGPR_32RegClassID),
        GIR_ConstrainOperandRC, /*InsnID*/4, /*Op*/1, GIMT_Encode2(AMDGPU::VReg_64RegClassID),
        GIR_BuildMI, /*InsnID*/3, /*Opcode*/GIMT_Encode2(TargetOpcode::COPY),
        GIR_AddTempRegister, /*InsnID*/3, /*TempRegID*/2, /*TempRegFlags*/GIMT_Encode2(RegState::Define),
        GIR_CopySubReg, /*NewInsnID*/3, /*OldInsnID*/2, /*OpIdx*/1, /*SubRegIdx*/GIMT_Encode2(3), // x
        GIR_ConstrainOperandRC, /*InsnID*/3, /*Op*/0, GIMT_Encode2(AMDGPU::VGPR_32RegClassID),
        GIR_ConstrainOperandRC, /*InsnID*/3, /*Op*/1, GIMT_Encode2(AMDGPU::VReg_64RegClassID),
        GIR_BuildMI, /*InsnID*/2, /*Opcode*/GIMT_Encode2(AMDGPU::V_XOR_B32_e64),
        GIR_AddTempRegister, /*InsnID*/2, /*TempRegID*/1, /*TempRegFlags*/GIMT_Encode2(RegState::Define),
        GIR_AddSimpleTempRegister, /*InsnID*/2, /*TempRegID*/2,
        GIR_AddSimpleTempRegister, /*InsnID*/2, /*TempRegID*/3,
        GIR_ConstrainSelectedInstOperands, /*InsnID*/2,
        GIR_BuildMI, /*InsnID*/1, /*Opcode*/GIMT_Encode2(AMDGPU::V_BFI_B32_e64),
        GIR_AddTempRegister, /*InsnID*/1, /*TempRegID*/0, /*TempRegFlags*/GIMT_Encode2(RegState::Define),
        GIR_AddSimpleTempRegister, /*InsnID*/1, /*TempRegID*/1,
        GIR_AddSimpleTempRegister, /*InsnID*/1, /*TempRegID*/4,
        GIR_AddSimpleTempRegister, /*InsnID*/1, /*TempRegID*/5,
        GIR_ConstrainSelectedInstOperands, /*InsnID*/1,
        GIR_BuildMI, /*InsnID*/0, /*Opcode*/GIMT_Encode2(TargetOpcode::REG_SEQUENCE),
        GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/0, // DstI[dst]
        GIR_AddSimpleTempRegister, /*InsnID*/0, /*TempRegID*/0,
        GIR_AddImm8, /*InsnID*/0, /*SubRegIndex*/3,
        GIR_AddSimpleTempRegister, /*InsnID*/0, /*TempRegID*/6,
        GIR_AddImm8, /*InsnID*/0, /*SubRegIndex*/11,
        GIR_ConstrainOperandRC, /*InsnID*/0, /*Op*/0, GIMT_Encode2(AMDGPU::VReg_64RegClassID),
        GIR_ConstrainOperandRC, /*InsnID*/0, /*Op*/1, GIMT_Encode2(AMDGPU::VGPR_32RegClassID),
        GIR_ConstrainOperandRC, /*InsnID*/0, /*Op*/3, GIMT_Encode2(AMDGPU::VGPR_32RegClassID),
        GIR_EraseFromParent, /*InsnID*/0,
        // GIR_Coverage, 9932,
        GIR_Done,
      // Label 349: @29124
      GIM_Try, /*On fail goto*//*Label 350*/ GIMT_Encode4(29542), // Rule ID 9933 //
        GIM_CheckRegBankForClass, /*MI*/0, /*Op*/0, /*RC*/GIMT_Encode2(AMDGPU::VReg_64RegClassID),
        GIM_RecordInsnIgnoreCopies, /*DefineMI*/1, /*MI*/0, /*OpIdx*/1, // MIs[1]
        GIM_CheckOpcode, /*MI*/1, GIMT_Encode2(TargetOpcode::G_AND),
        GIM_CheckType, /*MI*/1, /*Op*/1, /*Type*/GILLT_s64,
        GIM_CheckType, /*MI*/1, /*Op*/2, /*Type*/GILLT_s64,
        GIM_RecordInsnIgnoreCopies, /*DefineMI*/2, /*MI*/1, /*OpIdx*/2, // MIs[2]
        GIM_CheckOpcode, /*MI*/2, GIMT_Encode2(TargetOpcode::G_OR),
        GIM_CheckType, /*MI*/2, /*Op*/1, /*Type*/GILLT_s64,
        GIM_CheckType, /*MI*/2, /*Op*/2, /*Type*/GILLT_s64,
        GIM_RecordInsnIgnoreCopies, /*DefineMI*/3, /*MI*/0, /*OpIdx*/2, // MIs[3]
        GIM_CheckOpcode, /*MI*/3, GIMT_Encode2(TargetOpcode::G_AND),
        // MIs[3] z
        GIM_CheckIsSameOperandIgnoreCopies, /*MI*/3, /*OpIdx*/1, /*OtherMI*/2, /*OtherOpIdx*/2,
        // MIs[3] x
        GIM_CheckIsSameOperandIgnoreCopies, /*MI*/3, /*OpIdx*/2, /*OtherMI*/2, /*OtherOpIdx*/1,
        GIM_CheckCxxInsnPredicate, /*MI*/0, /*FnId*/GIMT_Encode2(GICXXPred_MI_Predicate_anonymous_22557),
        GIM_CheckIsSafeToFold, /*InsnID*/1,
        GIM_CheckIsSafeToFold, /*InsnID*/2,
        GIM_CheckIsSafeToFold, /*InsnID*/3,
        // (or:{ *:[i64] } (and:{ *:[i64] } i64:{ *:[i64] }:$y, (or:{ *:[i64] } i64:{ *:[i64] }:$x, i64:{ *:[i64] }:$z)), (and:{ *:[i64] } i64:{ *:[i64] }:$z, i64:{ *:[i64] }:$x))<<P:Predicate_anonymous_22557>>  =>  (REG_SEQUENCE:{ *:[i64] } VReg_64:{ *:[i32] }, (V_BFI_B32_e64:{ *:[i16] } (V_XOR_B32_e64:{ *:[i16] } (EXTRACT_SUBREG:{ *:[i32] } VReg_64:{ *:[i64] }:$x, sub0:{ *:[i32] }), (EXTRACT_SUBREG:{ *:[i32] } VReg_64:{ *:[i64] }:$y, sub0:{ *:[i32] })), (EXTRACT_SUBREG:{ *:[i32] } VReg_64:{ *:[i64] }:$z, sub0:{ *:[i32] }), (EXTRACT_SUBREG:{ *:[i32] } VReg_64:{ *:[i64] }:$y, sub0:{ *:[i32] })), sub0:{ *:[i32] }, (V_BFI_B32_e64:{ *:[i16] } (V_XOR_B32_e64:{ *:[i16] } (EXTRACT_SUBREG:{ *:[i32] } VReg_64:{ *:[i64] }:$x, sub1:{ *:[i32] }), (EXTRACT_SUBREG:{ *:[i32] } VReg_64:{ *:[i64] }:$y, sub1:{ *:[i32] })), (EXTRACT_SUBREG:{ *:[i32] } VReg_64:{ *:[i64] }:$z, sub1:{ *:[i32] }), (EXTRACT_SUBREG:{ *:[i32] } VReg_64:{ *:[i64] }:$y, sub1:{ *:[i32] })), sub1:{ *:[i32] })
        GIR_MakeTempReg, /*TempRegID*/0, /*TypeID*/GILLT_s16,
        GIR_MakeTempReg, /*TempRegID*/1, /*TypeID*/GILLT_s16,
        GIR_MakeTempReg, /*TempRegID*/2, /*TypeID*/GILLT_s32,
        GIR_MakeTempReg, /*TempRegID*/3, /*TypeID*/GILLT_s32,
        GIR_MakeTempReg, /*TempRegID*/4, /*TypeID*/GILLT_s32,
        GIR_MakeTempReg, /*TempRegID*/5, /*TypeID*/GILLT_s32,
        GIR_MakeTempReg, /*TempRegID*/6, /*TypeID*/GILLT_s16,
        GIR_MakeTempReg, /*TempRegID*/7, /*TypeID*/GILLT_s16,
        GIR_MakeTempReg, /*TempRegID*/8, /*TypeID*/GILLT_s32,
        GIR_MakeTempReg, /*TempRegID*/9, /*TypeID*/GILLT_s32,
        GIR_MakeTempReg, /*TempRegID*/10, /*TypeID*/GILLT_s32,
        GIR_MakeTempReg, /*TempRegID*/11, /*TypeID*/GILLT_s32,
        GIR_BuildMI, /*InsnID*/12, /*Opcode*/GIMT_Encode2(TargetOpcode::COPY),
        GIR_AddTempRegister, /*InsnID*/12, /*TempRegID*/11, /*TempRegFlags*/GIMT_Encode2(RegState::Define),
        GIR_CopySubReg, /*NewInsnID*/12, /*OldInsnID*/1, /*OpIdx*/1, /*SubRegIdx*/GIMT_Encode2(11), // y
        GIR_ConstrainOperandRC, /*InsnID*/12, /*Op*/0, GIMT_Encode2(AMDGPU::VGPR_32RegClassID),
        GIR_ConstrainOperandRC, /*InsnID*/12, /*Op*/1, GIMT_Encode2(AMDGPU::VReg_64RegClassID),
        GIR_BuildMI, /*InsnID*/11, /*Opcode*/GIMT_Encode2(TargetOpcode::COPY),
        GIR_AddTempRegister, /*InsnID*/11, /*TempRegID*/10, /*TempRegFlags*/GIMT_Encode2(RegState::Define),
        GIR_CopySubReg, /*NewInsnID*/11, /*OldInsnID*/2, /*OpIdx*/2, /*SubRegIdx*/GIMT_Encode2(11), // z
        GIR_ConstrainOperandRC, /*InsnID*/11, /*Op*/0, GIMT_Encode2(AMDGPU::VGPR_32RegClassID),
        GIR_ConstrainOperandRC, /*InsnID*/11, /*Op*/1, GIMT_Encode2(AMDGPU::VReg_64RegClassID),
        GIR_BuildMI, /*InsnID*/10, /*Opcode*/GIMT_Encode2(TargetOpcode::COPY),
        GIR_AddTempRegister, /*InsnID*/10, /*TempRegID*/9, /*TempRegFlags*/GIMT_Encode2(RegState::Define),
        GIR_CopySubReg, /*NewInsnID*/10, /*OldInsnID*/1, /*OpIdx*/1, /*SubRegIdx*/GIMT_Encode2(11), // y
        GIR_ConstrainOperandRC, /*InsnID*/10, /*Op*/0, GIMT_Encode2(AMDGPU::VGPR_32RegClassID),
        GIR_ConstrainOperandRC, /*InsnID*/10, /*Op*/1, GIMT_Encode2(AMDGPU::VReg_64RegClassID),
        GIR_BuildMI, /*InsnID*/9, /*Opcode*/GIMT_Encode2(TargetOpcode::COPY),
        GIR_AddTempRegister, /*InsnID*/9, /*TempRegID*/8, /*TempRegFlags*/GIMT_Encode2(RegState::Define),
        GIR_CopySubReg, /*NewInsnID*/9, /*OldInsnID*/2, /*OpIdx*/1, /*SubRegIdx*/GIMT_Encode2(11), // x
        GIR_ConstrainOperandRC, /*InsnID*/9, /*Op*/0, GIMT_Encode2(AMDGPU::VGPR_32RegClassID),
        GIR_ConstrainOperandRC, /*InsnID*/9, /*Op*/1, GIMT_Encode2(AMDGPU::VReg_64RegClassID),
        GIR_BuildMI, /*InsnID*/8, /*Opcode*/GIMT_Encode2(AMDGPU::V_XOR_B32_e64),
        GIR_AddTempRegister, /*InsnID*/8, /*TempRegID*/7, /*TempRegFlags*/GIMT_Encode2(RegState::Define),
        GIR_AddSimpleTempRegister, /*InsnID*/8, /*TempRegID*/8,
        GIR_AddSimpleTempRegister, /*InsnID*/8, /*TempRegID*/9,
        GIR_ConstrainSelectedInstOperands, /*InsnID*/8,
        GIR_BuildMI, /*InsnID*/7, /*Opcode*/GIMT_Encode2(AMDGPU::V_BFI_B32_e64),
        GIR_AddTempRegister, /*InsnID*/7, /*TempRegID*/6, /*TempRegFlags*/GIMT_Encode2(RegState::Define),
        GIR_AddSimpleTempRegister, /*InsnID*/7, /*TempRegID*/7,
        GIR_AddSimpleTempRegister, /*InsnID*/7, /*TempRegID*/10,
        GIR_AddSimpleTempRegister, /*InsnID*/7, /*TempRegID*/11,
        GIR_ConstrainSelectedInstOperands, /*InsnID*/7,
        GIR_BuildMI, /*InsnID*/6, /*Opcode*/GIMT_Encode2(TargetOpcode::COPY),
        GIR_AddTempRegister, /*InsnID*/6, /*TempRegID*/5, /*TempRegFlags*/GIMT_Encode2(RegState::Define),
        GIR_CopySubReg, /*NewInsnID*/6, /*OldInsnID*/1, /*OpIdx*/1, /*SubRegIdx*/GIMT_Encode2(3), // y
        GIR_ConstrainOperandRC, /*InsnID*/6, /*Op*/0, GIMT_Encode2(AMDGPU::VGPR_32RegClassID),
        GIR_ConstrainOperandRC, /*InsnID*/6, /*Op*/1, GIMT_Encode2(AMDGPU::VReg_64RegClassID),
        GIR_BuildMI, /*InsnID*/5, /*Opcode*/GIMT_Encode2(TargetOpcode::COPY),
        GIR_AddTempRegister, /*InsnID*/5, /*TempRegID*/4, /*TempRegFlags*/GIMT_Encode2(RegState::Define),
        GIR_CopySubReg, /*NewInsnID*/5, /*OldInsnID*/2, /*OpIdx*/2, /*SubRegIdx*/GIMT_Encode2(3), // z
        GIR_ConstrainOperandRC, /*InsnID*/5, /*Op*/0, GIMT_Encode2(AMDGPU::VGPR_32RegClassID),
        GIR_ConstrainOperandRC, /*InsnID*/5, /*Op*/1, GIMT_Encode2(AMDGPU::VReg_64RegClassID),
        GIR_BuildMI, /*InsnID*/4, /*Opcode*/GIMT_Encode2(TargetOpcode::COPY),
        GIR_AddTempRegister, /*InsnID*/4, /*TempRegID*/3, /*TempRegFlags*/GIMT_Encode2(RegState::Define),
        GIR_CopySubReg, /*NewInsnID*/4, /*OldInsnID*/1, /*OpIdx*/1, /*SubRegIdx*/GIMT_Encode2(3), // y
        GIR_ConstrainOperandRC, /*InsnID*/4, /*Op*/0, GIMT_Encode2(AMDGPU::VGPR_32RegClassID),
        GIR_ConstrainOperandRC, /*InsnID*/4, /*Op*/1, GIMT_Encode2(AMDGPU::VReg_64RegClassID),
        GIR_BuildMI, /*InsnID*/3, /*Opcode*/GIMT_Encode2(TargetOpcode::COPY),
        GIR_AddTempRegister, /*InsnID*/3, /*TempRegID*/2, /*TempRegFlags*/GIMT_Encode2(RegState::Define),
        GIR_CopySubReg, /*NewInsnID*/3, /*OldInsnID*/2, /*OpIdx*/1, /*SubRegIdx*/GIMT_Encode2(3), // x
        GIR_ConstrainOperandRC, /*InsnID*/3, /*Op*/0, GIMT_Encode2(AMDGPU::VGPR_32RegClassID),
        GIR_ConstrainOperandRC, /*InsnID*/3, /*Op*/1, GIMT_Encode2(AMDGPU::VReg_64RegClassID),
        GIR_BuildMI, /*InsnID*/2, /*Opcode*/GIMT_Encode2(AMDGPU::V_XOR_B32_e64),
        GIR_AddTempRegister, /*InsnID*/2, /*TempRegID*/1, /*TempRegFlags*/GIMT_Encode2(RegState::Define),
        GIR_AddSimpleTempRegister, /*InsnID*/2, /*TempRegID*/2,
        GIR_AddSimpleTempRegister, /*InsnID*/2, /*TempRegID*/3,
        GIR_ConstrainSelectedInstOperands, /*InsnID*/2,
        GIR_BuildMI, /*InsnID*/1, /*Opcode*/GIMT_Encode2(AMDGPU::V_BFI_B32_e64),
        GIR_AddTempRegister, /*InsnID*/1, /*TempRegID*/0, /*TempRegFlags*/GIMT_Encode2(RegState::Define),
        GIR_AddSimpleTempRegister, /*InsnID*/1, /*TempRegID*/1,
        GIR_AddSimpleTempRegister, /*InsnID*/1, /*TempRegID*/4,
        GIR_AddSimpleTempRegister, /*InsnID*/1, /*TempRegID*/5,
        GIR_ConstrainSelectedInstOperands, /*InsnID*/1,
        GIR_BuildMI, /*InsnID*/0, /*Opcode*/GIMT_Encode2(TargetOpcode::REG_SEQUENCE),
        GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/0, // DstI[dst]
        GIR_AddSimpleTempRegister, /*InsnID*/0, /*TempRegID*/0,
        GIR_AddImm8, /*InsnID*/0, /*SubRegIndex*/3,
        GIR_AddSimpleTempRegister, /*InsnID*/0, /*TempRegID*/6,
        GIR_AddImm8, /*InsnID*/0, /*SubRegIndex*/11,
        GIR_ConstrainOperandRC, /*InsnID*/0, /*Op*/0, GIMT_Encode2(AMDGPU::VReg_64RegClassID),
        GIR_ConstrainOperandRC, /*InsnID*/0, /*Op*/1, GIMT_Encode2(AMDGPU::VGPR_32RegClassID),
        GIR_ConstrainOperandRC, /*InsnID*/0, /*Op*/3, GIMT_Encode2(AMDGPU::VGPR_32RegClassID),
        GIR_EraseFromParent, /*InsnID*/0,
        // GIR_Coverage, 9933,
        GIR_Done,
      // Label 350: @29542
      GIM_Try, /*On fail goto*//*Label 351*/ GIMT_Encode4(29960), // Rule ID 9934 //
        GIM_CheckRegBankForClass, /*MI*/0, /*Op*/0, /*RC*/GIMT_Encode2(AMDGPU::VReg_64RegClassID),
        GIM_RecordInsnIgnoreCopies, /*DefineMI*/1, /*MI*/0, /*OpIdx*/1, // MIs[1]
        GIM_CheckOpcode, /*MI*/1, GIMT_Encode2(TargetOpcode::G_AND),
        GIM_CheckType, /*MI*/1, /*Op*/1, /*Type*/GILLT_s64,
        GIM_CheckType, /*MI*/1, /*Op*/2, /*Type*/GILLT_s64,
        GIM_RecordInsnIgnoreCopies, /*DefineMI*/2, /*MI*/1, /*OpIdx*/2, // MIs[2]
        GIM_CheckOpcode, /*MI*/2, GIMT_Encode2(TargetOpcode::G_OR),
        GIM_CheckType, /*MI*/2, /*Op*/1, /*Type*/GILLT_s64,
        GIM_CheckType, /*MI*/2, /*Op*/2, /*Type*/GILLT_s64,
        GIM_RecordInsnIgnoreCopies, /*DefineMI*/3, /*MI*/0, /*OpIdx*/2, // MIs[3]
        GIM_CheckOpcode, /*MI*/3, GIMT_Encode2(TargetOpcode::G_AND),
        // MIs[3] x
        GIM_CheckIsSameOperandIgnoreCopies, /*MI*/3, /*OpIdx*/1, /*OtherMI*/2, /*OtherOpIdx*/2,
        // MIs[3] z
        GIM_CheckIsSameOperandIgnoreCopies, /*MI*/3, /*OpIdx*/2, /*OtherMI*/2, /*OtherOpIdx*/1,
        GIM_CheckCxxInsnPredicate, /*MI*/0, /*FnId*/GIMT_Encode2(GICXXPred_MI_Predicate_anonymous_22557),
        GIM_CheckIsSafeToFold, /*InsnID*/1,
        GIM_CheckIsSafeToFold, /*InsnID*/2,
        GIM_CheckIsSafeToFold, /*InsnID*/3,
        // (or:{ *:[i64] } (and:{ *:[i64] } i64:{ *:[i64] }:$y, (or:{ *:[i64] } i64:{ *:[i64] }:$z, i64:{ *:[i64] }:$x)), (and:{ *:[i64] } i64:{ *:[i64] }:$x, i64:{ *:[i64] }:$z))<<P:Predicate_anonymous_22557>>  =>  (REG_SEQUENCE:{ *:[i64] } VReg_64:{ *:[i32] }, (V_BFI_B32_e64:{ *:[i16] } (V_XOR_B32_e64:{ *:[i16] } (EXTRACT_SUBREG:{ *:[i32] } VReg_64:{ *:[i64] }:$x, sub0:{ *:[i32] }), (EXTRACT_SUBREG:{ *:[i32] } VReg_64:{ *:[i64] }:$y, sub0:{ *:[i32] })), (EXTRACT_SUBREG:{ *:[i32] } VReg_64:{ *:[i64] }:$z, sub0:{ *:[i32] }), (EXTRACT_SUBREG:{ *:[i32] } VReg_64:{ *:[i64] }:$y, sub0:{ *:[i32] })), sub0:{ *:[i32] }, (V_BFI_B32_e64:{ *:[i16] } (V_XOR_B32_e64:{ *:[i16] } (EXTRACT_SUBREG:{ *:[i32] } VReg_64:{ *:[i64] }:$x, sub1:{ *:[i32] }), (EXTRACT_SUBREG:{ *:[i32] } VReg_64:{ *:[i64] }:$y, sub1:{ *:[i32] })), (EXTRACT_SUBREG:{ *:[i32] } VReg_64:{ *:[i64] }:$z, sub1:{ *:[i32] }), (EXTRACT_SUBREG:{ *:[i32] } VReg_64:{ *:[i64] }:$y, sub1:{ *:[i32] })), sub1:{ *:[i32] })
        GIR_MakeTempReg, /*TempRegID*/0, /*TypeID*/GILLT_s16,
        GIR_MakeTempReg, /*TempRegID*/1, /*TypeID*/GILLT_s16,
        GIR_MakeTempReg, /*TempRegID*/2, /*TypeID*/GILLT_s32,
        GIR_MakeTempReg, /*TempRegID*/3, /*TypeID*/GILLT_s32,
        GIR_MakeTempReg, /*TempRegID*/4, /*TypeID*/GILLT_s32,
        GIR_MakeTempReg, /*TempRegID*/5, /*TypeID*/GILLT_s32,
        GIR_MakeTempReg, /*TempRegID*/6, /*TypeID*/GILLT_s16,
        GIR_MakeTempReg, /*TempRegID*/7, /*TypeID*/GILLT_s16,
        GIR_MakeTempReg, /*TempRegID*/8, /*TypeID*/GILLT_s32,
        GIR_MakeTempReg, /*TempRegID*/9, /*TypeID*/GILLT_s32,
        GIR_MakeTempReg, /*TempRegID*/10, /*TypeID*/GILLT_s32,
        GIR_MakeTempReg, /*TempRegID*/11, /*TypeID*/GILLT_s32,
        GIR_BuildMI, /*InsnID*/12, /*Opcode*/GIMT_Encode2(TargetOpcode::COPY),
        GIR_AddTempRegister, /*InsnID*/12, /*TempRegID*/11, /*TempRegFlags*/GIMT_Encode2(RegState::Define),
        GIR_CopySubReg, /*NewInsnID*/12, /*OldInsnID*/1, /*OpIdx*/1, /*SubRegIdx*/GIMT_Encode2(11), // y
        GIR_ConstrainOperandRC, /*InsnID*/12, /*Op*/0, GIMT_Encode2(AMDGPU::VGPR_32RegClassID),
        GIR_ConstrainOperandRC, /*InsnID*/12, /*Op*/1, GIMT_Encode2(AMDGPU::VReg_64RegClassID),
        GIR_BuildMI, /*InsnID*/11, /*Opcode*/GIMT_Encode2(TargetOpcode::COPY),
        GIR_AddTempRegister, /*InsnID*/11, /*TempRegID*/10, /*TempRegFlags*/GIMT_Encode2(RegState::Define),
        GIR_CopySubReg, /*NewInsnID*/11, /*OldInsnID*/2, /*OpIdx*/1, /*SubRegIdx*/GIMT_Encode2(11), // z
        GIR_ConstrainOperandRC, /*InsnID*/11, /*Op*/0, GIMT_Encode2(AMDGPU::VGPR_32RegClassID),
        GIR_ConstrainOperandRC, /*InsnID*/11, /*Op*/1, GIMT_Encode2(AMDGPU::VReg_64RegClassID),
        GIR_BuildMI, /*InsnID*/10, /*Opcode*/GIMT_Encode2(TargetOpcode::COPY),
        GIR_AddTempRegister, /*InsnID*/10, /*TempRegID*/9, /*TempRegFlags*/GIMT_Encode2(RegState::Define),
        GIR_CopySubReg, /*NewInsnID*/10, /*OldInsnID*/1, /*OpIdx*/1, /*SubRegIdx*/GIMT_Encode2(11), // y
        GIR_ConstrainOperandRC, /*InsnID*/10, /*Op*/0, GIMT_Encode2(AMDGPU::VGPR_32RegClassID),
        GIR_ConstrainOperandRC, /*InsnID*/10, /*Op*/1, GIMT_Encode2(AMDGPU::VReg_64RegClassID),
        GIR_BuildMI, /*InsnID*/9, /*Opcode*/GIMT_Encode2(TargetOpcode::COPY),
        GIR_AddTempRegister, /*InsnID*/9, /*TempRegID*/8, /*TempRegFlags*/GIMT_Encode2(RegState::Define),
        GIR_CopySubReg, /*NewInsnID*/9, /*OldInsnID*/2, /*OpIdx*/2, /*SubRegIdx*/GIMT_Encode2(11), // x
        GIR_ConstrainOperandRC, /*InsnID*/9, /*Op*/0, GIMT_Encode2(AMDGPU::VGPR_32RegClassID),
        GIR_ConstrainOperandRC, /*InsnID*/9, /*Op*/1, GIMT_Encode2(AMDGPU::VReg_64RegClassID),
        GIR_BuildMI, /*InsnID*/8, /*Opcode*/GIMT_Encode2(AMDGPU::V_XOR_B32_e64),
        GIR_AddTempRegister, /*InsnID*/8, /*TempRegID*/7, /*TempRegFlags*/GIMT_Encode2(RegState::Define),
        GIR_AddSimpleTempRegister, /*InsnID*/8, /*TempRegID*/8,
        GIR_AddSimpleTempRegister, /*InsnID*/8, /*TempRegID*/9,
        GIR_ConstrainSelectedInstOperands, /*InsnID*/8,
        GIR_BuildMI, /*InsnID*/7, /*Opcode*/GIMT_Encode2(AMDGPU::V_BFI_B32_e64),
        GIR_AddTempRegister, /*InsnID*/7, /*TempRegID*/6, /*TempRegFlags*/GIMT_Encode2(RegState::Define),
        GIR_AddSimpleTempRegister, /*InsnID*/7, /*TempRegID*/7,
        GIR_AddSimpleTempRegister, /*InsnID*/7, /*TempRegID*/10,
        GIR_AddSimpleTempRegister, /*InsnID*/7, /*TempRegID*/11,
        GIR_ConstrainSelectedInstOperands, /*InsnID*/7,
        GIR_BuildMI, /*InsnID*/6, /*Opcode*/GIMT_Encode2(TargetOpcode::COPY),
        GIR_AddTempRegister, /*InsnID*/6, /*TempRegID*/5, /*TempRegFlags*/GIMT_Encode2(RegState::Define),
        GIR_CopySubReg, /*NewInsnID*/6, /*OldInsnID*/1, /*OpIdx*/1, /*SubRegIdx*/GIMT_Encode2(3), // y
        GIR_ConstrainOperandRC, /*InsnID*/6, /*Op*/0, GIMT_Encode2(AMDGPU::VGPR_32RegClassID),
        GIR_ConstrainOperandRC, /*InsnID*/6, /*Op*/1, GIMT_Encode2(AMDGPU::VReg_64RegClassID),
        GIR_BuildMI, /*InsnID*/5, /*Opcode*/GIMT_Encode2(TargetOpcode::COPY),
        GIR_AddTempRegister, /*InsnID*/5, /*TempRegID*/4, /*TempRegFlags*/GIMT_Encode2(RegState::Define),
        GIR_CopySubReg, /*NewInsnID*/5, /*OldInsnID*/2, /*OpIdx*/1, /*SubRegIdx*/GIMT_Encode2(3), // z
        GIR_ConstrainOperandRC, /*InsnID*/5, /*Op*/0, GIMT_Encode2(AMDGPU::VGPR_32RegClassID),
        GIR_ConstrainOperandRC, /*InsnID*/5, /*Op*/1, GIMT_Encode2(AMDGPU::VReg_64RegClassID),
        GIR_BuildMI, /*InsnID*/4, /*Opcode*/GIMT_Encode2(TargetOpcode::COPY),
        GIR_AddTempRegister, /*InsnID*/4, /*TempRegID*/3, /*TempRegFlags*/GIMT_Encode2(RegState::Define),
        GIR_CopySubReg, /*NewInsnID*/4, /*OldInsnID*/1, /*OpIdx*/1, /*SubRegIdx*/GIMT_Encode2(3), // y
        GIR_ConstrainOperandRC, /*InsnID*/4, /*Op*/0, GIMT_Encode2(AMDGPU::VGPR_32RegClassID),
        GIR_ConstrainOperandRC, /*InsnID*/4, /*Op*/1, GIMT_Encode2(AMDGPU::VReg_64RegClassID),
        GIR_BuildMI, /*InsnID*/3, /*Opcode*/GIMT_Encode2(TargetOpcode::COPY),
        GIR_AddTempRegister, /*InsnID*/3, /*TempRegID*/2, /*TempRegFlags*/GIMT_Encode2(RegState::Define),
        GIR_CopySubReg, /*NewInsnID*/3, /*OldInsnID*/2, /*OpIdx*/2, /*SubRegIdx*/GIMT_Encode2(3), // x
        GIR_ConstrainOperandRC, /*InsnID*/3, /*Op*/0, GIMT_Encode2(AMDGPU::VGPR_32RegClassID),
        GIR_ConstrainOperandRC, /*InsnID*/3, /*Op*/1, GIMT_Encode2(AMDGPU::VReg_64RegClassID),
        GIR_BuildMI, /*InsnID*/2, /*Opcode*/GIMT_Encode2(AMDGPU::V_XOR_B32_e64),
        GIR_AddTempRegister, /*InsnID*/2, /*TempRegID*/1, /*TempRegFlags*/GIMT_Encode2(RegState::Define),
        GIR_AddSimpleTempRegister, /*InsnID*/2, /*TempRegID*/2,
        GIR_AddSimpleTempRegister, /*InsnID*/2, /*TempRegID*/3,
        GIR_ConstrainSelectedInstOperands, /*InsnID*/2,
        GIR_BuildMI, /*InsnID*/1, /*Opcode*/GIMT_Encode2(AMDGPU::V_BFI_B32_e64),
        GIR_AddTempRegister, /*InsnID*/1, /*TempRegID*/0, /*TempRegFlags*/GIMT_Encode2(RegState::Define),
        GIR_AddSimpleTempRegister, /*InsnID*/1, /*TempRegID*/1,
        GIR_AddSimpleTempRegister, /*InsnID*/1, /*TempRegID*/4,
        GIR_AddSimpleTempRegister, /*InsnID*/1, /*TempRegID*/5,
        GIR_ConstrainSelectedInstOperands, /*InsnID*/1,
        GIR_BuildMI, /*InsnID*/0, /*Opcode*/GIMT_Encode2(TargetOpcode::REG_SEQUENCE),
        GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/0, // DstI[dst]
        GIR_AddSimpleTempRegister, /*InsnID*/0, /*TempRegID*/0,
        GIR_AddImm8, /*InsnID*/0, /*SubRegIndex*/3,
        GIR_AddSimpleTempRegister, /*InsnID*/0, /*TempRegID*/6,
        GIR_AddImm8, /*InsnID*/0, /*SubRegIndex*/11,
        GIR_ConstrainOperandRC, /*InsnID*/0, /*Op*/0, GIMT_Encode2(AMDGPU::VReg_64RegClassID),
        GIR_ConstrainOperandRC, /*InsnID*/0, /*Op*/1, GIMT_Encode2(AMDGPU::VGPR_32RegClassID),
        GIR_ConstrainOperandRC, /*InsnID*/0, /*Op*/3, GIMT_Encode2(AMDGPU::VGPR_32RegClassID),
        GIR_EraseFromParent, /*InsnID*/0,
        // GIR_Coverage, 9934,
        GIR_Done,
      // Label 351: @29960
      GIM_Try, /*On fail goto*//*Label 352*/ GIMT_Encode4(30378), // Rule ID 9935 //
        GIM_CheckRegBankForClass, /*MI*/0, /*Op*/0, /*RC*/GIMT_Encode2(AMDGPU::VReg_64RegClassID),
        GIM_RecordInsnIgnoreCopies, /*DefineMI*/1, /*MI*/0, /*OpIdx*/1, // MIs[1]
        GIM_CheckOpcode, /*MI*/1, GIMT_Encode2(TargetOpcode::G_AND),
        GIM_CheckType, /*MI*/1, /*Op*/1, /*Type*/GILLT_s64,
        GIM_CheckType, /*MI*/1, /*Op*/2, /*Type*/GILLT_s64,
        GIM_RecordInsnIgnoreCopies, /*DefineMI*/2, /*MI*/1, /*OpIdx*/2, // MIs[2]
        GIM_CheckOpcode, /*MI*/2, GIMT_Encode2(TargetOpcode::G_OR),
        GIM_CheckType, /*MI*/2, /*Op*/1, /*Type*/GILLT_s64,
        GIM_CheckType, /*MI*/2, /*Op*/2, /*Type*/GILLT_s64,
        GIM_RecordInsnIgnoreCopies, /*DefineMI*/3, /*MI*/0, /*OpIdx*/2, // MIs[3]
        GIM_CheckOpcode, /*MI*/3, GIMT_Encode2(TargetOpcode::G_AND),
        // MIs[3] z
        GIM_CheckIsSameOperandIgnoreCopies, /*MI*/3, /*OpIdx*/1, /*OtherMI*/2, /*OtherOpIdx*/1,
        // MIs[3] x
        GIM_CheckIsSameOperandIgnoreCopies, /*MI*/3, /*OpIdx*/2, /*OtherMI*/2, /*OtherOpIdx*/2,
        GIM_CheckCxxInsnPredicate, /*MI*/0, /*FnId*/GIMT_Encode2(GICXXPred_MI_Predicate_anonymous_22557),
        GIM_CheckIsSafeToFold, /*InsnID*/1,
        GIM_CheckIsSafeToFold, /*InsnID*/2,
        GIM_CheckIsSafeToFold, /*InsnID*/3,
        // (or:{ *:[i64] } (and:{ *:[i64] } i64:{ *:[i64] }:$y, (or:{ *:[i64] } i64:{ *:[i64] }:$z, i64:{ *:[i64] }:$x)), (and:{ *:[i64] } i64:{ *:[i64] }:$z, i64:{ *:[i64] }:$x))<<P:Predicate_anonymous_22557>>  =>  (REG_SEQUENCE:{ *:[i64] } VReg_64:{ *:[i32] }, (V_BFI_B32_e64:{ *:[i16] } (V_XOR_B32_e64:{ *:[i16] } (EXTRACT_SUBREG:{ *:[i32] } VReg_64:{ *:[i64] }:$x, sub0:{ *:[i32] }), (EXTRACT_SUBREG:{ *:[i32] } VReg_64:{ *:[i64] }:$y, sub0:{ *:[i32] })), (EXTRACT_SUBREG:{ *:[i32] } VReg_64:{ *:[i64] }:$z, sub0:{ *:[i32] }), (EXTRACT_SUBREG:{ *:[i32] } VReg_64:{ *:[i64] }:$y, sub0:{ *:[i32] })), sub0:{ *:[i32] }, (V_BFI_B32_e64:{ *:[i16] } (V_XOR_B32_e64:{ *:[i16] } (EXTRACT_SUBREG:{ *:[i32] } VReg_64:{ *:[i64] }:$x, sub1:{ *:[i32] }), (EXTRACT_SUBREG:{ *:[i32] } VReg_64:{ *:[i64] }:$y, sub1:{ *:[i32] })), (EXTRACT_SUBREG:{ *:[i32] } VReg_64:{ *:[i64] }:$z, sub1:{ *:[i32] }), (EXTRACT_SUBREG:{ *:[i32] } VReg_64:{ *:[i64] }:$y, sub1:{ *:[i32] })), sub1:{ *:[i32] })
        GIR_MakeTempReg, /*TempRegID*/0, /*TypeID*/GILLT_s16,
        GIR_MakeTempReg, /*TempRegID*/1, /*TypeID*/GILLT_s16,
        GIR_MakeTempReg, /*TempRegID*/2, /*TypeID*/GILLT_s32,
        GIR_MakeTempReg, /*TempRegID*/3, /*TypeID*/GILLT_s32,
        GIR_MakeTempReg, /*TempRegID*/4, /*TypeID*/GILLT_s32,
        GIR_MakeTempReg, /*TempRegID*/5, /*TypeID*/GILLT_s32,
        GIR_MakeTempReg, /*TempRegID*/6, /*TypeID*/GILLT_s16,
        GIR_MakeTempReg, /*TempRegID*/7, /*TypeID*/GILLT_s16,
        GIR_MakeTempReg, /*TempRegID*/8, /*TypeID*/GILLT_s32,
        GIR_MakeTempReg, /*TempRegID*/9, /*TypeID*/GILLT_s32,
        GIR_MakeTempReg, /*TempRegID*/10, /*TypeID*/GILLT_s32,
        GIR_MakeTempReg, /*TempRegID*/11, /*TypeID*/GILLT_s32,
        GIR_BuildMI, /*InsnID*/12, /*Opcode*/GIMT_Encode2(TargetOpcode::COPY),
        GIR_AddTempRegister, /*InsnID*/12, /*TempRegID*/11, /*TempRegFlags*/GIMT_Encode2(RegState::Define),
        GIR_CopySubReg, /*NewInsnID*/12, /*OldInsnID*/1, /*OpIdx*/1, /*SubRegIdx*/GIMT_Encode2(11), // y
        GIR_ConstrainOperandRC, /*InsnID*/12, /*Op*/0, GIMT_Encode2(AMDGPU::VGPR_32RegClassID),
        GIR_ConstrainOperandRC, /*InsnID*/12, /*Op*/1, GIMT_Encode2(AMDGPU::VReg_64RegClassID),
        GIR_BuildMI, /*InsnID*/11, /*Opcode*/GIMT_Encode2(TargetOpcode::COPY),
        GIR_AddTempRegister, /*InsnID*/11, /*TempRegID*/10, /*TempRegFlags*/GIMT_Encode2(RegState::Define),
        GIR_CopySubReg, /*NewInsnID*/11, /*OldInsnID*/2, /*OpIdx*/1, /*SubRegIdx*/GIMT_Encode2(11), // z
        GIR_ConstrainOperandRC, /*InsnID*/11, /*Op*/0, GIMT_Encode2(AMDGPU::VGPR_32RegClassID),
        GIR_ConstrainOperandRC, /*InsnID*/11, /*Op*/1, GIMT_Encode2(AMDGPU::VReg_64RegClassID),
        GIR_BuildMI, /*InsnID*/10, /*Opcode*/GIMT_Encode2(TargetOpcode::COPY),
        GIR_AddTempRegister, /*InsnID*/10, /*TempRegID*/9, /*TempRegFlags*/GIMT_Encode2(RegState::Define),
        GIR_CopySubReg, /*NewInsnID*/10, /*OldInsnID*/1, /*OpIdx*/1, /*SubRegIdx*/GIMT_Encode2(11), // y
        GIR_ConstrainOperandRC, /*InsnID*/10, /*Op*/0, GIMT_Encode2(AMDGPU::VGPR_32RegClassID),
        GIR_ConstrainOperandRC, /*InsnID*/10, /*Op*/1, GIMT_Encode2(AMDGPU::VReg_64RegClassID),
        GIR_BuildMI, /*InsnID*/9, /*Opcode*/GIMT_Encode2(TargetOpcode::COPY),
        GIR_AddTempRegister, /*InsnID*/9, /*TempRegID*/8, /*TempRegFlags*/GIMT_Encode2(RegState::Define),
        GIR_CopySubReg, /*NewInsnID*/9, /*OldInsnID*/2, /*OpIdx*/2, /*SubRegIdx*/GIMT_Encode2(11), // x
        GIR_ConstrainOperandRC, /*InsnID*/9, /*Op*/0, GIMT_Encode2(AMDGPU::VGPR_32RegClassID),
        GIR_ConstrainOperandRC, /*InsnID*/9, /*Op*/1, GIMT_Encode2(AMDGPU::VReg_64RegClassID),
        GIR_BuildMI, /*InsnID*/8, /*Opcode*/GIMT_Encode2(AMDGPU::V_XOR_B32_e64),
        GIR_AddTempRegister, /*InsnID*/8, /*TempRegID*/7, /*TempRegFlags*/GIMT_Encode2(RegState::Define),
        GIR_AddSimpleTempRegister, /*InsnID*/8, /*TempRegID*/8,
        GIR_AddSimpleTempRegister, /*InsnID*/8, /*TempRegID*/9,
        GIR_ConstrainSelectedInstOperands, /*InsnID*/8,
        GIR_BuildMI, /*InsnID*/7, /*Opcode*/GIMT_Encode2(AMDGPU::V_BFI_B32_e64),
        GIR_AddTempRegister, /*InsnID*/7, /*TempRegID*/6, /*TempRegFlags*/GIMT_Encode2(RegState::Define),
        GIR_AddSimpleTempRegister, /*InsnID*/7, /*TempRegID*/7,
        GIR_AddSimpleTempRegister, /*InsnID*/7, /*TempRegID*/10,
        GIR_AddSimpleTempRegister, /*InsnID*/7, /*TempRegID*/11,
        GIR_ConstrainSelectedInstOperands, /*InsnID*/7,
        GIR_BuildMI, /*InsnID*/6, /*Opcode*/GIMT_Encode2(TargetOpcode::COPY),
        GIR_AddTempRegister, /*InsnID*/6, /*TempRegID*/5, /*TempRegFlags*/GIMT_Encode2(RegState::Define),
        GIR_CopySubReg, /*NewInsnID*/6, /*OldInsnID*/1, /*OpIdx*/1, /*SubRegIdx*/GIMT_Encode2(3), // y
        GIR_ConstrainOperandRC, /*InsnID*/6, /*Op*/0, GIMT_Encode2(AMDGPU::VGPR_32RegClassID),
        GIR_ConstrainOperandRC, /*InsnID*/6, /*Op*/1, GIMT_Encode2(AMDGPU::VReg_64RegClassID),
        GIR_BuildMI, /*InsnID*/5, /*Opcode*/GIMT_Encode2(TargetOpcode::COPY),
        GIR_AddTempRegister, /*InsnID*/5, /*TempRegID*/4, /*TempRegFlags*/GIMT_Encode2(RegState::Define),
        GIR_CopySubReg, /*NewInsnID*/5, /*OldInsnID*/2, /*OpIdx*/1, /*SubRegIdx*/GIMT_Encode2(3), // z
        GIR_ConstrainOperandRC, /*InsnID*/5, /*Op*/0, GIMT_Encode2(AMDGPU::VGPR_32RegClassID),
        GIR_ConstrainOperandRC, /*InsnID*/5, /*Op*/1, GIMT_Encode2(AMDGPU::VReg_64RegClassID),
        GIR_BuildMI, /*InsnID*/4, /*Opcode*/GIMT_Encode2(TargetOpcode::COPY),
        GIR_AddTempRegister, /*InsnID*/4, /*TempRegID*/3, /*TempRegFlags*/GIMT_Encode2(RegState::Define),
        GIR_CopySubReg, /*NewInsnID*/4, /*OldInsnID*/1, /*OpIdx*/1, /*SubRegIdx*/GIMT_Encode2(3), // y
        GIR_ConstrainOperandRC, /*InsnID*/4, /*Op*/0, GIMT_Encode2(AMDGPU::VGPR_32RegClassID),
        GIR_ConstrainOperandRC, /*InsnID*/4, /*Op*/1, GIMT_Encode2(AMDGPU::VReg_64RegClassID),
        GIR_BuildMI, /*InsnID*/3, /*Opcode*/GIMT_Encode2(TargetOpcode::COPY),
        GIR_AddTempRegister, /*InsnID*/3, /*TempRegID*/2, /*TempRegFlags*/GIMT_Encode2(RegState::Define),
        GIR_CopySubReg, /*NewInsnID*/3, /*OldInsnID*/2, /*OpIdx*/2, /*SubRegIdx*/GIMT_Encode2(3), // x
        GIR_ConstrainOperandRC, /*InsnID*/3, /*Op*/0, GIMT_Encode2(AMDGPU::VGPR_32RegClassID),
        GIR_ConstrainOperandRC, /*InsnID*/3, /*Op*/1, GIMT_Encode2(AMDGPU::VReg_64RegClassID),
        GIR_BuildMI, /*InsnID*/2, /*Opcode*/GIMT_Encode2(AMDGPU::V_XOR_B32_e64),
        GIR_AddTempRegister, /*InsnID*/2, /*TempRegID*/1, /*TempRegFlags*/GIMT_Encode2(RegState::Define),
        GIR_AddSimpleTempRegister, /*InsnID*/2, /*TempRegID*/2,
        GIR_AddSimpleTempRegister, /*InsnID*/2, /*TempRegID*/3,
        GIR_ConstrainSelectedInstOperands, /*InsnID*/2,
        GIR_BuildMI, /*InsnID*/1, /*Opcode*/GIMT_Encode2(AMDGPU::V_BFI_B32_e64),
        GIR_AddTempRegister, /*InsnID*/1, /*TempRegID*/0, /*TempRegFlags*/GIMT_Encode2(RegState::Define),
        GIR_AddSimpleTempRegister, /*InsnID*/1, /*TempRegID*/1,
        GIR_AddSimpleTempRegister, /*InsnID*/1, /*TempRegID*/4,
        GIR_AddSimpleTempRegister, /*InsnID*/1, /*TempRegID*/5,
        GIR_ConstrainSelectedInstOperands, /*InsnID*/1,
        GIR_BuildMI, /*InsnID*/0, /*Opcode*/GIMT_Encode2(TargetOpcode::REG_SEQUENCE),
        GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/0, // DstI[dst]
        GIR_AddSimpleTempRegister, /*InsnID*/0, /*TempRegID*/0,
        GIR_AddImm8, /*InsnID*/0, /*SubRegIndex*/3,
        GIR_AddSimpleTempRegister, /*InsnID*/0, /*TempRegID*/6,
        GIR_AddImm8, /*InsnID*/0, /*SubRegIndex*/11,
        GIR_ConstrainOperandRC, /*InsnID*/0, /*Op*/0, GIMT_Encode2(AMDGPU::VReg_64RegClassID),
        GIR_ConstrainOperandRC, /*InsnID*/0, /*Op*/1, GIMT_Encode2(AMDGPU::VGPR_32RegClassID),
        GIR_ConstrainOperandRC, /*InsnID*/0, /*Op*/3, GIMT_Encode2(AMDGPU::VGPR_32RegClassID),
        GIR_EraseFromParent, /*InsnID*/0,
        // GIR_Coverage, 9935,
        GIR_Done,
      // Label 352: @30378
      GIM_Try, /*On fail goto*//*Label 353*/ GIMT_Encode4(30796), // Rule ID 9926 //
        GIM_CheckRegBankForClass, /*MI*/0, /*Op*/0, /*RC*/GIMT_Encode2(AMDGPU::VReg_64RegClassID),
        GIM_RecordInsnIgnoreCopies, /*DefineMI*/1, /*MI*/0, /*OpIdx*/1, // MIs[1]
        GIM_CheckOpcode, /*MI*/1, GIMT_Encode2(TargetOpcode::G_AND),
        GIM_CheckType, /*MI*/1, /*Op*/1, /*Type*/GILLT_s64,
        GIM_CheckType, /*MI*/1, /*Op*/2, /*Type*/GILLT_s64,
        GIM_RecordInsnIgnoreCopies, /*DefineMI*/2, /*MI*/0, /*OpIdx*/2, // MIs[2]
        GIM_CheckOpcode, /*MI*/2, GIMT_Encode2(TargetOpcode::G_AND),
        GIM_CheckType, /*MI*/2, /*Op*/1, /*Type*/GILLT_s64,
        GIM_CheckType, /*MI*/2, /*Op*/2, /*Type*/GILLT_s64,
        GIM_RecordInsnIgnoreCopies, /*DefineMI*/3, /*MI*/2, /*OpIdx*/1, // MIs[3]
        GIM_CheckOpcode, /*MI*/3, GIMT_Encode2(TargetOpcode::G_OR),
        // MIs[3] x
        GIM_CheckIsSameOperandIgnoreCopies, /*MI*/3, /*OpIdx*/1, /*OtherMI*/1, /*OtherOpIdx*/1,
        // MIs[3] z
        GIM_CheckIsSameOperandIgnoreCopies, /*MI*/3, /*OpIdx*/2, /*OtherMI*/1, /*OtherOpIdx*/2,
        GIM_CheckCxxInsnPredicate, /*MI*/0, /*FnId*/GIMT_Encode2(GICXXPred_MI_Predicate_anonymous_22557),
        GIM_CheckIsSafeToFold, /*InsnID*/1,
        GIM_CheckIsSafeToFold, /*InsnID*/2,
        GIM_CheckIsSafeToFold, /*InsnID*/3,
        // (or:{ *:[i64] } (and:{ *:[i64] } i64:{ *:[i64] }:$x, i64:{ *:[i64] }:$z), (and:{ *:[i64] } (or:{ *:[i64] } i64:{ *:[i64] }:$x, i64:{ *:[i64] }:$z), i64:{ *:[i64] }:$y))<<P:Predicate_anonymous_22557>>  =>  (REG_SEQUENCE:{ *:[i64] } VReg_64:{ *:[i32] }, (V_BFI_B32_e64:{ *:[i16] } (V_XOR_B32_e64:{ *:[i16] } (EXTRACT_SUBREG:{ *:[i32] } VReg_64:{ *:[i64] }:$x, sub0:{ *:[i32] }), (EXTRACT_SUBREG:{ *:[i32] } VReg_64:{ *:[i64] }:$y, sub0:{ *:[i32] })), (EXTRACT_SUBREG:{ *:[i32] } VReg_64:{ *:[i64] }:$z, sub0:{ *:[i32] }), (EXTRACT_SUBREG:{ *:[i32] } VReg_64:{ *:[i64] }:$y, sub0:{ *:[i32] })), sub0:{ *:[i32] }, (V_BFI_B32_e64:{ *:[i16] } (V_XOR_B32_e64:{ *:[i16] } (EXTRACT_SUBREG:{ *:[i32] } VReg_64:{ *:[i64] }:$x, sub1:{ *:[i32] }), (EXTRACT_SUBREG:{ *:[i32] } VReg_64:{ *:[i64] }:$y, sub1:{ *:[i32] })), (EXTRACT_SUBREG:{ *:[i32] } VReg_64:{ *:[i64] }:$z, sub1:{ *:[i32] }), (EXTRACT_SUBREG:{ *:[i32] } VReg_64:{ *:[i64] }:$y, sub1:{ *:[i32] })), sub1:{ *:[i32] })
        GIR_MakeTempReg, /*TempRegID*/0, /*TypeID*/GILLT_s16,
        GIR_MakeTempReg, /*TempRegID*/1, /*TypeID*/GILLT_s16,
        GIR_MakeTempReg, /*TempRegID*/2, /*TypeID*/GILLT_s32,
        GIR_MakeTempReg, /*TempRegID*/3, /*TypeID*/GILLT_s32,
        GIR_MakeTempReg, /*TempRegID*/4, /*TypeID*/GILLT_s32,
        GIR_MakeTempReg, /*TempRegID*/5, /*TypeID*/GILLT_s32,
        GIR_MakeTempReg, /*TempRegID*/6, /*TypeID*/GILLT_s16,
        GIR_MakeTempReg, /*TempRegID*/7, /*TypeID*/GILLT_s16,
        GIR_MakeTempReg, /*TempRegID*/8, /*TypeID*/GILLT_s32,
        GIR_MakeTempReg, /*TempRegID*/9, /*TypeID*/GILLT_s32,
        GIR_MakeTempReg, /*TempRegID*/10, /*TypeID*/GILLT_s32,
        GIR_MakeTempReg, /*TempRegID*/11, /*TypeID*/GILLT_s32,
        GIR_BuildMI, /*InsnID*/12, /*Opcode*/GIMT_Encode2(TargetOpcode::COPY),
        GIR_AddTempRegister, /*InsnID*/12, /*TempRegID*/11, /*TempRegFlags*/GIMT_Encode2(RegState::Define),
        GIR_CopySubReg, /*NewInsnID*/12, /*OldInsnID*/2, /*OpIdx*/2, /*SubRegIdx*/GIMT_Encode2(11), // y
        GIR_ConstrainOperandRC, /*InsnID*/12, /*Op*/0, GIMT_Encode2(AMDGPU::VGPR_32RegClassID),
        GIR_ConstrainOperandRC, /*InsnID*/12, /*Op*/1, GIMT_Encode2(AMDGPU::VReg_64RegClassID),
        GIR_BuildMI, /*InsnID*/11, /*Opcode*/GIMT_Encode2(TargetOpcode::COPY),
        GIR_AddTempRegister, /*InsnID*/11, /*TempRegID*/10, /*TempRegFlags*/GIMT_Encode2(RegState::Define),
        GIR_CopySubReg, /*NewInsnID*/11, /*OldInsnID*/1, /*OpIdx*/2, /*SubRegIdx*/GIMT_Encode2(11), // z
        GIR_ConstrainOperandRC, /*InsnID*/11, /*Op*/0, GIMT_Encode2(AMDGPU::VGPR_32RegClassID),
        GIR_ConstrainOperandRC, /*InsnID*/11, /*Op*/1, GIMT_Encode2(AMDGPU::VReg_64RegClassID),
        GIR_BuildMI, /*InsnID*/10, /*Opcode*/GIMT_Encode2(TargetOpcode::COPY),
        GIR_AddTempRegister, /*InsnID*/10, /*TempRegID*/9, /*TempRegFlags*/GIMT_Encode2(RegState::Define),
        GIR_CopySubReg, /*NewInsnID*/10, /*OldInsnID*/2, /*OpIdx*/2, /*SubRegIdx*/GIMT_Encode2(11), // y
        GIR_ConstrainOperandRC, /*InsnID*/10, /*Op*/0, GIMT_Encode2(AMDGPU::VGPR_32RegClassID),
        GIR_ConstrainOperandRC, /*InsnID*/10, /*Op*/1, GIMT_Encode2(AMDGPU::VReg_64RegClassID),
        GIR_BuildMI, /*InsnID*/9, /*Opcode*/GIMT_Encode2(TargetOpcode::COPY),
        GIR_AddTempRegister, /*InsnID*/9, /*TempRegID*/8, /*TempRegFlags*/GIMT_Encode2(RegState::Define),
        GIR_CopySubReg, /*NewInsnID*/9, /*OldInsnID*/1, /*OpIdx*/1, /*SubRegIdx*/GIMT_Encode2(11), // x
        GIR_ConstrainOperandRC, /*InsnID*/9, /*Op*/0, GIMT_Encode2(AMDGPU::VGPR_32RegClassID),
        GIR_ConstrainOperandRC, /*InsnID*/9, /*Op*/1, GIMT_Encode2(AMDGPU::VReg_64RegClassID),
        GIR_BuildMI, /*InsnID*/8, /*Opcode*/GIMT_Encode2(AMDGPU::V_XOR_B32_e64),
        GIR_AddTempRegister, /*InsnID*/8, /*TempRegID*/7, /*TempRegFlags*/GIMT_Encode2(RegState::Define),
        GIR_AddSimpleTempRegister, /*InsnID*/8, /*TempRegID*/8,
        GIR_AddSimpleTempRegister, /*InsnID*/8, /*TempRegID*/9,
        GIR_ConstrainSelectedInstOperands, /*InsnID*/8,
        GIR_BuildMI, /*InsnID*/7, /*Opcode*/GIMT_Encode2(AMDGPU::V_BFI_B32_e64),
        GIR_AddTempRegister, /*InsnID*/7, /*TempRegID*/6, /*TempRegFlags*/GIMT_Encode2(RegState::Define),
        GIR_AddSimpleTempRegister, /*InsnID*/7, /*TempRegID*/7,
        GIR_AddSimpleTempRegister, /*InsnID*/7, /*TempRegID*/10,
        GIR_AddSimpleTempRegister, /*InsnID*/7, /*TempRegID*/11,
        GIR_ConstrainSelectedInstOperands, /*InsnID*/7,
        GIR_BuildMI, /*InsnID*/6, /*Opcode*/GIMT_Encode2(TargetOpcode::COPY),
        GIR_AddTempRegister, /*InsnID*/6, /*TempRegID*/5, /*TempRegFlags*/GIMT_Encode2(RegState::Define),
        GIR_CopySubReg, /*NewInsnID*/6, /*OldInsnID*/2, /*OpIdx*/2, /*SubRegIdx*/GIMT_Encode2(3), // y
        GIR_ConstrainOperandRC, /*InsnID*/6, /*Op*/0, GIMT_Encode2(AMDGPU::VGPR_32RegClassID),
        GIR_ConstrainOperandRC, /*InsnID*/6, /*Op*/1, GIMT_Encode2(AMDGPU::VReg_64RegClassID),
        GIR_BuildMI, /*InsnID*/5, /*Opcode*/GIMT_Encode2(TargetOpcode::COPY),
        GIR_AddTempRegister, /*InsnID*/5, /*TempRegID*/4, /*TempRegFlags*/GIMT_Encode2(RegState::Define),
        GIR_CopySubReg, /*NewInsnID*/5, /*OldInsnID*/1, /*OpIdx*/2, /*SubRegIdx*/GIMT_Encode2(3), // z
        GIR_ConstrainOperandRC, /*InsnID*/5, /*Op*/0, GIMT_Encode2(AMDGPU::VGPR_32RegClassID),
        GIR_ConstrainOperandRC, /*InsnID*/5, /*Op*/1, GIMT_Encode2(AMDGPU::VReg_64RegClassID),
        GIR_BuildMI, /*InsnID*/4, /*Opcode*/GIMT_Encode2(TargetOpcode::COPY),
        GIR_AddTempRegister, /*InsnID*/4, /*TempRegID*/3, /*TempRegFlags*/GIMT_Encode2(RegState::Define),
        GIR_CopySubReg, /*NewInsnID*/4, /*OldInsnID*/2, /*OpIdx*/2, /*SubRegIdx*/GIMT_Encode2(3), // y
        GIR_ConstrainOperandRC, /*InsnID*/4, /*Op*/0, GIMT_Encode2(AMDGPU::VGPR_32RegClassID),
        GIR_ConstrainOperandRC, /*InsnID*/4, /*Op*/1, GIMT_Encode2(AMDGPU::VReg_64RegClassID),
        GIR_BuildMI, /*InsnID*/3, /*Opcode*/GIMT_Encode2(TargetOpcode::COPY),
        GIR_AddTempRegister, /*InsnID*/3, /*TempRegID*/2, /*TempRegFlags*/GIMT_Encode2(RegState::Define),
        GIR_CopySubReg, /*NewInsnID*/3, /*OldInsnID*/1, /*OpIdx*/1, /*SubRegIdx*/GIMT_Encode2(3), // x
        GIR_ConstrainOperandRC, /*InsnID*/3, /*Op*/0, GIMT_Encode2(AMDGPU::VGPR_32RegClassID),
        GIR_ConstrainOperandRC, /*InsnID*/3, /*Op*/1, GIMT_Encode2(AMDGPU::VReg_64RegClassID),
        GIR_BuildMI, /*InsnID*/2, /*Opcode*/GIMT_Encode2(AMDGPU::V_XOR_B32_e64),
        GIR_AddTempRegister, /*InsnID*/2, /*TempRegID*/1, /*TempRegFlags*/GIMT_Encode2(RegState::Define),
        GIR_AddSimpleTempRegister, /*InsnID*/2, /*TempRegID*/2,
        GIR_AddSimpleTempRegister, /*InsnID*/2, /*TempRegID*/3,
        GIR_ConstrainSelectedInstOperands, /*InsnID*/2,
        GIR_BuildMI, /*InsnID*/1, /*Opcode*/GIMT_Encode2(AMDGPU::V_BFI_B32_e64),
        GIR_AddTempRegister, /*InsnID*/1, /*TempRegID*/0, /*TempRegFlags*/GIMT_Encode2(RegState::Define),
        GIR_AddSimpleTempRegister, /*InsnID*/1, /*TempRegID*/1,
        GIR_AddSimpleTempRegister, /*InsnID*/1, /*TempRegID*/4,
        GIR_AddSimpleTempRegister, /*InsnID*/1, /*TempRegID*/5,
        GIR_ConstrainSelectedInstOperands, /*InsnID*/1,
        GIR_BuildMI, /*InsnID*/0, /*Opcode*/GIMT_Encode2(TargetOpcode::REG_SEQUENCE),
        GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/0, // DstI[dst]
        GIR_AddSimpleTempRegister, /*InsnID*/0, /*TempRegID*/0,
        GIR_AddImm8, /*InsnID*/0, /*SubRegIndex*/3,
        GIR_AddSimpleTempRegister, /*InsnID*/0, /*TempRegID*/6,
        GIR_AddImm8, /*InsnID*/0, /*SubRegIndex*/11,
        GIR_ConstrainOperandRC, /*InsnID*/0, /*Op*/0, GIMT_Encode2(AMDGPU::VReg_64RegClassID),
        GIR_ConstrainOperandRC, /*InsnID*/0, /*Op*/1, GIMT_Encode2(AMDGPU::VGPR_32RegClassID),
        GIR_ConstrainOperandRC, /*InsnID*/0, /*Op*/3, GIMT_Encode2(AMDGPU::VGPR_32RegClassID),
        GIR_EraseFromParent, /*InsnID*/0,
        // GIR_Coverage, 9926,
        GIR_Done,
      // Label 353: @30796
      GIM_Try, /*On fail goto*//*Label 354*/ GIMT_Encode4(31214), // Rule ID 9927 //
        GIM_CheckRegBankForClass, /*MI*/0, /*Op*/0, /*RC*/GIMT_Encode2(AMDGPU::VReg_64RegClassID),
        GIM_RecordInsnIgnoreCopies, /*DefineMI*/1, /*MI*/0, /*OpIdx*/1, // MIs[1]
        GIM_CheckOpcode, /*MI*/1, GIMT_Encode2(TargetOpcode::G_AND),
        GIM_CheckType, /*MI*/1, /*Op*/1, /*Type*/GILLT_s64,
        GIM_CheckType, /*MI*/1, /*Op*/2, /*Type*/GILLT_s64,
        GIM_RecordInsnIgnoreCopies, /*DefineMI*/2, /*MI*/0, /*OpIdx*/2, // MIs[2]
        GIM_CheckOpcode, /*MI*/2, GIMT_Encode2(TargetOpcode::G_AND),
        GIM_CheckType, /*MI*/2, /*Op*/1, /*Type*/GILLT_s64,
        GIM_CheckType, /*MI*/2, /*Op*/2, /*Type*/GILLT_s64,
        GIM_RecordInsnIgnoreCopies, /*DefineMI*/3, /*MI*/2, /*OpIdx*/1, // MIs[3]
        GIM_CheckOpcode, /*MI*/3, GIMT_Encode2(TargetOpcode::G_OR),
        // MIs[3] z
        GIM_CheckIsSameOperandIgnoreCopies, /*MI*/3, /*OpIdx*/1, /*OtherMI*/1, /*OtherOpIdx*/2,
        // MIs[3] x
        GIM_CheckIsSameOperandIgnoreCopies, /*MI*/3, /*OpIdx*/2, /*OtherMI*/1, /*OtherOpIdx*/1,
        GIM_CheckCxxInsnPredicate, /*MI*/0, /*FnId*/GIMT_Encode2(GICXXPred_MI_Predicate_anonymous_22557),
        GIM_CheckIsSafeToFold, /*InsnID*/1,
        GIM_CheckIsSafeToFold, /*InsnID*/2,
        GIM_CheckIsSafeToFold, /*InsnID*/3,
        // (or:{ *:[i64] } (and:{ *:[i64] } i64:{ *:[i64] }:$x, i64:{ *:[i64] }:$z), (and:{ *:[i64] } (or:{ *:[i64] } i64:{ *:[i64] }:$z, i64:{ *:[i64] }:$x), i64:{ *:[i64] }:$y))<<P:Predicate_anonymous_22557>>  =>  (REG_SEQUENCE:{ *:[i64] } VReg_64:{ *:[i32] }, (V_BFI_B32_e64:{ *:[i16] } (V_XOR_B32_e64:{ *:[i16] } (EXTRACT_SUBREG:{ *:[i32] } VReg_64:{ *:[i64] }:$x, sub0:{ *:[i32] }), (EXTRACT_SUBREG:{ *:[i32] } VReg_64:{ *:[i64] }:$y, sub0:{ *:[i32] })), (EXTRACT_SUBREG:{ *:[i32] } VReg_64:{ *:[i64] }:$z, sub0:{ *:[i32] }), (EXTRACT_SUBREG:{ *:[i32] } VReg_64:{ *:[i64] }:$y, sub0:{ *:[i32] })), sub0:{ *:[i32] }, (V_BFI_B32_e64:{ *:[i16] } (V_XOR_B32_e64:{ *:[i16] } (EXTRACT_SUBREG:{ *:[i32] } VReg_64:{ *:[i64] }:$x, sub1:{ *:[i32] }), (EXTRACT_SUBREG:{ *:[i32] } VReg_64:{ *:[i64] }:$y, sub1:{ *:[i32] })), (EXTRACT_SUBREG:{ *:[i32] } VReg_64:{ *:[i64] }:$z, sub1:{ *:[i32] }), (EXTRACT_SUBREG:{ *:[i32] } VReg_64:{ *:[i64] }:$y, sub1:{ *:[i32] })), sub1:{ *:[i32] })
        GIR_MakeTempReg, /*TempRegID*/0, /*TypeID*/GILLT_s16,
        GIR_MakeTempReg, /*TempRegID*/1, /*TypeID*/GILLT_s16,
        GIR_MakeTempReg, /*TempRegID*/2, /*TypeID*/GILLT_s32,
        GIR_MakeTempReg, /*TempRegID*/3, /*TypeID*/GILLT_s32,
        GIR_MakeTempReg, /*TempRegID*/4, /*TypeID*/GILLT_s32,
        GIR_MakeTempReg, /*TempRegID*/5, /*TypeID*/GILLT_s32,
        GIR_MakeTempReg, /*TempRegID*/6, /*TypeID*/GILLT_s16,
        GIR_MakeTempReg, /*TempRegID*/7, /*TypeID*/GILLT_s16,
        GIR_MakeTempReg, /*TempRegID*/8, /*TypeID*/GILLT_s32,
        GIR_MakeTempReg, /*TempRegID*/9, /*TypeID*/GILLT_s32,
        GIR_MakeTempReg, /*TempRegID*/10, /*TypeID*/GILLT_s32,
        GIR_MakeTempReg, /*TempRegID*/11, /*TypeID*/GILLT_s32,
        GIR_BuildMI, /*InsnID*/12, /*Opcode*/GIMT_Encode2(TargetOpcode::COPY),
        GIR_AddTempRegister, /*InsnID*/12, /*TempRegID*/11, /*TempRegFlags*/GIMT_Encode2(RegState::Define),
        GIR_CopySubReg, /*NewInsnID*/12, /*OldInsnID*/2, /*OpIdx*/2, /*SubRegIdx*/GIMT_Encode2(11), // y
        GIR_ConstrainOperandRC, /*InsnID*/12, /*Op*/0, GIMT_Encode2(AMDGPU::VGPR_32RegClassID),
        GIR_ConstrainOperandRC, /*InsnID*/12, /*Op*/1, GIMT_Encode2(AMDGPU::VReg_64RegClassID),
        GIR_BuildMI, /*InsnID*/11, /*Opcode*/GIMT_Encode2(TargetOpcode::COPY),
        GIR_AddTempRegister, /*InsnID*/11, /*TempRegID*/10, /*TempRegFlags*/GIMT_Encode2(RegState::Define),
        GIR_CopySubReg, /*NewInsnID*/11, /*OldInsnID*/1, /*OpIdx*/2, /*SubRegIdx*/GIMT_Encode2(11), // z
        GIR_ConstrainOperandRC, /*InsnID*/11, /*Op*/0, GIMT_Encode2(AMDGPU::VGPR_32RegClassID),
        GIR_ConstrainOperandRC, /*InsnID*/11, /*Op*/1, GIMT_Encode2(AMDGPU::VReg_64RegClassID),
        GIR_BuildMI, /*InsnID*/10, /*Opcode*/GIMT_Encode2(TargetOpcode::COPY),
        GIR_AddTempRegister, /*InsnID*/10, /*TempRegID*/9, /*TempRegFlags*/GIMT_Encode2(RegState::Define),
        GIR_CopySubReg, /*NewInsnID*/10, /*OldInsnID*/2, /*OpIdx*/2, /*SubRegIdx*/GIMT_Encode2(11), // y
        GIR_ConstrainOperandRC, /*InsnID*/10, /*Op*/0, GIMT_Encode2(AMDGPU::VGPR_32RegClassID),
        GIR_ConstrainOperandRC, /*InsnID*/10, /*Op*/1, GIMT_Encode2(AMDGPU::VReg_64RegClassID),
        GIR_BuildMI, /*InsnID*/9, /*Opcode*/GIMT_Encode2(TargetOpcode::COPY),
        GIR_AddTempRegister, /*InsnID*/9, /*TempRegID*/8, /*TempRegFlags*/GIMT_Encode2(RegState::Define),
        GIR_CopySubReg, /*NewInsnID*/9, /*OldInsnID*/1, /*OpIdx*/1, /*SubRegIdx*/GIMT_Encode2(11), // x
        GIR_ConstrainOperandRC, /*InsnID*/9, /*Op*/0, GIMT_Encode2(AMDGPU::VGPR_32RegClassID),
        GIR_ConstrainOperandRC, /*InsnID*/9, /*Op*/1, GIMT_Encode2(AMDGPU::VReg_64RegClassID),
        GIR_BuildMI, /*InsnID*/8, /*Opcode*/GIMT_Encode2(AMDGPU::V_XOR_B32_e64),
        GIR_AddTempRegister, /*InsnID*/8, /*TempRegID*/7, /*TempRegFlags*/GIMT_Encode2(RegState::Define),
        GIR_AddSimpleTempRegister, /*InsnID*/8, /*TempRegID*/8,
        GIR_AddSimpleTempRegister, /*InsnID*/8, /*TempRegID*/9,
        GIR_ConstrainSelectedInstOperands, /*InsnID*/8,
        GIR_BuildMI, /*InsnID*/7, /*Opcode*/GIMT_Encode2(AMDGPU::V_BFI_B32_e64),
        GIR_AddTempRegister, /*InsnID*/7, /*TempRegID*/6, /*TempRegFlags*/GIMT_Encode2(RegState::Define),
        GIR_AddSimpleTempRegister, /*InsnID*/7, /*TempRegID*/7,
        GIR_AddSimpleTempRegister, /*InsnID*/7, /*TempRegID*/10,
        GIR_AddSimpleTempRegister, /*InsnID*/7, /*TempRegID*/11,
        GIR_ConstrainSelectedInstOperands, /*InsnID*/7,
        GIR_BuildMI, /*InsnID*/6, /*Opcode*/GIMT_Encode2(TargetOpcode::COPY),
        GIR_AddTempRegister, /*InsnID*/6, /*TempRegID*/5, /*TempRegFlags*/GIMT_Encode2(RegState::Define),
        GIR_CopySubReg, /*NewInsnID*/6, /*OldInsnID*/2, /*OpIdx*/2, /*SubRegIdx*/GIMT_Encode2(3), // y
        GIR_ConstrainOperandRC, /*InsnID*/6, /*Op*/0, GIMT_Encode2(AMDGPU::VGPR_32RegClassID),
        GIR_ConstrainOperandRC, /*InsnID*/6, /*Op*/1, GIMT_Encode2(AMDGPU::VReg_64RegClassID),
        GIR_BuildMI, /*InsnID*/5, /*Opcode*/GIMT_Encode2(TargetOpcode::COPY),
        GIR_AddTempRegister, /*InsnID*/5, /*TempRegID*/4, /*TempRegFlags*/GIMT_Encode2(RegState::Define),
        GIR_CopySubReg, /*NewInsnID*/5, /*OldInsnID*/1, /*OpIdx*/2, /*SubRegIdx*/GIMT_Encode2(3), // z
        GIR_ConstrainOperandRC, /*InsnID*/5, /*Op*/0, GIMT_Encode2(AMDGPU::VGPR_32RegClassID),
        GIR_ConstrainOperandRC, /*InsnID*/5, /*Op*/1, GIMT_Encode2(AMDGPU::VReg_64RegClassID),
        GIR_BuildMI, /*InsnID*/4, /*Opcode*/GIMT_Encode2(TargetOpcode::COPY),
        GIR_AddTempRegister, /*InsnID*/4, /*TempRegID*/3, /*TempRegFlags*/GIMT_Encode2(RegState::Define),
        GIR_CopySubReg, /*NewInsnID*/4, /*OldInsnID*/2, /*OpIdx*/2, /*SubRegIdx*/GIMT_Encode2(3), // y
        GIR_ConstrainOperandRC, /*InsnID*/4, /*Op*/0, GIMT_Encode2(AMDGPU::VGPR_32RegClassID),
        GIR_ConstrainOperandRC, /*InsnID*/4, /*Op*/1, GIMT_Encode2(AMDGPU::VReg_64RegClassID),
        GIR_BuildMI, /*InsnID*/3, /*Opcode*/GIMT_Encode2(TargetOpcode::COPY),
        GIR_AddTempRegister, /*InsnID*/3, /*TempRegID*/2, /*TempRegFlags*/GIMT_Encode2(RegState::Define),
        GIR_CopySubReg, /*NewInsnID*/3, /*OldInsnID*/1, /*OpIdx*/1, /*SubRegIdx*/GIMT_Encode2(3), // x
        GIR_ConstrainOperandRC, /*InsnID*/3, /*Op*/0, GIMT_Encode2(AMDGPU::VGPR_32RegClassID),
        GIR_ConstrainOperandRC, /*InsnID*/3, /*Op*/1, GIMT_Encode2(AMDGPU::VReg_64RegClassID),
        GIR_BuildMI, /*InsnID*/2, /*Opcode*/GIMT_Encode2(AMDGPU::V_XOR_B32_e64),
        GIR_AddTempRegister, /*InsnID*/2, /*TempRegID*/1, /*TempRegFlags*/GIMT_Encode2(RegState::Define),
        GIR_AddSimpleTempRegister, /*InsnID*/2, /*TempRegID*/2,
        GIR_AddSimpleTempRegister, /*InsnID*/2, /*TempRegID*/3,
        GIR_ConstrainSelectedInstOperands, /*InsnID*/2,
        GIR_BuildMI, /*InsnID*/1, /*Opcode*/GIMT_Encode2(AMDGPU::V_BFI_B32_e64),
        GIR_AddTempRegister, /*InsnID*/1, /*TempRegID*/0, /*TempRegFlags*/GIMT_Encode2(RegState::Define),
        GIR_AddSimpleTempRegister, /*InsnID*/1, /*TempRegID*/1,
        GIR_AddSimpleTempRegister, /*InsnID*/1, /*TempRegID*/4,
        GIR_AddSimpleTempRegister, /*InsnID*/1, /*TempRegID*/5,
        GIR_ConstrainSelectedInstOperands, /*InsnID*/1,
        GIR_BuildMI, /*InsnID*/0, /*Opcode*/GIMT_Encode2(TargetOpcode::REG_SEQUENCE),
        GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/0, // DstI[dst]
        GIR_AddSimpleTempRegister, /*InsnID*/0, /*TempRegID*/0,
        GIR_AddImm8, /*InsnID*/0, /*SubRegIndex*/3,
        GIR_AddSimpleTempRegister, /*InsnID*/0, /*TempRegID*/6,
        GIR_AddImm8, /*InsnID*/0, /*SubRegIndex*/11,
        GIR_ConstrainOperandRC, /*InsnID*/0, /*Op*/0, GIMT_Encode2(AMDGPU::VReg_64RegClassID),
        GIR_ConstrainOperandRC, /*InsnID*/0, /*Op*/1, GIMT_Encode2(AMDGPU::VGPR_32RegClassID),
        GIR_ConstrainOperandRC, /*InsnID*/0, /*Op*/3, GIMT_Encode2(AMDGPU::VGPR_32RegClassID),
        GIR_EraseFromParent, /*InsnID*/0,
        // GIR_Coverage, 9927,
        GIR_Done,
      // Label 354: @31214
      GIM_Try, /*On fail goto*//*Label 355*/ GIMT_Encode4(31632), // Rule ID 9930 //
        GIM_CheckRegBankForClass, /*MI*/0, /*Op*/0, /*RC*/GIMT_Encode2(AMDGPU::VReg_64RegClassID),
        GIM_RecordInsnIgnoreCopies, /*DefineMI*/1, /*MI*/0, /*OpIdx*/1, // MIs[1]
        GIM_CheckOpcode, /*MI*/1, GIMT_Encode2(TargetOpcode::G_AND),
        GIM_CheckType, /*MI*/1, /*Op*/1, /*Type*/GILLT_s64,
        GIM_CheckType, /*MI*/1, /*Op*/2, /*Type*/GILLT_s64,
        GIM_RecordInsnIgnoreCopies, /*DefineMI*/2, /*MI*/0, /*OpIdx*/2, // MIs[2]
        GIM_CheckOpcode, /*MI*/2, GIMT_Encode2(TargetOpcode::G_AND),
        GIM_CheckType, /*MI*/2, /*Op*/1, /*Type*/GILLT_s64,
        GIM_CheckType, /*MI*/2, /*Op*/2, /*Type*/GILLT_s64,
        GIM_RecordInsnIgnoreCopies, /*DefineMI*/3, /*MI*/2, /*OpIdx*/1, // MIs[3]
        GIM_CheckOpcode, /*MI*/3, GIMT_Encode2(TargetOpcode::G_OR),
        // MIs[3] x
        GIM_CheckIsSameOperandIgnoreCopies, /*MI*/3, /*OpIdx*/1, /*OtherMI*/1, /*OtherOpIdx*/2,
        // MIs[3] z
        GIM_CheckIsSameOperandIgnoreCopies, /*MI*/3, /*OpIdx*/2, /*OtherMI*/1, /*OtherOpIdx*/1,
        GIM_CheckCxxInsnPredicate, /*MI*/0, /*FnId*/GIMT_Encode2(GICXXPred_MI_Predicate_anonymous_22557),
        GIM_CheckIsSafeToFold, /*InsnID*/1,
        GIM_CheckIsSafeToFold, /*InsnID*/2,
        GIM_CheckIsSafeToFold, /*InsnID*/3,
        // (or:{ *:[i64] } (and:{ *:[i64] } i64:{ *:[i64] }:$z, i64:{ *:[i64] }:$x), (and:{ *:[i64] } (or:{ *:[i64] } i64:{ *:[i64] }:$x, i64:{ *:[i64] }:$z), i64:{ *:[i64] }:$y))<<P:Predicate_anonymous_22557>>  =>  (REG_SEQUENCE:{ *:[i64] } VReg_64:{ *:[i32] }, (V_BFI_B32_e64:{ *:[i16] } (V_XOR_B32_e64:{ *:[i16] } (EXTRACT_SUBREG:{ *:[i32] } VReg_64:{ *:[i64] }:$x, sub0:{ *:[i32] }), (EXTRACT_SUBREG:{ *:[i32] } VReg_64:{ *:[i64] }:$y, sub0:{ *:[i32] })), (EXTRACT_SUBREG:{ *:[i32] } VReg_64:{ *:[i64] }:$z, sub0:{ *:[i32] }), (EXTRACT_SUBREG:{ *:[i32] } VReg_64:{ *:[i64] }:$y, sub0:{ *:[i32] })), sub0:{ *:[i32] }, (V_BFI_B32_e64:{ *:[i16] } (V_XOR_B32_e64:{ *:[i16] } (EXTRACT_SUBREG:{ *:[i32] } VReg_64:{ *:[i64] }:$x, sub1:{ *:[i32] }), (EXTRACT_SUBREG:{ *:[i32] } VReg_64:{ *:[i64] }:$y, sub1:{ *:[i32] })), (EXTRACT_SUBREG:{ *:[i32] } VReg_64:{ *:[i64] }:$z, sub1:{ *:[i32] }), (EXTRACT_SUBREG:{ *:[i32] } VReg_64:{ *:[i64] }:$y, sub1:{ *:[i32] })), sub1:{ *:[i32] })
        GIR_MakeTempReg, /*TempRegID*/0, /*TypeID*/GILLT_s16,
        GIR_MakeTempReg, /*TempRegID*/1, /*TypeID*/GILLT_s16,
        GIR_MakeTempReg, /*TempRegID*/2, /*TypeID*/GILLT_s32,
        GIR_MakeTempReg, /*TempRegID*/3, /*TypeID*/GILLT_s32,
        GIR_MakeTempReg, /*TempRegID*/4, /*TypeID*/GILLT_s32,
        GIR_MakeTempReg, /*TempRegID*/5, /*TypeID*/GILLT_s32,
        GIR_MakeTempReg, /*TempRegID*/6, /*TypeID*/GILLT_s16,
        GIR_MakeTempReg, /*TempRegID*/7, /*TypeID*/GILLT_s16,
        GIR_MakeTempReg, /*TempRegID*/8, /*TypeID*/GILLT_s32,
        GIR_MakeTempReg, /*TempRegID*/9, /*TypeID*/GILLT_s32,
        GIR_MakeTempReg, /*TempRegID*/10, /*TypeID*/GILLT_s32,
        GIR_MakeTempReg, /*TempRegID*/11, /*TypeID*/GILLT_s32,
        GIR_BuildMI, /*InsnID*/12, /*Opcode*/GIMT_Encode2(TargetOpcode::COPY),
        GIR_AddTempRegister, /*InsnID*/12, /*TempRegID*/11, /*TempRegFlags*/GIMT_Encode2(RegState::Define),
        GIR_CopySubReg, /*NewInsnID*/12, /*OldInsnID*/2, /*OpIdx*/2, /*SubRegIdx*/GIMT_Encode2(11), // y
        GIR_ConstrainOperandRC, /*InsnID*/12, /*Op*/0, GIMT_Encode2(AMDGPU::VGPR_32RegClassID),
        GIR_ConstrainOperandRC, /*InsnID*/12, /*Op*/1, GIMT_Encode2(AMDGPU::VReg_64RegClassID),
        GIR_BuildMI, /*InsnID*/11, /*Opcode*/GIMT_Encode2(TargetOpcode::COPY),
        GIR_AddTempRegister, /*InsnID*/11, /*TempRegID*/10, /*TempRegFlags*/GIMT_Encode2(RegState::Define),
        GIR_CopySubReg, /*NewInsnID*/11, /*OldInsnID*/1, /*OpIdx*/1, /*SubRegIdx*/GIMT_Encode2(11), // z
        GIR_ConstrainOperandRC, /*InsnID*/11, /*Op*/0, GIMT_Encode2(AMDGPU::VGPR_32RegClassID),
        GIR_ConstrainOperandRC, /*InsnID*/11, /*Op*/1, GIMT_Encode2(AMDGPU::VReg_64RegClassID),
        GIR_BuildMI, /*InsnID*/10, /*Opcode*/GIMT_Encode2(TargetOpcode::COPY),
        GIR_AddTempRegister, /*InsnID*/10, /*TempRegID*/9, /*TempRegFlags*/GIMT_Encode2(RegState::Define),
        GIR_CopySubReg, /*NewInsnID*/10, /*OldInsnID*/2, /*OpIdx*/2, /*SubRegIdx*/GIMT_Encode2(11), // y
        GIR_ConstrainOperandRC, /*InsnID*/10, /*Op*/0, GIMT_Encode2(AMDGPU::VGPR_32RegClassID),
        GIR_ConstrainOperandRC, /*InsnID*/10, /*Op*/1, GIMT_Encode2(AMDGPU::VReg_64RegClassID),
        GIR_BuildMI, /*InsnID*/9, /*Opcode*/GIMT_Encode2(TargetOpcode::COPY),
        GIR_AddTempRegister, /*InsnID*/9, /*TempRegID*/8, /*TempRegFlags*/GIMT_Encode2(RegState::Define),
        GIR_CopySubReg, /*NewInsnID*/9, /*OldInsnID*/1, /*OpIdx*/2, /*SubRegIdx*/GIMT_Encode2(11), // x
        GIR_ConstrainOperandRC, /*InsnID*/9, /*Op*/0, GIMT_Encode2(AMDGPU::VGPR_32RegClassID),
        GIR_ConstrainOperandRC, /*InsnID*/9, /*Op*/1, GIMT_Encode2(AMDGPU::VReg_64RegClassID),
        GIR_BuildMI, /*InsnID*/8, /*Opcode*/GIMT_Encode2(AMDGPU::V_XOR_B32_e64),
        GIR_AddTempRegister, /*InsnID*/8, /*TempRegID*/7, /*TempRegFlags*/GIMT_Encode2(RegState::Define),
        GIR_AddSimpleTempRegister, /*InsnID*/8, /*TempRegID*/8,
        GIR_AddSimpleTempRegister, /*InsnID*/8, /*TempRegID*/9,
        GIR_ConstrainSelectedInstOperands, /*InsnID*/8,
        GIR_BuildMI, /*InsnID*/7, /*Opcode*/GIMT_Encode2(AMDGPU::V_BFI_B32_e64),
        GIR_AddTempRegister, /*InsnID*/7, /*TempRegID*/6, /*TempRegFlags*/GIMT_Encode2(RegState::Define),
        GIR_AddSimpleTempRegister, /*InsnID*/7, /*TempRegID*/7,
        GIR_AddSimpleTempRegister, /*InsnID*/7, /*TempRegID*/10,
        GIR_AddSimpleTempRegister, /*InsnID*/7, /*TempRegID*/11,
        GIR_ConstrainSelectedInstOperands, /*InsnID*/7,
        GIR_BuildMI, /*InsnID*/6, /*Opcode*/GIMT_Encode2(TargetOpcode::COPY),
        GIR_AddTempRegister, /*InsnID*/6, /*TempRegID*/5, /*TempRegFlags*/GIMT_Encode2(RegState::Define),
        GIR_CopySubReg, /*NewInsnID*/6, /*OldInsnID*/2, /*OpIdx*/2, /*SubRegIdx*/GIMT_Encode2(3), // y
        GIR_ConstrainOperandRC, /*InsnID*/6, /*Op*/0, GIMT_Encode2(AMDGPU::VGPR_32RegClassID),
        GIR_ConstrainOperandRC, /*InsnID*/6, /*Op*/1, GIMT_Encode2(AMDGPU::VReg_64RegClassID),
        GIR_BuildMI, /*InsnID*/5, /*Opcode*/GIMT_Encode2(TargetOpcode::COPY),
        GIR_AddTempRegister, /*InsnID*/5, /*TempRegID*/4, /*TempRegFlags*/GIMT_Encode2(RegState::Define),
        GIR_CopySubReg, /*NewInsnID*/5, /*OldInsnID*/1, /*OpIdx*/1, /*SubRegIdx*/GIMT_Encode2(3), // z
        GIR_ConstrainOperandRC, /*InsnID*/5, /*Op*/0, GIMT_Encode2(AMDGPU::VGPR_32RegClassID),
        GIR_ConstrainOperandRC, /*InsnID*/5, /*Op*/1, GIMT_Encode2(AMDGPU::VReg_64RegClassID),
        GIR_BuildMI, /*InsnID*/4, /*Opcode*/GIMT_Encode2(TargetOpcode::COPY),
        GIR_AddTempRegister, /*InsnID*/4, /*TempRegID*/3, /*TempRegFlags*/GIMT_Encode2(RegState::Define),
        GIR_CopySubReg, /*NewInsnID*/4, /*OldInsnID*/2, /*OpIdx*/2, /*SubRegIdx*/GIMT_Encode2(3), // y
        GIR_ConstrainOperandRC, /*InsnID*/4, /*Op*/0, GIMT_Encode2(AMDGPU::VGPR_32RegClassID),
        GIR_ConstrainOperandRC, /*InsnID*/4, /*Op*/1, GIMT_Encode2(AMDGPU::VReg_64RegClassID),
        GIR_BuildMI, /*InsnID*/3, /*Opcode*/GIMT_Encode2(TargetOpcode::COPY),
        GIR_AddTempRegister, /*InsnID*/3, /*TempRegID*/2, /*TempRegFlags*/GIMT_Encode2(RegState::Define),
        GIR_CopySubReg, /*NewInsnID*/3, /*OldInsnID*/1, /*OpIdx*/2, /*SubRegIdx*/GIMT_Encode2(3), // x
        GIR_ConstrainOperandRC, /*InsnID*/3, /*Op*/0, GIMT_Encode2(AMDGPU::VGPR_32RegClassID),
        GIR_ConstrainOperandRC, /*InsnID*/3, /*Op*/1, GIMT_Encode2(AMDGPU::VReg_64RegClassID),
        GIR_BuildMI, /*InsnID*/2, /*Opcode*/GIMT_Encode2(AMDGPU::V_XOR_B32_e64),
        GIR_AddTempRegister, /*InsnID*/2, /*TempRegID*/1, /*TempRegFlags*/GIMT_Encode2(RegState::Define),
        GIR_AddSimpleTempRegister, /*InsnID*/2, /*TempRegID*/2,
        GIR_AddSimpleTempRegister, /*InsnID*/2, /*TempRegID*/3,
        GIR_ConstrainSelectedInstOperands, /*InsnID*/2,
        GIR_BuildMI, /*InsnID*/1, /*Opcode*/GIMT_Encode2(AMDGPU::V_BFI_B32_e64),
        GIR_AddTempRegister, /*InsnID*/1, /*TempRegID*/0, /*TempRegFlags*/GIMT_Encode2(RegState::Define),
        GIR_AddSimpleTempRegister, /*InsnID*/1, /*TempRegID*/1,
        GIR_AddSimpleTempRegister, /*InsnID*/1, /*TempRegID*/4,
        GIR_AddSimpleTempRegister, /*InsnID*/1, /*TempRegID*/5,
        GIR_ConstrainSelectedInstOperands, /*InsnID*/1,
        GIR_BuildMI, /*InsnID*/0, /*Opcode*/GIMT_Encode2(TargetOpcode::REG_SEQUENCE),
        GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/0, // DstI[dst]
        GIR_AddSimpleTempRegister, /*InsnID*/0, /*TempRegID*/0,
        GIR_AddImm8, /*InsnID*/0, /*SubRegIndex*/3,
        GIR_AddSimpleTempRegister, /*InsnID*/0, /*TempRegID*/6,
        GIR_AddImm8, /*InsnID*/0, /*SubRegIndex*/11,
        GIR_ConstrainOperandRC, /*InsnID*/0, /*Op*/0, GIMT_Encode2(AMDGPU::VReg_64RegClassID),
        GIR_ConstrainOperandRC, /*InsnID*/0, /*Op*/1, GIMT_Encode2(AMDGPU::VGPR_32RegClassID),
        GIR_ConstrainOperandRC, /*InsnID*/0, /*Op*/3, GIMT_Encode2(AMDGPU::VGPR_32RegClassID),
        GIR_EraseFromParent, /*InsnID*/0,
        // GIR_Coverage, 9930,
        GIR_Done,
      // Label 355: @31632
      GIM_Try, /*On fail goto*//*Label 356*/ GIMT_Encode4(32050), // Rule ID 9931 //
        GIM_CheckRegBankForClass, /*MI*/0, /*Op*/0, /*RC*/GIMT_Encode2(AMDGPU::VReg_64RegClassID),
        GIM_RecordInsnIgnoreCopies, /*DefineMI*/1, /*MI*/0, /*OpIdx*/1, // MIs[1]
        GIM_CheckOpcode, /*MI*/1, GIMT_Encode2(TargetOpcode::G_AND),
        GIM_CheckType, /*MI*/1, /*Op*/1, /*Type*/GILLT_s64,
        GIM_CheckType, /*MI*/1, /*Op*/2, /*Type*/GILLT_s64,
        GIM_RecordInsnIgnoreCopies, /*DefineMI*/2, /*MI*/0, /*OpIdx*/2, // MIs[2]
        GIM_CheckOpcode, /*MI*/2, GIMT_Encode2(TargetOpcode::G_AND),
        GIM_CheckType, /*MI*/2, /*Op*/1, /*Type*/GILLT_s64,
        GIM_CheckType, /*MI*/2, /*Op*/2, /*Type*/GILLT_s64,
        GIM_RecordInsnIgnoreCopies, /*DefineMI*/3, /*MI*/2, /*OpIdx*/1, // MIs[3]
        GIM_CheckOpcode, /*MI*/3, GIMT_Encode2(TargetOpcode::G_OR),
        // MIs[3] z
        GIM_CheckIsSameOperandIgnoreCopies, /*MI*/3, /*OpIdx*/1, /*OtherMI*/1, /*OtherOpIdx*/1,
        // MIs[3] x
        GIM_CheckIsSameOperandIgnoreCopies, /*MI*/3, /*OpIdx*/2, /*OtherMI*/1, /*OtherOpIdx*/2,
        GIM_CheckCxxInsnPredicate, /*MI*/0, /*FnId*/GIMT_Encode2(GICXXPred_MI_Predicate_anonymous_22557),
        GIM_CheckIsSafeToFold, /*InsnID*/1,
        GIM_CheckIsSafeToFold, /*InsnID*/2,
        GIM_CheckIsSafeToFold, /*InsnID*/3,
        // (or:{ *:[i64] } (and:{ *:[i64] } i64:{ *:[i64] }:$z, i64:{ *:[i64] }:$x), (and:{ *:[i64] } (or:{ *:[i64] } i64:{ *:[i64] }:$z, i64:{ *:[i64] }:$x), i64:{ *:[i64] }:$y))<<P:Predicate_anonymous_22557>>  =>  (REG_SEQUENCE:{ *:[i64] } VReg_64:{ *:[i32] }, (V_BFI_B32_e64:{ *:[i16] } (V_XOR_B32_e64:{ *:[i16] } (EXTRACT_SUBREG:{ *:[i32] } VReg_64:{ *:[i64] }:$x, sub0:{ *:[i32] }), (EXTRACT_SUBREG:{ *:[i32] } VReg_64:{ *:[i64] }:$y, sub0:{ *:[i32] })), (EXTRACT_SUBREG:{ *:[i32] } VReg_64:{ *:[i64] }:$z, sub0:{ *:[i32] }), (EXTRACT_SUBREG:{ *:[i32] } VReg_64:{ *:[i64] }:$y, sub0:{ *:[i32] })), sub0:{ *:[i32] }, (V_BFI_B32_e64:{ *:[i16] } (V_XOR_B32_e64:{ *:[i16] } (EXTRACT_SUBREG:{ *:[i32] } VReg_64:{ *:[i64] }:$x, sub1:{ *:[i32] }), (EXTRACT_SUBREG:{ *:[i32] } VReg_64:{ *:[i64] }:$y, sub1:{ *:[i32] })), (EXTRACT_SUBREG:{ *:[i32] } VReg_64:{ *:[i64] }:$z, sub1:{ *:[i32] }), (EXTRACT_SUBREG:{ *:[i32] } VReg_64:{ *:[i64] }:$y, sub1:{ *:[i32] })), sub1:{ *:[i32] })
        GIR_MakeTempReg, /*TempRegID*/0, /*TypeID*/GILLT_s16,
        GIR_MakeTempReg, /*TempRegID*/1, /*TypeID*/GILLT_s16,
        GIR_MakeTempReg, /*TempRegID*/2, /*TypeID*/GILLT_s32,
        GIR_MakeTempReg, /*TempRegID*/3, /*TypeID*/GILLT_s32,
        GIR_MakeTempReg, /*TempRegID*/4, /*TypeID*/GILLT_s32,
        GIR_MakeTempReg, /*TempRegID*/5, /*TypeID*/GILLT_s32,
        GIR_MakeTempReg, /*TempRegID*/6, /*TypeID*/GILLT_s16,
        GIR_MakeTempReg, /*TempRegID*/7, /*TypeID*/GILLT_s16,
        GIR_MakeTempReg, /*TempRegID*/8, /*TypeID*/GILLT_s32,
        GIR_MakeTempReg, /*TempRegID*/9, /*TypeID*/GILLT_s32,
        GIR_MakeTempReg, /*TempRegID*/10, /*TypeID*/GILLT_s32,
        GIR_MakeTempReg, /*TempRegID*/11, /*TypeID*/GILLT_s32,
        GIR_BuildMI, /*InsnID*/12, /*Opcode*/GIMT_Encode2(TargetOpcode::COPY),
        GIR_AddTempRegister, /*InsnID*/12, /*TempRegID*/11, /*TempRegFlags*/GIMT_Encode2(RegState::Define),
        GIR_CopySubReg, /*NewInsnID*/12, /*OldInsnID*/2, /*OpIdx*/2, /*SubRegIdx*/GIMT_Encode2(11), // y
        GIR_ConstrainOperandRC, /*InsnID*/12, /*Op*/0, GIMT_Encode2(AMDGPU::VGPR_32RegClassID),
        GIR_ConstrainOperandRC, /*InsnID*/12, /*Op*/1, GIMT_Encode2(AMDGPU::VReg_64RegClassID),
        GIR_BuildMI, /*InsnID*/11, /*Opcode*/GIMT_Encode2(TargetOpcode::COPY),
        GIR_AddTempRegister, /*InsnID*/11, /*TempRegID*/10, /*TempRegFlags*/GIMT_Encode2(RegState::Define),
        GIR_CopySubReg, /*NewInsnID*/11, /*OldInsnID*/1, /*OpIdx*/1, /*SubRegIdx*/GIMT_Encode2(11), // z
        GIR_ConstrainOperandRC, /*InsnID*/11, /*Op*/0, GIMT_Encode2(AMDGPU::VGPR_32RegClassID),
        GIR_ConstrainOperandRC, /*InsnID*/11, /*Op*/1, GIMT_Encode2(AMDGPU::VReg_64RegClassID),
        GIR_BuildMI, /*InsnID*/10, /*Opcode*/GIMT_Encode2(TargetOpcode::COPY),
        GIR_AddTempRegister, /*InsnID*/10, /*TempRegID*/9, /*TempRegFlags*/GIMT_Encode2(RegState::Define),
        GIR_CopySubReg, /*NewInsnID*/10, /*OldInsnID*/2, /*OpIdx*/2, /*SubRegIdx*/GIMT_Encode2(11), // y
        GIR_ConstrainOperandRC, /*InsnID*/10, /*Op*/0, GIMT_Encode2(AMDGPU::VGPR_32RegClassID),
        GIR_ConstrainOperandRC, /*InsnID*/10, /*Op*/1, GIMT_Encode2(AMDGPU::VReg_64RegClassID),
        GIR_BuildMI, /*InsnID*/9, /*Opcode*/GIMT_Encode2(TargetOpcode::COPY),
        GIR_AddTempRegister, /*InsnID*/9, /*TempRegID*/8, /*TempRegFlags*/GIMT_Encode2(RegState::Define),
        GIR_CopySubReg, /*NewInsnID*/9, /*OldInsnID*/1, /*OpIdx*/2, /*SubRegIdx*/GIMT_Encode2(11), // x
        GIR_ConstrainOperandRC, /*InsnID*/9, /*Op*/0, GIMT_Encode2(AMDGPU::VGPR_32RegClassID),
        GIR_ConstrainOperandRC, /*InsnID*/9, /*Op*/1, GIMT_Encode2(AMDGPU::VReg_64RegClassID),
        GIR_BuildMI, /*InsnID*/8, /*Opcode*/GIMT_Encode2(AMDGPU::V_XOR_B32_e64),
        GIR_AddTempRegister, /*InsnID*/8, /*TempRegID*/7, /*TempRegFlags*/GIMT_Encode2(RegState::Define),
        GIR_AddSimpleTempRegister, /*InsnID*/8, /*TempRegID*/8,
        GIR_AddSimpleTempRegister, /*InsnID*/8, /*TempRegID*/9,
        GIR_ConstrainSelectedInstOperands, /*InsnID*/8,
        GIR_BuildMI, /*InsnID*/7, /*Opcode*/GIMT_Encode2(AMDGPU::V_BFI_B32_e64),
        GIR_AddTempRegister, /*InsnID*/7, /*TempRegID*/6, /*TempRegFlags*/GIMT_Encode2(RegState::Define),
        GIR_AddSimpleTempRegister, /*InsnID*/7, /*TempRegID*/7,
        GIR_AddSimpleTempRegister, /*InsnID*/7, /*TempRegID*/10,
        GIR_AddSimpleTempRegister, /*InsnID*/7, /*TempRegID*/11,
        GIR_ConstrainSelectedInstOperands, /*InsnID*/7,
        GIR_BuildMI, /*InsnID*/6, /*Opcode*/GIMT_Encode2(TargetOpcode::COPY),
        GIR_AddTempRegister, /*InsnID*/6, /*TempRegID*/5, /*TempRegFlags*/GIMT_Encode2(RegState::Define),
        GIR_CopySubReg, /*NewInsnID*/6, /*OldInsnID*/2, /*OpIdx*/2, /*SubRegIdx*/GIMT_Encode2(3), // y
        GIR_ConstrainOperandRC, /*InsnID*/6, /*Op*/0, GIMT_Encode2(AMDGPU::VGPR_32RegClassID),
        GIR_ConstrainOperandRC, /*InsnID*/6, /*Op*/1, GIMT_Encode2(AMDGPU::VReg_64RegClassID),
        GIR_BuildMI, /*InsnID*/5, /*Opcode*/GIMT_Encode2(TargetOpcode::COPY),
        GIR_AddTempRegister, /*InsnID*/5, /*TempRegID*/4, /*TempRegFlags*/GIMT_Encode2(RegState::Define),
        GIR_CopySubReg, /*NewInsnID*/5, /*OldInsnID*/1, /*OpIdx*/1, /*SubRegIdx*/GIMT_Encode2(3), // z
        GIR_ConstrainOperandRC, /*InsnID*/5, /*Op*/0, GIMT_Encode2(AMDGPU::VGPR_32RegClassID),
        GIR_ConstrainOperandRC, /*InsnID*/5, /*Op*/1, GIMT_Encode2(AMDGPU::VReg_64RegClassID),
        GIR_BuildMI, /*InsnID*/4, /*Opcode*/GIMT_Encode2(TargetOpcode::COPY),
        GIR_AddTempRegister, /*InsnID*/4, /*TempRegID*/3, /*TempRegFlags*/GIMT_Encode2(RegState::Define),
        GIR_CopySubReg, /*NewInsnID*/4, /*OldInsnID*/2, /*OpIdx*/2, /*SubRegIdx*/GIMT_Encode2(3), // y
        GIR_ConstrainOperandRC, /*InsnID*/4, /*Op*/0, GIMT_Encode2(AMDGPU::VGPR_32RegClassID),
        GIR_ConstrainOperandRC, /*InsnID*/4, /*Op*/1, GIMT_Encode2(AMDGPU::VReg_64RegClassID),
        GIR_BuildMI, /*InsnID*/3, /*Opcode*/GIMT_Encode2(TargetOpcode::COPY),
        GIR_AddTempRegister, /*InsnID*/3, /*TempRegID*/2, /*TempRegFlags*/GIMT_Encode2(RegState::Define),
        GIR_CopySubReg, /*NewInsnID*/3, /*OldInsnID*/1, /*OpIdx*/2, /*SubRegIdx*/GIMT_Encode2(3), // x
        GIR_ConstrainOperandRC, /*InsnID*/3, /*Op*/0, GIMT_Encode2(AMDGPU::VGPR_32RegClassID),
        GIR_ConstrainOperandRC, /*InsnID*/3, /*Op*/1, GIMT_Encode2(AMDGPU::VReg_64RegClassID),
        GIR_BuildMI, /*InsnID*/2, /*Opcode*/GIMT_Encode2(AMDGPU::V_XOR_B32_e64),
        GIR_AddTempRegister, /*InsnID*/2, /*TempRegID*/1, /*TempRegFlags*/GIMT_Encode2(RegState::Define),
        GIR_AddSimpleTempRegister, /*InsnID*/2, /*TempRegID*/2,
        GIR_AddSimpleTempRegister, /*InsnID*/2, /*TempRegID*/3,
        GIR_ConstrainSelectedInstOperands, /*InsnID*/2,
        GIR_BuildMI, /*InsnID*/1, /*Opcode*/GIMT_Encode2(AMDGPU::V_BFI_B32_e64),
        GIR_AddTempRegister, /*InsnID*/1, /*TempRegID*/0, /*TempRegFlags*/GIMT_Encode2(RegState::Define),
        GIR_AddSimpleTempRegister, /*InsnID*/1, /*TempRegID*/1,
        GIR_AddSimpleTempRegister, /*InsnID*/1, /*TempRegID*/4,
        GIR_AddSimpleTempRegister, /*InsnID*/1, /*TempRegID*/5,
        GIR_ConstrainSelectedInstOperands, /*InsnID*/1,
        GIR_BuildMI, /*InsnID*/0, /*Opcode*/GIMT_Encode2(TargetOpcode::REG_SEQUENCE),
        GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/0, // DstI[dst]
        GIR_AddSimpleTempRegister, /*InsnID*/0, /*TempRegID*/0,
        GIR_AddImm8, /*InsnID*/0, /*SubRegIndex*/3,
        GIR_AddSimpleTempRegister, /*InsnID*/0, /*TempRegID*/6,
        GIR_AddImm8, /*InsnID*/0, /*SubRegIndex*/11,
        GIR_ConstrainOperandRC, /*InsnID*/0, /*Op*/0, GIMT_Encode2(AMDGPU::VReg_64RegClassID),
        GIR_ConstrainOperandRC, /*InsnID*/0, /*Op*/1, GIMT_Encode2(AMDGPU::VGPR_32RegClassID),
        GIR_ConstrainOperandRC, /*InsnID*/0, /*Op*/3, GIMT_Encode2(AMDGPU::VGPR_32RegClassID),
        GIR_EraseFromParent, /*InsnID*/0,
        // GIR_Coverage, 9931,
        GIR_Done,
      // Label 356: @32050
      GIM_Try, /*On fail goto*//*Label 357*/ GIMT_Encode4(32468), // Rule ID 6477 //
        GIM_CheckRegBankForClass, /*MI*/0, /*Op*/0, /*RC*/GIMT_Encode2(AMDGPU::VReg_64RegClassID),
        GIM_RecordInsnIgnoreCopies, /*DefineMI*/1, /*MI*/0, /*OpIdx*/1, // MIs[1]
        GIM_CheckOpcode, /*MI*/1, GIMT_Encode2(TargetOpcode::G_AND),
        GIM_CheckType, /*MI*/1, /*Op*/1, /*Type*/GILLT_s64,
        GIM_CheckType, /*MI*/1, /*Op*/2, /*Type*/GILLT_s64,
        GIM_RecordInsnIgnoreCopies, /*DefineMI*/2, /*MI*/0, /*OpIdx*/2, // MIs[2]
        GIM_CheckOpcode, /*MI*/2, GIMT_Encode2(TargetOpcode::G_AND),
        GIM_CheckType, /*MI*/2, /*Op*/1, /*Type*/GILLT_s64,
        GIM_CheckType, /*MI*/2, /*Op*/2, /*Type*/GILLT_s64,
        GIM_RecordInsnIgnoreCopies, /*DefineMI*/3, /*MI*/2, /*OpIdx*/2, // MIs[3]
        GIM_CheckOpcode, /*MI*/3, GIMT_Encode2(TargetOpcode::G_OR),
        // MIs[3] x
        GIM_CheckIsSameOperandIgnoreCopies, /*MI*/3, /*OpIdx*/1, /*OtherMI*/1, /*OtherOpIdx*/1,
        // MIs[3] z
        GIM_CheckIsSameOperandIgnoreCopies, /*MI*/3, /*OpIdx*/2, /*OtherMI*/1, /*OtherOpIdx*/2,
        GIM_CheckCxxInsnPredicate, /*MI*/0, /*FnId*/GIMT_Encode2(GICXXPred_MI_Predicate_anonymous_22557),
        GIM_CheckIsSafeToFold, /*InsnID*/1,
        GIM_CheckIsSafeToFold, /*InsnID*/2,
        GIM_CheckIsSafeToFold, /*InsnID*/3,
        // (or:{ *:[i64] } (and:{ *:[i64] } i64:{ *:[i64] }:$x, i64:{ *:[i64] }:$z), (and:{ *:[i64] } i64:{ *:[i64] }:$y, (or:{ *:[i64] } i64:{ *:[i64] }:$x, i64:{ *:[i64] }:$z)))<<P:Predicate_anonymous_22557>>  =>  (REG_SEQUENCE:{ *:[i64] } VReg_64:{ *:[i32] }, (V_BFI_B32_e64:{ *:[i16] } (V_XOR_B32_e64:{ *:[i16] } (EXTRACT_SUBREG:{ *:[i32] } VReg_64:{ *:[i64] }:$x, sub0:{ *:[i32] }), (EXTRACT_SUBREG:{ *:[i32] } VReg_64:{ *:[i64] }:$y, sub0:{ *:[i32] })), (EXTRACT_SUBREG:{ *:[i32] } VReg_64:{ *:[i64] }:$z, sub0:{ *:[i32] }), (EXTRACT_SUBREG:{ *:[i32] } VReg_64:{ *:[i64] }:$y, sub0:{ *:[i32] })), sub0:{ *:[i32] }, (V_BFI_B32_e64:{ *:[i16] } (V_XOR_B32_e64:{ *:[i16] } (EXTRACT_SUBREG:{ *:[i32] } VReg_64:{ *:[i64] }:$x, sub1:{ *:[i32] }), (EXTRACT_SUBREG:{ *:[i32] } VReg_64:{ *:[i64] }:$y, sub1:{ *:[i32] })), (EXTRACT_SUBREG:{ *:[i32] } VReg_64:{ *:[i64] }:$z, sub1:{ *:[i32] }), (EXTRACT_SUBREG:{ *:[i32] } VReg_64:{ *:[i64] }:$y, sub1:{ *:[i32] })), sub1:{ *:[i32] })
        GIR_MakeTempReg, /*TempRegID*/0, /*TypeID*/GILLT_s16,
        GIR_MakeTempReg, /*TempRegID*/1, /*TypeID*/GILLT_s16,
        GIR_MakeTempReg, /*TempRegID*/2, /*TypeID*/GILLT_s32,
        GIR_MakeTempReg, /*TempRegID*/3, /*TypeID*/GILLT_s32,
        GIR_MakeTempReg, /*TempRegID*/4, /*TypeID*/GILLT_s32,
        GIR_MakeTempReg, /*TempRegID*/5, /*TypeID*/GILLT_s32,
        GIR_MakeTempReg, /*TempRegID*/6, /*TypeID*/GILLT_s16,
        GIR_MakeTempReg, /*TempRegID*/7, /*TypeID*/GILLT_s16,
        GIR_MakeTempReg, /*TempRegID*/8, /*TypeID*/GILLT_s32,
        GIR_MakeTempReg, /*TempRegID*/9, /*TypeID*/GILLT_s32,
        GIR_MakeTempReg, /*TempRegID*/10, /*TypeID*/GILLT_s32,
        GIR_MakeTempReg, /*TempRegID*/11, /*TypeID*/GILLT_s32,
        GIR_BuildMI, /*InsnID*/12, /*Opcode*/GIMT_Encode2(TargetOpcode::COPY),
        GIR_AddTempRegister, /*InsnID*/12, /*TempRegID*/11, /*TempRegFlags*/GIMT_Encode2(RegState::Define),
        GIR_CopySubReg, /*NewInsnID*/12, /*OldInsnID*/2, /*OpIdx*/1, /*SubRegIdx*/GIMT_Encode2(11), // y
        GIR_ConstrainOperandRC, /*InsnID*/12, /*Op*/0, GIMT_Encode2(AMDGPU::VGPR_32RegClassID),
        GIR_ConstrainOperandRC, /*InsnID*/12, /*Op*/1, GIMT_Encode2(AMDGPU::VReg_64RegClassID),
        GIR_BuildMI, /*InsnID*/11, /*Opcode*/GIMT_Encode2(TargetOpcode::COPY),
        GIR_AddTempRegister, /*InsnID*/11, /*TempRegID*/10, /*TempRegFlags*/GIMT_Encode2(RegState::Define),
        GIR_CopySubReg, /*NewInsnID*/11, /*OldInsnID*/1, /*OpIdx*/2, /*SubRegIdx*/GIMT_Encode2(11), // z
        GIR_ConstrainOperandRC, /*InsnID*/11, /*Op*/0, GIMT_Encode2(AMDGPU::VGPR_32RegClassID),
        GIR_ConstrainOperandRC, /*InsnID*/11, /*Op*/1, GIMT_Encode2(AMDGPU::VReg_64RegClassID),
        GIR_BuildMI, /*InsnID*/10, /*Opcode*/GIMT_Encode2(TargetOpcode::COPY),
        GIR_AddTempRegister, /*InsnID*/10, /*TempRegID*/9, /*TempRegFlags*/GIMT_Encode2(RegState::Define),
        GIR_CopySubReg, /*NewInsnID*/10, /*OldInsnID*/2, /*OpIdx*/1, /*SubRegIdx*/GIMT_Encode2(11), // y
        GIR_ConstrainOperandRC, /*InsnID*/10, /*Op*/0, GIMT_Encode2(AMDGPU::VGPR_32RegClassID),
        GIR_ConstrainOperandRC, /*InsnID*/10, /*Op*/1, GIMT_Encode2(AMDGPU::VReg_64RegClassID),
        GIR_BuildMI, /*InsnID*/9, /*Opcode*/GIMT_Encode2(TargetOpcode::COPY),
        GIR_AddTempRegister, /*InsnID*/9, /*TempRegID*/8, /*TempRegFlags*/GIMT_Encode2(RegState::Define),
        GIR_CopySubReg, /*NewInsnID*/9, /*OldInsnID*/1, /*OpIdx*/1, /*SubRegIdx*/GIMT_Encode2(11), // x
        GIR_ConstrainOperandRC, /*InsnID*/9, /*Op*/0, GIMT_Encode2(AMDGPU::VGPR_32RegClassID),
        GIR_ConstrainOperandRC, /*InsnID*/9, /*Op*/1, GIMT_Encode2(AMDGPU::VReg_64RegClassID),
        GIR_BuildMI, /*InsnID*/8, /*Opcode*/GIMT_Encode2(AMDGPU::V_XOR_B32_e64),
        GIR_AddTempRegister, /*InsnID*/8, /*TempRegID*/7, /*TempRegFlags*/GIMT_Encode2(RegState::Define),
        GIR_AddSimpleTempRegister, /*InsnID*/8, /*TempRegID*/8,
        GIR_AddSimpleTempRegister, /*InsnID*/8, /*TempRegID*/9,
        GIR_ConstrainSelectedInstOperands, /*InsnID*/8,
        GIR_BuildMI, /*InsnID*/7, /*Opcode*/GIMT_Encode2(AMDGPU::V_BFI_B32_e64),
        GIR_AddTempRegister, /*InsnID*/7, /*TempRegID*/6, /*TempRegFlags*/GIMT_Encode2(RegState::Define),
        GIR_AddSimpleTempRegister, /*InsnID*/7, /*TempRegID*/7,
        GIR_AddSimpleTempRegister, /*InsnID*/7, /*TempRegID*/10,
        GIR_AddSimpleTempRegister, /*InsnID*/7, /*TempRegID*/11,
        GIR_ConstrainSelectedInstOperands, /*InsnID*/7,
        GIR_BuildMI, /*InsnID*/6, /*Opcode*/GIMT_Encode2(TargetOpcode::COPY),
        GIR_AddTempRegister, /*InsnID*/6, /*TempRegID*/5, /*TempRegFlags*/GIMT_Encode2(RegState::Define),
        GIR_CopySubReg, /*NewInsnID*/6, /*OldInsnID*/2, /*OpIdx*/1, /*SubRegIdx*/GIMT_Encode2(3), // y
        GIR_ConstrainOperandRC, /*InsnID*/6, /*Op*/0, GIMT_Encode2(AMDGPU::VGPR_32RegClassID),
        GIR_ConstrainOperandRC, /*InsnID*/6, /*Op*/1, GIMT_Encode2(AMDGPU::VReg_64RegClassID),
        GIR_BuildMI, /*InsnID*/5, /*Opcode*/GIMT_Encode2(TargetOpcode::COPY),
        GIR_AddTempRegister, /*InsnID*/5, /*TempRegID*/4, /*TempRegFlags*/GIMT_Encode2(RegState::Define),
        GIR_CopySubReg, /*NewInsnID*/5, /*OldInsnID*/1, /*OpIdx*/2, /*SubRegIdx*/GIMT_Encode2(3), // z
        GIR_ConstrainOperandRC, /*InsnID*/5, /*Op*/0, GIMT_Encode2(AMDGPU::VGPR_32RegClassID),
        GIR_ConstrainOperandRC, /*InsnID*/5, /*Op*/1, GIMT_Encode2(AMDGPU::VReg_64RegClassID),
        GIR_BuildMI, /*InsnID*/4, /*Opcode*/GIMT_Encode2(TargetOpcode::COPY),
        GIR_AddTempRegister, /*InsnID*/4, /*TempRegID*/3, /*TempRegFlags*/GIMT_Encode2(RegState::Define),
        GIR_CopySubReg, /*NewInsnID*/4, /*OldInsnID*/2, /*OpIdx*/1, /*SubRegIdx*/GIMT_Encode2(3), // y
        GIR_ConstrainOperandRC, /*InsnID*/4, /*Op*/0, GIMT_Encode2(AMDGPU::VGPR_32RegClassID),
        GIR_ConstrainOperandRC, /*InsnID*/4, /*Op*/1, GIMT_Encode2(AMDGPU::VReg_64RegClassID),
        GIR_BuildMI, /*InsnID*/3, /*Opcode*/GIMT_Encode2(TargetOpcode::COPY),
        GIR_AddTempRegister, /*InsnID*/3, /*TempRegID*/2, /*TempRegFlags*/GIMT_Encode2(RegState::Define),
        GIR_CopySubReg, /*NewInsnID*/3, /*OldInsnID*/1, /*OpIdx*/1, /*SubRegIdx*/GIMT_Encode2(3), // x
        GIR_ConstrainOperandRC, /*InsnID*/3, /*Op*/0, GIMT_Encode2(AMDGPU::VGPR_32RegClassID),
        GIR_ConstrainOperandRC, /*InsnID*/3, /*Op*/1, GIMT_Encode2(AMDGPU::VReg_64RegClassID),
        GIR_BuildMI, /*InsnID*/2, /*Opcode*/GIMT_Encode2(AMDGPU::V_XOR_B32_e64),
        GIR_AddTempRegister, /*InsnID*/2, /*TempRegID*/1, /*TempRegFlags*/GIMT_Encode2(RegState::Define),
        GIR_AddSimpleTempRegister, /*InsnID*/2, /*TempRegID*/2,
        GIR_AddSimpleTempRegister, /*InsnID*/2, /*TempRegID*/3,
        GIR_ConstrainSelectedInstOperands, /*InsnID*/2,
        GIR_BuildMI, /*InsnID*/1, /*Opcode*/GIMT_Encode2(AMDGPU::V_BFI_B32_e64),
        GIR_AddTempRegister, /*InsnID*/1, /*TempRegID*/0, /*TempRegFlags*/GIMT_Encode2(RegState::Define),
        GIR_AddSimpleTempRegister, /*InsnID*/1, /*TempRegID*/1,
        GIR_AddSimpleTempRegister, /*InsnID*/1, /*TempRegID*/4,
        GIR_AddSimpleTempRegister, /*InsnID*/1, /*TempRegID*/5,
        GIR_ConstrainSelectedInstOperands, /*InsnID*/1,
        GIR_BuildMI, /*InsnID*/0, /*Opcode*/GIMT_Encode2(TargetOpcode::REG_SEQUENCE),
        GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/0, // DstI[dst]
        GIR_AddSimpleTempRegister, /*InsnID*/0, /*TempRegID*/0,
        GIR_AddImm8, /*InsnID*/0, /*SubRegIndex*/3,
        GIR_AddSimpleTempRegister, /*InsnID*/0, /*TempRegID*/6,
        GIR_AddImm8, /*InsnID*/0, /*SubRegIndex*/11,
        GIR_ConstrainOperandRC, /*InsnID*/0, /*Op*/0, GIMT_Encode2(AMDGPU::VReg_64RegClassID),
        GIR_ConstrainOperandRC, /*InsnID*/0, /*Op*/1, GIMT_Encode2(AMDGPU::VGPR_32RegClassID),
        GIR_ConstrainOperandRC, /*InsnID*/0, /*Op*/3, GIMT_Encode2(AMDGPU::VGPR_32RegClassID),
        GIR_EraseFromParent, /*InsnID*/0,
        // GIR_Coverage, 6477,
        GIR_Done,
      // Label 357: @32468
      GIM_Try, /*On fail goto*//*Label 358*/ GIMT_Encode4(32886), // Rule ID 9925 //
        GIM_CheckRegBankForClass, /*MI*/0, /*Op*/0, /*RC*/GIMT_Encode2(AMDGPU::VReg_64RegClassID),
        GIM_RecordInsnIgnoreCopies, /*DefineMI*/1, /*MI*/0, /*OpIdx*/1, // MIs[1]
        GIM_CheckOpcode, /*MI*/1, GIMT_Encode2(TargetOpcode::G_AND),
        GIM_CheckType, /*MI*/1, /*Op*/1, /*Type*/GILLT_s64,
        GIM_CheckType, /*MI*/1, /*Op*/2, /*Type*/GILLT_s64,
        GIM_RecordInsnIgnoreCopies, /*DefineMI*/2, /*MI*/0, /*OpIdx*/2, // MIs[2]
        GIM_CheckOpcode, /*MI*/2, GIMT_Encode2(TargetOpcode::G_AND),
        GIM_CheckType, /*MI*/2, /*Op*/1, /*Type*/GILLT_s64,
        GIM_CheckType, /*MI*/2, /*Op*/2, /*Type*/GILLT_s64,
        GIM_RecordInsnIgnoreCopies, /*DefineMI*/3, /*MI*/2, /*OpIdx*/2, // MIs[3]
        GIM_CheckOpcode, /*MI*/3, GIMT_Encode2(TargetOpcode::G_OR),
        // MIs[3] z
        GIM_CheckIsSameOperandIgnoreCopies, /*MI*/3, /*OpIdx*/1, /*OtherMI*/1, /*OtherOpIdx*/2,
        // MIs[3] x
        GIM_CheckIsSameOperandIgnoreCopies, /*MI*/3, /*OpIdx*/2, /*OtherMI*/1, /*OtherOpIdx*/1,
        GIM_CheckCxxInsnPredicate, /*MI*/0, /*FnId*/GIMT_Encode2(GICXXPred_MI_Predicate_anonymous_22557),
        GIM_CheckIsSafeToFold, /*InsnID*/1,
        GIM_CheckIsSafeToFold, /*InsnID*/2,
        GIM_CheckIsSafeToFold, /*InsnID*/3,
        // (or:{ *:[i64] } (and:{ *:[i64] } i64:{ *:[i64] }:$x, i64:{ *:[i64] }:$z), (and:{ *:[i64] } i64:{ *:[i64] }:$y, (or:{ *:[i64] } i64:{ *:[i64] }:$z, i64:{ *:[i64] }:$x)))<<P:Predicate_anonymous_22557>>  =>  (REG_SEQUENCE:{ *:[i64] } VReg_64:{ *:[i32] }, (V_BFI_B32_e64:{ *:[i16] } (V_XOR_B32_e64:{ *:[i16] } (EXTRACT_SUBREG:{ *:[i32] } VReg_64:{ *:[i64] }:$x, sub0:{ *:[i32] }), (EXTRACT_SUBREG:{ *:[i32] } VReg_64:{ *:[i64] }:$y, sub0:{ *:[i32] })), (EXTRACT_SUBREG:{ *:[i32] } VReg_64:{ *:[i64] }:$z, sub0:{ *:[i32] }), (EXTRACT_SUBREG:{ *:[i32] } VReg_64:{ *:[i64] }:$y, sub0:{ *:[i32] })), sub0:{ *:[i32] }, (V_BFI_B32_e64:{ *:[i16] } (V_XOR_B32_e64:{ *:[i16] } (EXTRACT_SUBREG:{ *:[i32] } VReg_64:{ *:[i64] }:$x, sub1:{ *:[i32] }), (EXTRACT_SUBREG:{ *:[i32] } VReg_64:{ *:[i64] }:$y, sub1:{ *:[i32] })), (EXTRACT_SUBREG:{ *:[i32] } VReg_64:{ *:[i64] }:$z, sub1:{ *:[i32] }), (EXTRACT_SUBREG:{ *:[i32] } VReg_64:{ *:[i64] }:$y, sub1:{ *:[i32] })), sub1:{ *:[i32] })
        GIR_MakeTempReg, /*TempRegID*/0, /*TypeID*/GILLT_s16,
        GIR_MakeTempReg, /*TempRegID*/1, /*TypeID*/GILLT_s16,
        GIR_MakeTempReg, /*TempRegID*/2, /*TypeID*/GILLT_s32,
        GIR_MakeTempReg, /*TempRegID*/3, /*TypeID*/GILLT_s32,
        GIR_MakeTempReg, /*TempRegID*/4, /*TypeID*/GILLT_s32,
        GIR_MakeTempReg, /*TempRegID*/5, /*TypeID*/GILLT_s32,
        GIR_MakeTempReg, /*TempRegID*/6, /*TypeID*/GILLT_s16,
        GIR_MakeTempReg, /*TempRegID*/7, /*TypeID*/GILLT_s16,
        GIR_MakeTempReg, /*TempRegID*/8, /*TypeID*/GILLT_s32,
        GIR_MakeTempReg, /*TempRegID*/9, /*TypeID*/GILLT_s32,
        GIR_MakeTempReg, /*TempRegID*/10, /*TypeID*/GILLT_s32,
        GIR_MakeTempReg, /*TempRegID*/11, /*TypeID*/GILLT_s32,
        GIR_BuildMI, /*InsnID*/12, /*Opcode*/GIMT_Encode2(TargetOpcode::COPY),
        GIR_AddTempRegister, /*InsnID*/12, /*TempRegID*/11, /*TempRegFlags*/GIMT_Encode2(RegState::Define),
        GIR_CopySubReg, /*NewInsnID*/12, /*OldInsnID*/2, /*OpIdx*/1, /*SubRegIdx*/GIMT_Encode2(11), // y
        GIR_ConstrainOperandRC, /*InsnID*/12, /*Op*/0, GIMT_Encode2(AMDGPU::VGPR_32RegClassID),
        GIR_ConstrainOperandRC, /*InsnID*/12, /*Op*/1, GIMT_Encode2(AMDGPU::VReg_64RegClassID),
        GIR_BuildMI, /*InsnID*/11, /*Opcode*/GIMT_Encode2(TargetOpcode::COPY),
        GIR_AddTempRegister, /*InsnID*/11, /*TempRegID*/10, /*TempRegFlags*/GIMT_Encode2(RegState::Define),
        GIR_CopySubReg, /*NewInsnID*/11, /*OldInsnID*/1, /*OpIdx*/2, /*SubRegIdx*/GIMT_Encode2(11), // z
        GIR_ConstrainOperandRC, /*InsnID*/11, /*Op*/0, GIMT_Encode2(AMDGPU::VGPR_32RegClassID),
        GIR_ConstrainOperandRC, /*InsnID*/11, /*Op*/1, GIMT_Encode2(AMDGPU::VReg_64RegClassID),
        GIR_BuildMI, /*InsnID*/10, /*Opcode*/GIMT_Encode2(TargetOpcode::COPY),
        GIR_AddTempRegister, /*InsnID*/10, /*TempRegID*/9, /*TempRegFlags*/GIMT_Encode2(RegState::Define),
        GIR_CopySubReg, /*NewInsnID*/10, /*OldInsnID*/2, /*OpIdx*/1, /*SubRegIdx*/GIMT_Encode2(11), // y
        GIR_ConstrainOperandRC, /*InsnID*/10, /*Op*/0, GIMT_Encode2(AMDGPU::VGPR_32RegClassID),
        GIR_ConstrainOperandRC, /*InsnID*/10, /*Op*/1, GIMT_Encode2(AMDGPU::VReg_64RegClassID),
        GIR_BuildMI, /*InsnID*/9, /*Opcode*/GIMT_Encode2(TargetOpcode::COPY),
        GIR_AddTempRegister, /*InsnID*/9, /*TempRegID*/8, /*TempRegFlags*/GIMT_Encode2(RegState::Define),
        GIR_CopySubReg, /*NewInsnID*/9, /*OldInsnID*/1, /*OpIdx*/1, /*SubRegIdx*/GIMT_Encode2(11), // x
        GIR_ConstrainOperandRC, /*InsnID*/9, /*Op*/0, GIMT_Encode2(AMDGPU::VGPR_32RegClassID),
        GIR_ConstrainOperandRC, /*InsnID*/9, /*Op*/1, GIMT_Encode2(AMDGPU::VReg_64RegClassID),
        GIR_BuildMI, /*InsnID*/8, /*Opcode*/GIMT_Encode2(AMDGPU::V_XOR_B32_e64),
        GIR_AddTempRegister, /*InsnID*/8, /*TempRegID*/7, /*TempRegFlags*/GIMT_Encode2(RegState::Define),
        GIR_AddSimpleTempRegister, /*InsnID*/8, /*TempRegID*/8,
        GIR_AddSimpleTempRegister, /*InsnID*/8, /*TempRegID*/9,
        GIR_ConstrainSelectedInstOperands, /*InsnID*/8,
        GIR_BuildMI, /*InsnID*/7, /*Opcode*/GIMT_Encode2(AMDGPU::V_BFI_B32_e64),
        GIR_AddTempRegister, /*InsnID*/7, /*TempRegID*/6, /*TempRegFlags*/GIMT_Encode2(RegState::Define),
        GIR_AddSimpleTempRegister, /*InsnID*/7, /*TempRegID*/7,
        GIR_AddSimpleTempRegister, /*InsnID*/7, /*TempRegID*/10,
        GIR_AddSimpleTempRegister, /*InsnID*/7, /*TempRegID*/11,
        GIR_ConstrainSelectedInstOperands, /*InsnID*/7,
        GIR_BuildMI, /*InsnID*/6, /*Opcode*/GIMT_Encode2(TargetOpcode::COPY),
        GIR_AddTempRegister, /*InsnID*/6, /*TempRegID*/5, /*TempRegFlags*/GIMT_Encode2(RegState::Define),
        GIR_CopySubReg, /*NewInsnID*/6, /*OldInsnID*/2, /*OpIdx*/1, /*SubRegIdx*/GIMT_Encode2(3), // y
        GIR_ConstrainOperandRC, /*InsnID*/6, /*Op*/0, GIMT_Encode2(AMDGPU::VGPR_32RegClassID),
        GIR_ConstrainOperandRC, /*InsnID*/6, /*Op*/1, GIMT_Encode2(AMDGPU::VReg_64RegClassID),
        GIR_BuildMI, /*InsnID*/5, /*Opcode*/GIMT_Encode2(TargetOpcode::COPY),
        GIR_AddTempRegister, /*InsnID*/5, /*TempRegID*/4, /*TempRegFlags*/GIMT_Encode2(RegState::Define),
        GIR_CopySubReg, /*NewInsnID*/5, /*OldInsnID*/1, /*OpIdx*/2, /*SubRegIdx*/GIMT_Encode2(3), // z
        GIR_ConstrainOperandRC, /*InsnID*/5, /*Op*/0, GIMT_Encode2(AMDGPU::VGPR_32RegClassID),
        GIR_ConstrainOperandRC, /*InsnID*/5, /*Op*/1, GIMT_Encode2(AMDGPU::VReg_64RegClassID),
        GIR_BuildMI, /*InsnID*/4, /*Opcode*/GIMT_Encode2(TargetOpcode::COPY),
        GIR_AddTempRegister, /*InsnID*/4, /*TempRegID*/3, /*TempRegFlags*/GIMT_Encode2(RegState::Define),
        GIR_CopySubReg, /*NewInsnID*/4, /*OldInsnID*/2, /*OpIdx*/1, /*SubRegIdx*/GIMT_Encode2(3), // y
        GIR_ConstrainOperandRC, /*InsnID*/4, /*Op*/0, GIMT_Encode2(AMDGPU::VGPR_32RegClassID),
        GIR_ConstrainOperandRC, /*InsnID*/4, /*Op*/1, GIMT_Encode2(AMDGPU::VReg_64RegClassID),
        GIR_BuildMI, /*InsnID*/3, /*Opcode*/GIMT_Encode2(TargetOpcode::COPY),
        GIR_AddTempRegister, /*InsnID*/3, /*TempRegID*/2, /*TempRegFlags*/GIMT_Encode2(RegState::Define),
        GIR_CopySubReg, /*NewInsnID*/3, /*OldInsnID*/1, /*OpIdx*/1, /*SubRegIdx*/GIMT_Encode2(3), // x
        GIR_ConstrainOperandRC, /*InsnID*/3, /*Op*/0, GIMT_Encode2(AMDGPU::VGPR_32RegClassID),
        GIR_ConstrainOperandRC, /*InsnID*/3, /*Op*/1, GIMT_Encode2(AMDGPU::VReg_64RegClassID),
        GIR_BuildMI, /*InsnID*/2, /*Opcode*/GIMT_Encode2(AMDGPU::V_XOR_B32_e64),
        GIR_AddTempRegister, /*InsnID*/2, /*TempRegID*/1, /*TempRegFlags*/GIMT_Encode2(RegState::Define),
        GIR_AddSimpleTempRegister, /*InsnID*/2, /*TempRegID*/2,
        GIR_AddSimpleTempRegister, /*InsnID*/2, /*TempRegID*/3,
        GIR_ConstrainSelectedInstOperands, /*InsnID*/2,
        GIR_BuildMI, /*InsnID*/1, /*Opcode*/GIMT_Encode2(AMDGPU::V_BFI_B32_e64),
        GIR_AddTempRegister, /*InsnID*/1, /*TempRegID*/0, /*TempRegFlags*/GIMT_Encode2(RegState::Define),
        GIR_AddSimpleTempRegister, /*InsnID*/1, /*TempRegID*/1,
        GIR_AddSimpleTempRegister, /*InsnID*/1, /*TempRegID*/4,
        GIR_AddSimpleTempRegister, /*InsnID*/1, /*TempRegID*/5,
        GIR_ConstrainSelectedInstOperands, /*InsnID*/1,
        GIR_BuildMI, /*InsnID*/0, /*Opcode*/GIMT_Encode2(TargetOpcode::REG_SEQUENCE),
        GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/0, // DstI[dst]
        GIR_AddSimpleTempRegister, /*InsnID*/0, /*TempRegID*/0,
        GIR_AddImm8, /*InsnID*/0, /*SubRegIndex*/3,
        GIR_AddSimpleTempRegister, /*InsnID*/0, /*TempRegID*/6,
        GIR_AddImm8, /*InsnID*/0, /*SubRegIndex*/11,
        GIR_ConstrainOperandRC, /*InsnID*/0, /*Op*/0, GIMT_Encode2(AMDGPU::VReg_64RegClassID),
        GIR_ConstrainOperandRC, /*InsnID*/0, /*Op*/1, GIMT_Encode2(AMDGPU::VGPR_32RegClassID),
        GIR_ConstrainOperandRC, /*InsnID*/0, /*Op*/3, GIMT_Encode2(AMDGPU::VGPR_32RegClassID),
        GIR_EraseFromParent, /*InsnID*/0,
        // GIR_Coverage, 9925,
        GIR_Done,
      // Label 358: @32886
      GIM_Try, /*On fail goto*//*Label 359*/ GIMT_Encode4(33304), // Rule ID 9928 //
        GIM_CheckRegBankForClass, /*MI*/0, /*Op*/0, /*RC*/GIMT_Encode2(AMDGPU::VReg_64RegClassID),
        GIM_RecordInsnIgnoreCopies, /*DefineMI*/1, /*MI*/0, /*OpIdx*/1, // MIs[1]
        GIM_CheckOpcode, /*MI*/1, GIMT_Encode2(TargetOpcode::G_AND),
        GIM_CheckType, /*MI*/1, /*Op*/1, /*Type*/GILLT_s64,
        GIM_CheckType, /*MI*/1, /*Op*/2, /*Type*/GILLT_s64,
        GIM_RecordInsnIgnoreCopies, /*DefineMI*/2, /*MI*/0, /*OpIdx*/2, // MIs[2]
        GIM_CheckOpcode, /*MI*/2, GIMT_Encode2(TargetOpcode::G_AND),
        GIM_CheckType, /*MI*/2, /*Op*/1, /*Type*/GILLT_s64,
        GIM_CheckType, /*MI*/2, /*Op*/2, /*Type*/GILLT_s64,
        GIM_RecordInsnIgnoreCopies, /*DefineMI*/3, /*MI*/2, /*OpIdx*/2, // MIs[3]
        GIM_CheckOpcode, /*MI*/3, GIMT_Encode2(TargetOpcode::G_OR),
        // MIs[3] x
        GIM_CheckIsSameOperandIgnoreCopies, /*MI*/3, /*OpIdx*/1, /*OtherMI*/1, /*OtherOpIdx*/2,
        // MIs[3] z
        GIM_CheckIsSameOperandIgnoreCopies, /*MI*/3, /*OpIdx*/2, /*OtherMI*/1, /*OtherOpIdx*/1,
        GIM_CheckCxxInsnPredicate, /*MI*/0, /*FnId*/GIMT_Encode2(GICXXPred_MI_Predicate_anonymous_22557),
        GIM_CheckIsSafeToFold, /*InsnID*/1,
        GIM_CheckIsSafeToFold, /*InsnID*/2,
        GIM_CheckIsSafeToFold, /*InsnID*/3,
        // (or:{ *:[i64] } (and:{ *:[i64] } i64:{ *:[i64] }:$z, i64:{ *:[i64] }:$x), (and:{ *:[i64] } i64:{ *:[i64] }:$y, (or:{ *:[i64] } i64:{ *:[i64] }:$x, i64:{ *:[i64] }:$z)))<<P:Predicate_anonymous_22557>>  =>  (REG_SEQUENCE:{ *:[i64] } VReg_64:{ *:[i32] }, (V_BFI_B32_e64:{ *:[i16] } (V_XOR_B32_e64:{ *:[i16] } (EXTRACT_SUBREG:{ *:[i32] } VReg_64:{ *:[i64] }:$x, sub0:{ *:[i32] }), (EXTRACT_SUBREG:{ *:[i32] } VReg_64:{ *:[i64] }:$y, sub0:{ *:[i32] })), (EXTRACT_SUBREG:{ *:[i32] } VReg_64:{ *:[i64] }:$z, sub0:{ *:[i32] }), (EXTRACT_SUBREG:{ *:[i32] } VReg_64:{ *:[i64] }:$y, sub0:{ *:[i32] })), sub0:{ *:[i32] }, (V_BFI_B32_e64:{ *:[i16] } (V_XOR_B32_e64:{ *:[i16] } (EXTRACT_SUBREG:{ *:[i32] } VReg_64:{ *:[i64] }:$x, sub1:{ *:[i32] }), (EXTRACT_SUBREG:{ *:[i32] } VReg_64:{ *:[i64] }:$y, sub1:{ *:[i32] })), (EXTRACT_SUBREG:{ *:[i32] } VReg_64:{ *:[i64] }:$z, sub1:{ *:[i32] }), (EXTRACT_SUBREG:{ *:[i32] } VReg_64:{ *:[i64] }:$y, sub1:{ *:[i32] })), sub1:{ *:[i32] })
        GIR_MakeTempReg, /*TempRegID*/0, /*TypeID*/GILLT_s16,
        GIR_MakeTempReg, /*TempRegID*/1, /*TypeID*/GILLT_s16,
        GIR_MakeTempReg, /*TempRegID*/2, /*TypeID*/GILLT_s32,
        GIR_MakeTempReg, /*TempRegID*/3, /*TypeID*/GILLT_s32,
        GIR_MakeTempReg, /*TempRegID*/4, /*TypeID*/GILLT_s32,
        GIR_MakeTempReg, /*TempRegID*/5, /*TypeID*/GILLT_s32,
        GIR_MakeTempReg, /*TempRegID*/6, /*TypeID*/GILLT_s16,
        GIR_MakeTempReg, /*TempRegID*/7, /*TypeID*/GILLT_s16,
        GIR_MakeTempReg, /*TempRegID*/8, /*TypeID*/GILLT_s32,
        GIR_MakeTempReg, /*TempRegID*/9, /*TypeID*/GILLT_s32,
        GIR_MakeTempReg, /*TempRegID*/10, /*TypeID*/GILLT_s32,
        GIR_MakeTempReg, /*TempRegID*/11, /*TypeID*/GILLT_s32,
        GIR_BuildMI, /*InsnID*/12, /*Opcode*/GIMT_Encode2(TargetOpcode::COPY),
        GIR_AddTempRegister, /*InsnID*/12, /*TempRegID*/11, /*TempRegFlags*/GIMT_Encode2(RegState::Define),
        GIR_CopySubReg, /*NewInsnID*/12, /*OldInsnID*/2, /*OpIdx*/1, /*SubRegIdx*/GIMT_Encode2(11), // y
        GIR_ConstrainOperandRC, /*InsnID*/12, /*Op*/0, GIMT_Encode2(AMDGPU::VGPR_32RegClassID),
        GIR_ConstrainOperandRC, /*InsnID*/12, /*Op*/1, GIMT_Encode2(AMDGPU::VReg_64RegClassID),
        GIR_BuildMI, /*InsnID*/11, /*Opcode*/GIMT_Encode2(TargetOpcode::COPY),
        GIR_AddTempRegister, /*InsnID*/11, /*TempRegID*/10, /*TempRegFlags*/GIMT_Encode2(RegState::Define),
        GIR_CopySubReg, /*NewInsnID*/11, /*OldInsnID*/1, /*OpIdx*/1, /*SubRegIdx*/GIMT_Encode2(11), // z
        GIR_ConstrainOperandRC, /*InsnID*/11, /*Op*/0, GIMT_Encode2(AMDGPU::VGPR_32RegClassID),
        GIR_ConstrainOperandRC, /*InsnID*/11, /*Op*/1, GIMT_Encode2(AMDGPU::VReg_64RegClassID),
        GIR_BuildMI, /*InsnID*/10, /*Opcode*/GIMT_Encode2(TargetOpcode::COPY),
        GIR_AddTempRegister, /*InsnID*/10, /*TempRegID*/9, /*TempRegFlags*/GIMT_Encode2(RegState::Define),
        GIR_CopySubReg, /*NewInsnID*/10, /*OldInsnID*/2, /*OpIdx*/1, /*SubRegIdx*/GIMT_Encode2(11), // y
        GIR_ConstrainOperandRC, /*InsnID*/10, /*Op*/0, GIMT_Encode2(AMDGPU::VGPR_32RegClassID),
        GIR_ConstrainOperandRC, /*InsnID*/10, /*Op*/1, GIMT_Encode2(AMDGPU::VReg_64RegClassID),
        GIR_BuildMI, /*InsnID*/9, /*Opcode*/GIMT_Encode2(TargetOpcode::COPY),
        GIR_AddTempRegister, /*InsnID*/9, /*TempRegID*/8, /*TempRegFlags*/GIMT_Encode2(RegState::Define),
        GIR_CopySubReg, /*NewInsnID*/9, /*OldInsnID*/1, /*OpIdx*/2, /*SubRegIdx*/GIMT_Encode2(11), // x
        GIR_ConstrainOperandRC, /*InsnID*/9, /*Op*/0, GIMT_Encode2(AMDGPU::VGPR_32RegClassID),
        GIR_ConstrainOperandRC, /*InsnID*/9, /*Op*/1, GIMT_Encode2(AMDGPU::VReg_64RegClassID),
        GIR_BuildMI, /*InsnID*/8, /*Opcode*/GIMT_Encode2(AMDGPU::V_XOR_B32_e64),
        GIR_AddTempRegister, /*InsnID*/8, /*TempRegID*/7, /*TempRegFlags*/GIMT_Encode2(RegState::Define),
        GIR_AddSimpleTempRegister, /*InsnID*/8, /*TempRegID*/8,
        GIR_AddSimpleTempRegister, /*InsnID*/8, /*TempRegID*/9,
        GIR_ConstrainSelectedInstOperands, /*InsnID*/8,
        GIR_BuildMI, /*InsnID*/7, /*Opcode*/GIMT_Encode2(AMDGPU::V_BFI_B32_e64),
        GIR_AddTempRegister, /*InsnID*/7, /*TempRegID*/6, /*TempRegFlags*/GIMT_Encode2(RegState::Define),
        GIR_AddSimpleTempRegister, /*InsnID*/7, /*TempRegID*/7,
        GIR_AddSimpleTempRegister, /*InsnID*/7, /*TempRegID*/10,
        GIR_AddSimpleTempRegister, /*InsnID*/7, /*TempRegID*/11,
        GIR_ConstrainSelectedInstOperands, /*InsnID*/7,
        GIR_BuildMI, /*InsnID*/6, /*Opcode*/GIMT_Encode2(TargetOpcode::COPY),
        GIR_AddTempRegister, /*InsnID*/6, /*TempRegID*/5, /*TempRegFlags*/GIMT_Encode2(RegState::Define),
        GIR_CopySubReg, /*NewInsnID*/6, /*OldInsnID*/2, /*OpIdx*/1, /*SubRegIdx*/GIMT_Encode2(3), // y
        GIR_ConstrainOperandRC, /*InsnID*/6, /*Op*/0, GIMT_Encode2(AMDGPU::VGPR_32RegClassID),
        GIR_ConstrainOperandRC, /*InsnID*/6, /*Op*/1, GIMT_Encode2(AMDGPU::VReg_64RegClassID),
        GIR_BuildMI, /*InsnID*/5, /*Opcode*/GIMT_Encode2(TargetOpcode::COPY),
        GIR_AddTempRegister, /*InsnID*/5, /*TempRegID*/4, /*TempRegFlags*/GIMT_Encode2(RegState::Define),
        GIR_CopySubReg, /*NewInsnID*/5, /*OldInsnID*/1, /*OpIdx*/1, /*SubRegIdx*/GIMT_Encode2(3), // z
        GIR_ConstrainOperandRC, /*InsnID*/5, /*Op*/0, GIMT_Encode2(AMDGPU::VGPR_32RegClassID),
        GIR_ConstrainOperandRC, /*InsnID*/5, /*Op*/1, GIMT_Encode2(AMDGPU::VReg_64RegClassID),
        GIR_BuildMI, /*InsnID*/4, /*Opcode*/GIMT_Encode2(TargetOpcode::COPY),
        GIR_AddTempRegister, /*InsnID*/4, /*TempRegID*/3, /*TempRegFlags*/GIMT_Encode2(RegState::Define),
        GIR_CopySubReg, /*NewInsnID*/4, /*OldInsnID*/2, /*OpIdx*/1, /*SubRegIdx*/GIMT_Encode2(3), // y
        GIR_ConstrainOperandRC, /*InsnID*/4, /*Op*/0, GIMT_Encode2(AMDGPU::VGPR_32RegClassID),
        GIR_ConstrainOperandRC, /*InsnID*/4, /*Op*/1, GIMT_Encode2(AMDGPU::VReg_64RegClassID),
        GIR_BuildMI, /*InsnID*/3, /*Opcode*/GIMT_Encode2(TargetOpcode::COPY),
        GIR_AddTempRegister, /*InsnID*/3, /*TempRegID*/2, /*TempRegFlags*/GIMT_Encode2(RegState::Define),
        GIR_CopySubReg, /*NewInsnID*/3, /*OldInsnID*/1, /*OpIdx*/2, /*SubRegIdx*/GIMT_Encode2(3), // x
        GIR_ConstrainOperandRC, /*InsnID*/3, /*Op*/0, GIMT_Encode2(AMDGPU::VGPR_32RegClassID),
        GIR_ConstrainOperandRC, /*InsnID*/3, /*Op*/1, GIMT_Encode2(AMDGPU::VReg_64RegClassID),
        GIR_BuildMI, /*InsnID*/2, /*Opcode*/GIMT_Encode2(AMDGPU::V_XOR_B32_e64),
        GIR_AddTempRegister, /*InsnID*/2, /*TempRegID*/1, /*TempRegFlags*/GIMT_Encode2(RegState::Define),
        GIR_AddSimpleTempRegister, /*InsnID*/2, /*TempRegID*/2,
        GIR_AddSimpleTempRegister, /*InsnID*/2, /*TempRegID*/3,
        GIR_ConstrainSelectedInstOperands, /*InsnID*/2,
        GIR_BuildMI, /*InsnID*/1, /*Opcode*/GIMT_Encode2(AMDGPU::V_BFI_B32_e64),
        GIR_AddTempRegister, /*InsnID*/1, /*TempRegID*/0, /*TempRegFlags*/GIMT_Encode2(RegState::Define),
        GIR_AddSimpleTempRegister, /*InsnID*/1, /*TempRegID*/1,
        GIR_AddSimpleTempRegister, /*InsnID*/1, /*TempRegID*/4,
        GIR_AddSimpleTempRegister, /*InsnID*/1, /*TempRegID*/5,
        GIR_ConstrainSelectedInstOperands, /*InsnID*/1,
        GIR_BuildMI, /*InsnID*/0, /*Opcode*/GIMT_Encode2(TargetOpcode::REG_SEQUENCE),
        GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/0, // DstI[dst]
        GIR_AddSimpleTempRegister, /*InsnID*/0, /*TempRegID*/0,
        GIR_AddImm8, /*InsnID*/0, /*SubRegIndex*/3,
        GIR_AddSimpleTempRegister, /*InsnID*/0, /*TempRegID*/6,
        GIR_AddImm8, /*InsnID*/0, /*SubRegIndex*/11,
        GIR_ConstrainOperandRC, /*InsnID*/0, /*Op*/0, GIMT_Encode2(AMDGPU::VReg_64RegClassID),
        GIR_ConstrainOperandRC, /*InsnID*/0, /*Op*/1, GIMT_Encode2(AMDGPU::VGPR_32RegClassID),
        GIR_ConstrainOperandRC, /*InsnID*/0, /*Op*/3, GIMT_Encode2(AMDGPU::VGPR_32RegClassID),
        GIR_EraseFromParent, /*InsnID*/0,
        // GIR_Coverage, 9928,
        GIR_Done,
      // Label 359: @33304
      GIM_Try, /*On fail goto*//*Label 360*/ GIMT_Encode4(33722), // Rule ID 9929 //
        GIM_CheckRegBankForClass, /*MI*/0, /*Op*/0, /*RC*/GIMT_Encode2(AMDGPU::VReg_64RegClassID),
        GIM_RecordInsnIgnoreCopies, /*DefineMI*/1, /*MI*/0, /*OpIdx*/1, // MIs[1]
        GIM_CheckOpcode, /*MI*/1, GIMT_Encode2(TargetOpcode::G_AND),
        GIM_CheckType, /*MI*/1, /*Op*/1, /*Type*/GILLT_s64,
        GIM_CheckType, /*MI*/1, /*Op*/2, /*Type*/GILLT_s64,
        GIM_RecordInsnIgnoreCopies, /*DefineMI*/2, /*MI*/0, /*OpIdx*/2, // MIs[2]
        GIM_CheckOpcode, /*MI*/2, GIMT_Encode2(TargetOpcode::G_AND),
        GIM_CheckType, /*MI*/2, /*Op*/1, /*Type*/GILLT_s64,
        GIM_CheckType, /*MI*/2, /*Op*/2, /*Type*/GILLT_s64,
        GIM_RecordInsnIgnoreCopies, /*DefineMI*/3, /*MI*/2, /*OpIdx*/2, // MIs[3]
        GIM_CheckOpcode, /*MI*/3, GIMT_Encode2(TargetOpcode::G_OR),
        // MIs[3] z
        GIM_CheckIsSameOperandIgnoreCopies, /*MI*/3, /*OpIdx*/1, /*OtherMI*/1, /*OtherOpIdx*/1,
        // MIs[3] x
        GIM_CheckIsSameOperandIgnoreCopies, /*MI*/3, /*OpIdx*/2, /*OtherMI*/1, /*OtherOpIdx*/2,
        GIM_CheckCxxInsnPredicate, /*MI*/0, /*FnId*/GIMT_Encode2(GICXXPred_MI_Predicate_anonymous_22557),
        GIM_CheckIsSafeToFold, /*InsnID*/1,
        GIM_CheckIsSafeToFold, /*InsnID*/2,
        GIM_CheckIsSafeToFold, /*InsnID*/3,
        // (or:{ *:[i64] } (and:{ *:[i64] } i64:{ *:[i64] }:$z, i64:{ *:[i64] }:$x), (and:{ *:[i64] } i64:{ *:[i64] }:$y, (or:{ *:[i64] } i64:{ *:[i64] }:$z, i64:{ *:[i64] }:$x)))<<P:Predicate_anonymous_22557>>  =>  (REG_SEQUENCE:{ *:[i64] } VReg_64:{ *:[i32] }, (V_BFI_B32_e64:{ *:[i16] } (V_XOR_B32_e64:{ *:[i16] } (EXTRACT_SUBREG:{ *:[i32] } VReg_64:{ *:[i64] }:$x, sub0:{ *:[i32] }), (EXTRACT_SUBREG:{ *:[i32] } VReg_64:{ *:[i64] }:$y, sub0:{ *:[i32] })), (EXTRACT_SUBREG:{ *:[i32] } VReg_64:{ *:[i64] }:$z, sub0:{ *:[i32] }), (EXTRACT_SUBREG:{ *:[i32] } VReg_64:{ *:[i64] }:$y, sub0:{ *:[i32] })), sub0:{ *:[i32] }, (V_BFI_B32_e64:{ *:[i16] } (V_XOR_B32_e64:{ *:[i16] } (EXTRACT_SUBREG:{ *:[i32] } VReg_64:{ *:[i64] }:$x, sub1:{ *:[i32] }), (EXTRACT_SUBREG:{ *:[i32] } VReg_64:{ *:[i64] }:$y, sub1:{ *:[i32] })), (EXTRACT_SUBREG:{ *:[i32] } VReg_64:{ *:[i64] }:$z, sub1:{ *:[i32] }), (EXTRACT_SUBREG:{ *:[i32] } VReg_64:{ *:[i64] }:$y, sub1:{ *:[i32] })), sub1:{ *:[i32] })
        GIR_MakeTempReg, /*TempRegID*/0, /*TypeID*/GILLT_s16,
        GIR_MakeTempReg, /*TempRegID*/1, /*TypeID*/GILLT_s16,
        GIR_MakeTempReg, /*TempRegID*/2, /*TypeID*/GILLT_s32,
        GIR_MakeTempReg, /*TempRegID*/3, /*TypeID*/GILLT_s32,
        GIR_MakeTempReg, /*TempRegID*/4, /*TypeID*/GILLT_s32,
        GIR_MakeTempReg, /*TempRegID*/5, /*TypeID*/GILLT_s32,
        GIR_MakeTempReg, /*TempRegID*/6, /*TypeID*/GILLT_s16,
        GIR_MakeTempReg, /*TempRegID*/7, /*TypeID*/GILLT_s16,
        GIR_MakeTempReg, /*TempRegID*/8, /*TypeID*/GILLT_s32,
        GIR_MakeTempReg, /*TempRegID*/9, /*TypeID*/GILLT_s32,
        GIR_MakeTempReg, /*TempRegID*/10, /*TypeID*/GILLT_s32,
        GIR_MakeTempReg, /*TempRegID*/11, /*TypeID*/GILLT_s32,
        GIR_BuildMI, /*InsnID*/12, /*Opcode*/GIMT_Encode2(TargetOpcode::COPY),
        GIR_AddTempRegister, /*InsnID*/12, /*TempRegID*/11, /*TempRegFlags*/GIMT_Encode2(RegState::Define),
        GIR_CopySubReg, /*NewInsnID*/12, /*OldInsnID*/2, /*OpIdx*/1, /*SubRegIdx*/GIMT_Encode2(11), // y
        GIR_ConstrainOperandRC, /*InsnID*/12, /*Op*/0, GIMT_Encode2(AMDGPU::VGPR_32RegClassID),
        GIR_ConstrainOperandRC, /*InsnID*/12, /*Op*/1, GIMT_Encode2(AMDGPU::VReg_64RegClassID),
        GIR_BuildMI, /*InsnID*/11, /*Opcode*/GIMT_Encode2(TargetOpcode::COPY),
        GIR_AddTempRegister, /*InsnID*/11, /*TempRegID*/10, /*TempRegFlags*/GIMT_Encode2(RegState::Define),
        GIR_CopySubReg, /*NewInsnID*/11, /*OldInsnID*/1, /*OpIdx*/1, /*SubRegIdx*/GIMT_Encode2(11), // z
        GIR_ConstrainOperandRC, /*InsnID*/11, /*Op*/0, GIMT_Encode2(AMDGPU::VGPR_32RegClassID),
        GIR_ConstrainOperandRC, /*InsnID*/11, /*Op*/1, GIMT_Encode2(AMDGPU::VReg_64RegClassID),
        GIR_BuildMI, /*InsnID*/10, /*Opcode*/GIMT_Encode2(TargetOpcode::COPY),
        GIR_AddTempRegister, /*InsnID*/10, /*TempRegID*/9, /*TempRegFlags*/GIMT_Encode2(RegState::Define),
        GIR_CopySubReg, /*NewInsnID*/10, /*OldInsnID*/2, /*OpIdx*/1, /*SubRegIdx*/GIMT_Encode2(11), // y
        GIR_ConstrainOperandRC, /*InsnID*/10, /*Op*/0, GIMT_Encode2(AMDGPU::VGPR_32RegClassID),
        GIR_ConstrainOperandRC, /*InsnID*/10, /*Op*/1, GIMT_Encode2(AMDGPU::VReg_64RegClassID),
        GIR_BuildMI, /*InsnID*/9, /*Opcode*/GIMT_Encode2(TargetOpcode::COPY),
        GIR_AddTempRegister, /*InsnID*/9, /*TempRegID*/8, /*TempRegFlags*/GIMT_Encode2(RegState::Define),
        GIR_CopySubReg, /*NewInsnID*/9, /*OldInsnID*/1, /*OpIdx*/2, /*SubRegIdx*/GIMT_Encode2(11), // x
        GIR_ConstrainOperandRC, /*InsnID*/9, /*Op*/0, GIMT_Encode2(AMDGPU::VGPR_32RegClassID),
        GIR_ConstrainOperandRC, /*InsnID*/9, /*Op*/1, GIMT_Encode2(AMDGPU::VReg_64RegClassID),
        GIR_BuildMI, /*InsnID*/8, /*Opcode*/GIMT_Encode2(AMDGPU::V_XOR_B32_e64),
        GIR_AddTempRegister, /*InsnID*/8, /*TempRegID*/7, /*TempRegFlags*/GIMT_Encode2(RegState::Define),
        GIR_AddSimpleTempRegister, /*InsnID*/8, /*TempRegID*/8,
        GIR_AddSimpleTempRegister, /*InsnID*/8, /*TempRegID*/9,
        GIR_ConstrainSelectedInstOperands, /*InsnID*/8,
        GIR_BuildMI, /*InsnID*/7, /*Opcode*/GIMT_Encode2(AMDGPU::V_BFI_B32_e64),
        GIR_AddTempRegister, /*InsnID*/7, /*TempRegID*/6, /*TempRegFlags*/GIMT_Encode2(RegState::Define),
        GIR_AddSimpleTempRegister, /*InsnID*/7, /*TempRegID*/7,
        GIR_AddSimpleTempRegister, /*InsnID*/7, /*TempRegID*/10,
        GIR_AddSimpleTempRegister, /*InsnID*/7, /*TempRegID*/11,
        GIR_ConstrainSelectedInstOperands, /*InsnID*/7,
        GIR_BuildMI, /*InsnID*/6, /*Opcode*/GIMT_Encode2(TargetOpcode::COPY),
        GIR_AddTempRegister, /*InsnID*/6, /*TempRegID*/5, /*TempRegFlags*/GIMT_Encode2(RegState::Define),
        GIR_CopySubReg, /*NewInsnID*/6, /*OldInsnID*/2, /*OpIdx*/1, /*SubRegIdx*/GIMT_Encode2(3), // y
        GIR_ConstrainOperandRC, /*InsnID*/6, /*Op*/0, GIMT_Encode2(AMDGPU::VGPR_32RegClassID),
        GIR_ConstrainOperandRC, /*InsnID*/6, /*Op*/1, GIMT_Encode2(AMDGPU::VReg_64RegClassID),
        GIR_BuildMI, /*InsnID*/5, /*Opcode*/GIMT_Encode2(TargetOpcode::COPY),
        GIR_AddTempRegister, /*InsnID*/5, /*TempRegID*/4, /*TempRegFlags*/GIMT_Encode2(RegState::Define),
        GIR_CopySubReg, /*NewInsnID*/5, /*OldInsnID*/1, /*OpIdx*/1, /*SubRegIdx*/GIMT_Encode2(3), // z
        GIR_ConstrainOperandRC, /*InsnID*/5, /*Op*/0, GIMT_Encode2(AMDGPU::VGPR_32RegClassID),
        GIR_ConstrainOperandRC, /*InsnID*/5, /*Op*/1, GIMT_Encode2(AMDGPU::VReg_64RegClassID),
        GIR_BuildMI, /*InsnID*/4, /*Opcode*/GIMT_Encode2(TargetOpcode::COPY),
        GIR_AddTempRegister, /*InsnID*/4, /*TempRegID*/3, /*TempRegFlags*/GIMT_Encode2(RegState::Define),
        GIR_CopySubReg, /*NewInsnID*/4, /*OldInsnID*/2, /*OpIdx*/1, /*SubRegIdx*/GIMT_Encode2(3), // y
        GIR_ConstrainOperandRC, /*InsnID*/4, /*Op*/0, GIMT_Encode2(AMDGPU::VGPR_32RegClassID),
        GIR_ConstrainOperandRC, /*InsnID*/4, /*Op*/1, GIMT_Encode2(AMDGPU::VReg_64RegClassID),
        GIR_BuildMI, /*InsnID*/3, /*Opcode*/GIMT_Encode2(TargetOpcode::COPY),
        GIR_AddTempRegister, /*InsnID*/3, /*TempRegID*/2, /*TempRegFlags*/GIMT_Encode2(RegState::Define),
        GIR_CopySubReg, /*NewInsnID*/3, /*OldInsnID*/1, /*OpIdx*/2, /*SubRegIdx*/GIMT_Encode2(3), // x
        GIR_ConstrainOperandRC, /*InsnID*/3, /*Op*/0, GIMT_Encode2(AMDGPU::VGPR_32RegClassID),
        GIR_ConstrainOperandRC, /*InsnID*/3, /*Op*/1, GIMT_Encode2(AMDGPU::VReg_64RegClassID),
        GIR_BuildMI, /*InsnID*/2, /*Opcode*/GIMT_Encode2(AMDGPU::V_XOR_B32_e64),
        GIR_AddTempRegister, /*InsnID*/2, /*TempRegID*/1, /*TempRegFlags*/GIMT_Encode2(RegState::Define),
        GIR_AddSimpleTempRegister, /*InsnID*/2, /*TempRegID*/2,
        GIR_AddSimpleTempRegister, /*InsnID*/2, /*TempRegID*/3,
        GIR_ConstrainSelectedInstOperands, /*InsnID*/2,
        GIR_BuildMI, /*InsnID*/1, /*Opcode*/GIMT_Encode2(AMDGPU::V_BFI_B32_e64),
        GIR_AddTempRegister, /*InsnID*/1, /*TempRegID*/0, /*TempRegFlags*/GIMT_Encode2(RegState::Define),
        GIR_AddSimpleTempRegister, /*InsnID*/1, /*TempRegID*/1,
        GIR_AddSimpleTempRegister, /*InsnID*/1, /*TempRegID*/4,
        GIR_AddSimpleTempRegister, /*InsnID*/1, /*TempRegID*/5,
        GIR_ConstrainSelectedInstOperands, /*InsnID*/1,
        GIR_BuildMI, /*InsnID*/0, /*Opcode*/GIMT_Encode2(TargetOpcode::REG_SEQUENCE),
        GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/0, // DstI[dst]
        GIR_AddSimpleTempRegister, /*InsnID*/0, /*TempRegID*/0,
        GIR_AddImm8, /*InsnID*/0, /*SubRegIndex*/3,
        GIR_AddSimpleTempRegister, /*InsnID*/0, /*TempRegID*/6,
        GIR_AddImm8, /*InsnID*/0, /*SubRegIndex*/11,
        GIR_ConstrainOperandRC, /*InsnID*/0, /*Op*/0, GIMT_Encode2(AMDGPU::VReg_64RegClassID),
        GIR_ConstrainOperandRC, /*InsnID*/0, /*Op*/1, GIMT_Encode2(AMDGPU::VGPR_32RegClassID),
        GIR_ConstrainOperandRC, /*InsnID*/0, /*Op*/3, GIMT_Encode2(AMDGPU::VGPR_32RegClassID),
        GIR_EraseFromParent, /*InsnID*/0,
        // GIR_Coverage, 9929,
        GIR_Done,
      // Label 360: @33722
      GIM_Try, /*On fail goto*//*Label 361*/ GIMT_Encode4(33786), // Rule ID 7119 //
        GIM_CheckRegBankForClass, /*MI*/0, /*Op*/0, /*RC*/GIMT_Encode2(AMDGPU::SReg_64RegClassID),
        GIM_RecordInsn, /*DefineMI*/1, /*MI*/0, /*OpIdx*/1, // MIs[1]
        GIM_CheckOpcode, /*MI*/1, GIMT_Encode2(TargetOpcode::G_XOR),
        GIM_CheckType, /*MI*/1, /*Op*/1, /*Type*/GILLT_s64,
        GIM_CheckType, /*MI*/1, /*Op*/2, /*Type*/GILLT_s64,
        GIM_CheckConstantInt8, /*MI*/1, /*Op*/2, uint8_t(-1),
        GIM_CheckCxxInsnPredicate, /*MI*/1, /*FnId*/GIMT_Encode2(GICXXPred_MI_Predicate_anonymous_17562),
        GIM_CheckCxxInsnPredicate, /*MI*/0, /*FnId*/GIMT_Encode2(GICXXPred_MI_Predicate_anonymous_17616),
        GIM_CheckIsSafeToFold, /*InsnID*/1,
        // (or:{ *:[i64] } (xor:{ *:[i64] } i64:{ *:[i64] }:$src1, -1:{ *:[i64] })<<P:Predicate_anonymous_17562>>, i64:{ *:[i64] }:$src0)<<P:Predicate_anonymous_17616>>  =>  (S_ORN2_B64:{ *:[i64] }:{ *:[i1] } i64:{ *:[i64] }:$src0, i64:{ *:[i64] }:$src1)
        GIR_BuildMI, /*InsnID*/0, /*Opcode*/GIMT_Encode2(AMDGPU::S_ORN2_B64),
        GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/0, // DstI[sdst]
        GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/2, // src0
        GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/1, /*OpIdx*/1, // src1
        GIR_SetImplicitDefDead, /*InsnID*/0, /*OpIdx for AMDGPU::SCC*/0,
        GIR_ConstrainSelectedInstOperands, /*InsnID*/0,
        GIR_EraseFromParent, /*InsnID*/0,
        // GIR_Coverage, 7119,
        GIR_Done,
      // Label 361: @33786
      GIM_Try, /*On fail goto*//*Label 362*/ GIMT_Encode4(33850), // Rule ID 69 //
        GIM_CheckRegBankForClass, /*MI*/0, /*Op*/0, /*RC*/GIMT_Encode2(AMDGPU::SReg_64RegClassID),
        GIM_RecordInsn, /*DefineMI*/1, /*MI*/0, /*OpIdx*/2, // MIs[1]
        GIM_CheckOpcode, /*MI*/1, GIMT_Encode2(TargetOpcode::G_XOR),
        GIM_CheckType, /*MI*/1, /*Op*/1, /*Type*/GILLT_s64,
        GIM_CheckType, /*MI*/1, /*Op*/2, /*Type*/GILLT_s64,
        GIM_CheckConstantInt8, /*MI*/1, /*Op*/2, uint8_t(-1),
        GIM_CheckCxxInsnPredicate, /*MI*/1, /*FnId*/GIMT_Encode2(GICXXPred_MI_Predicate_anonymous_17562),
        GIM_CheckCxxInsnPredicate, /*MI*/0, /*FnId*/GIMT_Encode2(GICXXPred_MI_Predicate_anonymous_17616),
        GIM_CheckIsSafeToFold, /*InsnID*/1,
        // (or:{ *:[i64] } i64:{ *:[i64] }:$src0, (xor:{ *:[i64] } i64:{ *:[i64] }:$src1, -1:{ *:[i64] })<<P:Predicate_anonymous_17562>>)<<P:Predicate_anonymous_17616>>  =>  (S_ORN2_B64:{ *:[i64] }:{ *:[i1] } i64:{ *:[i64] }:$src0, i64:{ *:[i64] }:$src1)
        GIR_BuildMI, /*InsnID*/0, /*Opcode*/GIMT_Encode2(AMDGPU::S_ORN2_B64),
        GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/0, // DstI[sdst]
        GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/1, // src0
        GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/1, /*OpIdx*/1, // src1
        GIR_SetImplicitDefDead, /*InsnID*/0, /*OpIdx for AMDGPU::SCC*/0,
        GIR_ConstrainSelectedInstOperands, /*InsnID*/0,
        GIR_EraseFromParent, /*InsnID*/0,
        // GIR_Coverage, 69,
        GIR_Done,
      // Label 362: @33850
      GIM_Try, /*On fail goto*//*Label 363*/ GIMT_Encode4(33878), // Rule ID 57 //
        GIM_CheckRegBankForClass, /*MI*/0, /*Op*/0, /*RC*/GIMT_Encode2(AMDGPU::SReg_64RegClassID),
        GIM_CheckCxxInsnPredicate, /*MI*/0, /*FnId*/GIMT_Encode2(GICXXPred_MI_Predicate_anonymous_17616),
        // (or:{ *:[i64] } i64:{ *:[i64] }:$src0, i64:{ *:[i64] }:$src1)<<P:Predicate_anonymous_17616>>  =>  (S_OR_B64:{ *:[i64] }:{ *:[i1] } i64:{ *:[i64] }:$src0, i64:{ *:[i64] }:$src1)
        GIR_MutateOpcode, /*InsnID*/0, /*RecycleInsnID*/0, /*Opcode*/GIMT_Encode2(AMDGPU::S_OR_B64),
        GIR_AddImplicitDef, /*InsnID*/0, GIMT_Encode2(AMDGPU::SCC), GIMT_Encode2(RegState::Dead),
        GIR_ConstrainSelectedInstOperands, /*InsnID*/0,
        // GIR_Coverage, 57,
        GIR_Done,
      // Label 363: @33878
      GIM_Reject,
    // Label 336: @33879
    GIM_Reject,
    // Label 287: @33880
    GIM_Try, /*On fail goto*//*Label 364*/ GIMT_Encode4(34064),
      GIM_CheckType, /*MI*/0, /*Op*/1, /*Type*/GILLT_v2s16,
      GIM_CheckType, /*MI*/0, /*Op*/2, /*Type*/GILLT_v2s16,
      GIM_Try, /*On fail goto*//*Label 365*/ GIMT_Encode4(33967), // Rule ID 7201 //
        GIM_CheckRegBankForClass, /*MI*/0, /*Op*/0, /*RC*/GIMT_Encode2(AMDGPU::SReg_32RegClassID),
        GIM_RecordInsn, /*DefineMI*/1, /*MI*/0, /*OpIdx*/1, // MIs[1]
        GIM_CheckOpcode, /*MI*/1, GIMT_Encode2(TargetOpcode::G_XOR),
        GIM_CheckType, /*MI*/1, /*Op*/1, /*Type*/GILLT_v2s16,
        GIM_CheckType, /*MI*/1, /*Op*/2, /*Type*/GILLT_v2s16,
        GIM_RecordInsn, /*DefineMI*/2, /*MI*/1, /*OpIdx*/2, // MIs[2]
        GIM_CheckOpcodeIsEither, /*MI*/2, GIMT_Encode2(TargetOpcode::G_BUILD_VECTOR), GIMT_Encode2(TargetOpcode::G_BUILD_VECTOR_TRUNC),
        GIM_CheckIsBuildVectorAllOnes, /*MI*/2,
        GIM_CheckCxxInsnPredicate, /*MI*/1, /*FnId*/GIMT_Encode2(GICXXPred_MI_Predicate_anonymous_17683),
        GIM_CheckCxxInsnPredicate, /*MI*/0, /*FnId*/GIMT_Encode2(GICXXPred_MI_Predicate_anonymous_17616),
        GIM_CheckIsSafeToFold, /*InsnID*/1,
        GIM_CheckIsSafeToFold, /*InsnID*/2,
        // (or:{ *:[v2i16] } (xor:{ *:[v2i16] } v2i16:{ *:[v2i16] }:$src1, immAllOnesV:{ *:[v2i16] })<<P:Predicate_anonymous_17683>>, v2i16:{ *:[v2i16] }:$src0)<<P:Predicate_anonymous_17616>>  =>  (S_ORN2_B32:{ *:[v2i16] }:{ *:[i1] } SSrc_b32:{ *:[v2i16] }:$src0, SSrc_b32:{ *:[v2i16] }:$src1)
        GIR_BuildMI, /*InsnID*/0, /*Opcode*/GIMT_Encode2(AMDGPU::S_ORN2_B32),
        GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/0, // DstI[sdst]
        GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/2, // src0
        GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/1, /*OpIdx*/1, // src1
        GIR_SetImplicitDefDead, /*InsnID*/0, /*OpIdx for AMDGPU::SCC*/0,
        GIR_ConstrainSelectedInstOperands, /*InsnID*/0,
        GIR_EraseFromParent, /*InsnID*/0,
        // GIR_Coverage, 7201,
        GIR_Done,
      // Label 365: @33967
      GIM_Try, /*On fail goto*//*Label 366*/ GIMT_Encode4(34041), // Rule ID 1663 //
        GIM_CheckRegBankForClass, /*MI*/0, /*Op*/0, /*RC*/GIMT_Encode2(AMDGPU::SReg_32RegClassID),
        GIM_RecordInsn, /*DefineMI*/1, /*MI*/0, /*OpIdx*/2, // MIs[1]
        GIM_CheckOpcode, /*MI*/1, GIMT_Encode2(TargetOpcode::G_XOR),
        GIM_CheckType, /*MI*/1, /*Op*/1, /*Type*/GILLT_v2s16,
        GIM_CheckType, /*MI*/1, /*Op*/2, /*Type*/GILLT_v2s16,
        GIM_RecordInsn, /*DefineMI*/2, /*MI*/1, /*OpIdx*/2, // MIs[2]
        GIM_CheckOpcodeIsEither, /*MI*/2, GIMT_Encode2(TargetOpcode::G_BUILD_VECTOR), GIMT_Encode2(TargetOpcode::G_BUILD_VECTOR_TRUNC),
        GIM_CheckIsBuildVectorAllOnes, /*MI*/2,
        GIM_CheckCxxInsnPredicate, /*MI*/1, /*FnId*/GIMT_Encode2(GICXXPred_MI_Predicate_anonymous_17683),
        GIM_CheckCxxInsnPredicate, /*MI*/0, /*FnId*/GIMT_Encode2(GICXXPred_MI_Predicate_anonymous_17616),
        GIM_CheckIsSafeToFold, /*InsnID*/1,
        GIM_CheckIsSafeToFold, /*InsnID*/2,
        // (or:{ *:[v2i16] } v2i16:{ *:[v2i16] }:$src0, (xor:{ *:[v2i16] } v2i16:{ *:[v2i16] }:$src1, immAllOnesV:{ *:[v2i16] })<<P:Predicate_anonymous_17683>>)<<P:Predicate_anonymous_17616>>  =>  (S_ORN2_B32:{ *:[v2i16] }:{ *:[i1] } SSrc_b32:{ *:[v2i16] }:$src0, SSrc_b32:{ *:[v2i16] }:$src1)
        GIR_BuildMI, /*InsnID*/0, /*Opcode*/GIMT_Encode2(AMDGPU::S_ORN2_B32),
        GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/0, // DstI[sdst]
        GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/1, // src0
        GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/1, /*OpIdx*/1, // src1
        GIR_SetImplicitDefDead, /*InsnID*/0, /*OpIdx for AMDGPU::SCC*/0,
        GIR_ConstrainSelectedInstOperands, /*InsnID*/0,
        GIR_EraseFromParent, /*InsnID*/0,
        // GIR_Coverage, 1663,
        GIR_Done,
      // Label 366: @34041
      GIM_Try, /*On fail goto*//*Label 367*/ GIMT_Encode4(34063), // Rule ID 2130 //
        GIM_CheckRegBankForClass, /*MI*/0, /*Op*/0, /*RC*/GIMT_Encode2(AMDGPU::VGPR_32RegClassID),
        // (or:{ *:[v2i16] } v2i16:{ *:[v2i16] }:$src0, v2i16:{ *:[v2i16] }:$src1)  =>  (V_OR_B32_e64:{ *:[v2i16] } VSrc_b32:{ *:[v2i16] }:$src0, VSrc_b32:{ *:[v2i16] }:$src1)
        GIR_MutateOpcode, /*InsnID*/0, /*RecycleInsnID*/0, /*Opcode*/GIMT_Encode2(AMDGPU::V_OR_B32_e64),
        GIR_AddImplicitUse, /*InsnID*/0, GIMT_Encode2(AMDGPU::EXEC),
        GIR_ConstrainSelectedInstOperands, /*InsnID*/0,
        // GIR_Coverage, 2130,
        GIR_Done,
      // Label 367: @34063
      GIM_Reject,
    // Label 364: @34064
    GIM_Reject,
    // Label 288: @34065
    GIM_Try, /*On fail goto*//*Label 368*/ GIMT_Encode4(34218),
      GIM_CheckType, /*MI*/0, /*Op*/1, /*Type*/GILLT_v2s32,
      GIM_CheckType, /*MI*/0, /*Op*/2, /*Type*/GILLT_v2s32,
      GIM_CheckCxxInsnPredicate, /*MI*/0, /*FnId*/GIMT_Encode2(GICXXPred_MI_Predicate_anonymous_17616),
      GIM_CheckRegBankForClass, /*MI*/0, /*Op*/0, /*RC*/GIMT_Encode2(AMDGPU::SReg_64RegClassID),
      GIM_Try, /*On fail goto*//*Label 369*/ GIMT_Encode4(34152), // Rule ID 7203 //
        GIM_RecordInsn, /*DefineMI*/1, /*MI*/0, /*OpIdx*/1, // MIs[1]
        GIM_CheckOpcode, /*MI*/1, GIMT_Encode2(TargetOpcode::G_XOR),
        GIM_CheckType, /*MI*/1, /*Op*/1, /*Type*/GILLT_v2s32,
        GIM_CheckType, /*MI*/1, /*Op*/2, /*Type*/GILLT_v2s32,
        GIM_RecordInsn, /*DefineMI*/2, /*MI*/1, /*OpIdx*/2, // MIs[2]
        GIM_CheckOpcodeIsEither, /*MI*/2, GIMT_Encode2(TargetOpcode::G_BUILD_VECTOR), GIMT_Encode2(TargetOpcode::G_BUILD_VECTOR_TRUNC),
        GIM_CheckIsBuildVectorAllOnes, /*MI*/2,
        GIM_CheckCxxInsnPredicate, /*MI*/1, /*FnId*/GIMT_Encode2(GICXXPred_MI_Predicate_anonymous_17683),
        GIM_CheckIsSafeToFold, /*InsnID*/1,
        GIM_CheckIsSafeToFold, /*InsnID*/2,
        // (or:{ *:[v2i32] } (xor:{ *:[v2i32] } v2i32:{ *:[v2i32] }:$src1, immAllOnesV:{ *:[v2i32] })<<P:Predicate_anonymous_17683>>, v2i32:{ *:[v2i32] }:$src0)<<P:Predicate_anonymous_17616>>  =>  (S_ORN2_B64:{ *:[v2i32] }:{ *:[i1] } SSrc_b64:{ *:[v2i32] }:$src0, SSrc_b64:{ *:[v2i32] }:$src1)
        GIR_BuildMI, /*InsnID*/0, /*Opcode*/GIMT_Encode2(AMDGPU::S_ORN2_B64),
        GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/0, // DstI[sdst]
        GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/2, // src0
        GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/1, /*OpIdx*/1, // src1
        GIR_SetImplicitDefDead, /*InsnID*/0, /*OpIdx for AMDGPU::SCC*/0,
        GIR_ConstrainSelectedInstOperands, /*InsnID*/0,
        GIR_EraseFromParent, /*InsnID*/0,
        // GIR_Coverage, 7203,
        GIR_Done,
      // Label 369: @34152
      GIM_Try, /*On fail goto*//*Label 370*/ GIMT_Encode4(34217), // Rule ID 1665 //
        GIM_RecordInsn, /*DefineMI*/1, /*MI*/0, /*OpIdx*/2, // MIs[1]
        GIM_CheckOpcode, /*MI*/1, GIMT_Encode2(TargetOpcode::G_XOR),
        GIM_CheckType, /*MI*/1, /*Op*/1, /*Type*/GILLT_v2s32,
        GIM_CheckType, /*MI*/1, /*Op*/2, /*Type*/GILLT_v2s32,
        GIM_RecordInsn, /*DefineMI*/2, /*MI*/1, /*OpIdx*/2, // MIs[2]
        GIM_CheckOpcodeIsEither, /*MI*/2, GIMT_Encode2(TargetOpcode::G_BUILD_VECTOR), GIMT_Encode2(TargetOpcode::G_BUILD_VECTOR_TRUNC),
        GIM_CheckIsBuildVectorAllOnes, /*MI*/2,
        GIM_CheckCxxInsnPredicate, /*MI*/1, /*FnId*/GIMT_Encode2(GICXXPred_MI_Predicate_anonymous_17683),
        GIM_CheckIsSafeToFold, /*InsnID*/1,
        GIM_CheckIsSafeToFold, /*InsnID*/2,
        // (or:{ *:[v2i32] } v2i32:{ *:[v2i32] }:$src0, (xor:{ *:[v2i32] } v2i32:{ *:[v2i32] }:$src1, immAllOnesV:{ *:[v2i32] })<<P:Predicate_anonymous_17683>>)<<P:Predicate_anonymous_17616>>  =>  (S_ORN2_B64:{ *:[v2i32] }:{ *:[i1] } SSrc_b64:{ *:[v2i32] }:$src0, SSrc_b64:{ *:[v2i32] }:$src1)
        GIR_BuildMI, /*InsnID*/0, /*Opcode*/GIMT_Encode2(AMDGPU::S_ORN2_B64),
        GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/0, // DstI[sdst]
        GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/1, // src0
        GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/1, /*OpIdx*/1, // src1
        GIR_SetImplicitDefDead, /*InsnID*/0, /*OpIdx for AMDGPU::SCC*/0,
        GIR_ConstrainSelectedInstOperands, /*InsnID*/0,
        GIR_EraseFromParent, /*InsnID*/0,
        // GIR_Coverage, 1665,
        GIR_Done,
      // Label 370: @34217
      GIM_Reject,
    // Label 368: @34218
    GIM_Reject,
    // Label 289: @34219
    GIM_Try, /*On fail goto*//*Label 371*/ GIMT_Encode4(34372),
      GIM_CheckType, /*MI*/0, /*Op*/1, /*Type*/GILLT_v4s16,
      GIM_CheckType, /*MI*/0, /*Op*/2, /*Type*/GILLT_v4s16,
      GIM_CheckCxxInsnPredicate, /*MI*/0, /*FnId*/GIMT_Encode2(GICXXPred_MI_Predicate_anonymous_17616),
      GIM_CheckRegBankForClass, /*MI*/0, /*Op*/0, /*RC*/GIMT_Encode2(AMDGPU::SReg_64RegClassID),
      GIM_Try, /*On fail goto*//*Label 372*/ GIMT_Encode4(34306), // Rule ID 7202 //
        GIM_RecordInsn, /*DefineMI*/1, /*MI*/0, /*OpIdx*/1, // MIs[1]
        GIM_CheckOpcode, /*MI*/1, GIMT_Encode2(TargetOpcode::G_XOR),
        GIM_CheckType, /*MI*/1, /*Op*/1, /*Type*/GILLT_v4s16,
        GIM_CheckType, /*MI*/1, /*Op*/2, /*Type*/GILLT_v4s16,
        GIM_RecordInsn, /*DefineMI*/2, /*MI*/1, /*OpIdx*/2, // MIs[2]
        GIM_CheckOpcodeIsEither, /*MI*/2, GIMT_Encode2(TargetOpcode::G_BUILD_VECTOR), GIMT_Encode2(TargetOpcode::G_BUILD_VECTOR_TRUNC),
        GIM_CheckIsBuildVectorAllOnes, /*MI*/2,
        GIM_CheckCxxInsnPredicate, /*MI*/1, /*FnId*/GIMT_Encode2(GICXXPred_MI_Predicate_anonymous_17683),
        GIM_CheckIsSafeToFold, /*InsnID*/1,
        GIM_CheckIsSafeToFold, /*InsnID*/2,
        // (or:{ *:[v4i16] } (xor:{ *:[v4i16] } v4i16:{ *:[v4i16] }:$src1, immAllOnesV:{ *:[v4i16] })<<P:Predicate_anonymous_17683>>, v4i16:{ *:[v4i16] }:$src0)<<P:Predicate_anonymous_17616>>  =>  (S_ORN2_B64:{ *:[v4i16] }:{ *:[i1] } SSrc_b64:{ *:[v4i16] }:$src0, SSrc_b64:{ *:[v4i16] }:$src1)
        GIR_BuildMI, /*InsnID*/0, /*Opcode*/GIMT_Encode2(AMDGPU::S_ORN2_B64),
        GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/0, // DstI[sdst]
        GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/2, // src0
        GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/1, /*OpIdx*/1, // src1
        GIR_SetImplicitDefDead, /*InsnID*/0, /*OpIdx for AMDGPU::SCC*/0,
        GIR_ConstrainSelectedInstOperands, /*InsnID*/0,
        GIR_EraseFromParent, /*InsnID*/0,
        // GIR_Coverage, 7202,
        GIR_Done,
      // Label 372: @34306
      GIM_Try, /*On fail goto*//*Label 373*/ GIMT_Encode4(34371), // Rule ID 1664 //
        GIM_RecordInsn, /*DefineMI*/1, /*MI*/0, /*OpIdx*/2, // MIs[1]
        GIM_CheckOpcode, /*MI*/1, GIMT_Encode2(TargetOpcode::G_XOR),
        GIM_CheckType, /*MI*/1, /*Op*/1, /*Type*/GILLT_v4s16,
        GIM_CheckType, /*MI*/1, /*Op*/2, /*Type*/GILLT_v4s16,
        GIM_RecordInsn, /*DefineMI*/2, /*MI*/1, /*OpIdx*/2, // MIs[2]
        GIM_CheckOpcodeIsEither, /*MI*/2, GIMT_Encode2(TargetOpcode::G_BUILD_VECTOR), GIMT_Encode2(TargetOpcode::G_BUILD_VECTOR_TRUNC),
        GIM_CheckIsBuildVectorAllOnes, /*MI*/2,
        GIM_CheckCxxInsnPredicate, /*MI*/1, /*FnId*/GIMT_Encode2(GICXXPred_MI_Predicate_anonymous_17683),
        GIM_CheckIsSafeToFold, /*InsnID*/1,
        GIM_CheckIsSafeToFold, /*InsnID*/2,
        // (or:{ *:[v4i16] } v4i16:{ *:[v4i16] }:$src0, (xor:{ *:[v4i16] } v4i16:{ *:[v4i16] }:$src1, immAllOnesV:{ *:[v4i16] })<<P:Predicate_anonymous_17683>>)<<P:Predicate_anonymous_17616>>  =>  (S_ORN2_B64:{ *:[v4i16] }:{ *:[i1] } SSrc_b64:{ *:[v4i16] }:$src0, SSrc_b64:{ *:[v4i16] }:$src1)
        GIR_BuildMI, /*InsnID*/0, /*Opcode*/GIMT_Encode2(AMDGPU::S_ORN2_B64),
        GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/0, // DstI[sdst]
        GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/1, // src0
        GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/1, /*OpIdx*/1, // src1
        GIR_SetImplicitDefDead, /*InsnID*/0, /*OpIdx for AMDGPU::SCC*/0,
        GIR_ConstrainSelectedInstOperands, /*InsnID*/0,
        GIR_EraseFromParent, /*InsnID*/0,
        // GIR_Coverage, 1664,
        GIR_Done,
      // Label 373: @34371
      GIM_Reject,
    // Label 371: @34372
    GIM_Reject,
    // Label 290: @34373
    GIM_Reject,
    // Label 5: @34374
    GIM_SwitchType, /*MI*/0, /*Op*/0, /*[*/GIMT_Encode2(7), GIMT_Encode2(12), /*)*//*default:*//*Label 379*/ GIMT_Encode4(39049),
    /*GILLT_s1*//*Label 374*/ GIMT_Encode4(34405),
    /*GILLT_s16*//*Label 375*/ GIMT_Encode4(34474),
    /*GILLT_s32*//*Label 376*/ GIMT_Encode4(34531),
    /*GILLT_s64*//*Label 377*/ GIMT_Encode4(36273),
    /*GILLT_v2s16*//*Label 378*/ GIMT_Encode4(39018),
    // Label 374: @34405
    GIM_Try, /*On fail goto*//*Label 380*/ GIMT_Encode4(34473),
      GIM_CheckType, /*MI*/0, /*Op*/1, /*Type*/GILLT_s1,
      GIM_CheckType, /*MI*/0, /*Op*/2, /*Type*/GILLT_s1,
      GIM_Try, /*On fail goto*//*Label 381*/ GIMT_Encode4(34445), // Rule ID 6356 //
        GIM_CheckFeatures, GIMT_Encode2(GIFBS_isWave64),
        GIM_CheckRegBankForClass, /*MI*/0, /*Op*/0, /*RC*/GIMT_Encode2(AMDGPU::SReg_64RegClassID),
        // (xor:{ *:[i1] } i1:{ *:[i1] }:$src0, i1:{ *:[i1] }:$src1)  =>  (S_XOR_B64:{ *:[i1] }:{ *:[i1] } ?:{ *:[i1] }:$src0, ?:{ *:[i1] }:$src1)
        GIR_MutateOpcode, /*InsnID*/0, /*RecycleInsnID*/0, /*Opcode*/GIMT_Encode2(AMDGPU::S_XOR_B64),
        GIR_AddImplicitDef, /*InsnID*/0, GIMT_Encode2(AMDGPU::SCC), GIMT_Encode2(RegState::Dead),
        GIR_ConstrainSelectedInstOperands, /*InsnID*/0,
        // GIR_Coverage, 6356,
        GIR_Done,
      // Label 381: @34445
      GIM_Try, /*On fail goto*//*Label 382*/ GIMT_Encode4(34472), // Rule ID 6363 //
        GIM_CheckFeatures, GIMT_Encode2(GIFBS_isWave32),
        GIM_CheckRegBankForClass, /*MI*/0, /*Op*/0, /*RC*/GIMT_Encode2(AMDGPU::SReg_32RegClassID),
        // (xor:{ *:[i1] } i1:{ *:[i1] }:$src0, i1:{ *:[i1] }:$src1)  =>  (S_XOR_B32:{ *:[i1] }:{ *:[i1] } ?:{ *:[i1] }:$src0, ?:{ *:[i1] }:$src1)
        GIR_MutateOpcode, /*InsnID*/0, /*RecycleInsnID*/0, /*Opcode*/GIMT_Encode2(AMDGPU::S_XOR_B32),
        GIR_AddImplicitDef, /*InsnID*/0, GIMT_Encode2(AMDGPU::SCC), GIMT_Encode2(RegState::Dead),
        GIR_ConstrainSelectedInstOperands, /*InsnID*/0,
        // GIR_Coverage, 6363,
        GIR_Done,
      // Label 382: @34472
      GIM_Reject,
    // Label 380: @34473
    GIM_Reject,
    // Label 375: @34474
    GIM_Try, /*On fail goto*//*Label 383*/ GIMT_Encode4(34530),
      GIM_CheckType, /*MI*/0, /*Op*/1, /*Type*/GILLT_s16,
      GIM_CheckType, /*MI*/0, /*Op*/2, /*Type*/GILLT_s16,
      GIM_CheckRegBankForClass, /*MI*/0, /*Op*/0, /*RC*/GIMT_Encode2(AMDGPU::VGPR_32RegClassID),
      GIM_Try, /*On fail goto*//*Label 384*/ GIMT_Encode4(34509), // Rule ID 2128 //
        // (xor:{ *:[i16] } i16:{ *:[i16] }:$src0, i16:{ *:[i16] }:$src1)  =>  (V_XOR_B32_e64:{ *:[i16] } VSrc_b32:{ *:[i16] }:$src0, VSrc_b32:{ *:[i16] }:$src1)
        GIR_MutateOpcode, /*InsnID*/0, /*RecycleInsnID*/0, /*Opcode*/GIMT_Encode2(AMDGPU::V_XOR_B32_e64),
        GIR_AddImplicitUse, /*InsnID*/0, GIMT_Encode2(AMDGPU::EXEC),
        GIR_ConstrainSelectedInstOperands, /*InsnID*/0,
        // GIR_Coverage, 2128,
        GIR_Done,
      // Label 384: @34509
      GIM_Try, /*On fail goto*//*Label 385*/ GIMT_Encode4(34529), // Rule ID 835 //
        GIM_CheckFeatures, GIMT_Encode2(GIFBS_isGFX11Plus),
        // (xor:{ *:[i16] } i16:{ *:[i16] }:$src0, i16:{ *:[i16] }:$src1)  =>  (V_XOR_B16_t16_e64:{ *:[i16] } i16:{ *:[i16] }:$src0, i16:{ *:[i16] }:$src1)
        GIR_MutateOpcode, /*InsnID*/0, /*RecycleInsnID*/0, /*Opcode*/GIMT_Encode2(AMDGPU::V_XOR_B16_t16_e64),
        GIR_AddImplicitUse, /*InsnID*/0, GIMT_Encode2(AMDGPU::EXEC),
        GIR_ConstrainSelectedInstOperands, /*InsnID*/0,
        // GIR_Coverage, 835,
        GIR_Done,
      // Label 385: @34529
      GIM_Reject,
    // Label 383: @34530
    GIM_Reject,
    // Label 376: @34531
    GIM_Try, /*On fail goto*//*Label 386*/ GIMT_Encode4(36272),
      GIM_CheckType, /*MI*/0, /*Op*/1, /*Type*/GILLT_s32,
      GIM_Try, /*On fail goto*//*Label 387*/ GIMT_Encode4(34608), // Rule ID 62 //
        GIM_CheckType, /*MI*/0, /*Op*/2, /*Type*/GILLT_s32,
        GIM_CheckRegBankForClass, /*MI*/0, /*Op*/0, /*RC*/GIMT_Encode2(AMDGPU::SReg_32RegClassID),
        GIM_RecordInsn, /*DefineMI*/1, /*MI*/0, /*OpIdx*/1, // MIs[1]
        GIM_CheckOpcode, /*MI*/1, GIMT_Encode2(TargetOpcode::G_AND),
        GIM_CheckType, /*MI*/1, /*Op*/1, /*Type*/GILLT_s32,
        GIM_CheckType, /*MI*/1, /*Op*/2, /*Type*/GILLT_s32,
        GIM_CheckCxxInsnPredicate, /*MI*/1, /*FnId*/GIMT_Encode2(GICXXPred_MI_Predicate_and_oneuse),
        GIM_CheckConstantInt8, /*MI*/0, /*Op*/2, uint8_t(-1),
        GIM_CheckCxxInsnPredicate, /*MI*/0, /*FnId*/GIMT_Encode2(GICXXPred_MI_Predicate_anonymous_17562),
        GIM_CheckIsSafeToFold, /*InsnID*/1,
        // (xor:{ *:[i32] } (and:{ *:[i32] } i32:{ *:[i32] }:$src0, i32:{ *:[i32] }:$src1)<<P:Predicate_and_oneuse>>, -1:{ *:[i32] })<<P:Predicate_anonymous_17562>>  =>  (S_NAND_B32:{ *:[i32] }:{ *:[i1] } i32:{ *:[i32] }:$src0, i32:{ *:[i32] }:$src1)
        GIR_BuildMI, /*InsnID*/0, /*Opcode*/GIMT_Encode2(AMDGPU::S_NAND_B32),
        GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/0, // DstI[sdst]
        GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/1, /*OpIdx*/1, // src0
        GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/1, /*OpIdx*/2, // src1
        GIR_SetImplicitDefDead, /*InsnID*/0, /*OpIdx for AMDGPU::SCC*/0,
        GIR_ConstrainSelectedInstOperands, /*InsnID*/0,
        GIR_EraseFromParent, /*InsnID*/0,
        // GIR_Coverage, 62,
        GIR_Done,
      // Label 387: @34608
      GIM_Try, /*On fail goto*//*Label 388*/ GIMT_Encode4(34676), // Rule ID 64 //
        GIM_CheckType, /*MI*/0, /*Op*/2, /*Type*/GILLT_s32,
        GIM_CheckRegBankForClass, /*MI*/0, /*Op*/0, /*RC*/GIMT_Encode2(AMDGPU::SReg_32RegClassID),
        GIM_RecordInsn, /*DefineMI*/1, /*MI*/0, /*OpIdx*/1, // MIs[1]
        GIM_CheckOpcode, /*MI*/1, GIMT_Encode2(TargetOpcode::G_OR),
        GIM_CheckType, /*MI*/1, /*Op*/1, /*Type*/GILLT_s32,
        GIM_CheckType, /*MI*/1, /*Op*/2, /*Type*/GILLT_s32,
        GIM_CheckCxxInsnPredicate, /*MI*/1, /*FnId*/GIMT_Encode2(GICXXPred_MI_Predicate_or_oneuse),
        GIM_CheckConstantInt8, /*MI*/0, /*Op*/2, uint8_t(-1),
        GIM_CheckCxxInsnPredicate, /*MI*/0, /*FnId*/GIMT_Encode2(GICXXPred_MI_Predicate_anonymous_17562),
        GIM_CheckIsSafeToFold, /*InsnID*/1,
        // (xor:{ *:[i32] } (or:{ *:[i32] } i32:{ *:[i32] }:$src0, i32:{ *:[i32] }:$src1)<<P:Predicate_or_oneuse>>, -1:{ *:[i32] })<<P:Predicate_anonymous_17562>>  =>  (S_NOR_B32:{ *:[i32] }:{ *:[i1] } i32:{ *:[i32] }:$src0, i32:{ *:[i32] }:$src1)
        GIR_BuildMI, /*InsnID*/0, /*Opcode*/GIMT_Encode2(AMDGPU::S_NOR_B32),
        GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/0, // DstI[sdst]
        GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/1, /*OpIdx*/1, // src0
        GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/1, /*OpIdx*/2, // src1
        GIR_SetImplicitDefDead, /*InsnID*/0, /*OpIdx for AMDGPU::SCC*/0,
        GIR_ConstrainSelectedInstOperands, /*InsnID*/0,
        GIR_EraseFromParent, /*InsnID*/0,
        // GIR_Coverage, 64,
        GIR_Done,
      // Label 388: @34676
      GIM_Try, /*On fail goto*//*Label 389*/ GIMT_Encode4(34744), // Rule ID 60 //
        GIM_CheckType, /*MI*/0, /*Op*/2, /*Type*/GILLT_s32,
        GIM_CheckRegBankForClass, /*MI*/0, /*Op*/0, /*RC*/GIMT_Encode2(AMDGPU::SReg_32RegClassID),
        GIM_RecordInsn, /*DefineMI*/1, /*MI*/0, /*OpIdx*/1, // MIs[1]
        GIM_CheckOpcode, /*MI*/1, GIMT_Encode2(TargetOpcode::G_XOR),
        GIM_CheckType, /*MI*/1, /*Op*/1, /*Type*/GILLT_s32,
        GIM_CheckType, /*MI*/1, /*Op*/2, /*Type*/GILLT_s32,
        GIM_CheckCxxInsnPredicate, /*MI*/1, /*FnId*/GIMT_Encode2(GICXXPred_MI_Predicate_xor_oneuse),
        GIM_CheckConstantInt8, /*MI*/0, /*Op*/2, uint8_t(-1),
        GIM_CheckCxxInsnPredicate, /*MI*/0, /*FnId*/GIMT_Encode2(GICXXPred_MI_Predicate_anonymous_17562),
        GIM_CheckIsSafeToFold, /*InsnID*/1,
        // (xor:{ *:[i32] } (xor:{ *:[i32] } i32:{ *:[i32] }:$src0, i32:{ *:[i32] }:$src1)<<P:Predicate_xor_oneuse>>, -1:{ *:[i32] })<<P:Predicate_anonymous_17562>>  =>  (S_XNOR_B32:{ *:[i32] }:{ *:[i1] } i32:{ *:[i32] }:$src0, i32:{ *:[i32] }:$src1)
        GIR_BuildMI, /*InsnID*/0, /*Opcode*/GIMT_Encode2(AMDGPU::S_XNOR_B32),
        GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/0, // DstI[sdst]
        GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/1, /*OpIdx*/1, // src0
        GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/1, /*OpIdx*/2, // src1
        GIR_SetImplicitDefDead, /*InsnID*/0, /*OpIdx for AMDGPU::SCC*/0,
        GIR_ConstrainSelectedInstOperands, /*InsnID*/0,
        GIR_EraseFromParent, /*InsnID*/0,
        // GIR_Coverage, 60,
        GIR_Done,
      // Label 389: @34744
      GIM_Try, /*On fail goto*//*Label 390*/ GIMT_Encode4(34875), // Rule ID 9890 //
        GIM_CheckRegBankForClass, /*MI*/0, /*Op*/0, /*RC*/GIMT_Encode2(AMDGPU::VGPR_32RegClassID),
        GIM_RecordInsnIgnoreCopies, /*DefineMI*/1, /*MI*/0, /*OpIdx*/1, // MIs[1]
        GIM_CheckOpcode, /*MI*/1, GIMT_Encode2(TargetOpcode::G_AND),
        GIM_CheckType, /*MI*/1, /*Op*/1, /*Type*/GILLT_s32,
        GIM_CheckType, /*MI*/1, /*Op*/2, /*Type*/GILLT_s32,
        GIM_RecordInsnIgnoreCopies, /*DefineMI*/2, /*MI*/1, /*OpIdx*/1, // MIs[2]
        GIM_CheckOpcode, /*MI*/2, GIMT_Encode2(TargetOpcode::G_XOR),
        GIM_CheckType, /*MI*/2, /*Op*/1, /*Type*/GILLT_s32,
        GIM_CheckType, /*MI*/2, /*Op*/2, /*Type*/GILLT_s32,
        // MIs[0] z
        GIM_CheckIsSameOperandIgnoreCopies, /*MI*/0, /*OpIdx*/2, /*OtherMI*/2, /*OtherOpIdx*/2,
        GIM_CheckCxxInsnPredicate, /*MI*/0, /*FnId*/GIMT_Encode2(GICXXPred_MI_Predicate_anonymous_22559),
        GIM_CheckIsSafeToFold, /*InsnID*/1,
        GIM_CheckIsSafeToFold, /*InsnID*/2,
        // (xor:{ *:[i32] } (and:{ *:[i32] } (xor:{ *:[i32] } i32:{ *:[i32] }:$y, i32:{ *:[i32] }:$z), i32:{ *:[i32] }:$x), i32:{ *:[i32] }:$z)<<P:Predicate_anonymous_22559>>  =>  (V_BFI_B32_e64:{ *:[i32] } (COPY_TO_REGCLASS:{ *:[i16] } VSrc_b32:{ *:[i32] }:$x, VGPR_32:{ *:[i32] }), (COPY_TO_REGCLASS:{ *:[i16] } VSrc_b32:{ *:[i32] }:$y, VGPR_32:{ *:[i32] }), (COPY_TO_REGCLASS:{ *:[i16] } VSrc_b32:{ *:[i32] }:$z, VGPR_32:{ *:[i32] }))
        GIR_MakeTempReg, /*TempRegID*/0, /*TypeID*/GILLT_s16,
        GIR_MakeTempReg, /*TempRegID*/1, /*TypeID*/GILLT_s16,
        GIR_MakeTempReg, /*TempRegID*/2, /*TypeID*/GILLT_s16,
        GIR_BuildMI, /*InsnID*/3, /*Opcode*/GIMT_Encode2(TargetOpcode::COPY),
        GIR_AddTempRegister, /*InsnID*/3, /*TempRegID*/2, /*TempRegFlags*/GIMT_Encode2(RegState::Define),
        GIR_Copy, /*NewInsnID*/3, /*OldInsnID*/2, /*OpIdx*/2, // z
        GIR_ConstrainSelectedInstOperands, /*InsnID*/3,
        GIR_BuildMI, /*InsnID*/2, /*Opcode*/GIMT_Encode2(TargetOpcode::COPY),
        GIR_AddTempRegister, /*InsnID*/2, /*TempRegID*/1, /*TempRegFlags*/GIMT_Encode2(RegState::Define),
        GIR_Copy, /*NewInsnID*/2, /*OldInsnID*/2, /*OpIdx*/1, // y
        GIR_ConstrainSelectedInstOperands, /*InsnID*/2,
        GIR_BuildMI, /*InsnID*/1, /*Opcode*/GIMT_Encode2(TargetOpcode::COPY),
        GIR_AddTempRegister, /*InsnID*/1, /*TempRegID*/0, /*TempRegFlags*/GIMT_Encode2(RegState::Define),
        GIR_Copy, /*NewInsnID*/1, /*OldInsnID*/1, /*OpIdx*/2, // x
        GIR_ConstrainSelectedInstOperands, /*InsnID*/1,
        GIR_BuildMI, /*InsnID*/0, /*Opcode*/GIMT_Encode2(AMDGPU::V_BFI_B32_e64),
        GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/0, // DstI[vdst]
        GIR_AddSimpleTempRegister, /*InsnID*/0, /*TempRegID*/0,
        GIR_AddSimpleTempRegister, /*InsnID*/0, /*TempRegID*/1,
        GIR_AddSimpleTempRegister, /*InsnID*/0, /*TempRegID*/2,
        GIR_ConstrainSelectedInstOperands, /*InsnID*/0,
        GIR_EraseFromParent, /*InsnID*/0,
        // GIR_Coverage, 9890,
        GIR_Done,
      // Label 390: @34875
      GIM_Try, /*On fail goto*//*Label 391*/ GIMT_Encode4(35006), // Rule ID 9891 //
        GIM_CheckRegBankForClass, /*MI*/0, /*Op*/0, /*RC*/GIMT_Encode2(AMDGPU::VGPR_32RegClassID),
        GIM_RecordInsnIgnoreCopies, /*DefineMI*/1, /*MI*/0, /*OpIdx*/1, // MIs[1]
        GIM_CheckOpcode, /*MI*/1, GIMT_Encode2(TargetOpcode::G_AND),
        GIM_CheckType, /*MI*/1, /*Op*/1, /*Type*/GILLT_s32,
        GIM_CheckType, /*MI*/1, /*Op*/2, /*Type*/GILLT_s32,
        GIM_RecordInsnIgnoreCopies, /*DefineMI*/2, /*MI*/1, /*OpIdx*/1, // MIs[2]
        GIM_CheckOpcode, /*MI*/2, GIMT_Encode2(TargetOpcode::G_XOR),
        GIM_CheckType, /*MI*/2, /*Op*/1, /*Type*/GILLT_s32,
        GIM_CheckType, /*MI*/2, /*Op*/2, /*Type*/GILLT_s32,
        // MIs[0] z
        GIM_CheckIsSameOperandIgnoreCopies, /*MI*/0, /*OpIdx*/2, /*OtherMI*/2, /*OtherOpIdx*/1,
        GIM_CheckCxxInsnPredicate, /*MI*/0, /*FnId*/GIMT_Encode2(GICXXPred_MI_Predicate_anonymous_22559),
        GIM_CheckIsSafeToFold, /*InsnID*/1,
        GIM_CheckIsSafeToFold, /*InsnID*/2,
        // (xor:{ *:[i32] } (and:{ *:[i32] } (xor:{ *:[i32] } i32:{ *:[i32] }:$z, i32:{ *:[i32] }:$y), i32:{ *:[i32] }:$x), i32:{ *:[i32] }:$z)<<P:Predicate_anonymous_22559>>  =>  (V_BFI_B32_e64:{ *:[i32] } (COPY_TO_REGCLASS:{ *:[i16] } VSrc_b32:{ *:[i32] }:$x, VGPR_32:{ *:[i32] }), (COPY_TO_REGCLASS:{ *:[i16] } VSrc_b32:{ *:[i32] }:$y, VGPR_32:{ *:[i32] }), (COPY_TO_REGCLASS:{ *:[i16] } VSrc_b32:{ *:[i32] }:$z, VGPR_32:{ *:[i32] }))
        GIR_MakeTempReg, /*TempRegID*/0, /*TypeID*/GILLT_s16,
        GIR_MakeTempReg, /*TempRegID*/1, /*TypeID*/GILLT_s16,
        GIR_MakeTempReg, /*TempRegID*/2, /*TypeID*/GILLT_s16,
        GIR_BuildMI, /*InsnID*/3, /*Opcode*/GIMT_Encode2(TargetOpcode::COPY),
        GIR_AddTempRegister, /*InsnID*/3, /*TempRegID*/2, /*TempRegFlags*/GIMT_Encode2(RegState::Define),
        GIR_Copy, /*NewInsnID*/3, /*OldInsnID*/2, /*OpIdx*/1, // z
        GIR_ConstrainSelectedInstOperands, /*InsnID*/3,
        GIR_BuildMI, /*InsnID*/2, /*Opcode*/GIMT_Encode2(TargetOpcode::COPY),
        GIR_AddTempRegister, /*InsnID*/2, /*TempRegID*/1, /*TempRegFlags*/GIMT_Encode2(RegState::Define),
        GIR_Copy, /*NewInsnID*/2, /*OldInsnID*/2, /*OpIdx*/2, // y
        GIR_ConstrainSelectedInstOperands, /*InsnID*/2,
        GIR_BuildMI, /*InsnID*/1, /*Opcode*/GIMT_Encode2(TargetOpcode::COPY),
        GIR_AddTempRegister, /*InsnID*/1, /*TempRegID*/0, /*TempRegFlags*/GIMT_Encode2(RegState::Define),
        GIR_Copy, /*NewInsnID*/1, /*OldInsnID*/1, /*OpIdx*/2, // x
        GIR_ConstrainSelectedInstOperands, /*InsnID*/1,
        GIR_BuildMI, /*InsnID*/0, /*Opcode*/GIMT_Encode2(AMDGPU::V_BFI_B32_e64),
        GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/0, // DstI[vdst]
        GIR_AddSimpleTempRegister, /*InsnID*/0, /*TempRegID*/0,
        GIR_AddSimpleTempRegister, /*InsnID*/0, /*TempRegID*/1,
        GIR_AddSimpleTempRegister, /*InsnID*/0, /*TempRegID*/2,
        GIR_ConstrainSelectedInstOperands, /*InsnID*/0,
        GIR_EraseFromParent, /*InsnID*/0,
        // GIR_Coverage, 9891,
        GIR_Done,
      // Label 391: @35006
      GIM_Try, /*On fail goto*//*Label 392*/ GIMT_Encode4(35137), // Rule ID 9888 //
        GIM_CheckRegBankForClass, /*MI*/0, /*Op*/0, /*RC*/GIMT_Encode2(AMDGPU::VGPR_32RegClassID),
        GIM_RecordInsnIgnoreCopies, /*DefineMI*/1, /*MI*/0, /*OpIdx*/1, // MIs[1]
        GIM_CheckOpcode, /*MI*/1, GIMT_Encode2(TargetOpcode::G_AND),
        GIM_CheckType, /*MI*/1, /*Op*/1, /*Type*/GILLT_s32,
        GIM_CheckType, /*MI*/1, /*Op*/2, /*Type*/GILLT_s32,
        GIM_RecordInsnIgnoreCopies, /*DefineMI*/2, /*MI*/1, /*OpIdx*/2, // MIs[2]
        GIM_CheckOpcode, /*MI*/2, GIMT_Encode2(TargetOpcode::G_XOR),
        GIM_CheckType, /*MI*/2, /*Op*/1, /*Type*/GILLT_s32,
        GIM_CheckType, /*MI*/2, /*Op*/2, /*Type*/GILLT_s32,
        // MIs[0] z
        GIM_CheckIsSameOperandIgnoreCopies, /*MI*/0, /*OpIdx*/2, /*OtherMI*/2, /*OtherOpIdx*/2,
        GIM_CheckCxxInsnPredicate, /*MI*/0, /*FnId*/GIMT_Encode2(GICXXPred_MI_Predicate_anonymous_22559),
        GIM_CheckIsSafeToFold, /*InsnID*/1,
        GIM_CheckIsSafeToFold, /*InsnID*/2,
        // (xor:{ *:[i32] } (and:{ *:[i32] } i32:{ *:[i32] }:$x, (xor:{ *:[i32] } i32:{ *:[i32] }:$y, i32:{ *:[i32] }:$z)), i32:{ *:[i32] }:$z)<<P:Predicate_anonymous_22559>>  =>  (V_BFI_B32_e64:{ *:[i32] } (COPY_TO_REGCLASS:{ *:[i16] } VSrc_b32:{ *:[i32] }:$x, VGPR_32:{ *:[i32] }), (COPY_TO_REGCLASS:{ *:[i16] } VSrc_b32:{ *:[i32] }:$y, VGPR_32:{ *:[i32] }), (COPY_TO_REGCLASS:{ *:[i16] } VSrc_b32:{ *:[i32] }:$z, VGPR_32:{ *:[i32] }))
        GIR_MakeTempReg, /*TempRegID*/0, /*TypeID*/GILLT_s16,
        GIR_MakeTempReg, /*TempRegID*/1, /*TypeID*/GILLT_s16,
        GIR_MakeTempReg, /*TempRegID*/2, /*TypeID*/GILLT_s16,
        GIR_BuildMI, /*InsnID*/3, /*Opcode*/GIMT_Encode2(TargetOpcode::COPY),
        GIR_AddTempRegister, /*InsnID*/3, /*TempRegID*/2, /*TempRegFlags*/GIMT_Encode2(RegState::Define),
        GIR_Copy, /*NewInsnID*/3, /*OldInsnID*/2, /*OpIdx*/2, // z
        GIR_ConstrainSelectedInstOperands, /*InsnID*/3,
        GIR_BuildMI, /*InsnID*/2, /*Opcode*/GIMT_Encode2(TargetOpcode::COPY),
        GIR_AddTempRegister, /*InsnID*/2, /*TempRegID*/1, /*TempRegFlags*/GIMT_Encode2(RegState::Define),
        GIR_Copy, /*NewInsnID*/2, /*OldInsnID*/2, /*OpIdx*/1, // y
        GIR_ConstrainSelectedInstOperands, /*InsnID*/2,
        GIR_BuildMI, /*InsnID*/1, /*Opcode*/GIMT_Encode2(TargetOpcode::COPY),
        GIR_AddTempRegister, /*InsnID*/1, /*TempRegID*/0, /*TempRegFlags*/GIMT_Encode2(RegState::Define),
        GIR_Copy, /*NewInsnID*/1, /*OldInsnID*/1, /*OpIdx*/1, // x
        GIR_ConstrainSelectedInstOperands, /*InsnID*/1,
        GIR_BuildMI, /*InsnID*/0, /*Opcode*/GIMT_Encode2(AMDGPU::V_BFI_B32_e64),
        GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/0, // DstI[vdst]
        GIR_AddSimpleTempRegister, /*InsnID*/0, /*TempRegID*/0,
        GIR_AddSimpleTempRegister, /*InsnID*/0, /*TempRegID*/1,
        GIR_AddSimpleTempRegister, /*InsnID*/0, /*TempRegID*/2,
        GIR_ConstrainSelectedInstOperands, /*InsnID*/0,
        GIR_EraseFromParent, /*InsnID*/0,
        // GIR_Coverage, 9888,
        GIR_Done,
      // Label 392: @35137
      GIM_Try, /*On fail goto*//*Label 393*/ GIMT_Encode4(35268), // Rule ID 9889 //
        GIM_CheckRegBankForClass, /*MI*/0, /*Op*/0, /*RC*/GIMT_Encode2(AMDGPU::VGPR_32RegClassID),
        GIM_RecordInsnIgnoreCopies, /*DefineMI*/1, /*MI*/0, /*OpIdx*/1, // MIs[1]
        GIM_CheckOpcode, /*MI*/1, GIMT_Encode2(TargetOpcode::G_AND),
        GIM_CheckType, /*MI*/1, /*Op*/1, /*Type*/GILLT_s32,
        GIM_CheckType, /*MI*/1, /*Op*/2, /*Type*/GILLT_s32,
        GIM_RecordInsnIgnoreCopies, /*DefineMI*/2, /*MI*/1, /*OpIdx*/2, // MIs[2]
        GIM_CheckOpcode, /*MI*/2, GIMT_Encode2(TargetOpcode::G_XOR),
        GIM_CheckType, /*MI*/2, /*Op*/1, /*Type*/GILLT_s32,
        GIM_CheckType, /*MI*/2, /*Op*/2, /*Type*/GILLT_s32,
        // MIs[0] z
        GIM_CheckIsSameOperandIgnoreCopies, /*MI*/0, /*OpIdx*/2, /*OtherMI*/2, /*OtherOpIdx*/1,
        GIM_CheckCxxInsnPredicate, /*MI*/0, /*FnId*/GIMT_Encode2(GICXXPred_MI_Predicate_anonymous_22559),
        GIM_CheckIsSafeToFold, /*InsnID*/1,
        GIM_CheckIsSafeToFold, /*InsnID*/2,
        // (xor:{ *:[i32] } (and:{ *:[i32] } i32:{ *:[i32] }:$x, (xor:{ *:[i32] } i32:{ *:[i32] }:$z, i32:{ *:[i32] }:$y)), i32:{ *:[i32] }:$z)<<P:Predicate_anonymous_22559>>  =>  (V_BFI_B32_e64:{ *:[i32] } (COPY_TO_REGCLASS:{ *:[i16] } VSrc_b32:{ *:[i32] }:$x, VGPR_32:{ *:[i32] }), (COPY_TO_REGCLASS:{ *:[i16] } VSrc_b32:{ *:[i32] }:$y, VGPR_32:{ *:[i32] }), (COPY_TO_REGCLASS:{ *:[i16] } VSrc_b32:{ *:[i32] }:$z, VGPR_32:{ *:[i32] }))
        GIR_MakeTempReg, /*TempRegID*/0, /*TypeID*/GILLT_s16,
        GIR_MakeTempReg, /*TempRegID*/1, /*TypeID*/GILLT_s16,
        GIR_MakeTempReg, /*TempRegID*/2, /*TypeID*/GILLT_s16,
        GIR_BuildMI, /*InsnID*/3, /*Opcode*/GIMT_Encode2(TargetOpcode::COPY),
        GIR_AddTempRegister, /*InsnID*/3, /*TempRegID*/2, /*TempRegFlags*/GIMT_Encode2(RegState::Define),
        GIR_Copy, /*NewInsnID*/3, /*OldInsnID*/2, /*OpIdx*/1, // z
        GIR_ConstrainSelectedInstOperands, /*InsnID*/3,
        GIR_BuildMI, /*InsnID*/2, /*Opcode*/GIMT_Encode2(TargetOpcode::COPY),
        GIR_AddTempRegister, /*InsnID*/2, /*TempRegID*/1, /*TempRegFlags*/GIMT_Encode2(RegState::Define),
        GIR_Copy, /*NewInsnID*/2, /*OldInsnID*/2, /*OpIdx*/2, // y
        GIR_ConstrainSelectedInstOperands, /*InsnID*/2,
        GIR_BuildMI, /*InsnID*/1, /*Opcode*/GIMT_Encode2(TargetOpcode::COPY),
        GIR_AddTempRegister, /*InsnID*/1, /*TempRegID*/0, /*TempRegFlags*/GIMT_Encode2(RegState::Define),
        GIR_Copy, /*NewInsnID*/1, /*OldInsnID*/1, /*OpIdx*/1, // x
        GIR_ConstrainSelectedInstOperands, /*InsnID*/1,
        GIR_BuildMI, /*InsnID*/0, /*Opcode*/GIMT_Encode2(AMDGPU::V_BFI_B32_e64),
        GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/0, // DstI[vdst]
        GIR_AddSimpleTempRegister, /*InsnID*/0, /*TempRegID*/0,
        GIR_AddSimpleTempRegister, /*InsnID*/0, /*TempRegID*/1,
        GIR_AddSimpleTempRegister, /*InsnID*/0, /*TempRegID*/2,
        GIR_ConstrainSelectedInstOperands, /*InsnID*/0,
        GIR_EraseFromParent, /*InsnID*/0,
        // GIR_Coverage, 9889,
        GIR_Done,
      // Label 393: @35268
      GIM_Try, /*On fail goto*//*Label 394*/ GIMT_Encode4(35399), // Rule ID 9887 //
        GIM_CheckType, /*MI*/0, /*Op*/2, /*Type*/GILLT_s32,
        GIM_CheckRegBankForClass, /*MI*/0, /*Op*/0, /*RC*/GIMT_Encode2(AMDGPU::VGPR_32RegClassID),
        GIM_RecordInsnIgnoreCopies, /*DefineMI*/1, /*MI*/0, /*OpIdx*/2, // MIs[1]
        GIM_CheckOpcode, /*MI*/1, GIMT_Encode2(TargetOpcode::G_AND),
        GIM_CheckType, /*MI*/1, /*Op*/1, /*Type*/GILLT_s32,
        GIM_CheckType, /*MI*/1, /*Op*/2, /*Type*/GILLT_s32,
        GIM_RecordInsnIgnoreCopies, /*DefineMI*/2, /*MI*/1, /*OpIdx*/1, // MIs[2]
        GIM_CheckOpcode, /*MI*/2, GIMT_Encode2(TargetOpcode::G_XOR),
        GIM_CheckType, /*MI*/2, /*Op*/2, /*Type*/GILLT_s32,
        // MIs[2] z
        GIM_CheckIsSameOperandIgnoreCopies, /*MI*/2, /*OpIdx*/1, /*OtherMI*/0, /*OtherOpIdx*/1,
        GIM_CheckCxxInsnPredicate, /*MI*/0, /*FnId*/GIMT_Encode2(GICXXPred_MI_Predicate_anonymous_22559),
        GIM_CheckIsSafeToFold, /*InsnID*/1,
        GIM_CheckIsSafeToFold, /*InsnID*/2,
        // (xor:{ *:[i32] } i32:{ *:[i32] }:$z, (and:{ *:[i32] } (xor:{ *:[i32] } i32:{ *:[i32] }:$z, i32:{ *:[i32] }:$y), i32:{ *:[i32] }:$x))<<P:Predicate_anonymous_22559>>  =>  (V_BFI_B32_e64:{ *:[i32] } (COPY_TO_REGCLASS:{ *:[i16] } VSrc_b32:{ *:[i32] }:$x, VGPR_32:{ *:[i32] }), (COPY_TO_REGCLASS:{ *:[i16] } VSrc_b32:{ *:[i32] }:$y, VGPR_32:{ *:[i32] }), (COPY_TO_REGCLASS:{ *:[i16] } VSrc_b32:{ *:[i32] }:$z, VGPR_32:{ *:[i32] }))
        GIR_MakeTempReg, /*TempRegID*/0, /*TypeID*/GILLT_s16,
        GIR_MakeTempReg, /*TempRegID*/1, /*TypeID*/GILLT_s16,
        GIR_MakeTempReg, /*TempRegID*/2, /*TypeID*/GILLT_s16,
        GIR_BuildMI, /*InsnID*/3, /*Opcode*/GIMT_Encode2(TargetOpcode::COPY),
        GIR_AddTempRegister, /*InsnID*/3, /*TempRegID*/2, /*TempRegFlags*/GIMT_Encode2(RegState::Define),
        GIR_Copy, /*NewInsnID*/3, /*OldInsnID*/0, /*OpIdx*/1, // z
        GIR_ConstrainSelectedInstOperands, /*InsnID*/3,
        GIR_BuildMI, /*InsnID*/2, /*Opcode*/GIMT_Encode2(TargetOpcode::COPY),
        GIR_AddTempRegister, /*InsnID*/2, /*TempRegID*/1, /*TempRegFlags*/GIMT_Encode2(RegState::Define),
        GIR_Copy, /*NewInsnID*/2, /*OldInsnID*/2, /*OpIdx*/2, // y
        GIR_ConstrainSelectedInstOperands, /*InsnID*/2,
        GIR_BuildMI, /*InsnID*/1, /*Opcode*/GIMT_Encode2(TargetOpcode::COPY),
        GIR_AddTempRegister, /*InsnID*/1, /*TempRegID*/0, /*TempRegFlags*/GIMT_Encode2(RegState::Define),
        GIR_Copy, /*NewInsnID*/1, /*OldInsnID*/1, /*OpIdx*/2, // x
        GIR_ConstrainSelectedInstOperands, /*InsnID*/1,
        GIR_BuildMI, /*InsnID*/0, /*Opcode*/GIMT_Encode2(AMDGPU::V_BFI_B32_e64),
        GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/0, // DstI[vdst]
        GIR_AddSimpleTempRegister, /*InsnID*/0, /*TempRegID*/0,
        GIR_AddSimpleTempRegister, /*InsnID*/0, /*TempRegID*/1,
        GIR_AddSimpleTempRegister, /*InsnID*/0, /*TempRegID*/2,
        GIR_ConstrainSelectedInstOperands, /*InsnID*/0,
        GIR_EraseFromParent, /*InsnID*/0,
        // GIR_Coverage, 9887,
        GIR_Done,
      // Label 394: @35399
      GIM_Try, /*On fail goto*//*Label 395*/ GIMT_Encode4(35530), // Rule ID 9886 //
        GIM_CheckType, /*MI*/0, /*Op*/2, /*Type*/GILLT_s32,
        GIM_CheckRegBankForClass, /*MI*/0, /*Op*/0, /*RC*/GIMT_Encode2(AMDGPU::VGPR_32RegClassID),
        GIM_RecordInsnIgnoreCopies, /*DefineMI*/1, /*MI*/0, /*OpIdx*/2, // MIs[1]
        GIM_CheckOpcode, /*MI*/1, GIMT_Encode2(TargetOpcode::G_AND),
        GIM_CheckType, /*MI*/1, /*Op*/1, /*Type*/GILLT_s32,
        GIM_CheckType, /*MI*/1, /*Op*/2, /*Type*/GILLT_s32,
        GIM_RecordInsnIgnoreCopies, /*DefineMI*/2, /*MI*/1, /*OpIdx*/1, // MIs[2]
        GIM_CheckOpcode, /*MI*/2, GIMT_Encode2(TargetOpcode::G_XOR),
        GIM_CheckType, /*MI*/2, /*Op*/1, /*Type*/GILLT_s32,
        // MIs[2] z
        GIM_CheckIsSameOperandIgnoreCopies, /*MI*/2, /*OpIdx*/2, /*OtherMI*/0, /*OtherOpIdx*/1,
        GIM_CheckCxxInsnPredicate, /*MI*/0, /*FnId*/GIMT_Encode2(GICXXPred_MI_Predicate_anonymous_22559),
        GIM_CheckIsSafeToFold, /*InsnID*/1,
        GIM_CheckIsSafeToFold, /*InsnID*/2,
        // (xor:{ *:[i32] } i32:{ *:[i32] }:$z, (and:{ *:[i32] } (xor:{ *:[i32] } i32:{ *:[i32] }:$y, i32:{ *:[i32] }:$z), i32:{ *:[i32] }:$x))<<P:Predicate_anonymous_22559>>  =>  (V_BFI_B32_e64:{ *:[i32] } (COPY_TO_REGCLASS:{ *:[i16] } VSrc_b32:{ *:[i32] }:$x, VGPR_32:{ *:[i32] }), (COPY_TO_REGCLASS:{ *:[i16] } VSrc_b32:{ *:[i32] }:$y, VGPR_32:{ *:[i32] }), (COPY_TO_REGCLASS:{ *:[i16] } VSrc_b32:{ *:[i32] }:$z, VGPR_32:{ *:[i32] }))
        GIR_MakeTempReg, /*TempRegID*/0, /*TypeID*/GILLT_s16,
        GIR_MakeTempReg, /*TempRegID*/1, /*TypeID*/GILLT_s16,
        GIR_MakeTempReg, /*TempRegID*/2, /*TypeID*/GILLT_s16,
        GIR_BuildMI, /*InsnID*/3, /*Opcode*/GIMT_Encode2(TargetOpcode::COPY),
        GIR_AddTempRegister, /*InsnID*/3, /*TempRegID*/2, /*TempRegFlags*/GIMT_Encode2(RegState::Define),
        GIR_Copy, /*NewInsnID*/3, /*OldInsnID*/0, /*OpIdx*/1, // z
        GIR_ConstrainSelectedInstOperands, /*InsnID*/3,
        GIR_BuildMI, /*InsnID*/2, /*Opcode*/GIMT_Encode2(TargetOpcode::COPY),
        GIR_AddTempRegister, /*InsnID*/2, /*TempRegID*/1, /*TempRegFlags*/GIMT_Encode2(RegState::Define),
        GIR_Copy, /*NewInsnID*/2, /*OldInsnID*/2, /*OpIdx*/1, // y
        GIR_ConstrainSelectedInstOperands, /*InsnID*/2,
        GIR_BuildMI, /*InsnID*/1, /*Opcode*/GIMT_Encode2(TargetOpcode::COPY),
        GIR_AddTempRegister, /*InsnID*/1, /*TempRegID*/0, /*TempRegFlags*/GIMT_Encode2(RegState::Define),
        GIR_Copy, /*NewInsnID*/1, /*OldInsnID*/1, /*OpIdx*/2, // x
        GIR_ConstrainSelectedInstOperands, /*InsnID*/1,
        GIR_BuildMI, /*InsnID*/0, /*Opcode*/GIMT_Encode2(AMDGPU::V_BFI_B32_e64),
        GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/0, // DstI[vdst]
        GIR_AddSimpleTempRegister, /*InsnID*/0, /*TempRegID*/0,
        GIR_AddSimpleTempRegister, /*InsnID*/0, /*TempRegID*/1,
        GIR_AddSimpleTempRegister, /*InsnID*/0, /*TempRegID*/2,
        GIR_ConstrainSelectedInstOperands, /*InsnID*/0,
        GIR_EraseFromParent, /*InsnID*/0,
        // GIR_Coverage, 9886,
        GIR_Done,
      // Label 395: @35530
      GIM_Try, /*On fail goto*//*Label 396*/ GIMT_Encode4(35661), // Rule ID 9885 //
        GIM_CheckType, /*MI*/0, /*Op*/2, /*Type*/GILLT_s32,
        GIM_CheckRegBankForClass, /*MI*/0, /*Op*/0, /*RC*/GIMT_Encode2(AMDGPU::VGPR_32RegClassID),
        GIM_RecordInsnIgnoreCopies, /*DefineMI*/1, /*MI*/0, /*OpIdx*/2, // MIs[1]
        GIM_CheckOpcode, /*MI*/1, GIMT_Encode2(TargetOpcode::G_AND),
        GIM_CheckType, /*MI*/1, /*Op*/1, /*Type*/GILLT_s32,
        GIM_CheckType, /*MI*/1, /*Op*/2, /*Type*/GILLT_s32,
        GIM_RecordInsnIgnoreCopies, /*DefineMI*/2, /*MI*/1, /*OpIdx*/2, // MIs[2]
        GIM_CheckOpcode, /*MI*/2, GIMT_Encode2(TargetOpcode::G_XOR),
        GIM_CheckType, /*MI*/2, /*Op*/2, /*Type*/GILLT_s32,
        // MIs[2] z
        GIM_CheckIsSameOperandIgnoreCopies, /*MI*/2, /*OpIdx*/1, /*OtherMI*/0, /*OtherOpIdx*/1,
        GIM_CheckCxxInsnPredicate, /*MI*/0, /*FnId*/GIMT_Encode2(GICXXPred_MI_Predicate_anonymous_22559),
        GIM_CheckIsSafeToFold, /*InsnID*/1,
        GIM_CheckIsSafeToFold, /*InsnID*/2,
        // (xor:{ *:[i32] } i32:{ *:[i32] }:$z, (and:{ *:[i32] } i32:{ *:[i32] }:$x, (xor:{ *:[i32] } i32:{ *:[i32] }:$z, i32:{ *:[i32] }:$y)))<<P:Predicate_anonymous_22559>>  =>  (V_BFI_B32_e64:{ *:[i32] } (COPY_TO_REGCLASS:{ *:[i16] } VSrc_b32:{ *:[i32] }:$x, VGPR_32:{ *:[i32] }), (COPY_TO_REGCLASS:{ *:[i16] } VSrc_b32:{ *:[i32] }:$y, VGPR_32:{ *:[i32] }), (COPY_TO_REGCLASS:{ *:[i16] } VSrc_b32:{ *:[i32] }:$z, VGPR_32:{ *:[i32] }))
        GIR_MakeTempReg, /*TempRegID*/0, /*TypeID*/GILLT_s16,
        GIR_MakeTempReg, /*TempRegID*/1, /*TypeID*/GILLT_s16,
        GIR_MakeTempReg, /*TempRegID*/2, /*TypeID*/GILLT_s16,
        GIR_BuildMI, /*InsnID*/3, /*Opcode*/GIMT_Encode2(TargetOpcode::COPY),
        GIR_AddTempRegister, /*InsnID*/3, /*TempRegID*/2, /*TempRegFlags*/GIMT_Encode2(RegState::Define),
        GIR_Copy, /*NewInsnID*/3, /*OldInsnID*/0, /*OpIdx*/1, // z
        GIR_ConstrainSelectedInstOperands, /*InsnID*/3,
        GIR_BuildMI, /*InsnID*/2, /*Opcode*/GIMT_Encode2(TargetOpcode::COPY),
        GIR_AddTempRegister, /*InsnID*/2, /*TempRegID*/1, /*TempRegFlags*/GIMT_Encode2(RegState::Define),
        GIR_Copy, /*NewInsnID*/2, /*OldInsnID*/2, /*OpIdx*/2, // y
        GIR_ConstrainSelectedInstOperands, /*InsnID*/2,
        GIR_BuildMI, /*InsnID*/1, /*Opcode*/GIMT_Encode2(TargetOpcode::COPY),
        GIR_AddTempRegister, /*InsnID*/1, /*TempRegID*/0, /*TempRegFlags*/GIMT_Encode2(RegState::Define),
        GIR_Copy, /*NewInsnID*/1, /*OldInsnID*/1, /*OpIdx*/1, // x
        GIR_ConstrainSelectedInstOperands, /*InsnID*/1,
        GIR_BuildMI, /*InsnID*/0, /*Opcode*/GIMT_Encode2(AMDGPU::V_BFI_B32_e64),
        GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/0, // DstI[vdst]
        GIR_AddSimpleTempRegister, /*InsnID*/0, /*TempRegID*/0,
        GIR_AddSimpleTempRegister, /*InsnID*/0, /*TempRegID*/1,
        GIR_AddSimpleTempRegister, /*InsnID*/0, /*TempRegID*/2,
        GIR_ConstrainSelectedInstOperands, /*InsnID*/0,
        GIR_EraseFromParent, /*InsnID*/0,
        // GIR_Coverage, 9885,
        GIR_Done,
      // Label 396: @35661
      GIM_Try, /*On fail goto*//*Label 397*/ GIMT_Encode4(35792), // Rule ID 6276 //
        GIM_CheckType, /*MI*/0, /*Op*/2, /*Type*/GILLT_s32,
        GIM_CheckRegBankForClass, /*MI*/0, /*Op*/0, /*RC*/GIMT_Encode2(AMDGPU::VGPR_32RegClassID),
        GIM_RecordInsnIgnoreCopies, /*DefineMI*/1, /*MI*/0, /*OpIdx*/2, // MIs[1]
        GIM_CheckOpcode, /*MI*/1, GIMT_Encode2(TargetOpcode::G_AND),
        GIM_CheckType, /*MI*/1, /*Op*/1, /*Type*/GILLT_s32,
        GIM_CheckType, /*MI*/1, /*Op*/2, /*Type*/GILLT_s32,
        GIM_RecordInsnIgnoreCopies, /*DefineMI*/2, /*MI*/1, /*OpIdx*/2, // MIs[2]
        GIM_CheckOpcode, /*MI*/2, GIMT_Encode2(TargetOpcode::G_XOR),
        GIM_CheckType, /*MI*/2, /*Op*/1, /*Type*/GILLT_s32,
        // MIs[2] z
        GIM_CheckIsSameOperandIgnoreCopies, /*MI*/2, /*OpIdx*/2, /*OtherMI*/0, /*OtherOpIdx*/1,
        GIM_CheckCxxInsnPredicate, /*MI*/0, /*FnId*/GIMT_Encode2(GICXXPred_MI_Predicate_anonymous_22559),
        GIM_CheckIsSafeToFold, /*InsnID*/1,
        GIM_CheckIsSafeToFold, /*InsnID*/2,
        // (xor:{ *:[i32] } i32:{ *:[i32] }:$z, (and:{ *:[i32] } i32:{ *:[i32] }:$x, (xor:{ *:[i32] } i32:{ *:[i32] }:$y, i32:{ *:[i32] }:$z)))<<P:Predicate_anonymous_22559>>  =>  (V_BFI_B32_e64:{ *:[i32] } (COPY_TO_REGCLASS:{ *:[i16] } VSrc_b32:{ *:[i32] }:$x, VGPR_32:{ *:[i32] }), (COPY_TO_REGCLASS:{ *:[i16] } VSrc_b32:{ *:[i32] }:$y, VGPR_32:{ *:[i32] }), (COPY_TO_REGCLASS:{ *:[i16] } VSrc_b32:{ *:[i32] }:$z, VGPR_32:{ *:[i32] }))
        GIR_MakeTempReg, /*TempRegID*/0, /*TypeID*/GILLT_s16,
        GIR_MakeTempReg, /*TempRegID*/1, /*TypeID*/GILLT_s16,
        GIR_MakeTempReg, /*TempRegID*/2, /*TypeID*/GILLT_s16,
        GIR_BuildMI, /*InsnID*/3, /*Opcode*/GIMT_Encode2(TargetOpcode::COPY),
        GIR_AddTempRegister, /*InsnID*/3, /*TempRegID*/2, /*TempRegFlags*/GIMT_Encode2(RegState::Define),
        GIR_Copy, /*NewInsnID*/3, /*OldInsnID*/0, /*OpIdx*/1, // z
        GIR_ConstrainSelectedInstOperands, /*InsnID*/3,
        GIR_BuildMI, /*InsnID*/2, /*Opcode*/GIMT_Encode2(TargetOpcode::COPY),
        GIR_AddTempRegister, /*InsnID*/2, /*TempRegID*/1, /*TempRegFlags*/GIMT_Encode2(RegState::Define),
        GIR_Copy, /*NewInsnID*/2, /*OldInsnID*/2, /*OpIdx*/1, // y
        GIR_ConstrainSelectedInstOperands, /*InsnID*/2,
        GIR_BuildMI, /*InsnID*/1, /*Opcode*/GIMT_Encode2(TargetOpcode::COPY),
        GIR_AddTempRegister, /*InsnID*/1, /*TempRegID*/0, /*TempRegFlags*/GIMT_Encode2(RegState::Define),
        GIR_Copy, /*NewInsnID*/1, /*OldInsnID*/1, /*OpIdx*/1, // x
        GIR_ConstrainSelectedInstOperands, /*InsnID*/1,
        GIR_BuildMI, /*InsnID*/0, /*Opcode*/GIMT_Encode2(AMDGPU::V_BFI_B32_e64),
        GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/0, // DstI[vdst]
        GIR_AddSimpleTempRegister, /*InsnID*/0, /*TempRegID*/0,
        GIR_AddSimpleTempRegister, /*InsnID*/0, /*TempRegID*/1,
        GIR_AddSimpleTempRegister, /*InsnID*/0, /*TempRegID*/2,
        GIR_ConstrainSelectedInstOperands, /*InsnID*/0,
        GIR_EraseFromParent, /*InsnID*/0,
        // GIR_Coverage, 6276,
        GIR_Done,
      // Label 397: @35792
      GIM_Try, /*On fail goto*//*Label 398*/ GIMT_Encode4(35834), // Rule ID 0 //
        GIM_CheckType, /*MI*/0, /*Op*/2, /*Type*/GILLT_s32,
        GIM_CheckRegBankForClass, /*MI*/0, /*Op*/0, /*RC*/GIMT_Encode2(AMDGPU::SReg_32RegClassID),
        GIM_CheckConstantInt8, /*MI*/0, /*Op*/2, uint8_t(-1),
        GIM_CheckCxxInsnPredicate, /*MI*/0, /*FnId*/GIMT_Encode2(GICXXPred_MI_Predicate_anonymous_17562),
        // (xor:{ *:[i32] } i32:{ *:[i32] }:$src0, -1:{ *:[i32] })<<P:Predicate_anonymous_17562>>  =>  (S_NOT_B32:{ *:[i32] }:{ *:[i1] } i32:{ *:[i32] }:$src0)
        GIR_BuildMI, /*InsnID*/0, /*Opcode*/GIMT_Encode2(AMDGPU::S_NOT_B32),
        GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/0, // DstI[sdst]
        GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/1, // src0
        GIR_SetImplicitDefDead, /*InsnID*/0, /*OpIdx for AMDGPU::SCC*/0,
        GIR_ConstrainSelectedInstOperands, /*InsnID*/0,
        GIR_EraseFromParent, /*InsnID*/0,
        // GIR_Coverage, 0,
        GIR_Done,
      // Label 398: @35834
      GIM_Try, /*On fail goto*//*Label 399*/ GIMT_Encode4(35873), // Rule ID 6368 //
        GIM_CheckType, /*MI*/0, /*Op*/2, /*Type*/GILLT_s32,
        GIM_CheckRegBankForClass, /*MI*/0, /*Op*/0, /*RC*/GIMT_Encode2(AMDGPU::VGPR_32RegClassID),
        GIM_CheckConstantInt8, /*MI*/0, /*Op*/2, uint8_t(-1),
        GIM_CheckCxxInsnPredicate, /*MI*/0, /*FnId*/GIMT_Encode2(GICXXPred_MI_Predicate_anonymous_22559),
        // (xor:{ *:[i32] } i32:{ *:[i32] }:$src0, -1:{ *:[i32] })<<P:Predicate_anonymous_22559>>  =>  (V_NOT_B32_e32:{ *:[i32] } ?:{ *:[i32] }:$src0)
        GIR_BuildMI, /*InsnID*/0, /*Opcode*/GIMT_Encode2(AMDGPU::V_NOT_B32_e32),
        GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/0, // DstI[vdst]
        GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/1, // src0
        GIR_ConstrainSelectedInstOperands, /*InsnID*/0,
        GIR_EraseFromParent, /*InsnID*/0,
        // GIR_Coverage, 6368,
        GIR_Done,
      // Label 399: @35873
      GIM_Try, /*On fail goto*//*Label 400*/ GIMT_Encode4(35953), // Rule ID 2210 //
        GIM_CheckFeatures, GIMT_Encode2(GIFBS_isGFX10Plus),
        GIM_CheckType, /*MI*/0, /*Op*/2, /*Type*/GILLT_s32,
        GIM_CheckRegBankForClass, /*MI*/0, /*Op*/0, /*RC*/GIMT_Encode2(AMDGPU::VGPR_32RegClassID),
        GIM_RecordInsn, /*DefineMI*/1, /*MI*/0, /*OpIdx*/1, // MIs[1]
        GIM_CheckOpcode, /*MI*/1, GIMT_Encode2(TargetOpcode::G_XOR),
        GIM_CheckType, /*MI*/1, /*Op*/1, /*Type*/GILLT_s32,
        GIM_CheckType, /*MI*/1, /*Op*/2, /*Type*/GILLT_s32,
        GIM_RecordNamedOperand, /*MI*/1, /*Op*/1, /*StoreIdx*/0, // Name : pred:14:x
        GIM_RecordNamedOperand, /*MI*/1, /*Op*/2, /*StoreIdx*/1, // Name : pred:14:y
        GIM_CheckCxxInsnPredicate, /*MI*/1, /*FnId*/GIMT_Encode2(GICXXPred_MI_Predicate_anonymous_23622),
        GIM_RecordNamedOperand, /*MI*/0, /*Op*/2, /*StoreIdx*/2, // Name : pred:14:z
        GIM_CheckCxxInsnPredicate, /*MI*/0, /*FnId*/GIMT_Encode2(GICXXPred_MI_Predicate_anonymous_23670),
        GIM_CheckIsSafeToFold, /*InsnID*/1,
        // (xor:{ *:[i32] } (xor:{ *:[i32] } i32:{ *:[i32] }:$src0:$pred:14:x, i32:{ *:[i32] }:$src1:$pred:14:y)<<P:Predicate_anonymous_23622>>, i32:{ *:[i32] }:$src2:$pred:14:z)<<P:14:Predicate_anonymous_23670>>  =>  (V_XOR3_B32_e64:{ *:[i32] } VSrc_b32:{ *:[i32] }:$src0, VSrc_b32:{ *:[i32] }:$src1, VSrc_b32:{ *:[i32] }:$src2)
        GIR_BuildMI, /*InsnID*/0, /*Opcode*/GIMT_Encode2(AMDGPU::V_XOR3_B32_e64),
        GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/0, // DstI[vdst]
        GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/1, /*OpIdx*/1, // src0
        GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/1, /*OpIdx*/2, // src1
        GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/2, // src2
        GIR_ConstrainSelectedInstOperands, /*InsnID*/0,
        GIR_EraseFromParent, /*InsnID*/0,
        // GIR_Coverage, 2210,
        GIR_Done,
      // Label 400: @35953
      GIM_Try, /*On fail goto*//*Label 401*/ GIMT_Encode4(36033), // Rule ID 7225 //
        GIM_CheckFeatures, GIMT_Encode2(GIFBS_isGFX10Plus),
        GIM_CheckType, /*MI*/0, /*Op*/2, /*Type*/GILLT_s32,
        GIM_CheckRegBankForClass, /*MI*/0, /*Op*/0, /*RC*/GIMT_Encode2(AMDGPU::VGPR_32RegClassID),
        GIM_RecordNamedOperand, /*MI*/0, /*Op*/1, /*StoreIdx*/2, // Name : pred:14:z
        GIM_RecordInsn, /*DefineMI*/1, /*MI*/0, /*OpIdx*/2, // MIs[1]
        GIM_CheckOpcode, /*MI*/1, GIMT_Encode2(TargetOpcode::G_XOR),
        GIM_CheckType, /*MI*/1, /*Op*/1, /*Type*/GILLT_s32,
        GIM_CheckType, /*MI*/1, /*Op*/2, /*Type*/GILLT_s32,
        GIM_RecordNamedOperand, /*MI*/1, /*Op*/1, /*StoreIdx*/0, // Name : pred:14:x
        GIM_RecordNamedOperand, /*MI*/1, /*Op*/2, /*StoreIdx*/1, // Name : pred:14:y
        GIM_CheckCxxInsnPredicate, /*MI*/1, /*FnId*/GIMT_Encode2(GICXXPred_MI_Predicate_anonymous_23622),
        GIM_CheckCxxInsnPredicate, /*MI*/0, /*FnId*/GIMT_Encode2(GICXXPred_MI_Predicate_anonymous_23670),
        GIM_CheckIsSafeToFold, /*InsnID*/1,
        // (xor:{ *:[i32] } i32:{ *:[i32] }:$src2:$pred:14:z, (xor:{ *:[i32] } i32:{ *:[i32] }:$src0:$pred:14:x, i32:{ *:[i32] }:$src1:$pred:14:y)<<P:Predicate_anonymous_23622>>)<<P:14:Predicate_anonymous_23670>>  =>  (V_XOR3_B32_e64:{ *:[i32] } VSrc_b32:{ *:[i32] }:$src0, VSrc_b32:{ *:[i32] }:$src1, VSrc_b32:{ *:[i32] }:$src2)
        GIR_BuildMI, /*InsnID*/0, /*Opcode*/GIMT_Encode2(AMDGPU::V_XOR3_B32_e64),
        GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/0, // DstI[vdst]
        GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/1, /*OpIdx*/1, // src0
        GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/1, /*OpIdx*/2, // src1
        GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/1, // src2
        GIR_ConstrainSelectedInstOperands, /*InsnID*/0,
        GIR_EraseFromParent, /*InsnID*/0,
        // GIR_Coverage, 7225,
        GIR_Done,
      // Label 401: @36033
      GIM_Try, /*On fail goto*//*Label 402*/ GIMT_Encode4(36065), // Rule ID 58 //
        GIM_CheckType, /*MI*/0, /*Op*/2, /*Type*/GILLT_s32,
        GIM_CheckRegBankForClass, /*MI*/0, /*Op*/0, /*RC*/GIMT_Encode2(AMDGPU::SReg_32RegClassID),
        GIM_CheckCxxInsnPredicate, /*MI*/0, /*FnId*/GIMT_Encode2(GICXXPred_MI_Predicate_anonymous_17617),
        // (xor:{ *:[i32] } i32:{ *:[i32] }:$src0, i32:{ *:[i32] }:$src1)<<P:Predicate_anonymous_17617>>  =>  (S_XOR_B32:{ *:[i32] }:{ *:[i1] } i32:{ *:[i32] }:$src0, i32:{ *:[i32] }:$src1)
        GIR_MutateOpcode, /*InsnID*/0, /*RecycleInsnID*/0, /*Opcode*/GIMT_Encode2(AMDGPU::S_XOR_B32),
        GIR_AddImplicitDef, /*InsnID*/0, GIMT_Encode2(AMDGPU::SCC), GIMT_Encode2(RegState::Dead),
        GIR_ConstrainSelectedInstOperands, /*InsnID*/0,
        // GIR_Coverage, 58,
        GIR_Done,
      // Label 402: @36065
      GIM_Try, /*On fail goto*//*Label 403*/ GIMT_Encode4(36125), // Rule ID 7160 //
        GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasDLInsts),
        GIM_CheckType, /*MI*/0, /*Op*/2, /*Type*/GILLT_s32,
        GIM_CheckRegBankForClass, /*MI*/0, /*Op*/0, /*RC*/GIMT_Encode2(AMDGPU::VGPR_32RegClassID),
        GIM_RecordInsn, /*DefineMI*/1, /*MI*/0, /*OpIdx*/1, // MIs[1]
        GIM_CheckOpcode, /*MI*/1, GIMT_Encode2(TargetOpcode::G_XOR),
        GIM_CheckType, /*MI*/1, /*Op*/1, /*Type*/GILLT_s32,
        GIM_CheckType, /*MI*/1, /*Op*/2, /*Type*/GILLT_s32,
        GIM_CheckConstantInt8, /*MI*/1, /*Op*/2, uint8_t(-1),
        GIM_CheckIsSafeToFold, /*InsnID*/1,
        // (xor:{ *:[i32] } (xor:{ *:[i32] } i32:{ *:[i32] }:$src0, -1:{ *:[i32] }), i32:{ *:[i32] }:$src1)  =>  (V_XNOR_B32_e64:{ *:[i32] } i32:{ *:[i32] }:$src0, i32:{ *:[i32] }:$src1)
        GIR_BuildMI, /*InsnID*/0, /*Opcode*/GIMT_Encode2(AMDGPU::V_XNOR_B32_e64),
        GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/0, // DstI[vdst]
        GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/1, /*OpIdx*/1, // src0
        GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/2, // src1
        GIR_ConstrainSelectedInstOperands, /*InsnID*/0,
        GIR_EraseFromParent, /*InsnID*/0,
        // GIR_Coverage, 7160,
        GIR_Done,
      // Label 403: @36125
      GIM_Try, /*On fail goto*//*Label 404*/ GIMT_Encode4(36185), // Rule ID 838 //
        GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasDLInsts),
        GIM_CheckType, /*MI*/0, /*Op*/2, /*Type*/GILLT_s32,
        GIM_CheckRegBankForClass, /*MI*/0, /*Op*/0, /*RC*/GIMT_Encode2(AMDGPU::VGPR_32RegClassID),
        GIM_RecordInsn, /*DefineMI*/1, /*MI*/0, /*OpIdx*/1, // MIs[1]
        GIM_CheckOpcode, /*MI*/1, GIMT_Encode2(TargetOpcode::G_XOR),
        GIM_CheckType, /*MI*/1, /*Op*/1, /*Type*/GILLT_s32,
        GIM_CheckType, /*MI*/1, /*Op*/2, /*Type*/GILLT_s32,
        GIM_CheckConstantInt8, /*MI*/0, /*Op*/2, uint8_t(-1),
        GIM_CheckIsSafeToFold, /*InsnID*/1,
        // (xor:{ *:[i32] } (xor:{ *:[i32] } i32:{ *:[i32] }:$src0, i32:{ *:[i32] }:$src1), -1:{ *:[i32] })  =>  (V_XNOR_B32_e64:{ *:[i32] } i32:{ *:[i32] }:$src0, i32:{ *:[i32] }:$src1)
        GIR_BuildMI, /*InsnID*/0, /*Opcode*/GIMT_Encode2(AMDGPU::V_XNOR_B32_e64),
        GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/0, // DstI[vdst]
        GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/1, /*OpIdx*/1, // src0
        GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/1, /*OpIdx*/2, // src1
        GIR_ConstrainSelectedInstOperands, /*InsnID*/0,
        GIR_EraseFromParent, /*InsnID*/0,
        // GIR_Coverage, 838,
        GIR_Done,
      // Label 404: @36185
      GIM_Try, /*On fail goto*//*Label 405*/ GIMT_Encode4(36245), // Rule ID 7161 //
        GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasDLInsts),
        GIM_CheckType, /*MI*/0, /*Op*/2, /*Type*/GILLT_s32,
        GIM_CheckRegBankForClass, /*MI*/0, /*Op*/0, /*RC*/GIMT_Encode2(AMDGPU::VGPR_32RegClassID),
        GIM_RecordInsn, /*DefineMI*/1, /*MI*/0, /*OpIdx*/2, // MIs[1]
        GIM_CheckOpcode, /*MI*/1, GIMT_Encode2(TargetOpcode::G_XOR),
        GIM_CheckType, /*MI*/1, /*Op*/1, /*Type*/GILLT_s32,
        GIM_CheckType, /*MI*/1, /*Op*/2, /*Type*/GILLT_s32,
        GIM_CheckConstantInt8, /*MI*/1, /*Op*/2, uint8_t(-1),
        GIM_CheckIsSafeToFold, /*InsnID*/1,
        // (xor:{ *:[i32] } i32:{ *:[i32] }:$src1, (xor:{ *:[i32] } i32:{ *:[i32] }:$src0, -1:{ *:[i32] }))  =>  (V_XNOR_B32_e64:{ *:[i32] } i32:{ *:[i32] }:$src0, i32:{ *:[i32] }:$src1)
        GIR_BuildMI, /*InsnID*/0, /*Opcode*/GIMT_Encode2(AMDGPU::V_XNOR_B32_e64),
        GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/0, // DstI[vdst]
        GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/1, /*OpIdx*/1, // src0
        GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/1, // src1
        GIR_ConstrainSelectedInstOperands, /*InsnID*/0,
        GIR_EraseFromParent, /*InsnID*/0,
        // GIR_Coverage, 7161,
        GIR_Done,
      // Label 405: @36245
      GIM_Try, /*On fail goto*//*Label 406*/ GIMT_Encode4(36271), // Rule ID 755 //
        GIM_CheckType, /*MI*/0, /*Op*/2, /*Type*/GILLT_s32,
        GIM_CheckRegBankForClass, /*MI*/0, /*Op*/0, /*RC*/GIMT_Encode2(AMDGPU::VGPR_32RegClassID),
        // (xor:{ *:[i32] } i32:{ *:[i32] }:$src0, i32:{ *:[i32] }:$src1)  =>  (V_XOR_B32_e64:{ *:[i32] } i32:{ *:[i32] }:$src0, i32:{ *:[i32] }:$src1)
        GIR_MutateOpcode, /*InsnID*/0, /*RecycleInsnID*/0, /*Opcode*/GIMT_Encode2(AMDGPU::V_XOR_B32_e64),
        GIR_AddImplicitUse, /*InsnID*/0, GIMT_Encode2(AMDGPU::EXEC),
        GIR_ConstrainSelectedInstOperands, /*InsnID*/0,
        // GIR_Coverage, 755,
        GIR_Done,
      // Label 406: @36271
      GIM_Reject,
    // Label 386: @36272
    GIM_Reject,
    // Label 377: @36273
    GIM_Try, /*On fail goto*//*Label 407*/ GIMT_Encode4(39017),
      GIM_CheckType, /*MI*/0, /*Op*/1, /*Type*/GILLT_s64,
      GIM_Try, /*On fail goto*//*Label 408*/ GIMT_Encode4(36350), // Rule ID 63 //
        GIM_CheckType, /*MI*/0, /*Op*/2, /*Type*/GILLT_s64,
        GIM_CheckRegBankForClass, /*MI*/0, /*Op*/0, /*RC*/GIMT_Encode2(AMDGPU::SReg_64RegClassID),
        GIM_RecordInsn, /*DefineMI*/1, /*MI*/0, /*OpIdx*/1, // MIs[1]
        GIM_CheckOpcode, /*MI*/1, GIMT_Encode2(TargetOpcode::G_AND),
        GIM_CheckType, /*MI*/1, /*Op*/1, /*Type*/GILLT_s64,
        GIM_CheckType, /*MI*/1, /*Op*/2, /*Type*/GILLT_s64,
        GIM_CheckCxxInsnPredicate, /*MI*/1, /*FnId*/GIMT_Encode2(GICXXPred_MI_Predicate_and_oneuse),
        GIM_CheckConstantInt8, /*MI*/0, /*Op*/2, uint8_t(-1),
        GIM_CheckCxxInsnPredicate, /*MI*/0, /*FnId*/GIMT_Encode2(GICXXPred_MI_Predicate_anonymous_17562),
        GIM_CheckIsSafeToFold, /*InsnID*/1,
        // (xor:{ *:[i64] } (and:{ *:[i64] } i64:{ *:[i64] }:$src0, i64:{ *:[i64] }:$src1)<<P:Predicate_and_oneuse>>, -1:{ *:[i64] })<<P:Predicate_anonymous_17562>>  =>  (S_NAND_B64:{ *:[i64] }:{ *:[i1] } i64:{ *:[i64] }:$src0, i64:{ *:[i64] }:$src1)
        GIR_BuildMI, /*InsnID*/0, /*Opcode*/GIMT_Encode2(AMDGPU::S_NAND_B64),
        GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/0, // DstI[sdst]
        GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/1, /*OpIdx*/1, // src0
        GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/1, /*OpIdx*/2, // src1
        GIR_SetImplicitDefDead, /*InsnID*/0, /*OpIdx for AMDGPU::SCC*/0,
        GIR_ConstrainSelectedInstOperands, /*InsnID*/0,
        GIR_EraseFromParent, /*InsnID*/0,
        // GIR_Coverage, 63,
        GIR_Done,
      // Label 408: @36350
      GIM_Try, /*On fail goto*//*Label 409*/ GIMT_Encode4(36418), // Rule ID 65 //
        GIM_CheckType, /*MI*/0, /*Op*/2, /*Type*/GILLT_s64,
        GIM_CheckRegBankForClass, /*MI*/0, /*Op*/0, /*RC*/GIMT_Encode2(AMDGPU::SReg_64RegClassID),
        GIM_RecordInsn, /*DefineMI*/1, /*MI*/0, /*OpIdx*/1, // MIs[1]
        GIM_CheckOpcode, /*MI*/1, GIMT_Encode2(TargetOpcode::G_OR),
        GIM_CheckType, /*MI*/1, /*Op*/1, /*Type*/GILLT_s64,
        GIM_CheckType, /*MI*/1, /*Op*/2, /*Type*/GILLT_s64,
        GIM_CheckCxxInsnPredicate, /*MI*/1, /*FnId*/GIMT_Encode2(GICXXPred_MI_Predicate_or_oneuse),
        GIM_CheckConstantInt8, /*MI*/0, /*Op*/2, uint8_t(-1),
        GIM_CheckCxxInsnPredicate, /*MI*/0, /*FnId*/GIMT_Encode2(GICXXPred_MI_Predicate_anonymous_17562),
        GIM_CheckIsSafeToFold, /*InsnID*/1,
        // (xor:{ *:[i64] } (or:{ *:[i64] } i64:{ *:[i64] }:$src0, i64:{ *:[i64] }:$src1)<<P:Predicate_or_oneuse>>, -1:{ *:[i64] })<<P:Predicate_anonymous_17562>>  =>  (S_NOR_B64:{ *:[i64] }:{ *:[i1] } i64:{ *:[i64] }:$src0, i64:{ *:[i64] }:$src1)
        GIR_BuildMI, /*InsnID*/0, /*Opcode*/GIMT_Encode2(AMDGPU::S_NOR_B64),
        GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/0, // DstI[sdst]
        GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/1, /*OpIdx*/1, // src0
        GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/1, /*OpIdx*/2, // src1
        GIR_SetImplicitDefDead, /*InsnID*/0, /*OpIdx for AMDGPU::SCC*/0,
        GIR_ConstrainSelectedInstOperands, /*InsnID*/0,
        GIR_EraseFromParent, /*InsnID*/0,
        // GIR_Coverage, 65,
        GIR_Done,
      // Label 409: @36418
      GIM_Try, /*On fail goto*//*Label 410*/ GIMT_Encode4(36486), // Rule ID 61 //
        GIM_CheckType, /*MI*/0, /*Op*/2, /*Type*/GILLT_s64,
        GIM_CheckRegBankForClass, /*MI*/0, /*Op*/0, /*RC*/GIMT_Encode2(AMDGPU::SReg_64RegClassID),
        GIM_RecordInsn, /*DefineMI*/1, /*MI*/0, /*OpIdx*/1, // MIs[1]
        GIM_CheckOpcode, /*MI*/1, GIMT_Encode2(TargetOpcode::G_XOR),
        GIM_CheckType, /*MI*/1, /*Op*/1, /*Type*/GILLT_s64,
        GIM_CheckType, /*MI*/1, /*Op*/2, /*Type*/GILLT_s64,
        GIM_CheckCxxInsnPredicate, /*MI*/1, /*FnId*/GIMT_Encode2(GICXXPred_MI_Predicate_xor_oneuse),
        GIM_CheckConstantInt8, /*MI*/0, /*Op*/2, uint8_t(-1),
        GIM_CheckCxxInsnPredicate, /*MI*/0, /*FnId*/GIMT_Encode2(GICXXPred_MI_Predicate_anonymous_17562),
        GIM_CheckIsSafeToFold, /*InsnID*/1,
        // (xor:{ *:[i64] } (xor:{ *:[i64] } i64:{ *:[i64] }:$src0, i64:{ *:[i64] }:$src1)<<P:Predicate_xor_oneuse>>, -1:{ *:[i64] })<<P:Predicate_anonymous_17562>>  =>  (S_XNOR_B64:{ *:[i64] }:{ *:[i1] } i64:{ *:[i64] }:$src0, i64:{ *:[i64] }:$src1)
        GIR_BuildMI, /*InsnID*/0, /*Opcode*/GIMT_Encode2(AMDGPU::S_XNOR_B64),
        GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/0, // DstI[sdst]
        GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/1, /*OpIdx*/1, // src0
        GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/1, /*OpIdx*/2, // src1
        GIR_SetImplicitDefDead, /*InsnID*/0, /*OpIdx for AMDGPU::SCC*/0,
        GIR_ConstrainSelectedInstOperands, /*InsnID*/0,
        GIR_EraseFromParent, /*InsnID*/0,
        // GIR_Coverage, 61,
        GIR_Done,
      // Label 410: @36486
      GIM_Try, /*On fail goto*//*Label 411*/ GIMT_Encode4(36793), // Rule ID 9897 //
        GIM_CheckRegBankForClass, /*MI*/0, /*Op*/0, /*RC*/GIMT_Encode2(AMDGPU::VReg_64RegClassID),
        GIM_RecordInsnIgnoreCopies, /*DefineMI*/1, /*MI*/0, /*OpIdx*/1, // MIs[1]
        GIM_CheckOpcode, /*MI*/1, GIMT_Encode2(TargetOpcode::G_AND),
        GIM_CheckType, /*MI*/1, /*Op*/1, /*Type*/GILLT_s64,
        GIM_CheckType, /*MI*/1, /*Op*/2, /*Type*/GILLT_s64,
        GIM_RecordInsnIgnoreCopies, /*DefineMI*/2, /*MI*/1, /*OpIdx*/1, // MIs[2]
        GIM_CheckOpcode, /*MI*/2, GIMT_Encode2(TargetOpcode::G_XOR),
        GIM_CheckType, /*MI*/2, /*Op*/1, /*Type*/GILLT_s64,
        GIM_CheckType, /*MI*/2, /*Op*/2, /*Type*/GILLT_s64,
        // MIs[0] z
        GIM_CheckIsSameOperandIgnoreCopies, /*MI*/0, /*OpIdx*/2, /*OtherMI*/2, /*OtherOpIdx*/2,
        GIM_CheckCxxInsnPredicate, /*MI*/0, /*FnId*/GIMT_Encode2(GICXXPred_MI_Predicate_anonymous_22559),
        GIM_CheckIsSafeToFold, /*InsnID*/1,
        GIM_CheckIsSafeToFold, /*InsnID*/2,
        // (xor:{ *:[i64] } (and:{ *:[i64] } (xor:{ *:[i64] } i64:{ *:[i64] }:$y, i64:{ *:[i64] }:$z), i64:{ *:[i64] }:$x), i64:{ *:[i64] }:$z)<<P:Predicate_anonymous_22559>>  =>  (REG_SEQUENCE:{ *:[i64] } VReg_64:{ *:[i32] }, (V_BFI_B32_e64:{ *:[i16] } (EXTRACT_SUBREG:{ *:[i32] } VReg_64:{ *:[i64] }:$x, sub0:{ *:[i32] }), (EXTRACT_SUBREG:{ *:[i32] } VReg_64:{ *:[i64] }:$y, sub0:{ *:[i32] }), (EXTRACT_SUBREG:{ *:[i32] } VReg_64:{ *:[i64] }:$z, sub0:{ *:[i32] })), sub0:{ *:[i32] }, (V_BFI_B32_e64:{ *:[i16] } (EXTRACT_SUBREG:{ *:[i32] } VReg_64:{ *:[i64] }:$x, sub1:{ *:[i32] }), (EXTRACT_SUBREG:{ *:[i32] } VReg_64:{ *:[i64] }:$y, sub1:{ *:[i32] }), (EXTRACT_SUBREG:{ *:[i32] } VReg_64:{ *:[i64] }:$z, sub1:{ *:[i32] })), sub1:{ *:[i32] })
        GIR_MakeTempReg, /*TempRegID*/0, /*TypeID*/GILLT_s16,
        GIR_MakeTempReg, /*TempRegID*/1, /*TypeID*/GILLT_s32,
        GIR_MakeTempReg, /*TempRegID*/2, /*TypeID*/GILLT_s32,
        GIR_MakeTempReg, /*TempRegID*/3, /*TypeID*/GILLT_s32,
        GIR_MakeTempReg, /*TempRegID*/4, /*TypeID*/GILLT_s16,
        GIR_MakeTempReg, /*TempRegID*/5, /*TypeID*/GILLT_s32,
        GIR_MakeTempReg, /*TempRegID*/6, /*TypeID*/GILLT_s32,
        GIR_MakeTempReg, /*TempRegID*/7, /*TypeID*/GILLT_s32,
        GIR_BuildMI, /*InsnID*/8, /*Opcode*/GIMT_Encode2(TargetOpcode::COPY),
        GIR_AddTempRegister, /*InsnID*/8, /*TempRegID*/7, /*TempRegFlags*/GIMT_Encode2(RegState::Define),
        GIR_CopySubReg, /*NewInsnID*/8, /*OldInsnID*/2, /*OpIdx*/2, /*SubRegIdx*/GIMT_Encode2(11), // z
        GIR_ConstrainOperandRC, /*InsnID*/8, /*Op*/0, GIMT_Encode2(AMDGPU::VGPR_32RegClassID),
        GIR_ConstrainOperandRC, /*InsnID*/8, /*Op*/1, GIMT_Encode2(AMDGPU::VReg_64RegClassID),
        GIR_BuildMI, /*InsnID*/7, /*Opcode*/GIMT_Encode2(TargetOpcode::COPY),
        GIR_AddTempRegister, /*InsnID*/7, /*TempRegID*/6, /*TempRegFlags*/GIMT_Encode2(RegState::Define),
        GIR_CopySubReg, /*NewInsnID*/7, /*OldInsnID*/2, /*OpIdx*/1, /*SubRegIdx*/GIMT_Encode2(11), // y
        GIR_ConstrainOperandRC, /*InsnID*/7, /*Op*/0, GIMT_Encode2(AMDGPU::VGPR_32RegClassID),
        GIR_ConstrainOperandRC, /*InsnID*/7, /*Op*/1, GIMT_Encode2(AMDGPU::VReg_64RegClassID),
        GIR_BuildMI, /*InsnID*/6, /*Opcode*/GIMT_Encode2(TargetOpcode::COPY),
        GIR_AddTempRegister, /*InsnID*/6, /*TempRegID*/5, /*TempRegFlags*/GIMT_Encode2(RegState::Define),
        GIR_CopySubReg, /*NewInsnID*/6, /*OldInsnID*/1, /*OpIdx*/2, /*SubRegIdx*/GIMT_Encode2(11), // x
        GIR_ConstrainOperandRC, /*InsnID*/6, /*Op*/0, GIMT_Encode2(AMDGPU::VGPR_32RegClassID),
        GIR_ConstrainOperandRC, /*InsnID*/6, /*Op*/1, GIMT_Encode2(AMDGPU::VReg_64RegClassID),
        GIR_BuildMI, /*InsnID*/5, /*Opcode*/GIMT_Encode2(AMDGPU::V_BFI_B32_e64),
        GIR_AddTempRegister, /*InsnID*/5, /*TempRegID*/4, /*TempRegFlags*/GIMT_Encode2(RegState::Define),
        GIR_AddSimpleTempRegister, /*InsnID*/5, /*TempRegID*/5,
        GIR_AddSimpleTempRegister, /*InsnID*/5, /*TempRegID*/6,
        GIR_AddSimpleTempRegister, /*InsnID*/5, /*TempRegID*/7,
        GIR_ConstrainSelectedInstOperands, /*InsnID*/5,
        GIR_BuildMI, /*InsnID*/4, /*Opcode*/GIMT_Encode2(TargetOpcode::COPY),
        GIR_AddTempRegister, /*InsnID*/4, /*TempRegID*/3, /*TempRegFlags*/GIMT_Encode2(RegState::Define),
        GIR_CopySubReg, /*NewInsnID*/4, /*OldInsnID*/2, /*OpIdx*/2, /*SubRegIdx*/GIMT_Encode2(3), // z
        GIR_ConstrainOperandRC, /*InsnID*/4, /*Op*/0, GIMT_Encode2(AMDGPU::VGPR_32RegClassID),
        GIR_ConstrainOperandRC, /*InsnID*/4, /*Op*/1, GIMT_Encode2(AMDGPU::VReg_64RegClassID),
        GIR_BuildMI, /*InsnID*/3, /*Opcode*/GIMT_Encode2(TargetOpcode::COPY),
        GIR_AddTempRegister, /*InsnID*/3, /*TempRegID*/2, /*TempRegFlags*/GIMT_Encode2(RegState::Define),
        GIR_CopySubReg, /*NewInsnID*/3, /*OldInsnID*/2, /*OpIdx*/1, /*SubRegIdx*/GIMT_Encode2(3), // y
        GIR_ConstrainOperandRC, /*InsnID*/3, /*Op*/0, GIMT_Encode2(AMDGPU::VGPR_32RegClassID),
        GIR_ConstrainOperandRC, /*InsnID*/3, /*Op*/1, GIMT_Encode2(AMDGPU::VReg_64RegClassID),
        GIR_BuildMI, /*InsnID*/2, /*Opcode*/GIMT_Encode2(TargetOpcode::COPY),
        GIR_AddTempRegister, /*InsnID*/2, /*TempRegID*/1, /*TempRegFlags*/GIMT_Encode2(RegState::Define),
        GIR_CopySubReg, /*NewInsnID*/2, /*OldInsnID*/1, /*OpIdx*/2, /*SubRegIdx*/GIMT_Encode2(3), // x
        GIR_ConstrainOperandRC, /*InsnID*/2, /*Op*/0, GIMT_Encode2(AMDGPU::VGPR_32RegClassID),
        GIR_ConstrainOperandRC, /*InsnID*/2, /*Op*/1, GIMT_Encode2(AMDGPU::VReg_64RegClassID),
        GIR_BuildMI, /*InsnID*/1, /*Opcode*/GIMT_Encode2(AMDGPU::V_BFI_B32_e64),
        GIR_AddTempRegister, /*InsnID*/1, /*TempRegID*/0, /*TempRegFlags*/GIMT_Encode2(RegState::Define),
        GIR_AddSimpleTempRegister, /*InsnID*/1, /*TempRegID*/1,
        GIR_AddSimpleTempRegister, /*InsnID*/1, /*TempRegID*/2,
        GIR_AddSimpleTempRegister, /*InsnID*/1, /*TempRegID*/3,
        GIR_ConstrainSelectedInstOperands, /*InsnID*/1,
        GIR_BuildMI, /*InsnID*/0, /*Opcode*/GIMT_Encode2(TargetOpcode::REG_SEQUENCE),
        GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/0, // DstI[dst]
        GIR_AddSimpleTempRegister, /*InsnID*/0, /*TempRegID*/0,
        GIR_AddImm8, /*InsnID*/0, /*SubRegIndex*/3,
        GIR_AddSimpleTempRegister, /*InsnID*/0, /*TempRegID*/4,
        GIR_AddImm8, /*InsnID*/0, /*SubRegIndex*/11,
        GIR_ConstrainOperandRC, /*InsnID*/0, /*Op*/0, GIMT_Encode2(AMDGPU::VReg_64RegClassID),
        GIR_ConstrainOperandRC, /*InsnID*/0, /*Op*/1, GIMT_Encode2(AMDGPU::VGPR_32RegClassID),
        GIR_ConstrainOperandRC, /*InsnID*/0, /*Op*/3, GIMT_Encode2(AMDGPU::VGPR_32RegClassID),
        GIR_EraseFromParent, /*InsnID*/0,
        // GIR_Coverage, 9897,
        GIR_Done,
      // Label 411: @36793
      GIM_Try, /*On fail goto*//*Label 412*/ GIMT_Encode4(37100), // Rule ID 9898 //
        GIM_CheckRegBankForClass, /*MI*/0, /*Op*/0, /*RC*/GIMT_Encode2(AMDGPU::VReg_64RegClassID),
        GIM_RecordInsnIgnoreCopies, /*DefineMI*/1, /*MI*/0, /*OpIdx*/1, // MIs[1]
        GIM_CheckOpcode, /*MI*/1, GIMT_Encode2(TargetOpcode::G_AND),
        GIM_CheckType, /*MI*/1, /*Op*/1, /*Type*/GILLT_s64,
        GIM_CheckType, /*MI*/1, /*Op*/2, /*Type*/GILLT_s64,
        GIM_RecordInsnIgnoreCopies, /*DefineMI*/2, /*MI*/1, /*OpIdx*/1, // MIs[2]
        GIM_CheckOpcode, /*MI*/2, GIMT_Encode2(TargetOpcode::G_XOR),
        GIM_CheckType, /*MI*/2, /*Op*/1, /*Type*/GILLT_s64,
        GIM_CheckType, /*MI*/2, /*Op*/2, /*Type*/GILLT_s64,
        // MIs[0] z
        GIM_CheckIsSameOperandIgnoreCopies, /*MI*/0, /*OpIdx*/2, /*OtherMI*/2, /*OtherOpIdx*/1,
        GIM_CheckCxxInsnPredicate, /*MI*/0, /*FnId*/GIMT_Encode2(GICXXPred_MI_Predicate_anonymous_22559),
        GIM_CheckIsSafeToFold, /*InsnID*/1,
        GIM_CheckIsSafeToFold, /*InsnID*/2,
        // (xor:{ *:[i64] } (and:{ *:[i64] } (xor:{ *:[i64] } i64:{ *:[i64] }:$z, i64:{ *:[i64] }:$y), i64:{ *:[i64] }:$x), i64:{ *:[i64] }:$z)<<P:Predicate_anonymous_22559>>  =>  (REG_SEQUENCE:{ *:[i64] } VReg_64:{ *:[i32] }, (V_BFI_B32_e64:{ *:[i16] } (EXTRACT_SUBREG:{ *:[i32] } VReg_64:{ *:[i64] }:$x, sub0:{ *:[i32] }), (EXTRACT_SUBREG:{ *:[i32] } VReg_64:{ *:[i64] }:$y, sub0:{ *:[i32] }), (EXTRACT_SUBREG:{ *:[i32] } VReg_64:{ *:[i64] }:$z, sub0:{ *:[i32] })), sub0:{ *:[i32] }, (V_BFI_B32_e64:{ *:[i16] } (EXTRACT_SUBREG:{ *:[i32] } VReg_64:{ *:[i64] }:$x, sub1:{ *:[i32] }), (EXTRACT_SUBREG:{ *:[i32] } VReg_64:{ *:[i64] }:$y, sub1:{ *:[i32] }), (EXTRACT_SUBREG:{ *:[i32] } VReg_64:{ *:[i64] }:$z, sub1:{ *:[i32] })), sub1:{ *:[i32] })
        GIR_MakeTempReg, /*TempRegID*/0, /*TypeID*/GILLT_s16,
        GIR_MakeTempReg, /*TempRegID*/1, /*TypeID*/GILLT_s32,
        GIR_MakeTempReg, /*TempRegID*/2, /*TypeID*/GILLT_s32,
        GIR_MakeTempReg, /*TempRegID*/3, /*TypeID*/GILLT_s32,
        GIR_MakeTempReg, /*TempRegID*/4, /*TypeID*/GILLT_s16,
        GIR_MakeTempReg, /*TempRegID*/5, /*TypeID*/GILLT_s32,
        GIR_MakeTempReg, /*TempRegID*/6, /*TypeID*/GILLT_s32,
        GIR_MakeTempReg, /*TempRegID*/7, /*TypeID*/GILLT_s32,
        GIR_BuildMI, /*InsnID*/8, /*Opcode*/GIMT_Encode2(TargetOpcode::COPY),
        GIR_AddTempRegister, /*InsnID*/8, /*TempRegID*/7, /*TempRegFlags*/GIMT_Encode2(RegState::Define),
        GIR_CopySubReg, /*NewInsnID*/8, /*OldInsnID*/2, /*OpIdx*/1, /*SubRegIdx*/GIMT_Encode2(11), // z
        GIR_ConstrainOperandRC, /*InsnID*/8, /*Op*/0, GIMT_Encode2(AMDGPU::VGPR_32RegClassID),
        GIR_ConstrainOperandRC, /*InsnID*/8, /*Op*/1, GIMT_Encode2(AMDGPU::VReg_64RegClassID),
        GIR_BuildMI, /*InsnID*/7, /*Opcode*/GIMT_Encode2(TargetOpcode::COPY),
        GIR_AddTempRegister, /*InsnID*/7, /*TempRegID*/6, /*TempRegFlags*/GIMT_Encode2(RegState::Define),
        GIR_CopySubReg, /*NewInsnID*/7, /*OldInsnID*/2, /*OpIdx*/2, /*SubRegIdx*/GIMT_Encode2(11), // y
        GIR_ConstrainOperandRC, /*InsnID*/7, /*Op*/0, GIMT_Encode2(AMDGPU::VGPR_32RegClassID),
        GIR_ConstrainOperandRC, /*InsnID*/7, /*Op*/1, GIMT_Encode2(AMDGPU::VReg_64RegClassID),
        GIR_BuildMI, /*InsnID*/6, /*Opcode*/GIMT_Encode2(TargetOpcode::COPY),
        GIR_AddTempRegister, /*InsnID*/6, /*TempRegID*/5, /*TempRegFlags*/GIMT_Encode2(RegState::Define),
        GIR_CopySubReg, /*NewInsnID*/6, /*OldInsnID*/1, /*OpIdx*/2, /*SubRegIdx*/GIMT_Encode2(11), // x
        GIR_ConstrainOperandRC, /*InsnID*/6, /*Op*/0, GIMT_Encode2(AMDGPU::VGPR_32RegClassID),
        GIR_ConstrainOperandRC, /*InsnID*/6, /*Op*/1, GIMT_Encode2(AMDGPU::VReg_64RegClassID),
        GIR_BuildMI, /*InsnID*/5, /*Opcode*/GIMT_Encode2(AMDGPU::V_BFI_B32_e64),
        GIR_AddTempRegister, /*InsnID*/5, /*TempRegID*/4, /*TempRegFlags*/GIMT_Encode2(RegState::Define),
        GIR_AddSimpleTempRegister, /*InsnID*/5, /*TempRegID*/5,
        GIR_AddSimpleTempRegister, /*InsnID*/5, /*TempRegID*/6,
        GIR_AddSimpleTempRegister, /*InsnID*/5, /*TempRegID*/7,
        GIR_ConstrainSelectedInstOperands, /*InsnID*/5,
        GIR_BuildMI, /*InsnID*/4, /*Opcode*/GIMT_Encode2(TargetOpcode::COPY),
        GIR_AddTempRegister, /*InsnID*/4, /*TempRegID*/3, /*TempRegFlags*/GIMT_Encode2(RegState::Define),
        GIR_CopySubReg, /*NewInsnID*/4, /*OldInsnID*/2, /*OpIdx*/1, /*SubRegIdx*/GIMT_Encode2(3), // z
        GIR_ConstrainOperandRC, /*InsnID*/4, /*Op*/0, GIMT_Encode2(AMDGPU::VGPR_32RegClassID),
        GIR_ConstrainOperandRC, /*InsnID*/4, /*Op*/1, GIMT_Encode2(AMDGPU::VReg_64RegClassID),
        GIR_BuildMI, /*InsnID*/3, /*Opcode*/GIMT_Encode2(TargetOpcode::COPY),
        GIR_AddTempRegister, /*InsnID*/3, /*TempRegID*/2, /*TempRegFlags*/GIMT_Encode2(RegState::Define),
        GIR_CopySubReg, /*NewInsnID*/3, /*OldInsnID*/2, /*OpIdx*/2, /*SubRegIdx*/GIMT_Encode2(3), // y
        GIR_ConstrainOperandRC, /*InsnID*/3, /*Op*/0, GIMT_Encode2(AMDGPU::VGPR_32RegClassID),
        GIR_ConstrainOperandRC, /*InsnID*/3, /*Op*/1, GIMT_Encode2(AMDGPU::VReg_64RegClassID),
        GIR_BuildMI, /*InsnID*/2, /*Opcode*/GIMT_Encode2(TargetOpcode::COPY),
        GIR_AddTempRegister, /*InsnID*/2, /*TempRegID*/1, /*TempRegFlags*/GIMT_Encode2(RegState::Define),
        GIR_CopySubReg, /*NewInsnID*/2, /*OldInsnID*/1, /*OpIdx*/2, /*SubRegIdx*/GIMT_Encode2(3), // x
        GIR_ConstrainOperandRC, /*InsnID*/2, /*Op*/0, GIMT_Encode2(AMDGPU::VGPR_32RegClassID),
        GIR_ConstrainOperandRC, /*InsnID*/2, /*Op*/1, GIMT_Encode2(AMDGPU::VReg_64RegClassID),
        GIR_BuildMI, /*InsnID*/1, /*Opcode*/GIMT_Encode2(AMDGPU::V_BFI_B32_e64),
        GIR_AddTempRegister, /*InsnID*/1, /*TempRegID*/0, /*TempRegFlags*/GIMT_Encode2(RegState::Define),
        GIR_AddSimpleTempRegister, /*InsnID*/1, /*TempRegID*/1,
        GIR_AddSimpleTempRegister, /*InsnID*/1, /*TempRegID*/2,
        GIR_AddSimpleTempRegister, /*InsnID*/1, /*TempRegID*/3,
        GIR_ConstrainSelectedInstOperands, /*InsnID*/1,
        GIR_BuildMI, /*InsnID*/0, /*Opcode*/GIMT_Encode2(TargetOpcode::REG_SEQUENCE),
        GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/0, // DstI[dst]
        GIR_AddSimpleTempRegister, /*InsnID*/0, /*TempRegID*/0,
        GIR_AddImm8, /*InsnID*/0, /*SubRegIndex*/3,
        GIR_AddSimpleTempRegister, /*InsnID*/0, /*TempRegID*/4,
        GIR_AddImm8, /*InsnID*/0, /*SubRegIndex*/11,
        GIR_ConstrainOperandRC, /*InsnID*/0, /*Op*/0, GIMT_Encode2(AMDGPU::VReg_64RegClassID),
        GIR_ConstrainOperandRC, /*InsnID*/0, /*Op*/1, GIMT_Encode2(AMDGPU::VGPR_32RegClassID),
        GIR_ConstrainOperandRC, /*InsnID*/0, /*Op*/3, GIMT_Encode2(AMDGPU::VGPR_32RegClassID),
        GIR_EraseFromParent, /*InsnID*/0,
        // GIR_Coverage, 9898,
        GIR_Done,
      // Label 412: @37100
      GIM_Try, /*On fail goto*//*Label 413*/ GIMT_Encode4(37407), // Rule ID 9895 //
        GIM_CheckRegBankForClass, /*MI*/0, /*Op*/0, /*RC*/GIMT_Encode2(AMDGPU::VReg_64RegClassID),
        GIM_RecordInsnIgnoreCopies, /*DefineMI*/1, /*MI*/0, /*OpIdx*/1, // MIs[1]
        GIM_CheckOpcode, /*MI*/1, GIMT_Encode2(TargetOpcode::G_AND),
        GIM_CheckType, /*MI*/1, /*Op*/1, /*Type*/GILLT_s64,
        GIM_CheckType, /*MI*/1, /*Op*/2, /*Type*/GILLT_s64,
        GIM_RecordInsnIgnoreCopies, /*DefineMI*/2, /*MI*/1, /*OpIdx*/2, // MIs[2]
        GIM_CheckOpcode, /*MI*/2, GIMT_Encode2(TargetOpcode::G_XOR),
        GIM_CheckType, /*MI*/2, /*Op*/1, /*Type*/GILLT_s64,
        GIM_CheckType, /*MI*/2, /*Op*/2, /*Type*/GILLT_s64,
        // MIs[0] z
        GIM_CheckIsSameOperandIgnoreCopies, /*MI*/0, /*OpIdx*/2, /*OtherMI*/2, /*OtherOpIdx*/2,
        GIM_CheckCxxInsnPredicate, /*MI*/0, /*FnId*/GIMT_Encode2(GICXXPred_MI_Predicate_anonymous_22559),
        GIM_CheckIsSafeToFold, /*InsnID*/1,
        GIM_CheckIsSafeToFold, /*InsnID*/2,
        // (xor:{ *:[i64] } (and:{ *:[i64] } i64:{ *:[i64] }:$x, (xor:{ *:[i64] } i64:{ *:[i64] }:$y, i64:{ *:[i64] }:$z)), i64:{ *:[i64] }:$z)<<P:Predicate_anonymous_22559>>  =>  (REG_SEQUENCE:{ *:[i64] } VReg_64:{ *:[i32] }, (V_BFI_B32_e64:{ *:[i16] } (EXTRACT_SUBREG:{ *:[i32] } VReg_64:{ *:[i64] }:$x, sub0:{ *:[i32] }), (EXTRACT_SUBREG:{ *:[i32] } VReg_64:{ *:[i64] }:$y, sub0:{ *:[i32] }), (EXTRACT_SUBREG:{ *:[i32] } VReg_64:{ *:[i64] }:$z, sub0:{ *:[i32] })), sub0:{ *:[i32] }, (V_BFI_B32_e64:{ *:[i16] } (EXTRACT_SUBREG:{ *:[i32] } VReg_64:{ *:[i64] }:$x, sub1:{ *:[i32] }), (EXTRACT_SUBREG:{ *:[i32] } VReg_64:{ *:[i64] }:$y, sub1:{ *:[i32] }), (EXTRACT_SUBREG:{ *:[i32] } VReg_64:{ *:[i64] }:$z, sub1:{ *:[i32] })), sub1:{ *:[i32] })
        GIR_MakeTempReg, /*TempRegID*/0, /*TypeID*/GILLT_s16,
        GIR_MakeTempReg, /*TempRegID*/1, /*TypeID*/GILLT_s32,
        GIR_MakeTempReg, /*TempRegID*/2, /*TypeID*/GILLT_s32,
        GIR_MakeTempReg, /*TempRegID*/3, /*TypeID*/GILLT_s32,
        GIR_MakeTempReg, /*TempRegID*/4, /*TypeID*/GILLT_s16,
        GIR_MakeTempReg, /*TempRegID*/5, /*TypeID*/GILLT_s32,
        GIR_MakeTempReg, /*TempRegID*/6, /*TypeID*/GILLT_s32,
        GIR_MakeTempReg, /*TempRegID*/7, /*TypeID*/GILLT_s32,
        GIR_BuildMI, /*InsnID*/8, /*Opcode*/GIMT_Encode2(TargetOpcode::COPY),
        GIR_AddTempRegister, /*InsnID*/8, /*TempRegID*/7, /*TempRegFlags*/GIMT_Encode2(RegState::Define),
        GIR_CopySubReg, /*NewInsnID*/8, /*OldInsnID*/2, /*OpIdx*/2, /*SubRegIdx*/GIMT_Encode2(11), // z
        GIR_ConstrainOperandRC, /*InsnID*/8, /*Op*/0, GIMT_Encode2(AMDGPU::VGPR_32RegClassID),
        GIR_ConstrainOperandRC, /*InsnID*/8, /*Op*/1, GIMT_Encode2(AMDGPU::VReg_64RegClassID),
        GIR_BuildMI, /*InsnID*/7, /*Opcode*/GIMT_Encode2(TargetOpcode::COPY),
        GIR_AddTempRegister, /*InsnID*/7, /*TempRegID*/6, /*TempRegFlags*/GIMT_Encode2(RegState::Define),
        GIR_CopySubReg, /*NewInsnID*/7, /*OldInsnID*/2, /*OpIdx*/1, /*SubRegIdx*/GIMT_Encode2(11), // y
        GIR_ConstrainOperandRC, /*InsnID*/7, /*Op*/0, GIMT_Encode2(AMDGPU::VGPR_32RegClassID),
        GIR_ConstrainOperandRC, /*InsnID*/7, /*Op*/1, GIMT_Encode2(AMDGPU::VReg_64RegClassID),
        GIR_BuildMI, /*InsnID*/6, /*Opcode*/GIMT_Encode2(TargetOpcode::COPY),
        GIR_AddTempRegister, /*InsnID*/6, /*TempRegID*/5, /*TempRegFlags*/GIMT_Encode2(RegState::Define),
        GIR_CopySubReg, /*NewInsnID*/6, /*OldInsnID*/1, /*OpIdx*/1, /*SubRegIdx*/GIMT_Encode2(11), // x
        GIR_ConstrainOperandRC, /*InsnID*/6, /*Op*/0, GIMT_Encode2(AMDGPU::VGPR_32RegClassID),
        GIR_ConstrainOperandRC, /*InsnID*/6, /*Op*/1, GIMT_Encode2(AMDGPU::VReg_64RegClassID),
        GIR_BuildMI, /*InsnID*/5, /*Opcode*/GIMT_Encode2(AMDGPU::V_BFI_B32_e64),
        GIR_AddTempRegister, /*InsnID*/5, /*TempRegID*/4, /*TempRegFlags*/GIMT_Encode2(RegState::Define),
        GIR_AddSimpleTempRegister, /*InsnID*/5, /*TempRegID*/5,
        GIR_AddSimpleTempRegister, /*InsnID*/5, /*TempRegID*/6,
        GIR_AddSimpleTempRegister, /*InsnID*/5, /*TempRegID*/7,
        GIR_ConstrainSelectedInstOperands, /*InsnID*/5,
        GIR_BuildMI, /*InsnID*/4, /*Opcode*/GIMT_Encode2(TargetOpcode::COPY),
        GIR_AddTempRegister, /*InsnID*/4, /*TempRegID*/3, /*TempRegFlags*/GIMT_Encode2(RegState::Define),
        GIR_CopySubReg, /*NewInsnID*/4, /*OldInsnID*/2, /*OpIdx*/2, /*SubRegIdx*/GIMT_Encode2(3), // z
        GIR_ConstrainOperandRC, /*InsnID*/4, /*Op*/0, GIMT_Encode2(AMDGPU::VGPR_32RegClassID),
        GIR_ConstrainOperandRC, /*InsnID*/4, /*Op*/1, GIMT_Encode2(AMDGPU::VReg_64RegClassID),
        GIR_BuildMI, /*InsnID*/3, /*Opcode*/GIMT_Encode2(TargetOpcode::COPY),
        GIR_AddTempRegister, /*InsnID*/3, /*TempRegID*/2, /*TempRegFlags*/GIMT_Encode2(RegState::Define),
        GIR_CopySubReg, /*NewInsnID*/3, /*OldInsnID*/2, /*OpIdx*/1, /*SubRegIdx*/GIMT_Encode2(3), // y
        GIR_ConstrainOperandRC, /*InsnID*/3, /*Op*/0, GIMT_Encode2(AMDGPU::VGPR_32RegClassID),
        GIR_ConstrainOperandRC, /*InsnID*/3, /*Op*/1, GIMT_Encode2(AMDGPU::VReg_64RegClassID),
        GIR_BuildMI, /*InsnID*/2, /*Opcode*/GIMT_Encode2(TargetOpcode::COPY),
        GIR_AddTempRegister, /*InsnID*/2, /*TempRegID*/1, /*TempRegFlags*/GIMT_Encode2(RegState::Define),
        GIR_CopySubReg, /*NewInsnID*/2, /*OldInsnID*/1, /*OpIdx*/1, /*SubRegIdx*/GIMT_Encode2(3), // x
        GIR_ConstrainOperandRC, /*InsnID*/2, /*Op*/0, GIMT_Encode2(AMDGPU::VGPR_32RegClassID),
        GIR_ConstrainOperandRC, /*InsnID*/2, /*Op*/1, GIMT_Encode2(AMDGPU::VReg_64RegClassID),
        GIR_BuildMI, /*InsnID*/1, /*Opcode*/GIMT_Encode2(AMDGPU::V_BFI_B32_e64),
        GIR_AddTempRegister, /*InsnID*/1, /*TempRegID*/0, /*TempRegFlags*/GIMT_Encode2(RegState::Define),
        GIR_AddSimpleTempRegister, /*InsnID*/1, /*TempRegID*/1,
        GIR_AddSimpleTempRegister, /*InsnID*/1, /*TempRegID*/2,
        GIR_AddSimpleTempRegister, /*InsnID*/1, /*TempRegID*/3,
        GIR_ConstrainSelectedInstOperands, /*InsnID*/1,
        GIR_BuildMI, /*InsnID*/0, /*Opcode*/GIMT_Encode2(TargetOpcode::REG_SEQUENCE),
        GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/0, // DstI[dst]
        GIR_AddSimpleTempRegister, /*InsnID*/0, /*TempRegID*/0,
        GIR_AddImm8, /*InsnID*/0, /*SubRegIndex*/3,
        GIR_AddSimpleTempRegister, /*InsnID*/0, /*TempRegID*/4,
        GIR_AddImm8, /*InsnID*/0, /*SubRegIndex*/11,
        GIR_ConstrainOperandRC, /*InsnID*/0, /*Op*/0, GIMT_Encode2(AMDGPU::VReg_64RegClassID),
        GIR_ConstrainOperandRC, /*InsnID*/0, /*Op*/1, GIMT_Encode2(AMDGPU::VGPR_32RegClassID),
        GIR_ConstrainOperandRC, /*InsnID*/0, /*Op*/3, GIMT_Encode2(AMDGPU::VGPR_32RegClassID),
        GIR_EraseFromParent, /*InsnID*/0,
        // GIR_Coverage, 9895,
        GIR_Done,
      // Label 413: @37407
      GIM_Try, /*On fail goto*//*Label 414*/ GIMT_Encode4(37714), // Rule ID 9896 //
        GIM_CheckRegBankForClass, /*MI*/0, /*Op*/0, /*RC*/GIMT_Encode2(AMDGPU::VReg_64RegClassID),
        GIM_RecordInsnIgnoreCopies, /*DefineMI*/1, /*MI*/0, /*OpIdx*/1, // MIs[1]
        GIM_CheckOpcode, /*MI*/1, GIMT_Encode2(TargetOpcode::G_AND),
        GIM_CheckType, /*MI*/1, /*Op*/1, /*Type*/GILLT_s64,
        GIM_CheckType, /*MI*/1, /*Op*/2, /*Type*/GILLT_s64,
        GIM_RecordInsnIgnoreCopies, /*DefineMI*/2, /*MI*/1, /*OpIdx*/2, // MIs[2]
        GIM_CheckOpcode, /*MI*/2, GIMT_Encode2(TargetOpcode::G_XOR),
        GIM_CheckType, /*MI*/2, /*Op*/1, /*Type*/GILLT_s64,
        GIM_CheckType, /*MI*/2, /*Op*/2, /*Type*/GILLT_s64,
        // MIs[0] z
        GIM_CheckIsSameOperandIgnoreCopies, /*MI*/0, /*OpIdx*/2, /*OtherMI*/2, /*OtherOpIdx*/1,
        GIM_CheckCxxInsnPredicate, /*MI*/0, /*FnId*/GIMT_Encode2(GICXXPred_MI_Predicate_anonymous_22559),
        GIM_CheckIsSafeToFold, /*InsnID*/1,
        GIM_CheckIsSafeToFold, /*InsnID*/2,
        // (xor:{ *:[i64] } (and:{ *:[i64] } i64:{ *:[i64] }:$x, (xor:{ *:[i64] } i64:{ *:[i64] }:$z, i64:{ *:[i64] }:$y)), i64:{ *:[i64] }:$z)<<P:Predicate_anonymous_22559>>  =>  (REG_SEQUENCE:{ *:[i64] } VReg_64:{ *:[i32] }, (V_BFI_B32_e64:{ *:[i16] } (EXTRACT_SUBREG:{ *:[i32] } VReg_64:{ *:[i64] }:$x, sub0:{ *:[i32] }), (EXTRACT_SUBREG:{ *:[i32] } VReg_64:{ *:[i64] }:$y, sub0:{ *:[i32] }), (EXTRACT_SUBREG:{ *:[i32] } VReg_64:{ *:[i64] }:$z, sub0:{ *:[i32] })), sub0:{ *:[i32] }, (V_BFI_B32_e64:{ *:[i16] } (EXTRACT_SUBREG:{ *:[i32] } VReg_64:{ *:[i64] }:$x, sub1:{ *:[i32] }), (EXTRACT_SUBREG:{ *:[i32] } VReg_64:{ *:[i64] }:$y, sub1:{ *:[i32] }), (EXTRACT_SUBREG:{ *:[i32] } VReg_64:{ *:[i64] }:$z, sub1:{ *:[i32] })), sub1:{ *:[i32] })
        GIR_MakeTempReg, /*TempRegID*/0, /*TypeID*/GILLT_s16,
        GIR_MakeTempReg, /*TempRegID*/1, /*TypeID*/GILLT_s32,
        GIR_MakeTempReg, /*TempRegID*/2, /*TypeID*/GILLT_s32,
        GIR_MakeTempReg, /*TempRegID*/3, /*TypeID*/GILLT_s32,
        GIR_MakeTempReg, /*TempRegID*/4, /*TypeID*/GILLT_s16,
        GIR_MakeTempReg, /*TempRegID*/5, /*TypeID*/GILLT_s32,
        GIR_MakeTempReg, /*TempRegID*/6, /*TypeID*/GILLT_s32,
        GIR_MakeTempReg, /*TempRegID*/7, /*TypeID*/GILLT_s32,
        GIR_BuildMI, /*InsnID*/8, /*Opcode*/GIMT_Encode2(TargetOpcode::COPY),
        GIR_AddTempRegister, /*InsnID*/8, /*TempRegID*/7, /*TempRegFlags*/GIMT_Encode2(RegState::Define),
        GIR_CopySubReg, /*NewInsnID*/8, /*OldInsnID*/2, /*OpIdx*/1, /*SubRegIdx*/GIMT_Encode2(11), // z
        GIR_ConstrainOperandRC, /*InsnID*/8, /*Op*/0, GIMT_Encode2(AMDGPU::VGPR_32RegClassID),
        GIR_ConstrainOperandRC, /*InsnID*/8, /*Op*/1, GIMT_Encode2(AMDGPU::VReg_64RegClassID),
        GIR_BuildMI, /*InsnID*/7, /*Opcode*/GIMT_Encode2(TargetOpcode::COPY),
        GIR_AddTempRegister, /*InsnID*/7, /*TempRegID*/6, /*TempRegFlags*/GIMT_Encode2(RegState::Define),
        GIR_CopySubReg, /*NewInsnID*/7, /*OldInsnID*/2, /*OpIdx*/2, /*SubRegIdx*/GIMT_Encode2(11), // y
        GIR_ConstrainOperandRC, /*InsnID*/7, /*Op*/0, GIMT_Encode2(AMDGPU::VGPR_32RegClassID),
        GIR_ConstrainOperandRC, /*InsnID*/7, /*Op*/1, GIMT_Encode2(AMDGPU::VReg_64RegClassID),
        GIR_BuildMI, /*InsnID*/6, /*Opcode*/GIMT_Encode2(TargetOpcode::COPY),
        GIR_AddTempRegister, /*InsnID*/6, /*TempRegID*/5, /*TempRegFlags*/GIMT_Encode2(RegState::Define),
        GIR_CopySubReg, /*NewInsnID*/6, /*OldInsnID*/1, /*OpIdx*/1, /*SubRegIdx*/GIMT_Encode2(11), // x
        GIR_ConstrainOperandRC, /*InsnID*/6, /*Op*/0, GIMT_Encode2(AMDGPU::VGPR_32RegClassID),
        GIR_ConstrainOperandRC, /*InsnID*/6, /*Op*/1, GIMT_Encode2(AMDGPU::VReg_64RegClassID),
        GIR_BuildMI, /*InsnID*/5, /*Opcode*/GIMT_Encode2(AMDGPU::V_BFI_B32_e64),
        GIR_AddTempRegister, /*InsnID*/5, /*TempRegID*/4, /*TempRegFlags*/GIMT_Encode2(RegState::Define),
        GIR_AddSimpleTempRegister, /*InsnID*/5, /*TempRegID*/5,
        GIR_AddSimpleTempRegister, /*InsnID*/5, /*TempRegID*/6,
        GIR_AddSimpleTempRegister, /*InsnID*/5, /*TempRegID*/7,
        GIR_ConstrainSelectedInstOperands, /*InsnID*/5,
        GIR_BuildMI, /*InsnID*/4, /*Opcode*/GIMT_Encode2(TargetOpcode::COPY),
        GIR_AddTempRegister, /*InsnID*/4, /*TempRegID*/3, /*TempRegFlags*/GIMT_Encode2(RegState::Define),
        GIR_CopySubReg, /*NewInsnID*/4, /*OldInsnID*/2, /*OpIdx*/1, /*SubRegIdx*/GIMT_Encode2(3), // z
        GIR_ConstrainOperandRC, /*InsnID*/4, /*Op*/0, GIMT_Encode2(AMDGPU::VGPR_32RegClassID),
        GIR_ConstrainOperandRC, /*InsnID*/4, /*Op*/1, GIMT_Encode2(AMDGPU::VReg_64RegClassID),
        GIR_BuildMI, /*InsnID*/3, /*Opcode*/GIMT_Encode2(TargetOpcode::COPY),
        GIR_AddTempRegister, /*InsnID*/3, /*TempRegID*/2, /*TempRegFlags*/GIMT_Encode2(RegState::Define),
        GIR_CopySubReg, /*NewInsnID*/3, /*OldInsnID*/2, /*OpIdx*/2, /*SubRegIdx*/GIMT_Encode2(3), // y
        GIR_ConstrainOperandRC, /*InsnID*/3, /*Op*/0, GIMT_Encode2(AMDGPU::VGPR_32RegClassID),
        GIR_ConstrainOperandRC, /*InsnID*/3, /*Op*/1, GIMT_Encode2(AMDGPU::VReg_64RegClassID),
        GIR_BuildMI, /*InsnID*/2, /*Opcode*/GIMT_Encode2(TargetOpcode::COPY),
        GIR_AddTempRegister, /*InsnID*/2, /*TempRegID*/1, /*TempRegFlags*/GIMT_Encode2(RegState::Define),
        GIR_CopySubReg, /*NewInsnID*/2, /*OldInsnID*/1, /*OpIdx*/1, /*SubRegIdx*/GIMT_Encode2(3), // x
        GIR_ConstrainOperandRC, /*InsnID*/2, /*Op*/0, GIMT_Encode2(AMDGPU::VGPR_32RegClassID),
        GIR_ConstrainOperandRC, /*InsnID*/2, /*Op*/1, GIMT_Encode2(AMDGPU::VReg_64RegClassID),
        GIR_BuildMI, /*InsnID*/1, /*Opcode*/GIMT_Encode2(AMDGPU::V_BFI_B32_e64),
        GIR_AddTempRegister, /*InsnID*/1, /*TempRegID*/0, /*TempRegFlags*/GIMT_Encode2(RegState::Define),
        GIR_AddSimpleTempRegister, /*InsnID*/1, /*TempRegID*/1,
        GIR_AddSimpleTempRegister, /*InsnID*/1, /*TempRegID*/2,
        GIR_AddSimpleTempRegister, /*InsnID*/1, /*TempRegID*/3,
        GIR_ConstrainSelectedInstOperands, /*InsnID*/1,
        GIR_BuildMI, /*InsnID*/0, /*Opcode*/GIMT_Encode2(TargetOpcode::REG_SEQUENCE),
        GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/0, // DstI[dst]
        GIR_AddSimpleTempRegister, /*InsnID*/0, /*TempRegID*/0,
        GIR_AddImm8, /*InsnID*/0, /*SubRegIndex*/3,
        GIR_AddSimpleTempRegister, /*InsnID*/0, /*TempRegID*/4,
        GIR_AddImm8, /*InsnID*/0, /*SubRegIndex*/11,
        GIR_ConstrainOperandRC, /*InsnID*/0, /*Op*/0, GIMT_Encode2(AMDGPU::VReg_64RegClassID),
        GIR_ConstrainOperandRC, /*InsnID*/0, /*Op*/1, GIMT_Encode2(AMDGPU::VGPR_32RegClassID),
        GIR_ConstrainOperandRC, /*InsnID*/0, /*Op*/3, GIMT_Encode2(AMDGPU::VGPR_32RegClassID),
        GIR_EraseFromParent, /*InsnID*/0,
        // GIR_Coverage, 9896,
        GIR_Done,
      // Label 414: @37714
      GIM_Try, /*On fail goto*//*Label 415*/ GIMT_Encode4(38021), // Rule ID 9894 //
        GIM_CheckType, /*MI*/0, /*Op*/2, /*Type*/GILLT_s64,
        GIM_CheckRegBankForClass, /*MI*/0, /*Op*/0, /*RC*/GIMT_Encode2(AMDGPU::VReg_64RegClassID),
        GIM_RecordInsnIgnoreCopies, /*DefineMI*/1, /*MI*/0, /*OpIdx*/2, // MIs[1]
        GIM_CheckOpcode, /*MI*/1, GIMT_Encode2(TargetOpcode::G_AND),
        GIM_CheckType, /*MI*/1, /*Op*/1, /*Type*/GILLT_s64,
        GIM_CheckType, /*MI*/1, /*Op*/2, /*Type*/GILLT_s64,
        GIM_RecordInsnIgnoreCopies, /*DefineMI*/2, /*MI*/1, /*OpIdx*/1, // MIs[2]
        GIM_CheckOpcode, /*MI*/2, GIMT_Encode2(TargetOpcode::G_XOR),
        GIM_CheckType, /*MI*/2, /*Op*/2, /*Type*/GILLT_s64,
        // MIs[2] z
        GIM_CheckIsSameOperandIgnoreCopies, /*MI*/2, /*OpIdx*/1, /*OtherMI*/0, /*OtherOpIdx*/1,
        GIM_CheckCxxInsnPredicate, /*MI*/0, /*FnId*/GIMT_Encode2(GICXXPred_MI_Predicate_anonymous_22559),
        GIM_CheckIsSafeToFold, /*InsnID*/1,
        GIM_CheckIsSafeToFold, /*InsnID*/2,
        // (xor:{ *:[i64] } i64:{ *:[i64] }:$z, (and:{ *:[i64] } (xor:{ *:[i64] } i64:{ *:[i64] }:$z, i64:{ *:[i64] }:$y), i64:{ *:[i64] }:$x))<<P:Predicate_anonymous_22559>>  =>  (REG_SEQUENCE:{ *:[i64] } VReg_64:{ *:[i32] }, (V_BFI_B32_e64:{ *:[i16] } (EXTRACT_SUBREG:{ *:[i32] } VReg_64:{ *:[i64] }:$x, sub0:{ *:[i32] }), (EXTRACT_SUBREG:{ *:[i32] } VReg_64:{ *:[i64] }:$y, sub0:{ *:[i32] }), (EXTRACT_SUBREG:{ *:[i32] } VReg_64:{ *:[i64] }:$z, sub0:{ *:[i32] })), sub0:{ *:[i32] }, (V_BFI_B32_e64:{ *:[i16] } (EXTRACT_SUBREG:{ *:[i32] } VReg_64:{ *:[i64] }:$x, sub1:{ *:[i32] }), (EXTRACT_SUBREG:{ *:[i32] } VReg_64:{ *:[i64] }:$y, sub1:{ *:[i32] }), (EXTRACT_SUBREG:{ *:[i32] } VReg_64:{ *:[i64] }:$z, sub1:{ *:[i32] })), sub1:{ *:[i32] })
        GIR_MakeTempReg, /*TempRegID*/0, /*TypeID*/GILLT_s16,
        GIR_MakeTempReg, /*TempRegID*/1, /*TypeID*/GILLT_s32,
        GIR_MakeTempReg, /*TempRegID*/2, /*TypeID*/GILLT_s32,
        GIR_MakeTempReg, /*TempRegID*/3, /*TypeID*/GILLT_s32,
        GIR_MakeTempReg, /*TempRegID*/4, /*TypeID*/GILLT_s16,
        GIR_MakeTempReg, /*TempRegID*/5, /*TypeID*/GILLT_s32,
        GIR_MakeTempReg, /*TempRegID*/6, /*TypeID*/GILLT_s32,
        GIR_MakeTempReg, /*TempRegID*/7, /*TypeID*/GILLT_s32,
        GIR_BuildMI, /*InsnID*/8, /*Opcode*/GIMT_Encode2(TargetOpcode::COPY),
        GIR_AddTempRegister, /*InsnID*/8, /*TempRegID*/7, /*TempRegFlags*/GIMT_Encode2(RegState::Define),
        GIR_CopySubReg, /*NewInsnID*/8, /*OldInsnID*/0, /*OpIdx*/1, /*SubRegIdx*/GIMT_Encode2(11), // z
        GIR_ConstrainOperandRC, /*InsnID*/8, /*Op*/0, GIMT_Encode2(AMDGPU::VGPR_32RegClassID),
        GIR_ConstrainOperandRC, /*InsnID*/8, /*Op*/1, GIMT_Encode2(AMDGPU::VReg_64RegClassID),
        GIR_BuildMI, /*InsnID*/7, /*Opcode*/GIMT_Encode2(TargetOpcode::COPY),
        GIR_AddTempRegister, /*InsnID*/7, /*TempRegID*/6, /*TempRegFlags*/GIMT_Encode2(RegState::Define),
        GIR_CopySubReg, /*NewInsnID*/7, /*OldInsnID*/2, /*OpIdx*/2, /*SubRegIdx*/GIMT_Encode2(11), // y
        GIR_ConstrainOperandRC, /*InsnID*/7, /*Op*/0, GIMT_Encode2(AMDGPU::VGPR_32RegClassID),
        GIR_ConstrainOperandRC, /*InsnID*/7, /*Op*/1, GIMT_Encode2(AMDGPU::VReg_64RegClassID),
        GIR_BuildMI, /*InsnID*/6, /*Opcode*/GIMT_Encode2(TargetOpcode::COPY),
        GIR_AddTempRegister, /*InsnID*/6, /*TempRegID*/5, /*TempRegFlags*/GIMT_Encode2(RegState::Define),
        GIR_CopySubReg, /*NewInsnID*/6, /*OldInsnID*/1, /*OpIdx*/2, /*SubRegIdx*/GIMT_Encode2(11), // x
        GIR_ConstrainOperandRC, /*InsnID*/6, /*Op*/0, GIMT_Encode2(AMDGPU::VGPR_32RegClassID),
        GIR_ConstrainOperandRC, /*InsnID*/6, /*Op*/1, GIMT_Encode2(AMDGPU::VReg_64RegClassID),
        GIR_BuildMI, /*InsnID*/5, /*Opcode*/GIMT_Encode2(AMDGPU::V_BFI_B32_e64),
        GIR_AddTempRegister, /*InsnID*/5, /*TempRegID*/4, /*TempRegFlags*/GIMT_Encode2(RegState::Define),
        GIR_AddSimpleTempRegister, /*InsnID*/5, /*TempRegID*/5,
        GIR_AddSimpleTempRegister, /*InsnID*/5, /*TempRegID*/6,
        GIR_AddSimpleTempRegister, /*InsnID*/5, /*TempRegID*/7,
        GIR_ConstrainSelectedInstOperands, /*InsnID*/5,
        GIR_BuildMI, /*InsnID*/4, /*Opcode*/GIMT_Encode2(TargetOpcode::COPY),
        GIR_AddTempRegister, /*InsnID*/4, /*TempRegID*/3, /*TempRegFlags*/GIMT_Encode2(RegState::Define),
        GIR_CopySubReg, /*NewInsnID*/4, /*OldInsnID*/0, /*OpIdx*/1, /*SubRegIdx*/GIMT_Encode2(3), // z
        GIR_ConstrainOperandRC, /*InsnID*/4, /*Op*/0, GIMT_Encode2(AMDGPU::VGPR_32RegClassID),
        GIR_ConstrainOperandRC, /*InsnID*/4, /*Op*/1, GIMT_Encode2(AMDGPU::VReg_64RegClassID),
        GIR_BuildMI, /*InsnID*/3, /*Opcode*/GIMT_Encode2(TargetOpcode::COPY),
        GIR_AddTempRegister, /*InsnID*/3, /*TempRegID*/2, /*TempRegFlags*/GIMT_Encode2(RegState::Define),
        GIR_CopySubReg, /*NewInsnID*/3, /*OldInsnID*/2, /*OpIdx*/2, /*SubRegIdx*/GIMT_Encode2(3), // y
        GIR_ConstrainOperandRC, /*InsnID*/3, /*Op*/0, GIMT_Encode2(AMDGPU::VGPR_32RegClassID),
        GIR_ConstrainOperandRC, /*InsnID*/3, /*Op*/1, GIMT_Encode2(AMDGPU::VReg_64RegClassID),
        GIR_BuildMI, /*InsnID*/2, /*Opcode*/GIMT_Encode2(TargetOpcode::COPY),
        GIR_AddTempRegister, /*InsnID*/2, /*TempRegID*/1, /*TempRegFlags*/GIMT_Encode2(RegState::Define),
        GIR_CopySubReg, /*NewInsnID*/2, /*OldInsnID*/1, /*OpIdx*/2, /*SubRegIdx*/GIMT_Encode2(3), // x
        GIR_ConstrainOperandRC, /*InsnID*/2, /*Op*/0, GIMT_Encode2(AMDGPU::VGPR_32RegClassID),
        GIR_ConstrainOperandRC, /*InsnID*/2, /*Op*/1, GIMT_Encode2(AMDGPU::VReg_64RegClassID),
        GIR_BuildMI, /*InsnID*/1, /*Opcode*/GIMT_Encode2(AMDGPU::V_BFI_B32_e64),
        GIR_AddTempRegister, /*InsnID*/1, /*TempRegID*/0, /*TempRegFlags*/GIMT_Encode2(RegState::Define),
        GIR_AddSimpleTempRegister, /*InsnID*/1, /*TempRegID*/1,
        GIR_AddSimpleTempRegister, /*InsnID*/1, /*TempRegID*/2,
        GIR_AddSimpleTempRegister, /*InsnID*/1, /*TempRegID*/3,
        GIR_ConstrainSelectedInstOperands, /*InsnID*/1,
        GIR_BuildMI, /*InsnID*/0, /*Opcode*/GIMT_Encode2(TargetOpcode::REG_SEQUENCE),
        GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/0, // DstI[dst]
        GIR_AddSimpleTempRegister, /*InsnID*/0, /*TempRegID*/0,
        GIR_AddImm8, /*InsnID*/0, /*SubRegIndex*/3,
        GIR_AddSimpleTempRegister, /*InsnID*/0, /*TempRegID*/4,
        GIR_AddImm8, /*InsnID*/0, /*SubRegIndex*/11,
        GIR_ConstrainOperandRC, /*InsnID*/0, /*Op*/0, GIMT_Encode2(AMDGPU::VReg_64RegClassID),
        GIR_ConstrainOperandRC, /*InsnID*/0, /*Op*/1, GIMT_Encode2(AMDGPU::VGPR_32RegClassID),
        GIR_ConstrainOperandRC, /*InsnID*/0, /*Op*/3, GIMT_Encode2(AMDGPU::VGPR_32RegClassID),
        GIR_EraseFromParent, /*InsnID*/0,
        // GIR_Coverage, 9894,
        GIR_Done,
      // Label 415: @38021
      GIM_Try, /*On fail goto*//*Label 416*/ GIMT_Encode4(38328), // Rule ID 9893 //
        GIM_CheckType, /*MI*/0, /*Op*/2, /*Type*/GILLT_s64,
        GIM_CheckRegBankForClass, /*MI*/0, /*Op*/0, /*RC*/GIMT_Encode2(AMDGPU::VReg_64RegClassID),
        GIM_RecordInsnIgnoreCopies, /*DefineMI*/1, /*MI*/0, /*OpIdx*/2, // MIs[1]
        GIM_CheckOpcode, /*MI*/1, GIMT_Encode2(TargetOpcode::G_AND),
        GIM_CheckType, /*MI*/1, /*Op*/1, /*Type*/GILLT_s64,
        GIM_CheckType, /*MI*/1, /*Op*/2, /*Type*/GILLT_s64,
        GIM_RecordInsnIgnoreCopies, /*DefineMI*/2, /*MI*/1, /*OpIdx*/1, // MIs[2]
        GIM_CheckOpcode, /*MI*/2, GIMT_Encode2(TargetOpcode::G_XOR),
        GIM_CheckType, /*MI*/2, /*Op*/1, /*Type*/GILLT_s64,
        // MIs[2] z
        GIM_CheckIsSameOperandIgnoreCopies, /*MI*/2, /*OpIdx*/2, /*OtherMI*/0, /*OtherOpIdx*/1,
        GIM_CheckCxxInsnPredicate, /*MI*/0, /*FnId*/GIMT_Encode2(GICXXPred_MI_Predicate_anonymous_22559),
        GIM_CheckIsSafeToFold, /*InsnID*/1,
        GIM_CheckIsSafeToFold, /*InsnID*/2,
        // (xor:{ *:[i64] } i64:{ *:[i64] }:$z, (and:{ *:[i64] } (xor:{ *:[i64] } i64:{ *:[i64] }:$y, i64:{ *:[i64] }:$z), i64:{ *:[i64] }:$x))<<P:Predicate_anonymous_22559>>  =>  (REG_SEQUENCE:{ *:[i64] } VReg_64:{ *:[i32] }, (V_BFI_B32_e64:{ *:[i16] } (EXTRACT_SUBREG:{ *:[i32] } VReg_64:{ *:[i64] }:$x, sub0:{ *:[i32] }), (EXTRACT_SUBREG:{ *:[i32] } VReg_64:{ *:[i64] }:$y, sub0:{ *:[i32] }), (EXTRACT_SUBREG:{ *:[i32] } VReg_64:{ *:[i64] }:$z, sub0:{ *:[i32] })), sub0:{ *:[i32] }, (V_BFI_B32_e64:{ *:[i16] } (EXTRACT_SUBREG:{ *:[i32] } VReg_64:{ *:[i64] }:$x, sub1:{ *:[i32] }), (EXTRACT_SUBREG:{ *:[i32] } VReg_64:{ *:[i64] }:$y, sub1:{ *:[i32] }), (EXTRACT_SUBREG:{ *:[i32] } VReg_64:{ *:[i64] }:$z, sub1:{ *:[i32] })), sub1:{ *:[i32] })
        GIR_MakeTempReg, /*TempRegID*/0, /*TypeID*/GILLT_s16,
        GIR_MakeTempReg, /*TempRegID*/1, /*TypeID*/GILLT_s32,
        GIR_MakeTempReg, /*TempRegID*/2, /*TypeID*/GILLT_s32,
        GIR_MakeTempReg, /*TempRegID*/3, /*TypeID*/GILLT_s32,
        GIR_MakeTempReg, /*TempRegID*/4, /*TypeID*/GILLT_s16,
        GIR_MakeTempReg, /*TempRegID*/5, /*TypeID*/GILLT_s32,
        GIR_MakeTempReg, /*TempRegID*/6, /*TypeID*/GILLT_s32,
        GIR_MakeTempReg, /*TempRegID*/7, /*TypeID*/GILLT_s32,
        GIR_BuildMI, /*InsnID*/8, /*Opcode*/GIMT_Encode2(TargetOpcode::COPY),
        GIR_AddTempRegister, /*InsnID*/8, /*TempRegID*/7, /*TempRegFlags*/GIMT_Encode2(RegState::Define),
        GIR_CopySubReg, /*NewInsnID*/8, /*OldInsnID*/0, /*OpIdx*/1, /*SubRegIdx*/GIMT_Encode2(11), // z
        GIR_ConstrainOperandRC, /*InsnID*/8, /*Op*/0, GIMT_Encode2(AMDGPU::VGPR_32RegClassID),
        GIR_ConstrainOperandRC, /*InsnID*/8, /*Op*/1, GIMT_Encode2(AMDGPU::VReg_64RegClassID),
        GIR_BuildMI, /*InsnID*/7, /*Opcode*/GIMT_Encode2(TargetOpcode::COPY),
        GIR_AddTempRegister, /*InsnID*/7, /*TempRegID*/6, /*TempRegFlags*/GIMT_Encode2(RegState::Define),
        GIR_CopySubReg, /*NewInsnID*/7, /*OldInsnID*/2, /*OpIdx*/1, /*SubRegIdx*/GIMT_Encode2(11), // y
        GIR_ConstrainOperandRC, /*InsnID*/7, /*Op*/0, GIMT_Encode2(AMDGPU::VGPR_32RegClassID),
        GIR_ConstrainOperandRC, /*InsnID*/7, /*Op*/1, GIMT_Encode2(AMDGPU::VReg_64RegClassID),
        GIR_BuildMI, /*InsnID*/6, /*Opcode*/GIMT_Encode2(TargetOpcode::COPY),
        GIR_AddTempRegister, /*InsnID*/6, /*TempRegID*/5, /*TempRegFlags*/GIMT_Encode2(RegState::Define),
        GIR_CopySubReg, /*NewInsnID*/6, /*OldInsnID*/1, /*OpIdx*/2, /*SubRegIdx*/GIMT_Encode2(11), // x
        GIR_ConstrainOperandRC, /*InsnID*/6, /*Op*/0, GIMT_Encode2(AMDGPU::VGPR_32RegClassID),
        GIR_ConstrainOperandRC, /*InsnID*/6, /*Op*/1, GIMT_Encode2(AMDGPU::VReg_64RegClassID),
        GIR_BuildMI, /*InsnID*/5, /*Opcode*/GIMT_Encode2(AMDGPU::V_BFI_B32_e64),
        GIR_AddTempRegister, /*InsnID*/5, /*TempRegID*/4, /*TempRegFlags*/GIMT_Encode2(RegState::Define),
        GIR_AddSimpleTempRegister, /*InsnID*/5, /*TempRegID*/5,
        GIR_AddSimpleTempRegister, /*InsnID*/5, /*TempRegID*/6,
        GIR_AddSimpleTempRegister, /*InsnID*/5, /*TempRegID*/7,
        GIR_ConstrainSelectedInstOperands, /*InsnID*/5,
        GIR_BuildMI, /*InsnID*/4, /*Opcode*/GIMT_Encode2(TargetOpcode::COPY),
        GIR_AddTempRegister, /*InsnID*/4, /*TempRegID*/3, /*TempRegFlags*/GIMT_Encode2(RegState::Define),
        GIR_CopySubReg, /*NewInsnID*/4, /*OldInsnID*/0, /*OpIdx*/1, /*SubRegIdx*/GIMT_Encode2(3), // z
        GIR_ConstrainOperandRC, /*InsnID*/4, /*Op*/0, GIMT_Encode2(AMDGPU::VGPR_32RegClassID),
        GIR_ConstrainOperandRC, /*InsnID*/4, /*Op*/1, GIMT_Encode2(AMDGPU::VReg_64RegClassID),
        GIR_BuildMI, /*InsnID*/3, /*Opcode*/GIMT_Encode2(TargetOpcode::COPY),
        GIR_AddTempRegister, /*InsnID*/3, /*TempRegID*/2, /*TempRegFlags*/GIMT_Encode2(RegState::Define),
        GIR_CopySubReg, /*NewInsnID*/3, /*OldInsnID*/2, /*OpIdx*/1, /*SubRegIdx*/GIMT_Encode2(3), // y
        GIR_ConstrainOperandRC, /*InsnID*/3, /*Op*/0, GIMT_Encode2(AMDGPU::VGPR_32RegClassID),
        GIR_ConstrainOperandRC, /*InsnID*/3, /*Op*/1, GIMT_Encode2(AMDGPU::VReg_64RegClassID),
        GIR_BuildMI, /*InsnID*/2, /*Opcode*/GIMT_Encode2(TargetOpcode::COPY),
        GIR_AddTempRegister, /*InsnID*/2, /*TempRegID*/1, /*TempRegFlags*/GIMT_Encode2(RegState::Define),
        GIR_CopySubReg, /*NewInsnID*/2, /*OldInsnID*/1, /*OpIdx*/2, /*SubRegIdx*/GIMT_Encode2(3), // x
        GIR_ConstrainOperandRC, /*InsnID*/2, /*Op*/0, GIMT_Encode2(AMDGPU::VGPR_32RegClassID),
        GIR_ConstrainOperandRC, /*InsnID*/2, /*Op*/1, GIMT_Encode2(AMDGPU::VReg_64RegClassID),
        GIR_BuildMI, /*InsnID*/1, /*Opcode*/GIMT_Encode2(AMDGPU::V_BFI_B32_e64),
        GIR_AddTempRegister, /*InsnID*/1, /*TempRegID*/0, /*TempRegFlags*/GIMT_Encode2(RegState::Define),
        GIR_AddSimpleTempRegister, /*InsnID*/1, /*TempRegID*/1,
        GIR_AddSimpleTempRegister, /*InsnID*/1, /*TempRegID*/2,
        GIR_AddSimpleTempRegister, /*InsnID*/1, /*TempRegID*/3,
        GIR_ConstrainSelectedInstOperands, /*InsnID*/1,
        GIR_BuildMI, /*InsnID*/0, /*Opcode*/GIMT_Encode2(TargetOpcode::REG_SEQUENCE),
        GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/0, // DstI[dst]
        GIR_AddSimpleTempRegister, /*InsnID*/0, /*TempRegID*/0,
        GIR_AddImm8, /*InsnID*/0, /*SubRegIndex*/3,
        GIR_AddSimpleTempRegister, /*InsnID*/0, /*TempRegID*/4,
        GIR_AddImm8, /*InsnID*/0, /*SubRegIndex*/11,
        GIR_ConstrainOperandRC, /*InsnID*/0, /*Op*/0, GIMT_Encode2(AMDGPU::VReg_64RegClassID),
        GIR_ConstrainOperandRC, /*InsnID*/0, /*Op*/1, GIMT_Encode2(AMDGPU::VGPR_32RegClassID),
        GIR_ConstrainOperandRC, /*InsnID*/0, /*Op*/3, GIMT_Encode2(AMDGPU::VGPR_32RegClassID),
        GIR_EraseFromParent, /*InsnID*/0,
        // GIR_Coverage, 9893,
        GIR_Done,
      // Label 416: @38328
      GIM_Try, /*On fail goto*//*Label 417*/ GIMT_Encode4(38635), // Rule ID 9892 //
        GIM_CheckType, /*MI*/0, /*Op*/2, /*Type*/GILLT_s64,
        GIM_CheckRegBankForClass, /*MI*/0, /*Op*/0, /*RC*/GIMT_Encode2(AMDGPU::VReg_64RegClassID),
        GIM_RecordInsnIgnoreCopies, /*DefineMI*/1, /*MI*/0, /*OpIdx*/2, // MIs[1]
        GIM_CheckOpcode, /*MI*/1, GIMT_Encode2(TargetOpcode::G_AND),
        GIM_CheckType, /*MI*/1, /*Op*/1, /*Type*/GILLT_s64,
        GIM_CheckType, /*MI*/1, /*Op*/2, /*Type*/GILLT_s64,
        GIM_RecordInsnIgnoreCopies, /*DefineMI*/2, /*MI*/1, /*OpIdx*/2, // MIs[2]
        GIM_CheckOpcode, /*MI*/2, GIMT_Encode2(TargetOpcode::G_XOR),
        GIM_CheckType, /*MI*/2, /*Op*/2, /*Type*/GILLT_s64,
        // MIs[2] z
        GIM_CheckIsSameOperandIgnoreCopies, /*MI*/2, /*OpIdx*/1, /*OtherMI*/0, /*OtherOpIdx*/1,
        GIM_CheckCxxInsnPredicate, /*MI*/0, /*FnId*/GIMT_Encode2(GICXXPred_MI_Predicate_anonymous_22559),
        GIM_CheckIsSafeToFold, /*InsnID*/1,
        GIM_CheckIsSafeToFold, /*InsnID*/2,
        // (xor:{ *:[i64] } i64:{ *:[i64] }:$z, (and:{ *:[i64] } i64:{ *:[i64] }:$x, (xor:{ *:[i64] } i64:{ *:[i64] }:$z, i64:{ *:[i64] }:$y)))<<P:Predicate_anonymous_22559>>  =>  (REG_SEQUENCE:{ *:[i64] } VReg_64:{ *:[i32] }, (V_BFI_B32_e64:{ *:[i16] } (EXTRACT_SUBREG:{ *:[i32] } VReg_64:{ *:[i64] }:$x, sub0:{ *:[i32] }), (EXTRACT_SUBREG:{ *:[i32] } VReg_64:{ *:[i64] }:$y, sub0:{ *:[i32] }), (EXTRACT_SUBREG:{ *:[i32] } VReg_64:{ *:[i64] }:$z, sub0:{ *:[i32] })), sub0:{ *:[i32] }, (V_BFI_B32_e64:{ *:[i16] } (EXTRACT_SUBREG:{ *:[i32] } VReg_64:{ *:[i64] }:$x, sub1:{ *:[i32] }), (EXTRACT_SUBREG:{ *:[i32] } VReg_64:{ *:[i64] }:$y, sub1:{ *:[i32] }), (EXTRACT_SUBREG:{ *:[i32] } VReg_64:{ *:[i64] }:$z, sub1:{ *:[i32] })), sub1:{ *:[i32] })
        GIR_MakeTempReg, /*TempRegID*/0, /*TypeID*/GILLT_s16,
        GIR_MakeTempReg, /*TempRegID*/1, /*TypeID*/GILLT_s32,
        GIR_MakeTempReg, /*TempRegID*/2, /*TypeID*/GILLT_s32,
        GIR_MakeTempReg, /*TempRegID*/3, /*TypeID*/GILLT_s32,
        GIR_MakeTempReg, /*TempRegID*/4, /*TypeID*/GILLT_s16,
        GIR_MakeTempReg, /*TempRegID*/5, /*TypeID*/GILLT_s32,
        GIR_MakeTempReg, /*TempRegID*/6, /*TypeID*/GILLT_s32,
        GIR_MakeTempReg, /*TempRegID*/7, /*TypeID*/GILLT_s32,
        GIR_BuildMI, /*InsnID*/8, /*Opcode*/GIMT_Encode2(TargetOpcode::COPY),
        GIR_AddTempRegister, /*InsnID*/8, /*TempRegID*/7, /*TempRegFlags*/GIMT_Encode2(RegState::Define),
        GIR_CopySubReg, /*NewInsnID*/8, /*OldInsnID*/0, /*OpIdx*/1, /*SubRegIdx*/GIMT_Encode2(11), // z
        GIR_ConstrainOperandRC, /*InsnID*/8, /*Op*/0, GIMT_Encode2(AMDGPU::VGPR_32RegClassID),
        GIR_ConstrainOperandRC, /*InsnID*/8, /*Op*/1, GIMT_Encode2(AMDGPU::VReg_64RegClassID),
        GIR_BuildMI, /*InsnID*/7, /*Opcode*/GIMT_Encode2(TargetOpcode::COPY),
        GIR_AddTempRegister, /*InsnID*/7, /*TempRegID*/6, /*TempRegFlags*/GIMT_Encode2(RegState::Define),
        GIR_CopySubReg, /*NewInsnID*/7, /*OldInsnID*/2, /*OpIdx*/2, /*SubRegIdx*/GIMT_Encode2(11), // y
        GIR_ConstrainOperandRC, /*InsnID*/7, /*Op*/0, GIMT_Encode2(AMDGPU::VGPR_32RegClassID),
        GIR_ConstrainOperandRC, /*InsnID*/7, /*Op*/1, GIMT_Encode2(AMDGPU::VReg_64RegClassID),
        GIR_BuildMI, /*InsnID*/6, /*Opcode*/GIMT_Encode2(TargetOpcode::COPY),
        GIR_AddTempRegister, /*InsnID*/6, /*TempRegID*/5, /*TempRegFlags*/GIMT_Encode2(RegState::Define),
        GIR_CopySubReg, /*NewInsnID*/6, /*OldInsnID*/1, /*OpIdx*/1, /*SubRegIdx*/GIMT_Encode2(11), // x
        GIR_ConstrainOperandRC, /*InsnID*/6, /*Op*/0, GIMT_Encode2(AMDGPU::VGPR_32RegClassID),
        GIR_ConstrainOperandRC, /*InsnID*/6, /*Op*/1, GIMT_Encode2(AMDGPU::VReg_64RegClassID),
        GIR_BuildMI, /*InsnID*/5, /*Opcode*/GIMT_Encode2(AMDGPU::V_BFI_B32_e64),
        GIR_AddTempRegister, /*InsnID*/5, /*TempRegID*/4, /*TempRegFlags*/GIMT_Encode2(RegState::Define),
        GIR_AddSimpleTempRegister, /*InsnID*/5, /*TempRegID*/5,
        GIR_AddSimpleTempRegister, /*InsnID*/5, /*TempRegID*/6,
        GIR_AddSimpleTempRegister, /*InsnID*/5, /*TempRegID*/7,
        GIR_ConstrainSelectedInstOperands, /*InsnID*/5,
        GIR_BuildMI, /*InsnID*/4, /*Opcode*/GIMT_Encode2(TargetOpcode::COPY),
        GIR_AddTempRegister, /*InsnID*/4, /*TempRegID*/3, /*TempRegFlags*/GIMT_Encode2(RegState::Define),
        GIR_CopySubReg, /*NewInsnID*/4, /*OldInsnID*/0, /*OpIdx*/1, /*SubRegIdx*/GIMT_Encode2(3), // z
        GIR_ConstrainOperandRC, /*InsnID*/4, /*Op*/0, GIMT_Encode2(AMDGPU::VGPR_32RegClassID),
        GIR_ConstrainOperandRC, /*InsnID*/4, /*Op*/1, GIMT_Encode2(AMDGPU::VReg_64RegClassID),
        GIR_BuildMI, /*InsnID*/3, /*Opcode*/GIMT_Encode2(TargetOpcode::COPY),
        GIR_AddTempRegister, /*InsnID*/3, /*TempRegID*/2, /*TempRegFlags*/GIMT_Encode2(RegState::Define),
        GIR_CopySubReg, /*NewInsnID*/3, /*OldInsnID*/2, /*OpIdx*/2, /*SubRegIdx*/GIMT_Encode2(3), // y
        GIR_ConstrainOperandRC, /*InsnID*/3, /*Op*/0, GIMT_Encode2(AMDGPU::VGPR_32RegClassID),
        GIR_ConstrainOperandRC, /*InsnID*/3, /*Op*/1, GIMT_Encode2(AMDGPU::VReg_64RegClassID),
        GIR_BuildMI, /*InsnID*/2, /*Opcode*/GIMT_Encode2(TargetOpcode::COPY),
        GIR_AddTempRegister, /*InsnID*/2, /*TempRegID*/1, /*TempRegFlags*/GIMT_Encode2(RegState::Define),
        GIR_CopySubReg, /*NewInsnID*/2, /*OldInsnID*/1, /*OpIdx*/1, /*SubRegIdx*/GIMT_Encode2(3), // x
        GIR_ConstrainOperandRC, /*InsnID*/2, /*Op*/0, GIMT_Encode2(AMDGPU::VGPR_32RegClassID),
        GIR_ConstrainOperandRC, /*InsnID*/2, /*Op*/1, GIMT_Encode2(AMDGPU::VReg_64RegClassID),
        GIR_BuildMI, /*InsnID*/1, /*Opcode*/GIMT_Encode2(AMDGPU::V_BFI_B32_e64),
        GIR_AddTempRegister, /*InsnID*/1, /*TempRegID*/0, /*TempRegFlags*/GIMT_Encode2(RegState::Define),
        GIR_AddSimpleTempRegister, /*InsnID*/1, /*TempRegID*/1,
        GIR_AddSimpleTempRegister, /*InsnID*/1, /*TempRegID*/2,
        GIR_AddSimpleTempRegister, /*InsnID*/1, /*TempRegID*/3,
        GIR_ConstrainSelectedInstOperands, /*InsnID*/1,
        GIR_BuildMI, /*InsnID*/0, /*Opcode*/GIMT_Encode2(TargetOpcode::REG_SEQUENCE),
        GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/0, // DstI[dst]
        GIR_AddSimpleTempRegister, /*InsnID*/0, /*TempRegID*/0,
        GIR_AddImm8, /*InsnID*/0, /*SubRegIndex*/3,
        GIR_AddSimpleTempRegister, /*InsnID*/0, /*TempRegID*/4,
        GIR_AddImm8, /*InsnID*/0, /*SubRegIndex*/11,
        GIR_ConstrainOperandRC, /*InsnID*/0, /*Op*/0, GIMT_Encode2(AMDGPU::VReg_64RegClassID),
        GIR_ConstrainOperandRC, /*InsnID*/0, /*Op*/1, GIMT_Encode2(AMDGPU::VGPR_32RegClassID),
        GIR_ConstrainOperandRC, /*InsnID*/0, /*Op*/3, GIMT_Encode2(AMDGPU::VGPR_32RegClassID),
        GIR_EraseFromParent, /*InsnID*/0,
        // GIR_Coverage, 9892,
        GIR_Done,
      // Label 417: @38635
      GIM_Try, /*On fail goto*//*Label 418*/ GIMT_Encode4(38942), // Rule ID 6277 //
        GIM_CheckType, /*MI*/0, /*Op*/2, /*Type*/GILLT_s64,
        GIM_CheckRegBankForClass, /*MI*/0, /*Op*/0, /*RC*/GIMT_Encode2(AMDGPU::VReg_64RegClassID),
        GIM_RecordInsnIgnoreCopies, /*DefineMI*/1, /*MI*/0, /*OpIdx*/2, // MIs[1]
        GIM_CheckOpcode, /*MI*/1, GIMT_Encode2(TargetOpcode::G_AND),
        GIM_CheckType, /*MI*/1, /*Op*/1, /*Type*/GILLT_s64,
        GIM_CheckType, /*MI*/1, /*Op*/2, /*Type*/GILLT_s64,
        GIM_RecordInsnIgnoreCopies, /*DefineMI*/2, /*MI*/1, /*OpIdx*/2, // MIs[2]
        GIM_CheckOpcode, /*MI*/2, GIMT_Encode2(TargetOpcode::G_XOR),
        GIM_CheckType, /*MI*/2, /*Op*/1, /*Type*/GILLT_s64,
        // MIs[2] z
        GIM_CheckIsSameOperandIgnoreCopies, /*MI*/2, /*OpIdx*/2, /*OtherMI*/0, /*OtherOpIdx*/1,
        GIM_CheckCxxInsnPredicate, /*MI*/0, /*FnId*/GIMT_Encode2(GICXXPred_MI_Predicate_anonymous_22559),
        GIM_CheckIsSafeToFold, /*InsnID*/1,
        GIM_CheckIsSafeToFold, /*InsnID*/2,
        // (xor:{ *:[i64] } i64:{ *:[i64] }:$z, (and:{ *:[i64] } i64:{ *:[i64] }:$x, (xor:{ *:[i64] } i64:{ *:[i64] }:$y, i64:{ *:[i64] }:$z)))<<P:Predicate_anonymous_22559>>  =>  (REG_SEQUENCE:{ *:[i64] } VReg_64:{ *:[i32] }, (V_BFI_B32_e64:{ *:[i16] } (EXTRACT_SUBREG:{ *:[i32] } VReg_64:{ *:[i64] }:$x, sub0:{ *:[i32] }), (EXTRACT_SUBREG:{ *:[i32] } VReg_64:{ *:[i64] }:$y, sub0:{ *:[i32] }), (EXTRACT_SUBREG:{ *:[i32] } VReg_64:{ *:[i64] }:$z, sub0:{ *:[i32] })), sub0:{ *:[i32] }, (V_BFI_B32_e64:{ *:[i16] } (EXTRACT_SUBREG:{ *:[i32] } VReg_64:{ *:[i64] }:$x, sub1:{ *:[i32] }), (EXTRACT_SUBREG:{ *:[i32] } VReg_64:{ *:[i64] }:$y, sub1:{ *:[i32] }), (EXTRACT_SUBREG:{ *:[i32] } VReg_64:{ *:[i64] }:$z, sub1:{ *:[i32] })), sub1:{ *:[i32] })
        GIR_MakeTempReg, /*TempRegID*/0, /*TypeID*/GILLT_s16,
        GIR_MakeTempReg, /*TempRegID*/1, /*TypeID*/GILLT_s32,
        GIR_MakeTempReg, /*TempRegID*/2, /*TypeID*/GILLT_s32,
        GIR_MakeTempReg, /*TempRegID*/3, /*TypeID*/GILLT_s32,
        GIR_MakeTempReg, /*TempRegID*/4, /*TypeID*/GILLT_s16,
        GIR_MakeTempReg, /*TempRegID*/5, /*TypeID*/GILLT_s32,
        GIR_MakeTempReg, /*TempRegID*/6, /*TypeID*/GILLT_s32,
        GIR_MakeTempReg, /*TempRegID*/7, /*TypeID*/GILLT_s32,
        GIR_BuildMI, /*InsnID*/8, /*Opcode*/GIMT_Encode2(TargetOpcode::COPY),
        GIR_AddTempRegister, /*InsnID*/8, /*TempRegID*/7, /*TempRegFlags*/GIMT_Encode2(RegState::Define),
        GIR_CopySubReg, /*NewInsnID*/8, /*OldInsnID*/0, /*OpIdx*/1, /*SubRegIdx*/GIMT_Encode2(11), // z
        GIR_ConstrainOperandRC, /*InsnID*/8, /*Op*/0, GIMT_Encode2(AMDGPU::VGPR_32RegClassID),
        GIR_ConstrainOperandRC, /*InsnID*/8, /*Op*/1, GIMT_Encode2(AMDGPU::VReg_64RegClassID),
        GIR_BuildMI, /*InsnID*/7, /*Opcode*/GIMT_Encode2(TargetOpcode::COPY),
        GIR_AddTempRegister, /*InsnID*/7, /*TempRegID*/6, /*TempRegFlags*/GIMT_Encode2(RegState::Define),
        GIR_CopySubReg, /*NewInsnID*/7, /*OldInsnID*/2, /*OpIdx*/1, /*SubRegIdx*/GIMT_Encode2(11), // y
        GIR_ConstrainOperandRC, /*InsnID*/7, /*Op*/0, GIMT_Encode2(AMDGPU::VGPR_32RegClassID),
        GIR_ConstrainOperandRC, /*InsnID*/7, /*Op*/1, GIMT_Encode2(AMDGPU::VReg_64RegClassID),
        GIR_BuildMI, /*InsnID*/6, /*Opcode*/GIMT_Encode2(TargetOpcode::COPY),
        GIR_AddTempRegister, /*InsnID*/6, /*TempRegID*/5, /*TempRegFlags*/GIMT_Encode2(RegState::Define),
        GIR_CopySubReg, /*NewInsnID*/6, /*OldInsnID*/1, /*OpIdx*/1, /*SubRegIdx*/GIMT_Encode2(11), // x
        GIR_ConstrainOperandRC, /*InsnID*/6, /*Op*/0, GIMT_Encode2(AMDGPU::VGPR_32RegClassID),
        GIR_ConstrainOperandRC, /*InsnID*/6, /*Op*/1, GIMT_Encode2(AMDGPU::VReg_64RegClassID),
        GIR_BuildMI, /*InsnID*/5, /*Opcode*/GIMT_Encode2(AMDGPU::V_BFI_B32_e64),
        GIR_AddTempRegister, /*InsnID*/5, /*TempRegID*/4, /*TempRegFlags*/GIMT_Encode2(RegState::Define),
        GIR_AddSimpleTempRegister, /*InsnID*/5, /*TempRegID*/5,
        GIR_AddSimpleTempRegister, /*InsnID*/5, /*TempRegID*/6,
        GIR_AddSimpleTempRegister, /*InsnID*/5, /*TempRegID*/7,
        GIR_ConstrainSelectedInstOperands, /*InsnID*/5,
        GIR_BuildMI, /*InsnID*/4, /*Opcode*/GIMT_Encode2(TargetOpcode::COPY),
        GIR_AddTempRegister, /*InsnID*/4, /*TempRegID*/3, /*TempRegFlags*/GIMT_Encode2(RegState::Define),
        GIR_CopySubReg, /*NewInsnID*/4, /*OldInsnID*/0, /*OpIdx*/1, /*SubRegIdx*/GIMT_Encode2(3), // z
        GIR_ConstrainOperandRC, /*InsnID*/4, /*Op*/0, GIMT_Encode2(AMDGPU::VGPR_32RegClassID),
        GIR_ConstrainOperandRC, /*InsnID*/4, /*Op*/1, GIMT_Encode2(AMDGPU::VReg_64RegClassID),
        GIR_BuildMI, /*InsnID*/3, /*Opcode*/GIMT_Encode2(TargetOpcode::COPY),
        GIR_AddTempRegister, /*InsnID*/3, /*TempRegID*/2, /*TempRegFlags*/GIMT_Encode2(RegState::Define),
        GIR_CopySubReg, /*NewInsnID*/3, /*OldInsnID*/2, /*OpIdx*/1, /*SubRegIdx*/GIMT_Encode2(3), // y
        GIR_ConstrainOperandRC, /*InsnID*/3, /*Op*/0, GIMT_Encode2(AMDGPU::VGPR_32RegClassID),
        GIR_ConstrainOperandRC, /*InsnID*/3, /*Op*/1, GIMT_Encode2(AMDGPU::VReg_64RegClassID),
        GIR_BuildMI, /*InsnID*/2, /*Opcode*/GIMT_Encode2(TargetOpcode::COPY),
        GIR_AddTempRegister, /*InsnID*/2, /*TempRegID*/1, /*TempRegFlags*/GIMT_Encode2(RegState::Define),
        GIR_CopySubReg, /*NewInsnID*/2, /*OldInsnID*/1, /*OpIdx*/1, /*SubRegIdx*/GIMT_Encode2(3), // x
        GIR_ConstrainOperandRC, /*InsnID*/2, /*Op*/0, GIMT_Encode2(AMDGPU::VGPR_32RegClassID),
        GIR_ConstrainOperandRC, /*InsnID*/2, /*Op*/1, GIMT_Encode2(AMDGPU::VReg_64RegClassID),
        GIR_BuildMI, /*InsnID*/1, /*Opcode*/GIMT_Encode2(AMDGPU::V_BFI_B32_e64),
        GIR_AddTempRegister, /*InsnID*/1, /*TempRegID*/0, /*TempRegFlags*/GIMT_Encode2(RegState::Define),
        GIR_AddSimpleTempRegister, /*InsnID*/1, /*TempRegID*/1,
        GIR_AddSimpleTempRegister, /*InsnID*/1, /*TempRegID*/2,
        GIR_AddSimpleTempRegister, /*InsnID*/1, /*TempRegID*/3,
        GIR_ConstrainSelectedInstOperands, /*InsnID*/1,
        GIR_BuildMI, /*InsnID*/0, /*Opcode*/GIMT_Encode2(TargetOpcode::REG_SEQUENCE),
        GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/0, // DstI[dst]
        GIR_AddSimpleTempRegister, /*InsnID*/0, /*TempRegID*/0,
        GIR_AddImm8, /*InsnID*/0, /*SubRegIndex*/3,
        GIR_AddSimpleTempRegister, /*InsnID*/0, /*TempRegID*/4,
        GIR_AddImm8, /*InsnID*/0, /*SubRegIndex*/11,
        GIR_ConstrainOperandRC, /*InsnID*/0, /*Op*/0, GIMT_Encode2(AMDGPU::VReg_64RegClassID),
        GIR_ConstrainOperandRC, /*InsnID*/0, /*Op*/1, GIMT_Encode2(AMDGPU::VGPR_32RegClassID),
        GIR_ConstrainOperandRC, /*InsnID*/0, /*Op*/3, GIMT_Encode2(AMDGPU::VGPR_32RegClassID),
        GIR_EraseFromParent, /*InsnID*/0,
        // GIR_Coverage, 6277,
        GIR_Done,
      // Label 418: @38942
      GIM_Try, /*On fail goto*//*Label 419*/ GIMT_Encode4(38984), // Rule ID 1 //
        GIM_CheckType, /*MI*/0, /*Op*/2, /*Type*/GILLT_s64,
        GIM_CheckRegBankForClass, /*MI*/0, /*Op*/0, /*RC*/GIMT_Encode2(AMDGPU::SReg_64RegClassID),
        GIM_CheckConstantInt8, /*MI*/0, /*Op*/2, uint8_t(-1),
        GIM_CheckCxxInsnPredicate, /*MI*/0, /*FnId*/GIMT_Encode2(GICXXPred_MI_Predicate_anonymous_17562),
        // (xor:{ *:[i64] } i64:{ *:[i64] }:$src0, -1:{ *:[i64] })<<P:Predicate_anonymous_17562>>  =>  (S_NOT_B64:{ *:[i64] }:{ *:[i1] } i64:{ *:[i64] }:$src0)
        GIR_BuildMI, /*InsnID*/0, /*Opcode*/GIMT_Encode2(AMDGPU::S_NOT_B64),
        GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/0, // DstI[sdst]
        GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/1, // src0
        GIR_SetImplicitDefDead, /*InsnID*/0, /*OpIdx for AMDGPU::SCC*/0,
        GIR_ConstrainSelectedInstOperands, /*InsnID*/0,
        GIR_EraseFromParent, /*InsnID*/0,
        // GIR_Coverage, 1,
        GIR_Done,
      // Label 419: @38984
      GIM_Try, /*On fail goto*//*Label 420*/ GIMT_Encode4(39016), // Rule ID 59 //
        GIM_CheckType, /*MI*/0, /*Op*/2, /*Type*/GILLT_s64,
        GIM_CheckRegBankForClass, /*MI*/0, /*Op*/0, /*RC*/GIMT_Encode2(AMDGPU::SReg_64RegClassID),
        GIM_CheckCxxInsnPredicate, /*MI*/0, /*FnId*/GIMT_Encode2(GICXXPred_MI_Predicate_anonymous_17617),
        // (xor:{ *:[i64] } i64:{ *:[i64] }:$src0, i64:{ *:[i64] }:$src1)<<P:Predicate_anonymous_17617>>  =>  (S_XOR_B64:{ *:[i64] }:{ *:[i1] } i64:{ *:[i64] }:$src0, i64:{ *:[i64] }:$src1)
        GIR_MutateOpcode, /*InsnID*/0, /*RecycleInsnID*/0, /*Opcode*/GIMT_Encode2(AMDGPU::S_XOR_B64),
        GIR_AddImplicitDef, /*InsnID*/0, GIMT_Encode2(AMDGPU::SCC), GIMT_Encode2(RegState::Dead),
        GIR_ConstrainSelectedInstOperands, /*InsnID*/0,
        // GIR_Coverage, 59,
        GIR_Done,
      // Label 420: @39016
      GIM_Reject,
    // Label 407: @39017
    GIM_Reject,
    // Label 378: @39018
    GIM_Try, /*On fail goto*//*Label 421*/ GIMT_Encode4(39048), // Rule ID 2131 //
      GIM_CheckType, /*MI*/0, /*Op*/1, /*Type*/GILLT_v2s16,
      GIM_CheckType, /*MI*/0, /*Op*/2, /*Type*/GILLT_v2s16,
      GIM_CheckRegBankForClass, /*MI*/0, /*Op*/0, /*RC*/GIMT_Encode2(AMDGPU::VGPR_32RegClassID),
      // (xor:{ *:[v2i16] } v2i16:{ *:[v2i16] }:$src0, v2i16:{ *:[v2i16] }:$src1)  =>  (V_XOR_B32_e64:{ *:[v2i16] } VSrc_b32:{ *:[v2i16] }:$src0, VSrc_b32:{ *:[v2i16] }:$src1)
      GIR_MutateOpcode, /*InsnID*/0, /*RecycleInsnID*/0, /*Opcode*/GIMT_Encode2(AMDGPU::V_XOR_B32_e64),
      GIR_AddImplicitUse, /*InsnID*/0, GIMT_Encode2(AMDGPU::EXEC),
      GIR_ConstrainSelectedInstOperands, /*InsnID*/0,
      // GIR_Coverage, 2131,
      GIR_Done,
    // Label 421: @39048
    GIM_Reject,
    // Label 379: @39049
    GIM_Reject,
    // Label 6: @39050
    GIM_Try, /*On fail goto*//*Label 422*/ GIMT_Encode4(39116),
      GIM_CheckType, /*MI*/0, /*Op*/0, /*Type*/GILLT_p5s32,
      GIM_Try, /*On fail goto*//*Label 423*/ GIMT_Encode4(39087), // Rule ID 6258 //
        GIM_CheckRegBankForClass, /*MI*/0, /*Op*/0, /*RC*/GIMT_Encode2(AMDGPU::VGPR_32RegClassID),
        // (frameindex:{ *:[i32] }):$fi  =>  (V_MOV_B32_e32:{ *:[i32] } (frameindex_to_targetframeindex:{ *:[i32] } ?:{ *:[i32] }:$fi))
        GIR_BuildMI, /*InsnID*/0, /*Opcode*/GIMT_Encode2(AMDGPU::V_MOV_B32_e32),
        GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/0, // DstI[vdst]
        GIR_CustomRenderer, /*InsnID*/0, /*OldInsnID*/0, /*Renderer*/GIMT_Encode2(GICR_renderFrameIndex), // fi
        GIR_ConstrainSelectedInstOperands, /*InsnID*/0,
        GIR_EraseFromParent, /*InsnID*/0,
        // GIR_Coverage, 6258,
        GIR_Done,
      // Label 423: @39087
      GIM_Try, /*On fail goto*//*Label 424*/ GIMT_Encode4(39115), // Rule ID 6259 //
        GIM_CheckRegBankForClass, /*MI*/0, /*Op*/0, /*RC*/GIMT_Encode2(AMDGPU::SReg_32RegClassID),
        // (frameindex:{ *:[i32] }):$fi  =>  (S_MOV_B32:{ *:[i32] } (frameindex_to_targetframeindex:{ *:[i32] } ?:{ *:[i32] }:$fi))
        GIR_BuildMI, /*InsnID*/0, /*Opcode*/GIMT_Encode2(AMDGPU::S_MOV_B32),
        GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/0, // DstI[sdst]
        GIR_CustomRenderer, /*InsnID*/0, /*OldInsnID*/0, /*Renderer*/GIMT_Encode2(GICR_renderFrameIndex), // fi
        GIR_ConstrainSelectedInstOperands, /*InsnID*/0,
        GIR_EraseFromParent, /*InsnID*/0,
        // GIR_Coverage, 6259,
        GIR_Done,
      // Label 424: @39115
      GIM_Reject,
    // Label 422: @39116
    GIM_Reject,
    // Label 7: @39117
    GIM_Try, /*On fail goto*//*Label 425*/ GIMT_Encode4(41816),
      GIM_CheckNumOperands, /*MI*/0, /*Expected*/3,
      GIM_CheckType, /*MI*/0, /*Op*/0, /*Type*/GILLT_v2s16,
      GIM_CheckType, /*MI*/0, /*Op*/1, /*Type*/GILLT_s16,
      GIM_CheckType, /*MI*/0, /*Op*/2, /*Type*/GILLT_s16,
      GIM_Try, /*On fail goto*//*Label 426*/ GIMT_Encode4(39660),
        GIM_CheckRegBankForClass, /*MI*/0, /*Op*/0, /*RC*/GIMT_Encode2(AMDGPU::VGPR_32RegClassID),
        GIM_Try, /*On fail goto*//*Label 427*/ GIMT_Encode4(39282), // Rule ID 2263 //
          GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasFmaMixInsts),
          GIM_RecordInsn, /*DefineMI*/1, /*MI*/0, /*OpIdx*/2, // MIs[1]
          GIM_CheckOpcode, /*MI*/1, GIMT_Encode2(AMDGPU::G_AMDGPU_CLAMP),
          GIM_CheckType, /*MI*/1, /*Op*/1, /*Type*/GILLT_s16,
          GIM_RecordInsn, /*DefineMI*/2, /*MI*/1, /*OpIdx*/1, // MIs[2]
          GIM_CheckOpcode, /*MI*/2, GIMT_Encode2(TargetOpcode::G_FPTRUNC),
          GIM_CheckType, /*MI*/2, /*Op*/1, /*Type*/GILLT_s32,
          GIM_RecordInsn, /*DefineMI*/3, /*MI*/2, /*OpIdx*/1, // MIs[3]
          GIM_CheckOpcode, /*MI*/3, GIMT_Encode2(TargetOpcode::G_FMA),
          GIM_CheckType, /*MI*/3, /*Op*/1, /*Type*/GILLT_s32,
          GIM_CheckType, /*MI*/3, /*Op*/2, /*Type*/GILLT_s32,
          GIM_CheckType, /*MI*/3, /*Op*/3, /*Type*/GILLT_s32,
          GIM_CheckIsSafeToFold, /*InsnID*/1,
          GIM_CheckIsSafeToFold, /*InsnID*/2,
          GIM_CheckIsSafeToFold, /*InsnID*/3,
          GIM_CheckComplexPattern, /*MI*/3, /*Op*/1, /*Renderer*/GIMT_Encode2(0), GIMT_Encode2(GICP_gi_vop3_mad_mix_mods),
          GIM_CheckComplexPattern, /*MI*/3, /*Op*/2, /*Renderer*/GIMT_Encode2(1), GIMT_Encode2(GICP_gi_vop3_mad_mix_mods),
          GIM_CheckComplexPattern, /*MI*/3, /*Op*/3, /*Renderer*/GIMT_Encode2(2), GIMT_Encode2(GICP_gi_vop3_mad_mix_mods),
          // (build_vector:{ *:[v2f16] } f16:{ *:[f16] }:$elt0, (AMDGPUclamp:{ *:[f16] } (fpround:{ *:[f16] } (fma:{ *:[f32] } (VOP3PMadMixMods:{ *:[f32] } f16:{ *:[f16] }:$src0, i32:{ *:[i32] }:$src0_modifiers), (VOP3PMadMixMods:{ *:[f32] } f16:{ *:[f16] }:$src1, i32:{ *:[i32] }:$src1_modifiers), (VOP3PMadMixMods:{ *:[f32] } f16:{ *:[f16] }:$src2, i32:{ *:[i32] }:$src2_modifiers)))))  =>  (V_FMA_MIXHI_F16:{ *:[v2f16] } ?:{ *:[i32] }:$src0_modifiers, ?:{ *:[f16] }:$src0, ?:{ *:[i32] }:$src1_modifiers, ?:{ *:[f16] }:$src1, ?:{ *:[i32] }:$src2_modifiers, ?:{ *:[f16] }:$src2, 1:{ *:[i1] }, VGPR_32:{ *:[f16] }:$elt0)
          GIR_BuildMI, /*InsnID*/0, /*Opcode*/GIMT_Encode2(AMDGPU::V_FMA_MIXHI_F16),
          GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/0, // DstI[vdst]
          GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/1, // src0_modifiers
          GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/0, // src0
          GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(1), /*SubOperand*/1, // src1_modifiers
          GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(1), /*SubOperand*/0, // src1
          GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(2), /*SubOperand*/1, // src2_modifiers
          GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(2), /*SubOperand*/0, // src2
          GIR_AddImm8, /*InsnID*/0, /*Imm*/1,
          GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/1, // elt0
          GIR_AddImm8, /*InsnID*/0, /*Imm*/0,
          GIR_AddImm8, /*InsnID*/0, /*Imm*/0,
          GIR_ConstrainSelectedInstOperands, /*InsnID*/0,
          GIR_EraseFromParent, /*InsnID*/0,
          // GIR_Coverage, 2263,
          GIR_Done,
        // Label 427: @39282
        GIM_Try, /*On fail goto*//*Label 428*/ GIMT_Encode4(39417), // Rule ID 2254 //
          GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasMadMixInsts_NoFP32Denormals),
          GIM_RecordInsn, /*DefineMI*/1, /*MI*/0, /*OpIdx*/2, // MIs[1]
          GIM_CheckOpcode, /*MI*/1, GIMT_Encode2(AMDGPU::G_AMDGPU_CLAMP),
          GIM_CheckType, /*MI*/1, /*Op*/1, /*Type*/GILLT_s16,
          GIM_RecordInsn, /*DefineMI*/2, /*MI*/1, /*OpIdx*/1, // MIs[2]
          GIM_CheckOpcode, /*MI*/2, GIMT_Encode2(TargetOpcode::G_FPTRUNC),
          GIM_CheckType, /*MI*/2, /*Op*/1, /*Type*/GILLT_s32,
          GIM_RecordInsn, /*DefineMI*/3, /*MI*/2, /*OpIdx*/1, // MIs[3]
          GIM_CheckOpcode, /*MI*/3, GIMT_Encode2(TargetOpcode::G_FMAD),
          GIM_CheckType, /*MI*/3, /*Op*/1, /*Type*/GILLT_s32,
          GIM_CheckType, /*MI*/3, /*Op*/2, /*Type*/GILLT_s32,
          GIM_CheckType, /*MI*/3, /*Op*/3, /*Type*/GILLT_s32,
          GIM_CheckIsSafeToFold, /*InsnID*/1,
          GIM_CheckIsSafeToFold, /*InsnID*/2,
          GIM_CheckIsSafeToFold, /*InsnID*/3,
          GIM_CheckComplexPattern, /*MI*/3, /*Op*/1, /*Renderer*/GIMT_Encode2(0), GIMT_Encode2(GICP_gi_vop3_mad_mix_mods),
          GIM_CheckComplexPattern, /*MI*/3, /*Op*/2, /*Renderer*/GIMT_Encode2(1), GIMT_Encode2(GICP_gi_vop3_mad_mix_mods),
          GIM_CheckComplexPattern, /*MI*/3, /*Op*/3, /*Renderer*/GIMT_Encode2(2), GIMT_Encode2(GICP_gi_vop3_mad_mix_mods),
          // (build_vector:{ *:[v2f16] } f16:{ *:[f16] }:$elt0, (AMDGPUclamp:{ *:[f16] } (fpround:{ *:[f16] } (fmad:{ *:[f32] } (VOP3PMadMixMods:{ *:[f32] } f16:{ *:[f16] }:$src0, i32:{ *:[i32] }:$src0_modifiers), (VOP3PMadMixMods:{ *:[f32] } f16:{ *:[f16] }:$src1, i32:{ *:[i32] }:$src1_modifiers), (VOP3PMadMixMods:{ *:[f32] } f16:{ *:[f16] }:$src2, i32:{ *:[i32] }:$src2_modifiers)))))  =>  (V_MAD_MIXHI_F16:{ *:[v2f16] } ?:{ *:[i32] }:$src0_modifiers, ?:{ *:[f16] }:$src0, ?:{ *:[i32] }:$src1_modifiers, ?:{ *:[f16] }:$src1, ?:{ *:[i32] }:$src2_modifiers, ?:{ *:[f16] }:$src2, 1:{ *:[i1] }, VGPR_32:{ *:[f16] }:$elt0)
          GIR_BuildMI, /*InsnID*/0, /*Opcode*/GIMT_Encode2(AMDGPU::V_MAD_MIXHI_F16),
          GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/0, // DstI[vdst]
          GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/1, // src0_modifiers
          GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/0, // src0
          GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(1), /*SubOperand*/1, // src1_modifiers
          GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(1), /*SubOperand*/0, // src1
          GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(2), /*SubOperand*/1, // src2_modifiers
          GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(2), /*SubOperand*/0, // src2
          GIR_AddImm8, /*InsnID*/0, /*Imm*/1,
          GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/1, // elt0
          GIR_AddImm8, /*InsnID*/0, /*Imm*/0,
          GIR_AddImm8, /*InsnID*/0, /*Imm*/0,
          GIR_ConstrainSelectedInstOperands, /*InsnID*/0,
          GIR_EraseFromParent, /*InsnID*/0,
          // GIR_Coverage, 2254,
          GIR_Done,
        // Label 428: @39417
        GIM_Try, /*On fail goto*//*Label 429*/ GIMT_Encode4(39538), // Rule ID 2262 //
          GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasFmaMixInsts),
          GIM_RecordInsn, /*DefineMI*/1, /*MI*/0, /*OpIdx*/2, // MIs[1]
          GIM_CheckOpcode, /*MI*/1, GIMT_Encode2(TargetOpcode::G_FPTRUNC),
          GIM_CheckType, /*MI*/1, /*Op*/1, /*Type*/GILLT_s32,
          GIM_RecordInsn, /*DefineMI*/2, /*MI*/1, /*OpIdx*/1, // MIs[2]
          GIM_CheckOpcode, /*MI*/2, GIMT_Encode2(TargetOpcode::G_FMA),
          GIM_CheckType, /*MI*/2, /*Op*/1, /*Type*/GILLT_s32,
          GIM_CheckType, /*MI*/2, /*Op*/2, /*Type*/GILLT_s32,
          GIM_CheckType, /*MI*/2, /*Op*/3, /*Type*/GILLT_s32,
          GIM_CheckIsSafeToFold, /*InsnID*/1,
          GIM_CheckIsSafeToFold, /*InsnID*/2,
          GIM_CheckComplexPattern, /*MI*/2, /*Op*/1, /*Renderer*/GIMT_Encode2(0), GIMT_Encode2(GICP_gi_vop3_mad_mix_mods),
          GIM_CheckComplexPattern, /*MI*/2, /*Op*/2, /*Renderer*/GIMT_Encode2(1), GIMT_Encode2(GICP_gi_vop3_mad_mix_mods),
          GIM_CheckComplexPattern, /*MI*/2, /*Op*/3, /*Renderer*/GIMT_Encode2(2), GIMT_Encode2(GICP_gi_vop3_mad_mix_mods),
          // (build_vector:{ *:[v2f16] } f16:{ *:[f16] }:$elt0, (fpround:{ *:[f16] } (fma:{ *:[f32] } (VOP3PMadMixMods:{ *:[f32] } f16:{ *:[f16] }:$src0, i32:{ *:[i32] }:$src0_modifiers), (VOP3PMadMixMods:{ *:[f32] } f16:{ *:[f16] }:$src1, i32:{ *:[i32] }:$src1_modifiers), (VOP3PMadMixMods:{ *:[f32] } f16:{ *:[f16] }:$src2, i32:{ *:[i32] }:$src2_modifiers))))  =>  (V_FMA_MIXHI_F16:{ *:[v2f16] } ?:{ *:[i32] }:$src0_modifiers, ?:{ *:[f16] }:$src0, ?:{ *:[i32] }:$src1_modifiers, ?:{ *:[f16] }:$src1, ?:{ *:[i32] }:$src2_modifiers, ?:{ *:[f16] }:$src2, 0:{ *:[i1] }, VGPR_32:{ *:[f16] }:$elt0)
          GIR_BuildMI, /*InsnID*/0, /*Opcode*/GIMT_Encode2(AMDGPU::V_FMA_MIXHI_F16),
          GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/0, // DstI[vdst]
          GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/1, // src0_modifiers
          GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/0, // src0
          GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(1), /*SubOperand*/1, // src1_modifiers
          GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(1), /*SubOperand*/0, // src1
          GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(2), /*SubOperand*/1, // src2_modifiers
          GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(2), /*SubOperand*/0, // src2
          GIR_AddImm8, /*InsnID*/0, /*Imm*/0,
          GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/1, // elt0
          GIR_AddImm8, /*InsnID*/0, /*Imm*/0,
          GIR_AddImm8, /*InsnID*/0, /*Imm*/0,
          GIR_ConstrainSelectedInstOperands, /*InsnID*/0,
          GIR_EraseFromParent, /*InsnID*/0,
          // GIR_Coverage, 2262,
          GIR_Done,
        // Label 429: @39538
        GIM_Try, /*On fail goto*//*Label 430*/ GIMT_Encode4(39659), // Rule ID 2253 //
          GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasMadMixInsts_NoFP32Denormals),
          GIM_RecordInsn, /*DefineMI*/1, /*MI*/0, /*OpIdx*/2, // MIs[1]
          GIM_CheckOpcode, /*MI*/1, GIMT_Encode2(TargetOpcode::G_FPTRUNC),
          GIM_CheckType, /*MI*/1, /*Op*/1, /*Type*/GILLT_s32,
          GIM_RecordInsn, /*DefineMI*/2, /*MI*/1, /*OpIdx*/1, // MIs[2]
          GIM_CheckOpcode, /*MI*/2, GIMT_Encode2(TargetOpcode::G_FMAD),
          GIM_CheckType, /*MI*/2, /*Op*/1, /*Type*/GILLT_s32,
          GIM_CheckType, /*MI*/2, /*Op*/2, /*Type*/GILLT_s32,
          GIM_CheckType, /*MI*/2, /*Op*/3, /*Type*/GILLT_s32,
          GIM_CheckIsSafeToFold, /*InsnID*/1,
          GIM_CheckIsSafeToFold, /*InsnID*/2,
          GIM_CheckComplexPattern, /*MI*/2, /*Op*/1, /*Renderer*/GIMT_Encode2(0), GIMT_Encode2(GICP_gi_vop3_mad_mix_mods),
          GIM_CheckComplexPattern, /*MI*/2, /*Op*/2, /*Renderer*/GIMT_Encode2(1), GIMT_Encode2(GICP_gi_vop3_mad_mix_mods),
          GIM_CheckComplexPattern, /*MI*/2, /*Op*/3, /*Renderer*/GIMT_Encode2(2), GIMT_Encode2(GICP_gi_vop3_mad_mix_mods),
          // (build_vector:{ *:[v2f16] } f16:{ *:[f16] }:$elt0, (fpround:{ *:[f16] } (fmad:{ *:[f32] } (VOP3PMadMixMods:{ *:[f32] } f16:{ *:[f16] }:$src0, i32:{ *:[i32] }:$src0_modifiers), (VOP3PMadMixMods:{ *:[f32] } f16:{ *:[f16] }:$src1, i32:{ *:[i32] }:$src1_modifiers), (VOP3PMadMixMods:{ *:[f32] } f16:{ *:[f16] }:$src2, i32:{ *:[i32] }:$src2_modifiers))))  =>  (V_MAD_MIXHI_F16:{ *:[v2f16] } ?:{ *:[i32] }:$src0_modifiers, ?:{ *:[f16] }:$src0, ?:{ *:[i32] }:$src1_modifiers, ?:{ *:[f16] }:$src1, ?:{ *:[i32] }:$src2_modifiers, ?:{ *:[f16] }:$src2, 0:{ *:[i1] }, VGPR_32:{ *:[f16] }:$elt0)
          GIR_BuildMI, /*InsnID*/0, /*Opcode*/GIMT_Encode2(AMDGPU::V_MAD_MIXHI_F16),
          GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/0, // DstI[vdst]
          GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/1, // src0_modifiers
          GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/0, // src0
          GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(1), /*SubOperand*/1, // src1_modifiers
          GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(1), /*SubOperand*/0, // src1
          GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(2), /*SubOperand*/1, // src2_modifiers
          GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(2), /*SubOperand*/0, // src2
          GIR_AddImm8, /*InsnID*/0, /*Imm*/0,
          GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/1, // elt0
          GIR_AddImm8, /*InsnID*/0, /*Imm*/0,
          GIR_AddImm8, /*InsnID*/0, /*Imm*/0,
          GIR_ConstrainSelectedInstOperands, /*InsnID*/0,
          GIR_EraseFromParent, /*InsnID*/0,
          // GIR_Coverage, 2253,
          GIR_Done,
        // Label 430: @39659
        GIM_Reject,
      // Label 426: @39660
      GIM_Try, /*On fail goto*//*Label 431*/ GIMT_Encode4(39835), // Rule ID 6452 //
        GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasVOP3PInsts),
        GIM_CheckRegBankForClass, /*MI*/0, /*Op*/0, /*RC*/GIMT_Encode2(AMDGPU::VGPR_32RegClassID),
        GIM_RecordInsn, /*DefineMI*/1, /*MI*/0, /*OpIdx*/1, // MIs[1]
        GIM_CheckOpcode, /*MI*/1, GIMT_Encode2(TargetOpcode::G_BITCAST),
        GIM_CheckType, /*MI*/1, /*Op*/1, /*Type*/GILLT_s16,
        GIM_RecordInsn, /*DefineMI*/2, /*MI*/1, /*OpIdx*/1, // MIs[2]
        GIM_CheckOpcode, /*MI*/2, GIMT_Encode2(TargetOpcode::G_TRUNC),
        GIM_CheckType, /*MI*/2, /*Op*/1, /*Type*/GILLT_s32,
        GIM_RecordInsn, /*DefineMI*/3, /*MI*/2, /*OpIdx*/1, // MIs[3]
        GIM_CheckOpcode, /*MI*/3, GIMT_Encode2(TargetOpcode::G_LSHR),
        GIM_CheckType, /*MI*/3, /*Op*/1, /*Type*/GILLT_s32,
        GIM_CheckType, /*MI*/3, /*Op*/2, /*Type*/GILLT_s32,
        GIM_CheckRegBankForClass, /*MI*/3, /*Op*/1, /*RC*/GIMT_Encode2(AMDGPU::VGPR_32RegClassID),
        GIM_CheckConstantInt8, /*MI*/3, /*Op*/2, 16,
        GIM_RecordInsn, /*DefineMI*/4, /*MI*/0, /*OpIdx*/2, // MIs[4]
        GIM_CheckOpcode, /*MI*/4, GIMT_Encode2(TargetOpcode::G_BITCAST),
        GIM_CheckType, /*MI*/4, /*Op*/1, /*Type*/GILLT_s16,
        GIM_RecordInsn, /*DefineMI*/5, /*MI*/4, /*OpIdx*/1, // MIs[5]
        GIM_CheckOpcode, /*MI*/5, GIMT_Encode2(TargetOpcode::G_TRUNC),
        GIM_CheckType, /*MI*/5, /*Op*/1, /*Type*/GILLT_s32,
        GIM_RecordInsn, /*DefineMI*/6, /*MI*/5, /*OpIdx*/1, // MIs[6]
        GIM_CheckOpcode, /*MI*/6, GIMT_Encode2(TargetOpcode::G_LSHR),
        GIM_CheckType, /*MI*/6, /*Op*/1, /*Type*/GILLT_s32,
        GIM_CheckType, /*MI*/6, /*Op*/2, /*Type*/GILLT_s32,
        GIM_CheckRegBankForClass, /*MI*/6, /*Op*/1, /*RC*/GIMT_Encode2(AMDGPU::VGPR_32RegClassID),
        GIM_CheckConstantInt8, /*MI*/6, /*Op*/2, 16,
        GIM_CheckCxxInsnPredicate, /*MI*/0, /*FnId*/GIMT_Encode2(GICXXPred_MI_Predicate_anonymous_35288),
        GIM_CheckIsSafeToFold, /*InsnID*/1,
        GIM_CheckIsSafeToFold, /*InsnID*/2,
        GIM_CheckIsSafeToFold, /*InsnID*/3,
        GIM_CheckIsSafeToFold, /*InsnID*/4,
        GIM_CheckIsSafeToFold, /*InsnID*/5,
        GIM_CheckIsSafeToFold, /*InsnID*/6,
        // (build_vector:{ *:[v2f16] } (bitconvert:{ *:[f16] } (trunc:{ *:[i16] } (srl:{ *:[i32] } VGPR_32:{ *:[i32] }:$a, 16:{ *:[i32] }))), (bitconvert:{ *:[f16] } (trunc:{ *:[i16] } (srl:{ *:[i32] } VGPR_32:{ *:[i32] }:$b, 16:{ *:[i32] }))))<<P:Predicate_anonymous_35288>>  =>  (V_PERM_B32_e64:{ *:[v2f16] } VGPR_32:{ *:[i32] }:$b, VGPR_32:{ *:[i32] }:$a, (S_MOV_B32:{ *:[i16] } 117834498:{ *:[i32] }))
        GIR_MakeTempReg, /*TempRegID*/0, /*TypeID*/GILLT_s16,
        GIR_BuildMI, /*InsnID*/1, /*Opcode*/GIMT_Encode2(AMDGPU::S_MOV_B32),
        GIR_AddTempRegister, /*InsnID*/1, /*TempRegID*/0, /*TempRegFlags*/GIMT_Encode2(RegState::Define),
        GIR_AddImm, /*InsnID*/1, /*Imm*/GIMT_Encode8(117834498),
        GIR_ConstrainSelectedInstOperands, /*InsnID*/1,
        GIR_BuildMI, /*InsnID*/0, /*Opcode*/GIMT_Encode2(AMDGPU::V_PERM_B32_e64),
        GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/0, // DstI[vdst]
        GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/6, /*OpIdx*/1, // b
        GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/3, /*OpIdx*/1, // a
        GIR_AddSimpleTempRegister, /*InsnID*/0, /*TempRegID*/0,
        GIR_ConstrainSelectedInstOperands, /*InsnID*/0,
        GIR_EraseFromParent, /*InsnID*/0,
        // GIR_Coverage, 6452,
        GIR_Done,
      // Label 431: @39835
      GIM_Try, /*On fail goto*//*Label 432*/ GIMT_Encode4(39963), // Rule ID 6441 //
        GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasVOP3PInsts),
        GIM_CheckRegBankForClass, /*MI*/0, /*Op*/0, /*RC*/GIMT_Encode2(AMDGPU::SReg_32RegClassID),
        GIM_RecordInsn, /*DefineMI*/1, /*MI*/0, /*OpIdx*/1, // MIs[1]
        GIM_CheckOpcode, /*MI*/1, GIMT_Encode2(TargetOpcode::G_TRUNC),
        GIM_CheckType, /*MI*/1, /*Op*/1, /*Type*/GILLT_s32,
        GIM_RecordInsn, /*DefineMI*/2, /*MI*/1, /*OpIdx*/1, // MIs[2]
        GIM_CheckOpcode, /*MI*/2, GIMT_Encode2(TargetOpcode::G_LSHR),
        GIM_CheckType, /*MI*/2, /*Op*/1, /*Type*/GILLT_s32,
        GIM_CheckType, /*MI*/2, /*Op*/2, /*Type*/GILLT_s32,
        GIM_CheckRegBankForClass, /*MI*/2, /*Op*/1, /*RC*/GIMT_Encode2(AMDGPU::SReg_32RegClassID),
        GIM_CheckConstantInt8, /*MI*/2, /*Op*/2, 16,
        GIM_CheckCxxInsnPredicate, /*MI*/2, /*FnId*/GIMT_Encode2(GICXXPred_MI_Predicate_srl_oneuse),
        GIM_RecordInsn, /*DefineMI*/3, /*MI*/0, /*OpIdx*/2, // MIs[3]
        GIM_CheckOpcode, /*MI*/3, GIMT_Encode2(TargetOpcode::G_TRUNC),
        GIM_CheckType, /*MI*/3, /*Op*/1, /*Type*/GILLT_s32,
        GIM_RecordInsn, /*DefineMI*/4, /*MI*/3, /*OpIdx*/1, // MIs[4]
        GIM_CheckOpcode, /*MI*/4, GIMT_Encode2(TargetOpcode::G_LSHR),
        GIM_CheckType, /*MI*/4, /*Op*/1, /*Type*/GILLT_s32,
        GIM_CheckType, /*MI*/4, /*Op*/2, /*Type*/GILLT_s32,
        GIM_CheckRegBankForClass, /*MI*/4, /*Op*/1, /*RC*/GIMT_Encode2(AMDGPU::SReg_32RegClassID),
        GIM_CheckConstantInt8, /*MI*/4, /*Op*/2, 16,
        GIM_CheckCxxInsnPredicate, /*MI*/4, /*FnId*/GIMT_Encode2(GICXXPred_MI_Predicate_srl_oneuse),
        GIM_CheckCxxInsnPredicate, /*MI*/0, /*FnId*/GIMT_Encode2(GICXXPred_MI_Predicate_anonymous_35286),
        GIM_CheckIsSafeToFold, /*InsnID*/1,
        GIM_CheckIsSafeToFold, /*InsnID*/2,
        GIM_CheckIsSafeToFold, /*InsnID*/3,
        GIM_CheckIsSafeToFold, /*InsnID*/4,
        // (build_vector:{ *:[v2i16] } (trunc:{ *:[i16] } (srl:{ *:[i32] } SReg_32:{ *:[i32] }:$src0, 16:{ *:[i32] })<<P:Predicate_srl_oneuse>>), (trunc:{ *:[i16] } (srl:{ *:[i32] } SReg_32:{ *:[i32] }:$src1, 16:{ *:[i32] })<<P:Predicate_srl_oneuse>>))<<P:Predicate_anonymous_35286>>  =>  (S_PACK_HH_B32_B16:{ *:[v2i16] } SReg_32:{ *:[i32] }:$src0, SReg_32:{ *:[i32] }:$src1)
        GIR_BuildMI, /*InsnID*/0, /*Opcode*/GIMT_Encode2(AMDGPU::S_PACK_HH_B32_B16),
        GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/0, // DstI[sdst]
        GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/2, /*OpIdx*/1, // src0
        GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/4, /*OpIdx*/1, // src1
        GIR_ConstrainSelectedInstOperands, /*InsnID*/0,
        GIR_EraseFromParent, /*InsnID*/0,
        // GIR_Coverage, 6441,
        GIR_Done,
      // Label 432: @39963
      GIM_Try, /*On fail goto*//*Label 433*/ GIMT_Encode4(40033), // Rule ID 6453 //
        GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasVOP3PInsts),
        GIM_CheckRegBankForClass, /*MI*/0, /*Op*/0, /*RC*/GIMT_Encode2(AMDGPU::VGPR_32RegClassID),
        GIM_CheckCxxInsnPredicate, /*MI*/0, /*FnId*/GIMT_Encode2(GICXXPred_MI_Predicate_anonymous_35316),
        GIM_CheckComplexPattern, /*MI*/0, /*Op*/1, /*Renderer*/GIMT_Encode2(0), GIMT_Encode2(GICP_gi_vop3mods),
        GIM_CheckComplexPattern, /*MI*/0, /*Op*/2, /*Renderer*/GIMT_Encode2(1), GIMT_Encode2(GICP_gi_vop3mods),
        // (build_vector:{ *:[v2f16] } (VOP3Mods:{ *:[f16] } VGPR_32:{ *:[f16] }:$src0, i32:{ *:[i32] }:$src0_mods), (VOP3Mods:{ *:[f16] } VGPR_32:{ *:[f16] }:$src1, i32:{ *:[i32] }:$src1_mods))<<P:Predicate_anonymous_35316>>  =>  (V_PACK_B32_F16_e64:{ *:[v2f16] } ?:{ *:[i32] }:$src0_mods, VGPR_32:{ *:[f16] }:$src0, ?:{ *:[i32] }:$src1_mods, VGPR_32:{ *:[f16] }:$src1)
        GIR_BuildMI, /*InsnID*/0, /*Opcode*/GIMT_Encode2(AMDGPU::V_PACK_B32_F16_e64),
        GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/0, // DstI[vdst]
        GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/1, // src0_mods
        GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/0, // src0
        GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(1), /*SubOperand*/1, // src1_mods
        GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(1), /*SubOperand*/0, // src1
        GIR_AddImm8, /*InsnID*/0, /*Imm*/0,
        GIR_AddImm8, /*InsnID*/0, /*Imm*/0,
        GIR_ConstrainSelectedInstOperands, /*InsnID*/0,
        GIR_EraseFromParent, /*InsnID*/0,
        // GIR_Coverage, 6453,
        GIR_Done,
      // Label 433: @40033
      GIM_Try, /*On fail goto*//*Label 434*/ GIMT_Encode4(40256),
        GIM_CheckRegBankForClass, /*MI*/0, /*Op*/0, /*RC*/GIMT_Encode2(AMDGPU::VGPR_32RegClassID),
        GIM_Try, /*On fail goto*//*Label 435*/ GIMT_Encode4(40149), // Rule ID 2257 //
          GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasMadMixInsts_NoFP32Denormals),
          GIM_RecordInsn, /*DefineMI*/1, /*MI*/0, /*OpIdx*/2, // MIs[1]
          GIM_CheckOpcode, /*MI*/1, GIMT_Encode2(TargetOpcode::G_FPTRUNC),
          GIM_CheckType, /*MI*/1, /*Op*/1, /*Type*/GILLT_s32,
          GIM_RecordInsn, /*DefineMI*/2, /*MI*/1, /*OpIdx*/1, // MIs[2]
          GIM_CheckOpcode, /*MI*/2, GIMT_Encode2(TargetOpcode::G_FMUL),
          GIM_CheckType, /*MI*/2, /*Op*/1, /*Type*/GILLT_s32,
          GIM_CheckType, /*MI*/2, /*Op*/2, /*Type*/GILLT_s32,
          GIM_CheckIsSafeToFold, /*InsnID*/1,
          GIM_CheckIsSafeToFold, /*InsnID*/2,
          GIM_CheckComplexPattern, /*MI*/2, /*Op*/1, /*Renderer*/GIMT_Encode2(0), GIMT_Encode2(GICP_gi_vop3_mad_mix_mods),
          GIM_CheckComplexPattern, /*MI*/2, /*Op*/2, /*Renderer*/GIMT_Encode2(1), GIMT_Encode2(GICP_gi_vop3_mad_mix_mods),
          // (build_vector:{ *:[v2f16] } f16:{ *:[f16] }:$elt0, (fpround:{ *:[f16] } (fmul:{ *:[f32] } (VOP3PMadMixMods:{ *:[f32] } f32:{ *:[f32] }:$src0, i32:{ *:[i32] }:$src0_modifiers), (VOP3PMadMixMods:{ *:[f32] } f32:{ *:[f32] }:$src1, i32:{ *:[i32] }:$src1_modifiers))))  =>  (V_MAD_MIXHI_F16:{ *:[v2f16] } ?:{ *:[i32] }:$src0_modifiers, ?:{ *:[f32] }:$src0, ?:{ *:[i32] }:$src1_modifiers, ?:{ *:[f32] }:$src1, 0:{ *:[i32] }, 0:{ *:[i32] }, 0:{ *:[i1] }, VGPR_32:{ *:[f16] }:$elt0)
          GIR_BuildMI, /*InsnID*/0, /*Opcode*/GIMT_Encode2(AMDGPU::V_MAD_MIXHI_F16),
          GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/0, // DstI[vdst]
          GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/1, // src0_modifiers
          GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/0, // src0
          GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(1), /*SubOperand*/1, // src1_modifiers
          GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(1), /*SubOperand*/0, // src1
          GIR_AddImm8, /*InsnID*/0, /*Imm*/0,
          GIR_AddImm8, /*InsnID*/0, /*Imm*/0,
          GIR_AddImm8, /*InsnID*/0, /*Imm*/0,
          GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/1, // elt0
          GIR_AddImm8, /*InsnID*/0, /*Imm*/0,
          GIR_AddImm8, /*InsnID*/0, /*Imm*/0,
          GIR_ConstrainSelectedInstOperands, /*InsnID*/0,
          GIR_EraseFromParent, /*InsnID*/0,
          // GIR_Coverage, 2257,
          GIR_Done,
        // Label 435: @40149
        GIM_Try, /*On fail goto*//*Label 436*/ GIMT_Encode4(40255), // Rule ID 2266 //
          GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasFmaMixInsts),
          GIM_RecordInsn, /*DefineMI*/1, /*MI*/0, /*OpIdx*/2, // MIs[1]
          GIM_CheckOpcode, /*MI*/1, GIMT_Encode2(TargetOpcode::G_FPTRUNC),
          GIM_CheckType, /*MI*/1, /*Op*/1, /*Type*/GILLT_s32,
          GIM_RecordInsn, /*DefineMI*/2, /*MI*/1, /*OpIdx*/1, // MIs[2]
          GIM_CheckOpcode, /*MI*/2, GIMT_Encode2(TargetOpcode::G_FMUL),
          GIM_CheckType, /*MI*/2, /*Op*/1, /*Type*/GILLT_s32,
          GIM_CheckType, /*MI*/2, /*Op*/2, /*Type*/GILLT_s32,
          GIM_CheckIsSafeToFold, /*InsnID*/1,
          GIM_CheckIsSafeToFold, /*InsnID*/2,
          GIM_CheckComplexPattern, /*MI*/2, /*Op*/1, /*Renderer*/GIMT_Encode2(0), GIMT_Encode2(GICP_gi_vop3_mad_mix_mods),
          GIM_CheckComplexPattern, /*MI*/2, /*Op*/2, /*Renderer*/GIMT_Encode2(1), GIMT_Encode2(GICP_gi_vop3_mad_mix_mods),
          // (build_vector:{ *:[v2f16] } f16:{ *:[f16] }:$elt0, (fpround:{ *:[f16] } (fmul:{ *:[f32] } (VOP3PMadMixMods:{ *:[f32] } f32:{ *:[f32] }:$src0, i32:{ *:[i32] }:$src0_modifiers), (VOP3PMadMixMods:{ *:[f32] } f32:{ *:[f32] }:$src1, i32:{ *:[i32] }:$src1_modifiers))))  =>  (V_FMA_MIXHI_F16:{ *:[v2f16] } ?:{ *:[i32] }:$src0_modifiers, ?:{ *:[f32] }:$src0, ?:{ *:[i32] }:$src1_modifiers, ?:{ *:[f32] }:$src1, 0:{ *:[i32] }, 0:{ *:[i32] }, 0:{ *:[i1] }, VGPR_32:{ *:[f16] }:$elt0)
          GIR_BuildMI, /*InsnID*/0, /*Opcode*/GIMT_Encode2(AMDGPU::V_FMA_MIXHI_F16),
          GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/0, // DstI[vdst]
          GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/1, // src0_modifiers
          GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/0, // src0
          GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(1), /*SubOperand*/1, // src1_modifiers
          GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(1), /*SubOperand*/0, // src1
          GIR_AddImm8, /*InsnID*/0, /*Imm*/0,
          GIR_AddImm8, /*InsnID*/0, /*Imm*/0,
          GIR_AddImm8, /*InsnID*/0, /*Imm*/0,
          GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/1, // elt0
          GIR_AddImm8, /*InsnID*/0, /*Imm*/0,
          GIR_AddImm8, /*InsnID*/0, /*Imm*/0,
          GIR_ConstrainSelectedInstOperands, /*InsnID*/0,
          GIR_EraseFromParent, /*InsnID*/0,
          // GIR_Coverage, 2266,
          GIR_Done,
        // Label 436: @40255
        GIM_Reject,
      // Label 434: @40256
      GIM_Try, /*On fail goto*//*Label 437*/ GIMT_Encode4(40617),
        GIM_CheckCxxInsnPredicate, /*MI*/0, /*FnId*/GIMT_Encode2(GICXXPred_MI_Predicate_anonymous_35288),
        GIM_CheckRegBankForClass, /*MI*/0, /*Op*/0, /*RC*/GIMT_Encode2(AMDGPU::VGPR_32RegClassID),
        GIM_Try, /*On fail goto*//*Label 438*/ GIMT_Encode4(40408), // Rule ID 6447 //
          GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasVOP3PInsts),
          GIM_RecordInsn, /*DefineMI*/1, /*MI*/0, /*OpIdx*/1, // MIs[1]
          GIM_CheckOpcode, /*MI*/1, GIMT_Encode2(TargetOpcode::G_TRUNC),
          GIM_CheckType, /*MI*/1, /*Op*/1, /*Type*/GILLT_s32,
          GIM_RecordInsn, /*DefineMI*/2, /*MI*/1, /*OpIdx*/1, // MIs[2]
          GIM_CheckOpcode, /*MI*/2, GIMT_Encode2(TargetOpcode::G_LSHR),
          GIM_CheckType, /*MI*/2, /*Op*/1, /*Type*/GILLT_s32,
          GIM_CheckType, /*MI*/2, /*Op*/2, /*Type*/GILLT_s32,
          GIM_CheckRegBankForClass, /*MI*/2, /*Op*/1, /*RC*/GIMT_Encode2(AMDGPU::VGPR_32RegClassID),
          GIM_CheckConstantInt8, /*MI*/2, /*Op*/2, 16,
          GIM_RecordInsn, /*DefineMI*/3, /*MI*/0, /*OpIdx*/2, // MIs[3]
          GIM_CheckOpcode, /*MI*/3, GIMT_Encode2(TargetOpcode::G_TRUNC),
          GIM_CheckType, /*MI*/3, /*Op*/1, /*Type*/GILLT_s32,
          GIM_RecordInsn, /*DefineMI*/4, /*MI*/3, /*OpIdx*/1, // MIs[4]
          GIM_CheckOpcode, /*MI*/4, GIMT_Encode2(TargetOpcode::G_LSHR),
          GIM_CheckType, /*MI*/4, /*Op*/1, /*Type*/GILLT_s32,
          GIM_CheckType, /*MI*/4, /*Op*/2, /*Type*/GILLT_s32,
          GIM_CheckRegBankForClass, /*MI*/4, /*Op*/1, /*RC*/GIMT_Encode2(AMDGPU::VGPR_32RegClassID),
          GIM_CheckConstantInt8, /*MI*/4, /*Op*/2, 16,
          GIM_CheckIsSafeToFold, /*InsnID*/1,
          GIM_CheckIsSafeToFold, /*InsnID*/2,
          GIM_CheckIsSafeToFold, /*InsnID*/3,
          GIM_CheckIsSafeToFold, /*InsnID*/4,
          // (build_vector:{ *:[v2i16] } (trunc:{ *:[i16] } (srl:{ *:[i32] } VGPR_32:{ *:[i32] }:$a, 16:{ *:[i32] })), (trunc:{ *:[i16] } (srl:{ *:[i32] } VGPR_32:{ *:[i32] }:$b, 16:{ *:[i32] })))<<P:Predicate_anonymous_35288>>  =>  (V_PERM_B32_e64:{ *:[v2i16] } VGPR_32:{ *:[i32] }:$b, VGPR_32:{ *:[i32] }:$a, (S_MOV_B32:{ *:[i16] } 117834498:{ *:[i32] }))
          GIR_MakeTempReg, /*TempRegID*/0, /*TypeID*/GILLT_s16,
          GIR_BuildMI, /*InsnID*/1, /*Opcode*/GIMT_Encode2(AMDGPU::S_MOV_B32),
          GIR_AddTempRegister, /*InsnID*/1, /*TempRegID*/0, /*TempRegFlags*/GIMT_Encode2(RegState::Define),
          GIR_AddImm, /*InsnID*/1, /*Imm*/GIMT_Encode8(117834498),
          GIR_ConstrainSelectedInstOperands, /*InsnID*/1,
          GIR_BuildMI, /*InsnID*/0, /*Opcode*/GIMT_Encode2(AMDGPU::V_PERM_B32_e64),
          GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/0, // DstI[vdst]
          GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/4, /*OpIdx*/1, // b
          GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/2, /*OpIdx*/1, // a
          GIR_AddSimpleTempRegister, /*InsnID*/0, /*TempRegID*/0,
          GIR_ConstrainSelectedInstOperands, /*InsnID*/0,
          GIR_EraseFromParent, /*InsnID*/0,
          // GIR_Coverage, 6447,
          GIR_Done,
        // Label 438: @40408
        GIM_Try, /*On fail goto*//*Label 439*/ GIMT_Encode4(40500), // Rule ID 6451 //
          GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasVOP3PInsts),
          GIM_RecordInsn, /*DefineMI*/1, /*MI*/0, /*OpIdx*/1, // MIs[1]
          GIM_CheckOpcode, /*MI*/1, GIMT_Encode2(TargetOpcode::G_BITCAST),
          GIM_CheckType, /*MI*/1, /*Op*/1, /*Type*/GILLT_s16,
          GIM_RecordInsn, /*DefineMI*/2, /*MI*/1, /*OpIdx*/1, // MIs[2]
          GIM_CheckOpcode, /*MI*/2, GIMT_Encode2(TargetOpcode::G_TRUNC),
          GIM_CheckType, /*MI*/2, /*Op*/1, /*Type*/GILLT_s32,
          GIM_RecordInsn, /*DefineMI*/3, /*MI*/2, /*OpIdx*/1, // MIs[3]
          GIM_CheckOpcode, /*MI*/3, GIMT_Encode2(TargetOpcode::G_LSHR),
          GIM_CheckType, /*MI*/3, /*Op*/1, /*Type*/GILLT_s32,
          GIM_CheckType, /*MI*/3, /*Op*/2, /*Type*/GILLT_s32,
          GIM_CheckRegBankForClass, /*MI*/3, /*Op*/1, /*RC*/GIMT_Encode2(AMDGPU::VGPR_32RegClassID),
          GIM_CheckConstantInt8, /*MI*/3, /*Op*/2, 16,
          GIM_CheckRegBankForClass, /*MI*/0, /*Op*/2, /*RC*/GIMT_Encode2(AMDGPU::VGPR_32RegClassID),
          GIM_CheckIsSafeToFold, /*InsnID*/1,
          GIM_CheckIsSafeToFold, /*InsnID*/2,
          GIM_CheckIsSafeToFold, /*InsnID*/3,
          // (build_vector:{ *:[v2f16] } (bitconvert:{ *:[f16] } (trunc:{ *:[i16] } (srl:{ *:[i32] } VGPR_32:{ *:[i32] }:$a, 16:{ *:[i32] }))), VGPR_32:{ *:[f16] }:$b)<<P:Predicate_anonymous_35288>>  =>  (V_ALIGNBIT_B32_e64:{ *:[v2f16] } VGPR_32:{ *:[f16] }:$b, VGPR_32:{ *:[i32] }:$a, 16:{ *:[i32] })
          GIR_BuildMI, /*InsnID*/0, /*Opcode*/GIMT_Encode2(AMDGPU::V_ALIGNBIT_B32_e64),
          GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/0, // DstI[vdst]
          GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/2, // b
          GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/3, /*OpIdx*/1, // a
          GIR_AddImm8, /*InsnID*/0, /*Imm*/16,
          GIR_ConstrainSelectedInstOperands, /*InsnID*/0,
          GIR_EraseFromParent, /*InsnID*/0,
          // GIR_Coverage, 6451,
          GIR_Done,
        // Label 439: @40500
        GIM_Try, /*On fail goto*//*Label 440*/ GIMT_Encode4(40616), // Rule ID 6450 //
          GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasVOP3PInsts),
          GIM_CheckRegBankForClass, /*MI*/0, /*Op*/1, /*RC*/GIMT_Encode2(AMDGPU::VGPR_32RegClassID),
          GIM_RecordInsn, /*DefineMI*/1, /*MI*/0, /*OpIdx*/2, // MIs[1]
          GIM_CheckOpcode, /*MI*/1, GIMT_Encode2(TargetOpcode::G_BITCAST),
          GIM_CheckType, /*MI*/1, /*Op*/1, /*Type*/GILLT_s16,
          GIM_RecordInsn, /*DefineMI*/2, /*MI*/1, /*OpIdx*/1, // MIs[2]
          GIM_CheckOpcode, /*MI*/2, GIMT_Encode2(TargetOpcode::G_TRUNC),
          GIM_CheckType, /*MI*/2, /*Op*/1, /*Type*/GILLT_s32,
          GIM_RecordInsn, /*DefineMI*/3, /*MI*/2, /*OpIdx*/1, // MIs[3]
          GIM_CheckOpcode, /*MI*/3, GIMT_Encode2(TargetOpcode::G_LSHR),
          GIM_CheckType, /*MI*/3, /*Op*/1, /*Type*/GILLT_s32,
          GIM_CheckType, /*MI*/3, /*Op*/2, /*Type*/GILLT_s32,
          GIM_CheckRegBankForClass, /*MI*/3, /*Op*/1, /*RC*/GIMT_Encode2(AMDGPU::VGPR_32RegClassID),
          GIM_CheckConstantInt8, /*MI*/3, /*Op*/2, 16,
          GIM_CheckIsSafeToFold, /*InsnID*/1,
          GIM_CheckIsSafeToFold, /*InsnID*/2,
          GIM_CheckIsSafeToFold, /*InsnID*/3,
          // (build_vector:{ *:[v2f16] } VGPR_32:{ *:[f16] }:$a, (bitconvert:{ *:[f16] } (trunc:{ *:[i16] } (srl:{ *:[i32] } VGPR_32:{ *:[i32] }:$b, 16:{ *:[i32] }))))<<P:Predicate_anonymous_35288>>  =>  (V_BFI_B32_e64:{ *:[v2f16] } (S_MOV_B32:{ *:[i16] } 65535:{ *:[i32] }), VGPR_32:{ *:[f16] }:$a, VGPR_32:{ *:[i32] }:$b)
          GIR_MakeTempReg, /*TempRegID*/0, /*TypeID*/GILLT_s16,
          GIR_BuildMI, /*InsnID*/1, /*Opcode*/GIMT_Encode2(AMDGPU::S_MOV_B32),
          GIR_AddTempRegister, /*InsnID*/1, /*TempRegID*/0, /*TempRegFlags*/GIMT_Encode2(RegState::Define),
          GIR_AddImm, /*InsnID*/1, /*Imm*/GIMT_Encode8(65535),
          GIR_ConstrainSelectedInstOperands, /*InsnID*/1,
          GIR_BuildMI, /*InsnID*/0, /*Opcode*/GIMT_Encode2(AMDGPU::V_BFI_B32_e64),
          GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/0, // DstI[vdst]
          GIR_AddSimpleTempRegister, /*InsnID*/0, /*TempRegID*/0,
          GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/1, // a
          GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/3, /*OpIdx*/1, // b
          GIR_ConstrainSelectedInstOperands, /*InsnID*/0,
          GIR_EraseFromParent, /*InsnID*/0,
          // GIR_Coverage, 6450,
          GIR_Done,
        // Label 440: @40616
        GIM_Reject,
      // Label 437: @40617
      GIM_Try, /*On fail goto*//*Label 441*/ GIMT_Encode4(40705), // Rule ID 6440 //
        GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasVOP3PInsts),
        GIM_CheckRegBankForClass, /*MI*/0, /*Op*/0, /*RC*/GIMT_Encode2(AMDGPU::SReg_32RegClassID),
        GIM_CheckRegBankForClass, /*MI*/0, /*Op*/1, /*RC*/GIMT_Encode2(AMDGPU::SReg_32RegClassID),
        GIM_RecordInsn, /*DefineMI*/1, /*MI*/0, /*OpIdx*/2, // MIs[1]
        GIM_CheckOpcode, /*MI*/1, GIMT_Encode2(TargetOpcode::G_TRUNC),
        GIM_CheckType, /*MI*/1, /*Op*/1, /*Type*/GILLT_s32,
        GIM_RecordInsn, /*DefineMI*/2, /*MI*/1, /*OpIdx*/1, // MIs[2]
        GIM_CheckOpcode, /*MI*/2, GIMT_Encode2(TargetOpcode::G_LSHR),
        GIM_CheckType, /*MI*/2, /*Op*/1, /*Type*/GILLT_s32,
        GIM_CheckType, /*MI*/2, /*Op*/2, /*Type*/GILLT_s32,
        GIM_CheckRegBankForClass, /*MI*/2, /*Op*/1, /*RC*/GIMT_Encode2(AMDGPU::SReg_32RegClassID),
        GIM_CheckConstantInt8, /*MI*/2, /*Op*/2, 16,
        GIM_CheckCxxInsnPredicate, /*MI*/2, /*FnId*/GIMT_Encode2(GICXXPred_MI_Predicate_srl_oneuse),
        GIM_CheckCxxInsnPredicate, /*MI*/0, /*FnId*/GIMT_Encode2(GICXXPred_MI_Predicate_anonymous_35286),
        GIM_CheckIsSafeToFold, /*InsnID*/1,
        GIM_CheckIsSafeToFold, /*InsnID*/2,
        // (build_vector:{ *:[v2i16] } SReg_32:{ *:[i16] }:$src0, (trunc:{ *:[i16] } (srl:{ *:[i32] } SReg_32:{ *:[i32] }:$src1, 16:{ *:[i32] })<<P:Predicate_srl_oneuse>>))<<P:Predicate_anonymous_35286>>  =>  (S_PACK_LH_B32_B16:{ *:[v2i16] } SReg_32:{ *:[i16] }:$src0, SReg_32:{ *:[i32] }:$src1)
        GIR_BuildMI, /*InsnID*/0, /*Opcode*/GIMT_Encode2(AMDGPU::S_PACK_LH_B32_B16),
        GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/0, // DstI[sdst]
        GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/1, // src0
        GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/2, /*OpIdx*/1, // src1
        GIR_ConstrainSelectedInstOperands, /*InsnID*/0,
        GIR_EraseFromParent, /*InsnID*/0,
        // GIR_Coverage, 6440,
        GIR_Done,
      // Label 441: @40705
      GIM_Try, /*On fail goto*//*Label 442*/ GIMT_Encode4(40792), // Rule ID 6446 //
        GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasVOP3PInsts),
        GIM_CheckRegBankForClass, /*MI*/0, /*Op*/0, /*RC*/GIMT_Encode2(AMDGPU::VGPR_32RegClassID),
        GIM_RecordInsn, /*DefineMI*/1, /*MI*/0, /*OpIdx*/1, // MIs[1]
        GIM_CheckOpcode, /*MI*/1, GIMT_Encode2(TargetOpcode::G_TRUNC),
        GIM_CheckType, /*MI*/1, /*Op*/1, /*Type*/GILLT_s32,
        GIM_RecordInsn, /*DefineMI*/2, /*MI*/1, /*OpIdx*/1, // MIs[2]
        GIM_CheckOpcode, /*MI*/2, GIMT_Encode2(TargetOpcode::G_LSHR),
        GIM_CheckType, /*MI*/2, /*Op*/1, /*Type*/GILLT_s32,
        GIM_CheckType, /*MI*/2, /*Op*/2, /*Type*/GILLT_s32,
        GIM_CheckRegBankForClass, /*MI*/2, /*Op*/1, /*RC*/GIMT_Encode2(AMDGPU::VGPR_32RegClassID),
        GIM_CheckConstantInt8, /*MI*/2, /*Op*/2, 16,
        GIM_CheckRegBankForClass, /*MI*/0, /*Op*/2, /*RC*/GIMT_Encode2(AMDGPU::VGPR_32RegClassID),
        GIM_CheckCxxInsnPredicate, /*MI*/0, /*FnId*/GIMT_Encode2(GICXXPred_MI_Predicate_anonymous_35288),
        GIM_CheckIsSafeToFold, /*InsnID*/1,
        GIM_CheckIsSafeToFold, /*InsnID*/2,
        // (build_vector:{ *:[v2i16] } (trunc:{ *:[i16] } (srl:{ *:[i32] } VGPR_32:{ *:[i32] }:$a, 16:{ *:[i32] })), VGPR_32:{ *:[i16] }:$b)<<P:Predicate_anonymous_35288>>  =>  (V_ALIGNBIT_B32_e64:{ *:[v2i16] } VGPR_32:{ *:[i16] }:$b, VGPR_32:{ *:[i32] }:$a, 16:{ *:[i32] })
        GIR_BuildMI, /*InsnID*/0, /*Opcode*/GIMT_Encode2(AMDGPU::V_ALIGNBIT_B32_e64),
        GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/0, // DstI[vdst]
        GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/2, // b
        GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/2, /*OpIdx*/1, // a
        GIR_AddImm8, /*InsnID*/0, /*Imm*/16,
        GIR_ConstrainSelectedInstOperands, /*InsnID*/0,
        GIR_EraseFromParent, /*InsnID*/0,
        // GIR_Coverage, 6446,
        GIR_Done,
      // Label 442: @40792
      GIM_Try, /*On fail goto*//*Label 443*/ GIMT_Encode4(40876), // Rule ID 6454 //
        GIM_CheckFeatures, GIMT_Encode2(GIFBS_isGFX11Plus),
        GIM_CheckRegBankForClass, /*MI*/0, /*Op*/0, /*RC*/GIMT_Encode2(AMDGPU::SReg_32RegClassID),
        GIM_RecordInsn, /*DefineMI*/1, /*MI*/0, /*OpIdx*/1, // MIs[1]
        GIM_CheckOpcode, /*MI*/1, GIMT_Encode2(TargetOpcode::G_TRUNC),
        GIM_CheckType, /*MI*/1, /*Op*/1, /*Type*/GILLT_s32,
        GIM_RecordInsn, /*DefineMI*/2, /*MI*/1, /*OpIdx*/1, // MIs[2]
        GIM_CheckOpcode, /*MI*/2, GIMT_Encode2(TargetOpcode::G_LSHR),
        GIM_CheckType, /*MI*/2, /*Op*/1, /*Type*/GILLT_s32,
        GIM_CheckType, /*MI*/2, /*Op*/2, /*Type*/GILLT_s32,
        GIM_CheckRegBankForClass, /*MI*/2, /*Op*/1, /*RC*/GIMT_Encode2(AMDGPU::SReg_32RegClassID),
        GIM_CheckConstantInt8, /*MI*/2, /*Op*/2, 16,
        GIM_CheckCxxInsnPredicate, /*MI*/2, /*FnId*/GIMT_Encode2(GICXXPred_MI_Predicate_srl_oneuse),
        GIM_CheckRegBankForClass, /*MI*/0, /*Op*/2, /*RC*/GIMT_Encode2(AMDGPU::SReg_32RegClassID),
        GIM_CheckIsSafeToFold, /*InsnID*/1,
        GIM_CheckIsSafeToFold, /*InsnID*/2,
        // (build_vector:{ *:[v2i16] } (trunc:{ *:[i16] } (srl:{ *:[i32] } SReg_32:{ *:[i32] }:$src0, 16:{ *:[i32] })<<P:Predicate_srl_oneuse>>), SReg_32:{ *:[i16] }:$src1)  =>  (S_PACK_HL_B32_B16:{ *:[v2i16] } SReg_32:{ *:[i32] }:$src0, SReg_32:{ *:[i16] }:$src1)
        GIR_BuildMI, /*InsnID*/0, /*Opcode*/GIMT_Encode2(AMDGPU::S_PACK_HL_B32_B16),
        GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/0, // DstI[sdst]
        GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/2, /*OpIdx*/1, // src0
        GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/2, // src1
        GIR_ConstrainSelectedInstOperands, /*InsnID*/0,
        GIR_EraseFromParent, /*InsnID*/0,
        // GIR_Coverage, 6454,
        GIR_Done,
      // Label 443: @40876
      GIM_Try, /*On fail goto*//*Label 444*/ GIMT_Encode4(40987), // Rule ID 6445 //
        GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasVOP3PInsts),
        GIM_CheckRegBankForClass, /*MI*/0, /*Op*/0, /*RC*/GIMT_Encode2(AMDGPU::VGPR_32RegClassID),
        GIM_CheckRegBankForClass, /*MI*/0, /*Op*/1, /*RC*/GIMT_Encode2(AMDGPU::VGPR_32RegClassID),
        GIM_RecordInsn, /*DefineMI*/1, /*MI*/0, /*OpIdx*/2, // MIs[1]
        GIM_CheckOpcode, /*MI*/1, GIMT_Encode2(TargetOpcode::G_TRUNC),
        GIM_CheckType, /*MI*/1, /*Op*/1, /*Type*/GILLT_s32,
        GIM_RecordInsn, /*DefineMI*/2, /*MI*/1, /*OpIdx*/1, // MIs[2]
        GIM_CheckOpcode, /*MI*/2, GIMT_Encode2(TargetOpcode::G_LSHR),
        GIM_CheckType, /*MI*/2, /*Op*/1, /*Type*/GILLT_s32,
        GIM_CheckType, /*MI*/2, /*Op*/2, /*Type*/GILLT_s32,
        GIM_CheckRegBankForClass, /*MI*/2, /*Op*/1, /*RC*/GIMT_Encode2(AMDGPU::VGPR_32RegClassID),
        GIM_CheckConstantInt8, /*MI*/2, /*Op*/2, 16,
        GIM_CheckCxxInsnPredicate, /*MI*/0, /*FnId*/GIMT_Encode2(GICXXPred_MI_Predicate_anonymous_35288),
        GIM_CheckIsSafeToFold, /*InsnID*/1,
        GIM_CheckIsSafeToFold, /*InsnID*/2,
        // (build_vector:{ *:[v2i16] } VGPR_32:{ *:[i16] }:$a, (trunc:{ *:[i16] } (srl:{ *:[i32] } VGPR_32:{ *:[i32] }:$b, 16:{ *:[i32] })))<<P:Predicate_anonymous_35288>>  =>  (V_BFI_B32_e64:{ *:[v2i16] } (S_MOV_B32:{ *:[i16] } 65535:{ *:[i32] }), VGPR_32:{ *:[i16] }:$a, VGPR_32:{ *:[i32] }:$b)
        GIR_MakeTempReg, /*TempRegID*/0, /*TypeID*/GILLT_s16,
        GIR_BuildMI, /*InsnID*/1, /*Opcode*/GIMT_Encode2(AMDGPU::S_MOV_B32),
        GIR_AddTempRegister, /*InsnID*/1, /*TempRegID*/0, /*TempRegFlags*/GIMT_Encode2(RegState::Define),
        GIR_AddImm, /*InsnID*/1, /*Imm*/GIMT_Encode8(65535),
        GIR_ConstrainSelectedInstOperands, /*InsnID*/1,
        GIR_BuildMI, /*InsnID*/0, /*Opcode*/GIMT_Encode2(AMDGPU::V_BFI_B32_e64),
        GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/0, // DstI[vdst]
        GIR_AddSimpleTempRegister, /*InsnID*/0, /*TempRegID*/0,
        GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/1, // a
        GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/2, /*OpIdx*/1, // b
        GIR_ConstrainSelectedInstOperands, /*InsnID*/0,
        GIR_EraseFromParent, /*InsnID*/0,
        // GIR_Coverage, 6445,
        GIR_Done,
      // Label 444: @40987
      GIM_Try, /*On fail goto*//*Label 445*/ GIMT_Encode4(41033), // Rule ID 6425 //
        GIM_CheckRegBankForClass, /*MI*/0, /*Op*/0, /*RC*/GIMT_Encode2(AMDGPU::SReg_32RegClassID),
        GIM_CheckConstantInt8, /*MI*/0, /*Op*/1, 0,
        GIM_CheckRegBankForClass, /*MI*/0, /*Op*/2, /*RC*/GIMT_Encode2(AMDGPU::SReg_32RegClassID),
        GIM_CheckCxxInsnPredicate, /*MI*/0, /*FnId*/GIMT_Encode2(GICXXPred_MI_Predicate_anonymous_35286),
        // (build_vector:{ *:[v2i16] } 0:{ *:[i16] }, SReg_32:{ *:[i16] }:$src1)<<P:Predicate_anonymous_35286>>  =>  (S_LSHL_B32:{ *:[v2i16] }:{ *:[i1] } SReg_32:{ *:[i16] }:$src1, 16:{ *:[i16] })
        GIR_BuildMI, /*InsnID*/0, /*Opcode*/GIMT_Encode2(AMDGPU::S_LSHL_B32),
        GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/0, // DstI[sdst]
        GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/2, // src1
        GIR_AddImm8, /*InsnID*/0, /*Imm*/16,
        GIR_SetImplicitDefDead, /*InsnID*/0, /*OpIdx for AMDGPU::SCC*/0,
        GIR_ConstrainSelectedInstOperands, /*InsnID*/0,
        GIR_EraseFromParent, /*InsnID*/0,
        // GIR_Coverage, 6425,
        GIR_Done,
      // Label 445: @41033
      GIM_Try, /*On fail goto*//*Label 446*/ GIMT_Encode4(41076), // Rule ID 6426 //
        GIM_CheckRegBankForClass, /*MI*/0, /*Op*/0, /*RC*/GIMT_Encode2(AMDGPU::VGPR_32RegClassID),
        GIM_CheckConstantInt8, /*MI*/0, /*Op*/1, 0,
        GIM_CheckRegBankForClass, /*MI*/0, /*Op*/2, /*RC*/GIMT_Encode2(AMDGPU::VGPR_32RegClassID),
        GIM_CheckCxxInsnPredicate, /*MI*/0, /*FnId*/GIMT_Encode2(GICXXPred_MI_Predicate_anonymous_35288),
        // (build_vector:{ *:[v2i16] } 0:{ *:[i16] }, VGPR_32:{ *:[i16] }:$src1)<<P:Predicate_anonymous_35288>>  =>  (V_LSHLREV_B32_e64:{ *:[v2i16] } 16:{ *:[i16] }, VGPR_32:{ *:[i16] }:$src1)
        GIR_BuildMI, /*InsnID*/0, /*Opcode*/GIMT_Encode2(AMDGPU::V_LSHLREV_B32_e64),
        GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/0, // DstI[vdst]
        GIR_AddImm8, /*InsnID*/0, /*Imm*/16,
        GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/2, // src1
        GIR_ConstrainSelectedInstOperands, /*InsnID*/0,
        GIR_EraseFromParent, /*InsnID*/0,
        // GIR_Coverage, 6426,
        GIR_Done,
      // Label 446: @41076
      GIM_Try, /*On fail goto*//*Label 447*/ GIMT_Encode4(41146), // Rule ID 6427 //
        GIM_CheckRegBankForClass, /*MI*/0, /*Op*/0, /*RC*/GIMT_Encode2(AMDGPU::SReg_32RegClassID),
        GIM_CheckRegBankForClass, /*MI*/0, /*Op*/1, /*RC*/GIMT_Encode2(AMDGPU::SReg_32RegClassID),
        GIM_CheckConstantInt8, /*MI*/0, /*Op*/2, 0,
        GIM_CheckCxxInsnPredicate, /*MI*/0, /*FnId*/GIMT_Encode2(GICXXPred_MI_Predicate_anonymous_35286),
        // (build_vector:{ *:[v2i16] } SReg_32:{ *:[i16] }:$src1, 0:{ *:[i16] })<<P:Predicate_anonymous_35286>>  =>  (S_AND_B32:{ *:[v2i16] }:{ *:[i1] } (S_MOV_B32:{ *:[i1] } 65535:{ *:[i32] }), SReg_32:{ *:[i16] }:$src1)
        GIR_MakeTempReg, /*TempRegID*/0, /*TypeID*/GILLT_s1,
        GIR_BuildMI, /*InsnID*/1, /*Opcode*/GIMT_Encode2(AMDGPU::S_MOV_B32),
        GIR_AddTempRegister, /*InsnID*/1, /*TempRegID*/0, /*TempRegFlags*/GIMT_Encode2(RegState::Define),
        GIR_AddImm, /*InsnID*/1, /*Imm*/GIMT_Encode8(65535),
        GIR_ConstrainSelectedInstOperands, /*InsnID*/1,
        GIR_BuildMI, /*InsnID*/0, /*Opcode*/GIMT_Encode2(AMDGPU::S_AND_B32),
        GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/0, // DstI[sdst]
        GIR_AddSimpleTempRegister, /*InsnID*/0, /*TempRegID*/0,
        GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/1, // src1
        GIR_SetImplicitDefDead, /*InsnID*/0, /*OpIdx for AMDGPU::SCC*/0,
        GIR_ConstrainSelectedInstOperands, /*InsnID*/0,
        GIR_EraseFromParent, /*InsnID*/0,
        // GIR_Coverage, 6427,
        GIR_Done,
      // Label 447: @41146
      GIM_Try, /*On fail goto*//*Label 448*/ GIMT_Encode4(41213), // Rule ID 6428 //
        GIM_CheckRegBankForClass, /*MI*/0, /*Op*/0, /*RC*/GIMT_Encode2(AMDGPU::VGPR_32RegClassID),
        GIM_CheckRegBankForClass, /*MI*/0, /*Op*/1, /*RC*/GIMT_Encode2(AMDGPU::VGPR_32RegClassID),
        GIM_CheckConstantInt8, /*MI*/0, /*Op*/2, 0,
        GIM_CheckCxxInsnPredicate, /*MI*/0, /*FnId*/GIMT_Encode2(GICXXPred_MI_Predicate_anonymous_35288),
        // (build_vector:{ *:[v2i16] } VGPR_32:{ *:[i16] }:$src1, 0:{ *:[i16] })<<P:Predicate_anonymous_35288>>  =>  (V_AND_B32_e64:{ *:[v2i16] } (V_MOV_B32_e32:{ *:[i32] } 65535:{ *:[i32] }), VGPR_32:{ *:[i16] }:$src1)
        GIR_MakeTempReg, /*TempRegID*/0, /*TypeID*/GILLT_s32,
        GIR_BuildMI, /*InsnID*/1, /*Opcode*/GIMT_Encode2(AMDGPU::V_MOV_B32_e32),
        GIR_AddTempRegister, /*InsnID*/1, /*TempRegID*/0, /*TempRegFlags*/GIMT_Encode2(RegState::Define),
        GIR_AddImm, /*InsnID*/1, /*Imm*/GIMT_Encode8(65535),
        GIR_ConstrainSelectedInstOperands, /*InsnID*/1,
        GIR_BuildMI, /*InsnID*/0, /*Opcode*/GIMT_Encode2(AMDGPU::V_AND_B32_e64),
        GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/0, // DstI[vdst]
        GIR_AddSimpleTempRegister, /*InsnID*/0, /*TempRegID*/0,
        GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/1, // src1
        GIR_ConstrainSelectedInstOperands, /*InsnID*/0,
        GIR_EraseFromParent, /*InsnID*/0,
        // GIR_Coverage, 6428,
        GIR_Done,
      // Label 448: @41213
      GIM_Try, /*On fail goto*//*Label 449*/ GIMT_Encode4(41265), // Rule ID 6434 //
        GIM_CheckRegBankForClass, /*MI*/0, /*Op*/0, /*RC*/GIMT_Encode2(AMDGPU::SReg_32RegClassID),
        GIM_RecordInsn, /*DefineMI*/1, /*MI*/0, /*OpIdx*/1, // MIs[1]
        GIM_CheckOpcode, /*MI*/1, GIMT_Encode2(TargetOpcode::G_IMPLICIT_DEF),
        GIM_CheckRegBankForClass, /*MI*/0, /*Op*/2, /*RC*/GIMT_Encode2(AMDGPU::SReg_32RegClassID),
        GIM_CheckCxxInsnPredicate, /*MI*/0, /*FnId*/GIMT_Encode2(GICXXPred_MI_Predicate_anonymous_35286),
        GIM_CheckIsSafeToFold, /*InsnID*/1,
        // (build_vector:{ *:[v2i16] } (undef:{ *:[i16] }), SReg_32:{ *:[i16] }:$src1)<<P:Predicate_anonymous_35286>>  =>  (S_LSHL_B32:{ *:[v2i16] }:{ *:[i1] } SReg_32:{ *:[i16] }:$src1, 16:{ *:[i32] })
        GIR_BuildMI, /*InsnID*/0, /*Opcode*/GIMT_Encode2(AMDGPU::S_LSHL_B32),
        GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/0, // DstI[sdst]
        GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/2, // src1
        GIR_AddImm8, /*InsnID*/0, /*Imm*/16,
        GIR_SetImplicitDefDead, /*InsnID*/0, /*OpIdx for AMDGPU::SCC*/0,
        GIR_ConstrainSelectedInstOperands, /*InsnID*/0,
        GIR_EraseFromParent, /*InsnID*/0,
        // GIR_Coverage, 6434,
        GIR_Done,
      // Label 449: @41265
      GIM_Try, /*On fail goto*//*Label 450*/ GIMT_Encode4(41314), // Rule ID 6435 //
        GIM_CheckRegBankForClass, /*MI*/0, /*Op*/0, /*RC*/GIMT_Encode2(AMDGPU::VGPR_32RegClassID),
        GIM_RecordInsn, /*DefineMI*/1, /*MI*/0, /*OpIdx*/1, // MIs[1]
        GIM_CheckOpcode, /*MI*/1, GIMT_Encode2(TargetOpcode::G_IMPLICIT_DEF),
        GIM_CheckRegBankForClass, /*MI*/0, /*Op*/2, /*RC*/GIMT_Encode2(AMDGPU::VGPR_32RegClassID),
        GIM_CheckCxxInsnPredicate, /*MI*/0, /*FnId*/GIMT_Encode2(GICXXPred_MI_Predicate_anonymous_35288),
        GIM_CheckIsSafeToFold, /*InsnID*/1,
        // (build_vector:{ *:[v2i16] } (undef:{ *:[i16] }), VGPR_32:{ *:[i16] }:$src1)<<P:Predicate_anonymous_35288>>  =>  (V_LSHLREV_B32_e64:{ *:[v2i16] } 16:{ *:[i32] }, VGPR_32:{ *:[i16] }:$src1)
        GIR_BuildMI, /*InsnID*/0, /*Opcode*/GIMT_Encode2(AMDGPU::V_LSHLREV_B32_e64),
        GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/0, // DstI[vdst]
        GIR_AddImm8, /*InsnID*/0, /*Imm*/16,
        GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/2, // src1
        GIR_ConstrainSelectedInstOperands, /*InsnID*/0,
        GIR_EraseFromParent, /*InsnID*/0,
        // GIR_Coverage, 6435,
        GIR_Done,
      // Label 450: @41314
      GIM_Try, /*On fail goto*//*Label 451*/ GIMT_Encode4(41366), // Rule ID 6436 //
        GIM_CheckRegBankForClass, /*MI*/0, /*Op*/0, /*RC*/GIMT_Encode2(AMDGPU::SReg_32RegClassID),
        GIM_RecordInsn, /*DefineMI*/1, /*MI*/0, /*OpIdx*/1, // MIs[1]
        GIM_CheckOpcode, /*MI*/1, GIMT_Encode2(TargetOpcode::G_IMPLICIT_DEF),
        GIM_CheckRegBankForClass, /*MI*/0, /*Op*/2, /*RC*/GIMT_Encode2(AMDGPU::SReg_32RegClassID),
        GIM_CheckCxxInsnPredicate, /*MI*/0, /*FnId*/GIMT_Encode2(GICXXPred_MI_Predicate_anonymous_35286),
        GIM_CheckIsSafeToFold, /*InsnID*/1,
        // (build_vector:{ *:[v2f16] } (undef:{ *:[f16] }), SReg_32:{ *:[f16] }:$src1)<<P:Predicate_anonymous_35286>>  =>  (S_LSHL_B32:{ *:[v2f16] }:{ *:[i1] } SReg_32:{ *:[f16] }:$src1, 16:{ *:[i32] })
        GIR_BuildMI, /*InsnID*/0, /*Opcode*/GIMT_Encode2(AMDGPU::S_LSHL_B32),
        GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/0, // DstI[sdst]
        GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/2, // src1
        GIR_AddImm8, /*InsnID*/0, /*Imm*/16,
        GIR_SetImplicitDefDead, /*InsnID*/0, /*OpIdx for AMDGPU::SCC*/0,
        GIR_ConstrainSelectedInstOperands, /*InsnID*/0,
        GIR_EraseFromParent, /*InsnID*/0,
        // GIR_Coverage, 6436,
        GIR_Done,
      // Label 451: @41366
      GIM_Try, /*On fail goto*//*Label 452*/ GIMT_Encode4(41415), // Rule ID 6437 //
        GIM_CheckRegBankForClass, /*MI*/0, /*Op*/0, /*RC*/GIMT_Encode2(AMDGPU::VGPR_32RegClassID),
        GIM_RecordInsn, /*DefineMI*/1, /*MI*/0, /*OpIdx*/1, // MIs[1]
        GIM_CheckOpcode, /*MI*/1, GIMT_Encode2(TargetOpcode::G_IMPLICIT_DEF),
        GIM_CheckRegBankForClass, /*MI*/0, /*Op*/2, /*RC*/GIMT_Encode2(AMDGPU::VGPR_32RegClassID),
        GIM_CheckCxxInsnPredicate, /*MI*/0, /*FnId*/GIMT_Encode2(GICXXPred_MI_Predicate_anonymous_35288),
        GIM_CheckIsSafeToFold, /*InsnID*/1,
        // (build_vector:{ *:[v2f16] } (undef:{ *:[f16] }), VGPR_32:{ *:[f16] }:$src1)<<P:Predicate_anonymous_35288>>  =>  (V_LSHLREV_B32_e64:{ *:[v2f16] } 16:{ *:[i32] }, VGPR_32:{ *:[f16] }:$src1)
        GIR_BuildMI, /*InsnID*/0, /*Opcode*/GIMT_Encode2(AMDGPU::V_LSHLREV_B32_e64),
        GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/0, // DstI[vdst]
        GIR_AddImm8, /*InsnID*/0, /*Imm*/16,
        GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/2, // src1
        GIR_ConstrainSelectedInstOperands, /*InsnID*/0,
        GIR_EraseFromParent, /*InsnID*/0,
        // GIR_Coverage, 6437,
        GIR_Done,
      // Label 452: @41415
      GIM_Try, /*On fail goto*//*Label 453*/ GIMT_Encode4(41464), // Rule ID 6431 //
        GIM_CheckRegBankForClass, /*MI*/0, /*Op*/0, /*RC*/GIMT_Encode2(AMDGPU::SReg_32RegClassID),
        GIM_CheckRegBankForClass, /*MI*/0, /*Op*/1, /*RC*/GIMT_Encode2(AMDGPU::SReg_32RegClassID),
        GIM_RecordInsn, /*DefineMI*/1, /*MI*/0, /*OpIdx*/2, // MIs[1]
        GIM_CheckOpcode, /*MI*/1, GIMT_Encode2(TargetOpcode::G_IMPLICIT_DEF),
        GIM_CheckCxxInsnPredicate, /*MI*/0, /*FnId*/GIMT_Encode2(GICXXPred_MI_Predicate_anonymous_35286),
        GIM_CheckIsSafeToFold, /*InsnID*/1,
        // (build_vector:{ *:[v2i16] } SReg_32:{ *:[i16] }:$src0, (undef:{ *:[i16] }))<<P:Predicate_anonymous_35286>>  =>  (COPY_TO_REGCLASS:{ *:[v2i16] } SReg_32:{ *:[i16] }:$src0, SReg_32:{ *:[i32] })
        GIR_BuildMI, /*InsnID*/0, /*Opcode*/GIMT_Encode2(TargetOpcode::COPY),
        GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/0, // DstI[dst]
        GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/1, // src0
        GIR_ConstrainOperandRC, /*InsnID*/0, /*Op*/0, GIMT_Encode2(AMDGPU::SReg_32RegClassID),
        GIR_EraseFromParent, /*InsnID*/0,
        // GIR_Coverage, 6431,
        GIR_Done,
      // Label 453: @41464
      GIM_Try, /*On fail goto*//*Label 454*/ GIMT_Encode4(41513), // Rule ID 6432 //
        GIM_CheckRegBankForClass, /*MI*/0, /*Op*/0, /*RC*/GIMT_Encode2(AMDGPU::VGPR_32RegClassID),
        GIM_CheckRegBankForClass, /*MI*/0, /*Op*/1, /*RC*/GIMT_Encode2(AMDGPU::VGPR_32RegClassID),
        GIM_RecordInsn, /*DefineMI*/1, /*MI*/0, /*OpIdx*/2, // MIs[1]
        GIM_CheckOpcode, /*MI*/1, GIMT_Encode2(TargetOpcode::G_IMPLICIT_DEF),
        GIM_CheckCxxInsnPredicate, /*MI*/0, /*FnId*/GIMT_Encode2(GICXXPred_MI_Predicate_anonymous_35288),
        GIM_CheckIsSafeToFold, /*InsnID*/1,
        // (build_vector:{ *:[v2i16] } VGPR_32:{ *:[i16] }:$src0, (undef:{ *:[i16] }))<<P:Predicate_anonymous_35288>>  =>  (COPY_TO_REGCLASS:{ *:[v2i16] } VGPR_32:{ *:[i16] }:$src0, VGPR_32:{ *:[i32] })
        GIR_BuildMI, /*InsnID*/0, /*Opcode*/GIMT_Encode2(TargetOpcode::COPY),
        GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/0, // DstI[dst]
        GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/1, // src0
        GIR_ConstrainOperandRC, /*InsnID*/0, /*Op*/0, GIMT_Encode2(AMDGPU::VGPR_32RegClassID),
        GIR_EraseFromParent, /*InsnID*/0,
        // GIR_Coverage, 6432,
        GIR_Done,
      // Label 454: @41513
      GIM_Try, /*On fail goto*//*Label 455*/ GIMT_Encode4(41548), // Rule ID 6438 //
        GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasVOP3PInsts),
        GIM_CheckRegBankForClass, /*MI*/0, /*Op*/0, /*RC*/GIMT_Encode2(AMDGPU::SReg_32RegClassID),
        GIM_CheckRegBankForClass, /*MI*/0, /*Op*/1, /*RC*/GIMT_Encode2(AMDGPU::SReg_32RegClassID),
        GIM_CheckRegBankForClass, /*MI*/0, /*Op*/2, /*RC*/GIMT_Encode2(AMDGPU::SReg_32RegClassID),
        GIM_CheckCxxInsnPredicate, /*MI*/0, /*FnId*/GIMT_Encode2(GICXXPred_MI_Predicate_anonymous_35286),
        // (build_vector:{ *:[v2i16] } SReg_32:{ *:[i16] }:$src0, SReg_32:{ *:[i16] }:$src1)<<P:Predicate_anonymous_35286>>  =>  (S_PACK_LL_B32_B16:{ *:[v2i16] } SReg_32:{ *:[i16] }:$src0, SReg_32:{ *:[i16] }:$src1)
        GIR_MutateOpcode, /*InsnID*/0, /*RecycleInsnID*/0, /*Opcode*/GIMT_Encode2(AMDGPU::S_PACK_LL_B32_B16),
        GIR_ConstrainSelectedInstOperands, /*InsnID*/0,
        // GIR_Coverage, 6438,
        GIR_Done,
      // Label 455: @41548
      GIM_Try, /*On fail goto*//*Label 456*/ GIMT_Encode4(41643), // Rule ID 6439 //
        GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasVOP3PInsts),
        GIM_CheckRegBankForClass, /*MI*/0, /*Op*/0, /*RC*/GIMT_Encode2(AMDGPU::VGPR_32RegClassID),
        GIM_CheckRegBankForClass, /*MI*/0, /*Op*/1, /*RC*/GIMT_Encode2(AMDGPU::VGPR_32RegClassID),
        GIM_CheckRegBankForClass, /*MI*/0, /*Op*/2, /*RC*/GIMT_Encode2(AMDGPU::VGPR_32RegClassID),
        GIM_CheckCxxInsnPredicate, /*MI*/0, /*FnId*/GIMT_Encode2(GICXXPred_MI_Predicate_anonymous_35288),
        // (build_vector:{ *:[v2i16] } VGPR_32:{ *:[i16] }:$src0, VGPR_32:{ *:[i16] }:$src1)<<P:Predicate_anonymous_35288>>  =>  (V_LSHL_OR_B32_e64:{ *:[v2i16] } ?:{ *:[i16] }:$src1, 16:{ *:[i32] }, (V_AND_B32_e64:{ *:[i32] } (V_MOV_B32_e32:{ *:[i32] } 65535:{ *:[i32] }), ?:{ *:[i16] }:$src0))
        GIR_MakeTempReg, /*TempRegID*/0, /*TypeID*/GILLT_s32,
        GIR_MakeTempReg, /*TempRegID*/1, /*TypeID*/GILLT_s32,
        GIR_BuildMI, /*InsnID*/2, /*Opcode*/GIMT_Encode2(AMDGPU::V_MOV_B32_e32),
        GIR_AddTempRegister, /*InsnID*/2, /*TempRegID*/1, /*TempRegFlags*/GIMT_Encode2(RegState::Define),
        GIR_AddImm, /*InsnID*/2, /*Imm*/GIMT_Encode8(65535),
        GIR_ConstrainSelectedInstOperands, /*InsnID*/2,
        GIR_BuildMI, /*InsnID*/1, /*Opcode*/GIMT_Encode2(AMDGPU::V_AND_B32_e64),
        GIR_AddTempRegister, /*InsnID*/1, /*TempRegID*/0, /*TempRegFlags*/GIMT_Encode2(RegState::Define),
        GIR_AddSimpleTempRegister, /*InsnID*/1, /*TempRegID*/1,
        GIR_Copy, /*NewInsnID*/1, /*OldInsnID*/0, /*OpIdx*/1, // src0
        GIR_ConstrainSelectedInstOperands, /*InsnID*/1,
        GIR_BuildMI, /*InsnID*/0, /*Opcode*/GIMT_Encode2(AMDGPU::V_LSHL_OR_B32_e64),
        GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/0, // DstI[vdst]
        GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/2, // src1
        GIR_AddImm8, /*InsnID*/0, /*Imm*/16,
        GIR_AddSimpleTempRegister, /*InsnID*/0, /*TempRegID*/0,
        GIR_ConstrainSelectedInstOperands, /*InsnID*/0,
        GIR_EraseFromParent, /*InsnID*/0,
        // GIR_Coverage, 6439,
        GIR_Done,
      // Label 456: @41643
      GIM_Try, /*On fail goto*//*Label 457*/ GIMT_Encode4(41678), // Rule ID 6442 //
        GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasVOP3PInsts),
        GIM_CheckRegBankForClass, /*MI*/0, /*Op*/0, /*RC*/GIMT_Encode2(AMDGPU::SReg_32RegClassID),
        GIM_CheckRegBankForClass, /*MI*/0, /*Op*/1, /*RC*/GIMT_Encode2(AMDGPU::SReg_32RegClassID),
        GIM_CheckRegBankForClass, /*MI*/0, /*Op*/2, /*RC*/GIMT_Encode2(AMDGPU::SReg_32RegClassID),
        GIM_CheckCxxInsnPredicate, /*MI*/0, /*FnId*/GIMT_Encode2(GICXXPred_MI_Predicate_anonymous_35286),
        // (build_vector:{ *:[v2f16] } SReg_32:{ *:[f16] }:$src0, SReg_32:{ *:[f16] }:$src1)<<P:Predicate_anonymous_35286>>  =>  (S_PACK_LL_B32_B16:{ *:[v2f16] } SReg_32:{ *:[f16] }:$src0, SReg_32:{ *:[f16] }:$src1)
        GIR_MutateOpcode, /*InsnID*/0, /*RecycleInsnID*/0, /*Opcode*/GIMT_Encode2(AMDGPU::S_PACK_LL_B32_B16),
        GIR_ConstrainSelectedInstOperands, /*InsnID*/0,
        // GIR_Coverage, 6442,
        GIR_Done,
      // Label 457: @41678
      GIM_Try, /*On fail goto*//*Label 458*/ GIMT_Encode4(41815),
        GIM_CheckCxxInsnPredicate, /*MI*/0, /*FnId*/GIMT_Encode2(GICXXPred_MI_Predicate_anonymous_35288),
        GIM_CheckRegBankForClass, /*MI*/0, /*Op*/0, /*RC*/GIMT_Encode2(AMDGPU::VGPR_32RegClassID),
        GIM_CheckRegBankForClass, /*MI*/0, /*Op*/1, /*RC*/GIMT_Encode2(AMDGPU::VGPR_32RegClassID),
        GIM_CheckRegBankForClass, /*MI*/0, /*Op*/2, /*RC*/GIMT_Encode2(AMDGPU::VGPR_32RegClassID),
        GIM_Try, /*On fail goto*//*Label 459*/ GIMT_Encode4(41758), // Rule ID 6443 //
          GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasVOP3PInsts),
          // (build_vector:{ *:[v2i16] } VGPR_32:{ *:[i16] }:$a, VGPR_32:{ *:[i16] }:$b)<<P:Predicate_anonymous_35288>>  =>  (V_PERM_B32_e64:{ *:[v2i16] } VGPR_32:{ *:[i16] }:$b, VGPR_32:{ *:[i16] }:$a, (S_MOV_B32:{ *:[i16] } 84148480:{ *:[i32] }))
          GIR_MakeTempReg, /*TempRegID*/0, /*TypeID*/GILLT_s16,
          GIR_BuildMI, /*InsnID*/1, /*Opcode*/GIMT_Encode2(AMDGPU::S_MOV_B32),
          GIR_AddTempRegister, /*InsnID*/1, /*TempRegID*/0, /*TempRegFlags*/GIMT_Encode2(RegState::Define),
          GIR_AddImm, /*InsnID*/1, /*Imm*/GIMT_Encode8(84148480),
          GIR_ConstrainSelectedInstOperands, /*InsnID*/1,
          GIR_BuildMI, /*InsnID*/0, /*Opcode*/GIMT_Encode2(AMDGPU::V_PERM_B32_e64),
          GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/0, // DstI[vdst]
          GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/2, // b
          GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/1, // a
          GIR_AddSimpleTempRegister, /*InsnID*/0, /*TempRegID*/0,
          GIR_ConstrainSelectedInstOperands, /*InsnID*/0,
          GIR_EraseFromParent, /*InsnID*/0,
          // GIR_Coverage, 6443,
          GIR_Done,
        // Label 459: @41758
        GIM_Try, /*On fail goto*//*Label 460*/ GIMT_Encode4(41814), // Rule ID 6448 //
          GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasVOP3PInsts),
          // (build_vector:{ *:[v2f16] } VGPR_32:{ *:[f16] }:$a, VGPR_32:{ *:[f16] }:$b)<<P:Predicate_anonymous_35288>>  =>  (V_PERM_B32_e64:{ *:[v2f16] } VGPR_32:{ *:[f16] }:$b, VGPR_32:{ *:[f16] }:$a, (S_MOV_B32:{ *:[i16] } 84148480:{ *:[i32] }))
          GIR_MakeTempReg, /*TempRegID*/0, /*TypeID*/GILLT_s16,
          GIR_BuildMI, /*InsnID*/1, /*Opcode*/GIMT_Encode2(AMDGPU::S_MOV_B32),
          GIR_AddTempRegister, /*InsnID*/1, /*TempRegID*/0, /*TempRegFlags*/GIMT_Encode2(RegState::Define),
          GIR_AddImm, /*InsnID*/1, /*Imm*/GIMT_Encode8(84148480),
          GIR_ConstrainSelectedInstOperands, /*InsnID*/1,
          GIR_BuildMI, /*InsnID*/0, /*Opcode*/GIMT_Encode2(AMDGPU::V_PERM_B32_e64),
          GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/0, // DstI[vdst]
          GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/2, // b
          GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/1, // a
          GIR_AddSimpleTempRegister, /*InsnID*/0, /*TempRegID*/0,
          GIR_ConstrainSelectedInstOperands, /*InsnID*/0,
          GIR_EraseFromParent, /*InsnID*/0,
          // GIR_Coverage, 6448,
          GIR_Done,
        // Label 460: @41814
        GIM_Reject,
      // Label 458: @41815
      GIM_Reject,
    // Label 425: @41816
    GIM_Reject,
    // Label 8: @41817
    GIM_SwitchType, /*MI*/0, /*Op*/0, /*[*/GIMT_Encode2(8), GIMT_Encode2(34), /*)*//*default:*//*Label 487*/ GIMT_Encode4(53147),
    /*GILLT_s16*//*Label 461*/ GIMT_Encode4(41932),
    /*GILLT_s32*//*Label 462*/ GIMT_Encode4(42363),
    /*GILLT_s64*//*Label 463*/ GIMT_Encode4(42832),
    /*GILLT_v2s16*//*Label 464*/ GIMT_Encode4(43301),
    /*GILLT_v2s32*//*Label 465*/ GIMT_Encode4(44004),
    /*GILLT_v2s64*//*Label 466*/ GIMT_Encode4(44512),
    /*GILLT_v3s32*//*Label 467*/ GIMT_Encode4(45059),
    /*GILLT_v3s64*//*Label 468*/ GIMT_Encode4(45130),
    /*GILLT_v4s16*//*Label 469*/ GIMT_Encode4(45365),
    /*GILLT_v4s32*//*Label 470*/ GIMT_Encode4(46068),
    /*GILLT_v4s64*//*Label 471*/ GIMT_Encode4(46615),
    /*GILLT_v5s32*//*Label 472*/ GIMT_Encode4(47084),
    /*GILLT_v6s32*//*Label 473*/ GIMT_Encode4(47235),
    /*GILLT_v7s32*//*Label 474*/ GIMT_Encode4(47548),
    /*GILLT_v8s16*//*Label 475*/ GIMT_Encode4(47699),
    /*GILLT_v8s32*//*Label 476*/ GIMT_Encode4(48792),
    /*GILLT_v8s64*//*Label 477*/ GIMT_Encode4(49339),
    /*GILLT_v9s32*//*Label 478*/ GIMT_Encode4(49730),
    /*GILLT_v10s32*//*Label 479*/ GIMT_Encode4(49881),
    /*GILLT_v11s32*//*Label 480*/ GIMT_Encode4(50032),
    /*GILLT_v12s32*//*Label 481*/ GIMT_Encode4(50183),
    /*GILLT_v16s16*//*Label 482*/ GIMT_Encode4(50334),
    /*GILLT_v16s32*//*Label 483*/ GIMT_Encode4(51271),
    /*GILLT_v16s64*//*Label 484*/ GIMT_Encode4(51818),
    /*GILLT_v32s16*//*Label 485*/ GIMT_Encode4(52053),
    /*GILLT_v32s32*//*Label 486*/ GIMT_Encode4(52912),
    // Label 461: @41932
    GIM_Try, /*On fail goto*//*Label 488*/ GIMT_Encode4(42362),
      GIM_CheckType, /*MI*/0, /*Op*/1, /*Type*/GILLT_s16,
      GIM_Try, /*On fail goto*//*Label 489*/ GIMT_Encode4(41976), // Rule ID 5909 //
        GIM_CheckRegBankForClass, /*MI*/0, /*Op*/0, /*RC*/GIMT_Encode2(AMDGPU::VGPR_32RegClassID),
        GIM_CheckRegBankForClass, /*MI*/0, /*Op*/1, /*RC*/GIMT_Encode2(AMDGPU::VGPR_32RegClassID),
        // (bitconvert:{ *:[i16] } VGPR_32:{ *:[f16] }:$src0)  =>  VGPR_32:{ *:[i16] }:$src0
        GIR_BuildMI, /*InsnID*/0, /*Opcode*/GIMT_Encode2(TargetOpcode::COPY),
        GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/0, // dst
        GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/1, // src0
        GIR_ConstrainOperandRC, /*InsnID*/0, /*Op*/0, GIMT_Encode2(AMDGPU::VGPR_32RegClassID),
        GIR_EraseFromParent, /*InsnID*/0,
        // GIR_Coverage, 5909,
        GIR_Done,
      // Label 489: @41976
      GIM_Try, /*On fail goto*//*Label 490*/ GIMT_Encode4(42011), // Rule ID 5910 //
        GIM_CheckRegBankForClass, /*MI*/0, /*Op*/0, /*RC*/GIMT_Encode2(AMDGPU::VGPR_32RegClassID),
        GIM_CheckRegBankForClass, /*MI*/0, /*Op*/1, /*RC*/GIMT_Encode2(AMDGPU::VGPR_32RegClassID),
        // (bitconvert:{ *:[f16] } VGPR_32:{ *:[i16] }:$src0)  =>  VGPR_32:{ *:[f16] }:$src0
        GIR_BuildMI, /*InsnID*/0, /*Opcode*/GIMT_Encode2(TargetOpcode::COPY),
        GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/0, // dst
        GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/1, // src0
        GIR_ConstrainOperandRC, /*InsnID*/0, /*Op*/0, GIMT_Encode2(AMDGPU::VGPR_32RegClassID),
        GIR_EraseFromParent, /*InsnID*/0,
        // GIR_Coverage, 5910,
        GIR_Done,
      // Label 490: @42011
      GIM_Try, /*On fail goto*//*Label 491*/ GIMT_Encode4(42046), // Rule ID 5911 //
        GIM_CheckRegBankForClass, /*MI*/0, /*Op*/0, /*RC*/GIMT_Encode2(AMDGPU::VGPR_32RegClassID),
        GIM_CheckRegBankForClass, /*MI*/0, /*Op*/1, /*RC*/GIMT_Encode2(AMDGPU::VGPR_32RegClassID),
        // (bitconvert:{ *:[f16] } VGPR_32:{ *:[bf16] }:$src0)  =>  VGPR_32:{ *:[f16] }:$src0
        GIR_BuildMI, /*InsnID*/0, /*Opcode*/GIMT_Encode2(TargetOpcode::COPY),
        GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/0, // dst
        GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/1, // src0
        GIR_ConstrainOperandRC, /*InsnID*/0, /*Op*/0, GIMT_Encode2(AMDGPU::VGPR_32RegClassID),
        GIR_EraseFromParent, /*InsnID*/0,
        // GIR_Coverage, 5911,
        GIR_Done,
      // Label 491: @42046
      GIM_Try, /*On fail goto*//*Label 492*/ GIMT_Encode4(42081), // Rule ID 5912 //
        GIM_CheckRegBankForClass, /*MI*/0, /*Op*/0, /*RC*/GIMT_Encode2(AMDGPU::VGPR_32RegClassID),
        GIM_CheckRegBankForClass, /*MI*/0, /*Op*/1, /*RC*/GIMT_Encode2(AMDGPU::VGPR_32RegClassID),
        // (bitconvert:{ *:[bf16] } VGPR_32:{ *:[f16] }:$src0)  =>  VGPR_32:{ *:[bf16] }:$src0
        GIR_BuildMI, /*InsnID*/0, /*Opcode*/GIMT_Encode2(TargetOpcode::COPY),
        GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/0, // dst
        GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/1, // src0
        GIR_ConstrainOperandRC, /*InsnID*/0, /*Op*/0, GIMT_Encode2(AMDGPU::VGPR_32RegClassID),
        GIR_EraseFromParent, /*InsnID*/0,
        // GIR_Coverage, 5912,
        GIR_Done,
      // Label 492: @42081
      GIM_Try, /*On fail goto*//*Label 493*/ GIMT_Encode4(42116), // Rule ID 5913 //
        GIM_CheckRegBankForClass, /*MI*/0, /*Op*/0, /*RC*/GIMT_Encode2(AMDGPU::SReg_32RegClassID),
        GIM_CheckRegBankForClass, /*MI*/0, /*Op*/1, /*RC*/GIMT_Encode2(AMDGPU::SReg_32RegClassID),
        // (bitconvert:{ *:[i16] } SReg_32:{ *:[f16] }:$src0)  =>  SReg_32:{ *:[i16] }:$src0
        GIR_BuildMI, /*InsnID*/0, /*Opcode*/GIMT_Encode2(TargetOpcode::COPY),
        GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/0, // dst
        GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/1, // src0
        GIR_ConstrainOperandRC, /*InsnID*/0, /*Op*/0, GIMT_Encode2(AMDGPU::SReg_32RegClassID),
        GIR_EraseFromParent, /*InsnID*/0,
        // GIR_Coverage, 5913,
        GIR_Done,
      // Label 493: @42116
      GIM_Try, /*On fail goto*//*Label 494*/ GIMT_Encode4(42151), // Rule ID 5914 //
        GIM_CheckRegBankForClass, /*MI*/0, /*Op*/0, /*RC*/GIMT_Encode2(AMDGPU::SReg_32RegClassID),
        GIM_CheckRegBankForClass, /*MI*/0, /*Op*/1, /*RC*/GIMT_Encode2(AMDGPU::SReg_32RegClassID),
        // (bitconvert:{ *:[f16] } SReg_32:{ *:[i16] }:$src0)  =>  SReg_32:{ *:[f16] }:$src0
        GIR_BuildMI, /*InsnID*/0, /*Opcode*/GIMT_Encode2(TargetOpcode::COPY),
        GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/0, // dst
        GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/1, // src0
        GIR_ConstrainOperandRC, /*InsnID*/0, /*Op*/0, GIMT_Encode2(AMDGPU::SReg_32RegClassID),
        GIR_EraseFromParent, /*InsnID*/0,
        // GIR_Coverage, 5914,
        GIR_Done,
      // Label 494: @42151
      GIM_Try, /*On fail goto*//*Label 495*/ GIMT_Encode4(42186), // Rule ID 5915 //
        GIM_CheckRegBankForClass, /*MI*/0, /*Op*/0, /*RC*/GIMT_Encode2(AMDGPU::SReg_32RegClassID),
        GIM_CheckRegBankForClass, /*MI*/0, /*Op*/1, /*RC*/GIMT_Encode2(AMDGPU::SReg_32RegClassID),
        // (bitconvert:{ *:[f16] } SReg_32:{ *:[bf16] }:$src0)  =>  SReg_32:{ *:[f16] }:$src0
        GIR_BuildMI, /*InsnID*/0, /*Opcode*/GIMT_Encode2(TargetOpcode::COPY),
        GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/0, // dst
        GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/1, // src0
        GIR_ConstrainOperandRC, /*InsnID*/0, /*Op*/0, GIMT_Encode2(AMDGPU::SReg_32RegClassID),
        GIR_EraseFromParent, /*InsnID*/0,
        // GIR_Coverage, 5915,
        GIR_Done,
      // Label 495: @42186
      GIM_Try, /*On fail goto*//*Label 496*/ GIMT_Encode4(42221), // Rule ID 5916 //
        GIM_CheckRegBankForClass, /*MI*/0, /*Op*/0, /*RC*/GIMT_Encode2(AMDGPU::SReg_32RegClassID),
        GIM_CheckRegBankForClass, /*MI*/0, /*Op*/1, /*RC*/GIMT_Encode2(AMDGPU::SReg_32RegClassID),
        // (bitconvert:{ *:[bf16] } SReg_32:{ *:[f16] }:$src0)  =>  SReg_32:{ *:[bf16] }:$src0
        GIR_BuildMI, /*InsnID*/0, /*Opcode*/GIMT_Encode2(TargetOpcode::COPY),
        GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/0, // dst
        GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/1, // src0
        GIR_ConstrainOperandRC, /*InsnID*/0, /*Op*/0, GIMT_Encode2(AMDGPU::SReg_32RegClassID),
        GIR_EraseFromParent, /*InsnID*/0,
        // GIR_Coverage, 5916,
        GIR_Done,
      // Label 496: @42221
      GIM_Try, /*On fail goto*//*Label 497*/ GIMT_Encode4(42256), // Rule ID 5917 //
        GIM_CheckRegBankForClass, /*MI*/0, /*Op*/0, /*RC*/GIMT_Encode2(AMDGPU::VGPR_32RegClassID),
        GIM_CheckRegBankForClass, /*MI*/0, /*Op*/1, /*RC*/GIMT_Encode2(AMDGPU::VGPR_32RegClassID),
        // (bitconvert:{ *:[i16] } VGPR_32:{ *:[bf16] }:$src0)  =>  VGPR_32:{ *:[i16] }:$src0
        GIR_BuildMI, /*InsnID*/0, /*Opcode*/GIMT_Encode2(TargetOpcode::COPY),
        GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/0, // dst
        GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/1, // src0
        GIR_ConstrainOperandRC, /*InsnID*/0, /*Op*/0, GIMT_Encode2(AMDGPU::VGPR_32RegClassID),
        GIR_EraseFromParent, /*InsnID*/0,
        // GIR_Coverage, 5917,
        GIR_Done,
      // Label 497: @42256
      GIM_Try, /*On fail goto*//*Label 498*/ GIMT_Encode4(42291), // Rule ID 5918 //
        GIM_CheckRegBankForClass, /*MI*/0, /*Op*/0, /*RC*/GIMT_Encode2(AMDGPU::VGPR_32RegClassID),
        GIM_CheckRegBankForClass, /*MI*/0, /*Op*/1, /*RC*/GIMT_Encode2(AMDGPU::VGPR_32RegClassID),
        // (bitconvert:{ *:[bf16] } VGPR_32:{ *:[i16] }:$src0)  =>  VGPR_32:{ *:[bf16] }:$src0
        GIR_BuildMI, /*InsnID*/0, /*Opcode*/GIMT_Encode2(TargetOpcode::COPY),
        GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/0, // dst
        GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/1, // src0
        GIR_ConstrainOperandRC, /*InsnID*/0, /*Op*/0, GIMT_Encode2(AMDGPU::VGPR_32RegClassID),
        GIR_EraseFromParent, /*InsnID*/0,
        // GIR_Coverage, 5918,
        GIR_Done,
      // Label 498: @42291
      GIM_Try, /*On fail goto*//*Label 499*/ GIMT_Encode4(42326), // Rule ID 5919 //
        GIM_CheckRegBankForClass, /*MI*/0, /*Op*/0, /*RC*/GIMT_Encode2(AMDGPU::SReg_32RegClassID),
        GIM_CheckRegBankForClass, /*MI*/0, /*Op*/1, /*RC*/GIMT_Encode2(AMDGPU::SReg_32RegClassID),
        // (bitconvert:{ *:[i16] } SReg_32:{ *:[bf16] }:$src0)  =>  SReg_32:{ *:[i16] }:$src0
        GIR_BuildMI, /*InsnID*/0, /*Opcode*/GIMT_Encode2(TargetOpcode::COPY),
        GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/0, // dst
        GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/1, // src0
        GIR_ConstrainOperandRC, /*InsnID*/0, /*Op*/0, GIMT_Encode2(AMDGPU::SReg_32RegClassID),
        GIR_EraseFromParent, /*InsnID*/0,
        // GIR_Coverage, 5919,
        GIR_Done,
      // Label 499: @42326
      GIM_Try, /*On fail goto*//*Label 500*/ GIMT_Encode4(42361), // Rule ID 5920 //
        GIM_CheckRegBankForClass, /*MI*/0, /*Op*/0, /*RC*/GIMT_Encode2(AMDGPU::SReg_32RegClassID),
        GIM_CheckRegBankForClass, /*MI*/0, /*Op*/1, /*RC*/GIMT_Encode2(AMDGPU::SReg_32RegClassID),
        // (bitconvert:{ *:[bf16] } SReg_32:{ *:[i16] }:$src0)  =>  SReg_32:{ *:[bf16] }:$src0
        GIR_BuildMI, /*InsnID*/0, /*Opcode*/GIMT_Encode2(TargetOpcode::COPY),
        GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/0, // dst
        GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/1, // src0
        GIR_ConstrainOperandRC, /*InsnID*/0, /*Op*/0, GIMT_Encode2(AMDGPU::SReg_32RegClassID),
        GIR_EraseFromParent, /*InsnID*/0,
        // GIR_Coverage, 5920,
        GIR_Done,
      // Label 500: @42361
      GIM_Reject,
    // Label 488: @42362
    GIM_Reject,
    // Label 462: @42363
    GIM_Try, /*On fail goto*//*Label 501*/ GIMT_Encode4(42402), // Rule ID 5921 //
      GIM_CheckType, /*MI*/0, /*Op*/1, /*Type*/GILLT_s32,
      GIM_CheckRegBankForClass, /*MI*/0, /*Op*/0, /*RC*/GIMT_Encode2(AMDGPU::VGPR_32RegClassID),
      GIM_CheckRegBankForClass, /*MI*/0, /*Op*/1, /*RC*/GIMT_Encode2(AMDGPU::VGPR_32RegClassID),
      // (bitconvert:{ *:[i32] } VGPR_32:{ *:[f32] }:$src0)  =>  VGPR_32:{ *:[i32] }:$src0
      GIR_BuildMI, /*InsnID*/0, /*Opcode*/GIMT_Encode2(TargetOpcode::COPY),
      GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/0, // dst
      GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/1, // src0
      GIR_ConstrainOperandRC, /*InsnID*/0, /*Op*/0, GIMT_Encode2(AMDGPU::VGPR_32RegClassID),
      GIR_EraseFromParent, /*InsnID*/0,
      // GIR_Coverage, 5921,
      GIR_Done,
    // Label 501: @42402
    GIM_Try, /*On fail goto*//*Label 502*/ GIMT_Encode4(42441), // Rule ID 5922 //
      GIM_CheckType, /*MI*/0, /*Op*/1, /*Type*/GILLT_s32,
      GIM_CheckRegBankForClass, /*MI*/0, /*Op*/0, /*RC*/GIMT_Encode2(AMDGPU::VGPR_32RegClassID),
      GIM_CheckRegBankForClass, /*MI*/0, /*Op*/1, /*RC*/GIMT_Encode2(AMDGPU::VGPR_32RegClassID),
      // (bitconvert:{ *:[f32] } VGPR_32:{ *:[i32] }:$src0)  =>  VGPR_32:{ *:[f32] }:$src0
      GIR_BuildMI, /*InsnID*/0, /*Opcode*/GIMT_Encode2(TargetOpcode::COPY),
      GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/0, // dst
      GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/1, // src0
      GIR_ConstrainOperandRC, /*InsnID*/0, /*Op*/0, GIMT_Encode2(AMDGPU::VGPR_32RegClassID),
      GIR_EraseFromParent, /*InsnID*/0,
      // GIR_Coverage, 5922,
      GIR_Done,
    // Label 502: @42441
    GIM_Try, /*On fail goto*//*Label 503*/ GIMT_Encode4(42480), // Rule ID 5923 //
      GIM_CheckType, /*MI*/0, /*Op*/1, /*Type*/GILLT_s32,
      GIM_CheckRegBankForClass, /*MI*/0, /*Op*/0, /*RC*/GIMT_Encode2(AMDGPU::SReg_32RegClassID),
      GIM_CheckRegBankForClass, /*MI*/0, /*Op*/1, /*RC*/GIMT_Encode2(AMDGPU::SReg_32RegClassID),
      // (bitconvert:{ *:[i32] } SReg_32:{ *:[f32] }:$src0)  =>  SReg_32:{ *:[i32] }:$src0
      GIR_BuildMI, /*InsnID*/0, /*Opcode*/GIMT_Encode2(TargetOpcode::COPY),
      GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/0, // dst
      GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/1, // src0
      GIR_ConstrainOperandRC, /*InsnID*/0, /*Op*/0, GIMT_Encode2(AMDGPU::SReg_32RegClassID),
      GIR_EraseFromParent, /*InsnID*/0,
      // GIR_Coverage, 5923,
      GIR_Done,
    // Label 503: @42480
    GIM_Try, /*On fail goto*//*Label 504*/ GIMT_Encode4(42519), // Rule ID 5924 //
      GIM_CheckType, /*MI*/0, /*Op*/1, /*Type*/GILLT_s32,
      GIM_CheckRegBankForClass, /*MI*/0, /*Op*/0, /*RC*/GIMT_Encode2(AMDGPU::SReg_32RegClassID),
      GIM_CheckRegBankForClass, /*MI*/0, /*Op*/1, /*RC*/GIMT_Encode2(AMDGPU::SReg_32RegClassID),
      // (bitconvert:{ *:[f32] } SReg_32:{ *:[i32] }:$src0)  =>  SReg_32:{ *:[f32] }:$src0
      GIR_BuildMI, /*InsnID*/0, /*Opcode*/GIMT_Encode2(TargetOpcode::COPY),
      GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/0, // dst
      GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/1, // src0
      GIR_ConstrainOperandRC, /*InsnID*/0, /*Op*/0, GIMT_Encode2(AMDGPU::SReg_32RegClassID),
      GIR_EraseFromParent, /*InsnID*/0,
      // GIR_Coverage, 5924,
      GIR_Done,
    // Label 504: @42519
    GIM_Try, /*On fail goto*//*Label 505*/ GIMT_Encode4(42558), // Rule ID 5926 //
      GIM_CheckType, /*MI*/0, /*Op*/1, /*Type*/GILLT_v2s16,
      GIM_CheckRegBankForClass, /*MI*/0, /*Op*/0, /*RC*/GIMT_Encode2(AMDGPU::SReg_32RegClassID),
      GIM_CheckRegBankForClass, /*MI*/0, /*Op*/1, /*RC*/GIMT_Encode2(AMDGPU::SReg_32RegClassID),
      // (bitconvert:{ *:[i32] } SReg_32:{ *:[v2i16] }:$src0)  =>  SReg_32:{ *:[i32] }:$src0
      GIR_BuildMI, /*InsnID*/0, /*Opcode*/GIMT_Encode2(TargetOpcode::COPY),
      GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/0, // dst
      GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/1, // src0
      GIR_ConstrainOperandRC, /*InsnID*/0, /*Op*/0, GIMT_Encode2(AMDGPU::SReg_32RegClassID),
      GIR_EraseFromParent, /*InsnID*/0,
      // GIR_Coverage, 5926,
      GIR_Done,
    // Label 505: @42558
    GIM_Try, /*On fail goto*//*Label 506*/ GIMT_Encode4(42597), // Rule ID 5928 //
      GIM_CheckType, /*MI*/0, /*Op*/1, /*Type*/GILLT_v2s16,
      GIM_CheckRegBankForClass, /*MI*/0, /*Op*/0, /*RC*/GIMT_Encode2(AMDGPU::SReg_32RegClassID),
      GIM_CheckRegBankForClass, /*MI*/0, /*Op*/1, /*RC*/GIMT_Encode2(AMDGPU::SReg_32RegClassID),
      // (bitconvert:{ *:[i32] } SReg_32:{ *:[v2f16] }:$src0)  =>  SReg_32:{ *:[i32] }:$src0
      GIR_BuildMI, /*InsnID*/0, /*Opcode*/GIMT_Encode2(TargetOpcode::COPY),
      GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/0, // dst
      GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/1, // src0
      GIR_ConstrainOperandRC, /*InsnID*/0, /*Op*/0, GIMT_Encode2(AMDGPU::SReg_32RegClassID),
      GIR_EraseFromParent, /*InsnID*/0,
      // GIR_Coverage, 5928,
      GIR_Done,
    // Label 506: @42597
    GIM_Try, /*On fail goto*//*Label 507*/ GIMT_Encode4(42636), // Rule ID 5932 //
      GIM_CheckType, /*MI*/0, /*Op*/1, /*Type*/GILLT_v2s16,
      GIM_CheckRegBankForClass, /*MI*/0, /*Op*/0, /*RC*/GIMT_Encode2(AMDGPU::SReg_32RegClassID),
      GIM_CheckRegBankForClass, /*MI*/0, /*Op*/1, /*RC*/GIMT_Encode2(AMDGPU::SReg_32RegClassID),
      // (bitconvert:{ *:[f32] } SReg_32:{ *:[v2f16] }:$src0)  =>  SReg_32:{ *:[f32] }:$src0
      GIR_BuildMI, /*InsnID*/0, /*Opcode*/GIMT_Encode2(TargetOpcode::COPY),
      GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/0, // dst
      GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/1, // src0
      GIR_ConstrainOperandRC, /*InsnID*/0, /*Op*/0, GIMT_Encode2(AMDGPU::SReg_32RegClassID),
      GIR_EraseFromParent, /*InsnID*/0,
      // GIR_Coverage, 5932,
      GIR_Done,
    // Label 507: @42636
    GIM_Try, /*On fail goto*//*Label 508*/ GIMT_Encode4(42675), // Rule ID 5934 //
      GIM_CheckType, /*MI*/0, /*Op*/1, /*Type*/GILLT_v2s16,
      GIM_CheckRegBankForClass, /*MI*/0, /*Op*/0, /*RC*/GIMT_Encode2(AMDGPU::SReg_32RegClassID),
      GIM_CheckRegBankForClass, /*MI*/0, /*Op*/1, /*RC*/GIMT_Encode2(AMDGPU::SReg_32RegClassID),
      // (bitconvert:{ *:[f32] } SReg_32:{ *:[v2i16] }:$src0)  =>  SReg_32:{ *:[f32] }:$src0
      GIR_BuildMI, /*InsnID*/0, /*Opcode*/GIMT_Encode2(TargetOpcode::COPY),
      GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/0, // dst
      GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/1, // src0
      GIR_ConstrainOperandRC, /*InsnID*/0, /*Op*/0, GIMT_Encode2(AMDGPU::SReg_32RegClassID),
      GIR_EraseFromParent, /*InsnID*/0,
      // GIR_Coverage, 5934,
      GIR_Done,
    // Label 508: @42675
    GIM_Try, /*On fail goto*//*Label 509*/ GIMT_Encode4(42714), // Rule ID 5936 //
      GIM_CheckType, /*MI*/0, /*Op*/1, /*Type*/GILLT_v2s16,
      GIM_CheckRegBankForClass, /*MI*/0, /*Op*/0, /*RC*/GIMT_Encode2(AMDGPU::SReg_32RegClassID),
      GIM_CheckRegBankForClass, /*MI*/0, /*Op*/1, /*RC*/GIMT_Encode2(AMDGPU::SReg_32RegClassID),
      // (bitconvert:{ *:[i32] } SReg_32:{ *:[v2bf16] }:$src0)  =>  SReg_32:{ *:[i32] }:$src0
      GIR_BuildMI, /*InsnID*/0, /*Opcode*/GIMT_Encode2(TargetOpcode::COPY),
      GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/0, // dst
      GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/1, // src0
      GIR_ConstrainOperandRC, /*InsnID*/0, /*Op*/0, GIMT_Encode2(AMDGPU::SReg_32RegClassID),
      GIR_EraseFromParent, /*InsnID*/0,
      // GIR_Coverage, 5936,
      GIR_Done,
    // Label 509: @42714
    GIM_Try, /*On fail goto*//*Label 510*/ GIMT_Encode4(42753), // Rule ID 5938 //
      GIM_CheckType, /*MI*/0, /*Op*/1, /*Type*/GILLT_v2s16,
      GIM_CheckRegBankForClass, /*MI*/0, /*Op*/0, /*RC*/GIMT_Encode2(AMDGPU::VGPR_32RegClassID),
      GIM_CheckRegBankForClass, /*MI*/0, /*Op*/1, /*RC*/GIMT_Encode2(AMDGPU::VGPR_32RegClassID),
      // (bitconvert:{ *:[i32] } VGPR_32:{ *:[v2bf16] }:$src0)  =>  VGPR_32:{ *:[i32] }:$src0
      GIR_BuildMI, /*InsnID*/0, /*Opcode*/GIMT_Encode2(TargetOpcode::COPY),
      GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/0, // dst
      GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/1, // src0
      GIR_ConstrainOperandRC, /*InsnID*/0, /*Op*/0, GIMT_Encode2(AMDGPU::VGPR_32RegClassID),
      GIR_EraseFromParent, /*InsnID*/0,
      // GIR_Coverage, 5938,
      GIR_Done,
    // Label 510: @42753
    GIM_Try, /*On fail goto*//*Label 511*/ GIMT_Encode4(42792), // Rule ID 5947 //
      GIM_CheckType, /*MI*/0, /*Op*/1, /*Type*/GILLT_v2s16,
      GIM_CheckRegBankForClass, /*MI*/0, /*Op*/0, /*RC*/GIMT_Encode2(AMDGPU::VGPR_32RegClassID),
      GIM_CheckRegBankForClass, /*MI*/0, /*Op*/1, /*RC*/GIMT_Encode2(AMDGPU::VGPR_32RegClassID),
      // (bitconvert:{ *:[f32] } VGPR_32:{ *:[v2bf16] }:$src0)  =>  VGPR_32:{ *:[f32] }:$src0
      GIR_BuildMI, /*InsnID*/0, /*Opcode*/GIMT_Encode2(TargetOpcode::COPY),
      GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/0, // dst
      GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/1, // src0
      GIR_ConstrainOperandRC, /*InsnID*/0, /*Op*/0, GIMT_Encode2(AMDGPU::VGPR_32RegClassID),
      GIR_EraseFromParent, /*InsnID*/0,
      // GIR_Coverage, 5947,
      GIR_Done,
    // Label 511: @42792
    GIM_Try, /*On fail goto*//*Label 512*/ GIMT_Encode4(42831), // Rule ID 5949 //
      GIM_CheckType, /*MI*/0, /*Op*/1, /*Type*/GILLT_v2s16,
      GIM_CheckRegBankForClass, /*MI*/0, /*Op*/0, /*RC*/GIMT_Encode2(AMDGPU::SReg_32RegClassID),
      GIM_CheckRegBankForClass, /*MI*/0, /*Op*/1, /*RC*/GIMT_Encode2(AMDGPU::SReg_32RegClassID),
      // (bitconvert:{ *:[f32] } SReg_32:{ *:[v2bf16] }:$src0)  =>  SReg_32:{ *:[f32] }:$src0
      GIR_BuildMI, /*InsnID*/0, /*Opcode*/GIMT_Encode2(TargetOpcode::COPY),
      GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/0, // dst
      GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/1, // src0
      GIR_ConstrainOperandRC, /*InsnID*/0, /*Op*/0, GIMT_Encode2(AMDGPU::SReg_32RegClassID),
      GIR_EraseFromParent, /*InsnID*/0,
      // GIR_Coverage, 5949,
      GIR_Done,
    // Label 512: @42831
    GIM_Reject,
    // Label 463: @42832
    GIM_Try, /*On fail goto*//*Label 513*/ GIMT_Encode4(42871), // Rule ID 5951 //
      GIM_CheckType, /*MI*/0, /*Op*/1, /*Type*/GILLT_s64,
      GIM_CheckRegBankForClass, /*MI*/0, /*Op*/0, /*RC*/GIMT_Encode2(AMDGPU::VReg_64RegClassID),
      GIM_CheckRegBankForClass, /*MI*/0, /*Op*/1, /*RC*/GIMT_Encode2(AMDGPU::VReg_64RegClassID),
      // (bitconvert:{ *:[i64] } VReg_64:{ *:[f64] }:$src0)  =>  VReg_64:{ *:[i64] }:$src0
      GIR_BuildMI, /*InsnID*/0, /*Opcode*/GIMT_Encode2(TargetOpcode::COPY),
      GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/0, // dst
      GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/1, // src0
      GIR_ConstrainOperandRC, /*InsnID*/0, /*Op*/0, GIMT_Encode2(AMDGPU::VReg_64RegClassID),
      GIR_EraseFromParent, /*InsnID*/0,
      // GIR_Coverage, 5951,
      GIR_Done,
    // Label 513: @42871
    GIM_Try, /*On fail goto*//*Label 514*/ GIMT_Encode4(42910), // Rule ID 5952 //
      GIM_CheckType, /*MI*/0, /*Op*/1, /*Type*/GILLT_s64,
      GIM_CheckRegBankForClass, /*MI*/0, /*Op*/0, /*RC*/GIMT_Encode2(AMDGPU::VReg_64RegClassID),
      GIM_CheckRegBankForClass, /*MI*/0, /*Op*/1, /*RC*/GIMT_Encode2(AMDGPU::VReg_64RegClassID),
      // (bitconvert:{ *:[f64] } VReg_64:{ *:[i64] }:$src0)  =>  VReg_64:{ *:[f64] }:$src0
      GIR_BuildMI, /*InsnID*/0, /*Opcode*/GIMT_Encode2(TargetOpcode::COPY),
      GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/0, // dst
      GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/1, // src0
      GIR_ConstrainOperandRC, /*InsnID*/0, /*Op*/0, GIMT_Encode2(AMDGPU::VReg_64RegClassID),
      GIR_EraseFromParent, /*InsnID*/0,
      // GIR_Coverage, 5952,
      GIR_Done,
    // Label 514: @42910
    GIM_Try, /*On fail goto*//*Label 515*/ GIMT_Encode4(42949), // Rule ID 5955 //
      GIM_CheckType, /*MI*/0, /*Op*/1, /*Type*/GILLT_v2s32,
      GIM_CheckRegBankForClass, /*MI*/0, /*Op*/0, /*RC*/GIMT_Encode2(AMDGPU::VReg_64RegClassID),
      GIM_CheckRegBankForClass, /*MI*/0, /*Op*/1, /*RC*/GIMT_Encode2(AMDGPU::VReg_64RegClassID),
      // (bitconvert:{ *:[i64] } VReg_64:{ *:[v2i32] }:$src0)  =>  VReg_64:{ *:[i64] }:$src0
      GIR_BuildMI, /*InsnID*/0, /*Opcode*/GIMT_Encode2(TargetOpcode::COPY),
      GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/0, // dst
      GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/1, // src0
      GIR_ConstrainOperandRC, /*InsnID*/0, /*Op*/0, GIMT_Encode2(AMDGPU::VReg_64RegClassID),
      GIR_EraseFromParent, /*InsnID*/0,
      // GIR_Coverage, 5955,
      GIR_Done,
    // Label 515: @42949
    GIM_Try, /*On fail goto*//*Label 516*/ GIMT_Encode4(42988), // Rule ID 5957 //
      GIM_CheckType, /*MI*/0, /*Op*/1, /*Type*/GILLT_v2s32,
      GIM_CheckRegBankForClass, /*MI*/0, /*Op*/0, /*RC*/GIMT_Encode2(AMDGPU::VReg_64RegClassID),
      GIM_CheckRegBankForClass, /*MI*/0, /*Op*/1, /*RC*/GIMT_Encode2(AMDGPU::VReg_64RegClassID),
      // (bitconvert:{ *:[i64] } VReg_64:{ *:[v2f32] }:$src0)  =>  VReg_64:{ *:[i64] }:$src0
      GIR_BuildMI, /*InsnID*/0, /*Opcode*/GIMT_Encode2(TargetOpcode::COPY),
      GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/0, // dst
      GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/1, // src0
      GIR_ConstrainOperandRC, /*InsnID*/0, /*Op*/0, GIMT_Encode2(AMDGPU::VReg_64RegClassID),
      GIR_EraseFromParent, /*InsnID*/0,
      // GIR_Coverage, 5957,
      GIR_Done,
    // Label 516: @42988
    GIM_Try, /*On fail goto*//*Label 517*/ GIMT_Encode4(43027), // Rule ID 5959 //
      GIM_CheckType, /*MI*/0, /*Op*/1, /*Type*/GILLT_v2s32,
      GIM_CheckRegBankForClass, /*MI*/0, /*Op*/0, /*RC*/GIMT_Encode2(AMDGPU::VReg_64RegClassID),
      GIM_CheckRegBankForClass, /*MI*/0, /*Op*/1, /*RC*/GIMT_Encode2(AMDGPU::VReg_64RegClassID),
      // (bitconvert:{ *:[f64] } VReg_64:{ *:[v2f32] }:$src0)  =>  VReg_64:{ *:[f64] }:$src0
      GIR_BuildMI, /*InsnID*/0, /*Opcode*/GIMT_Encode2(TargetOpcode::COPY),
      GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/0, // dst
      GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/1, // src0
      GIR_ConstrainOperandRC, /*InsnID*/0, /*Op*/0, GIMT_Encode2(AMDGPU::VReg_64RegClassID),
      GIR_EraseFromParent, /*InsnID*/0,
      // GIR_Coverage, 5959,
      GIR_Done,
    // Label 517: @43027
    GIM_Try, /*On fail goto*//*Label 518*/ GIMT_Encode4(43066), // Rule ID 5961 //
      GIM_CheckType, /*MI*/0, /*Op*/1, /*Type*/GILLT_v2s32,
      GIM_CheckRegBankForClass, /*MI*/0, /*Op*/0, /*RC*/GIMT_Encode2(AMDGPU::VReg_64RegClassID),
      GIM_CheckRegBankForClass, /*MI*/0, /*Op*/1, /*RC*/GIMT_Encode2(AMDGPU::VReg_64RegClassID),
      // (bitconvert:{ *:[f64] } VReg_64:{ *:[v2i32] }:$src0)  =>  VReg_64:{ *:[f64] }:$src0
      GIR_BuildMI, /*InsnID*/0, /*Opcode*/GIMT_Encode2(TargetOpcode::COPY),
      GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/0, // dst
      GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/1, // src0
      GIR_ConstrainOperandRC, /*InsnID*/0, /*Op*/0, GIMT_Encode2(AMDGPU::VReg_64RegClassID),
      GIR_EraseFromParent, /*InsnID*/0,
      // GIR_Coverage, 5961,
      GIR_Done,
    // Label 518: @43066
    GIM_Try, /*On fail goto*//*Label 519*/ GIMT_Encode4(43105), // Rule ID 5968 //
      GIM_CheckType, /*MI*/0, /*Op*/1, /*Type*/GILLT_v4s16,
      GIM_CheckRegBankForClass, /*MI*/0, /*Op*/0, /*RC*/GIMT_Encode2(AMDGPU::VReg_64RegClassID),
      GIM_CheckRegBankForClass, /*MI*/0, /*Op*/1, /*RC*/GIMT_Encode2(AMDGPU::VReg_64RegClassID),
      // (bitconvert:{ *:[i64] } VReg_64:{ *:[v4bf16] }:$src0)  =>  VReg_64:{ *:[i64] }:$src0
      GIR_BuildMI, /*InsnID*/0, /*Opcode*/GIMT_Encode2(TargetOpcode::COPY),
      GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/0, // dst
      GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/1, // src0
      GIR_ConstrainOperandRC, /*InsnID*/0, /*Op*/0, GIMT_Encode2(AMDGPU::VReg_64RegClassID),
      GIR_EraseFromParent, /*InsnID*/0,
      // GIR_Coverage, 5968,
      GIR_Done,
    // Label 519: @43105
    GIM_Try, /*On fail goto*//*Label 520*/ GIMT_Encode4(43144), // Rule ID 5976 //
      GIM_CheckType, /*MI*/0, /*Op*/1, /*Type*/GILLT_v4s16,
      GIM_CheckRegBankForClass, /*MI*/0, /*Op*/0, /*RC*/GIMT_Encode2(AMDGPU::VReg_64RegClassID),
      GIM_CheckRegBankForClass, /*MI*/0, /*Op*/1, /*RC*/GIMT_Encode2(AMDGPU::VReg_64RegClassID),
      // (bitconvert:{ *:[f64] } VReg_64:{ *:[v4bf16] }:$src0)  =>  VReg_64:{ *:[f64] }:$src0
      GIR_BuildMI, /*InsnID*/0, /*Opcode*/GIMT_Encode2(TargetOpcode::COPY),
      GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/0, // dst
      GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/1, // src0
      GIR_ConstrainOperandRC, /*InsnID*/0, /*Op*/0, GIMT_Encode2(AMDGPU::VReg_64RegClassID),
      GIR_EraseFromParent, /*InsnID*/0,
      // GIR_Coverage, 5976,
      GIR_Done,
    // Label 520: @43144
    GIM_Try, /*On fail goto*//*Label 521*/ GIMT_Encode4(43183), // Rule ID 5988 //
      GIM_CheckType, /*MI*/0, /*Op*/1, /*Type*/GILLT_v4s16,
      GIM_CheckRegBankForClass, /*MI*/0, /*Op*/0, /*RC*/GIMT_Encode2(AMDGPU::VReg_64RegClassID),
      GIM_CheckRegBankForClass, /*MI*/0, /*Op*/1, /*RC*/GIMT_Encode2(AMDGPU::VReg_64RegClassID),
      // (bitconvert:{ *:[f64] } VReg_64:{ *:[v4i16] }:$src0)  =>  VReg_64:{ *:[f64] }:$src0
      GIR_BuildMI, /*InsnID*/0, /*Opcode*/GIMT_Encode2(TargetOpcode::COPY),
      GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/0, // dst
      GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/1, // src0
      GIR_ConstrainOperandRC, /*InsnID*/0, /*Op*/0, GIMT_Encode2(AMDGPU::VReg_64RegClassID),
      GIR_EraseFromParent, /*InsnID*/0,
      // GIR_Coverage, 5988,
      GIR_Done,
    // Label 521: @43183
    GIM_Try, /*On fail goto*//*Label 522*/ GIMT_Encode4(43222), // Rule ID 5989 //
      GIM_CheckType, /*MI*/0, /*Op*/1, /*Type*/GILLT_v4s16,
      GIM_CheckRegBankForClass, /*MI*/0, /*Op*/0, /*RC*/GIMT_Encode2(AMDGPU::VReg_64RegClassID),
      GIM_CheckRegBankForClass, /*MI*/0, /*Op*/1, /*RC*/GIMT_Encode2(AMDGPU::VReg_64RegClassID),
      // (bitconvert:{ *:[f64] } VReg_64:{ *:[v4f16] }:$src0)  =>  VReg_64:{ *:[f64] }:$src0
      GIR_BuildMI, /*InsnID*/0, /*Opcode*/GIMT_Encode2(TargetOpcode::COPY),
      GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/0, // dst
      GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/1, // src0
      GIR_ConstrainOperandRC, /*InsnID*/0, /*Op*/0, GIMT_Encode2(AMDGPU::VReg_64RegClassID),
      GIR_EraseFromParent, /*InsnID*/0,
      // GIR_Coverage, 5989,
      GIR_Done,
    // Label 522: @43222
    GIM_Try, /*On fail goto*//*Label 523*/ GIMT_Encode4(43261), // Rule ID 5992 //
      GIM_CheckType, /*MI*/0, /*Op*/1, /*Type*/GILLT_v4s16,
      GIM_CheckRegBankForClass, /*MI*/0, /*Op*/0, /*RC*/GIMT_Encode2(AMDGPU::VReg_64RegClassID),
      GIM_CheckRegBankForClass, /*MI*/0, /*Op*/1, /*RC*/GIMT_Encode2(AMDGPU::VReg_64RegClassID),
      // (bitconvert:{ *:[i64] } VReg_64:{ *:[v4i16] }:$src0)  =>  VReg_64:{ *:[i64] }:$src0
      GIR_BuildMI, /*InsnID*/0, /*Opcode*/GIMT_Encode2(TargetOpcode::COPY),
      GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/0, // dst
      GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/1, // src0
      GIR_ConstrainOperandRC, /*InsnID*/0, /*Op*/0, GIMT_Encode2(AMDGPU::VReg_64RegClassID),
      GIR_EraseFromParent, /*InsnID*/0,
      // GIR_Coverage, 5992,
      GIR_Done,
    // Label 523: @43261
    GIM_Try, /*On fail goto*//*Label 524*/ GIMT_Encode4(43300), // Rule ID 5993 //
      GIM_CheckType, /*MI*/0, /*Op*/1, /*Type*/GILLT_v4s16,
      GIM_CheckRegBankForClass, /*MI*/0, /*Op*/0, /*RC*/GIMT_Encode2(AMDGPU::VReg_64RegClassID),
      GIM_CheckRegBankForClass, /*MI*/0, /*Op*/1, /*RC*/GIMT_Encode2(AMDGPU::VReg_64RegClassID),
      // (bitconvert:{ *:[i64] } VReg_64:{ *:[v4f16] }:$src0)  =>  VReg_64:{ *:[i64] }:$src0
      GIR_BuildMI, /*InsnID*/0, /*Opcode*/GIMT_Encode2(TargetOpcode::COPY),
      GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/0, // dst
      GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/1, // src0
      GIR_ConstrainOperandRC, /*InsnID*/0, /*Op*/0, GIMT_Encode2(AMDGPU::VReg_64RegClassID),
      GIR_EraseFromParent, /*InsnID*/0,
      // GIR_Coverage, 5993,
      GIR_Done,
    // Label 524: @43300
    GIM_Reject,
    // Label 464: @43301
    GIM_Try, /*On fail goto*//*Label 525*/ GIMT_Encode4(43340), // Rule ID 5925 //
      GIM_CheckType, /*MI*/0, /*Op*/1, /*Type*/GILLT_s32,
      GIM_CheckRegBankForClass, /*MI*/0, /*Op*/0, /*RC*/GIMT_Encode2(AMDGPU::SReg_32RegClassID),
      GIM_CheckRegBankForClass, /*MI*/0, /*Op*/1, /*RC*/GIMT_Encode2(AMDGPU::SReg_32RegClassID),
      // (bitconvert:{ *:[v2i16] } SReg_32:{ *:[i32] }:$src0)  =>  SReg_32:{ *:[v2i16] }:$src0
      GIR_BuildMI, /*InsnID*/0, /*Opcode*/GIMT_Encode2(TargetOpcode::COPY),
      GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/0, // dst
      GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/1, // src0
      GIR_ConstrainOperandRC, /*InsnID*/0, /*Op*/0, GIMT_Encode2(AMDGPU::SReg_32RegClassID),
      GIR_EraseFromParent, /*InsnID*/0,
      // GIR_Coverage, 5925,
      GIR_Done,
    // Label 525: @43340
    GIM_Try, /*On fail goto*//*Label 526*/ GIMT_Encode4(43379), // Rule ID 5927 //
      GIM_CheckType, /*MI*/0, /*Op*/1, /*Type*/GILLT_s32,
      GIM_CheckRegBankForClass, /*MI*/0, /*Op*/0, /*RC*/GIMT_Encode2(AMDGPU::SReg_32RegClassID),
      GIM_CheckRegBankForClass, /*MI*/0, /*Op*/1, /*RC*/GIMT_Encode2(AMDGPU::SReg_32RegClassID),
      // (bitconvert:{ *:[v2f16] } SReg_32:{ *:[i32] }:$src0)  =>  SReg_32:{ *:[v2f16] }:$src0
      GIR_BuildMI, /*InsnID*/0, /*Opcode*/GIMT_Encode2(TargetOpcode::COPY),
      GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/0, // dst
      GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/1, // src0
      GIR_ConstrainOperandRC, /*InsnID*/0, /*Op*/0, GIMT_Encode2(AMDGPU::SReg_32RegClassID),
      GIR_EraseFromParent, /*InsnID*/0,
      // GIR_Coverage, 5927,
      GIR_Done,
    // Label 526: @43379
    GIM_Try, /*On fail goto*//*Label 527*/ GIMT_Encode4(43418), // Rule ID 5929 //
      GIM_CheckType, /*MI*/0, /*Op*/1, /*Type*/GILLT_v2s16,
      GIM_CheckRegBankForClass, /*MI*/0, /*Op*/0, /*RC*/GIMT_Encode2(AMDGPU::SReg_32RegClassID),
      GIM_CheckRegBankForClass, /*MI*/0, /*Op*/1, /*RC*/GIMT_Encode2(AMDGPU::SReg_32RegClassID),
      // (bitconvert:{ *:[v2i16] } SReg_32:{ *:[v2f16] }:$src0)  =>  SReg_32:{ *:[v2i16] }:$src0
      GIR_BuildMI, /*InsnID*/0, /*Opcode*/GIMT_Encode2(TargetOpcode::COPY),
      GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/0, // dst
      GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/1, // src0
      GIR_ConstrainOperandRC, /*InsnID*/0, /*Op*/0, GIMT_Encode2(AMDGPU::SReg_32RegClassID),
      GIR_EraseFromParent, /*InsnID*/0,
      // GIR_Coverage, 5929,
      GIR_Done,
    // Label 527: @43418
    GIM_Try, /*On fail goto*//*Label 528*/ GIMT_Encode4(43457), // Rule ID 5930 //
      GIM_CheckType, /*MI*/0, /*Op*/1, /*Type*/GILLT_v2s16,
      GIM_CheckRegBankForClass, /*MI*/0, /*Op*/0, /*RC*/GIMT_Encode2(AMDGPU::SReg_32RegClassID),
      GIM_CheckRegBankForClass, /*MI*/0, /*Op*/1, /*RC*/GIMT_Encode2(AMDGPU::SReg_32RegClassID),
      // (bitconvert:{ *:[v2f16] } SReg_32:{ *:[v2i16] }:$src0)  =>  SReg_32:{ *:[v2f16] }:$src0
      GIR_BuildMI, /*InsnID*/0, /*Opcode*/GIMT_Encode2(TargetOpcode::COPY),
      GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/0, // dst
      GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/1, // src0
      GIR_ConstrainOperandRC, /*InsnID*/0, /*Op*/0, GIMT_Encode2(AMDGPU::SReg_32RegClassID),
      GIR_EraseFromParent, /*InsnID*/0,
      // GIR_Coverage, 5930,
      GIR_Done,
    // Label 528: @43457
    GIM_Try, /*On fail goto*//*Label 529*/ GIMT_Encode4(43496), // Rule ID 5931 //
      GIM_CheckType, /*MI*/0, /*Op*/1, /*Type*/GILLT_s32,
      GIM_CheckRegBankForClass, /*MI*/0, /*Op*/0, /*RC*/GIMT_Encode2(AMDGPU::SReg_32RegClassID),
      GIM_CheckRegBankForClass, /*MI*/0, /*Op*/1, /*RC*/GIMT_Encode2(AMDGPU::SReg_32RegClassID),
      // (bitconvert:{ *:[v2f16] } SReg_32:{ *:[f32] }:$src0)  =>  SReg_32:{ *:[v2f16] }:$src0
      GIR_BuildMI, /*InsnID*/0, /*Opcode*/GIMT_Encode2(TargetOpcode::COPY),
      GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/0, // dst
      GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/1, // src0
      GIR_ConstrainOperandRC, /*InsnID*/0, /*Op*/0, GIMT_Encode2(AMDGPU::SReg_32RegClassID),
      GIR_EraseFromParent, /*InsnID*/0,
      // GIR_Coverage, 5931,
      GIR_Done,
    // Label 529: @43496
    GIM_Try, /*On fail goto*//*Label 530*/ GIMT_Encode4(43535), // Rule ID 5933 //
      GIM_CheckType, /*MI*/0, /*Op*/1, /*Type*/GILLT_s32,
      GIM_CheckRegBankForClass, /*MI*/0, /*Op*/0, /*RC*/GIMT_Encode2(AMDGPU::SReg_32RegClassID),
      GIM_CheckRegBankForClass, /*MI*/0, /*Op*/1, /*RC*/GIMT_Encode2(AMDGPU::SReg_32RegClassID),
      // (bitconvert:{ *:[v2i16] } SReg_32:{ *:[f32] }:$src0)  =>  SReg_32:{ *:[v2i16] }:$src0
      GIR_BuildMI, /*InsnID*/0, /*Opcode*/GIMT_Encode2(TargetOpcode::COPY),
      GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/0, // dst
      GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/1, // src0
      GIR_ConstrainOperandRC, /*InsnID*/0, /*Op*/0, GIMT_Encode2(AMDGPU::SReg_32RegClassID),
      GIR_EraseFromParent, /*InsnID*/0,
      // GIR_Coverage, 5933,
      GIR_Done,
    // Label 530: @43535
    GIM_Try, /*On fail goto*//*Label 531*/ GIMT_Encode4(43574), // Rule ID 5935 //
      GIM_CheckType, /*MI*/0, /*Op*/1, /*Type*/GILLT_s32,
      GIM_CheckRegBankForClass, /*MI*/0, /*Op*/0, /*RC*/GIMT_Encode2(AMDGPU::SReg_32RegClassID),
      GIM_CheckRegBankForClass, /*MI*/0, /*Op*/1, /*RC*/GIMT_Encode2(AMDGPU::SReg_32RegClassID),
      // (bitconvert:{ *:[v2bf16] } SReg_32:{ *:[i32] }:$src0)  =>  SReg_32:{ *:[v2bf16] }:$src0
      GIR_BuildMI, /*InsnID*/0, /*Opcode*/GIMT_Encode2(TargetOpcode::COPY),
      GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/0, // dst
      GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/1, // src0
      GIR_ConstrainOperandRC, /*InsnID*/0, /*Op*/0, GIMT_Encode2(AMDGPU::SReg_32RegClassID),
      GIR_EraseFromParent, /*InsnID*/0,
      // GIR_Coverage, 5935,
      GIR_Done,
    // Label 531: @43574
    GIM_Try, /*On fail goto*//*Label 532*/ GIMT_Encode4(43613), // Rule ID 5937 //
      GIM_CheckType, /*MI*/0, /*Op*/1, /*Type*/GILLT_s32,
      GIM_CheckRegBankForClass, /*MI*/0, /*Op*/0, /*RC*/GIMT_Encode2(AMDGPU::VGPR_32RegClassID),
      GIM_CheckRegBankForClass, /*MI*/0, /*Op*/1, /*RC*/GIMT_Encode2(AMDGPU::VGPR_32RegClassID),
      // (bitconvert:{ *:[v2bf16] } VGPR_32:{ *:[i32] }:$src0)  =>  VGPR_32:{ *:[v2bf16] }:$src0
      GIR_BuildMI, /*InsnID*/0, /*Opcode*/GIMT_Encode2(TargetOpcode::COPY),
      GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/0, // dst
      GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/1, // src0
      GIR_ConstrainOperandRC, /*InsnID*/0, /*Op*/0, GIMT_Encode2(AMDGPU::VGPR_32RegClassID),
      GIR_EraseFromParent, /*InsnID*/0,
      // GIR_Coverage, 5937,
      GIR_Done,
    // Label 532: @43613
    GIM_Try, /*On fail goto*//*Label 533*/ GIMT_Encode4(43652), // Rule ID 5939 //
      GIM_CheckType, /*MI*/0, /*Op*/1, /*Type*/GILLT_v2s16,
      GIM_CheckRegBankForClass, /*MI*/0, /*Op*/0, /*RC*/GIMT_Encode2(AMDGPU::SReg_32RegClassID),
      GIM_CheckRegBankForClass, /*MI*/0, /*Op*/1, /*RC*/GIMT_Encode2(AMDGPU::SReg_32RegClassID),
      // (bitconvert:{ *:[v2bf16] } SReg_32:{ *:[v2i16] }:$src0)  =>  SReg_32:{ *:[v2bf16] }:$src0
      GIR_BuildMI, /*InsnID*/0, /*Opcode*/GIMT_Encode2(TargetOpcode::COPY),
      GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/0, // dst
      GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/1, // src0
      GIR_ConstrainOperandRC, /*InsnID*/0, /*Op*/0, GIMT_Encode2(AMDGPU::SReg_32RegClassID),
      GIR_EraseFromParent, /*InsnID*/0,
      // GIR_Coverage, 5939,
      GIR_Done,
    // Label 533: @43652
    GIM_Try, /*On fail goto*//*Label 534*/ GIMT_Encode4(43691), // Rule ID 5940 //
      GIM_CheckType, /*MI*/0, /*Op*/1, /*Type*/GILLT_v2s16,
      GIM_CheckRegBankForClass, /*MI*/0, /*Op*/0, /*RC*/GIMT_Encode2(AMDGPU::SReg_32RegClassID),
      GIM_CheckRegBankForClass, /*MI*/0, /*Op*/1, /*RC*/GIMT_Encode2(AMDGPU::SReg_32RegClassID),
      // (bitconvert:{ *:[v2i16] } SReg_32:{ *:[v2bf16] }:$src0)  =>  SReg_32:{ *:[v2i16] }:$src0
      GIR_BuildMI, /*InsnID*/0, /*Opcode*/GIMT_Encode2(TargetOpcode::COPY),
      GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/0, // dst
      GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/1, // src0
      GIR_ConstrainOperandRC, /*InsnID*/0, /*Op*/0, GIMT_Encode2(AMDGPU::SReg_32RegClassID),
      GIR_EraseFromParent, /*InsnID*/0,
      // GIR_Coverage, 5940,
      GIR_Done,
    // Label 534: @43691
    GIM_Try, /*On fail goto*//*Label 535*/ GIMT_Encode4(43730), // Rule ID 5941 //
      GIM_CheckType, /*MI*/0, /*Op*/1, /*Type*/GILLT_v2s16,
      GIM_CheckRegBankForClass, /*MI*/0, /*Op*/0, /*RC*/GIMT_Encode2(AMDGPU::VGPR_32RegClassID),
      GIM_CheckRegBankForClass, /*MI*/0, /*Op*/1, /*RC*/GIMT_Encode2(AMDGPU::VGPR_32RegClassID),
      // (bitconvert:{ *:[v2bf16] } VGPR_32:{ *:[v2i16] }:$src0)  =>  VGPR_32:{ *:[v2bf16] }:$src0
      GIR_BuildMI, /*InsnID*/0, /*Opcode*/GIMT_Encode2(TargetOpcode::COPY),
      GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/0, // dst
      GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/1, // src0
      GIR_ConstrainOperandRC, /*InsnID*/0, /*Op*/0, GIMT_Encode2(AMDGPU::VGPR_32RegClassID),
      GIR_EraseFromParent, /*InsnID*/0,
      // GIR_Coverage, 5941,
      GIR_Done,
    // Label 535: @43730
    GIM_Try, /*On fail goto*//*Label 536*/ GIMT_Encode4(43769), // Rule ID 5942 //
      GIM_CheckType, /*MI*/0, /*Op*/1, /*Type*/GILLT_v2s16,
      GIM_CheckRegBankForClass, /*MI*/0, /*Op*/0, /*RC*/GIMT_Encode2(AMDGPU::VGPR_32RegClassID),
      GIM_CheckRegBankForClass, /*MI*/0, /*Op*/1, /*RC*/GIMT_Encode2(AMDGPU::VGPR_32RegClassID),
      // (bitconvert:{ *:[v2i16] } VGPR_32:{ *:[v2bf16] }:$src0)  =>  VGPR_32:{ *:[v2i16] }:$src0
      GIR_BuildMI, /*InsnID*/0, /*Opcode*/GIMT_Encode2(TargetOpcode::COPY),
      GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/0, // dst
      GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/1, // src0
      GIR_ConstrainOperandRC, /*InsnID*/0, /*Op*/0, GIMT_Encode2(AMDGPU::VGPR_32RegClassID),
      GIR_EraseFromParent, /*InsnID*/0,
      // GIR_Coverage, 5942,
      GIR_Done,
    // Label 536: @43769
    GIM_Try, /*On fail goto*//*Label 537*/ GIMT_Encode4(43808), // Rule ID 5943 //
      GIM_CheckType, /*MI*/0, /*Op*/1, /*Type*/GILLT_v2s16,
      GIM_CheckRegBankForClass, /*MI*/0, /*Op*/0, /*RC*/GIMT_Encode2(AMDGPU::SReg_32RegClassID),
      GIM_CheckRegBankForClass, /*MI*/0, /*Op*/1, /*RC*/GIMT_Encode2(AMDGPU::SReg_32RegClassID),
      // (bitconvert:{ *:[v2bf16] } SReg_32:{ *:[v2f16] }:$src0)  =>  SReg_32:{ *:[v2bf16] }:$src0
      GIR_BuildMI, /*InsnID*/0, /*Opcode*/GIMT_Encode2(TargetOpcode::COPY),
      GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/0, // dst
      GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/1, // src0
      GIR_ConstrainOperandRC, /*InsnID*/0, /*Op*/0, GIMT_Encode2(AMDGPU::SReg_32RegClassID),
      GIR_EraseFromParent, /*InsnID*/0,
      // GIR_Coverage, 5943,
      GIR_Done,
    // Label 537: @43808
    GIM_Try, /*On fail goto*//*Label 538*/ GIMT_Encode4(43847), // Rule ID 5944 //
      GIM_CheckType, /*MI*/0, /*Op*/1, /*Type*/GILLT_v2s16,
      GIM_CheckRegBankForClass, /*MI*/0, /*Op*/0, /*RC*/GIMT_Encode2(AMDGPU::SReg_32RegClassID),
      GIM_CheckRegBankForClass, /*MI*/0, /*Op*/1, /*RC*/GIMT_Encode2(AMDGPU::SReg_32RegClassID),
      // (bitconvert:{ *:[v2f16] } SReg_32:{ *:[v2bf16] }:$src0)  =>  SReg_32:{ *:[v2f16] }:$src0
      GIR_BuildMI, /*InsnID*/0, /*Opcode*/GIMT_Encode2(TargetOpcode::COPY),
      GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/0, // dst
      GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/1, // src0
      GIR_ConstrainOperandRC, /*InsnID*/0, /*Op*/0, GIMT_Encode2(AMDGPU::SReg_32RegClassID),
      GIR_EraseFromParent, /*InsnID*/0,
      // GIR_Coverage, 5944,
      GIR_Done,
    // Label 538: @43847
    GIM_Try, /*On fail goto*//*Label 539*/ GIMT_Encode4(43886), // Rule ID 5945 //
      GIM_CheckType, /*MI*/0, /*Op*/1, /*Type*/GILLT_v2s16,
      GIM_CheckRegBankForClass, /*MI*/0, /*Op*/0, /*RC*/GIMT_Encode2(AMDGPU::VGPR_32RegClassID),
      GIM_CheckRegBankForClass, /*MI*/0, /*Op*/1, /*RC*/GIMT_Encode2(AMDGPU::VGPR_32RegClassID),
      // (bitconvert:{ *:[v2bf16] } VGPR_32:{ *:[v2f16] }:$src0)  =>  VGPR_32:{ *:[v2bf16] }:$src0
      GIR_BuildMI, /*InsnID*/0, /*Opcode*/GIMT_Encode2(TargetOpcode::COPY),
      GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/0, // dst
      GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/1, // src0
      GIR_ConstrainOperandRC, /*InsnID*/0, /*Op*/0, GIMT_Encode2(AMDGPU::VGPR_32RegClassID),
      GIR_EraseFromParent, /*InsnID*/0,
      // GIR_Coverage, 5945,
      GIR_Done,
    // Label 539: @43886
    GIM_Try, /*On fail goto*//*Label 540*/ GIMT_Encode4(43925), // Rule ID 5946 //
      GIM_CheckType, /*MI*/0, /*Op*/1, /*Type*/GILLT_v2s16,
      GIM_CheckRegBankForClass, /*MI*/0, /*Op*/0, /*RC*/GIMT_Encode2(AMDGPU::VGPR_32RegClassID),
      GIM_CheckRegBankForClass, /*MI*/0, /*Op*/1, /*RC*/GIMT_Encode2(AMDGPU::VGPR_32RegClassID),
      // (bitconvert:{ *:[v2f16] } VGPR_32:{ *:[v2bf16] }:$src0)  =>  VGPR_32:{ *:[v2f16] }:$src0
      GIR_BuildMI, /*InsnID*/0, /*Opcode*/GIMT_Encode2(TargetOpcode::COPY),
      GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/0, // dst
      GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/1, // src0
      GIR_ConstrainOperandRC, /*InsnID*/0, /*Op*/0, GIMT_Encode2(AMDGPU::VGPR_32RegClassID),
      GIR_EraseFromParent, /*InsnID*/0,
      // GIR_Coverage, 5946,
      GIR_Done,
    // Label 540: @43925
    GIM_Try, /*On fail goto*//*Label 541*/ GIMT_Encode4(43964), // Rule ID 5948 //
      GIM_CheckType, /*MI*/0, /*Op*/1, /*Type*/GILLT_s32,
      GIM_CheckRegBankForClass, /*MI*/0, /*Op*/0, /*RC*/GIMT_Encode2(AMDGPU::VGPR_32RegClassID),
      GIM_CheckRegBankForClass, /*MI*/0, /*Op*/1, /*RC*/GIMT_Encode2(AMDGPU::VGPR_32RegClassID),
      // (bitconvert:{ *:[v2bf16] } VGPR_32:{ *:[f32] }:$src0)  =>  VGPR_32:{ *:[v2bf16] }:$src0
      GIR_BuildMI, /*InsnID*/0, /*Opcode*/GIMT_Encode2(TargetOpcode::COPY),
      GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/0, // dst
      GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/1, // src0
      GIR_ConstrainOperandRC, /*InsnID*/0, /*Op*/0, GIMT_Encode2(AMDGPU::VGPR_32RegClassID),
      GIR_EraseFromParent, /*InsnID*/0,
      // GIR_Coverage, 5948,
      GIR_Done,
    // Label 541: @43964
    GIM_Try, /*On fail goto*//*Label 542*/ GIMT_Encode4(44003), // Rule ID 5950 //
      GIM_CheckType, /*MI*/0, /*Op*/1, /*Type*/GILLT_s32,
      GIM_CheckRegBankForClass, /*MI*/0, /*Op*/0, /*RC*/GIMT_Encode2(AMDGPU::SReg_32RegClassID),
      GIM_CheckRegBankForClass, /*MI*/0, /*Op*/1, /*RC*/GIMT_Encode2(AMDGPU::SReg_32RegClassID),
      // (bitconvert:{ *:[v2bf16] } SReg_32:{ *:[f32] }:$src0)  =>  SReg_32:{ *:[v2bf16] }:$src0
      GIR_BuildMI, /*InsnID*/0, /*Opcode*/GIMT_Encode2(TargetOpcode::COPY),
      GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/0, // dst
      GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/1, // src0
      GIR_ConstrainOperandRC, /*InsnID*/0, /*Op*/0, GIMT_Encode2(AMDGPU::SReg_32RegClassID),
      GIR_EraseFromParent, /*InsnID*/0,
      // GIR_Coverage, 5950,
      GIR_Done,
    // Label 542: @44003
    GIM_Reject,
    // Label 465: @44004
    GIM_Try, /*On fail goto*//*Label 543*/ GIMT_Encode4(44043), // Rule ID 5953 //
      GIM_CheckType, /*MI*/0, /*Op*/1, /*Type*/GILLT_v2s32,
      GIM_CheckRegBankForClass, /*MI*/0, /*Op*/0, /*RC*/GIMT_Encode2(AMDGPU::VReg_64RegClassID),
      GIM_CheckRegBankForClass, /*MI*/0, /*Op*/1, /*RC*/GIMT_Encode2(AMDGPU::VReg_64RegClassID),
      // (bitconvert:{ *:[v2i32] } VReg_64:{ *:[v2f32] }:$src0)  =>  VReg_64:{ *:[v2i32] }:$src0
      GIR_BuildMI, /*InsnID*/0, /*Opcode*/GIMT_Encode2(TargetOpcode::COPY),
      GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/0, // dst
      GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/1, // src0
      GIR_ConstrainOperandRC, /*InsnID*/0, /*Op*/0, GIMT_Encode2(AMDGPU::VReg_64RegClassID),
      GIR_EraseFromParent, /*InsnID*/0,
      // GIR_Coverage, 5953,
      GIR_Done,
    // Label 543: @44043
    GIM_Try, /*On fail goto*//*Label 544*/ GIMT_Encode4(44082), // Rule ID 5954 //
      GIM_CheckType, /*MI*/0, /*Op*/1, /*Type*/GILLT_v2s32,
      GIM_CheckRegBankForClass, /*MI*/0, /*Op*/0, /*RC*/GIMT_Encode2(AMDGPU::VReg_64RegClassID),
      GIM_CheckRegBankForClass, /*MI*/0, /*Op*/1, /*RC*/GIMT_Encode2(AMDGPU::VReg_64RegClassID),
      // (bitconvert:{ *:[v2f32] } VReg_64:{ *:[v2i32] }:$src0)  =>  VReg_64:{ *:[v2f32] }:$src0
      GIR_BuildMI, /*InsnID*/0, /*Opcode*/GIMT_Encode2(TargetOpcode::COPY),
      GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/0, // dst
      GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/1, // src0
      GIR_ConstrainOperandRC, /*InsnID*/0, /*Op*/0, GIMT_Encode2(AMDGPU::VReg_64RegClassID),
      GIR_EraseFromParent, /*InsnID*/0,
      // GIR_Coverage, 5954,
      GIR_Done,
    // Label 544: @44082
    GIM_Try, /*On fail goto*//*Label 545*/ GIMT_Encode4(44121), // Rule ID 5956 //
      GIM_CheckType, /*MI*/0, /*Op*/1, /*Type*/GILLT_s64,
      GIM_CheckRegBankForClass, /*MI*/0, /*Op*/0, /*RC*/GIMT_Encode2(AMDGPU::VReg_64RegClassID),
      GIM_CheckRegBankForClass, /*MI*/0, /*Op*/1, /*RC*/GIMT_Encode2(AMDGPU::VReg_64RegClassID),
      // (bitconvert:{ *:[v2i32] } VReg_64:{ *:[i64] }:$src0)  =>  VReg_64:{ *:[v2i32] }:$src0
      GIR_BuildMI, /*InsnID*/0, /*Opcode*/GIMT_Encode2(TargetOpcode::COPY),
      GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/0, // dst
      GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/1, // src0
      GIR_ConstrainOperandRC, /*InsnID*/0, /*Op*/0, GIMT_Encode2(AMDGPU::VReg_64RegClassID),
      GIR_EraseFromParent, /*InsnID*/0,
      // GIR_Coverage, 5956,
      GIR_Done,
    // Label 545: @44121
    GIM_Try, /*On fail goto*//*Label 546*/ GIMT_Encode4(44160), // Rule ID 5958 //
      GIM_CheckType, /*MI*/0, /*Op*/1, /*Type*/GILLT_s64,
      GIM_CheckRegBankForClass, /*MI*/0, /*Op*/0, /*RC*/GIMT_Encode2(AMDGPU::VReg_64RegClassID),
      GIM_CheckRegBankForClass, /*MI*/0, /*Op*/1, /*RC*/GIMT_Encode2(AMDGPU::VReg_64RegClassID),
      // (bitconvert:{ *:[v2f32] } VReg_64:{ *:[i64] }:$src0)  =>  VReg_64:{ *:[v2f32] }:$src0
      GIR_BuildMI, /*InsnID*/0, /*Opcode*/GIMT_Encode2(TargetOpcode::COPY),
      GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/0, // dst
      GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/1, // src0
      GIR_ConstrainOperandRC, /*InsnID*/0, /*Op*/0, GIMT_Encode2(AMDGPU::VReg_64RegClassID),
      GIR_EraseFromParent, /*InsnID*/0,
      // GIR_Coverage, 5958,
      GIR_Done,
    // Label 546: @44160
    GIM_Try, /*On fail goto*//*Label 547*/ GIMT_Encode4(44199), // Rule ID 5960 //
      GIM_CheckType, /*MI*/0, /*Op*/1, /*Type*/GILLT_s64,
      GIM_CheckRegBankForClass, /*MI*/0, /*Op*/0, /*RC*/GIMT_Encode2(AMDGPU::VReg_64RegClassID),
      GIM_CheckRegBankForClass, /*MI*/0, /*Op*/1, /*RC*/GIMT_Encode2(AMDGPU::VReg_64RegClassID),
      // (bitconvert:{ *:[v2f32] } VReg_64:{ *:[f64] }:$src0)  =>  VReg_64:{ *:[v2f32] }:$src0
      GIR_BuildMI, /*InsnID*/0, /*Opcode*/GIMT_Encode2(TargetOpcode::COPY),
      GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/0, // dst
      GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/1, // src0
      GIR_ConstrainOperandRC, /*InsnID*/0, /*Op*/0, GIMT_Encode2(AMDGPU::VReg_64RegClassID),
      GIR_EraseFromParent, /*InsnID*/0,
      // GIR_Coverage, 5960,
      GIR_Done,
    // Label 547: @44199
    GIM_Try, /*On fail goto*//*Label 548*/ GIMT_Encode4(44238), // Rule ID 5962 //
      GIM_CheckType, /*MI*/0, /*Op*/1, /*Type*/GILLT_s64,
      GIM_CheckRegBankForClass, /*MI*/0, /*Op*/0, /*RC*/GIMT_Encode2(AMDGPU::VReg_64RegClassID),
      GIM_CheckRegBankForClass, /*MI*/0, /*Op*/1, /*RC*/GIMT_Encode2(AMDGPU::VReg_64RegClassID),
      // (bitconvert:{ *:[v2i32] } VReg_64:{ *:[f64] }:$src0)  =>  VReg_64:{ *:[v2i32] }:$src0
      GIR_BuildMI, /*InsnID*/0, /*Opcode*/GIMT_Encode2(TargetOpcode::COPY),
      GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/0, // dst
      GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/1, // src0
      GIR_ConstrainOperandRC, /*InsnID*/0, /*Op*/0, GIMT_Encode2(AMDGPU::VReg_64RegClassID),
      GIR_EraseFromParent, /*InsnID*/0,
      // GIR_Coverage, 5962,
      GIR_Done,
    // Label 548: @44238
    GIM_Try, /*On fail goto*//*Label 549*/ GIMT_Encode4(44277), // Rule ID 5966 //
      GIM_CheckType, /*MI*/0, /*Op*/1, /*Type*/GILLT_v4s16,
      GIM_CheckRegBankForClass, /*MI*/0, /*Op*/0, /*RC*/GIMT_Encode2(AMDGPU::VReg_64RegClassID),
      GIM_CheckRegBankForClass, /*MI*/0, /*Op*/1, /*RC*/GIMT_Encode2(AMDGPU::VReg_64RegClassID),
      // (bitconvert:{ *:[v2i32] } VReg_64:{ *:[v4bf16] }:$src0)  =>  VReg_64:{ *:[v2i32] }:$src0
      GIR_BuildMI, /*InsnID*/0, /*Opcode*/GIMT_Encode2(TargetOpcode::COPY),
      GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/0, // dst
      GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/1, // src0
      GIR_ConstrainOperandRC, /*InsnID*/0, /*Op*/0, GIMT_Encode2(AMDGPU::VReg_64RegClassID),
      GIR_EraseFromParent, /*InsnID*/0,
      // GIR_Coverage, 5966,
      GIR_Done,
    // Label 549: @44277
    GIM_Try, /*On fail goto*//*Label 550*/ GIMT_Encode4(44316), // Rule ID 5974 //
      GIM_CheckType, /*MI*/0, /*Op*/1, /*Type*/GILLT_v4s16,
      GIM_CheckRegBankForClass, /*MI*/0, /*Op*/0, /*RC*/GIMT_Encode2(AMDGPU::VReg_64RegClassID),
      GIM_CheckRegBankForClass, /*MI*/0, /*Op*/1, /*RC*/GIMT_Encode2(AMDGPU::VReg_64RegClassID),
      // (bitconvert:{ *:[v2f32] } VReg_64:{ *:[v4bf16] }:$src0)  =>  VReg_64:{ *:[v2f32] }:$src0
      GIR_BuildMI, /*InsnID*/0, /*Opcode*/GIMT_Encode2(TargetOpcode::COPY),
      GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/0, // dst
      GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/1, // src0
      GIR_ConstrainOperandRC, /*InsnID*/0, /*Op*/0, GIMT_Encode2(AMDGPU::VReg_64RegClassID),
      GIR_EraseFromParent, /*InsnID*/0,
      // GIR_Coverage, 5974,
      GIR_Done,
    // Label 550: @44316
    GIM_Try, /*On fail goto*//*Label 551*/ GIMT_Encode4(44355), // Rule ID 5977 //
      GIM_CheckType, /*MI*/0, /*Op*/1, /*Type*/GILLT_v4s16,
      GIM_CheckRegBankForClass, /*MI*/0, /*Op*/0, /*RC*/GIMT_Encode2(AMDGPU::VReg_64RegClassID),
      GIM_CheckRegBankForClass, /*MI*/0, /*Op*/1, /*RC*/GIMT_Encode2(AMDGPU::VReg_64RegClassID),
      // (bitconvert:{ *:[v2i32] } VReg_64:{ *:[v4f16] }:$src0)  =>  VReg_64:{ *:[v2i32] }:$src0
      GIR_BuildMI, /*InsnID*/0, /*Opcode*/GIMT_Encode2(TargetOpcode::COPY),
      GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/0, // dst
      GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/1, // src0
      GIR_ConstrainOperandRC, /*InsnID*/0, /*Op*/0, GIMT_Encode2(AMDGPU::VReg_64RegClassID),
      GIR_EraseFromParent, /*InsnID*/0,
      // GIR_Coverage, 5977,
      GIR_Done,
    // Label 551: @44355
    GIM_Try, /*On fail goto*//*Label 552*/ GIMT_Encode4(44394), // Rule ID 5979 //
      GIM_CheckType, /*MI*/0, /*Op*/1, /*Type*/GILLT_v4s16,
      GIM_CheckRegBankForClass, /*MI*/0, /*Op*/0, /*RC*/GIMT_Encode2(AMDGPU::VReg_64RegClassID),
      GIM_CheckRegBankForClass, /*MI*/0, /*Op*/1, /*RC*/GIMT_Encode2(AMDGPU::VReg_64RegClassID),
      // (bitconvert:{ *:[v2i32] } VReg_64:{ *:[v4f16] }:$src0)  =>  VReg_64:{ *:[v2i32] }:$src0
      GIR_BuildMI, /*InsnID*/0, /*Opcode*/GIMT_Encode2(TargetOpcode::COPY),
      GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/0, // dst
      GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/1, // src0
      GIR_ConstrainOperandRC, /*InsnID*/0, /*Op*/0, GIMT_Encode2(AMDGPU::VReg_64RegClassID),
      GIR_EraseFromParent, /*InsnID*/0,
      // GIR_Coverage, 5979,
      GIR_Done,
    // Label 552: @44394
    GIM_Try, /*On fail goto*//*Label 553*/ GIMT_Encode4(44433), // Rule ID 5980 //
      GIM_CheckType, /*MI*/0, /*Op*/1, /*Type*/GILLT_v4s16,
      GIM_CheckRegBankForClass, /*MI*/0, /*Op*/0, /*RC*/GIMT_Encode2(AMDGPU::VReg_64RegClassID),
      GIM_CheckRegBankForClass, /*MI*/0, /*Op*/1, /*RC*/GIMT_Encode2(AMDGPU::VReg_64RegClassID),
      // (bitconvert:{ *:[v2i32] } VReg_64:{ *:[v4i16] }:$src0)  =>  VReg_64:{ *:[v2i32] }:$src0
      GIR_BuildMI, /*InsnID*/0, /*Opcode*/GIMT_Encode2(TargetOpcode::COPY),
      GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/0, // dst
      GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/1, // src0
      GIR_ConstrainOperandRC, /*InsnID*/0, /*Op*/0, GIMT_Encode2(AMDGPU::VReg_64RegClassID),
      GIR_EraseFromParent, /*InsnID*/0,
      // GIR_Coverage, 5980,
      GIR_Done,
    // Label 553: @44433
    GIM_Try, /*On fail goto*//*Label 554*/ GIMT_Encode4(44472), // Rule ID 5982 //
      GIM_CheckType, /*MI*/0, /*Op*/1, /*Type*/GILLT_v4s16,
      GIM_CheckRegBankForClass, /*MI*/0, /*Op*/0, /*RC*/GIMT_Encode2(AMDGPU::VReg_64RegClassID),
      GIM_CheckRegBankForClass, /*MI*/0, /*Op*/1, /*RC*/GIMT_Encode2(AMDGPU::VReg_64RegClassID),
      // (bitconvert:{ *:[v2f32] } VReg_64:{ *:[v4f16] }:$src0)  =>  VReg_64:{ *:[v2f32] }:$src0
      GIR_BuildMI, /*InsnID*/0, /*Opcode*/GIMT_Encode2(TargetOpcode::COPY),
      GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/0, // dst
      GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/1, // src0
      GIR_ConstrainOperandRC, /*InsnID*/0, /*Op*/0, GIMT_Encode2(AMDGPU::VReg_64RegClassID),
      GIR_EraseFromParent, /*InsnID*/0,
      // GIR_Coverage, 5982,
      GIR_Done,
    // Label 554: @44472
    GIM_Try, /*On fail goto*//*Label 555*/ GIMT_Encode4(44511), // Rule ID 5984 //
      GIM_CheckType, /*MI*/0, /*Op*/1, /*Type*/GILLT_v4s16,
      GIM_CheckRegBankForClass, /*MI*/0, /*Op*/0, /*RC*/GIMT_Encode2(AMDGPU::VReg_64RegClassID),
      GIM_CheckRegBankForClass, /*MI*/0, /*Op*/1, /*RC*/GIMT_Encode2(AMDGPU::VReg_64RegClassID),
      // (bitconvert:{ *:[v2f32] } VReg_64:{ *:[v4i16] }:$src0)  =>  VReg_64:{ *:[v2f32] }:$src0
      GIR_BuildMI, /*InsnID*/0, /*Opcode*/GIMT_Encode2(TargetOpcode::COPY),
      GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/0, // dst
      GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/1, // src0
      GIR_ConstrainOperandRC, /*InsnID*/0, /*Op*/0, GIMT_Encode2(AMDGPU::VReg_64RegClassID),
      GIR_EraseFromParent, /*InsnID*/0,
      // GIR_Coverage, 5984,
      GIR_Done,
    // Label 555: @44511
    GIM_Reject,
    // Label 466: @44512
    GIM_Try, /*On fail goto*//*Label 556*/ GIMT_Encode4(44551), // Rule ID 5998 //
      GIM_CheckType, /*MI*/0, /*Op*/1, /*Type*/GILLT_v4s32,
      GIM_CheckRegBankForClass, /*MI*/0, /*Op*/0, /*RC*/GIMT_Encode2(AMDGPU::SReg_128RegClassID),
      GIM_CheckRegBankForClass, /*MI*/0, /*Op*/1, /*RC*/GIMT_Encode2(AMDGPU::SReg_128RegClassID),
      // (bitconvert:{ *:[v2i64] } SReg_128:{ *:[v4i32] }:$src0)  =>  SReg_128:{ *:[v2i64] }:$src0
      GIR_BuildMI, /*InsnID*/0, /*Opcode*/GIMT_Encode2(TargetOpcode::COPY),
      GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/0, // dst
      GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/1, // src0
      GIR_ConstrainOperandRC, /*InsnID*/0, /*Op*/0, GIMT_Encode2(AMDGPU::SReg_128RegClassID),
      GIR_EraseFromParent, /*InsnID*/0,
      // GIR_Coverage, 5998,
      GIR_Done,
    // Label 556: @44551
    GIM_Try, /*On fail goto*//*Label 557*/ GIMT_Encode4(44590), // Rule ID 6000 //
      GIM_CheckType, /*MI*/0, /*Op*/1, /*Type*/GILLT_v4s32,
      GIM_CheckRegBankForClass, /*MI*/0, /*Op*/0, /*RC*/GIMT_Encode2(AMDGPU::VReg_128RegClassID),
      GIM_CheckRegBankForClass, /*MI*/0, /*Op*/1, /*RC*/GIMT_Encode2(AMDGPU::VReg_128RegClassID),
      // (bitconvert:{ *:[v2f64] } VReg_128:{ *:[v4f32] }:$src0)  =>  VReg_128:{ *:[v2f64] }:$src0
      GIR_BuildMI, /*InsnID*/0, /*Opcode*/GIMT_Encode2(TargetOpcode::COPY),
      GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/0, // dst
      GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/1, // src0
      GIR_ConstrainOperandRC, /*InsnID*/0, /*Op*/0, GIMT_Encode2(AMDGPU::VReg_128RegClassID),
      GIR_EraseFromParent, /*InsnID*/0,
      // GIR_Coverage, 6000,
      GIR_Done,
    // Label 557: @44590
    GIM_Try, /*On fail goto*//*Label 558*/ GIMT_Encode4(44629), // Rule ID 6001 //
      GIM_CheckType, /*MI*/0, /*Op*/1, /*Type*/GILLT_v4s32,
      GIM_CheckRegBankForClass, /*MI*/0, /*Op*/0, /*RC*/GIMT_Encode2(AMDGPU::VReg_128RegClassID),
      GIM_CheckRegBankForClass, /*MI*/0, /*Op*/1, /*RC*/GIMT_Encode2(AMDGPU::VReg_128RegClassID),
      // (bitconvert:{ *:[v2f64] } VReg_128:{ *:[v4i32] }:$src0)  =>  VReg_128:{ *:[v2f64] }:$src0
      GIR_BuildMI, /*InsnID*/0, /*Opcode*/GIMT_Encode2(TargetOpcode::COPY),
      GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/0, // dst
      GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/1, // src0
      GIR_ConstrainOperandRC, /*InsnID*/0, /*Op*/0, GIMT_Encode2(AMDGPU::VReg_128RegClassID),
      GIR_EraseFromParent, /*InsnID*/0,
      // GIR_Coverage, 6001,
      GIR_Done,
    // Label 558: @44629
    GIM_Try, /*On fail goto*//*Label 559*/ GIMT_Encode4(44668), // Rule ID 6004 //
      GIM_CheckType, /*MI*/0, /*Op*/1, /*Type*/GILLT_v2s64,
      GIM_CheckRegBankForClass, /*MI*/0, /*Op*/0, /*RC*/GIMT_Encode2(AMDGPU::VReg_128RegClassID),
      GIM_CheckRegBankForClass, /*MI*/0, /*Op*/1, /*RC*/GIMT_Encode2(AMDGPU::VReg_128RegClassID),
      // (bitconvert:{ *:[v2i64] } VReg_128:{ *:[v2f64] }:$src0)  =>  VReg_128:{ *:[v2i64] }:$src0
      GIR_BuildMI, /*InsnID*/0, /*Opcode*/GIMT_Encode2(TargetOpcode::COPY),
      GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/0, // dst
      GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/1, // src0
      GIR_ConstrainOperandRC, /*InsnID*/0, /*Op*/0, GIMT_Encode2(AMDGPU::VReg_128RegClassID),
      GIR_EraseFromParent, /*InsnID*/0,
      // GIR_Coverage, 6004,
      GIR_Done,
    // Label 559: @44668
    GIM_Try, /*On fail goto*//*Label 560*/ GIMT_Encode4(44707), // Rule ID 6005 //
      GIM_CheckType, /*MI*/0, /*Op*/1, /*Type*/GILLT_v2s64,
      GIM_CheckRegBankForClass, /*MI*/0, /*Op*/0, /*RC*/GIMT_Encode2(AMDGPU::VReg_128RegClassID),
      GIM_CheckRegBankForClass, /*MI*/0, /*Op*/1, /*RC*/GIMT_Encode2(AMDGPU::VReg_128RegClassID),
      // (bitconvert:{ *:[v2f64] } VReg_128:{ *:[v2i64] }:$src0)  =>  VReg_128:{ *:[v2f64] }:$src0
      GIR_BuildMI, /*InsnID*/0, /*Opcode*/GIMT_Encode2(TargetOpcode::COPY),
      GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/0, // dst
      GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/1, // src0
      GIR_ConstrainOperandRC, /*InsnID*/0, /*Op*/0, GIMT_Encode2(AMDGPU::VReg_128RegClassID),
      GIR_EraseFromParent, /*InsnID*/0,
      // GIR_Coverage, 6005,
      GIR_Done,
    // Label 560: @44707
    GIM_Try, /*On fail goto*//*Label 561*/ GIMT_Encode4(44746), // Rule ID 6007 //
      GIM_CheckType, /*MI*/0, /*Op*/1, /*Type*/GILLT_v4s32,
      GIM_CheckRegBankForClass, /*MI*/0, /*Op*/0, /*RC*/GIMT_Encode2(AMDGPU::VReg_128RegClassID),
      GIM_CheckRegBankForClass, /*MI*/0, /*Op*/1, /*RC*/GIMT_Encode2(AMDGPU::VReg_128RegClassID),
      // (bitconvert:{ *:[v2i64] } VReg_128:{ *:[v4f32] }:$src0)  =>  VReg_128:{ *:[v2i64] }:$src0
      GIR_BuildMI, /*InsnID*/0, /*Opcode*/GIMT_Encode2(TargetOpcode::COPY),
      GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/0, // dst
      GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/1, // src0
      GIR_ConstrainOperandRC, /*InsnID*/0, /*Op*/0, GIMT_Encode2(AMDGPU::VReg_128RegClassID),
      GIR_EraseFromParent, /*InsnID*/0,
      // GIR_Coverage, 6007,
      GIR_Done,
    // Label 561: @44746
    GIM_Try, /*On fail goto*//*Label 562*/ GIMT_Encode4(44785), // Rule ID 6024 //
      GIM_CheckType, /*MI*/0, /*Op*/1, /*Type*/GILLT_v8s16,
      GIM_CheckRegBankForClass, /*MI*/0, /*Op*/0, /*RC*/GIMT_Encode2(AMDGPU::SReg_128RegClassID),
      GIM_CheckRegBankForClass, /*MI*/0, /*Op*/1, /*RC*/GIMT_Encode2(AMDGPU::SReg_128RegClassID),
      // (bitconvert:{ *:[v2i64] } SReg_128:{ *:[v8i16] }:$src0)  =>  SReg_128:{ *:[v2i64] }:$src0
      GIR_BuildMI, /*InsnID*/0, /*Opcode*/GIMT_Encode2(TargetOpcode::COPY),
      GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/0, // dst
      GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/1, // src0
      GIR_ConstrainOperandRC, /*InsnID*/0, /*Op*/0, GIMT_Encode2(AMDGPU::SReg_128RegClassID),
      GIR_EraseFromParent, /*InsnID*/0,
      // GIR_Coverage, 6024,
      GIR_Done,
    // Label 562: @44785
    GIM_Try, /*On fail goto*//*Label 563*/ GIMT_Encode4(44824), // Rule ID 6025 //
      GIM_CheckType, /*MI*/0, /*Op*/1, /*Type*/GILLT_v8s16,
      GIM_CheckRegBankForClass, /*MI*/0, /*Op*/0, /*RC*/GIMT_Encode2(AMDGPU::SReg_128RegClassID),
      GIM_CheckRegBankForClass, /*MI*/0, /*Op*/1, /*RC*/GIMT_Encode2(AMDGPU::SReg_128RegClassID),
      // (bitconvert:{ *:[v2f64] } SReg_128:{ *:[v8i16] }:$src0)  =>  SReg_128:{ *:[v2f64] }:$src0
      GIR_BuildMI, /*InsnID*/0, /*Opcode*/GIMT_Encode2(TargetOpcode::COPY),
      GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/0, // dst
      GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/1, // src0
      GIR_ConstrainOperandRC, /*InsnID*/0, /*Op*/0, GIMT_Encode2(AMDGPU::SReg_128RegClassID),
      GIR_EraseFromParent, /*InsnID*/0,
      // GIR_Coverage, 6025,
      GIR_Done,
    // Label 563: @44824
    GIM_Try, /*On fail goto*//*Label 564*/ GIMT_Encode4(44863), // Rule ID 6026 //
      GIM_CheckType, /*MI*/0, /*Op*/1, /*Type*/GILLT_v8s16,
      GIM_CheckRegBankForClass, /*MI*/0, /*Op*/0, /*RC*/GIMT_Encode2(AMDGPU::SReg_128RegClassID),
      GIM_CheckRegBankForClass, /*MI*/0, /*Op*/1, /*RC*/GIMT_Encode2(AMDGPU::SReg_128RegClassID),
      // (bitconvert:{ *:[v2i64] } SReg_128:{ *:[v8f16] }:$src0)  =>  SReg_128:{ *:[v2i64] }:$src0
      GIR_BuildMI, /*InsnID*/0, /*Opcode*/GIMT_Encode2(TargetOpcode::COPY),
      GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/0, // dst
      GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/1, // src0
      GIR_ConstrainOperandRC, /*InsnID*/0, /*Op*/0, GIMT_Encode2(AMDGPU::SReg_128RegClassID),
      GIR_EraseFromParent, /*InsnID*/0,
      // GIR_Coverage, 6026,
      GIR_Done,
    // Label 564: @44863
    GIM_Try, /*On fail goto*//*Label 565*/ GIMT_Encode4(44902), // Rule ID 6027 //
      GIM_CheckType, /*MI*/0, /*Op*/1, /*Type*/GILLT_v8s16,
      GIM_CheckRegBankForClass, /*MI*/0, /*Op*/0, /*RC*/GIMT_Encode2(AMDGPU::SReg_128RegClassID),
      GIM_CheckRegBankForClass, /*MI*/0, /*Op*/1, /*RC*/GIMT_Encode2(AMDGPU::SReg_128RegClassID),
      // (bitconvert:{ *:[v2f64] } SReg_128:{ *:[v8f16] }:$src0)  =>  SReg_128:{ *:[v2f64] }:$src0
      GIR_BuildMI, /*InsnID*/0, /*Opcode*/GIMT_Encode2(TargetOpcode::COPY),
      GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/0, // dst
      GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/1, // src0
      GIR_ConstrainOperandRC, /*InsnID*/0, /*Op*/0, GIMT_Encode2(AMDGPU::SReg_128RegClassID),
      GIR_EraseFromParent, /*InsnID*/0,
      // GIR_Coverage, 6027,
      GIR_Done,
    // Label 565: @44902
    GIM_Try, /*On fail goto*//*Label 566*/ GIMT_Encode4(44941), // Rule ID 6044 //
      GIM_CheckType, /*MI*/0, /*Op*/1, /*Type*/GILLT_v8s16,
      GIM_CheckRegBankForClass, /*MI*/0, /*Op*/0, /*RC*/GIMT_Encode2(AMDGPU::SReg_128RegClassID),
      GIM_CheckRegBankForClass, /*MI*/0, /*Op*/1, /*RC*/GIMT_Encode2(AMDGPU::SReg_128RegClassID),
      // (bitconvert:{ *:[v2f64] } SReg_128:{ *:[v8bf16] }:$src0)  =>  SReg_128:{ *:[v2f64] }:$src0
      GIR_BuildMI, /*InsnID*/0, /*Opcode*/GIMT_Encode2(TargetOpcode::COPY),
      GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/0, // dst
      GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/1, // src0
      GIR_ConstrainOperandRC, /*InsnID*/0, /*Op*/0, GIMT_Encode2(AMDGPU::SReg_128RegClassID),
      GIR_EraseFromParent, /*InsnID*/0,
      // GIR_Coverage, 6044,
      GIR_Done,
    // Label 566: @44941
    GIM_Try, /*On fail goto*//*Label 567*/ GIMT_Encode4(44980), // Rule ID 6046 //
      GIM_CheckType, /*MI*/0, /*Op*/1, /*Type*/GILLT_v8s16,
      GIM_CheckRegBankForClass, /*MI*/0, /*Op*/0, /*RC*/GIMT_Encode2(AMDGPU::VReg_128RegClassID),
      GIM_CheckRegBankForClass, /*MI*/0, /*Op*/1, /*RC*/GIMT_Encode2(AMDGPU::VReg_128RegClassID),
      // (bitconvert:{ *:[v2f64] } VReg_128:{ *:[v8bf16] }:$src0)  =>  VReg_128:{ *:[v2f64] }:$src0
      GIR_BuildMI, /*InsnID*/0, /*Opcode*/GIMT_Encode2(TargetOpcode::COPY),
      GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/0, // dst
      GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/1, // src0
      GIR_ConstrainOperandRC, /*InsnID*/0, /*Op*/0, GIMT_Encode2(AMDGPU::VReg_128RegClassID),
      GIR_EraseFromParent, /*InsnID*/0,
      // GIR_Coverage, 6046,
      GIR_Done,
    // Label 567: @44980
    GIM_Try, /*On fail goto*//*Label 568*/ GIMT_Encode4(45019), // Rule ID 6048 //
      GIM_CheckType, /*MI*/0, /*Op*/1, /*Type*/GILLT_v8s16,
      GIM_CheckRegBankForClass, /*MI*/0, /*Op*/0, /*RC*/GIMT_Encode2(AMDGPU::SReg_128RegClassID),
      GIM_CheckRegBankForClass, /*MI*/0, /*Op*/1, /*RC*/GIMT_Encode2(AMDGPU::SReg_128RegClassID),
      // (bitconvert:{ *:[v2i64] } SReg_128:{ *:[v8bf16] }:$src0)  =>  SReg_128:{ *:[v2i64] }:$src0
      GIR_BuildMI, /*InsnID*/0, /*Opcode*/GIMT_Encode2(TargetOpcode::COPY),
      GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/0, // dst
      GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/1, // src0
      GIR_ConstrainOperandRC, /*InsnID*/0, /*Op*/0, GIMT_Encode2(AMDGPU::SReg_128RegClassID),
      GIR_EraseFromParent, /*InsnID*/0,
      // GIR_Coverage, 6048,
      GIR_Done,
    // Label 568: @45019
    GIM_Try, /*On fail goto*//*Label 569*/ GIMT_Encode4(45058), // Rule ID 6050 //
      GIM_CheckType, /*MI*/0, /*Op*/1, /*Type*/GILLT_v8s16,
      GIM_CheckRegBankForClass, /*MI*/0, /*Op*/0, /*RC*/GIMT_Encode2(AMDGPU::VReg_128RegClassID),
      GIM_CheckRegBankForClass, /*MI*/0, /*Op*/1, /*RC*/GIMT_Encode2(AMDGPU::VReg_128RegClassID),
      // (bitconvert:{ *:[v2i64] } VReg_128:{ *:[v8bf16] }:$src0)  =>  VReg_128:{ *:[v2i64] }:$src0
      GIR_BuildMI, /*InsnID*/0, /*Opcode*/GIMT_Encode2(TargetOpcode::COPY),
      GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/0, // dst
      GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/1, // src0
      GIR_ConstrainOperandRC, /*InsnID*/0, /*Op*/0, GIMT_Encode2(AMDGPU::VReg_128RegClassID),
      GIR_EraseFromParent, /*InsnID*/0,
      // GIR_Coverage, 6050,
      GIR_Done,
    // Label 569: @45058
    GIM_Reject,
    // Label 467: @45059
    GIM_Try, /*On fail goto*//*Label 570*/ GIMT_Encode4(45129),
      GIM_CheckType, /*MI*/0, /*Op*/1, /*Type*/GILLT_v3s32,
      GIM_CheckRegBankForClass, /*MI*/0, /*Op*/0, /*RC*/GIMT_Encode2(AMDGPU::SGPR_96RegClassID),
      GIM_CheckRegBankForClass, /*MI*/0, /*Op*/1, /*RC*/GIMT_Encode2(AMDGPU::SGPR_96RegClassID),
      GIM_Try, /*On fail goto*//*Label 571*/ GIMT_Encode4(45103), // Rule ID 5996 //
        // (bitconvert:{ *:[v3i32] } SGPR_96:{ *:[v3f32] }:$src0)  =>  SGPR_96:{ *:[v3i32] }:$src0
        GIR_BuildMI, /*InsnID*/0, /*Opcode*/GIMT_Encode2(TargetOpcode::COPY),
        GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/0, // dst
        GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/1, // src0
        GIR_ConstrainOperandRC, /*InsnID*/0, /*Op*/0, GIMT_Encode2(AMDGPU::SGPR_96RegClassID),
        GIR_EraseFromParent, /*InsnID*/0,
        // GIR_Coverage, 5996,
        GIR_Done,
      // Label 571: @45103
      GIM_Try, /*On fail goto*//*Label 572*/ GIMT_Encode4(45128), // Rule ID 5997 //
        // (bitconvert:{ *:[v3f32] } SGPR_96:{ *:[v3i32] }:$src0)  =>  SGPR_96:{ *:[v3f32] }:$src0
        GIR_BuildMI, /*InsnID*/0, /*Opcode*/GIMT_Encode2(TargetOpcode::COPY),
        GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/0, // dst
        GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/1, // src0
        GIR_ConstrainOperandRC, /*InsnID*/0, /*Op*/0, GIMT_Encode2(AMDGPU::SGPR_96RegClassID),
        GIR_EraseFromParent, /*InsnID*/0,
        // GIR_Coverage, 5997,
        GIR_Done,
      // Label 572: @45128
      GIM_Reject,
    // Label 570: @45129
    GIM_Reject,
    // Label 468: @45130
    GIM_Try, /*On fail goto*//*Label 573*/ GIMT_Encode4(45169), // Rule ID 6060 //
      GIM_CheckType, /*MI*/0, /*Op*/1, /*Type*/GILLT_v3s64,
      GIM_CheckRegBankForClass, /*MI*/0, /*Op*/0, /*RC*/GIMT_Encode2(AMDGPU::VReg_192RegClassID),
      GIM_CheckRegBankForClass, /*MI*/0, /*Op*/1, /*RC*/GIMT_Encode2(AMDGPU::VReg_192RegClassID),
      // (bitconvert:{ *:[v3i64] } VReg_192:{ *:[v3f64] }:$src0)  =>  VReg_192:{ *:[v3i64] }:$src0
      GIR_BuildMI, /*InsnID*/0, /*Opcode*/GIMT_Encode2(TargetOpcode::COPY),
      GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/0, // dst
      GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/1, // src0
      GIR_ConstrainOperandRC, /*InsnID*/0, /*Op*/0, GIMT_Encode2(AMDGPU::VReg_192RegClassID),
      GIR_EraseFromParent, /*InsnID*/0,
      // GIR_Coverage, 6060,
      GIR_Done,
    // Label 573: @45169
    GIM_Try, /*On fail goto*//*Label 574*/ GIMT_Encode4(45208), // Rule ID 6061 //
      GIM_CheckType, /*MI*/0, /*Op*/1, /*Type*/GILLT_v3s64,
      GIM_CheckRegBankForClass, /*MI*/0, /*Op*/0, /*RC*/GIMT_Encode2(AMDGPU::VReg_192RegClassID),
      GIM_CheckRegBankForClass, /*MI*/0, /*Op*/1, /*RC*/GIMT_Encode2(AMDGPU::VReg_192RegClassID),
      // (bitconvert:{ *:[v3f64] } VReg_192:{ *:[v3i64] }:$src0)  =>  VReg_192:{ *:[v3f64] }:$src0
      GIR_BuildMI, /*InsnID*/0, /*Opcode*/GIMT_Encode2(TargetOpcode::COPY),
      GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/0, // dst
      GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/1, // src0
      GIR_ConstrainOperandRC, /*InsnID*/0, /*Op*/0, GIMT_Encode2(AMDGPU::VReg_192RegClassID),
      GIR_EraseFromParent, /*InsnID*/0,
      // GIR_Coverage, 6061,
      GIR_Done,
    // Label 574: @45208
    GIM_Try, /*On fail goto*//*Label 575*/ GIMT_Encode4(45247), // Rule ID 6062 //
      GIM_CheckType, /*MI*/0, /*Op*/1, /*Type*/GILLT_v6s32,
      GIM_CheckRegBankForClass, /*MI*/0, /*Op*/0, /*RC*/GIMT_Encode2(AMDGPU::VReg_192RegClassID),
      GIM_CheckRegBankForClass, /*MI*/0, /*Op*/1, /*RC*/GIMT_Encode2(AMDGPU::VReg_192RegClassID),
      // (bitconvert:{ *:[v3i64] } VReg_192:{ *:[v6i32] }:$src0)  =>  VReg_192:{ *:[v3i64] }:$src0
      GIR_BuildMI, /*InsnID*/0, /*Opcode*/GIMT_Encode2(TargetOpcode::COPY),
      GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/0, // dst
      GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/1, // src0
      GIR_ConstrainOperandRC, /*InsnID*/0, /*Op*/0, GIMT_Encode2(AMDGPU::VReg_192RegClassID),
      GIR_EraseFromParent, /*InsnID*/0,
      // GIR_Coverage, 6062,
      GIR_Done,
    // Label 575: @45247
    GIM_Try, /*On fail goto*//*Label 576*/ GIMT_Encode4(45286), // Rule ID 6063 //
      GIM_CheckType, /*MI*/0, /*Op*/1, /*Type*/GILLT_v6s32,
      GIM_CheckRegBankForClass, /*MI*/0, /*Op*/0, /*RC*/GIMT_Encode2(AMDGPU::VReg_192RegClassID),
      GIM_CheckRegBankForClass, /*MI*/0, /*Op*/1, /*RC*/GIMT_Encode2(AMDGPU::VReg_192RegClassID),
      // (bitconvert:{ *:[v3i64] } VReg_192:{ *:[v6f32] }:$src0)  =>  VReg_192:{ *:[v3i64] }:$src0
      GIR_BuildMI, /*InsnID*/0, /*Opcode*/GIMT_Encode2(TargetOpcode::COPY),
      GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/0, // dst
      GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/1, // src0
      GIR_ConstrainOperandRC, /*InsnID*/0, /*Op*/0, GIMT_Encode2(AMDGPU::VReg_192RegClassID),
      GIR_EraseFromParent, /*InsnID*/0,
      // GIR_Coverage, 6063,
      GIR_Done,
    // Label 576: @45286
    GIM_Try, /*On fail goto*//*Label 577*/ GIMT_Encode4(45325), // Rule ID 6064 //
      GIM_CheckType, /*MI*/0, /*Op*/1, /*Type*/GILLT_v6s32,
      GIM_CheckRegBankForClass, /*MI*/0, /*Op*/0, /*RC*/GIMT_Encode2(AMDGPU::VReg_192RegClassID),
      GIM_CheckRegBankForClass, /*MI*/0, /*Op*/1, /*RC*/GIMT_Encode2(AMDGPU::VReg_192RegClassID),
      // (bitconvert:{ *:[v3f64] } VReg_192:{ *:[v6i32] }:$src0)  =>  VReg_192:{ *:[v3f64] }:$src0
      GIR_BuildMI, /*InsnID*/0, /*Opcode*/GIMT_Encode2(TargetOpcode::COPY),
      GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/0, // dst
      GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/1, // src0
      GIR_ConstrainOperandRC, /*InsnID*/0, /*Op*/0, GIMT_Encode2(AMDGPU::VReg_192RegClassID),
      GIR_EraseFromParent, /*InsnID*/0,
      // GIR_Coverage, 6064,
      GIR_Done,
    // Label 577: @45325
    GIM_Try, /*On fail goto*//*Label 578*/ GIMT_Encode4(45364), // Rule ID 6065 //
      GIM_CheckType, /*MI*/0, /*Op*/1, /*Type*/GILLT_v6s32,
      GIM_CheckRegBankForClass, /*MI*/0, /*Op*/0, /*RC*/GIMT_Encode2(AMDGPU::VReg_192RegClassID),
      GIM_CheckRegBankForClass, /*MI*/0, /*Op*/1, /*RC*/GIMT_Encode2(AMDGPU::VReg_192RegClassID),
      // (bitconvert:{ *:[v3f64] } VReg_192:{ *:[v6f32] }:$src0)  =>  VReg_192:{ *:[v3f64] }:$src0
      GIR_BuildMI, /*InsnID*/0, /*Opcode*/GIMT_Encode2(TargetOpcode::COPY),
      GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/0, // dst
      GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/1, // src0
      GIR_ConstrainOperandRC, /*InsnID*/0, /*Op*/0, GIMT_Encode2(AMDGPU::VReg_192RegClassID),
      GIR_EraseFromParent, /*InsnID*/0,
      // GIR_Coverage, 6065,
      GIR_Done,
    // Label 578: @45364
    GIM_Reject,
    // Label 469: @45365
    GIM_Try, /*On fail goto*//*Label 579*/ GIMT_Encode4(45404), // Rule ID 5963 //
      GIM_CheckType, /*MI*/0, /*Op*/1, /*Type*/GILLT_v4s16,
      GIM_CheckRegBankForClass, /*MI*/0, /*Op*/0, /*RC*/GIMT_Encode2(AMDGPU::VReg_64RegClassID),
      GIM_CheckRegBankForClass, /*MI*/0, /*Op*/1, /*RC*/GIMT_Encode2(AMDGPU::VReg_64RegClassID),
      // (bitconvert:{ *:[v4i16] } VReg_64:{ *:[v4f16] }:$src0)  =>  VReg_64:{ *:[v4i16] }:$src0
      GIR_BuildMI, /*InsnID*/0, /*Opcode*/GIMT_Encode2(TargetOpcode::COPY),
      GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/0, // dst
      GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/1, // src0
      GIR_ConstrainOperandRC, /*InsnID*/0, /*Op*/0, GIMT_Encode2(AMDGPU::VReg_64RegClassID),
      GIR_EraseFromParent, /*InsnID*/0,
      // GIR_Coverage, 5963,
      GIR_Done,
    // Label 579: @45404
    GIM_Try, /*On fail goto*//*Label 580*/ GIMT_Encode4(45443), // Rule ID 5964 //
      GIM_CheckType, /*MI*/0, /*Op*/1, /*Type*/GILLT_v4s16,
      GIM_CheckRegBankForClass, /*MI*/0, /*Op*/0, /*RC*/GIMT_Encode2(AMDGPU::VReg_64RegClassID),
      GIM_CheckRegBankForClass, /*MI*/0, /*Op*/1, /*RC*/GIMT_Encode2(AMDGPU::VReg_64RegClassID),
      // (bitconvert:{ *:[v4f16] } VReg_64:{ *:[v4i16] }:$src0)  =>  VReg_64:{ *:[v4f16] }:$src0
      GIR_BuildMI, /*InsnID*/0, /*Opcode*/GIMT_Encode2(TargetOpcode::COPY),
      GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/0, // dst
      GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/1, // src0
      GIR_ConstrainOperandRC, /*InsnID*/0, /*Op*/0, GIMT_Encode2(AMDGPU::VReg_64RegClassID),
      GIR_EraseFromParent, /*InsnID*/0,
      // GIR_Coverage, 5964,
      GIR_Done,
    // Label 580: @45443
    GIM_Try, /*On fail goto*//*Label 581*/ GIMT_Encode4(45482), // Rule ID 5965 //
      GIM_CheckType, /*MI*/0, /*Op*/1, /*Type*/GILLT_v2s32,
      GIM_CheckRegBankForClass, /*MI*/0, /*Op*/0, /*RC*/GIMT_Encode2(AMDGPU::VReg_64RegClassID),
      GIM_CheckRegBankForClass, /*MI*/0, /*Op*/1, /*RC*/GIMT_Encode2(AMDGPU::VReg_64RegClassID),
      // (bitconvert:{ *:[v4bf16] } VReg_64:{ *:[v2i32] }:$src0)  =>  VReg_64:{ *:[v4bf16] }:$src0
      GIR_BuildMI, /*InsnID*/0, /*Opcode*/GIMT_Encode2(TargetOpcode::COPY),
      GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/0, // dst
      GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/1, // src0
      GIR_ConstrainOperandRC, /*InsnID*/0, /*Op*/0, GIMT_Encode2(AMDGPU::VReg_64RegClassID),
      GIR_EraseFromParent, /*InsnID*/0,
      // GIR_Coverage, 5965,
      GIR_Done,
    // Label 581: @45482
    GIM_Try, /*On fail goto*//*Label 582*/ GIMT_Encode4(45521), // Rule ID 5967 //
      GIM_CheckType, /*MI*/0, /*Op*/1, /*Type*/GILLT_s64,
      GIM_CheckRegBankForClass, /*MI*/0, /*Op*/0, /*RC*/GIMT_Encode2(AMDGPU::VReg_64RegClassID),
      GIM_CheckRegBankForClass, /*MI*/0, /*Op*/1, /*RC*/GIMT_Encode2(AMDGPU::VReg_64RegClassID),
      // (bitconvert:{ *:[v4bf16] } VReg_64:{ *:[i64] }:$src0)  =>  VReg_64:{ *:[v4bf16] }:$src0
      GIR_BuildMI, /*InsnID*/0, /*Opcode*/GIMT_Encode2(TargetOpcode::COPY),
      GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/0, // dst
      GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/1, // src0
      GIR_ConstrainOperandRC, /*InsnID*/0, /*Op*/0, GIMT_Encode2(AMDGPU::VReg_64RegClassID),
      GIR_EraseFromParent, /*InsnID*/0,
      // GIR_Coverage, 5967,
      GIR_Done,
    // Label 582: @45521
    GIM_Try, /*On fail goto*//*Label 583*/ GIMT_Encode4(45560), // Rule ID 5969 //
      GIM_CheckType, /*MI*/0, /*Op*/1, /*Type*/GILLT_v4s16,
      GIM_CheckRegBankForClass, /*MI*/0, /*Op*/0, /*RC*/GIMT_Encode2(AMDGPU::VReg_64RegClassID),
      GIM_CheckRegBankForClass, /*MI*/0, /*Op*/1, /*RC*/GIMT_Encode2(AMDGPU::VReg_64RegClassID),
      // (bitconvert:{ *:[v4bf16] } VReg_64:{ *:[v4i16] }:$src0)  =>  VReg_64:{ *:[v4bf16] }:$src0
      GIR_BuildMI, /*InsnID*/0, /*Opcode*/GIMT_Encode2(TargetOpcode::COPY),
      GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/0, // dst
      GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/1, // src0
      GIR_ConstrainOperandRC, /*InsnID*/0, /*Op*/0, GIMT_Encode2(AMDGPU::VReg_64RegClassID),
      GIR_EraseFromParent, /*InsnID*/0,
      // GIR_Coverage, 5969,
      GIR_Done,
    // Label 583: @45560
    GIM_Try, /*On fail goto*//*Label 584*/ GIMT_Encode4(45599), // Rule ID 5970 //
      GIM_CheckType, /*MI*/0, /*Op*/1, /*Type*/GILLT_v4s16,
      GIM_CheckRegBankForClass, /*MI*/0, /*Op*/0, /*RC*/GIMT_Encode2(AMDGPU::VReg_64RegClassID),
      GIM_CheckRegBankForClass, /*MI*/0, /*Op*/1, /*RC*/GIMT_Encode2(AMDGPU::VReg_64RegClassID),
      // (bitconvert:{ *:[v4i16] } VReg_64:{ *:[v4bf16] }:$src0)  =>  VReg_64:{ *:[v4i16] }:$src0
      GIR_BuildMI, /*InsnID*/0, /*Opcode*/GIMT_Encode2(TargetOpcode::COPY),
      GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/0, // dst
      GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/1, // src0
      GIR_ConstrainOperandRC, /*InsnID*/0, /*Op*/0, GIMT_Encode2(AMDGPU::VReg_64RegClassID),
      GIR_EraseFromParent, /*InsnID*/0,
      // GIR_Coverage, 5970,
      GIR_Done,
    // Label 584: @45599
    GIM_Try, /*On fail goto*//*Label 585*/ GIMT_Encode4(45638), // Rule ID 5971 //
      GIM_CheckType, /*MI*/0, /*Op*/1, /*Type*/GILLT_v4s16,
      GIM_CheckRegBankForClass, /*MI*/0, /*Op*/0, /*RC*/GIMT_Encode2(AMDGPU::VReg_64RegClassID),
      GIM_CheckRegBankForClass, /*MI*/0, /*Op*/1, /*RC*/GIMT_Encode2(AMDGPU::VReg_64RegClassID),
      // (bitconvert:{ *:[v4bf16] } VReg_64:{ *:[v4f16] }:$src0)  =>  VReg_64:{ *:[v4bf16] }:$src0
      GIR_BuildMI, /*InsnID*/0, /*Opcode*/GIMT_Encode2(TargetOpcode::COPY),
      GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/0, // dst
      GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/1, // src0
      GIR_ConstrainOperandRC, /*InsnID*/0, /*Op*/0, GIMT_Encode2(AMDGPU::VReg_64RegClassID),
      GIR_EraseFromParent, /*InsnID*/0,
      // GIR_Coverage, 5971,
      GIR_Done,
    // Label 585: @45638
    GIM_Try, /*On fail goto*//*Label 586*/ GIMT_Encode4(45677), // Rule ID 5972 //
      GIM_CheckType, /*MI*/0, /*Op*/1, /*Type*/GILLT_v4s16,
      GIM_CheckRegBankForClass, /*MI*/0, /*Op*/0, /*RC*/GIMT_Encode2(AMDGPU::VReg_64RegClassID),
      GIM_CheckRegBankForClass, /*MI*/0, /*Op*/1, /*RC*/GIMT_Encode2(AMDGPU::VReg_64RegClassID),
      // (bitconvert:{ *:[v4f16] } VReg_64:{ *:[v4bf16] }:$src0)  =>  VReg_64:{ *:[v4f16] }:$src0
      GIR_BuildMI, /*InsnID*/0, /*Opcode*/GIMT_Encode2(TargetOpcode::COPY),
      GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/0, // dst
      GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/1, // src0
      GIR_ConstrainOperandRC, /*InsnID*/0, /*Op*/0, GIMT_Encode2(AMDGPU::VReg_64RegClassID),
      GIR_EraseFromParent, /*InsnID*/0,
      // GIR_Coverage, 5972,
      GIR_Done,
    // Label 586: @45677
    GIM_Try, /*On fail goto*//*Label 587*/ GIMT_Encode4(45716), // Rule ID 5973 //
      GIM_CheckType, /*MI*/0, /*Op*/1, /*Type*/GILLT_v2s32,
      GIM_CheckRegBankForClass, /*MI*/0, /*Op*/0, /*RC*/GIMT_Encode2(AMDGPU::VReg_64RegClassID),
      GIM_CheckRegBankForClass, /*MI*/0, /*Op*/1, /*RC*/GIMT_Encode2(AMDGPU::VReg_64RegClassID),
      // (bitconvert:{ *:[v4bf16] } VReg_64:{ *:[v2f32] }:$src0)  =>  VReg_64:{ *:[v4bf16] }:$src0
      GIR_BuildMI, /*InsnID*/0, /*Opcode*/GIMT_Encode2(TargetOpcode::COPY),
      GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/0, // dst
      GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/1, // src0
      GIR_ConstrainOperandRC, /*InsnID*/0, /*Op*/0, GIMT_Encode2(AMDGPU::VReg_64RegClassID),
      GIR_EraseFromParent, /*InsnID*/0,
      // GIR_Coverage, 5973,
      GIR_Done,
    // Label 587: @45716
    GIM_Try, /*On fail goto*//*Label 588*/ GIMT_Encode4(45755), // Rule ID 5975 //
      GIM_CheckType, /*MI*/0, /*Op*/1, /*Type*/GILLT_s64,
      GIM_CheckRegBankForClass, /*MI*/0, /*Op*/0, /*RC*/GIMT_Encode2(AMDGPU::VReg_64RegClassID),
      GIM_CheckRegBankForClass, /*MI*/0, /*Op*/1, /*RC*/GIMT_Encode2(AMDGPU::VReg_64RegClassID),
      // (bitconvert:{ *:[v4bf16] } VReg_64:{ *:[f64] }:$src0)  =>  VReg_64:{ *:[v4bf16] }:$src0
      GIR_BuildMI, /*InsnID*/0, /*Opcode*/GIMT_Encode2(TargetOpcode::COPY),
      GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/0, // dst
      GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/1, // src0
      GIR_ConstrainOperandRC, /*InsnID*/0, /*Op*/0, GIMT_Encode2(AMDGPU::VReg_64RegClassID),
      GIR_EraseFromParent, /*InsnID*/0,
      // GIR_Coverage, 5975,
      GIR_Done,
    // Label 588: @45755
    GIM_Try, /*On fail goto*//*Label 589*/ GIMT_Encode4(45794), // Rule ID 5978 //
      GIM_CheckType, /*MI*/0, /*Op*/1, /*Type*/GILLT_v2s32,
      GIM_CheckRegBankForClass, /*MI*/0, /*Op*/0, /*RC*/GIMT_Encode2(AMDGPU::VReg_64RegClassID),
      GIM_CheckRegBankForClass, /*MI*/0, /*Op*/1, /*RC*/GIMT_Encode2(AMDGPU::VReg_64RegClassID),
      // (bitconvert:{ *:[v4f16] } VReg_64:{ *:[v2i32] }:$src0)  =>  VReg_64:{ *:[v4f16] }:$src0
      GIR_BuildMI, /*InsnID*/0, /*Opcode*/GIMT_Encode2(TargetOpcode::COPY),
      GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/0, // dst
      GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/1, // src0
      GIR_ConstrainOperandRC, /*InsnID*/0, /*Op*/0, GIMT_Encode2(AMDGPU::VReg_64RegClassID),
      GIR_EraseFromParent, /*InsnID*/0,
      // GIR_Coverage, 5978,
      GIR_Done,
    // Label 589: @45794
    GIM_Try, /*On fail goto*//*Label 590*/ GIMT_Encode4(45833), // Rule ID 5981 //
      GIM_CheckType, /*MI*/0, /*Op*/1, /*Type*/GILLT_v2s32,
      GIM_CheckRegBankForClass, /*MI*/0, /*Op*/0, /*RC*/GIMT_Encode2(AMDGPU::VReg_64RegClassID),
      GIM_CheckRegBankForClass, /*MI*/0, /*Op*/1, /*RC*/GIMT_Encode2(AMDGPU::VReg_64RegClassID),
      // (bitconvert:{ *:[v4i16] } VReg_64:{ *:[v2i32] }:$src0)  =>  VReg_64:{ *:[v4i16] }:$src0
      GIR_BuildMI, /*InsnID*/0, /*Opcode*/GIMT_Encode2(TargetOpcode::COPY),
      GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/0, // dst
      GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/1, // src0
      GIR_ConstrainOperandRC, /*InsnID*/0, /*Op*/0, GIMT_Encode2(AMDGPU::VReg_64RegClassID),
      GIR_EraseFromParent, /*InsnID*/0,
      // GIR_Coverage, 5981,
      GIR_Done,
    // Label 590: @45833
    GIM_Try, /*On fail goto*//*Label 591*/ GIMT_Encode4(45872), // Rule ID 5983 //
      GIM_CheckType, /*MI*/0, /*Op*/1, /*Type*/GILLT_v2s32,
      GIM_CheckRegBankForClass, /*MI*/0, /*Op*/0, /*RC*/GIMT_Encode2(AMDGPU::VReg_64RegClassID),
      GIM_CheckRegBankForClass, /*MI*/0, /*Op*/1, /*RC*/GIMT_Encode2(AMDGPU::VReg_64RegClassID),
      // (bitconvert:{ *:[v4f16] } VReg_64:{ *:[v2f32] }:$src0)  =>  VReg_64:{ *:[v4f16] }:$src0
      GIR_BuildMI, /*InsnID*/0, /*Opcode*/GIMT_Encode2(TargetOpcode::COPY),
      GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/0, // dst
      GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/1, // src0
      GIR_ConstrainOperandRC, /*InsnID*/0, /*Op*/0, GIMT_Encode2(AMDGPU::VReg_64RegClassID),
      GIR_EraseFromParent, /*InsnID*/0,
      // GIR_Coverage, 5983,
      GIR_Done,
    // Label 591: @45872
    GIM_Try, /*On fail goto*//*Label 592*/ GIMT_Encode4(45911), // Rule ID 5985 //
      GIM_CheckType, /*MI*/0, /*Op*/1, /*Type*/GILLT_v2s32,
      GIM_CheckRegBankForClass, /*MI*/0, /*Op*/0, /*RC*/GIMT_Encode2(AMDGPU::VReg_64RegClassID),
      GIM_CheckRegBankForClass, /*MI*/0, /*Op*/1, /*RC*/GIMT_Encode2(AMDGPU::VReg_64RegClassID),
      // (bitconvert:{ *:[v4i16] } VReg_64:{ *:[v2f32] }:$src0)  =>  VReg_64:{ *:[v4i16] }:$src0
      GIR_BuildMI, /*InsnID*/0, /*Opcode*/GIMT_Encode2(TargetOpcode::COPY),
      GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/0, // dst
      GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/1, // src0
      GIR_ConstrainOperandRC, /*InsnID*/0, /*Op*/0, GIMT_Encode2(AMDGPU::VReg_64RegClassID),
      GIR_EraseFromParent, /*InsnID*/0,
      // GIR_Coverage, 5985,
      GIR_Done,
    // Label 592: @45911
    GIM_Try, /*On fail goto*//*Label 593*/ GIMT_Encode4(45950), // Rule ID 5986 //
      GIM_CheckType, /*MI*/0, /*Op*/1, /*Type*/GILLT_s64,
      GIM_CheckRegBankForClass, /*MI*/0, /*Op*/0, /*RC*/GIMT_Encode2(AMDGPU::VReg_64RegClassID),
      GIM_CheckRegBankForClass, /*MI*/0, /*Op*/1, /*RC*/GIMT_Encode2(AMDGPU::VReg_64RegClassID),
      // (bitconvert:{ *:[v4i16] } VReg_64:{ *:[f64] }:$src0)  =>  VReg_64:{ *:[v4i16] }:$src0
      GIR_BuildMI, /*InsnID*/0, /*Opcode*/GIMT_Encode2(TargetOpcode::COPY),
      GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/0, // dst
      GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/1, // src0
      GIR_ConstrainOperandRC, /*InsnID*/0, /*Op*/0, GIMT_Encode2(AMDGPU::VReg_64RegClassID),
      GIR_EraseFromParent, /*InsnID*/0,
      // GIR_Coverage, 5986,
      GIR_Done,
    // Label 593: @45950
    GIM_Try, /*On fail goto*//*Label 594*/ GIMT_Encode4(45989), // Rule ID 5987 //
      GIM_CheckType, /*MI*/0, /*Op*/1, /*Type*/GILLT_s64,
      GIM_CheckRegBankForClass, /*MI*/0, /*Op*/0, /*RC*/GIMT_Encode2(AMDGPU::VReg_64RegClassID),
      GIM_CheckRegBankForClass, /*MI*/0, /*Op*/1, /*RC*/GIMT_Encode2(AMDGPU::VReg_64RegClassID),
      // (bitconvert:{ *:[v4f16] } VReg_64:{ *:[f64] }:$src0)  =>  VReg_64:{ *:[v4f16] }:$src0
      GIR_BuildMI, /*InsnID*/0, /*Opcode*/GIMT_Encode2(TargetOpcode::COPY),
      GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/0, // dst
      GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/1, // src0
      GIR_ConstrainOperandRC, /*InsnID*/0, /*Op*/0, GIMT_Encode2(AMDGPU::VReg_64RegClassID),
      GIR_EraseFromParent, /*InsnID*/0,
      // GIR_Coverage, 5987,
      GIR_Done,
    // Label 594: @45989
    GIM_Try, /*On fail goto*//*Label 595*/ GIMT_Encode4(46028), // Rule ID 5990 //
      GIM_CheckType, /*MI*/0, /*Op*/1, /*Type*/GILLT_s64,
      GIM_CheckRegBankForClass, /*MI*/0, /*Op*/0, /*RC*/GIMT_Encode2(AMDGPU::VReg_64RegClassID),
      GIM_CheckRegBankForClass, /*MI*/0, /*Op*/1, /*RC*/GIMT_Encode2(AMDGPU::VReg_64RegClassID),
      // (bitconvert:{ *:[v4i16] } VReg_64:{ *:[i64] }:$src0)  =>  VReg_64:{ *:[v4i16] }:$src0
      GIR_BuildMI, /*InsnID*/0, /*Opcode*/GIMT_Encode2(TargetOpcode::COPY),
      GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/0, // dst
      GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/1, // src0
      GIR_ConstrainOperandRC, /*InsnID*/0, /*Op*/0, GIMT_Encode2(AMDGPU::VReg_64RegClassID),
      GIR_EraseFromParent, /*InsnID*/0,
      // GIR_Coverage, 5990,
      GIR_Done,
    // Label 595: @46028
    GIM_Try, /*On fail goto*//*Label 596*/ GIMT_Encode4(46067), // Rule ID 5991 //
      GIM_CheckType, /*MI*/0, /*Op*/1, /*Type*/GILLT_s64,
      GIM_CheckRegBankForClass, /*MI*/0, /*Op*/0, /*RC*/GIMT_Encode2(AMDGPU::VReg_64RegClassID),
      GIM_CheckRegBankForClass, /*MI*/0, /*Op*/1, /*RC*/GIMT_Encode2(AMDGPU::VReg_64RegClassID),
      // (bitconvert:{ *:[v4f16] } VReg_64:{ *:[i64] }:$src0)  =>  VReg_64:{ *:[v4f16] }:$src0
      GIR_BuildMI, /*InsnID*/0, /*Opcode*/GIMT_Encode2(TargetOpcode::COPY),
      GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/0, // dst
      GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/1, // src0
      GIR_ConstrainOperandRC, /*InsnID*/0, /*Op*/0, GIMT_Encode2(AMDGPU::VReg_64RegClassID),
      GIR_EraseFromParent, /*InsnID*/0,
      // GIR_Coverage, 5991,
      GIR_Done,
    // Label 596: @46067
    GIM_Reject,
    // Label 470: @46068
    GIM_Try, /*On fail goto*//*Label 597*/ GIMT_Encode4(46107), // Rule ID 5994 //
      GIM_CheckType, /*MI*/0, /*Op*/1, /*Type*/GILLT_v4s32,
      GIM_CheckRegBankForClass, /*MI*/0, /*Op*/0, /*RC*/GIMT_Encode2(AMDGPU::VReg_128RegClassID),
      GIM_CheckRegBankForClass, /*MI*/0, /*Op*/1, /*RC*/GIMT_Encode2(AMDGPU::VReg_128RegClassID),
      // (bitconvert:{ *:[v4i32] } VReg_128:{ *:[v4f32] }:$src0)  =>  VReg_128:{ *:[v4i32] }:$src0
      GIR_BuildMI, /*InsnID*/0, /*Opcode*/GIMT_Encode2(TargetOpcode::COPY),
      GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/0, // dst
      GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/1, // src0
      GIR_ConstrainOperandRC, /*InsnID*/0, /*Op*/0, GIMT_Encode2(AMDGPU::VReg_128RegClassID),
      GIR_EraseFromParent, /*InsnID*/0,
      // GIR_Coverage, 5994,
      GIR_Done,
    // Label 597: @46107
    GIM_Try, /*On fail goto*//*Label 598*/ GIMT_Encode4(46146), // Rule ID 5995 //
      GIM_CheckType, /*MI*/0, /*Op*/1, /*Type*/GILLT_v4s32,
      GIM_CheckRegBankForClass, /*MI*/0, /*Op*/0, /*RC*/GIMT_Encode2(AMDGPU::VReg_128RegClassID),
      GIM_CheckRegBankForClass, /*MI*/0, /*Op*/1, /*RC*/GIMT_Encode2(AMDGPU::VReg_128RegClassID),
      // (bitconvert:{ *:[v4f32] } VReg_128:{ *:[v4i32] }:$src0)  =>  VReg_128:{ *:[v4f32] }:$src0
      GIR_BuildMI, /*InsnID*/0, /*Opcode*/GIMT_Encode2(TargetOpcode::COPY),
      GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/0, // dst
      GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/1, // src0
      GIR_ConstrainOperandRC, /*InsnID*/0, /*Op*/0, GIMT_Encode2(AMDGPU::VReg_128RegClassID),
      GIR_EraseFromParent, /*InsnID*/0,
      // GIR_Coverage, 5995,
      GIR_Done,
    // Label 598: @46146
    GIM_Try, /*On fail goto*//*Label 599*/ GIMT_Encode4(46185), // Rule ID 5999 //
      GIM_CheckType, /*MI*/0, /*Op*/1, /*Type*/GILLT_v2s64,
      GIM_CheckRegBankForClass, /*MI*/0, /*Op*/0, /*RC*/GIMT_Encode2(AMDGPU::SReg_128RegClassID),
      GIM_CheckRegBankForClass, /*MI*/0, /*Op*/1, /*RC*/GIMT_Encode2(AMDGPU::SReg_128RegClassID),
      // (bitconvert:{ *:[v4i32] } SReg_128:{ *:[v2i64] }:$src0)  =>  SReg_128:{ *:[v4i32] }:$src0
      GIR_BuildMI, /*InsnID*/0, /*Opcode*/GIMT_Encode2(TargetOpcode::COPY),
      GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/0, // dst
      GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/1, // src0
      GIR_ConstrainOperandRC, /*InsnID*/0, /*Op*/0, GIMT_Encode2(AMDGPU::SReg_128RegClassID),
      GIR_EraseFromParent, /*InsnID*/0,
      // GIR_Coverage, 5999,
      GIR_Done,
    // Label 599: @46185
    GIM_Try, /*On fail goto*//*Label 600*/ GIMT_Encode4(46224), // Rule ID 6002 //
      GIM_CheckType, /*MI*/0, /*Op*/1, /*Type*/GILLT_v2s64,
      GIM_CheckRegBankForClass, /*MI*/0, /*Op*/0, /*RC*/GIMT_Encode2(AMDGPU::VReg_128RegClassID),
      GIM_CheckRegBankForClass, /*MI*/0, /*Op*/1, /*RC*/GIMT_Encode2(AMDGPU::VReg_128RegClassID),
      // (bitconvert:{ *:[v4f32] } VReg_128:{ *:[v2f64] }:$src0)  =>  VReg_128:{ *:[v4f32] }:$src0
      GIR_BuildMI, /*InsnID*/0, /*Opcode*/GIMT_Encode2(TargetOpcode::COPY),
      GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/0, // dst
      GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/1, // src0
      GIR_ConstrainOperandRC, /*InsnID*/0, /*Op*/0, GIMT_Encode2(AMDGPU::VReg_128RegClassID),
      GIR_EraseFromParent, /*InsnID*/0,
      // GIR_Coverage, 6002,
      GIR_Done,
    // Label 600: @46224
    GIM_Try, /*On fail goto*//*Label 601*/ GIMT_Encode4(46263), // Rule ID 6003 //
      GIM_CheckType, /*MI*/0, /*Op*/1, /*Type*/GILLT_v2s64,
      GIM_CheckRegBankForClass, /*MI*/0, /*Op*/0, /*RC*/GIMT_Encode2(AMDGPU::VReg_128RegClassID),
      GIM_CheckRegBankForClass, /*MI*/0, /*Op*/1, /*RC*/GIMT_Encode2(AMDGPU::VReg_128RegClassID),
      // (bitconvert:{ *:[v4i32] } VReg_128:{ *:[v2f64] }:$src0)  =>  VReg_128:{ *:[v4i32] }:$src0
      GIR_BuildMI, /*InsnID*/0, /*Opcode*/GIMT_Encode2(TargetOpcode::COPY),
      GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/0, // dst
      GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/1, // src0
      GIR_ConstrainOperandRC, /*InsnID*/0, /*Op*/0, GIMT_Encode2(AMDGPU::VReg_128RegClassID),
      GIR_EraseFromParent, /*InsnID*/0,
      // GIR_Coverage, 6003,
      GIR_Done,
    // Label 601: @46263
    GIM_Try, /*On fail goto*//*Label 602*/ GIMT_Encode4(46302), // Rule ID 6006 //
      GIM_CheckType, /*MI*/0, /*Op*/1, /*Type*/GILLT_v2s64,
      GIM_CheckRegBankForClass, /*MI*/0, /*Op*/0, /*RC*/GIMT_Encode2(AMDGPU::VReg_128RegClassID),
      GIM_CheckRegBankForClass, /*MI*/0, /*Op*/1, /*RC*/GIMT_Encode2(AMDGPU::VReg_128RegClassID),
      // (bitconvert:{ *:[v4f32] } VReg_128:{ *:[v2i64] }:$src0)  =>  VReg_128:{ *:[v4f32] }:$src0
      GIR_BuildMI, /*InsnID*/0, /*Opcode*/GIMT_Encode2(TargetOpcode::COPY),
      GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/0, // dst
      GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/1, // src0
      GIR_ConstrainOperandRC, /*InsnID*/0, /*Op*/0, GIMT_Encode2(AMDGPU::VReg_128RegClassID),
      GIR_EraseFromParent, /*InsnID*/0,
      // GIR_Coverage, 6006,
      GIR_Done,
    // Label 602: @46302
    GIM_Try, /*On fail goto*//*Label 603*/ GIMT_Encode4(46341), // Rule ID 6009 //
      GIM_CheckType, /*MI*/0, /*Op*/1, /*Type*/GILLT_v8s16,
      GIM_CheckRegBankForClass, /*MI*/0, /*Op*/0, /*RC*/GIMT_Encode2(AMDGPU::SReg_128RegClassID),
      GIM_CheckRegBankForClass, /*MI*/0, /*Op*/1, /*RC*/GIMT_Encode2(AMDGPU::SReg_128RegClassID),
      // (bitconvert:{ *:[v4i32] } SReg_128:{ *:[v8i16] }:$src0)  =>  SReg_128:{ *:[v4i32] }:$src0
      GIR_BuildMI, /*InsnID*/0, /*Opcode*/GIMT_Encode2(TargetOpcode::COPY),
      GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/0, // dst
      GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/1, // src0
      GIR_ConstrainOperandRC, /*InsnID*/0, /*Op*/0, GIMT_Encode2(AMDGPU::SReg_128RegClassID),
      GIR_EraseFromParent, /*InsnID*/0,
      // GIR_Coverage, 6009,
      GIR_Done,
    // Label 603: @46341
    GIM_Try, /*On fail goto*//*Label 604*/ GIMT_Encode4(46380), // Rule ID 6012 //
      GIM_CheckType, /*MI*/0, /*Op*/1, /*Type*/GILLT_v8s16,
      GIM_CheckRegBankForClass, /*MI*/0, /*Op*/0, /*RC*/GIMT_Encode2(AMDGPU::VReg_128RegClassID),
      GIM_CheckRegBankForClass, /*MI*/0, /*Op*/1, /*RC*/GIMT_Encode2(AMDGPU::VReg_128RegClassID),
      // (bitconvert:{ *:[v4f32] } VReg_128:{ *:[v8f16] }:$src0)  =>  VReg_128:{ *:[v4f32] }:$src0
      GIR_BuildMI, /*InsnID*/0, /*Opcode*/GIMT_Encode2(TargetOpcode::COPY),
      GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/0, // dst
      GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/1, // src0
      GIR_ConstrainOperandRC, /*InsnID*/0, /*Op*/0, GIMT_Encode2(AMDGPU::VReg_128RegClassID),
      GIR_EraseFromParent, /*InsnID*/0,
      // GIR_Coverage, 6012,
      GIR_Done,
    // Label 604: @46380
    GIM_Try, /*On fail goto*//*Label 605*/ GIMT_Encode4(46419), // Rule ID 6013 //
      GIM_CheckType, /*MI*/0, /*Op*/1, /*Type*/GILLT_v8s16,
      GIM_CheckRegBankForClass, /*MI*/0, /*Op*/0, /*RC*/GIMT_Encode2(AMDGPU::VReg_128RegClassID),
      GIM_CheckRegBankForClass, /*MI*/0, /*Op*/1, /*RC*/GIMT_Encode2(AMDGPU::VReg_128RegClassID),
      // (bitconvert:{ *:[v4i32] } VReg_128:{ *:[v8f16] }:$src0)  =>  VReg_128:{ *:[v4i32] }:$src0
      GIR_BuildMI, /*InsnID*/0, /*Opcode*/GIMT_Encode2(TargetOpcode::COPY),
      GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/0, // dst
      GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/1, // src0
      GIR_ConstrainOperandRC, /*InsnID*/0, /*Op*/0, GIMT_Encode2(AMDGPU::VReg_128RegClassID),
      GIR_EraseFromParent, /*InsnID*/0,
      // GIR_Coverage, 6013,
      GIR_Done,
    // Label 605: @46419
    GIM_Try, /*On fail goto*//*Label 606*/ GIMT_Encode4(46458), // Rule ID 6016 //
      GIM_CheckType, /*MI*/0, /*Op*/1, /*Type*/GILLT_v8s16,
      GIM_CheckRegBankForClass, /*MI*/0, /*Op*/0, /*RC*/GIMT_Encode2(AMDGPU::VReg_128RegClassID),
      GIM_CheckRegBankForClass, /*MI*/0, /*Op*/1, /*RC*/GIMT_Encode2(AMDGPU::VReg_128RegClassID),
      // (bitconvert:{ *:[v4f32] } VReg_128:{ *:[v8i16] }:$src0)  =>  VReg_128:{ *:[v4f32] }:$src0
      GIR_BuildMI, /*InsnID*/0, /*Opcode*/GIMT_Encode2(TargetOpcode::COPY),
      GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/0, // dst
      GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/1, // src0
      GIR_ConstrainOperandRC, /*InsnID*/0, /*Op*/0, GIMT_Encode2(AMDGPU::VReg_128RegClassID),
      GIR_EraseFromParent, /*InsnID*/0,
      // GIR_Coverage, 6016,
      GIR_Done,
    // Label 606: @46458
    GIM_Try, /*On fail goto*//*Label 607*/ GIMT_Encode4(46497), // Rule ID 6028 //
      GIM_CheckType, /*MI*/0, /*Op*/1, /*Type*/GILLT_v8s16,
      GIM_CheckRegBankForClass, /*MI*/0, /*Op*/0, /*RC*/GIMT_Encode2(AMDGPU::SReg_128RegClassID),
      GIM_CheckRegBankForClass, /*MI*/0, /*Op*/1, /*RC*/GIMT_Encode2(AMDGPU::SReg_128RegClassID),
      // (bitconvert:{ *:[v4i32] } SReg_128:{ *:[v8bf16] }:$src0)  =>  SReg_128:{ *:[v4i32] }:$src0
      GIR_BuildMI, /*InsnID*/0, /*Opcode*/GIMT_Encode2(TargetOpcode::COPY),
      GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/0, // dst
      GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/1, // src0
      GIR_ConstrainOperandRC, /*InsnID*/0, /*Op*/0, GIMT_Encode2(AMDGPU::SReg_128RegClassID),
      GIR_EraseFromParent, /*InsnID*/0,
      // GIR_Coverage, 6028,
      GIR_Done,
    // Label 607: @46497
    GIM_Try, /*On fail goto*//*Label 608*/ GIMT_Encode4(46536), // Rule ID 6030 //
      GIM_CheckType, /*MI*/0, /*Op*/1, /*Type*/GILLT_v8s16,
      GIM_CheckRegBankForClass, /*MI*/0, /*Op*/0, /*RC*/GIMT_Encode2(AMDGPU::VReg_128RegClassID),
      GIM_CheckRegBankForClass, /*MI*/0, /*Op*/1, /*RC*/GIMT_Encode2(AMDGPU::VReg_128RegClassID),
      // (bitconvert:{ *:[v4i32] } VReg_128:{ *:[v8bf16] }:$src0)  =>  VReg_128:{ *:[v4i32] }:$src0
      GIR_BuildMI, /*InsnID*/0, /*Opcode*/GIMT_Encode2(TargetOpcode::COPY),
      GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/0, // dst
      GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/1, // src0
      GIR_ConstrainOperandRC, /*InsnID*/0, /*Op*/0, GIMT_Encode2(AMDGPU::VReg_128RegClassID),
      GIR_EraseFromParent, /*InsnID*/0,
      // GIR_Coverage, 6030,
      GIR_Done,
    // Label 608: @46536
    GIM_Try, /*On fail goto*//*Label 609*/ GIMT_Encode4(46575), // Rule ID 6032 //
      GIM_CheckType, /*MI*/0, /*Op*/1, /*Type*/GILLT_v8s16,
      GIM_CheckRegBankForClass, /*MI*/0, /*Op*/0, /*RC*/GIMT_Encode2(AMDGPU::SReg_128RegClassID),
      GIM_CheckRegBankForClass, /*MI*/0, /*Op*/1, /*RC*/GIMT_Encode2(AMDGPU::SReg_128RegClassID),
      // (bitconvert:{ *:[v4f32] } SReg_128:{ *:[v8bf16] }:$src0)  =>  SReg_128:{ *:[v4f32] }:$src0
      GIR_BuildMI, /*InsnID*/0, /*Opcode*/GIMT_Encode2(TargetOpcode::COPY),
      GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/0, // dst
      GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/1, // src0
      GIR_ConstrainOperandRC, /*InsnID*/0, /*Op*/0, GIMT_Encode2(AMDGPU::SReg_128RegClassID),
      GIR_EraseFromParent, /*InsnID*/0,
      // GIR_Coverage, 6032,
      GIR_Done,
    // Label 609: @46575
    GIM_Try, /*On fail goto*//*Label 610*/ GIMT_Encode4(46614), // Rule ID 6034 //
      GIM_CheckType, /*MI*/0, /*Op*/1, /*Type*/GILLT_v8s16,
      GIM_CheckRegBankForClass, /*MI*/0, /*Op*/0, /*RC*/GIMT_Encode2(AMDGPU::VReg_128RegClassID),
      GIM_CheckRegBankForClass, /*MI*/0, /*Op*/1, /*RC*/GIMT_Encode2(AMDGPU::VReg_128RegClassID),
      // (bitconvert:{ *:[v4f32] } VReg_128:{ *:[v8bf16] }:$src0)  =>  VReg_128:{ *:[v4f32] }:$src0
      GIR_BuildMI, /*InsnID*/0, /*Opcode*/GIMT_Encode2(TargetOpcode::COPY),
      GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/0, // dst
      GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/1, // src0
      GIR_ConstrainOperandRC, /*InsnID*/0, /*Op*/0, GIMT_Encode2(AMDGPU::VReg_128RegClassID),
      GIR_EraseFromParent, /*InsnID*/0,
      // GIR_Coverage, 6034,
      GIR_Done,
    // Label 610: @46614
    GIM_Reject,
    // Label 471: @46615
    GIM_Try, /*On fail goto*//*Label 611*/ GIMT_Encode4(46654), // Rule ID 6078 //
      GIM_CheckType, /*MI*/0, /*Op*/1, /*Type*/GILLT_v4s64,
      GIM_CheckRegBankForClass, /*MI*/0, /*Op*/0, /*RC*/GIMT_Encode2(AMDGPU::VReg_256RegClassID),
      GIM_CheckRegBankForClass, /*MI*/0, /*Op*/1, /*RC*/GIMT_Encode2(AMDGPU::VReg_256RegClassID),
      // (bitconvert:{ *:[v4i64] } VReg_256:{ *:[v4f64] }:$src0)  =>  VReg_256:{ *:[v4i64] }:$src0
      GIR_BuildMI, /*InsnID*/0, /*Opcode*/GIMT_Encode2(TargetOpcode::COPY),
      GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/0, // dst
      GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/1, // src0
      GIR_ConstrainOperandRC, /*InsnID*/0, /*Op*/0, GIMT_Encode2(AMDGPU::VReg_256RegClassID),
      GIR_EraseFromParent, /*InsnID*/0,
      // GIR_Coverage, 6078,
      GIR_Done,
    // Label 611: @46654
    GIM_Try, /*On fail goto*//*Label 612*/ GIMT_Encode4(46693), // Rule ID 6079 //
      GIM_CheckType, /*MI*/0, /*Op*/1, /*Type*/GILLT_v4s64,
      GIM_CheckRegBankForClass, /*MI*/0, /*Op*/0, /*RC*/GIMT_Encode2(AMDGPU::VReg_256RegClassID),
      GIM_CheckRegBankForClass, /*MI*/0, /*Op*/1, /*RC*/GIMT_Encode2(AMDGPU::VReg_256RegClassID),
      // (bitconvert:{ *:[v4f64] } VReg_256:{ *:[v4i64] }:$src0)  =>  VReg_256:{ *:[v4f64] }:$src0
      GIR_BuildMI, /*InsnID*/0, /*Opcode*/GIMT_Encode2(TargetOpcode::COPY),
      GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/0, // dst
      GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/1, // src0
      GIR_ConstrainOperandRC, /*InsnID*/0, /*Op*/0, GIMT_Encode2(AMDGPU::VReg_256RegClassID),
      GIR_EraseFromParent, /*InsnID*/0,
      // GIR_Coverage, 6079,
      GIR_Done,
    // Label 612: @46693
    GIM_Try, /*On fail goto*//*Label 613*/ GIMT_Encode4(46732), // Rule ID 6080 //
      GIM_CheckType, /*MI*/0, /*Op*/1, /*Type*/GILLT_v8s32,
      GIM_CheckRegBankForClass, /*MI*/0, /*Op*/0, /*RC*/GIMT_Encode2(AMDGPU::VReg_256RegClassID),
      GIM_CheckRegBankForClass, /*MI*/0, /*Op*/1, /*RC*/GIMT_Encode2(AMDGPU::VReg_256RegClassID),
      // (bitconvert:{ *:[v4i64] } VReg_256:{ *:[v8i32] }:$src0)  =>  VReg_256:{ *:[v4i64] }:$src0
      GIR_BuildMI, /*InsnID*/0, /*Opcode*/GIMT_Encode2(TargetOpcode::COPY),
      GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/0, // dst
      GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/1, // src0
      GIR_ConstrainOperandRC, /*InsnID*/0, /*Op*/0, GIMT_Encode2(AMDGPU::VReg_256RegClassID),
      GIR_EraseFromParent, /*InsnID*/0,
      // GIR_Coverage, 6080,
      GIR_Done,
    // Label 613: @46732
    GIM_Try, /*On fail goto*//*Label 614*/ GIMT_Encode4(46771), // Rule ID 6081 //
      GIM_CheckType, /*MI*/0, /*Op*/1, /*Type*/GILLT_v8s32,
      GIM_CheckRegBankForClass, /*MI*/0, /*Op*/0, /*RC*/GIMT_Encode2(AMDGPU::VReg_256RegClassID),
      GIM_CheckRegBankForClass, /*MI*/0, /*Op*/1, /*RC*/GIMT_Encode2(AMDGPU::VReg_256RegClassID),
      // (bitconvert:{ *:[v4i64] } VReg_256:{ *:[v8f32] }:$src0)  =>  VReg_256:{ *:[v4i64] }:$src0
      GIR_BuildMI, /*InsnID*/0, /*Opcode*/GIMT_Encode2(TargetOpcode::COPY),
      GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/0, // dst
      GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/1, // src0
      GIR_ConstrainOperandRC, /*InsnID*/0, /*Op*/0, GIMT_Encode2(AMDGPU::VReg_256RegClassID),
      GIR_EraseFromParent, /*InsnID*/0,
      // GIR_Coverage, 6081,
      GIR_Done,
    // Label 614: @46771
    GIM_Try, /*On fail goto*//*Label 615*/ GIMT_Encode4(46810), // Rule ID 6082 //
      GIM_CheckType, /*MI*/0, /*Op*/1, /*Type*/GILLT_v8s32,
      GIM_CheckRegBankForClass, /*MI*/0, /*Op*/0, /*RC*/GIMT_Encode2(AMDGPU::VReg_256RegClassID),
      GIM_CheckRegBankForClass, /*MI*/0, /*Op*/1, /*RC*/GIMT_Encode2(AMDGPU::VReg_256RegClassID),
      // (bitconvert:{ *:[v4f64] } VReg_256:{ *:[v8i32] }:$src0)  =>  VReg_256:{ *:[v4f64] }:$src0
      GIR_BuildMI, /*InsnID*/0, /*Opcode*/GIMT_Encode2(TargetOpcode::COPY),
      GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/0, // dst
      GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/1, // src0
      GIR_ConstrainOperandRC, /*InsnID*/0, /*Op*/0, GIMT_Encode2(AMDGPU::VReg_256RegClassID),
      GIR_EraseFromParent, /*InsnID*/0,
      // GIR_Coverage, 6082,
      GIR_Done,
    // Label 615: @46810
    GIM_Try, /*On fail goto*//*Label 616*/ GIMT_Encode4(46849), // Rule ID 6083 //
      GIM_CheckType, /*MI*/0, /*Op*/1, /*Type*/GILLT_v8s32,
      GIM_CheckRegBankForClass, /*MI*/0, /*Op*/0, /*RC*/GIMT_Encode2(AMDGPU::VReg_256RegClassID),
      GIM_CheckRegBankForClass, /*MI*/0, /*Op*/1, /*RC*/GIMT_Encode2(AMDGPU::VReg_256RegClassID),
      // (bitconvert:{ *:[v4f64] } VReg_256:{ *:[v8f32] }:$src0)  =>  VReg_256:{ *:[v4f64] }:$src0
      GIR_BuildMI, /*InsnID*/0, /*Opcode*/GIMT_Encode2(TargetOpcode::COPY),
      GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/0, // dst
      GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/1, // src0
      GIR_ConstrainOperandRC, /*InsnID*/0, /*Op*/0, GIMT_Encode2(AMDGPU::VReg_256RegClassID),
      GIR_EraseFromParent, /*InsnID*/0,
      // GIR_Coverage, 6083,
      GIR_Done,
    // Label 616: @46849
    GIM_Try, /*On fail goto*//*Label 617*/ GIMT_Encode4(46888), // Rule ID 6104 //
      GIM_CheckType, /*MI*/0, /*Op*/1, /*Type*/GILLT_v16s16,
      GIM_CheckRegBankForClass, /*MI*/0, /*Op*/0, /*RC*/GIMT_Encode2(AMDGPU::VReg_256RegClassID),
      GIM_CheckRegBankForClass, /*MI*/0, /*Op*/1, /*RC*/GIMT_Encode2(AMDGPU::VReg_256RegClassID),
      // (bitconvert:{ *:[v4i64] } VReg_256:{ *:[v16f16] }:$src0)  =>  VReg_256:{ *:[v4i64] }:$src0
      GIR_BuildMI, /*InsnID*/0, /*Opcode*/GIMT_Encode2(TargetOpcode::COPY),
      GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/0, // dst
      GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/1, // src0
      GIR_ConstrainOperandRC, /*InsnID*/0, /*Op*/0, GIMT_Encode2(AMDGPU::VReg_256RegClassID),
      GIR_EraseFromParent, /*InsnID*/0,
      // GIR_Coverage, 6104,
      GIR_Done,
    // Label 617: @46888
    GIM_Try, /*On fail goto*//*Label 618*/ GIMT_Encode4(46927), // Rule ID 6105 //
      GIM_CheckType, /*MI*/0, /*Op*/1, /*Type*/GILLT_v16s16,
      GIM_CheckRegBankForClass, /*MI*/0, /*Op*/0, /*RC*/GIMT_Encode2(AMDGPU::VReg_256RegClassID),
      GIM_CheckRegBankForClass, /*MI*/0, /*Op*/1, /*RC*/GIMT_Encode2(AMDGPU::VReg_256RegClassID),
      // (bitconvert:{ *:[v4i64] } VReg_256:{ *:[v16i16] }:$src0)  =>  VReg_256:{ *:[v4i64] }:$src0
      GIR_BuildMI, /*InsnID*/0, /*Opcode*/GIMT_Encode2(TargetOpcode::COPY),
      GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/0, // dst
      GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/1, // src0
      GIR_ConstrainOperandRC, /*InsnID*/0, /*Op*/0, GIMT_Encode2(AMDGPU::VReg_256RegClassID),
      GIR_EraseFromParent, /*InsnID*/0,
      // GIR_Coverage, 6105,
      GIR_Done,
    // Label 618: @46927
    GIM_Try, /*On fail goto*//*Label 619*/ GIMT_Encode4(46966), // Rule ID 6106 //
      GIM_CheckType, /*MI*/0, /*Op*/1, /*Type*/GILLT_v16s16,
      GIM_CheckRegBankForClass, /*MI*/0, /*Op*/0, /*RC*/GIMT_Encode2(AMDGPU::VReg_256RegClassID),
      GIM_CheckRegBankForClass, /*MI*/0, /*Op*/1, /*RC*/GIMT_Encode2(AMDGPU::VReg_256RegClassID),
      // (bitconvert:{ *:[v4f64] } VReg_256:{ *:[v16f16] }:$src0)  =>  VReg_256:{ *:[v4f64] }:$src0
      GIR_BuildMI, /*InsnID*/0, /*Opcode*/GIMT_Encode2(TargetOpcode::COPY),
      GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/0, // dst
      GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/1, // src0
      GIR_ConstrainOperandRC, /*InsnID*/0, /*Op*/0, GIMT_Encode2(AMDGPU::VReg_256RegClassID),
      GIR_EraseFromParent, /*InsnID*/0,
      // GIR_Coverage, 6106,
      GIR_Done,
    // Label 619: @46966
    GIM_Try, /*On fail goto*//*Label 620*/ GIMT_Encode4(47005), // Rule ID 6107 //
      GIM_CheckType, /*MI*/0, /*Op*/1, /*Type*/GILLT_v16s16,
      GIM_CheckRegBankForClass, /*MI*/0, /*Op*/0, /*RC*/GIMT_Encode2(AMDGPU::VReg_256RegClassID),
      GIM_CheckRegBankForClass, /*MI*/0, /*Op*/1, /*RC*/GIMT_Encode2(AMDGPU::VReg_256RegClassID),
      // (bitconvert:{ *:[v4f64] } VReg_256:{ *:[v16i16] }:$src0)  =>  VReg_256:{ *:[v4f64] }:$src0
      GIR_BuildMI, /*InsnID*/0, /*Opcode*/GIMT_Encode2(TargetOpcode::COPY),
      GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/0, // dst
      GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/1, // src0
      GIR_ConstrainOperandRC, /*InsnID*/0, /*Op*/0, GIMT_Encode2(AMDGPU::VReg_256RegClassID),
      GIR_EraseFromParent, /*InsnID*/0,
      // GIR_Coverage, 6107,
      GIR_Done,
    // Label 620: @47005
    GIM_Try, /*On fail goto*//*Label 621*/ GIMT_Encode4(47044), // Rule ID 6112 //
      GIM_CheckType, /*MI*/0, /*Op*/1, /*Type*/GILLT_v16s16,
      GIM_CheckRegBankForClass, /*MI*/0, /*Op*/0, /*RC*/GIMT_Encode2(AMDGPU::VReg_256RegClassID),
      GIM_CheckRegBankForClass, /*MI*/0, /*Op*/1, /*RC*/GIMT_Encode2(AMDGPU::VReg_256RegClassID),
      // (bitconvert:{ *:[v4i64] } VReg_256:{ *:[v16bf16] }:$src0)  =>  VReg_256:{ *:[v4i64] }:$src0
      GIR_BuildMI, /*InsnID*/0, /*Opcode*/GIMT_Encode2(TargetOpcode::COPY),
      GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/0, // dst
      GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/1, // src0
      GIR_ConstrainOperandRC, /*InsnID*/0, /*Op*/0, GIMT_Encode2(AMDGPU::VReg_256RegClassID),
      GIR_EraseFromParent, /*InsnID*/0,
      // GIR_Coverage, 6112,
      GIR_Done,
    // Label 621: @47044
    GIM_Try, /*On fail goto*//*Label 622*/ GIMT_Encode4(47083), // Rule ID 6114 //
      GIM_CheckType, /*MI*/0, /*Op*/1, /*Type*/GILLT_v16s16,
      GIM_CheckRegBankForClass, /*MI*/0, /*Op*/0, /*RC*/GIMT_Encode2(AMDGPU::VReg_256RegClassID),
      GIM_CheckRegBankForClass, /*MI*/0, /*Op*/1, /*RC*/GIMT_Encode2(AMDGPU::VReg_256RegClassID),
      // (bitconvert:{ *:[v4f64] } VReg_256:{ *:[v16bf16] }:$src0)  =>  VReg_256:{ *:[v4f64] }:$src0
      GIR_BuildMI, /*InsnID*/0, /*Opcode*/GIMT_Encode2(TargetOpcode::COPY),
      GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/0, // dst
      GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/1, // src0
      GIR_ConstrainOperandRC, /*InsnID*/0, /*Op*/0, GIMT_Encode2(AMDGPU::VReg_256RegClassID),
      GIR_EraseFromParent, /*InsnID*/0,
      // GIR_Coverage, 6114,
      GIR_Done,
    // Label 622: @47083
    GIM_Reject,
    // Label 472: @47084
    GIM_Try, /*On fail goto*//*Label 623*/ GIMT_Encode4(47234),
      GIM_CheckType, /*MI*/0, /*Op*/1, /*Type*/GILLT_v5s32,
      GIM_Try, /*On fail goto*//*Label 624*/ GIMT_Encode4(47128), // Rule ID 6052 //
        GIM_CheckRegBankForClass, /*MI*/0, /*Op*/0, /*RC*/GIMT_Encode2(AMDGPU::SReg_160RegClassID),
        GIM_CheckRegBankForClass, /*MI*/0, /*Op*/1, /*RC*/GIMT_Encode2(AMDGPU::SReg_160RegClassID),
        // (bitconvert:{ *:[v5i32] } SReg_160:{ *:[v5f32] }:$src0)  =>  SReg_160:{ *:[v5i32] }:$src0
        GIR_BuildMI, /*InsnID*/0, /*Opcode*/GIMT_Encode2(TargetOpcode::COPY),
        GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/0, // dst
        GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/1, // src0
        GIR_ConstrainOperandRC, /*InsnID*/0, /*Op*/0, GIMT_Encode2(AMDGPU::SReg_160RegClassID),
        GIR_EraseFromParent, /*InsnID*/0,
        // GIR_Coverage, 6052,
        GIR_Done,
      // Label 624: @47128
      GIM_Try, /*On fail goto*//*Label 625*/ GIMT_Encode4(47163), // Rule ID 6053 //
        GIM_CheckRegBankForClass, /*MI*/0, /*Op*/0, /*RC*/GIMT_Encode2(AMDGPU::SReg_160RegClassID),
        GIM_CheckRegBankForClass, /*MI*/0, /*Op*/1, /*RC*/GIMT_Encode2(AMDGPU::SReg_160RegClassID),
        // (bitconvert:{ *:[v5f32] } SReg_160:{ *:[v5i32] }:$src0)  =>  SReg_160:{ *:[v5f32] }:$src0
        GIR_BuildMI, /*InsnID*/0, /*Opcode*/GIMT_Encode2(TargetOpcode::COPY),
        GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/0, // dst
        GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/1, // src0
        GIR_ConstrainOperandRC, /*InsnID*/0, /*Op*/0, GIMT_Encode2(AMDGPU::SReg_160RegClassID),
        GIR_EraseFromParent, /*InsnID*/0,
        // GIR_Coverage, 6053,
        GIR_Done,
      // Label 625: @47163
      GIM_Try, /*On fail goto*//*Label 626*/ GIMT_Encode4(47198), // Rule ID 6054 //
        GIM_CheckRegBankForClass, /*MI*/0, /*Op*/0, /*RC*/GIMT_Encode2(AMDGPU::VReg_160RegClassID),
        GIM_CheckRegBankForClass, /*MI*/0, /*Op*/1, /*RC*/GIMT_Encode2(AMDGPU::VReg_160RegClassID),
        // (bitconvert:{ *:[v5i32] } VReg_160:{ *:[v5f32] }:$src0)  =>  VReg_160:{ *:[v5i32] }:$src0
        GIR_BuildMI, /*InsnID*/0, /*Opcode*/GIMT_Encode2(TargetOpcode::COPY),
        GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/0, // dst
        GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/1, // src0
        GIR_ConstrainOperandRC, /*InsnID*/0, /*Op*/0, GIMT_Encode2(AMDGPU::VReg_160RegClassID),
        GIR_EraseFromParent, /*InsnID*/0,
        // GIR_Coverage, 6054,
        GIR_Done,
      // Label 626: @47198
      GIM_Try, /*On fail goto*//*Label 627*/ GIMT_Encode4(47233), // Rule ID 6055 //
        GIM_CheckRegBankForClass, /*MI*/0, /*Op*/0, /*RC*/GIMT_Encode2(AMDGPU::VReg_160RegClassID),
        GIM_CheckRegBankForClass, /*MI*/0, /*Op*/1, /*RC*/GIMT_Encode2(AMDGPU::VReg_160RegClassID),
        // (bitconvert:{ *:[v5f32] } VReg_160:{ *:[v5i32] }:$src0)  =>  VReg_160:{ *:[v5f32] }:$src0
        GIR_BuildMI, /*InsnID*/0, /*Opcode*/GIMT_Encode2(TargetOpcode::COPY),
        GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/0, // dst
        GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/1, // src0
        GIR_ConstrainOperandRC, /*InsnID*/0, /*Op*/0, GIMT_Encode2(AMDGPU::VReg_160RegClassID),
        GIR_EraseFromParent, /*InsnID*/0,
        // GIR_Coverage, 6055,
        GIR_Done,
      // Label 627: @47233
      GIM_Reject,
    // Label 623: @47234
    GIM_Reject,
    // Label 473: @47235
    GIM_Try, /*On fail goto*//*Label 628*/ GIMT_Encode4(47274), // Rule ID 6056 //
      GIM_CheckType, /*MI*/0, /*Op*/1, /*Type*/GILLT_v6s32,
      GIM_CheckRegBankForClass, /*MI*/0, /*Op*/0, /*RC*/GIMT_Encode2(AMDGPU::SReg_192RegClassID),
      GIM_CheckRegBankForClass, /*MI*/0, /*Op*/1, /*RC*/GIMT_Encode2(AMDGPU::SReg_192RegClassID),
      // (bitconvert:{ *:[v6i32] } SReg_192:{ *:[v6f32] }:$src0)  =>  SReg_192:{ *:[v6i32] }:$src0
      GIR_BuildMI, /*InsnID*/0, /*Opcode*/GIMT_Encode2(TargetOpcode::COPY),
      GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/0, // dst
      GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/1, // src0
      GIR_ConstrainOperandRC, /*InsnID*/0, /*Op*/0, GIMT_Encode2(AMDGPU::SReg_192RegClassID),
      GIR_EraseFromParent, /*InsnID*/0,
      // GIR_Coverage, 6056,
      GIR_Done,
    // Label 628: @47274
    GIM_Try, /*On fail goto*//*Label 629*/ GIMT_Encode4(47313), // Rule ID 6057 //
      GIM_CheckType, /*MI*/0, /*Op*/1, /*Type*/GILLT_v6s32,
      GIM_CheckRegBankForClass, /*MI*/0, /*Op*/0, /*RC*/GIMT_Encode2(AMDGPU::SReg_192RegClassID),
      GIM_CheckRegBankForClass, /*MI*/0, /*Op*/1, /*RC*/GIMT_Encode2(AMDGPU::SReg_192RegClassID),
      // (bitconvert:{ *:[v6f32] } SReg_192:{ *:[v6i32] }:$src0)  =>  SReg_192:{ *:[v6f32] }:$src0
      GIR_BuildMI, /*InsnID*/0, /*Opcode*/GIMT_Encode2(TargetOpcode::COPY),
      GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/0, // dst
      GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/1, // src0
      GIR_ConstrainOperandRC, /*InsnID*/0, /*Op*/0, GIMT_Encode2(AMDGPU::SReg_192RegClassID),
      GIR_EraseFromParent, /*InsnID*/0,
      // GIR_Coverage, 6057,
      GIR_Done,
    // Label 629: @47313
    GIM_Try, /*On fail goto*//*Label 630*/ GIMT_Encode4(47352), // Rule ID 6058 //
      GIM_CheckType, /*MI*/0, /*Op*/1, /*Type*/GILLT_v6s32,
      GIM_CheckRegBankForClass, /*MI*/0, /*Op*/0, /*RC*/GIMT_Encode2(AMDGPU::VReg_192RegClassID),
      GIM_CheckRegBankForClass, /*MI*/0, /*Op*/1, /*RC*/GIMT_Encode2(AMDGPU::VReg_192RegClassID),
      // (bitconvert:{ *:[v6i32] } VReg_192:{ *:[v6f32] }:$src0)  =>  VReg_192:{ *:[v6i32] }:$src0
      GIR_BuildMI, /*InsnID*/0, /*Opcode*/GIMT_Encode2(TargetOpcode::COPY),
      GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/0, // dst
      GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/1, // src0
      GIR_ConstrainOperandRC, /*InsnID*/0, /*Op*/0, GIMT_Encode2(AMDGPU::VReg_192RegClassID),
      GIR_EraseFromParent, /*InsnID*/0,
      // GIR_Coverage, 6058,
      GIR_Done,
    // Label 630: @47352
    GIM_Try, /*On fail goto*//*Label 631*/ GIMT_Encode4(47391), // Rule ID 6059 //
      GIM_CheckType, /*MI*/0, /*Op*/1, /*Type*/GILLT_v6s32,
      GIM_CheckRegBankForClass, /*MI*/0, /*Op*/0, /*RC*/GIMT_Encode2(AMDGPU::VReg_192RegClassID),
      GIM_CheckRegBankForClass, /*MI*/0, /*Op*/1, /*RC*/GIMT_Encode2(AMDGPU::VReg_192RegClassID),
      // (bitconvert:{ *:[v6f32] } VReg_192:{ *:[v6i32] }:$src0)  =>  VReg_192:{ *:[v6f32] }:$src0
      GIR_BuildMI, /*InsnID*/0, /*Opcode*/GIMT_Encode2(TargetOpcode::COPY),
      GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/0, // dst
      GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/1, // src0
      GIR_ConstrainOperandRC, /*InsnID*/0, /*Op*/0, GIMT_Encode2(AMDGPU::VReg_192RegClassID),
      GIR_EraseFromParent, /*InsnID*/0,
      // GIR_Coverage, 6059,
      GIR_Done,
    // Label 631: @47391
    GIM_Try, /*On fail goto*//*Label 632*/ GIMT_Encode4(47430), // Rule ID 6066 //
      GIM_CheckType, /*MI*/0, /*Op*/1, /*Type*/GILLT_v3s64,
      GIM_CheckRegBankForClass, /*MI*/0, /*Op*/0, /*RC*/GIMT_Encode2(AMDGPU::VReg_192RegClassID),
      GIM_CheckRegBankForClass, /*MI*/0, /*Op*/1, /*RC*/GIMT_Encode2(AMDGPU::VReg_192RegClassID),
      // (bitconvert:{ *:[v6i32] } VReg_192:{ *:[v3i64] }:$src0)  =>  VReg_192:{ *:[v6i32] }:$src0
      GIR_BuildMI, /*InsnID*/0, /*Opcode*/GIMT_Encode2(TargetOpcode::COPY),
      GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/0, // dst
      GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/1, // src0
      GIR_ConstrainOperandRC, /*InsnID*/0, /*Op*/0, GIMT_Encode2(AMDGPU::VReg_192RegClassID),
      GIR_EraseFromParent, /*InsnID*/0,
      // GIR_Coverage, 6066,
      GIR_Done,
    // Label 632: @47430
    GIM_Try, /*On fail goto*//*Label 633*/ GIMT_Encode4(47469), // Rule ID 6067 //
      GIM_CheckType, /*MI*/0, /*Op*/1, /*Type*/GILLT_v3s64,
      GIM_CheckRegBankForClass, /*MI*/0, /*Op*/0, /*RC*/GIMT_Encode2(AMDGPU::VReg_192RegClassID),
      GIM_CheckRegBankForClass, /*MI*/0, /*Op*/1, /*RC*/GIMT_Encode2(AMDGPU::VReg_192RegClassID),
      // (bitconvert:{ *:[v6f32] } VReg_192:{ *:[v3i64] }:$src0)  =>  VReg_192:{ *:[v6f32] }:$src0
      GIR_BuildMI, /*InsnID*/0, /*Opcode*/GIMT_Encode2(TargetOpcode::COPY),
      GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/0, // dst
      GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/1, // src0
      GIR_ConstrainOperandRC, /*InsnID*/0, /*Op*/0, GIMT_Encode2(AMDGPU::VReg_192RegClassID),
      GIR_EraseFromParent, /*InsnID*/0,
      // GIR_Coverage, 6067,
      GIR_Done,
    // Label 633: @47469
    GIM_Try, /*On fail goto*//*Label 634*/ GIMT_Encode4(47508), // Rule ID 6068 //
      GIM_CheckType, /*MI*/0, /*Op*/1, /*Type*/GILLT_v3s64,
      GIM_CheckRegBankForClass, /*MI*/0, /*Op*/0, /*RC*/GIMT_Encode2(AMDGPU::VReg_192RegClassID),
      GIM_CheckRegBankForClass, /*MI*/0, /*Op*/1, /*RC*/GIMT_Encode2(AMDGPU::VReg_192RegClassID),
      // (bitconvert:{ *:[v6i32] } VReg_192:{ *:[v3f64] }:$src0)  =>  VReg_192:{ *:[v6i32] }:$src0
      GIR_BuildMI, /*InsnID*/0, /*Opcode*/GIMT_Encode2(TargetOpcode::COPY),
      GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/0, // dst
      GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/1, // src0
      GIR_ConstrainOperandRC, /*InsnID*/0, /*Op*/0, GIMT_Encode2(AMDGPU::VReg_192RegClassID),
      GIR_EraseFromParent, /*InsnID*/0,
      // GIR_Coverage, 6068,
      GIR_Done,
    // Label 634: @47508
    GIM_Try, /*On fail goto*//*Label 635*/ GIMT_Encode4(47547), // Rule ID 6069 //
      GIM_CheckType, /*MI*/0, /*Op*/1, /*Type*/GILLT_v3s64,
      GIM_CheckRegBankForClass, /*MI*/0, /*Op*/0, /*RC*/GIMT_Encode2(AMDGPU::VReg_192RegClassID),
      GIM_CheckRegBankForClass, /*MI*/0, /*Op*/1, /*RC*/GIMT_Encode2(AMDGPU::VReg_192RegClassID),
      // (bitconvert:{ *:[v6f32] } VReg_192:{ *:[v3f64] }:$src0)  =>  VReg_192:{ *:[v6f32] }:$src0
      GIR_BuildMI, /*InsnID*/0, /*Opcode*/GIMT_Encode2(TargetOpcode::COPY),
      GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/0, // dst
      GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/1, // src0
      GIR_ConstrainOperandRC, /*InsnID*/0, /*Op*/0, GIMT_Encode2(AMDGPU::VReg_192RegClassID),
      GIR_EraseFromParent, /*InsnID*/0,
      // GIR_Coverage, 6069,
      GIR_Done,
    // Label 635: @47547
    GIM_Reject,
    // Label 474: @47548
    GIM_Try, /*On fail goto*//*Label 636*/ GIMT_Encode4(47698),
      GIM_CheckType, /*MI*/0, /*Op*/1, /*Type*/GILLT_v7s32,
      GIM_Try, /*On fail goto*//*Label 637*/ GIMT_Encode4(47592), // Rule ID 6070 //
        GIM_CheckRegBankForClass, /*MI*/0, /*Op*/0, /*RC*/GIMT_Encode2(AMDGPU::SReg_224RegClassID),
        GIM_CheckRegBankForClass, /*MI*/0, /*Op*/1, /*RC*/GIMT_Encode2(AMDGPU::SReg_224RegClassID),
        // (bitconvert:{ *:[v7i32] } SReg_224:{ *:[v7f32] }:$src0)  =>  SReg_224:{ *:[v7i32] }:$src0
        GIR_BuildMI, /*InsnID*/0, /*Opcode*/GIMT_Encode2(TargetOpcode::COPY),
        GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/0, // dst
        GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/1, // src0
        GIR_ConstrainOperandRC, /*InsnID*/0, /*Op*/0, GIMT_Encode2(AMDGPU::SReg_224RegClassID),
        GIR_EraseFromParent, /*InsnID*/0,
        // GIR_Coverage, 6070,
        GIR_Done,
      // Label 637: @47592
      GIM_Try, /*On fail goto*//*Label 638*/ GIMT_Encode4(47627), // Rule ID 6071 //
        GIM_CheckRegBankForClass, /*MI*/0, /*Op*/0, /*RC*/GIMT_Encode2(AMDGPU::SReg_224RegClassID),
        GIM_CheckRegBankForClass, /*MI*/0, /*Op*/1, /*RC*/GIMT_Encode2(AMDGPU::SReg_224RegClassID),
        // (bitconvert:{ *:[v7f32] } SReg_224:{ *:[v7i32] }:$src0)  =>  SReg_224:{ *:[v7f32] }:$src0
        GIR_BuildMI, /*InsnID*/0, /*Opcode*/GIMT_Encode2(TargetOpcode::COPY),
        GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/0, // dst
        GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/1, // src0
        GIR_ConstrainOperandRC, /*InsnID*/0, /*Op*/0, GIMT_Encode2(AMDGPU::SReg_224RegClassID),
        GIR_EraseFromParent, /*InsnID*/0,
        // GIR_Coverage, 6071,
        GIR_Done,
      // Label 638: @47627
      GIM_Try, /*On fail goto*//*Label 639*/ GIMT_Encode4(47662), // Rule ID 6072 //
        GIM_CheckRegBankForClass, /*MI*/0, /*Op*/0, /*RC*/GIMT_Encode2(AMDGPU::VReg_224RegClassID),
        GIM_CheckRegBankForClass, /*MI*/0, /*Op*/1, /*RC*/GIMT_Encode2(AMDGPU::VReg_224RegClassID),
        // (bitconvert:{ *:[v7i32] } VReg_224:{ *:[v7f32] }:$src0)  =>  VReg_224:{ *:[v7i32] }:$src0
        GIR_BuildMI, /*InsnID*/0, /*Opcode*/GIMT_Encode2(TargetOpcode::COPY),
        GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/0, // dst
        GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/1, // src0
        GIR_ConstrainOperandRC, /*InsnID*/0, /*Op*/0, GIMT_Encode2(AMDGPU::VReg_224RegClassID),
        GIR_EraseFromParent, /*InsnID*/0,
        // GIR_Coverage, 6072,
        GIR_Done,
      // Label 639: @47662
      GIM_Try, /*On fail goto*//*Label 640*/ GIMT_Encode4(47697), // Rule ID 6073 //
        GIM_CheckRegBankForClass, /*MI*/0, /*Op*/0, /*RC*/GIMT_Encode2(AMDGPU::VReg_224RegClassID),
        GIM_CheckRegBankForClass, /*MI*/0, /*Op*/1, /*RC*/GIMT_Encode2(AMDGPU::VReg_224RegClassID),
        // (bitconvert:{ *:[v7f32] } VReg_224:{ *:[v7i32] }:$src0)  =>  VReg_224:{ *:[v7f32] }:$src0
        GIR_BuildMI, /*InsnID*/0, /*Opcode*/GIMT_Encode2(TargetOpcode::COPY),
        GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/0, // dst
        GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/1, // src0
        GIR_ConstrainOperandRC, /*InsnID*/0, /*Op*/0, GIMT_Encode2(AMDGPU::VReg_224RegClassID),
        GIR_EraseFromParent, /*InsnID*/0,
        // GIR_Coverage, 6073,
        GIR_Done,
      // Label 640: @47697
      GIM_Reject,
    // Label 636: @47698
    GIM_Reject,
    // Label 475: @47699
    GIM_Try, /*On fail goto*//*Label 641*/ GIMT_Encode4(47738), // Rule ID 6008 //
      GIM_CheckType, /*MI*/0, /*Op*/1, /*Type*/GILLT_v4s32,
      GIM_CheckRegBankForClass, /*MI*/0, /*Op*/0, /*RC*/GIMT_Encode2(AMDGPU::SReg_128RegClassID),
      GIM_CheckRegBankForClass, /*MI*/0, /*Op*/1, /*RC*/GIMT_Encode2(AMDGPU::SReg_128RegClassID),
      // (bitconvert:{ *:[v8i16] } SReg_128:{ *:[v4i32] }:$src0)  =>  SReg_128:{ *:[v8i16] }:$src0
      GIR_BuildMI, /*InsnID*/0, /*Opcode*/GIMT_Encode2(TargetOpcode::COPY),
      GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/0, // dst
      GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/1, // src0
      GIR_ConstrainOperandRC, /*InsnID*/0, /*Op*/0, GIMT_Encode2(AMDGPU::SReg_128RegClassID),
      GIR_EraseFromParent, /*InsnID*/0,
      // GIR_Coverage, 6008,
      GIR_Done,
    // Label 641: @47738
    GIM_Try, /*On fail goto*//*Label 642*/ GIMT_Encode4(47777), // Rule ID 6010 //
      GIM_CheckType, /*MI*/0, /*Op*/1, /*Type*/GILLT_v4s32,
      GIM_CheckRegBankForClass, /*MI*/0, /*Op*/0, /*RC*/GIMT_Encode2(AMDGPU::VReg_128RegClassID),
      GIM_CheckRegBankForClass, /*MI*/0, /*Op*/1, /*RC*/GIMT_Encode2(AMDGPU::VReg_128RegClassID),
      // (bitconvert:{ *:[v8f16] } VReg_128:{ *:[v4f32] }:$src0)  =>  VReg_128:{ *:[v8f16] }:$src0
      GIR_BuildMI, /*InsnID*/0, /*Opcode*/GIMT_Encode2(TargetOpcode::COPY),
      GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/0, // dst
      GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/1, // src0
      GIR_ConstrainOperandRC, /*InsnID*/0, /*Op*/0, GIMT_Encode2(AMDGPU::VReg_128RegClassID),
      GIR_EraseFromParent, /*InsnID*/0,
      // GIR_Coverage, 6010,
      GIR_Done,
    // Label 642: @47777
    GIM_Try, /*On fail goto*//*Label 643*/ GIMT_Encode4(47816), // Rule ID 6011 //
      GIM_CheckType, /*MI*/0, /*Op*/1, /*Type*/GILLT_v4s32,
      GIM_CheckRegBankForClass, /*MI*/0, /*Op*/0, /*RC*/GIMT_Encode2(AMDGPU::VReg_128RegClassID),
      GIM_CheckRegBankForClass, /*MI*/0, /*Op*/1, /*RC*/GIMT_Encode2(AMDGPU::VReg_128RegClassID),
      // (bitconvert:{ *:[v8f16] } VReg_128:{ *:[v4i32] }:$src0)  =>  VReg_128:{ *:[v8f16] }:$src0
      GIR_BuildMI, /*InsnID*/0, /*Opcode*/GIMT_Encode2(TargetOpcode::COPY),
      GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/0, // dst
      GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/1, // src0
      GIR_ConstrainOperandRC, /*InsnID*/0, /*Op*/0, GIMT_Encode2(AMDGPU::VReg_128RegClassID),
      GIR_EraseFromParent, /*InsnID*/0,
      // GIR_Coverage, 6011,
      GIR_Done,
    // Label 643: @47816
    GIM_Try, /*On fail goto*//*Label 644*/ GIMT_Encode4(47855), // Rule ID 6014 //
      GIM_CheckType, /*MI*/0, /*Op*/1, /*Type*/GILLT_v8s16,
      GIM_CheckRegBankForClass, /*MI*/0, /*Op*/0, /*RC*/GIMT_Encode2(AMDGPU::VReg_128RegClassID),
      GIM_CheckRegBankForClass, /*MI*/0, /*Op*/1, /*RC*/GIMT_Encode2(AMDGPU::VReg_128RegClassID),
      // (bitconvert:{ *:[v8i16] } VReg_128:{ *:[v8f16] }:$src0)  =>  VReg_128:{ *:[v8i16] }:$src0
      GIR_BuildMI, /*InsnID*/0, /*Opcode*/GIMT_Encode2(TargetOpcode::COPY),
      GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/0, // dst
      GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/1, // src0
      GIR_ConstrainOperandRC, /*InsnID*/0, /*Op*/0, GIMT_Encode2(AMDGPU::VReg_128RegClassID),
      GIR_EraseFromParent, /*InsnID*/0,
      // GIR_Coverage, 6014,
      GIR_Done,
    // Label 644: @47855
    GIM_Try, /*On fail goto*//*Label 645*/ GIMT_Encode4(47894), // Rule ID 6015 //
      GIM_CheckType, /*MI*/0, /*Op*/1, /*Type*/GILLT_v8s16,
      GIM_CheckRegBankForClass, /*MI*/0, /*Op*/0, /*RC*/GIMT_Encode2(AMDGPU::VReg_128RegClassID),
      GIM_CheckRegBankForClass, /*MI*/0, /*Op*/1, /*RC*/GIMT_Encode2(AMDGPU::VReg_128RegClassID),
      // (bitconvert:{ *:[v8f16] } VReg_128:{ *:[v8i16] }:$src0)  =>  VReg_128:{ *:[v8f16] }:$src0
      GIR_BuildMI, /*InsnID*/0, /*Opcode*/GIMT_Encode2(TargetOpcode::COPY),
      GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/0, // dst
      GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/1, // src0
      GIR_ConstrainOperandRC, /*InsnID*/0, /*Op*/0, GIMT_Encode2(AMDGPU::VReg_128RegClassID),
      GIR_EraseFromParent, /*InsnID*/0,
      // GIR_Coverage, 6015,
      GIR_Done,
    // Label 645: @47894
    GIM_Try, /*On fail goto*//*Label 646*/ GIMT_Encode4(47933), // Rule ID 6017 //
      GIM_CheckType, /*MI*/0, /*Op*/1, /*Type*/GILLT_v4s32,
      GIM_CheckRegBankForClass, /*MI*/0, /*Op*/0, /*RC*/GIMT_Encode2(AMDGPU::VReg_128RegClassID),
      GIM_CheckRegBankForClass, /*MI*/0, /*Op*/1, /*RC*/GIMT_Encode2(AMDGPU::VReg_128RegClassID),
      // (bitconvert:{ *:[v8i16] } VReg_128:{ *:[v4f32] }:$src0)  =>  VReg_128:{ *:[v8i16] }:$src0
      GIR_BuildMI, /*InsnID*/0, /*Opcode*/GIMT_Encode2(TargetOpcode::COPY),
      GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/0, // dst
      GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/1, // src0
      GIR_ConstrainOperandRC, /*InsnID*/0, /*Op*/0, GIMT_Encode2(AMDGPU::VReg_128RegClassID),
      GIR_EraseFromParent, /*InsnID*/0,
      // GIR_Coverage, 6017,
      GIR_Done,
    // Label 646: @47933
    GIM_Try, /*On fail goto*//*Label 647*/ GIMT_Encode4(47972), // Rule ID 6018 //
      GIM_CheckType, /*MI*/0, /*Op*/1, /*Type*/GILLT_v8s16,
      GIM_CheckRegBankForClass, /*MI*/0, /*Op*/0, /*RC*/GIMT_Encode2(AMDGPU::SReg_128RegClassID),
      GIM_CheckRegBankForClass, /*MI*/0, /*Op*/1, /*RC*/GIMT_Encode2(AMDGPU::SReg_128RegClassID),
      // (bitconvert:{ *:[v8i16] } SReg_128:{ *:[v8f16] }:$src0)  =>  SReg_128:{ *:[v8i16] }:$src0
      GIR_BuildMI, /*InsnID*/0, /*Opcode*/GIMT_Encode2(TargetOpcode::COPY),
      GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/0, // dst
      GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/1, // src0
      GIR_ConstrainOperandRC, /*InsnID*/0, /*Op*/0, GIMT_Encode2(AMDGPU::SReg_128RegClassID),
      GIR_EraseFromParent, /*InsnID*/0,
      // GIR_Coverage, 6018,
      GIR_Done,
    // Label 647: @47972
    GIM_Try, /*On fail goto*//*Label 648*/ GIMT_Encode4(48011), // Rule ID 6019 //
      GIM_CheckType, /*MI*/0, /*Op*/1, /*Type*/GILLT_v2s64,
      GIM_CheckRegBankForClass, /*MI*/0, /*Op*/0, /*RC*/GIMT_Encode2(AMDGPU::SReg_128RegClassID),
      GIM_CheckRegBankForClass, /*MI*/0, /*Op*/1, /*RC*/GIMT_Encode2(AMDGPU::SReg_128RegClassID),
      // (bitconvert:{ *:[v8i16] } SReg_128:{ *:[v2i64] }:$src0)  =>  SReg_128:{ *:[v8i16] }:$src0
      GIR_BuildMI, /*InsnID*/0, /*Opcode*/GIMT_Encode2(TargetOpcode::COPY),
      GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/0, // dst
      GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/1, // src0
      GIR_ConstrainOperandRC, /*InsnID*/0, /*Op*/0, GIMT_Encode2(AMDGPU::SReg_128RegClassID),
      GIR_EraseFromParent, /*InsnID*/0,
      // GIR_Coverage, 6019,
      GIR_Done,
    // Label 648: @48011
    GIM_Try, /*On fail goto*//*Label 649*/ GIMT_Encode4(48050), // Rule ID 6020 //
      GIM_CheckType, /*MI*/0, /*Op*/1, /*Type*/GILLT_v2s64,
      GIM_CheckRegBankForClass, /*MI*/0, /*Op*/0, /*RC*/GIMT_Encode2(AMDGPU::SReg_128RegClassID),
      GIM_CheckRegBankForClass, /*MI*/0, /*Op*/1, /*RC*/GIMT_Encode2(AMDGPU::SReg_128RegClassID),
      // (bitconvert:{ *:[v8i16] } SReg_128:{ *:[v2f64] }:$src0)  =>  SReg_128:{ *:[v8i16] }:$src0
      GIR_BuildMI, /*InsnID*/0, /*Opcode*/GIMT_Encode2(TargetOpcode::COPY),
      GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/0, // dst
      GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/1, // src0
      GIR_ConstrainOperandRC, /*InsnID*/0, /*Op*/0, GIMT_Encode2(AMDGPU::SReg_128RegClassID),
      GIR_EraseFromParent, /*InsnID*/0,
      // GIR_Coverage, 6020,
      GIR_Done,
    // Label 649: @48050
    GIM_Try, /*On fail goto*//*Label 650*/ GIMT_Encode4(48089), // Rule ID 6021 //
      GIM_CheckType, /*MI*/0, /*Op*/1, /*Type*/GILLT_v2s64,
      GIM_CheckRegBankForClass, /*MI*/0, /*Op*/0, /*RC*/GIMT_Encode2(AMDGPU::SReg_128RegClassID),
      GIM_CheckRegBankForClass, /*MI*/0, /*Op*/1, /*RC*/GIMT_Encode2(AMDGPU::SReg_128RegClassID),
      // (bitconvert:{ *:[v8f16] } SReg_128:{ *:[v2i64] }:$src0)  =>  SReg_128:{ *:[v8f16] }:$src0
      GIR_BuildMI, /*InsnID*/0, /*Opcode*/GIMT_Encode2(TargetOpcode::COPY),
      GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/0, // dst
      GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/1, // src0
      GIR_ConstrainOperandRC, /*InsnID*/0, /*Op*/0, GIMT_Encode2(AMDGPU::SReg_128RegClassID),
      GIR_EraseFromParent, /*InsnID*/0,
      // GIR_Coverage, 6021,
      GIR_Done,
    // Label 650: @48089
    GIM_Try, /*On fail goto*//*Label 651*/ GIMT_Encode4(48128), // Rule ID 6022 //
      GIM_CheckType, /*MI*/0, /*Op*/1, /*Type*/GILLT_v2s64,
      GIM_CheckRegBankForClass, /*MI*/0, /*Op*/0, /*RC*/GIMT_Encode2(AMDGPU::SReg_128RegClassID),
      GIM_CheckRegBankForClass, /*MI*/0, /*Op*/1, /*RC*/GIMT_Encode2(AMDGPU::SReg_128RegClassID),
      // (bitconvert:{ *:[v8f16] } SReg_128:{ *:[v2f64] }:$src0)  =>  SReg_128:{ *:[v8f16] }:$src0
      GIR_BuildMI, /*InsnID*/0, /*Opcode*/GIMT_Encode2(TargetOpcode::COPY),
      GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/0, // dst
      GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/1, // src0
      GIR_ConstrainOperandRC, /*InsnID*/0, /*Op*/0, GIMT_Encode2(AMDGPU::SReg_128RegClassID),
      GIR_EraseFromParent, /*InsnID*/0,
      // GIR_Coverage, 6022,
      GIR_Done,
    // Label 651: @48128
    GIM_Try, /*On fail goto*//*Label 652*/ GIMT_Encode4(48167), // Rule ID 6023 //
      GIM_CheckType, /*MI*/0, /*Op*/1, /*Type*/GILLT_v8s16,
      GIM_CheckRegBankForClass, /*MI*/0, /*Op*/0, /*RC*/GIMT_Encode2(AMDGPU::SReg_128RegClassID),
      GIM_CheckRegBankForClass, /*MI*/0, /*Op*/1, /*RC*/GIMT_Encode2(AMDGPU::SReg_128RegClassID),
      // (bitconvert:{ *:[v8f16] } SReg_128:{ *:[v8i16] }:$src0)  =>  SReg_128:{ *:[v8f16] }:$src0
      GIR_BuildMI, /*InsnID*/0, /*Opcode*/GIMT_Encode2(TargetOpcode::COPY),
      GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/0, // dst
      GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/1, // src0
      GIR_ConstrainOperandRC, /*InsnID*/0, /*Op*/0, GIMT_Encode2(AMDGPU::SReg_128RegClassID),
      GIR_EraseFromParent, /*InsnID*/0,
      // GIR_Coverage, 6023,
      GIR_Done,
    // Label 652: @48167
    GIM_Try, /*On fail goto*//*Label 653*/ GIMT_Encode4(48206), // Rule ID 6029 //
      GIM_CheckType, /*MI*/0, /*Op*/1, /*Type*/GILLT_v4s32,
      GIM_CheckRegBankForClass, /*MI*/0, /*Op*/0, /*RC*/GIMT_Encode2(AMDGPU::SReg_128RegClassID),
      GIM_CheckRegBankForClass, /*MI*/0, /*Op*/1, /*RC*/GIMT_Encode2(AMDGPU::SReg_128RegClassID),
      // (bitconvert:{ *:[v8bf16] } SReg_128:{ *:[v4i32] }:$src0)  =>  SReg_128:{ *:[v8bf16] }:$src0
      GIR_BuildMI, /*InsnID*/0, /*Opcode*/GIMT_Encode2(TargetOpcode::COPY),
      GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/0, // dst
      GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/1, // src0
      GIR_ConstrainOperandRC, /*InsnID*/0, /*Op*/0, GIMT_Encode2(AMDGPU::SReg_128RegClassID),
      GIR_EraseFromParent, /*InsnID*/0,
      // GIR_Coverage, 6029,
      GIR_Done,
    // Label 653: @48206
    GIM_Try, /*On fail goto*//*Label 654*/ GIMT_Encode4(48245), // Rule ID 6031 //
      GIM_CheckType, /*MI*/0, /*Op*/1, /*Type*/GILLT_v4s32,
      GIM_CheckRegBankForClass, /*MI*/0, /*Op*/0, /*RC*/GIMT_Encode2(AMDGPU::VReg_128RegClassID),
      GIM_CheckRegBankForClass, /*MI*/0, /*Op*/1, /*RC*/GIMT_Encode2(AMDGPU::VReg_128RegClassID),
      // (bitconvert:{ *:[v8bf16] } VReg_128:{ *:[v4i32] }:$src0)  =>  VReg_128:{ *:[v8bf16] }:$src0
      GIR_BuildMI, /*InsnID*/0, /*Opcode*/GIMT_Encode2(TargetOpcode::COPY),
      GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/0, // dst
      GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/1, // src0
      GIR_ConstrainOperandRC, /*InsnID*/0, /*Op*/0, GIMT_Encode2(AMDGPU::VReg_128RegClassID),
      GIR_EraseFromParent, /*InsnID*/0,
      // GIR_Coverage, 6031,
      GIR_Done,
    // Label 654: @48245
    GIM_Try, /*On fail goto*//*Label 655*/ GIMT_Encode4(48284), // Rule ID 6033 //
      GIM_CheckType, /*MI*/0, /*Op*/1, /*Type*/GILLT_v4s32,
      GIM_CheckRegBankForClass, /*MI*/0, /*Op*/0, /*RC*/GIMT_Encode2(AMDGPU::SReg_128RegClassID),
      GIM_CheckRegBankForClass, /*MI*/0, /*Op*/1, /*RC*/GIMT_Encode2(AMDGPU::SReg_128RegClassID),
      // (bitconvert:{ *:[v8bf16] } SReg_128:{ *:[v4f32] }:$src0)  =>  SReg_128:{ *:[v8bf16] }:$src0
      GIR_BuildMI, /*InsnID*/0, /*Opcode*/GIMT_Encode2(TargetOpcode::COPY),
      GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/0, // dst
      GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/1, // src0
      GIR_ConstrainOperandRC, /*InsnID*/0, /*Op*/0, GIMT_Encode2(AMDGPU::SReg_128RegClassID),
      GIR_EraseFromParent, /*InsnID*/0,
      // GIR_Coverage, 6033,
      GIR_Done,
    // Label 655: @48284
    GIM_Try, /*On fail goto*//*Label 656*/ GIMT_Encode4(48323), // Rule ID 6035 //
      GIM_CheckType, /*MI*/0, /*Op*/1, /*Type*/GILLT_v4s32,
      GIM_CheckRegBankForClass, /*MI*/0, /*Op*/0, /*RC*/GIMT_Encode2(AMDGPU::VReg_128RegClassID),
      GIM_CheckRegBankForClass, /*MI*/0, /*Op*/1, /*RC*/GIMT_Encode2(AMDGPU::VReg_128RegClassID),
      // (bitconvert:{ *:[v8bf16] } VReg_128:{ *:[v4f32] }:$src0)  =>  VReg_128:{ *:[v8bf16] }:$src0
      GIR_BuildMI, /*InsnID*/0, /*Opcode*/GIMT_Encode2(TargetOpcode::COPY),
      GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/0, // dst
      GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/1, // src0
      GIR_ConstrainOperandRC, /*InsnID*/0, /*Op*/0, GIMT_Encode2(AMDGPU::VReg_128RegClassID),
      GIR_EraseFromParent, /*InsnID*/0,
      // GIR_Coverage, 6035,
      GIR_Done,
    // Label 656: @48323
    GIM_Try, /*On fail goto*//*Label 657*/ GIMT_Encode4(48362), // Rule ID 6036 //
      GIM_CheckType, /*MI*/0, /*Op*/1, /*Type*/GILLT_v8s16,
      GIM_CheckRegBankForClass, /*MI*/0, /*Op*/0, /*RC*/GIMT_Encode2(AMDGPU::SReg_128RegClassID),
      GIM_CheckRegBankForClass, /*MI*/0, /*Op*/1, /*RC*/GIMT_Encode2(AMDGPU::SReg_128RegClassID),
      // (bitconvert:{ *:[v8i16] } SReg_128:{ *:[v8bf16] }:$src0)  =>  SReg_128:{ *:[v8i16] }:$src0
      GIR_BuildMI, /*InsnID*/0, /*Opcode*/GIMT_Encode2(TargetOpcode::COPY),
      GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/0, // dst
      GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/1, // src0
      GIR_ConstrainOperandRC, /*InsnID*/0, /*Op*/0, GIMT_Encode2(AMDGPU::SReg_128RegClassID),
      GIR_EraseFromParent, /*InsnID*/0,
      // GIR_Coverage, 6036,
      GIR_Done,
    // Label 657: @48362
    GIM_Try, /*On fail goto*//*Label 658*/ GIMT_Encode4(48401), // Rule ID 6037 //
      GIM_CheckType, /*MI*/0, /*Op*/1, /*Type*/GILLT_v8s16,
      GIM_CheckRegBankForClass, /*MI*/0, /*Op*/0, /*RC*/GIMT_Encode2(AMDGPU::SReg_128RegClassID),
      GIM_CheckRegBankForClass, /*MI*/0, /*Op*/1, /*RC*/GIMT_Encode2(AMDGPU::SReg_128RegClassID),
      // (bitconvert:{ *:[v8bf16] } SReg_128:{ *:[v8i16] }:$src0)  =>  SReg_128:{ *:[v8bf16] }:$src0
      GIR_BuildMI, /*InsnID*/0, /*Opcode*/GIMT_Encode2(TargetOpcode::COPY),
      GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/0, // dst
      GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/1, // src0
      GIR_ConstrainOperandRC, /*InsnID*/0, /*Op*/0, GIMT_Encode2(AMDGPU::SReg_128RegClassID),
      GIR_EraseFromParent, /*InsnID*/0,
      // GIR_Coverage, 6037,
      GIR_Done,
    // Label 658: @48401
    GIM_Try, /*On fail goto*//*Label 659*/ GIMT_Encode4(48440), // Rule ID 6038 //
      GIM_CheckType, /*MI*/0, /*Op*/1, /*Type*/GILLT_v8s16,
      GIM_CheckRegBankForClass, /*MI*/0, /*Op*/0, /*RC*/GIMT_Encode2(AMDGPU::VReg_128RegClassID),
      GIM_CheckRegBankForClass, /*MI*/0, /*Op*/1, /*RC*/GIMT_Encode2(AMDGPU::VReg_128RegClassID),
      // (bitconvert:{ *:[v8i16] } VReg_128:{ *:[v8bf16] }:$src0)  =>  VReg_128:{ *:[v8i16] }:$src0
      GIR_BuildMI, /*InsnID*/0, /*Opcode*/GIMT_Encode2(TargetOpcode::COPY),
      GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/0, // dst
      GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/1, // src0
      GIR_ConstrainOperandRC, /*InsnID*/0, /*Op*/0, GIMT_Encode2(AMDGPU::VReg_128RegClassID),
      GIR_EraseFromParent, /*InsnID*/0,
      // GIR_Coverage, 6038,
      GIR_Done,
    // Label 659: @48440
    GIM_Try, /*On fail goto*//*Label 660*/ GIMT_Encode4(48479), // Rule ID 6039 //
      GIM_CheckType, /*MI*/0, /*Op*/1, /*Type*/GILLT_v8s16,
      GIM_CheckRegBankForClass, /*MI*/0, /*Op*/0, /*RC*/GIMT_Encode2(AMDGPU::VReg_128RegClassID),
      GIM_CheckRegBankForClass, /*MI*/0, /*Op*/1, /*RC*/GIMT_Encode2(AMDGPU::VReg_128RegClassID),
      // (bitconvert:{ *:[v8bf16] } VReg_128:{ *:[v8i16] }:$src0)  =>  VReg_128:{ *:[v8bf16] }:$src0
      GIR_BuildMI, /*InsnID*/0, /*Opcode*/GIMT_Encode2(TargetOpcode::COPY),
      GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/0, // dst
      GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/1, // src0
      GIR_ConstrainOperandRC, /*InsnID*/0, /*Op*/0, GIMT_Encode2(AMDGPU::VReg_128RegClassID),
      GIR_EraseFromParent, /*InsnID*/0,
      // GIR_Coverage, 6039,
      GIR_Done,
    // Label 660: @48479
    GIM_Try, /*On fail goto*//*Label 661*/ GIMT_Encode4(48518), // Rule ID 6040 //
      GIM_CheckType, /*MI*/0, /*Op*/1, /*Type*/GILLT_v8s16,
      GIM_CheckRegBankForClass, /*MI*/0, /*Op*/0, /*RC*/GIMT_Encode2(AMDGPU::SReg_128RegClassID),
      GIM_CheckRegBankForClass, /*MI*/0, /*Op*/1, /*RC*/GIMT_Encode2(AMDGPU::SReg_128RegClassID),
      // (bitconvert:{ *:[v8f16] } SReg_128:{ *:[v8bf16] }:$src0)  =>  SReg_128:{ *:[v8f16] }:$src0
      GIR_BuildMI, /*InsnID*/0, /*Opcode*/GIMT_Encode2(TargetOpcode::COPY),
      GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/0, // dst
      GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/1, // src0
      GIR_ConstrainOperandRC, /*InsnID*/0, /*Op*/0, GIMT_Encode2(AMDGPU::SReg_128RegClassID),
      GIR_EraseFromParent, /*InsnID*/0,
      // GIR_Coverage, 6040,
      GIR_Done,
    // Label 661: @48518
    GIM_Try, /*On fail goto*//*Label 662*/ GIMT_Encode4(48557), // Rule ID 6041 //
      GIM_CheckType, /*MI*/0, /*Op*/1, /*Type*/GILLT_v8s16,
      GIM_CheckRegBankForClass, /*MI*/0, /*Op*/0, /*RC*/GIMT_Encode2(AMDGPU::SReg_128RegClassID),
      GIM_CheckRegBankForClass, /*MI*/0, /*Op*/1, /*RC*/GIMT_Encode2(AMDGPU::SReg_128RegClassID),
      // (bitconvert:{ *:[v8bf16] } SReg_128:{ *:[v8f16] }:$src0)  =>  SReg_128:{ *:[v8bf16] }:$src0
      GIR_BuildMI, /*InsnID*/0, /*Opcode*/GIMT_Encode2(TargetOpcode::COPY),
      GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/0, // dst
      GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/1, // src0
      GIR_ConstrainOperandRC, /*InsnID*/0, /*Op*/0, GIMT_Encode2(AMDGPU::SReg_128RegClassID),
      GIR_EraseFromParent, /*InsnID*/0,
      // GIR_Coverage, 6041,
      GIR_Done,
    // Label 662: @48557
    GIM_Try, /*On fail goto*//*Label 663*/ GIMT_Encode4(48596), // Rule ID 6042 //
      GIM_CheckType, /*MI*/0, /*Op*/1, /*Type*/GILLT_v8s16,
      GIM_CheckRegBankForClass, /*MI*/0, /*Op*/0, /*RC*/GIMT_Encode2(AMDGPU::VReg_128RegClassID),
      GIM_CheckRegBankForClass, /*MI*/0, /*Op*/1, /*RC*/GIMT_Encode2(AMDGPU::VReg_128RegClassID),
      // (bitconvert:{ *:[v8f16] } VReg_128:{ *:[v8bf16] }:$src0)  =>  VReg_128:{ *:[v8f16] }:$src0
      GIR_BuildMI, /*InsnID*/0, /*Opcode*/GIMT_Encode2(TargetOpcode::COPY),
      GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/0, // dst
      GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/1, // src0
      GIR_ConstrainOperandRC, /*InsnID*/0, /*Op*/0, GIMT_Encode2(AMDGPU::VReg_128RegClassID),
      GIR_EraseFromParent, /*InsnID*/0,
      // GIR_Coverage, 6042,
      GIR_Done,
    // Label 663: @48596
    GIM_Try, /*On fail goto*//*Label 664*/ GIMT_Encode4(48635), // Rule ID 6043 //
      GIM_CheckType, /*MI*/0, /*Op*/1, /*Type*/GILLT_v8s16,
      GIM_CheckRegBankForClass, /*MI*/0, /*Op*/0, /*RC*/GIMT_Encode2(AMDGPU::VReg_128RegClassID),
      GIM_CheckRegBankForClass, /*MI*/0, /*Op*/1, /*RC*/GIMT_Encode2(AMDGPU::VReg_128RegClassID),
      // (bitconvert:{ *:[v8bf16] } VReg_128:{ *:[v8f16] }:$src0)  =>  VReg_128:{ *:[v8bf16] }:$src0
      GIR_BuildMI, /*InsnID*/0, /*Opcode*/GIMT_Encode2(TargetOpcode::COPY),
      GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/0, // dst
      GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/1, // src0
      GIR_ConstrainOperandRC, /*InsnID*/0, /*Op*/0, GIMT_Encode2(AMDGPU::VReg_128RegClassID),
      GIR_EraseFromParent, /*InsnID*/0,
      // GIR_Coverage, 6043,
      GIR_Done,
    // Label 664: @48635
    GIM_Try, /*On fail goto*//*Label 665*/ GIMT_Encode4(48674), // Rule ID 6045 //
      GIM_CheckType, /*MI*/0, /*Op*/1, /*Type*/GILLT_v2s64,
      GIM_CheckRegBankForClass, /*MI*/0, /*Op*/0, /*RC*/GIMT_Encode2(AMDGPU::SReg_128RegClassID),
      GIM_CheckRegBankForClass, /*MI*/0, /*Op*/1, /*RC*/GIMT_Encode2(AMDGPU::SReg_128RegClassID),
      // (bitconvert:{ *:[v8bf16] } SReg_128:{ *:[v2f64] }:$src0)  =>  SReg_128:{ *:[v8bf16] }:$src0
      GIR_BuildMI, /*InsnID*/0, /*Opcode*/GIMT_Encode2(TargetOpcode::COPY),
      GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/0, // dst
      GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/1, // src0
      GIR_ConstrainOperandRC, /*InsnID*/0, /*Op*/0, GIMT_Encode2(AMDGPU::SReg_128RegClassID),
      GIR_EraseFromParent, /*InsnID*/0,
      // GIR_Coverage, 6045,
      GIR_Done,
    // Label 665: @48674
    GIM_Try, /*On fail goto*//*Label 666*/ GIMT_Encode4(48713), // Rule ID 6047 //
      GIM_CheckType, /*MI*/0, /*Op*/1, /*Type*/GILLT_v2s64,
      GIM_CheckRegBankForClass, /*MI*/0, /*Op*/0, /*RC*/GIMT_Encode2(AMDGPU::VReg_128RegClassID),
      GIM_CheckRegBankForClass, /*MI*/0, /*Op*/1, /*RC*/GIMT_Encode2(AMDGPU::VReg_128RegClassID),
      // (bitconvert:{ *:[v8bf16] } VReg_128:{ *:[v2f64] }:$src0)  =>  VReg_128:{ *:[v8bf16] }:$src0
      GIR_BuildMI, /*InsnID*/0, /*Opcode*/GIMT_Encode2(TargetOpcode::COPY),
      GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/0, // dst
      GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/1, // src0
      GIR_ConstrainOperandRC, /*InsnID*/0, /*Op*/0, GIMT_Encode2(AMDGPU::VReg_128RegClassID),
      GIR_EraseFromParent, /*InsnID*/0,
      // GIR_Coverage, 6047,
      GIR_Done,
    // Label 666: @48713
    GIM_Try, /*On fail goto*//*Label 667*/ GIMT_Encode4(48752), // Rule ID 6049 //
      GIM_CheckType, /*MI*/0, /*Op*/1, /*Type*/GILLT_v2s64,
      GIM_CheckRegBankForClass, /*MI*/0, /*Op*/0, /*RC*/GIMT_Encode2(AMDGPU::SReg_128RegClassID),
      GIM_CheckRegBankForClass, /*MI*/0, /*Op*/1, /*RC*/GIMT_Encode2(AMDGPU::SReg_128RegClassID),
      // (bitconvert:{ *:[v8bf16] } SReg_128:{ *:[v2i64] }:$src0)  =>  SReg_128:{ *:[v8bf16] }:$src0
      GIR_BuildMI, /*InsnID*/0, /*Opcode*/GIMT_Encode2(TargetOpcode::COPY),
      GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/0, // dst
      GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/1, // src0
      GIR_ConstrainOperandRC, /*InsnID*/0, /*Op*/0, GIMT_Encode2(AMDGPU::SReg_128RegClassID),
      GIR_EraseFromParent, /*InsnID*/0,
      // GIR_Coverage, 6049,
      GIR_Done,
    // Label 667: @48752
    GIM_Try, /*On fail goto*//*Label 668*/ GIMT_Encode4(48791), // Rule ID 6051 //
      GIM_CheckType, /*MI*/0, /*Op*/1, /*Type*/GILLT_v2s64,
      GIM_CheckRegBankForClass, /*MI*/0, /*Op*/0, /*RC*/GIMT_Encode2(AMDGPU::VReg_128RegClassID),
      GIM_CheckRegBankForClass, /*MI*/0, /*Op*/1, /*RC*/GIMT_Encode2(AMDGPU::VReg_128RegClassID),
      // (bitconvert:{ *:[v8bf16] } VReg_128:{ *:[v2i64] }:$src0)  =>  VReg_128:{ *:[v8bf16] }:$src0
      GIR_BuildMI, /*InsnID*/0, /*Opcode*/GIMT_Encode2(TargetOpcode::COPY),
      GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/0, // dst
      GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/1, // src0
      GIR_ConstrainOperandRC, /*InsnID*/0, /*Op*/0, GIMT_Encode2(AMDGPU::VReg_128RegClassID),
      GIR_EraseFromParent, /*InsnID*/0,
      // GIR_Coverage, 6051,
      GIR_Done,
    // Label 668: @48791
    GIM_Reject,
    // Label 476: @48792
    GIM_Try, /*On fail goto*//*Label 669*/ GIMT_Encode4(48831), // Rule ID 6074 //
      GIM_CheckType, /*MI*/0, /*Op*/1, /*Type*/GILLT_v8s32,
      GIM_CheckRegBankForClass, /*MI*/0, /*Op*/0, /*RC*/GIMT_Encode2(AMDGPU::SReg_256RegClassID),
      GIM_CheckRegBankForClass, /*MI*/0, /*Op*/1, /*RC*/GIMT_Encode2(AMDGPU::SReg_256RegClassID),
      // (bitconvert:{ *:[v8i32] } SReg_256:{ *:[v8f32] }:$src0)  =>  SReg_256:{ *:[v8i32] }:$src0
      GIR_BuildMI, /*InsnID*/0, /*Opcode*/GIMT_Encode2(TargetOpcode::COPY),
      GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/0, // dst
      GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/1, // src0
      GIR_ConstrainOperandRC, /*InsnID*/0, /*Op*/0, GIMT_Encode2(AMDGPU::SReg_256RegClassID),
      GIR_EraseFromParent, /*InsnID*/0,
      // GIR_Coverage, 6074,
      GIR_Done,
    // Label 669: @48831
    GIM_Try, /*On fail goto*//*Label 670*/ GIMT_Encode4(48870), // Rule ID 6075 //
      GIM_CheckType, /*MI*/0, /*Op*/1, /*Type*/GILLT_v8s32,
      GIM_CheckRegBankForClass, /*MI*/0, /*Op*/0, /*RC*/GIMT_Encode2(AMDGPU::SReg_256RegClassID),
      GIM_CheckRegBankForClass, /*MI*/0, /*Op*/1, /*RC*/GIMT_Encode2(AMDGPU::SReg_256RegClassID),
      // (bitconvert:{ *:[v8f32] } SReg_256:{ *:[v8i32] }:$src0)  =>  SReg_256:{ *:[v8f32] }:$src0
      GIR_BuildMI, /*InsnID*/0, /*Opcode*/GIMT_Encode2(TargetOpcode::COPY),
      GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/0, // dst
      GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/1, // src0
      GIR_ConstrainOperandRC, /*InsnID*/0, /*Op*/0, GIMT_Encode2(AMDGPU::SReg_256RegClassID),
      GIR_EraseFromParent, /*InsnID*/0,
      // GIR_Coverage, 6075,
      GIR_Done,
    // Label 670: @48870
    GIM_Try, /*On fail goto*//*Label 671*/ GIMT_Encode4(48909), // Rule ID 6076 //
      GIM_CheckType, /*MI*/0, /*Op*/1, /*Type*/GILLT_v8s32,
      GIM_CheckRegBankForClass, /*MI*/0, /*Op*/0, /*RC*/GIMT_Encode2(AMDGPU::VReg_256RegClassID),
      GIM_CheckRegBankForClass, /*MI*/0, /*Op*/1, /*RC*/GIMT_Encode2(AMDGPU::VReg_256RegClassID),
      // (bitconvert:{ *:[v8i32] } VReg_256:{ *:[v8f32] }:$src0)  =>  VReg_256:{ *:[v8i32] }:$src0
      GIR_BuildMI, /*InsnID*/0, /*Opcode*/GIMT_Encode2(TargetOpcode::COPY),
      GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/0, // dst
      GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/1, // src0
      GIR_ConstrainOperandRC, /*InsnID*/0, /*Op*/0, GIMT_Encode2(AMDGPU::VReg_256RegClassID),
      GIR_EraseFromParent, /*InsnID*/0,
      // GIR_Coverage, 6076,
      GIR_Done,
    // Label 671: @48909
    GIM_Try, /*On fail goto*//*Label 672*/ GIMT_Encode4(48948), // Rule ID 6077 //
      GIM_CheckType, /*MI*/0, /*Op*/1, /*Type*/GILLT_v8s32,
      GIM_CheckRegBankForClass, /*MI*/0, /*Op*/0, /*RC*/GIMT_Encode2(AMDGPU::VReg_256RegClassID),
      GIM_CheckRegBankForClass, /*MI*/0, /*Op*/1, /*RC*/GIMT_Encode2(AMDGPU::VReg_256RegClassID),
      // (bitconvert:{ *:[v8f32] } VReg_256:{ *:[v8i32] }:$src0)  =>  VReg_256:{ *:[v8f32] }:$src0
      GIR_BuildMI, /*InsnID*/0, /*Opcode*/GIMT_Encode2(TargetOpcode::COPY),
      GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/0, // dst
      GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/1, // src0
      GIR_ConstrainOperandRC, /*InsnID*/0, /*Op*/0, GIMT_Encode2(AMDGPU::VReg_256RegClassID),
      GIR_EraseFromParent, /*InsnID*/0,
      // GIR_Coverage, 6077,
      GIR_Done,
    // Label 672: @48948
    GIM_Try, /*On fail goto*//*Label 673*/ GIMT_Encode4(48987), // Rule ID 6084 //
      GIM_CheckType, /*MI*/0, /*Op*/1, /*Type*/GILLT_v4s64,
      GIM_CheckRegBankForClass, /*MI*/0, /*Op*/0, /*RC*/GIMT_Encode2(AMDGPU::VReg_256RegClassID),
      GIM_CheckRegBankForClass, /*MI*/0, /*Op*/1, /*RC*/GIMT_Encode2(AMDGPU::VReg_256RegClassID),
      // (bitconvert:{ *:[v8i32] } VReg_256:{ *:[v4i64] }:$src0)  =>  VReg_256:{ *:[v8i32] }:$src0
      GIR_BuildMI, /*InsnID*/0, /*Opcode*/GIMT_Encode2(TargetOpcode::COPY),
      GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/0, // dst
      GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/1, // src0
      GIR_ConstrainOperandRC, /*InsnID*/0, /*Op*/0, GIMT_Encode2(AMDGPU::VReg_256RegClassID),
      GIR_EraseFromParent, /*InsnID*/0,
      // GIR_Coverage, 6084,
      GIR_Done,
    // Label 673: @48987
    GIM_Try, /*On fail goto*//*Label 674*/ GIMT_Encode4(49026), // Rule ID 6085 //
      GIM_CheckType, /*MI*/0, /*Op*/1, /*Type*/GILLT_v4s64,
      GIM_CheckRegBankForClass, /*MI*/0, /*Op*/0, /*RC*/GIMT_Encode2(AMDGPU::VReg_256RegClassID),
      GIM_CheckRegBankForClass, /*MI*/0, /*Op*/1, /*RC*/GIMT_Encode2(AMDGPU::VReg_256RegClassID),
      // (bitconvert:{ *:[v8f32] } VReg_256:{ *:[v4i64] }:$src0)  =>  VReg_256:{ *:[v8f32] }:$src0
      GIR_BuildMI, /*InsnID*/0, /*Opcode*/GIMT_Encode2(TargetOpcode::COPY),
      GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/0, // dst
      GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/1, // src0
      GIR_ConstrainOperandRC, /*InsnID*/0, /*Op*/0, GIMT_Encode2(AMDGPU::VReg_256RegClassID),
      GIR_EraseFromParent, /*InsnID*/0,
      // GIR_Coverage, 6085,
      GIR_Done,
    // Label 674: @49026
    GIM_Try, /*On fail goto*//*Label 675*/ GIMT_Encode4(49065), // Rule ID 6086 //
      GIM_CheckType, /*MI*/0, /*Op*/1, /*Type*/GILLT_v4s64,
      GIM_CheckRegBankForClass, /*MI*/0, /*Op*/0, /*RC*/GIMT_Encode2(AMDGPU::VReg_256RegClassID),
      GIM_CheckRegBankForClass, /*MI*/0, /*Op*/1, /*RC*/GIMT_Encode2(AMDGPU::VReg_256RegClassID),
      // (bitconvert:{ *:[v8i32] } VReg_256:{ *:[v4f64] }:$src0)  =>  VReg_256:{ *:[v8i32] }:$src0
      GIR_BuildMI, /*InsnID*/0, /*Opcode*/GIMT_Encode2(TargetOpcode::COPY),
      GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/0, // dst
      GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/1, // src0
      GIR_ConstrainOperandRC, /*InsnID*/0, /*Op*/0, GIMT_Encode2(AMDGPU::VReg_256RegClassID),
      GIR_EraseFromParent, /*InsnID*/0,
      // GIR_Coverage, 6086,
      GIR_Done,
    // Label 675: @49065
    GIM_Try, /*On fail goto*//*Label 676*/ GIMT_Encode4(49104), // Rule ID 6087 //
      GIM_CheckType, /*MI*/0, /*Op*/1, /*Type*/GILLT_v4s64,
      GIM_CheckRegBankForClass, /*MI*/0, /*Op*/0, /*RC*/GIMT_Encode2(AMDGPU::VReg_256RegClassID),
      GIM_CheckRegBankForClass, /*MI*/0, /*Op*/1, /*RC*/GIMT_Encode2(AMDGPU::VReg_256RegClassID),
      // (bitconvert:{ *:[v8f32] } VReg_256:{ *:[v4f64] }:$src0)  =>  VReg_256:{ *:[v8f32] }:$src0
      GIR_BuildMI, /*InsnID*/0, /*Opcode*/GIMT_Encode2(TargetOpcode::COPY),
      GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/0, // dst
      GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/1, // src0
      GIR_ConstrainOperandRC, /*InsnID*/0, /*Op*/0, GIMT_Encode2(AMDGPU::VReg_256RegClassID),
      GIR_EraseFromParent, /*InsnID*/0,
      // GIR_Coverage, 6087,
      GIR_Done,
    // Label 676: @49104
    GIM_Try, /*On fail goto*//*Label 677*/ GIMT_Encode4(49143), // Rule ID 6096 //
      GIM_CheckType, /*MI*/0, /*Op*/1, /*Type*/GILLT_v16s16,
      GIM_CheckRegBankForClass, /*MI*/0, /*Op*/0, /*RC*/GIMT_Encode2(AMDGPU::VReg_256RegClassID),
      GIM_CheckRegBankForClass, /*MI*/0, /*Op*/1, /*RC*/GIMT_Encode2(AMDGPU::VReg_256RegClassID),
      // (bitconvert:{ *:[v8i32] } VReg_256:{ *:[v16f16] }:$src0)  =>  VReg_256:{ *:[v8i32] }:$src0
      GIR_BuildMI, /*InsnID*/0, /*Opcode*/GIMT_Encode2(TargetOpcode::COPY),
      GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/0, // dst
      GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/1, // src0
      GIR_ConstrainOperandRC, /*InsnID*/0, /*Op*/0, GIMT_Encode2(AMDGPU::VReg_256RegClassID),
      GIR_EraseFromParent, /*InsnID*/0,
      // GIR_Coverage, 6096,
      GIR_Done,
    // Label 677: @49143
    GIM_Try, /*On fail goto*//*Label 678*/ GIMT_Encode4(49182), // Rule ID 6097 //
      GIM_CheckType, /*MI*/0, /*Op*/1, /*Type*/GILLT_v16s16,
      GIM_CheckRegBankForClass, /*MI*/0, /*Op*/0, /*RC*/GIMT_Encode2(AMDGPU::VReg_256RegClassID),
      GIM_CheckRegBankForClass, /*MI*/0, /*Op*/1, /*RC*/GIMT_Encode2(AMDGPU::VReg_256RegClassID),
      // (bitconvert:{ *:[v8i32] } VReg_256:{ *:[v16i16] }:$src0)  =>  VReg_256:{ *:[v8i32] }:$src0
      GIR_BuildMI, /*InsnID*/0, /*Opcode*/GIMT_Encode2(TargetOpcode::COPY),
      GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/0, // dst
      GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/1, // src0
      GIR_ConstrainOperandRC, /*InsnID*/0, /*Op*/0, GIMT_Encode2(AMDGPU::VReg_256RegClassID),
      GIR_EraseFromParent, /*InsnID*/0,
      // GIR_Coverage, 6097,
      GIR_Done,
    // Label 678: @49182
    GIM_Try, /*On fail goto*//*Label 679*/ GIMT_Encode4(49221), // Rule ID 6098 //
      GIM_CheckType, /*MI*/0, /*Op*/1, /*Type*/GILLT_v16s16,
      GIM_CheckRegBankForClass, /*MI*/0, /*Op*/0, /*RC*/GIMT_Encode2(AMDGPU::VReg_256RegClassID),
      GIM_CheckRegBankForClass, /*MI*/0, /*Op*/1, /*RC*/GIMT_Encode2(AMDGPU::VReg_256RegClassID),
      // (bitconvert:{ *:[v8f32] } VReg_256:{ *:[v16f16] }:$src0)  =>  VReg_256:{ *:[v8f32] }:$src0
      GIR_BuildMI, /*InsnID*/0, /*Opcode*/GIMT_Encode2(TargetOpcode::COPY),
      GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/0, // dst
      GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/1, // src0
      GIR_ConstrainOperandRC, /*InsnID*/0, /*Op*/0, GIMT_Encode2(AMDGPU::VReg_256RegClassID),
      GIR_EraseFromParent, /*InsnID*/0,
      // GIR_Coverage, 6098,
      GIR_Done,
    // Label 679: @49221
    GIM_Try, /*On fail goto*//*Label 680*/ GIMT_Encode4(49260), // Rule ID 6099 //
      GIM_CheckType, /*MI*/0, /*Op*/1, /*Type*/GILLT_v16s16,
      GIM_CheckRegBankForClass, /*MI*/0, /*Op*/0, /*RC*/GIMT_Encode2(AMDGPU::VReg_256RegClassID),
      GIM_CheckRegBankForClass, /*MI*/0, /*Op*/1, /*RC*/GIMT_Encode2(AMDGPU::VReg_256RegClassID),
      // (bitconvert:{ *:[v8f32] } VReg_256:{ *:[v16i16] }:$src0)  =>  VReg_256:{ *:[v8f32] }:$src0
      GIR_BuildMI, /*InsnID*/0, /*Opcode*/GIMT_Encode2(TargetOpcode::COPY),
      GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/0, // dst
      GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/1, // src0
      GIR_ConstrainOperandRC, /*InsnID*/0, /*Op*/0, GIMT_Encode2(AMDGPU::VReg_256RegClassID),
      GIR_EraseFromParent, /*InsnID*/0,
      // GIR_Coverage, 6099,
      GIR_Done,
    // Label 680: @49260
    GIM_Try, /*On fail goto*//*Label 681*/ GIMT_Encode4(49299), // Rule ID 6108 //
      GIM_CheckType, /*MI*/0, /*Op*/1, /*Type*/GILLT_v16s16,
      GIM_CheckRegBankForClass, /*MI*/0, /*Op*/0, /*RC*/GIMT_Encode2(AMDGPU::VReg_256RegClassID),
      GIM_CheckRegBankForClass, /*MI*/0, /*Op*/1, /*RC*/GIMT_Encode2(AMDGPU::VReg_256RegClassID),
      // (bitconvert:{ *:[v8i32] } VReg_256:{ *:[v16bf16] }:$src0)  =>  VReg_256:{ *:[v8i32] }:$src0
      GIR_BuildMI, /*InsnID*/0, /*Opcode*/GIMT_Encode2(TargetOpcode::COPY),
      GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/0, // dst
      GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/1, // src0
      GIR_ConstrainOperandRC, /*InsnID*/0, /*Op*/0, GIMT_Encode2(AMDGPU::VReg_256RegClassID),
      GIR_EraseFromParent, /*InsnID*/0,
      // GIR_Coverage, 6108,
      GIR_Done,
    // Label 681: @49299
    GIM_Try, /*On fail goto*//*Label 682*/ GIMT_Encode4(49338), // Rule ID 6110 //
      GIM_CheckType, /*MI*/0, /*Op*/1, /*Type*/GILLT_v16s16,
      GIM_CheckRegBankForClass, /*MI*/0, /*Op*/0, /*RC*/GIMT_Encode2(AMDGPU::VReg_256RegClassID),
      GIM_CheckRegBankForClass, /*MI*/0, /*Op*/1, /*RC*/GIMT_Encode2(AMDGPU::VReg_256RegClassID),
      // (bitconvert:{ *:[v8f32] } VReg_256:{ *:[v16bf16] }:$src0)  =>  VReg_256:{ *:[v8f32] }:$src0
      GIR_BuildMI, /*InsnID*/0, /*Opcode*/GIMT_Encode2(TargetOpcode::COPY),
      GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/0, // dst
      GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/1, // src0
      GIR_ConstrainOperandRC, /*InsnID*/0, /*Op*/0, GIMT_Encode2(AMDGPU::VReg_256RegClassID),
      GIR_EraseFromParent, /*InsnID*/0,
      // GIR_Coverage, 6110,
      GIR_Done,
    // Label 682: @49338
    GIM_Reject,
    // Label 477: @49339
    GIM_Try, /*On fail goto*//*Label 683*/ GIMT_Encode4(49378), // Rule ID 6152 //
      GIM_CheckType, /*MI*/0, /*Op*/1, /*Type*/GILLT_v8s64,
      GIM_CheckRegBankForClass, /*MI*/0, /*Op*/0, /*RC*/GIMT_Encode2(AMDGPU::VReg_512RegClassID),
      GIM_CheckRegBankForClass, /*MI*/0, /*Op*/1, /*RC*/GIMT_Encode2(AMDGPU::VReg_512RegClassID),
      // (bitconvert:{ *:[v8i64] } VReg_512:{ *:[v8f64] }:$src0)  =>  VReg_512:{ *:[v8i64] }:$src0
      GIR_BuildMI, /*InsnID*/0, /*Opcode*/GIMT_Encode2(TargetOpcode::COPY),
      GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/0, // dst
      GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/1, // src0
      GIR_ConstrainOperandRC, /*InsnID*/0, /*Op*/0, GIMT_Encode2(AMDGPU::VReg_512RegClassID),
      GIR_EraseFromParent, /*InsnID*/0,
      // GIR_Coverage, 6152,
      GIR_Done,
    // Label 683: @49378
    GIM_Try, /*On fail goto*//*Label 684*/ GIMT_Encode4(49417), // Rule ID 6153 //
      GIM_CheckType, /*MI*/0, /*Op*/1, /*Type*/GILLT_v8s64,
      GIM_CheckRegBankForClass, /*MI*/0, /*Op*/0, /*RC*/GIMT_Encode2(AMDGPU::VReg_512RegClassID),
      GIM_CheckRegBankForClass, /*MI*/0, /*Op*/1, /*RC*/GIMT_Encode2(AMDGPU::VReg_512RegClassID),
      // (bitconvert:{ *:[v8f64] } VReg_512:{ *:[v8i64] }:$src0)  =>  VReg_512:{ *:[v8f64] }:$src0
      GIR_BuildMI, /*InsnID*/0, /*Opcode*/GIMT_Encode2(TargetOpcode::COPY),
      GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/0, // dst
      GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/1, // src0
      GIR_ConstrainOperandRC, /*InsnID*/0, /*Op*/0, GIMT_Encode2(AMDGPU::VReg_512RegClassID),
      GIR_EraseFromParent, /*InsnID*/0,
      // GIR_Coverage, 6153,
      GIR_Done,
    // Label 684: @49417
    GIM_Try, /*On fail goto*//*Label 685*/ GIMT_Encode4(49456), // Rule ID 6154 //
      GIM_CheckType, /*MI*/0, /*Op*/1, /*Type*/GILLT_v16s32,
      GIM_CheckRegBankForClass, /*MI*/0, /*Op*/0, /*RC*/GIMT_Encode2(AMDGPU::VReg_512RegClassID),
      GIM_CheckRegBankForClass, /*MI*/0, /*Op*/1, /*RC*/GIMT_Encode2(AMDGPU::VReg_512RegClassID),
      // (bitconvert:{ *:[v8i64] } VReg_512:{ *:[v16i32] }:$src0)  =>  VReg_512:{ *:[v8i64] }:$src0
      GIR_BuildMI, /*InsnID*/0, /*Opcode*/GIMT_Encode2(TargetOpcode::COPY),
      GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/0, // dst
      GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/1, // src0
      GIR_ConstrainOperandRC, /*InsnID*/0, /*Op*/0, GIMT_Encode2(AMDGPU::VReg_512RegClassID),
      GIR_EraseFromParent, /*InsnID*/0,
      // GIR_Coverage, 6154,
      GIR_Done,
    // Label 685: @49456
    GIM_Try, /*On fail goto*//*Label 686*/ GIMT_Encode4(49495), // Rule ID 6155 //
      GIM_CheckType, /*MI*/0, /*Op*/1, /*Type*/GILLT_v16s32,
      GIM_CheckRegBankForClass, /*MI*/0, /*Op*/0, /*RC*/GIMT_Encode2(AMDGPU::VReg_512RegClassID),
      GIM_CheckRegBankForClass, /*MI*/0, /*Op*/1, /*RC*/GIMT_Encode2(AMDGPU::VReg_512RegClassID),
      // (bitconvert:{ *:[v8f64] } VReg_512:{ *:[v16i32] }:$src0)  =>  VReg_512:{ *:[v8f64] }:$src0
      GIR_BuildMI, /*InsnID*/0, /*Opcode*/GIMT_Encode2(TargetOpcode::COPY),
      GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/0, // dst
      GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/1, // src0
      GIR_ConstrainOperandRC, /*InsnID*/0, /*Op*/0, GIMT_Encode2(AMDGPU::VReg_512RegClassID),
      GIR_EraseFromParent, /*InsnID*/0,
      // GIR_Coverage, 6155,
      GIR_Done,
    // Label 686: @49495
    GIM_Try, /*On fail goto*//*Label 687*/ GIMT_Encode4(49534), // Rule ID 6158 //
      GIM_CheckType, /*MI*/0, /*Op*/1, /*Type*/GILLT_v16s32,
      GIM_CheckRegBankForClass, /*MI*/0, /*Op*/0, /*RC*/GIMT_Encode2(AMDGPU::VReg_512RegClassID),
      GIM_CheckRegBankForClass, /*MI*/0, /*Op*/1, /*RC*/GIMT_Encode2(AMDGPU::VReg_512RegClassID),
      // (bitconvert:{ *:[v8i64] } VReg_512:{ *:[v16f32] }:$src0)  =>  VReg_512:{ *:[v8i64] }:$src0
      GIR_BuildMI, /*InsnID*/0, /*Opcode*/GIMT_Encode2(TargetOpcode::COPY),
      GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/0, // dst
      GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/1, // src0
      GIR_ConstrainOperandRC, /*InsnID*/0, /*Op*/0, GIMT_Encode2(AMDGPU::VReg_512RegClassID),
      GIR_EraseFromParent, /*InsnID*/0,
      // GIR_Coverage, 6158,
      GIR_Done,
    // Label 687: @49534
    GIM_Try, /*On fail goto*//*Label 688*/ GIMT_Encode4(49573), // Rule ID 6159 //
      GIM_CheckType, /*MI*/0, /*Op*/1, /*Type*/GILLT_v16s32,
      GIM_CheckRegBankForClass, /*MI*/0, /*Op*/0, /*RC*/GIMT_Encode2(AMDGPU::VReg_512RegClassID),
      GIM_CheckRegBankForClass, /*MI*/0, /*Op*/1, /*RC*/GIMT_Encode2(AMDGPU::VReg_512RegClassID),
      // (bitconvert:{ *:[v8f64] } VReg_512:{ *:[v16f32] }:$src0)  =>  VReg_512:{ *:[v8f64] }:$src0
      GIR_BuildMI, /*InsnID*/0, /*Opcode*/GIMT_Encode2(TargetOpcode::COPY),
      GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/0, // dst
      GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/1, // src0
      GIR_ConstrainOperandRC, /*InsnID*/0, /*Op*/0, GIMT_Encode2(AMDGPU::VReg_512RegClassID),
      GIR_EraseFromParent, /*InsnID*/0,
      // GIR_Coverage, 6159,
      GIR_Done,
    // Label 688: @49573
    GIM_Try, /*On fail goto*//*Label 689*/ GIMT_Encode4(49612), // Rule ID 6179 //
      GIM_CheckType, /*MI*/0, /*Op*/1, /*Type*/GILLT_v32s16,
      GIM_CheckRegBankForClass, /*MI*/0, /*Op*/0, /*RC*/GIMT_Encode2(AMDGPU::VReg_512RegClassID),
      GIM_CheckRegBankForClass, /*MI*/0, /*Op*/1, /*RC*/GIMT_Encode2(AMDGPU::VReg_512RegClassID),
      // (bitconvert:{ *:[v8f64] } VReg_512:{ *:[v32bf16] }:$src0)  =>  VReg_512:{ *:[v8f64] }:$src0
      GIR_BuildMI, /*InsnID*/0, /*Opcode*/GIMT_Encode2(TargetOpcode::COPY),
      GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/0, // dst
      GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/1, // src0
      GIR_ConstrainOperandRC, /*InsnID*/0, /*Op*/0, GIMT_Encode2(AMDGPU::VReg_512RegClassID),
      GIR_EraseFromParent, /*InsnID*/0,
      // GIR_Coverage, 6179,
      GIR_Done,
    // Label 689: @49612
    GIM_Try, /*On fail goto*//*Label 690*/ GIMT_Encode4(49651), // Rule ID 6181 //
      GIM_CheckType, /*MI*/0, /*Op*/1, /*Type*/GILLT_v32s16,
      GIM_CheckRegBankForClass, /*MI*/0, /*Op*/0, /*RC*/GIMT_Encode2(AMDGPU::SReg_512RegClassID),
      GIM_CheckRegBankForClass, /*MI*/0, /*Op*/1, /*RC*/GIMT_Encode2(AMDGPU::SReg_512RegClassID),
      // (bitconvert:{ *:[v8f64] } SReg_512:{ *:[v32bf16] }:$src0)  =>  SReg_512:{ *:[v8f64] }:$src0
      GIR_BuildMI, /*InsnID*/0, /*Opcode*/GIMT_Encode2(TargetOpcode::COPY),
      GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/0, // dst
      GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/1, // src0
      GIR_ConstrainOperandRC, /*InsnID*/0, /*Op*/0, GIMT_Encode2(AMDGPU::SReg_512RegClassID),
      GIR_EraseFromParent, /*InsnID*/0,
      // GIR_Coverage, 6181,
      GIR_Done,
    // Label 690: @49651
    GIM_Try, /*On fail goto*//*Label 691*/ GIMT_Encode4(49690), // Rule ID 6183 //
      GIM_CheckType, /*MI*/0, /*Op*/1, /*Type*/GILLT_v32s16,
      GIM_CheckRegBankForClass, /*MI*/0, /*Op*/0, /*RC*/GIMT_Encode2(AMDGPU::VReg_512RegClassID),
      GIM_CheckRegBankForClass, /*MI*/0, /*Op*/1, /*RC*/GIMT_Encode2(AMDGPU::VReg_512RegClassID),
      // (bitconvert:{ *:[v8i64] } VReg_512:{ *:[v32bf16] }:$src0)  =>  VReg_512:{ *:[v8i64] }:$src0
      GIR_BuildMI, /*InsnID*/0, /*Opcode*/GIMT_Encode2(TargetOpcode::COPY),
      GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/0, // dst
      GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/1, // src0
      GIR_ConstrainOperandRC, /*InsnID*/0, /*Op*/0, GIMT_Encode2(AMDGPU::VReg_512RegClassID),
      GIR_EraseFromParent, /*InsnID*/0,
      // GIR_Coverage, 6183,
      GIR_Done,
    // Label 691: @49690
    GIM_Try, /*On fail goto*//*Label 692*/ GIMT_Encode4(49729), // Rule ID 6185 //
      GIM_CheckType, /*MI*/0, /*Op*/1, /*Type*/GILLT_v32s16,
      GIM_CheckRegBankForClass, /*MI*/0, /*Op*/0, /*RC*/GIMT_Encode2(AMDGPU::SReg_512RegClassID),
      GIM_CheckRegBankForClass, /*MI*/0, /*Op*/1, /*RC*/GIMT_Encode2(AMDGPU::SReg_512RegClassID),
      // (bitconvert:{ *:[v8i64] } SReg_512:{ *:[v32bf16] }:$src0)  =>  SReg_512:{ *:[v8i64] }:$src0
      GIR_BuildMI, /*InsnID*/0, /*Opcode*/GIMT_Encode2(TargetOpcode::COPY),
      GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/0, // dst
      GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/1, // src0
      GIR_ConstrainOperandRC, /*InsnID*/0, /*Op*/0, GIMT_Encode2(AMDGPU::SReg_512RegClassID),
      GIR_EraseFromParent, /*InsnID*/0,
      // GIR_Coverage, 6185,
      GIR_Done,
    // Label 692: @49729
    GIM_Reject,
    // Label 478: @49730
    GIM_Try, /*On fail goto*//*Label 693*/ GIMT_Encode4(49880),
      GIM_CheckType, /*MI*/0, /*Op*/1, /*Type*/GILLT_v9s32,
      GIM_Try, /*On fail goto*//*Label 694*/ GIMT_Encode4(49774), // Rule ID 6124 //
        GIM_CheckRegBankForClass, /*MI*/0, /*Op*/0, /*RC*/GIMT_Encode2(AMDGPU::SReg_288RegClassID),
        GIM_CheckRegBankForClass, /*MI*/0, /*Op*/1, /*RC*/GIMT_Encode2(AMDGPU::SReg_288RegClassID),
        // (bitconvert:{ *:[v9i32] } SReg_288:{ *:[v9f32] }:$src0)  =>  SReg_288:{ *:[v9i32] }:$src0
        GIR_BuildMI, /*InsnID*/0, /*Opcode*/GIMT_Encode2(TargetOpcode::COPY),
        GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/0, // dst
        GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/1, // src0
        GIR_ConstrainOperandRC, /*InsnID*/0, /*Op*/0, GIMT_Encode2(AMDGPU::SReg_288RegClassID),
        GIR_EraseFromParent, /*InsnID*/0,
        // GIR_Coverage, 6124,
        GIR_Done,
      // Label 694: @49774
      GIM_Try, /*On fail goto*//*Label 695*/ GIMT_Encode4(49809), // Rule ID 6125 //
        GIM_CheckRegBankForClass, /*MI*/0, /*Op*/0, /*RC*/GIMT_Encode2(AMDGPU::SReg_288RegClassID),
        GIM_CheckRegBankForClass, /*MI*/0, /*Op*/1, /*RC*/GIMT_Encode2(AMDGPU::SReg_288RegClassID),
        // (bitconvert:{ *:[v9f32] } SReg_288:{ *:[v9i32] }:$src0)  =>  SReg_288:{ *:[v9f32] }:$src0
        GIR_BuildMI, /*InsnID*/0, /*Opcode*/GIMT_Encode2(TargetOpcode::COPY),
        GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/0, // dst
        GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/1, // src0
        GIR_ConstrainOperandRC, /*InsnID*/0, /*Op*/0, GIMT_Encode2(AMDGPU::SReg_288RegClassID),
        GIR_EraseFromParent, /*InsnID*/0,
        // GIR_Coverage, 6125,
        GIR_Done,
      // Label 695: @49809
      GIM_Try, /*On fail goto*//*Label 696*/ GIMT_Encode4(49844), // Rule ID 6126 //
        GIM_CheckRegBankForClass, /*MI*/0, /*Op*/0, /*RC*/GIMT_Encode2(AMDGPU::VReg_288RegClassID),
        GIM_CheckRegBankForClass, /*MI*/0, /*Op*/1, /*RC*/GIMT_Encode2(AMDGPU::VReg_288RegClassID),
        // (bitconvert:{ *:[v9i32] } VReg_288:{ *:[v9f32] }:$src0)  =>  VReg_288:{ *:[v9i32] }:$src0
        GIR_BuildMI, /*InsnID*/0, /*Opcode*/GIMT_Encode2(TargetOpcode::COPY),
        GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/0, // dst
        GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/1, // src0
        GIR_ConstrainOperandRC, /*InsnID*/0, /*Op*/0, GIMT_Encode2(AMDGPU::VReg_288RegClassID),
        GIR_EraseFromParent, /*InsnID*/0,
        // GIR_Coverage, 6126,
        GIR_Done,
      // Label 696: @49844
      GIM_Try, /*On fail goto*//*Label 697*/ GIMT_Encode4(49879), // Rule ID 6127 //
        GIM_CheckRegBankForClass, /*MI*/0, /*Op*/0, /*RC*/GIMT_Encode2(AMDGPU::VReg_288RegClassID),
        GIM_CheckRegBankForClass, /*MI*/0, /*Op*/1, /*RC*/GIMT_Encode2(AMDGPU::VReg_288RegClassID),
        // (bitconvert:{ *:[v9f32] } VReg_288:{ *:[v9i32] }:$src0)  =>  VReg_288:{ *:[v9f32] }:$src0
        GIR_BuildMI, /*InsnID*/0, /*Opcode*/GIMT_Encode2(TargetOpcode::COPY),
        GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/0, // dst
        GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/1, // src0
        GIR_ConstrainOperandRC, /*InsnID*/0, /*Op*/0, GIMT_Encode2(AMDGPU::VReg_288RegClassID),
        GIR_EraseFromParent, /*InsnID*/0,
        // GIR_Coverage, 6127,
        GIR_Done,
      // Label 697: @49879
      GIM_Reject,
    // Label 693: @49880
    GIM_Reject,
    // Label 479: @49881
    GIM_Try, /*On fail goto*//*Label 698*/ GIMT_Encode4(50031),
      GIM_CheckType, /*MI*/0, /*Op*/1, /*Type*/GILLT_v10s32,
      GIM_Try, /*On fail goto*//*Label 699*/ GIMT_Encode4(49925), // Rule ID 6128 //
        GIM_CheckRegBankForClass, /*MI*/0, /*Op*/0, /*RC*/GIMT_Encode2(AMDGPU::SReg_320RegClassID),
        GIM_CheckRegBankForClass, /*MI*/0, /*Op*/1, /*RC*/GIMT_Encode2(AMDGPU::SReg_320RegClassID),
        // (bitconvert:{ *:[v10i32] } SReg_320:{ *:[v10f32] }:$src0)  =>  SReg_320:{ *:[v10i32] }:$src0
        GIR_BuildMI, /*InsnID*/0, /*Opcode*/GIMT_Encode2(TargetOpcode::COPY),
        GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/0, // dst
        GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/1, // src0
        GIR_ConstrainOperandRC, /*InsnID*/0, /*Op*/0, GIMT_Encode2(AMDGPU::SReg_320RegClassID),
        GIR_EraseFromParent, /*InsnID*/0,
        // GIR_Coverage, 6128,
        GIR_Done,
      // Label 699: @49925
      GIM_Try, /*On fail goto*//*Label 700*/ GIMT_Encode4(49960), // Rule ID 6129 //
        GIM_CheckRegBankForClass, /*MI*/0, /*Op*/0, /*RC*/GIMT_Encode2(AMDGPU::SReg_320RegClassID),
        GIM_CheckRegBankForClass, /*MI*/0, /*Op*/1, /*RC*/GIMT_Encode2(AMDGPU::SReg_320RegClassID),
        // (bitconvert:{ *:[v10f32] } SReg_320:{ *:[v10i32] }:$src0)  =>  SReg_320:{ *:[v10f32] }:$src0
        GIR_BuildMI, /*InsnID*/0, /*Opcode*/GIMT_Encode2(TargetOpcode::COPY),
        GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/0, // dst
        GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/1, // src0
        GIR_ConstrainOperandRC, /*InsnID*/0, /*Op*/0, GIMT_Encode2(AMDGPU::SReg_320RegClassID),
        GIR_EraseFromParent, /*InsnID*/0,
        // GIR_Coverage, 6129,
        GIR_Done,
      // Label 700: @49960
      GIM_Try, /*On fail goto*//*Label 701*/ GIMT_Encode4(49995), // Rule ID 6130 //
        GIM_CheckRegBankForClass, /*MI*/0, /*Op*/0, /*RC*/GIMT_Encode2(AMDGPU::VReg_320RegClassID),
        GIM_CheckRegBankForClass, /*MI*/0, /*Op*/1, /*RC*/GIMT_Encode2(AMDGPU::VReg_320RegClassID),
        // (bitconvert:{ *:[v10i32] } VReg_320:{ *:[v10f32] }:$src0)  =>  VReg_320:{ *:[v10i32] }:$src0
        GIR_BuildMI, /*InsnID*/0, /*Opcode*/GIMT_Encode2(TargetOpcode::COPY),
        GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/0, // dst
        GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/1, // src0
        GIR_ConstrainOperandRC, /*InsnID*/0, /*Op*/0, GIMT_Encode2(AMDGPU::VReg_320RegClassID),
        GIR_EraseFromParent, /*InsnID*/0,
        // GIR_Coverage, 6130,
        GIR_Done,
      // Label 701: @49995
      GIM_Try, /*On fail goto*//*Label 702*/ GIMT_Encode4(50030), // Rule ID 6131 //
        GIM_CheckRegBankForClass, /*MI*/0, /*Op*/0, /*RC*/GIMT_Encode2(AMDGPU::VReg_320RegClassID),
        GIM_CheckRegBankForClass, /*MI*/0, /*Op*/1, /*RC*/GIMT_Encode2(AMDGPU::VReg_320RegClassID),
        // (bitconvert:{ *:[v10f32] } VReg_320:{ *:[v10i32] }:$src0)  =>  VReg_320:{ *:[v10f32] }:$src0
        GIR_BuildMI, /*InsnID*/0, /*Opcode*/GIMT_Encode2(TargetOpcode::COPY),
        GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/0, // dst
        GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/1, // src0
        GIR_ConstrainOperandRC, /*InsnID*/0, /*Op*/0, GIMT_Encode2(AMDGPU::VReg_320RegClassID),
        GIR_EraseFromParent, /*InsnID*/0,
        // GIR_Coverage, 6131,
        GIR_Done,
      // Label 702: @50030
      GIM_Reject,
    // Label 698: @50031
    GIM_Reject,
    // Label 480: @50032
    GIM_Try, /*On fail goto*//*Label 703*/ GIMT_Encode4(50182),
      GIM_CheckType, /*MI*/0, /*Op*/1, /*Type*/GILLT_v11s32,
      GIM_Try, /*On fail goto*//*Label 704*/ GIMT_Encode4(50076), // Rule ID 6132 //
        GIM_CheckRegBankForClass, /*MI*/0, /*Op*/0, /*RC*/GIMT_Encode2(AMDGPU::SReg_352RegClassID),
        GIM_CheckRegBankForClass, /*MI*/0, /*Op*/1, /*RC*/GIMT_Encode2(AMDGPU::SReg_352RegClassID),
        // (bitconvert:{ *:[v11i32] } SReg_352:{ *:[v11f32] }:$src0)  =>  SReg_352:{ *:[v11i32] }:$src0
        GIR_BuildMI, /*InsnID*/0, /*Opcode*/GIMT_Encode2(TargetOpcode::COPY),
        GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/0, // dst
        GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/1, // src0
        GIR_ConstrainOperandRC, /*InsnID*/0, /*Op*/0, GIMT_Encode2(AMDGPU::SReg_352RegClassID),
        GIR_EraseFromParent, /*InsnID*/0,
        // GIR_Coverage, 6132,
        GIR_Done,
      // Label 704: @50076
      GIM_Try, /*On fail goto*//*Label 705*/ GIMT_Encode4(50111), // Rule ID 6133 //
        GIM_CheckRegBankForClass, /*MI*/0, /*Op*/0, /*RC*/GIMT_Encode2(AMDGPU::SReg_352RegClassID),
        GIM_CheckRegBankForClass, /*MI*/0, /*Op*/1, /*RC*/GIMT_Encode2(AMDGPU::SReg_352RegClassID),
        // (bitconvert:{ *:[v11f32] } SReg_352:{ *:[v11i32] }:$src0)  =>  SReg_352:{ *:[v11f32] }:$src0
        GIR_BuildMI, /*InsnID*/0, /*Opcode*/GIMT_Encode2(TargetOpcode::COPY),
        GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/0, // dst
        GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/1, // src0
        GIR_ConstrainOperandRC, /*InsnID*/0, /*Op*/0, GIMT_Encode2(AMDGPU::SReg_352RegClassID),
        GIR_EraseFromParent, /*InsnID*/0,
        // GIR_Coverage, 6133,
        GIR_Done,
      // Label 705: @50111
      GIM_Try, /*On fail goto*//*Label 706*/ GIMT_Encode4(50146), // Rule ID 6134 //
        GIM_CheckRegBankForClass, /*MI*/0, /*Op*/0, /*RC*/GIMT_Encode2(AMDGPU::VReg_352RegClassID),
        GIM_CheckRegBankForClass, /*MI*/0, /*Op*/1, /*RC*/GIMT_Encode2(AMDGPU::VReg_352RegClassID),
        // (bitconvert:{ *:[v11i32] } VReg_352:{ *:[v11f32] }:$src0)  =>  VReg_352:{ *:[v11i32] }:$src0
        GIR_BuildMI, /*InsnID*/0, /*Opcode*/GIMT_Encode2(TargetOpcode::COPY),
        GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/0, // dst
        GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/1, // src0
        GIR_ConstrainOperandRC, /*InsnID*/0, /*Op*/0, GIMT_Encode2(AMDGPU::VReg_352RegClassID),
        GIR_EraseFromParent, /*InsnID*/0,
        // GIR_Coverage, 6134,
        GIR_Done,
      // Label 706: @50146
      GIM_Try, /*On fail goto*//*Label 707*/ GIMT_Encode4(50181), // Rule ID 6135 //
        GIM_CheckRegBankForClass, /*MI*/0, /*Op*/0, /*RC*/GIMT_Encode2(AMDGPU::VReg_352RegClassID),
        GIM_CheckRegBankForClass, /*MI*/0, /*Op*/1, /*RC*/GIMT_Encode2(AMDGPU::VReg_352RegClassID),
        // (bitconvert:{ *:[v11f32] } VReg_352:{ *:[v11i32] }:$src0)  =>  VReg_352:{ *:[v11f32] }:$src0
        GIR_BuildMI, /*InsnID*/0, /*Opcode*/GIMT_Encode2(TargetOpcode::COPY),
        GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/0, // dst
        GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/1, // src0
        GIR_ConstrainOperandRC, /*InsnID*/0, /*Op*/0, GIMT_Encode2(AMDGPU::VReg_352RegClassID),
        GIR_EraseFromParent, /*InsnID*/0,
        // GIR_Coverage, 6135,
        GIR_Done,
      // Label 707: @50181
      GIM_Reject,
    // Label 703: @50182
    GIM_Reject,
    // Label 481: @50183
    GIM_Try, /*On fail goto*//*Label 708*/ GIMT_Encode4(50333),
      GIM_CheckType, /*MI*/0, /*Op*/1, /*Type*/GILLT_v12s32,
      GIM_Try, /*On fail goto*//*Label 709*/ GIMT_Encode4(50227), // Rule ID 6136 //
        GIM_CheckRegBankForClass, /*MI*/0, /*Op*/0, /*RC*/GIMT_Encode2(AMDGPU::SReg_384RegClassID),
        GIM_CheckRegBankForClass, /*MI*/0, /*Op*/1, /*RC*/GIMT_Encode2(AMDGPU::SReg_384RegClassID),
        // (bitconvert:{ *:[v12i32] } SReg_384:{ *:[v12f32] }:$src0)  =>  SReg_384:{ *:[v12i32] }:$src0
        GIR_BuildMI, /*InsnID*/0, /*Opcode*/GIMT_Encode2(TargetOpcode::COPY),
        GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/0, // dst
        GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/1, // src0
        GIR_ConstrainOperandRC, /*InsnID*/0, /*Op*/0, GIMT_Encode2(AMDGPU::SReg_384RegClassID),
        GIR_EraseFromParent, /*InsnID*/0,
        // GIR_Coverage, 6136,
        GIR_Done,
      // Label 709: @50227
      GIM_Try, /*On fail goto*//*Label 710*/ GIMT_Encode4(50262), // Rule ID 6137 //
        GIM_CheckRegBankForClass, /*MI*/0, /*Op*/0, /*RC*/GIMT_Encode2(AMDGPU::SReg_384RegClassID),
        GIM_CheckRegBankForClass, /*MI*/0, /*Op*/1, /*RC*/GIMT_Encode2(AMDGPU::SReg_384RegClassID),
        // (bitconvert:{ *:[v12f32] } SReg_384:{ *:[v12i32] }:$src0)  =>  SReg_384:{ *:[v12f32] }:$src0
        GIR_BuildMI, /*InsnID*/0, /*Opcode*/GIMT_Encode2(TargetOpcode::COPY),
        GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/0, // dst
        GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/1, // src0
        GIR_ConstrainOperandRC, /*InsnID*/0, /*Op*/0, GIMT_Encode2(AMDGPU::SReg_384RegClassID),
        GIR_EraseFromParent, /*InsnID*/0,
        // GIR_Coverage, 6137,
        GIR_Done,
      // Label 710: @50262
      GIM_Try, /*On fail goto*//*Label 711*/ GIMT_Encode4(50297), // Rule ID 6138 //
        GIM_CheckRegBankForClass, /*MI*/0, /*Op*/0, /*RC*/GIMT_Encode2(AMDGPU::VReg_384RegClassID),
        GIM_CheckRegBankForClass, /*MI*/0, /*Op*/1, /*RC*/GIMT_Encode2(AMDGPU::VReg_384RegClassID),
        // (bitconvert:{ *:[v12i32] } VReg_384:{ *:[v12f32] }:$src0)  =>  VReg_384:{ *:[v12i32] }:$src0
        GIR_BuildMI, /*InsnID*/0, /*Opcode*/GIMT_Encode2(TargetOpcode::COPY),
        GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/0, // dst
        GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/1, // src0
        GIR_ConstrainOperandRC, /*InsnID*/0, /*Op*/0, GIMT_Encode2(AMDGPU::VReg_384RegClassID),
        GIR_EraseFromParent, /*InsnID*/0,
        // GIR_Coverage, 6138,
        GIR_Done,
      // Label 711: @50297
      GIM_Try, /*On fail goto*//*Label 712*/ GIMT_Encode4(50332), // Rule ID 6139 //
        GIM_CheckRegBankForClass, /*MI*/0, /*Op*/0, /*RC*/GIMT_Encode2(AMDGPU::VReg_384RegClassID),
        GIM_CheckRegBankForClass, /*MI*/0, /*Op*/1, /*RC*/GIMT_Encode2(AMDGPU::VReg_384RegClassID),
        // (bitconvert:{ *:[v12f32] } VReg_384:{ *:[v12i32] }:$src0)  =>  VReg_384:{ *:[v12f32] }:$src0
        GIR_BuildMI, /*InsnID*/0, /*Opcode*/GIMT_Encode2(TargetOpcode::COPY),
        GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/0, // dst
        GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/1, // src0
        GIR_ConstrainOperandRC, /*InsnID*/0, /*Op*/0, GIMT_Encode2(AMDGPU::VReg_384RegClassID),
        GIR_EraseFromParent, /*InsnID*/0,
        // GIR_Coverage, 6139,
        GIR_Done,
      // Label 712: @50332
      GIM_Reject,
    // Label 708: @50333
    GIM_Reject,
    // Label 482: @50334
    GIM_Try, /*On fail goto*//*Label 713*/ GIMT_Encode4(50373), // Rule ID 6088 //
      GIM_CheckType, /*MI*/0, /*Op*/1, /*Type*/GILLT_v16s16,
      GIM_CheckRegBankForClass, /*MI*/0, /*Op*/0, /*RC*/GIMT_Encode2(AMDGPU::SReg_256RegClassID),
      GIM_CheckRegBankForClass, /*MI*/0, /*Op*/1, /*RC*/GIMT_Encode2(AMDGPU::SReg_256RegClassID),
      // (bitconvert:{ *:[v16i16] } SReg_256:{ *:[v16f16] }:$src0)  =>  SReg_256:{ *:[v16i16] }:$src0
      GIR_BuildMI, /*InsnID*/0, /*Opcode*/GIMT_Encode2(TargetOpcode::COPY),
      GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/0, // dst
      GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/1, // src0
      GIR_ConstrainOperandRC, /*InsnID*/0, /*Op*/0, GIMT_Encode2(AMDGPU::SReg_256RegClassID),
      GIR_EraseFromParent, /*InsnID*/0,
      // GIR_Coverage, 6088,
      GIR_Done,
    // Label 713: @50373
    GIM_Try, /*On fail goto*//*Label 714*/ GIMT_Encode4(50412), // Rule ID 6089 //
      GIM_CheckType, /*MI*/0, /*Op*/1, /*Type*/GILLT_v16s16,
      GIM_CheckRegBankForClass, /*MI*/0, /*Op*/0, /*RC*/GIMT_Encode2(AMDGPU::SReg_256RegClassID),
      GIM_CheckRegBankForClass, /*MI*/0, /*Op*/1, /*RC*/GIMT_Encode2(AMDGPU::SReg_256RegClassID),
      // (bitconvert:{ *:[v16f16] } SReg_256:{ *:[v16i16] }:$src0)  =>  SReg_256:{ *:[v16f16] }:$src0
      GIR_BuildMI, /*InsnID*/0, /*Opcode*/GIMT_Encode2(TargetOpcode::COPY),
      GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/0, // dst
      GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/1, // src0
      GIR_ConstrainOperandRC, /*InsnID*/0, /*Op*/0, GIMT_Encode2(AMDGPU::SReg_256RegClassID),
      GIR_EraseFromParent, /*InsnID*/0,
      // GIR_Coverage, 6089,
      GIR_Done,
    // Label 714: @50412
    GIM_Try, /*On fail goto*//*Label 715*/ GIMT_Encode4(50451), // Rule ID 6090 //
      GIM_CheckType, /*MI*/0, /*Op*/1, /*Type*/GILLT_v16s16,
      GIM_CheckRegBankForClass, /*MI*/0, /*Op*/0, /*RC*/GIMT_Encode2(AMDGPU::VReg_256RegClassID),
      GIM_CheckRegBankForClass, /*MI*/0, /*Op*/1, /*RC*/GIMT_Encode2(AMDGPU::VReg_256RegClassID),
      // (bitconvert:{ *:[v16i16] } VReg_256:{ *:[v16f16] }:$src0)  =>  VReg_256:{ *:[v16i16] }:$src0
      GIR_BuildMI, /*InsnID*/0, /*Opcode*/GIMT_Encode2(TargetOpcode::COPY),
      GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/0, // dst
      GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/1, // src0
      GIR_ConstrainOperandRC, /*InsnID*/0, /*Op*/0, GIMT_Encode2(AMDGPU::VReg_256RegClassID),
      GIR_EraseFromParent, /*InsnID*/0,
      // GIR_Coverage, 6090,
      GIR_Done,
    // Label 715: @50451
    GIM_Try, /*On fail goto*//*Label 716*/ GIMT_Encode4(50490), // Rule ID 6091 //
      GIM_CheckType, /*MI*/0, /*Op*/1, /*Type*/GILLT_v16s16,
      GIM_CheckRegBankForClass, /*MI*/0, /*Op*/0, /*RC*/GIMT_Encode2(AMDGPU::VReg_256RegClassID),
      GIM_CheckRegBankForClass, /*MI*/0, /*Op*/1, /*RC*/GIMT_Encode2(AMDGPU::VReg_256RegClassID),
      // (bitconvert:{ *:[v16f16] } VReg_256:{ *:[v16i16] }:$src0)  =>  VReg_256:{ *:[v16f16] }:$src0
      GIR_BuildMI, /*InsnID*/0, /*Opcode*/GIMT_Encode2(TargetOpcode::COPY),
      GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/0, // dst
      GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/1, // src0
      GIR_ConstrainOperandRC, /*InsnID*/0, /*Op*/0, GIMT_Encode2(AMDGPU::VReg_256RegClassID),
      GIR_EraseFromParent, /*InsnID*/0,
      // GIR_Coverage, 6091,
      GIR_Done,
    // Label 716: @50490
    GIM_Try, /*On fail goto*//*Label 717*/ GIMT_Encode4(50529), // Rule ID 6092 //
      GIM_CheckType, /*MI*/0, /*Op*/1, /*Type*/GILLT_v8s32,
      GIM_CheckRegBankForClass, /*MI*/0, /*Op*/0, /*RC*/GIMT_Encode2(AMDGPU::VReg_256RegClassID),
      GIM_CheckRegBankForClass, /*MI*/0, /*Op*/1, /*RC*/GIMT_Encode2(AMDGPU::VReg_256RegClassID),
      // (bitconvert:{ *:[v16f16] } VReg_256:{ *:[v8i32] }:$src0)  =>  VReg_256:{ *:[v16f16] }:$src0
      GIR_BuildMI, /*InsnID*/0, /*Opcode*/GIMT_Encode2(TargetOpcode::COPY),
      GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/0, // dst
      GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/1, // src0
      GIR_ConstrainOperandRC, /*InsnID*/0, /*Op*/0, GIMT_Encode2(AMDGPU::VReg_256RegClassID),
      GIR_EraseFromParent, /*InsnID*/0,
      // GIR_Coverage, 6092,
      GIR_Done,
    // Label 717: @50529
    GIM_Try, /*On fail goto*//*Label 718*/ GIMT_Encode4(50568), // Rule ID 6093 //
      GIM_CheckType, /*MI*/0, /*Op*/1, /*Type*/GILLT_v8s32,
      GIM_CheckRegBankForClass, /*MI*/0, /*Op*/0, /*RC*/GIMT_Encode2(AMDGPU::VReg_256RegClassID),
      GIM_CheckRegBankForClass, /*MI*/0, /*Op*/1, /*RC*/GIMT_Encode2(AMDGPU::VReg_256RegClassID),
      // (bitconvert:{ *:[v16i16] } VReg_256:{ *:[v8i32] }:$src0)  =>  VReg_256:{ *:[v16i16] }:$src0
      GIR_BuildMI, /*InsnID*/0, /*Opcode*/GIMT_Encode2(TargetOpcode::COPY),
      GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/0, // dst
      GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/1, // src0
      GIR_ConstrainOperandRC, /*InsnID*/0, /*Op*/0, GIMT_Encode2(AMDGPU::VReg_256RegClassID),
      GIR_EraseFromParent, /*InsnID*/0,
      // GIR_Coverage, 6093,
      GIR_Done,
    // Label 718: @50568
    GIM_Try, /*On fail goto*//*Label 719*/ GIMT_Encode4(50607), // Rule ID 6094 //
      GIM_CheckType, /*MI*/0, /*Op*/1, /*Type*/GILLT_v8s32,
      GIM_CheckRegBankForClass, /*MI*/0, /*Op*/0, /*RC*/GIMT_Encode2(AMDGPU::VReg_256RegClassID),
      GIM_CheckRegBankForClass, /*MI*/0, /*Op*/1, /*RC*/GIMT_Encode2(AMDGPU::VReg_256RegClassID),
      // (bitconvert:{ *:[v16f16] } VReg_256:{ *:[v8f32] }:$src0)  =>  VReg_256:{ *:[v16f16] }:$src0
      GIR_BuildMI, /*InsnID*/0, /*Opcode*/GIMT_Encode2(TargetOpcode::COPY),
      GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/0, // dst
      GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/1, // src0
      GIR_ConstrainOperandRC, /*InsnID*/0, /*Op*/0, GIMT_Encode2(AMDGPU::VReg_256RegClassID),
      GIR_EraseFromParent, /*InsnID*/0,
      // GIR_Coverage, 6094,
      GIR_Done,
    // Label 719: @50607
    GIM_Try, /*On fail goto*//*Label 720*/ GIMT_Encode4(50646), // Rule ID 6095 //
      GIM_CheckType, /*MI*/0, /*Op*/1, /*Type*/GILLT_v8s32,
      GIM_CheckRegBankForClass, /*MI*/0, /*Op*/0, /*RC*/GIMT_Encode2(AMDGPU::VReg_256RegClassID),
      GIM_CheckRegBankForClass, /*MI*/0, /*Op*/1, /*RC*/GIMT_Encode2(AMDGPU::VReg_256RegClassID),
      // (bitconvert:{ *:[v16i16] } VReg_256:{ *:[v8f32] }:$src0)  =>  VReg_256:{ *:[v16i16] }:$src0
      GIR_BuildMI, /*InsnID*/0, /*Opcode*/GIMT_Encode2(TargetOpcode::COPY),
      GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/0, // dst
      GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/1, // src0
      GIR_ConstrainOperandRC, /*InsnID*/0, /*Op*/0, GIMT_Encode2(AMDGPU::VReg_256RegClassID),
      GIR_EraseFromParent, /*InsnID*/0,
      // GIR_Coverage, 6095,
      GIR_Done,
    // Label 720: @50646
    GIM_Try, /*On fail goto*//*Label 721*/ GIMT_Encode4(50685), // Rule ID 6100 //
      GIM_CheckType, /*MI*/0, /*Op*/1, /*Type*/GILLT_v4s64,
      GIM_CheckRegBankForClass, /*MI*/0, /*Op*/0, /*RC*/GIMT_Encode2(AMDGPU::VReg_256RegClassID),
      GIM_CheckRegBankForClass, /*MI*/0, /*Op*/1, /*RC*/GIMT_Encode2(AMDGPU::VReg_256RegClassID),
      // (bitconvert:{ *:[v16f16] } VReg_256:{ *:[v4i64] }:$src0)  =>  VReg_256:{ *:[v16f16] }:$src0
      GIR_BuildMI, /*InsnID*/0, /*Opcode*/GIMT_Encode2(TargetOpcode::COPY),
      GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/0, // dst
      GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/1, // src0
      GIR_ConstrainOperandRC, /*InsnID*/0, /*Op*/0, GIMT_Encode2(AMDGPU::VReg_256RegClassID),
      GIR_EraseFromParent, /*InsnID*/0,
      // GIR_Coverage, 6100,
      GIR_Done,
    // Label 721: @50685
    GIM_Try, /*On fail goto*//*Label 722*/ GIMT_Encode4(50724), // Rule ID 6101 //
      GIM_CheckType, /*MI*/0, /*Op*/1, /*Type*/GILLT_v4s64,
      GIM_CheckRegBankForClass, /*MI*/0, /*Op*/0, /*RC*/GIMT_Encode2(AMDGPU::VReg_256RegClassID),
      GIM_CheckRegBankForClass, /*MI*/0, /*Op*/1, /*RC*/GIMT_Encode2(AMDGPU::VReg_256RegClassID),
      // (bitconvert:{ *:[v16i16] } VReg_256:{ *:[v4i64] }:$src0)  =>  VReg_256:{ *:[v16i16] }:$src0
      GIR_BuildMI, /*InsnID*/0, /*Opcode*/GIMT_Encode2(TargetOpcode::COPY),
      GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/0, // dst
      GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/1, // src0
      GIR_ConstrainOperandRC, /*InsnID*/0, /*Op*/0, GIMT_Encode2(AMDGPU::VReg_256RegClassID),
      GIR_EraseFromParent, /*InsnID*/0,
      // GIR_Coverage, 6101,
      GIR_Done,
    // Label 722: @50724
    GIM_Try, /*On fail goto*//*Label 723*/ GIMT_Encode4(50763), // Rule ID 6102 //
      GIM_CheckType, /*MI*/0, /*Op*/1, /*Type*/GILLT_v4s64,
      GIM_CheckRegBankForClass, /*MI*/0, /*Op*/0, /*RC*/GIMT_Encode2(AMDGPU::VReg_256RegClassID),
      GIM_CheckRegBankForClass, /*MI*/0, /*Op*/1, /*RC*/GIMT_Encode2(AMDGPU::VReg_256RegClassID),
      // (bitconvert:{ *:[v16f16] } VReg_256:{ *:[v4f64] }:$src0)  =>  VReg_256:{ *:[v16f16] }:$src0
      GIR_BuildMI, /*InsnID*/0, /*Opcode*/GIMT_Encode2(TargetOpcode::COPY),
      GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/0, // dst
      GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/1, // src0
      GIR_ConstrainOperandRC, /*InsnID*/0, /*Op*/0, GIMT_Encode2(AMDGPU::VReg_256RegClassID),
      GIR_EraseFromParent, /*InsnID*/0,
      // GIR_Coverage, 6102,
      GIR_Done,
    // Label 723: @50763
    GIM_Try, /*On fail goto*//*Label 724*/ GIMT_Encode4(50802), // Rule ID 6103 //
      GIM_CheckType, /*MI*/0, /*Op*/1, /*Type*/GILLT_v4s64,
      GIM_CheckRegBankForClass, /*MI*/0, /*Op*/0, /*RC*/GIMT_Encode2(AMDGPU::VReg_256RegClassID),
      GIM_CheckRegBankForClass, /*MI*/0, /*Op*/1, /*RC*/GIMT_Encode2(AMDGPU::VReg_256RegClassID),
      // (bitconvert:{ *:[v16i16] } VReg_256:{ *:[v4f64] }:$src0)  =>  VReg_256:{ *:[v16i16] }:$src0
      GIR_BuildMI, /*InsnID*/0, /*Opcode*/GIMT_Encode2(TargetOpcode::COPY),
      GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/0, // dst
      GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/1, // src0
      GIR_ConstrainOperandRC, /*InsnID*/0, /*Op*/0, GIMT_Encode2(AMDGPU::VReg_256RegClassID),
      GIR_EraseFromParent, /*InsnID*/0,
      // GIR_Coverage, 6103,
      GIR_Done,
    // Label 724: @50802
    GIM_Try, /*On fail goto*//*Label 725*/ GIMT_Encode4(50841), // Rule ID 6109 //
      GIM_CheckType, /*MI*/0, /*Op*/1, /*Type*/GILLT_v8s32,
      GIM_CheckRegBankForClass, /*MI*/0, /*Op*/0, /*RC*/GIMT_Encode2(AMDGPU::VReg_256RegClassID),
      GIM_CheckRegBankForClass, /*MI*/0, /*Op*/1, /*RC*/GIMT_Encode2(AMDGPU::VReg_256RegClassID),
      // (bitconvert:{ *:[v16bf16] } VReg_256:{ *:[v8i32] }:$src0)  =>  VReg_256:{ *:[v16bf16] }:$src0
      GIR_BuildMI, /*InsnID*/0, /*Opcode*/GIMT_Encode2(TargetOpcode::COPY),
      GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/0, // dst
      GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/1, // src0
      GIR_ConstrainOperandRC, /*InsnID*/0, /*Op*/0, GIMT_Encode2(AMDGPU::VReg_256RegClassID),
      GIR_EraseFromParent, /*InsnID*/0,
      // GIR_Coverage, 6109,
      GIR_Done,
    // Label 725: @50841
    GIM_Try, /*On fail goto*//*Label 726*/ GIMT_Encode4(50880), // Rule ID 6111 //
      GIM_CheckType, /*MI*/0, /*Op*/1, /*Type*/GILLT_v8s32,
      GIM_CheckRegBankForClass, /*MI*/0, /*Op*/0, /*RC*/GIMT_Encode2(AMDGPU::VReg_256RegClassID),
      GIM_CheckRegBankForClass, /*MI*/0, /*Op*/1, /*RC*/GIMT_Encode2(AMDGPU::VReg_256RegClassID),
      // (bitconvert:{ *:[v16bf16] } VReg_256:{ *:[v8f32] }:$src0)  =>  VReg_256:{ *:[v16bf16] }:$src0
      GIR_BuildMI, /*InsnID*/0, /*Opcode*/GIMT_Encode2(TargetOpcode::COPY),
      GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/0, // dst
      GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/1, // src0
      GIR_ConstrainOperandRC, /*InsnID*/0, /*Op*/0, GIMT_Encode2(AMDGPU::VReg_256RegClassID),
      GIR_EraseFromParent, /*InsnID*/0,
      // GIR_Coverage, 6111,
      GIR_Done,
    // Label 726: @50880
    GIM_Try, /*On fail goto*//*Label 727*/ GIMT_Encode4(50919), // Rule ID 6113 //
      GIM_CheckType, /*MI*/0, /*Op*/1, /*Type*/GILLT_v4s64,
      GIM_CheckRegBankForClass, /*MI*/0, /*Op*/0, /*RC*/GIMT_Encode2(AMDGPU::VReg_256RegClassID),
      GIM_CheckRegBankForClass, /*MI*/0, /*Op*/1, /*RC*/GIMT_Encode2(AMDGPU::VReg_256RegClassID),
      // (bitconvert:{ *:[v16bf16] } VReg_256:{ *:[v4i64] }:$src0)  =>  VReg_256:{ *:[v16bf16] }:$src0
      GIR_BuildMI, /*InsnID*/0, /*Opcode*/GIMT_Encode2(TargetOpcode::COPY),
      GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/0, // dst
      GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/1, // src0
      GIR_ConstrainOperandRC, /*InsnID*/0, /*Op*/0, GIMT_Encode2(AMDGPU::VReg_256RegClassID),
      GIR_EraseFromParent, /*InsnID*/0,
      // GIR_Coverage, 6113,
      GIR_Done,
    // Label 727: @50919
    GIM_Try, /*On fail goto*//*Label 728*/ GIMT_Encode4(50958), // Rule ID 6115 //
      GIM_CheckType, /*MI*/0, /*Op*/1, /*Type*/GILLT_v4s64,
      GIM_CheckRegBankForClass, /*MI*/0, /*Op*/0, /*RC*/GIMT_Encode2(AMDGPU::VReg_256RegClassID),
      GIM_CheckRegBankForClass, /*MI*/0, /*Op*/1, /*RC*/GIMT_Encode2(AMDGPU::VReg_256RegClassID),
      // (bitconvert:{ *:[v16bf16] } VReg_256:{ *:[v4f64] }:$src0)  =>  VReg_256:{ *:[v16bf16] }:$src0
      GIR_BuildMI, /*InsnID*/0, /*Opcode*/GIMT_Encode2(TargetOpcode::COPY),
      GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/0, // dst
      GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/1, // src0
      GIR_ConstrainOperandRC, /*InsnID*/0, /*Op*/0, GIMT_Encode2(AMDGPU::VReg_256RegClassID),
      GIR_EraseFromParent, /*InsnID*/0,
      // GIR_Coverage, 6115,
      GIR_Done,
    // Label 728: @50958
    GIM_Try, /*On fail goto*//*Label 729*/ GIMT_Encode4(50997), // Rule ID 6116 //
      GIM_CheckType, /*MI*/0, /*Op*/1, /*Type*/GILLT_v16s16,
      GIM_CheckRegBankForClass, /*MI*/0, /*Op*/0, /*RC*/GIMT_Encode2(AMDGPU::SReg_256RegClassID),
      GIM_CheckRegBankForClass, /*MI*/0, /*Op*/1, /*RC*/GIMT_Encode2(AMDGPU::SReg_256RegClassID),
      // (bitconvert:{ *:[v16i16] } SReg_256:{ *:[v16bf16] }:$src0)  =>  SReg_256:{ *:[v16i16] }:$src0
      GIR_BuildMI, /*InsnID*/0, /*Opcode*/GIMT_Encode2(TargetOpcode::COPY),
      GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/0, // dst
      GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/1, // src0
      GIR_ConstrainOperandRC, /*InsnID*/0, /*Op*/0, GIMT_Encode2(AMDGPU::SReg_256RegClassID),
      GIR_EraseFromParent, /*InsnID*/0,
      // GIR_Coverage, 6116,
      GIR_Done,
    // Label 729: @50997
    GIM_Try, /*On fail goto*//*Label 730*/ GIMT_Encode4(51036), // Rule ID 6117 //
      GIM_CheckType, /*MI*/0, /*Op*/1, /*Type*/GILLT_v16s16,
      GIM_CheckRegBankForClass, /*MI*/0, /*Op*/0, /*RC*/GIMT_Encode2(AMDGPU::SReg_256RegClassID),
      GIM_CheckRegBankForClass, /*MI*/0, /*Op*/1, /*RC*/GIMT_Encode2(AMDGPU::SReg_256RegClassID),
      // (bitconvert:{ *:[v16bf16] } SReg_256:{ *:[v16i16] }:$src0)  =>  SReg_256:{ *:[v16bf16] }:$src0
      GIR_BuildMI, /*InsnID*/0, /*Opcode*/GIMT_Encode2(TargetOpcode::COPY),
      GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/0, // dst
      GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/1, // src0
      GIR_ConstrainOperandRC, /*InsnID*/0, /*Op*/0, GIMT_Encode2(AMDGPU::SReg_256RegClassID),
      GIR_EraseFromParent, /*InsnID*/0,
      // GIR_Coverage, 6117,
      GIR_Done,
    // Label 730: @51036
    GIM_Try, /*On fail goto*//*Label 731*/ GIMT_Encode4(51075), // Rule ID 6118 //
      GIM_CheckType, /*MI*/0, /*Op*/1, /*Type*/GILLT_v16s16,
      GIM_CheckRegBankForClass, /*MI*/0, /*Op*/0, /*RC*/GIMT_Encode2(AMDGPU::VReg_256RegClassID),
      GIM_CheckRegBankForClass, /*MI*/0, /*Op*/1, /*RC*/GIMT_Encode2(AMDGPU::VReg_256RegClassID),
      // (bitconvert:{ *:[v16i16] } VReg_256:{ *:[v16bf16] }:$src0)  =>  VReg_256:{ *:[v16i16] }:$src0
      GIR_BuildMI, /*InsnID*/0, /*Opcode*/GIMT_Encode2(TargetOpcode::COPY),
      GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/0, // dst
      GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/1, // src0
      GIR_ConstrainOperandRC, /*InsnID*/0, /*Op*/0, GIMT_Encode2(AMDGPU::VReg_256RegClassID),
      GIR_EraseFromParent, /*InsnID*/0,
      // GIR_Coverage, 6118,
      GIR_Done,
    // Label 731: @51075
    GIM_Try, /*On fail goto*//*Label 732*/ GIMT_Encode4(51114), // Rule ID 6119 //
      GIM_CheckType, /*MI*/0, /*Op*/1, /*Type*/GILLT_v16s16,
      GIM_CheckRegBankForClass, /*MI*/0, /*Op*/0, /*RC*/GIMT_Encode2(AMDGPU::VReg_256RegClassID),
      GIM_CheckRegBankForClass, /*MI*/0, /*Op*/1, /*RC*/GIMT_Encode2(AMDGPU::VReg_256RegClassID),
      // (bitconvert:{ *:[v16bf16] } VReg_256:{ *:[v16i16] }:$src0)  =>  VReg_256:{ *:[v16bf16] }:$src0
      GIR_BuildMI, /*InsnID*/0, /*Opcode*/GIMT_Encode2(TargetOpcode::COPY),
      GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/0, // dst
      GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/1, // src0
      GIR_ConstrainOperandRC, /*InsnID*/0, /*Op*/0, GIMT_Encode2(AMDGPU::VReg_256RegClassID),
      GIR_EraseFromParent, /*InsnID*/0,
      // GIR_Coverage, 6119,
      GIR_Done,
    // Label 732: @51114
    GIM_Try, /*On fail goto*//*Label 733*/ GIMT_Encode4(51153), // Rule ID 6120 //
      GIM_CheckType, /*MI*/0, /*Op*/1, /*Type*/GILLT_v16s16,
      GIM_CheckRegBankForClass, /*MI*/0, /*Op*/0, /*RC*/GIMT_Encode2(AMDGPU::SReg_256RegClassID),
      GIM_CheckRegBankForClass, /*MI*/0, /*Op*/1, /*RC*/GIMT_Encode2(AMDGPU::SReg_256RegClassID),
      // (bitconvert:{ *:[v16f16] } SReg_256:{ *:[v16bf16] }:$src0)  =>  SReg_256:{ *:[v16f16] }:$src0
      GIR_BuildMI, /*InsnID*/0, /*Opcode*/GIMT_Encode2(TargetOpcode::COPY),
      GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/0, // dst
      GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/1, // src0
      GIR_ConstrainOperandRC, /*InsnID*/0, /*Op*/0, GIMT_Encode2(AMDGPU::SReg_256RegClassID),
      GIR_EraseFromParent, /*InsnID*/0,
      // GIR_Coverage, 6120,
      GIR_Done,
    // Label 733: @51153
    GIM_Try, /*On fail goto*//*Label 734*/ GIMT_Encode4(51192), // Rule ID 6121 //
      GIM_CheckType, /*MI*/0, /*Op*/1, /*Type*/GILLT_v16s16,
      GIM_CheckRegBankForClass, /*MI*/0, /*Op*/0, /*RC*/GIMT_Encode2(AMDGPU::SReg_256RegClassID),
      GIM_CheckRegBankForClass, /*MI*/0, /*Op*/1, /*RC*/GIMT_Encode2(AMDGPU::SReg_256RegClassID),
      // (bitconvert:{ *:[v16bf16] } SReg_256:{ *:[v16f16] }:$src0)  =>  SReg_256:{ *:[v16bf16] }:$src0
      GIR_BuildMI, /*InsnID*/0, /*Opcode*/GIMT_Encode2(TargetOpcode::COPY),
      GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/0, // dst
      GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/1, // src0
      GIR_ConstrainOperandRC, /*InsnID*/0, /*Op*/0, GIMT_Encode2(AMDGPU::SReg_256RegClassID),
      GIR_EraseFromParent, /*InsnID*/0,
      // GIR_Coverage, 6121,
      GIR_Done,
    // Label 734: @51192
    GIM_Try, /*On fail goto*//*Label 735*/ GIMT_Encode4(51231), // Rule ID 6122 //
      GIM_CheckType, /*MI*/0, /*Op*/1, /*Type*/GILLT_v16s16,
      GIM_CheckRegBankForClass, /*MI*/0, /*Op*/0, /*RC*/GIMT_Encode2(AMDGPU::VReg_256RegClassID),
      GIM_CheckRegBankForClass, /*MI*/0, /*Op*/1, /*RC*/GIMT_Encode2(AMDGPU::VReg_256RegClassID),
      // (bitconvert:{ *:[v16f16] } VReg_256:{ *:[v16bf16] }:$src0)  =>  VReg_256:{ *:[v16f16] }:$src0
      GIR_BuildMI, /*InsnID*/0, /*Opcode*/GIMT_Encode2(TargetOpcode::COPY),
      GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/0, // dst
      GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/1, // src0
      GIR_ConstrainOperandRC, /*InsnID*/0, /*Op*/0, GIMT_Encode2(AMDGPU::VReg_256RegClassID),
      GIR_EraseFromParent, /*InsnID*/0,
      // GIR_Coverage, 6122,
      GIR_Done,
    // Label 735: @51231
    GIM_Try, /*On fail goto*//*Label 736*/ GIMT_Encode4(51270), // Rule ID 6123 //
      GIM_CheckType, /*MI*/0, /*Op*/1, /*Type*/GILLT_v16s16,
      GIM_CheckRegBankForClass, /*MI*/0, /*Op*/0, /*RC*/GIMT_Encode2(AMDGPU::VReg_256RegClassID),
      GIM_CheckRegBankForClass, /*MI*/0, /*Op*/1, /*RC*/GIMT_Encode2(AMDGPU::VReg_256RegClassID),
      // (bitconvert:{ *:[v16bf16] } VReg_256:{ *:[v16f16] }:$src0)  =>  VReg_256:{ *:[v16bf16] }:$src0
      GIR_BuildMI, /*InsnID*/0, /*Opcode*/GIMT_Encode2(TargetOpcode::COPY),
      GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/0, // dst
      GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/1, // src0
      GIR_ConstrainOperandRC, /*InsnID*/0, /*Op*/0, GIMT_Encode2(AMDGPU::VReg_256RegClassID),
      GIR_EraseFromParent, /*InsnID*/0,
      // GIR_Coverage, 6123,
      GIR_Done,
    // Label 736: @51270
    GIM_Reject,
    // Label 483: @51271
    GIM_Try, /*On fail goto*//*Label 737*/ GIMT_Encode4(51310), // Rule ID 6144 //
      GIM_CheckType, /*MI*/0, /*Op*/1, /*Type*/GILLT_v32s16,
      GIM_CheckRegBankForClass, /*MI*/0, /*Op*/0, /*RC*/GIMT_Encode2(AMDGPU::VReg_512RegClassID),
      GIM_CheckRegBankForClass, /*MI*/0, /*Op*/1, /*RC*/GIMT_Encode2(AMDGPU::VReg_512RegClassID),
      // (bitconvert:{ *:[v16f32] } VReg_512:{ *:[v32f16] }:$src0)  =>  VReg_512:{ *:[v16f32] }:$src0
      GIR_BuildMI, /*InsnID*/0, /*Opcode*/GIMT_Encode2(TargetOpcode::COPY),
      GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/0, // dst
      GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/1, // src0
      GIR_ConstrainOperandRC, /*InsnID*/0, /*Op*/0, GIMT_Encode2(AMDGPU::VReg_512RegClassID),
      GIR_EraseFromParent, /*InsnID*/0,
      // GIR_Coverage, 6144,
      GIR_Done,
    // Label 737: @51310
    GIM_Try, /*On fail goto*//*Label 738*/ GIMT_Encode4(51349), // Rule ID 6145 //
      GIM_CheckType, /*MI*/0, /*Op*/1, /*Type*/GILLT_v32s16,
      GIM_CheckRegBankForClass, /*MI*/0, /*Op*/0, /*RC*/GIMT_Encode2(AMDGPU::VReg_512RegClassID),
      GIM_CheckRegBankForClass, /*MI*/0, /*Op*/1, /*RC*/GIMT_Encode2(AMDGPU::VReg_512RegClassID),
      // (bitconvert:{ *:[v16i32] } VReg_512:{ *:[v32f16] }:$src0)  =>  VReg_512:{ *:[v16i32] }:$src0
      GIR_BuildMI, /*InsnID*/0, /*Opcode*/GIMT_Encode2(TargetOpcode::COPY),
      GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/0, // dst
      GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/1, // src0
      GIR_ConstrainOperandRC, /*InsnID*/0, /*Op*/0, GIMT_Encode2(AMDGPU::VReg_512RegClassID),
      GIR_EraseFromParent, /*InsnID*/0,
      // GIR_Coverage, 6145,
      GIR_Done,
    // Label 738: @51349
    GIM_Try, /*On fail goto*//*Label 739*/ GIMT_Encode4(51388), // Rule ID 6148 //
      GIM_CheckType, /*MI*/0, /*Op*/1, /*Type*/GILLT_v32s16,
      GIM_CheckRegBankForClass, /*MI*/0, /*Op*/0, /*RC*/GIMT_Encode2(AMDGPU::VReg_512RegClassID),
      GIM_CheckRegBankForClass, /*MI*/0, /*Op*/1, /*RC*/GIMT_Encode2(AMDGPU::VReg_512RegClassID),
      // (bitconvert:{ *:[v16f32] } VReg_512:{ *:[v32i16] }:$src0)  =>  VReg_512:{ *:[v16f32] }:$src0
      GIR_BuildMI, /*InsnID*/0, /*Opcode*/GIMT_Encode2(TargetOpcode::COPY),
      GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/0, // dst
      GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/1, // src0
      GIR_ConstrainOperandRC, /*InsnID*/0, /*Op*/0, GIMT_Encode2(AMDGPU::VReg_512RegClassID),
      GIR_EraseFromParent, /*InsnID*/0,
      // GIR_Coverage, 6148,
      GIR_Done,
    // Label 739: @51388
    GIM_Try, /*On fail goto*//*Label 740*/ GIMT_Encode4(51427), // Rule ID 6149 //
      GIM_CheckType, /*MI*/0, /*Op*/1, /*Type*/GILLT_v32s16,
      GIM_CheckRegBankForClass, /*MI*/0, /*Op*/0, /*RC*/GIMT_Encode2(AMDGPU::VReg_512RegClassID),
      GIM_CheckRegBankForClass, /*MI*/0, /*Op*/1, /*RC*/GIMT_Encode2(AMDGPU::VReg_512RegClassID),
      // (bitconvert:{ *:[v16i32] } VReg_512:{ *:[v32i16] }:$src0)  =>  VReg_512:{ *:[v16i32] }:$src0
      GIR_BuildMI, /*InsnID*/0, /*Opcode*/GIMT_Encode2(TargetOpcode::COPY),
      GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/0, // dst
      GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/1, // src0
      GIR_ConstrainOperandRC, /*InsnID*/0, /*Op*/0, GIMT_Encode2(AMDGPU::VReg_512RegClassID),
      GIR_EraseFromParent, /*InsnID*/0,
      // GIR_Coverage, 6149,
      GIR_Done,
    // Label 740: @51427
    GIM_Try, /*On fail goto*//*Label 741*/ GIMT_Encode4(51466), // Rule ID 6150 //
      GIM_CheckType, /*MI*/0, /*Op*/1, /*Type*/GILLT_v16s32,
      GIM_CheckRegBankForClass, /*MI*/0, /*Op*/0, /*RC*/GIMT_Encode2(AMDGPU::VReg_512RegClassID),
      GIM_CheckRegBankForClass, /*MI*/0, /*Op*/1, /*RC*/GIMT_Encode2(AMDGPU::VReg_512RegClassID),
      // (bitconvert:{ *:[v16i32] } VReg_512:{ *:[v16f32] }:$src0)  =>  VReg_512:{ *:[v16i32] }:$src0
      GIR_BuildMI, /*InsnID*/0, /*Opcode*/GIMT_Encode2(TargetOpcode::COPY),
      GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/0, // dst
      GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/1, // src0
      GIR_ConstrainOperandRC, /*InsnID*/0, /*Op*/0, GIMT_Encode2(AMDGPU::VReg_512RegClassID),
      GIR_EraseFromParent, /*InsnID*/0,
      // GIR_Coverage, 6150,
      GIR_Done,
    // Label 741: @51466
    GIM_Try, /*On fail goto*//*Label 742*/ GIMT_Encode4(51505), // Rule ID 6151 //
      GIM_CheckType, /*MI*/0, /*Op*/1, /*Type*/GILLT_v16s32,
      GIM_CheckRegBankForClass, /*MI*/0, /*Op*/0, /*RC*/GIMT_Encode2(AMDGPU::VReg_512RegClassID),
      GIM_CheckRegBankForClass, /*MI*/0, /*Op*/1, /*RC*/GIMT_Encode2(AMDGPU::VReg_512RegClassID),
      // (bitconvert:{ *:[v16f32] } VReg_512:{ *:[v16i32] }:$src0)  =>  VReg_512:{ *:[v16f32] }:$src0
      GIR_BuildMI, /*InsnID*/0, /*Opcode*/GIMT_Encode2(TargetOpcode::COPY),
      GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/0, // dst
      GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/1, // src0
      GIR_ConstrainOperandRC, /*InsnID*/0, /*Op*/0, GIMT_Encode2(AMDGPU::VReg_512RegClassID),
      GIR_EraseFromParent, /*InsnID*/0,
      // GIR_Coverage, 6151,
      GIR_Done,
    // Label 742: @51505
    GIM_Try, /*On fail goto*//*Label 743*/ GIMT_Encode4(51544), // Rule ID 6156 //
      GIM_CheckType, /*MI*/0, /*Op*/1, /*Type*/GILLT_v8s64,
      GIM_CheckRegBankForClass, /*MI*/0, /*Op*/0, /*RC*/GIMT_Encode2(AMDGPU::VReg_512RegClassID),
      GIM_CheckRegBankForClass, /*MI*/0, /*Op*/1, /*RC*/GIMT_Encode2(AMDGPU::VReg_512RegClassID),
      // (bitconvert:{ *:[v16i32] } VReg_512:{ *:[v8i64] }:$src0)  =>  VReg_512:{ *:[v16i32] }:$src0
      GIR_BuildMI, /*InsnID*/0, /*Opcode*/GIMT_Encode2(TargetOpcode::COPY),
      GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/0, // dst
      GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/1, // src0
      GIR_ConstrainOperandRC, /*InsnID*/0, /*Op*/0, GIMT_Encode2(AMDGPU::VReg_512RegClassID),
      GIR_EraseFromParent, /*InsnID*/0,
      // GIR_Coverage, 6156,
      GIR_Done,
    // Label 743: @51544
    GIM_Try, /*On fail goto*//*Label 744*/ GIMT_Encode4(51583), // Rule ID 6157 //
      GIM_CheckType, /*MI*/0, /*Op*/1, /*Type*/GILLT_v8s64,
      GIM_CheckRegBankForClass, /*MI*/0, /*Op*/0, /*RC*/GIMT_Encode2(AMDGPU::VReg_512RegClassID),
      GIM_CheckRegBankForClass, /*MI*/0, /*Op*/1, /*RC*/GIMT_Encode2(AMDGPU::VReg_512RegClassID),
      // (bitconvert:{ *:[v16i32] } VReg_512:{ *:[v8f64] }:$src0)  =>  VReg_512:{ *:[v16i32] }:$src0
      GIR_BuildMI, /*InsnID*/0, /*Opcode*/GIMT_Encode2(TargetOpcode::COPY),
      GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/0, // dst
      GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/1, // src0
      GIR_ConstrainOperandRC, /*InsnID*/0, /*Op*/0, GIMT_Encode2(AMDGPU::VReg_512RegClassID),
      GIR_EraseFromParent, /*InsnID*/0,
      // GIR_Coverage, 6157,
      GIR_Done,
    // Label 744: @51583
    GIM_Try, /*On fail goto*//*Label 745*/ GIMT_Encode4(51622), // Rule ID 6160 //
      GIM_CheckType, /*MI*/0, /*Op*/1, /*Type*/GILLT_v8s64,
      GIM_CheckRegBankForClass, /*MI*/0, /*Op*/0, /*RC*/GIMT_Encode2(AMDGPU::VReg_512RegClassID),
      GIM_CheckRegBankForClass, /*MI*/0, /*Op*/1, /*RC*/GIMT_Encode2(AMDGPU::VReg_512RegClassID),
      // (bitconvert:{ *:[v16f32] } VReg_512:{ *:[v8i64] }:$src0)  =>  VReg_512:{ *:[v16f32] }:$src0
      GIR_BuildMI, /*InsnID*/0, /*Opcode*/GIMT_Encode2(TargetOpcode::COPY),
      GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/0, // dst
      GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/1, // src0
      GIR_ConstrainOperandRC, /*InsnID*/0, /*Op*/0, GIMT_Encode2(AMDGPU::VReg_512RegClassID),
      GIR_EraseFromParent, /*InsnID*/0,
      // GIR_Coverage, 6160,
      GIR_Done,
    // Label 745: @51622
    GIM_Try, /*On fail goto*//*Label 746*/ GIMT_Encode4(51661), // Rule ID 6161 //
      GIM_CheckType, /*MI*/0, /*Op*/1, /*Type*/GILLT_v8s64,
      GIM_CheckRegBankForClass, /*MI*/0, /*Op*/0, /*RC*/GIMT_Encode2(AMDGPU::VReg_512RegClassID),
      GIM_CheckRegBankForClass, /*MI*/0, /*Op*/1, /*RC*/GIMT_Encode2(AMDGPU::VReg_512RegClassID),
      // (bitconvert:{ *:[v16f32] } VReg_512:{ *:[v8f64] }:$src0)  =>  VReg_512:{ *:[v16f32] }:$src0
      GIR_BuildMI, /*InsnID*/0, /*Opcode*/GIMT_Encode2(TargetOpcode::COPY),
      GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/0, // dst
      GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/1, // src0
      GIR_ConstrainOperandRC, /*InsnID*/0, /*Op*/0, GIMT_Encode2(AMDGPU::VReg_512RegClassID),
      GIR_EraseFromParent, /*InsnID*/0,
      // GIR_Coverage, 6161,
      GIR_Done,
    // Label 746: @51661
    GIM_Try, /*On fail goto*//*Label 747*/ GIMT_Encode4(51700), // Rule ID 6171 //
      GIM_CheckType, /*MI*/0, /*Op*/1, /*Type*/GILLT_v32s16,
      GIM_CheckRegBankForClass, /*MI*/0, /*Op*/0, /*RC*/GIMT_Encode2(AMDGPU::VReg_512RegClassID),
      GIM_CheckRegBankForClass, /*MI*/0, /*Op*/1, /*RC*/GIMT_Encode2(AMDGPU::VReg_512RegClassID),
      // (bitconvert:{ *:[v16i32] } VReg_512:{ *:[v32bf16] }:$src0)  =>  VReg_512:{ *:[v16i32] }:$src0
      GIR_BuildMI, /*InsnID*/0, /*Opcode*/GIMT_Encode2(TargetOpcode::COPY),
      GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/0, // dst
      GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/1, // src0
      GIR_ConstrainOperandRC, /*InsnID*/0, /*Op*/0, GIMT_Encode2(AMDGPU::VReg_512RegClassID),
      GIR_EraseFromParent, /*InsnID*/0,
      // GIR_Coverage, 6171,
      GIR_Done,
    // Label 747: @51700
    GIM_Try, /*On fail goto*//*Label 748*/ GIMT_Encode4(51739), // Rule ID 6173 //
      GIM_CheckType, /*MI*/0, /*Op*/1, /*Type*/GILLT_v32s16,
      GIM_CheckRegBankForClass, /*MI*/0, /*Op*/0, /*RC*/GIMT_Encode2(AMDGPU::SReg_512RegClassID),
      GIM_CheckRegBankForClass, /*MI*/0, /*Op*/1, /*RC*/GIMT_Encode2(AMDGPU::SReg_512RegClassID),
      // (bitconvert:{ *:[v16i32] } SReg_512:{ *:[v32bf16] }:$src0)  =>  SReg_512:{ *:[v16i32] }:$src0
      GIR_BuildMI, /*InsnID*/0, /*Opcode*/GIMT_Encode2(TargetOpcode::COPY),
      GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/0, // dst
      GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/1, // src0
      GIR_ConstrainOperandRC, /*InsnID*/0, /*Op*/0, GIMT_Encode2(AMDGPU::SReg_512RegClassID),
      GIR_EraseFromParent, /*InsnID*/0,
      // GIR_Coverage, 6173,
      GIR_Done,
    // Label 748: @51739
    GIM_Try, /*On fail goto*//*Label 749*/ GIMT_Encode4(51778), // Rule ID 6175 //
      GIM_CheckType, /*MI*/0, /*Op*/1, /*Type*/GILLT_v32s16,
      GIM_CheckRegBankForClass, /*MI*/0, /*Op*/0, /*RC*/GIMT_Encode2(AMDGPU::VReg_512RegClassID),
      GIM_CheckRegBankForClass, /*MI*/0, /*Op*/1, /*RC*/GIMT_Encode2(AMDGPU::VReg_512RegClassID),
      // (bitconvert:{ *:[v16f32] } VReg_512:{ *:[v32bf16] }:$src0)  =>  VReg_512:{ *:[v16f32] }:$src0
      GIR_BuildMI, /*InsnID*/0, /*Opcode*/GIMT_Encode2(TargetOpcode::COPY),
      GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/0, // dst
      GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/1, // src0
      GIR_ConstrainOperandRC, /*InsnID*/0, /*Op*/0, GIMT_Encode2(AMDGPU::VReg_512RegClassID),
      GIR_EraseFromParent, /*InsnID*/0,
      // GIR_Coverage, 6175,
      GIR_Done,
    // Label 749: @51778
    GIM_Try, /*On fail goto*//*Label 750*/ GIMT_Encode4(51817), // Rule ID 6177 //
      GIM_CheckType, /*MI*/0, /*Op*/1, /*Type*/GILLT_v32s16,
      GIM_CheckRegBankForClass, /*MI*/0, /*Op*/0, /*RC*/GIMT_Encode2(AMDGPU::SReg_512RegClassID),
      GIM_CheckRegBankForClass, /*MI*/0, /*Op*/1, /*RC*/GIMT_Encode2(AMDGPU::SReg_512RegClassID),
      // (bitconvert:{ *:[v16f32] } SReg_512:{ *:[v32bf16] }:$src0)  =>  SReg_512:{ *:[v16f32] }:$src0
      GIR_BuildMI, /*InsnID*/0, /*Opcode*/GIMT_Encode2(TargetOpcode::COPY),
      GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/0, // dst
      GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/1, // src0
      GIR_ConstrainOperandRC, /*InsnID*/0, /*Op*/0, GIMT_Encode2(AMDGPU::SReg_512RegClassID),
      GIR_EraseFromParent, /*InsnID*/0,
      // GIR_Coverage, 6177,
      GIR_Done,
    // Label 750: @51817
    GIM_Reject,
    // Label 484: @51818
    GIM_Try, /*On fail goto*//*Label 751*/ GIMT_Encode4(51857), // Rule ID 6188 //
      GIM_CheckType, /*MI*/0, /*Op*/1, /*Type*/GILLT_v16s64,
      GIM_CheckRegBankForClass, /*MI*/0, /*Op*/0, /*RC*/GIMT_Encode2(AMDGPU::VReg_1024RegClassID),
      GIM_CheckRegBankForClass, /*MI*/0, /*Op*/1, /*RC*/GIMT_Encode2(AMDGPU::VReg_1024RegClassID),
      // (bitconvert:{ *:[v16i64] } VReg_1024:{ *:[v16f64] }:$src0)  =>  VReg_1024:{ *:[v16i64] }:$src0
      GIR_BuildMI, /*InsnID*/0, /*Opcode*/GIMT_Encode2(TargetOpcode::COPY),
      GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/0, // dst
      GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/1, // src0
      GIR_ConstrainOperandRC, /*InsnID*/0, /*Op*/0, GIMT_Encode2(AMDGPU::VReg_1024RegClassID),
      GIR_EraseFromParent, /*InsnID*/0,
      // GIR_Coverage, 6188,
      GIR_Done,
    // Label 751: @51857
    GIM_Try, /*On fail goto*//*Label 752*/ GIMT_Encode4(51896), // Rule ID 6189 //
      GIM_CheckType, /*MI*/0, /*Op*/1, /*Type*/GILLT_v16s64,
      GIM_CheckRegBankForClass, /*MI*/0, /*Op*/0, /*RC*/GIMT_Encode2(AMDGPU::VReg_1024RegClassID),
      GIM_CheckRegBankForClass, /*MI*/0, /*Op*/1, /*RC*/GIMT_Encode2(AMDGPU::VReg_1024RegClassID),
      // (bitconvert:{ *:[v16f64] } VReg_1024:{ *:[v16i64] }:$src0)  =>  VReg_1024:{ *:[v16f64] }:$src0
      GIR_BuildMI, /*InsnID*/0, /*Opcode*/GIMT_Encode2(TargetOpcode::COPY),
      GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/0, // dst
      GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/1, // src0
      GIR_ConstrainOperandRC, /*InsnID*/0, /*Op*/0, GIMT_Encode2(AMDGPU::VReg_1024RegClassID),
      GIR_EraseFromParent, /*InsnID*/0,
      // GIR_Coverage, 6189,
      GIR_Done,
    // Label 752: @51896
    GIM_Try, /*On fail goto*//*Label 753*/ GIMT_Encode4(51935), // Rule ID 6190 //
      GIM_CheckType, /*MI*/0, /*Op*/1, /*Type*/GILLT_v32s32,
      GIM_CheckRegBankForClass, /*MI*/0, /*Op*/0, /*RC*/GIMT_Encode2(AMDGPU::VReg_1024RegClassID),
      GIM_CheckRegBankForClass, /*MI*/0, /*Op*/1, /*RC*/GIMT_Encode2(AMDGPU::VReg_1024RegClassID),
      // (bitconvert:{ *:[v16i64] } VReg_1024:{ *:[v32i32] }:$src0)  =>  VReg_1024:{ *:[v16i64] }:$src0
      GIR_BuildMI, /*InsnID*/0, /*Opcode*/GIMT_Encode2(TargetOpcode::COPY),
      GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/0, // dst
      GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/1, // src0
      GIR_ConstrainOperandRC, /*InsnID*/0, /*Op*/0, GIMT_Encode2(AMDGPU::VReg_1024RegClassID),
      GIR_EraseFromParent, /*InsnID*/0,
      // GIR_Coverage, 6190,
      GIR_Done,
    // Label 753: @51935
    GIM_Try, /*On fail goto*//*Label 754*/ GIMT_Encode4(51974), // Rule ID 6192 //
      GIM_CheckType, /*MI*/0, /*Op*/1, /*Type*/GILLT_v32s32,
      GIM_CheckRegBankForClass, /*MI*/0, /*Op*/0, /*RC*/GIMT_Encode2(AMDGPU::VReg_1024RegClassID),
      GIM_CheckRegBankForClass, /*MI*/0, /*Op*/1, /*RC*/GIMT_Encode2(AMDGPU::VReg_1024RegClassID),
      // (bitconvert:{ *:[v16f64] } VReg_1024:{ *:[v32f32] }:$src0)  =>  VReg_1024:{ *:[v16f64] }:$src0
      GIR_BuildMI, /*InsnID*/0, /*Opcode*/GIMT_Encode2(TargetOpcode::COPY),
      GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/0, // dst
      GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/1, // src0
      GIR_ConstrainOperandRC, /*InsnID*/0, /*Op*/0, GIMT_Encode2(AMDGPU::VReg_1024RegClassID),
      GIR_EraseFromParent, /*InsnID*/0,
      // GIR_Coverage, 6192,
      GIR_Done,
    // Label 754: @51974
    GIM_Try, /*On fail goto*//*Label 755*/ GIMT_Encode4(52013), // Rule ID 6194 //
      GIM_CheckType, /*MI*/0, /*Op*/1, /*Type*/GILLT_v32s32,
      GIM_CheckRegBankForClass, /*MI*/0, /*Op*/0, /*RC*/GIMT_Encode2(AMDGPU::VReg_1024RegClassID),
      GIM_CheckRegBankForClass, /*MI*/0, /*Op*/1, /*RC*/GIMT_Encode2(AMDGPU::VReg_1024RegClassID),
      // (bitconvert:{ *:[v16i64] } VReg_1024:{ *:[v32f32] }:$src0)  =>  VReg_1024:{ *:[v16i64] }:$src0
      GIR_BuildMI, /*InsnID*/0, /*Opcode*/GIMT_Encode2(TargetOpcode::COPY),
      GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/0, // dst
      GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/1, // src0
      GIR_ConstrainOperandRC, /*InsnID*/0, /*Op*/0, GIMT_Encode2(AMDGPU::VReg_1024RegClassID),
      GIR_EraseFromParent, /*InsnID*/0,
      // GIR_Coverage, 6194,
      GIR_Done,
    // Label 755: @52013
    GIM_Try, /*On fail goto*//*Label 756*/ GIMT_Encode4(52052), // Rule ID 6196 //
      GIM_CheckType, /*MI*/0, /*Op*/1, /*Type*/GILLT_v32s32,
      GIM_CheckRegBankForClass, /*MI*/0, /*Op*/0, /*RC*/GIMT_Encode2(AMDGPU::VReg_1024RegClassID),
      GIM_CheckRegBankForClass, /*MI*/0, /*Op*/1, /*RC*/GIMT_Encode2(AMDGPU::VReg_1024RegClassID),
      // (bitconvert:{ *:[v16f64] } VReg_1024:{ *:[v32i32] }:$src0)  =>  VReg_1024:{ *:[v16f64] }:$src0
      GIR_BuildMI, /*InsnID*/0, /*Opcode*/GIMT_Encode2(TargetOpcode::COPY),
      GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/0, // dst
      GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/1, // src0
      GIR_ConstrainOperandRC, /*InsnID*/0, /*Op*/0, GIMT_Encode2(AMDGPU::VReg_1024RegClassID),
      GIR_EraseFromParent, /*InsnID*/0,
      // GIR_Coverage, 6196,
      GIR_Done,
    // Label 756: @52052
    GIM_Reject,
    // Label 485: @52053
    GIM_Try, /*On fail goto*//*Label 757*/ GIMT_Encode4(52092), // Rule ID 6140 //
      GIM_CheckType, /*MI*/0, /*Op*/1, /*Type*/GILLT_v32s16,
      GIM_CheckRegBankForClass, /*MI*/0, /*Op*/0, /*RC*/GIMT_Encode2(AMDGPU::VReg_512RegClassID),
      GIM_CheckRegBankForClass, /*MI*/0, /*Op*/1, /*RC*/GIMT_Encode2(AMDGPU::VReg_512RegClassID),
      // (bitconvert:{ *:[v32f16] } VReg_512:{ *:[v32i16] }:$src0)  =>  VReg_512:{ *:[v32f16] }:$src0
      GIR_BuildMI, /*InsnID*/0, /*Opcode*/GIMT_Encode2(TargetOpcode::COPY),
      GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/0, // dst
      GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/1, // src0
      GIR_ConstrainOperandRC, /*InsnID*/0, /*Op*/0, GIMT_Encode2(AMDGPU::VReg_512RegClassID),
      GIR_EraseFromParent, /*InsnID*/0,
      // GIR_Coverage, 6140,
      GIR_Done,
    // Label 757: @52092
    GIM_Try, /*On fail goto*//*Label 758*/ GIMT_Encode4(52131), // Rule ID 6141 //
      GIM_CheckType, /*MI*/0, /*Op*/1, /*Type*/GILLT_v32s16,
      GIM_CheckRegBankForClass, /*MI*/0, /*Op*/0, /*RC*/GIMT_Encode2(AMDGPU::VReg_512RegClassID),
      GIM_CheckRegBankForClass, /*MI*/0, /*Op*/1, /*RC*/GIMT_Encode2(AMDGPU::VReg_512RegClassID),
      // (bitconvert:{ *:[v32i16] } VReg_512:{ *:[v32f16] }:$src0)  =>  VReg_512:{ *:[v32i16] }:$src0
      GIR_BuildMI, /*InsnID*/0, /*Opcode*/GIMT_Encode2(TargetOpcode::COPY),
      GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/0, // dst
      GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/1, // src0
      GIR_ConstrainOperandRC, /*InsnID*/0, /*Op*/0, GIMT_Encode2(AMDGPU::VReg_512RegClassID),
      GIR_EraseFromParent, /*InsnID*/0,
      // GIR_Coverage, 6141,
      GIR_Done,
    // Label 758: @52131
    GIM_Try, /*On fail goto*//*Label 759*/ GIMT_Encode4(52170), // Rule ID 6142 //
      GIM_CheckType, /*MI*/0, /*Op*/1, /*Type*/GILLT_v16s32,
      GIM_CheckRegBankForClass, /*MI*/0, /*Op*/0, /*RC*/GIMT_Encode2(AMDGPU::VReg_512RegClassID),
      GIM_CheckRegBankForClass, /*MI*/0, /*Op*/1, /*RC*/GIMT_Encode2(AMDGPU::VReg_512RegClassID),
      // (bitconvert:{ *:[v32f16] } VReg_512:{ *:[v16i32] }:$src0)  =>  VReg_512:{ *:[v32f16] }:$src0
      GIR_BuildMI, /*InsnID*/0, /*Opcode*/GIMT_Encode2(TargetOpcode::COPY),
      GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/0, // dst
      GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/1, // src0
      GIR_ConstrainOperandRC, /*InsnID*/0, /*Op*/0, GIMT_Encode2(AMDGPU::VReg_512RegClassID),
      GIR_EraseFromParent, /*InsnID*/0,
      // GIR_Coverage, 6142,
      GIR_Done,
    // Label 759: @52170
    GIM_Try, /*On fail goto*//*Label 760*/ GIMT_Encode4(52209), // Rule ID 6143 //
      GIM_CheckType, /*MI*/0, /*Op*/1, /*Type*/GILLT_v16s32,
      GIM_CheckRegBankForClass, /*MI*/0, /*Op*/0, /*RC*/GIMT_Encode2(AMDGPU::VReg_512RegClassID),
      GIM_CheckRegBankForClass, /*MI*/0, /*Op*/1, /*RC*/GIMT_Encode2(AMDGPU::VReg_512RegClassID),
      // (bitconvert:{ *:[v32f16] } VReg_512:{ *:[v16f32] }:$src0)  =>  VReg_512:{ *:[v32f16] }:$src0
      GIR_BuildMI, /*InsnID*/0, /*Opcode*/GIMT_Encode2(TargetOpcode::COPY),
      GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/0, // dst
      GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/1, // src0
      GIR_ConstrainOperandRC, /*InsnID*/0, /*Op*/0, GIMT_Encode2(AMDGPU::VReg_512RegClassID),
      GIR_EraseFromParent, /*InsnID*/0,
      // GIR_Coverage, 6143,
      GIR_Done,
    // Label 760: @52209
    GIM_Try, /*On fail goto*//*Label 761*/ GIMT_Encode4(52248), // Rule ID 6146 //
      GIM_CheckType, /*MI*/0, /*Op*/1, /*Type*/GILLT_v16s32,
      GIM_CheckRegBankForClass, /*MI*/0, /*Op*/0, /*RC*/GIMT_Encode2(AMDGPU::VReg_512RegClassID),
      GIM_CheckRegBankForClass, /*MI*/0, /*Op*/1, /*RC*/GIMT_Encode2(AMDGPU::VReg_512RegClassID),
      // (bitconvert:{ *:[v32i16] } VReg_512:{ *:[v16i32] }:$src0)  =>  VReg_512:{ *:[v32i16] }:$src0
      GIR_BuildMI, /*InsnID*/0, /*Opcode*/GIMT_Encode2(TargetOpcode::COPY),
      GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/0, // dst
      GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/1, // src0
      GIR_ConstrainOperandRC, /*InsnID*/0, /*Op*/0, GIMT_Encode2(AMDGPU::VReg_512RegClassID),
      GIR_EraseFromParent, /*InsnID*/0,
      // GIR_Coverage, 6146,
      GIR_Done,
    // Label 761: @52248
    GIM_Try, /*On fail goto*//*Label 762*/ GIMT_Encode4(52287), // Rule ID 6147 //
      GIM_CheckType, /*MI*/0, /*Op*/1, /*Type*/GILLT_v16s32,
      GIM_CheckRegBankForClass, /*MI*/0, /*Op*/0, /*RC*/GIMT_Encode2(AMDGPU::VReg_512RegClassID),
      GIM_CheckRegBankForClass, /*MI*/0, /*Op*/1, /*RC*/GIMT_Encode2(AMDGPU::VReg_512RegClassID),
      // (bitconvert:{ *:[v32i16] } VReg_512:{ *:[v16f32] }:$src0)  =>  VReg_512:{ *:[v32i16] }:$src0
      GIR_BuildMI, /*InsnID*/0, /*Opcode*/GIMT_Encode2(TargetOpcode::COPY),
      GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/0, // dst
      GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/1, // src0
      GIR_ConstrainOperandRC, /*InsnID*/0, /*Op*/0, GIMT_Encode2(AMDGPU::VReg_512RegClassID),
      GIR_EraseFromParent, /*InsnID*/0,
      // GIR_Coverage, 6147,
      GIR_Done,
    // Label 762: @52287
    GIM_Try, /*On fail goto*//*Label 763*/ GIMT_Encode4(52326), // Rule ID 6162 //
      GIM_CheckType, /*MI*/0, /*Op*/1, /*Type*/GILLT_v32s16,
      GIM_CheckRegBankForClass, /*MI*/0, /*Op*/0, /*RC*/GIMT_Encode2(AMDGPU::VReg_512RegClassID),
      GIM_CheckRegBankForClass, /*MI*/0, /*Op*/1, /*RC*/GIMT_Encode2(AMDGPU::VReg_512RegClassID),
      // (bitconvert:{ *:[v32bf16] } VReg_512:{ *:[v32i16] }:$src0)  =>  VReg_512:{ *:[v32bf16] }:$src0
      GIR_BuildMI, /*InsnID*/0, /*Opcode*/GIMT_Encode2(TargetOpcode::COPY),
      GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/0, // dst
      GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/1, // src0
      GIR_ConstrainOperandRC, /*InsnID*/0, /*Op*/0, GIMT_Encode2(AMDGPU::VReg_512RegClassID),
      GIR_EraseFromParent, /*InsnID*/0,
      // GIR_Coverage, 6162,
      GIR_Done,
    // Label 763: @52326
    GIM_Try, /*On fail goto*//*Label 764*/ GIMT_Encode4(52365), // Rule ID 6163 //
      GIM_CheckType, /*MI*/0, /*Op*/1, /*Type*/GILLT_v32s16,
      GIM_CheckRegBankForClass, /*MI*/0, /*Op*/0, /*RC*/GIMT_Encode2(AMDGPU::VReg_512RegClassID),
      GIM_CheckRegBankForClass, /*MI*/0, /*Op*/1, /*RC*/GIMT_Encode2(AMDGPU::VReg_512RegClassID),
      // (bitconvert:{ *:[v32i16] } VReg_512:{ *:[v32bf16] }:$src0)  =>  VReg_512:{ *:[v32i16] }:$src0
      GIR_BuildMI, /*InsnID*/0, /*Opcode*/GIMT_Encode2(TargetOpcode::COPY),
      GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/0, // dst
      GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/1, // src0
      GIR_ConstrainOperandRC, /*InsnID*/0, /*Op*/0, GIMT_Encode2(AMDGPU::VReg_512RegClassID),
      GIR_EraseFromParent, /*InsnID*/0,
      // GIR_Coverage, 6163,
      GIR_Done,
    // Label 764: @52365
    GIM_Try, /*On fail goto*//*Label 765*/ GIMT_Encode4(52404), // Rule ID 6164 //
      GIM_CheckType, /*MI*/0, /*Op*/1, /*Type*/GILLT_v32s16,
      GIM_CheckRegBankForClass, /*MI*/0, /*Op*/0, /*RC*/GIMT_Encode2(AMDGPU::SReg_512RegClassID),
      GIM_CheckRegBankForClass, /*MI*/0, /*Op*/1, /*RC*/GIMT_Encode2(AMDGPU::SReg_512RegClassID),
      // (bitconvert:{ *:[v32bf16] } SReg_512:{ *:[v32i16] }:$src0)  =>  SReg_512:{ *:[v32bf16] }:$src0
      GIR_BuildMI, /*InsnID*/0, /*Opcode*/GIMT_Encode2(TargetOpcode::COPY),
      GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/0, // dst
      GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/1, // src0
      GIR_ConstrainOperandRC, /*InsnID*/0, /*Op*/0, GIMT_Encode2(AMDGPU::SReg_512RegClassID),
      GIR_EraseFromParent, /*InsnID*/0,
      // GIR_Coverage, 6164,
      GIR_Done,
    // Label 765: @52404
    GIM_Try, /*On fail goto*//*Label 766*/ GIMT_Encode4(52443), // Rule ID 6165 //
      GIM_CheckType, /*MI*/0, /*Op*/1, /*Type*/GILLT_v32s16,
      GIM_CheckRegBankForClass, /*MI*/0, /*Op*/0, /*RC*/GIMT_Encode2(AMDGPU::SReg_512RegClassID),
      GIM_CheckRegBankForClass, /*MI*/0, /*Op*/1, /*RC*/GIMT_Encode2(AMDGPU::SReg_512RegClassID),
      // (bitconvert:{ *:[v32i16] } SReg_512:{ *:[v32bf16] }:$src0)  =>  SReg_512:{ *:[v32i16] }:$src0
      GIR_BuildMI, /*InsnID*/0, /*Opcode*/GIMT_Encode2(TargetOpcode::COPY),
      GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/0, // dst
      GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/1, // src0
      GIR_ConstrainOperandRC, /*InsnID*/0, /*Op*/0, GIMT_Encode2(AMDGPU::SReg_512RegClassID),
      GIR_EraseFromParent, /*InsnID*/0,
      // GIR_Coverage, 6165,
      GIR_Done,
    // Label 766: @52443
    GIM_Try, /*On fail goto*//*Label 767*/ GIMT_Encode4(52482), // Rule ID 6166 //
      GIM_CheckType, /*MI*/0, /*Op*/1, /*Type*/GILLT_v32s16,
      GIM_CheckRegBankForClass, /*MI*/0, /*Op*/0, /*RC*/GIMT_Encode2(AMDGPU::VReg_512RegClassID),
      GIM_CheckRegBankForClass, /*MI*/0, /*Op*/1, /*RC*/GIMT_Encode2(AMDGPU::VReg_512RegClassID),
      // (bitconvert:{ *:[v32bf16] } VReg_512:{ *:[v32f16] }:$src0)  =>  VReg_512:{ *:[v32bf16] }:$src0
      GIR_BuildMI, /*InsnID*/0, /*Opcode*/GIMT_Encode2(TargetOpcode::COPY),
      GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/0, // dst
      GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/1, // src0
      GIR_ConstrainOperandRC, /*InsnID*/0, /*Op*/0, GIMT_Encode2(AMDGPU::VReg_512RegClassID),
      GIR_EraseFromParent, /*InsnID*/0,
      // GIR_Coverage, 6166,
      GIR_Done,
    // Label 767: @52482
    GIM_Try, /*On fail goto*//*Label 768*/ GIMT_Encode4(52521), // Rule ID 6167 //
      GIM_CheckType, /*MI*/0, /*Op*/1, /*Type*/GILLT_v32s16,
      GIM_CheckRegBankForClass, /*MI*/0, /*Op*/0, /*RC*/GIMT_Encode2(AMDGPU::VReg_512RegClassID),
      GIM_CheckRegBankForClass, /*MI*/0, /*Op*/1, /*RC*/GIMT_Encode2(AMDGPU::VReg_512RegClassID),
      // (bitconvert:{ *:[v32f16] } VReg_512:{ *:[v32bf16] }:$src0)  =>  VReg_512:{ *:[v32f16] }:$src0
      GIR_BuildMI, /*InsnID*/0, /*Opcode*/GIMT_Encode2(TargetOpcode::COPY),
      GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/0, // dst
      GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/1, // src0
      GIR_ConstrainOperandRC, /*InsnID*/0, /*Op*/0, GIMT_Encode2(AMDGPU::VReg_512RegClassID),
      GIR_EraseFromParent, /*InsnID*/0,
      // GIR_Coverage, 6167,
      GIR_Done,
    // Label 768: @52521
    GIM_Try, /*On fail goto*//*Label 769*/ GIMT_Encode4(52560), // Rule ID 6168 //
      GIM_CheckType, /*MI*/0, /*Op*/1, /*Type*/GILLT_v32s16,
      GIM_CheckRegBankForClass, /*MI*/0, /*Op*/0, /*RC*/GIMT_Encode2(AMDGPU::SReg_512RegClassID),
      GIM_CheckRegBankForClass, /*MI*/0, /*Op*/1, /*RC*/GIMT_Encode2(AMDGPU::SReg_512RegClassID),
      // (bitconvert:{ *:[v32bf16] } SReg_512:{ *:[v32f16] }:$src0)  =>  SReg_512:{ *:[v32bf16] }:$src0
      GIR_BuildMI, /*InsnID*/0, /*Opcode*/GIMT_Encode2(TargetOpcode::COPY),
      GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/0, // dst
      GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/1, // src0
      GIR_ConstrainOperandRC, /*InsnID*/0, /*Op*/0, GIMT_Encode2(AMDGPU::SReg_512RegClassID),
      GIR_EraseFromParent, /*InsnID*/0,
      // GIR_Coverage, 6168,
      GIR_Done,
    // Label 769: @52560
    GIM_Try, /*On fail goto*//*Label 770*/ GIMT_Encode4(52599), // Rule ID 6169 //
      GIM_CheckType, /*MI*/0, /*Op*/1, /*Type*/GILLT_v32s16,
      GIM_CheckRegBankForClass, /*MI*/0, /*Op*/0, /*RC*/GIMT_Encode2(AMDGPU::SReg_512RegClassID),
      GIM_CheckRegBankForClass, /*MI*/0, /*Op*/1, /*RC*/GIMT_Encode2(AMDGPU::SReg_512RegClassID),
      // (bitconvert:{ *:[v32f16] } SReg_512:{ *:[v32bf16] }:$src0)  =>  SReg_512:{ *:[v32f16] }:$src0
      GIR_BuildMI, /*InsnID*/0, /*Opcode*/GIMT_Encode2(TargetOpcode::COPY),
      GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/0, // dst
      GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/1, // src0
      GIR_ConstrainOperandRC, /*InsnID*/0, /*Op*/0, GIMT_Encode2(AMDGPU::SReg_512RegClassID),
      GIR_EraseFromParent, /*InsnID*/0,
      // GIR_Coverage, 6169,
      GIR_Done,
    // Label 770: @52599
    GIM_Try, /*On fail goto*//*Label 771*/ GIMT_Encode4(52638), // Rule ID 6170 //
      GIM_CheckType, /*MI*/0, /*Op*/1, /*Type*/GILLT_v16s32,
      GIM_CheckRegBankForClass, /*MI*/0, /*Op*/0, /*RC*/GIMT_Encode2(AMDGPU::VReg_512RegClassID),
      GIM_CheckRegBankForClass, /*MI*/0, /*Op*/1, /*RC*/GIMT_Encode2(AMDGPU::VReg_512RegClassID),
      // (bitconvert:{ *:[v32bf16] } VReg_512:{ *:[v16i32] }:$src0)  =>  VReg_512:{ *:[v32bf16] }:$src0
      GIR_BuildMI, /*InsnID*/0, /*Opcode*/GIMT_Encode2(TargetOpcode::COPY),
      GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/0, // dst
      GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/1, // src0
      GIR_ConstrainOperandRC, /*InsnID*/0, /*Op*/0, GIMT_Encode2(AMDGPU::VReg_512RegClassID),
      GIR_EraseFromParent, /*InsnID*/0,
      // GIR_Coverage, 6170,
      GIR_Done,
    // Label 771: @52638
    GIM_Try, /*On fail goto*//*Label 772*/ GIMT_Encode4(52677), // Rule ID 6172 //
      GIM_CheckType, /*MI*/0, /*Op*/1, /*Type*/GILLT_v16s32,
      GIM_CheckRegBankForClass, /*MI*/0, /*Op*/0, /*RC*/GIMT_Encode2(AMDGPU::SReg_512RegClassID),
      GIM_CheckRegBankForClass, /*MI*/0, /*Op*/1, /*RC*/GIMT_Encode2(AMDGPU::SReg_512RegClassID),
      // (bitconvert:{ *:[v32bf16] } SReg_512:{ *:[v16i32] }:$src0)  =>  SReg_512:{ *:[v32bf16] }:$src0
      GIR_BuildMI, /*InsnID*/0, /*Opcode*/GIMT_Encode2(TargetOpcode::COPY),
      GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/0, // dst
      GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/1, // src0
      GIR_ConstrainOperandRC, /*InsnID*/0, /*Op*/0, GIMT_Encode2(AMDGPU::SReg_512RegClassID),
      GIR_EraseFromParent, /*InsnID*/0,
      // GIR_Coverage, 6172,
      GIR_Done,
    // Label 772: @52677
    GIM_Try, /*On fail goto*//*Label 773*/ GIMT_Encode4(52716), // Rule ID 6174 //
      GIM_CheckType, /*MI*/0, /*Op*/1, /*Type*/GILLT_v16s32,
      GIM_CheckRegBankForClass, /*MI*/0, /*Op*/0, /*RC*/GIMT_Encode2(AMDGPU::VReg_512RegClassID),
      GIM_CheckRegBankForClass, /*MI*/0, /*Op*/1, /*RC*/GIMT_Encode2(AMDGPU::VReg_512RegClassID),
      // (bitconvert:{ *:[v32bf16] } VReg_512:{ *:[v16f32] }:$src0)  =>  VReg_512:{ *:[v32bf16] }:$src0
      GIR_BuildMI, /*InsnID*/0, /*Opcode*/GIMT_Encode2(TargetOpcode::COPY),
      GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/0, // dst
      GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/1, // src0
      GIR_ConstrainOperandRC, /*InsnID*/0, /*Op*/0, GIMT_Encode2(AMDGPU::VReg_512RegClassID),
      GIR_EraseFromParent, /*InsnID*/0,
      // GIR_Coverage, 6174,
      GIR_Done,
    // Label 773: @52716
    GIM_Try, /*On fail goto*//*Label 774*/ GIMT_Encode4(52755), // Rule ID 6176 //
      GIM_CheckType, /*MI*/0, /*Op*/1, /*Type*/GILLT_v16s32,
      GIM_CheckRegBankForClass, /*MI*/0, /*Op*/0, /*RC*/GIMT_Encode2(AMDGPU::SReg_512RegClassID),
      GIM_CheckRegBankForClass, /*MI*/0, /*Op*/1, /*RC*/GIMT_Encode2(AMDGPU::SReg_512RegClassID),
      // (bitconvert:{ *:[v32bf16] } SReg_512:{ *:[v16f32] }:$src0)  =>  SReg_512:{ *:[v32bf16] }:$src0
      GIR_BuildMI, /*InsnID*/0, /*Opcode*/GIMT_Encode2(TargetOpcode::COPY),
      GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/0, // dst
      GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/1, // src0
      GIR_ConstrainOperandRC, /*InsnID*/0, /*Op*/0, GIMT_Encode2(AMDGPU::SReg_512RegClassID),
      GIR_EraseFromParent, /*InsnID*/0,
      // GIR_Coverage, 6176,
      GIR_Done,
    // Label 774: @52755
    GIM_Try, /*On fail goto*//*Label 775*/ GIMT_Encode4(52794), // Rule ID 6178 //
      GIM_CheckType, /*MI*/0, /*Op*/1, /*Type*/GILLT_v8s64,
      GIM_CheckRegBankForClass, /*MI*/0, /*Op*/0, /*RC*/GIMT_Encode2(AMDGPU::VReg_512RegClassID),
      GIM_CheckRegBankForClass, /*MI*/0, /*Op*/1, /*RC*/GIMT_Encode2(AMDGPU::VReg_512RegClassID),
      // (bitconvert:{ *:[v32bf16] } VReg_512:{ *:[v8f64] }:$src0)  =>  VReg_512:{ *:[v32bf16] }:$src0
      GIR_BuildMI, /*InsnID*/0, /*Opcode*/GIMT_Encode2(TargetOpcode::COPY),
      GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/0, // dst
      GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/1, // src0
      GIR_ConstrainOperandRC, /*InsnID*/0, /*Op*/0, GIMT_Encode2(AMDGPU::VReg_512RegClassID),
      GIR_EraseFromParent, /*InsnID*/0,
      // GIR_Coverage, 6178,
      GIR_Done,
    // Label 775: @52794
    GIM_Try, /*On fail goto*//*Label 776*/ GIMT_Encode4(52833), // Rule ID 6180 //
      GIM_CheckType, /*MI*/0, /*Op*/1, /*Type*/GILLT_v8s64,
      GIM_CheckRegBankForClass, /*MI*/0, /*Op*/0, /*RC*/GIMT_Encode2(AMDGPU::SReg_512RegClassID),
      GIM_CheckRegBankForClass, /*MI*/0, /*Op*/1, /*RC*/GIMT_Encode2(AMDGPU::SReg_512RegClassID),
      // (bitconvert:{ *:[v32bf16] } SReg_512:{ *:[v8f64] }:$src0)  =>  SReg_512:{ *:[v32bf16] }:$src0
      GIR_BuildMI, /*InsnID*/0, /*Opcode*/GIMT_Encode2(TargetOpcode::COPY),
      GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/0, // dst
      GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/1, // src0
      GIR_ConstrainOperandRC, /*InsnID*/0, /*Op*/0, GIMT_Encode2(AMDGPU::SReg_512RegClassID),
      GIR_EraseFromParent, /*InsnID*/0,
      // GIR_Coverage, 6180,
      GIR_Done,
    // Label 776: @52833
    GIM_Try, /*On fail goto*//*Label 777*/ GIMT_Encode4(52872), // Rule ID 6182 //
      GIM_CheckType, /*MI*/0, /*Op*/1, /*Type*/GILLT_v8s64,
      GIM_CheckRegBankForClass, /*MI*/0, /*Op*/0, /*RC*/GIMT_Encode2(AMDGPU::VReg_512RegClassID),
      GIM_CheckRegBankForClass, /*MI*/0, /*Op*/1, /*RC*/GIMT_Encode2(AMDGPU::VReg_512RegClassID),
      // (bitconvert:{ *:[v32bf16] } VReg_512:{ *:[v8i64] }:$src0)  =>  VReg_512:{ *:[v32bf16] }:$src0
      GIR_BuildMI, /*InsnID*/0, /*Opcode*/GIMT_Encode2(TargetOpcode::COPY),
      GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/0, // dst
      GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/1, // src0
      GIR_ConstrainOperandRC, /*InsnID*/0, /*Op*/0, GIMT_Encode2(AMDGPU::VReg_512RegClassID),
      GIR_EraseFromParent, /*InsnID*/0,
      // GIR_Coverage, 6182,
      GIR_Done,
    // Label 777: @52872
    GIM_Try, /*On fail goto*//*Label 778*/ GIMT_Encode4(52911), // Rule ID 6184 //
      GIM_CheckType, /*MI*/0, /*Op*/1, /*Type*/GILLT_v8s64,
      GIM_CheckRegBankForClass, /*MI*/0, /*Op*/0, /*RC*/GIMT_Encode2(AMDGPU::SReg_512RegClassID),
      GIM_CheckRegBankForClass, /*MI*/0, /*Op*/1, /*RC*/GIMT_Encode2(AMDGPU::SReg_512RegClassID),
      // (bitconvert:{ *:[v32bf16] } SReg_512:{ *:[v8i64] }:$src0)  =>  SReg_512:{ *:[v32bf16] }:$src0
      GIR_BuildMI, /*InsnID*/0, /*Opcode*/GIMT_Encode2(TargetOpcode::COPY),
      GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/0, // dst
      GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/1, // src0
      GIR_ConstrainOperandRC, /*InsnID*/0, /*Op*/0, GIMT_Encode2(AMDGPU::SReg_512RegClassID),
      GIR_EraseFromParent, /*InsnID*/0,
      // GIR_Coverage, 6184,
      GIR_Done,
    // Label 778: @52911
    GIM_Reject,
    // Label 486: @52912
    GIM_Try, /*On fail goto*//*Label 779*/ GIMT_Encode4(52951), // Rule ID 6186 //
      GIM_CheckType, /*MI*/0, /*Op*/1, /*Type*/GILLT_v32s32,
      GIM_CheckRegBankForClass, /*MI*/0, /*Op*/0, /*RC*/GIMT_Encode2(AMDGPU::VReg_1024RegClassID),
      GIM_CheckRegBankForClass, /*MI*/0, /*Op*/1, /*RC*/GIMT_Encode2(AMDGPU::VReg_1024RegClassID),
      // (bitconvert:{ *:[v32i32] } VReg_1024:{ *:[v32f32] }:$src0)  =>  VReg_1024:{ *:[v32i32] }:$src0
      GIR_BuildMI, /*InsnID*/0, /*Opcode*/GIMT_Encode2(TargetOpcode::COPY),
      GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/0, // dst
      GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/1, // src0
      GIR_ConstrainOperandRC, /*InsnID*/0, /*Op*/0, GIMT_Encode2(AMDGPU::VReg_1024RegClassID),
      GIR_EraseFromParent, /*InsnID*/0,
      // GIR_Coverage, 6186,
      GIR_Done,
    // Label 779: @52951
    GIM_Try, /*On fail goto*//*Label 780*/ GIMT_Encode4(52990), // Rule ID 6187 //
      GIM_CheckType, /*MI*/0, /*Op*/1, /*Type*/GILLT_v32s32,
      GIM_CheckRegBankForClass, /*MI*/0, /*Op*/0, /*RC*/GIMT_Encode2(AMDGPU::VReg_1024RegClassID),
      GIM_CheckRegBankForClass, /*MI*/0, /*Op*/1, /*RC*/GIMT_Encode2(AMDGPU::VReg_1024RegClassID),
      // (bitconvert:{ *:[v32f32] } VReg_1024:{ *:[v32i32] }:$src0)  =>  VReg_1024:{ *:[v32f32] }:$src0
      GIR_BuildMI, /*InsnID*/0, /*Opcode*/GIMT_Encode2(TargetOpcode::COPY),
      GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/0, // dst
      GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/1, // src0
      GIR_ConstrainOperandRC, /*InsnID*/0, /*Op*/0, GIMT_Encode2(AMDGPU::VReg_1024RegClassID),
      GIR_EraseFromParent, /*InsnID*/0,
      // GIR_Coverage, 6187,
      GIR_Done,
    // Label 780: @52990
    GIM_Try, /*On fail goto*//*Label 781*/ GIMT_Encode4(53029), // Rule ID 6191 //
      GIM_CheckType, /*MI*/0, /*Op*/1, /*Type*/GILLT_v16s64,
      GIM_CheckRegBankForClass, /*MI*/0, /*Op*/0, /*RC*/GIMT_Encode2(AMDGPU::VReg_1024RegClassID),
      GIM_CheckRegBankForClass, /*MI*/0, /*Op*/1, /*RC*/GIMT_Encode2(AMDGPU::VReg_1024RegClassID),
      // (bitconvert:{ *:[v32i32] } VReg_1024:{ *:[v16i64] }:$src0)  =>  VReg_1024:{ *:[v32i32] }:$src0
      GIR_BuildMI, /*InsnID*/0, /*Opcode*/GIMT_Encode2(TargetOpcode::COPY),
      GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/0, // dst
      GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/1, // src0
      GIR_ConstrainOperandRC, /*InsnID*/0, /*Op*/0, GIMT_Encode2(AMDGPU::VReg_1024RegClassID),
      GIR_EraseFromParent, /*InsnID*/0,
      // GIR_Coverage, 6191,
      GIR_Done,
    // Label 781: @53029
    GIM_Try, /*On fail goto*//*Label 782*/ GIMT_Encode4(53068), // Rule ID 6193 //
      GIM_CheckType, /*MI*/0, /*Op*/1, /*Type*/GILLT_v16s64,
      GIM_CheckRegBankForClass, /*MI*/0, /*Op*/0, /*RC*/GIMT_Encode2(AMDGPU::VReg_1024RegClassID),
      GIM_CheckRegBankForClass, /*MI*/0, /*Op*/1, /*RC*/GIMT_Encode2(AMDGPU::VReg_1024RegClassID),
      // (bitconvert:{ *:[v32f32] } VReg_1024:{ *:[v16f64] }:$src0)  =>  VReg_1024:{ *:[v32f32] }:$src0
      GIR_BuildMI, /*InsnID*/0, /*Opcode*/GIMT_Encode2(TargetOpcode::COPY),
      GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/0, // dst
      GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/1, // src0
      GIR_ConstrainOperandRC, /*InsnID*/0, /*Op*/0, GIMT_Encode2(AMDGPU::VReg_1024RegClassID),
      GIR_EraseFromParent, /*InsnID*/0,
      // GIR_Coverage, 6193,
      GIR_Done,
    // Label 782: @53068
    GIM_Try, /*On fail goto*//*Label 783*/ GIMT_Encode4(53107), // Rule ID 6195 //
      GIM_CheckType, /*MI*/0, /*Op*/1, /*Type*/GILLT_v16s64,
      GIM_CheckRegBankForClass, /*MI*/0, /*Op*/0, /*RC*/GIMT_Encode2(AMDGPU::VReg_1024RegClassID),
      GIM_CheckRegBankForClass, /*MI*/0, /*Op*/1, /*RC*/GIMT_Encode2(AMDGPU::VReg_1024RegClassID),
      // (bitconvert:{ *:[v32i32] } VReg_1024:{ *:[v16f64] }:$src0)  =>  VReg_1024:{ *:[v32i32] }:$src0
      GIR_BuildMI, /*InsnID*/0, /*Opcode*/GIMT_Encode2(TargetOpcode::COPY),
      GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/0, // dst
      GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/1, // src0
      GIR_ConstrainOperandRC, /*InsnID*/0, /*Op*/0, GIMT_Encode2(AMDGPU::VReg_1024RegClassID),
      GIR_EraseFromParent, /*InsnID*/0,
      // GIR_Coverage, 6195,
      GIR_Done,
    // Label 783: @53107
    GIM_Try, /*On fail goto*//*Label 784*/ GIMT_Encode4(53146), // Rule ID 6197 //
      GIM_CheckType, /*MI*/0, /*Op*/1, /*Type*/GILLT_v16s64,
      GIM_CheckRegBankForClass, /*MI*/0, /*Op*/0, /*RC*/GIMT_Encode2(AMDGPU::VReg_1024RegClassID),
      GIM_CheckRegBankForClass, /*MI*/0, /*Op*/1, /*RC*/GIMT_Encode2(AMDGPU::VReg_1024RegClassID),
      // (bitconvert:{ *:[v32f32] } VReg_1024:{ *:[v16i64] }:$src0)  =>  VReg_1024:{ *:[v32f32] }:$src0
      GIR_BuildMI, /*InsnID*/0, /*Opcode*/GIMT_Encode2(TargetOpcode::COPY),
      GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/0, // dst
      GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/1, // src0
      GIR_ConstrainOperandRC, /*InsnID*/0, /*Op*/0, GIMT_Encode2(AMDGPU::VReg_1024RegClassID),
      GIR_EraseFromParent, /*InsnID*/0,
      // GIR_Coverage, 6197,
      GIR_Done,
    // Label 784: @53146
    GIM_Reject,
    // Label 487: @53147
    GIM_Reject,
    // Label 9: @53148
    GIM_SwitchType, /*MI*/0, /*Op*/0, /*[*/GIMT_Encode2(8), GIMT_Encode2(11), /*)*//*default:*//*Label 788*/ GIMT_Encode4(53518),
    /*GILLT_s16*//*Label 785*/ GIMT_Encode4(53171),
    /*GILLT_s32*//*Label 786*/ GIMT_Encode4(53370),
    /*GILLT_s64*//*Label 787*/ GIMT_Encode4(53460),
    // Label 785: @53171
    GIM_Try, /*On fail goto*//*Label 789*/ GIMT_Encode4(53369),
      GIM_CheckType, /*MI*/0, /*Op*/1, /*Type*/GILLT_s16,
      GIM_Try, /*On fail goto*//*Label 790*/ GIMT_Encode4(53209), // Rule ID 39 //
        GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasSALUFloatInsts),
        GIM_CheckRegBankForClass, /*MI*/0, /*Op*/0, /*RC*/GIMT_Encode2(AMDGPU::SReg_32RegClassID),
        GIM_CheckCxxInsnPredicate, /*MI*/0, /*FnId*/GIMT_Encode2(GICXXPred_MI_Predicate_anonymous_17600),
        // (ftrunc:{ *:[f16] } f16:{ *:[f16] }:$src0)<<P:Predicate_anonymous_17600>>  =>  (S_TRUNC_F16:{ *:[f16] } f16:{ *:[f16] }:$src0)
        GIR_MutateOpcode, /*InsnID*/0, /*RecycleInsnID*/0, /*Opcode*/GIMT_Encode2(AMDGPU::S_TRUNC_F16),
        GIR_AddImplicitUse, /*InsnID*/0, GIMT_Encode2(AMDGPU::MODE),
        GIR_ConstrainSelectedInstOperands, /*InsnID*/0,
        // GIR_Coverage, 39,
        GIR_Done,
      // Label 790: @53209
      GIM_Try, /*On fail goto*//*Label 791*/ GIMT_Encode4(53262), // Rule ID 710 //
        GIM_CheckFeatures, GIMT_Encode2(GIFBS_Has16BitInsts_NotHasTrue16BitInsts),
        GIM_CheckRegBankForClass, /*MI*/0, /*Op*/0, /*RC*/GIMT_Encode2(AMDGPU::VGPR_32RegClassID),
        GIM_CheckComplexPattern, /*MI*/0, /*Op*/1, /*Renderer*/GIMT_Encode2(0), GIMT_Encode2(GICP_gi_vop3mods0),
        // (ftrunc:{ *:[f16] } (VOP3Mods0:{ *:[f16] } f16:{ *:[f16] }:$src0, i32:{ *:[i32] }:$src0_modifiers, i1:{ *:[i1] }:$clamp, i32:{ *:[i32] }:$omod))  =>  (V_TRUNC_F16_e64:{ *:[f16] } i32:{ *:[i32] }:$src0_modifiers, f16:{ *:[f16] }:$src0, i1:{ *:[i1] }:$clamp, i32:{ *:[i32] }:$omod)
        GIR_BuildMI, /*InsnID*/0, /*Opcode*/GIMT_Encode2(AMDGPU::V_TRUNC_F16_e64),
        GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/0, // DstI[vdst]
        GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/1, // src0_modifiers
        GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/0, // src0
        GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/2, // clamp
        GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/3, // omod
        GIR_ConstrainSelectedInstOperands, /*InsnID*/0,
        GIR_EraseFromParent, /*InsnID*/0,
        // GIR_Coverage, 710,
        GIR_Done,
      // Label 791: @53262
      GIM_Try, /*On fail goto*//*Label 792*/ GIMT_Encode4(53315), // Rule ID 711 //
        GIM_CheckFeatures, GIMT_Encode2(GIFBS_UseRealTrue16Insts),
        GIM_CheckRegBankForClass, /*MI*/0, /*Op*/0, /*RC*/GIMT_Encode2(AMDGPU::VGPR_16RegClassID),
        GIM_CheckComplexPattern, /*MI*/0, /*Op*/1, /*Renderer*/GIMT_Encode2(0), GIMT_Encode2(GICP_gi_vop3mods0),
        // (ftrunc:{ *:[f16] } (VOP3Mods0:{ *:[f16] } f16:{ *:[f16] }:$src0, i32:{ *:[i32] }:$src0_modifiers, i1:{ *:[i1] }:$clamp, i32:{ *:[i32] }:$omod))  =>  (V_TRUNC_F16_t16_e64:{ *:[f16] } i32:{ *:[i32] }:$src0_modifiers, f16:{ *:[f16] }:$src0, i1:{ *:[i1] }:$clamp, i32:{ *:[i32] }:$omod)
        GIR_BuildMI, /*InsnID*/0, /*Opcode*/GIMT_Encode2(AMDGPU::V_TRUNC_F16_t16_e64),
        GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/0, // DstI[vdst]
        GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/1, // src0_modifiers
        GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/0, // src0
        GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/2, // clamp
        GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/3, // omod
        GIR_ConstrainSelectedInstOperands, /*InsnID*/0,
        GIR_EraseFromParent, /*InsnID*/0,
        // GIR_Coverage, 711,
        GIR_Done,
      // Label 792: @53315
      GIM_Try, /*On fail goto*//*Label 793*/ GIMT_Encode4(53368), // Rule ID 712 //
        GIM_CheckFeatures, GIMT_Encode2(GIFBS_UseFakeTrue16Insts),
        GIM_CheckRegBankForClass, /*MI*/0, /*Op*/0, /*RC*/GIMT_Encode2(AMDGPU::VGPR_32RegClassID),
        GIM_CheckComplexPattern, /*MI*/0, /*Op*/1, /*Renderer*/GIMT_Encode2(0), GIMT_Encode2(GICP_gi_vop3mods0),
        // (ftrunc:{ *:[f16] } (VOP3Mods0:{ *:[f16] } f16:{ *:[f16] }:$src0, i32:{ *:[i32] }:$src0_modifiers, i1:{ *:[i1] }:$clamp, i32:{ *:[i32] }:$omod))  =>  (V_TRUNC_F16_fake16_e64:{ *:[f16] } i32:{ *:[i32] }:$src0_modifiers, f16:{ *:[f16] }:$src0, i1:{ *:[i1] }:$clamp, i32:{ *:[i32] }:$omod)
        GIR_BuildMI, /*InsnID*/0, /*Opcode*/GIMT_Encode2(AMDGPU::V_TRUNC_F16_fake16_e64),
        GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/0, // DstI[vdst]
        GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/1, // src0_modifiers
        GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/0, // src0
        GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/2, // clamp
        GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/3, // omod
        GIR_ConstrainSelectedInstOperands, /*InsnID*/0,
        GIR_EraseFromParent, /*InsnID*/0,
        // GIR_Coverage, 712,
        GIR_Done,
      // Label 793: @53368
      GIM_Reject,
    // Label 789: @53369
    GIM_Reject,
    // Label 786: @53370
    GIM_Try, /*On fail goto*//*Label 794*/ GIMT_Encode4(53459),
      GIM_CheckType, /*MI*/0, /*Op*/1, /*Type*/GILLT_s32,
      GIM_Try, /*On fail goto*//*Label 795*/ GIMT_Encode4(53408), // Rule ID 34 //
        GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasSALUFloatInsts),
        GIM_CheckRegBankForClass, /*MI*/0, /*Op*/0, /*RC*/GIMT_Encode2(AMDGPU::SReg_32RegClassID),
        GIM_CheckCxxInsnPredicate, /*MI*/0, /*FnId*/GIMT_Encode2(GICXXPred_MI_Predicate_anonymous_17600),
        // (ftrunc:{ *:[f32] } f32:{ *:[f32] }:$src0)<<P:Predicate_anonymous_17600>>  =>  (S_TRUNC_F32:{ *:[f32] } f32:{ *:[f32] }:$src0)
        GIR_MutateOpcode, /*InsnID*/0, /*RecycleInsnID*/0, /*Opcode*/GIMT_Encode2(AMDGPU::S_TRUNC_F32),
        GIR_AddImplicitUse, /*InsnID*/0, GIMT_Encode2(AMDGPU::MODE),
        GIR_ConstrainSelectedInstOperands, /*InsnID*/0,
        // GIR_Coverage, 34,
        GIR_Done,
      // Label 795: @53408
      GIM_Try, /*On fail goto*//*Label 796*/ GIMT_Encode4(53458), // Rule ID 601 //
        GIM_CheckRegBankForClass, /*MI*/0, /*Op*/0, /*RC*/GIMT_Encode2(AMDGPU::VGPR_32RegClassID),
        GIM_CheckComplexPattern, /*MI*/0, /*Op*/1, /*Renderer*/GIMT_Encode2(0), GIMT_Encode2(GICP_gi_vop3mods0),
        // (ftrunc:{ *:[f32] } (VOP3Mods0:{ *:[f32] } f32:{ *:[f32] }:$src0, i32:{ *:[i32] }:$src0_modifiers, i1:{ *:[i1] }:$clamp, i32:{ *:[i32] }:$omod))  =>  (V_TRUNC_F32_e64:{ *:[f32] } i32:{ *:[i32] }:$src0_modifiers, f32:{ *:[f32] }:$src0, i1:{ *:[i1] }:$clamp, i32:{ *:[i32] }:$omod)
        GIR_BuildMI, /*InsnID*/0, /*Opcode*/GIMT_Encode2(AMDGPU::V_TRUNC_F32_e64),
        GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/0, // DstI[vdst]
        GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/1, // src0_modifiers
        GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/0, // src0
        GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/2, // clamp
        GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/3, // omod
        GIR_ConstrainSelectedInstOperands, /*InsnID*/0,
        GIR_EraseFromParent, /*InsnID*/0,
        // GIR_Coverage, 601,
        GIR_Done,
      // Label 796: @53458
      GIM_Reject,
    // Label 794: @53459
    GIM_Reject,
    // Label 787: @53460
    GIM_Try, /*On fail goto*//*Label 797*/ GIMT_Encode4(53517), // Rule ID 645 //
      GIM_CheckFeatures, GIMT_Encode2(GIFBS_isGFX7Plus),
      GIM_CheckType, /*MI*/0, /*Op*/1, /*Type*/GILLT_s64,
      GIM_CheckRegBankForClass, /*MI*/0, /*Op*/0, /*RC*/GIMT_Encode2(AMDGPU::VReg_64RegClassID),
      GIM_CheckComplexPattern, /*MI*/0, /*Op*/1, /*Renderer*/GIMT_Encode2(0), GIMT_Encode2(GICP_gi_vop3mods0),
      // (ftrunc:{ *:[f64] } (VOP3Mods0:{ *:[f64] } f64:{ *:[f64] }:$src0, i32:{ *:[i32] }:$src0_modifiers, i1:{ *:[i1] }:$clamp, i32:{ *:[i32] }:$omod))  =>  (V_TRUNC_F64_e64:{ *:[f64] } i32:{ *:[i32] }:$src0_modifiers, f64:{ *:[f64] }:$src0, i1:{ *:[i1] }:$clamp, i32:{ *:[i32] }:$omod)
      GIR_BuildMI, /*InsnID*/0, /*Opcode*/GIMT_Encode2(AMDGPU::V_TRUNC_F64_e64),
      GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/0, // DstI[vdst]
      GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/1, // src0_modifiers
      GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/0, // src0
      GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/2, // clamp
      GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/3, // omod
      GIR_ConstrainSelectedInstOperands, /*InsnID*/0,
      GIR_EraseFromParent, /*InsnID*/0,
      // GIR_Coverage, 645,
      GIR_Done,
    // Label 797: @53517
    GIM_Reject,
    // Label 788: @53518
    GIM_Reject,
    // Label 10: @53519
    GIM_SwitchType, /*MI*/0, /*Op*/0, /*[*/GIMT_Encode2(8), GIMT_Encode2(11), /*)*//*default:*//*Label 801*/ GIMT_Encode4(53889),
    /*GILLT_s16*//*Label 798*/ GIMT_Encode4(53542),
    /*GILLT_s32*//*Label 799*/ GIMT_Encode4(53741),
    /*GILLT_s64*//*Label 800*/ GIMT_Encode4(53831),
    // Label 798: @53542
    GIM_Try, /*On fail goto*//*Label 802*/ GIMT_Encode4(53740),
      GIM_CheckType, /*MI*/0, /*Op*/1, /*Type*/GILLT_s16,
      GIM_Try, /*On fail goto*//*Label 803*/ GIMT_Encode4(53580), // Rule ID 40 //
        GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasSALUFloatInsts),
        GIM_CheckRegBankForClass, /*MI*/0, /*Op*/0, /*RC*/GIMT_Encode2(AMDGPU::SReg_32RegClassID),
        GIM_CheckCxxInsnPredicate, /*MI*/0, /*FnId*/GIMT_Encode2(GICXXPred_MI_Predicate_anonymous_17601),
        // (froundeven:{ *:[f16] } f16:{ *:[f16] }:$src0)<<P:Predicate_anonymous_17601>>  =>  (S_RNDNE_F16:{ *:[f16] } f16:{ *:[f16] }:$src0)
        GIR_MutateOpcode, /*InsnID*/0, /*RecycleInsnID*/0, /*Opcode*/GIMT_Encode2(AMDGPU::S_RNDNE_F16),
        GIR_AddImplicitUse, /*InsnID*/0, GIMT_Encode2(AMDGPU::MODE),
        GIR_ConstrainSelectedInstOperands, /*InsnID*/0,
        // GIR_Coverage, 40,
        GIR_Done,
      // Label 803: @53580
      GIM_Try, /*On fail goto*//*Label 804*/ GIMT_Encode4(53633), // Rule ID 713 //
        GIM_CheckFeatures, GIMT_Encode2(GIFBS_Has16BitInsts_NotHasTrue16BitInsts),
        GIM_CheckRegBankForClass, /*MI*/0, /*Op*/0, /*RC*/GIMT_Encode2(AMDGPU::VGPR_32RegClassID),
        GIM_CheckComplexPattern, /*MI*/0, /*Op*/1, /*Renderer*/GIMT_Encode2(0), GIMT_Encode2(GICP_gi_vop3mods0),
        // (froundeven:{ *:[f16] } (VOP3Mods0:{ *:[f16] } f16:{ *:[f16] }:$src0, i32:{ *:[i32] }:$src0_modifiers, i1:{ *:[i1] }:$clamp, i32:{ *:[i32] }:$omod))  =>  (V_RNDNE_F16_e64:{ *:[f16] } i32:{ *:[i32] }:$src0_modifiers, f16:{ *:[f16] }:$src0, i1:{ *:[i1] }:$clamp, i32:{ *:[i32] }:$omod)
        GIR_BuildMI, /*InsnID*/0, /*Opcode*/GIMT_Encode2(AMDGPU::V_RNDNE_F16_e64),
        GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/0, // DstI[vdst]
        GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/1, // src0_modifiers
        GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/0, // src0
        GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/2, // clamp
        GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/3, // omod
        GIR_ConstrainSelectedInstOperands, /*InsnID*/0,
        GIR_EraseFromParent, /*InsnID*/0,
        // GIR_Coverage, 713,
        GIR_Done,
      // Label 804: @53633
      GIM_Try, /*On fail goto*//*Label 805*/ GIMT_Encode4(53686), // Rule ID 714 //
        GIM_CheckFeatures, GIMT_Encode2(GIFBS_UseRealTrue16Insts),
        GIM_CheckRegBankForClass, /*MI*/0, /*Op*/0, /*RC*/GIMT_Encode2(AMDGPU::VGPR_16RegClassID),
        GIM_CheckComplexPattern, /*MI*/0, /*Op*/1, /*Renderer*/GIMT_Encode2(0), GIMT_Encode2(GICP_gi_vop3mods0),
        // (froundeven:{ *:[f16] } (VOP3Mods0:{ *:[f16] } f16:{ *:[f16] }:$src0, i32:{ *:[i32] }:$src0_modifiers, i1:{ *:[i1] }:$clamp, i32:{ *:[i32] }:$omod))  =>  (V_RNDNE_F16_t16_e64:{ *:[f16] } i32:{ *:[i32] }:$src0_modifiers, f16:{ *:[f16] }:$src0, i1:{ *:[i1] }:$clamp, i32:{ *:[i32] }:$omod)
        GIR_BuildMI, /*InsnID*/0, /*Opcode*/GIMT_Encode2(AMDGPU::V_RNDNE_F16_t16_e64),
        GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/0, // DstI[vdst]
        GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/1, // src0_modifiers
        GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/0, // src0
        GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/2, // clamp
        GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/3, // omod
        GIR_ConstrainSelectedInstOperands, /*InsnID*/0,
        GIR_EraseFromParent, /*InsnID*/0,
        // GIR_Coverage, 714,
        GIR_Done,
      // Label 805: @53686
      GIM_Try, /*On fail goto*//*Label 806*/ GIMT_Encode4(53739), // Rule ID 715 //
        GIM_CheckFeatures, GIMT_Encode2(GIFBS_UseFakeTrue16Insts),
        GIM_CheckRegBankForClass, /*MI*/0, /*Op*/0, /*RC*/GIMT_Encode2(AMDGPU::VGPR_32RegClassID),
        GIM_CheckComplexPattern, /*MI*/0, /*Op*/1, /*Renderer*/GIMT_Encode2(0), GIMT_Encode2(GICP_gi_vop3mods0),
        // (froundeven:{ *:[f16] } (VOP3Mods0:{ *:[f16] } f16:{ *:[f16] }:$src0, i32:{ *:[i32] }:$src0_modifiers, i1:{ *:[i1] }:$clamp, i32:{ *:[i32] }:$omod))  =>  (V_RNDNE_F16_fake16_e64:{ *:[f16] } i32:{ *:[i32] }:$src0_modifiers, f16:{ *:[f16] }:$src0, i1:{ *:[i1] }:$clamp, i32:{ *:[i32] }:$omod)
        GIR_BuildMI, /*InsnID*/0, /*Opcode*/GIMT_Encode2(AMDGPU::V_RNDNE_F16_fake16_e64),
        GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/0, // DstI[vdst]
        GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/1, // src0_modifiers
        GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/0, // src0
        GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/2, // clamp
        GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/3, // omod
        GIR_ConstrainSelectedInstOperands, /*InsnID*/0,
        GIR_EraseFromParent, /*InsnID*/0,
        // GIR_Coverage, 715,
        GIR_Done,
      // Label 806: @53739
      GIM_Reject,
    // Label 802: @53740
    GIM_Reject,
    // Label 799: @53741
    GIM_Try, /*On fail goto*//*Label 807*/ GIMT_Encode4(53830),
      GIM_CheckType, /*MI*/0, /*Op*/1, /*Type*/GILLT_s32,
      GIM_Try, /*On fail goto*//*Label 808*/ GIMT_Encode4(53779), // Rule ID 35 //
        GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasSALUFloatInsts),
        GIM_CheckRegBankForClass, /*MI*/0, /*Op*/0, /*RC*/GIMT_Encode2(AMDGPU::SReg_32RegClassID),
        GIM_CheckCxxInsnPredicate, /*MI*/0, /*FnId*/GIMT_Encode2(GICXXPred_MI_Predicate_anonymous_17601),
        // (froundeven:{ *:[f32] } f32:{ *:[f32] }:$src0)<<P:Predicate_anonymous_17601>>  =>  (S_RNDNE_F32:{ *:[f32] } f32:{ *:[f32] }:$src0)
        GIR_MutateOpcode, /*InsnID*/0, /*RecycleInsnID*/0, /*Opcode*/GIMT_Encode2(AMDGPU::S_RNDNE_F32),
        GIR_AddImplicitUse, /*InsnID*/0, GIMT_Encode2(AMDGPU::MODE),
        GIR_ConstrainSelectedInstOperands, /*InsnID*/0,
        // GIR_Coverage, 35,
        GIR_Done,
      // Label 808: @53779
      GIM_Try, /*On fail goto*//*Label 809*/ GIMT_Encode4(53829), // Rule ID 603 //
        GIM_CheckRegBankForClass, /*MI*/0, /*Op*/0, /*RC*/GIMT_Encode2(AMDGPU::VGPR_32RegClassID),
        GIM_CheckComplexPattern, /*MI*/0, /*Op*/1, /*Renderer*/GIMT_Encode2(0), GIMT_Encode2(GICP_gi_vop3mods0),
        // (froundeven:{ *:[f32] } (VOP3Mods0:{ *:[f32] } f32:{ *:[f32] }:$src0, i32:{ *:[i32] }:$src0_modifiers, i1:{ *:[i1] }:$clamp, i32:{ *:[i32] }:$omod))  =>  (V_RNDNE_F32_e64:{ *:[f32] } i32:{ *:[i32] }:$src0_modifiers, f32:{ *:[f32] }:$src0, i1:{ *:[i1] }:$clamp, i32:{ *:[i32] }:$omod)
        GIR_BuildMI, /*InsnID*/0, /*Opcode*/GIMT_Encode2(AMDGPU::V_RNDNE_F32_e64),
        GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/0, // DstI[vdst]
        GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/1, // src0_modifiers
        GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/0, // src0
        GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/2, // clamp
        GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/3, // omod
        GIR_ConstrainSelectedInstOperands, /*InsnID*/0,
        GIR_EraseFromParent, /*InsnID*/0,
        // GIR_Coverage, 603,
        GIR_Done,
      // Label 809: @53829
      GIM_Reject,
    // Label 807: @53830
    GIM_Reject,
    // Label 800: @53831
    GIM_Try, /*On fail goto*//*Label 810*/ GIMT_Encode4(53888), // Rule ID 647 //
      GIM_CheckFeatures, GIMT_Encode2(GIFBS_isGFX7Plus),
      GIM_CheckType, /*MI*/0, /*Op*/1, /*Type*/GILLT_s64,
      GIM_CheckRegBankForClass, /*MI*/0, /*Op*/0, /*RC*/GIMT_Encode2(AMDGPU::VReg_64RegClassID),
      GIM_CheckComplexPattern, /*MI*/0, /*Op*/1, /*Renderer*/GIMT_Encode2(0), GIMT_Encode2(GICP_gi_vop3mods0),
      // (froundeven:{ *:[f64] } (VOP3Mods0:{ *:[f64] } f64:{ *:[f64] }:$src0, i32:{ *:[i32] }:$src0_modifiers, i1:{ *:[i1] }:$clamp, i32:{ *:[i32] }:$omod))  =>  (V_RNDNE_F64_e64:{ *:[f64] } i32:{ *:[i32] }:$src0_modifiers, f64:{ *:[f64] }:$src0, i1:{ *:[i1] }:$clamp, i32:{ *:[i32] }:$omod)
      GIR_BuildMI, /*InsnID*/0, /*Opcode*/GIMT_Encode2(AMDGPU::V_RNDNE_F64_e64),
      GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/0, // DstI[vdst]
      GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/1, // src0_modifiers
      GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/0, // src0
      GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/2, // clamp
      GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/3, // omod
      GIR_ConstrainSelectedInstOperands, /*InsnID*/0,
      GIR_EraseFromParent, /*InsnID*/0,
      // GIR_Coverage, 647,
      GIR_Done,
    // Label 810: @53888
    GIM_Reject,
    // Label 801: @53889
    GIM_Reject,
    // Label 11: @53890
    GIM_Try, /*On fail goto*//*Label 811*/ GIMT_Encode4(54041),
      GIM_CheckType, /*MI*/0, /*Op*/0, /*Type*/GILLT_s64,
      GIM_Try, /*On fail goto*//*Label 812*/ GIMT_Encode4(54019),
        GIM_CheckRegBankForClass, /*MI*/0, /*Op*/0, /*RC*/GIMT_Encode2(AMDGPU::SReg_64RegClassID),
        GIM_Try, /*On fail goto*//*Label 813*/ GIMT_Encode4(53996), // Rule ID 2738 //
          GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasShaderCyclesRegister),
          // (readcyclecounter:{ *:[i64] })  =>  (REG_SEQUENCE:{ *:[i64] } SReg_64:{ *:[i32] }, (S_GETREG_B32:{ *:[i1] } 38941:{ *:[i32] }), sub0:{ *:[i32] }, (S_MOV_B32:{ *:[i1] } 0:{ *:[i32] }), sub1:{ *:[i32] })
          GIR_MakeTempReg, /*TempRegID*/0, /*TypeID*/GILLT_s1,
          GIR_MakeTempReg, /*TempRegID*/1, /*TypeID*/GILLT_s1,
          GIR_BuildMI, /*InsnID*/2, /*Opcode*/GIMT_Encode2(AMDGPU::S_MOV_B32),
          GIR_AddTempRegister, /*InsnID*/2, /*TempRegID*/1, /*TempRegFlags*/GIMT_Encode2(RegState::Define),
          GIR_AddImm8, /*InsnID*/2, /*Imm*/0,
          GIR_ConstrainSelectedInstOperands, /*InsnID*/2,
          GIR_BuildMI, /*InsnID*/1, /*Opcode*/GIMT_Encode2(AMDGPU::S_GETREG_B32),
          GIR_AddTempRegister, /*InsnID*/1, /*TempRegID*/0, /*TempRegFlags*/GIMT_Encode2(RegState::Define),
          GIR_AddImm, /*InsnID*/1, /*Imm*/GIMT_Encode8(38941),
          GIR_ConstrainSelectedInstOperands, /*InsnID*/1,
          GIR_BuildMI, /*InsnID*/0, /*Opcode*/GIMT_Encode2(TargetOpcode::REG_SEQUENCE),
          GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/0, // DstI[dst]
          GIR_AddSimpleTempRegister, /*InsnID*/0, /*TempRegID*/0,
          GIR_AddImm8, /*InsnID*/0, /*SubRegIndex*/3,
          GIR_AddSimpleTempRegister, /*InsnID*/0, /*TempRegID*/1,
          GIR_AddImm8, /*InsnID*/0, /*SubRegIndex*/11,
          GIR_ConstrainOperandRC, /*InsnID*/0, /*Op*/0, GIMT_Encode2(AMDGPU::SReg_64RegClassID),
          GIR_ConstrainOperandRC, /*InsnID*/0, /*Op*/1, GIMT_Encode2(AMDGPU::SReg_32_XEXEC_HI_and_SReg_32_XM0RegClassID),
          GIR_ConstrainOperandRC, /*InsnID*/0, /*Op*/3, GIMT_Encode2(AMDGPU::SReg_32_XM0RegClassID),
          GIR_EraseFromParent, /*InsnID*/0,
          // GIR_Coverage, 2738,
          GIR_Done,
        // Label 813: @53996
        GIM_Try, /*On fail goto*//*Label 814*/ GIMT_Encode4(54018), // Rule ID 1120 //
          GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasShaderCyclesHiLoRegisters),
          // (readcyclecounter:{ *:[i64] })  =>  (GET_SHADERCYCLESHILO:{ *:[i64] }:{ *:[i1] })
          GIR_MutateOpcode, /*InsnID*/0, /*RecycleInsnID*/0, /*Opcode*/GIMT_Encode2(AMDGPU::GET_SHADERCYCLESHILO),
          GIR_AddImplicitDef, /*InsnID*/0, GIMT_Encode2(AMDGPU::SCC), GIMT_Encode2(RegState::Dead),
          GIR_ConstrainSelectedInstOperands, /*InsnID*/0,
          // GIR_Coverage, 1120,
          GIR_Done,
        // Label 814: @54018
        GIM_Reject,
      // Label 812: @54019
      GIM_Try, /*On fail goto*//*Label 815*/ GIMT_Encode4(54040), // Rule ID 2737 //
        GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasSMemTimeInst),
        GIM_CheckRegBankForClass, /*MI*/0, /*Op*/0, /*RC*/GIMT_Encode2(AMDGPU::SReg_64_XEXECRegClassID),
        // (readcyclecounter:{ *:[i64] })  =>  (S_MEMTIME:{ *:[i64] })
        GIR_MutateOpcode, /*InsnID*/0, /*RecycleInsnID*/0, /*Opcode*/GIMT_Encode2(AMDGPU::S_MEMTIME),
        GIR_ConstrainSelectedInstOperands, /*InsnID*/0,
        // GIR_Coverage, 2737,
        GIR_Done,
      // Label 815: @54040
      GIM_Reject,
    // Label 811: @54041
    GIM_Reject,
    // Label 12: @54042
    GIM_SwitchType, /*MI*/0, /*Op*/0, /*[*/GIMT_Encode2(0), GIMT_Encode2(33), /*)*//*default:*//*Label 840*/ GIMT_Encode4(109904),
    /*GILLT_p0s64*//*Label 816*/ GIMT_Encode4(54185),
    /*GILLT_p1s64*//*Label 817*/ GIMT_Encode4(55674),
    /*GILLT_p2s32*//*Label 818*/ GIMT_Encode4(57163),
    /*GILLT_p3s32*//*Label 819*/ GIMT_Encode4(58650),
    /*GILLT_p4s64*//*Label 820*/ GIMT_Encode4(60137),
    /*GILLT_p5s32*//*Label 821*/ GIMT_Encode4(61626),
    /*GILLT_p6s32*//*Label 822*/ GIMT_Encode4(63113),
    /*GILLT_s1*//*Label 823*/ GIMT_Encode4(64600),
    /*GILLT_s16*//*Label 824*/ GIMT_Encode4(64914),
    /*GILLT_s32*//*Label 825*/ GIMT_Encode4(68485),
    /*GILLT_s64*//*Label 826*/ GIMT_Encode4(76551),
    /*GILLT_v2s16*//*Label 827*/ GIMT_Encode4(80356),
    /*GILLT_v2s32*//*Label 828*/ GIMT_Encode4(84815),
    /*GILLT_v2s64*//*Label 829*/ GIMT_Encode4(88082),
    /*GILLT_v3s32*//*Label 830*/ GIMT_Encode4(91059), GIMT_Encode4(0),
    /*GILLT_v4s16*//*Label 831*/ GIMT_Encode4(93495),
    /*GILLT_v4s32*//*Label 832*/ GIMT_Encode4(97960),
    /*GILLT_v4s64*//*Label 833*/ GIMT_Encode4(101227), GIMT_Encode4(0), GIMT_Encode4(0), GIMT_Encode4(0),
    /*GILLT_v8s16*//*Label 834*/ GIMT_Encode4(101832),
    /*GILLT_v8s32*//*Label 835*/ GIMT_Encode4(106297),
    /*GILLT_v8s64*//*Label 836*/ GIMT_Encode4(106902), GIMT_Encode4(0), GIMT_Encode4(0), GIMT_Encode4(0), GIMT_Encode4(0),
    /*GILLT_v16s16*//*Label 837*/ GIMT_Encode4(107507),
    /*GILLT_v16s32*//*Label 838*/ GIMT_Encode4(108403), GIMT_Encode4(0),
    /*GILLT_v32s16*//*Label 839*/ GIMT_Encode4(109008),
    // Label 816: @54185
    GIM_Try, /*On fail goto*//*Label 841*/ GIMT_Encode4(54260), // Rule ID 6843 //
      GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasUnalignedAccessMode_LDSRequiresM0Init),
      GIM_CheckMemorySizeEqualToLLT, /*MI*/0, /*MMO*/0, /*OpIdx*/0,
      GIM_CheckMemoryAddressSpace, /*MI*/0, /*MMO*/0, /*NumAddrSpace*/1, /*AddrSpace*/3,
      GIM_CheckMemoryAddressSpace, /*MI*/0, /*MMO*/0, /*NumAddrSpace*/1, /*AddrSpace*/3,
      GIM_CheckAtomicOrdering, /*MI*/0, /*Order*/(uint8_t)AtomicOrdering::NotAtomic,
      GIM_CheckRegBankForClass, /*MI*/0, /*Op*/0, /*RC*/GIMT_Encode2(AMDGPU::AV_64RegClassID),
      GIM_CheckPointerToAny, /*MI*/0, /*Op*/1, /*SizeInBits*/0,
      GIM_CheckCxxInsnPredicate, /*MI*/0, /*FnId*/GIMT_Encode2(GICXXPred_MI_Predicate_load_align_less_than_4_local_m0),
      GIM_CheckComplexPattern, /*MI*/0, /*Op*/1, /*Renderer*/GIMT_Encode2(0), GIMT_Encode2(GICP_gi_ds_1addr_1offset),
      // (AMDGPUld_glue:{ *:[i64] } (DS1Addr1Offset:{ *:[iPTR] } i32:{ *:[i32] }:$ptr, i32:{ *:[i32] }:$offset))<<P:Predicate_unindexedload_glue>><<P:Predicate_load_glue>><<P:Predicate_load_local_m0>><<P:Predicate_load_align_less_than_4_local_m0>>  =>  (DS_READ_B64:{ *:[i64] } ?:{ *:[i32] }:$ptr, offset:{ *:[i32] }:$offset, 0:{ *:[i1] })
      GIR_BuildMI, /*InsnID*/0, /*Opcode*/GIMT_Encode2(AMDGPU::DS_READ_B64),
      GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/0, // DstI[vdst]
      GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/0, // ptr
      GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/1, // offset
      GIR_AddImm8, /*InsnID*/0, /*Imm*/0,
      GIR_MergeMemOperands, /*InsnID*/0, /*NumInsns*/1, /*MergeInsnID's*/0,
      GIR_ConstrainSelectedInstOperands, /*InsnID*/0,
      GIR_EraseFromParent, /*InsnID*/0,
      // GIR_Coverage, 6843,
      GIR_Done,
    // Label 841: @54260
    GIM_Try, /*On fail goto*//*Label 842*/ GIMT_Encode4(54330), // Rule ID 6767 //
      GIM_CheckFeatures, GIMT_Encode2(GIFBS_LDSRequiresM0Init),
      GIM_CheckMemorySizeEqualToLLT, /*MI*/0, /*MMO*/0, /*OpIdx*/0,
      GIM_CheckMemoryAddressSpace, /*MI*/0, /*MMO*/0, /*NumAddrSpace*/1, /*AddrSpace*/3,
      GIM_CheckMemoryAlignment, /*MI*/0, /*MMO*/0, /*MinAlign*/8,
      GIM_CheckAtomicOrdering, /*MI*/0, /*Order*/(uint8_t)AtomicOrdering::NotAtomic,
      GIM_CheckRegBankForClass, /*MI*/0, /*Op*/0, /*RC*/GIMT_Encode2(AMDGPU::AV_64RegClassID),
      GIM_CheckPointerToAny, /*MI*/0, /*Op*/1, /*SizeInBits*/0,
      GIM_CheckComplexPattern, /*MI*/0, /*Op*/1, /*Renderer*/GIMT_Encode2(0), GIMT_Encode2(GICP_gi_ds_1addr_1offset),
      // (AMDGPUld_glue:{ *:[i64] } (DS1Addr1Offset:{ *:[iPTR] } i32:{ *:[i32] }:$ptr, i32:{ *:[i32] }:$offset))<<P:Predicate_unindexedload_glue>><<P:Predicate_load_glue>><<P:Predicate_load_local_m0>><<P:Predicate_load_align8_local_m0>>  =>  (DS_READ_B64:{ *:[i64] } ?:{ *:[i32] }:$ptr, offset:{ *:[i32] }:$offset, 0:{ *:[i1] })
      GIR_BuildMI, /*InsnID*/0, /*Opcode*/GIMT_Encode2(AMDGPU::DS_READ_B64),
      GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/0, // DstI[vdst]
      GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/0, // ptr
      GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/1, // offset
      GIR_AddImm8, /*InsnID*/0, /*Imm*/0,
      GIR_MergeMemOperands, /*InsnID*/0, /*NumInsns*/1, /*MergeInsnID's*/0,
      GIR_ConstrainSelectedInstOperands, /*InsnID*/0,
      GIR_EraseFromParent, /*InsnID*/0,
      // GIR_Coverage, 6767,
      GIR_Done,
    // Label 842: @54330
    GIM_Try, /*On fail goto*//*Label 843*/ GIMT_Encode4(54401), // Rule ID 6844 //
      GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasUnalignedAccessMode_NotLDSRequiresM0Init),
      GIM_CheckMemoryAddressSpace, /*MI*/0, /*MMO*/0, /*NumAddrSpace*/1, /*AddrSpace*/3,
      GIM_CheckMemoryAddressSpace, /*MI*/0, /*MMO*/0, /*NumAddrSpace*/1, /*AddrSpace*/3,
      GIM_CheckAtomicOrdering, /*MI*/0, /*Order*/(uint8_t)AtomicOrdering::NotAtomic,
      GIM_CheckRegBankForClass, /*MI*/0, /*Op*/0, /*RC*/GIMT_Encode2(AMDGPU::AV_64RegClassID),
      GIM_CheckPointerToAny, /*MI*/0, /*Op*/1, /*SizeInBits*/0,
      GIM_CheckCxxInsnPredicate, /*MI*/0, /*FnId*/GIMT_Encode2(GICXXPred_MI_Predicate_load_align_less_than_4_local),
      GIM_CheckComplexPattern, /*MI*/0, /*Op*/1, /*Renderer*/GIMT_Encode2(0), GIMT_Encode2(GICP_gi_ds_1addr_1offset),
      // (ld:{ *:[i64] } (DS1Addr1Offset:{ *:[iPTR] } i32:{ *:[i32] }:$ptr, i32:{ *:[i32] }:$offset))<<P:Predicate_unindexedload>><<P:Predicate_load_local>><<P:Predicate_load_align_less_than_4_local>>  =>  (DS_READ_B64_gfx9:{ *:[i64] } ?:{ *:[i32] }:$ptr, offset:{ *:[i32] }:$offset, 0:{ *:[i1] })
      GIR_BuildMI, /*InsnID*/0, /*Opcode*/GIMT_Encode2(AMDGPU::DS_READ_B64_gfx9),
      GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/0, // DstI[vdst]
      GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/0, // ptr
      GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/1, // offset
      GIR_AddImm8, /*InsnID*/0, /*Imm*/0,
      GIR_MergeMemOperands, /*InsnID*/0, /*NumInsns*/1, /*MergeInsnID's*/0,
      GIR_ConstrainSelectedInstOperands, /*InsnID*/0,
      GIR_EraseFromParent, /*InsnID*/0,
      // GIR_Coverage, 6844,
      GIR_Done,
    // Label 843: @54401
    GIM_Try, /*On fail goto*//*Label 844*/ GIMT_Encode4(54467), // Rule ID 6768 //
      GIM_CheckFeatures, GIMT_Encode2(GIFBS_NotLDSRequiresM0Init),
      GIM_CheckMemoryAddressSpace, /*MI*/0, /*MMO*/0, /*NumAddrSpace*/1, /*AddrSpace*/3,
      GIM_CheckMemoryAlignment, /*MI*/0, /*MMO*/0, /*MinAlign*/8,
      GIM_CheckAtomicOrdering, /*MI*/0, /*Order*/(uint8_t)AtomicOrdering::NotAtomic,
      GIM_CheckRegBankForClass, /*MI*/0, /*Op*/0, /*RC*/GIMT_Encode2(AMDGPU::AV_64RegClassID),
      GIM_CheckPointerToAny, /*MI*/0, /*Op*/1, /*SizeInBits*/0,
      GIM_CheckComplexPattern, /*MI*/0, /*Op*/1, /*Renderer*/GIMT_Encode2(0), GIMT_Encode2(GICP_gi_ds_1addr_1offset),
      // (ld:{ *:[i64] } (DS1Addr1Offset:{ *:[iPTR] } i32:{ *:[i32] }:$ptr, i32:{ *:[i32] }:$offset))<<P:Predicate_unindexedload>><<P:Predicate_load_local>><<P:Predicate_load_align8_local>>  =>  (DS_READ_B64_gfx9:{ *:[i64] } ?:{ *:[i32] }:$ptr, offset:{ *:[i32] }:$offset, 0:{ *:[i1] })
      GIR_BuildMI, /*InsnID*/0, /*Opcode*/GIMT_Encode2(AMDGPU::DS_READ_B64_gfx9),
      GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/0, // DstI[vdst]
      GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/0, // ptr
      GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/1, // offset
      GIR_AddImm8, /*InsnID*/0, /*Imm*/0,
      GIR_MergeMemOperands, /*InsnID*/0, /*NumInsns*/1, /*MergeInsnID's*/0,
      GIR_ConstrainSelectedInstOperands, /*InsnID*/0,
      GIR_EraseFromParent, /*InsnID*/0,
      // GIR_Coverage, 6768,
      GIR_Done,
    // Label 844: @54467
    GIM_Try, /*On fail goto*//*Label 845*/ GIMT_Encode4(54534), // Rule ID 3526 //
      GIM_CheckFeatures, GIMT_Encode2(GIFBS_EnableFlatScratch_HasFlatScratchInsts_HasFlatScratchSVSMode),
      GIM_CheckMemoryAddressSpace, /*MI*/0, /*MMO*/0, /*NumAddrSpace*/1, /*AddrSpace*/5,
      GIM_CheckAtomicOrdering, /*MI*/0, /*Order*/(uint8_t)AtomicOrdering::NotAtomic,
      GIM_CheckRegBankForClass, /*MI*/0, /*Op*/0, /*RC*/GIMT_Encode2(AMDGPU::AV_64RegClassID),
      GIM_CheckPointerToAny, /*MI*/0, /*Op*/1, /*SizeInBits*/0,
      GIM_CheckComplexPattern, /*MI*/0, /*Op*/1, /*Renderer*/GIMT_Encode2(0), GIMT_Encode2(GICP_gi_flat_scratch_svaddr),
      // (ld:{ *:[i64] } (ScratchSVAddr:{ *:[iPTR] } VGPR_32:{ *:[i32] }:$vaddr, SGPR_32:{ *:[i32] }:$saddr, i32:{ *:[i32] }:$offset))<<P:Predicate_unindexedload>><<P:Predicate_load_private>>  =>  (SCRATCH_LOAD_DWORDX2_SVS:{ *:[i64] } ?:{ *:[i32] }:$vaddr, ?:{ *:[i32] }:$saddr, ?:{ *:[i32] }:$offset, 0:{ *:[i32] })
      GIR_BuildMI, /*InsnID*/0, /*Opcode*/GIMT_Encode2(AMDGPU::SCRATCH_LOAD_DWORDX2_SVS),
      GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/0, // DstI[vdst]
      GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/0, // vaddr
      GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/1, // saddr
      GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/2, // offset
      GIR_AddImm8, /*InsnID*/0, /*Imm*/0,
      GIR_MergeMemOperands, /*InsnID*/0, /*NumInsns*/1, /*MergeInsnID's*/0,
      GIR_ConstrainSelectedInstOperands, /*InsnID*/0,
      GIR_EraseFromParent, /*InsnID*/0,
      // GIR_Coverage, 3526,
      GIR_Done,
    // Label 845: @54534
    GIM_Try, /*On fail goto*//*Label 846*/ GIMT_Encode4(54596), // Rule ID 3525 //
      GIM_CheckFeatures, GIMT_Encode2(GIFBS_EnableFlatScratch_HasFlatScratchInsts),
      GIM_CheckMemoryAddressSpace, /*MI*/0, /*MMO*/0, /*NumAddrSpace*/1, /*AddrSpace*/5,
      GIM_CheckAtomicOrdering, /*MI*/0, /*Order*/(uint8_t)AtomicOrdering::NotAtomic,
      GIM_CheckRegBankForClass, /*MI*/0, /*Op*/0, /*RC*/GIMT_Encode2(AMDGPU::AV_64RegClassID),
      GIM_CheckPointerToAny, /*MI*/0, /*Op*/1, /*SizeInBits*/0,
      GIM_CheckComplexPattern, /*MI*/0, /*Op*/1, /*Renderer*/GIMT_Encode2(0), GIMT_Encode2(GICP_gi_flat_scratch_saddr),
      // (ld:{ *:[i64] } (ScratchSAddr:{ *:[iPTR] } SGPR_32:{ *:[i32] }:$saddr, i32:{ *:[i32] }:$offset))<<P:Predicate_unindexedload>><<P:Predicate_load_private>>  =>  (SCRATCH_LOAD_DWORDX2_SADDR:{ *:[i64] } ?:{ *:[i32] }:$saddr, ?:{ *:[i32] }:$offset)
      GIR_BuildMI, /*InsnID*/0, /*Opcode*/GIMT_Encode2(AMDGPU::SCRATCH_LOAD_DWORDX2_SADDR),
      GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/0, // DstI[vdst]
      GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/0, // saddr
      GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/1, // offset
      GIR_AddImm8, /*InsnID*/0, /*Imm*/0,
      GIR_MergeMemOperands, /*InsnID*/0, /*NumInsns*/1, /*MergeInsnID's*/0,
      GIR_ConstrainSelectedInstOperands, /*InsnID*/0,
      GIR_EraseFromParent, /*InsnID*/0,
      // GIR_Coverage, 3525,
      GIR_Done,
    // Label 846: @54596
    GIM_Try, /*On fail goto*//*Label 847*/ GIMT_Encode4(54658), // Rule ID 3524 //
      GIM_CheckFeatures, GIMT_Encode2(GIFBS_EnableFlatScratch_HasFlatScratchInsts),
      GIM_CheckMemoryAddressSpace, /*MI*/0, /*MMO*/0, /*NumAddrSpace*/1, /*AddrSpace*/5,
      GIM_CheckAtomicOrdering, /*MI*/0, /*Order*/(uint8_t)AtomicOrdering::NotAtomic,
      GIM_CheckRegBankForClass, /*MI*/0, /*Op*/0, /*RC*/GIMT_Encode2(AMDGPU::AV_64RegClassID),
      GIM_CheckPointerToAny, /*MI*/0, /*Op*/1, /*SizeInBits*/0,
      GIM_CheckComplexPattern, /*MI*/0, /*Op*/1, /*Renderer*/GIMT_Encode2(0), GIMT_Encode2(GICP_gi_flat_scratch_offset),
      // (ld:{ *:[i64] } (ScratchOffset:{ *:[iPTR] } VGPR_32:{ *:[i32] }:$vaddr, i32:{ *:[i32] }:$offset))<<P:Predicate_unindexedload>><<P:Predicate_load_private>>  =>  (SCRATCH_LOAD_DWORDX2:{ *:[i64] } ?:{ *:[i32] }:$vaddr, ?:{ *:[i32] }:$offset)
      GIR_BuildMI, /*InsnID*/0, /*Opcode*/GIMT_Encode2(AMDGPU::SCRATCH_LOAD_DWORDX2),
      GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/0, // DstI[vdst]
      GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/0, // vaddr
      GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/1, // offset
      GIR_AddImm8, /*InsnID*/0, /*Imm*/0,
      GIR_MergeMemOperands, /*InsnID*/0, /*NumInsns*/1, /*MergeInsnID's*/0,
      GIR_ConstrainSelectedInstOperands, /*InsnID*/0,
      GIR_EraseFromParent, /*InsnID*/0,
      // GIR_Coverage, 3524,
      GIR_Done,
    // Label 847: @54658
    GIM_Try, /*On fail goto*//*Label 848*/ GIMT_Encode4(54735), // Rule ID 3748 //
      GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasUnrestrictedSOffset),
      GIM_CheckMemoryAddressSpace, /*MI*/0, /*MMO*/0, /*NumAddrSpace*/3, /*AddrSpace*/1, /*AddrSpace*/4, /*AddrSpace*/6,
      GIM_CheckAtomicOrdering, /*MI*/0, /*Order*/(uint8_t)AtomicOrdering::NotAtomic,
      GIM_CheckRegBankForClass, /*MI*/0, /*Op*/0, /*RC*/GIMT_Encode2(AMDGPU::AV_64RegClassID),
      GIM_CheckPointerToAny, /*MI*/0, /*Op*/1, /*SizeInBits*/0,
      GIM_CheckComplexPattern, /*MI*/0, /*Op*/1, /*Renderer*/GIMT_Encode2(0), GIMT_Encode2(GICP_gi_mubuf_addr64),
      // (ld:{ *:[i64] } (MUBUFAddr64:{ *:[iPTR] } v4i32:{ *:[v4i32] }:$srsrc, i64:{ *:[i64] }:$vaddr, i32:{ *:[i32] }:$soffset, i32:{ *:[i32] }:$offset))<<P:Predicate_unindexedload>><<P:Predicate_load_global>>  =>  (BUFFER_LOAD_DWORDX2_ADDR64:{ *:[i64] } i64:{ *:[i64] }:$vaddr, v4i32:{ *:[v4i32] }:$srsrc, i32:{ *:[i32] }:$soffset, i32:{ *:[i32] }:$offset)
      GIR_BuildMI, /*InsnID*/0, /*Opcode*/GIMT_Encode2(AMDGPU::BUFFER_LOAD_DWORDX2_ADDR64),
      GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/0, // DstI[vdata]
      GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/1, // vaddr
      GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/0, // srsrc
      GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/2, // soffset
      GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/3, // offset
      GIR_AddImm8, /*InsnID*/0, /*Imm*/0,
      GIR_AddImm8, /*InsnID*/0, /*Imm*/0,
      GIR_MergeMemOperands, /*InsnID*/0, /*NumInsns*/1, /*MergeInsnID's*/0,
      GIR_ConstrainSelectedInstOperands, /*InsnID*/0,
      GIR_EraseFromParent, /*InsnID*/0,
      // GIR_Coverage, 3748,
      GIR_Done,
    // Label 848: @54735
    GIM_Try, /*On fail goto*//*Label 849*/ GIMT_Encode4(54809), // Rule ID 3750 //
      GIM_CheckMemoryAddressSpace, /*MI*/0, /*MMO*/0, /*NumAddrSpace*/3, /*AddrSpace*/1, /*AddrSpace*/4, /*AddrSpace*/6,
      GIM_CheckAtomicOrdering, /*MI*/0, /*Order*/(uint8_t)AtomicOrdering::NotAtomic,
      GIM_CheckRegBankForClass, /*MI*/0, /*Op*/0, /*RC*/GIMT_Encode2(AMDGPU::AV_64RegClassID),
      GIM_CheckPointerToAny, /*MI*/0, /*Op*/1, /*SizeInBits*/0,
      GIM_CheckComplexPattern, /*MI*/0, /*Op*/1, /*Renderer*/GIMT_Encode2(0), GIMT_Encode2(GICP_gi_mubuf_addr64),
      // (ld:{ *:[i64] } (MUBUFAddr64:{ *:[iPTR] } v4i32:{ *:[v4i32] }:$srsrc, i64:{ *:[i64] }:$vaddr, i32:{ *:[i32] }:$soffset, i32:{ *:[i32] }:$offset))<<P:Predicate_unindexedload>><<P:Predicate_load_global>>  =>  (BUFFER_LOAD_DWORDX2_VBUFFER_ADDR64:{ *:[i64] } i64:{ *:[i64] }:$vaddr, v4i32:{ *:[v4i32] }:$srsrc, i32:{ *:[i32] }:$soffset, i32:{ *:[i32] }:$offset)
      GIR_BuildMI, /*InsnID*/0, /*Opcode*/GIMT_Encode2(AMDGPU::BUFFER_LOAD_DWORDX2_VBUFFER_ADDR64),
      GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/0, // DstI[vdata]
      GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/1, // vaddr
      GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/0, // srsrc
      GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/2, // soffset
      GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/3, // offset
      GIR_AddImm8, /*InsnID*/0, /*Imm*/0,
      GIR_AddImm8, /*InsnID*/0, /*Imm*/0,
      GIR_MergeMemOperands, /*InsnID*/0, /*NumInsns*/1, /*MergeInsnID's*/0,
      GIR_ConstrainSelectedInstOperands, /*InsnID*/0,
      GIR_EraseFromParent, /*InsnID*/0,
      // GIR_Coverage, 3750,
      GIR_Done,
    // Label 849: @54809
    GIM_Try, /*On fail goto*//*Label 850*/ GIMT_Encode4(54880), // Rule ID 6703 //
      GIM_CheckFeatures, GIMT_Encode2(GIFBS_LDSRequiresM0Init_isGFX7Plus),
      GIM_CheckMemorySizeEqualToLLT, /*MI*/0, /*MMO*/0, /*OpIdx*/0,
      GIM_CheckMemoryAddressSpace, /*MI*/0, /*MMO*/0, /*NumAddrSpace*/1, /*AddrSpace*/3,
      GIM_CheckAtomicOrdering, /*MI*/0, /*Order*/(uint8_t)AtomicOrdering::NotAtomic,
      GIM_CheckRegBankForClass, /*MI*/0, /*Op*/0, /*RC*/GIMT_Encode2(AMDGPU::AV_64RegClassID),
      GIM_CheckPointerToAny, /*MI*/0, /*Op*/1, /*SizeInBits*/0,
      GIM_CheckComplexPattern, /*MI*/0, /*Op*/1, /*Renderer*/GIMT_Encode2(0), GIMT_Encode2(GICP_gi_ds_64bit_4byte_aligned),
      // (AMDGPUld_glue:{ *:[i64] } (DS64Bit4ByteAligned:{ *:[iPTR] } i32:{ *:[i32] }:$ptr, i8:{ *:[i8] }:$offset0, i8:{ *:[i8] }:$offset1))<<P:Predicate_unindexedload_glue>><<P:Predicate_load_glue>><<P:Predicate_load_local_m0>>  =>  (DS_READ2_B32:{ *:[i64] } ?:{ *:[i32] }:$ptr, ?:{ *:[i8] }:$offset0, ?:{ *:[i8] }:$offset1, 0:{ *:[i1] })
      GIR_BuildMI, /*InsnID*/0, /*Opcode*/GIMT_Encode2(AMDGPU::DS_READ2_B32),
      GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/0, // DstI[vdst]
      GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/0, // ptr
      GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/1, // offset0
      GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/2, // offset1
      GIR_AddImm8, /*InsnID*/0, /*Imm*/0,
      GIR_MergeMemOperands, /*InsnID*/0, /*NumInsns*/1, /*MergeInsnID's*/0,
      GIR_ConstrainSelectedInstOperands, /*InsnID*/0,
      GIR_EraseFromParent, /*InsnID*/0,
      // GIR_Coverage, 6703,
      GIR_Done,
    // Label 850: @54880
    GIM_Try, /*On fail goto*//*Label 851*/ GIMT_Encode4(54950), // Rule ID 7102 //
      GIM_CheckFeatures, GIMT_Encode2(GIFBS_isGFX9Plus),
      GIM_CheckMemorySizeEqualToLLT, /*MI*/0, /*MMO*/0, /*OpIdx*/0,
      GIM_CheckAtomicOrdering, /*MI*/0, /*Order*/(uint8_t)AtomicOrdering::NotAtomic,
      GIM_CheckRegBankForClass, /*MI*/0, /*Op*/0, /*RC*/GIMT_Encode2(AMDGPU::SReg_64_XEXECRegClassID),
      GIM_CheckPointerToAny, /*MI*/0, /*Op*/1, /*SizeInBits*/0,
      GIM_CheckCxxInsnPredicate, /*MI*/0, /*FnId*/GIMT_Encode2(GICXXPred_MI_Predicate_smrd_load),
      GIM_CheckComplexPattern, /*MI*/0, /*Op*/1, /*Renderer*/GIMT_Encode2(0), GIMT_Encode2(GICP_gi_smrd_sgpr_imm),
      // (ld:{ *:[i64] } (SMRDSgprImm:{ *:[iPTR] } i64:{ *:[i64] }:$sbase, i32:{ *:[i32] }:$soffset, i32:{ *:[i32] }:$offset))<<P:Predicate_unindexedload>><<P:Predicate_load>><<P:Predicate_smrd_load>>  =>  (S_LOAD_DWORDX2_SGPR_IMM:{ *:[i64] } ?:{ *:[i64] }:$sbase, ?:{ *:[i32] }:$soffset, ?:{ *:[i32] }:$offset, 0:{ *:[i32] })
      GIR_BuildMI, /*InsnID*/0, /*Opcode*/GIMT_Encode2(AMDGPU::S_LOAD_DWORDX2_SGPR_IMM),
      GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/0, // DstI[sdst]
      GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/0, // sbase
      GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/1, // soffset
      GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/2, // offset
      GIR_AddImm8, /*InsnID*/0, /*Imm*/0,
      GIR_MergeMemOperands, /*InsnID*/0, /*NumInsns*/1, /*MergeInsnID's*/0,
      GIR_ConstrainSelectedInstOperands, /*InsnID*/0,
      GIR_EraseFromParent, /*InsnID*/0,
      // GIR_Coverage, 7102,
      GIR_Done,
    // Label 851: @54950
    GIM_Try, /*On fail goto*//*Label 852*/ GIMT_Encode4(55022), // Rule ID 3747 //
      GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasUnrestrictedSOffset),
      GIM_CheckMemoryAddressSpace, /*MI*/0, /*MMO*/0, /*NumAddrSpace*/3, /*AddrSpace*/1, /*AddrSpace*/4, /*AddrSpace*/6,
      GIM_CheckAtomicOrdering, /*MI*/0, /*Order*/(uint8_t)AtomicOrdering::NotAtomic,
      GIM_CheckRegBankForClass, /*MI*/0, /*Op*/0, /*RC*/GIMT_Encode2(AMDGPU::AV_64RegClassID),
      GIM_CheckPointerToAny, /*MI*/0, /*Op*/1, /*SizeInBits*/0,
      GIM_CheckComplexPattern, /*MI*/0, /*Op*/1, /*Renderer*/GIMT_Encode2(0), GIMT_Encode2(GICP_gi_mubuf_offset),
      // (ld:{ *:[i64] } (MUBUFOffset:{ *:[iPTR] } v4i32:{ *:[v4i32] }:$srsrc, i32:{ *:[i32] }:$soffset, i32:{ *:[i32] }:$offset))<<P:Predicate_unindexedload>><<P:Predicate_load_global>>  =>  (BUFFER_LOAD_DWORDX2_OFFSET:{ *:[i64] } v4i32:{ *:[v4i32] }:$srsrc, i32:{ *:[i32] }:$soffset, i32:{ *:[i32] }:$offset)
      GIR_BuildMI, /*InsnID*/0, /*Opcode*/GIMT_Encode2(AMDGPU::BUFFER_LOAD_DWORDX2_OFFSET),
      GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/0, // DstI[vdata]
      GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/0, // srsrc
      GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/1, // soffset
      GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/2, // offset
      GIR_AddImm8, /*InsnID*/0, /*Imm*/0,
      GIR_AddImm8, /*InsnID*/0, /*Imm*/0,
      GIR_MergeMemOperands, /*InsnID*/0, /*NumInsns*/1, /*MergeInsnID's*/0,
      GIR_ConstrainSelectedInstOperands, /*InsnID*/0,
      GIR_EraseFromParent, /*InsnID*/0,
      // GIR_Coverage, 3747,
      GIR_Done,
    // Label 852: @55022
    GIM_Try, /*On fail goto*//*Label 853*/ GIMT_Encode4(55091), // Rule ID 3749 //
      GIM_CheckMemoryAddressSpace, /*MI*/0, /*MMO*/0, /*NumAddrSpace*/3, /*AddrSpace*/1, /*AddrSpace*/4, /*AddrSpace*/6,
      GIM_CheckAtomicOrdering, /*MI*/0, /*Order*/(uint8_t)AtomicOrdering::NotAtomic,
      GIM_CheckRegBankForClass, /*MI*/0, /*Op*/0, /*RC*/GIMT_Encode2(AMDGPU::AV_64RegClassID),
      GIM_CheckPointerToAny, /*MI*/0, /*Op*/1, /*SizeInBits*/0,
      GIM_CheckComplexPattern, /*MI*/0, /*Op*/1, /*Renderer*/GIMT_Encode2(0), GIMT_Encode2(GICP_gi_mubuf_offset),
      // (ld:{ *:[i64] } (MUBUFOffset:{ *:[iPTR] } v4i32:{ *:[v4i32] }:$srsrc, i32:{ *:[i32] }:$soffset, i32:{ *:[i32] }:$offset))<<P:Predicate_unindexedload>><<P:Predicate_load_global>>  =>  (BUFFER_LOAD_DWORDX2_VBUFFER_OFFSET:{ *:[i64] } v4i32:{ *:[v4i32] }:$srsrc, i32:{ *:[i32] }:$soffset, i32:{ *:[i32] }:$offset)
      GIR_BuildMI, /*InsnID*/0, /*Opcode*/GIMT_Encode2(AMDGPU::BUFFER_LOAD_DWORDX2_VBUFFER_OFFSET),
      GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/0, // DstI[vdata]
      GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/0, // srsrc
      GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/1, // soffset
      GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/2, // offset
      GIR_AddImm8, /*InsnID*/0, /*Imm*/0,
      GIR_AddImm8, /*InsnID*/0, /*Imm*/0,
      GIR_MergeMemOperands, /*InsnID*/0, /*NumInsns*/1, /*MergeInsnID's*/0,
      GIR_ConstrainSelectedInstOperands, /*InsnID*/0,
      GIR_EraseFromParent, /*InsnID*/0,
      // GIR_Coverage, 3749,
      GIR_Done,
    // Label 853: @55091
    GIM_Try, /*On fail goto*//*Label 854*/ GIMT_Encode4(55158), // Rule ID 6705 //
      GIM_CheckFeatures, GIMT_Encode2(GIFBS_NotLDSRequiresM0Init),
      GIM_CheckMemoryAddressSpace, /*MI*/0, /*MMO*/0, /*NumAddrSpace*/1, /*AddrSpace*/3,
      GIM_CheckAtomicOrdering, /*MI*/0, /*Order*/(uint8_t)AtomicOrdering::NotAtomic,
      GIM_CheckRegBankForClass, /*MI*/0, /*Op*/0, /*RC*/GIMT_Encode2(AMDGPU::AV_64RegClassID),
      GIM_CheckPointerToAny, /*MI*/0, /*Op*/1, /*SizeInBits*/0,
      GIM_CheckComplexPattern, /*MI*/0, /*Op*/1, /*Renderer*/GIMT_Encode2(0), GIMT_Encode2(GICP_gi_ds_64bit_4byte_aligned),
      // (ld:{ *:[i64] } (DS64Bit4ByteAligned:{ *:[iPTR] } i32:{ *:[i32] }:$ptr, i8:{ *:[i8] }:$offset0, i8:{ *:[i8] }:$offset1))<<P:Predicate_unindexedload>><<P:Predicate_load_local>>  =>  (DS_READ2_B32_gfx9:{ *:[i64] } ?:{ *:[i32] }:$ptr, ?:{ *:[i8] }:$offset0, ?:{ *:[i8] }:$offset1, 0:{ *:[i1] })
      GIR_BuildMI, /*InsnID*/0, /*Opcode*/GIMT_Encode2(AMDGPU::DS_READ2_B32_gfx9),
      GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/0, // DstI[vdst]
      GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/0, // ptr
      GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/1, // offset0
      GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/2, // offset1
      GIR_AddImm8, /*InsnID*/0, /*Imm*/0,
      GIR_MergeMemOperands, /*InsnID*/0, /*NumInsns*/1, /*MergeInsnID's*/0,
      GIR_ConstrainSelectedInstOperands, /*InsnID*/0,
      GIR_EraseFromParent, /*InsnID*/0,
      // GIR_Coverage, 6705,
      GIR_Done,
    // Label 854: @55158
    GIM_Try, /*On fail goto*//*Label 855*/ GIMT_Encode4(55220), // Rule ID 7098 //
      GIM_CheckMemorySizeEqualToLLT, /*MI*/0, /*MMO*/0, /*OpIdx*/0,
      GIM_CheckAtomicOrdering, /*MI*/0, /*Order*/(uint8_t)AtomicOrdering::NotAtomic,
      GIM_CheckRegBankForClass, /*MI*/0, /*Op*/0, /*RC*/GIMT_Encode2(AMDGPU::SReg_64_XEXECRegClassID),
      GIM_CheckPointerToAny, /*MI*/0, /*Op*/1, /*SizeInBits*/0,
      GIM_CheckCxxInsnPredicate, /*MI*/0, /*FnId*/GIMT_Encode2(GICXXPred_MI_Predicate_smrd_load),
      GIM_CheckComplexPattern, /*MI*/0, /*Op*/1, /*Renderer*/GIMT_Encode2(0), GIMT_Encode2(GICP_gi_smrd_imm),
      // (ld:{ *:[i64] } (SMRDImm:{ *:[iPTR] } i64:{ *:[i64] }:$sbase, i32:{ *:[i32] }:$offset))<<P:Predicate_unindexedload>><<P:Predicate_load>><<P:Predicate_smrd_load>>  =>  (S_LOAD_DWORDX2_IMM:{ *:[i64] } ?:{ *:[i64] }:$sbase, ?:{ *:[i32] }:$offset, 0:{ *:[i32] })
      GIR_BuildMI, /*InsnID*/0, /*Opcode*/GIMT_Encode2(AMDGPU::S_LOAD_DWORDX2_IMM),
      GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/0, // DstI[sdst]
      GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/0, // sbase
      GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/1, // offset
      GIR_AddImm8, /*InsnID*/0, /*Imm*/0,
      GIR_MergeMemOperands, /*InsnID*/0, /*NumInsns*/1, /*MergeInsnID's*/0,
      GIR_ConstrainSelectedInstOperands, /*InsnID*/0,
      GIR_EraseFromParent, /*InsnID*/0,
      // GIR_Coverage, 7098,
      GIR_Done,
    // Label 855: @55220
    GIM_Try, /*On fail goto*//*Label 856*/ GIMT_Encode4(55285), // Rule ID 7099 //
      GIM_CheckFeatures, GIMT_Encode2(GIFBS_isGFX7Only),
      GIM_CheckMemorySizeEqualToLLT, /*MI*/0, /*MMO*/0, /*OpIdx*/0,
      GIM_CheckAtomicOrdering, /*MI*/0, /*Order*/(uint8_t)AtomicOrdering::NotAtomic,
      GIM_CheckRegBankForClass, /*MI*/0, /*Op*/0, /*RC*/GIMT_Encode2(AMDGPU::SReg_64_XEXECRegClassID),
      GIM_CheckPointerToAny, /*MI*/0, /*Op*/1, /*SizeInBits*/0,
      GIM_CheckCxxInsnPredicate, /*MI*/0, /*FnId*/GIMT_Encode2(GICXXPred_MI_Predicate_smrd_load),
      GIM_CheckComplexPattern, /*MI*/0, /*Op*/1, /*Renderer*/GIMT_Encode2(0), GIMT_Encode2(GICP_gi_smrd_imm32),
      // (ld:{ *:[i64] } (SMRDImm32:{ *:[iPTR] } i64:{ *:[i64] }:$sbase, i32:{ *:[i32] }:$offset))<<P:Predicate_unindexedload>><<P:Predicate_load>><<P:Predicate_smrd_load>>  =>  (S_LOAD_DWORDX2_IMM_ci:{ *:[i64] } ?:{ *:[i64] }:$sbase, ?:{ *:[i32] }:$offset, 0:{ *:[i32] })
      GIR_BuildMI, /*InsnID*/0, /*Opcode*/GIMT_Encode2(AMDGPU::S_LOAD_DWORDX2_IMM_ci),
      GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/0, // DstI[sdst]
      GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/0, // sbase
      GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/1, // offset
      GIR_AddImm8, /*InsnID*/0, /*Imm*/0,
      GIR_MergeMemOperands, /*InsnID*/0, /*NumInsns*/1, /*MergeInsnID's*/0,
      GIR_ConstrainSelectedInstOperands, /*InsnID*/0,
      GIR_EraseFromParent, /*InsnID*/0,
      // GIR_Coverage, 7099,
      GIR_Done,
    // Label 856: @55285
    GIM_Try, /*On fail goto*//*Label 857*/ GIMT_Encode4(55350), // Rule ID 7100 //
      GIM_CheckFeatures, GIMT_Encode2(GIFBS_isNotGFX9Plus),
      GIM_CheckMemorySizeEqualToLLT, /*MI*/0, /*MMO*/0, /*OpIdx*/0,
      GIM_CheckAtomicOrdering, /*MI*/0, /*Order*/(uint8_t)AtomicOrdering::NotAtomic,
      GIM_CheckRegBankForClass, /*MI*/0, /*Op*/0, /*RC*/GIMT_Encode2(AMDGPU::SReg_64_XEXECRegClassID),
      GIM_CheckPointerToAny, /*MI*/0, /*Op*/1, /*SizeInBits*/0,
      GIM_CheckCxxInsnPredicate, /*MI*/0, /*FnId*/GIMT_Encode2(GICXXPred_MI_Predicate_smrd_load),
      GIM_CheckComplexPattern, /*MI*/0, /*Op*/1, /*Renderer*/GIMT_Encode2(0), GIMT_Encode2(GICP_gi_smrd_sgpr),
      // (ld:{ *:[i64] } (SMRDSgpr:{ *:[iPTR] } i64:{ *:[i64] }:$sbase, i32:{ *:[i32] }:$soffset))<<P:Predicate_unindexedload>><<P:Predicate_load>><<P:Predicate_smrd_load>>  =>  (S_LOAD_DWORDX2_SGPR:{ *:[i64] } ?:{ *:[i64] }:$sbase, ?:{ *:[i32] }:$soffset, 0:{ *:[i32] })
      GIR_BuildMI, /*InsnID*/0, /*Opcode*/GIMT_Encode2(AMDGPU::S_LOAD_DWORDX2_SGPR),
      GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/0, // DstI[sdst]
      GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/0, // sbase
      GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/1, // soffset
      GIR_AddImm8, /*InsnID*/0, /*Imm*/0,
      GIR_MergeMemOperands, /*InsnID*/0, /*NumInsns*/1, /*MergeInsnID's*/0,
      GIR_ConstrainSelectedInstOperands, /*InsnID*/0,
      GIR_EraseFromParent, /*InsnID*/0,
      // GIR_Coverage, 7100,
      GIR_Done,
    // Label 857: @55350
    GIM_Try, /*On fail goto*//*Label 858*/ GIMT_Encode4(55418), // Rule ID 7101 //
      GIM_CheckFeatures, GIMT_Encode2(GIFBS_isGFX9Plus),
      GIM_CheckMemorySizeEqualToLLT, /*MI*/0, /*MMO*/0, /*OpIdx*/0,
      GIM_CheckAtomicOrdering, /*MI*/0, /*Order*/(uint8_t)AtomicOrdering::NotAtomic,
      GIM_CheckRegBankForClass, /*MI*/0, /*Op*/0, /*RC*/GIMT_Encode2(AMDGPU::SReg_64_XEXECRegClassID),
      GIM_CheckPointerToAny, /*MI*/0, /*Op*/1, /*SizeInBits*/0,
      GIM_CheckCxxInsnPredicate, /*MI*/0, /*FnId*/GIMT_Encode2(GICXXPred_MI_Predicate_smrd_load),
      GIM_CheckComplexPattern, /*MI*/0, /*Op*/1, /*Renderer*/GIMT_Encode2(0), GIMT_Encode2(GICP_gi_smrd_sgpr),
      // (ld:{ *:[i64] } (SMRDSgpr:{ *:[iPTR] } i64:{ *:[i64] }:$sbase, i32:{ *:[i32] }:$soffset))<<P:Predicate_unindexedload>><<P:Predicate_load>><<P:Predicate_smrd_load>>  =>  (S_LOAD_DWORDX2_SGPR_IMM:{ *:[i64] } ?:{ *:[i64] }:$sbase, ?:{ *:[i32] }:$soffset, 0:{ *:[i32] }, 0:{ *:[i32] })
      GIR_BuildMI, /*InsnID*/0, /*Opcode*/GIMT_Encode2(AMDGPU::S_LOAD_DWORDX2_SGPR_IMM),
      GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/0, // DstI[sdst]
      GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/0, // sbase
      GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/1, // soffset
      GIR_AddImm8, /*InsnID*/0, /*Imm*/0,
      GIR_AddImm8, /*InsnID*/0, /*Imm*/0,
      GIR_MergeMemOperands, /*InsnID*/0, /*NumInsns*/1, /*MergeInsnID's*/0,
      GIR_ConstrainSelectedInstOperands, /*InsnID*/0,
      GIR_EraseFromParent, /*InsnID*/0,
      // GIR_Coverage, 7101,
      GIR_Done,
    // Label 858: @55418
    GIM_Try, /*On fail goto*//*Label 859*/ GIMT_Encode4(55487), // Rule ID 3057 //
      GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasFlatGlobalInsts),
      GIM_CheckMemoryAddressSpace, /*MI*/0, /*MMO*/0, /*NumAddrSpace*/3, /*AddrSpace*/1, /*AddrSpace*/4, /*AddrSpace*/6,
      GIM_CheckAtomicOrdering, /*MI*/0, /*Order*/(uint8_t)AtomicOrdering::NotAtomic,
      GIM_CheckRegBankForClass, /*MI*/0, /*Op*/0, /*RC*/GIMT_Encode2(AMDGPU::AV_64RegClassID),
      GIM_CheckPointerToAny, /*MI*/0, /*Op*/1, /*SizeInBits*/0,
      GIM_CheckComplexPattern, /*MI*/0, /*Op*/1, /*Renderer*/GIMT_Encode2(0), GIMT_Encode2(GICP_gi_global_saddr),
      // (ld:{ *:[i64] } (GlobalSAddr:{ *:[iPTR] } SReg_64:{ *:[i64] }:$saddr, VGPR_32:{ *:[i32] }:$voffset, i32:{ *:[i32] }:$offset))<<P:Predicate_unindexedload>><<P:Predicate_load_global>>  =>  (GLOBAL_LOAD_DWORDX2_SADDR:{ *:[i64] } ?:{ *:[i64] }:$saddr, ?:{ *:[i32] }:$voffset, ?:{ *:[i32] }:$offset, 0:{ *:[i32] })
      GIR_BuildMI, /*InsnID*/0, /*Opcode*/GIMT_Encode2(AMDGPU::GLOBAL_LOAD_DWORDX2_SADDR),
      GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/0, // DstI[vdst]
      GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/0, // saddr
      GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/1, // voffset
      GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/2, // offset
      GIR_AddImm8, /*InsnID*/0, /*Imm*/0,
      GIR_MergeMemOperands, /*InsnID*/0, /*NumInsns*/1, /*MergeInsnID's*/0,
      GIR_ConstrainSelectedInstOperands, /*InsnID*/0,
      GIR_EraseFromParent, /*InsnID*/0,
      // GIR_Coverage, 3057,
      GIR_Done,
    // Label 859: @55487
    GIM_Try, /*On fail goto*//*Label 860*/ GIMT_Encode4(55551), // Rule ID 3056 //
      GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasFlatGlobalInsts),
      GIM_CheckMemoryAddressSpace, /*MI*/0, /*MMO*/0, /*NumAddrSpace*/3, /*AddrSpace*/1, /*AddrSpace*/4, /*AddrSpace*/6,
      GIM_CheckAtomicOrdering, /*MI*/0, /*Order*/(uint8_t)AtomicOrdering::NotAtomic,
      GIM_CheckRegBankForClass, /*MI*/0, /*Op*/0, /*RC*/GIMT_Encode2(AMDGPU::AV_64RegClassID),
      GIM_CheckPointerToAny, /*MI*/0, /*Op*/1, /*SizeInBits*/0,
      GIM_CheckComplexPattern, /*MI*/0, /*Op*/1, /*Renderer*/GIMT_Encode2(0), GIMT_Encode2(GICP_gi_global_offset),
      // (ld:{ *:[i64] } (GlobalOffset:{ *:[iPTR] } VReg_64:{ *:[i64] }:$vaddr, i32:{ *:[i32] }:$offset))<<P:Predicate_unindexedload>><<P:Predicate_load_global>>  =>  (GLOBAL_LOAD_DWORDX2:{ *:[i64] } ?:{ *:[i64] }:$vaddr, ?:{ *:[i32] }:$offset)
      GIR_BuildMI, /*InsnID*/0, /*Opcode*/GIMT_Encode2(AMDGPU::GLOBAL_LOAD_DWORDX2),
      GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/0, // DstI[vdst]
      GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/0, // vaddr
      GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/1, // offset
      GIR_AddImm8, /*InsnID*/0, /*Imm*/0,
      GIR_MergeMemOperands, /*InsnID*/0, /*NumInsns*/1, /*MergeInsnID's*/0,
      GIR_ConstrainSelectedInstOperands, /*InsnID*/0,
      GIR_EraseFromParent, /*InsnID*/0,
      // GIR_Coverage, 3056,
      GIR_Done,
    // Label 860: @55551
    GIM_Try, /*On fail goto*//*Label 861*/ GIMT_Encode4(55608), // Rule ID 7103 //
      GIM_CheckMemorySizeEqualToLLT, /*MI*/0, /*MMO*/0, /*OpIdx*/0,
      GIM_CheckAtomicOrdering, /*MI*/0, /*Order*/(uint8_t)AtomicOrdering::NotAtomic,
      GIM_CheckRegBankForClass, /*MI*/0, /*Op*/0, /*RC*/GIMT_Encode2(AMDGPU::SReg_64_XEXECRegClassID),
      // MIs[0] sbase
      GIM_CheckPointerToAny, /*MI*/0, /*Op*/1, /*SizeInBits*/64,
      GIM_CheckRegBankForClass, /*MI*/0, /*Op*/1, /*RC*/GIMT_Encode2(AMDGPU::SReg_64RegClassID),
      GIM_CheckCxxInsnPredicate, /*MI*/0, /*FnId*/GIMT_Encode2(GICXXPred_MI_Predicate_smrd_load),
      // (ld:{ *:[i64] } SReg_64:{ *:[i64] }:$sbase)<<P:Predicate_unindexedload>><<P:Predicate_load>><<P:Predicate_smrd_load>>  =>  (S_LOAD_DWORDX2_IMM:{ *:[i64] } i64:{ *:[i64] }:$sbase, 0:{ *:[i32] }, 0:{ *:[i32] })
      GIR_BuildMI, /*InsnID*/0, /*Opcode*/GIMT_Encode2(AMDGPU::S_LOAD_DWORDX2_IMM),
      GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/0, // DstI[sdst]
      GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/1, // sbase
      GIR_AddImm8, /*InsnID*/0, /*Imm*/0,
      GIR_AddImm8, /*InsnID*/0, /*Imm*/0,
      GIR_MergeMemOperands, /*InsnID*/0, /*NumInsns*/1, /*MergeInsnID's*/0,
      GIR_ConstrainSelectedInstOperands, /*InsnID*/0,
      GIR_EraseFromParent, /*InsnID*/0,
      // GIR_Coverage, 7103,
      GIR_Done,
    // Label 861: @55608
    GIM_Try, /*On fail goto*//*Label 862*/ GIMT_Encode4(55673), // Rule ID 2803 //
      GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasFlatAddressSpace),
      GIM_CheckMemoryAddressSpace, /*MI*/0, /*MMO*/0, /*NumAddrSpace*/4, /*AddrSpace*/0, /*AddrSpace*/1, /*AddrSpace*/4, /*AddrSpace*/6,
      GIM_CheckAtomicOrdering, /*MI*/0, /*Order*/(uint8_t)AtomicOrdering::NotAtomic,
      GIM_CheckRegBankForClass, /*MI*/0, /*Op*/0, /*RC*/GIMT_Encode2(AMDGPU::AV_64RegClassID),
      GIM_CheckPointerToAny, /*MI*/0, /*Op*/1, /*SizeInBits*/0,
      GIM_CheckComplexPattern, /*MI*/0, /*Op*/1, /*Renderer*/GIMT_Encode2(0), GIMT_Encode2(GICP_gi_flat_offset),
      // (ld:{ *:[i64] } (FlatOffset:{ *:[iPTR] } i64:{ *:[i64] }:$vaddr, i32:{ *:[i32] }:$offset))<<P:Predicate_unindexedload>><<P:Predicate_load_flat>>  =>  (FLAT_LOAD_DWORDX2:{ *:[i64] } ?:{ *:[i64] }:$vaddr, ?:{ *:[i32] }:$offset)
      GIR_BuildMI, /*InsnID*/0, /*Opcode*/GIMT_Encode2(AMDGPU::FLAT_LOAD_DWORDX2),
      GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/0, // DstI[vdst]
      GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/0, // vaddr
      GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/1, // offset
      GIR_AddImm8, /*InsnID*/0, /*Imm*/0,
      GIR_MergeMemOperands, /*InsnID*/0, /*NumInsns*/1, /*MergeInsnID's*/0,
      GIR_ConstrainSelectedInstOperands, /*InsnID*/0,
      GIR_EraseFromParent, /*InsnID*/0,
      // GIR_Coverage, 2803,
      GIR_Done,
    // Label 862: @55673
    GIM_Reject,
    // Label 817: @55674
    GIM_Try, /*On fail goto*//*Label 863*/ GIMT_Encode4(55749), // Rule ID 6847 //
      GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasUnalignedAccessMode_LDSRequiresM0Init),
      GIM_CheckMemorySizeEqualToLLT, /*MI*/0, /*MMO*/0, /*OpIdx*/0,
      GIM_CheckMemoryAddressSpace, /*MI*/0, /*MMO*/0, /*NumAddrSpace*/1, /*AddrSpace*/3,
      GIM_CheckMemoryAddressSpace, /*MI*/0, /*MMO*/0, /*NumAddrSpace*/1, /*AddrSpace*/3,
      GIM_CheckAtomicOrdering, /*MI*/0, /*Order*/(uint8_t)AtomicOrdering::NotAtomic,
      GIM_CheckRegBankForClass, /*MI*/0, /*Op*/0, /*RC*/GIMT_Encode2(AMDGPU::AV_64RegClassID),
      GIM_CheckPointerToAny, /*MI*/0, /*Op*/1, /*SizeInBits*/0,
      GIM_CheckCxxInsnPredicate, /*MI*/0, /*FnId*/GIMT_Encode2(GICXXPred_MI_Predicate_load_align_less_than_4_local_m0),
      GIM_CheckComplexPattern, /*MI*/0, /*Op*/1, /*Renderer*/GIMT_Encode2(0), GIMT_Encode2(GICP_gi_ds_1addr_1offset),
      // (AMDGPUld_glue:{ *:[i64] } (DS1Addr1Offset:{ *:[iPTR] } i32:{ *:[i32] }:$ptr, i32:{ *:[i32] }:$offset))<<P:Predicate_unindexedload_glue>><<P:Predicate_load_glue>><<P:Predicate_load_local_m0>><<P:Predicate_load_align_less_than_4_local_m0>>  =>  (DS_READ_B64:{ *:[i64] } ?:{ *:[i32] }:$ptr, offset:{ *:[i32] }:$offset, 0:{ *:[i1] })
      GIR_BuildMI, /*InsnID*/0, /*Opcode*/GIMT_Encode2(AMDGPU::DS_READ_B64),
      GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/0, // DstI[vdst]
      GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/0, // ptr
      GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/1, // offset
      GIR_AddImm8, /*InsnID*/0, /*Imm*/0,
      GIR_MergeMemOperands, /*InsnID*/0, /*NumInsns*/1, /*MergeInsnID's*/0,
      GIR_ConstrainSelectedInstOperands, /*InsnID*/0,
      GIR_EraseFromParent, /*InsnID*/0,
      // GIR_Coverage, 6847,
      GIR_Done,
    // Label 863: @55749
    GIM_Try, /*On fail goto*//*Label 864*/ GIMT_Encode4(55819), // Rule ID 6771 //
      GIM_CheckFeatures, GIMT_Encode2(GIFBS_LDSRequiresM0Init),
      GIM_CheckMemorySizeEqualToLLT, /*MI*/0, /*MMO*/0, /*OpIdx*/0,
      GIM_CheckMemoryAddressSpace, /*MI*/0, /*MMO*/0, /*NumAddrSpace*/1, /*AddrSpace*/3,
      GIM_CheckMemoryAlignment, /*MI*/0, /*MMO*/0, /*MinAlign*/8,
      GIM_CheckAtomicOrdering, /*MI*/0, /*Order*/(uint8_t)AtomicOrdering::NotAtomic,
      GIM_CheckRegBankForClass, /*MI*/0, /*Op*/0, /*RC*/GIMT_Encode2(AMDGPU::AV_64RegClassID),
      GIM_CheckPointerToAny, /*MI*/0, /*Op*/1, /*SizeInBits*/0,
      GIM_CheckComplexPattern, /*MI*/0, /*Op*/1, /*Renderer*/GIMT_Encode2(0), GIMT_Encode2(GICP_gi_ds_1addr_1offset),
      // (AMDGPUld_glue:{ *:[i64] } (DS1Addr1Offset:{ *:[iPTR] } i32:{ *:[i32] }:$ptr, i32:{ *:[i32] }:$offset))<<P:Predicate_unindexedload_glue>><<P:Predicate_load_glue>><<P:Predicate_load_local_m0>><<P:Predicate_load_align8_local_m0>>  =>  (DS_READ_B64:{ *:[i64] } ?:{ *:[i32] }:$ptr, offset:{ *:[i32] }:$offset, 0:{ *:[i1] })
      GIR_BuildMI, /*InsnID*/0, /*Opcode*/GIMT_Encode2(AMDGPU::DS_READ_B64),
      GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/0, // DstI[vdst]
      GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/0, // ptr
      GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/1, // offset
      GIR_AddImm8, /*InsnID*/0, /*Imm*/0,
      GIR_MergeMemOperands, /*InsnID*/0, /*NumInsns*/1, /*MergeInsnID's*/0,
      GIR_ConstrainSelectedInstOperands, /*InsnID*/0,
      GIR_EraseFromParent, /*InsnID*/0,
      // GIR_Coverage, 6771,
      GIR_Done,
    // Label 864: @55819
    GIM_Try, /*On fail goto*//*Label 865*/ GIMT_Encode4(55890), // Rule ID 6848 //
      GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasUnalignedAccessMode_NotLDSRequiresM0Init),
      GIM_CheckMemoryAddressSpace, /*MI*/0, /*MMO*/0, /*NumAddrSpace*/1, /*AddrSpace*/3,
      GIM_CheckMemoryAddressSpace, /*MI*/0, /*MMO*/0, /*NumAddrSpace*/1, /*AddrSpace*/3,
      GIM_CheckAtomicOrdering, /*MI*/0, /*Order*/(uint8_t)AtomicOrdering::NotAtomic,
      GIM_CheckRegBankForClass, /*MI*/0, /*Op*/0, /*RC*/GIMT_Encode2(AMDGPU::AV_64RegClassID),
      GIM_CheckPointerToAny, /*MI*/0, /*Op*/1, /*SizeInBits*/0,
      GIM_CheckCxxInsnPredicate, /*MI*/0, /*FnId*/GIMT_Encode2(GICXXPred_MI_Predicate_load_align_less_than_4_local),
      GIM_CheckComplexPattern, /*MI*/0, /*Op*/1, /*Renderer*/GIMT_Encode2(0), GIMT_Encode2(GICP_gi_ds_1addr_1offset),
      // (ld:{ *:[i64] } (DS1Addr1Offset:{ *:[iPTR] } i32:{ *:[i32] }:$ptr, i32:{ *:[i32] }:$offset))<<P:Predicate_unindexedload>><<P:Predicate_load_local>><<P:Predicate_load_align_less_than_4_local>>  =>  (DS_READ_B64_gfx9:{ *:[i64] } ?:{ *:[i32] }:$ptr, offset:{ *:[i32] }:$offset, 0:{ *:[i1] })
      GIR_BuildMI, /*InsnID*/0, /*Opcode*/GIMT_Encode2(AMDGPU::DS_READ_B64_gfx9),
      GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/0, // DstI[vdst]
      GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/0, // ptr
      GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/1, // offset
      GIR_AddImm8, /*InsnID*/0, /*Imm*/0,
      GIR_MergeMemOperands, /*InsnID*/0, /*NumInsns*/1, /*MergeInsnID's*/0,
      GIR_ConstrainSelectedInstOperands, /*InsnID*/0,
      GIR_EraseFromParent, /*InsnID*/0,
      // GIR_Coverage, 6848,
      GIR_Done,
    // Label 865: @55890
    GIM_Try, /*On fail goto*//*Label 866*/ GIMT_Encode4(55956), // Rule ID 6772 //
      GIM_CheckFeatures, GIMT_Encode2(GIFBS_NotLDSRequiresM0Init),
      GIM_CheckMemoryAddressSpace, /*MI*/0, /*MMO*/0, /*NumAddrSpace*/1, /*AddrSpace*/3,
      GIM_CheckMemoryAlignment, /*MI*/0, /*MMO*/0, /*MinAlign*/8,
      GIM_CheckAtomicOrdering, /*MI*/0, /*Order*/(uint8_t)AtomicOrdering::NotAtomic,
      GIM_CheckRegBankForClass, /*MI*/0, /*Op*/0, /*RC*/GIMT_Encode2(AMDGPU::AV_64RegClassID),
      GIM_CheckPointerToAny, /*MI*/0, /*Op*/1, /*SizeInBits*/0,
      GIM_CheckComplexPattern, /*MI*/0, /*Op*/1, /*Renderer*/GIMT_Encode2(0), GIMT_Encode2(GICP_gi_ds_1addr_1offset),
      // (ld:{ *:[i64] } (DS1Addr1Offset:{ *:[iPTR] } i32:{ *:[i32] }:$ptr, i32:{ *:[i32] }:$offset))<<P:Predicate_unindexedload>><<P:Predicate_load_local>><<P:Predicate_load_align8_local>>  =>  (DS_READ_B64_gfx9:{ *:[i64] } ?:{ *:[i32] }:$ptr, offset:{ *:[i32] }:$offset, 0:{ *:[i1] })
      GIR_BuildMI, /*InsnID*/0, /*Opcode*/GIMT_Encode2(AMDGPU::DS_READ_B64_gfx9),
      GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/0, // DstI[vdst]
      GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/0, // ptr
      GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/1, // offset
      GIR_AddImm8, /*InsnID*/0, /*Imm*/0,
      GIR_MergeMemOperands, /*InsnID*/0, /*NumInsns*/1, /*MergeInsnID's*/0,
      GIR_ConstrainSelectedInstOperands, /*InsnID*/0,
      GIR_EraseFromParent, /*InsnID*/0,
      // GIR_Coverage, 6772,
      GIR_Done,
    // Label 866: @55956
    GIM_Try, /*On fail goto*//*Label 867*/ GIMT_Encode4(56023), // Rule ID 3532 //
      GIM_CheckFeatures, GIMT_Encode2(GIFBS_EnableFlatScratch_HasFlatScratchInsts_HasFlatScratchSVSMode),
      GIM_CheckMemoryAddressSpace, /*MI*/0, /*MMO*/0, /*NumAddrSpace*/1, /*AddrSpace*/5,
      GIM_CheckAtomicOrdering, /*MI*/0, /*Order*/(uint8_t)AtomicOrdering::NotAtomic,
      GIM_CheckRegBankForClass, /*MI*/0, /*Op*/0, /*RC*/GIMT_Encode2(AMDGPU::AV_64RegClassID),
      GIM_CheckPointerToAny, /*MI*/0, /*Op*/1, /*SizeInBits*/0,
      GIM_CheckComplexPattern, /*MI*/0, /*Op*/1, /*Renderer*/GIMT_Encode2(0), GIMT_Encode2(GICP_gi_flat_scratch_svaddr),
      // (ld:{ *:[i64] } (ScratchSVAddr:{ *:[iPTR] } VGPR_32:{ *:[i32] }:$vaddr, SGPR_32:{ *:[i32] }:$saddr, i32:{ *:[i32] }:$offset))<<P:Predicate_unindexedload>><<P:Predicate_load_private>>  =>  (SCRATCH_LOAD_DWORDX2_SVS:{ *:[i64] } ?:{ *:[i32] }:$vaddr, ?:{ *:[i32] }:$saddr, ?:{ *:[i32] }:$offset, 0:{ *:[i32] })
      GIR_BuildMI, /*InsnID*/0, /*Opcode*/GIMT_Encode2(AMDGPU::SCRATCH_LOAD_DWORDX2_SVS),
      GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/0, // DstI[vdst]
      GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/0, // vaddr
      GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/1, // saddr
      GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/2, // offset
      GIR_AddImm8, /*InsnID*/0, /*Imm*/0,
      GIR_MergeMemOperands, /*InsnID*/0, /*NumInsns*/1, /*MergeInsnID's*/0,
      GIR_ConstrainSelectedInstOperands, /*InsnID*/0,
      GIR_EraseFromParent, /*InsnID*/0,
      // GIR_Coverage, 3532,
      GIR_Done,
    // Label 867: @56023
    GIM_Try, /*On fail goto*//*Label 868*/ GIMT_Encode4(56085), // Rule ID 3531 //
      GIM_CheckFeatures, GIMT_Encode2(GIFBS_EnableFlatScratch_HasFlatScratchInsts),
      GIM_CheckMemoryAddressSpace, /*MI*/0, /*MMO*/0, /*NumAddrSpace*/1, /*AddrSpace*/5,
      GIM_CheckAtomicOrdering, /*MI*/0, /*Order*/(uint8_t)AtomicOrdering::NotAtomic,
      GIM_CheckRegBankForClass, /*MI*/0, /*Op*/0, /*RC*/GIMT_Encode2(AMDGPU::AV_64RegClassID),
      GIM_CheckPointerToAny, /*MI*/0, /*Op*/1, /*SizeInBits*/0,
      GIM_CheckComplexPattern, /*MI*/0, /*Op*/1, /*Renderer*/GIMT_Encode2(0), GIMT_Encode2(GICP_gi_flat_scratch_saddr),
      // (ld:{ *:[i64] } (ScratchSAddr:{ *:[iPTR] } SGPR_32:{ *:[i32] }:$saddr, i32:{ *:[i32] }:$offset))<<P:Predicate_unindexedload>><<P:Predicate_load_private>>  =>  (SCRATCH_LOAD_DWORDX2_SADDR:{ *:[i64] } ?:{ *:[i32] }:$saddr, ?:{ *:[i32] }:$offset)
      GIR_BuildMI, /*InsnID*/0, /*Opcode*/GIMT_Encode2(AMDGPU::SCRATCH_LOAD_DWORDX2_SADDR),
      GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/0, // DstI[vdst]
      GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/0, // saddr
      GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/1, // offset
      GIR_AddImm8, /*InsnID*/0, /*Imm*/0,
      GIR_MergeMemOperands, /*InsnID*/0, /*NumInsns*/1, /*MergeInsnID's*/0,
      GIR_ConstrainSelectedInstOperands, /*InsnID*/0,
      GIR_EraseFromParent, /*InsnID*/0,
      // GIR_Coverage, 3531,
      GIR_Done,
    // Label 868: @56085
    GIM_Try, /*On fail goto*//*Label 869*/ GIMT_Encode4(56147), // Rule ID 3530 //
      GIM_CheckFeatures, GIMT_Encode2(GIFBS_EnableFlatScratch_HasFlatScratchInsts),
      GIM_CheckMemoryAddressSpace, /*MI*/0, /*MMO*/0, /*NumAddrSpace*/1, /*AddrSpace*/5,
      GIM_CheckAtomicOrdering, /*MI*/0, /*Order*/(uint8_t)AtomicOrdering::NotAtomic,
      GIM_CheckRegBankForClass, /*MI*/0, /*Op*/0, /*RC*/GIMT_Encode2(AMDGPU::AV_64RegClassID),
      GIM_CheckPointerToAny, /*MI*/0, /*Op*/1, /*SizeInBits*/0,
      GIM_CheckComplexPattern, /*MI*/0, /*Op*/1, /*Renderer*/GIMT_Encode2(0), GIMT_Encode2(GICP_gi_flat_scratch_offset),
      // (ld:{ *:[i64] } (ScratchOffset:{ *:[iPTR] } VGPR_32:{ *:[i32] }:$vaddr, i32:{ *:[i32] }:$offset))<<P:Predicate_unindexedload>><<P:Predicate_load_private>>  =>  (SCRATCH_LOAD_DWORDX2:{ *:[i64] } ?:{ *:[i32] }:$vaddr, ?:{ *:[i32] }:$offset)
      GIR_BuildMI, /*InsnID*/0, /*Opcode*/GIMT_Encode2(AMDGPU::SCRATCH_LOAD_DWORDX2),
      GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/0, // DstI[vdst]
      GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/0, // vaddr
      GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/1, // offset
      GIR_AddImm8, /*InsnID*/0, /*Imm*/0,
      GIR_MergeMemOperands, /*InsnID*/0, /*NumInsns*/1, /*MergeInsnID's*/0,
      GIR_ConstrainSelectedInstOperands, /*InsnID*/0,
      GIR_EraseFromParent, /*InsnID*/0,
      // GIR_Coverage, 3530,
      GIR_Done,
    // Label 869: @56147
    GIM_Try, /*On fail goto*//*Label 870*/ GIMT_Encode4(56224), // Rule ID 3752 //
      GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasUnrestrictedSOffset),
      GIM_CheckMemoryAddressSpace, /*MI*/0, /*MMO*/0, /*NumAddrSpace*/3, /*AddrSpace*/1, /*AddrSpace*/4, /*AddrSpace*/6,
      GIM_CheckAtomicOrdering, /*MI*/0, /*Order*/(uint8_t)AtomicOrdering::NotAtomic,
      GIM_CheckRegBankForClass, /*MI*/0, /*Op*/0, /*RC*/GIMT_Encode2(AMDGPU::AV_64RegClassID),
      GIM_CheckPointerToAny, /*MI*/0, /*Op*/1, /*SizeInBits*/0,
      GIM_CheckComplexPattern, /*MI*/0, /*Op*/1, /*Renderer*/GIMT_Encode2(0), GIMT_Encode2(GICP_gi_mubuf_addr64),
      // (ld:{ *:[i64] } (MUBUFAddr64:{ *:[iPTR] } v4i32:{ *:[v4i32] }:$srsrc, i64:{ *:[i64] }:$vaddr, i32:{ *:[i32] }:$soffset, i32:{ *:[i32] }:$offset))<<P:Predicate_unindexedload>><<P:Predicate_load_global>>  =>  (BUFFER_LOAD_DWORDX2_ADDR64:{ *:[i64] } i64:{ *:[i64] }:$vaddr, v4i32:{ *:[v4i32] }:$srsrc, i32:{ *:[i32] }:$soffset, i32:{ *:[i32] }:$offset)
      GIR_BuildMI, /*InsnID*/0, /*Opcode*/GIMT_Encode2(AMDGPU::BUFFER_LOAD_DWORDX2_ADDR64),
      GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/0, // DstI[vdata]
      GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/1, // vaddr
      GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/0, // srsrc
      GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/2, // soffset
      GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/3, // offset
      GIR_AddImm8, /*InsnID*/0, /*Imm*/0,
      GIR_AddImm8, /*InsnID*/0, /*Imm*/0,
      GIR_MergeMemOperands, /*InsnID*/0, /*NumInsns*/1, /*MergeInsnID's*/0,
      GIR_ConstrainSelectedInstOperands, /*InsnID*/0,
      GIR_EraseFromParent, /*InsnID*/0,
      // GIR_Coverage, 3752,
      GIR_Done,
    // Label 870: @56224
    GIM_Try, /*On fail goto*//*Label 871*/ GIMT_Encode4(56298), // Rule ID 3754 //
      GIM_CheckMemoryAddressSpace, /*MI*/0, /*MMO*/0, /*NumAddrSpace*/3, /*AddrSpace*/1, /*AddrSpace*/4, /*AddrSpace*/6,
      GIM_CheckAtomicOrdering, /*MI*/0, /*Order*/(uint8_t)AtomicOrdering::NotAtomic,
      GIM_CheckRegBankForClass, /*MI*/0, /*Op*/0, /*RC*/GIMT_Encode2(AMDGPU::AV_64RegClassID),
      GIM_CheckPointerToAny, /*MI*/0, /*Op*/1, /*SizeInBits*/0,
      GIM_CheckComplexPattern, /*MI*/0, /*Op*/1, /*Renderer*/GIMT_Encode2(0), GIMT_Encode2(GICP_gi_mubuf_addr64),
      // (ld:{ *:[i64] } (MUBUFAddr64:{ *:[iPTR] } v4i32:{ *:[v4i32] }:$srsrc, i64:{ *:[i64] }:$vaddr, i32:{ *:[i32] }:$soffset, i32:{ *:[i32] }:$offset))<<P:Predicate_unindexedload>><<P:Predicate_load_global>>  =>  (BUFFER_LOAD_DWORDX2_VBUFFER_ADDR64:{ *:[i64] } i64:{ *:[i64] }:$vaddr, v4i32:{ *:[v4i32] }:$srsrc, i32:{ *:[i32] }:$soffset, i32:{ *:[i32] }:$offset)
      GIR_BuildMI, /*InsnID*/0, /*Opcode*/GIMT_Encode2(AMDGPU::BUFFER_LOAD_DWORDX2_VBUFFER_ADDR64),
      GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/0, // DstI[vdata]
      GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/1, // vaddr
      GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/0, // srsrc
      GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/2, // soffset
      GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/3, // offset
      GIR_AddImm8, /*InsnID*/0, /*Imm*/0,
      GIR_AddImm8, /*InsnID*/0, /*Imm*/0,
      GIR_MergeMemOperands, /*InsnID*/0, /*NumInsns*/1, /*MergeInsnID's*/0,
      GIR_ConstrainSelectedInstOperands, /*InsnID*/0,
      GIR_EraseFromParent, /*InsnID*/0,
      // GIR_Coverage, 3754,
      GIR_Done,
    // Label 871: @56298
    GIM_Try, /*On fail goto*//*Label 872*/ GIMT_Encode4(56369), // Rule ID 6707 //
      GIM_CheckFeatures, GIMT_Encode2(GIFBS_LDSRequiresM0Init_isGFX7Plus),
      GIM_CheckMemorySizeEqualToLLT, /*MI*/0, /*MMO*/0, /*OpIdx*/0,
      GIM_CheckMemoryAddressSpace, /*MI*/0, /*MMO*/0, /*NumAddrSpace*/1, /*AddrSpace*/3,
      GIM_CheckAtomicOrdering, /*MI*/0, /*Order*/(uint8_t)AtomicOrdering::NotAtomic,
      GIM_CheckRegBankForClass, /*MI*/0, /*Op*/0, /*RC*/GIMT_Encode2(AMDGPU::AV_64RegClassID),
      GIM_CheckPointerToAny, /*MI*/0, /*Op*/1, /*SizeInBits*/0,
      GIM_CheckComplexPattern, /*MI*/0, /*Op*/1, /*Renderer*/GIMT_Encode2(0), GIMT_Encode2(GICP_gi_ds_64bit_4byte_aligned),
      // (AMDGPUld_glue:{ *:[i64] } (DS64Bit4ByteAligned:{ *:[iPTR] } i32:{ *:[i32] }:$ptr, i8:{ *:[i8] }:$offset0, i8:{ *:[i8] }:$offset1))<<P:Predicate_unindexedload_glue>><<P:Predicate_load_glue>><<P:Predicate_load_local_m0>>  =>  (DS_READ2_B32:{ *:[i64] } ?:{ *:[i32] }:$ptr, ?:{ *:[i8] }:$offset0, ?:{ *:[i8] }:$offset1, 0:{ *:[i1] })
      GIR_BuildMI, /*InsnID*/0, /*Opcode*/GIMT_Encode2(AMDGPU::DS_READ2_B32),
      GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/0, // DstI[vdst]
      GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/0, // ptr
      GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/1, // offset0
      GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/2, // offset1
      GIR_AddImm8, /*InsnID*/0, /*Imm*/0,
      GIR_MergeMemOperands, /*InsnID*/0, /*NumInsns*/1, /*MergeInsnID's*/0,
      GIR_ConstrainSelectedInstOperands, /*InsnID*/0,
      GIR_EraseFromParent, /*InsnID*/0,
      // GIR_Coverage, 6707,
      GIR_Done,
    // Label 872: @56369
    GIM_Try, /*On fail goto*//*Label 873*/ GIMT_Encode4(56439), // Rule ID 7108 //
      GIM_CheckFeatures, GIMT_Encode2(GIFBS_isGFX9Plus),
      GIM_CheckMemorySizeEqualToLLT, /*MI*/0, /*MMO*/0, /*OpIdx*/0,
      GIM_CheckAtomicOrdering, /*MI*/0, /*Order*/(uint8_t)AtomicOrdering::NotAtomic,
      GIM_CheckRegBankForClass, /*MI*/0, /*Op*/0, /*RC*/GIMT_Encode2(AMDGPU::SReg_64_XEXECRegClassID),
      GIM_CheckPointerToAny, /*MI*/0, /*Op*/1, /*SizeInBits*/0,
      GIM_CheckCxxInsnPredicate, /*MI*/0, /*FnId*/GIMT_Encode2(GICXXPred_MI_Predicate_smrd_load),
      GIM_CheckComplexPattern, /*MI*/0, /*Op*/1, /*Renderer*/GIMT_Encode2(0), GIMT_Encode2(GICP_gi_smrd_sgpr_imm),
      // (ld:{ *:[i64] } (SMRDSgprImm:{ *:[iPTR] } i64:{ *:[i64] }:$sbase, i32:{ *:[i32] }:$soffset, i32:{ *:[i32] }:$offset))<<P:Predicate_unindexedload>><<P:Predicate_load>><<P:Predicate_smrd_load>>  =>  (S_LOAD_DWORDX2_SGPR_IMM:{ *:[i64] } ?:{ *:[i64] }:$sbase, ?:{ *:[i32] }:$soffset, ?:{ *:[i32] }:$offset, 0:{ *:[i32] })
      GIR_BuildMI, /*InsnID*/0, /*Opcode*/GIMT_Encode2(AMDGPU::S_LOAD_DWORDX2_SGPR_IMM),
      GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/0, // DstI[sdst]
      GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/0, // sbase
      GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/1, // soffset
      GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/2, // offset
      GIR_AddImm8, /*InsnID*/0, /*Imm*/0,
      GIR_MergeMemOperands, /*InsnID*/0, /*NumInsns*/1, /*MergeInsnID's*/0,
      GIR_ConstrainSelectedInstOperands, /*InsnID*/0,
      GIR_EraseFromParent, /*InsnID*/0,
      // GIR_Coverage, 7108,
      GIR_Done,
    // Label 873: @56439
    GIM_Try, /*On fail goto*//*Label 874*/ GIMT_Encode4(56511), // Rule ID 3751 //
      GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasUnrestrictedSOffset),
      GIM_CheckMemoryAddressSpace, /*MI*/0, /*MMO*/0, /*NumAddrSpace*/3, /*AddrSpace*/1, /*AddrSpace*/4, /*AddrSpace*/6,
      GIM_CheckAtomicOrdering, /*MI*/0, /*Order*/(uint8_t)AtomicOrdering::NotAtomic,
      GIM_CheckRegBankForClass, /*MI*/0, /*Op*/0, /*RC*/GIMT_Encode2(AMDGPU::AV_64RegClassID),
      GIM_CheckPointerToAny, /*MI*/0, /*Op*/1, /*SizeInBits*/0,
      GIM_CheckComplexPattern, /*MI*/0, /*Op*/1, /*Renderer*/GIMT_Encode2(0), GIMT_Encode2(GICP_gi_mubuf_offset),
      // (ld:{ *:[i64] } (MUBUFOffset:{ *:[iPTR] } v4i32:{ *:[v4i32] }:$srsrc, i32:{ *:[i32] }:$soffset, i32:{ *:[i32] }:$offset))<<P:Predicate_unindexedload>><<P:Predicate_load_global>>  =>  (BUFFER_LOAD_DWORDX2_OFFSET:{ *:[i64] } v4i32:{ *:[v4i32] }:$srsrc, i32:{ *:[i32] }:$soffset, i32:{ *:[i32] }:$offset)
      GIR_BuildMI, /*InsnID*/0, /*Opcode*/GIMT_Encode2(AMDGPU::BUFFER_LOAD_DWORDX2_OFFSET),
      GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/0, // DstI[vdata]
      GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/0, // srsrc
      GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/1, // soffset
      GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/2, // offset
      GIR_AddImm8, /*InsnID*/0, /*Imm*/0,
      GIR_AddImm8, /*InsnID*/0, /*Imm*/0,
      GIR_MergeMemOperands, /*InsnID*/0, /*NumInsns*/1, /*MergeInsnID's*/0,
      GIR_ConstrainSelectedInstOperands, /*InsnID*/0,
      GIR_EraseFromParent, /*InsnID*/0,
      // GIR_Coverage, 3751,
      GIR_Done,
    // Label 874: @56511
    GIM_Try, /*On fail goto*//*Label 875*/ GIMT_Encode4(56580), // Rule ID 3753 //
      GIM_CheckMemoryAddressSpace, /*MI*/0, /*MMO*/0, /*NumAddrSpace*/3, /*AddrSpace*/1, /*AddrSpace*/4, /*AddrSpace*/6,
      GIM_CheckAtomicOrdering, /*MI*/0, /*Order*/(uint8_t)AtomicOrdering::NotAtomic,
      GIM_CheckRegBankForClass, /*MI*/0, /*Op*/0, /*RC*/GIMT_Encode2(AMDGPU::AV_64RegClassID),
      GIM_CheckPointerToAny, /*MI*/0, /*Op*/1, /*SizeInBits*/0,
      GIM_CheckComplexPattern, /*MI*/0, /*Op*/1, /*Renderer*/GIMT_Encode2(0), GIMT_Encode2(GICP_gi_mubuf_offset),
      // (ld:{ *:[i64] } (MUBUFOffset:{ *:[iPTR] } v4i32:{ *:[v4i32] }:$srsrc, i32:{ *:[i32] }:$soffset, i32:{ *:[i32] }:$offset))<<P:Predicate_unindexedload>><<P:Predicate_load_global>>  =>  (BUFFER_LOAD_DWORDX2_VBUFFER_OFFSET:{ *:[i64] } v4i32:{ *:[v4i32] }:$srsrc, i32:{ *:[i32] }:$soffset, i32:{ *:[i32] }:$offset)
      GIR_BuildMI, /*InsnID*/0, /*Opcode*/GIMT_Encode2(AMDGPU::BUFFER_LOAD_DWORDX2_VBUFFER_OFFSET),
      GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/0, // DstI[vdata]
      GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/0, // srsrc
      GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/1, // soffset
      GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/2, // offset
      GIR_AddImm8, /*InsnID*/0, /*Imm*/0,
      GIR_AddImm8, /*InsnID*/0, /*Imm*/0,
      GIR_MergeMemOperands, /*InsnID*/0, /*NumInsns*/1, /*MergeInsnID's*/0,
      GIR_ConstrainSelectedInstOperands, /*InsnID*/0,
      GIR_EraseFromParent, /*InsnID*/0,
      // GIR_Coverage, 3753,
      GIR_Done,
    // Label 875: @56580
    GIM_Try, /*On fail goto*//*Label 876*/ GIMT_Encode4(56647), // Rule ID 6709 //
      GIM_CheckFeatures, GIMT_Encode2(GIFBS_NotLDSRequiresM0Init),
      GIM_CheckMemoryAddressSpace, /*MI*/0, /*MMO*/0, /*NumAddrSpace*/1, /*AddrSpace*/3,
      GIM_CheckAtomicOrdering, /*MI*/0, /*Order*/(uint8_t)AtomicOrdering::NotAtomic,
      GIM_CheckRegBankForClass, /*MI*/0, /*Op*/0, /*RC*/GIMT_Encode2(AMDGPU::AV_64RegClassID),
      GIM_CheckPointerToAny, /*MI*/0, /*Op*/1, /*SizeInBits*/0,
      GIM_CheckComplexPattern, /*MI*/0, /*Op*/1, /*Renderer*/GIMT_Encode2(0), GIMT_Encode2(GICP_gi_ds_64bit_4byte_aligned),
      // (ld:{ *:[i64] } (DS64Bit4ByteAligned:{ *:[iPTR] } i32:{ *:[i32] }:$ptr, i8:{ *:[i8] }:$offset0, i8:{ *:[i8] }:$offset1))<<P:Predicate_unindexedload>><<P:Predicate_load_local>>  =>  (DS_READ2_B32_gfx9:{ *:[i64] } ?:{ *:[i32] }:$ptr, ?:{ *:[i8] }:$offset0, ?:{ *:[i8] }:$offset1, 0:{ *:[i1] })
      GIR_BuildMI, /*InsnID*/0, /*Opcode*/GIMT_Encode2(AMDGPU::DS_READ2_B32_gfx9),
      GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/0, // DstI[vdst]
      GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/0, // ptr
      GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/1, // offset0
      GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/2, // offset1
      GIR_AddImm8, /*InsnID*/0, /*Imm*/0,
      GIR_MergeMemOperands, /*InsnID*/0, /*NumInsns*/1, /*MergeInsnID's*/0,
      GIR_ConstrainSelectedInstOperands, /*InsnID*/0,
      GIR_EraseFromParent, /*InsnID*/0,
      // GIR_Coverage, 6709,
      GIR_Done,
    // Label 876: @56647
    GIM_Try, /*On fail goto*//*Label 877*/ GIMT_Encode4(56709), // Rule ID 7104 //
      GIM_CheckMemorySizeEqualToLLT, /*MI*/0, /*MMO*/0, /*OpIdx*/0,
      GIM_CheckAtomicOrdering, /*MI*/0, /*Order*/(uint8_t)AtomicOrdering::NotAtomic,
      GIM_CheckRegBankForClass, /*MI*/0, /*Op*/0, /*RC*/GIMT_Encode2(AMDGPU::SReg_64_XEXECRegClassID),
      GIM_CheckPointerToAny, /*MI*/0, /*Op*/1, /*SizeInBits*/0,
      GIM_CheckCxxInsnPredicate, /*MI*/0, /*FnId*/GIMT_Encode2(GICXXPred_MI_Predicate_smrd_load),
      GIM_CheckComplexPattern, /*MI*/0, /*Op*/1, /*Renderer*/GIMT_Encode2(0), GIMT_Encode2(GICP_gi_smrd_imm),
      // (ld:{ *:[i64] } (SMRDImm:{ *:[iPTR] } i64:{ *:[i64] }:$sbase, i32:{ *:[i32] }:$offset))<<P:Predicate_unindexedload>><<P:Predicate_load>><<P:Predicate_smrd_load>>  =>  (S_LOAD_DWORDX2_IMM:{ *:[i64] } ?:{ *:[i64] }:$sbase, ?:{ *:[i32] }:$offset, 0:{ *:[i32] })
      GIR_BuildMI, /*InsnID*/0, /*Opcode*/GIMT_Encode2(AMDGPU::S_LOAD_DWORDX2_IMM),
      GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/0, // DstI[sdst]
      GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/0, // sbase
      GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/1, // offset
      GIR_AddImm8, /*InsnID*/0, /*Imm*/0,
      GIR_MergeMemOperands, /*InsnID*/0, /*NumInsns*/1, /*MergeInsnID's*/0,
      GIR_ConstrainSelectedInstOperands, /*InsnID*/0,
      GIR_EraseFromParent, /*InsnID*/0,
      // GIR_Coverage, 7104,
      GIR_Done,
    // Label 877: @56709
    GIM_Try, /*On fail goto*//*Label 878*/ GIMT_Encode4(56774), // Rule ID 7105 //
      GIM_CheckFeatures, GIMT_Encode2(GIFBS_isGFX7Only),
      GIM_CheckMemorySizeEqualToLLT, /*MI*/0, /*MMO*/0, /*OpIdx*/0,
      GIM_CheckAtomicOrdering, /*MI*/0, /*Order*/(uint8_t)AtomicOrdering::NotAtomic,
      GIM_CheckRegBankForClass, /*MI*/0, /*Op*/0, /*RC*/GIMT_Encode2(AMDGPU::SReg_64_XEXECRegClassID),
      GIM_CheckPointerToAny, /*MI*/0, /*Op*/1, /*SizeInBits*/0,
      GIM_CheckCxxInsnPredicate, /*MI*/0, /*FnId*/GIMT_Encode2(GICXXPred_MI_Predicate_smrd_load),
      GIM_CheckComplexPattern, /*MI*/0, /*Op*/1, /*Renderer*/GIMT_Encode2(0), GIMT_Encode2(GICP_gi_smrd_imm32),
      // (ld:{ *:[i64] } (SMRDImm32:{ *:[iPTR] } i64:{ *:[i64] }:$sbase, i32:{ *:[i32] }:$offset))<<P:Predicate_unindexedload>><<P:Predicate_load>><<P:Predicate_smrd_load>>  =>  (S_LOAD_DWORDX2_IMM_ci:{ *:[i64] } ?:{ *:[i64] }:$sbase, ?:{ *:[i32] }:$offset, 0:{ *:[i32] })
      GIR_BuildMI, /*InsnID*/0, /*Opcode*/GIMT_Encode2(AMDGPU::S_LOAD_DWORDX2_IMM_ci),
      GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/0, // DstI[sdst]
      GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/0, // sbase
      GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/1, // offset
      GIR_AddImm8, /*InsnID*/0, /*Imm*/0,
      GIR_MergeMemOperands, /*InsnID*/0, /*NumInsns*/1, /*MergeInsnID's*/0,
      GIR_ConstrainSelectedInstOperands, /*InsnID*/0,
      GIR_EraseFromParent, /*InsnID*/0,
      // GIR_Coverage, 7105,
      GIR_Done,
    // Label 878: @56774
    GIM_Try, /*On fail goto*//*Label 879*/ GIMT_Encode4(56839), // Rule ID 7106 //
      GIM_CheckFeatures, GIMT_Encode2(GIFBS_isNotGFX9Plus),
      GIM_CheckMemorySizeEqualToLLT, /*MI*/0, /*MMO*/0, /*OpIdx*/0,
      GIM_CheckAtomicOrdering, /*MI*/0, /*Order*/(uint8_t)AtomicOrdering::NotAtomic,
      GIM_CheckRegBankForClass, /*MI*/0, /*Op*/0, /*RC*/GIMT_Encode2(AMDGPU::SReg_64_XEXECRegClassID),
      GIM_CheckPointerToAny, /*MI*/0, /*Op*/1, /*SizeInBits*/0,
      GIM_CheckCxxInsnPredicate, /*MI*/0, /*FnId*/GIMT_Encode2(GICXXPred_MI_Predicate_smrd_load),
      GIM_CheckComplexPattern, /*MI*/0, /*Op*/1, /*Renderer*/GIMT_Encode2(0), GIMT_Encode2(GICP_gi_smrd_sgpr),
      // (ld:{ *:[i64] } (SMRDSgpr:{ *:[iPTR] } i64:{ *:[i64] }:$sbase, i32:{ *:[i32] }:$soffset))<<P:Predicate_unindexedload>><<P:Predicate_load>><<P:Predicate_smrd_load>>  =>  (S_LOAD_DWORDX2_SGPR:{ *:[i64] } ?:{ *:[i64] }:$sbase, ?:{ *:[i32] }:$soffset, 0:{ *:[i32] })
      GIR_BuildMI, /*InsnID*/0, /*Opcode*/GIMT_Encode2(AMDGPU::S_LOAD_DWORDX2_SGPR),
      GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/0, // DstI[sdst]
      GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/0, // sbase
      GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/1, // soffset
      GIR_AddImm8, /*InsnID*/0, /*Imm*/0,
      GIR_MergeMemOperands, /*InsnID*/0, /*NumInsns*/1, /*MergeInsnID's*/0,
      GIR_ConstrainSelectedInstOperands, /*InsnID*/0,
      GIR_EraseFromParent, /*InsnID*/0,
      // GIR_Coverage, 7106,
      GIR_Done,
    // Label 879: @56839
    GIM_Try, /*On fail goto*//*Label 880*/ GIMT_Encode4(56907), // Rule ID 7107 //
      GIM_CheckFeatures, GIMT_Encode2(GIFBS_isGFX9Plus),
      GIM_CheckMemorySizeEqualToLLT, /*MI*/0, /*MMO*/0, /*OpIdx*/0,
      GIM_CheckAtomicOrdering, /*MI*/0, /*Order*/(uint8_t)AtomicOrdering::NotAtomic,
      GIM_CheckRegBankForClass, /*MI*/0, /*Op*/0, /*RC*/GIMT_Encode2(AMDGPU::SReg_64_XEXECRegClassID),
      GIM_CheckPointerToAny, /*MI*/0, /*Op*/1, /*SizeInBits*/0,
      GIM_CheckCxxInsnPredicate, /*MI*/0, /*FnId*/GIMT_Encode2(GICXXPred_MI_Predicate_smrd_load),
      GIM_CheckComplexPattern, /*MI*/0, /*Op*/1, /*Renderer*/GIMT_Encode2(0), GIMT_Encode2(GICP_gi_smrd_sgpr),
      // (ld:{ *:[i64] } (SMRDSgpr:{ *:[iPTR] } i64:{ *:[i64] }:$sbase, i32:{ *:[i32] }:$soffset))<<P:Predicate_unindexedload>><<P:Predicate_load>><<P:Predicate_smrd_load>>  =>  (S_LOAD_DWORDX2_SGPR_IMM:{ *:[i64] } ?:{ *:[i64] }:$sbase, ?:{ *:[i32] }:$soffset, 0:{ *:[i32] }, 0:{ *:[i32] })
      GIR_BuildMI, /*InsnID*/0, /*Opcode*/GIMT_Encode2(AMDGPU::S_LOAD_DWORDX2_SGPR_IMM),
      GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/0, // DstI[sdst]
      GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/0, // sbase
      GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/1, // soffset
      GIR_AddImm8, /*InsnID*/0, /*Imm*/0,
      GIR_AddImm8, /*InsnID*/0, /*Imm*/0,
      GIR_MergeMemOperands, /*InsnID*/0, /*NumInsns*/1, /*MergeInsnID's*/0,
      GIR_ConstrainSelectedInstOperands, /*InsnID*/0,
      GIR_EraseFromParent, /*InsnID*/0,
      // GIR_Coverage, 7107,
      GIR_Done,
    // Label 880: @56907
    GIM_Try, /*On fail goto*//*Label 881*/ GIMT_Encode4(56976), // Rule ID 3061 //
      GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasFlatGlobalInsts),
      GIM_CheckMemoryAddressSpace, /*MI*/0, /*MMO*/0, /*NumAddrSpace*/3, /*AddrSpace*/1, /*AddrSpace*/4, /*AddrSpace*/6,
      GIM_CheckAtomicOrdering, /*MI*/0, /*Order*/(uint8_t)AtomicOrdering::NotAtomic,
      GIM_CheckRegBankForClass, /*MI*/0, /*Op*/0, /*RC*/GIMT_Encode2(AMDGPU::AV_64RegClassID),
      GIM_CheckPointerToAny, /*MI*/0, /*Op*/1, /*SizeInBits*/0,
      GIM_CheckComplexPattern, /*MI*/0, /*Op*/1, /*Renderer*/GIMT_Encode2(0), GIMT_Encode2(GICP_gi_global_saddr),
      // (ld:{ *:[i64] } (GlobalSAddr:{ *:[iPTR] } SReg_64:{ *:[i64] }:$saddr, VGPR_32:{ *:[i32] }:$voffset, i32:{ *:[i32] }:$offset))<<P:Predicate_unindexedload>><<P:Predicate_load_global>>  =>  (GLOBAL_LOAD_DWORDX2_SADDR:{ *:[i64] } ?:{ *:[i64] }:$saddr, ?:{ *:[i32] }:$voffset, ?:{ *:[i32] }:$offset, 0:{ *:[i32] })
      GIR_BuildMI, /*InsnID*/0, /*Opcode*/GIMT_Encode2(AMDGPU::GLOBAL_LOAD_DWORDX2_SADDR),
      GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/0, // DstI[vdst]
      GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/0, // saddr
      GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/1, // voffset
      GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/2, // offset
      GIR_AddImm8, /*InsnID*/0, /*Imm*/0,
      GIR_MergeMemOperands, /*InsnID*/0, /*NumInsns*/1, /*MergeInsnID's*/0,
      GIR_ConstrainSelectedInstOperands, /*InsnID*/0,
      GIR_EraseFromParent, /*InsnID*/0,
      // GIR_Coverage, 3061,
      GIR_Done,
    // Label 881: @56976
    GIM_Try, /*On fail goto*//*Label 882*/ GIMT_Encode4(57040), // Rule ID 3060 //
      GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasFlatGlobalInsts),
      GIM_CheckMemoryAddressSpace, /*MI*/0, /*MMO*/0, /*NumAddrSpace*/3, /*AddrSpace*/1, /*AddrSpace*/4, /*AddrSpace*/6,
      GIM_CheckAtomicOrdering, /*MI*/0, /*Order*/(uint8_t)AtomicOrdering::NotAtomic,
      GIM_CheckRegBankForClass, /*MI*/0, /*Op*/0, /*RC*/GIMT_Encode2(AMDGPU::AV_64RegClassID),
      GIM_CheckPointerToAny, /*MI*/0, /*Op*/1, /*SizeInBits*/0,
      GIM_CheckComplexPattern, /*MI*/0, /*Op*/1, /*Renderer*/GIMT_Encode2(0), GIMT_Encode2(GICP_gi_global_offset),
      // (ld:{ *:[i64] } (GlobalOffset:{ *:[iPTR] } VReg_64:{ *:[i64] }:$vaddr, i32:{ *:[i32] }:$offset))<<P:Predicate_unindexedload>><<P:Predicate_load_global>>  =>  (GLOBAL_LOAD_DWORDX2:{ *:[i64] } ?:{ *:[i64] }:$vaddr, ?:{ *:[i32] }:$offset)
      GIR_BuildMI, /*InsnID*/0, /*Opcode*/GIMT_Encode2(AMDGPU::GLOBAL_LOAD_DWORDX2),
      GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/0, // DstI[vdst]
      GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/0, // vaddr
      GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/1, // offset
      GIR_AddImm8, /*InsnID*/0, /*Imm*/0,
      GIR_MergeMemOperands, /*InsnID*/0, /*NumInsns*/1, /*MergeInsnID's*/0,
      GIR_ConstrainSelectedInstOperands, /*InsnID*/0,
      GIR_EraseFromParent, /*InsnID*/0,
      // GIR_Coverage, 3060,
      GIR_Done,
    // Label 882: @57040
    GIM_Try, /*On fail goto*//*Label 883*/ GIMT_Encode4(57097), // Rule ID 7109 //
      GIM_CheckMemorySizeEqualToLLT, /*MI*/0, /*MMO*/0, /*OpIdx*/0,
      GIM_CheckAtomicOrdering, /*MI*/0, /*Order*/(uint8_t)AtomicOrdering::NotAtomic,
      GIM_CheckRegBankForClass, /*MI*/0, /*Op*/0, /*RC*/GIMT_Encode2(AMDGPU::SReg_64_XEXECRegClassID),
      // MIs[0] sbase
      GIM_CheckPointerToAny, /*MI*/0, /*Op*/1, /*SizeInBits*/64,
      GIM_CheckRegBankForClass, /*MI*/0, /*Op*/1, /*RC*/GIMT_Encode2(AMDGPU::SReg_64RegClassID),
      GIM_CheckCxxInsnPredicate, /*MI*/0, /*FnId*/GIMT_Encode2(GICXXPred_MI_Predicate_smrd_load),
      // (ld:{ *:[i64] } SReg_64:{ *:[i64] }:$sbase)<<P:Predicate_unindexedload>><<P:Predicate_load>><<P:Predicate_smrd_load>>  =>  (S_LOAD_DWORDX2_IMM:{ *:[i64] } i64:{ *:[i64] }:$sbase, 0:{ *:[i32] }, 0:{ *:[i32] })
      GIR_BuildMI, /*InsnID*/0, /*Opcode*/GIMT_Encode2(AMDGPU::S_LOAD_DWORDX2_IMM),
      GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/0, // DstI[sdst]
      GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/1, // sbase
      GIR_AddImm8, /*InsnID*/0, /*Imm*/0,
      GIR_AddImm8, /*InsnID*/0, /*Imm*/0,
      GIR_MergeMemOperands, /*InsnID*/0, /*NumInsns*/1, /*MergeInsnID's*/0,
      GIR_ConstrainSelectedInstOperands, /*InsnID*/0,
      GIR_EraseFromParent, /*InsnID*/0,
      // GIR_Coverage, 7109,
      GIR_Done,
    // Label 883: @57097
    GIM_Try, /*On fail goto*//*Label 884*/ GIMT_Encode4(57162), // Rule ID 2805 //
      GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasFlatAddressSpace),
      GIM_CheckMemoryAddressSpace, /*MI*/0, /*MMO*/0, /*NumAddrSpace*/4, /*AddrSpace*/0, /*AddrSpace*/1, /*AddrSpace*/4, /*AddrSpace*/6,
      GIM_CheckAtomicOrdering, /*MI*/0, /*Order*/(uint8_t)AtomicOrdering::NotAtomic,
      GIM_CheckRegBankForClass, /*MI*/0, /*Op*/0, /*RC*/GIMT_Encode2(AMDGPU::AV_64RegClassID),
      GIM_CheckPointerToAny, /*MI*/0, /*Op*/1, /*SizeInBits*/0,
      GIM_CheckComplexPattern, /*MI*/0, /*Op*/1, /*Renderer*/GIMT_Encode2(0), GIMT_Encode2(GICP_gi_flat_offset),
      // (ld:{ *:[i64] } (FlatOffset:{ *:[iPTR] } i64:{ *:[i64] }:$vaddr, i32:{ *:[i32] }:$offset))<<P:Predicate_unindexedload>><<P:Predicate_load_flat>>  =>  (FLAT_LOAD_DWORDX2:{ *:[i64] } ?:{ *:[i64] }:$vaddr, ?:{ *:[i32] }:$offset)
      GIR_BuildMI, /*InsnID*/0, /*Opcode*/GIMT_Encode2(AMDGPU::FLAT_LOAD_DWORDX2),
      GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/0, // DstI[vdst]
      GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/0, // vaddr
      GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/1, // offset
      GIR_AddImm8, /*InsnID*/0, /*Imm*/0,
      GIR_MergeMemOperands, /*InsnID*/0, /*NumInsns*/1, /*MergeInsnID's*/0,
      GIR_ConstrainSelectedInstOperands, /*InsnID*/0,
      GIR_EraseFromParent, /*InsnID*/0,
      // GIR_Coverage, 2805,
      GIR_Done,
    // Label 884: @57162
    GIM_Reject,
    // Label 818: @57163
    GIM_Try, /*On fail goto*//*Label 885*/ GIMT_Encode4(57233), // Rule ID 2480 //
      GIM_CheckFeatures, GIMT_Encode2(GIFBS_isGFX9Plus),
      GIM_CheckMemorySizeEqualToLLT, /*MI*/0, /*MMO*/0, /*OpIdx*/0,
      GIM_CheckAtomicOrdering, /*MI*/0, /*Order*/(uint8_t)AtomicOrdering::NotAtomic,
      GIM_CheckRegBankForClass, /*MI*/0, /*Op*/0, /*RC*/GIMT_Encode2(AMDGPU::SReg_32_XM0_XEXECRegClassID),
      GIM_CheckPointerToAny, /*MI*/0, /*Op*/1, /*SizeInBits*/0,
      GIM_CheckCxxInsnPredicate, /*MI*/0, /*FnId*/GIMT_Encode2(GICXXPred_MI_Predicate_smrd_load),
      GIM_CheckComplexPattern, /*MI*/0, /*Op*/1, /*Renderer*/GIMT_Encode2(0), GIMT_Encode2(GICP_gi_smrd_sgpr_imm),
      // (ld:{ *:[i32] } (SMRDSgprImm:{ *:[iPTR] } i64:{ *:[i64] }:$sbase, i32:{ *:[i32] }:$soffset, i32:{ *:[i32] }:$offset))<<P:Predicate_unindexedload>><<P:Predicate_load>><<P:Predicate_smrd_load>>  =>  (S_LOAD_DWORD_SGPR_IMM:{ *:[i32] } ?:{ *:[i64] }:$sbase, ?:{ *:[i32] }:$soffset, ?:{ *:[i32] }:$offset, 0:{ *:[i32] })
      GIR_BuildMI, /*InsnID*/0, /*Opcode*/GIMT_Encode2(AMDGPU::S_LOAD_DWORD_SGPR_IMM),
      GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/0, // DstI[sdst]
      GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/0, // sbase
      GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/1, // soffset
      GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/2, // offset
      GIR_AddImm8, /*InsnID*/0, /*Imm*/0,
      GIR_MergeMemOperands, /*InsnID*/0, /*NumInsns*/1, /*MergeInsnID's*/0,
      GIR_ConstrainSelectedInstOperands, /*InsnID*/0,
      GIR_EraseFromParent, /*InsnID*/0,
      // GIR_Coverage, 2480,
      GIR_Done,
    // Label 885: @57233
    GIM_Try, /*On fail goto*//*Label 886*/ GIMT_Encode4(57295), // Rule ID 2476 //
      GIM_CheckMemorySizeEqualToLLT, /*MI*/0, /*MMO*/0, /*OpIdx*/0,
      GIM_CheckAtomicOrdering, /*MI*/0, /*Order*/(uint8_t)AtomicOrdering::NotAtomic,
      GIM_CheckRegBankForClass, /*MI*/0, /*Op*/0, /*RC*/GIMT_Encode2(AMDGPU::SReg_32_XM0_XEXECRegClassID),
      GIM_CheckPointerToAny, /*MI*/0, /*Op*/1, /*SizeInBits*/0,
      GIM_CheckCxxInsnPredicate, /*MI*/0, /*FnId*/GIMT_Encode2(GICXXPred_MI_Predicate_smrd_load),
      GIM_CheckComplexPattern, /*MI*/0, /*Op*/1, /*Renderer*/GIMT_Encode2(0), GIMT_Encode2(GICP_gi_smrd_imm),
      // (ld:{ *:[i32] } (SMRDImm:{ *:[iPTR] } i64:{ *:[i64] }:$sbase, i32:{ *:[i32] }:$offset))<<P:Predicate_unindexedload>><<P:Predicate_load>><<P:Predicate_smrd_load>>  =>  (S_LOAD_DWORD_IMM:{ *:[i32] } ?:{ *:[i64] }:$sbase, ?:{ *:[i32] }:$offset, 0:{ *:[i32] })
      GIR_BuildMI, /*InsnID*/0, /*Opcode*/GIMT_Encode2(AMDGPU::S_LOAD_DWORD_IMM),
      GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/0, // DstI[sdst]
      GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/0, // sbase
      GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/1, // offset
      GIR_AddImm8, /*InsnID*/0, /*Imm*/0,
      GIR_MergeMemOperands, /*InsnID*/0, /*NumInsns*/1, /*MergeInsnID's*/0,
      GIR_ConstrainSelectedInstOperands, /*InsnID*/0,
      GIR_EraseFromParent, /*InsnID*/0,
      // GIR_Coverage, 2476,
      GIR_Done,
    // Label 886: @57295
    GIM_Try, /*On fail goto*//*Label 887*/ GIMT_Encode4(57360), // Rule ID 2477 //
      GIM_CheckFeatures, GIMT_Encode2(GIFBS_isGFX7Only),
      GIM_CheckMemorySizeEqualToLLT, /*MI*/0, /*MMO*/0, /*OpIdx*/0,
      GIM_CheckAtomicOrdering, /*MI*/0, /*Order*/(uint8_t)AtomicOrdering::NotAtomic,
      GIM_CheckRegBankForClass, /*MI*/0, /*Op*/0, /*RC*/GIMT_Encode2(AMDGPU::SReg_32_XM0_XEXECRegClassID),
      GIM_CheckPointerToAny, /*MI*/0, /*Op*/1, /*SizeInBits*/0,
      GIM_CheckCxxInsnPredicate, /*MI*/0, /*FnId*/GIMT_Encode2(GICXXPred_MI_Predicate_smrd_load),
      GIM_CheckComplexPattern, /*MI*/0, /*Op*/1, /*Renderer*/GIMT_Encode2(0), GIMT_Encode2(GICP_gi_smrd_imm32),
      // (ld:{ *:[i32] } (SMRDImm32:{ *:[iPTR] } i64:{ *:[i64] }:$sbase, i32:{ *:[i32] }:$offset))<<P:Predicate_unindexedload>><<P:Predicate_load>><<P:Predicate_smrd_load>>  =>  (S_LOAD_DWORD_IMM_ci:{ *:[i32] } ?:{ *:[i64] }:$sbase, ?:{ *:[i32] }:$offset, 0:{ *:[i32] })
      GIR_BuildMI, /*InsnID*/0, /*Opcode*/GIMT_Encode2(AMDGPU::S_LOAD_DWORD_IMM_ci),
      GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/0, // DstI[sdst]
      GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/0, // sbase
      GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/1, // offset
      GIR_AddImm8, /*InsnID*/0, /*Imm*/0,
      GIR_MergeMemOperands, /*InsnID*/0, /*NumInsns*/1, /*MergeInsnID's*/0,
      GIR_ConstrainSelectedInstOperands, /*InsnID*/0,
      GIR_EraseFromParent, /*InsnID*/0,
      // GIR_Coverage, 2477,
      GIR_Done,
    // Label 887: @57360
    GIM_Try, /*On fail goto*//*Label 888*/ GIMT_Encode4(57425), // Rule ID 2478 //
      GIM_CheckFeatures, GIMT_Encode2(GIFBS_isNotGFX9Plus),
      GIM_CheckMemorySizeEqualToLLT, /*MI*/0, /*MMO*/0, /*OpIdx*/0,
      GIM_CheckAtomicOrdering, /*MI*/0, /*Order*/(uint8_t)AtomicOrdering::NotAtomic,
      GIM_CheckRegBankForClass, /*MI*/0, /*Op*/0, /*RC*/GIMT_Encode2(AMDGPU::SReg_32_XM0_XEXECRegClassID),
      GIM_CheckPointerToAny, /*MI*/0, /*Op*/1, /*SizeInBits*/0,
      GIM_CheckCxxInsnPredicate, /*MI*/0, /*FnId*/GIMT_Encode2(GICXXPred_MI_Predicate_smrd_load),
      GIM_CheckComplexPattern, /*MI*/0, /*Op*/1, /*Renderer*/GIMT_Encode2(0), GIMT_Encode2(GICP_gi_smrd_sgpr),
      // (ld:{ *:[i32] } (SMRDSgpr:{ *:[iPTR] } i64:{ *:[i64] }:$sbase, i32:{ *:[i32] }:$soffset))<<P:Predicate_unindexedload>><<P:Predicate_load>><<P:Predicate_smrd_load>>  =>  (S_LOAD_DWORD_SGPR:{ *:[i32] } ?:{ *:[i64] }:$sbase, ?:{ *:[i32] }:$soffset, 0:{ *:[i32] })
      GIR_BuildMI, /*InsnID*/0, /*Opcode*/GIMT_Encode2(AMDGPU::S_LOAD_DWORD_SGPR),
      GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/0, // DstI[sdst]
      GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/0, // sbase
      GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/1, // soffset
      GIR_AddImm8, /*InsnID*/0, /*Imm*/0,
      GIR_MergeMemOperands, /*InsnID*/0, /*NumInsns*/1, /*MergeInsnID's*/0,
      GIR_ConstrainSelectedInstOperands, /*InsnID*/0,
      GIR_EraseFromParent, /*InsnID*/0,
      // GIR_Coverage, 2478,
      GIR_Done,
    // Label 888: @57425
    GIM_Try, /*On fail goto*//*Label 889*/ GIMT_Encode4(57493), // Rule ID 2479 //
      GIM_CheckFeatures, GIMT_Encode2(GIFBS_isGFX9Plus),
      GIM_CheckMemorySizeEqualToLLT, /*MI*/0, /*MMO*/0, /*OpIdx*/0,
      GIM_CheckAtomicOrdering, /*MI*/0, /*Order*/(uint8_t)AtomicOrdering::NotAtomic,
      GIM_CheckRegBankForClass, /*MI*/0, /*Op*/0, /*RC*/GIMT_Encode2(AMDGPU::SReg_32_XM0_XEXECRegClassID),
      GIM_CheckPointerToAny, /*MI*/0, /*Op*/1, /*SizeInBits*/0,
      GIM_CheckCxxInsnPredicate, /*MI*/0, /*FnId*/GIMT_Encode2(GICXXPred_MI_Predicate_smrd_load),
      GIM_CheckComplexPattern, /*MI*/0, /*Op*/1, /*Renderer*/GIMT_Encode2(0), GIMT_Encode2(GICP_gi_smrd_sgpr),
      // (ld:{ *:[i32] } (SMRDSgpr:{ *:[iPTR] } i64:{ *:[i64] }:$sbase, i32:{ *:[i32] }:$soffset))<<P:Predicate_unindexedload>><<P:Predicate_load>><<P:Predicate_smrd_load>>  =>  (S_LOAD_DWORD_SGPR_IMM:{ *:[i32] } ?:{ *:[i64] }:$sbase, ?:{ *:[i32] }:$soffset, 0:{ *:[i32] }, 0:{ *:[i32] })
      GIR_BuildMI, /*InsnID*/0, /*Opcode*/GIMT_Encode2(AMDGPU::S_LOAD_DWORD_SGPR_IMM),
      GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/0, // DstI[sdst]
      GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/0, // sbase
      GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/1, // soffset
      GIR_AddImm8, /*InsnID*/0, /*Imm*/0,
      GIR_AddImm8, /*InsnID*/0, /*Imm*/0,
      GIR_MergeMemOperands, /*InsnID*/0, /*NumInsns*/1, /*MergeInsnID's*/0,
      GIR_ConstrainSelectedInstOperands, /*InsnID*/0,
      GIR_EraseFromParent, /*InsnID*/0,
      // GIR_Coverage, 2479,
      GIR_Done,
    // Label 889: @57493
    GIM_Try, /*On fail goto*//*Label 890*/ GIMT_Encode4(57550), // Rule ID 2481 //
      GIM_CheckMemorySizeEqualToLLT, /*MI*/0, /*MMO*/0, /*OpIdx*/0,
      GIM_CheckAtomicOrdering, /*MI*/0, /*Order*/(uint8_t)AtomicOrdering::NotAtomic,
      GIM_CheckRegBankForClass, /*MI*/0, /*Op*/0, /*RC*/GIMT_Encode2(AMDGPU::SReg_32_XM0_XEXECRegClassID),
      // MIs[0] sbase
      GIM_CheckPointerToAny, /*MI*/0, /*Op*/1, /*SizeInBits*/64,
      GIM_CheckRegBankForClass, /*MI*/0, /*Op*/1, /*RC*/GIMT_Encode2(AMDGPU::SReg_64RegClassID),
      GIM_CheckCxxInsnPredicate, /*MI*/0, /*FnId*/GIMT_Encode2(GICXXPred_MI_Predicate_smrd_load),
      // (ld:{ *:[i32] } SReg_64:{ *:[i64] }:$sbase)<<P:Predicate_unindexedload>><<P:Predicate_load>><<P:Predicate_smrd_load>>  =>  (S_LOAD_DWORD_IMM:{ *:[i32] } i64:{ *:[i64] }:$sbase, 0:{ *:[i32] }, 0:{ *:[i32] })
      GIR_BuildMI, /*InsnID*/0, /*Opcode*/GIMT_Encode2(AMDGPU::S_LOAD_DWORD_IMM),
      GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/0, // DstI[sdst]
      GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/1, // sbase
      GIR_AddImm8, /*InsnID*/0, /*Imm*/0,
      GIR_AddImm8, /*InsnID*/0, /*Imm*/0,
      GIR_MergeMemOperands, /*InsnID*/0, /*NumInsns*/1, /*MergeInsnID's*/0,
      GIR_ConstrainSelectedInstOperands, /*InsnID*/0,
      GIR_EraseFromParent, /*InsnID*/0,
      // GIR_Coverage, 2481,
      GIR_Done,
    // Label 890: @57550
    GIM_Try, /*On fail goto*//*Label 891*/ GIMT_Encode4(57620), // Rule ID 5408 //
      GIM_CheckFeatures, GIMT_Encode2(GIFBS_DisableFlatScratch_HasUnrestrictedSOffset),
      GIM_CheckMemoryAddressSpace, /*MI*/0, /*MMO*/0, /*NumAddrSpace*/1, /*AddrSpace*/5,
      GIM_CheckAtomicOrdering, /*MI*/0, /*Order*/(uint8_t)AtomicOrdering::NotAtomic,
      GIM_CheckRegBankForClass, /*MI*/0, /*Op*/0, /*RC*/GIMT_Encode2(AMDGPU::AV_32RegClassID),
      GIM_CheckPointerToAny, /*MI*/0, /*Op*/1, /*SizeInBits*/0,
      GIM_CheckComplexPattern, /*MI*/0, /*Op*/1, /*Renderer*/GIMT_Encode2(0), GIMT_Encode2(GICP_gi_mubuf_scratch_offset),
      // (ld:{ *:[i32] } (MUBUFScratchOffset:{ *:[iPTR] } v4i32:{ *:[v4i32] }:$srsrc, i32:{ *:[i32] }:$soffset, i32:{ *:[i32] }:$offset))<<P:Predicate_unindexedload>><<P:Predicate_load_private>>  =>  (BUFFER_LOAD_DWORD_OFFSET:{ *:[i32] } ?:{ *:[v4i32] }:$srsrc, ?:{ *:[i32] }:$soffset, ?:{ *:[i32] }:$offset, 0:{ *:[i32] }, 0:{ *:[i1] })
      GIR_BuildMI, /*InsnID*/0, /*Opcode*/GIMT_Encode2(AMDGPU::BUFFER_LOAD_DWORD_OFFSET),
      GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/0, // DstI[vdata]
      GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/0, // srsrc
      GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/1, // soffset
      GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/2, // offset
      GIR_AddImm8, /*InsnID*/0, /*Imm*/0,
      GIR_AddImm8, /*InsnID*/0, /*Imm*/0,
      GIR_MergeMemOperands, /*InsnID*/0, /*NumInsns*/1, /*MergeInsnID's*/0,
      GIR_ConstrainSelectedInstOperands, /*InsnID*/0,
      GIR_EraseFromParent, /*InsnID*/0,
      // GIR_Coverage, 5408,
      GIR_Done,
    // Label 891: @57620
    GIM_Try, /*On fail goto*//*Label 892*/ GIMT_Encode4(57690), // Rule ID 5410 //
      GIM_CheckFeatures, GIMT_Encode2(GIFBS_DisableFlatScratch),
      GIM_CheckMemoryAddressSpace, /*MI*/0, /*MMO*/0, /*NumAddrSpace*/1, /*AddrSpace*/5,
      GIM_CheckAtomicOrdering, /*MI*/0, /*Order*/(uint8_t)AtomicOrdering::NotAtomic,
      GIM_CheckRegBankForClass, /*MI*/0, /*Op*/0, /*RC*/GIMT_Encode2(AMDGPU::AV_32RegClassID),
      GIM_CheckPointerToAny, /*MI*/0, /*Op*/1, /*SizeInBits*/0,
      GIM_CheckComplexPattern, /*MI*/0, /*Op*/1, /*Renderer*/GIMT_Encode2(0), GIMT_Encode2(GICP_gi_mubuf_scratch_offset),
      // (ld:{ *:[i32] } (MUBUFScratchOffset:{ *:[iPTR] } v4i32:{ *:[v4i32] }:$srsrc, i32:{ *:[i32] }:$soffset, i32:{ *:[i32] }:$offset))<<P:Predicate_unindexedload>><<P:Predicate_load_private>>  =>  (BUFFER_LOAD_DWORD_VBUFFER_OFFSET:{ *:[i32] } ?:{ *:[v4i32] }:$srsrc, ?:{ *:[i32] }:$soffset, ?:{ *:[i32] }:$offset, 0:{ *:[i32] }, 0:{ *:[i1] })
      GIR_BuildMI, /*InsnID*/0, /*Opcode*/GIMT_Encode2(AMDGPU::BUFFER_LOAD_DWORD_VBUFFER_OFFSET),
      GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/0, // DstI[vdata]
      GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/0, // srsrc
      GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/1, // soffset
      GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/2, // offset
      GIR_AddImm8, /*InsnID*/0, /*Imm*/0,
      GIR_AddImm8, /*InsnID*/0, /*Imm*/0,
      GIR_MergeMemOperands, /*InsnID*/0, /*NumInsns*/1, /*MergeInsnID's*/0,
      GIR_ConstrainSelectedInstOperands, /*InsnID*/0,
      GIR_EraseFromParent, /*InsnID*/0,
      // GIR_Coverage, 5410,
      GIR_Done,
    // Label 892: @57690
    GIM_Try, /*On fail goto*//*Label 893*/ GIMT_Encode4(57757), // Rule ID 3460 //
      GIM_CheckFeatures, GIMT_Encode2(GIFBS_EnableFlatScratch_HasFlatScratchInsts_HasFlatScratchSVSMode),
      GIM_CheckMemoryAddressSpace, /*MI*/0, /*MMO*/0, /*NumAddrSpace*/1, /*AddrSpace*/5,
      GIM_CheckAtomicOrdering, /*MI*/0, /*Order*/(uint8_t)AtomicOrdering::NotAtomic,
      GIM_CheckRegBankForClass, /*MI*/0, /*Op*/0, /*RC*/GIMT_Encode2(AMDGPU::AV_32RegClassID),
      GIM_CheckPointerToAny, /*MI*/0, /*Op*/1, /*SizeInBits*/0,
      GIM_CheckComplexPattern, /*MI*/0, /*Op*/1, /*Renderer*/GIMT_Encode2(0), GIMT_Encode2(GICP_gi_flat_scratch_svaddr),
      // (ld:{ *:[i32] } (ScratchSVAddr:{ *:[iPTR] } VGPR_32:{ *:[i32] }:$vaddr, SGPR_32:{ *:[i32] }:$saddr, i32:{ *:[i32] }:$offset))<<P:Predicate_unindexedload>><<P:Predicate_load_private>>  =>  (SCRATCH_LOAD_DWORD_SVS:{ *:[i32] } ?:{ *:[i32] }:$vaddr, ?:{ *:[i32] }:$saddr, ?:{ *:[i32] }:$offset, 0:{ *:[i32] })
      GIR_BuildMI, /*InsnID*/0, /*Opcode*/GIMT_Encode2(AMDGPU::SCRATCH_LOAD_DWORD_SVS),
      GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/0, // DstI[vdst]
      GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/0, // vaddr
      GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/1, // saddr
      GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/2, // offset
      GIR_AddImm8, /*InsnID*/0, /*Imm*/0,
      GIR_MergeMemOperands, /*InsnID*/0, /*NumInsns*/1, /*MergeInsnID's*/0,
      GIR_ConstrainSelectedInstOperands, /*InsnID*/0,
      GIR_EraseFromParent, /*InsnID*/0,
      // GIR_Coverage, 3460,
      GIR_Done,
    // Label 893: @57757
    GIM_Try, /*On fail goto*//*Label 894*/ GIMT_Encode4(57819), // Rule ID 3459 //
      GIM_CheckFeatures, GIMT_Encode2(GIFBS_EnableFlatScratch_HasFlatScratchInsts),
      GIM_CheckMemoryAddressSpace, /*MI*/0, /*MMO*/0, /*NumAddrSpace*/1, /*AddrSpace*/5,
      GIM_CheckAtomicOrdering, /*MI*/0, /*Order*/(uint8_t)AtomicOrdering::NotAtomic,
      GIM_CheckRegBankForClass, /*MI*/0, /*Op*/0, /*RC*/GIMT_Encode2(AMDGPU::AV_32RegClassID),
      GIM_CheckPointerToAny, /*MI*/0, /*Op*/1, /*SizeInBits*/0,
      GIM_CheckComplexPattern, /*MI*/0, /*Op*/1, /*Renderer*/GIMT_Encode2(0), GIMT_Encode2(GICP_gi_flat_scratch_saddr),
      // (ld:{ *:[i32] } (ScratchSAddr:{ *:[iPTR] } SGPR_32:{ *:[i32] }:$saddr, i32:{ *:[i32] }:$offset))<<P:Predicate_unindexedload>><<P:Predicate_load_private>>  =>  (SCRATCH_LOAD_DWORD_SADDR:{ *:[i32] } ?:{ *:[i32] }:$saddr, ?:{ *:[i32] }:$offset)
      GIR_BuildMI, /*InsnID*/0, /*Opcode*/GIMT_Encode2(AMDGPU::SCRATCH_LOAD_DWORD_SADDR),
      GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/0, // DstI[vdst]
      GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/0, // saddr
      GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/1, // offset
      GIR_AddImm8, /*InsnID*/0, /*Imm*/0,
      GIR_MergeMemOperands, /*InsnID*/0, /*NumInsns*/1, /*MergeInsnID's*/0,
      GIR_ConstrainSelectedInstOperands, /*InsnID*/0,
      GIR_EraseFromParent, /*InsnID*/0,
      // GIR_Coverage, 3459,
      GIR_Done,
    // Label 894: @57819
    GIM_Try, /*On fail goto*//*Label 895*/ GIMT_Encode4(57881), // Rule ID 3458 //
      GIM_CheckFeatures, GIMT_Encode2(GIFBS_EnableFlatScratch_HasFlatScratchInsts),
      GIM_CheckMemoryAddressSpace, /*MI*/0, /*MMO*/0, /*NumAddrSpace*/1, /*AddrSpace*/5,
      GIM_CheckAtomicOrdering, /*MI*/0, /*Order*/(uint8_t)AtomicOrdering::NotAtomic,
      GIM_CheckRegBankForClass, /*MI*/0, /*Op*/0, /*RC*/GIMT_Encode2(AMDGPU::AV_32RegClassID),
      GIM_CheckPointerToAny, /*MI*/0, /*Op*/1, /*SizeInBits*/0,
      GIM_CheckComplexPattern, /*MI*/0, /*Op*/1, /*Renderer*/GIMT_Encode2(0), GIMT_Encode2(GICP_gi_flat_scratch_offset),
      // (ld:{ *:[i32] } (ScratchOffset:{ *:[iPTR] } VGPR_32:{ *:[i32] }:$vaddr, i32:{ *:[i32] }:$offset))<<P:Predicate_unindexedload>><<P:Predicate_load_private>>  =>  (SCRATCH_LOAD_DWORD:{ *:[i32] } ?:{ *:[i32] }:$vaddr, ?:{ *:[i32] }:$offset)
      GIR_BuildMI, /*InsnID*/0, /*Opcode*/GIMT_Encode2(AMDGPU::SCRATCH_LOAD_DWORD),
      GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/0, // DstI[vdst]
      GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/0, // vaddr
      GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/1, // offset
      GIR_AddImm8, /*InsnID*/0, /*Imm*/0,
      GIR_MergeMemOperands, /*InsnID*/0, /*NumInsns*/1, /*MergeInsnID's*/0,
      GIR_ConstrainSelectedInstOperands, /*InsnID*/0,
      GIR_EraseFromParent, /*InsnID*/0,
      // GIR_Coverage, 3458,
      GIR_Done,
    // Label 895: @57881
    GIM_Try, /*On fail goto*//*Label 896*/ GIMT_Encode4(57958), // Rule ID 3704 //
      GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasUnrestrictedSOffset),
      GIM_CheckMemoryAddressSpace, /*MI*/0, /*MMO*/0, /*NumAddrSpace*/3, /*AddrSpace*/1, /*AddrSpace*/4, /*AddrSpace*/6,
      GIM_CheckAtomicOrdering, /*MI*/0, /*Order*/(uint8_t)AtomicOrdering::NotAtomic,
      GIM_CheckRegBankForClass, /*MI*/0, /*Op*/0, /*RC*/GIMT_Encode2(AMDGPU::AV_32RegClassID),
      GIM_CheckPointerToAny, /*MI*/0, /*Op*/1, /*SizeInBits*/0,
      GIM_CheckComplexPattern, /*MI*/0, /*Op*/1, /*Renderer*/GIMT_Encode2(0), GIMT_Encode2(GICP_gi_mubuf_addr64),
      // (ld:{ *:[i32] } (MUBUFAddr64:{ *:[iPTR] } v4i32:{ *:[v4i32] }:$srsrc, i64:{ *:[i64] }:$vaddr, i32:{ *:[i32] }:$soffset, i32:{ *:[i32] }:$offset))<<P:Predicate_unindexedload>><<P:Predicate_load_global>>  =>  (BUFFER_LOAD_DWORD_ADDR64:{ *:[i32] } i64:{ *:[i64] }:$vaddr, v4i32:{ *:[v4i32] }:$srsrc, i32:{ *:[i32] }:$soffset, i32:{ *:[i32] }:$offset)
      GIR_BuildMI, /*InsnID*/0, /*Opcode*/GIMT_Encode2(AMDGPU::BUFFER_LOAD_DWORD_ADDR64),
      GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/0, // DstI[vdata]
      GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/1, // vaddr
      GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/0, // srsrc
      GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/2, // soffset
      GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/3, // offset
      GIR_AddImm8, /*InsnID*/0, /*Imm*/0,
      GIR_AddImm8, /*InsnID*/0, /*Imm*/0,
      GIR_MergeMemOperands, /*InsnID*/0, /*NumInsns*/1, /*MergeInsnID's*/0,
      GIR_ConstrainSelectedInstOperands, /*InsnID*/0,
      GIR_EraseFromParent, /*InsnID*/0,
      // GIR_Coverage, 3704,
      GIR_Done,
    // Label 896: @57958
    GIM_Try, /*On fail goto*//*Label 897*/ GIMT_Encode4(58032), // Rule ID 3706 //
      GIM_CheckMemoryAddressSpace, /*MI*/0, /*MMO*/0, /*NumAddrSpace*/3, /*AddrSpace*/1, /*AddrSpace*/4, /*AddrSpace*/6,
      GIM_CheckAtomicOrdering, /*MI*/0, /*Order*/(uint8_t)AtomicOrdering::NotAtomic,
      GIM_CheckRegBankForClass, /*MI*/0, /*Op*/0, /*RC*/GIMT_Encode2(AMDGPU::AV_32RegClassID),
      GIM_CheckPointerToAny, /*MI*/0, /*Op*/1, /*SizeInBits*/0,
      GIM_CheckComplexPattern, /*MI*/0, /*Op*/1, /*Renderer*/GIMT_Encode2(0), GIMT_Encode2(GICP_gi_mubuf_addr64),
      // (ld:{ *:[i32] } (MUBUFAddr64:{ *:[iPTR] } v4i32:{ *:[v4i32] }:$srsrc, i64:{ *:[i64] }:$vaddr, i32:{ *:[i32] }:$soffset, i32:{ *:[i32] }:$offset))<<P:Predicate_unindexedload>><<P:Predicate_load_global>>  =>  (BUFFER_LOAD_DWORD_VBUFFER_ADDR64:{ *:[i32] } i64:{ *:[i64] }:$vaddr, v4i32:{ *:[v4i32] }:$srsrc, i32:{ *:[i32] }:$soffset, i32:{ *:[i32] }:$offset)
      GIR_BuildMI, /*InsnID*/0, /*Opcode*/GIMT_Encode2(AMDGPU::BUFFER_LOAD_DWORD_VBUFFER_ADDR64),
      GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/0, // DstI[vdata]
      GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/1, // vaddr
      GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/0, // srsrc
      GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/2, // soffset
      GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/3, // offset
      GIR_AddImm8, /*InsnID*/0, /*Imm*/0,
      GIR_AddImm8, /*InsnID*/0, /*Imm*/0,
      GIR_MergeMemOperands, /*InsnID*/0, /*NumInsns*/1, /*MergeInsnID's*/0,
      GIR_ConstrainSelectedInstOperands, /*InsnID*/0,
      GIR_EraseFromParent, /*InsnID*/0,
      // GIR_Coverage, 3706,
      GIR_Done,
    // Label 897: @58032
    GIM_Try, /*On fail goto*//*Label 898*/ GIMT_Encode4(58107), // Rule ID 5407 //
      GIM_CheckFeatures, GIMT_Encode2(GIFBS_DisableFlatScratch_HasUnrestrictedSOffset),
      GIM_CheckMemoryAddressSpace, /*MI*/0, /*MMO*/0, /*NumAddrSpace*/1, /*AddrSpace*/5,
      GIM_CheckAtomicOrdering, /*MI*/0, /*Order*/(uint8_t)AtomicOrdering::NotAtomic,
      GIM_CheckRegBankForClass, /*MI*/0, /*Op*/0, /*RC*/GIMT_Encode2(AMDGPU::AV_32RegClassID),
      GIM_CheckPointerToAny, /*MI*/0, /*Op*/1, /*SizeInBits*/0,
      GIM_CheckComplexPattern, /*MI*/0, /*Op*/1, /*Renderer*/GIMT_Encode2(0), GIMT_Encode2(GICP_gi_mubuf_scratch_offen),
      // (ld:{ *:[i32] } (MUBUFScratchOffen:{ *:[iPTR] } v4i32:{ *:[v4i32] }:$srsrc, i32:{ *:[i32] }:$vaddr, i32:{ *:[i32] }:$soffset, i32:{ *:[i32] }:$offset))<<P:Predicate_unindexedload>><<P:Predicate_load_private>>  =>  (BUFFER_LOAD_DWORD_OFFEN:{ *:[i32] } ?:{ *:[i32] }:$vaddr, ?:{ *:[v4i32] }:$srsrc, ?:{ *:[i32] }:$soffset, ?:{ *:[i32] }:$offset, 0:{ *:[i32] }, 0:{ *:[i1] })
      GIR_BuildMI, /*InsnID*/0, /*Opcode*/GIMT_Encode2(AMDGPU::BUFFER_LOAD_DWORD_OFFEN),
      GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/0, // DstI[vdata]
      GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/1, // vaddr
      GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/0, // srsrc
      GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/2, // soffset
      GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/3, // offset
      GIR_AddImm8, /*InsnID*/0, /*Imm*/0,
      GIR_AddImm8, /*InsnID*/0, /*Imm*/0,
      GIR_MergeMemOperands, /*InsnID*/0, /*NumInsns*/1, /*MergeInsnID's*/0,
      GIR_ConstrainSelectedInstOperands, /*InsnID*/0,
      GIR_EraseFromParent, /*InsnID*/0,
      // GIR_Coverage, 5407,
      GIR_Done,
    // Label 898: @58107
    GIM_Try, /*On fail goto*//*Label 899*/ GIMT_Encode4(58182), // Rule ID 5409 //
      GIM_CheckFeatures, GIMT_Encode2(GIFBS_DisableFlatScratch),
      GIM_CheckMemoryAddressSpace, /*MI*/0, /*MMO*/0, /*NumAddrSpace*/1, /*AddrSpace*/5,
      GIM_CheckAtomicOrdering, /*MI*/0, /*Order*/(uint8_t)AtomicOrdering::NotAtomic,
      GIM_CheckRegBankForClass, /*MI*/0, /*Op*/0, /*RC*/GIMT_Encode2(AMDGPU::AV_32RegClassID),
      GIM_CheckPointerToAny, /*MI*/0, /*Op*/1, /*SizeInBits*/0,
      GIM_CheckComplexPattern, /*MI*/0, /*Op*/1, /*Renderer*/GIMT_Encode2(0), GIMT_Encode2(GICP_gi_mubuf_scratch_offen),
      // (ld:{ *:[i32] } (MUBUFScratchOffen:{ *:[iPTR] } v4i32:{ *:[v4i32] }:$srsrc, i32:{ *:[i32] }:$vaddr, i32:{ *:[i32] }:$soffset, i32:{ *:[i32] }:$offset))<<P:Predicate_unindexedload>><<P:Predicate_load_private>>  =>  (BUFFER_LOAD_DWORD_VBUFFER_OFFEN:{ *:[i32] } ?:{ *:[i32] }:$vaddr, ?:{ *:[v4i32] }:$srsrc, ?:{ *:[i32] }:$soffset, ?:{ *:[i32] }:$offset, 0:{ *:[i32] }, 0:{ *:[i1] })
      GIR_BuildMI, /*InsnID*/0, /*Opcode*/GIMT_Encode2(AMDGPU::BUFFER_LOAD_DWORD_VBUFFER_OFFEN),
      GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/0, // DstI[vdata]
      GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/1, // vaddr
      GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/0, // srsrc
      GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/2, // soffset
      GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/3, // offset
      GIR_AddImm8, /*InsnID*/0, /*Imm*/0,
      GIR_AddImm8, /*InsnID*/0, /*Imm*/0,
      GIR_MergeMemOperands, /*InsnID*/0, /*NumInsns*/1, /*MergeInsnID's*/0,
      GIR_ConstrainSelectedInstOperands, /*InsnID*/0,
      GIR_EraseFromParent, /*InsnID*/0,
      // GIR_Coverage, 5409,
      GIR_Done,
    // Label 899: @58182
    GIM_Try, /*On fail goto*//*Label 900*/ GIMT_Encode4(58254), // Rule ID 3703 //
      GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasUnrestrictedSOffset),
      GIM_CheckMemoryAddressSpace, /*MI*/0, /*MMO*/0, /*NumAddrSpace*/3, /*AddrSpace*/1, /*AddrSpace*/4, /*AddrSpace*/6,
      GIM_CheckAtomicOrdering, /*MI*/0, /*Order*/(uint8_t)AtomicOrdering::NotAtomic,
      GIM_CheckRegBankForClass, /*MI*/0, /*Op*/0, /*RC*/GIMT_Encode2(AMDGPU::AV_32RegClassID),
      GIM_CheckPointerToAny, /*MI*/0, /*Op*/1, /*SizeInBits*/0,
      GIM_CheckComplexPattern, /*MI*/0, /*Op*/1, /*Renderer*/GIMT_Encode2(0), GIMT_Encode2(GICP_gi_mubuf_offset),
      // (ld:{ *:[i32] } (MUBUFOffset:{ *:[iPTR] } v4i32:{ *:[v4i32] }:$srsrc, i32:{ *:[i32] }:$soffset, i32:{ *:[i32] }:$offset))<<P:Predicate_unindexedload>><<P:Predicate_load_global>>  =>  (BUFFER_LOAD_DWORD_OFFSET:{ *:[i32] } v4i32:{ *:[v4i32] }:$srsrc, i32:{ *:[i32] }:$soffset, i32:{ *:[i32] }:$offset)
      GIR_BuildMI, /*InsnID*/0, /*Opcode*/GIMT_Encode2(AMDGPU::BUFFER_LOAD_DWORD_OFFSET),
      GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/0, // DstI[vdata]
      GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/0, // srsrc
      GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/1, // soffset
      GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/2, // offset
      GIR_AddImm8, /*InsnID*/0, /*Imm*/0,
      GIR_AddImm8, /*InsnID*/0, /*Imm*/0,
      GIR_MergeMemOperands, /*InsnID*/0, /*NumInsns*/1, /*MergeInsnID's*/0,
      GIR_ConstrainSelectedInstOperands, /*InsnID*/0,
      GIR_EraseFromParent, /*InsnID*/0,
      // GIR_Coverage, 3703,
      GIR_Done,
    // Label 900: @58254
    GIM_Try, /*On fail goto*//*Label 901*/ GIMT_Encode4(58323), // Rule ID 3705 //
      GIM_CheckMemoryAddressSpace, /*MI*/0, /*MMO*/0, /*NumAddrSpace*/3, /*AddrSpace*/1, /*AddrSpace*/4, /*AddrSpace*/6,
      GIM_CheckAtomicOrdering, /*MI*/0, /*Order*/(uint8_t)AtomicOrdering::NotAtomic,
      GIM_CheckRegBankForClass, /*MI*/0, /*Op*/0, /*RC*/GIMT_Encode2(AMDGPU::AV_32RegClassID),
      GIM_CheckPointerToAny, /*MI*/0, /*Op*/1, /*SizeInBits*/0,
      GIM_CheckComplexPattern, /*MI*/0, /*Op*/1, /*Renderer*/GIMT_Encode2(0), GIMT_Encode2(GICP_gi_mubuf_offset),
      // (ld:{ *:[i32] } (MUBUFOffset:{ *:[iPTR] } v4i32:{ *:[v4i32] }:$srsrc, i32:{ *:[i32] }:$soffset, i32:{ *:[i32] }:$offset))<<P:Predicate_unindexedload>><<P:Predicate_load_global>>  =>  (BUFFER_LOAD_DWORD_VBUFFER_OFFSET:{ *:[i32] } v4i32:{ *:[v4i32] }:$srsrc, i32:{ *:[i32] }:$soffset, i32:{ *:[i32] }:$offset)
      GIR_BuildMI, /*InsnID*/0, /*Opcode*/GIMT_Encode2(AMDGPU::BUFFER_LOAD_DWORD_VBUFFER_OFFSET),
      GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/0, // DstI[vdata]
      GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/0, // srsrc
      GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/1, // soffset
      GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/2, // offset
      GIR_AddImm8, /*InsnID*/0, /*Imm*/0,
      GIR_AddImm8, /*InsnID*/0, /*Imm*/0,
      GIR_MergeMemOperands, /*InsnID*/0, /*NumInsns*/1, /*MergeInsnID's*/0,
      GIR_ConstrainSelectedInstOperands, /*InsnID*/0,
      GIR_EraseFromParent, /*InsnID*/0,
      // GIR_Coverage, 3705,
      GIR_Done,
    // Label 901: @58323
    GIM_Try, /*On fail goto*//*Label 902*/ GIMT_Encode4(58389), // Rule ID 6599 //
      GIM_CheckFeatures, GIMT_Encode2(GIFBS_LDSRequiresM0Init),
      GIM_CheckMemorySizeEqualToLLT, /*MI*/0, /*MMO*/0, /*OpIdx*/0,
      GIM_CheckMemoryAddressSpace, /*MI*/0, /*MMO*/0, /*NumAddrSpace*/1, /*AddrSpace*/3,
      GIM_CheckAtomicOrdering, /*MI*/0, /*Order*/(uint8_t)AtomicOrdering::NotAtomic,
      GIM_CheckRegBankForClass, /*MI*/0, /*Op*/0, /*RC*/GIMT_Encode2(AMDGPU::AV_32RegClassID),
      GIM_CheckPointerToAny, /*MI*/0, /*Op*/1, /*SizeInBits*/0,
      GIM_CheckComplexPattern, /*MI*/0, /*Op*/1, /*Renderer*/GIMT_Encode2(0), GIMT_Encode2(GICP_gi_ds_1addr_1offset),
      // (AMDGPUld_glue:{ *:[i32] } (DS1Addr1Offset:{ *:[iPTR] } i32:{ *:[i32] }:$ptr, i32:{ *:[i32] }:$offset))<<P:Predicate_unindexedload_glue>><<P:Predicate_load_glue>><<P:Predicate_load_local_m0>>  =>  (DS_READ_B32:{ *:[i32] } ?:{ *:[i32] }:$ptr, offset:{ *:[i32] }:$offset, 0:{ *:[i1] })
      GIR_BuildMI, /*InsnID*/0, /*Opcode*/GIMT_Encode2(AMDGPU::DS_READ_B32),
      GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/0, // DstI[vdst]
      GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/0, // ptr
      GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/1, // offset
      GIR_AddImm8, /*InsnID*/0, /*Imm*/0,
      GIR_MergeMemOperands, /*InsnID*/0, /*NumInsns*/1, /*MergeInsnID's*/0,
      GIR_ConstrainSelectedInstOperands, /*InsnID*/0,
      GIR_EraseFromParent, /*InsnID*/0,
      // GIR_Coverage, 6599,
      GIR_Done,
    // Label 902: @58389
    GIM_Try, /*On fail goto*//*Label 903*/ GIMT_Encode4(58451), // Rule ID 6600 //
      GIM_CheckFeatures, GIMT_Encode2(GIFBS_NotLDSRequiresM0Init),
      GIM_CheckMemoryAddressSpace, /*MI*/0, /*MMO*/0, /*NumAddrSpace*/1, /*AddrSpace*/3,
      GIM_CheckAtomicOrdering, /*MI*/0, /*Order*/(uint8_t)AtomicOrdering::NotAtomic,
      GIM_CheckRegBankForClass, /*MI*/0, /*Op*/0, /*RC*/GIMT_Encode2(AMDGPU::AV_32RegClassID),
      GIM_CheckPointerToAny, /*MI*/0, /*Op*/1, /*SizeInBits*/0,
      GIM_CheckComplexPattern, /*MI*/0, /*Op*/1, /*Renderer*/GIMT_Encode2(0), GIMT_Encode2(GICP_gi_ds_1addr_1offset),
      // (ld:{ *:[i32] } (DS1Addr1Offset:{ *:[iPTR] } i32:{ *:[i32] }:$ptr, i32:{ *:[i32] }:$offset))<<P:Predicate_unindexedload>><<P:Predicate_load_local>>  =>  (DS_READ_B32_gfx9:{ *:[i32] } ?:{ *:[i32] }:$ptr, offset:{ *:[i32] }:$offset, 0:{ *:[i1] })
      GIR_BuildMI, /*InsnID*/0, /*Opcode*/GIMT_Encode2(AMDGPU::DS_READ_B32_gfx9),
      GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/0, // DstI[vdst]
      GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/0, // ptr
      GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/1, // offset
      GIR_AddImm8, /*InsnID*/0, /*Imm*/0,
      GIR_MergeMemOperands, /*InsnID*/0, /*NumInsns*/1, /*MergeInsnID's*/0,
      GIR_ConstrainSelectedInstOperands, /*InsnID*/0,
      GIR_EraseFromParent, /*InsnID*/0,
      // GIR_Coverage, 6600,
      GIR_Done,
    // Label 903: @58451
    GIM_Try, /*On fail goto*//*Label 904*/ GIMT_Encode4(58520), // Rule ID 3013 //
      GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasFlatGlobalInsts),
      GIM_CheckMemoryAddressSpace, /*MI*/0, /*MMO*/0, /*NumAddrSpace*/3, /*AddrSpace*/1, /*AddrSpace*/4, /*AddrSpace*/6,
      GIM_CheckAtomicOrdering, /*MI*/0, /*Order*/(uint8_t)AtomicOrdering::NotAtomic,
      GIM_CheckRegBankForClass, /*MI*/0, /*Op*/0, /*RC*/GIMT_Encode2(AMDGPU::AV_32RegClassID),
      GIM_CheckPointerToAny, /*MI*/0, /*Op*/1, /*SizeInBits*/0,
      GIM_CheckComplexPattern, /*MI*/0, /*Op*/1, /*Renderer*/GIMT_Encode2(0), GIMT_Encode2(GICP_gi_global_saddr),
      // (ld:{ *:[i32] } (GlobalSAddr:{ *:[iPTR] } SReg_64:{ *:[i64] }:$saddr, VGPR_32:{ *:[i32] }:$voffset, i32:{ *:[i32] }:$offset))<<P:Predicate_unindexedload>><<P:Predicate_load_global>>  =>  (GLOBAL_LOAD_DWORD_SADDR:{ *:[i32] } ?:{ *:[i64] }:$saddr, ?:{ *:[i32] }:$voffset, ?:{ *:[i32] }:$offset, 0:{ *:[i32] })
      GIR_BuildMI, /*InsnID*/0, /*Opcode*/GIMT_Encode2(AMDGPU::GLOBAL_LOAD_DWORD_SADDR),
      GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/0, // DstI[vdst]
      GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/0, // saddr
      GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/1, // voffset
      GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/2, // offset
      GIR_AddImm8, /*InsnID*/0, /*Imm*/0,
      GIR_MergeMemOperands, /*InsnID*/0, /*NumInsns*/1, /*MergeInsnID's*/0,
      GIR_ConstrainSelectedInstOperands, /*InsnID*/0,
      GIR_EraseFromParent, /*InsnID*/0,
      // GIR_Coverage, 3013,
      GIR_Done,
    // Label 904: @58520
    GIM_Try, /*On fail goto*//*Label 905*/ GIMT_Encode4(58584), // Rule ID 3012 //
      GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasFlatGlobalInsts),
      GIM_CheckMemoryAddressSpace, /*MI*/0, /*MMO*/0, /*NumAddrSpace*/3, /*AddrSpace*/1, /*AddrSpace*/4, /*AddrSpace*/6,
      GIM_CheckAtomicOrdering, /*MI*/0, /*Order*/(uint8_t)AtomicOrdering::NotAtomic,
      GIM_CheckRegBankForClass, /*MI*/0, /*Op*/0, /*RC*/GIMT_Encode2(AMDGPU::AV_32RegClassID),
      GIM_CheckPointerToAny, /*MI*/0, /*Op*/1, /*SizeInBits*/0,
      GIM_CheckComplexPattern, /*MI*/0, /*Op*/1, /*Renderer*/GIMT_Encode2(0), GIMT_Encode2(GICP_gi_global_offset),
      // (ld:{ *:[i32] } (GlobalOffset:{ *:[iPTR] } VReg_64:{ *:[i64] }:$vaddr, i32:{ *:[i32] }:$offset))<<P:Predicate_unindexedload>><<P:Predicate_load_global>>  =>  (GLOBAL_LOAD_DWORD:{ *:[i32] } ?:{ *:[i64] }:$vaddr, ?:{ *:[i32] }:$offset)
      GIR_BuildMI, /*InsnID*/0, /*Opcode*/GIMT_Encode2(AMDGPU::GLOBAL_LOAD_DWORD),
      GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/0, // DstI[vdst]
      GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/0, // vaddr
      GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/1, // offset
      GIR_AddImm8, /*InsnID*/0, /*Imm*/0,
      GIR_MergeMemOperands, /*InsnID*/0, /*NumInsns*/1, /*MergeInsnID's*/0,
      GIR_ConstrainSelectedInstOperands, /*InsnID*/0,
      GIR_EraseFromParent, /*InsnID*/0,
      // GIR_Coverage, 3012,
      GIR_Done,
    // Label 905: @58584
    GIM_Try, /*On fail goto*//*Label 906*/ GIMT_Encode4(58649), // Rule ID 2780 //
      GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasFlatAddressSpace),
      GIM_CheckMemoryAddressSpace, /*MI*/0, /*MMO*/0, /*NumAddrSpace*/4, /*AddrSpace*/0, /*AddrSpace*/1, /*AddrSpace*/4, /*AddrSpace*/6,
      GIM_CheckAtomicOrdering, /*MI*/0, /*Order*/(uint8_t)AtomicOrdering::NotAtomic,
      GIM_CheckRegBankForClass, /*MI*/0, /*Op*/0, /*RC*/GIMT_Encode2(AMDGPU::AV_32RegClassID),
      GIM_CheckPointerToAny, /*MI*/0, /*Op*/1, /*SizeInBits*/0,
      GIM_CheckComplexPattern, /*MI*/0, /*Op*/1, /*Renderer*/GIMT_Encode2(0), GIMT_Encode2(GICP_gi_flat_offset),
      // (ld:{ *:[i32] } (FlatOffset:{ *:[iPTR] } i64:{ *:[i64] }:$vaddr, i32:{ *:[i32] }:$offset))<<P:Predicate_unindexedload>><<P:Predicate_load_flat>>  =>  (FLAT_LOAD_DWORD:{ *:[i32] } ?:{ *:[i64] }:$vaddr, ?:{ *:[i32] }:$offset)
      GIR_BuildMI, /*InsnID*/0, /*Opcode*/GIMT_Encode2(AMDGPU::FLAT_LOAD_DWORD),
      GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/0, // DstI[vdst]
      GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/0, // vaddr
      GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/1, // offset
      GIR_AddImm8, /*InsnID*/0, /*Imm*/0,
      GIR_MergeMemOperands, /*InsnID*/0, /*NumInsns*/1, /*MergeInsnID's*/0,
      GIR_ConstrainSelectedInstOperands, /*InsnID*/0,
      GIR_EraseFromParent, /*InsnID*/0,
      // GIR_Coverage, 2780,
      GIR_Done,
    // Label 906: @58649
    GIM_Reject,
    // Label 819: @58650
    GIM_Try, /*On fail goto*//*Label 907*/ GIMT_Encode4(58720), // Rule ID 2486 //
      GIM_CheckFeatures, GIMT_Encode2(GIFBS_isGFX9Plus),
      GIM_CheckMemorySizeEqualToLLT, /*MI*/0, /*MMO*/0, /*OpIdx*/0,
      GIM_CheckAtomicOrdering, /*MI*/0, /*Order*/(uint8_t)AtomicOrdering::NotAtomic,
      GIM_CheckRegBankForClass, /*MI*/0, /*Op*/0, /*RC*/GIMT_Encode2(AMDGPU::SReg_32_XM0_XEXECRegClassID),
      GIM_CheckPointerToAny, /*MI*/0, /*Op*/1, /*SizeInBits*/0,
      GIM_CheckCxxInsnPredicate, /*MI*/0, /*FnId*/GIMT_Encode2(GICXXPred_MI_Predicate_smrd_load),
      GIM_CheckComplexPattern, /*MI*/0, /*Op*/1, /*Renderer*/GIMT_Encode2(0), GIMT_Encode2(GICP_gi_smrd_sgpr_imm),
      // (ld:{ *:[i32] } (SMRDSgprImm:{ *:[iPTR] } i64:{ *:[i64] }:$sbase, i32:{ *:[i32] }:$soffset, i32:{ *:[i32] }:$offset))<<P:Predicate_unindexedload>><<P:Predicate_load>><<P:Predicate_smrd_load>>  =>  (S_LOAD_DWORD_SGPR_IMM:{ *:[i32] } ?:{ *:[i64] }:$sbase, ?:{ *:[i32] }:$soffset, ?:{ *:[i32] }:$offset, 0:{ *:[i32] })
      GIR_BuildMI, /*InsnID*/0, /*Opcode*/GIMT_Encode2(AMDGPU::S_LOAD_DWORD_SGPR_IMM),
      GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/0, // DstI[sdst]
      GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/0, // sbase
      GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/1, // soffset
      GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/2, // offset
      GIR_AddImm8, /*InsnID*/0, /*Imm*/0,
      GIR_MergeMemOperands, /*InsnID*/0, /*NumInsns*/1, /*MergeInsnID's*/0,
      GIR_ConstrainSelectedInstOperands, /*InsnID*/0,
      GIR_EraseFromParent, /*InsnID*/0,
      // GIR_Coverage, 2486,
      GIR_Done,
    // Label 907: @58720
    GIM_Try, /*On fail goto*//*Label 908*/ GIMT_Encode4(58782), // Rule ID 2482 //
      GIM_CheckMemorySizeEqualToLLT, /*MI*/0, /*MMO*/0, /*OpIdx*/0,
      GIM_CheckAtomicOrdering, /*MI*/0, /*Order*/(uint8_t)AtomicOrdering::NotAtomic,
      GIM_CheckRegBankForClass, /*MI*/0, /*Op*/0, /*RC*/GIMT_Encode2(AMDGPU::SReg_32_XM0_XEXECRegClassID),
      GIM_CheckPointerToAny, /*MI*/0, /*Op*/1, /*SizeInBits*/0,
      GIM_CheckCxxInsnPredicate, /*MI*/0, /*FnId*/GIMT_Encode2(GICXXPred_MI_Predicate_smrd_load),
      GIM_CheckComplexPattern, /*MI*/0, /*Op*/1, /*Renderer*/GIMT_Encode2(0), GIMT_Encode2(GICP_gi_smrd_imm),
      // (ld:{ *:[i32] } (SMRDImm:{ *:[iPTR] } i64:{ *:[i64] }:$sbase, i32:{ *:[i32] }:$offset))<<P:Predicate_unindexedload>><<P:Predicate_load>><<P:Predicate_smrd_load>>  =>  (S_LOAD_DWORD_IMM:{ *:[i32] } ?:{ *:[i64] }:$sbase, ?:{ *:[i32] }:$offset, 0:{ *:[i32] })
      GIR_BuildMI, /*InsnID*/0, /*Opcode*/GIMT_Encode2(AMDGPU::S_LOAD_DWORD_IMM),
      GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/0, // DstI[sdst]
      GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/0, // sbase
      GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/1, // offset
      GIR_AddImm8, /*InsnID*/0, /*Imm*/0,
      GIR_MergeMemOperands, /*InsnID*/0, /*NumInsns*/1, /*MergeInsnID's*/0,
      GIR_ConstrainSelectedInstOperands, /*InsnID*/0,
      GIR_EraseFromParent, /*InsnID*/0,
      // GIR_Coverage, 2482,
      GIR_Done,
    // Label 908: @58782
    GIM_Try, /*On fail goto*//*Label 909*/ GIMT_Encode4(58847), // Rule ID 2483 //
      GIM_CheckFeatures, GIMT_Encode2(GIFBS_isGFX7Only),
      GIM_CheckMemorySizeEqualToLLT, /*MI*/0, /*MMO*/0, /*OpIdx*/0,
      GIM_CheckAtomicOrdering, /*MI*/0, /*Order*/(uint8_t)AtomicOrdering::NotAtomic,
      GIM_CheckRegBankForClass, /*MI*/0, /*Op*/0, /*RC*/GIMT_Encode2(AMDGPU::SReg_32_XM0_XEXECRegClassID),
      GIM_CheckPointerToAny, /*MI*/0, /*Op*/1, /*SizeInBits*/0,
      GIM_CheckCxxInsnPredicate, /*MI*/0, /*FnId*/GIMT_Encode2(GICXXPred_MI_Predicate_smrd_load),
      GIM_CheckComplexPattern, /*MI*/0, /*Op*/1, /*Renderer*/GIMT_Encode2(0), GIMT_Encode2(GICP_gi_smrd_imm32),
      // (ld:{ *:[i32] } (SMRDImm32:{ *:[iPTR] } i64:{ *:[i64] }:$sbase, i32:{ *:[i32] }:$offset))<<P:Predicate_unindexedload>><<P:Predicate_load>><<P:Predicate_smrd_load>>  =>  (S_LOAD_DWORD_IMM_ci:{ *:[i32] } ?:{ *:[i64] }:$sbase, ?:{ *:[i32] }:$offset, 0:{ *:[i32] })
      GIR_BuildMI, /*InsnID*/0, /*Opcode*/GIMT_Encode2(AMDGPU::S_LOAD_DWORD_IMM_ci),
      GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/0, // DstI[sdst]
      GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/0, // sbase
      GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/1, // offset
      GIR_AddImm8, /*InsnID*/0, /*Imm*/0,
      GIR_MergeMemOperands, /*InsnID*/0, /*NumInsns*/1, /*MergeInsnID's*/0,
      GIR_ConstrainSelectedInstOperands, /*InsnID*/0,
      GIR_EraseFromParent, /*InsnID*/0,
      // GIR_Coverage, 2483,
      GIR_Done,
    // Label 909: @58847
    GIM_Try, /*On fail goto*//*Label 910*/ GIMT_Encode4(58912), // Rule ID 2484 //
      GIM_CheckFeatures, GIMT_Encode2(GIFBS_isNotGFX9Plus),
      GIM_CheckMemorySizeEqualToLLT, /*MI*/0, /*MMO*/0, /*OpIdx*/0,
      GIM_CheckAtomicOrdering, /*MI*/0, /*Order*/(uint8_t)AtomicOrdering::NotAtomic,
      GIM_CheckRegBankForClass, /*MI*/0, /*Op*/0, /*RC*/GIMT_Encode2(AMDGPU::SReg_32_XM0_XEXECRegClassID),
      GIM_CheckPointerToAny, /*MI*/0, /*Op*/1, /*SizeInBits*/0,
      GIM_CheckCxxInsnPredicate, /*MI*/0, /*FnId*/GIMT_Encode2(GICXXPred_MI_Predicate_smrd_load),
      GIM_CheckComplexPattern, /*MI*/0, /*Op*/1, /*Renderer*/GIMT_Encode2(0), GIMT_Encode2(GICP_gi_smrd_sgpr),
      // (ld:{ *:[i32] } (SMRDSgpr:{ *:[iPTR] } i64:{ *:[i64] }:$sbase, i32:{ *:[i32] }:$soffset))<<P:Predicate_unindexedload>><<P:Predicate_load>><<P:Predicate_smrd_load>>  =>  (S_LOAD_DWORD_SGPR:{ *:[i32] } ?:{ *:[i64] }:$sbase, ?:{ *:[i32] }:$soffset, 0:{ *:[i32] })
      GIR_BuildMI, /*InsnID*/0, /*Opcode*/GIMT_Encode2(AMDGPU::S_LOAD_DWORD_SGPR),
      GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/0, // DstI[sdst]
      GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/0, // sbase
      GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/1, // soffset
      GIR_AddImm8, /*InsnID*/0, /*Imm*/0,
      GIR_MergeMemOperands, /*InsnID*/0, /*NumInsns*/1, /*MergeInsnID's*/0,
      GIR_ConstrainSelectedInstOperands, /*InsnID*/0,
      GIR_EraseFromParent, /*InsnID*/0,
      // GIR_Coverage, 2484,
      GIR_Done,
    // Label 910: @58912
    GIM_Try, /*On fail goto*//*Label 911*/ GIMT_Encode4(58980), // Rule ID 2485 //
      GIM_CheckFeatures, GIMT_Encode2(GIFBS_isGFX9Plus),
      GIM_CheckMemorySizeEqualToLLT, /*MI*/0, /*MMO*/0, /*OpIdx*/0,
      GIM_CheckAtomicOrdering, /*MI*/0, /*Order*/(uint8_t)AtomicOrdering::NotAtomic,
      GIM_CheckRegBankForClass, /*MI*/0, /*Op*/0, /*RC*/GIMT_Encode2(AMDGPU::SReg_32_XM0_XEXECRegClassID),
      GIM_CheckPointerToAny, /*MI*/0, /*Op*/1, /*SizeInBits*/0,
      GIM_CheckCxxInsnPredicate, /*MI*/0, /*FnId*/GIMT_Encode2(GICXXPred_MI_Predicate_smrd_load),
      GIM_CheckComplexPattern, /*MI*/0, /*Op*/1, /*Renderer*/GIMT_Encode2(0), GIMT_Encode2(GICP_gi_smrd_sgpr),
      // (ld:{ *:[i32] } (SMRDSgpr:{ *:[iPTR] } i64:{ *:[i64] }:$sbase, i32:{ *:[i32] }:$soffset))<<P:Predicate_unindexedload>><<P:Predicate_load>><<P:Predicate_smrd_load>>  =>  (S_LOAD_DWORD_SGPR_IMM:{ *:[i32] } ?:{ *:[i64] }:$sbase, ?:{ *:[i32] }:$soffset, 0:{ *:[i32] }, 0:{ *:[i32] })
      GIR_BuildMI, /*InsnID*/0, /*Opcode*/GIMT_Encode2(AMDGPU::S_LOAD_DWORD_SGPR_IMM),
      GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/0, // DstI[sdst]
      GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/0, // sbase
      GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/1, // soffset
      GIR_AddImm8, /*InsnID*/0, /*Imm*/0,
      GIR_AddImm8, /*InsnID*/0, /*Imm*/0,
      GIR_MergeMemOperands, /*InsnID*/0, /*NumInsns*/1, /*MergeInsnID's*/0,
      GIR_ConstrainSelectedInstOperands, /*InsnID*/0,
      GIR_EraseFromParent, /*InsnID*/0,
      // GIR_Coverage, 2485,
      GIR_Done,
    // Label 911: @58980
    GIM_Try, /*On fail goto*//*Label 912*/ GIMT_Encode4(59037), // Rule ID 2487 //
      GIM_CheckMemorySizeEqualToLLT, /*MI*/0, /*MMO*/0, /*OpIdx*/0,
      GIM_CheckAtomicOrdering, /*MI*/0, /*Order*/(uint8_t)AtomicOrdering::NotAtomic,
      GIM_CheckRegBankForClass, /*MI*/0, /*Op*/0, /*RC*/GIMT_Encode2(AMDGPU::SReg_32_XM0_XEXECRegClassID),
      // MIs[0] sbase
      GIM_CheckPointerToAny, /*MI*/0, /*Op*/1, /*SizeInBits*/64,
      GIM_CheckRegBankForClass, /*MI*/0, /*Op*/1, /*RC*/GIMT_Encode2(AMDGPU::SReg_64RegClassID),
      GIM_CheckCxxInsnPredicate, /*MI*/0, /*FnId*/GIMT_Encode2(GICXXPred_MI_Predicate_smrd_load),
      // (ld:{ *:[i32] } SReg_64:{ *:[i64] }:$sbase)<<P:Predicate_unindexedload>><<P:Predicate_load>><<P:Predicate_smrd_load>>  =>  (S_LOAD_DWORD_IMM:{ *:[i32] } i64:{ *:[i64] }:$sbase, 0:{ *:[i32] }, 0:{ *:[i32] })
      GIR_BuildMI, /*InsnID*/0, /*Opcode*/GIMT_Encode2(AMDGPU::S_LOAD_DWORD_IMM),
      GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/0, // DstI[sdst]
      GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/1, // sbase
      GIR_AddImm8, /*InsnID*/0, /*Imm*/0,
      GIR_AddImm8, /*InsnID*/0, /*Imm*/0,
      GIR_MergeMemOperands, /*InsnID*/0, /*NumInsns*/1, /*MergeInsnID's*/0,
      GIR_ConstrainSelectedInstOperands, /*InsnID*/0,
      GIR_EraseFromParent, /*InsnID*/0,
      // GIR_Coverage, 2487,
      GIR_Done,
    // Label 912: @59037
    GIM_Try, /*On fail goto*//*Label 913*/ GIMT_Encode4(59107), // Rule ID 5412 //
      GIM_CheckFeatures, GIMT_Encode2(GIFBS_DisableFlatScratch_HasUnrestrictedSOffset),
      GIM_CheckMemoryAddressSpace, /*MI*/0, /*MMO*/0, /*NumAddrSpace*/1, /*AddrSpace*/5,
      GIM_CheckAtomicOrdering, /*MI*/0, /*Order*/(uint8_t)AtomicOrdering::NotAtomic,
      GIM_CheckRegBankForClass, /*MI*/0, /*Op*/0, /*RC*/GIMT_Encode2(AMDGPU::AV_32RegClassID),
      GIM_CheckPointerToAny, /*MI*/0, /*Op*/1, /*SizeInBits*/0,
      GIM_CheckComplexPattern, /*MI*/0, /*Op*/1, /*Renderer*/GIMT_Encode2(0), GIMT_Encode2(GICP_gi_mubuf_scratch_offset),
      // (ld:{ *:[i32] } (MUBUFScratchOffset:{ *:[iPTR] } v4i32:{ *:[v4i32] }:$srsrc, i32:{ *:[i32] }:$soffset, i32:{ *:[i32] }:$offset))<<P:Predicate_unindexedload>><<P:Predicate_load_private>>  =>  (BUFFER_LOAD_DWORD_OFFSET:{ *:[i32] } ?:{ *:[v4i32] }:$srsrc, ?:{ *:[i32] }:$soffset, ?:{ *:[i32] }:$offset, 0:{ *:[i32] }, 0:{ *:[i1] })
      GIR_BuildMI, /*InsnID*/0, /*Opcode*/GIMT_Encode2(AMDGPU::BUFFER_LOAD_DWORD_OFFSET),
      GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/0, // DstI[vdata]
      GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/0, // srsrc
      GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/1, // soffset
      GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/2, // offset
      GIR_AddImm8, /*InsnID*/0, /*Imm*/0,
      GIR_AddImm8, /*InsnID*/0, /*Imm*/0,
      GIR_MergeMemOperands, /*InsnID*/0, /*NumInsns*/1, /*MergeInsnID's*/0,
      GIR_ConstrainSelectedInstOperands, /*InsnID*/0,
      GIR_EraseFromParent, /*InsnID*/0,
      // GIR_Coverage, 5412,
      GIR_Done,
    // Label 913: @59107
    GIM_Try, /*On fail goto*//*Label 914*/ GIMT_Encode4(59177), // Rule ID 5414 //
      GIM_CheckFeatures, GIMT_Encode2(GIFBS_DisableFlatScratch),
      GIM_CheckMemoryAddressSpace, /*MI*/0, /*MMO*/0, /*NumAddrSpace*/1, /*AddrSpace*/5,
      GIM_CheckAtomicOrdering, /*MI*/0, /*Order*/(uint8_t)AtomicOrdering::NotAtomic,
      GIM_CheckRegBankForClass, /*MI*/0, /*Op*/0, /*RC*/GIMT_Encode2(AMDGPU::AV_32RegClassID),
      GIM_CheckPointerToAny, /*MI*/0, /*Op*/1, /*SizeInBits*/0,
      GIM_CheckComplexPattern, /*MI*/0, /*Op*/1, /*Renderer*/GIMT_Encode2(0), GIMT_Encode2(GICP_gi_mubuf_scratch_offset),
      // (ld:{ *:[i32] } (MUBUFScratchOffset:{ *:[iPTR] } v4i32:{ *:[v4i32] }:$srsrc, i32:{ *:[i32] }:$soffset, i32:{ *:[i32] }:$offset))<<P:Predicate_unindexedload>><<P:Predicate_load_private>>  =>  (BUFFER_LOAD_DWORD_VBUFFER_OFFSET:{ *:[i32] } ?:{ *:[v4i32] }:$srsrc, ?:{ *:[i32] }:$soffset, ?:{ *:[i32] }:$offset, 0:{ *:[i32] }, 0:{ *:[i1] })
      GIR_BuildMI, /*InsnID*/0, /*Opcode*/GIMT_Encode2(AMDGPU::BUFFER_LOAD_DWORD_VBUFFER_OFFSET),
      GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/0, // DstI[vdata]
      GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/0, // srsrc
      GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/1, // soffset
      GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/2, // offset
      GIR_AddImm8, /*InsnID*/0, /*Imm*/0,
      GIR_AddImm8, /*InsnID*/0, /*Imm*/0,
      GIR_MergeMemOperands, /*InsnID*/0, /*NumInsns*/1, /*MergeInsnID's*/0,
      GIR_ConstrainSelectedInstOperands, /*InsnID*/0,
      GIR_EraseFromParent, /*InsnID*/0,
      // GIR_Coverage, 5414,
      GIR_Done,
    // Label 914: @59177
    GIM_Try, /*On fail goto*//*Label 915*/ GIMT_Encode4(59244), // Rule ID 3466 //
      GIM_CheckFeatures, GIMT_Encode2(GIFBS_EnableFlatScratch_HasFlatScratchInsts_HasFlatScratchSVSMode),
      GIM_CheckMemoryAddressSpace, /*MI*/0, /*MMO*/0, /*NumAddrSpace*/1, /*AddrSpace*/5,
      GIM_CheckAtomicOrdering, /*MI*/0, /*Order*/(uint8_t)AtomicOrdering::NotAtomic,
      GIM_CheckRegBankForClass, /*MI*/0, /*Op*/0, /*RC*/GIMT_Encode2(AMDGPU::AV_32RegClassID),
      GIM_CheckPointerToAny, /*MI*/0, /*Op*/1, /*SizeInBits*/0,
      GIM_CheckComplexPattern, /*MI*/0, /*Op*/1, /*Renderer*/GIMT_Encode2(0), GIMT_Encode2(GICP_gi_flat_scratch_svaddr),
      // (ld:{ *:[i32] } (ScratchSVAddr:{ *:[iPTR] } VGPR_32:{ *:[i32] }:$vaddr, SGPR_32:{ *:[i32] }:$saddr, i32:{ *:[i32] }:$offset))<<P:Predicate_unindexedload>><<P:Predicate_load_private>>  =>  (SCRATCH_LOAD_DWORD_SVS:{ *:[i32] } ?:{ *:[i32] }:$vaddr, ?:{ *:[i32] }:$saddr, ?:{ *:[i32] }:$offset, 0:{ *:[i32] })
      GIR_BuildMI, /*InsnID*/0, /*Opcode*/GIMT_Encode2(AMDGPU::SCRATCH_LOAD_DWORD_SVS),
      GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/0, // DstI[vdst]
      GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/0, // vaddr
      GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/1, // saddr
      GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/2, // offset
      GIR_AddImm8, /*InsnID*/0, /*Imm*/0,
      GIR_MergeMemOperands, /*InsnID*/0, /*NumInsns*/1, /*MergeInsnID's*/0,
      GIR_ConstrainSelectedInstOperands, /*InsnID*/0,
      GIR_EraseFromParent, /*InsnID*/0,
      // GIR_Coverage, 3466,
      GIR_Done,
    // Label 915: @59244
    GIM_Try, /*On fail goto*//*Label 916*/ GIMT_Encode4(59306), // Rule ID 3465 //
      GIM_CheckFeatures, GIMT_Encode2(GIFBS_EnableFlatScratch_HasFlatScratchInsts),
      GIM_CheckMemoryAddressSpace, /*MI*/0, /*MMO*/0, /*NumAddrSpace*/1, /*AddrSpace*/5,
      GIM_CheckAtomicOrdering, /*MI*/0, /*Order*/(uint8_t)AtomicOrdering::NotAtomic,
      GIM_CheckRegBankForClass, /*MI*/0, /*Op*/0, /*RC*/GIMT_Encode2(AMDGPU::AV_32RegClassID),
      GIM_CheckPointerToAny, /*MI*/0, /*Op*/1, /*SizeInBits*/0,
      GIM_CheckComplexPattern, /*MI*/0, /*Op*/1, /*Renderer*/GIMT_Encode2(0), GIMT_Encode2(GICP_gi_flat_scratch_saddr),
      // (ld:{ *:[i32] } (ScratchSAddr:{ *:[iPTR] } SGPR_32:{ *:[i32] }:$saddr, i32:{ *:[i32] }:$offset))<<P:Predicate_unindexedload>><<P:Predicate_load_private>>  =>  (SCRATCH_LOAD_DWORD_SADDR:{ *:[i32] } ?:{ *:[i32] }:$saddr, ?:{ *:[i32] }:$offset)
      GIR_BuildMI, /*InsnID*/0, /*Opcode*/GIMT_Encode2(AMDGPU::SCRATCH_LOAD_DWORD_SADDR),
      GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/0, // DstI[vdst]
      GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/0, // saddr
      GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/1, // offset
      GIR_AddImm8, /*InsnID*/0, /*Imm*/0,
      GIR_MergeMemOperands, /*InsnID*/0, /*NumInsns*/1, /*MergeInsnID's*/0,
      GIR_ConstrainSelectedInstOperands, /*InsnID*/0,
      GIR_EraseFromParent, /*InsnID*/0,
      // GIR_Coverage, 3465,
      GIR_Done,
    // Label 916: @59306
    GIM_Try, /*On fail goto*//*Label 917*/ GIMT_Encode4(59368), // Rule ID 3464 //
      GIM_CheckFeatures, GIMT_Encode2(GIFBS_EnableFlatScratch_HasFlatScratchInsts),
      GIM_CheckMemoryAddressSpace, /*MI*/0, /*MMO*/0, /*NumAddrSpace*/1, /*AddrSpace*/5,
      GIM_CheckAtomicOrdering, /*MI*/0, /*Order*/(uint8_t)AtomicOrdering::NotAtomic,
      GIM_CheckRegBankForClass, /*MI*/0, /*Op*/0, /*RC*/GIMT_Encode2(AMDGPU::AV_32RegClassID),
      GIM_CheckPointerToAny, /*MI*/0, /*Op*/1, /*SizeInBits*/0,
      GIM_CheckComplexPattern, /*MI*/0, /*Op*/1, /*Renderer*/GIMT_Encode2(0), GIMT_Encode2(GICP_gi_flat_scratch_offset),
      // (ld:{ *:[i32] } (ScratchOffset:{ *:[iPTR] } VGPR_32:{ *:[i32] }:$vaddr, i32:{ *:[i32] }:$offset))<<P:Predicate_unindexedload>><<P:Predicate_load_private>>  =>  (SCRATCH_LOAD_DWORD:{ *:[i32] } ?:{ *:[i32] }:$vaddr, ?:{ *:[i32] }:$offset)
      GIR_BuildMI, /*InsnID*/0, /*Opcode*/GIMT_Encode2(AMDGPU::SCRATCH_LOAD_DWORD),
      GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/0, // DstI[vdst]
      GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/0, // vaddr
      GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/1, // offset
      GIR_AddImm8, /*InsnID*/0, /*Imm*/0,
      GIR_MergeMemOperands, /*InsnID*/0, /*NumInsns*/1, /*MergeInsnID's*/0,
      GIR_ConstrainSelectedInstOperands, /*InsnID*/0,
      GIR_EraseFromParent, /*InsnID*/0,
      // GIR_Coverage, 3464,
      GIR_Done,
    // Label 917: @59368
    GIM_Try, /*On fail goto*//*Label 918*/ GIMT_Encode4(59445), // Rule ID 3708 //
      GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasUnrestrictedSOffset),
      GIM_CheckMemoryAddressSpace, /*MI*/0, /*MMO*/0, /*NumAddrSpace*/3, /*AddrSpace*/1, /*AddrSpace*/4, /*AddrSpace*/6,
      GIM_CheckAtomicOrdering, /*MI*/0, /*Order*/(uint8_t)AtomicOrdering::NotAtomic,
      GIM_CheckRegBankForClass, /*MI*/0, /*Op*/0, /*RC*/GIMT_Encode2(AMDGPU::AV_32RegClassID),
      GIM_CheckPointerToAny, /*MI*/0, /*Op*/1, /*SizeInBits*/0,
      GIM_CheckComplexPattern, /*MI*/0, /*Op*/1, /*Renderer*/GIMT_Encode2(0), GIMT_Encode2(GICP_gi_mubuf_addr64),
      // (ld:{ *:[i32] } (MUBUFAddr64:{ *:[iPTR] } v4i32:{ *:[v4i32] }:$srsrc, i64:{ *:[i64] }:$vaddr, i32:{ *:[i32] }:$soffset, i32:{ *:[i32] }:$offset))<<P:Predicate_unindexedload>><<P:Predicate_load_global>>  =>  (BUFFER_LOAD_DWORD_ADDR64:{ *:[i32] } i64:{ *:[i64] }:$vaddr, v4i32:{ *:[v4i32] }:$srsrc, i32:{ *:[i32] }:$soffset, i32:{ *:[i32] }:$offset)
      GIR_BuildMI, /*InsnID*/0, /*Opcode*/GIMT_Encode2(AMDGPU::BUFFER_LOAD_DWORD_ADDR64),
      GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/0, // DstI[vdata]
      GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/1, // vaddr
      GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/0, // srsrc
      GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/2, // soffset
      GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/3, // offset
      GIR_AddImm8, /*InsnID*/0, /*Imm*/0,
      GIR_AddImm8, /*InsnID*/0, /*Imm*/0,
      GIR_MergeMemOperands, /*InsnID*/0, /*NumInsns*/1, /*MergeInsnID's*/0,
      GIR_ConstrainSelectedInstOperands, /*InsnID*/0,
      GIR_EraseFromParent, /*InsnID*/0,
      // GIR_Coverage, 3708,
      GIR_Done,
    // Label 918: @59445
    GIM_Try, /*On fail goto*//*Label 919*/ GIMT_Encode4(59519), // Rule ID 3710 //
      GIM_CheckMemoryAddressSpace, /*MI*/0, /*MMO*/0, /*NumAddrSpace*/3, /*AddrSpace*/1, /*AddrSpace*/4, /*AddrSpace*/6,
      GIM_CheckAtomicOrdering, /*MI*/0, /*Order*/(uint8_t)AtomicOrdering::NotAtomic,
      GIM_CheckRegBankForClass, /*MI*/0, /*Op*/0, /*RC*/GIMT_Encode2(AMDGPU::AV_32RegClassID),
      GIM_CheckPointerToAny, /*MI*/0, /*Op*/1, /*SizeInBits*/0,
      GIM_CheckComplexPattern, /*MI*/0, /*Op*/1, /*Renderer*/GIMT_Encode2(0), GIMT_Encode2(GICP_gi_mubuf_addr64),
      // (ld:{ *:[i32] } (MUBUFAddr64:{ *:[iPTR] } v4i32:{ *:[v4i32] }:$srsrc, i64:{ *:[i64] }:$vaddr, i32:{ *:[i32] }:$soffset, i32:{ *:[i32] }:$offset))<<P:Predicate_unindexedload>><<P:Predicate_load_global>>  =>  (BUFFER_LOAD_DWORD_VBUFFER_ADDR64:{ *:[i32] } i64:{ *:[i64] }:$vaddr, v4i32:{ *:[v4i32] }:$srsrc, i32:{ *:[i32] }:$soffset, i32:{ *:[i32] }:$offset)
      GIR_BuildMI, /*InsnID*/0, /*Opcode*/GIMT_Encode2(AMDGPU::BUFFER_LOAD_DWORD_VBUFFER_ADDR64),
      GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/0, // DstI[vdata]
      GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/1, // vaddr
      GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/0, // srsrc
      GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/2, // soffset
      GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/3, // offset
      GIR_AddImm8, /*InsnID*/0, /*Imm*/0,
      GIR_AddImm8, /*InsnID*/0, /*Imm*/0,
      GIR_MergeMemOperands, /*InsnID*/0, /*NumInsns*/1, /*MergeInsnID's*/0,
      GIR_ConstrainSelectedInstOperands, /*InsnID*/0,
      GIR_EraseFromParent, /*InsnID*/0,
      // GIR_Coverage, 3710,
      GIR_Done,
    // Label 919: @59519
    GIM_Try, /*On fail goto*//*Label 920*/ GIMT_Encode4(59594), // Rule ID 5411 //
      GIM_CheckFeatures, GIMT_Encode2(GIFBS_DisableFlatScratch_HasUnrestrictedSOffset),
      GIM_CheckMemoryAddressSpace, /*MI*/0, /*MMO*/0, /*NumAddrSpace*/1, /*AddrSpace*/5,
      GIM_CheckAtomicOrdering, /*MI*/0, /*Order*/(uint8_t)AtomicOrdering::NotAtomic,
      GIM_CheckRegBankForClass, /*MI*/0, /*Op*/0, /*RC*/GIMT_Encode2(AMDGPU::AV_32RegClassID),
      GIM_CheckPointerToAny, /*MI*/0, /*Op*/1, /*SizeInBits*/0,
      GIM_CheckComplexPattern, /*MI*/0, /*Op*/1, /*Renderer*/GIMT_Encode2(0), GIMT_Encode2(GICP_gi_mubuf_scratch_offen),
      // (ld:{ *:[i32] } (MUBUFScratchOffen:{ *:[iPTR] } v4i32:{ *:[v4i32] }:$srsrc, i32:{ *:[i32] }:$vaddr, i32:{ *:[i32] }:$soffset, i32:{ *:[i32] }:$offset))<<P:Predicate_unindexedload>><<P:Predicate_load_private>>  =>  (BUFFER_LOAD_DWORD_OFFEN:{ *:[i32] } ?:{ *:[i32] }:$vaddr, ?:{ *:[v4i32] }:$srsrc, ?:{ *:[i32] }:$soffset, ?:{ *:[i32] }:$offset, 0:{ *:[i32] }, 0:{ *:[i1] })
      GIR_BuildMI, /*InsnID*/0, /*Opcode*/GIMT_Encode2(AMDGPU::BUFFER_LOAD_DWORD_OFFEN),
      GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/0, // DstI[vdata]
      GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/1, // vaddr
      GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/0, // srsrc
      GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/2, // soffset
      GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/3, // offset
      GIR_AddImm8, /*InsnID*/0, /*Imm*/0,
      GIR_AddImm8, /*InsnID*/0, /*Imm*/0,
      GIR_MergeMemOperands, /*InsnID*/0, /*NumInsns*/1, /*MergeInsnID's*/0,
      GIR_ConstrainSelectedInstOperands, /*InsnID*/0,
      GIR_EraseFromParent, /*InsnID*/0,
      // GIR_Coverage, 5411,
      GIR_Done,
    // Label 920: @59594
    GIM_Try, /*On fail goto*//*Label 921*/ GIMT_Encode4(59669), // Rule ID 5413 //
      GIM_CheckFeatures, GIMT_Encode2(GIFBS_DisableFlatScratch),
      GIM_CheckMemoryAddressSpace, /*MI*/0, /*MMO*/0, /*NumAddrSpace*/1, /*AddrSpace*/5,
      GIM_CheckAtomicOrdering, /*MI*/0, /*Order*/(uint8_t)AtomicOrdering::NotAtomic,
      GIM_CheckRegBankForClass, /*MI*/0, /*Op*/0, /*RC*/GIMT_Encode2(AMDGPU::AV_32RegClassID),
      GIM_CheckPointerToAny, /*MI*/0, /*Op*/1, /*SizeInBits*/0,
      GIM_CheckComplexPattern, /*MI*/0, /*Op*/1, /*Renderer*/GIMT_Encode2(0), GIMT_Encode2(GICP_gi_mubuf_scratch_offen),
      // (ld:{ *:[i32] } (MUBUFScratchOffen:{ *:[iPTR] } v4i32:{ *:[v4i32] }:$srsrc, i32:{ *:[i32] }:$vaddr, i32:{ *:[i32] }:$soffset, i32:{ *:[i32] }:$offset))<<P:Predicate_unindexedload>><<P:Predicate_load_private>>  =>  (BUFFER_LOAD_DWORD_VBUFFER_OFFEN:{ *:[i32] } ?:{ *:[i32] }:$vaddr, ?:{ *:[v4i32] }:$srsrc, ?:{ *:[i32] }:$soffset, ?:{ *:[i32] }:$offset, 0:{ *:[i32] }, 0:{ *:[i1] })
      GIR_BuildMI, /*InsnID*/0, /*Opcode*/GIMT_Encode2(AMDGPU::BUFFER_LOAD_DWORD_VBUFFER_OFFEN),
      GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/0, // DstI[vdata]
      GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/1, // vaddr
      GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/0, // srsrc
      GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/2, // soffset
      GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/3, // offset
      GIR_AddImm8, /*InsnID*/0, /*Imm*/0,
      GIR_AddImm8, /*InsnID*/0, /*Imm*/0,
      GIR_MergeMemOperands, /*InsnID*/0, /*NumInsns*/1, /*MergeInsnID's*/0,
      GIR_ConstrainSelectedInstOperands, /*InsnID*/0,
      GIR_EraseFromParent, /*InsnID*/0,
      // GIR_Coverage, 5413,
      GIR_Done,
    // Label 921: @59669
    GIM_Try, /*On fail goto*//*Label 922*/ GIMT_Encode4(59741), // Rule ID 3707 //
      GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasUnrestrictedSOffset),
      GIM_CheckMemoryAddressSpace, /*MI*/0, /*MMO*/0, /*NumAddrSpace*/3, /*AddrSpace*/1, /*AddrSpace*/4, /*AddrSpace*/6,
      GIM_CheckAtomicOrdering, /*MI*/0, /*Order*/(uint8_t)AtomicOrdering::NotAtomic,
      GIM_CheckRegBankForClass, /*MI*/0, /*Op*/0, /*RC*/GIMT_Encode2(AMDGPU::AV_32RegClassID),
      GIM_CheckPointerToAny, /*MI*/0, /*Op*/1, /*SizeInBits*/0,
      GIM_CheckComplexPattern, /*MI*/0, /*Op*/1, /*Renderer*/GIMT_Encode2(0), GIMT_Encode2(GICP_gi_mubuf_offset),
      // (ld:{ *:[i32] } (MUBUFOffset:{ *:[iPTR] } v4i32:{ *:[v4i32] }:$srsrc, i32:{ *:[i32] }:$soffset, i32:{ *:[i32] }:$offset))<<P:Predicate_unindexedload>><<P:Predicate_load_global>>  =>  (BUFFER_LOAD_DWORD_OFFSET:{ *:[i32] } v4i32:{ *:[v4i32] }:$srsrc, i32:{ *:[i32] }:$soffset, i32:{ *:[i32] }:$offset)
      GIR_BuildMI, /*InsnID*/0, /*Opcode*/GIMT_Encode2(AMDGPU::BUFFER_LOAD_DWORD_OFFSET),
      GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/0, // DstI[vdata]
      GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/0, // srsrc
      GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/1, // soffset
      GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/2, // offset
      GIR_AddImm8, /*InsnID*/0, /*Imm*/0,
      GIR_AddImm8, /*InsnID*/0, /*Imm*/0,
      GIR_MergeMemOperands, /*InsnID*/0, /*NumInsns*/1, /*MergeInsnID's*/0,
      GIR_ConstrainSelectedInstOperands, /*InsnID*/0,
      GIR_EraseFromParent, /*InsnID*/0,
      // GIR_Coverage, 3707,
      GIR_Done,
    // Label 922: @59741
    GIM_Try, /*On fail goto*//*Label 923*/ GIMT_Encode4(59810), // Rule ID 3709 //
      GIM_CheckMemoryAddressSpace, /*MI*/0, /*MMO*/0, /*NumAddrSpace*/3, /*AddrSpace*/1, /*AddrSpace*/4, /*AddrSpace*/6,
      GIM_CheckAtomicOrdering, /*MI*/0, /*Order*/(uint8_t)AtomicOrdering::NotAtomic,
      GIM_CheckRegBankForClass, /*MI*/0, /*Op*/0, /*RC*/GIMT_Encode2(AMDGPU::AV_32RegClassID),
      GIM_CheckPointerToAny, /*MI*/0, /*Op*/1, /*SizeInBits*/0,
      GIM_CheckComplexPattern, /*MI*/0, /*Op*/1, /*Renderer*/GIMT_Encode2(0), GIMT_Encode2(GICP_gi_mubuf_offset),
      // (ld:{ *:[i32] } (MUBUFOffset:{ *:[iPTR] } v4i32:{ *:[v4i32] }:$srsrc, i32:{ *:[i32] }:$soffset, i32:{ *:[i32] }:$offset))<<P:Predicate_unindexedload>><<P:Predicate_load_global>>  =>  (BUFFER_LOAD_DWORD_VBUFFER_OFFSET:{ *:[i32] } v4i32:{ *:[v4i32] }:$srsrc, i32:{ *:[i32] }:$soffset, i32:{ *:[i32] }:$offset)
      GIR_BuildMI, /*InsnID*/0, /*Opcode*/GIMT_Encode2(AMDGPU::BUFFER_LOAD_DWORD_VBUFFER_OFFSET),
      GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/0, // DstI[vdata]
      GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/0, // srsrc
      GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/1, // soffset
      GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/2, // offset
      GIR_AddImm8, /*InsnID*/0, /*Imm*/0,
      GIR_AddImm8, /*InsnID*/0, /*Imm*/0,
      GIR_MergeMemOperands, /*InsnID*/0, /*NumInsns*/1, /*MergeInsnID's*/0,
      GIR_ConstrainSelectedInstOperands, /*InsnID*/0,
      GIR_EraseFromParent, /*InsnID*/0,
      // GIR_Coverage, 3709,
      GIR_Done,
    // Label 923: @59810
    GIM_Try, /*On fail goto*//*Label 924*/ GIMT_Encode4(59876), // Rule ID 6601 //
      GIM_CheckFeatures, GIMT_Encode2(GIFBS_LDSRequiresM0Init),
      GIM_CheckMemorySizeEqualToLLT, /*MI*/0, /*MMO*/0, /*OpIdx*/0,
      GIM_CheckMemoryAddressSpace, /*MI*/0, /*MMO*/0, /*NumAddrSpace*/1, /*AddrSpace*/3,
      GIM_CheckAtomicOrdering, /*MI*/0, /*Order*/(uint8_t)AtomicOrdering::NotAtomic,
      GIM_CheckRegBankForClass, /*MI*/0, /*Op*/0, /*RC*/GIMT_Encode2(AMDGPU::AV_32RegClassID),
      GIM_CheckPointerToAny, /*MI*/0, /*Op*/1, /*SizeInBits*/0,
      GIM_CheckComplexPattern, /*MI*/0, /*Op*/1, /*Renderer*/GIMT_Encode2(0), GIMT_Encode2(GICP_gi_ds_1addr_1offset),
      // (AMDGPUld_glue:{ *:[i32] } (DS1Addr1Offset:{ *:[iPTR] } i32:{ *:[i32] }:$ptr, i32:{ *:[i32] }:$offset))<<P:Predicate_unindexedload_glue>><<P:Predicate_load_glue>><<P:Predicate_load_local_m0>>  =>  (DS_READ_B32:{ *:[i32] } ?:{ *:[i32] }:$ptr, offset:{ *:[i32] }:$offset, 0:{ *:[i1] })
      GIR_BuildMI, /*InsnID*/0, /*Opcode*/GIMT_Encode2(AMDGPU::DS_READ_B32),
      GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/0, // DstI[vdst]
      GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/0, // ptr
      GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/1, // offset
      GIR_AddImm8, /*InsnID*/0, /*Imm*/0,
      GIR_MergeMemOperands, /*InsnID*/0, /*NumInsns*/1, /*MergeInsnID's*/0,
      GIR_ConstrainSelectedInstOperands, /*InsnID*/0,
      GIR_EraseFromParent, /*InsnID*/0,
      // GIR_Coverage, 6601,
      GIR_Done,
    // Label 924: @59876
    GIM_Try, /*On fail goto*//*Label 925*/ GIMT_Encode4(59938), // Rule ID 6602 //
      GIM_CheckFeatures, GIMT_Encode2(GIFBS_NotLDSRequiresM0Init),
      GIM_CheckMemoryAddressSpace, /*MI*/0, /*MMO*/0, /*NumAddrSpace*/1, /*AddrSpace*/3,
      GIM_CheckAtomicOrdering, /*MI*/0, /*Order*/(uint8_t)AtomicOrdering::NotAtomic,
      GIM_CheckRegBankForClass, /*MI*/0, /*Op*/0, /*RC*/GIMT_Encode2(AMDGPU::AV_32RegClassID),
      GIM_CheckPointerToAny, /*MI*/0, /*Op*/1, /*SizeInBits*/0,
      GIM_CheckComplexPattern, /*MI*/0, /*Op*/1, /*Renderer*/GIMT_Encode2(0), GIMT_Encode2(GICP_gi_ds_1addr_1offset),
      // (ld:{ *:[i32] } (DS1Addr1Offset:{ *:[iPTR] } i32:{ *:[i32] }:$ptr, i32:{ *:[i32] }:$offset))<<P:Predicate_unindexedload>><<P:Predicate_load_local>>  =>  (DS_READ_B32_gfx9:{ *:[i32] } ?:{ *:[i32] }:$ptr, offset:{ *:[i32] }:$offset, 0:{ *:[i1] })
      GIR_BuildMI, /*InsnID*/0, /*Opcode*/GIMT_Encode2(AMDGPU::DS_READ_B32_gfx9),
      GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/0, // DstI[vdst]
      GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/0, // ptr
      GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/1, // offset
      GIR_AddImm8, /*InsnID*/0, /*Imm*/0,
      GIR_MergeMemOperands, /*InsnID*/0, /*NumInsns*/1, /*MergeInsnID's*/0,
      GIR_ConstrainSelectedInstOperands, /*InsnID*/0,
      GIR_EraseFromParent, /*InsnID*/0,
      // GIR_Coverage, 6602,
      GIR_Done,
    // Label 925: @59938
    GIM_Try, /*On fail goto*//*Label 926*/ GIMT_Encode4(60007), // Rule ID 3017 //
      GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasFlatGlobalInsts),
      GIM_CheckMemoryAddressSpace, /*MI*/0, /*MMO*/0, /*NumAddrSpace*/3, /*AddrSpace*/1, /*AddrSpace*/4, /*AddrSpace*/6,
      GIM_CheckAtomicOrdering, /*MI*/0, /*Order*/(uint8_t)AtomicOrdering::NotAtomic,
      GIM_CheckRegBankForClass, /*MI*/0, /*Op*/0, /*RC*/GIMT_Encode2(AMDGPU::AV_32RegClassID),
      GIM_CheckPointerToAny, /*MI*/0, /*Op*/1, /*SizeInBits*/0,
      GIM_CheckComplexPattern, /*MI*/0, /*Op*/1, /*Renderer*/GIMT_Encode2(0), GIMT_Encode2(GICP_gi_global_saddr),
      // (ld:{ *:[i32] } (GlobalSAddr:{ *:[iPTR] } SReg_64:{ *:[i64] }:$saddr, VGPR_32:{ *:[i32] }:$voffset, i32:{ *:[i32] }:$offset))<<P:Predicate_unindexedload>><<P:Predicate_load_global>>  =>  (GLOBAL_LOAD_DWORD_SADDR:{ *:[i32] } ?:{ *:[i64] }:$saddr, ?:{ *:[i32] }:$voffset, ?:{ *:[i32] }:$offset, 0:{ *:[i32] })
      GIR_BuildMI, /*InsnID*/0, /*Opcode*/GIMT_Encode2(AMDGPU::GLOBAL_LOAD_DWORD_SADDR),
      GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/0, // DstI[vdst]
      GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/0, // saddr
      GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/1, // voffset
      GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/2, // offset
      GIR_AddImm8, /*InsnID*/0, /*Imm*/0,
      GIR_MergeMemOperands, /*InsnID*/0, /*NumInsns*/1, /*MergeInsnID's*/0,
      GIR_ConstrainSelectedInstOperands, /*InsnID*/0,
      GIR_EraseFromParent, /*InsnID*/0,
      // GIR_Coverage, 3017,
      GIR_Done,
    // Label 926: @60007
    GIM_Try, /*On fail goto*//*Label 927*/ GIMT_Encode4(60071), // Rule ID 3016 //
      GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasFlatGlobalInsts),
      GIM_CheckMemoryAddressSpace, /*MI*/0, /*MMO*/0, /*NumAddrSpace*/3, /*AddrSpace*/1, /*AddrSpace*/4, /*AddrSpace*/6,
      GIM_CheckAtomicOrdering, /*MI*/0, /*Order*/(uint8_t)AtomicOrdering::NotAtomic,
      GIM_CheckRegBankForClass, /*MI*/0, /*Op*/0, /*RC*/GIMT_Encode2(AMDGPU::AV_32RegClassID),
      GIM_CheckPointerToAny, /*MI*/0, /*Op*/1, /*SizeInBits*/0,
      GIM_CheckComplexPattern, /*MI*/0, /*Op*/1, /*Renderer*/GIMT_Encode2(0), GIMT_Encode2(GICP_gi_global_offset),
      // (ld:{ *:[i32] } (GlobalOffset:{ *:[iPTR] } VReg_64:{ *:[i64] }:$vaddr, i32:{ *:[i32] }:$offset))<<P:Predicate_unindexedload>><<P:Predicate_load_global>>  =>  (GLOBAL_LOAD_DWORD:{ *:[i32] } ?:{ *:[i64] }:$vaddr, ?:{ *:[i32] }:$offset)
      GIR_BuildMI, /*InsnID*/0, /*Opcode*/GIMT_Encode2(AMDGPU::GLOBAL_LOAD_DWORD),
      GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/0, // DstI[vdst]
      GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/0, // vaddr
      GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/1, // offset
      GIR_AddImm8, /*InsnID*/0, /*Imm*/0,
      GIR_MergeMemOperands, /*InsnID*/0, /*NumInsns*/1, /*MergeInsnID's*/0,
      GIR_ConstrainSelectedInstOperands, /*InsnID*/0,
      GIR_EraseFromParent, /*InsnID*/0,
      // GIR_Coverage, 3016,
      GIR_Done,
    // Label 927: @60071
    GIM_Try, /*On fail goto*//*Label 928*/ GIMT_Encode4(60136), // Rule ID 2782 //
      GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasFlatAddressSpace),
      GIM_CheckMemoryAddressSpace, /*MI*/0, /*MMO*/0, /*NumAddrSpace*/4, /*AddrSpace*/0, /*AddrSpace*/1, /*AddrSpace*/4, /*AddrSpace*/6,
      GIM_CheckAtomicOrdering, /*MI*/0, /*Order*/(uint8_t)AtomicOrdering::NotAtomic,
      GIM_CheckRegBankForClass, /*MI*/0, /*Op*/0, /*RC*/GIMT_Encode2(AMDGPU::AV_32RegClassID),
      GIM_CheckPointerToAny, /*MI*/0, /*Op*/1, /*SizeInBits*/0,
      GIM_CheckComplexPattern, /*MI*/0, /*Op*/1, /*Renderer*/GIMT_Encode2(0), GIMT_Encode2(GICP_gi_flat_offset),
      // (ld:{ *:[i32] } (FlatOffset:{ *:[iPTR] } i64:{ *:[i64] }:$vaddr, i32:{ *:[i32] }:$offset))<<P:Predicate_unindexedload>><<P:Predicate_load_flat>>  =>  (FLAT_LOAD_DWORD:{ *:[i32] } ?:{ *:[i64] }:$vaddr, ?:{ *:[i32] }:$offset)
      GIR_BuildMI, /*InsnID*/0, /*Opcode*/GIMT_Encode2(AMDGPU::FLAT_LOAD_DWORD),
      GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/0, // DstI[vdst]
      GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/0, // vaddr
      GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/1, // offset
      GIR_AddImm8, /*InsnID*/0, /*Imm*/0,
      GIR_MergeMemOperands, /*InsnID*/0, /*NumInsns*/1, /*MergeInsnID's*/0,
      GIR_ConstrainSelectedInstOperands, /*InsnID*/0,
      GIR_EraseFromParent, /*InsnID*/0,
      // GIR_Coverage, 2782,
      GIR_Done,
    // Label 928: @60136
    GIM_Reject,
    // Label 820: @60137
    GIM_Try, /*On fail goto*//*Label 929*/ GIMT_Encode4(60212), // Rule ID 6851 //
      GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasUnalignedAccessMode_LDSRequiresM0Init),
      GIM_CheckMemorySizeEqualToLLT, /*MI*/0, /*MMO*/0, /*OpIdx*/0,
      GIM_CheckMemoryAddressSpace, /*MI*/0, /*MMO*/0, /*NumAddrSpace*/1, /*AddrSpace*/3,
      GIM_CheckMemoryAddressSpace, /*MI*/0, /*MMO*/0, /*NumAddrSpace*/1, /*AddrSpace*/3,
      GIM_CheckAtomicOrdering, /*MI*/0, /*Order*/(uint8_t)AtomicOrdering::NotAtomic,
      GIM_CheckRegBankForClass, /*MI*/0, /*Op*/0, /*RC*/GIMT_Encode2(AMDGPU::AV_64RegClassID),
      GIM_CheckPointerToAny, /*MI*/0, /*Op*/1, /*SizeInBits*/0,
      GIM_CheckCxxInsnPredicate, /*MI*/0, /*FnId*/GIMT_Encode2(GICXXPred_MI_Predicate_load_align_less_than_4_local_m0),
      GIM_CheckComplexPattern, /*MI*/0, /*Op*/1, /*Renderer*/GIMT_Encode2(0), GIMT_Encode2(GICP_gi_ds_1addr_1offset),
      // (AMDGPUld_glue:{ *:[i64] } (DS1Addr1Offset:{ *:[iPTR] } i32:{ *:[i32] }:$ptr, i32:{ *:[i32] }:$offset))<<P:Predicate_unindexedload_glue>><<P:Predicate_load_glue>><<P:Predicate_load_local_m0>><<P:Predicate_load_align_less_than_4_local_m0>>  =>  (DS_READ_B64:{ *:[i64] } ?:{ *:[i32] }:$ptr, offset:{ *:[i32] }:$offset, 0:{ *:[i1] })
      GIR_BuildMI, /*InsnID*/0, /*Opcode*/GIMT_Encode2(AMDGPU::DS_READ_B64),
      GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/0, // DstI[vdst]
      GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/0, // ptr
      GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/1, // offset
      GIR_AddImm8, /*InsnID*/0, /*Imm*/0,
      GIR_MergeMemOperands, /*InsnID*/0, /*NumInsns*/1, /*MergeInsnID's*/0,
      GIR_ConstrainSelectedInstOperands, /*InsnID*/0,
      GIR_EraseFromParent, /*InsnID*/0,
      // GIR_Coverage, 6851,
      GIR_Done,
    // Label 929: @60212
    GIM_Try, /*On fail goto*//*Label 930*/ GIMT_Encode4(60282), // Rule ID 6775 //
      GIM_CheckFeatures, GIMT_Encode2(GIFBS_LDSRequiresM0Init),
      GIM_CheckMemorySizeEqualToLLT, /*MI*/0, /*MMO*/0, /*OpIdx*/0,
      GIM_CheckMemoryAddressSpace, /*MI*/0, /*MMO*/0, /*NumAddrSpace*/1, /*AddrSpace*/3,
      GIM_CheckMemoryAlignment, /*MI*/0, /*MMO*/0, /*MinAlign*/8,
      GIM_CheckAtomicOrdering, /*MI*/0, /*Order*/(uint8_t)AtomicOrdering::NotAtomic,
      GIM_CheckRegBankForClass, /*MI*/0, /*Op*/0, /*RC*/GIMT_Encode2(AMDGPU::AV_64RegClassID),
      GIM_CheckPointerToAny, /*MI*/0, /*Op*/1, /*SizeInBits*/0,
      GIM_CheckComplexPattern, /*MI*/0, /*Op*/1, /*Renderer*/GIMT_Encode2(0), GIMT_Encode2(GICP_gi_ds_1addr_1offset),
      // (AMDGPUld_glue:{ *:[i64] } (DS1Addr1Offset:{ *:[iPTR] } i32:{ *:[i32] }:$ptr, i32:{ *:[i32] }:$offset))<<P:Predicate_unindexedload_glue>><<P:Predicate_load_glue>><<P:Predicate_load_local_m0>><<P:Predicate_load_align8_local_m0>>  =>  (DS_READ_B64:{ *:[i64] } ?:{ *:[i32] }:$ptr, offset:{ *:[i32] }:$offset, 0:{ *:[i1] })
      GIR_BuildMI, /*InsnID*/0, /*Opcode*/GIMT_Encode2(AMDGPU::DS_READ_B64),
      GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/0, // DstI[vdst]
      GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/0, // ptr
      GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/1, // offset
      GIR_AddImm8, /*InsnID*/0, /*Imm*/0,
      GIR_MergeMemOperands, /*InsnID*/0, /*NumInsns*/1, /*MergeInsnID's*/0,
      GIR_ConstrainSelectedInstOperands, /*InsnID*/0,
      GIR_EraseFromParent, /*InsnID*/0,
      // GIR_Coverage, 6775,
      GIR_Done,
    // Label 930: @60282
    GIM_Try, /*On fail goto*//*Label 931*/ GIMT_Encode4(60353), // Rule ID 6852 //
      GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasUnalignedAccessMode_NotLDSRequiresM0Init),
      GIM_CheckMemoryAddressSpace, /*MI*/0, /*MMO*/0, /*NumAddrSpace*/1, /*AddrSpace*/3,
      GIM_CheckMemoryAddressSpace, /*MI*/0, /*MMO*/0, /*NumAddrSpace*/1, /*AddrSpace*/3,
      GIM_CheckAtomicOrdering, /*MI*/0, /*Order*/(uint8_t)AtomicOrdering::NotAtomic,
      GIM_CheckRegBankForClass, /*MI*/0, /*Op*/0, /*RC*/GIMT_Encode2(AMDGPU::AV_64RegClassID),
      GIM_CheckPointerToAny, /*MI*/0, /*Op*/1, /*SizeInBits*/0,
      GIM_CheckCxxInsnPredicate, /*MI*/0, /*FnId*/GIMT_Encode2(GICXXPred_MI_Predicate_load_align_less_than_4_local),
      GIM_CheckComplexPattern, /*MI*/0, /*Op*/1, /*Renderer*/GIMT_Encode2(0), GIMT_Encode2(GICP_gi_ds_1addr_1offset),
      // (ld:{ *:[i64] } (DS1Addr1Offset:{ *:[iPTR] } i32:{ *:[i32] }:$ptr, i32:{ *:[i32] }:$offset))<<P:Predicate_unindexedload>><<P:Predicate_load_local>><<P:Predicate_load_align_less_than_4_local>>  =>  (DS_READ_B64_gfx9:{ *:[i64] } ?:{ *:[i32] }:$ptr, offset:{ *:[i32] }:$offset, 0:{ *:[i1] })
      GIR_BuildMI, /*InsnID*/0, /*Opcode*/GIMT_Encode2(AMDGPU::DS_READ_B64_gfx9),
      GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/0, // DstI[vdst]
      GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/0, // ptr
      GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/1, // offset
      GIR_AddImm8, /*InsnID*/0, /*Imm*/0,
      GIR_MergeMemOperands, /*InsnID*/0, /*NumInsns*/1, /*MergeInsnID's*/0,
      GIR_ConstrainSelectedInstOperands, /*InsnID*/0,
      GIR_EraseFromParent, /*InsnID*/0,
      // GIR_Coverage, 6852,
      GIR_Done,
    // Label 931: @60353
    GIM_Try, /*On fail goto*//*Label 932*/ GIMT_Encode4(60419), // Rule ID 6776 //
      GIM_CheckFeatures, GIMT_Encode2(GIFBS_NotLDSRequiresM0Init),
      GIM_CheckMemoryAddressSpace, /*MI*/0, /*MMO*/0, /*NumAddrSpace*/1, /*AddrSpace*/3,
      GIM_CheckMemoryAlignment, /*MI*/0, /*MMO*/0, /*MinAlign*/8,
      GIM_CheckAtomicOrdering, /*MI*/0, /*Order*/(uint8_t)AtomicOrdering::NotAtomic,
      GIM_CheckRegBankForClass, /*MI*/0, /*Op*/0, /*RC*/GIMT_Encode2(AMDGPU::AV_64RegClassID),
      GIM_CheckPointerToAny, /*MI*/0, /*Op*/1, /*SizeInBits*/0,
      GIM_CheckComplexPattern, /*MI*/0, /*Op*/1, /*Renderer*/GIMT_Encode2(0), GIMT_Encode2(GICP_gi_ds_1addr_1offset),
      // (ld:{ *:[i64] } (DS1Addr1Offset:{ *:[iPTR] } i32:{ *:[i32] }:$ptr, i32:{ *:[i32] }:$offset))<<P:Predicate_unindexedload>><<P:Predicate_load_local>><<P:Predicate_load_align8_local>>  =>  (DS_READ_B64_gfx9:{ *:[i64] } ?:{ *:[i32] }:$ptr, offset:{ *:[i32] }:$offset, 0:{ *:[i1] })
      GIR_BuildMI, /*InsnID*/0, /*Opcode*/GIMT_Encode2(AMDGPU::DS_READ_B64_gfx9),
      GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/0, // DstI[vdst]
      GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/0, // ptr
      GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/1, // offset
      GIR_AddImm8, /*InsnID*/0, /*Imm*/0,
      GIR_MergeMemOperands, /*InsnID*/0, /*NumInsns*/1, /*MergeInsnID's*/0,
      GIR_ConstrainSelectedInstOperands, /*InsnID*/0,
      GIR_EraseFromParent, /*InsnID*/0,
      // GIR_Coverage, 6776,
      GIR_Done,
    // Label 932: @60419
    GIM_Try, /*On fail goto*//*Label 933*/ GIMT_Encode4(60486), // Rule ID 3538 //
      GIM_CheckFeatures, GIMT_Encode2(GIFBS_EnableFlatScratch_HasFlatScratchInsts_HasFlatScratchSVSMode),
      GIM_CheckMemoryAddressSpace, /*MI*/0, /*MMO*/0, /*NumAddrSpace*/1, /*AddrSpace*/5,
      GIM_CheckAtomicOrdering, /*MI*/0, /*Order*/(uint8_t)AtomicOrdering::NotAtomic,
      GIM_CheckRegBankForClass, /*MI*/0, /*Op*/0, /*RC*/GIMT_Encode2(AMDGPU::AV_64RegClassID),
      GIM_CheckPointerToAny, /*MI*/0, /*Op*/1, /*SizeInBits*/0,
      GIM_CheckComplexPattern, /*MI*/0, /*Op*/1, /*Renderer*/GIMT_Encode2(0), GIMT_Encode2(GICP_gi_flat_scratch_svaddr),
      // (ld:{ *:[i64] } (ScratchSVAddr:{ *:[iPTR] } VGPR_32:{ *:[i32] }:$vaddr, SGPR_32:{ *:[i32] }:$saddr, i32:{ *:[i32] }:$offset))<<P:Predicate_unindexedload>><<P:Predicate_load_private>>  =>  (SCRATCH_LOAD_DWORDX2_SVS:{ *:[i64] } ?:{ *:[i32] }:$vaddr, ?:{ *:[i32] }:$saddr, ?:{ *:[i32] }:$offset, 0:{ *:[i32] })
      GIR_BuildMI, /*InsnID*/0, /*Opcode*/GIMT_Encode2(AMDGPU::SCRATCH_LOAD_DWORDX2_SVS),
      GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/0, // DstI[vdst]
      GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/0, // vaddr
      GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/1, // saddr
      GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/2, // offset
      GIR_AddImm8, /*InsnID*/0, /*Imm*/0,
      GIR_MergeMemOperands, /*InsnID*/0, /*NumInsns*/1, /*MergeInsnID's*/0,
      GIR_ConstrainSelectedInstOperands, /*InsnID*/0,
      GIR_EraseFromParent, /*InsnID*/0,
      // GIR_Coverage, 3538,
      GIR_Done,
    // Label 933: @60486
    GIM_Try, /*On fail goto*//*Label 934*/ GIMT_Encode4(60548), // Rule ID 3537 //
      GIM_CheckFeatures, GIMT_Encode2(GIFBS_EnableFlatScratch_HasFlatScratchInsts),
      GIM_CheckMemoryAddressSpace, /*MI*/0, /*MMO*/0, /*NumAddrSpace*/1, /*AddrSpace*/5,
      GIM_CheckAtomicOrdering, /*MI*/0, /*Order*/(uint8_t)AtomicOrdering::NotAtomic,
      GIM_CheckRegBankForClass, /*MI*/0, /*Op*/0, /*RC*/GIMT_Encode2(AMDGPU::AV_64RegClassID),
      GIM_CheckPointerToAny, /*MI*/0, /*Op*/1, /*SizeInBits*/0,
      GIM_CheckComplexPattern, /*MI*/0, /*Op*/1, /*Renderer*/GIMT_Encode2(0), GIMT_Encode2(GICP_gi_flat_scratch_saddr),
      // (ld:{ *:[i64] } (ScratchSAddr:{ *:[iPTR] } SGPR_32:{ *:[i32] }:$saddr, i32:{ *:[i32] }:$offset))<<P:Predicate_unindexedload>><<P:Predicate_load_private>>  =>  (SCRATCH_LOAD_DWORDX2_SADDR:{ *:[i64] } ?:{ *:[i32] }:$saddr, ?:{ *:[i32] }:$offset)
      GIR_BuildMI, /*InsnID*/0, /*Opcode*/GIMT_Encode2(AMDGPU::SCRATCH_LOAD_DWORDX2_SADDR),
      GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/0, // DstI[vdst]
      GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/0, // saddr
      GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/1, // offset
      GIR_AddImm8, /*InsnID*/0, /*Imm*/0,
      GIR_MergeMemOperands, /*InsnID*/0, /*NumInsns*/1, /*MergeInsnID's*/0,
      GIR_ConstrainSelectedInstOperands, /*InsnID*/0,
      GIR_EraseFromParent, /*InsnID*/0,
      // GIR_Coverage, 3537,
      GIR_Done,
    // Label 934: @60548
    GIM_Try, /*On fail goto*//*Label 935*/ GIMT_Encode4(60610), // Rule ID 3536 //
      GIM_CheckFeatures, GIMT_Encode2(GIFBS_EnableFlatScratch_HasFlatScratchInsts),
      GIM_CheckMemoryAddressSpace, /*MI*/0, /*MMO*/0, /*NumAddrSpace*/1, /*AddrSpace*/5,
      GIM_CheckAtomicOrdering, /*MI*/0, /*Order*/(uint8_t)AtomicOrdering::NotAtomic,
      GIM_CheckRegBankForClass, /*MI*/0, /*Op*/0, /*RC*/GIMT_Encode2(AMDGPU::AV_64RegClassID),
      GIM_CheckPointerToAny, /*MI*/0, /*Op*/1, /*SizeInBits*/0,
      GIM_CheckComplexPattern, /*MI*/0, /*Op*/1, /*Renderer*/GIMT_Encode2(0), GIMT_Encode2(GICP_gi_flat_scratch_offset),
      // (ld:{ *:[i64] } (ScratchOffset:{ *:[iPTR] } VGPR_32:{ *:[i32] }:$vaddr, i32:{ *:[i32] }:$offset))<<P:Predicate_unindexedload>><<P:Predicate_load_private>>  =>  (SCRATCH_LOAD_DWORDX2:{ *:[i64] } ?:{ *:[i32] }:$vaddr, ?:{ *:[i32] }:$offset)
      GIR_BuildMI, /*InsnID*/0, /*Opcode*/GIMT_Encode2(AMDGPU::SCRATCH_LOAD_DWORDX2),
      GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/0, // DstI[vdst]
      GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/0, // vaddr
      GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/1, // offset
      GIR_AddImm8, /*InsnID*/0, /*Imm*/0,
      GIR_MergeMemOperands, /*InsnID*/0, /*NumInsns*/1, /*MergeInsnID's*/0,
      GIR_ConstrainSelectedInstOperands, /*InsnID*/0,
      GIR_EraseFromParent, /*InsnID*/0,
      // GIR_Coverage, 3536,
      GIR_Done,
    // Label 935: @60610
    GIM_Try, /*On fail goto*//*Label 936*/ GIMT_Encode4(60687), // Rule ID 3756 //
      GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasUnrestrictedSOffset),
      GIM_CheckMemoryAddressSpace, /*MI*/0, /*MMO*/0, /*NumAddrSpace*/3, /*AddrSpace*/1, /*AddrSpace*/4, /*AddrSpace*/6,
      GIM_CheckAtomicOrdering, /*MI*/0, /*Order*/(uint8_t)AtomicOrdering::NotAtomic,
      GIM_CheckRegBankForClass, /*MI*/0, /*Op*/0, /*RC*/GIMT_Encode2(AMDGPU::AV_64RegClassID),
      GIM_CheckPointerToAny, /*MI*/0, /*Op*/1, /*SizeInBits*/0,
      GIM_CheckComplexPattern, /*MI*/0, /*Op*/1, /*Renderer*/GIMT_Encode2(0), GIMT_Encode2(GICP_gi_mubuf_addr64),
      // (ld:{ *:[i64] } (MUBUFAddr64:{ *:[iPTR] } v4i32:{ *:[v4i32] }:$srsrc, i64:{ *:[i64] }:$vaddr, i32:{ *:[i32] }:$soffset, i32:{ *:[i32] }:$offset))<<P:Predicate_unindexedload>><<P:Predicate_load_global>>  =>  (BUFFER_LOAD_DWORDX2_ADDR64:{ *:[i64] } i64:{ *:[i64] }:$vaddr, v4i32:{ *:[v4i32] }:$srsrc, i32:{ *:[i32] }:$soffset, i32:{ *:[i32] }:$offset)
      GIR_BuildMI, /*InsnID*/0, /*Opcode*/GIMT_Encode2(AMDGPU::BUFFER_LOAD_DWORDX2_ADDR64),
      GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/0, // DstI[vdata]
      GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/1, // vaddr
      GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/0, // srsrc
      GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/2, // soffset
      GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/3, // offset
      GIR_AddImm8, /*InsnID*/0, /*Imm*/0,
      GIR_AddImm8, /*InsnID*/0, /*Imm*/0,
      GIR_MergeMemOperands, /*InsnID*/0, /*NumInsns*/1, /*MergeInsnID's*/0,
      GIR_ConstrainSelectedInstOperands, /*InsnID*/0,
      GIR_EraseFromParent, /*InsnID*/0,
      // GIR_Coverage, 3756,
      GIR_Done,
    // Label 936: @60687
    GIM_Try, /*On fail goto*//*Label 937*/ GIMT_Encode4(60761), // Rule ID 3758 //
      GIM_CheckMemoryAddressSpace, /*MI*/0, /*MMO*/0, /*NumAddrSpace*/3, /*AddrSpace*/1, /*AddrSpace*/4, /*AddrSpace*/6,
      GIM_CheckAtomicOrdering, /*MI*/0, /*Order*/(uint8_t)AtomicOrdering::NotAtomic,
      GIM_CheckRegBankForClass, /*MI*/0, /*Op*/0, /*RC*/GIMT_Encode2(AMDGPU::AV_64RegClassID),
      GIM_CheckPointerToAny, /*MI*/0, /*Op*/1, /*SizeInBits*/0,
      GIM_CheckComplexPattern, /*MI*/0, /*Op*/1, /*Renderer*/GIMT_Encode2(0), GIMT_Encode2(GICP_gi_mubuf_addr64),
      // (ld:{ *:[i64] } (MUBUFAddr64:{ *:[iPTR] } v4i32:{ *:[v4i32] }:$srsrc, i64:{ *:[i64] }:$vaddr, i32:{ *:[i32] }:$soffset, i32:{ *:[i32] }:$offset))<<P:Predicate_unindexedload>><<P:Predicate_load_global>>  =>  (BUFFER_LOAD_DWORDX2_VBUFFER_ADDR64:{ *:[i64] } i64:{ *:[i64] }:$vaddr, v4i32:{ *:[v4i32] }:$srsrc, i32:{ *:[i32] }:$soffset, i32:{ *:[i32] }:$offset)
      GIR_BuildMI, /*InsnID*/0, /*Opcode*/GIMT_Encode2(AMDGPU::BUFFER_LOAD_DWORDX2_VBUFFER_ADDR64),
      GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/0, // DstI[vdata]
      GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/1, // vaddr
      GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/0, // srsrc
      GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/2, // soffset
      GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/3, // offset
      GIR_AddImm8, /*InsnID*/0, /*Imm*/0,
      GIR_AddImm8, /*InsnID*/0, /*Imm*/0,
      GIR_MergeMemOperands, /*InsnID*/0, /*NumInsns*/1, /*MergeInsnID's*/0,
      GIR_ConstrainSelectedInstOperands, /*InsnID*/0,
      GIR_EraseFromParent, /*InsnID*/0,
      // GIR_Coverage, 3758,
      GIR_Done,
    // Label 937: @60761
    GIM_Try, /*On fail goto*//*Label 938*/ GIMT_Encode4(60832), // Rule ID 6711 //
      GIM_CheckFeatures, GIMT_Encode2(GIFBS_LDSRequiresM0Init_isGFX7Plus),
      GIM_CheckMemorySizeEqualToLLT, /*MI*/0, /*MMO*/0, /*OpIdx*/0,
      GIM_CheckMemoryAddressSpace, /*MI*/0, /*MMO*/0, /*NumAddrSpace*/1, /*AddrSpace*/3,
      GIM_CheckAtomicOrdering, /*MI*/0, /*Order*/(uint8_t)AtomicOrdering::NotAtomic,
      GIM_CheckRegBankForClass, /*MI*/0, /*Op*/0, /*RC*/GIMT_Encode2(AMDGPU::AV_64RegClassID),
      GIM_CheckPointerToAny, /*MI*/0, /*Op*/1, /*SizeInBits*/0,
      GIM_CheckComplexPattern, /*MI*/0, /*Op*/1, /*Renderer*/GIMT_Encode2(0), GIMT_Encode2(GICP_gi_ds_64bit_4byte_aligned),
      // (AMDGPUld_glue:{ *:[i64] } (DS64Bit4ByteAligned:{ *:[iPTR] } i32:{ *:[i32] }:$ptr, i8:{ *:[i8] }:$offset0, i8:{ *:[i8] }:$offset1))<<P:Predicate_unindexedload_glue>><<P:Predicate_load_glue>><<P:Predicate_load_local_m0>>  =>  (DS_READ2_B32:{ *:[i64] } ?:{ *:[i32] }:$ptr, ?:{ *:[i8] }:$offset0, ?:{ *:[i8] }:$offset1, 0:{ *:[i1] })
      GIR_BuildMI, /*InsnID*/0, /*Opcode*/GIMT_Encode2(AMDGPU::DS_READ2_B32),
      GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/0, // DstI[vdst]
      GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/0, // ptr
      GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/1, // offset0
      GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/2, // offset1
      GIR_AddImm8, /*InsnID*/0, /*Imm*/0,
      GIR_MergeMemOperands, /*InsnID*/0, /*NumInsns*/1, /*MergeInsnID's*/0,
      GIR_ConstrainSelectedInstOperands, /*InsnID*/0,
      GIR_EraseFromParent, /*InsnID*/0,
      // GIR_Coverage, 6711,
      GIR_Done,
    // Label 938: @60832
    GIM_Try, /*On fail goto*//*Label 939*/ GIMT_Encode4(60902), // Rule ID 7114 //
      GIM_CheckFeatures, GIMT_Encode2(GIFBS_isGFX9Plus),
      GIM_CheckMemorySizeEqualToLLT, /*MI*/0, /*MMO*/0, /*OpIdx*/0,
      GIM_CheckAtomicOrdering, /*MI*/0, /*Order*/(uint8_t)AtomicOrdering::NotAtomic,
      GIM_CheckRegBankForClass, /*MI*/0, /*Op*/0, /*RC*/GIMT_Encode2(AMDGPU::SReg_64_XEXECRegClassID),
      GIM_CheckPointerToAny, /*MI*/0, /*Op*/1, /*SizeInBits*/0,
      GIM_CheckCxxInsnPredicate, /*MI*/0, /*FnId*/GIMT_Encode2(GICXXPred_MI_Predicate_smrd_load),
      GIM_CheckComplexPattern, /*MI*/0, /*Op*/1, /*Renderer*/GIMT_Encode2(0), GIMT_Encode2(GICP_gi_smrd_sgpr_imm),
      // (ld:{ *:[i64] } (SMRDSgprImm:{ *:[iPTR] } i64:{ *:[i64] }:$sbase, i32:{ *:[i32] }:$soffset, i32:{ *:[i32] }:$offset))<<P:Predicate_unindexedload>><<P:Predicate_load>><<P:Predicate_smrd_load>>  =>  (S_LOAD_DWORDX2_SGPR_IMM:{ *:[i64] } ?:{ *:[i64] }:$sbase, ?:{ *:[i32] }:$soffset, ?:{ *:[i32] }:$offset, 0:{ *:[i32] })
      GIR_BuildMI, /*InsnID*/0, /*Opcode*/GIMT_Encode2(AMDGPU::S_LOAD_DWORDX2_SGPR_IMM),
      GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/0, // DstI[sdst]
      GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/0, // sbase
      GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/1, // soffset
      GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/2, // offset
      GIR_AddImm8, /*InsnID*/0, /*Imm*/0,
      GIR_MergeMemOperands, /*InsnID*/0, /*NumInsns*/1, /*MergeInsnID's*/0,
      GIR_ConstrainSelectedInstOperands, /*InsnID*/0,
      GIR_EraseFromParent, /*InsnID*/0,
      // GIR_Coverage, 7114,
      GIR_Done,
    // Label 939: @60902
    GIM_Try, /*On fail goto*//*Label 940*/ GIMT_Encode4(60974), // Rule ID 3755 //
      GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasUnrestrictedSOffset),
      GIM_CheckMemoryAddressSpace, /*MI*/0, /*MMO*/0, /*NumAddrSpace*/3, /*AddrSpace*/1, /*AddrSpace*/4, /*AddrSpace*/6,
      GIM_CheckAtomicOrdering, /*MI*/0, /*Order*/(uint8_t)AtomicOrdering::NotAtomic,
      GIM_CheckRegBankForClass, /*MI*/0, /*Op*/0, /*RC*/GIMT_Encode2(AMDGPU::AV_64RegClassID),
      GIM_CheckPointerToAny, /*MI*/0, /*Op*/1, /*SizeInBits*/0,
      GIM_CheckComplexPattern, /*MI*/0, /*Op*/1, /*Renderer*/GIMT_Encode2(0), GIMT_Encode2(GICP_gi_mubuf_offset),
      // (ld:{ *:[i64] } (MUBUFOffset:{ *:[iPTR] } v4i32:{ *:[v4i32] }:$srsrc, i32:{ *:[i32] }:$soffset, i32:{ *:[i32] }:$offset))<<P:Predicate_unindexedload>><<P:Predicate_load_global>>  =>  (BUFFER_LOAD_DWORDX2_OFFSET:{ *:[i64] } v4i32:{ *:[v4i32] }:$srsrc, i32:{ *:[i32] }:$soffset, i32:{ *:[i32] }:$offset)
      GIR_BuildMI, /*InsnID*/0, /*Opcode*/GIMT_Encode2(AMDGPU::BUFFER_LOAD_DWORDX2_OFFSET),
      GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/0, // DstI[vdata]
      GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/0, // srsrc
      GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/1, // soffset
      GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/2, // offset
      GIR_AddImm8, /*InsnID*/0, /*Imm*/0,
      GIR_AddImm8, /*InsnID*/0, /*Imm*/0,
      GIR_MergeMemOperands, /*InsnID*/0, /*NumInsns*/1, /*MergeInsnID's*/0,
      GIR_ConstrainSelectedInstOperands, /*InsnID*/0,
      GIR_EraseFromParent, /*InsnID*/0,
      // GIR_Coverage, 3755,
      GIR_Done,
    // Label 940: @60974
    GIM_Try, /*On fail goto*//*Label 941*/ GIMT_Encode4(61043), // Rule ID 3757 //
      GIM_CheckMemoryAddressSpace, /*MI*/0, /*MMO*/0, /*NumAddrSpace*/3, /*AddrSpace*/1, /*AddrSpace*/4, /*AddrSpace*/6,
      GIM_CheckAtomicOrdering, /*MI*/0, /*Order*/(uint8_t)AtomicOrdering::NotAtomic,
      GIM_CheckRegBankForClass, /*MI*/0, /*Op*/0, /*RC*/GIMT_Encode2(AMDGPU::AV_64RegClassID),
      GIM_CheckPointerToAny, /*MI*/0, /*Op*/1, /*SizeInBits*/0,
      GIM_CheckComplexPattern, /*MI*/0, /*Op*/1, /*Renderer*/GIMT_Encode2(0), GIMT_Encode2(GICP_gi_mubuf_offset),
      // (ld:{ *:[i64] } (MUBUFOffset:{ *:[iPTR] } v4i32:{ *:[v4i32] }:$srsrc, i32:{ *:[i32] }:$soffset, i32:{ *:[i32] }:$offset))<<P:Predicate_unindexedload>><<P:Predicate_load_global>>  =>  (BUFFER_LOAD_DWORDX2_VBUFFER_OFFSET:{ *:[i64] } v4i32:{ *:[v4i32] }:$srsrc, i32:{ *:[i32] }:$soffset, i32:{ *:[i32] }:$offset)
      GIR_BuildMI, /*InsnID*/0, /*Opcode*/GIMT_Encode2(AMDGPU::BUFFER_LOAD_DWORDX2_VBUFFER_OFFSET),
      GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/0, // DstI[vdata]
      GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/0, // srsrc
      GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/1, // soffset
      GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/2, // offset
      GIR_AddImm8, /*InsnID*/0, /*Imm*/0,
      GIR_AddImm8, /*InsnID*/0, /*Imm*/0,
      GIR_MergeMemOperands, /*InsnID*/0, /*NumInsns*/1, /*MergeInsnID's*/0,
      GIR_ConstrainSelectedInstOperands, /*InsnID*/0,
      GIR_EraseFromParent, /*InsnID*/0,
      // GIR_Coverage, 3757,
      GIR_Done,
    // Label 941: @61043
    GIM_Try, /*On fail goto*//*Label 942*/ GIMT_Encode4(61110), // Rule ID 6713 //
      GIM_CheckFeatures, GIMT_Encode2(GIFBS_NotLDSRequiresM0Init),
      GIM_CheckMemoryAddressSpace, /*MI*/0, /*MMO*/0, /*NumAddrSpace*/1, /*AddrSpace*/3,
      GIM_CheckAtomicOrdering, /*MI*/0, /*Order*/(uint8_t)AtomicOrdering::NotAtomic,
      GIM_CheckRegBankForClass, /*MI*/0, /*Op*/0, /*RC*/GIMT_Encode2(AMDGPU::AV_64RegClassID),
      GIM_CheckPointerToAny, /*MI*/0, /*Op*/1, /*SizeInBits*/0,
      GIM_CheckComplexPattern, /*MI*/0, /*Op*/1, /*Renderer*/GIMT_Encode2(0), GIMT_Encode2(GICP_gi_ds_64bit_4byte_aligned),
      // (ld:{ *:[i64] } (DS64Bit4ByteAligned:{ *:[iPTR] } i32:{ *:[i32] }:$ptr, i8:{ *:[i8] }:$offset0, i8:{ *:[i8] }:$offset1))<<P:Predicate_unindexedload>><<P:Predicate_load_local>>  =>  (DS_READ2_B32_gfx9:{ *:[i64] } ?:{ *:[i32] }:$ptr, ?:{ *:[i8] }:$offset0, ?:{ *:[i8] }:$offset1, 0:{ *:[i1] })
      GIR_BuildMI, /*InsnID*/0, /*Opcode*/GIMT_Encode2(AMDGPU::DS_READ2_B32_gfx9),
      GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/0, // DstI[vdst]
      GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/0, // ptr
      GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/1, // offset0
      GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/2, // offset1
      GIR_AddImm8, /*InsnID*/0, /*Imm*/0,
      GIR_MergeMemOperands, /*InsnID*/0, /*NumInsns*/1, /*MergeInsnID's*/0,
      GIR_ConstrainSelectedInstOperands, /*InsnID*/0,
      GIR_EraseFromParent, /*InsnID*/0,
      // GIR_Coverage, 6713,
      GIR_Done,
    // Label 942: @61110
    GIM_Try, /*On fail goto*//*Label 943*/ GIMT_Encode4(61172), // Rule ID 7110 //
      GIM_CheckMemorySizeEqualToLLT, /*MI*/0, /*MMO*/0, /*OpIdx*/0,
      GIM_CheckAtomicOrdering, /*MI*/0, /*Order*/(uint8_t)AtomicOrdering::NotAtomic,
      GIM_CheckRegBankForClass, /*MI*/0, /*Op*/0, /*RC*/GIMT_Encode2(AMDGPU::SReg_64_XEXECRegClassID),
      GIM_CheckPointerToAny, /*MI*/0, /*Op*/1, /*SizeInBits*/0,
      GIM_CheckCxxInsnPredicate, /*MI*/0, /*FnId*/GIMT_Encode2(GICXXPred_MI_Predicate_smrd_load),
      GIM_CheckComplexPattern, /*MI*/0, /*Op*/1, /*Renderer*/GIMT_Encode2(0), GIMT_Encode2(GICP_gi_smrd_imm),
      // (ld:{ *:[i64] } (SMRDImm:{ *:[iPTR] } i64:{ *:[i64] }:$sbase, i32:{ *:[i32] }:$offset))<<P:Predicate_unindexedload>><<P:Predicate_load>><<P:Predicate_smrd_load>>  =>  (S_LOAD_DWORDX2_IMM:{ *:[i64] } ?:{ *:[i64] }:$sbase, ?:{ *:[i32] }:$offset, 0:{ *:[i32] })
      GIR_BuildMI, /*InsnID*/0, /*Opcode*/GIMT_Encode2(AMDGPU::S_LOAD_DWORDX2_IMM),
      GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/0, // DstI[sdst]
      GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/0, // sbase
      GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/1, // offset
      GIR_AddImm8, /*InsnID*/0, /*Imm*/0,
      GIR_MergeMemOperands, /*InsnID*/0, /*NumInsns*/1, /*MergeInsnID's*/0,
      GIR_ConstrainSelectedInstOperands, /*InsnID*/0,
      GIR_EraseFromParent, /*InsnID*/0,
      // GIR_Coverage, 7110,
      GIR_Done,
    // Label 943: @61172
    GIM_Try, /*On fail goto*//*Label 944*/ GIMT_Encode4(61237), // Rule ID 7111 //
      GIM_CheckFeatures, GIMT_Encode2(GIFBS_isGFX7Only),
      GIM_CheckMemorySizeEqualToLLT, /*MI*/0, /*MMO*/0, /*OpIdx*/0,
      GIM_CheckAtomicOrdering, /*MI*/0, /*Order*/(uint8_t)AtomicOrdering::NotAtomic,
      GIM_CheckRegBankForClass, /*MI*/0, /*Op*/0, /*RC*/GIMT_Encode2(AMDGPU::SReg_64_XEXECRegClassID),
      GIM_CheckPointerToAny, /*MI*/0, /*Op*/1, /*SizeInBits*/0,
      GIM_CheckCxxInsnPredicate, /*MI*/0, /*FnId*/GIMT_Encode2(GICXXPred_MI_Predicate_smrd_load),
      GIM_CheckComplexPattern, /*MI*/0, /*Op*/1, /*Renderer*/GIMT_Encode2(0), GIMT_Encode2(GICP_gi_smrd_imm32),
      // (ld:{ *:[i64] } (SMRDImm32:{ *:[iPTR] } i64:{ *:[i64] }:$sbase, i32:{ *:[i32] }:$offset))<<P:Predicate_unindexedload>><<P:Predicate_load>><<P:Predicate_smrd_load>>  =>  (S_LOAD_DWORDX2_IMM_ci:{ *:[i64] } ?:{ *:[i64] }:$sbase, ?:{ *:[i32] }:$offset, 0:{ *:[i32] })
      GIR_BuildMI, /*InsnID*/0, /*Opcode*/GIMT_Encode2(AMDGPU::S_LOAD_DWORDX2_IMM_ci),
      GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/0, // DstI[sdst]
      GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/0, // sbase
      GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/1, // offset
      GIR_AddImm8, /*InsnID*/0, /*Imm*/0,
      GIR_MergeMemOperands, /*InsnID*/0, /*NumInsns*/1, /*MergeInsnID's*/0,
      GIR_ConstrainSelectedInstOperands, /*InsnID*/0,
      GIR_EraseFromParent, /*InsnID*/0,
      // GIR_Coverage, 7111,
      GIR_Done,
    // Label 944: @61237
    GIM_Try, /*On fail goto*//*Label 945*/ GIMT_Encode4(61302), // Rule ID 7112 //
      GIM_CheckFeatures, GIMT_Encode2(GIFBS_isNotGFX9Plus),
      GIM_CheckMemorySizeEqualToLLT, /*MI*/0, /*MMO*/0, /*OpIdx*/0,
      GIM_CheckAtomicOrdering, /*MI*/0, /*Order*/(uint8_t)AtomicOrdering::NotAtomic,
      GIM_CheckRegBankForClass, /*MI*/0, /*Op*/0, /*RC*/GIMT_Encode2(AMDGPU::SReg_64_XEXECRegClassID),
      GIM_CheckPointerToAny, /*MI*/0, /*Op*/1, /*SizeInBits*/0,
      GIM_CheckCxxInsnPredicate, /*MI*/0, /*FnId*/GIMT_Encode2(GICXXPred_MI_Predicate_smrd_load),
      GIM_CheckComplexPattern, /*MI*/0, /*Op*/1, /*Renderer*/GIMT_Encode2(0), GIMT_Encode2(GICP_gi_smrd_sgpr),
      // (ld:{ *:[i64] } (SMRDSgpr:{ *:[iPTR] } i64:{ *:[i64] }:$sbase, i32:{ *:[i32] }:$soffset))<<P:Predicate_unindexedload>><<P:Predicate_load>><<P:Predicate_smrd_load>>  =>  (S_LOAD_DWORDX2_SGPR:{ *:[i64] } ?:{ *:[i64] }:$sbase, ?:{ *:[i32] }:$soffset, 0:{ *:[i32] })
      GIR_BuildMI, /*InsnID*/0, /*Opcode*/GIMT_Encode2(AMDGPU::S_LOAD_DWORDX2_SGPR),
      GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/0, // DstI[sdst]
      GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/0, // sbase
      GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/1, // soffset
      GIR_AddImm8, /*InsnID*/0, /*Imm*/0,
      GIR_MergeMemOperands, /*InsnID*/0, /*NumInsns*/1, /*MergeInsnID's*/0,
      GIR_ConstrainSelectedInstOperands, /*InsnID*/0,
      GIR_EraseFromParent, /*InsnID*/0,
      // GIR_Coverage, 7112,
      GIR_Done,
    // Label 945: @61302
    GIM_Try, /*On fail goto*//*Label 946*/ GIMT_Encode4(61370), // Rule ID 7113 //
      GIM_CheckFeatures, GIMT_Encode2(GIFBS_isGFX9Plus),
      GIM_CheckMemorySizeEqualToLLT, /*MI*/0, /*MMO*/0, /*OpIdx*/0,
      GIM_CheckAtomicOrdering, /*MI*/0, /*Order*/(uint8_t)AtomicOrdering::NotAtomic,
      GIM_CheckRegBankForClass, /*MI*/0, /*Op*/0, /*RC*/GIMT_Encode2(AMDGPU::SReg_64_XEXECRegClassID),
      GIM_CheckPointerToAny, /*MI*/0, /*Op*/1, /*SizeInBits*/0,
      GIM_CheckCxxInsnPredicate, /*MI*/0, /*FnId*/GIMT_Encode2(GICXXPred_MI_Predicate_smrd_load),
      GIM_CheckComplexPattern, /*MI*/0, /*Op*/1, /*Renderer*/GIMT_Encode2(0), GIMT_Encode2(GICP_gi_smrd_sgpr),
      // (ld:{ *:[i64] } (SMRDSgpr:{ *:[iPTR] } i64:{ *:[i64] }:$sbase, i32:{ *:[i32] }:$soffset))<<P:Predicate_unindexedload>><<P:Predicate_load>><<P:Predicate_smrd_load>>  =>  (S_LOAD_DWORDX2_SGPR_IMM:{ *:[i64] } ?:{ *:[i64] }:$sbase, ?:{ *:[i32] }:$soffset, 0:{ *:[i32] }, 0:{ *:[i32] })
      GIR_BuildMI, /*InsnID*/0, /*Opcode*/GIMT_Encode2(AMDGPU::S_LOAD_DWORDX2_SGPR_IMM),
      GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/0, // DstI[sdst]
      GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/0, // sbase
      GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/1, // soffset
      GIR_AddImm8, /*InsnID*/0, /*Imm*/0,
      GIR_AddImm8, /*InsnID*/0, /*Imm*/0,
      GIR_MergeMemOperands, /*InsnID*/0, /*NumInsns*/1, /*MergeInsnID's*/0,
      GIR_ConstrainSelectedInstOperands, /*InsnID*/0,
      GIR_EraseFromParent, /*InsnID*/0,
      // GIR_Coverage, 7113,
      GIR_Done,
    // Label 946: @61370
    GIM_Try, /*On fail goto*//*Label 947*/ GIMT_Encode4(61439), // Rule ID 3065 //
      GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasFlatGlobalInsts),
      GIM_CheckMemoryAddressSpace, /*MI*/0, /*MMO*/0, /*NumAddrSpace*/3, /*AddrSpace*/1, /*AddrSpace*/4, /*AddrSpace*/6,
      GIM_CheckAtomicOrdering, /*MI*/0, /*Order*/(uint8_t)AtomicOrdering::NotAtomic,
      GIM_CheckRegBankForClass, /*MI*/0, /*Op*/0, /*RC*/GIMT_Encode2(AMDGPU::AV_64RegClassID),
      GIM_CheckPointerToAny, /*MI*/0, /*Op*/1, /*SizeInBits*/0,
      GIM_CheckComplexPattern, /*MI*/0, /*Op*/1, /*Renderer*/GIMT_Encode2(0), GIMT_Encode2(GICP_gi_global_saddr),
      // (ld:{ *:[i64] } (GlobalSAddr:{ *:[iPTR] } SReg_64:{ *:[i64] }:$saddr, VGPR_32:{ *:[i32] }:$voffset, i32:{ *:[i32] }:$offset))<<P:Predicate_unindexedload>><<P:Predicate_load_global>>  =>  (GLOBAL_LOAD_DWORDX2_SADDR:{ *:[i64] } ?:{ *:[i64] }:$saddr, ?:{ *:[i32] }:$voffset, ?:{ *:[i32] }:$offset, 0:{ *:[i32] })
      GIR_BuildMI, /*InsnID*/0, /*Opcode*/GIMT_Encode2(AMDGPU::GLOBAL_LOAD_DWORDX2_SADDR),
      GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/0, // DstI[vdst]
      GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/0, // saddr
      GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/1, // voffset
      GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/2, // offset
      GIR_AddImm8, /*InsnID*/0, /*Imm*/0,
      GIR_MergeMemOperands, /*InsnID*/0, /*NumInsns*/1, /*MergeInsnID's*/0,
      GIR_ConstrainSelectedInstOperands, /*InsnID*/0,
      GIR_EraseFromParent, /*InsnID*/0,
      // GIR_Coverage, 3065,
      GIR_Done,
    // Label 947: @61439
    GIM_Try, /*On fail goto*//*Label 948*/ GIMT_Encode4(61503), // Rule ID 3064 //
      GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasFlatGlobalInsts),
      GIM_CheckMemoryAddressSpace, /*MI*/0, /*MMO*/0, /*NumAddrSpace*/3, /*AddrSpace*/1, /*AddrSpace*/4, /*AddrSpace*/6,
      GIM_CheckAtomicOrdering, /*MI*/0, /*Order*/(uint8_t)AtomicOrdering::NotAtomic,
      GIM_CheckRegBankForClass, /*MI*/0, /*Op*/0, /*RC*/GIMT_Encode2(AMDGPU::AV_64RegClassID),
      GIM_CheckPointerToAny, /*MI*/0, /*Op*/1, /*SizeInBits*/0,
      GIM_CheckComplexPattern, /*MI*/0, /*Op*/1, /*Renderer*/GIMT_Encode2(0), GIMT_Encode2(GICP_gi_global_offset),
      // (ld:{ *:[i64] } (GlobalOffset:{ *:[iPTR] } VReg_64:{ *:[i64] }:$vaddr, i32:{ *:[i32] }:$offset))<<P:Predicate_unindexedload>><<P:Predicate_load_global>>  =>  (GLOBAL_LOAD_DWORDX2:{ *:[i64] } ?:{ *:[i64] }:$vaddr, ?:{ *:[i32] }:$offset)
      GIR_BuildMI, /*InsnID*/0, /*Opcode*/GIMT_Encode2(AMDGPU::GLOBAL_LOAD_DWORDX2),
      GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/0, // DstI[vdst]
      GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/0, // vaddr
      GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/1, // offset
      GIR_AddImm8, /*InsnID*/0, /*Imm*/0,
      GIR_MergeMemOperands, /*InsnID*/0, /*NumInsns*/1, /*MergeInsnID's*/0,
      GIR_ConstrainSelectedInstOperands, /*InsnID*/0,
      GIR_EraseFromParent, /*InsnID*/0,
      // GIR_Coverage, 3064,
      GIR_Done,
    // Label 948: @61503
    GIM_Try, /*On fail goto*//*Label 949*/ GIMT_Encode4(61560), // Rule ID 7115 //
      GIM_CheckMemorySizeEqualToLLT, /*MI*/0, /*MMO*/0, /*OpIdx*/0,
      GIM_CheckAtomicOrdering, /*MI*/0, /*Order*/(uint8_t)AtomicOrdering::NotAtomic,
      GIM_CheckRegBankForClass, /*MI*/0, /*Op*/0, /*RC*/GIMT_Encode2(AMDGPU::SReg_64_XEXECRegClassID),
      // MIs[0] sbase
      GIM_CheckPointerToAny, /*MI*/0, /*Op*/1, /*SizeInBits*/64,
      GIM_CheckRegBankForClass, /*MI*/0, /*Op*/1, /*RC*/GIMT_Encode2(AMDGPU::SReg_64RegClassID),
      GIM_CheckCxxInsnPredicate, /*MI*/0, /*FnId*/GIMT_Encode2(GICXXPred_MI_Predicate_smrd_load),
      // (ld:{ *:[i64] } SReg_64:{ *:[i64] }:$sbase)<<P:Predicate_unindexedload>><<P:Predicate_load>><<P:Predicate_smrd_load>>  =>  (S_LOAD_DWORDX2_IMM:{ *:[i64] } i64:{ *:[i64] }:$sbase, 0:{ *:[i32] }, 0:{ *:[i32] })
      GIR_BuildMI, /*InsnID*/0, /*Opcode*/GIMT_Encode2(AMDGPU::S_LOAD_DWORDX2_IMM),
      GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/0, // DstI[sdst]
      GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/1, // sbase
      GIR_AddImm8, /*InsnID*/0, /*Imm*/0,
      GIR_AddImm8, /*InsnID*/0, /*Imm*/0,
      GIR_MergeMemOperands, /*InsnID*/0, /*NumInsns*/1, /*MergeInsnID's*/0,
      GIR_ConstrainSelectedInstOperands, /*InsnID*/0,
      GIR_EraseFromParent, /*InsnID*/0,
      // GIR_Coverage, 7115,
      GIR_Done,
    // Label 949: @61560
    GIM_Try, /*On fail goto*//*Label 950*/ GIMT_Encode4(61625), // Rule ID 2807 //
      GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasFlatAddressSpace),
      GIM_CheckMemoryAddressSpace, /*MI*/0, /*MMO*/0, /*NumAddrSpace*/4, /*AddrSpace*/0, /*AddrSpace*/1, /*AddrSpace*/4, /*AddrSpace*/6,
      GIM_CheckAtomicOrdering, /*MI*/0, /*Order*/(uint8_t)AtomicOrdering::NotAtomic,
      GIM_CheckRegBankForClass, /*MI*/0, /*Op*/0, /*RC*/GIMT_Encode2(AMDGPU::AV_64RegClassID),
      GIM_CheckPointerToAny, /*MI*/0, /*Op*/1, /*SizeInBits*/0,
      GIM_CheckComplexPattern, /*MI*/0, /*Op*/1, /*Renderer*/GIMT_Encode2(0), GIMT_Encode2(GICP_gi_flat_offset),
      // (ld:{ *:[i64] } (FlatOffset:{ *:[iPTR] } i64:{ *:[i64] }:$vaddr, i32:{ *:[i32] }:$offset))<<P:Predicate_unindexedload>><<P:Predicate_load_flat>>  =>  (FLAT_LOAD_DWORDX2:{ *:[i64] } ?:{ *:[i64] }:$vaddr, ?:{ *:[i32] }:$offset)
      GIR_BuildMI, /*InsnID*/0, /*Opcode*/GIMT_Encode2(AMDGPU::FLAT_LOAD_DWORDX2),
      GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/0, // DstI[vdst]
      GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/0, // vaddr
      GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/1, // offset
      GIR_AddImm8, /*InsnID*/0, /*Imm*/0,
      GIR_MergeMemOperands, /*InsnID*/0, /*NumInsns*/1, /*MergeInsnID's*/0,
      GIR_ConstrainSelectedInstOperands, /*InsnID*/0,
      GIR_EraseFromParent, /*InsnID*/0,
      // GIR_Coverage, 2807,
      GIR_Done,
    // Label 950: @61625
    GIM_Reject,
    // Label 821: @61626
    GIM_Try, /*On fail goto*//*Label 951*/ GIMT_Encode4(61696), // Rule ID 2492 //
      GIM_CheckFeatures, GIMT_Encode2(GIFBS_isGFX9Plus),
      GIM_CheckMemorySizeEqualToLLT, /*MI*/0, /*MMO*/0, /*OpIdx*/0,
      GIM_CheckAtomicOrdering, /*MI*/0, /*Order*/(uint8_t)AtomicOrdering::NotAtomic,
      GIM_CheckRegBankForClass, /*MI*/0, /*Op*/0, /*RC*/GIMT_Encode2(AMDGPU::SReg_32_XM0_XEXECRegClassID),
      GIM_CheckPointerToAny, /*MI*/0, /*Op*/1, /*SizeInBits*/0,
      GIM_CheckCxxInsnPredicate, /*MI*/0, /*FnId*/GIMT_Encode2(GICXXPred_MI_Predicate_smrd_load),
      GIM_CheckComplexPattern, /*MI*/0, /*Op*/1, /*Renderer*/GIMT_Encode2(0), GIMT_Encode2(GICP_gi_smrd_sgpr_imm),
      // (ld:{ *:[i32] } (SMRDSgprImm:{ *:[iPTR] } i64:{ *:[i64] }:$sbase, i32:{ *:[i32] }:$soffset, i32:{ *:[i32] }:$offset))<<P:Predicate_unindexedload>><<P:Predicate_load>><<P:Predicate_smrd_load>>  =>  (S_LOAD_DWORD_SGPR_IMM:{ *:[i32] } ?:{ *:[i64] }:$sbase, ?:{ *:[i32] }:$soffset, ?:{ *:[i32] }:$offset, 0:{ *:[i32] })
      GIR_BuildMI, /*InsnID*/0, /*Opcode*/GIMT_Encode2(AMDGPU::S_LOAD_DWORD_SGPR_IMM),
      GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/0, // DstI[sdst]
      GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/0, // sbase
      GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/1, // soffset
      GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/2, // offset
      GIR_AddImm8, /*InsnID*/0, /*Imm*/0,
      GIR_MergeMemOperands, /*InsnID*/0, /*NumInsns*/1, /*MergeInsnID's*/0,
      GIR_ConstrainSelectedInstOperands, /*InsnID*/0,
      GIR_EraseFromParent, /*InsnID*/0,
      // GIR_Coverage, 2492,
      GIR_Done,
    // Label 951: @61696
    GIM_Try, /*On fail goto*//*Label 952*/ GIMT_Encode4(61758), // Rule ID 2488 //
      GIM_CheckMemorySizeEqualToLLT, /*MI*/0, /*MMO*/0, /*OpIdx*/0,
      GIM_CheckAtomicOrdering, /*MI*/0, /*Order*/(uint8_t)AtomicOrdering::NotAtomic,
      GIM_CheckRegBankForClass, /*MI*/0, /*Op*/0, /*RC*/GIMT_Encode2(AMDGPU::SReg_32_XM0_XEXECRegClassID),
      GIM_CheckPointerToAny, /*MI*/0, /*Op*/1, /*SizeInBits*/0,
      GIM_CheckCxxInsnPredicate, /*MI*/0, /*FnId*/GIMT_Encode2(GICXXPred_MI_Predicate_smrd_load),
      GIM_CheckComplexPattern, /*MI*/0, /*Op*/1, /*Renderer*/GIMT_Encode2(0), GIMT_Encode2(GICP_gi_smrd_imm),
      // (ld:{ *:[i32] } (SMRDImm:{ *:[iPTR] } i64:{ *:[i64] }:$sbase, i32:{ *:[i32] }:$offset))<<P:Predicate_unindexedload>><<P:Predicate_load>><<P:Predicate_smrd_load>>  =>  (S_LOAD_DWORD_IMM:{ *:[i32] } ?:{ *:[i64] }:$sbase, ?:{ *:[i32] }:$offset, 0:{ *:[i32] })
      GIR_BuildMI, /*InsnID*/0, /*Opcode*/GIMT_Encode2(AMDGPU::S_LOAD_DWORD_IMM),
      GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/0, // DstI[sdst]
      GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/0, // sbase
      GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/1, // offset
      GIR_AddImm8, /*InsnID*/0, /*Imm*/0,
      GIR_MergeMemOperands, /*InsnID*/0, /*NumInsns*/1, /*MergeInsnID's*/0,
      GIR_ConstrainSelectedInstOperands, /*InsnID*/0,
      GIR_EraseFromParent, /*InsnID*/0,
      // GIR_Coverage, 2488,
      GIR_Done,
    // Label 952: @61758
    GIM_Try, /*On fail goto*//*Label 953*/ GIMT_Encode4(61823), // Rule ID 2489 //
      GIM_CheckFeatures, GIMT_Encode2(GIFBS_isGFX7Only),
      GIM_CheckMemorySizeEqualToLLT, /*MI*/0, /*MMO*/0, /*OpIdx*/0,
      GIM_CheckAtomicOrdering, /*MI*/0, /*Order*/(uint8_t)AtomicOrdering::NotAtomic,
      GIM_CheckRegBankForClass, /*MI*/0, /*Op*/0, /*RC*/GIMT_Encode2(AMDGPU::SReg_32_XM0_XEXECRegClassID),
      GIM_CheckPointerToAny, /*MI*/0, /*Op*/1, /*SizeInBits*/0,
      GIM_CheckCxxInsnPredicate, /*MI*/0, /*FnId*/GIMT_Encode2(GICXXPred_MI_Predicate_smrd_load),
      GIM_CheckComplexPattern, /*MI*/0, /*Op*/1, /*Renderer*/GIMT_Encode2(0), GIMT_Encode2(GICP_gi_smrd_imm32),
      // (ld:{ *:[i32] } (SMRDImm32:{ *:[iPTR] } i64:{ *:[i64] }:$sbase, i32:{ *:[i32] }:$offset))<<P:Predicate_unindexedload>><<P:Predicate_load>><<P:Predicate_smrd_load>>  =>  (S_LOAD_DWORD_IMM_ci:{ *:[i32] } ?:{ *:[i64] }:$sbase, ?:{ *:[i32] }:$offset, 0:{ *:[i32] })
      GIR_BuildMI, /*InsnID*/0, /*Opcode*/GIMT_Encode2(AMDGPU::S_LOAD_DWORD_IMM_ci),
      GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/0, // DstI[sdst]
      GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/0, // sbase
      GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/1, // offset
      GIR_AddImm8, /*InsnID*/0, /*Imm*/0,
      GIR_MergeMemOperands, /*InsnID*/0, /*NumInsns*/1, /*MergeInsnID's*/0,
      GIR_ConstrainSelectedInstOperands, /*InsnID*/0,
      GIR_EraseFromParent, /*InsnID*/0,
      // GIR_Coverage, 2489,
      GIR_Done,
    // Label 953: @61823
    GIM_Try, /*On fail goto*//*Label 954*/ GIMT_Encode4(61888), // Rule ID 2490 //
      GIM_CheckFeatures, GIMT_Encode2(GIFBS_isNotGFX9Plus),
      GIM_CheckMemorySizeEqualToLLT, /*MI*/0, /*MMO*/0, /*OpIdx*/0,
      GIM_CheckAtomicOrdering, /*MI*/0, /*Order*/(uint8_t)AtomicOrdering::NotAtomic,
      GIM_CheckRegBankForClass, /*MI*/0, /*Op*/0, /*RC*/GIMT_Encode2(AMDGPU::SReg_32_XM0_XEXECRegClassID),
      GIM_CheckPointerToAny, /*MI*/0, /*Op*/1, /*SizeInBits*/0,
      GIM_CheckCxxInsnPredicate, /*MI*/0, /*FnId*/GIMT_Encode2(GICXXPred_MI_Predicate_smrd_load),
      GIM_CheckComplexPattern, /*MI*/0, /*Op*/1, /*Renderer*/GIMT_Encode2(0), GIMT_Encode2(GICP_gi_smrd_sgpr),
      // (ld:{ *:[i32] } (SMRDSgpr:{ *:[iPTR] } i64:{ *:[i64] }:$sbase, i32:{ *:[i32] }:$soffset))<<P:Predicate_unindexedload>><<P:Predicate_load>><<P:Predicate_smrd_load>>  =>  (S_LOAD_DWORD_SGPR:{ *:[i32] } ?:{ *:[i64] }:$sbase, ?:{ *:[i32] }:$soffset, 0:{ *:[i32] })
      GIR_BuildMI, /*InsnID*/0, /*Opcode*/GIMT_Encode2(AMDGPU::S_LOAD_DWORD_SGPR),
      GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/0, // DstI[sdst]
      GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/0, // sbase
      GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/1, // soffset
      GIR_AddImm8, /*InsnID*/0, /*Imm*/0,
      GIR_MergeMemOperands, /*InsnID*/0, /*NumInsns*/1, /*MergeInsnID's*/0,
      GIR_ConstrainSelectedInstOperands, /*InsnID*/0,
      GIR_EraseFromParent, /*InsnID*/0,
      // GIR_Coverage, 2490,
      GIR_Done,
    // Label 954: @61888
    GIM_Try, /*On fail goto*//*Label 955*/ GIMT_Encode4(61956), // Rule ID 2491 //
      GIM_CheckFeatures, GIMT_Encode2(GIFBS_isGFX9Plus),
      GIM_CheckMemorySizeEqualToLLT, /*MI*/0, /*MMO*/0, /*OpIdx*/0,
      GIM_CheckAtomicOrdering, /*MI*/0, /*Order*/(uint8_t)AtomicOrdering::NotAtomic,
      GIM_CheckRegBankForClass, /*MI*/0, /*Op*/0, /*RC*/GIMT_Encode2(AMDGPU::SReg_32_XM0_XEXECRegClassID),
      GIM_CheckPointerToAny, /*MI*/0, /*Op*/1, /*SizeInBits*/0,
      GIM_CheckCxxInsnPredicate, /*MI*/0, /*FnId*/GIMT_Encode2(GICXXPred_MI_Predicate_smrd_load),
      GIM_CheckComplexPattern, /*MI*/0, /*Op*/1, /*Renderer*/GIMT_Encode2(0), GIMT_Encode2(GICP_gi_smrd_sgpr),
      // (ld:{ *:[i32] } (SMRDSgpr:{ *:[iPTR] } i64:{ *:[i64] }:$sbase, i32:{ *:[i32] }:$soffset))<<P:Predicate_unindexedload>><<P:Predicate_load>><<P:Predicate_smrd_load>>  =>  (S_LOAD_DWORD_SGPR_IMM:{ *:[i32] } ?:{ *:[i64] }:$sbase, ?:{ *:[i32] }:$soffset, 0:{ *:[i32] }, 0:{ *:[i32] })
      GIR_BuildMI, /*InsnID*/0, /*Opcode*/GIMT_Encode2(AMDGPU::S_LOAD_DWORD_SGPR_IMM),
      GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/0, // DstI[sdst]
      GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/0, // sbase
      GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/1, // soffset
      GIR_AddImm8, /*InsnID*/0, /*Imm*/0,
      GIR_AddImm8, /*InsnID*/0, /*Imm*/0,
      GIR_MergeMemOperands, /*InsnID*/0, /*NumInsns*/1, /*MergeInsnID's*/0,
      GIR_ConstrainSelectedInstOperands, /*InsnID*/0,
      GIR_EraseFromParent, /*InsnID*/0,
      // GIR_Coverage, 2491,
      GIR_Done,
    // Label 955: @61956
    GIM_Try, /*On fail goto*//*Label 956*/ GIMT_Encode4(62013), // Rule ID 2493 //
      GIM_CheckMemorySizeEqualToLLT, /*MI*/0, /*MMO*/0, /*OpIdx*/0,
      GIM_CheckAtomicOrdering, /*MI*/0, /*Order*/(uint8_t)AtomicOrdering::NotAtomic,
      GIM_CheckRegBankForClass, /*MI*/0, /*Op*/0, /*RC*/GIMT_Encode2(AMDGPU::SReg_32_XM0_XEXECRegClassID),
      // MIs[0] sbase
      GIM_CheckPointerToAny, /*MI*/0, /*Op*/1, /*SizeInBits*/64,
      GIM_CheckRegBankForClass, /*MI*/0, /*Op*/1, /*RC*/GIMT_Encode2(AMDGPU::SReg_64RegClassID),
      GIM_CheckCxxInsnPredicate, /*MI*/0, /*FnId*/GIMT_Encode2(GICXXPred_MI_Predicate_smrd_load),
      // (ld:{ *:[i32] } SReg_64:{ *:[i64] }:$sbase)<<P:Predicate_unindexedload>><<P:Predicate_load>><<P:Predicate_smrd_load>>  =>  (S_LOAD_DWORD_IMM:{ *:[i32] } i64:{ *:[i64] }:$sbase, 0:{ *:[i32] }, 0:{ *:[i32] })
      GIR_BuildMI, /*InsnID*/0, /*Opcode*/GIMT_Encode2(AMDGPU::S_LOAD_DWORD_IMM),
      GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/0, // DstI[sdst]
      GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/1, // sbase
      GIR_AddImm8, /*InsnID*/0, /*Imm*/0,
      GIR_AddImm8, /*InsnID*/0, /*Imm*/0,
      GIR_MergeMemOperands, /*InsnID*/0, /*NumInsns*/1, /*MergeInsnID's*/0,
      GIR_ConstrainSelectedInstOperands, /*InsnID*/0,
      GIR_EraseFromParent, /*InsnID*/0,
      // GIR_Coverage, 2493,
      GIR_Done,
    // Label 956: @62013
    GIM_Try, /*On fail goto*//*Label 957*/ GIMT_Encode4(62083), // Rule ID 5416 //
      GIM_CheckFeatures, GIMT_Encode2(GIFBS_DisableFlatScratch_HasUnrestrictedSOffset),
      GIM_CheckMemoryAddressSpace, /*MI*/0, /*MMO*/0, /*NumAddrSpace*/1, /*AddrSpace*/5,
      GIM_CheckAtomicOrdering, /*MI*/0, /*Order*/(uint8_t)AtomicOrdering::NotAtomic,
      GIM_CheckRegBankForClass, /*MI*/0, /*Op*/0, /*RC*/GIMT_Encode2(AMDGPU::AV_32RegClassID),
      GIM_CheckPointerToAny, /*MI*/0, /*Op*/1, /*SizeInBits*/0,
      GIM_CheckComplexPattern, /*MI*/0, /*Op*/1, /*Renderer*/GIMT_Encode2(0), GIMT_Encode2(GICP_gi_mubuf_scratch_offset),
      // (ld:{ *:[i32] } (MUBUFScratchOffset:{ *:[iPTR] } v4i32:{ *:[v4i32] }:$srsrc, i32:{ *:[i32] }:$soffset, i32:{ *:[i32] }:$offset))<<P:Predicate_unindexedload>><<P:Predicate_load_private>>  =>  (BUFFER_LOAD_DWORD_OFFSET:{ *:[i32] } ?:{ *:[v4i32] }:$srsrc, ?:{ *:[i32] }:$soffset, ?:{ *:[i32] }:$offset, 0:{ *:[i32] }, 0:{ *:[i1] })
      GIR_BuildMI, /*InsnID*/0, /*Opcode*/GIMT_Encode2(AMDGPU::BUFFER_LOAD_DWORD_OFFSET),
      GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/0, // DstI[vdata]
      GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/0, // srsrc
      GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/1, // soffset
      GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/2, // offset
      GIR_AddImm8, /*InsnID*/0, /*Imm*/0,
      GIR_AddImm8, /*InsnID*/0, /*Imm*/0,
      GIR_MergeMemOperands, /*InsnID*/0, /*NumInsns*/1, /*MergeInsnID's*/0,
      GIR_ConstrainSelectedInstOperands, /*InsnID*/0,
      GIR_EraseFromParent, /*InsnID*/0,
      // GIR_Coverage, 5416,
      GIR_Done,
    // Label 957: @62083
    GIM_Try, /*On fail goto*//*Label 958*/ GIMT_Encode4(62153), // Rule ID 5418 //
      GIM_CheckFeatures, GIMT_Encode2(GIFBS_DisableFlatScratch),
      GIM_CheckMemoryAddressSpace, /*MI*/0, /*MMO*/0, /*NumAddrSpace*/1, /*AddrSpace*/5,
      GIM_CheckAtomicOrdering, /*MI*/0, /*Order*/(uint8_t)AtomicOrdering::NotAtomic,
      GIM_CheckRegBankForClass, /*MI*/0, /*Op*/0, /*RC*/GIMT_Encode2(AMDGPU::AV_32RegClassID),
      GIM_CheckPointerToAny, /*MI*/0, /*Op*/1, /*SizeInBits*/0,
      GIM_CheckComplexPattern, /*MI*/0, /*Op*/1, /*Renderer*/GIMT_Encode2(0), GIMT_Encode2(GICP_gi_mubuf_scratch_offset),
      // (ld:{ *:[i32] } (MUBUFScratchOffset:{ *:[iPTR] } v4i32:{ *:[v4i32] }:$srsrc, i32:{ *:[i32] }:$soffset, i32:{ *:[i32] }:$offset))<<P:Predicate_unindexedload>><<P:Predicate_load_private>>  =>  (BUFFER_LOAD_DWORD_VBUFFER_OFFSET:{ *:[i32] } ?:{ *:[v4i32] }:$srsrc, ?:{ *:[i32] }:$soffset, ?:{ *:[i32] }:$offset, 0:{ *:[i32] }, 0:{ *:[i1] })
      GIR_BuildMI, /*InsnID*/0, /*Opcode*/GIMT_Encode2(AMDGPU::BUFFER_LOAD_DWORD_VBUFFER_OFFSET),
      GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/0, // DstI[vdata]
      GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/0, // srsrc
      GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/1, // soffset
      GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/2, // offset
      GIR_AddImm8, /*InsnID*/0, /*Imm*/0,
      GIR_AddImm8, /*InsnID*/0, /*Imm*/0,
      GIR_MergeMemOperands, /*InsnID*/0, /*NumInsns*/1, /*MergeInsnID's*/0,
      GIR_ConstrainSelectedInstOperands, /*InsnID*/0,
      GIR_EraseFromParent, /*InsnID*/0,
      // GIR_Coverage, 5418,
      GIR_Done,
    // Label 958: @62153
    GIM_Try, /*On fail goto*//*Label 959*/ GIMT_Encode4(62220), // Rule ID 3472 //
      GIM_CheckFeatures, GIMT_Encode2(GIFBS_EnableFlatScratch_HasFlatScratchInsts_HasFlatScratchSVSMode),
      GIM_CheckMemoryAddressSpace, /*MI*/0, /*MMO*/0, /*NumAddrSpace*/1, /*AddrSpace*/5,
      GIM_CheckAtomicOrdering, /*MI*/0, /*Order*/(uint8_t)AtomicOrdering::NotAtomic,
      GIM_CheckRegBankForClass, /*MI*/0, /*Op*/0, /*RC*/GIMT_Encode2(AMDGPU::AV_32RegClassID),
      GIM_CheckPointerToAny, /*MI*/0, /*Op*/1, /*SizeInBits*/0,
      GIM_CheckComplexPattern, /*MI*/0, /*Op*/1, /*Renderer*/GIMT_Encode2(0), GIMT_Encode2(GICP_gi_flat_scratch_svaddr),
      // (ld:{ *:[i32] } (ScratchSVAddr:{ *:[iPTR] } VGPR_32:{ *:[i32] }:$vaddr, SGPR_32:{ *:[i32] }:$saddr, i32:{ *:[i32] }:$offset))<<P:Predicate_unindexedload>><<P:Predicate_load_private>>  =>  (SCRATCH_LOAD_DWORD_SVS:{ *:[i32] } ?:{ *:[i32] }:$vaddr, ?:{ *:[i32] }:$saddr, ?:{ *:[i32] }:$offset, 0:{ *:[i32] })
      GIR_BuildMI, /*InsnID*/0, /*Opcode*/GIMT_Encode2(AMDGPU::SCRATCH_LOAD_DWORD_SVS),
      GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/0, // DstI[vdst]
      GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/0, // vaddr
      GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/1, // saddr
      GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/2, // offset
      GIR_AddImm8, /*InsnID*/0, /*Imm*/0,
      GIR_MergeMemOperands, /*InsnID*/0, /*NumInsns*/1, /*MergeInsnID's*/0,
      GIR_ConstrainSelectedInstOperands, /*InsnID*/0,
      GIR_EraseFromParent, /*InsnID*/0,
      // GIR_Coverage, 3472,
      GIR_Done,
    // Label 959: @62220
    GIM_Try, /*On fail goto*//*Label 960*/ GIMT_Encode4(62282), // Rule ID 3471 //
      GIM_CheckFeatures, GIMT_Encode2(GIFBS_EnableFlatScratch_HasFlatScratchInsts),
      GIM_CheckMemoryAddressSpace, /*MI*/0, /*MMO*/0, /*NumAddrSpace*/1, /*AddrSpace*/5,
      GIM_CheckAtomicOrdering, /*MI*/0, /*Order*/(uint8_t)AtomicOrdering::NotAtomic,
      GIM_CheckRegBankForClass, /*MI*/0, /*Op*/0, /*RC*/GIMT_Encode2(AMDGPU::AV_32RegClassID),
      GIM_CheckPointerToAny, /*MI*/0, /*Op*/1, /*SizeInBits*/0,
      GIM_CheckComplexPattern, /*MI*/0, /*Op*/1, /*Renderer*/GIMT_Encode2(0), GIMT_Encode2(GICP_gi_flat_scratch_saddr),
      // (ld:{ *:[i32] } (ScratchSAddr:{ *:[iPTR] } SGPR_32:{ *:[i32] }:$saddr, i32:{ *:[i32] }:$offset))<<P:Predicate_unindexedload>><<P:Predicate_load_private>>  =>  (SCRATCH_LOAD_DWORD_SADDR:{ *:[i32] } ?:{ *:[i32] }:$saddr, ?:{ *:[i32] }:$offset)
      GIR_BuildMI, /*InsnID*/0, /*Opcode*/GIMT_Encode2(AMDGPU::SCRATCH_LOAD_DWORD_SADDR),
      GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/0, // DstI[vdst]
      GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/0, // saddr
      GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/1, // offset
      GIR_AddImm8, /*InsnID*/0, /*Imm*/0,
      GIR_MergeMemOperands, /*InsnID*/0, /*NumInsns*/1, /*MergeInsnID's*/0,
      GIR_ConstrainSelectedInstOperands, /*InsnID*/0,
      GIR_EraseFromParent, /*InsnID*/0,
      // GIR_Coverage, 3471,
      GIR_Done,
    // Label 960: @62282
    GIM_Try, /*On fail goto*//*Label 961*/ GIMT_Encode4(62344), // Rule ID 3470 //
      GIM_CheckFeatures, GIMT_Encode2(GIFBS_EnableFlatScratch_HasFlatScratchInsts),
      GIM_CheckMemoryAddressSpace, /*MI*/0, /*MMO*/0, /*NumAddrSpace*/1, /*AddrSpace*/5,
      GIM_CheckAtomicOrdering, /*MI*/0, /*Order*/(uint8_t)AtomicOrdering::NotAtomic,
      GIM_CheckRegBankForClass, /*MI*/0, /*Op*/0, /*RC*/GIMT_Encode2(AMDGPU::AV_32RegClassID),
      GIM_CheckPointerToAny, /*MI*/0, /*Op*/1, /*SizeInBits*/0,
      GIM_CheckComplexPattern, /*MI*/0, /*Op*/1, /*Renderer*/GIMT_Encode2(0), GIMT_Encode2(GICP_gi_flat_scratch_offset),
      // (ld:{ *:[i32] } (ScratchOffset:{ *:[iPTR] } VGPR_32:{ *:[i32] }:$vaddr, i32:{ *:[i32] }:$offset))<<P:Predicate_unindexedload>><<P:Predicate_load_private>>  =>  (SCRATCH_LOAD_DWORD:{ *:[i32] } ?:{ *:[i32] }:$vaddr, ?:{ *:[i32] }:$offset)
      GIR_BuildMI, /*InsnID*/0, /*Opcode*/GIMT_Encode2(AMDGPU::SCRATCH_LOAD_DWORD),
      GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/0, // DstI[vdst]
      GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/0, // vaddr
      GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/1, // offset
      GIR_AddImm8, /*InsnID*/0, /*Imm*/0,
      GIR_MergeMemOperands, /*InsnID*/0, /*NumInsns*/1, /*MergeInsnID's*/0,
      GIR_ConstrainSelectedInstOperands, /*InsnID*/0,
      GIR_EraseFromParent, /*InsnID*/0,
      // GIR_Coverage, 3470,
      GIR_Done,
    // Label 961: @62344
    GIM_Try, /*On fail goto*//*Label 962*/ GIMT_Encode4(62421), // Rule ID 3712 //
      GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasUnrestrictedSOffset),
      GIM_CheckMemoryAddressSpace, /*MI*/0, /*MMO*/0, /*NumAddrSpace*/3, /*AddrSpace*/1, /*AddrSpace*/4, /*AddrSpace*/6,
      GIM_CheckAtomicOrdering, /*MI*/0, /*Order*/(uint8_t)AtomicOrdering::NotAtomic,
      GIM_CheckRegBankForClass, /*MI*/0, /*Op*/0, /*RC*/GIMT_Encode2(AMDGPU::AV_32RegClassID),
      GIM_CheckPointerToAny, /*MI*/0, /*Op*/1, /*SizeInBits*/0,
      GIM_CheckComplexPattern, /*MI*/0, /*Op*/1, /*Renderer*/GIMT_Encode2(0), GIMT_Encode2(GICP_gi_mubuf_addr64),
      // (ld:{ *:[i32] } (MUBUFAddr64:{ *:[iPTR] } v4i32:{ *:[v4i32] }:$srsrc, i64:{ *:[i64] }:$vaddr, i32:{ *:[i32] }:$soffset, i32:{ *:[i32] }:$offset))<<P:Predicate_unindexedload>><<P:Predicate_load_global>>  =>  (BUFFER_LOAD_DWORD_ADDR64:{ *:[i32] } i64:{ *:[i64] }:$vaddr, v4i32:{ *:[v4i32] }:$srsrc, i32:{ *:[i32] }:$soffset, i32:{ *:[i32] }:$offset)
      GIR_BuildMI, /*InsnID*/0, /*Opcode*/GIMT_Encode2(AMDGPU::BUFFER_LOAD_DWORD_ADDR64),
      GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/0, // DstI[vdata]
      GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/1, // vaddr
      GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/0, // srsrc
      GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/2, // soffset
      GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/3, // offset
      GIR_AddImm8, /*InsnID*/0, /*Imm*/0,
      GIR_AddImm8, /*InsnID*/0, /*Imm*/0,
      GIR_MergeMemOperands, /*InsnID*/0, /*NumInsns*/1, /*MergeInsnID's*/0,
      GIR_ConstrainSelectedInstOperands, /*InsnID*/0,
      GIR_EraseFromParent, /*InsnID*/0,
      // GIR_Coverage, 3712,
      GIR_Done,
    // Label 962: @62421
    GIM_Try, /*On fail goto*//*Label 963*/ GIMT_Encode4(62495), // Rule ID 3714 //
      GIM_CheckMemoryAddressSpace, /*MI*/0, /*MMO*/0, /*NumAddrSpace*/3, /*AddrSpace*/1, /*AddrSpace*/4, /*AddrSpace*/6,
      GIM_CheckAtomicOrdering, /*MI*/0, /*Order*/(uint8_t)AtomicOrdering::NotAtomic,
      GIM_CheckRegBankForClass, /*MI*/0, /*Op*/0, /*RC*/GIMT_Encode2(AMDGPU::AV_32RegClassID),
      GIM_CheckPointerToAny, /*MI*/0, /*Op*/1, /*SizeInBits*/0,
      GIM_CheckComplexPattern, /*MI*/0, /*Op*/1, /*Renderer*/GIMT_Encode2(0), GIMT_Encode2(GICP_gi_mubuf_addr64),
      // (ld:{ *:[i32] } (MUBUFAddr64:{ *:[iPTR] } v4i32:{ *:[v4i32] }:$srsrc, i64:{ *:[i64] }:$vaddr, i32:{ *:[i32] }:$soffset, i32:{ *:[i32] }:$offset))<<P:Predicate_unindexedload>><<P:Predicate_load_global>>  =>  (BUFFER_LOAD_DWORD_VBUFFER_ADDR64:{ *:[i32] } i64:{ *:[i64] }:$vaddr, v4i32:{ *:[v4i32] }:$srsrc, i32:{ *:[i32] }:$soffset, i32:{ *:[i32] }:$offset)
      GIR_BuildMI, /*InsnID*/0, /*Opcode*/GIMT_Encode2(AMDGPU::BUFFER_LOAD_DWORD_VBUFFER_ADDR64),
      GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/0, // DstI[vdata]
      GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/1, // vaddr
      GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/0, // srsrc
      GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/2, // soffset
      GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/3, // offset
      GIR_AddImm8, /*InsnID*/0, /*Imm*/0,
      GIR_AddImm8, /*InsnID*/0, /*Imm*/0,
      GIR_MergeMemOperands, /*InsnID*/0, /*NumInsns*/1, /*MergeInsnID's*/0,
      GIR_ConstrainSelectedInstOperands, /*InsnID*/0,
      GIR_EraseFromParent, /*InsnID*/0,
      // GIR_Coverage, 3714,
      GIR_Done,
    // Label 963: @62495
    GIM_Try, /*On fail goto*//*Label 964*/ GIMT_Encode4(62570), // Rule ID 5415 //
      GIM_CheckFeatures, GIMT_Encode2(GIFBS_DisableFlatScratch_HasUnrestrictedSOffset),
      GIM_CheckMemoryAddressSpace, /*MI*/0, /*MMO*/0, /*NumAddrSpace*/1, /*AddrSpace*/5,
      GIM_CheckAtomicOrdering, /*MI*/0, /*Order*/(uint8_t)AtomicOrdering::NotAtomic,
      GIM_CheckRegBankForClass, /*MI*/0, /*Op*/0, /*RC*/GIMT_Encode2(AMDGPU::AV_32RegClassID),
      GIM_CheckPointerToAny, /*MI*/0, /*Op*/1, /*SizeInBits*/0,
      GIM_CheckComplexPattern, /*MI*/0, /*Op*/1, /*Renderer*/GIMT_Encode2(0), GIMT_Encode2(GICP_gi_mubuf_scratch_offen),
      // (ld:{ *:[i32] } (MUBUFScratchOffen:{ *:[iPTR] } v4i32:{ *:[v4i32] }:$srsrc, i32:{ *:[i32] }:$vaddr, i32:{ *:[i32] }:$soffset, i32:{ *:[i32] }:$offset))<<P:Predicate_unindexedload>><<P:Predicate_load_private>>  =>  (BUFFER_LOAD_DWORD_OFFEN:{ *:[i32] } ?:{ *:[i32] }:$vaddr, ?:{ *:[v4i32] }:$srsrc, ?:{ *:[i32] }:$soffset, ?:{ *:[i32] }:$offset, 0:{ *:[i32] }, 0:{ *:[i1] })
      GIR_BuildMI, /*InsnID*/0, /*Opcode*/GIMT_Encode2(AMDGPU::BUFFER_LOAD_DWORD_OFFEN),
      GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/0, // DstI[vdata]
      GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/1, // vaddr
      GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/0, // srsrc
      GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/2, // soffset
      GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/3, // offset
      GIR_AddImm8, /*InsnID*/0, /*Imm*/0,
      GIR_AddImm8, /*InsnID*/0, /*Imm*/0,
      GIR_MergeMemOperands, /*InsnID*/0, /*NumInsns*/1, /*MergeInsnID's*/0,
      GIR_ConstrainSelectedInstOperands, /*InsnID*/0,
      GIR_EraseFromParent, /*InsnID*/0,
      // GIR_Coverage, 5415,
      GIR_Done,
    // Label 964: @62570
    GIM_Try, /*On fail goto*//*Label 965*/ GIMT_Encode4(62645), // Rule ID 5417 //
      GIM_CheckFeatures, GIMT_Encode2(GIFBS_DisableFlatScratch),
      GIM_CheckMemoryAddressSpace, /*MI*/0, /*MMO*/0, /*NumAddrSpace*/1, /*AddrSpace*/5,
      GIM_CheckAtomicOrdering, /*MI*/0, /*Order*/(uint8_t)AtomicOrdering::NotAtomic,
      GIM_CheckRegBankForClass, /*MI*/0, /*Op*/0, /*RC*/GIMT_Encode2(AMDGPU::AV_32RegClassID),
      GIM_CheckPointerToAny, /*MI*/0, /*Op*/1, /*SizeInBits*/0,
      GIM_CheckComplexPattern, /*MI*/0, /*Op*/1, /*Renderer*/GIMT_Encode2(0), GIMT_Encode2(GICP_gi_mubuf_scratch_offen),
      // (ld:{ *:[i32] } (MUBUFScratchOffen:{ *:[iPTR] } v4i32:{ *:[v4i32] }:$srsrc, i32:{ *:[i32] }:$vaddr, i32:{ *:[i32] }:$soffset, i32:{ *:[i32] }:$offset))<<P:Predicate_unindexedload>><<P:Predicate_load_private>>  =>  (BUFFER_LOAD_DWORD_VBUFFER_OFFEN:{ *:[i32] } ?:{ *:[i32] }:$vaddr, ?:{ *:[v4i32] }:$srsrc, ?:{ *:[i32] }:$soffset, ?:{ *:[i32] }:$offset, 0:{ *:[i32] }, 0:{ *:[i1] })
      GIR_BuildMI, /*InsnID*/0, /*Opcode*/GIMT_Encode2(AMDGPU::BUFFER_LOAD_DWORD_VBUFFER_OFFEN),
      GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/0, // DstI[vdata]
      GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/1, // vaddr
      GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/0, // srsrc
      GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/2, // soffset
      GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/3, // offset
      GIR_AddImm8, /*InsnID*/0, /*Imm*/0,
      GIR_AddImm8, /*InsnID*/0, /*Imm*/0,
      GIR_MergeMemOperands, /*InsnID*/0, /*NumInsns*/1, /*MergeInsnID's*/0,
      GIR_ConstrainSelectedInstOperands, /*InsnID*/0,
      GIR_EraseFromParent, /*InsnID*/0,
      // GIR_Coverage, 5417,
      GIR_Done,
    // Label 965: @62645
    GIM_Try, /*On fail goto*//*Label 966*/ GIMT_Encode4(62717), // Rule ID 3711 //
      GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasUnrestrictedSOffset),
      GIM_CheckMemoryAddressSpace, /*MI*/0, /*MMO*/0, /*NumAddrSpace*/3, /*AddrSpace*/1, /*AddrSpace*/4, /*AddrSpace*/6,
      GIM_CheckAtomicOrdering, /*MI*/0, /*Order*/(uint8_t)AtomicOrdering::NotAtomic,
      GIM_CheckRegBankForClass, /*MI*/0, /*Op*/0, /*RC*/GIMT_Encode2(AMDGPU::AV_32RegClassID),
      GIM_CheckPointerToAny, /*MI*/0, /*Op*/1, /*SizeInBits*/0,
      GIM_CheckComplexPattern, /*MI*/0, /*Op*/1, /*Renderer*/GIMT_Encode2(0), GIMT_Encode2(GICP_gi_mubuf_offset),
      // (ld:{ *:[i32] } (MUBUFOffset:{ *:[iPTR] } v4i32:{ *:[v4i32] }:$srsrc, i32:{ *:[i32] }:$soffset, i32:{ *:[i32] }:$offset))<<P:Predicate_unindexedload>><<P:Predicate_load_global>>  =>  (BUFFER_LOAD_DWORD_OFFSET:{ *:[i32] } v4i32:{ *:[v4i32] }:$srsrc, i32:{ *:[i32] }:$soffset, i32:{ *:[i32] }:$offset)
      GIR_BuildMI, /*InsnID*/0, /*Opcode*/GIMT_Encode2(AMDGPU::BUFFER_LOAD_DWORD_OFFSET),
      GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/0, // DstI[vdata]
      GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/0, // srsrc
      GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/1, // soffset
      GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/2, // offset
      GIR_AddImm8, /*InsnID*/0, /*Imm*/0,
      GIR_AddImm8, /*InsnID*/0, /*Imm*/0,
      GIR_MergeMemOperands, /*InsnID*/0, /*NumInsns*/1, /*MergeInsnID's*/0,
      GIR_ConstrainSelectedInstOperands, /*InsnID*/0,
      GIR_EraseFromParent, /*InsnID*/0,
      // GIR_Coverage, 3711,
      GIR_Done,
    // Label 966: @62717
    GIM_Try, /*On fail goto*//*Label 967*/ GIMT_Encode4(62786), // Rule ID 3713 //
      GIM_CheckMemoryAddressSpace, /*MI*/0, /*MMO*/0, /*NumAddrSpace*/3, /*AddrSpace*/1, /*AddrSpace*/4, /*AddrSpace*/6,
      GIM_CheckAtomicOrdering, /*MI*/0, /*Order*/(uint8_t)AtomicOrdering::NotAtomic,
      GIM_CheckRegBankForClass, /*MI*/0, /*Op*/0, /*RC*/GIMT_Encode2(AMDGPU::AV_32RegClassID),
      GIM_CheckPointerToAny, /*MI*/0, /*Op*/1, /*SizeInBits*/0,
      GIM_CheckComplexPattern, /*MI*/0, /*Op*/1, /*Renderer*/GIMT_Encode2(0), GIMT_Encode2(GICP_gi_mubuf_offset),
      // (ld:{ *:[i32] } (MUBUFOffset:{ *:[iPTR] } v4i32:{ *:[v4i32] }:$srsrc, i32:{ *:[i32] }:$soffset, i32:{ *:[i32] }:$offset))<<P:Predicate_unindexedload>><<P:Predicate_load_global>>  =>  (BUFFER_LOAD_DWORD_VBUFFER_OFFSET:{ *:[i32] } v4i32:{ *:[v4i32] }:$srsrc, i32:{ *:[i32] }:$soffset, i32:{ *:[i32] }:$offset)
      GIR_BuildMI, /*InsnID*/0, /*Opcode*/GIMT_Encode2(AMDGPU::BUFFER_LOAD_DWORD_VBUFFER_OFFSET),
      GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/0, // DstI[vdata]
      GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/0, // srsrc
      GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/1, // soffset
      GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/2, // offset
      GIR_AddImm8, /*InsnID*/0, /*Imm*/0,
      GIR_AddImm8, /*InsnID*/0, /*Imm*/0,
      GIR_MergeMemOperands, /*InsnID*/0, /*NumInsns*/1, /*MergeInsnID's*/0,
      GIR_ConstrainSelectedInstOperands, /*InsnID*/0,
      GIR_EraseFromParent, /*InsnID*/0,
      // GIR_Coverage, 3713,
      GIR_Done,
    // Label 967: @62786
    GIM_Try, /*On fail goto*//*Label 968*/ GIMT_Encode4(62852), // Rule ID 6603 //
      GIM_CheckFeatures, GIMT_Encode2(GIFBS_LDSRequiresM0Init),
      GIM_CheckMemorySizeEqualToLLT, /*MI*/0, /*MMO*/0, /*OpIdx*/0,
      GIM_CheckMemoryAddressSpace, /*MI*/0, /*MMO*/0, /*NumAddrSpace*/1, /*AddrSpace*/3,
      GIM_CheckAtomicOrdering, /*MI*/0, /*Order*/(uint8_t)AtomicOrdering::NotAtomic,
      GIM_CheckRegBankForClass, /*MI*/0, /*Op*/0, /*RC*/GIMT_Encode2(AMDGPU::AV_32RegClassID),
      GIM_CheckPointerToAny, /*MI*/0, /*Op*/1, /*SizeInBits*/0,
      GIM_CheckComplexPattern, /*MI*/0, /*Op*/1, /*Renderer*/GIMT_Encode2(0), GIMT_Encode2(GICP_gi_ds_1addr_1offset),
      // (AMDGPUld_glue:{ *:[i32] } (DS1Addr1Offset:{ *:[iPTR] } i32:{ *:[i32] }:$ptr, i32:{ *:[i32] }:$offset))<<P:Predicate_unindexedload_glue>><<P:Predicate_load_glue>><<P:Predicate_load_local_m0>>  =>  (DS_READ_B32:{ *:[i32] } ?:{ *:[i32] }:$ptr, offset:{ *:[i32] }:$offset, 0:{ *:[i1] })
      GIR_BuildMI, /*InsnID*/0, /*Opcode*/GIMT_Encode2(AMDGPU::DS_READ_B32),
      GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/0, // DstI[vdst]
      GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/0, // ptr
      GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/1, // offset
      GIR_AddImm8, /*InsnID*/0, /*Imm*/0,
      GIR_MergeMemOperands, /*InsnID*/0, /*NumInsns*/1, /*MergeInsnID's*/0,
      GIR_ConstrainSelectedInstOperands, /*InsnID*/0,
      GIR_EraseFromParent, /*InsnID*/0,
      // GIR_Coverage, 6603,
      GIR_Done,
    // Label 968: @62852
    GIM_Try, /*On fail goto*//*Label 969*/ GIMT_Encode4(62914), // Rule ID 6604 //
      GIM_CheckFeatures, GIMT_Encode2(GIFBS_NotLDSRequiresM0Init),
      GIM_CheckMemoryAddressSpace, /*MI*/0, /*MMO*/0, /*NumAddrSpace*/1, /*AddrSpace*/3,
      GIM_CheckAtomicOrdering, /*MI*/0, /*Order*/(uint8_t)AtomicOrdering::NotAtomic,
      GIM_CheckRegBankForClass, /*MI*/0, /*Op*/0, /*RC*/GIMT_Encode2(AMDGPU::AV_32RegClassID),
      GIM_CheckPointerToAny, /*MI*/0, /*Op*/1, /*SizeInBits*/0,
      GIM_CheckComplexPattern, /*MI*/0, /*Op*/1, /*Renderer*/GIMT_Encode2(0), GIMT_Encode2(GICP_gi_ds_1addr_1offset),
      // (ld:{ *:[i32] } (DS1Addr1Offset:{ *:[iPTR] } i32:{ *:[i32] }:$ptr, i32:{ *:[i32] }:$offset))<<P:Predicate_unindexedload>><<P:Predicate_load_local>>  =>  (DS_READ_B32_gfx9:{ *:[i32] } ?:{ *:[i32] }:$ptr, offset:{ *:[i32] }:$offset, 0:{ *:[i1] })
      GIR_BuildMI, /*InsnID*/0, /*Opcode*/GIMT_Encode2(AMDGPU::DS_READ_B32_gfx9),
      GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/0, // DstI[vdst]
      GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/0, // ptr
      GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/1, // offset
      GIR_AddImm8, /*InsnID*/0, /*Imm*/0,
      GIR_MergeMemOperands, /*InsnID*/0, /*NumInsns*/1, /*MergeInsnID's*/0,
      GIR_ConstrainSelectedInstOperands, /*InsnID*/0,
      GIR_EraseFromParent, /*InsnID*/0,
      // GIR_Coverage, 6604,
      GIR_Done,
    // Label 969: @62914
    GIM_Try, /*On fail goto*//*Label 970*/ GIMT_Encode4(62983), // Rule ID 3021 //
      GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasFlatGlobalInsts),
      GIM_CheckMemoryAddressSpace, /*MI*/0, /*MMO*/0, /*NumAddrSpace*/3, /*AddrSpace*/1, /*AddrSpace*/4, /*AddrSpace*/6,
      GIM_CheckAtomicOrdering, /*MI*/0, /*Order*/(uint8_t)AtomicOrdering::NotAtomic,
      GIM_CheckRegBankForClass, /*MI*/0, /*Op*/0, /*RC*/GIMT_Encode2(AMDGPU::AV_32RegClassID),
      GIM_CheckPointerToAny, /*MI*/0, /*Op*/1, /*SizeInBits*/0,
      GIM_CheckComplexPattern, /*MI*/0, /*Op*/1, /*Renderer*/GIMT_Encode2(0), GIMT_Encode2(GICP_gi_global_saddr),
      // (ld:{ *:[i32] } (GlobalSAddr:{ *:[iPTR] } SReg_64:{ *:[i64] }:$saddr, VGPR_32:{ *:[i32] }:$voffset, i32:{ *:[i32] }:$offset))<<P:Predicate_unindexedload>><<P:Predicate_load_global>>  =>  (GLOBAL_LOAD_DWORD_SADDR:{ *:[i32] } ?:{ *:[i64] }:$saddr, ?:{ *:[i32] }:$voffset, ?:{ *:[i32] }:$offset, 0:{ *:[i32] })
      GIR_BuildMI, /*InsnID*/0, /*Opcode*/GIMT_Encode2(AMDGPU::GLOBAL_LOAD_DWORD_SADDR),
      GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/0, // DstI[vdst]
      GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/0, // saddr
      GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/1, // voffset
      GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/2, // offset
      GIR_AddImm8, /*InsnID*/0, /*Imm*/0,
      GIR_MergeMemOperands, /*InsnID*/0, /*NumInsns*/1, /*MergeInsnID's*/0,
      GIR_ConstrainSelectedInstOperands, /*InsnID*/0,
      GIR_EraseFromParent, /*InsnID*/0,
      // GIR_Coverage, 3021,
      GIR_Done,
    // Label 970: @62983
    GIM_Try, /*On fail goto*//*Label 971*/ GIMT_Encode4(63047), // Rule ID 3020 //
      GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasFlatGlobalInsts),
      GIM_CheckMemoryAddressSpace, /*MI*/0, /*MMO*/0, /*NumAddrSpace*/3, /*AddrSpace*/1, /*AddrSpace*/4, /*AddrSpace*/6,
      GIM_CheckAtomicOrdering, /*MI*/0, /*Order*/(uint8_t)AtomicOrdering::NotAtomic,
      GIM_CheckRegBankForClass, /*MI*/0, /*Op*/0, /*RC*/GIMT_Encode2(AMDGPU::AV_32RegClassID),
      GIM_CheckPointerToAny, /*MI*/0, /*Op*/1, /*SizeInBits*/0,
      GIM_CheckComplexPattern, /*MI*/0, /*Op*/1, /*Renderer*/GIMT_Encode2(0), GIMT_Encode2(GICP_gi_global_offset),
      // (ld:{ *:[i32] } (GlobalOffset:{ *:[iPTR] } VReg_64:{ *:[i64] }:$vaddr, i32:{ *:[i32] }:$offset))<<P:Predicate_unindexedload>><<P:Predicate_load_global>>  =>  (GLOBAL_LOAD_DWORD:{ *:[i32] } ?:{ *:[i64] }:$vaddr, ?:{ *:[i32] }:$offset)
      GIR_BuildMI, /*InsnID*/0, /*Opcode*/GIMT_Encode2(AMDGPU::GLOBAL_LOAD_DWORD),
      GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/0, // DstI[vdst]
      GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/0, // vaddr
      GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/1, // offset
      GIR_AddImm8, /*InsnID*/0, /*Imm*/0,
      GIR_MergeMemOperands, /*InsnID*/0, /*NumInsns*/1, /*MergeInsnID's*/0,
      GIR_ConstrainSelectedInstOperands, /*InsnID*/0,
      GIR_EraseFromParent, /*InsnID*/0,
      // GIR_Coverage, 3020,
      GIR_Done,
    // Label 971: @63047
    GIM_Try, /*On fail goto*//*Label 972*/ GIMT_Encode4(63112), // Rule ID 2784 //
      GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasFlatAddressSpace),
      GIM_CheckMemoryAddressSpace, /*MI*/0, /*MMO*/0, /*NumAddrSpace*/4, /*AddrSpace*/0, /*AddrSpace*/1, /*AddrSpace*/4, /*AddrSpace*/6,
      GIM_CheckAtomicOrdering, /*MI*/0, /*Order*/(uint8_t)AtomicOrdering::NotAtomic,
      GIM_CheckRegBankForClass, /*MI*/0, /*Op*/0, /*RC*/GIMT_Encode2(AMDGPU::AV_32RegClassID),
      GIM_CheckPointerToAny, /*MI*/0, /*Op*/1, /*SizeInBits*/0,
      GIM_CheckComplexPattern, /*MI*/0, /*Op*/1, /*Renderer*/GIMT_Encode2(0), GIMT_Encode2(GICP_gi_flat_offset),
      // (ld:{ *:[i32] } (FlatOffset:{ *:[iPTR] } i64:{ *:[i64] }:$vaddr, i32:{ *:[i32] }:$offset))<<P:Predicate_unindexedload>><<P:Predicate_load_flat>>  =>  (FLAT_LOAD_DWORD:{ *:[i32] } ?:{ *:[i64] }:$vaddr, ?:{ *:[i32] }:$offset)
      GIR_BuildMI, /*InsnID*/0, /*Opcode*/GIMT_Encode2(AMDGPU::FLAT_LOAD_DWORD),
      GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/0, // DstI[vdst]
      GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/0, // vaddr
      GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/1, // offset
      GIR_AddImm8, /*InsnID*/0, /*Imm*/0,
      GIR_MergeMemOperands, /*InsnID*/0, /*NumInsns*/1, /*MergeInsnID's*/0,
      GIR_ConstrainSelectedInstOperands, /*InsnID*/0,
      GIR_EraseFromParent, /*InsnID*/0,
      // GIR_Coverage, 2784,
      GIR_Done,
    // Label 972: @63112
    GIM_Reject,
    // Label 822: @63113
    GIM_Try, /*On fail goto*//*Label 973*/ GIMT_Encode4(63183), // Rule ID 2498 //
      GIM_CheckFeatures, GIMT_Encode2(GIFBS_isGFX9Plus),
      GIM_CheckMemorySizeEqualToLLT, /*MI*/0, /*MMO*/0, /*OpIdx*/0,
      GIM_CheckAtomicOrdering, /*MI*/0, /*Order*/(uint8_t)AtomicOrdering::NotAtomic,
      GIM_CheckRegBankForClass, /*MI*/0, /*Op*/0, /*RC*/GIMT_Encode2(AMDGPU::SReg_32_XM0_XEXECRegClassID),
      GIM_CheckPointerToAny, /*MI*/0, /*Op*/1, /*SizeInBits*/0,
      GIM_CheckCxxInsnPredicate, /*MI*/0, /*FnId*/GIMT_Encode2(GICXXPred_MI_Predicate_smrd_load),
      GIM_CheckComplexPattern, /*MI*/0, /*Op*/1, /*Renderer*/GIMT_Encode2(0), GIMT_Encode2(GICP_gi_smrd_sgpr_imm),
      // (ld:{ *:[i32] } (SMRDSgprImm:{ *:[iPTR] } i64:{ *:[i64] }:$sbase, i32:{ *:[i32] }:$soffset, i32:{ *:[i32] }:$offset))<<P:Predicate_unindexedload>><<P:Predicate_load>><<P:Predicate_smrd_load>>  =>  (S_LOAD_DWORD_SGPR_IMM:{ *:[i32] } ?:{ *:[i64] }:$sbase, ?:{ *:[i32] }:$soffset, ?:{ *:[i32] }:$offset, 0:{ *:[i32] })
      GIR_BuildMI, /*InsnID*/0, /*Opcode*/GIMT_Encode2(AMDGPU::S_LOAD_DWORD_SGPR_IMM),
      GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/0, // DstI[sdst]
      GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/0, // sbase
      GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/1, // soffset
      GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/2, // offset
      GIR_AddImm8, /*InsnID*/0, /*Imm*/0,
      GIR_MergeMemOperands, /*InsnID*/0, /*NumInsns*/1, /*MergeInsnID's*/0,
      GIR_ConstrainSelectedInstOperands, /*InsnID*/0,
      GIR_EraseFromParent, /*InsnID*/0,
      // GIR_Coverage, 2498,
      GIR_Done,
    // Label 973: @63183
    GIM_Try, /*On fail goto*//*Label 974*/ GIMT_Encode4(63245), // Rule ID 2494 //
      GIM_CheckMemorySizeEqualToLLT, /*MI*/0, /*MMO*/0, /*OpIdx*/0,
      GIM_CheckAtomicOrdering, /*MI*/0, /*Order*/(uint8_t)AtomicOrdering::NotAtomic,
      GIM_CheckRegBankForClass, /*MI*/0, /*Op*/0, /*RC*/GIMT_Encode2(AMDGPU::SReg_32_XM0_XEXECRegClassID),
      GIM_CheckPointerToAny, /*MI*/0, /*Op*/1, /*SizeInBits*/0,
      GIM_CheckCxxInsnPredicate, /*MI*/0, /*FnId*/GIMT_Encode2(GICXXPred_MI_Predicate_smrd_load),
      GIM_CheckComplexPattern, /*MI*/0, /*Op*/1, /*Renderer*/GIMT_Encode2(0), GIMT_Encode2(GICP_gi_smrd_imm),
      // (ld:{ *:[i32] } (SMRDImm:{ *:[iPTR] } i64:{ *:[i64] }:$sbase, i32:{ *:[i32] }:$offset))<<P:Predicate_unindexedload>><<P:Predicate_load>><<P:Predicate_smrd_load>>  =>  (S_LOAD_DWORD_IMM:{ *:[i32] } ?:{ *:[i64] }:$sbase, ?:{ *:[i32] }:$offset, 0:{ *:[i32] })
      GIR_BuildMI, /*InsnID*/0, /*Opcode*/GIMT_Encode2(AMDGPU::S_LOAD_DWORD_IMM),
      GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/0, // DstI[sdst]
      GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/0, // sbase
      GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/1, // offset
      GIR_AddImm8, /*InsnID*/0, /*Imm*/0,
      GIR_MergeMemOperands, /*InsnID*/0, /*NumInsns*/1, /*MergeInsnID's*/0,
      GIR_ConstrainSelectedInstOperands, /*InsnID*/0,
      GIR_EraseFromParent, /*InsnID*/0,
      // GIR_Coverage, 2494,
      GIR_Done,
    // Label 974: @63245
    GIM_Try, /*On fail goto*//*Label 975*/ GIMT_Encode4(63310), // Rule ID 2495 //
      GIM_CheckFeatures, GIMT_Encode2(GIFBS_isGFX7Only),
      GIM_CheckMemorySizeEqualToLLT, /*MI*/0, /*MMO*/0, /*OpIdx*/0,
      GIM_CheckAtomicOrdering, /*MI*/0, /*Order*/(uint8_t)AtomicOrdering::NotAtomic,
      GIM_CheckRegBankForClass, /*MI*/0, /*Op*/0, /*RC*/GIMT_Encode2(AMDGPU::SReg_32_XM0_XEXECRegClassID),
      GIM_CheckPointerToAny, /*MI*/0, /*Op*/1, /*SizeInBits*/0,
      GIM_CheckCxxInsnPredicate, /*MI*/0, /*FnId*/GIMT_Encode2(GICXXPred_MI_Predicate_smrd_load),
      GIM_CheckComplexPattern, /*MI*/0, /*Op*/1, /*Renderer*/GIMT_Encode2(0), GIMT_Encode2(GICP_gi_smrd_imm32),
      // (ld:{ *:[i32] } (SMRDImm32:{ *:[iPTR] } i64:{ *:[i64] }:$sbase, i32:{ *:[i32] }:$offset))<<P:Predicate_unindexedload>><<P:Predicate_load>><<P:Predicate_smrd_load>>  =>  (S_LOAD_DWORD_IMM_ci:{ *:[i32] } ?:{ *:[i64] }:$sbase, ?:{ *:[i32] }:$offset, 0:{ *:[i32] })
      GIR_BuildMI, /*InsnID*/0, /*Opcode*/GIMT_Encode2(AMDGPU::S_LOAD_DWORD_IMM_ci),
      GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/0, // DstI[sdst]
      GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/0, // sbase
      GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/1, // offset
      GIR_AddImm8, /*InsnID*/0, /*Imm*/0,
      GIR_MergeMemOperands, /*InsnID*/0, /*NumInsns*/1, /*MergeInsnID's*/0,
      GIR_ConstrainSelectedInstOperands, /*InsnID*/0,
      GIR_EraseFromParent, /*InsnID*/0,
      // GIR_Coverage, 2495,
      GIR_Done,
    // Label 975: @63310
    GIM_Try, /*On fail goto*//*Label 976*/ GIMT_Encode4(63375), // Rule ID 2496 //
      GIM_CheckFeatures, GIMT_Encode2(GIFBS_isNotGFX9Plus),
      GIM_CheckMemorySizeEqualToLLT, /*MI*/0, /*MMO*/0, /*OpIdx*/0,
      GIM_CheckAtomicOrdering, /*MI*/0, /*Order*/(uint8_t)AtomicOrdering::NotAtomic,
      GIM_CheckRegBankForClass, /*MI*/0, /*Op*/0, /*RC*/GIMT_Encode2(AMDGPU::SReg_32_XM0_XEXECRegClassID),
      GIM_CheckPointerToAny, /*MI*/0, /*Op*/1, /*SizeInBits*/0,
      GIM_CheckCxxInsnPredicate, /*MI*/0, /*FnId*/GIMT_Encode2(GICXXPred_MI_Predicate_smrd_load),
      GIM_CheckComplexPattern, /*MI*/0, /*Op*/1, /*Renderer*/GIMT_Encode2(0), GIMT_Encode2(GICP_gi_smrd_sgpr),
      // (ld:{ *:[i32] } (SMRDSgpr:{ *:[iPTR] } i64:{ *:[i64] }:$sbase, i32:{ *:[i32] }:$soffset))<<P:Predicate_unindexedload>><<P:Predicate_load>><<P:Predicate_smrd_load>>  =>  (S_LOAD_DWORD_SGPR:{ *:[i32] } ?:{ *:[i64] }:$sbase, ?:{ *:[i32] }:$soffset, 0:{ *:[i32] })
      GIR_BuildMI, /*InsnID*/0, /*Opcode*/GIMT_Encode2(AMDGPU::S_LOAD_DWORD_SGPR),
      GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/0, // DstI[sdst]
      GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/0, // sbase
      GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/1, // soffset
      GIR_AddImm8, /*InsnID*/0, /*Imm*/0,
      GIR_MergeMemOperands, /*InsnID*/0, /*NumInsns*/1, /*MergeInsnID's*/0,
      GIR_ConstrainSelectedInstOperands, /*InsnID*/0,
      GIR_EraseFromParent, /*InsnID*/0,
      // GIR_Coverage, 2496,
      GIR_Done,
    // Label 976: @63375
    GIM_Try, /*On fail goto*//*Label 977*/ GIMT_Encode4(63443), // Rule ID 2497 //
      GIM_CheckFeatures, GIMT_Encode2(GIFBS_isGFX9Plus),
      GIM_CheckMemorySizeEqualToLLT, /*MI*/0, /*MMO*/0, /*OpIdx*/0,
      GIM_CheckAtomicOrdering, /*MI*/0, /*Order*/(uint8_t)AtomicOrdering::NotAtomic,
      GIM_CheckRegBankForClass, /*MI*/0, /*Op*/0, /*RC*/GIMT_Encode2(AMDGPU::SReg_32_XM0_XEXECRegClassID),
      GIM_CheckPointerToAny, /*MI*/0, /*Op*/1, /*SizeInBits*/0,
      GIM_CheckCxxInsnPredicate, /*MI*/0, /*FnId*/GIMT_Encode2(GICXXPred_MI_Predicate_smrd_load),
      GIM_CheckComplexPattern, /*MI*/0, /*Op*/1, /*Renderer*/GIMT_Encode2(0), GIMT_Encode2(GICP_gi_smrd_sgpr),
      // (ld:{ *:[i32] } (SMRDSgpr:{ *:[iPTR] } i64:{ *:[i64] }:$sbase, i32:{ *:[i32] }:$soffset))<<P:Predicate_unindexedload>><<P:Predicate_load>><<P:Predicate_smrd_load>>  =>  (S_LOAD_DWORD_SGPR_IMM:{ *:[i32] } ?:{ *:[i64] }:$sbase, ?:{ *:[i32] }:$soffset, 0:{ *:[i32] }, 0:{ *:[i32] })
      GIR_BuildMI, /*InsnID*/0, /*Opcode*/GIMT_Encode2(AMDGPU::S_LOAD_DWORD_SGPR_IMM),
      GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/0, // DstI[sdst]
      GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/0, // sbase
      GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/1, // soffset
      GIR_AddImm8, /*InsnID*/0, /*Imm*/0,
      GIR_AddImm8, /*InsnID*/0, /*Imm*/0,
      GIR_MergeMemOperands, /*InsnID*/0, /*NumInsns*/1, /*MergeInsnID's*/0,
      GIR_ConstrainSelectedInstOperands, /*InsnID*/0,
      GIR_EraseFromParent, /*InsnID*/0,
      // GIR_Coverage, 2497,
      GIR_Done,
    // Label 977: @63443
    GIM_Try, /*On fail goto*//*Label 978*/ GIMT_Encode4(63500), // Rule ID 2499 //
      GIM_CheckMemorySizeEqualToLLT, /*MI*/0, /*MMO*/0, /*OpIdx*/0,
      GIM_CheckAtomicOrdering, /*MI*/0, /*Order*/(uint8_t)AtomicOrdering::NotAtomic,
      GIM_CheckRegBankForClass, /*MI*/0, /*Op*/0, /*RC*/GIMT_Encode2(AMDGPU::SReg_32_XM0_XEXECRegClassID),
      // MIs[0] sbase
      GIM_CheckPointerToAny, /*MI*/0, /*Op*/1, /*SizeInBits*/64,
      GIM_CheckRegBankForClass, /*MI*/0, /*Op*/1, /*RC*/GIMT_Encode2(AMDGPU::SReg_64RegClassID),
      GIM_CheckCxxInsnPredicate, /*MI*/0, /*FnId*/GIMT_Encode2(GICXXPred_MI_Predicate_smrd_load),
      // (ld:{ *:[i32] } SReg_64:{ *:[i64] }:$sbase)<<P:Predicate_unindexedload>><<P:Predicate_load>><<P:Predicate_smrd_load>>  =>  (S_LOAD_DWORD_IMM:{ *:[i32] } i64:{ *:[i64] }:$sbase, 0:{ *:[i32] }, 0:{ *:[i32] })
      GIR_BuildMI, /*InsnID*/0, /*Opcode*/GIMT_Encode2(AMDGPU::S_LOAD_DWORD_IMM),
      GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/0, // DstI[sdst]
      GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/1, // sbase
      GIR_AddImm8, /*InsnID*/0, /*Imm*/0,
      GIR_AddImm8, /*InsnID*/0, /*Imm*/0,
      GIR_MergeMemOperands, /*InsnID*/0, /*NumInsns*/1, /*MergeInsnID's*/0,
      GIR_ConstrainSelectedInstOperands, /*InsnID*/0,
      GIR_EraseFromParent, /*InsnID*/0,
      // GIR_Coverage, 2499,
      GIR_Done,
    // Label 978: @63500
    GIM_Try, /*On fail goto*//*Label 979*/ GIMT_Encode4(63570), // Rule ID 5420 //
      GIM_CheckFeatures, GIMT_Encode2(GIFBS_DisableFlatScratch_HasUnrestrictedSOffset),
      GIM_CheckMemoryAddressSpace, /*MI*/0, /*MMO*/0, /*NumAddrSpace*/1, /*AddrSpace*/5,
      GIM_CheckAtomicOrdering, /*MI*/0, /*Order*/(uint8_t)AtomicOrdering::NotAtomic,
      GIM_CheckRegBankForClass, /*MI*/0, /*Op*/0, /*RC*/GIMT_Encode2(AMDGPU::AV_32RegClassID),
      GIM_CheckPointerToAny, /*MI*/0, /*Op*/1, /*SizeInBits*/0,
      GIM_CheckComplexPattern, /*MI*/0, /*Op*/1, /*Renderer*/GIMT_Encode2(0), GIMT_Encode2(GICP_gi_mubuf_scratch_offset),
      // (ld:{ *:[i32] } (MUBUFScratchOffset:{ *:[iPTR] } v4i32:{ *:[v4i32] }:$srsrc, i32:{ *:[i32] }:$soffset, i32:{ *:[i32] }:$offset))<<P:Predicate_unindexedload>><<P:Predicate_load_private>>  =>  (BUFFER_LOAD_DWORD_OFFSET:{ *:[i32] } ?:{ *:[v4i32] }:$srsrc, ?:{ *:[i32] }:$soffset, ?:{ *:[i32] }:$offset, 0:{ *:[i32] }, 0:{ *:[i1] })
      GIR_BuildMI, /*InsnID*/0, /*Opcode*/GIMT_Encode2(AMDGPU::BUFFER_LOAD_DWORD_OFFSET),
      GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/0, // DstI[vdata]
      GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/0, // srsrc
      GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/1, // soffset
      GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/2, // offset
      GIR_AddImm8, /*InsnID*/0, /*Imm*/0,
      GIR_AddImm8, /*InsnID*/0, /*Imm*/0,
      GIR_MergeMemOperands, /*InsnID*/0, /*NumInsns*/1, /*MergeInsnID's*/0,
      GIR_ConstrainSelectedInstOperands, /*InsnID*/0,
      GIR_EraseFromParent, /*InsnID*/0,
      // GIR_Coverage, 5420,
      GIR_Done,
    // Label 979: @63570
    GIM_Try, /*On fail goto*//*Label 980*/ GIMT_Encode4(63640), // Rule ID 5422 //
      GIM_CheckFeatures, GIMT_Encode2(GIFBS_DisableFlatScratch),
      GIM_CheckMemoryAddressSpace, /*MI*/0, /*MMO*/0, /*NumAddrSpace*/1, /*AddrSpace*/5,
      GIM_CheckAtomicOrdering, /*MI*/0, /*Order*/(uint8_t)AtomicOrdering::NotAtomic,
      GIM_CheckRegBankForClass, /*MI*/0, /*Op*/0, /*RC*/GIMT_Encode2(AMDGPU::AV_32RegClassID),
      GIM_CheckPointerToAny, /*MI*/0, /*Op*/1, /*SizeInBits*/0,
      GIM_CheckComplexPattern, /*MI*/0, /*Op*/1, /*Renderer*/GIMT_Encode2(0), GIMT_Encode2(GICP_gi_mubuf_scratch_offset),
      // (ld:{ *:[i32] } (MUBUFScratchOffset:{ *:[iPTR] } v4i32:{ *:[v4i32] }:$srsrc, i32:{ *:[i32] }:$soffset, i32:{ *:[i32] }:$offset))<<P:Predicate_unindexedload>><<P:Predicate_load_private>>  =>  (BUFFER_LOAD_DWORD_VBUFFER_OFFSET:{ *:[i32] } ?:{ *:[v4i32] }:$srsrc, ?:{ *:[i32] }:$soffset, ?:{ *:[i32] }:$offset, 0:{ *:[i32] }, 0:{ *:[i1] })
      GIR_BuildMI, /*InsnID*/0, /*Opcode*/GIMT_Encode2(AMDGPU::BUFFER_LOAD_DWORD_VBUFFER_OFFSET),
      GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/0, // DstI[vdata]
      GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/0, // srsrc
      GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/1, // soffset
      GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/2, // offset
      GIR_AddImm8, /*InsnID*/0, /*Imm*/0,
      GIR_AddImm8, /*InsnID*/0, /*Imm*/0,
      GIR_MergeMemOperands, /*InsnID*/0, /*NumInsns*/1, /*MergeInsnID's*/0,
      GIR_ConstrainSelectedInstOperands, /*InsnID*/0,
      GIR_EraseFromParent, /*InsnID*/0,
      // GIR_Coverage, 5422,
      GIR_Done,
    // Label 980: @63640
    GIM_Try, /*On fail goto*//*Label 981*/ GIMT_Encode4(63707), // Rule ID 3478 //
      GIM_CheckFeatures, GIMT_Encode2(GIFBS_EnableFlatScratch_HasFlatScratchInsts_HasFlatScratchSVSMode),
      GIM_CheckMemoryAddressSpace, /*MI*/0, /*MMO*/0, /*NumAddrSpace*/1, /*AddrSpace*/5,
      GIM_CheckAtomicOrdering, /*MI*/0, /*Order*/(uint8_t)AtomicOrdering::NotAtomic,
      GIM_CheckRegBankForClass, /*MI*/0, /*Op*/0, /*RC*/GIMT_Encode2(AMDGPU::AV_32RegClassID),
      GIM_CheckPointerToAny, /*MI*/0, /*Op*/1, /*SizeInBits*/0,
      GIM_CheckComplexPattern, /*MI*/0, /*Op*/1, /*Renderer*/GIMT_Encode2(0), GIMT_Encode2(GICP_gi_flat_scratch_svaddr),
      // (ld:{ *:[i32] } (ScratchSVAddr:{ *:[iPTR] } VGPR_32:{ *:[i32] }:$vaddr, SGPR_32:{ *:[i32] }:$saddr, i32:{ *:[i32] }:$offset))<<P:Predicate_unindexedload>><<P:Predicate_load_private>>  =>  (SCRATCH_LOAD_DWORD_SVS:{ *:[i32] } ?:{ *:[i32] }:$vaddr, ?:{ *:[i32] }:$saddr, ?:{ *:[i32] }:$offset, 0:{ *:[i32] })
      GIR_BuildMI, /*InsnID*/0, /*Opcode*/GIMT_Encode2(AMDGPU::SCRATCH_LOAD_DWORD_SVS),
      GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/0, // DstI[vdst]
      GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/0, // vaddr
      GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/1, // saddr
      GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/2, // offset
      GIR_AddImm8, /*InsnID*/0, /*Imm*/0,
      GIR_MergeMemOperands, /*InsnID*/0, /*NumInsns*/1, /*MergeInsnID's*/0,
      GIR_ConstrainSelectedInstOperands, /*InsnID*/0,
      GIR_EraseFromParent, /*InsnID*/0,
      // GIR_Coverage, 3478,
      GIR_Done,
    // Label 981: @63707
    GIM_Try, /*On fail goto*//*Label 982*/ GIMT_Encode4(63769), // Rule ID 3477 //
      GIM_CheckFeatures, GIMT_Encode2(GIFBS_EnableFlatScratch_HasFlatScratchInsts),
      GIM_CheckMemoryAddressSpace, /*MI*/0, /*MMO*/0, /*NumAddrSpace*/1, /*AddrSpace*/5,
      GIM_CheckAtomicOrdering, /*MI*/0, /*Order*/(uint8_t)AtomicOrdering::NotAtomic,
      GIM_CheckRegBankForClass, /*MI*/0, /*Op*/0, /*RC*/GIMT_Encode2(AMDGPU::AV_32RegClassID),
      GIM_CheckPointerToAny, /*MI*/0, /*Op*/1, /*SizeInBits*/0,
      GIM_CheckComplexPattern, /*MI*/0, /*Op*/1, /*Renderer*/GIMT_Encode2(0), GIMT_Encode2(GICP_gi_flat_scratch_saddr),
      // (ld:{ *:[i32] } (ScratchSAddr:{ *:[iPTR] } SGPR_32:{ *:[i32] }:$saddr, i32:{ *:[i32] }:$offset))<<P:Predicate_unindexedload>><<P:Predicate_load_private>>  =>  (SCRATCH_LOAD_DWORD_SADDR:{ *:[i32] } ?:{ *:[i32] }:$saddr, ?:{ *:[i32] }:$offset)
      GIR_BuildMI, /*InsnID*/0, /*Opcode*/GIMT_Encode2(AMDGPU::SCRATCH_LOAD_DWORD_SADDR),
      GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/0, // DstI[vdst]
      GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/0, // saddr
      GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/1, // offset
      GIR_AddImm8, /*InsnID*/0, /*Imm*/0,
      GIR_MergeMemOperands, /*InsnID*/0, /*NumInsns*/1, /*MergeInsnID's*/0,
      GIR_ConstrainSelectedInstOperands, /*InsnID*/0,
      GIR_EraseFromParent, /*InsnID*/0,
      // GIR_Coverage, 3477,
      GIR_Done,
    // Label 982: @63769
    GIM_Try, /*On fail goto*//*Label 983*/ GIMT_Encode4(63831), // Rule ID 3476 //
      GIM_CheckFeatures, GIMT_Encode2(GIFBS_EnableFlatScratch_HasFlatScratchInsts),
      GIM_CheckMemoryAddressSpace, /*MI*/0, /*MMO*/0, /*NumAddrSpace*/1, /*AddrSpace*/5,
      GIM_CheckAtomicOrdering, /*MI*/0, /*Order*/(uint8_t)AtomicOrdering::NotAtomic,
      GIM_CheckRegBankForClass, /*MI*/0, /*Op*/0, /*RC*/GIMT_Encode2(AMDGPU::AV_32RegClassID),
      GIM_CheckPointerToAny, /*MI*/0, /*Op*/1, /*SizeInBits*/0,
      GIM_CheckComplexPattern, /*MI*/0, /*Op*/1, /*Renderer*/GIMT_Encode2(0), GIMT_Encode2(GICP_gi_flat_scratch_offset),
      // (ld:{ *:[i32] } (ScratchOffset:{ *:[iPTR] } VGPR_32:{ *:[i32] }:$vaddr, i32:{ *:[i32] }:$offset))<<P:Predicate_unindexedload>><<P:Predicate_load_private>>  =>  (SCRATCH_LOAD_DWORD:{ *:[i32] } ?:{ *:[i32] }:$vaddr, ?:{ *:[i32] }:$offset)
      GIR_BuildMI, /*InsnID*/0, /*Opcode*/GIMT_Encode2(AMDGPU::SCRATCH_LOAD_DWORD),
      GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/0, // DstI[vdst]
      GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/0, // vaddr
      GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/1, // offset
      GIR_AddImm8, /*InsnID*/0, /*Imm*/0,
      GIR_MergeMemOperands, /*InsnID*/0, /*NumInsns*/1, /*MergeInsnID's*/0,
      GIR_ConstrainSelectedInstOperands, /*InsnID*/0,
      GIR_EraseFromParent, /*InsnID*/0,
      // GIR_Coverage, 3476,
      GIR_Done,
    // Label 983: @63831
    GIM_Try, /*On fail goto*//*Label 984*/ GIMT_Encode4(63908), // Rule ID 3716 //
      GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasUnrestrictedSOffset),
      GIM_CheckMemoryAddressSpace, /*MI*/0, /*MMO*/0, /*NumAddrSpace*/3, /*AddrSpace*/1, /*AddrSpace*/4, /*AddrSpace*/6,
      GIM_CheckAtomicOrdering, /*MI*/0, /*Order*/(uint8_t)AtomicOrdering::NotAtomic,
      GIM_CheckRegBankForClass, /*MI*/0, /*Op*/0, /*RC*/GIMT_Encode2(AMDGPU::AV_32RegClassID),
      GIM_CheckPointerToAny, /*MI*/0, /*Op*/1, /*SizeInBits*/0,
      GIM_CheckComplexPattern, /*MI*/0, /*Op*/1, /*Renderer*/GIMT_Encode2(0), GIMT_Encode2(GICP_gi_mubuf_addr64),
      // (ld:{ *:[i32] } (MUBUFAddr64:{ *:[iPTR] } v4i32:{ *:[v4i32] }:$srsrc, i64:{ *:[i64] }:$vaddr, i32:{ *:[i32] }:$soffset, i32:{ *:[i32] }:$offset))<<P:Predicate_unindexedload>><<P:Predicate_load_global>>  =>  (BUFFER_LOAD_DWORD_ADDR64:{ *:[i32] } i64:{ *:[i64] }:$vaddr, v4i32:{ *:[v4i32] }:$srsrc, i32:{ *:[i32] }:$soffset, i32:{ *:[i32] }:$offset)
      GIR_BuildMI, /*InsnID*/0, /*Opcode*/GIMT_Encode2(AMDGPU::BUFFER_LOAD_DWORD_ADDR64),
      GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/0, // DstI[vdata]
      GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/1, // vaddr
      GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/0, // srsrc
      GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/2, // soffset
      GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/3, // offset
      GIR_AddImm8, /*InsnID*/0, /*Imm*/0,
      GIR_AddImm8, /*InsnID*/0, /*Imm*/0,
      GIR_MergeMemOperands, /*InsnID*/0, /*NumInsns*/1, /*MergeInsnID's*/0,
      GIR_ConstrainSelectedInstOperands, /*InsnID*/0,
      GIR_EraseFromParent, /*InsnID*/0,
      // GIR_Coverage, 3716,
      GIR_Done,
    // Label 984: @63908
    GIM_Try, /*On fail goto*//*Label 985*/ GIMT_Encode4(63982), // Rule ID 3718 //
      GIM_CheckMemoryAddressSpace, /*MI*/0, /*MMO*/0, /*NumAddrSpace*/3, /*AddrSpace*/1, /*AddrSpace*/4, /*AddrSpace*/6,
      GIM_CheckAtomicOrdering, /*MI*/0, /*Order*/(uint8_t)AtomicOrdering::NotAtomic,
      GIM_CheckRegBankForClass, /*MI*/0, /*Op*/0, /*RC*/GIMT_Encode2(AMDGPU::AV_32RegClassID),
      GIM_CheckPointerToAny, /*MI*/0, /*Op*/1, /*SizeInBits*/0,
      GIM_CheckComplexPattern, /*MI*/0, /*Op*/1, /*Renderer*/GIMT_Encode2(0), GIMT_Encode2(GICP_gi_mubuf_addr64),
      // (ld:{ *:[i32] } (MUBUFAddr64:{ *:[iPTR] } v4i32:{ *:[v4i32] }:$srsrc, i64:{ *:[i64] }:$vaddr, i32:{ *:[i32] }:$soffset, i32:{ *:[i32] }:$offset))<<P:Predicate_unindexedload>><<P:Predicate_load_global>>  =>  (BUFFER_LOAD_DWORD_VBUFFER_ADDR64:{ *:[i32] } i64:{ *:[i64] }:$vaddr, v4i32:{ *:[v4i32] }:$srsrc, i32:{ *:[i32] }:$soffset, i32:{ *:[i32] }:$offset)
      GIR_BuildMI, /*InsnID*/0, /*Opcode*/GIMT_Encode2(AMDGPU::BUFFER_LOAD_DWORD_VBUFFER_ADDR64),
      GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/0, // DstI[vdata]
      GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/1, // vaddr
      GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/0, // srsrc
      GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/2, // soffset
      GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/3, // offset
      GIR_AddImm8, /*InsnID*/0, /*Imm*/0,
      GIR_AddImm8, /*InsnID*/0, /*Imm*/0,
      GIR_MergeMemOperands, /*InsnID*/0, /*NumInsns*/1, /*MergeInsnID's*/0,
      GIR_ConstrainSelectedInstOperands, /*InsnID*/0,
      GIR_EraseFromParent, /*InsnID*/0,
      // GIR_Coverage, 3718,
      GIR_Done,
    // Label 985: @63982
    GIM_Try, /*On fail goto*//*Label 986*/ GIMT_Encode4(64057), // Rule ID 5419 //
      GIM_CheckFeatures, GIMT_Encode2(GIFBS_DisableFlatScratch_HasUnrestrictedSOffset),
      GIM_CheckMemoryAddressSpace, /*MI*/0, /*MMO*/0, /*NumAddrSpace*/1, /*AddrSpace*/5,
      GIM_CheckAtomicOrdering, /*MI*/0, /*Order*/(uint8_t)AtomicOrdering::NotAtomic,
      GIM_CheckRegBankForClass, /*MI*/0, /*Op*/0, /*RC*/GIMT_Encode2(AMDGPU::AV_32RegClassID),
      GIM_CheckPointerToAny, /*MI*/0, /*Op*/1, /*SizeInBits*/0,
      GIM_CheckComplexPattern, /*MI*/0, /*Op*/1, /*Renderer*/GIMT_Encode2(0), GIMT_Encode2(GICP_gi_mubuf_scratch_offen),
      // (ld:{ *:[i32] } (MUBUFScratchOffen:{ *:[iPTR] } v4i32:{ *:[v4i32] }:$srsrc, i32:{ *:[i32] }:$vaddr, i32:{ *:[i32] }:$soffset, i32:{ *:[i32] }:$offset))<<P:Predicate_unindexedload>><<P:Predicate_load_private>>  =>  (BUFFER_LOAD_DWORD_OFFEN:{ *:[i32] } ?:{ *:[i32] }:$vaddr, ?:{ *:[v4i32] }:$srsrc, ?:{ *:[i32] }:$soffset, ?:{ *:[i32] }:$offset, 0:{ *:[i32] }, 0:{ *:[i1] })
      GIR_BuildMI, /*InsnID*/0, /*Opcode*/GIMT_Encode2(AMDGPU::BUFFER_LOAD_DWORD_OFFEN),
      GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/0, // DstI[vdata]
      GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/1, // vaddr
      GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/0, // srsrc
      GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/2, // soffset
      GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/3, // offset
      GIR_AddImm8, /*InsnID*/0, /*Imm*/0,
      GIR_AddImm8, /*InsnID*/0, /*Imm*/0,
      GIR_MergeMemOperands, /*InsnID*/0, /*NumInsns*/1, /*MergeInsnID's*/0,
      GIR_ConstrainSelectedInstOperands, /*InsnID*/0,
      GIR_EraseFromParent, /*InsnID*/0,
      // GIR_Coverage, 5419,
      GIR_Done,
    // Label 986: @64057
    GIM_Try, /*On fail goto*//*Label 987*/ GIMT_Encode4(64132), // Rule ID 5421 //
      GIM_CheckFeatures, GIMT_Encode2(GIFBS_DisableFlatScratch),
      GIM_CheckMemoryAddressSpace, /*MI*/0, /*MMO*/0, /*NumAddrSpace*/1, /*AddrSpace*/5,
      GIM_CheckAtomicOrdering, /*MI*/0, /*Order*/(uint8_t)AtomicOrdering::NotAtomic,
      GIM_CheckRegBankForClass, /*MI*/0, /*Op*/0, /*RC*/GIMT_Encode2(AMDGPU::AV_32RegClassID),
      GIM_CheckPointerToAny, /*MI*/0, /*Op*/1, /*SizeInBits*/0,
      GIM_CheckComplexPattern, /*MI*/0, /*Op*/1, /*Renderer*/GIMT_Encode2(0), GIMT_Encode2(GICP_gi_mubuf_scratch_offen),
      // (ld:{ *:[i32] } (MUBUFScratchOffen:{ *:[iPTR] } v4i32:{ *:[v4i32] }:$srsrc, i32:{ *:[i32] }:$vaddr, i32:{ *:[i32] }:$soffset, i32:{ *:[i32] }:$offset))<<P:Predicate_unindexedload>><<P:Predicate_load_private>>  =>  (BUFFER_LOAD_DWORD_VBUFFER_OFFEN:{ *:[i32] } ?:{ *:[i32] }:$vaddr, ?:{ *:[v4i32] }:$srsrc, ?:{ *:[i32] }:$soffset, ?:{ *:[i32] }:$offset, 0:{ *:[i32] }, 0:{ *:[i1] })
      GIR_BuildMI, /*InsnID*/0, /*Opcode*/GIMT_Encode2(AMDGPU::BUFFER_LOAD_DWORD_VBUFFER_OFFEN),
      GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/0, // DstI[vdata]
      GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/1, // vaddr
      GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/0, // srsrc
      GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/2, // soffset
      GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/3, // offset
      GIR_AddImm8, /*InsnID*/0, /*Imm*/0,
      GIR_AddImm8, /*InsnID*/0, /*Imm*/0,
      GIR_MergeMemOperands, /*InsnID*/0, /*NumInsns*/1, /*MergeInsnID's*/0,
      GIR_ConstrainSelectedInstOperands, /*InsnID*/0,
      GIR_EraseFromParent, /*InsnID*/0,
      // GIR_Coverage, 5421,
      GIR_Done,
    // Label 987: @64132
    GIM_Try, /*On fail goto*//*Label 988*/ GIMT_Encode4(64204), // Rule ID 3715 //
      GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasUnrestrictedSOffset),
      GIM_CheckMemoryAddressSpace, /*MI*/0, /*MMO*/0, /*NumAddrSpace*/3, /*AddrSpace*/1, /*AddrSpace*/4, /*AddrSpace*/6,
      GIM_CheckAtomicOrdering, /*MI*/0, /*Order*/(uint8_t)AtomicOrdering::NotAtomic,
      GIM_CheckRegBankForClass, /*MI*/0, /*Op*/0, /*RC*/GIMT_Encode2(AMDGPU::AV_32RegClassID),
      GIM_CheckPointerToAny, /*MI*/0, /*Op*/1, /*SizeInBits*/0,
      GIM_CheckComplexPattern, /*MI*/0, /*Op*/1, /*Renderer*/GIMT_Encode2(0), GIMT_Encode2(GICP_gi_mubuf_offset),
      // (ld:{ *:[i32] } (MUBUFOffset:{ *:[iPTR] } v4i32:{ *:[v4i32] }:$srsrc, i32:{ *:[i32] }:$soffset, i32:{ *:[i32] }:$offset))<<P:Predicate_unindexedload>><<P:Predicate_load_global>>  =>  (BUFFER_LOAD_DWORD_OFFSET:{ *:[i32] } v4i32:{ *:[v4i32] }:$srsrc, i32:{ *:[i32] }:$soffset, i32:{ *:[i32] }:$offset)
      GIR_BuildMI, /*InsnID*/0, /*Opcode*/GIMT_Encode2(AMDGPU::BUFFER_LOAD_DWORD_OFFSET),
      GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/0, // DstI[vdata]
      GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/0, // srsrc
      GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/1, // soffset
      GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/2, // offset
      GIR_AddImm8, /*InsnID*/0, /*Imm*/0,
      GIR_AddImm8, /*InsnID*/0, /*Imm*/0,
      GIR_MergeMemOperands, /*InsnID*/0, /*NumInsns*/1, /*MergeInsnID's*/0,
      GIR_ConstrainSelectedInstOperands, /*InsnID*/0,
      GIR_EraseFromParent, /*InsnID*/0,
      // GIR_Coverage, 3715,
      GIR_Done,
    // Label 988: @64204
    GIM_Try, /*On fail goto*//*Label 989*/ GIMT_Encode4(64273), // Rule ID 3717 //
      GIM_CheckMemoryAddressSpace, /*MI*/0, /*MMO*/0, /*NumAddrSpace*/3, /*AddrSpace*/1, /*AddrSpace*/4, /*AddrSpace*/6,
      GIM_CheckAtomicOrdering, /*MI*/0, /*Order*/(uint8_t)AtomicOrdering::NotAtomic,
      GIM_CheckRegBankForClass, /*MI*/0, /*Op*/0, /*RC*/GIMT_Encode2(AMDGPU::AV_32RegClassID),
      GIM_CheckPointerToAny, /*MI*/0, /*Op*/1, /*SizeInBits*/0,
      GIM_CheckComplexPattern, /*MI*/0, /*Op*/1, /*Renderer*/GIMT_Encode2(0), GIMT_Encode2(GICP_gi_mubuf_offset),
      // (ld:{ *:[i32] } (MUBUFOffset:{ *:[iPTR] } v4i32:{ *:[v4i32] }:$srsrc, i32:{ *:[i32] }:$soffset, i32:{ *:[i32] }:$offset))<<P:Predicate_unindexedload>><<P:Predicate_load_global>>  =>  (BUFFER_LOAD_DWORD_VBUFFER_OFFSET:{ *:[i32] } v4i32:{ *:[v4i32] }:$srsrc, i32:{ *:[i32] }:$soffset, i32:{ *:[i32] }:$offset)
      GIR_BuildMI, /*InsnID*/0, /*Opcode*/GIMT_Encode2(AMDGPU::BUFFER_LOAD_DWORD_VBUFFER_OFFSET),
      GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/0, // DstI[vdata]
      GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/0, // srsrc
      GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/1, // soffset
      GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/2, // offset
      GIR_AddImm8, /*InsnID*/0, /*Imm*/0,
      GIR_AddImm8, /*InsnID*/0, /*Imm*/0,
      GIR_MergeMemOperands, /*InsnID*/0, /*NumInsns*/1, /*MergeInsnID's*/0,
      GIR_ConstrainSelectedInstOperands, /*InsnID*/0,
      GIR_EraseFromParent, /*InsnID*/0,
      // GIR_Coverage, 3717,
      GIR_Done,
    // Label 989: @64273
    GIM_Try, /*On fail goto*//*Label 990*/ GIMT_Encode4(64339), // Rule ID 6605 //
      GIM_CheckFeatures, GIMT_Encode2(GIFBS_LDSRequiresM0Init),
      GIM_CheckMemorySizeEqualToLLT, /*MI*/0, /*MMO*/0, /*OpIdx*/0,
      GIM_CheckMemoryAddressSpace, /*MI*/0, /*MMO*/0, /*NumAddrSpace*/1, /*AddrSpace*/3,
      GIM_CheckAtomicOrdering, /*MI*/0, /*Order*/(uint8_t)AtomicOrdering::NotAtomic,
      GIM_CheckRegBankForClass, /*MI*/0, /*Op*/0, /*RC*/GIMT_Encode2(AMDGPU::AV_32RegClassID),
      GIM_CheckPointerToAny, /*MI*/0, /*Op*/1, /*SizeInBits*/0,
      GIM_CheckComplexPattern, /*MI*/0, /*Op*/1, /*Renderer*/GIMT_Encode2(0), GIMT_Encode2(GICP_gi_ds_1addr_1offset),
      // (AMDGPUld_glue:{ *:[i32] } (DS1Addr1Offset:{ *:[iPTR] } i32:{ *:[i32] }:$ptr, i32:{ *:[i32] }:$offset))<<P:Predicate_unindexedload_glue>><<P:Predicate_load_glue>><<P:Predicate_load_local_m0>>  =>  (DS_READ_B32:{ *:[i32] } ?:{ *:[i32] }:$ptr, offset:{ *:[i32] }:$offset, 0:{ *:[i1] })
      GIR_BuildMI, /*InsnID*/0, /*Opcode*/GIMT_Encode2(AMDGPU::DS_READ_B32),
      GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/0, // DstI[vdst]
      GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/0, // ptr
      GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/1, // offset
      GIR_AddImm8, /*InsnID*/0, /*Imm*/0,
      GIR_MergeMemOperands, /*InsnID*/0, /*NumInsns*/1, /*MergeInsnID's*/0,
      GIR_ConstrainSelectedInstOperands, /*InsnID*/0,
      GIR_EraseFromParent, /*InsnID*/0,
      // GIR_Coverage, 6605,
      GIR_Done,
    // Label 990: @64339
    GIM_Try, /*On fail goto*//*Label 991*/ GIMT_Encode4(64401), // Rule ID 6606 //
      GIM_CheckFeatures, GIMT_Encode2(GIFBS_NotLDSRequiresM0Init),
      GIM_CheckMemoryAddressSpace, /*MI*/0, /*MMO*/0, /*NumAddrSpace*/1, /*AddrSpace*/3,
      GIM_CheckAtomicOrdering, /*MI*/0, /*Order*/(uint8_t)AtomicOrdering::NotAtomic,
      GIM_CheckRegBankForClass, /*MI*/0, /*Op*/0, /*RC*/GIMT_Encode2(AMDGPU::AV_32RegClassID),
      GIM_CheckPointerToAny, /*MI*/0, /*Op*/1, /*SizeInBits*/0,
      GIM_CheckComplexPattern, /*MI*/0, /*Op*/1, /*Renderer*/GIMT_Encode2(0), GIMT_Encode2(GICP_gi_ds_1addr_1offset),
      // (ld:{ *:[i32] } (DS1Addr1Offset:{ *:[iPTR] } i32:{ *:[i32] }:$ptr, i32:{ *:[i32] }:$offset))<<P:Predicate_unindexedload>><<P:Predicate_load_local>>  =>  (DS_READ_B32_gfx9:{ *:[i32] } ?:{ *:[i32] }:$ptr, offset:{ *:[i32] }:$offset, 0:{ *:[i1] })
      GIR_BuildMI, /*InsnID*/0, /*Opcode*/GIMT_Encode2(AMDGPU::DS_READ_B32_gfx9),
      GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/0, // DstI[vdst]
      GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/0, // ptr
      GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/1, // offset
      GIR_AddImm8, /*InsnID*/0, /*Imm*/0,
      GIR_MergeMemOperands, /*InsnID*/0, /*NumInsns*/1, /*MergeInsnID's*/0,
      GIR_ConstrainSelectedInstOperands, /*InsnID*/0,
      GIR_EraseFromParent, /*InsnID*/0,
      // GIR_Coverage, 6606,
      GIR_Done,
    // Label 991: @64401
    GIM_Try, /*On fail goto*//*Label 992*/ GIMT_Encode4(64470), // Rule ID 3025 //
      GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasFlatGlobalInsts),
      GIM_CheckMemoryAddressSpace, /*MI*/0, /*MMO*/0, /*NumAddrSpace*/3, /*AddrSpace*/1, /*AddrSpace*/4, /*AddrSpace*/6,
      GIM_CheckAtomicOrdering, /*MI*/0, /*Order*/(uint8_t)AtomicOrdering::NotAtomic,
      GIM_CheckRegBankForClass, /*MI*/0, /*Op*/0, /*RC*/GIMT_Encode2(AMDGPU::AV_32RegClassID),
      GIM_CheckPointerToAny, /*MI*/0, /*Op*/1, /*SizeInBits*/0,
      GIM_CheckComplexPattern, /*MI*/0, /*Op*/1, /*Renderer*/GIMT_Encode2(0), GIMT_Encode2(GICP_gi_global_saddr),
      // (ld:{ *:[i32] } (GlobalSAddr:{ *:[iPTR] } SReg_64:{ *:[i64] }:$saddr, VGPR_32:{ *:[i32] }:$voffset, i32:{ *:[i32] }:$offset))<<P:Predicate_unindexedload>><<P:Predicate_load_global>>  =>  (GLOBAL_LOAD_DWORD_SADDR:{ *:[i32] } ?:{ *:[i64] }:$saddr, ?:{ *:[i32] }:$voffset, ?:{ *:[i32] }:$offset, 0:{ *:[i32] })
      GIR_BuildMI, /*InsnID*/0, /*Opcode*/GIMT_Encode2(AMDGPU::GLOBAL_LOAD_DWORD_SADDR),
      GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/0, // DstI[vdst]
      GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/0, // saddr
      GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/1, // voffset
      GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/2, // offset
      GIR_AddImm8, /*InsnID*/0, /*Imm*/0,
      GIR_MergeMemOperands, /*InsnID*/0, /*NumInsns*/1, /*MergeInsnID's*/0,
      GIR_ConstrainSelectedInstOperands, /*InsnID*/0,
      GIR_EraseFromParent, /*InsnID*/0,
      // GIR_Coverage, 3025,
      GIR_Done,
    // Label 992: @64470
    GIM_Try, /*On fail goto*//*Label 993*/ GIMT_Encode4(64534), // Rule ID 3024 //
      GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasFlatGlobalInsts),
      GIM_CheckMemoryAddressSpace, /*MI*/0, /*MMO*/0, /*NumAddrSpace*/3, /*AddrSpace*/1, /*AddrSpace*/4, /*AddrSpace*/6,
      GIM_CheckAtomicOrdering, /*MI*/0, /*Order*/(uint8_t)AtomicOrdering::NotAtomic,
      GIM_CheckRegBankForClass, /*MI*/0, /*Op*/0, /*RC*/GIMT_Encode2(AMDGPU::AV_32RegClassID),
      GIM_CheckPointerToAny, /*MI*/0, /*Op*/1, /*SizeInBits*/0,
      GIM_CheckComplexPattern, /*MI*/0, /*Op*/1, /*Renderer*/GIMT_Encode2(0), GIMT_Encode2(GICP_gi_global_offset),
      // (ld:{ *:[i32] } (GlobalOffset:{ *:[iPTR] } VReg_64:{ *:[i64] }:$vaddr, i32:{ *:[i32] }:$offset))<<P:Predicate_unindexedload>><<P:Predicate_load_global>>  =>  (GLOBAL_LOAD_DWORD:{ *:[i32] } ?:{ *:[i64] }:$vaddr, ?:{ *:[i32] }:$offset)
      GIR_BuildMI, /*InsnID*/0, /*Opcode*/GIMT_Encode2(AMDGPU::GLOBAL_LOAD_DWORD),
      GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/0, // DstI[vdst]
      GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/0, // vaddr
      GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/1, // offset
      GIR_AddImm8, /*InsnID*/0, /*Imm*/0,
      GIR_MergeMemOperands, /*InsnID*/0, /*NumInsns*/1, /*MergeInsnID's*/0,
      GIR_ConstrainSelectedInstOperands, /*InsnID*/0,
      GIR_EraseFromParent, /*InsnID*/0,
      // GIR_Coverage, 3024,
      GIR_Done,
    // Label 993: @64534
    GIM_Try, /*On fail goto*//*Label 994*/ GIMT_Encode4(64599), // Rule ID 2786 //
      GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasFlatAddressSpace),
      GIM_CheckMemoryAddressSpace, /*MI*/0, /*MMO*/0, /*NumAddrSpace*/4, /*AddrSpace*/0, /*AddrSpace*/1, /*AddrSpace*/4, /*AddrSpace*/6,
      GIM_CheckAtomicOrdering, /*MI*/0, /*Order*/(uint8_t)AtomicOrdering::NotAtomic,
      GIM_CheckRegBankForClass, /*MI*/0, /*Op*/0, /*RC*/GIMT_Encode2(AMDGPU::AV_32RegClassID),
      GIM_CheckPointerToAny, /*MI*/0, /*Op*/1, /*SizeInBits*/0,
      GIM_CheckComplexPattern, /*MI*/0, /*Op*/1, /*Renderer*/GIMT_Encode2(0), GIMT_Encode2(GICP_gi_flat_offset),
      // (ld:{ *:[i32] } (FlatOffset:{ *:[iPTR] } i64:{ *:[i64] }:$vaddr, i32:{ *:[i32] }:$offset))<<P:Predicate_unindexedload>><<P:Predicate_load_flat>>  =>  (FLAT_LOAD_DWORD:{ *:[i32] } ?:{ *:[i64] }:$vaddr, ?:{ *:[i32] }:$offset)
      GIR_BuildMI, /*InsnID*/0, /*Opcode*/GIMT_Encode2(AMDGPU::FLAT_LOAD_DWORD),
      GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/0, // DstI[vdst]
      GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/0, // vaddr
      GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/1, // offset
      GIR_AddImm8, /*InsnID*/0, /*Imm*/0,
      GIR_MergeMemOperands, /*InsnID*/0, /*NumInsns*/1, /*MergeInsnID's*/0,
      GIR_ConstrainSelectedInstOperands, /*InsnID*/0,
      GIR_EraseFromParent, /*InsnID*/0,
      // GIR_Coverage, 2786,
      GIR_Done,
    // Label 994: @64599
    GIM_Reject,
    // Label 823: @64600
    GIM_Try, /*On fail goto*//*Label 995*/ GIMT_Encode4(64913),
      GIM_CheckMemorySizeEqualToLLT, /*MI*/0, /*MMO*/0, /*OpIdx*/0,
      GIM_CheckCxxInsnPredicate, /*MI*/0, /*FnId*/GIMT_Encode2(GICXXPred_MI_Predicate_smrd_load),
      GIM_CheckAtomicOrdering, /*MI*/0, /*Order*/(uint8_t)AtomicOrdering::NotAtomic,
      GIM_CheckRegBankForClass, /*MI*/0, /*Op*/0, /*RC*/GIMT_Encode2(AMDGPU::SReg_64_XEXECRegClassID),
      GIM_Try, /*On fail goto*//*Label 996*/ GIMT_Encode4(64675), // Rule ID 2528 //
        GIM_CheckFeatures, GIMT_Encode2(GIFBS_isGFX9Plus),
        GIM_CheckPointerToAny, /*MI*/0, /*Op*/1, /*SizeInBits*/0,
        GIM_CheckComplexPattern, /*MI*/0, /*Op*/1, /*Renderer*/GIMT_Encode2(0), GIMT_Encode2(GICP_gi_smrd_sgpr_imm),
        // (ld:{ *:[i1] } (SMRDSgprImm:{ *:[iPTR] } i64:{ *:[i64] }:$sbase, i32:{ *:[i32] }:$soffset, i32:{ *:[i32] }:$offset))<<P:Predicate_unindexedload>><<P:Predicate_load>><<P:Predicate_smrd_load>>  =>  (S_LOAD_DWORDX2_SGPR_IMM:{ *:[i1] } ?:{ *:[i64] }:$sbase, ?:{ *:[i32] }:$soffset, ?:{ *:[i32] }:$offset, 0:{ *:[i32] })
        GIR_BuildMI, /*InsnID*/0, /*Opcode*/GIMT_Encode2(AMDGPU::S_LOAD_DWORDX2_SGPR_IMM),
        GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/0, // DstI[sdst]
        GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/0, // sbase
        GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/1, // soffset
        GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/2, // offset
        GIR_AddImm8, /*InsnID*/0, /*Imm*/0,
        GIR_MergeMemOperands, /*InsnID*/0, /*NumInsns*/1, /*MergeInsnID's*/0,
        GIR_ConstrainSelectedInstOperands, /*InsnID*/0,
        GIR_EraseFromParent, /*InsnID*/0,
        // GIR_Coverage, 2528,
        GIR_Done,
      // Label 996: @64675
      GIM_Try, /*On fail goto*//*Label 997*/ GIMT_Encode4(64721), // Rule ID 2524 //
        GIM_CheckPointerToAny, /*MI*/0, /*Op*/1, /*SizeInBits*/0,
        GIM_CheckComplexPattern, /*MI*/0, /*Op*/1, /*Renderer*/GIMT_Encode2(0), GIMT_Encode2(GICP_gi_smrd_imm),
        // (ld:{ *:[i1] } (SMRDImm:{ *:[iPTR] } i64:{ *:[i64] }:$sbase, i32:{ *:[i32] }:$offset))<<P:Predicate_unindexedload>><<P:Predicate_load>><<P:Predicate_smrd_load>>  =>  (S_LOAD_DWORDX2_IMM:{ *:[i1] } ?:{ *:[i64] }:$sbase, ?:{ *:[i32] }:$offset, 0:{ *:[i32] })
        GIR_BuildMI, /*InsnID*/0, /*Opcode*/GIMT_Encode2(AMDGPU::S_LOAD_DWORDX2_IMM),
        GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/0, // DstI[sdst]
        GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/0, // sbase
        GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/1, // offset
        GIR_AddImm8, /*InsnID*/0, /*Imm*/0,
        GIR_MergeMemOperands, /*InsnID*/0, /*NumInsns*/1, /*MergeInsnID's*/0,
        GIR_ConstrainSelectedInstOperands, /*InsnID*/0,
        GIR_EraseFromParent, /*InsnID*/0,
        // GIR_Coverage, 2524,
        GIR_Done,
      // Label 997: @64721
      GIM_Try, /*On fail goto*//*Label 998*/ GIMT_Encode4(64770), // Rule ID 2525 //
        GIM_CheckFeatures, GIMT_Encode2(GIFBS_isGFX7Only),
        GIM_CheckPointerToAny, /*MI*/0, /*Op*/1, /*SizeInBits*/0,
        GIM_CheckComplexPattern, /*MI*/0, /*Op*/1, /*Renderer*/GIMT_Encode2(0), GIMT_Encode2(GICP_gi_smrd_imm32),
        // (ld:{ *:[i1] } (SMRDImm32:{ *:[iPTR] } i64:{ *:[i64] }:$sbase, i32:{ *:[i32] }:$offset))<<P:Predicate_unindexedload>><<P:Predicate_load>><<P:Predicate_smrd_load>>  =>  (S_LOAD_DWORDX2_IMM_ci:{ *:[i1] } ?:{ *:[i64] }:$sbase, ?:{ *:[i32] }:$offset, 0:{ *:[i32] })
        GIR_BuildMI, /*InsnID*/0, /*Opcode*/GIMT_Encode2(AMDGPU::S_LOAD_DWORDX2_IMM_ci),
        GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/0, // DstI[sdst]
        GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/0, // sbase
        GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/1, // offset
        GIR_AddImm8, /*InsnID*/0, /*Imm*/0,
        GIR_MergeMemOperands, /*InsnID*/0, /*NumInsns*/1, /*MergeInsnID's*/0,
        GIR_ConstrainSelectedInstOperands, /*InsnID*/0,
        GIR_EraseFromParent, /*InsnID*/0,
        // GIR_Coverage, 2525,
        GIR_Done,
      // Label 998: @64770
      GIM_Try, /*On fail goto*//*Label 999*/ GIMT_Encode4(64819), // Rule ID 2526 //
        GIM_CheckFeatures, GIMT_Encode2(GIFBS_isNotGFX9Plus),
        GIM_CheckPointerToAny, /*MI*/0, /*Op*/1, /*SizeInBits*/0,
        GIM_CheckComplexPattern, /*MI*/0, /*Op*/1, /*Renderer*/GIMT_Encode2(0), GIMT_Encode2(GICP_gi_smrd_sgpr),
        // (ld:{ *:[i1] } (SMRDSgpr:{ *:[iPTR] } i64:{ *:[i64] }:$sbase, i32:{ *:[i32] }:$soffset))<<P:Predicate_unindexedload>><<P:Predicate_load>><<P:Predicate_smrd_load>>  =>  (S_LOAD_DWORDX2_SGPR:{ *:[i1] } ?:{ *:[i64] }:$sbase, ?:{ *:[i32] }:$soffset, 0:{ *:[i32] })
        GIR_BuildMI, /*InsnID*/0, /*Opcode*/GIMT_Encode2(AMDGPU::S_LOAD_DWORDX2_SGPR),
        GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/0, // DstI[sdst]
        GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/0, // sbase
        GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/1, // soffset
        GIR_AddImm8, /*InsnID*/0, /*Imm*/0,
        GIR_MergeMemOperands, /*InsnID*/0, /*NumInsns*/1, /*MergeInsnID's*/0,
        GIR_ConstrainSelectedInstOperands, /*InsnID*/0,
        GIR_EraseFromParent, /*InsnID*/0,
        // GIR_Coverage, 2526,
        GIR_Done,
      // Label 999: @64819
      GIM_Try, /*On fail goto*//*Label 1000*/ GIMT_Encode4(64871), // Rule ID 2527 //
        GIM_CheckFeatures, GIMT_Encode2(GIFBS_isGFX9Plus),
        GIM_CheckPointerToAny, /*MI*/0, /*Op*/1, /*SizeInBits*/0,
        GIM_CheckComplexPattern, /*MI*/0, /*Op*/1, /*Renderer*/GIMT_Encode2(0), GIMT_Encode2(GICP_gi_smrd_sgpr),
        // (ld:{ *:[i1] } (SMRDSgpr:{ *:[iPTR] } i64:{ *:[i64] }:$sbase, i32:{ *:[i32] }:$soffset))<<P:Predicate_unindexedload>><<P:Predicate_load>><<P:Predicate_smrd_load>>  =>  (S_LOAD_DWORDX2_SGPR_IMM:{ *:[i1] } ?:{ *:[i64] }:$sbase, ?:{ *:[i32] }:$soffset, 0:{ *:[i32] }, 0:{ *:[i32] })
        GIR_BuildMI, /*InsnID*/0, /*Opcode*/GIMT_Encode2(AMDGPU::S_LOAD_DWORDX2_SGPR_IMM),
        GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/0, // DstI[sdst]
        GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/0, // sbase
        GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/1, // soffset
        GIR_AddImm8, /*InsnID*/0, /*Imm*/0,
        GIR_AddImm8, /*InsnID*/0, /*Imm*/0,
        GIR_MergeMemOperands, /*InsnID*/0, /*NumInsns*/1, /*MergeInsnID's*/0,
        GIR_ConstrainSelectedInstOperands, /*InsnID*/0,
        GIR_EraseFromParent, /*InsnID*/0,
        // GIR_Coverage, 2527,
        GIR_Done,
      // Label 1000: @64871
      GIM_Try, /*On fail goto*//*Label 1001*/ GIMT_Encode4(64912), // Rule ID 2529 //
        // MIs[0] sbase
        GIM_CheckPointerToAny, /*MI*/0, /*Op*/1, /*SizeInBits*/64,
        GIM_CheckRegBankForClass, /*MI*/0, /*Op*/1, /*RC*/GIMT_Encode2(AMDGPU::SReg_64RegClassID),
        // (ld:{ *:[i1] } SReg_64:{ *:[i64] }:$sbase)<<P:Predicate_unindexedload>><<P:Predicate_load>><<P:Predicate_smrd_load>>  =>  (S_LOAD_DWORDX2_IMM:{ *:[i1] } i64:{ *:[i64] }:$sbase, 0:{ *:[i32] }, 0:{ *:[i32] })
        GIR_BuildMI, /*InsnID*/0, /*Opcode*/GIMT_Encode2(AMDGPU::S_LOAD_DWORDX2_IMM),
        GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/0, // DstI[sdst]
        GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/1, // sbase
        GIR_AddImm8, /*InsnID*/0, /*Imm*/0,
        GIR_AddImm8, /*InsnID*/0, /*Imm*/0,
        GIR_MergeMemOperands, /*InsnID*/0, /*NumInsns*/1, /*MergeInsnID's*/0,
        GIR_ConstrainSelectedInstOperands, /*InsnID*/0,
        GIR_EraseFromParent, /*InsnID*/0,
        // GIR_Coverage, 2529,
        GIR_Done,
      // Label 1001: @64912
      GIM_Reject,
    // Label 995: @64913
    GIM_Reject,
    // Label 824: @64914
    GIM_Try, /*On fail goto*//*Label 1002*/ GIMT_Encode4(64995), // Rule ID 5364 //
      GIM_CheckFeatures, GIMT_Encode2(GIFBS_DisableFlatScratch_HasUnrestrictedSOffset),
      GIM_CheckMemorySizeLessThanLLT, /*MI*/0, /*MMO*/0, /*OpIdx*/0,
      GIM_CheckMemorySizeEqualTo, /*MI*/0, /*MMO*/0, /*Size*/GIMT_Encode4(1),
      GIM_CheckMemoryAddressSpace, /*MI*/0, /*MMO*/0, /*NumAddrSpace*/1, /*AddrSpace*/5,
      GIM_CheckAtomicOrdering, /*MI*/0, /*Order*/(uint8_t)AtomicOrdering::NotAtomic,
      GIM_CheckRegBankForClass, /*MI*/0, /*Op*/0, /*RC*/GIMT_Encode2(AMDGPU::AV_32RegClassID),
      GIM_CheckPointerToAny, /*MI*/0, /*Op*/1, /*SizeInBits*/0,
      GIM_CheckComplexPattern, /*MI*/0, /*Op*/1, /*Renderer*/GIMT_Encode2(0), GIMT_Encode2(GICP_gi_mubuf_scratch_offset),
      // (ld:{ *:[i16] } (MUBUFScratchOffset:{ *:[iPTR] } v4i32:{ *:[v4i32] }:$srsrc, i32:{ *:[i32] }:$soffset, i32:{ *:[i32] }:$offset))<<P:Predicate_unindexedload>><<P:Predicate_extload>><<P:Predicate_extloadi8>><<P:Predicate_extloadi8_private>>  =>  (BUFFER_LOAD_UBYTE_OFFSET:{ *:[i16] } ?:{ *:[v4i32] }:$srsrc, ?:{ *:[i32] }:$soffset, ?:{ *:[i32] }:$offset, 0:{ *:[i32] }, 0:{ *:[i1] })
      GIR_BuildMI, /*InsnID*/0, /*Opcode*/GIMT_Encode2(AMDGPU::BUFFER_LOAD_UBYTE_OFFSET),
      GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/0, // DstI[vdata]
      GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/0, // srsrc
      GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/1, // soffset
      GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/2, // offset
      GIR_AddImm8, /*InsnID*/0, /*Imm*/0,
      GIR_AddImm8, /*InsnID*/0, /*Imm*/0,
      GIR_MergeMemOperands, /*InsnID*/0, /*NumInsns*/1, /*MergeInsnID's*/0,
      GIR_ConstrainSelectedInstOperands, /*InsnID*/0,
      GIR_EraseFromParent, /*InsnID*/0,
      // GIR_Coverage, 5364,
      GIR_Done,
    // Label 1002: @64995
    GIM_Try, /*On fail goto*//*Label 1003*/ GIMT_Encode4(65076), // Rule ID 5366 //
      GIM_CheckFeatures, GIMT_Encode2(GIFBS_DisableFlatScratch),
      GIM_CheckMemorySizeLessThanLLT, /*MI*/0, /*MMO*/0, /*OpIdx*/0,
      GIM_CheckMemorySizeEqualTo, /*MI*/0, /*MMO*/0, /*Size*/GIMT_Encode4(1),
      GIM_CheckMemoryAddressSpace, /*MI*/0, /*MMO*/0, /*NumAddrSpace*/1, /*AddrSpace*/5,
      GIM_CheckAtomicOrdering, /*MI*/0, /*Order*/(uint8_t)AtomicOrdering::NotAtomic,
      GIM_CheckRegBankForClass, /*MI*/0, /*Op*/0, /*RC*/GIMT_Encode2(AMDGPU::AV_32RegClassID),
      GIM_CheckPointerToAny, /*MI*/0, /*Op*/1, /*SizeInBits*/0,
      GIM_CheckComplexPattern, /*MI*/0, /*Op*/1, /*Renderer*/GIMT_Encode2(0), GIMT_Encode2(GICP_gi_mubuf_scratch_offset),
      // (ld:{ *:[i16] } (MUBUFScratchOffset:{ *:[iPTR] } v4i32:{ *:[v4i32] }:$srsrc, i32:{ *:[i32] }:$soffset, i32:{ *:[i32] }:$offset))<<P:Predicate_unindexedload>><<P:Predicate_extload>><<P:Predicate_extloadi8>><<P:Predicate_extloadi8_private>>  =>  (BUFFER_LOAD_UBYTE_VBUFFER_OFFSET:{ *:[i16] } ?:{ *:[v4i32] }:$srsrc, ?:{ *:[i32] }:$soffset, ?:{ *:[i32] }:$offset, 0:{ *:[i32] }, 0:{ *:[i1] })
      GIR_BuildMI, /*InsnID*/0, /*Opcode*/GIMT_Encode2(AMDGPU::BUFFER_LOAD_UBYTE_VBUFFER_OFFSET),
      GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/0, // DstI[vdata]
      GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/0, // srsrc
      GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/1, // soffset
      GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/2, // offset
      GIR_AddImm8, /*InsnID*/0, /*Imm*/0,
      GIR_AddImm8, /*InsnID*/0, /*Imm*/0,
      GIR_MergeMemOperands, /*InsnID*/0, /*NumInsns*/1, /*MergeInsnID's*/0,
      GIR_ConstrainSelectedInstOperands, /*InsnID*/0,
      GIR_EraseFromParent, /*InsnID*/0,
      // GIR_Coverage, 5366,
      GIR_Done,
    // Label 1003: @65076
    GIM_Try, /*On fail goto*//*Label 1004*/ GIMT_Encode4(65146), // Rule ID 5384 //
      GIM_CheckFeatures, GIMT_Encode2(GIFBS_DisableFlatScratch_HasUnrestrictedSOffset),
      GIM_CheckMemoryAddressSpace, /*MI*/0, /*MMO*/0, /*NumAddrSpace*/1, /*AddrSpace*/5,
      GIM_CheckAtomicOrdering, /*MI*/0, /*Order*/(uint8_t)AtomicOrdering::NotAtomic,
      GIM_CheckRegBankForClass, /*MI*/0, /*Op*/0, /*RC*/GIMT_Encode2(AMDGPU::AV_32RegClassID),
      GIM_CheckPointerToAny, /*MI*/0, /*Op*/1, /*SizeInBits*/0,
      GIM_CheckComplexPattern, /*MI*/0, /*Op*/1, /*Renderer*/GIMT_Encode2(0), GIMT_Encode2(GICP_gi_mubuf_scratch_offset),
      // (ld:{ *:[i16] } (MUBUFScratchOffset:{ *:[iPTR] } v4i32:{ *:[v4i32] }:$srsrc, i32:{ *:[i32] }:$soffset, i32:{ *:[i32] }:$offset))<<P:Predicate_unindexedload>><<P:Predicate_load_private>>  =>  (BUFFER_LOAD_USHORT_OFFSET:{ *:[i16] } ?:{ *:[v4i32] }:$srsrc, ?:{ *:[i32] }:$soffset, ?:{ *:[i32] }:$offset, 0:{ *:[i32] }, 0:{ *:[i1] })
      GIR_BuildMI, /*InsnID*/0, /*Opcode*/GIMT_Encode2(AMDGPU::BUFFER_LOAD_USHORT_OFFSET),
      GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/0, // DstI[vdata]
      GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/0, // srsrc
      GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/1, // soffset
      GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/2, // offset
      GIR_AddImm8, /*InsnID*/0, /*Imm*/0,
      GIR_AddImm8, /*InsnID*/0, /*Imm*/0,
      GIR_MergeMemOperands, /*InsnID*/0, /*NumInsns*/1, /*MergeInsnID's*/0,
      GIR_ConstrainSelectedInstOperands, /*InsnID*/0,
      GIR_EraseFromParent, /*InsnID*/0,
      // GIR_Coverage, 5384,
      GIR_Done,
    // Label 1004: @65146
    GIM_Try, /*On fail goto*//*Label 1005*/ GIMT_Encode4(65216), // Rule ID 5386 //
      GIM_CheckFeatures, GIMT_Encode2(GIFBS_DisableFlatScratch),
      GIM_CheckMemoryAddressSpace, /*MI*/0, /*MMO*/0, /*NumAddrSpace*/1, /*AddrSpace*/5,
      GIM_CheckAtomicOrdering, /*MI*/0, /*Order*/(uint8_t)AtomicOrdering::NotAtomic,
      GIM_CheckRegBankForClass, /*MI*/0, /*Op*/0, /*RC*/GIMT_Encode2(AMDGPU::AV_32RegClassID),
      GIM_CheckPointerToAny, /*MI*/0, /*Op*/1, /*SizeInBits*/0,
      GIM_CheckComplexPattern, /*MI*/0, /*Op*/1, /*Renderer*/GIMT_Encode2(0), GIMT_Encode2(GICP_gi_mubuf_scratch_offset),
      // (ld:{ *:[i16] } (MUBUFScratchOffset:{ *:[iPTR] } v4i32:{ *:[v4i32] }:$srsrc, i32:{ *:[i32] }:$soffset, i32:{ *:[i32] }:$offset))<<P:Predicate_unindexedload>><<P:Predicate_load_private>>  =>  (BUFFER_LOAD_USHORT_VBUFFER_OFFSET:{ *:[i16] } ?:{ *:[v4i32] }:$srsrc, ?:{ *:[i32] }:$soffset, ?:{ *:[i32] }:$offset, 0:{ *:[i32] }, 0:{ *:[i1] })
      GIR_BuildMI, /*InsnID*/0, /*Opcode*/GIMT_Encode2(AMDGPU::BUFFER_LOAD_USHORT_VBUFFER_OFFSET),
      GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/0, // DstI[vdata]
      GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/0, // srsrc
      GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/1, // soffset
      GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/2, // offset
      GIR_AddImm8, /*InsnID*/0, /*Imm*/0,
      GIR_AddImm8, /*InsnID*/0, /*Imm*/0,
      GIR_MergeMemOperands, /*InsnID*/0, /*NumInsns*/1, /*MergeInsnID's*/0,
      GIR_ConstrainSelectedInstOperands, /*InsnID*/0,
      GIR_EraseFromParent, /*InsnID*/0,
      // GIR_Coverage, 5386,
      GIR_Done,
    // Label 1005: @65216
    GIM_Try, /*On fail goto*//*Label 1006*/ GIMT_Encode4(65294), // Rule ID 3412 //
      GIM_CheckFeatures, GIMT_Encode2(GIFBS_EnableFlatScratch_HasFlatScratchInsts_HasFlatScratchSVSMode),
      GIM_CheckMemorySizeLessThanLLT, /*MI*/0, /*MMO*/0, /*OpIdx*/0,
      GIM_CheckMemorySizeEqualTo, /*MI*/0, /*MMO*/0, /*Size*/GIMT_Encode4(1),
      GIM_CheckMemoryAddressSpace, /*MI*/0, /*MMO*/0, /*NumAddrSpace*/1, /*AddrSpace*/5,
      GIM_CheckAtomicOrdering, /*MI*/0, /*Order*/(uint8_t)AtomicOrdering::NotAtomic,
      GIM_CheckRegBankForClass, /*MI*/0, /*Op*/0, /*RC*/GIMT_Encode2(AMDGPU::AV_32RegClassID),
      GIM_CheckPointerToAny, /*MI*/0, /*Op*/1, /*SizeInBits*/0,
      GIM_CheckComplexPattern, /*MI*/0, /*Op*/1, /*Renderer*/GIMT_Encode2(0), GIMT_Encode2(GICP_gi_flat_scratch_svaddr),
      // (ld:{ *:[i16] } (ScratchSVAddr:{ *:[iPTR] } VGPR_32:{ *:[i32] }:$vaddr, SGPR_32:{ *:[i32] }:$saddr, i32:{ *:[i32] }:$offset))<<P:Predicate_unindexedload>><<P:Predicate_extload>><<P:Predicate_extloadi8>><<P:Predicate_extloadi8_private>>  =>  (SCRATCH_LOAD_UBYTE_SVS:{ *:[i16] } ?:{ *:[i32] }:$vaddr, ?:{ *:[i32] }:$saddr, ?:{ *:[i32] }:$offset, 0:{ *:[i32] })
      GIR_BuildMI, /*InsnID*/0, /*Opcode*/GIMT_Encode2(AMDGPU::SCRATCH_LOAD_UBYTE_SVS),
      GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/0, // DstI[vdst]
      GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/0, // vaddr
      GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/1, // saddr
      GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/2, // offset
      GIR_AddImm8, /*InsnID*/0, /*Imm*/0,
      GIR_MergeMemOperands, /*InsnID*/0, /*NumInsns*/1, /*MergeInsnID's*/0,
      GIR_ConstrainSelectedInstOperands, /*InsnID*/0,
      GIR_EraseFromParent, /*InsnID*/0,
      // GIR_Coverage, 3412,
      GIR_Done,
    // Label 1006: @65294
    GIM_Try, /*On fail goto*//*Label 1007*/ GIMT_Encode4(65361), // Rule ID 3430 //
      GIM_CheckFeatures, GIMT_Encode2(GIFBS_EnableFlatScratch_HasFlatScratchInsts_HasFlatScratchSVSMode),
      GIM_CheckMemoryAddressSpace, /*MI*/0, /*MMO*/0, /*NumAddrSpace*/1, /*AddrSpace*/5,
      GIM_CheckAtomicOrdering, /*MI*/0, /*Order*/(uint8_t)AtomicOrdering::NotAtomic,
      GIM_CheckRegBankForClass, /*MI*/0, /*Op*/0, /*RC*/GIMT_Encode2(AMDGPU::AV_32RegClassID),
      GIM_CheckPointerToAny, /*MI*/0, /*Op*/1, /*SizeInBits*/0,
      GIM_CheckComplexPattern, /*MI*/0, /*Op*/1, /*Renderer*/GIMT_Encode2(0), GIMT_Encode2(GICP_gi_flat_scratch_svaddr),
      // (ld:{ *:[i16] } (ScratchSVAddr:{ *:[iPTR] } VGPR_32:{ *:[i32] }:$vaddr, SGPR_32:{ *:[i32] }:$saddr, i32:{ *:[i32] }:$offset))<<P:Predicate_unindexedload>><<P:Predicate_load_private>>  =>  (SCRATCH_LOAD_USHORT_SVS:{ *:[i16] } ?:{ *:[i32] }:$vaddr, ?:{ *:[i32] }:$saddr, ?:{ *:[i32] }:$offset, 0:{ *:[i32] })
      GIR_BuildMI, /*InsnID*/0, /*Opcode*/GIMT_Encode2(AMDGPU::SCRATCH_LOAD_USHORT_SVS),
      GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/0, // DstI[vdst]
      GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/0, // vaddr
      GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/1, // saddr
      GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/2, // offset
      GIR_AddImm8, /*InsnID*/0, /*Imm*/0,
      GIR_MergeMemOperands, /*InsnID*/0, /*NumInsns*/1, /*MergeInsnID's*/0,
      GIR_ConstrainSelectedInstOperands, /*InsnID*/0,
      GIR_EraseFromParent, /*InsnID*/0,
      // GIR_Coverage, 3430,
      GIR_Done,
    // Label 1007: @65361
    GIM_Try, /*On fail goto*//*Label 1008*/ GIMT_Encode4(65434), // Rule ID 3411 //
      GIM_CheckFeatures, GIMT_Encode2(GIFBS_EnableFlatScratch_HasFlatScratchInsts),
      GIM_CheckMemorySizeLessThanLLT, /*MI*/0, /*MMO*/0, /*OpIdx*/0,
      GIM_CheckMemorySizeEqualTo, /*MI*/0, /*MMO*/0, /*Size*/GIMT_Encode4(1),
      GIM_CheckMemoryAddressSpace, /*MI*/0, /*MMO*/0, /*NumAddrSpace*/1, /*AddrSpace*/5,
      GIM_CheckAtomicOrdering, /*MI*/0, /*Order*/(uint8_t)AtomicOrdering::NotAtomic,
      GIM_CheckRegBankForClass, /*MI*/0, /*Op*/0, /*RC*/GIMT_Encode2(AMDGPU::AV_32RegClassID),
      GIM_CheckPointerToAny, /*MI*/0, /*Op*/1, /*SizeInBits*/0,
      GIM_CheckComplexPattern, /*MI*/0, /*Op*/1, /*Renderer*/GIMT_Encode2(0), GIMT_Encode2(GICP_gi_flat_scratch_saddr),
      // (ld:{ *:[i16] } (ScratchSAddr:{ *:[iPTR] } SGPR_32:{ *:[i32] }:$saddr, i32:{ *:[i32] }:$offset))<<P:Predicate_unindexedload>><<P:Predicate_extload>><<P:Predicate_extloadi8>><<P:Predicate_extloadi8_private>>  =>  (SCRATCH_LOAD_UBYTE_SADDR:{ *:[i16] } ?:{ *:[i32] }:$saddr, ?:{ *:[i32] }:$offset)
      GIR_BuildMI, /*InsnID*/0, /*Opcode*/GIMT_Encode2(AMDGPU::SCRATCH_LOAD_UBYTE_SADDR),
      GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/0, // DstI[vdst]
      GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/0, // saddr
      GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/1, // offset
      GIR_AddImm8, /*InsnID*/0, /*Imm*/0,
      GIR_MergeMemOperands, /*InsnID*/0, /*NumInsns*/1, /*MergeInsnID's*/0,
      GIR_ConstrainSelectedInstOperands, /*InsnID*/0,
      GIR_EraseFromParent, /*InsnID*/0,
      // GIR_Coverage, 3411,
      GIR_Done,
    // Label 1008: @65434
    GIM_Try, /*On fail goto*//*Label 1009*/ GIMT_Encode4(65496), // Rule ID 3429 //
      GIM_CheckFeatures, GIMT_Encode2(GIFBS_EnableFlatScratch_HasFlatScratchInsts),
      GIM_CheckMemoryAddressSpace, /*MI*/0, /*MMO*/0, /*NumAddrSpace*/1, /*AddrSpace*/5,
      GIM_CheckAtomicOrdering, /*MI*/0, /*Order*/(uint8_t)AtomicOrdering::NotAtomic,
      GIM_CheckRegBankForClass, /*MI*/0, /*Op*/0, /*RC*/GIMT_Encode2(AMDGPU::AV_32RegClassID),
      GIM_CheckPointerToAny, /*MI*/0, /*Op*/1, /*SizeInBits*/0,
      GIM_CheckComplexPattern, /*MI*/0, /*Op*/1, /*Renderer*/GIMT_Encode2(0), GIMT_Encode2(GICP_gi_flat_scratch_saddr),
      // (ld:{ *:[i16] } (ScratchSAddr:{ *:[iPTR] } SGPR_32:{ *:[i32] }:$saddr, i32:{ *:[i32] }:$offset))<<P:Predicate_unindexedload>><<P:Predicate_load_private>>  =>  (SCRATCH_LOAD_USHORT_SADDR:{ *:[i16] } ?:{ *:[i32] }:$saddr, ?:{ *:[i32] }:$offset)
      GIR_BuildMI, /*InsnID*/0, /*Opcode*/GIMT_Encode2(AMDGPU::SCRATCH_LOAD_USHORT_SADDR),
      GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/0, // DstI[vdst]
      GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/0, // saddr
      GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/1, // offset
      GIR_AddImm8, /*InsnID*/0, /*Imm*/0,
      GIR_MergeMemOperands, /*InsnID*/0, /*NumInsns*/1, /*MergeInsnID's*/0,
      GIR_ConstrainSelectedInstOperands, /*InsnID*/0,
      GIR_EraseFromParent, /*InsnID*/0,
      // GIR_Coverage, 3429,
      GIR_Done,
    // Label 1009: @65496
    GIM_Try, /*On fail goto*//*Label 1010*/ GIMT_Encode4(65569), // Rule ID 3410 //
      GIM_CheckFeatures, GIMT_Encode2(GIFBS_EnableFlatScratch_HasFlatScratchInsts),
      GIM_CheckMemorySizeLessThanLLT, /*MI*/0, /*MMO*/0, /*OpIdx*/0,
      GIM_CheckMemorySizeEqualTo, /*MI*/0, /*MMO*/0, /*Size*/GIMT_Encode4(1),
      GIM_CheckMemoryAddressSpace, /*MI*/0, /*MMO*/0, /*NumAddrSpace*/1, /*AddrSpace*/5,
      GIM_CheckAtomicOrdering, /*MI*/0, /*Order*/(uint8_t)AtomicOrdering::NotAtomic,
      GIM_CheckRegBankForClass, /*MI*/0, /*Op*/0, /*RC*/GIMT_Encode2(AMDGPU::AV_32RegClassID),
      GIM_CheckPointerToAny, /*MI*/0, /*Op*/1, /*SizeInBits*/0,
      GIM_CheckComplexPattern, /*MI*/0, /*Op*/1, /*Renderer*/GIMT_Encode2(0), GIMT_Encode2(GICP_gi_flat_scratch_offset),
      // (ld:{ *:[i16] } (ScratchOffset:{ *:[iPTR] } VGPR_32:{ *:[i32] }:$vaddr, i32:{ *:[i32] }:$offset))<<P:Predicate_unindexedload>><<P:Predicate_extload>><<P:Predicate_extloadi8>><<P:Predicate_extloadi8_private>>  =>  (SCRATCH_LOAD_UBYTE:{ *:[i16] } ?:{ *:[i32] }:$vaddr, ?:{ *:[i32] }:$offset)
      GIR_BuildMI, /*InsnID*/0, /*Opcode*/GIMT_Encode2(AMDGPU::SCRATCH_LOAD_UBYTE),
      GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/0, // DstI[vdst]
      GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/0, // vaddr
      GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/1, // offset
      GIR_AddImm8, /*InsnID*/0, /*Imm*/0,
      GIR_MergeMemOperands, /*InsnID*/0, /*NumInsns*/1, /*MergeInsnID's*/0,
      GIR_ConstrainSelectedInstOperands, /*InsnID*/0,
      GIR_EraseFromParent, /*InsnID*/0,
      // GIR_Coverage, 3410,
      GIR_Done,
    // Label 1010: @65569
    GIM_Try, /*On fail goto*//*Label 1011*/ GIMT_Encode4(65631), // Rule ID 3428 //
      GIM_CheckFeatures, GIMT_Encode2(GIFBS_EnableFlatScratch_HasFlatScratchInsts),
      GIM_CheckMemoryAddressSpace, /*MI*/0, /*MMO*/0, /*NumAddrSpace*/1, /*AddrSpace*/5,
      GIM_CheckAtomicOrdering, /*MI*/0, /*Order*/(uint8_t)AtomicOrdering::NotAtomic,
      GIM_CheckRegBankForClass, /*MI*/0, /*Op*/0, /*RC*/GIMT_Encode2(AMDGPU::AV_32RegClassID),
      GIM_CheckPointerToAny, /*MI*/0, /*Op*/1, /*SizeInBits*/0,
      GIM_CheckComplexPattern, /*MI*/0, /*Op*/1, /*Renderer*/GIMT_Encode2(0), GIMT_Encode2(GICP_gi_flat_scratch_offset),
      // (ld:{ *:[i16] } (ScratchOffset:{ *:[iPTR] } VGPR_32:{ *:[i32] }:$vaddr, i32:{ *:[i32] }:$offset))<<P:Predicate_unindexedload>><<P:Predicate_load_private>>  =>  (SCRATCH_LOAD_USHORT:{ *:[i16] } ?:{ *:[i32] }:$vaddr, ?:{ *:[i32] }:$offset)
      GIR_BuildMI, /*InsnID*/0, /*Opcode*/GIMT_Encode2(AMDGPU::SCRATCH_LOAD_USHORT),
      GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/0, // DstI[vdst]
      GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/0, // vaddr
      GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/1, // offset
      GIR_AddImm8, /*InsnID*/0, /*Imm*/0,
      GIR_MergeMemOperands, /*InsnID*/0, /*NumInsns*/1, /*MergeInsnID's*/0,
      GIR_ConstrainSelectedInstOperands, /*InsnID*/0,
      GIR_EraseFromParent, /*InsnID*/0,
      // GIR_Coverage, 3428,
      GIR_Done,
    // Label 1011: @65631
    GIM_Try, /*On fail goto*//*Label 1012*/ GIMT_Encode4(65715), // Rule ID 3652 //
      GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasUnrestrictedSOffset),
      GIM_CheckMemorySizeEqualTo, /*MI*/0, /*MMO*/0, /*Size*/GIMT_Encode4(1),
      GIM_CheckMemoryAddressSpace, /*MI*/0, /*MMO*/0, /*NumAddrSpace*/3, /*AddrSpace*/1, /*AddrSpace*/4, /*AddrSpace*/6,
      GIM_CheckAtomicOrderingOrStrongerThan, /*MI*/0, /*Order*/(uint8_t)AtomicOrdering::Unordered,
      GIM_CheckRegBankForClass, /*MI*/0, /*Op*/0, /*RC*/GIMT_Encode2(AMDGPU::AV_32RegClassID),
      GIM_CheckPointerToAny, /*MI*/0, /*Op*/1, /*SizeInBits*/0,
      GIM_CheckComplexPattern, /*MI*/0, /*Op*/1, /*Renderer*/GIMT_Encode2(0), GIMT_Encode2(GICP_gi_mubuf_addr64),
      // (atomic_load:{ *:[i16] } (MUBUFAddr64:{ *:[iPTR] } v4i32:{ *:[v4i32] }:$srsrc, i64:{ *:[i64] }:$vaddr, i32:{ *:[i32] }:$soffset, i32:{ *:[i32] }:$offset))<<P:Predicate_atomic_load_8>><<P:Predicate_atomic_load_8_global>>  =>  (BUFFER_LOAD_UBYTE_ADDR64:{ *:[i16] } i64:{ *:[i64] }:$vaddr, v4i32:{ *:[v4i32] }:$srsrc, i32:{ *:[i32] }:$soffset, i32:{ *:[i32] }:$offset)
      GIR_BuildMI, /*InsnID*/0, /*Opcode*/GIMT_Encode2(AMDGPU::BUFFER_LOAD_UBYTE_ADDR64),
      GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/0, // DstI[vdata]
      GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/1, // vaddr
      GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/0, // srsrc
      GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/2, // soffset
      GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/3, // offset
      GIR_AddImm8, /*InsnID*/0, /*Imm*/0,
      GIR_AddImm8, /*InsnID*/0, /*Imm*/0,
      GIR_MergeMemOperands, /*InsnID*/0, /*NumInsns*/1, /*MergeInsnID's*/0,
      GIR_ConstrainSelectedInstOperands, /*InsnID*/0,
      GIR_EraseFromParent, /*InsnID*/0,
      // GIR_Coverage, 3652,
      GIR_Done,
    // Label 1012: @65715
    GIM_Try, /*On fail goto*//*Label 1013*/ GIMT_Encode4(65796), // Rule ID 3654 //
      GIM_CheckMemorySizeEqualTo, /*MI*/0, /*MMO*/0, /*Size*/GIMT_Encode4(1),
      GIM_CheckMemoryAddressSpace, /*MI*/0, /*MMO*/0, /*NumAddrSpace*/3, /*AddrSpace*/1, /*AddrSpace*/4, /*AddrSpace*/6,
      GIM_CheckAtomicOrderingOrStrongerThan, /*MI*/0, /*Order*/(uint8_t)AtomicOrdering::Unordered,
      GIM_CheckRegBankForClass, /*MI*/0, /*Op*/0, /*RC*/GIMT_Encode2(AMDGPU::AV_32RegClassID),
      GIM_CheckPointerToAny, /*MI*/0, /*Op*/1, /*SizeInBits*/0,
      GIM_CheckComplexPattern, /*MI*/0, /*Op*/1, /*Renderer*/GIMT_Encode2(0), GIMT_Encode2(GICP_gi_mubuf_addr64),
      // (atomic_load:{ *:[i16] } (MUBUFAddr64:{ *:[iPTR] } v4i32:{ *:[v4i32] }:$srsrc, i64:{ *:[i64] }:$vaddr, i32:{ *:[i32] }:$soffset, i32:{ *:[i32] }:$offset))<<P:Predicate_atomic_load_8>><<P:Predicate_atomic_load_8_global>>  =>  (BUFFER_LOAD_UBYTE_VBUFFER_ADDR64:{ *:[i16] } i64:{ *:[i64] }:$vaddr, v4i32:{ *:[v4i32] }:$srsrc, i32:{ *:[i32] }:$soffset, i32:{ *:[i32] }:$offset)
      GIR_BuildMI, /*InsnID*/0, /*Opcode*/GIMT_Encode2(AMDGPU::BUFFER_LOAD_UBYTE_VBUFFER_ADDR64),
      GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/0, // DstI[vdata]
      GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/1, // vaddr
      GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/0, // srsrc
      GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/2, // soffset
      GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/3, // offset
      GIR_AddImm8, /*InsnID*/0, /*Imm*/0,
      GIR_AddImm8, /*InsnID*/0, /*Imm*/0,
      GIR_MergeMemOperands, /*InsnID*/0, /*NumInsns*/1, /*MergeInsnID's*/0,
      GIR_ConstrainSelectedInstOperands, /*InsnID*/0,
      GIR_EraseFromParent, /*InsnID*/0,
      // GIR_Coverage, 3654,
      GIR_Done,
    // Label 1013: @65796
    GIM_Try, /*On fail goto*//*Label 1014*/ GIMT_Encode4(65880), // Rule ID 3656 //
      GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasUnrestrictedSOffset),
      GIM_CheckMemorySizeEqualTo, /*MI*/0, /*MMO*/0, /*Size*/GIMT_Encode4(2),
      GIM_CheckMemoryAddressSpace, /*MI*/0, /*MMO*/0, /*NumAddrSpace*/3, /*AddrSpace*/1, /*AddrSpace*/4, /*AddrSpace*/6,
      GIM_CheckAtomicOrderingOrStrongerThan, /*MI*/0, /*Order*/(uint8_t)AtomicOrdering::Unordered,
      GIM_CheckRegBankForClass, /*MI*/0, /*Op*/0, /*RC*/GIMT_Encode2(AMDGPU::AV_32RegClassID),
      GIM_CheckPointerToAny, /*MI*/0, /*Op*/1, /*SizeInBits*/0,
      GIM_CheckComplexPattern, /*MI*/0, /*Op*/1, /*Renderer*/GIMT_Encode2(0), GIMT_Encode2(GICP_gi_mubuf_addr64),
      // (atomic_load:{ *:[i16] } (MUBUFAddr64:{ *:[iPTR] } v4i32:{ *:[v4i32] }:$srsrc, i64:{ *:[i64] }:$vaddr, i32:{ *:[i32] }:$soffset, i32:{ *:[i32] }:$offset))<<P:Predicate_atomic_load_16>><<P:Predicate_atomic_load_16_global>>  =>  (BUFFER_LOAD_USHORT_ADDR64:{ *:[i16] } i64:{ *:[i64] }:$vaddr, v4i32:{ *:[v4i32] }:$srsrc, i32:{ *:[i32] }:$soffset, i32:{ *:[i32] }:$offset)
      GIR_BuildMI, /*InsnID*/0, /*Opcode*/GIMT_Encode2(AMDGPU::BUFFER_LOAD_USHORT_ADDR64),
      GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/0, // DstI[vdata]
      GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/1, // vaddr
      GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/0, // srsrc
      GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/2, // soffset
      GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/3, // offset
      GIR_AddImm8, /*InsnID*/0, /*Imm*/0,
      GIR_AddImm8, /*InsnID*/0, /*Imm*/0,
      GIR_MergeMemOperands, /*InsnID*/0, /*NumInsns*/1, /*MergeInsnID's*/0,
      GIR_ConstrainSelectedInstOperands, /*InsnID*/0,
      GIR_EraseFromParent, /*InsnID*/0,
      // GIR_Coverage, 3656,
      GIR_Done,
    // Label 1014: @65880
    GIM_Try, /*On fail goto*//*Label 1015*/ GIMT_Encode4(65961), // Rule ID 3658 //
      GIM_CheckMemorySizeEqualTo, /*MI*/0, /*MMO*/0, /*Size*/GIMT_Encode4(2),
      GIM_CheckMemoryAddressSpace, /*MI*/0, /*MMO*/0, /*NumAddrSpace*/3, /*AddrSpace*/1, /*AddrSpace*/4, /*AddrSpace*/6,
      GIM_CheckAtomicOrderingOrStrongerThan, /*MI*/0, /*Order*/(uint8_t)AtomicOrdering::Unordered,
      GIM_CheckRegBankForClass, /*MI*/0, /*Op*/0, /*RC*/GIMT_Encode2(AMDGPU::AV_32RegClassID),
      GIM_CheckPointerToAny, /*MI*/0, /*Op*/1, /*SizeInBits*/0,
      GIM_CheckComplexPattern, /*MI*/0, /*Op*/1, /*Renderer*/GIMT_Encode2(0), GIMT_Encode2(GICP_gi_mubuf_addr64),
      // (atomic_load:{ *:[i16] } (MUBUFAddr64:{ *:[iPTR] } v4i32:{ *:[v4i32] }:$srsrc, i64:{ *:[i64] }:$vaddr, i32:{ *:[i32] }:$soffset, i32:{ *:[i32] }:$offset))<<P:Predicate_atomic_load_16>><<P:Predicate_atomic_load_16_global>>  =>  (BUFFER_LOAD_USHORT_VBUFFER_ADDR64:{ *:[i16] } i64:{ *:[i64] }:$vaddr, v4i32:{ *:[v4i32] }:$srsrc, i32:{ *:[i32] }:$soffset, i32:{ *:[i32] }:$offset)
      GIR_BuildMI, /*InsnID*/0, /*Opcode*/GIMT_Encode2(AMDGPU::BUFFER_LOAD_USHORT_VBUFFER_ADDR64),
      GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/0, // DstI[vdata]
      GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/1, // vaddr
      GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/0, // srsrc
      GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/2, // soffset
      GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/3, // offset
      GIR_AddImm8, /*InsnID*/0, /*Imm*/0,
      GIR_AddImm8, /*InsnID*/0, /*Imm*/0,
      GIR_MergeMemOperands, /*InsnID*/0, /*NumInsns*/1, /*MergeInsnID's*/0,
      GIR_ConstrainSelectedInstOperands, /*InsnID*/0,
      GIR_EraseFromParent, /*InsnID*/0,
      // GIR_Coverage, 3658,
      GIR_Done,
    // Label 1015: @65961
    GIM_Try, /*On fail goto*//*Label 1016*/ GIMT_Encode4(66047), // Rule ID 5363 //
      GIM_CheckFeatures, GIMT_Encode2(GIFBS_DisableFlatScratch_HasUnrestrictedSOffset),
      GIM_CheckMemorySizeLessThanLLT, /*MI*/0, /*MMO*/0, /*OpIdx*/0,
      GIM_CheckMemorySizeEqualTo, /*MI*/0, /*MMO*/0, /*Size*/GIMT_Encode4(1),
      GIM_CheckMemoryAddressSpace, /*MI*/0, /*MMO*/0, /*NumAddrSpace*/1, /*AddrSpace*/5,
      GIM_CheckAtomicOrdering, /*MI*/0, /*Order*/(uint8_t)AtomicOrdering::NotAtomic,
      GIM_CheckRegBankForClass, /*MI*/0, /*Op*/0, /*RC*/GIMT_Encode2(AMDGPU::AV_32RegClassID),
      GIM_CheckPointerToAny, /*MI*/0, /*Op*/1, /*SizeInBits*/0,
      GIM_CheckComplexPattern, /*MI*/0, /*Op*/1, /*Renderer*/GIMT_Encode2(0), GIMT_Encode2(GICP_gi_mubuf_scratch_offen),
      // (ld:{ *:[i16] } (MUBUFScratchOffen:{ *:[iPTR] } v4i32:{ *:[v4i32] }:$srsrc, i32:{ *:[i32] }:$vaddr, i32:{ *:[i32] }:$soffset, i32:{ *:[i32] }:$offset))<<P:Predicate_unindexedload>><<P:Predicate_extload>><<P:Predicate_extloadi8>><<P:Predicate_extloadi8_private>>  =>  (BUFFER_LOAD_UBYTE_OFFEN:{ *:[i16] } ?:{ *:[i32] }:$vaddr, ?:{ *:[v4i32] }:$srsrc, ?:{ *:[i32] }:$soffset, ?:{ *:[i32] }:$offset, 0:{ *:[i32] }, 0:{ *:[i1] })
      GIR_BuildMI, /*InsnID*/0, /*Opcode*/GIMT_Encode2(AMDGPU::BUFFER_LOAD_UBYTE_OFFEN),
      GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/0, // DstI[vdata]
      GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/1, // vaddr
      GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/0, // srsrc
      GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/2, // soffset
      GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/3, // offset
      GIR_AddImm8, /*InsnID*/0, /*Imm*/0,
      GIR_AddImm8, /*InsnID*/0, /*Imm*/0,
      GIR_MergeMemOperands, /*InsnID*/0, /*NumInsns*/1, /*MergeInsnID's*/0,
      GIR_ConstrainSelectedInstOperands, /*InsnID*/0,
      GIR_EraseFromParent, /*InsnID*/0,
      // GIR_Coverage, 5363,
      GIR_Done,
    // Label 1016: @66047
    GIM_Try, /*On fail goto*//*Label 1017*/ GIMT_Encode4(66133), // Rule ID 5365 //
      GIM_CheckFeatures, GIMT_Encode2(GIFBS_DisableFlatScratch),
      GIM_CheckMemorySizeLessThanLLT, /*MI*/0, /*MMO*/0, /*OpIdx*/0,
      GIM_CheckMemorySizeEqualTo, /*MI*/0, /*MMO*/0, /*Size*/GIMT_Encode4(1),
      GIM_CheckMemoryAddressSpace, /*MI*/0, /*MMO*/0, /*NumAddrSpace*/1, /*AddrSpace*/5,
      GIM_CheckAtomicOrdering, /*MI*/0, /*Order*/(uint8_t)AtomicOrdering::NotAtomic,
      GIM_CheckRegBankForClass, /*MI*/0, /*Op*/0, /*RC*/GIMT_Encode2(AMDGPU::AV_32RegClassID),
      GIM_CheckPointerToAny, /*MI*/0, /*Op*/1, /*SizeInBits*/0,
      GIM_CheckComplexPattern, /*MI*/0, /*Op*/1, /*Renderer*/GIMT_Encode2(0), GIMT_Encode2(GICP_gi_mubuf_scratch_offen),
      // (ld:{ *:[i16] } (MUBUFScratchOffen:{ *:[iPTR] } v4i32:{ *:[v4i32] }:$srsrc, i32:{ *:[i32] }:$vaddr, i32:{ *:[i32] }:$soffset, i32:{ *:[i32] }:$offset))<<P:Predicate_unindexedload>><<P:Predicate_extload>><<P:Predicate_extloadi8>><<P:Predicate_extloadi8_private>>  =>  (BUFFER_LOAD_UBYTE_VBUFFER_OFFEN:{ *:[i16] } ?:{ *:[i32] }:$vaddr, ?:{ *:[v4i32] }:$srsrc, ?:{ *:[i32] }:$soffset, ?:{ *:[i32] }:$offset, 0:{ *:[i32] }, 0:{ *:[i1] })
      GIR_BuildMI, /*InsnID*/0, /*Opcode*/GIMT_Encode2(AMDGPU::BUFFER_LOAD_UBYTE_VBUFFER_OFFEN),
      GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/0, // DstI[vdata]
      GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/1, // vaddr
      GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/0, // srsrc
      GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/2, // soffset
      GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/3, // offset
      GIR_AddImm8, /*InsnID*/0, /*Imm*/0,
      GIR_AddImm8, /*InsnID*/0, /*Imm*/0,
      GIR_MergeMemOperands, /*InsnID*/0, /*NumInsns*/1, /*MergeInsnID's*/0,
      GIR_ConstrainSelectedInstOperands, /*InsnID*/0,
      GIR_EraseFromParent, /*InsnID*/0,
      // GIR_Coverage, 5365,
      GIR_Done,
    // Label 1017: @66133
    GIM_Try, /*On fail goto*//*Label 1018*/ GIMT_Encode4(66208), // Rule ID 5383 //
      GIM_CheckFeatures, GIMT_Encode2(GIFBS_DisableFlatScratch_HasUnrestrictedSOffset),
      GIM_CheckMemoryAddressSpace, /*MI*/0, /*MMO*/0, /*NumAddrSpace*/1, /*AddrSpace*/5,
      GIM_CheckAtomicOrdering, /*MI*/0, /*Order*/(uint8_t)AtomicOrdering::NotAtomic,
      GIM_CheckRegBankForClass, /*MI*/0, /*Op*/0, /*RC*/GIMT_Encode2(AMDGPU::AV_32RegClassID),
      GIM_CheckPointerToAny, /*MI*/0, /*Op*/1, /*SizeInBits*/0,
      GIM_CheckComplexPattern, /*MI*/0, /*Op*/1, /*Renderer*/GIMT_Encode2(0), GIMT_Encode2(GICP_gi_mubuf_scratch_offen),
      // (ld:{ *:[i16] } (MUBUFScratchOffen:{ *:[iPTR] } v4i32:{ *:[v4i32] }:$srsrc, i32:{ *:[i32] }:$vaddr, i32:{ *:[i32] }:$soffset, i32:{ *:[i32] }:$offset))<<P:Predicate_unindexedload>><<P:Predicate_load_private>>  =>  (BUFFER_LOAD_USHORT_OFFEN:{ *:[i16] } ?:{ *:[i32] }:$vaddr, ?:{ *:[v4i32] }:$srsrc, ?:{ *:[i32] }:$soffset, ?:{ *:[i32] }:$offset, 0:{ *:[i32] }, 0:{ *:[i1] })
      GIR_BuildMI, /*InsnID*/0, /*Opcode*/GIMT_Encode2(AMDGPU::BUFFER_LOAD_USHORT_OFFEN),
      GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/0, // DstI[vdata]
      GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/1, // vaddr
      GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/0, // srsrc
      GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/2, // soffset
      GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/3, // offset
      GIR_AddImm8, /*InsnID*/0, /*Imm*/0,
      GIR_AddImm8, /*InsnID*/0, /*Imm*/0,
      GIR_MergeMemOperands, /*InsnID*/0, /*NumInsns*/1, /*MergeInsnID's*/0,
      GIR_ConstrainSelectedInstOperands, /*InsnID*/0,
      GIR_EraseFromParent, /*InsnID*/0,
      // GIR_Coverage, 5383,
      GIR_Done,
    // Label 1018: @66208
    GIM_Try, /*On fail goto*//*Label 1019*/ GIMT_Encode4(66283), // Rule ID 5385 //
      GIM_CheckFeatures, GIMT_Encode2(GIFBS_DisableFlatScratch),
      GIM_CheckMemoryAddressSpace, /*MI*/0, /*MMO*/0, /*NumAddrSpace*/1, /*AddrSpace*/5,
      GIM_CheckAtomicOrdering, /*MI*/0, /*Order*/(uint8_t)AtomicOrdering::NotAtomic,
      GIM_CheckRegBankForClass, /*MI*/0, /*Op*/0, /*RC*/GIMT_Encode2(AMDGPU::AV_32RegClassID),
      GIM_CheckPointerToAny, /*MI*/0, /*Op*/1, /*SizeInBits*/0,
      GIM_CheckComplexPattern, /*MI*/0, /*Op*/1, /*Renderer*/GIMT_Encode2(0), GIMT_Encode2(GICP_gi_mubuf_scratch_offen),
      // (ld:{ *:[i16] } (MUBUFScratchOffen:{ *:[iPTR] } v4i32:{ *:[v4i32] }:$srsrc, i32:{ *:[i32] }:$vaddr, i32:{ *:[i32] }:$soffset, i32:{ *:[i32] }:$offset))<<P:Predicate_unindexedload>><<P:Predicate_load_private>>  =>  (BUFFER_LOAD_USHORT_VBUFFER_OFFEN:{ *:[i16] } ?:{ *:[i32] }:$vaddr, ?:{ *:[v4i32] }:$srsrc, ?:{ *:[i32] }:$soffset, ?:{ *:[i32] }:$offset, 0:{ *:[i32] }, 0:{ *:[i1] })
      GIR_BuildMI, /*InsnID*/0, /*Opcode*/GIMT_Encode2(AMDGPU::BUFFER_LOAD_USHORT_VBUFFER_OFFEN),
      GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/0, // DstI[vdata]
      GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/1, // vaddr
      GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/0, // srsrc
      GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/2, // soffset
      GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/3, // offset
      GIR_AddImm8, /*InsnID*/0, /*Imm*/0,
      GIR_AddImm8, /*InsnID*/0, /*Imm*/0,
      GIR_MergeMemOperands, /*InsnID*/0, /*NumInsns*/1, /*MergeInsnID's*/0,
      GIR_ConstrainSelectedInstOperands, /*InsnID*/0,
      GIR_EraseFromParent, /*InsnID*/0,
      // GIR_Coverage, 5385,
      GIR_Done,
    // Label 1019: @66283
    GIM_Try, /*On fail goto*//*Label 1020*/ GIMT_Encode4(66362), // Rule ID 3651 //
      GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasUnrestrictedSOffset),
      GIM_CheckMemorySizeEqualTo, /*MI*/0, /*MMO*/0, /*Size*/GIMT_Encode4(1),
      GIM_CheckMemoryAddressSpace, /*MI*/0, /*MMO*/0, /*NumAddrSpace*/3, /*AddrSpace*/1, /*AddrSpace*/4, /*AddrSpace*/6,
      GIM_CheckAtomicOrderingOrStrongerThan, /*MI*/0, /*Order*/(uint8_t)AtomicOrdering::Unordered,
      GIM_CheckRegBankForClass, /*MI*/0, /*Op*/0, /*RC*/GIMT_Encode2(AMDGPU::AV_32RegClassID),
      GIM_CheckPointerToAny, /*MI*/0, /*Op*/1, /*SizeInBits*/0,
      GIM_CheckComplexPattern, /*MI*/0, /*Op*/1, /*Renderer*/GIMT_Encode2(0), GIMT_Encode2(GICP_gi_mubuf_offset),
      // (atomic_load:{ *:[i16] } (MUBUFOffset:{ *:[iPTR] } v4i32:{ *:[v4i32] }:$srsrc, i32:{ *:[i32] }:$soffset, i32:{ *:[i32] }:$offset))<<P:Predicate_atomic_load_8>><<P:Predicate_atomic_load_8_global>>  =>  (BUFFER_LOAD_UBYTE_OFFSET:{ *:[i16] } v4i32:{ *:[v4i32] }:$srsrc, i32:{ *:[i32] }:$soffset, i32:{ *:[i32] }:$offset)
      GIR_BuildMI, /*InsnID*/0, /*Opcode*/GIMT_Encode2(AMDGPU::BUFFER_LOAD_UBYTE_OFFSET),
      GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/0, // DstI[vdata]
      GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/0, // srsrc
      GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/1, // soffset
      GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/2, // offset
      GIR_AddImm8, /*InsnID*/0, /*Imm*/0,
      GIR_AddImm8, /*InsnID*/0, /*Imm*/0,
      GIR_MergeMemOperands, /*InsnID*/0, /*NumInsns*/1, /*MergeInsnID's*/0,
      GIR_ConstrainSelectedInstOperands, /*InsnID*/0,
      GIR_EraseFromParent, /*InsnID*/0,
      // GIR_Coverage, 3651,
      GIR_Done,
    // Label 1020: @66362
    GIM_Try, /*On fail goto*//*Label 1021*/ GIMT_Encode4(66438), // Rule ID 3653 //
      GIM_CheckMemorySizeEqualTo, /*MI*/0, /*MMO*/0, /*Size*/GIMT_Encode4(1),
      GIM_CheckMemoryAddressSpace, /*MI*/0, /*MMO*/0, /*NumAddrSpace*/3, /*AddrSpace*/1, /*AddrSpace*/4, /*AddrSpace*/6,
      GIM_CheckAtomicOrderingOrStrongerThan, /*MI*/0, /*Order*/(uint8_t)AtomicOrdering::Unordered,
      GIM_CheckRegBankForClass, /*MI*/0, /*Op*/0, /*RC*/GIMT_Encode2(AMDGPU::AV_32RegClassID),
      GIM_CheckPointerToAny, /*MI*/0, /*Op*/1, /*SizeInBits*/0,
      GIM_CheckComplexPattern, /*MI*/0, /*Op*/1, /*Renderer*/GIMT_Encode2(0), GIMT_Encode2(GICP_gi_mubuf_offset),
      // (atomic_load:{ *:[i16] } (MUBUFOffset:{ *:[iPTR] } v4i32:{ *:[v4i32] }:$srsrc, i32:{ *:[i32] }:$soffset, i32:{ *:[i32] }:$offset))<<P:Predicate_atomic_load_8>><<P:Predicate_atomic_load_8_global>>  =>  (BUFFER_LOAD_UBYTE_VBUFFER_OFFSET:{ *:[i16] } v4i32:{ *:[v4i32] }:$srsrc, i32:{ *:[i32] }:$soffset, i32:{ *:[i32] }:$offset)
      GIR_BuildMI, /*InsnID*/0, /*Opcode*/GIMT_Encode2(AMDGPU::BUFFER_LOAD_UBYTE_VBUFFER_OFFSET),
      GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/0, // DstI[vdata]
      GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/0, // srsrc
      GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/1, // soffset
      GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/2, // offset
      GIR_AddImm8, /*InsnID*/0, /*Imm*/0,
      GIR_AddImm8, /*InsnID*/0, /*Imm*/0,
      GIR_MergeMemOperands, /*InsnID*/0, /*NumInsns*/1, /*MergeInsnID's*/0,
      GIR_ConstrainSelectedInstOperands, /*InsnID*/0,
      GIR_EraseFromParent, /*InsnID*/0,
      // GIR_Coverage, 3653,
      GIR_Done,
    // Label 1021: @66438
    GIM_Try, /*On fail goto*//*Label 1022*/ GIMT_Encode4(66517), // Rule ID 3655 //
      GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasUnrestrictedSOffset),
      GIM_CheckMemorySizeEqualTo, /*MI*/0, /*MMO*/0, /*Size*/GIMT_Encode4(2),
      GIM_CheckMemoryAddressSpace, /*MI*/0, /*MMO*/0, /*NumAddrSpace*/3, /*AddrSpace*/1, /*AddrSpace*/4, /*AddrSpace*/6,
      GIM_CheckAtomicOrderingOrStrongerThan, /*MI*/0, /*Order*/(uint8_t)AtomicOrdering::Unordered,
      GIM_CheckRegBankForClass, /*MI*/0, /*Op*/0, /*RC*/GIMT_Encode2(AMDGPU::AV_32RegClassID),
      GIM_CheckPointerToAny, /*MI*/0, /*Op*/1, /*SizeInBits*/0,
      GIM_CheckComplexPattern, /*MI*/0, /*Op*/1, /*Renderer*/GIMT_Encode2(0), GIMT_Encode2(GICP_gi_mubuf_offset),
      // (atomic_load:{ *:[i16] } (MUBUFOffset:{ *:[iPTR] } v4i32:{ *:[v4i32] }:$srsrc, i32:{ *:[i32] }:$soffset, i32:{ *:[i32] }:$offset))<<P:Predicate_atomic_load_16>><<P:Predicate_atomic_load_16_global>>  =>  (BUFFER_LOAD_USHORT_OFFSET:{ *:[i16] } v4i32:{ *:[v4i32] }:$srsrc, i32:{ *:[i32] }:$soffset, i32:{ *:[i32] }:$offset)
      GIR_BuildMI, /*InsnID*/0, /*Opcode*/GIMT_Encode2(AMDGPU::BUFFER_LOAD_USHORT_OFFSET),
      GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/0, // DstI[vdata]
      GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/0, // srsrc
      GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/1, // soffset
      GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/2, // offset
      GIR_AddImm8, /*InsnID*/0, /*Imm*/0,
      GIR_AddImm8, /*InsnID*/0, /*Imm*/0,
      GIR_MergeMemOperands, /*InsnID*/0, /*NumInsns*/1, /*MergeInsnID's*/0,
      GIR_ConstrainSelectedInstOperands, /*InsnID*/0,
      GIR_EraseFromParent, /*InsnID*/0,
      // GIR_Coverage, 3655,
      GIR_Done,
    // Label 1022: @66517
    GIM_Try, /*On fail goto*//*Label 1023*/ GIMT_Encode4(66593), // Rule ID 3657 //
      GIM_CheckMemorySizeEqualTo, /*MI*/0, /*MMO*/0, /*Size*/GIMT_Encode4(2),
      GIM_CheckMemoryAddressSpace, /*MI*/0, /*MMO*/0, /*NumAddrSpace*/3, /*AddrSpace*/1, /*AddrSpace*/4, /*AddrSpace*/6,
      GIM_CheckAtomicOrderingOrStrongerThan, /*MI*/0, /*Order*/(uint8_t)AtomicOrdering::Unordered,
      GIM_CheckRegBankForClass, /*MI*/0, /*Op*/0, /*RC*/GIMT_Encode2(AMDGPU::AV_32RegClassID),
      GIM_CheckPointerToAny, /*MI*/0, /*Op*/1, /*SizeInBits*/0,
      GIM_CheckComplexPattern, /*MI*/0, /*Op*/1, /*Renderer*/GIMT_Encode2(0), GIMT_Encode2(GICP_gi_mubuf_offset),
      // (atomic_load:{ *:[i16] } (MUBUFOffset:{ *:[iPTR] } v4i32:{ *:[v4i32] }:$srsrc, i32:{ *:[i32] }:$soffset, i32:{ *:[i32] }:$offset))<<P:Predicate_atomic_load_16>><<P:Predicate_atomic_load_16_global>>  =>  (BUFFER_LOAD_USHORT_VBUFFER_OFFSET:{ *:[i16] } v4i32:{ *:[v4i32] }:$srsrc, i32:{ *:[i32] }:$soffset, i32:{ *:[i32] }:$offset)
      GIR_BuildMI, /*InsnID*/0, /*Opcode*/GIMT_Encode2(AMDGPU::BUFFER_LOAD_USHORT_VBUFFER_OFFSET),
      GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/0, // DstI[vdata]
      GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/0, // srsrc
      GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/1, // soffset
      GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/2, // offset
      GIR_AddImm8, /*InsnID*/0, /*Imm*/0,
      GIR_AddImm8, /*InsnID*/0, /*Imm*/0,
      GIR_MergeMemOperands, /*InsnID*/0, /*NumInsns*/1, /*MergeInsnID's*/0,
      GIR_ConstrainSelectedInstOperands, /*InsnID*/0,
      GIR_EraseFromParent, /*InsnID*/0,
      // GIR_Coverage, 3657,
      GIR_Done,
    // Label 1023: @66593
    GIM_Try, /*On fail goto*//*Label 1024*/ GIMT_Encode4(66675), // Rule ID 5333 //
      GIM_CheckFeatures, GIMT_Encode2(GIFBS_Has16BitInsts_HasUnrestrictedSOffset),
      GIM_CheckMemorySizeLessThanLLT, /*MI*/0, /*MMO*/0, /*OpIdx*/0,
      GIM_CheckMemorySizeEqualTo, /*MI*/0, /*MMO*/0, /*Size*/GIMT_Encode4(1),
      GIM_CheckMemoryAddressSpace, /*MI*/0, /*MMO*/0, /*NumAddrSpace*/2, /*AddrSpace*/4, /*AddrSpace*/6,
      GIM_CheckAtomicOrdering, /*MI*/0, /*Order*/(uint8_t)AtomicOrdering::NotAtomic,
      GIM_CheckRegBankForClass, /*MI*/0, /*Op*/0, /*RC*/GIMT_Encode2(AMDGPU::AV_32RegClassID),
      GIM_CheckPointerToAny, /*MI*/0, /*Op*/1, /*SizeInBits*/0,
      GIM_CheckComplexPattern, /*MI*/0, /*Op*/1, /*Renderer*/GIMT_Encode2(0), GIMT_Encode2(GICP_gi_mubuf_offset),
      // (ld:{ *:[i16] } (MUBUFOffset:{ *:[iPTR] } v4i32:{ *:[v4i32] }:$srsrc, i32:{ *:[i32] }:$soffset, i32:{ *:[i32] }:$offset))<<P:Predicate_unindexedload>><<P:Predicate_extload>><<P:Predicate_extloadi8>><<P:Predicate_extloadi8_constant>>  =>  (BUFFER_LOAD_UBYTE_OFFSET:{ *:[i16] } ?:{ *:[v4i32] }:$srsrc, ?:{ *:[i32] }:$soffset, ?:{ *:[i32] }:$offset)
      GIR_BuildMI, /*InsnID*/0, /*Opcode*/GIMT_Encode2(AMDGPU::BUFFER_LOAD_UBYTE_OFFSET),
      GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/0, // DstI[vdata]
      GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/0, // srsrc
      GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/1, // soffset
      GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/2, // offset
      GIR_AddImm8, /*InsnID*/0, /*Imm*/0,
      GIR_AddImm8, /*InsnID*/0, /*Imm*/0,
      GIR_MergeMemOperands, /*InsnID*/0, /*NumInsns*/1, /*MergeInsnID's*/0,
      GIR_ConstrainSelectedInstOperands, /*InsnID*/0,
      GIR_EraseFromParent, /*InsnID*/0,
      // GIR_Coverage, 5333,
      GIR_Done,
    // Label 1024: @66675
    GIM_Try, /*On fail goto*//*Label 1025*/ GIMT_Encode4(66757), // Rule ID 5334 //
      GIM_CheckFeatures, GIMT_Encode2(GIFBS_Has16BitInsts),
      GIM_CheckMemorySizeLessThanLLT, /*MI*/0, /*MMO*/0, /*OpIdx*/0,
      GIM_CheckMemorySizeEqualTo, /*MI*/0, /*MMO*/0, /*Size*/GIMT_Encode4(1),
      GIM_CheckMemoryAddressSpace, /*MI*/0, /*MMO*/0, /*NumAddrSpace*/2, /*AddrSpace*/4, /*AddrSpace*/6,
      GIM_CheckAtomicOrdering, /*MI*/0, /*Order*/(uint8_t)AtomicOrdering::NotAtomic,
      GIM_CheckRegBankForClass, /*MI*/0, /*Op*/0, /*RC*/GIMT_Encode2(AMDGPU::AV_32RegClassID),
      GIM_CheckPointerToAny, /*MI*/0, /*Op*/1, /*SizeInBits*/0,
      GIM_CheckComplexPattern, /*MI*/0, /*Op*/1, /*Renderer*/GIMT_Encode2(0), GIMT_Encode2(GICP_gi_mubuf_offset),
      // (ld:{ *:[i16] } (MUBUFOffset:{ *:[iPTR] } v4i32:{ *:[v4i32] }:$srsrc, i32:{ *:[i32] }:$soffset, i32:{ *:[i32] }:$offset))<<P:Predicate_unindexedload>><<P:Predicate_extload>><<P:Predicate_extloadi8>><<P:Predicate_extloadi8_constant>>  =>  (BUFFER_LOAD_UBYTE_VBUFFER_OFFSET:{ *:[i16] } ?:{ *:[v4i32] }:$srsrc, ?:{ *:[i32] }:$soffset, ?:{ *:[i32] }:$offset)
      GIR_BuildMI, /*InsnID*/0, /*Opcode*/GIMT_Encode2(AMDGPU::BUFFER_LOAD_UBYTE_VBUFFER_OFFSET),
      GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/0, // DstI[vdata]
      GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/0, // srsrc
      GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/1, // soffset
      GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/2, // offset
      GIR_AddImm8, /*InsnID*/0, /*Imm*/0,
      GIR_AddImm8, /*InsnID*/0, /*Imm*/0,
      GIR_MergeMemOperands, /*InsnID*/0, /*NumInsns*/1, /*MergeInsnID's*/0,
      GIR_ConstrainSelectedInstOperands, /*InsnID*/0,
      GIR_EraseFromParent, /*InsnID*/0,
      // GIR_Coverage, 5334,
      GIR_Done,
    // Label 1025: @66757
    GIM_Try, /*On fail goto*//*Label 1026*/ GIMT_Encode4(66840), // Rule ID 5339 //
      GIM_CheckFeatures, GIMT_Encode2(GIFBS_Has16BitInsts_HasUnrestrictedSOffset),
      GIM_CheckMemorySizeLessThanLLT, /*MI*/0, /*MMO*/0, /*OpIdx*/0,
      GIM_CheckMemorySizeEqualTo, /*MI*/0, /*MMO*/0, /*Size*/GIMT_Encode4(1),
      GIM_CheckMemoryAddressSpace, /*MI*/0, /*MMO*/0, /*NumAddrSpace*/3, /*AddrSpace*/1, /*AddrSpace*/4, /*AddrSpace*/6,
      GIM_CheckAtomicOrdering, /*MI*/0, /*Order*/(uint8_t)AtomicOrdering::NotAtomic,
      GIM_CheckRegBankForClass, /*MI*/0, /*Op*/0, /*RC*/GIMT_Encode2(AMDGPU::AV_32RegClassID),
      GIM_CheckPointerToAny, /*MI*/0, /*Op*/1, /*SizeInBits*/0,
      GIM_CheckComplexPattern, /*MI*/0, /*Op*/1, /*Renderer*/GIMT_Encode2(0), GIMT_Encode2(GICP_gi_mubuf_offset),
      // (ld:{ *:[i16] } (MUBUFOffset:{ *:[iPTR] } v4i32:{ *:[v4i32] }:$srsrc, i32:{ *:[i32] }:$soffset, i32:{ *:[i32] }:$offset))<<P:Predicate_unindexedload>><<P:Predicate_extload>><<P:Predicate_extloadi8>><<P:Predicate_extloadi8_global>>  =>  (BUFFER_LOAD_UBYTE_OFFSET:{ *:[i16] } ?:{ *:[v4i32] }:$srsrc, ?:{ *:[i32] }:$soffset, ?:{ *:[i32] }:$offset)
      GIR_BuildMI, /*InsnID*/0, /*Opcode*/GIMT_Encode2(AMDGPU::BUFFER_LOAD_UBYTE_OFFSET),
      GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/0, // DstI[vdata]
      GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/0, // srsrc
      GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/1, // soffset
      GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/2, // offset
      GIR_AddImm8, /*InsnID*/0, /*Imm*/0,
      GIR_AddImm8, /*InsnID*/0, /*Imm*/0,
      GIR_MergeMemOperands, /*InsnID*/0, /*NumInsns*/1, /*MergeInsnID's*/0,
      GIR_ConstrainSelectedInstOperands, /*InsnID*/0,
      GIR_EraseFromParent, /*InsnID*/0,
      // GIR_Coverage, 5339,
      GIR_Done,
    // Label 1026: @66840
    GIM_Try, /*On fail goto*//*Label 1027*/ GIMT_Encode4(66923), // Rule ID 5340 //
      GIM_CheckFeatures, GIMT_Encode2(GIFBS_Has16BitInsts),
      GIM_CheckMemorySizeLessThanLLT, /*MI*/0, /*MMO*/0, /*OpIdx*/0,
      GIM_CheckMemorySizeEqualTo, /*MI*/0, /*MMO*/0, /*Size*/GIMT_Encode4(1),
      GIM_CheckMemoryAddressSpace, /*MI*/0, /*MMO*/0, /*NumAddrSpace*/3, /*AddrSpace*/1, /*AddrSpace*/4, /*AddrSpace*/6,
      GIM_CheckAtomicOrdering, /*MI*/0, /*Order*/(uint8_t)AtomicOrdering::NotAtomic,
      GIM_CheckRegBankForClass, /*MI*/0, /*Op*/0, /*RC*/GIMT_Encode2(AMDGPU::AV_32RegClassID),
      GIM_CheckPointerToAny, /*MI*/0, /*Op*/1, /*SizeInBits*/0,
      GIM_CheckComplexPattern, /*MI*/0, /*Op*/1, /*Renderer*/GIMT_Encode2(0), GIMT_Encode2(GICP_gi_mubuf_offset),
      // (ld:{ *:[i16] } (MUBUFOffset:{ *:[iPTR] } v4i32:{ *:[v4i32] }:$srsrc, i32:{ *:[i32] }:$soffset, i32:{ *:[i32] }:$offset))<<P:Predicate_unindexedload>><<P:Predicate_extload>><<P:Predicate_extloadi8>><<P:Predicate_extloadi8_global>>  =>  (BUFFER_LOAD_UBYTE_VBUFFER_OFFSET:{ *:[i16] } ?:{ *:[v4i32] }:$srsrc, ?:{ *:[i32] }:$soffset, ?:{ *:[i32] }:$offset)
      GIR_BuildMI, /*InsnID*/0, /*Opcode*/GIMT_Encode2(AMDGPU::BUFFER_LOAD_UBYTE_VBUFFER_OFFSET),
      GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/0, // DstI[vdata]
      GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/0, // srsrc
      GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/1, // soffset
      GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/2, // offset
      GIR_AddImm8, /*InsnID*/0, /*Imm*/0,
      GIR_AddImm8, /*InsnID*/0, /*Imm*/0,
      GIR_MergeMemOperands, /*InsnID*/0, /*NumInsns*/1, /*MergeInsnID's*/0,
      GIR_ConstrainSelectedInstOperands, /*InsnID*/0,
      GIR_EraseFromParent, /*InsnID*/0,
      // GIR_Coverage, 5340,
      GIR_Done,
    // Label 1027: @66923
    GIM_Try, /*On fail goto*//*Label 1028*/ GIMT_Encode4(66995), // Rule ID 5343 //
      GIM_CheckFeatures, GIMT_Encode2(GIFBS_Has16BitInsts_HasUnrestrictedSOffset),
      GIM_CheckMemoryAddressSpace, /*MI*/0, /*MMO*/0, /*NumAddrSpace*/3, /*AddrSpace*/1, /*AddrSpace*/4, /*AddrSpace*/6,
      GIM_CheckAtomicOrdering, /*MI*/0, /*Order*/(uint8_t)AtomicOrdering::NotAtomic,
      GIM_CheckRegBankForClass, /*MI*/0, /*Op*/0, /*RC*/GIMT_Encode2(AMDGPU::AV_32RegClassID),
      GIM_CheckPointerToAny, /*MI*/0, /*Op*/1, /*SizeInBits*/0,
      GIM_CheckComplexPattern, /*MI*/0, /*Op*/1, /*Renderer*/GIMT_Encode2(0), GIMT_Encode2(GICP_gi_mubuf_offset),
      // (ld:{ *:[i16] } (MUBUFOffset:{ *:[iPTR] } v4i32:{ *:[v4i32] }:$srsrc, i32:{ *:[i32] }:$soffset, i32:{ *:[i32] }:$offset))<<P:Predicate_unindexedload>><<P:Predicate_load_global>>  =>  (BUFFER_LOAD_USHORT_OFFSET:{ *:[i16] } ?:{ *:[v4i32] }:$srsrc, ?:{ *:[i32] }:$soffset, ?:{ *:[i32] }:$offset)
      GIR_BuildMI, /*InsnID*/0, /*Opcode*/GIMT_Encode2(AMDGPU::BUFFER_LOAD_USHORT_OFFSET),
      GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/0, // DstI[vdata]
      GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/0, // srsrc
      GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/1, // soffset
      GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/2, // offset
      GIR_AddImm8, /*InsnID*/0, /*Imm*/0,
      GIR_AddImm8, /*InsnID*/0, /*Imm*/0,
      GIR_MergeMemOperands, /*InsnID*/0, /*NumInsns*/1, /*MergeInsnID's*/0,
      GIR_ConstrainSelectedInstOperands, /*InsnID*/0,
      GIR_EraseFromParent, /*InsnID*/0,
      // GIR_Coverage, 5343,
      GIR_Done,
    // Label 1028: @66995
    GIM_Try, /*On fail goto*//*Label 1029*/ GIMT_Encode4(67067), // Rule ID 5344 //
      GIM_CheckFeatures, GIMT_Encode2(GIFBS_Has16BitInsts),
      GIM_CheckMemoryAddressSpace, /*MI*/0, /*MMO*/0, /*NumAddrSpace*/3, /*AddrSpace*/1, /*AddrSpace*/4, /*AddrSpace*/6,
      GIM_CheckAtomicOrdering, /*MI*/0, /*Order*/(uint8_t)AtomicOrdering::NotAtomic,
      GIM_CheckRegBankForClass, /*MI*/0, /*Op*/0, /*RC*/GIMT_Encode2(AMDGPU::AV_32RegClassID),
      GIM_CheckPointerToAny, /*MI*/0, /*Op*/1, /*SizeInBits*/0,
      GIM_CheckComplexPattern, /*MI*/0, /*Op*/1, /*Renderer*/GIMT_Encode2(0), GIMT_Encode2(GICP_gi_mubuf_offset),
      // (ld:{ *:[i16] } (MUBUFOffset:{ *:[iPTR] } v4i32:{ *:[v4i32] }:$srsrc, i32:{ *:[i32] }:$soffset, i32:{ *:[i32] }:$offset))<<P:Predicate_unindexedload>><<P:Predicate_load_global>>  =>  (BUFFER_LOAD_USHORT_VBUFFER_OFFSET:{ *:[i16] } ?:{ *:[v4i32] }:$srsrc, ?:{ *:[i32] }:$soffset, ?:{ *:[i32] }:$offset)
      GIR_BuildMI, /*InsnID*/0, /*Opcode*/GIMT_Encode2(AMDGPU::BUFFER_LOAD_USHORT_VBUFFER_OFFSET),
      GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/0, // DstI[vdata]
      GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/0, // srsrc
      GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/1, // soffset
      GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/2, // offset
      GIR_AddImm8, /*InsnID*/0, /*Imm*/0,
      GIR_AddImm8, /*InsnID*/0, /*Imm*/0,
      GIR_MergeMemOperands, /*InsnID*/0, /*NumInsns*/1, /*MergeInsnID's*/0,
      GIR_ConstrainSelectedInstOperands, /*InsnID*/0,
      GIR_EraseFromParent, /*InsnID*/0,
      // GIR_Coverage, 5344,
      GIR_Done,
    // Label 1029: @67067
    GIM_Try, /*On fail goto*//*Label 1030*/ GIMT_Encode4(67136), // Rule ID 6607 //
      GIM_CheckFeatures, GIMT_Encode2(GIFBS_LDSRequiresM0Init),
      GIM_CheckMemorySizeEqualTo, /*MI*/0, /*MMO*/0, /*Size*/GIMT_Encode4(1),
      GIM_CheckMemoryAddressSpace, /*MI*/0, /*MMO*/0, /*NumAddrSpace*/1, /*AddrSpace*/3,
      GIM_CheckAtomicOrderingOrStrongerThan, /*MI*/0, /*Order*/(uint8_t)AtomicOrdering::Unordered,
      GIM_CheckRegBankForClass, /*MI*/0, /*Op*/0, /*RC*/GIMT_Encode2(AMDGPU::AV_32RegClassID),
      GIM_CheckPointerToAny, /*MI*/0, /*Op*/1, /*SizeInBits*/0,
      GIM_CheckComplexPattern, /*MI*/0, /*Op*/1, /*Renderer*/GIMT_Encode2(0), GIMT_Encode2(GICP_gi_ds_1addr_1offset),
      // (AMDGPUatomic_ld_glue:{ *:[i16] } (DS1Addr1Offset:{ *:[iPTR] } i32:{ *:[i32] }:$ptr, i32:{ *:[i32] }:$offset))<<P:Predicate_atomic_load_8_glue>><<P:Predicate_atomic_load_8_local_m0>>  =>  (DS_READ_U8:{ *:[i16] } ?:{ *:[i32] }:$ptr, offset:{ *:[i32] }:$offset, 0:{ *:[i1] })
      GIR_BuildMI, /*InsnID*/0, /*Opcode*/GIMT_Encode2(AMDGPU::DS_READ_U8),
      GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/0, // DstI[vdst]
      GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/0, // ptr
      GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/1, // offset
      GIR_AddImm8, /*InsnID*/0, /*Imm*/0,
      GIR_MergeMemOperands, /*InsnID*/0, /*NumInsns*/1, /*MergeInsnID's*/0,
      GIR_ConstrainSelectedInstOperands, /*InsnID*/0,
      GIR_EraseFromParent, /*InsnID*/0,
      // GIR_Coverage, 6607,
      GIR_Done,
    // Label 1030: @67136
    GIM_Try, /*On fail goto*//*Label 1031*/ GIMT_Encode4(67205), // Rule ID 6608 //
      GIM_CheckFeatures, GIMT_Encode2(GIFBS_NotLDSRequiresM0Init),
      GIM_CheckMemorySizeEqualTo, /*MI*/0, /*MMO*/0, /*Size*/GIMT_Encode4(1),
      GIM_CheckMemoryAddressSpace, /*MI*/0, /*MMO*/0, /*NumAddrSpace*/1, /*AddrSpace*/3,
      GIM_CheckAtomicOrderingOrStrongerThan, /*MI*/0, /*Order*/(uint8_t)AtomicOrdering::Unordered,
      GIM_CheckRegBankForClass, /*MI*/0, /*Op*/0, /*RC*/GIMT_Encode2(AMDGPU::AV_32RegClassID),
      GIM_CheckPointerToAny, /*MI*/0, /*Op*/1, /*SizeInBits*/0,
      GIM_CheckComplexPattern, /*MI*/0, /*Op*/1, /*Renderer*/GIMT_Encode2(0), GIMT_Encode2(GICP_gi_ds_1addr_1offset),
      // (atomic_load:{ *:[i16] } (DS1Addr1Offset:{ *:[iPTR] } i32:{ *:[i32] }:$ptr, i32:{ *:[i32] }:$offset))<<P:Predicate_atomic_load_8>><<P:Predicate_atomic_load_8_local>>  =>  (DS_READ_U8_gfx9:{ *:[i16] } ?:{ *:[i32] }:$ptr, offset:{ *:[i32] }:$offset, 0:{ *:[i1] })
      GIR_BuildMI, /*InsnID*/0, /*Opcode*/GIMT_Encode2(AMDGPU::DS_READ_U8_gfx9),
      GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/0, // DstI[vdst]
      GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/0, // ptr
      GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/1, // offset
      GIR_AddImm8, /*InsnID*/0, /*Imm*/0,
      GIR_MergeMemOperands, /*InsnID*/0, /*NumInsns*/1, /*MergeInsnID's*/0,
      GIR_ConstrainSelectedInstOperands, /*InsnID*/0,
      GIR_EraseFromParent, /*InsnID*/0,
      // GIR_Coverage, 6608,
      GIR_Done,
    // Label 1031: @67205
    GIM_Try, /*On fail goto*//*Label 1032*/ GIMT_Encode4(67274), // Rule ID 6611 //
      GIM_CheckFeatures, GIMT_Encode2(GIFBS_LDSRequiresM0Init),
      GIM_CheckMemorySizeEqualTo, /*MI*/0, /*MMO*/0, /*Size*/GIMT_Encode4(2),
      GIM_CheckMemoryAddressSpace, /*MI*/0, /*MMO*/0, /*NumAddrSpace*/1, /*AddrSpace*/3,
      GIM_CheckAtomicOrderingOrStrongerThan, /*MI*/0, /*Order*/(uint8_t)AtomicOrdering::Unordered,
      GIM_CheckRegBankForClass, /*MI*/0, /*Op*/0, /*RC*/GIMT_Encode2(AMDGPU::AV_32RegClassID),
      GIM_CheckPointerToAny, /*MI*/0, /*Op*/1, /*SizeInBits*/0,
      GIM_CheckComplexPattern, /*MI*/0, /*Op*/1, /*Renderer*/GIMT_Encode2(0), GIMT_Encode2(GICP_gi_ds_1addr_1offset),
      // (AMDGPUatomic_ld_glue:{ *:[i16] } (DS1Addr1Offset:{ *:[iPTR] } i32:{ *:[i32] }:$ptr, i32:{ *:[i32] }:$offset))<<P:Predicate_atomic_load_16_glue>><<P:Predicate_atomic_load_16_local_m0>>  =>  (DS_READ_U16:{ *:[i16] } ?:{ *:[i32] }:$ptr, offset:{ *:[i32] }:$offset, 0:{ *:[i1] })
      GIR_BuildMI, /*InsnID*/0, /*Opcode*/GIMT_Encode2(AMDGPU::DS_READ_U16),
      GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/0, // DstI[vdst]
      GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/0, // ptr
      GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/1, // offset
      GIR_AddImm8, /*InsnID*/0, /*Imm*/0,
      GIR_MergeMemOperands, /*InsnID*/0, /*NumInsns*/1, /*MergeInsnID's*/0,
      GIR_ConstrainSelectedInstOperands, /*InsnID*/0,
      GIR_EraseFromParent, /*InsnID*/0,
      // GIR_Coverage, 6611,
      GIR_Done,
    // Label 1032: @67274
    GIM_Try, /*On fail goto*//*Label 1033*/ GIMT_Encode4(67343), // Rule ID 6612 //
      GIM_CheckFeatures, GIMT_Encode2(GIFBS_NotLDSRequiresM0Init),
      GIM_CheckMemorySizeEqualTo, /*MI*/0, /*MMO*/0, /*Size*/GIMT_Encode4(2),
      GIM_CheckMemoryAddressSpace, /*MI*/0, /*MMO*/0, /*NumAddrSpace*/1, /*AddrSpace*/3,
      GIM_CheckAtomicOrderingOrStrongerThan, /*MI*/0, /*Order*/(uint8_t)AtomicOrdering::Unordered,
      GIM_CheckRegBankForClass, /*MI*/0, /*Op*/0, /*RC*/GIMT_Encode2(AMDGPU::AV_32RegClassID),
      GIM_CheckPointerToAny, /*MI*/0, /*Op*/1, /*SizeInBits*/0,
      GIM_CheckComplexPattern, /*MI*/0, /*Op*/1, /*Renderer*/GIMT_Encode2(0), GIMT_Encode2(GICP_gi_ds_1addr_1offset),
      // (atomic_load:{ *:[i16] } (DS1Addr1Offset:{ *:[iPTR] } i32:{ *:[i32] }:$ptr, i32:{ *:[i32] }:$offset))<<P:Predicate_atomic_load_16>><<P:Predicate_atomic_load_16_local>>  =>  (DS_READ_U16_gfx9:{ *:[i16] } ?:{ *:[i32] }:$ptr, offset:{ *:[i32] }:$offset, 0:{ *:[i1] })
      GIR_BuildMI, /*InsnID*/0, /*Opcode*/GIMT_Encode2(AMDGPU::DS_READ_U16_gfx9),
      GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/0, // DstI[vdst]
      GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/0, // ptr
      GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/1, // offset
      GIR_AddImm8, /*InsnID*/0, /*Imm*/0,
      GIR_MergeMemOperands, /*InsnID*/0, /*NumInsns*/1, /*MergeInsnID's*/0,
      GIR_ConstrainSelectedInstOperands, /*InsnID*/0,
      GIR_EraseFromParent, /*InsnID*/0,
      // GIR_Coverage, 6612,
      GIR_Done,
    // Label 1033: @67343
    GIM_Try, /*On fail goto*//*Label 1034*/ GIMT_Encode4(67416), // Rule ID 6575 //
      GIM_CheckFeatures, GIMT_Encode2(GIFBS_LDSRequiresM0Init),
      GIM_CheckMemorySizeLessThanLLT, /*MI*/0, /*MMO*/0, /*OpIdx*/0,
      GIM_CheckMemorySizeEqualTo, /*MI*/0, /*MMO*/0, /*Size*/GIMT_Encode4(1),
      GIM_CheckMemoryAddressSpace, /*MI*/0, /*MMO*/0, /*NumAddrSpace*/1, /*AddrSpace*/3,
      GIM_CheckAtomicOrdering, /*MI*/0, /*Order*/(uint8_t)AtomicOrdering::NotAtomic,
      GIM_CheckRegBankForClass, /*MI*/0, /*Op*/0, /*RC*/GIMT_Encode2(AMDGPU::AV_32RegClassID),
      GIM_CheckPointerToAny, /*MI*/0, /*Op*/1, /*SizeInBits*/0,
      GIM_CheckComplexPattern, /*MI*/0, /*Op*/1, /*Renderer*/GIMT_Encode2(0), GIMT_Encode2(GICP_gi_ds_1addr_1offset),
      // (AMDGPUld_glue:{ *:[i16] } (DS1Addr1Offset:{ *:[iPTR] } i32:{ *:[i32] }:$ptr, i32:{ *:[i32] }:$offset))<<P:Predicate_unindexedload_glue>><<P:Predicate_extload_glue>><<P:Predicate_extloadi8_glue>><<P:Predicate_extloadi8_local_m0>>  =>  (DS_READ_U8:{ *:[i16] } ?:{ *:[i32] }:$ptr, offset:{ *:[i32] }:$offset, 0:{ *:[i1] })
      GIR_BuildMI, /*InsnID*/0, /*Opcode*/GIMT_Encode2(AMDGPU::DS_READ_U8),
      GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/0, // DstI[vdst]
      GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/0, // ptr
      GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/1, // offset
      GIR_AddImm8, /*InsnID*/0, /*Imm*/0,
      GIR_MergeMemOperands, /*InsnID*/0, /*NumInsns*/1, /*MergeInsnID's*/0,
      GIR_ConstrainSelectedInstOperands, /*InsnID*/0,
      GIR_EraseFromParent, /*InsnID*/0,
      // GIR_Coverage, 6575,
      GIR_Done,
    // Label 1034: @67416
    GIM_Try, /*On fail goto*//*Label 1035*/ GIMT_Encode4(67489), // Rule ID 6576 //
      GIM_CheckFeatures, GIMT_Encode2(GIFBS_NotLDSRequiresM0Init),
      GIM_CheckMemorySizeLessThanLLT, /*MI*/0, /*MMO*/0, /*OpIdx*/0,
      GIM_CheckMemorySizeEqualTo, /*MI*/0, /*MMO*/0, /*Size*/GIMT_Encode4(1),
      GIM_CheckMemoryAddressSpace, /*MI*/0, /*MMO*/0, /*NumAddrSpace*/1, /*AddrSpace*/3,
      GIM_CheckAtomicOrdering, /*MI*/0, /*Order*/(uint8_t)AtomicOrdering::NotAtomic,
      GIM_CheckRegBankForClass, /*MI*/0, /*Op*/0, /*RC*/GIMT_Encode2(AMDGPU::AV_32RegClassID),
      GIM_CheckPointerToAny, /*MI*/0, /*Op*/1, /*SizeInBits*/0,
      GIM_CheckComplexPattern, /*MI*/0, /*Op*/1, /*Renderer*/GIMT_Encode2(0), GIMT_Encode2(GICP_gi_ds_1addr_1offset),
      // (ld:{ *:[i16] } (DS1Addr1Offset:{ *:[iPTR] } i32:{ *:[i32] }:$ptr, i32:{ *:[i32] }:$offset))<<P:Predicate_unindexedload>><<P:Predicate_extload>><<P:Predicate_extloadi8>><<P:Predicate_extloadi8_local>>  =>  (DS_READ_U8_gfx9:{ *:[i16] } ?:{ *:[i32] }:$ptr, offset:{ *:[i32] }:$offset, 0:{ *:[i1] })
      GIR_BuildMI, /*InsnID*/0, /*Opcode*/GIMT_Encode2(AMDGPU::DS_READ_U8_gfx9),
      GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/0, // DstI[vdst]
      GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/0, // ptr
      GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/1, // offset
      GIR_AddImm8, /*InsnID*/0, /*Imm*/0,
      GIR_MergeMemOperands, /*InsnID*/0, /*NumInsns*/1, /*MergeInsnID's*/0,
      GIR_ConstrainSelectedInstOperands, /*InsnID*/0,
      GIR_EraseFromParent, /*InsnID*/0,
      // GIR_Coverage, 6576,
      GIR_Done,
    // Label 1035: @67489
    GIM_Try, /*On fail goto*//*Label 1036*/ GIMT_Encode4(67555), // Rule ID 6587 //
      GIM_CheckFeatures, GIMT_Encode2(GIFBS_LDSRequiresM0Init),
      GIM_CheckMemorySizeEqualToLLT, /*MI*/0, /*MMO*/0, /*OpIdx*/0,
      GIM_CheckMemoryAddressSpace, /*MI*/0, /*MMO*/0, /*NumAddrSpace*/1, /*AddrSpace*/3,
      GIM_CheckAtomicOrdering, /*MI*/0, /*Order*/(uint8_t)AtomicOrdering::NotAtomic,
      GIM_CheckRegBankForClass, /*MI*/0, /*Op*/0, /*RC*/GIMT_Encode2(AMDGPU::AV_32RegClassID),
      GIM_CheckPointerToAny, /*MI*/0, /*Op*/1, /*SizeInBits*/0,
      GIM_CheckComplexPattern, /*MI*/0, /*Op*/1, /*Renderer*/GIMT_Encode2(0), GIMT_Encode2(GICP_gi_ds_1addr_1offset),
      // (AMDGPUld_glue:{ *:[i16] } (DS1Addr1Offset:{ *:[iPTR] } i32:{ *:[i32] }:$ptr, i32:{ *:[i32] }:$offset))<<P:Predicate_unindexedload_glue>><<P:Predicate_load_glue>><<P:Predicate_load_local_m0>>  =>  (DS_READ_U16:{ *:[i16] } ?:{ *:[i32] }:$ptr, offset:{ *:[i32] }:$offset, 0:{ *:[i1] })
      GIR_BuildMI, /*InsnID*/0, /*Opcode*/GIMT_Encode2(AMDGPU::DS_READ_U16),
      GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/0, // DstI[vdst]
      GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/0, // ptr
      GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/1, // offset
      GIR_AddImm8, /*InsnID*/0, /*Imm*/0,
      GIR_MergeMemOperands, /*InsnID*/0, /*NumInsns*/1, /*MergeInsnID's*/0,
      GIR_ConstrainSelectedInstOperands, /*InsnID*/0,
      GIR_EraseFromParent, /*InsnID*/0,
      // GIR_Coverage, 6587,
      GIR_Done,
    // Label 1036: @67555
    GIM_Try, /*On fail goto*//*Label 1037*/ GIMT_Encode4(67617), // Rule ID 6588 //
      GIM_CheckFeatures, GIMT_Encode2(GIFBS_NotLDSRequiresM0Init),
      GIM_CheckMemoryAddressSpace, /*MI*/0, /*MMO*/0, /*NumAddrSpace*/1, /*AddrSpace*/3,
      GIM_CheckAtomicOrdering, /*MI*/0, /*Order*/(uint8_t)AtomicOrdering::NotAtomic,
      GIM_CheckRegBankForClass, /*MI*/0, /*Op*/0, /*RC*/GIMT_Encode2(AMDGPU::AV_32RegClassID),
      GIM_CheckPointerToAny, /*MI*/0, /*Op*/1, /*SizeInBits*/0,
      GIM_CheckComplexPattern, /*MI*/0, /*Op*/1, /*Renderer*/GIMT_Encode2(0), GIMT_Encode2(GICP_gi_ds_1addr_1offset),
      // (ld:{ *:[i16] } (DS1Addr1Offset:{ *:[iPTR] } i32:{ *:[i32] }:$ptr, i32:{ *:[i32] }:$offset))<<P:Predicate_unindexedload>><<P:Predicate_load_local>>  =>  (DS_READ_U16_gfx9:{ *:[i16] } ?:{ *:[i32] }:$ptr, offset:{ *:[i32] }:$offset, 0:{ *:[i1] })
      GIR_BuildMI, /*InsnID*/0, /*Opcode*/GIMT_Encode2(AMDGPU::DS_READ_U16_gfx9),
      GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/0, // DstI[vdst]
      GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/0, // ptr
      GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/1, // offset
      GIR_AddImm8, /*InsnID*/0, /*Imm*/0,
      GIR_MergeMemOperands, /*InsnID*/0, /*NumInsns*/1, /*MergeInsnID's*/0,
      GIR_ConstrainSelectedInstOperands, /*InsnID*/0,
      GIR_EraseFromParent, /*InsnID*/0,
      // GIR_Coverage, 6588,
      GIR_Done,
    // Label 1037: @67617
    GIM_Try, /*On fail goto*//*Label 1038*/ GIMT_Encode4(67693), // Rule ID 2969 //
      GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasFlatGlobalInsts),
      GIM_CheckMemorySizeEqualTo, /*MI*/0, /*MMO*/0, /*Size*/GIMT_Encode4(1),
      GIM_CheckMemoryAddressSpace, /*MI*/0, /*MMO*/0, /*NumAddrSpace*/3, /*AddrSpace*/1, /*AddrSpace*/4, /*AddrSpace*/6,
      GIM_CheckAtomicOrderingOrStrongerThan, /*MI*/0, /*Order*/(uint8_t)AtomicOrdering::Unordered,
      GIM_CheckRegBankForClass, /*MI*/0, /*Op*/0, /*RC*/GIMT_Encode2(AMDGPU::AV_32RegClassID),
      GIM_CheckPointerToAny, /*MI*/0, /*Op*/1, /*SizeInBits*/0,
      GIM_CheckComplexPattern, /*MI*/0, /*Op*/1, /*Renderer*/GIMT_Encode2(0), GIMT_Encode2(GICP_gi_global_saddr),
      // (atomic_load:{ *:[i16] } (GlobalSAddr:{ *:[iPTR] } SReg_64:{ *:[i64] }:$saddr, VGPR_32:{ *:[i32] }:$voffset, i32:{ *:[i32] }:$offset))<<P:Predicate_atomic_load_8>><<P:Predicate_atomic_load_8_global>>  =>  (GLOBAL_LOAD_UBYTE_SADDR:{ *:[i16] } ?:{ *:[i64] }:$saddr, ?:{ *:[i32] }:$voffset, ?:{ *:[i32] }:$offset, 0:{ *:[i32] })
      GIR_BuildMI, /*InsnID*/0, /*Opcode*/GIMT_Encode2(AMDGPU::GLOBAL_LOAD_UBYTE_SADDR),
      GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/0, // DstI[vdst]
      GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/0, // saddr
      GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/1, // voffset
      GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/2, // offset
      GIR_AddImm8, /*InsnID*/0, /*Imm*/0,
      GIR_MergeMemOperands, /*InsnID*/0, /*NumInsns*/1, /*MergeInsnID's*/0,
      GIR_ConstrainSelectedInstOperands, /*InsnID*/0,
      GIR_EraseFromParent, /*InsnID*/0,
      // GIR_Coverage, 2969,
      GIR_Done,
    // Label 1038: @67693
    GIM_Try, /*On fail goto*//*Label 1039*/ GIMT_Encode4(67769), // Rule ID 2973 //
      GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasFlatGlobalInsts),
      GIM_CheckMemorySizeEqualTo, /*MI*/0, /*MMO*/0, /*Size*/GIMT_Encode4(2),
      GIM_CheckMemoryAddressSpace, /*MI*/0, /*MMO*/0, /*NumAddrSpace*/3, /*AddrSpace*/1, /*AddrSpace*/4, /*AddrSpace*/6,
      GIM_CheckAtomicOrderingOrStrongerThan, /*MI*/0, /*Order*/(uint8_t)AtomicOrdering::Unordered,
      GIM_CheckRegBankForClass, /*MI*/0, /*Op*/0, /*RC*/GIMT_Encode2(AMDGPU::AV_32RegClassID),
      GIM_CheckPointerToAny, /*MI*/0, /*Op*/1, /*SizeInBits*/0,
      GIM_CheckComplexPattern, /*MI*/0, /*Op*/1, /*Renderer*/GIMT_Encode2(0), GIMT_Encode2(GICP_gi_global_saddr),
      // (atomic_load:{ *:[i16] } (GlobalSAddr:{ *:[iPTR] } SReg_64:{ *:[i64] }:$saddr, VGPR_32:{ *:[i32] }:$voffset, i32:{ *:[i32] }:$offset))<<P:Predicate_atomic_load_16>><<P:Predicate_atomic_load_16_global>>  =>  (GLOBAL_LOAD_USHORT_SADDR:{ *:[i16] } ?:{ *:[i64] }:$saddr, ?:{ *:[i32] }:$voffset, ?:{ *:[i32] }:$offset, 0:{ *:[i32] })
      GIR_BuildMI, /*InsnID*/0, /*Opcode*/GIMT_Encode2(AMDGPU::GLOBAL_LOAD_USHORT_SADDR),
      GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/0, // DstI[vdst]
      GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/0, // saddr
      GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/1, // voffset
      GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/2, // offset
      GIR_AddImm8, /*InsnID*/0, /*Imm*/0,
      GIR_MergeMemOperands, /*InsnID*/0, /*NumInsns*/1, /*MergeInsnID's*/0,
      GIR_ConstrainSelectedInstOperands, /*InsnID*/0,
      GIR_EraseFromParent, /*InsnID*/0,
      // GIR_Coverage, 2973,
      GIR_Done,
    // Label 1039: @67769
    GIM_Try, /*On fail goto*//*Label 1040*/ GIMT_Encode4(67849), // Rule ID 2981 //
      GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasFlatGlobalInsts),
      GIM_CheckMemorySizeLessThanLLT, /*MI*/0, /*MMO*/0, /*OpIdx*/0,
      GIM_CheckMemorySizeEqualTo, /*MI*/0, /*MMO*/0, /*Size*/GIMT_Encode4(1),
      GIM_CheckMemoryAddressSpace, /*MI*/0, /*MMO*/0, /*NumAddrSpace*/3, /*AddrSpace*/1, /*AddrSpace*/4, /*AddrSpace*/6,
      GIM_CheckAtomicOrdering, /*MI*/0, /*Order*/(uint8_t)AtomicOrdering::NotAtomic,
      GIM_CheckRegBankForClass, /*MI*/0, /*Op*/0, /*RC*/GIMT_Encode2(AMDGPU::AV_32RegClassID),
      GIM_CheckPointerToAny, /*MI*/0, /*Op*/1, /*SizeInBits*/0,
      GIM_CheckComplexPattern, /*MI*/0, /*Op*/1, /*Renderer*/GIMT_Encode2(0), GIMT_Encode2(GICP_gi_global_saddr),
      // (ld:{ *:[i16] } (GlobalSAddr:{ *:[iPTR] } SReg_64:{ *:[i64] }:$saddr, VGPR_32:{ *:[i32] }:$voffset, i32:{ *:[i32] }:$offset))<<P:Predicate_unindexedload>><<P:Predicate_extload>><<P:Predicate_extloadi8>><<P:Predicate_extloadi8_global>>  =>  (GLOBAL_LOAD_UBYTE_SADDR:{ *:[i16] } ?:{ *:[i64] }:$saddr, ?:{ *:[i32] }:$voffset, ?:{ *:[i32] }:$offset, 0:{ *:[i32] })
      GIR_BuildMI, /*InsnID*/0, /*Opcode*/GIMT_Encode2(AMDGPU::GLOBAL_LOAD_UBYTE_SADDR),
      GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/0, // DstI[vdst]
      GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/0, // saddr
      GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/1, // voffset
      GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/2, // offset
      GIR_AddImm8, /*InsnID*/0, /*Imm*/0,
      GIR_MergeMemOperands, /*InsnID*/0, /*NumInsns*/1, /*MergeInsnID's*/0,
      GIR_ConstrainSelectedInstOperands, /*InsnID*/0,
      GIR_EraseFromParent, /*InsnID*/0,
      // GIR_Coverage, 2981,
      GIR_Done,
    // Label 1040: @67849
    GIM_Try, /*On fail goto*//*Label 1041*/ GIMT_Encode4(67918), // Rule ID 2993 //
      GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasFlatGlobalInsts),
      GIM_CheckMemoryAddressSpace, /*MI*/0, /*MMO*/0, /*NumAddrSpace*/3, /*AddrSpace*/1, /*AddrSpace*/4, /*AddrSpace*/6,
      GIM_CheckAtomicOrdering, /*MI*/0, /*Order*/(uint8_t)AtomicOrdering::NotAtomic,
      GIM_CheckRegBankForClass, /*MI*/0, /*Op*/0, /*RC*/GIMT_Encode2(AMDGPU::AV_32RegClassID),
      GIM_CheckPointerToAny, /*MI*/0, /*Op*/1, /*SizeInBits*/0,
      GIM_CheckComplexPattern, /*MI*/0, /*Op*/1, /*Renderer*/GIMT_Encode2(0), GIMT_Encode2(GICP_gi_global_saddr),
      // (ld:{ *:[i16] } (GlobalSAddr:{ *:[iPTR] } SReg_64:{ *:[i64] }:$saddr, VGPR_32:{ *:[i32] }:$voffset, i32:{ *:[i32] }:$offset))<<P:Predicate_unindexedload>><<P:Predicate_load_global>>  =>  (GLOBAL_LOAD_USHORT_SADDR:{ *:[i16] } ?:{ *:[i64] }:$saddr, ?:{ *:[i32] }:$voffset, ?:{ *:[i32] }:$offset, 0:{ *:[i32] })
      GIR_BuildMI, /*InsnID*/0, /*Opcode*/GIMT_Encode2(AMDGPU::GLOBAL_LOAD_USHORT_SADDR),
      GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/0, // DstI[vdst]
      GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/0, // saddr
      GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/1, // voffset
      GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/2, // offset
      GIR_AddImm8, /*InsnID*/0, /*Imm*/0,
      GIR_MergeMemOperands, /*InsnID*/0, /*NumInsns*/1, /*MergeInsnID's*/0,
      GIR_ConstrainSelectedInstOperands, /*InsnID*/0,
      GIR_EraseFromParent, /*InsnID*/0,
      // GIR_Coverage, 2993,
      GIR_Done,
    // Label 1041: @67918
    GIM_Try, /*On fail goto*//*Label 1042*/ GIMT_Encode4(67989), // Rule ID 2968 //
      GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasFlatGlobalInsts),
      GIM_CheckMemorySizeEqualTo, /*MI*/0, /*MMO*/0, /*Size*/GIMT_Encode4(1),
      GIM_CheckMemoryAddressSpace, /*MI*/0, /*MMO*/0, /*NumAddrSpace*/3, /*AddrSpace*/1, /*AddrSpace*/4, /*AddrSpace*/6,
      GIM_CheckAtomicOrderingOrStrongerThan, /*MI*/0, /*Order*/(uint8_t)AtomicOrdering::Unordered,
      GIM_CheckRegBankForClass, /*MI*/0, /*Op*/0, /*RC*/GIMT_Encode2(AMDGPU::AV_32RegClassID),
      GIM_CheckPointerToAny, /*MI*/0, /*Op*/1, /*SizeInBits*/0,
      GIM_CheckComplexPattern, /*MI*/0, /*Op*/1, /*Renderer*/GIMT_Encode2(0), GIMT_Encode2(GICP_gi_global_offset),
      // (atomic_load:{ *:[i16] } (GlobalOffset:{ *:[iPTR] } VReg_64:{ *:[i64] }:$vaddr, i32:{ *:[i32] }:$offset))<<P:Predicate_atomic_load_8>><<P:Predicate_atomic_load_8_global>>  =>  (GLOBAL_LOAD_UBYTE:{ *:[i16] } ?:{ *:[i64] }:$vaddr, ?:{ *:[i32] }:$offset)
      GIR_BuildMI, /*InsnID*/0, /*Opcode*/GIMT_Encode2(AMDGPU::GLOBAL_LOAD_UBYTE),
      GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/0, // DstI[vdst]
      GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/0, // vaddr
      GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/1, // offset
      GIR_AddImm8, /*InsnID*/0, /*Imm*/0,
      GIR_MergeMemOperands, /*InsnID*/0, /*NumInsns*/1, /*MergeInsnID's*/0,
      GIR_ConstrainSelectedInstOperands, /*InsnID*/0,
      GIR_EraseFromParent, /*InsnID*/0,
      // GIR_Coverage, 2968,
      GIR_Done,
    // Label 1042: @67989
    GIM_Try, /*On fail goto*//*Label 1043*/ GIMT_Encode4(68060), // Rule ID 2972 //
      GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasFlatGlobalInsts),
      GIM_CheckMemorySizeEqualTo, /*MI*/0, /*MMO*/0, /*Size*/GIMT_Encode4(2),
      GIM_CheckMemoryAddressSpace, /*MI*/0, /*MMO*/0, /*NumAddrSpace*/3, /*AddrSpace*/1, /*AddrSpace*/4, /*AddrSpace*/6,
      GIM_CheckAtomicOrderingOrStrongerThan, /*MI*/0, /*Order*/(uint8_t)AtomicOrdering::Unordered,
      GIM_CheckRegBankForClass, /*MI*/0, /*Op*/0, /*RC*/GIMT_Encode2(AMDGPU::AV_32RegClassID),
      GIM_CheckPointerToAny, /*MI*/0, /*Op*/1, /*SizeInBits*/0,
      GIM_CheckComplexPattern, /*MI*/0, /*Op*/1, /*Renderer*/GIMT_Encode2(0), GIMT_Encode2(GICP_gi_global_offset),
      // (atomic_load:{ *:[i16] } (GlobalOffset:{ *:[iPTR] } VReg_64:{ *:[i64] }:$vaddr, i32:{ *:[i32] }:$offset))<<P:Predicate_atomic_load_16>><<P:Predicate_atomic_load_16_global>>  =>  (GLOBAL_LOAD_USHORT:{ *:[i16] } ?:{ *:[i64] }:$vaddr, ?:{ *:[i32] }:$offset)
      GIR_BuildMI, /*InsnID*/0, /*Opcode*/GIMT_Encode2(AMDGPU::GLOBAL_LOAD_USHORT),
      GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/0, // DstI[vdst]
      GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/0, // vaddr
      GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/1, // offset
      GIR_AddImm8, /*InsnID*/0, /*Imm*/0,
      GIR_MergeMemOperands, /*InsnID*/0, /*NumInsns*/1, /*MergeInsnID's*/0,
      GIR_ConstrainSelectedInstOperands, /*InsnID*/0,
      GIR_EraseFromParent, /*InsnID*/0,
      // GIR_Coverage, 2972,
      GIR_Done,
    // Label 1043: @68060
    GIM_Try, /*On fail goto*//*Label 1044*/ GIMT_Encode4(68135), // Rule ID 2980 //
      GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasFlatGlobalInsts),
      GIM_CheckMemorySizeLessThanLLT, /*MI*/0, /*MMO*/0, /*OpIdx*/0,
      GIM_CheckMemorySizeEqualTo, /*MI*/0, /*MMO*/0, /*Size*/GIMT_Encode4(1),
      GIM_CheckMemoryAddressSpace, /*MI*/0, /*MMO*/0, /*NumAddrSpace*/3, /*AddrSpace*/1, /*AddrSpace*/4, /*AddrSpace*/6,
      GIM_CheckAtomicOrdering, /*MI*/0, /*Order*/(uint8_t)AtomicOrdering::NotAtomic,
      GIM_CheckRegBankForClass, /*MI*/0, /*Op*/0, /*RC*/GIMT_Encode2(AMDGPU::AV_32RegClassID),
      GIM_CheckPointerToAny, /*MI*/0, /*Op*/1, /*SizeInBits*/0,
      GIM_CheckComplexPattern, /*MI*/0, /*Op*/1, /*Renderer*/GIMT_Encode2(0), GIMT_Encode2(GICP_gi_global_offset),
      // (ld:{ *:[i16] } (GlobalOffset:{ *:[iPTR] } VReg_64:{ *:[i64] }:$vaddr, i32:{ *:[i32] }:$offset))<<P:Predicate_unindexedload>><<P:Predicate_extload>><<P:Predicate_extloadi8>><<P:Predicate_extloadi8_global>>  =>  (GLOBAL_LOAD_UBYTE:{ *:[i16] } ?:{ *:[i64] }:$vaddr, ?:{ *:[i32] }:$offset)
      GIR_BuildMI, /*InsnID*/0, /*Opcode*/GIMT_Encode2(AMDGPU::GLOBAL_LOAD_UBYTE),
      GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/0, // DstI[vdst]
      GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/0, // vaddr
      GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/1, // offset
      GIR_AddImm8, /*InsnID*/0, /*Imm*/0,
      GIR_MergeMemOperands, /*InsnID*/0, /*NumInsns*/1, /*MergeInsnID's*/0,
      GIR_ConstrainSelectedInstOperands, /*InsnID*/0,
      GIR_EraseFromParent, /*InsnID*/0,
      // GIR_Coverage, 2980,
      GIR_Done,
    // Label 1044: @68135
    GIM_Try, /*On fail goto*//*Label 1045*/ GIMT_Encode4(68199), // Rule ID 2992 //
      GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasFlatGlobalInsts),
      GIM_CheckMemoryAddressSpace, /*MI*/0, /*MMO*/0, /*NumAddrSpace*/3, /*AddrSpace*/1, /*AddrSpace*/4, /*AddrSpace*/6,
      GIM_CheckAtomicOrdering, /*MI*/0, /*Order*/(uint8_t)AtomicOrdering::NotAtomic,
      GIM_CheckRegBankForClass, /*MI*/0, /*Op*/0, /*RC*/GIMT_Encode2(AMDGPU::AV_32RegClassID),
      GIM_CheckPointerToAny, /*MI*/0, /*Op*/1, /*SizeInBits*/0,
      GIM_CheckComplexPattern, /*MI*/0, /*Op*/1, /*Renderer*/GIMT_Encode2(0), GIMT_Encode2(GICP_gi_global_offset),
      // (ld:{ *:[i16] } (GlobalOffset:{ *:[iPTR] } VReg_64:{ *:[i64] }:$vaddr, i32:{ *:[i32] }:$offset))<<P:Predicate_unindexedload>><<P:Predicate_load_global>>  =>  (GLOBAL_LOAD_USHORT:{ *:[i16] } ?:{ *:[i64] }:$vaddr, ?:{ *:[i32] }:$offset)
      GIR_BuildMI, /*InsnID*/0, /*Opcode*/GIMT_Encode2(AMDGPU::GLOBAL_LOAD_USHORT),
      GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/0, // DstI[vdst]
      GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/0, // vaddr
      GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/1, // offset
      GIR_AddImm8, /*InsnID*/0, /*Imm*/0,
      GIR_MergeMemOperands, /*InsnID*/0, /*NumInsns*/1, /*MergeInsnID's*/0,
      GIR_ConstrainSelectedInstOperands, /*InsnID*/0,
      GIR_EraseFromParent, /*InsnID*/0,
      // GIR_Coverage, 2992,
      GIR_Done,
    // Label 1045: @68199
    GIM_Try, /*On fail goto*//*Label 1046*/ GIMT_Encode4(68271), // Rule ID 2752 //
      GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasFlatAddressSpace),
      GIM_CheckMemorySizeEqualTo, /*MI*/0, /*MMO*/0, /*Size*/GIMT_Encode4(1),
      GIM_CheckMemoryAddressSpace, /*MI*/0, /*MMO*/0, /*NumAddrSpace*/4, /*AddrSpace*/0, /*AddrSpace*/1, /*AddrSpace*/4, /*AddrSpace*/6,
      GIM_CheckAtomicOrderingOrStrongerThan, /*MI*/0, /*Order*/(uint8_t)AtomicOrdering::Unordered,
      GIM_CheckRegBankForClass, /*MI*/0, /*Op*/0, /*RC*/GIMT_Encode2(AMDGPU::AV_32RegClassID),
      GIM_CheckPointerToAny, /*MI*/0, /*Op*/1, /*SizeInBits*/0,
      GIM_CheckComplexPattern, /*MI*/0, /*Op*/1, /*Renderer*/GIMT_Encode2(0), GIMT_Encode2(GICP_gi_flat_offset),
      // (atomic_load:{ *:[i16] } (FlatOffset:{ *:[iPTR] } i64:{ *:[i64] }:$vaddr, i32:{ *:[i32] }:$offset))<<P:Predicate_atomic_load_8>><<P:Predicate_atomic_load_8_flat>>  =>  (FLAT_LOAD_UBYTE:{ *:[i16] } ?:{ *:[i64] }:$vaddr, ?:{ *:[i32] }:$offset)
      GIR_BuildMI, /*InsnID*/0, /*Opcode*/GIMT_Encode2(AMDGPU::FLAT_LOAD_UBYTE),
      GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/0, // DstI[vdst]
      GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/0, // vaddr
      GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/1, // offset
      GIR_AddImm8, /*InsnID*/0, /*Imm*/0,
      GIR_MergeMemOperands, /*InsnID*/0, /*NumInsns*/1, /*MergeInsnID's*/0,
      GIR_ConstrainSelectedInstOperands, /*InsnID*/0,
      GIR_EraseFromParent, /*InsnID*/0,
      // GIR_Coverage, 2752,
      GIR_Done,
    // Label 1046: @68271
    GIM_Try, /*On fail goto*//*Label 1047*/ GIMT_Encode4(68343), // Rule ID 2754 //
      GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasFlatAddressSpace),
      GIM_CheckMemorySizeEqualTo, /*MI*/0, /*MMO*/0, /*Size*/GIMT_Encode4(2),
      GIM_CheckMemoryAddressSpace, /*MI*/0, /*MMO*/0, /*NumAddrSpace*/4, /*AddrSpace*/0, /*AddrSpace*/1, /*AddrSpace*/4, /*AddrSpace*/6,
      GIM_CheckAtomicOrderingOrStrongerThan, /*MI*/0, /*Order*/(uint8_t)AtomicOrdering::Unordered,
      GIM_CheckRegBankForClass, /*MI*/0, /*Op*/0, /*RC*/GIMT_Encode2(AMDGPU::AV_32RegClassID),
      GIM_CheckPointerToAny, /*MI*/0, /*Op*/1, /*SizeInBits*/0,
      GIM_CheckComplexPattern, /*MI*/0, /*Op*/1, /*Renderer*/GIMT_Encode2(0), GIMT_Encode2(GICP_gi_flat_offset),
      // (atomic_load:{ *:[i16] } (FlatOffset:{ *:[iPTR] } i64:{ *:[i64] }:$vaddr, i32:{ *:[i32] }:$offset))<<P:Predicate_atomic_load_16>><<P:Predicate_atomic_load_16_flat>>  =>  (FLAT_LOAD_USHORT:{ *:[i16] } ?:{ *:[i64] }:$vaddr, ?:{ *:[i32] }:$offset)
      GIR_BuildMI, /*InsnID*/0, /*Opcode*/GIMT_Encode2(AMDGPU::FLAT_LOAD_USHORT),
      GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/0, // DstI[vdst]
      GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/0, // vaddr
      GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/1, // offset
      GIR_AddImm8, /*InsnID*/0, /*Imm*/0,
      GIR_MergeMemOperands, /*InsnID*/0, /*NumInsns*/1, /*MergeInsnID's*/0,
      GIR_ConstrainSelectedInstOperands, /*InsnID*/0,
      GIR_EraseFromParent, /*InsnID*/0,
      // GIR_Coverage, 2754,
      GIR_Done,
    // Label 1047: @68343
    GIM_Try, /*On fail goto*//*Label 1048*/ GIMT_Encode4(68419), // Rule ID 2758 //
      GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasFlatAddressSpace),
      GIM_CheckMemorySizeLessThanLLT, /*MI*/0, /*MMO*/0, /*OpIdx*/0,
      GIM_CheckMemorySizeEqualTo, /*MI*/0, /*MMO*/0, /*Size*/GIMT_Encode4(1),
      GIM_CheckMemoryAddressSpace, /*MI*/0, /*MMO*/0, /*NumAddrSpace*/4, /*AddrSpace*/0, /*AddrSpace*/1, /*AddrSpace*/4, /*AddrSpace*/6,
      GIM_CheckAtomicOrdering, /*MI*/0, /*Order*/(uint8_t)AtomicOrdering::NotAtomic,
      GIM_CheckRegBankForClass, /*MI*/0, /*Op*/0, /*RC*/GIMT_Encode2(AMDGPU::AV_32RegClassID),
      GIM_CheckPointerToAny, /*MI*/0, /*Op*/1, /*SizeInBits*/0,
      GIM_CheckComplexPattern, /*MI*/0, /*Op*/1, /*Renderer*/GIMT_Encode2(0), GIMT_Encode2(GICP_gi_flat_offset),
      // (ld:{ *:[i16] } (FlatOffset:{ *:[iPTR] } i64:{ *:[i64] }:$vaddr, i32:{ *:[i32] }:$offset))<<P:Predicate_unindexedload>><<P:Predicate_extload>><<P:Predicate_extloadi8>><<P:Predicate_extloadi8_flat>>  =>  (FLAT_LOAD_UBYTE:{ *:[i16] } ?:{ *:[i64] }:$vaddr, ?:{ *:[i32] }:$offset)
      GIR_BuildMI, /*InsnID*/0, /*Opcode*/GIMT_Encode2(AMDGPU::FLAT_LOAD_UBYTE),
      GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/0, // DstI[vdst]
      GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/0, // vaddr
      GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/1, // offset
      GIR_AddImm8, /*InsnID*/0, /*Imm*/0,
      GIR_MergeMemOperands, /*InsnID*/0, /*NumInsns*/1, /*MergeInsnID's*/0,
      GIR_ConstrainSelectedInstOperands, /*InsnID*/0,
      GIR_EraseFromParent, /*InsnID*/0,
      // GIR_Coverage, 2758,
      GIR_Done,
    // Label 1048: @68419
    GIM_Try, /*On fail goto*//*Label 1049*/ GIMT_Encode4(68484), // Rule ID 2763 //
      GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasFlatAddressSpace),
      GIM_CheckMemoryAddressSpace, /*MI*/0, /*MMO*/0, /*NumAddrSpace*/4, /*AddrSpace*/0, /*AddrSpace*/1, /*AddrSpace*/4, /*AddrSpace*/6,
      GIM_CheckAtomicOrdering, /*MI*/0, /*Order*/(uint8_t)AtomicOrdering::NotAtomic,
      GIM_CheckRegBankForClass, /*MI*/0, /*Op*/0, /*RC*/GIMT_Encode2(AMDGPU::AV_32RegClassID),
      GIM_CheckPointerToAny, /*MI*/0, /*Op*/1, /*SizeInBits*/0,
      GIM_CheckComplexPattern, /*MI*/0, /*Op*/1, /*Renderer*/GIMT_Encode2(0), GIMT_Encode2(GICP_gi_flat_offset),
      // (ld:{ *:[i16] } (FlatOffset:{ *:[iPTR] } i64:{ *:[i64] }:$vaddr, i32:{ *:[i32] }:$offset))<<P:Predicate_unindexedload>><<P:Predicate_load_flat>>  =>  (FLAT_LOAD_USHORT:{ *:[i16] } ?:{ *:[i64] }:$vaddr, ?:{ *:[i32] }:$offset)
      GIR_BuildMI, /*InsnID*/0, /*Opcode*/GIMT_Encode2(AMDGPU::FLAT_LOAD_USHORT),
      GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/0, // DstI[vdst]
      GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/0, // vaddr
      GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/1, // offset
      GIR_AddImm8, /*InsnID*/0, /*Imm*/0,
      GIR_MergeMemOperands, /*InsnID*/0, /*NumInsns*/1, /*MergeInsnID's*/0,
      GIR_ConstrainSelectedInstOperands, /*InsnID*/0,
      GIR_EraseFromParent, /*InsnID*/0,
      // GIR_Coverage, 2763,
      GIR_Done,
    // Label 1049: @68484
    GIM_Reject,
    // Label 825: @68485
    GIM_Try, /*On fail goto*//*Label 1050*/ GIMT_Encode4(68562), // Rule ID 2418 //
      GIM_CheckFeatures, GIMT_Encode2(GIFBS_isGFX12Plus),
      GIM_CheckMemorySizeLessThanLLT, /*MI*/0, /*MMO*/0, /*OpIdx*/0,
      GIM_CheckMemorySizeEqualTo, /*MI*/0, /*MMO*/0, /*Size*/GIMT_Encode4(1),
      GIM_CheckAtomicOrdering, /*MI*/0, /*Order*/(uint8_t)AtomicOrdering::NotAtomic,
      GIM_CheckRegBankForClass, /*MI*/0, /*Op*/0, /*RC*/GIMT_Encode2(AMDGPU::SReg_32_XM0_XEXECRegClassID),
      GIM_CheckPointerToAny, /*MI*/0, /*Op*/1, /*SizeInBits*/0,
      GIM_CheckCxxInsnPredicate, /*MI*/0, /*FnId*/GIMT_Encode2(GICXXPred_MI_Predicate_smrd_extloadi8),
      GIM_CheckComplexPattern, /*MI*/0, /*Op*/1, /*Renderer*/GIMT_Encode2(0), GIMT_Encode2(GICP_gi_smrd_sgpr_imm),
      // (ld:{ *:[i32] } (SMRDSgprImm:{ *:[iPTR] } i64:{ *:[i64] }:$sbase, i32:{ *:[i32] }:$soffset, i32:{ *:[i32] }:$offset))<<P:Predicate_unindexedload>><<P:Predicate_extload>><<P:Predicate_extloadi8>><<P:Predicate_smrd_extloadi8>>  =>  (S_LOAD_U8_SGPR_IMM:{ *:[i32] } ?:{ *:[i64] }:$sbase, ?:{ *:[i32] }:$soffset, ?:{ *:[i32] }:$offset, 0:{ *:[i32] })
      GIR_BuildMI, /*InsnID*/0, /*Opcode*/GIMT_Encode2(AMDGPU::S_LOAD_U8_SGPR_IMM),
      GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/0, // DstI[sdst]
      GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/0, // sbase
      GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/1, // soffset
      GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/2, // offset
      GIR_AddImm8, /*InsnID*/0, /*Imm*/0,
      GIR_MergeMemOperands, /*InsnID*/0, /*NumInsns*/1, /*MergeInsnID's*/0,
      GIR_ConstrainSelectedInstOperands, /*InsnID*/0,
      GIR_EraseFromParent, /*InsnID*/0,
      // GIR_Coverage, 2418,
      GIR_Done,
    // Label 1050: @68562
    GIM_Try, /*On fail goto*//*Label 1051*/ GIMT_Encode4(68639), // Rule ID 2433 //
      GIM_CheckFeatures, GIMT_Encode2(GIFBS_isGFX12Plus),
      GIM_CheckMemorySizeLessThanLLT, /*MI*/0, /*MMO*/0, /*OpIdx*/0,
      GIM_CheckMemorySizeEqualTo, /*MI*/0, /*MMO*/0, /*Size*/GIMT_Encode4(2),
      GIM_CheckAtomicOrdering, /*MI*/0, /*Order*/(uint8_t)AtomicOrdering::NotAtomic,
      GIM_CheckRegBankForClass, /*MI*/0, /*Op*/0, /*RC*/GIMT_Encode2(AMDGPU::SReg_32_XM0_XEXECRegClassID),
      GIM_CheckPointerToAny, /*MI*/0, /*Op*/1, /*SizeInBits*/0,
      GIM_CheckCxxInsnPredicate, /*MI*/0, /*FnId*/GIMT_Encode2(GICXXPred_MI_Predicate_smrd_extloadi16),
      GIM_CheckComplexPattern, /*MI*/0, /*Op*/1, /*Renderer*/GIMT_Encode2(0), GIMT_Encode2(GICP_gi_smrd_sgpr_imm),
      // (ld:{ *:[i32] } (SMRDSgprImm:{ *:[iPTR] } i64:{ *:[i64] }:$sbase, i32:{ *:[i32] }:$soffset, i32:{ *:[i32] }:$offset))<<P:Predicate_unindexedload>><<P:Predicate_extload>><<P:Predicate_extloadi16>><<P:Predicate_smrd_extloadi16>>  =>  (S_LOAD_U16_SGPR_IMM:{ *:[i32] } ?:{ *:[i64] }:$sbase, ?:{ *:[i32] }:$soffset, ?:{ *:[i32] }:$offset, 0:{ *:[i32] })
      GIR_BuildMI, /*InsnID*/0, /*Opcode*/GIMT_Encode2(AMDGPU::S_LOAD_U16_SGPR_IMM),
      GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/0, // DstI[sdst]
      GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/0, // sbase
      GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/1, // soffset
      GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/2, // offset
      GIR_AddImm8, /*InsnID*/0, /*Imm*/0,
      GIR_MergeMemOperands, /*InsnID*/0, /*NumInsns*/1, /*MergeInsnID's*/0,
      GIR_ConstrainSelectedInstOperands, /*InsnID*/0,
      GIR_EraseFromParent, /*InsnID*/0,
      // GIR_Coverage, 2433,
      GIR_Done,
    // Label 1051: @68639
    GIM_Try, /*On fail goto*//*Label 1052*/ GIMT_Encode4(68709), // Rule ID 2409 //
      GIM_CheckFeatures, GIMT_Encode2(GIFBS_isGFX9Plus),
      GIM_CheckMemorySizeEqualToLLT, /*MI*/0, /*MMO*/0, /*OpIdx*/0,
      GIM_CheckAtomicOrdering, /*MI*/0, /*Order*/(uint8_t)AtomicOrdering::NotAtomic,
      GIM_CheckRegBankForClass, /*MI*/0, /*Op*/0, /*RC*/GIMT_Encode2(AMDGPU::SReg_32_XM0_XEXECRegClassID),
      GIM_CheckPointerToAny, /*MI*/0, /*Op*/1, /*SizeInBits*/0,
      GIM_CheckCxxInsnPredicate, /*MI*/0, /*FnId*/GIMT_Encode2(GICXXPred_MI_Predicate_smrd_load),
      GIM_CheckComplexPattern, /*MI*/0, /*Op*/1, /*Renderer*/GIMT_Encode2(0), GIMT_Encode2(GICP_gi_smrd_sgpr_imm),
      // (ld:{ *:[i32] } (SMRDSgprImm:{ *:[iPTR] } i64:{ *:[i64] }:$sbase, i32:{ *:[i32] }:$soffset, i32:{ *:[i32] }:$offset))<<P:Predicate_unindexedload>><<P:Predicate_load>><<P:Predicate_smrd_load>>  =>  (S_LOAD_DWORD_SGPR_IMM:{ *:[i32] } ?:{ *:[i64] }:$sbase, ?:{ *:[i32] }:$soffset, ?:{ *:[i32] }:$offset, 0:{ *:[i32] })
      GIR_BuildMI, /*InsnID*/0, /*Opcode*/GIMT_Encode2(AMDGPU::S_LOAD_DWORD_SGPR_IMM),
      GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/0, // DstI[sdst]
      GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/0, // sbase
      GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/1, // soffset
      GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/2, // offset
      GIR_AddImm8, /*InsnID*/0, /*Imm*/0,
      GIR_MergeMemOperands, /*InsnID*/0, /*NumInsns*/1, /*MergeInsnID's*/0,
      GIR_ConstrainSelectedInstOperands, /*InsnID*/0,
      GIR_EraseFromParent, /*InsnID*/0,
      // GIR_Coverage, 2409,
      GIR_Done,
    // Label 1052: @68709
    GIM_Try, /*On fail goto*//*Label 1053*/ GIMT_Encode4(68779), // Rule ID 2456 //
      GIM_CheckFeatures, GIMT_Encode2(GIFBS_isGFX9Plus),
      GIM_CheckMemorySizeEqualToLLT, /*MI*/0, /*MMO*/0, /*OpIdx*/0,
      GIM_CheckAtomicOrdering, /*MI*/0, /*Order*/(uint8_t)AtomicOrdering::NotAtomic,
      GIM_CheckRegBankForClass, /*MI*/0, /*Op*/0, /*RC*/GIMT_Encode2(AMDGPU::SReg_32_XM0_XEXECRegClassID),
      GIM_CheckPointerToAny, /*MI*/0, /*Op*/1, /*SizeInBits*/0,
      GIM_CheckCxxInsnPredicate, /*MI*/0, /*FnId*/GIMT_Encode2(GICXXPred_MI_Predicate_smrd_load),
      GIM_CheckComplexPattern, /*MI*/0, /*Op*/1, /*Renderer*/GIMT_Encode2(0), GIMT_Encode2(GICP_gi_smrd_sgpr_imm),
      // (ld:{ *:[f32] } (SMRDSgprImm:{ *:[iPTR] } i64:{ *:[i64] }:$sbase, i32:{ *:[i32] }:$soffset, i32:{ *:[i32] }:$offset))<<P:Predicate_unindexedload>><<P:Predicate_load>><<P:Predicate_smrd_load>>  =>  (S_LOAD_DWORD_SGPR_IMM:{ *:[f32] } ?:{ *:[i64] }:$sbase, ?:{ *:[i32] }:$soffset, ?:{ *:[i32] }:$offset, 0:{ *:[i32] })
      GIR_BuildMI, /*InsnID*/0, /*Opcode*/GIMT_Encode2(AMDGPU::S_LOAD_DWORD_SGPR_IMM),
      GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/0, // DstI[sdst]
      GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/0, // sbase
      GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/1, // soffset
      GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/2, // offset
      GIR_AddImm8, /*InsnID*/0, /*Imm*/0,
      GIR_MergeMemOperands, /*InsnID*/0, /*NumInsns*/1, /*MergeInsnID's*/0,
      GIR_ConstrainSelectedInstOperands, /*InsnID*/0,
      GIR_EraseFromParent, /*InsnID*/0,
      // GIR_Coverage, 2456,
      GIR_Done,
    // Label 1053: @68779
    GIM_Try, /*On fail goto*//*Label 1054*/ GIMT_Encode4(68851), // Rule ID 2416 //
      GIM_CheckFeatures, GIMT_Encode2(GIFBS_isGFX12Plus),
      GIM_CheckMemorySizeLessThanLLT, /*MI*/0, /*MMO*/0, /*OpIdx*/0,
      GIM_CheckMemorySizeEqualTo, /*MI*/0, /*MMO*/0, /*Size*/GIMT_Encode4(1),
      GIM_CheckAtomicOrdering, /*MI*/0, /*Order*/(uint8_t)AtomicOrdering::NotAtomic,
      GIM_CheckRegBankForClass, /*MI*/0, /*Op*/0, /*RC*/GIMT_Encode2(AMDGPU::SReg_32_XM0_XEXECRegClassID),
      GIM_CheckPointerToAny, /*MI*/0, /*Op*/1, /*SizeInBits*/0,
      GIM_CheckCxxInsnPredicate, /*MI*/0, /*FnId*/GIMT_Encode2(GICXXPred_MI_Predicate_smrd_extloadi8),
      GIM_CheckComplexPattern, /*MI*/0, /*Op*/1, /*Renderer*/GIMT_Encode2(0), GIMT_Encode2(GICP_gi_smrd_imm),
      // (ld:{ *:[i32] } (SMRDImm:{ *:[iPTR] } i64:{ *:[i64] }:$sbase, i32:{ *:[i32] }:$offset))<<P:Predicate_unindexedload>><<P:Predicate_extload>><<P:Predicate_extloadi8>><<P:Predicate_smrd_extloadi8>>  =>  (S_LOAD_U8_IMM:{ *:[i32] } ?:{ *:[i64] }:$sbase, ?:{ *:[i32] }:$offset, 0:{ *:[i32] })
      GIR_BuildMI, /*InsnID*/0, /*Opcode*/GIMT_Encode2(AMDGPU::S_LOAD_U8_IMM),
      GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/0, // DstI[sdst]
      GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/0, // sbase
      GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/1, // offset
      GIR_AddImm8, /*InsnID*/0, /*Imm*/0,
      GIR_MergeMemOperands, /*InsnID*/0, /*NumInsns*/1, /*MergeInsnID's*/0,
      GIR_ConstrainSelectedInstOperands, /*InsnID*/0,
      GIR_EraseFromParent, /*InsnID*/0,
      // GIR_Coverage, 2416,
      GIR_Done,
    // Label 1054: @68851
    GIM_Try, /*On fail goto*//*Label 1055*/ GIMT_Encode4(68926), // Rule ID 2417 //
      GIM_CheckFeatures, GIMT_Encode2(GIFBS_isGFX12Plus),
      GIM_CheckMemorySizeLessThanLLT, /*MI*/0, /*MMO*/0, /*OpIdx*/0,
      GIM_CheckMemorySizeEqualTo, /*MI*/0, /*MMO*/0, /*Size*/GIMT_Encode4(1),
      GIM_CheckAtomicOrdering, /*MI*/0, /*Order*/(uint8_t)AtomicOrdering::NotAtomic,
      GIM_CheckRegBankForClass, /*MI*/0, /*Op*/0, /*RC*/GIMT_Encode2(AMDGPU::SReg_32_XM0_XEXECRegClassID),
      GIM_CheckPointerToAny, /*MI*/0, /*Op*/1, /*SizeInBits*/0,
      GIM_CheckCxxInsnPredicate, /*MI*/0, /*FnId*/GIMT_Encode2(GICXXPred_MI_Predicate_smrd_extloadi8),
      GIM_CheckComplexPattern, /*MI*/0, /*Op*/1, /*Renderer*/GIMT_Encode2(0), GIMT_Encode2(GICP_gi_smrd_sgpr),
      // (ld:{ *:[i32] } (SMRDSgpr:{ *:[iPTR] } i64:{ *:[i64] }:$sbase, i32:{ *:[i32] }:$soffset))<<P:Predicate_unindexedload>><<P:Predicate_extload>><<P:Predicate_extloadi8>><<P:Predicate_smrd_extloadi8>>  =>  (S_LOAD_U8_SGPR_IMM:{ *:[i32] } ?:{ *:[i64] }:$sbase, ?:{ *:[i32] }:$soffset, 0:{ *:[i32] }, 0:{ *:[i32] })
      GIR_BuildMI, /*InsnID*/0, /*Opcode*/GIMT_Encode2(AMDGPU::S_LOAD_U8_SGPR_IMM),
      GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/0, // DstI[sdst]
      GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/0, // sbase
      GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/1, // soffset
      GIR_AddImm8, /*InsnID*/0, /*Imm*/0,
      GIR_AddImm8, /*InsnID*/0, /*Imm*/0,
      GIR_MergeMemOperands, /*InsnID*/0, /*NumInsns*/1, /*MergeInsnID's*/0,
      GIR_ConstrainSelectedInstOperands, /*InsnID*/0,
      GIR_EraseFromParent, /*InsnID*/0,
      // GIR_Coverage, 2417,
      GIR_Done,
    // Label 1055: @68926
    GIM_Try, /*On fail goto*//*Label 1056*/ GIMT_Encode4(68998), // Rule ID 2431 //
      GIM_CheckFeatures, GIMT_Encode2(GIFBS_isGFX12Plus),
      GIM_CheckMemorySizeLessThanLLT, /*MI*/0, /*MMO*/0, /*OpIdx*/0,
      GIM_CheckMemorySizeEqualTo, /*MI*/0, /*MMO*/0, /*Size*/GIMT_Encode4(2),
      GIM_CheckAtomicOrdering, /*MI*/0, /*Order*/(uint8_t)AtomicOrdering::NotAtomic,
      GIM_CheckRegBankForClass, /*MI*/0, /*Op*/0, /*RC*/GIMT_Encode2(AMDGPU::SReg_32_XM0_XEXECRegClassID),
      GIM_CheckPointerToAny, /*MI*/0, /*Op*/1, /*SizeInBits*/0,
      GIM_CheckCxxInsnPredicate, /*MI*/0, /*FnId*/GIMT_Encode2(GICXXPred_MI_Predicate_smrd_extloadi16),
      GIM_CheckComplexPattern, /*MI*/0, /*Op*/1, /*Renderer*/GIMT_Encode2(0), GIMT_Encode2(GICP_gi_smrd_imm),
      // (ld:{ *:[i32] } (SMRDImm:{ *:[iPTR] } i64:{ *:[i64] }:$sbase, i32:{ *:[i32] }:$offset))<<P:Predicate_unindexedload>><<P:Predicate_extload>><<P:Predicate_extloadi16>><<P:Predicate_smrd_extloadi16>>  =>  (S_LOAD_U16_IMM:{ *:[i32] } ?:{ *:[i64] }:$sbase, ?:{ *:[i32] }:$offset, 0:{ *:[i32] })
      GIR_BuildMI, /*InsnID*/0, /*Opcode*/GIMT_Encode2(AMDGPU::S_LOAD_U16_IMM),
      GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/0, // DstI[sdst]
      GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/0, // sbase
      GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/1, // offset
      GIR_AddImm8, /*InsnID*/0, /*Imm*/0,
      GIR_MergeMemOperands, /*InsnID*/0, /*NumInsns*/1, /*MergeInsnID's*/0,
      GIR_ConstrainSelectedInstOperands, /*InsnID*/0,
      GIR_EraseFromParent, /*InsnID*/0,
      // GIR_Coverage, 2431,
      GIR_Done,
    // Label 1056: @68998
    GIM_Try, /*On fail goto*//*Label 1057*/ GIMT_Encode4(69073), // Rule ID 2432 //
      GIM_CheckFeatures, GIMT_Encode2(GIFBS_isGFX12Plus),
      GIM_CheckMemorySizeLessThanLLT, /*MI*/0, /*MMO*/0, /*OpIdx*/0,
      GIM_CheckMemorySizeEqualTo, /*MI*/0, /*MMO*/0, /*Size*/GIMT_Encode4(2),
      GIM_CheckAtomicOrdering, /*MI*/0, /*Order*/(uint8_t)AtomicOrdering::NotAtomic,
      GIM_CheckRegBankForClass, /*MI*/0, /*Op*/0, /*RC*/GIMT_Encode2(AMDGPU::SReg_32_XM0_XEXECRegClassID),
      GIM_CheckPointerToAny, /*MI*/0, /*Op*/1, /*SizeInBits*/0,
      GIM_CheckCxxInsnPredicate, /*MI*/0, /*FnId*/GIMT_Encode2(GICXXPred_MI_Predicate_smrd_extloadi16),
      GIM_CheckComplexPattern, /*MI*/0, /*Op*/1, /*Renderer*/GIMT_Encode2(0), GIMT_Encode2(GICP_gi_smrd_sgpr),
      // (ld:{ *:[i32] } (SMRDSgpr:{ *:[iPTR] } i64:{ *:[i64] }:$sbase, i32:{ *:[i32] }:$soffset))<<P:Predicate_unindexedload>><<P:Predicate_extload>><<P:Predicate_extloadi16>><<P:Predicate_smrd_extloadi16>>  =>  (S_LOAD_U16_SGPR_IMM:{ *:[i32] } ?:{ *:[i64] }:$sbase, ?:{ *:[i32] }:$soffset, 0:{ *:[i32] }, 0:{ *:[i32] })
      GIR_BuildMI, /*InsnID*/0, /*Opcode*/GIMT_Encode2(AMDGPU::S_LOAD_U16_SGPR_IMM),
      GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/0, // DstI[sdst]
      GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/0, // sbase
      GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/1, // soffset
      GIR_AddImm8, /*InsnID*/0, /*Imm*/0,
      GIR_AddImm8, /*InsnID*/0, /*Imm*/0,
      GIR_MergeMemOperands, /*InsnID*/0, /*NumInsns*/1, /*MergeInsnID's*/0,
      GIR_ConstrainSelectedInstOperands, /*InsnID*/0,
      GIR_EraseFromParent, /*InsnID*/0,
      // GIR_Coverage, 2432,
      GIR_Done,
    // Label 1057: @69073
    GIM_Try, /*On fail goto*//*Label 1058*/ GIMT_Encode4(69135), // Rule ID 2405 //
      GIM_CheckMemorySizeEqualToLLT, /*MI*/0, /*MMO*/0, /*OpIdx*/0,
      GIM_CheckAtomicOrdering, /*MI*/0, /*Order*/(uint8_t)AtomicOrdering::NotAtomic,
      GIM_CheckRegBankForClass, /*MI*/0, /*Op*/0, /*RC*/GIMT_Encode2(AMDGPU::SReg_32_XM0_XEXECRegClassID),
      GIM_CheckPointerToAny, /*MI*/0, /*Op*/1, /*SizeInBits*/0,
      GIM_CheckCxxInsnPredicate, /*MI*/0, /*FnId*/GIMT_Encode2(GICXXPred_MI_Predicate_smrd_load),
      GIM_CheckComplexPattern, /*MI*/0, /*Op*/1, /*Renderer*/GIMT_Encode2(0), GIMT_Encode2(GICP_gi_smrd_imm),
      // (ld:{ *:[i32] } (SMRDImm:{ *:[iPTR] } i64:{ *:[i64] }:$sbase, i32:{ *:[i32] }:$offset))<<P:Predicate_unindexedload>><<P:Predicate_load>><<P:Predicate_smrd_load>>  =>  (S_LOAD_DWORD_IMM:{ *:[i32] } ?:{ *:[i64] }:$sbase, ?:{ *:[i32] }:$offset, 0:{ *:[i32] })
      GIR_BuildMI, /*InsnID*/0, /*Opcode*/GIMT_Encode2(AMDGPU::S_LOAD_DWORD_IMM),
      GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/0, // DstI[sdst]
      GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/0, // sbase
      GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/1, // offset
      GIR_AddImm8, /*InsnID*/0, /*Imm*/0,
      GIR_MergeMemOperands, /*InsnID*/0, /*NumInsns*/1, /*MergeInsnID's*/0,
      GIR_ConstrainSelectedInstOperands, /*InsnID*/0,
      GIR_EraseFromParent, /*InsnID*/0,
      // GIR_Coverage, 2405,
      GIR_Done,
    // Label 1058: @69135
    GIM_Try, /*On fail goto*//*Label 1059*/ GIMT_Encode4(69200), // Rule ID 2406 //
      GIM_CheckFeatures, GIMT_Encode2(GIFBS_isGFX7Only),
      GIM_CheckMemorySizeEqualToLLT, /*MI*/0, /*MMO*/0, /*OpIdx*/0,
      GIM_CheckAtomicOrdering, /*MI*/0, /*Order*/(uint8_t)AtomicOrdering::NotAtomic,
      GIM_CheckRegBankForClass, /*MI*/0, /*Op*/0, /*RC*/GIMT_Encode2(AMDGPU::SReg_32_XM0_XEXECRegClassID),
      GIM_CheckPointerToAny, /*MI*/0, /*Op*/1, /*SizeInBits*/0,
      GIM_CheckCxxInsnPredicate, /*MI*/0, /*FnId*/GIMT_Encode2(GICXXPred_MI_Predicate_smrd_load),
      GIM_CheckComplexPattern, /*MI*/0, /*Op*/1, /*Renderer*/GIMT_Encode2(0), GIMT_Encode2(GICP_gi_smrd_imm32),
      // (ld:{ *:[i32] } (SMRDImm32:{ *:[iPTR] } i64:{ *:[i64] }:$sbase, i32:{ *:[i32] }:$offset))<<P:Predicate_unindexedload>><<P:Predicate_load>><<P:Predicate_smrd_load>>  =>  (S_LOAD_DWORD_IMM_ci:{ *:[i32] } ?:{ *:[i64] }:$sbase, ?:{ *:[i32] }:$offset, 0:{ *:[i32] })
      GIR_BuildMI, /*InsnID*/0, /*Opcode*/GIMT_Encode2(AMDGPU::S_LOAD_DWORD_IMM_ci),
      GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/0, // DstI[sdst]
      GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/0, // sbase
      GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/1, // offset
      GIR_AddImm8, /*InsnID*/0, /*Imm*/0,
      GIR_MergeMemOperands, /*InsnID*/0, /*NumInsns*/1, /*MergeInsnID's*/0,
      GIR_ConstrainSelectedInstOperands, /*InsnID*/0,
      GIR_EraseFromParent, /*InsnID*/0,
      // GIR_Coverage, 2406,
      GIR_Done,
    // Label 1059: @69200
    GIM_Try, /*On fail goto*//*Label 1060*/ GIMT_Encode4(69265), // Rule ID 2407 //
      GIM_CheckFeatures, GIMT_Encode2(GIFBS_isNotGFX9Plus),
      GIM_CheckMemorySizeEqualToLLT, /*MI*/0, /*MMO*/0, /*OpIdx*/0,
      GIM_CheckAtomicOrdering, /*MI*/0, /*Order*/(uint8_t)AtomicOrdering::NotAtomic,
      GIM_CheckRegBankForClass, /*MI*/0, /*Op*/0, /*RC*/GIMT_Encode2(AMDGPU::SReg_32_XM0_XEXECRegClassID),
      GIM_CheckPointerToAny, /*MI*/0, /*Op*/1, /*SizeInBits*/0,
      GIM_CheckCxxInsnPredicate, /*MI*/0, /*FnId*/GIMT_Encode2(GICXXPred_MI_Predicate_smrd_load),
      GIM_CheckComplexPattern, /*MI*/0, /*Op*/1, /*Renderer*/GIMT_Encode2(0), GIMT_Encode2(GICP_gi_smrd_sgpr),
      // (ld:{ *:[i32] } (SMRDSgpr:{ *:[iPTR] } i64:{ *:[i64] }:$sbase, i32:{ *:[i32] }:$soffset))<<P:Predicate_unindexedload>><<P:Predicate_load>><<P:Predicate_smrd_load>>  =>  (S_LOAD_DWORD_SGPR:{ *:[i32] } ?:{ *:[i64] }:$sbase, ?:{ *:[i32] }:$soffset, 0:{ *:[i32] })
      GIR_BuildMI, /*InsnID*/0, /*Opcode*/GIMT_Encode2(AMDGPU::S_LOAD_DWORD_SGPR),
      GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/0, // DstI[sdst]
      GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/0, // sbase
      GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/1, // soffset
      GIR_AddImm8, /*InsnID*/0, /*Imm*/0,
      GIR_MergeMemOperands, /*InsnID*/0, /*NumInsns*/1, /*MergeInsnID's*/0,
      GIR_ConstrainSelectedInstOperands, /*InsnID*/0,
      GIR_EraseFromParent, /*InsnID*/0,
      // GIR_Coverage, 2407,
      GIR_Done,
    // Label 1060: @69265
    GIM_Try, /*On fail goto*//*Label 1061*/ GIMT_Encode4(69333), // Rule ID 2408 //
      GIM_CheckFeatures, GIMT_Encode2(GIFBS_isGFX9Plus),
      GIM_CheckMemorySizeEqualToLLT, /*MI*/0, /*MMO*/0, /*OpIdx*/0,
      GIM_CheckAtomicOrdering, /*MI*/0, /*Order*/(uint8_t)AtomicOrdering::NotAtomic,
      GIM_CheckRegBankForClass, /*MI*/0, /*Op*/0, /*RC*/GIMT_Encode2(AMDGPU::SReg_32_XM0_XEXECRegClassID),
      GIM_CheckPointerToAny, /*MI*/0, /*Op*/1, /*SizeInBits*/0,
      GIM_CheckCxxInsnPredicate, /*MI*/0, /*FnId*/GIMT_Encode2(GICXXPred_MI_Predicate_smrd_load),
      GIM_CheckComplexPattern, /*MI*/0, /*Op*/1, /*Renderer*/GIMT_Encode2(0), GIMT_Encode2(GICP_gi_smrd_sgpr),
      // (ld:{ *:[i32] } (SMRDSgpr:{ *:[iPTR] } i64:{ *:[i64] }:$sbase, i32:{ *:[i32] }:$soffset))<<P:Predicate_unindexedload>><<P:Predicate_load>><<P:Predicate_smrd_load>>  =>  (S_LOAD_DWORD_SGPR_IMM:{ *:[i32] } ?:{ *:[i64] }:$sbase, ?:{ *:[i32] }:$soffset, 0:{ *:[i32] }, 0:{ *:[i32] })
      GIR_BuildMI, /*InsnID*/0, /*Opcode*/GIMT_Encode2(AMDGPU::S_LOAD_DWORD_SGPR_IMM),
      GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/0, // DstI[sdst]
      GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/0, // sbase
      GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/1, // soffset
      GIR_AddImm8, /*InsnID*/0, /*Imm*/0,
      GIR_AddImm8, /*InsnID*/0, /*Imm*/0,
      GIR_MergeMemOperands, /*InsnID*/0, /*NumInsns*/1, /*MergeInsnID's*/0,
      GIR_ConstrainSelectedInstOperands, /*InsnID*/0,
      GIR_EraseFromParent, /*InsnID*/0,
      // GIR_Coverage, 2408,
      GIR_Done,
    // Label 1061: @69333
    GIM_Try, /*On fail goto*//*Label 1062*/ GIMT_Encode4(69395), // Rule ID 2452 //
      GIM_CheckMemorySizeEqualToLLT, /*MI*/0, /*MMO*/0, /*OpIdx*/0,
      GIM_CheckAtomicOrdering, /*MI*/0, /*Order*/(uint8_t)AtomicOrdering::NotAtomic,
      GIM_CheckRegBankForClass, /*MI*/0, /*Op*/0, /*RC*/GIMT_Encode2(AMDGPU::SReg_32_XM0_XEXECRegClassID),
      GIM_CheckPointerToAny, /*MI*/0, /*Op*/1, /*SizeInBits*/0,
      GIM_CheckCxxInsnPredicate, /*MI*/0, /*FnId*/GIMT_Encode2(GICXXPred_MI_Predicate_smrd_load),
      GIM_CheckComplexPattern, /*MI*/0, /*Op*/1, /*Renderer*/GIMT_Encode2(0), GIMT_Encode2(GICP_gi_smrd_imm),
      // (ld:{ *:[f32] } (SMRDImm:{ *:[iPTR] } i64:{ *:[i64] }:$sbase, i32:{ *:[i32] }:$offset))<<P:Predicate_unindexedload>><<P:Predicate_load>><<P:Predicate_smrd_load>>  =>  (S_LOAD_DWORD_IMM:{ *:[f32] } ?:{ *:[i64] }:$sbase, ?:{ *:[i32] }:$offset, 0:{ *:[i32] })
      GIR_BuildMI, /*InsnID*/0, /*Opcode*/GIMT_Encode2(AMDGPU::S_LOAD_DWORD_IMM),
      GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/0, // DstI[sdst]
      GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/0, // sbase
      GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/1, // offset
      GIR_AddImm8, /*InsnID*/0, /*Imm*/0,
      GIR_MergeMemOperands, /*InsnID*/0, /*NumInsns*/1, /*MergeInsnID's*/0,
      GIR_ConstrainSelectedInstOperands, /*InsnID*/0,
      GIR_EraseFromParent, /*InsnID*/0,
      // GIR_Coverage, 2452,
      GIR_Done,
    // Label 1062: @69395
    GIM_Try, /*On fail goto*//*Label 1063*/ GIMT_Encode4(69460), // Rule ID 2453 //
      GIM_CheckFeatures, GIMT_Encode2(GIFBS_isGFX7Only),
      GIM_CheckMemorySizeEqualToLLT, /*MI*/0, /*MMO*/0, /*OpIdx*/0,
      GIM_CheckAtomicOrdering, /*MI*/0, /*Order*/(uint8_t)AtomicOrdering::NotAtomic,
      GIM_CheckRegBankForClass, /*MI*/0, /*Op*/0, /*RC*/GIMT_Encode2(AMDGPU::SReg_32_XM0_XEXECRegClassID),
      GIM_CheckPointerToAny, /*MI*/0, /*Op*/1, /*SizeInBits*/0,
      GIM_CheckCxxInsnPredicate, /*MI*/0, /*FnId*/GIMT_Encode2(GICXXPred_MI_Predicate_smrd_load),
      GIM_CheckComplexPattern, /*MI*/0, /*Op*/1, /*Renderer*/GIMT_Encode2(0), GIMT_Encode2(GICP_gi_smrd_imm32),
      // (ld:{ *:[f32] } (SMRDImm32:{ *:[iPTR] } i64:{ *:[i64] }:$sbase, i32:{ *:[i32] }:$offset))<<P:Predicate_unindexedload>><<P:Predicate_load>><<P:Predicate_smrd_load>>  =>  (S_LOAD_DWORD_IMM_ci:{ *:[f32] } ?:{ *:[i64] }:$sbase, ?:{ *:[i32] }:$offset, 0:{ *:[i32] })
      GIR_BuildMI, /*InsnID*/0, /*Opcode*/GIMT_Encode2(AMDGPU::S_LOAD_DWORD_IMM_ci),
      GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/0, // DstI[sdst]
      GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/0, // sbase
      GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/1, // offset
      GIR_AddImm8, /*InsnID*/0, /*Imm*/0,
      GIR_MergeMemOperands, /*InsnID*/0, /*NumInsns*/1, /*MergeInsnID's*/0,
      GIR_ConstrainSelectedInstOperands, /*InsnID*/0,
      GIR_EraseFromParent, /*InsnID*/0,
      // GIR_Coverage, 2453,
      GIR_Done,
    // Label 1063: @69460
    GIM_Try, /*On fail goto*//*Label 1064*/ GIMT_Encode4(69525), // Rule ID 2454 //
      GIM_CheckFeatures, GIMT_Encode2(GIFBS_isNotGFX9Plus),
      GIM_CheckMemorySizeEqualToLLT, /*MI*/0, /*MMO*/0, /*OpIdx*/0,
      GIM_CheckAtomicOrdering, /*MI*/0, /*Order*/(uint8_t)AtomicOrdering::NotAtomic,
      GIM_CheckRegBankForClass, /*MI*/0, /*Op*/0, /*RC*/GIMT_Encode2(AMDGPU::SReg_32_XM0_XEXECRegClassID),
      GIM_CheckPointerToAny, /*MI*/0, /*Op*/1, /*SizeInBits*/0,
      GIM_CheckCxxInsnPredicate, /*MI*/0, /*FnId*/GIMT_Encode2(GICXXPred_MI_Predicate_smrd_load),
      GIM_CheckComplexPattern, /*MI*/0, /*Op*/1, /*Renderer*/GIMT_Encode2(0), GIMT_Encode2(GICP_gi_smrd_sgpr),
      // (ld:{ *:[f32] } (SMRDSgpr:{ *:[iPTR] } i64:{ *:[i64] }:$sbase, i32:{ *:[i32] }:$soffset))<<P:Predicate_unindexedload>><<P:Predicate_load>><<P:Predicate_smrd_load>>  =>  (S_LOAD_DWORD_SGPR:{ *:[f32] } ?:{ *:[i64] }:$sbase, ?:{ *:[i32] }:$soffset, 0:{ *:[i32] })
      GIR_BuildMI, /*InsnID*/0, /*Opcode*/GIMT_Encode2(AMDGPU::S_LOAD_DWORD_SGPR),
      GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/0, // DstI[sdst]
      GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/0, // sbase
      GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/1, // soffset
      GIR_AddImm8, /*InsnID*/0, /*Imm*/0,
      GIR_MergeMemOperands, /*InsnID*/0, /*NumInsns*/1, /*MergeInsnID's*/0,
      GIR_ConstrainSelectedInstOperands, /*InsnID*/0,
      GIR_EraseFromParent, /*InsnID*/0,
      // GIR_Coverage, 2454,
      GIR_Done,
    // Label 1064: @69525
    GIM_Try, /*On fail goto*//*Label 1065*/ GIMT_Encode4(69593), // Rule ID 2455 //
      GIM_CheckFeatures, GIMT_Encode2(GIFBS_isGFX9Plus),
      GIM_CheckMemorySizeEqualToLLT, /*MI*/0, /*MMO*/0, /*OpIdx*/0,
      GIM_CheckAtomicOrdering, /*MI*/0, /*Order*/(uint8_t)AtomicOrdering::NotAtomic,
      GIM_CheckRegBankForClass, /*MI*/0, /*Op*/0, /*RC*/GIMT_Encode2(AMDGPU::SReg_32_XM0_XEXECRegClassID),
      GIM_CheckPointerToAny, /*MI*/0, /*Op*/1, /*SizeInBits*/0,
      GIM_CheckCxxInsnPredicate, /*MI*/0, /*FnId*/GIMT_Encode2(GICXXPred_MI_Predicate_smrd_load),
      GIM_CheckComplexPattern, /*MI*/0, /*Op*/1, /*Renderer*/GIMT_Encode2(0), GIMT_Encode2(GICP_gi_smrd_sgpr),
      // (ld:{ *:[f32] } (SMRDSgpr:{ *:[iPTR] } i64:{ *:[i64] }:$sbase, i32:{ *:[i32] }:$soffset))<<P:Predicate_unindexedload>><<P:Predicate_load>><<P:Predicate_smrd_load>>  =>  (S_LOAD_DWORD_SGPR_IMM:{ *:[f32] } ?:{ *:[i64] }:$sbase, ?:{ *:[i32] }:$soffset, 0:{ *:[i32] }, 0:{ *:[i32] })
      GIR_BuildMI, /*InsnID*/0, /*Opcode*/GIMT_Encode2(AMDGPU::S_LOAD_DWORD_SGPR_IMM),
      GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/0, // DstI[sdst]
      GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/0, // sbase
      GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/1, // soffset
      GIR_AddImm8, /*InsnID*/0, /*Imm*/0,
      GIR_AddImm8, /*InsnID*/0, /*Imm*/0,
      GIR_MergeMemOperands, /*InsnID*/0, /*NumInsns*/1, /*MergeInsnID's*/0,
      GIR_ConstrainSelectedInstOperands, /*InsnID*/0,
      GIR_EraseFromParent, /*InsnID*/0,
      // GIR_Coverage, 2455,
      GIR_Done,
    // Label 1065: @69593
    GIM_Try, /*On fail goto*//*Label 1066*/ GIMT_Encode4(69660), // Rule ID 2419 //
      GIM_CheckFeatures, GIMT_Encode2(GIFBS_isGFX12Plus),
      GIM_CheckMemorySizeLessThanLLT, /*MI*/0, /*MMO*/0, /*OpIdx*/0,
      GIM_CheckMemorySizeEqualTo, /*MI*/0, /*MMO*/0, /*Size*/GIMT_Encode4(1),
      GIM_CheckAtomicOrdering, /*MI*/0, /*Order*/(uint8_t)AtomicOrdering::NotAtomic,
      GIM_CheckRegBankForClass, /*MI*/0, /*Op*/0, /*RC*/GIMT_Encode2(AMDGPU::SReg_32_XM0_XEXECRegClassID),
      // MIs[0] sbase
      GIM_CheckPointerToAny, /*MI*/0, /*Op*/1, /*SizeInBits*/64,
      GIM_CheckRegBankForClass, /*MI*/0, /*Op*/1, /*RC*/GIMT_Encode2(AMDGPU::SReg_64RegClassID),
      GIM_CheckCxxInsnPredicate, /*MI*/0, /*FnId*/GIMT_Encode2(GICXXPred_MI_Predicate_smrd_extloadi8),
      // (ld:{ *:[i32] } SReg_64:{ *:[i64] }:$sbase)<<P:Predicate_unindexedload>><<P:Predicate_extload>><<P:Predicate_extloadi8>><<P:Predicate_smrd_extloadi8>>  =>  (S_LOAD_U8_IMM:{ *:[i32] } i64:{ *:[i64] }:$sbase, 0:{ *:[i32] }, 0:{ *:[i32] })
      GIR_BuildMI, /*InsnID*/0, /*Opcode*/GIMT_Encode2(AMDGPU::S_LOAD_U8_IMM),
      GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/0, // DstI[sdst]
      GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/1, // sbase
      GIR_AddImm8, /*InsnID*/0, /*Imm*/0,
      GIR_AddImm8, /*InsnID*/0, /*Imm*/0,
      GIR_MergeMemOperands, /*InsnID*/0, /*NumInsns*/1, /*MergeInsnID's*/0,
      GIR_ConstrainSelectedInstOperands, /*InsnID*/0,
      GIR_EraseFromParent, /*InsnID*/0,
      // GIR_Coverage, 2419,
      GIR_Done,
    // Label 1066: @69660
    GIM_Try, /*On fail goto*//*Label 1067*/ GIMT_Encode4(69727), // Rule ID 2434 //
      GIM_CheckFeatures, GIMT_Encode2(GIFBS_isGFX12Plus),
      GIM_CheckMemorySizeLessThanLLT, /*MI*/0, /*MMO*/0, /*OpIdx*/0,
      GIM_CheckMemorySizeEqualTo, /*MI*/0, /*MMO*/0, /*Size*/GIMT_Encode4(2),
      GIM_CheckAtomicOrdering, /*MI*/0, /*Order*/(uint8_t)AtomicOrdering::NotAtomic,
      GIM_CheckRegBankForClass, /*MI*/0, /*Op*/0, /*RC*/GIMT_Encode2(AMDGPU::SReg_32_XM0_XEXECRegClassID),
      // MIs[0] sbase
      GIM_CheckPointerToAny, /*MI*/0, /*Op*/1, /*SizeInBits*/64,
      GIM_CheckRegBankForClass, /*MI*/0, /*Op*/1, /*RC*/GIMT_Encode2(AMDGPU::SReg_64RegClassID),
      GIM_CheckCxxInsnPredicate, /*MI*/0, /*FnId*/GIMT_Encode2(GICXXPred_MI_Predicate_smrd_extloadi16),
      // (ld:{ *:[i32] } SReg_64:{ *:[i64] }:$sbase)<<P:Predicate_unindexedload>><<P:Predicate_extload>><<P:Predicate_extloadi16>><<P:Predicate_smrd_extloadi16>>  =>  (S_LOAD_U16_IMM:{ *:[i32] } i64:{ *:[i64] }:$sbase, 0:{ *:[i32] }, 0:{ *:[i32] })
      GIR_BuildMI, /*InsnID*/0, /*Opcode*/GIMT_Encode2(AMDGPU::S_LOAD_U16_IMM),
      GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/0, // DstI[sdst]
      GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/1, // sbase
      GIR_AddImm8, /*InsnID*/0, /*Imm*/0,
      GIR_AddImm8, /*InsnID*/0, /*Imm*/0,
      GIR_MergeMemOperands, /*InsnID*/0, /*NumInsns*/1, /*MergeInsnID's*/0,
      GIR_ConstrainSelectedInstOperands, /*InsnID*/0,
      GIR_EraseFromParent, /*InsnID*/0,
      // GIR_Coverage, 2434,
      GIR_Done,
    // Label 1067: @69727
    GIM_Try, /*On fail goto*//*Label 1068*/ GIMT_Encode4(69784), // Rule ID 2410 //
      GIM_CheckMemorySizeEqualToLLT, /*MI*/0, /*MMO*/0, /*OpIdx*/0,
      GIM_CheckAtomicOrdering, /*MI*/0, /*Order*/(uint8_t)AtomicOrdering::NotAtomic,
      GIM_CheckRegBankForClass, /*MI*/0, /*Op*/0, /*RC*/GIMT_Encode2(AMDGPU::SReg_32_XM0_XEXECRegClassID),
      // MIs[0] sbase
      GIM_CheckPointerToAny, /*MI*/0, /*Op*/1, /*SizeInBits*/64,
      GIM_CheckRegBankForClass, /*MI*/0, /*Op*/1, /*RC*/GIMT_Encode2(AMDGPU::SReg_64RegClassID),
      GIM_CheckCxxInsnPredicate, /*MI*/0, /*FnId*/GIMT_Encode2(GICXXPred_MI_Predicate_smrd_load),
      // (ld:{ *:[i32] } SReg_64:{ *:[i64] }:$sbase)<<P:Predicate_unindexedload>><<P:Predicate_load>><<P:Predicate_smrd_load>>  =>  (S_LOAD_DWORD_IMM:{ *:[i32] } i64:{ *:[i64] }:$sbase, 0:{ *:[i32] }, 0:{ *:[i32] })
      GIR_BuildMI, /*InsnID*/0, /*Opcode*/GIMT_Encode2(AMDGPU::S_LOAD_DWORD_IMM),
      GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/0, // DstI[sdst]
      GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/1, // sbase
      GIR_AddImm8, /*InsnID*/0, /*Imm*/0,
      GIR_AddImm8, /*InsnID*/0, /*Imm*/0,
      GIR_MergeMemOperands, /*InsnID*/0, /*NumInsns*/1, /*MergeInsnID's*/0,
      GIR_ConstrainSelectedInstOperands, /*InsnID*/0,
      GIR_EraseFromParent, /*InsnID*/0,
      // GIR_Coverage, 2410,
      GIR_Done,
    // Label 1068: @69784
    GIM_Try, /*On fail goto*//*Label 1069*/ GIMT_Encode4(69841), // Rule ID 2457 //
      GIM_CheckMemorySizeEqualToLLT, /*MI*/0, /*MMO*/0, /*OpIdx*/0,
      GIM_CheckAtomicOrdering, /*MI*/0, /*Order*/(uint8_t)AtomicOrdering::NotAtomic,
      GIM_CheckRegBankForClass, /*MI*/0, /*Op*/0, /*RC*/GIMT_Encode2(AMDGPU::SReg_32_XM0_XEXECRegClassID),
      // MIs[0] sbase
      GIM_CheckPointerToAny, /*MI*/0, /*Op*/1, /*SizeInBits*/64,
      GIM_CheckRegBankForClass, /*MI*/0, /*Op*/1, /*RC*/GIMT_Encode2(AMDGPU::SReg_64RegClassID),
      GIM_CheckCxxInsnPredicate, /*MI*/0, /*FnId*/GIMT_Encode2(GICXXPred_MI_Predicate_smrd_load),
      // (ld:{ *:[f32] } SReg_64:{ *:[i64] }:$sbase)<<P:Predicate_unindexedload>><<P:Predicate_load>><<P:Predicate_smrd_load>>  =>  (S_LOAD_DWORD_IMM:{ *:[f32] } i64:{ *:[i64] }:$sbase, 0:{ *:[i32] }, 0:{ *:[i32] })
      GIR_BuildMI, /*InsnID*/0, /*Opcode*/GIMT_Encode2(AMDGPU::S_LOAD_DWORD_IMM),
      GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/0, // DstI[sdst]
      GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/1, // sbase
      GIR_AddImm8, /*InsnID*/0, /*Imm*/0,
      GIR_AddImm8, /*InsnID*/0, /*Imm*/0,
      GIR_MergeMemOperands, /*InsnID*/0, /*NumInsns*/1, /*MergeInsnID's*/0,
      GIR_ConstrainSelectedInstOperands, /*InsnID*/0,
      GIR_EraseFromParent, /*InsnID*/0,
      // GIR_Coverage, 2457,
      GIR_Done,
    // Label 1069: @69841
    GIM_Try, /*On fail goto*//*Label 1070*/ GIMT_Encode4(69922), // Rule ID 5352 //
      GIM_CheckFeatures, GIMT_Encode2(GIFBS_DisableFlatScratch_HasUnrestrictedSOffset),
      GIM_CheckMemorySizeLessThanLLT, /*MI*/0, /*MMO*/0, /*OpIdx*/0,
      GIM_CheckMemorySizeEqualTo, /*MI*/0, /*MMO*/0, /*Size*/GIMT_Encode4(1),
      GIM_CheckMemoryAddressSpace, /*MI*/0, /*MMO*/0, /*NumAddrSpace*/1, /*AddrSpace*/5,
      GIM_CheckAtomicOrdering, /*MI*/0, /*Order*/(uint8_t)AtomicOrdering::NotAtomic,
      GIM_CheckRegBankForClass, /*MI*/0, /*Op*/0, /*RC*/GIMT_Encode2(AMDGPU::AV_32RegClassID),
      GIM_CheckPointerToAny, /*MI*/0, /*Op*/1, /*SizeInBits*/0,
      GIM_CheckComplexPattern, /*MI*/0, /*Op*/1, /*Renderer*/GIMT_Encode2(0), GIMT_Encode2(GICP_gi_mubuf_scratch_offset),
      // (ld:{ *:[i32] } (MUBUFScratchOffset:{ *:[iPTR] } v4i32:{ *:[v4i32] }:$srsrc, i32:{ *:[i32] }:$soffset, i32:{ *:[i32] }:$offset))<<P:Predicate_unindexedload>><<P:Predicate_extload>><<P:Predicate_extloadi8>><<P:Predicate_extloadi8_private>>  =>  (BUFFER_LOAD_UBYTE_OFFSET:{ *:[i32] } ?:{ *:[v4i32] }:$srsrc, ?:{ *:[i32] }:$soffset, ?:{ *:[i32] }:$offset, 0:{ *:[i32] }, 0:{ *:[i1] })
      GIR_BuildMI, /*InsnID*/0, /*Opcode*/GIMT_Encode2(AMDGPU::BUFFER_LOAD_UBYTE_OFFSET),
      GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/0, // DstI[vdata]
      GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/0, // srsrc
      GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/1, // soffset
      GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/2, // offset
      GIR_AddImm8, /*InsnID*/0, /*Imm*/0,
      GIR_AddImm8, /*InsnID*/0, /*Imm*/0,
      GIR_MergeMemOperands, /*InsnID*/0, /*NumInsns*/1, /*MergeInsnID's*/0,
      GIR_ConstrainSelectedInstOperands, /*InsnID*/0,
      GIR_EraseFromParent, /*InsnID*/0,
      // GIR_Coverage, 5352,
      GIR_Done,
    // Label 1070: @69922
    GIM_Try, /*On fail goto*//*Label 1071*/ GIMT_Encode4(70003), // Rule ID 5354 //
      GIM_CheckFeatures, GIMT_Encode2(GIFBS_DisableFlatScratch),
      GIM_CheckMemorySizeLessThanLLT, /*MI*/0, /*MMO*/0, /*OpIdx*/0,
      GIM_CheckMemorySizeEqualTo, /*MI*/0, /*MMO*/0, /*Size*/GIMT_Encode4(1),
      GIM_CheckMemoryAddressSpace, /*MI*/0, /*MMO*/0, /*NumAddrSpace*/1, /*AddrSpace*/5,
      GIM_CheckAtomicOrdering, /*MI*/0, /*Order*/(uint8_t)AtomicOrdering::NotAtomic,
      GIM_CheckRegBankForClass, /*MI*/0, /*Op*/0, /*RC*/GIMT_Encode2(AMDGPU::AV_32RegClassID),
      GIM_CheckPointerToAny, /*MI*/0, /*Op*/1, /*SizeInBits*/0,
      GIM_CheckComplexPattern, /*MI*/0, /*Op*/1, /*Renderer*/GIMT_Encode2(0), GIMT_Encode2(GICP_gi_mubuf_scratch_offset),
      // (ld:{ *:[i32] } (MUBUFScratchOffset:{ *:[iPTR] } v4i32:{ *:[v4i32] }:$srsrc, i32:{ *:[i32] }:$soffset, i32:{ *:[i32] }:$offset))<<P:Predicate_unindexedload>><<P:Predicate_extload>><<P:Predicate_extloadi8>><<P:Predicate_extloadi8_private>>  =>  (BUFFER_LOAD_UBYTE_VBUFFER_OFFSET:{ *:[i32] } ?:{ *:[v4i32] }:$srsrc, ?:{ *:[i32] }:$soffset, ?:{ *:[i32] }:$offset, 0:{ *:[i32] }, 0:{ *:[i1] })
      GIR_BuildMI, /*InsnID*/0, /*Opcode*/GIMT_Encode2(AMDGPU::BUFFER_LOAD_UBYTE_VBUFFER_OFFSET),
      GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/0, // DstI[vdata]
      GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/0, // srsrc
      GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/1, // soffset
      GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/2, // offset
      GIR_AddImm8, /*InsnID*/0, /*Imm*/0,
      GIR_AddImm8, /*InsnID*/0, /*Imm*/0,
      GIR_MergeMemOperands, /*InsnID*/0, /*NumInsns*/1, /*MergeInsnID's*/0,
      GIR_ConstrainSelectedInstOperands, /*InsnID*/0,
      GIR_EraseFromParent, /*InsnID*/0,
      // GIR_Coverage, 5354,
      GIR_Done,
    // Label 1071: @70003
    GIM_Try, /*On fail goto*//*Label 1072*/ GIMT_Encode4(70084), // Rule ID 5376 //
      GIM_CheckFeatures, GIMT_Encode2(GIFBS_DisableFlatScratch_HasUnrestrictedSOffset),
      GIM_CheckMemorySizeLessThanLLT, /*MI*/0, /*MMO*/0, /*OpIdx*/0,
      GIM_CheckMemorySizeEqualTo, /*MI*/0, /*MMO*/0, /*Size*/GIMT_Encode4(2),
      GIM_CheckMemoryAddressSpace, /*MI*/0, /*MMO*/0, /*NumAddrSpace*/1, /*AddrSpace*/5,
      GIM_CheckAtomicOrdering, /*MI*/0, /*Order*/(uint8_t)AtomicOrdering::NotAtomic,
      GIM_CheckRegBankForClass, /*MI*/0, /*Op*/0, /*RC*/GIMT_Encode2(AMDGPU::AV_32RegClassID),
      GIM_CheckPointerToAny, /*MI*/0, /*Op*/1, /*SizeInBits*/0,
      GIM_CheckComplexPattern, /*MI*/0, /*Op*/1, /*Renderer*/GIMT_Encode2(0), GIMT_Encode2(GICP_gi_mubuf_scratch_offset),
      // (ld:{ *:[i32] } (MUBUFScratchOffset:{ *:[iPTR] } v4i32:{ *:[v4i32] }:$srsrc, i32:{ *:[i32] }:$soffset, i32:{ *:[i32] }:$offset))<<P:Predicate_unindexedload>><<P:Predicate_extload>><<P:Predicate_extloadi16>><<P:Predicate_extloadi16_private>>  =>  (BUFFER_LOAD_USHORT_OFFSET:{ *:[i32] } ?:{ *:[v4i32] }:$srsrc, ?:{ *:[i32] }:$soffset, ?:{ *:[i32] }:$offset, 0:{ *:[i32] }, 0:{ *:[i1] })
      GIR_BuildMI, /*InsnID*/0, /*Opcode*/GIMT_Encode2(AMDGPU::BUFFER_LOAD_USHORT_OFFSET),
      GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/0, // DstI[vdata]
      GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/0, // srsrc
      GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/1, // soffset
      GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/2, // offset
      GIR_AddImm8, /*InsnID*/0, /*Imm*/0,
      GIR_AddImm8, /*InsnID*/0, /*Imm*/0,
      GIR_MergeMemOperands, /*InsnID*/0, /*NumInsns*/1, /*MergeInsnID's*/0,
      GIR_ConstrainSelectedInstOperands, /*InsnID*/0,
      GIR_EraseFromParent, /*InsnID*/0,
      // GIR_Coverage, 5376,
      GIR_Done,
    // Label 1072: @70084
    GIM_Try, /*On fail goto*//*Label 1073*/ GIMT_Encode4(70165), // Rule ID 5378 //
      GIM_CheckFeatures, GIMT_Encode2(GIFBS_DisableFlatScratch),
      GIM_CheckMemorySizeLessThanLLT, /*MI*/0, /*MMO*/0, /*OpIdx*/0,
      GIM_CheckMemorySizeEqualTo, /*MI*/0, /*MMO*/0, /*Size*/GIMT_Encode4(2),
      GIM_CheckMemoryAddressSpace, /*MI*/0, /*MMO*/0, /*NumAddrSpace*/1, /*AddrSpace*/5,
      GIM_CheckAtomicOrdering, /*MI*/0, /*Order*/(uint8_t)AtomicOrdering::NotAtomic,
      GIM_CheckRegBankForClass, /*MI*/0, /*Op*/0, /*RC*/GIMT_Encode2(AMDGPU::AV_32RegClassID),
      GIM_CheckPointerToAny, /*MI*/0, /*Op*/1, /*SizeInBits*/0,
      GIM_CheckComplexPattern, /*MI*/0, /*Op*/1, /*Renderer*/GIMT_Encode2(0), GIMT_Encode2(GICP_gi_mubuf_scratch_offset),
      // (ld:{ *:[i32] } (MUBUFScratchOffset:{ *:[iPTR] } v4i32:{ *:[v4i32] }:$srsrc, i32:{ *:[i32] }:$soffset, i32:{ *:[i32] }:$offset))<<P:Predicate_unindexedload>><<P:Predicate_extload>><<P:Predicate_extloadi16>><<P:Predicate_extloadi16_private>>  =>  (BUFFER_LOAD_USHORT_VBUFFER_OFFSET:{ *:[i32] } ?:{ *:[v4i32] }:$srsrc, ?:{ *:[i32] }:$soffset, ?:{ *:[i32] }:$offset, 0:{ *:[i32] }, 0:{ *:[i1] })
      GIR_BuildMI, /*InsnID*/0, /*Opcode*/GIMT_Encode2(AMDGPU::BUFFER_LOAD_USHORT_VBUFFER_OFFSET),
      GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/0, // DstI[vdata]
      GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/0, // srsrc
      GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/1, // soffset
      GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/2, // offset
      GIR_AddImm8, /*InsnID*/0, /*Imm*/0,
      GIR_AddImm8, /*InsnID*/0, /*Imm*/0,
      GIR_MergeMemOperands, /*InsnID*/0, /*NumInsns*/1, /*MergeInsnID's*/0,
      GIR_ConstrainSelectedInstOperands, /*InsnID*/0,
      GIR_EraseFromParent, /*InsnID*/0,
      // GIR_Coverage, 5378,
      GIR_Done,
    // Label 1073: @70165
    GIM_Try, /*On fail goto*//*Label 1074*/ GIMT_Encode4(70235), // Rule ID 5388 //
      GIM_CheckFeatures, GIMT_Encode2(GIFBS_DisableFlatScratch_HasUnrestrictedSOffset),
      GIM_CheckMemoryAddressSpace, /*MI*/0, /*MMO*/0, /*NumAddrSpace*/1, /*AddrSpace*/5,
      GIM_CheckAtomicOrdering, /*MI*/0, /*Order*/(uint8_t)AtomicOrdering::NotAtomic,
      GIM_CheckRegBankForClass, /*MI*/0, /*Op*/0, /*RC*/GIMT_Encode2(AMDGPU::AV_32RegClassID),
      GIM_CheckPointerToAny, /*MI*/0, /*Op*/1, /*SizeInBits*/0,
      GIM_CheckComplexPattern, /*MI*/0, /*Op*/1, /*Renderer*/GIMT_Encode2(0), GIMT_Encode2(GICP_gi_mubuf_scratch_offset),
      // (ld:{ *:[i32] } (MUBUFScratchOffset:{ *:[iPTR] } v4i32:{ *:[v4i32] }:$srsrc, i32:{ *:[i32] }:$soffset, i32:{ *:[i32] }:$offset))<<P:Predicate_unindexedload>><<P:Predicate_load_private>>  =>  (BUFFER_LOAD_DWORD_OFFSET:{ *:[i32] } ?:{ *:[v4i32] }:$srsrc, ?:{ *:[i32] }:$soffset, ?:{ *:[i32] }:$offset, 0:{ *:[i32] }, 0:{ *:[i1] })
      GIR_BuildMI, /*InsnID*/0, /*Opcode*/GIMT_Encode2(AMDGPU::BUFFER_LOAD_DWORD_OFFSET),
      GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/0, // DstI[vdata]
      GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/0, // srsrc
      GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/1, // soffset
      GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/2, // offset
      GIR_AddImm8, /*InsnID*/0, /*Imm*/0,
      GIR_AddImm8, /*InsnID*/0, /*Imm*/0,
      GIR_MergeMemOperands, /*InsnID*/0, /*NumInsns*/1, /*MergeInsnID's*/0,
      GIR_ConstrainSelectedInstOperands, /*InsnID*/0,
      GIR_EraseFromParent, /*InsnID*/0,
      // GIR_Coverage, 5388,
      GIR_Done,
    // Label 1074: @70235
    GIM_Try, /*On fail goto*//*Label 1075*/ GIMT_Encode4(70305), // Rule ID 5390 //
      GIM_CheckFeatures, GIMT_Encode2(GIFBS_DisableFlatScratch),
      GIM_CheckMemoryAddressSpace, /*MI*/0, /*MMO*/0, /*NumAddrSpace*/1, /*AddrSpace*/5,
      GIM_CheckAtomicOrdering, /*MI*/0, /*Order*/(uint8_t)AtomicOrdering::NotAtomic,
      GIM_CheckRegBankForClass, /*MI*/0, /*Op*/0, /*RC*/GIMT_Encode2(AMDGPU::AV_32RegClassID),
      GIM_CheckPointerToAny, /*MI*/0, /*Op*/1, /*SizeInBits*/0,
      GIM_CheckComplexPattern, /*MI*/0, /*Op*/1, /*Renderer*/GIMT_Encode2(0), GIMT_Encode2(GICP_gi_mubuf_scratch_offset),
      // (ld:{ *:[i32] } (MUBUFScratchOffset:{ *:[iPTR] } v4i32:{ *:[v4i32] }:$srsrc, i32:{ *:[i32] }:$soffset, i32:{ *:[i32] }:$offset))<<P:Predicate_unindexedload>><<P:Predicate_load_private>>  =>  (BUFFER_LOAD_DWORD_VBUFFER_OFFSET:{ *:[i32] } ?:{ *:[v4i32] }:$srsrc, ?:{ *:[i32] }:$soffset, ?:{ *:[i32] }:$offset, 0:{ *:[i32] }, 0:{ *:[i1] })
      GIR_BuildMI, /*InsnID*/0, /*Opcode*/GIMT_Encode2(AMDGPU::BUFFER_LOAD_DWORD_VBUFFER_OFFSET),
      GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/0, // DstI[vdata]
      GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/0, // srsrc
      GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/1, // soffset
      GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/2, // offset
      GIR_AddImm8, /*InsnID*/0, /*Imm*/0,
      GIR_AddImm8, /*InsnID*/0, /*Imm*/0,
      GIR_MergeMemOperands, /*InsnID*/0, /*NumInsns*/1, /*MergeInsnID's*/0,
      GIR_ConstrainSelectedInstOperands, /*InsnID*/0,
      GIR_EraseFromParent, /*InsnID*/0,
      // GIR_Coverage, 5390,
      GIR_Done,
    // Label 1075: @70305
    GIM_Try, /*On fail goto*//*Label 1076*/ GIMT_Encode4(70375), // Rule ID 5392 //
      GIM_CheckFeatures, GIMT_Encode2(GIFBS_DisableFlatScratch_HasUnrestrictedSOffset),
      GIM_CheckMemoryAddressSpace, /*MI*/0, /*MMO*/0, /*NumAddrSpace*/1, /*AddrSpace*/5,
      GIM_CheckAtomicOrdering, /*MI*/0, /*Order*/(uint8_t)AtomicOrdering::NotAtomic,
      GIM_CheckRegBankForClass, /*MI*/0, /*Op*/0, /*RC*/GIMT_Encode2(AMDGPU::AV_32RegClassID),
      GIM_CheckPointerToAny, /*MI*/0, /*Op*/1, /*SizeInBits*/0,
      GIM_CheckComplexPattern, /*MI*/0, /*Op*/1, /*Renderer*/GIMT_Encode2(0), GIMT_Encode2(GICP_gi_mubuf_scratch_offset),
      // (ld:{ *:[f32] } (MUBUFScratchOffset:{ *:[iPTR] } v4i32:{ *:[v4i32] }:$srsrc, i32:{ *:[i32] }:$soffset, i32:{ *:[i32] }:$offset))<<P:Predicate_unindexedload>><<P:Predicate_load_private>>  =>  (BUFFER_LOAD_DWORD_OFFSET:{ *:[f32] } ?:{ *:[v4i32] }:$srsrc, ?:{ *:[i32] }:$soffset, ?:{ *:[i32] }:$offset, 0:{ *:[i32] }, 0:{ *:[i1] })
      GIR_BuildMI, /*InsnID*/0, /*Opcode*/GIMT_Encode2(AMDGPU::BUFFER_LOAD_DWORD_OFFSET),
      GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/0, // DstI[vdata]
      GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/0, // srsrc
      GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/1, // soffset
      GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/2, // offset
      GIR_AddImm8, /*InsnID*/0, /*Imm*/0,
      GIR_AddImm8, /*InsnID*/0, /*Imm*/0,
      GIR_MergeMemOperands, /*InsnID*/0, /*NumInsns*/1, /*MergeInsnID's*/0,
      GIR_ConstrainSelectedInstOperands, /*InsnID*/0,
      GIR_EraseFromParent, /*InsnID*/0,
      // GIR_Coverage, 5392,
      GIR_Done,
    // Label 1076: @70375
    GIM_Try, /*On fail goto*//*Label 1077*/ GIMT_Encode4(70445), // Rule ID 5394 //
      GIM_CheckFeatures, GIMT_Encode2(GIFBS_DisableFlatScratch),
      GIM_CheckMemoryAddressSpace, /*MI*/0, /*MMO*/0, /*NumAddrSpace*/1, /*AddrSpace*/5,
      GIM_CheckAtomicOrdering, /*MI*/0, /*Order*/(uint8_t)AtomicOrdering::NotAtomic,
      GIM_CheckRegBankForClass, /*MI*/0, /*Op*/0, /*RC*/GIMT_Encode2(AMDGPU::AV_32RegClassID),
      GIM_CheckPointerToAny, /*MI*/0, /*Op*/1, /*SizeInBits*/0,
      GIM_CheckComplexPattern, /*MI*/0, /*Op*/1, /*Renderer*/GIMT_Encode2(0), GIMT_Encode2(GICP_gi_mubuf_scratch_offset),
      // (ld:{ *:[f32] } (MUBUFScratchOffset:{ *:[iPTR] } v4i32:{ *:[v4i32] }:$srsrc, i32:{ *:[i32] }:$soffset, i32:{ *:[i32] }:$offset))<<P:Predicate_unindexedload>><<P:Predicate_load_private>>  =>  (BUFFER_LOAD_DWORD_VBUFFER_OFFSET:{ *:[f32] } ?:{ *:[v4i32] }:$srsrc, ?:{ *:[i32] }:$soffset, ?:{ *:[i32] }:$offset, 0:{ *:[i32] }, 0:{ *:[i1] })
      GIR_BuildMI, /*InsnID*/0, /*Opcode*/GIMT_Encode2(AMDGPU::BUFFER_LOAD_DWORD_VBUFFER_OFFSET),
      GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/0, // DstI[vdata]
      GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/0, // srsrc
      GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/1, // soffset
      GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/2, // offset
      GIR_AddImm8, /*InsnID*/0, /*Imm*/0,
      GIR_AddImm8, /*InsnID*/0, /*Imm*/0,
      GIR_MergeMemOperands, /*InsnID*/0, /*NumInsns*/1, /*MergeInsnID's*/0,
      GIR_ConstrainSelectedInstOperands, /*InsnID*/0,
      GIR_EraseFromParent, /*InsnID*/0,
      // GIR_Coverage, 5394,
      GIR_Done,
    // Label 1077: @70445
    GIM_Try, /*On fail goto*//*Label 1078*/ GIMT_Encode4(70523), // Rule ID 2961 //
      GIM_CheckFeatures, GIMT_Encode2(GIFBS_EnableFlatScratch_HasFlatScratchInsts_HasFlatScratchSVSMode),
      GIM_CheckMemorySizeLessThanLLT, /*MI*/0, /*MMO*/0, /*OpIdx*/0,
      GIM_CheckMemorySizeEqualTo, /*MI*/0, /*MMO*/0, /*Size*/GIMT_Encode4(1),
      GIM_CheckMemoryAddressSpace, /*MI*/0, /*MMO*/0, /*NumAddrSpace*/1, /*AddrSpace*/5,
      GIM_CheckAtomicOrdering, /*MI*/0, /*Order*/(uint8_t)AtomicOrdering::NotAtomic,
      GIM_CheckRegBankForClass, /*MI*/0, /*Op*/0, /*RC*/GIMT_Encode2(AMDGPU::AV_32RegClassID),
      GIM_CheckPointerToAny, /*MI*/0, /*Op*/1, /*SizeInBits*/0,
      GIM_CheckComplexPattern, /*MI*/0, /*Op*/1, /*Renderer*/GIMT_Encode2(0), GIMT_Encode2(GICP_gi_flat_scratch_svaddr),
      // (ld:{ *:[i32] } (ScratchSVAddr:{ *:[iPTR] } VGPR_32:{ *:[i32] }:$vaddr, SGPR_32:{ *:[i32] }:$saddr, i32:{ *:[i32] }:$offset))<<P:Predicate_unindexedload>><<P:Predicate_extload>><<P:Predicate_extloadi8>><<P:Predicate_extloadi8_private>>  =>  (SCRATCH_LOAD_UBYTE_SVS:{ *:[i32] } ?:{ *:[i32] }:$vaddr, ?:{ *:[i32] }:$saddr, ?:{ *:[i32] }:$offset, 0:{ *:[i32] })
      GIR_BuildMI, /*InsnID*/0, /*Opcode*/GIMT_Encode2(AMDGPU::SCRATCH_LOAD_UBYTE_SVS),
      GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/0, // DstI[vdst]
      GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/0, // vaddr
      GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/1, // saddr
      GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/2, // offset
      GIR_AddImm8, /*InsnID*/0, /*Imm*/0,
      GIR_MergeMemOperands, /*InsnID*/0, /*NumInsns*/1, /*MergeInsnID's*/0,
      GIR_ConstrainSelectedInstOperands, /*InsnID*/0,
      GIR_EraseFromParent, /*InsnID*/0,
      // GIR_Coverage, 2961,
      GIR_Done,
    // Label 1078: @70523
    GIM_Try, /*On fail goto*//*Label 1079*/ GIMT_Encode4(70601), // Rule ID 3421 //
      GIM_CheckFeatures, GIMT_Encode2(GIFBS_EnableFlatScratch_HasFlatScratchInsts_HasFlatScratchSVSMode),
      GIM_CheckMemorySizeLessThanLLT, /*MI*/0, /*MMO*/0, /*OpIdx*/0,
      GIM_CheckMemorySizeEqualTo, /*MI*/0, /*MMO*/0, /*Size*/GIMT_Encode4(2),
      GIM_CheckMemoryAddressSpace, /*MI*/0, /*MMO*/0, /*NumAddrSpace*/1, /*AddrSpace*/5,
      GIM_CheckAtomicOrdering, /*MI*/0, /*Order*/(uint8_t)AtomicOrdering::NotAtomic,
      GIM_CheckRegBankForClass, /*MI*/0, /*Op*/0, /*RC*/GIMT_Encode2(AMDGPU::AV_32RegClassID),
      GIM_CheckPointerToAny, /*MI*/0, /*Op*/1, /*SizeInBits*/0,
      GIM_CheckComplexPattern, /*MI*/0, /*Op*/1, /*Renderer*/GIMT_Encode2(0), GIMT_Encode2(GICP_gi_flat_scratch_svaddr),
      // (ld:{ *:[i32] } (ScratchSVAddr:{ *:[iPTR] } VGPR_32:{ *:[i32] }:$vaddr, SGPR_32:{ *:[i32] }:$saddr, i32:{ *:[i32] }:$offset))<<P:Predicate_unindexedload>><<P:Predicate_extload>><<P:Predicate_extloadi16>><<P:Predicate_extloadi16_private>>  =>  (SCRATCH_LOAD_USHORT_SVS:{ *:[i32] } ?:{ *:[i32] }:$vaddr, ?:{ *:[i32] }:$saddr, ?:{ *:[i32] }:$offset, 0:{ *:[i32] })
      GIR_BuildMI, /*InsnID*/0, /*Opcode*/GIMT_Encode2(AMDGPU::SCRATCH_LOAD_USHORT_SVS),
      GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/0, // DstI[vdst]
      GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/0, // vaddr
      GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/1, // saddr
      GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/2, // offset
      GIR_AddImm8, /*InsnID*/0, /*Imm*/0,
      GIR_MergeMemOperands, /*InsnID*/0, /*NumInsns*/1, /*MergeInsnID's*/0,
      GIR_ConstrainSelectedInstOperands, /*InsnID*/0,
      GIR_EraseFromParent, /*InsnID*/0,
      // GIR_Coverage, 3421,
      GIR_Done,
    // Label 1079: @70601
    GIM_Try, /*On fail goto*//*Label 1080*/ GIMT_Encode4(70668), // Rule ID 3433 //
      GIM_CheckFeatures, GIMT_Encode2(GIFBS_EnableFlatScratch_HasFlatScratchInsts_HasFlatScratchSVSMode),
      GIM_CheckMemoryAddressSpace, /*MI*/0, /*MMO*/0, /*NumAddrSpace*/1, /*AddrSpace*/5,
      GIM_CheckAtomicOrdering, /*MI*/0, /*Order*/(uint8_t)AtomicOrdering::NotAtomic,
      GIM_CheckRegBankForClass, /*MI*/0, /*Op*/0, /*RC*/GIMT_Encode2(AMDGPU::AV_32RegClassID),
      GIM_CheckPointerToAny, /*MI*/0, /*Op*/1, /*SizeInBits*/0,
      GIM_CheckComplexPattern, /*MI*/0, /*Op*/1, /*Renderer*/GIMT_Encode2(0), GIMT_Encode2(GICP_gi_flat_scratch_svaddr),
      // (ld:{ *:[i32] } (ScratchSVAddr:{ *:[iPTR] } VGPR_32:{ *:[i32] }:$vaddr, SGPR_32:{ *:[i32] }:$saddr, i32:{ *:[i32] }:$offset))<<P:Predicate_unindexedload>><<P:Predicate_load_private>>  =>  (SCRATCH_LOAD_DWORD_SVS:{ *:[i32] } ?:{ *:[i32] }:$vaddr, ?:{ *:[i32] }:$saddr, ?:{ *:[i32] }:$offset, 0:{ *:[i32] })
      GIR_BuildMI, /*InsnID*/0, /*Opcode*/GIMT_Encode2(AMDGPU::SCRATCH_LOAD_DWORD_SVS),
      GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/0, // DstI[vdst]
      GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/0, // vaddr
      GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/1, // saddr
      GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/2, // offset
      GIR_AddImm8, /*InsnID*/0, /*Imm*/0,
      GIR_MergeMemOperands, /*InsnID*/0, /*NumInsns*/1, /*MergeInsnID's*/0,
      GIR_ConstrainSelectedInstOperands, /*InsnID*/0,
      GIR_EraseFromParent, /*InsnID*/0,
      // GIR_Coverage, 3433,
      GIR_Done,
    // Label 1080: @70668
    GIM_Try, /*On fail goto*//*Label 1081*/ GIMT_Encode4(70735), // Rule ID 3436 //
      GIM_CheckFeatures, GIMT_Encode2(GIFBS_EnableFlatScratch_HasFlatScratchInsts_HasFlatScratchSVSMode),
      GIM_CheckMemoryAddressSpace, /*MI*/0, /*MMO*/0, /*NumAddrSpace*/1, /*AddrSpace*/5,
      GIM_CheckAtomicOrdering, /*MI*/0, /*Order*/(uint8_t)AtomicOrdering::NotAtomic,
      GIM_CheckRegBankForClass, /*MI*/0, /*Op*/0, /*RC*/GIMT_Encode2(AMDGPU::AV_32RegClassID),
      GIM_CheckPointerToAny, /*MI*/0, /*Op*/1, /*SizeInBits*/0,
      GIM_CheckComplexPattern, /*MI*/0, /*Op*/1, /*Renderer*/GIMT_Encode2(0), GIMT_Encode2(GICP_gi_flat_scratch_svaddr),
      // (ld:{ *:[f32] } (ScratchSVAddr:{ *:[iPTR] } VGPR_32:{ *:[i32] }:$vaddr, SGPR_32:{ *:[i32] }:$saddr, i32:{ *:[i32] }:$offset))<<P:Predicate_unindexedload>><<P:Predicate_load_private>>  =>  (SCRATCH_LOAD_DWORD_SVS:{ *:[f32] } ?:{ *:[i32] }:$vaddr, ?:{ *:[i32] }:$saddr, ?:{ *:[i32] }:$offset, 0:{ *:[i32] })
      GIR_BuildMI, /*InsnID*/0, /*Opcode*/GIMT_Encode2(AMDGPU::SCRATCH_LOAD_DWORD_SVS),
      GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/0, // DstI[vdst]
      GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/0, // vaddr
      GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/1, // saddr
      GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/2, // offset
      GIR_AddImm8, /*InsnID*/0, /*Imm*/0,
      GIR_MergeMemOperands, /*InsnID*/0, /*NumInsns*/1, /*MergeInsnID's*/0,
      GIR_ConstrainSelectedInstOperands, /*InsnID*/0,
      GIR_EraseFromParent, /*InsnID*/0,
      // GIR_Coverage, 3436,
      GIR_Done,
    // Label 1081: @70735
    GIM_Try, /*On fail goto*//*Label 1082*/ GIMT_Encode4(70808), // Rule ID 2960 //
      GIM_CheckFeatures, GIMT_Encode2(GIFBS_EnableFlatScratch_HasFlatScratchInsts),
      GIM_CheckMemorySizeLessThanLLT, /*MI*/0, /*MMO*/0, /*OpIdx*/0,
      GIM_CheckMemorySizeEqualTo, /*MI*/0, /*MMO*/0, /*Size*/GIMT_Encode4(1),
      GIM_CheckMemoryAddressSpace, /*MI*/0, /*MMO*/0, /*NumAddrSpace*/1, /*AddrSpace*/5,
      GIM_CheckAtomicOrdering, /*MI*/0, /*Order*/(uint8_t)AtomicOrdering::NotAtomic,
      GIM_CheckRegBankForClass, /*MI*/0, /*Op*/0, /*RC*/GIMT_Encode2(AMDGPU::AV_32RegClassID),
      GIM_CheckPointerToAny, /*MI*/0, /*Op*/1, /*SizeInBits*/0,
      GIM_CheckComplexPattern, /*MI*/0, /*Op*/1, /*Renderer*/GIMT_Encode2(0), GIMT_Encode2(GICP_gi_flat_scratch_saddr),
      // (ld:{ *:[i32] } (ScratchSAddr:{ *:[iPTR] } SGPR_32:{ *:[i32] }:$saddr, i32:{ *:[i32] }:$offset))<<P:Predicate_unindexedload>><<P:Predicate_extload>><<P:Predicate_extloadi8>><<P:Predicate_extloadi8_private>>  =>  (SCRATCH_LOAD_UBYTE_SADDR:{ *:[i32] } ?:{ *:[i32] }:$saddr, ?:{ *:[i32] }:$offset)
      GIR_BuildMI, /*InsnID*/0, /*Opcode*/GIMT_Encode2(AMDGPU::SCRATCH_LOAD_UBYTE_SADDR),
      GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/0, // DstI[vdst]
      GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/0, // saddr
      GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/1, // offset
      GIR_AddImm8, /*InsnID*/0, /*Imm*/0,
      GIR_MergeMemOperands, /*InsnID*/0, /*NumInsns*/1, /*MergeInsnID's*/0,
      GIR_ConstrainSelectedInstOperands, /*InsnID*/0,
      GIR_EraseFromParent, /*InsnID*/0,
      // GIR_Coverage, 2960,
      GIR_Done,
    // Label 1082: @70808
    GIM_Try, /*On fail goto*//*Label 1083*/ GIMT_Encode4(70881), // Rule ID 3420 //
      GIM_CheckFeatures, GIMT_Encode2(GIFBS_EnableFlatScratch_HasFlatScratchInsts),
      GIM_CheckMemorySizeLessThanLLT, /*MI*/0, /*MMO*/0, /*OpIdx*/0,
      GIM_CheckMemorySizeEqualTo, /*MI*/0, /*MMO*/0, /*Size*/GIMT_Encode4(2),
      GIM_CheckMemoryAddressSpace, /*MI*/0, /*MMO*/0, /*NumAddrSpace*/1, /*AddrSpace*/5,
      GIM_CheckAtomicOrdering, /*MI*/0, /*Order*/(uint8_t)AtomicOrdering::NotAtomic,
      GIM_CheckRegBankForClass, /*MI*/0, /*Op*/0, /*RC*/GIMT_Encode2(AMDGPU::AV_32RegClassID),
      GIM_CheckPointerToAny, /*MI*/0, /*Op*/1, /*SizeInBits*/0,
      GIM_CheckComplexPattern, /*MI*/0, /*Op*/1, /*Renderer*/GIMT_Encode2(0), GIMT_Encode2(GICP_gi_flat_scratch_saddr),
      // (ld:{ *:[i32] } (ScratchSAddr:{ *:[iPTR] } SGPR_32:{ *:[i32] }:$saddr, i32:{ *:[i32] }:$offset))<<P:Predicate_unindexedload>><<P:Predicate_extload>><<P:Predicate_extloadi16>><<P:Predicate_extloadi16_private>>  =>  (SCRATCH_LOAD_USHORT_SADDR:{ *:[i32] } ?:{ *:[i32] }:$saddr, ?:{ *:[i32] }:$offset)
      GIR_BuildMI, /*InsnID*/0, /*Opcode*/GIMT_Encode2(AMDGPU::SCRATCH_LOAD_USHORT_SADDR),
      GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/0, // DstI[vdst]
      GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/0, // saddr
      GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/1, // offset
      GIR_AddImm8, /*InsnID*/0, /*Imm*/0,
      GIR_MergeMemOperands, /*InsnID*/0, /*NumInsns*/1, /*MergeInsnID's*/0,
      GIR_ConstrainSelectedInstOperands, /*InsnID*/0,
      GIR_EraseFromParent, /*InsnID*/0,
      // GIR_Coverage, 3420,
      GIR_Done,
    // Label 1083: @70881
    GIM_Try, /*On fail goto*//*Label 1084*/ GIMT_Encode4(70943), // Rule ID 3432 //
      GIM_CheckFeatures, GIMT_Encode2(GIFBS_EnableFlatScratch_HasFlatScratchInsts),
      GIM_CheckMemoryAddressSpace, /*MI*/0, /*MMO*/0, /*NumAddrSpace*/1, /*AddrSpace*/5,
      GIM_CheckAtomicOrdering, /*MI*/0, /*Order*/(uint8_t)AtomicOrdering::NotAtomic,
      GIM_CheckRegBankForClass, /*MI*/0, /*Op*/0, /*RC*/GIMT_Encode2(AMDGPU::AV_32RegClassID),
      GIM_CheckPointerToAny, /*MI*/0, /*Op*/1, /*SizeInBits*/0,
      GIM_CheckComplexPattern, /*MI*/0, /*Op*/1, /*Renderer*/GIMT_Encode2(0), GIMT_Encode2(GICP_gi_flat_scratch_saddr),
      // (ld:{ *:[i32] } (ScratchSAddr:{ *:[iPTR] } SGPR_32:{ *:[i32] }:$saddr, i32:{ *:[i32] }:$offset))<<P:Predicate_unindexedload>><<P:Predicate_load_private>>  =>  (SCRATCH_LOAD_DWORD_SADDR:{ *:[i32] } ?:{ *:[i32] }:$saddr, ?:{ *:[i32] }:$offset)
      GIR_BuildMI, /*InsnID*/0, /*Opcode*/GIMT_Encode2(AMDGPU::SCRATCH_LOAD_DWORD_SADDR),
      GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/0, // DstI[vdst]
      GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/0, // saddr
      GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/1, // offset
      GIR_AddImm8, /*InsnID*/0, /*Imm*/0,
      GIR_MergeMemOperands, /*InsnID*/0, /*NumInsns*/1, /*MergeInsnID's*/0,
      GIR_ConstrainSelectedInstOperands, /*InsnID*/0,
      GIR_EraseFromParent, /*InsnID*/0,
      // GIR_Coverage, 3432,
      GIR_Done,
    // Label 1084: @70943
    GIM_Try, /*On fail goto*//*Label 1085*/ GIMT_Encode4(71005), // Rule ID 3435 //
      GIM_CheckFeatures, GIMT_Encode2(GIFBS_EnableFlatScratch_HasFlatScratchInsts),
      GIM_CheckMemoryAddressSpace, /*MI*/0, /*MMO*/0, /*NumAddrSpace*/1, /*AddrSpace*/5,
      GIM_CheckAtomicOrdering, /*MI*/0, /*Order*/(uint8_t)AtomicOrdering::NotAtomic,
      GIM_CheckRegBankForClass, /*MI*/0, /*Op*/0, /*RC*/GIMT_Encode2(AMDGPU::AV_32RegClassID),
      GIM_CheckPointerToAny, /*MI*/0, /*Op*/1, /*SizeInBits*/0,
      GIM_CheckComplexPattern, /*MI*/0, /*Op*/1, /*Renderer*/GIMT_Encode2(0), GIMT_Encode2(GICP_gi_flat_scratch_saddr),
      // (ld:{ *:[f32] } (ScratchSAddr:{ *:[iPTR] } SGPR_32:{ *:[i32] }:$saddr, i32:{ *:[i32] }:$offset))<<P:Predicate_unindexedload>><<P:Predicate_load_private>>  =>  (SCRATCH_LOAD_DWORD_SADDR:{ *:[f32] } ?:{ *:[i32] }:$saddr, ?:{ *:[i32] }:$offset)
      GIR_BuildMI, /*InsnID*/0, /*Opcode*/GIMT_Encode2(AMDGPU::SCRATCH_LOAD_DWORD_SADDR),
      GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/0, // DstI[vdst]
      GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/0, // saddr
      GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/1, // offset
      GIR_AddImm8, /*InsnID*/0, /*Imm*/0,
      GIR_MergeMemOperands, /*InsnID*/0, /*NumInsns*/1, /*MergeInsnID's*/0,
      GIR_ConstrainSelectedInstOperands, /*InsnID*/0,
      GIR_EraseFromParent, /*InsnID*/0,
      // GIR_Coverage, 3435,
      GIR_Done,
    // Label 1085: @71005
    GIM_Try, /*On fail goto*//*Label 1086*/ GIMT_Encode4(71078), // Rule ID 2959 //
      GIM_CheckFeatures, GIMT_Encode2(GIFBS_EnableFlatScratch_HasFlatScratchInsts),
      GIM_CheckMemorySizeLessThanLLT, /*MI*/0, /*MMO*/0, /*OpIdx*/0,
      GIM_CheckMemorySizeEqualTo, /*MI*/0, /*MMO*/0, /*Size*/GIMT_Encode4(1),
      GIM_CheckMemoryAddressSpace, /*MI*/0, /*MMO*/0, /*NumAddrSpace*/1, /*AddrSpace*/5,
      GIM_CheckAtomicOrdering, /*MI*/0, /*Order*/(uint8_t)AtomicOrdering::NotAtomic,
      GIM_CheckRegBankForClass, /*MI*/0, /*Op*/0, /*RC*/GIMT_Encode2(AMDGPU::AV_32RegClassID),
      GIM_CheckPointerToAny, /*MI*/0, /*Op*/1, /*SizeInBits*/0,
      GIM_CheckComplexPattern, /*MI*/0, /*Op*/1, /*Renderer*/GIMT_Encode2(0), GIMT_Encode2(GICP_gi_flat_scratch_offset),
      // (ld:{ *:[i32] } (ScratchOffset:{ *:[iPTR] } VGPR_32:{ *:[i32] }:$vaddr, i32:{ *:[i32] }:$offset))<<P:Predicate_unindexedload>><<P:Predicate_extload>><<P:Predicate_extloadi8>><<P:Predicate_extloadi8_private>>  =>  (SCRATCH_LOAD_UBYTE:{ *:[i32] } ?:{ *:[i32] }:$vaddr, ?:{ *:[i32] }:$offset)
      GIR_BuildMI, /*InsnID*/0, /*Opcode*/GIMT_Encode2(AMDGPU::SCRATCH_LOAD_UBYTE),
      GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/0, // DstI[vdst]
      GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/0, // vaddr
      GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/1, // offset
      GIR_AddImm8, /*InsnID*/0, /*Imm*/0,
      GIR_MergeMemOperands, /*InsnID*/0, /*NumInsns*/1, /*MergeInsnID's*/0,
      GIR_ConstrainSelectedInstOperands, /*InsnID*/0,
      GIR_EraseFromParent, /*InsnID*/0,
      // GIR_Coverage, 2959,
      GIR_Done,
    // Label 1086: @71078
    GIM_Try, /*On fail goto*//*Label 1087*/ GIMT_Encode4(71151), // Rule ID 3419 //
      GIM_CheckFeatures, GIMT_Encode2(GIFBS_EnableFlatScratch_HasFlatScratchInsts),
      GIM_CheckMemorySizeLessThanLLT, /*MI*/0, /*MMO*/0, /*OpIdx*/0,
      GIM_CheckMemorySizeEqualTo, /*MI*/0, /*MMO*/0, /*Size*/GIMT_Encode4(2),
      GIM_CheckMemoryAddressSpace, /*MI*/0, /*MMO*/0, /*NumAddrSpace*/1, /*AddrSpace*/5,
      GIM_CheckAtomicOrdering, /*MI*/0, /*Order*/(uint8_t)AtomicOrdering::NotAtomic,
      GIM_CheckRegBankForClass, /*MI*/0, /*Op*/0, /*RC*/GIMT_Encode2(AMDGPU::AV_32RegClassID),
      GIM_CheckPointerToAny, /*MI*/0, /*Op*/1, /*SizeInBits*/0,
      GIM_CheckComplexPattern, /*MI*/0, /*Op*/1, /*Renderer*/GIMT_Encode2(0), GIMT_Encode2(GICP_gi_flat_scratch_offset),
      // (ld:{ *:[i32] } (ScratchOffset:{ *:[iPTR] } VGPR_32:{ *:[i32] }:$vaddr, i32:{ *:[i32] }:$offset))<<P:Predicate_unindexedload>><<P:Predicate_extload>><<P:Predicate_extloadi16>><<P:Predicate_extloadi16_private>>  =>  (SCRATCH_LOAD_USHORT:{ *:[i32] } ?:{ *:[i32] }:$vaddr, ?:{ *:[i32] }:$offset)
      GIR_BuildMI, /*InsnID*/0, /*Opcode*/GIMT_Encode2(AMDGPU::SCRATCH_LOAD_USHORT),
      GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/0, // DstI[vdst]
      GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/0, // vaddr
      GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/1, // offset
      GIR_AddImm8, /*InsnID*/0, /*Imm*/0,
      GIR_MergeMemOperands, /*InsnID*/0, /*NumInsns*/1, /*MergeInsnID's*/0,
      GIR_ConstrainSelectedInstOperands, /*InsnID*/0,
      GIR_EraseFromParent, /*InsnID*/0,
      // GIR_Coverage, 3419,
      GIR_Done,
    // Label 1087: @71151
    GIM_Try, /*On fail goto*//*Label 1088*/ GIMT_Encode4(71213), // Rule ID 3431 //
      GIM_CheckFeatures, GIMT_Encode2(GIFBS_EnableFlatScratch_HasFlatScratchInsts),
      GIM_CheckMemoryAddressSpace, /*MI*/0, /*MMO*/0, /*NumAddrSpace*/1, /*AddrSpace*/5,
      GIM_CheckAtomicOrdering, /*MI*/0, /*Order*/(uint8_t)AtomicOrdering::NotAtomic,
      GIM_CheckRegBankForClass, /*MI*/0, /*Op*/0, /*RC*/GIMT_Encode2(AMDGPU::AV_32RegClassID),
      GIM_CheckPointerToAny, /*MI*/0, /*Op*/1, /*SizeInBits*/0,
      GIM_CheckComplexPattern, /*MI*/0, /*Op*/1, /*Renderer*/GIMT_Encode2(0), GIMT_Encode2(GICP_gi_flat_scratch_offset),
      // (ld:{ *:[i32] } (ScratchOffset:{ *:[iPTR] } VGPR_32:{ *:[i32] }:$vaddr, i32:{ *:[i32] }:$offset))<<P:Predicate_unindexedload>><<P:Predicate_load_private>>  =>  (SCRATCH_LOAD_DWORD:{ *:[i32] } ?:{ *:[i32] }:$vaddr, ?:{ *:[i32] }:$offset)
      GIR_BuildMI, /*InsnID*/0, /*Opcode*/GIMT_Encode2(AMDGPU::SCRATCH_LOAD_DWORD),
      GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/0, // DstI[vdst]
      GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/0, // vaddr
      GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/1, // offset
      GIR_AddImm8, /*InsnID*/0, /*Imm*/0,
      GIR_MergeMemOperands, /*InsnID*/0, /*NumInsns*/1, /*MergeInsnID's*/0,
      GIR_ConstrainSelectedInstOperands, /*InsnID*/0,
      GIR_EraseFromParent, /*InsnID*/0,
      // GIR_Coverage, 3431,
      GIR_Done,
    // Label 1088: @71213
    GIM_Try, /*On fail goto*//*Label 1089*/ GIMT_Encode4(71275), // Rule ID 3434 //
      GIM_CheckFeatures, GIMT_Encode2(GIFBS_EnableFlatScratch_HasFlatScratchInsts),
      GIM_CheckMemoryAddressSpace, /*MI*/0, /*MMO*/0, /*NumAddrSpace*/1, /*AddrSpace*/5,
      GIM_CheckAtomicOrdering, /*MI*/0, /*Order*/(uint8_t)AtomicOrdering::NotAtomic,
      GIM_CheckRegBankForClass, /*MI*/0, /*Op*/0, /*RC*/GIMT_Encode2(AMDGPU::AV_32RegClassID),
      GIM_CheckPointerToAny, /*MI*/0, /*Op*/1, /*SizeInBits*/0,
      GIM_CheckComplexPattern, /*MI*/0, /*Op*/1, /*Renderer*/GIMT_Encode2(0), GIMT_Encode2(GICP_gi_flat_scratch_offset),
      // (ld:{ *:[f32] } (ScratchOffset:{ *:[iPTR] } VGPR_32:{ *:[i32] }:$vaddr, i32:{ *:[i32] }:$offset))<<P:Predicate_unindexedload>><<P:Predicate_load_private>>  =>  (SCRATCH_LOAD_DWORD:{ *:[f32] } ?:{ *:[i32] }:$vaddr, ?:{ *:[i32] }:$offset)
      GIR_BuildMI, /*InsnID*/0, /*Opcode*/GIMT_Encode2(AMDGPU::SCRATCH_LOAD_DWORD),
      GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/0, // DstI[vdst]
      GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/0, // vaddr
      GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/1, // offset
      GIR_AddImm8, /*InsnID*/0, /*Imm*/0,
      GIR_MergeMemOperands, /*InsnID*/0, /*NumInsns*/1, /*MergeInsnID's*/0,
      GIR_ConstrainSelectedInstOperands, /*InsnID*/0,
      GIR_EraseFromParent, /*InsnID*/0,
      // GIR_Coverage, 3434,
      GIR_Done,
    // Label 1089: @71275
    GIM_Try, /*On fail goto*//*Label 1090*/ GIMT_Encode4(71359), // Rule ID 3642 //
      GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasUnrestrictedSOffset),
      GIM_CheckMemorySizeEqualTo, /*MI*/0, /*MMO*/0, /*Size*/GIMT_Encode4(1),
      GIM_CheckMemoryAddressSpace, /*MI*/0, /*MMO*/0, /*NumAddrSpace*/3, /*AddrSpace*/1, /*AddrSpace*/4, /*AddrSpace*/6,
      GIM_CheckAtomicOrderingOrStrongerThan, /*MI*/0, /*Order*/(uint8_t)AtomicOrdering::Unordered,
      GIM_CheckRegBankForClass, /*MI*/0, /*Op*/0, /*RC*/GIMT_Encode2(AMDGPU::AV_32RegClassID),
      GIM_CheckPointerToAny, /*MI*/0, /*Op*/1, /*SizeInBits*/0,
      GIM_CheckComplexPattern, /*MI*/0, /*Op*/1, /*Renderer*/GIMT_Encode2(0), GIMT_Encode2(GICP_gi_mubuf_addr64),
      // (atomic_load:{ *:[i32] } (MUBUFAddr64:{ *:[iPTR] } v4i32:{ *:[v4i32] }:$srsrc, i64:{ *:[i64] }:$vaddr, i32:{ *:[i32] }:$soffset, i32:{ *:[i32] }:$offset))<<P:Predicate_atomic_load_8>><<P:Predicate_atomic_load_8_global>>  =>  (BUFFER_LOAD_UBYTE_ADDR64:{ *:[i32] } i64:{ *:[i64] }:$vaddr, v4i32:{ *:[v4i32] }:$srsrc, i32:{ *:[i32] }:$soffset, i32:{ *:[i32] }:$offset)
      GIR_BuildMI, /*InsnID*/0, /*Opcode*/GIMT_Encode2(AMDGPU::BUFFER_LOAD_UBYTE_ADDR64),
      GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/0, // DstI[vdata]
      GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/1, // vaddr
      GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/0, // srsrc
      GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/2, // soffset
      GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/3, // offset
      GIR_AddImm8, /*InsnID*/0, /*Imm*/0,
      GIR_AddImm8, /*InsnID*/0, /*Imm*/0,
      GIR_MergeMemOperands, /*InsnID*/0, /*NumInsns*/1, /*MergeInsnID's*/0,
      GIR_ConstrainSelectedInstOperands, /*InsnID*/0,
      GIR_EraseFromParent, /*InsnID*/0,
      // GIR_Coverage, 3642,
      GIR_Done,
    // Label 1090: @71359
    GIM_Try, /*On fail goto*//*Label 1091*/ GIMT_Encode4(71440), // Rule ID 3646 //
      GIM_CheckMemorySizeEqualTo, /*MI*/0, /*MMO*/0, /*Size*/GIMT_Encode4(1),
      GIM_CheckMemoryAddressSpace, /*MI*/0, /*MMO*/0, /*NumAddrSpace*/3, /*AddrSpace*/1, /*AddrSpace*/4, /*AddrSpace*/6,
      GIM_CheckAtomicOrderingOrStrongerThan, /*MI*/0, /*Order*/(uint8_t)AtomicOrdering::Unordered,
      GIM_CheckRegBankForClass, /*MI*/0, /*Op*/0, /*RC*/GIMT_Encode2(AMDGPU::AV_32RegClassID),
      GIM_CheckPointerToAny, /*MI*/0, /*Op*/1, /*SizeInBits*/0,
      GIM_CheckComplexPattern, /*MI*/0, /*Op*/1, /*Renderer*/GIMT_Encode2(0), GIMT_Encode2(GICP_gi_mubuf_addr64),
      // (atomic_load:{ *:[i32] } (MUBUFAddr64:{ *:[iPTR] } v4i32:{ *:[v4i32] }:$srsrc, i64:{ *:[i64] }:$vaddr, i32:{ *:[i32] }:$soffset, i32:{ *:[i32] }:$offset))<<P:Predicate_atomic_load_8>><<P:Predicate_atomic_load_8_global>>  =>  (BUFFER_LOAD_UBYTE_VBUFFER_ADDR64:{ *:[i32] } i64:{ *:[i64] }:$vaddr, v4i32:{ *:[v4i32] }:$srsrc, i32:{ *:[i32] }:$soffset, i32:{ *:[i32] }:$offset)
      GIR_BuildMI, /*InsnID*/0, /*Opcode*/GIMT_Encode2(AMDGPU::BUFFER_LOAD_UBYTE_VBUFFER_ADDR64),
      GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/0, // DstI[vdata]
      GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/1, // vaddr
      GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/0, // srsrc
      GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/2, // soffset
      GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/3, // offset
      GIR_AddImm8, /*InsnID*/0, /*Imm*/0,
      GIR_AddImm8, /*InsnID*/0, /*Imm*/0,
      GIR_MergeMemOperands, /*InsnID*/0, /*NumInsns*/1, /*MergeInsnID's*/0,
      GIR_ConstrainSelectedInstOperands, /*InsnID*/0,
      GIR_EraseFromParent, /*InsnID*/0,
      // GIR_Coverage, 3646,
      GIR_Done,
    // Label 1091: @71440
    GIM_Try, /*On fail goto*//*Label 1092*/ GIMT_Encode4(71524), // Rule ID 3648 //
      GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasUnrestrictedSOffset),
      GIM_CheckMemorySizeEqualTo, /*MI*/0, /*MMO*/0, /*Size*/GIMT_Encode4(2),
      GIM_CheckMemoryAddressSpace, /*MI*/0, /*MMO*/0, /*NumAddrSpace*/3, /*AddrSpace*/1, /*AddrSpace*/4, /*AddrSpace*/6,
      GIM_CheckAtomicOrderingOrStrongerThan, /*MI*/0, /*Order*/(uint8_t)AtomicOrdering::Unordered,
      GIM_CheckRegBankForClass, /*MI*/0, /*Op*/0, /*RC*/GIMT_Encode2(AMDGPU::AV_32RegClassID),
      GIM_CheckPointerToAny, /*MI*/0, /*Op*/1, /*SizeInBits*/0,
      GIM_CheckComplexPattern, /*MI*/0, /*Op*/1, /*Renderer*/GIMT_Encode2(0), GIMT_Encode2(GICP_gi_mubuf_addr64),
      // (atomic_load:{ *:[i32] } (MUBUFAddr64:{ *:[iPTR] } v4i32:{ *:[v4i32] }:$srsrc, i64:{ *:[i64] }:$vaddr, i32:{ *:[i32] }:$soffset, i32:{ *:[i32] }:$offset))<<P:Predicate_atomic_load_16>><<P:Predicate_atomic_load_16_global>>  =>  (BUFFER_LOAD_USHORT_ADDR64:{ *:[i32] } i64:{ *:[i64] }:$vaddr, v4i32:{ *:[v4i32] }:$srsrc, i32:{ *:[i32] }:$soffset, i32:{ *:[i32] }:$offset)
      GIR_BuildMI, /*InsnID*/0, /*Opcode*/GIMT_Encode2(AMDGPU::BUFFER_LOAD_USHORT_ADDR64),
      GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/0, // DstI[vdata]
      GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/1, // vaddr
      GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/0, // srsrc
      GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/2, // soffset
      GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/3, // offset
      GIR_AddImm8, /*InsnID*/0, /*Imm*/0,
      GIR_AddImm8, /*InsnID*/0, /*Imm*/0,
      GIR_MergeMemOperands, /*InsnID*/0, /*NumInsns*/1, /*MergeInsnID's*/0,
      GIR_ConstrainSelectedInstOperands, /*InsnID*/0,
      GIR_EraseFromParent, /*InsnID*/0,
      // GIR_Coverage, 3648,
      GIR_Done,
    // Label 1092: @71524
    GIM_Try, /*On fail goto*//*Label 1093*/ GIMT_Encode4(71605), // Rule ID 3650 //
      GIM_CheckMemorySizeEqualTo, /*MI*/0, /*MMO*/0, /*Size*/GIMT_Encode4(2),
      GIM_CheckMemoryAddressSpace, /*MI*/0, /*MMO*/0, /*NumAddrSpace*/3, /*AddrSpace*/1, /*AddrSpace*/4, /*AddrSpace*/6,
      GIM_CheckAtomicOrderingOrStrongerThan, /*MI*/0, /*Order*/(uint8_t)AtomicOrdering::Unordered,
      GIM_CheckRegBankForClass, /*MI*/0, /*Op*/0, /*RC*/GIMT_Encode2(AMDGPU::AV_32RegClassID),
      GIM_CheckPointerToAny, /*MI*/0, /*Op*/1, /*SizeInBits*/0,
      GIM_CheckComplexPattern, /*MI*/0, /*Op*/1, /*Renderer*/GIMT_Encode2(0), GIMT_Encode2(GICP_gi_mubuf_addr64),
      // (atomic_load:{ *:[i32] } (MUBUFAddr64:{ *:[iPTR] } v4i32:{ *:[v4i32] }:$srsrc, i64:{ *:[i64] }:$vaddr, i32:{ *:[i32] }:$soffset, i32:{ *:[i32] }:$offset))<<P:Predicate_atomic_load_16>><<P:Predicate_atomic_load_16_global>>  =>  (BUFFER_LOAD_USHORT_VBUFFER_ADDR64:{ *:[i32] } i64:{ *:[i64] }:$vaddr, v4i32:{ *:[v4i32] }:$srsrc, i32:{ *:[i32] }:$soffset, i32:{ *:[i32] }:$offset)
      GIR_BuildMI, /*InsnID*/0, /*Opcode*/GIMT_Encode2(AMDGPU::BUFFER_LOAD_USHORT_VBUFFER_ADDR64),
      GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/0, // DstI[vdata]
      GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/1, // vaddr
      GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/0, // srsrc
      GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/2, // soffset
      GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/3, // offset
      GIR_AddImm8, /*InsnID*/0, /*Imm*/0,
      GIR_AddImm8, /*InsnID*/0, /*Imm*/0,
      GIR_MergeMemOperands, /*InsnID*/0, /*NumInsns*/1, /*MergeInsnID's*/0,
      GIR_ConstrainSelectedInstOperands, /*InsnID*/0,
      GIR_EraseFromParent, /*InsnID*/0,
      // GIR_Coverage, 3650,
      GIR_Done,
    // Label 1093: @71605
    GIM_Try, /*On fail goto*//*Label 1094*/ GIMT_Encode4(71689), // Rule ID 5321 //
      GIM_CheckFeatures, GIMT_Encode2(GIFBS_isGFX6GFX7),
      GIM_CheckMemorySizeEqualTo, /*MI*/0, /*MMO*/0, /*Size*/GIMT_Encode4(4),
      GIM_CheckMemoryAddressSpace, /*MI*/0, /*MMO*/0, /*NumAddrSpace*/3, /*AddrSpace*/1, /*AddrSpace*/4, /*AddrSpace*/6,
      GIM_CheckAtomicOrderingOrStrongerThan, /*MI*/0, /*Order*/(uint8_t)AtomicOrdering::Unordered,
      GIM_CheckRegBankForClass, /*MI*/0, /*Op*/0, /*RC*/GIMT_Encode2(AMDGPU::AV_32RegClassID),
      GIM_CheckPointerToAny, /*MI*/0, /*Op*/1, /*SizeInBits*/0,
      GIM_CheckComplexPattern, /*MI*/0, /*Op*/1, /*Renderer*/GIMT_Encode2(0), GIMT_Encode2(GICP_gi_mubuf_addr64),
      // (atomic_load:{ *:[i32] } (MUBUFAddr64:{ *:[iPTR] } v4i32:{ *:[v4i32] }:$srsrc, i64:{ *:[i64] }:$vaddr, i32:{ *:[i32] }:$soffset, i32:{ *:[i32] }:$offset))<<P:Predicate_atomic_load_32>><<P:Predicate_atomic_load_32_global>>  =>  (BUFFER_LOAD_DWORD_ADDR64:{ *:[i32] } ?:{ *:[i64] }:$vaddr, ?:{ *:[v4i32] }:$srsrc, ?:{ *:[i32] }:$soffset, ?:{ *:[i32] }:$offset)
      GIR_BuildMI, /*InsnID*/0, /*Opcode*/GIMT_Encode2(AMDGPU::BUFFER_LOAD_DWORD_ADDR64),
      GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/0, // DstI[vdata]
      GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/1, // vaddr
      GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/0, // srsrc
      GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/2, // soffset
      GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/3, // offset
      GIR_AddImm8, /*InsnID*/0, /*Imm*/0,
      GIR_AddImm8, /*InsnID*/0, /*Imm*/0,
      GIR_MergeMemOperands, /*InsnID*/0, /*NumInsns*/1, /*MergeInsnID's*/0,
      GIR_ConstrainSelectedInstOperands, /*InsnID*/0,
      GIR_EraseFromParent, /*InsnID*/0,
      // GIR_Coverage, 5321,
      GIR_Done,
    // Label 1094: @71689
    GIM_Try, /*On fail goto*//*Label 1095*/ GIMT_Encode4(71777), // Rule ID 3660 //
      GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasUnrestrictedSOffset),
      GIM_CheckMemorySizeLessThanLLT, /*MI*/0, /*MMO*/0, /*OpIdx*/0,
      GIM_CheckMemorySizeEqualTo, /*MI*/0, /*MMO*/0, /*Size*/GIMT_Encode4(1),
      GIM_CheckMemoryAddressSpace, /*MI*/0, /*MMO*/0, /*NumAddrSpace*/3, /*AddrSpace*/1, /*AddrSpace*/4, /*AddrSpace*/6,
      GIM_CheckAtomicOrdering, /*MI*/0, /*Order*/(uint8_t)AtomicOrdering::NotAtomic,
      GIM_CheckRegBankForClass, /*MI*/0, /*Op*/0, /*RC*/GIMT_Encode2(AMDGPU::AV_32RegClassID),
      GIM_CheckPointerToAny, /*MI*/0, /*Op*/1, /*SizeInBits*/0,
      GIM_CheckComplexPattern, /*MI*/0, /*Op*/1, /*Renderer*/GIMT_Encode2(0), GIMT_Encode2(GICP_gi_mubuf_addr64),
      // (ld:{ *:[i32] } (MUBUFAddr64:{ *:[iPTR] } v4i32:{ *:[v4i32] }:$srsrc, i64:{ *:[i64] }:$vaddr, i32:{ *:[i32] }:$soffset, i32:{ *:[i32] }:$offset))<<P:Predicate_unindexedload>><<P:Predicate_extload>><<P:Predicate_extloadi8>><<P:Predicate_extloadi8_global>>  =>  (BUFFER_LOAD_UBYTE_ADDR64:{ *:[i32] } i64:{ *:[i64] }:$vaddr, v4i32:{ *:[v4i32] }:$srsrc, i32:{ *:[i32] }:$soffset, i32:{ *:[i32] }:$offset)
      GIR_BuildMI, /*InsnID*/0, /*Opcode*/GIMT_Encode2(AMDGPU::BUFFER_LOAD_UBYTE_ADDR64),
      GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/0, // DstI[vdata]
      GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/1, // vaddr
      GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/0, // srsrc
      GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/2, // soffset
      GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/3, // offset
      GIR_AddImm8, /*InsnID*/0, /*Imm*/0,
      GIR_AddImm8, /*InsnID*/0, /*Imm*/0,
      GIR_MergeMemOperands, /*InsnID*/0, /*NumInsns*/1, /*MergeInsnID's*/0,
      GIR_ConstrainSelectedInstOperands, /*InsnID*/0,
      GIR_EraseFromParent, /*InsnID*/0,
      // GIR_Coverage, 3660,
      GIR_Done,
    // Label 1095: @71777
    GIM_Try, /*On fail goto*//*Label 1096*/ GIMT_Encode4(71862), // Rule ID 3662 //
      GIM_CheckMemorySizeLessThanLLT, /*MI*/0, /*MMO*/0, /*OpIdx*/0,
      GIM_CheckMemorySizeEqualTo, /*MI*/0, /*MMO*/0, /*Size*/GIMT_Encode4(1),
      GIM_CheckMemoryAddressSpace, /*MI*/0, /*MMO*/0, /*NumAddrSpace*/3, /*AddrSpace*/1, /*AddrSpace*/4, /*AddrSpace*/6,
      GIM_CheckAtomicOrdering, /*MI*/0, /*Order*/(uint8_t)AtomicOrdering::NotAtomic,
      GIM_CheckRegBankForClass, /*MI*/0, /*Op*/0, /*RC*/GIMT_Encode2(AMDGPU::AV_32RegClassID),
      GIM_CheckPointerToAny, /*MI*/0, /*Op*/1, /*SizeInBits*/0,
      GIM_CheckComplexPattern, /*MI*/0, /*Op*/1, /*Renderer*/GIMT_Encode2(0), GIMT_Encode2(GICP_gi_mubuf_addr64),
      // (ld:{ *:[i32] } (MUBUFAddr64:{ *:[iPTR] } v4i32:{ *:[v4i32] }:$srsrc, i64:{ *:[i64] }:$vaddr, i32:{ *:[i32] }:$soffset, i32:{ *:[i32] }:$offset))<<P:Predicate_unindexedload>><<P:Predicate_extload>><<P:Predicate_extloadi8>><<P:Predicate_extloadi8_global>>  =>  (BUFFER_LOAD_UBYTE_VBUFFER_ADDR64:{ *:[i32] } i64:{ *:[i64] }:$vaddr, v4i32:{ *:[v4i32] }:$srsrc, i32:{ *:[i32] }:$soffset, i32:{ *:[i32] }:$offset)
      GIR_BuildMI, /*InsnID*/0, /*Opcode*/GIMT_Encode2(AMDGPU::BUFFER_LOAD_UBYTE_VBUFFER_ADDR64),
      GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/0, // DstI[vdata]
      GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/1, // vaddr
      GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/0, // srsrc
      GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/2, // soffset
      GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/3, // offset
      GIR_AddImm8, /*InsnID*/0, /*Imm*/0,
      GIR_AddImm8, /*InsnID*/0, /*Imm*/0,
      GIR_MergeMemOperands, /*InsnID*/0, /*NumInsns*/1, /*MergeInsnID's*/0,
      GIR_ConstrainSelectedInstOperands, /*InsnID*/0,
      GIR_EraseFromParent, /*InsnID*/0,
      // GIR_Coverage, 3662,
      GIR_Done,
    // Label 1096: @71862
    GIM_Try, /*On fail goto*//*Label 1097*/ GIMT_Encode4(71950), // Rule ID 3672 //
      GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasUnrestrictedSOffset),
      GIM_CheckMemorySizeLessThanLLT, /*MI*/0, /*MMO*/0, /*OpIdx*/0,
      GIM_CheckMemorySizeEqualTo, /*MI*/0, /*MMO*/0, /*Size*/GIMT_Encode4(2),
      GIM_CheckMemoryAddressSpace, /*MI*/0, /*MMO*/0, /*NumAddrSpace*/3, /*AddrSpace*/1, /*AddrSpace*/4, /*AddrSpace*/6,
      GIM_CheckAtomicOrdering, /*MI*/0, /*Order*/(uint8_t)AtomicOrdering::NotAtomic,
      GIM_CheckRegBankForClass, /*MI*/0, /*Op*/0, /*RC*/GIMT_Encode2(AMDGPU::AV_32RegClassID),
      GIM_CheckPointerToAny, /*MI*/0, /*Op*/1, /*SizeInBits*/0,
      GIM_CheckComplexPattern, /*MI*/0, /*Op*/1, /*Renderer*/GIMT_Encode2(0), GIMT_Encode2(GICP_gi_mubuf_addr64),
      // (ld:{ *:[i32] } (MUBUFAddr64:{ *:[iPTR] } v4i32:{ *:[v4i32] }:$srsrc, i64:{ *:[i64] }:$vaddr, i32:{ *:[i32] }:$soffset, i32:{ *:[i32] }:$offset))<<P:Predicate_unindexedload>><<P:Predicate_extload>><<P:Predicate_extloadi16>><<P:Predicate_extloadi16_global>>  =>  (BUFFER_LOAD_USHORT_ADDR64:{ *:[i32] } i64:{ *:[i64] }:$vaddr, v4i32:{ *:[v4i32] }:$srsrc, i32:{ *:[i32] }:$soffset, i32:{ *:[i32] }:$offset)
      GIR_BuildMI, /*InsnID*/0, /*Opcode*/GIMT_Encode2(AMDGPU::BUFFER_LOAD_USHORT_ADDR64),
      GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/0, // DstI[vdata]
      GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/1, // vaddr
      GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/0, // srsrc
      GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/2, // soffset
      GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/3, // offset
      GIR_AddImm8, /*InsnID*/0, /*Imm*/0,
      GIR_AddImm8, /*InsnID*/0, /*Imm*/0,
      GIR_MergeMemOperands, /*InsnID*/0, /*NumInsns*/1, /*MergeInsnID's*/0,
      GIR_ConstrainSelectedInstOperands, /*InsnID*/0,
      GIR_EraseFromParent, /*InsnID*/0,
      // GIR_Coverage, 3672,
      GIR_Done,
    // Label 1097: @71950
    GIM_Try, /*On fail goto*//*Label 1098*/ GIMT_Encode4(72035), // Rule ID 3674 //
      GIM_CheckMemorySizeLessThanLLT, /*MI*/0, /*MMO*/0, /*OpIdx*/0,
      GIM_CheckMemorySizeEqualTo, /*MI*/0, /*MMO*/0, /*Size*/GIMT_Encode4(2),
      GIM_CheckMemoryAddressSpace, /*MI*/0, /*MMO*/0, /*NumAddrSpace*/3, /*AddrSpace*/1, /*AddrSpace*/4, /*AddrSpace*/6,
      GIM_CheckAtomicOrdering, /*MI*/0, /*Order*/(uint8_t)AtomicOrdering::NotAtomic,
      GIM_CheckRegBankForClass, /*MI*/0, /*Op*/0, /*RC*/GIMT_Encode2(AMDGPU::AV_32RegClassID),
      GIM_CheckPointerToAny, /*MI*/0, /*Op*/1, /*SizeInBits*/0,
      GIM_CheckComplexPattern, /*MI*/0, /*Op*/1, /*Renderer*/GIMT_Encode2(0), GIMT_Encode2(GICP_gi_mubuf_addr64),
      // (ld:{ *:[i32] } (MUBUFAddr64:{ *:[iPTR] } v4i32:{ *:[v4i32] }:$srsrc, i64:{ *:[i64] }:$vaddr, i32:{ *:[i32] }:$soffset, i32:{ *:[i32] }:$offset))<<P:Predicate_unindexedload>><<P:Predicate_extload>><<P:Predicate_extloadi16>><<P:Predicate_extloadi16_global>>  =>  (BUFFER_LOAD_USHORT_VBUFFER_ADDR64:{ *:[i32] } i64:{ *:[i64] }:$vaddr, v4i32:{ *:[v4i32] }:$srsrc, i32:{ *:[i32] }:$soffset, i32:{ *:[i32] }:$offset)
      GIR_BuildMI, /*InsnID*/0, /*Opcode*/GIMT_Encode2(AMDGPU::BUFFER_LOAD_USHORT_VBUFFER_ADDR64),
      GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/0, // DstI[vdata]
      GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/1, // vaddr
      GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/0, // srsrc
      GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/2, // soffset
      GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/3, // offset
      GIR_AddImm8, /*InsnID*/0, /*Imm*/0,
      GIR_AddImm8, /*InsnID*/0, /*Imm*/0,
      GIR_MergeMemOperands, /*InsnID*/0, /*NumInsns*/1, /*MergeInsnID's*/0,
      GIR_ConstrainSelectedInstOperands, /*InsnID*/0,
      GIR_EraseFromParent, /*InsnID*/0,
      // GIR_Coverage, 3674,
      GIR_Done,
    // Label 1098: @72035
    GIM_Try, /*On fail goto*//*Label 1099*/ GIMT_Encode4(72122), // Rule ID 5324 //
      GIM_CheckFeatures, GIMT_Encode2(GIFBS_isGFX6GFX7),
      GIM_CheckMemorySizeLessThanLLT, /*MI*/0, /*MMO*/0, /*OpIdx*/0,
      GIM_CheckMemorySizeEqualTo, /*MI*/0, /*MMO*/0, /*Size*/GIMT_Encode4(1),
      GIM_CheckMemoryAddressSpace, /*MI*/0, /*MMO*/0, /*NumAddrSpace*/2, /*AddrSpace*/4, /*AddrSpace*/6,
      GIM_CheckAtomicOrdering, /*MI*/0, /*Order*/(uint8_t)AtomicOrdering::NotAtomic,
      GIM_CheckRegBankForClass, /*MI*/0, /*Op*/0, /*RC*/GIMT_Encode2(AMDGPU::AV_32RegClassID),
      GIM_CheckPointerToAny, /*MI*/0, /*Op*/1, /*SizeInBits*/0,
      GIM_CheckComplexPattern, /*MI*/0, /*Op*/1, /*Renderer*/GIMT_Encode2(0), GIMT_Encode2(GICP_gi_mubuf_addr64),
      // (ld:{ *:[i32] } (MUBUFAddr64:{ *:[iPTR] } v4i32:{ *:[v4i32] }:$srsrc, i64:{ *:[i64] }:$vaddr, i32:{ *:[i32] }:$soffset, i32:{ *:[i32] }:$offset))<<P:Predicate_unindexedload>><<P:Predicate_extload>><<P:Predicate_extloadi8>><<P:Predicate_extloadi8_constant>>  =>  (BUFFER_LOAD_UBYTE_ADDR64:{ *:[i32] } ?:{ *:[i64] }:$vaddr, ?:{ *:[v4i32] }:$srsrc, ?:{ *:[i32] }:$soffset, ?:{ *:[i32] }:$offset)
      GIR_BuildMI, /*InsnID*/0, /*Opcode*/GIMT_Encode2(AMDGPU::BUFFER_LOAD_UBYTE_ADDR64),
      GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/0, // DstI[vdata]
      GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/1, // vaddr
      GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/0, // srsrc
      GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/2, // soffset
      GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/3, // offset
      GIR_AddImm8, /*InsnID*/0, /*Imm*/0,
      GIR_AddImm8, /*InsnID*/0, /*Imm*/0,
      GIR_MergeMemOperands, /*InsnID*/0, /*NumInsns*/1, /*MergeInsnID's*/0,
      GIR_ConstrainSelectedInstOperands, /*InsnID*/0,
      GIR_EraseFromParent, /*InsnID*/0,
      // GIR_Coverage, 5324,
      GIR_Done,
    // Label 1099: @72122
    GIM_Try, /*On fail goto*//*Label 1100*/ GIMT_Encode4(72209), // Rule ID 5327 //
      GIM_CheckFeatures, GIMT_Encode2(GIFBS_isGFX6GFX7),
      GIM_CheckMemorySizeLessThanLLT, /*MI*/0, /*MMO*/0, /*OpIdx*/0,
      GIM_CheckMemorySizeEqualTo, /*MI*/0, /*MMO*/0, /*Size*/GIMT_Encode4(2),
      GIM_CheckMemoryAddressSpace, /*MI*/0, /*MMO*/0, /*NumAddrSpace*/2, /*AddrSpace*/4, /*AddrSpace*/6,
      GIM_CheckAtomicOrdering, /*MI*/0, /*Order*/(uint8_t)AtomicOrdering::NotAtomic,
      GIM_CheckRegBankForClass, /*MI*/0, /*Op*/0, /*RC*/GIMT_Encode2(AMDGPU::AV_32RegClassID),
      GIM_CheckPointerToAny, /*MI*/0, /*Op*/1, /*SizeInBits*/0,
      GIM_CheckComplexPattern, /*MI*/0, /*Op*/1, /*Renderer*/GIMT_Encode2(0), GIMT_Encode2(GICP_gi_mubuf_addr64),
      // (ld:{ *:[i32] } (MUBUFAddr64:{ *:[iPTR] } v4i32:{ *:[v4i32] }:$srsrc, i64:{ *:[i64] }:$vaddr, i32:{ *:[i32] }:$soffset, i32:{ *:[i32] }:$offset))<<P:Predicate_unindexedload>><<P:Predicate_extload>><<P:Predicate_extloadi16>><<P:Predicate_extloadi16_constant>>  =>  (BUFFER_LOAD_USHORT_ADDR64:{ *:[i32] } ?:{ *:[i64] }:$vaddr, ?:{ *:[v4i32] }:$srsrc, ?:{ *:[i32] }:$soffset, ?:{ *:[i32] }:$offset)
      GIR_BuildMI, /*InsnID*/0, /*Opcode*/GIMT_Encode2(AMDGPU::BUFFER_LOAD_USHORT_ADDR64),
      GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/0, // DstI[vdata]
      GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/1, // vaddr
      GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/0, // srsrc
      GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/2, // soffset
      GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/3, // offset
      GIR_AddImm8, /*InsnID*/0, /*Imm*/0,
      GIR_AddImm8, /*InsnID*/0, /*Imm*/0,
      GIR_MergeMemOperands, /*InsnID*/0, /*NumInsns*/1, /*MergeInsnID's*/0,
      GIR_ConstrainSelectedInstOperands, /*InsnID*/0,
      GIR_EraseFromParent, /*InsnID*/0,
      // GIR_Coverage, 5327,
      GIR_Done,
    // Label 1100: @72209
    GIM_Try, /*On fail goto*//*Label 1101*/ GIMT_Encode4(72295), // Rule ID 5351 //
      GIM_CheckFeatures, GIMT_Encode2(GIFBS_DisableFlatScratch_HasUnrestrictedSOffset),
      GIM_CheckMemorySizeLessThanLLT, /*MI*/0, /*MMO*/0, /*OpIdx*/0,
      GIM_CheckMemorySizeEqualTo, /*MI*/0, /*MMO*/0, /*Size*/GIMT_Encode4(1),
      GIM_CheckMemoryAddressSpace, /*MI*/0, /*MMO*/0, /*NumAddrSpace*/1, /*AddrSpace*/5,
      GIM_CheckAtomicOrdering, /*MI*/0, /*Order*/(uint8_t)AtomicOrdering::NotAtomic,
      GIM_CheckRegBankForClass, /*MI*/0, /*Op*/0, /*RC*/GIMT_Encode2(AMDGPU::AV_32RegClassID),
      GIM_CheckPointerToAny, /*MI*/0, /*Op*/1, /*SizeInBits*/0,
      GIM_CheckComplexPattern, /*MI*/0, /*Op*/1, /*Renderer*/GIMT_Encode2(0), GIMT_Encode2(GICP_gi_mubuf_scratch_offen),
      // (ld:{ *:[i32] } (MUBUFScratchOffen:{ *:[iPTR] } v4i32:{ *:[v4i32] }:$srsrc, i32:{ *:[i32] }:$vaddr, i32:{ *:[i32] }:$soffset, i32:{ *:[i32] }:$offset))<<P:Predicate_unindexedload>><<P:Predicate_extload>><<P:Predicate_extloadi8>><<P:Predicate_extloadi8_private>>  =>  (BUFFER_LOAD_UBYTE_OFFEN:{ *:[i32] } ?:{ *:[i32] }:$vaddr, ?:{ *:[v4i32] }:$srsrc, ?:{ *:[i32] }:$soffset, ?:{ *:[i32] }:$offset, 0:{ *:[i32] }, 0:{ *:[i1] })
      GIR_BuildMI, /*InsnID*/0, /*Opcode*/GIMT_Encode2(AMDGPU::BUFFER_LOAD_UBYTE_OFFEN),
      GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/0, // DstI[vdata]
      GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/1, // vaddr
      GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/0, // srsrc
      GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/2, // soffset
      GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/3, // offset
      GIR_AddImm8, /*InsnID*/0, /*Imm*/0,
      GIR_AddImm8, /*InsnID*/0, /*Imm*/0,
      GIR_MergeMemOperands, /*InsnID*/0, /*NumInsns*/1, /*MergeInsnID's*/0,
      GIR_ConstrainSelectedInstOperands, /*InsnID*/0,
      GIR_EraseFromParent, /*InsnID*/0,
      // GIR_Coverage, 5351,
      GIR_Done,
    // Label 1101: @72295
    GIM_Try, /*On fail goto*//*Label 1102*/ GIMT_Encode4(72381), // Rule ID 5353 //
      GIM_CheckFeatures, GIMT_Encode2(GIFBS_DisableFlatScratch),
      GIM_CheckMemorySizeLessThanLLT, /*MI*/0, /*MMO*/0, /*OpIdx*/0,
      GIM_CheckMemorySizeEqualTo, /*MI*/0, /*MMO*/0, /*Size*/GIMT_Encode4(1),
      GIM_CheckMemoryAddressSpace, /*MI*/0, /*MMO*/0, /*NumAddrSpace*/1, /*AddrSpace*/5,
      GIM_CheckAtomicOrdering, /*MI*/0, /*Order*/(uint8_t)AtomicOrdering::NotAtomic,
      GIM_CheckRegBankForClass, /*MI*/0, /*Op*/0, /*RC*/GIMT_Encode2(AMDGPU::AV_32RegClassID),
      GIM_CheckPointerToAny, /*MI*/0, /*Op*/1, /*SizeInBits*/0,
      GIM_CheckComplexPattern, /*MI*/0, /*Op*/1, /*Renderer*/GIMT_Encode2(0), GIMT_Encode2(GICP_gi_mubuf_scratch_offen),
      // (ld:{ *:[i32] } (MUBUFScratchOffen:{ *:[iPTR] } v4i32:{ *:[v4i32] }:$srsrc, i32:{ *:[i32] }:$vaddr, i32:{ *:[i32] }:$soffset, i32:{ *:[i32] }:$offset))<<P:Predicate_unindexedload>><<P:Predicate_extload>><<P:Predicate_extloadi8>><<P:Predicate_extloadi8_private>>  =>  (BUFFER_LOAD_UBYTE_VBUFFER_OFFEN:{ *:[i32] } ?:{ *:[i32] }:$vaddr, ?:{ *:[v4i32] }:$srsrc, ?:{ *:[i32] }:$soffset, ?:{ *:[i32] }:$offset, 0:{ *:[i32] }, 0:{ *:[i1] })
      GIR_BuildMI, /*InsnID*/0, /*Opcode*/GIMT_Encode2(AMDGPU::BUFFER_LOAD_UBYTE_VBUFFER_OFFEN),
      GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/0, // DstI[vdata]
      GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/1, // vaddr
      GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/0, // srsrc
      GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/2, // soffset
      GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/3, // offset
      GIR_AddImm8, /*InsnID*/0, /*Imm*/0,
      GIR_AddImm8, /*InsnID*/0, /*Imm*/0,
      GIR_MergeMemOperands, /*InsnID*/0, /*NumInsns*/1, /*MergeInsnID's*/0,
      GIR_ConstrainSelectedInstOperands, /*InsnID*/0,
      GIR_EraseFromParent, /*InsnID*/0,
      // GIR_Coverage, 5353,
      GIR_Done,
    // Label 1102: @72381
    GIM_Try, /*On fail goto*//*Label 1103*/ GIMT_Encode4(72467), // Rule ID 5375 //
      GIM_CheckFeatures, GIMT_Encode2(GIFBS_DisableFlatScratch_HasUnrestrictedSOffset),
      GIM_CheckMemorySizeLessThanLLT, /*MI*/0, /*MMO*/0, /*OpIdx*/0,
      GIM_CheckMemorySizeEqualTo, /*MI*/0, /*MMO*/0, /*Size*/GIMT_Encode4(2),
      GIM_CheckMemoryAddressSpace, /*MI*/0, /*MMO*/0, /*NumAddrSpace*/1, /*AddrSpace*/5,
      GIM_CheckAtomicOrdering, /*MI*/0, /*Order*/(uint8_t)AtomicOrdering::NotAtomic,
      GIM_CheckRegBankForClass, /*MI*/0, /*Op*/0, /*RC*/GIMT_Encode2(AMDGPU::AV_32RegClassID),
      GIM_CheckPointerToAny, /*MI*/0, /*Op*/1, /*SizeInBits*/0,
      GIM_CheckComplexPattern, /*MI*/0, /*Op*/1, /*Renderer*/GIMT_Encode2(0), GIMT_Encode2(GICP_gi_mubuf_scratch_offen),
      // (ld:{ *:[i32] } (MUBUFScratchOffen:{ *:[iPTR] } v4i32:{ *:[v4i32] }:$srsrc, i32:{ *:[i32] }:$vaddr, i32:{ *:[i32] }:$soffset, i32:{ *:[i32] }:$offset))<<P:Predicate_unindexedload>><<P:Predicate_extload>><<P:Predicate_extloadi16>><<P:Predicate_extloadi16_private>>  =>  (BUFFER_LOAD_USHORT_OFFEN:{ *:[i32] } ?:{ *:[i32] }:$vaddr, ?:{ *:[v4i32] }:$srsrc, ?:{ *:[i32] }:$soffset, ?:{ *:[i32] }:$offset, 0:{ *:[i32] }, 0:{ *:[i1] })
      GIR_BuildMI, /*InsnID*/0, /*Opcode*/GIMT_Encode2(AMDGPU::BUFFER_LOAD_USHORT_OFFEN),
      GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/0, // DstI[vdata]
      GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/1, // vaddr
      GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/0, // srsrc
      GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/2, // soffset
      GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/3, // offset
      GIR_AddImm8, /*InsnID*/0, /*Imm*/0,
      GIR_AddImm8, /*InsnID*/0, /*Imm*/0,
      GIR_MergeMemOperands, /*InsnID*/0, /*NumInsns*/1, /*MergeInsnID's*/0,
      GIR_ConstrainSelectedInstOperands, /*InsnID*/0,
      GIR_EraseFromParent, /*InsnID*/0,
      // GIR_Coverage, 5375,
      GIR_Done,
    // Label 1103: @72467
    GIM_Try, /*On fail goto*//*Label 1104*/ GIMT_Encode4(72553), // Rule ID 5377 //
      GIM_CheckFeatures, GIMT_Encode2(GIFBS_DisableFlatScratch),
      GIM_CheckMemorySizeLessThanLLT, /*MI*/0, /*MMO*/0, /*OpIdx*/0,
      GIM_CheckMemorySizeEqualTo, /*MI*/0, /*MMO*/0, /*Size*/GIMT_Encode4(2),
      GIM_CheckMemoryAddressSpace, /*MI*/0, /*MMO*/0, /*NumAddrSpace*/1, /*AddrSpace*/5,
      GIM_CheckAtomicOrdering, /*MI*/0, /*Order*/(uint8_t)AtomicOrdering::NotAtomic,
      GIM_CheckRegBankForClass, /*MI*/0, /*Op*/0, /*RC*/GIMT_Encode2(AMDGPU::AV_32RegClassID),
      GIM_CheckPointerToAny, /*MI*/0, /*Op*/1, /*SizeInBits*/0,
      GIM_CheckComplexPattern, /*MI*/0, /*Op*/1, /*Renderer*/GIMT_Encode2(0), GIMT_Encode2(GICP_gi_mubuf_scratch_offen),
      // (ld:{ *:[i32] } (MUBUFScratchOffen:{ *:[iPTR] } v4i32:{ *:[v4i32] }:$srsrc, i32:{ *:[i32] }:$vaddr, i32:{ *:[i32] }:$soffset, i32:{ *:[i32] }:$offset))<<P:Predicate_unindexedload>><<P:Predicate_extload>><<P:Predicate_extloadi16>><<P:Predicate_extloadi16_private>>  =>  (BUFFER_LOAD_USHORT_VBUFFER_OFFEN:{ *:[i32] } ?:{ *:[i32] }:$vaddr, ?:{ *:[v4i32] }:$srsrc, ?:{ *:[i32] }:$soffset, ?:{ *:[i32] }:$offset, 0:{ *:[i32] }, 0:{ *:[i1] })
      GIR_BuildMI, /*InsnID*/0, /*Opcode*/GIMT_Encode2(AMDGPU::BUFFER_LOAD_USHORT_VBUFFER_OFFEN),
      GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/0, // DstI[vdata]
      GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/1, // vaddr
      GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/0, // srsrc
      GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/2, // soffset
      GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/3, // offset
      GIR_AddImm8, /*InsnID*/0, /*Imm*/0,
      GIR_AddImm8, /*InsnID*/0, /*Imm*/0,
      GIR_MergeMemOperands, /*InsnID*/0, /*NumInsns*/1, /*MergeInsnID's*/0,
      GIR_ConstrainSelectedInstOperands, /*InsnID*/0,
      GIR_EraseFromParent, /*InsnID*/0,
      // GIR_Coverage, 5377,
      GIR_Done,
    // Label 1104: @72553
    GIM_Try, /*On fail goto*//*Label 1105*/ GIMT_Encode4(72630), // Rule ID 3684 //
      GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasUnrestrictedSOffset),
      GIM_CheckMemoryAddressSpace, /*MI*/0, /*MMO*/0, /*NumAddrSpace*/3, /*AddrSpace*/1, /*AddrSpace*/4, /*AddrSpace*/6,
      GIM_CheckAtomicOrdering, /*MI*/0, /*Order*/(uint8_t)AtomicOrdering::NotAtomic,
      GIM_CheckRegBankForClass, /*MI*/0, /*Op*/0, /*RC*/GIMT_Encode2(AMDGPU::AV_32RegClassID),
      GIM_CheckPointerToAny, /*MI*/0, /*Op*/1, /*SizeInBits*/0,
      GIM_CheckComplexPattern, /*MI*/0, /*Op*/1, /*Renderer*/GIMT_Encode2(0), GIMT_Encode2(GICP_gi_mubuf_addr64),
      // (ld:{ *:[i32] } (MUBUFAddr64:{ *:[iPTR] } v4i32:{ *:[v4i32] }:$srsrc, i64:{ *:[i64] }:$vaddr, i32:{ *:[i32] }:$soffset, i32:{ *:[i32] }:$offset))<<P:Predicate_unindexedload>><<P:Predicate_load_global>>  =>  (BUFFER_LOAD_DWORD_ADDR64:{ *:[i32] } i64:{ *:[i64] }:$vaddr, v4i32:{ *:[v4i32] }:$srsrc, i32:{ *:[i32] }:$soffset, i32:{ *:[i32] }:$offset)
      GIR_BuildMI, /*InsnID*/0, /*Opcode*/GIMT_Encode2(AMDGPU::BUFFER_LOAD_DWORD_ADDR64),
      GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/0, // DstI[vdata]
      GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/1, // vaddr
      GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/0, // srsrc
      GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/2, // soffset
      GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/3, // offset
      GIR_AddImm8, /*InsnID*/0, /*Imm*/0,
      GIR_AddImm8, /*InsnID*/0, /*Imm*/0,
      GIR_MergeMemOperands, /*InsnID*/0, /*NumInsns*/1, /*MergeInsnID's*/0,
      GIR_ConstrainSelectedInstOperands, /*InsnID*/0,
      GIR_EraseFromParent, /*InsnID*/0,
      // GIR_Coverage, 3684,
      GIR_Done,
    // Label 1105: @72630
    GIM_Try, /*On fail goto*//*Label 1106*/ GIMT_Encode4(72704), // Rule ID 3686 //
      GIM_CheckMemoryAddressSpace, /*MI*/0, /*MMO*/0, /*NumAddrSpace*/3, /*AddrSpace*/1, /*AddrSpace*/4, /*AddrSpace*/6,
      GIM_CheckAtomicOrdering, /*MI*/0, /*Order*/(uint8_t)AtomicOrdering::NotAtomic,
      GIM_CheckRegBankForClass, /*MI*/0, /*Op*/0, /*RC*/GIMT_Encode2(AMDGPU::AV_32RegClassID),
      GIM_CheckPointerToAny, /*MI*/0, /*Op*/1, /*SizeInBits*/0,
      GIM_CheckComplexPattern, /*MI*/0, /*Op*/1, /*Renderer*/GIMT_Encode2(0), GIMT_Encode2(GICP_gi_mubuf_addr64),
      // (ld:{ *:[i32] } (MUBUFAddr64:{ *:[iPTR] } v4i32:{ *:[v4i32] }:$srsrc, i64:{ *:[i64] }:$vaddr, i32:{ *:[i32] }:$soffset, i32:{ *:[i32] }:$offset))<<P:Predicate_unindexedload>><<P:Predicate_load_global>>  =>  (BUFFER_LOAD_DWORD_VBUFFER_ADDR64:{ *:[i32] } i64:{ *:[i64] }:$vaddr, v4i32:{ *:[v4i32] }:$srsrc, i32:{ *:[i32] }:$soffset, i32:{ *:[i32] }:$offset)
      GIR_BuildMI, /*InsnID*/0, /*Opcode*/GIMT_Encode2(AMDGPU::BUFFER_LOAD_DWORD_VBUFFER_ADDR64),
      GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/0, // DstI[vdata]
      GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/1, // vaddr
      GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/0, // srsrc
      GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/2, // soffset
      GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/3, // offset
      GIR_AddImm8, /*InsnID*/0, /*Imm*/0,
      GIR_AddImm8, /*InsnID*/0, /*Imm*/0,
      GIR_MergeMemOperands, /*InsnID*/0, /*NumInsns*/1, /*MergeInsnID's*/0,
      GIR_ConstrainSelectedInstOperands, /*InsnID*/0,
      GIR_EraseFromParent, /*InsnID*/0,
      // GIR_Coverage, 3686,
      GIR_Done,
    // Label 1106: @72704
    GIM_Try, /*On fail goto*//*Label 1107*/ GIMT_Encode4(72781), // Rule ID 3688 //
      GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasUnrestrictedSOffset),
      GIM_CheckMemoryAddressSpace, /*MI*/0, /*MMO*/0, /*NumAddrSpace*/3, /*AddrSpace*/1, /*AddrSpace*/4, /*AddrSpace*/6,
      GIM_CheckAtomicOrdering, /*MI*/0, /*Order*/(uint8_t)AtomicOrdering::NotAtomic,
      GIM_CheckRegBankForClass, /*MI*/0, /*Op*/0, /*RC*/GIMT_Encode2(AMDGPU::AV_32RegClassID),
      GIM_CheckPointerToAny, /*MI*/0, /*Op*/1, /*SizeInBits*/0,
      GIM_CheckComplexPattern, /*MI*/0, /*Op*/1, /*Renderer*/GIMT_Encode2(0), GIMT_Encode2(GICP_gi_mubuf_addr64),
      // (ld:{ *:[f32] } (MUBUFAddr64:{ *:[iPTR] } v4i32:{ *:[v4i32] }:$srsrc, i64:{ *:[i64] }:$vaddr, i32:{ *:[i32] }:$soffset, i32:{ *:[i32] }:$offset))<<P:Predicate_unindexedload>><<P:Predicate_load_global>>  =>  (BUFFER_LOAD_DWORD_ADDR64:{ *:[f32] } i64:{ *:[i64] }:$vaddr, v4i32:{ *:[v4i32] }:$srsrc, i32:{ *:[i32] }:$soffset, i32:{ *:[i32] }:$offset)
      GIR_BuildMI, /*InsnID*/0, /*Opcode*/GIMT_Encode2(AMDGPU::BUFFER_LOAD_DWORD_ADDR64),
      GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/0, // DstI[vdata]
      GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/1, // vaddr
      GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/0, // srsrc
      GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/2, // soffset
      GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/3, // offset
      GIR_AddImm8, /*InsnID*/0, /*Imm*/0,
      GIR_AddImm8, /*InsnID*/0, /*Imm*/0,
      GIR_MergeMemOperands, /*InsnID*/0, /*NumInsns*/1, /*MergeInsnID's*/0,
      GIR_ConstrainSelectedInstOperands, /*InsnID*/0,
      GIR_EraseFromParent, /*InsnID*/0,
      // GIR_Coverage, 3688,
      GIR_Done,
    // Label 1107: @72781
    GIM_Try, /*On fail goto*//*Label 1108*/ GIMT_Encode4(72855), // Rule ID 3690 //
      GIM_CheckMemoryAddressSpace, /*MI*/0, /*MMO*/0, /*NumAddrSpace*/3, /*AddrSpace*/1, /*AddrSpace*/4, /*AddrSpace*/6,
      GIM_CheckAtomicOrdering, /*MI*/0, /*Order*/(uint8_t)AtomicOrdering::NotAtomic,
      GIM_CheckRegBankForClass, /*MI*/0, /*Op*/0, /*RC*/GIMT_Encode2(AMDGPU::AV_32RegClassID),
      GIM_CheckPointerToAny, /*MI*/0, /*Op*/1, /*SizeInBits*/0,
      GIM_CheckComplexPattern, /*MI*/0, /*Op*/1, /*Renderer*/GIMT_Encode2(0), GIMT_Encode2(GICP_gi_mubuf_addr64),
      // (ld:{ *:[f32] } (MUBUFAddr64:{ *:[iPTR] } v4i32:{ *:[v4i32] }:$srsrc, i64:{ *:[i64] }:$vaddr, i32:{ *:[i32] }:$soffset, i32:{ *:[i32] }:$offset))<<P:Predicate_unindexedload>><<P:Predicate_load_global>>  =>  (BUFFER_LOAD_DWORD_VBUFFER_ADDR64:{ *:[f32] } i64:{ *:[i64] }:$vaddr, v4i32:{ *:[v4i32] }:$srsrc, i32:{ *:[i32] }:$soffset, i32:{ *:[i32] }:$offset)
      GIR_BuildMI, /*InsnID*/0, /*Opcode*/GIMT_Encode2(AMDGPU::BUFFER_LOAD_DWORD_VBUFFER_ADDR64),
      GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/0, // DstI[vdata]
      GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/1, // vaddr
      GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/0, // srsrc
      GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/2, // soffset
      GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/3, // offset
      GIR_AddImm8, /*InsnID*/0, /*Imm*/0,
      GIR_AddImm8, /*InsnID*/0, /*Imm*/0,
      GIR_MergeMemOperands, /*InsnID*/0, /*NumInsns*/1, /*MergeInsnID's*/0,
      GIR_ConstrainSelectedInstOperands, /*InsnID*/0,
      GIR_EraseFromParent, /*InsnID*/0,
      // GIR_Coverage, 3690,
      GIR_Done,
    // Label 1108: @72855
    GIM_Try, /*On fail goto*//*Label 1109*/ GIMT_Encode4(72930), // Rule ID 5387 //
      GIM_CheckFeatures, GIMT_Encode2(GIFBS_DisableFlatScratch_HasUnrestrictedSOffset),
      GIM_CheckMemoryAddressSpace, /*MI*/0, /*MMO*/0, /*NumAddrSpace*/1, /*AddrSpace*/5,
      GIM_CheckAtomicOrdering, /*MI*/0, /*Order*/(uint8_t)AtomicOrdering::NotAtomic,
      GIM_CheckRegBankForClass, /*MI*/0, /*Op*/0, /*RC*/GIMT_Encode2(AMDGPU::AV_32RegClassID),
      GIM_CheckPointerToAny, /*MI*/0, /*Op*/1, /*SizeInBits*/0,
      GIM_CheckComplexPattern, /*MI*/0, /*Op*/1, /*Renderer*/GIMT_Encode2(0), GIMT_Encode2(GICP_gi_mubuf_scratch_offen),
      // (ld:{ *:[i32] } (MUBUFScratchOffen:{ *:[iPTR] } v4i32:{ *:[v4i32] }:$srsrc, i32:{ *:[i32] }:$vaddr, i32:{ *:[i32] }:$soffset, i32:{ *:[i32] }:$offset))<<P:Predicate_unindexedload>><<P:Predicate_load_private>>  =>  (BUFFER_LOAD_DWORD_OFFEN:{ *:[i32] } ?:{ *:[i32] }:$vaddr, ?:{ *:[v4i32] }:$srsrc, ?:{ *:[i32] }:$soffset, ?:{ *:[i32] }:$offset, 0:{ *:[i32] }, 0:{ *:[i1] })
      GIR_BuildMI, /*InsnID*/0, /*Opcode*/GIMT_Encode2(AMDGPU::BUFFER_LOAD_DWORD_OFFEN),
      GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/0, // DstI[vdata]
      GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/1, // vaddr
      GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/0, // srsrc
      GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/2, // soffset
      GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/3, // offset
      GIR_AddImm8, /*InsnID*/0, /*Imm*/0,
      GIR_AddImm8, /*InsnID*/0, /*Imm*/0,
      GIR_MergeMemOperands, /*InsnID*/0, /*NumInsns*/1, /*MergeInsnID's*/0,
      GIR_ConstrainSelectedInstOperands, /*InsnID*/0,
      GIR_EraseFromParent, /*InsnID*/0,
      // GIR_Coverage, 5387,
      GIR_Done,
    // Label 1109: @72930
    GIM_Try, /*On fail goto*//*Label 1110*/ GIMT_Encode4(73005), // Rule ID 5389 //
      GIM_CheckFeatures, GIMT_Encode2(GIFBS_DisableFlatScratch),
      GIM_CheckMemoryAddressSpace, /*MI*/0, /*MMO*/0, /*NumAddrSpace*/1, /*AddrSpace*/5,
      GIM_CheckAtomicOrdering, /*MI*/0, /*Order*/(uint8_t)AtomicOrdering::NotAtomic,
      GIM_CheckRegBankForClass, /*MI*/0, /*Op*/0, /*RC*/GIMT_Encode2(AMDGPU::AV_32RegClassID),
      GIM_CheckPointerToAny, /*MI*/0, /*Op*/1, /*SizeInBits*/0,
      GIM_CheckComplexPattern, /*MI*/0, /*Op*/1, /*Renderer*/GIMT_Encode2(0), GIMT_Encode2(GICP_gi_mubuf_scratch_offen),
      // (ld:{ *:[i32] } (MUBUFScratchOffen:{ *:[iPTR] } v4i32:{ *:[v4i32] }:$srsrc, i32:{ *:[i32] }:$vaddr, i32:{ *:[i32] }:$soffset, i32:{ *:[i32] }:$offset))<<P:Predicate_unindexedload>><<P:Predicate_load_private>>  =>  (BUFFER_LOAD_DWORD_VBUFFER_OFFEN:{ *:[i32] } ?:{ *:[i32] }:$vaddr, ?:{ *:[v4i32] }:$srsrc, ?:{ *:[i32] }:$soffset, ?:{ *:[i32] }:$offset, 0:{ *:[i32] }, 0:{ *:[i1] })
      GIR_BuildMI, /*InsnID*/0, /*Opcode*/GIMT_Encode2(AMDGPU::BUFFER_LOAD_DWORD_VBUFFER_OFFEN),
      GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/0, // DstI[vdata]
      GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/1, // vaddr
      GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/0, // srsrc
      GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/2, // soffset
      GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/3, // offset
      GIR_AddImm8, /*InsnID*/0, /*Imm*/0,
      GIR_AddImm8, /*InsnID*/0, /*Imm*/0,
      GIR_MergeMemOperands, /*InsnID*/0, /*NumInsns*/1, /*MergeInsnID's*/0,
      GIR_ConstrainSelectedInstOperands, /*InsnID*/0,
      GIR_EraseFromParent, /*InsnID*/0,
      // GIR_Coverage, 5389,
      GIR_Done,
    // Label 1110: @73005
    GIM_Try, /*On fail goto*//*Label 1111*/ GIMT_Encode4(73080), // Rule ID 5391 //
      GIM_CheckFeatures, GIMT_Encode2(GIFBS_DisableFlatScratch_HasUnrestrictedSOffset),
      GIM_CheckMemoryAddressSpace, /*MI*/0, /*MMO*/0, /*NumAddrSpace*/1, /*AddrSpace*/5,
      GIM_CheckAtomicOrdering, /*MI*/0, /*Order*/(uint8_t)AtomicOrdering::NotAtomic,
      GIM_CheckRegBankForClass, /*MI*/0, /*Op*/0, /*RC*/GIMT_Encode2(AMDGPU::AV_32RegClassID),
      GIM_CheckPointerToAny, /*MI*/0, /*Op*/1, /*SizeInBits*/0,
      GIM_CheckComplexPattern, /*MI*/0, /*Op*/1, /*Renderer*/GIMT_Encode2(0), GIMT_Encode2(GICP_gi_mubuf_scratch_offen),
      // (ld:{ *:[f32] } (MUBUFScratchOffen:{ *:[iPTR] } v4i32:{ *:[v4i32] }:$srsrc, i32:{ *:[i32] }:$vaddr, i32:{ *:[i32] }:$soffset, i32:{ *:[i32] }:$offset))<<P:Predicate_unindexedload>><<P:Predicate_load_private>>  =>  (BUFFER_LOAD_DWORD_OFFEN:{ *:[f32] } ?:{ *:[i32] }:$vaddr, ?:{ *:[v4i32] }:$srsrc, ?:{ *:[i32] }:$soffset, ?:{ *:[i32] }:$offset, 0:{ *:[i32] }, 0:{ *:[i1] })
      GIR_BuildMI, /*InsnID*/0, /*Opcode*/GIMT_Encode2(AMDGPU::BUFFER_LOAD_DWORD_OFFEN),
      GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/0, // DstI[vdata]
      GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/1, // vaddr
      GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/0, // srsrc
      GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/2, // soffset
      GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/3, // offset
      GIR_AddImm8, /*InsnID*/0, /*Imm*/0,
      GIR_AddImm8, /*InsnID*/0, /*Imm*/0,
      GIR_MergeMemOperands, /*InsnID*/0, /*NumInsns*/1, /*MergeInsnID's*/0,
      GIR_ConstrainSelectedInstOperands, /*InsnID*/0,
      GIR_EraseFromParent, /*InsnID*/0,
      // GIR_Coverage, 5391,
      GIR_Done,
    // Label 1111: @73080
    GIM_Try, /*On fail goto*//*Label 1112*/ GIMT_Encode4(73155), // Rule ID 5393 //
      GIM_CheckFeatures, GIMT_Encode2(GIFBS_DisableFlatScratch),
      GIM_CheckMemoryAddressSpace, /*MI*/0, /*MMO*/0, /*NumAddrSpace*/1, /*AddrSpace*/5,
      GIM_CheckAtomicOrdering, /*MI*/0, /*Order*/(uint8_t)AtomicOrdering::NotAtomic,
      GIM_CheckRegBankForClass, /*MI*/0, /*Op*/0, /*RC*/GIMT_Encode2(AMDGPU::AV_32RegClassID),
      GIM_CheckPointerToAny, /*MI*/0, /*Op*/1, /*SizeInBits*/0,
      GIM_CheckComplexPattern, /*MI*/0, /*Op*/1, /*Renderer*/GIMT_Encode2(0), GIMT_Encode2(GICP_gi_mubuf_scratch_offen),
      // (ld:{ *:[f32] } (MUBUFScratchOffen:{ *:[iPTR] } v4i32:{ *:[v4i32] }:$srsrc, i32:{ *:[i32] }:$vaddr, i32:{ *:[i32] }:$soffset, i32:{ *:[i32] }:$offset))<<P:Predicate_unindexedload>><<P:Predicate_load_private>>  =>  (BUFFER_LOAD_DWORD_VBUFFER_OFFEN:{ *:[f32] } ?:{ *:[i32] }:$vaddr, ?:{ *:[v4i32] }:$srsrc, ?:{ *:[i32] }:$soffset, ?:{ *:[i32] }:$offset, 0:{ *:[i32] }, 0:{ *:[i1] })
      GIR_BuildMI, /*InsnID*/0, /*Opcode*/GIMT_Encode2(AMDGPU::BUFFER_LOAD_DWORD_VBUFFER_OFFEN),
      GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/0, // DstI[vdata]
      GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/1, // vaddr
      GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/0, // srsrc
      GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/2, // soffset
      GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/3, // offset
      GIR_AddImm8, /*InsnID*/0, /*Imm*/0,
      GIR_AddImm8, /*InsnID*/0, /*Imm*/0,
      GIR_MergeMemOperands, /*InsnID*/0, /*NumInsns*/1, /*MergeInsnID's*/0,
      GIR_ConstrainSelectedInstOperands, /*InsnID*/0,
      GIR_EraseFromParent, /*InsnID*/0,
      // GIR_Coverage, 5393,
      GIR_Done,
    // Label 1112: @73155
    GIM_Try, /*On fail goto*//*Label 1113*/ GIMT_Encode4(73234), // Rule ID 3641 //
      GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasUnrestrictedSOffset),
      GIM_CheckMemorySizeEqualTo, /*MI*/0, /*MMO*/0, /*Size*/GIMT_Encode4(1),
      GIM_CheckMemoryAddressSpace, /*MI*/0, /*MMO*/0, /*NumAddrSpace*/3, /*AddrSpace*/1, /*AddrSpace*/4, /*AddrSpace*/6,
      GIM_CheckAtomicOrderingOrStrongerThan, /*MI*/0, /*Order*/(uint8_t)AtomicOrdering::Unordered,
      GIM_CheckRegBankForClass, /*MI*/0, /*Op*/0, /*RC*/GIMT_Encode2(AMDGPU::AV_32RegClassID),
      GIM_CheckPointerToAny, /*MI*/0, /*Op*/1, /*SizeInBits*/0,
      GIM_CheckComplexPattern, /*MI*/0, /*Op*/1, /*Renderer*/GIMT_Encode2(0), GIMT_Encode2(GICP_gi_mubuf_offset),
      // (atomic_load:{ *:[i32] } (MUBUFOffset:{ *:[iPTR] } v4i32:{ *:[v4i32] }:$srsrc, i32:{ *:[i32] }:$soffset, i32:{ *:[i32] }:$offset))<<P:Predicate_atomic_load_8>><<P:Predicate_atomic_load_8_global>>  =>  (BUFFER_LOAD_UBYTE_OFFSET:{ *:[i32] } v4i32:{ *:[v4i32] }:$srsrc, i32:{ *:[i32] }:$soffset, i32:{ *:[i32] }:$offset)
      GIR_BuildMI, /*InsnID*/0, /*Opcode*/GIMT_Encode2(AMDGPU::BUFFER_LOAD_UBYTE_OFFSET),
      GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/0, // DstI[vdata]
      GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/0, // srsrc
      GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/1, // soffset
      GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/2, // offset
      GIR_AddImm8, /*InsnID*/0, /*Imm*/0,
      GIR_AddImm8, /*InsnID*/0, /*Imm*/0,
      GIR_MergeMemOperands, /*InsnID*/0, /*NumInsns*/1, /*MergeInsnID's*/0,
      GIR_ConstrainSelectedInstOperands, /*InsnID*/0,
      GIR_EraseFromParent, /*InsnID*/0,
      // GIR_Coverage, 3641,
      GIR_Done,
    // Label 1113: @73234
    GIM_Try, /*On fail goto*//*Label 1114*/ GIMT_Encode4(73310), // Rule ID 3645 //
      GIM_CheckMemorySizeEqualTo, /*MI*/0, /*MMO*/0, /*Size*/GIMT_Encode4(1),
      GIM_CheckMemoryAddressSpace, /*MI*/0, /*MMO*/0, /*NumAddrSpace*/3, /*AddrSpace*/1, /*AddrSpace*/4, /*AddrSpace*/6,
      GIM_CheckAtomicOrderingOrStrongerThan, /*MI*/0, /*Order*/(uint8_t)AtomicOrdering::Unordered,
      GIM_CheckRegBankForClass, /*MI*/0, /*Op*/0, /*RC*/GIMT_Encode2(AMDGPU::AV_32RegClassID),
      GIM_CheckPointerToAny, /*MI*/0, /*Op*/1, /*SizeInBits*/0,
      GIM_CheckComplexPattern, /*MI*/0, /*Op*/1, /*Renderer*/GIMT_Encode2(0), GIMT_Encode2(GICP_gi_mubuf_offset),
      // (atomic_load:{ *:[i32] } (MUBUFOffset:{ *:[iPTR] } v4i32:{ *:[v4i32] }:$srsrc, i32:{ *:[i32] }:$soffset, i32:{ *:[i32] }:$offset))<<P:Predicate_atomic_load_8>><<P:Predicate_atomic_load_8_global>>  =>  (BUFFER_LOAD_UBYTE_VBUFFER_OFFSET:{ *:[i32] } v4i32:{ *:[v4i32] }:$srsrc, i32:{ *:[i32] }:$soffset, i32:{ *:[i32] }:$offset)
      GIR_BuildMI, /*InsnID*/0, /*Opcode*/GIMT_Encode2(AMDGPU::BUFFER_LOAD_UBYTE_VBUFFER_OFFSET),
      GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/0, // DstI[vdata]
      GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/0, // srsrc
      GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/1, // soffset
      GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/2, // offset
      GIR_AddImm8, /*InsnID*/0, /*Imm*/0,
      GIR_AddImm8, /*InsnID*/0, /*Imm*/0,
      GIR_MergeMemOperands, /*InsnID*/0, /*NumInsns*/1, /*MergeInsnID's*/0,
      GIR_ConstrainSelectedInstOperands, /*InsnID*/0,
      GIR_EraseFromParent, /*InsnID*/0,
      // GIR_Coverage, 3645,
      GIR_Done,
    // Label 1114: @73310
    GIM_Try, /*On fail goto*//*Label 1115*/ GIMT_Encode4(73389), // Rule ID 3647 //
      GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasUnrestrictedSOffset),
      GIM_CheckMemorySizeEqualTo, /*MI*/0, /*MMO*/0, /*Size*/GIMT_Encode4(2),
      GIM_CheckMemoryAddressSpace, /*MI*/0, /*MMO*/0, /*NumAddrSpace*/3, /*AddrSpace*/1, /*AddrSpace*/4, /*AddrSpace*/6,
      GIM_CheckAtomicOrderingOrStrongerThan, /*MI*/0, /*Order*/(uint8_t)AtomicOrdering::Unordered,
      GIM_CheckRegBankForClass, /*MI*/0, /*Op*/0, /*RC*/GIMT_Encode2(AMDGPU::AV_32RegClassID),
      GIM_CheckPointerToAny, /*MI*/0, /*Op*/1, /*SizeInBits*/0,
      GIM_CheckComplexPattern, /*MI*/0, /*Op*/1, /*Renderer*/GIMT_Encode2(0), GIMT_Encode2(GICP_gi_mubuf_offset),
      // (atomic_load:{ *:[i32] } (MUBUFOffset:{ *:[iPTR] } v4i32:{ *:[v4i32] }:$srsrc, i32:{ *:[i32] }:$soffset, i32:{ *:[i32] }:$offset))<<P:Predicate_atomic_load_16>><<P:Predicate_atomic_load_16_global>>  =>  (BUFFER_LOAD_USHORT_OFFSET:{ *:[i32] } v4i32:{ *:[v4i32] }:$srsrc, i32:{ *:[i32] }:$soffset, i32:{ *:[i32] }:$offset)
      GIR_BuildMI, /*InsnID*/0, /*Opcode*/GIMT_Encode2(AMDGPU::BUFFER_LOAD_USHORT_OFFSET),
      GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/0, // DstI[vdata]
      GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/0, // srsrc
      GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/1, // soffset
      GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/2, // offset
      GIR_AddImm8, /*InsnID*/0, /*Imm*/0,
      GIR_AddImm8, /*InsnID*/0, /*Imm*/0,
      GIR_MergeMemOperands, /*InsnID*/0, /*NumInsns*/1, /*MergeInsnID's*/0,
      GIR_ConstrainSelectedInstOperands, /*InsnID*/0,
      GIR_EraseFromParent, /*InsnID*/0,
      // GIR_Coverage, 3647,
      GIR_Done,
    // Label 1115: @73389
    GIM_Try, /*On fail goto*//*Label 1116*/ GIMT_Encode4(73465), // Rule ID 3649 //
      GIM_CheckMemorySizeEqualTo, /*MI*/0, /*MMO*/0, /*Size*/GIMT_Encode4(2),
      GIM_CheckMemoryAddressSpace, /*MI*/0, /*MMO*/0, /*NumAddrSpace*/3, /*AddrSpace*/1, /*AddrSpace*/4, /*AddrSpace*/6,
      GIM_CheckAtomicOrderingOrStrongerThan, /*MI*/0, /*Order*/(uint8_t)AtomicOrdering::Unordered,
      GIM_CheckRegBankForClass, /*MI*/0, /*Op*/0, /*RC*/GIMT_Encode2(AMDGPU::AV_32RegClassID),
      GIM_CheckPointerToAny, /*MI*/0, /*Op*/1, /*SizeInBits*/0,
      GIM_CheckComplexPattern, /*MI*/0, /*Op*/1, /*Renderer*/GIMT_Encode2(0), GIMT_Encode2(GICP_gi_mubuf_offset),
      // (atomic_load:{ *:[i32] } (MUBUFOffset:{ *:[iPTR] } v4i32:{ *:[v4i32] }:$srsrc, i32:{ *:[i32] }:$soffset, i32:{ *:[i32] }:$offset))<<P:Predicate_atomic_load_16>><<P:Predicate_atomic_load_16_global>>  =>  (BUFFER_LOAD_USHORT_VBUFFER_OFFSET:{ *:[i32] } v4i32:{ *:[v4i32] }:$srsrc, i32:{ *:[i32] }:$soffset, i32:{ *:[i32] }:$offset)
      GIR_BuildMI, /*InsnID*/0, /*Opcode*/GIMT_Encode2(AMDGPU::BUFFER_LOAD_USHORT_VBUFFER_OFFSET),
      GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/0, // DstI[vdata]
      GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/0, // srsrc
      GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/1, // soffset
      GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/2, // offset
      GIR_AddImm8, /*InsnID*/0, /*Imm*/0,
      GIR_AddImm8, /*InsnID*/0, /*Imm*/0,
      GIR_MergeMemOperands, /*InsnID*/0, /*NumInsns*/1, /*MergeInsnID's*/0,
      GIR_ConstrainSelectedInstOperands, /*InsnID*/0,
      GIR_EraseFromParent, /*InsnID*/0,
      // GIR_Coverage, 3649,
      GIR_Done,
    // Label 1116: @73465
    GIM_Try, /*On fail goto*//*Label 1117*/ GIMT_Encode4(73548), // Rule ID 3659 //
      GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasUnrestrictedSOffset),
      GIM_CheckMemorySizeLessThanLLT, /*MI*/0, /*MMO*/0, /*OpIdx*/0,
      GIM_CheckMemorySizeEqualTo, /*MI*/0, /*MMO*/0, /*Size*/GIMT_Encode4(1),
      GIM_CheckMemoryAddressSpace, /*MI*/0, /*MMO*/0, /*NumAddrSpace*/3, /*AddrSpace*/1, /*AddrSpace*/4, /*AddrSpace*/6,
      GIM_CheckAtomicOrdering, /*MI*/0, /*Order*/(uint8_t)AtomicOrdering::NotAtomic,
      GIM_CheckRegBankForClass, /*MI*/0, /*Op*/0, /*RC*/GIMT_Encode2(AMDGPU::AV_32RegClassID),
      GIM_CheckPointerToAny, /*MI*/0, /*Op*/1, /*SizeInBits*/0,
      GIM_CheckComplexPattern, /*MI*/0, /*Op*/1, /*Renderer*/GIMT_Encode2(0), GIMT_Encode2(GICP_gi_mubuf_offset),
      // (ld:{ *:[i32] } (MUBUFOffset:{ *:[iPTR] } v4i32:{ *:[v4i32] }:$srsrc, i32:{ *:[i32] }:$soffset, i32:{ *:[i32] }:$offset))<<P:Predicate_unindexedload>><<P:Predicate_extload>><<P:Predicate_extloadi8>><<P:Predicate_extloadi8_global>>  =>  (BUFFER_LOAD_UBYTE_OFFSET:{ *:[i32] } v4i32:{ *:[v4i32] }:$srsrc, i32:{ *:[i32] }:$soffset, i32:{ *:[i32] }:$offset)
      GIR_BuildMI, /*InsnID*/0, /*Opcode*/GIMT_Encode2(AMDGPU::BUFFER_LOAD_UBYTE_OFFSET),
      GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/0, // DstI[vdata]
      GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/0, // srsrc
      GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/1, // soffset
      GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/2, // offset
      GIR_AddImm8, /*InsnID*/0, /*Imm*/0,
      GIR_AddImm8, /*InsnID*/0, /*Imm*/0,
      GIR_MergeMemOperands, /*InsnID*/0, /*NumInsns*/1, /*MergeInsnID's*/0,
      GIR_ConstrainSelectedInstOperands, /*InsnID*/0,
      GIR_EraseFromParent, /*InsnID*/0,
      // GIR_Coverage, 3659,
      GIR_Done,
    // Label 1117: @73548
    GIM_Try, /*On fail goto*//*Label 1118*/ GIMT_Encode4(73628), // Rule ID 3661 //
      GIM_CheckMemorySizeLessThanLLT, /*MI*/0, /*MMO*/0, /*OpIdx*/0,
      GIM_CheckMemorySizeEqualTo, /*MI*/0, /*MMO*/0, /*Size*/GIMT_Encode4(1),
      GIM_CheckMemoryAddressSpace, /*MI*/0, /*MMO*/0, /*NumAddrSpace*/3, /*AddrSpace*/1, /*AddrSpace*/4, /*AddrSpace*/6,
      GIM_CheckAtomicOrdering, /*MI*/0, /*Order*/(uint8_t)AtomicOrdering::NotAtomic,
      GIM_CheckRegBankForClass, /*MI*/0, /*Op*/0, /*RC*/GIMT_Encode2(AMDGPU::AV_32RegClassID),
      GIM_CheckPointerToAny, /*MI*/0, /*Op*/1, /*SizeInBits*/0,
      GIM_CheckComplexPattern, /*MI*/0, /*Op*/1, /*Renderer*/GIMT_Encode2(0), GIMT_Encode2(GICP_gi_mubuf_offset),
      // (ld:{ *:[i32] } (MUBUFOffset:{ *:[iPTR] } v4i32:{ *:[v4i32] }:$srsrc, i32:{ *:[i32] }:$soffset, i32:{ *:[i32] }:$offset))<<P:Predicate_unindexedload>><<P:Predicate_extload>><<P:Predicate_extloadi8>><<P:Predicate_extloadi8_global>>  =>  (BUFFER_LOAD_UBYTE_VBUFFER_OFFSET:{ *:[i32] } v4i32:{ *:[v4i32] }:$srsrc, i32:{ *:[i32] }:$soffset, i32:{ *:[i32] }:$offset)
      GIR_BuildMI, /*InsnID*/0, /*Opcode*/GIMT_Encode2(AMDGPU::BUFFER_LOAD_UBYTE_VBUFFER_OFFSET),
      GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/0, // DstI[vdata]
      GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/0, // srsrc
      GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/1, // soffset
      GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/2, // offset
      GIR_AddImm8, /*InsnID*/0, /*Imm*/0,
      GIR_AddImm8, /*InsnID*/0, /*Imm*/0,
      GIR_MergeMemOperands, /*InsnID*/0, /*NumInsns*/1, /*MergeInsnID's*/0,
      GIR_ConstrainSelectedInstOperands, /*InsnID*/0,
      GIR_EraseFromParent, /*InsnID*/0,
      // GIR_Coverage, 3661,
      GIR_Done,
    // Label 1118: @73628
    GIM_Try, /*On fail goto*//*Label 1119*/ GIMT_Encode4(73711), // Rule ID 3671 //
      GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasUnrestrictedSOffset),
      GIM_CheckMemorySizeLessThanLLT, /*MI*/0, /*MMO*/0, /*OpIdx*/0,
      GIM_CheckMemorySizeEqualTo, /*MI*/0, /*MMO*/0, /*Size*/GIMT_Encode4(2),
      GIM_CheckMemoryAddressSpace, /*MI*/0, /*MMO*/0, /*NumAddrSpace*/3, /*AddrSpace*/1, /*AddrSpace*/4, /*AddrSpace*/6,
      GIM_CheckAtomicOrdering, /*MI*/0, /*Order*/(uint8_t)AtomicOrdering::NotAtomic,
      GIM_CheckRegBankForClass, /*MI*/0, /*Op*/0, /*RC*/GIMT_Encode2(AMDGPU::AV_32RegClassID),
      GIM_CheckPointerToAny, /*MI*/0, /*Op*/1, /*SizeInBits*/0,
      GIM_CheckComplexPattern, /*MI*/0, /*Op*/1, /*Renderer*/GIMT_Encode2(0), GIMT_Encode2(GICP_gi_mubuf_offset),
      // (ld:{ *:[i32] } (MUBUFOffset:{ *:[iPTR] } v4i32:{ *:[v4i32] }:$srsrc, i32:{ *:[i32] }:$soffset, i32:{ *:[i32] }:$offset))<<P:Predicate_unindexedload>><<P:Predicate_extload>><<P:Predicate_extloadi16>><<P:Predicate_extloadi16_global>>  =>  (BUFFER_LOAD_USHORT_OFFSET:{ *:[i32] } v4i32:{ *:[v4i32] }:$srsrc, i32:{ *:[i32] }:$soffset, i32:{ *:[i32] }:$offset)
      GIR_BuildMI, /*InsnID*/0, /*Opcode*/GIMT_Encode2(AMDGPU::BUFFER_LOAD_USHORT_OFFSET),
      GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/0, // DstI[vdata]
      GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/0, // srsrc
      GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/1, // soffset
      GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/2, // offset
      GIR_AddImm8, /*InsnID*/0, /*Imm*/0,
      GIR_AddImm8, /*InsnID*/0, /*Imm*/0,
      GIR_MergeMemOperands, /*InsnID*/0, /*NumInsns*/1, /*MergeInsnID's*/0,
      GIR_ConstrainSelectedInstOperands, /*InsnID*/0,
      GIR_EraseFromParent, /*InsnID*/0,
      // GIR_Coverage, 3671,
      GIR_Done,
    // Label 1119: @73711
    GIM_Try, /*On fail goto*//*Label 1120*/ GIMT_Encode4(73791), // Rule ID 3673 //
      GIM_CheckMemorySizeLessThanLLT, /*MI*/0, /*MMO*/0, /*OpIdx*/0,
      GIM_CheckMemorySizeEqualTo, /*MI*/0, /*MMO*/0, /*Size*/GIMT_Encode4(2),
      GIM_CheckMemoryAddressSpace, /*MI*/0, /*MMO*/0, /*NumAddrSpace*/3, /*AddrSpace*/1, /*AddrSpace*/4, /*AddrSpace*/6,
      GIM_CheckAtomicOrdering, /*MI*/0, /*Order*/(uint8_t)AtomicOrdering::NotAtomic,
      GIM_CheckRegBankForClass, /*MI*/0, /*Op*/0, /*RC*/GIMT_Encode2(AMDGPU::AV_32RegClassID),
      GIM_CheckPointerToAny, /*MI*/0, /*Op*/1, /*SizeInBits*/0,
      GIM_CheckComplexPattern, /*MI*/0, /*Op*/1, /*Renderer*/GIMT_Encode2(0), GIMT_Encode2(GICP_gi_mubuf_offset),
      // (ld:{ *:[i32] } (MUBUFOffset:{ *:[iPTR] } v4i32:{ *:[v4i32] }:$srsrc, i32:{ *:[i32] }:$soffset, i32:{ *:[i32] }:$offset))<<P:Predicate_unindexedload>><<P:Predicate_extload>><<P:Predicate_extloadi16>><<P:Predicate_extloadi16_global>>  =>  (BUFFER_LOAD_USHORT_VBUFFER_OFFSET:{ *:[i32] } v4i32:{ *:[v4i32] }:$srsrc, i32:{ *:[i32] }:$soffset, i32:{ *:[i32] }:$offset)
      GIR_BuildMI, /*InsnID*/0, /*Opcode*/GIMT_Encode2(AMDGPU::BUFFER_LOAD_USHORT_VBUFFER_OFFSET),
      GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/0, // DstI[vdata]
      GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/0, // srsrc
      GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/1, // soffset
      GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/2, // offset
      GIR_AddImm8, /*InsnID*/0, /*Imm*/0,
      GIR_AddImm8, /*InsnID*/0, /*Imm*/0,
      GIR_MergeMemOperands, /*InsnID*/0, /*NumInsns*/1, /*MergeInsnID's*/0,
      GIR_ConstrainSelectedInstOperands, /*InsnID*/0,
      GIR_EraseFromParent, /*InsnID*/0,
      // GIR_Coverage, 3673,
      GIR_Done,
    // Label 1120: @73791
    GIM_Try, /*On fail goto*//*Label 1121*/ GIMT_Encode4(73863), // Rule ID 3683 //
      GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasUnrestrictedSOffset),
      GIM_CheckMemoryAddressSpace, /*MI*/0, /*MMO*/0, /*NumAddrSpace*/3, /*AddrSpace*/1, /*AddrSpace*/4, /*AddrSpace*/6,
      GIM_CheckAtomicOrdering, /*MI*/0, /*Order*/(uint8_t)AtomicOrdering::NotAtomic,
      GIM_CheckRegBankForClass, /*MI*/0, /*Op*/0, /*RC*/GIMT_Encode2(AMDGPU::AV_32RegClassID),
      GIM_CheckPointerToAny, /*MI*/0, /*Op*/1, /*SizeInBits*/0,
      GIM_CheckComplexPattern, /*MI*/0, /*Op*/1, /*Renderer*/GIMT_Encode2(0), GIMT_Encode2(GICP_gi_mubuf_offset),
      // (ld:{ *:[i32] } (MUBUFOffset:{ *:[iPTR] } v4i32:{ *:[v4i32] }:$srsrc, i32:{ *:[i32] }:$soffset, i32:{ *:[i32] }:$offset))<<P:Predicate_unindexedload>><<P:Predicate_load_global>>  =>  (BUFFER_LOAD_DWORD_OFFSET:{ *:[i32] } v4i32:{ *:[v4i32] }:$srsrc, i32:{ *:[i32] }:$soffset, i32:{ *:[i32] }:$offset)
      GIR_BuildMI, /*InsnID*/0, /*Opcode*/GIMT_Encode2(AMDGPU::BUFFER_LOAD_DWORD_OFFSET),
      GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/0, // DstI[vdata]
      GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/0, // srsrc
      GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/1, // soffset
      GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/2, // offset
      GIR_AddImm8, /*InsnID*/0, /*Imm*/0,
      GIR_AddImm8, /*InsnID*/0, /*Imm*/0,
      GIR_MergeMemOperands, /*InsnID*/0, /*NumInsns*/1, /*MergeInsnID's*/0,
      GIR_ConstrainSelectedInstOperands, /*InsnID*/0,
      GIR_EraseFromParent, /*InsnID*/0,
      // GIR_Coverage, 3683,
      GIR_Done,
    // Label 1121: @73863
    GIM_Try, /*On fail goto*//*Label 1122*/ GIMT_Encode4(73932), // Rule ID 3685 //
      GIM_CheckMemoryAddressSpace, /*MI*/0, /*MMO*/0, /*NumAddrSpace*/3, /*AddrSpace*/1, /*AddrSpace*/4, /*AddrSpace*/6,
      GIM_CheckAtomicOrdering, /*MI*/0, /*Order*/(uint8_t)AtomicOrdering::NotAtomic,
      GIM_CheckRegBankForClass, /*MI*/0, /*Op*/0, /*RC*/GIMT_Encode2(AMDGPU::AV_32RegClassID),
      GIM_CheckPointerToAny, /*MI*/0, /*Op*/1, /*SizeInBits*/0,
      GIM_CheckComplexPattern, /*MI*/0, /*Op*/1, /*Renderer*/GIMT_Encode2(0), GIMT_Encode2(GICP_gi_mubuf_offset),
      // (ld:{ *:[i32] } (MUBUFOffset:{ *:[iPTR] } v4i32:{ *:[v4i32] }:$srsrc, i32:{ *:[i32] }:$soffset, i32:{ *:[i32] }:$offset))<<P:Predicate_unindexedload>><<P:Predicate_load_global>>  =>  (BUFFER_LOAD_DWORD_VBUFFER_OFFSET:{ *:[i32] } v4i32:{ *:[v4i32] }:$srsrc, i32:{ *:[i32] }:$soffset, i32:{ *:[i32] }:$offset)
      GIR_BuildMI, /*InsnID*/0, /*Opcode*/GIMT_Encode2(AMDGPU::BUFFER_LOAD_DWORD_VBUFFER_OFFSET),
      GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/0, // DstI[vdata]
      GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/0, // srsrc
      GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/1, // soffset
      GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/2, // offset
      GIR_AddImm8, /*InsnID*/0, /*Imm*/0,
      GIR_AddImm8, /*InsnID*/0, /*Imm*/0,
      GIR_MergeMemOperands, /*InsnID*/0, /*NumInsns*/1, /*MergeInsnID's*/0,
      GIR_ConstrainSelectedInstOperands, /*InsnID*/0,
      GIR_EraseFromParent, /*InsnID*/0,
      // GIR_Coverage, 3685,
      GIR_Done,
    // Label 1122: @73932
    GIM_Try, /*On fail goto*//*Label 1123*/ GIMT_Encode4(74004), // Rule ID 3687 //
      GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasUnrestrictedSOffset),
      GIM_CheckMemoryAddressSpace, /*MI*/0, /*MMO*/0, /*NumAddrSpace*/3, /*AddrSpace*/1, /*AddrSpace*/4, /*AddrSpace*/6,
      GIM_CheckAtomicOrdering, /*MI*/0, /*Order*/(uint8_t)AtomicOrdering::NotAtomic,
      GIM_CheckRegBankForClass, /*MI*/0, /*Op*/0, /*RC*/GIMT_Encode2(AMDGPU::AV_32RegClassID),
      GIM_CheckPointerToAny, /*MI*/0, /*Op*/1, /*SizeInBits*/0,
      GIM_CheckComplexPattern, /*MI*/0, /*Op*/1, /*Renderer*/GIMT_Encode2(0), GIMT_Encode2(GICP_gi_mubuf_offset),
      // (ld:{ *:[f32] } (MUBUFOffset:{ *:[iPTR] } v4i32:{ *:[v4i32] }:$srsrc, i32:{ *:[i32] }:$soffset, i32:{ *:[i32] }:$offset))<<P:Predicate_unindexedload>><<P:Predicate_load_global>>  =>  (BUFFER_LOAD_DWORD_OFFSET:{ *:[f32] } v4i32:{ *:[v4i32] }:$srsrc, i32:{ *:[i32] }:$soffset, i32:{ *:[i32] }:$offset)
      GIR_BuildMI, /*InsnID*/0, /*Opcode*/GIMT_Encode2(AMDGPU::BUFFER_LOAD_DWORD_OFFSET),
      GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/0, // DstI[vdata]
      GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/0, // srsrc
      GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/1, // soffset
      GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/2, // offset
      GIR_AddImm8, /*InsnID*/0, /*Imm*/0,
      GIR_AddImm8, /*InsnID*/0, /*Imm*/0,
      GIR_MergeMemOperands, /*InsnID*/0, /*NumInsns*/1, /*MergeInsnID's*/0,
      GIR_ConstrainSelectedInstOperands, /*InsnID*/0,
      GIR_EraseFromParent, /*InsnID*/0,
      // GIR_Coverage, 3687,
      GIR_Done,
    // Label 1123: @74004
    GIM_Try, /*On fail goto*//*Label 1124*/ GIMT_Encode4(74073), // Rule ID 3689 //
      GIM_CheckMemoryAddressSpace, /*MI*/0, /*MMO*/0, /*NumAddrSpace*/3, /*AddrSpace*/1, /*AddrSpace*/4, /*AddrSpace*/6,
      GIM_CheckAtomicOrdering, /*MI*/0, /*Order*/(uint8_t)AtomicOrdering::NotAtomic,
      GIM_CheckRegBankForClass, /*MI*/0, /*Op*/0, /*RC*/GIMT_Encode2(AMDGPU::AV_32RegClassID),
      GIM_CheckPointerToAny, /*MI*/0, /*Op*/1, /*SizeInBits*/0,
      GIM_CheckComplexPattern, /*MI*/0, /*Op*/1, /*Renderer*/GIMT_Encode2(0), GIMT_Encode2(GICP_gi_mubuf_offset),
      // (ld:{ *:[f32] } (MUBUFOffset:{ *:[iPTR] } v4i32:{ *:[v4i32] }:$srsrc, i32:{ *:[i32] }:$soffset, i32:{ *:[i32] }:$offset))<<P:Predicate_unindexedload>><<P:Predicate_load_global>>  =>  (BUFFER_LOAD_DWORD_VBUFFER_OFFSET:{ *:[f32] } v4i32:{ *:[v4i32] }:$srsrc, i32:{ *:[i32] }:$soffset, i32:{ *:[i32] }:$offset)
      GIR_BuildMI, /*InsnID*/0, /*Opcode*/GIMT_Encode2(AMDGPU::BUFFER_LOAD_DWORD_VBUFFER_OFFSET),
      GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/0, // DstI[vdata]
      GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/0, // srsrc
      GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/1, // soffset
      GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/2, // offset
      GIR_AddImm8, /*InsnID*/0, /*Imm*/0,
      GIR_AddImm8, /*InsnID*/0, /*Imm*/0,
      GIR_MergeMemOperands, /*InsnID*/0, /*NumInsns*/1, /*MergeInsnID's*/0,
      GIR_ConstrainSelectedInstOperands, /*InsnID*/0,
      GIR_EraseFromParent, /*InsnID*/0,
      // GIR_Coverage, 3689,
      GIR_Done,
    // Label 1124: @74073
    GIM_Try, /*On fail goto*//*Label 1125*/ GIMT_Encode4(74142), // Rule ID 6609 //
      GIM_CheckFeatures, GIMT_Encode2(GIFBS_LDSRequiresM0Init),
      GIM_CheckMemorySizeEqualTo, /*MI*/0, /*MMO*/0, /*Size*/GIMT_Encode4(1),
      GIM_CheckMemoryAddressSpace, /*MI*/0, /*MMO*/0, /*NumAddrSpace*/1, /*AddrSpace*/3,
      GIM_CheckAtomicOrderingOrStrongerThan, /*MI*/0, /*Order*/(uint8_t)AtomicOrdering::Unordered,
      GIM_CheckRegBankForClass, /*MI*/0, /*Op*/0, /*RC*/GIMT_Encode2(AMDGPU::AV_32RegClassID),
      GIM_CheckPointerToAny, /*MI*/0, /*Op*/1, /*SizeInBits*/0,
      GIM_CheckComplexPattern, /*MI*/0, /*Op*/1, /*Renderer*/GIMT_Encode2(0), GIMT_Encode2(GICP_gi_ds_1addr_1offset),
      // (AMDGPUatomic_ld_glue:{ *:[i32] } (DS1Addr1Offset:{ *:[iPTR] } i32:{ *:[i32] }:$ptr, i32:{ *:[i32] }:$offset))<<P:Predicate_atomic_load_8_glue>><<P:Predicate_atomic_load_8_local_m0>>  =>  (DS_READ_U8:{ *:[i32] } ?:{ *:[i32] }:$ptr, offset:{ *:[i32] }:$offset, 0:{ *:[i1] })
      GIR_BuildMI, /*InsnID*/0, /*Opcode*/GIMT_Encode2(AMDGPU::DS_READ_U8),
      GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/0, // DstI[vdst]
      GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/0, // ptr
      GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/1, // offset
      GIR_AddImm8, /*InsnID*/0, /*Imm*/0,
      GIR_MergeMemOperands, /*InsnID*/0, /*NumInsns*/1, /*MergeInsnID's*/0,
      GIR_ConstrainSelectedInstOperands, /*InsnID*/0,
      GIR_EraseFromParent, /*InsnID*/0,
      // GIR_Coverage, 6609,
      GIR_Done,
    // Label 1125: @74142
    GIM_Try, /*On fail goto*//*Label 1126*/ GIMT_Encode4(74211), // Rule ID 6610 //
      GIM_CheckFeatures, GIMT_Encode2(GIFBS_NotLDSRequiresM0Init),
      GIM_CheckMemorySizeEqualTo, /*MI*/0, /*MMO*/0, /*Size*/GIMT_Encode4(1),
      GIM_CheckMemoryAddressSpace, /*MI*/0, /*MMO*/0, /*NumAddrSpace*/1, /*AddrSpace*/3,
      GIM_CheckAtomicOrderingOrStrongerThan, /*MI*/0, /*Order*/(uint8_t)AtomicOrdering::Unordered,
      GIM_CheckRegBankForClass, /*MI*/0, /*Op*/0, /*RC*/GIMT_Encode2(AMDGPU::AV_32RegClassID),
      GIM_CheckPointerToAny, /*MI*/0, /*Op*/1, /*SizeInBits*/0,
      GIM_CheckComplexPattern, /*MI*/0, /*Op*/1, /*Renderer*/GIMT_Encode2(0), GIMT_Encode2(GICP_gi_ds_1addr_1offset),
      // (atomic_load:{ *:[i32] } (DS1Addr1Offset:{ *:[iPTR] } i32:{ *:[i32] }:$ptr, i32:{ *:[i32] }:$offset))<<P:Predicate_atomic_load_8>><<P:Predicate_atomic_load_8_local>>  =>  (DS_READ_U8_gfx9:{ *:[i32] } ?:{ *:[i32] }:$ptr, offset:{ *:[i32] }:$offset, 0:{ *:[i1] })
      GIR_BuildMI, /*InsnID*/0, /*Opcode*/GIMT_Encode2(AMDGPU::DS_READ_U8_gfx9),
      GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/0, // DstI[vdst]
      GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/0, // ptr
      GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/1, // offset
      GIR_AddImm8, /*InsnID*/0, /*Imm*/0,
      GIR_MergeMemOperands, /*InsnID*/0, /*NumInsns*/1, /*MergeInsnID's*/0,
      GIR_ConstrainSelectedInstOperands, /*InsnID*/0,
      GIR_EraseFromParent, /*InsnID*/0,
      // GIR_Coverage, 6610,
      GIR_Done,
    // Label 1126: @74211
    GIM_Try, /*On fail goto*//*Label 1127*/ GIMT_Encode4(74280), // Rule ID 6613 //
      GIM_CheckFeatures, GIMT_Encode2(GIFBS_LDSRequiresM0Init),
      GIM_CheckMemorySizeEqualTo, /*MI*/0, /*MMO*/0, /*Size*/GIMT_Encode4(2),
      GIM_CheckMemoryAddressSpace, /*MI*/0, /*MMO*/0, /*NumAddrSpace*/1, /*AddrSpace*/3,
      GIM_CheckAtomicOrderingOrStrongerThan, /*MI*/0, /*Order*/(uint8_t)AtomicOrdering::Unordered,
      GIM_CheckRegBankForClass, /*MI*/0, /*Op*/0, /*RC*/GIMT_Encode2(AMDGPU::AV_32RegClassID),
      GIM_CheckPointerToAny, /*MI*/0, /*Op*/1, /*SizeInBits*/0,
      GIM_CheckComplexPattern, /*MI*/0, /*Op*/1, /*Renderer*/GIMT_Encode2(0), GIMT_Encode2(GICP_gi_ds_1addr_1offset),
      // (AMDGPUatomic_ld_glue:{ *:[i32] } (DS1Addr1Offset:{ *:[iPTR] } i32:{ *:[i32] }:$ptr, i32:{ *:[i32] }:$offset))<<P:Predicate_atomic_load_16_glue>><<P:Predicate_atomic_load_16_local_m0>>  =>  (DS_READ_U16:{ *:[i32] } ?:{ *:[i32] }:$ptr, offset:{ *:[i32] }:$offset, 0:{ *:[i1] })
      GIR_BuildMI, /*InsnID*/0, /*Opcode*/GIMT_Encode2(AMDGPU::DS_READ_U16),
      GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/0, // DstI[vdst]
      GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/0, // ptr
      GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/1, // offset
      GIR_AddImm8, /*InsnID*/0, /*Imm*/0,
      GIR_MergeMemOperands, /*InsnID*/0, /*NumInsns*/1, /*MergeInsnID's*/0,
      GIR_ConstrainSelectedInstOperands, /*InsnID*/0,
      GIR_EraseFromParent, /*InsnID*/0,
      // GIR_Coverage, 6613,
      GIR_Done,
    // Label 1127: @74280
    GIM_Try, /*On fail goto*//*Label 1128*/ GIMT_Encode4(74349), // Rule ID 6614 //
      GIM_CheckFeatures, GIMT_Encode2(GIFBS_NotLDSRequiresM0Init),
      GIM_CheckMemorySizeEqualTo, /*MI*/0, /*MMO*/0, /*Size*/GIMT_Encode4(2),
      GIM_CheckMemoryAddressSpace, /*MI*/0, /*MMO*/0, /*NumAddrSpace*/1, /*AddrSpace*/3,
      GIM_CheckAtomicOrderingOrStrongerThan, /*MI*/0, /*Order*/(uint8_t)AtomicOrdering::Unordered,
      GIM_CheckRegBankForClass, /*MI*/0, /*Op*/0, /*RC*/GIMT_Encode2(AMDGPU::AV_32RegClassID),
      GIM_CheckPointerToAny, /*MI*/0, /*Op*/1, /*SizeInBits*/0,
      GIM_CheckComplexPattern, /*MI*/0, /*Op*/1, /*Renderer*/GIMT_Encode2(0), GIMT_Encode2(GICP_gi_ds_1addr_1offset),
      // (atomic_load:{ *:[i32] } (DS1Addr1Offset:{ *:[iPTR] } i32:{ *:[i32] }:$ptr, i32:{ *:[i32] }:$offset))<<P:Predicate_atomic_load_16>><<P:Predicate_atomic_load_16_local>>  =>  (DS_READ_U16_gfx9:{ *:[i32] } ?:{ *:[i32] }:$ptr, offset:{ *:[i32] }:$offset, 0:{ *:[i1] })
      GIR_BuildMI, /*InsnID*/0, /*Opcode*/GIMT_Encode2(AMDGPU::DS_READ_U16_gfx9),
      GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/0, // DstI[vdst]
      GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/0, // ptr
      GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/1, // offset
      GIR_AddImm8, /*InsnID*/0, /*Imm*/0,
      GIR_MergeMemOperands, /*InsnID*/0, /*NumInsns*/1, /*MergeInsnID's*/0,
      GIR_ConstrainSelectedInstOperands, /*InsnID*/0,
      GIR_EraseFromParent, /*InsnID*/0,
      // GIR_Coverage, 6614,
      GIR_Done,
    // Label 1128: @74349
    GIM_Try, /*On fail goto*//*Label 1129*/ GIMT_Encode4(74418), // Rule ID 6615 //
      GIM_CheckFeatures, GIMT_Encode2(GIFBS_LDSRequiresM0Init),
      GIM_CheckMemorySizeEqualTo, /*MI*/0, /*MMO*/0, /*Size*/GIMT_Encode4(4),
      GIM_CheckMemoryAddressSpace, /*MI*/0, /*MMO*/0, /*NumAddrSpace*/1, /*AddrSpace*/3,
      GIM_CheckAtomicOrderingOrStrongerThan, /*MI*/0, /*Order*/(uint8_t)AtomicOrdering::Unordered,
      GIM_CheckRegBankForClass, /*MI*/0, /*Op*/0, /*RC*/GIMT_Encode2(AMDGPU::AV_32RegClassID),
      GIM_CheckPointerToAny, /*MI*/0, /*Op*/1, /*SizeInBits*/0,
      GIM_CheckComplexPattern, /*MI*/0, /*Op*/1, /*Renderer*/GIMT_Encode2(0), GIMT_Encode2(GICP_gi_ds_1addr_1offset),
      // (AMDGPUatomic_ld_glue:{ *:[i32] } (DS1Addr1Offset:{ *:[iPTR] } i32:{ *:[i32] }:$ptr, i32:{ *:[i32] }:$offset))<<P:Predicate_atomic_load_32_glue>><<P:Predicate_atomic_load_32_local_m0>>  =>  (DS_READ_B32:{ *:[i32] } ?:{ *:[i32] }:$ptr, offset:{ *:[i32] }:$offset, 0:{ *:[i1] })
      GIR_BuildMI, /*InsnID*/0, /*Opcode*/GIMT_Encode2(AMDGPU::DS_READ_B32),
      GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/0, // DstI[vdst]
      GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/0, // ptr
      GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/1, // offset
      GIR_AddImm8, /*InsnID*/0, /*Imm*/0,
      GIR_MergeMemOperands, /*InsnID*/0, /*NumInsns*/1, /*MergeInsnID's*/0,
      GIR_ConstrainSelectedInstOperands, /*InsnID*/0,
      GIR_EraseFromParent, /*InsnID*/0,
      // GIR_Coverage, 6615,
      GIR_Done,
    // Label 1129: @74418
    GIM_Try, /*On fail goto*//*Label 1130*/ GIMT_Encode4(74487), // Rule ID 6616 //
      GIM_CheckFeatures, GIMT_Encode2(GIFBS_NotLDSRequiresM0Init),
      GIM_CheckMemorySizeEqualTo, /*MI*/0, /*MMO*/0, /*Size*/GIMT_Encode4(4),
      GIM_CheckMemoryAddressSpace, /*MI*/0, /*MMO*/0, /*NumAddrSpace*/1, /*AddrSpace*/3,
      GIM_CheckAtomicOrderingOrStrongerThan, /*MI*/0, /*Order*/(uint8_t)AtomicOrdering::Unordered,
      GIM_CheckRegBankForClass, /*MI*/0, /*Op*/0, /*RC*/GIMT_Encode2(AMDGPU::AV_32RegClassID),
      GIM_CheckPointerToAny, /*MI*/0, /*Op*/1, /*SizeInBits*/0,
      GIM_CheckComplexPattern, /*MI*/0, /*Op*/1, /*Renderer*/GIMT_Encode2(0), GIMT_Encode2(GICP_gi_ds_1addr_1offset),
      // (atomic_load:{ *:[i32] } (DS1Addr1Offset:{ *:[iPTR] } i32:{ *:[i32] }:$ptr, i32:{ *:[i32] }:$offset))<<P:Predicate_atomic_load_32>><<P:Predicate_atomic_load_32_local>>  =>  (DS_READ_B32_gfx9:{ *:[i32] } ?:{ *:[i32] }:$ptr, offset:{ *:[i32] }:$offset, 0:{ *:[i1] })
      GIR_BuildMI, /*InsnID*/0, /*Opcode*/GIMT_Encode2(AMDGPU::DS_READ_B32_gfx9),
      GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/0, // DstI[vdst]
      GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/0, // ptr
      GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/1, // offset
      GIR_AddImm8, /*InsnID*/0, /*Imm*/0,
      GIR_MergeMemOperands, /*InsnID*/0, /*NumInsns*/1, /*MergeInsnID's*/0,
      GIR_ConstrainSelectedInstOperands, /*InsnID*/0,
      GIR_EraseFromParent, /*InsnID*/0,
      // GIR_Coverage, 6616,
      GIR_Done,
    // Label 1130: @74487
    GIM_Try, /*On fail goto*//*Label 1131*/ GIMT_Encode4(74560), // Rule ID 6571 //
      GIM_CheckFeatures, GIMT_Encode2(GIFBS_LDSRequiresM0Init),
      GIM_CheckMemorySizeLessThanLLT, /*MI*/0, /*MMO*/0, /*OpIdx*/0,
      GIM_CheckMemorySizeEqualTo, /*MI*/0, /*MMO*/0, /*Size*/GIMT_Encode4(1),
      GIM_CheckMemoryAddressSpace, /*MI*/0, /*MMO*/0, /*NumAddrSpace*/1, /*AddrSpace*/3,
      GIM_CheckAtomicOrdering, /*MI*/0, /*Order*/(uint8_t)AtomicOrdering::NotAtomic,
      GIM_CheckRegBankForClass, /*MI*/0, /*Op*/0, /*RC*/GIMT_Encode2(AMDGPU::AV_32RegClassID),
      GIM_CheckPointerToAny, /*MI*/0, /*Op*/1, /*SizeInBits*/0,
      GIM_CheckComplexPattern, /*MI*/0, /*Op*/1, /*Renderer*/GIMT_Encode2(0), GIMT_Encode2(GICP_gi_ds_1addr_1offset),
      // (AMDGPUld_glue:{ *:[i32] } (DS1Addr1Offset:{ *:[iPTR] } i32:{ *:[i32] }:$ptr, i32:{ *:[i32] }:$offset))<<P:Predicate_unindexedload_glue>><<P:Predicate_extload_glue>><<P:Predicate_extloadi8_glue>><<P:Predicate_extloadi8_local_m0>>  =>  (DS_READ_U8:{ *:[i32] } ?:{ *:[i32] }:$ptr, offset:{ *:[i32] }:$offset, 0:{ *:[i1] })
      GIR_BuildMI, /*InsnID*/0, /*Opcode*/GIMT_Encode2(AMDGPU::DS_READ_U8),
      GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/0, // DstI[vdst]
      GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/0, // ptr
      GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/1, // offset
      GIR_AddImm8, /*InsnID*/0, /*Imm*/0,
      GIR_MergeMemOperands, /*InsnID*/0, /*NumInsns*/1, /*MergeInsnID's*/0,
      GIR_ConstrainSelectedInstOperands, /*InsnID*/0,
      GIR_EraseFromParent, /*InsnID*/0,
      // GIR_Coverage, 6571,
      GIR_Done,
    // Label 1131: @74560
    GIM_Try, /*On fail goto*//*Label 1132*/ GIMT_Encode4(74633), // Rule ID 6572 //
      GIM_CheckFeatures, GIMT_Encode2(GIFBS_NotLDSRequiresM0Init),
      GIM_CheckMemorySizeLessThanLLT, /*MI*/0, /*MMO*/0, /*OpIdx*/0,
      GIM_CheckMemorySizeEqualTo, /*MI*/0, /*MMO*/0, /*Size*/GIMT_Encode4(1),
      GIM_CheckMemoryAddressSpace, /*MI*/0, /*MMO*/0, /*NumAddrSpace*/1, /*AddrSpace*/3,
      GIM_CheckAtomicOrdering, /*MI*/0, /*Order*/(uint8_t)AtomicOrdering::NotAtomic,
      GIM_CheckRegBankForClass, /*MI*/0, /*Op*/0, /*RC*/GIMT_Encode2(AMDGPU::AV_32RegClassID),
      GIM_CheckPointerToAny, /*MI*/0, /*Op*/1, /*SizeInBits*/0,
      GIM_CheckComplexPattern, /*MI*/0, /*Op*/1, /*Renderer*/GIMT_Encode2(0), GIMT_Encode2(GICP_gi_ds_1addr_1offset),
      // (ld:{ *:[i32] } (DS1Addr1Offset:{ *:[iPTR] } i32:{ *:[i32] }:$ptr, i32:{ *:[i32] }:$offset))<<P:Predicate_unindexedload>><<P:Predicate_extload>><<P:Predicate_extloadi8>><<P:Predicate_extloadi8_local>>  =>  (DS_READ_U8_gfx9:{ *:[i32] } ?:{ *:[i32] }:$ptr, offset:{ *:[i32] }:$offset, 0:{ *:[i1] })
      GIR_BuildMI, /*InsnID*/0, /*Opcode*/GIMT_Encode2(AMDGPU::DS_READ_U8_gfx9),
      GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/0, // DstI[vdst]
      GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/0, // ptr
      GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/1, // offset
      GIR_AddImm8, /*InsnID*/0, /*Imm*/0,
      GIR_MergeMemOperands, /*InsnID*/0, /*NumInsns*/1, /*MergeInsnID's*/0,
      GIR_ConstrainSelectedInstOperands, /*InsnID*/0,
      GIR_EraseFromParent, /*InsnID*/0,
      // GIR_Coverage, 6572,
      GIR_Done,
    // Label 1132: @74633
    GIM_Try, /*On fail goto*//*Label 1133*/ GIMT_Encode4(74706), // Rule ID 6583 //
      GIM_CheckFeatures, GIMT_Encode2(GIFBS_LDSRequiresM0Init),
      GIM_CheckMemorySizeLessThanLLT, /*MI*/0, /*MMO*/0, /*OpIdx*/0,
      GIM_CheckMemorySizeEqualTo, /*MI*/0, /*MMO*/0, /*Size*/GIMT_Encode4(2),
      GIM_CheckMemoryAddressSpace, /*MI*/0, /*MMO*/0, /*NumAddrSpace*/1, /*AddrSpace*/3,
      GIM_CheckAtomicOrdering, /*MI*/0, /*Order*/(uint8_t)AtomicOrdering::NotAtomic,
      GIM_CheckRegBankForClass, /*MI*/0, /*Op*/0, /*RC*/GIMT_Encode2(AMDGPU::AV_32RegClassID),
      GIM_CheckPointerToAny, /*MI*/0, /*Op*/1, /*SizeInBits*/0,
      GIM_CheckComplexPattern, /*MI*/0, /*Op*/1, /*Renderer*/GIMT_Encode2(0), GIMT_Encode2(GICP_gi_ds_1addr_1offset),
      // (AMDGPUld_glue:{ *:[i32] } (DS1Addr1Offset:{ *:[iPTR] } i32:{ *:[i32] }:$ptr, i32:{ *:[i32] }:$offset))<<P:Predicate_unindexedload_glue>><<P:Predicate_extload_glue>><<P:Predicate_extloadi16_glue>><<P:Predicate_extloadi16_local_m0>>  =>  (DS_READ_U16:{ *:[i32] } ?:{ *:[i32] }:$ptr, offset:{ *:[i32] }:$offset, 0:{ *:[i1] })
      GIR_BuildMI, /*InsnID*/0, /*Opcode*/GIMT_Encode2(AMDGPU::DS_READ_U16),
      GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/0, // DstI[vdst]
      GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/0, // ptr
      GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/1, // offset
      GIR_AddImm8, /*InsnID*/0, /*Imm*/0,
      GIR_MergeMemOperands, /*InsnID*/0, /*NumInsns*/1, /*MergeInsnID's*/0,
      GIR_ConstrainSelectedInstOperands, /*InsnID*/0,
      GIR_EraseFromParent, /*InsnID*/0,
      // GIR_Coverage, 6583,
      GIR_Done,
    // Label 1133: @74706
    GIM_Try, /*On fail goto*//*Label 1134*/ GIMT_Encode4(74779), // Rule ID 6584 //
      GIM_CheckFeatures, GIMT_Encode2(GIFBS_NotLDSRequiresM0Init),
      GIM_CheckMemorySizeLessThanLLT, /*MI*/0, /*MMO*/0, /*OpIdx*/0,
      GIM_CheckMemorySizeEqualTo, /*MI*/0, /*MMO*/0, /*Size*/GIMT_Encode4(2),
      GIM_CheckMemoryAddressSpace, /*MI*/0, /*MMO*/0, /*NumAddrSpace*/1, /*AddrSpace*/3,
      GIM_CheckAtomicOrdering, /*MI*/0, /*Order*/(uint8_t)AtomicOrdering::NotAtomic,
      GIM_CheckRegBankForClass, /*MI*/0, /*Op*/0, /*RC*/GIMT_Encode2(AMDGPU::AV_32RegClassID),
      GIM_CheckPointerToAny, /*MI*/0, /*Op*/1, /*SizeInBits*/0,
      GIM_CheckComplexPattern, /*MI*/0, /*Op*/1, /*Renderer*/GIMT_Encode2(0), GIMT_Encode2(GICP_gi_ds_1addr_1offset),
      // (ld:{ *:[i32] } (DS1Addr1Offset:{ *:[iPTR] } i32:{ *:[i32] }:$ptr, i32:{ *:[i32] }:$offset))<<P:Predicate_unindexedload>><<P:Predicate_extload>><<P:Predicate_extloadi16>><<P:Predicate_extloadi16_local>>  =>  (DS_READ_U16_gfx9:{ *:[i32] } ?:{ *:[i32] }:$ptr, offset:{ *:[i32] }:$offset, 0:{ *:[i1] })
      GIR_BuildMI, /*InsnID*/0, /*Opcode*/GIMT_Encode2(AMDGPU::DS_READ_U16_gfx9),
      GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/0, // DstI[vdst]
      GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/0, // ptr
      GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/1, // offset
      GIR_AddImm8, /*InsnID*/0, /*Imm*/0,
      GIR_MergeMemOperands, /*InsnID*/0, /*NumInsns*/1, /*MergeInsnID's*/0,
      GIR_ConstrainSelectedInstOperands, /*InsnID*/0,
      GIR_EraseFromParent, /*InsnID*/0,
      // GIR_Coverage, 6584,
      GIR_Done,
    // Label 1134: @74779
    GIM_Try, /*On fail goto*//*Label 1135*/ GIMT_Encode4(74845), // Rule ID 6589 //
      GIM_CheckFeatures, GIMT_Encode2(GIFBS_LDSRequiresM0Init),
      GIM_CheckMemorySizeEqualToLLT, /*MI*/0, /*MMO*/0, /*OpIdx*/0,
      GIM_CheckMemoryAddressSpace, /*MI*/0, /*MMO*/0, /*NumAddrSpace*/1, /*AddrSpace*/3,
      GIM_CheckAtomicOrdering, /*MI*/0, /*Order*/(uint8_t)AtomicOrdering::NotAtomic,
      GIM_CheckRegBankForClass, /*MI*/0, /*Op*/0, /*RC*/GIMT_Encode2(AMDGPU::AV_32RegClassID),
      GIM_CheckPointerToAny, /*MI*/0, /*Op*/1, /*SizeInBits*/0,
      GIM_CheckComplexPattern, /*MI*/0, /*Op*/1, /*Renderer*/GIMT_Encode2(0), GIMT_Encode2(GICP_gi_ds_1addr_1offset),
      // (AMDGPUld_glue:{ *:[i32] } (DS1Addr1Offset:{ *:[iPTR] } i32:{ *:[i32] }:$ptr, i32:{ *:[i32] }:$offset))<<P:Predicate_unindexedload_glue>><<P:Predicate_load_glue>><<P:Predicate_load_local_m0>>  =>  (DS_READ_B32:{ *:[i32] } ?:{ *:[i32] }:$ptr, offset:{ *:[i32] }:$offset, 0:{ *:[i1] })
      GIR_BuildMI, /*InsnID*/0, /*Opcode*/GIMT_Encode2(AMDGPU::DS_READ_B32),
      GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/0, // DstI[vdst]
      GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/0, // ptr
      GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/1, // offset
      GIR_AddImm8, /*InsnID*/0, /*Imm*/0,
      GIR_MergeMemOperands, /*InsnID*/0, /*NumInsns*/1, /*MergeInsnID's*/0,
      GIR_ConstrainSelectedInstOperands, /*InsnID*/0,
      GIR_EraseFromParent, /*InsnID*/0,
      // GIR_Coverage, 6589,
      GIR_Done,
    // Label 1135: @74845
    GIM_Try, /*On fail goto*//*Label 1136*/ GIMT_Encode4(74911), // Rule ID 6591 //
      GIM_CheckFeatures, GIMT_Encode2(GIFBS_LDSRequiresM0Init),
      GIM_CheckMemorySizeEqualToLLT, /*MI*/0, /*MMO*/0, /*OpIdx*/0,
      GIM_CheckMemoryAddressSpace, /*MI*/0, /*MMO*/0, /*NumAddrSpace*/1, /*AddrSpace*/3,
      GIM_CheckAtomicOrdering, /*MI*/0, /*Order*/(uint8_t)AtomicOrdering::NotAtomic,
      GIM_CheckRegBankForClass, /*MI*/0, /*Op*/0, /*RC*/GIMT_Encode2(AMDGPU::AV_32RegClassID),
      GIM_CheckPointerToAny, /*MI*/0, /*Op*/1, /*SizeInBits*/0,
      GIM_CheckComplexPattern, /*MI*/0, /*Op*/1, /*Renderer*/GIMT_Encode2(0), GIMT_Encode2(GICP_gi_ds_1addr_1offset),
      // (AMDGPUld_glue:{ *:[f32] } (DS1Addr1Offset:{ *:[iPTR] } i32:{ *:[i32] }:$ptr, i32:{ *:[i32] }:$offset))<<P:Predicate_unindexedload_glue>><<P:Predicate_load_glue>><<P:Predicate_load_local_m0>>  =>  (DS_READ_B32:{ *:[f32] } ?:{ *:[i32] }:$ptr, offset:{ *:[i32] }:$offset, 0:{ *:[i1] })
      GIR_BuildMI, /*InsnID*/0, /*Opcode*/GIMT_Encode2(AMDGPU::DS_READ_B32),
      GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/0, // DstI[vdst]
      GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/0, // ptr
      GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/1, // offset
      GIR_AddImm8, /*InsnID*/0, /*Imm*/0,
      GIR_MergeMemOperands, /*InsnID*/0, /*NumInsns*/1, /*MergeInsnID's*/0,
      GIR_ConstrainSelectedInstOperands, /*InsnID*/0,
      GIR_EraseFromParent, /*InsnID*/0,
      // GIR_Coverage, 6591,
      GIR_Done,
    // Label 1136: @74911
    GIM_Try, /*On fail goto*//*Label 1137*/ GIMT_Encode4(74973), // Rule ID 6590 //
      GIM_CheckFeatures, GIMT_Encode2(GIFBS_NotLDSRequiresM0Init),
      GIM_CheckMemoryAddressSpace, /*MI*/0, /*MMO*/0, /*NumAddrSpace*/1, /*AddrSpace*/3,
      GIM_CheckAtomicOrdering, /*MI*/0, /*Order*/(uint8_t)AtomicOrdering::NotAtomic,
      GIM_CheckRegBankForClass, /*MI*/0, /*Op*/0, /*RC*/GIMT_Encode2(AMDGPU::AV_32RegClassID),
      GIM_CheckPointerToAny, /*MI*/0, /*Op*/1, /*SizeInBits*/0,
      GIM_CheckComplexPattern, /*MI*/0, /*Op*/1, /*Renderer*/GIMT_Encode2(0), GIMT_Encode2(GICP_gi_ds_1addr_1offset),
      // (ld:{ *:[i32] } (DS1Addr1Offset:{ *:[iPTR] } i32:{ *:[i32] }:$ptr, i32:{ *:[i32] }:$offset))<<P:Predicate_unindexedload>><<P:Predicate_load_local>>  =>  (DS_READ_B32_gfx9:{ *:[i32] } ?:{ *:[i32] }:$ptr, offset:{ *:[i32] }:$offset, 0:{ *:[i1] })
      GIR_BuildMI, /*InsnID*/0, /*Opcode*/GIMT_Encode2(AMDGPU::DS_READ_B32_gfx9),
      GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/0, // DstI[vdst]
      GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/0, // ptr
      GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/1, // offset
      GIR_AddImm8, /*InsnID*/0, /*Imm*/0,
      GIR_MergeMemOperands, /*InsnID*/0, /*NumInsns*/1, /*MergeInsnID's*/0,
      GIR_ConstrainSelectedInstOperands, /*InsnID*/0,
      GIR_EraseFromParent, /*InsnID*/0,
      // GIR_Coverage, 6590,
      GIR_Done,
    // Label 1137: @74973
    GIM_Try, /*On fail goto*//*Label 1138*/ GIMT_Encode4(75035), // Rule ID 6592 //
      GIM_CheckFeatures, GIMT_Encode2(GIFBS_NotLDSRequiresM0Init),
      GIM_CheckMemoryAddressSpace, /*MI*/0, /*MMO*/0, /*NumAddrSpace*/1, /*AddrSpace*/3,
      GIM_CheckAtomicOrdering, /*MI*/0, /*Order*/(uint8_t)AtomicOrdering::NotAtomic,
      GIM_CheckRegBankForClass, /*MI*/0, /*Op*/0, /*RC*/GIMT_Encode2(AMDGPU::AV_32RegClassID),
      GIM_CheckPointerToAny, /*MI*/0, /*Op*/1, /*SizeInBits*/0,
      GIM_CheckComplexPattern, /*MI*/0, /*Op*/1, /*Renderer*/GIMT_Encode2(0), GIMT_Encode2(GICP_gi_ds_1addr_1offset),
      // (ld:{ *:[f32] } (DS1Addr1Offset:{ *:[iPTR] } i32:{ *:[i32] }:$ptr, i32:{ *:[i32] }:$offset))<<P:Predicate_unindexedload>><<P:Predicate_load_local>>  =>  (DS_READ_B32_gfx9:{ *:[f32] } ?:{ *:[i32] }:$ptr, offset:{ *:[i32] }:$offset, 0:{ *:[i1] })
      GIR_BuildMI, /*InsnID*/0, /*Opcode*/GIMT_Encode2(AMDGPU::DS_READ_B32_gfx9),
      GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/0, // DstI[vdst]
      GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/0, // ptr
      GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/1, // offset
      GIR_AddImm8, /*InsnID*/0, /*Imm*/0,
      GIR_MergeMemOperands, /*InsnID*/0, /*NumInsns*/1, /*MergeInsnID's*/0,
      GIR_ConstrainSelectedInstOperands, /*InsnID*/0,
      GIR_EraseFromParent, /*InsnID*/0,
      // GIR_Coverage, 6592,
      GIR_Done,
    // Label 1138: @75035
    GIM_Try, /*On fail goto*//*Label 1139*/ GIMT_Encode4(75111), // Rule ID 2950 //
      GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasFlatGlobalInsts),
      GIM_CheckMemorySizeEqualTo, /*MI*/0, /*MMO*/0, /*Size*/GIMT_Encode4(1),
      GIM_CheckMemoryAddressSpace, /*MI*/0, /*MMO*/0, /*NumAddrSpace*/3, /*AddrSpace*/1, /*AddrSpace*/4, /*AddrSpace*/6,
      GIM_CheckAtomicOrderingOrStrongerThan, /*MI*/0, /*Order*/(uint8_t)AtomicOrdering::Unordered,
      GIM_CheckRegBankForClass, /*MI*/0, /*Op*/0, /*RC*/GIMT_Encode2(AMDGPU::AV_32RegClassID),
      GIM_CheckPointerToAny, /*MI*/0, /*Op*/1, /*SizeInBits*/0,
      GIM_CheckComplexPattern, /*MI*/0, /*Op*/1, /*Renderer*/GIMT_Encode2(0), GIMT_Encode2(GICP_gi_global_saddr),
      // (atomic_load:{ *:[i32] } (GlobalSAddr:{ *:[iPTR] } SReg_64:{ *:[i64] }:$saddr, VGPR_32:{ *:[i32] }:$voffset, i32:{ *:[i32] }:$offset))<<P:Predicate_atomic_load_8>><<P:Predicate_atomic_load_8_global>>  =>  (GLOBAL_LOAD_UBYTE_SADDR:{ *:[i32] } ?:{ *:[i64] }:$saddr, ?:{ *:[i32] }:$voffset, ?:{ *:[i32] }:$offset, 0:{ *:[i32] })
      GIR_BuildMI, /*InsnID*/0, /*Opcode*/GIMT_Encode2(AMDGPU::GLOBAL_LOAD_UBYTE_SADDR),
      GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/0, // DstI[vdst]
      GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/0, // saddr
      GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/1, // voffset
      GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/2, // offset
      GIR_AddImm8, /*InsnID*/0, /*Imm*/0,
      GIR_MergeMemOperands, /*InsnID*/0, /*NumInsns*/1, /*MergeInsnID's*/0,
      GIR_ConstrainSelectedInstOperands, /*InsnID*/0,
      GIR_EraseFromParent, /*InsnID*/0,
      // GIR_Coverage, 2950,
      GIR_Done,
    // Label 1139: @75111
    GIM_Try, /*On fail goto*//*Label 1140*/ GIMT_Encode4(75187), // Rule ID 2971 //
      GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasFlatGlobalInsts),
      GIM_CheckMemorySizeEqualTo, /*MI*/0, /*MMO*/0, /*Size*/GIMT_Encode4(2),
      GIM_CheckMemoryAddressSpace, /*MI*/0, /*MMO*/0, /*NumAddrSpace*/3, /*AddrSpace*/1, /*AddrSpace*/4, /*AddrSpace*/6,
      GIM_CheckAtomicOrderingOrStrongerThan, /*MI*/0, /*Order*/(uint8_t)AtomicOrdering::Unordered,
      GIM_CheckRegBankForClass, /*MI*/0, /*Op*/0, /*RC*/GIMT_Encode2(AMDGPU::AV_32RegClassID),
      GIM_CheckPointerToAny, /*MI*/0, /*Op*/1, /*SizeInBits*/0,
      GIM_CheckComplexPattern, /*MI*/0, /*Op*/1, /*Renderer*/GIMT_Encode2(0), GIMT_Encode2(GICP_gi_global_saddr),
      // (atomic_load:{ *:[i32] } (GlobalSAddr:{ *:[iPTR] } SReg_64:{ *:[i64] }:$saddr, VGPR_32:{ *:[i32] }:$voffset, i32:{ *:[i32] }:$offset))<<P:Predicate_atomic_load_16>><<P:Predicate_atomic_load_16_global>>  =>  (GLOBAL_LOAD_USHORT_SADDR:{ *:[i32] } ?:{ *:[i64] }:$saddr, ?:{ *:[i32] }:$voffset, ?:{ *:[i32] }:$offset, 0:{ *:[i32] })
      GIR_BuildMI, /*InsnID*/0, /*Opcode*/GIMT_Encode2(AMDGPU::GLOBAL_LOAD_USHORT_SADDR),
      GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/0, // DstI[vdst]
      GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/0, // saddr
      GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/1, // voffset
      GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/2, // offset
      GIR_AddImm8, /*InsnID*/0, /*Imm*/0,
      GIR_MergeMemOperands, /*InsnID*/0, /*NumInsns*/1, /*MergeInsnID's*/0,
      GIR_ConstrainSelectedInstOperands, /*InsnID*/0,
      GIR_EraseFromParent, /*InsnID*/0,
      // GIR_Coverage, 2971,
      GIR_Done,
    // Label 1140: @75187
    GIM_Try, /*On fail goto*//*Label 1141*/ GIMT_Encode4(75263), // Rule ID 3099 //
      GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasFlatGlobalInsts),
      GIM_CheckMemorySizeEqualTo, /*MI*/0, /*MMO*/0, /*Size*/GIMT_Encode4(4),
      GIM_CheckMemoryAddressSpace, /*MI*/0, /*MMO*/0, /*NumAddrSpace*/3, /*AddrSpace*/1, /*AddrSpace*/4, /*AddrSpace*/6,
      GIM_CheckAtomicOrderingOrStrongerThan, /*MI*/0, /*Order*/(uint8_t)AtomicOrdering::Unordered,
      GIM_CheckRegBankForClass, /*MI*/0, /*Op*/0, /*RC*/GIMT_Encode2(AMDGPU::AV_32RegClassID),
      GIM_CheckPointerToAny, /*MI*/0, /*Op*/1, /*SizeInBits*/0,
      GIM_CheckComplexPattern, /*MI*/0, /*Op*/1, /*Renderer*/GIMT_Encode2(0), GIMT_Encode2(GICP_gi_global_saddr),
      // (atomic_load:{ *:[i32] } (GlobalSAddr:{ *:[iPTR] } SReg_64:{ *:[i64] }:$saddr, VGPR_32:{ *:[i32] }:$voffset, i32:{ *:[i32] }:$offset))<<P:Predicate_atomic_load_32>><<P:Predicate_atomic_load_32_global>>  =>  (GLOBAL_LOAD_DWORD_SADDR:{ *:[i32] } ?:{ *:[i64] }:$saddr, ?:{ *:[i32] }:$voffset, ?:{ *:[i32] }:$offset, 0:{ *:[i32] })
      GIR_BuildMI, /*InsnID*/0, /*Opcode*/GIMT_Encode2(AMDGPU::GLOBAL_LOAD_DWORD_SADDR),
      GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/0, // DstI[vdst]
      GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/0, // saddr
      GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/1, // voffset
      GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/2, // offset
      GIR_AddImm8, /*InsnID*/0, /*Imm*/0,
      GIR_MergeMemOperands, /*InsnID*/0, /*NumInsns*/1, /*MergeInsnID's*/0,
      GIR_ConstrainSelectedInstOperands, /*InsnID*/0,
      GIR_EraseFromParent, /*InsnID*/0,
      // GIR_Coverage, 3099,
      GIR_Done,
    // Label 1141: @75263
    GIM_Try, /*On fail goto*//*Label 1142*/ GIMT_Encode4(75343), // Rule ID 2975 //
      GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasFlatGlobalInsts),
      GIM_CheckMemorySizeLessThanLLT, /*MI*/0, /*MMO*/0, /*OpIdx*/0,
      GIM_CheckMemorySizeEqualTo, /*MI*/0, /*MMO*/0, /*Size*/GIMT_Encode4(1),
      GIM_CheckMemoryAddressSpace, /*MI*/0, /*MMO*/0, /*NumAddrSpace*/3, /*AddrSpace*/1, /*AddrSpace*/4, /*AddrSpace*/6,
      GIM_CheckAtomicOrdering, /*MI*/0, /*Order*/(uint8_t)AtomicOrdering::NotAtomic,
      GIM_CheckRegBankForClass, /*MI*/0, /*Op*/0, /*RC*/GIMT_Encode2(AMDGPU::AV_32RegClassID),
      GIM_CheckPointerToAny, /*MI*/0, /*Op*/1, /*SizeInBits*/0,
      GIM_CheckComplexPattern, /*MI*/0, /*Op*/1, /*Renderer*/GIMT_Encode2(0), GIMT_Encode2(GICP_gi_global_saddr),
      // (ld:{ *:[i32] } (GlobalSAddr:{ *:[iPTR] } SReg_64:{ *:[i64] }:$saddr, VGPR_32:{ *:[i32] }:$voffset, i32:{ *:[i32] }:$offset))<<P:Predicate_unindexedload>><<P:Predicate_extload>><<P:Predicate_extloadi8>><<P:Predicate_extloadi8_global>>  =>  (GLOBAL_LOAD_UBYTE_SADDR:{ *:[i32] } ?:{ *:[i64] }:$saddr, ?:{ *:[i32] }:$voffset, ?:{ *:[i32] }:$offset, 0:{ *:[i32] })
      GIR_BuildMI, /*InsnID*/0, /*Opcode*/GIMT_Encode2(AMDGPU::GLOBAL_LOAD_UBYTE_SADDR),
      GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/0, // DstI[vdst]
      GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/0, // saddr
      GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/1, // voffset
      GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/2, // offset
      GIR_AddImm8, /*InsnID*/0, /*Imm*/0,
      GIR_MergeMemOperands, /*InsnID*/0, /*NumInsns*/1, /*MergeInsnID's*/0,
      GIR_ConstrainSelectedInstOperands, /*InsnID*/0,
      GIR_EraseFromParent, /*InsnID*/0,
      // GIR_Coverage, 2975,
      GIR_Done,
    // Label 1142: @75343
    GIM_Try, /*On fail goto*//*Label 1143*/ GIMT_Encode4(75423), // Rule ID 2987 //
      GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasFlatGlobalInsts),
      GIM_CheckMemorySizeLessThanLLT, /*MI*/0, /*MMO*/0, /*OpIdx*/0,
      GIM_CheckMemorySizeEqualTo, /*MI*/0, /*MMO*/0, /*Size*/GIMT_Encode4(2),
      GIM_CheckMemoryAddressSpace, /*MI*/0, /*MMO*/0, /*NumAddrSpace*/3, /*AddrSpace*/1, /*AddrSpace*/4, /*AddrSpace*/6,
      GIM_CheckAtomicOrdering, /*MI*/0, /*Order*/(uint8_t)AtomicOrdering::NotAtomic,
      GIM_CheckRegBankForClass, /*MI*/0, /*Op*/0, /*RC*/GIMT_Encode2(AMDGPU::AV_32RegClassID),
      GIM_CheckPointerToAny, /*MI*/0, /*Op*/1, /*SizeInBits*/0,
      GIM_CheckComplexPattern, /*MI*/0, /*Op*/1, /*Renderer*/GIMT_Encode2(0), GIMT_Encode2(GICP_gi_global_saddr),
      // (ld:{ *:[i32] } (GlobalSAddr:{ *:[iPTR] } SReg_64:{ *:[i64] }:$saddr, VGPR_32:{ *:[i32] }:$voffset, i32:{ *:[i32] }:$offset))<<P:Predicate_unindexedload>><<P:Predicate_extload>><<P:Predicate_extloadi16>><<P:Predicate_extloadi16_global>>  =>  (GLOBAL_LOAD_USHORT_SADDR:{ *:[i32] } ?:{ *:[i64] }:$saddr, ?:{ *:[i32] }:$voffset, ?:{ *:[i32] }:$offset, 0:{ *:[i32] })
      GIR_BuildMI, /*InsnID*/0, /*Opcode*/GIMT_Encode2(AMDGPU::GLOBAL_LOAD_USHORT_SADDR),
      GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/0, // DstI[vdst]
      GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/0, // saddr
      GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/1, // voffset
      GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/2, // offset
      GIR_AddImm8, /*InsnID*/0, /*Imm*/0,
      GIR_MergeMemOperands, /*InsnID*/0, /*NumInsns*/1, /*MergeInsnID's*/0,
      GIR_ConstrainSelectedInstOperands, /*InsnID*/0,
      GIR_EraseFromParent, /*InsnID*/0,
      // GIR_Coverage, 2987,
      GIR_Done,
    // Label 1143: @75423
    GIM_Try, /*On fail goto*//*Label 1144*/ GIMT_Encode4(75492), // Rule ID 2995 //
      GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasFlatGlobalInsts),
      GIM_CheckMemoryAddressSpace, /*MI*/0, /*MMO*/0, /*NumAddrSpace*/3, /*AddrSpace*/1, /*AddrSpace*/4, /*AddrSpace*/6,
      GIM_CheckAtomicOrdering, /*MI*/0, /*Order*/(uint8_t)AtomicOrdering::NotAtomic,
      GIM_CheckRegBankForClass, /*MI*/0, /*Op*/0, /*RC*/GIMT_Encode2(AMDGPU::AV_32RegClassID),
      GIM_CheckPointerToAny, /*MI*/0, /*Op*/1, /*SizeInBits*/0,
      GIM_CheckComplexPattern, /*MI*/0, /*Op*/1, /*Renderer*/GIMT_Encode2(0), GIMT_Encode2(GICP_gi_global_saddr),
      // (ld:{ *:[i32] } (GlobalSAddr:{ *:[iPTR] } SReg_64:{ *:[i64] }:$saddr, VGPR_32:{ *:[i32] }:$voffset, i32:{ *:[i32] }:$offset))<<P:Predicate_unindexedload>><<P:Predicate_load_global>>  =>  (GLOBAL_LOAD_DWORD_SADDR:{ *:[i32] } ?:{ *:[i64] }:$saddr, ?:{ *:[i32] }:$voffset, ?:{ *:[i32] }:$offset, 0:{ *:[i32] })
      GIR_BuildMI, /*InsnID*/0, /*Opcode*/GIMT_Encode2(AMDGPU::GLOBAL_LOAD_DWORD_SADDR),
      GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/0, // DstI[vdst]
      GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/0, // saddr
      GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/1, // voffset
      GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/2, // offset
      GIR_AddImm8, /*InsnID*/0, /*Imm*/0,
      GIR_MergeMemOperands, /*InsnID*/0, /*NumInsns*/1, /*MergeInsnID's*/0,
      GIR_ConstrainSelectedInstOperands, /*InsnID*/0,
      GIR_EraseFromParent, /*InsnID*/0,
      // GIR_Coverage, 2995,
      GIR_Done,
    // Label 1144: @75492
    GIM_Try, /*On fail goto*//*Label 1145*/ GIMT_Encode4(75561), // Rule ID 2997 //
      GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasFlatGlobalInsts),
      GIM_CheckMemoryAddressSpace, /*MI*/0, /*MMO*/0, /*NumAddrSpace*/3, /*AddrSpace*/1, /*AddrSpace*/4, /*AddrSpace*/6,
      GIM_CheckAtomicOrdering, /*MI*/0, /*Order*/(uint8_t)AtomicOrdering::NotAtomic,
      GIM_CheckRegBankForClass, /*MI*/0, /*Op*/0, /*RC*/GIMT_Encode2(AMDGPU::AV_32RegClassID),
      GIM_CheckPointerToAny, /*MI*/0, /*Op*/1, /*SizeInBits*/0,
      GIM_CheckComplexPattern, /*MI*/0, /*Op*/1, /*Renderer*/GIMT_Encode2(0), GIMT_Encode2(GICP_gi_global_saddr),
      // (ld:{ *:[f32] } (GlobalSAddr:{ *:[iPTR] } SReg_64:{ *:[i64] }:$saddr, VGPR_32:{ *:[i32] }:$voffset, i32:{ *:[i32] }:$offset))<<P:Predicate_unindexedload>><<P:Predicate_load_global>>  =>  (GLOBAL_LOAD_DWORD_SADDR:{ *:[f32] } ?:{ *:[i64] }:$saddr, ?:{ *:[i32] }:$voffset, ?:{ *:[i32] }:$offset, 0:{ *:[i32] })
      GIR_BuildMI, /*InsnID*/0, /*Opcode*/GIMT_Encode2(AMDGPU::GLOBAL_LOAD_DWORD_SADDR),
      GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/0, // DstI[vdst]
      GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/0, // saddr
      GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/1, // voffset
      GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/2, // offset
      GIR_AddImm8, /*InsnID*/0, /*Imm*/0,
      GIR_MergeMemOperands, /*InsnID*/0, /*NumInsns*/1, /*MergeInsnID's*/0,
      GIR_ConstrainSelectedInstOperands, /*InsnID*/0,
      GIR_EraseFromParent, /*InsnID*/0,
      // GIR_Coverage, 2997,
      GIR_Done,
    // Label 1145: @75561
    GIM_Try, /*On fail goto*//*Label 1146*/ GIMT_Encode4(75632), // Rule ID 2949 //
      GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasFlatGlobalInsts),
      GIM_CheckMemorySizeEqualTo, /*MI*/0, /*MMO*/0, /*Size*/GIMT_Encode4(1),
      GIM_CheckMemoryAddressSpace, /*MI*/0, /*MMO*/0, /*NumAddrSpace*/3, /*AddrSpace*/1, /*AddrSpace*/4, /*AddrSpace*/6,
      GIM_CheckAtomicOrderingOrStrongerThan, /*MI*/0, /*Order*/(uint8_t)AtomicOrdering::Unordered,
      GIM_CheckRegBankForClass, /*MI*/0, /*Op*/0, /*RC*/GIMT_Encode2(AMDGPU::AV_32RegClassID),
      GIM_CheckPointerToAny, /*MI*/0, /*Op*/1, /*SizeInBits*/0,
      GIM_CheckComplexPattern, /*MI*/0, /*Op*/1, /*Renderer*/GIMT_Encode2(0), GIMT_Encode2(GICP_gi_global_offset),
      // (atomic_load:{ *:[i32] } (GlobalOffset:{ *:[iPTR] } VReg_64:{ *:[i64] }:$vaddr, i32:{ *:[i32] }:$offset))<<P:Predicate_atomic_load_8>><<P:Predicate_atomic_load_8_global>>  =>  (GLOBAL_LOAD_UBYTE:{ *:[i32] } ?:{ *:[i64] }:$vaddr, ?:{ *:[i32] }:$offset)
      GIR_BuildMI, /*InsnID*/0, /*Opcode*/GIMT_Encode2(AMDGPU::GLOBAL_LOAD_UBYTE),
      GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/0, // DstI[vdst]
      GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/0, // vaddr
      GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/1, // offset
      GIR_AddImm8, /*InsnID*/0, /*Imm*/0,
      GIR_MergeMemOperands, /*InsnID*/0, /*NumInsns*/1, /*MergeInsnID's*/0,
      GIR_ConstrainSelectedInstOperands, /*InsnID*/0,
      GIR_EraseFromParent, /*InsnID*/0,
      // GIR_Coverage, 2949,
      GIR_Done,
    // Label 1146: @75632
    GIM_Try, /*On fail goto*//*Label 1147*/ GIMT_Encode4(75703), // Rule ID 2970 //
      GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasFlatGlobalInsts),
      GIM_CheckMemorySizeEqualTo, /*MI*/0, /*MMO*/0, /*Size*/GIMT_Encode4(2),
      GIM_CheckMemoryAddressSpace, /*MI*/0, /*MMO*/0, /*NumAddrSpace*/3, /*AddrSpace*/1, /*AddrSpace*/4, /*AddrSpace*/6,
      GIM_CheckAtomicOrderingOrStrongerThan, /*MI*/0, /*Order*/(uint8_t)AtomicOrdering::Unordered,
      GIM_CheckRegBankForClass, /*MI*/0, /*Op*/0, /*RC*/GIMT_Encode2(AMDGPU::AV_32RegClassID),
      GIM_CheckPointerToAny, /*MI*/0, /*Op*/1, /*SizeInBits*/0,
      GIM_CheckComplexPattern, /*MI*/0, /*Op*/1, /*Renderer*/GIMT_Encode2(0), GIMT_Encode2(GICP_gi_global_offset),
      // (atomic_load:{ *:[i32] } (GlobalOffset:{ *:[iPTR] } VReg_64:{ *:[i64] }:$vaddr, i32:{ *:[i32] }:$offset))<<P:Predicate_atomic_load_16>><<P:Predicate_atomic_load_16_global>>  =>  (GLOBAL_LOAD_USHORT:{ *:[i32] } ?:{ *:[i64] }:$vaddr, ?:{ *:[i32] }:$offset)
      GIR_BuildMI, /*InsnID*/0, /*Opcode*/GIMT_Encode2(AMDGPU::GLOBAL_LOAD_USHORT),
      GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/0, // DstI[vdst]
      GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/0, // vaddr
      GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/1, // offset
      GIR_AddImm8, /*InsnID*/0, /*Imm*/0,
      GIR_MergeMemOperands, /*InsnID*/0, /*NumInsns*/1, /*MergeInsnID's*/0,
      GIR_ConstrainSelectedInstOperands, /*InsnID*/0,
      GIR_EraseFromParent, /*InsnID*/0,
      // GIR_Coverage, 2970,
      GIR_Done,
    // Label 1147: @75703
    GIM_Try, /*On fail goto*//*Label 1148*/ GIMT_Encode4(75774), // Rule ID 3098 //
      GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasFlatGlobalInsts),
      GIM_CheckMemorySizeEqualTo, /*MI*/0, /*MMO*/0, /*Size*/GIMT_Encode4(4),
      GIM_CheckMemoryAddressSpace, /*MI*/0, /*MMO*/0, /*NumAddrSpace*/3, /*AddrSpace*/1, /*AddrSpace*/4, /*AddrSpace*/6,
      GIM_CheckAtomicOrderingOrStrongerThan, /*MI*/0, /*Order*/(uint8_t)AtomicOrdering::Unordered,
      GIM_CheckRegBankForClass, /*MI*/0, /*Op*/0, /*RC*/GIMT_Encode2(AMDGPU::AV_32RegClassID),
      GIM_CheckPointerToAny, /*MI*/0, /*Op*/1, /*SizeInBits*/0,
      GIM_CheckComplexPattern, /*MI*/0, /*Op*/1, /*Renderer*/GIMT_Encode2(0), GIMT_Encode2(GICP_gi_global_offset),
      // (atomic_load:{ *:[i32] } (GlobalOffset:{ *:[iPTR] } VReg_64:{ *:[i64] }:$vaddr, i32:{ *:[i32] }:$offset))<<P:Predicate_atomic_load_32>><<P:Predicate_atomic_load_32_global>>  =>  (GLOBAL_LOAD_DWORD:{ *:[i32] } ?:{ *:[i64] }:$vaddr, ?:{ *:[i32] }:$offset)
      GIR_BuildMI, /*InsnID*/0, /*Opcode*/GIMT_Encode2(AMDGPU::GLOBAL_LOAD_DWORD),
      GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/0, // DstI[vdst]
      GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/0, // vaddr
      GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/1, // offset
      GIR_AddImm8, /*InsnID*/0, /*Imm*/0,
      GIR_MergeMemOperands, /*InsnID*/0, /*NumInsns*/1, /*MergeInsnID's*/0,
      GIR_ConstrainSelectedInstOperands, /*InsnID*/0,
      GIR_EraseFromParent, /*InsnID*/0,
      // GIR_Coverage, 3098,
      GIR_Done,
    // Label 1148: @75774
    GIM_Try, /*On fail goto*//*Label 1149*/ GIMT_Encode4(75849), // Rule ID 2974 //
      GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasFlatGlobalInsts),
      GIM_CheckMemorySizeLessThanLLT, /*MI*/0, /*MMO*/0, /*OpIdx*/0,
      GIM_CheckMemorySizeEqualTo, /*MI*/0, /*MMO*/0, /*Size*/GIMT_Encode4(1),
      GIM_CheckMemoryAddressSpace, /*MI*/0, /*MMO*/0, /*NumAddrSpace*/3, /*AddrSpace*/1, /*AddrSpace*/4, /*AddrSpace*/6,
      GIM_CheckAtomicOrdering, /*MI*/0, /*Order*/(uint8_t)AtomicOrdering::NotAtomic,
      GIM_CheckRegBankForClass, /*MI*/0, /*Op*/0, /*RC*/GIMT_Encode2(AMDGPU::AV_32RegClassID),
      GIM_CheckPointerToAny, /*MI*/0, /*Op*/1, /*SizeInBits*/0,
      GIM_CheckComplexPattern, /*MI*/0, /*Op*/1, /*Renderer*/GIMT_Encode2(0), GIMT_Encode2(GICP_gi_global_offset),
      // (ld:{ *:[i32] } (GlobalOffset:{ *:[iPTR] } VReg_64:{ *:[i64] }:$vaddr, i32:{ *:[i32] }:$offset))<<P:Predicate_unindexedload>><<P:Predicate_extload>><<P:Predicate_extloadi8>><<P:Predicate_extloadi8_global>>  =>  (GLOBAL_LOAD_UBYTE:{ *:[i32] } ?:{ *:[i64] }:$vaddr, ?:{ *:[i32] }:$offset)
      GIR_BuildMI, /*InsnID*/0, /*Opcode*/GIMT_Encode2(AMDGPU::GLOBAL_LOAD_UBYTE),
      GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/0, // DstI[vdst]
      GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/0, // vaddr
      GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/1, // offset
      GIR_AddImm8, /*InsnID*/0, /*Imm*/0,
      GIR_MergeMemOperands, /*InsnID*/0, /*NumInsns*/1, /*MergeInsnID's*/0,
      GIR_ConstrainSelectedInstOperands, /*InsnID*/0,
      GIR_EraseFromParent, /*InsnID*/0,
      // GIR_Coverage, 2974,
      GIR_Done,
    // Label 1149: @75849
    GIM_Try, /*On fail goto*//*Label 1150*/ GIMT_Encode4(75924), // Rule ID 2986 //
      GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasFlatGlobalInsts),
      GIM_CheckMemorySizeLessThanLLT, /*MI*/0, /*MMO*/0, /*OpIdx*/0,
      GIM_CheckMemorySizeEqualTo, /*MI*/0, /*MMO*/0, /*Size*/GIMT_Encode4(2),
      GIM_CheckMemoryAddressSpace, /*MI*/0, /*MMO*/0, /*NumAddrSpace*/3, /*AddrSpace*/1, /*AddrSpace*/4, /*AddrSpace*/6,
      GIM_CheckAtomicOrdering, /*MI*/0, /*Order*/(uint8_t)AtomicOrdering::NotAtomic,
      GIM_CheckRegBankForClass, /*MI*/0, /*Op*/0, /*RC*/GIMT_Encode2(AMDGPU::AV_32RegClassID),
      GIM_CheckPointerToAny, /*MI*/0, /*Op*/1, /*SizeInBits*/0,
      GIM_CheckComplexPattern, /*MI*/0, /*Op*/1, /*Renderer*/GIMT_Encode2(0), GIMT_Encode2(GICP_gi_global_offset),
      // (ld:{ *:[i32] } (GlobalOffset:{ *:[iPTR] } VReg_64:{ *:[i64] }:$vaddr, i32:{ *:[i32] }:$offset))<<P:Predicate_unindexedload>><<P:Predicate_extload>><<P:Predicate_extloadi16>><<P:Predicate_extloadi16_global>>  =>  (GLOBAL_LOAD_USHORT:{ *:[i32] } ?:{ *:[i64] }:$vaddr, ?:{ *:[i32] }:$offset)
      GIR_BuildMI, /*InsnID*/0, /*Opcode*/GIMT_Encode2(AMDGPU::GLOBAL_LOAD_USHORT),
      GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/0, // DstI[vdst]
      GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/0, // vaddr
      GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/1, // offset
      GIR_AddImm8, /*InsnID*/0, /*Imm*/0,
      GIR_MergeMemOperands, /*InsnID*/0, /*NumInsns*/1, /*MergeInsnID's*/0,
      GIR_ConstrainSelectedInstOperands, /*InsnID*/0,
      GIR_EraseFromParent, /*InsnID*/0,
      // GIR_Coverage, 2986,
      GIR_Done,
    // Label 1150: @75924
    GIM_Try, /*On fail goto*//*Label 1151*/ GIMT_Encode4(75988), // Rule ID 2994 //
      GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasFlatGlobalInsts),
      GIM_CheckMemoryAddressSpace, /*MI*/0, /*MMO*/0, /*NumAddrSpace*/3, /*AddrSpace*/1, /*AddrSpace*/4, /*AddrSpace*/6,
      GIM_CheckAtomicOrdering, /*MI*/0, /*Order*/(uint8_t)AtomicOrdering::NotAtomic,
      GIM_CheckRegBankForClass, /*MI*/0, /*Op*/0, /*RC*/GIMT_Encode2(AMDGPU::AV_32RegClassID),
      GIM_CheckPointerToAny, /*MI*/0, /*Op*/1, /*SizeInBits*/0,
      GIM_CheckComplexPattern, /*MI*/0, /*Op*/1, /*Renderer*/GIMT_Encode2(0), GIMT_Encode2(GICP_gi_global_offset),
      // (ld:{ *:[i32] } (GlobalOffset:{ *:[iPTR] } VReg_64:{ *:[i64] }:$vaddr, i32:{ *:[i32] }:$offset))<<P:Predicate_unindexedload>><<P:Predicate_load_global>>  =>  (GLOBAL_LOAD_DWORD:{ *:[i32] } ?:{ *:[i64] }:$vaddr, ?:{ *:[i32] }:$offset)
      GIR_BuildMI, /*InsnID*/0, /*Opcode*/GIMT_Encode2(AMDGPU::GLOBAL_LOAD_DWORD),
      GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/0, // DstI[vdst]
      GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/0, // vaddr
      GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/1, // offset
      GIR_AddImm8, /*InsnID*/0, /*Imm*/0,
      GIR_MergeMemOperands, /*InsnID*/0, /*NumInsns*/1, /*MergeInsnID's*/0,
      GIR_ConstrainSelectedInstOperands, /*InsnID*/0,
      GIR_EraseFromParent, /*InsnID*/0,
      // GIR_Coverage, 2994,
      GIR_Done,
    // Label 1151: @75988
    GIM_Try, /*On fail goto*//*Label 1152*/ GIMT_Encode4(76052), // Rule ID 2996 //
      GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasFlatGlobalInsts),
      GIM_CheckMemoryAddressSpace, /*MI*/0, /*MMO*/0, /*NumAddrSpace*/3, /*AddrSpace*/1, /*AddrSpace*/4, /*AddrSpace*/6,
      GIM_CheckAtomicOrdering, /*MI*/0, /*Order*/(uint8_t)AtomicOrdering::NotAtomic,
      GIM_CheckRegBankForClass, /*MI*/0, /*Op*/0, /*RC*/GIMT_Encode2(AMDGPU::AV_32RegClassID),
      GIM_CheckPointerToAny, /*MI*/0, /*Op*/1, /*SizeInBits*/0,
      GIM_CheckComplexPattern, /*MI*/0, /*Op*/1, /*Renderer*/GIMT_Encode2(0), GIMT_Encode2(GICP_gi_global_offset),
      // (ld:{ *:[f32] } (GlobalOffset:{ *:[iPTR] } VReg_64:{ *:[i64] }:$vaddr, i32:{ *:[i32] }:$offset))<<P:Predicate_unindexedload>><<P:Predicate_load_global>>  =>  (GLOBAL_LOAD_DWORD:{ *:[f32] } ?:{ *:[i64] }:$vaddr, ?:{ *:[i32] }:$offset)
      GIR_BuildMI, /*InsnID*/0, /*Opcode*/GIMT_Encode2(AMDGPU::GLOBAL_LOAD_DWORD),
      GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/0, // DstI[vdst]
      GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/0, // vaddr
      GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/1, // offset
      GIR_AddImm8, /*InsnID*/0, /*Imm*/0,
      GIR_MergeMemOperands, /*InsnID*/0, /*NumInsns*/1, /*MergeInsnID's*/0,
      GIR_ConstrainSelectedInstOperands, /*InsnID*/0,
      GIR_EraseFromParent, /*InsnID*/0,
      // GIR_Coverage, 2996,
      GIR_Done,
    // Label 1152: @76052
    GIM_Try, /*On fail goto*//*Label 1153*/ GIMT_Encode4(76124), // Rule ID 2751 //
      GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasFlatAddressSpace),
      GIM_CheckMemorySizeEqualTo, /*MI*/0, /*MMO*/0, /*Size*/GIMT_Encode4(1),
      GIM_CheckMemoryAddressSpace, /*MI*/0, /*MMO*/0, /*NumAddrSpace*/4, /*AddrSpace*/0, /*AddrSpace*/1, /*AddrSpace*/4, /*AddrSpace*/6,
      GIM_CheckAtomicOrderingOrStrongerThan, /*MI*/0, /*Order*/(uint8_t)AtomicOrdering::Unordered,
      GIM_CheckRegBankForClass, /*MI*/0, /*Op*/0, /*RC*/GIMT_Encode2(AMDGPU::AV_32RegClassID),
      GIM_CheckPointerToAny, /*MI*/0, /*Op*/1, /*SizeInBits*/0,
      GIM_CheckComplexPattern, /*MI*/0, /*Op*/1, /*Renderer*/GIMT_Encode2(0), GIMT_Encode2(GICP_gi_flat_offset),
      // (atomic_load:{ *:[i32] } (FlatOffset:{ *:[iPTR] } i64:{ *:[i64] }:$vaddr, i32:{ *:[i32] }:$offset))<<P:Predicate_atomic_load_8>><<P:Predicate_atomic_load_8_flat>>  =>  (FLAT_LOAD_UBYTE:{ *:[i32] } ?:{ *:[i64] }:$vaddr, ?:{ *:[i32] }:$offset)
      GIR_BuildMI, /*InsnID*/0, /*Opcode*/GIMT_Encode2(AMDGPU::FLAT_LOAD_UBYTE),
      GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/0, // DstI[vdst]
      GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/0, // vaddr
      GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/1, // offset
      GIR_AddImm8, /*InsnID*/0, /*Imm*/0,
      GIR_MergeMemOperands, /*InsnID*/0, /*NumInsns*/1, /*MergeInsnID's*/0,
      GIR_ConstrainSelectedInstOperands, /*InsnID*/0,
      GIR_EraseFromParent, /*InsnID*/0,
      // GIR_Coverage, 2751,
      GIR_Done,
    // Label 1153: @76124
    GIM_Try, /*On fail goto*//*Label 1154*/ GIMT_Encode4(76196), // Rule ID 2753 //
      GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasFlatAddressSpace),
      GIM_CheckMemorySizeEqualTo, /*MI*/0, /*MMO*/0, /*Size*/GIMT_Encode4(2),
      GIM_CheckMemoryAddressSpace, /*MI*/0, /*MMO*/0, /*NumAddrSpace*/4, /*AddrSpace*/0, /*AddrSpace*/1, /*AddrSpace*/4, /*AddrSpace*/6,
      GIM_CheckAtomicOrderingOrStrongerThan, /*MI*/0, /*Order*/(uint8_t)AtomicOrdering::Unordered,
      GIM_CheckRegBankForClass, /*MI*/0, /*Op*/0, /*RC*/GIMT_Encode2(AMDGPU::AV_32RegClassID),
      GIM_CheckPointerToAny, /*MI*/0, /*Op*/1, /*SizeInBits*/0,
      GIM_CheckComplexPattern, /*MI*/0, /*Op*/1, /*Renderer*/GIMT_Encode2(0), GIMT_Encode2(GICP_gi_flat_offset),
      // (atomic_load:{ *:[i32] } (FlatOffset:{ *:[iPTR] } i64:{ *:[i64] }:$vaddr, i32:{ *:[i32] }:$offset))<<P:Predicate_atomic_load_16>><<P:Predicate_atomic_load_16_flat>>  =>  (FLAT_LOAD_USHORT:{ *:[i32] } ?:{ *:[i64] }:$vaddr, ?:{ *:[i32] }:$offset)
      GIR_BuildMI, /*InsnID*/0, /*Opcode*/GIMT_Encode2(AMDGPU::FLAT_LOAD_USHORT),
      GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/0, // DstI[vdst]
      GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/0, // vaddr
      GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/1, // offset
      GIR_AddImm8, /*InsnID*/0, /*Imm*/0,
      GIR_MergeMemOperands, /*InsnID*/0, /*NumInsns*/1, /*MergeInsnID's*/0,
      GIR_ConstrainSelectedInstOperands, /*InsnID*/0,
      GIR_EraseFromParent, /*InsnID*/0,
      // GIR_Coverage, 2753,
      GIR_Done,
    // Label 1154: @76196
    GIM_Try, /*On fail goto*//*Label 1155*/ GIMT_Encode4(76268), // Rule ID 2766 //
      GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasFlatAddressSpace),
      GIM_CheckMemorySizeEqualTo, /*MI*/0, /*MMO*/0, /*Size*/GIMT_Encode4(4),
      GIM_CheckMemoryAddressSpace, /*MI*/0, /*MMO*/0, /*NumAddrSpace*/4, /*AddrSpace*/0, /*AddrSpace*/1, /*AddrSpace*/4, /*AddrSpace*/6,
      GIM_CheckAtomicOrderingOrStrongerThan, /*MI*/0, /*Order*/(uint8_t)AtomicOrdering::Unordered,
      GIM_CheckRegBankForClass, /*MI*/0, /*Op*/0, /*RC*/GIMT_Encode2(AMDGPU::AV_32RegClassID),
      GIM_CheckPointerToAny, /*MI*/0, /*Op*/1, /*SizeInBits*/0,
      GIM_CheckComplexPattern, /*MI*/0, /*Op*/1, /*Renderer*/GIMT_Encode2(0), GIMT_Encode2(GICP_gi_flat_offset),
      // (atomic_load:{ *:[i32] } (FlatOffset:{ *:[iPTR] } i64:{ *:[i64] }:$vaddr, i32:{ *:[i32] }:$offset))<<P:Predicate_atomic_load_32>><<P:Predicate_atomic_load_32_flat>>  =>  (FLAT_LOAD_DWORD:{ *:[i32] } ?:{ *:[i64] }:$vaddr, ?:{ *:[i32] }:$offset)
      GIR_BuildMI, /*InsnID*/0, /*Opcode*/GIMT_Encode2(AMDGPU::FLAT_LOAD_DWORD),
      GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/0, // DstI[vdst]
      GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/0, // vaddr
      GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/1, // offset
      GIR_AddImm8, /*InsnID*/0, /*Imm*/0,
      GIR_MergeMemOperands, /*InsnID*/0, /*NumInsns*/1, /*MergeInsnID's*/0,
      GIR_ConstrainSelectedInstOperands, /*InsnID*/0,
      GIR_EraseFromParent, /*InsnID*/0,
      // GIR_Coverage, 2766,
      GIR_Done,
    // Label 1155: @76268
    GIM_Try, /*On fail goto*//*Label 1156*/ GIMT_Encode4(76344), // Rule ID 2755 //
      GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasFlatAddressSpace),
      GIM_CheckMemorySizeLessThanLLT, /*MI*/0, /*MMO*/0, /*OpIdx*/0,
      GIM_CheckMemorySizeEqualTo, /*MI*/0, /*MMO*/0, /*Size*/GIMT_Encode4(1),
      GIM_CheckMemoryAddressSpace, /*MI*/0, /*MMO*/0, /*NumAddrSpace*/4, /*AddrSpace*/0, /*AddrSpace*/1, /*AddrSpace*/4, /*AddrSpace*/6,
      GIM_CheckAtomicOrdering, /*MI*/0, /*Order*/(uint8_t)AtomicOrdering::NotAtomic,
      GIM_CheckRegBankForClass, /*MI*/0, /*Op*/0, /*RC*/GIMT_Encode2(AMDGPU::AV_32RegClassID),
      GIM_CheckPointerToAny, /*MI*/0, /*Op*/1, /*SizeInBits*/0,
      GIM_CheckComplexPattern, /*MI*/0, /*Op*/1, /*Renderer*/GIMT_Encode2(0), GIMT_Encode2(GICP_gi_flat_offset),
      // (ld:{ *:[i32] } (FlatOffset:{ *:[iPTR] } i64:{ *:[i64] }:$vaddr, i32:{ *:[i32] }:$offset))<<P:Predicate_unindexedload>><<P:Predicate_extload>><<P:Predicate_extloadi8>><<P:Predicate_extloadi8_flat>>  =>  (FLAT_LOAD_UBYTE:{ *:[i32] } ?:{ *:[i64] }:$vaddr, ?:{ *:[i32] }:$offset)
      GIR_BuildMI, /*InsnID*/0, /*Opcode*/GIMT_Encode2(AMDGPU::FLAT_LOAD_UBYTE),
      GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/0, // DstI[vdst]
      GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/0, // vaddr
      GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/1, // offset
      GIR_AddImm8, /*InsnID*/0, /*Imm*/0,
      GIR_MergeMemOperands, /*InsnID*/0, /*NumInsns*/1, /*MergeInsnID's*/0,
      GIR_ConstrainSelectedInstOperands, /*InsnID*/0,
      GIR_EraseFromParent, /*InsnID*/0,
      // GIR_Coverage, 2755,
      GIR_Done,
    // Label 1156: @76344
    GIM_Try, /*On fail goto*//*Label 1157*/ GIMT_Encode4(76420), // Rule ID 2761 //
      GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasFlatAddressSpace),
      GIM_CheckMemorySizeLessThanLLT, /*MI*/0, /*MMO*/0, /*OpIdx*/0,
      GIM_CheckMemorySizeEqualTo, /*MI*/0, /*MMO*/0, /*Size*/GIMT_Encode4(2),
      GIM_CheckMemoryAddressSpace, /*MI*/0, /*MMO*/0, /*NumAddrSpace*/4, /*AddrSpace*/0, /*AddrSpace*/1, /*AddrSpace*/4, /*AddrSpace*/6,
      GIM_CheckAtomicOrdering, /*MI*/0, /*Order*/(uint8_t)AtomicOrdering::NotAtomic,
      GIM_CheckRegBankForClass, /*MI*/0, /*Op*/0, /*RC*/GIMT_Encode2(AMDGPU::AV_32RegClassID),
      GIM_CheckPointerToAny, /*MI*/0, /*Op*/1, /*SizeInBits*/0,
      GIM_CheckComplexPattern, /*MI*/0, /*Op*/1, /*Renderer*/GIMT_Encode2(0), GIMT_Encode2(GICP_gi_flat_offset),
      // (ld:{ *:[i32] } (FlatOffset:{ *:[iPTR] } i64:{ *:[i64] }:$vaddr, i32:{ *:[i32] }:$offset))<<P:Predicate_unindexedload>><<P:Predicate_extload>><<P:Predicate_extloadi16>><<P:Predicate_extloadi16_flat>>  =>  (FLAT_LOAD_USHORT:{ *:[i32] } ?:{ *:[i64] }:$vaddr, ?:{ *:[i32] }:$offset)
      GIR_BuildMI, /*InsnID*/0, /*Opcode*/GIMT_Encode2(AMDGPU::FLAT_LOAD_USHORT),
      GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/0, // DstI[vdst]
      GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/0, // vaddr
      GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/1, // offset
      GIR_AddImm8, /*InsnID*/0, /*Imm*/0,
      GIR_MergeMemOperands, /*InsnID*/0, /*NumInsns*/1, /*MergeInsnID's*/0,
      GIR_ConstrainSelectedInstOperands, /*InsnID*/0,
      GIR_EraseFromParent, /*InsnID*/0,
      // GIR_Coverage, 2761,
      GIR_Done,
    // Label 1157: @76420
    GIM_Try, /*On fail goto*//*Label 1158*/ GIMT_Encode4(76485), // Rule ID 2770 //
      GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasFlatAddressSpace),
      GIM_CheckMemoryAddressSpace, /*MI*/0, /*MMO*/0, /*NumAddrSpace*/4, /*AddrSpace*/0, /*AddrSpace*/1, /*AddrSpace*/4, /*AddrSpace*/6,
      GIM_CheckAtomicOrdering, /*MI*/0, /*Order*/(uint8_t)AtomicOrdering::NotAtomic,
      GIM_CheckRegBankForClass, /*MI*/0, /*Op*/0, /*RC*/GIMT_Encode2(AMDGPU::AV_32RegClassID),
      GIM_CheckPointerToAny, /*MI*/0, /*Op*/1, /*SizeInBits*/0,
      GIM_CheckComplexPattern, /*MI*/0, /*Op*/1, /*Renderer*/GIMT_Encode2(0), GIMT_Encode2(GICP_gi_flat_offset),
      // (ld:{ *:[i32] } (FlatOffset:{ *:[iPTR] } i64:{ *:[i64] }:$vaddr, i32:{ *:[i32] }:$offset))<<P:Predicate_unindexedload>><<P:Predicate_load_flat>>  =>  (FLAT_LOAD_DWORD:{ *:[i32] } ?:{ *:[i64] }:$vaddr, ?:{ *:[i32] }:$offset)
      GIR_BuildMI, /*InsnID*/0, /*Opcode*/GIMT_Encode2(AMDGPU::FLAT_LOAD_DWORD),
      GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/0, // DstI[vdst]
      GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/0, // vaddr
      GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/1, // offset
      GIR_AddImm8, /*InsnID*/0, /*Imm*/0,
      GIR_MergeMemOperands, /*InsnID*/0, /*NumInsns*/1, /*MergeInsnID's*/0,
      GIR_ConstrainSelectedInstOperands, /*InsnID*/0,
      GIR_EraseFromParent, /*InsnID*/0,
      // GIR_Coverage, 2770,
      GIR_Done,
    // Label 1158: @76485
    GIM_Try, /*On fail goto*//*Label 1159*/ GIMT_Encode4(76550), // Rule ID 2772 //
      GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasFlatAddressSpace),
      GIM_CheckMemoryAddressSpace, /*MI*/0, /*MMO*/0, /*NumAddrSpace*/4, /*AddrSpace*/0, /*AddrSpace*/1, /*AddrSpace*/4, /*AddrSpace*/6,
      GIM_CheckAtomicOrdering, /*MI*/0, /*Order*/(uint8_t)AtomicOrdering::NotAtomic,
      GIM_CheckRegBankForClass, /*MI*/0, /*Op*/0, /*RC*/GIMT_Encode2(AMDGPU::AV_32RegClassID),
      GIM_CheckPointerToAny, /*MI*/0, /*Op*/1, /*SizeInBits*/0,
      GIM_CheckComplexPattern, /*MI*/0, /*Op*/1, /*Renderer*/GIMT_Encode2(0), GIMT_Encode2(GICP_gi_flat_offset),
      // (ld:{ *:[f32] } (FlatOffset:{ *:[iPTR] } i64:{ *:[i64] }:$vaddr, i32:{ *:[i32] }:$offset))<<P:Predicate_unindexedload>><<P:Predicate_load_flat>>  =>  (FLAT_LOAD_DWORD:{ *:[f32] } ?:{ *:[i64] }:$vaddr, ?:{ *:[i32] }:$offset)
      GIR_BuildMI, /*InsnID*/0, /*Opcode*/GIMT_Encode2(AMDGPU::FLAT_LOAD_DWORD),
      GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/0, // DstI[vdst]
      GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/0, // vaddr
      GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/1, // offset
      GIR_AddImm8, /*InsnID*/0, /*Imm*/0,
      GIR_MergeMemOperands, /*InsnID*/0, /*NumInsns*/1, /*MergeInsnID's*/0,
      GIR_ConstrainSelectedInstOperands, /*InsnID*/0,
      GIR_EraseFromParent, /*InsnID*/0,
      // GIR_Coverage, 2772,
      GIR_Done,
    // Label 1159: @76550
    GIM_Reject,
    // Label 826: @76551
    GIM_Try, /*On fail goto*//*Label 1160*/ GIMT_Encode4(76621), // Rule ID 2510 //
      GIM_CheckFeatures, GIMT_Encode2(GIFBS_isGFX9Plus),
      GIM_CheckMemorySizeEqualToLLT, /*MI*/0, /*MMO*/0, /*OpIdx*/0,
      GIM_CheckAtomicOrdering, /*MI*/0, /*Order*/(uint8_t)AtomicOrdering::NotAtomic,
      GIM_CheckRegBankForClass, /*MI*/0, /*Op*/0, /*RC*/GIMT_Encode2(AMDGPU::SReg_64_XEXECRegClassID),
      GIM_CheckPointerToAny, /*MI*/0, /*Op*/1, /*SizeInBits*/0,
      GIM_CheckCxxInsnPredicate, /*MI*/0, /*FnId*/GIMT_Encode2(GICXXPred_MI_Predicate_smrd_load),
      GIM_CheckComplexPattern, /*MI*/0, /*Op*/1, /*Renderer*/GIMT_Encode2(0), GIMT_Encode2(GICP_gi_smrd_sgpr_imm),
      // (ld:{ *:[i64] } (SMRDSgprImm:{ *:[iPTR] } i64:{ *:[i64] }:$sbase, i32:{ *:[i32] }:$soffset, i32:{ *:[i32] }:$offset))<<P:Predicate_unindexedload>><<P:Predicate_load>><<P:Predicate_smrd_load>>  =>  (S_LOAD_DWORDX2_SGPR_IMM:{ *:[i64] } ?:{ *:[i64] }:$sbase, ?:{ *:[i32] }:$soffset, ?:{ *:[i32] }:$offset, 0:{ *:[i32] })
      GIR_BuildMI, /*InsnID*/0, /*Opcode*/GIMT_Encode2(AMDGPU::S_LOAD_DWORDX2_SGPR_IMM),
      GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/0, // DstI[sdst]
      GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/0, // sbase
      GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/1, // soffset
      GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/2, // offset
      GIR_AddImm8, /*InsnID*/0, /*Imm*/0,
      GIR_MergeMemOperands, /*InsnID*/0, /*NumInsns*/1, /*MergeInsnID's*/0,
      GIR_ConstrainSelectedInstOperands, /*InsnID*/0,
      GIR_EraseFromParent, /*InsnID*/0,
      // GIR_Coverage, 2510,
      GIR_Done,
    // Label 1160: @76621
    GIM_Try, /*On fail goto*//*Label 1161*/ GIMT_Encode4(76691), // Rule ID 2522 //
      GIM_CheckFeatures, GIMT_Encode2(GIFBS_isGFX9Plus),
      GIM_CheckMemorySizeEqualToLLT, /*MI*/0, /*MMO*/0, /*OpIdx*/0,
      GIM_CheckAtomicOrdering, /*MI*/0, /*Order*/(uint8_t)AtomicOrdering::NotAtomic,
      GIM_CheckRegBankForClass, /*MI*/0, /*Op*/0, /*RC*/GIMT_Encode2(AMDGPU::SReg_64_XEXECRegClassID),
      GIM_CheckPointerToAny, /*MI*/0, /*Op*/1, /*SizeInBits*/0,
      GIM_CheckCxxInsnPredicate, /*MI*/0, /*FnId*/GIMT_Encode2(GICXXPred_MI_Predicate_smrd_load),
      GIM_CheckComplexPattern, /*MI*/0, /*Op*/1, /*Renderer*/GIMT_Encode2(0), GIMT_Encode2(GICP_gi_smrd_sgpr_imm),
      // (ld:{ *:[f64] } (SMRDSgprImm:{ *:[iPTR] } i64:{ *:[i64] }:$sbase, i32:{ *:[i32] }:$soffset, i32:{ *:[i32] }:$offset))<<P:Predicate_unindexedload>><<P:Predicate_load>><<P:Predicate_smrd_load>>  =>  (S_LOAD_DWORDX2_SGPR_IMM:{ *:[f64] } ?:{ *:[i64] }:$sbase, ?:{ *:[i32] }:$soffset, ?:{ *:[i32] }:$offset, 0:{ *:[i32] })
      GIR_BuildMI, /*InsnID*/0, /*Opcode*/GIMT_Encode2(AMDGPU::S_LOAD_DWORDX2_SGPR_IMM),
      GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/0, // DstI[sdst]
      GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/0, // sbase
      GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/1, // soffset
      GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/2, // offset
      GIR_AddImm8, /*InsnID*/0, /*Imm*/0,
      GIR_MergeMemOperands, /*InsnID*/0, /*NumInsns*/1, /*MergeInsnID's*/0,
      GIR_ConstrainSelectedInstOperands, /*InsnID*/0,
      GIR_EraseFromParent, /*InsnID*/0,
      // GIR_Coverage, 2522,
      GIR_Done,
    // Label 1161: @76691
    GIM_Try, /*On fail goto*//*Label 1162*/ GIMT_Encode4(76766), // Rule ID 6815 //
      GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasUnalignedAccessMode_LDSRequiresM0Init),
      GIM_CheckMemorySizeEqualToLLT, /*MI*/0, /*MMO*/0, /*OpIdx*/0,
      GIM_CheckMemoryAddressSpace, /*MI*/0, /*MMO*/0, /*NumAddrSpace*/1, /*AddrSpace*/3,
      GIM_CheckMemoryAddressSpace, /*MI*/0, /*MMO*/0, /*NumAddrSpace*/1, /*AddrSpace*/3,
      GIM_CheckAtomicOrdering, /*MI*/0, /*Order*/(uint8_t)AtomicOrdering::NotAtomic,
      GIM_CheckRegBankForClass, /*MI*/0, /*Op*/0, /*RC*/GIMT_Encode2(AMDGPU::AV_64RegClassID),
      GIM_CheckPointerToAny, /*MI*/0, /*Op*/1, /*SizeInBits*/0,
      GIM_CheckCxxInsnPredicate, /*MI*/0, /*FnId*/GIMT_Encode2(GICXXPred_MI_Predicate_load_align_less_than_4_local_m0),
      GIM_CheckComplexPattern, /*MI*/0, /*Op*/1, /*Renderer*/GIMT_Encode2(0), GIMT_Encode2(GICP_gi_ds_1addr_1offset),
      // (AMDGPUld_glue:{ *:[i64] } (DS1Addr1Offset:{ *:[iPTR] } i32:{ *:[i32] }:$ptr, i32:{ *:[i32] }:$offset))<<P:Predicate_unindexedload_glue>><<P:Predicate_load_glue>><<P:Predicate_load_local_m0>><<P:Predicate_load_align_less_than_4_local_m0>>  =>  (DS_READ_B64:{ *:[i64] } ?:{ *:[i32] }:$ptr, offset:{ *:[i32] }:$offset, 0:{ *:[i1] })
      GIR_BuildMI, /*InsnID*/0, /*Opcode*/GIMT_Encode2(AMDGPU::DS_READ_B64),
      GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/0, // DstI[vdst]
      GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/0, // ptr
      GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/1, // offset
      GIR_AddImm8, /*InsnID*/0, /*Imm*/0,
      GIR_MergeMemOperands, /*InsnID*/0, /*NumInsns*/1, /*MergeInsnID's*/0,
      GIR_ConstrainSelectedInstOperands, /*InsnID*/0,
      GIR_EraseFromParent, /*InsnID*/0,
      // GIR_Coverage, 6815,
      GIR_Done,
    // Label 1162: @76766
    GIM_Try, /*On fail goto*//*Label 1163*/ GIMT_Encode4(76841), // Rule ID 6819 //
      GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasUnalignedAccessMode_LDSRequiresM0Init),
      GIM_CheckMemorySizeEqualToLLT, /*MI*/0, /*MMO*/0, /*OpIdx*/0,
      GIM_CheckMemoryAddressSpace, /*MI*/0, /*MMO*/0, /*NumAddrSpace*/1, /*AddrSpace*/3,
      GIM_CheckMemoryAddressSpace, /*MI*/0, /*MMO*/0, /*NumAddrSpace*/1, /*AddrSpace*/3,
      GIM_CheckAtomicOrdering, /*MI*/0, /*Order*/(uint8_t)AtomicOrdering::NotAtomic,
      GIM_CheckRegBankForClass, /*MI*/0, /*Op*/0, /*RC*/GIMT_Encode2(AMDGPU::AV_64RegClassID),
      GIM_CheckPointerToAny, /*MI*/0, /*Op*/1, /*SizeInBits*/0,
      GIM_CheckCxxInsnPredicate, /*MI*/0, /*FnId*/GIMT_Encode2(GICXXPred_MI_Predicate_load_align_less_than_4_local_m0),
      GIM_CheckComplexPattern, /*MI*/0, /*Op*/1, /*Renderer*/GIMT_Encode2(0), GIMT_Encode2(GICP_gi_ds_1addr_1offset),
      // (AMDGPUld_glue:{ *:[f64] } (DS1Addr1Offset:{ *:[iPTR] } i32:{ *:[i32] }:$ptr, i32:{ *:[i32] }:$offset))<<P:Predicate_unindexedload_glue>><<P:Predicate_load_glue>><<P:Predicate_load_local_m0>><<P:Predicate_load_align_less_than_4_local_m0>>  =>  (DS_READ_B64:{ *:[f64] } ?:{ *:[i32] }:$ptr, offset:{ *:[i32] }:$offset, 0:{ *:[i1] })
      GIR_BuildMI, /*InsnID*/0, /*Opcode*/GIMT_Encode2(AMDGPU::DS_READ_B64),
      GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/0, // DstI[vdst]
      GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/0, // ptr
      GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/1, // offset
      GIR_AddImm8, /*InsnID*/0, /*Imm*/0,
      GIR_MergeMemOperands, /*InsnID*/0, /*NumInsns*/1, /*MergeInsnID's*/0,
      GIR_ConstrainSelectedInstOperands, /*InsnID*/0,
      GIR_EraseFromParent, /*InsnID*/0,
      // GIR_Coverage, 6819,
      GIR_Done,
    // Label 1163: @76841
    GIM_Try, /*On fail goto*//*Label 1164*/ GIMT_Encode4(76911), // Rule ID 6739 //
      GIM_CheckFeatures, GIMT_Encode2(GIFBS_LDSRequiresM0Init),
      GIM_CheckMemorySizeEqualToLLT, /*MI*/0, /*MMO*/0, /*OpIdx*/0,
      GIM_CheckMemoryAddressSpace, /*MI*/0, /*MMO*/0, /*NumAddrSpace*/1, /*AddrSpace*/3,
      GIM_CheckMemoryAlignment, /*MI*/0, /*MMO*/0, /*MinAlign*/8,
      GIM_CheckAtomicOrdering, /*MI*/0, /*Order*/(uint8_t)AtomicOrdering::NotAtomic,
      GIM_CheckRegBankForClass, /*MI*/0, /*Op*/0, /*RC*/GIMT_Encode2(AMDGPU::AV_64RegClassID),
      GIM_CheckPointerToAny, /*MI*/0, /*Op*/1, /*SizeInBits*/0,
      GIM_CheckComplexPattern, /*MI*/0, /*Op*/1, /*Renderer*/GIMT_Encode2(0), GIMT_Encode2(GICP_gi_ds_1addr_1offset),
      // (AMDGPUld_glue:{ *:[i64] } (DS1Addr1Offset:{ *:[iPTR] } i32:{ *:[i32] }:$ptr, i32:{ *:[i32] }:$offset))<<P:Predicate_unindexedload_glue>><<P:Predicate_load_glue>><<P:Predicate_load_local_m0>><<P:Predicate_load_align8_local_m0>>  =>  (DS_READ_B64:{ *:[i64] } ?:{ *:[i32] }:$ptr, offset:{ *:[i32] }:$offset, 0:{ *:[i1] })
      GIR_BuildMI, /*InsnID*/0, /*Opcode*/GIMT_Encode2(AMDGPU::DS_READ_B64),
      GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/0, // DstI[vdst]
      GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/0, // ptr
      GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/1, // offset
      GIR_AddImm8, /*InsnID*/0, /*Imm*/0,
      GIR_MergeMemOperands, /*InsnID*/0, /*NumInsns*/1, /*MergeInsnID's*/0,
      GIR_ConstrainSelectedInstOperands, /*InsnID*/0,
      GIR_EraseFromParent, /*InsnID*/0,
      // GIR_Coverage, 6739,
      GIR_Done,
    // Label 1164: @76911
    GIM_Try, /*On fail goto*//*Label 1165*/ GIMT_Encode4(76981), // Rule ID 6743 //
      GIM_CheckFeatures, GIMT_Encode2(GIFBS_LDSRequiresM0Init),
      GIM_CheckMemorySizeEqualToLLT, /*MI*/0, /*MMO*/0, /*OpIdx*/0,
      GIM_CheckMemoryAddressSpace, /*MI*/0, /*MMO*/0, /*NumAddrSpace*/1, /*AddrSpace*/3,
      GIM_CheckMemoryAlignment, /*MI*/0, /*MMO*/0, /*MinAlign*/8,
      GIM_CheckAtomicOrdering, /*MI*/0, /*Order*/(uint8_t)AtomicOrdering::NotAtomic,
      GIM_CheckRegBankForClass, /*MI*/0, /*Op*/0, /*RC*/GIMT_Encode2(AMDGPU::AV_64RegClassID),
      GIM_CheckPointerToAny, /*MI*/0, /*Op*/1, /*SizeInBits*/0,
      GIM_CheckComplexPattern, /*MI*/0, /*Op*/1, /*Renderer*/GIMT_Encode2(0), GIMT_Encode2(GICP_gi_ds_1addr_1offset),
      // (AMDGPUld_glue:{ *:[f64] } (DS1Addr1Offset:{ *:[iPTR] } i32:{ *:[i32] }:$ptr, i32:{ *:[i32] }:$offset))<<P:Predicate_unindexedload_glue>><<P:Predicate_load_glue>><<P:Predicate_load_local_m0>><<P:Predicate_load_align8_local_m0>>  =>  (DS_READ_B64:{ *:[f64] } ?:{ *:[i32] }:$ptr, offset:{ *:[i32] }:$offset, 0:{ *:[i1] })
      GIR_BuildMI, /*InsnID*/0, /*Opcode*/GIMT_Encode2(AMDGPU::DS_READ_B64),
      GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/0, // DstI[vdst]
      GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/0, // ptr
      GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/1, // offset
      GIR_AddImm8, /*InsnID*/0, /*Imm*/0,
      GIR_MergeMemOperands, /*InsnID*/0, /*NumInsns*/1, /*MergeInsnID's*/0,
      GIR_ConstrainSelectedInstOperands, /*InsnID*/0,
      GIR_EraseFromParent, /*InsnID*/0,
      // GIR_Coverage, 6743,
      GIR_Done,
    // Label 1165: @76981
    GIM_Try, /*On fail goto*//*Label 1166*/ GIMT_Encode4(77043), // Rule ID 2506 //
      GIM_CheckMemorySizeEqualToLLT, /*MI*/0, /*MMO*/0, /*OpIdx*/0,
      GIM_CheckAtomicOrdering, /*MI*/0, /*Order*/(uint8_t)AtomicOrdering::NotAtomic,
      GIM_CheckRegBankForClass, /*MI*/0, /*Op*/0, /*RC*/GIMT_Encode2(AMDGPU::SReg_64_XEXECRegClassID),
      GIM_CheckPointerToAny, /*MI*/0, /*Op*/1, /*SizeInBits*/0,
      GIM_CheckCxxInsnPredicate, /*MI*/0, /*FnId*/GIMT_Encode2(GICXXPred_MI_Predicate_smrd_load),
      GIM_CheckComplexPattern, /*MI*/0, /*Op*/1, /*Renderer*/GIMT_Encode2(0), GIMT_Encode2(GICP_gi_smrd_imm),
      // (ld:{ *:[i64] } (SMRDImm:{ *:[iPTR] } i64:{ *:[i64] }:$sbase, i32:{ *:[i32] }:$offset))<<P:Predicate_unindexedload>><<P:Predicate_load>><<P:Predicate_smrd_load>>  =>  (S_LOAD_DWORDX2_IMM:{ *:[i64] } ?:{ *:[i64] }:$sbase, ?:{ *:[i32] }:$offset, 0:{ *:[i32] })
      GIR_BuildMI, /*InsnID*/0, /*Opcode*/GIMT_Encode2(AMDGPU::S_LOAD_DWORDX2_IMM),
      GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/0, // DstI[sdst]
      GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/0, // sbase
      GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/1, // offset
      GIR_AddImm8, /*InsnID*/0, /*Imm*/0,
      GIR_MergeMemOperands, /*InsnID*/0, /*NumInsns*/1, /*MergeInsnID's*/0,
      GIR_ConstrainSelectedInstOperands, /*InsnID*/0,
      GIR_EraseFromParent, /*InsnID*/0,
      // GIR_Coverage, 2506,
      GIR_Done,
    // Label 1166: @77043
    GIM_Try, /*On fail goto*//*Label 1167*/ GIMT_Encode4(77108), // Rule ID 2507 //
      GIM_CheckFeatures, GIMT_Encode2(GIFBS_isGFX7Only),
      GIM_CheckMemorySizeEqualToLLT, /*MI*/0, /*MMO*/0, /*OpIdx*/0,
      GIM_CheckAtomicOrdering, /*MI*/0, /*Order*/(uint8_t)AtomicOrdering::NotAtomic,
      GIM_CheckRegBankForClass, /*MI*/0, /*Op*/0, /*RC*/GIMT_Encode2(AMDGPU::SReg_64_XEXECRegClassID),
      GIM_CheckPointerToAny, /*MI*/0, /*Op*/1, /*SizeInBits*/0,
      GIM_CheckCxxInsnPredicate, /*MI*/0, /*FnId*/GIMT_Encode2(GICXXPred_MI_Predicate_smrd_load),
      GIM_CheckComplexPattern, /*MI*/0, /*Op*/1, /*Renderer*/GIMT_Encode2(0), GIMT_Encode2(GICP_gi_smrd_imm32),
      // (ld:{ *:[i64] } (SMRDImm32:{ *:[iPTR] } i64:{ *:[i64] }:$sbase, i32:{ *:[i32] }:$offset))<<P:Predicate_unindexedload>><<P:Predicate_load>><<P:Predicate_smrd_load>>  =>  (S_LOAD_DWORDX2_IMM_ci:{ *:[i64] } ?:{ *:[i64] }:$sbase, ?:{ *:[i32] }:$offset, 0:{ *:[i32] })
      GIR_BuildMI, /*InsnID*/0, /*Opcode*/GIMT_Encode2(AMDGPU::S_LOAD_DWORDX2_IMM_ci),
      GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/0, // DstI[sdst]
      GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/0, // sbase
      GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/1, // offset
      GIR_AddImm8, /*InsnID*/0, /*Imm*/0,
      GIR_MergeMemOperands, /*InsnID*/0, /*NumInsns*/1, /*MergeInsnID's*/0,
      GIR_ConstrainSelectedInstOperands, /*InsnID*/0,
      GIR_EraseFromParent, /*InsnID*/0,
      // GIR_Coverage, 2507,
      GIR_Done,
    // Label 1167: @77108
    GIM_Try, /*On fail goto*//*Label 1168*/ GIMT_Encode4(77173), // Rule ID 2508 //
      GIM_CheckFeatures, GIMT_Encode2(GIFBS_isNotGFX9Plus),
      GIM_CheckMemorySizeEqualToLLT, /*MI*/0, /*MMO*/0, /*OpIdx*/0,
      GIM_CheckAtomicOrdering, /*MI*/0, /*Order*/(uint8_t)AtomicOrdering::NotAtomic,
      GIM_CheckRegBankForClass, /*MI*/0, /*Op*/0, /*RC*/GIMT_Encode2(AMDGPU::SReg_64_XEXECRegClassID),
      GIM_CheckPointerToAny, /*MI*/0, /*Op*/1, /*SizeInBits*/0,
      GIM_CheckCxxInsnPredicate, /*MI*/0, /*FnId*/GIMT_Encode2(GICXXPred_MI_Predicate_smrd_load),
      GIM_CheckComplexPattern, /*MI*/0, /*Op*/1, /*Renderer*/GIMT_Encode2(0), GIMT_Encode2(GICP_gi_smrd_sgpr),
      // (ld:{ *:[i64] } (SMRDSgpr:{ *:[iPTR] } i64:{ *:[i64] }:$sbase, i32:{ *:[i32] }:$soffset))<<P:Predicate_unindexedload>><<P:Predicate_load>><<P:Predicate_smrd_load>>  =>  (S_LOAD_DWORDX2_SGPR:{ *:[i64] } ?:{ *:[i64] }:$sbase, ?:{ *:[i32] }:$soffset, 0:{ *:[i32] })
      GIR_BuildMI, /*InsnID*/0, /*Opcode*/GIMT_Encode2(AMDGPU::S_LOAD_DWORDX2_SGPR),
      GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/0, // DstI[sdst]
      GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/0, // sbase
      GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/1, // soffset
      GIR_AddImm8, /*InsnID*/0, /*Imm*/0,
      GIR_MergeMemOperands, /*InsnID*/0, /*NumInsns*/1, /*MergeInsnID's*/0,
      GIR_ConstrainSelectedInstOperands, /*InsnID*/0,
      GIR_EraseFromParent, /*InsnID*/0,
      // GIR_Coverage, 2508,
      GIR_Done,
    // Label 1168: @77173
    GIM_Try, /*On fail goto*//*Label 1169*/ GIMT_Encode4(77241), // Rule ID 2509 //
      GIM_CheckFeatures, GIMT_Encode2(GIFBS_isGFX9Plus),
      GIM_CheckMemorySizeEqualToLLT, /*MI*/0, /*MMO*/0, /*OpIdx*/0,
      GIM_CheckAtomicOrdering, /*MI*/0, /*Order*/(uint8_t)AtomicOrdering::NotAtomic,
      GIM_CheckRegBankForClass, /*MI*/0, /*Op*/0, /*RC*/GIMT_Encode2(AMDGPU::SReg_64_XEXECRegClassID),
      GIM_CheckPointerToAny, /*MI*/0, /*Op*/1, /*SizeInBits*/0,
      GIM_CheckCxxInsnPredicate, /*MI*/0, /*FnId*/GIMT_Encode2(GICXXPred_MI_Predicate_smrd_load),
      GIM_CheckComplexPattern, /*MI*/0, /*Op*/1, /*Renderer*/GIMT_Encode2(0), GIMT_Encode2(GICP_gi_smrd_sgpr),
      // (ld:{ *:[i64] } (SMRDSgpr:{ *:[iPTR] } i64:{ *:[i64] }:$sbase, i32:{ *:[i32] }:$soffset))<<P:Predicate_unindexedload>><<P:Predicate_load>><<P:Predicate_smrd_load>>  =>  (S_LOAD_DWORDX2_SGPR_IMM:{ *:[i64] } ?:{ *:[i64] }:$sbase, ?:{ *:[i32] }:$soffset, 0:{ *:[i32] }, 0:{ *:[i32] })
      GIR_BuildMI, /*InsnID*/0, /*Opcode*/GIMT_Encode2(AMDGPU::S_LOAD_DWORDX2_SGPR_IMM),
      GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/0, // DstI[sdst]
      GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/0, // sbase
      GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/1, // soffset
      GIR_AddImm8, /*InsnID*/0, /*Imm*/0,
      GIR_AddImm8, /*InsnID*/0, /*Imm*/0,
      GIR_MergeMemOperands, /*InsnID*/0, /*NumInsns*/1, /*MergeInsnID's*/0,
      GIR_ConstrainSelectedInstOperands, /*InsnID*/0,
      GIR_EraseFromParent, /*InsnID*/0,
      // GIR_Coverage, 2509,
      GIR_Done,
    // Label 1169: @77241
    GIM_Try, /*On fail goto*//*Label 1170*/ GIMT_Encode4(77303), // Rule ID 2518 //
      GIM_CheckMemorySizeEqualToLLT, /*MI*/0, /*MMO*/0, /*OpIdx*/0,
      GIM_CheckAtomicOrdering, /*MI*/0, /*Order*/(uint8_t)AtomicOrdering::NotAtomic,
      GIM_CheckRegBankForClass, /*MI*/0, /*Op*/0, /*RC*/GIMT_Encode2(AMDGPU::SReg_64_XEXECRegClassID),
      GIM_CheckPointerToAny, /*MI*/0, /*Op*/1, /*SizeInBits*/0,
      GIM_CheckCxxInsnPredicate, /*MI*/0, /*FnId*/GIMT_Encode2(GICXXPred_MI_Predicate_smrd_load),
      GIM_CheckComplexPattern, /*MI*/0, /*Op*/1, /*Renderer*/GIMT_Encode2(0), GIMT_Encode2(GICP_gi_smrd_imm),
      // (ld:{ *:[f64] } (SMRDImm:{ *:[iPTR] } i64:{ *:[i64] }:$sbase, i32:{ *:[i32] }:$offset))<<P:Predicate_unindexedload>><<P:Predicate_load>><<P:Predicate_smrd_load>>  =>  (S_LOAD_DWORDX2_IMM:{ *:[f64] } ?:{ *:[i64] }:$sbase, ?:{ *:[i32] }:$offset, 0:{ *:[i32] })
      GIR_BuildMI, /*InsnID*/0, /*Opcode*/GIMT_Encode2(AMDGPU::S_LOAD_DWORDX2_IMM),
      GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/0, // DstI[sdst]
      GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/0, // sbase
      GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/1, // offset
      GIR_AddImm8, /*InsnID*/0, /*Imm*/0,
      GIR_MergeMemOperands, /*InsnID*/0, /*NumInsns*/1, /*MergeInsnID's*/0,
      GIR_ConstrainSelectedInstOperands, /*InsnID*/0,
      GIR_EraseFromParent, /*InsnID*/0,
      // GIR_Coverage, 2518,
      GIR_Done,
    // Label 1170: @77303
    GIM_Try, /*On fail goto*//*Label 1171*/ GIMT_Encode4(77368), // Rule ID 2519 //
      GIM_CheckFeatures, GIMT_Encode2(GIFBS_isGFX7Only),
      GIM_CheckMemorySizeEqualToLLT, /*MI*/0, /*MMO*/0, /*OpIdx*/0,
      GIM_CheckAtomicOrdering, /*MI*/0, /*Order*/(uint8_t)AtomicOrdering::NotAtomic,
      GIM_CheckRegBankForClass, /*MI*/0, /*Op*/0, /*RC*/GIMT_Encode2(AMDGPU::SReg_64_XEXECRegClassID),
      GIM_CheckPointerToAny, /*MI*/0, /*Op*/1, /*SizeInBits*/0,
      GIM_CheckCxxInsnPredicate, /*MI*/0, /*FnId*/GIMT_Encode2(GICXXPred_MI_Predicate_smrd_load),
      GIM_CheckComplexPattern, /*MI*/0, /*Op*/1, /*Renderer*/GIMT_Encode2(0), GIMT_Encode2(GICP_gi_smrd_imm32),
      // (ld:{ *:[f64] } (SMRDImm32:{ *:[iPTR] } i64:{ *:[i64] }:$sbase, i32:{ *:[i32] }:$offset))<<P:Predicate_unindexedload>><<P:Predicate_load>><<P:Predicate_smrd_load>>  =>  (S_LOAD_DWORDX2_IMM_ci:{ *:[f64] } ?:{ *:[i64] }:$sbase, ?:{ *:[i32] }:$offset, 0:{ *:[i32] })
      GIR_BuildMI, /*InsnID*/0, /*Opcode*/GIMT_Encode2(AMDGPU::S_LOAD_DWORDX2_IMM_ci),
      GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/0, // DstI[sdst]
      GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/0, // sbase
      GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/1, // offset
      GIR_AddImm8, /*InsnID*/0, /*Imm*/0,
      GIR_MergeMemOperands, /*InsnID*/0, /*NumInsns*/1, /*MergeInsnID's*/0,
      GIR_ConstrainSelectedInstOperands, /*InsnID*/0,
      GIR_EraseFromParent, /*InsnID*/0,
      // GIR_Coverage, 2519,
      GIR_Done,
    // Label 1171: @77368
    GIM_Try, /*On fail goto*//*Label 1172*/ GIMT_Encode4(77433), // Rule ID 2520 //
      GIM_CheckFeatures, GIMT_Encode2(GIFBS_isNotGFX9Plus),
      GIM_CheckMemorySizeEqualToLLT, /*MI*/0, /*MMO*/0, /*OpIdx*/0,
      GIM_CheckAtomicOrdering, /*MI*/0, /*Order*/(uint8_t)AtomicOrdering::NotAtomic,
      GIM_CheckRegBankForClass, /*MI*/0, /*Op*/0, /*RC*/GIMT_Encode2(AMDGPU::SReg_64_XEXECRegClassID),
      GIM_CheckPointerToAny, /*MI*/0, /*Op*/1, /*SizeInBits*/0,
      GIM_CheckCxxInsnPredicate, /*MI*/0, /*FnId*/GIMT_Encode2(GICXXPred_MI_Predicate_smrd_load),
      GIM_CheckComplexPattern, /*MI*/0, /*Op*/1, /*Renderer*/GIMT_Encode2(0), GIMT_Encode2(GICP_gi_smrd_sgpr),
      // (ld:{ *:[f64] } (SMRDSgpr:{ *:[iPTR] } i64:{ *:[i64] }:$sbase, i32:{ *:[i32] }:$soffset))<<P:Predicate_unindexedload>><<P:Predicate_load>><<P:Predicate_smrd_load>>  =>  (S_LOAD_DWORDX2_SGPR:{ *:[f64] } ?:{ *:[i64] }:$sbase, ?:{ *:[i32] }:$soffset, 0:{ *:[i32] })
      GIR_BuildMI, /*InsnID*/0, /*Opcode*/GIMT_Encode2(AMDGPU::S_LOAD_DWORDX2_SGPR),
      GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/0, // DstI[sdst]
      GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/0, // sbase
      GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/1, // soffset
      GIR_AddImm8, /*InsnID*/0, /*Imm*/0,
      GIR_MergeMemOperands, /*InsnID*/0, /*NumInsns*/1, /*MergeInsnID's*/0,
      GIR_ConstrainSelectedInstOperands, /*InsnID*/0,
      GIR_EraseFromParent, /*InsnID*/0,
      // GIR_Coverage, 2520,
      GIR_Done,
    // Label 1172: @77433
    GIM_Try, /*On fail goto*//*Label 1173*/ GIMT_Encode4(77501), // Rule ID 2521 //
      GIM_CheckFeatures, GIMT_Encode2(GIFBS_isGFX9Plus),
      GIM_CheckMemorySizeEqualToLLT, /*MI*/0, /*MMO*/0, /*OpIdx*/0,
      GIM_CheckAtomicOrdering, /*MI*/0, /*Order*/(uint8_t)AtomicOrdering::NotAtomic,
      GIM_CheckRegBankForClass, /*MI*/0, /*Op*/0, /*RC*/GIMT_Encode2(AMDGPU::SReg_64_XEXECRegClassID),
      GIM_CheckPointerToAny, /*MI*/0, /*Op*/1, /*SizeInBits*/0,
      GIM_CheckCxxInsnPredicate, /*MI*/0, /*FnId*/GIMT_Encode2(GICXXPred_MI_Predicate_smrd_load),
      GIM_CheckComplexPattern, /*MI*/0, /*Op*/1, /*Renderer*/GIMT_Encode2(0), GIMT_Encode2(GICP_gi_smrd_sgpr),
      // (ld:{ *:[f64] } (SMRDSgpr:{ *:[iPTR] } i64:{ *:[i64] }:$sbase, i32:{ *:[i32] }:$soffset))<<P:Predicate_unindexedload>><<P:Predicate_load>><<P:Predicate_smrd_load>>  =>  (S_LOAD_DWORDX2_SGPR_IMM:{ *:[f64] } ?:{ *:[i64] }:$sbase, ?:{ *:[i32] }:$soffset, 0:{ *:[i32] }, 0:{ *:[i32] })
      GIR_BuildMI, /*InsnID*/0, /*Opcode*/GIMT_Encode2(AMDGPU::S_LOAD_DWORDX2_SGPR_IMM),
      GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/0, // DstI[sdst]
      GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/0, // sbase
      GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/1, // soffset
      GIR_AddImm8, /*InsnID*/0, /*Imm*/0,
      GIR_AddImm8, /*InsnID*/0, /*Imm*/0,
      GIR_MergeMemOperands, /*InsnID*/0, /*NumInsns*/1, /*MergeInsnID's*/0,
      GIR_ConstrainSelectedInstOperands, /*InsnID*/0,
      GIR_EraseFromParent, /*InsnID*/0,
      // GIR_Coverage, 2521,
      GIR_Done,
    // Label 1173: @77501
    GIM_Try, /*On fail goto*//*Label 1174*/ GIMT_Encode4(77572), // Rule ID 6816 //
      GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasUnalignedAccessMode_NotLDSRequiresM0Init),
      GIM_CheckMemoryAddressSpace, /*MI*/0, /*MMO*/0, /*NumAddrSpace*/1, /*AddrSpace*/3,
      GIM_CheckMemoryAddressSpace, /*MI*/0, /*MMO*/0, /*NumAddrSpace*/1, /*AddrSpace*/3,
      GIM_CheckAtomicOrdering, /*MI*/0, /*Order*/(uint8_t)AtomicOrdering::NotAtomic,
      GIM_CheckRegBankForClass, /*MI*/0, /*Op*/0, /*RC*/GIMT_Encode2(AMDGPU::AV_64RegClassID),
      GIM_CheckPointerToAny, /*MI*/0, /*Op*/1, /*SizeInBits*/0,
      GIM_CheckCxxInsnPredicate, /*MI*/0, /*FnId*/GIMT_Encode2(GICXXPred_MI_Predicate_load_align_less_than_4_local),
      GIM_CheckComplexPattern, /*MI*/0, /*Op*/1, /*Renderer*/GIMT_Encode2(0), GIMT_Encode2(GICP_gi_ds_1addr_1offset),
      // (ld:{ *:[i64] } (DS1Addr1Offset:{ *:[iPTR] } i32:{ *:[i32] }:$ptr, i32:{ *:[i32] }:$offset))<<P:Predicate_unindexedload>><<P:Predicate_load_local>><<P:Predicate_load_align_less_than_4_local>>  =>  (DS_READ_B64_gfx9:{ *:[i64] } ?:{ *:[i32] }:$ptr, offset:{ *:[i32] }:$offset, 0:{ *:[i1] })
      GIR_BuildMI, /*InsnID*/0, /*Opcode*/GIMT_Encode2(AMDGPU::DS_READ_B64_gfx9),
      GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/0, // DstI[vdst]
      GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/0, // ptr
      GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/1, // offset
      GIR_AddImm8, /*InsnID*/0, /*Imm*/0,
      GIR_MergeMemOperands, /*InsnID*/0, /*NumInsns*/1, /*MergeInsnID's*/0,
      GIR_ConstrainSelectedInstOperands, /*InsnID*/0,
      GIR_EraseFromParent, /*InsnID*/0,
      // GIR_Coverage, 6816,
      GIR_Done,
    // Label 1174: @77572
    GIM_Try, /*On fail goto*//*Label 1175*/ GIMT_Encode4(77643), // Rule ID 6820 //
      GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasUnalignedAccessMode_NotLDSRequiresM0Init),
      GIM_CheckMemoryAddressSpace, /*MI*/0, /*MMO*/0, /*NumAddrSpace*/1, /*AddrSpace*/3,
      GIM_CheckMemoryAddressSpace, /*MI*/0, /*MMO*/0, /*NumAddrSpace*/1, /*AddrSpace*/3,
      GIM_CheckAtomicOrdering, /*MI*/0, /*Order*/(uint8_t)AtomicOrdering::NotAtomic,
      GIM_CheckRegBankForClass, /*MI*/0, /*Op*/0, /*RC*/GIMT_Encode2(AMDGPU::AV_64RegClassID),
      GIM_CheckPointerToAny, /*MI*/0, /*Op*/1, /*SizeInBits*/0,
      GIM_CheckCxxInsnPredicate, /*MI*/0, /*FnId*/GIMT_Encode2(GICXXPred_MI_Predicate_load_align_less_than_4_local),
      GIM_CheckComplexPattern, /*MI*/0, /*Op*/1, /*Renderer*/GIMT_Encode2(0), GIMT_Encode2(GICP_gi_ds_1addr_1offset),
      // (ld:{ *:[f64] } (DS1Addr1Offset:{ *:[iPTR] } i32:{ *:[i32] }:$ptr, i32:{ *:[i32] }:$offset))<<P:Predicate_unindexedload>><<P:Predicate_load_local>><<P:Predicate_load_align_less_than_4_local>>  =>  (DS_READ_B64_gfx9:{ *:[f64] } ?:{ *:[i32] }:$ptr, offset:{ *:[i32] }:$offset, 0:{ *:[i1] })
      GIR_BuildMI, /*InsnID*/0, /*Opcode*/GIMT_Encode2(AMDGPU::DS_READ_B64_gfx9),
      GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/0, // DstI[vdst]
      GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/0, // ptr
      GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/1, // offset
      GIR_AddImm8, /*InsnID*/0, /*Imm*/0,
      GIR_MergeMemOperands, /*InsnID*/0, /*NumInsns*/1, /*MergeInsnID's*/0,
      GIR_ConstrainSelectedInstOperands, /*InsnID*/0,
      GIR_EraseFromParent, /*InsnID*/0,
      // GIR_Coverage, 6820,
      GIR_Done,
    // Label 1175: @77643
    GIM_Try, /*On fail goto*//*Label 1176*/ GIMT_Encode4(77709), // Rule ID 6740 //
      GIM_CheckFeatures, GIMT_Encode2(GIFBS_NotLDSRequiresM0Init),
      GIM_CheckMemoryAddressSpace, /*MI*/0, /*MMO*/0, /*NumAddrSpace*/1, /*AddrSpace*/3,
      GIM_CheckMemoryAlignment, /*MI*/0, /*MMO*/0, /*MinAlign*/8,
      GIM_CheckAtomicOrdering, /*MI*/0, /*Order*/(uint8_t)AtomicOrdering::NotAtomic,
      GIM_CheckRegBankForClass, /*MI*/0, /*Op*/0, /*RC*/GIMT_Encode2(AMDGPU::AV_64RegClassID),
      GIM_CheckPointerToAny, /*MI*/0, /*Op*/1, /*SizeInBits*/0,
      GIM_CheckComplexPattern, /*MI*/0, /*Op*/1, /*Renderer*/GIMT_Encode2(0), GIMT_Encode2(GICP_gi_ds_1addr_1offset),
      // (ld:{ *:[i64] } (DS1Addr1Offset:{ *:[iPTR] } i32:{ *:[i32] }:$ptr, i32:{ *:[i32] }:$offset))<<P:Predicate_unindexedload>><<P:Predicate_load_local>><<P:Predicate_load_align8_local>>  =>  (DS_READ_B64_gfx9:{ *:[i64] } ?:{ *:[i32] }:$ptr, offset:{ *:[i32] }:$offset, 0:{ *:[i1] })
      GIR_BuildMI, /*InsnID*/0, /*Opcode*/GIMT_Encode2(AMDGPU::DS_READ_B64_gfx9),
      GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/0, // DstI[vdst]
      GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/0, // ptr
      GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/1, // offset
      GIR_AddImm8, /*InsnID*/0, /*Imm*/0,
      GIR_MergeMemOperands, /*InsnID*/0, /*NumInsns*/1, /*MergeInsnID's*/0,
      GIR_ConstrainSelectedInstOperands, /*InsnID*/0,
      GIR_EraseFromParent, /*InsnID*/0,
      // GIR_Coverage, 6740,
      GIR_Done,
    // Label 1176: @77709
    GIM_Try, /*On fail goto*//*Label 1177*/ GIMT_Encode4(77775), // Rule ID 6744 //
      GIM_CheckFeatures, GIMT_Encode2(GIFBS_NotLDSRequiresM0Init),
      GIM_CheckMemoryAddressSpace, /*MI*/0, /*MMO*/0, /*NumAddrSpace*/1, /*AddrSpace*/3,
      GIM_CheckMemoryAlignment, /*MI*/0, /*MMO*/0, /*MinAlign*/8,
      GIM_CheckAtomicOrdering, /*MI*/0, /*Order*/(uint8_t)AtomicOrdering::NotAtomic,
      GIM_CheckRegBankForClass, /*MI*/0, /*Op*/0, /*RC*/GIMT_Encode2(AMDGPU::AV_64RegClassID),
      GIM_CheckPointerToAny, /*MI*/0, /*Op*/1, /*SizeInBits*/0,
      GIM_CheckComplexPattern, /*MI*/0, /*Op*/1, /*Renderer*/GIMT_Encode2(0), GIMT_Encode2(GICP_gi_ds_1addr_1offset),
      // (ld:{ *:[f64] } (DS1Addr1Offset:{ *:[iPTR] } i32:{ *:[i32] }:$ptr, i32:{ *:[i32] }:$offset))<<P:Predicate_unindexedload>><<P:Predicate_load_local>><<P:Predicate_load_align8_local>>  =>  (DS_READ_B64_gfx9:{ *:[f64] } ?:{ *:[i32] }:$ptr, offset:{ *:[i32] }:$offset, 0:{ *:[i1] })
      GIR_BuildMI, /*InsnID*/0, /*Opcode*/GIMT_Encode2(AMDGPU::DS_READ_B64_gfx9),
      GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/0, // DstI[vdst]
      GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/0, // ptr
      GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/1, // offset
      GIR_AddImm8, /*InsnID*/0, /*Imm*/0,
      GIR_MergeMemOperands, /*InsnID*/0, /*NumInsns*/1, /*MergeInsnID's*/0,
      GIR_ConstrainSelectedInstOperands, /*InsnID*/0,
      GIR_EraseFromParent, /*InsnID*/0,
      // GIR_Coverage, 6744,
      GIR_Done,
    // Label 1177: @77775
    GIM_Try, /*On fail goto*//*Label 1178*/ GIMT_Encode4(77832), // Rule ID 2511 //
      GIM_CheckMemorySizeEqualToLLT, /*MI*/0, /*MMO*/0, /*OpIdx*/0,
      GIM_CheckAtomicOrdering, /*MI*/0, /*Order*/(uint8_t)AtomicOrdering::NotAtomic,
      GIM_CheckRegBankForClass, /*MI*/0, /*Op*/0, /*RC*/GIMT_Encode2(AMDGPU::SReg_64_XEXECRegClassID),
      // MIs[0] sbase
      GIM_CheckPointerToAny, /*MI*/0, /*Op*/1, /*SizeInBits*/64,
      GIM_CheckRegBankForClass, /*MI*/0, /*Op*/1, /*RC*/GIMT_Encode2(AMDGPU::SReg_64RegClassID),
      GIM_CheckCxxInsnPredicate, /*MI*/0, /*FnId*/GIMT_Encode2(GICXXPred_MI_Predicate_smrd_load),
      // (ld:{ *:[i64] } SReg_64:{ *:[i64] }:$sbase)<<P:Predicate_unindexedload>><<P:Predicate_load>><<P:Predicate_smrd_load>>  =>  (S_LOAD_DWORDX2_IMM:{ *:[i64] } i64:{ *:[i64] }:$sbase, 0:{ *:[i32] }, 0:{ *:[i32] })
      GIR_BuildMI, /*InsnID*/0, /*Opcode*/GIMT_Encode2(AMDGPU::S_LOAD_DWORDX2_IMM),
      GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/0, // DstI[sdst]
      GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/1, // sbase
      GIR_AddImm8, /*InsnID*/0, /*Imm*/0,
      GIR_AddImm8, /*InsnID*/0, /*Imm*/0,
      GIR_MergeMemOperands, /*InsnID*/0, /*NumInsns*/1, /*MergeInsnID's*/0,
      GIR_ConstrainSelectedInstOperands, /*InsnID*/0,
      GIR_EraseFromParent, /*InsnID*/0,
      // GIR_Coverage, 2511,
      GIR_Done,
    // Label 1178: @77832
    GIM_Try, /*On fail goto*//*Label 1179*/ GIMT_Encode4(77889), // Rule ID 2523 //
      GIM_CheckMemorySizeEqualToLLT, /*MI*/0, /*MMO*/0, /*OpIdx*/0,
      GIM_CheckAtomicOrdering, /*MI*/0, /*Order*/(uint8_t)AtomicOrdering::NotAtomic,
      GIM_CheckRegBankForClass, /*MI*/0, /*Op*/0, /*RC*/GIMT_Encode2(AMDGPU::SReg_64_XEXECRegClassID),
      // MIs[0] sbase
      GIM_CheckPointerToAny, /*MI*/0, /*Op*/1, /*SizeInBits*/64,
      GIM_CheckRegBankForClass, /*MI*/0, /*Op*/1, /*RC*/GIMT_Encode2(AMDGPU::SReg_64RegClassID),
      GIM_CheckCxxInsnPredicate, /*MI*/0, /*FnId*/GIMT_Encode2(GICXXPred_MI_Predicate_smrd_load),
      // (ld:{ *:[f64] } SReg_64:{ *:[i64] }:$sbase)<<P:Predicate_unindexedload>><<P:Predicate_load>><<P:Predicate_smrd_load>>  =>  (S_LOAD_DWORDX2_IMM:{ *:[f64] } i64:{ *:[i64] }:$sbase, 0:{ *:[i32] }, 0:{ *:[i32] })
      GIR_BuildMI, /*InsnID*/0, /*Opcode*/GIMT_Encode2(AMDGPU::S_LOAD_DWORDX2_IMM),
      GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/0, // DstI[sdst]
      GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/1, // sbase
      GIR_AddImm8, /*InsnID*/0, /*Imm*/0,
      GIR_AddImm8, /*InsnID*/0, /*Imm*/0,
      GIR_MergeMemOperands, /*InsnID*/0, /*NumInsns*/1, /*MergeInsnID's*/0,
      GIR_ConstrainSelectedInstOperands, /*InsnID*/0,
      GIR_EraseFromParent, /*InsnID*/0,
      // GIR_Coverage, 2523,
      GIR_Done,
    // Label 1179: @77889
    GIM_Try, /*On fail goto*//*Label 1180*/ GIMT_Encode4(77956), // Rule ID 3484 //
      GIM_CheckFeatures, GIMT_Encode2(GIFBS_EnableFlatScratch_HasFlatScratchInsts_HasFlatScratchSVSMode),
      GIM_CheckMemoryAddressSpace, /*MI*/0, /*MMO*/0, /*NumAddrSpace*/1, /*AddrSpace*/5,
      GIM_CheckAtomicOrdering, /*MI*/0, /*Order*/(uint8_t)AtomicOrdering::NotAtomic,
      GIM_CheckRegBankForClass, /*MI*/0, /*Op*/0, /*RC*/GIMT_Encode2(AMDGPU::AV_64RegClassID),
      GIM_CheckPointerToAny, /*MI*/0, /*Op*/1, /*SizeInBits*/0,
      GIM_CheckComplexPattern, /*MI*/0, /*Op*/1, /*Renderer*/GIMT_Encode2(0), GIMT_Encode2(GICP_gi_flat_scratch_svaddr),
      // (ld:{ *:[i64] } (ScratchSVAddr:{ *:[iPTR] } VGPR_32:{ *:[i32] }:$vaddr, SGPR_32:{ *:[i32] }:$saddr, i32:{ *:[i32] }:$offset))<<P:Predicate_unindexedload>><<P:Predicate_load_private>>  =>  (SCRATCH_LOAD_DWORDX2_SVS:{ *:[i64] } ?:{ *:[i32] }:$vaddr, ?:{ *:[i32] }:$saddr, ?:{ *:[i32] }:$offset, 0:{ *:[i32] })
      GIR_BuildMI, /*InsnID*/0, /*Opcode*/GIMT_Encode2(AMDGPU::SCRATCH_LOAD_DWORDX2_SVS),
      GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/0, // DstI[vdst]
      GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/0, // vaddr
      GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/1, // saddr
      GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/2, // offset
      GIR_AddImm8, /*InsnID*/0, /*Imm*/0,
      GIR_MergeMemOperands, /*InsnID*/0, /*NumInsns*/1, /*MergeInsnID's*/0,
      GIR_ConstrainSelectedInstOperands, /*InsnID*/0,
      GIR_EraseFromParent, /*InsnID*/0,
      // GIR_Coverage, 3484,
      GIR_Done,
    // Label 1180: @77956
    GIM_Try, /*On fail goto*//*Label 1181*/ GIMT_Encode4(78023), // Rule ID 3490 //
      GIM_CheckFeatures, GIMT_Encode2(GIFBS_EnableFlatScratch_HasFlatScratchInsts_HasFlatScratchSVSMode),
      GIM_CheckMemoryAddressSpace, /*MI*/0, /*MMO*/0, /*NumAddrSpace*/1, /*AddrSpace*/5,
      GIM_CheckAtomicOrdering, /*MI*/0, /*Order*/(uint8_t)AtomicOrdering::NotAtomic,
      GIM_CheckRegBankForClass, /*MI*/0, /*Op*/0, /*RC*/GIMT_Encode2(AMDGPU::AV_64RegClassID),
      GIM_CheckPointerToAny, /*MI*/0, /*Op*/1, /*SizeInBits*/0,
      GIM_CheckComplexPattern, /*MI*/0, /*Op*/1, /*Renderer*/GIMT_Encode2(0), GIMT_Encode2(GICP_gi_flat_scratch_svaddr),
      // (ld:{ *:[f64] } (ScratchSVAddr:{ *:[iPTR] } VGPR_32:{ *:[i32] }:$vaddr, SGPR_32:{ *:[i32] }:$saddr, i32:{ *:[i32] }:$offset))<<P:Predicate_unindexedload>><<P:Predicate_load_private>>  =>  (SCRATCH_LOAD_DWORDX2_SVS:{ *:[f64] } ?:{ *:[i32] }:$vaddr, ?:{ *:[i32] }:$saddr, ?:{ *:[i32] }:$offset, 0:{ *:[i32] })
      GIR_BuildMI, /*InsnID*/0, /*Opcode*/GIMT_Encode2(AMDGPU::SCRATCH_LOAD_DWORDX2_SVS),
      GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/0, // DstI[vdst]
      GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/0, // vaddr
      GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/1, // saddr
      GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/2, // offset
      GIR_AddImm8, /*InsnID*/0, /*Imm*/0,
      GIR_MergeMemOperands, /*InsnID*/0, /*NumInsns*/1, /*MergeInsnID's*/0,
      GIR_ConstrainSelectedInstOperands, /*InsnID*/0,
      GIR_EraseFromParent, /*InsnID*/0,
      // GIR_Coverage, 3490,
      GIR_Done,
    // Label 1181: @78023
    GIM_Try, /*On fail goto*//*Label 1182*/ GIMT_Encode4(78085), // Rule ID 3483 //
      GIM_CheckFeatures, GIMT_Encode2(GIFBS_EnableFlatScratch_HasFlatScratchInsts),
      GIM_CheckMemoryAddressSpace, /*MI*/0, /*MMO*/0, /*NumAddrSpace*/1, /*AddrSpace*/5,
      GIM_CheckAtomicOrdering, /*MI*/0, /*Order*/(uint8_t)AtomicOrdering::NotAtomic,
      GIM_CheckRegBankForClass, /*MI*/0, /*Op*/0, /*RC*/GIMT_Encode2(AMDGPU::AV_64RegClassID),
      GIM_CheckPointerToAny, /*MI*/0, /*Op*/1, /*SizeInBits*/0,
      GIM_CheckComplexPattern, /*MI*/0, /*Op*/1, /*Renderer*/GIMT_Encode2(0), GIMT_Encode2(GICP_gi_flat_scratch_saddr),
      // (ld:{ *:[i64] } (ScratchSAddr:{ *:[iPTR] } SGPR_32:{ *:[i32] }:$saddr, i32:{ *:[i32] }:$offset))<<P:Predicate_unindexedload>><<P:Predicate_load_private>>  =>  (SCRATCH_LOAD_DWORDX2_SADDR:{ *:[i64] } ?:{ *:[i32] }:$saddr, ?:{ *:[i32] }:$offset)
      GIR_BuildMI, /*InsnID*/0, /*Opcode*/GIMT_Encode2(AMDGPU::SCRATCH_LOAD_DWORDX2_SADDR),
      GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/0, // DstI[vdst]
      GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/0, // saddr
      GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/1, // offset
      GIR_AddImm8, /*InsnID*/0, /*Imm*/0,
      GIR_MergeMemOperands, /*InsnID*/0, /*NumInsns*/1, /*MergeInsnID's*/0,
      GIR_ConstrainSelectedInstOperands, /*InsnID*/0,
      GIR_EraseFromParent, /*InsnID*/0,
      // GIR_Coverage, 3483,
      GIR_Done,
    // Label 1182: @78085
    GIM_Try, /*On fail goto*//*Label 1183*/ GIMT_Encode4(78147), // Rule ID 3489 //
      GIM_CheckFeatures, GIMT_Encode2(GIFBS_EnableFlatScratch_HasFlatScratchInsts),
      GIM_CheckMemoryAddressSpace, /*MI*/0, /*MMO*/0, /*NumAddrSpace*/1, /*AddrSpace*/5,
      GIM_CheckAtomicOrdering, /*MI*/0, /*Order*/(uint8_t)AtomicOrdering::NotAtomic,
      GIM_CheckRegBankForClass, /*MI*/0, /*Op*/0, /*RC*/GIMT_Encode2(AMDGPU::AV_64RegClassID),
      GIM_CheckPointerToAny, /*MI*/0, /*Op*/1, /*SizeInBits*/0,
      GIM_CheckComplexPattern, /*MI*/0, /*Op*/1, /*Renderer*/GIMT_Encode2(0), GIMT_Encode2(GICP_gi_flat_scratch_saddr),
      // (ld:{ *:[f64] } (ScratchSAddr:{ *:[iPTR] } SGPR_32:{ *:[i32] }:$saddr, i32:{ *:[i32] }:$offset))<<P:Predicate_unindexedload>><<P:Predicate_load_private>>  =>  (SCRATCH_LOAD_DWORDX2_SADDR:{ *:[f64] } ?:{ *:[i32] }:$saddr, ?:{ *:[i32] }:$offset)
      GIR_BuildMI, /*InsnID*/0, /*Opcode*/GIMT_Encode2(AMDGPU::SCRATCH_LOAD_DWORDX2_SADDR),
      GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/0, // DstI[vdst]
      GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/0, // saddr
      GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/1, // offset
      GIR_AddImm8, /*InsnID*/0, /*Imm*/0,
      GIR_MergeMemOperands, /*InsnID*/0, /*NumInsns*/1, /*MergeInsnID's*/0,
      GIR_ConstrainSelectedInstOperands, /*InsnID*/0,
      GIR_EraseFromParent, /*InsnID*/0,
      // GIR_Coverage, 3489,
      GIR_Done,
    // Label 1183: @78147
    GIM_Try, /*On fail goto*//*Label 1184*/ GIMT_Encode4(78209), // Rule ID 3482 //
      GIM_CheckFeatures, GIMT_Encode2(GIFBS_EnableFlatScratch_HasFlatScratchInsts),
      GIM_CheckMemoryAddressSpace, /*MI*/0, /*MMO*/0, /*NumAddrSpace*/1, /*AddrSpace*/5,
      GIM_CheckAtomicOrdering, /*MI*/0, /*Order*/(uint8_t)AtomicOrdering::NotAtomic,
      GIM_CheckRegBankForClass, /*MI*/0, /*Op*/0, /*RC*/GIMT_Encode2(AMDGPU::AV_64RegClassID),
      GIM_CheckPointerToAny, /*MI*/0, /*Op*/1, /*SizeInBits*/0,
      GIM_CheckComplexPattern, /*MI*/0, /*Op*/1, /*Renderer*/GIMT_Encode2(0), GIMT_Encode2(GICP_gi_flat_scratch_offset),
      // (ld:{ *:[i64] } (ScratchOffset:{ *:[iPTR] } VGPR_32:{ *:[i32] }:$vaddr, i32:{ *:[i32] }:$offset))<<P:Predicate_unindexedload>><<P:Predicate_load_private>>  =>  (SCRATCH_LOAD_DWORDX2:{ *:[i64] } ?:{ *:[i32] }:$vaddr, ?:{ *:[i32] }:$offset)
      GIR_BuildMI, /*InsnID*/0, /*Opcode*/GIMT_Encode2(AMDGPU::SCRATCH_LOAD_DWORDX2),
      GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/0, // DstI[vdst]
      GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/0, // vaddr
      GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/1, // offset
      GIR_AddImm8, /*InsnID*/0, /*Imm*/0,
      GIR_MergeMemOperands, /*InsnID*/0, /*NumInsns*/1, /*MergeInsnID's*/0,
      GIR_ConstrainSelectedInstOperands, /*InsnID*/0,
      GIR_EraseFromParent, /*InsnID*/0,
      // GIR_Coverage, 3482,
      GIR_Done,
    // Label 1184: @78209
    GIM_Try, /*On fail goto*//*Label 1185*/ GIMT_Encode4(78271), // Rule ID 3488 //
      GIM_CheckFeatures, GIMT_Encode2(GIFBS_EnableFlatScratch_HasFlatScratchInsts),
      GIM_CheckMemoryAddressSpace, /*MI*/0, /*MMO*/0, /*NumAddrSpace*/1, /*AddrSpace*/5,
      GIM_CheckAtomicOrdering, /*MI*/0, /*Order*/(uint8_t)AtomicOrdering::NotAtomic,
      GIM_CheckRegBankForClass, /*MI*/0, /*Op*/0, /*RC*/GIMT_Encode2(AMDGPU::AV_64RegClassID),
      GIM_CheckPointerToAny, /*MI*/0, /*Op*/1, /*SizeInBits*/0,
      GIM_CheckComplexPattern, /*MI*/0, /*Op*/1, /*Renderer*/GIMT_Encode2(0), GIMT_Encode2(GICP_gi_flat_scratch_offset),
      // (ld:{ *:[f64] } (ScratchOffset:{ *:[iPTR] } VGPR_32:{ *:[i32] }:$vaddr, i32:{ *:[i32] }:$offset))<<P:Predicate_unindexedload>><<P:Predicate_load_private>>  =>  (SCRATCH_LOAD_DWORDX2:{ *:[f64] } ?:{ *:[i32] }:$vaddr, ?:{ *:[i32] }:$offset)
      GIR_BuildMI, /*InsnID*/0, /*Opcode*/GIMT_Encode2(AMDGPU::SCRATCH_LOAD_DWORDX2),
      GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/0, // DstI[vdst]
      GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/0, // vaddr
      GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/1, // offset
      GIR_AddImm8, /*InsnID*/0, /*Imm*/0,
      GIR_MergeMemOperands, /*InsnID*/0, /*NumInsns*/1, /*MergeInsnID's*/0,
      GIR_ConstrainSelectedInstOperands, /*InsnID*/0,
      GIR_EraseFromParent, /*InsnID*/0,
      // GIR_Coverage, 3488,
      GIR_Done,
    // Label 1185: @78271
    GIM_Try, /*On fail goto*//*Label 1186*/ GIMT_Encode4(78355), // Rule ID 5329 //
      GIM_CheckFeatures, GIMT_Encode2(GIFBS_isGFX6GFX7),
      GIM_CheckMemorySizeEqualTo, /*MI*/0, /*MMO*/0, /*Size*/GIMT_Encode4(8),
      GIM_CheckMemoryAddressSpace, /*MI*/0, /*MMO*/0, /*NumAddrSpace*/3, /*AddrSpace*/1, /*AddrSpace*/4, /*AddrSpace*/6,
      GIM_CheckAtomicOrderingOrStrongerThan, /*MI*/0, /*Order*/(uint8_t)AtomicOrdering::Unordered,
      GIM_CheckRegBankForClass, /*MI*/0, /*Op*/0, /*RC*/GIMT_Encode2(AMDGPU::AV_64RegClassID),
      GIM_CheckPointerToAny, /*MI*/0, /*Op*/1, /*SizeInBits*/0,
      GIM_CheckComplexPattern, /*MI*/0, /*Op*/1, /*Renderer*/GIMT_Encode2(0), GIMT_Encode2(GICP_gi_mubuf_addr64),
      // (atomic_load:{ *:[i64] } (MUBUFAddr64:{ *:[iPTR] } v4i32:{ *:[v4i32] }:$srsrc, i64:{ *:[i64] }:$vaddr, i32:{ *:[i32] }:$soffset, i32:{ *:[i32] }:$offset))<<P:Predicate_atomic_load_64>><<P:Predicate_atomic_load_64_global>>  =>  (BUFFER_LOAD_DWORDX2_ADDR64:{ *:[i64] } ?:{ *:[i64] }:$vaddr, ?:{ *:[v4i32] }:$srsrc, ?:{ *:[i32] }:$soffset, ?:{ *:[i32] }:$offset)
      GIR_BuildMI, /*InsnID*/0, /*Opcode*/GIMT_Encode2(AMDGPU::BUFFER_LOAD_DWORDX2_ADDR64),
      GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/0, // DstI[vdata]
      GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/1, // vaddr
      GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/0, // srsrc
      GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/2, // soffset
      GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/3, // offset
      GIR_AddImm8, /*InsnID*/0, /*Imm*/0,
      GIR_AddImm8, /*InsnID*/0, /*Imm*/0,
      GIR_MergeMemOperands, /*InsnID*/0, /*NumInsns*/1, /*MergeInsnID's*/0,
      GIR_ConstrainSelectedInstOperands, /*InsnID*/0,
      GIR_EraseFromParent, /*InsnID*/0,
      // GIR_Coverage, 5329,
      GIR_Done,
    // Label 1186: @78355
    GIM_Try, /*On fail goto*//*Label 1187*/ GIMT_Encode4(78432), // Rule ID 3720 //
      GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasUnrestrictedSOffset),
      GIM_CheckMemoryAddressSpace, /*MI*/0, /*MMO*/0, /*NumAddrSpace*/3, /*AddrSpace*/1, /*AddrSpace*/4, /*AddrSpace*/6,
      GIM_CheckAtomicOrdering, /*MI*/0, /*Order*/(uint8_t)AtomicOrdering::NotAtomic,
      GIM_CheckRegBankForClass, /*MI*/0, /*Op*/0, /*RC*/GIMT_Encode2(AMDGPU::AV_64RegClassID),
      GIM_CheckPointerToAny, /*MI*/0, /*Op*/1, /*SizeInBits*/0,
      GIM_CheckComplexPattern, /*MI*/0, /*Op*/1, /*Renderer*/GIMT_Encode2(0), GIMT_Encode2(GICP_gi_mubuf_addr64),
      // (ld:{ *:[i64] } (MUBUFAddr64:{ *:[iPTR] } v4i32:{ *:[v4i32] }:$srsrc, i64:{ *:[i64] }:$vaddr, i32:{ *:[i32] }:$soffset, i32:{ *:[i32] }:$offset))<<P:Predicate_unindexedload>><<P:Predicate_load_global>>  =>  (BUFFER_LOAD_DWORDX2_ADDR64:{ *:[i64] } i64:{ *:[i64] }:$vaddr, v4i32:{ *:[v4i32] }:$srsrc, i32:{ *:[i32] }:$soffset, i32:{ *:[i32] }:$offset)
      GIR_BuildMI, /*InsnID*/0, /*Opcode*/GIMT_Encode2(AMDGPU::BUFFER_LOAD_DWORDX2_ADDR64),
      GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/0, // DstI[vdata]
      GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/1, // vaddr
      GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/0, // srsrc
      GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/2, // soffset
      GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/3, // offset
      GIR_AddImm8, /*InsnID*/0, /*Imm*/0,
      GIR_AddImm8, /*InsnID*/0, /*Imm*/0,
      GIR_MergeMemOperands, /*InsnID*/0, /*NumInsns*/1, /*MergeInsnID's*/0,
      GIR_ConstrainSelectedInstOperands, /*InsnID*/0,
      GIR_EraseFromParent, /*InsnID*/0,
      // GIR_Coverage, 3720,
      GIR_Done,
    // Label 1187: @78432
    GIM_Try, /*On fail goto*//*Label 1188*/ GIMT_Encode4(78506), // Rule ID 3722 //
      GIM_CheckMemoryAddressSpace, /*MI*/0, /*MMO*/0, /*NumAddrSpace*/3, /*AddrSpace*/1, /*AddrSpace*/4, /*AddrSpace*/6,
      GIM_CheckAtomicOrdering, /*MI*/0, /*Order*/(uint8_t)AtomicOrdering::NotAtomic,
      GIM_CheckRegBankForClass, /*MI*/0, /*Op*/0, /*RC*/GIMT_Encode2(AMDGPU::AV_64RegClassID),
      GIM_CheckPointerToAny, /*MI*/0, /*Op*/1, /*SizeInBits*/0,
      GIM_CheckComplexPattern, /*MI*/0, /*Op*/1, /*Renderer*/GIMT_Encode2(0), GIMT_Encode2(GICP_gi_mubuf_addr64),
      // (ld:{ *:[i64] } (MUBUFAddr64:{ *:[iPTR] } v4i32:{ *:[v4i32] }:$srsrc, i64:{ *:[i64] }:$vaddr, i32:{ *:[i32] }:$soffset, i32:{ *:[i32] }:$offset))<<P:Predicate_unindexedload>><<P:Predicate_load_global>>  =>  (BUFFER_LOAD_DWORDX2_VBUFFER_ADDR64:{ *:[i64] } i64:{ *:[i64] }:$vaddr, v4i32:{ *:[v4i32] }:$srsrc, i32:{ *:[i32] }:$soffset, i32:{ *:[i32] }:$offset)
      GIR_BuildMI, /*InsnID*/0, /*Opcode*/GIMT_Encode2(AMDGPU::BUFFER_LOAD_DWORDX2_VBUFFER_ADDR64),
      GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/0, // DstI[vdata]
      GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/1, // vaddr
      GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/0, // srsrc
      GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/2, // soffset
      GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/3, // offset
      GIR_AddImm8, /*InsnID*/0, /*Imm*/0,
      GIR_AddImm8, /*InsnID*/0, /*Imm*/0,
      GIR_MergeMemOperands, /*InsnID*/0, /*NumInsns*/1, /*MergeInsnID's*/0,
      GIR_ConstrainSelectedInstOperands, /*InsnID*/0,
      GIR_EraseFromParent, /*InsnID*/0,
      // GIR_Coverage, 3722,
      GIR_Done,
    // Label 1188: @78506
    GIM_Try, /*On fail goto*//*Label 1189*/ GIMT_Encode4(78583), // Rule ID 3724 //
      GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasUnrestrictedSOffset),
      GIM_CheckMemoryAddressSpace, /*MI*/0, /*MMO*/0, /*NumAddrSpace*/3, /*AddrSpace*/1, /*AddrSpace*/4, /*AddrSpace*/6,
      GIM_CheckAtomicOrdering, /*MI*/0, /*Order*/(uint8_t)AtomicOrdering::NotAtomic,
      GIM_CheckRegBankForClass, /*MI*/0, /*Op*/0, /*RC*/GIMT_Encode2(AMDGPU::AV_64RegClassID),
      GIM_CheckPointerToAny, /*MI*/0, /*Op*/1, /*SizeInBits*/0,
      GIM_CheckComplexPattern, /*MI*/0, /*Op*/1, /*Renderer*/GIMT_Encode2(0), GIMT_Encode2(GICP_gi_mubuf_addr64),
      // (ld:{ *:[f64] } (MUBUFAddr64:{ *:[iPTR] } v4i32:{ *:[v4i32] }:$srsrc, i64:{ *:[i64] }:$vaddr, i32:{ *:[i32] }:$soffset, i32:{ *:[i32] }:$offset))<<P:Predicate_unindexedload>><<P:Predicate_load_global>>  =>  (BUFFER_LOAD_DWORDX2_ADDR64:{ *:[f64] } i64:{ *:[i64] }:$vaddr, v4i32:{ *:[v4i32] }:$srsrc, i32:{ *:[i32] }:$soffset, i32:{ *:[i32] }:$offset)
      GIR_BuildMI, /*InsnID*/0, /*Opcode*/GIMT_Encode2(AMDGPU::BUFFER_LOAD_DWORDX2_ADDR64),
      GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/0, // DstI[vdata]
      GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/1, // vaddr
      GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/0, // srsrc
      GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/2, // soffset
      GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/3, // offset
      GIR_AddImm8, /*InsnID*/0, /*Imm*/0,
      GIR_AddImm8, /*InsnID*/0, /*Imm*/0,
      GIR_MergeMemOperands, /*InsnID*/0, /*NumInsns*/1, /*MergeInsnID's*/0,
      GIR_ConstrainSelectedInstOperands, /*InsnID*/0,
      GIR_EraseFromParent, /*InsnID*/0,
      // GIR_Coverage, 3724,
      GIR_Done,
    // Label 1189: @78583
    GIM_Try, /*On fail goto*//*Label 1190*/ GIMT_Encode4(78657), // Rule ID 3726 //
      GIM_CheckMemoryAddressSpace, /*MI*/0, /*MMO*/0, /*NumAddrSpace*/3, /*AddrSpace*/1, /*AddrSpace*/4, /*AddrSpace*/6,
      GIM_CheckAtomicOrdering, /*MI*/0, /*Order*/(uint8_t)AtomicOrdering::NotAtomic,
      GIM_CheckRegBankForClass, /*MI*/0, /*Op*/0, /*RC*/GIMT_Encode2(AMDGPU::AV_64RegClassID),
      GIM_CheckPointerToAny, /*MI*/0, /*Op*/1, /*SizeInBits*/0,
      GIM_CheckComplexPattern, /*MI*/0, /*Op*/1, /*Renderer*/GIMT_Encode2(0), GIMT_Encode2(GICP_gi_mubuf_addr64),
      // (ld:{ *:[f64] } (MUBUFAddr64:{ *:[iPTR] } v4i32:{ *:[v4i32] }:$srsrc, i64:{ *:[i64] }:$vaddr, i32:{ *:[i32] }:$soffset, i32:{ *:[i32] }:$offset))<<P:Predicate_unindexedload>><<P:Predicate_load_global>>  =>  (BUFFER_LOAD_DWORDX2_VBUFFER_ADDR64:{ *:[f64] } i64:{ *:[i64] }:$vaddr, v4i32:{ *:[v4i32] }:$srsrc, i32:{ *:[i32] }:$soffset, i32:{ *:[i32] }:$offset)
      GIR_BuildMI, /*InsnID*/0, /*Opcode*/GIMT_Encode2(AMDGPU::BUFFER_LOAD_DWORDX2_VBUFFER_ADDR64),
      GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/0, // DstI[vdata]
      GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/1, // vaddr
      GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/0, // srsrc
      GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/2, // soffset
      GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/3, // offset
      GIR_AddImm8, /*InsnID*/0, /*Imm*/0,
      GIR_AddImm8, /*InsnID*/0, /*Imm*/0,
      GIR_MergeMemOperands, /*InsnID*/0, /*NumInsns*/1, /*MergeInsnID's*/0,
      GIR_ConstrainSelectedInstOperands, /*InsnID*/0,
      GIR_EraseFromParent, /*InsnID*/0,
      // GIR_Coverage, 3726,
      GIR_Done,
    // Label 1190: @78657
    GIM_Try, /*On fail goto*//*Label 1191*/ GIMT_Encode4(78728), // Rule ID 6671 //
      GIM_CheckFeatures, GIMT_Encode2(GIFBS_LDSRequiresM0Init_isGFX7Plus),
      GIM_CheckMemorySizeEqualToLLT, /*MI*/0, /*MMO*/0, /*OpIdx*/0,
      GIM_CheckMemoryAddressSpace, /*MI*/0, /*MMO*/0, /*NumAddrSpace*/1, /*AddrSpace*/3,
      GIM_CheckAtomicOrdering, /*MI*/0, /*Order*/(uint8_t)AtomicOrdering::NotAtomic,
      GIM_CheckRegBankForClass, /*MI*/0, /*Op*/0, /*RC*/GIMT_Encode2(AMDGPU::AV_64RegClassID),
      GIM_CheckPointerToAny, /*MI*/0, /*Op*/1, /*SizeInBits*/0,
      GIM_CheckComplexPattern, /*MI*/0, /*Op*/1, /*Renderer*/GIMT_Encode2(0), GIMT_Encode2(GICP_gi_ds_64bit_4byte_aligned),
      // (AMDGPUld_glue:{ *:[i64] } (DS64Bit4ByteAligned:{ *:[iPTR] } i32:{ *:[i32] }:$ptr, i8:{ *:[i8] }:$offset0, i8:{ *:[i8] }:$offset1))<<P:Predicate_unindexedload_glue>><<P:Predicate_load_glue>><<P:Predicate_load_local_m0>>  =>  (DS_READ2_B32:{ *:[i64] } ?:{ *:[i32] }:$ptr, ?:{ *:[i8] }:$offset0, ?:{ *:[i8] }:$offset1, 0:{ *:[i1] })
      GIR_BuildMI, /*InsnID*/0, /*Opcode*/GIMT_Encode2(AMDGPU::DS_READ2_B32),
      GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/0, // DstI[vdst]
      GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/0, // ptr
      GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/1, // offset0
      GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/2, // offset1
      GIR_AddImm8, /*InsnID*/0, /*Imm*/0,
      GIR_MergeMemOperands, /*InsnID*/0, /*NumInsns*/1, /*MergeInsnID's*/0,
      GIR_ConstrainSelectedInstOperands, /*InsnID*/0,
      GIR_EraseFromParent, /*InsnID*/0,
      // GIR_Coverage, 6671,
      GIR_Done,
    // Label 1191: @78728
    GIM_Try, /*On fail goto*//*Label 1192*/ GIMT_Encode4(78799), // Rule ID 6679 //
      GIM_CheckFeatures, GIMT_Encode2(GIFBS_LDSRequiresM0Init_isGFX7Plus),
      GIM_CheckMemorySizeEqualToLLT, /*MI*/0, /*MMO*/0, /*OpIdx*/0,
      GIM_CheckMemoryAddressSpace, /*MI*/0, /*MMO*/0, /*NumAddrSpace*/1, /*AddrSpace*/3,
      GIM_CheckAtomicOrdering, /*MI*/0, /*Order*/(uint8_t)AtomicOrdering::NotAtomic,
      GIM_CheckRegBankForClass, /*MI*/0, /*Op*/0, /*RC*/GIMT_Encode2(AMDGPU::AV_64RegClassID),
      GIM_CheckPointerToAny, /*MI*/0, /*Op*/1, /*SizeInBits*/0,
      GIM_CheckComplexPattern, /*MI*/0, /*Op*/1, /*Renderer*/GIMT_Encode2(0), GIMT_Encode2(GICP_gi_ds_64bit_4byte_aligned),
      // (AMDGPUld_glue:{ *:[f64] } (DS64Bit4ByteAligned:{ *:[iPTR] } i32:{ *:[i32] }:$ptr, i8:{ *:[i8] }:$offset0, i8:{ *:[i8] }:$offset1))<<P:Predicate_unindexedload_glue>><<P:Predicate_load_glue>><<P:Predicate_load_local_m0>>  =>  (DS_READ2_B32:{ *:[f64] } ?:{ *:[i32] }:$ptr, ?:{ *:[i8] }:$offset0, ?:{ *:[i8] }:$offset1, 0:{ *:[i1] })
      GIR_BuildMI, /*InsnID*/0, /*Opcode*/GIMT_Encode2(AMDGPU::DS_READ2_B32),
      GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/0, // DstI[vdst]
      GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/0, // ptr
      GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/1, // offset0
      GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/2, // offset1
      GIR_AddImm8, /*InsnID*/0, /*Imm*/0,
      GIR_MergeMemOperands, /*InsnID*/0, /*NumInsns*/1, /*MergeInsnID's*/0,
      GIR_ConstrainSelectedInstOperands, /*InsnID*/0,
      GIR_EraseFromParent, /*InsnID*/0,
      // GIR_Coverage, 6679,
      GIR_Done,
    // Label 1192: @78799
    GIM_Try, /*On fail goto*//*Label 1193*/ GIMT_Encode4(78869), // Rule ID 7096 //
      GIM_CheckFeatures, GIMT_Encode2(GIFBS_isGFX9Plus),
      GIM_CheckMemorySizeEqualToLLT, /*MI*/0, /*MMO*/0, /*OpIdx*/0,
      GIM_CheckAtomicOrdering, /*MI*/0, /*Order*/(uint8_t)AtomicOrdering::NotAtomic,
      GIM_CheckRegBankForClass, /*MI*/0, /*Op*/0, /*RC*/GIMT_Encode2(AMDGPU::SReg_64_XEXECRegClassID),
      GIM_CheckPointerToAny, /*MI*/0, /*Op*/1, /*SizeInBits*/0,
      GIM_CheckCxxInsnPredicate, /*MI*/0, /*FnId*/GIMT_Encode2(GICXXPred_MI_Predicate_smrd_load),
      GIM_CheckComplexPattern, /*MI*/0, /*Op*/1, /*Renderer*/GIMT_Encode2(0), GIMT_Encode2(GICP_gi_smrd_sgpr_imm),
      // (ld:{ *:[i64] } (SMRDSgprImm:{ *:[iPTR] } i64:{ *:[i64] }:$sbase, i32:{ *:[i32] }:$soffset, i32:{ *:[i32] }:$offset))<<P:Predicate_unindexedload>><<P:Predicate_load>><<P:Predicate_smrd_load>>  =>  (S_LOAD_DWORDX2_SGPR_IMM:{ *:[i64] } ?:{ *:[i64] }:$sbase, ?:{ *:[i32] }:$soffset, ?:{ *:[i32] }:$offset, 0:{ *:[i32] })
      GIR_BuildMI, /*InsnID*/0, /*Opcode*/GIMT_Encode2(AMDGPU::S_LOAD_DWORDX2_SGPR_IMM),
      GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/0, // DstI[sdst]
      GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/0, // sbase
      GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/1, // soffset
      GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/2, // offset
      GIR_AddImm8, /*InsnID*/0, /*Imm*/0,
      GIR_MergeMemOperands, /*InsnID*/0, /*NumInsns*/1, /*MergeInsnID's*/0,
      GIR_ConstrainSelectedInstOperands, /*InsnID*/0,
      GIR_EraseFromParent, /*InsnID*/0,
      // GIR_Coverage, 7096,
      GIR_Done,
    // Label 1193: @78869
    GIM_Try, /*On fail goto*//*Label 1194*/ GIMT_Encode4(78941), // Rule ID 3719 //
      GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasUnrestrictedSOffset),
      GIM_CheckMemoryAddressSpace, /*MI*/0, /*MMO*/0, /*NumAddrSpace*/3, /*AddrSpace*/1, /*AddrSpace*/4, /*AddrSpace*/6,
      GIM_CheckAtomicOrdering, /*MI*/0, /*Order*/(uint8_t)AtomicOrdering::NotAtomic,
      GIM_CheckRegBankForClass, /*MI*/0, /*Op*/0, /*RC*/GIMT_Encode2(AMDGPU::AV_64RegClassID),
      GIM_CheckPointerToAny, /*MI*/0, /*Op*/1, /*SizeInBits*/0,
      GIM_CheckComplexPattern, /*MI*/0, /*Op*/1, /*Renderer*/GIMT_Encode2(0), GIMT_Encode2(GICP_gi_mubuf_offset),
      // (ld:{ *:[i64] } (MUBUFOffset:{ *:[iPTR] } v4i32:{ *:[v4i32] }:$srsrc, i32:{ *:[i32] }:$soffset, i32:{ *:[i32] }:$offset))<<P:Predicate_unindexedload>><<P:Predicate_load_global>>  =>  (BUFFER_LOAD_DWORDX2_OFFSET:{ *:[i64] } v4i32:{ *:[v4i32] }:$srsrc, i32:{ *:[i32] }:$soffset, i32:{ *:[i32] }:$offset)
      GIR_BuildMI, /*InsnID*/0, /*Opcode*/GIMT_Encode2(AMDGPU::BUFFER_LOAD_DWORDX2_OFFSET),
      GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/0, // DstI[vdata]
      GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/0, // srsrc
      GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/1, // soffset
      GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/2, // offset
      GIR_AddImm8, /*InsnID*/0, /*Imm*/0,
      GIR_AddImm8, /*InsnID*/0, /*Imm*/0,
      GIR_MergeMemOperands, /*InsnID*/0, /*NumInsns*/1, /*MergeInsnID's*/0,
      GIR_ConstrainSelectedInstOperands, /*InsnID*/0,
      GIR_EraseFromParent, /*InsnID*/0,
      // GIR_Coverage, 3719,
      GIR_Done,
    // Label 1194: @78941
    GIM_Try, /*On fail goto*//*Label 1195*/ GIMT_Encode4(79010), // Rule ID 3721 //
      GIM_CheckMemoryAddressSpace, /*MI*/0, /*MMO*/0, /*NumAddrSpace*/3, /*AddrSpace*/1, /*AddrSpace*/4, /*AddrSpace*/6,
      GIM_CheckAtomicOrdering, /*MI*/0, /*Order*/(uint8_t)AtomicOrdering::NotAtomic,
      GIM_CheckRegBankForClass, /*MI*/0, /*Op*/0, /*RC*/GIMT_Encode2(AMDGPU::AV_64RegClassID),
      GIM_CheckPointerToAny, /*MI*/0, /*Op*/1, /*SizeInBits*/0,
      GIM_CheckComplexPattern, /*MI*/0, /*Op*/1, /*Renderer*/GIMT_Encode2(0), GIMT_Encode2(GICP_gi_mubuf_offset),
      // (ld:{ *:[i64] } (MUBUFOffset:{ *:[iPTR] } v4i32:{ *:[v4i32] }:$srsrc, i32:{ *:[i32] }:$soffset, i32:{ *:[i32] }:$offset))<<P:Predicate_unindexedload>><<P:Predicate_load_global>>  =>  (BUFFER_LOAD_DWORDX2_VBUFFER_OFFSET:{ *:[i64] } v4i32:{ *:[v4i32] }:$srsrc, i32:{ *:[i32] }:$soffset, i32:{ *:[i32] }:$offset)
      GIR_BuildMI, /*InsnID*/0, /*Opcode*/GIMT_Encode2(AMDGPU::BUFFER_LOAD_DWORDX2_VBUFFER_OFFSET),
      GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/0, // DstI[vdata]
      GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/0, // srsrc
      GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/1, // soffset
      GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/2, // offset
      GIR_AddImm8, /*InsnID*/0, /*Imm*/0,
      GIR_AddImm8, /*InsnID*/0, /*Imm*/0,
      GIR_MergeMemOperands, /*InsnID*/0, /*NumInsns*/1, /*MergeInsnID's*/0,
      GIR_ConstrainSelectedInstOperands, /*InsnID*/0,
      GIR_EraseFromParent, /*InsnID*/0,
      // GIR_Coverage, 3721,
      GIR_Done,
    // Label 1195: @79010
    GIM_Try, /*On fail goto*//*Label 1196*/ GIMT_Encode4(79082), // Rule ID 3723 //
      GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasUnrestrictedSOffset),
      GIM_CheckMemoryAddressSpace, /*MI*/0, /*MMO*/0, /*NumAddrSpace*/3, /*AddrSpace*/1, /*AddrSpace*/4, /*AddrSpace*/6,
      GIM_CheckAtomicOrdering, /*MI*/0, /*Order*/(uint8_t)AtomicOrdering::NotAtomic,
      GIM_CheckRegBankForClass, /*MI*/0, /*Op*/0, /*RC*/GIMT_Encode2(AMDGPU::AV_64RegClassID),
      GIM_CheckPointerToAny, /*MI*/0, /*Op*/1, /*SizeInBits*/0,
      GIM_CheckComplexPattern, /*MI*/0, /*Op*/1, /*Renderer*/GIMT_Encode2(0), GIMT_Encode2(GICP_gi_mubuf_offset),
      // (ld:{ *:[f64] } (MUBUFOffset:{ *:[iPTR] } v4i32:{ *:[v4i32] }:$srsrc, i32:{ *:[i32] }:$soffset, i32:{ *:[i32] }:$offset))<<P:Predicate_unindexedload>><<P:Predicate_load_global>>  =>  (BUFFER_LOAD_DWORDX2_OFFSET:{ *:[f64] } v4i32:{ *:[v4i32] }:$srsrc, i32:{ *:[i32] }:$soffset, i32:{ *:[i32] }:$offset)
      GIR_BuildMI, /*InsnID*/0, /*Opcode*/GIMT_Encode2(AMDGPU::BUFFER_LOAD_DWORDX2_OFFSET),
      GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/0, // DstI[vdata]
      GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/0, // srsrc
      GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/1, // soffset
      GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/2, // offset
      GIR_AddImm8, /*InsnID*/0, /*Imm*/0,
      GIR_AddImm8, /*InsnID*/0, /*Imm*/0,
      GIR_MergeMemOperands, /*InsnID*/0, /*NumInsns*/1, /*MergeInsnID's*/0,
      GIR_ConstrainSelectedInstOperands, /*InsnID*/0,
      GIR_EraseFromParent, /*InsnID*/0,
      // GIR_Coverage, 3723,
      GIR_Done,
    // Label 1196: @79082
    GIM_Try, /*On fail goto*//*Label 1197*/ GIMT_Encode4(79151), // Rule ID 3725 //
      GIM_CheckMemoryAddressSpace, /*MI*/0, /*MMO*/0, /*NumAddrSpace*/3, /*AddrSpace*/1, /*AddrSpace*/4, /*AddrSpace*/6,
      GIM_CheckAtomicOrdering, /*MI*/0, /*Order*/(uint8_t)AtomicOrdering::NotAtomic,
      GIM_CheckRegBankForClass, /*MI*/0, /*Op*/0, /*RC*/GIMT_Encode2(AMDGPU::AV_64RegClassID),
      GIM_CheckPointerToAny, /*MI*/0, /*Op*/1, /*SizeInBits*/0,
      GIM_CheckComplexPattern, /*MI*/0, /*Op*/1, /*Renderer*/GIMT_Encode2(0), GIMT_Encode2(GICP_gi_mubuf_offset),
      // (ld:{ *:[f64] } (MUBUFOffset:{ *:[iPTR] } v4i32:{ *:[v4i32] }:$srsrc, i32:{ *:[i32] }:$soffset, i32:{ *:[i32] }:$offset))<<P:Predicate_unindexedload>><<P:Predicate_load_global>>  =>  (BUFFER_LOAD_DWORDX2_VBUFFER_OFFSET:{ *:[f64] } v4i32:{ *:[v4i32] }:$srsrc, i32:{ *:[i32] }:$soffset, i32:{ *:[i32] }:$offset)
      GIR_BuildMI, /*InsnID*/0, /*Opcode*/GIMT_Encode2(AMDGPU::BUFFER_LOAD_DWORDX2_VBUFFER_OFFSET),
      GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/0, // DstI[vdata]
      GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/0, // srsrc
      GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/1, // soffset
      GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/2, // offset
      GIR_AddImm8, /*InsnID*/0, /*Imm*/0,
      GIR_AddImm8, /*InsnID*/0, /*Imm*/0,
      GIR_MergeMemOperands, /*InsnID*/0, /*NumInsns*/1, /*MergeInsnID's*/0,
      GIR_ConstrainSelectedInstOperands, /*InsnID*/0,
      GIR_EraseFromParent, /*InsnID*/0,
      // GIR_Coverage, 3725,
      GIR_Done,
    // Label 1197: @79151
    GIM_Try, /*On fail goto*//*Label 1198*/ GIMT_Encode4(79218), // Rule ID 6673 //
      GIM_CheckFeatures, GIMT_Encode2(GIFBS_NotLDSRequiresM0Init),
      GIM_CheckMemoryAddressSpace, /*MI*/0, /*MMO*/0, /*NumAddrSpace*/1, /*AddrSpace*/3,
      GIM_CheckAtomicOrdering, /*MI*/0, /*Order*/(uint8_t)AtomicOrdering::NotAtomic,
      GIM_CheckRegBankForClass, /*MI*/0, /*Op*/0, /*RC*/GIMT_Encode2(AMDGPU::AV_64RegClassID),
      GIM_CheckPointerToAny, /*MI*/0, /*Op*/1, /*SizeInBits*/0,
      GIM_CheckComplexPattern, /*MI*/0, /*Op*/1, /*Renderer*/GIMT_Encode2(0), GIMT_Encode2(GICP_gi_ds_64bit_4byte_aligned),
      // (ld:{ *:[i64] } (DS64Bit4ByteAligned:{ *:[iPTR] } i32:{ *:[i32] }:$ptr, i8:{ *:[i8] }:$offset0, i8:{ *:[i8] }:$offset1))<<P:Predicate_unindexedload>><<P:Predicate_load_local>>  =>  (DS_READ2_B32_gfx9:{ *:[i64] } ?:{ *:[i32] }:$ptr, ?:{ *:[i8] }:$offset0, ?:{ *:[i8] }:$offset1, 0:{ *:[i1] })
      GIR_BuildMI, /*InsnID*/0, /*Opcode*/GIMT_Encode2(AMDGPU::DS_READ2_B32_gfx9),
      GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/0, // DstI[vdst]
      GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/0, // ptr
      GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/1, // offset0
      GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/2, // offset1
      GIR_AddImm8, /*InsnID*/0, /*Imm*/0,
      GIR_MergeMemOperands, /*InsnID*/0, /*NumInsns*/1, /*MergeInsnID's*/0,
      GIR_ConstrainSelectedInstOperands, /*InsnID*/0,
      GIR_EraseFromParent, /*InsnID*/0,
      // GIR_Coverage, 6673,
      GIR_Done,
    // Label 1198: @79218
    GIM_Try, /*On fail goto*//*Label 1199*/ GIMT_Encode4(79285), // Rule ID 6681 //
      GIM_CheckFeatures, GIMT_Encode2(GIFBS_NotLDSRequiresM0Init),
      GIM_CheckMemoryAddressSpace, /*MI*/0, /*MMO*/0, /*NumAddrSpace*/1, /*AddrSpace*/3,
      GIM_CheckAtomicOrdering, /*MI*/0, /*Order*/(uint8_t)AtomicOrdering::NotAtomic,
      GIM_CheckRegBankForClass, /*MI*/0, /*Op*/0, /*RC*/GIMT_Encode2(AMDGPU::AV_64RegClassID),
      GIM_CheckPointerToAny, /*MI*/0, /*Op*/1, /*SizeInBits*/0,
      GIM_CheckComplexPattern, /*MI*/0, /*Op*/1, /*Renderer*/GIMT_Encode2(0), GIMT_Encode2(GICP_gi_ds_64bit_4byte_aligned),
      // (ld:{ *:[f64] } (DS64Bit4ByteAligned:{ *:[iPTR] } i32:{ *:[i32] }:$ptr, i8:{ *:[i8] }:$offset0, i8:{ *:[i8] }:$offset1))<<P:Predicate_unindexedload>><<P:Predicate_load_local>>  =>  (DS_READ2_B32_gfx9:{ *:[f64] } ?:{ *:[i32] }:$ptr, ?:{ *:[i8] }:$offset0, ?:{ *:[i8] }:$offset1, 0:{ *:[i1] })
      GIR_BuildMI, /*InsnID*/0, /*Opcode*/GIMT_Encode2(AMDGPU::DS_READ2_B32_gfx9),
      GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/0, // DstI[vdst]
      GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/0, // ptr
      GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/1, // offset0
      GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/2, // offset1
      GIR_AddImm8, /*InsnID*/0, /*Imm*/0,
      GIR_MergeMemOperands, /*InsnID*/0, /*NumInsns*/1, /*MergeInsnID's*/0,
      GIR_ConstrainSelectedInstOperands, /*InsnID*/0,
      GIR_EraseFromParent, /*InsnID*/0,
      // GIR_Coverage, 6681,
      GIR_Done,
    // Label 1199: @79285
    GIM_Try, /*On fail goto*//*Label 1200*/ GIMT_Encode4(79354), // Rule ID 6617 //
      GIM_CheckFeatures, GIMT_Encode2(GIFBS_LDSRequiresM0Init),
      GIM_CheckMemorySizeEqualTo, /*MI*/0, /*MMO*/0, /*Size*/GIMT_Encode4(8),
      GIM_CheckMemoryAddressSpace, /*MI*/0, /*MMO*/0, /*NumAddrSpace*/1, /*AddrSpace*/3,
      GIM_CheckAtomicOrderingOrStrongerThan, /*MI*/0, /*Order*/(uint8_t)AtomicOrdering::Unordered,
      GIM_CheckRegBankForClass, /*MI*/0, /*Op*/0, /*RC*/GIMT_Encode2(AMDGPU::AV_64RegClassID),
      GIM_CheckPointerToAny, /*MI*/0, /*Op*/1, /*SizeInBits*/0,
      GIM_CheckComplexPattern, /*MI*/0, /*Op*/1, /*Renderer*/GIMT_Encode2(0), GIMT_Encode2(GICP_gi_ds_1addr_1offset),
      // (AMDGPUatomic_ld_glue:{ *:[i64] } (DS1Addr1Offset:{ *:[iPTR] } i32:{ *:[i32] }:$ptr, i32:{ *:[i32] }:$offset))<<P:Predicate_atomic_load_64_glue>><<P:Predicate_atomic_load_64_local_m0>>  =>  (DS_READ_B64:{ *:[i64] } ?:{ *:[i32] }:$ptr, offset:{ *:[i32] }:$offset, 0:{ *:[i1] })
      GIR_BuildMI, /*InsnID*/0, /*Opcode*/GIMT_Encode2(AMDGPU::DS_READ_B64),
      GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/0, // DstI[vdst]
      GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/0, // ptr
      GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/1, // offset
      GIR_AddImm8, /*InsnID*/0, /*Imm*/0,
      GIR_MergeMemOperands, /*InsnID*/0, /*NumInsns*/1, /*MergeInsnID's*/0,
      GIR_ConstrainSelectedInstOperands, /*InsnID*/0,
      GIR_EraseFromParent, /*InsnID*/0,
      // GIR_Coverage, 6617,
      GIR_Done,
    // Label 1200: @79354
    GIM_Try, /*On fail goto*//*Label 1201*/ GIMT_Encode4(79423), // Rule ID 6618 //
      GIM_CheckFeatures, GIMT_Encode2(GIFBS_NotLDSRequiresM0Init),
      GIM_CheckMemorySizeEqualTo, /*MI*/0, /*MMO*/0, /*Size*/GIMT_Encode4(8),
      GIM_CheckMemoryAddressSpace, /*MI*/0, /*MMO*/0, /*NumAddrSpace*/1, /*AddrSpace*/3,
      GIM_CheckAtomicOrderingOrStrongerThan, /*MI*/0, /*Order*/(uint8_t)AtomicOrdering::Unordered,
      GIM_CheckRegBankForClass, /*MI*/0, /*Op*/0, /*RC*/GIMT_Encode2(AMDGPU::AV_64RegClassID),
      GIM_CheckPointerToAny, /*MI*/0, /*Op*/1, /*SizeInBits*/0,
      GIM_CheckComplexPattern, /*MI*/0, /*Op*/1, /*Renderer*/GIMT_Encode2(0), GIMT_Encode2(GICP_gi_ds_1addr_1offset),
      // (atomic_load:{ *:[i64] } (DS1Addr1Offset:{ *:[iPTR] } i32:{ *:[i32] }:$ptr, i32:{ *:[i32] }:$offset))<<P:Predicate_atomic_load_64>><<P:Predicate_atomic_load_64_local>>  =>  (DS_READ_B64_gfx9:{ *:[i64] } ?:{ *:[i32] }:$ptr, offset:{ *:[i32] }:$offset, 0:{ *:[i1] })
      GIR_BuildMI, /*InsnID*/0, /*Opcode*/GIMT_Encode2(AMDGPU::DS_READ_B64_gfx9),
      GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/0, // DstI[vdst]
      GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/0, // ptr
      GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/1, // offset
      GIR_AddImm8, /*InsnID*/0, /*Imm*/0,
      GIR_MergeMemOperands, /*InsnID*/0, /*NumInsns*/1, /*MergeInsnID's*/0,
      GIR_ConstrainSelectedInstOperands, /*InsnID*/0,
      GIR_EraseFromParent, /*InsnID*/0,
      // GIR_Coverage, 6618,
      GIR_Done,
    // Label 1201: @79423
    GIM_Try, /*On fail goto*//*Label 1202*/ GIMT_Encode4(79485), // Rule ID 7092 //
      GIM_CheckMemorySizeEqualToLLT, /*MI*/0, /*MMO*/0, /*OpIdx*/0,
      GIM_CheckAtomicOrdering, /*MI*/0, /*Order*/(uint8_t)AtomicOrdering::NotAtomic,
      GIM_CheckRegBankForClass, /*MI*/0, /*Op*/0, /*RC*/GIMT_Encode2(AMDGPU::SReg_64_XEXECRegClassID),
      GIM_CheckPointerToAny, /*MI*/0, /*Op*/1, /*SizeInBits*/0,
      GIM_CheckCxxInsnPredicate, /*MI*/0, /*FnId*/GIMT_Encode2(GICXXPred_MI_Predicate_smrd_load),
      GIM_CheckComplexPattern, /*MI*/0, /*Op*/1, /*Renderer*/GIMT_Encode2(0), GIMT_Encode2(GICP_gi_smrd_imm),
      // (ld:{ *:[i64] } (SMRDImm:{ *:[iPTR] } i64:{ *:[i64] }:$sbase, i32:{ *:[i32] }:$offset))<<P:Predicate_unindexedload>><<P:Predicate_load>><<P:Predicate_smrd_load>>  =>  (S_LOAD_DWORDX2_IMM:{ *:[i64] } ?:{ *:[i64] }:$sbase, ?:{ *:[i32] }:$offset, 0:{ *:[i32] })
      GIR_BuildMI, /*InsnID*/0, /*Opcode*/GIMT_Encode2(AMDGPU::S_LOAD_DWORDX2_IMM),
      GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/0, // DstI[sdst]
      GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/0, // sbase
      GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/1, // offset
      GIR_AddImm8, /*InsnID*/0, /*Imm*/0,
      GIR_MergeMemOperands, /*InsnID*/0, /*NumInsns*/1, /*MergeInsnID's*/0,
      GIR_ConstrainSelectedInstOperands, /*InsnID*/0,
      GIR_EraseFromParent, /*InsnID*/0,
      // GIR_Coverage, 7092,
      GIR_Done,
    // Label 1202: @79485
    GIM_Try, /*On fail goto*//*Label 1203*/ GIMT_Encode4(79550), // Rule ID 7093 //
      GIM_CheckFeatures, GIMT_Encode2(GIFBS_isGFX7Only),
      GIM_CheckMemorySizeEqualToLLT, /*MI*/0, /*MMO*/0, /*OpIdx*/0,
      GIM_CheckAtomicOrdering, /*MI*/0, /*Order*/(uint8_t)AtomicOrdering::NotAtomic,
      GIM_CheckRegBankForClass, /*MI*/0, /*Op*/0, /*RC*/GIMT_Encode2(AMDGPU::SReg_64_XEXECRegClassID),
      GIM_CheckPointerToAny, /*MI*/0, /*Op*/1, /*SizeInBits*/0,
      GIM_CheckCxxInsnPredicate, /*MI*/0, /*FnId*/GIMT_Encode2(GICXXPred_MI_Predicate_smrd_load),
      GIM_CheckComplexPattern, /*MI*/0, /*Op*/1, /*Renderer*/GIMT_Encode2(0), GIMT_Encode2(GICP_gi_smrd_imm32),
      // (ld:{ *:[i64] } (SMRDImm32:{ *:[iPTR] } i64:{ *:[i64] }:$sbase, i32:{ *:[i32] }:$offset))<<P:Predicate_unindexedload>><<P:Predicate_load>><<P:Predicate_smrd_load>>  =>  (S_LOAD_DWORDX2_IMM_ci:{ *:[i64] } ?:{ *:[i64] }:$sbase, ?:{ *:[i32] }:$offset, 0:{ *:[i32] })
      GIR_BuildMI, /*InsnID*/0, /*Opcode*/GIMT_Encode2(AMDGPU::S_LOAD_DWORDX2_IMM_ci),
      GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/0, // DstI[sdst]
      GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/0, // sbase
      GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/1, // offset
      GIR_AddImm8, /*InsnID*/0, /*Imm*/0,
      GIR_MergeMemOperands, /*InsnID*/0, /*NumInsns*/1, /*MergeInsnID's*/0,
      GIR_ConstrainSelectedInstOperands, /*InsnID*/0,
      GIR_EraseFromParent, /*InsnID*/0,
      // GIR_Coverage, 7093,
      GIR_Done,
    // Label 1203: @79550
    GIM_Try, /*On fail goto*//*Label 1204*/ GIMT_Encode4(79615), // Rule ID 7094 //
      GIM_CheckFeatures, GIMT_Encode2(GIFBS_isNotGFX9Plus),
      GIM_CheckMemorySizeEqualToLLT, /*MI*/0, /*MMO*/0, /*OpIdx*/0,
      GIM_CheckAtomicOrdering, /*MI*/0, /*Order*/(uint8_t)AtomicOrdering::NotAtomic,
      GIM_CheckRegBankForClass, /*MI*/0, /*Op*/0, /*RC*/GIMT_Encode2(AMDGPU::SReg_64_XEXECRegClassID),
      GIM_CheckPointerToAny, /*MI*/0, /*Op*/1, /*SizeInBits*/0,
      GIM_CheckCxxInsnPredicate, /*MI*/0, /*FnId*/GIMT_Encode2(GICXXPred_MI_Predicate_smrd_load),
      GIM_CheckComplexPattern, /*MI*/0, /*Op*/1, /*Renderer*/GIMT_Encode2(0), GIMT_Encode2(GICP_gi_smrd_sgpr),
      // (ld:{ *:[i64] } (SMRDSgpr:{ *:[iPTR] } i64:{ *:[i64] }:$sbase, i32:{ *:[i32] }:$soffset))<<P:Predicate_unindexedload>><<P:Predicate_load>><<P:Predicate_smrd_load>>  =>  (S_LOAD_DWORDX2_SGPR:{ *:[i64] } ?:{ *:[i64] }:$sbase, ?:{ *:[i32] }:$soffset, 0:{ *:[i32] })
      GIR_BuildMI, /*InsnID*/0, /*Opcode*/GIMT_Encode2(AMDGPU::S_LOAD_DWORDX2_SGPR),
      GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/0, // DstI[sdst]
      GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/0, // sbase
      GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/1, // soffset
      GIR_AddImm8, /*InsnID*/0, /*Imm*/0,
      GIR_MergeMemOperands, /*InsnID*/0, /*NumInsns*/1, /*MergeInsnID's*/0,
      GIR_ConstrainSelectedInstOperands, /*InsnID*/0,
      GIR_EraseFromParent, /*InsnID*/0,
      // GIR_Coverage, 7094,
      GIR_Done,
    // Label 1204: @79615
    GIM_Try, /*On fail goto*//*Label 1205*/ GIMT_Encode4(79683), // Rule ID 7095 //
      GIM_CheckFeatures, GIMT_Encode2(GIFBS_isGFX9Plus),
      GIM_CheckMemorySizeEqualToLLT, /*MI*/0, /*MMO*/0, /*OpIdx*/0,
      GIM_CheckAtomicOrdering, /*MI*/0, /*Order*/(uint8_t)AtomicOrdering::NotAtomic,
      GIM_CheckRegBankForClass, /*MI*/0, /*Op*/0, /*RC*/GIMT_Encode2(AMDGPU::SReg_64_XEXECRegClassID),
      GIM_CheckPointerToAny, /*MI*/0, /*Op*/1, /*SizeInBits*/0,
      GIM_CheckCxxInsnPredicate, /*MI*/0, /*FnId*/GIMT_Encode2(GICXXPred_MI_Predicate_smrd_load),
      GIM_CheckComplexPattern, /*MI*/0, /*Op*/1, /*Renderer*/GIMT_Encode2(0), GIMT_Encode2(GICP_gi_smrd_sgpr),
      // (ld:{ *:[i64] } (SMRDSgpr:{ *:[iPTR] } i64:{ *:[i64] }:$sbase, i32:{ *:[i32] }:$soffset))<<P:Predicate_unindexedload>><<P:Predicate_load>><<P:Predicate_smrd_load>>  =>  (S_LOAD_DWORDX2_SGPR_IMM:{ *:[i64] } ?:{ *:[i64] }:$sbase, ?:{ *:[i32] }:$soffset, 0:{ *:[i32] }, 0:{ *:[i32] })
      GIR_BuildMI, /*InsnID*/0, /*Opcode*/GIMT_Encode2(AMDGPU::S_LOAD_DWORDX2_SGPR_IMM),
      GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/0, // DstI[sdst]
      GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/0, // sbase
      GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/1, // soffset
      GIR_AddImm8, /*InsnID*/0, /*Imm*/0,
      GIR_AddImm8, /*InsnID*/0, /*Imm*/0,
      GIR_MergeMemOperands, /*InsnID*/0, /*NumInsns*/1, /*MergeInsnID's*/0,
      GIR_ConstrainSelectedInstOperands, /*InsnID*/0,
      GIR_EraseFromParent, /*InsnID*/0,
      // GIR_Coverage, 7095,
      GIR_Done,
    // Label 1205: @79683
    GIM_Try, /*On fail goto*//*Label 1206*/ GIMT_Encode4(79759), // Rule ID 3101 //
      GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasFlatGlobalInsts),
      GIM_CheckMemorySizeEqualTo, /*MI*/0, /*MMO*/0, /*Size*/GIMT_Encode4(8),
      GIM_CheckMemoryAddressSpace, /*MI*/0, /*MMO*/0, /*NumAddrSpace*/3, /*AddrSpace*/1, /*AddrSpace*/4, /*AddrSpace*/6,
      GIM_CheckAtomicOrderingOrStrongerThan, /*MI*/0, /*Order*/(uint8_t)AtomicOrdering::Unordered,
      GIM_CheckRegBankForClass, /*MI*/0, /*Op*/0, /*RC*/GIMT_Encode2(AMDGPU::AV_64RegClassID),
      GIM_CheckPointerToAny, /*MI*/0, /*Op*/1, /*SizeInBits*/0,
      GIM_CheckComplexPattern, /*MI*/0, /*Op*/1, /*Renderer*/GIMT_Encode2(0), GIMT_Encode2(GICP_gi_global_saddr),
      // (atomic_load:{ *:[i64] } (GlobalSAddr:{ *:[iPTR] } SReg_64:{ *:[i64] }:$saddr, VGPR_32:{ *:[i32] }:$voffset, i32:{ *:[i32] }:$offset))<<P:Predicate_atomic_load_64>><<P:Predicate_atomic_load_64_global>>  =>  (GLOBAL_LOAD_DWORDX2_SADDR:{ *:[i64] } ?:{ *:[i64] }:$saddr, ?:{ *:[i32] }:$voffset, ?:{ *:[i32] }:$offset, 0:{ *:[i32] })
      GIR_BuildMI, /*InsnID*/0, /*Opcode*/GIMT_Encode2(AMDGPU::GLOBAL_LOAD_DWORDX2_SADDR),
      GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/0, // DstI[vdst]
      GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/0, // saddr
      GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/1, // voffset
      GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/2, // offset
      GIR_AddImm8, /*InsnID*/0, /*Imm*/0,
      GIR_MergeMemOperands, /*InsnID*/0, /*NumInsns*/1, /*MergeInsnID's*/0,
      GIR_ConstrainSelectedInstOperands, /*InsnID*/0,
      GIR_EraseFromParent, /*InsnID*/0,
      // GIR_Coverage, 3101,
      GIR_Done,
    // Label 1206: @79759
    GIM_Try, /*On fail goto*//*Label 1207*/ GIMT_Encode4(79828), // Rule ID 3029 //
      GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasFlatGlobalInsts),
      GIM_CheckMemoryAddressSpace, /*MI*/0, /*MMO*/0, /*NumAddrSpace*/3, /*AddrSpace*/1, /*AddrSpace*/4, /*AddrSpace*/6,
      GIM_CheckAtomicOrdering, /*MI*/0, /*Order*/(uint8_t)AtomicOrdering::NotAtomic,
      GIM_CheckRegBankForClass, /*MI*/0, /*Op*/0, /*RC*/GIMT_Encode2(AMDGPU::AV_64RegClassID),
      GIM_CheckPointerToAny, /*MI*/0, /*Op*/1, /*SizeInBits*/0,
      GIM_CheckComplexPattern, /*MI*/0, /*Op*/1, /*Renderer*/GIMT_Encode2(0), GIMT_Encode2(GICP_gi_global_saddr),
      // (ld:{ *:[i64] } (GlobalSAddr:{ *:[iPTR] } SReg_64:{ *:[i64] }:$saddr, VGPR_32:{ *:[i32] }:$voffset, i32:{ *:[i32] }:$offset))<<P:Predicate_unindexedload>><<P:Predicate_load_global>>  =>  (GLOBAL_LOAD_DWORDX2_SADDR:{ *:[i64] } ?:{ *:[i64] }:$saddr, ?:{ *:[i32] }:$voffset, ?:{ *:[i32] }:$offset, 0:{ *:[i32] })
      GIR_BuildMI, /*InsnID*/0, /*Opcode*/GIMT_Encode2(AMDGPU::GLOBAL_LOAD_DWORDX2_SADDR),
      GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/0, // DstI[vdst]
      GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/0, // saddr
      GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/1, // voffset
      GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/2, // offset
      GIR_AddImm8, /*InsnID*/0, /*Imm*/0,
      GIR_MergeMemOperands, /*InsnID*/0, /*NumInsns*/1, /*MergeInsnID's*/0,
      GIR_ConstrainSelectedInstOperands, /*InsnID*/0,
      GIR_EraseFromParent, /*InsnID*/0,
      // GIR_Coverage, 3029,
      GIR_Done,
    // Label 1207: @79828
    GIM_Try, /*On fail goto*//*Label 1208*/ GIMT_Encode4(79897), // Rule ID 3033 //
      GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasFlatGlobalInsts),
      GIM_CheckMemoryAddressSpace, /*MI*/0, /*MMO*/0, /*NumAddrSpace*/3, /*AddrSpace*/1, /*AddrSpace*/4, /*AddrSpace*/6,
      GIM_CheckAtomicOrdering, /*MI*/0, /*Order*/(uint8_t)AtomicOrdering::NotAtomic,
      GIM_CheckRegBankForClass, /*MI*/0, /*Op*/0, /*RC*/GIMT_Encode2(AMDGPU::AV_64RegClassID),
      GIM_CheckPointerToAny, /*MI*/0, /*Op*/1, /*SizeInBits*/0,
      GIM_CheckComplexPattern, /*MI*/0, /*Op*/1, /*Renderer*/GIMT_Encode2(0), GIMT_Encode2(GICP_gi_global_saddr),
      // (ld:{ *:[f64] } (GlobalSAddr:{ *:[iPTR] } SReg_64:{ *:[i64] }:$saddr, VGPR_32:{ *:[i32] }:$voffset, i32:{ *:[i32] }:$offset))<<P:Predicate_unindexedload>><<P:Predicate_load_global>>  =>  (GLOBAL_LOAD_DWORDX2_SADDR:{ *:[f64] } ?:{ *:[i64] }:$saddr, ?:{ *:[i32] }:$voffset, ?:{ *:[i32] }:$offset, 0:{ *:[i32] })
      GIR_BuildMI, /*InsnID*/0, /*Opcode*/GIMT_Encode2(AMDGPU::GLOBAL_LOAD_DWORDX2_SADDR),
      GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/0, // DstI[vdst]
      GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/0, // saddr
      GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/1, // voffset
      GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/2, // offset
      GIR_AddImm8, /*InsnID*/0, /*Imm*/0,
      GIR_MergeMemOperands, /*InsnID*/0, /*NumInsns*/1, /*MergeInsnID's*/0,
      GIR_ConstrainSelectedInstOperands, /*InsnID*/0,
      GIR_EraseFromParent, /*InsnID*/0,
      // GIR_Coverage, 3033,
      GIR_Done,
    // Label 1208: @79897
    GIM_Try, /*On fail goto*//*Label 1209*/ GIMT_Encode4(79968), // Rule ID 3100 //
      GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasFlatGlobalInsts),
      GIM_CheckMemorySizeEqualTo, /*MI*/0, /*MMO*/0, /*Size*/GIMT_Encode4(8),
      GIM_CheckMemoryAddressSpace, /*MI*/0, /*MMO*/0, /*NumAddrSpace*/3, /*AddrSpace*/1, /*AddrSpace*/4, /*AddrSpace*/6,
      GIM_CheckAtomicOrderingOrStrongerThan, /*MI*/0, /*Order*/(uint8_t)AtomicOrdering::Unordered,
      GIM_CheckRegBankForClass, /*MI*/0, /*Op*/0, /*RC*/GIMT_Encode2(AMDGPU::AV_64RegClassID),
      GIM_CheckPointerToAny, /*MI*/0, /*Op*/1, /*SizeInBits*/0,
      GIM_CheckComplexPattern, /*MI*/0, /*Op*/1, /*Renderer*/GIMT_Encode2(0), GIMT_Encode2(GICP_gi_global_offset),
      // (atomic_load:{ *:[i64] } (GlobalOffset:{ *:[iPTR] } VReg_64:{ *:[i64] }:$vaddr, i32:{ *:[i32] }:$offset))<<P:Predicate_atomic_load_64>><<P:Predicate_atomic_load_64_global>>  =>  (GLOBAL_LOAD_DWORDX2:{ *:[i64] } ?:{ *:[i64] }:$vaddr, ?:{ *:[i32] }:$offset)
      GIR_BuildMI, /*InsnID*/0, /*Opcode*/GIMT_Encode2(AMDGPU::GLOBAL_LOAD_DWORDX2),
      GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/0, // DstI[vdst]
      GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/0, // vaddr
      GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/1, // offset
      GIR_AddImm8, /*InsnID*/0, /*Imm*/0,
      GIR_MergeMemOperands, /*InsnID*/0, /*NumInsns*/1, /*MergeInsnID's*/0,
      GIR_ConstrainSelectedInstOperands, /*InsnID*/0,
      GIR_EraseFromParent, /*InsnID*/0,
      // GIR_Coverage, 3100,
      GIR_Done,
    // Label 1209: @79968
    GIM_Try, /*On fail goto*//*Label 1210*/ GIMT_Encode4(80032), // Rule ID 3028 //
      GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasFlatGlobalInsts),
      GIM_CheckMemoryAddressSpace, /*MI*/0, /*MMO*/0, /*NumAddrSpace*/3, /*AddrSpace*/1, /*AddrSpace*/4, /*AddrSpace*/6,
      GIM_CheckAtomicOrdering, /*MI*/0, /*Order*/(uint8_t)AtomicOrdering::NotAtomic,
      GIM_CheckRegBankForClass, /*MI*/0, /*Op*/0, /*RC*/GIMT_Encode2(AMDGPU::AV_64RegClassID),
      GIM_CheckPointerToAny, /*MI*/0, /*Op*/1, /*SizeInBits*/0,
      GIM_CheckComplexPattern, /*MI*/0, /*Op*/1, /*Renderer*/GIMT_Encode2(0), GIMT_Encode2(GICP_gi_global_offset),
      // (ld:{ *:[i64] } (GlobalOffset:{ *:[iPTR] } VReg_64:{ *:[i64] }:$vaddr, i32:{ *:[i32] }:$offset))<<P:Predicate_unindexedload>><<P:Predicate_load_global>>  =>  (GLOBAL_LOAD_DWORDX2:{ *:[i64] } ?:{ *:[i64] }:$vaddr, ?:{ *:[i32] }:$offset)
      GIR_BuildMI, /*InsnID*/0, /*Opcode*/GIMT_Encode2(AMDGPU::GLOBAL_LOAD_DWORDX2),
      GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/0, // DstI[vdst]
      GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/0, // vaddr
      GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/1, // offset
      GIR_AddImm8, /*InsnID*/0, /*Imm*/0,
      GIR_MergeMemOperands, /*InsnID*/0, /*NumInsns*/1, /*MergeInsnID's*/0,
      GIR_ConstrainSelectedInstOperands, /*InsnID*/0,
      GIR_EraseFromParent, /*InsnID*/0,
      // GIR_Coverage, 3028,
      GIR_Done,
    // Label 1210: @80032
    GIM_Try, /*On fail goto*//*Label 1211*/ GIMT_Encode4(80096), // Rule ID 3032 //
      GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasFlatGlobalInsts),
      GIM_CheckMemoryAddressSpace, /*MI*/0, /*MMO*/0, /*NumAddrSpace*/3, /*AddrSpace*/1, /*AddrSpace*/4, /*AddrSpace*/6,
      GIM_CheckAtomicOrdering, /*MI*/0, /*Order*/(uint8_t)AtomicOrdering::NotAtomic,
      GIM_CheckRegBankForClass, /*MI*/0, /*Op*/0, /*RC*/GIMT_Encode2(AMDGPU::AV_64RegClassID),
      GIM_CheckPointerToAny, /*MI*/0, /*Op*/1, /*SizeInBits*/0,
      GIM_CheckComplexPattern, /*MI*/0, /*Op*/1, /*Renderer*/GIMT_Encode2(0), GIMT_Encode2(GICP_gi_global_offset),
      // (ld:{ *:[f64] } (GlobalOffset:{ *:[iPTR] } VReg_64:{ *:[i64] }:$vaddr, i32:{ *:[i32] }:$offset))<<P:Predicate_unindexedload>><<P:Predicate_load_global>>  =>  (GLOBAL_LOAD_DWORDX2:{ *:[f64] } ?:{ *:[i64] }:$vaddr, ?:{ *:[i32] }:$offset)
      GIR_BuildMI, /*InsnID*/0, /*Opcode*/GIMT_Encode2(AMDGPU::GLOBAL_LOAD_DWORDX2),
      GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/0, // DstI[vdst]
      GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/0, // vaddr
      GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/1, // offset
      GIR_AddImm8, /*InsnID*/0, /*Imm*/0,
      GIR_MergeMemOperands, /*InsnID*/0, /*NumInsns*/1, /*MergeInsnID's*/0,
      GIR_ConstrainSelectedInstOperands, /*InsnID*/0,
      GIR_EraseFromParent, /*InsnID*/0,
      // GIR_Coverage, 3032,
      GIR_Done,
    // Label 1211: @80096
    GIM_Try, /*On fail goto*//*Label 1212*/ GIMT_Encode4(80153), // Rule ID 7097 //
      GIM_CheckMemorySizeEqualToLLT, /*MI*/0, /*MMO*/0, /*OpIdx*/0,
      GIM_CheckAtomicOrdering, /*MI*/0, /*Order*/(uint8_t)AtomicOrdering::NotAtomic,
      GIM_CheckRegBankForClass, /*MI*/0, /*Op*/0, /*RC*/GIMT_Encode2(AMDGPU::SReg_64_XEXECRegClassID),
      // MIs[0] sbase
      GIM_CheckPointerToAny, /*MI*/0, /*Op*/1, /*SizeInBits*/64,
      GIM_CheckRegBankForClass, /*MI*/0, /*Op*/1, /*RC*/GIMT_Encode2(AMDGPU::SReg_64RegClassID),
      GIM_CheckCxxInsnPredicate, /*MI*/0, /*FnId*/GIMT_Encode2(GICXXPred_MI_Predicate_smrd_load),
      // (ld:{ *:[i64] } SReg_64:{ *:[i64] }:$sbase)<<P:Predicate_unindexedload>><<P:Predicate_load>><<P:Predicate_smrd_load>>  =>  (S_LOAD_DWORDX2_IMM:{ *:[i64] } i64:{ *:[i64] }:$sbase, 0:{ *:[i32] }, 0:{ *:[i32] })
      GIR_BuildMI, /*InsnID*/0, /*Opcode*/GIMT_Encode2(AMDGPU::S_LOAD_DWORDX2_IMM),
      GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/0, // DstI[sdst]
      GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/1, // sbase
      GIR_AddImm8, /*InsnID*/0, /*Imm*/0,
      GIR_AddImm8, /*InsnID*/0, /*Imm*/0,
      GIR_MergeMemOperands, /*InsnID*/0, /*NumInsns*/1, /*MergeInsnID's*/0,
      GIR_ConstrainSelectedInstOperands, /*InsnID*/0,
      GIR_EraseFromParent, /*InsnID*/0,
      // GIR_Coverage, 7097,
      GIR_Done,
    // Label 1212: @80153
    GIM_Try, /*On fail goto*//*Label 1213*/ GIMT_Encode4(80225), // Rule ID 2767 //
      GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasFlatAddressSpace),
      GIM_CheckMemorySizeEqualTo, /*MI*/0, /*MMO*/0, /*Size*/GIMT_Encode4(8),
      GIM_CheckMemoryAddressSpace, /*MI*/0, /*MMO*/0, /*NumAddrSpace*/4, /*AddrSpace*/0, /*AddrSpace*/1, /*AddrSpace*/4, /*AddrSpace*/6,
      GIM_CheckAtomicOrderingOrStrongerThan, /*MI*/0, /*Order*/(uint8_t)AtomicOrdering::Unordered,
      GIM_CheckRegBankForClass, /*MI*/0, /*Op*/0, /*RC*/GIMT_Encode2(AMDGPU::AV_64RegClassID),
      GIM_CheckPointerToAny, /*MI*/0, /*Op*/1, /*SizeInBits*/0,
      GIM_CheckComplexPattern, /*MI*/0, /*Op*/1, /*Renderer*/GIMT_Encode2(0), GIMT_Encode2(GICP_gi_flat_offset),
      // (atomic_load:{ *:[i64] } (FlatOffset:{ *:[iPTR] } i64:{ *:[i64] }:$vaddr, i32:{ *:[i32] }:$offset))<<P:Predicate_atomic_load_64>><<P:Predicate_atomic_load_64_flat>>  =>  (FLAT_LOAD_DWORDX2:{ *:[i64] } ?:{ *:[i64] }:$vaddr, ?:{ *:[i32] }:$offset)
      GIR_BuildMI, /*InsnID*/0, /*Opcode*/GIMT_Encode2(AMDGPU::FLAT_LOAD_DWORDX2),
      GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/0, // DstI[vdst]
      GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/0, // vaddr
      GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/1, // offset
      GIR_AddImm8, /*InsnID*/0, /*Imm*/0,
      GIR_MergeMemOperands, /*InsnID*/0, /*NumInsns*/1, /*MergeInsnID's*/0,
      GIR_ConstrainSelectedInstOperands, /*InsnID*/0,
      GIR_EraseFromParent, /*InsnID*/0,
      // GIR_Coverage, 2767,
      GIR_Done,
    // Label 1213: @80225
    GIM_Try, /*On fail goto*//*Label 1214*/ GIMT_Encode4(80290), // Rule ID 2789 //
      GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasFlatAddressSpace),
      GIM_CheckMemoryAddressSpace, /*MI*/0, /*MMO*/0, /*NumAddrSpace*/4, /*AddrSpace*/0, /*AddrSpace*/1, /*AddrSpace*/4, /*AddrSpace*/6,
      GIM_CheckAtomicOrdering, /*MI*/0, /*Order*/(uint8_t)AtomicOrdering::NotAtomic,
      GIM_CheckRegBankForClass, /*MI*/0, /*Op*/0, /*RC*/GIMT_Encode2(AMDGPU::AV_64RegClassID),
      GIM_CheckPointerToAny, /*MI*/0, /*Op*/1, /*SizeInBits*/0,
      GIM_CheckComplexPattern, /*MI*/0, /*Op*/1, /*Renderer*/GIMT_Encode2(0), GIMT_Encode2(GICP_gi_flat_offset),
      // (ld:{ *:[i64] } (FlatOffset:{ *:[iPTR] } i64:{ *:[i64] }:$vaddr, i32:{ *:[i32] }:$offset))<<P:Predicate_unindexedload>><<P:Predicate_load_flat>>  =>  (FLAT_LOAD_DWORDX2:{ *:[i64] } ?:{ *:[i64] }:$vaddr, ?:{ *:[i32] }:$offset)
      GIR_BuildMI, /*InsnID*/0, /*Opcode*/GIMT_Encode2(AMDGPU::FLAT_LOAD_DWORDX2),
      GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/0, // DstI[vdst]
      GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/0, // vaddr
      GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/1, // offset
      GIR_AddImm8, /*InsnID*/0, /*Imm*/0,
      GIR_MergeMemOperands, /*InsnID*/0, /*NumInsns*/1, /*MergeInsnID's*/0,
      GIR_ConstrainSelectedInstOperands, /*InsnID*/0,
      GIR_EraseFromParent, /*InsnID*/0,
      // GIR_Coverage, 2789,
      GIR_Done,
    // Label 1214: @80290
    GIM_Try, /*On fail goto*//*Label 1215*/ GIMT_Encode4(80355), // Rule ID 2791 //
      GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasFlatAddressSpace),
      GIM_CheckMemoryAddressSpace, /*MI*/0, /*MMO*/0, /*NumAddrSpace*/4, /*AddrSpace*/0, /*AddrSpace*/1, /*AddrSpace*/4, /*AddrSpace*/6,
      GIM_CheckAtomicOrdering, /*MI*/0, /*Order*/(uint8_t)AtomicOrdering::NotAtomic,
      GIM_CheckRegBankForClass, /*MI*/0, /*Op*/0, /*RC*/GIMT_Encode2(AMDGPU::AV_64RegClassID),
      GIM_CheckPointerToAny, /*MI*/0, /*Op*/1, /*SizeInBits*/0,
      GIM_CheckComplexPattern, /*MI*/0, /*Op*/1, /*Renderer*/GIMT_Encode2(0), GIMT_Encode2(GICP_gi_flat_offset),
      // (ld:{ *:[f64] } (FlatOffset:{ *:[iPTR] } i64:{ *:[i64] }:$vaddr, i32:{ *:[i32] }:$offset))<<P:Predicate_unindexedload>><<P:Predicate_load_flat>>  =>  (FLAT_LOAD_DWORDX2:{ *:[f64] } ?:{ *:[i64] }:$vaddr, ?:{ *:[i32] }:$offset)
      GIR_BuildMI, /*InsnID*/0, /*Opcode*/GIMT_Encode2(AMDGPU::FLAT_LOAD_DWORDX2),
      GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/0, // DstI[vdst]
      GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/0, // vaddr
      GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/1, // offset
      GIR_AddImm8, /*InsnID*/0, /*Imm*/0,
      GIR_MergeMemOperands, /*InsnID*/0, /*NumInsns*/1, /*MergeInsnID's*/0,
      GIR_ConstrainSelectedInstOperands, /*InsnID*/0,
      GIR_EraseFromParent, /*InsnID*/0,
      // GIR_Coverage, 2791,
      GIR_Done,
    // Label 1215: @80355
    GIM_Reject,
    // Label 827: @80356
    GIM_Try, /*On fail goto*//*Label 1216*/ GIMT_Encode4(80426), // Rule ID 2462 //
      GIM_CheckFeatures, GIMT_Encode2(GIFBS_isGFX9Plus),
      GIM_CheckMemorySizeEqualToLLT, /*MI*/0, /*MMO*/0, /*OpIdx*/0,
      GIM_CheckAtomicOrdering, /*MI*/0, /*Order*/(uint8_t)AtomicOrdering::NotAtomic,
      GIM_CheckRegBankForClass, /*MI*/0, /*Op*/0, /*RC*/GIMT_Encode2(AMDGPU::SReg_32_XM0_XEXECRegClassID),
      GIM_CheckPointerToAny, /*MI*/0, /*Op*/1, /*SizeInBits*/0,
      GIM_CheckCxxInsnPredicate, /*MI*/0, /*FnId*/GIMT_Encode2(GICXXPred_MI_Predicate_smrd_load),
      GIM_CheckComplexPattern, /*MI*/0, /*Op*/1, /*Renderer*/GIMT_Encode2(0), GIMT_Encode2(GICP_gi_smrd_sgpr_imm),
      // (ld:{ *:[v2i16] } (SMRDSgprImm:{ *:[iPTR] } i64:{ *:[i64] }:$sbase, i32:{ *:[i32] }:$soffset, i32:{ *:[i32] }:$offset))<<P:Predicate_unindexedload>><<P:Predicate_load>><<P:Predicate_smrd_load>>  =>  (S_LOAD_DWORD_SGPR_IMM:{ *:[v2i16] } ?:{ *:[i64] }:$sbase, ?:{ *:[i32] }:$soffset, ?:{ *:[i32] }:$offset, 0:{ *:[i32] })
      GIR_BuildMI, /*InsnID*/0, /*Opcode*/GIMT_Encode2(AMDGPU::S_LOAD_DWORD_SGPR_IMM),
      GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/0, // DstI[sdst]
      GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/0, // sbase
      GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/1, // soffset
      GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/2, // offset
      GIR_AddImm8, /*InsnID*/0, /*Imm*/0,
      GIR_MergeMemOperands, /*InsnID*/0, /*NumInsns*/1, /*MergeInsnID's*/0,
      GIR_ConstrainSelectedInstOperands, /*InsnID*/0,
      GIR_EraseFromParent, /*InsnID*/0,
      // GIR_Coverage, 2462,
      GIR_Done,
    // Label 1216: @80426
    GIM_Try, /*On fail goto*//*Label 1217*/ GIMT_Encode4(80496), // Rule ID 2468 //
      GIM_CheckFeatures, GIMT_Encode2(GIFBS_isGFX9Plus),
      GIM_CheckMemorySizeEqualToLLT, /*MI*/0, /*MMO*/0, /*OpIdx*/0,
      GIM_CheckAtomicOrdering, /*MI*/0, /*Order*/(uint8_t)AtomicOrdering::NotAtomic,
      GIM_CheckRegBankForClass, /*MI*/0, /*Op*/0, /*RC*/GIMT_Encode2(AMDGPU::SReg_32_XM0_XEXECRegClassID),
      GIM_CheckPointerToAny, /*MI*/0, /*Op*/1, /*SizeInBits*/0,
      GIM_CheckCxxInsnPredicate, /*MI*/0, /*FnId*/GIMT_Encode2(GICXXPred_MI_Predicate_smrd_load),
      GIM_CheckComplexPattern, /*MI*/0, /*Op*/1, /*Renderer*/GIMT_Encode2(0), GIMT_Encode2(GICP_gi_smrd_sgpr_imm),
      // (ld:{ *:[v2f16] } (SMRDSgprImm:{ *:[iPTR] } i64:{ *:[i64] }:$sbase, i32:{ *:[i32] }:$soffset, i32:{ *:[i32] }:$offset))<<P:Predicate_unindexedload>><<P:Predicate_load>><<P:Predicate_smrd_load>>  =>  (S_LOAD_DWORD_SGPR_IMM:{ *:[v2f16] } ?:{ *:[i64] }:$sbase, ?:{ *:[i32] }:$soffset, ?:{ *:[i32] }:$offset, 0:{ *:[i32] })
      GIR_BuildMI, /*InsnID*/0, /*Opcode*/GIMT_Encode2(AMDGPU::S_LOAD_DWORD_SGPR_IMM),
      GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/0, // DstI[sdst]
      GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/0, // sbase
      GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/1, // soffset
      GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/2, // offset
      GIR_AddImm8, /*InsnID*/0, /*Imm*/0,
      GIR_MergeMemOperands, /*InsnID*/0, /*NumInsns*/1, /*MergeInsnID's*/0,
      GIR_ConstrainSelectedInstOperands, /*InsnID*/0,
      GIR_EraseFromParent, /*InsnID*/0,
      // GIR_Coverage, 2468,
      GIR_Done,
    // Label 1217: @80496
    GIM_Try, /*On fail goto*//*Label 1218*/ GIMT_Encode4(80566), // Rule ID 2474 //
      GIM_CheckFeatures, GIMT_Encode2(GIFBS_isGFX9Plus),
      GIM_CheckMemorySizeEqualToLLT, /*MI*/0, /*MMO*/0, /*OpIdx*/0,
      GIM_CheckAtomicOrdering, /*MI*/0, /*Order*/(uint8_t)AtomicOrdering::NotAtomic,
      GIM_CheckRegBankForClass, /*MI*/0, /*Op*/0, /*RC*/GIMT_Encode2(AMDGPU::SReg_32_XM0_XEXECRegClassID),
      GIM_CheckPointerToAny, /*MI*/0, /*Op*/1, /*SizeInBits*/0,
      GIM_CheckCxxInsnPredicate, /*MI*/0, /*FnId*/GIMT_Encode2(GICXXPred_MI_Predicate_smrd_load),
      GIM_CheckComplexPattern, /*MI*/0, /*Op*/1, /*Renderer*/GIMT_Encode2(0), GIMT_Encode2(GICP_gi_smrd_sgpr_imm),
      // (ld:{ *:[v2bf16] } (SMRDSgprImm:{ *:[iPTR] } i64:{ *:[i64] }:$sbase, i32:{ *:[i32] }:$soffset, i32:{ *:[i32] }:$offset))<<P:Predicate_unindexedload>><<P:Predicate_load>><<P:Predicate_smrd_load>>  =>  (S_LOAD_DWORD_SGPR_IMM:{ *:[v2bf16] } ?:{ *:[i64] }:$sbase, ?:{ *:[i32] }:$soffset, ?:{ *:[i32] }:$offset, 0:{ *:[i32] })
      GIR_BuildMI, /*InsnID*/0, /*Opcode*/GIMT_Encode2(AMDGPU::S_LOAD_DWORD_SGPR_IMM),
      GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/0, // DstI[sdst]
      GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/0, // sbase
      GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/1, // soffset
      GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/2, // offset
      GIR_AddImm8, /*InsnID*/0, /*Imm*/0,
      GIR_MergeMemOperands, /*InsnID*/0, /*NumInsns*/1, /*MergeInsnID's*/0,
      GIR_ConstrainSelectedInstOperands, /*InsnID*/0,
      GIR_EraseFromParent, /*InsnID*/0,
      // GIR_Coverage, 2474,
      GIR_Done,
    // Label 1218: @80566
    GIM_Try, /*On fail goto*//*Label 1219*/ GIMT_Encode4(80628), // Rule ID 2458 //
      GIM_CheckMemorySizeEqualToLLT, /*MI*/0, /*MMO*/0, /*OpIdx*/0,
      GIM_CheckAtomicOrdering, /*MI*/0, /*Order*/(uint8_t)AtomicOrdering::NotAtomic,
      GIM_CheckRegBankForClass, /*MI*/0, /*Op*/0, /*RC*/GIMT_Encode2(AMDGPU::SReg_32_XM0_XEXECRegClassID),
      GIM_CheckPointerToAny, /*MI*/0, /*Op*/1, /*SizeInBits*/0,
      GIM_CheckCxxInsnPredicate, /*MI*/0, /*FnId*/GIMT_Encode2(GICXXPred_MI_Predicate_smrd_load),
      GIM_CheckComplexPattern, /*MI*/0, /*Op*/1, /*Renderer*/GIMT_Encode2(0), GIMT_Encode2(GICP_gi_smrd_imm),
      // (ld:{ *:[v2i16] } (SMRDImm:{ *:[iPTR] } i64:{ *:[i64] }:$sbase, i32:{ *:[i32] }:$offset))<<P:Predicate_unindexedload>><<P:Predicate_load>><<P:Predicate_smrd_load>>  =>  (S_LOAD_DWORD_IMM:{ *:[v2i16] } ?:{ *:[i64] }:$sbase, ?:{ *:[i32] }:$offset, 0:{ *:[i32] })
      GIR_BuildMI, /*InsnID*/0, /*Opcode*/GIMT_Encode2(AMDGPU::S_LOAD_DWORD_IMM),
      GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/0, // DstI[sdst]
      GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/0, // sbase
      GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/1, // offset
      GIR_AddImm8, /*InsnID*/0, /*Imm*/0,
      GIR_MergeMemOperands, /*InsnID*/0, /*NumInsns*/1, /*MergeInsnID's*/0,
      GIR_ConstrainSelectedInstOperands, /*InsnID*/0,
      GIR_EraseFromParent, /*InsnID*/0,
      // GIR_Coverage, 2458,
      GIR_Done,
    // Label 1219: @80628
    GIM_Try, /*On fail goto*//*Label 1220*/ GIMT_Encode4(80693), // Rule ID 2459 //
      GIM_CheckFeatures, GIMT_Encode2(GIFBS_isGFX7Only),
      GIM_CheckMemorySizeEqualToLLT, /*MI*/0, /*MMO*/0, /*OpIdx*/0,
      GIM_CheckAtomicOrdering, /*MI*/0, /*Order*/(uint8_t)AtomicOrdering::NotAtomic,
      GIM_CheckRegBankForClass, /*MI*/0, /*Op*/0, /*RC*/GIMT_Encode2(AMDGPU::SReg_32_XM0_XEXECRegClassID),
      GIM_CheckPointerToAny, /*MI*/0, /*Op*/1, /*SizeInBits*/0,
      GIM_CheckCxxInsnPredicate, /*MI*/0, /*FnId*/GIMT_Encode2(GICXXPred_MI_Predicate_smrd_load),
      GIM_CheckComplexPattern, /*MI*/0, /*Op*/1, /*Renderer*/GIMT_Encode2(0), GIMT_Encode2(GICP_gi_smrd_imm32),
      // (ld:{ *:[v2i16] } (SMRDImm32:{ *:[iPTR] } i64:{ *:[i64] }:$sbase, i32:{ *:[i32] }:$offset))<<P:Predicate_unindexedload>><<P:Predicate_load>><<P:Predicate_smrd_load>>  =>  (S_LOAD_DWORD_IMM_ci:{ *:[v2i16] } ?:{ *:[i64] }:$sbase, ?:{ *:[i32] }:$offset, 0:{ *:[i32] })
      GIR_BuildMI, /*InsnID*/0, /*Opcode*/GIMT_Encode2(AMDGPU::S_LOAD_DWORD_IMM_ci),
      GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/0, // DstI[sdst]
      GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/0, // sbase
      GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/1, // offset
      GIR_AddImm8, /*InsnID*/0, /*Imm*/0,
      GIR_MergeMemOperands, /*InsnID*/0, /*NumInsns*/1, /*MergeInsnID's*/0,
      GIR_ConstrainSelectedInstOperands, /*InsnID*/0,
      GIR_EraseFromParent, /*InsnID*/0,
      // GIR_Coverage, 2459,
      GIR_Done,
    // Label 1220: @80693
    GIM_Try, /*On fail goto*//*Label 1221*/ GIMT_Encode4(80758), // Rule ID 2460 //
      GIM_CheckFeatures, GIMT_Encode2(GIFBS_isNotGFX9Plus),
      GIM_CheckMemorySizeEqualToLLT, /*MI*/0, /*MMO*/0, /*OpIdx*/0,
      GIM_CheckAtomicOrdering, /*MI*/0, /*Order*/(uint8_t)AtomicOrdering::NotAtomic,
      GIM_CheckRegBankForClass, /*MI*/0, /*Op*/0, /*RC*/GIMT_Encode2(AMDGPU::SReg_32_XM0_XEXECRegClassID),
      GIM_CheckPointerToAny, /*MI*/0, /*Op*/1, /*SizeInBits*/0,
      GIM_CheckCxxInsnPredicate, /*MI*/0, /*FnId*/GIMT_Encode2(GICXXPred_MI_Predicate_smrd_load),
      GIM_CheckComplexPattern, /*MI*/0, /*Op*/1, /*Renderer*/GIMT_Encode2(0), GIMT_Encode2(GICP_gi_smrd_sgpr),
      // (ld:{ *:[v2i16] } (SMRDSgpr:{ *:[iPTR] } i64:{ *:[i64] }:$sbase, i32:{ *:[i32] }:$soffset))<<P:Predicate_unindexedload>><<P:Predicate_load>><<P:Predicate_smrd_load>>  =>  (S_LOAD_DWORD_SGPR:{ *:[v2i16] } ?:{ *:[i64] }:$sbase, ?:{ *:[i32] }:$soffset, 0:{ *:[i32] })
      GIR_BuildMI, /*InsnID*/0, /*Opcode*/GIMT_Encode2(AMDGPU::S_LOAD_DWORD_SGPR),
      GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/0, // DstI[sdst]
      GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/0, // sbase
      GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/1, // soffset
      GIR_AddImm8, /*InsnID*/0, /*Imm*/0,
      GIR_MergeMemOperands, /*InsnID*/0, /*NumInsns*/1, /*MergeInsnID's*/0,
      GIR_ConstrainSelectedInstOperands, /*InsnID*/0,
      GIR_EraseFromParent, /*InsnID*/0,
      // GIR_Coverage, 2460,
      GIR_Done,
    // Label 1221: @80758
    GIM_Try, /*On fail goto*//*Label 1222*/ GIMT_Encode4(80826), // Rule ID 2461 //
      GIM_CheckFeatures, GIMT_Encode2(GIFBS_isGFX9Plus),
      GIM_CheckMemorySizeEqualToLLT, /*MI*/0, /*MMO*/0, /*OpIdx*/0,
      GIM_CheckAtomicOrdering, /*MI*/0, /*Order*/(uint8_t)AtomicOrdering::NotAtomic,
      GIM_CheckRegBankForClass, /*MI*/0, /*Op*/0, /*RC*/GIMT_Encode2(AMDGPU::SReg_32_XM0_XEXECRegClassID),
      GIM_CheckPointerToAny, /*MI*/0, /*Op*/1, /*SizeInBits*/0,
      GIM_CheckCxxInsnPredicate, /*MI*/0, /*FnId*/GIMT_Encode2(GICXXPred_MI_Predicate_smrd_load),
      GIM_CheckComplexPattern, /*MI*/0, /*Op*/1, /*Renderer*/GIMT_Encode2(0), GIMT_Encode2(GICP_gi_smrd_sgpr),
      // (ld:{ *:[v2i16] } (SMRDSgpr:{ *:[iPTR] } i64:{ *:[i64] }:$sbase, i32:{ *:[i32] }:$soffset))<<P:Predicate_unindexedload>><<P:Predicate_load>><<P:Predicate_smrd_load>>  =>  (S_LOAD_DWORD_SGPR_IMM:{ *:[v2i16] } ?:{ *:[i64] }:$sbase, ?:{ *:[i32] }:$soffset, 0:{ *:[i32] }, 0:{ *:[i32] })
      GIR_BuildMI, /*InsnID*/0, /*Opcode*/GIMT_Encode2(AMDGPU::S_LOAD_DWORD_SGPR_IMM),
      GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/0, // DstI[sdst]
      GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/0, // sbase
      GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/1, // soffset
      GIR_AddImm8, /*InsnID*/0, /*Imm*/0,
      GIR_AddImm8, /*InsnID*/0, /*Imm*/0,
      GIR_MergeMemOperands, /*InsnID*/0, /*NumInsns*/1, /*MergeInsnID's*/0,
      GIR_ConstrainSelectedInstOperands, /*InsnID*/0,
      GIR_EraseFromParent, /*InsnID*/0,
      // GIR_Coverage, 2461,
      GIR_Done,
    // Label 1222: @80826
    GIM_Try, /*On fail goto*//*Label 1223*/ GIMT_Encode4(80888), // Rule ID 2464 //
      GIM_CheckMemorySizeEqualToLLT, /*MI*/0, /*MMO*/0, /*OpIdx*/0,
      GIM_CheckAtomicOrdering, /*MI*/0, /*Order*/(uint8_t)AtomicOrdering::NotAtomic,
      GIM_CheckRegBankForClass, /*MI*/0, /*Op*/0, /*RC*/GIMT_Encode2(AMDGPU::SReg_32_XM0_XEXECRegClassID),
      GIM_CheckPointerToAny, /*MI*/0, /*Op*/1, /*SizeInBits*/0,
      GIM_CheckCxxInsnPredicate, /*MI*/0, /*FnId*/GIMT_Encode2(GICXXPred_MI_Predicate_smrd_load),
      GIM_CheckComplexPattern, /*MI*/0, /*Op*/1, /*Renderer*/GIMT_Encode2(0), GIMT_Encode2(GICP_gi_smrd_imm),
      // (ld:{ *:[v2f16] } (SMRDImm:{ *:[iPTR] } i64:{ *:[i64] }:$sbase, i32:{ *:[i32] }:$offset))<<P:Predicate_unindexedload>><<P:Predicate_load>><<P:Predicate_smrd_load>>  =>  (S_LOAD_DWORD_IMM:{ *:[v2f16] } ?:{ *:[i64] }:$sbase, ?:{ *:[i32] }:$offset, 0:{ *:[i32] })
      GIR_BuildMI, /*InsnID*/0, /*Opcode*/GIMT_Encode2(AMDGPU::S_LOAD_DWORD_IMM),
      GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/0, // DstI[sdst]
      GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/0, // sbase
      GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/1, // offset
      GIR_AddImm8, /*InsnID*/0, /*Imm*/0,
      GIR_MergeMemOperands, /*InsnID*/0, /*NumInsns*/1, /*MergeInsnID's*/0,
      GIR_ConstrainSelectedInstOperands, /*InsnID*/0,
      GIR_EraseFromParent, /*InsnID*/0,
      // GIR_Coverage, 2464,
      GIR_Done,
    // Label 1223: @80888
    GIM_Try, /*On fail goto*//*Label 1224*/ GIMT_Encode4(80953), // Rule ID 2465 //
      GIM_CheckFeatures, GIMT_Encode2(GIFBS_isGFX7Only),
      GIM_CheckMemorySizeEqualToLLT, /*MI*/0, /*MMO*/0, /*OpIdx*/0,
      GIM_CheckAtomicOrdering, /*MI*/0, /*Order*/(uint8_t)AtomicOrdering::NotAtomic,
      GIM_CheckRegBankForClass, /*MI*/0, /*Op*/0, /*RC*/GIMT_Encode2(AMDGPU::SReg_32_XM0_XEXECRegClassID),
      GIM_CheckPointerToAny, /*MI*/0, /*Op*/1, /*SizeInBits*/0,
      GIM_CheckCxxInsnPredicate, /*MI*/0, /*FnId*/GIMT_Encode2(GICXXPred_MI_Predicate_smrd_load),
      GIM_CheckComplexPattern, /*MI*/0, /*Op*/1, /*Renderer*/GIMT_Encode2(0), GIMT_Encode2(GICP_gi_smrd_imm32),
      // (ld:{ *:[v2f16] } (SMRDImm32:{ *:[iPTR] } i64:{ *:[i64] }:$sbase, i32:{ *:[i32] }:$offset))<<P:Predicate_unindexedload>><<P:Predicate_load>><<P:Predicate_smrd_load>>  =>  (S_LOAD_DWORD_IMM_ci:{ *:[v2f16] } ?:{ *:[i64] }:$sbase, ?:{ *:[i32] }:$offset, 0:{ *:[i32] })
      GIR_BuildMI, /*InsnID*/0, /*Opcode*/GIMT_Encode2(AMDGPU::S_LOAD_DWORD_IMM_ci),
      GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/0, // DstI[sdst]
      GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/0, // sbase
      GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/1, // offset
      GIR_AddImm8, /*InsnID*/0, /*Imm*/0,
      GIR_MergeMemOperands, /*InsnID*/0, /*NumInsns*/1, /*MergeInsnID's*/0,
      GIR_ConstrainSelectedInstOperands, /*InsnID*/0,
      GIR_EraseFromParent, /*InsnID*/0,
      // GIR_Coverage, 2465,
      GIR_Done,
    // Label 1224: @80953
    GIM_Try, /*On fail goto*//*Label 1225*/ GIMT_Encode4(81018), // Rule ID 2466 //
      GIM_CheckFeatures, GIMT_Encode2(GIFBS_isNotGFX9Plus),
      GIM_CheckMemorySizeEqualToLLT, /*MI*/0, /*MMO*/0, /*OpIdx*/0,
      GIM_CheckAtomicOrdering, /*MI*/0, /*Order*/(uint8_t)AtomicOrdering::NotAtomic,
      GIM_CheckRegBankForClass, /*MI*/0, /*Op*/0, /*RC*/GIMT_Encode2(AMDGPU::SReg_32_XM0_XEXECRegClassID),
      GIM_CheckPointerToAny, /*MI*/0, /*Op*/1, /*SizeInBits*/0,
      GIM_CheckCxxInsnPredicate, /*MI*/0, /*FnId*/GIMT_Encode2(GICXXPred_MI_Predicate_smrd_load),
      GIM_CheckComplexPattern, /*MI*/0, /*Op*/1, /*Renderer*/GIMT_Encode2(0), GIMT_Encode2(GICP_gi_smrd_sgpr),
      // (ld:{ *:[v2f16] } (SMRDSgpr:{ *:[iPTR] } i64:{ *:[i64] }:$sbase, i32:{ *:[i32] }:$soffset))<<P:Predicate_unindexedload>><<P:Predicate_load>><<P:Predicate_smrd_load>>  =>  (S_LOAD_DWORD_SGPR:{ *:[v2f16] } ?:{ *:[i64] }:$sbase, ?:{ *:[i32] }:$soffset, 0:{ *:[i32] })
      GIR_BuildMI, /*InsnID*/0, /*Opcode*/GIMT_Encode2(AMDGPU::S_LOAD_DWORD_SGPR),
      GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/0, // DstI[sdst]
      GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/0, // sbase
      GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/1, // soffset
      GIR_AddImm8, /*InsnID*/0, /*Imm*/0,
      GIR_MergeMemOperands, /*InsnID*/0, /*NumInsns*/1, /*MergeInsnID's*/0,
      GIR_ConstrainSelectedInstOperands, /*InsnID*/0,
      GIR_EraseFromParent, /*InsnID*/0,
      // GIR_Coverage, 2466,
      GIR_Done,
    // Label 1225: @81018
    GIM_Try, /*On fail goto*//*Label 1226*/ GIMT_Encode4(81086), // Rule ID 2467 //
      GIM_CheckFeatures, GIMT_Encode2(GIFBS_isGFX9Plus),
      GIM_CheckMemorySizeEqualToLLT, /*MI*/0, /*MMO*/0, /*OpIdx*/0,
      GIM_CheckAtomicOrdering, /*MI*/0, /*Order*/(uint8_t)AtomicOrdering::NotAtomic,
      GIM_CheckRegBankForClass, /*MI*/0, /*Op*/0, /*RC*/GIMT_Encode2(AMDGPU::SReg_32_XM0_XEXECRegClassID),
      GIM_CheckPointerToAny, /*MI*/0, /*Op*/1, /*SizeInBits*/0,
      GIM_CheckCxxInsnPredicate, /*MI*/0, /*FnId*/GIMT_Encode2(GICXXPred_MI_Predicate_smrd_load),
      GIM_CheckComplexPattern, /*MI*/0, /*Op*/1, /*Renderer*/GIMT_Encode2(0), GIMT_Encode2(GICP_gi_smrd_sgpr),
      // (ld:{ *:[v2f16] } (SMRDSgpr:{ *:[iPTR] } i64:{ *:[i64] }:$sbase, i32:{ *:[i32] }:$soffset))<<P:Predicate_unindexedload>><<P:Predicate_load>><<P:Predicate_smrd_load>>  =>  (S_LOAD_DWORD_SGPR_IMM:{ *:[v2f16] } ?:{ *:[i64] }:$sbase, ?:{ *:[i32] }:$soffset, 0:{ *:[i32] }, 0:{ *:[i32] })
      GIR_BuildMI, /*InsnID*/0, /*Opcode*/GIMT_Encode2(AMDGPU::S_LOAD_DWORD_SGPR_IMM),
      GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/0, // DstI[sdst]
      GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/0, // sbase
      GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/1, // soffset
      GIR_AddImm8, /*InsnID*/0, /*Imm*/0,
      GIR_AddImm8, /*InsnID*/0, /*Imm*/0,
      GIR_MergeMemOperands, /*InsnID*/0, /*NumInsns*/1, /*MergeInsnID's*/0,
      GIR_ConstrainSelectedInstOperands, /*InsnID*/0,
      GIR_EraseFromParent, /*InsnID*/0,
      // GIR_Coverage, 2467,
      GIR_Done,
    // Label 1226: @81086
    GIM_Try, /*On fail goto*//*Label 1227*/ GIMT_Encode4(81148), // Rule ID 2470 //
      GIM_CheckMemorySizeEqualToLLT, /*MI*/0, /*MMO*/0, /*OpIdx*/0,
      GIM_CheckAtomicOrdering, /*MI*/0, /*Order*/(uint8_t)AtomicOrdering::NotAtomic,
      GIM_CheckRegBankForClass, /*MI*/0, /*Op*/0, /*RC*/GIMT_Encode2(AMDGPU::SReg_32_XM0_XEXECRegClassID),
      GIM_CheckPointerToAny, /*MI*/0, /*Op*/1, /*SizeInBits*/0,
      GIM_CheckCxxInsnPredicate, /*MI*/0, /*FnId*/GIMT_Encode2(GICXXPred_MI_Predicate_smrd_load),
      GIM_CheckComplexPattern, /*MI*/0, /*Op*/1, /*Renderer*/GIMT_Encode2(0), GIMT_Encode2(GICP_gi_smrd_imm),
      // (ld:{ *:[v2bf16] } (SMRDImm:{ *:[iPTR] } i64:{ *:[i64] }:$sbase, i32:{ *:[i32] }:$offset))<<P:Predicate_unindexedload>><<P:Predicate_load>><<P:Predicate_smrd_load>>  =>  (S_LOAD_DWORD_IMM:{ *:[v2bf16] } ?:{ *:[i64] }:$sbase, ?:{ *:[i32] }:$offset, 0:{ *:[i32] })
      GIR_BuildMI, /*InsnID*/0, /*Opcode*/GIMT_Encode2(AMDGPU::S_LOAD_DWORD_IMM),
      GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/0, // DstI[sdst]
      GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/0, // sbase
      GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/1, // offset
      GIR_AddImm8, /*InsnID*/0, /*Imm*/0,
      GIR_MergeMemOperands, /*InsnID*/0, /*NumInsns*/1, /*MergeInsnID's*/0,
      GIR_ConstrainSelectedInstOperands, /*InsnID*/0,
      GIR_EraseFromParent, /*InsnID*/0,
      // GIR_Coverage, 2470,
      GIR_Done,
    // Label 1227: @81148
    GIM_Try, /*On fail goto*//*Label 1228*/ GIMT_Encode4(81213), // Rule ID 2471 //
      GIM_CheckFeatures, GIMT_Encode2(GIFBS_isGFX7Only),
      GIM_CheckMemorySizeEqualToLLT, /*MI*/0, /*MMO*/0, /*OpIdx*/0,
      GIM_CheckAtomicOrdering, /*MI*/0, /*Order*/(uint8_t)AtomicOrdering::NotAtomic,
      GIM_CheckRegBankForClass, /*MI*/0, /*Op*/0, /*RC*/GIMT_Encode2(AMDGPU::SReg_32_XM0_XEXECRegClassID),
      GIM_CheckPointerToAny, /*MI*/0, /*Op*/1, /*SizeInBits*/0,
      GIM_CheckCxxInsnPredicate, /*MI*/0, /*FnId*/GIMT_Encode2(GICXXPred_MI_Predicate_smrd_load),
      GIM_CheckComplexPattern, /*MI*/0, /*Op*/1, /*Renderer*/GIMT_Encode2(0), GIMT_Encode2(GICP_gi_smrd_imm32),
      // (ld:{ *:[v2bf16] } (SMRDImm32:{ *:[iPTR] } i64:{ *:[i64] }:$sbase, i32:{ *:[i32] }:$offset))<<P:Predicate_unindexedload>><<P:Predicate_load>><<P:Predicate_smrd_load>>  =>  (S_LOAD_DWORD_IMM_ci:{ *:[v2bf16] } ?:{ *:[i64] }:$sbase, ?:{ *:[i32] }:$offset, 0:{ *:[i32] })
      GIR_BuildMI, /*InsnID*/0, /*Opcode*/GIMT_Encode2(AMDGPU::S_LOAD_DWORD_IMM_ci),
      GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/0, // DstI[sdst]
      GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/0, // sbase
      GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/1, // offset
      GIR_AddImm8, /*InsnID*/0, /*Imm*/0,
      GIR_MergeMemOperands, /*InsnID*/0, /*NumInsns*/1, /*MergeInsnID's*/0,
      GIR_ConstrainSelectedInstOperands, /*InsnID*/0,
      GIR_EraseFromParent, /*InsnID*/0,
      // GIR_Coverage, 2471,
      GIR_Done,
    // Label 1228: @81213
    GIM_Try, /*On fail goto*//*Label 1229*/ GIMT_Encode4(81278), // Rule ID 2472 //
      GIM_CheckFeatures, GIMT_Encode2(GIFBS_isNotGFX9Plus),
      GIM_CheckMemorySizeEqualToLLT, /*MI*/0, /*MMO*/0, /*OpIdx*/0,
      GIM_CheckAtomicOrdering, /*MI*/0, /*Order*/(uint8_t)AtomicOrdering::NotAtomic,
      GIM_CheckRegBankForClass, /*MI*/0, /*Op*/0, /*RC*/GIMT_Encode2(AMDGPU::SReg_32_XM0_XEXECRegClassID),
      GIM_CheckPointerToAny, /*MI*/0, /*Op*/1, /*SizeInBits*/0,
      GIM_CheckCxxInsnPredicate, /*MI*/0, /*FnId*/GIMT_Encode2(GICXXPred_MI_Predicate_smrd_load),
      GIM_CheckComplexPattern, /*MI*/0, /*Op*/1, /*Renderer*/GIMT_Encode2(0), GIMT_Encode2(GICP_gi_smrd_sgpr),
      // (ld:{ *:[v2bf16] } (SMRDSgpr:{ *:[iPTR] } i64:{ *:[i64] }:$sbase, i32:{ *:[i32] }:$soffset))<<P:Predicate_unindexedload>><<P:Predicate_load>><<P:Predicate_smrd_load>>  =>  (S_LOAD_DWORD_SGPR:{ *:[v2bf16] } ?:{ *:[i64] }:$sbase, ?:{ *:[i32] }:$soffset, 0:{ *:[i32] })
      GIR_BuildMI, /*InsnID*/0, /*Opcode*/GIMT_Encode2(AMDGPU::S_LOAD_DWORD_SGPR),
      GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/0, // DstI[sdst]
      GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/0, // sbase
      GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/1, // soffset
      GIR_AddImm8, /*InsnID*/0, /*Imm*/0,
      GIR_MergeMemOperands, /*InsnID*/0, /*NumInsns*/1, /*MergeInsnID's*/0,
      GIR_ConstrainSelectedInstOperands, /*InsnID*/0,
      GIR_EraseFromParent, /*InsnID*/0,
      // GIR_Coverage, 2472,
      GIR_Done,
    // Label 1229: @81278
    GIM_Try, /*On fail goto*//*Label 1230*/ GIMT_Encode4(81346), // Rule ID 2473 //
      GIM_CheckFeatures, GIMT_Encode2(GIFBS_isGFX9Plus),
      GIM_CheckMemorySizeEqualToLLT, /*MI*/0, /*MMO*/0, /*OpIdx*/0,
      GIM_CheckAtomicOrdering, /*MI*/0, /*Order*/(uint8_t)AtomicOrdering::NotAtomic,
      GIM_CheckRegBankForClass, /*MI*/0, /*Op*/0, /*RC*/GIMT_Encode2(AMDGPU::SReg_32_XM0_XEXECRegClassID),
      GIM_CheckPointerToAny, /*MI*/0, /*Op*/1, /*SizeInBits*/0,
      GIM_CheckCxxInsnPredicate, /*MI*/0, /*FnId*/GIMT_Encode2(GICXXPred_MI_Predicate_smrd_load),
      GIM_CheckComplexPattern, /*MI*/0, /*Op*/1, /*Renderer*/GIMT_Encode2(0), GIMT_Encode2(GICP_gi_smrd_sgpr),
      // (ld:{ *:[v2bf16] } (SMRDSgpr:{ *:[iPTR] } i64:{ *:[i64] }:$sbase, i32:{ *:[i32] }:$soffset))<<P:Predicate_unindexedload>><<P:Predicate_load>><<P:Predicate_smrd_load>>  =>  (S_LOAD_DWORD_SGPR_IMM:{ *:[v2bf16] } ?:{ *:[i64] }:$sbase, ?:{ *:[i32] }:$soffset, 0:{ *:[i32] }, 0:{ *:[i32] })
      GIR_BuildMI, /*InsnID*/0, /*Opcode*/GIMT_Encode2(AMDGPU::S_LOAD_DWORD_SGPR_IMM),
      GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/0, // DstI[sdst]
      GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/0, // sbase
      GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/1, // soffset
      GIR_AddImm8, /*InsnID*/0, /*Imm*/0,
      GIR_AddImm8, /*InsnID*/0, /*Imm*/0,
      GIR_MergeMemOperands, /*InsnID*/0, /*NumInsns*/1, /*MergeInsnID's*/0,
      GIR_ConstrainSelectedInstOperands, /*InsnID*/0,
      GIR_EraseFromParent, /*InsnID*/0,
      // GIR_Coverage, 2473,
      GIR_Done,
    // Label 1230: @81346
    GIM_Try, /*On fail goto*//*Label 1231*/ GIMT_Encode4(81403), // Rule ID 2463 //
      GIM_CheckMemorySizeEqualToLLT, /*MI*/0, /*MMO*/0, /*OpIdx*/0,
      GIM_CheckAtomicOrdering, /*MI*/0, /*Order*/(uint8_t)AtomicOrdering::NotAtomic,
      GIM_CheckRegBankForClass, /*MI*/0, /*Op*/0, /*RC*/GIMT_Encode2(AMDGPU::SReg_32_XM0_XEXECRegClassID),
      // MIs[0] sbase
      GIM_CheckPointerToAny, /*MI*/0, /*Op*/1, /*SizeInBits*/64,
      GIM_CheckRegBankForClass, /*MI*/0, /*Op*/1, /*RC*/GIMT_Encode2(AMDGPU::SReg_64RegClassID),
      GIM_CheckCxxInsnPredicate, /*MI*/0, /*FnId*/GIMT_Encode2(GICXXPred_MI_Predicate_smrd_load),
      // (ld:{ *:[v2i16] } SReg_64:{ *:[i64] }:$sbase)<<P:Predicate_unindexedload>><<P:Predicate_load>><<P:Predicate_smrd_load>>  =>  (S_LOAD_DWORD_IMM:{ *:[v2i16] } i64:{ *:[i64] }:$sbase, 0:{ *:[i32] }, 0:{ *:[i32] })
      GIR_BuildMI, /*InsnID*/0, /*Opcode*/GIMT_Encode2(AMDGPU::S_LOAD_DWORD_IMM),
      GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/0, // DstI[sdst]
      GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/1, // sbase
      GIR_AddImm8, /*InsnID*/0, /*Imm*/0,
      GIR_AddImm8, /*InsnID*/0, /*Imm*/0,
      GIR_MergeMemOperands, /*InsnID*/0, /*NumInsns*/1, /*MergeInsnID's*/0,
      GIR_ConstrainSelectedInstOperands, /*InsnID*/0,
      GIR_EraseFromParent, /*InsnID*/0,
      // GIR_Coverage, 2463,
      GIR_Done,
    // Label 1231: @81403
    GIM_Try, /*On fail goto*//*Label 1232*/ GIMT_Encode4(81460), // Rule ID 2469 //
      GIM_CheckMemorySizeEqualToLLT, /*MI*/0, /*MMO*/0, /*OpIdx*/0,
      GIM_CheckAtomicOrdering, /*MI*/0, /*Order*/(uint8_t)AtomicOrdering::NotAtomic,
      GIM_CheckRegBankForClass, /*MI*/0, /*Op*/0, /*RC*/GIMT_Encode2(AMDGPU::SReg_32_XM0_XEXECRegClassID),
      // MIs[0] sbase
      GIM_CheckPointerToAny, /*MI*/0, /*Op*/1, /*SizeInBits*/64,
      GIM_CheckRegBankForClass, /*MI*/0, /*Op*/1, /*RC*/GIMT_Encode2(AMDGPU::SReg_64RegClassID),
      GIM_CheckCxxInsnPredicate, /*MI*/0, /*FnId*/GIMT_Encode2(GICXXPred_MI_Predicate_smrd_load),
      // (ld:{ *:[v2f16] } SReg_64:{ *:[i64] }:$sbase)<<P:Predicate_unindexedload>><<P:Predicate_load>><<P:Predicate_smrd_load>>  =>  (S_LOAD_DWORD_IMM:{ *:[v2f16] } i64:{ *:[i64] }:$sbase, 0:{ *:[i32] }, 0:{ *:[i32] })
      GIR_BuildMI, /*InsnID*/0, /*Opcode*/GIMT_Encode2(AMDGPU::S_LOAD_DWORD_IMM),
      GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/0, // DstI[sdst]
      GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/1, // sbase
      GIR_AddImm8, /*InsnID*/0, /*Imm*/0,
      GIR_AddImm8, /*InsnID*/0, /*Imm*/0,
      GIR_MergeMemOperands, /*InsnID*/0, /*NumInsns*/1, /*MergeInsnID's*/0,
      GIR_ConstrainSelectedInstOperands, /*InsnID*/0,
      GIR_EraseFromParent, /*InsnID*/0,
      // GIR_Coverage, 2469,
      GIR_Done,
    // Label 1232: @81460
    GIM_Try, /*On fail goto*//*Label 1233*/ GIMT_Encode4(81517), // Rule ID 2475 //
      GIM_CheckMemorySizeEqualToLLT, /*MI*/0, /*MMO*/0, /*OpIdx*/0,
      GIM_CheckAtomicOrdering, /*MI*/0, /*Order*/(uint8_t)AtomicOrdering::NotAtomic,
      GIM_CheckRegBankForClass, /*MI*/0, /*Op*/0, /*RC*/GIMT_Encode2(AMDGPU::SReg_32_XM0_XEXECRegClassID),
      // MIs[0] sbase
      GIM_CheckPointerToAny, /*MI*/0, /*Op*/1, /*SizeInBits*/64,
      GIM_CheckRegBankForClass, /*MI*/0, /*Op*/1, /*RC*/GIMT_Encode2(AMDGPU::SReg_64RegClassID),
      GIM_CheckCxxInsnPredicate, /*MI*/0, /*FnId*/GIMT_Encode2(GICXXPred_MI_Predicate_smrd_load),
      // (ld:{ *:[v2bf16] } SReg_64:{ *:[i64] }:$sbase)<<P:Predicate_unindexedload>><<P:Predicate_load>><<P:Predicate_smrd_load>>  =>  (S_LOAD_DWORD_IMM:{ *:[v2bf16] } i64:{ *:[i64] }:$sbase, 0:{ *:[i32] }, 0:{ *:[i32] })
      GIR_BuildMI, /*InsnID*/0, /*Opcode*/GIMT_Encode2(AMDGPU::S_LOAD_DWORD_IMM),
      GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/0, // DstI[sdst]
      GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/1, // sbase
      GIR_AddImm8, /*InsnID*/0, /*Imm*/0,
      GIR_AddImm8, /*InsnID*/0, /*Imm*/0,
      GIR_MergeMemOperands, /*InsnID*/0, /*NumInsns*/1, /*MergeInsnID's*/0,
      GIR_ConstrainSelectedInstOperands, /*InsnID*/0,
      GIR_EraseFromParent, /*InsnID*/0,
      // GIR_Coverage, 2475,
      GIR_Done,
    // Label 1233: @81517
    GIM_Try, /*On fail goto*//*Label 1234*/ GIMT_Encode4(81587), // Rule ID 5396 //
      GIM_CheckFeatures, GIMT_Encode2(GIFBS_DisableFlatScratch_HasUnrestrictedSOffset),
      GIM_CheckMemoryAddressSpace, /*MI*/0, /*MMO*/0, /*NumAddrSpace*/1, /*AddrSpace*/5,
      GIM_CheckAtomicOrdering, /*MI*/0, /*Order*/(uint8_t)AtomicOrdering::NotAtomic,
      GIM_CheckRegBankForClass, /*MI*/0, /*Op*/0, /*RC*/GIMT_Encode2(AMDGPU::AV_32RegClassID),
      GIM_CheckPointerToAny, /*MI*/0, /*Op*/1, /*SizeInBits*/0,
      GIM_CheckComplexPattern, /*MI*/0, /*Op*/1, /*Renderer*/GIMT_Encode2(0), GIMT_Encode2(GICP_gi_mubuf_scratch_offset),
      // (ld:{ *:[v2i16] } (MUBUFScratchOffset:{ *:[iPTR] } v4i32:{ *:[v4i32] }:$srsrc, i32:{ *:[i32] }:$soffset, i32:{ *:[i32] }:$offset))<<P:Predicate_unindexedload>><<P:Predicate_load_private>>  =>  (BUFFER_LOAD_DWORD_OFFSET:{ *:[v2i16] } ?:{ *:[v4i32] }:$srsrc, ?:{ *:[i32] }:$soffset, ?:{ *:[i32] }:$offset, 0:{ *:[i32] }, 0:{ *:[i1] })
      GIR_BuildMI, /*InsnID*/0, /*Opcode*/GIMT_Encode2(AMDGPU::BUFFER_LOAD_DWORD_OFFSET),
      GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/0, // DstI[vdata]
      GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/0, // srsrc
      GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/1, // soffset
      GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/2, // offset
      GIR_AddImm8, /*InsnID*/0, /*Imm*/0,
      GIR_AddImm8, /*InsnID*/0, /*Imm*/0,
      GIR_MergeMemOperands, /*InsnID*/0, /*NumInsns*/1, /*MergeInsnID's*/0,
      GIR_ConstrainSelectedInstOperands, /*InsnID*/0,
      GIR_EraseFromParent, /*InsnID*/0,
      // GIR_Coverage, 5396,
      GIR_Done,
    // Label 1234: @81587
    GIM_Try, /*On fail goto*//*Label 1235*/ GIMT_Encode4(81657), // Rule ID 5398 //
      GIM_CheckFeatures, GIMT_Encode2(GIFBS_DisableFlatScratch),
      GIM_CheckMemoryAddressSpace, /*MI*/0, /*MMO*/0, /*NumAddrSpace*/1, /*AddrSpace*/5,
      GIM_CheckAtomicOrdering, /*MI*/0, /*Order*/(uint8_t)AtomicOrdering::NotAtomic,
      GIM_CheckRegBankForClass, /*MI*/0, /*Op*/0, /*RC*/GIMT_Encode2(AMDGPU::AV_32RegClassID),
      GIM_CheckPointerToAny, /*MI*/0, /*Op*/1, /*SizeInBits*/0,
      GIM_CheckComplexPattern, /*MI*/0, /*Op*/1, /*Renderer*/GIMT_Encode2(0), GIMT_Encode2(GICP_gi_mubuf_scratch_offset),
      // (ld:{ *:[v2i16] } (MUBUFScratchOffset:{ *:[iPTR] } v4i32:{ *:[v4i32] }:$srsrc, i32:{ *:[i32] }:$soffset, i32:{ *:[i32] }:$offset))<<P:Predicate_unindexedload>><<P:Predicate_load_private>>  =>  (BUFFER_LOAD_DWORD_VBUFFER_OFFSET:{ *:[v2i16] } ?:{ *:[v4i32] }:$srsrc, ?:{ *:[i32] }:$soffset, ?:{ *:[i32] }:$offset, 0:{ *:[i32] }, 0:{ *:[i1] })
      GIR_BuildMI, /*InsnID*/0, /*Opcode*/GIMT_Encode2(AMDGPU::BUFFER_LOAD_DWORD_VBUFFER_OFFSET),
      GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/0, // DstI[vdata]
      GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/0, // srsrc
      GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/1, // soffset
      GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/2, // offset
      GIR_AddImm8, /*InsnID*/0, /*Imm*/0,
      GIR_AddImm8, /*InsnID*/0, /*Imm*/0,
      GIR_MergeMemOperands, /*InsnID*/0, /*NumInsns*/1, /*MergeInsnID's*/0,
      GIR_ConstrainSelectedInstOperands, /*InsnID*/0,
      GIR_EraseFromParent, /*InsnID*/0,
      // GIR_Coverage, 5398,
      GIR_Done,
    // Label 1235: @81657
    GIM_Try, /*On fail goto*//*Label 1236*/ GIMT_Encode4(81727), // Rule ID 5400 //
      GIM_CheckFeatures, GIMT_Encode2(GIFBS_DisableFlatScratch_HasUnrestrictedSOffset),
      GIM_CheckMemoryAddressSpace, /*MI*/0, /*MMO*/0, /*NumAddrSpace*/1, /*AddrSpace*/5,
      GIM_CheckAtomicOrdering, /*MI*/0, /*Order*/(uint8_t)AtomicOrdering::NotAtomic,
      GIM_CheckRegBankForClass, /*MI*/0, /*Op*/0, /*RC*/GIMT_Encode2(AMDGPU::AV_32RegClassID),
      GIM_CheckPointerToAny, /*MI*/0, /*Op*/1, /*SizeInBits*/0,
      GIM_CheckComplexPattern, /*MI*/0, /*Op*/1, /*Renderer*/GIMT_Encode2(0), GIMT_Encode2(GICP_gi_mubuf_scratch_offset),
      // (ld:{ *:[v2f16] } (MUBUFScratchOffset:{ *:[iPTR] } v4i32:{ *:[v4i32] }:$srsrc, i32:{ *:[i32] }:$soffset, i32:{ *:[i32] }:$offset))<<P:Predicate_unindexedload>><<P:Predicate_load_private>>  =>  (BUFFER_LOAD_DWORD_OFFSET:{ *:[v2f16] } ?:{ *:[v4i32] }:$srsrc, ?:{ *:[i32] }:$soffset, ?:{ *:[i32] }:$offset, 0:{ *:[i32] }, 0:{ *:[i1] })
      GIR_BuildMI, /*InsnID*/0, /*Opcode*/GIMT_Encode2(AMDGPU::BUFFER_LOAD_DWORD_OFFSET),
      GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/0, // DstI[vdata]
      GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/0, // srsrc
      GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/1, // soffset
      GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/2, // offset
      GIR_AddImm8, /*InsnID*/0, /*Imm*/0,
      GIR_AddImm8, /*InsnID*/0, /*Imm*/0,
      GIR_MergeMemOperands, /*InsnID*/0, /*NumInsns*/1, /*MergeInsnID's*/0,
      GIR_ConstrainSelectedInstOperands, /*InsnID*/0,
      GIR_EraseFromParent, /*InsnID*/0,
      // GIR_Coverage, 5400,
      GIR_Done,
    // Label 1236: @81727
    GIM_Try, /*On fail goto*//*Label 1237*/ GIMT_Encode4(81797), // Rule ID 5402 //
      GIM_CheckFeatures, GIMT_Encode2(GIFBS_DisableFlatScratch),
      GIM_CheckMemoryAddressSpace, /*MI*/0, /*MMO*/0, /*NumAddrSpace*/1, /*AddrSpace*/5,
      GIM_CheckAtomicOrdering, /*MI*/0, /*Order*/(uint8_t)AtomicOrdering::NotAtomic,
      GIM_CheckRegBankForClass, /*MI*/0, /*Op*/0, /*RC*/GIMT_Encode2(AMDGPU::AV_32RegClassID),
      GIM_CheckPointerToAny, /*MI*/0, /*Op*/1, /*SizeInBits*/0,
      GIM_CheckComplexPattern, /*MI*/0, /*Op*/1, /*Renderer*/GIMT_Encode2(0), GIMT_Encode2(GICP_gi_mubuf_scratch_offset),
      // (ld:{ *:[v2f16] } (MUBUFScratchOffset:{ *:[iPTR] } v4i32:{ *:[v4i32] }:$srsrc, i32:{ *:[i32] }:$soffset, i32:{ *:[i32] }:$offset))<<P:Predicate_unindexedload>><<P:Predicate_load_private>>  =>  (BUFFER_LOAD_DWORD_VBUFFER_OFFSET:{ *:[v2f16] } ?:{ *:[v4i32] }:$srsrc, ?:{ *:[i32] }:$soffset, ?:{ *:[i32] }:$offset, 0:{ *:[i32] }, 0:{ *:[i1] })
      GIR_BuildMI, /*InsnID*/0, /*Opcode*/GIMT_Encode2(AMDGPU::BUFFER_LOAD_DWORD_VBUFFER_OFFSET),
      GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/0, // DstI[vdata]
      GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/0, // srsrc
      GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/1, // soffset
      GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/2, // offset
      GIR_AddImm8, /*InsnID*/0, /*Imm*/0,
      GIR_AddImm8, /*InsnID*/0, /*Imm*/0,
      GIR_MergeMemOperands, /*InsnID*/0, /*NumInsns*/1, /*MergeInsnID's*/0,
      GIR_ConstrainSelectedInstOperands, /*InsnID*/0,
      GIR_EraseFromParent, /*InsnID*/0,
      // GIR_Coverage, 5402,
      GIR_Done,
    // Label 1237: @81797
    GIM_Try, /*On fail goto*//*Label 1238*/ GIMT_Encode4(81867), // Rule ID 5404 //
      GIM_CheckFeatures, GIMT_Encode2(GIFBS_DisableFlatScratch_HasUnrestrictedSOffset),
      GIM_CheckMemoryAddressSpace, /*MI*/0, /*MMO*/0, /*NumAddrSpace*/1, /*AddrSpace*/5,
      GIM_CheckAtomicOrdering, /*MI*/0, /*Order*/(uint8_t)AtomicOrdering::NotAtomic,
      GIM_CheckRegBankForClass, /*MI*/0, /*Op*/0, /*RC*/GIMT_Encode2(AMDGPU::AV_32RegClassID),
      GIM_CheckPointerToAny, /*MI*/0, /*Op*/1, /*SizeInBits*/0,
      GIM_CheckComplexPattern, /*MI*/0, /*Op*/1, /*Renderer*/GIMT_Encode2(0), GIMT_Encode2(GICP_gi_mubuf_scratch_offset),
      // (ld:{ *:[v2bf16] } (MUBUFScratchOffset:{ *:[iPTR] } v4i32:{ *:[v4i32] }:$srsrc, i32:{ *:[i32] }:$soffset, i32:{ *:[i32] }:$offset))<<P:Predicate_unindexedload>><<P:Predicate_load_private>>  =>  (BUFFER_LOAD_DWORD_OFFSET:{ *:[v2bf16] } ?:{ *:[v4i32] }:$srsrc, ?:{ *:[i32] }:$soffset, ?:{ *:[i32] }:$offset, 0:{ *:[i32] }, 0:{ *:[i1] })
      GIR_BuildMI, /*InsnID*/0, /*Opcode*/GIMT_Encode2(AMDGPU::BUFFER_LOAD_DWORD_OFFSET),
      GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/0, // DstI[vdata]
      GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/0, // srsrc
      GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/1, // soffset
      GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/2, // offset
      GIR_AddImm8, /*InsnID*/0, /*Imm*/0,
      GIR_AddImm8, /*InsnID*/0, /*Imm*/0,
      GIR_MergeMemOperands, /*InsnID*/0, /*NumInsns*/1, /*MergeInsnID's*/0,
      GIR_ConstrainSelectedInstOperands, /*InsnID*/0,
      GIR_EraseFromParent, /*InsnID*/0,
      // GIR_Coverage, 5404,
      GIR_Done,
    // Label 1238: @81867
    GIM_Try, /*On fail goto*//*Label 1239*/ GIMT_Encode4(81937), // Rule ID 5406 //
      GIM_CheckFeatures, GIMT_Encode2(GIFBS_DisableFlatScratch),
      GIM_CheckMemoryAddressSpace, /*MI*/0, /*MMO*/0, /*NumAddrSpace*/1, /*AddrSpace*/5,
      GIM_CheckAtomicOrdering, /*MI*/0, /*Order*/(uint8_t)AtomicOrdering::NotAtomic,
      GIM_CheckRegBankForClass, /*MI*/0, /*Op*/0, /*RC*/GIMT_Encode2(AMDGPU::AV_32RegClassID),
      GIM_CheckPointerToAny, /*MI*/0, /*Op*/1, /*SizeInBits*/0,
      GIM_CheckComplexPattern, /*MI*/0, /*Op*/1, /*Renderer*/GIMT_Encode2(0), GIMT_Encode2(GICP_gi_mubuf_scratch_offset),
      // (ld:{ *:[v2bf16] } (MUBUFScratchOffset:{ *:[iPTR] } v4i32:{ *:[v4i32] }:$srsrc, i32:{ *:[i32] }:$soffset, i32:{ *:[i32] }:$offset))<<P:Predicate_unindexedload>><<P:Predicate_load_private>>  =>  (BUFFER_LOAD_DWORD_VBUFFER_OFFSET:{ *:[v2bf16] } ?:{ *:[v4i32] }:$srsrc, ?:{ *:[i32] }:$soffset, ?:{ *:[i32] }:$offset, 0:{ *:[i32] }, 0:{ *:[i1] })
      GIR_BuildMI, /*InsnID*/0, /*Opcode*/GIMT_Encode2(AMDGPU::BUFFER_LOAD_DWORD_VBUFFER_OFFSET),
      GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/0, // DstI[vdata]
      GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/0, // srsrc
      GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/1, // soffset
      GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/2, // offset
      GIR_AddImm8, /*InsnID*/0, /*Imm*/0,
      GIR_AddImm8, /*InsnID*/0, /*Imm*/0,
      GIR_MergeMemOperands, /*InsnID*/0, /*NumInsns*/1, /*MergeInsnID's*/0,
      GIR_ConstrainSelectedInstOperands, /*InsnID*/0,
      GIR_EraseFromParent, /*InsnID*/0,
      // GIR_Coverage, 5406,
      GIR_Done,
    // Label 1239: @81937
    GIM_Try, /*On fail goto*//*Label 1240*/ GIMT_Encode4(82004), // Rule ID 3442 //
      GIM_CheckFeatures, GIMT_Encode2(GIFBS_EnableFlatScratch_HasFlatScratchInsts_HasFlatScratchSVSMode),
      GIM_CheckMemoryAddressSpace, /*MI*/0, /*MMO*/0, /*NumAddrSpace*/1, /*AddrSpace*/5,
      GIM_CheckAtomicOrdering, /*MI*/0, /*Order*/(uint8_t)AtomicOrdering::NotAtomic,
      GIM_CheckRegBankForClass, /*MI*/0, /*Op*/0, /*RC*/GIMT_Encode2(AMDGPU::AV_32RegClassID),
      GIM_CheckPointerToAny, /*MI*/0, /*Op*/1, /*SizeInBits*/0,
      GIM_CheckComplexPattern, /*MI*/0, /*Op*/1, /*Renderer*/GIMT_Encode2(0), GIMT_Encode2(GICP_gi_flat_scratch_svaddr),
      // (ld:{ *:[v2i16] } (ScratchSVAddr:{ *:[iPTR] } VGPR_32:{ *:[i32] }:$vaddr, SGPR_32:{ *:[i32] }:$saddr, i32:{ *:[i32] }:$offset))<<P:Predicate_unindexedload>><<P:Predicate_load_private>>  =>  (SCRATCH_LOAD_DWORD_SVS:{ *:[v2i16] } ?:{ *:[i32] }:$vaddr, ?:{ *:[i32] }:$saddr, ?:{ *:[i32] }:$offset, 0:{ *:[i32] })
      GIR_BuildMI, /*InsnID*/0, /*Opcode*/GIMT_Encode2(AMDGPU::SCRATCH_LOAD_DWORD_SVS),
      GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/0, // DstI[vdst]
      GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/0, // vaddr
      GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/1, // saddr
      GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/2, // offset
      GIR_AddImm8, /*InsnID*/0, /*Imm*/0,
      GIR_MergeMemOperands, /*InsnID*/0, /*NumInsns*/1, /*MergeInsnID's*/0,
      GIR_ConstrainSelectedInstOperands, /*InsnID*/0,
      GIR_EraseFromParent, /*InsnID*/0,
      // GIR_Coverage, 3442,
      GIR_Done,
    // Label 1240: @82004
    GIM_Try, /*On fail goto*//*Label 1241*/ GIMT_Encode4(82071), // Rule ID 3448 //
      GIM_CheckFeatures, GIMT_Encode2(GIFBS_EnableFlatScratch_HasFlatScratchInsts_HasFlatScratchSVSMode),
      GIM_CheckMemoryAddressSpace, /*MI*/0, /*MMO*/0, /*NumAddrSpace*/1, /*AddrSpace*/5,
      GIM_CheckAtomicOrdering, /*MI*/0, /*Order*/(uint8_t)AtomicOrdering::NotAtomic,
      GIM_CheckRegBankForClass, /*MI*/0, /*Op*/0, /*RC*/GIMT_Encode2(AMDGPU::AV_32RegClassID),
      GIM_CheckPointerToAny, /*MI*/0, /*Op*/1, /*SizeInBits*/0,
      GIM_CheckComplexPattern, /*MI*/0, /*Op*/1, /*Renderer*/GIMT_Encode2(0), GIMT_Encode2(GICP_gi_flat_scratch_svaddr),
      // (ld:{ *:[v2f16] } (ScratchSVAddr:{ *:[iPTR] } VGPR_32:{ *:[i32] }:$vaddr, SGPR_32:{ *:[i32] }:$saddr, i32:{ *:[i32] }:$offset))<<P:Predicate_unindexedload>><<P:Predicate_load_private>>  =>  (SCRATCH_LOAD_DWORD_SVS:{ *:[v2f16] } ?:{ *:[i32] }:$vaddr, ?:{ *:[i32] }:$saddr, ?:{ *:[i32] }:$offset, 0:{ *:[i32] })
      GIR_BuildMI, /*InsnID*/0, /*Opcode*/GIMT_Encode2(AMDGPU::SCRATCH_LOAD_DWORD_SVS),
      GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/0, // DstI[vdst]
      GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/0, // vaddr
      GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/1, // saddr
      GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/2, // offset
      GIR_AddImm8, /*InsnID*/0, /*Imm*/0,
      GIR_MergeMemOperands, /*InsnID*/0, /*NumInsns*/1, /*MergeInsnID's*/0,
      GIR_ConstrainSelectedInstOperands, /*InsnID*/0,
      GIR_EraseFromParent, /*InsnID*/0,
      // GIR_Coverage, 3448,
      GIR_Done,
    // Label 1241: @82071
    GIM_Try, /*On fail goto*//*Label 1242*/ GIMT_Encode4(82138), // Rule ID 3454 //
      GIM_CheckFeatures, GIMT_Encode2(GIFBS_EnableFlatScratch_HasFlatScratchInsts_HasFlatScratchSVSMode),
      GIM_CheckMemoryAddressSpace, /*MI*/0, /*MMO*/0, /*NumAddrSpace*/1, /*AddrSpace*/5,
      GIM_CheckAtomicOrdering, /*MI*/0, /*Order*/(uint8_t)AtomicOrdering::NotAtomic,
      GIM_CheckRegBankForClass, /*MI*/0, /*Op*/0, /*RC*/GIMT_Encode2(AMDGPU::AV_32RegClassID),
      GIM_CheckPointerToAny, /*MI*/0, /*Op*/1, /*SizeInBits*/0,
      GIM_CheckComplexPattern, /*MI*/0, /*Op*/1, /*Renderer*/GIMT_Encode2(0), GIMT_Encode2(GICP_gi_flat_scratch_svaddr),
      // (ld:{ *:[v2bf16] } (ScratchSVAddr:{ *:[iPTR] } VGPR_32:{ *:[i32] }:$vaddr, SGPR_32:{ *:[i32] }:$saddr, i32:{ *:[i32] }:$offset))<<P:Predicate_unindexedload>><<P:Predicate_load_private>>  =>  (SCRATCH_LOAD_DWORD_SVS:{ *:[v2bf16] } ?:{ *:[i32] }:$vaddr, ?:{ *:[i32] }:$saddr, ?:{ *:[i32] }:$offset, 0:{ *:[i32] })
      GIR_BuildMI, /*InsnID*/0, /*Opcode*/GIMT_Encode2(AMDGPU::SCRATCH_LOAD_DWORD_SVS),
      GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/0, // DstI[vdst]
      GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/0, // vaddr
      GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/1, // saddr
      GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/2, // offset
      GIR_AddImm8, /*InsnID*/0, /*Imm*/0,
      GIR_MergeMemOperands, /*InsnID*/0, /*NumInsns*/1, /*MergeInsnID's*/0,
      GIR_ConstrainSelectedInstOperands, /*InsnID*/0,
      GIR_EraseFromParent, /*InsnID*/0,
      // GIR_Coverage, 3454,
      GIR_Done,
    // Label 1242: @82138
    GIM_Try, /*On fail goto*//*Label 1243*/ GIMT_Encode4(82200), // Rule ID 3441 //
      GIM_CheckFeatures, GIMT_Encode2(GIFBS_EnableFlatScratch_HasFlatScratchInsts),
      GIM_CheckMemoryAddressSpace, /*MI*/0, /*MMO*/0, /*NumAddrSpace*/1, /*AddrSpace*/5,
      GIM_CheckAtomicOrdering, /*MI*/0, /*Order*/(uint8_t)AtomicOrdering::NotAtomic,
      GIM_CheckRegBankForClass, /*MI*/0, /*Op*/0, /*RC*/GIMT_Encode2(AMDGPU::AV_32RegClassID),
      GIM_CheckPointerToAny, /*MI*/0, /*Op*/1, /*SizeInBits*/0,
      GIM_CheckComplexPattern, /*MI*/0, /*Op*/1, /*Renderer*/GIMT_Encode2(0), GIMT_Encode2(GICP_gi_flat_scratch_saddr),
      // (ld:{ *:[v2i16] } (ScratchSAddr:{ *:[iPTR] } SGPR_32:{ *:[i32] }:$saddr, i32:{ *:[i32] }:$offset))<<P:Predicate_unindexedload>><<P:Predicate_load_private>>  =>  (SCRATCH_LOAD_DWORD_SADDR:{ *:[v2i16] } ?:{ *:[i32] }:$saddr, ?:{ *:[i32] }:$offset)
      GIR_BuildMI, /*InsnID*/0, /*Opcode*/GIMT_Encode2(AMDGPU::SCRATCH_LOAD_DWORD_SADDR),
      GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/0, // DstI[vdst]
      GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/0, // saddr
      GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/1, // offset
      GIR_AddImm8, /*InsnID*/0, /*Imm*/0,
      GIR_MergeMemOperands, /*InsnID*/0, /*NumInsns*/1, /*MergeInsnID's*/0,
      GIR_ConstrainSelectedInstOperands, /*InsnID*/0,
      GIR_EraseFromParent, /*InsnID*/0,
      // GIR_Coverage, 3441,
      GIR_Done,
    // Label 1243: @82200
    GIM_Try, /*On fail goto*//*Label 1244*/ GIMT_Encode4(82262), // Rule ID 3447 //
      GIM_CheckFeatures, GIMT_Encode2(GIFBS_EnableFlatScratch_HasFlatScratchInsts),
      GIM_CheckMemoryAddressSpace, /*MI*/0, /*MMO*/0, /*NumAddrSpace*/1, /*AddrSpace*/5,
      GIM_CheckAtomicOrdering, /*MI*/0, /*Order*/(uint8_t)AtomicOrdering::NotAtomic,
      GIM_CheckRegBankForClass, /*MI*/0, /*Op*/0, /*RC*/GIMT_Encode2(AMDGPU::AV_32RegClassID),
      GIM_CheckPointerToAny, /*MI*/0, /*Op*/1, /*SizeInBits*/0,
      GIM_CheckComplexPattern, /*MI*/0, /*Op*/1, /*Renderer*/GIMT_Encode2(0), GIMT_Encode2(GICP_gi_flat_scratch_saddr),
      // (ld:{ *:[v2f16] } (ScratchSAddr:{ *:[iPTR] } SGPR_32:{ *:[i32] }:$saddr, i32:{ *:[i32] }:$offset))<<P:Predicate_unindexedload>><<P:Predicate_load_private>>  =>  (SCRATCH_LOAD_DWORD_SADDR:{ *:[v2f16] } ?:{ *:[i32] }:$saddr, ?:{ *:[i32] }:$offset)
      GIR_BuildMI, /*InsnID*/0, /*Opcode*/GIMT_Encode2(AMDGPU::SCRATCH_LOAD_DWORD_SADDR),
      GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/0, // DstI[vdst]
      GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/0, // saddr
      GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/1, // offset
      GIR_AddImm8, /*InsnID*/0, /*Imm*/0,
      GIR_MergeMemOperands, /*InsnID*/0, /*NumInsns*/1, /*MergeInsnID's*/0,
      GIR_ConstrainSelectedInstOperands, /*InsnID*/0,
      GIR_EraseFromParent, /*InsnID*/0,
      // GIR_Coverage, 3447,
      GIR_Done,
    // Label 1244: @82262
    GIM_Try, /*On fail goto*//*Label 1245*/ GIMT_Encode4(82324), // Rule ID 3453 //
      GIM_CheckFeatures, GIMT_Encode2(GIFBS_EnableFlatScratch_HasFlatScratchInsts),
      GIM_CheckMemoryAddressSpace, /*MI*/0, /*MMO*/0, /*NumAddrSpace*/1, /*AddrSpace*/5,
      GIM_CheckAtomicOrdering, /*MI*/0, /*Order*/(uint8_t)AtomicOrdering::NotAtomic,
      GIM_CheckRegBankForClass, /*MI*/0, /*Op*/0, /*RC*/GIMT_Encode2(AMDGPU::AV_32RegClassID),
      GIM_CheckPointerToAny, /*MI*/0, /*Op*/1, /*SizeInBits*/0,
      GIM_CheckComplexPattern, /*MI*/0, /*Op*/1, /*Renderer*/GIMT_Encode2(0), GIMT_Encode2(GICP_gi_flat_scratch_saddr),
      // (ld:{ *:[v2bf16] } (ScratchSAddr:{ *:[iPTR] } SGPR_32:{ *:[i32] }:$saddr, i32:{ *:[i32] }:$offset))<<P:Predicate_unindexedload>><<P:Predicate_load_private>>  =>  (SCRATCH_LOAD_DWORD_SADDR:{ *:[v2bf16] } ?:{ *:[i32] }:$saddr, ?:{ *:[i32] }:$offset)
      GIR_BuildMI, /*InsnID*/0, /*Opcode*/GIMT_Encode2(AMDGPU::SCRATCH_LOAD_DWORD_SADDR),
      GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/0, // DstI[vdst]
      GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/0, // saddr
      GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/1, // offset
      GIR_AddImm8, /*InsnID*/0, /*Imm*/0,
      GIR_MergeMemOperands, /*InsnID*/0, /*NumInsns*/1, /*MergeInsnID's*/0,
      GIR_ConstrainSelectedInstOperands, /*InsnID*/0,
      GIR_EraseFromParent, /*InsnID*/0,
      // GIR_Coverage, 3453,
      GIR_Done,
    // Label 1245: @82324
    GIM_Try, /*On fail goto*//*Label 1246*/ GIMT_Encode4(82386), // Rule ID 3440 //
      GIM_CheckFeatures, GIMT_Encode2(GIFBS_EnableFlatScratch_HasFlatScratchInsts),
      GIM_CheckMemoryAddressSpace, /*MI*/0, /*MMO*/0, /*NumAddrSpace*/1, /*AddrSpace*/5,
      GIM_CheckAtomicOrdering, /*MI*/0, /*Order*/(uint8_t)AtomicOrdering::NotAtomic,
      GIM_CheckRegBankForClass, /*MI*/0, /*Op*/0, /*RC*/GIMT_Encode2(AMDGPU::AV_32RegClassID),
      GIM_CheckPointerToAny, /*MI*/0, /*Op*/1, /*SizeInBits*/0,
      GIM_CheckComplexPattern, /*MI*/0, /*Op*/1, /*Renderer*/GIMT_Encode2(0), GIMT_Encode2(GICP_gi_flat_scratch_offset),
      // (ld:{ *:[v2i16] } (ScratchOffset:{ *:[iPTR] } VGPR_32:{ *:[i32] }:$vaddr, i32:{ *:[i32] }:$offset))<<P:Predicate_unindexedload>><<P:Predicate_load_private>>  =>  (SCRATCH_LOAD_DWORD:{ *:[v2i16] } ?:{ *:[i32] }:$vaddr, ?:{ *:[i32] }:$offset)
      GIR_BuildMI, /*InsnID*/0, /*Opcode*/GIMT_Encode2(AMDGPU::SCRATCH_LOAD_DWORD),
      GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/0, // DstI[vdst]
      GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/0, // vaddr
      GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/1, // offset
      GIR_AddImm8, /*InsnID*/0, /*Imm*/0,
      GIR_MergeMemOperands, /*InsnID*/0, /*NumInsns*/1, /*MergeInsnID's*/0,
      GIR_ConstrainSelectedInstOperands, /*InsnID*/0,
      GIR_EraseFromParent, /*InsnID*/0,
      // GIR_Coverage, 3440,
      GIR_Done,
    // Label 1246: @82386
    GIM_Try, /*On fail goto*//*Label 1247*/ GIMT_Encode4(82448), // Rule ID 3446 //
      GIM_CheckFeatures, GIMT_Encode2(GIFBS_EnableFlatScratch_HasFlatScratchInsts),
      GIM_CheckMemoryAddressSpace, /*MI*/0, /*MMO*/0, /*NumAddrSpace*/1, /*AddrSpace*/5,
      GIM_CheckAtomicOrdering, /*MI*/0, /*Order*/(uint8_t)AtomicOrdering::NotAtomic,
      GIM_CheckRegBankForClass, /*MI*/0, /*Op*/0, /*RC*/GIMT_Encode2(AMDGPU::AV_32RegClassID),
      GIM_CheckPointerToAny, /*MI*/0, /*Op*/1, /*SizeInBits*/0,
      GIM_CheckComplexPattern, /*MI*/0, /*Op*/1, /*Renderer*/GIMT_Encode2(0), GIMT_Encode2(GICP_gi_flat_scratch_offset),
      // (ld:{ *:[v2f16] } (ScratchOffset:{ *:[iPTR] } VGPR_32:{ *:[i32] }:$vaddr, i32:{ *:[i32] }:$offset))<<P:Predicate_unindexedload>><<P:Predicate_load_private>>  =>  (SCRATCH_LOAD_DWORD:{ *:[v2f16] } ?:{ *:[i32] }:$vaddr, ?:{ *:[i32] }:$offset)
      GIR_BuildMI, /*InsnID*/0, /*Opcode*/GIMT_Encode2(AMDGPU::SCRATCH_LOAD_DWORD),
      GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/0, // DstI[vdst]
      GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/0, // vaddr
      GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/1, // offset
      GIR_AddImm8, /*InsnID*/0, /*Imm*/0,
      GIR_MergeMemOperands, /*InsnID*/0, /*NumInsns*/1, /*MergeInsnID's*/0,
      GIR_ConstrainSelectedInstOperands, /*InsnID*/0,
      GIR_EraseFromParent, /*InsnID*/0,
      // GIR_Coverage, 3446,
      GIR_Done,
    // Label 1247: @82448
    GIM_Try, /*On fail goto*//*Label 1248*/ GIMT_Encode4(82510), // Rule ID 3452 //
      GIM_CheckFeatures, GIMT_Encode2(GIFBS_EnableFlatScratch_HasFlatScratchInsts),
      GIM_CheckMemoryAddressSpace, /*MI*/0, /*MMO*/0, /*NumAddrSpace*/1, /*AddrSpace*/5,
      GIM_CheckAtomicOrdering, /*MI*/0, /*Order*/(uint8_t)AtomicOrdering::NotAtomic,
      GIM_CheckRegBankForClass, /*MI*/0, /*Op*/0, /*RC*/GIMT_Encode2(AMDGPU::AV_32RegClassID),
      GIM_CheckPointerToAny, /*MI*/0, /*Op*/1, /*SizeInBits*/0,
      GIM_CheckComplexPattern, /*MI*/0, /*Op*/1, /*Renderer*/GIMT_Encode2(0), GIMT_Encode2(GICP_gi_flat_scratch_offset),
      // (ld:{ *:[v2bf16] } (ScratchOffset:{ *:[iPTR] } VGPR_32:{ *:[i32] }:$vaddr, i32:{ *:[i32] }:$offset))<<P:Predicate_unindexedload>><<P:Predicate_load_private>>  =>  (SCRATCH_LOAD_DWORD:{ *:[v2bf16] } ?:{ *:[i32] }:$vaddr, ?:{ *:[i32] }:$offset)
      GIR_BuildMI, /*InsnID*/0, /*Opcode*/GIMT_Encode2(AMDGPU::SCRATCH_LOAD_DWORD),
      GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/0, // DstI[vdst]
      GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/0, // vaddr
      GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/1, // offset
      GIR_AddImm8, /*InsnID*/0, /*Imm*/0,
      GIR_MergeMemOperands, /*InsnID*/0, /*NumInsns*/1, /*MergeInsnID's*/0,
      GIR_ConstrainSelectedInstOperands, /*InsnID*/0,
      GIR_EraseFromParent, /*InsnID*/0,
      // GIR_Coverage, 3452,
      GIR_Done,
    // Label 1248: @82510
    GIM_Try, /*On fail goto*//*Label 1249*/ GIMT_Encode4(82587), // Rule ID 3692 //
      GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasUnrestrictedSOffset),
      GIM_CheckMemoryAddressSpace, /*MI*/0, /*MMO*/0, /*NumAddrSpace*/3, /*AddrSpace*/1, /*AddrSpace*/4, /*AddrSpace*/6,
      GIM_CheckAtomicOrdering, /*MI*/0, /*Order*/(uint8_t)AtomicOrdering::NotAtomic,
      GIM_CheckRegBankForClass, /*MI*/0, /*Op*/0, /*RC*/GIMT_Encode2(AMDGPU::AV_32RegClassID),
      GIM_CheckPointerToAny, /*MI*/0, /*Op*/1, /*SizeInBits*/0,
      GIM_CheckComplexPattern, /*MI*/0, /*Op*/1, /*Renderer*/GIMT_Encode2(0), GIMT_Encode2(GICP_gi_mubuf_addr64),
      // (ld:{ *:[v2i16] } (MUBUFAddr64:{ *:[iPTR] } v4i32:{ *:[v4i32] }:$srsrc, i64:{ *:[i64] }:$vaddr, i32:{ *:[i32] }:$soffset, i32:{ *:[i32] }:$offset))<<P:Predicate_unindexedload>><<P:Predicate_load_global>>  =>  (BUFFER_LOAD_DWORD_ADDR64:{ *:[v2i16] } i64:{ *:[i64] }:$vaddr, v4i32:{ *:[v4i32] }:$srsrc, i32:{ *:[i32] }:$soffset, i32:{ *:[i32] }:$offset)
      GIR_BuildMI, /*InsnID*/0, /*Opcode*/GIMT_Encode2(AMDGPU::BUFFER_LOAD_DWORD_ADDR64),
      GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/0, // DstI[vdata]
      GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/1, // vaddr
      GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/0, // srsrc
      GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/2, // soffset
      GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/3, // offset
      GIR_AddImm8, /*InsnID*/0, /*Imm*/0,
      GIR_AddImm8, /*InsnID*/0, /*Imm*/0,
      GIR_MergeMemOperands, /*InsnID*/0, /*NumInsns*/1, /*MergeInsnID's*/0,
      GIR_ConstrainSelectedInstOperands, /*InsnID*/0,
      GIR_EraseFromParent, /*InsnID*/0,
      // GIR_Coverage, 3692,
      GIR_Done,
    // Label 1249: @82587
    GIM_Try, /*On fail goto*//*Label 1250*/ GIMT_Encode4(82661), // Rule ID 3694 //
      GIM_CheckMemoryAddressSpace, /*MI*/0, /*MMO*/0, /*NumAddrSpace*/3, /*AddrSpace*/1, /*AddrSpace*/4, /*AddrSpace*/6,
      GIM_CheckAtomicOrdering, /*MI*/0, /*Order*/(uint8_t)AtomicOrdering::NotAtomic,
      GIM_CheckRegBankForClass, /*MI*/0, /*Op*/0, /*RC*/GIMT_Encode2(AMDGPU::AV_32RegClassID),
      GIM_CheckPointerToAny, /*MI*/0, /*Op*/1, /*SizeInBits*/0,
      GIM_CheckComplexPattern, /*MI*/0, /*Op*/1, /*Renderer*/GIMT_Encode2(0), GIMT_Encode2(GICP_gi_mubuf_addr64),
      // (ld:{ *:[v2i16] } (MUBUFAddr64:{ *:[iPTR] } v4i32:{ *:[v4i32] }:$srsrc, i64:{ *:[i64] }:$vaddr, i32:{ *:[i32] }:$soffset, i32:{ *:[i32] }:$offset))<<P:Predicate_unindexedload>><<P:Predicate_load_global>>  =>  (BUFFER_LOAD_DWORD_VBUFFER_ADDR64:{ *:[v2i16] } i64:{ *:[i64] }:$vaddr, v4i32:{ *:[v4i32] }:$srsrc, i32:{ *:[i32] }:$soffset, i32:{ *:[i32] }:$offset)
      GIR_BuildMI, /*InsnID*/0, /*Opcode*/GIMT_Encode2(AMDGPU::BUFFER_LOAD_DWORD_VBUFFER_ADDR64),
      GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/0, // DstI[vdata]
      GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/1, // vaddr
      GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/0, // srsrc
      GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/2, // soffset
      GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/3, // offset
      GIR_AddImm8, /*InsnID*/0, /*Imm*/0,
      GIR_AddImm8, /*InsnID*/0, /*Imm*/0,
      GIR_MergeMemOperands, /*InsnID*/0, /*NumInsns*/1, /*MergeInsnID's*/0,
      GIR_ConstrainSelectedInstOperands, /*InsnID*/0,
      GIR_EraseFromParent, /*InsnID*/0,
      // GIR_Coverage, 3694,
      GIR_Done,
    // Label 1250: @82661
    GIM_Try, /*On fail goto*//*Label 1251*/ GIMT_Encode4(82738), // Rule ID 3696 //
      GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasUnrestrictedSOffset),
      GIM_CheckMemoryAddressSpace, /*MI*/0, /*MMO*/0, /*NumAddrSpace*/3, /*AddrSpace*/1, /*AddrSpace*/4, /*AddrSpace*/6,
      GIM_CheckAtomicOrdering, /*MI*/0, /*Order*/(uint8_t)AtomicOrdering::NotAtomic,
      GIM_CheckRegBankForClass, /*MI*/0, /*Op*/0, /*RC*/GIMT_Encode2(AMDGPU::AV_32RegClassID),
      GIM_CheckPointerToAny, /*MI*/0, /*Op*/1, /*SizeInBits*/0,
      GIM_CheckComplexPattern, /*MI*/0, /*Op*/1, /*Renderer*/GIMT_Encode2(0), GIMT_Encode2(GICP_gi_mubuf_addr64),
      // (ld:{ *:[v2f16] } (MUBUFAddr64:{ *:[iPTR] } v4i32:{ *:[v4i32] }:$srsrc, i64:{ *:[i64] }:$vaddr, i32:{ *:[i32] }:$soffset, i32:{ *:[i32] }:$offset))<<P:Predicate_unindexedload>><<P:Predicate_load_global>>  =>  (BUFFER_LOAD_DWORD_ADDR64:{ *:[v2f16] } i64:{ *:[i64] }:$vaddr, v4i32:{ *:[v4i32] }:$srsrc, i32:{ *:[i32] }:$soffset, i32:{ *:[i32] }:$offset)
      GIR_BuildMI, /*InsnID*/0, /*Opcode*/GIMT_Encode2(AMDGPU::BUFFER_LOAD_DWORD_ADDR64),
      GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/0, // DstI[vdata]
      GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/1, // vaddr
      GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/0, // srsrc
      GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/2, // soffset
      GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/3, // offset
      GIR_AddImm8, /*InsnID*/0, /*Imm*/0,
      GIR_AddImm8, /*InsnID*/0, /*Imm*/0,
      GIR_MergeMemOperands, /*InsnID*/0, /*NumInsns*/1, /*MergeInsnID's*/0,
      GIR_ConstrainSelectedInstOperands, /*InsnID*/0,
      GIR_EraseFromParent, /*InsnID*/0,
      // GIR_Coverage, 3696,
      GIR_Done,
    // Label 1251: @82738
    GIM_Try, /*On fail goto*//*Label 1252*/ GIMT_Encode4(82812), // Rule ID 3698 //
      GIM_CheckMemoryAddressSpace, /*MI*/0, /*MMO*/0, /*NumAddrSpace*/3, /*AddrSpace*/1, /*AddrSpace*/4, /*AddrSpace*/6,
      GIM_CheckAtomicOrdering, /*MI*/0, /*Order*/(uint8_t)AtomicOrdering::NotAtomic,
      GIM_CheckRegBankForClass, /*MI*/0, /*Op*/0, /*RC*/GIMT_Encode2(AMDGPU::AV_32RegClassID),
      GIM_CheckPointerToAny, /*MI*/0, /*Op*/1, /*SizeInBits*/0,
      GIM_CheckComplexPattern, /*MI*/0, /*Op*/1, /*Renderer*/GIMT_Encode2(0), GIMT_Encode2(GICP_gi_mubuf_addr64),
      // (ld:{ *:[v2f16] } (MUBUFAddr64:{ *:[iPTR] } v4i32:{ *:[v4i32] }:$srsrc, i64:{ *:[i64] }:$vaddr, i32:{ *:[i32] }:$soffset, i32:{ *:[i32] }:$offset))<<P:Predicate_unindexedload>><<P:Predicate_load_global>>  =>  (BUFFER_LOAD_DWORD_VBUFFER_ADDR64:{ *:[v2f16] } i64:{ *:[i64] }:$vaddr, v4i32:{ *:[v4i32] }:$srsrc, i32:{ *:[i32] }:$soffset, i32:{ *:[i32] }:$offset)
      GIR_BuildMI, /*InsnID*/0, /*Opcode*/GIMT_Encode2(AMDGPU::BUFFER_LOAD_DWORD_VBUFFER_ADDR64),
      GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/0, // DstI[vdata]
      GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/1, // vaddr
      GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/0, // srsrc
      GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/2, // soffset
      GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/3, // offset
      GIR_AddImm8, /*InsnID*/0, /*Imm*/0,
      GIR_AddImm8, /*InsnID*/0, /*Imm*/0,
      GIR_MergeMemOperands, /*InsnID*/0, /*NumInsns*/1, /*MergeInsnID's*/0,
      GIR_ConstrainSelectedInstOperands, /*InsnID*/0,
      GIR_EraseFromParent, /*InsnID*/0,
      // GIR_Coverage, 3698,
      GIR_Done,
    // Label 1252: @82812
    GIM_Try, /*On fail goto*//*Label 1253*/ GIMT_Encode4(82889), // Rule ID 3700 //
      GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasUnrestrictedSOffset),
      GIM_CheckMemoryAddressSpace, /*MI*/0, /*MMO*/0, /*NumAddrSpace*/3, /*AddrSpace*/1, /*AddrSpace*/4, /*AddrSpace*/6,
      GIM_CheckAtomicOrdering, /*MI*/0, /*Order*/(uint8_t)AtomicOrdering::NotAtomic,
      GIM_CheckRegBankForClass, /*MI*/0, /*Op*/0, /*RC*/GIMT_Encode2(AMDGPU::AV_32RegClassID),
      GIM_CheckPointerToAny, /*MI*/0, /*Op*/1, /*SizeInBits*/0,
      GIM_CheckComplexPattern, /*MI*/0, /*Op*/1, /*Renderer*/GIMT_Encode2(0), GIMT_Encode2(GICP_gi_mubuf_addr64),
      // (ld:{ *:[v2bf16] } (MUBUFAddr64:{ *:[iPTR] } v4i32:{ *:[v4i32] }:$srsrc, i64:{ *:[i64] }:$vaddr, i32:{ *:[i32] }:$soffset, i32:{ *:[i32] }:$offset))<<P:Predicate_unindexedload>><<P:Predicate_load_global>>  =>  (BUFFER_LOAD_DWORD_ADDR64:{ *:[v2bf16] } i64:{ *:[i64] }:$vaddr, v4i32:{ *:[v4i32] }:$srsrc, i32:{ *:[i32] }:$soffset, i32:{ *:[i32] }:$offset)
      GIR_BuildMI, /*InsnID*/0, /*Opcode*/GIMT_Encode2(AMDGPU::BUFFER_LOAD_DWORD_ADDR64),
      GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/0, // DstI[vdata]
      GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/1, // vaddr
      GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/0, // srsrc
      GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/2, // soffset
      GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/3, // offset
      GIR_AddImm8, /*InsnID*/0, /*Imm*/0,
      GIR_AddImm8, /*InsnID*/0, /*Imm*/0,
      GIR_MergeMemOperands, /*InsnID*/0, /*NumInsns*/1, /*MergeInsnID's*/0,
      GIR_ConstrainSelectedInstOperands, /*InsnID*/0,
      GIR_EraseFromParent, /*InsnID*/0,
      // GIR_Coverage, 3700,
      GIR_Done,
    // Label 1253: @82889
    GIM_Try, /*On fail goto*//*Label 1254*/ GIMT_Encode4(82963), // Rule ID 3702 //
      GIM_CheckMemoryAddressSpace, /*MI*/0, /*MMO*/0, /*NumAddrSpace*/3, /*AddrSpace*/1, /*AddrSpace*/4, /*AddrSpace*/6,
      GIM_CheckAtomicOrdering, /*MI*/0, /*Order*/(uint8_t)AtomicOrdering::NotAtomic,
      GIM_CheckRegBankForClass, /*MI*/0, /*Op*/0, /*RC*/GIMT_Encode2(AMDGPU::AV_32RegClassID),
      GIM_CheckPointerToAny, /*MI*/0, /*Op*/1, /*SizeInBits*/0,
      GIM_CheckComplexPattern, /*MI*/0, /*Op*/1, /*Renderer*/GIMT_Encode2(0), GIMT_Encode2(GICP_gi_mubuf_addr64),
      // (ld:{ *:[v2bf16] } (MUBUFAddr64:{ *:[iPTR] } v4i32:{ *:[v4i32] }:$srsrc, i64:{ *:[i64] }:$vaddr, i32:{ *:[i32] }:$soffset, i32:{ *:[i32] }:$offset))<<P:Predicate_unindexedload>><<P:Predicate_load_global>>  =>  (BUFFER_LOAD_DWORD_VBUFFER_ADDR64:{ *:[v2bf16] } i64:{ *:[i64] }:$vaddr, v4i32:{ *:[v4i32] }:$srsrc, i32:{ *:[i32] }:$soffset, i32:{ *:[i32] }:$offset)
      GIR_BuildMI, /*InsnID*/0, /*Opcode*/GIMT_Encode2(AMDGPU::BUFFER_LOAD_DWORD_VBUFFER_ADDR64),
      GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/0, // DstI[vdata]
      GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/1, // vaddr
      GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/0, // srsrc
      GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/2, // soffset
      GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/3, // offset
      GIR_AddImm8, /*InsnID*/0, /*Imm*/0,
      GIR_AddImm8, /*InsnID*/0, /*Imm*/0,
      GIR_MergeMemOperands, /*InsnID*/0, /*NumInsns*/1, /*MergeInsnID's*/0,
      GIR_ConstrainSelectedInstOperands, /*InsnID*/0,
      GIR_EraseFromParent, /*InsnID*/0,
      // GIR_Coverage, 3702,
      GIR_Done,
    // Label 1254: @82963
    GIM_Try, /*On fail goto*//*Label 1255*/ GIMT_Encode4(83038), // Rule ID 5395 //
      GIM_CheckFeatures, GIMT_Encode2(GIFBS_DisableFlatScratch_HasUnrestrictedSOffset),
      GIM_CheckMemoryAddressSpace, /*MI*/0, /*MMO*/0, /*NumAddrSpace*/1, /*AddrSpace*/5,
      GIM_CheckAtomicOrdering, /*MI*/0, /*Order*/(uint8_t)AtomicOrdering::NotAtomic,
      GIM_CheckRegBankForClass, /*MI*/0, /*Op*/0, /*RC*/GIMT_Encode2(AMDGPU::AV_32RegClassID),
      GIM_CheckPointerToAny, /*MI*/0, /*Op*/1, /*SizeInBits*/0,
      GIM_CheckComplexPattern, /*MI*/0, /*Op*/1, /*Renderer*/GIMT_Encode2(0), GIMT_Encode2(GICP_gi_mubuf_scratch_offen),
      // (ld:{ *:[v2i16] } (MUBUFScratchOffen:{ *:[iPTR] } v4i32:{ *:[v4i32] }:$srsrc, i32:{ *:[i32] }:$vaddr, i32:{ *:[i32] }:$soffset, i32:{ *:[i32] }:$offset))<<P:Predicate_unindexedload>><<P:Predicate_load_private>>  =>  (BUFFER_LOAD_DWORD_OFFEN:{ *:[v2i16] } ?:{ *:[i32] }:$vaddr, ?:{ *:[v4i32] }:$srsrc, ?:{ *:[i32] }:$soffset, ?:{ *:[i32] }:$offset, 0:{ *:[i32] }, 0:{ *:[i1] })
      GIR_BuildMI, /*InsnID*/0, /*Opcode*/GIMT_Encode2(AMDGPU::BUFFER_LOAD_DWORD_OFFEN),
      GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/0, // DstI[vdata]
      GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/1, // vaddr
      GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/0, // srsrc
      GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/2, // soffset
      GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/3, // offset
      GIR_AddImm8, /*InsnID*/0, /*Imm*/0,
      GIR_AddImm8, /*InsnID*/0, /*Imm*/0,
      GIR_MergeMemOperands, /*InsnID*/0, /*NumInsns*/1, /*MergeInsnID's*/0,
      GIR_ConstrainSelectedInstOperands, /*InsnID*/0,
      GIR_EraseFromParent, /*InsnID*/0,
      // GIR_Coverage, 5395,
      GIR_Done,
    // Label 1255: @83038
    GIM_Try, /*On fail goto*//*Label 1256*/ GIMT_Encode4(83113), // Rule ID 5397 //
      GIM_CheckFeatures, GIMT_Encode2(GIFBS_DisableFlatScratch),
      GIM_CheckMemoryAddressSpace, /*MI*/0, /*MMO*/0, /*NumAddrSpace*/1, /*AddrSpace*/5,
      GIM_CheckAtomicOrdering, /*MI*/0, /*Order*/(uint8_t)AtomicOrdering::NotAtomic,
      GIM_CheckRegBankForClass, /*MI*/0, /*Op*/0, /*RC*/GIMT_Encode2(AMDGPU::AV_32RegClassID),
      GIM_CheckPointerToAny, /*MI*/0, /*Op*/1, /*SizeInBits*/0,
      GIM_CheckComplexPattern, /*MI*/0, /*Op*/1, /*Renderer*/GIMT_Encode2(0), GIMT_Encode2(GICP_gi_mubuf_scratch_offen),
      // (ld:{ *:[v2i16] } (MUBUFScratchOffen:{ *:[iPTR] } v4i32:{ *:[v4i32] }:$srsrc, i32:{ *:[i32] }:$vaddr, i32:{ *:[i32] }:$soffset, i32:{ *:[i32] }:$offset))<<P:Predicate_unindexedload>><<P:Predicate_load_private>>  =>  (BUFFER_LOAD_DWORD_VBUFFER_OFFEN:{ *:[v2i16] } ?:{ *:[i32] }:$vaddr, ?:{ *:[v4i32] }:$srsrc, ?:{ *:[i32] }:$soffset, ?:{ *:[i32] }:$offset, 0:{ *:[i32] }, 0:{ *:[i1] })
      GIR_BuildMI, /*InsnID*/0, /*Opcode*/GIMT_Encode2(AMDGPU::BUFFER_LOAD_DWORD_VBUFFER_OFFEN),
      GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/0, // DstI[vdata]
      GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/1, // vaddr
      GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/0, // srsrc
      GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/2, // soffset
      GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/3, // offset
      GIR_AddImm8, /*InsnID*/0, /*Imm*/0,
      GIR_AddImm8, /*InsnID*/0, /*Imm*/0,
      GIR_MergeMemOperands, /*InsnID*/0, /*NumInsns*/1, /*MergeInsnID's*/0,
      GIR_ConstrainSelectedInstOperands, /*InsnID*/0,
      GIR_EraseFromParent, /*InsnID*/0,
      // GIR_Coverage, 5397,
      GIR_Done,
    // Label 1256: @83113
    GIM_Try, /*On fail goto*//*Label 1257*/ GIMT_Encode4(83188), // Rule ID 5399 //
      GIM_CheckFeatures, GIMT_Encode2(GIFBS_DisableFlatScratch_HasUnrestrictedSOffset),
      GIM_CheckMemoryAddressSpace, /*MI*/0, /*MMO*/0, /*NumAddrSpace*/1, /*AddrSpace*/5,
      GIM_CheckAtomicOrdering, /*MI*/0, /*Order*/(uint8_t)AtomicOrdering::NotAtomic,
      GIM_CheckRegBankForClass, /*MI*/0, /*Op*/0, /*RC*/GIMT_Encode2(AMDGPU::AV_32RegClassID),
      GIM_CheckPointerToAny, /*MI*/0, /*Op*/1, /*SizeInBits*/0,
      GIM_CheckComplexPattern, /*MI*/0, /*Op*/1, /*Renderer*/GIMT_Encode2(0), GIMT_Encode2(GICP_gi_mubuf_scratch_offen),
      // (ld:{ *:[v2f16] } (MUBUFScratchOffen:{ *:[iPTR] } v4i32:{ *:[v4i32] }:$srsrc, i32:{ *:[i32] }:$vaddr, i32:{ *:[i32] }:$soffset, i32:{ *:[i32] }:$offset))<<P:Predicate_unindexedload>><<P:Predicate_load_private>>  =>  (BUFFER_LOAD_DWORD_OFFEN:{ *:[v2f16] } ?:{ *:[i32] }:$vaddr, ?:{ *:[v4i32] }:$srsrc, ?:{ *:[i32] }:$soffset, ?:{ *:[i32] }:$offset, 0:{ *:[i32] }, 0:{ *:[i1] })
      GIR_BuildMI, /*InsnID*/0, /*Opcode*/GIMT_Encode2(AMDGPU::BUFFER_LOAD_DWORD_OFFEN),
      GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/0, // DstI[vdata]
      GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/1, // vaddr
      GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/0, // srsrc
      GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/2, // soffset
      GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/3, // offset
      GIR_AddImm8, /*InsnID*/0, /*Imm*/0,
      GIR_AddImm8, /*InsnID*/0, /*Imm*/0,
      GIR_MergeMemOperands, /*InsnID*/0, /*NumInsns*/1, /*MergeInsnID's*/0,
      GIR_ConstrainSelectedInstOperands, /*InsnID*/0,
      GIR_EraseFromParent, /*InsnID*/0,
      // GIR_Coverage, 5399,
      GIR_Done,
    // Label 1257: @83188
    GIM_Try, /*On fail goto*//*Label 1258*/ GIMT_Encode4(83263), // Rule ID 5401 //
      GIM_CheckFeatures, GIMT_Encode2(GIFBS_DisableFlatScratch),
      GIM_CheckMemoryAddressSpace, /*MI*/0, /*MMO*/0, /*NumAddrSpace*/1, /*AddrSpace*/5,
      GIM_CheckAtomicOrdering, /*MI*/0, /*Order*/(uint8_t)AtomicOrdering::NotAtomic,
      GIM_CheckRegBankForClass, /*MI*/0, /*Op*/0, /*RC*/GIMT_Encode2(AMDGPU::AV_32RegClassID),
      GIM_CheckPointerToAny, /*MI*/0, /*Op*/1, /*SizeInBits*/0,
      GIM_CheckComplexPattern, /*MI*/0, /*Op*/1, /*Renderer*/GIMT_Encode2(0), GIMT_Encode2(GICP_gi_mubuf_scratch_offen),
      // (ld:{ *:[v2f16] } (MUBUFScratchOffen:{ *:[iPTR] } v4i32:{ *:[v4i32] }:$srsrc, i32:{ *:[i32] }:$vaddr, i32:{ *:[i32] }:$soffset, i32:{ *:[i32] }:$offset))<<P:Predicate_unindexedload>><<P:Predicate_load_private>>  =>  (BUFFER_LOAD_DWORD_VBUFFER_OFFEN:{ *:[v2f16] } ?:{ *:[i32] }:$vaddr, ?:{ *:[v4i32] }:$srsrc, ?:{ *:[i32] }:$soffset, ?:{ *:[i32] }:$offset, 0:{ *:[i32] }, 0:{ *:[i1] })
      GIR_BuildMI, /*InsnID*/0, /*Opcode*/GIMT_Encode2(AMDGPU::BUFFER_LOAD_DWORD_VBUFFER_OFFEN),
      GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/0, // DstI[vdata]
      GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/1, // vaddr
      GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/0, // srsrc
      GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/2, // soffset
      GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/3, // offset
      GIR_AddImm8, /*InsnID*/0, /*Imm*/0,
      GIR_AddImm8, /*InsnID*/0, /*Imm*/0,
      GIR_MergeMemOperands, /*InsnID*/0, /*NumInsns*/1, /*MergeInsnID's*/0,
      GIR_ConstrainSelectedInstOperands, /*InsnID*/0,
      GIR_EraseFromParent, /*InsnID*/0,
      // GIR_Coverage, 5401,
      GIR_Done,
    // Label 1258: @83263
    GIM_Try, /*On fail goto*//*Label 1259*/ GIMT_Encode4(83338), // Rule ID 5403 //
      GIM_CheckFeatures, GIMT_Encode2(GIFBS_DisableFlatScratch_HasUnrestrictedSOffset),
      GIM_CheckMemoryAddressSpace, /*MI*/0, /*MMO*/0, /*NumAddrSpace*/1, /*AddrSpace*/5,
      GIM_CheckAtomicOrdering, /*MI*/0, /*Order*/(uint8_t)AtomicOrdering::NotAtomic,
      GIM_CheckRegBankForClass, /*MI*/0, /*Op*/0, /*RC*/GIMT_Encode2(AMDGPU::AV_32RegClassID),
      GIM_CheckPointerToAny, /*MI*/0, /*Op*/1, /*SizeInBits*/0,
      GIM_CheckComplexPattern, /*MI*/0, /*Op*/1, /*Renderer*/GIMT_Encode2(0), GIMT_Encode2(GICP_gi_mubuf_scratch_offen),
      // (ld:{ *:[v2bf16] } (MUBUFScratchOffen:{ *:[iPTR] } v4i32:{ *:[v4i32] }:$srsrc, i32:{ *:[i32] }:$vaddr, i32:{ *:[i32] }:$soffset, i32:{ *:[i32] }:$offset))<<P:Predicate_unindexedload>><<P:Predicate_load_private>>  =>  (BUFFER_LOAD_DWORD_OFFEN:{ *:[v2bf16] } ?:{ *:[i32] }:$vaddr, ?:{ *:[v4i32] }:$srsrc, ?:{ *:[i32] }:$soffset, ?:{ *:[i32] }:$offset, 0:{ *:[i32] }, 0:{ *:[i1] })
      GIR_BuildMI, /*InsnID*/0, /*Opcode*/GIMT_Encode2(AMDGPU::BUFFER_LOAD_DWORD_OFFEN),
      GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/0, // DstI[vdata]
      GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/1, // vaddr
      GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/0, // srsrc
      GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/2, // soffset
      GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/3, // offset
      GIR_AddImm8, /*InsnID*/0, /*Imm*/0,
      GIR_AddImm8, /*InsnID*/0, /*Imm*/0,
      GIR_MergeMemOperands, /*InsnID*/0, /*NumInsns*/1, /*MergeInsnID's*/0,
      GIR_ConstrainSelectedInstOperands, /*InsnID*/0,
      GIR_EraseFromParent, /*InsnID*/0,
      // GIR_Coverage, 5403,
      GIR_Done,
    // Label 1259: @83338
    GIM_Try, /*On fail goto*//*Label 1260*/ GIMT_Encode4(83413), // Rule ID 5405 //
      GIM_CheckFeatures, GIMT_Encode2(GIFBS_DisableFlatScratch),
      GIM_CheckMemoryAddressSpace, /*MI*/0, /*MMO*/0, /*NumAddrSpace*/1, /*AddrSpace*/5,
      GIM_CheckAtomicOrdering, /*MI*/0, /*Order*/(uint8_t)AtomicOrdering::NotAtomic,
      GIM_CheckRegBankForClass, /*MI*/0, /*Op*/0, /*RC*/GIMT_Encode2(AMDGPU::AV_32RegClassID),
      GIM_CheckPointerToAny, /*MI*/0, /*Op*/1, /*SizeInBits*/0,
      GIM_CheckComplexPattern, /*MI*/0, /*Op*/1, /*Renderer*/GIMT_Encode2(0), GIMT_Encode2(GICP_gi_mubuf_scratch_offen),
      // (ld:{ *:[v2bf16] } (MUBUFScratchOffen:{ *:[iPTR] } v4i32:{ *:[v4i32] }:$srsrc, i32:{ *:[i32] }:$vaddr, i32:{ *:[i32] }:$soffset, i32:{ *:[i32] }:$offset))<<P:Predicate_unindexedload>><<P:Predicate_load_private>>  =>  (BUFFER_LOAD_DWORD_VBUFFER_OFFEN:{ *:[v2bf16] } ?:{ *:[i32] }:$vaddr, ?:{ *:[v4i32] }:$srsrc, ?:{ *:[i32] }:$soffset, ?:{ *:[i32] }:$offset, 0:{ *:[i32] }, 0:{ *:[i1] })
      GIR_BuildMI, /*InsnID*/0, /*Opcode*/GIMT_Encode2(AMDGPU::BUFFER_LOAD_DWORD_VBUFFER_OFFEN),
      GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/0, // DstI[vdata]
      GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/1, // vaddr
      GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/0, // srsrc
      GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/2, // soffset
      GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/3, // offset
      GIR_AddImm8, /*InsnID*/0, /*Imm*/0,
      GIR_AddImm8, /*InsnID*/0, /*Imm*/0,
      GIR_MergeMemOperands, /*InsnID*/0, /*NumInsns*/1, /*MergeInsnID's*/0,
      GIR_ConstrainSelectedInstOperands, /*InsnID*/0,
      GIR_EraseFromParent, /*InsnID*/0,
      // GIR_Coverage, 5405,
      GIR_Done,
    // Label 1260: @83413
    GIM_Try, /*On fail goto*//*Label 1261*/ GIMT_Encode4(83485), // Rule ID 3691 //
      GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasUnrestrictedSOffset),
      GIM_CheckMemoryAddressSpace, /*MI*/0, /*MMO*/0, /*NumAddrSpace*/3, /*AddrSpace*/1, /*AddrSpace*/4, /*AddrSpace*/6,
      GIM_CheckAtomicOrdering, /*MI*/0, /*Order*/(uint8_t)AtomicOrdering::NotAtomic,
      GIM_CheckRegBankForClass, /*MI*/0, /*Op*/0, /*RC*/GIMT_Encode2(AMDGPU::AV_32RegClassID),
      GIM_CheckPointerToAny, /*MI*/0, /*Op*/1, /*SizeInBits*/0,
      GIM_CheckComplexPattern, /*MI*/0, /*Op*/1, /*Renderer*/GIMT_Encode2(0), GIMT_Encode2(GICP_gi_mubuf_offset),
      // (ld:{ *:[v2i16] } (MUBUFOffset:{ *:[iPTR] } v4i32:{ *:[v4i32] }:$srsrc, i32:{ *:[i32] }:$soffset, i32:{ *:[i32] }:$offset))<<P:Predicate_unindexedload>><<P:Predicate_load_global>>  =>  (BUFFER_LOAD_DWORD_OFFSET:{ *:[v2i16] } v4i32:{ *:[v4i32] }:$srsrc, i32:{ *:[i32] }:$soffset, i32:{ *:[i32] }:$offset)
      GIR_BuildMI, /*InsnID*/0, /*Opcode*/GIMT_Encode2(AMDGPU::BUFFER_LOAD_DWORD_OFFSET),
      GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/0, // DstI[vdata]
      GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/0, // srsrc
      GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/1, // soffset
      GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/2, // offset
      GIR_AddImm8, /*InsnID*/0, /*Imm*/0,
      GIR_AddImm8, /*InsnID*/0, /*Imm*/0,
      GIR_MergeMemOperands, /*InsnID*/0, /*NumInsns*/1, /*MergeInsnID's*/0,
      GIR_ConstrainSelectedInstOperands, /*InsnID*/0,
      GIR_EraseFromParent, /*InsnID*/0,
      // GIR_Coverage, 3691,
      GIR_Done,
    // Label 1261: @83485
    GIM_Try, /*On fail goto*//*Label 1262*/ GIMT_Encode4(83554), // Rule ID 3693 //
      GIM_CheckMemoryAddressSpace, /*MI*/0, /*MMO*/0, /*NumAddrSpace*/3, /*AddrSpace*/1, /*AddrSpace*/4, /*AddrSpace*/6,
      GIM_CheckAtomicOrdering, /*MI*/0, /*Order*/(uint8_t)AtomicOrdering::NotAtomic,
      GIM_CheckRegBankForClass, /*MI*/0, /*Op*/0, /*RC*/GIMT_Encode2(AMDGPU::AV_32RegClassID),
      GIM_CheckPointerToAny, /*MI*/0, /*Op*/1, /*SizeInBits*/0,
      GIM_CheckComplexPattern, /*MI*/0, /*Op*/1, /*Renderer*/GIMT_Encode2(0), GIMT_Encode2(GICP_gi_mubuf_offset),
      // (ld:{ *:[v2i16] } (MUBUFOffset:{ *:[iPTR] } v4i32:{ *:[v4i32] }:$srsrc, i32:{ *:[i32] }:$soffset, i32:{ *:[i32] }:$offset))<<P:Predicate_unindexedload>><<P:Predicate_load_global>>  =>  (BUFFER_LOAD_DWORD_VBUFFER_OFFSET:{ *:[v2i16] } v4i32:{ *:[v4i32] }:$srsrc, i32:{ *:[i32] }:$soffset, i32:{ *:[i32] }:$offset)
      GIR_BuildMI, /*InsnID*/0, /*Opcode*/GIMT_Encode2(AMDGPU::BUFFER_LOAD_DWORD_VBUFFER_OFFSET),
      GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/0, // DstI[vdata]
      GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/0, // srsrc
      GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/1, // soffset
      GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/2, // offset
      GIR_AddImm8, /*InsnID*/0, /*Imm*/0,
      GIR_AddImm8, /*InsnID*/0, /*Imm*/0,
      GIR_MergeMemOperands, /*InsnID*/0, /*NumInsns*/1, /*MergeInsnID's*/0,
      GIR_ConstrainSelectedInstOperands, /*InsnID*/0,
      GIR_EraseFromParent, /*InsnID*/0,
      // GIR_Coverage, 3693,
      GIR_Done,
    // Label 1262: @83554
    GIM_Try, /*On fail goto*//*Label 1263*/ GIMT_Encode4(83626), // Rule ID 3695 //
      GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasUnrestrictedSOffset),
      GIM_CheckMemoryAddressSpace, /*MI*/0, /*MMO*/0, /*NumAddrSpace*/3, /*AddrSpace*/1, /*AddrSpace*/4, /*AddrSpace*/6,
      GIM_CheckAtomicOrdering, /*MI*/0, /*Order*/(uint8_t)AtomicOrdering::NotAtomic,
      GIM_CheckRegBankForClass, /*MI*/0, /*Op*/0, /*RC*/GIMT_Encode2(AMDGPU::AV_32RegClassID),
      GIM_CheckPointerToAny, /*MI*/0, /*Op*/1, /*SizeInBits*/0,
      GIM_CheckComplexPattern, /*MI*/0, /*Op*/1, /*Renderer*/GIMT_Encode2(0), GIMT_Encode2(GICP_gi_mubuf_offset),
      // (ld:{ *:[v2f16] } (MUBUFOffset:{ *:[iPTR] } v4i32:{ *:[v4i32] }:$srsrc, i32:{ *:[i32] }:$soffset, i32:{ *:[i32] }:$offset))<<P:Predicate_unindexedload>><<P:Predicate_load_global>>  =>  (BUFFER_LOAD_DWORD_OFFSET:{ *:[v2f16] } v4i32:{ *:[v4i32] }:$srsrc, i32:{ *:[i32] }:$soffset, i32:{ *:[i32] }:$offset)
      GIR_BuildMI, /*InsnID*/0, /*Opcode*/GIMT_Encode2(AMDGPU::BUFFER_LOAD_DWORD_OFFSET),
      GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/0, // DstI[vdata]
      GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/0, // srsrc
      GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/1, // soffset
      GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/2, // offset
      GIR_AddImm8, /*InsnID*/0, /*Imm*/0,
      GIR_AddImm8, /*InsnID*/0, /*Imm*/0,
      GIR_MergeMemOperands, /*InsnID*/0, /*NumInsns*/1, /*MergeInsnID's*/0,
      GIR_ConstrainSelectedInstOperands, /*InsnID*/0,
      GIR_EraseFromParent, /*InsnID*/0,
      // GIR_Coverage, 3695,
      GIR_Done,
    // Label 1263: @83626
    GIM_Try, /*On fail goto*//*Label 1264*/ GIMT_Encode4(83695), // Rule ID 3697 //
      GIM_CheckMemoryAddressSpace, /*MI*/0, /*MMO*/0, /*NumAddrSpace*/3, /*AddrSpace*/1, /*AddrSpace*/4, /*AddrSpace*/6,
      GIM_CheckAtomicOrdering, /*MI*/0, /*Order*/(uint8_t)AtomicOrdering::NotAtomic,
      GIM_CheckRegBankForClass, /*MI*/0, /*Op*/0, /*RC*/GIMT_Encode2(AMDGPU::AV_32RegClassID),
      GIM_CheckPointerToAny, /*MI*/0, /*Op*/1, /*SizeInBits*/0,
      GIM_CheckComplexPattern, /*MI*/0, /*Op*/1, /*Renderer*/GIMT_Encode2(0), GIMT_Encode2(GICP_gi_mubuf_offset),
      // (ld:{ *:[v2f16] } (MUBUFOffset:{ *:[iPTR] } v4i32:{ *:[v4i32] }:$srsrc, i32:{ *:[i32] }:$soffset, i32:{ *:[i32] }:$offset))<<P:Predicate_unindexedload>><<P:Predicate_load_global>>  =>  (BUFFER_LOAD_DWORD_VBUFFER_OFFSET:{ *:[v2f16] } v4i32:{ *:[v4i32] }:$srsrc, i32:{ *:[i32] }:$soffset, i32:{ *:[i32] }:$offset)
      GIR_BuildMI, /*InsnID*/0, /*Opcode*/GIMT_Encode2(AMDGPU::BUFFER_LOAD_DWORD_VBUFFER_OFFSET),
      GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/0, // DstI[vdata]
      GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/0, // srsrc
      GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/1, // soffset
      GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/2, // offset
      GIR_AddImm8, /*InsnID*/0, /*Imm*/0,
      GIR_AddImm8, /*InsnID*/0, /*Imm*/0,
      GIR_MergeMemOperands, /*InsnID*/0, /*NumInsns*/1, /*MergeInsnID's*/0,
      GIR_ConstrainSelectedInstOperands, /*InsnID*/0,
      GIR_EraseFromParent, /*InsnID*/0,
      // GIR_Coverage, 3697,
      GIR_Done,
    // Label 1264: @83695
    GIM_Try, /*On fail goto*//*Label 1265*/ GIMT_Encode4(83767), // Rule ID 3699 //
      GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasUnrestrictedSOffset),
      GIM_CheckMemoryAddressSpace, /*MI*/0, /*MMO*/0, /*NumAddrSpace*/3, /*AddrSpace*/1, /*AddrSpace*/4, /*AddrSpace*/6,
      GIM_CheckAtomicOrdering, /*MI*/0, /*Order*/(uint8_t)AtomicOrdering::NotAtomic,
      GIM_CheckRegBankForClass, /*MI*/0, /*Op*/0, /*RC*/GIMT_Encode2(AMDGPU::AV_32RegClassID),
      GIM_CheckPointerToAny, /*MI*/0, /*Op*/1, /*SizeInBits*/0,
      GIM_CheckComplexPattern, /*MI*/0, /*Op*/1, /*Renderer*/GIMT_Encode2(0), GIMT_Encode2(GICP_gi_mubuf_offset),
      // (ld:{ *:[v2bf16] } (MUBUFOffset:{ *:[iPTR] } v4i32:{ *:[v4i32] }:$srsrc, i32:{ *:[i32] }:$soffset, i32:{ *:[i32] }:$offset))<<P:Predicate_unindexedload>><<P:Predicate_load_global>>  =>  (BUFFER_LOAD_DWORD_OFFSET:{ *:[v2bf16] } v4i32:{ *:[v4i32] }:$srsrc, i32:{ *:[i32] }:$soffset, i32:{ *:[i32] }:$offset)
      GIR_BuildMI, /*InsnID*/0, /*Opcode*/GIMT_Encode2(AMDGPU::BUFFER_LOAD_DWORD_OFFSET),
      GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/0, // DstI[vdata]
      GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/0, // srsrc
      GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/1, // soffset
      GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/2, // offset
      GIR_AddImm8, /*InsnID*/0, /*Imm*/0,
      GIR_AddImm8, /*InsnID*/0, /*Imm*/0,
      GIR_MergeMemOperands, /*InsnID*/0, /*NumInsns*/1, /*MergeInsnID's*/0,
      GIR_ConstrainSelectedInstOperands, /*InsnID*/0,
      GIR_EraseFromParent, /*InsnID*/0,
      // GIR_Coverage, 3699,
      GIR_Done,
    // Label 1265: @83767
    GIM_Try, /*On fail goto*//*Label 1266*/ GIMT_Encode4(83836), // Rule ID 3701 //
      GIM_CheckMemoryAddressSpace, /*MI*/0, /*MMO*/0, /*NumAddrSpace*/3, /*AddrSpace*/1, /*AddrSpace*/4, /*AddrSpace*/6,
      GIM_CheckAtomicOrdering, /*MI*/0, /*Order*/(uint8_t)AtomicOrdering::NotAtomic,
      GIM_CheckRegBankForClass, /*MI*/0, /*Op*/0, /*RC*/GIMT_Encode2(AMDGPU::AV_32RegClassID),
      GIM_CheckPointerToAny, /*MI*/0, /*Op*/1, /*SizeInBits*/0,
      GIM_CheckComplexPattern, /*MI*/0, /*Op*/1, /*Renderer*/GIMT_Encode2(0), GIMT_Encode2(GICP_gi_mubuf_offset),
      // (ld:{ *:[v2bf16] } (MUBUFOffset:{ *:[iPTR] } v4i32:{ *:[v4i32] }:$srsrc, i32:{ *:[i32] }:$soffset, i32:{ *:[i32] }:$offset))<<P:Predicate_unindexedload>><<P:Predicate_load_global>>  =>  (BUFFER_LOAD_DWORD_VBUFFER_OFFSET:{ *:[v2bf16] } v4i32:{ *:[v4i32] }:$srsrc, i32:{ *:[i32] }:$soffset, i32:{ *:[i32] }:$offset)
      GIR_BuildMI, /*InsnID*/0, /*Opcode*/GIMT_Encode2(AMDGPU::BUFFER_LOAD_DWORD_VBUFFER_OFFSET),
      GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/0, // DstI[vdata]
      GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/0, // srsrc
      GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/1, // soffset
      GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/2, // offset
      GIR_AddImm8, /*InsnID*/0, /*Imm*/0,
      GIR_AddImm8, /*InsnID*/0, /*Imm*/0,
      GIR_MergeMemOperands, /*InsnID*/0, /*NumInsns*/1, /*MergeInsnID's*/0,
      GIR_ConstrainSelectedInstOperands, /*InsnID*/0,
      GIR_EraseFromParent, /*InsnID*/0,
      // GIR_Coverage, 3701,
      GIR_Done,
    // Label 1266: @83836
    GIM_Try, /*On fail goto*//*Label 1267*/ GIMT_Encode4(83902), // Rule ID 6593 //
      GIM_CheckFeatures, GIMT_Encode2(GIFBS_LDSRequiresM0Init),
      GIM_CheckMemorySizeEqualToLLT, /*MI*/0, /*MMO*/0, /*OpIdx*/0,
      GIM_CheckMemoryAddressSpace, /*MI*/0, /*MMO*/0, /*NumAddrSpace*/1, /*AddrSpace*/3,
      GIM_CheckAtomicOrdering, /*MI*/0, /*Order*/(uint8_t)AtomicOrdering::NotAtomic,
      GIM_CheckRegBankForClass, /*MI*/0, /*Op*/0, /*RC*/GIMT_Encode2(AMDGPU::AV_32RegClassID),
      GIM_CheckPointerToAny, /*MI*/0, /*Op*/1, /*SizeInBits*/0,
      GIM_CheckComplexPattern, /*MI*/0, /*Op*/1, /*Renderer*/GIMT_Encode2(0), GIMT_Encode2(GICP_gi_ds_1addr_1offset),
      // (AMDGPUld_glue:{ *:[v2i16] } (DS1Addr1Offset:{ *:[iPTR] } i32:{ *:[i32] }:$ptr, i32:{ *:[i32] }:$offset))<<P:Predicate_unindexedload_glue>><<P:Predicate_load_glue>><<P:Predicate_load_local_m0>>  =>  (DS_READ_B32:{ *:[v2i16] } ?:{ *:[i32] }:$ptr, offset:{ *:[i32] }:$offset, 0:{ *:[i1] })
      GIR_BuildMI, /*InsnID*/0, /*Opcode*/GIMT_Encode2(AMDGPU::DS_READ_B32),
      GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/0, // DstI[vdst]
      GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/0, // ptr
      GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/1, // offset
      GIR_AddImm8, /*InsnID*/0, /*Imm*/0,
      GIR_MergeMemOperands, /*InsnID*/0, /*NumInsns*/1, /*MergeInsnID's*/0,
      GIR_ConstrainSelectedInstOperands, /*InsnID*/0,
      GIR_EraseFromParent, /*InsnID*/0,
      // GIR_Coverage, 6593,
      GIR_Done,
    // Label 1267: @83902
    GIM_Try, /*On fail goto*//*Label 1268*/ GIMT_Encode4(83968), // Rule ID 6595 //
      GIM_CheckFeatures, GIMT_Encode2(GIFBS_LDSRequiresM0Init),
      GIM_CheckMemorySizeEqualToLLT, /*MI*/0, /*MMO*/0, /*OpIdx*/0,
      GIM_CheckMemoryAddressSpace, /*MI*/0, /*MMO*/0, /*NumAddrSpace*/1, /*AddrSpace*/3,
      GIM_CheckAtomicOrdering, /*MI*/0, /*Order*/(uint8_t)AtomicOrdering::NotAtomic,
      GIM_CheckRegBankForClass, /*MI*/0, /*Op*/0, /*RC*/GIMT_Encode2(AMDGPU::AV_32RegClassID),
      GIM_CheckPointerToAny, /*MI*/0, /*Op*/1, /*SizeInBits*/0,
      GIM_CheckComplexPattern, /*MI*/0, /*Op*/1, /*Renderer*/GIMT_Encode2(0), GIMT_Encode2(GICP_gi_ds_1addr_1offset),
      // (AMDGPUld_glue:{ *:[v2f16] } (DS1Addr1Offset:{ *:[iPTR] } i32:{ *:[i32] }:$ptr, i32:{ *:[i32] }:$offset))<<P:Predicate_unindexedload_glue>><<P:Predicate_load_glue>><<P:Predicate_load_local_m0>>  =>  (DS_READ_B32:{ *:[v2f16] } ?:{ *:[i32] }:$ptr, offset:{ *:[i32] }:$offset, 0:{ *:[i1] })
      GIR_BuildMI, /*InsnID*/0, /*Opcode*/GIMT_Encode2(AMDGPU::DS_READ_B32),
      GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/0, // DstI[vdst]
      GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/0, // ptr
      GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/1, // offset
      GIR_AddImm8, /*InsnID*/0, /*Imm*/0,
      GIR_MergeMemOperands, /*InsnID*/0, /*NumInsns*/1, /*MergeInsnID's*/0,
      GIR_ConstrainSelectedInstOperands, /*InsnID*/0,
      GIR_EraseFromParent, /*InsnID*/0,
      // GIR_Coverage, 6595,
      GIR_Done,
    // Label 1268: @83968
    GIM_Try, /*On fail goto*//*Label 1269*/ GIMT_Encode4(84034), // Rule ID 6597 //
      GIM_CheckFeatures, GIMT_Encode2(GIFBS_LDSRequiresM0Init),
      GIM_CheckMemorySizeEqualToLLT, /*MI*/0, /*MMO*/0, /*OpIdx*/0,
      GIM_CheckMemoryAddressSpace, /*MI*/0, /*MMO*/0, /*NumAddrSpace*/1, /*AddrSpace*/3,
      GIM_CheckAtomicOrdering, /*MI*/0, /*Order*/(uint8_t)AtomicOrdering::NotAtomic,
      GIM_CheckRegBankForClass, /*MI*/0, /*Op*/0, /*RC*/GIMT_Encode2(AMDGPU::AV_32RegClassID),
      GIM_CheckPointerToAny, /*MI*/0, /*Op*/1, /*SizeInBits*/0,
      GIM_CheckComplexPattern, /*MI*/0, /*Op*/1, /*Renderer*/GIMT_Encode2(0), GIMT_Encode2(GICP_gi_ds_1addr_1offset),
      // (AMDGPUld_glue:{ *:[v2bf16] } (DS1Addr1Offset:{ *:[iPTR] } i32:{ *:[i32] }:$ptr, i32:{ *:[i32] }:$offset))<<P:Predicate_unindexedload_glue>><<P:Predicate_load_glue>><<P:Predicate_load_local_m0>>  =>  (DS_READ_B32:{ *:[v2bf16] } ?:{ *:[i32] }:$ptr, offset:{ *:[i32] }:$offset, 0:{ *:[i1] })
      GIR_BuildMI, /*InsnID*/0, /*Opcode*/GIMT_Encode2(AMDGPU::DS_READ_B32),
      GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/0, // DstI[vdst]
      GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/0, // ptr
      GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/1, // offset
      GIR_AddImm8, /*InsnID*/0, /*Imm*/0,
      GIR_MergeMemOperands, /*InsnID*/0, /*NumInsns*/1, /*MergeInsnID's*/0,
      GIR_ConstrainSelectedInstOperands, /*InsnID*/0,
      GIR_EraseFromParent, /*InsnID*/0,
      // GIR_Coverage, 6597,
      GIR_Done,
    // Label 1269: @84034
    GIM_Try, /*On fail goto*//*Label 1270*/ GIMT_Encode4(84096), // Rule ID 6594 //
      GIM_CheckFeatures, GIMT_Encode2(GIFBS_NotLDSRequiresM0Init),
      GIM_CheckMemoryAddressSpace, /*MI*/0, /*MMO*/0, /*NumAddrSpace*/1, /*AddrSpace*/3,
      GIM_CheckAtomicOrdering, /*MI*/0, /*Order*/(uint8_t)AtomicOrdering::NotAtomic,
      GIM_CheckRegBankForClass, /*MI*/0, /*Op*/0, /*RC*/GIMT_Encode2(AMDGPU::AV_32RegClassID),
      GIM_CheckPointerToAny, /*MI*/0, /*Op*/1, /*SizeInBits*/0,
      GIM_CheckComplexPattern, /*MI*/0, /*Op*/1, /*Renderer*/GIMT_Encode2(0), GIMT_Encode2(GICP_gi_ds_1addr_1offset),
      // (ld:{ *:[v2i16] } (DS1Addr1Offset:{ *:[iPTR] } i32:{ *:[i32] }:$ptr, i32:{ *:[i32] }:$offset))<<P:Predicate_unindexedload>><<P:Predicate_load_local>>  =>  (DS_READ_B32_gfx9:{ *:[v2i16] } ?:{ *:[i32] }:$ptr, offset:{ *:[i32] }:$offset, 0:{ *:[i1] })
      GIR_BuildMI, /*InsnID*/0, /*Opcode*/GIMT_Encode2(AMDGPU::DS_READ_B32_gfx9),
      GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/0, // DstI[vdst]
      GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/0, // ptr
      GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/1, // offset
      GIR_AddImm8, /*InsnID*/0, /*Imm*/0,
      GIR_MergeMemOperands, /*InsnID*/0, /*NumInsns*/1, /*MergeInsnID's*/0,
      GIR_ConstrainSelectedInstOperands, /*InsnID*/0,
      GIR_EraseFromParent, /*InsnID*/0,
      // GIR_Coverage, 6594,
      GIR_Done,
    // Label 1270: @84096
    GIM_Try, /*On fail goto*//*Label 1271*/ GIMT_Encode4(84158), // Rule ID 6596 //
      GIM_CheckFeatures, GIMT_Encode2(GIFBS_NotLDSRequiresM0Init),
      GIM_CheckMemoryAddressSpace, /*MI*/0, /*MMO*/0, /*NumAddrSpace*/1, /*AddrSpace*/3,
      GIM_CheckAtomicOrdering, /*MI*/0, /*Order*/(uint8_t)AtomicOrdering::NotAtomic,
      GIM_CheckRegBankForClass, /*MI*/0, /*Op*/0, /*RC*/GIMT_Encode2(AMDGPU::AV_32RegClassID),
      GIM_CheckPointerToAny, /*MI*/0, /*Op*/1, /*SizeInBits*/0,
      GIM_CheckComplexPattern, /*MI*/0, /*Op*/1, /*Renderer*/GIMT_Encode2(0), GIMT_Encode2(GICP_gi_ds_1addr_1offset),
      // (ld:{ *:[v2f16] } (DS1Addr1Offset:{ *:[iPTR] } i32:{ *:[i32] }:$ptr, i32:{ *:[i32] }:$offset))<<P:Predicate_unindexedload>><<P:Predicate_load_local>>  =>  (DS_READ_B32_gfx9:{ *:[v2f16] } ?:{ *:[i32] }:$ptr, offset:{ *:[i32] }:$offset, 0:{ *:[i1] })
      GIR_BuildMI, /*InsnID*/0, /*Opcode*/GIMT_Encode2(AMDGPU::DS_READ_B32_gfx9),
      GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/0, // DstI[vdst]
      GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/0, // ptr
      GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/1, // offset
      GIR_AddImm8, /*InsnID*/0, /*Imm*/0,
      GIR_MergeMemOperands, /*InsnID*/0, /*NumInsns*/1, /*MergeInsnID's*/0,
      GIR_ConstrainSelectedInstOperands, /*InsnID*/0,
      GIR_EraseFromParent, /*InsnID*/0,
      // GIR_Coverage, 6596,
      GIR_Done,
    // Label 1271: @84158
    GIM_Try, /*On fail goto*//*Label 1272*/ GIMT_Encode4(84220), // Rule ID 6598 //
      GIM_CheckFeatures, GIMT_Encode2(GIFBS_NotLDSRequiresM0Init),
      GIM_CheckMemoryAddressSpace, /*MI*/0, /*MMO*/0, /*NumAddrSpace*/1, /*AddrSpace*/3,
      GIM_CheckAtomicOrdering, /*MI*/0, /*Order*/(uint8_t)AtomicOrdering::NotAtomic,
      GIM_CheckRegBankForClass, /*MI*/0, /*Op*/0, /*RC*/GIMT_Encode2(AMDGPU::AV_32RegClassID),
      GIM_CheckPointerToAny, /*MI*/0, /*Op*/1, /*SizeInBits*/0,
      GIM_CheckComplexPattern, /*MI*/0, /*Op*/1, /*Renderer*/GIMT_Encode2(0), GIMT_Encode2(GICP_gi_ds_1addr_1offset),
      // (ld:{ *:[v2bf16] } (DS1Addr1Offset:{ *:[iPTR] } i32:{ *:[i32] }:$ptr, i32:{ *:[i32] }:$offset))<<P:Predicate_unindexedload>><<P:Predicate_load_local>>  =>  (DS_READ_B32_gfx9:{ *:[v2bf16] } ?:{ *:[i32] }:$ptr, offset:{ *:[i32] }:$offset, 0:{ *:[i1] })
      GIR_BuildMI, /*InsnID*/0, /*Opcode*/GIMT_Encode2(AMDGPU::DS_READ_B32_gfx9),
      GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/0, // DstI[vdst]
      GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/0, // ptr
      GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/1, // offset
      GIR_AddImm8, /*InsnID*/0, /*Imm*/0,
      GIR_MergeMemOperands, /*InsnID*/0, /*NumInsns*/1, /*MergeInsnID's*/0,
      GIR_ConstrainSelectedInstOperands, /*InsnID*/0,
      GIR_EraseFromParent, /*InsnID*/0,
      // GIR_Coverage, 6598,
      GIR_Done,
    // Label 1272: @84220
    GIM_Try, /*On fail goto*//*Label 1273*/ GIMT_Encode4(84289), // Rule ID 3001 //
      GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasFlatGlobalInsts),
      GIM_CheckMemoryAddressSpace, /*MI*/0, /*MMO*/0, /*NumAddrSpace*/3, /*AddrSpace*/1, /*AddrSpace*/4, /*AddrSpace*/6,
      GIM_CheckAtomicOrdering, /*MI*/0, /*Order*/(uint8_t)AtomicOrdering::NotAtomic,
      GIM_CheckRegBankForClass, /*MI*/0, /*Op*/0, /*RC*/GIMT_Encode2(AMDGPU::AV_32RegClassID),
      GIM_CheckPointerToAny, /*MI*/0, /*Op*/1, /*SizeInBits*/0,
      GIM_CheckComplexPattern, /*MI*/0, /*Op*/1, /*Renderer*/GIMT_Encode2(0), GIMT_Encode2(GICP_gi_global_saddr),
      // (ld:{ *:[v2i16] } (GlobalSAddr:{ *:[iPTR] } SReg_64:{ *:[i64] }:$saddr, VGPR_32:{ *:[i32] }:$voffset, i32:{ *:[i32] }:$offset))<<P:Predicate_unindexedload>><<P:Predicate_load_global>>  =>  (GLOBAL_LOAD_DWORD_SADDR:{ *:[v2i16] } ?:{ *:[i64] }:$saddr, ?:{ *:[i32] }:$voffset, ?:{ *:[i32] }:$offset, 0:{ *:[i32] })
      GIR_BuildMI, /*InsnID*/0, /*Opcode*/GIMT_Encode2(AMDGPU::GLOBAL_LOAD_DWORD_SADDR),
      GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/0, // DstI[vdst]
      GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/0, // saddr
      GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/1, // voffset
      GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/2, // offset
      GIR_AddImm8, /*InsnID*/0, /*Imm*/0,
      GIR_MergeMemOperands, /*InsnID*/0, /*NumInsns*/1, /*MergeInsnID's*/0,
      GIR_ConstrainSelectedInstOperands, /*InsnID*/0,
      GIR_EraseFromParent, /*InsnID*/0,
      // GIR_Coverage, 3001,
      GIR_Done,
    // Label 1273: @84289
    GIM_Try, /*On fail goto*//*Label 1274*/ GIMT_Encode4(84358), // Rule ID 3005 //
      GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasFlatGlobalInsts),
      GIM_CheckMemoryAddressSpace, /*MI*/0, /*MMO*/0, /*NumAddrSpace*/3, /*AddrSpace*/1, /*AddrSpace*/4, /*AddrSpace*/6,
      GIM_CheckAtomicOrdering, /*MI*/0, /*Order*/(uint8_t)AtomicOrdering::NotAtomic,
      GIM_CheckRegBankForClass, /*MI*/0, /*Op*/0, /*RC*/GIMT_Encode2(AMDGPU::AV_32RegClassID),
      GIM_CheckPointerToAny, /*MI*/0, /*Op*/1, /*SizeInBits*/0,
      GIM_CheckComplexPattern, /*MI*/0, /*Op*/1, /*Renderer*/GIMT_Encode2(0), GIMT_Encode2(GICP_gi_global_saddr),
      // (ld:{ *:[v2f16] } (GlobalSAddr:{ *:[iPTR] } SReg_64:{ *:[i64] }:$saddr, VGPR_32:{ *:[i32] }:$voffset, i32:{ *:[i32] }:$offset))<<P:Predicate_unindexedload>><<P:Predicate_load_global>>  =>  (GLOBAL_LOAD_DWORD_SADDR:{ *:[v2f16] } ?:{ *:[i64] }:$saddr, ?:{ *:[i32] }:$voffset, ?:{ *:[i32] }:$offset, 0:{ *:[i32] })
      GIR_BuildMI, /*InsnID*/0, /*Opcode*/GIMT_Encode2(AMDGPU::GLOBAL_LOAD_DWORD_SADDR),
      GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/0, // DstI[vdst]
      GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/0, // saddr
      GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/1, // voffset
      GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/2, // offset
      GIR_AddImm8, /*InsnID*/0, /*Imm*/0,
      GIR_MergeMemOperands, /*InsnID*/0, /*NumInsns*/1, /*MergeInsnID's*/0,
      GIR_ConstrainSelectedInstOperands, /*InsnID*/0,
      GIR_EraseFromParent, /*InsnID*/0,
      // GIR_Coverage, 3005,
      GIR_Done,
    // Label 1274: @84358
    GIM_Try, /*On fail goto*//*Label 1275*/ GIMT_Encode4(84427), // Rule ID 3009 //
      GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasFlatGlobalInsts),
      GIM_CheckMemoryAddressSpace, /*MI*/0, /*MMO*/0, /*NumAddrSpace*/3, /*AddrSpace*/1, /*AddrSpace*/4, /*AddrSpace*/6,
      GIM_CheckAtomicOrdering, /*MI*/0, /*Order*/(uint8_t)AtomicOrdering::NotAtomic,
      GIM_CheckRegBankForClass, /*MI*/0, /*Op*/0, /*RC*/GIMT_Encode2(AMDGPU::AV_32RegClassID),
      GIM_CheckPointerToAny, /*MI*/0, /*Op*/1, /*SizeInBits*/0,
      GIM_CheckComplexPattern, /*MI*/0, /*Op*/1, /*Renderer*/GIMT_Encode2(0), GIMT_Encode2(GICP_gi_global_saddr),
      // (ld:{ *:[v2bf16] } (GlobalSAddr:{ *:[iPTR] } SReg_64:{ *:[i64] }:$saddr, VGPR_32:{ *:[i32] }:$voffset, i32:{ *:[i32] }:$offset))<<P:Predicate_unindexedload>><<P:Predicate_load_global>>  =>  (GLOBAL_LOAD_DWORD_SADDR:{ *:[v2bf16] } ?:{ *:[i64] }:$saddr, ?:{ *:[i32] }:$voffset, ?:{ *:[i32] }:$offset, 0:{ *:[i32] })
      GIR_BuildMI, /*InsnID*/0, /*Opcode*/GIMT_Encode2(AMDGPU::GLOBAL_LOAD_DWORD_SADDR),
      GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/0, // DstI[vdst]
      GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/0, // saddr
      GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/1, // voffset
      GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/2, // offset
      GIR_AddImm8, /*InsnID*/0, /*Imm*/0,
      GIR_MergeMemOperands, /*InsnID*/0, /*NumInsns*/1, /*MergeInsnID's*/0,
      GIR_ConstrainSelectedInstOperands, /*InsnID*/0,
      GIR_EraseFromParent, /*InsnID*/0,
      // GIR_Coverage, 3009,
      GIR_Done,
    // Label 1275: @84427
    GIM_Try, /*On fail goto*//*Label 1276*/ GIMT_Encode4(84491), // Rule ID 3000 //
      GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasFlatGlobalInsts),
      GIM_CheckMemoryAddressSpace, /*MI*/0, /*MMO*/0, /*NumAddrSpace*/3, /*AddrSpace*/1, /*AddrSpace*/4, /*AddrSpace*/6,
      GIM_CheckAtomicOrdering, /*MI*/0, /*Order*/(uint8_t)AtomicOrdering::NotAtomic,
      GIM_CheckRegBankForClass, /*MI*/0, /*Op*/0, /*RC*/GIMT_Encode2(AMDGPU::AV_32RegClassID),
      GIM_CheckPointerToAny, /*MI*/0, /*Op*/1, /*SizeInBits*/0,
      GIM_CheckComplexPattern, /*MI*/0, /*Op*/1, /*Renderer*/GIMT_Encode2(0), GIMT_Encode2(GICP_gi_global_offset),
      // (ld:{ *:[v2i16] } (GlobalOffset:{ *:[iPTR] } VReg_64:{ *:[i64] }:$vaddr, i32:{ *:[i32] }:$offset))<<P:Predicate_unindexedload>><<P:Predicate_load_global>>  =>  (GLOBAL_LOAD_DWORD:{ *:[v2i16] } ?:{ *:[i64] }:$vaddr, ?:{ *:[i32] }:$offset)
      GIR_BuildMI, /*InsnID*/0, /*Opcode*/GIMT_Encode2(AMDGPU::GLOBAL_LOAD_DWORD),
      GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/0, // DstI[vdst]
      GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/0, // vaddr
      GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/1, // offset
      GIR_AddImm8, /*InsnID*/0, /*Imm*/0,
      GIR_MergeMemOperands, /*InsnID*/0, /*NumInsns*/1, /*MergeInsnID's*/0,
      GIR_ConstrainSelectedInstOperands, /*InsnID*/0,
      GIR_EraseFromParent, /*InsnID*/0,
      // GIR_Coverage, 3000,
      GIR_Done,
    // Label 1276: @84491
    GIM_Try, /*On fail goto*//*Label 1277*/ GIMT_Encode4(84555), // Rule ID 3004 //
      GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasFlatGlobalInsts),
      GIM_CheckMemoryAddressSpace, /*MI*/0, /*MMO*/0, /*NumAddrSpace*/3, /*AddrSpace*/1, /*AddrSpace*/4, /*AddrSpace*/6,
      GIM_CheckAtomicOrdering, /*MI*/0, /*Order*/(uint8_t)AtomicOrdering::NotAtomic,
      GIM_CheckRegBankForClass, /*MI*/0, /*Op*/0, /*RC*/GIMT_Encode2(AMDGPU::AV_32RegClassID),
      GIM_CheckPointerToAny, /*MI*/0, /*Op*/1, /*SizeInBits*/0,
      GIM_CheckComplexPattern, /*MI*/0, /*Op*/1, /*Renderer*/GIMT_Encode2(0), GIMT_Encode2(GICP_gi_global_offset),
      // (ld:{ *:[v2f16] } (GlobalOffset:{ *:[iPTR] } VReg_64:{ *:[i64] }:$vaddr, i32:{ *:[i32] }:$offset))<<P:Predicate_unindexedload>><<P:Predicate_load_global>>  =>  (GLOBAL_LOAD_DWORD:{ *:[v2f16] } ?:{ *:[i64] }:$vaddr, ?:{ *:[i32] }:$offset)
      GIR_BuildMI, /*InsnID*/0, /*Opcode*/GIMT_Encode2(AMDGPU::GLOBAL_LOAD_DWORD),
      GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/0, // DstI[vdst]
      GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/0, // vaddr
      GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/1, // offset
      GIR_AddImm8, /*InsnID*/0, /*Imm*/0,
      GIR_MergeMemOperands, /*InsnID*/0, /*NumInsns*/1, /*MergeInsnID's*/0,
      GIR_ConstrainSelectedInstOperands, /*InsnID*/0,
      GIR_EraseFromParent, /*InsnID*/0,
      // GIR_Coverage, 3004,
      GIR_Done,
    // Label 1277: @84555
    GIM_Try, /*On fail goto*//*Label 1278*/ GIMT_Encode4(84619), // Rule ID 3008 //
      GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasFlatGlobalInsts),
      GIM_CheckMemoryAddressSpace, /*MI*/0, /*MMO*/0, /*NumAddrSpace*/3, /*AddrSpace*/1, /*AddrSpace*/4, /*AddrSpace*/6,
      GIM_CheckAtomicOrdering, /*MI*/0, /*Order*/(uint8_t)AtomicOrdering::NotAtomic,
      GIM_CheckRegBankForClass, /*MI*/0, /*Op*/0, /*RC*/GIMT_Encode2(AMDGPU::AV_32RegClassID),
      GIM_CheckPointerToAny, /*MI*/0, /*Op*/1, /*SizeInBits*/0,
      GIM_CheckComplexPattern, /*MI*/0, /*Op*/1, /*Renderer*/GIMT_Encode2(0), GIMT_Encode2(GICP_gi_global_offset),
      // (ld:{ *:[v2bf16] } (GlobalOffset:{ *:[iPTR] } VReg_64:{ *:[i64] }:$vaddr, i32:{ *:[i32] }:$offset))<<P:Predicate_unindexedload>><<P:Predicate_load_global>>  =>  (GLOBAL_LOAD_DWORD:{ *:[v2bf16] } ?:{ *:[i64] }:$vaddr, ?:{ *:[i32] }:$offset)
      GIR_BuildMI, /*InsnID*/0, /*Opcode*/GIMT_Encode2(AMDGPU::GLOBAL_LOAD_DWORD),
      GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/0, // DstI[vdst]
      GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/0, // vaddr
      GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/1, // offset
      GIR_AddImm8, /*InsnID*/0, /*Imm*/0,
      GIR_MergeMemOperands, /*InsnID*/0, /*NumInsns*/1, /*MergeInsnID's*/0,
      GIR_ConstrainSelectedInstOperands, /*InsnID*/0,
      GIR_EraseFromParent, /*InsnID*/0,
      // GIR_Coverage, 3008,
      GIR_Done,
    // Label 1278: @84619
    GIM_Try, /*On fail goto*//*Label 1279*/ GIMT_Encode4(84684), // Rule ID 2774 //
      GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasFlatAddressSpace),
      GIM_CheckMemoryAddressSpace, /*MI*/0, /*MMO*/0, /*NumAddrSpace*/4, /*AddrSpace*/0, /*AddrSpace*/1, /*AddrSpace*/4, /*AddrSpace*/6,
      GIM_CheckAtomicOrdering, /*MI*/0, /*Order*/(uint8_t)AtomicOrdering::NotAtomic,
      GIM_CheckRegBankForClass, /*MI*/0, /*Op*/0, /*RC*/GIMT_Encode2(AMDGPU::AV_32RegClassID),
      GIM_CheckPointerToAny, /*MI*/0, /*Op*/1, /*SizeInBits*/0,
      GIM_CheckComplexPattern, /*MI*/0, /*Op*/1, /*Renderer*/GIMT_Encode2(0), GIMT_Encode2(GICP_gi_flat_offset),
      // (ld:{ *:[v2i16] } (FlatOffset:{ *:[iPTR] } i64:{ *:[i64] }:$vaddr, i32:{ *:[i32] }:$offset))<<P:Predicate_unindexedload>><<P:Predicate_load_flat>>  =>  (FLAT_LOAD_DWORD:{ *:[v2i16] } ?:{ *:[i64] }:$vaddr, ?:{ *:[i32] }:$offset)
      GIR_BuildMI, /*InsnID*/0, /*Opcode*/GIMT_Encode2(AMDGPU::FLAT_LOAD_DWORD),
      GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/0, // DstI[vdst]
      GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/0, // vaddr
      GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/1, // offset
      GIR_AddImm8, /*InsnID*/0, /*Imm*/0,
      GIR_MergeMemOperands, /*InsnID*/0, /*NumInsns*/1, /*MergeInsnID's*/0,
      GIR_ConstrainSelectedInstOperands, /*InsnID*/0,
      GIR_EraseFromParent, /*InsnID*/0,
      // GIR_Coverage, 2774,
      GIR_Done,
    // Label 1279: @84684
    GIM_Try, /*On fail goto*//*Label 1280*/ GIMT_Encode4(84749), // Rule ID 2776 //
      GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasFlatAddressSpace),
      GIM_CheckMemoryAddressSpace, /*MI*/0, /*MMO*/0, /*NumAddrSpace*/4, /*AddrSpace*/0, /*AddrSpace*/1, /*AddrSpace*/4, /*AddrSpace*/6,
      GIM_CheckAtomicOrdering, /*MI*/0, /*Order*/(uint8_t)AtomicOrdering::NotAtomic,
      GIM_CheckRegBankForClass, /*MI*/0, /*Op*/0, /*RC*/GIMT_Encode2(AMDGPU::AV_32RegClassID),
      GIM_CheckPointerToAny, /*MI*/0, /*Op*/1, /*SizeInBits*/0,
      GIM_CheckComplexPattern, /*MI*/0, /*Op*/1, /*Renderer*/GIMT_Encode2(0), GIMT_Encode2(GICP_gi_flat_offset),
      // (ld:{ *:[v2f16] } (FlatOffset:{ *:[iPTR] } i64:{ *:[i64] }:$vaddr, i32:{ *:[i32] }:$offset))<<P:Predicate_unindexedload>><<P:Predicate_load_flat>>  =>  (FLAT_LOAD_DWORD:{ *:[v2f16] } ?:{ *:[i64] }:$vaddr, ?:{ *:[i32] }:$offset)
      GIR_BuildMI, /*InsnID*/0, /*Opcode*/GIMT_Encode2(AMDGPU::FLAT_LOAD_DWORD),
      GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/0, // DstI[vdst]
      GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/0, // vaddr
      GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/1, // offset
      GIR_AddImm8, /*InsnID*/0, /*Imm*/0,
      GIR_MergeMemOperands, /*InsnID*/0, /*NumInsns*/1, /*MergeInsnID's*/0,
      GIR_ConstrainSelectedInstOperands, /*InsnID*/0,
      GIR_EraseFromParent, /*InsnID*/0,
      // GIR_Coverage, 2776,
      GIR_Done,
    // Label 1280: @84749
    GIM_Try, /*On fail goto*//*Label 1281*/ GIMT_Encode4(84814), // Rule ID 2778 //
      GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasFlatAddressSpace),
      GIM_CheckMemoryAddressSpace, /*MI*/0, /*MMO*/0, /*NumAddrSpace*/4, /*AddrSpace*/0, /*AddrSpace*/1, /*AddrSpace*/4, /*AddrSpace*/6,
      GIM_CheckAtomicOrdering, /*MI*/0, /*Order*/(uint8_t)AtomicOrdering::NotAtomic,
      GIM_CheckRegBankForClass, /*MI*/0, /*Op*/0, /*RC*/GIMT_Encode2(AMDGPU::AV_32RegClassID),
      GIM_CheckPointerToAny, /*MI*/0, /*Op*/1, /*SizeInBits*/0,
      GIM_CheckComplexPattern, /*MI*/0, /*Op*/1, /*Renderer*/GIMT_Encode2(0), GIMT_Encode2(GICP_gi_flat_offset),
      // (ld:{ *:[v2bf16] } (FlatOffset:{ *:[iPTR] } i64:{ *:[i64] }:$vaddr, i32:{ *:[i32] }:$offset))<<P:Predicate_unindexedload>><<P:Predicate_load_flat>>  =>  (FLAT_LOAD_DWORD:{ *:[v2bf16] } ?:{ *:[i64] }:$vaddr, ?:{ *:[i32] }:$offset)
      GIR_BuildMI, /*InsnID*/0, /*Opcode*/GIMT_Encode2(AMDGPU::FLAT_LOAD_DWORD),
      GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/0, // DstI[vdst]
      GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/0, // vaddr
      GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/1, // offset
      GIR_AddImm8, /*InsnID*/0, /*Imm*/0,
      GIR_MergeMemOperands, /*InsnID*/0, /*NumInsns*/1, /*MergeInsnID's*/0,
      GIR_ConstrainSelectedInstOperands, /*InsnID*/0,
      GIR_EraseFromParent, /*InsnID*/0,
      // GIR_Coverage, 2778,
      GIR_Done,
    // Label 1281: @84814
    GIM_Reject,
    // Label 828: @84815
    GIM_Try, /*On fail goto*//*Label 1282*/ GIMT_Encode4(84885), // Rule ID 2504 //
      GIM_CheckFeatures, GIMT_Encode2(GIFBS_isGFX9Plus),
      GIM_CheckMemorySizeEqualToLLT, /*MI*/0, /*MMO*/0, /*OpIdx*/0,
      GIM_CheckAtomicOrdering, /*MI*/0, /*Order*/(uint8_t)AtomicOrdering::NotAtomic,
      GIM_CheckRegBankForClass, /*MI*/0, /*Op*/0, /*RC*/GIMT_Encode2(AMDGPU::SReg_64_XEXECRegClassID),
      GIM_CheckPointerToAny, /*MI*/0, /*Op*/1, /*SizeInBits*/0,
      GIM_CheckCxxInsnPredicate, /*MI*/0, /*FnId*/GIMT_Encode2(GICXXPred_MI_Predicate_smrd_load),
      GIM_CheckComplexPattern, /*MI*/0, /*Op*/1, /*Renderer*/GIMT_Encode2(0), GIMT_Encode2(GICP_gi_smrd_sgpr_imm),
      // (ld:{ *:[v2i32] } (SMRDSgprImm:{ *:[iPTR] } i64:{ *:[i64] }:$sbase, i32:{ *:[i32] }:$soffset, i32:{ *:[i32] }:$offset))<<P:Predicate_unindexedload>><<P:Predicate_load>><<P:Predicate_smrd_load>>  =>  (S_LOAD_DWORDX2_SGPR_IMM:{ *:[v2i32] } ?:{ *:[i64] }:$sbase, ?:{ *:[i32] }:$soffset, ?:{ *:[i32] }:$offset, 0:{ *:[i32] })
      GIR_BuildMI, /*InsnID*/0, /*Opcode*/GIMT_Encode2(AMDGPU::S_LOAD_DWORDX2_SGPR_IMM),
      GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/0, // DstI[sdst]
      GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/0, // sbase
      GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/1, // soffset
      GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/2, // offset
      GIR_AddImm8, /*InsnID*/0, /*Imm*/0,
      GIR_MergeMemOperands, /*InsnID*/0, /*NumInsns*/1, /*MergeInsnID's*/0,
      GIR_ConstrainSelectedInstOperands, /*InsnID*/0,
      GIR_EraseFromParent, /*InsnID*/0,
      // GIR_Coverage, 2504,
      GIR_Done,
    // Label 1282: @84885
    GIM_Try, /*On fail goto*//*Label 1283*/ GIMT_Encode4(84955), // Rule ID 2516 //
      GIM_CheckFeatures, GIMT_Encode2(GIFBS_isGFX9Plus),
      GIM_CheckMemorySizeEqualToLLT, /*MI*/0, /*MMO*/0, /*OpIdx*/0,
      GIM_CheckAtomicOrdering, /*MI*/0, /*Order*/(uint8_t)AtomicOrdering::NotAtomic,
      GIM_CheckRegBankForClass, /*MI*/0, /*Op*/0, /*RC*/GIMT_Encode2(AMDGPU::SReg_64_XEXECRegClassID),
      GIM_CheckPointerToAny, /*MI*/0, /*Op*/1, /*SizeInBits*/0,
      GIM_CheckCxxInsnPredicate, /*MI*/0, /*FnId*/GIMT_Encode2(GICXXPred_MI_Predicate_smrd_load),
      GIM_CheckComplexPattern, /*MI*/0, /*Op*/1, /*Renderer*/GIMT_Encode2(0), GIMT_Encode2(GICP_gi_smrd_sgpr_imm),
      // (ld:{ *:[v2f32] } (SMRDSgprImm:{ *:[iPTR] } i64:{ *:[i64] }:$sbase, i32:{ *:[i32] }:$soffset, i32:{ *:[i32] }:$offset))<<P:Predicate_unindexedload>><<P:Predicate_load>><<P:Predicate_smrd_load>>  =>  (S_LOAD_DWORDX2_SGPR_IMM:{ *:[v2f32] } ?:{ *:[i64] }:$sbase, ?:{ *:[i32] }:$soffset, ?:{ *:[i32] }:$offset, 0:{ *:[i32] })
      GIR_BuildMI, /*InsnID*/0, /*Opcode*/GIMT_Encode2(AMDGPU::S_LOAD_DWORDX2_SGPR_IMM),
      GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/0, // DstI[sdst]
      GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/0, // sbase
      GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/1, // soffset
      GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/2, // offset
      GIR_AddImm8, /*InsnID*/0, /*Imm*/0,
      GIR_MergeMemOperands, /*InsnID*/0, /*NumInsns*/1, /*MergeInsnID's*/0,
      GIR_ConstrainSelectedInstOperands, /*InsnID*/0,
      GIR_EraseFromParent, /*InsnID*/0,
      // GIR_Coverage, 2516,
      GIR_Done,
    // Label 1283: @84955
    GIM_Try, /*On fail goto*//*Label 1284*/ GIMT_Encode4(85030), // Rule ID 6823 //
      GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasUnalignedAccessMode_LDSRequiresM0Init),
      GIM_CheckMemorySizeEqualToLLT, /*MI*/0, /*MMO*/0, /*OpIdx*/0,
      GIM_CheckMemoryAddressSpace, /*MI*/0, /*MMO*/0, /*NumAddrSpace*/1, /*AddrSpace*/3,
      GIM_CheckMemoryAddressSpace, /*MI*/0, /*MMO*/0, /*NumAddrSpace*/1, /*AddrSpace*/3,
      GIM_CheckAtomicOrdering, /*MI*/0, /*Order*/(uint8_t)AtomicOrdering::NotAtomic,
      GIM_CheckRegBankForClass, /*MI*/0, /*Op*/0, /*RC*/GIMT_Encode2(AMDGPU::AV_64RegClassID),
      GIM_CheckPointerToAny, /*MI*/0, /*Op*/1, /*SizeInBits*/0,
      GIM_CheckCxxInsnPredicate, /*MI*/0, /*FnId*/GIMT_Encode2(GICXXPred_MI_Predicate_load_align_less_than_4_local_m0),
      GIM_CheckComplexPattern, /*MI*/0, /*Op*/1, /*Renderer*/GIMT_Encode2(0), GIMT_Encode2(GICP_gi_ds_1addr_1offset),
      // (AMDGPUld_glue:{ *:[v2i32] } (DS1Addr1Offset:{ *:[iPTR] } i32:{ *:[i32] }:$ptr, i32:{ *:[i32] }:$offset))<<P:Predicate_unindexedload_glue>><<P:Predicate_load_glue>><<P:Predicate_load_local_m0>><<P:Predicate_load_align_less_than_4_local_m0>>  =>  (DS_READ_B64:{ *:[v2i32] } ?:{ *:[i32] }:$ptr, offset:{ *:[i32] }:$offset, 0:{ *:[i1] })
      GIR_BuildMI, /*InsnID*/0, /*Opcode*/GIMT_Encode2(AMDGPU::DS_READ_B64),
      GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/0, // DstI[vdst]
      GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/0, // ptr
      GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/1, // offset
      GIR_AddImm8, /*InsnID*/0, /*Imm*/0,
      GIR_MergeMemOperands, /*InsnID*/0, /*NumInsns*/1, /*MergeInsnID's*/0,
      GIR_ConstrainSelectedInstOperands, /*InsnID*/0,
      GIR_EraseFromParent, /*InsnID*/0,
      // GIR_Coverage, 6823,
      GIR_Done,
    // Label 1284: @85030
    GIM_Try, /*On fail goto*//*Label 1285*/ GIMT_Encode4(85105), // Rule ID 6827 //
      GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasUnalignedAccessMode_LDSRequiresM0Init),
      GIM_CheckMemorySizeEqualToLLT, /*MI*/0, /*MMO*/0, /*OpIdx*/0,
      GIM_CheckMemoryAddressSpace, /*MI*/0, /*MMO*/0, /*NumAddrSpace*/1, /*AddrSpace*/3,
      GIM_CheckMemoryAddressSpace, /*MI*/0, /*MMO*/0, /*NumAddrSpace*/1, /*AddrSpace*/3,
      GIM_CheckAtomicOrdering, /*MI*/0, /*Order*/(uint8_t)AtomicOrdering::NotAtomic,
      GIM_CheckRegBankForClass, /*MI*/0, /*Op*/0, /*RC*/GIMT_Encode2(AMDGPU::AV_64RegClassID),
      GIM_CheckPointerToAny, /*MI*/0, /*Op*/1, /*SizeInBits*/0,
      GIM_CheckCxxInsnPredicate, /*MI*/0, /*FnId*/GIMT_Encode2(GICXXPred_MI_Predicate_load_align_less_than_4_local_m0),
      GIM_CheckComplexPattern, /*MI*/0, /*Op*/1, /*Renderer*/GIMT_Encode2(0), GIMT_Encode2(GICP_gi_ds_1addr_1offset),
      // (AMDGPUld_glue:{ *:[v2f32] } (DS1Addr1Offset:{ *:[iPTR] } i32:{ *:[i32] }:$ptr, i32:{ *:[i32] }:$offset))<<P:Predicate_unindexedload_glue>><<P:Predicate_load_glue>><<P:Predicate_load_local_m0>><<P:Predicate_load_align_less_than_4_local_m0>>  =>  (DS_READ_B64:{ *:[v2f32] } ?:{ *:[i32] }:$ptr, offset:{ *:[i32] }:$offset, 0:{ *:[i1] })
      GIR_BuildMI, /*InsnID*/0, /*Opcode*/GIMT_Encode2(AMDGPU::DS_READ_B64),
      GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/0, // DstI[vdst]
      GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/0, // ptr
      GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/1, // offset
      GIR_AddImm8, /*InsnID*/0, /*Imm*/0,
      GIR_MergeMemOperands, /*InsnID*/0, /*NumInsns*/1, /*MergeInsnID's*/0,
      GIR_ConstrainSelectedInstOperands, /*InsnID*/0,
      GIR_EraseFromParent, /*InsnID*/0,
      // GIR_Coverage, 6827,
      GIR_Done,
    // Label 1285: @85105
    GIM_Try, /*On fail goto*//*Label 1286*/ GIMT_Encode4(85175), // Rule ID 6747 //
      GIM_CheckFeatures, GIMT_Encode2(GIFBS_LDSRequiresM0Init),
      GIM_CheckMemorySizeEqualToLLT, /*MI*/0, /*MMO*/0, /*OpIdx*/0,
      GIM_CheckMemoryAddressSpace, /*MI*/0, /*MMO*/0, /*NumAddrSpace*/1, /*AddrSpace*/3,
      GIM_CheckMemoryAlignment, /*MI*/0, /*MMO*/0, /*MinAlign*/8,
      GIM_CheckAtomicOrdering, /*MI*/0, /*Order*/(uint8_t)AtomicOrdering::NotAtomic,
      GIM_CheckRegBankForClass, /*MI*/0, /*Op*/0, /*RC*/GIMT_Encode2(AMDGPU::AV_64RegClassID),
      GIM_CheckPointerToAny, /*MI*/0, /*Op*/1, /*SizeInBits*/0,
      GIM_CheckComplexPattern, /*MI*/0, /*Op*/1, /*Renderer*/GIMT_Encode2(0), GIMT_Encode2(GICP_gi_ds_1addr_1offset),
      // (AMDGPUld_glue:{ *:[v2i32] } (DS1Addr1Offset:{ *:[iPTR] } i32:{ *:[i32] }:$ptr, i32:{ *:[i32] }:$offset))<<P:Predicate_unindexedload_glue>><<P:Predicate_load_glue>><<P:Predicate_load_local_m0>><<P:Predicate_load_align8_local_m0>>  =>  (DS_READ_B64:{ *:[v2i32] } ?:{ *:[i32] }:$ptr, offset:{ *:[i32] }:$offset, 0:{ *:[i1] })
      GIR_BuildMI, /*InsnID*/0, /*Opcode*/GIMT_Encode2(AMDGPU::DS_READ_B64),
      GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/0, // DstI[vdst]
      GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/0, // ptr
      GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/1, // offset
      GIR_AddImm8, /*InsnID*/0, /*Imm*/0,
      GIR_MergeMemOperands, /*InsnID*/0, /*NumInsns*/1, /*MergeInsnID's*/0,
      GIR_ConstrainSelectedInstOperands, /*InsnID*/0,
      GIR_EraseFromParent, /*InsnID*/0,
      // GIR_Coverage, 6747,
      GIR_Done,
    // Label 1286: @85175
    GIM_Try, /*On fail goto*//*Label 1287*/ GIMT_Encode4(85245), // Rule ID 6751 //
      GIM_CheckFeatures, GIMT_Encode2(GIFBS_LDSRequiresM0Init),
      GIM_CheckMemorySizeEqualToLLT, /*MI*/0, /*MMO*/0, /*OpIdx*/0,
      GIM_CheckMemoryAddressSpace, /*MI*/0, /*MMO*/0, /*NumAddrSpace*/1, /*AddrSpace*/3,
      GIM_CheckMemoryAlignment, /*MI*/0, /*MMO*/0, /*MinAlign*/8,
      GIM_CheckAtomicOrdering, /*MI*/0, /*Order*/(uint8_t)AtomicOrdering::NotAtomic,
      GIM_CheckRegBankForClass, /*MI*/0, /*Op*/0, /*RC*/GIMT_Encode2(AMDGPU::AV_64RegClassID),
      GIM_CheckPointerToAny, /*MI*/0, /*Op*/1, /*SizeInBits*/0,
      GIM_CheckComplexPattern, /*MI*/0, /*Op*/1, /*Renderer*/GIMT_Encode2(0), GIMT_Encode2(GICP_gi_ds_1addr_1offset),
      // (AMDGPUld_glue:{ *:[v2f32] } (DS1Addr1Offset:{ *:[iPTR] } i32:{ *:[i32] }:$ptr, i32:{ *:[i32] }:$offset))<<P:Predicate_unindexedload_glue>><<P:Predicate_load_glue>><<P:Predicate_load_local_m0>><<P:Predicate_load_align8_local_m0>>  =>  (DS_READ_B64:{ *:[v2f32] } ?:{ *:[i32] }:$ptr, offset:{ *:[i32] }:$offset, 0:{ *:[i1] })
      GIR_BuildMI, /*InsnID*/0, /*Opcode*/GIMT_Encode2(AMDGPU::DS_READ_B64),
      GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/0, // DstI[vdst]
      GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/0, // ptr
      GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/1, // offset
      GIR_AddImm8, /*InsnID*/0, /*Imm*/0,
      GIR_MergeMemOperands, /*InsnID*/0, /*NumInsns*/1, /*MergeInsnID's*/0,
      GIR_ConstrainSelectedInstOperands, /*InsnID*/0,
      GIR_EraseFromParent, /*InsnID*/0,
      // GIR_Coverage, 6751,
      GIR_Done,
    // Label 1287: @85245
    GIM_Try, /*On fail goto*//*Label 1288*/ GIMT_Encode4(85307), // Rule ID 2500 //
      GIM_CheckMemorySizeEqualToLLT, /*MI*/0, /*MMO*/0, /*OpIdx*/0,
      GIM_CheckAtomicOrdering, /*MI*/0, /*Order*/(uint8_t)AtomicOrdering::NotAtomic,
      GIM_CheckRegBankForClass, /*MI*/0, /*Op*/0, /*RC*/GIMT_Encode2(AMDGPU::SReg_64_XEXECRegClassID),
      GIM_CheckPointerToAny, /*MI*/0, /*Op*/1, /*SizeInBits*/0,
      GIM_CheckCxxInsnPredicate, /*MI*/0, /*FnId*/GIMT_Encode2(GICXXPred_MI_Predicate_smrd_load),
      GIM_CheckComplexPattern, /*MI*/0, /*Op*/1, /*Renderer*/GIMT_Encode2(0), GIMT_Encode2(GICP_gi_smrd_imm),
      // (ld:{ *:[v2i32] } (SMRDImm:{ *:[iPTR] } i64:{ *:[i64] }:$sbase, i32:{ *:[i32] }:$offset))<<P:Predicate_unindexedload>><<P:Predicate_load>><<P:Predicate_smrd_load>>  =>  (S_LOAD_DWORDX2_IMM:{ *:[v2i32] } ?:{ *:[i64] }:$sbase, ?:{ *:[i32] }:$offset, 0:{ *:[i32] })
      GIR_BuildMI, /*InsnID*/0, /*Opcode*/GIMT_Encode2(AMDGPU::S_LOAD_DWORDX2_IMM),
      GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/0, // DstI[sdst]
      GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/0, // sbase
      GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/1, // offset
      GIR_AddImm8, /*InsnID*/0, /*Imm*/0,
      GIR_MergeMemOperands, /*InsnID*/0, /*NumInsns*/1, /*MergeInsnID's*/0,
      GIR_ConstrainSelectedInstOperands, /*InsnID*/0,
      GIR_EraseFromParent, /*InsnID*/0,
      // GIR_Coverage, 2500,
      GIR_Done,
    // Label 1288: @85307
    GIM_Try, /*On fail goto*//*Label 1289*/ GIMT_Encode4(85372), // Rule ID 2501 //
      GIM_CheckFeatures, GIMT_Encode2(GIFBS_isGFX7Only),
      GIM_CheckMemorySizeEqualToLLT, /*MI*/0, /*MMO*/0, /*OpIdx*/0,
      GIM_CheckAtomicOrdering, /*MI*/0, /*Order*/(uint8_t)AtomicOrdering::NotAtomic,
      GIM_CheckRegBankForClass, /*MI*/0, /*Op*/0, /*RC*/GIMT_Encode2(AMDGPU::SReg_64_XEXECRegClassID),
      GIM_CheckPointerToAny, /*MI*/0, /*Op*/1, /*SizeInBits*/0,
      GIM_CheckCxxInsnPredicate, /*MI*/0, /*FnId*/GIMT_Encode2(GICXXPred_MI_Predicate_smrd_load),
      GIM_CheckComplexPattern, /*MI*/0, /*Op*/1, /*Renderer*/GIMT_Encode2(0), GIMT_Encode2(GICP_gi_smrd_imm32),
      // (ld:{ *:[v2i32] } (SMRDImm32:{ *:[iPTR] } i64:{ *:[i64] }:$sbase, i32:{ *:[i32] }:$offset))<<P:Predicate_unindexedload>><<P:Predicate_load>><<P:Predicate_smrd_load>>  =>  (S_LOAD_DWORDX2_IMM_ci:{ *:[v2i32] } ?:{ *:[i64] }:$sbase, ?:{ *:[i32] }:$offset, 0:{ *:[i32] })
      GIR_BuildMI, /*InsnID*/0, /*Opcode*/GIMT_Encode2(AMDGPU::S_LOAD_DWORDX2_IMM_ci),
      GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/0, // DstI[sdst]
      GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/0, // sbase
      GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/1, // offset
      GIR_AddImm8, /*InsnID*/0, /*Imm*/0,
      GIR_MergeMemOperands, /*InsnID*/0, /*NumInsns*/1, /*MergeInsnID's*/0,
      GIR_ConstrainSelectedInstOperands, /*InsnID*/0,
      GIR_EraseFromParent, /*InsnID*/0,
      // GIR_Coverage, 2501,
      GIR_Done,
    // Label 1289: @85372
    GIM_Try, /*On fail goto*//*Label 1290*/ GIMT_Encode4(85437), // Rule ID 2502 //
      GIM_CheckFeatures, GIMT_Encode2(GIFBS_isNotGFX9Plus),
      GIM_CheckMemorySizeEqualToLLT, /*MI*/0, /*MMO*/0, /*OpIdx*/0,
      GIM_CheckAtomicOrdering, /*MI*/0, /*Order*/(uint8_t)AtomicOrdering::NotAtomic,
      GIM_CheckRegBankForClass, /*MI*/0, /*Op*/0, /*RC*/GIMT_Encode2(AMDGPU::SReg_64_XEXECRegClassID),
      GIM_CheckPointerToAny, /*MI*/0, /*Op*/1, /*SizeInBits*/0,
      GIM_CheckCxxInsnPredicate, /*MI*/0, /*FnId*/GIMT_Encode2(GICXXPred_MI_Predicate_smrd_load),
      GIM_CheckComplexPattern, /*MI*/0, /*Op*/1, /*Renderer*/GIMT_Encode2(0), GIMT_Encode2(GICP_gi_smrd_sgpr),
      // (ld:{ *:[v2i32] } (SMRDSgpr:{ *:[iPTR] } i64:{ *:[i64] }:$sbase, i32:{ *:[i32] }:$soffset))<<P:Predicate_unindexedload>><<P:Predicate_load>><<P:Predicate_smrd_load>>  =>  (S_LOAD_DWORDX2_SGPR:{ *:[v2i32] } ?:{ *:[i64] }:$sbase, ?:{ *:[i32] }:$soffset, 0:{ *:[i32] })
      GIR_BuildMI, /*InsnID*/0, /*Opcode*/GIMT_Encode2(AMDGPU::S_LOAD_DWORDX2_SGPR),
      GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/0, // DstI[sdst]
      GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/0, // sbase
      GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/1, // soffset
      GIR_AddImm8, /*InsnID*/0, /*Imm*/0,
      GIR_MergeMemOperands, /*InsnID*/0, /*NumInsns*/1, /*MergeInsnID's*/0,
      GIR_ConstrainSelectedInstOperands, /*InsnID*/0,
      GIR_EraseFromParent, /*InsnID*/0,
      // GIR_Coverage, 2502,
      GIR_Done,
    // Label 1290: @85437
    GIM_Try, /*On fail goto*//*Label 1291*/ GIMT_Encode4(85505), // Rule ID 2503 //
      GIM_CheckFeatures, GIMT_Encode2(GIFBS_isGFX9Plus),
      GIM_CheckMemorySizeEqualToLLT, /*MI*/0, /*MMO*/0, /*OpIdx*/0,
      GIM_CheckAtomicOrdering, /*MI*/0, /*Order*/(uint8_t)AtomicOrdering::NotAtomic,
      GIM_CheckRegBankForClass, /*MI*/0, /*Op*/0, /*RC*/GIMT_Encode2(AMDGPU::SReg_64_XEXECRegClassID),
      GIM_CheckPointerToAny, /*MI*/0, /*Op*/1, /*SizeInBits*/0,
      GIM_CheckCxxInsnPredicate, /*MI*/0, /*FnId*/GIMT_Encode2(GICXXPred_MI_Predicate_smrd_load),
      GIM_CheckComplexPattern, /*MI*/0, /*Op*/1, /*Renderer*/GIMT_Encode2(0), GIMT_Encode2(GICP_gi_smrd_sgpr),
      // (ld:{ *:[v2i32] } (SMRDSgpr:{ *:[iPTR] } i64:{ *:[i64] }:$sbase, i32:{ *:[i32] }:$soffset))<<P:Predicate_unindexedload>><<P:Predicate_load>><<P:Predicate_smrd_load>>  =>  (S_LOAD_DWORDX2_SGPR_IMM:{ *:[v2i32] } ?:{ *:[i64] }:$sbase, ?:{ *:[i32] }:$soffset, 0:{ *:[i32] }, 0:{ *:[i32] })
      GIR_BuildMI, /*InsnID*/0, /*Opcode*/GIMT_Encode2(AMDGPU::S_LOAD_DWORDX2_SGPR_IMM),
      GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/0, // DstI[sdst]
      GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/0, // sbase
      GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/1, // soffset
      GIR_AddImm8, /*InsnID*/0, /*Imm*/0,
      GIR_AddImm8, /*InsnID*/0, /*Imm*/0,
      GIR_MergeMemOperands, /*InsnID*/0, /*NumInsns*/1, /*MergeInsnID's*/0,
      GIR_ConstrainSelectedInstOperands, /*InsnID*/0,
      GIR_EraseFromParent, /*InsnID*/0,
      // GIR_Coverage, 2503,
      GIR_Done,
    // Label 1291: @85505
    GIM_Try, /*On fail goto*//*Label 1292*/ GIMT_Encode4(85567), // Rule ID 2512 //
      GIM_CheckMemorySizeEqualToLLT, /*MI*/0, /*MMO*/0, /*OpIdx*/0,
      GIM_CheckAtomicOrdering, /*MI*/0, /*Order*/(uint8_t)AtomicOrdering::NotAtomic,
      GIM_CheckRegBankForClass, /*MI*/0, /*Op*/0, /*RC*/GIMT_Encode2(AMDGPU::SReg_64_XEXECRegClassID),
      GIM_CheckPointerToAny, /*MI*/0, /*Op*/1, /*SizeInBits*/0,
      GIM_CheckCxxInsnPredicate, /*MI*/0, /*FnId*/GIMT_Encode2(GICXXPred_MI_Predicate_smrd_load),
      GIM_CheckComplexPattern, /*MI*/0, /*Op*/1, /*Renderer*/GIMT_Encode2(0), GIMT_Encode2(GICP_gi_smrd_imm),
      // (ld:{ *:[v2f32] } (SMRDImm:{ *:[iPTR] } i64:{ *:[i64] }:$sbase, i32:{ *:[i32] }:$offset))<<P:Predicate_unindexedload>><<P:Predicate_load>><<P:Predicate_smrd_load>>  =>  (S_LOAD_DWORDX2_IMM:{ *:[v2f32] } ?:{ *:[i64] }:$sbase, ?:{ *:[i32] }:$offset, 0:{ *:[i32] })
      GIR_BuildMI, /*InsnID*/0, /*Opcode*/GIMT_Encode2(AMDGPU::S_LOAD_DWORDX2_IMM),
      GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/0, // DstI[sdst]
      GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/0, // sbase
      GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/1, // offset
      GIR_AddImm8, /*InsnID*/0, /*Imm*/0,
      GIR_MergeMemOperands, /*InsnID*/0, /*NumInsns*/1, /*MergeInsnID's*/0,
      GIR_ConstrainSelectedInstOperands, /*InsnID*/0,
      GIR_EraseFromParent, /*InsnID*/0,
      // GIR_Coverage, 2512,
      GIR_Done,
    // Label 1292: @85567
    GIM_Try, /*On fail goto*//*Label 1293*/ GIMT_Encode4(85632), // Rule ID 2513 //
      GIM_CheckFeatures, GIMT_Encode2(GIFBS_isGFX7Only),
      GIM_CheckMemorySizeEqualToLLT, /*MI*/0, /*MMO*/0, /*OpIdx*/0,
      GIM_CheckAtomicOrdering, /*MI*/0, /*Order*/(uint8_t)AtomicOrdering::NotAtomic,
      GIM_CheckRegBankForClass, /*MI*/0, /*Op*/0, /*RC*/GIMT_Encode2(AMDGPU::SReg_64_XEXECRegClassID),
      GIM_CheckPointerToAny, /*MI*/0, /*Op*/1, /*SizeInBits*/0,
      GIM_CheckCxxInsnPredicate, /*MI*/0, /*FnId*/GIMT_Encode2(GICXXPred_MI_Predicate_smrd_load),
      GIM_CheckComplexPattern, /*MI*/0, /*Op*/1, /*Renderer*/GIMT_Encode2(0), GIMT_Encode2(GICP_gi_smrd_imm32),
      // (ld:{ *:[v2f32] } (SMRDImm32:{ *:[iPTR] } i64:{ *:[i64] }:$sbase, i32:{ *:[i32] }:$offset))<<P:Predicate_unindexedload>><<P:Predicate_load>><<P:Predicate_smrd_load>>  =>  (S_LOAD_DWORDX2_IMM_ci:{ *:[v2f32] } ?:{ *:[i64] }:$sbase, ?:{ *:[i32] }:$offset, 0:{ *:[i32] })
      GIR_BuildMI, /*InsnID*/0, /*Opcode*/GIMT_Encode2(AMDGPU::S_LOAD_DWORDX2_IMM_ci),
      GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/0, // DstI[sdst]
      GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/0, // sbase
      GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/1, // offset
      GIR_AddImm8, /*InsnID*/0, /*Imm*/0,
      GIR_MergeMemOperands, /*InsnID*/0, /*NumInsns*/1, /*MergeInsnID's*/0,
      GIR_ConstrainSelectedInstOperands, /*InsnID*/0,
      GIR_EraseFromParent, /*InsnID*/0,
      // GIR_Coverage, 2513,
      GIR_Done,
    // Label 1293: @85632
    GIM_Try, /*On fail goto*//*Label 1294*/ GIMT_Encode4(85697), // Rule ID 2514 //
      GIM_CheckFeatures, GIMT_Encode2(GIFBS_isNotGFX9Plus),
      GIM_CheckMemorySizeEqualToLLT, /*MI*/0, /*MMO*/0, /*OpIdx*/0,
      GIM_CheckAtomicOrdering, /*MI*/0, /*Order*/(uint8_t)AtomicOrdering::NotAtomic,
      GIM_CheckRegBankForClass, /*MI*/0, /*Op*/0, /*RC*/GIMT_Encode2(AMDGPU::SReg_64_XEXECRegClassID),
      GIM_CheckPointerToAny, /*MI*/0, /*Op*/1, /*SizeInBits*/0,
      GIM_CheckCxxInsnPredicate, /*MI*/0, /*FnId*/GIMT_Encode2(GICXXPred_MI_Predicate_smrd_load),
      GIM_CheckComplexPattern, /*MI*/0, /*Op*/1, /*Renderer*/GIMT_Encode2(0), GIMT_Encode2(GICP_gi_smrd_sgpr),
      // (ld:{ *:[v2f32] } (SMRDSgpr:{ *:[iPTR] } i64:{ *:[i64] }:$sbase, i32:{ *:[i32] }:$soffset))<<P:Predicate_unindexedload>><<P:Predicate_load>><<P:Predicate_smrd_load>>  =>  (S_LOAD_DWORDX2_SGPR:{ *:[v2f32] } ?:{ *:[i64] }:$sbase, ?:{ *:[i32] }:$soffset, 0:{ *:[i32] })
      GIR_BuildMI, /*InsnID*/0, /*Opcode*/GIMT_Encode2(AMDGPU::S_LOAD_DWORDX2_SGPR),
      GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/0, // DstI[sdst]
      GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/0, // sbase
      GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/1, // soffset
      GIR_AddImm8, /*InsnID*/0, /*Imm*/0,
      GIR_MergeMemOperands, /*InsnID*/0, /*NumInsns*/1, /*MergeInsnID's*/0,
      GIR_ConstrainSelectedInstOperands, /*InsnID*/0,
      GIR_EraseFromParent, /*InsnID*/0,
      // GIR_Coverage, 2514,
      GIR_Done,
    // Label 1294: @85697
    GIM_Try, /*On fail goto*//*Label 1295*/ GIMT_Encode4(85765), // Rule ID 2515 //
      GIM_CheckFeatures, GIMT_Encode2(GIFBS_isGFX9Plus),
      GIM_CheckMemorySizeEqualToLLT, /*MI*/0, /*MMO*/0, /*OpIdx*/0,
      GIM_CheckAtomicOrdering, /*MI*/0, /*Order*/(uint8_t)AtomicOrdering::NotAtomic,
      GIM_CheckRegBankForClass, /*MI*/0, /*Op*/0, /*RC*/GIMT_Encode2(AMDGPU::SReg_64_XEXECRegClassID),
      GIM_CheckPointerToAny, /*MI*/0, /*Op*/1, /*SizeInBits*/0,
      GIM_CheckCxxInsnPredicate, /*MI*/0, /*FnId*/GIMT_Encode2(GICXXPred_MI_Predicate_smrd_load),
      GIM_CheckComplexPattern, /*MI*/0, /*Op*/1, /*Renderer*/GIMT_Encode2(0), GIMT_Encode2(GICP_gi_smrd_sgpr),
      // (ld:{ *:[v2f32] } (SMRDSgpr:{ *:[iPTR] } i64:{ *:[i64] }:$sbase, i32:{ *:[i32] }:$soffset))<<P:Predicate_unindexedload>><<P:Predicate_load>><<P:Predicate_smrd_load>>  =>  (S_LOAD_DWORDX2_SGPR_IMM:{ *:[v2f32] } ?:{ *:[i64] }:$sbase, ?:{ *:[i32] }:$soffset, 0:{ *:[i32] }, 0:{ *:[i32] })
      GIR_BuildMI, /*InsnID*/0, /*Opcode*/GIMT_Encode2(AMDGPU::S_LOAD_DWORDX2_SGPR_IMM),
      GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/0, // DstI[sdst]
      GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/0, // sbase
      GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/1, // soffset
      GIR_AddImm8, /*InsnID*/0, /*Imm*/0,
      GIR_AddImm8, /*InsnID*/0, /*Imm*/0,
      GIR_MergeMemOperands, /*InsnID*/0, /*NumInsns*/1, /*MergeInsnID's*/0,
      GIR_ConstrainSelectedInstOperands, /*InsnID*/0,
      GIR_EraseFromParent, /*InsnID*/0,
      // GIR_Coverage, 2515,
      GIR_Done,
    // Label 1295: @85765
    GIM_Try, /*On fail goto*//*Label 1296*/ GIMT_Encode4(85836), // Rule ID 6824 //
      GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasUnalignedAccessMode_NotLDSRequiresM0Init),
      GIM_CheckMemoryAddressSpace, /*MI*/0, /*MMO*/0, /*NumAddrSpace*/1, /*AddrSpace*/3,
      GIM_CheckMemoryAddressSpace, /*MI*/0, /*MMO*/0, /*NumAddrSpace*/1, /*AddrSpace*/3,
      GIM_CheckAtomicOrdering, /*MI*/0, /*Order*/(uint8_t)AtomicOrdering::NotAtomic,
      GIM_CheckRegBankForClass, /*MI*/0, /*Op*/0, /*RC*/GIMT_Encode2(AMDGPU::AV_64RegClassID),
      GIM_CheckPointerToAny, /*MI*/0, /*Op*/1, /*SizeInBits*/0,
      GIM_CheckCxxInsnPredicate, /*MI*/0, /*FnId*/GIMT_Encode2(GICXXPred_MI_Predicate_load_align_less_than_4_local),
      GIM_CheckComplexPattern, /*MI*/0, /*Op*/1, /*Renderer*/GIMT_Encode2(0), GIMT_Encode2(GICP_gi_ds_1addr_1offset),
      // (ld:{ *:[v2i32] } (DS1Addr1Offset:{ *:[iPTR] } i32:{ *:[i32] }:$ptr, i32:{ *:[i32] }:$offset))<<P:Predicate_unindexedload>><<P:Predicate_load_local>><<P:Predicate_load_align_less_than_4_local>>  =>  (DS_READ_B64_gfx9:{ *:[v2i32] } ?:{ *:[i32] }:$ptr, offset:{ *:[i32] }:$offset, 0:{ *:[i1] })
      GIR_BuildMI, /*InsnID*/0, /*Opcode*/GIMT_Encode2(AMDGPU::DS_READ_B64_gfx9),
      GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/0, // DstI[vdst]
      GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/0, // ptr
      GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/1, // offset
      GIR_AddImm8, /*InsnID*/0, /*Imm*/0,
      GIR_MergeMemOperands, /*InsnID*/0, /*NumInsns*/1, /*MergeInsnID's*/0,
      GIR_ConstrainSelectedInstOperands, /*InsnID*/0,
      GIR_EraseFromParent, /*InsnID*/0,
      // GIR_Coverage, 6824,
      GIR_Done,
    // Label 1296: @85836
    GIM_Try, /*On fail goto*//*Label 1297*/ GIMT_Encode4(85907), // Rule ID 6828 //
      GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasUnalignedAccessMode_NotLDSRequiresM0Init),
      GIM_CheckMemoryAddressSpace, /*MI*/0, /*MMO*/0, /*NumAddrSpace*/1, /*AddrSpace*/3,
      GIM_CheckMemoryAddressSpace, /*MI*/0, /*MMO*/0, /*NumAddrSpace*/1, /*AddrSpace*/3,
      GIM_CheckAtomicOrdering, /*MI*/0, /*Order*/(uint8_t)AtomicOrdering::NotAtomic,
      GIM_CheckRegBankForClass, /*MI*/0, /*Op*/0, /*RC*/GIMT_Encode2(AMDGPU::AV_64RegClassID),
      GIM_CheckPointerToAny, /*MI*/0, /*Op*/1, /*SizeInBits*/0,
      GIM_CheckCxxInsnPredicate, /*MI*/0, /*FnId*/GIMT_Encode2(GICXXPred_MI_Predicate_load_align_less_than_4_local),
      GIM_CheckComplexPattern, /*MI*/0, /*Op*/1, /*Renderer*/GIMT_Encode2(0), GIMT_Encode2(GICP_gi_ds_1addr_1offset),
      // (ld:{ *:[v2f32] } (DS1Addr1Offset:{ *:[iPTR] } i32:{ *:[i32] }:$ptr, i32:{ *:[i32] }:$offset))<<P:Predicate_unindexedload>><<P:Predicate_load_local>><<P:Predicate_load_align_less_than_4_local>>  =>  (DS_READ_B64_gfx9:{ *:[v2f32] } ?:{ *:[i32] }:$ptr, offset:{ *:[i32] }:$offset, 0:{ *:[i1] })
      GIR_BuildMI, /*InsnID*/0, /*Opcode*/GIMT_Encode2(AMDGPU::DS_READ_B64_gfx9),
      GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/0, // DstI[vdst]
      GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/0, // ptr
      GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/1, // offset
      GIR_AddImm8, /*InsnID*/0, /*Imm*/0,
      GIR_MergeMemOperands, /*InsnID*/0, /*NumInsns*/1, /*MergeInsnID's*/0,
      GIR_ConstrainSelectedInstOperands, /*InsnID*/0,
      GIR_EraseFromParent, /*InsnID*/0,
      // GIR_Coverage, 6828,
      GIR_Done,
    // Label 1297: @85907
    GIM_Try, /*On fail goto*//*Label 1298*/ GIMT_Encode4(85973), // Rule ID 6748 //
      GIM_CheckFeatures, GIMT_Encode2(GIFBS_NotLDSRequiresM0Init),
      GIM_CheckMemoryAddressSpace, /*MI*/0, /*MMO*/0, /*NumAddrSpace*/1, /*AddrSpace*/3,
      GIM_CheckMemoryAlignment, /*MI*/0, /*MMO*/0, /*MinAlign*/8,
      GIM_CheckAtomicOrdering, /*MI*/0, /*Order*/(uint8_t)AtomicOrdering::NotAtomic,
      GIM_CheckRegBankForClass, /*MI*/0, /*Op*/0, /*RC*/GIMT_Encode2(AMDGPU::AV_64RegClassID),
      GIM_CheckPointerToAny, /*MI*/0, /*Op*/1, /*SizeInBits*/0,
      GIM_CheckComplexPattern, /*MI*/0, /*Op*/1, /*Renderer*/GIMT_Encode2(0), GIMT_Encode2(GICP_gi_ds_1addr_1offset),
      // (ld:{ *:[v2i32] } (DS1Addr1Offset:{ *:[iPTR] } i32:{ *:[i32] }:$ptr, i32:{ *:[i32] }:$offset))<<P:Predicate_unindexedload>><<P:Predicate_load_local>><<P:Predicate_load_align8_local>>  =>  (DS_READ_B64_gfx9:{ *:[v2i32] } ?:{ *:[i32] }:$ptr, offset:{ *:[i32] }:$offset, 0:{ *:[i1] })
      GIR_BuildMI, /*InsnID*/0, /*Opcode*/GIMT_Encode2(AMDGPU::DS_READ_B64_gfx9),
      GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/0, // DstI[vdst]
      GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/0, // ptr
      GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/1, // offset
      GIR_AddImm8, /*InsnID*/0, /*Imm*/0,
      GIR_MergeMemOperands, /*InsnID*/0, /*NumInsns*/1, /*MergeInsnID's*/0,
      GIR_ConstrainSelectedInstOperands, /*InsnID*/0,
      GIR_EraseFromParent, /*InsnID*/0,
      // GIR_Coverage, 6748,
      GIR_Done,
    // Label 1298: @85973
    GIM_Try, /*On fail goto*//*Label 1299*/ GIMT_Encode4(86039), // Rule ID 6752 //
      GIM_CheckFeatures, GIMT_Encode2(GIFBS_NotLDSRequiresM0Init),
      GIM_CheckMemoryAddressSpace, /*MI*/0, /*MMO*/0, /*NumAddrSpace*/1, /*AddrSpace*/3,
      GIM_CheckMemoryAlignment, /*MI*/0, /*MMO*/0, /*MinAlign*/8,
      GIM_CheckAtomicOrdering, /*MI*/0, /*Order*/(uint8_t)AtomicOrdering::NotAtomic,
      GIM_CheckRegBankForClass, /*MI*/0, /*Op*/0, /*RC*/GIMT_Encode2(AMDGPU::AV_64RegClassID),
      GIM_CheckPointerToAny, /*MI*/0, /*Op*/1, /*SizeInBits*/0,
      GIM_CheckComplexPattern, /*MI*/0, /*Op*/1, /*Renderer*/GIMT_Encode2(0), GIMT_Encode2(GICP_gi_ds_1addr_1offset),
      // (ld:{ *:[v2f32] } (DS1Addr1Offset:{ *:[iPTR] } i32:{ *:[i32] }:$ptr, i32:{ *:[i32] }:$offset))<<P:Predicate_unindexedload>><<P:Predicate_load_local>><<P:Predicate_load_align8_local>>  =>  (DS_READ_B64_gfx9:{ *:[v2f32] } ?:{ *:[i32] }:$ptr, offset:{ *:[i32] }:$offset, 0:{ *:[i1] })
      GIR_BuildMI, /*InsnID*/0, /*Opcode*/GIMT_Encode2(AMDGPU::DS_READ_B64_gfx9),
      GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/0, // DstI[vdst]
      GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/0, // ptr
      GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/1, // offset
      GIR_AddImm8, /*InsnID*/0, /*Imm*/0,
      GIR_MergeMemOperands, /*InsnID*/0, /*NumInsns*/1, /*MergeInsnID's*/0,
      GIR_ConstrainSelectedInstOperands, /*InsnID*/0,
      GIR_EraseFromParent, /*InsnID*/0,
      // GIR_Coverage, 6752,
      GIR_Done,
    // Label 1299: @86039
    GIM_Try, /*On fail goto*//*Label 1300*/ GIMT_Encode4(86096), // Rule ID 2505 //
      GIM_CheckMemorySizeEqualToLLT, /*MI*/0, /*MMO*/0, /*OpIdx*/0,
      GIM_CheckAtomicOrdering, /*MI*/0, /*Order*/(uint8_t)AtomicOrdering::NotAtomic,
      GIM_CheckRegBankForClass, /*MI*/0, /*Op*/0, /*RC*/GIMT_Encode2(AMDGPU::SReg_64_XEXECRegClassID),
      // MIs[0] sbase
      GIM_CheckPointerToAny, /*MI*/0, /*Op*/1, /*SizeInBits*/64,
      GIM_CheckRegBankForClass, /*MI*/0, /*Op*/1, /*RC*/GIMT_Encode2(AMDGPU::SReg_64RegClassID),
      GIM_CheckCxxInsnPredicate, /*MI*/0, /*FnId*/GIMT_Encode2(GICXXPred_MI_Predicate_smrd_load),
      // (ld:{ *:[v2i32] } SReg_64:{ *:[i64] }:$sbase)<<P:Predicate_unindexedload>><<P:Predicate_load>><<P:Predicate_smrd_load>>  =>  (S_LOAD_DWORDX2_IMM:{ *:[v2i32] } i64:{ *:[i64] }:$sbase, 0:{ *:[i32] }, 0:{ *:[i32] })
      GIR_BuildMI, /*InsnID*/0, /*Opcode*/GIMT_Encode2(AMDGPU::S_LOAD_DWORDX2_IMM),
      GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/0, // DstI[sdst]
      GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/1, // sbase
      GIR_AddImm8, /*InsnID*/0, /*Imm*/0,
      GIR_AddImm8, /*InsnID*/0, /*Imm*/0,
      GIR_MergeMemOperands, /*InsnID*/0, /*NumInsns*/1, /*MergeInsnID's*/0,
      GIR_ConstrainSelectedInstOperands, /*InsnID*/0,
      GIR_EraseFromParent, /*InsnID*/0,
      // GIR_Coverage, 2505,
      GIR_Done,
    // Label 1300: @86096
    GIM_Try, /*On fail goto*//*Label 1301*/ GIMT_Encode4(86153), // Rule ID 2517 //
      GIM_CheckMemorySizeEqualToLLT, /*MI*/0, /*MMO*/0, /*OpIdx*/0,
      GIM_CheckAtomicOrdering, /*MI*/0, /*Order*/(uint8_t)AtomicOrdering::NotAtomic,
      GIM_CheckRegBankForClass, /*MI*/0, /*Op*/0, /*RC*/GIMT_Encode2(AMDGPU::SReg_64_XEXECRegClassID),
      // MIs[0] sbase
      GIM_CheckPointerToAny, /*MI*/0, /*Op*/1, /*SizeInBits*/64,
      GIM_CheckRegBankForClass, /*MI*/0, /*Op*/1, /*RC*/GIMT_Encode2(AMDGPU::SReg_64RegClassID),
      GIM_CheckCxxInsnPredicate, /*MI*/0, /*FnId*/GIMT_Encode2(GICXXPred_MI_Predicate_smrd_load),
      // (ld:{ *:[v2f32] } SReg_64:{ *:[i64] }:$sbase)<<P:Predicate_unindexedload>><<P:Predicate_load>><<P:Predicate_smrd_load>>  =>  (S_LOAD_DWORDX2_IMM:{ *:[v2f32] } i64:{ *:[i64] }:$sbase, 0:{ *:[i32] }, 0:{ *:[i32] })
      GIR_BuildMI, /*InsnID*/0, /*Opcode*/GIMT_Encode2(AMDGPU::S_LOAD_DWORDX2_IMM),
      GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/0, // DstI[sdst]
      GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/1, // sbase
      GIR_AddImm8, /*InsnID*/0, /*Imm*/0,
      GIR_AddImm8, /*InsnID*/0, /*Imm*/0,
      GIR_MergeMemOperands, /*InsnID*/0, /*NumInsns*/1, /*MergeInsnID's*/0,
      GIR_ConstrainSelectedInstOperands, /*InsnID*/0,
      GIR_EraseFromParent, /*InsnID*/0,
      // GIR_Coverage, 2517,
      GIR_Done,
    // Label 1301: @86153
    GIM_Try, /*On fail goto*//*Label 1302*/ GIMT_Encode4(86223), // Rule ID 5424 //
      GIM_CheckFeatures, GIMT_Encode2(GIFBS_DisableFlatScratch_HasUnrestrictedSOffset),
      GIM_CheckMemoryAddressSpace, /*MI*/0, /*MMO*/0, /*NumAddrSpace*/1, /*AddrSpace*/5,
      GIM_CheckAtomicOrdering, /*MI*/0, /*Order*/(uint8_t)AtomicOrdering::NotAtomic,
      GIM_CheckRegBankForClass, /*MI*/0, /*Op*/0, /*RC*/GIMT_Encode2(AMDGPU::AV_64RegClassID),
      GIM_CheckPointerToAny, /*MI*/0, /*Op*/1, /*SizeInBits*/0,
      GIM_CheckComplexPattern, /*MI*/0, /*Op*/1, /*Renderer*/GIMT_Encode2(0), GIMT_Encode2(GICP_gi_mubuf_scratch_offset),
      // (ld:{ *:[v2i32] } (MUBUFScratchOffset:{ *:[iPTR] } v4i32:{ *:[v4i32] }:$srsrc, i32:{ *:[i32] }:$soffset, i32:{ *:[i32] }:$offset))<<P:Predicate_unindexedload>><<P:Predicate_load_private>>  =>  (BUFFER_LOAD_DWORDX2_OFFSET:{ *:[v2i32] } ?:{ *:[v4i32] }:$srsrc, ?:{ *:[i32] }:$soffset, ?:{ *:[i32] }:$offset, 0:{ *:[i32] }, 0:{ *:[i1] })
      GIR_BuildMI, /*InsnID*/0, /*Opcode*/GIMT_Encode2(AMDGPU::BUFFER_LOAD_DWORDX2_OFFSET),
      GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/0, // DstI[vdata]
      GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/0, // srsrc
      GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/1, // soffset
      GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/2, // offset
      GIR_AddImm8, /*InsnID*/0, /*Imm*/0,
      GIR_AddImm8, /*InsnID*/0, /*Imm*/0,
      GIR_MergeMemOperands, /*InsnID*/0, /*NumInsns*/1, /*MergeInsnID's*/0,
      GIR_ConstrainSelectedInstOperands, /*InsnID*/0,
      GIR_EraseFromParent, /*InsnID*/0,
      // GIR_Coverage, 5424,
      GIR_Done,
    // Label 1302: @86223
    GIM_Try, /*On fail goto*//*Label 1303*/ GIMT_Encode4(86293), // Rule ID 5426 //
      GIM_CheckFeatures, GIMT_Encode2(GIFBS_DisableFlatScratch),
      GIM_CheckMemoryAddressSpace, /*MI*/0, /*MMO*/0, /*NumAddrSpace*/1, /*AddrSpace*/5,
      GIM_CheckAtomicOrdering, /*MI*/0, /*Order*/(uint8_t)AtomicOrdering::NotAtomic,
      GIM_CheckRegBankForClass, /*MI*/0, /*Op*/0, /*RC*/GIMT_Encode2(AMDGPU::AV_64RegClassID),
      GIM_CheckPointerToAny, /*MI*/0, /*Op*/1, /*SizeInBits*/0,
      GIM_CheckComplexPattern, /*MI*/0, /*Op*/1, /*Renderer*/GIMT_Encode2(0), GIMT_Encode2(GICP_gi_mubuf_scratch_offset),
      // (ld:{ *:[v2i32] } (MUBUFScratchOffset:{ *:[iPTR] } v4i32:{ *:[v4i32] }:$srsrc, i32:{ *:[i32] }:$soffset, i32:{ *:[i32] }:$offset))<<P:Predicate_unindexedload>><<P:Predicate_load_private>>  =>  (BUFFER_LOAD_DWORDX2_VBUFFER_OFFSET:{ *:[v2i32] } ?:{ *:[v4i32] }:$srsrc, ?:{ *:[i32] }:$soffset, ?:{ *:[i32] }:$offset, 0:{ *:[i32] }, 0:{ *:[i1] })
      GIR_BuildMI, /*InsnID*/0, /*Opcode*/GIMT_Encode2(AMDGPU::BUFFER_LOAD_DWORDX2_VBUFFER_OFFSET),
      GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/0, // DstI[vdata]
      GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/0, // srsrc
      GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/1, // soffset
      GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/2, // offset
      GIR_AddImm8, /*InsnID*/0, /*Imm*/0,
      GIR_AddImm8, /*InsnID*/0, /*Imm*/0,
      GIR_MergeMemOperands, /*InsnID*/0, /*NumInsns*/1, /*MergeInsnID's*/0,
      GIR_ConstrainSelectedInstOperands, /*InsnID*/0,
      GIR_EraseFromParent, /*InsnID*/0,
      // GIR_Coverage, 5426,
      GIR_Done,
    // Label 1303: @86293
    GIM_Try, /*On fail goto*//*Label 1304*/ GIMT_Encode4(86360), // Rule ID 3496 //
      GIM_CheckFeatures, GIMT_Encode2(GIFBS_EnableFlatScratch_HasFlatScratchInsts_HasFlatScratchSVSMode),
      GIM_CheckMemoryAddressSpace, /*MI*/0, /*MMO*/0, /*NumAddrSpace*/1, /*AddrSpace*/5,
      GIM_CheckAtomicOrdering, /*MI*/0, /*Order*/(uint8_t)AtomicOrdering::NotAtomic,
      GIM_CheckRegBankForClass, /*MI*/0, /*Op*/0, /*RC*/GIMT_Encode2(AMDGPU::AV_64RegClassID),
      GIM_CheckPointerToAny, /*MI*/0, /*Op*/1, /*SizeInBits*/0,
      GIM_CheckComplexPattern, /*MI*/0, /*Op*/1, /*Renderer*/GIMT_Encode2(0), GIMT_Encode2(GICP_gi_flat_scratch_svaddr),
      // (ld:{ *:[v2i32] } (ScratchSVAddr:{ *:[iPTR] } VGPR_32:{ *:[i32] }:$vaddr, SGPR_32:{ *:[i32] }:$saddr, i32:{ *:[i32] }:$offset))<<P:Predicate_unindexedload>><<P:Predicate_load_private>>  =>  (SCRATCH_LOAD_DWORDX2_SVS:{ *:[v2i32] } ?:{ *:[i32] }:$vaddr, ?:{ *:[i32] }:$saddr, ?:{ *:[i32] }:$offset, 0:{ *:[i32] })
      GIR_BuildMI, /*InsnID*/0, /*Opcode*/GIMT_Encode2(AMDGPU::SCRATCH_LOAD_DWORDX2_SVS),
      GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/0, // DstI[vdst]
      GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/0, // vaddr
      GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/1, // saddr
      GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/2, // offset
      GIR_AddImm8, /*InsnID*/0, /*Imm*/0,
      GIR_MergeMemOperands, /*InsnID*/0, /*NumInsns*/1, /*MergeInsnID's*/0,
      GIR_ConstrainSelectedInstOperands, /*InsnID*/0,
      GIR_EraseFromParent, /*InsnID*/0,
      // GIR_Coverage, 3496,
      GIR_Done,
    // Label 1304: @86360
    GIM_Try, /*On fail goto*//*Label 1305*/ GIMT_Encode4(86427), // Rule ID 3502 //
      GIM_CheckFeatures, GIMT_Encode2(GIFBS_EnableFlatScratch_HasFlatScratchInsts_HasFlatScratchSVSMode),
      GIM_CheckMemoryAddressSpace, /*MI*/0, /*MMO*/0, /*NumAddrSpace*/1, /*AddrSpace*/5,
      GIM_CheckAtomicOrdering, /*MI*/0, /*Order*/(uint8_t)AtomicOrdering::NotAtomic,
      GIM_CheckRegBankForClass, /*MI*/0, /*Op*/0, /*RC*/GIMT_Encode2(AMDGPU::AV_64RegClassID),
      GIM_CheckPointerToAny, /*MI*/0, /*Op*/1, /*SizeInBits*/0,
      GIM_CheckComplexPattern, /*MI*/0, /*Op*/1, /*Renderer*/GIMT_Encode2(0), GIMT_Encode2(GICP_gi_flat_scratch_svaddr),
      // (ld:{ *:[v2f32] } (ScratchSVAddr:{ *:[iPTR] } VGPR_32:{ *:[i32] }:$vaddr, SGPR_32:{ *:[i32] }:$saddr, i32:{ *:[i32] }:$offset))<<P:Predicate_unindexedload>><<P:Predicate_load_private>>  =>  (SCRATCH_LOAD_DWORDX2_SVS:{ *:[v2f32] } ?:{ *:[i32] }:$vaddr, ?:{ *:[i32] }:$saddr, ?:{ *:[i32] }:$offset, 0:{ *:[i32] })
      GIR_BuildMI, /*InsnID*/0, /*Opcode*/GIMT_Encode2(AMDGPU::SCRATCH_LOAD_DWORDX2_SVS),
      GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/0, // DstI[vdst]
      GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/0, // vaddr
      GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/1, // saddr
      GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/2, // offset
      GIR_AddImm8, /*InsnID*/0, /*Imm*/0,
      GIR_MergeMemOperands, /*InsnID*/0, /*NumInsns*/1, /*MergeInsnID's*/0,
      GIR_ConstrainSelectedInstOperands, /*InsnID*/0,
      GIR_EraseFromParent, /*InsnID*/0,
      // GIR_Coverage, 3502,
      GIR_Done,
    // Label 1305: @86427
    GIM_Try, /*On fail goto*//*Label 1306*/ GIMT_Encode4(86489), // Rule ID 3495 //
      GIM_CheckFeatures, GIMT_Encode2(GIFBS_EnableFlatScratch_HasFlatScratchInsts),
      GIM_CheckMemoryAddressSpace, /*MI*/0, /*MMO*/0, /*NumAddrSpace*/1, /*AddrSpace*/5,
      GIM_CheckAtomicOrdering, /*MI*/0, /*Order*/(uint8_t)AtomicOrdering::NotAtomic,
      GIM_CheckRegBankForClass, /*MI*/0, /*Op*/0, /*RC*/GIMT_Encode2(AMDGPU::AV_64RegClassID),
      GIM_CheckPointerToAny, /*MI*/0, /*Op*/1, /*SizeInBits*/0,
      GIM_CheckComplexPattern, /*MI*/0, /*Op*/1, /*Renderer*/GIMT_Encode2(0), GIMT_Encode2(GICP_gi_flat_scratch_saddr),
      // (ld:{ *:[v2i32] } (ScratchSAddr:{ *:[iPTR] } SGPR_32:{ *:[i32] }:$saddr, i32:{ *:[i32] }:$offset))<<P:Predicate_unindexedload>><<P:Predicate_load_private>>  =>  (SCRATCH_LOAD_DWORDX2_SADDR:{ *:[v2i32] } ?:{ *:[i32] }:$saddr, ?:{ *:[i32] }:$offset)
      GIR_BuildMI, /*InsnID*/0, /*Opcode*/GIMT_Encode2(AMDGPU::SCRATCH_LOAD_DWORDX2_SADDR),
      GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/0, // DstI[vdst]
      GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/0, // saddr
      GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/1, // offset
      GIR_AddImm8, /*InsnID*/0, /*Imm*/0,
      GIR_MergeMemOperands, /*InsnID*/0, /*NumInsns*/1, /*MergeInsnID's*/0,
      GIR_ConstrainSelectedInstOperands, /*InsnID*/0,
      GIR_EraseFromParent, /*InsnID*/0,
      // GIR_Coverage, 3495,
      GIR_Done,
    // Label 1306: @86489
    GIM_Try, /*On fail goto*//*Label 1307*/ GIMT_Encode4(86551), // Rule ID 3501 //
      GIM_CheckFeatures, GIMT_Encode2(GIFBS_EnableFlatScratch_HasFlatScratchInsts),
      GIM_CheckMemoryAddressSpace, /*MI*/0, /*MMO*/0, /*NumAddrSpace*/1, /*AddrSpace*/5,
      GIM_CheckAtomicOrdering, /*MI*/0, /*Order*/(uint8_t)AtomicOrdering::NotAtomic,
      GIM_CheckRegBankForClass, /*MI*/0, /*Op*/0, /*RC*/GIMT_Encode2(AMDGPU::AV_64RegClassID),
      GIM_CheckPointerToAny, /*MI*/0, /*Op*/1, /*SizeInBits*/0,
      GIM_CheckComplexPattern, /*MI*/0, /*Op*/1, /*Renderer*/GIMT_Encode2(0), GIMT_Encode2(GICP_gi_flat_scratch_saddr),
      // (ld:{ *:[v2f32] } (ScratchSAddr:{ *:[iPTR] } SGPR_32:{ *:[i32] }:$saddr, i32:{ *:[i32] }:$offset))<<P:Predicate_unindexedload>><<P:Predicate_load_private>>  =>  (SCRATCH_LOAD_DWORDX2_SADDR:{ *:[v2f32] } ?:{ *:[i32] }:$saddr, ?:{ *:[i32] }:$offset)
      GIR_BuildMI, /*InsnID*/0, /*Opcode*/GIMT_Encode2(AMDGPU::SCRATCH_LOAD_DWORDX2_SADDR),
      GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/0, // DstI[vdst]
      GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/0, // saddr
      GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/1, // offset
      GIR_AddImm8, /*InsnID*/0, /*Imm*/0,
      GIR_MergeMemOperands, /*InsnID*/0, /*NumInsns*/1, /*MergeInsnID's*/0,
      GIR_ConstrainSelectedInstOperands, /*InsnID*/0,
      GIR_EraseFromParent, /*InsnID*/0,
      // GIR_Coverage, 3501,
      GIR_Done,
    // Label 1307: @86551
    GIM_Try, /*On fail goto*//*Label 1308*/ GIMT_Encode4(86613), // Rule ID 3494 //
      GIM_CheckFeatures, GIMT_Encode2(GIFBS_EnableFlatScratch_HasFlatScratchInsts),
      GIM_CheckMemoryAddressSpace, /*MI*/0, /*MMO*/0, /*NumAddrSpace*/1, /*AddrSpace*/5,
      GIM_CheckAtomicOrdering, /*MI*/0, /*Order*/(uint8_t)AtomicOrdering::NotAtomic,
      GIM_CheckRegBankForClass, /*MI*/0, /*Op*/0, /*RC*/GIMT_Encode2(AMDGPU::AV_64RegClassID),
      GIM_CheckPointerToAny, /*MI*/0, /*Op*/1, /*SizeInBits*/0,
      GIM_CheckComplexPattern, /*MI*/0, /*Op*/1, /*Renderer*/GIMT_Encode2(0), GIMT_Encode2(GICP_gi_flat_scratch_offset),
      // (ld:{ *:[v2i32] } (ScratchOffset:{ *:[iPTR] } VGPR_32:{ *:[i32] }:$vaddr, i32:{ *:[i32] }:$offset))<<P:Predicate_unindexedload>><<P:Predicate_load_private>>  =>  (SCRATCH_LOAD_DWORDX2:{ *:[v2i32] } ?:{ *:[i32] }:$vaddr, ?:{ *:[i32] }:$offset)
      GIR_BuildMI, /*InsnID*/0, /*Opcode*/GIMT_Encode2(AMDGPU::SCRATCH_LOAD_DWORDX2),
      GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/0, // DstI[vdst]
      GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/0, // vaddr
      GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/1, // offset
      GIR_AddImm8, /*InsnID*/0, /*Imm*/0,
      GIR_MergeMemOperands, /*InsnID*/0, /*NumInsns*/1, /*MergeInsnID's*/0,
      GIR_ConstrainSelectedInstOperands, /*InsnID*/0,
      GIR_EraseFromParent, /*InsnID*/0,
      // GIR_Coverage, 3494,
      GIR_Done,
    // Label 1308: @86613
    GIM_Try, /*On fail goto*//*Label 1309*/ GIMT_Encode4(86675), // Rule ID 3500 //
      GIM_CheckFeatures, GIMT_Encode2(GIFBS_EnableFlatScratch_HasFlatScratchInsts),
      GIM_CheckMemoryAddressSpace, /*MI*/0, /*MMO*/0, /*NumAddrSpace*/1, /*AddrSpace*/5,
      GIM_CheckAtomicOrdering, /*MI*/0, /*Order*/(uint8_t)AtomicOrdering::NotAtomic,
      GIM_CheckRegBankForClass, /*MI*/0, /*Op*/0, /*RC*/GIMT_Encode2(AMDGPU::AV_64RegClassID),
      GIM_CheckPointerToAny, /*MI*/0, /*Op*/1, /*SizeInBits*/0,
      GIM_CheckComplexPattern, /*MI*/0, /*Op*/1, /*Renderer*/GIMT_Encode2(0), GIMT_Encode2(GICP_gi_flat_scratch_offset),
      // (ld:{ *:[v2f32] } (ScratchOffset:{ *:[iPTR] } VGPR_32:{ *:[i32] }:$vaddr, i32:{ *:[i32] }:$offset))<<P:Predicate_unindexedload>><<P:Predicate_load_private>>  =>  (SCRATCH_LOAD_DWORDX2:{ *:[v2f32] } ?:{ *:[i32] }:$vaddr, ?:{ *:[i32] }:$offset)
      GIR_BuildMI, /*InsnID*/0, /*Opcode*/GIMT_Encode2(AMDGPU::SCRATCH_LOAD_DWORDX2),
      GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/0, // DstI[vdst]
      GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/0, // vaddr
      GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/1, // offset
      GIR_AddImm8, /*InsnID*/0, /*Imm*/0,
      GIR_MergeMemOperands, /*InsnID*/0, /*NumInsns*/1, /*MergeInsnID's*/0,
      GIR_ConstrainSelectedInstOperands, /*InsnID*/0,
      GIR_EraseFromParent, /*InsnID*/0,
      // GIR_Coverage, 3500,
      GIR_Done,
    // Label 1309: @86675
    GIM_Try, /*On fail goto*//*Label 1310*/ GIMT_Encode4(86752), // Rule ID 3728 //
      GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasUnrestrictedSOffset),
      GIM_CheckMemoryAddressSpace, /*MI*/0, /*MMO*/0, /*NumAddrSpace*/3, /*AddrSpace*/1, /*AddrSpace*/4, /*AddrSpace*/6,
      GIM_CheckAtomicOrdering, /*MI*/0, /*Order*/(uint8_t)AtomicOrdering::NotAtomic,
      GIM_CheckRegBankForClass, /*MI*/0, /*Op*/0, /*RC*/GIMT_Encode2(AMDGPU::AV_64RegClassID),
      GIM_CheckPointerToAny, /*MI*/0, /*Op*/1, /*SizeInBits*/0,
      GIM_CheckComplexPattern, /*MI*/0, /*Op*/1, /*Renderer*/GIMT_Encode2(0), GIMT_Encode2(GICP_gi_mubuf_addr64),
      // (ld:{ *:[v2i32] } (MUBUFAddr64:{ *:[iPTR] } v4i32:{ *:[v4i32] }:$srsrc, i64:{ *:[i64] }:$vaddr, i32:{ *:[i32] }:$soffset, i32:{ *:[i32] }:$offset))<<P:Predicate_unindexedload>><<P:Predicate_load_global>>  =>  (BUFFER_LOAD_DWORDX2_ADDR64:{ *:[v2i32] } i64:{ *:[i64] }:$vaddr, v4i32:{ *:[v4i32] }:$srsrc, i32:{ *:[i32] }:$soffset, i32:{ *:[i32] }:$offset)
      GIR_BuildMI, /*InsnID*/0, /*Opcode*/GIMT_Encode2(AMDGPU::BUFFER_LOAD_DWORDX2_ADDR64),
      GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/0, // DstI[vdata]
      GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/1, // vaddr
      GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/0, // srsrc
      GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/2, // soffset
      GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/3, // offset
      GIR_AddImm8, /*InsnID*/0, /*Imm*/0,
      GIR_AddImm8, /*InsnID*/0, /*Imm*/0,
      GIR_MergeMemOperands, /*InsnID*/0, /*NumInsns*/1, /*MergeInsnID's*/0,
      GIR_ConstrainSelectedInstOperands, /*InsnID*/0,
      GIR_EraseFromParent, /*InsnID*/0,
      // GIR_Coverage, 3728,
      GIR_Done,
    // Label 1310: @86752
    GIM_Try, /*On fail goto*//*Label 1311*/ GIMT_Encode4(86826), // Rule ID 3730 //
      GIM_CheckMemoryAddressSpace, /*MI*/0, /*MMO*/0, /*NumAddrSpace*/3, /*AddrSpace*/1, /*AddrSpace*/4, /*AddrSpace*/6,
      GIM_CheckAtomicOrdering, /*MI*/0, /*Order*/(uint8_t)AtomicOrdering::NotAtomic,
      GIM_CheckRegBankForClass, /*MI*/0, /*Op*/0, /*RC*/GIMT_Encode2(AMDGPU::AV_64RegClassID),
      GIM_CheckPointerToAny, /*MI*/0, /*Op*/1, /*SizeInBits*/0,
      GIM_CheckComplexPattern, /*MI*/0, /*Op*/1, /*Renderer*/GIMT_Encode2(0), GIMT_Encode2(GICP_gi_mubuf_addr64),
      // (ld:{ *:[v2i32] } (MUBUFAddr64:{ *:[iPTR] } v4i32:{ *:[v4i32] }:$srsrc, i64:{ *:[i64] }:$vaddr, i32:{ *:[i32] }:$soffset, i32:{ *:[i32] }:$offset))<<P:Predicate_unindexedload>><<P:Predicate_load_global>>  =>  (BUFFER_LOAD_DWORDX2_VBUFFER_ADDR64:{ *:[v2i32] } i64:{ *:[i64] }:$vaddr, v4i32:{ *:[v4i32] }:$srsrc, i32:{ *:[i32] }:$soffset, i32:{ *:[i32] }:$offset)
      GIR_BuildMI, /*InsnID*/0, /*Opcode*/GIMT_Encode2(AMDGPU::BUFFER_LOAD_DWORDX2_VBUFFER_ADDR64),
      GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/0, // DstI[vdata]
      GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/1, // vaddr
      GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/0, // srsrc
      GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/2, // soffset
      GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/3, // offset
      GIR_AddImm8, /*InsnID*/0, /*Imm*/0,
      GIR_AddImm8, /*InsnID*/0, /*Imm*/0,
      GIR_MergeMemOperands, /*InsnID*/0, /*NumInsns*/1, /*MergeInsnID's*/0,
      GIR_ConstrainSelectedInstOperands, /*InsnID*/0,
      GIR_EraseFromParent, /*InsnID*/0,
      // GIR_Coverage, 3730,
      GIR_Done,
    // Label 1311: @86826
    GIM_Try, /*On fail goto*//*Label 1312*/ GIMT_Encode4(86903), // Rule ID 3732 //
      GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasUnrestrictedSOffset),
      GIM_CheckMemoryAddressSpace, /*MI*/0, /*MMO*/0, /*NumAddrSpace*/3, /*AddrSpace*/1, /*AddrSpace*/4, /*AddrSpace*/6,
      GIM_CheckAtomicOrdering, /*MI*/0, /*Order*/(uint8_t)AtomicOrdering::NotAtomic,
      GIM_CheckRegBankForClass, /*MI*/0, /*Op*/0, /*RC*/GIMT_Encode2(AMDGPU::AV_64RegClassID),
      GIM_CheckPointerToAny, /*MI*/0, /*Op*/1, /*SizeInBits*/0,
      GIM_CheckComplexPattern, /*MI*/0, /*Op*/1, /*Renderer*/GIMT_Encode2(0), GIMT_Encode2(GICP_gi_mubuf_addr64),
      // (ld:{ *:[v2f32] } (MUBUFAddr64:{ *:[iPTR] } v4i32:{ *:[v4i32] }:$srsrc, i64:{ *:[i64] }:$vaddr, i32:{ *:[i32] }:$soffset, i32:{ *:[i32] }:$offset))<<P:Predicate_unindexedload>><<P:Predicate_load_global>>  =>  (BUFFER_LOAD_DWORDX2_ADDR64:{ *:[v2f32] } i64:{ *:[i64] }:$vaddr, v4i32:{ *:[v4i32] }:$srsrc, i32:{ *:[i32] }:$soffset, i32:{ *:[i32] }:$offset)
      GIR_BuildMI, /*InsnID*/0, /*Opcode*/GIMT_Encode2(AMDGPU::BUFFER_LOAD_DWORDX2_ADDR64),
      GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/0, // DstI[vdata]
      GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/1, // vaddr
      GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/0, // srsrc
      GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/2, // soffset
      GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/3, // offset
      GIR_AddImm8, /*InsnID*/0, /*Imm*/0,
      GIR_AddImm8, /*InsnID*/0, /*Imm*/0,
      GIR_MergeMemOperands, /*InsnID*/0, /*NumInsns*/1, /*MergeInsnID's*/0,
      GIR_ConstrainSelectedInstOperands, /*InsnID*/0,
      GIR_EraseFromParent, /*InsnID*/0,
      // GIR_Coverage, 3732,
      GIR_Done,
    // Label 1312: @86903
    GIM_Try, /*On fail goto*//*Label 1313*/ GIMT_Encode4(86977), // Rule ID 3734 //
      GIM_CheckMemoryAddressSpace, /*MI*/0, /*MMO*/0, /*NumAddrSpace*/3, /*AddrSpace*/1, /*AddrSpace*/4, /*AddrSpace*/6,
      GIM_CheckAtomicOrdering, /*MI*/0, /*Order*/(uint8_t)AtomicOrdering::NotAtomic,
      GIM_CheckRegBankForClass, /*MI*/0, /*Op*/0, /*RC*/GIMT_Encode2(AMDGPU::AV_64RegClassID),
      GIM_CheckPointerToAny, /*MI*/0, /*Op*/1, /*SizeInBits*/0,
      GIM_CheckComplexPattern, /*MI*/0, /*Op*/1, /*Renderer*/GIMT_Encode2(0), GIMT_Encode2(GICP_gi_mubuf_addr64),
      // (ld:{ *:[v2f32] } (MUBUFAddr64:{ *:[iPTR] } v4i32:{ *:[v4i32] }:$srsrc, i64:{ *:[i64] }:$vaddr, i32:{ *:[i32] }:$soffset, i32:{ *:[i32] }:$offset))<<P:Predicate_unindexedload>><<P:Predicate_load_global>>  =>  (BUFFER_LOAD_DWORDX2_VBUFFER_ADDR64:{ *:[v2f32] } i64:{ *:[i64] }:$vaddr, v4i32:{ *:[v4i32] }:$srsrc, i32:{ *:[i32] }:$soffset, i32:{ *:[i32] }:$offset)
      GIR_BuildMI, /*InsnID*/0, /*Opcode*/GIMT_Encode2(AMDGPU::BUFFER_LOAD_DWORDX2_VBUFFER_ADDR64),
      GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/0, // DstI[vdata]
      GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/1, // vaddr
      GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/0, // srsrc
      GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/2, // soffset
      GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/3, // offset
      GIR_AddImm8, /*InsnID*/0, /*Imm*/0,
      GIR_AddImm8, /*InsnID*/0, /*Imm*/0,
      GIR_MergeMemOperands, /*InsnID*/0, /*NumInsns*/1, /*MergeInsnID's*/0,
      GIR_ConstrainSelectedInstOperands, /*InsnID*/0,
      GIR_EraseFromParent, /*InsnID*/0,
      // GIR_Coverage, 3734,
      GIR_Done,
    // Label 1313: @86977
    GIM_Try, /*On fail goto*//*Label 1314*/ GIMT_Encode4(87052), // Rule ID 5423 //
      GIM_CheckFeatures, GIMT_Encode2(GIFBS_DisableFlatScratch_HasUnrestrictedSOffset),
      GIM_CheckMemoryAddressSpace, /*MI*/0, /*MMO*/0, /*NumAddrSpace*/1, /*AddrSpace*/5,
      GIM_CheckAtomicOrdering, /*MI*/0, /*Order*/(uint8_t)AtomicOrdering::NotAtomic,
      GIM_CheckRegBankForClass, /*MI*/0, /*Op*/0, /*RC*/GIMT_Encode2(AMDGPU::AV_64RegClassID),
      GIM_CheckPointerToAny, /*MI*/0, /*Op*/1, /*SizeInBits*/0,
      GIM_CheckComplexPattern, /*MI*/0, /*Op*/1, /*Renderer*/GIMT_Encode2(0), GIMT_Encode2(GICP_gi_mubuf_scratch_offen),
      // (ld:{ *:[v2i32] } (MUBUFScratchOffen:{ *:[iPTR] } v4i32:{ *:[v4i32] }:$srsrc, i32:{ *:[i32] }:$vaddr, i32:{ *:[i32] }:$soffset, i32:{ *:[i32] }:$offset))<<P:Predicate_unindexedload>><<P:Predicate_load_private>>  =>  (BUFFER_LOAD_DWORDX2_OFFEN:{ *:[v2i32] } ?:{ *:[i32] }:$vaddr, ?:{ *:[v4i32] }:$srsrc, ?:{ *:[i32] }:$soffset, ?:{ *:[i32] }:$offset, 0:{ *:[i32] }, 0:{ *:[i1] })
      GIR_BuildMI, /*InsnID*/0, /*Opcode*/GIMT_Encode2(AMDGPU::BUFFER_LOAD_DWORDX2_OFFEN),
      GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/0, // DstI[vdata]
      GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/1, // vaddr
      GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/0, // srsrc
      GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/2, // soffset
      GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/3, // offset
      GIR_AddImm8, /*InsnID*/0, /*Imm*/0,
      GIR_AddImm8, /*InsnID*/0, /*Imm*/0,
      GIR_MergeMemOperands, /*InsnID*/0, /*NumInsns*/1, /*MergeInsnID's*/0,
      GIR_ConstrainSelectedInstOperands, /*InsnID*/0,
      GIR_EraseFromParent, /*InsnID*/0,
      // GIR_Coverage, 5423,
      GIR_Done,
    // Label 1314: @87052
    GIM_Try, /*On fail goto*//*Label 1315*/ GIMT_Encode4(87127), // Rule ID 5425 //
      GIM_CheckFeatures, GIMT_Encode2(GIFBS_DisableFlatScratch),
      GIM_CheckMemoryAddressSpace, /*MI*/0, /*MMO*/0, /*NumAddrSpace*/1, /*AddrSpace*/5,
      GIM_CheckAtomicOrdering, /*MI*/0, /*Order*/(uint8_t)AtomicOrdering::NotAtomic,
      GIM_CheckRegBankForClass, /*MI*/0, /*Op*/0, /*RC*/GIMT_Encode2(AMDGPU::AV_64RegClassID),
      GIM_CheckPointerToAny, /*MI*/0, /*Op*/1, /*SizeInBits*/0,
      GIM_CheckComplexPattern, /*MI*/0, /*Op*/1, /*Renderer*/GIMT_Encode2(0), GIMT_Encode2(GICP_gi_mubuf_scratch_offen),
      // (ld:{ *:[v2i32] } (MUBUFScratchOffen:{ *:[iPTR] } v4i32:{ *:[v4i32] }:$srsrc, i32:{ *:[i32] }:$vaddr, i32:{ *:[i32] }:$soffset, i32:{ *:[i32] }:$offset))<<P:Predicate_unindexedload>><<P:Predicate_load_private>>  =>  (BUFFER_LOAD_DWORDX2_VBUFFER_OFFEN:{ *:[v2i32] } ?:{ *:[i32] }:$vaddr, ?:{ *:[v4i32] }:$srsrc, ?:{ *:[i32] }:$soffset, ?:{ *:[i32] }:$offset, 0:{ *:[i32] }, 0:{ *:[i1] })
      GIR_BuildMI, /*InsnID*/0, /*Opcode*/GIMT_Encode2(AMDGPU::BUFFER_LOAD_DWORDX2_VBUFFER_OFFEN),
      GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/0, // DstI[vdata]
      GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/1, // vaddr
      GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/0, // srsrc
      GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/2, // soffset
      GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/3, // offset
      GIR_AddImm8, /*InsnID*/0, /*Imm*/0,
      GIR_AddImm8, /*InsnID*/0, /*Imm*/0,
      GIR_MergeMemOperands, /*InsnID*/0, /*NumInsns*/1, /*MergeInsnID's*/0,
      GIR_ConstrainSelectedInstOperands, /*InsnID*/0,
      GIR_EraseFromParent, /*InsnID*/0,
      // GIR_Coverage, 5425,
      GIR_Done,
    // Label 1315: @87127
    GIM_Try, /*On fail goto*//*Label 1316*/ GIMT_Encode4(87198), // Rule ID 6683 //
      GIM_CheckFeatures, GIMT_Encode2(GIFBS_LDSRequiresM0Init_isGFX7Plus),
      GIM_CheckMemorySizeEqualToLLT, /*MI*/0, /*MMO*/0, /*OpIdx*/0,
      GIM_CheckMemoryAddressSpace, /*MI*/0, /*MMO*/0, /*NumAddrSpace*/1, /*AddrSpace*/3,
      GIM_CheckAtomicOrdering, /*MI*/0, /*Order*/(uint8_t)AtomicOrdering::NotAtomic,
      GIM_CheckRegBankForClass, /*MI*/0, /*Op*/0, /*RC*/GIMT_Encode2(AMDGPU::AV_64RegClassID),
      GIM_CheckPointerToAny, /*MI*/0, /*Op*/1, /*SizeInBits*/0,
      GIM_CheckComplexPattern, /*MI*/0, /*Op*/1, /*Renderer*/GIMT_Encode2(0), GIMT_Encode2(GICP_gi_ds_64bit_4byte_aligned),
      // (AMDGPUld_glue:{ *:[v2i32] } (DS64Bit4ByteAligned:{ *:[iPTR] } i32:{ *:[i32] }:$ptr, i8:{ *:[i8] }:$offset0, i8:{ *:[i8] }:$offset1))<<P:Predicate_unindexedload_glue>><<P:Predicate_load_glue>><<P:Predicate_load_local_m0>>  =>  (DS_READ2_B32:{ *:[v2i32] } ?:{ *:[i32] }:$ptr, ?:{ *:[i8] }:$offset0, ?:{ *:[i8] }:$offset1, 0:{ *:[i1] })
      GIR_BuildMI, /*InsnID*/0, /*Opcode*/GIMT_Encode2(AMDGPU::DS_READ2_B32),
      GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/0, // DstI[vdst]
      GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/0, // ptr
      GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/1, // offset0
      GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/2, // offset1
      GIR_AddImm8, /*InsnID*/0, /*Imm*/0,
      GIR_MergeMemOperands, /*InsnID*/0, /*NumInsns*/1, /*MergeInsnID's*/0,
      GIR_ConstrainSelectedInstOperands, /*InsnID*/0,
      GIR_EraseFromParent, /*InsnID*/0,
      // GIR_Coverage, 6683,
      GIR_Done,
    // Label 1316: @87198
    GIM_Try, /*On fail goto*//*Label 1317*/ GIMT_Encode4(87269), // Rule ID 6687 //
      GIM_CheckFeatures, GIMT_Encode2(GIFBS_LDSRequiresM0Init_isGFX7Plus),
      GIM_CheckMemorySizeEqualToLLT, /*MI*/0, /*MMO*/0, /*OpIdx*/0,
      GIM_CheckMemoryAddressSpace, /*MI*/0, /*MMO*/0, /*NumAddrSpace*/1, /*AddrSpace*/3,
      GIM_CheckAtomicOrdering, /*MI*/0, /*Order*/(uint8_t)AtomicOrdering::NotAtomic,
      GIM_CheckRegBankForClass, /*MI*/0, /*Op*/0, /*RC*/GIMT_Encode2(AMDGPU::AV_64RegClassID),
      GIM_CheckPointerToAny, /*MI*/0, /*Op*/1, /*SizeInBits*/0,
      GIM_CheckComplexPattern, /*MI*/0, /*Op*/1, /*Renderer*/GIMT_Encode2(0), GIMT_Encode2(GICP_gi_ds_64bit_4byte_aligned),
      // (AMDGPUld_glue:{ *:[v2f32] } (DS64Bit4ByteAligned:{ *:[iPTR] } i32:{ *:[i32] }:$ptr, i8:{ *:[i8] }:$offset0, i8:{ *:[i8] }:$offset1))<<P:Predicate_unindexedload_glue>><<P:Predicate_load_glue>><<P:Predicate_load_local_m0>>  =>  (DS_READ2_B32:{ *:[v2f32] } ?:{ *:[i32] }:$ptr, ?:{ *:[i8] }:$offset0, ?:{ *:[i8] }:$offset1, 0:{ *:[i1] })
      GIR_BuildMI, /*InsnID*/0, /*Opcode*/GIMT_Encode2(AMDGPU::DS_READ2_B32),
      GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/0, // DstI[vdst]
      GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/0, // ptr
      GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/1, // offset0
      GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/2, // offset1
      GIR_AddImm8, /*InsnID*/0, /*Imm*/0,
      GIR_MergeMemOperands, /*InsnID*/0, /*NumInsns*/1, /*MergeInsnID's*/0,
      GIR_ConstrainSelectedInstOperands, /*InsnID*/0,
      GIR_EraseFromParent, /*InsnID*/0,
      // GIR_Coverage, 6687,
      GIR_Done,
    // Label 1317: @87269
    GIM_Try, /*On fail goto*//*Label 1318*/ GIMT_Encode4(87341), // Rule ID 3727 //
      GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasUnrestrictedSOffset),
      GIM_CheckMemoryAddressSpace, /*MI*/0, /*MMO*/0, /*NumAddrSpace*/3, /*AddrSpace*/1, /*AddrSpace*/4, /*AddrSpace*/6,
      GIM_CheckAtomicOrdering, /*MI*/0, /*Order*/(uint8_t)AtomicOrdering::NotAtomic,
      GIM_CheckRegBankForClass, /*MI*/0, /*Op*/0, /*RC*/GIMT_Encode2(AMDGPU::AV_64RegClassID),
      GIM_CheckPointerToAny, /*MI*/0, /*Op*/1, /*SizeInBits*/0,
      GIM_CheckComplexPattern, /*MI*/0, /*Op*/1, /*Renderer*/GIMT_Encode2(0), GIMT_Encode2(GICP_gi_mubuf_offset),
      // (ld:{ *:[v2i32] } (MUBUFOffset:{ *:[iPTR] } v4i32:{ *:[v4i32] }:$srsrc, i32:{ *:[i32] }:$soffset, i32:{ *:[i32] }:$offset))<<P:Predicate_unindexedload>><<P:Predicate_load_global>>  =>  (BUFFER_LOAD_DWORDX2_OFFSET:{ *:[v2i32] } v4i32:{ *:[v4i32] }:$srsrc, i32:{ *:[i32] }:$soffset, i32:{ *:[i32] }:$offset)
      GIR_BuildMI, /*InsnID*/0, /*Opcode*/GIMT_Encode2(AMDGPU::BUFFER_LOAD_DWORDX2_OFFSET),
      GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/0, // DstI[vdata]
      GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/0, // srsrc
      GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/1, // soffset
      GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/2, // offset
      GIR_AddImm8, /*InsnID*/0, /*Imm*/0,
      GIR_AddImm8, /*InsnID*/0, /*Imm*/0,
      GIR_MergeMemOperands, /*InsnID*/0, /*NumInsns*/1, /*MergeInsnID's*/0,
      GIR_ConstrainSelectedInstOperands, /*InsnID*/0,
      GIR_EraseFromParent, /*InsnID*/0,
      // GIR_Coverage, 3727,
      GIR_Done,
    // Label 1318: @87341
    GIM_Try, /*On fail goto*//*Label 1319*/ GIMT_Encode4(87410), // Rule ID 3729 //
      GIM_CheckMemoryAddressSpace, /*MI*/0, /*MMO*/0, /*NumAddrSpace*/3, /*AddrSpace*/1, /*AddrSpace*/4, /*AddrSpace*/6,
      GIM_CheckAtomicOrdering, /*MI*/0, /*Order*/(uint8_t)AtomicOrdering::NotAtomic,
      GIM_CheckRegBankForClass, /*MI*/0, /*Op*/0, /*RC*/GIMT_Encode2(AMDGPU::AV_64RegClassID),
      GIM_CheckPointerToAny, /*MI*/0, /*Op*/1, /*SizeInBits*/0,
      GIM_CheckComplexPattern, /*MI*/0, /*Op*/1, /*Renderer*/GIMT_Encode2(0), GIMT_Encode2(GICP_gi_mubuf_offset),
      // (ld:{ *:[v2i32] } (MUBUFOffset:{ *:[iPTR] } v4i32:{ *:[v4i32] }:$srsrc, i32:{ *:[i32] }:$soffset, i32:{ *:[i32] }:$offset))<<P:Predicate_unindexedload>><<P:Predicate_load_global>>  =>  (BUFFER_LOAD_DWORDX2_VBUFFER_OFFSET:{ *:[v2i32] } v4i32:{ *:[v4i32] }:$srsrc, i32:{ *:[i32] }:$soffset, i32:{ *:[i32] }:$offset)
      GIR_BuildMI, /*InsnID*/0, /*Opcode*/GIMT_Encode2(AMDGPU::BUFFER_LOAD_DWORDX2_VBUFFER_OFFSET),
      GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/0, // DstI[vdata]
      GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/0, // srsrc
      GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/1, // soffset
      GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/2, // offset
      GIR_AddImm8, /*InsnID*/0, /*Imm*/0,
      GIR_AddImm8, /*InsnID*/0, /*Imm*/0,
      GIR_MergeMemOperands, /*InsnID*/0, /*NumInsns*/1, /*MergeInsnID's*/0,
      GIR_ConstrainSelectedInstOperands, /*InsnID*/0,
      GIR_EraseFromParent, /*InsnID*/0,
      // GIR_Coverage, 3729,
      GIR_Done,
    // Label 1319: @87410
    GIM_Try, /*On fail goto*//*Label 1320*/ GIMT_Encode4(87482), // Rule ID 3731 //
      GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasUnrestrictedSOffset),
      GIM_CheckMemoryAddressSpace, /*MI*/0, /*MMO*/0, /*NumAddrSpace*/3, /*AddrSpace*/1, /*AddrSpace*/4, /*AddrSpace*/6,
      GIM_CheckAtomicOrdering, /*MI*/0, /*Order*/(uint8_t)AtomicOrdering::NotAtomic,
      GIM_CheckRegBankForClass, /*MI*/0, /*Op*/0, /*RC*/GIMT_Encode2(AMDGPU::AV_64RegClassID),
      GIM_CheckPointerToAny, /*MI*/0, /*Op*/1, /*SizeInBits*/0,
      GIM_CheckComplexPattern, /*MI*/0, /*Op*/1, /*Renderer*/GIMT_Encode2(0), GIMT_Encode2(GICP_gi_mubuf_offset),
      // (ld:{ *:[v2f32] } (MUBUFOffset:{ *:[iPTR] } v4i32:{ *:[v4i32] }:$srsrc, i32:{ *:[i32] }:$soffset, i32:{ *:[i32] }:$offset))<<P:Predicate_unindexedload>><<P:Predicate_load_global>>  =>  (BUFFER_LOAD_DWORDX2_OFFSET:{ *:[v2f32] } v4i32:{ *:[v4i32] }:$srsrc, i32:{ *:[i32] }:$soffset, i32:{ *:[i32] }:$offset)
      GIR_BuildMI, /*InsnID*/0, /*Opcode*/GIMT_Encode2(AMDGPU::BUFFER_LOAD_DWORDX2_OFFSET),
      GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/0, // DstI[vdata]
      GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/0, // srsrc
      GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/1, // soffset
      GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/2, // offset
      GIR_AddImm8, /*InsnID*/0, /*Imm*/0,
      GIR_AddImm8, /*InsnID*/0, /*Imm*/0,
      GIR_MergeMemOperands, /*InsnID*/0, /*NumInsns*/1, /*MergeInsnID's*/0,
      GIR_ConstrainSelectedInstOperands, /*InsnID*/0,
      GIR_EraseFromParent, /*InsnID*/0,
      // GIR_Coverage, 3731,
      GIR_Done,
    // Label 1320: @87482
    GIM_Try, /*On fail goto*//*Label 1321*/ GIMT_Encode4(87551), // Rule ID 3733 //
      GIM_CheckMemoryAddressSpace, /*MI*/0, /*MMO*/0, /*NumAddrSpace*/3, /*AddrSpace*/1, /*AddrSpace*/4, /*AddrSpace*/6,
      GIM_CheckAtomicOrdering, /*MI*/0, /*Order*/(uint8_t)AtomicOrdering::NotAtomic,
      GIM_CheckRegBankForClass, /*MI*/0, /*Op*/0, /*RC*/GIMT_Encode2(AMDGPU::AV_64RegClassID),
      GIM_CheckPointerToAny, /*MI*/0, /*Op*/1, /*SizeInBits*/0,
      GIM_CheckComplexPattern, /*MI*/0, /*Op*/1, /*Renderer*/GIMT_Encode2(0), GIMT_Encode2(GICP_gi_mubuf_offset),
      // (ld:{ *:[v2f32] } (MUBUFOffset:{ *:[iPTR] } v4i32:{ *:[v4i32] }:$srsrc, i32:{ *:[i32] }:$soffset, i32:{ *:[i32] }:$offset))<<P:Predicate_unindexedload>><<P:Predicate_load_global>>  =>  (BUFFER_LOAD_DWORDX2_VBUFFER_OFFSET:{ *:[v2f32] } v4i32:{ *:[v4i32] }:$srsrc, i32:{ *:[i32] }:$soffset, i32:{ *:[i32] }:$offset)
      GIR_BuildMI, /*InsnID*/0, /*Opcode*/GIMT_Encode2(AMDGPU::BUFFER_LOAD_DWORDX2_VBUFFER_OFFSET),
      GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/0, // DstI[vdata]
      GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/0, // srsrc
      GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/1, // soffset
      GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/2, // offset
      GIR_AddImm8, /*InsnID*/0, /*Imm*/0,
      GIR_AddImm8, /*InsnID*/0, /*Imm*/0,
      GIR_MergeMemOperands, /*InsnID*/0, /*NumInsns*/1, /*MergeInsnID's*/0,
      GIR_ConstrainSelectedInstOperands, /*InsnID*/0,
      GIR_EraseFromParent, /*InsnID*/0,
      // GIR_Coverage, 3733,
      GIR_Done,
    // Label 1321: @87551
    GIM_Try, /*On fail goto*//*Label 1322*/ GIMT_Encode4(87618), // Rule ID 6685 //
      GIM_CheckFeatures, GIMT_Encode2(GIFBS_NotLDSRequiresM0Init),
      GIM_CheckMemoryAddressSpace, /*MI*/0, /*MMO*/0, /*NumAddrSpace*/1, /*AddrSpace*/3,
      GIM_CheckAtomicOrdering, /*MI*/0, /*Order*/(uint8_t)AtomicOrdering::NotAtomic,
      GIM_CheckRegBankForClass, /*MI*/0, /*Op*/0, /*RC*/GIMT_Encode2(AMDGPU::AV_64RegClassID),
      GIM_CheckPointerToAny, /*MI*/0, /*Op*/1, /*SizeInBits*/0,
      GIM_CheckComplexPattern, /*MI*/0, /*Op*/1, /*Renderer*/GIMT_Encode2(0), GIMT_Encode2(GICP_gi_ds_64bit_4byte_aligned),
      // (ld:{ *:[v2i32] } (DS64Bit4ByteAligned:{ *:[iPTR] } i32:{ *:[i32] }:$ptr, i8:{ *:[i8] }:$offset0, i8:{ *:[i8] }:$offset1))<<P:Predicate_unindexedload>><<P:Predicate_load_local>>  =>  (DS_READ2_B32_gfx9:{ *:[v2i32] } ?:{ *:[i32] }:$ptr, ?:{ *:[i8] }:$offset0, ?:{ *:[i8] }:$offset1, 0:{ *:[i1] })
      GIR_BuildMI, /*InsnID*/0, /*Opcode*/GIMT_Encode2(AMDGPU::DS_READ2_B32_gfx9),
      GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/0, // DstI[vdst]
      GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/0, // ptr
      GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/1, // offset0
      GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/2, // offset1
      GIR_AddImm8, /*InsnID*/0, /*Imm*/0,
      GIR_MergeMemOperands, /*InsnID*/0, /*NumInsns*/1, /*MergeInsnID's*/0,
      GIR_ConstrainSelectedInstOperands, /*InsnID*/0,
      GIR_EraseFromParent, /*InsnID*/0,
      // GIR_Coverage, 6685,
      GIR_Done,
    // Label 1322: @87618
    GIM_Try, /*On fail goto*//*Label 1323*/ GIMT_Encode4(87685), // Rule ID 6689 //
      GIM_CheckFeatures, GIMT_Encode2(GIFBS_NotLDSRequiresM0Init),
      GIM_CheckMemoryAddressSpace, /*MI*/0, /*MMO*/0, /*NumAddrSpace*/1, /*AddrSpace*/3,
      GIM_CheckAtomicOrdering, /*MI*/0, /*Order*/(uint8_t)AtomicOrdering::NotAtomic,
      GIM_CheckRegBankForClass, /*MI*/0, /*Op*/0, /*RC*/GIMT_Encode2(AMDGPU::AV_64RegClassID),
      GIM_CheckPointerToAny, /*MI*/0, /*Op*/1, /*SizeInBits*/0,
      GIM_CheckComplexPattern, /*MI*/0, /*Op*/1, /*Renderer*/GIMT_Encode2(0), GIMT_Encode2(GICP_gi_ds_64bit_4byte_aligned),
      // (ld:{ *:[v2f32] } (DS64Bit4ByteAligned:{ *:[iPTR] } i32:{ *:[i32] }:$ptr, i8:{ *:[i8] }:$offset0, i8:{ *:[i8] }:$offset1))<<P:Predicate_unindexedload>><<P:Predicate_load_local>>  =>  (DS_READ2_B32_gfx9:{ *:[v2f32] } ?:{ *:[i32] }:$ptr, ?:{ *:[i8] }:$offset0, ?:{ *:[i8] }:$offset1, 0:{ *:[i1] })
      GIR_BuildMI, /*InsnID*/0, /*Opcode*/GIMT_Encode2(AMDGPU::DS_READ2_B32_gfx9),
      GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/0, // DstI[vdst]
      GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/0, // ptr
      GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/1, // offset0
      GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/2, // offset1
      GIR_AddImm8, /*InsnID*/0, /*Imm*/0,
      GIR_MergeMemOperands, /*InsnID*/0, /*NumInsns*/1, /*MergeInsnID's*/0,
      GIR_ConstrainSelectedInstOperands, /*InsnID*/0,
      GIR_EraseFromParent, /*InsnID*/0,
      // GIR_Coverage, 6689,
      GIR_Done,
    // Label 1323: @87685
    GIM_Try, /*On fail goto*//*Label 1324*/ GIMT_Encode4(87754), // Rule ID 3037 //
      GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasFlatGlobalInsts),
      GIM_CheckMemoryAddressSpace, /*MI*/0, /*MMO*/0, /*NumAddrSpace*/3, /*AddrSpace*/1, /*AddrSpace*/4, /*AddrSpace*/6,
      GIM_CheckAtomicOrdering, /*MI*/0, /*Order*/(uint8_t)AtomicOrdering::NotAtomic,
      GIM_CheckRegBankForClass, /*MI*/0, /*Op*/0, /*RC*/GIMT_Encode2(AMDGPU::AV_64RegClassID),
      GIM_CheckPointerToAny, /*MI*/0, /*Op*/1, /*SizeInBits*/0,
      GIM_CheckComplexPattern, /*MI*/0, /*Op*/1, /*Renderer*/GIMT_Encode2(0), GIMT_Encode2(GICP_gi_global_saddr),
      // (ld:{ *:[v2i32] } (GlobalSAddr:{ *:[iPTR] } SReg_64:{ *:[i64] }:$saddr, VGPR_32:{ *:[i32] }:$voffset, i32:{ *:[i32] }:$offset))<<P:Predicate_unindexedload>><<P:Predicate_load_global>>  =>  (GLOBAL_LOAD_DWORDX2_SADDR:{ *:[v2i32] } ?:{ *:[i64] }:$saddr, ?:{ *:[i32] }:$voffset, ?:{ *:[i32] }:$offset, 0:{ *:[i32] })
      GIR_BuildMI, /*InsnID*/0, /*Opcode*/GIMT_Encode2(AMDGPU::GLOBAL_LOAD_DWORDX2_SADDR),
      GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/0, // DstI[vdst]
      GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/0, // saddr
      GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/1, // voffset
      GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/2, // offset
      GIR_AddImm8, /*InsnID*/0, /*Imm*/0,
      GIR_MergeMemOperands, /*InsnID*/0, /*NumInsns*/1, /*MergeInsnID's*/0,
      GIR_ConstrainSelectedInstOperands, /*InsnID*/0,
      GIR_EraseFromParent, /*InsnID*/0,
      // GIR_Coverage, 3037,
      GIR_Done,
    // Label 1324: @87754
    GIM_Try, /*On fail goto*//*Label 1325*/ GIMT_Encode4(87823), // Rule ID 3041 //
      GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasFlatGlobalInsts),
      GIM_CheckMemoryAddressSpace, /*MI*/0, /*MMO*/0, /*NumAddrSpace*/3, /*AddrSpace*/1, /*AddrSpace*/4, /*AddrSpace*/6,
      GIM_CheckAtomicOrdering, /*MI*/0, /*Order*/(uint8_t)AtomicOrdering::NotAtomic,
      GIM_CheckRegBankForClass, /*MI*/0, /*Op*/0, /*RC*/GIMT_Encode2(AMDGPU::AV_64RegClassID),
      GIM_CheckPointerToAny, /*MI*/0, /*Op*/1, /*SizeInBits*/0,
      GIM_CheckComplexPattern, /*MI*/0, /*Op*/1, /*Renderer*/GIMT_Encode2(0), GIMT_Encode2(GICP_gi_global_saddr),
      // (ld:{ *:[v2f32] } (GlobalSAddr:{ *:[iPTR] } SReg_64:{ *:[i64] }:$saddr, VGPR_32:{ *:[i32] }:$voffset, i32:{ *:[i32] }:$offset))<<P:Predicate_unindexedload>><<P:Predicate_load_global>>  =>  (GLOBAL_LOAD_DWORDX2_SADDR:{ *:[v2f32] } ?:{ *:[i64] }:$saddr, ?:{ *:[i32] }:$voffset, ?:{ *:[i32] }:$offset, 0:{ *:[i32] })
      GIR_BuildMI, /*InsnID*/0, /*Opcode*/GIMT_Encode2(AMDGPU::GLOBAL_LOAD_DWORDX2_SADDR),
      GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/0, // DstI[vdst]
      GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/0, // saddr
      GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/1, // voffset
      GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/2, // offset
      GIR_AddImm8, /*InsnID*/0, /*Imm*/0,
      GIR_MergeMemOperands, /*InsnID*/0, /*NumInsns*/1, /*MergeInsnID's*/0,
      GIR_ConstrainSelectedInstOperands, /*InsnID*/0,
      GIR_EraseFromParent, /*InsnID*/0,
      // GIR_Coverage, 3041,
      GIR_Done,
    // Label 1325: @87823
    GIM_Try, /*On fail goto*//*Label 1326*/ GIMT_Encode4(87887), // Rule ID 3036 //
      GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasFlatGlobalInsts),
      GIM_CheckMemoryAddressSpace, /*MI*/0, /*MMO*/0, /*NumAddrSpace*/3, /*AddrSpace*/1, /*AddrSpace*/4, /*AddrSpace*/6,
      GIM_CheckAtomicOrdering, /*MI*/0, /*Order*/(uint8_t)AtomicOrdering::NotAtomic,
      GIM_CheckRegBankForClass, /*MI*/0, /*Op*/0, /*RC*/GIMT_Encode2(AMDGPU::AV_64RegClassID),
      GIM_CheckPointerToAny, /*MI*/0, /*Op*/1, /*SizeInBits*/0,
      GIM_CheckComplexPattern, /*MI*/0, /*Op*/1, /*Renderer*/GIMT_Encode2(0), GIMT_Encode2(GICP_gi_global_offset),
      // (ld:{ *:[v2i32] } (GlobalOffset:{ *:[iPTR] } VReg_64:{ *:[i64] }:$vaddr, i32:{ *:[i32] }:$offset))<<P:Predicate_unindexedload>><<P:Predicate_load_global>>  =>  (GLOBAL_LOAD_DWORDX2:{ *:[v2i32] } ?:{ *:[i64] }:$vaddr, ?:{ *:[i32] }:$offset)
      GIR_BuildMI, /*InsnID*/0, /*Opcode*/GIMT_Encode2(AMDGPU::GLOBAL_LOAD_DWORDX2),
      GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/0, // DstI[vdst]
      GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/0, // vaddr
      GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/1, // offset
      GIR_AddImm8, /*InsnID*/0, /*Imm*/0,
      GIR_MergeMemOperands, /*InsnID*/0, /*NumInsns*/1, /*MergeInsnID's*/0,
      GIR_ConstrainSelectedInstOperands, /*InsnID*/0,
      GIR_EraseFromParent, /*InsnID*/0,
      // GIR_Coverage, 3036,
      GIR_Done,
    // Label 1326: @87887
    GIM_Try, /*On fail goto*//*Label 1327*/ GIMT_Encode4(87951), // Rule ID 3040 //
      GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasFlatGlobalInsts),
      GIM_CheckMemoryAddressSpace, /*MI*/0, /*MMO*/0, /*NumAddrSpace*/3, /*AddrSpace*/1, /*AddrSpace*/4, /*AddrSpace*/6,
      GIM_CheckAtomicOrdering, /*MI*/0, /*Order*/(uint8_t)AtomicOrdering::NotAtomic,
      GIM_CheckRegBankForClass, /*MI*/0, /*Op*/0, /*RC*/GIMT_Encode2(AMDGPU::AV_64RegClassID),
      GIM_CheckPointerToAny, /*MI*/0, /*Op*/1, /*SizeInBits*/0,
      GIM_CheckComplexPattern, /*MI*/0, /*Op*/1, /*Renderer*/GIMT_Encode2(0), GIMT_Encode2(GICP_gi_global_offset),
      // (ld:{ *:[v2f32] } (GlobalOffset:{ *:[iPTR] } VReg_64:{ *:[i64] }:$vaddr, i32:{ *:[i32] }:$offset))<<P:Predicate_unindexedload>><<P:Predicate_load_global>>  =>  (GLOBAL_LOAD_DWORDX2:{ *:[v2f32] } ?:{ *:[i64] }:$vaddr, ?:{ *:[i32] }:$offset)
      GIR_BuildMI, /*InsnID*/0, /*Opcode*/GIMT_Encode2(AMDGPU::GLOBAL_LOAD_DWORDX2),
      GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/0, // DstI[vdst]
      GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/0, // vaddr
      GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/1, // offset
      GIR_AddImm8, /*InsnID*/0, /*Imm*/0,
      GIR_MergeMemOperands, /*InsnID*/0, /*NumInsns*/1, /*MergeInsnID's*/0,
      GIR_ConstrainSelectedInstOperands, /*InsnID*/0,
      GIR_EraseFromParent, /*InsnID*/0,
      // GIR_Coverage, 3040,
      GIR_Done,
    // Label 1327: @87951
    GIM_Try, /*On fail goto*//*Label 1328*/ GIMT_Encode4(88016), // Rule ID 2793 //
      GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasFlatAddressSpace),
      GIM_CheckMemoryAddressSpace, /*MI*/0, /*MMO*/0, /*NumAddrSpace*/4, /*AddrSpace*/0, /*AddrSpace*/1, /*AddrSpace*/4, /*AddrSpace*/6,
      GIM_CheckAtomicOrdering, /*MI*/0, /*Order*/(uint8_t)AtomicOrdering::NotAtomic,
      GIM_CheckRegBankForClass, /*MI*/0, /*Op*/0, /*RC*/GIMT_Encode2(AMDGPU::AV_64RegClassID),
      GIM_CheckPointerToAny, /*MI*/0, /*Op*/1, /*SizeInBits*/0,
      GIM_CheckComplexPattern, /*MI*/0, /*Op*/1, /*Renderer*/GIMT_Encode2(0), GIMT_Encode2(GICP_gi_flat_offset),
      // (ld:{ *:[v2i32] } (FlatOffset:{ *:[iPTR] } i64:{ *:[i64] }:$vaddr, i32:{ *:[i32] }:$offset))<<P:Predicate_unindexedload>><<P:Predicate_load_flat>>  =>  (FLAT_LOAD_DWORDX2:{ *:[v2i32] } ?:{ *:[i64] }:$vaddr, ?:{ *:[i32] }:$offset)
      GIR_BuildMI, /*InsnID*/0, /*Opcode*/GIMT_Encode2(AMDGPU::FLAT_LOAD_DWORDX2),
      GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/0, // DstI[vdst]
      GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/0, // vaddr
      GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/1, // offset
      GIR_AddImm8, /*InsnID*/0, /*Imm*/0,
      GIR_MergeMemOperands, /*InsnID*/0, /*NumInsns*/1, /*MergeInsnID's*/0,
      GIR_ConstrainSelectedInstOperands, /*InsnID*/0,
      GIR_EraseFromParent, /*InsnID*/0,
      // GIR_Coverage, 2793,
      GIR_Done,
    // Label 1328: @88016
    GIM_Try, /*On fail goto*//*Label 1329*/ GIMT_Encode4(88081), // Rule ID 2795 //
      GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasFlatAddressSpace),
      GIM_CheckMemoryAddressSpace, /*MI*/0, /*MMO*/0, /*NumAddrSpace*/4, /*AddrSpace*/0, /*AddrSpace*/1, /*AddrSpace*/4, /*AddrSpace*/6,
      GIM_CheckAtomicOrdering, /*MI*/0, /*Order*/(uint8_t)AtomicOrdering::NotAtomic,
      GIM_CheckRegBankForClass, /*MI*/0, /*Op*/0, /*RC*/GIMT_Encode2(AMDGPU::AV_64RegClassID),
      GIM_CheckPointerToAny, /*MI*/0, /*Op*/1, /*SizeInBits*/0,
      GIM_CheckComplexPattern, /*MI*/0, /*Op*/1, /*Renderer*/GIMT_Encode2(0), GIMT_Encode2(GICP_gi_flat_offset),
      // (ld:{ *:[v2f32] } (FlatOffset:{ *:[iPTR] } i64:{ *:[i64] }:$vaddr, i32:{ *:[i32] }:$offset))<<P:Predicate_unindexedload>><<P:Predicate_load_flat>>  =>  (FLAT_LOAD_DWORDX2:{ *:[v2f32] } ?:{ *:[i64] }:$vaddr, ?:{ *:[i32] }:$offset)
      GIR_BuildMI, /*InsnID*/0, /*Opcode*/GIMT_Encode2(AMDGPU::FLAT_LOAD_DWORDX2),
      GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/0, // DstI[vdst]
      GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/0, // vaddr
      GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/1, // offset
      GIR_AddImm8, /*InsnID*/0, /*Imm*/0,
      GIR_MergeMemOperands, /*InsnID*/0, /*NumInsns*/1, /*MergeInsnID's*/0,
      GIR_ConstrainSelectedInstOperands, /*InsnID*/0,
      GIR_EraseFromParent, /*InsnID*/0,
      // GIR_Coverage, 2795,
      GIR_Done,
    // Label 1329: @88081
    GIM_Reject,
    // Label 829: @88082
    GIM_Try, /*On fail goto*//*Label 1330*/ GIMT_Encode4(88152), // Rule ID 2574 //
      GIM_CheckFeatures, GIMT_Encode2(GIFBS_isGFX9Plus),
      GIM_CheckMemorySizeEqualToLLT, /*MI*/0, /*MMO*/0, /*OpIdx*/0,
      GIM_CheckAtomicOrdering, /*MI*/0, /*Order*/(uint8_t)AtomicOrdering::NotAtomic,
      GIM_CheckRegBankForClass, /*MI*/0, /*Op*/0, /*RC*/GIMT_Encode2(AMDGPU::SReg_128RegClassID),
      GIM_CheckPointerToAny, /*MI*/0, /*Op*/1, /*SizeInBits*/0,
      GIM_CheckCxxInsnPredicate, /*MI*/0, /*FnId*/GIMT_Encode2(GICXXPred_MI_Predicate_smrd_load),
      GIM_CheckComplexPattern, /*MI*/0, /*Op*/1, /*Renderer*/GIMT_Encode2(0), GIMT_Encode2(GICP_gi_smrd_sgpr_imm),
      // (ld:{ *:[v2i64] } (SMRDSgprImm:{ *:[iPTR] } i64:{ *:[i64] }:$sbase, i32:{ *:[i32] }:$soffset, i32:{ *:[i32] }:$offset))<<P:Predicate_unindexedload>><<P:Predicate_load>><<P:Predicate_smrd_load>>  =>  (S_LOAD_DWORDX4_SGPR_IMM:{ *:[v2i64] } ?:{ *:[i64] }:$sbase, ?:{ *:[i32] }:$soffset, ?:{ *:[i32] }:$offset, 0:{ *:[i32] })
      GIR_BuildMI, /*InsnID*/0, /*Opcode*/GIMT_Encode2(AMDGPU::S_LOAD_DWORDX4_SGPR_IMM),
      GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/0, // DstI[sdst]
      GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/0, // sbase
      GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/1, // soffset
      GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/2, // offset
      GIR_AddImm8, /*InsnID*/0, /*Imm*/0,
      GIR_MergeMemOperands, /*InsnID*/0, /*NumInsns*/1, /*MergeInsnID's*/0,
      GIR_ConstrainSelectedInstOperands, /*InsnID*/0,
      GIR_EraseFromParent, /*InsnID*/0,
      // GIR_Coverage, 2574,
      GIR_Done,
    // Label 1330: @88152
    GIM_Try, /*On fail goto*//*Label 1331*/ GIMT_Encode4(88222), // Rule ID 2580 //
      GIM_CheckFeatures, GIMT_Encode2(GIFBS_isGFX9Plus),
      GIM_CheckMemorySizeEqualToLLT, /*MI*/0, /*MMO*/0, /*OpIdx*/0,
      GIM_CheckAtomicOrdering, /*MI*/0, /*Order*/(uint8_t)AtomicOrdering::NotAtomic,
      GIM_CheckRegBankForClass, /*MI*/0, /*Op*/0, /*RC*/GIMT_Encode2(AMDGPU::SReg_128RegClassID),
      GIM_CheckPointerToAny, /*MI*/0, /*Op*/1, /*SizeInBits*/0,
      GIM_CheckCxxInsnPredicate, /*MI*/0, /*FnId*/GIMT_Encode2(GICXXPred_MI_Predicate_smrd_load),
      GIM_CheckComplexPattern, /*MI*/0, /*Op*/1, /*Renderer*/GIMT_Encode2(0), GIMT_Encode2(GICP_gi_smrd_sgpr_imm),
      // (ld:{ *:[v2f64] } (SMRDSgprImm:{ *:[iPTR] } i64:{ *:[i64] }:$sbase, i32:{ *:[i32] }:$soffset, i32:{ *:[i32] }:$offset))<<P:Predicate_unindexedload>><<P:Predicate_load>><<P:Predicate_smrd_load>>  =>  (S_LOAD_DWORDX4_SGPR_IMM:{ *:[v2f64] } ?:{ *:[i64] }:$sbase, ?:{ *:[i32] }:$soffset, ?:{ *:[i32] }:$offset, 0:{ *:[i32] })
      GIR_BuildMI, /*InsnID*/0, /*Opcode*/GIMT_Encode2(AMDGPU::S_LOAD_DWORDX4_SGPR_IMM),
      GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/0, // DstI[sdst]
      GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/0, // sbase
      GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/1, // soffset
      GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/2, // offset
      GIR_AddImm8, /*InsnID*/0, /*Imm*/0,
      GIR_MergeMemOperands, /*InsnID*/0, /*NumInsns*/1, /*MergeInsnID's*/0,
      GIR_ConstrainSelectedInstOperands, /*InsnID*/0,
      GIR_EraseFromParent, /*InsnID*/0,
      // GIR_Coverage, 2580,
      GIR_Done,
    // Label 1331: @88222
    GIM_Try, /*On fail goto*//*Label 1332*/ GIMT_Encode4(88297), // Rule ID 6871 //
      GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasUnalignedAccessMode_LDSRequiresM0Init),
      GIM_CheckMemorySizeEqualToLLT, /*MI*/0, /*MMO*/0, /*OpIdx*/0,
      GIM_CheckMemoryAddressSpace, /*MI*/0, /*MMO*/0, /*NumAddrSpace*/1, /*AddrSpace*/3,
      GIM_CheckMemoryAddressSpace, /*MI*/0, /*MMO*/0, /*NumAddrSpace*/1, /*AddrSpace*/3,
      GIM_CheckAtomicOrdering, /*MI*/0, /*Order*/(uint8_t)AtomicOrdering::NotAtomic,
      GIM_CheckRegBankForClass, /*MI*/0, /*Op*/0, /*RC*/GIMT_Encode2(AMDGPU::AV_128RegClassID),
      GIM_CheckPointerToAny, /*MI*/0, /*Op*/1, /*SizeInBits*/0,
      GIM_CheckCxxInsnPredicate, /*MI*/0, /*FnId*/GIMT_Encode2(GICXXPred_MI_Predicate_load_align_less_than_4_local_m0),
      GIM_CheckComplexPattern, /*MI*/0, /*Op*/1, /*Renderer*/GIMT_Encode2(0), GIMT_Encode2(GICP_gi_ds_1addr_1offset),
      // (AMDGPUld_glue:{ *:[v2i64] } (DS1Addr1Offset:{ *:[iPTR] } i32:{ *:[i32] }:$ptr, i32:{ *:[i32] }:$offset))<<P:Predicate_unindexedload_glue>><<P:Predicate_load_glue>><<P:Predicate_load_local_m0>><<P:Predicate_load_align_less_than_4_local_m0>>  =>  (DS_READ_B128:{ *:[v2i64] } ?:{ *:[i32] }:$ptr, offset:{ *:[i32] }:$offset, 0:{ *:[i1] })
      GIR_BuildMI, /*InsnID*/0, /*Opcode*/GIMT_Encode2(AMDGPU::DS_READ_B128),
      GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/0, // DstI[vdst]
      GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/0, // ptr
      GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/1, // offset
      GIR_AddImm8, /*InsnID*/0, /*Imm*/0,
      GIR_MergeMemOperands, /*InsnID*/0, /*NumInsns*/1, /*MergeInsnID's*/0,
      GIR_ConstrainSelectedInstOperands, /*InsnID*/0,
      GIR_EraseFromParent, /*InsnID*/0,
      // GIR_Coverage, 6871,
      GIR_Done,
    // Label 1332: @88297
    GIM_Try, /*On fail goto*//*Label 1333*/ GIMT_Encode4(88372), // Rule ID 6875 //
      GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasUnalignedAccessMode_LDSRequiresM0Init),
      GIM_CheckMemorySizeEqualToLLT, /*MI*/0, /*MMO*/0, /*OpIdx*/0,
      GIM_CheckMemoryAddressSpace, /*MI*/0, /*MMO*/0, /*NumAddrSpace*/1, /*AddrSpace*/3,
      GIM_CheckMemoryAddressSpace, /*MI*/0, /*MMO*/0, /*NumAddrSpace*/1, /*AddrSpace*/3,
      GIM_CheckAtomicOrdering, /*MI*/0, /*Order*/(uint8_t)AtomicOrdering::NotAtomic,
      GIM_CheckRegBankForClass, /*MI*/0, /*Op*/0, /*RC*/GIMT_Encode2(AMDGPU::AV_128RegClassID),
      GIM_CheckPointerToAny, /*MI*/0, /*Op*/1, /*SizeInBits*/0,
      GIM_CheckCxxInsnPredicate, /*MI*/0, /*FnId*/GIMT_Encode2(GICXXPred_MI_Predicate_load_align_less_than_4_local_m0),
      GIM_CheckComplexPattern, /*MI*/0, /*Op*/1, /*Renderer*/GIMT_Encode2(0), GIMT_Encode2(GICP_gi_ds_1addr_1offset),
      // (AMDGPUld_glue:{ *:[v2f64] } (DS1Addr1Offset:{ *:[iPTR] } i32:{ *:[i32] }:$ptr, i32:{ *:[i32] }:$offset))<<P:Predicate_unindexedload_glue>><<P:Predicate_load_glue>><<P:Predicate_load_local_m0>><<P:Predicate_load_align_less_than_4_local_m0>>  =>  (DS_READ_B128:{ *:[v2f64] } ?:{ *:[i32] }:$ptr, offset:{ *:[i32] }:$offset, 0:{ *:[i1] })
      GIR_BuildMI, /*InsnID*/0, /*Opcode*/GIMT_Encode2(AMDGPU::DS_READ_B128),
      GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/0, // DstI[vdst]
      GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/0, // ptr
      GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/1, // offset
      GIR_AddImm8, /*InsnID*/0, /*Imm*/0,
      GIR_MergeMemOperands, /*InsnID*/0, /*NumInsns*/1, /*MergeInsnID's*/0,
      GIR_ConstrainSelectedInstOperands, /*InsnID*/0,
      GIR_EraseFromParent, /*InsnID*/0,
      // GIR_Coverage, 6875,
      GIR_Done,
    // Label 1333: @88372
    GIM_Try, /*On fail goto*//*Label 1334*/ GIMT_Encode4(88442), // Rule ID 6795 //
      GIM_CheckFeatures, GIMT_Encode2(GIFBS_LDSRequiresM0Init_isGFX7Plus),
      GIM_CheckMemorySizeEqualToLLT, /*MI*/0, /*MMO*/0, /*OpIdx*/0,
      GIM_CheckMemoryAddressSpace, /*MI*/0, /*MMO*/0, /*NumAddrSpace*/1, /*AddrSpace*/3,
      GIM_CheckMemoryAlignment, /*MI*/0, /*MMO*/0, /*MinAlign*/16,
      GIM_CheckAtomicOrdering, /*MI*/0, /*Order*/(uint8_t)AtomicOrdering::NotAtomic,
      GIM_CheckRegBankForClass, /*MI*/0, /*Op*/0, /*RC*/GIMT_Encode2(AMDGPU::AV_128RegClassID),
      GIM_CheckPointerToAny, /*MI*/0, /*Op*/1, /*SizeInBits*/0,
      GIM_CheckComplexPattern, /*MI*/0, /*Op*/1, /*Renderer*/GIMT_Encode2(0), GIMT_Encode2(GICP_gi_ds_1addr_1offset),
      // (AMDGPUld_glue:{ *:[v2i64] } (DS1Addr1Offset:{ *:[iPTR] } i32:{ *:[i32] }:$ptr, i32:{ *:[i32] }:$offset))<<P:Predicate_unindexedload_glue>><<P:Predicate_load_glue>><<P:Predicate_load_local_m0>><<P:Predicate_load_align16_local_m0>>  =>  (DS_READ_B128:{ *:[v2i64] } ?:{ *:[i32] }:$ptr, offset:{ *:[i32] }:$offset, 0:{ *:[i1] })
      GIR_BuildMI, /*InsnID*/0, /*Opcode*/GIMT_Encode2(AMDGPU::DS_READ_B128),
      GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/0, // DstI[vdst]
      GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/0, // ptr
      GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/1, // offset
      GIR_AddImm8, /*InsnID*/0, /*Imm*/0,
      GIR_MergeMemOperands, /*InsnID*/0, /*NumInsns*/1, /*MergeInsnID's*/0,
      GIR_ConstrainSelectedInstOperands, /*InsnID*/0,
      GIR_EraseFromParent, /*InsnID*/0,
      // GIR_Coverage, 6795,
      GIR_Done,
    // Label 1334: @88442
    GIM_Try, /*On fail goto*//*Label 1335*/ GIMT_Encode4(88512), // Rule ID 6799 //
      GIM_CheckFeatures, GIMT_Encode2(GIFBS_LDSRequiresM0Init_isGFX7Plus),
      GIM_CheckMemorySizeEqualToLLT, /*MI*/0, /*MMO*/0, /*OpIdx*/0,
      GIM_CheckMemoryAddressSpace, /*MI*/0, /*MMO*/0, /*NumAddrSpace*/1, /*AddrSpace*/3,
      GIM_CheckMemoryAlignment, /*MI*/0, /*MMO*/0, /*MinAlign*/16,
      GIM_CheckAtomicOrdering, /*MI*/0, /*Order*/(uint8_t)AtomicOrdering::NotAtomic,
      GIM_CheckRegBankForClass, /*MI*/0, /*Op*/0, /*RC*/GIMT_Encode2(AMDGPU::AV_128RegClassID),
      GIM_CheckPointerToAny, /*MI*/0, /*Op*/1, /*SizeInBits*/0,
      GIM_CheckComplexPattern, /*MI*/0, /*Op*/1, /*Renderer*/GIMT_Encode2(0), GIMT_Encode2(GICP_gi_ds_1addr_1offset),
      // (AMDGPUld_glue:{ *:[v2f64] } (DS1Addr1Offset:{ *:[iPTR] } i32:{ *:[i32] }:$ptr, i32:{ *:[i32] }:$offset))<<P:Predicate_unindexedload_glue>><<P:Predicate_load_glue>><<P:Predicate_load_local_m0>><<P:Predicate_load_align16_local_m0>>  =>  (DS_READ_B128:{ *:[v2f64] } ?:{ *:[i32] }:$ptr, offset:{ *:[i32] }:$offset, 0:{ *:[i1] })
      GIR_BuildMI, /*InsnID*/0, /*Opcode*/GIMT_Encode2(AMDGPU::DS_READ_B128),
      GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/0, // DstI[vdst]
      GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/0, // ptr
      GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/1, // offset
      GIR_AddImm8, /*InsnID*/0, /*Imm*/0,
      GIR_MergeMemOperands, /*InsnID*/0, /*NumInsns*/1, /*MergeInsnID's*/0,
      GIR_ConstrainSelectedInstOperands, /*InsnID*/0,
      GIR_EraseFromParent, /*InsnID*/0,
      // GIR_Coverage, 6799,
      GIR_Done,
    // Label 1335: @88512
    GIM_Try, /*On fail goto*//*Label 1336*/ GIMT_Encode4(88574), // Rule ID 2570 //
      GIM_CheckMemorySizeEqualToLLT, /*MI*/0, /*MMO*/0, /*OpIdx*/0,
      GIM_CheckAtomicOrdering, /*MI*/0, /*Order*/(uint8_t)AtomicOrdering::NotAtomic,
      GIM_CheckRegBankForClass, /*MI*/0, /*Op*/0, /*RC*/GIMT_Encode2(AMDGPU::SReg_128RegClassID),
      GIM_CheckPointerToAny, /*MI*/0, /*Op*/1, /*SizeInBits*/0,
      GIM_CheckCxxInsnPredicate, /*MI*/0, /*FnId*/GIMT_Encode2(GICXXPred_MI_Predicate_smrd_load),
      GIM_CheckComplexPattern, /*MI*/0, /*Op*/1, /*Renderer*/GIMT_Encode2(0), GIMT_Encode2(GICP_gi_smrd_imm),
      // (ld:{ *:[v2i64] } (SMRDImm:{ *:[iPTR] } i64:{ *:[i64] }:$sbase, i32:{ *:[i32] }:$offset))<<P:Predicate_unindexedload>><<P:Predicate_load>><<P:Predicate_smrd_load>>  =>  (S_LOAD_DWORDX4_IMM:{ *:[v2i64] } ?:{ *:[i64] }:$sbase, ?:{ *:[i32] }:$offset, 0:{ *:[i32] })
      GIR_BuildMI, /*InsnID*/0, /*Opcode*/GIMT_Encode2(AMDGPU::S_LOAD_DWORDX4_IMM),
      GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/0, // DstI[sdst]
      GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/0, // sbase
      GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/1, // offset
      GIR_AddImm8, /*InsnID*/0, /*Imm*/0,
      GIR_MergeMemOperands, /*InsnID*/0, /*NumInsns*/1, /*MergeInsnID's*/0,
      GIR_ConstrainSelectedInstOperands, /*InsnID*/0,
      GIR_EraseFromParent, /*InsnID*/0,
      // GIR_Coverage, 2570,
      GIR_Done,
    // Label 1336: @88574
    GIM_Try, /*On fail goto*//*Label 1337*/ GIMT_Encode4(88639), // Rule ID 2571 //
      GIM_CheckFeatures, GIMT_Encode2(GIFBS_isGFX7Only),
      GIM_CheckMemorySizeEqualToLLT, /*MI*/0, /*MMO*/0, /*OpIdx*/0,
      GIM_CheckAtomicOrdering, /*MI*/0, /*Order*/(uint8_t)AtomicOrdering::NotAtomic,
      GIM_CheckRegBankForClass, /*MI*/0, /*Op*/0, /*RC*/GIMT_Encode2(AMDGPU::SReg_128RegClassID),
      GIM_CheckPointerToAny, /*MI*/0, /*Op*/1, /*SizeInBits*/0,
      GIM_CheckCxxInsnPredicate, /*MI*/0, /*FnId*/GIMT_Encode2(GICXXPred_MI_Predicate_smrd_load),
      GIM_CheckComplexPattern, /*MI*/0, /*Op*/1, /*Renderer*/GIMT_Encode2(0), GIMT_Encode2(GICP_gi_smrd_imm32),
      // (ld:{ *:[v2i64] } (SMRDImm32:{ *:[iPTR] } i64:{ *:[i64] }:$sbase, i32:{ *:[i32] }:$offset))<<P:Predicate_unindexedload>><<P:Predicate_load>><<P:Predicate_smrd_load>>  =>  (S_LOAD_DWORDX4_IMM_ci:{ *:[v2i64] } ?:{ *:[i64] }:$sbase, ?:{ *:[i32] }:$offset, 0:{ *:[i32] })
      GIR_BuildMI, /*InsnID*/0, /*Opcode*/GIMT_Encode2(AMDGPU::S_LOAD_DWORDX4_IMM_ci),
      GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/0, // DstI[sdst]
      GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/0, // sbase
      GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/1, // offset
      GIR_AddImm8, /*InsnID*/0, /*Imm*/0,
      GIR_MergeMemOperands, /*InsnID*/0, /*NumInsns*/1, /*MergeInsnID's*/0,
      GIR_ConstrainSelectedInstOperands, /*InsnID*/0,
      GIR_EraseFromParent, /*InsnID*/0,
      // GIR_Coverage, 2571,
      GIR_Done,
    // Label 1337: @88639
    GIM_Try, /*On fail goto*//*Label 1338*/ GIMT_Encode4(88704), // Rule ID 2572 //
      GIM_CheckFeatures, GIMT_Encode2(GIFBS_isNotGFX9Plus),
      GIM_CheckMemorySizeEqualToLLT, /*MI*/0, /*MMO*/0, /*OpIdx*/0,
      GIM_CheckAtomicOrdering, /*MI*/0, /*Order*/(uint8_t)AtomicOrdering::NotAtomic,
      GIM_CheckRegBankForClass, /*MI*/0, /*Op*/0, /*RC*/GIMT_Encode2(AMDGPU::SReg_128RegClassID),
      GIM_CheckPointerToAny, /*MI*/0, /*Op*/1, /*SizeInBits*/0,
      GIM_CheckCxxInsnPredicate, /*MI*/0, /*FnId*/GIMT_Encode2(GICXXPred_MI_Predicate_smrd_load),
      GIM_CheckComplexPattern, /*MI*/0, /*Op*/1, /*Renderer*/GIMT_Encode2(0), GIMT_Encode2(GICP_gi_smrd_sgpr),
      // (ld:{ *:[v2i64] } (SMRDSgpr:{ *:[iPTR] } i64:{ *:[i64] }:$sbase, i32:{ *:[i32] }:$soffset))<<P:Predicate_unindexedload>><<P:Predicate_load>><<P:Predicate_smrd_load>>  =>  (S_LOAD_DWORDX4_SGPR:{ *:[v2i64] } ?:{ *:[i64] }:$sbase, ?:{ *:[i32] }:$soffset, 0:{ *:[i32] })
      GIR_BuildMI, /*InsnID*/0, /*Opcode*/GIMT_Encode2(AMDGPU::S_LOAD_DWORDX4_SGPR),
      GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/0, // DstI[sdst]
      GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/0, // sbase
      GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/1, // soffset
      GIR_AddImm8, /*InsnID*/0, /*Imm*/0,
      GIR_MergeMemOperands, /*InsnID*/0, /*NumInsns*/1, /*MergeInsnID's*/0,
      GIR_ConstrainSelectedInstOperands, /*InsnID*/0,
      GIR_EraseFromParent, /*InsnID*/0,
      // GIR_Coverage, 2572,
      GIR_Done,
    // Label 1338: @88704
    GIM_Try, /*On fail goto*//*Label 1339*/ GIMT_Encode4(88772), // Rule ID 2573 //
      GIM_CheckFeatures, GIMT_Encode2(GIFBS_isGFX9Plus),
      GIM_CheckMemorySizeEqualToLLT, /*MI*/0, /*MMO*/0, /*OpIdx*/0,
      GIM_CheckAtomicOrdering, /*MI*/0, /*Order*/(uint8_t)AtomicOrdering::NotAtomic,
      GIM_CheckRegBankForClass, /*MI*/0, /*Op*/0, /*RC*/GIMT_Encode2(AMDGPU::SReg_128RegClassID),
      GIM_CheckPointerToAny, /*MI*/0, /*Op*/1, /*SizeInBits*/0,
      GIM_CheckCxxInsnPredicate, /*MI*/0, /*FnId*/GIMT_Encode2(GICXXPred_MI_Predicate_smrd_load),
      GIM_CheckComplexPattern, /*MI*/0, /*Op*/1, /*Renderer*/GIMT_Encode2(0), GIMT_Encode2(GICP_gi_smrd_sgpr),
      // (ld:{ *:[v2i64] } (SMRDSgpr:{ *:[iPTR] } i64:{ *:[i64] }:$sbase, i32:{ *:[i32] }:$soffset))<<P:Predicate_unindexedload>><<P:Predicate_load>><<P:Predicate_smrd_load>>  =>  (S_LOAD_DWORDX4_SGPR_IMM:{ *:[v2i64] } ?:{ *:[i64] }:$sbase, ?:{ *:[i32] }:$soffset, 0:{ *:[i32] }, 0:{ *:[i32] })
      GIR_BuildMI, /*InsnID*/0, /*Opcode*/GIMT_Encode2(AMDGPU::S_LOAD_DWORDX4_SGPR_IMM),
      GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/0, // DstI[sdst]
      GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/0, // sbase
      GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/1, // soffset
      GIR_AddImm8, /*InsnID*/0, /*Imm*/0,
      GIR_AddImm8, /*InsnID*/0, /*Imm*/0,
      GIR_MergeMemOperands, /*InsnID*/0, /*NumInsns*/1, /*MergeInsnID's*/0,
      GIR_ConstrainSelectedInstOperands, /*InsnID*/0,
      GIR_EraseFromParent, /*InsnID*/0,
      // GIR_Coverage, 2573,
      GIR_Done,
    // Label 1339: @88772
    GIM_Try, /*On fail goto*//*Label 1340*/ GIMT_Encode4(88834), // Rule ID 2576 //
      GIM_CheckMemorySizeEqualToLLT, /*MI*/0, /*MMO*/0, /*OpIdx*/0,
      GIM_CheckAtomicOrdering, /*MI*/0, /*Order*/(uint8_t)AtomicOrdering::NotAtomic,
      GIM_CheckRegBankForClass, /*MI*/0, /*Op*/0, /*RC*/GIMT_Encode2(AMDGPU::SReg_128RegClassID),
      GIM_CheckPointerToAny, /*MI*/0, /*Op*/1, /*SizeInBits*/0,
      GIM_CheckCxxInsnPredicate, /*MI*/0, /*FnId*/GIMT_Encode2(GICXXPred_MI_Predicate_smrd_load),
      GIM_CheckComplexPattern, /*MI*/0, /*Op*/1, /*Renderer*/GIMT_Encode2(0), GIMT_Encode2(GICP_gi_smrd_imm),
      // (ld:{ *:[v2f64] } (SMRDImm:{ *:[iPTR] } i64:{ *:[i64] }:$sbase, i32:{ *:[i32] }:$offset))<<P:Predicate_unindexedload>><<P:Predicate_load>><<P:Predicate_smrd_load>>  =>  (S_LOAD_DWORDX4_IMM:{ *:[v2f64] } ?:{ *:[i64] }:$sbase, ?:{ *:[i32] }:$offset, 0:{ *:[i32] })
      GIR_BuildMI, /*InsnID*/0, /*Opcode*/GIMT_Encode2(AMDGPU::S_LOAD_DWORDX4_IMM),
      GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/0, // DstI[sdst]
      GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/0, // sbase
      GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/1, // offset
      GIR_AddImm8, /*InsnID*/0, /*Imm*/0,
      GIR_MergeMemOperands, /*InsnID*/0, /*NumInsns*/1, /*MergeInsnID's*/0,
      GIR_ConstrainSelectedInstOperands, /*InsnID*/0,
      GIR_EraseFromParent, /*InsnID*/0,
      // GIR_Coverage, 2576,
      GIR_Done,
    // Label 1340: @88834
    GIM_Try, /*On fail goto*//*Label 1341*/ GIMT_Encode4(88899), // Rule ID 2577 //
      GIM_CheckFeatures, GIMT_Encode2(GIFBS_isGFX7Only),
      GIM_CheckMemorySizeEqualToLLT, /*MI*/0, /*MMO*/0, /*OpIdx*/0,
      GIM_CheckAtomicOrdering, /*MI*/0, /*Order*/(uint8_t)AtomicOrdering::NotAtomic,
      GIM_CheckRegBankForClass, /*MI*/0, /*Op*/0, /*RC*/GIMT_Encode2(AMDGPU::SReg_128RegClassID),
      GIM_CheckPointerToAny, /*MI*/0, /*Op*/1, /*SizeInBits*/0,
      GIM_CheckCxxInsnPredicate, /*MI*/0, /*FnId*/GIMT_Encode2(GICXXPred_MI_Predicate_smrd_load),
      GIM_CheckComplexPattern, /*MI*/0, /*Op*/1, /*Renderer*/GIMT_Encode2(0), GIMT_Encode2(GICP_gi_smrd_imm32),
      // (ld:{ *:[v2f64] } (SMRDImm32:{ *:[iPTR] } i64:{ *:[i64] }:$sbase, i32:{ *:[i32] }:$offset))<<P:Predicate_unindexedload>><<P:Predicate_load>><<P:Predicate_smrd_load>>  =>  (S_LOAD_DWORDX4_IMM_ci:{ *:[v2f64] } ?:{ *:[i64] }:$sbase, ?:{ *:[i32] }:$offset, 0:{ *:[i32] })
      GIR_BuildMI, /*InsnID*/0, /*Opcode*/GIMT_Encode2(AMDGPU::S_LOAD_DWORDX4_IMM_ci),
      GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/0, // DstI[sdst]
      GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/0, // sbase
      GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/1, // offset
      GIR_AddImm8, /*InsnID*/0, /*Imm*/0,
      GIR_MergeMemOperands, /*InsnID*/0, /*NumInsns*/1, /*MergeInsnID's*/0,
      GIR_ConstrainSelectedInstOperands, /*InsnID*/0,
      GIR_EraseFromParent, /*InsnID*/0,
      // GIR_Coverage, 2577,
      GIR_Done,
    // Label 1341: @88899
    GIM_Try, /*On fail goto*//*Label 1342*/ GIMT_Encode4(88964), // Rule ID 2578 //
      GIM_CheckFeatures, GIMT_Encode2(GIFBS_isNotGFX9Plus),
      GIM_CheckMemorySizeEqualToLLT, /*MI*/0, /*MMO*/0, /*OpIdx*/0,
      GIM_CheckAtomicOrdering, /*MI*/0, /*Order*/(uint8_t)AtomicOrdering::NotAtomic,
      GIM_CheckRegBankForClass, /*MI*/0, /*Op*/0, /*RC*/GIMT_Encode2(AMDGPU::SReg_128RegClassID),
      GIM_CheckPointerToAny, /*MI*/0, /*Op*/1, /*SizeInBits*/0,
      GIM_CheckCxxInsnPredicate, /*MI*/0, /*FnId*/GIMT_Encode2(GICXXPred_MI_Predicate_smrd_load),
      GIM_CheckComplexPattern, /*MI*/0, /*Op*/1, /*Renderer*/GIMT_Encode2(0), GIMT_Encode2(GICP_gi_smrd_sgpr),
      // (ld:{ *:[v2f64] } (SMRDSgpr:{ *:[iPTR] } i64:{ *:[i64] }:$sbase, i32:{ *:[i32] }:$soffset))<<P:Predicate_unindexedload>><<P:Predicate_load>><<P:Predicate_smrd_load>>  =>  (S_LOAD_DWORDX4_SGPR:{ *:[v2f64] } ?:{ *:[i64] }:$sbase, ?:{ *:[i32] }:$soffset, 0:{ *:[i32] })
      GIR_BuildMI, /*InsnID*/0, /*Opcode*/GIMT_Encode2(AMDGPU::S_LOAD_DWORDX4_SGPR),
      GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/0, // DstI[sdst]
      GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/0, // sbase
      GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/1, // soffset
      GIR_AddImm8, /*InsnID*/0, /*Imm*/0,
      GIR_MergeMemOperands, /*InsnID*/0, /*NumInsns*/1, /*MergeInsnID's*/0,
      GIR_ConstrainSelectedInstOperands, /*InsnID*/0,
      GIR_EraseFromParent, /*InsnID*/0,
      // GIR_Coverage, 2578,
      GIR_Done,
    // Label 1342: @88964
    GIM_Try, /*On fail goto*//*Label 1343*/ GIMT_Encode4(89032), // Rule ID 2579 //
      GIM_CheckFeatures, GIMT_Encode2(GIFBS_isGFX9Plus),
      GIM_CheckMemorySizeEqualToLLT, /*MI*/0, /*MMO*/0, /*OpIdx*/0,
      GIM_CheckAtomicOrdering, /*MI*/0, /*Order*/(uint8_t)AtomicOrdering::NotAtomic,
      GIM_CheckRegBankForClass, /*MI*/0, /*Op*/0, /*RC*/GIMT_Encode2(AMDGPU::SReg_128RegClassID),
      GIM_CheckPointerToAny, /*MI*/0, /*Op*/1, /*SizeInBits*/0,
      GIM_CheckCxxInsnPredicate, /*MI*/0, /*FnId*/GIMT_Encode2(GICXXPred_MI_Predicate_smrd_load),
      GIM_CheckComplexPattern, /*MI*/0, /*Op*/1, /*Renderer*/GIMT_Encode2(0), GIMT_Encode2(GICP_gi_smrd_sgpr),
      // (ld:{ *:[v2f64] } (SMRDSgpr:{ *:[iPTR] } i64:{ *:[i64] }:$sbase, i32:{ *:[i32] }:$soffset))<<P:Predicate_unindexedload>><<P:Predicate_load>><<P:Predicate_smrd_load>>  =>  (S_LOAD_DWORDX4_SGPR_IMM:{ *:[v2f64] } ?:{ *:[i64] }:$sbase, ?:{ *:[i32] }:$soffset, 0:{ *:[i32] }, 0:{ *:[i32] })
      GIR_BuildMI, /*InsnID*/0, /*Opcode*/GIMT_Encode2(AMDGPU::S_LOAD_DWORDX4_SGPR_IMM),
      GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/0, // DstI[sdst]
      GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/0, // sbase
      GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/1, // soffset
      GIR_AddImm8, /*InsnID*/0, /*Imm*/0,
      GIR_AddImm8, /*InsnID*/0, /*Imm*/0,
      GIR_MergeMemOperands, /*InsnID*/0, /*NumInsns*/1, /*MergeInsnID's*/0,
      GIR_ConstrainSelectedInstOperands, /*InsnID*/0,
      GIR_EraseFromParent, /*InsnID*/0,
      // GIR_Coverage, 2579,
      GIR_Done,
    // Label 1343: @89032
    GIM_Try, /*On fail goto*//*Label 1344*/ GIMT_Encode4(89103), // Rule ID 6872 //
      GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasUnalignedAccessMode_NotLDSRequiresM0Init),
      GIM_CheckMemoryAddressSpace, /*MI*/0, /*MMO*/0, /*NumAddrSpace*/1, /*AddrSpace*/3,
      GIM_CheckMemoryAddressSpace, /*MI*/0, /*MMO*/0, /*NumAddrSpace*/1, /*AddrSpace*/3,
      GIM_CheckAtomicOrdering, /*MI*/0, /*Order*/(uint8_t)AtomicOrdering::NotAtomic,
      GIM_CheckRegBankForClass, /*MI*/0, /*Op*/0, /*RC*/GIMT_Encode2(AMDGPU::AV_128RegClassID),
      GIM_CheckPointerToAny, /*MI*/0, /*Op*/1, /*SizeInBits*/0,
      GIM_CheckCxxInsnPredicate, /*MI*/0, /*FnId*/GIMT_Encode2(GICXXPred_MI_Predicate_load_align_less_than_4_local),
      GIM_CheckComplexPattern, /*MI*/0, /*Op*/1, /*Renderer*/GIMT_Encode2(0), GIMT_Encode2(GICP_gi_ds_1addr_1offset),
      // (ld:{ *:[v2i64] } (DS1Addr1Offset:{ *:[iPTR] } i32:{ *:[i32] }:$ptr, i32:{ *:[i32] }:$offset))<<P:Predicate_unindexedload>><<P:Predicate_load_local>><<P:Predicate_load_align_less_than_4_local>>  =>  (DS_READ_B128_gfx9:{ *:[v2i64] } ?:{ *:[i32] }:$ptr, offset:{ *:[i32] }:$offset, 0:{ *:[i1] })
      GIR_BuildMI, /*InsnID*/0, /*Opcode*/GIMT_Encode2(AMDGPU::DS_READ_B128_gfx9),
      GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/0, // DstI[vdst]
      GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/0, // ptr
      GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/1, // offset
      GIR_AddImm8, /*InsnID*/0, /*Imm*/0,
      GIR_MergeMemOperands, /*InsnID*/0, /*NumInsns*/1, /*MergeInsnID's*/0,
      GIR_ConstrainSelectedInstOperands, /*InsnID*/0,
      GIR_EraseFromParent, /*InsnID*/0,
      // GIR_Coverage, 6872,
      GIR_Done,
    // Label 1344: @89103
    GIM_Try, /*On fail goto*//*Label 1345*/ GIMT_Encode4(89174), // Rule ID 6876 //
      GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasUnalignedAccessMode_NotLDSRequiresM0Init),
      GIM_CheckMemoryAddressSpace, /*MI*/0, /*MMO*/0, /*NumAddrSpace*/1, /*AddrSpace*/3,
      GIM_CheckMemoryAddressSpace, /*MI*/0, /*MMO*/0, /*NumAddrSpace*/1, /*AddrSpace*/3,
      GIM_CheckAtomicOrdering, /*MI*/0, /*Order*/(uint8_t)AtomicOrdering::NotAtomic,
      GIM_CheckRegBankForClass, /*MI*/0, /*Op*/0, /*RC*/GIMT_Encode2(AMDGPU::AV_128RegClassID),
      GIM_CheckPointerToAny, /*MI*/0, /*Op*/1, /*SizeInBits*/0,
      GIM_CheckCxxInsnPredicate, /*MI*/0, /*FnId*/GIMT_Encode2(GICXXPred_MI_Predicate_load_align_less_than_4_local),
      GIM_CheckComplexPattern, /*MI*/0, /*Op*/1, /*Renderer*/GIMT_Encode2(0), GIMT_Encode2(GICP_gi_ds_1addr_1offset),
      // (ld:{ *:[v2f64] } (DS1Addr1Offset:{ *:[iPTR] } i32:{ *:[i32] }:$ptr, i32:{ *:[i32] }:$offset))<<P:Predicate_unindexedload>><<P:Predicate_load_local>><<P:Predicate_load_align_less_than_4_local>>  =>  (DS_READ_B128_gfx9:{ *:[v2f64] } ?:{ *:[i32] }:$ptr, offset:{ *:[i32] }:$offset, 0:{ *:[i1] })
      GIR_BuildMI, /*InsnID*/0, /*Opcode*/GIMT_Encode2(AMDGPU::DS_READ_B128_gfx9),
      GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/0, // DstI[vdst]
      GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/0, // ptr
      GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/1, // offset
      GIR_AddImm8, /*InsnID*/0, /*Imm*/0,
      GIR_MergeMemOperands, /*InsnID*/0, /*NumInsns*/1, /*MergeInsnID's*/0,
      GIR_ConstrainSelectedInstOperands, /*InsnID*/0,
      GIR_EraseFromParent, /*InsnID*/0,
      // GIR_Coverage, 6876,
      GIR_Done,
    // Label 1345: @89174
    GIM_Try, /*On fail goto*//*Label 1346*/ GIMT_Encode4(89240), // Rule ID 6796 //
      GIM_CheckFeatures, GIMT_Encode2(GIFBS_NotLDSRequiresM0Init_isGFX7Plus),
      GIM_CheckMemoryAddressSpace, /*MI*/0, /*MMO*/0, /*NumAddrSpace*/1, /*AddrSpace*/3,
      GIM_CheckMemoryAlignment, /*MI*/0, /*MMO*/0, /*MinAlign*/16,
      GIM_CheckAtomicOrdering, /*MI*/0, /*Order*/(uint8_t)AtomicOrdering::NotAtomic,
      GIM_CheckRegBankForClass, /*MI*/0, /*Op*/0, /*RC*/GIMT_Encode2(AMDGPU::AV_128RegClassID),
      GIM_CheckPointerToAny, /*MI*/0, /*Op*/1, /*SizeInBits*/0,
      GIM_CheckComplexPattern, /*MI*/0, /*Op*/1, /*Renderer*/GIMT_Encode2(0), GIMT_Encode2(GICP_gi_ds_1addr_1offset),
      // (ld:{ *:[v2i64] } (DS1Addr1Offset:{ *:[iPTR] } i32:{ *:[i32] }:$ptr, i32:{ *:[i32] }:$offset))<<P:Predicate_unindexedload>><<P:Predicate_load_local>><<P:Predicate_load_align16_local>>  =>  (DS_READ_B128_gfx9:{ *:[v2i64] } ?:{ *:[i32] }:$ptr, offset:{ *:[i32] }:$offset, 0:{ *:[i1] })
      GIR_BuildMI, /*InsnID*/0, /*Opcode*/GIMT_Encode2(AMDGPU::DS_READ_B128_gfx9),
      GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/0, // DstI[vdst]
      GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/0, // ptr
      GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/1, // offset
      GIR_AddImm8, /*InsnID*/0, /*Imm*/0,
      GIR_MergeMemOperands, /*InsnID*/0, /*NumInsns*/1, /*MergeInsnID's*/0,
      GIR_ConstrainSelectedInstOperands, /*InsnID*/0,
      GIR_EraseFromParent, /*InsnID*/0,
      // GIR_Coverage, 6796,
      GIR_Done,
    // Label 1346: @89240
    GIM_Try, /*On fail goto*//*Label 1347*/ GIMT_Encode4(89306), // Rule ID 6800 //
      GIM_CheckFeatures, GIMT_Encode2(GIFBS_NotLDSRequiresM0Init_isGFX7Plus),
      GIM_CheckMemoryAddressSpace, /*MI*/0, /*MMO*/0, /*NumAddrSpace*/1, /*AddrSpace*/3,
      GIM_CheckMemoryAlignment, /*MI*/0, /*MMO*/0, /*MinAlign*/16,
      GIM_CheckAtomicOrdering, /*MI*/0, /*Order*/(uint8_t)AtomicOrdering::NotAtomic,
      GIM_CheckRegBankForClass, /*MI*/0, /*Op*/0, /*RC*/GIMT_Encode2(AMDGPU::AV_128RegClassID),
      GIM_CheckPointerToAny, /*MI*/0, /*Op*/1, /*SizeInBits*/0,
      GIM_CheckComplexPattern, /*MI*/0, /*Op*/1, /*Renderer*/GIMT_Encode2(0), GIMT_Encode2(GICP_gi_ds_1addr_1offset),
      // (ld:{ *:[v2f64] } (DS1Addr1Offset:{ *:[iPTR] } i32:{ *:[i32] }:$ptr, i32:{ *:[i32] }:$offset))<<P:Predicate_unindexedload>><<P:Predicate_load_local>><<P:Predicate_load_align16_local>>  =>  (DS_READ_B128_gfx9:{ *:[v2f64] } ?:{ *:[i32] }:$ptr, offset:{ *:[i32] }:$offset, 0:{ *:[i1] })
      GIR_BuildMI, /*InsnID*/0, /*Opcode*/GIMT_Encode2(AMDGPU::DS_READ_B128_gfx9),
      GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/0, // DstI[vdst]
      GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/0, // ptr
      GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/1, // offset
      GIR_AddImm8, /*InsnID*/0, /*Imm*/0,
      GIR_MergeMemOperands, /*InsnID*/0, /*NumInsns*/1, /*MergeInsnID's*/0,
      GIR_ConstrainSelectedInstOperands, /*InsnID*/0,
      GIR_EraseFromParent, /*InsnID*/0,
      // GIR_Coverage, 6800,
      GIR_Done,
    // Label 1347: @89306
    GIM_Try, /*On fail goto*//*Label 1348*/ GIMT_Encode4(89363), // Rule ID 2575 //
      GIM_CheckMemorySizeEqualToLLT, /*MI*/0, /*MMO*/0, /*OpIdx*/0,
      GIM_CheckAtomicOrdering, /*MI*/0, /*Order*/(uint8_t)AtomicOrdering::NotAtomic,
      GIM_CheckRegBankForClass, /*MI*/0, /*Op*/0, /*RC*/GIMT_Encode2(AMDGPU::SReg_128RegClassID),
      // MIs[0] sbase
      GIM_CheckPointerToAny, /*MI*/0, /*Op*/1, /*SizeInBits*/64,
      GIM_CheckRegBankForClass, /*MI*/0, /*Op*/1, /*RC*/GIMT_Encode2(AMDGPU::SReg_64RegClassID),
      GIM_CheckCxxInsnPredicate, /*MI*/0, /*FnId*/GIMT_Encode2(GICXXPred_MI_Predicate_smrd_load),
      // (ld:{ *:[v2i64] } SReg_64:{ *:[i64] }:$sbase)<<P:Predicate_unindexedload>><<P:Predicate_load>><<P:Predicate_smrd_load>>  =>  (S_LOAD_DWORDX4_IMM:{ *:[v2i64] } i64:{ *:[i64] }:$sbase, 0:{ *:[i32] }, 0:{ *:[i32] })
      GIR_BuildMI, /*InsnID*/0, /*Opcode*/GIMT_Encode2(AMDGPU::S_LOAD_DWORDX4_IMM),
      GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/0, // DstI[sdst]
      GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/1, // sbase
      GIR_AddImm8, /*InsnID*/0, /*Imm*/0,
      GIR_AddImm8, /*InsnID*/0, /*Imm*/0,
      GIR_MergeMemOperands, /*InsnID*/0, /*NumInsns*/1, /*MergeInsnID's*/0,
      GIR_ConstrainSelectedInstOperands, /*InsnID*/0,
      GIR_EraseFromParent, /*InsnID*/0,
      // GIR_Coverage, 2575,
      GIR_Done,
    // Label 1348: @89363
    GIM_Try, /*On fail goto*//*Label 1349*/ GIMT_Encode4(89420), // Rule ID 2581 //
      GIM_CheckMemorySizeEqualToLLT, /*MI*/0, /*MMO*/0, /*OpIdx*/0,
      GIM_CheckAtomicOrdering, /*MI*/0, /*Order*/(uint8_t)AtomicOrdering::NotAtomic,
      GIM_CheckRegBankForClass, /*MI*/0, /*Op*/0, /*RC*/GIMT_Encode2(AMDGPU::SReg_128RegClassID),
      // MIs[0] sbase
      GIM_CheckPointerToAny, /*MI*/0, /*Op*/1, /*SizeInBits*/64,
      GIM_CheckRegBankForClass, /*MI*/0, /*Op*/1, /*RC*/GIMT_Encode2(AMDGPU::SReg_64RegClassID),
      GIM_CheckCxxInsnPredicate, /*MI*/0, /*FnId*/GIMT_Encode2(GICXXPred_MI_Predicate_smrd_load),
      // (ld:{ *:[v2f64] } SReg_64:{ *:[i64] }:$sbase)<<P:Predicate_unindexedload>><<P:Predicate_load>><<P:Predicate_smrd_load>>  =>  (S_LOAD_DWORDX4_IMM:{ *:[v2f64] } i64:{ *:[i64] }:$sbase, 0:{ *:[i32] }, 0:{ *:[i32] })
      GIR_BuildMI, /*InsnID*/0, /*Opcode*/GIMT_Encode2(AMDGPU::S_LOAD_DWORDX4_IMM),
      GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/0, // DstI[sdst]
      GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/1, // sbase
      GIR_AddImm8, /*InsnID*/0, /*Imm*/0,
      GIR_AddImm8, /*InsnID*/0, /*Imm*/0,
      GIR_MergeMemOperands, /*InsnID*/0, /*NumInsns*/1, /*MergeInsnID's*/0,
      GIR_ConstrainSelectedInstOperands, /*InsnID*/0,
      GIR_EraseFromParent, /*InsnID*/0,
      // GIR_Coverage, 2581,
      GIR_Done,
    // Label 1349: @89420
    GIM_Try, /*On fail goto*//*Label 1350*/ GIMT_Encode4(89487), // Rule ID 3559 //
      GIM_CheckFeatures, GIMT_Encode2(GIFBS_EnableFlatScratch_HasFlatScratchInsts_HasFlatScratchSVSMode),
      GIM_CheckMemoryAddressSpace, /*MI*/0, /*MMO*/0, /*NumAddrSpace*/1, /*AddrSpace*/5,
      GIM_CheckAtomicOrdering, /*MI*/0, /*Order*/(uint8_t)AtomicOrdering::NotAtomic,
      GIM_CheckRegBankForClass, /*MI*/0, /*Op*/0, /*RC*/GIMT_Encode2(AMDGPU::AV_128RegClassID),
      GIM_CheckPointerToAny, /*MI*/0, /*Op*/1, /*SizeInBits*/0,
      GIM_CheckComplexPattern, /*MI*/0, /*Op*/1, /*Renderer*/GIMT_Encode2(0), GIMT_Encode2(GICP_gi_flat_scratch_svaddr),
      // (ld:{ *:[v2i64] } (ScratchSVAddr:{ *:[iPTR] } VGPR_32:{ *:[i32] }:$vaddr, SGPR_32:{ *:[i32] }:$saddr, i32:{ *:[i32] }:$offset))<<P:Predicate_unindexedload>><<P:Predicate_load_private>>  =>  (SCRATCH_LOAD_DWORDX4_SVS:{ *:[v2i64] } ?:{ *:[i32] }:$vaddr, ?:{ *:[i32] }:$saddr, ?:{ *:[i32] }:$offset, 0:{ *:[i32] })
      GIR_BuildMI, /*InsnID*/0, /*Opcode*/GIMT_Encode2(AMDGPU::SCRATCH_LOAD_DWORDX4_SVS),
      GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/0, // DstI[vdst]
      GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/0, // vaddr
      GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/1, // saddr
      GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/2, // offset
      GIR_AddImm8, /*InsnID*/0, /*Imm*/0,
      GIR_MergeMemOperands, /*InsnID*/0, /*NumInsns*/1, /*MergeInsnID's*/0,
      GIR_ConstrainSelectedInstOperands, /*InsnID*/0,
      GIR_EraseFromParent, /*InsnID*/0,
      // GIR_Coverage, 3559,
      GIR_Done,
    // Label 1350: @89487
    GIM_Try, /*On fail goto*//*Label 1351*/ GIMT_Encode4(89554), // Rule ID 3565 //
      GIM_CheckFeatures, GIMT_Encode2(GIFBS_EnableFlatScratch_HasFlatScratchInsts_HasFlatScratchSVSMode),
      GIM_CheckMemoryAddressSpace, /*MI*/0, /*MMO*/0, /*NumAddrSpace*/1, /*AddrSpace*/5,
      GIM_CheckAtomicOrdering, /*MI*/0, /*Order*/(uint8_t)AtomicOrdering::NotAtomic,
      GIM_CheckRegBankForClass, /*MI*/0, /*Op*/0, /*RC*/GIMT_Encode2(AMDGPU::AV_128RegClassID),
      GIM_CheckPointerToAny, /*MI*/0, /*Op*/1, /*SizeInBits*/0,
      GIM_CheckComplexPattern, /*MI*/0, /*Op*/1, /*Renderer*/GIMT_Encode2(0), GIMT_Encode2(GICP_gi_flat_scratch_svaddr),
      // (ld:{ *:[v2f64] } (ScratchSVAddr:{ *:[iPTR] } VGPR_32:{ *:[i32] }:$vaddr, SGPR_32:{ *:[i32] }:$saddr, i32:{ *:[i32] }:$offset))<<P:Predicate_unindexedload>><<P:Predicate_load_private>>  =>  (SCRATCH_LOAD_DWORDX4_SVS:{ *:[v2f64] } ?:{ *:[i32] }:$vaddr, ?:{ *:[i32] }:$saddr, ?:{ *:[i32] }:$offset, 0:{ *:[i32] })
      GIR_BuildMI, /*InsnID*/0, /*Opcode*/GIMT_Encode2(AMDGPU::SCRATCH_LOAD_DWORDX4_SVS),
      GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/0, // DstI[vdst]
      GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/0, // vaddr
      GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/1, // saddr
      GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/2, // offset
      GIR_AddImm8, /*InsnID*/0, /*Imm*/0,
      GIR_MergeMemOperands, /*InsnID*/0, /*NumInsns*/1, /*MergeInsnID's*/0,
      GIR_ConstrainSelectedInstOperands, /*InsnID*/0,
      GIR_EraseFromParent, /*InsnID*/0,
      // GIR_Coverage, 3565,
      GIR_Done,
    // Label 1351: @89554
    GIM_Try, /*On fail goto*//*Label 1352*/ GIMT_Encode4(89616), // Rule ID 3558 //
      GIM_CheckFeatures, GIMT_Encode2(GIFBS_EnableFlatScratch_HasFlatScratchInsts),
      GIM_CheckMemoryAddressSpace, /*MI*/0, /*MMO*/0, /*NumAddrSpace*/1, /*AddrSpace*/5,
      GIM_CheckAtomicOrdering, /*MI*/0, /*Order*/(uint8_t)AtomicOrdering::NotAtomic,
      GIM_CheckRegBankForClass, /*MI*/0, /*Op*/0, /*RC*/GIMT_Encode2(AMDGPU::AV_128RegClassID),
      GIM_CheckPointerToAny, /*MI*/0, /*Op*/1, /*SizeInBits*/0,
      GIM_CheckComplexPattern, /*MI*/0, /*Op*/1, /*Renderer*/GIMT_Encode2(0), GIMT_Encode2(GICP_gi_flat_scratch_saddr),
      // (ld:{ *:[v2i64] } (ScratchSAddr:{ *:[iPTR] } SGPR_32:{ *:[i32] }:$saddr, i32:{ *:[i32] }:$offset))<<P:Predicate_unindexedload>><<P:Predicate_load_private>>  =>  (SCRATCH_LOAD_DWORDX4_SADDR:{ *:[v2i64] } ?:{ *:[i32] }:$saddr, ?:{ *:[i32] }:$offset)
      GIR_BuildMI, /*InsnID*/0, /*Opcode*/GIMT_Encode2(AMDGPU::SCRATCH_LOAD_DWORDX4_SADDR),
      GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/0, // DstI[vdst]
      GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/0, // saddr
      GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/1, // offset
      GIR_AddImm8, /*InsnID*/0, /*Imm*/0,
      GIR_MergeMemOperands, /*InsnID*/0, /*NumInsns*/1, /*MergeInsnID's*/0,
      GIR_ConstrainSelectedInstOperands, /*InsnID*/0,
      GIR_EraseFromParent, /*InsnID*/0,
      // GIR_Coverage, 3558,
      GIR_Done,
    // Label 1352: @89616
    GIM_Try, /*On fail goto*//*Label 1353*/ GIMT_Encode4(89678), // Rule ID 3564 //
      GIM_CheckFeatures, GIMT_Encode2(GIFBS_EnableFlatScratch_HasFlatScratchInsts),
      GIM_CheckMemoryAddressSpace, /*MI*/0, /*MMO*/0, /*NumAddrSpace*/1, /*AddrSpace*/5,
      GIM_CheckAtomicOrdering, /*MI*/0, /*Order*/(uint8_t)AtomicOrdering::NotAtomic,
      GIM_CheckRegBankForClass, /*MI*/0, /*Op*/0, /*RC*/GIMT_Encode2(AMDGPU::AV_128RegClassID),
      GIM_CheckPointerToAny, /*MI*/0, /*Op*/1, /*SizeInBits*/0,
      GIM_CheckComplexPattern, /*MI*/0, /*Op*/1, /*Renderer*/GIMT_Encode2(0), GIMT_Encode2(GICP_gi_flat_scratch_saddr),
      // (ld:{ *:[v2f64] } (ScratchSAddr:{ *:[iPTR] } SGPR_32:{ *:[i32] }:$saddr, i32:{ *:[i32] }:$offset))<<P:Predicate_unindexedload>><<P:Predicate_load_private>>  =>  (SCRATCH_LOAD_DWORDX4_SADDR:{ *:[v2f64] } ?:{ *:[i32] }:$saddr, ?:{ *:[i32] }:$offset)
      GIR_BuildMI, /*InsnID*/0, /*Opcode*/GIMT_Encode2(AMDGPU::SCRATCH_LOAD_DWORDX4_SADDR),
      GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/0, // DstI[vdst]
      GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/0, // saddr
      GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/1, // offset
      GIR_AddImm8, /*InsnID*/0, /*Imm*/0,
      GIR_MergeMemOperands, /*InsnID*/0, /*NumInsns*/1, /*MergeInsnID's*/0,
      GIR_ConstrainSelectedInstOperands, /*InsnID*/0,
      GIR_EraseFromParent, /*InsnID*/0,
      // GIR_Coverage, 3564,
      GIR_Done,
    // Label 1353: @89678
    GIM_Try, /*On fail goto*//*Label 1354*/ GIMT_Encode4(89740), // Rule ID 3557 //
      GIM_CheckFeatures, GIMT_Encode2(GIFBS_EnableFlatScratch_HasFlatScratchInsts),
      GIM_CheckMemoryAddressSpace, /*MI*/0, /*MMO*/0, /*NumAddrSpace*/1, /*AddrSpace*/5,
      GIM_CheckAtomicOrdering, /*MI*/0, /*Order*/(uint8_t)AtomicOrdering::NotAtomic,
      GIM_CheckRegBankForClass, /*MI*/0, /*Op*/0, /*RC*/GIMT_Encode2(AMDGPU::AV_128RegClassID),
      GIM_CheckPointerToAny, /*MI*/0, /*Op*/1, /*SizeInBits*/0,
      GIM_CheckComplexPattern, /*MI*/0, /*Op*/1, /*Renderer*/GIMT_Encode2(0), GIMT_Encode2(GICP_gi_flat_scratch_offset),
      // (ld:{ *:[v2i64] } (ScratchOffset:{ *:[iPTR] } VGPR_32:{ *:[i32] }:$vaddr, i32:{ *:[i32] }:$offset))<<P:Predicate_unindexedload>><<P:Predicate_load_private>>  =>  (SCRATCH_LOAD_DWORDX4:{ *:[v2i64] } ?:{ *:[i32] }:$vaddr, ?:{ *:[i32] }:$offset)
      GIR_BuildMI, /*InsnID*/0, /*Opcode*/GIMT_Encode2(AMDGPU::SCRATCH_LOAD_DWORDX4),
      GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/0, // DstI[vdst]
      GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/0, // vaddr
      GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/1, // offset
      GIR_AddImm8, /*InsnID*/0, /*Imm*/0,
      GIR_MergeMemOperands, /*InsnID*/0, /*NumInsns*/1, /*MergeInsnID's*/0,
      GIR_ConstrainSelectedInstOperands, /*InsnID*/0,
      GIR_EraseFromParent, /*InsnID*/0,
      // GIR_Coverage, 3557,
      GIR_Done,
    // Label 1354: @89740
    GIM_Try, /*On fail goto*//*Label 1355*/ GIMT_Encode4(89802), // Rule ID 3563 //
      GIM_CheckFeatures, GIMT_Encode2(GIFBS_EnableFlatScratch_HasFlatScratchInsts),
      GIM_CheckMemoryAddressSpace, /*MI*/0, /*MMO*/0, /*NumAddrSpace*/1, /*AddrSpace*/5,
      GIM_CheckAtomicOrdering, /*MI*/0, /*Order*/(uint8_t)AtomicOrdering::NotAtomic,
      GIM_CheckRegBankForClass, /*MI*/0, /*Op*/0, /*RC*/GIMT_Encode2(AMDGPU::AV_128RegClassID),
      GIM_CheckPointerToAny, /*MI*/0, /*Op*/1, /*SizeInBits*/0,
      GIM_CheckComplexPattern, /*MI*/0, /*Op*/1, /*Renderer*/GIMT_Encode2(0), GIMT_Encode2(GICP_gi_flat_scratch_offset),
      // (ld:{ *:[v2f64] } (ScratchOffset:{ *:[iPTR] } VGPR_32:{ *:[i32] }:$vaddr, i32:{ *:[i32] }:$offset))<<P:Predicate_unindexedload>><<P:Predicate_load_private>>  =>  (SCRATCH_LOAD_DWORDX4:{ *:[v2f64] } ?:{ *:[i32] }:$vaddr, ?:{ *:[i32] }:$offset)
      GIR_BuildMI, /*InsnID*/0, /*Opcode*/GIMT_Encode2(AMDGPU::SCRATCH_LOAD_DWORDX4),
      GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/0, // DstI[vdst]
      GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/0, // vaddr
      GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/1, // offset
      GIR_AddImm8, /*InsnID*/0, /*Imm*/0,
      GIR_MergeMemOperands, /*InsnID*/0, /*NumInsns*/1, /*MergeInsnID's*/0,
      GIR_ConstrainSelectedInstOperands, /*InsnID*/0,
      GIR_EraseFromParent, /*InsnID*/0,
      // GIR_Coverage, 3563,
      GIR_Done,
    // Label 1355: @89802
    GIM_Try, /*On fail goto*//*Label 1356*/ GIMT_Encode4(89879), // Rule ID 3776 //
      GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasUnrestrictedSOffset),
      GIM_CheckMemoryAddressSpace, /*MI*/0, /*MMO*/0, /*NumAddrSpace*/3, /*AddrSpace*/1, /*AddrSpace*/4, /*AddrSpace*/6,
      GIM_CheckAtomicOrdering, /*MI*/0, /*Order*/(uint8_t)AtomicOrdering::NotAtomic,
      GIM_CheckRegBankForClass, /*MI*/0, /*Op*/0, /*RC*/GIMT_Encode2(AMDGPU::AV_128RegClassID),
      GIM_CheckPointerToAny, /*MI*/0, /*Op*/1, /*SizeInBits*/0,
      GIM_CheckComplexPattern, /*MI*/0, /*Op*/1, /*Renderer*/GIMT_Encode2(0), GIMT_Encode2(GICP_gi_mubuf_addr64),
      // (ld:{ *:[v2i64] } (MUBUFAddr64:{ *:[iPTR] } v4i32:{ *:[v4i32] }:$srsrc, i64:{ *:[i64] }:$vaddr, i32:{ *:[i32] }:$soffset, i32:{ *:[i32] }:$offset))<<P:Predicate_unindexedload>><<P:Predicate_load_global>>  =>  (BUFFER_LOAD_DWORDX4_ADDR64:{ *:[v2i64] } i64:{ *:[i64] }:$vaddr, v4i32:{ *:[v4i32] }:$srsrc, i32:{ *:[i32] }:$soffset, i32:{ *:[i32] }:$offset)
      GIR_BuildMI, /*InsnID*/0, /*Opcode*/GIMT_Encode2(AMDGPU::BUFFER_LOAD_DWORDX4_ADDR64),
      GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/0, // DstI[vdata]
      GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/1, // vaddr
      GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/0, // srsrc
      GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/2, // soffset
      GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/3, // offset
      GIR_AddImm8, /*InsnID*/0, /*Imm*/0,
      GIR_AddImm8, /*InsnID*/0, /*Imm*/0,
      GIR_MergeMemOperands, /*InsnID*/0, /*NumInsns*/1, /*MergeInsnID's*/0,
      GIR_ConstrainSelectedInstOperands, /*InsnID*/0,
      GIR_EraseFromParent, /*InsnID*/0,
      // GIR_Coverage, 3776,
      GIR_Done,
    // Label 1356: @89879
    GIM_Try, /*On fail goto*//*Label 1357*/ GIMT_Encode4(89953), // Rule ID 3778 //
      GIM_CheckMemoryAddressSpace, /*MI*/0, /*MMO*/0, /*NumAddrSpace*/3, /*AddrSpace*/1, /*AddrSpace*/4, /*AddrSpace*/6,
      GIM_CheckAtomicOrdering, /*MI*/0, /*Order*/(uint8_t)AtomicOrdering::NotAtomic,
      GIM_CheckRegBankForClass, /*MI*/0, /*Op*/0, /*RC*/GIMT_Encode2(AMDGPU::AV_128RegClassID),
      GIM_CheckPointerToAny, /*MI*/0, /*Op*/1, /*SizeInBits*/0,
      GIM_CheckComplexPattern, /*MI*/0, /*Op*/1, /*Renderer*/GIMT_Encode2(0), GIMT_Encode2(GICP_gi_mubuf_addr64),
      // (ld:{ *:[v2i64] } (MUBUFAddr64:{ *:[iPTR] } v4i32:{ *:[v4i32] }:$srsrc, i64:{ *:[i64] }:$vaddr, i32:{ *:[i32] }:$soffset, i32:{ *:[i32] }:$offset))<<P:Predicate_unindexedload>><<P:Predicate_load_global>>  =>  (BUFFER_LOAD_DWORDX4_VBUFFER_ADDR64:{ *:[v2i64] } i64:{ *:[i64] }:$vaddr, v4i32:{ *:[v4i32] }:$srsrc, i32:{ *:[i32] }:$soffset, i32:{ *:[i32] }:$offset)
      GIR_BuildMI, /*InsnID*/0, /*Opcode*/GIMT_Encode2(AMDGPU::BUFFER_LOAD_DWORDX4_VBUFFER_ADDR64),
      GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/0, // DstI[vdata]
      GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/1, // vaddr
      GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/0, // srsrc
      GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/2, // soffset
      GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/3, // offset
      GIR_AddImm8, /*InsnID*/0, /*Imm*/0,
      GIR_AddImm8, /*InsnID*/0, /*Imm*/0,
      GIR_MergeMemOperands, /*InsnID*/0, /*NumInsns*/1, /*MergeInsnID's*/0,
      GIR_ConstrainSelectedInstOperands, /*InsnID*/0,
      GIR_EraseFromParent, /*InsnID*/0,
      // GIR_Coverage, 3778,
      GIR_Done,
    // Label 1357: @89953
    GIM_Try, /*On fail goto*//*Label 1358*/ GIMT_Encode4(90030), // Rule ID 3780 //
      GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasUnrestrictedSOffset),
      GIM_CheckMemoryAddressSpace, /*MI*/0, /*MMO*/0, /*NumAddrSpace*/3, /*AddrSpace*/1, /*AddrSpace*/4, /*AddrSpace*/6,
      GIM_CheckAtomicOrdering, /*MI*/0, /*Order*/(uint8_t)AtomicOrdering::NotAtomic,
      GIM_CheckRegBankForClass, /*MI*/0, /*Op*/0, /*RC*/GIMT_Encode2(AMDGPU::AV_128RegClassID),
      GIM_CheckPointerToAny, /*MI*/0, /*Op*/1, /*SizeInBits*/0,
      GIM_CheckComplexPattern, /*MI*/0, /*Op*/1, /*Renderer*/GIMT_Encode2(0), GIMT_Encode2(GICP_gi_mubuf_addr64),
      // (ld:{ *:[v2f64] } (MUBUFAddr64:{ *:[iPTR] } v4i32:{ *:[v4i32] }:$srsrc, i64:{ *:[i64] }:$vaddr, i32:{ *:[i32] }:$soffset, i32:{ *:[i32] }:$offset))<<P:Predicate_unindexedload>><<P:Predicate_load_global>>  =>  (BUFFER_LOAD_DWORDX4_ADDR64:{ *:[v2f64] } i64:{ *:[i64] }:$vaddr, v4i32:{ *:[v4i32] }:$srsrc, i32:{ *:[i32] }:$soffset, i32:{ *:[i32] }:$offset)
      GIR_BuildMI, /*InsnID*/0, /*Opcode*/GIMT_Encode2(AMDGPU::BUFFER_LOAD_DWORDX4_ADDR64),
      GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/0, // DstI[vdata]
      GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/1, // vaddr
      GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/0, // srsrc
      GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/2, // soffset
      GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/3, // offset
      GIR_AddImm8, /*InsnID*/0, /*Imm*/0,
      GIR_AddImm8, /*InsnID*/0, /*Imm*/0,
      GIR_MergeMemOperands, /*InsnID*/0, /*NumInsns*/1, /*MergeInsnID's*/0,
      GIR_ConstrainSelectedInstOperands, /*InsnID*/0,
      GIR_EraseFromParent, /*InsnID*/0,
      // GIR_Coverage, 3780,
      GIR_Done,
    // Label 1358: @90030
    GIM_Try, /*On fail goto*//*Label 1359*/ GIMT_Encode4(90104), // Rule ID 3782 //
      GIM_CheckMemoryAddressSpace, /*MI*/0, /*MMO*/0, /*NumAddrSpace*/3, /*AddrSpace*/1, /*AddrSpace*/4, /*AddrSpace*/6,
      GIM_CheckAtomicOrdering, /*MI*/0, /*Order*/(uint8_t)AtomicOrdering::NotAtomic,
      GIM_CheckRegBankForClass, /*MI*/0, /*Op*/0, /*RC*/GIMT_Encode2(AMDGPU::AV_128RegClassID),
      GIM_CheckPointerToAny, /*MI*/0, /*Op*/1, /*SizeInBits*/0,
      GIM_CheckComplexPattern, /*MI*/0, /*Op*/1, /*Renderer*/GIMT_Encode2(0), GIMT_Encode2(GICP_gi_mubuf_addr64),
      // (ld:{ *:[v2f64] } (MUBUFAddr64:{ *:[iPTR] } v4i32:{ *:[v4i32] }:$srsrc, i64:{ *:[i64] }:$vaddr, i32:{ *:[i32] }:$soffset, i32:{ *:[i32] }:$offset))<<P:Predicate_unindexedload>><<P:Predicate_load_global>>  =>  (BUFFER_LOAD_DWORDX4_VBUFFER_ADDR64:{ *:[v2f64] } i64:{ *:[i64] }:$vaddr, v4i32:{ *:[v4i32] }:$srsrc, i32:{ *:[i32] }:$soffset, i32:{ *:[i32] }:$offset)
      GIR_BuildMI, /*InsnID*/0, /*Opcode*/GIMT_Encode2(AMDGPU::BUFFER_LOAD_DWORDX4_VBUFFER_ADDR64),
      GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/0, // DstI[vdata]
      GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/1, // vaddr
      GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/0, // srsrc
      GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/2, // soffset
      GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/3, // offset
      GIR_AddImm8, /*InsnID*/0, /*Imm*/0,
      GIR_AddImm8, /*InsnID*/0, /*Imm*/0,
      GIR_MergeMemOperands, /*InsnID*/0, /*NumInsns*/1, /*MergeInsnID's*/0,
      GIR_ConstrainSelectedInstOperands, /*InsnID*/0,
      GIR_EraseFromParent, /*InsnID*/0,
      // GIR_Coverage, 3782,
      GIR_Done,
    // Label 1359: @90104
    GIM_Try, /*On fail goto*//*Label 1360*/ GIMT_Encode4(90175), // Rule ID 6719 //
      GIM_CheckFeatures, GIMT_Encode2(GIFBS_LDSRequiresM0Init_isGFX7Plus),
      GIM_CheckMemorySizeEqualToLLT, /*MI*/0, /*MMO*/0, /*OpIdx*/0,
      GIM_CheckMemoryAddressSpace, /*MI*/0, /*MMO*/0, /*NumAddrSpace*/1, /*AddrSpace*/3,
      GIM_CheckAtomicOrdering, /*MI*/0, /*Order*/(uint8_t)AtomicOrdering::NotAtomic,
      GIM_CheckRegBankForClass, /*MI*/0, /*Op*/0, /*RC*/GIMT_Encode2(AMDGPU::AV_128RegClassID),
      GIM_CheckPointerToAny, /*MI*/0, /*Op*/1, /*SizeInBits*/0,
      GIM_CheckComplexPattern, /*MI*/0, /*Op*/1, /*Renderer*/GIMT_Encode2(0), GIMT_Encode2(GICP_gi_ds_128bit_8byte_aligned),
      // (AMDGPUld_glue:{ *:[v2i64] } (DS128Bit8ByteAligned:{ *:[iPTR] } i32:{ *:[i32] }:$ptr, i8:{ *:[i8] }:$offset0, i8:{ *:[i8] }:$offset1))<<P:Predicate_unindexedload_glue>><<P:Predicate_load_glue>><<P:Predicate_load_local_m0>>  =>  (DS_READ2_B64:{ *:[v2i64] } ?:{ *:[i32] }:$ptr, ?:{ *:[i8] }:$offset0, ?:{ *:[i8] }:$offset1, 0:{ *:[i1] })
      GIR_BuildMI, /*InsnID*/0, /*Opcode*/GIMT_Encode2(AMDGPU::DS_READ2_B64),
      GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/0, // DstI[vdst]
      GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/0, // ptr
      GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/1, // offset0
      GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/2, // offset1
      GIR_AddImm8, /*InsnID*/0, /*Imm*/0,
      GIR_MergeMemOperands, /*InsnID*/0, /*NumInsns*/1, /*MergeInsnID's*/0,
      GIR_ConstrainSelectedInstOperands, /*InsnID*/0,
      GIR_EraseFromParent, /*InsnID*/0,
      // GIR_Coverage, 6719,
      GIR_Done,
    // Label 1360: @90175
    GIM_Try, /*On fail goto*//*Label 1361*/ GIMT_Encode4(90246), // Rule ID 6723 //
      GIM_CheckFeatures, GIMT_Encode2(GIFBS_LDSRequiresM0Init_isGFX7Plus),
      GIM_CheckMemorySizeEqualToLLT, /*MI*/0, /*MMO*/0, /*OpIdx*/0,
      GIM_CheckMemoryAddressSpace, /*MI*/0, /*MMO*/0, /*NumAddrSpace*/1, /*AddrSpace*/3,
      GIM_CheckAtomicOrdering, /*MI*/0, /*Order*/(uint8_t)AtomicOrdering::NotAtomic,
      GIM_CheckRegBankForClass, /*MI*/0, /*Op*/0, /*RC*/GIMT_Encode2(AMDGPU::AV_128RegClassID),
      GIM_CheckPointerToAny, /*MI*/0, /*Op*/1, /*SizeInBits*/0,
      GIM_CheckComplexPattern, /*MI*/0, /*Op*/1, /*Renderer*/GIMT_Encode2(0), GIMT_Encode2(GICP_gi_ds_128bit_8byte_aligned),
      // (AMDGPUld_glue:{ *:[v2f64] } (DS128Bit8ByteAligned:{ *:[iPTR] } i32:{ *:[i32] }:$ptr, i8:{ *:[i8] }:$offset0, i8:{ *:[i8] }:$offset1))<<P:Predicate_unindexedload_glue>><<P:Predicate_load_glue>><<P:Predicate_load_local_m0>>  =>  (DS_READ2_B64:{ *:[v2f64] } ?:{ *:[i32] }:$ptr, ?:{ *:[i8] }:$offset0, ?:{ *:[i8] }:$offset1, 0:{ *:[i1] })
      GIR_BuildMI, /*InsnID*/0, /*Opcode*/GIMT_Encode2(AMDGPU::DS_READ2_B64),
      GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/0, // DstI[vdst]
      GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/0, // ptr
      GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/1, // offset0
      GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/2, // offset1
      GIR_AddImm8, /*InsnID*/0, /*Imm*/0,
      GIR_MergeMemOperands, /*InsnID*/0, /*NumInsns*/1, /*MergeInsnID's*/0,
      GIR_ConstrainSelectedInstOperands, /*InsnID*/0,
      GIR_EraseFromParent, /*InsnID*/0,
      // GIR_Coverage, 6723,
      GIR_Done,
    // Label 1361: @90246
    GIM_Try, /*On fail goto*//*Label 1362*/ GIMT_Encode4(90318), // Rule ID 3775 //
      GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasUnrestrictedSOffset),
      GIM_CheckMemoryAddressSpace, /*MI*/0, /*MMO*/0, /*NumAddrSpace*/3, /*AddrSpace*/1, /*AddrSpace*/4, /*AddrSpace*/6,
      GIM_CheckAtomicOrdering, /*MI*/0, /*Order*/(uint8_t)AtomicOrdering::NotAtomic,
      GIM_CheckRegBankForClass, /*MI*/0, /*Op*/0, /*RC*/GIMT_Encode2(AMDGPU::AV_128RegClassID),
      GIM_CheckPointerToAny, /*MI*/0, /*Op*/1, /*SizeInBits*/0,
      GIM_CheckComplexPattern, /*MI*/0, /*Op*/1, /*Renderer*/GIMT_Encode2(0), GIMT_Encode2(GICP_gi_mubuf_offset),
      // (ld:{ *:[v2i64] } (MUBUFOffset:{ *:[iPTR] } v4i32:{ *:[v4i32] }:$srsrc, i32:{ *:[i32] }:$soffset, i32:{ *:[i32] }:$offset))<<P:Predicate_unindexedload>><<P:Predicate_load_global>>  =>  (BUFFER_LOAD_DWORDX4_OFFSET:{ *:[v2i64] } v4i32:{ *:[v4i32] }:$srsrc, i32:{ *:[i32] }:$soffset, i32:{ *:[i32] }:$offset)
      GIR_BuildMI, /*InsnID*/0, /*Opcode*/GIMT_Encode2(AMDGPU::BUFFER_LOAD_DWORDX4_OFFSET),
      GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/0, // DstI[vdata]
      GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/0, // srsrc
      GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/1, // soffset
      GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/2, // offset
      GIR_AddImm8, /*InsnID*/0, /*Imm*/0,
      GIR_AddImm8, /*InsnID*/0, /*Imm*/0,
      GIR_MergeMemOperands, /*InsnID*/0, /*NumInsns*/1, /*MergeInsnID's*/0,
      GIR_ConstrainSelectedInstOperands, /*InsnID*/0,
      GIR_EraseFromParent, /*InsnID*/0,
      // GIR_Coverage, 3775,
      GIR_Done,
    // Label 1362: @90318
    GIM_Try, /*On fail goto*//*Label 1363*/ GIMT_Encode4(90387), // Rule ID 3777 //
      GIM_CheckMemoryAddressSpace, /*MI*/0, /*MMO*/0, /*NumAddrSpace*/3, /*AddrSpace*/1, /*AddrSpace*/4, /*AddrSpace*/6,
      GIM_CheckAtomicOrdering, /*MI*/0, /*Order*/(uint8_t)AtomicOrdering::NotAtomic,
      GIM_CheckRegBankForClass, /*MI*/0, /*Op*/0, /*RC*/GIMT_Encode2(AMDGPU::AV_128RegClassID),
      GIM_CheckPointerToAny, /*MI*/0, /*Op*/1, /*SizeInBits*/0,
      GIM_CheckComplexPattern, /*MI*/0, /*Op*/1, /*Renderer*/GIMT_Encode2(0), GIMT_Encode2(GICP_gi_mubuf_offset),
      // (ld:{ *:[v2i64] } (MUBUFOffset:{ *:[iPTR] } v4i32:{ *:[v4i32] }:$srsrc, i32:{ *:[i32] }:$soffset, i32:{ *:[i32] }:$offset))<<P:Predicate_unindexedload>><<P:Predicate_load_global>>  =>  (BUFFER_LOAD_DWORDX4_VBUFFER_OFFSET:{ *:[v2i64] } v4i32:{ *:[v4i32] }:$srsrc, i32:{ *:[i32] }:$soffset, i32:{ *:[i32] }:$offset)
      GIR_BuildMI, /*InsnID*/0, /*Opcode*/GIMT_Encode2(AMDGPU::BUFFER_LOAD_DWORDX4_VBUFFER_OFFSET),
      GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/0, // DstI[vdata]
      GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/0, // srsrc
      GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/1, // soffset
      GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/2, // offset
      GIR_AddImm8, /*InsnID*/0, /*Imm*/0,
      GIR_AddImm8, /*InsnID*/0, /*Imm*/0,
      GIR_MergeMemOperands, /*InsnID*/0, /*NumInsns*/1, /*MergeInsnID's*/0,
      GIR_ConstrainSelectedInstOperands, /*InsnID*/0,
      GIR_EraseFromParent, /*InsnID*/0,
      // GIR_Coverage, 3777,
      GIR_Done,
    // Label 1363: @90387
    GIM_Try, /*On fail goto*//*Label 1364*/ GIMT_Encode4(90459), // Rule ID 3779 //
      GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasUnrestrictedSOffset),
      GIM_CheckMemoryAddressSpace, /*MI*/0, /*MMO*/0, /*NumAddrSpace*/3, /*AddrSpace*/1, /*AddrSpace*/4, /*AddrSpace*/6,
      GIM_CheckAtomicOrdering, /*MI*/0, /*Order*/(uint8_t)AtomicOrdering::NotAtomic,
      GIM_CheckRegBankForClass, /*MI*/0, /*Op*/0, /*RC*/GIMT_Encode2(AMDGPU::AV_128RegClassID),
      GIM_CheckPointerToAny, /*MI*/0, /*Op*/1, /*SizeInBits*/0,
      GIM_CheckComplexPattern, /*MI*/0, /*Op*/1, /*Renderer*/GIMT_Encode2(0), GIMT_Encode2(GICP_gi_mubuf_offset),
      // (ld:{ *:[v2f64] } (MUBUFOffset:{ *:[iPTR] } v4i32:{ *:[v4i32] }:$srsrc, i32:{ *:[i32] }:$soffset, i32:{ *:[i32] }:$offset))<<P:Predicate_unindexedload>><<P:Predicate_load_global>>  =>  (BUFFER_LOAD_DWORDX4_OFFSET:{ *:[v2f64] } v4i32:{ *:[v4i32] }:$srsrc, i32:{ *:[i32] }:$soffset, i32:{ *:[i32] }:$offset)
      GIR_BuildMI, /*InsnID*/0, /*Opcode*/GIMT_Encode2(AMDGPU::BUFFER_LOAD_DWORDX4_OFFSET),
      GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/0, // DstI[vdata]
      GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/0, // srsrc
      GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/1, // soffset
      GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/2, // offset
      GIR_AddImm8, /*InsnID*/0, /*Imm*/0,
      GIR_AddImm8, /*InsnID*/0, /*Imm*/0,
      GIR_MergeMemOperands, /*InsnID*/0, /*NumInsns*/1, /*MergeInsnID's*/0,
      GIR_ConstrainSelectedInstOperands, /*InsnID*/0,
      GIR_EraseFromParent, /*InsnID*/0,
      // GIR_Coverage, 3779,
      GIR_Done,
    // Label 1364: @90459
    GIM_Try, /*On fail goto*//*Label 1365*/ GIMT_Encode4(90528), // Rule ID 3781 //
      GIM_CheckMemoryAddressSpace, /*MI*/0, /*MMO*/0, /*NumAddrSpace*/3, /*AddrSpace*/1, /*AddrSpace*/4, /*AddrSpace*/6,
      GIM_CheckAtomicOrdering, /*MI*/0, /*Order*/(uint8_t)AtomicOrdering::NotAtomic,
      GIM_CheckRegBankForClass, /*MI*/0, /*Op*/0, /*RC*/GIMT_Encode2(AMDGPU::AV_128RegClassID),
      GIM_CheckPointerToAny, /*MI*/0, /*Op*/1, /*SizeInBits*/0,
      GIM_CheckComplexPattern, /*MI*/0, /*Op*/1, /*Renderer*/GIMT_Encode2(0), GIMT_Encode2(GICP_gi_mubuf_offset),
      // (ld:{ *:[v2f64] } (MUBUFOffset:{ *:[iPTR] } v4i32:{ *:[v4i32] }:$srsrc, i32:{ *:[i32] }:$soffset, i32:{ *:[i32] }:$offset))<<P:Predicate_unindexedload>><<P:Predicate_load_global>>  =>  (BUFFER_LOAD_DWORDX4_VBUFFER_OFFSET:{ *:[v2f64] } v4i32:{ *:[v4i32] }:$srsrc, i32:{ *:[i32] }:$soffset, i32:{ *:[i32] }:$offset)
      GIR_BuildMI, /*InsnID*/0, /*Opcode*/GIMT_Encode2(AMDGPU::BUFFER_LOAD_DWORDX4_VBUFFER_OFFSET),
      GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/0, // DstI[vdata]
      GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/0, // srsrc
      GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/1, // soffset
      GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/2, // offset
      GIR_AddImm8, /*InsnID*/0, /*Imm*/0,
      GIR_AddImm8, /*InsnID*/0, /*Imm*/0,
      GIR_MergeMemOperands, /*InsnID*/0, /*NumInsns*/1, /*MergeInsnID's*/0,
      GIR_ConstrainSelectedInstOperands, /*InsnID*/0,
      GIR_EraseFromParent, /*InsnID*/0,
      // GIR_Coverage, 3781,
      GIR_Done,
    // Label 1365: @90528
    GIM_Try, /*On fail goto*//*Label 1366*/ GIMT_Encode4(90595), // Rule ID 6721 //
      GIM_CheckFeatures, GIMT_Encode2(GIFBS_NotLDSRequiresM0Init),
      GIM_CheckMemoryAddressSpace, /*MI*/0, /*MMO*/0, /*NumAddrSpace*/1, /*AddrSpace*/3,
      GIM_CheckAtomicOrdering, /*MI*/0, /*Order*/(uint8_t)AtomicOrdering::NotAtomic,
      GIM_CheckRegBankForClass, /*MI*/0, /*Op*/0, /*RC*/GIMT_Encode2(AMDGPU::AV_128RegClassID),
      GIM_CheckPointerToAny, /*MI*/0, /*Op*/1, /*SizeInBits*/0,
      GIM_CheckComplexPattern, /*MI*/0, /*Op*/1, /*Renderer*/GIMT_Encode2(0), GIMT_Encode2(GICP_gi_ds_128bit_8byte_aligned),
      // (ld:{ *:[v2i64] } (DS128Bit8ByteAligned:{ *:[iPTR] } i32:{ *:[i32] }:$ptr, i8:{ *:[i8] }:$offset0, i8:{ *:[i8] }:$offset1))<<P:Predicate_unindexedload>><<P:Predicate_load_local>>  =>  (DS_READ2_B64_gfx9:{ *:[v2i64] } ?:{ *:[i32] }:$ptr, ?:{ *:[i8] }:$offset0, ?:{ *:[i8] }:$offset1, 0:{ *:[i1] })
      GIR_BuildMI, /*InsnID*/0, /*Opcode*/GIMT_Encode2(AMDGPU::DS_READ2_B64_gfx9),
      GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/0, // DstI[vdst]
      GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/0, // ptr
      GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/1, // offset0
      GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/2, // offset1
      GIR_AddImm8, /*InsnID*/0, /*Imm*/0,
      GIR_MergeMemOperands, /*InsnID*/0, /*NumInsns*/1, /*MergeInsnID's*/0,
      GIR_ConstrainSelectedInstOperands, /*InsnID*/0,
      GIR_EraseFromParent, /*InsnID*/0,
      // GIR_Coverage, 6721,
      GIR_Done,
    // Label 1366: @90595
    GIM_Try, /*On fail goto*//*Label 1367*/ GIMT_Encode4(90662), // Rule ID 6725 //
      GIM_CheckFeatures, GIMT_Encode2(GIFBS_NotLDSRequiresM0Init),
      GIM_CheckMemoryAddressSpace, /*MI*/0, /*MMO*/0, /*NumAddrSpace*/1, /*AddrSpace*/3,
      GIM_CheckAtomicOrdering, /*MI*/0, /*Order*/(uint8_t)AtomicOrdering::NotAtomic,
      GIM_CheckRegBankForClass, /*MI*/0, /*Op*/0, /*RC*/GIMT_Encode2(AMDGPU::AV_128RegClassID),
      GIM_CheckPointerToAny, /*MI*/0, /*Op*/1, /*SizeInBits*/0,
      GIM_CheckComplexPattern, /*MI*/0, /*Op*/1, /*Renderer*/GIMT_Encode2(0), GIMT_Encode2(GICP_gi_ds_128bit_8byte_aligned),
      // (ld:{ *:[v2f64] } (DS128Bit8ByteAligned:{ *:[iPTR] } i32:{ *:[i32] }:$ptr, i8:{ *:[i8] }:$offset0, i8:{ *:[i8] }:$offset1))<<P:Predicate_unindexedload>><<P:Predicate_load_local>>  =>  (DS_READ2_B64_gfx9:{ *:[v2f64] } ?:{ *:[i32] }:$ptr, ?:{ *:[i8] }:$offset0, ?:{ *:[i8] }:$offset1, 0:{ *:[i1] })
      GIR_BuildMI, /*InsnID*/0, /*Opcode*/GIMT_Encode2(AMDGPU::DS_READ2_B64_gfx9),
      GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/0, // DstI[vdst]
      GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/0, // ptr
      GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/1, // offset0
      GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/2, // offset1
      GIR_AddImm8, /*InsnID*/0, /*Imm*/0,
      GIR_MergeMemOperands, /*InsnID*/0, /*NumInsns*/1, /*MergeInsnID's*/0,
      GIR_ConstrainSelectedInstOperands, /*InsnID*/0,
      GIR_EraseFromParent, /*InsnID*/0,
      // GIR_Coverage, 6725,
      GIR_Done,
    // Label 1367: @90662
    GIM_Try, /*On fail goto*//*Label 1368*/ GIMT_Encode4(90731), // Rule ID 3079 //
      GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasFlatGlobalInsts),
      GIM_CheckMemoryAddressSpace, /*MI*/0, /*MMO*/0, /*NumAddrSpace*/3, /*AddrSpace*/1, /*AddrSpace*/4, /*AddrSpace*/6,
      GIM_CheckAtomicOrdering, /*MI*/0, /*Order*/(uint8_t)AtomicOrdering::NotAtomic,
      GIM_CheckRegBankForClass, /*MI*/0, /*Op*/0, /*RC*/GIMT_Encode2(AMDGPU::AV_128RegClassID),
      GIM_CheckPointerToAny, /*MI*/0, /*Op*/1, /*SizeInBits*/0,
      GIM_CheckComplexPattern, /*MI*/0, /*Op*/1, /*Renderer*/GIMT_Encode2(0), GIMT_Encode2(GICP_gi_global_saddr),
      // (ld:{ *:[v2i64] } (GlobalSAddr:{ *:[iPTR] } SReg_64:{ *:[i64] }:$saddr, VGPR_32:{ *:[i32] }:$voffset, i32:{ *:[i32] }:$offset))<<P:Predicate_unindexedload>><<P:Predicate_load_global>>  =>  (GLOBAL_LOAD_DWORDX4_SADDR:{ *:[v2i64] } ?:{ *:[i64] }:$saddr, ?:{ *:[i32] }:$voffset, ?:{ *:[i32] }:$offset, 0:{ *:[i32] })
      GIR_BuildMI, /*InsnID*/0, /*Opcode*/GIMT_Encode2(AMDGPU::GLOBAL_LOAD_DWORDX4_SADDR),
      GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/0, // DstI[vdst]
      GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/0, // saddr
      GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/1, // voffset
      GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/2, // offset
      GIR_AddImm8, /*InsnID*/0, /*Imm*/0,
      GIR_MergeMemOperands, /*InsnID*/0, /*NumInsns*/1, /*MergeInsnID's*/0,
      GIR_ConstrainSelectedInstOperands, /*InsnID*/0,
      GIR_EraseFromParent, /*InsnID*/0,
      // GIR_Coverage, 3079,
      GIR_Done,
    // Label 1368: @90731
    GIM_Try, /*On fail goto*//*Label 1369*/ GIMT_Encode4(90800), // Rule ID 3083 //
      GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasFlatGlobalInsts),
      GIM_CheckMemoryAddressSpace, /*MI*/0, /*MMO*/0, /*NumAddrSpace*/3, /*AddrSpace*/1, /*AddrSpace*/4, /*AddrSpace*/6,
      GIM_CheckAtomicOrdering, /*MI*/0, /*Order*/(uint8_t)AtomicOrdering::NotAtomic,
      GIM_CheckRegBankForClass, /*MI*/0, /*Op*/0, /*RC*/GIMT_Encode2(AMDGPU::AV_128RegClassID),
      GIM_CheckPointerToAny, /*MI*/0, /*Op*/1, /*SizeInBits*/0,
      GIM_CheckComplexPattern, /*MI*/0, /*Op*/1, /*Renderer*/GIMT_Encode2(0), GIMT_Encode2(GICP_gi_global_saddr),
      // (ld:{ *:[v2f64] } (GlobalSAddr:{ *:[iPTR] } SReg_64:{ *:[i64] }:$saddr, VGPR_32:{ *:[i32] }:$voffset, i32:{ *:[i32] }:$offset))<<P:Predicate_unindexedload>><<P:Predicate_load_global>>  =>  (GLOBAL_LOAD_DWORDX4_SADDR:{ *:[v2f64] } ?:{ *:[i64] }:$saddr, ?:{ *:[i32] }:$voffset, ?:{ *:[i32] }:$offset, 0:{ *:[i32] })
      GIR_BuildMI, /*InsnID*/0, /*Opcode*/GIMT_Encode2(AMDGPU::GLOBAL_LOAD_DWORDX4_SADDR),
      GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/0, // DstI[vdst]
      GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/0, // saddr
      GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/1, // voffset
      GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/2, // offset
      GIR_AddImm8, /*InsnID*/0, /*Imm*/0,
      GIR_MergeMemOperands, /*InsnID*/0, /*NumInsns*/1, /*MergeInsnID's*/0,
      GIR_ConstrainSelectedInstOperands, /*InsnID*/0,
      GIR_EraseFromParent, /*InsnID*/0,
      // GIR_Coverage, 3083,
      GIR_Done,
    // Label 1369: @90800
    GIM_Try, /*On fail goto*//*Label 1370*/ GIMT_Encode4(90864), // Rule ID 3078 //
      GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasFlatGlobalInsts),
      GIM_CheckMemoryAddressSpace, /*MI*/0, /*MMO*/0, /*NumAddrSpace*/3, /*AddrSpace*/1, /*AddrSpace*/4, /*AddrSpace*/6,
      GIM_CheckAtomicOrdering, /*MI*/0, /*Order*/(uint8_t)AtomicOrdering::NotAtomic,
      GIM_CheckRegBankForClass, /*MI*/0, /*Op*/0, /*RC*/GIMT_Encode2(AMDGPU::AV_128RegClassID),
      GIM_CheckPointerToAny, /*MI*/0, /*Op*/1, /*SizeInBits*/0,
      GIM_CheckComplexPattern, /*MI*/0, /*Op*/1, /*Renderer*/GIMT_Encode2(0), GIMT_Encode2(GICP_gi_global_offset),
      // (ld:{ *:[v2i64] } (GlobalOffset:{ *:[iPTR] } VReg_64:{ *:[i64] }:$vaddr, i32:{ *:[i32] }:$offset))<<P:Predicate_unindexedload>><<P:Predicate_load_global>>  =>  (GLOBAL_LOAD_DWORDX4:{ *:[v2i64] } ?:{ *:[i64] }:$vaddr, ?:{ *:[i32] }:$offset)
      GIR_BuildMI, /*InsnID*/0, /*Opcode*/GIMT_Encode2(AMDGPU::GLOBAL_LOAD_DWORDX4),
      GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/0, // DstI[vdst]
      GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/0, // vaddr
      GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/1, // offset
      GIR_AddImm8, /*InsnID*/0, /*Imm*/0,
      GIR_MergeMemOperands, /*InsnID*/0, /*NumInsns*/1, /*MergeInsnID's*/0,
      GIR_ConstrainSelectedInstOperands, /*InsnID*/0,
      GIR_EraseFromParent, /*InsnID*/0,
      // GIR_Coverage, 3078,
      GIR_Done,
    // Label 1370: @90864
    GIM_Try, /*On fail goto*//*Label 1371*/ GIMT_Encode4(90928), // Rule ID 3082 //
      GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasFlatGlobalInsts),
      GIM_CheckMemoryAddressSpace, /*MI*/0, /*MMO*/0, /*NumAddrSpace*/3, /*AddrSpace*/1, /*AddrSpace*/4, /*AddrSpace*/6,
      GIM_CheckAtomicOrdering, /*MI*/0, /*Order*/(uint8_t)AtomicOrdering::NotAtomic,
      GIM_CheckRegBankForClass, /*MI*/0, /*Op*/0, /*RC*/GIMT_Encode2(AMDGPU::AV_128RegClassID),
      GIM_CheckPointerToAny, /*MI*/0, /*Op*/1, /*SizeInBits*/0,
      GIM_CheckComplexPattern, /*MI*/0, /*Op*/1, /*Renderer*/GIMT_Encode2(0), GIMT_Encode2(GICP_gi_global_offset),
      // (ld:{ *:[v2f64] } (GlobalOffset:{ *:[iPTR] } VReg_64:{ *:[i64] }:$vaddr, i32:{ *:[i32] }:$offset))<<P:Predicate_unindexedload>><<P:Predicate_load_global>>  =>  (GLOBAL_LOAD_DWORDX4:{ *:[v2f64] } ?:{ *:[i64] }:$vaddr, ?:{ *:[i32] }:$offset)
      GIR_BuildMI, /*InsnID*/0, /*Opcode*/GIMT_Encode2(AMDGPU::GLOBAL_LOAD_DWORDX4),
      GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/0, // DstI[vdst]
      GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/0, // vaddr
      GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/1, // offset
      GIR_AddImm8, /*InsnID*/0, /*Imm*/0,
      GIR_MergeMemOperands, /*InsnID*/0, /*NumInsns*/1, /*MergeInsnID's*/0,
      GIR_ConstrainSelectedInstOperands, /*InsnID*/0,
      GIR_EraseFromParent, /*InsnID*/0,
      // GIR_Coverage, 3082,
      GIR_Done,
    // Label 1371: @90928
    GIM_Try, /*On fail goto*//*Label 1372*/ GIMT_Encode4(90993), // Rule ID 2813 //
      GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasFlatAddressSpace),
      GIM_CheckMemoryAddressSpace, /*MI*/0, /*MMO*/0, /*NumAddrSpace*/4, /*AddrSpace*/0, /*AddrSpace*/1, /*AddrSpace*/4, /*AddrSpace*/6,
      GIM_CheckAtomicOrdering, /*MI*/0, /*Order*/(uint8_t)AtomicOrdering::NotAtomic,
      GIM_CheckRegBankForClass, /*MI*/0, /*Op*/0, /*RC*/GIMT_Encode2(AMDGPU::AV_128RegClassID),
      GIM_CheckPointerToAny, /*MI*/0, /*Op*/1, /*SizeInBits*/0,
      GIM_CheckComplexPattern, /*MI*/0, /*Op*/1, /*Renderer*/GIMT_Encode2(0), GIMT_Encode2(GICP_gi_flat_offset),
      // (ld:{ *:[v2i64] } (FlatOffset:{ *:[iPTR] } i64:{ *:[i64] }:$vaddr, i32:{ *:[i32] }:$offset))<<P:Predicate_unindexedload>><<P:Predicate_load_flat>>  =>  (FLAT_LOAD_DWORDX4:{ *:[v2i64] } ?:{ *:[i64] }:$vaddr, ?:{ *:[i32] }:$offset)
      GIR_BuildMI, /*InsnID*/0, /*Opcode*/GIMT_Encode2(AMDGPU::FLAT_LOAD_DWORDX4),
      GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/0, // DstI[vdst]
      GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/0, // vaddr
      GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/1, // offset
      GIR_AddImm8, /*InsnID*/0, /*Imm*/0,
      GIR_MergeMemOperands, /*InsnID*/0, /*NumInsns*/1, /*MergeInsnID's*/0,
      GIR_ConstrainSelectedInstOperands, /*InsnID*/0,
      GIR_EraseFromParent, /*InsnID*/0,
      // GIR_Coverage, 2813,
      GIR_Done,
    // Label 1372: @90993
    GIM_Try, /*On fail goto*//*Label 1373*/ GIMT_Encode4(91058), // Rule ID 2815 //
      GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasFlatAddressSpace),
      GIM_CheckMemoryAddressSpace, /*MI*/0, /*MMO*/0, /*NumAddrSpace*/4, /*AddrSpace*/0, /*AddrSpace*/1, /*AddrSpace*/4, /*AddrSpace*/6,
      GIM_CheckAtomicOrdering, /*MI*/0, /*Order*/(uint8_t)AtomicOrdering::NotAtomic,
      GIM_CheckRegBankForClass, /*MI*/0, /*Op*/0, /*RC*/GIMT_Encode2(AMDGPU::AV_128RegClassID),
      GIM_CheckPointerToAny, /*MI*/0, /*Op*/1, /*SizeInBits*/0,
      GIM_CheckComplexPattern, /*MI*/0, /*Op*/1, /*Renderer*/GIMT_Encode2(0), GIMT_Encode2(GICP_gi_flat_offset),
      // (ld:{ *:[v2f64] } (FlatOffset:{ *:[iPTR] } i64:{ *:[i64] }:$vaddr, i32:{ *:[i32] }:$offset))<<P:Predicate_unindexedload>><<P:Predicate_load_flat>>  =>  (FLAT_LOAD_DWORDX4:{ *:[v2f64] } ?:{ *:[i64] }:$vaddr, ?:{ *:[i32] }:$offset)
      GIR_BuildMI, /*InsnID*/0, /*Opcode*/GIMT_Encode2(AMDGPU::FLAT_LOAD_DWORDX4),
      GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/0, // DstI[vdst]
      GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/0, // vaddr
      GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/1, // offset
      GIR_AddImm8, /*InsnID*/0, /*Imm*/0,
      GIR_MergeMemOperands, /*InsnID*/0, /*NumInsns*/1, /*MergeInsnID's*/0,
      GIR_ConstrainSelectedInstOperands, /*InsnID*/0,
      GIR_EraseFromParent, /*InsnID*/0,
      // GIR_Coverage, 2815,
      GIR_Done,
    // Label 1373: @91058
    GIM_Reject,
    // Label 830: @91059
    GIM_Try, /*On fail goto*//*Label 1374*/ GIMT_Encode4(91129), // Rule ID 2551 //
      GIM_CheckFeatures, GIMT_Encode2(GIFBS_isGFX9Plus),
      GIM_CheckMemorySizeEqualToLLT, /*MI*/0, /*MMO*/0, /*OpIdx*/0,
      GIM_CheckAtomicOrdering, /*MI*/0, /*Order*/(uint8_t)AtomicOrdering::NotAtomic,
      GIM_CheckRegBankForClass, /*MI*/0, /*Op*/0, /*RC*/GIMT_Encode2(AMDGPU::SReg_96RegClassID),
      GIM_CheckPointerToAny, /*MI*/0, /*Op*/1, /*SizeInBits*/0,
      GIM_CheckCxxInsnPredicate, /*MI*/0, /*FnId*/GIMT_Encode2(GICXXPred_MI_Predicate_smrd_load),
      GIM_CheckComplexPattern, /*MI*/0, /*Op*/1, /*Renderer*/GIMT_Encode2(0), GIMT_Encode2(GICP_gi_smrd_sgpr_imm),
      // (ld:{ *:[v3i32] } (SMRDSgprImm:{ *:[iPTR] } i64:{ *:[i64] }:$sbase, i32:{ *:[i32] }:$soffset, i32:{ *:[i32] }:$offset))<<P:Predicate_unindexedload>><<P:Predicate_load>><<P:Predicate_smrd_load>>  =>  (S_LOAD_DWORDX3_SGPR_IMM:{ *:[v3i32] } ?:{ *:[i64] }:$sbase, ?:{ *:[i32] }:$soffset, ?:{ *:[i32] }:$offset, 0:{ *:[i32] })
      GIR_BuildMI, /*InsnID*/0, /*Opcode*/GIMT_Encode2(AMDGPU::S_LOAD_DWORDX3_SGPR_IMM),
      GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/0, // DstI[sdst]
      GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/0, // sbase
      GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/1, // soffset
      GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/2, // offset
      GIR_AddImm8, /*InsnID*/0, /*Imm*/0,
      GIR_MergeMemOperands, /*InsnID*/0, /*NumInsns*/1, /*MergeInsnID's*/0,
      GIR_ConstrainSelectedInstOperands, /*InsnID*/0,
      GIR_EraseFromParent, /*InsnID*/0,
      // GIR_Coverage, 2551,
      GIR_Done,
    // Label 1374: @91129
    GIM_Try, /*On fail goto*//*Label 1375*/ GIMT_Encode4(91199), // Rule ID 2556 //
      GIM_CheckFeatures, GIMT_Encode2(GIFBS_isGFX9Plus),
      GIM_CheckMemorySizeEqualToLLT, /*MI*/0, /*MMO*/0, /*OpIdx*/0,
      GIM_CheckAtomicOrdering, /*MI*/0, /*Order*/(uint8_t)AtomicOrdering::NotAtomic,
      GIM_CheckRegBankForClass, /*MI*/0, /*Op*/0, /*RC*/GIMT_Encode2(AMDGPU::SReg_96RegClassID),
      GIM_CheckPointerToAny, /*MI*/0, /*Op*/1, /*SizeInBits*/0,
      GIM_CheckCxxInsnPredicate, /*MI*/0, /*FnId*/GIMT_Encode2(GICXXPred_MI_Predicate_smrd_load),
      GIM_CheckComplexPattern, /*MI*/0, /*Op*/1, /*Renderer*/GIMT_Encode2(0), GIMT_Encode2(GICP_gi_smrd_sgpr_imm),
      // (ld:{ *:[v3f32] } (SMRDSgprImm:{ *:[iPTR] } i64:{ *:[i64] }:$sbase, i32:{ *:[i32] }:$soffset, i32:{ *:[i32] }:$offset))<<P:Predicate_unindexedload>><<P:Predicate_load>><<P:Predicate_smrd_load>>  =>  (S_LOAD_DWORDX3_SGPR_IMM:{ *:[v3f32] } ?:{ *:[i64] }:$sbase, ?:{ *:[i32] }:$soffset, ?:{ *:[i32] }:$offset, 0:{ *:[i32] })
      GIR_BuildMI, /*InsnID*/0, /*Opcode*/GIMT_Encode2(AMDGPU::S_LOAD_DWORDX3_SGPR_IMM),
      GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/0, // DstI[sdst]
      GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/0, // sbase
      GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/1, // soffset
      GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/2, // offset
      GIR_AddImm8, /*InsnID*/0, /*Imm*/0,
      GIR_MergeMemOperands, /*InsnID*/0, /*NumInsns*/1, /*MergeInsnID's*/0,
      GIR_ConstrainSelectedInstOperands, /*InsnID*/0,
      GIR_EraseFromParent, /*InsnID*/0,
      // GIR_Coverage, 2556,
      GIR_Done,
    // Label 1375: @91199
    GIM_Try, /*On fail goto*//*Label 1376*/ GIMT_Encode4(91265), // Rule ID 6855 //
      GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasUnalignedAccessMode_LDSRequiresM0Init),
      GIM_CheckMemorySizeEqualToLLT, /*MI*/0, /*MMO*/0, /*OpIdx*/0,
      GIM_CheckMemoryAddressSpace, /*MI*/0, /*MMO*/0, /*NumAddrSpace*/1, /*AddrSpace*/3,
      GIM_CheckAtomicOrdering, /*MI*/0, /*Order*/(uint8_t)AtomicOrdering::NotAtomic,
      GIM_CheckRegBankForClass, /*MI*/0, /*Op*/0, /*RC*/GIMT_Encode2(AMDGPU::AV_96RegClassID),
      GIM_CheckPointerToAny, /*MI*/0, /*Op*/1, /*SizeInBits*/0,
      GIM_CheckComplexPattern, /*MI*/0, /*Op*/1, /*Renderer*/GIMT_Encode2(0), GIMT_Encode2(GICP_gi_ds_1addr_1offset),
      // (AMDGPUld_glue:{ *:[v3i32] } (DS1Addr1Offset:{ *:[iPTR] } i32:{ *:[i32] }:$ptr, i32:{ *:[i32] }:$offset))<<P:Predicate_unindexedload_glue>><<P:Predicate_load_glue>><<P:Predicate_load_local_m0>>  =>  (DS_READ_B96:{ *:[v3i32] } ?:{ *:[i32] }:$ptr, offset:{ *:[i32] }:$offset, 0:{ *:[i1] })
      GIR_BuildMI, /*InsnID*/0, /*Opcode*/GIMT_Encode2(AMDGPU::DS_READ_B96),
      GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/0, // DstI[vdst]
      GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/0, // ptr
      GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/1, // offset
      GIR_AddImm8, /*InsnID*/0, /*Imm*/0,
      GIR_MergeMemOperands, /*InsnID*/0, /*NumInsns*/1, /*MergeInsnID's*/0,
      GIR_ConstrainSelectedInstOperands, /*InsnID*/0,
      GIR_EraseFromParent, /*InsnID*/0,
      // GIR_Coverage, 6855,
      GIR_Done,
    // Label 1376: @91265
    GIM_Try, /*On fail goto*//*Label 1377*/ GIMT_Encode4(91331), // Rule ID 6859 //
      GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasUnalignedAccessMode_LDSRequiresM0Init),
      GIM_CheckMemorySizeEqualToLLT, /*MI*/0, /*MMO*/0, /*OpIdx*/0,
      GIM_CheckMemoryAddressSpace, /*MI*/0, /*MMO*/0, /*NumAddrSpace*/1, /*AddrSpace*/3,
      GIM_CheckAtomicOrdering, /*MI*/0, /*Order*/(uint8_t)AtomicOrdering::NotAtomic,
      GIM_CheckRegBankForClass, /*MI*/0, /*Op*/0, /*RC*/GIMT_Encode2(AMDGPU::AV_96RegClassID),
      GIM_CheckPointerToAny, /*MI*/0, /*Op*/1, /*SizeInBits*/0,
      GIM_CheckComplexPattern, /*MI*/0, /*Op*/1, /*Renderer*/GIMT_Encode2(0), GIMT_Encode2(GICP_gi_ds_1addr_1offset),
      // (AMDGPUld_glue:{ *:[v3f32] } (DS1Addr1Offset:{ *:[iPTR] } i32:{ *:[i32] }:$ptr, i32:{ *:[i32] }:$offset))<<P:Predicate_unindexedload_glue>><<P:Predicate_load_glue>><<P:Predicate_load_local_m0>>  =>  (DS_READ_B96:{ *:[v3f32] } ?:{ *:[i32] }:$ptr, offset:{ *:[i32] }:$offset, 0:{ *:[i1] })
      GIR_BuildMI, /*InsnID*/0, /*Opcode*/GIMT_Encode2(AMDGPU::DS_READ_B96),
      GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/0, // DstI[vdst]
      GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/0, // ptr
      GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/1, // offset
      GIR_AddImm8, /*InsnID*/0, /*Imm*/0,
      GIR_MergeMemOperands, /*InsnID*/0, /*NumInsns*/1, /*MergeInsnID's*/0,
      GIR_ConstrainSelectedInstOperands, /*InsnID*/0,
      GIR_EraseFromParent, /*InsnID*/0,
      // GIR_Coverage, 6859,
      GIR_Done,
    // Label 1377: @91331
    GIM_Try, /*On fail goto*//*Label 1378*/ GIMT_Encode4(91401), // Rule ID 6779 //
      GIM_CheckFeatures, GIMT_Encode2(GIFBS_LDSRequiresM0Init_isGFX7Plus),
      GIM_CheckMemorySizeEqualToLLT, /*MI*/0, /*MMO*/0, /*OpIdx*/0,
      GIM_CheckMemoryAddressSpace, /*MI*/0, /*MMO*/0, /*NumAddrSpace*/1, /*AddrSpace*/3,
      GIM_CheckMemoryAlignment, /*MI*/0, /*MMO*/0, /*MinAlign*/16,
      GIM_CheckAtomicOrdering, /*MI*/0, /*Order*/(uint8_t)AtomicOrdering::NotAtomic,
      GIM_CheckRegBankForClass, /*MI*/0, /*Op*/0, /*RC*/GIMT_Encode2(AMDGPU::AV_96RegClassID),
      GIM_CheckPointerToAny, /*MI*/0, /*Op*/1, /*SizeInBits*/0,
      GIM_CheckComplexPattern, /*MI*/0, /*Op*/1, /*Renderer*/GIMT_Encode2(0), GIMT_Encode2(GICP_gi_ds_1addr_1offset),
      // (AMDGPUld_glue:{ *:[v3i32] } (DS1Addr1Offset:{ *:[iPTR] } i32:{ *:[i32] }:$ptr, i32:{ *:[i32] }:$offset))<<P:Predicate_unindexedload_glue>><<P:Predicate_load_glue>><<P:Predicate_load_local_m0>><<P:Predicate_load_align16_local_m0>>  =>  (DS_READ_B96:{ *:[v3i32] } ?:{ *:[i32] }:$ptr, offset:{ *:[i32] }:$offset, 0:{ *:[i1] })
      GIR_BuildMI, /*InsnID*/0, /*Opcode*/GIMT_Encode2(AMDGPU::DS_READ_B96),
      GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/0, // DstI[vdst]
      GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/0, // ptr
      GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/1, // offset
      GIR_AddImm8, /*InsnID*/0, /*Imm*/0,
      GIR_MergeMemOperands, /*InsnID*/0, /*NumInsns*/1, /*MergeInsnID's*/0,
      GIR_ConstrainSelectedInstOperands, /*InsnID*/0,
      GIR_EraseFromParent, /*InsnID*/0,
      // GIR_Coverage, 6779,
      GIR_Done,
    // Label 1378: @91401
    GIM_Try, /*On fail goto*//*Label 1379*/ GIMT_Encode4(91471), // Rule ID 6783 //
      GIM_CheckFeatures, GIMT_Encode2(GIFBS_LDSRequiresM0Init_isGFX7Plus),
      GIM_CheckMemorySizeEqualToLLT, /*MI*/0, /*MMO*/0, /*OpIdx*/0,
      GIM_CheckMemoryAddressSpace, /*MI*/0, /*MMO*/0, /*NumAddrSpace*/1, /*AddrSpace*/3,
      GIM_CheckMemoryAlignment, /*MI*/0, /*MMO*/0, /*MinAlign*/16,
      GIM_CheckAtomicOrdering, /*MI*/0, /*Order*/(uint8_t)AtomicOrdering::NotAtomic,
      GIM_CheckRegBankForClass, /*MI*/0, /*Op*/0, /*RC*/GIMT_Encode2(AMDGPU::AV_96RegClassID),
      GIM_CheckPointerToAny, /*MI*/0, /*Op*/1, /*SizeInBits*/0,
      GIM_CheckComplexPattern, /*MI*/0, /*Op*/1, /*Renderer*/GIMT_Encode2(0), GIMT_Encode2(GICP_gi_ds_1addr_1offset),
      // (AMDGPUld_glue:{ *:[v3f32] } (DS1Addr1Offset:{ *:[iPTR] } i32:{ *:[i32] }:$ptr, i32:{ *:[i32] }:$offset))<<P:Predicate_unindexedload_glue>><<P:Predicate_load_glue>><<P:Predicate_load_local_m0>><<P:Predicate_load_align16_local_m0>>  =>  (DS_READ_B96:{ *:[v3f32] } ?:{ *:[i32] }:$ptr, offset:{ *:[i32] }:$offset, 0:{ *:[i1] })
      GIR_BuildMI, /*InsnID*/0, /*Opcode*/GIMT_Encode2(AMDGPU::DS_READ_B96),
      GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/0, // DstI[vdst]
      GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/0, // ptr
      GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/1, // offset
      GIR_AddImm8, /*InsnID*/0, /*Imm*/0,
      GIR_MergeMemOperands, /*InsnID*/0, /*NumInsns*/1, /*MergeInsnID's*/0,
      GIR_ConstrainSelectedInstOperands, /*InsnID*/0,
      GIR_EraseFromParent, /*InsnID*/0,
      // GIR_Coverage, 6783,
      GIR_Done,
    // Label 1379: @91471
    GIM_Try, /*On fail goto*//*Label 1380*/ GIMT_Encode4(91533), // Rule ID 2548 //
      GIM_CheckMemorySizeEqualToLLT, /*MI*/0, /*MMO*/0, /*OpIdx*/0,
      GIM_CheckAtomicOrdering, /*MI*/0, /*Order*/(uint8_t)AtomicOrdering::NotAtomic,
      GIM_CheckRegBankForClass, /*MI*/0, /*Op*/0, /*RC*/GIMT_Encode2(AMDGPU::SReg_96RegClassID),
      GIM_CheckPointerToAny, /*MI*/0, /*Op*/1, /*SizeInBits*/0,
      GIM_CheckCxxInsnPredicate, /*MI*/0, /*FnId*/GIMT_Encode2(GICXXPred_MI_Predicate_smrd_load),
      GIM_CheckComplexPattern, /*MI*/0, /*Op*/1, /*Renderer*/GIMT_Encode2(0), GIMT_Encode2(GICP_gi_smrd_imm),
      // (ld:{ *:[v3i32] } (SMRDImm:{ *:[iPTR] } i64:{ *:[i64] }:$sbase, i32:{ *:[i32] }:$offset))<<P:Predicate_unindexedload>><<P:Predicate_load>><<P:Predicate_smrd_load>>  =>  (S_LOAD_DWORDX3_IMM:{ *:[v3i32] } ?:{ *:[i64] }:$sbase, ?:{ *:[i32] }:$offset, 0:{ *:[i32] })
      GIR_BuildMI, /*InsnID*/0, /*Opcode*/GIMT_Encode2(AMDGPU::S_LOAD_DWORDX3_IMM),
      GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/0, // DstI[sdst]
      GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/0, // sbase
      GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/1, // offset
      GIR_AddImm8, /*InsnID*/0, /*Imm*/0,
      GIR_MergeMemOperands, /*InsnID*/0, /*NumInsns*/1, /*MergeInsnID's*/0,
      GIR_ConstrainSelectedInstOperands, /*InsnID*/0,
      GIR_EraseFromParent, /*InsnID*/0,
      // GIR_Coverage, 2548,
      GIR_Done,
    // Label 1380: @91533
    GIM_Try, /*On fail goto*//*Label 1381*/ GIMT_Encode4(91598), // Rule ID 2549 //
      GIM_CheckFeatures, GIMT_Encode2(GIFBS_isNotGFX9Plus),
      GIM_CheckMemorySizeEqualToLLT, /*MI*/0, /*MMO*/0, /*OpIdx*/0,
      GIM_CheckAtomicOrdering, /*MI*/0, /*Order*/(uint8_t)AtomicOrdering::NotAtomic,
      GIM_CheckRegBankForClass, /*MI*/0, /*Op*/0, /*RC*/GIMT_Encode2(AMDGPU::SReg_96RegClassID),
      GIM_CheckPointerToAny, /*MI*/0, /*Op*/1, /*SizeInBits*/0,
      GIM_CheckCxxInsnPredicate, /*MI*/0, /*FnId*/GIMT_Encode2(GICXXPred_MI_Predicate_smrd_load),
      GIM_CheckComplexPattern, /*MI*/0, /*Op*/1, /*Renderer*/GIMT_Encode2(0), GIMT_Encode2(GICP_gi_smrd_sgpr),
      // (ld:{ *:[v3i32] } (SMRDSgpr:{ *:[iPTR] } i64:{ *:[i64] }:$sbase, i32:{ *:[i32] }:$soffset))<<P:Predicate_unindexedload>><<P:Predicate_load>><<P:Predicate_smrd_load>>  =>  (S_LOAD_DWORDX3_SGPR:{ *:[v3i32] } ?:{ *:[i64] }:$sbase, ?:{ *:[i32] }:$soffset, 0:{ *:[i32] })
      GIR_BuildMI, /*InsnID*/0, /*Opcode*/GIMT_Encode2(AMDGPU::S_LOAD_DWORDX3_SGPR),
      GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/0, // DstI[sdst]
      GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/0, // sbase
      GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/1, // soffset
      GIR_AddImm8, /*InsnID*/0, /*Imm*/0,
      GIR_MergeMemOperands, /*InsnID*/0, /*NumInsns*/1, /*MergeInsnID's*/0,
      GIR_ConstrainSelectedInstOperands, /*InsnID*/0,
      GIR_EraseFromParent, /*InsnID*/0,
      // GIR_Coverage, 2549,
      GIR_Done,
    // Label 1381: @91598
    GIM_Try, /*On fail goto*//*Label 1382*/ GIMT_Encode4(91666), // Rule ID 2550 //
      GIM_CheckFeatures, GIMT_Encode2(GIFBS_isGFX9Plus),
      GIM_CheckMemorySizeEqualToLLT, /*MI*/0, /*MMO*/0, /*OpIdx*/0,
      GIM_CheckAtomicOrdering, /*MI*/0, /*Order*/(uint8_t)AtomicOrdering::NotAtomic,
      GIM_CheckRegBankForClass, /*MI*/0, /*Op*/0, /*RC*/GIMT_Encode2(AMDGPU::SReg_96RegClassID),
      GIM_CheckPointerToAny, /*MI*/0, /*Op*/1, /*SizeInBits*/0,
      GIM_CheckCxxInsnPredicate, /*MI*/0, /*FnId*/GIMT_Encode2(GICXXPred_MI_Predicate_smrd_load),
      GIM_CheckComplexPattern, /*MI*/0, /*Op*/1, /*Renderer*/GIMT_Encode2(0), GIMT_Encode2(GICP_gi_smrd_sgpr),
      // (ld:{ *:[v3i32] } (SMRDSgpr:{ *:[iPTR] } i64:{ *:[i64] }:$sbase, i32:{ *:[i32] }:$soffset))<<P:Predicate_unindexedload>><<P:Predicate_load>><<P:Predicate_smrd_load>>  =>  (S_LOAD_DWORDX3_SGPR_IMM:{ *:[v3i32] } ?:{ *:[i64] }:$sbase, ?:{ *:[i32] }:$soffset, 0:{ *:[i32] }, 0:{ *:[i32] })
      GIR_BuildMI, /*InsnID*/0, /*Opcode*/GIMT_Encode2(AMDGPU::S_LOAD_DWORDX3_SGPR_IMM),
      GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/0, // DstI[sdst]
      GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/0, // sbase
      GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/1, // soffset
      GIR_AddImm8, /*InsnID*/0, /*Imm*/0,
      GIR_AddImm8, /*InsnID*/0, /*Imm*/0,
      GIR_MergeMemOperands, /*InsnID*/0, /*NumInsns*/1, /*MergeInsnID's*/0,
      GIR_ConstrainSelectedInstOperands, /*InsnID*/0,
      GIR_EraseFromParent, /*InsnID*/0,
      // GIR_Coverage, 2550,
      GIR_Done,
    // Label 1382: @91666
    GIM_Try, /*On fail goto*//*Label 1383*/ GIMT_Encode4(91728), // Rule ID 2553 //
      GIM_CheckMemorySizeEqualToLLT, /*MI*/0, /*MMO*/0, /*OpIdx*/0,
      GIM_CheckAtomicOrdering, /*MI*/0, /*Order*/(uint8_t)AtomicOrdering::NotAtomic,
      GIM_CheckRegBankForClass, /*MI*/0, /*Op*/0, /*RC*/GIMT_Encode2(AMDGPU::SReg_96RegClassID),
      GIM_CheckPointerToAny, /*MI*/0, /*Op*/1, /*SizeInBits*/0,
      GIM_CheckCxxInsnPredicate, /*MI*/0, /*FnId*/GIMT_Encode2(GICXXPred_MI_Predicate_smrd_load),
      GIM_CheckComplexPattern, /*MI*/0, /*Op*/1, /*Renderer*/GIMT_Encode2(0), GIMT_Encode2(GICP_gi_smrd_imm),
      // (ld:{ *:[v3f32] } (SMRDImm:{ *:[iPTR] } i64:{ *:[i64] }:$sbase, i32:{ *:[i32] }:$offset))<<P:Predicate_unindexedload>><<P:Predicate_load>><<P:Predicate_smrd_load>>  =>  (S_LOAD_DWORDX3_IMM:{ *:[v3f32] } ?:{ *:[i64] }:$sbase, ?:{ *:[i32] }:$offset, 0:{ *:[i32] })
      GIR_BuildMI, /*InsnID*/0, /*Opcode*/GIMT_Encode2(AMDGPU::S_LOAD_DWORDX3_IMM),
      GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/0, // DstI[sdst]
      GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/0, // sbase
      GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/1, // offset
      GIR_AddImm8, /*InsnID*/0, /*Imm*/0,
      GIR_MergeMemOperands, /*InsnID*/0, /*NumInsns*/1, /*MergeInsnID's*/0,
      GIR_ConstrainSelectedInstOperands, /*InsnID*/0,
      GIR_EraseFromParent, /*InsnID*/0,
      // GIR_Coverage, 2553,
      GIR_Done,
    // Label 1383: @91728
    GIM_Try, /*On fail goto*//*Label 1384*/ GIMT_Encode4(91793), // Rule ID 2554 //
      GIM_CheckFeatures, GIMT_Encode2(GIFBS_isNotGFX9Plus),
      GIM_CheckMemorySizeEqualToLLT, /*MI*/0, /*MMO*/0, /*OpIdx*/0,
      GIM_CheckAtomicOrdering, /*MI*/0, /*Order*/(uint8_t)AtomicOrdering::NotAtomic,
      GIM_CheckRegBankForClass, /*MI*/0, /*Op*/0, /*RC*/GIMT_Encode2(AMDGPU::SReg_96RegClassID),
      GIM_CheckPointerToAny, /*MI*/0, /*Op*/1, /*SizeInBits*/0,
      GIM_CheckCxxInsnPredicate, /*MI*/0, /*FnId*/GIMT_Encode2(GICXXPred_MI_Predicate_smrd_load),
      GIM_CheckComplexPattern, /*MI*/0, /*Op*/1, /*Renderer*/GIMT_Encode2(0), GIMT_Encode2(GICP_gi_smrd_sgpr),
      // (ld:{ *:[v3f32] } (SMRDSgpr:{ *:[iPTR] } i64:{ *:[i64] }:$sbase, i32:{ *:[i32] }:$soffset))<<P:Predicate_unindexedload>><<P:Predicate_load>><<P:Predicate_smrd_load>>  =>  (S_LOAD_DWORDX3_SGPR:{ *:[v3f32] } ?:{ *:[i64] }:$sbase, ?:{ *:[i32] }:$soffset, 0:{ *:[i32] })
      GIR_BuildMI, /*InsnID*/0, /*Opcode*/GIMT_Encode2(AMDGPU::S_LOAD_DWORDX3_SGPR),
      GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/0, // DstI[sdst]
      GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/0, // sbase
      GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/1, // soffset
      GIR_AddImm8, /*InsnID*/0, /*Imm*/0,
      GIR_MergeMemOperands, /*InsnID*/0, /*NumInsns*/1, /*MergeInsnID's*/0,
      GIR_ConstrainSelectedInstOperands, /*InsnID*/0,
      GIR_EraseFromParent, /*InsnID*/0,
      // GIR_Coverage, 2554,
      GIR_Done,
    // Label 1384: @91793
    GIM_Try, /*On fail goto*//*Label 1385*/ GIMT_Encode4(91861), // Rule ID 2555 //
      GIM_CheckFeatures, GIMT_Encode2(GIFBS_isGFX9Plus),
      GIM_CheckMemorySizeEqualToLLT, /*MI*/0, /*MMO*/0, /*OpIdx*/0,
      GIM_CheckAtomicOrdering, /*MI*/0, /*Order*/(uint8_t)AtomicOrdering::NotAtomic,
      GIM_CheckRegBankForClass, /*MI*/0, /*Op*/0, /*RC*/GIMT_Encode2(AMDGPU::SReg_96RegClassID),
      GIM_CheckPointerToAny, /*MI*/0, /*Op*/1, /*SizeInBits*/0,
      GIM_CheckCxxInsnPredicate, /*MI*/0, /*FnId*/GIMT_Encode2(GICXXPred_MI_Predicate_smrd_load),
      GIM_CheckComplexPattern, /*MI*/0, /*Op*/1, /*Renderer*/GIMT_Encode2(0), GIMT_Encode2(GICP_gi_smrd_sgpr),
      // (ld:{ *:[v3f32] } (SMRDSgpr:{ *:[iPTR] } i64:{ *:[i64] }:$sbase, i32:{ *:[i32] }:$soffset))<<P:Predicate_unindexedload>><<P:Predicate_load>><<P:Predicate_smrd_load>>  =>  (S_LOAD_DWORDX3_SGPR_IMM:{ *:[v3f32] } ?:{ *:[i64] }:$sbase, ?:{ *:[i32] }:$soffset, 0:{ *:[i32] }, 0:{ *:[i32] })
      GIR_BuildMI, /*InsnID*/0, /*Opcode*/GIMT_Encode2(AMDGPU::S_LOAD_DWORDX3_SGPR_IMM),
      GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/0, // DstI[sdst]
      GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/0, // sbase
      GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/1, // soffset
      GIR_AddImm8, /*InsnID*/0, /*Imm*/0,
      GIR_AddImm8, /*InsnID*/0, /*Imm*/0,
      GIR_MergeMemOperands, /*InsnID*/0, /*NumInsns*/1, /*MergeInsnID's*/0,
      GIR_ConstrainSelectedInstOperands, /*InsnID*/0,
      GIR_EraseFromParent, /*InsnID*/0,
      // GIR_Coverage, 2555,
      GIR_Done,
    // Label 1385: @91861
    GIM_Try, /*On fail goto*//*Label 1386*/ GIMT_Encode4(91923), // Rule ID 6856 //
      GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasUnalignedAccessMode_NotLDSRequiresM0Init),
      GIM_CheckMemoryAddressSpace, /*MI*/0, /*MMO*/0, /*NumAddrSpace*/1, /*AddrSpace*/3,
      GIM_CheckAtomicOrdering, /*MI*/0, /*Order*/(uint8_t)AtomicOrdering::NotAtomic,
      GIM_CheckRegBankForClass, /*MI*/0, /*Op*/0, /*RC*/GIMT_Encode2(AMDGPU::AV_96RegClassID),
      GIM_CheckPointerToAny, /*MI*/0, /*Op*/1, /*SizeInBits*/0,
      GIM_CheckComplexPattern, /*MI*/0, /*Op*/1, /*Renderer*/GIMT_Encode2(0), GIMT_Encode2(GICP_gi_ds_1addr_1offset),
      // (ld:{ *:[v3i32] } (DS1Addr1Offset:{ *:[iPTR] } i32:{ *:[i32] }:$ptr, i32:{ *:[i32] }:$offset))<<P:Predicate_unindexedload>><<P:Predicate_load_local>>  =>  (DS_READ_B96_gfx9:{ *:[v3i32] } ?:{ *:[i32] }:$ptr, offset:{ *:[i32] }:$offset, 0:{ *:[i1] })
      GIR_BuildMI, /*InsnID*/0, /*Opcode*/GIMT_Encode2(AMDGPU::DS_READ_B96_gfx9),
      GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/0, // DstI[vdst]
      GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/0, // ptr
      GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/1, // offset
      GIR_AddImm8, /*InsnID*/0, /*Imm*/0,
      GIR_MergeMemOperands, /*InsnID*/0, /*NumInsns*/1, /*MergeInsnID's*/0,
      GIR_ConstrainSelectedInstOperands, /*InsnID*/0,
      GIR_EraseFromParent, /*InsnID*/0,
      // GIR_Coverage, 6856,
      GIR_Done,
    // Label 1386: @91923
    GIM_Try, /*On fail goto*//*Label 1387*/ GIMT_Encode4(91985), // Rule ID 6860 //
      GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasUnalignedAccessMode_NotLDSRequiresM0Init),
      GIM_CheckMemoryAddressSpace, /*MI*/0, /*MMO*/0, /*NumAddrSpace*/1, /*AddrSpace*/3,
      GIM_CheckAtomicOrdering, /*MI*/0, /*Order*/(uint8_t)AtomicOrdering::NotAtomic,
      GIM_CheckRegBankForClass, /*MI*/0, /*Op*/0, /*RC*/GIMT_Encode2(AMDGPU::AV_96RegClassID),
      GIM_CheckPointerToAny, /*MI*/0, /*Op*/1, /*SizeInBits*/0,
      GIM_CheckComplexPattern, /*MI*/0, /*Op*/1, /*Renderer*/GIMT_Encode2(0), GIMT_Encode2(GICP_gi_ds_1addr_1offset),
      // (ld:{ *:[v3f32] } (DS1Addr1Offset:{ *:[iPTR] } i32:{ *:[i32] }:$ptr, i32:{ *:[i32] }:$offset))<<P:Predicate_unindexedload>><<P:Predicate_load_local>>  =>  (DS_READ_B96_gfx9:{ *:[v3f32] } ?:{ *:[i32] }:$ptr, offset:{ *:[i32] }:$offset, 0:{ *:[i1] })
      GIR_BuildMI, /*InsnID*/0, /*Opcode*/GIMT_Encode2(AMDGPU::DS_READ_B96_gfx9),
      GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/0, // DstI[vdst]
      GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/0, // ptr
      GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/1, // offset
      GIR_AddImm8, /*InsnID*/0, /*Imm*/0,
      GIR_MergeMemOperands, /*InsnID*/0, /*NumInsns*/1, /*MergeInsnID's*/0,
      GIR_ConstrainSelectedInstOperands, /*InsnID*/0,
      GIR_EraseFromParent, /*InsnID*/0,
      // GIR_Coverage, 6860,
      GIR_Done,
    // Label 1387: @91985
    GIM_Try, /*On fail goto*//*Label 1388*/ GIMT_Encode4(92051), // Rule ID 6780 //
      GIM_CheckFeatures, GIMT_Encode2(GIFBS_NotLDSRequiresM0Init_isGFX7Plus),
      GIM_CheckMemoryAddressSpace, /*MI*/0, /*MMO*/0, /*NumAddrSpace*/1, /*AddrSpace*/3,
      GIM_CheckMemoryAlignment, /*MI*/0, /*MMO*/0, /*MinAlign*/16,
      GIM_CheckAtomicOrdering, /*MI*/0, /*Order*/(uint8_t)AtomicOrdering::NotAtomic,
      GIM_CheckRegBankForClass, /*MI*/0, /*Op*/0, /*RC*/GIMT_Encode2(AMDGPU::AV_96RegClassID),
      GIM_CheckPointerToAny, /*MI*/0, /*Op*/1, /*SizeInBits*/0,
      GIM_CheckComplexPattern, /*MI*/0, /*Op*/1, /*Renderer*/GIMT_Encode2(0), GIMT_Encode2(GICP_gi_ds_1addr_1offset),
      // (ld:{ *:[v3i32] } (DS1Addr1Offset:{ *:[iPTR] } i32:{ *:[i32] }:$ptr, i32:{ *:[i32] }:$offset))<<P:Predicate_unindexedload>><<P:Predicate_load_local>><<P:Predicate_load_align16_local>>  =>  (DS_READ_B96_gfx9:{ *:[v3i32] } ?:{ *:[i32] }:$ptr, offset:{ *:[i32] }:$offset, 0:{ *:[i1] })
      GIR_BuildMI, /*InsnID*/0, /*Opcode*/GIMT_Encode2(AMDGPU::DS_READ_B96_gfx9),
      GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/0, // DstI[vdst]
      GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/0, // ptr
      GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/1, // offset
      GIR_AddImm8, /*InsnID*/0, /*Imm*/0,
      GIR_MergeMemOperands, /*InsnID*/0, /*NumInsns*/1, /*MergeInsnID's*/0,
      GIR_ConstrainSelectedInstOperands, /*InsnID*/0,
      GIR_EraseFromParent, /*InsnID*/0,
      // GIR_Coverage, 6780,
      GIR_Done,
    // Label 1388: @92051
    GIM_Try, /*On fail goto*//*Label 1389*/ GIMT_Encode4(92117), // Rule ID 6784 //
      GIM_CheckFeatures, GIMT_Encode2(GIFBS_NotLDSRequiresM0Init_isGFX7Plus),
      GIM_CheckMemoryAddressSpace, /*MI*/0, /*MMO*/0, /*NumAddrSpace*/1, /*AddrSpace*/3,
      GIM_CheckMemoryAlignment, /*MI*/0, /*MMO*/0, /*MinAlign*/16,
      GIM_CheckAtomicOrdering, /*MI*/0, /*Order*/(uint8_t)AtomicOrdering::NotAtomic,
      GIM_CheckRegBankForClass, /*MI*/0, /*Op*/0, /*RC*/GIMT_Encode2(AMDGPU::AV_96RegClassID),
      GIM_CheckPointerToAny, /*MI*/0, /*Op*/1, /*SizeInBits*/0,
      GIM_CheckComplexPattern, /*MI*/0, /*Op*/1, /*Renderer*/GIMT_Encode2(0), GIMT_Encode2(GICP_gi_ds_1addr_1offset),
      // (ld:{ *:[v3f32] } (DS1Addr1Offset:{ *:[iPTR] } i32:{ *:[i32] }:$ptr, i32:{ *:[i32] }:$offset))<<P:Predicate_unindexedload>><<P:Predicate_load_local>><<P:Predicate_load_align16_local>>  =>  (DS_READ_B96_gfx9:{ *:[v3f32] } ?:{ *:[i32] }:$ptr, offset:{ *:[i32] }:$offset, 0:{ *:[i1] })
      GIR_BuildMI, /*InsnID*/0, /*Opcode*/GIMT_Encode2(AMDGPU::DS_READ_B96_gfx9),
      GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/0, // DstI[vdst]
      GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/0, // ptr
      GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/1, // offset
      GIR_AddImm8, /*InsnID*/0, /*Imm*/0,
      GIR_MergeMemOperands, /*InsnID*/0, /*NumInsns*/1, /*MergeInsnID's*/0,
      GIR_ConstrainSelectedInstOperands, /*InsnID*/0,
      GIR_EraseFromParent, /*InsnID*/0,
      // GIR_Coverage, 6784,
      GIR_Done,
    // Label 1389: @92117
    GIM_Try, /*On fail goto*//*Label 1390*/ GIMT_Encode4(92174), // Rule ID 2552 //
      GIM_CheckMemorySizeEqualToLLT, /*MI*/0, /*MMO*/0, /*OpIdx*/0,
      GIM_CheckAtomicOrdering, /*MI*/0, /*Order*/(uint8_t)AtomicOrdering::NotAtomic,
      GIM_CheckRegBankForClass, /*MI*/0, /*Op*/0, /*RC*/GIMT_Encode2(AMDGPU::SReg_96RegClassID),
      // MIs[0] sbase
      GIM_CheckPointerToAny, /*MI*/0, /*Op*/1, /*SizeInBits*/64,
      GIM_CheckRegBankForClass, /*MI*/0, /*Op*/1, /*RC*/GIMT_Encode2(AMDGPU::SReg_64RegClassID),
      GIM_CheckCxxInsnPredicate, /*MI*/0, /*FnId*/GIMT_Encode2(GICXXPred_MI_Predicate_smrd_load),
      // (ld:{ *:[v3i32] } SReg_64:{ *:[i64] }:$sbase)<<P:Predicate_unindexedload>><<P:Predicate_load>><<P:Predicate_smrd_load>>  =>  (S_LOAD_DWORDX3_IMM:{ *:[v3i32] } i64:{ *:[i64] }:$sbase, 0:{ *:[i32] }, 0:{ *:[i32] })
      GIR_BuildMI, /*InsnID*/0, /*Opcode*/GIMT_Encode2(AMDGPU::S_LOAD_DWORDX3_IMM),
      GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/0, // DstI[sdst]
      GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/1, // sbase
      GIR_AddImm8, /*InsnID*/0, /*Imm*/0,
      GIR_AddImm8, /*InsnID*/0, /*Imm*/0,
      GIR_MergeMemOperands, /*InsnID*/0, /*NumInsns*/1, /*MergeInsnID's*/0,
      GIR_ConstrainSelectedInstOperands, /*InsnID*/0,
      GIR_EraseFromParent, /*InsnID*/0,
      // GIR_Coverage, 2552,
      GIR_Done,
    // Label 1390: @92174
    GIM_Try, /*On fail goto*//*Label 1391*/ GIMT_Encode4(92231), // Rule ID 2557 //
      GIM_CheckMemorySizeEqualToLLT, /*MI*/0, /*MMO*/0, /*OpIdx*/0,
      GIM_CheckAtomicOrdering, /*MI*/0, /*Order*/(uint8_t)AtomicOrdering::NotAtomic,
      GIM_CheckRegBankForClass, /*MI*/0, /*Op*/0, /*RC*/GIMT_Encode2(AMDGPU::SReg_96RegClassID),
      // MIs[0] sbase
      GIM_CheckPointerToAny, /*MI*/0, /*Op*/1, /*SizeInBits*/64,
      GIM_CheckRegBankForClass, /*MI*/0, /*Op*/1, /*RC*/GIMT_Encode2(AMDGPU::SReg_64RegClassID),
      GIM_CheckCxxInsnPredicate, /*MI*/0, /*FnId*/GIMT_Encode2(GICXXPred_MI_Predicate_smrd_load),
      // (ld:{ *:[v3f32] } SReg_64:{ *:[i64] }:$sbase)<<P:Predicate_unindexedload>><<P:Predicate_load>><<P:Predicate_smrd_load>>  =>  (S_LOAD_DWORDX3_IMM:{ *:[v3f32] } i64:{ *:[i64] }:$sbase, 0:{ *:[i32] }, 0:{ *:[i32] })
      GIR_BuildMI, /*InsnID*/0, /*Opcode*/GIMT_Encode2(AMDGPU::S_LOAD_DWORDX3_IMM),
      GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/0, // DstI[sdst]
      GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/1, // sbase
      GIR_AddImm8, /*InsnID*/0, /*Imm*/0,
      GIR_AddImm8, /*InsnID*/0, /*Imm*/0,
      GIR_MergeMemOperands, /*InsnID*/0, /*NumInsns*/1, /*MergeInsnID's*/0,
      GIR_ConstrainSelectedInstOperands, /*InsnID*/0,
      GIR_EraseFromParent, /*InsnID*/0,
      // GIR_Coverage, 2557,
      GIR_Done,
    // Label 1391: @92231
    GIM_Try, /*On fail goto*//*Label 1392*/ GIMT_Encode4(92301), // Rule ID 5428 //
      GIM_CheckFeatures, GIMT_Encode2(GIFBS_DisableFlatScratch_HasUnrestrictedSOffset),
      GIM_CheckMemoryAddressSpace, /*MI*/0, /*MMO*/0, /*NumAddrSpace*/1, /*AddrSpace*/5,
      GIM_CheckAtomicOrdering, /*MI*/0, /*Order*/(uint8_t)AtomicOrdering::NotAtomic,
      GIM_CheckRegBankForClass, /*MI*/0, /*Op*/0, /*RC*/GIMT_Encode2(AMDGPU::AV_96RegClassID),
      GIM_CheckPointerToAny, /*MI*/0, /*Op*/1, /*SizeInBits*/0,
      GIM_CheckComplexPattern, /*MI*/0, /*Op*/1, /*Renderer*/GIMT_Encode2(0), GIMT_Encode2(GICP_gi_mubuf_scratch_offset),
      // (ld:{ *:[v3i32] } (MUBUFScratchOffset:{ *:[iPTR] } v4i32:{ *:[v4i32] }:$srsrc, i32:{ *:[i32] }:$soffset, i32:{ *:[i32] }:$offset))<<P:Predicate_unindexedload>><<P:Predicate_load_private>>  =>  (BUFFER_LOAD_DWORDX3_OFFSET:{ *:[v3i32] } ?:{ *:[v4i32] }:$srsrc, ?:{ *:[i32] }:$soffset, ?:{ *:[i32] }:$offset, 0:{ *:[i32] }, 0:{ *:[i1] })
      GIR_BuildMI, /*InsnID*/0, /*Opcode*/GIMT_Encode2(AMDGPU::BUFFER_LOAD_DWORDX3_OFFSET),
      GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/0, // DstI[vdata]
      GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/0, // srsrc
      GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/1, // soffset
      GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/2, // offset
      GIR_AddImm8, /*InsnID*/0, /*Imm*/0,
      GIR_AddImm8, /*InsnID*/0, /*Imm*/0,
      GIR_MergeMemOperands, /*InsnID*/0, /*NumInsns*/1, /*MergeInsnID's*/0,
      GIR_ConstrainSelectedInstOperands, /*InsnID*/0,
      GIR_EraseFromParent, /*InsnID*/0,
      // GIR_Coverage, 5428,
      GIR_Done,
    // Label 1392: @92301
    GIM_Try, /*On fail goto*//*Label 1393*/ GIMT_Encode4(92371), // Rule ID 5430 //
      GIM_CheckFeatures, GIMT_Encode2(GIFBS_DisableFlatScratch),
      GIM_CheckMemoryAddressSpace, /*MI*/0, /*MMO*/0, /*NumAddrSpace*/1, /*AddrSpace*/5,
      GIM_CheckAtomicOrdering, /*MI*/0, /*Order*/(uint8_t)AtomicOrdering::NotAtomic,
      GIM_CheckRegBankForClass, /*MI*/0, /*Op*/0, /*RC*/GIMT_Encode2(AMDGPU::AV_96RegClassID),
      GIM_CheckPointerToAny, /*MI*/0, /*Op*/1, /*SizeInBits*/0,
      GIM_CheckComplexPattern, /*MI*/0, /*Op*/1, /*Renderer*/GIMT_Encode2(0), GIMT_Encode2(GICP_gi_mubuf_scratch_offset),
      // (ld:{ *:[v3i32] } (MUBUFScratchOffset:{ *:[iPTR] } v4i32:{ *:[v4i32] }:$srsrc, i32:{ *:[i32] }:$soffset, i32:{ *:[i32] }:$offset))<<P:Predicate_unindexedload>><<P:Predicate_load_private>>  =>  (BUFFER_LOAD_DWORDX3_VBUFFER_OFFSET:{ *:[v3i32] } ?:{ *:[v4i32] }:$srsrc, ?:{ *:[i32] }:$soffset, ?:{ *:[i32] }:$offset, 0:{ *:[i32] }, 0:{ *:[i1] })
      GIR_BuildMI, /*InsnID*/0, /*Opcode*/GIMT_Encode2(AMDGPU::BUFFER_LOAD_DWORDX3_VBUFFER_OFFSET),
      GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/0, // DstI[vdata]
      GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/0, // srsrc
      GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/1, // soffset
      GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/2, // offset
      GIR_AddImm8, /*InsnID*/0, /*Imm*/0,
      GIR_AddImm8, /*InsnID*/0, /*Imm*/0,
      GIR_MergeMemOperands, /*InsnID*/0, /*NumInsns*/1, /*MergeInsnID's*/0,
      GIR_ConstrainSelectedInstOperands, /*InsnID*/0,
      GIR_EraseFromParent, /*InsnID*/0,
      // GIR_Coverage, 5430,
      GIR_Done,
    // Label 1393: @92371
    GIM_Try, /*On fail goto*//*Label 1394*/ GIMT_Encode4(92438), // Rule ID 3544 //
      GIM_CheckFeatures, GIMT_Encode2(GIFBS_EnableFlatScratch_HasFlatScratchInsts_HasFlatScratchSVSMode),
      GIM_CheckMemoryAddressSpace, /*MI*/0, /*MMO*/0, /*NumAddrSpace*/1, /*AddrSpace*/5,
      GIM_CheckAtomicOrdering, /*MI*/0, /*Order*/(uint8_t)AtomicOrdering::NotAtomic,
      GIM_CheckRegBankForClass, /*MI*/0, /*Op*/0, /*RC*/GIMT_Encode2(AMDGPU::AV_96RegClassID),
      GIM_CheckPointerToAny, /*MI*/0, /*Op*/1, /*SizeInBits*/0,
      GIM_CheckComplexPattern, /*MI*/0, /*Op*/1, /*Renderer*/GIMT_Encode2(0), GIMT_Encode2(GICP_gi_flat_scratch_svaddr),
      // (ld:{ *:[v3i32] } (ScratchSVAddr:{ *:[iPTR] } VGPR_32:{ *:[i32] }:$vaddr, SGPR_32:{ *:[i32] }:$saddr, i32:{ *:[i32] }:$offset))<<P:Predicate_unindexedload>><<P:Predicate_load_private>>  =>  (SCRATCH_LOAD_DWORDX3_SVS:{ *:[v3i32] } ?:{ *:[i32] }:$vaddr, ?:{ *:[i32] }:$saddr, ?:{ *:[i32] }:$offset, 0:{ *:[i32] })
      GIR_BuildMI, /*InsnID*/0, /*Opcode*/GIMT_Encode2(AMDGPU::SCRATCH_LOAD_DWORDX3_SVS),
      GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/0, // DstI[vdst]
      GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/0, // vaddr
      GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/1, // saddr
      GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/2, // offset
      GIR_AddImm8, /*InsnID*/0, /*Imm*/0,
      GIR_MergeMemOperands, /*InsnID*/0, /*NumInsns*/1, /*MergeInsnID's*/0,
      GIR_ConstrainSelectedInstOperands, /*InsnID*/0,
      GIR_EraseFromParent, /*InsnID*/0,
      // GIR_Coverage, 3544,
      GIR_Done,
    // Label 1394: @92438
    GIM_Try, /*On fail goto*//*Label 1395*/ GIMT_Encode4(92500), // Rule ID 3543 //
      GIM_CheckFeatures, GIMT_Encode2(GIFBS_EnableFlatScratch_HasFlatScratchInsts),
      GIM_CheckMemoryAddressSpace, /*MI*/0, /*MMO*/0, /*NumAddrSpace*/1, /*AddrSpace*/5,
      GIM_CheckAtomicOrdering, /*MI*/0, /*Order*/(uint8_t)AtomicOrdering::NotAtomic,
      GIM_CheckRegBankForClass, /*MI*/0, /*Op*/0, /*RC*/GIMT_Encode2(AMDGPU::AV_96RegClassID),
      GIM_CheckPointerToAny, /*MI*/0, /*Op*/1, /*SizeInBits*/0,
      GIM_CheckComplexPattern, /*MI*/0, /*Op*/1, /*Renderer*/GIMT_Encode2(0), GIMT_Encode2(GICP_gi_flat_scratch_saddr),
      // (ld:{ *:[v3i32] } (ScratchSAddr:{ *:[iPTR] } SGPR_32:{ *:[i32] }:$saddr, i32:{ *:[i32] }:$offset))<<P:Predicate_unindexedload>><<P:Predicate_load_private>>  =>  (SCRATCH_LOAD_DWORDX3_SADDR:{ *:[v3i32] } ?:{ *:[i32] }:$saddr, ?:{ *:[i32] }:$offset)
      GIR_BuildMI, /*InsnID*/0, /*Opcode*/GIMT_Encode2(AMDGPU::SCRATCH_LOAD_DWORDX3_SADDR),
      GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/0, // DstI[vdst]
      GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/0, // saddr
      GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/1, // offset
      GIR_AddImm8, /*InsnID*/0, /*Imm*/0,
      GIR_MergeMemOperands, /*InsnID*/0, /*NumInsns*/1, /*MergeInsnID's*/0,
      GIR_ConstrainSelectedInstOperands, /*InsnID*/0,
      GIR_EraseFromParent, /*InsnID*/0,
      // GIR_Coverage, 3543,
      GIR_Done,
    // Label 1395: @92500
    GIM_Try, /*On fail goto*//*Label 1396*/ GIMT_Encode4(92562), // Rule ID 3542 //
      GIM_CheckFeatures, GIMT_Encode2(GIFBS_EnableFlatScratch_HasFlatScratchInsts),
      GIM_CheckMemoryAddressSpace, /*MI*/0, /*MMO*/0, /*NumAddrSpace*/1, /*AddrSpace*/5,
      GIM_CheckAtomicOrdering, /*MI*/0, /*Order*/(uint8_t)AtomicOrdering::NotAtomic,
      GIM_CheckRegBankForClass, /*MI*/0, /*Op*/0, /*RC*/GIMT_Encode2(AMDGPU::AV_96RegClassID),
      GIM_CheckPointerToAny, /*MI*/0, /*Op*/1, /*SizeInBits*/0,
      GIM_CheckComplexPattern, /*MI*/0, /*Op*/1, /*Renderer*/GIMT_Encode2(0), GIMT_Encode2(GICP_gi_flat_scratch_offset),
      // (ld:{ *:[v3i32] } (ScratchOffset:{ *:[iPTR] } VGPR_32:{ *:[i32] }:$vaddr, i32:{ *:[i32] }:$offset))<<P:Predicate_unindexedload>><<P:Predicate_load_private>>  =>  (SCRATCH_LOAD_DWORDX3:{ *:[v3i32] } ?:{ *:[i32] }:$vaddr, ?:{ *:[i32] }:$offset)
      GIR_BuildMI, /*InsnID*/0, /*Opcode*/GIMT_Encode2(AMDGPU::SCRATCH_LOAD_DWORDX3),
      GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/0, // DstI[vdst]
      GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/0, // vaddr
      GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/1, // offset
      GIR_AddImm8, /*InsnID*/0, /*Imm*/0,
      GIR_MergeMemOperands, /*InsnID*/0, /*NumInsns*/1, /*MergeInsnID's*/0,
      GIR_ConstrainSelectedInstOperands, /*InsnID*/0,
      GIR_EraseFromParent, /*InsnID*/0,
      // GIR_Coverage, 3542,
      GIR_Done,
    // Label 1396: @92562
    GIM_Try, /*On fail goto*//*Label 1397*/ GIMT_Encode4(92639), // Rule ID 3760 //
      GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasUnrestrictedSOffset),
      GIM_CheckMemoryAddressSpace, /*MI*/0, /*MMO*/0, /*NumAddrSpace*/3, /*AddrSpace*/1, /*AddrSpace*/4, /*AddrSpace*/6,
      GIM_CheckAtomicOrdering, /*MI*/0, /*Order*/(uint8_t)AtomicOrdering::NotAtomic,
      GIM_CheckRegBankForClass, /*MI*/0, /*Op*/0, /*RC*/GIMT_Encode2(AMDGPU::AV_96RegClassID),
      GIM_CheckPointerToAny, /*MI*/0, /*Op*/1, /*SizeInBits*/0,
      GIM_CheckComplexPattern, /*MI*/0, /*Op*/1, /*Renderer*/GIMT_Encode2(0), GIMT_Encode2(GICP_gi_mubuf_addr64),
      // (ld:{ *:[v3i32] } (MUBUFAddr64:{ *:[iPTR] } v4i32:{ *:[v4i32] }:$srsrc, i64:{ *:[i64] }:$vaddr, i32:{ *:[i32] }:$soffset, i32:{ *:[i32] }:$offset))<<P:Predicate_unindexedload>><<P:Predicate_load_global>>  =>  (BUFFER_LOAD_DWORDX3_ADDR64:{ *:[v3i32] } i64:{ *:[i64] }:$vaddr, v4i32:{ *:[v4i32] }:$srsrc, i32:{ *:[i32] }:$soffset, i32:{ *:[i32] }:$offset)
      GIR_BuildMI, /*InsnID*/0, /*Opcode*/GIMT_Encode2(AMDGPU::BUFFER_LOAD_DWORDX3_ADDR64),
      GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/0, // DstI[vdata]
      GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/1, // vaddr
      GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/0, // srsrc
      GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/2, // soffset
      GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/3, // offset
      GIR_AddImm8, /*InsnID*/0, /*Imm*/0,
      GIR_AddImm8, /*InsnID*/0, /*Imm*/0,
      GIR_MergeMemOperands, /*InsnID*/0, /*NumInsns*/1, /*MergeInsnID's*/0,
      GIR_ConstrainSelectedInstOperands, /*InsnID*/0,
      GIR_EraseFromParent, /*InsnID*/0,
      // GIR_Coverage, 3760,
      GIR_Done,
    // Label 1397: @92639
    GIM_Try, /*On fail goto*//*Label 1398*/ GIMT_Encode4(92713), // Rule ID 3762 //
      GIM_CheckMemoryAddressSpace, /*MI*/0, /*MMO*/0, /*NumAddrSpace*/3, /*AddrSpace*/1, /*AddrSpace*/4, /*AddrSpace*/6,
      GIM_CheckAtomicOrdering, /*MI*/0, /*Order*/(uint8_t)AtomicOrdering::NotAtomic,
      GIM_CheckRegBankForClass, /*MI*/0, /*Op*/0, /*RC*/GIMT_Encode2(AMDGPU::AV_96RegClassID),
      GIM_CheckPointerToAny, /*MI*/0, /*Op*/1, /*SizeInBits*/0,
      GIM_CheckComplexPattern, /*MI*/0, /*Op*/1, /*Renderer*/GIMT_Encode2(0), GIMT_Encode2(GICP_gi_mubuf_addr64),
      // (ld:{ *:[v3i32] } (MUBUFAddr64:{ *:[iPTR] } v4i32:{ *:[v4i32] }:$srsrc, i64:{ *:[i64] }:$vaddr, i32:{ *:[i32] }:$soffset, i32:{ *:[i32] }:$offset))<<P:Predicate_unindexedload>><<P:Predicate_load_global>>  =>  (BUFFER_LOAD_DWORDX3_VBUFFER_ADDR64:{ *:[v3i32] } i64:{ *:[i64] }:$vaddr, v4i32:{ *:[v4i32] }:$srsrc, i32:{ *:[i32] }:$soffset, i32:{ *:[i32] }:$offset)
      GIR_BuildMI, /*InsnID*/0, /*Opcode*/GIMT_Encode2(AMDGPU::BUFFER_LOAD_DWORDX3_VBUFFER_ADDR64),
      GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/0, // DstI[vdata]
      GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/1, // vaddr
      GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/0, // srsrc
      GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/2, // soffset
      GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/3, // offset
      GIR_AddImm8, /*InsnID*/0, /*Imm*/0,
      GIR_AddImm8, /*InsnID*/0, /*Imm*/0,
      GIR_MergeMemOperands, /*InsnID*/0, /*NumInsns*/1, /*MergeInsnID's*/0,
      GIR_ConstrainSelectedInstOperands, /*InsnID*/0,
      GIR_EraseFromParent, /*InsnID*/0,
      // GIR_Coverage, 3762,
      GIR_Done,
    // Label 1398: @92713
    GIM_Try, /*On fail goto*//*Label 1399*/ GIMT_Encode4(92790), // Rule ID 3764 //
      GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasUnrestrictedSOffset),
      GIM_CheckMemoryAddressSpace, /*MI*/0, /*MMO*/0, /*NumAddrSpace*/3, /*AddrSpace*/1, /*AddrSpace*/4, /*AddrSpace*/6,
      GIM_CheckAtomicOrdering, /*MI*/0, /*Order*/(uint8_t)AtomicOrdering::NotAtomic,
      GIM_CheckRegBankForClass, /*MI*/0, /*Op*/0, /*RC*/GIMT_Encode2(AMDGPU::AV_96RegClassID),
      GIM_CheckPointerToAny, /*MI*/0, /*Op*/1, /*SizeInBits*/0,
      GIM_CheckComplexPattern, /*MI*/0, /*Op*/1, /*Renderer*/GIMT_Encode2(0), GIMT_Encode2(GICP_gi_mubuf_addr64),
      // (ld:{ *:[v3f32] } (MUBUFAddr64:{ *:[iPTR] } v4i32:{ *:[v4i32] }:$srsrc, i64:{ *:[i64] }:$vaddr, i32:{ *:[i32] }:$soffset, i32:{ *:[i32] }:$offset))<<P:Predicate_unindexedload>><<P:Predicate_load_global>>  =>  (BUFFER_LOAD_DWORDX3_ADDR64:{ *:[v3f32] } i64:{ *:[i64] }:$vaddr, v4i32:{ *:[v4i32] }:$srsrc, i32:{ *:[i32] }:$soffset, i32:{ *:[i32] }:$offset)
      GIR_BuildMI, /*InsnID*/0, /*Opcode*/GIMT_Encode2(AMDGPU::BUFFER_LOAD_DWORDX3_ADDR64),
      GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/0, // DstI[vdata]
      GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/1, // vaddr
      GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/0, // srsrc
      GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/2, // soffset
      GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/3, // offset
      GIR_AddImm8, /*InsnID*/0, /*Imm*/0,
      GIR_AddImm8, /*InsnID*/0, /*Imm*/0,
      GIR_MergeMemOperands, /*InsnID*/0, /*NumInsns*/1, /*MergeInsnID's*/0,
      GIR_ConstrainSelectedInstOperands, /*InsnID*/0,
      GIR_EraseFromParent, /*InsnID*/0,
      // GIR_Coverage, 3764,
      GIR_Done,
    // Label 1399: @92790
    GIM_Try, /*On fail goto*//*Label 1400*/ GIMT_Encode4(92864), // Rule ID 3766 //
      GIM_CheckMemoryAddressSpace, /*MI*/0, /*MMO*/0, /*NumAddrSpace*/3, /*AddrSpace*/1, /*AddrSpace*/4, /*AddrSpace*/6,
      GIM_CheckAtomicOrdering, /*MI*/0, /*Order*/(uint8_t)AtomicOrdering::NotAtomic,
      GIM_CheckRegBankForClass, /*MI*/0, /*Op*/0, /*RC*/GIMT_Encode2(AMDGPU::AV_96RegClassID),
      GIM_CheckPointerToAny, /*MI*/0, /*Op*/1, /*SizeInBits*/0,
      GIM_CheckComplexPattern, /*MI*/0, /*Op*/1, /*Renderer*/GIMT_Encode2(0), GIMT_Encode2(GICP_gi_mubuf_addr64),
      // (ld:{ *:[v3f32] } (MUBUFAddr64:{ *:[iPTR] } v4i32:{ *:[v4i32] }:$srsrc, i64:{ *:[i64] }:$vaddr, i32:{ *:[i32] }:$soffset, i32:{ *:[i32] }:$offset))<<P:Predicate_unindexedload>><<P:Predicate_load_global>>  =>  (BUFFER_LOAD_DWORDX3_VBUFFER_ADDR64:{ *:[v3f32] } i64:{ *:[i64] }:$vaddr, v4i32:{ *:[v4i32] }:$srsrc, i32:{ *:[i32] }:$soffset, i32:{ *:[i32] }:$offset)
      GIR_BuildMI, /*InsnID*/0, /*Opcode*/GIMT_Encode2(AMDGPU::BUFFER_LOAD_DWORDX3_VBUFFER_ADDR64),
      GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/0, // DstI[vdata]
      GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/1, // vaddr
      GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/0, // srsrc
      GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/2, // soffset
      GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/3, // offset
      GIR_AddImm8, /*InsnID*/0, /*Imm*/0,
      GIR_AddImm8, /*InsnID*/0, /*Imm*/0,
      GIR_MergeMemOperands, /*InsnID*/0, /*NumInsns*/1, /*MergeInsnID's*/0,
      GIR_ConstrainSelectedInstOperands, /*InsnID*/0,
      GIR_EraseFromParent, /*InsnID*/0,
      // GIR_Coverage, 3766,
      GIR_Done,
    // Label 1400: @92864
    GIM_Try, /*On fail goto*//*Label 1401*/ GIMT_Encode4(92939), // Rule ID 5427 //
      GIM_CheckFeatures, GIMT_Encode2(GIFBS_DisableFlatScratch_HasUnrestrictedSOffset),
      GIM_CheckMemoryAddressSpace, /*MI*/0, /*MMO*/0, /*NumAddrSpace*/1, /*AddrSpace*/5,
      GIM_CheckAtomicOrdering, /*MI*/0, /*Order*/(uint8_t)AtomicOrdering::NotAtomic,
      GIM_CheckRegBankForClass, /*MI*/0, /*Op*/0, /*RC*/GIMT_Encode2(AMDGPU::AV_96RegClassID),
      GIM_CheckPointerToAny, /*MI*/0, /*Op*/1, /*SizeInBits*/0,
      GIM_CheckComplexPattern, /*MI*/0, /*Op*/1, /*Renderer*/GIMT_Encode2(0), GIMT_Encode2(GICP_gi_mubuf_scratch_offen),
      // (ld:{ *:[v3i32] } (MUBUFScratchOffen:{ *:[iPTR] } v4i32:{ *:[v4i32] }:$srsrc, i32:{ *:[i32] }:$vaddr, i32:{ *:[i32] }:$soffset, i32:{ *:[i32] }:$offset))<<P:Predicate_unindexedload>><<P:Predicate_load_private>>  =>  (BUFFER_LOAD_DWORDX3_OFFEN:{ *:[v3i32] } ?:{ *:[i32] }:$vaddr, ?:{ *:[v4i32] }:$srsrc, ?:{ *:[i32] }:$soffset, ?:{ *:[i32] }:$offset, 0:{ *:[i32] }, 0:{ *:[i1] })
      GIR_BuildMI, /*InsnID*/0, /*Opcode*/GIMT_Encode2(AMDGPU::BUFFER_LOAD_DWORDX3_OFFEN),
      GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/0, // DstI[vdata]
      GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/1, // vaddr
      GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/0, // srsrc
      GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/2, // soffset
      GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/3, // offset
      GIR_AddImm8, /*InsnID*/0, /*Imm*/0,
      GIR_AddImm8, /*InsnID*/0, /*Imm*/0,
      GIR_MergeMemOperands, /*InsnID*/0, /*NumInsns*/1, /*MergeInsnID's*/0,
      GIR_ConstrainSelectedInstOperands, /*InsnID*/0,
      GIR_EraseFromParent, /*InsnID*/0,
      // GIR_Coverage, 5427,
      GIR_Done,
    // Label 1401: @92939
    GIM_Try, /*On fail goto*//*Label 1402*/ GIMT_Encode4(93014), // Rule ID 5429 //
      GIM_CheckFeatures, GIMT_Encode2(GIFBS_DisableFlatScratch),
      GIM_CheckMemoryAddressSpace, /*MI*/0, /*MMO*/0, /*NumAddrSpace*/1, /*AddrSpace*/5,
      GIM_CheckAtomicOrdering, /*MI*/0, /*Order*/(uint8_t)AtomicOrdering::NotAtomic,
      GIM_CheckRegBankForClass, /*MI*/0, /*Op*/0, /*RC*/GIMT_Encode2(AMDGPU::AV_96RegClassID),
      GIM_CheckPointerToAny, /*MI*/0, /*Op*/1, /*SizeInBits*/0,
      GIM_CheckComplexPattern, /*MI*/0, /*Op*/1, /*Renderer*/GIMT_Encode2(0), GIMT_Encode2(GICP_gi_mubuf_scratch_offen),
      // (ld:{ *:[v3i32] } (MUBUFScratchOffen:{ *:[iPTR] } v4i32:{ *:[v4i32] }:$srsrc, i32:{ *:[i32] }:$vaddr, i32:{ *:[i32] }:$soffset, i32:{ *:[i32] }:$offset))<<P:Predicate_unindexedload>><<P:Predicate_load_private>>  =>  (BUFFER_LOAD_DWORDX3_VBUFFER_OFFEN:{ *:[v3i32] } ?:{ *:[i32] }:$vaddr, ?:{ *:[v4i32] }:$srsrc, ?:{ *:[i32] }:$soffset, ?:{ *:[i32] }:$offset, 0:{ *:[i32] }, 0:{ *:[i1] })
      GIR_BuildMI, /*InsnID*/0, /*Opcode*/GIMT_Encode2(AMDGPU::BUFFER_LOAD_DWORDX3_VBUFFER_OFFEN),
      GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/0, // DstI[vdata]
      GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/1, // vaddr
      GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/0, // srsrc
      GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/2, // soffset
      GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/3, // offset
      GIR_AddImm8, /*InsnID*/0, /*Imm*/0,
      GIR_AddImm8, /*InsnID*/0, /*Imm*/0,
      GIR_MergeMemOperands, /*InsnID*/0, /*NumInsns*/1, /*MergeInsnID's*/0,
      GIR_ConstrainSelectedInstOperands, /*InsnID*/0,
      GIR_EraseFromParent, /*InsnID*/0,
      // GIR_Coverage, 5429,
      GIR_Done,
    // Label 1402: @93014
    GIM_Try, /*On fail goto*//*Label 1403*/ GIMT_Encode4(93086), // Rule ID 3759 //
      GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasUnrestrictedSOffset),
      GIM_CheckMemoryAddressSpace, /*MI*/0, /*MMO*/0, /*NumAddrSpace*/3, /*AddrSpace*/1, /*AddrSpace*/4, /*AddrSpace*/6,
      GIM_CheckAtomicOrdering, /*MI*/0, /*Order*/(uint8_t)AtomicOrdering::NotAtomic,
      GIM_CheckRegBankForClass, /*MI*/0, /*Op*/0, /*RC*/GIMT_Encode2(AMDGPU::AV_96RegClassID),
      GIM_CheckPointerToAny, /*MI*/0, /*Op*/1, /*SizeInBits*/0,
      GIM_CheckComplexPattern, /*MI*/0, /*Op*/1, /*Renderer*/GIMT_Encode2(0), GIMT_Encode2(GICP_gi_mubuf_offset),
      // (ld:{ *:[v3i32] } (MUBUFOffset:{ *:[iPTR] } v4i32:{ *:[v4i32] }:$srsrc, i32:{ *:[i32] }:$soffset, i32:{ *:[i32] }:$offset))<<P:Predicate_unindexedload>><<P:Predicate_load_global>>  =>  (BUFFER_LOAD_DWORDX3_OFFSET:{ *:[v3i32] } v4i32:{ *:[v4i32] }:$srsrc, i32:{ *:[i32] }:$soffset, i32:{ *:[i32] }:$offset)
      GIR_BuildMI, /*InsnID*/0, /*Opcode*/GIMT_Encode2(AMDGPU::BUFFER_LOAD_DWORDX3_OFFSET),
      GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/0, // DstI[vdata]
      GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/0, // srsrc
      GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/1, // soffset
      GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/2, // offset
      GIR_AddImm8, /*InsnID*/0, /*Imm*/0,
      GIR_AddImm8, /*InsnID*/0, /*Imm*/0,
      GIR_MergeMemOperands, /*InsnID*/0, /*NumInsns*/1, /*MergeInsnID's*/0,
      GIR_ConstrainSelectedInstOperands, /*InsnID*/0,
      GIR_EraseFromParent, /*InsnID*/0,
      // GIR_Coverage, 3759,
      GIR_Done,
    // Label 1403: @93086
    GIM_Try, /*On fail goto*//*Label 1404*/ GIMT_Encode4(93155), // Rule ID 3761 //
      GIM_CheckMemoryAddressSpace, /*MI*/0, /*MMO*/0, /*NumAddrSpace*/3, /*AddrSpace*/1, /*AddrSpace*/4, /*AddrSpace*/6,
      GIM_CheckAtomicOrdering, /*MI*/0, /*Order*/(uint8_t)AtomicOrdering::NotAtomic,
      GIM_CheckRegBankForClass, /*MI*/0, /*Op*/0, /*RC*/GIMT_Encode2(AMDGPU::AV_96RegClassID),
      GIM_CheckPointerToAny, /*MI*/0, /*Op*/1, /*SizeInBits*/0,
      GIM_CheckComplexPattern, /*MI*/0, /*Op*/1, /*Renderer*/GIMT_Encode2(0), GIMT_Encode2(GICP_gi_mubuf_offset),
      // (ld:{ *:[v3i32] } (MUBUFOffset:{ *:[iPTR] } v4i32:{ *:[v4i32] }:$srsrc, i32:{ *:[i32] }:$soffset, i32:{ *:[i32] }:$offset))<<P:Predicate_unindexedload>><<P:Predicate_load_global>>  =>  (BUFFER_LOAD_DWORDX3_VBUFFER_OFFSET:{ *:[v3i32] } v4i32:{ *:[v4i32] }:$srsrc, i32:{ *:[i32] }:$soffset, i32:{ *:[i32] }:$offset)
      GIR_BuildMI, /*InsnID*/0, /*Opcode*/GIMT_Encode2(AMDGPU::BUFFER_LOAD_DWORDX3_VBUFFER_OFFSET),
      GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/0, // DstI[vdata]
      GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/0, // srsrc
      GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/1, // soffset
      GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/2, // offset
      GIR_AddImm8, /*InsnID*/0, /*Imm*/0,
      GIR_AddImm8, /*InsnID*/0, /*Imm*/0,
      GIR_MergeMemOperands, /*InsnID*/0, /*NumInsns*/1, /*MergeInsnID's*/0,
      GIR_ConstrainSelectedInstOperands, /*InsnID*/0,
      GIR_EraseFromParent, /*InsnID*/0,
      // GIR_Coverage, 3761,
      GIR_Done,
    // Label 1404: @93155
    GIM_Try, /*On fail goto*//*Label 1405*/ GIMT_Encode4(93227), // Rule ID 3763 //
      GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasUnrestrictedSOffset),
      GIM_CheckMemoryAddressSpace, /*MI*/0, /*MMO*/0, /*NumAddrSpace*/3, /*AddrSpace*/1, /*AddrSpace*/4, /*AddrSpace*/6,
      GIM_CheckAtomicOrdering, /*MI*/0, /*Order*/(uint8_t)AtomicOrdering::NotAtomic,
      GIM_CheckRegBankForClass, /*MI*/0, /*Op*/0, /*RC*/GIMT_Encode2(AMDGPU::AV_96RegClassID),
      GIM_CheckPointerToAny, /*MI*/0, /*Op*/1, /*SizeInBits*/0,
      GIM_CheckComplexPattern, /*MI*/0, /*Op*/1, /*Renderer*/GIMT_Encode2(0), GIMT_Encode2(GICP_gi_mubuf_offset),
      // (ld:{ *:[v3f32] } (MUBUFOffset:{ *:[iPTR] } v4i32:{ *:[v4i32] }:$srsrc, i32:{ *:[i32] }:$soffset, i32:{ *:[i32] }:$offset))<<P:Predicate_unindexedload>><<P:Predicate_load_global>>  =>  (BUFFER_LOAD_DWORDX3_OFFSET:{ *:[v3f32] } v4i32:{ *:[v4i32] }:$srsrc, i32:{ *:[i32] }:$soffset, i32:{ *:[i32] }:$offset)
      GIR_BuildMI, /*InsnID*/0, /*Opcode*/GIMT_Encode2(AMDGPU::BUFFER_LOAD_DWORDX3_OFFSET),
      GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/0, // DstI[vdata]
      GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/0, // srsrc
      GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/1, // soffset
      GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/2, // offset
      GIR_AddImm8, /*InsnID*/0, /*Imm*/0,
      GIR_AddImm8, /*InsnID*/0, /*Imm*/0,
      GIR_MergeMemOperands, /*InsnID*/0, /*NumInsns*/1, /*MergeInsnID's*/0,
      GIR_ConstrainSelectedInstOperands, /*InsnID*/0,
      GIR_EraseFromParent, /*InsnID*/0,
      // GIR_Coverage, 3763,
      GIR_Done,
    // Label 1405: @93227
    GIM_Try, /*On fail goto*//*Label 1406*/ GIMT_Encode4(93296), // Rule ID 3765 //
      GIM_CheckMemoryAddressSpace, /*MI*/0, /*MMO*/0, /*NumAddrSpace*/3, /*AddrSpace*/1, /*AddrSpace*/4, /*AddrSpace*/6,
      GIM_CheckAtomicOrdering, /*MI*/0, /*Order*/(uint8_t)AtomicOrdering::NotAtomic,
      GIM_CheckRegBankForClass, /*MI*/0, /*Op*/0, /*RC*/GIMT_Encode2(AMDGPU::AV_96RegClassID),
      GIM_CheckPointerToAny, /*MI*/0, /*Op*/1, /*SizeInBits*/0,
      GIM_CheckComplexPattern, /*MI*/0, /*Op*/1, /*Renderer*/GIMT_Encode2(0), GIMT_Encode2(GICP_gi_mubuf_offset),
      // (ld:{ *:[v3f32] } (MUBUFOffset:{ *:[iPTR] } v4i32:{ *:[v4i32] }:$srsrc, i32:{ *:[i32] }:$soffset, i32:{ *:[i32] }:$offset))<<P:Predicate_unindexedload>><<P:Predicate_load_global>>  =>  (BUFFER_LOAD_DWORDX3_VBUFFER_OFFSET:{ *:[v3f32] } v4i32:{ *:[v4i32] }:$srsrc, i32:{ *:[i32] }:$soffset, i32:{ *:[i32] }:$offset)
      GIR_BuildMI, /*InsnID*/0, /*Opcode*/GIMT_Encode2(AMDGPU::BUFFER_LOAD_DWORDX3_VBUFFER_OFFSET),
      GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/0, // DstI[vdata]
      GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/0, // srsrc
      GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/1, // soffset
      GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/2, // offset
      GIR_AddImm8, /*InsnID*/0, /*Imm*/0,
      GIR_AddImm8, /*InsnID*/0, /*Imm*/0,
      GIR_MergeMemOperands, /*InsnID*/0, /*NumInsns*/1, /*MergeInsnID's*/0,
      GIR_ConstrainSelectedInstOperands, /*InsnID*/0,
      GIR_EraseFromParent, /*InsnID*/0,
      // GIR_Coverage, 3765,
      GIR_Done,
    // Label 1406: @93296
    GIM_Try, /*On fail goto*//*Label 1407*/ GIMT_Encode4(93365), // Rule ID 3069 //
      GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasFlatGlobalInsts),
      GIM_CheckMemoryAddressSpace, /*MI*/0, /*MMO*/0, /*NumAddrSpace*/3, /*AddrSpace*/1, /*AddrSpace*/4, /*AddrSpace*/6,
      GIM_CheckAtomicOrdering, /*MI*/0, /*Order*/(uint8_t)AtomicOrdering::NotAtomic,
      GIM_CheckRegBankForClass, /*MI*/0, /*Op*/0, /*RC*/GIMT_Encode2(AMDGPU::AV_96RegClassID),
      GIM_CheckPointerToAny, /*MI*/0, /*Op*/1, /*SizeInBits*/0,
      GIM_CheckComplexPattern, /*MI*/0, /*Op*/1, /*Renderer*/GIMT_Encode2(0), GIMT_Encode2(GICP_gi_global_saddr),
      // (ld:{ *:[v3i32] } (GlobalSAddr:{ *:[iPTR] } SReg_64:{ *:[i64] }:$saddr, VGPR_32:{ *:[i32] }:$voffset, i32:{ *:[i32] }:$offset))<<P:Predicate_unindexedload>><<P:Predicate_load_global>>  =>  (GLOBAL_LOAD_DWORDX3_SADDR:{ *:[v3i32] } ?:{ *:[i64] }:$saddr, ?:{ *:[i32] }:$voffset, ?:{ *:[i32] }:$offset, 0:{ *:[i32] })
      GIR_BuildMI, /*InsnID*/0, /*Opcode*/GIMT_Encode2(AMDGPU::GLOBAL_LOAD_DWORDX3_SADDR),
      GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/0, // DstI[vdst]
      GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/0, // saddr
      GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/1, // voffset
      GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/2, // offset
      GIR_AddImm8, /*InsnID*/0, /*Imm*/0,
      GIR_MergeMemOperands, /*InsnID*/0, /*NumInsns*/1, /*MergeInsnID's*/0,
      GIR_ConstrainSelectedInstOperands, /*InsnID*/0,
      GIR_EraseFromParent, /*InsnID*/0,
      // GIR_Coverage, 3069,
      GIR_Done,
    // Label 1407: @93365
    GIM_Try, /*On fail goto*//*Label 1408*/ GIMT_Encode4(93429), // Rule ID 3068 //
      GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasFlatGlobalInsts),
      GIM_CheckMemoryAddressSpace, /*MI*/0, /*MMO*/0, /*NumAddrSpace*/3, /*AddrSpace*/1, /*AddrSpace*/4, /*AddrSpace*/6,
      GIM_CheckAtomicOrdering, /*MI*/0, /*Order*/(uint8_t)AtomicOrdering::NotAtomic,
      GIM_CheckRegBankForClass, /*MI*/0, /*Op*/0, /*RC*/GIMT_Encode2(AMDGPU::AV_96RegClassID),
      GIM_CheckPointerToAny, /*MI*/0, /*Op*/1, /*SizeInBits*/0,
      GIM_CheckComplexPattern, /*MI*/0, /*Op*/1, /*Renderer*/GIMT_Encode2(0), GIMT_Encode2(GICP_gi_global_offset),
      // (ld:{ *:[v3i32] } (GlobalOffset:{ *:[iPTR] } VReg_64:{ *:[i64] }:$vaddr, i32:{ *:[i32] }:$offset))<<P:Predicate_unindexedload>><<P:Predicate_load_global>>  =>  (GLOBAL_LOAD_DWORDX3:{ *:[v3i32] } ?:{ *:[i64] }:$vaddr, ?:{ *:[i32] }:$offset)
      GIR_BuildMI, /*InsnID*/0, /*Opcode*/GIMT_Encode2(AMDGPU::GLOBAL_LOAD_DWORDX3),
      GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/0, // DstI[vdst]
      GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/0, // vaddr
      GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/1, // offset
      GIR_AddImm8, /*InsnID*/0, /*Imm*/0,
      GIR_MergeMemOperands, /*InsnID*/0, /*NumInsns*/1, /*MergeInsnID's*/0,
      GIR_ConstrainSelectedInstOperands, /*InsnID*/0,
      GIR_EraseFromParent, /*InsnID*/0,
      // GIR_Coverage, 3068,
      GIR_Done,
    // Label 1408: @93429
    GIM_Try, /*On fail goto*//*Label 1409*/ GIMT_Encode4(93494), // Rule ID 2765 //
      GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasFlatAddressSpace),
      GIM_CheckMemoryAddressSpace, /*MI*/0, /*MMO*/0, /*NumAddrSpace*/4, /*AddrSpace*/0, /*AddrSpace*/1, /*AddrSpace*/4, /*AddrSpace*/6,
      GIM_CheckAtomicOrdering, /*MI*/0, /*Order*/(uint8_t)AtomicOrdering::NotAtomic,
      GIM_CheckRegBankForClass, /*MI*/0, /*Op*/0, /*RC*/GIMT_Encode2(AMDGPU::AV_96RegClassID),
      GIM_CheckPointerToAny, /*MI*/0, /*Op*/1, /*SizeInBits*/0,
      GIM_CheckComplexPattern, /*MI*/0, /*Op*/1, /*Renderer*/GIMT_Encode2(0), GIMT_Encode2(GICP_gi_flat_offset),
      // (ld:{ *:[v3i32] } (FlatOffset:{ *:[iPTR] } i64:{ *:[i64] }:$vaddr, i32:{ *:[i32] }:$offset))<<P:Predicate_unindexedload>><<P:Predicate_load_flat>>  =>  (FLAT_LOAD_DWORDX3:{ *:[v3i32] } ?:{ *:[i64] }:$vaddr, ?:{ *:[i32] }:$offset)
      GIR_BuildMI, /*InsnID*/0, /*Opcode*/GIMT_Encode2(AMDGPU::FLAT_LOAD_DWORDX3),
      GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/0, // DstI[vdst]
      GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/0, // vaddr
      GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/1, // offset
      GIR_AddImm8, /*InsnID*/0, /*Imm*/0,
      GIR_MergeMemOperands, /*InsnID*/0, /*NumInsns*/1, /*MergeInsnID's*/0,
      GIR_ConstrainSelectedInstOperands, /*InsnID*/0,
      GIR_EraseFromParent, /*InsnID*/0,
      // GIR_Coverage, 2765,
      GIR_Done,
    // Label 1409: @93494
    GIM_Reject,
    // Label 831: @93495
    GIM_Try, /*On fail goto*//*Label 1410*/ GIMT_Encode4(93565), // Rule ID 2534 //
      GIM_CheckFeatures, GIMT_Encode2(GIFBS_isGFX9Plus),
      GIM_CheckMemorySizeEqualToLLT, /*MI*/0, /*MMO*/0, /*OpIdx*/0,
      GIM_CheckAtomicOrdering, /*MI*/0, /*Order*/(uint8_t)AtomicOrdering::NotAtomic,
      GIM_CheckRegBankForClass, /*MI*/0, /*Op*/0, /*RC*/GIMT_Encode2(AMDGPU::SReg_64_XEXECRegClassID),
      GIM_CheckPointerToAny, /*MI*/0, /*Op*/1, /*SizeInBits*/0,
      GIM_CheckCxxInsnPredicate, /*MI*/0, /*FnId*/GIMT_Encode2(GICXXPred_MI_Predicate_smrd_load),
      GIM_CheckComplexPattern, /*MI*/0, /*Op*/1, /*Renderer*/GIMT_Encode2(0), GIMT_Encode2(GICP_gi_smrd_sgpr_imm),
      // (ld:{ *:[v4i16] } (SMRDSgprImm:{ *:[iPTR] } i64:{ *:[i64] }:$sbase, i32:{ *:[i32] }:$soffset, i32:{ *:[i32] }:$offset))<<P:Predicate_unindexedload>><<P:Predicate_load>><<P:Predicate_smrd_load>>  =>  (S_LOAD_DWORDX2_SGPR_IMM:{ *:[v4i16] } ?:{ *:[i64] }:$sbase, ?:{ *:[i32] }:$soffset, ?:{ *:[i32] }:$offset, 0:{ *:[i32] })
      GIR_BuildMI, /*InsnID*/0, /*Opcode*/GIMT_Encode2(AMDGPU::S_LOAD_DWORDX2_SGPR_IMM),
      GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/0, // DstI[sdst]
      GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/0, // sbase
      GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/1, // soffset
      GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/2, // offset
      GIR_AddImm8, /*InsnID*/0, /*Imm*/0,
      GIR_MergeMemOperands, /*InsnID*/0, /*NumInsns*/1, /*MergeInsnID's*/0,
      GIR_ConstrainSelectedInstOperands, /*InsnID*/0,
      GIR_EraseFromParent, /*InsnID*/0,
      // GIR_Coverage, 2534,
      GIR_Done,
    // Label 1410: @93565
    GIM_Try, /*On fail goto*//*Label 1411*/ GIMT_Encode4(93635), // Rule ID 2540 //
      GIM_CheckFeatures, GIMT_Encode2(GIFBS_isGFX9Plus),
      GIM_CheckMemorySizeEqualToLLT, /*MI*/0, /*MMO*/0, /*OpIdx*/0,
      GIM_CheckAtomicOrdering, /*MI*/0, /*Order*/(uint8_t)AtomicOrdering::NotAtomic,
      GIM_CheckRegBankForClass, /*MI*/0, /*Op*/0, /*RC*/GIMT_Encode2(AMDGPU::SReg_64_XEXECRegClassID),
      GIM_CheckPointerToAny, /*MI*/0, /*Op*/1, /*SizeInBits*/0,
      GIM_CheckCxxInsnPredicate, /*MI*/0, /*FnId*/GIMT_Encode2(GICXXPred_MI_Predicate_smrd_load),
      GIM_CheckComplexPattern, /*MI*/0, /*Op*/1, /*Renderer*/GIMT_Encode2(0), GIMT_Encode2(GICP_gi_smrd_sgpr_imm),
      // (ld:{ *:[v4f16] } (SMRDSgprImm:{ *:[iPTR] } i64:{ *:[i64] }:$sbase, i32:{ *:[i32] }:$soffset, i32:{ *:[i32] }:$offset))<<P:Predicate_unindexedload>><<P:Predicate_load>><<P:Predicate_smrd_load>>  =>  (S_LOAD_DWORDX2_SGPR_IMM:{ *:[v4f16] } ?:{ *:[i64] }:$sbase, ?:{ *:[i32] }:$soffset, ?:{ *:[i32] }:$offset, 0:{ *:[i32] })
      GIR_BuildMI, /*InsnID*/0, /*Opcode*/GIMT_Encode2(AMDGPU::S_LOAD_DWORDX2_SGPR_IMM),
      GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/0, // DstI[sdst]
      GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/0, // sbase
      GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/1, // soffset
      GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/2, // offset
      GIR_AddImm8, /*InsnID*/0, /*Imm*/0,
      GIR_MergeMemOperands, /*InsnID*/0, /*NumInsns*/1, /*MergeInsnID's*/0,
      GIR_ConstrainSelectedInstOperands, /*InsnID*/0,
      GIR_EraseFromParent, /*InsnID*/0,
      // GIR_Coverage, 2540,
      GIR_Done,
    // Label 1411: @93635
    GIM_Try, /*On fail goto*//*Label 1412*/ GIMT_Encode4(93705), // Rule ID 2546 //
      GIM_CheckFeatures, GIMT_Encode2(GIFBS_isGFX9Plus),
      GIM_CheckMemorySizeEqualToLLT, /*MI*/0, /*MMO*/0, /*OpIdx*/0,
      GIM_CheckAtomicOrdering, /*MI*/0, /*Order*/(uint8_t)AtomicOrdering::NotAtomic,
      GIM_CheckRegBankForClass, /*MI*/0, /*Op*/0, /*RC*/GIMT_Encode2(AMDGPU::SReg_64_XEXECRegClassID),
      GIM_CheckPointerToAny, /*MI*/0, /*Op*/1, /*SizeInBits*/0,
      GIM_CheckCxxInsnPredicate, /*MI*/0, /*FnId*/GIMT_Encode2(GICXXPred_MI_Predicate_smrd_load),
      GIM_CheckComplexPattern, /*MI*/0, /*Op*/1, /*Renderer*/GIMT_Encode2(0), GIMT_Encode2(GICP_gi_smrd_sgpr_imm),
      // (ld:{ *:[v4bf16] } (SMRDSgprImm:{ *:[iPTR] } i64:{ *:[i64] }:$sbase, i32:{ *:[i32] }:$soffset, i32:{ *:[i32] }:$offset))<<P:Predicate_unindexedload>><<P:Predicate_load>><<P:Predicate_smrd_load>>  =>  (S_LOAD_DWORDX2_SGPR_IMM:{ *:[v4bf16] } ?:{ *:[i64] }:$sbase, ?:{ *:[i32] }:$soffset, ?:{ *:[i32] }:$offset, 0:{ *:[i32] })
      GIR_BuildMI, /*InsnID*/0, /*Opcode*/GIMT_Encode2(AMDGPU::S_LOAD_DWORDX2_SGPR_IMM),
      GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/0, // DstI[sdst]
      GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/0, // sbase
      GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/1, // soffset
      GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/2, // offset
      GIR_AddImm8, /*InsnID*/0, /*Imm*/0,
      GIR_MergeMemOperands, /*InsnID*/0, /*NumInsns*/1, /*MergeInsnID's*/0,
      GIR_ConstrainSelectedInstOperands, /*InsnID*/0,
      GIR_EraseFromParent, /*InsnID*/0,
      // GIR_Coverage, 2546,
      GIR_Done,
    // Label 1412: @93705
    GIM_Try, /*On fail goto*//*Label 1413*/ GIMT_Encode4(93780), // Rule ID 6831 //
      GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasUnalignedAccessMode_LDSRequiresM0Init),
      GIM_CheckMemorySizeEqualToLLT, /*MI*/0, /*MMO*/0, /*OpIdx*/0,
      GIM_CheckMemoryAddressSpace, /*MI*/0, /*MMO*/0, /*NumAddrSpace*/1, /*AddrSpace*/3,
      GIM_CheckMemoryAddressSpace, /*MI*/0, /*MMO*/0, /*NumAddrSpace*/1, /*AddrSpace*/3,
      GIM_CheckAtomicOrdering, /*MI*/0, /*Order*/(uint8_t)AtomicOrdering::NotAtomic,
      GIM_CheckRegBankForClass, /*MI*/0, /*Op*/0, /*RC*/GIMT_Encode2(AMDGPU::AV_64RegClassID),
      GIM_CheckPointerToAny, /*MI*/0, /*Op*/1, /*SizeInBits*/0,
      GIM_CheckCxxInsnPredicate, /*MI*/0, /*FnId*/GIMT_Encode2(GICXXPred_MI_Predicate_load_align_less_than_4_local_m0),
      GIM_CheckComplexPattern, /*MI*/0, /*Op*/1, /*Renderer*/GIMT_Encode2(0), GIMT_Encode2(GICP_gi_ds_1addr_1offset),
      // (AMDGPUld_glue:{ *:[v4f16] } (DS1Addr1Offset:{ *:[iPTR] } i32:{ *:[i32] }:$ptr, i32:{ *:[i32] }:$offset))<<P:Predicate_unindexedload_glue>><<P:Predicate_load_glue>><<P:Predicate_load_local_m0>><<P:Predicate_load_align_less_than_4_local_m0>>  =>  (DS_READ_B64:{ *:[v4f16] } ?:{ *:[i32] }:$ptr, offset:{ *:[i32] }:$offset, 0:{ *:[i1] })
      GIR_BuildMI, /*InsnID*/0, /*Opcode*/GIMT_Encode2(AMDGPU::DS_READ_B64),
      GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/0, // DstI[vdst]
      GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/0, // ptr
      GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/1, // offset
      GIR_AddImm8, /*InsnID*/0, /*Imm*/0,
      GIR_MergeMemOperands, /*InsnID*/0, /*NumInsns*/1, /*MergeInsnID's*/0,
      GIR_ConstrainSelectedInstOperands, /*InsnID*/0,
      GIR_EraseFromParent, /*InsnID*/0,
      // GIR_Coverage, 6831,
      GIR_Done,
    // Label 1413: @93780
    GIM_Try, /*On fail goto*//*Label 1414*/ GIMT_Encode4(93855), // Rule ID 6835 //
      GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasUnalignedAccessMode_LDSRequiresM0Init),
      GIM_CheckMemorySizeEqualToLLT, /*MI*/0, /*MMO*/0, /*OpIdx*/0,
      GIM_CheckMemoryAddressSpace, /*MI*/0, /*MMO*/0, /*NumAddrSpace*/1, /*AddrSpace*/3,
      GIM_CheckMemoryAddressSpace, /*MI*/0, /*MMO*/0, /*NumAddrSpace*/1, /*AddrSpace*/3,
      GIM_CheckAtomicOrdering, /*MI*/0, /*Order*/(uint8_t)AtomicOrdering::NotAtomic,
      GIM_CheckRegBankForClass, /*MI*/0, /*Op*/0, /*RC*/GIMT_Encode2(AMDGPU::AV_64RegClassID),
      GIM_CheckPointerToAny, /*MI*/0, /*Op*/1, /*SizeInBits*/0,
      GIM_CheckCxxInsnPredicate, /*MI*/0, /*FnId*/GIMT_Encode2(GICXXPred_MI_Predicate_load_align_less_than_4_local_m0),
      GIM_CheckComplexPattern, /*MI*/0, /*Op*/1, /*Renderer*/GIMT_Encode2(0), GIMT_Encode2(GICP_gi_ds_1addr_1offset),
      // (AMDGPUld_glue:{ *:[v4bf16] } (DS1Addr1Offset:{ *:[iPTR] } i32:{ *:[i32] }:$ptr, i32:{ *:[i32] }:$offset))<<P:Predicate_unindexedload_glue>><<P:Predicate_load_glue>><<P:Predicate_load_local_m0>><<P:Predicate_load_align_less_than_4_local_m0>>  =>  (DS_READ_B64:{ *:[v4bf16] } ?:{ *:[i32] }:$ptr, offset:{ *:[i32] }:$offset, 0:{ *:[i1] })
      GIR_BuildMI, /*InsnID*/0, /*Opcode*/GIMT_Encode2(AMDGPU::DS_READ_B64),
      GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/0, // DstI[vdst]
      GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/0, // ptr
      GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/1, // offset
      GIR_AddImm8, /*InsnID*/0, /*Imm*/0,
      GIR_MergeMemOperands, /*InsnID*/0, /*NumInsns*/1, /*MergeInsnID's*/0,
      GIR_ConstrainSelectedInstOperands, /*InsnID*/0,
      GIR_EraseFromParent, /*InsnID*/0,
      // GIR_Coverage, 6835,
      GIR_Done,
    // Label 1414: @93855
    GIM_Try, /*On fail goto*//*Label 1415*/ GIMT_Encode4(93930), // Rule ID 6839 //
      GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasUnalignedAccessMode_LDSRequiresM0Init),
      GIM_CheckMemorySizeEqualToLLT, /*MI*/0, /*MMO*/0, /*OpIdx*/0,
      GIM_CheckMemoryAddressSpace, /*MI*/0, /*MMO*/0, /*NumAddrSpace*/1, /*AddrSpace*/3,
      GIM_CheckMemoryAddressSpace, /*MI*/0, /*MMO*/0, /*NumAddrSpace*/1, /*AddrSpace*/3,
      GIM_CheckAtomicOrdering, /*MI*/0, /*Order*/(uint8_t)AtomicOrdering::NotAtomic,
      GIM_CheckRegBankForClass, /*MI*/0, /*Op*/0, /*RC*/GIMT_Encode2(AMDGPU::AV_64RegClassID),
      GIM_CheckPointerToAny, /*MI*/0, /*Op*/1, /*SizeInBits*/0,
      GIM_CheckCxxInsnPredicate, /*MI*/0, /*FnId*/GIMT_Encode2(GICXXPred_MI_Predicate_load_align_less_than_4_local_m0),
      GIM_CheckComplexPattern, /*MI*/0, /*Op*/1, /*Renderer*/GIMT_Encode2(0), GIMT_Encode2(GICP_gi_ds_1addr_1offset),
      // (AMDGPUld_glue:{ *:[v4i16] } (DS1Addr1Offset:{ *:[iPTR] } i32:{ *:[i32] }:$ptr, i32:{ *:[i32] }:$offset))<<P:Predicate_unindexedload_glue>><<P:Predicate_load_glue>><<P:Predicate_load_local_m0>><<P:Predicate_load_align_less_than_4_local_m0>>  =>  (DS_READ_B64:{ *:[v4i16] } ?:{ *:[i32] }:$ptr, offset:{ *:[i32] }:$offset, 0:{ *:[i1] })
      GIR_BuildMI, /*InsnID*/0, /*Opcode*/GIMT_Encode2(AMDGPU::DS_READ_B64),
      GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/0, // DstI[vdst]
      GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/0, // ptr
      GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/1, // offset
      GIR_AddImm8, /*InsnID*/0, /*Imm*/0,
      GIR_MergeMemOperands, /*InsnID*/0, /*NumInsns*/1, /*MergeInsnID's*/0,
      GIR_ConstrainSelectedInstOperands, /*InsnID*/0,
      GIR_EraseFromParent, /*InsnID*/0,
      // GIR_Coverage, 6839,
      GIR_Done,
    // Label 1415: @93930
    GIM_Try, /*On fail goto*//*Label 1416*/ GIMT_Encode4(94000), // Rule ID 6755 //
      GIM_CheckFeatures, GIMT_Encode2(GIFBS_LDSRequiresM0Init),
      GIM_CheckMemorySizeEqualToLLT, /*MI*/0, /*MMO*/0, /*OpIdx*/0,
      GIM_CheckMemoryAddressSpace, /*MI*/0, /*MMO*/0, /*NumAddrSpace*/1, /*AddrSpace*/3,
      GIM_CheckMemoryAlignment, /*MI*/0, /*MMO*/0, /*MinAlign*/8,
      GIM_CheckAtomicOrdering, /*MI*/0, /*Order*/(uint8_t)AtomicOrdering::NotAtomic,
      GIM_CheckRegBankForClass, /*MI*/0, /*Op*/0, /*RC*/GIMT_Encode2(AMDGPU::AV_64RegClassID),
      GIM_CheckPointerToAny, /*MI*/0, /*Op*/1, /*SizeInBits*/0,
      GIM_CheckComplexPattern, /*MI*/0, /*Op*/1, /*Renderer*/GIMT_Encode2(0), GIMT_Encode2(GICP_gi_ds_1addr_1offset),
      // (AMDGPUld_glue:{ *:[v4f16] } (DS1Addr1Offset:{ *:[iPTR] } i32:{ *:[i32] }:$ptr, i32:{ *:[i32] }:$offset))<<P:Predicate_unindexedload_glue>><<P:Predicate_load_glue>><<P:Predicate_load_local_m0>><<P:Predicate_load_align8_local_m0>>  =>  (DS_READ_B64:{ *:[v4f16] } ?:{ *:[i32] }:$ptr, offset:{ *:[i32] }:$offset, 0:{ *:[i1] })
      GIR_BuildMI, /*InsnID*/0, /*Opcode*/GIMT_Encode2(AMDGPU::DS_READ_B64),
      GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/0, // DstI[vdst]
      GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/0, // ptr
      GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/1, // offset
      GIR_AddImm8, /*InsnID*/0, /*Imm*/0,
      GIR_MergeMemOperands, /*InsnID*/0, /*NumInsns*/1, /*MergeInsnID's*/0,
      GIR_ConstrainSelectedInstOperands, /*InsnID*/0,
      GIR_EraseFromParent, /*InsnID*/0,
      // GIR_Coverage, 6755,
      GIR_Done,
    // Label 1416: @94000
    GIM_Try, /*On fail goto*//*Label 1417*/ GIMT_Encode4(94070), // Rule ID 6759 //
      GIM_CheckFeatures, GIMT_Encode2(GIFBS_LDSRequiresM0Init),
      GIM_CheckMemorySizeEqualToLLT, /*MI*/0, /*MMO*/0, /*OpIdx*/0,
      GIM_CheckMemoryAddressSpace, /*MI*/0, /*MMO*/0, /*NumAddrSpace*/1, /*AddrSpace*/3,
      GIM_CheckMemoryAlignment, /*MI*/0, /*MMO*/0, /*MinAlign*/8,
      GIM_CheckAtomicOrdering, /*MI*/0, /*Order*/(uint8_t)AtomicOrdering::NotAtomic,
      GIM_CheckRegBankForClass, /*MI*/0, /*Op*/0, /*RC*/GIMT_Encode2(AMDGPU::AV_64RegClassID),
      GIM_CheckPointerToAny, /*MI*/0, /*Op*/1, /*SizeInBits*/0,
      GIM_CheckComplexPattern, /*MI*/0, /*Op*/1, /*Renderer*/GIMT_Encode2(0), GIMT_Encode2(GICP_gi_ds_1addr_1offset),
      // (AMDGPUld_glue:{ *:[v4bf16] } (DS1Addr1Offset:{ *:[iPTR] } i32:{ *:[i32] }:$ptr, i32:{ *:[i32] }:$offset))<<P:Predicate_unindexedload_glue>><<P:Predicate_load_glue>><<P:Predicate_load_local_m0>><<P:Predicate_load_align8_local_m0>>  =>  (DS_READ_B64:{ *:[v4bf16] } ?:{ *:[i32] }:$ptr, offset:{ *:[i32] }:$offset, 0:{ *:[i1] })
      GIR_BuildMI, /*InsnID*/0, /*Opcode*/GIMT_Encode2(AMDGPU::DS_READ_B64),
      GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/0, // DstI[vdst]
      GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/0, // ptr
      GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/1, // offset
      GIR_AddImm8, /*InsnID*/0, /*Imm*/0,
      GIR_MergeMemOperands, /*InsnID*/0, /*NumInsns*/1, /*MergeInsnID's*/0,
      GIR_ConstrainSelectedInstOperands, /*InsnID*/0,
      GIR_EraseFromParent, /*InsnID*/0,
      // GIR_Coverage, 6759,
      GIR_Done,
    // Label 1417: @94070
    GIM_Try, /*On fail goto*//*Label 1418*/ GIMT_Encode4(94140), // Rule ID 6763 //
      GIM_CheckFeatures, GIMT_Encode2(GIFBS_LDSRequiresM0Init),
      GIM_CheckMemorySizeEqualToLLT, /*MI*/0, /*MMO*/0, /*OpIdx*/0,
      GIM_CheckMemoryAddressSpace, /*MI*/0, /*MMO*/0, /*NumAddrSpace*/1, /*AddrSpace*/3,
      GIM_CheckMemoryAlignment, /*MI*/0, /*MMO*/0, /*MinAlign*/8,
      GIM_CheckAtomicOrdering, /*MI*/0, /*Order*/(uint8_t)AtomicOrdering::NotAtomic,
      GIM_CheckRegBankForClass, /*MI*/0, /*Op*/0, /*RC*/GIMT_Encode2(AMDGPU::AV_64RegClassID),
      GIM_CheckPointerToAny, /*MI*/0, /*Op*/1, /*SizeInBits*/0,
      GIM_CheckComplexPattern, /*MI*/0, /*Op*/1, /*Renderer*/GIMT_Encode2(0), GIMT_Encode2(GICP_gi_ds_1addr_1offset),
      // (AMDGPUld_glue:{ *:[v4i16] } (DS1Addr1Offset:{ *:[iPTR] } i32:{ *:[i32] }:$ptr, i32:{ *:[i32] }:$offset))<<P:Predicate_unindexedload_glue>><<P:Predicate_load_glue>><<P:Predicate_load_local_m0>><<P:Predicate_load_align8_local_m0>>  =>  (DS_READ_B64:{ *:[v4i16] } ?:{ *:[i32] }:$ptr, offset:{ *:[i32] }:$offset, 0:{ *:[i1] })
      GIR_BuildMI, /*InsnID*/0, /*Opcode*/GIMT_Encode2(AMDGPU::DS_READ_B64),
      GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/0, // DstI[vdst]
      GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/0, // ptr
      GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/1, // offset
      GIR_AddImm8, /*InsnID*/0, /*Imm*/0,
      GIR_MergeMemOperands, /*InsnID*/0, /*NumInsns*/1, /*MergeInsnID's*/0,
      GIR_ConstrainSelectedInstOperands, /*InsnID*/0,
      GIR_EraseFromParent, /*InsnID*/0,
      // GIR_Coverage, 6763,
      GIR_Done,
    // Label 1418: @94140
    GIM_Try, /*On fail goto*//*Label 1419*/ GIMT_Encode4(94202), // Rule ID 2530 //
      GIM_CheckMemorySizeEqualToLLT, /*MI*/0, /*MMO*/0, /*OpIdx*/0,
      GIM_CheckAtomicOrdering, /*MI*/0, /*Order*/(uint8_t)AtomicOrdering::NotAtomic,
      GIM_CheckRegBankForClass, /*MI*/0, /*Op*/0, /*RC*/GIMT_Encode2(AMDGPU::SReg_64_XEXECRegClassID),
      GIM_CheckPointerToAny, /*MI*/0, /*Op*/1, /*SizeInBits*/0,
      GIM_CheckCxxInsnPredicate, /*MI*/0, /*FnId*/GIMT_Encode2(GICXXPred_MI_Predicate_smrd_load),
      GIM_CheckComplexPattern, /*MI*/0, /*Op*/1, /*Renderer*/GIMT_Encode2(0), GIMT_Encode2(GICP_gi_smrd_imm),
      // (ld:{ *:[v4i16] } (SMRDImm:{ *:[iPTR] } i64:{ *:[i64] }:$sbase, i32:{ *:[i32] }:$offset))<<P:Predicate_unindexedload>><<P:Predicate_load>><<P:Predicate_smrd_load>>  =>  (S_LOAD_DWORDX2_IMM:{ *:[v4i16] } ?:{ *:[i64] }:$sbase, ?:{ *:[i32] }:$offset, 0:{ *:[i32] })
      GIR_BuildMI, /*InsnID*/0, /*Opcode*/GIMT_Encode2(AMDGPU::S_LOAD_DWORDX2_IMM),
      GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/0, // DstI[sdst]
      GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/0, // sbase
      GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/1, // offset
      GIR_AddImm8, /*InsnID*/0, /*Imm*/0,
      GIR_MergeMemOperands, /*InsnID*/0, /*NumInsns*/1, /*MergeInsnID's*/0,
      GIR_ConstrainSelectedInstOperands, /*InsnID*/0,
      GIR_EraseFromParent, /*InsnID*/0,
      // GIR_Coverage, 2530,
      GIR_Done,
    // Label 1419: @94202
    GIM_Try, /*On fail goto*//*Label 1420*/ GIMT_Encode4(94267), // Rule ID 2531 //
      GIM_CheckFeatures, GIMT_Encode2(GIFBS_isGFX7Only),
      GIM_CheckMemorySizeEqualToLLT, /*MI*/0, /*MMO*/0, /*OpIdx*/0,
      GIM_CheckAtomicOrdering, /*MI*/0, /*Order*/(uint8_t)AtomicOrdering::NotAtomic,
      GIM_CheckRegBankForClass, /*MI*/0, /*Op*/0, /*RC*/GIMT_Encode2(AMDGPU::SReg_64_XEXECRegClassID),
      GIM_CheckPointerToAny, /*MI*/0, /*Op*/1, /*SizeInBits*/0,
      GIM_CheckCxxInsnPredicate, /*MI*/0, /*FnId*/GIMT_Encode2(GICXXPred_MI_Predicate_smrd_load),
      GIM_CheckComplexPattern, /*MI*/0, /*Op*/1, /*Renderer*/GIMT_Encode2(0), GIMT_Encode2(GICP_gi_smrd_imm32),
      // (ld:{ *:[v4i16] } (SMRDImm32:{ *:[iPTR] } i64:{ *:[i64] }:$sbase, i32:{ *:[i32] }:$offset))<<P:Predicate_unindexedload>><<P:Predicate_load>><<P:Predicate_smrd_load>>  =>  (S_LOAD_DWORDX2_IMM_ci:{ *:[v4i16] } ?:{ *:[i64] }:$sbase, ?:{ *:[i32] }:$offset, 0:{ *:[i32] })
      GIR_BuildMI, /*InsnID*/0, /*Opcode*/GIMT_Encode2(AMDGPU::S_LOAD_DWORDX2_IMM_ci),
      GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/0, // DstI[sdst]
      GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/0, // sbase
      GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/1, // offset
      GIR_AddImm8, /*InsnID*/0, /*Imm*/0,
      GIR_MergeMemOperands, /*InsnID*/0, /*NumInsns*/1, /*MergeInsnID's*/0,
      GIR_ConstrainSelectedInstOperands, /*InsnID*/0,
      GIR_EraseFromParent, /*InsnID*/0,
      // GIR_Coverage, 2531,
      GIR_Done,
    // Label 1420: @94267
    GIM_Try, /*On fail goto*//*Label 1421*/ GIMT_Encode4(94332), // Rule ID 2532 //
      GIM_CheckFeatures, GIMT_Encode2(GIFBS_isNotGFX9Plus),
      GIM_CheckMemorySizeEqualToLLT, /*MI*/0, /*MMO*/0, /*OpIdx*/0,
      GIM_CheckAtomicOrdering, /*MI*/0, /*Order*/(uint8_t)AtomicOrdering::NotAtomic,
      GIM_CheckRegBankForClass, /*MI*/0, /*Op*/0, /*RC*/GIMT_Encode2(AMDGPU::SReg_64_XEXECRegClassID),
      GIM_CheckPointerToAny, /*MI*/0, /*Op*/1, /*SizeInBits*/0,
      GIM_CheckCxxInsnPredicate, /*MI*/0, /*FnId*/GIMT_Encode2(GICXXPred_MI_Predicate_smrd_load),
      GIM_CheckComplexPattern, /*MI*/0, /*Op*/1, /*Renderer*/GIMT_Encode2(0), GIMT_Encode2(GICP_gi_smrd_sgpr),
      // (ld:{ *:[v4i16] } (SMRDSgpr:{ *:[iPTR] } i64:{ *:[i64] }:$sbase, i32:{ *:[i32] }:$soffset))<<P:Predicate_unindexedload>><<P:Predicate_load>><<P:Predicate_smrd_load>>  =>  (S_LOAD_DWORDX2_SGPR:{ *:[v4i16] } ?:{ *:[i64] }:$sbase, ?:{ *:[i32] }:$soffset, 0:{ *:[i32] })
      GIR_BuildMI, /*InsnID*/0, /*Opcode*/GIMT_Encode2(AMDGPU::S_LOAD_DWORDX2_SGPR),
      GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/0, // DstI[sdst]
      GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/0, // sbase
      GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/1, // soffset
      GIR_AddImm8, /*InsnID*/0, /*Imm*/0,
      GIR_MergeMemOperands, /*InsnID*/0, /*NumInsns*/1, /*MergeInsnID's*/0,
      GIR_ConstrainSelectedInstOperands, /*InsnID*/0,
      GIR_EraseFromParent, /*InsnID*/0,
      // GIR_Coverage, 2532,
      GIR_Done,
    // Label 1421: @94332
    GIM_Try, /*On fail goto*//*Label 1422*/ GIMT_Encode4(94400), // Rule ID 2533 //
      GIM_CheckFeatures, GIMT_Encode2(GIFBS_isGFX9Plus),
      GIM_CheckMemorySizeEqualToLLT, /*MI*/0, /*MMO*/0, /*OpIdx*/0,
      GIM_CheckAtomicOrdering, /*MI*/0, /*Order*/(uint8_t)AtomicOrdering::NotAtomic,
      GIM_CheckRegBankForClass, /*MI*/0, /*Op*/0, /*RC*/GIMT_Encode2(AMDGPU::SReg_64_XEXECRegClassID),
      GIM_CheckPointerToAny, /*MI*/0, /*Op*/1, /*SizeInBits*/0,
      GIM_CheckCxxInsnPredicate, /*MI*/0, /*FnId*/GIMT_Encode2(GICXXPred_MI_Predicate_smrd_load),
      GIM_CheckComplexPattern, /*MI*/0, /*Op*/1, /*Renderer*/GIMT_Encode2(0), GIMT_Encode2(GICP_gi_smrd_sgpr),
      // (ld:{ *:[v4i16] } (SMRDSgpr:{ *:[iPTR] } i64:{ *:[i64] }:$sbase, i32:{ *:[i32] }:$soffset))<<P:Predicate_unindexedload>><<P:Predicate_load>><<P:Predicate_smrd_load>>  =>  (S_LOAD_DWORDX2_SGPR_IMM:{ *:[v4i16] } ?:{ *:[i64] }:$sbase, ?:{ *:[i32] }:$soffset, 0:{ *:[i32] }, 0:{ *:[i32] })
      GIR_BuildMI, /*InsnID*/0, /*Opcode*/GIMT_Encode2(AMDGPU::S_LOAD_DWORDX2_SGPR_IMM),
      GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/0, // DstI[sdst]
      GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/0, // sbase
      GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/1, // soffset
      GIR_AddImm8, /*InsnID*/0, /*Imm*/0,
      GIR_AddImm8, /*InsnID*/0, /*Imm*/0,
      GIR_MergeMemOperands, /*InsnID*/0, /*NumInsns*/1, /*MergeInsnID's*/0,
      GIR_ConstrainSelectedInstOperands, /*InsnID*/0,
      GIR_EraseFromParent, /*InsnID*/0,
      // GIR_Coverage, 2533,
      GIR_Done,
    // Label 1422: @94400
    GIM_Try, /*On fail goto*//*Label 1423*/ GIMT_Encode4(94462), // Rule ID 2536 //
      GIM_CheckMemorySizeEqualToLLT, /*MI*/0, /*MMO*/0, /*OpIdx*/0,
      GIM_CheckAtomicOrdering, /*MI*/0, /*Order*/(uint8_t)AtomicOrdering::NotAtomic,
      GIM_CheckRegBankForClass, /*MI*/0, /*Op*/0, /*RC*/GIMT_Encode2(AMDGPU::SReg_64_XEXECRegClassID),
      GIM_CheckPointerToAny, /*MI*/0, /*Op*/1, /*SizeInBits*/0,
      GIM_CheckCxxInsnPredicate, /*MI*/0, /*FnId*/GIMT_Encode2(GICXXPred_MI_Predicate_smrd_load),
      GIM_CheckComplexPattern, /*MI*/0, /*Op*/1, /*Renderer*/GIMT_Encode2(0), GIMT_Encode2(GICP_gi_smrd_imm),
      // (ld:{ *:[v4f16] } (SMRDImm:{ *:[iPTR] } i64:{ *:[i64] }:$sbase, i32:{ *:[i32] }:$offset))<<P:Predicate_unindexedload>><<P:Predicate_load>><<P:Predicate_smrd_load>>  =>  (S_LOAD_DWORDX2_IMM:{ *:[v4f16] } ?:{ *:[i64] }:$sbase, ?:{ *:[i32] }:$offset, 0:{ *:[i32] })
      GIR_BuildMI, /*InsnID*/0, /*Opcode*/GIMT_Encode2(AMDGPU::S_LOAD_DWORDX2_IMM),
      GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/0, // DstI[sdst]
      GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/0, // sbase
      GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/1, // offset
      GIR_AddImm8, /*InsnID*/0, /*Imm*/0,
      GIR_MergeMemOperands, /*InsnID*/0, /*NumInsns*/1, /*MergeInsnID's*/0,
      GIR_ConstrainSelectedInstOperands, /*InsnID*/0,
      GIR_EraseFromParent, /*InsnID*/0,
      // GIR_Coverage, 2536,
      GIR_Done,
    // Label 1423: @94462
    GIM_Try, /*On fail goto*//*Label 1424*/ GIMT_Encode4(94527), // Rule ID 2537 //
      GIM_CheckFeatures, GIMT_Encode2(GIFBS_isGFX7Only),
      GIM_CheckMemorySizeEqualToLLT, /*MI*/0, /*MMO*/0, /*OpIdx*/0,
      GIM_CheckAtomicOrdering, /*MI*/0, /*Order*/(uint8_t)AtomicOrdering::NotAtomic,
      GIM_CheckRegBankForClass, /*MI*/0, /*Op*/0, /*RC*/GIMT_Encode2(AMDGPU::SReg_64_XEXECRegClassID),
      GIM_CheckPointerToAny, /*MI*/0, /*Op*/1, /*SizeInBits*/0,
      GIM_CheckCxxInsnPredicate, /*MI*/0, /*FnId*/GIMT_Encode2(GICXXPred_MI_Predicate_smrd_load),
      GIM_CheckComplexPattern, /*MI*/0, /*Op*/1, /*Renderer*/GIMT_Encode2(0), GIMT_Encode2(GICP_gi_smrd_imm32),
      // (ld:{ *:[v4f16] } (SMRDImm32:{ *:[iPTR] } i64:{ *:[i64] }:$sbase, i32:{ *:[i32] }:$offset))<<P:Predicate_unindexedload>><<P:Predicate_load>><<P:Predicate_smrd_load>>  =>  (S_LOAD_DWORDX2_IMM_ci:{ *:[v4f16] } ?:{ *:[i64] }:$sbase, ?:{ *:[i32] }:$offset, 0:{ *:[i32] })
      GIR_BuildMI, /*InsnID*/0, /*Opcode*/GIMT_Encode2(AMDGPU::S_LOAD_DWORDX2_IMM_ci),
      GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/0, // DstI[sdst]
      GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/0, // sbase
      GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/1, // offset
      GIR_AddImm8, /*InsnID*/0, /*Imm*/0,
      GIR_MergeMemOperands, /*InsnID*/0, /*NumInsns*/1, /*MergeInsnID's*/0,
      GIR_ConstrainSelectedInstOperands, /*InsnID*/0,
      GIR_EraseFromParent, /*InsnID*/0,
      // GIR_Coverage, 2537,
      GIR_Done,
    // Label 1424: @94527
    GIM_Try, /*On fail goto*//*Label 1425*/ GIMT_Encode4(94592), // Rule ID 2538 //
      GIM_CheckFeatures, GIMT_Encode2(GIFBS_isNotGFX9Plus),
      GIM_CheckMemorySizeEqualToLLT, /*MI*/0, /*MMO*/0, /*OpIdx*/0,
      GIM_CheckAtomicOrdering, /*MI*/0, /*Order*/(uint8_t)AtomicOrdering::NotAtomic,
      GIM_CheckRegBankForClass, /*MI*/0, /*Op*/0, /*RC*/GIMT_Encode2(AMDGPU::SReg_64_XEXECRegClassID),
      GIM_CheckPointerToAny, /*MI*/0, /*Op*/1, /*SizeInBits*/0,
      GIM_CheckCxxInsnPredicate, /*MI*/0, /*FnId*/GIMT_Encode2(GICXXPred_MI_Predicate_smrd_load),
      GIM_CheckComplexPattern, /*MI*/0, /*Op*/1, /*Renderer*/GIMT_Encode2(0), GIMT_Encode2(GICP_gi_smrd_sgpr),
      // (ld:{ *:[v4f16] } (SMRDSgpr:{ *:[iPTR] } i64:{ *:[i64] }:$sbase, i32:{ *:[i32] }:$soffset))<<P:Predicate_unindexedload>><<P:Predicate_load>><<P:Predicate_smrd_load>>  =>  (S_LOAD_DWORDX2_SGPR:{ *:[v4f16] } ?:{ *:[i64] }:$sbase, ?:{ *:[i32] }:$soffset, 0:{ *:[i32] })
      GIR_BuildMI, /*InsnID*/0, /*Opcode*/GIMT_Encode2(AMDGPU::S_LOAD_DWORDX2_SGPR),
      GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/0, // DstI[sdst]
      GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/0, // sbase
      GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/1, // soffset
      GIR_AddImm8, /*InsnID*/0, /*Imm*/0,
      GIR_MergeMemOperands, /*InsnID*/0, /*NumInsns*/1, /*MergeInsnID's*/0,
      GIR_ConstrainSelectedInstOperands, /*InsnID*/0,
      GIR_EraseFromParent, /*InsnID*/0,
      // GIR_Coverage, 2538,
      GIR_Done,
    // Label 1425: @94592
    GIM_Try, /*On fail goto*//*Label 1426*/ GIMT_Encode4(94660), // Rule ID 2539 //
      GIM_CheckFeatures, GIMT_Encode2(GIFBS_isGFX9Plus),
      GIM_CheckMemorySizeEqualToLLT, /*MI*/0, /*MMO*/0, /*OpIdx*/0,
      GIM_CheckAtomicOrdering, /*MI*/0, /*Order*/(uint8_t)AtomicOrdering::NotAtomic,
      GIM_CheckRegBankForClass, /*MI*/0, /*Op*/0, /*RC*/GIMT_Encode2(AMDGPU::SReg_64_XEXECRegClassID),
      GIM_CheckPointerToAny, /*MI*/0, /*Op*/1, /*SizeInBits*/0,
      GIM_CheckCxxInsnPredicate, /*MI*/0, /*FnId*/GIMT_Encode2(GICXXPred_MI_Predicate_smrd_load),
      GIM_CheckComplexPattern, /*MI*/0, /*Op*/1, /*Renderer*/GIMT_Encode2(0), GIMT_Encode2(GICP_gi_smrd_sgpr),
      // (ld:{ *:[v4f16] } (SMRDSgpr:{ *:[iPTR] } i64:{ *:[i64] }:$sbase, i32:{ *:[i32] }:$soffset))<<P:Predicate_unindexedload>><<P:Predicate_load>><<P:Predicate_smrd_load>>  =>  (S_LOAD_DWORDX2_SGPR_IMM:{ *:[v4f16] } ?:{ *:[i64] }:$sbase, ?:{ *:[i32] }:$soffset, 0:{ *:[i32] }, 0:{ *:[i32] })
      GIR_BuildMI, /*InsnID*/0, /*Opcode*/GIMT_Encode2(AMDGPU::S_LOAD_DWORDX2_SGPR_IMM),
      GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/0, // DstI[sdst]
      GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/0, // sbase
      GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/1, // soffset
      GIR_AddImm8, /*InsnID*/0, /*Imm*/0,
      GIR_AddImm8, /*InsnID*/0, /*Imm*/0,
      GIR_MergeMemOperands, /*InsnID*/0, /*NumInsns*/1, /*MergeInsnID's*/0,
      GIR_ConstrainSelectedInstOperands, /*InsnID*/0,
      GIR_EraseFromParent, /*InsnID*/0,
      // GIR_Coverage, 2539,
      GIR_Done,
    // Label 1426: @94660
    GIM_Try, /*On fail goto*//*Label 1427*/ GIMT_Encode4(94722), // Rule ID 2542 //
      GIM_CheckMemorySizeEqualToLLT, /*MI*/0, /*MMO*/0, /*OpIdx*/0,
      GIM_CheckAtomicOrdering, /*MI*/0, /*Order*/(uint8_t)AtomicOrdering::NotAtomic,
      GIM_CheckRegBankForClass, /*MI*/0, /*Op*/0, /*RC*/GIMT_Encode2(AMDGPU::SReg_64_XEXECRegClassID),
      GIM_CheckPointerToAny, /*MI*/0, /*Op*/1, /*SizeInBits*/0,
      GIM_CheckCxxInsnPredicate, /*MI*/0, /*FnId*/GIMT_Encode2(GICXXPred_MI_Predicate_smrd_load),
      GIM_CheckComplexPattern, /*MI*/0, /*Op*/1, /*Renderer*/GIMT_Encode2(0), GIMT_Encode2(GICP_gi_smrd_imm),
      // (ld:{ *:[v4bf16] } (SMRDImm:{ *:[iPTR] } i64:{ *:[i64] }:$sbase, i32:{ *:[i32] }:$offset))<<P:Predicate_unindexedload>><<P:Predicate_load>><<P:Predicate_smrd_load>>  =>  (S_LOAD_DWORDX2_IMM:{ *:[v4bf16] } ?:{ *:[i64] }:$sbase, ?:{ *:[i32] }:$offset, 0:{ *:[i32] })
      GIR_BuildMI, /*InsnID*/0, /*Opcode*/GIMT_Encode2(AMDGPU::S_LOAD_DWORDX2_IMM),
      GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/0, // DstI[sdst]
      GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/0, // sbase
      GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/1, // offset
      GIR_AddImm8, /*InsnID*/0, /*Imm*/0,
      GIR_MergeMemOperands, /*InsnID*/0, /*NumInsns*/1, /*MergeInsnID's*/0,
      GIR_ConstrainSelectedInstOperands, /*InsnID*/0,
      GIR_EraseFromParent, /*InsnID*/0,
      // GIR_Coverage, 2542,
      GIR_Done,
    // Label 1427: @94722
    GIM_Try, /*On fail goto*//*Label 1428*/ GIMT_Encode4(94787), // Rule ID 2543 //
      GIM_CheckFeatures, GIMT_Encode2(GIFBS_isGFX7Only),
      GIM_CheckMemorySizeEqualToLLT, /*MI*/0, /*MMO*/0, /*OpIdx*/0,
      GIM_CheckAtomicOrdering, /*MI*/0, /*Order*/(uint8_t)AtomicOrdering::NotAtomic,
      GIM_CheckRegBankForClass, /*MI*/0, /*Op*/0, /*RC*/GIMT_Encode2(AMDGPU::SReg_64_XEXECRegClassID),
      GIM_CheckPointerToAny, /*MI*/0, /*Op*/1, /*SizeInBits*/0,
      GIM_CheckCxxInsnPredicate, /*MI*/0, /*FnId*/GIMT_Encode2(GICXXPred_MI_Predicate_smrd_load),
      GIM_CheckComplexPattern, /*MI*/0, /*Op*/1, /*Renderer*/GIMT_Encode2(0), GIMT_Encode2(GICP_gi_smrd_imm32),
      // (ld:{ *:[v4bf16] } (SMRDImm32:{ *:[iPTR] } i64:{ *:[i64] }:$sbase, i32:{ *:[i32] }:$offset))<<P:Predicate_unindexedload>><<P:Predicate_load>><<P:Predicate_smrd_load>>  =>  (S_LOAD_DWORDX2_IMM_ci:{ *:[v4bf16] } ?:{ *:[i64] }:$sbase, ?:{ *:[i32] }:$offset, 0:{ *:[i32] })
      GIR_BuildMI, /*InsnID*/0, /*Opcode*/GIMT_Encode2(AMDGPU::S_LOAD_DWORDX2_IMM_ci),
      GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/0, // DstI[sdst]
      GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/0, // sbase
      GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/1, // offset
      GIR_AddImm8, /*InsnID*/0, /*Imm*/0,
      GIR_MergeMemOperands, /*InsnID*/0, /*NumInsns*/1, /*MergeInsnID's*/0,
      GIR_ConstrainSelectedInstOperands, /*InsnID*/0,
      GIR_EraseFromParent, /*InsnID*/0,
      // GIR_Coverage, 2543,
      GIR_Done,
    // Label 1428: @94787
    GIM_Try, /*On fail goto*//*Label 1429*/ GIMT_Encode4(94852), // Rule ID 2544 //
      GIM_CheckFeatures, GIMT_Encode2(GIFBS_isNotGFX9Plus),
      GIM_CheckMemorySizeEqualToLLT, /*MI*/0, /*MMO*/0, /*OpIdx*/0,
      GIM_CheckAtomicOrdering, /*MI*/0, /*Order*/(uint8_t)AtomicOrdering::NotAtomic,
      GIM_CheckRegBankForClass, /*MI*/0, /*Op*/0, /*RC*/GIMT_Encode2(AMDGPU::SReg_64_XEXECRegClassID),
      GIM_CheckPointerToAny, /*MI*/0, /*Op*/1, /*SizeInBits*/0,
      GIM_CheckCxxInsnPredicate, /*MI*/0, /*FnId*/GIMT_Encode2(GICXXPred_MI_Predicate_smrd_load),
      GIM_CheckComplexPattern, /*MI*/0, /*Op*/1, /*Renderer*/GIMT_Encode2(0), GIMT_Encode2(GICP_gi_smrd_sgpr),
      // (ld:{ *:[v4bf16] } (SMRDSgpr:{ *:[iPTR] } i64:{ *:[i64] }:$sbase, i32:{ *:[i32] }:$soffset))<<P:Predicate_unindexedload>><<P:Predicate_load>><<P:Predicate_smrd_load>>  =>  (S_LOAD_DWORDX2_SGPR:{ *:[v4bf16] } ?:{ *:[i64] }:$sbase, ?:{ *:[i32] }:$soffset, 0:{ *:[i32] })
      GIR_BuildMI, /*InsnID*/0, /*Opcode*/GIMT_Encode2(AMDGPU::S_LOAD_DWORDX2_SGPR),
      GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/0, // DstI[sdst]
      GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/0, // sbase
      GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/1, // soffset
      GIR_AddImm8, /*InsnID*/0, /*Imm*/0,
      GIR_MergeMemOperands, /*InsnID*/0, /*NumInsns*/1, /*MergeInsnID's*/0,
      GIR_ConstrainSelectedInstOperands, /*InsnID*/0,
      GIR_EraseFromParent, /*InsnID*/0,
      // GIR_Coverage, 2544,
      GIR_Done,
    // Label 1429: @94852
    GIM_Try, /*On fail goto*//*Label 1430*/ GIMT_Encode4(94920), // Rule ID 2545 //
      GIM_CheckFeatures, GIMT_Encode2(GIFBS_isGFX9Plus),
      GIM_CheckMemorySizeEqualToLLT, /*MI*/0, /*MMO*/0, /*OpIdx*/0,
      GIM_CheckAtomicOrdering, /*MI*/0, /*Order*/(uint8_t)AtomicOrdering::NotAtomic,
      GIM_CheckRegBankForClass, /*MI*/0, /*Op*/0, /*RC*/GIMT_Encode2(AMDGPU::SReg_64_XEXECRegClassID),
      GIM_CheckPointerToAny, /*MI*/0, /*Op*/1, /*SizeInBits*/0,
      GIM_CheckCxxInsnPredicate, /*MI*/0, /*FnId*/GIMT_Encode2(GICXXPred_MI_Predicate_smrd_load),
      GIM_CheckComplexPattern, /*MI*/0, /*Op*/1, /*Renderer*/GIMT_Encode2(0), GIMT_Encode2(GICP_gi_smrd_sgpr),
      // (ld:{ *:[v4bf16] } (SMRDSgpr:{ *:[iPTR] } i64:{ *:[i64] }:$sbase, i32:{ *:[i32] }:$soffset))<<P:Predicate_unindexedload>><<P:Predicate_load>><<P:Predicate_smrd_load>>  =>  (S_LOAD_DWORDX2_SGPR_IMM:{ *:[v4bf16] } ?:{ *:[i64] }:$sbase, ?:{ *:[i32] }:$soffset, 0:{ *:[i32] }, 0:{ *:[i32] })
      GIR_BuildMI, /*InsnID*/0, /*Opcode*/GIMT_Encode2(AMDGPU::S_LOAD_DWORDX2_SGPR_IMM),
      GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/0, // DstI[sdst]
      GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/0, // sbase
      GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/1, // soffset
      GIR_AddImm8, /*InsnID*/0, /*Imm*/0,
      GIR_AddImm8, /*InsnID*/0, /*Imm*/0,
      GIR_MergeMemOperands, /*InsnID*/0, /*NumInsns*/1, /*MergeInsnID's*/0,
      GIR_ConstrainSelectedInstOperands, /*InsnID*/0,
      GIR_EraseFromParent, /*InsnID*/0,
      // GIR_Coverage, 2545,
      GIR_Done,
    // Label 1430: @94920
    GIM_Try, /*On fail goto*//*Label 1431*/ GIMT_Encode4(94991), // Rule ID 6832 //
      GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasUnalignedAccessMode_NotLDSRequiresM0Init),
      GIM_CheckMemoryAddressSpace, /*MI*/0, /*MMO*/0, /*NumAddrSpace*/1, /*AddrSpace*/3,
      GIM_CheckMemoryAddressSpace, /*MI*/0, /*MMO*/0, /*NumAddrSpace*/1, /*AddrSpace*/3,
      GIM_CheckAtomicOrdering, /*MI*/0, /*Order*/(uint8_t)AtomicOrdering::NotAtomic,
      GIM_CheckRegBankForClass, /*MI*/0, /*Op*/0, /*RC*/GIMT_Encode2(AMDGPU::AV_64RegClassID),
      GIM_CheckPointerToAny, /*MI*/0, /*Op*/1, /*SizeInBits*/0,
      GIM_CheckCxxInsnPredicate, /*MI*/0, /*FnId*/GIMT_Encode2(GICXXPred_MI_Predicate_load_align_less_than_4_local),
      GIM_CheckComplexPattern, /*MI*/0, /*Op*/1, /*Renderer*/GIMT_Encode2(0), GIMT_Encode2(GICP_gi_ds_1addr_1offset),
      // (ld:{ *:[v4f16] } (DS1Addr1Offset:{ *:[iPTR] } i32:{ *:[i32] }:$ptr, i32:{ *:[i32] }:$offset))<<P:Predicate_unindexedload>><<P:Predicate_load_local>><<P:Predicate_load_align_less_than_4_local>>  =>  (DS_READ_B64_gfx9:{ *:[v4f16] } ?:{ *:[i32] }:$ptr, offset:{ *:[i32] }:$offset, 0:{ *:[i1] })
      GIR_BuildMI, /*InsnID*/0, /*Opcode*/GIMT_Encode2(AMDGPU::DS_READ_B64_gfx9),
      GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/0, // DstI[vdst]
      GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/0, // ptr
      GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/1, // offset
      GIR_AddImm8, /*InsnID*/0, /*Imm*/0,
      GIR_MergeMemOperands, /*InsnID*/0, /*NumInsns*/1, /*MergeInsnID's*/0,
      GIR_ConstrainSelectedInstOperands, /*InsnID*/0,
      GIR_EraseFromParent, /*InsnID*/0,
      // GIR_Coverage, 6832,
      GIR_Done,
    // Label 1431: @94991
    GIM_Try, /*On fail goto*//*Label 1432*/ GIMT_Encode4(95062), // Rule ID 6836 //
      GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasUnalignedAccessMode_NotLDSRequiresM0Init),
      GIM_CheckMemoryAddressSpace, /*MI*/0, /*MMO*/0, /*NumAddrSpace*/1, /*AddrSpace*/3,
      GIM_CheckMemoryAddressSpace, /*MI*/0, /*MMO*/0, /*NumAddrSpace*/1, /*AddrSpace*/3,
      GIM_CheckAtomicOrdering, /*MI*/0, /*Order*/(uint8_t)AtomicOrdering::NotAtomic,
      GIM_CheckRegBankForClass, /*MI*/0, /*Op*/0, /*RC*/GIMT_Encode2(AMDGPU::AV_64RegClassID),
      GIM_CheckPointerToAny, /*MI*/0, /*Op*/1, /*SizeInBits*/0,
      GIM_CheckCxxInsnPredicate, /*MI*/0, /*FnId*/GIMT_Encode2(GICXXPred_MI_Predicate_load_align_less_than_4_local),
      GIM_CheckComplexPattern, /*MI*/0, /*Op*/1, /*Renderer*/GIMT_Encode2(0), GIMT_Encode2(GICP_gi_ds_1addr_1offset),
      // (ld:{ *:[v4bf16] } (DS1Addr1Offset:{ *:[iPTR] } i32:{ *:[i32] }:$ptr, i32:{ *:[i32] }:$offset))<<P:Predicate_unindexedload>><<P:Predicate_load_local>><<P:Predicate_load_align_less_than_4_local>>  =>  (DS_READ_B64_gfx9:{ *:[v4bf16] } ?:{ *:[i32] }:$ptr, offset:{ *:[i32] }:$offset, 0:{ *:[i1] })
      GIR_BuildMI, /*InsnID*/0, /*Opcode*/GIMT_Encode2(AMDGPU::DS_READ_B64_gfx9),
      GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/0, // DstI[vdst]
      GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/0, // ptr
      GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/1, // offset
      GIR_AddImm8, /*InsnID*/0, /*Imm*/0,
      GIR_MergeMemOperands, /*InsnID*/0, /*NumInsns*/1, /*MergeInsnID's*/0,
      GIR_ConstrainSelectedInstOperands, /*InsnID*/0,
      GIR_EraseFromParent, /*InsnID*/0,
      // GIR_Coverage, 6836,
      GIR_Done,
    // Label 1432: @95062
    GIM_Try, /*On fail goto*//*Label 1433*/ GIMT_Encode4(95133), // Rule ID 6840 //
      GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasUnalignedAccessMode_NotLDSRequiresM0Init),
      GIM_CheckMemoryAddressSpace, /*MI*/0, /*MMO*/0, /*NumAddrSpace*/1, /*AddrSpace*/3,
      GIM_CheckMemoryAddressSpace, /*MI*/0, /*MMO*/0, /*NumAddrSpace*/1, /*AddrSpace*/3,
      GIM_CheckAtomicOrdering, /*MI*/0, /*Order*/(uint8_t)AtomicOrdering::NotAtomic,
      GIM_CheckRegBankForClass, /*MI*/0, /*Op*/0, /*RC*/GIMT_Encode2(AMDGPU::AV_64RegClassID),
      GIM_CheckPointerToAny, /*MI*/0, /*Op*/1, /*SizeInBits*/0,
      GIM_CheckCxxInsnPredicate, /*MI*/0, /*FnId*/GIMT_Encode2(GICXXPred_MI_Predicate_load_align_less_than_4_local),
      GIM_CheckComplexPattern, /*MI*/0, /*Op*/1, /*Renderer*/GIMT_Encode2(0), GIMT_Encode2(GICP_gi_ds_1addr_1offset),
      // (ld:{ *:[v4i16] } (DS1Addr1Offset:{ *:[iPTR] } i32:{ *:[i32] }:$ptr, i32:{ *:[i32] }:$offset))<<P:Predicate_unindexedload>><<P:Predicate_load_local>><<P:Predicate_load_align_less_than_4_local>>  =>  (DS_READ_B64_gfx9:{ *:[v4i16] } ?:{ *:[i32] }:$ptr, offset:{ *:[i32] }:$offset, 0:{ *:[i1] })
      GIR_BuildMI, /*InsnID*/0, /*Opcode*/GIMT_Encode2(AMDGPU::DS_READ_B64_gfx9),
      GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/0, // DstI[vdst]
      GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/0, // ptr
      GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/1, // offset
      GIR_AddImm8, /*InsnID*/0, /*Imm*/0,
      GIR_MergeMemOperands, /*InsnID*/0, /*NumInsns*/1, /*MergeInsnID's*/0,
      GIR_ConstrainSelectedInstOperands, /*InsnID*/0,
      GIR_EraseFromParent, /*InsnID*/0,
      // GIR_Coverage, 6840,
      GIR_Done,
    // Label 1433: @95133
    GIM_Try, /*On fail goto*//*Label 1434*/ GIMT_Encode4(95199), // Rule ID 6756 //
      GIM_CheckFeatures, GIMT_Encode2(GIFBS_NotLDSRequiresM0Init),
      GIM_CheckMemoryAddressSpace, /*MI*/0, /*MMO*/0, /*NumAddrSpace*/1, /*AddrSpace*/3,
      GIM_CheckMemoryAlignment, /*MI*/0, /*MMO*/0, /*MinAlign*/8,
      GIM_CheckAtomicOrdering, /*MI*/0, /*Order*/(uint8_t)AtomicOrdering::NotAtomic,
      GIM_CheckRegBankForClass, /*MI*/0, /*Op*/0, /*RC*/GIMT_Encode2(AMDGPU::AV_64RegClassID),
      GIM_CheckPointerToAny, /*MI*/0, /*Op*/1, /*SizeInBits*/0,
      GIM_CheckComplexPattern, /*MI*/0, /*Op*/1, /*Renderer*/GIMT_Encode2(0), GIMT_Encode2(GICP_gi_ds_1addr_1offset),
      // (ld:{ *:[v4f16] } (DS1Addr1Offset:{ *:[iPTR] } i32:{ *:[i32] }:$ptr, i32:{ *:[i32] }:$offset))<<P:Predicate_unindexedload>><<P:Predicate_load_local>><<P:Predicate_load_align8_local>>  =>  (DS_READ_B64_gfx9:{ *:[v4f16] } ?:{ *:[i32] }:$ptr, offset:{ *:[i32] }:$offset, 0:{ *:[i1] })
      GIR_BuildMI, /*InsnID*/0, /*Opcode*/GIMT_Encode2(AMDGPU::DS_READ_B64_gfx9),
      GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/0, // DstI[vdst]
      GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/0, // ptr
      GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/1, // offset
      GIR_AddImm8, /*InsnID*/0, /*Imm*/0,
      GIR_MergeMemOperands, /*InsnID*/0, /*NumInsns*/1, /*MergeInsnID's*/0,
      GIR_ConstrainSelectedInstOperands, /*InsnID*/0,
      GIR_EraseFromParent, /*InsnID*/0,
      // GIR_Coverage, 6756,
      GIR_Done,
    // Label 1434: @95199
    GIM_Try, /*On fail goto*//*Label 1435*/ GIMT_Encode4(95265), // Rule ID 6760 //
      GIM_CheckFeatures, GIMT_Encode2(GIFBS_NotLDSRequiresM0Init),
      GIM_CheckMemoryAddressSpace, /*MI*/0, /*MMO*/0, /*NumAddrSpace*/1, /*AddrSpace*/3,
      GIM_CheckMemoryAlignment, /*MI*/0, /*MMO*/0, /*MinAlign*/8,
      GIM_CheckAtomicOrdering, /*MI*/0, /*Order*/(uint8_t)AtomicOrdering::NotAtomic,
      GIM_CheckRegBankForClass, /*MI*/0, /*Op*/0, /*RC*/GIMT_Encode2(AMDGPU::AV_64RegClassID),
      GIM_CheckPointerToAny, /*MI*/0, /*Op*/1, /*SizeInBits*/0,
      GIM_CheckComplexPattern, /*MI*/0, /*Op*/1, /*Renderer*/GIMT_Encode2(0), GIMT_Encode2(GICP_gi_ds_1addr_1offset),
      // (ld:{ *:[v4bf16] } (DS1Addr1Offset:{ *:[iPTR] } i32:{ *:[i32] }:$ptr, i32:{ *:[i32] }:$offset))<<P:Predicate_unindexedload>><<P:Predicate_load_local>><<P:Predicate_load_align8_local>>  =>  (DS_READ_B64_gfx9:{ *:[v4bf16] } ?:{ *:[i32] }:$ptr, offset:{ *:[i32] }:$offset, 0:{ *:[i1] })
      GIR_BuildMI, /*InsnID*/0, /*Opcode*/GIMT_Encode2(AMDGPU::DS_READ_B64_gfx9),
      GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/0, // DstI[vdst]
      GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/0, // ptr
      GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/1, // offset
      GIR_AddImm8, /*InsnID*/0, /*Imm*/0,
      GIR_MergeMemOperands, /*InsnID*/0, /*NumInsns*/1, /*MergeInsnID's*/0,
      GIR_ConstrainSelectedInstOperands, /*InsnID*/0,
      GIR_EraseFromParent, /*InsnID*/0,
      // GIR_Coverage, 6760,
      GIR_Done,
    // Label 1435: @95265
    GIM_Try, /*On fail goto*//*Label 1436*/ GIMT_Encode4(95331), // Rule ID 6764 //
      GIM_CheckFeatures, GIMT_Encode2(GIFBS_NotLDSRequiresM0Init),
      GIM_CheckMemoryAddressSpace, /*MI*/0, /*MMO*/0, /*NumAddrSpace*/1, /*AddrSpace*/3,
      GIM_CheckMemoryAlignment, /*MI*/0, /*MMO*/0, /*MinAlign*/8,
      GIM_CheckAtomicOrdering, /*MI*/0, /*Order*/(uint8_t)AtomicOrdering::NotAtomic,
      GIM_CheckRegBankForClass, /*MI*/0, /*Op*/0, /*RC*/GIMT_Encode2(AMDGPU::AV_64RegClassID),
      GIM_CheckPointerToAny, /*MI*/0, /*Op*/1, /*SizeInBits*/0,
      GIM_CheckComplexPattern, /*MI*/0, /*Op*/1, /*Renderer*/GIMT_Encode2(0), GIMT_Encode2(GICP_gi_ds_1addr_1offset),
      // (ld:{ *:[v4i16] } (DS1Addr1Offset:{ *:[iPTR] } i32:{ *:[i32] }:$ptr, i32:{ *:[i32] }:$offset))<<P:Predicate_unindexedload>><<P:Predicate_load_local>><<P:Predicate_load_align8_local>>  =>  (DS_READ_B64_gfx9:{ *:[v4i16] } ?:{ *:[i32] }:$ptr, offset:{ *:[i32] }:$offset, 0:{ *:[i1] })
      GIR_BuildMI, /*InsnID*/0, /*Opcode*/GIMT_Encode2(AMDGPU::DS_READ_B64_gfx9),
      GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/0, // DstI[vdst]
      GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/0, // ptr
      GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/1, // offset
      GIR_AddImm8, /*InsnID*/0, /*Imm*/0,
      GIR_MergeMemOperands, /*InsnID*/0, /*NumInsns*/1, /*MergeInsnID's*/0,
      GIR_ConstrainSelectedInstOperands, /*InsnID*/0,
      GIR_EraseFromParent, /*InsnID*/0,
      // GIR_Coverage, 6764,
      GIR_Done,
    // Label 1436: @95331
    GIM_Try, /*On fail goto*//*Label 1437*/ GIMT_Encode4(95388), // Rule ID 2535 //
      GIM_CheckMemorySizeEqualToLLT, /*MI*/0, /*MMO*/0, /*OpIdx*/0,
      GIM_CheckAtomicOrdering, /*MI*/0, /*Order*/(uint8_t)AtomicOrdering::NotAtomic,
      GIM_CheckRegBankForClass, /*MI*/0, /*Op*/0, /*RC*/GIMT_Encode2(AMDGPU::SReg_64_XEXECRegClassID),
      // MIs[0] sbase
      GIM_CheckPointerToAny, /*MI*/0, /*Op*/1, /*SizeInBits*/64,
      GIM_CheckRegBankForClass, /*MI*/0, /*Op*/1, /*RC*/GIMT_Encode2(AMDGPU::SReg_64RegClassID),
      GIM_CheckCxxInsnPredicate, /*MI*/0, /*FnId*/GIMT_Encode2(GICXXPred_MI_Predicate_smrd_load),
      // (ld:{ *:[v4i16] } SReg_64:{ *:[i64] }:$sbase)<<P:Predicate_unindexedload>><<P:Predicate_load>><<P:Predicate_smrd_load>>  =>  (S_LOAD_DWORDX2_IMM:{ *:[v4i16] } i64:{ *:[i64] }:$sbase, 0:{ *:[i32] }, 0:{ *:[i32] })
      GIR_BuildMI, /*InsnID*/0, /*Opcode*/GIMT_Encode2(AMDGPU::S_LOAD_DWORDX2_IMM),
      GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/0, // DstI[sdst]
      GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/1, // sbase
      GIR_AddImm8, /*InsnID*/0, /*Imm*/0,
      GIR_AddImm8, /*InsnID*/0, /*Imm*/0,
      GIR_MergeMemOperands, /*InsnID*/0, /*NumInsns*/1, /*MergeInsnID's*/0,
      GIR_ConstrainSelectedInstOperands, /*InsnID*/0,
      GIR_EraseFromParent, /*InsnID*/0,
      // GIR_Coverage, 2535,
      GIR_Done,
    // Label 1437: @95388
    GIM_Try, /*On fail goto*//*Label 1438*/ GIMT_Encode4(95445), // Rule ID 2541 //
      GIM_CheckMemorySizeEqualToLLT, /*MI*/0, /*MMO*/0, /*OpIdx*/0,
      GIM_CheckAtomicOrdering, /*MI*/0, /*Order*/(uint8_t)AtomicOrdering::NotAtomic,
      GIM_CheckRegBankForClass, /*MI*/0, /*Op*/0, /*RC*/GIMT_Encode2(AMDGPU::SReg_64_XEXECRegClassID),
      // MIs[0] sbase
      GIM_CheckPointerToAny, /*MI*/0, /*Op*/1, /*SizeInBits*/64,
      GIM_CheckRegBankForClass, /*MI*/0, /*Op*/1, /*RC*/GIMT_Encode2(AMDGPU::SReg_64RegClassID),
      GIM_CheckCxxInsnPredicate, /*MI*/0, /*FnId*/GIMT_Encode2(GICXXPred_MI_Predicate_smrd_load),
      // (ld:{ *:[v4f16] } SReg_64:{ *:[i64] }:$sbase)<<P:Predicate_unindexedload>><<P:Predicate_load>><<P:Predicate_smrd_load>>  =>  (S_LOAD_DWORDX2_IMM:{ *:[v4f16] } i64:{ *:[i64] }:$sbase, 0:{ *:[i32] }, 0:{ *:[i32] })
      GIR_BuildMI, /*InsnID*/0, /*Opcode*/GIMT_Encode2(AMDGPU::S_LOAD_DWORDX2_IMM),
      GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/0, // DstI[sdst]
      GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/1, // sbase
      GIR_AddImm8, /*InsnID*/0, /*Imm*/0,
      GIR_AddImm8, /*InsnID*/0, /*Imm*/0,
      GIR_MergeMemOperands, /*InsnID*/0, /*NumInsns*/1, /*MergeInsnID's*/0,
      GIR_ConstrainSelectedInstOperands, /*InsnID*/0,
      GIR_EraseFromParent, /*InsnID*/0,
      // GIR_Coverage, 2541,
      GIR_Done,
    // Label 1438: @95445
    GIM_Try, /*On fail goto*//*Label 1439*/ GIMT_Encode4(95502), // Rule ID 2547 //
      GIM_CheckMemorySizeEqualToLLT, /*MI*/0, /*MMO*/0, /*OpIdx*/0,
      GIM_CheckAtomicOrdering, /*MI*/0, /*Order*/(uint8_t)AtomicOrdering::NotAtomic,
      GIM_CheckRegBankForClass, /*MI*/0, /*Op*/0, /*RC*/GIMT_Encode2(AMDGPU::SReg_64_XEXECRegClassID),
      // MIs[0] sbase
      GIM_CheckPointerToAny, /*MI*/0, /*Op*/1, /*SizeInBits*/64,
      GIM_CheckRegBankForClass, /*MI*/0, /*Op*/1, /*RC*/GIMT_Encode2(AMDGPU::SReg_64RegClassID),
      GIM_CheckCxxInsnPredicate, /*MI*/0, /*FnId*/GIMT_Encode2(GICXXPred_MI_Predicate_smrd_load),
      // (ld:{ *:[v4bf16] } SReg_64:{ *:[i64] }:$sbase)<<P:Predicate_unindexedload>><<P:Predicate_load>><<P:Predicate_smrd_load>>  =>  (S_LOAD_DWORDX2_IMM:{ *:[v4bf16] } i64:{ *:[i64] }:$sbase, 0:{ *:[i32] }, 0:{ *:[i32] })
      GIR_BuildMI, /*InsnID*/0, /*Opcode*/GIMT_Encode2(AMDGPU::S_LOAD_DWORDX2_IMM),
      GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/0, // DstI[sdst]
      GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/1, // sbase
      GIR_AddImm8, /*InsnID*/0, /*Imm*/0,
      GIR_AddImm8, /*InsnID*/0, /*Imm*/0,
      GIR_MergeMemOperands, /*InsnID*/0, /*NumInsns*/1, /*MergeInsnID's*/0,
      GIR_ConstrainSelectedInstOperands, /*InsnID*/0,
      GIR_EraseFromParent, /*InsnID*/0,
      // GIR_Coverage, 2547,
      GIR_Done,
    // Label 1439: @95502
    GIM_Try, /*On fail goto*//*Label 1440*/ GIMT_Encode4(95569), // Rule ID 3508 //
      GIM_CheckFeatures, GIMT_Encode2(GIFBS_EnableFlatScratch_HasFlatScratchInsts_HasFlatScratchSVSMode),
      GIM_CheckMemoryAddressSpace, /*MI*/0, /*MMO*/0, /*NumAddrSpace*/1, /*AddrSpace*/5,
      GIM_CheckAtomicOrdering, /*MI*/0, /*Order*/(uint8_t)AtomicOrdering::NotAtomic,
      GIM_CheckRegBankForClass, /*MI*/0, /*Op*/0, /*RC*/GIMT_Encode2(AMDGPU::AV_64RegClassID),
      GIM_CheckPointerToAny, /*MI*/0, /*Op*/1, /*SizeInBits*/0,
      GIM_CheckComplexPattern, /*MI*/0, /*Op*/1, /*Renderer*/GIMT_Encode2(0), GIMT_Encode2(GICP_gi_flat_scratch_svaddr),
      // (ld:{ *:[v4f16] } (ScratchSVAddr:{ *:[iPTR] } VGPR_32:{ *:[i32] }:$vaddr, SGPR_32:{ *:[i32] }:$saddr, i32:{ *:[i32] }:$offset))<<P:Predicate_unindexedload>><<P:Predicate_load_private>>  =>  (SCRATCH_LOAD_DWORDX2_SVS:{ *:[v4f16] } ?:{ *:[i32] }:$vaddr, ?:{ *:[i32] }:$saddr, ?:{ *:[i32] }:$offset, 0:{ *:[i32] })
      GIR_BuildMI, /*InsnID*/0, /*Opcode*/GIMT_Encode2(AMDGPU::SCRATCH_LOAD_DWORDX2_SVS),
      GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/0, // DstI[vdst]
      GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/0, // vaddr
      GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/1, // saddr
      GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/2, // offset
      GIR_AddImm8, /*InsnID*/0, /*Imm*/0,
      GIR_MergeMemOperands, /*InsnID*/0, /*NumInsns*/1, /*MergeInsnID's*/0,
      GIR_ConstrainSelectedInstOperands, /*InsnID*/0,
      GIR_EraseFromParent, /*InsnID*/0,
      // GIR_Coverage, 3508,
      GIR_Done,
    // Label 1440: @95569
    GIM_Try, /*On fail goto*//*Label 1441*/ GIMT_Encode4(95636), // Rule ID 3514 //
      GIM_CheckFeatures, GIMT_Encode2(GIFBS_EnableFlatScratch_HasFlatScratchInsts_HasFlatScratchSVSMode),
      GIM_CheckMemoryAddressSpace, /*MI*/0, /*MMO*/0, /*NumAddrSpace*/1, /*AddrSpace*/5,
      GIM_CheckAtomicOrdering, /*MI*/0, /*Order*/(uint8_t)AtomicOrdering::NotAtomic,
      GIM_CheckRegBankForClass, /*MI*/0, /*Op*/0, /*RC*/GIMT_Encode2(AMDGPU::AV_64RegClassID),
      GIM_CheckPointerToAny, /*MI*/0, /*Op*/1, /*SizeInBits*/0,
      GIM_CheckComplexPattern, /*MI*/0, /*Op*/1, /*Renderer*/GIMT_Encode2(0), GIMT_Encode2(GICP_gi_flat_scratch_svaddr),
      // (ld:{ *:[v4bf16] } (ScratchSVAddr:{ *:[iPTR] } VGPR_32:{ *:[i32] }:$vaddr, SGPR_32:{ *:[i32] }:$saddr, i32:{ *:[i32] }:$offset))<<P:Predicate_unindexedload>><<P:Predicate_load_private>>  =>  (SCRATCH_LOAD_DWORDX2_SVS:{ *:[v4bf16] } ?:{ *:[i32] }:$vaddr, ?:{ *:[i32] }:$saddr, ?:{ *:[i32] }:$offset, 0:{ *:[i32] })
      GIR_BuildMI, /*InsnID*/0, /*Opcode*/GIMT_Encode2(AMDGPU::SCRATCH_LOAD_DWORDX2_SVS),
      GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/0, // DstI[vdst]
      GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/0, // vaddr
      GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/1, // saddr
      GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/2, // offset
      GIR_AddImm8, /*InsnID*/0, /*Imm*/0,
      GIR_MergeMemOperands, /*InsnID*/0, /*NumInsns*/1, /*MergeInsnID's*/0,
      GIR_ConstrainSelectedInstOperands, /*InsnID*/0,
      GIR_EraseFromParent, /*InsnID*/0,
      // GIR_Coverage, 3514,
      GIR_Done,
    // Label 1441: @95636
    GIM_Try, /*On fail goto*//*Label 1442*/ GIMT_Encode4(95703), // Rule ID 3520 //
      GIM_CheckFeatures, GIMT_Encode2(GIFBS_EnableFlatScratch_HasFlatScratchInsts_HasFlatScratchSVSMode),
      GIM_CheckMemoryAddressSpace, /*MI*/0, /*MMO*/0, /*NumAddrSpace*/1, /*AddrSpace*/5,
      GIM_CheckAtomicOrdering, /*MI*/0, /*Order*/(uint8_t)AtomicOrdering::NotAtomic,
      GIM_CheckRegBankForClass, /*MI*/0, /*Op*/0, /*RC*/GIMT_Encode2(AMDGPU::AV_64RegClassID),
      GIM_CheckPointerToAny, /*MI*/0, /*Op*/1, /*SizeInBits*/0,
      GIM_CheckComplexPattern, /*MI*/0, /*Op*/1, /*Renderer*/GIMT_Encode2(0), GIMT_Encode2(GICP_gi_flat_scratch_svaddr),
      // (ld:{ *:[v4i16] } (ScratchSVAddr:{ *:[iPTR] } VGPR_32:{ *:[i32] }:$vaddr, SGPR_32:{ *:[i32] }:$saddr, i32:{ *:[i32] }:$offset))<<P:Predicate_unindexedload>><<P:Predicate_load_private>>  =>  (SCRATCH_LOAD_DWORDX2_SVS:{ *:[v4i16] } ?:{ *:[i32] }:$vaddr, ?:{ *:[i32] }:$saddr, ?:{ *:[i32] }:$offset, 0:{ *:[i32] })
      GIR_BuildMI, /*InsnID*/0, /*Opcode*/GIMT_Encode2(AMDGPU::SCRATCH_LOAD_DWORDX2_SVS),
      GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/0, // DstI[vdst]
      GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/0, // vaddr
      GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/1, // saddr
      GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/2, // offset
      GIR_AddImm8, /*InsnID*/0, /*Imm*/0,
      GIR_MergeMemOperands, /*InsnID*/0, /*NumInsns*/1, /*MergeInsnID's*/0,
      GIR_ConstrainSelectedInstOperands, /*InsnID*/0,
      GIR_EraseFromParent, /*InsnID*/0,
      // GIR_Coverage, 3520,
      GIR_Done,
    // Label 1442: @95703
    GIM_Try, /*On fail goto*//*Label 1443*/ GIMT_Encode4(95765), // Rule ID 3507 //
      GIM_CheckFeatures, GIMT_Encode2(GIFBS_EnableFlatScratch_HasFlatScratchInsts),
      GIM_CheckMemoryAddressSpace, /*MI*/0, /*MMO*/0, /*NumAddrSpace*/1, /*AddrSpace*/5,
      GIM_CheckAtomicOrdering, /*MI*/0, /*Order*/(uint8_t)AtomicOrdering::NotAtomic,
      GIM_CheckRegBankForClass, /*MI*/0, /*Op*/0, /*RC*/GIMT_Encode2(AMDGPU::AV_64RegClassID),
      GIM_CheckPointerToAny, /*MI*/0, /*Op*/1, /*SizeInBits*/0,
      GIM_CheckComplexPattern, /*MI*/0, /*Op*/1, /*Renderer*/GIMT_Encode2(0), GIMT_Encode2(GICP_gi_flat_scratch_saddr),
      // (ld:{ *:[v4f16] } (ScratchSAddr:{ *:[iPTR] } SGPR_32:{ *:[i32] }:$saddr, i32:{ *:[i32] }:$offset))<<P:Predicate_unindexedload>><<P:Predicate_load_private>>  =>  (SCRATCH_LOAD_DWORDX2_SADDR:{ *:[v4f16] } ?:{ *:[i32] }:$saddr, ?:{ *:[i32] }:$offset)
      GIR_BuildMI, /*InsnID*/0, /*Opcode*/GIMT_Encode2(AMDGPU::SCRATCH_LOAD_DWORDX2_SADDR),
      GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/0, // DstI[vdst]
      GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/0, // saddr
      GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/1, // offset
      GIR_AddImm8, /*InsnID*/0, /*Imm*/0,
      GIR_MergeMemOperands, /*InsnID*/0, /*NumInsns*/1, /*MergeInsnID's*/0,
      GIR_ConstrainSelectedInstOperands, /*InsnID*/0,
      GIR_EraseFromParent, /*InsnID*/0,
      // GIR_Coverage, 3507,
      GIR_Done,
    // Label 1443: @95765
    GIM_Try, /*On fail goto*//*Label 1444*/ GIMT_Encode4(95827), // Rule ID 3513 //
      GIM_CheckFeatures, GIMT_Encode2(GIFBS_EnableFlatScratch_HasFlatScratchInsts),
      GIM_CheckMemoryAddressSpace, /*MI*/0, /*MMO*/0, /*NumAddrSpace*/1, /*AddrSpace*/5,
      GIM_CheckAtomicOrdering, /*MI*/0, /*Order*/(uint8_t)AtomicOrdering::NotAtomic,
      GIM_CheckRegBankForClass, /*MI*/0, /*Op*/0, /*RC*/GIMT_Encode2(AMDGPU::AV_64RegClassID),
      GIM_CheckPointerToAny, /*MI*/0, /*Op*/1, /*SizeInBits*/0,
      GIM_CheckComplexPattern, /*MI*/0, /*Op*/1, /*Renderer*/GIMT_Encode2(0), GIMT_Encode2(GICP_gi_flat_scratch_saddr),
      // (ld:{ *:[v4bf16] } (ScratchSAddr:{ *:[iPTR] } SGPR_32:{ *:[i32] }:$saddr, i32:{ *:[i32] }:$offset))<<P:Predicate_unindexedload>><<P:Predicate_load_private>>  =>  (SCRATCH_LOAD_DWORDX2_SADDR:{ *:[v4bf16] } ?:{ *:[i32] }:$saddr, ?:{ *:[i32] }:$offset)
      GIR_BuildMI, /*InsnID*/0, /*Opcode*/GIMT_Encode2(AMDGPU::SCRATCH_LOAD_DWORDX2_SADDR),
      GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/0, // DstI[vdst]
      GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/0, // saddr
      GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/1, // offset
      GIR_AddImm8, /*InsnID*/0, /*Imm*/0,
      GIR_MergeMemOperands, /*InsnID*/0, /*NumInsns*/1, /*MergeInsnID's*/0,
      GIR_ConstrainSelectedInstOperands, /*InsnID*/0,
      GIR_EraseFromParent, /*InsnID*/0,
      // GIR_Coverage, 3513,
      GIR_Done,
    // Label 1444: @95827
    GIM_Try, /*On fail goto*//*Label 1445*/ GIMT_Encode4(95889), // Rule ID 3519 //
      GIM_CheckFeatures, GIMT_Encode2(GIFBS_EnableFlatScratch_HasFlatScratchInsts),
      GIM_CheckMemoryAddressSpace, /*MI*/0, /*MMO*/0, /*NumAddrSpace*/1, /*AddrSpace*/5,
      GIM_CheckAtomicOrdering, /*MI*/0, /*Order*/(uint8_t)AtomicOrdering::NotAtomic,
      GIM_CheckRegBankForClass, /*MI*/0, /*Op*/0, /*RC*/GIMT_Encode2(AMDGPU::AV_64RegClassID),
      GIM_CheckPointerToAny, /*MI*/0, /*Op*/1, /*SizeInBits*/0,
      GIM_CheckComplexPattern, /*MI*/0, /*Op*/1, /*Renderer*/GIMT_Encode2(0), GIMT_Encode2(GICP_gi_flat_scratch_saddr),
      // (ld:{ *:[v4i16] } (ScratchSAddr:{ *:[iPTR] } SGPR_32:{ *:[i32] }:$saddr, i32:{ *:[i32] }:$offset))<<P:Predicate_unindexedload>><<P:Predicate_load_private>>  =>  (SCRATCH_LOAD_DWORDX2_SADDR:{ *:[v4i16] } ?:{ *:[i32] }:$saddr, ?:{ *:[i32] }:$offset)
      GIR_BuildMI, /*InsnID*/0, /*Opcode*/GIMT_Encode2(AMDGPU::SCRATCH_LOAD_DWORDX2_SADDR),
      GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/0, // DstI[vdst]
      GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/0, // saddr
      GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/1, // offset
      GIR_AddImm8, /*InsnID*/0, /*Imm*/0,
      GIR_MergeMemOperands, /*InsnID*/0, /*NumInsns*/1, /*MergeInsnID's*/0,
      GIR_ConstrainSelectedInstOperands, /*InsnID*/0,
      GIR_EraseFromParent, /*InsnID*/0,
      // GIR_Coverage, 3519,
      GIR_Done,
    // Label 1445: @95889
    GIM_Try, /*On fail goto*//*Label 1446*/ GIMT_Encode4(95951), // Rule ID 3506 //
      GIM_CheckFeatures, GIMT_Encode2(GIFBS_EnableFlatScratch_HasFlatScratchInsts),
      GIM_CheckMemoryAddressSpace, /*MI*/0, /*MMO*/0, /*NumAddrSpace*/1, /*AddrSpace*/5,
      GIM_CheckAtomicOrdering, /*MI*/0, /*Order*/(uint8_t)AtomicOrdering::NotAtomic,
      GIM_CheckRegBankForClass, /*MI*/0, /*Op*/0, /*RC*/GIMT_Encode2(AMDGPU::AV_64RegClassID),
      GIM_CheckPointerToAny, /*MI*/0, /*Op*/1, /*SizeInBits*/0,
      GIM_CheckComplexPattern, /*MI*/0, /*Op*/1, /*Renderer*/GIMT_Encode2(0), GIMT_Encode2(GICP_gi_flat_scratch_offset),
      // (ld:{ *:[v4f16] } (ScratchOffset:{ *:[iPTR] } VGPR_32:{ *:[i32] }:$vaddr, i32:{ *:[i32] }:$offset))<<P:Predicate_unindexedload>><<P:Predicate_load_private>>  =>  (SCRATCH_LOAD_DWORDX2:{ *:[v4f16] } ?:{ *:[i32] }:$vaddr, ?:{ *:[i32] }:$offset)
      GIR_BuildMI, /*InsnID*/0, /*Opcode*/GIMT_Encode2(AMDGPU::SCRATCH_LOAD_DWORDX2),
      GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/0, // DstI[vdst]
      GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/0, // vaddr
      GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/1, // offset
      GIR_AddImm8, /*InsnID*/0, /*Imm*/0,
      GIR_MergeMemOperands, /*InsnID*/0, /*NumInsns*/1, /*MergeInsnID's*/0,
      GIR_ConstrainSelectedInstOperands, /*InsnID*/0,
      GIR_EraseFromParent, /*InsnID*/0,
      // GIR_Coverage, 3506,
      GIR_Done,
    // Label 1446: @95951
    GIM_Try, /*On fail goto*//*Label 1447*/ GIMT_Encode4(96013), // Rule ID 3512 //
      GIM_CheckFeatures, GIMT_Encode2(GIFBS_EnableFlatScratch_HasFlatScratchInsts),
      GIM_CheckMemoryAddressSpace, /*MI*/0, /*MMO*/0, /*NumAddrSpace*/1, /*AddrSpace*/5,
      GIM_CheckAtomicOrdering, /*MI*/0, /*Order*/(uint8_t)AtomicOrdering::NotAtomic,
      GIM_CheckRegBankForClass, /*MI*/0, /*Op*/0, /*RC*/GIMT_Encode2(AMDGPU::AV_64RegClassID),
      GIM_CheckPointerToAny, /*MI*/0, /*Op*/1, /*SizeInBits*/0,
      GIM_CheckComplexPattern, /*MI*/0, /*Op*/1, /*Renderer*/GIMT_Encode2(0), GIMT_Encode2(GICP_gi_flat_scratch_offset),
      // (ld:{ *:[v4bf16] } (ScratchOffset:{ *:[iPTR] } VGPR_32:{ *:[i32] }:$vaddr, i32:{ *:[i32] }:$offset))<<P:Predicate_unindexedload>><<P:Predicate_load_private>>  =>  (SCRATCH_LOAD_DWORDX2:{ *:[v4bf16] } ?:{ *:[i32] }:$vaddr, ?:{ *:[i32] }:$offset)
      GIR_BuildMI, /*InsnID*/0, /*Opcode*/GIMT_Encode2(AMDGPU::SCRATCH_LOAD_DWORDX2),
      GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/0, // DstI[vdst]
      GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/0, // vaddr
      GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/1, // offset
      GIR_AddImm8, /*InsnID*/0, /*Imm*/0,
      GIR_MergeMemOperands, /*InsnID*/0, /*NumInsns*/1, /*MergeInsnID's*/0,
      GIR_ConstrainSelectedInstOperands, /*InsnID*/0,
      GIR_EraseFromParent, /*InsnID*/0,
      // GIR_Coverage, 3512,
      GIR_Done,
    // Label 1447: @96013
    GIM_Try, /*On fail goto*//*Label 1448*/ GIMT_Encode4(96075), // Rule ID 3518 //
      GIM_CheckFeatures, GIMT_Encode2(GIFBS_EnableFlatScratch_HasFlatScratchInsts),
      GIM_CheckMemoryAddressSpace, /*MI*/0, /*MMO*/0, /*NumAddrSpace*/1, /*AddrSpace*/5,
      GIM_CheckAtomicOrdering, /*MI*/0, /*Order*/(uint8_t)AtomicOrdering::NotAtomic,
      GIM_CheckRegBankForClass, /*MI*/0, /*Op*/0, /*RC*/GIMT_Encode2(AMDGPU::AV_64RegClassID),
      GIM_CheckPointerToAny, /*MI*/0, /*Op*/1, /*SizeInBits*/0,
      GIM_CheckComplexPattern, /*MI*/0, /*Op*/1, /*Renderer*/GIMT_Encode2(0), GIMT_Encode2(GICP_gi_flat_scratch_offset),
      // (ld:{ *:[v4i16] } (ScratchOffset:{ *:[iPTR] } VGPR_32:{ *:[i32] }:$vaddr, i32:{ *:[i32] }:$offset))<<P:Predicate_unindexedload>><<P:Predicate_load_private>>  =>  (SCRATCH_LOAD_DWORDX2:{ *:[v4i16] } ?:{ *:[i32] }:$vaddr, ?:{ *:[i32] }:$offset)
      GIR_BuildMI, /*InsnID*/0, /*Opcode*/GIMT_Encode2(AMDGPU::SCRATCH_LOAD_DWORDX2),
      GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/0, // DstI[vdst]
      GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/0, // vaddr
      GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/1, // offset
      GIR_AddImm8, /*InsnID*/0, /*Imm*/0,
      GIR_MergeMemOperands, /*InsnID*/0, /*NumInsns*/1, /*MergeInsnID's*/0,
      GIR_ConstrainSelectedInstOperands, /*InsnID*/0,
      GIR_EraseFromParent, /*InsnID*/0,
      // GIR_Coverage, 3518,
      GIR_Done,
    // Label 1448: @96075
    GIM_Try, /*On fail goto*//*Label 1449*/ GIMT_Encode4(96152), // Rule ID 3736 //
      GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasUnrestrictedSOffset),
      GIM_CheckMemoryAddressSpace, /*MI*/0, /*MMO*/0, /*NumAddrSpace*/3, /*AddrSpace*/1, /*AddrSpace*/4, /*AddrSpace*/6,
      GIM_CheckAtomicOrdering, /*MI*/0, /*Order*/(uint8_t)AtomicOrdering::NotAtomic,
      GIM_CheckRegBankForClass, /*MI*/0, /*Op*/0, /*RC*/GIMT_Encode2(AMDGPU::AV_64RegClassID),
      GIM_CheckPointerToAny, /*MI*/0, /*Op*/1, /*SizeInBits*/0,
      GIM_CheckComplexPattern, /*MI*/0, /*Op*/1, /*Renderer*/GIMT_Encode2(0), GIMT_Encode2(GICP_gi_mubuf_addr64),
      // (ld:{ *:[v4f16] } (MUBUFAddr64:{ *:[iPTR] } v4i32:{ *:[v4i32] }:$srsrc, i64:{ *:[i64] }:$vaddr, i32:{ *:[i32] }:$soffset, i32:{ *:[i32] }:$offset))<<P:Predicate_unindexedload>><<P:Predicate_load_global>>  =>  (BUFFER_LOAD_DWORDX2_ADDR64:{ *:[v4f16] } i64:{ *:[i64] }:$vaddr, v4i32:{ *:[v4i32] }:$srsrc, i32:{ *:[i32] }:$soffset, i32:{ *:[i32] }:$offset)
      GIR_BuildMI, /*InsnID*/0, /*Opcode*/GIMT_Encode2(AMDGPU::BUFFER_LOAD_DWORDX2_ADDR64),
      GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/0, // DstI[vdata]
      GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/1, // vaddr
      GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/0, // srsrc
      GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/2, // soffset
      GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/3, // offset
      GIR_AddImm8, /*InsnID*/0, /*Imm*/0,
      GIR_AddImm8, /*InsnID*/0, /*Imm*/0,
      GIR_MergeMemOperands, /*InsnID*/0, /*NumInsns*/1, /*MergeInsnID's*/0,
      GIR_ConstrainSelectedInstOperands, /*InsnID*/0,
      GIR_EraseFromParent, /*InsnID*/0,
      // GIR_Coverage, 3736,
      GIR_Done,
    // Label 1449: @96152
    GIM_Try, /*On fail goto*//*Label 1450*/ GIMT_Encode4(96226), // Rule ID 3738 //
      GIM_CheckMemoryAddressSpace, /*MI*/0, /*MMO*/0, /*NumAddrSpace*/3, /*AddrSpace*/1, /*AddrSpace*/4, /*AddrSpace*/6,
      GIM_CheckAtomicOrdering, /*MI*/0, /*Order*/(uint8_t)AtomicOrdering::NotAtomic,
      GIM_CheckRegBankForClass, /*MI*/0, /*Op*/0, /*RC*/GIMT_Encode2(AMDGPU::AV_64RegClassID),
      GIM_CheckPointerToAny, /*MI*/0, /*Op*/1, /*SizeInBits*/0,
      GIM_CheckComplexPattern, /*MI*/0, /*Op*/1, /*Renderer*/GIMT_Encode2(0), GIMT_Encode2(GICP_gi_mubuf_addr64),
      // (ld:{ *:[v4f16] } (MUBUFAddr64:{ *:[iPTR] } v4i32:{ *:[v4i32] }:$srsrc, i64:{ *:[i64] }:$vaddr, i32:{ *:[i32] }:$soffset, i32:{ *:[i32] }:$offset))<<P:Predicate_unindexedload>><<P:Predicate_load_global>>  =>  (BUFFER_LOAD_DWORDX2_VBUFFER_ADDR64:{ *:[v4f16] } i64:{ *:[i64] }:$vaddr, v4i32:{ *:[v4i32] }:$srsrc, i32:{ *:[i32] }:$soffset, i32:{ *:[i32] }:$offset)
      GIR_BuildMI, /*InsnID*/0, /*Opcode*/GIMT_Encode2(AMDGPU::BUFFER_LOAD_DWORDX2_VBUFFER_ADDR64),
      GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/0, // DstI[vdata]
      GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/1, // vaddr
      GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/0, // srsrc
      GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/2, // soffset
      GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/3, // offset
      GIR_AddImm8, /*InsnID*/0, /*Imm*/0,
      GIR_AddImm8, /*InsnID*/0, /*Imm*/0,
      GIR_MergeMemOperands, /*InsnID*/0, /*NumInsns*/1, /*MergeInsnID's*/0,
      GIR_ConstrainSelectedInstOperands, /*InsnID*/0,
      GIR_EraseFromParent, /*InsnID*/0,
      // GIR_Coverage, 3738,
      GIR_Done,
    // Label 1450: @96226
    GIM_Try, /*On fail goto*//*Label 1451*/ GIMT_Encode4(96303), // Rule ID 3740 //
      GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasUnrestrictedSOffset),
      GIM_CheckMemoryAddressSpace, /*MI*/0, /*MMO*/0, /*NumAddrSpace*/3, /*AddrSpace*/1, /*AddrSpace*/4, /*AddrSpace*/6,
      GIM_CheckAtomicOrdering, /*MI*/0, /*Order*/(uint8_t)AtomicOrdering::NotAtomic,
      GIM_CheckRegBankForClass, /*MI*/0, /*Op*/0, /*RC*/GIMT_Encode2(AMDGPU::AV_64RegClassID),
      GIM_CheckPointerToAny, /*MI*/0, /*Op*/1, /*SizeInBits*/0,
      GIM_CheckComplexPattern, /*MI*/0, /*Op*/1, /*Renderer*/GIMT_Encode2(0), GIMT_Encode2(GICP_gi_mubuf_addr64),
      // (ld:{ *:[v4bf16] } (MUBUFAddr64:{ *:[iPTR] } v4i32:{ *:[v4i32] }:$srsrc, i64:{ *:[i64] }:$vaddr, i32:{ *:[i32] }:$soffset, i32:{ *:[i32] }:$offset))<<P:Predicate_unindexedload>><<P:Predicate_load_global>>  =>  (BUFFER_LOAD_DWORDX2_ADDR64:{ *:[v4bf16] } i64:{ *:[i64] }:$vaddr, v4i32:{ *:[v4i32] }:$srsrc, i32:{ *:[i32] }:$soffset, i32:{ *:[i32] }:$offset)
      GIR_BuildMI, /*InsnID*/0, /*Opcode*/GIMT_Encode2(AMDGPU::BUFFER_LOAD_DWORDX2_ADDR64),
      GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/0, // DstI[vdata]
      GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/1, // vaddr
      GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/0, // srsrc
      GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/2, // soffset
      GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/3, // offset
      GIR_AddImm8, /*InsnID*/0, /*Imm*/0,
      GIR_AddImm8, /*InsnID*/0, /*Imm*/0,
      GIR_MergeMemOperands, /*InsnID*/0, /*NumInsns*/1, /*MergeInsnID's*/0,
      GIR_ConstrainSelectedInstOperands, /*InsnID*/0,
      GIR_EraseFromParent, /*InsnID*/0,
      // GIR_Coverage, 3740,
      GIR_Done,
    // Label 1451: @96303
    GIM_Try, /*On fail goto*//*Label 1452*/ GIMT_Encode4(96377), // Rule ID 3742 //
      GIM_CheckMemoryAddressSpace, /*MI*/0, /*MMO*/0, /*NumAddrSpace*/3, /*AddrSpace*/1, /*AddrSpace*/4, /*AddrSpace*/6,
      GIM_CheckAtomicOrdering, /*MI*/0, /*Order*/(uint8_t)AtomicOrdering::NotAtomic,
      GIM_CheckRegBankForClass, /*MI*/0, /*Op*/0, /*RC*/GIMT_Encode2(AMDGPU::AV_64RegClassID),
      GIM_CheckPointerToAny, /*MI*/0, /*Op*/1, /*SizeInBits*/0,
      GIM_CheckComplexPattern, /*MI*/0, /*Op*/1, /*Renderer*/GIMT_Encode2(0), GIMT_Encode2(GICP_gi_mubuf_addr64),
      // (ld:{ *:[v4bf16] } (MUBUFAddr64:{ *:[iPTR] } v4i32:{ *:[v4i32] }:$srsrc, i64:{ *:[i64] }:$vaddr, i32:{ *:[i32] }:$soffset, i32:{ *:[i32] }:$offset))<<P:Predicate_unindexedload>><<P:Predicate_load_global>>  =>  (BUFFER_LOAD_DWORDX2_VBUFFER_ADDR64:{ *:[v4bf16] } i64:{ *:[i64] }:$vaddr, v4i32:{ *:[v4i32] }:$srsrc, i32:{ *:[i32] }:$soffset, i32:{ *:[i32] }:$offset)
      GIR_BuildMI, /*InsnID*/0, /*Opcode*/GIMT_Encode2(AMDGPU::BUFFER_LOAD_DWORDX2_VBUFFER_ADDR64),
      GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/0, // DstI[vdata]
      GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/1, // vaddr
      GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/0, // srsrc
      GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/2, // soffset
      GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/3, // offset
      GIR_AddImm8, /*InsnID*/0, /*Imm*/0,
      GIR_AddImm8, /*InsnID*/0, /*Imm*/0,
      GIR_MergeMemOperands, /*InsnID*/0, /*NumInsns*/1, /*MergeInsnID's*/0,
      GIR_ConstrainSelectedInstOperands, /*InsnID*/0,
      GIR_EraseFromParent, /*InsnID*/0,
      // GIR_Coverage, 3742,
      GIR_Done,
    // Label 1452: @96377
    GIM_Try, /*On fail goto*//*Label 1453*/ GIMT_Encode4(96454), // Rule ID 3744 //
      GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasUnrestrictedSOffset),
      GIM_CheckMemoryAddressSpace, /*MI*/0, /*MMO*/0, /*NumAddrSpace*/3, /*AddrSpace*/1, /*AddrSpace*/4, /*AddrSpace*/6,
      GIM_CheckAtomicOrdering, /*MI*/0, /*Order*/(uint8_t)AtomicOrdering::NotAtomic,
      GIM_CheckRegBankForClass, /*MI*/0, /*Op*/0, /*RC*/GIMT_Encode2(AMDGPU::AV_64RegClassID),
      GIM_CheckPointerToAny, /*MI*/0, /*Op*/1, /*SizeInBits*/0,
      GIM_CheckComplexPattern, /*MI*/0, /*Op*/1, /*Renderer*/GIMT_Encode2(0), GIMT_Encode2(GICP_gi_mubuf_addr64),
      // (ld:{ *:[v4i16] } (MUBUFAddr64:{ *:[iPTR] } v4i32:{ *:[v4i32] }:$srsrc, i64:{ *:[i64] }:$vaddr, i32:{ *:[i32] }:$soffset, i32:{ *:[i32] }:$offset))<<P:Predicate_unindexedload>><<P:Predicate_load_global>>  =>  (BUFFER_LOAD_DWORDX2_ADDR64:{ *:[v4i16] } i64:{ *:[i64] }:$vaddr, v4i32:{ *:[v4i32] }:$srsrc, i32:{ *:[i32] }:$soffset, i32:{ *:[i32] }:$offset)
      GIR_BuildMI, /*InsnID*/0, /*Opcode*/GIMT_Encode2(AMDGPU::BUFFER_LOAD_DWORDX2_ADDR64),
      GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/0, // DstI[vdata]
      GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/1, // vaddr
      GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/0, // srsrc
      GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/2, // soffset
      GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/3, // offset
      GIR_AddImm8, /*InsnID*/0, /*Imm*/0,
      GIR_AddImm8, /*InsnID*/0, /*Imm*/0,
      GIR_MergeMemOperands, /*InsnID*/0, /*NumInsns*/1, /*MergeInsnID's*/0,
      GIR_ConstrainSelectedInstOperands, /*InsnID*/0,
      GIR_EraseFromParent, /*InsnID*/0,
      // GIR_Coverage, 3744,
      GIR_Done,
    // Label 1453: @96454
    GIM_Try, /*On fail goto*//*Label 1454*/ GIMT_Encode4(96528), // Rule ID 3746 //
      GIM_CheckMemoryAddressSpace, /*MI*/0, /*MMO*/0, /*NumAddrSpace*/3, /*AddrSpace*/1, /*AddrSpace*/4, /*AddrSpace*/6,
      GIM_CheckAtomicOrdering, /*MI*/0, /*Order*/(uint8_t)AtomicOrdering::NotAtomic,
      GIM_CheckRegBankForClass, /*MI*/0, /*Op*/0, /*RC*/GIMT_Encode2(AMDGPU::AV_64RegClassID),
      GIM_CheckPointerToAny, /*MI*/0, /*Op*/1, /*SizeInBits*/0,
      GIM_CheckComplexPattern, /*MI*/0, /*Op*/1, /*Renderer*/GIMT_Encode2(0), GIMT_Encode2(GICP_gi_mubuf_addr64),
      // (ld:{ *:[v4i16] } (MUBUFAddr64:{ *:[iPTR] } v4i32:{ *:[v4i32] }:$srsrc, i64:{ *:[i64] }:$vaddr, i32:{ *:[i32] }:$soffset, i32:{ *:[i32] }:$offset))<<P:Predicate_unindexedload>><<P:Predicate_load_global>>  =>  (BUFFER_LOAD_DWORDX2_VBUFFER_ADDR64:{ *:[v4i16] } i64:{ *:[i64] }:$vaddr, v4i32:{ *:[v4i32] }:$srsrc, i32:{ *:[i32] }:$soffset, i32:{ *:[i32] }:$offset)
      GIR_BuildMI, /*InsnID*/0, /*Opcode*/GIMT_Encode2(AMDGPU::BUFFER_LOAD_DWORDX2_VBUFFER_ADDR64),
      GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/0, // DstI[vdata]
      GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/1, // vaddr
      GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/0, // srsrc
      GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/2, // soffset
      GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/3, // offset
      GIR_AddImm8, /*InsnID*/0, /*Imm*/0,
      GIR_AddImm8, /*InsnID*/0, /*Imm*/0,
      GIR_MergeMemOperands, /*InsnID*/0, /*NumInsns*/1, /*MergeInsnID's*/0,
      GIR_ConstrainSelectedInstOperands, /*InsnID*/0,
      GIR_EraseFromParent, /*InsnID*/0,
      // GIR_Coverage, 3746,
      GIR_Done,
    // Label 1454: @96528
    GIM_Try, /*On fail goto*//*Label 1455*/ GIMT_Encode4(96599), // Rule ID 6691 //
      GIM_CheckFeatures, GIMT_Encode2(GIFBS_LDSRequiresM0Init_isGFX7Plus),
      GIM_CheckMemorySizeEqualToLLT, /*MI*/0, /*MMO*/0, /*OpIdx*/0,
      GIM_CheckMemoryAddressSpace, /*MI*/0, /*MMO*/0, /*NumAddrSpace*/1, /*AddrSpace*/3,
      GIM_CheckAtomicOrdering, /*MI*/0, /*Order*/(uint8_t)AtomicOrdering::NotAtomic,
      GIM_CheckRegBankForClass, /*MI*/0, /*Op*/0, /*RC*/GIMT_Encode2(AMDGPU::AV_64RegClassID),
      GIM_CheckPointerToAny, /*MI*/0, /*Op*/1, /*SizeInBits*/0,
      GIM_CheckComplexPattern, /*MI*/0, /*Op*/1, /*Renderer*/GIMT_Encode2(0), GIMT_Encode2(GICP_gi_ds_64bit_4byte_aligned),
      // (AMDGPUld_glue:{ *:[v4f16] } (DS64Bit4ByteAligned:{ *:[iPTR] } i32:{ *:[i32] }:$ptr, i8:{ *:[i8] }:$offset0, i8:{ *:[i8] }:$offset1))<<P:Predicate_unindexedload_glue>><<P:Predicate_load_glue>><<P:Predicate_load_local_m0>>  =>  (DS_READ2_B32:{ *:[v4f16] } ?:{ *:[i32] }:$ptr, ?:{ *:[i8] }:$offset0, ?:{ *:[i8] }:$offset1, 0:{ *:[i1] })
      GIR_BuildMI, /*InsnID*/0, /*Opcode*/GIMT_Encode2(AMDGPU::DS_READ2_B32),
      GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/0, // DstI[vdst]
      GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/0, // ptr
      GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/1, // offset0
      GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/2, // offset1
      GIR_AddImm8, /*InsnID*/0, /*Imm*/0,
      GIR_MergeMemOperands, /*InsnID*/0, /*NumInsns*/1, /*MergeInsnID's*/0,
      GIR_ConstrainSelectedInstOperands, /*InsnID*/0,
      GIR_EraseFromParent, /*InsnID*/0,
      // GIR_Coverage, 6691,
      GIR_Done,
    // Label 1455: @96599
    GIM_Try, /*On fail goto*//*Label 1456*/ GIMT_Encode4(96670), // Rule ID 6695 //
      GIM_CheckFeatures, GIMT_Encode2(GIFBS_LDSRequiresM0Init_isGFX7Plus),
      GIM_CheckMemorySizeEqualToLLT, /*MI*/0, /*MMO*/0, /*OpIdx*/0,
      GIM_CheckMemoryAddressSpace, /*MI*/0, /*MMO*/0, /*NumAddrSpace*/1, /*AddrSpace*/3,
      GIM_CheckAtomicOrdering, /*MI*/0, /*Order*/(uint8_t)AtomicOrdering::NotAtomic,
      GIM_CheckRegBankForClass, /*MI*/0, /*Op*/0, /*RC*/GIMT_Encode2(AMDGPU::AV_64RegClassID),
      GIM_CheckPointerToAny, /*MI*/0, /*Op*/1, /*SizeInBits*/0,
      GIM_CheckComplexPattern, /*MI*/0, /*Op*/1, /*Renderer*/GIMT_Encode2(0), GIMT_Encode2(GICP_gi_ds_64bit_4byte_aligned),
      // (AMDGPUld_glue:{ *:[v4bf16] } (DS64Bit4ByteAligned:{ *:[iPTR] } i32:{ *:[i32] }:$ptr, i8:{ *:[i8] }:$offset0, i8:{ *:[i8] }:$offset1))<<P:Predicate_unindexedload_glue>><<P:Predicate_load_glue>><<P:Predicate_load_local_m0>>  =>  (DS_READ2_B32:{ *:[v4bf16] } ?:{ *:[i32] }:$ptr, ?:{ *:[i8] }:$offset0, ?:{ *:[i8] }:$offset1, 0:{ *:[i1] })
      GIR_BuildMI, /*InsnID*/0, /*Opcode*/GIMT_Encode2(AMDGPU::DS_READ2_B32),
      GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/0, // DstI[vdst]
      GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/0, // ptr
      GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/1, // offset0
      GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/2, // offset1
      GIR_AddImm8, /*InsnID*/0, /*Imm*/0,
      GIR_MergeMemOperands, /*InsnID*/0, /*NumInsns*/1, /*MergeInsnID's*/0,
      GIR_ConstrainSelectedInstOperands, /*InsnID*/0,
      GIR_EraseFromParent, /*InsnID*/0,
      // GIR_Coverage, 6695,
      GIR_Done,
    // Label 1456: @96670
    GIM_Try, /*On fail goto*//*Label 1457*/ GIMT_Encode4(96741), // Rule ID 6699 //
      GIM_CheckFeatures, GIMT_Encode2(GIFBS_LDSRequiresM0Init_isGFX7Plus),
      GIM_CheckMemorySizeEqualToLLT, /*MI*/0, /*MMO*/0, /*OpIdx*/0,
      GIM_CheckMemoryAddressSpace, /*MI*/0, /*MMO*/0, /*NumAddrSpace*/1, /*AddrSpace*/3,
      GIM_CheckAtomicOrdering, /*MI*/0, /*Order*/(uint8_t)AtomicOrdering::NotAtomic,
      GIM_CheckRegBankForClass, /*MI*/0, /*Op*/0, /*RC*/GIMT_Encode2(AMDGPU::AV_64RegClassID),
      GIM_CheckPointerToAny, /*MI*/0, /*Op*/1, /*SizeInBits*/0,
      GIM_CheckComplexPattern, /*MI*/0, /*Op*/1, /*Renderer*/GIMT_Encode2(0), GIMT_Encode2(GICP_gi_ds_64bit_4byte_aligned),
      // (AMDGPUld_glue:{ *:[v4i16] } (DS64Bit4ByteAligned:{ *:[iPTR] } i32:{ *:[i32] }:$ptr, i8:{ *:[i8] }:$offset0, i8:{ *:[i8] }:$offset1))<<P:Predicate_unindexedload_glue>><<P:Predicate_load_glue>><<P:Predicate_load_local_m0>>  =>  (DS_READ2_B32:{ *:[v4i16] } ?:{ *:[i32] }:$ptr, ?:{ *:[i8] }:$offset0, ?:{ *:[i8] }:$offset1, 0:{ *:[i1] })
      GIR_BuildMI, /*InsnID*/0, /*Opcode*/GIMT_Encode2(AMDGPU::DS_READ2_B32),
      GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/0, // DstI[vdst]
      GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/0, // ptr
      GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/1, // offset0
      GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/2, // offset1
      GIR_AddImm8, /*InsnID*/0, /*Imm*/0,
      GIR_MergeMemOperands, /*InsnID*/0, /*NumInsns*/1, /*MergeInsnID's*/0,
      GIR_ConstrainSelectedInstOperands, /*InsnID*/0,
      GIR_EraseFromParent, /*InsnID*/0,
      // GIR_Coverage, 6699,
      GIR_Done,
    // Label 1457: @96741
    GIM_Try, /*On fail goto*//*Label 1458*/ GIMT_Encode4(96813), // Rule ID 3735 //
      GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasUnrestrictedSOffset),
      GIM_CheckMemoryAddressSpace, /*MI*/0, /*MMO*/0, /*NumAddrSpace*/3, /*AddrSpace*/1, /*AddrSpace*/4, /*AddrSpace*/6,
      GIM_CheckAtomicOrdering, /*MI*/0, /*Order*/(uint8_t)AtomicOrdering::NotAtomic,
      GIM_CheckRegBankForClass, /*MI*/0, /*Op*/0, /*RC*/GIMT_Encode2(AMDGPU::AV_64RegClassID),
      GIM_CheckPointerToAny, /*MI*/0, /*Op*/1, /*SizeInBits*/0,
      GIM_CheckComplexPattern, /*MI*/0, /*Op*/1, /*Renderer*/GIMT_Encode2(0), GIMT_Encode2(GICP_gi_mubuf_offset),
      // (ld:{ *:[v4f16] } (MUBUFOffset:{ *:[iPTR] } v4i32:{ *:[v4i32] }:$srsrc, i32:{ *:[i32] }:$soffset, i32:{ *:[i32] }:$offset))<<P:Predicate_unindexedload>><<P:Predicate_load_global>>  =>  (BUFFER_LOAD_DWORDX2_OFFSET:{ *:[v4f16] } v4i32:{ *:[v4i32] }:$srsrc, i32:{ *:[i32] }:$soffset, i32:{ *:[i32] }:$offset)
      GIR_BuildMI, /*InsnID*/0, /*Opcode*/GIMT_Encode2(AMDGPU::BUFFER_LOAD_DWORDX2_OFFSET),
      GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/0, // DstI[vdata]
      GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/0, // srsrc
      GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/1, // soffset
      GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/2, // offset
      GIR_AddImm8, /*InsnID*/0, /*Imm*/0,
      GIR_AddImm8, /*InsnID*/0, /*Imm*/0,
      GIR_MergeMemOperands, /*InsnID*/0, /*NumInsns*/1, /*MergeInsnID's*/0,
      GIR_ConstrainSelectedInstOperands, /*InsnID*/0,
      GIR_EraseFromParent, /*InsnID*/0,
      // GIR_Coverage, 3735,
      GIR_Done,
    // Label 1458: @96813
    GIM_Try, /*On fail goto*//*Label 1459*/ GIMT_Encode4(96882), // Rule ID 3737 //
      GIM_CheckMemoryAddressSpace, /*MI*/0, /*MMO*/0, /*NumAddrSpace*/3, /*AddrSpace*/1, /*AddrSpace*/4, /*AddrSpace*/6,
      GIM_CheckAtomicOrdering, /*MI*/0, /*Order*/(uint8_t)AtomicOrdering::NotAtomic,
      GIM_CheckRegBankForClass, /*MI*/0, /*Op*/0, /*RC*/GIMT_Encode2(AMDGPU::AV_64RegClassID),
      GIM_CheckPointerToAny, /*MI*/0, /*Op*/1, /*SizeInBits*/0,
      GIM_CheckComplexPattern, /*MI*/0, /*Op*/1, /*Renderer*/GIMT_Encode2(0), GIMT_Encode2(GICP_gi_mubuf_offset),
      // (ld:{ *:[v4f16] } (MUBUFOffset:{ *:[iPTR] } v4i32:{ *:[v4i32] }:$srsrc, i32:{ *:[i32] }:$soffset, i32:{ *:[i32] }:$offset))<<P:Predicate_unindexedload>><<P:Predicate_load_global>>  =>  (BUFFER_LOAD_DWORDX2_VBUFFER_OFFSET:{ *:[v4f16] } v4i32:{ *:[v4i32] }:$srsrc, i32:{ *:[i32] }:$soffset, i32:{ *:[i32] }:$offset)
      GIR_BuildMI, /*InsnID*/0, /*Opcode*/GIMT_Encode2(AMDGPU::BUFFER_LOAD_DWORDX2_VBUFFER_OFFSET),
      GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/0, // DstI[vdata]
      GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/0, // srsrc
      GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/1, // soffset
      GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/2, // offset
      GIR_AddImm8, /*InsnID*/0, /*Imm*/0,
      GIR_AddImm8, /*InsnID*/0, /*Imm*/0,
      GIR_MergeMemOperands, /*InsnID*/0, /*NumInsns*/1, /*MergeInsnID's*/0,
      GIR_ConstrainSelectedInstOperands, /*InsnID*/0,
      GIR_EraseFromParent, /*InsnID*/0,
      // GIR_Coverage, 3737,
      GIR_Done,
    // Label 1459: @96882
    GIM_Try, /*On fail goto*//*Label 1460*/ GIMT_Encode4(96954), // Rule ID 3739 //
      GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasUnrestrictedSOffset),
      GIM_CheckMemoryAddressSpace, /*MI*/0, /*MMO*/0, /*NumAddrSpace*/3, /*AddrSpace*/1, /*AddrSpace*/4, /*AddrSpace*/6,
      GIM_CheckAtomicOrdering, /*MI*/0, /*Order*/(uint8_t)AtomicOrdering::NotAtomic,
      GIM_CheckRegBankForClass, /*MI*/0, /*Op*/0, /*RC*/GIMT_Encode2(AMDGPU::AV_64RegClassID),
      GIM_CheckPointerToAny, /*MI*/0, /*Op*/1, /*SizeInBits*/0,
      GIM_CheckComplexPattern, /*MI*/0, /*Op*/1, /*Renderer*/GIMT_Encode2(0), GIMT_Encode2(GICP_gi_mubuf_offset),
      // (ld:{ *:[v4bf16] } (MUBUFOffset:{ *:[iPTR] } v4i32:{ *:[v4i32] }:$srsrc, i32:{ *:[i32] }:$soffset, i32:{ *:[i32] }:$offset))<<P:Predicate_unindexedload>><<P:Predicate_load_global>>  =>  (BUFFER_LOAD_DWORDX2_OFFSET:{ *:[v4bf16] } v4i32:{ *:[v4i32] }:$srsrc, i32:{ *:[i32] }:$soffset, i32:{ *:[i32] }:$offset)
      GIR_BuildMI, /*InsnID*/0, /*Opcode*/GIMT_Encode2(AMDGPU::BUFFER_LOAD_DWORDX2_OFFSET),
      GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/0, // DstI[vdata]
      GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/0, // srsrc
      GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/1, // soffset
      GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/2, // offset
      GIR_AddImm8, /*InsnID*/0, /*Imm*/0,
      GIR_AddImm8, /*InsnID*/0, /*Imm*/0,
      GIR_MergeMemOperands, /*InsnID*/0, /*NumInsns*/1, /*MergeInsnID's*/0,
      GIR_ConstrainSelectedInstOperands, /*InsnID*/0,
      GIR_EraseFromParent, /*InsnID*/0,
      // GIR_Coverage, 3739,
      GIR_Done,
    // Label 1460: @96954
    GIM_Try, /*On fail goto*//*Label 1461*/ GIMT_Encode4(97023), // Rule ID 3741 //
      GIM_CheckMemoryAddressSpace, /*MI*/0, /*MMO*/0, /*NumAddrSpace*/3, /*AddrSpace*/1, /*AddrSpace*/4, /*AddrSpace*/6,
      GIM_CheckAtomicOrdering, /*MI*/0, /*Order*/(uint8_t)AtomicOrdering::NotAtomic,
      GIM_CheckRegBankForClass, /*MI*/0, /*Op*/0, /*RC*/GIMT_Encode2(AMDGPU::AV_64RegClassID),
      GIM_CheckPointerToAny, /*MI*/0, /*Op*/1, /*SizeInBits*/0,
      GIM_CheckComplexPattern, /*MI*/0, /*Op*/1, /*Renderer*/GIMT_Encode2(0), GIMT_Encode2(GICP_gi_mubuf_offset),
      // (ld:{ *:[v4bf16] } (MUBUFOffset:{ *:[iPTR] } v4i32:{ *:[v4i32] }:$srsrc, i32:{ *:[i32] }:$soffset, i32:{ *:[i32] }:$offset))<<P:Predicate_unindexedload>><<P:Predicate_load_global>>  =>  (BUFFER_LOAD_DWORDX2_VBUFFER_OFFSET:{ *:[v4bf16] } v4i32:{ *:[v4i32] }:$srsrc, i32:{ *:[i32] }:$soffset, i32:{ *:[i32] }:$offset)
      GIR_BuildMI, /*InsnID*/0, /*Opcode*/GIMT_Encode2(AMDGPU::BUFFER_LOAD_DWORDX2_VBUFFER_OFFSET),
      GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/0, // DstI[vdata]
      GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/0, // srsrc
      GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/1, // soffset
      GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/2, // offset
      GIR_AddImm8, /*InsnID*/0, /*Imm*/0,
      GIR_AddImm8, /*InsnID*/0, /*Imm*/0,
      GIR_MergeMemOperands, /*InsnID*/0, /*NumInsns*/1, /*MergeInsnID's*/0,
      GIR_ConstrainSelectedInstOperands, /*InsnID*/0,
      GIR_EraseFromParent, /*InsnID*/0,
      // GIR_Coverage, 3741,
      GIR_Done,
    // Label 1461: @97023
    GIM_Try, /*On fail goto*//*Label 1462*/ GIMT_Encode4(97095), // Rule ID 3743 //
      GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasUnrestrictedSOffset),
      GIM_CheckMemoryAddressSpace, /*MI*/0, /*MMO*/0, /*NumAddrSpace*/3, /*AddrSpace*/1, /*AddrSpace*/4, /*AddrSpace*/6,
      GIM_CheckAtomicOrdering, /*MI*/0, /*Order*/(uint8_t)AtomicOrdering::NotAtomic,
      GIM_CheckRegBankForClass, /*MI*/0, /*Op*/0, /*RC*/GIMT_Encode2(AMDGPU::AV_64RegClassID),
      GIM_CheckPointerToAny, /*MI*/0, /*Op*/1, /*SizeInBits*/0,
      GIM_CheckComplexPattern, /*MI*/0, /*Op*/1, /*Renderer*/GIMT_Encode2(0), GIMT_Encode2(GICP_gi_mubuf_offset),
      // (ld:{ *:[v4i16] } (MUBUFOffset:{ *:[iPTR] } v4i32:{ *:[v4i32] }:$srsrc, i32:{ *:[i32] }:$soffset, i32:{ *:[i32] }:$offset))<<P:Predicate_unindexedload>><<P:Predicate_load_global>>  =>  (BUFFER_LOAD_DWORDX2_OFFSET:{ *:[v4i16] } v4i32:{ *:[v4i32] }:$srsrc, i32:{ *:[i32] }:$soffset, i32:{ *:[i32] }:$offset)
      GIR_BuildMI, /*InsnID*/0, /*Opcode*/GIMT_Encode2(AMDGPU::BUFFER_LOAD_DWORDX2_OFFSET),
      GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/0, // DstI[vdata]
      GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/0, // srsrc
      GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/1, // soffset
      GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/2, // offset
      GIR_AddImm8, /*InsnID*/0, /*Imm*/0,
      GIR_AddImm8, /*InsnID*/0, /*Imm*/0,
      GIR_MergeMemOperands, /*InsnID*/0, /*NumInsns*/1, /*MergeInsnID's*/0,
      GIR_ConstrainSelectedInstOperands, /*InsnID*/0,
      GIR_EraseFromParent, /*InsnID*/0,
      // GIR_Coverage, 3743,
      GIR_Done,
    // Label 1462: @97095
    GIM_Try, /*On fail goto*//*Label 1463*/ GIMT_Encode4(97164), // Rule ID 3745 //
      GIM_CheckMemoryAddressSpace, /*MI*/0, /*MMO*/0, /*NumAddrSpace*/3, /*AddrSpace*/1, /*AddrSpace*/4, /*AddrSpace*/6,
      GIM_CheckAtomicOrdering, /*MI*/0, /*Order*/(uint8_t)AtomicOrdering::NotAtomic,
      GIM_CheckRegBankForClass, /*MI*/0, /*Op*/0, /*RC*/GIMT_Encode2(AMDGPU::AV_64RegClassID),
      GIM_CheckPointerToAny, /*MI*/0, /*Op*/1, /*SizeInBits*/0,
      GIM_CheckComplexPattern, /*MI*/0, /*Op*/1, /*Renderer*/GIMT_Encode2(0), GIMT_Encode2(GICP_gi_mubuf_offset),
      // (ld:{ *:[v4i16] } (MUBUFOffset:{ *:[iPTR] } v4i32:{ *:[v4i32] }:$srsrc, i32:{ *:[i32] }:$soffset, i32:{ *:[i32] }:$offset))<<P:Predicate_unindexedload>><<P:Predicate_load_global>>  =>  (BUFFER_LOAD_DWORDX2_VBUFFER_OFFSET:{ *:[v4i16] } v4i32:{ *:[v4i32] }:$srsrc, i32:{ *:[i32] }:$soffset, i32:{ *:[i32] }:$offset)
      GIR_BuildMI, /*InsnID*/0, /*Opcode*/GIMT_Encode2(AMDGPU::BUFFER_LOAD_DWORDX2_VBUFFER_OFFSET),
      GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/0, // DstI[vdata]
      GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/0, // srsrc
      GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/1, // soffset
      GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/2, // offset
      GIR_AddImm8, /*InsnID*/0, /*Imm*/0,
      GIR_AddImm8, /*InsnID*/0, /*Imm*/0,
      GIR_MergeMemOperands, /*InsnID*/0, /*NumInsns*/1, /*MergeInsnID's*/0,
      GIR_ConstrainSelectedInstOperands, /*InsnID*/0,
      GIR_EraseFromParent, /*InsnID*/0,
      // GIR_Coverage, 3745,
      GIR_Done,
    // Label 1463: @97164
    GIM_Try, /*On fail goto*//*Label 1464*/ GIMT_Encode4(97231), // Rule ID 6693 //
      GIM_CheckFeatures, GIMT_Encode2(GIFBS_NotLDSRequiresM0Init),
      GIM_CheckMemoryAddressSpace, /*MI*/0, /*MMO*/0, /*NumAddrSpace*/1, /*AddrSpace*/3,
      GIM_CheckAtomicOrdering, /*MI*/0, /*Order*/(uint8_t)AtomicOrdering::NotAtomic,
      GIM_CheckRegBankForClass, /*MI*/0, /*Op*/0, /*RC*/GIMT_Encode2(AMDGPU::AV_64RegClassID),
      GIM_CheckPointerToAny, /*MI*/0, /*Op*/1, /*SizeInBits*/0,
      GIM_CheckComplexPattern, /*MI*/0, /*Op*/1, /*Renderer*/GIMT_Encode2(0), GIMT_Encode2(GICP_gi_ds_64bit_4byte_aligned),
      // (ld:{ *:[v4f16] } (DS64Bit4ByteAligned:{ *:[iPTR] } i32:{ *:[i32] }:$ptr, i8:{ *:[i8] }:$offset0, i8:{ *:[i8] }:$offset1))<<P:Predicate_unindexedload>><<P:Predicate_load_local>>  =>  (DS_READ2_B32_gfx9:{ *:[v4f16] } ?:{ *:[i32] }:$ptr, ?:{ *:[i8] }:$offset0, ?:{ *:[i8] }:$offset1, 0:{ *:[i1] })
      GIR_BuildMI, /*InsnID*/0, /*Opcode*/GIMT_Encode2(AMDGPU::DS_READ2_B32_gfx9),
      GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/0, // DstI[vdst]
      GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/0, // ptr
      GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/1, // offset0
      GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/2, // offset1
      GIR_AddImm8, /*InsnID*/0, /*Imm*/0,
      GIR_MergeMemOperands, /*InsnID*/0, /*NumInsns*/1, /*MergeInsnID's*/0,
      GIR_ConstrainSelectedInstOperands, /*InsnID*/0,
      GIR_EraseFromParent, /*InsnID*/0,
      // GIR_Coverage, 6693,
      GIR_Done,
    // Label 1464: @97231
    GIM_Try, /*On fail goto*//*Label 1465*/ GIMT_Encode4(97298), // Rule ID 6697 //
      GIM_CheckFeatures, GIMT_Encode2(GIFBS_NotLDSRequiresM0Init),
      GIM_CheckMemoryAddressSpace, /*MI*/0, /*MMO*/0, /*NumAddrSpace*/1, /*AddrSpace*/3,
      GIM_CheckAtomicOrdering, /*MI*/0, /*Order*/(uint8_t)AtomicOrdering::NotAtomic,
      GIM_CheckRegBankForClass, /*MI*/0, /*Op*/0, /*RC*/GIMT_Encode2(AMDGPU::AV_64RegClassID),
      GIM_CheckPointerToAny, /*MI*/0, /*Op*/1, /*SizeInBits*/0,
      GIM_CheckComplexPattern, /*MI*/0, /*Op*/1, /*Renderer*/GIMT_Encode2(0), GIMT_Encode2(GICP_gi_ds_64bit_4byte_aligned),
      // (ld:{ *:[v4bf16] } (DS64Bit4ByteAligned:{ *:[iPTR] } i32:{ *:[i32] }:$ptr, i8:{ *:[i8] }:$offset0, i8:{ *:[i8] }:$offset1))<<P:Predicate_unindexedload>><<P:Predicate_load_local>>  =>  (DS_READ2_B32_gfx9:{ *:[v4bf16] } ?:{ *:[i32] }:$ptr, ?:{ *:[i8] }:$offset0, ?:{ *:[i8] }:$offset1, 0:{ *:[i1] })
      GIR_BuildMI, /*InsnID*/0, /*Opcode*/GIMT_Encode2(AMDGPU::DS_READ2_B32_gfx9),
      GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/0, // DstI[vdst]
      GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/0, // ptr
      GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/1, // offset0
      GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/2, // offset1
      GIR_AddImm8, /*InsnID*/0, /*Imm*/0,
      GIR_MergeMemOperands, /*InsnID*/0, /*NumInsns*/1, /*MergeInsnID's*/0,
      GIR_ConstrainSelectedInstOperands, /*InsnID*/0,
      GIR_EraseFromParent, /*InsnID*/0,
      // GIR_Coverage, 6697,
      GIR_Done,
    // Label 1465: @97298
    GIM_Try, /*On fail goto*//*Label 1466*/ GIMT_Encode4(97365), // Rule ID 6701 //
      GIM_CheckFeatures, GIMT_Encode2(GIFBS_NotLDSRequiresM0Init),
      GIM_CheckMemoryAddressSpace, /*MI*/0, /*MMO*/0, /*NumAddrSpace*/1, /*AddrSpace*/3,
      GIM_CheckAtomicOrdering, /*MI*/0, /*Order*/(uint8_t)AtomicOrdering::NotAtomic,
      GIM_CheckRegBankForClass, /*MI*/0, /*Op*/0, /*RC*/GIMT_Encode2(AMDGPU::AV_64RegClassID),
      GIM_CheckPointerToAny, /*MI*/0, /*Op*/1, /*SizeInBits*/0,
      GIM_CheckComplexPattern, /*MI*/0, /*Op*/1, /*Renderer*/GIMT_Encode2(0), GIMT_Encode2(GICP_gi_ds_64bit_4byte_aligned),
      // (ld:{ *:[v4i16] } (DS64Bit4ByteAligned:{ *:[iPTR] } i32:{ *:[i32] }:$ptr, i8:{ *:[i8] }:$offset0, i8:{ *:[i8] }:$offset1))<<P:Predicate_unindexedload>><<P:Predicate_load_local>>  =>  (DS_READ2_B32_gfx9:{ *:[v4i16] } ?:{ *:[i32] }:$ptr, ?:{ *:[i8] }:$offset0, ?:{ *:[i8] }:$offset1, 0:{ *:[i1] })
      GIR_BuildMI, /*InsnID*/0, /*Opcode*/GIMT_Encode2(AMDGPU::DS_READ2_B32_gfx9),
      GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/0, // DstI[vdst]
      GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/0, // ptr
      GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/1, // offset0
      GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/2, // offset1
      GIR_AddImm8, /*InsnID*/0, /*Imm*/0,
      GIR_MergeMemOperands, /*InsnID*/0, /*NumInsns*/1, /*MergeInsnID's*/0,
      GIR_ConstrainSelectedInstOperands, /*InsnID*/0,
      GIR_EraseFromParent, /*InsnID*/0,
      // GIR_Coverage, 6701,
      GIR_Done,
    // Label 1466: @97365
    GIM_Try, /*On fail goto*//*Label 1467*/ GIMT_Encode4(97434), // Rule ID 3045 //
      GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasFlatGlobalInsts),
      GIM_CheckMemoryAddressSpace, /*MI*/0, /*MMO*/0, /*NumAddrSpace*/3, /*AddrSpace*/1, /*AddrSpace*/4, /*AddrSpace*/6,
      GIM_CheckAtomicOrdering, /*MI*/0, /*Order*/(uint8_t)AtomicOrdering::NotAtomic,
      GIM_CheckRegBankForClass, /*MI*/0, /*Op*/0, /*RC*/GIMT_Encode2(AMDGPU::AV_64RegClassID),
      GIM_CheckPointerToAny, /*MI*/0, /*Op*/1, /*SizeInBits*/0,
      GIM_CheckComplexPattern, /*MI*/0, /*Op*/1, /*Renderer*/GIMT_Encode2(0), GIMT_Encode2(GICP_gi_global_saddr),
      // (ld:{ *:[v4f16] } (GlobalSAddr:{ *:[iPTR] } SReg_64:{ *:[i64] }:$saddr, VGPR_32:{ *:[i32] }:$voffset, i32:{ *:[i32] }:$offset))<<P:Predicate_unindexedload>><<P:Predicate_load_global>>  =>  (GLOBAL_LOAD_DWORDX2_SADDR:{ *:[v4f16] } ?:{ *:[i64] }:$saddr, ?:{ *:[i32] }:$voffset, ?:{ *:[i32] }:$offset, 0:{ *:[i32] })
      GIR_BuildMI, /*InsnID*/0, /*Opcode*/GIMT_Encode2(AMDGPU::GLOBAL_LOAD_DWORDX2_SADDR),
      GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/0, // DstI[vdst]
      GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/0, // saddr
      GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/1, // voffset
      GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/2, // offset
      GIR_AddImm8, /*InsnID*/0, /*Imm*/0,
      GIR_MergeMemOperands, /*InsnID*/0, /*NumInsns*/1, /*MergeInsnID's*/0,
      GIR_ConstrainSelectedInstOperands, /*InsnID*/0,
      GIR_EraseFromParent, /*InsnID*/0,
      // GIR_Coverage, 3045,
      GIR_Done,
    // Label 1467: @97434
    GIM_Try, /*On fail goto*//*Label 1468*/ GIMT_Encode4(97503), // Rule ID 3049 //
      GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasFlatGlobalInsts),
      GIM_CheckMemoryAddressSpace, /*MI*/0, /*MMO*/0, /*NumAddrSpace*/3, /*AddrSpace*/1, /*AddrSpace*/4, /*AddrSpace*/6,
      GIM_CheckAtomicOrdering, /*MI*/0, /*Order*/(uint8_t)AtomicOrdering::NotAtomic,
      GIM_CheckRegBankForClass, /*MI*/0, /*Op*/0, /*RC*/GIMT_Encode2(AMDGPU::AV_64RegClassID),
      GIM_CheckPointerToAny, /*MI*/0, /*Op*/1, /*SizeInBits*/0,
      GIM_CheckComplexPattern, /*MI*/0, /*Op*/1, /*Renderer*/GIMT_Encode2(0), GIMT_Encode2(GICP_gi_global_saddr),
      // (ld:{ *:[v4bf16] } (GlobalSAddr:{ *:[iPTR] } SReg_64:{ *:[i64] }:$saddr, VGPR_32:{ *:[i32] }:$voffset, i32:{ *:[i32] }:$offset))<<P:Predicate_unindexedload>><<P:Predicate_load_global>>  =>  (GLOBAL_LOAD_DWORDX2_SADDR:{ *:[v4bf16] } ?:{ *:[i64] }:$saddr, ?:{ *:[i32] }:$voffset, ?:{ *:[i32] }:$offset, 0:{ *:[i32] })
      GIR_BuildMI, /*InsnID*/0, /*Opcode*/GIMT_Encode2(AMDGPU::GLOBAL_LOAD_DWORDX2_SADDR),
      GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/0, // DstI[vdst]
      GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/0, // saddr
      GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/1, // voffset
      GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/2, // offset
      GIR_AddImm8, /*InsnID*/0, /*Imm*/0,
      GIR_MergeMemOperands, /*InsnID*/0, /*NumInsns*/1, /*MergeInsnID's*/0,
      GIR_ConstrainSelectedInstOperands, /*InsnID*/0,
      GIR_EraseFromParent, /*InsnID*/0,
      // GIR_Coverage, 3049,
      GIR_Done,
    // Label 1468: @97503
    GIM_Try, /*On fail goto*//*Label 1469*/ GIMT_Encode4(97572), // Rule ID 3053 //
      GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasFlatGlobalInsts),
      GIM_CheckMemoryAddressSpace, /*MI*/0, /*MMO*/0, /*NumAddrSpace*/3, /*AddrSpace*/1, /*AddrSpace*/4, /*AddrSpace*/6,
      GIM_CheckAtomicOrdering, /*MI*/0, /*Order*/(uint8_t)AtomicOrdering::NotAtomic,
      GIM_CheckRegBankForClass, /*MI*/0, /*Op*/0, /*RC*/GIMT_Encode2(AMDGPU::AV_64RegClassID),
      GIM_CheckPointerToAny, /*MI*/0, /*Op*/1, /*SizeInBits*/0,
      GIM_CheckComplexPattern, /*MI*/0, /*Op*/1, /*Renderer*/GIMT_Encode2(0), GIMT_Encode2(GICP_gi_global_saddr),
      // (ld:{ *:[v4i16] } (GlobalSAddr:{ *:[iPTR] } SReg_64:{ *:[i64] }:$saddr, VGPR_32:{ *:[i32] }:$voffset, i32:{ *:[i32] }:$offset))<<P:Predicate_unindexedload>><<P:Predicate_load_global>>  =>  (GLOBAL_LOAD_DWORDX2_SADDR:{ *:[v4i16] } ?:{ *:[i64] }:$saddr, ?:{ *:[i32] }:$voffset, ?:{ *:[i32] }:$offset, 0:{ *:[i32] })
      GIR_BuildMI, /*InsnID*/0, /*Opcode*/GIMT_Encode2(AMDGPU::GLOBAL_LOAD_DWORDX2_SADDR),
      GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/0, // DstI[vdst]
      GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/0, // saddr
      GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/1, // voffset
      GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/2, // offset
      GIR_AddImm8, /*InsnID*/0, /*Imm*/0,
      GIR_MergeMemOperands, /*InsnID*/0, /*NumInsns*/1, /*MergeInsnID's*/0,
      GIR_ConstrainSelectedInstOperands, /*InsnID*/0,
      GIR_EraseFromParent, /*InsnID*/0,
      // GIR_Coverage, 3053,
      GIR_Done,
    // Label 1469: @97572
    GIM_Try, /*On fail goto*//*Label 1470*/ GIMT_Encode4(97636), // Rule ID 3044 //
      GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasFlatGlobalInsts),
      GIM_CheckMemoryAddressSpace, /*MI*/0, /*MMO*/0, /*NumAddrSpace*/3, /*AddrSpace*/1, /*AddrSpace*/4, /*AddrSpace*/6,
      GIM_CheckAtomicOrdering, /*MI*/0, /*Order*/(uint8_t)AtomicOrdering::NotAtomic,
      GIM_CheckRegBankForClass, /*MI*/0, /*Op*/0, /*RC*/GIMT_Encode2(AMDGPU::AV_64RegClassID),
      GIM_CheckPointerToAny, /*MI*/0, /*Op*/1, /*SizeInBits*/0,
      GIM_CheckComplexPattern, /*MI*/0, /*Op*/1, /*Renderer*/GIMT_Encode2(0), GIMT_Encode2(GICP_gi_global_offset),
      // (ld:{ *:[v4f16] } (GlobalOffset:{ *:[iPTR] } VReg_64:{ *:[i64] }:$vaddr, i32:{ *:[i32] }:$offset))<<P:Predicate_unindexedload>><<P:Predicate_load_global>>  =>  (GLOBAL_LOAD_DWORDX2:{ *:[v4f16] } ?:{ *:[i64] }:$vaddr, ?:{ *:[i32] }:$offset)
      GIR_BuildMI, /*InsnID*/0, /*Opcode*/GIMT_Encode2(AMDGPU::GLOBAL_LOAD_DWORDX2),
      GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/0, // DstI[vdst]
      GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/0, // vaddr
      GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/1, // offset
      GIR_AddImm8, /*InsnID*/0, /*Imm*/0,
      GIR_MergeMemOperands, /*InsnID*/0, /*NumInsns*/1, /*MergeInsnID's*/0,
      GIR_ConstrainSelectedInstOperands, /*InsnID*/0,
      GIR_EraseFromParent, /*InsnID*/0,
      // GIR_Coverage, 3044,
      GIR_Done,
    // Label 1470: @97636
    GIM_Try, /*On fail goto*//*Label 1471*/ GIMT_Encode4(97700), // Rule ID 3048 //
      GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasFlatGlobalInsts),
      GIM_CheckMemoryAddressSpace, /*MI*/0, /*MMO*/0, /*NumAddrSpace*/3, /*AddrSpace*/1, /*AddrSpace*/4, /*AddrSpace*/6,
      GIM_CheckAtomicOrdering, /*MI*/0, /*Order*/(uint8_t)AtomicOrdering::NotAtomic,
      GIM_CheckRegBankForClass, /*MI*/0, /*Op*/0, /*RC*/GIMT_Encode2(AMDGPU::AV_64RegClassID),
      GIM_CheckPointerToAny, /*MI*/0, /*Op*/1, /*SizeInBits*/0,
      GIM_CheckComplexPattern, /*MI*/0, /*Op*/1, /*Renderer*/GIMT_Encode2(0), GIMT_Encode2(GICP_gi_global_offset),
      // (ld:{ *:[v4bf16] } (GlobalOffset:{ *:[iPTR] } VReg_64:{ *:[i64] }:$vaddr, i32:{ *:[i32] }:$offset))<<P:Predicate_unindexedload>><<P:Predicate_load_global>>  =>  (GLOBAL_LOAD_DWORDX2:{ *:[v4bf16] } ?:{ *:[i64] }:$vaddr, ?:{ *:[i32] }:$offset)
      GIR_BuildMI, /*InsnID*/0, /*Opcode*/GIMT_Encode2(AMDGPU::GLOBAL_LOAD_DWORDX2),
      GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/0, // DstI[vdst]
      GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/0, // vaddr
      GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/1, // offset
      GIR_AddImm8, /*InsnID*/0, /*Imm*/0,
      GIR_MergeMemOperands, /*InsnID*/0, /*NumInsns*/1, /*MergeInsnID's*/0,
      GIR_ConstrainSelectedInstOperands, /*InsnID*/0,
      GIR_EraseFromParent, /*InsnID*/0,
      // GIR_Coverage, 3048,
      GIR_Done,
    // Label 1471: @97700
    GIM_Try, /*On fail goto*//*Label 1472*/ GIMT_Encode4(97764), // Rule ID 3052 //
      GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasFlatGlobalInsts),
      GIM_CheckMemoryAddressSpace, /*MI*/0, /*MMO*/0, /*NumAddrSpace*/3, /*AddrSpace*/1, /*AddrSpace*/4, /*AddrSpace*/6,
      GIM_CheckAtomicOrdering, /*MI*/0, /*Order*/(uint8_t)AtomicOrdering::NotAtomic,
      GIM_CheckRegBankForClass, /*MI*/0, /*Op*/0, /*RC*/GIMT_Encode2(AMDGPU::AV_64RegClassID),
      GIM_CheckPointerToAny, /*MI*/0, /*Op*/1, /*SizeInBits*/0,
      GIM_CheckComplexPattern, /*MI*/0, /*Op*/1, /*Renderer*/GIMT_Encode2(0), GIMT_Encode2(GICP_gi_global_offset),
      // (ld:{ *:[v4i16] } (GlobalOffset:{ *:[iPTR] } VReg_64:{ *:[i64] }:$vaddr, i32:{ *:[i32] }:$offset))<<P:Predicate_unindexedload>><<P:Predicate_load_global>>  =>  (GLOBAL_LOAD_DWORDX2:{ *:[v4i16] } ?:{ *:[i64] }:$vaddr, ?:{ *:[i32] }:$offset)
      GIR_BuildMI, /*InsnID*/0, /*Opcode*/GIMT_Encode2(AMDGPU::GLOBAL_LOAD_DWORDX2),
      GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/0, // DstI[vdst]
      GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/0, // vaddr
      GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/1, // offset
      GIR_AddImm8, /*InsnID*/0, /*Imm*/0,
      GIR_MergeMemOperands, /*InsnID*/0, /*NumInsns*/1, /*MergeInsnID's*/0,
      GIR_ConstrainSelectedInstOperands, /*InsnID*/0,
      GIR_EraseFromParent, /*InsnID*/0,
      // GIR_Coverage, 3052,
      GIR_Done,
    // Label 1472: @97764
    GIM_Try, /*On fail goto*//*Label 1473*/ GIMT_Encode4(97829), // Rule ID 2797 //
      GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasFlatAddressSpace),
      GIM_CheckMemoryAddressSpace, /*MI*/0, /*MMO*/0, /*NumAddrSpace*/4, /*AddrSpace*/0, /*AddrSpace*/1, /*AddrSpace*/4, /*AddrSpace*/6,
      GIM_CheckAtomicOrdering, /*MI*/0, /*Order*/(uint8_t)AtomicOrdering::NotAtomic,
      GIM_CheckRegBankForClass, /*MI*/0, /*Op*/0, /*RC*/GIMT_Encode2(AMDGPU::AV_64RegClassID),
      GIM_CheckPointerToAny, /*MI*/0, /*Op*/1, /*SizeInBits*/0,
      GIM_CheckComplexPattern, /*MI*/0, /*Op*/1, /*Renderer*/GIMT_Encode2(0), GIMT_Encode2(GICP_gi_flat_offset),
      // (ld:{ *:[v4f16] } (FlatOffset:{ *:[iPTR] } i64:{ *:[i64] }:$vaddr, i32:{ *:[i32] }:$offset))<<P:Predicate_unindexedload>><<P:Predicate_load_flat>>  =>  (FLAT_LOAD_DWORDX2:{ *:[v4f16] } ?:{ *:[i64] }:$vaddr, ?:{ *:[i32] }:$offset)
      GIR_BuildMI, /*InsnID*/0, /*Opcode*/GIMT_Encode2(AMDGPU::FLAT_LOAD_DWORDX2),
      GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/0, // DstI[vdst]
      GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/0, // vaddr
      GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/1, // offset
      GIR_AddImm8, /*InsnID*/0, /*Imm*/0,
      GIR_MergeMemOperands, /*InsnID*/0, /*NumInsns*/1, /*MergeInsnID's*/0,
      GIR_ConstrainSelectedInstOperands, /*InsnID*/0,
      GIR_EraseFromParent, /*InsnID*/0,
      // GIR_Coverage, 2797,
      GIR_Done,
    // Label 1473: @97829
    GIM_Try, /*On fail goto*//*Label 1474*/ GIMT_Encode4(97894), // Rule ID 2799 //
      GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasFlatAddressSpace),
      GIM_CheckMemoryAddressSpace, /*MI*/0, /*MMO*/0, /*NumAddrSpace*/4, /*AddrSpace*/0, /*AddrSpace*/1, /*AddrSpace*/4, /*AddrSpace*/6,
      GIM_CheckAtomicOrdering, /*MI*/0, /*Order*/(uint8_t)AtomicOrdering::NotAtomic,
      GIM_CheckRegBankForClass, /*MI*/0, /*Op*/0, /*RC*/GIMT_Encode2(AMDGPU::AV_64RegClassID),
      GIM_CheckPointerToAny, /*MI*/0, /*Op*/1, /*SizeInBits*/0,
      GIM_CheckComplexPattern, /*MI*/0, /*Op*/1, /*Renderer*/GIMT_Encode2(0), GIMT_Encode2(GICP_gi_flat_offset),
      // (ld:{ *:[v4bf16] } (FlatOffset:{ *:[iPTR] } i64:{ *:[i64] }:$vaddr, i32:{ *:[i32] }:$offset))<<P:Predicate_unindexedload>><<P:Predicate_load_flat>>  =>  (FLAT_LOAD_DWORDX2:{ *:[v4bf16] } ?:{ *:[i64] }:$vaddr, ?:{ *:[i32] }:$offset)
      GIR_BuildMI, /*InsnID*/0, /*Opcode*/GIMT_Encode2(AMDGPU::FLAT_LOAD_DWORDX2),
      GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/0, // DstI[vdst]
      GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/0, // vaddr
      GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/1, // offset
      GIR_AddImm8, /*InsnID*/0, /*Imm*/0,
      GIR_MergeMemOperands, /*InsnID*/0, /*NumInsns*/1, /*MergeInsnID's*/0,
      GIR_ConstrainSelectedInstOperands, /*InsnID*/0,
      GIR_EraseFromParent, /*InsnID*/0,
      // GIR_Coverage, 2799,
      GIR_Done,
    // Label 1474: @97894
    GIM_Try, /*On fail goto*//*Label 1475*/ GIMT_Encode4(97959), // Rule ID 2801 //
      GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasFlatAddressSpace),
      GIM_CheckMemoryAddressSpace, /*MI*/0, /*MMO*/0, /*NumAddrSpace*/4, /*AddrSpace*/0, /*AddrSpace*/1, /*AddrSpace*/4, /*AddrSpace*/6,
      GIM_CheckAtomicOrdering, /*MI*/0, /*Order*/(uint8_t)AtomicOrdering::NotAtomic,
      GIM_CheckRegBankForClass, /*MI*/0, /*Op*/0, /*RC*/GIMT_Encode2(AMDGPU::AV_64RegClassID),
      GIM_CheckPointerToAny, /*MI*/0, /*Op*/1, /*SizeInBits*/0,
      GIM_CheckComplexPattern, /*MI*/0, /*Op*/1, /*Renderer*/GIMT_Encode2(0), GIMT_Encode2(GICP_gi_flat_offset),
      // (ld:{ *:[v4i16] } (FlatOffset:{ *:[iPTR] } i64:{ *:[i64] }:$vaddr, i32:{ *:[i32] }:$offset))<<P:Predicate_unindexedload>><<P:Predicate_load_flat>>  =>  (FLAT_LOAD_DWORDX2:{ *:[v4i16] } ?:{ *:[i64] }:$vaddr, ?:{ *:[i32] }:$offset)
      GIR_BuildMI, /*InsnID*/0, /*Opcode*/GIMT_Encode2(AMDGPU::FLAT_LOAD_DWORDX2),
      GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/0, // DstI[vdst]
      GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/0, // vaddr
      GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/1, // offset
      GIR_AddImm8, /*InsnID*/0, /*Imm*/0,
      GIR_MergeMemOperands, /*InsnID*/0, /*NumInsns*/1, /*MergeInsnID's*/0,
      GIR_ConstrainSelectedInstOperands, /*InsnID*/0,
      GIR_EraseFromParent, /*InsnID*/0,
      // GIR_Coverage, 2801,
      GIR_Done,
    // Label 1475: @97959
    GIM_Reject,
    // Label 832: @97960
    GIM_Try, /*On fail goto*//*Label 1476*/ GIMT_Encode4(98030), // Rule ID 2562 //
      GIM_CheckFeatures, GIMT_Encode2(GIFBS_isGFX9Plus),
      GIM_CheckMemorySizeEqualToLLT, /*MI*/0, /*MMO*/0, /*OpIdx*/0,
      GIM_CheckAtomicOrdering, /*MI*/0, /*Order*/(uint8_t)AtomicOrdering::NotAtomic,
      GIM_CheckRegBankForClass, /*MI*/0, /*Op*/0, /*RC*/GIMT_Encode2(AMDGPU::SReg_128RegClassID),
      GIM_CheckPointerToAny, /*MI*/0, /*Op*/1, /*SizeInBits*/0,
      GIM_CheckCxxInsnPredicate, /*MI*/0, /*FnId*/GIMT_Encode2(GICXXPred_MI_Predicate_smrd_load),
      GIM_CheckComplexPattern, /*MI*/0, /*Op*/1, /*Renderer*/GIMT_Encode2(0), GIMT_Encode2(GICP_gi_smrd_sgpr_imm),
      // (ld:{ *:[v4i32] } (SMRDSgprImm:{ *:[iPTR] } i64:{ *:[i64] }:$sbase, i32:{ *:[i32] }:$soffset, i32:{ *:[i32] }:$offset))<<P:Predicate_unindexedload>><<P:Predicate_load>><<P:Predicate_smrd_load>>  =>  (S_LOAD_DWORDX4_SGPR_IMM:{ *:[v4i32] } ?:{ *:[i64] }:$sbase, ?:{ *:[i32] }:$soffset, ?:{ *:[i32] }:$offset, 0:{ *:[i32] })
      GIR_BuildMI, /*InsnID*/0, /*Opcode*/GIMT_Encode2(AMDGPU::S_LOAD_DWORDX4_SGPR_IMM),
      GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/0, // DstI[sdst]
      GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/0, // sbase
      GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/1, // soffset
      GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/2, // offset
      GIR_AddImm8, /*InsnID*/0, /*Imm*/0,
      GIR_MergeMemOperands, /*InsnID*/0, /*NumInsns*/1, /*MergeInsnID's*/0,
      GIR_ConstrainSelectedInstOperands, /*InsnID*/0,
      GIR_EraseFromParent, /*InsnID*/0,
      // GIR_Coverage, 2562,
      GIR_Done,
    // Label 1476: @98030
    GIM_Try, /*On fail goto*//*Label 1477*/ GIMT_Encode4(98100), // Rule ID 2568 //
      GIM_CheckFeatures, GIMT_Encode2(GIFBS_isGFX9Plus),
      GIM_CheckMemorySizeEqualToLLT, /*MI*/0, /*MMO*/0, /*OpIdx*/0,
      GIM_CheckAtomicOrdering, /*MI*/0, /*Order*/(uint8_t)AtomicOrdering::NotAtomic,
      GIM_CheckRegBankForClass, /*MI*/0, /*Op*/0, /*RC*/GIMT_Encode2(AMDGPU::SReg_128RegClassID),
      GIM_CheckPointerToAny, /*MI*/0, /*Op*/1, /*SizeInBits*/0,
      GIM_CheckCxxInsnPredicate, /*MI*/0, /*FnId*/GIMT_Encode2(GICXXPred_MI_Predicate_smrd_load),
      GIM_CheckComplexPattern, /*MI*/0, /*Op*/1, /*Renderer*/GIMT_Encode2(0), GIMT_Encode2(GICP_gi_smrd_sgpr_imm),
      // (ld:{ *:[v4f32] } (SMRDSgprImm:{ *:[iPTR] } i64:{ *:[i64] }:$sbase, i32:{ *:[i32] }:$soffset, i32:{ *:[i32] }:$offset))<<P:Predicate_unindexedload>><<P:Predicate_load>><<P:Predicate_smrd_load>>  =>  (S_LOAD_DWORDX4_SGPR_IMM:{ *:[v4f32] } ?:{ *:[i64] }:$sbase, ?:{ *:[i32] }:$soffset, ?:{ *:[i32] }:$offset, 0:{ *:[i32] })
      GIR_BuildMI, /*InsnID*/0, /*Opcode*/GIMT_Encode2(AMDGPU::S_LOAD_DWORDX4_SGPR_IMM),
      GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/0, // DstI[sdst]
      GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/0, // sbase
      GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/1, // soffset
      GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/2, // offset
      GIR_AddImm8, /*InsnID*/0, /*Imm*/0,
      GIR_MergeMemOperands, /*InsnID*/0, /*NumInsns*/1, /*MergeInsnID's*/0,
      GIR_ConstrainSelectedInstOperands, /*InsnID*/0,
      GIR_EraseFromParent, /*InsnID*/0,
      // GIR_Coverage, 2568,
      GIR_Done,
    // Label 1477: @98100
    GIM_Try, /*On fail goto*//*Label 1478*/ GIMT_Encode4(98175), // Rule ID 6863 //
      GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasUnalignedAccessMode_LDSRequiresM0Init),
      GIM_CheckMemorySizeEqualToLLT, /*MI*/0, /*MMO*/0, /*OpIdx*/0,
      GIM_CheckMemoryAddressSpace, /*MI*/0, /*MMO*/0, /*NumAddrSpace*/1, /*AddrSpace*/3,
      GIM_CheckMemoryAddressSpace, /*MI*/0, /*MMO*/0, /*NumAddrSpace*/1, /*AddrSpace*/3,
      GIM_CheckAtomicOrdering, /*MI*/0, /*Order*/(uint8_t)AtomicOrdering::NotAtomic,
      GIM_CheckRegBankForClass, /*MI*/0, /*Op*/0, /*RC*/GIMT_Encode2(AMDGPU::AV_128RegClassID),
      GIM_CheckPointerToAny, /*MI*/0, /*Op*/1, /*SizeInBits*/0,
      GIM_CheckCxxInsnPredicate, /*MI*/0, /*FnId*/GIMT_Encode2(GICXXPred_MI_Predicate_load_align_less_than_4_local_m0),
      GIM_CheckComplexPattern, /*MI*/0, /*Op*/1, /*Renderer*/GIMT_Encode2(0), GIMT_Encode2(GICP_gi_ds_1addr_1offset),
      // (AMDGPUld_glue:{ *:[v4i32] } (DS1Addr1Offset:{ *:[iPTR] } i32:{ *:[i32] }:$ptr, i32:{ *:[i32] }:$offset))<<P:Predicate_unindexedload_glue>><<P:Predicate_load_glue>><<P:Predicate_load_local_m0>><<P:Predicate_load_align_less_than_4_local_m0>>  =>  (DS_READ_B128:{ *:[v4i32] } ?:{ *:[i32] }:$ptr, offset:{ *:[i32] }:$offset, 0:{ *:[i1] })
      GIR_BuildMI, /*InsnID*/0, /*Opcode*/GIMT_Encode2(AMDGPU::DS_READ_B128),
      GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/0, // DstI[vdst]
      GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/0, // ptr
      GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/1, // offset
      GIR_AddImm8, /*InsnID*/0, /*Imm*/0,
      GIR_MergeMemOperands, /*InsnID*/0, /*NumInsns*/1, /*MergeInsnID's*/0,
      GIR_ConstrainSelectedInstOperands, /*InsnID*/0,
      GIR_EraseFromParent, /*InsnID*/0,
      // GIR_Coverage, 6863,
      GIR_Done,
    // Label 1478: @98175
    GIM_Try, /*On fail goto*//*Label 1479*/ GIMT_Encode4(98250), // Rule ID 6867 //
      GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasUnalignedAccessMode_LDSRequiresM0Init),
      GIM_CheckMemorySizeEqualToLLT, /*MI*/0, /*MMO*/0, /*OpIdx*/0,
      GIM_CheckMemoryAddressSpace, /*MI*/0, /*MMO*/0, /*NumAddrSpace*/1, /*AddrSpace*/3,
      GIM_CheckMemoryAddressSpace, /*MI*/0, /*MMO*/0, /*NumAddrSpace*/1, /*AddrSpace*/3,
      GIM_CheckAtomicOrdering, /*MI*/0, /*Order*/(uint8_t)AtomicOrdering::NotAtomic,
      GIM_CheckRegBankForClass, /*MI*/0, /*Op*/0, /*RC*/GIMT_Encode2(AMDGPU::AV_128RegClassID),
      GIM_CheckPointerToAny, /*MI*/0, /*Op*/1, /*SizeInBits*/0,
      GIM_CheckCxxInsnPredicate, /*MI*/0, /*FnId*/GIMT_Encode2(GICXXPred_MI_Predicate_load_align_less_than_4_local_m0),
      GIM_CheckComplexPattern, /*MI*/0, /*Op*/1, /*Renderer*/GIMT_Encode2(0), GIMT_Encode2(GICP_gi_ds_1addr_1offset),
      // (AMDGPUld_glue:{ *:[v4f32] } (DS1Addr1Offset:{ *:[iPTR] } i32:{ *:[i32] }:$ptr, i32:{ *:[i32] }:$offset))<<P:Predicate_unindexedload_glue>><<P:Predicate_load_glue>><<P:Predicate_load_local_m0>><<P:Predicate_load_align_less_than_4_local_m0>>  =>  (DS_READ_B128:{ *:[v4f32] } ?:{ *:[i32] }:$ptr, offset:{ *:[i32] }:$offset, 0:{ *:[i1] })
      GIR_BuildMI, /*InsnID*/0, /*Opcode*/GIMT_Encode2(AMDGPU::DS_READ_B128),
      GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/0, // DstI[vdst]
      GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/0, // ptr
      GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/1, // offset
      GIR_AddImm8, /*InsnID*/0, /*Imm*/0,
      GIR_MergeMemOperands, /*InsnID*/0, /*NumInsns*/1, /*MergeInsnID's*/0,
      GIR_ConstrainSelectedInstOperands, /*InsnID*/0,
      GIR_EraseFromParent, /*InsnID*/0,
      // GIR_Coverage, 6867,
      GIR_Done,
    // Label 1479: @98250
    GIM_Try, /*On fail goto*//*Label 1480*/ GIMT_Encode4(98320), // Rule ID 6787 //
      GIM_CheckFeatures, GIMT_Encode2(GIFBS_LDSRequiresM0Init_isGFX7Plus),
      GIM_CheckMemorySizeEqualToLLT, /*MI*/0, /*MMO*/0, /*OpIdx*/0,
      GIM_CheckMemoryAddressSpace, /*MI*/0, /*MMO*/0, /*NumAddrSpace*/1, /*AddrSpace*/3,
      GIM_CheckMemoryAlignment, /*MI*/0, /*MMO*/0, /*MinAlign*/16,
      GIM_CheckAtomicOrdering, /*MI*/0, /*Order*/(uint8_t)AtomicOrdering::NotAtomic,
      GIM_CheckRegBankForClass, /*MI*/0, /*Op*/0, /*RC*/GIMT_Encode2(AMDGPU::AV_128RegClassID),
      GIM_CheckPointerToAny, /*MI*/0, /*Op*/1, /*SizeInBits*/0,
      GIM_CheckComplexPattern, /*MI*/0, /*Op*/1, /*Renderer*/GIMT_Encode2(0), GIMT_Encode2(GICP_gi_ds_1addr_1offset),
      // (AMDGPUld_glue:{ *:[v4i32] } (DS1Addr1Offset:{ *:[iPTR] } i32:{ *:[i32] }:$ptr, i32:{ *:[i32] }:$offset))<<P:Predicate_unindexedload_glue>><<P:Predicate_load_glue>><<P:Predicate_load_local_m0>><<P:Predicate_load_align16_local_m0>>  =>  (DS_READ_B128:{ *:[v4i32] } ?:{ *:[i32] }:$ptr, offset:{ *:[i32] }:$offset, 0:{ *:[i1] })
      GIR_BuildMI, /*InsnID*/0, /*Opcode*/GIMT_Encode2(AMDGPU::DS_READ_B128),
      GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/0, // DstI[vdst]
      GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/0, // ptr
      GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/1, // offset
      GIR_AddImm8, /*InsnID*/0, /*Imm*/0,
      GIR_MergeMemOperands, /*InsnID*/0, /*NumInsns*/1, /*MergeInsnID's*/0,
      GIR_ConstrainSelectedInstOperands, /*InsnID*/0,
      GIR_EraseFromParent, /*InsnID*/0,
      // GIR_Coverage, 6787,
      GIR_Done,
    // Label 1480: @98320
    GIM_Try, /*On fail goto*//*Label 1481*/ GIMT_Encode4(98390), // Rule ID 6791 //
      GIM_CheckFeatures, GIMT_Encode2(GIFBS_LDSRequiresM0Init_isGFX7Plus),
      GIM_CheckMemorySizeEqualToLLT, /*MI*/0, /*MMO*/0, /*OpIdx*/0,
      GIM_CheckMemoryAddressSpace, /*MI*/0, /*MMO*/0, /*NumAddrSpace*/1, /*AddrSpace*/3,
      GIM_CheckMemoryAlignment, /*MI*/0, /*MMO*/0, /*MinAlign*/16,
      GIM_CheckAtomicOrdering, /*MI*/0, /*Order*/(uint8_t)AtomicOrdering::NotAtomic,
      GIM_CheckRegBankForClass, /*MI*/0, /*Op*/0, /*RC*/GIMT_Encode2(AMDGPU::AV_128RegClassID),
      GIM_CheckPointerToAny, /*MI*/0, /*Op*/1, /*SizeInBits*/0,
      GIM_CheckComplexPattern, /*MI*/0, /*Op*/1, /*Renderer*/GIMT_Encode2(0), GIMT_Encode2(GICP_gi_ds_1addr_1offset),
      // (AMDGPUld_glue:{ *:[v4f32] } (DS1Addr1Offset:{ *:[iPTR] } i32:{ *:[i32] }:$ptr, i32:{ *:[i32] }:$offset))<<P:Predicate_unindexedload_glue>><<P:Predicate_load_glue>><<P:Predicate_load_local_m0>><<P:Predicate_load_align16_local_m0>>  =>  (DS_READ_B128:{ *:[v4f32] } ?:{ *:[i32] }:$ptr, offset:{ *:[i32] }:$offset, 0:{ *:[i1] })
      GIR_BuildMI, /*InsnID*/0, /*Opcode*/GIMT_Encode2(AMDGPU::DS_READ_B128),
      GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/0, // DstI[vdst]
      GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/0, // ptr
      GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/1, // offset
      GIR_AddImm8, /*InsnID*/0, /*Imm*/0,
      GIR_MergeMemOperands, /*InsnID*/0, /*NumInsns*/1, /*MergeInsnID's*/0,
      GIR_ConstrainSelectedInstOperands, /*InsnID*/0,
      GIR_EraseFromParent, /*InsnID*/0,
      // GIR_Coverage, 6791,
      GIR_Done,
    // Label 1481: @98390
    GIM_Try, /*On fail goto*//*Label 1482*/ GIMT_Encode4(98452), // Rule ID 2558 //
      GIM_CheckMemorySizeEqualToLLT, /*MI*/0, /*MMO*/0, /*OpIdx*/0,
      GIM_CheckAtomicOrdering, /*MI*/0, /*Order*/(uint8_t)AtomicOrdering::NotAtomic,
      GIM_CheckRegBankForClass, /*MI*/0, /*Op*/0, /*RC*/GIMT_Encode2(AMDGPU::SReg_128RegClassID),
      GIM_CheckPointerToAny, /*MI*/0, /*Op*/1, /*SizeInBits*/0,
      GIM_CheckCxxInsnPredicate, /*MI*/0, /*FnId*/GIMT_Encode2(GICXXPred_MI_Predicate_smrd_load),
      GIM_CheckComplexPattern, /*MI*/0, /*Op*/1, /*Renderer*/GIMT_Encode2(0), GIMT_Encode2(GICP_gi_smrd_imm),
      // (ld:{ *:[v4i32] } (SMRDImm:{ *:[iPTR] } i64:{ *:[i64] }:$sbase, i32:{ *:[i32] }:$offset))<<P:Predicate_unindexedload>><<P:Predicate_load>><<P:Predicate_smrd_load>>  =>  (S_LOAD_DWORDX4_IMM:{ *:[v4i32] } ?:{ *:[i64] }:$sbase, ?:{ *:[i32] }:$offset, 0:{ *:[i32] })
      GIR_BuildMI, /*InsnID*/0, /*Opcode*/GIMT_Encode2(AMDGPU::S_LOAD_DWORDX4_IMM),
      GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/0, // DstI[sdst]
      GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/0, // sbase
      GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/1, // offset
      GIR_AddImm8, /*InsnID*/0, /*Imm*/0,
      GIR_MergeMemOperands, /*InsnID*/0, /*NumInsns*/1, /*MergeInsnID's*/0,
      GIR_ConstrainSelectedInstOperands, /*InsnID*/0,
      GIR_EraseFromParent, /*InsnID*/0,
      // GIR_Coverage, 2558,
      GIR_Done,
    // Label 1482: @98452
    GIM_Try, /*On fail goto*//*Label 1483*/ GIMT_Encode4(98517), // Rule ID 2559 //
      GIM_CheckFeatures, GIMT_Encode2(GIFBS_isGFX7Only),
      GIM_CheckMemorySizeEqualToLLT, /*MI*/0, /*MMO*/0, /*OpIdx*/0,
      GIM_CheckAtomicOrdering, /*MI*/0, /*Order*/(uint8_t)AtomicOrdering::NotAtomic,
      GIM_CheckRegBankForClass, /*MI*/0, /*Op*/0, /*RC*/GIMT_Encode2(AMDGPU::SReg_128RegClassID),
      GIM_CheckPointerToAny, /*MI*/0, /*Op*/1, /*SizeInBits*/0,
      GIM_CheckCxxInsnPredicate, /*MI*/0, /*FnId*/GIMT_Encode2(GICXXPred_MI_Predicate_smrd_load),
      GIM_CheckComplexPattern, /*MI*/0, /*Op*/1, /*Renderer*/GIMT_Encode2(0), GIMT_Encode2(GICP_gi_smrd_imm32),
      // (ld:{ *:[v4i32] } (SMRDImm32:{ *:[iPTR] } i64:{ *:[i64] }:$sbase, i32:{ *:[i32] }:$offset))<<P:Predicate_unindexedload>><<P:Predicate_load>><<P:Predicate_smrd_load>>  =>  (S_LOAD_DWORDX4_IMM_ci:{ *:[v4i32] } ?:{ *:[i64] }:$sbase, ?:{ *:[i32] }:$offset, 0:{ *:[i32] })
      GIR_BuildMI, /*InsnID*/0, /*Opcode*/GIMT_Encode2(AMDGPU::S_LOAD_DWORDX4_IMM_ci),
      GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/0, // DstI[sdst]
      GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/0, // sbase
      GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/1, // offset
      GIR_AddImm8, /*InsnID*/0, /*Imm*/0,
      GIR_MergeMemOperands, /*InsnID*/0, /*NumInsns*/1, /*MergeInsnID's*/0,
      GIR_ConstrainSelectedInstOperands, /*InsnID*/0,
      GIR_EraseFromParent, /*InsnID*/0,
      // GIR_Coverage, 2559,
      GIR_Done,
    // Label 1483: @98517
    GIM_Try, /*On fail goto*//*Label 1484*/ GIMT_Encode4(98582), // Rule ID 2560 //
      GIM_CheckFeatures, GIMT_Encode2(GIFBS_isNotGFX9Plus),
      GIM_CheckMemorySizeEqualToLLT, /*MI*/0, /*MMO*/0, /*OpIdx*/0,
      GIM_CheckAtomicOrdering, /*MI*/0, /*Order*/(uint8_t)AtomicOrdering::NotAtomic,
      GIM_CheckRegBankForClass, /*MI*/0, /*Op*/0, /*RC*/GIMT_Encode2(AMDGPU::SReg_128RegClassID),
      GIM_CheckPointerToAny, /*MI*/0, /*Op*/1, /*SizeInBits*/0,
      GIM_CheckCxxInsnPredicate, /*MI*/0, /*FnId*/GIMT_Encode2(GICXXPred_MI_Predicate_smrd_load),
      GIM_CheckComplexPattern, /*MI*/0, /*Op*/1, /*Renderer*/GIMT_Encode2(0), GIMT_Encode2(GICP_gi_smrd_sgpr),
      // (ld:{ *:[v4i32] } (SMRDSgpr:{ *:[iPTR] } i64:{ *:[i64] }:$sbase, i32:{ *:[i32] }:$soffset))<<P:Predicate_unindexedload>><<P:Predicate_load>><<P:Predicate_smrd_load>>  =>  (S_LOAD_DWORDX4_SGPR:{ *:[v4i32] } ?:{ *:[i64] }:$sbase, ?:{ *:[i32] }:$soffset, 0:{ *:[i32] })
      GIR_BuildMI, /*InsnID*/0, /*Opcode*/GIMT_Encode2(AMDGPU::S_LOAD_DWORDX4_SGPR),
      GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/0, // DstI[sdst]
      GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/0, // sbase
      GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/1, // soffset
      GIR_AddImm8, /*InsnID*/0, /*Imm*/0,
      GIR_MergeMemOperands, /*InsnID*/0, /*NumInsns*/1, /*MergeInsnID's*/0,
      GIR_ConstrainSelectedInstOperands, /*InsnID*/0,
      GIR_EraseFromParent, /*InsnID*/0,
      // GIR_Coverage, 2560,
      GIR_Done,
    // Label 1484: @98582
    GIM_Try, /*On fail goto*//*Label 1485*/ GIMT_Encode4(98650), // Rule ID 2561 //
      GIM_CheckFeatures, GIMT_Encode2(GIFBS_isGFX9Plus),
      GIM_CheckMemorySizeEqualToLLT, /*MI*/0, /*MMO*/0, /*OpIdx*/0,
      GIM_CheckAtomicOrdering, /*MI*/0, /*Order*/(uint8_t)AtomicOrdering::NotAtomic,
      GIM_CheckRegBankForClass, /*MI*/0, /*Op*/0, /*RC*/GIMT_Encode2(AMDGPU::SReg_128RegClassID),
      GIM_CheckPointerToAny, /*MI*/0, /*Op*/1, /*SizeInBits*/0,
      GIM_CheckCxxInsnPredicate, /*MI*/0, /*FnId*/GIMT_Encode2(GICXXPred_MI_Predicate_smrd_load),
      GIM_CheckComplexPattern, /*MI*/0, /*Op*/1, /*Renderer*/GIMT_Encode2(0), GIMT_Encode2(GICP_gi_smrd_sgpr),
      // (ld:{ *:[v4i32] } (SMRDSgpr:{ *:[iPTR] } i64:{ *:[i64] }:$sbase, i32:{ *:[i32] }:$soffset))<<P:Predicate_unindexedload>><<P:Predicate_load>><<P:Predicate_smrd_load>>  =>  (S_LOAD_DWORDX4_SGPR_IMM:{ *:[v4i32] } ?:{ *:[i64] }:$sbase, ?:{ *:[i32] }:$soffset, 0:{ *:[i32] }, 0:{ *:[i32] })
      GIR_BuildMI, /*InsnID*/0, /*Opcode*/GIMT_Encode2(AMDGPU::S_LOAD_DWORDX4_SGPR_IMM),
      GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/0, // DstI[sdst]
      GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/0, // sbase
      GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/1, // soffset
      GIR_AddImm8, /*InsnID*/0, /*Imm*/0,
      GIR_AddImm8, /*InsnID*/0, /*Imm*/0,
      GIR_MergeMemOperands, /*InsnID*/0, /*NumInsns*/1, /*MergeInsnID's*/0,
      GIR_ConstrainSelectedInstOperands, /*InsnID*/0,
      GIR_EraseFromParent, /*InsnID*/0,
      // GIR_Coverage, 2561,
      GIR_Done,
    // Label 1485: @98650
    GIM_Try, /*On fail goto*//*Label 1486*/ GIMT_Encode4(98712), // Rule ID 2564 //
      GIM_CheckMemorySizeEqualToLLT, /*MI*/0, /*MMO*/0, /*OpIdx*/0,
      GIM_CheckAtomicOrdering, /*MI*/0, /*Order*/(uint8_t)AtomicOrdering::NotAtomic,
      GIM_CheckRegBankForClass, /*MI*/0, /*Op*/0, /*RC*/GIMT_Encode2(AMDGPU::SReg_128RegClassID),
      GIM_CheckPointerToAny, /*MI*/0, /*Op*/1, /*SizeInBits*/0,
      GIM_CheckCxxInsnPredicate, /*MI*/0, /*FnId*/GIMT_Encode2(GICXXPred_MI_Predicate_smrd_load),
      GIM_CheckComplexPattern, /*MI*/0, /*Op*/1, /*Renderer*/GIMT_Encode2(0), GIMT_Encode2(GICP_gi_smrd_imm),
      // (ld:{ *:[v4f32] } (SMRDImm:{ *:[iPTR] } i64:{ *:[i64] }:$sbase, i32:{ *:[i32] }:$offset))<<P:Predicate_unindexedload>><<P:Predicate_load>><<P:Predicate_smrd_load>>  =>  (S_LOAD_DWORDX4_IMM:{ *:[v4f32] } ?:{ *:[i64] }:$sbase, ?:{ *:[i32] }:$offset, 0:{ *:[i32] })
      GIR_BuildMI, /*InsnID*/0, /*Opcode*/GIMT_Encode2(AMDGPU::S_LOAD_DWORDX4_IMM),
      GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/0, // DstI[sdst]
      GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/0, // sbase
      GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/1, // offset
      GIR_AddImm8, /*InsnID*/0, /*Imm*/0,
      GIR_MergeMemOperands, /*InsnID*/0, /*NumInsns*/1, /*MergeInsnID's*/0,
      GIR_ConstrainSelectedInstOperands, /*InsnID*/0,
      GIR_EraseFromParent, /*InsnID*/0,
      // GIR_Coverage, 2564,
      GIR_Done,
    // Label 1486: @98712
    GIM_Try, /*On fail goto*//*Label 1487*/ GIMT_Encode4(98777), // Rule ID 2565 //
      GIM_CheckFeatures, GIMT_Encode2(GIFBS_isGFX7Only),
      GIM_CheckMemorySizeEqualToLLT, /*MI*/0, /*MMO*/0, /*OpIdx*/0,
      GIM_CheckAtomicOrdering, /*MI*/0, /*Order*/(uint8_t)AtomicOrdering::NotAtomic,
      GIM_CheckRegBankForClass, /*MI*/0, /*Op*/0, /*RC*/GIMT_Encode2(AMDGPU::SReg_128RegClassID),
      GIM_CheckPointerToAny, /*MI*/0, /*Op*/1, /*SizeInBits*/0,
      GIM_CheckCxxInsnPredicate, /*MI*/0, /*FnId*/GIMT_Encode2(GICXXPred_MI_Predicate_smrd_load),
      GIM_CheckComplexPattern, /*MI*/0, /*Op*/1, /*Renderer*/GIMT_Encode2(0), GIMT_Encode2(GICP_gi_smrd_imm32),
      // (ld:{ *:[v4f32] } (SMRDImm32:{ *:[iPTR] } i64:{ *:[i64] }:$sbase, i32:{ *:[i32] }:$offset))<<P:Predicate_unindexedload>><<P:Predicate_load>><<P:Predicate_smrd_load>>  =>  (S_LOAD_DWORDX4_IMM_ci:{ *:[v4f32] } ?:{ *:[i64] }:$sbase, ?:{ *:[i32] }:$offset, 0:{ *:[i32] })
      GIR_BuildMI, /*InsnID*/0, /*Opcode*/GIMT_Encode2(AMDGPU::S_LOAD_DWORDX4_IMM_ci),
      GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/0, // DstI[sdst]
      GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/0, // sbase
      GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/1, // offset
      GIR_AddImm8, /*InsnID*/0, /*Imm*/0,
      GIR_MergeMemOperands, /*InsnID*/0, /*NumInsns*/1, /*MergeInsnID's*/0,
      GIR_ConstrainSelectedInstOperands, /*InsnID*/0,
      GIR_EraseFromParent, /*InsnID*/0,
      // GIR_Coverage, 2565,
      GIR_Done,
    // Label 1487: @98777
    GIM_Try, /*On fail goto*//*Label 1488*/ GIMT_Encode4(98842), // Rule ID 2566 //
      GIM_CheckFeatures, GIMT_Encode2(GIFBS_isNotGFX9Plus),
      GIM_CheckMemorySizeEqualToLLT, /*MI*/0, /*MMO*/0, /*OpIdx*/0,
      GIM_CheckAtomicOrdering, /*MI*/0, /*Order*/(uint8_t)AtomicOrdering::NotAtomic,
      GIM_CheckRegBankForClass, /*MI*/0, /*Op*/0, /*RC*/GIMT_Encode2(AMDGPU::SReg_128RegClassID),
      GIM_CheckPointerToAny, /*MI*/0, /*Op*/1, /*SizeInBits*/0,
      GIM_CheckCxxInsnPredicate, /*MI*/0, /*FnId*/GIMT_Encode2(GICXXPred_MI_Predicate_smrd_load),
      GIM_CheckComplexPattern, /*MI*/0, /*Op*/1, /*Renderer*/GIMT_Encode2(0), GIMT_Encode2(GICP_gi_smrd_sgpr),
      // (ld:{ *:[v4f32] } (SMRDSgpr:{ *:[iPTR] } i64:{ *:[i64] }:$sbase, i32:{ *:[i32] }:$soffset))<<P:Predicate_unindexedload>><<P:Predicate_load>><<P:Predicate_smrd_load>>  =>  (S_LOAD_DWORDX4_SGPR:{ *:[v4f32] } ?:{ *:[i64] }:$sbase, ?:{ *:[i32] }:$soffset, 0:{ *:[i32] })
      GIR_BuildMI, /*InsnID*/0, /*Opcode*/GIMT_Encode2(AMDGPU::S_LOAD_DWORDX4_SGPR),
      GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/0, // DstI[sdst]
      GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/0, // sbase
      GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/1, // soffset
      GIR_AddImm8, /*InsnID*/0, /*Imm*/0,
      GIR_MergeMemOperands, /*InsnID*/0, /*NumInsns*/1, /*MergeInsnID's*/0,
      GIR_ConstrainSelectedInstOperands, /*InsnID*/0,
      GIR_EraseFromParent, /*InsnID*/0,
      // GIR_Coverage, 2566,
      GIR_Done,
    // Label 1488: @98842
    GIM_Try, /*On fail goto*//*Label 1489*/ GIMT_Encode4(98910), // Rule ID 2567 //
      GIM_CheckFeatures, GIMT_Encode2(GIFBS_isGFX9Plus),
      GIM_CheckMemorySizeEqualToLLT, /*MI*/0, /*MMO*/0, /*OpIdx*/0,
      GIM_CheckAtomicOrdering, /*MI*/0, /*Order*/(uint8_t)AtomicOrdering::NotAtomic,
      GIM_CheckRegBankForClass, /*MI*/0, /*Op*/0, /*RC*/GIMT_Encode2(AMDGPU::SReg_128RegClassID),
      GIM_CheckPointerToAny, /*MI*/0, /*Op*/1, /*SizeInBits*/0,
      GIM_CheckCxxInsnPredicate, /*MI*/0, /*FnId*/GIMT_Encode2(GICXXPred_MI_Predicate_smrd_load),
      GIM_CheckComplexPattern, /*MI*/0, /*Op*/1, /*Renderer*/GIMT_Encode2(0), GIMT_Encode2(GICP_gi_smrd_sgpr),
      // (ld:{ *:[v4f32] } (SMRDSgpr:{ *:[iPTR] } i64:{ *:[i64] }:$sbase, i32:{ *:[i32] }:$soffset))<<P:Predicate_unindexedload>><<P:Predicate_load>><<P:Predicate_smrd_load>>  =>  (S_LOAD_DWORDX4_SGPR_IMM:{ *:[v4f32] } ?:{ *:[i64] }:$sbase, ?:{ *:[i32] }:$soffset, 0:{ *:[i32] }, 0:{ *:[i32] })
      GIR_BuildMI, /*InsnID*/0, /*Opcode*/GIMT_Encode2(AMDGPU::S_LOAD_DWORDX4_SGPR_IMM),
      GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/0, // DstI[sdst]
      GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/0, // sbase
      GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/1, // soffset
      GIR_AddImm8, /*InsnID*/0, /*Imm*/0,
      GIR_AddImm8, /*InsnID*/0, /*Imm*/0,
      GIR_MergeMemOperands, /*InsnID*/0, /*NumInsns*/1, /*MergeInsnID's*/0,
      GIR_ConstrainSelectedInstOperands, /*InsnID*/0,
      GIR_EraseFromParent, /*InsnID*/0,
      // GIR_Coverage, 2567,
      GIR_Done,
    // Label 1489: @98910
    GIM_Try, /*On fail goto*//*Label 1490*/ GIMT_Encode4(98981), // Rule ID 6864 //
      GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasUnalignedAccessMode_NotLDSRequiresM0Init),
      GIM_CheckMemoryAddressSpace, /*MI*/0, /*MMO*/0, /*NumAddrSpace*/1, /*AddrSpace*/3,
      GIM_CheckMemoryAddressSpace, /*MI*/0, /*MMO*/0, /*NumAddrSpace*/1, /*AddrSpace*/3,
      GIM_CheckAtomicOrdering, /*MI*/0, /*Order*/(uint8_t)AtomicOrdering::NotAtomic,
      GIM_CheckRegBankForClass, /*MI*/0, /*Op*/0, /*RC*/GIMT_Encode2(AMDGPU::AV_128RegClassID),
      GIM_CheckPointerToAny, /*MI*/0, /*Op*/1, /*SizeInBits*/0,
      GIM_CheckCxxInsnPredicate, /*MI*/0, /*FnId*/GIMT_Encode2(GICXXPred_MI_Predicate_load_align_less_than_4_local),
      GIM_CheckComplexPattern, /*MI*/0, /*Op*/1, /*Renderer*/GIMT_Encode2(0), GIMT_Encode2(GICP_gi_ds_1addr_1offset),
      // (ld:{ *:[v4i32] } (DS1Addr1Offset:{ *:[iPTR] } i32:{ *:[i32] }:$ptr, i32:{ *:[i32] }:$offset))<<P:Predicate_unindexedload>><<P:Predicate_load_local>><<P:Predicate_load_align_less_than_4_local>>  =>  (DS_READ_B128_gfx9:{ *:[v4i32] } ?:{ *:[i32] }:$ptr, offset:{ *:[i32] }:$offset, 0:{ *:[i1] })
      GIR_BuildMI, /*InsnID*/0, /*Opcode*/GIMT_Encode2(AMDGPU::DS_READ_B128_gfx9),
      GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/0, // DstI[vdst]
      GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/0, // ptr
      GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/1, // offset
      GIR_AddImm8, /*InsnID*/0, /*Imm*/0,
      GIR_MergeMemOperands, /*InsnID*/0, /*NumInsns*/1, /*MergeInsnID's*/0,
      GIR_ConstrainSelectedInstOperands, /*InsnID*/0,
      GIR_EraseFromParent, /*InsnID*/0,
      // GIR_Coverage, 6864,
      GIR_Done,
    // Label 1490: @98981
    GIM_Try, /*On fail goto*//*Label 1491*/ GIMT_Encode4(99052), // Rule ID 6868 //
      GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasUnalignedAccessMode_NotLDSRequiresM0Init),
      GIM_CheckMemoryAddressSpace, /*MI*/0, /*MMO*/0, /*NumAddrSpace*/1, /*AddrSpace*/3,
      GIM_CheckMemoryAddressSpace, /*MI*/0, /*MMO*/0, /*NumAddrSpace*/1, /*AddrSpace*/3,
      GIM_CheckAtomicOrdering, /*MI*/0, /*Order*/(uint8_t)AtomicOrdering::NotAtomic,
      GIM_CheckRegBankForClass, /*MI*/0, /*Op*/0, /*RC*/GIMT_Encode2(AMDGPU::AV_128RegClassID),
      GIM_CheckPointerToAny, /*MI*/0, /*Op*/1, /*SizeInBits*/0,
      GIM_CheckCxxInsnPredicate, /*MI*/0, /*FnId*/GIMT_Encode2(GICXXPred_MI_Predicate_load_align_less_than_4_local),
      GIM_CheckComplexPattern, /*MI*/0, /*Op*/1, /*Renderer*/GIMT_Encode2(0), GIMT_Encode2(GICP_gi_ds_1addr_1offset),
      // (ld:{ *:[v4f32] } (DS1Addr1Offset:{ *:[iPTR] } i32:{ *:[i32] }:$ptr, i32:{ *:[i32] }:$offset))<<P:Predicate_unindexedload>><<P:Predicate_load_local>><<P:Predicate_load_align_less_than_4_local>>  =>  (DS_READ_B128_gfx9:{ *:[v4f32] } ?:{ *:[i32] }:$ptr, offset:{ *:[i32] }:$offset, 0:{ *:[i1] })
      GIR_BuildMI, /*InsnID*/0, /*Opcode*/GIMT_Encode2(AMDGPU::DS_READ_B128_gfx9),
      GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/0, // DstI[vdst]
      GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/0, // ptr
      GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/1, // offset
      GIR_AddImm8, /*InsnID*/0, /*Imm*/0,
      GIR_MergeMemOperands, /*InsnID*/0, /*NumInsns*/1, /*MergeInsnID's*/0,
      GIR_ConstrainSelectedInstOperands, /*InsnID*/0,
      GIR_EraseFromParent, /*InsnID*/0,
      // GIR_Coverage, 6868,
      GIR_Done,
    // Label 1491: @99052
    GIM_Try, /*On fail goto*//*Label 1492*/ GIMT_Encode4(99118), // Rule ID 6788 //
      GIM_CheckFeatures, GIMT_Encode2(GIFBS_NotLDSRequiresM0Init_isGFX7Plus),
      GIM_CheckMemoryAddressSpace, /*MI*/0, /*MMO*/0, /*NumAddrSpace*/1, /*AddrSpace*/3,
      GIM_CheckMemoryAlignment, /*MI*/0, /*MMO*/0, /*MinAlign*/16,
      GIM_CheckAtomicOrdering, /*MI*/0, /*Order*/(uint8_t)AtomicOrdering::NotAtomic,
      GIM_CheckRegBankForClass, /*MI*/0, /*Op*/0, /*RC*/GIMT_Encode2(AMDGPU::AV_128RegClassID),
      GIM_CheckPointerToAny, /*MI*/0, /*Op*/1, /*SizeInBits*/0,
      GIM_CheckComplexPattern, /*MI*/0, /*Op*/1, /*Renderer*/GIMT_Encode2(0), GIMT_Encode2(GICP_gi_ds_1addr_1offset),
      // (ld:{ *:[v4i32] } (DS1Addr1Offset:{ *:[iPTR] } i32:{ *:[i32] }:$ptr, i32:{ *:[i32] }:$offset))<<P:Predicate_unindexedload>><<P:Predicate_load_local>><<P:Predicate_load_align16_local>>  =>  (DS_READ_B128_gfx9:{ *:[v4i32] } ?:{ *:[i32] }:$ptr, offset:{ *:[i32] }:$offset, 0:{ *:[i1] })
      GIR_BuildMI, /*InsnID*/0, /*Opcode*/GIMT_Encode2(AMDGPU::DS_READ_B128_gfx9),
      GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/0, // DstI[vdst]
      GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/0, // ptr
      GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/1, // offset
      GIR_AddImm8, /*InsnID*/0, /*Imm*/0,
      GIR_MergeMemOperands, /*InsnID*/0, /*NumInsns*/1, /*MergeInsnID's*/0,
      GIR_ConstrainSelectedInstOperands, /*InsnID*/0,
      GIR_EraseFromParent, /*InsnID*/0,
      // GIR_Coverage, 6788,
      GIR_Done,
    // Label 1492: @99118
    GIM_Try, /*On fail goto*//*Label 1493*/ GIMT_Encode4(99184), // Rule ID 6792 //
      GIM_CheckFeatures, GIMT_Encode2(GIFBS_NotLDSRequiresM0Init_isGFX7Plus),
      GIM_CheckMemoryAddressSpace, /*MI*/0, /*MMO*/0, /*NumAddrSpace*/1, /*AddrSpace*/3,
      GIM_CheckMemoryAlignment, /*MI*/0, /*MMO*/0, /*MinAlign*/16,
      GIM_CheckAtomicOrdering, /*MI*/0, /*Order*/(uint8_t)AtomicOrdering::NotAtomic,
      GIM_CheckRegBankForClass, /*MI*/0, /*Op*/0, /*RC*/GIMT_Encode2(AMDGPU::AV_128RegClassID),
      GIM_CheckPointerToAny, /*MI*/0, /*Op*/1, /*SizeInBits*/0,
      GIM_CheckComplexPattern, /*MI*/0, /*Op*/1, /*Renderer*/GIMT_Encode2(0), GIMT_Encode2(GICP_gi_ds_1addr_1offset),
      // (ld:{ *:[v4f32] } (DS1Addr1Offset:{ *:[iPTR] } i32:{ *:[i32] }:$ptr, i32:{ *:[i32] }:$offset))<<P:Predicate_unindexedload>><<P:Predicate_load_local>><<P:Predicate_load_align16_local>>  =>  (DS_READ_B128_gfx9:{ *:[v4f32] } ?:{ *:[i32] }:$ptr, offset:{ *:[i32] }:$offset, 0:{ *:[i1] })
      GIR_BuildMI, /*InsnID*/0, /*Opcode*/GIMT_Encode2(AMDGPU::DS_READ_B128_gfx9),
      GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/0, // DstI[vdst]
      GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/0, // ptr
      GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/1, // offset
      GIR_AddImm8, /*InsnID*/0, /*Imm*/0,
      GIR_MergeMemOperands, /*InsnID*/0, /*NumInsns*/1, /*MergeInsnID's*/0,
      GIR_ConstrainSelectedInstOperands, /*InsnID*/0,
      GIR_EraseFromParent, /*InsnID*/0,
      // GIR_Coverage, 6792,
      GIR_Done,
    // Label 1493: @99184
    GIM_Try, /*On fail goto*//*Label 1494*/ GIMT_Encode4(99241), // Rule ID 2563 //
      GIM_CheckMemorySizeEqualToLLT, /*MI*/0, /*MMO*/0, /*OpIdx*/0,
      GIM_CheckAtomicOrdering, /*MI*/0, /*Order*/(uint8_t)AtomicOrdering::NotAtomic,
      GIM_CheckRegBankForClass, /*MI*/0, /*Op*/0, /*RC*/GIMT_Encode2(AMDGPU::SReg_128RegClassID),
      // MIs[0] sbase
      GIM_CheckPointerToAny, /*MI*/0, /*Op*/1, /*SizeInBits*/64,
      GIM_CheckRegBankForClass, /*MI*/0, /*Op*/1, /*RC*/GIMT_Encode2(AMDGPU::SReg_64RegClassID),
      GIM_CheckCxxInsnPredicate, /*MI*/0, /*FnId*/GIMT_Encode2(GICXXPred_MI_Predicate_smrd_load),
      // (ld:{ *:[v4i32] } SReg_64:{ *:[i64] }:$sbase)<<P:Predicate_unindexedload>><<P:Predicate_load>><<P:Predicate_smrd_load>>  =>  (S_LOAD_DWORDX4_IMM:{ *:[v4i32] } i64:{ *:[i64] }:$sbase, 0:{ *:[i32] }, 0:{ *:[i32] })
      GIR_BuildMI, /*InsnID*/0, /*Opcode*/GIMT_Encode2(AMDGPU::S_LOAD_DWORDX4_IMM),
      GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/0, // DstI[sdst]
      GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/1, // sbase
      GIR_AddImm8, /*InsnID*/0, /*Imm*/0,
      GIR_AddImm8, /*InsnID*/0, /*Imm*/0,
      GIR_MergeMemOperands, /*InsnID*/0, /*NumInsns*/1, /*MergeInsnID's*/0,
      GIR_ConstrainSelectedInstOperands, /*InsnID*/0,
      GIR_EraseFromParent, /*InsnID*/0,
      // GIR_Coverage, 2563,
      GIR_Done,
    // Label 1494: @99241
    GIM_Try, /*On fail goto*//*Label 1495*/ GIMT_Encode4(99298), // Rule ID 2569 //
      GIM_CheckMemorySizeEqualToLLT, /*MI*/0, /*MMO*/0, /*OpIdx*/0,
      GIM_CheckAtomicOrdering, /*MI*/0, /*Order*/(uint8_t)AtomicOrdering::NotAtomic,
      GIM_CheckRegBankForClass, /*MI*/0, /*Op*/0, /*RC*/GIMT_Encode2(AMDGPU::SReg_128RegClassID),
      // MIs[0] sbase
      GIM_CheckPointerToAny, /*MI*/0, /*Op*/1, /*SizeInBits*/64,
      GIM_CheckRegBankForClass, /*MI*/0, /*Op*/1, /*RC*/GIMT_Encode2(AMDGPU::SReg_64RegClassID),
      GIM_CheckCxxInsnPredicate, /*MI*/0, /*FnId*/GIMT_Encode2(GICXXPred_MI_Predicate_smrd_load),
      // (ld:{ *:[v4f32] } SReg_64:{ *:[i64] }:$sbase)<<P:Predicate_unindexedload>><<P:Predicate_load>><<P:Predicate_smrd_load>>  =>  (S_LOAD_DWORDX4_IMM:{ *:[v4f32] } i64:{ *:[i64] }:$sbase, 0:{ *:[i32] }, 0:{ *:[i32] })
      GIR_BuildMI, /*InsnID*/0, /*Opcode*/GIMT_Encode2(AMDGPU::S_LOAD_DWORDX4_IMM),
      GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/0, // DstI[sdst]
      GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/1, // sbase
      GIR_AddImm8, /*InsnID*/0, /*Imm*/0,
      GIR_AddImm8, /*InsnID*/0, /*Imm*/0,
      GIR_MergeMemOperands, /*InsnID*/0, /*NumInsns*/1, /*MergeInsnID's*/0,
      GIR_ConstrainSelectedInstOperands, /*InsnID*/0,
      GIR_EraseFromParent, /*InsnID*/0,
      // GIR_Coverage, 2569,
      GIR_Done,
    // Label 1495: @99298
    GIM_Try, /*On fail goto*//*Label 1496*/ GIMT_Encode4(99368), // Rule ID 5432 //
      GIM_CheckFeatures, GIMT_Encode2(GIFBS_DisableFlatScratch_HasUnrestrictedSOffset),
      GIM_CheckMemoryAddressSpace, /*MI*/0, /*MMO*/0, /*NumAddrSpace*/1, /*AddrSpace*/5,
      GIM_CheckAtomicOrdering, /*MI*/0, /*Order*/(uint8_t)AtomicOrdering::NotAtomic,
      GIM_CheckRegBankForClass, /*MI*/0, /*Op*/0, /*RC*/GIMT_Encode2(AMDGPU::AV_128RegClassID),
      GIM_CheckPointerToAny, /*MI*/0, /*Op*/1, /*SizeInBits*/0,
      GIM_CheckComplexPattern, /*MI*/0, /*Op*/1, /*Renderer*/GIMT_Encode2(0), GIMT_Encode2(GICP_gi_mubuf_scratch_offset),
      // (ld:{ *:[v4i32] } (MUBUFScratchOffset:{ *:[iPTR] } v4i32:{ *:[v4i32] }:$srsrc, i32:{ *:[i32] }:$soffset, i32:{ *:[i32] }:$offset))<<P:Predicate_unindexedload>><<P:Predicate_load_private>>  =>  (BUFFER_LOAD_DWORDX4_OFFSET:{ *:[v4i32] } ?:{ *:[v4i32] }:$srsrc, ?:{ *:[i32] }:$soffset, ?:{ *:[i32] }:$offset, 0:{ *:[i32] }, 0:{ *:[i1] })
      GIR_BuildMI, /*InsnID*/0, /*Opcode*/GIMT_Encode2(AMDGPU::BUFFER_LOAD_DWORDX4_OFFSET),
      GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/0, // DstI[vdata]
      GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/0, // srsrc
      GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/1, // soffset
      GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/2, // offset
      GIR_AddImm8, /*InsnID*/0, /*Imm*/0,
      GIR_AddImm8, /*InsnID*/0, /*Imm*/0,
      GIR_MergeMemOperands, /*InsnID*/0, /*NumInsns*/1, /*MergeInsnID's*/0,
      GIR_ConstrainSelectedInstOperands, /*InsnID*/0,
      GIR_EraseFromParent, /*InsnID*/0,
      // GIR_Coverage, 5432,
      GIR_Done,
    // Label 1496: @99368
    GIM_Try, /*On fail goto*//*Label 1497*/ GIMT_Encode4(99438), // Rule ID 5434 //
      GIM_CheckFeatures, GIMT_Encode2(GIFBS_DisableFlatScratch),
      GIM_CheckMemoryAddressSpace, /*MI*/0, /*MMO*/0, /*NumAddrSpace*/1, /*AddrSpace*/5,
      GIM_CheckAtomicOrdering, /*MI*/0, /*Order*/(uint8_t)AtomicOrdering::NotAtomic,
      GIM_CheckRegBankForClass, /*MI*/0, /*Op*/0, /*RC*/GIMT_Encode2(AMDGPU::AV_128RegClassID),
      GIM_CheckPointerToAny, /*MI*/0, /*Op*/1, /*SizeInBits*/0,
      GIM_CheckComplexPattern, /*MI*/0, /*Op*/1, /*Renderer*/GIMT_Encode2(0), GIMT_Encode2(GICP_gi_mubuf_scratch_offset),
      // (ld:{ *:[v4i32] } (MUBUFScratchOffset:{ *:[iPTR] } v4i32:{ *:[v4i32] }:$srsrc, i32:{ *:[i32] }:$soffset, i32:{ *:[i32] }:$offset))<<P:Predicate_unindexedload>><<P:Predicate_load_private>>  =>  (BUFFER_LOAD_DWORDX4_VBUFFER_OFFSET:{ *:[v4i32] } ?:{ *:[v4i32] }:$srsrc, ?:{ *:[i32] }:$soffset, ?:{ *:[i32] }:$offset, 0:{ *:[i32] }, 0:{ *:[i1] })
      GIR_BuildMI, /*InsnID*/0, /*Opcode*/GIMT_Encode2(AMDGPU::BUFFER_LOAD_DWORDX4_VBUFFER_OFFSET),
      GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/0, // DstI[vdata]
      GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/0, // srsrc
      GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/1, // soffset
      GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/2, // offset
      GIR_AddImm8, /*InsnID*/0, /*Imm*/0,
      GIR_AddImm8, /*InsnID*/0, /*Imm*/0,
      GIR_MergeMemOperands, /*InsnID*/0, /*NumInsns*/1, /*MergeInsnID's*/0,
      GIR_ConstrainSelectedInstOperands, /*InsnID*/0,
      GIR_EraseFromParent, /*InsnID*/0,
      // GIR_Coverage, 5434,
      GIR_Done,
    // Label 1497: @99438
    GIM_Try, /*On fail goto*//*Label 1498*/ GIMT_Encode4(99505), // Rule ID 3547 //
      GIM_CheckFeatures, GIMT_Encode2(GIFBS_EnableFlatScratch_HasFlatScratchInsts_HasFlatScratchSVSMode),
      GIM_CheckMemoryAddressSpace, /*MI*/0, /*MMO*/0, /*NumAddrSpace*/1, /*AddrSpace*/5,
      GIM_CheckAtomicOrdering, /*MI*/0, /*Order*/(uint8_t)AtomicOrdering::NotAtomic,
      GIM_CheckRegBankForClass, /*MI*/0, /*Op*/0, /*RC*/GIMT_Encode2(AMDGPU::AV_128RegClassID),
      GIM_CheckPointerToAny, /*MI*/0, /*Op*/1, /*SizeInBits*/0,
      GIM_CheckComplexPattern, /*MI*/0, /*Op*/1, /*Renderer*/GIMT_Encode2(0), GIMT_Encode2(GICP_gi_flat_scratch_svaddr),
      // (ld:{ *:[v4i32] } (ScratchSVAddr:{ *:[iPTR] } VGPR_32:{ *:[i32] }:$vaddr, SGPR_32:{ *:[i32] }:$saddr, i32:{ *:[i32] }:$offset))<<P:Predicate_unindexedload>><<P:Predicate_load_private>>  =>  (SCRATCH_LOAD_DWORDX4_SVS:{ *:[v4i32] } ?:{ *:[i32] }:$vaddr, ?:{ *:[i32] }:$saddr, ?:{ *:[i32] }:$offset, 0:{ *:[i32] })
      GIR_BuildMI, /*InsnID*/0, /*Opcode*/GIMT_Encode2(AMDGPU::SCRATCH_LOAD_DWORDX4_SVS),
      GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/0, // DstI[vdst]
      GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/0, // vaddr
      GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/1, // saddr
      GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/2, // offset
      GIR_AddImm8, /*InsnID*/0, /*Imm*/0,
      GIR_MergeMemOperands, /*InsnID*/0, /*NumInsns*/1, /*MergeInsnID's*/0,
      GIR_ConstrainSelectedInstOperands, /*InsnID*/0,
      GIR_EraseFromParent, /*InsnID*/0,
      // GIR_Coverage, 3547,
      GIR_Done,
    // Label 1498: @99505
    GIM_Try, /*On fail goto*//*Label 1499*/ GIMT_Encode4(99572), // Rule ID 3553 //
      GIM_CheckFeatures, GIMT_Encode2(GIFBS_EnableFlatScratch_HasFlatScratchInsts_HasFlatScratchSVSMode),
      GIM_CheckMemoryAddressSpace, /*MI*/0, /*MMO*/0, /*NumAddrSpace*/1, /*AddrSpace*/5,
      GIM_CheckAtomicOrdering, /*MI*/0, /*Order*/(uint8_t)AtomicOrdering::NotAtomic,
      GIM_CheckRegBankForClass, /*MI*/0, /*Op*/0, /*RC*/GIMT_Encode2(AMDGPU::AV_128RegClassID),
      GIM_CheckPointerToAny, /*MI*/0, /*Op*/1, /*SizeInBits*/0,
      GIM_CheckComplexPattern, /*MI*/0, /*Op*/1, /*Renderer*/GIMT_Encode2(0), GIMT_Encode2(GICP_gi_flat_scratch_svaddr),
      // (ld:{ *:[v4f32] } (ScratchSVAddr:{ *:[iPTR] } VGPR_32:{ *:[i32] }:$vaddr, SGPR_32:{ *:[i32] }:$saddr, i32:{ *:[i32] }:$offset))<<P:Predicate_unindexedload>><<P:Predicate_load_private>>  =>  (SCRATCH_LOAD_DWORDX4_SVS:{ *:[v4f32] } ?:{ *:[i32] }:$vaddr, ?:{ *:[i32] }:$saddr, ?:{ *:[i32] }:$offset, 0:{ *:[i32] })
      GIR_BuildMI, /*InsnID*/0, /*Opcode*/GIMT_Encode2(AMDGPU::SCRATCH_LOAD_DWORDX4_SVS),
      GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/0, // DstI[vdst]
      GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/0, // vaddr
      GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/1, // saddr
      GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/2, // offset
      GIR_AddImm8, /*InsnID*/0, /*Imm*/0,
      GIR_MergeMemOperands, /*InsnID*/0, /*NumInsns*/1, /*MergeInsnID's*/0,
      GIR_ConstrainSelectedInstOperands, /*InsnID*/0,
      GIR_EraseFromParent, /*InsnID*/0,
      // GIR_Coverage, 3553,
      GIR_Done,
    // Label 1499: @99572
    GIM_Try, /*On fail goto*//*Label 1500*/ GIMT_Encode4(99634), // Rule ID 3546 //
      GIM_CheckFeatures, GIMT_Encode2(GIFBS_EnableFlatScratch_HasFlatScratchInsts),
      GIM_CheckMemoryAddressSpace, /*MI*/0, /*MMO*/0, /*NumAddrSpace*/1, /*AddrSpace*/5,
      GIM_CheckAtomicOrdering, /*MI*/0, /*Order*/(uint8_t)AtomicOrdering::NotAtomic,
      GIM_CheckRegBankForClass, /*MI*/0, /*Op*/0, /*RC*/GIMT_Encode2(AMDGPU::AV_128RegClassID),
      GIM_CheckPointerToAny, /*MI*/0, /*Op*/1, /*SizeInBits*/0,
      GIM_CheckComplexPattern, /*MI*/0, /*Op*/1, /*Renderer*/GIMT_Encode2(0), GIMT_Encode2(GICP_gi_flat_scratch_saddr),
      // (ld:{ *:[v4i32] } (ScratchSAddr:{ *:[iPTR] } SGPR_32:{ *:[i32] }:$saddr, i32:{ *:[i32] }:$offset))<<P:Predicate_unindexedload>><<P:Predicate_load_private>>  =>  (SCRATCH_LOAD_DWORDX4_SADDR:{ *:[v4i32] } ?:{ *:[i32] }:$saddr, ?:{ *:[i32] }:$offset)
      GIR_BuildMI, /*InsnID*/0, /*Opcode*/GIMT_Encode2(AMDGPU::SCRATCH_LOAD_DWORDX4_SADDR),
      GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/0, // DstI[vdst]
      GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/0, // saddr
      GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/1, // offset
      GIR_AddImm8, /*InsnID*/0, /*Imm*/0,
      GIR_MergeMemOperands, /*InsnID*/0, /*NumInsns*/1, /*MergeInsnID's*/0,
      GIR_ConstrainSelectedInstOperands, /*InsnID*/0,
      GIR_EraseFromParent, /*InsnID*/0,
      // GIR_Coverage, 3546,
      GIR_Done,
    // Label 1500: @99634
    GIM_Try, /*On fail goto*//*Label 1501*/ GIMT_Encode4(99696), // Rule ID 3552 //
      GIM_CheckFeatures, GIMT_Encode2(GIFBS_EnableFlatScratch_HasFlatScratchInsts),
      GIM_CheckMemoryAddressSpace, /*MI*/0, /*MMO*/0, /*NumAddrSpace*/1, /*AddrSpace*/5,
      GIM_CheckAtomicOrdering, /*MI*/0, /*Order*/(uint8_t)AtomicOrdering::NotAtomic,
      GIM_CheckRegBankForClass, /*MI*/0, /*Op*/0, /*RC*/GIMT_Encode2(AMDGPU::AV_128RegClassID),
      GIM_CheckPointerToAny, /*MI*/0, /*Op*/1, /*SizeInBits*/0,
      GIM_CheckComplexPattern, /*MI*/0, /*Op*/1, /*Renderer*/GIMT_Encode2(0), GIMT_Encode2(GICP_gi_flat_scratch_saddr),
      // (ld:{ *:[v4f32] } (ScratchSAddr:{ *:[iPTR] } SGPR_32:{ *:[i32] }:$saddr, i32:{ *:[i32] }:$offset))<<P:Predicate_unindexedload>><<P:Predicate_load_private>>  =>  (SCRATCH_LOAD_DWORDX4_SADDR:{ *:[v4f32] } ?:{ *:[i32] }:$saddr, ?:{ *:[i32] }:$offset)
      GIR_BuildMI, /*InsnID*/0, /*Opcode*/GIMT_Encode2(AMDGPU::SCRATCH_LOAD_DWORDX4_SADDR),
      GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/0, // DstI[vdst]
      GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/0, // saddr
      GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/1, // offset
      GIR_AddImm8, /*InsnID*/0, /*Imm*/0,
      GIR_MergeMemOperands, /*InsnID*/0, /*NumInsns*/1, /*MergeInsnID's*/0,
      GIR_ConstrainSelectedInstOperands, /*InsnID*/0,
      GIR_EraseFromParent, /*InsnID*/0,
      // GIR_Coverage, 3552,
      GIR_Done,
    // Label 1501: @99696
    GIM_Try, /*On fail goto*//*Label 1502*/ GIMT_Encode4(99758), // Rule ID 3545 //
      GIM_CheckFeatures, GIMT_Encode2(GIFBS_EnableFlatScratch_HasFlatScratchInsts),
      GIM_CheckMemoryAddressSpace, /*MI*/0, /*MMO*/0, /*NumAddrSpace*/1, /*AddrSpace*/5,
      GIM_CheckAtomicOrdering, /*MI*/0, /*Order*/(uint8_t)AtomicOrdering::NotAtomic,
      GIM_CheckRegBankForClass, /*MI*/0, /*Op*/0, /*RC*/GIMT_Encode2(AMDGPU::AV_128RegClassID),
      GIM_CheckPointerToAny, /*MI*/0, /*Op*/1, /*SizeInBits*/0,
      GIM_CheckComplexPattern, /*MI*/0, /*Op*/1, /*Renderer*/GIMT_Encode2(0), GIMT_Encode2(GICP_gi_flat_scratch_offset),
      // (ld:{ *:[v4i32] } (ScratchOffset:{ *:[iPTR] } VGPR_32:{ *:[i32] }:$vaddr, i32:{ *:[i32] }:$offset))<<P:Predicate_unindexedload>><<P:Predicate_load_private>>  =>  (SCRATCH_LOAD_DWORDX4:{ *:[v4i32] } ?:{ *:[i32] }:$vaddr, ?:{ *:[i32] }:$offset)
      GIR_BuildMI, /*InsnID*/0, /*Opcode*/GIMT_Encode2(AMDGPU::SCRATCH_LOAD_DWORDX4),
      GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/0, // DstI[vdst]
      GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/0, // vaddr
      GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/1, // offset
      GIR_AddImm8, /*InsnID*/0, /*Imm*/0,
      GIR_MergeMemOperands, /*InsnID*/0, /*NumInsns*/1, /*MergeInsnID's*/0,
      GIR_ConstrainSelectedInstOperands, /*InsnID*/0,
      GIR_EraseFromParent, /*InsnID*/0,
      // GIR_Coverage, 3545,
      GIR_Done,
    // Label 1502: @99758
    GIM_Try, /*On fail goto*//*Label 1503*/ GIMT_Encode4(99820), // Rule ID 3551 //
      GIM_CheckFeatures, GIMT_Encode2(GIFBS_EnableFlatScratch_HasFlatScratchInsts),
      GIM_CheckMemoryAddressSpace, /*MI*/0, /*MMO*/0, /*NumAddrSpace*/1, /*AddrSpace*/5,
      GIM_CheckAtomicOrdering, /*MI*/0, /*Order*/(uint8_t)AtomicOrdering::NotAtomic,
      GIM_CheckRegBankForClass, /*MI*/0, /*Op*/0, /*RC*/GIMT_Encode2(AMDGPU::AV_128RegClassID),
      GIM_CheckPointerToAny, /*MI*/0, /*Op*/1, /*SizeInBits*/0,
      GIM_CheckComplexPattern, /*MI*/0, /*Op*/1, /*Renderer*/GIMT_Encode2(0), GIMT_Encode2(GICP_gi_flat_scratch_offset),
      // (ld:{ *:[v4f32] } (ScratchOffset:{ *:[iPTR] } VGPR_32:{ *:[i32] }:$vaddr, i32:{ *:[i32] }:$offset))<<P:Predicate_unindexedload>><<P:Predicate_load_private>>  =>  (SCRATCH_LOAD_DWORDX4:{ *:[v4f32] } ?:{ *:[i32] }:$vaddr, ?:{ *:[i32] }:$offset)
      GIR_BuildMI, /*InsnID*/0, /*Opcode*/GIMT_Encode2(AMDGPU::SCRATCH_LOAD_DWORDX4),
      GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/0, // DstI[vdst]
      GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/0, // vaddr
      GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/1, // offset
      GIR_AddImm8, /*InsnID*/0, /*Imm*/0,
      GIR_MergeMemOperands, /*InsnID*/0, /*NumInsns*/1, /*MergeInsnID's*/0,
      GIR_ConstrainSelectedInstOperands, /*InsnID*/0,
      GIR_EraseFromParent, /*InsnID*/0,
      // GIR_Coverage, 3551,
      GIR_Done,
    // Label 1503: @99820
    GIM_Try, /*On fail goto*//*Label 1504*/ GIMT_Encode4(99897), // Rule ID 3768 //
      GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasUnrestrictedSOffset),
      GIM_CheckMemoryAddressSpace, /*MI*/0, /*MMO*/0, /*NumAddrSpace*/3, /*AddrSpace*/1, /*AddrSpace*/4, /*AddrSpace*/6,
      GIM_CheckAtomicOrdering, /*MI*/0, /*Order*/(uint8_t)AtomicOrdering::NotAtomic,
      GIM_CheckRegBankForClass, /*MI*/0, /*Op*/0, /*RC*/GIMT_Encode2(AMDGPU::AV_128RegClassID),
      GIM_CheckPointerToAny, /*MI*/0, /*Op*/1, /*SizeInBits*/0,
      GIM_CheckComplexPattern, /*MI*/0, /*Op*/1, /*Renderer*/GIMT_Encode2(0), GIMT_Encode2(GICP_gi_mubuf_addr64),
      // (ld:{ *:[v4i32] } (MUBUFAddr64:{ *:[iPTR] } v4i32:{ *:[v4i32] }:$srsrc, i64:{ *:[i64] }:$vaddr, i32:{ *:[i32] }:$soffset, i32:{ *:[i32] }:$offset))<<P:Predicate_unindexedload>><<P:Predicate_load_global>>  =>  (BUFFER_LOAD_DWORDX4_ADDR64:{ *:[v4i32] } i64:{ *:[i64] }:$vaddr, v4i32:{ *:[v4i32] }:$srsrc, i32:{ *:[i32] }:$soffset, i32:{ *:[i32] }:$offset)
      GIR_BuildMI, /*InsnID*/0, /*Opcode*/GIMT_Encode2(AMDGPU::BUFFER_LOAD_DWORDX4_ADDR64),
      GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/0, // DstI[vdata]
      GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/1, // vaddr
      GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/0, // srsrc
      GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/2, // soffset
      GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/3, // offset
      GIR_AddImm8, /*InsnID*/0, /*Imm*/0,
      GIR_AddImm8, /*InsnID*/0, /*Imm*/0,
      GIR_MergeMemOperands, /*InsnID*/0, /*NumInsns*/1, /*MergeInsnID's*/0,
      GIR_ConstrainSelectedInstOperands, /*InsnID*/0,
      GIR_EraseFromParent, /*InsnID*/0,
      // GIR_Coverage, 3768,
      GIR_Done,
    // Label 1504: @99897
    GIM_Try, /*On fail goto*//*Label 1505*/ GIMT_Encode4(99971), // Rule ID 3770 //
      GIM_CheckMemoryAddressSpace, /*MI*/0, /*MMO*/0, /*NumAddrSpace*/3, /*AddrSpace*/1, /*AddrSpace*/4, /*AddrSpace*/6,
      GIM_CheckAtomicOrdering, /*MI*/0, /*Order*/(uint8_t)AtomicOrdering::NotAtomic,
      GIM_CheckRegBankForClass, /*MI*/0, /*Op*/0, /*RC*/GIMT_Encode2(AMDGPU::AV_128RegClassID),
      GIM_CheckPointerToAny, /*MI*/0, /*Op*/1, /*SizeInBits*/0,
      GIM_CheckComplexPattern, /*MI*/0, /*Op*/1, /*Renderer*/GIMT_Encode2(0), GIMT_Encode2(GICP_gi_mubuf_addr64),
      // (ld:{ *:[v4i32] } (MUBUFAddr64:{ *:[iPTR] } v4i32:{ *:[v4i32] }:$srsrc, i64:{ *:[i64] }:$vaddr, i32:{ *:[i32] }:$soffset, i32:{ *:[i32] }:$offset))<<P:Predicate_unindexedload>><<P:Predicate_load_global>>  =>  (BUFFER_LOAD_DWORDX4_VBUFFER_ADDR64:{ *:[v4i32] } i64:{ *:[i64] }:$vaddr, v4i32:{ *:[v4i32] }:$srsrc, i32:{ *:[i32] }:$soffset, i32:{ *:[i32] }:$offset)
      GIR_BuildMI, /*InsnID*/0, /*Opcode*/GIMT_Encode2(AMDGPU::BUFFER_LOAD_DWORDX4_VBUFFER_ADDR64),
      GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/0, // DstI[vdata]
      GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/1, // vaddr
      GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/0, // srsrc
      GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/2, // soffset
      GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/3, // offset
      GIR_AddImm8, /*InsnID*/0, /*Imm*/0,
      GIR_AddImm8, /*InsnID*/0, /*Imm*/0,
      GIR_MergeMemOperands, /*InsnID*/0, /*NumInsns*/1, /*MergeInsnID's*/0,
      GIR_ConstrainSelectedInstOperands, /*InsnID*/0,
      GIR_EraseFromParent, /*InsnID*/0,
      // GIR_Coverage, 3770,
      GIR_Done,
    // Label 1505: @99971
    GIM_Try, /*On fail goto*//*Label 1506*/ GIMT_Encode4(100048), // Rule ID 3772 //
      GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasUnrestrictedSOffset),
      GIM_CheckMemoryAddressSpace, /*MI*/0, /*MMO*/0, /*NumAddrSpace*/3, /*AddrSpace*/1, /*AddrSpace*/4, /*AddrSpace*/6,
      GIM_CheckAtomicOrdering, /*MI*/0, /*Order*/(uint8_t)AtomicOrdering::NotAtomic,
      GIM_CheckRegBankForClass, /*MI*/0, /*Op*/0, /*RC*/GIMT_Encode2(AMDGPU::AV_128RegClassID),
      GIM_CheckPointerToAny, /*MI*/0, /*Op*/1, /*SizeInBits*/0,
      GIM_CheckComplexPattern, /*MI*/0, /*Op*/1, /*Renderer*/GIMT_Encode2(0), GIMT_Encode2(GICP_gi_mubuf_addr64),
      // (ld:{ *:[v4f32] } (MUBUFAddr64:{ *:[iPTR] } v4i32:{ *:[v4i32] }:$srsrc, i64:{ *:[i64] }:$vaddr, i32:{ *:[i32] }:$soffset, i32:{ *:[i32] }:$offset))<<P:Predicate_unindexedload>><<P:Predicate_load_global>>  =>  (BUFFER_LOAD_DWORDX4_ADDR64:{ *:[v4f32] } i64:{ *:[i64] }:$vaddr, v4i32:{ *:[v4i32] }:$srsrc, i32:{ *:[i32] }:$soffset, i32:{ *:[i32] }:$offset)
      GIR_BuildMI, /*InsnID*/0, /*Opcode*/GIMT_Encode2(AMDGPU::BUFFER_LOAD_DWORDX4_ADDR64),
      GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/0, // DstI[vdata]
      GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/1, // vaddr
      GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/0, // srsrc
      GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/2, // soffset
      GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/3, // offset
      GIR_AddImm8, /*InsnID*/0, /*Imm*/0,
      GIR_AddImm8, /*InsnID*/0, /*Imm*/0,
      GIR_MergeMemOperands, /*InsnID*/0, /*NumInsns*/1, /*MergeInsnID's*/0,
      GIR_ConstrainSelectedInstOperands, /*InsnID*/0,
      GIR_EraseFromParent, /*InsnID*/0,
      // GIR_Coverage, 3772,
      GIR_Done,
    // Label 1506: @100048
    GIM_Try, /*On fail goto*//*Label 1507*/ GIMT_Encode4(100122), // Rule ID 3774 //
      GIM_CheckMemoryAddressSpace, /*MI*/0, /*MMO*/0, /*NumAddrSpace*/3, /*AddrSpace*/1, /*AddrSpace*/4, /*AddrSpace*/6,
      GIM_CheckAtomicOrdering, /*MI*/0, /*Order*/(uint8_t)AtomicOrdering::NotAtomic,
      GIM_CheckRegBankForClass, /*MI*/0, /*Op*/0, /*RC*/GIMT_Encode2(AMDGPU::AV_128RegClassID),
      GIM_CheckPointerToAny, /*MI*/0, /*Op*/1, /*SizeInBits*/0,
      GIM_CheckComplexPattern, /*MI*/0, /*Op*/1, /*Renderer*/GIMT_Encode2(0), GIMT_Encode2(GICP_gi_mubuf_addr64),
      // (ld:{ *:[v4f32] } (MUBUFAddr64:{ *:[iPTR] } v4i32:{ *:[v4i32] }:$srsrc, i64:{ *:[i64] }:$vaddr, i32:{ *:[i32] }:$soffset, i32:{ *:[i32] }:$offset))<<P:Predicate_unindexedload>><<P:Predicate_load_global>>  =>  (BUFFER_LOAD_DWORDX4_VBUFFER_ADDR64:{ *:[v4f32] } i64:{ *:[i64] }:$vaddr, v4i32:{ *:[v4i32] }:$srsrc, i32:{ *:[i32] }:$soffset, i32:{ *:[i32] }:$offset)
      GIR_BuildMI, /*InsnID*/0, /*Opcode*/GIMT_Encode2(AMDGPU::BUFFER_LOAD_DWORDX4_VBUFFER_ADDR64),
      GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/0, // DstI[vdata]
      GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/1, // vaddr
      GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/0, // srsrc
      GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/2, // soffset
      GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/3, // offset
      GIR_AddImm8, /*InsnID*/0, /*Imm*/0,
      GIR_AddImm8, /*InsnID*/0, /*Imm*/0,
      GIR_MergeMemOperands, /*InsnID*/0, /*NumInsns*/1, /*MergeInsnID's*/0,
      GIR_ConstrainSelectedInstOperands, /*InsnID*/0,
      GIR_EraseFromParent, /*InsnID*/0,
      // GIR_Coverage, 3774,
      GIR_Done,
    // Label 1507: @100122
    GIM_Try, /*On fail goto*//*Label 1508*/ GIMT_Encode4(100197), // Rule ID 5431 //
      GIM_CheckFeatures, GIMT_Encode2(GIFBS_DisableFlatScratch_HasUnrestrictedSOffset),
      GIM_CheckMemoryAddressSpace, /*MI*/0, /*MMO*/0, /*NumAddrSpace*/1, /*AddrSpace*/5,
      GIM_CheckAtomicOrdering, /*MI*/0, /*Order*/(uint8_t)AtomicOrdering::NotAtomic,
      GIM_CheckRegBankForClass, /*MI*/0, /*Op*/0, /*RC*/GIMT_Encode2(AMDGPU::AV_128RegClassID),
      GIM_CheckPointerToAny, /*MI*/0, /*Op*/1, /*SizeInBits*/0,
      GIM_CheckComplexPattern, /*MI*/0, /*Op*/1, /*Renderer*/GIMT_Encode2(0), GIMT_Encode2(GICP_gi_mubuf_scratch_offen),
      // (ld:{ *:[v4i32] } (MUBUFScratchOffen:{ *:[iPTR] } v4i32:{ *:[v4i32] }:$srsrc, i32:{ *:[i32] }:$vaddr, i32:{ *:[i32] }:$soffset, i32:{ *:[i32] }:$offset))<<P:Predicate_unindexedload>><<P:Predicate_load_private>>  =>  (BUFFER_LOAD_DWORDX4_OFFEN:{ *:[v4i32] } ?:{ *:[i32] }:$vaddr, ?:{ *:[v4i32] }:$srsrc, ?:{ *:[i32] }:$soffset, ?:{ *:[i32] }:$offset, 0:{ *:[i32] }, 0:{ *:[i1] })
      GIR_BuildMI, /*InsnID*/0, /*Opcode*/GIMT_Encode2(AMDGPU::BUFFER_LOAD_DWORDX4_OFFEN),
      GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/0, // DstI[vdata]
      GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/1, // vaddr
      GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/0, // srsrc
      GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/2, // soffset
      GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/3, // offset
      GIR_AddImm8, /*InsnID*/0, /*Imm*/0,
      GIR_AddImm8, /*InsnID*/0, /*Imm*/0,
      GIR_MergeMemOperands, /*InsnID*/0, /*NumInsns*/1, /*MergeInsnID's*/0,
      GIR_ConstrainSelectedInstOperands, /*InsnID*/0,
      GIR_EraseFromParent, /*InsnID*/0,
      // GIR_Coverage, 5431,
      GIR_Done,
    // Label 1508: @100197
    GIM_Try, /*On fail goto*//*Label 1509*/ GIMT_Encode4(100272), // Rule ID 5433 //
      GIM_CheckFeatures, GIMT_Encode2(GIFBS_DisableFlatScratch),
      GIM_CheckMemoryAddressSpace, /*MI*/0, /*MMO*/0, /*NumAddrSpace*/1, /*AddrSpace*/5,
      GIM_CheckAtomicOrdering, /*MI*/0, /*Order*/(uint8_t)AtomicOrdering::NotAtomic,
      GIM_CheckRegBankForClass, /*MI*/0, /*Op*/0, /*RC*/GIMT_Encode2(AMDGPU::AV_128RegClassID),
      GIM_CheckPointerToAny, /*MI*/0, /*Op*/1, /*SizeInBits*/0,
      GIM_CheckComplexPattern, /*MI*/0, /*Op*/1, /*Renderer*/GIMT_Encode2(0), GIMT_Encode2(GICP_gi_mubuf_scratch_offen),
      // (ld:{ *:[v4i32] } (MUBUFScratchOffen:{ *:[iPTR] } v4i32:{ *:[v4i32] }:$srsrc, i32:{ *:[i32] }:$vaddr, i32:{ *:[i32] }:$soffset, i32:{ *:[i32] }:$offset))<<P:Predicate_unindexedload>><<P:Predicate_load_private>>  =>  (BUFFER_LOAD_DWORDX4_VBUFFER_OFFEN:{ *:[v4i32] } ?:{ *:[i32] }:$vaddr, ?:{ *:[v4i32] }:$srsrc, ?:{ *:[i32] }:$soffset, ?:{ *:[i32] }:$offset, 0:{ *:[i32] }, 0:{ *:[i1] })
      GIR_BuildMI, /*InsnID*/0, /*Opcode*/GIMT_Encode2(AMDGPU::BUFFER_LOAD_DWORDX4_VBUFFER_OFFEN),
      GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/0, // DstI[vdata]
      GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/1, // vaddr
      GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/0, // srsrc
      GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/2, // soffset
      GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/3, // offset
      GIR_AddImm8, /*InsnID*/0, /*Imm*/0,
      GIR_AddImm8, /*InsnID*/0, /*Imm*/0,
      GIR_MergeMemOperands, /*InsnID*/0, /*NumInsns*/1, /*MergeInsnID's*/0,
      GIR_ConstrainSelectedInstOperands, /*InsnID*/0,
      GIR_EraseFromParent, /*InsnID*/0,
      // GIR_Coverage, 5433,
      GIR_Done,
    // Label 1509: @100272
    GIM_Try, /*On fail goto*//*Label 1510*/ GIMT_Encode4(100343), // Rule ID 6675 //
      GIM_CheckFeatures, GIMT_Encode2(GIFBS_LDSRequiresM0Init_isGFX7Plus),
      GIM_CheckMemorySizeEqualToLLT, /*MI*/0, /*MMO*/0, /*OpIdx*/0,
      GIM_CheckMemoryAddressSpace, /*MI*/0, /*MMO*/0, /*NumAddrSpace*/1, /*AddrSpace*/3,
      GIM_CheckAtomicOrdering, /*MI*/0, /*Order*/(uint8_t)AtomicOrdering::NotAtomic,
      GIM_CheckRegBankForClass, /*MI*/0, /*Op*/0, /*RC*/GIMT_Encode2(AMDGPU::AV_128RegClassID),
      GIM_CheckPointerToAny, /*MI*/0, /*Op*/1, /*SizeInBits*/0,
      GIM_CheckComplexPattern, /*MI*/0, /*Op*/1, /*Renderer*/GIMT_Encode2(0), GIMT_Encode2(GICP_gi_ds_128bit_8byte_aligned),
      // (AMDGPUld_glue:{ *:[v4i32] } (DS128Bit8ByteAligned:{ *:[iPTR] } i32:{ *:[i32] }:$ptr, i8:{ *:[i8] }:$offset0, i8:{ *:[i8] }:$offset1))<<P:Predicate_unindexedload_glue>><<P:Predicate_load_glue>><<P:Predicate_load_local_m0>>  =>  (DS_READ2_B64:{ *:[v4i32] } ?:{ *:[i32] }:$ptr, ?:{ *:[i8] }:$offset0, ?:{ *:[i8] }:$offset1, 0:{ *:[i1] })
      GIR_BuildMI, /*InsnID*/0, /*Opcode*/GIMT_Encode2(AMDGPU::DS_READ2_B64),
      GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/0, // DstI[vdst]
      GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/0, // ptr
      GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/1, // offset0
      GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/2, // offset1
      GIR_AddImm8, /*InsnID*/0, /*Imm*/0,
      GIR_MergeMemOperands, /*InsnID*/0, /*NumInsns*/1, /*MergeInsnID's*/0,
      GIR_ConstrainSelectedInstOperands, /*InsnID*/0,
      GIR_EraseFromParent, /*InsnID*/0,
      // GIR_Coverage, 6675,
      GIR_Done,
    // Label 1510: @100343
    GIM_Try, /*On fail goto*//*Label 1511*/ GIMT_Encode4(100414), // Rule ID 6715 //
      GIM_CheckFeatures, GIMT_Encode2(GIFBS_LDSRequiresM0Init_isGFX7Plus),
      GIM_CheckMemorySizeEqualToLLT, /*MI*/0, /*MMO*/0, /*OpIdx*/0,
      GIM_CheckMemoryAddressSpace, /*MI*/0, /*MMO*/0, /*NumAddrSpace*/1, /*AddrSpace*/3,
      GIM_CheckAtomicOrdering, /*MI*/0, /*Order*/(uint8_t)AtomicOrdering::NotAtomic,
      GIM_CheckRegBankForClass, /*MI*/0, /*Op*/0, /*RC*/GIMT_Encode2(AMDGPU::AV_128RegClassID),
      GIM_CheckPointerToAny, /*MI*/0, /*Op*/1, /*SizeInBits*/0,
      GIM_CheckComplexPattern, /*MI*/0, /*Op*/1, /*Renderer*/GIMT_Encode2(0), GIMT_Encode2(GICP_gi_ds_128bit_8byte_aligned),
      // (AMDGPUld_glue:{ *:[v4f32] } (DS128Bit8ByteAligned:{ *:[iPTR] } i32:{ *:[i32] }:$ptr, i8:{ *:[i8] }:$offset0, i8:{ *:[i8] }:$offset1))<<P:Predicate_unindexedload_glue>><<P:Predicate_load_glue>><<P:Predicate_load_local_m0>>  =>  (DS_READ2_B64:{ *:[v4f32] } ?:{ *:[i32] }:$ptr, ?:{ *:[i8] }:$offset0, ?:{ *:[i8] }:$offset1, 0:{ *:[i1] })
      GIR_BuildMI, /*InsnID*/0, /*Opcode*/GIMT_Encode2(AMDGPU::DS_READ2_B64),
      GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/0, // DstI[vdst]
      GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/0, // ptr
      GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/1, // offset0
      GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/2, // offset1
      GIR_AddImm8, /*InsnID*/0, /*Imm*/0,
      GIR_MergeMemOperands, /*InsnID*/0, /*NumInsns*/1, /*MergeInsnID's*/0,
      GIR_ConstrainSelectedInstOperands, /*InsnID*/0,
      GIR_EraseFromParent, /*InsnID*/0,
      // GIR_Coverage, 6715,
      GIR_Done,
    // Label 1511: @100414
    GIM_Try, /*On fail goto*//*Label 1512*/ GIMT_Encode4(100486), // Rule ID 3767 //
      GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasUnrestrictedSOffset),
      GIM_CheckMemoryAddressSpace, /*MI*/0, /*MMO*/0, /*NumAddrSpace*/3, /*AddrSpace*/1, /*AddrSpace*/4, /*AddrSpace*/6,
      GIM_CheckAtomicOrdering, /*MI*/0, /*Order*/(uint8_t)AtomicOrdering::NotAtomic,
      GIM_CheckRegBankForClass, /*MI*/0, /*Op*/0, /*RC*/GIMT_Encode2(AMDGPU::AV_128RegClassID),
      GIM_CheckPointerToAny, /*MI*/0, /*Op*/1, /*SizeInBits*/0,
      GIM_CheckComplexPattern, /*MI*/0, /*Op*/1, /*Renderer*/GIMT_Encode2(0), GIMT_Encode2(GICP_gi_mubuf_offset),
      // (ld:{ *:[v4i32] } (MUBUFOffset:{ *:[iPTR] } v4i32:{ *:[v4i32] }:$srsrc, i32:{ *:[i32] }:$soffset, i32:{ *:[i32] }:$offset))<<P:Predicate_unindexedload>><<P:Predicate_load_global>>  =>  (BUFFER_LOAD_DWORDX4_OFFSET:{ *:[v4i32] } v4i32:{ *:[v4i32] }:$srsrc, i32:{ *:[i32] }:$soffset, i32:{ *:[i32] }:$offset)
      GIR_BuildMI, /*InsnID*/0, /*Opcode*/GIMT_Encode2(AMDGPU::BUFFER_LOAD_DWORDX4_OFFSET),
      GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/0, // DstI[vdata]
      GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/0, // srsrc
      GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/1, // soffset
      GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/2, // offset
      GIR_AddImm8, /*InsnID*/0, /*Imm*/0,
      GIR_AddImm8, /*InsnID*/0, /*Imm*/0,
      GIR_MergeMemOperands, /*InsnID*/0, /*NumInsns*/1, /*MergeInsnID's*/0,
      GIR_ConstrainSelectedInstOperands, /*InsnID*/0,
      GIR_EraseFromParent, /*InsnID*/0,
      // GIR_Coverage, 3767,
      GIR_Done,
    // Label 1512: @100486
    GIM_Try, /*On fail goto*//*Label 1513*/ GIMT_Encode4(100555), // Rule ID 3769 //
      GIM_CheckMemoryAddressSpace, /*MI*/0, /*MMO*/0, /*NumAddrSpace*/3, /*AddrSpace*/1, /*AddrSpace*/4, /*AddrSpace*/6,
      GIM_CheckAtomicOrdering, /*MI*/0, /*Order*/(uint8_t)AtomicOrdering::NotAtomic,
      GIM_CheckRegBankForClass, /*MI*/0, /*Op*/0, /*RC*/GIMT_Encode2(AMDGPU::AV_128RegClassID),
      GIM_CheckPointerToAny, /*MI*/0, /*Op*/1, /*SizeInBits*/0,
      GIM_CheckComplexPattern, /*MI*/0, /*Op*/1, /*Renderer*/GIMT_Encode2(0), GIMT_Encode2(GICP_gi_mubuf_offset),
      // (ld:{ *:[v4i32] } (MUBUFOffset:{ *:[iPTR] } v4i32:{ *:[v4i32] }:$srsrc, i32:{ *:[i32] }:$soffset, i32:{ *:[i32] }:$offset))<<P:Predicate_unindexedload>><<P:Predicate_load_global>>  =>  (BUFFER_LOAD_DWORDX4_VBUFFER_OFFSET:{ *:[v4i32] } v4i32:{ *:[v4i32] }:$srsrc, i32:{ *:[i32] }:$soffset, i32:{ *:[i32] }:$offset)
      GIR_BuildMI, /*InsnID*/0, /*Opcode*/GIMT_Encode2(AMDGPU::BUFFER_LOAD_DWORDX4_VBUFFER_OFFSET),
      GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/0, // DstI[vdata]
      GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/0, // srsrc
      GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/1, // soffset
      GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/2, // offset
      GIR_AddImm8, /*InsnID*/0, /*Imm*/0,
      GIR_AddImm8, /*InsnID*/0, /*Imm*/0,
      GIR_MergeMemOperands, /*InsnID*/0, /*NumInsns*/1, /*MergeInsnID's*/0,
      GIR_ConstrainSelectedInstOperands, /*InsnID*/0,
      GIR_EraseFromParent, /*InsnID*/0,
      // GIR_Coverage, 3769,
      GIR_Done,
    // Label 1513: @100555
    GIM_Try, /*On fail goto*//*Label 1514*/ GIMT_Encode4(100627), // Rule ID 3771 //
      GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasUnrestrictedSOffset),
      GIM_CheckMemoryAddressSpace, /*MI*/0, /*MMO*/0, /*NumAddrSpace*/3, /*AddrSpace*/1, /*AddrSpace*/4, /*AddrSpace*/6,
      GIM_CheckAtomicOrdering, /*MI*/0, /*Order*/(uint8_t)AtomicOrdering::NotAtomic,
      GIM_CheckRegBankForClass, /*MI*/0, /*Op*/0, /*RC*/GIMT_Encode2(AMDGPU::AV_128RegClassID),
      GIM_CheckPointerToAny, /*MI*/0, /*Op*/1, /*SizeInBits*/0,
      GIM_CheckComplexPattern, /*MI*/0, /*Op*/1, /*Renderer*/GIMT_Encode2(0), GIMT_Encode2(GICP_gi_mubuf_offset),
      // (ld:{ *:[v4f32] } (MUBUFOffset:{ *:[iPTR] } v4i32:{ *:[v4i32] }:$srsrc, i32:{ *:[i32] }:$soffset, i32:{ *:[i32] }:$offset))<<P:Predicate_unindexedload>><<P:Predicate_load_global>>  =>  (BUFFER_LOAD_DWORDX4_OFFSET:{ *:[v4f32] } v4i32:{ *:[v4i32] }:$srsrc, i32:{ *:[i32] }:$soffset, i32:{ *:[i32] }:$offset)
      GIR_BuildMI, /*InsnID*/0, /*Opcode*/GIMT_Encode2(AMDGPU::BUFFER_LOAD_DWORDX4_OFFSET),
      GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/0, // DstI[vdata]
      GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/0, // srsrc
      GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/1, // soffset
      GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/2, // offset
      GIR_AddImm8, /*InsnID*/0, /*Imm*/0,
      GIR_AddImm8, /*InsnID*/0, /*Imm*/0,
      GIR_MergeMemOperands, /*InsnID*/0, /*NumInsns*/1, /*MergeInsnID's*/0,
      GIR_ConstrainSelectedInstOperands, /*InsnID*/0,
      GIR_EraseFromParent, /*InsnID*/0,
      // GIR_Coverage, 3771,
      GIR_Done,
    // Label 1514: @100627
    GIM_Try, /*On fail goto*//*Label 1515*/ GIMT_Encode4(100696), // Rule ID 3773 //
      GIM_CheckMemoryAddressSpace, /*MI*/0, /*MMO*/0, /*NumAddrSpace*/3, /*AddrSpace*/1, /*AddrSpace*/4, /*AddrSpace*/6,
      GIM_CheckAtomicOrdering, /*MI*/0, /*Order*/(uint8_t)AtomicOrdering::NotAtomic,
      GIM_CheckRegBankForClass, /*MI*/0, /*Op*/0, /*RC*/GIMT_Encode2(AMDGPU::AV_128RegClassID),
      GIM_CheckPointerToAny, /*MI*/0, /*Op*/1, /*SizeInBits*/0,
      GIM_CheckComplexPattern, /*MI*/0, /*Op*/1, /*Renderer*/GIMT_Encode2(0), GIMT_Encode2(GICP_gi_mubuf_offset),
      // (ld:{ *:[v4f32] } (MUBUFOffset:{ *:[iPTR] } v4i32:{ *:[v4i32] }:$srsrc, i32:{ *:[i32] }:$soffset, i32:{ *:[i32] }:$offset))<<P:Predicate_unindexedload>><<P:Predicate_load_global>>  =>  (BUFFER_LOAD_DWORDX4_VBUFFER_OFFSET:{ *:[v4f32] } v4i32:{ *:[v4i32] }:$srsrc, i32:{ *:[i32] }:$soffset, i32:{ *:[i32] }:$offset)
      GIR_BuildMI, /*InsnID*/0, /*Opcode*/GIMT_Encode2(AMDGPU::BUFFER_LOAD_DWORDX4_VBUFFER_OFFSET),
      GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/0, // DstI[vdata]
      GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/0, // srsrc
      GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/1, // soffset
      GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/2, // offset
      GIR_AddImm8, /*InsnID*/0, /*Imm*/0,
      GIR_AddImm8, /*InsnID*/0, /*Imm*/0,
      GIR_MergeMemOperands, /*InsnID*/0, /*NumInsns*/1, /*MergeInsnID's*/0,
      GIR_ConstrainSelectedInstOperands, /*InsnID*/0,
      GIR_EraseFromParent, /*InsnID*/0,
      // GIR_Coverage, 3773,
      GIR_Done,
    // Label 1515: @100696
    GIM_Try, /*On fail goto*//*Label 1516*/ GIMT_Encode4(100763), // Rule ID 6677 //
      GIM_CheckFeatures, GIMT_Encode2(GIFBS_NotLDSRequiresM0Init),
      GIM_CheckMemoryAddressSpace, /*MI*/0, /*MMO*/0, /*NumAddrSpace*/1, /*AddrSpace*/3,
      GIM_CheckAtomicOrdering, /*MI*/0, /*Order*/(uint8_t)AtomicOrdering::NotAtomic,
      GIM_CheckRegBankForClass, /*MI*/0, /*Op*/0, /*RC*/GIMT_Encode2(AMDGPU::AV_128RegClassID),
      GIM_CheckPointerToAny, /*MI*/0, /*Op*/1, /*SizeInBits*/0,
      GIM_CheckComplexPattern, /*MI*/0, /*Op*/1, /*Renderer*/GIMT_Encode2(0), GIMT_Encode2(GICP_gi_ds_128bit_8byte_aligned),
      // (ld:{ *:[v4i32] } (DS128Bit8ByteAligned:{ *:[iPTR] } i32:{ *:[i32] }:$ptr, i8:{ *:[i8] }:$offset0, i8:{ *:[i8] }:$offset1))<<P:Predicate_unindexedload>><<P:Predicate_load_local>>  =>  (DS_READ2_B64_gfx9:{ *:[v4i32] } ?:{ *:[i32] }:$ptr, ?:{ *:[i8] }:$offset0, ?:{ *:[i8] }:$offset1, 0:{ *:[i1] })
      GIR_BuildMI, /*InsnID*/0, /*Opcode*/GIMT_Encode2(AMDGPU::DS_READ2_B64_gfx9),
      GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/0, // DstI[vdst]
      GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/0, // ptr
      GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/1, // offset0
      GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/2, // offset1
      GIR_AddImm8, /*InsnID*/0, /*Imm*/0,
      GIR_MergeMemOperands, /*InsnID*/0, /*NumInsns*/1, /*MergeInsnID's*/0,
      GIR_ConstrainSelectedInstOperands, /*InsnID*/0,
      GIR_EraseFromParent, /*InsnID*/0,
      // GIR_Coverage, 6677,
      GIR_Done,
    // Label 1516: @100763
    GIM_Try, /*On fail goto*//*Label 1517*/ GIMT_Encode4(100830), // Rule ID 6717 //
      GIM_CheckFeatures, GIMT_Encode2(GIFBS_NotLDSRequiresM0Init),
      GIM_CheckMemoryAddressSpace, /*MI*/0, /*MMO*/0, /*NumAddrSpace*/1, /*AddrSpace*/3,
      GIM_CheckAtomicOrdering, /*MI*/0, /*Order*/(uint8_t)AtomicOrdering::NotAtomic,
      GIM_CheckRegBankForClass, /*MI*/0, /*Op*/0, /*RC*/GIMT_Encode2(AMDGPU::AV_128RegClassID),
      GIM_CheckPointerToAny, /*MI*/0, /*Op*/1, /*SizeInBits*/0,
      GIM_CheckComplexPattern, /*MI*/0, /*Op*/1, /*Renderer*/GIMT_Encode2(0), GIMT_Encode2(GICP_gi_ds_128bit_8byte_aligned),
      // (ld:{ *:[v4f32] } (DS128Bit8ByteAligned:{ *:[iPTR] } i32:{ *:[i32] }:$ptr, i8:{ *:[i8] }:$offset0, i8:{ *:[i8] }:$offset1))<<P:Predicate_unindexedload>><<P:Predicate_load_local>>  =>  (DS_READ2_B64_gfx9:{ *:[v4f32] } ?:{ *:[i32] }:$ptr, ?:{ *:[i8] }:$offset0, ?:{ *:[i8] }:$offset1, 0:{ *:[i1] })
      GIR_BuildMI, /*InsnID*/0, /*Opcode*/GIMT_Encode2(AMDGPU::DS_READ2_B64_gfx9),
      GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/0, // DstI[vdst]
      GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/0, // ptr
      GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/1, // offset0
      GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/2, // offset1
      GIR_AddImm8, /*InsnID*/0, /*Imm*/0,
      GIR_MergeMemOperands, /*InsnID*/0, /*NumInsns*/1, /*MergeInsnID's*/0,
      GIR_ConstrainSelectedInstOperands, /*InsnID*/0,
      GIR_EraseFromParent, /*InsnID*/0,
      // GIR_Coverage, 6717,
      GIR_Done,
    // Label 1517: @100830
    GIM_Try, /*On fail goto*//*Label 1518*/ GIMT_Encode4(100899), // Rule ID 3071 //
      GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasFlatGlobalInsts),
      GIM_CheckMemoryAddressSpace, /*MI*/0, /*MMO*/0, /*NumAddrSpace*/3, /*AddrSpace*/1, /*AddrSpace*/4, /*AddrSpace*/6,
      GIM_CheckAtomicOrdering, /*MI*/0, /*Order*/(uint8_t)AtomicOrdering::NotAtomic,
      GIM_CheckRegBankForClass, /*MI*/0, /*Op*/0, /*RC*/GIMT_Encode2(AMDGPU::AV_128RegClassID),
      GIM_CheckPointerToAny, /*MI*/0, /*Op*/1, /*SizeInBits*/0,
      GIM_CheckComplexPattern, /*MI*/0, /*Op*/1, /*Renderer*/GIMT_Encode2(0), GIMT_Encode2(GICP_gi_global_saddr),
      // (ld:{ *:[v4i32] } (GlobalSAddr:{ *:[iPTR] } SReg_64:{ *:[i64] }:$saddr, VGPR_32:{ *:[i32] }:$voffset, i32:{ *:[i32] }:$offset))<<P:Predicate_unindexedload>><<P:Predicate_load_global>>  =>  (GLOBAL_LOAD_DWORDX4_SADDR:{ *:[v4i32] } ?:{ *:[i64] }:$saddr, ?:{ *:[i32] }:$voffset, ?:{ *:[i32] }:$offset, 0:{ *:[i32] })
      GIR_BuildMI, /*InsnID*/0, /*Opcode*/GIMT_Encode2(AMDGPU::GLOBAL_LOAD_DWORDX4_SADDR),
      GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/0, // DstI[vdst]
      GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/0, // saddr
      GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/1, // voffset
      GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/2, // offset
      GIR_AddImm8, /*InsnID*/0, /*Imm*/0,
      GIR_MergeMemOperands, /*InsnID*/0, /*NumInsns*/1, /*MergeInsnID's*/0,
      GIR_ConstrainSelectedInstOperands, /*InsnID*/0,
      GIR_EraseFromParent, /*InsnID*/0,
      // GIR_Coverage, 3071,
      GIR_Done,
    // Label 1518: @100899
    GIM_Try, /*On fail goto*//*Label 1519*/ GIMT_Encode4(100968), // Rule ID 3075 //
      GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasFlatGlobalInsts),
      GIM_CheckMemoryAddressSpace, /*MI*/0, /*MMO*/0, /*NumAddrSpace*/3, /*AddrSpace*/1, /*AddrSpace*/4, /*AddrSpace*/6,
      GIM_CheckAtomicOrdering, /*MI*/0, /*Order*/(uint8_t)AtomicOrdering::NotAtomic,
      GIM_CheckRegBankForClass, /*MI*/0, /*Op*/0, /*RC*/GIMT_Encode2(AMDGPU::AV_128RegClassID),
      GIM_CheckPointerToAny, /*MI*/0, /*Op*/1, /*SizeInBits*/0,
      GIM_CheckComplexPattern, /*MI*/0, /*Op*/1, /*Renderer*/GIMT_Encode2(0), GIMT_Encode2(GICP_gi_global_saddr),
      // (ld:{ *:[v4f32] } (GlobalSAddr:{ *:[iPTR] } SReg_64:{ *:[i64] }:$saddr, VGPR_32:{ *:[i32] }:$voffset, i32:{ *:[i32] }:$offset))<<P:Predicate_unindexedload>><<P:Predicate_load_global>>  =>  (GLOBAL_LOAD_DWORDX4_SADDR:{ *:[v4f32] } ?:{ *:[i64] }:$saddr, ?:{ *:[i32] }:$voffset, ?:{ *:[i32] }:$offset, 0:{ *:[i32] })
      GIR_BuildMI, /*InsnID*/0, /*Opcode*/GIMT_Encode2(AMDGPU::GLOBAL_LOAD_DWORDX4_SADDR),
      GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/0, // DstI[vdst]
      GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/0, // saddr
      GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/1, // voffset
      GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/2, // offset
      GIR_AddImm8, /*InsnID*/0, /*Imm*/0,
      GIR_MergeMemOperands, /*InsnID*/0, /*NumInsns*/1, /*MergeInsnID's*/0,
      GIR_ConstrainSelectedInstOperands, /*InsnID*/0,
      GIR_EraseFromParent, /*InsnID*/0,
      // GIR_Coverage, 3075,
      GIR_Done,
    // Label 1519: @100968
    GIM_Try, /*On fail goto*//*Label 1520*/ GIMT_Encode4(101032), // Rule ID 3070 //
      GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasFlatGlobalInsts),
      GIM_CheckMemoryAddressSpace, /*MI*/0, /*MMO*/0, /*NumAddrSpace*/3, /*AddrSpace*/1, /*AddrSpace*/4, /*AddrSpace*/6,
      GIM_CheckAtomicOrdering, /*MI*/0, /*Order*/(uint8_t)AtomicOrdering::NotAtomic,
      GIM_CheckRegBankForClass, /*MI*/0, /*Op*/0, /*RC*/GIMT_Encode2(AMDGPU::AV_128RegClassID),
      GIM_CheckPointerToAny, /*MI*/0, /*Op*/1, /*SizeInBits*/0,
      GIM_CheckComplexPattern, /*MI*/0, /*Op*/1, /*Renderer*/GIMT_Encode2(0), GIMT_Encode2(GICP_gi_global_offset),
      // (ld:{ *:[v4i32] } (GlobalOffset:{ *:[iPTR] } VReg_64:{ *:[i64] }:$vaddr, i32:{ *:[i32] }:$offset))<<P:Predicate_unindexedload>><<P:Predicate_load_global>>  =>  (GLOBAL_LOAD_DWORDX4:{ *:[v4i32] } ?:{ *:[i64] }:$vaddr, ?:{ *:[i32] }:$offset)
      GIR_BuildMI, /*InsnID*/0, /*Opcode*/GIMT_Encode2(AMDGPU::GLOBAL_LOAD_DWORDX4),
      GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/0, // DstI[vdst]
      GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/0, // vaddr
      GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/1, // offset
      GIR_AddImm8, /*InsnID*/0, /*Imm*/0,
      GIR_MergeMemOperands, /*InsnID*/0, /*NumInsns*/1, /*MergeInsnID's*/0,
      GIR_ConstrainSelectedInstOperands, /*InsnID*/0,
      GIR_EraseFromParent, /*InsnID*/0,
      // GIR_Coverage, 3070,
      GIR_Done,
    // Label 1520: @101032
    GIM_Try, /*On fail goto*//*Label 1521*/ GIMT_Encode4(101096), // Rule ID 3074 //
      GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasFlatGlobalInsts),
      GIM_CheckMemoryAddressSpace, /*MI*/0, /*MMO*/0, /*NumAddrSpace*/3, /*AddrSpace*/1, /*AddrSpace*/4, /*AddrSpace*/6,
      GIM_CheckAtomicOrdering, /*MI*/0, /*Order*/(uint8_t)AtomicOrdering::NotAtomic,
      GIM_CheckRegBankForClass, /*MI*/0, /*Op*/0, /*RC*/GIMT_Encode2(AMDGPU::AV_128RegClassID),
      GIM_CheckPointerToAny, /*MI*/0, /*Op*/1, /*SizeInBits*/0,
      GIM_CheckComplexPattern, /*MI*/0, /*Op*/1, /*Renderer*/GIMT_Encode2(0), GIMT_Encode2(GICP_gi_global_offset),
      // (ld:{ *:[v4f32] } (GlobalOffset:{ *:[iPTR] } VReg_64:{ *:[i64] }:$vaddr, i32:{ *:[i32] }:$offset))<<P:Predicate_unindexedload>><<P:Predicate_load_global>>  =>  (GLOBAL_LOAD_DWORDX4:{ *:[v4f32] } ?:{ *:[i64] }:$vaddr, ?:{ *:[i32] }:$offset)
      GIR_BuildMI, /*InsnID*/0, /*Opcode*/GIMT_Encode2(AMDGPU::GLOBAL_LOAD_DWORDX4),
      GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/0, // DstI[vdst]
      GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/0, // vaddr
      GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/1, // offset
      GIR_AddImm8, /*InsnID*/0, /*Imm*/0,
      GIR_MergeMemOperands, /*InsnID*/0, /*NumInsns*/1, /*MergeInsnID's*/0,
      GIR_ConstrainSelectedInstOperands, /*InsnID*/0,
      GIR_EraseFromParent, /*InsnID*/0,
      // GIR_Coverage, 3074,
      GIR_Done,
    // Label 1521: @101096
    GIM_Try, /*On fail goto*//*Label 1522*/ GIMT_Encode4(101161), // Rule ID 2809 //
      GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasFlatAddressSpace),
      GIM_CheckMemoryAddressSpace, /*MI*/0, /*MMO*/0, /*NumAddrSpace*/4, /*AddrSpace*/0, /*AddrSpace*/1, /*AddrSpace*/4, /*AddrSpace*/6,
      GIM_CheckAtomicOrdering, /*MI*/0, /*Order*/(uint8_t)AtomicOrdering::NotAtomic,
      GIM_CheckRegBankForClass, /*MI*/0, /*Op*/0, /*RC*/GIMT_Encode2(AMDGPU::AV_128RegClassID),
      GIM_CheckPointerToAny, /*MI*/0, /*Op*/1, /*SizeInBits*/0,
      GIM_CheckComplexPattern, /*MI*/0, /*Op*/1, /*Renderer*/GIMT_Encode2(0), GIMT_Encode2(GICP_gi_flat_offset),
      // (ld:{ *:[v4i32] } (FlatOffset:{ *:[iPTR] } i64:{ *:[i64] }:$vaddr, i32:{ *:[i32] }:$offset))<<P:Predicate_unindexedload>><<P:Predicate_load_flat>>  =>  (FLAT_LOAD_DWORDX4:{ *:[v4i32] } ?:{ *:[i64] }:$vaddr, ?:{ *:[i32] }:$offset)
      GIR_BuildMI, /*InsnID*/0, /*Opcode*/GIMT_Encode2(AMDGPU::FLAT_LOAD_DWORDX4),
      GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/0, // DstI[vdst]
      GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/0, // vaddr
      GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/1, // offset
      GIR_AddImm8, /*InsnID*/0, /*Imm*/0,
      GIR_MergeMemOperands, /*InsnID*/0, /*NumInsns*/1, /*MergeInsnID's*/0,
      GIR_ConstrainSelectedInstOperands, /*InsnID*/0,
      GIR_EraseFromParent, /*InsnID*/0,
      // GIR_Coverage, 2809,
      GIR_Done,
    // Label 1522: @101161
    GIM_Try, /*On fail goto*//*Label 1523*/ GIMT_Encode4(101226), // Rule ID 2811 //
      GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasFlatAddressSpace),
      GIM_CheckMemoryAddressSpace, /*MI*/0, /*MMO*/0, /*NumAddrSpace*/4, /*AddrSpace*/0, /*AddrSpace*/1, /*AddrSpace*/4, /*AddrSpace*/6,
      GIM_CheckAtomicOrdering, /*MI*/0, /*Order*/(uint8_t)AtomicOrdering::NotAtomic,
      GIM_CheckRegBankForClass, /*MI*/0, /*Op*/0, /*RC*/GIMT_Encode2(AMDGPU::AV_128RegClassID),
      GIM_CheckPointerToAny, /*MI*/0, /*Op*/1, /*SizeInBits*/0,
      GIM_CheckComplexPattern, /*MI*/0, /*Op*/1, /*Renderer*/GIMT_Encode2(0), GIMT_Encode2(GICP_gi_flat_offset),
      // (ld:{ *:[v4f32] } (FlatOffset:{ *:[iPTR] } i64:{ *:[i64] }:$vaddr, i32:{ *:[i32] }:$offset))<<P:Predicate_unindexedload>><<P:Predicate_load_flat>>  =>  (FLAT_LOAD_DWORDX4:{ *:[v4f32] } ?:{ *:[i64] }:$vaddr, ?:{ *:[i32] }:$offset)
      GIR_BuildMI, /*InsnID*/0, /*Opcode*/GIMT_Encode2(AMDGPU::FLAT_LOAD_DWORDX4),
      GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/0, // DstI[vdst]
      GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/0, // vaddr
      GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/1, // offset
      GIR_AddImm8, /*InsnID*/0, /*Imm*/0,
      GIR_MergeMemOperands, /*InsnID*/0, /*NumInsns*/1, /*MergeInsnID's*/0,
      GIR_ConstrainSelectedInstOperands, /*InsnID*/0,
      GIR_EraseFromParent, /*InsnID*/0,
      // GIR_Coverage, 2811,
      GIR_Done,
    // Label 1523: @101226
    GIM_Reject,
    // Label 833: @101227
    GIM_Try, /*On fail goto*//*Label 1524*/ GIMT_Encode4(101831),
      GIM_CheckMemorySizeEqualToLLT, /*MI*/0, /*MMO*/0, /*OpIdx*/0,
      GIM_CheckCxxInsnPredicate, /*MI*/0, /*FnId*/GIMT_Encode2(GICXXPred_MI_Predicate_smrd_load),
      GIM_CheckAtomicOrdering, /*MI*/0, /*Order*/(uint8_t)AtomicOrdering::NotAtomic,
      GIM_CheckRegBankForClass, /*MI*/0, /*Op*/0, /*RC*/GIMT_Encode2(AMDGPU::SReg_256RegClassID),
      GIM_Try, /*On fail goto*//*Label 1525*/ GIMT_Encode4(101302), // Rule ID 2616 //
        GIM_CheckFeatures, GIMT_Encode2(GIFBS_isGFX9Plus),
        GIM_CheckPointerToAny, /*MI*/0, /*Op*/1, /*SizeInBits*/0,
        GIM_CheckComplexPattern, /*MI*/0, /*Op*/1, /*Renderer*/GIMT_Encode2(0), GIMT_Encode2(GICP_gi_smrd_sgpr_imm),
        // (ld:{ *:[v4i64] } (SMRDSgprImm:{ *:[iPTR] } i64:{ *:[i64] }:$sbase, i32:{ *:[i32] }:$soffset, i32:{ *:[i32] }:$offset))<<P:Predicate_unindexedload>><<P:Predicate_load>><<P:Predicate_smrd_load>>  =>  (S_LOAD_DWORDX8_SGPR_IMM:{ *:[v4i64] } ?:{ *:[i64] }:$sbase, ?:{ *:[i32] }:$soffset, ?:{ *:[i32] }:$offset, 0:{ *:[i32] })
        GIR_BuildMI, /*InsnID*/0, /*Opcode*/GIMT_Encode2(AMDGPU::S_LOAD_DWORDX8_SGPR_IMM),
        GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/0, // DstI[sdst]
        GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/0, // sbase
        GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/1, // soffset
        GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/2, // offset
        GIR_AddImm8, /*InsnID*/0, /*Imm*/0,
        GIR_MergeMemOperands, /*InsnID*/0, /*NumInsns*/1, /*MergeInsnID's*/0,
        GIR_ConstrainSelectedInstOperands, /*InsnID*/0,
        GIR_EraseFromParent, /*InsnID*/0,
        // GIR_Coverage, 2616,
        GIR_Done,
      // Label 1525: @101302
      GIM_Try, /*On fail goto*//*Label 1526*/ GIMT_Encode4(101356), // Rule ID 2622 //
        GIM_CheckFeatures, GIMT_Encode2(GIFBS_isGFX9Plus),
        GIM_CheckPointerToAny, /*MI*/0, /*Op*/1, /*SizeInBits*/0,
        GIM_CheckComplexPattern, /*MI*/0, /*Op*/1, /*Renderer*/GIMT_Encode2(0), GIMT_Encode2(GICP_gi_smrd_sgpr_imm),
        // (ld:{ *:[v4f64] } (SMRDSgprImm:{ *:[iPTR] } i64:{ *:[i64] }:$sbase, i32:{ *:[i32] }:$soffset, i32:{ *:[i32] }:$offset))<<P:Predicate_unindexedload>><<P:Predicate_load>><<P:Predicate_smrd_load>>  =>  (S_LOAD_DWORDX8_SGPR_IMM:{ *:[v4f64] } ?:{ *:[i64] }:$sbase, ?:{ *:[i32] }:$soffset, ?:{ *:[i32] }:$offset, 0:{ *:[i32] })
        GIR_BuildMI, /*InsnID*/0, /*Opcode*/GIMT_Encode2(AMDGPU::S_LOAD_DWORDX8_SGPR_IMM),
        GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/0, // DstI[sdst]
        GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/0, // sbase
        GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/1, // soffset
        GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/2, // offset
        GIR_AddImm8, /*InsnID*/0, /*Imm*/0,
        GIR_MergeMemOperands, /*InsnID*/0, /*NumInsns*/1, /*MergeInsnID's*/0,
        GIR_ConstrainSelectedInstOperands, /*InsnID*/0,
        GIR_EraseFromParent, /*InsnID*/0,
        // GIR_Coverage, 2622,
        GIR_Done,
      // Label 1526: @101356
      GIM_Try, /*On fail goto*//*Label 1527*/ GIMT_Encode4(101402), // Rule ID 2612 //
        GIM_CheckPointerToAny, /*MI*/0, /*Op*/1, /*SizeInBits*/0,
        GIM_CheckComplexPattern, /*MI*/0, /*Op*/1, /*Renderer*/GIMT_Encode2(0), GIMT_Encode2(GICP_gi_smrd_imm),
        // (ld:{ *:[v4i64] } (SMRDImm:{ *:[iPTR] } i64:{ *:[i64] }:$sbase, i32:{ *:[i32] }:$offset))<<P:Predicate_unindexedload>><<P:Predicate_load>><<P:Predicate_smrd_load>>  =>  (S_LOAD_DWORDX8_IMM:{ *:[v4i64] } ?:{ *:[i64] }:$sbase, ?:{ *:[i32] }:$offset, 0:{ *:[i32] })
        GIR_BuildMI, /*InsnID*/0, /*Opcode*/GIMT_Encode2(AMDGPU::S_LOAD_DWORDX8_IMM),
        GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/0, // DstI[sdst]
        GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/0, // sbase
        GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/1, // offset
        GIR_AddImm8, /*InsnID*/0, /*Imm*/0,
        GIR_MergeMemOperands, /*InsnID*/0, /*NumInsns*/1, /*MergeInsnID's*/0,
        GIR_ConstrainSelectedInstOperands, /*InsnID*/0,
        GIR_EraseFromParent, /*InsnID*/0,
        // GIR_Coverage, 2612,
        GIR_Done,
      // Label 1527: @101402
      GIM_Try, /*On fail goto*//*Label 1528*/ GIMT_Encode4(101451), // Rule ID 2613 //
        GIM_CheckFeatures, GIMT_Encode2(GIFBS_isGFX7Only),
        GIM_CheckPointerToAny, /*MI*/0, /*Op*/1, /*SizeInBits*/0,
        GIM_CheckComplexPattern, /*MI*/0, /*Op*/1, /*Renderer*/GIMT_Encode2(0), GIMT_Encode2(GICP_gi_smrd_imm32),
        // (ld:{ *:[v4i64] } (SMRDImm32:{ *:[iPTR] } i64:{ *:[i64] }:$sbase, i32:{ *:[i32] }:$offset))<<P:Predicate_unindexedload>><<P:Predicate_load>><<P:Predicate_smrd_load>>  =>  (S_LOAD_DWORDX8_IMM_ci:{ *:[v4i64] } ?:{ *:[i64] }:$sbase, ?:{ *:[i32] }:$offset, 0:{ *:[i32] })
        GIR_BuildMI, /*InsnID*/0, /*Opcode*/GIMT_Encode2(AMDGPU::S_LOAD_DWORDX8_IMM_ci),
        GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/0, // DstI[sdst]
        GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/0, // sbase
        GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/1, // offset
        GIR_AddImm8, /*InsnID*/0, /*Imm*/0,
        GIR_MergeMemOperands, /*InsnID*/0, /*NumInsns*/1, /*MergeInsnID's*/0,
        GIR_ConstrainSelectedInstOperands, /*InsnID*/0,
        GIR_EraseFromParent, /*InsnID*/0,
        // GIR_Coverage, 2613,
        GIR_Done,
      // Label 1528: @101451
      GIM_Try, /*On fail goto*//*Label 1529*/ GIMT_Encode4(101500), // Rule ID 2614 //
        GIM_CheckFeatures, GIMT_Encode2(GIFBS_isNotGFX9Plus),
        GIM_CheckPointerToAny, /*MI*/0, /*Op*/1, /*SizeInBits*/0,
        GIM_CheckComplexPattern, /*MI*/0, /*Op*/1, /*Renderer*/GIMT_Encode2(0), GIMT_Encode2(GICP_gi_smrd_sgpr),
        // (ld:{ *:[v4i64] } (SMRDSgpr:{ *:[iPTR] } i64:{ *:[i64] }:$sbase, i32:{ *:[i32] }:$soffset))<<P:Predicate_unindexedload>><<P:Predicate_load>><<P:Predicate_smrd_load>>  =>  (S_LOAD_DWORDX8_SGPR:{ *:[v4i64] } ?:{ *:[i64] }:$sbase, ?:{ *:[i32] }:$soffset, 0:{ *:[i32] })
        GIR_BuildMI, /*InsnID*/0, /*Opcode*/GIMT_Encode2(AMDGPU::S_LOAD_DWORDX8_SGPR),
        GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/0, // DstI[sdst]
        GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/0, // sbase
        GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/1, // soffset
        GIR_AddImm8, /*InsnID*/0, /*Imm*/0,
        GIR_MergeMemOperands, /*InsnID*/0, /*NumInsns*/1, /*MergeInsnID's*/0,
        GIR_ConstrainSelectedInstOperands, /*InsnID*/0,
        GIR_EraseFromParent, /*InsnID*/0,
        // GIR_Coverage, 2614,
        GIR_Done,
      // Label 1529: @101500
      GIM_Try, /*On fail goto*//*Label 1530*/ GIMT_Encode4(101552), // Rule ID 2615 //
        GIM_CheckFeatures, GIMT_Encode2(GIFBS_isGFX9Plus),
        GIM_CheckPointerToAny, /*MI*/0, /*Op*/1, /*SizeInBits*/0,
        GIM_CheckComplexPattern, /*MI*/0, /*Op*/1, /*Renderer*/GIMT_Encode2(0), GIMT_Encode2(GICP_gi_smrd_sgpr),
        // (ld:{ *:[v4i64] } (SMRDSgpr:{ *:[iPTR] } i64:{ *:[i64] }:$sbase, i32:{ *:[i32] }:$soffset))<<P:Predicate_unindexedload>><<P:Predicate_load>><<P:Predicate_smrd_load>>  =>  (S_LOAD_DWORDX8_SGPR_IMM:{ *:[v4i64] } ?:{ *:[i64] }:$sbase, ?:{ *:[i32] }:$soffset, 0:{ *:[i32] }, 0:{ *:[i32] })
        GIR_BuildMI, /*InsnID*/0, /*Opcode*/GIMT_Encode2(AMDGPU::S_LOAD_DWORDX8_SGPR_IMM),
        GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/0, // DstI[sdst]
        GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/0, // sbase
        GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/1, // soffset
        GIR_AddImm8, /*InsnID*/0, /*Imm*/0,
        GIR_AddImm8, /*InsnID*/0, /*Imm*/0,
        GIR_MergeMemOperands, /*InsnID*/0, /*NumInsns*/1, /*MergeInsnID's*/0,
        GIR_ConstrainSelectedInstOperands, /*InsnID*/0,
        GIR_EraseFromParent, /*InsnID*/0,
        // GIR_Coverage, 2615,
        GIR_Done,
      // Label 1530: @101552
      GIM_Try, /*On fail goto*//*Label 1531*/ GIMT_Encode4(101598), // Rule ID 2618 //
        GIM_CheckPointerToAny, /*MI*/0, /*Op*/1, /*SizeInBits*/0,
        GIM_CheckComplexPattern, /*MI*/0, /*Op*/1, /*Renderer*/GIMT_Encode2(0), GIMT_Encode2(GICP_gi_smrd_imm),
        // (ld:{ *:[v4f64] } (SMRDImm:{ *:[iPTR] } i64:{ *:[i64] }:$sbase, i32:{ *:[i32] }:$offset))<<P:Predicate_unindexedload>><<P:Predicate_load>><<P:Predicate_smrd_load>>  =>  (S_LOAD_DWORDX8_IMM:{ *:[v4f64] } ?:{ *:[i64] }:$sbase, ?:{ *:[i32] }:$offset, 0:{ *:[i32] })
        GIR_BuildMI, /*InsnID*/0, /*Opcode*/GIMT_Encode2(AMDGPU::S_LOAD_DWORDX8_IMM),
        GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/0, // DstI[sdst]
        GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/0, // sbase
        GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/1, // offset
        GIR_AddImm8, /*InsnID*/0, /*Imm*/0,
        GIR_MergeMemOperands, /*InsnID*/0, /*NumInsns*/1, /*MergeInsnID's*/0,
        GIR_ConstrainSelectedInstOperands, /*InsnID*/0,
        GIR_EraseFromParent, /*InsnID*/0,
        // GIR_Coverage, 2618,
        GIR_Done,
      // Label 1531: @101598
      GIM_Try, /*On fail goto*//*Label 1532*/ GIMT_Encode4(101647), // Rule ID 2619 //
        GIM_CheckFeatures, GIMT_Encode2(GIFBS_isGFX7Only),
        GIM_CheckPointerToAny, /*MI*/0, /*Op*/1, /*SizeInBits*/0,
        GIM_CheckComplexPattern, /*MI*/0, /*Op*/1, /*Renderer*/GIMT_Encode2(0), GIMT_Encode2(GICP_gi_smrd_imm32),
        // (ld:{ *:[v4f64] } (SMRDImm32:{ *:[iPTR] } i64:{ *:[i64] }:$sbase, i32:{ *:[i32] }:$offset))<<P:Predicate_unindexedload>><<P:Predicate_load>><<P:Predicate_smrd_load>>  =>  (S_LOAD_DWORDX8_IMM_ci:{ *:[v4f64] } ?:{ *:[i64] }:$sbase, ?:{ *:[i32] }:$offset, 0:{ *:[i32] })
        GIR_BuildMI, /*InsnID*/0, /*Opcode*/GIMT_Encode2(AMDGPU::S_LOAD_DWORDX8_IMM_ci),
        GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/0, // DstI[sdst]
        GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/0, // sbase
        GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/1, // offset
        GIR_AddImm8, /*InsnID*/0, /*Imm*/0,
        GIR_MergeMemOperands, /*InsnID*/0, /*NumInsns*/1, /*MergeInsnID's*/0,
        GIR_ConstrainSelectedInstOperands, /*InsnID*/0,
        GIR_EraseFromParent, /*InsnID*/0,
        // GIR_Coverage, 2619,
        GIR_Done,
      // Label 1532: @101647
      GIM_Try, /*On fail goto*//*Label 1533*/ GIMT_Encode4(101696), // Rule ID 2620 //
        GIM_CheckFeatures, GIMT_Encode2(GIFBS_isNotGFX9Plus),
        GIM_CheckPointerToAny, /*MI*/0, /*Op*/1, /*SizeInBits*/0,
        GIM_CheckComplexPattern, /*MI*/0, /*Op*/1, /*Renderer*/GIMT_Encode2(0), GIMT_Encode2(GICP_gi_smrd_sgpr),
        // (ld:{ *:[v4f64] } (SMRDSgpr:{ *:[iPTR] } i64:{ *:[i64] }:$sbase, i32:{ *:[i32] }:$soffset))<<P:Predicate_unindexedload>><<P:Predicate_load>><<P:Predicate_smrd_load>>  =>  (S_LOAD_DWORDX8_SGPR:{ *:[v4f64] } ?:{ *:[i64] }:$sbase, ?:{ *:[i32] }:$soffset, 0:{ *:[i32] })
        GIR_BuildMI, /*InsnID*/0, /*Opcode*/GIMT_Encode2(AMDGPU::S_LOAD_DWORDX8_SGPR),
        GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/0, // DstI[sdst]
        GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/0, // sbase
        GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/1, // soffset
        GIR_AddImm8, /*InsnID*/0, /*Imm*/0,
        GIR_MergeMemOperands, /*InsnID*/0, /*NumInsns*/1, /*MergeInsnID's*/0,
        GIR_ConstrainSelectedInstOperands, /*InsnID*/0,
        GIR_EraseFromParent, /*InsnID*/0,
        // GIR_Coverage, 2620,
        GIR_Done,
      // Label 1533: @101696
      GIM_Try, /*On fail goto*//*Label 1534*/ GIMT_Encode4(101748), // Rule ID 2621 //
        GIM_CheckFeatures, GIMT_Encode2(GIFBS_isGFX9Plus),
        GIM_CheckPointerToAny, /*MI*/0, /*Op*/1, /*SizeInBits*/0,
        GIM_CheckComplexPattern, /*MI*/0, /*Op*/1, /*Renderer*/GIMT_Encode2(0), GIMT_Encode2(GICP_gi_smrd_sgpr),
        // (ld:{ *:[v4f64] } (SMRDSgpr:{ *:[iPTR] } i64:{ *:[i64] }:$sbase, i32:{ *:[i32] }:$soffset))<<P:Predicate_unindexedload>><<P:Predicate_load>><<P:Predicate_smrd_load>>  =>  (S_LOAD_DWORDX8_SGPR_IMM:{ *:[v4f64] } ?:{ *:[i64] }:$sbase, ?:{ *:[i32] }:$soffset, 0:{ *:[i32] }, 0:{ *:[i32] })
        GIR_BuildMI, /*InsnID*/0, /*Opcode*/GIMT_Encode2(AMDGPU::S_LOAD_DWORDX8_SGPR_IMM),
        GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/0, // DstI[sdst]
        GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/0, // sbase
        GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/1, // soffset
        GIR_AddImm8, /*InsnID*/0, /*Imm*/0,
        GIR_AddImm8, /*InsnID*/0, /*Imm*/0,
        GIR_MergeMemOperands, /*InsnID*/0, /*NumInsns*/1, /*MergeInsnID's*/0,
        GIR_ConstrainSelectedInstOperands, /*InsnID*/0,
        GIR_EraseFromParent, /*InsnID*/0,
        // GIR_Coverage, 2621,
        GIR_Done,
      // Label 1534: @101748
      GIM_Try, /*On fail goto*//*Label 1535*/ GIMT_Encode4(101789), // Rule ID 2617 //
        // MIs[0] sbase
        GIM_CheckPointerToAny, /*MI*/0, /*Op*/1, /*SizeInBits*/64,
        GIM_CheckRegBankForClass, /*MI*/0, /*Op*/1, /*RC*/GIMT_Encode2(AMDGPU::SReg_64RegClassID),
        // (ld:{ *:[v4i64] } SReg_64:{ *:[i64] }:$sbase)<<P:Predicate_unindexedload>><<P:Predicate_load>><<P:Predicate_smrd_load>>  =>  (S_LOAD_DWORDX8_IMM:{ *:[v4i64] } i64:{ *:[i64] }:$sbase, 0:{ *:[i32] }, 0:{ *:[i32] })
        GIR_BuildMI, /*InsnID*/0, /*Opcode*/GIMT_Encode2(AMDGPU::S_LOAD_DWORDX8_IMM),
        GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/0, // DstI[sdst]
        GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/1, // sbase
        GIR_AddImm8, /*InsnID*/0, /*Imm*/0,
        GIR_AddImm8, /*InsnID*/0, /*Imm*/0,
        GIR_MergeMemOperands, /*InsnID*/0, /*NumInsns*/1, /*MergeInsnID's*/0,
        GIR_ConstrainSelectedInstOperands, /*InsnID*/0,
        GIR_EraseFromParent, /*InsnID*/0,
        // GIR_Coverage, 2617,
        GIR_Done,
      // Label 1535: @101789
      GIM_Try, /*On fail goto*//*Label 1536*/ GIMT_Encode4(101830), // Rule ID 2623 //
        // MIs[0] sbase
        GIM_CheckPointerToAny, /*MI*/0, /*Op*/1, /*SizeInBits*/64,
        GIM_CheckRegBankForClass, /*MI*/0, /*Op*/1, /*RC*/GIMT_Encode2(AMDGPU::SReg_64RegClassID),
        // (ld:{ *:[v4f64] } SReg_64:{ *:[i64] }:$sbase)<<P:Predicate_unindexedload>><<P:Predicate_load>><<P:Predicate_smrd_load>>  =>  (S_LOAD_DWORDX8_IMM:{ *:[v4f64] } i64:{ *:[i64] }:$sbase, 0:{ *:[i32] }, 0:{ *:[i32] })
        GIR_BuildMI, /*InsnID*/0, /*Opcode*/GIMT_Encode2(AMDGPU::S_LOAD_DWORDX8_IMM),
        GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/0, // DstI[sdst]
        GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/1, // sbase
        GIR_AddImm8, /*InsnID*/0, /*Imm*/0,
        GIR_AddImm8, /*InsnID*/0, /*Imm*/0,
        GIR_MergeMemOperands, /*InsnID*/0, /*NumInsns*/1, /*MergeInsnID's*/0,
        GIR_ConstrainSelectedInstOperands, /*InsnID*/0,
        GIR_EraseFromParent, /*InsnID*/0,
        // GIR_Coverage, 2623,
        GIR_Done,
      // Label 1536: @101830
      GIM_Reject,
    // Label 1524: @101831
    GIM_Reject,
    // Label 834: @101832
    GIM_Try, /*On fail goto*//*Label 1537*/ GIMT_Encode4(101902), // Rule ID 2586 //
      GIM_CheckFeatures, GIMT_Encode2(GIFBS_isGFX9Plus),
      GIM_CheckMemorySizeEqualToLLT, /*MI*/0, /*MMO*/0, /*OpIdx*/0,
      GIM_CheckAtomicOrdering, /*MI*/0, /*Order*/(uint8_t)AtomicOrdering::NotAtomic,
      GIM_CheckRegBankForClass, /*MI*/0, /*Op*/0, /*RC*/GIMT_Encode2(AMDGPU::SReg_128RegClassID),
      GIM_CheckPointerToAny, /*MI*/0, /*Op*/1, /*SizeInBits*/0,
      GIM_CheckCxxInsnPredicate, /*MI*/0, /*FnId*/GIMT_Encode2(GICXXPred_MI_Predicate_smrd_load),
      GIM_CheckComplexPattern, /*MI*/0, /*Op*/1, /*Renderer*/GIMT_Encode2(0), GIMT_Encode2(GICP_gi_smrd_sgpr_imm),
      // (ld:{ *:[v8i16] } (SMRDSgprImm:{ *:[iPTR] } i64:{ *:[i64] }:$sbase, i32:{ *:[i32] }:$soffset, i32:{ *:[i32] }:$offset))<<P:Predicate_unindexedload>><<P:Predicate_load>><<P:Predicate_smrd_load>>  =>  (S_LOAD_DWORDX4_SGPR_IMM:{ *:[v8i16] } ?:{ *:[i64] }:$sbase, ?:{ *:[i32] }:$soffset, ?:{ *:[i32] }:$offset, 0:{ *:[i32] })
      GIR_BuildMI, /*InsnID*/0, /*Opcode*/GIMT_Encode2(AMDGPU::S_LOAD_DWORDX4_SGPR_IMM),
      GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/0, // DstI[sdst]
      GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/0, // sbase
      GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/1, // soffset
      GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/2, // offset
      GIR_AddImm8, /*InsnID*/0, /*Imm*/0,
      GIR_MergeMemOperands, /*InsnID*/0, /*NumInsns*/1, /*MergeInsnID's*/0,
      GIR_ConstrainSelectedInstOperands, /*InsnID*/0,
      GIR_EraseFromParent, /*InsnID*/0,
      // GIR_Coverage, 2586,
      GIR_Done,
    // Label 1537: @101902
    GIM_Try, /*On fail goto*//*Label 1538*/ GIMT_Encode4(101972), // Rule ID 2592 //
      GIM_CheckFeatures, GIMT_Encode2(GIFBS_isGFX9Plus),
      GIM_CheckMemorySizeEqualToLLT, /*MI*/0, /*MMO*/0, /*OpIdx*/0,
      GIM_CheckAtomicOrdering, /*MI*/0, /*Order*/(uint8_t)AtomicOrdering::NotAtomic,
      GIM_CheckRegBankForClass, /*MI*/0, /*Op*/0, /*RC*/GIMT_Encode2(AMDGPU::SReg_128RegClassID),
      GIM_CheckPointerToAny, /*MI*/0, /*Op*/1, /*SizeInBits*/0,
      GIM_CheckCxxInsnPredicate, /*MI*/0, /*FnId*/GIMT_Encode2(GICXXPred_MI_Predicate_smrd_load),
      GIM_CheckComplexPattern, /*MI*/0, /*Op*/1, /*Renderer*/GIMT_Encode2(0), GIMT_Encode2(GICP_gi_smrd_sgpr_imm),
      // (ld:{ *:[v8f16] } (SMRDSgprImm:{ *:[iPTR] } i64:{ *:[i64] }:$sbase, i32:{ *:[i32] }:$soffset, i32:{ *:[i32] }:$offset))<<P:Predicate_unindexedload>><<P:Predicate_load>><<P:Predicate_smrd_load>>  =>  (S_LOAD_DWORDX4_SGPR_IMM:{ *:[v8f16] } ?:{ *:[i64] }:$sbase, ?:{ *:[i32] }:$soffset, ?:{ *:[i32] }:$offset, 0:{ *:[i32] })
      GIR_BuildMI, /*InsnID*/0, /*Opcode*/GIMT_Encode2(AMDGPU::S_LOAD_DWORDX4_SGPR_IMM),
      GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/0, // DstI[sdst]
      GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/0, // sbase
      GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/1, // soffset
      GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/2, // offset
      GIR_AddImm8, /*InsnID*/0, /*Imm*/0,
      GIR_MergeMemOperands, /*InsnID*/0, /*NumInsns*/1, /*MergeInsnID's*/0,
      GIR_ConstrainSelectedInstOperands, /*InsnID*/0,
      GIR_EraseFromParent, /*InsnID*/0,
      // GIR_Coverage, 2592,
      GIR_Done,
    // Label 1538: @101972
    GIM_Try, /*On fail goto*//*Label 1539*/ GIMT_Encode4(102042), // Rule ID 2598 //
      GIM_CheckFeatures, GIMT_Encode2(GIFBS_isGFX9Plus),
      GIM_CheckMemorySizeEqualToLLT, /*MI*/0, /*MMO*/0, /*OpIdx*/0,
      GIM_CheckAtomicOrdering, /*MI*/0, /*Order*/(uint8_t)AtomicOrdering::NotAtomic,
      GIM_CheckRegBankForClass, /*MI*/0, /*Op*/0, /*RC*/GIMT_Encode2(AMDGPU::SReg_128RegClassID),
      GIM_CheckPointerToAny, /*MI*/0, /*Op*/1, /*SizeInBits*/0,
      GIM_CheckCxxInsnPredicate, /*MI*/0, /*FnId*/GIMT_Encode2(GICXXPred_MI_Predicate_smrd_load),
      GIM_CheckComplexPattern, /*MI*/0, /*Op*/1, /*Renderer*/GIMT_Encode2(0), GIMT_Encode2(GICP_gi_smrd_sgpr_imm),
      // (ld:{ *:[v8bf16] } (SMRDSgprImm:{ *:[iPTR] } i64:{ *:[i64] }:$sbase, i32:{ *:[i32] }:$soffset, i32:{ *:[i32] }:$offset))<<P:Predicate_unindexedload>><<P:Predicate_load>><<P:Predicate_smrd_load>>  =>  (S_LOAD_DWORDX4_SGPR_IMM:{ *:[v8bf16] } ?:{ *:[i64] }:$sbase, ?:{ *:[i32] }:$soffset, ?:{ *:[i32] }:$offset, 0:{ *:[i32] })
      GIR_BuildMI, /*InsnID*/0, /*Opcode*/GIMT_Encode2(AMDGPU::S_LOAD_DWORDX4_SGPR_IMM),
      GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/0, // DstI[sdst]
      GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/0, // sbase
      GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/1, // soffset
      GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/2, // offset
      GIR_AddImm8, /*InsnID*/0, /*Imm*/0,
      GIR_MergeMemOperands, /*InsnID*/0, /*NumInsns*/1, /*MergeInsnID's*/0,
      GIR_ConstrainSelectedInstOperands, /*InsnID*/0,
      GIR_EraseFromParent, /*InsnID*/0,
      // GIR_Coverage, 2598,
      GIR_Done,
    // Label 1539: @102042
    GIM_Try, /*On fail goto*//*Label 1540*/ GIMT_Encode4(102117), // Rule ID 6879 //
      GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasUnalignedAccessMode_LDSRequiresM0Init),
      GIM_CheckMemorySizeEqualToLLT, /*MI*/0, /*MMO*/0, /*OpIdx*/0,
      GIM_CheckMemoryAddressSpace, /*MI*/0, /*MMO*/0, /*NumAddrSpace*/1, /*AddrSpace*/3,
      GIM_CheckMemoryAddressSpace, /*MI*/0, /*MMO*/0, /*NumAddrSpace*/1, /*AddrSpace*/3,
      GIM_CheckAtomicOrdering, /*MI*/0, /*Order*/(uint8_t)AtomicOrdering::NotAtomic,
      GIM_CheckRegBankForClass, /*MI*/0, /*Op*/0, /*RC*/GIMT_Encode2(AMDGPU::AV_128RegClassID),
      GIM_CheckPointerToAny, /*MI*/0, /*Op*/1, /*SizeInBits*/0,
      GIM_CheckCxxInsnPredicate, /*MI*/0, /*FnId*/GIMT_Encode2(GICXXPred_MI_Predicate_load_align_less_than_4_local_m0),
      GIM_CheckComplexPattern, /*MI*/0, /*Op*/1, /*Renderer*/GIMT_Encode2(0), GIMT_Encode2(GICP_gi_ds_1addr_1offset),
      // (AMDGPUld_glue:{ *:[v8i16] } (DS1Addr1Offset:{ *:[iPTR] } i32:{ *:[i32] }:$ptr, i32:{ *:[i32] }:$offset))<<P:Predicate_unindexedload_glue>><<P:Predicate_load_glue>><<P:Predicate_load_local_m0>><<P:Predicate_load_align_less_than_4_local_m0>>  =>  (DS_READ_B128:{ *:[v8i16] } ?:{ *:[i32] }:$ptr, offset:{ *:[i32] }:$offset, 0:{ *:[i1] })
      GIR_BuildMI, /*InsnID*/0, /*Opcode*/GIMT_Encode2(AMDGPU::DS_READ_B128),
      GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/0, // DstI[vdst]
      GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/0, // ptr
      GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/1, // offset
      GIR_AddImm8, /*InsnID*/0, /*Imm*/0,
      GIR_MergeMemOperands, /*InsnID*/0, /*NumInsns*/1, /*MergeInsnID's*/0,
      GIR_ConstrainSelectedInstOperands, /*InsnID*/0,
      GIR_EraseFromParent, /*InsnID*/0,
      // GIR_Coverage, 6879,
      GIR_Done,
    // Label 1540: @102117
    GIM_Try, /*On fail goto*//*Label 1541*/ GIMT_Encode4(102192), // Rule ID 6883 //
      GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasUnalignedAccessMode_LDSRequiresM0Init),
      GIM_CheckMemorySizeEqualToLLT, /*MI*/0, /*MMO*/0, /*OpIdx*/0,
      GIM_CheckMemoryAddressSpace, /*MI*/0, /*MMO*/0, /*NumAddrSpace*/1, /*AddrSpace*/3,
      GIM_CheckMemoryAddressSpace, /*MI*/0, /*MMO*/0, /*NumAddrSpace*/1, /*AddrSpace*/3,
      GIM_CheckAtomicOrdering, /*MI*/0, /*Order*/(uint8_t)AtomicOrdering::NotAtomic,
      GIM_CheckRegBankForClass, /*MI*/0, /*Op*/0, /*RC*/GIMT_Encode2(AMDGPU::AV_128RegClassID),
      GIM_CheckPointerToAny, /*MI*/0, /*Op*/1, /*SizeInBits*/0,
      GIM_CheckCxxInsnPredicate, /*MI*/0, /*FnId*/GIMT_Encode2(GICXXPred_MI_Predicate_load_align_less_than_4_local_m0),
      GIM_CheckComplexPattern, /*MI*/0, /*Op*/1, /*Renderer*/GIMT_Encode2(0), GIMT_Encode2(GICP_gi_ds_1addr_1offset),
      // (AMDGPUld_glue:{ *:[v8f16] } (DS1Addr1Offset:{ *:[iPTR] } i32:{ *:[i32] }:$ptr, i32:{ *:[i32] }:$offset))<<P:Predicate_unindexedload_glue>><<P:Predicate_load_glue>><<P:Predicate_load_local_m0>><<P:Predicate_load_align_less_than_4_local_m0>>  =>  (DS_READ_B128:{ *:[v8f16] } ?:{ *:[i32] }:$ptr, offset:{ *:[i32] }:$offset, 0:{ *:[i1] })
      GIR_BuildMI, /*InsnID*/0, /*Opcode*/GIMT_Encode2(AMDGPU::DS_READ_B128),
      GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/0, // DstI[vdst]
      GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/0, // ptr
      GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/1, // offset
      GIR_AddImm8, /*InsnID*/0, /*Imm*/0,
      GIR_MergeMemOperands, /*InsnID*/0, /*NumInsns*/1, /*MergeInsnID's*/0,
      GIR_ConstrainSelectedInstOperands, /*InsnID*/0,
      GIR_EraseFromParent, /*InsnID*/0,
      // GIR_Coverage, 6883,
      GIR_Done,
    // Label 1541: @102192
    GIM_Try, /*On fail goto*//*Label 1542*/ GIMT_Encode4(102267), // Rule ID 6887 //
      GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasUnalignedAccessMode_LDSRequiresM0Init),
      GIM_CheckMemorySizeEqualToLLT, /*MI*/0, /*MMO*/0, /*OpIdx*/0,
      GIM_CheckMemoryAddressSpace, /*MI*/0, /*MMO*/0, /*NumAddrSpace*/1, /*AddrSpace*/3,
      GIM_CheckMemoryAddressSpace, /*MI*/0, /*MMO*/0, /*NumAddrSpace*/1, /*AddrSpace*/3,
      GIM_CheckAtomicOrdering, /*MI*/0, /*Order*/(uint8_t)AtomicOrdering::NotAtomic,
      GIM_CheckRegBankForClass, /*MI*/0, /*Op*/0, /*RC*/GIMT_Encode2(AMDGPU::AV_128RegClassID),
      GIM_CheckPointerToAny, /*MI*/0, /*Op*/1, /*SizeInBits*/0,
      GIM_CheckCxxInsnPredicate, /*MI*/0, /*FnId*/GIMT_Encode2(GICXXPred_MI_Predicate_load_align_less_than_4_local_m0),
      GIM_CheckComplexPattern, /*MI*/0, /*Op*/1, /*Renderer*/GIMT_Encode2(0), GIMT_Encode2(GICP_gi_ds_1addr_1offset),
      // (AMDGPUld_glue:{ *:[v8bf16] } (DS1Addr1Offset:{ *:[iPTR] } i32:{ *:[i32] }:$ptr, i32:{ *:[i32] }:$offset))<<P:Predicate_unindexedload_glue>><<P:Predicate_load_glue>><<P:Predicate_load_local_m0>><<P:Predicate_load_align_less_than_4_local_m0>>  =>  (DS_READ_B128:{ *:[v8bf16] } ?:{ *:[i32] }:$ptr, offset:{ *:[i32] }:$offset, 0:{ *:[i1] })
      GIR_BuildMI, /*InsnID*/0, /*Opcode*/GIMT_Encode2(AMDGPU::DS_READ_B128),
      GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/0, // DstI[vdst]
      GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/0, // ptr
      GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/1, // offset
      GIR_AddImm8, /*InsnID*/0, /*Imm*/0,
      GIR_MergeMemOperands, /*InsnID*/0, /*NumInsns*/1, /*MergeInsnID's*/0,
      GIR_ConstrainSelectedInstOperands, /*InsnID*/0,
      GIR_EraseFromParent, /*InsnID*/0,
      // GIR_Coverage, 6887,
      GIR_Done,
    // Label 1542: @102267
    GIM_Try, /*On fail goto*//*Label 1543*/ GIMT_Encode4(102337), // Rule ID 6803 //
      GIM_CheckFeatures, GIMT_Encode2(GIFBS_LDSRequiresM0Init_isGFX7Plus),
      GIM_CheckMemorySizeEqualToLLT, /*MI*/0, /*MMO*/0, /*OpIdx*/0,
      GIM_CheckMemoryAddressSpace, /*MI*/0, /*MMO*/0, /*NumAddrSpace*/1, /*AddrSpace*/3,
      GIM_CheckMemoryAlignment, /*MI*/0, /*MMO*/0, /*MinAlign*/16,
      GIM_CheckAtomicOrdering, /*MI*/0, /*Order*/(uint8_t)AtomicOrdering::NotAtomic,
      GIM_CheckRegBankForClass, /*MI*/0, /*Op*/0, /*RC*/GIMT_Encode2(AMDGPU::AV_128RegClassID),
      GIM_CheckPointerToAny, /*MI*/0, /*Op*/1, /*SizeInBits*/0,
      GIM_CheckComplexPattern, /*MI*/0, /*Op*/1, /*Renderer*/GIMT_Encode2(0), GIMT_Encode2(GICP_gi_ds_1addr_1offset),
      // (AMDGPUld_glue:{ *:[v8i16] } (DS1Addr1Offset:{ *:[iPTR] } i32:{ *:[i32] }:$ptr, i32:{ *:[i32] }:$offset))<<P:Predicate_unindexedload_glue>><<P:Predicate_load_glue>><<P:Predicate_load_local_m0>><<P:Predicate_load_align16_local_m0>>  =>  (DS_READ_B128:{ *:[v8i16] } ?:{ *:[i32] }:$ptr, offset:{ *:[i32] }:$offset, 0:{ *:[i1] })
      GIR_BuildMI, /*InsnID*/0, /*Opcode*/GIMT_Encode2(AMDGPU::DS_READ_B128),
      GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/0, // DstI[vdst]
      GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/0, // ptr
      GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/1, // offset
      GIR_AddImm8, /*InsnID*/0, /*Imm*/0,
      GIR_MergeMemOperands, /*InsnID*/0, /*NumInsns*/1, /*MergeInsnID's*/0,
      GIR_ConstrainSelectedInstOperands, /*InsnID*/0,
      GIR_EraseFromParent, /*InsnID*/0,
      // GIR_Coverage, 6803,
      GIR_Done,
    // Label 1543: @102337
    GIM_Try, /*On fail goto*//*Label 1544*/ GIMT_Encode4(102407), // Rule ID 6807 //
      GIM_CheckFeatures, GIMT_Encode2(GIFBS_LDSRequiresM0Init_isGFX7Plus),
      GIM_CheckMemorySizeEqualToLLT, /*MI*/0, /*MMO*/0, /*OpIdx*/0,
      GIM_CheckMemoryAddressSpace, /*MI*/0, /*MMO*/0, /*NumAddrSpace*/1, /*AddrSpace*/3,
      GIM_CheckMemoryAlignment, /*MI*/0, /*MMO*/0, /*MinAlign*/16,
      GIM_CheckAtomicOrdering, /*MI*/0, /*Order*/(uint8_t)AtomicOrdering::NotAtomic,
      GIM_CheckRegBankForClass, /*MI*/0, /*Op*/0, /*RC*/GIMT_Encode2(AMDGPU::AV_128RegClassID),
      GIM_CheckPointerToAny, /*MI*/0, /*Op*/1, /*SizeInBits*/0,
      GIM_CheckComplexPattern, /*MI*/0, /*Op*/1, /*Renderer*/GIMT_Encode2(0), GIMT_Encode2(GICP_gi_ds_1addr_1offset),
      // (AMDGPUld_glue:{ *:[v8f16] } (DS1Addr1Offset:{ *:[iPTR] } i32:{ *:[i32] }:$ptr, i32:{ *:[i32] }:$offset))<<P:Predicate_unindexedload_glue>><<P:Predicate_load_glue>><<P:Predicate_load_local_m0>><<P:Predicate_load_align16_local_m0>>  =>  (DS_READ_B128:{ *:[v8f16] } ?:{ *:[i32] }:$ptr, offset:{ *:[i32] }:$offset, 0:{ *:[i1] })
      GIR_BuildMI, /*InsnID*/0, /*Opcode*/GIMT_Encode2(AMDGPU::DS_READ_B128),
      GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/0, // DstI[vdst]
      GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/0, // ptr
      GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/1, // offset
      GIR_AddImm8, /*InsnID*/0, /*Imm*/0,
      GIR_MergeMemOperands, /*InsnID*/0, /*NumInsns*/1, /*MergeInsnID's*/0,
      GIR_ConstrainSelectedInstOperands, /*InsnID*/0,
      GIR_EraseFromParent, /*InsnID*/0,
      // GIR_Coverage, 6807,
      GIR_Done,
    // Label 1544: @102407
    GIM_Try, /*On fail goto*//*Label 1545*/ GIMT_Encode4(102477), // Rule ID 6811 //
      GIM_CheckFeatures, GIMT_Encode2(GIFBS_LDSRequiresM0Init_isGFX7Plus),
      GIM_CheckMemorySizeEqualToLLT, /*MI*/0, /*MMO*/0, /*OpIdx*/0,
      GIM_CheckMemoryAddressSpace, /*MI*/0, /*MMO*/0, /*NumAddrSpace*/1, /*AddrSpace*/3,
      GIM_CheckMemoryAlignment, /*MI*/0, /*MMO*/0, /*MinAlign*/16,
      GIM_CheckAtomicOrdering, /*MI*/0, /*Order*/(uint8_t)AtomicOrdering::NotAtomic,
      GIM_CheckRegBankForClass, /*MI*/0, /*Op*/0, /*RC*/GIMT_Encode2(AMDGPU::AV_128RegClassID),
      GIM_CheckPointerToAny, /*MI*/0, /*Op*/1, /*SizeInBits*/0,
      GIM_CheckComplexPattern, /*MI*/0, /*Op*/1, /*Renderer*/GIMT_Encode2(0), GIMT_Encode2(GICP_gi_ds_1addr_1offset),
      // (AMDGPUld_glue:{ *:[v8bf16] } (DS1Addr1Offset:{ *:[iPTR] } i32:{ *:[i32] }:$ptr, i32:{ *:[i32] }:$offset))<<P:Predicate_unindexedload_glue>><<P:Predicate_load_glue>><<P:Predicate_load_local_m0>><<P:Predicate_load_align16_local_m0>>  =>  (DS_READ_B128:{ *:[v8bf16] } ?:{ *:[i32] }:$ptr, offset:{ *:[i32] }:$offset, 0:{ *:[i1] })
      GIR_BuildMI, /*InsnID*/0, /*Opcode*/GIMT_Encode2(AMDGPU::DS_READ_B128),
      GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/0, // DstI[vdst]
      GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/0, // ptr
      GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/1, // offset
      GIR_AddImm8, /*InsnID*/0, /*Imm*/0,
      GIR_MergeMemOperands, /*InsnID*/0, /*NumInsns*/1, /*MergeInsnID's*/0,
      GIR_ConstrainSelectedInstOperands, /*InsnID*/0,
      GIR_EraseFromParent, /*InsnID*/0,
      // GIR_Coverage, 6811,
      GIR_Done,
    // Label 1545: @102477
    GIM_Try, /*On fail goto*//*Label 1546*/ GIMT_Encode4(102539), // Rule ID 2582 //
      GIM_CheckMemorySizeEqualToLLT, /*MI*/0, /*MMO*/0, /*OpIdx*/0,
      GIM_CheckAtomicOrdering, /*MI*/0, /*Order*/(uint8_t)AtomicOrdering::NotAtomic,
      GIM_CheckRegBankForClass, /*MI*/0, /*Op*/0, /*RC*/GIMT_Encode2(AMDGPU::SReg_128RegClassID),
      GIM_CheckPointerToAny, /*MI*/0, /*Op*/1, /*SizeInBits*/0,
      GIM_CheckCxxInsnPredicate, /*MI*/0, /*FnId*/GIMT_Encode2(GICXXPred_MI_Predicate_smrd_load),
      GIM_CheckComplexPattern, /*MI*/0, /*Op*/1, /*Renderer*/GIMT_Encode2(0), GIMT_Encode2(GICP_gi_smrd_imm),
      // (ld:{ *:[v8i16] } (SMRDImm:{ *:[iPTR] } i64:{ *:[i64] }:$sbase, i32:{ *:[i32] }:$offset))<<P:Predicate_unindexedload>><<P:Predicate_load>><<P:Predicate_smrd_load>>  =>  (S_LOAD_DWORDX4_IMM:{ *:[v8i16] } ?:{ *:[i64] }:$sbase, ?:{ *:[i32] }:$offset, 0:{ *:[i32] })
      GIR_BuildMI, /*InsnID*/0, /*Opcode*/GIMT_Encode2(AMDGPU::S_LOAD_DWORDX4_IMM),
      GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/0, // DstI[sdst]
      GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/0, // sbase
      GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/1, // offset
      GIR_AddImm8, /*InsnID*/0, /*Imm*/0,
      GIR_MergeMemOperands, /*InsnID*/0, /*NumInsns*/1, /*MergeInsnID's*/0,
      GIR_ConstrainSelectedInstOperands, /*InsnID*/0,
      GIR_EraseFromParent, /*InsnID*/0,
      // GIR_Coverage, 2582,
      GIR_Done,
    // Label 1546: @102539
    GIM_Try, /*On fail goto*//*Label 1547*/ GIMT_Encode4(102604), // Rule ID 2583 //
      GIM_CheckFeatures, GIMT_Encode2(GIFBS_isGFX7Only),
      GIM_CheckMemorySizeEqualToLLT, /*MI*/0, /*MMO*/0, /*OpIdx*/0,
      GIM_CheckAtomicOrdering, /*MI*/0, /*Order*/(uint8_t)AtomicOrdering::NotAtomic,
      GIM_CheckRegBankForClass, /*MI*/0, /*Op*/0, /*RC*/GIMT_Encode2(AMDGPU::SReg_128RegClassID),
      GIM_CheckPointerToAny, /*MI*/0, /*Op*/1, /*SizeInBits*/0,
      GIM_CheckCxxInsnPredicate, /*MI*/0, /*FnId*/GIMT_Encode2(GICXXPred_MI_Predicate_smrd_load),
      GIM_CheckComplexPattern, /*MI*/0, /*Op*/1, /*Renderer*/GIMT_Encode2(0), GIMT_Encode2(GICP_gi_smrd_imm32),
      // (ld:{ *:[v8i16] } (SMRDImm32:{ *:[iPTR] } i64:{ *:[i64] }:$sbase, i32:{ *:[i32] }:$offset))<<P:Predicate_unindexedload>><<P:Predicate_load>><<P:Predicate_smrd_load>>  =>  (S_LOAD_DWORDX4_IMM_ci:{ *:[v8i16] } ?:{ *:[i64] }:$sbase, ?:{ *:[i32] }:$offset, 0:{ *:[i32] })
      GIR_BuildMI, /*InsnID*/0, /*Opcode*/GIMT_Encode2(AMDGPU::S_LOAD_DWORDX4_IMM_ci),
      GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/0, // DstI[sdst]
      GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/0, // sbase
      GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/1, // offset
      GIR_AddImm8, /*InsnID*/0, /*Imm*/0,
      GIR_MergeMemOperands, /*InsnID*/0, /*NumInsns*/1, /*MergeInsnID's*/0,
      GIR_ConstrainSelectedInstOperands, /*InsnID*/0,
      GIR_EraseFromParent, /*InsnID*/0,
      // GIR_Coverage, 2583,
      GIR_Done,
    // Label 1547: @102604
    GIM_Try, /*On fail goto*//*Label 1548*/ GIMT_Encode4(102669), // Rule ID 2584 //
      GIM_CheckFeatures, GIMT_Encode2(GIFBS_isNotGFX9Plus),
      GIM_CheckMemorySizeEqualToLLT, /*MI*/0, /*MMO*/0, /*OpIdx*/0,
      GIM_CheckAtomicOrdering, /*MI*/0, /*Order*/(uint8_t)AtomicOrdering::NotAtomic,
      GIM_CheckRegBankForClass, /*MI*/0, /*Op*/0, /*RC*/GIMT_Encode2(AMDGPU::SReg_128RegClassID),
      GIM_CheckPointerToAny, /*MI*/0, /*Op*/1, /*SizeInBits*/0,
      GIM_CheckCxxInsnPredicate, /*MI*/0, /*FnId*/GIMT_Encode2(GICXXPred_MI_Predicate_smrd_load),
      GIM_CheckComplexPattern, /*MI*/0, /*Op*/1, /*Renderer*/GIMT_Encode2(0), GIMT_Encode2(GICP_gi_smrd_sgpr),
      // (ld:{ *:[v8i16] } (SMRDSgpr:{ *:[iPTR] } i64:{ *:[i64] }:$sbase, i32:{ *:[i32] }:$soffset))<<P:Predicate_unindexedload>><<P:Predicate_load>><<P:Predicate_smrd_load>>  =>  (S_LOAD_DWORDX4_SGPR:{ *:[v8i16] } ?:{ *:[i64] }:$sbase, ?:{ *:[i32] }:$soffset, 0:{ *:[i32] })
      GIR_BuildMI, /*InsnID*/0, /*Opcode*/GIMT_Encode2(AMDGPU::S_LOAD_DWORDX4_SGPR),
      GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/0, // DstI[sdst]
      GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/0, // sbase
      GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/1, // soffset
      GIR_AddImm8, /*InsnID*/0, /*Imm*/0,
      GIR_MergeMemOperands, /*InsnID*/0, /*NumInsns*/1, /*MergeInsnID's*/0,
      GIR_ConstrainSelectedInstOperands, /*InsnID*/0,
      GIR_EraseFromParent, /*InsnID*/0,
      // GIR_Coverage, 2584,
      GIR_Done,
    // Label 1548: @102669
    GIM_Try, /*On fail goto*//*Label 1549*/ GIMT_Encode4(102737), // Rule ID 2585 //
      GIM_CheckFeatures, GIMT_Encode2(GIFBS_isGFX9Plus),
      GIM_CheckMemorySizeEqualToLLT, /*MI*/0, /*MMO*/0, /*OpIdx*/0,
      GIM_CheckAtomicOrdering, /*MI*/0, /*Order*/(uint8_t)AtomicOrdering::NotAtomic,
      GIM_CheckRegBankForClass, /*MI*/0, /*Op*/0, /*RC*/GIMT_Encode2(AMDGPU::SReg_128RegClassID),
      GIM_CheckPointerToAny, /*MI*/0, /*Op*/1, /*SizeInBits*/0,
      GIM_CheckCxxInsnPredicate, /*MI*/0, /*FnId*/GIMT_Encode2(GICXXPred_MI_Predicate_smrd_load),
      GIM_CheckComplexPattern, /*MI*/0, /*Op*/1, /*Renderer*/GIMT_Encode2(0), GIMT_Encode2(GICP_gi_smrd_sgpr),
      // (ld:{ *:[v8i16] } (SMRDSgpr:{ *:[iPTR] } i64:{ *:[i64] }:$sbase, i32:{ *:[i32] }:$soffset))<<P:Predicate_unindexedload>><<P:Predicate_load>><<P:Predicate_smrd_load>>  =>  (S_LOAD_DWORDX4_SGPR_IMM:{ *:[v8i16] } ?:{ *:[i64] }:$sbase, ?:{ *:[i32] }:$soffset, 0:{ *:[i32] }, 0:{ *:[i32] })
      GIR_BuildMI, /*InsnID*/0, /*Opcode*/GIMT_Encode2(AMDGPU::S_LOAD_DWORDX4_SGPR_IMM),
      GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/0, // DstI[sdst]
      GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/0, // sbase
      GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/1, // soffset
      GIR_AddImm8, /*InsnID*/0, /*Imm*/0,
      GIR_AddImm8, /*InsnID*/0, /*Imm*/0,
      GIR_MergeMemOperands, /*InsnID*/0, /*NumInsns*/1, /*MergeInsnID's*/0,
      GIR_ConstrainSelectedInstOperands, /*InsnID*/0,
      GIR_EraseFromParent, /*InsnID*/0,
      // GIR_Coverage, 2585,
      GIR_Done,
    // Label 1549: @102737
    GIM_Try, /*On fail goto*//*Label 1550*/ GIMT_Encode4(102799), // Rule ID 2588 //
      GIM_CheckMemorySizeEqualToLLT, /*MI*/0, /*MMO*/0, /*OpIdx*/0,
      GIM_CheckAtomicOrdering, /*MI*/0, /*Order*/(uint8_t)AtomicOrdering::NotAtomic,
      GIM_CheckRegBankForClass, /*MI*/0, /*Op*/0, /*RC*/GIMT_Encode2(AMDGPU::SReg_128RegClassID),
      GIM_CheckPointerToAny, /*MI*/0, /*Op*/1, /*SizeInBits*/0,
      GIM_CheckCxxInsnPredicate, /*MI*/0, /*FnId*/GIMT_Encode2(GICXXPred_MI_Predicate_smrd_load),
      GIM_CheckComplexPattern, /*MI*/0, /*Op*/1, /*Renderer*/GIMT_Encode2(0), GIMT_Encode2(GICP_gi_smrd_imm),
      // (ld:{ *:[v8f16] } (SMRDImm:{ *:[iPTR] } i64:{ *:[i64] }:$sbase, i32:{ *:[i32] }:$offset))<<P:Predicate_unindexedload>><<P:Predicate_load>><<P:Predicate_smrd_load>>  =>  (S_LOAD_DWORDX4_IMM:{ *:[v8f16] } ?:{ *:[i64] }:$sbase, ?:{ *:[i32] }:$offset, 0:{ *:[i32] })
      GIR_BuildMI, /*InsnID*/0, /*Opcode*/GIMT_Encode2(AMDGPU::S_LOAD_DWORDX4_IMM),
      GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/0, // DstI[sdst]
      GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/0, // sbase
      GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/1, // offset
      GIR_AddImm8, /*InsnID*/0, /*Imm*/0,
      GIR_MergeMemOperands, /*InsnID*/0, /*NumInsns*/1, /*MergeInsnID's*/0,
      GIR_ConstrainSelectedInstOperands, /*InsnID*/0,
      GIR_EraseFromParent, /*InsnID*/0,
      // GIR_Coverage, 2588,
      GIR_Done,
    // Label 1550: @102799
    GIM_Try, /*On fail goto*//*Label 1551*/ GIMT_Encode4(102864), // Rule ID 2589 //
      GIM_CheckFeatures, GIMT_Encode2(GIFBS_isGFX7Only),
      GIM_CheckMemorySizeEqualToLLT, /*MI*/0, /*MMO*/0, /*OpIdx*/0,
      GIM_CheckAtomicOrdering, /*MI*/0, /*Order*/(uint8_t)AtomicOrdering::NotAtomic,
      GIM_CheckRegBankForClass, /*MI*/0, /*Op*/0, /*RC*/GIMT_Encode2(AMDGPU::SReg_128RegClassID),
      GIM_CheckPointerToAny, /*MI*/0, /*Op*/1, /*SizeInBits*/0,
      GIM_CheckCxxInsnPredicate, /*MI*/0, /*FnId*/GIMT_Encode2(GICXXPred_MI_Predicate_smrd_load),
      GIM_CheckComplexPattern, /*MI*/0, /*Op*/1, /*Renderer*/GIMT_Encode2(0), GIMT_Encode2(GICP_gi_smrd_imm32),
      // (ld:{ *:[v8f16] } (SMRDImm32:{ *:[iPTR] } i64:{ *:[i64] }:$sbase, i32:{ *:[i32] }:$offset))<<P:Predicate_unindexedload>><<P:Predicate_load>><<P:Predicate_smrd_load>>  =>  (S_LOAD_DWORDX4_IMM_ci:{ *:[v8f16] } ?:{ *:[i64] }:$sbase, ?:{ *:[i32] }:$offset, 0:{ *:[i32] })
      GIR_BuildMI, /*InsnID*/0, /*Opcode*/GIMT_Encode2(AMDGPU::S_LOAD_DWORDX4_IMM_ci),
      GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/0, // DstI[sdst]
      GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/0, // sbase
      GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/1, // offset
      GIR_AddImm8, /*InsnID*/0, /*Imm*/0,
      GIR_MergeMemOperands, /*InsnID*/0, /*NumInsns*/1, /*MergeInsnID's*/0,
      GIR_ConstrainSelectedInstOperands, /*InsnID*/0,
      GIR_EraseFromParent, /*InsnID*/0,
      // GIR_Coverage, 2589,
      GIR_Done,
    // Label 1551: @102864
    GIM_Try, /*On fail goto*//*Label 1552*/ GIMT_Encode4(102929), // Rule ID 2590 //
      GIM_CheckFeatures, GIMT_Encode2(GIFBS_isNotGFX9Plus),
      GIM_CheckMemorySizeEqualToLLT, /*MI*/0, /*MMO*/0, /*OpIdx*/0,
      GIM_CheckAtomicOrdering, /*MI*/0, /*Order*/(uint8_t)AtomicOrdering::NotAtomic,
      GIM_CheckRegBankForClass, /*MI*/0, /*Op*/0, /*RC*/GIMT_Encode2(AMDGPU::SReg_128RegClassID),
      GIM_CheckPointerToAny, /*MI*/0, /*Op*/1, /*SizeInBits*/0,
      GIM_CheckCxxInsnPredicate, /*MI*/0, /*FnId*/GIMT_Encode2(GICXXPred_MI_Predicate_smrd_load),
      GIM_CheckComplexPattern, /*MI*/0, /*Op*/1, /*Renderer*/GIMT_Encode2(0), GIMT_Encode2(GICP_gi_smrd_sgpr),
      // (ld:{ *:[v8f16] } (SMRDSgpr:{ *:[iPTR] } i64:{ *:[i64] }:$sbase, i32:{ *:[i32] }:$soffset))<<P:Predicate_unindexedload>><<P:Predicate_load>><<P:Predicate_smrd_load>>  =>  (S_LOAD_DWORDX4_SGPR:{ *:[v8f16] } ?:{ *:[i64] }:$sbase, ?:{ *:[i32] }:$soffset, 0:{ *:[i32] })
      GIR_BuildMI, /*InsnID*/0, /*Opcode*/GIMT_Encode2(AMDGPU::S_LOAD_DWORDX4_SGPR),
      GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/0, // DstI[sdst]
      GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/0, // sbase
      GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/1, // soffset
      GIR_AddImm8, /*InsnID*/0, /*Imm*/0,
      GIR_MergeMemOperands, /*InsnID*/0, /*NumInsns*/1, /*MergeInsnID's*/0,
      GIR_ConstrainSelectedInstOperands, /*InsnID*/0,
      GIR_EraseFromParent, /*InsnID*/0,
      // GIR_Coverage, 2590,
      GIR_Done,
    // Label 1552: @102929
    GIM_Try, /*On fail goto*//*Label 1553*/ GIMT_Encode4(102997), // Rule ID 2591 //
      GIM_CheckFeatures, GIMT_Encode2(GIFBS_isGFX9Plus),
      GIM_CheckMemorySizeEqualToLLT, /*MI*/0, /*MMO*/0, /*OpIdx*/0,
      GIM_CheckAtomicOrdering, /*MI*/0, /*Order*/(uint8_t)AtomicOrdering::NotAtomic,
      GIM_CheckRegBankForClass, /*MI*/0, /*Op*/0, /*RC*/GIMT_Encode2(AMDGPU::SReg_128RegClassID),
      GIM_CheckPointerToAny, /*MI*/0, /*Op*/1, /*SizeInBits*/0,
      GIM_CheckCxxInsnPredicate, /*MI*/0, /*FnId*/GIMT_Encode2(GICXXPred_MI_Predicate_smrd_load),
      GIM_CheckComplexPattern, /*MI*/0, /*Op*/1, /*Renderer*/GIMT_Encode2(0), GIMT_Encode2(GICP_gi_smrd_sgpr),
      // (ld:{ *:[v8f16] } (SMRDSgpr:{ *:[iPTR] } i64:{ *:[i64] }:$sbase, i32:{ *:[i32] }:$soffset))<<P:Predicate_unindexedload>><<P:Predicate_load>><<P:Predicate_smrd_load>>  =>  (S_LOAD_DWORDX4_SGPR_IMM:{ *:[v8f16] } ?:{ *:[i64] }:$sbase, ?:{ *:[i32] }:$soffset, 0:{ *:[i32] }, 0:{ *:[i32] })
      GIR_BuildMI, /*InsnID*/0, /*Opcode*/GIMT_Encode2(AMDGPU::S_LOAD_DWORDX4_SGPR_IMM),
      GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/0, // DstI[sdst]
      GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/0, // sbase
      GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/1, // soffset
      GIR_AddImm8, /*InsnID*/0, /*Imm*/0,
      GIR_AddImm8, /*InsnID*/0, /*Imm*/0,
      GIR_MergeMemOperands, /*InsnID*/0, /*NumInsns*/1, /*MergeInsnID's*/0,
      GIR_ConstrainSelectedInstOperands, /*InsnID*/0,
      GIR_EraseFromParent, /*InsnID*/0,
      // GIR_Coverage, 2591,
      GIR_Done,
    // Label 1553: @102997
    GIM_Try, /*On fail goto*//*Label 1554*/ GIMT_Encode4(103059), // Rule ID 2594 //
      GIM_CheckMemorySizeEqualToLLT, /*MI*/0, /*MMO*/0, /*OpIdx*/0,
      GIM_CheckAtomicOrdering, /*MI*/0, /*Order*/(uint8_t)AtomicOrdering::NotAtomic,
      GIM_CheckRegBankForClass, /*MI*/0, /*Op*/0, /*RC*/GIMT_Encode2(AMDGPU::SReg_128RegClassID),
      GIM_CheckPointerToAny, /*MI*/0, /*Op*/1, /*SizeInBits*/0,
      GIM_CheckCxxInsnPredicate, /*MI*/0, /*FnId*/GIMT_Encode2(GICXXPred_MI_Predicate_smrd_load),
      GIM_CheckComplexPattern, /*MI*/0, /*Op*/1, /*Renderer*/GIMT_Encode2(0), GIMT_Encode2(GICP_gi_smrd_imm),
      // (ld:{ *:[v8bf16] } (SMRDImm:{ *:[iPTR] } i64:{ *:[i64] }:$sbase, i32:{ *:[i32] }:$offset))<<P:Predicate_unindexedload>><<P:Predicate_load>><<P:Predicate_smrd_load>>  =>  (S_LOAD_DWORDX4_IMM:{ *:[v8bf16] } ?:{ *:[i64] }:$sbase, ?:{ *:[i32] }:$offset, 0:{ *:[i32] })
      GIR_BuildMI, /*InsnID*/0, /*Opcode*/GIMT_Encode2(AMDGPU::S_LOAD_DWORDX4_IMM),
      GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/0, // DstI[sdst]
      GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/0, // sbase
      GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/1, // offset
      GIR_AddImm8, /*InsnID*/0, /*Imm*/0,
      GIR_MergeMemOperands, /*InsnID*/0, /*NumInsns*/1, /*MergeInsnID's*/0,
      GIR_ConstrainSelectedInstOperands, /*InsnID*/0,
      GIR_EraseFromParent, /*InsnID*/0,
      // GIR_Coverage, 2594,
      GIR_Done,
    // Label 1554: @103059
    GIM_Try, /*On fail goto*//*Label 1555*/ GIMT_Encode4(103124), // Rule ID 2595 //
      GIM_CheckFeatures, GIMT_Encode2(GIFBS_isGFX7Only),
      GIM_CheckMemorySizeEqualToLLT, /*MI*/0, /*MMO*/0, /*OpIdx*/0,
      GIM_CheckAtomicOrdering, /*MI*/0, /*Order*/(uint8_t)AtomicOrdering::NotAtomic,
      GIM_CheckRegBankForClass, /*MI*/0, /*Op*/0, /*RC*/GIMT_Encode2(AMDGPU::SReg_128RegClassID),
      GIM_CheckPointerToAny, /*MI*/0, /*Op*/1, /*SizeInBits*/0,
      GIM_CheckCxxInsnPredicate, /*MI*/0, /*FnId*/GIMT_Encode2(GICXXPred_MI_Predicate_smrd_load),
      GIM_CheckComplexPattern, /*MI*/0, /*Op*/1, /*Renderer*/GIMT_Encode2(0), GIMT_Encode2(GICP_gi_smrd_imm32),
      // (ld:{ *:[v8bf16] } (SMRDImm32:{ *:[iPTR] } i64:{ *:[i64] }:$sbase, i32:{ *:[i32] }:$offset))<<P:Predicate_unindexedload>><<P:Predicate_load>><<P:Predicate_smrd_load>>  =>  (S_LOAD_DWORDX4_IMM_ci:{ *:[v8bf16] } ?:{ *:[i64] }:$sbase, ?:{ *:[i32] }:$offset, 0:{ *:[i32] })
      GIR_BuildMI, /*InsnID*/0, /*Opcode*/GIMT_Encode2(AMDGPU::S_LOAD_DWORDX4_IMM_ci),
      GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/0, // DstI[sdst]
      GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/0, // sbase
      GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/1, // offset
      GIR_AddImm8, /*InsnID*/0, /*Imm*/0,
      GIR_MergeMemOperands, /*InsnID*/0, /*NumInsns*/1, /*MergeInsnID's*/0,
      GIR_ConstrainSelectedInstOperands, /*InsnID*/0,
      GIR_EraseFromParent, /*InsnID*/0,
      // GIR_Coverage, 2595,
      GIR_Done,
    // Label 1555: @103124
    GIM_Try, /*On fail goto*//*Label 1556*/ GIMT_Encode4(103189), // Rule ID 2596 //
      GIM_CheckFeatures, GIMT_Encode2(GIFBS_isNotGFX9Plus),
      GIM_CheckMemorySizeEqualToLLT, /*MI*/0, /*MMO*/0, /*OpIdx*/0,
      GIM_CheckAtomicOrdering, /*MI*/0, /*Order*/(uint8_t)AtomicOrdering::NotAtomic,
      GIM_CheckRegBankForClass, /*MI*/0, /*Op*/0, /*RC*/GIMT_Encode2(AMDGPU::SReg_128RegClassID),
      GIM_CheckPointerToAny, /*MI*/0, /*Op*/1, /*SizeInBits*/0,
      GIM_CheckCxxInsnPredicate, /*MI*/0, /*FnId*/GIMT_Encode2(GICXXPred_MI_Predicate_smrd_load),
      GIM_CheckComplexPattern, /*MI*/0, /*Op*/1, /*Renderer*/GIMT_Encode2(0), GIMT_Encode2(GICP_gi_smrd_sgpr),
      // (ld:{ *:[v8bf16] } (SMRDSgpr:{ *:[iPTR] } i64:{ *:[i64] }:$sbase, i32:{ *:[i32] }:$soffset))<<P:Predicate_unindexedload>><<P:Predicate_load>><<P:Predicate_smrd_load>>  =>  (S_LOAD_DWORDX4_SGPR:{ *:[v8bf16] } ?:{ *:[i64] }:$sbase, ?:{ *:[i32] }:$soffset, 0:{ *:[i32] })
      GIR_BuildMI, /*InsnID*/0, /*Opcode*/GIMT_Encode2(AMDGPU::S_LOAD_DWORDX4_SGPR),
      GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/0, // DstI[sdst]
      GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/0, // sbase
      GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/1, // soffset
      GIR_AddImm8, /*InsnID*/0, /*Imm*/0,
      GIR_MergeMemOperands, /*InsnID*/0, /*NumInsns*/1, /*MergeInsnID's*/0,
      GIR_ConstrainSelectedInstOperands, /*InsnID*/0,
      GIR_EraseFromParent, /*InsnID*/0,
      // GIR_Coverage, 2596,
      GIR_Done,
    // Label 1556: @103189
    GIM_Try, /*On fail goto*//*Label 1557*/ GIMT_Encode4(103257), // Rule ID 2597 //
      GIM_CheckFeatures, GIMT_Encode2(GIFBS_isGFX9Plus),
      GIM_CheckMemorySizeEqualToLLT, /*MI*/0, /*MMO*/0, /*OpIdx*/0,
      GIM_CheckAtomicOrdering, /*MI*/0, /*Order*/(uint8_t)AtomicOrdering::NotAtomic,
      GIM_CheckRegBankForClass, /*MI*/0, /*Op*/0, /*RC*/GIMT_Encode2(AMDGPU::SReg_128RegClassID),
      GIM_CheckPointerToAny, /*MI*/0, /*Op*/1, /*SizeInBits*/0,
      GIM_CheckCxxInsnPredicate, /*MI*/0, /*FnId*/GIMT_Encode2(GICXXPred_MI_Predicate_smrd_load),
      GIM_CheckComplexPattern, /*MI*/0, /*Op*/1, /*Renderer*/GIMT_Encode2(0), GIMT_Encode2(GICP_gi_smrd_sgpr),
      // (ld:{ *:[v8bf16] } (SMRDSgpr:{ *:[iPTR] } i64:{ *:[i64] }:$sbase, i32:{ *:[i32] }:$soffset))<<P:Predicate_unindexedload>><<P:Predicate_load>><<P:Predicate_smrd_load>>  =>  (S_LOAD_DWORDX4_SGPR_IMM:{ *:[v8bf16] } ?:{ *:[i64] }:$sbase, ?:{ *:[i32] }:$soffset, 0:{ *:[i32] }, 0:{ *:[i32] })
      GIR_BuildMI, /*InsnID*/0, /*Opcode*/GIMT_Encode2(AMDGPU::S_LOAD_DWORDX4_SGPR_IMM),
      GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/0, // DstI[sdst]
      GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/0, // sbase
      GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/1, // soffset
      GIR_AddImm8, /*InsnID*/0, /*Imm*/0,
      GIR_AddImm8, /*InsnID*/0, /*Imm*/0,
      GIR_MergeMemOperands, /*InsnID*/0, /*NumInsns*/1, /*MergeInsnID's*/0,
      GIR_ConstrainSelectedInstOperands, /*InsnID*/0,
      GIR_EraseFromParent, /*InsnID*/0,
      // GIR_Coverage, 2597,
      GIR_Done,
    // Label 1557: @103257
    GIM_Try, /*On fail goto*//*Label 1558*/ GIMT_Encode4(103328), // Rule ID 6880 //
      GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasUnalignedAccessMode_NotLDSRequiresM0Init),
      GIM_CheckMemoryAddressSpace, /*MI*/0, /*MMO*/0, /*NumAddrSpace*/1, /*AddrSpace*/3,
      GIM_CheckMemoryAddressSpace, /*MI*/0, /*MMO*/0, /*NumAddrSpace*/1, /*AddrSpace*/3,
      GIM_CheckAtomicOrdering, /*MI*/0, /*Order*/(uint8_t)AtomicOrdering::NotAtomic,
      GIM_CheckRegBankForClass, /*MI*/0, /*Op*/0, /*RC*/GIMT_Encode2(AMDGPU::AV_128RegClassID),
      GIM_CheckPointerToAny, /*MI*/0, /*Op*/1, /*SizeInBits*/0,
      GIM_CheckCxxInsnPredicate, /*MI*/0, /*FnId*/GIMT_Encode2(GICXXPred_MI_Predicate_load_align_less_than_4_local),
      GIM_CheckComplexPattern, /*MI*/0, /*Op*/1, /*Renderer*/GIMT_Encode2(0), GIMT_Encode2(GICP_gi_ds_1addr_1offset),
      // (ld:{ *:[v8i16] } (DS1Addr1Offset:{ *:[iPTR] } i32:{ *:[i32] }:$ptr, i32:{ *:[i32] }:$offset))<<P:Predicate_unindexedload>><<P:Predicate_load_local>><<P:Predicate_load_align_less_than_4_local>>  =>  (DS_READ_B128_gfx9:{ *:[v8i16] } ?:{ *:[i32] }:$ptr, offset:{ *:[i32] }:$offset, 0:{ *:[i1] })
      GIR_BuildMI, /*InsnID*/0, /*Opcode*/GIMT_Encode2(AMDGPU::DS_READ_B128_gfx9),
      GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/0, // DstI[vdst]
      GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/0, // ptr
      GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/1, // offset
      GIR_AddImm8, /*InsnID*/0, /*Imm*/0,
      GIR_MergeMemOperands, /*InsnID*/0, /*NumInsns*/1, /*MergeInsnID's*/0,
      GIR_ConstrainSelectedInstOperands, /*InsnID*/0,
      GIR_EraseFromParent, /*InsnID*/0,
      // GIR_Coverage, 6880,
      GIR_Done,
    // Label 1558: @103328
    GIM_Try, /*On fail goto*//*Label 1559*/ GIMT_Encode4(103399), // Rule ID 6884 //
      GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasUnalignedAccessMode_NotLDSRequiresM0Init),
      GIM_CheckMemoryAddressSpace, /*MI*/0, /*MMO*/0, /*NumAddrSpace*/1, /*AddrSpace*/3,
      GIM_CheckMemoryAddressSpace, /*MI*/0, /*MMO*/0, /*NumAddrSpace*/1, /*AddrSpace*/3,
      GIM_CheckAtomicOrdering, /*MI*/0, /*Order*/(uint8_t)AtomicOrdering::NotAtomic,
      GIM_CheckRegBankForClass, /*MI*/0, /*Op*/0, /*RC*/GIMT_Encode2(AMDGPU::AV_128RegClassID),
      GIM_CheckPointerToAny, /*MI*/0, /*Op*/1, /*SizeInBits*/0,
      GIM_CheckCxxInsnPredicate, /*MI*/0, /*FnId*/GIMT_Encode2(GICXXPred_MI_Predicate_load_align_less_than_4_local),
      GIM_CheckComplexPattern, /*MI*/0, /*Op*/1, /*Renderer*/GIMT_Encode2(0), GIMT_Encode2(GICP_gi_ds_1addr_1offset),
      // (ld:{ *:[v8f16] } (DS1Addr1Offset:{ *:[iPTR] } i32:{ *:[i32] }:$ptr, i32:{ *:[i32] }:$offset))<<P:Predicate_unindexedload>><<P:Predicate_load_local>><<P:Predicate_load_align_less_than_4_local>>  =>  (DS_READ_B128_gfx9:{ *:[v8f16] } ?:{ *:[i32] }:$ptr, offset:{ *:[i32] }:$offset, 0:{ *:[i1] })
      GIR_BuildMI, /*InsnID*/0, /*Opcode*/GIMT_Encode2(AMDGPU::DS_READ_B128_gfx9),
      GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/0, // DstI[vdst]
      GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/0, // ptr
      GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/1, // offset
      GIR_AddImm8, /*InsnID*/0, /*Imm*/0,
      GIR_MergeMemOperands, /*InsnID*/0, /*NumInsns*/1, /*MergeInsnID's*/0,
      GIR_ConstrainSelectedInstOperands, /*InsnID*/0,
      GIR_EraseFromParent, /*InsnID*/0,
      // GIR_Coverage, 6884,
      GIR_Done,
    // Label 1559: @103399
    GIM_Try, /*On fail goto*//*Label 1560*/ GIMT_Encode4(103470), // Rule ID 6888 //
      GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasUnalignedAccessMode_NotLDSRequiresM0Init),
      GIM_CheckMemoryAddressSpace, /*MI*/0, /*MMO*/0, /*NumAddrSpace*/1, /*AddrSpace*/3,
      GIM_CheckMemoryAddressSpace, /*MI*/0, /*MMO*/0, /*NumAddrSpace*/1, /*AddrSpace*/3,
      GIM_CheckAtomicOrdering, /*MI*/0, /*Order*/(uint8_t)AtomicOrdering::NotAtomic,
      GIM_CheckRegBankForClass, /*MI*/0, /*Op*/0, /*RC*/GIMT_Encode2(AMDGPU::AV_128RegClassID),
      GIM_CheckPointerToAny, /*MI*/0, /*Op*/1, /*SizeInBits*/0,
      GIM_CheckCxxInsnPredicate, /*MI*/0, /*FnId*/GIMT_Encode2(GICXXPred_MI_Predicate_load_align_less_than_4_local),
      GIM_CheckComplexPattern, /*MI*/0, /*Op*/1, /*Renderer*/GIMT_Encode2(0), GIMT_Encode2(GICP_gi_ds_1addr_1offset),
      // (ld:{ *:[v8bf16] } (DS1Addr1Offset:{ *:[iPTR] } i32:{ *:[i32] }:$ptr, i32:{ *:[i32] }:$offset))<<P:Predicate_unindexedload>><<P:Predicate_load_local>><<P:Predicate_load_align_less_than_4_local>>  =>  (DS_READ_B128_gfx9:{ *:[v8bf16] } ?:{ *:[i32] }:$ptr, offset:{ *:[i32] }:$offset, 0:{ *:[i1] })
      GIR_BuildMI, /*InsnID*/0, /*Opcode*/GIMT_Encode2(AMDGPU::DS_READ_B128_gfx9),
      GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/0, // DstI[vdst]
      GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/0, // ptr
      GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/1, // offset
      GIR_AddImm8, /*InsnID*/0, /*Imm*/0,
      GIR_MergeMemOperands, /*InsnID*/0, /*NumInsns*/1, /*MergeInsnID's*/0,
      GIR_ConstrainSelectedInstOperands, /*InsnID*/0,
      GIR_EraseFromParent, /*InsnID*/0,
      // GIR_Coverage, 6888,
      GIR_Done,
    // Label 1560: @103470
    GIM_Try, /*On fail goto*//*Label 1561*/ GIMT_Encode4(103536), // Rule ID 6804 //
      GIM_CheckFeatures, GIMT_Encode2(GIFBS_NotLDSRequiresM0Init_isGFX7Plus),
      GIM_CheckMemoryAddressSpace, /*MI*/0, /*MMO*/0, /*NumAddrSpace*/1, /*AddrSpace*/3,
      GIM_CheckMemoryAlignment, /*MI*/0, /*MMO*/0, /*MinAlign*/16,
      GIM_CheckAtomicOrdering, /*MI*/0, /*Order*/(uint8_t)AtomicOrdering::NotAtomic,
      GIM_CheckRegBankForClass, /*MI*/0, /*Op*/0, /*RC*/GIMT_Encode2(AMDGPU::AV_128RegClassID),
      GIM_CheckPointerToAny, /*MI*/0, /*Op*/1, /*SizeInBits*/0,
      GIM_CheckComplexPattern, /*MI*/0, /*Op*/1, /*Renderer*/GIMT_Encode2(0), GIMT_Encode2(GICP_gi_ds_1addr_1offset),
      // (ld:{ *:[v8i16] } (DS1Addr1Offset:{ *:[iPTR] } i32:{ *:[i32] }:$ptr, i32:{ *:[i32] }:$offset))<<P:Predicate_unindexedload>><<P:Predicate_load_local>><<P:Predicate_load_align16_local>>  =>  (DS_READ_B128_gfx9:{ *:[v8i16] } ?:{ *:[i32] }:$ptr, offset:{ *:[i32] }:$offset, 0:{ *:[i1] })
      GIR_BuildMI, /*InsnID*/0, /*Opcode*/GIMT_Encode2(AMDGPU::DS_READ_B128_gfx9),
      GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/0, // DstI[vdst]
      GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/0, // ptr
      GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/1, // offset
      GIR_AddImm8, /*InsnID*/0, /*Imm*/0,
      GIR_MergeMemOperands, /*InsnID*/0, /*NumInsns*/1, /*MergeInsnID's*/0,
      GIR_ConstrainSelectedInstOperands, /*InsnID*/0,
      GIR_EraseFromParent, /*InsnID*/0,
      // GIR_Coverage, 6804,
      GIR_Done,
    // Label 1561: @103536
    GIM_Try, /*On fail goto*//*Label 1562*/ GIMT_Encode4(103602), // Rule ID 6808 //
      GIM_CheckFeatures, GIMT_Encode2(GIFBS_NotLDSRequiresM0Init_isGFX7Plus),
      GIM_CheckMemoryAddressSpace, /*MI*/0, /*MMO*/0, /*NumAddrSpace*/1, /*AddrSpace*/3,
      GIM_CheckMemoryAlignment, /*MI*/0, /*MMO*/0, /*MinAlign*/16,
      GIM_CheckAtomicOrdering, /*MI*/0, /*Order*/(uint8_t)AtomicOrdering::NotAtomic,
      GIM_CheckRegBankForClass, /*MI*/0, /*Op*/0, /*RC*/GIMT_Encode2(AMDGPU::AV_128RegClassID),
      GIM_CheckPointerToAny, /*MI*/0, /*Op*/1, /*SizeInBits*/0,
      GIM_CheckComplexPattern, /*MI*/0, /*Op*/1, /*Renderer*/GIMT_Encode2(0), GIMT_Encode2(GICP_gi_ds_1addr_1offset),
      // (ld:{ *:[v8f16] } (DS1Addr1Offset:{ *:[iPTR] } i32:{ *:[i32] }:$ptr, i32:{ *:[i32] }:$offset))<<P:Predicate_unindexedload>><<P:Predicate_load_local>><<P:Predicate_load_align16_local>>  =>  (DS_READ_B128_gfx9:{ *:[v8f16] } ?:{ *:[i32] }:$ptr, offset:{ *:[i32] }:$offset, 0:{ *:[i1] })
      GIR_BuildMI, /*InsnID*/0, /*Opcode*/GIMT_Encode2(AMDGPU::DS_READ_B128_gfx9),
      GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/0, // DstI[vdst]
      GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/0, // ptr
      GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/1, // offset
      GIR_AddImm8, /*InsnID*/0, /*Imm*/0,
      GIR_MergeMemOperands, /*InsnID*/0, /*NumInsns*/1, /*MergeInsnID's*/0,
      GIR_ConstrainSelectedInstOperands, /*InsnID*/0,
      GIR_EraseFromParent, /*InsnID*/0,
      // GIR_Coverage, 6808,
      GIR_Done,
    // Label 1562: @103602
    GIM_Try, /*On fail goto*//*Label 1563*/ GIMT_Encode4(103668), // Rule ID 6812 //
      GIM_CheckFeatures, GIMT_Encode2(GIFBS_NotLDSRequiresM0Init_isGFX7Plus),
      GIM_CheckMemoryAddressSpace, /*MI*/0, /*MMO*/0, /*NumAddrSpace*/1, /*AddrSpace*/3,
      GIM_CheckMemoryAlignment, /*MI*/0, /*MMO*/0, /*MinAlign*/16,
      GIM_CheckAtomicOrdering, /*MI*/0, /*Order*/(uint8_t)AtomicOrdering::NotAtomic,
      GIM_CheckRegBankForClass, /*MI*/0, /*Op*/0, /*RC*/GIMT_Encode2(AMDGPU::AV_128RegClassID),
      GIM_CheckPointerToAny, /*MI*/0, /*Op*/1, /*SizeInBits*/0,
      GIM_CheckComplexPattern, /*MI*/0, /*Op*/1, /*Renderer*/GIMT_Encode2(0), GIMT_Encode2(GICP_gi_ds_1addr_1offset),
      // (ld:{ *:[v8bf16] } (DS1Addr1Offset:{ *:[iPTR] } i32:{ *:[i32] }:$ptr, i32:{ *:[i32] }:$offset))<<P:Predicate_unindexedload>><<P:Predicate_load_local>><<P:Predicate_load_align16_local>>  =>  (DS_READ_B128_gfx9:{ *:[v8bf16] } ?:{ *:[i32] }:$ptr, offset:{ *:[i32] }:$offset, 0:{ *:[i1] })
      GIR_BuildMI, /*InsnID*/0, /*Opcode*/GIMT_Encode2(AMDGPU::DS_READ_B128_gfx9),
      GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/0, // DstI[vdst]
      GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/0, // ptr
      GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/1, // offset
      GIR_AddImm8, /*InsnID*/0, /*Imm*/0,
      GIR_MergeMemOperands, /*InsnID*/0, /*NumInsns*/1, /*MergeInsnID's*/0,
      GIR_ConstrainSelectedInstOperands, /*InsnID*/0,
      GIR_EraseFromParent, /*InsnID*/0,
      // GIR_Coverage, 6812,
      GIR_Done,
    // Label 1563: @103668
    GIM_Try, /*On fail goto*//*Label 1564*/ GIMT_Encode4(103725), // Rule ID 2587 //
      GIM_CheckMemorySizeEqualToLLT, /*MI*/0, /*MMO*/0, /*OpIdx*/0,
      GIM_CheckAtomicOrdering, /*MI*/0, /*Order*/(uint8_t)AtomicOrdering::NotAtomic,
      GIM_CheckRegBankForClass, /*MI*/0, /*Op*/0, /*RC*/GIMT_Encode2(AMDGPU::SReg_128RegClassID),
      // MIs[0] sbase
      GIM_CheckPointerToAny, /*MI*/0, /*Op*/1, /*SizeInBits*/64,
      GIM_CheckRegBankForClass, /*MI*/0, /*Op*/1, /*RC*/GIMT_Encode2(AMDGPU::SReg_64RegClassID),
      GIM_CheckCxxInsnPredicate, /*MI*/0, /*FnId*/GIMT_Encode2(GICXXPred_MI_Predicate_smrd_load),
      // (ld:{ *:[v8i16] } SReg_64:{ *:[i64] }:$sbase)<<P:Predicate_unindexedload>><<P:Predicate_load>><<P:Predicate_smrd_load>>  =>  (S_LOAD_DWORDX4_IMM:{ *:[v8i16] } i64:{ *:[i64] }:$sbase, 0:{ *:[i32] }, 0:{ *:[i32] })
      GIR_BuildMI, /*InsnID*/0, /*Opcode*/GIMT_Encode2(AMDGPU::S_LOAD_DWORDX4_IMM),
      GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/0, // DstI[sdst]
      GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/1, // sbase
      GIR_AddImm8, /*InsnID*/0, /*Imm*/0,
      GIR_AddImm8, /*InsnID*/0, /*Imm*/0,
      GIR_MergeMemOperands, /*InsnID*/0, /*NumInsns*/1, /*MergeInsnID's*/0,
      GIR_ConstrainSelectedInstOperands, /*InsnID*/0,
      GIR_EraseFromParent, /*InsnID*/0,
      // GIR_Coverage, 2587,
      GIR_Done,
    // Label 1564: @103725
    GIM_Try, /*On fail goto*//*Label 1565*/ GIMT_Encode4(103782), // Rule ID 2593 //
      GIM_CheckMemorySizeEqualToLLT, /*MI*/0, /*MMO*/0, /*OpIdx*/0,
      GIM_CheckAtomicOrdering, /*MI*/0, /*Order*/(uint8_t)AtomicOrdering::NotAtomic,
      GIM_CheckRegBankForClass, /*MI*/0, /*Op*/0, /*RC*/GIMT_Encode2(AMDGPU::SReg_128RegClassID),
      // MIs[0] sbase
      GIM_CheckPointerToAny, /*MI*/0, /*Op*/1, /*SizeInBits*/64,
      GIM_CheckRegBankForClass, /*MI*/0, /*Op*/1, /*RC*/GIMT_Encode2(AMDGPU::SReg_64RegClassID),
      GIM_CheckCxxInsnPredicate, /*MI*/0, /*FnId*/GIMT_Encode2(GICXXPred_MI_Predicate_smrd_load),
      // (ld:{ *:[v8f16] } SReg_64:{ *:[i64] }:$sbase)<<P:Predicate_unindexedload>><<P:Predicate_load>><<P:Predicate_smrd_load>>  =>  (S_LOAD_DWORDX4_IMM:{ *:[v8f16] } i64:{ *:[i64] }:$sbase, 0:{ *:[i32] }, 0:{ *:[i32] })
      GIR_BuildMI, /*InsnID*/0, /*Opcode*/GIMT_Encode2(AMDGPU::S_LOAD_DWORDX4_IMM),
      GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/0, // DstI[sdst]
      GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/1, // sbase
      GIR_AddImm8, /*InsnID*/0, /*Imm*/0,
      GIR_AddImm8, /*InsnID*/0, /*Imm*/0,
      GIR_MergeMemOperands, /*InsnID*/0, /*NumInsns*/1, /*MergeInsnID's*/0,
      GIR_ConstrainSelectedInstOperands, /*InsnID*/0,
      GIR_EraseFromParent, /*InsnID*/0,
      // GIR_Coverage, 2593,
      GIR_Done,
    // Label 1565: @103782
    GIM_Try, /*On fail goto*//*Label 1566*/ GIMT_Encode4(103839), // Rule ID 2599 //
      GIM_CheckMemorySizeEqualToLLT, /*MI*/0, /*MMO*/0, /*OpIdx*/0,
      GIM_CheckAtomicOrdering, /*MI*/0, /*Order*/(uint8_t)AtomicOrdering::NotAtomic,
      GIM_CheckRegBankForClass, /*MI*/0, /*Op*/0, /*RC*/GIMT_Encode2(AMDGPU::SReg_128RegClassID),
      // MIs[0] sbase
      GIM_CheckPointerToAny, /*MI*/0, /*Op*/1, /*SizeInBits*/64,
      GIM_CheckRegBankForClass, /*MI*/0, /*Op*/1, /*RC*/GIMT_Encode2(AMDGPU::SReg_64RegClassID),
      GIM_CheckCxxInsnPredicate, /*MI*/0, /*FnId*/GIMT_Encode2(GICXXPred_MI_Predicate_smrd_load),
      // (ld:{ *:[v8bf16] } SReg_64:{ *:[i64] }:$sbase)<<P:Predicate_unindexedload>><<P:Predicate_load>><<P:Predicate_smrd_load>>  =>  (S_LOAD_DWORDX4_IMM:{ *:[v8bf16] } i64:{ *:[i64] }:$sbase, 0:{ *:[i32] }, 0:{ *:[i32] })
      GIR_BuildMI, /*InsnID*/0, /*Opcode*/GIMT_Encode2(AMDGPU::S_LOAD_DWORDX4_IMM),
      GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/0, // DstI[sdst]
      GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/1, // sbase
      GIR_AddImm8, /*InsnID*/0, /*Imm*/0,
      GIR_AddImm8, /*InsnID*/0, /*Imm*/0,
      GIR_MergeMemOperands, /*InsnID*/0, /*NumInsns*/1, /*MergeInsnID's*/0,
      GIR_ConstrainSelectedInstOperands, /*InsnID*/0,
      GIR_EraseFromParent, /*InsnID*/0,
      // GIR_Coverage, 2599,
      GIR_Done,
    // Label 1566: @103839
    GIM_Try, /*On fail goto*//*Label 1567*/ GIMT_Encode4(103906), // Rule ID 3571 //
      GIM_CheckFeatures, GIMT_Encode2(GIFBS_EnableFlatScratch_HasFlatScratchInsts_HasFlatScratchSVSMode),
      GIM_CheckMemoryAddressSpace, /*MI*/0, /*MMO*/0, /*NumAddrSpace*/1, /*AddrSpace*/5,
      GIM_CheckAtomicOrdering, /*MI*/0, /*Order*/(uint8_t)AtomicOrdering::NotAtomic,
      GIM_CheckRegBankForClass, /*MI*/0, /*Op*/0, /*RC*/GIMT_Encode2(AMDGPU::AV_128RegClassID),
      GIM_CheckPointerToAny, /*MI*/0, /*Op*/1, /*SizeInBits*/0,
      GIM_CheckComplexPattern, /*MI*/0, /*Op*/1, /*Renderer*/GIMT_Encode2(0), GIMT_Encode2(GICP_gi_flat_scratch_svaddr),
      // (ld:{ *:[v8i16] } (ScratchSVAddr:{ *:[iPTR] } VGPR_32:{ *:[i32] }:$vaddr, SGPR_32:{ *:[i32] }:$saddr, i32:{ *:[i32] }:$offset))<<P:Predicate_unindexedload>><<P:Predicate_load_private>>  =>  (SCRATCH_LOAD_DWORDX4_SVS:{ *:[v8i16] } ?:{ *:[i32] }:$vaddr, ?:{ *:[i32] }:$saddr, ?:{ *:[i32] }:$offset, 0:{ *:[i32] })
      GIR_BuildMI, /*InsnID*/0, /*Opcode*/GIMT_Encode2(AMDGPU::SCRATCH_LOAD_DWORDX4_SVS),
      GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/0, // DstI[vdst]
      GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/0, // vaddr
      GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/1, // saddr
      GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/2, // offset
      GIR_AddImm8, /*InsnID*/0, /*Imm*/0,
      GIR_MergeMemOperands, /*InsnID*/0, /*NumInsns*/1, /*MergeInsnID's*/0,
      GIR_ConstrainSelectedInstOperands, /*InsnID*/0,
      GIR_EraseFromParent, /*InsnID*/0,
      // GIR_Coverage, 3571,
      GIR_Done,
    // Label 1567: @103906
    GIM_Try, /*On fail goto*//*Label 1568*/ GIMT_Encode4(103973), // Rule ID 3577 //
      GIM_CheckFeatures, GIMT_Encode2(GIFBS_EnableFlatScratch_HasFlatScratchInsts_HasFlatScratchSVSMode),
      GIM_CheckMemoryAddressSpace, /*MI*/0, /*MMO*/0, /*NumAddrSpace*/1, /*AddrSpace*/5,
      GIM_CheckAtomicOrdering, /*MI*/0, /*Order*/(uint8_t)AtomicOrdering::NotAtomic,
      GIM_CheckRegBankForClass, /*MI*/0, /*Op*/0, /*RC*/GIMT_Encode2(AMDGPU::AV_128RegClassID),
      GIM_CheckPointerToAny, /*MI*/0, /*Op*/1, /*SizeInBits*/0,
      GIM_CheckComplexPattern, /*MI*/0, /*Op*/1, /*Renderer*/GIMT_Encode2(0), GIMT_Encode2(GICP_gi_flat_scratch_svaddr),
      // (ld:{ *:[v8f16] } (ScratchSVAddr:{ *:[iPTR] } VGPR_32:{ *:[i32] }:$vaddr, SGPR_32:{ *:[i32] }:$saddr, i32:{ *:[i32] }:$offset))<<P:Predicate_unindexedload>><<P:Predicate_load_private>>  =>  (SCRATCH_LOAD_DWORDX4_SVS:{ *:[v8f16] } ?:{ *:[i32] }:$vaddr, ?:{ *:[i32] }:$saddr, ?:{ *:[i32] }:$offset, 0:{ *:[i32] })
      GIR_BuildMI, /*InsnID*/0, /*Opcode*/GIMT_Encode2(AMDGPU::SCRATCH_LOAD_DWORDX4_SVS),
      GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/0, // DstI[vdst]
      GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/0, // vaddr
      GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/1, // saddr
      GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/2, // offset
      GIR_AddImm8, /*InsnID*/0, /*Imm*/0,
      GIR_MergeMemOperands, /*InsnID*/0, /*NumInsns*/1, /*MergeInsnID's*/0,
      GIR_ConstrainSelectedInstOperands, /*InsnID*/0,
      GIR_EraseFromParent, /*InsnID*/0,
      // GIR_Coverage, 3577,
      GIR_Done,
    // Label 1568: @103973
    GIM_Try, /*On fail goto*//*Label 1569*/ GIMT_Encode4(104040), // Rule ID 3583 //
      GIM_CheckFeatures, GIMT_Encode2(GIFBS_EnableFlatScratch_HasFlatScratchInsts_HasFlatScratchSVSMode),
      GIM_CheckMemoryAddressSpace, /*MI*/0, /*MMO*/0, /*NumAddrSpace*/1, /*AddrSpace*/5,
      GIM_CheckAtomicOrdering, /*MI*/0, /*Order*/(uint8_t)AtomicOrdering::NotAtomic,
      GIM_CheckRegBankForClass, /*MI*/0, /*Op*/0, /*RC*/GIMT_Encode2(AMDGPU::AV_128RegClassID),
      GIM_CheckPointerToAny, /*MI*/0, /*Op*/1, /*SizeInBits*/0,
      GIM_CheckComplexPattern, /*MI*/0, /*Op*/1, /*Renderer*/GIMT_Encode2(0), GIMT_Encode2(GICP_gi_flat_scratch_svaddr),
      // (ld:{ *:[v8bf16] } (ScratchSVAddr:{ *:[iPTR] } VGPR_32:{ *:[i32] }:$vaddr, SGPR_32:{ *:[i32] }:$saddr, i32:{ *:[i32] }:$offset))<<P:Predicate_unindexedload>><<P:Predicate_load_private>>  =>  (SCRATCH_LOAD_DWORDX4_SVS:{ *:[v8bf16] } ?:{ *:[i32] }:$vaddr, ?:{ *:[i32] }:$saddr, ?:{ *:[i32] }:$offset, 0:{ *:[i32] })
      GIR_BuildMI, /*InsnID*/0, /*Opcode*/GIMT_Encode2(AMDGPU::SCRATCH_LOAD_DWORDX4_SVS),
      GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/0, // DstI[vdst]
      GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/0, // vaddr
      GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/1, // saddr
      GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/2, // offset
      GIR_AddImm8, /*InsnID*/0, /*Imm*/0,
      GIR_MergeMemOperands, /*InsnID*/0, /*NumInsns*/1, /*MergeInsnID's*/0,
      GIR_ConstrainSelectedInstOperands, /*InsnID*/0,
      GIR_EraseFromParent, /*InsnID*/0,
      // GIR_Coverage, 3583,
      GIR_Done,
    // Label 1569: @104040
    GIM_Try, /*On fail goto*//*Label 1570*/ GIMT_Encode4(104102), // Rule ID 3570 //
      GIM_CheckFeatures, GIMT_Encode2(GIFBS_EnableFlatScratch_HasFlatScratchInsts),
      GIM_CheckMemoryAddressSpace, /*MI*/0, /*MMO*/0, /*NumAddrSpace*/1, /*AddrSpace*/5,
      GIM_CheckAtomicOrdering, /*MI*/0, /*Order*/(uint8_t)AtomicOrdering::NotAtomic,
      GIM_CheckRegBankForClass, /*MI*/0, /*Op*/0, /*RC*/GIMT_Encode2(AMDGPU::AV_128RegClassID),
      GIM_CheckPointerToAny, /*MI*/0, /*Op*/1, /*SizeInBits*/0,
      GIM_CheckComplexPattern, /*MI*/0, /*Op*/1, /*Renderer*/GIMT_Encode2(0), GIMT_Encode2(GICP_gi_flat_scratch_saddr),
      // (ld:{ *:[v8i16] } (ScratchSAddr:{ *:[iPTR] } SGPR_32:{ *:[i32] }:$saddr, i32:{ *:[i32] }:$offset))<<P:Predicate_unindexedload>><<P:Predicate_load_private>>  =>  (SCRATCH_LOAD_DWORDX4_SADDR:{ *:[v8i16] } ?:{ *:[i32] }:$saddr, ?:{ *:[i32] }:$offset)
      GIR_BuildMI, /*InsnID*/0, /*Opcode*/GIMT_Encode2(AMDGPU::SCRATCH_LOAD_DWORDX4_SADDR),
      GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/0, // DstI[vdst]
      GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/0, // saddr
      GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/1, // offset
      GIR_AddImm8, /*InsnID*/0, /*Imm*/0,
      GIR_MergeMemOperands, /*InsnID*/0, /*NumInsns*/1, /*MergeInsnID's*/0,
      GIR_ConstrainSelectedInstOperands, /*InsnID*/0,
      GIR_EraseFromParent, /*InsnID*/0,
      // GIR_Coverage, 3570,
      GIR_Done,
    // Label 1570: @104102
    GIM_Try, /*On fail goto*//*Label 1571*/ GIMT_Encode4(104164), // Rule ID 3576 //
      GIM_CheckFeatures, GIMT_Encode2(GIFBS_EnableFlatScratch_HasFlatScratchInsts),
      GIM_CheckMemoryAddressSpace, /*MI*/0, /*MMO*/0, /*NumAddrSpace*/1, /*AddrSpace*/5,
      GIM_CheckAtomicOrdering, /*MI*/0, /*Order*/(uint8_t)AtomicOrdering::NotAtomic,
      GIM_CheckRegBankForClass, /*MI*/0, /*Op*/0, /*RC*/GIMT_Encode2(AMDGPU::AV_128RegClassID),
      GIM_CheckPointerToAny, /*MI*/0, /*Op*/1, /*SizeInBits*/0,
      GIM_CheckComplexPattern, /*MI*/0, /*Op*/1, /*Renderer*/GIMT_Encode2(0), GIMT_Encode2(GICP_gi_flat_scratch_saddr),
      // (ld:{ *:[v8f16] } (ScratchSAddr:{ *:[iPTR] } SGPR_32:{ *:[i32] }:$saddr, i32:{ *:[i32] }:$offset))<<P:Predicate_unindexedload>><<P:Predicate_load_private>>  =>  (SCRATCH_LOAD_DWORDX4_SADDR:{ *:[v8f16] } ?:{ *:[i32] }:$saddr, ?:{ *:[i32] }:$offset)
      GIR_BuildMI, /*InsnID*/0, /*Opcode*/GIMT_Encode2(AMDGPU::SCRATCH_LOAD_DWORDX4_SADDR),
      GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/0, // DstI[vdst]
      GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/0, // saddr
      GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/1, // offset
      GIR_AddImm8, /*InsnID*/0, /*Imm*/0,
      GIR_MergeMemOperands, /*InsnID*/0, /*NumInsns*/1, /*MergeInsnID's*/0,
      GIR_ConstrainSelectedInstOperands, /*InsnID*/0,
      GIR_EraseFromParent, /*InsnID*/0,
      // GIR_Coverage, 3576,
      GIR_Done,
    // Label 1571: @104164
    GIM_Try, /*On fail goto*//*Label 1572*/ GIMT_Encode4(104226), // Rule ID 3582 //
      GIM_CheckFeatures, GIMT_Encode2(GIFBS_EnableFlatScratch_HasFlatScratchInsts),
      GIM_CheckMemoryAddressSpace, /*MI*/0, /*MMO*/0, /*NumAddrSpace*/1, /*AddrSpace*/5,
      GIM_CheckAtomicOrdering, /*MI*/0, /*Order*/(uint8_t)AtomicOrdering::NotAtomic,
      GIM_CheckRegBankForClass, /*MI*/0, /*Op*/0, /*RC*/GIMT_Encode2(AMDGPU::AV_128RegClassID),
      GIM_CheckPointerToAny, /*MI*/0, /*Op*/1, /*SizeInBits*/0,
      GIM_CheckComplexPattern, /*MI*/0, /*Op*/1, /*Renderer*/GIMT_Encode2(0), GIMT_Encode2(GICP_gi_flat_scratch_saddr),
      // (ld:{ *:[v8bf16] } (ScratchSAddr:{ *:[iPTR] } SGPR_32:{ *:[i32] }:$saddr, i32:{ *:[i32] }:$offset))<<P:Predicate_unindexedload>><<P:Predicate_load_private>>  =>  (SCRATCH_LOAD_DWORDX4_SADDR:{ *:[v8bf16] } ?:{ *:[i32] }:$saddr, ?:{ *:[i32] }:$offset)
      GIR_BuildMI, /*InsnID*/0, /*Opcode*/GIMT_Encode2(AMDGPU::SCRATCH_LOAD_DWORDX4_SADDR),
      GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/0, // DstI[vdst]
      GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/0, // saddr
      GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/1, // offset
      GIR_AddImm8, /*InsnID*/0, /*Imm*/0,
      GIR_MergeMemOperands, /*InsnID*/0, /*NumInsns*/1, /*MergeInsnID's*/0,
      GIR_ConstrainSelectedInstOperands, /*InsnID*/0,
      GIR_EraseFromParent, /*InsnID*/0,
      // GIR_Coverage, 3582,
      GIR_Done,
    // Label 1572: @104226
    GIM_Try, /*On fail goto*//*Label 1573*/ GIMT_Encode4(104288), // Rule ID 3569 //
      GIM_CheckFeatures, GIMT_Encode2(GIFBS_EnableFlatScratch_HasFlatScratchInsts),
      GIM_CheckMemoryAddressSpace, /*MI*/0, /*MMO*/0, /*NumAddrSpace*/1, /*AddrSpace*/5,
      GIM_CheckAtomicOrdering, /*MI*/0, /*Order*/(uint8_t)AtomicOrdering::NotAtomic,
      GIM_CheckRegBankForClass, /*MI*/0, /*Op*/0, /*RC*/GIMT_Encode2(AMDGPU::AV_128RegClassID),
      GIM_CheckPointerToAny, /*MI*/0, /*Op*/1, /*SizeInBits*/0,
      GIM_CheckComplexPattern, /*MI*/0, /*Op*/1, /*Renderer*/GIMT_Encode2(0), GIMT_Encode2(GICP_gi_flat_scratch_offset),
      // (ld:{ *:[v8i16] } (ScratchOffset:{ *:[iPTR] } VGPR_32:{ *:[i32] }:$vaddr, i32:{ *:[i32] }:$offset))<<P:Predicate_unindexedload>><<P:Predicate_load_private>>  =>  (SCRATCH_LOAD_DWORDX4:{ *:[v8i16] } ?:{ *:[i32] }:$vaddr, ?:{ *:[i32] }:$offset)
      GIR_BuildMI, /*InsnID*/0, /*Opcode*/GIMT_Encode2(AMDGPU::SCRATCH_LOAD_DWORDX4),
      GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/0, // DstI[vdst]
      GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/0, // vaddr
      GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/1, // offset
      GIR_AddImm8, /*InsnID*/0, /*Imm*/0,
      GIR_MergeMemOperands, /*InsnID*/0, /*NumInsns*/1, /*MergeInsnID's*/0,
      GIR_ConstrainSelectedInstOperands, /*InsnID*/0,
      GIR_EraseFromParent, /*InsnID*/0,
      // GIR_Coverage, 3569,
      GIR_Done,
    // Label 1573: @104288
    GIM_Try, /*On fail goto*//*Label 1574*/ GIMT_Encode4(104350), // Rule ID 3575 //
      GIM_CheckFeatures, GIMT_Encode2(GIFBS_EnableFlatScratch_HasFlatScratchInsts),
      GIM_CheckMemoryAddressSpace, /*MI*/0, /*MMO*/0, /*NumAddrSpace*/1, /*AddrSpace*/5,
      GIM_CheckAtomicOrdering, /*MI*/0, /*Order*/(uint8_t)AtomicOrdering::NotAtomic,
      GIM_CheckRegBankForClass, /*MI*/0, /*Op*/0, /*RC*/GIMT_Encode2(AMDGPU::AV_128RegClassID),
      GIM_CheckPointerToAny, /*MI*/0, /*Op*/1, /*SizeInBits*/0,
      GIM_CheckComplexPattern, /*MI*/0, /*Op*/1, /*Renderer*/GIMT_Encode2(0), GIMT_Encode2(GICP_gi_flat_scratch_offset),
      // (ld:{ *:[v8f16] } (ScratchOffset:{ *:[iPTR] } VGPR_32:{ *:[i32] }:$vaddr, i32:{ *:[i32] }:$offset))<<P:Predicate_unindexedload>><<P:Predicate_load_private>>  =>  (SCRATCH_LOAD_DWORDX4:{ *:[v8f16] } ?:{ *:[i32] }:$vaddr, ?:{ *:[i32] }:$offset)
      GIR_BuildMI, /*InsnID*/0, /*Opcode*/GIMT_Encode2(AMDGPU::SCRATCH_LOAD_DWORDX4),
      GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/0, // DstI[vdst]
      GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/0, // vaddr
      GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/1, // offset
      GIR_AddImm8, /*InsnID*/0, /*Imm*/0,
      GIR_MergeMemOperands, /*InsnID*/0, /*NumInsns*/1, /*MergeInsnID's*/0,
      GIR_ConstrainSelectedInstOperands, /*InsnID*/0,
      GIR_EraseFromParent, /*InsnID*/0,
      // GIR_Coverage, 3575,
      GIR_Done,
    // Label 1574: @104350
    GIM_Try, /*On fail goto*//*Label 1575*/ GIMT_Encode4(104412), // Rule ID 3581 //
      GIM_CheckFeatures, GIMT_Encode2(GIFBS_EnableFlatScratch_HasFlatScratchInsts),
      GIM_CheckMemoryAddressSpace, /*MI*/0, /*MMO*/0, /*NumAddrSpace*/1, /*AddrSpace*/5,
      GIM_CheckAtomicOrdering, /*MI*/0, /*Order*/(uint8_t)AtomicOrdering::NotAtomic,
      GIM_CheckRegBankForClass, /*MI*/0, /*Op*/0, /*RC*/GIMT_Encode2(AMDGPU::AV_128RegClassID),
      GIM_CheckPointerToAny, /*MI*/0, /*Op*/1, /*SizeInBits*/0,
      GIM_CheckComplexPattern, /*MI*/0, /*Op*/1, /*Renderer*/GIMT_Encode2(0), GIMT_Encode2(GICP_gi_flat_scratch_offset),
      // (ld:{ *:[v8bf16] } (ScratchOffset:{ *:[iPTR] } VGPR_32:{ *:[i32] }:$vaddr, i32:{ *:[i32] }:$offset))<<P:Predicate_unindexedload>><<P:Predicate_load_private>>  =>  (SCRATCH_LOAD_DWORDX4:{ *:[v8bf16] } ?:{ *:[i32] }:$vaddr, ?:{ *:[i32] }:$offset)
      GIR_BuildMI, /*InsnID*/0, /*Opcode*/GIMT_Encode2(AMDGPU::SCRATCH_LOAD_DWORDX4),
      GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/0, // DstI[vdst]
      GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/0, // vaddr
      GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/1, // offset
      GIR_AddImm8, /*InsnID*/0, /*Imm*/0,
      GIR_MergeMemOperands, /*InsnID*/0, /*NumInsns*/1, /*MergeInsnID's*/0,
      GIR_ConstrainSelectedInstOperands, /*InsnID*/0,
      GIR_EraseFromParent, /*InsnID*/0,
      // GIR_Coverage, 3581,
      GIR_Done,
    // Label 1575: @104412
    GIM_Try, /*On fail goto*//*Label 1576*/ GIMT_Encode4(104489), // Rule ID 3784 //
      GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasUnrestrictedSOffset),
      GIM_CheckMemoryAddressSpace, /*MI*/0, /*MMO*/0, /*NumAddrSpace*/3, /*AddrSpace*/1, /*AddrSpace*/4, /*AddrSpace*/6,
      GIM_CheckAtomicOrdering, /*MI*/0, /*Order*/(uint8_t)AtomicOrdering::NotAtomic,
      GIM_CheckRegBankForClass, /*MI*/0, /*Op*/0, /*RC*/GIMT_Encode2(AMDGPU::AV_128RegClassID),
      GIM_CheckPointerToAny, /*MI*/0, /*Op*/1, /*SizeInBits*/0,
      GIM_CheckComplexPattern, /*MI*/0, /*Op*/1, /*Renderer*/GIMT_Encode2(0), GIMT_Encode2(GICP_gi_mubuf_addr64),
      // (ld:{ *:[v8i16] } (MUBUFAddr64:{ *:[iPTR] } v4i32:{ *:[v4i32] }:$srsrc, i64:{ *:[i64] }:$vaddr, i32:{ *:[i32] }:$soffset, i32:{ *:[i32] }:$offset))<<P:Predicate_unindexedload>><<P:Predicate_load_global>>  =>  (BUFFER_LOAD_DWORDX4_ADDR64:{ *:[v8i16] } i64:{ *:[i64] }:$vaddr, v4i32:{ *:[v4i32] }:$srsrc, i32:{ *:[i32] }:$soffset, i32:{ *:[i32] }:$offset)
      GIR_BuildMI, /*InsnID*/0, /*Opcode*/GIMT_Encode2(AMDGPU::BUFFER_LOAD_DWORDX4_ADDR64),
      GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/0, // DstI[vdata]
      GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/1, // vaddr
      GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/0, // srsrc
      GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/2, // soffset
      GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/3, // offset
      GIR_AddImm8, /*InsnID*/0, /*Imm*/0,
      GIR_AddImm8, /*InsnID*/0, /*Imm*/0,
      GIR_MergeMemOperands, /*InsnID*/0, /*NumInsns*/1, /*MergeInsnID's*/0,
      GIR_ConstrainSelectedInstOperands, /*InsnID*/0,
      GIR_EraseFromParent, /*InsnID*/0,
      // GIR_Coverage, 3784,
      GIR_Done,
    // Label 1576: @104489
    GIM_Try, /*On fail goto*//*Label 1577*/ GIMT_Encode4(104563), // Rule ID 3786 //
      GIM_CheckMemoryAddressSpace, /*MI*/0, /*MMO*/0, /*NumAddrSpace*/3, /*AddrSpace*/1, /*AddrSpace*/4, /*AddrSpace*/6,
      GIM_CheckAtomicOrdering, /*MI*/0, /*Order*/(uint8_t)AtomicOrdering::NotAtomic,
      GIM_CheckRegBankForClass, /*MI*/0, /*Op*/0, /*RC*/GIMT_Encode2(AMDGPU::AV_128RegClassID),
      GIM_CheckPointerToAny, /*MI*/0, /*Op*/1, /*SizeInBits*/0,
      GIM_CheckComplexPattern, /*MI*/0, /*Op*/1, /*Renderer*/GIMT_Encode2(0), GIMT_Encode2(GICP_gi_mubuf_addr64),
      // (ld:{ *:[v8i16] } (MUBUFAddr64:{ *:[iPTR] } v4i32:{ *:[v4i32] }:$srsrc, i64:{ *:[i64] }:$vaddr, i32:{ *:[i32] }:$soffset, i32:{ *:[i32] }:$offset))<<P:Predicate_unindexedload>><<P:Predicate_load_global>>  =>  (BUFFER_LOAD_DWORDX4_VBUFFER_ADDR64:{ *:[v8i16] } i64:{ *:[i64] }:$vaddr, v4i32:{ *:[v4i32] }:$srsrc, i32:{ *:[i32] }:$soffset, i32:{ *:[i32] }:$offset)
      GIR_BuildMI, /*InsnID*/0, /*Opcode*/GIMT_Encode2(AMDGPU::BUFFER_LOAD_DWORDX4_VBUFFER_ADDR64),
      GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/0, // DstI[vdata]
      GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/1, // vaddr
      GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/0, // srsrc
      GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/2, // soffset
      GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/3, // offset
      GIR_AddImm8, /*InsnID*/0, /*Imm*/0,
      GIR_AddImm8, /*InsnID*/0, /*Imm*/0,
      GIR_MergeMemOperands, /*InsnID*/0, /*NumInsns*/1, /*MergeInsnID's*/0,
      GIR_ConstrainSelectedInstOperands, /*InsnID*/0,
      GIR_EraseFromParent, /*InsnID*/0,
      // GIR_Coverage, 3786,
      GIR_Done,
    // Label 1577: @104563
    GIM_Try, /*On fail goto*//*Label 1578*/ GIMT_Encode4(104640), // Rule ID 3788 //
      GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasUnrestrictedSOffset),
      GIM_CheckMemoryAddressSpace, /*MI*/0, /*MMO*/0, /*NumAddrSpace*/3, /*AddrSpace*/1, /*AddrSpace*/4, /*AddrSpace*/6,
      GIM_CheckAtomicOrdering, /*MI*/0, /*Order*/(uint8_t)AtomicOrdering::NotAtomic,
      GIM_CheckRegBankForClass, /*MI*/0, /*Op*/0, /*RC*/GIMT_Encode2(AMDGPU::AV_128RegClassID),
      GIM_CheckPointerToAny, /*MI*/0, /*Op*/1, /*SizeInBits*/0,
      GIM_CheckComplexPattern, /*MI*/0, /*Op*/1, /*Renderer*/GIMT_Encode2(0), GIMT_Encode2(GICP_gi_mubuf_addr64),
      // (ld:{ *:[v8f16] } (MUBUFAddr64:{ *:[iPTR] } v4i32:{ *:[v4i32] }:$srsrc, i64:{ *:[i64] }:$vaddr, i32:{ *:[i32] }:$soffset, i32:{ *:[i32] }:$offset))<<P:Predicate_unindexedload>><<P:Predicate_load_global>>  =>  (BUFFER_LOAD_DWORDX4_ADDR64:{ *:[v8f16] } i64:{ *:[i64] }:$vaddr, v4i32:{ *:[v4i32] }:$srsrc, i32:{ *:[i32] }:$soffset, i32:{ *:[i32] }:$offset)
      GIR_BuildMI, /*InsnID*/0, /*Opcode*/GIMT_Encode2(AMDGPU::BUFFER_LOAD_DWORDX4_ADDR64),
      GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/0, // DstI[vdata]
      GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/1, // vaddr
      GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/0, // srsrc
      GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/2, // soffset
      GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/3, // offset
      GIR_AddImm8, /*InsnID*/0, /*Imm*/0,
      GIR_AddImm8, /*InsnID*/0, /*Imm*/0,
      GIR_MergeMemOperands, /*InsnID*/0, /*NumInsns*/1, /*MergeInsnID's*/0,
      GIR_ConstrainSelectedInstOperands, /*InsnID*/0,
      GIR_EraseFromParent, /*InsnID*/0,
      // GIR_Coverage, 3788,
      GIR_Done,
    // Label 1578: @104640
    GIM_Try, /*On fail goto*//*Label 1579*/ GIMT_Encode4(104714), // Rule ID 3790 //
      GIM_CheckMemoryAddressSpace, /*MI*/0, /*MMO*/0, /*NumAddrSpace*/3, /*AddrSpace*/1, /*AddrSpace*/4, /*AddrSpace*/6,
      GIM_CheckAtomicOrdering, /*MI*/0, /*Order*/(uint8_t)AtomicOrdering::NotAtomic,
      GIM_CheckRegBankForClass, /*MI*/0, /*Op*/0, /*RC*/GIMT_Encode2(AMDGPU::AV_128RegClassID),
      GIM_CheckPointerToAny, /*MI*/0, /*Op*/1, /*SizeInBits*/0,
      GIM_CheckComplexPattern, /*MI*/0, /*Op*/1, /*Renderer*/GIMT_Encode2(0), GIMT_Encode2(GICP_gi_mubuf_addr64),
      // (ld:{ *:[v8f16] } (MUBUFAddr64:{ *:[iPTR] } v4i32:{ *:[v4i32] }:$srsrc, i64:{ *:[i64] }:$vaddr, i32:{ *:[i32] }:$soffset, i32:{ *:[i32] }:$offset))<<P:Predicate_unindexedload>><<P:Predicate_load_global>>  =>  (BUFFER_LOAD_DWORDX4_VBUFFER_ADDR64:{ *:[v8f16] } i64:{ *:[i64] }:$vaddr, v4i32:{ *:[v4i32] }:$srsrc, i32:{ *:[i32] }:$soffset, i32:{ *:[i32] }:$offset)
      GIR_BuildMI, /*InsnID*/0, /*Opcode*/GIMT_Encode2(AMDGPU::BUFFER_LOAD_DWORDX4_VBUFFER_ADDR64),
      GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/0, // DstI[vdata]
      GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/1, // vaddr
      GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/0, // srsrc
      GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/2, // soffset
      GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/3, // offset
      GIR_AddImm8, /*InsnID*/0, /*Imm*/0,
      GIR_AddImm8, /*InsnID*/0, /*Imm*/0,
      GIR_MergeMemOperands, /*InsnID*/0, /*NumInsns*/1, /*MergeInsnID's*/0,
      GIR_ConstrainSelectedInstOperands, /*InsnID*/0,
      GIR_EraseFromParent, /*InsnID*/0,
      // GIR_Coverage, 3790,
      GIR_Done,
    // Label 1579: @104714
    GIM_Try, /*On fail goto*//*Label 1580*/ GIMT_Encode4(104791), // Rule ID 3792 //
      GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasUnrestrictedSOffset),
      GIM_CheckMemoryAddressSpace, /*MI*/0, /*MMO*/0, /*NumAddrSpace*/3, /*AddrSpace*/1, /*AddrSpace*/4, /*AddrSpace*/6,
      GIM_CheckAtomicOrdering, /*MI*/0, /*Order*/(uint8_t)AtomicOrdering::NotAtomic,
      GIM_CheckRegBankForClass, /*MI*/0, /*Op*/0, /*RC*/GIMT_Encode2(AMDGPU::AV_128RegClassID),
      GIM_CheckPointerToAny, /*MI*/0, /*Op*/1, /*SizeInBits*/0,
      GIM_CheckComplexPattern, /*MI*/0, /*Op*/1, /*Renderer*/GIMT_Encode2(0), GIMT_Encode2(GICP_gi_mubuf_addr64),
      // (ld:{ *:[v8bf16] } (MUBUFAddr64:{ *:[iPTR] } v4i32:{ *:[v4i32] }:$srsrc, i64:{ *:[i64] }:$vaddr, i32:{ *:[i32] }:$soffset, i32:{ *:[i32] }:$offset))<<P:Predicate_unindexedload>><<P:Predicate_load_global>>  =>  (BUFFER_LOAD_DWORDX4_ADDR64:{ *:[v8bf16] } i64:{ *:[i64] }:$vaddr, v4i32:{ *:[v4i32] }:$srsrc, i32:{ *:[i32] }:$soffset, i32:{ *:[i32] }:$offset)
      GIR_BuildMI, /*InsnID*/0, /*Opcode*/GIMT_Encode2(AMDGPU::BUFFER_LOAD_DWORDX4_ADDR64),
      GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/0, // DstI[vdata]
      GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/1, // vaddr
      GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/0, // srsrc
      GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/2, // soffset
      GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/3, // offset
      GIR_AddImm8, /*InsnID*/0, /*Imm*/0,
      GIR_AddImm8, /*InsnID*/0, /*Imm*/0,
      GIR_MergeMemOperands, /*InsnID*/0, /*NumInsns*/1, /*MergeInsnID's*/0,
      GIR_ConstrainSelectedInstOperands, /*InsnID*/0,
      GIR_EraseFromParent, /*InsnID*/0,
      // GIR_Coverage, 3792,
      GIR_Done,
    // Label 1580: @104791
    GIM_Try, /*On fail goto*//*Label 1581*/ GIMT_Encode4(104865), // Rule ID 3794 //
      GIM_CheckMemoryAddressSpace, /*MI*/0, /*MMO*/0, /*NumAddrSpace*/3, /*AddrSpace*/1, /*AddrSpace*/4, /*AddrSpace*/6,
      GIM_CheckAtomicOrdering, /*MI*/0, /*Order*/(uint8_t)AtomicOrdering::NotAtomic,
      GIM_CheckRegBankForClass, /*MI*/0, /*Op*/0, /*RC*/GIMT_Encode2(AMDGPU::AV_128RegClassID),
      GIM_CheckPointerToAny, /*MI*/0, /*Op*/1, /*SizeInBits*/0,
      GIM_CheckComplexPattern, /*MI*/0, /*Op*/1, /*Renderer*/GIMT_Encode2(0), GIMT_Encode2(GICP_gi_mubuf_addr64),
      // (ld:{ *:[v8bf16] } (MUBUFAddr64:{ *:[iPTR] } v4i32:{ *:[v4i32] }:$srsrc, i64:{ *:[i64] }:$vaddr, i32:{ *:[i32] }:$soffset, i32:{ *:[i32] }:$offset))<<P:Predicate_unindexedload>><<P:Predicate_load_global>>  =>  (BUFFER_LOAD_DWORDX4_VBUFFER_ADDR64:{ *:[v8bf16] } i64:{ *:[i64] }:$vaddr, v4i32:{ *:[v4i32] }:$srsrc, i32:{ *:[i32] }:$soffset, i32:{ *:[i32] }:$offset)
      GIR_BuildMI, /*InsnID*/0, /*Opcode*/GIMT_Encode2(AMDGPU::BUFFER_LOAD_DWORDX4_VBUFFER_ADDR64),
      GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/0, // DstI[vdata]
      GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/1, // vaddr
      GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/0, // srsrc
      GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/2, // soffset
      GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/3, // offset
      GIR_AddImm8, /*InsnID*/0, /*Imm*/0,
      GIR_AddImm8, /*InsnID*/0, /*Imm*/0,
      GIR_MergeMemOperands, /*InsnID*/0, /*NumInsns*/1, /*MergeInsnID's*/0,
      GIR_ConstrainSelectedInstOperands, /*InsnID*/0,
      GIR_EraseFromParent, /*InsnID*/0,
      // GIR_Coverage, 3794,
      GIR_Done,
    // Label 1581: @104865
    GIM_Try, /*On fail goto*//*Label 1582*/ GIMT_Encode4(104936), // Rule ID 6727 //
      GIM_CheckFeatures, GIMT_Encode2(GIFBS_LDSRequiresM0Init_isGFX7Plus),
      GIM_CheckMemorySizeEqualToLLT, /*MI*/0, /*MMO*/0, /*OpIdx*/0,
      GIM_CheckMemoryAddressSpace, /*MI*/0, /*MMO*/0, /*NumAddrSpace*/1, /*AddrSpace*/3,
      GIM_CheckAtomicOrdering, /*MI*/0, /*Order*/(uint8_t)AtomicOrdering::NotAtomic,
      GIM_CheckRegBankForClass, /*MI*/0, /*Op*/0, /*RC*/GIMT_Encode2(AMDGPU::AV_128RegClassID),
      GIM_CheckPointerToAny, /*MI*/0, /*Op*/1, /*SizeInBits*/0,
      GIM_CheckComplexPattern, /*MI*/0, /*Op*/1, /*Renderer*/GIMT_Encode2(0), GIMT_Encode2(GICP_gi_ds_128bit_8byte_aligned),
      // (AMDGPUld_glue:{ *:[v8i16] } (DS128Bit8ByteAligned:{ *:[iPTR] } i32:{ *:[i32] }:$ptr, i8:{ *:[i8] }:$offset0, i8:{ *:[i8] }:$offset1))<<P:Predicate_unindexedload_glue>><<P:Predicate_load_glue>><<P:Predicate_load_local_m0>>  =>  (DS_READ2_B64:{ *:[v8i16] } ?:{ *:[i32] }:$ptr, ?:{ *:[i8] }:$offset0, ?:{ *:[i8] }:$offset1, 0:{ *:[i1] })
      GIR_BuildMI, /*InsnID*/0, /*Opcode*/GIMT_Encode2(AMDGPU::DS_READ2_B64),
      GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/0, // DstI[vdst]
      GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/0, // ptr
      GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/1, // offset0
      GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/2, // offset1
      GIR_AddImm8, /*InsnID*/0, /*Imm*/0,
      GIR_MergeMemOperands, /*InsnID*/0, /*NumInsns*/1, /*MergeInsnID's*/0,
      GIR_ConstrainSelectedInstOperands, /*InsnID*/0,
      GIR_EraseFromParent, /*InsnID*/0,
      // GIR_Coverage, 6727,
      GIR_Done,
    // Label 1582: @104936
    GIM_Try, /*On fail goto*//*Label 1583*/ GIMT_Encode4(105007), // Rule ID 6731 //
      GIM_CheckFeatures, GIMT_Encode2(GIFBS_LDSRequiresM0Init_isGFX7Plus),
      GIM_CheckMemorySizeEqualToLLT, /*MI*/0, /*MMO*/0, /*OpIdx*/0,
      GIM_CheckMemoryAddressSpace, /*MI*/0, /*MMO*/0, /*NumAddrSpace*/1, /*AddrSpace*/3,
      GIM_CheckAtomicOrdering, /*MI*/0, /*Order*/(uint8_t)AtomicOrdering::NotAtomic,
      GIM_CheckRegBankForClass, /*MI*/0, /*Op*/0, /*RC*/GIMT_Encode2(AMDGPU::AV_128RegClassID),
      GIM_CheckPointerToAny, /*MI*/0, /*Op*/1, /*SizeInBits*/0,
      GIM_CheckComplexPattern, /*MI*/0, /*Op*/1, /*Renderer*/GIMT_Encode2(0), GIMT_Encode2(GICP_gi_ds_128bit_8byte_aligned),
      // (AMDGPUld_glue:{ *:[v8f16] } (DS128Bit8ByteAligned:{ *:[iPTR] } i32:{ *:[i32] }:$ptr, i8:{ *:[i8] }:$offset0, i8:{ *:[i8] }:$offset1))<<P:Predicate_unindexedload_glue>><<P:Predicate_load_glue>><<P:Predicate_load_local_m0>>  =>  (DS_READ2_B64:{ *:[v8f16] } ?:{ *:[i32] }:$ptr, ?:{ *:[i8] }:$offset0, ?:{ *:[i8] }:$offset1, 0:{ *:[i1] })
      GIR_BuildMI, /*InsnID*/0, /*Opcode*/GIMT_Encode2(AMDGPU::DS_READ2_B64),
      GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/0, // DstI[vdst]
      GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/0, // ptr
      GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/1, // offset0
      GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/2, // offset1
      GIR_AddImm8, /*InsnID*/0, /*Imm*/0,
      GIR_MergeMemOperands, /*InsnID*/0, /*NumInsns*/1, /*MergeInsnID's*/0,
      GIR_ConstrainSelectedInstOperands, /*InsnID*/0,
      GIR_EraseFromParent, /*InsnID*/0,
      // GIR_Coverage, 6731,
      GIR_Done,
    // Label 1583: @105007
    GIM_Try, /*On fail goto*//*Label 1584*/ GIMT_Encode4(105078), // Rule ID 6735 //
      GIM_CheckFeatures, GIMT_Encode2(GIFBS_LDSRequiresM0Init_isGFX7Plus),
      GIM_CheckMemorySizeEqualToLLT, /*MI*/0, /*MMO*/0, /*OpIdx*/0,
      GIM_CheckMemoryAddressSpace, /*MI*/0, /*MMO*/0, /*NumAddrSpace*/1, /*AddrSpace*/3,
      GIM_CheckAtomicOrdering, /*MI*/0, /*Order*/(uint8_t)AtomicOrdering::NotAtomic,
      GIM_CheckRegBankForClass, /*MI*/0, /*Op*/0, /*RC*/GIMT_Encode2(AMDGPU::AV_128RegClassID),
      GIM_CheckPointerToAny, /*MI*/0, /*Op*/1, /*SizeInBits*/0,
      GIM_CheckComplexPattern, /*MI*/0, /*Op*/1, /*Renderer*/GIMT_Encode2(0), GIMT_Encode2(GICP_gi_ds_128bit_8byte_aligned),
      // (AMDGPUld_glue:{ *:[v8bf16] } (DS128Bit8ByteAligned:{ *:[iPTR] } i32:{ *:[i32] }:$ptr, i8:{ *:[i8] }:$offset0, i8:{ *:[i8] }:$offset1))<<P:Predicate_unindexedload_glue>><<P:Predicate_load_glue>><<P:Predicate_load_local_m0>>  =>  (DS_READ2_B64:{ *:[v8bf16] } ?:{ *:[i32] }:$ptr, ?:{ *:[i8] }:$offset0, ?:{ *:[i8] }:$offset1, 0:{ *:[i1] })
      GIR_BuildMI, /*InsnID*/0, /*Opcode*/GIMT_Encode2(AMDGPU::DS_READ2_B64),
      GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/0, // DstI[vdst]
      GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/0, // ptr
      GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/1, // offset0
      GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/2, // offset1
      GIR_AddImm8, /*InsnID*/0, /*Imm*/0,
      GIR_MergeMemOperands, /*InsnID*/0, /*NumInsns*/1, /*MergeInsnID's*/0,
      GIR_ConstrainSelectedInstOperands, /*InsnID*/0,
      GIR_EraseFromParent, /*InsnID*/0,
      // GIR_Coverage, 6735,
      GIR_Done,
    // Label 1584: @105078
    GIM_Try, /*On fail goto*//*Label 1585*/ GIMT_Encode4(105150), // Rule ID 3783 //
      GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasUnrestrictedSOffset),
      GIM_CheckMemoryAddressSpace, /*MI*/0, /*MMO*/0, /*NumAddrSpace*/3, /*AddrSpace*/1, /*AddrSpace*/4, /*AddrSpace*/6,
      GIM_CheckAtomicOrdering, /*MI*/0, /*Order*/(uint8_t)AtomicOrdering::NotAtomic,
      GIM_CheckRegBankForClass, /*MI*/0, /*Op*/0, /*RC*/GIMT_Encode2(AMDGPU::AV_128RegClassID),
      GIM_CheckPointerToAny, /*MI*/0, /*Op*/1, /*SizeInBits*/0,
      GIM_CheckComplexPattern, /*MI*/0, /*Op*/1, /*Renderer*/GIMT_Encode2(0), GIMT_Encode2(GICP_gi_mubuf_offset),
      // (ld:{ *:[v8i16] } (MUBUFOffset:{ *:[iPTR] } v4i32:{ *:[v4i32] }:$srsrc, i32:{ *:[i32] }:$soffset, i32:{ *:[i32] }:$offset))<<P:Predicate_unindexedload>><<P:Predicate_load_global>>  =>  (BUFFER_LOAD_DWORDX4_OFFSET:{ *:[v8i16] } v4i32:{ *:[v4i32] }:$srsrc, i32:{ *:[i32] }:$soffset, i32:{ *:[i32] }:$offset)
      GIR_BuildMI, /*InsnID*/0, /*Opcode*/GIMT_Encode2(AMDGPU::BUFFER_LOAD_DWORDX4_OFFSET),
      GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/0, // DstI[vdata]
      GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/0, // srsrc
      GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/1, // soffset
      GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/2, // offset
      GIR_AddImm8, /*InsnID*/0, /*Imm*/0,
      GIR_AddImm8, /*InsnID*/0, /*Imm*/0,
      GIR_MergeMemOperands, /*InsnID*/0, /*NumInsns*/1, /*MergeInsnID's*/0,
      GIR_ConstrainSelectedInstOperands, /*InsnID*/0,
      GIR_EraseFromParent, /*InsnID*/0,
      // GIR_Coverage, 3783,
      GIR_Done,
    // Label 1585: @105150
    GIM_Try, /*On fail goto*//*Label 1586*/ GIMT_Encode4(105219), // Rule ID 3785 //
      GIM_CheckMemoryAddressSpace, /*MI*/0, /*MMO*/0, /*NumAddrSpace*/3, /*AddrSpace*/1, /*AddrSpace*/4, /*AddrSpace*/6,
      GIM_CheckAtomicOrdering, /*MI*/0, /*Order*/(uint8_t)AtomicOrdering::NotAtomic,
      GIM_CheckRegBankForClass, /*MI*/0, /*Op*/0, /*RC*/GIMT_Encode2(AMDGPU::AV_128RegClassID),
      GIM_CheckPointerToAny, /*MI*/0, /*Op*/1, /*SizeInBits*/0,
      GIM_CheckComplexPattern, /*MI*/0, /*Op*/1, /*Renderer*/GIMT_Encode2(0), GIMT_Encode2(GICP_gi_mubuf_offset),
      // (ld:{ *:[v8i16] } (MUBUFOffset:{ *:[iPTR] } v4i32:{ *:[v4i32] }:$srsrc, i32:{ *:[i32] }:$soffset, i32:{ *:[i32] }:$offset))<<P:Predicate_unindexedload>><<P:Predicate_load_global>>  =>  (BUFFER_LOAD_DWORDX4_VBUFFER_OFFSET:{ *:[v8i16] } v4i32:{ *:[v4i32] }:$srsrc, i32:{ *:[i32] }:$soffset, i32:{ *:[i32] }:$offset)
      GIR_BuildMI, /*InsnID*/0, /*Opcode*/GIMT_Encode2(AMDGPU::BUFFER_LOAD_DWORDX4_VBUFFER_OFFSET),
      GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/0, // DstI[vdata]
      GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/0, // srsrc
      GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/1, // soffset
      GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/2, // offset
      GIR_AddImm8, /*InsnID*/0, /*Imm*/0,
      GIR_AddImm8, /*InsnID*/0, /*Imm*/0,
      GIR_MergeMemOperands, /*InsnID*/0, /*NumInsns*/1, /*MergeInsnID's*/0,
      GIR_ConstrainSelectedInstOperands, /*InsnID*/0,
      GIR_EraseFromParent, /*InsnID*/0,
      // GIR_Coverage, 3785,
      GIR_Done,
    // Label 1586: @105219
    GIM_Try, /*On fail goto*//*Label 1587*/ GIMT_Encode4(105291), // Rule ID 3787 //
      GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasUnrestrictedSOffset),
      GIM_CheckMemoryAddressSpace, /*MI*/0, /*MMO*/0, /*NumAddrSpace*/3, /*AddrSpace*/1, /*AddrSpace*/4, /*AddrSpace*/6,
      GIM_CheckAtomicOrdering, /*MI*/0, /*Order*/(uint8_t)AtomicOrdering::NotAtomic,
      GIM_CheckRegBankForClass, /*MI*/0, /*Op*/0, /*RC*/GIMT_Encode2(AMDGPU::AV_128RegClassID),
      GIM_CheckPointerToAny, /*MI*/0, /*Op*/1, /*SizeInBits*/0,
      GIM_CheckComplexPattern, /*MI*/0, /*Op*/1, /*Renderer*/GIMT_Encode2(0), GIMT_Encode2(GICP_gi_mubuf_offset),
      // (ld:{ *:[v8f16] } (MUBUFOffset:{ *:[iPTR] } v4i32:{ *:[v4i32] }:$srsrc, i32:{ *:[i32] }:$soffset, i32:{ *:[i32] }:$offset))<<P:Predicate_unindexedload>><<P:Predicate_load_global>>  =>  (BUFFER_LOAD_DWORDX4_OFFSET:{ *:[v8f16] } v4i32:{ *:[v4i32] }:$srsrc, i32:{ *:[i32] }:$soffset, i32:{ *:[i32] }:$offset)
      GIR_BuildMI, /*InsnID*/0, /*Opcode*/GIMT_Encode2(AMDGPU::BUFFER_LOAD_DWORDX4_OFFSET),
      GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/0, // DstI[vdata]
      GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/0, // srsrc
      GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/1, // soffset
      GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/2, // offset
      GIR_AddImm8, /*InsnID*/0, /*Imm*/0,
      GIR_AddImm8, /*InsnID*/0, /*Imm*/0,
      GIR_MergeMemOperands, /*InsnID*/0, /*NumInsns*/1, /*MergeInsnID's*/0,
      GIR_ConstrainSelectedInstOperands, /*InsnID*/0,
      GIR_EraseFromParent, /*InsnID*/0,
      // GIR_Coverage, 3787,
      GIR_Done,
    // Label 1587: @105291
    GIM_Try, /*On fail goto*//*Label 1588*/ GIMT_Encode4(105360), // Rule ID 3789 //
      GIM_CheckMemoryAddressSpace, /*MI*/0, /*MMO*/0, /*NumAddrSpace*/3, /*AddrSpace*/1, /*AddrSpace*/4, /*AddrSpace*/6,
      GIM_CheckAtomicOrdering, /*MI*/0, /*Order*/(uint8_t)AtomicOrdering::NotAtomic,
      GIM_CheckRegBankForClass, /*MI*/0, /*Op*/0, /*RC*/GIMT_Encode2(AMDGPU::AV_128RegClassID),
      GIM_CheckPointerToAny, /*MI*/0, /*Op*/1, /*SizeInBits*/0,
      GIM_CheckComplexPattern, /*MI*/0, /*Op*/1, /*Renderer*/GIMT_Encode2(0), GIMT_Encode2(GICP_gi_mubuf_offset),
      // (ld:{ *:[v8f16] } (MUBUFOffset:{ *:[iPTR] } v4i32:{ *:[v4i32] }:$srsrc, i32:{ *:[i32] }:$soffset, i32:{ *:[i32] }:$offset))<<P:Predicate_unindexedload>><<P:Predicate_load_global>>  =>  (BUFFER_LOAD_DWORDX4_VBUFFER_OFFSET:{ *:[v8f16] } v4i32:{ *:[v4i32] }:$srsrc, i32:{ *:[i32] }:$soffset, i32:{ *:[i32] }:$offset)
      GIR_BuildMI, /*InsnID*/0, /*Opcode*/GIMT_Encode2(AMDGPU::BUFFER_LOAD_DWORDX4_VBUFFER_OFFSET),
      GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/0, // DstI[vdata]
      GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/0, // srsrc
      GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/1, // soffset
      GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/2, // offset
      GIR_AddImm8, /*InsnID*/0, /*Imm*/0,
      GIR_AddImm8, /*InsnID*/0, /*Imm*/0,
      GIR_MergeMemOperands, /*InsnID*/0, /*NumInsns*/1, /*MergeInsnID's*/0,
      GIR_ConstrainSelectedInstOperands, /*InsnID*/0,
      GIR_EraseFromParent, /*InsnID*/0,
      // GIR_Coverage, 3789,
      GIR_Done,
    // Label 1588: @105360
    GIM_Try, /*On fail goto*//*Label 1589*/ GIMT_Encode4(105432), // Rule ID 3791 //
      GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasUnrestrictedSOffset),
      GIM_CheckMemoryAddressSpace, /*MI*/0, /*MMO*/0, /*NumAddrSpace*/3, /*AddrSpace*/1, /*AddrSpace*/4, /*AddrSpace*/6,
      GIM_CheckAtomicOrdering, /*MI*/0, /*Order*/(uint8_t)AtomicOrdering::NotAtomic,
      GIM_CheckRegBankForClass, /*MI*/0, /*Op*/0, /*RC*/GIMT_Encode2(AMDGPU::AV_128RegClassID),
      GIM_CheckPointerToAny, /*MI*/0, /*Op*/1, /*SizeInBits*/0,
      GIM_CheckComplexPattern, /*MI*/0, /*Op*/1, /*Renderer*/GIMT_Encode2(0), GIMT_Encode2(GICP_gi_mubuf_offset),
      // (ld:{ *:[v8bf16] } (MUBUFOffset:{ *:[iPTR] } v4i32:{ *:[v4i32] }:$srsrc, i32:{ *:[i32] }:$soffset, i32:{ *:[i32] }:$offset))<<P:Predicate_unindexedload>><<P:Predicate_load_global>>  =>  (BUFFER_LOAD_DWORDX4_OFFSET:{ *:[v8bf16] } v4i32:{ *:[v4i32] }:$srsrc, i32:{ *:[i32] }:$soffset, i32:{ *:[i32] }:$offset)
      GIR_BuildMI, /*InsnID*/0, /*Opcode*/GIMT_Encode2(AMDGPU::BUFFER_LOAD_DWORDX4_OFFSET),
      GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/0, // DstI[vdata]
      GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/0, // srsrc
      GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/1, // soffset
      GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/2, // offset
      GIR_AddImm8, /*InsnID*/0, /*Imm*/0,
      GIR_AddImm8, /*InsnID*/0, /*Imm*/0,
      GIR_MergeMemOperands, /*InsnID*/0, /*NumInsns*/1, /*MergeInsnID's*/0,
      GIR_ConstrainSelectedInstOperands, /*InsnID*/0,
      GIR_EraseFromParent, /*InsnID*/0,
      // GIR_Coverage, 3791,
      GIR_Done,
    // Label 1589: @105432
    GIM_Try, /*On fail goto*//*Label 1590*/ GIMT_Encode4(105501), // Rule ID 3793 //
      GIM_CheckMemoryAddressSpace, /*MI*/0, /*MMO*/0, /*NumAddrSpace*/3, /*AddrSpace*/1, /*AddrSpace*/4, /*AddrSpace*/6,
      GIM_CheckAtomicOrdering, /*MI*/0, /*Order*/(uint8_t)AtomicOrdering::NotAtomic,
      GIM_CheckRegBankForClass, /*MI*/0, /*Op*/0, /*RC*/GIMT_Encode2(AMDGPU::AV_128RegClassID),
      GIM_CheckPointerToAny, /*MI*/0, /*Op*/1, /*SizeInBits*/0,
      GIM_CheckComplexPattern, /*MI*/0, /*Op*/1, /*Renderer*/GIMT_Encode2(0), GIMT_Encode2(GICP_gi_mubuf_offset),
      // (ld:{ *:[v8bf16] } (MUBUFOffset:{ *:[iPTR] } v4i32:{ *:[v4i32] }:$srsrc, i32:{ *:[i32] }:$soffset, i32:{ *:[i32] }:$offset))<<P:Predicate_unindexedload>><<P:Predicate_load_global>>  =>  (BUFFER_LOAD_DWORDX4_VBUFFER_OFFSET:{ *:[v8bf16] } v4i32:{ *:[v4i32] }:$srsrc, i32:{ *:[i32] }:$soffset, i32:{ *:[i32] }:$offset)
      GIR_BuildMI, /*InsnID*/0, /*Opcode*/GIMT_Encode2(AMDGPU::BUFFER_LOAD_DWORDX4_VBUFFER_OFFSET),
      GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/0, // DstI[vdata]
      GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/0, // srsrc
      GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/1, // soffset
      GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/2, // offset
      GIR_AddImm8, /*InsnID*/0, /*Imm*/0,
      GIR_AddImm8, /*InsnID*/0, /*Imm*/0,
      GIR_MergeMemOperands, /*InsnID*/0, /*NumInsns*/1, /*MergeInsnID's*/0,
      GIR_ConstrainSelectedInstOperands, /*InsnID*/0,
      GIR_EraseFromParent, /*InsnID*/0,
      // GIR_Coverage, 3793,
      GIR_Done,
    // Label 1590: @105501
    GIM_Try, /*On fail goto*//*Label 1591*/ GIMT_Encode4(105568), // Rule ID 6729 //
      GIM_CheckFeatures, GIMT_Encode2(GIFBS_NotLDSRequiresM0Init),
      GIM_CheckMemoryAddressSpace, /*MI*/0, /*MMO*/0, /*NumAddrSpace*/1, /*AddrSpace*/3,
      GIM_CheckAtomicOrdering, /*MI*/0, /*Order*/(uint8_t)AtomicOrdering::NotAtomic,
      GIM_CheckRegBankForClass, /*MI*/0, /*Op*/0, /*RC*/GIMT_Encode2(AMDGPU::AV_128RegClassID),
      GIM_CheckPointerToAny, /*MI*/0, /*Op*/1, /*SizeInBits*/0,
      GIM_CheckComplexPattern, /*MI*/0, /*Op*/1, /*Renderer*/GIMT_Encode2(0), GIMT_Encode2(GICP_gi_ds_128bit_8byte_aligned),
      // (ld:{ *:[v8i16] } (DS128Bit8ByteAligned:{ *:[iPTR] } i32:{ *:[i32] }:$ptr, i8:{ *:[i8] }:$offset0, i8:{ *:[i8] }:$offset1))<<P:Predicate_unindexedload>><<P:Predicate_load_local>>  =>  (DS_READ2_B64_gfx9:{ *:[v8i16] } ?:{ *:[i32] }:$ptr, ?:{ *:[i8] }:$offset0, ?:{ *:[i8] }:$offset1, 0:{ *:[i1] })
      GIR_BuildMI, /*InsnID*/0, /*Opcode*/GIMT_Encode2(AMDGPU::DS_READ2_B64_gfx9),
      GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/0, // DstI[vdst]
      GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/0, // ptr
      GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/1, // offset0
      GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/2, // offset1
      GIR_AddImm8, /*InsnID*/0, /*Imm*/0,
      GIR_MergeMemOperands, /*InsnID*/0, /*NumInsns*/1, /*MergeInsnID's*/0,
      GIR_ConstrainSelectedInstOperands, /*InsnID*/0,
      GIR_EraseFromParent, /*InsnID*/0,
      // GIR_Coverage, 6729,
      GIR_Done,
    // Label 1591: @105568
    GIM_Try, /*On fail goto*//*Label 1592*/ GIMT_Encode4(105635), // Rule ID 6733 //
      GIM_CheckFeatures, GIMT_Encode2(GIFBS_NotLDSRequiresM0Init),
      GIM_CheckMemoryAddressSpace, /*MI*/0, /*MMO*/0, /*NumAddrSpace*/1, /*AddrSpace*/3,
      GIM_CheckAtomicOrdering, /*MI*/0, /*Order*/(uint8_t)AtomicOrdering::NotAtomic,
      GIM_CheckRegBankForClass, /*MI*/0, /*Op*/0, /*RC*/GIMT_Encode2(AMDGPU::AV_128RegClassID),
      GIM_CheckPointerToAny, /*MI*/0, /*Op*/1, /*SizeInBits*/0,
      GIM_CheckComplexPattern, /*MI*/0, /*Op*/1, /*Renderer*/GIMT_Encode2(0), GIMT_Encode2(GICP_gi_ds_128bit_8byte_aligned),
      // (ld:{ *:[v8f16] } (DS128Bit8ByteAligned:{ *:[iPTR] } i32:{ *:[i32] }:$ptr, i8:{ *:[i8] }:$offset0, i8:{ *:[i8] }:$offset1))<<P:Predicate_unindexedload>><<P:Predicate_load_local>>  =>  (DS_READ2_B64_gfx9:{ *:[v8f16] } ?:{ *:[i32] }:$ptr, ?:{ *:[i8] }:$offset0, ?:{ *:[i8] }:$offset1, 0:{ *:[i1] })
      GIR_BuildMI, /*InsnID*/0, /*Opcode*/GIMT_Encode2(AMDGPU::DS_READ2_B64_gfx9),
      GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/0, // DstI[vdst]
      GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/0, // ptr
      GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/1, // offset0
      GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/2, // offset1
      GIR_AddImm8, /*InsnID*/0, /*Imm*/0,
      GIR_MergeMemOperands, /*InsnID*/0, /*NumInsns*/1, /*MergeInsnID's*/0,
      GIR_ConstrainSelectedInstOperands, /*InsnID*/0,
      GIR_EraseFromParent, /*InsnID*/0,
      // GIR_Coverage, 6733,
      GIR_Done,
    // Label 1592: @105635
    GIM_Try, /*On fail goto*//*Label 1593*/ GIMT_Encode4(105702), // Rule ID 6737 //
      GIM_CheckFeatures, GIMT_Encode2(GIFBS_NotLDSRequiresM0Init),
      GIM_CheckMemoryAddressSpace, /*MI*/0, /*MMO*/0, /*NumAddrSpace*/1, /*AddrSpace*/3,
      GIM_CheckAtomicOrdering, /*MI*/0, /*Order*/(uint8_t)AtomicOrdering::NotAtomic,
      GIM_CheckRegBankForClass, /*MI*/0, /*Op*/0, /*RC*/GIMT_Encode2(AMDGPU::AV_128RegClassID),
      GIM_CheckPointerToAny, /*MI*/0, /*Op*/1, /*SizeInBits*/0,
      GIM_CheckComplexPattern, /*MI*/0, /*Op*/1, /*Renderer*/GIMT_Encode2(0), GIMT_Encode2(GICP_gi_ds_128bit_8byte_aligned),
      // (ld:{ *:[v8bf16] } (DS128Bit8ByteAligned:{ *:[iPTR] } i32:{ *:[i32] }:$ptr, i8:{ *:[i8] }:$offset0, i8:{ *:[i8] }:$offset1))<<P:Predicate_unindexedload>><<P:Predicate_load_local>>  =>  (DS_READ2_B64_gfx9:{ *:[v8bf16] } ?:{ *:[i32] }:$ptr, ?:{ *:[i8] }:$offset0, ?:{ *:[i8] }:$offset1, 0:{ *:[i1] })
      GIR_BuildMI, /*InsnID*/0, /*Opcode*/GIMT_Encode2(AMDGPU::DS_READ2_B64_gfx9),
      GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/0, // DstI[vdst]
      GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/0, // ptr
      GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/1, // offset0
      GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/2, // offset1
      GIR_AddImm8, /*InsnID*/0, /*Imm*/0,
      GIR_MergeMemOperands, /*InsnID*/0, /*NumInsns*/1, /*MergeInsnID's*/0,
      GIR_ConstrainSelectedInstOperands, /*InsnID*/0,
      GIR_EraseFromParent, /*InsnID*/0,
      // GIR_Coverage, 6737,
      GIR_Done,
    // Label 1593: @105702
    GIM_Try, /*On fail goto*//*Label 1594*/ GIMT_Encode4(105771), // Rule ID 3087 //
      GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasFlatGlobalInsts),
      GIM_CheckMemoryAddressSpace, /*MI*/0, /*MMO*/0, /*NumAddrSpace*/3, /*AddrSpace*/1, /*AddrSpace*/4, /*AddrSpace*/6,
      GIM_CheckAtomicOrdering, /*MI*/0, /*Order*/(uint8_t)AtomicOrdering::NotAtomic,
      GIM_CheckRegBankForClass, /*MI*/0, /*Op*/0, /*RC*/GIMT_Encode2(AMDGPU::AV_128RegClassID),
      GIM_CheckPointerToAny, /*MI*/0, /*Op*/1, /*SizeInBits*/0,
      GIM_CheckComplexPattern, /*MI*/0, /*Op*/1, /*Renderer*/GIMT_Encode2(0), GIMT_Encode2(GICP_gi_global_saddr),
      // (ld:{ *:[v8i16] } (GlobalSAddr:{ *:[iPTR] } SReg_64:{ *:[i64] }:$saddr, VGPR_32:{ *:[i32] }:$voffset, i32:{ *:[i32] }:$offset))<<P:Predicate_unindexedload>><<P:Predicate_load_global>>  =>  (GLOBAL_LOAD_DWORDX4_SADDR:{ *:[v8i16] } ?:{ *:[i64] }:$saddr, ?:{ *:[i32] }:$voffset, ?:{ *:[i32] }:$offset, 0:{ *:[i32] })
      GIR_BuildMI, /*InsnID*/0, /*Opcode*/GIMT_Encode2(AMDGPU::GLOBAL_LOAD_DWORDX4_SADDR),
      GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/0, // DstI[vdst]
      GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/0, // saddr
      GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/1, // voffset
      GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/2, // offset
      GIR_AddImm8, /*InsnID*/0, /*Imm*/0,
      GIR_MergeMemOperands, /*InsnID*/0, /*NumInsns*/1, /*MergeInsnID's*/0,
      GIR_ConstrainSelectedInstOperands, /*InsnID*/0,
      GIR_EraseFromParent, /*InsnID*/0,
      // GIR_Coverage, 3087,
      GIR_Done,
    // Label 1594: @105771
    GIM_Try, /*On fail goto*//*Label 1595*/ GIMT_Encode4(105840), // Rule ID 3091 //
      GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasFlatGlobalInsts),
      GIM_CheckMemoryAddressSpace, /*MI*/0, /*MMO*/0, /*NumAddrSpace*/3, /*AddrSpace*/1, /*AddrSpace*/4, /*AddrSpace*/6,
      GIM_CheckAtomicOrdering, /*MI*/0, /*Order*/(uint8_t)AtomicOrdering::NotAtomic,
      GIM_CheckRegBankForClass, /*MI*/0, /*Op*/0, /*RC*/GIMT_Encode2(AMDGPU::AV_128RegClassID),
      GIM_CheckPointerToAny, /*MI*/0, /*Op*/1, /*SizeInBits*/0,
      GIM_CheckComplexPattern, /*MI*/0, /*Op*/1, /*Renderer*/GIMT_Encode2(0), GIMT_Encode2(GICP_gi_global_saddr),
      // (ld:{ *:[v8f16] } (GlobalSAddr:{ *:[iPTR] } SReg_64:{ *:[i64] }:$saddr, VGPR_32:{ *:[i32] }:$voffset, i32:{ *:[i32] }:$offset))<<P:Predicate_unindexedload>><<P:Predicate_load_global>>  =>  (GLOBAL_LOAD_DWORDX4_SADDR:{ *:[v8f16] } ?:{ *:[i64] }:$saddr, ?:{ *:[i32] }:$voffset, ?:{ *:[i32] }:$offset, 0:{ *:[i32] })
      GIR_BuildMI, /*InsnID*/0, /*Opcode*/GIMT_Encode2(AMDGPU::GLOBAL_LOAD_DWORDX4_SADDR),
      GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/0, // DstI[vdst]
      GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/0, // saddr
      GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/1, // voffset
      GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/2, // offset
      GIR_AddImm8, /*InsnID*/0, /*Imm*/0,
      GIR_MergeMemOperands, /*InsnID*/0, /*NumInsns*/1, /*MergeInsnID's*/0,
      GIR_ConstrainSelectedInstOperands, /*InsnID*/0,
      GIR_EraseFromParent, /*InsnID*/0,
      // GIR_Coverage, 3091,
      GIR_Done,
    // Label 1595: @105840
    GIM_Try, /*On fail goto*//*Label 1596*/ GIMT_Encode4(105909), // Rule ID 3095 //
      GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasFlatGlobalInsts),
      GIM_CheckMemoryAddressSpace, /*MI*/0, /*MMO*/0, /*NumAddrSpace*/3, /*AddrSpace*/1, /*AddrSpace*/4, /*AddrSpace*/6,
      GIM_CheckAtomicOrdering, /*MI*/0, /*Order*/(uint8_t)AtomicOrdering::NotAtomic,
      GIM_CheckRegBankForClass, /*MI*/0, /*Op*/0, /*RC*/GIMT_Encode2(AMDGPU::AV_128RegClassID),
      GIM_CheckPointerToAny, /*MI*/0, /*Op*/1, /*SizeInBits*/0,
      GIM_CheckComplexPattern, /*MI*/0, /*Op*/1, /*Renderer*/GIMT_Encode2(0), GIMT_Encode2(GICP_gi_global_saddr),
      // (ld:{ *:[v8bf16] } (GlobalSAddr:{ *:[iPTR] } SReg_64:{ *:[i64] }:$saddr, VGPR_32:{ *:[i32] }:$voffset, i32:{ *:[i32] }:$offset))<<P:Predicate_unindexedload>><<P:Predicate_load_global>>  =>  (GLOBAL_LOAD_DWORDX4_SADDR:{ *:[v8bf16] } ?:{ *:[i64] }:$saddr, ?:{ *:[i32] }:$voffset, ?:{ *:[i32] }:$offset, 0:{ *:[i32] })
      GIR_BuildMI, /*InsnID*/0, /*Opcode*/GIMT_Encode2(AMDGPU::GLOBAL_LOAD_DWORDX4_SADDR),
      GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/0, // DstI[vdst]
      GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/0, // saddr
      GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/1, // voffset
      GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/2, // offset
      GIR_AddImm8, /*InsnID*/0, /*Imm*/0,
      GIR_MergeMemOperands, /*InsnID*/0, /*NumInsns*/1, /*MergeInsnID's*/0,
      GIR_ConstrainSelectedInstOperands, /*InsnID*/0,
      GIR_EraseFromParent, /*InsnID*/0,
      // GIR_Coverage, 3095,
      GIR_Done,
    // Label 1596: @105909
    GIM_Try, /*On fail goto*//*Label 1597*/ GIMT_Encode4(105973), // Rule ID 3086 //
      GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasFlatGlobalInsts),
      GIM_CheckMemoryAddressSpace, /*MI*/0, /*MMO*/0, /*NumAddrSpace*/3, /*AddrSpace*/1, /*AddrSpace*/4, /*AddrSpace*/6,
      GIM_CheckAtomicOrdering, /*MI*/0, /*Order*/(uint8_t)AtomicOrdering::NotAtomic,
      GIM_CheckRegBankForClass, /*MI*/0, /*Op*/0, /*RC*/GIMT_Encode2(AMDGPU::AV_128RegClassID),
      GIM_CheckPointerToAny, /*MI*/0, /*Op*/1, /*SizeInBits*/0,
      GIM_CheckComplexPattern, /*MI*/0, /*Op*/1, /*Renderer*/GIMT_Encode2(0), GIMT_Encode2(GICP_gi_global_offset),
      // (ld:{ *:[v8i16] } (GlobalOffset:{ *:[iPTR] } VReg_64:{ *:[i64] }:$vaddr, i32:{ *:[i32] }:$offset))<<P:Predicate_unindexedload>><<P:Predicate_load_global>>  =>  (GLOBAL_LOAD_DWORDX4:{ *:[v8i16] } ?:{ *:[i64] }:$vaddr, ?:{ *:[i32] }:$offset)
      GIR_BuildMI, /*InsnID*/0, /*Opcode*/GIMT_Encode2(AMDGPU::GLOBAL_LOAD_DWORDX4),
      GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/0, // DstI[vdst]
      GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/0, // vaddr
      GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/1, // offset
      GIR_AddImm8, /*InsnID*/0, /*Imm*/0,
      GIR_MergeMemOperands, /*InsnID*/0, /*NumInsns*/1, /*MergeInsnID's*/0,
      GIR_ConstrainSelectedInstOperands, /*InsnID*/0,
      GIR_EraseFromParent, /*InsnID*/0,
      // GIR_Coverage, 3086,
      GIR_Done,
    // Label 1597: @105973
    GIM_Try, /*On fail goto*//*Label 1598*/ GIMT_Encode4(106037), // Rule ID 3090 //
      GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasFlatGlobalInsts),
      GIM_CheckMemoryAddressSpace, /*MI*/0, /*MMO*/0, /*NumAddrSpace*/3, /*AddrSpace*/1, /*AddrSpace*/4, /*AddrSpace*/6,
      GIM_CheckAtomicOrdering, /*MI*/0, /*Order*/(uint8_t)AtomicOrdering::NotAtomic,
      GIM_CheckRegBankForClass, /*MI*/0, /*Op*/0, /*RC*/GIMT_Encode2(AMDGPU::AV_128RegClassID),
      GIM_CheckPointerToAny, /*MI*/0, /*Op*/1, /*SizeInBits*/0,
      GIM_CheckComplexPattern, /*MI*/0, /*Op*/1, /*Renderer*/GIMT_Encode2(0), GIMT_Encode2(GICP_gi_global_offset),
      // (ld:{ *:[v8f16] } (GlobalOffset:{ *:[iPTR] } VReg_64:{ *:[i64] }:$vaddr, i32:{ *:[i32] }:$offset))<<P:Predicate_unindexedload>><<P:Predicate_load_global>>  =>  (GLOBAL_LOAD_DWORDX4:{ *:[v8f16] } ?:{ *:[i64] }:$vaddr, ?:{ *:[i32] }:$offset)
      GIR_BuildMI, /*InsnID*/0, /*Opcode*/GIMT_Encode2(AMDGPU::GLOBAL_LOAD_DWORDX4),
      GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/0, // DstI[vdst]
      GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/0, // vaddr
      GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/1, // offset
      GIR_AddImm8, /*InsnID*/0, /*Imm*/0,
      GIR_MergeMemOperands, /*InsnID*/0, /*NumInsns*/1, /*MergeInsnID's*/0,
      GIR_ConstrainSelectedInstOperands, /*InsnID*/0,
      GIR_EraseFromParent, /*InsnID*/0,
      // GIR_Coverage, 3090,
      GIR_Done,
    // Label 1598: @106037
    GIM_Try, /*On fail goto*//*Label 1599*/ GIMT_Encode4(106101), // Rule ID 3094 //
      GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasFlatGlobalInsts),
      GIM_CheckMemoryAddressSpace, /*MI*/0, /*MMO*/0, /*NumAddrSpace*/3, /*AddrSpace*/1, /*AddrSpace*/4, /*AddrSpace*/6,
      GIM_CheckAtomicOrdering, /*MI*/0, /*Order*/(uint8_t)AtomicOrdering::NotAtomic,
      GIM_CheckRegBankForClass, /*MI*/0, /*Op*/0, /*RC*/GIMT_Encode2(AMDGPU::AV_128RegClassID),
      GIM_CheckPointerToAny, /*MI*/0, /*Op*/1, /*SizeInBits*/0,
      GIM_CheckComplexPattern, /*MI*/0, /*Op*/1, /*Renderer*/GIMT_Encode2(0), GIMT_Encode2(GICP_gi_global_offset),
      // (ld:{ *:[v8bf16] } (GlobalOffset:{ *:[iPTR] } VReg_64:{ *:[i64] }:$vaddr, i32:{ *:[i32] }:$offset))<<P:Predicate_unindexedload>><<P:Predicate_load_global>>  =>  (GLOBAL_LOAD_DWORDX4:{ *:[v8bf16] } ?:{ *:[i64] }:$vaddr, ?:{ *:[i32] }:$offset)
      GIR_BuildMI, /*InsnID*/0, /*Opcode*/GIMT_Encode2(AMDGPU::GLOBAL_LOAD_DWORDX4),
      GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/0, // DstI[vdst]
      GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/0, // vaddr
      GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/1, // offset
      GIR_AddImm8, /*InsnID*/0, /*Imm*/0,
      GIR_MergeMemOperands, /*InsnID*/0, /*NumInsns*/1, /*MergeInsnID's*/0,
      GIR_ConstrainSelectedInstOperands, /*InsnID*/0,
      GIR_EraseFromParent, /*InsnID*/0,
      // GIR_Coverage, 3094,
      GIR_Done,
    // Label 1599: @106101
    GIM_Try, /*On fail goto*//*Label 1600*/ GIMT_Encode4(106166), // Rule ID 2817 //
      GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasFlatAddressSpace),
      GIM_CheckMemoryAddressSpace, /*MI*/0, /*MMO*/0, /*NumAddrSpace*/4, /*AddrSpace*/0, /*AddrSpace*/1, /*AddrSpace*/4, /*AddrSpace*/6,
      GIM_CheckAtomicOrdering, /*MI*/0, /*Order*/(uint8_t)AtomicOrdering::NotAtomic,
      GIM_CheckRegBankForClass, /*MI*/0, /*Op*/0, /*RC*/GIMT_Encode2(AMDGPU::AV_128RegClassID),
      GIM_CheckPointerToAny, /*MI*/0, /*Op*/1, /*SizeInBits*/0,
      GIM_CheckComplexPattern, /*MI*/0, /*Op*/1, /*Renderer*/GIMT_Encode2(0), GIMT_Encode2(GICP_gi_flat_offset),
      // (ld:{ *:[v8i16] } (FlatOffset:{ *:[iPTR] } i64:{ *:[i64] }:$vaddr, i32:{ *:[i32] }:$offset))<<P:Predicate_unindexedload>><<P:Predicate_load_flat>>  =>  (FLAT_LOAD_DWORDX4:{ *:[v8i16] } ?:{ *:[i64] }:$vaddr, ?:{ *:[i32] }:$offset)
      GIR_BuildMI, /*InsnID*/0, /*Opcode*/GIMT_Encode2(AMDGPU::FLAT_LOAD_DWORDX4),
      GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/0, // DstI[vdst]
      GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/0, // vaddr
      GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/1, // offset
      GIR_AddImm8, /*InsnID*/0, /*Imm*/0,
      GIR_MergeMemOperands, /*InsnID*/0, /*NumInsns*/1, /*MergeInsnID's*/0,
      GIR_ConstrainSelectedInstOperands, /*InsnID*/0,
      GIR_EraseFromParent, /*InsnID*/0,
      // GIR_Coverage, 2817,
      GIR_Done,
    // Label 1600: @106166
    GIM_Try, /*On fail goto*//*Label 1601*/ GIMT_Encode4(106231), // Rule ID 2819 //
      GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasFlatAddressSpace),
      GIM_CheckMemoryAddressSpace, /*MI*/0, /*MMO*/0, /*NumAddrSpace*/4, /*AddrSpace*/0, /*AddrSpace*/1, /*AddrSpace*/4, /*AddrSpace*/6,
      GIM_CheckAtomicOrdering, /*MI*/0, /*Order*/(uint8_t)AtomicOrdering::NotAtomic,
      GIM_CheckRegBankForClass, /*MI*/0, /*Op*/0, /*RC*/GIMT_Encode2(AMDGPU::AV_128RegClassID),
      GIM_CheckPointerToAny, /*MI*/0, /*Op*/1, /*SizeInBits*/0,
      GIM_CheckComplexPattern, /*MI*/0, /*Op*/1, /*Renderer*/GIMT_Encode2(0), GIMT_Encode2(GICP_gi_flat_offset),
      // (ld:{ *:[v8f16] } (FlatOffset:{ *:[iPTR] } i64:{ *:[i64] }:$vaddr, i32:{ *:[i32] }:$offset))<<P:Predicate_unindexedload>><<P:Predicate_load_flat>>  =>  (FLAT_LOAD_DWORDX4:{ *:[v8f16] } ?:{ *:[i64] }:$vaddr, ?:{ *:[i32] }:$offset)
      GIR_BuildMI, /*InsnID*/0, /*Opcode*/GIMT_Encode2(AMDGPU::FLAT_LOAD_DWORDX4),
      GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/0, // DstI[vdst]
      GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/0, // vaddr
      GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/1, // offset
      GIR_AddImm8, /*InsnID*/0, /*Imm*/0,
      GIR_MergeMemOperands, /*InsnID*/0, /*NumInsns*/1, /*MergeInsnID's*/0,
      GIR_ConstrainSelectedInstOperands, /*InsnID*/0,
      GIR_EraseFromParent, /*InsnID*/0,
      // GIR_Coverage, 2819,
      GIR_Done,
    // Label 1601: @106231
    GIM_Try, /*On fail goto*//*Label 1602*/ GIMT_Encode4(106296), // Rule ID 2821 //
      GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasFlatAddressSpace),
      GIM_CheckMemoryAddressSpace, /*MI*/0, /*MMO*/0, /*NumAddrSpace*/4, /*AddrSpace*/0, /*AddrSpace*/1, /*AddrSpace*/4, /*AddrSpace*/6,
      GIM_CheckAtomicOrdering, /*MI*/0, /*Order*/(uint8_t)AtomicOrdering::NotAtomic,
      GIM_CheckRegBankForClass, /*MI*/0, /*Op*/0, /*RC*/GIMT_Encode2(AMDGPU::AV_128RegClassID),
      GIM_CheckPointerToAny, /*MI*/0, /*Op*/1, /*SizeInBits*/0,
      GIM_CheckComplexPattern, /*MI*/0, /*Op*/1, /*Renderer*/GIMT_Encode2(0), GIMT_Encode2(GICP_gi_flat_offset),
      // (ld:{ *:[v8bf16] } (FlatOffset:{ *:[iPTR] } i64:{ *:[i64] }:$vaddr, i32:{ *:[i32] }:$offset))<<P:Predicate_unindexedload>><<P:Predicate_load_flat>>  =>  (FLAT_LOAD_DWORDX4:{ *:[v8bf16] } ?:{ *:[i64] }:$vaddr, ?:{ *:[i32] }:$offset)
      GIR_BuildMI, /*InsnID*/0, /*Opcode*/GIMT_Encode2(AMDGPU::FLAT_LOAD_DWORDX4),
      GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/0, // DstI[vdst]
      GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/0, // vaddr
      GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/1, // offset
      GIR_AddImm8, /*InsnID*/0, /*Imm*/0,
      GIR_MergeMemOperands, /*InsnID*/0, /*NumInsns*/1, /*MergeInsnID's*/0,
      GIR_ConstrainSelectedInstOperands, /*InsnID*/0,
      GIR_EraseFromParent, /*InsnID*/0,
      // GIR_Coverage, 2821,
      GIR_Done,
    // Label 1602: @106296
    GIM_Reject,
    // Label 835: @106297
    GIM_Try, /*On fail goto*//*Label 1603*/ GIMT_Encode4(106901),
      GIM_CheckMemorySizeEqualToLLT, /*MI*/0, /*MMO*/0, /*OpIdx*/0,
      GIM_CheckCxxInsnPredicate, /*MI*/0, /*FnId*/GIMT_Encode2(GICXXPred_MI_Predicate_smrd_load),
      GIM_CheckAtomicOrdering, /*MI*/0, /*Order*/(uint8_t)AtomicOrdering::NotAtomic,
      GIM_CheckRegBankForClass, /*MI*/0, /*Op*/0, /*RC*/GIMT_Encode2(AMDGPU::SReg_256RegClassID),
      GIM_Try, /*On fail goto*//*Label 1604*/ GIMT_Encode4(106372), // Rule ID 2604 //
        GIM_CheckFeatures, GIMT_Encode2(GIFBS_isGFX9Plus),
        GIM_CheckPointerToAny, /*MI*/0, /*Op*/1, /*SizeInBits*/0,
        GIM_CheckComplexPattern, /*MI*/0, /*Op*/1, /*Renderer*/GIMT_Encode2(0), GIMT_Encode2(GICP_gi_smrd_sgpr_imm),
        // (ld:{ *:[v8i32] } (SMRDSgprImm:{ *:[iPTR] } i64:{ *:[i64] }:$sbase, i32:{ *:[i32] }:$soffset, i32:{ *:[i32] }:$offset))<<P:Predicate_unindexedload>><<P:Predicate_load>><<P:Predicate_smrd_load>>  =>  (S_LOAD_DWORDX8_SGPR_IMM:{ *:[v8i32] } ?:{ *:[i64] }:$sbase, ?:{ *:[i32] }:$soffset, ?:{ *:[i32] }:$offset, 0:{ *:[i32] })
        GIR_BuildMI, /*InsnID*/0, /*Opcode*/GIMT_Encode2(AMDGPU::S_LOAD_DWORDX8_SGPR_IMM),
        GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/0, // DstI[sdst]
        GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/0, // sbase
        GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/1, // soffset
        GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/2, // offset
        GIR_AddImm8, /*InsnID*/0, /*Imm*/0,
        GIR_MergeMemOperands, /*InsnID*/0, /*NumInsns*/1, /*MergeInsnID's*/0,
        GIR_ConstrainSelectedInstOperands, /*InsnID*/0,
        GIR_EraseFromParent, /*InsnID*/0,
        // GIR_Coverage, 2604,
        GIR_Done,
      // Label 1604: @106372
      GIM_Try, /*On fail goto*//*Label 1605*/ GIMT_Encode4(106426), // Rule ID 2610 //
        GIM_CheckFeatures, GIMT_Encode2(GIFBS_isGFX9Plus),
        GIM_CheckPointerToAny, /*MI*/0, /*Op*/1, /*SizeInBits*/0,
        GIM_CheckComplexPattern, /*MI*/0, /*Op*/1, /*Renderer*/GIMT_Encode2(0), GIMT_Encode2(GICP_gi_smrd_sgpr_imm),
        // (ld:{ *:[v8f32] } (SMRDSgprImm:{ *:[iPTR] } i64:{ *:[i64] }:$sbase, i32:{ *:[i32] }:$soffset, i32:{ *:[i32] }:$offset))<<P:Predicate_unindexedload>><<P:Predicate_load>><<P:Predicate_smrd_load>>  =>  (S_LOAD_DWORDX8_SGPR_IMM:{ *:[v8f32] } ?:{ *:[i64] }:$sbase, ?:{ *:[i32] }:$soffset, ?:{ *:[i32] }:$offset, 0:{ *:[i32] })
        GIR_BuildMI, /*InsnID*/0, /*Opcode*/GIMT_Encode2(AMDGPU::S_LOAD_DWORDX8_SGPR_IMM),
        GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/0, // DstI[sdst]
        GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/0, // sbase
        GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/1, // soffset
        GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/2, // offset
        GIR_AddImm8, /*InsnID*/0, /*Imm*/0,
        GIR_MergeMemOperands, /*InsnID*/0, /*NumInsns*/1, /*MergeInsnID's*/0,
        GIR_ConstrainSelectedInstOperands, /*InsnID*/0,
        GIR_EraseFromParent, /*InsnID*/0,
        // GIR_Coverage, 2610,
        GIR_Done,
      // Label 1605: @106426
      GIM_Try, /*On fail goto*//*Label 1606*/ GIMT_Encode4(106472), // Rule ID 2600 //
        GIM_CheckPointerToAny, /*MI*/0, /*Op*/1, /*SizeInBits*/0,
        GIM_CheckComplexPattern, /*MI*/0, /*Op*/1, /*Renderer*/GIMT_Encode2(0), GIMT_Encode2(GICP_gi_smrd_imm),
        // (ld:{ *:[v8i32] } (SMRDImm:{ *:[iPTR] } i64:{ *:[i64] }:$sbase, i32:{ *:[i32] }:$offset))<<P:Predicate_unindexedload>><<P:Predicate_load>><<P:Predicate_smrd_load>>  =>  (S_LOAD_DWORDX8_IMM:{ *:[v8i32] } ?:{ *:[i64] }:$sbase, ?:{ *:[i32] }:$offset, 0:{ *:[i32] })
        GIR_BuildMI, /*InsnID*/0, /*Opcode*/GIMT_Encode2(AMDGPU::S_LOAD_DWORDX8_IMM),
        GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/0, // DstI[sdst]
        GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/0, // sbase
        GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/1, // offset
        GIR_AddImm8, /*InsnID*/0, /*Imm*/0,
        GIR_MergeMemOperands, /*InsnID*/0, /*NumInsns*/1, /*MergeInsnID's*/0,
        GIR_ConstrainSelectedInstOperands, /*InsnID*/0,
        GIR_EraseFromParent, /*InsnID*/0,
        // GIR_Coverage, 2600,
        GIR_Done,
      // Label 1606: @106472
      GIM_Try, /*On fail goto*//*Label 1607*/ GIMT_Encode4(106521), // Rule ID 2601 //
        GIM_CheckFeatures, GIMT_Encode2(GIFBS_isGFX7Only),
        GIM_CheckPointerToAny, /*MI*/0, /*Op*/1, /*SizeInBits*/0,
        GIM_CheckComplexPattern, /*MI*/0, /*Op*/1, /*Renderer*/GIMT_Encode2(0), GIMT_Encode2(GICP_gi_smrd_imm32),
        // (ld:{ *:[v8i32] } (SMRDImm32:{ *:[iPTR] } i64:{ *:[i64] }:$sbase, i32:{ *:[i32] }:$offset))<<P:Predicate_unindexedload>><<P:Predicate_load>><<P:Predicate_smrd_load>>  =>  (S_LOAD_DWORDX8_IMM_ci:{ *:[v8i32] } ?:{ *:[i64] }:$sbase, ?:{ *:[i32] }:$offset, 0:{ *:[i32] })
        GIR_BuildMI, /*InsnID*/0, /*Opcode*/GIMT_Encode2(AMDGPU::S_LOAD_DWORDX8_IMM_ci),
        GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/0, // DstI[sdst]
        GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/0, // sbase
        GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/1, // offset
        GIR_AddImm8, /*InsnID*/0, /*Imm*/0,
        GIR_MergeMemOperands, /*InsnID*/0, /*NumInsns*/1, /*MergeInsnID's*/0,
        GIR_ConstrainSelectedInstOperands, /*InsnID*/0,
        GIR_EraseFromParent, /*InsnID*/0,
        // GIR_Coverage, 2601,
        GIR_Done,
      // Label 1607: @106521
      GIM_Try, /*On fail goto*//*Label 1608*/ GIMT_Encode4(106570), // Rule ID 2602 //
        GIM_CheckFeatures, GIMT_Encode2(GIFBS_isNotGFX9Plus),
        GIM_CheckPointerToAny, /*MI*/0, /*Op*/1, /*SizeInBits*/0,
        GIM_CheckComplexPattern, /*MI*/0, /*Op*/1, /*Renderer*/GIMT_Encode2(0), GIMT_Encode2(GICP_gi_smrd_sgpr),
        // (ld:{ *:[v8i32] } (SMRDSgpr:{ *:[iPTR] } i64:{ *:[i64] }:$sbase, i32:{ *:[i32] }:$soffset))<<P:Predicate_unindexedload>><<P:Predicate_load>><<P:Predicate_smrd_load>>  =>  (S_LOAD_DWORDX8_SGPR:{ *:[v8i32] } ?:{ *:[i64] }:$sbase, ?:{ *:[i32] }:$soffset, 0:{ *:[i32] })
        GIR_BuildMI, /*InsnID*/0, /*Opcode*/GIMT_Encode2(AMDGPU::S_LOAD_DWORDX8_SGPR),
        GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/0, // DstI[sdst]
        GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/0, // sbase
        GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/1, // soffset
        GIR_AddImm8, /*InsnID*/0, /*Imm*/0,
        GIR_MergeMemOperands, /*InsnID*/0, /*NumInsns*/1, /*MergeInsnID's*/0,
        GIR_ConstrainSelectedInstOperands, /*InsnID*/0,
        GIR_EraseFromParent, /*InsnID*/0,
        // GIR_Coverage, 2602,
        GIR_Done,
      // Label 1608: @106570
      GIM_Try, /*On fail goto*//*Label 1609*/ GIMT_Encode4(106622), // Rule ID 2603 //
        GIM_CheckFeatures, GIMT_Encode2(GIFBS_isGFX9Plus),
        GIM_CheckPointerToAny, /*MI*/0, /*Op*/1, /*SizeInBits*/0,
        GIM_CheckComplexPattern, /*MI*/0, /*Op*/1, /*Renderer*/GIMT_Encode2(0), GIMT_Encode2(GICP_gi_smrd_sgpr),
        // (ld:{ *:[v8i32] } (SMRDSgpr:{ *:[iPTR] } i64:{ *:[i64] }:$sbase, i32:{ *:[i32] }:$soffset))<<P:Predicate_unindexedload>><<P:Predicate_load>><<P:Predicate_smrd_load>>  =>  (S_LOAD_DWORDX8_SGPR_IMM:{ *:[v8i32] } ?:{ *:[i64] }:$sbase, ?:{ *:[i32] }:$soffset, 0:{ *:[i32] }, 0:{ *:[i32] })
        GIR_BuildMI, /*InsnID*/0, /*Opcode*/GIMT_Encode2(AMDGPU::S_LOAD_DWORDX8_SGPR_IMM),
        GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/0, // DstI[sdst]
        GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/0, // sbase
        GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/1, // soffset
        GIR_AddImm8, /*InsnID*/0, /*Imm*/0,
        GIR_AddImm8, /*InsnID*/0, /*Imm*/0,
        GIR_MergeMemOperands, /*InsnID*/0, /*NumInsns*/1, /*MergeInsnID's*/0,
        GIR_ConstrainSelectedInstOperands, /*InsnID*/0,
        GIR_EraseFromParent, /*InsnID*/0,
        // GIR_Coverage, 2603,
        GIR_Done,
      // Label 1609: @106622
      GIM_Try, /*On fail goto*//*Label 1610*/ GIMT_Encode4(106668), // Rule ID 2606 //
        GIM_CheckPointerToAny, /*MI*/0, /*Op*/1, /*SizeInBits*/0,
        GIM_CheckComplexPattern, /*MI*/0, /*Op*/1, /*Renderer*/GIMT_Encode2(0), GIMT_Encode2(GICP_gi_smrd_imm),
        // (ld:{ *:[v8f32] } (SMRDImm:{ *:[iPTR] } i64:{ *:[i64] }:$sbase, i32:{ *:[i32] }:$offset))<<P:Predicate_unindexedload>><<P:Predicate_load>><<P:Predicate_smrd_load>>  =>  (S_LOAD_DWORDX8_IMM:{ *:[v8f32] } ?:{ *:[i64] }:$sbase, ?:{ *:[i32] }:$offset, 0:{ *:[i32] })
        GIR_BuildMI, /*InsnID*/0, /*Opcode*/GIMT_Encode2(AMDGPU::S_LOAD_DWORDX8_IMM),
        GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/0, // DstI[sdst]
        GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/0, // sbase
        GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/1, // offset
        GIR_AddImm8, /*InsnID*/0, /*Imm*/0,
        GIR_MergeMemOperands, /*InsnID*/0, /*NumInsns*/1, /*MergeInsnID's*/0,
        GIR_ConstrainSelectedInstOperands, /*InsnID*/0,
        GIR_EraseFromParent, /*InsnID*/0,
        // GIR_Coverage, 2606,
        GIR_Done,
      // Label 1610: @106668
      GIM_Try, /*On fail goto*//*Label 1611*/ GIMT_Encode4(106717), // Rule ID 2607 //
        GIM_CheckFeatures, GIMT_Encode2(GIFBS_isGFX7Only),
        GIM_CheckPointerToAny, /*MI*/0, /*Op*/1, /*SizeInBits*/0,
        GIM_CheckComplexPattern, /*MI*/0, /*Op*/1, /*Renderer*/GIMT_Encode2(0), GIMT_Encode2(GICP_gi_smrd_imm32),
        // (ld:{ *:[v8f32] } (SMRDImm32:{ *:[iPTR] } i64:{ *:[i64] }:$sbase, i32:{ *:[i32] }:$offset))<<P:Predicate_unindexedload>><<P:Predicate_load>><<P:Predicate_smrd_load>>  =>  (S_LOAD_DWORDX8_IMM_ci:{ *:[v8f32] } ?:{ *:[i64] }:$sbase, ?:{ *:[i32] }:$offset, 0:{ *:[i32] })
        GIR_BuildMI, /*InsnID*/0, /*Opcode*/GIMT_Encode2(AMDGPU::S_LOAD_DWORDX8_IMM_ci),
        GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/0, // DstI[sdst]
        GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/0, // sbase
        GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/1, // offset
        GIR_AddImm8, /*InsnID*/0, /*Imm*/0,
        GIR_MergeMemOperands, /*InsnID*/0, /*NumInsns*/1, /*MergeInsnID's*/0,
        GIR_ConstrainSelectedInstOperands, /*InsnID*/0,
        GIR_EraseFromParent, /*InsnID*/0,
        // GIR_Coverage, 2607,
        GIR_Done,
      // Label 1611: @106717
      GIM_Try, /*On fail goto*//*Label 1612*/ GIMT_Encode4(106766), // Rule ID 2608 //
        GIM_CheckFeatures, GIMT_Encode2(GIFBS_isNotGFX9Plus),
        GIM_CheckPointerToAny, /*MI*/0, /*Op*/1, /*SizeInBits*/0,
        GIM_CheckComplexPattern, /*MI*/0, /*Op*/1, /*Renderer*/GIMT_Encode2(0), GIMT_Encode2(GICP_gi_smrd_sgpr),
        // (ld:{ *:[v8f32] } (SMRDSgpr:{ *:[iPTR] } i64:{ *:[i64] }:$sbase, i32:{ *:[i32] }:$soffset))<<P:Predicate_unindexedload>><<P:Predicate_load>><<P:Predicate_smrd_load>>  =>  (S_LOAD_DWORDX8_SGPR:{ *:[v8f32] } ?:{ *:[i64] }:$sbase, ?:{ *:[i32] }:$soffset, 0:{ *:[i32] })
        GIR_BuildMI, /*InsnID*/0, /*Opcode*/GIMT_Encode2(AMDGPU::S_LOAD_DWORDX8_SGPR),
        GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/0, // DstI[sdst]
        GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/0, // sbase
        GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/1, // soffset
        GIR_AddImm8, /*InsnID*/0, /*Imm*/0,
        GIR_MergeMemOperands, /*InsnID*/0, /*NumInsns*/1, /*MergeInsnID's*/0,
        GIR_ConstrainSelectedInstOperands, /*InsnID*/0,
        GIR_EraseFromParent, /*InsnID*/0,
        // GIR_Coverage, 2608,
        GIR_Done,
      // Label 1612: @106766
      GIM_Try, /*On fail goto*//*Label 1613*/ GIMT_Encode4(106818), // Rule ID 2609 //
        GIM_CheckFeatures, GIMT_Encode2(GIFBS_isGFX9Plus),
        GIM_CheckPointerToAny, /*MI*/0, /*Op*/1, /*SizeInBits*/0,
        GIM_CheckComplexPattern, /*MI*/0, /*Op*/1, /*Renderer*/GIMT_Encode2(0), GIMT_Encode2(GICP_gi_smrd_sgpr),
        // (ld:{ *:[v8f32] } (SMRDSgpr:{ *:[iPTR] } i64:{ *:[i64] }:$sbase, i32:{ *:[i32] }:$soffset))<<P:Predicate_unindexedload>><<P:Predicate_load>><<P:Predicate_smrd_load>>  =>  (S_LOAD_DWORDX8_SGPR_IMM:{ *:[v8f32] } ?:{ *:[i64] }:$sbase, ?:{ *:[i32] }:$soffset, 0:{ *:[i32] }, 0:{ *:[i32] })
        GIR_BuildMI, /*InsnID*/0, /*Opcode*/GIMT_Encode2(AMDGPU::S_LOAD_DWORDX8_SGPR_IMM),
        GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/0, // DstI[sdst]
        GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/0, // sbase
        GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/1, // soffset
        GIR_AddImm8, /*InsnID*/0, /*Imm*/0,
        GIR_AddImm8, /*InsnID*/0, /*Imm*/0,
        GIR_MergeMemOperands, /*InsnID*/0, /*NumInsns*/1, /*MergeInsnID's*/0,
        GIR_ConstrainSelectedInstOperands, /*InsnID*/0,
        GIR_EraseFromParent, /*InsnID*/0,
        // GIR_Coverage, 2609,
        GIR_Done,
      // Label 1613: @106818
      GIM_Try, /*On fail goto*//*Label 1614*/ GIMT_Encode4(106859), // Rule ID 2605 //
        // MIs[0] sbase
        GIM_CheckPointerToAny, /*MI*/0, /*Op*/1, /*SizeInBits*/64,
        GIM_CheckRegBankForClass, /*MI*/0, /*Op*/1, /*RC*/GIMT_Encode2(AMDGPU::SReg_64RegClassID),
        // (ld:{ *:[v8i32] } SReg_64:{ *:[i64] }:$sbase)<<P:Predicate_unindexedload>><<P:Predicate_load>><<P:Predicate_smrd_load>>  =>  (S_LOAD_DWORDX8_IMM:{ *:[v8i32] } i64:{ *:[i64] }:$sbase, 0:{ *:[i32] }, 0:{ *:[i32] })
        GIR_BuildMI, /*InsnID*/0, /*Opcode*/GIMT_Encode2(AMDGPU::S_LOAD_DWORDX8_IMM),
        GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/0, // DstI[sdst]
        GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/1, // sbase
        GIR_AddImm8, /*InsnID*/0, /*Imm*/0,
        GIR_AddImm8, /*InsnID*/0, /*Imm*/0,
        GIR_MergeMemOperands, /*InsnID*/0, /*NumInsns*/1, /*MergeInsnID's*/0,
        GIR_ConstrainSelectedInstOperands, /*InsnID*/0,
        GIR_EraseFromParent, /*InsnID*/0,
        // GIR_Coverage, 2605,
        GIR_Done,
      // Label 1614: @106859
      GIM_Try, /*On fail goto*//*Label 1615*/ GIMT_Encode4(106900), // Rule ID 2611 //
        // MIs[0] sbase
        GIM_CheckPointerToAny, /*MI*/0, /*Op*/1, /*SizeInBits*/64,
        GIM_CheckRegBankForClass, /*MI*/0, /*Op*/1, /*RC*/GIMT_Encode2(AMDGPU::SReg_64RegClassID),
        // (ld:{ *:[v8f32] } SReg_64:{ *:[i64] }:$sbase)<<P:Predicate_unindexedload>><<P:Predicate_load>><<P:Predicate_smrd_load>>  =>  (S_LOAD_DWORDX8_IMM:{ *:[v8f32] } i64:{ *:[i64] }:$sbase, 0:{ *:[i32] }, 0:{ *:[i32] })
        GIR_BuildMI, /*InsnID*/0, /*Opcode*/GIMT_Encode2(AMDGPU::S_LOAD_DWORDX8_IMM),
        GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/0, // DstI[sdst]
        GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/1, // sbase
        GIR_AddImm8, /*InsnID*/0, /*Imm*/0,
        GIR_AddImm8, /*InsnID*/0, /*Imm*/0,
        GIR_MergeMemOperands, /*InsnID*/0, /*NumInsns*/1, /*MergeInsnID's*/0,
        GIR_ConstrainSelectedInstOperands, /*InsnID*/0,
        GIR_EraseFromParent, /*InsnID*/0,
        // GIR_Coverage, 2611,
        GIR_Done,
      // Label 1615: @106900
      GIM_Reject,
    // Label 1603: @106901
    GIM_Reject,
    // Label 836: @106902
    GIM_Try, /*On fail goto*//*Label 1616*/ GIMT_Encode4(107506),
      GIM_CheckMemorySizeEqualToLLT, /*MI*/0, /*MMO*/0, /*OpIdx*/0,
      GIM_CheckCxxInsnPredicate, /*MI*/0, /*FnId*/GIMT_Encode2(GICXXPred_MI_Predicate_smrd_load),
      GIM_CheckAtomicOrdering, /*MI*/0, /*Order*/(uint8_t)AtomicOrdering::NotAtomic,
      GIM_CheckRegBankForClass, /*MI*/0, /*Op*/0, /*RC*/GIMT_Encode2(AMDGPU::SReg_512RegClassID),
      GIM_Try, /*On fail goto*//*Label 1617*/ GIMT_Encode4(106977), // Rule ID 2658 //
        GIM_CheckFeatures, GIMT_Encode2(GIFBS_isGFX9Plus),
        GIM_CheckPointerToAny, /*MI*/0, /*Op*/1, /*SizeInBits*/0,
        GIM_CheckComplexPattern, /*MI*/0, /*Op*/1, /*Renderer*/GIMT_Encode2(0), GIMT_Encode2(GICP_gi_smrd_sgpr_imm),
        // (ld:{ *:[v8i64] } (SMRDSgprImm:{ *:[iPTR] } i64:{ *:[i64] }:$sbase, i32:{ *:[i32] }:$soffset, i32:{ *:[i32] }:$offset))<<P:Predicate_unindexedload>><<P:Predicate_load>><<P:Predicate_smrd_load>>  =>  (S_LOAD_DWORDX16_SGPR_IMM:{ *:[v8i64] } ?:{ *:[i64] }:$sbase, ?:{ *:[i32] }:$soffset, ?:{ *:[i32] }:$offset, 0:{ *:[i32] })
        GIR_BuildMI, /*InsnID*/0, /*Opcode*/GIMT_Encode2(AMDGPU::S_LOAD_DWORDX16_SGPR_IMM),
        GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/0, // DstI[sdst]
        GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/0, // sbase
        GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/1, // soffset
        GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/2, // offset
        GIR_AddImm8, /*InsnID*/0, /*Imm*/0,
        GIR_MergeMemOperands, /*InsnID*/0, /*NumInsns*/1, /*MergeInsnID's*/0,
        GIR_ConstrainSelectedInstOperands, /*InsnID*/0,
        GIR_EraseFromParent, /*InsnID*/0,
        // GIR_Coverage, 2658,
        GIR_Done,
      // Label 1617: @106977
      GIM_Try, /*On fail goto*//*Label 1618*/ GIMT_Encode4(107031), // Rule ID 2664 //
        GIM_CheckFeatures, GIMT_Encode2(GIFBS_isGFX9Plus),
        GIM_CheckPointerToAny, /*MI*/0, /*Op*/1, /*SizeInBits*/0,
        GIM_CheckComplexPattern, /*MI*/0, /*Op*/1, /*Renderer*/GIMT_Encode2(0), GIMT_Encode2(GICP_gi_smrd_sgpr_imm),
        // (ld:{ *:[v8f64] } (SMRDSgprImm:{ *:[iPTR] } i64:{ *:[i64] }:$sbase, i32:{ *:[i32] }:$soffset, i32:{ *:[i32] }:$offset))<<P:Predicate_unindexedload>><<P:Predicate_load>><<P:Predicate_smrd_load>>  =>  (S_LOAD_DWORDX16_SGPR_IMM:{ *:[v8f64] } ?:{ *:[i64] }:$sbase, ?:{ *:[i32] }:$soffset, ?:{ *:[i32] }:$offset, 0:{ *:[i32] })
        GIR_BuildMI, /*InsnID*/0, /*Opcode*/GIMT_Encode2(AMDGPU::S_LOAD_DWORDX16_SGPR_IMM),
        GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/0, // DstI[sdst]
        GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/0, // sbase
        GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/1, // soffset
        GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/2, // offset
        GIR_AddImm8, /*InsnID*/0, /*Imm*/0,
        GIR_MergeMemOperands, /*InsnID*/0, /*NumInsns*/1, /*MergeInsnID's*/0,
        GIR_ConstrainSelectedInstOperands, /*InsnID*/0,
        GIR_EraseFromParent, /*InsnID*/0,
        // GIR_Coverage, 2664,
        GIR_Done,
      // Label 1618: @107031
      GIM_Try, /*On fail goto*//*Label 1619*/ GIMT_Encode4(107077), // Rule ID 2654 //
        GIM_CheckPointerToAny, /*MI*/0, /*Op*/1, /*SizeInBits*/0,
        GIM_CheckComplexPattern, /*MI*/0, /*Op*/1, /*Renderer*/GIMT_Encode2(0), GIMT_Encode2(GICP_gi_smrd_imm),
        // (ld:{ *:[v8i64] } (SMRDImm:{ *:[iPTR] } i64:{ *:[i64] }:$sbase, i32:{ *:[i32] }:$offset))<<P:Predicate_unindexedload>><<P:Predicate_load>><<P:Predicate_smrd_load>>  =>  (S_LOAD_DWORDX16_IMM:{ *:[v8i64] } ?:{ *:[i64] }:$sbase, ?:{ *:[i32] }:$offset, 0:{ *:[i32] })
        GIR_BuildMI, /*InsnID*/0, /*Opcode*/GIMT_Encode2(AMDGPU::S_LOAD_DWORDX16_IMM),
        GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/0, // DstI[sdst]
        GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/0, // sbase
        GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/1, // offset
        GIR_AddImm8, /*InsnID*/0, /*Imm*/0,
        GIR_MergeMemOperands, /*InsnID*/0, /*NumInsns*/1, /*MergeInsnID's*/0,
        GIR_ConstrainSelectedInstOperands, /*InsnID*/0,
        GIR_EraseFromParent, /*InsnID*/0,
        // GIR_Coverage, 2654,
        GIR_Done,
      // Label 1619: @107077
      GIM_Try, /*On fail goto*//*Label 1620*/ GIMT_Encode4(107126), // Rule ID 2655 //
        GIM_CheckFeatures, GIMT_Encode2(GIFBS_isGFX7Only),
        GIM_CheckPointerToAny, /*MI*/0, /*Op*/1, /*SizeInBits*/0,
        GIM_CheckComplexPattern, /*MI*/0, /*Op*/1, /*Renderer*/GIMT_Encode2(0), GIMT_Encode2(GICP_gi_smrd_imm32),
        // (ld:{ *:[v8i64] } (SMRDImm32:{ *:[iPTR] } i64:{ *:[i64] }:$sbase, i32:{ *:[i32] }:$offset))<<P:Predicate_unindexedload>><<P:Predicate_load>><<P:Predicate_smrd_load>>  =>  (S_LOAD_DWORDX16_IMM_ci:{ *:[v8i64] } ?:{ *:[i64] }:$sbase, ?:{ *:[i32] }:$offset, 0:{ *:[i32] })
        GIR_BuildMI, /*InsnID*/0, /*Opcode*/GIMT_Encode2(AMDGPU::S_LOAD_DWORDX16_IMM_ci),
        GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/0, // DstI[sdst]
        GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/0, // sbase
        GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/1, // offset
        GIR_AddImm8, /*InsnID*/0, /*Imm*/0,
        GIR_MergeMemOperands, /*InsnID*/0, /*NumInsns*/1, /*MergeInsnID's*/0,
        GIR_ConstrainSelectedInstOperands, /*InsnID*/0,
        GIR_EraseFromParent, /*InsnID*/0,
        // GIR_Coverage, 2655,
        GIR_Done,
      // Label 1620: @107126
      GIM_Try, /*On fail goto*//*Label 1621*/ GIMT_Encode4(107175), // Rule ID 2656 //
        GIM_CheckFeatures, GIMT_Encode2(GIFBS_isNotGFX9Plus),
        GIM_CheckPointerToAny, /*MI*/0, /*Op*/1, /*SizeInBits*/0,
        GIM_CheckComplexPattern, /*MI*/0, /*Op*/1, /*Renderer*/GIMT_Encode2(0), GIMT_Encode2(GICP_gi_smrd_sgpr),
        // (ld:{ *:[v8i64] } (SMRDSgpr:{ *:[iPTR] } i64:{ *:[i64] }:$sbase, i32:{ *:[i32] }:$soffset))<<P:Predicate_unindexedload>><<P:Predicate_load>><<P:Predicate_smrd_load>>  =>  (S_LOAD_DWORDX16_SGPR:{ *:[v8i64] } ?:{ *:[i64] }:$sbase, ?:{ *:[i32] }:$soffset, 0:{ *:[i32] })
        GIR_BuildMI, /*InsnID*/0, /*Opcode*/GIMT_Encode2(AMDGPU::S_LOAD_DWORDX16_SGPR),
        GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/0, // DstI[sdst]
        GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/0, // sbase
        GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/1, // soffset
        GIR_AddImm8, /*InsnID*/0, /*Imm*/0,
        GIR_MergeMemOperands, /*InsnID*/0, /*NumInsns*/1, /*MergeInsnID's*/0,
        GIR_ConstrainSelectedInstOperands, /*InsnID*/0,
        GIR_EraseFromParent, /*InsnID*/0,
        // GIR_Coverage, 2656,
        GIR_Done,
      // Label 1621: @107175
      GIM_Try, /*On fail goto*//*Label 1622*/ GIMT_Encode4(107227), // Rule ID 2657 //
        GIM_CheckFeatures, GIMT_Encode2(GIFBS_isGFX9Plus),
        GIM_CheckPointerToAny, /*MI*/0, /*Op*/1, /*SizeInBits*/0,
        GIM_CheckComplexPattern, /*MI*/0, /*Op*/1, /*Renderer*/GIMT_Encode2(0), GIMT_Encode2(GICP_gi_smrd_sgpr),
        // (ld:{ *:[v8i64] } (SMRDSgpr:{ *:[iPTR] } i64:{ *:[i64] }:$sbase, i32:{ *:[i32] }:$soffset))<<P:Predicate_unindexedload>><<P:Predicate_load>><<P:Predicate_smrd_load>>  =>  (S_LOAD_DWORDX16_SGPR_IMM:{ *:[v8i64] } ?:{ *:[i64] }:$sbase, ?:{ *:[i32] }:$soffset, 0:{ *:[i32] }, 0:{ *:[i32] })
        GIR_BuildMI, /*InsnID*/0, /*Opcode*/GIMT_Encode2(AMDGPU::S_LOAD_DWORDX16_SGPR_IMM),
        GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/0, // DstI[sdst]
        GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/0, // sbase
        GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/1, // soffset
        GIR_AddImm8, /*InsnID*/0, /*Imm*/0,
        GIR_AddImm8, /*InsnID*/0, /*Imm*/0,
        GIR_MergeMemOperands, /*InsnID*/0, /*NumInsns*/1, /*MergeInsnID's*/0,
        GIR_ConstrainSelectedInstOperands, /*InsnID*/0,
        GIR_EraseFromParent, /*InsnID*/0,
        // GIR_Coverage, 2657,
        GIR_Done,
      // Label 1622: @107227
      GIM_Try, /*On fail goto*//*Label 1623*/ GIMT_Encode4(107273), // Rule ID 2660 //
        GIM_CheckPointerToAny, /*MI*/0, /*Op*/1, /*SizeInBits*/0,
        GIM_CheckComplexPattern, /*MI*/0, /*Op*/1, /*Renderer*/GIMT_Encode2(0), GIMT_Encode2(GICP_gi_smrd_imm),
        // (ld:{ *:[v8f64] } (SMRDImm:{ *:[iPTR] } i64:{ *:[i64] }:$sbase, i32:{ *:[i32] }:$offset))<<P:Predicate_unindexedload>><<P:Predicate_load>><<P:Predicate_smrd_load>>  =>  (S_LOAD_DWORDX16_IMM:{ *:[v8f64] } ?:{ *:[i64] }:$sbase, ?:{ *:[i32] }:$offset, 0:{ *:[i32] })
        GIR_BuildMI, /*InsnID*/0, /*Opcode*/GIMT_Encode2(AMDGPU::S_LOAD_DWORDX16_IMM),
        GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/0, // DstI[sdst]
        GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/0, // sbase
        GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/1, // offset
        GIR_AddImm8, /*InsnID*/0, /*Imm*/0,
        GIR_MergeMemOperands, /*InsnID*/0, /*NumInsns*/1, /*MergeInsnID's*/0,
        GIR_ConstrainSelectedInstOperands, /*InsnID*/0,
        GIR_EraseFromParent, /*InsnID*/0,
        // GIR_Coverage, 2660,
        GIR_Done,
      // Label 1623: @107273
      GIM_Try, /*On fail goto*//*Label 1624*/ GIMT_Encode4(107322), // Rule ID 2661 //
        GIM_CheckFeatures, GIMT_Encode2(GIFBS_isGFX7Only),
        GIM_CheckPointerToAny, /*MI*/0, /*Op*/1, /*SizeInBits*/0,
        GIM_CheckComplexPattern, /*MI*/0, /*Op*/1, /*Renderer*/GIMT_Encode2(0), GIMT_Encode2(GICP_gi_smrd_imm32),
        // (ld:{ *:[v8f64] } (SMRDImm32:{ *:[iPTR] } i64:{ *:[i64] }:$sbase, i32:{ *:[i32] }:$offset))<<P:Predicate_unindexedload>><<P:Predicate_load>><<P:Predicate_smrd_load>>  =>  (S_LOAD_DWORDX16_IMM_ci:{ *:[v8f64] } ?:{ *:[i64] }:$sbase, ?:{ *:[i32] }:$offset, 0:{ *:[i32] })
        GIR_BuildMI, /*InsnID*/0, /*Opcode*/GIMT_Encode2(AMDGPU::S_LOAD_DWORDX16_IMM_ci),
        GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/0, // DstI[sdst]
        GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/0, // sbase
        GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/1, // offset
        GIR_AddImm8, /*InsnID*/0, /*Imm*/0,
        GIR_MergeMemOperands, /*InsnID*/0, /*NumInsns*/1, /*MergeInsnID's*/0,
        GIR_ConstrainSelectedInstOperands, /*InsnID*/0,
        GIR_EraseFromParent, /*InsnID*/0,
        // GIR_Coverage, 2661,
        GIR_Done,
      // Label 1624: @107322
      GIM_Try, /*On fail goto*//*Label 1625*/ GIMT_Encode4(107371), // Rule ID 2662 //
        GIM_CheckFeatures, GIMT_Encode2(GIFBS_isNotGFX9Plus),
        GIM_CheckPointerToAny, /*MI*/0, /*Op*/1, /*SizeInBits*/0,
        GIM_CheckComplexPattern, /*MI*/0, /*Op*/1, /*Renderer*/GIMT_Encode2(0), GIMT_Encode2(GICP_gi_smrd_sgpr),
        // (ld:{ *:[v8f64] } (SMRDSgpr:{ *:[iPTR] } i64:{ *:[i64] }:$sbase, i32:{ *:[i32] }:$soffset))<<P:Predicate_unindexedload>><<P:Predicate_load>><<P:Predicate_smrd_load>>  =>  (S_LOAD_DWORDX16_SGPR:{ *:[v8f64] } ?:{ *:[i64] }:$sbase, ?:{ *:[i32] }:$soffset, 0:{ *:[i32] })
        GIR_BuildMI, /*InsnID*/0, /*Opcode*/GIMT_Encode2(AMDGPU::S_LOAD_DWORDX16_SGPR),
        GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/0, // DstI[sdst]
        GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/0, // sbase
        GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/1, // soffset
        GIR_AddImm8, /*InsnID*/0, /*Imm*/0,
        GIR_MergeMemOperands, /*InsnID*/0, /*NumInsns*/1, /*MergeInsnID's*/0,
        GIR_ConstrainSelectedInstOperands, /*InsnID*/0,
        GIR_EraseFromParent, /*InsnID*/0,
        // GIR_Coverage, 2662,
        GIR_Done,
      // Label 1625: @107371
      GIM_Try, /*On fail goto*//*Label 1626*/ GIMT_Encode4(107423), // Rule ID 2663 //
        GIM_CheckFeatures, GIMT_Encode2(GIFBS_isGFX9Plus),
        GIM_CheckPointerToAny, /*MI*/0, /*Op*/1, /*SizeInBits*/0,
        GIM_CheckComplexPattern, /*MI*/0, /*Op*/1, /*Renderer*/GIMT_Encode2(0), GIMT_Encode2(GICP_gi_smrd_sgpr),
        // (ld:{ *:[v8f64] } (SMRDSgpr:{ *:[iPTR] } i64:{ *:[i64] }:$sbase, i32:{ *:[i32] }:$soffset))<<P:Predicate_unindexedload>><<P:Predicate_load>><<P:Predicate_smrd_load>>  =>  (S_LOAD_DWORDX16_SGPR_IMM:{ *:[v8f64] } ?:{ *:[i64] }:$sbase, ?:{ *:[i32] }:$soffset, 0:{ *:[i32] }, 0:{ *:[i32] })
        GIR_BuildMI, /*InsnID*/0, /*Opcode*/GIMT_Encode2(AMDGPU::S_LOAD_DWORDX16_SGPR_IMM),
        GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/0, // DstI[sdst]
        GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/0, // sbase
        GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/1, // soffset
        GIR_AddImm8, /*InsnID*/0, /*Imm*/0,
        GIR_AddImm8, /*InsnID*/0, /*Imm*/0,
        GIR_MergeMemOperands, /*InsnID*/0, /*NumInsns*/1, /*MergeInsnID's*/0,
        GIR_ConstrainSelectedInstOperands, /*InsnID*/0,
        GIR_EraseFromParent, /*InsnID*/0,
        // GIR_Coverage, 2663,
        GIR_Done,
      // Label 1626: @107423
      GIM_Try, /*On fail goto*//*Label 1627*/ GIMT_Encode4(107464), // Rule ID 2659 //
        // MIs[0] sbase
        GIM_CheckPointerToAny, /*MI*/0, /*Op*/1, /*SizeInBits*/64,
        GIM_CheckRegBankForClass, /*MI*/0, /*Op*/1, /*RC*/GIMT_Encode2(AMDGPU::SReg_64RegClassID),
        // (ld:{ *:[v8i64] } SReg_64:{ *:[i64] }:$sbase)<<P:Predicate_unindexedload>><<P:Predicate_load>><<P:Predicate_smrd_load>>  =>  (S_LOAD_DWORDX16_IMM:{ *:[v8i64] } i64:{ *:[i64] }:$sbase, 0:{ *:[i32] }, 0:{ *:[i32] })
        GIR_BuildMI, /*InsnID*/0, /*Opcode*/GIMT_Encode2(AMDGPU::S_LOAD_DWORDX16_IMM),
        GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/0, // DstI[sdst]
        GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/1, // sbase
        GIR_AddImm8, /*InsnID*/0, /*Imm*/0,
        GIR_AddImm8, /*InsnID*/0, /*Imm*/0,
        GIR_MergeMemOperands, /*InsnID*/0, /*NumInsns*/1, /*MergeInsnID's*/0,
        GIR_ConstrainSelectedInstOperands, /*InsnID*/0,
        GIR_EraseFromParent, /*InsnID*/0,
        // GIR_Coverage, 2659,
        GIR_Done,
      // Label 1627: @107464
      GIM_Try, /*On fail goto*//*Label 1628*/ GIMT_Encode4(107505), // Rule ID 2665 //
        // MIs[0] sbase
        GIM_CheckPointerToAny, /*MI*/0, /*Op*/1, /*SizeInBits*/64,
        GIM_CheckRegBankForClass, /*MI*/0, /*Op*/1, /*RC*/GIMT_Encode2(AMDGPU::SReg_64RegClassID),
        // (ld:{ *:[v8f64] } SReg_64:{ *:[i64] }:$sbase)<<P:Predicate_unindexedload>><<P:Predicate_load>><<P:Predicate_smrd_load>>  =>  (S_LOAD_DWORDX16_IMM:{ *:[v8f64] } i64:{ *:[i64] }:$sbase, 0:{ *:[i32] }, 0:{ *:[i32] })
        GIR_BuildMI, /*InsnID*/0, /*Opcode*/GIMT_Encode2(AMDGPU::S_LOAD_DWORDX16_IMM),
        GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/0, // DstI[sdst]
        GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/1, // sbase
        GIR_AddImm8, /*InsnID*/0, /*Imm*/0,
        GIR_AddImm8, /*InsnID*/0, /*Imm*/0,
        GIR_MergeMemOperands, /*InsnID*/0, /*NumInsns*/1, /*MergeInsnID's*/0,
        GIR_ConstrainSelectedInstOperands, /*InsnID*/0,
        GIR_EraseFromParent, /*InsnID*/0,
        // GIR_Coverage, 2665,
        GIR_Done,
      // Label 1628: @107505
      GIM_Reject,
    // Label 1616: @107506
    GIM_Reject,
    // Label 837: @107507
    GIM_Try, /*On fail goto*//*Label 1629*/ GIMT_Encode4(108402),
      GIM_CheckMemorySizeEqualToLLT, /*MI*/0, /*MMO*/0, /*OpIdx*/0,
      GIM_CheckCxxInsnPredicate, /*MI*/0, /*FnId*/GIMT_Encode2(GICXXPred_MI_Predicate_smrd_load),
      GIM_CheckAtomicOrdering, /*MI*/0, /*Order*/(uint8_t)AtomicOrdering::NotAtomic,
      GIM_CheckRegBankForClass, /*MI*/0, /*Op*/0, /*RC*/GIMT_Encode2(AMDGPU::SReg_256RegClassID),
      GIM_Try, /*On fail goto*//*Label 1630*/ GIMT_Encode4(107582), // Rule ID 2628 //
        GIM_CheckFeatures, GIMT_Encode2(GIFBS_isGFX9Plus),
        GIM_CheckPointerToAny, /*MI*/0, /*Op*/1, /*SizeInBits*/0,
        GIM_CheckComplexPattern, /*MI*/0, /*Op*/1, /*Renderer*/GIMT_Encode2(0), GIMT_Encode2(GICP_gi_smrd_sgpr_imm),
        // (ld:{ *:[v16i16] } (SMRDSgprImm:{ *:[iPTR] } i64:{ *:[i64] }:$sbase, i32:{ *:[i32] }:$soffset, i32:{ *:[i32] }:$offset))<<P:Predicate_unindexedload>><<P:Predicate_load>><<P:Predicate_smrd_load>>  =>  (S_LOAD_DWORDX8_SGPR_IMM:{ *:[v16i16] } ?:{ *:[i64] }:$sbase, ?:{ *:[i32] }:$soffset, ?:{ *:[i32] }:$offset, 0:{ *:[i32] })
        GIR_BuildMI, /*InsnID*/0, /*Opcode*/GIMT_Encode2(AMDGPU::S_LOAD_DWORDX8_SGPR_IMM),
        GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/0, // DstI[sdst]
        GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/0, // sbase
        GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/1, // soffset
        GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/2, // offset
        GIR_AddImm8, /*InsnID*/0, /*Imm*/0,
        GIR_MergeMemOperands, /*InsnID*/0, /*NumInsns*/1, /*MergeInsnID's*/0,
        GIR_ConstrainSelectedInstOperands, /*InsnID*/0,
        GIR_EraseFromParent, /*InsnID*/0,
        // GIR_Coverage, 2628,
        GIR_Done,
      // Label 1630: @107582
      GIM_Try, /*On fail goto*//*Label 1631*/ GIMT_Encode4(107636), // Rule ID 2634 //
        GIM_CheckFeatures, GIMT_Encode2(GIFBS_isGFX9Plus),
        GIM_CheckPointerToAny, /*MI*/0, /*Op*/1, /*SizeInBits*/0,
        GIM_CheckComplexPattern, /*MI*/0, /*Op*/1, /*Renderer*/GIMT_Encode2(0), GIMT_Encode2(GICP_gi_smrd_sgpr_imm),
        // (ld:{ *:[v16f16] } (SMRDSgprImm:{ *:[iPTR] } i64:{ *:[i64] }:$sbase, i32:{ *:[i32] }:$soffset, i32:{ *:[i32] }:$offset))<<P:Predicate_unindexedload>><<P:Predicate_load>><<P:Predicate_smrd_load>>  =>  (S_LOAD_DWORDX8_SGPR_IMM:{ *:[v16f16] } ?:{ *:[i64] }:$sbase, ?:{ *:[i32] }:$soffset, ?:{ *:[i32] }:$offset, 0:{ *:[i32] })
        GIR_BuildMI, /*InsnID*/0, /*Opcode*/GIMT_Encode2(AMDGPU::S_LOAD_DWORDX8_SGPR_IMM),
        GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/0, // DstI[sdst]
        GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/0, // sbase
        GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/1, // soffset
        GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/2, // offset
        GIR_AddImm8, /*InsnID*/0, /*Imm*/0,
        GIR_MergeMemOperands, /*InsnID*/0, /*NumInsns*/1, /*MergeInsnID's*/0,
        GIR_ConstrainSelectedInstOperands, /*InsnID*/0,
        GIR_EraseFromParent, /*InsnID*/0,
        // GIR_Coverage, 2634,
        GIR_Done,
      // Label 1631: @107636
      GIM_Try, /*On fail goto*//*Label 1632*/ GIMT_Encode4(107690), // Rule ID 2640 //
        GIM_CheckFeatures, GIMT_Encode2(GIFBS_isGFX9Plus),
        GIM_CheckPointerToAny, /*MI*/0, /*Op*/1, /*SizeInBits*/0,
        GIM_CheckComplexPattern, /*MI*/0, /*Op*/1, /*Renderer*/GIMT_Encode2(0), GIMT_Encode2(GICP_gi_smrd_sgpr_imm),
        // (ld:{ *:[v16bf16] } (SMRDSgprImm:{ *:[iPTR] } i64:{ *:[i64] }:$sbase, i32:{ *:[i32] }:$soffset, i32:{ *:[i32] }:$offset))<<P:Predicate_unindexedload>><<P:Predicate_load>><<P:Predicate_smrd_load>>  =>  (S_LOAD_DWORDX8_SGPR_IMM:{ *:[v16bf16] } ?:{ *:[i64] }:$sbase, ?:{ *:[i32] }:$soffset, ?:{ *:[i32] }:$offset, 0:{ *:[i32] })
        GIR_BuildMI, /*InsnID*/0, /*Opcode*/GIMT_Encode2(AMDGPU::S_LOAD_DWORDX8_SGPR_IMM),
        GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/0, // DstI[sdst]
        GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/0, // sbase
        GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/1, // soffset
        GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/2, // offset
        GIR_AddImm8, /*InsnID*/0, /*Imm*/0,
        GIR_MergeMemOperands, /*InsnID*/0, /*NumInsns*/1, /*MergeInsnID's*/0,
        GIR_ConstrainSelectedInstOperands, /*InsnID*/0,
        GIR_EraseFromParent, /*InsnID*/0,
        // GIR_Coverage, 2640,
        GIR_Done,
      // Label 1632: @107690
      GIM_Try, /*On fail goto*//*Label 1633*/ GIMT_Encode4(107736), // Rule ID 2624 //
        GIM_CheckPointerToAny, /*MI*/0, /*Op*/1, /*SizeInBits*/0,
        GIM_CheckComplexPattern, /*MI*/0, /*Op*/1, /*Renderer*/GIMT_Encode2(0), GIMT_Encode2(GICP_gi_smrd_imm),
        // (ld:{ *:[v16i16] } (SMRDImm:{ *:[iPTR] } i64:{ *:[i64] }:$sbase, i32:{ *:[i32] }:$offset))<<P:Predicate_unindexedload>><<P:Predicate_load>><<P:Predicate_smrd_load>>  =>  (S_LOAD_DWORDX8_IMM:{ *:[v16i16] } ?:{ *:[i64] }:$sbase, ?:{ *:[i32] }:$offset, 0:{ *:[i32] })
        GIR_BuildMI, /*InsnID*/0, /*Opcode*/GIMT_Encode2(AMDGPU::S_LOAD_DWORDX8_IMM),
        GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/0, // DstI[sdst]
        GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/0, // sbase
        GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/1, // offset
        GIR_AddImm8, /*InsnID*/0, /*Imm*/0,
        GIR_MergeMemOperands, /*InsnID*/0, /*NumInsns*/1, /*MergeInsnID's*/0,
        GIR_ConstrainSelectedInstOperands, /*InsnID*/0,
        GIR_EraseFromParent, /*InsnID*/0,
        // GIR_Coverage, 2624,
        GIR_Done,
      // Label 1633: @107736
      GIM_Try, /*On fail goto*//*Label 1634*/ GIMT_Encode4(107785), // Rule ID 2625 //
        GIM_CheckFeatures, GIMT_Encode2(GIFBS_isGFX7Only),
        GIM_CheckPointerToAny, /*MI*/0, /*Op*/1, /*SizeInBits*/0,
        GIM_CheckComplexPattern, /*MI*/0, /*Op*/1, /*Renderer*/GIMT_Encode2(0), GIMT_Encode2(GICP_gi_smrd_imm32),
        // (ld:{ *:[v16i16] } (SMRDImm32:{ *:[iPTR] } i64:{ *:[i64] }:$sbase, i32:{ *:[i32] }:$offset))<<P:Predicate_unindexedload>><<P:Predicate_load>><<P:Predicate_smrd_load>>  =>  (S_LOAD_DWORDX8_IMM_ci:{ *:[v16i16] } ?:{ *:[i64] }:$sbase, ?:{ *:[i32] }:$offset, 0:{ *:[i32] })
        GIR_BuildMI, /*InsnID*/0, /*Opcode*/GIMT_Encode2(AMDGPU::S_LOAD_DWORDX8_IMM_ci),
        GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/0, // DstI[sdst]
        GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/0, // sbase
        GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/1, // offset
        GIR_AddImm8, /*InsnID*/0, /*Imm*/0,
        GIR_MergeMemOperands, /*InsnID*/0, /*NumInsns*/1, /*MergeInsnID's*/0,
        GIR_ConstrainSelectedInstOperands, /*InsnID*/0,
        GIR_EraseFromParent, /*InsnID*/0,
        // GIR_Coverage, 2625,
        GIR_Done,
      // Label 1634: @107785
      GIM_Try, /*On fail goto*//*Label 1635*/ GIMT_Encode4(107834), // Rule ID 2626 //
        GIM_CheckFeatures, GIMT_Encode2(GIFBS_isNotGFX9Plus),
        GIM_CheckPointerToAny, /*MI*/0, /*Op*/1, /*SizeInBits*/0,
        GIM_CheckComplexPattern, /*MI*/0, /*Op*/1, /*Renderer*/GIMT_Encode2(0), GIMT_Encode2(GICP_gi_smrd_sgpr),
        // (ld:{ *:[v16i16] } (SMRDSgpr:{ *:[iPTR] } i64:{ *:[i64] }:$sbase, i32:{ *:[i32] }:$soffset))<<P:Predicate_unindexedload>><<P:Predicate_load>><<P:Predicate_smrd_load>>  =>  (S_LOAD_DWORDX8_SGPR:{ *:[v16i16] } ?:{ *:[i64] }:$sbase, ?:{ *:[i32] }:$soffset, 0:{ *:[i32] })
        GIR_BuildMI, /*InsnID*/0, /*Opcode*/GIMT_Encode2(AMDGPU::S_LOAD_DWORDX8_SGPR),
        GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/0, // DstI[sdst]
        GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/0, // sbase
        GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/1, // soffset
        GIR_AddImm8, /*InsnID*/0, /*Imm*/0,
        GIR_MergeMemOperands, /*InsnID*/0, /*NumInsns*/1, /*MergeInsnID's*/0,
        GIR_ConstrainSelectedInstOperands, /*InsnID*/0,
        GIR_EraseFromParent, /*InsnID*/0,
        // GIR_Coverage, 2626,
        GIR_Done,
      // Label 1635: @107834
      GIM_Try, /*On fail goto*//*Label 1636*/ GIMT_Encode4(107886), // Rule ID 2627 //
        GIM_CheckFeatures, GIMT_Encode2(GIFBS_isGFX9Plus),
        GIM_CheckPointerToAny, /*MI*/0, /*Op*/1, /*SizeInBits*/0,
        GIM_CheckComplexPattern, /*MI*/0, /*Op*/1, /*Renderer*/GIMT_Encode2(0), GIMT_Encode2(GICP_gi_smrd_sgpr),
        // (ld:{ *:[v16i16] } (SMRDSgpr:{ *:[iPTR] } i64:{ *:[i64] }:$sbase, i32:{ *:[i32] }:$soffset))<<P:Predicate_unindexedload>><<P:Predicate_load>><<P:Predicate_smrd_load>>  =>  (S_LOAD_DWORDX8_SGPR_IMM:{ *:[v16i16] } ?:{ *:[i64] }:$sbase, ?:{ *:[i32] }:$soffset, 0:{ *:[i32] }, 0:{ *:[i32] })
        GIR_BuildMI, /*InsnID*/0, /*Opcode*/GIMT_Encode2(AMDGPU::S_LOAD_DWORDX8_SGPR_IMM),
        GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/0, // DstI[sdst]
        GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/0, // sbase
        GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/1, // soffset
        GIR_AddImm8, /*InsnID*/0, /*Imm*/0,
        GIR_AddImm8, /*InsnID*/0, /*Imm*/0,
        GIR_MergeMemOperands, /*InsnID*/0, /*NumInsns*/1, /*MergeInsnID's*/0,
        GIR_ConstrainSelectedInstOperands, /*InsnID*/0,
        GIR_EraseFromParent, /*InsnID*/0,
        // GIR_Coverage, 2627,
        GIR_Done,
      // Label 1636: @107886
      GIM_Try, /*On fail goto*//*Label 1637*/ GIMT_Encode4(107932), // Rule ID 2630 //
        GIM_CheckPointerToAny, /*MI*/0, /*Op*/1, /*SizeInBits*/0,
        GIM_CheckComplexPattern, /*MI*/0, /*Op*/1, /*Renderer*/GIMT_Encode2(0), GIMT_Encode2(GICP_gi_smrd_imm),
        // (ld:{ *:[v16f16] } (SMRDImm:{ *:[iPTR] } i64:{ *:[i64] }:$sbase, i32:{ *:[i32] }:$offset))<<P:Predicate_unindexedload>><<P:Predicate_load>><<P:Predicate_smrd_load>>  =>  (S_LOAD_DWORDX8_IMM:{ *:[v16f16] } ?:{ *:[i64] }:$sbase, ?:{ *:[i32] }:$offset, 0:{ *:[i32] })
        GIR_BuildMI, /*InsnID*/0, /*Opcode*/GIMT_Encode2(AMDGPU::S_LOAD_DWORDX8_IMM),
        GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/0, // DstI[sdst]
        GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/0, // sbase
        GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/1, // offset
        GIR_AddImm8, /*InsnID*/0, /*Imm*/0,
        GIR_MergeMemOperands, /*InsnID*/0, /*NumInsns*/1, /*MergeInsnID's*/0,
        GIR_ConstrainSelectedInstOperands, /*InsnID*/0,
        GIR_EraseFromParent, /*InsnID*/0,
        // GIR_Coverage, 2630,
        GIR_Done,
      // Label 1637: @107932
      GIM_Try, /*On fail goto*//*Label 1638*/ GIMT_Encode4(107981), // Rule ID 2631 //
        GIM_CheckFeatures, GIMT_Encode2(GIFBS_isGFX7Only),
        GIM_CheckPointerToAny, /*MI*/0, /*Op*/1, /*SizeInBits*/0,
        GIM_CheckComplexPattern, /*MI*/0, /*Op*/1, /*Renderer*/GIMT_Encode2(0), GIMT_Encode2(GICP_gi_smrd_imm32),
        // (ld:{ *:[v16f16] } (SMRDImm32:{ *:[iPTR] } i64:{ *:[i64] }:$sbase, i32:{ *:[i32] }:$offset))<<P:Predicate_unindexedload>><<P:Predicate_load>><<P:Predicate_smrd_load>>  =>  (S_LOAD_DWORDX8_IMM_ci:{ *:[v16f16] } ?:{ *:[i64] }:$sbase, ?:{ *:[i32] }:$offset, 0:{ *:[i32] })
        GIR_BuildMI, /*InsnID*/0, /*Opcode*/GIMT_Encode2(AMDGPU::S_LOAD_DWORDX8_IMM_ci),
        GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/0, // DstI[sdst]
        GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/0, // sbase
        GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/1, // offset
        GIR_AddImm8, /*InsnID*/0, /*Imm*/0,
        GIR_MergeMemOperands, /*InsnID*/0, /*NumInsns*/1, /*MergeInsnID's*/0,
        GIR_ConstrainSelectedInstOperands, /*InsnID*/0,
        GIR_EraseFromParent, /*InsnID*/0,
        // GIR_Coverage, 2631,
        GIR_Done,
      // Label 1638: @107981
      GIM_Try, /*On fail goto*//*Label 1639*/ GIMT_Encode4(108030), // Rule ID 2632 //
        GIM_CheckFeatures, GIMT_Encode2(GIFBS_isNotGFX9Plus),
        GIM_CheckPointerToAny, /*MI*/0, /*Op*/1, /*SizeInBits*/0,
        GIM_CheckComplexPattern, /*MI*/0, /*Op*/1, /*Renderer*/GIMT_Encode2(0), GIMT_Encode2(GICP_gi_smrd_sgpr),
        // (ld:{ *:[v16f16] } (SMRDSgpr:{ *:[iPTR] } i64:{ *:[i64] }:$sbase, i32:{ *:[i32] }:$soffset))<<P:Predicate_unindexedload>><<P:Predicate_load>><<P:Predicate_smrd_load>>  =>  (S_LOAD_DWORDX8_SGPR:{ *:[v16f16] } ?:{ *:[i64] }:$sbase, ?:{ *:[i32] }:$soffset, 0:{ *:[i32] })
        GIR_BuildMI, /*InsnID*/0, /*Opcode*/GIMT_Encode2(AMDGPU::S_LOAD_DWORDX8_SGPR),
        GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/0, // DstI[sdst]
        GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/0, // sbase
        GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/1, // soffset
        GIR_AddImm8, /*InsnID*/0, /*Imm*/0,
        GIR_MergeMemOperands, /*InsnID*/0, /*NumInsns*/1, /*MergeInsnID's*/0,
        GIR_ConstrainSelectedInstOperands, /*InsnID*/0,
        GIR_EraseFromParent, /*InsnID*/0,
        // GIR_Coverage, 2632,
        GIR_Done,
      // Label 1639: @108030
      GIM_Try, /*On fail goto*//*Label 1640*/ GIMT_Encode4(108082), // Rule ID 2633 //
        GIM_CheckFeatures, GIMT_Encode2(GIFBS_isGFX9Plus),
        GIM_CheckPointerToAny, /*MI*/0, /*Op*/1, /*SizeInBits*/0,
        GIM_CheckComplexPattern, /*MI*/0, /*Op*/1, /*Renderer*/GIMT_Encode2(0), GIMT_Encode2(GICP_gi_smrd_sgpr),
        // (ld:{ *:[v16f16] } (SMRDSgpr:{ *:[iPTR] } i64:{ *:[i64] }:$sbase, i32:{ *:[i32] }:$soffset))<<P:Predicate_unindexedload>><<P:Predicate_load>><<P:Predicate_smrd_load>>  =>  (S_LOAD_DWORDX8_SGPR_IMM:{ *:[v16f16] } ?:{ *:[i64] }:$sbase, ?:{ *:[i32] }:$soffset, 0:{ *:[i32] }, 0:{ *:[i32] })
        GIR_BuildMI, /*InsnID*/0, /*Opcode*/GIMT_Encode2(AMDGPU::S_LOAD_DWORDX8_SGPR_IMM),
        GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/0, // DstI[sdst]
        GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/0, // sbase
        GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/1, // soffset
        GIR_AddImm8, /*InsnID*/0, /*Imm*/0,
        GIR_AddImm8, /*InsnID*/0, /*Imm*/0,
        GIR_MergeMemOperands, /*InsnID*/0, /*NumInsns*/1, /*MergeInsnID's*/0,
        GIR_ConstrainSelectedInstOperands, /*InsnID*/0,
        GIR_EraseFromParent, /*InsnID*/0,
        // GIR_Coverage, 2633,
        GIR_Done,
      // Label 1640: @108082
      GIM_Try, /*On fail goto*//*Label 1641*/ GIMT_Encode4(108128), // Rule ID 2636 //
        GIM_CheckPointerToAny, /*MI*/0, /*Op*/1, /*SizeInBits*/0,
        GIM_CheckComplexPattern, /*MI*/0, /*Op*/1, /*Renderer*/GIMT_Encode2(0), GIMT_Encode2(GICP_gi_smrd_imm),
        // (ld:{ *:[v16bf16] } (SMRDImm:{ *:[iPTR] } i64:{ *:[i64] }:$sbase, i32:{ *:[i32] }:$offset))<<P:Predicate_unindexedload>><<P:Predicate_load>><<P:Predicate_smrd_load>>  =>  (S_LOAD_DWORDX8_IMM:{ *:[v16bf16] } ?:{ *:[i64] }:$sbase, ?:{ *:[i32] }:$offset, 0:{ *:[i32] })
        GIR_BuildMI, /*InsnID*/0, /*Opcode*/GIMT_Encode2(AMDGPU::S_LOAD_DWORDX8_IMM),
        GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/0, // DstI[sdst]
        GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/0, // sbase
        GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/1, // offset
        GIR_AddImm8, /*InsnID*/0, /*Imm*/0,
        GIR_MergeMemOperands, /*InsnID*/0, /*NumInsns*/1, /*MergeInsnID's*/0,
        GIR_ConstrainSelectedInstOperands, /*InsnID*/0,
        GIR_EraseFromParent, /*InsnID*/0,
        // GIR_Coverage, 2636,
        GIR_Done,
      // Label 1641: @108128
      GIM_Try, /*On fail goto*//*Label 1642*/ GIMT_Encode4(108177), // Rule ID 2637 //
        GIM_CheckFeatures, GIMT_Encode2(GIFBS_isGFX7Only),
        GIM_CheckPointerToAny, /*MI*/0, /*Op*/1, /*SizeInBits*/0,
        GIM_CheckComplexPattern, /*MI*/0, /*Op*/1, /*Renderer*/GIMT_Encode2(0), GIMT_Encode2(GICP_gi_smrd_imm32),
        // (ld:{ *:[v16bf16] } (SMRDImm32:{ *:[iPTR] } i64:{ *:[i64] }:$sbase, i32:{ *:[i32] }:$offset))<<P:Predicate_unindexedload>><<P:Predicate_load>><<P:Predicate_smrd_load>>  =>  (S_LOAD_DWORDX8_IMM_ci:{ *:[v16bf16] } ?:{ *:[i64] }:$sbase, ?:{ *:[i32] }:$offset, 0:{ *:[i32] })
        GIR_BuildMI, /*InsnID*/0, /*Opcode*/GIMT_Encode2(AMDGPU::S_LOAD_DWORDX8_IMM_ci),
        GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/0, // DstI[sdst]
        GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/0, // sbase
        GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/1, // offset
        GIR_AddImm8, /*InsnID*/0, /*Imm*/0,
        GIR_MergeMemOperands, /*InsnID*/0, /*NumInsns*/1, /*MergeInsnID's*/0,
        GIR_ConstrainSelectedInstOperands, /*InsnID*/0,
        GIR_EraseFromParent, /*InsnID*/0,
        // GIR_Coverage, 2637,
        GIR_Done,
      // Label 1642: @108177
      GIM_Try, /*On fail goto*//*Label 1643*/ GIMT_Encode4(108226), // Rule ID 2638 //
        GIM_CheckFeatures, GIMT_Encode2(GIFBS_isNotGFX9Plus),
        GIM_CheckPointerToAny, /*MI*/0, /*Op*/1, /*SizeInBits*/0,
        GIM_CheckComplexPattern, /*MI*/0, /*Op*/1, /*Renderer*/GIMT_Encode2(0), GIMT_Encode2(GICP_gi_smrd_sgpr),
        // (ld:{ *:[v16bf16] } (SMRDSgpr:{ *:[iPTR] } i64:{ *:[i64] }:$sbase, i32:{ *:[i32] }:$soffset))<<P:Predicate_unindexedload>><<P:Predicate_load>><<P:Predicate_smrd_load>>  =>  (S_LOAD_DWORDX8_SGPR:{ *:[v16bf16] } ?:{ *:[i64] }:$sbase, ?:{ *:[i32] }:$soffset, 0:{ *:[i32] })
        GIR_BuildMI, /*InsnID*/0, /*Opcode*/GIMT_Encode2(AMDGPU::S_LOAD_DWORDX8_SGPR),
        GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/0, // DstI[sdst]
        GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/0, // sbase
        GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/1, // soffset
        GIR_AddImm8, /*InsnID*/0, /*Imm*/0,
        GIR_MergeMemOperands, /*InsnID*/0, /*NumInsns*/1, /*MergeInsnID's*/0,
        GIR_ConstrainSelectedInstOperands, /*InsnID*/0,
        GIR_EraseFromParent, /*InsnID*/0,
        // GIR_Coverage, 2638,
        GIR_Done,
      // Label 1643: @108226
      GIM_Try, /*On fail goto*//*Label 1644*/ GIMT_Encode4(108278), // Rule ID 2639 //
        GIM_CheckFeatures, GIMT_Encode2(GIFBS_isGFX9Plus),
        GIM_CheckPointerToAny, /*MI*/0, /*Op*/1, /*SizeInBits*/0,
        GIM_CheckComplexPattern, /*MI*/0, /*Op*/1, /*Renderer*/GIMT_Encode2(0), GIMT_Encode2(GICP_gi_smrd_sgpr),
        // (ld:{ *:[v16bf16] } (SMRDSgpr:{ *:[iPTR] } i64:{ *:[i64] }:$sbase, i32:{ *:[i32] }:$soffset))<<P:Predicate_unindexedload>><<P:Predicate_load>><<P:Predicate_smrd_load>>  =>  (S_LOAD_DWORDX8_SGPR_IMM:{ *:[v16bf16] } ?:{ *:[i64] }:$sbase, ?:{ *:[i32] }:$soffset, 0:{ *:[i32] }, 0:{ *:[i32] })
        GIR_BuildMI, /*InsnID*/0, /*Opcode*/GIMT_Encode2(AMDGPU::S_LOAD_DWORDX8_SGPR_IMM),
        GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/0, // DstI[sdst]
        GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/0, // sbase
        GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/1, // soffset
        GIR_AddImm8, /*InsnID*/0, /*Imm*/0,
        GIR_AddImm8, /*InsnID*/0, /*Imm*/0,
        GIR_MergeMemOperands, /*InsnID*/0, /*NumInsns*/1, /*MergeInsnID's*/0,
        GIR_ConstrainSelectedInstOperands, /*InsnID*/0,
        GIR_EraseFromParent, /*InsnID*/0,
        // GIR_Coverage, 2639,
        GIR_Done,
      // Label 1644: @108278
      GIM_Try, /*On fail goto*//*Label 1645*/ GIMT_Encode4(108319), // Rule ID 2629 //
        // MIs[0] sbase
        GIM_CheckPointerToAny, /*MI*/0, /*Op*/1, /*SizeInBits*/64,
        GIM_CheckRegBankForClass, /*MI*/0, /*Op*/1, /*RC*/GIMT_Encode2(AMDGPU::SReg_64RegClassID),
        // (ld:{ *:[v16i16] } SReg_64:{ *:[i64] }:$sbase)<<P:Predicate_unindexedload>><<P:Predicate_load>><<P:Predicate_smrd_load>>  =>  (S_LOAD_DWORDX8_IMM:{ *:[v16i16] } i64:{ *:[i64] }:$sbase, 0:{ *:[i32] }, 0:{ *:[i32] })
        GIR_BuildMI, /*InsnID*/0, /*Opcode*/GIMT_Encode2(AMDGPU::S_LOAD_DWORDX8_IMM),
        GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/0, // DstI[sdst]
        GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/1, // sbase
        GIR_AddImm8, /*InsnID*/0, /*Imm*/0,
        GIR_AddImm8, /*InsnID*/0, /*Imm*/0,
        GIR_MergeMemOperands, /*InsnID*/0, /*NumInsns*/1, /*MergeInsnID's*/0,
        GIR_ConstrainSelectedInstOperands, /*InsnID*/0,
        GIR_EraseFromParent, /*InsnID*/0,
        // GIR_Coverage, 2629,
        GIR_Done,
      // Label 1645: @108319
      GIM_Try, /*On fail goto*//*Label 1646*/ GIMT_Encode4(108360), // Rule ID 2635 //
        // MIs[0] sbase
        GIM_CheckPointerToAny, /*MI*/0, /*Op*/1, /*SizeInBits*/64,
        GIM_CheckRegBankForClass, /*MI*/0, /*Op*/1, /*RC*/GIMT_Encode2(AMDGPU::SReg_64RegClassID),
        // (ld:{ *:[v16f16] } SReg_64:{ *:[i64] }:$sbase)<<P:Predicate_unindexedload>><<P:Predicate_load>><<P:Predicate_smrd_load>>  =>  (S_LOAD_DWORDX8_IMM:{ *:[v16f16] } i64:{ *:[i64] }:$sbase, 0:{ *:[i32] }, 0:{ *:[i32] })
        GIR_BuildMI, /*InsnID*/0, /*Opcode*/GIMT_Encode2(AMDGPU::S_LOAD_DWORDX8_IMM),
        GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/0, // DstI[sdst]
        GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/1, // sbase
        GIR_AddImm8, /*InsnID*/0, /*Imm*/0,
        GIR_AddImm8, /*InsnID*/0, /*Imm*/0,
        GIR_MergeMemOperands, /*InsnID*/0, /*NumInsns*/1, /*MergeInsnID's*/0,
        GIR_ConstrainSelectedInstOperands, /*InsnID*/0,
        GIR_EraseFromParent, /*InsnID*/0,
        // GIR_Coverage, 2635,
        GIR_Done,
      // Label 1646: @108360
      GIM_Try, /*On fail goto*//*Label 1647*/ GIMT_Encode4(108401), // Rule ID 2641 //
        // MIs[0] sbase
        GIM_CheckPointerToAny, /*MI*/0, /*Op*/1, /*SizeInBits*/64,
        GIM_CheckRegBankForClass, /*MI*/0, /*Op*/1, /*RC*/GIMT_Encode2(AMDGPU::SReg_64RegClassID),
        // (ld:{ *:[v16bf16] } SReg_64:{ *:[i64] }:$sbase)<<P:Predicate_unindexedload>><<P:Predicate_load>><<P:Predicate_smrd_load>>  =>  (S_LOAD_DWORDX8_IMM:{ *:[v16bf16] } i64:{ *:[i64] }:$sbase, 0:{ *:[i32] }, 0:{ *:[i32] })
        GIR_BuildMI, /*InsnID*/0, /*Opcode*/GIMT_Encode2(AMDGPU::S_LOAD_DWORDX8_IMM),
        GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/0, // DstI[sdst]
        GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/1, // sbase
        GIR_AddImm8, /*InsnID*/0, /*Imm*/0,
        GIR_AddImm8, /*InsnID*/0, /*Imm*/0,
        GIR_MergeMemOperands, /*InsnID*/0, /*NumInsns*/1, /*MergeInsnID's*/0,
        GIR_ConstrainSelectedInstOperands, /*InsnID*/0,
        GIR_EraseFromParent, /*InsnID*/0,
        // GIR_Coverage, 2641,
        GIR_Done,
      // Label 1647: @108401
      GIM_Reject,
    // Label 1629: @108402
    GIM_Reject,
    // Label 838: @108403
    GIM_Try, /*On fail goto*//*Label 1648*/ GIMT_Encode4(109007),
      GIM_CheckMemorySizeEqualToLLT, /*MI*/0, /*MMO*/0, /*OpIdx*/0,
      GIM_CheckCxxInsnPredicate, /*MI*/0, /*FnId*/GIMT_Encode2(GICXXPred_MI_Predicate_smrd_load),
      GIM_CheckAtomicOrdering, /*MI*/0, /*Order*/(uint8_t)AtomicOrdering::NotAtomic,
      GIM_CheckRegBankForClass, /*MI*/0, /*Op*/0, /*RC*/GIMT_Encode2(AMDGPU::SReg_512RegClassID),
      GIM_Try, /*On fail goto*//*Label 1649*/ GIMT_Encode4(108478), // Rule ID 2646 //
        GIM_CheckFeatures, GIMT_Encode2(GIFBS_isGFX9Plus),
        GIM_CheckPointerToAny, /*MI*/0, /*Op*/1, /*SizeInBits*/0,
        GIM_CheckComplexPattern, /*MI*/0, /*Op*/1, /*Renderer*/GIMT_Encode2(0), GIMT_Encode2(GICP_gi_smrd_sgpr_imm),
        // (ld:{ *:[v16i32] } (SMRDSgprImm:{ *:[iPTR] } i64:{ *:[i64] }:$sbase, i32:{ *:[i32] }:$soffset, i32:{ *:[i32] }:$offset))<<P:Predicate_unindexedload>><<P:Predicate_load>><<P:Predicate_smrd_load>>  =>  (S_LOAD_DWORDX16_SGPR_IMM:{ *:[v16i32] } ?:{ *:[i64] }:$sbase, ?:{ *:[i32] }:$soffset, ?:{ *:[i32] }:$offset, 0:{ *:[i32] })
        GIR_BuildMI, /*InsnID*/0, /*Opcode*/GIMT_Encode2(AMDGPU::S_LOAD_DWORDX16_SGPR_IMM),
        GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/0, // DstI[sdst]
        GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/0, // sbase
        GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/1, // soffset
        GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/2, // offset
        GIR_AddImm8, /*InsnID*/0, /*Imm*/0,
        GIR_MergeMemOperands, /*InsnID*/0, /*NumInsns*/1, /*MergeInsnID's*/0,
        GIR_ConstrainSelectedInstOperands, /*InsnID*/0,
        GIR_EraseFromParent, /*InsnID*/0,
        // GIR_Coverage, 2646,
        GIR_Done,
      // Label 1649: @108478
      GIM_Try, /*On fail goto*//*Label 1650*/ GIMT_Encode4(108532), // Rule ID 2652 //
        GIM_CheckFeatures, GIMT_Encode2(GIFBS_isGFX9Plus),
        GIM_CheckPointerToAny, /*MI*/0, /*Op*/1, /*SizeInBits*/0,
        GIM_CheckComplexPattern, /*MI*/0, /*Op*/1, /*Renderer*/GIMT_Encode2(0), GIMT_Encode2(GICP_gi_smrd_sgpr_imm),
        // (ld:{ *:[v16f32] } (SMRDSgprImm:{ *:[iPTR] } i64:{ *:[i64] }:$sbase, i32:{ *:[i32] }:$soffset, i32:{ *:[i32] }:$offset))<<P:Predicate_unindexedload>><<P:Predicate_load>><<P:Predicate_smrd_load>>  =>  (S_LOAD_DWORDX16_SGPR_IMM:{ *:[v16f32] } ?:{ *:[i64] }:$sbase, ?:{ *:[i32] }:$soffset, ?:{ *:[i32] }:$offset, 0:{ *:[i32] })
        GIR_BuildMI, /*InsnID*/0, /*Opcode*/GIMT_Encode2(AMDGPU::S_LOAD_DWORDX16_SGPR_IMM),
        GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/0, // DstI[sdst]
        GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/0, // sbase
        GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/1, // soffset
        GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/2, // offset
        GIR_AddImm8, /*InsnID*/0, /*Imm*/0,
        GIR_MergeMemOperands, /*InsnID*/0, /*NumInsns*/1, /*MergeInsnID's*/0,
        GIR_ConstrainSelectedInstOperands, /*InsnID*/0,
        GIR_EraseFromParent, /*InsnID*/0,
        // GIR_Coverage, 2652,
        GIR_Done,
      // Label 1650: @108532
      GIM_Try, /*On fail goto*//*Label 1651*/ GIMT_Encode4(108578), // Rule ID 2642 //
        GIM_CheckPointerToAny, /*MI*/0, /*Op*/1, /*SizeInBits*/0,
        GIM_CheckComplexPattern, /*MI*/0, /*Op*/1, /*Renderer*/GIMT_Encode2(0), GIMT_Encode2(GICP_gi_smrd_imm),
        // (ld:{ *:[v16i32] } (SMRDImm:{ *:[iPTR] } i64:{ *:[i64] }:$sbase, i32:{ *:[i32] }:$offset))<<P:Predicate_unindexedload>><<P:Predicate_load>><<P:Predicate_smrd_load>>  =>  (S_LOAD_DWORDX16_IMM:{ *:[v16i32] } ?:{ *:[i64] }:$sbase, ?:{ *:[i32] }:$offset, 0:{ *:[i32] })
        GIR_BuildMI, /*InsnID*/0, /*Opcode*/GIMT_Encode2(AMDGPU::S_LOAD_DWORDX16_IMM),
        GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/0, // DstI[sdst]
        GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/0, // sbase
        GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/1, // offset
        GIR_AddImm8, /*InsnID*/0, /*Imm*/0,
        GIR_MergeMemOperands, /*InsnID*/0, /*NumInsns*/1, /*MergeInsnID's*/0,
        GIR_ConstrainSelectedInstOperands, /*InsnID*/0,
        GIR_EraseFromParent, /*InsnID*/0,
        // GIR_Coverage, 2642,
        GIR_Done,
      // Label 1651: @108578
      GIM_Try, /*On fail goto*//*Label 1652*/ GIMT_Encode4(108627), // Rule ID 2643 //
        GIM_CheckFeatures, GIMT_Encode2(GIFBS_isGFX7Only),
        GIM_CheckPointerToAny, /*MI*/0, /*Op*/1, /*SizeInBits*/0,
        GIM_CheckComplexPattern, /*MI*/0, /*Op*/1, /*Renderer*/GIMT_Encode2(0), GIMT_Encode2(GICP_gi_smrd_imm32),
        // (ld:{ *:[v16i32] } (SMRDImm32:{ *:[iPTR] } i64:{ *:[i64] }:$sbase, i32:{ *:[i32] }:$offset))<<P:Predicate_unindexedload>><<P:Predicate_load>><<P:Predicate_smrd_load>>  =>  (S_LOAD_DWORDX16_IMM_ci:{ *:[v16i32] } ?:{ *:[i64] }:$sbase, ?:{ *:[i32] }:$offset, 0:{ *:[i32] })
        GIR_BuildMI, /*InsnID*/0, /*Opcode*/GIMT_Encode2(AMDGPU::S_LOAD_DWORDX16_IMM_ci),
        GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/0, // DstI[sdst]
        GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/0, // sbase
        GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/1, // offset
        GIR_AddImm8, /*InsnID*/0, /*Imm*/0,
        GIR_MergeMemOperands, /*InsnID*/0, /*NumInsns*/1, /*MergeInsnID's*/0,
        GIR_ConstrainSelectedInstOperands, /*InsnID*/0,
        GIR_EraseFromParent, /*InsnID*/0,
        // GIR_Coverage, 2643,
        GIR_Done,
      // Label 1652: @108627
      GIM_Try, /*On fail goto*//*Label 1653*/ GIMT_Encode4(108676), // Rule ID 2644 //
        GIM_CheckFeatures, GIMT_Encode2(GIFBS_isNotGFX9Plus),
        GIM_CheckPointerToAny, /*MI*/0, /*Op*/1, /*SizeInBits*/0,
        GIM_CheckComplexPattern, /*MI*/0, /*Op*/1, /*Renderer*/GIMT_Encode2(0), GIMT_Encode2(GICP_gi_smrd_sgpr),
        // (ld:{ *:[v16i32] } (SMRDSgpr:{ *:[iPTR] } i64:{ *:[i64] }:$sbase, i32:{ *:[i32] }:$soffset))<<P:Predicate_unindexedload>><<P:Predicate_load>><<P:Predicate_smrd_load>>  =>  (S_LOAD_DWORDX16_SGPR:{ *:[v16i32] } ?:{ *:[i64] }:$sbase, ?:{ *:[i32] }:$soffset, 0:{ *:[i32] })
        GIR_BuildMI, /*InsnID*/0, /*Opcode*/GIMT_Encode2(AMDGPU::S_LOAD_DWORDX16_SGPR),
        GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/0, // DstI[sdst]
        GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/0, // sbase
        GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/1, // soffset
        GIR_AddImm8, /*InsnID*/0, /*Imm*/0,
        GIR_MergeMemOperands, /*InsnID*/0, /*NumInsns*/1, /*MergeInsnID's*/0,
        GIR_ConstrainSelectedInstOperands, /*InsnID*/0,
        GIR_EraseFromParent, /*InsnID*/0,
        // GIR_Coverage, 2644,
        GIR_Done,
      // Label 1653: @108676
      GIM_Try, /*On fail goto*//*Label 1654*/ GIMT_Encode4(108728), // Rule ID 2645 //
        GIM_CheckFeatures, GIMT_Encode2(GIFBS_isGFX9Plus),
        GIM_CheckPointerToAny, /*MI*/0, /*Op*/1, /*SizeInBits*/0,
        GIM_CheckComplexPattern, /*MI*/0, /*Op*/1, /*Renderer*/GIMT_Encode2(0), GIMT_Encode2(GICP_gi_smrd_sgpr),
        // (ld:{ *:[v16i32] } (SMRDSgpr:{ *:[iPTR] } i64:{ *:[i64] }:$sbase, i32:{ *:[i32] }:$soffset))<<P:Predicate_unindexedload>><<P:Predicate_load>><<P:Predicate_smrd_load>>  =>  (S_LOAD_DWORDX16_SGPR_IMM:{ *:[v16i32] } ?:{ *:[i64] }:$sbase, ?:{ *:[i32] }:$soffset, 0:{ *:[i32] }, 0:{ *:[i32] })
        GIR_BuildMI, /*InsnID*/0, /*Opcode*/GIMT_Encode2(AMDGPU::S_LOAD_DWORDX16_SGPR_IMM),
        GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/0, // DstI[sdst]
        GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/0, // sbase
        GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/1, // soffset
        GIR_AddImm8, /*InsnID*/0, /*Imm*/0,
        GIR_AddImm8, /*InsnID*/0, /*Imm*/0,
        GIR_MergeMemOperands, /*InsnID*/0, /*NumInsns*/1, /*MergeInsnID's*/0,
        GIR_ConstrainSelectedInstOperands, /*InsnID*/0,
        GIR_EraseFromParent, /*InsnID*/0,
        // GIR_Coverage, 2645,
        GIR_Done,
      // Label 1654: @108728
      GIM_Try, /*On fail goto*//*Label 1655*/ GIMT_Encode4(108774), // Rule ID 2648 //
        GIM_CheckPointerToAny, /*MI*/0, /*Op*/1, /*SizeInBits*/0,
        GIM_CheckComplexPattern, /*MI*/0, /*Op*/1, /*Renderer*/GIMT_Encode2(0), GIMT_Encode2(GICP_gi_smrd_imm),
        // (ld:{ *:[v16f32] } (SMRDImm:{ *:[iPTR] } i64:{ *:[i64] }:$sbase, i32:{ *:[i32] }:$offset))<<P:Predicate_unindexedload>><<P:Predicate_load>><<P:Predicate_smrd_load>>  =>  (S_LOAD_DWORDX16_IMM:{ *:[v16f32] } ?:{ *:[i64] }:$sbase, ?:{ *:[i32] }:$offset, 0:{ *:[i32] })
        GIR_BuildMI, /*InsnID*/0, /*Opcode*/GIMT_Encode2(AMDGPU::S_LOAD_DWORDX16_IMM),
        GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/0, // DstI[sdst]
        GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/0, // sbase
        GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/1, // offset
        GIR_AddImm8, /*InsnID*/0, /*Imm*/0,
        GIR_MergeMemOperands, /*InsnID*/0, /*NumInsns*/1, /*MergeInsnID's*/0,
        GIR_ConstrainSelectedInstOperands, /*InsnID*/0,
        GIR_EraseFromParent, /*InsnID*/0,
        // GIR_Coverage, 2648,
        GIR_Done,
      // Label 1655: @108774
      GIM_Try, /*On fail goto*//*Label 1656*/ GIMT_Encode4(108823), // Rule ID 2649 //
        GIM_CheckFeatures, GIMT_Encode2(GIFBS_isGFX7Only),
        GIM_CheckPointerToAny, /*MI*/0, /*Op*/1, /*SizeInBits*/0,
        GIM_CheckComplexPattern, /*MI*/0, /*Op*/1, /*Renderer*/GIMT_Encode2(0), GIMT_Encode2(GICP_gi_smrd_imm32),
        // (ld:{ *:[v16f32] } (SMRDImm32:{ *:[iPTR] } i64:{ *:[i64] }:$sbase, i32:{ *:[i32] }:$offset))<<P:Predicate_unindexedload>><<P:Predicate_load>><<P:Predicate_smrd_load>>  =>  (S_LOAD_DWORDX16_IMM_ci:{ *:[v16f32] } ?:{ *:[i64] }:$sbase, ?:{ *:[i32] }:$offset, 0:{ *:[i32] })
        GIR_BuildMI, /*InsnID*/0, /*Opcode*/GIMT_Encode2(AMDGPU::S_LOAD_DWORDX16_IMM_ci),
        GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/0, // DstI[sdst]
        GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/0, // sbase
        GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/1, // offset
        GIR_AddImm8, /*InsnID*/0, /*Imm*/0,
        GIR_MergeMemOperands, /*InsnID*/0, /*NumInsns*/1, /*MergeInsnID's*/0,
        GIR_ConstrainSelectedInstOperands, /*InsnID*/0,
        GIR_EraseFromParent, /*InsnID*/0,
        // GIR_Coverage, 2649,
        GIR_Done,
      // Label 1656: @108823
      GIM_Try, /*On fail goto*//*Label 1657*/ GIMT_Encode4(108872), // Rule ID 2650 //
        GIM_CheckFeatures, GIMT_Encode2(GIFBS_isNotGFX9Plus),
        GIM_CheckPointerToAny, /*MI*/0, /*Op*/1, /*SizeInBits*/0,
        GIM_CheckComplexPattern, /*MI*/0, /*Op*/1, /*Renderer*/GIMT_Encode2(0), GIMT_Encode2(GICP_gi_smrd_sgpr),
        // (ld:{ *:[v16f32] } (SMRDSgpr:{ *:[iPTR] } i64:{ *:[i64] }:$sbase, i32:{ *:[i32] }:$soffset))<<P:Predicate_unindexedload>><<P:Predicate_load>><<P:Predicate_smrd_load>>  =>  (S_LOAD_DWORDX16_SGPR:{ *:[v16f32] } ?:{ *:[i64] }:$sbase, ?:{ *:[i32] }:$soffset, 0:{ *:[i32] })
        GIR_BuildMI, /*InsnID*/0, /*Opcode*/GIMT_Encode2(AMDGPU::S_LOAD_DWORDX16_SGPR),
        GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/0, // DstI[sdst]
        GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/0, // sbase
        GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/1, // soffset
        GIR_AddImm8, /*InsnID*/0, /*Imm*/0,
        GIR_MergeMemOperands, /*InsnID*/0, /*NumInsns*/1, /*MergeInsnID's*/0,
        GIR_ConstrainSelectedInstOperands, /*InsnID*/0,
        GIR_EraseFromParent, /*InsnID*/0,
        // GIR_Coverage, 2650,
        GIR_Done,
      // Label 1657: @108872
      GIM_Try, /*On fail goto*//*Label 1658*/ GIMT_Encode4(108924), // Rule ID 2651 //
        GIM_CheckFeatures, GIMT_Encode2(GIFBS_isGFX9Plus),
        GIM_CheckPointerToAny, /*MI*/0, /*Op*/1, /*SizeInBits*/0,
        GIM_CheckComplexPattern, /*MI*/0, /*Op*/1, /*Renderer*/GIMT_Encode2(0), GIMT_Encode2(GICP_gi_smrd_sgpr),
        // (ld:{ *:[v16f32] } (SMRDSgpr:{ *:[iPTR] } i64:{ *:[i64] }:$sbase, i32:{ *:[i32] }:$soffset))<<P:Predicate_unindexedload>><<P:Predicate_load>><<P:Predicate_smrd_load>>  =>  (S_LOAD_DWORDX16_SGPR_IMM:{ *:[v16f32] } ?:{ *:[i64] }:$sbase, ?:{ *:[i32] }:$soffset, 0:{ *:[i32] }, 0:{ *:[i32] })
        GIR_BuildMI, /*InsnID*/0, /*Opcode*/GIMT_Encode2(AMDGPU::S_LOAD_DWORDX16_SGPR_IMM),
        GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/0, // DstI[sdst]
        GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/0, // sbase
        GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/1, // soffset
        GIR_AddImm8, /*InsnID*/0, /*Imm*/0,
        GIR_AddImm8, /*InsnID*/0, /*Imm*/0,
        GIR_MergeMemOperands, /*InsnID*/0, /*NumInsns*/1, /*MergeInsnID's*/0,
        GIR_ConstrainSelectedInstOperands, /*InsnID*/0,
        GIR_EraseFromParent, /*InsnID*/0,
        // GIR_Coverage, 2651,
        GIR_Done,
      // Label 1658: @108924
      GIM_Try, /*On fail goto*//*Label 1659*/ GIMT_Encode4(108965), // Rule ID 2647 //
        // MIs[0] sbase
        GIM_CheckPointerToAny, /*MI*/0, /*Op*/1, /*SizeInBits*/64,
        GIM_CheckRegBankForClass, /*MI*/0, /*Op*/1, /*RC*/GIMT_Encode2(AMDGPU::SReg_64RegClassID),
        // (ld:{ *:[v16i32] } SReg_64:{ *:[i64] }:$sbase)<<P:Predicate_unindexedload>><<P:Predicate_load>><<P:Predicate_smrd_load>>  =>  (S_LOAD_DWORDX16_IMM:{ *:[v16i32] } i64:{ *:[i64] }:$sbase, 0:{ *:[i32] }, 0:{ *:[i32] })
        GIR_BuildMI, /*InsnID*/0, /*Opcode*/GIMT_Encode2(AMDGPU::S_LOAD_DWORDX16_IMM),
        GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/0, // DstI[sdst]
        GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/1, // sbase
        GIR_AddImm8, /*InsnID*/0, /*Imm*/0,
        GIR_AddImm8, /*InsnID*/0, /*Imm*/0,
        GIR_MergeMemOperands, /*InsnID*/0, /*NumInsns*/1, /*MergeInsnID's*/0,
        GIR_ConstrainSelectedInstOperands, /*InsnID*/0,
        GIR_EraseFromParent, /*InsnID*/0,
        // GIR_Coverage, 2647,
        GIR_Done,
      // Label 1659: @108965
      GIM_Try, /*On fail goto*//*Label 1660*/ GIMT_Encode4(109006), // Rule ID 2653 //
        // MIs[0] sbase
        GIM_CheckPointerToAny, /*MI*/0, /*Op*/1, /*SizeInBits*/64,
        GIM_CheckRegBankForClass, /*MI*/0, /*Op*/1, /*RC*/GIMT_Encode2(AMDGPU::SReg_64RegClassID),
        // (ld:{ *:[v16f32] } SReg_64:{ *:[i64] }:$sbase)<<P:Predicate_unindexedload>><<P:Predicate_load>><<P:Predicate_smrd_load>>  =>  (S_LOAD_DWORDX16_IMM:{ *:[v16f32] } i64:{ *:[i64] }:$sbase, 0:{ *:[i32] }, 0:{ *:[i32] })
        GIR_BuildMI, /*InsnID*/0, /*Opcode*/GIMT_Encode2(AMDGPU::S_LOAD_DWORDX16_IMM),
        GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/0, // DstI[sdst]
        GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/1, // sbase
        GIR_AddImm8, /*InsnID*/0, /*Imm*/0,
        GIR_AddImm8, /*InsnID*/0, /*Imm*/0,
        GIR_MergeMemOperands, /*InsnID*/0, /*NumInsns*/1, /*MergeInsnID's*/0,
        GIR_ConstrainSelectedInstOperands, /*InsnID*/0,
        GIR_EraseFromParent, /*InsnID*/0,
        // GIR_Coverage, 2653,
        GIR_Done,
      // Label 1660: @109006
      GIM_Reject,
    // Label 1648: @109007
    GIM_Reject,
    // Label 839: @109008
    GIM_Try, /*On fail goto*//*Label 1661*/ GIMT_Encode4(109903),
      GIM_CheckMemorySizeEqualToLLT, /*MI*/0, /*MMO*/0, /*OpIdx*/0,
      GIM_CheckCxxInsnPredicate, /*MI*/0, /*FnId*/GIMT_Encode2(GICXXPred_MI_Predicate_smrd_load),
      GIM_CheckAtomicOrdering, /*MI*/0, /*Order*/(uint8_t)AtomicOrdering::NotAtomic,
      GIM_CheckRegBankForClass, /*MI*/0, /*Op*/0, /*RC*/GIMT_Encode2(AMDGPU::SReg_512RegClassID),
      GIM_Try, /*On fail goto*//*Label 1662*/ GIMT_Encode4(109083), // Rule ID 2670 //
        GIM_CheckFeatures, GIMT_Encode2(GIFBS_isGFX9Plus),
        GIM_CheckPointerToAny, /*MI*/0, /*Op*/1, /*SizeInBits*/0,
        GIM_CheckComplexPattern, /*MI*/0, /*Op*/1, /*Renderer*/GIMT_Encode2(0), GIMT_Encode2(GICP_gi_smrd_sgpr_imm),
        // (ld:{ *:[v32i16] } (SMRDSgprImm:{ *:[iPTR] } i64:{ *:[i64] }:$sbase, i32:{ *:[i32] }:$soffset, i32:{ *:[i32] }:$offset))<<P:Predicate_unindexedload>><<P:Predicate_load>><<P:Predicate_smrd_load>>  =>  (S_LOAD_DWORDX16_SGPR_IMM:{ *:[v32i16] } ?:{ *:[i64] }:$sbase, ?:{ *:[i32] }:$soffset, ?:{ *:[i32] }:$offset, 0:{ *:[i32] })
        GIR_BuildMI, /*InsnID*/0, /*Opcode*/GIMT_Encode2(AMDGPU::S_LOAD_DWORDX16_SGPR_IMM),
        GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/0, // DstI[sdst]
        GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/0, // sbase
        GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/1, // soffset
        GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/2, // offset
        GIR_AddImm8, /*InsnID*/0, /*Imm*/0,
        GIR_MergeMemOperands, /*InsnID*/0, /*NumInsns*/1, /*MergeInsnID's*/0,
        GIR_ConstrainSelectedInstOperands, /*InsnID*/0,
        GIR_EraseFromParent, /*InsnID*/0,
        // GIR_Coverage, 2670,
        GIR_Done,
      // Label 1662: @109083
      GIM_Try, /*On fail goto*//*Label 1663*/ GIMT_Encode4(109137), // Rule ID 2676 //
        GIM_CheckFeatures, GIMT_Encode2(GIFBS_isGFX9Plus),
        GIM_CheckPointerToAny, /*MI*/0, /*Op*/1, /*SizeInBits*/0,
        GIM_CheckComplexPattern, /*MI*/0, /*Op*/1, /*Renderer*/GIMT_Encode2(0), GIMT_Encode2(GICP_gi_smrd_sgpr_imm),
        // (ld:{ *:[v32f16] } (SMRDSgprImm:{ *:[iPTR] } i64:{ *:[i64] }:$sbase, i32:{ *:[i32] }:$soffset, i32:{ *:[i32] }:$offset))<<P:Predicate_unindexedload>><<P:Predicate_load>><<P:Predicate_smrd_load>>  =>  (S_LOAD_DWORDX16_SGPR_IMM:{ *:[v32f16] } ?:{ *:[i64] }:$sbase, ?:{ *:[i32] }:$soffset, ?:{ *:[i32] }:$offset, 0:{ *:[i32] })
        GIR_BuildMI, /*InsnID*/0, /*Opcode*/GIMT_Encode2(AMDGPU::S_LOAD_DWORDX16_SGPR_IMM),
        GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/0, // DstI[sdst]
        GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/0, // sbase
        GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/1, // soffset
        GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/2, // offset
        GIR_AddImm8, /*InsnID*/0, /*Imm*/0,
        GIR_MergeMemOperands, /*InsnID*/0, /*NumInsns*/1, /*MergeInsnID's*/0,
        GIR_ConstrainSelectedInstOperands, /*InsnID*/0,
        GIR_EraseFromParent, /*InsnID*/0,
        // GIR_Coverage, 2676,
        GIR_Done,
      // Label 1663: @109137
      GIM_Try, /*On fail goto*//*Label 1664*/ GIMT_Encode4(109191), // Rule ID 2682 //
        GIM_CheckFeatures, GIMT_Encode2(GIFBS_isGFX9Plus),
        GIM_CheckPointerToAny, /*MI*/0, /*Op*/1, /*SizeInBits*/0,
        GIM_CheckComplexPattern, /*MI*/0, /*Op*/1, /*Renderer*/GIMT_Encode2(0), GIMT_Encode2(GICP_gi_smrd_sgpr_imm),
        // (ld:{ *:[v32bf16] } (SMRDSgprImm:{ *:[iPTR] } i64:{ *:[i64] }:$sbase, i32:{ *:[i32] }:$soffset, i32:{ *:[i32] }:$offset))<<P:Predicate_unindexedload>><<P:Predicate_load>><<P:Predicate_smrd_load>>  =>  (S_LOAD_DWORDX16_SGPR_IMM:{ *:[v32bf16] } ?:{ *:[i64] }:$sbase, ?:{ *:[i32] }:$soffset, ?:{ *:[i32] }:$offset, 0:{ *:[i32] })
        GIR_BuildMI, /*InsnID*/0, /*Opcode*/GIMT_Encode2(AMDGPU::S_LOAD_DWORDX16_SGPR_IMM),
        GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/0, // DstI[sdst]
        GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/0, // sbase
        GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/1, // soffset
        GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/2, // offset
        GIR_AddImm8, /*InsnID*/0, /*Imm*/0,
        GIR_MergeMemOperands, /*InsnID*/0, /*NumInsns*/1, /*MergeInsnID's*/0,
        GIR_ConstrainSelectedInstOperands, /*InsnID*/0,
        GIR_EraseFromParent, /*InsnID*/0,
        // GIR_Coverage, 2682,
        GIR_Done,
      // Label 1664: @109191
      GIM_Try, /*On fail goto*//*Label 1665*/ GIMT_Encode4(109237), // Rule ID 2666 //
        GIM_CheckPointerToAny, /*MI*/0, /*Op*/1, /*SizeInBits*/0,
        GIM_CheckComplexPattern, /*MI*/0, /*Op*/1, /*Renderer*/GIMT_Encode2(0), GIMT_Encode2(GICP_gi_smrd_imm),
        // (ld:{ *:[v32i16] } (SMRDImm:{ *:[iPTR] } i64:{ *:[i64] }:$sbase, i32:{ *:[i32] }:$offset))<<P:Predicate_unindexedload>><<P:Predicate_load>><<P:Predicate_smrd_load>>  =>  (S_LOAD_DWORDX16_IMM:{ *:[v32i16] } ?:{ *:[i64] }:$sbase, ?:{ *:[i32] }:$offset, 0:{ *:[i32] })
        GIR_BuildMI, /*InsnID*/0, /*Opcode*/GIMT_Encode2(AMDGPU::S_LOAD_DWORDX16_IMM),
        GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/0, // DstI[sdst]
        GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/0, // sbase
        GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/1, // offset
        GIR_AddImm8, /*InsnID*/0, /*Imm*/0,
        GIR_MergeMemOperands, /*InsnID*/0, /*NumInsns*/1, /*MergeInsnID's*/0,
        GIR_ConstrainSelectedInstOperands, /*InsnID*/0,
        GIR_EraseFromParent, /*InsnID*/0,
        // GIR_Coverage, 2666,
        GIR_Done,
      // Label 1665: @109237
      GIM_Try, /*On fail goto*//*Label 1666*/ GIMT_Encode4(109286), // Rule ID 2667 //
        GIM_CheckFeatures, GIMT_Encode2(GIFBS_isGFX7Only),
        GIM_CheckPointerToAny, /*MI*/0, /*Op*/1, /*SizeInBits*/0,
        GIM_CheckComplexPattern, /*MI*/0, /*Op*/1, /*Renderer*/GIMT_Encode2(0), GIMT_Encode2(GICP_gi_smrd_imm32),
        // (ld:{ *:[v32i16] } (SMRDImm32:{ *:[iPTR] } i64:{ *:[i64] }:$sbase, i32:{ *:[i32] }:$offset))<<P:Predicate_unindexedload>><<P:Predicate_load>><<P:Predicate_smrd_load>>  =>  (S_LOAD_DWORDX16_IMM_ci:{ *:[v32i16] } ?:{ *:[i64] }:$sbase, ?:{ *:[i32] }:$offset, 0:{ *:[i32] })
        GIR_BuildMI, /*InsnID*/0, /*Opcode*/GIMT_Encode2(AMDGPU::S_LOAD_DWORDX16_IMM_ci),
        GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/0, // DstI[sdst]
        GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/0, // sbase
        GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/1, // offset
        GIR_AddImm8, /*InsnID*/0, /*Imm*/0,
        GIR_MergeMemOperands, /*InsnID*/0, /*NumInsns*/1, /*MergeInsnID's*/0,
        GIR_ConstrainSelectedInstOperands, /*InsnID*/0,
        GIR_EraseFromParent, /*InsnID*/0,
        // GIR_Coverage, 2667,
        GIR_Done,
      // Label 1666: @109286
      GIM_Try, /*On fail goto*//*Label 1667*/ GIMT_Encode4(109335), // Rule ID 2668 //
        GIM_CheckFeatures, GIMT_Encode2(GIFBS_isNotGFX9Plus),
        GIM_CheckPointerToAny, /*MI*/0, /*Op*/1, /*SizeInBits*/0,
        GIM_CheckComplexPattern, /*MI*/0, /*Op*/1, /*Renderer*/GIMT_Encode2(0), GIMT_Encode2(GICP_gi_smrd_sgpr),
        // (ld:{ *:[v32i16] } (SMRDSgpr:{ *:[iPTR] } i64:{ *:[i64] }:$sbase, i32:{ *:[i32] }:$soffset))<<P:Predicate_unindexedload>><<P:Predicate_load>><<P:Predicate_smrd_load>>  =>  (S_LOAD_DWORDX16_SGPR:{ *:[v32i16] } ?:{ *:[i64] }:$sbase, ?:{ *:[i32] }:$soffset, 0:{ *:[i32] })
        GIR_BuildMI, /*InsnID*/0, /*Opcode*/GIMT_Encode2(AMDGPU::S_LOAD_DWORDX16_SGPR),
        GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/0, // DstI[sdst]
        GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/0, // sbase
        GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/1, // soffset
        GIR_AddImm8, /*InsnID*/0, /*Imm*/0,
        GIR_MergeMemOperands, /*InsnID*/0, /*NumInsns*/1, /*MergeInsnID's*/0,
        GIR_ConstrainSelectedInstOperands, /*InsnID*/0,
        GIR_EraseFromParent, /*InsnID*/0,
        // GIR_Coverage, 2668,
        GIR_Done,
      // Label 1667: @109335
      GIM_Try, /*On fail goto*//*Label 1668*/ GIMT_Encode4(109387), // Rule ID 2669 //
        GIM_CheckFeatures, GIMT_Encode2(GIFBS_isGFX9Plus),
        GIM_CheckPointerToAny, /*MI*/0, /*Op*/1, /*SizeInBits*/0,
        GIM_CheckComplexPattern, /*MI*/0, /*Op*/1, /*Renderer*/GIMT_Encode2(0), GIMT_Encode2(GICP_gi_smrd_sgpr),
        // (ld:{ *:[v32i16] } (SMRDSgpr:{ *:[iPTR] } i64:{ *:[i64] }:$sbase, i32:{ *:[i32] }:$soffset))<<P:Predicate_unindexedload>><<P:Predicate_load>><<P:Predicate_smrd_load>>  =>  (S_LOAD_DWORDX16_SGPR_IMM:{ *:[v32i16] } ?:{ *:[i64] }:$sbase, ?:{ *:[i32] }:$soffset, 0:{ *:[i32] }, 0:{ *:[i32] })
        GIR_BuildMI, /*InsnID*/0, /*Opcode*/GIMT_Encode2(AMDGPU::S_LOAD_DWORDX16_SGPR_IMM),
        GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/0, // DstI[sdst]
        GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/0, // sbase
        GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/1, // soffset
        GIR_AddImm8, /*InsnID*/0, /*Imm*/0,
        GIR_AddImm8, /*InsnID*/0, /*Imm*/0,
        GIR_MergeMemOperands, /*InsnID*/0, /*NumInsns*/1, /*MergeInsnID's*/0,
        GIR_ConstrainSelectedInstOperands, /*InsnID*/0,
        GIR_EraseFromParent, /*InsnID*/0,
        // GIR_Coverage, 2669,
        GIR_Done,
      // Label 1668: @109387
      GIM_Try, /*On fail goto*//*Label 1669*/ GIMT_Encode4(109433), // Rule ID 2672 //
        GIM_CheckPointerToAny, /*MI*/0, /*Op*/1, /*SizeInBits*/0,
        GIM_CheckComplexPattern, /*MI*/0, /*Op*/1, /*Renderer*/GIMT_Encode2(0), GIMT_Encode2(GICP_gi_smrd_imm),
        // (ld:{ *:[v32f16] } (SMRDImm:{ *:[iPTR] } i64:{ *:[i64] }:$sbase, i32:{ *:[i32] }:$offset))<<P:Predicate_unindexedload>><<P:Predicate_load>><<P:Predicate_smrd_load>>  =>  (S_LOAD_DWORDX16_IMM:{ *:[v32f16] } ?:{ *:[i64] }:$sbase, ?:{ *:[i32] }:$offset, 0:{ *:[i32] })
        GIR_BuildMI, /*InsnID*/0, /*Opcode*/GIMT_Encode2(AMDGPU::S_LOAD_DWORDX16_IMM),
        GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/0, // DstI[sdst]
        GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/0, // sbase
        GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/1, // offset
        GIR_AddImm8, /*InsnID*/0, /*Imm*/0,
        GIR_MergeMemOperands, /*InsnID*/0, /*NumInsns*/1, /*MergeInsnID's*/0,
        GIR_ConstrainSelectedInstOperands, /*InsnID*/0,
        GIR_EraseFromParent, /*InsnID*/0,
        // GIR_Coverage, 2672,
        GIR_Done,
      // Label 1669: @109433
      GIM_Try, /*On fail goto*//*Label 1670*/ GIMT_Encode4(109482), // Rule ID 2673 //
        GIM_CheckFeatures, GIMT_Encode2(GIFBS_isGFX7Only),
        GIM_CheckPointerToAny, /*MI*/0, /*Op*/1, /*SizeInBits*/0,
        GIM_CheckComplexPattern, /*MI*/0, /*Op*/1, /*Renderer*/GIMT_Encode2(0), GIMT_Encode2(GICP_gi_smrd_imm32),
        // (ld:{ *:[v32f16] } (SMRDImm32:{ *:[iPTR] } i64:{ *:[i64] }:$sbase, i32:{ *:[i32] }:$offset))<<P:Predicate_unindexedload>><<P:Predicate_load>><<P:Predicate_smrd_load>>  =>  (S_LOAD_DWORDX16_IMM_ci:{ *:[v32f16] } ?:{ *:[i64] }:$sbase, ?:{ *:[i32] }:$offset, 0:{ *:[i32] })
        GIR_BuildMI, /*InsnID*/0, /*Opcode*/GIMT_Encode2(AMDGPU::S_LOAD_DWORDX16_IMM_ci),
        GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/0, // DstI[sdst]
        GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/0, // sbase
        GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/1, // offset
        GIR_AddImm8, /*InsnID*/0, /*Imm*/0,
        GIR_MergeMemOperands, /*InsnID*/0, /*NumInsns*/1, /*MergeInsnID's*/0,
        GIR_ConstrainSelectedInstOperands, /*InsnID*/0,
        GIR_EraseFromParent, /*InsnID*/0,
        // GIR_Coverage, 2673,
        GIR_Done,
      // Label 1670: @109482
      GIM_Try, /*On fail goto*//*Label 1671*/ GIMT_Encode4(109531), // Rule ID 2674 //
        GIM_CheckFeatures, GIMT_Encode2(GIFBS_isNotGFX9Plus),
        GIM_CheckPointerToAny, /*MI*/0, /*Op*/1, /*SizeInBits*/0,
        GIM_CheckComplexPattern, /*MI*/0, /*Op*/1, /*Renderer*/GIMT_Encode2(0), GIMT_Encode2(GICP_gi_smrd_sgpr),
        // (ld:{ *:[v32f16] } (SMRDSgpr:{ *:[iPTR] } i64:{ *:[i64] }:$sbase, i32:{ *:[i32] }:$soffset))<<P:Predicate_unindexedload>><<P:Predicate_load>><<P:Predicate_smrd_load>>  =>  (S_LOAD_DWORDX16_SGPR:{ *:[v32f16] } ?:{ *:[i64] }:$sbase, ?:{ *:[i32] }:$soffset, 0:{ *:[i32] })
        GIR_BuildMI, /*InsnID*/0, /*Opcode*/GIMT_Encode2(AMDGPU::S_LOAD_DWORDX16_SGPR),
        GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/0, // DstI[sdst]
        GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/0, // sbase
        GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/1, // soffset
        GIR_AddImm8, /*InsnID*/0, /*Imm*/0,
        GIR_MergeMemOperands, /*InsnID*/0, /*NumInsns*/1, /*MergeInsnID's*/0,
        GIR_ConstrainSelectedInstOperands, /*InsnID*/0,
        GIR_EraseFromParent, /*InsnID*/0,
        // GIR_Coverage, 2674,
        GIR_Done,
      // Label 1671: @109531
      GIM_Try, /*On fail goto*//*Label 1672*/ GIMT_Encode4(109583), // Rule ID 2675 //
        GIM_CheckFeatures, GIMT_Encode2(GIFBS_isGFX9Plus),
        GIM_CheckPointerToAny, /*MI*/0, /*Op*/1, /*SizeInBits*/0,
        GIM_CheckComplexPattern, /*MI*/0, /*Op*/1, /*Renderer*/GIMT_Encode2(0), GIMT_Encode2(GICP_gi_smrd_sgpr),
        // (ld:{ *:[v32f16] } (SMRDSgpr:{ *:[iPTR] } i64:{ *:[i64] }:$sbase, i32:{ *:[i32] }:$soffset))<<P:Predicate_unindexedload>><<P:Predicate_load>><<P:Predicate_smrd_load>>  =>  (S_LOAD_DWORDX16_SGPR_IMM:{ *:[v32f16] } ?:{ *:[i64] }:$sbase, ?:{ *:[i32] }:$soffset, 0:{ *:[i32] }, 0:{ *:[i32] })
        GIR_BuildMI, /*InsnID*/0, /*Opcode*/GIMT_Encode2(AMDGPU::S_LOAD_DWORDX16_SGPR_IMM),
        GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/0, // DstI[sdst]
        GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/0, // sbase
        GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/1, // soffset
        GIR_AddImm8, /*InsnID*/0, /*Imm*/0,
        GIR_AddImm8, /*InsnID*/0, /*Imm*/0,
        GIR_MergeMemOperands, /*InsnID*/0, /*NumInsns*/1, /*MergeInsnID's*/0,
        GIR_ConstrainSelectedInstOperands, /*InsnID*/0,
        GIR_EraseFromParent, /*InsnID*/0,
        // GIR_Coverage, 2675,
        GIR_Done,
      // Label 1672: @109583
      GIM_Try, /*On fail goto*//*Label 1673*/ GIMT_Encode4(109629), // Rule ID 2678 //
        GIM_CheckPointerToAny, /*MI*/0, /*Op*/1, /*SizeInBits*/0,
        GIM_CheckComplexPattern, /*MI*/0, /*Op*/1, /*Renderer*/GIMT_Encode2(0), GIMT_Encode2(GICP_gi_smrd_imm),
        // (ld:{ *:[v32bf16] } (SMRDImm:{ *:[iPTR] } i64:{ *:[i64] }:$sbase, i32:{ *:[i32] }:$offset))<<P:Predicate_unindexedload>><<P:Predicate_load>><<P:Predicate_smrd_load>>  =>  (S_LOAD_DWORDX16_IMM:{ *:[v32bf16] } ?:{ *:[i64] }:$sbase, ?:{ *:[i32] }:$offset, 0:{ *:[i32] })
        GIR_BuildMI, /*InsnID*/0, /*Opcode*/GIMT_Encode2(AMDGPU::S_LOAD_DWORDX16_IMM),
        GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/0, // DstI[sdst]
        GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/0, // sbase
        GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/1, // offset
        GIR_AddImm8, /*InsnID*/0, /*Imm*/0,
        GIR_MergeMemOperands, /*InsnID*/0, /*NumInsns*/1, /*MergeInsnID's*/0,
        GIR_ConstrainSelectedInstOperands, /*InsnID*/0,
        GIR_EraseFromParent, /*InsnID*/0,
        // GIR_Coverage, 2678,
        GIR_Done,
      // Label 1673: @109629
      GIM_Try, /*On fail goto*//*Label 1674*/ GIMT_Encode4(109678), // Rule ID 2679 //
        GIM_CheckFeatures, GIMT_Encode2(GIFBS_isGFX7Only),
        GIM_CheckPointerToAny, /*MI*/0, /*Op*/1, /*SizeInBits*/0,
        GIM_CheckComplexPattern, /*MI*/0, /*Op*/1, /*Renderer*/GIMT_Encode2(0), GIMT_Encode2(GICP_gi_smrd_imm32),
        // (ld:{ *:[v32bf16] } (SMRDImm32:{ *:[iPTR] } i64:{ *:[i64] }:$sbase, i32:{ *:[i32] }:$offset))<<P:Predicate_unindexedload>><<P:Predicate_load>><<P:Predicate_smrd_load>>  =>  (S_LOAD_DWORDX16_IMM_ci:{ *:[v32bf16] } ?:{ *:[i64] }:$sbase, ?:{ *:[i32] }:$offset, 0:{ *:[i32] })
        GIR_BuildMI, /*InsnID*/0, /*Opcode*/GIMT_Encode2(AMDGPU::S_LOAD_DWORDX16_IMM_ci),
        GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/0, // DstI[sdst]
        GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/0, // sbase
        GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/1, // offset
        GIR_AddImm8, /*InsnID*/0, /*Imm*/0,
        GIR_MergeMemOperands, /*InsnID*/0, /*NumInsns*/1, /*MergeInsnID's*/0,
        GIR_ConstrainSelectedInstOperands, /*InsnID*/0,
        GIR_EraseFromParent, /*InsnID*/0,
        // GIR_Coverage, 2679,
        GIR_Done,
      // Label 1674: @109678
      GIM_Try, /*On fail goto*//*Label 1675*/ GIMT_Encode4(109727), // Rule ID 2680 //
        GIM_CheckFeatures, GIMT_Encode2(GIFBS_isNotGFX9Plus),
        GIM_CheckPointerToAny, /*MI*/0, /*Op*/1, /*SizeInBits*/0,
        GIM_CheckComplexPattern, /*MI*/0, /*Op*/1, /*Renderer*/GIMT_Encode2(0), GIMT_Encode2(GICP_gi_smrd_sgpr),
        // (ld:{ *:[v32bf16] } (SMRDSgpr:{ *:[iPTR] } i64:{ *:[i64] }:$sbase, i32:{ *:[i32] }:$soffset))<<P:Predicate_unindexedload>><<P:Predicate_load>><<P:Predicate_smrd_load>>  =>  (S_LOAD_DWORDX16_SGPR:{ *:[v32bf16] } ?:{ *:[i64] }:$sbase, ?:{ *:[i32] }:$soffset, 0:{ *:[i32] })
        GIR_BuildMI, /*InsnID*/0, /*Opcode*/GIMT_Encode2(AMDGPU::S_LOAD_DWORDX16_SGPR),
        GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/0, // DstI[sdst]
        GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/0, // sbase
        GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/1, // soffset
        GIR_AddImm8, /*InsnID*/0, /*Imm*/0,
        GIR_MergeMemOperands, /*InsnID*/0, /*NumInsns*/1, /*MergeInsnID's*/0,
        GIR_ConstrainSelectedInstOperands, /*InsnID*/0,
        GIR_EraseFromParent, /*InsnID*/0,
        // GIR_Coverage, 2680,
        GIR_Done,
      // Label 1675: @109727
      GIM_Try, /*On fail goto*//*Label 1676*/ GIMT_Encode4(109779), // Rule ID 2681 //
        GIM_CheckFeatures, GIMT_Encode2(GIFBS_isGFX9Plus),
        GIM_CheckPointerToAny, /*MI*/0, /*Op*/1, /*SizeInBits*/0,
        GIM_CheckComplexPattern, /*MI*/0, /*Op*/1, /*Renderer*/GIMT_Encode2(0), GIMT_Encode2(GICP_gi_smrd_sgpr),
        // (ld:{ *:[v32bf16] } (SMRDSgpr:{ *:[iPTR] } i64:{ *:[i64] }:$sbase, i32:{ *:[i32] }:$soffset))<<P:Predicate_unindexedload>><<P:Predicate_load>><<P:Predicate_smrd_load>>  =>  (S_LOAD_DWORDX16_SGPR_IMM:{ *:[v32bf16] } ?:{ *:[i64] }:$sbase, ?:{ *:[i32] }:$soffset, 0:{ *:[i32] }, 0:{ *:[i32] })
        GIR_BuildMI, /*InsnID*/0, /*Opcode*/GIMT_Encode2(AMDGPU::S_LOAD_DWORDX16_SGPR_IMM),
        GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/0, // DstI[sdst]
        GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/0, // sbase
        GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/1, // soffset
        GIR_AddImm8, /*InsnID*/0, /*Imm*/0,
        GIR_AddImm8, /*InsnID*/0, /*Imm*/0,
        GIR_MergeMemOperands, /*InsnID*/0, /*NumInsns*/1, /*MergeInsnID's*/0,
        GIR_ConstrainSelectedInstOperands, /*InsnID*/0,
        GIR_EraseFromParent, /*InsnID*/0,
        // GIR_Coverage, 2681,
        GIR_Done,
      // Label 1676: @109779
      GIM_Try, /*On fail goto*//*Label 1677*/ GIMT_Encode4(109820), // Rule ID 2671 //
        // MIs[0] sbase
        GIM_CheckPointerToAny, /*MI*/0, /*Op*/1, /*SizeInBits*/64,
        GIM_CheckRegBankForClass, /*MI*/0, /*Op*/1, /*RC*/GIMT_Encode2(AMDGPU::SReg_64RegClassID),
        // (ld:{ *:[v32i16] } SReg_64:{ *:[i64] }:$sbase)<<P:Predicate_unindexedload>><<P:Predicate_load>><<P:Predicate_smrd_load>>  =>  (S_LOAD_DWORDX16_IMM:{ *:[v32i16] } i64:{ *:[i64] }:$sbase, 0:{ *:[i32] }, 0:{ *:[i32] })
        GIR_BuildMI, /*InsnID*/0, /*Opcode*/GIMT_Encode2(AMDGPU::S_LOAD_DWORDX16_IMM),
        GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/0, // DstI[sdst]
        GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/1, // sbase
        GIR_AddImm8, /*InsnID*/0, /*Imm*/0,
        GIR_AddImm8, /*InsnID*/0, /*Imm*/0,
        GIR_MergeMemOperands, /*InsnID*/0, /*NumInsns*/1, /*MergeInsnID's*/0,
        GIR_ConstrainSelectedInstOperands, /*InsnID*/0,
        GIR_EraseFromParent, /*InsnID*/0,
        // GIR_Coverage, 2671,
        GIR_Done,
      // Label 1677: @109820
      GIM_Try, /*On fail goto*//*Label 1678*/ GIMT_Encode4(109861), // Rule ID 2677 //
        // MIs[0] sbase
        GIM_CheckPointerToAny, /*MI*/0, /*Op*/1, /*SizeInBits*/64,
        GIM_CheckRegBankForClass, /*MI*/0, /*Op*/1, /*RC*/GIMT_Encode2(AMDGPU::SReg_64RegClassID),
        // (ld:{ *:[v32f16] } SReg_64:{ *:[i64] }:$sbase)<<P:Predicate_unindexedload>><<P:Predicate_load>><<P:Predicate_smrd_load>>  =>  (S_LOAD_DWORDX16_IMM:{ *:[v32f16] } i64:{ *:[i64] }:$sbase, 0:{ *:[i32] }, 0:{ *:[i32] })
        GIR_BuildMI, /*InsnID*/0, /*Opcode*/GIMT_Encode2(AMDGPU::S_LOAD_DWORDX16_IMM),
        GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/0, // DstI[sdst]
        GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/1, // sbase
        GIR_AddImm8, /*InsnID*/0, /*Imm*/0,
        GIR_AddImm8, /*InsnID*/0, /*Imm*/0,
        GIR_MergeMemOperands, /*InsnID*/0, /*NumInsns*/1, /*MergeInsnID's*/0,
        GIR_ConstrainSelectedInstOperands, /*InsnID*/0,
        GIR_EraseFromParent, /*InsnID*/0,
        // GIR_Coverage, 2677,
        GIR_Done,
      // Label 1678: @109861
      GIM_Try, /*On fail goto*//*Label 1679*/ GIMT_Encode4(109902), // Rule ID 2683 //
        // MIs[0] sbase
        GIM_CheckPointerToAny, /*MI*/0, /*Op*/1, /*SizeInBits*/64,
        GIM_CheckRegBankForClass, /*MI*/0, /*Op*/1, /*RC*/GIMT_Encode2(AMDGPU::SReg_64RegClassID),
        // (ld:{ *:[v32bf16] } SReg_64:{ *:[i64] }:$sbase)<<P:Predicate_unindexedload>><<P:Predicate_load>><<P:Predicate_smrd_load>>  =>  (S_LOAD_DWORDX16_IMM:{ *:[v32bf16] } i64:{ *:[i64] }:$sbase, 0:{ *:[i32] }, 0:{ *:[i32] })
        GIR_BuildMI, /*InsnID*/0, /*Opcode*/GIMT_Encode2(AMDGPU::S_LOAD_DWORDX16_IMM),
        GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/0, // DstI[sdst]
        GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/1, // sbase
        GIR_AddImm8, /*InsnID*/0, /*Imm*/0,
        GIR_AddImm8, /*InsnID*/0, /*Imm*/0,
        GIR_MergeMemOperands, /*InsnID*/0, /*NumInsns*/1, /*MergeInsnID's*/0,
        GIR_ConstrainSelectedInstOperands, /*InsnID*/0,
        GIR_EraseFromParent, /*InsnID*/0,
        // GIR_Coverage, 2683,
        GIR_Done,
      // Label 1679: @109902
      GIM_Reject,
    // Label 1661: @109903
    GIM_Reject,
    // Label 840: @109904
    GIM_Reject,
    // Label 13: @109905
    GIM_SwitchType, /*MI*/0, /*Op*/0, /*[*/GIMT_Encode2(8), GIMT_Encode2(10), /*)*//*default:*//*Label 1682*/ GIMT_Encode4(114296),
    /*GILLT_s16*//*Label 1680*/ GIMT_Encode4(109924),
    /*GILLT_s32*//*Label 1681*/ GIMT_Encode4(111027),
    // Label 1680: @109924
    GIM_Try, /*On fail goto*//*Label 1683*/ GIMT_Encode4(111026),
      GIM_CheckMemorySizeEqualTo, /*MI*/0, /*MMO*/0, /*Size*/GIMT_Encode4(1),
      GIM_Try, /*On fail goto*//*Label 1684*/ GIMT_Encode4(110006), // Rule ID 5360 //
        GIM_CheckFeatures, GIMT_Encode2(GIFBS_DisableFlatScratch_HasUnrestrictedSOffset),
        GIM_CheckMemoryAddressSpace, /*MI*/0, /*MMO*/0, /*NumAddrSpace*/1, /*AddrSpace*/5,
        GIM_CheckAtomicOrdering, /*MI*/0, /*Order*/(uint8_t)AtomicOrdering::NotAtomic,
        GIM_CheckRegBankForClass, /*MI*/0, /*Op*/0, /*RC*/GIMT_Encode2(AMDGPU::AV_32RegClassID),
        GIM_CheckPointerToAny, /*MI*/0, /*Op*/1, /*SizeInBits*/0,
        GIM_CheckComplexPattern, /*MI*/0, /*Op*/1, /*Renderer*/GIMT_Encode2(0), GIMT_Encode2(GICP_gi_mubuf_scratch_offset),
        // (ld:{ *:[i16] } (MUBUFScratchOffset:{ *:[iPTR] } v4i32:{ *:[v4i32] }:$srsrc, i32:{ *:[i32] }:$soffset, i32:{ *:[i32] }:$offset))<<P:Predicate_unindexedload>><<P:Predicate_sextload>><<P:Predicate_sextloadi8>><<P:Predicate_sextloadi8_private>>  =>  (BUFFER_LOAD_SBYTE_OFFSET:{ *:[i16] } ?:{ *:[v4i32] }:$srsrc, ?:{ *:[i32] }:$soffset, ?:{ *:[i32] }:$offset, 0:{ *:[i32] }, 0:{ *:[i1] })
        GIR_BuildMI, /*InsnID*/0, /*Opcode*/GIMT_Encode2(AMDGPU::BUFFER_LOAD_SBYTE_OFFSET),
        GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/0, // DstI[vdata]
        GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/0, // srsrc
        GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/1, // soffset
        GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/2, // offset
        GIR_AddImm8, /*InsnID*/0, /*Imm*/0,
        GIR_AddImm8, /*InsnID*/0, /*Imm*/0,
        GIR_MergeMemOperands, /*InsnID*/0, /*NumInsns*/1, /*MergeInsnID's*/0,
        GIR_ConstrainSelectedInstOperands, /*InsnID*/0,
        GIR_EraseFromParent, /*InsnID*/0,
        // GIR_Coverage, 5360,
        GIR_Done,
      // Label 1684: @110006
      GIM_Try, /*On fail goto*//*Label 1685*/ GIMT_Encode4(110076), // Rule ID 5362 //
        GIM_CheckFeatures, GIMT_Encode2(GIFBS_DisableFlatScratch),
        GIM_CheckMemoryAddressSpace, /*MI*/0, /*MMO*/0, /*NumAddrSpace*/1, /*AddrSpace*/5,
        GIM_CheckAtomicOrdering, /*MI*/0, /*Order*/(uint8_t)AtomicOrdering::NotAtomic,
        GIM_CheckRegBankForClass, /*MI*/0, /*Op*/0, /*RC*/GIMT_Encode2(AMDGPU::AV_32RegClassID),
        GIM_CheckPointerToAny, /*MI*/0, /*Op*/1, /*SizeInBits*/0,
        GIM_CheckComplexPattern, /*MI*/0, /*Op*/1, /*Renderer*/GIMT_Encode2(0), GIMT_Encode2(GICP_gi_mubuf_scratch_offset),
        // (ld:{ *:[i16] } (MUBUFScratchOffset:{ *:[iPTR] } v4i32:{ *:[v4i32] }:$srsrc, i32:{ *:[i32] }:$soffset, i32:{ *:[i32] }:$offset))<<P:Predicate_unindexedload>><<P:Predicate_sextload>><<P:Predicate_sextloadi8>><<P:Predicate_sextloadi8_private>>  =>  (BUFFER_LOAD_SBYTE_VBUFFER_OFFSET:{ *:[i16] } ?:{ *:[v4i32] }:$srsrc, ?:{ *:[i32] }:$soffset, ?:{ *:[i32] }:$offset, 0:{ *:[i32] }, 0:{ *:[i1] })
        GIR_BuildMI, /*InsnID*/0, /*Opcode*/GIMT_Encode2(AMDGPU::BUFFER_LOAD_SBYTE_VBUFFER_OFFSET),
        GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/0, // DstI[vdata]
        GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/0, // srsrc
        GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/1, // soffset
        GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/2, // offset
        GIR_AddImm8, /*InsnID*/0, /*Imm*/0,
        GIR_AddImm8, /*InsnID*/0, /*Imm*/0,
        GIR_MergeMemOperands, /*InsnID*/0, /*NumInsns*/1, /*MergeInsnID's*/0,
        GIR_ConstrainSelectedInstOperands, /*InsnID*/0,
        GIR_EraseFromParent, /*InsnID*/0,
        // GIR_Coverage, 5362,
        GIR_Done,
      // Label 1685: @110076
      GIM_Try, /*On fail goto*//*Label 1686*/ GIMT_Encode4(110143), // Rule ID 3418 //
        GIM_CheckFeatures, GIMT_Encode2(GIFBS_EnableFlatScratch_HasFlatScratchInsts_HasFlatScratchSVSMode),
        GIM_CheckMemoryAddressSpace, /*MI*/0, /*MMO*/0, /*NumAddrSpace*/1, /*AddrSpace*/5,
        GIM_CheckAtomicOrdering, /*MI*/0, /*Order*/(uint8_t)AtomicOrdering::NotAtomic,
        GIM_CheckRegBankForClass, /*MI*/0, /*Op*/0, /*RC*/GIMT_Encode2(AMDGPU::AV_32RegClassID),
        GIM_CheckPointerToAny, /*MI*/0, /*Op*/1, /*SizeInBits*/0,
        GIM_CheckComplexPattern, /*MI*/0, /*Op*/1, /*Renderer*/GIMT_Encode2(0), GIMT_Encode2(GICP_gi_flat_scratch_svaddr),
        // (ld:{ *:[i16] } (ScratchSVAddr:{ *:[iPTR] } VGPR_32:{ *:[i32] }:$vaddr, SGPR_32:{ *:[i32] }:$saddr, i32:{ *:[i32] }:$offset))<<P:Predicate_unindexedload>><<P:Predicate_sextload>><<P:Predicate_sextloadi8>><<P:Predicate_sextloadi8_private>>  =>  (SCRATCH_LOAD_SBYTE_SVS:{ *:[i16] } ?:{ *:[i32] }:$vaddr, ?:{ *:[i32] }:$saddr, ?:{ *:[i32] }:$offset, 0:{ *:[i32] })
        GIR_BuildMI, /*InsnID*/0, /*Opcode*/GIMT_Encode2(AMDGPU::SCRATCH_LOAD_SBYTE_SVS),
        GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/0, // DstI[vdst]
        GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/0, // vaddr
        GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/1, // saddr
        GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/2, // offset
        GIR_AddImm8, /*InsnID*/0, /*Imm*/0,
        GIR_MergeMemOperands, /*InsnID*/0, /*NumInsns*/1, /*MergeInsnID's*/0,
        GIR_ConstrainSelectedInstOperands, /*InsnID*/0,
        GIR_EraseFromParent, /*InsnID*/0,
        // GIR_Coverage, 3418,
        GIR_Done,
      // Label 1686: @110143
      GIM_Try, /*On fail goto*//*Label 1687*/ GIMT_Encode4(110205), // Rule ID 3417 //
        GIM_CheckFeatures, GIMT_Encode2(GIFBS_EnableFlatScratch_HasFlatScratchInsts),
        GIM_CheckMemoryAddressSpace, /*MI*/0, /*MMO*/0, /*NumAddrSpace*/1, /*AddrSpace*/5,
        GIM_CheckAtomicOrdering, /*MI*/0, /*Order*/(uint8_t)AtomicOrdering::NotAtomic,
        GIM_CheckRegBankForClass, /*MI*/0, /*Op*/0, /*RC*/GIMT_Encode2(AMDGPU::AV_32RegClassID),
        GIM_CheckPointerToAny, /*MI*/0, /*Op*/1, /*SizeInBits*/0,
        GIM_CheckComplexPattern, /*MI*/0, /*Op*/1, /*Renderer*/GIMT_Encode2(0), GIMT_Encode2(GICP_gi_flat_scratch_saddr),
        // (ld:{ *:[i16] } (ScratchSAddr:{ *:[iPTR] } SGPR_32:{ *:[i32] }:$saddr, i32:{ *:[i32] }:$offset))<<P:Predicate_unindexedload>><<P:Predicate_sextload>><<P:Predicate_sextloadi8>><<P:Predicate_sextloadi8_private>>  =>  (SCRATCH_LOAD_SBYTE_SADDR:{ *:[i16] } ?:{ *:[i32] }:$saddr, ?:{ *:[i32] }:$offset)
        GIR_BuildMI, /*InsnID*/0, /*Opcode*/GIMT_Encode2(AMDGPU::SCRATCH_LOAD_SBYTE_SADDR),
        GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/0, // DstI[vdst]
        GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/0, // saddr
        GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/1, // offset
        GIR_AddImm8, /*InsnID*/0, /*Imm*/0,
        GIR_MergeMemOperands, /*InsnID*/0, /*NumInsns*/1, /*MergeInsnID's*/0,
        GIR_ConstrainSelectedInstOperands, /*InsnID*/0,
        GIR_EraseFromParent, /*InsnID*/0,
        // GIR_Coverage, 3417,
        GIR_Done,
      // Label 1687: @110205
      GIM_Try, /*On fail goto*//*Label 1688*/ GIMT_Encode4(110267), // Rule ID 3416 //
        GIM_CheckFeatures, GIMT_Encode2(GIFBS_EnableFlatScratch_HasFlatScratchInsts),
        GIM_CheckMemoryAddressSpace, /*MI*/0, /*MMO*/0, /*NumAddrSpace*/1, /*AddrSpace*/5,
        GIM_CheckAtomicOrdering, /*MI*/0, /*Order*/(uint8_t)AtomicOrdering::NotAtomic,
        GIM_CheckRegBankForClass, /*MI*/0, /*Op*/0, /*RC*/GIMT_Encode2(AMDGPU::AV_32RegClassID),
        GIM_CheckPointerToAny, /*MI*/0, /*Op*/1, /*SizeInBits*/0,
        GIM_CheckComplexPattern, /*MI*/0, /*Op*/1, /*Renderer*/GIMT_Encode2(0), GIMT_Encode2(GICP_gi_flat_scratch_offset),
        // (ld:{ *:[i16] } (ScratchOffset:{ *:[iPTR] } VGPR_32:{ *:[i32] }:$vaddr, i32:{ *:[i32] }:$offset))<<P:Predicate_unindexedload>><<P:Predicate_sextload>><<P:Predicate_sextloadi8>><<P:Predicate_sextloadi8_private>>  =>  (SCRATCH_LOAD_SBYTE:{ *:[i16] } ?:{ *:[i32] }:$vaddr, ?:{ *:[i32] }:$offset)
        GIR_BuildMI, /*InsnID*/0, /*Opcode*/GIMT_Encode2(AMDGPU::SCRATCH_LOAD_SBYTE),
        GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/0, // DstI[vdst]
        GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/0, // vaddr
        GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/1, // offset
        GIR_AddImm8, /*InsnID*/0, /*Imm*/0,
        GIR_MergeMemOperands, /*InsnID*/0, /*NumInsns*/1, /*MergeInsnID's*/0,
        GIR_ConstrainSelectedInstOperands, /*InsnID*/0,
        GIR_EraseFromParent, /*InsnID*/0,
        // GIR_Coverage, 3416,
        GIR_Done,
      // Label 1688: @110267
      GIM_Try, /*On fail goto*//*Label 1689*/ GIMT_Encode4(110342), // Rule ID 5359 //
        GIM_CheckFeatures, GIMT_Encode2(GIFBS_DisableFlatScratch_HasUnrestrictedSOffset),
        GIM_CheckMemoryAddressSpace, /*MI*/0, /*MMO*/0, /*NumAddrSpace*/1, /*AddrSpace*/5,
        GIM_CheckAtomicOrdering, /*MI*/0, /*Order*/(uint8_t)AtomicOrdering::NotAtomic,
        GIM_CheckRegBankForClass, /*MI*/0, /*Op*/0, /*RC*/GIMT_Encode2(AMDGPU::AV_32RegClassID),
        GIM_CheckPointerToAny, /*MI*/0, /*Op*/1, /*SizeInBits*/0,
        GIM_CheckComplexPattern, /*MI*/0, /*Op*/1, /*Renderer*/GIMT_Encode2(0), GIMT_Encode2(GICP_gi_mubuf_scratch_offen),
        // (ld:{ *:[i16] } (MUBUFScratchOffen:{ *:[iPTR] } v4i32:{ *:[v4i32] }:$srsrc, i32:{ *:[i32] }:$vaddr, i32:{ *:[i32] }:$soffset, i32:{ *:[i32] }:$offset))<<P:Predicate_unindexedload>><<P:Predicate_sextload>><<P:Predicate_sextloadi8>><<P:Predicate_sextloadi8_private>>  =>  (BUFFER_LOAD_SBYTE_OFFEN:{ *:[i16] } ?:{ *:[i32] }:$vaddr, ?:{ *:[v4i32] }:$srsrc, ?:{ *:[i32] }:$soffset, ?:{ *:[i32] }:$offset, 0:{ *:[i32] }, 0:{ *:[i1] })
        GIR_BuildMI, /*InsnID*/0, /*Opcode*/GIMT_Encode2(AMDGPU::BUFFER_LOAD_SBYTE_OFFEN),
        GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/0, // DstI[vdata]
        GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/1, // vaddr
        GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/0, // srsrc
        GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/2, // soffset
        GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/3, // offset
        GIR_AddImm8, /*InsnID*/0, /*Imm*/0,
        GIR_AddImm8, /*InsnID*/0, /*Imm*/0,
        GIR_MergeMemOperands, /*InsnID*/0, /*NumInsns*/1, /*MergeInsnID's*/0,
        GIR_ConstrainSelectedInstOperands, /*InsnID*/0,
        GIR_EraseFromParent, /*InsnID*/0,
        // GIR_Coverage, 5359,
        GIR_Done,
      // Label 1689: @110342
      GIM_Try, /*On fail goto*//*Label 1690*/ GIMT_Encode4(110417), // Rule ID 5361 //
        GIM_CheckFeatures, GIMT_Encode2(GIFBS_DisableFlatScratch),
        GIM_CheckMemoryAddressSpace, /*MI*/0, /*MMO*/0, /*NumAddrSpace*/1, /*AddrSpace*/5,
        GIM_CheckAtomicOrdering, /*MI*/0, /*Order*/(uint8_t)AtomicOrdering::NotAtomic,
        GIM_CheckRegBankForClass, /*MI*/0, /*Op*/0, /*RC*/GIMT_Encode2(AMDGPU::AV_32RegClassID),
        GIM_CheckPointerToAny, /*MI*/0, /*Op*/1, /*SizeInBits*/0,
        GIM_CheckComplexPattern, /*MI*/0, /*Op*/1, /*Renderer*/GIMT_Encode2(0), GIMT_Encode2(GICP_gi_mubuf_scratch_offen),
        // (ld:{ *:[i16] } (MUBUFScratchOffen:{ *:[iPTR] } v4i32:{ *:[v4i32] }:$srsrc, i32:{ *:[i32] }:$vaddr, i32:{ *:[i32] }:$soffset, i32:{ *:[i32] }:$offset))<<P:Predicate_unindexedload>><<P:Predicate_sextload>><<P:Predicate_sextloadi8>><<P:Predicate_sextloadi8_private>>  =>  (BUFFER_LOAD_SBYTE_VBUFFER_OFFEN:{ *:[i16] } ?:{ *:[i32] }:$vaddr, ?:{ *:[v4i32] }:$srsrc, ?:{ *:[i32] }:$soffset, ?:{ *:[i32] }:$offset, 0:{ *:[i32] }, 0:{ *:[i1] })
        GIR_BuildMI, /*InsnID*/0, /*Opcode*/GIMT_Encode2(AMDGPU::BUFFER_LOAD_SBYTE_VBUFFER_OFFEN),
        GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/0, // DstI[vdata]
        GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/1, // vaddr
        GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/0, // srsrc
        GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/2, // soffset
        GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/3, // offset
        GIR_AddImm8, /*InsnID*/0, /*Imm*/0,
        GIR_AddImm8, /*InsnID*/0, /*Imm*/0,
        GIR_MergeMemOperands, /*InsnID*/0, /*NumInsns*/1, /*MergeInsnID's*/0,
        GIR_ConstrainSelectedInstOperands, /*InsnID*/0,
        GIR_EraseFromParent, /*InsnID*/0,
        // GIR_Coverage, 5361,
        GIR_Done,
      // Label 1690: @110417
      GIM_Try, /*On fail goto*//*Label 1691*/ GIMT_Encode4(110488), // Rule ID 5331 //
        GIM_CheckFeatures, GIMT_Encode2(GIFBS_Has16BitInsts_HasUnrestrictedSOffset),
        GIM_CheckMemoryAddressSpace, /*MI*/0, /*MMO*/0, /*NumAddrSpace*/2, /*AddrSpace*/4, /*AddrSpace*/6,
        GIM_CheckAtomicOrdering, /*MI*/0, /*Order*/(uint8_t)AtomicOrdering::NotAtomic,
        GIM_CheckRegBankForClass, /*MI*/0, /*Op*/0, /*RC*/GIMT_Encode2(AMDGPU::AV_32RegClassID),
        GIM_CheckPointerToAny, /*MI*/0, /*Op*/1, /*SizeInBits*/0,
        GIM_CheckComplexPattern, /*MI*/0, /*Op*/1, /*Renderer*/GIMT_Encode2(0), GIMT_Encode2(GICP_gi_mubuf_offset),
        // (ld:{ *:[i16] } (MUBUFOffset:{ *:[iPTR] } v4i32:{ *:[v4i32] }:$srsrc, i32:{ *:[i32] }:$soffset, i32:{ *:[i32] }:$offset))<<P:Predicate_unindexedload>><<P:Predicate_sextload>><<P:Predicate_sextloadi8>><<P:Predicate_sextloadi8_constant>>  =>  (BUFFER_LOAD_SBYTE_OFFSET:{ *:[i16] } ?:{ *:[v4i32] }:$srsrc, ?:{ *:[i32] }:$soffset, ?:{ *:[i32] }:$offset)
        GIR_BuildMI, /*InsnID*/0, /*Opcode*/GIMT_Encode2(AMDGPU::BUFFER_LOAD_SBYTE_OFFSET),
        GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/0, // DstI[vdata]
        GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/0, // srsrc
        GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/1, // soffset
        GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/2, // offset
        GIR_AddImm8, /*InsnID*/0, /*Imm*/0,
        GIR_AddImm8, /*InsnID*/0, /*Imm*/0,
        GIR_MergeMemOperands, /*InsnID*/0, /*NumInsns*/1, /*MergeInsnID's*/0,
        GIR_ConstrainSelectedInstOperands, /*InsnID*/0,
        GIR_EraseFromParent, /*InsnID*/0,
        // GIR_Coverage, 5331,
        GIR_Done,
      // Label 1691: @110488
      GIM_Try, /*On fail goto*//*Label 1692*/ GIMT_Encode4(110559), // Rule ID 5332 //
        GIM_CheckFeatures, GIMT_Encode2(GIFBS_Has16BitInsts),
        GIM_CheckMemoryAddressSpace, /*MI*/0, /*MMO*/0, /*NumAddrSpace*/2, /*AddrSpace*/4, /*AddrSpace*/6,
        GIM_CheckAtomicOrdering, /*MI*/0, /*Order*/(uint8_t)AtomicOrdering::NotAtomic,
        GIM_CheckRegBankForClass, /*MI*/0, /*Op*/0, /*RC*/GIMT_Encode2(AMDGPU::AV_32RegClassID),
        GIM_CheckPointerToAny, /*MI*/0, /*Op*/1, /*SizeInBits*/0,
        GIM_CheckComplexPattern, /*MI*/0, /*Op*/1, /*Renderer*/GIMT_Encode2(0), GIMT_Encode2(GICP_gi_mubuf_offset),
        // (ld:{ *:[i16] } (MUBUFOffset:{ *:[iPTR] } v4i32:{ *:[v4i32] }:$srsrc, i32:{ *:[i32] }:$soffset, i32:{ *:[i32] }:$offset))<<P:Predicate_unindexedload>><<P:Predicate_sextload>><<P:Predicate_sextloadi8>><<P:Predicate_sextloadi8_constant>>  =>  (BUFFER_LOAD_SBYTE_VBUFFER_OFFSET:{ *:[i16] } ?:{ *:[v4i32] }:$srsrc, ?:{ *:[i32] }:$soffset, ?:{ *:[i32] }:$offset)
        GIR_BuildMI, /*InsnID*/0, /*Opcode*/GIMT_Encode2(AMDGPU::BUFFER_LOAD_SBYTE_VBUFFER_OFFSET),
        GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/0, // DstI[vdata]
        GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/0, // srsrc
        GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/1, // soffset
        GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/2, // offset
        GIR_AddImm8, /*InsnID*/0, /*Imm*/0,
        GIR_AddImm8, /*InsnID*/0, /*Imm*/0,
        GIR_MergeMemOperands, /*InsnID*/0, /*NumInsns*/1, /*MergeInsnID's*/0,
        GIR_ConstrainSelectedInstOperands, /*InsnID*/0,
        GIR_EraseFromParent, /*InsnID*/0,
        // GIR_Coverage, 5332,
        GIR_Done,
      // Label 1692: @110559
      GIM_Try, /*On fail goto*//*Label 1693*/ GIMT_Encode4(110631), // Rule ID 5337 //
        GIM_CheckFeatures, GIMT_Encode2(GIFBS_Has16BitInsts_HasUnrestrictedSOffset),
        GIM_CheckMemoryAddressSpace, /*MI*/0, /*MMO*/0, /*NumAddrSpace*/3, /*AddrSpace*/1, /*AddrSpace*/4, /*AddrSpace*/6,
        GIM_CheckAtomicOrdering, /*MI*/0, /*Order*/(uint8_t)AtomicOrdering::NotAtomic,
        GIM_CheckRegBankForClass, /*MI*/0, /*Op*/0, /*RC*/GIMT_Encode2(AMDGPU::AV_32RegClassID),
        GIM_CheckPointerToAny, /*MI*/0, /*Op*/1, /*SizeInBits*/0,
        GIM_CheckComplexPattern, /*MI*/0, /*Op*/1, /*Renderer*/GIMT_Encode2(0), GIMT_Encode2(GICP_gi_mubuf_offset),
        // (ld:{ *:[i16] } (MUBUFOffset:{ *:[iPTR] } v4i32:{ *:[v4i32] }:$srsrc, i32:{ *:[i32] }:$soffset, i32:{ *:[i32] }:$offset))<<P:Predicate_unindexedload>><<P:Predicate_sextload>><<P:Predicate_sextloadi8>><<P:Predicate_sextloadi8_global>>  =>  (BUFFER_LOAD_SBYTE_OFFSET:{ *:[i16] } ?:{ *:[v4i32] }:$srsrc, ?:{ *:[i32] }:$soffset, ?:{ *:[i32] }:$offset)
        GIR_BuildMI, /*InsnID*/0, /*Opcode*/GIMT_Encode2(AMDGPU::BUFFER_LOAD_SBYTE_OFFSET),
        GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/0, // DstI[vdata]
        GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/0, // srsrc
        GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/1, // soffset
        GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/2, // offset
        GIR_AddImm8, /*InsnID*/0, /*Imm*/0,
        GIR_AddImm8, /*InsnID*/0, /*Imm*/0,
        GIR_MergeMemOperands, /*InsnID*/0, /*NumInsns*/1, /*MergeInsnID's*/0,
        GIR_ConstrainSelectedInstOperands, /*InsnID*/0,
        GIR_EraseFromParent, /*InsnID*/0,
        // GIR_Coverage, 5337,
        GIR_Done,
      // Label 1693: @110631
      GIM_Try, /*On fail goto*//*Label 1694*/ GIMT_Encode4(110703), // Rule ID 5338 //
        GIM_CheckFeatures, GIMT_Encode2(GIFBS_Has16BitInsts),
        GIM_CheckMemoryAddressSpace, /*MI*/0, /*MMO*/0, /*NumAddrSpace*/3, /*AddrSpace*/1, /*AddrSpace*/4, /*AddrSpace*/6,
        GIM_CheckAtomicOrdering, /*MI*/0, /*Order*/(uint8_t)AtomicOrdering::NotAtomic,
        GIM_CheckRegBankForClass, /*MI*/0, /*Op*/0, /*RC*/GIMT_Encode2(AMDGPU::AV_32RegClassID),
        GIM_CheckPointerToAny, /*MI*/0, /*Op*/1, /*SizeInBits*/0,
        GIM_CheckComplexPattern, /*MI*/0, /*Op*/1, /*Renderer*/GIMT_Encode2(0), GIMT_Encode2(GICP_gi_mubuf_offset),
        // (ld:{ *:[i16] } (MUBUFOffset:{ *:[iPTR] } v4i32:{ *:[v4i32] }:$srsrc, i32:{ *:[i32] }:$soffset, i32:{ *:[i32] }:$offset))<<P:Predicate_unindexedload>><<P:Predicate_sextload>><<P:Predicate_sextloadi8>><<P:Predicate_sextloadi8_global>>  =>  (BUFFER_LOAD_SBYTE_VBUFFER_OFFSET:{ *:[i16] } ?:{ *:[v4i32] }:$srsrc, ?:{ *:[i32] }:$soffset, ?:{ *:[i32] }:$offset)
        GIR_BuildMI, /*InsnID*/0, /*Opcode*/GIMT_Encode2(AMDGPU::BUFFER_LOAD_SBYTE_VBUFFER_OFFSET),
        GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/0, // DstI[vdata]
        GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/0, // srsrc
        GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/1, // soffset
        GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/2, // offset
        GIR_AddImm8, /*InsnID*/0, /*Imm*/0,
        GIR_AddImm8, /*InsnID*/0, /*Imm*/0,
        GIR_MergeMemOperands, /*InsnID*/0, /*NumInsns*/1, /*MergeInsnID's*/0,
        GIR_ConstrainSelectedInstOperands, /*InsnID*/0,
        GIR_EraseFromParent, /*InsnID*/0,
        // GIR_Coverage, 5338,
        GIR_Done,
      // Label 1694: @110703
      GIM_Try, /*On fail goto*//*Label 1695*/ GIMT_Encode4(110765), // Rule ID 6569 //
        GIM_CheckFeatures, GIMT_Encode2(GIFBS_LDSRequiresM0Init),
        GIM_CheckMemoryAddressSpace, /*MI*/0, /*MMO*/0, /*NumAddrSpace*/1, /*AddrSpace*/3,
        GIM_CheckAtomicOrdering, /*MI*/0, /*Order*/(uint8_t)AtomicOrdering::NotAtomic,
        GIM_CheckRegBankForClass, /*MI*/0, /*Op*/0, /*RC*/GIMT_Encode2(AMDGPU::AV_32RegClassID),
        GIM_CheckPointerToAny, /*MI*/0, /*Op*/1, /*SizeInBits*/0,
        GIM_CheckComplexPattern, /*MI*/0, /*Op*/1, /*Renderer*/GIMT_Encode2(0), GIMT_Encode2(GICP_gi_ds_1addr_1offset),
        // (AMDGPUld_glue:{ *:[i16] } (DS1Addr1Offset:{ *:[iPTR] } i32:{ *:[i32] }:$ptr, i32:{ *:[i32] }:$offset))<<P:Predicate_unindexedload_glue>><<P:Predicate_sextload_glue>><<P:Predicate_sextloadi8_glue>><<P:Predicate_sextloadi8_local_m0>>  =>  (DS_READ_I8:{ *:[i16] } ?:{ *:[i32] }:$ptr, offset:{ *:[i32] }:$offset, 0:{ *:[i1] })
        GIR_BuildMI, /*InsnID*/0, /*Opcode*/GIMT_Encode2(AMDGPU::DS_READ_I8),
        GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/0, // DstI[vdst]
        GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/0, // ptr
        GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/1, // offset
        GIR_AddImm8, /*InsnID*/0, /*Imm*/0,
        GIR_MergeMemOperands, /*InsnID*/0, /*NumInsns*/1, /*MergeInsnID's*/0,
        GIR_ConstrainSelectedInstOperands, /*InsnID*/0,
        GIR_EraseFromParent, /*InsnID*/0,
        // GIR_Coverage, 6569,
        GIR_Done,
      // Label 1695: @110765
      GIM_Try, /*On fail goto*//*Label 1696*/ GIMT_Encode4(110827), // Rule ID 6570 //
        GIM_CheckFeatures, GIMT_Encode2(GIFBS_NotLDSRequiresM0Init),
        GIM_CheckMemoryAddressSpace, /*MI*/0, /*MMO*/0, /*NumAddrSpace*/1, /*AddrSpace*/3,
        GIM_CheckAtomicOrdering, /*MI*/0, /*Order*/(uint8_t)AtomicOrdering::NotAtomic,
        GIM_CheckRegBankForClass, /*MI*/0, /*Op*/0, /*RC*/GIMT_Encode2(AMDGPU::AV_32RegClassID),
        GIM_CheckPointerToAny, /*MI*/0, /*Op*/1, /*SizeInBits*/0,
        GIM_CheckComplexPattern, /*MI*/0, /*Op*/1, /*Renderer*/GIMT_Encode2(0), GIMT_Encode2(GICP_gi_ds_1addr_1offset),
        // (ld:{ *:[i16] } (DS1Addr1Offset:{ *:[iPTR] } i32:{ *:[i32] }:$ptr, i32:{ *:[i32] }:$offset))<<P:Predicate_unindexedload>><<P:Predicate_sextload>><<P:Predicate_sextloadi8>><<P:Predicate_sextloadi8_local>>  =>  (DS_READ_I8_gfx9:{ *:[i16] } ?:{ *:[i32] }:$ptr, offset:{ *:[i32] }:$offset, 0:{ *:[i1] })
        GIR_BuildMI, /*InsnID*/0, /*Opcode*/GIMT_Encode2(AMDGPU::DS_READ_I8_gfx9),
        GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/0, // DstI[vdst]
        GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/0, // ptr
        GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/1, // offset
        GIR_AddImm8, /*InsnID*/0, /*Imm*/0,
        GIR_MergeMemOperands, /*InsnID*/0, /*NumInsns*/1, /*MergeInsnID's*/0,
        GIR_ConstrainSelectedInstOperands, /*InsnID*/0,
        GIR_EraseFromParent, /*InsnID*/0,
        // GIR_Coverage, 6570,
        GIR_Done,
      // Label 1696: @110827
      GIM_Try, /*On fail goto*//*Label 1697*/ GIMT_Encode4(110896), // Rule ID 2985 //
        GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasFlatGlobalInsts),
        GIM_CheckMemoryAddressSpace, /*MI*/0, /*MMO*/0, /*NumAddrSpace*/3, /*AddrSpace*/1, /*AddrSpace*/4, /*AddrSpace*/6,
        GIM_CheckAtomicOrdering, /*MI*/0, /*Order*/(uint8_t)AtomicOrdering::NotAtomic,
        GIM_CheckRegBankForClass, /*MI*/0, /*Op*/0, /*RC*/GIMT_Encode2(AMDGPU::AV_32RegClassID),
        GIM_CheckPointerToAny, /*MI*/0, /*Op*/1, /*SizeInBits*/0,
        GIM_CheckComplexPattern, /*MI*/0, /*Op*/1, /*Renderer*/GIMT_Encode2(0), GIMT_Encode2(GICP_gi_global_saddr),
        // (ld:{ *:[i16] } (GlobalSAddr:{ *:[iPTR] } SReg_64:{ *:[i64] }:$saddr, VGPR_32:{ *:[i32] }:$voffset, i32:{ *:[i32] }:$offset))<<P:Predicate_unindexedload>><<P:Predicate_sextload>><<P:Predicate_sextloadi8>><<P:Predicate_sextloadi8_global>>  =>  (GLOBAL_LOAD_SBYTE_SADDR:{ *:[i16] } ?:{ *:[i64] }:$saddr, ?:{ *:[i32] }:$voffset, ?:{ *:[i32] }:$offset, 0:{ *:[i32] })
        GIR_BuildMI, /*InsnID*/0, /*Opcode*/GIMT_Encode2(AMDGPU::GLOBAL_LOAD_SBYTE_SADDR),
        GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/0, // DstI[vdst]
        GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/0, // saddr
        GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/1, // voffset
        GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/2, // offset
        GIR_AddImm8, /*InsnID*/0, /*Imm*/0,
        GIR_MergeMemOperands, /*InsnID*/0, /*NumInsns*/1, /*MergeInsnID's*/0,
        GIR_ConstrainSelectedInstOperands, /*InsnID*/0,
        GIR_EraseFromParent, /*InsnID*/0,
        // GIR_Coverage, 2985,
        GIR_Done,
      // Label 1697: @110896
      GIM_Try, /*On fail goto*//*Label 1698*/ GIMT_Encode4(110960), // Rule ID 2984 //
        GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasFlatGlobalInsts),
        GIM_CheckMemoryAddressSpace, /*MI*/0, /*MMO*/0, /*NumAddrSpace*/3, /*AddrSpace*/1, /*AddrSpace*/4, /*AddrSpace*/6,
        GIM_CheckAtomicOrdering, /*MI*/0, /*Order*/(uint8_t)AtomicOrdering::NotAtomic,
        GIM_CheckRegBankForClass, /*MI*/0, /*Op*/0, /*RC*/GIMT_Encode2(AMDGPU::AV_32RegClassID),
        GIM_CheckPointerToAny, /*MI*/0, /*Op*/1, /*SizeInBits*/0,
        GIM_CheckComplexPattern, /*MI*/0, /*Op*/1, /*Renderer*/GIMT_Encode2(0), GIMT_Encode2(GICP_gi_global_offset),
        // (ld:{ *:[i16] } (GlobalOffset:{ *:[iPTR] } VReg_64:{ *:[i64] }:$vaddr, i32:{ *:[i32] }:$offset))<<P:Predicate_unindexedload>><<P:Predicate_sextload>><<P:Predicate_sextloadi8>><<P:Predicate_sextloadi8_global>>  =>  (GLOBAL_LOAD_SBYTE:{ *:[i16] } ?:{ *:[i64] }:$vaddr, ?:{ *:[i32] }:$offset)
        GIR_BuildMI, /*InsnID*/0, /*Opcode*/GIMT_Encode2(AMDGPU::GLOBAL_LOAD_SBYTE),
        GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/0, // DstI[vdst]
        GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/0, // vaddr
        GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/1, // offset
        GIR_AddImm8, /*InsnID*/0, /*Imm*/0,
        GIR_MergeMemOperands, /*InsnID*/0, /*NumInsns*/1, /*MergeInsnID's*/0,
        GIR_ConstrainSelectedInstOperands, /*InsnID*/0,
        GIR_EraseFromParent, /*InsnID*/0,
        // GIR_Coverage, 2984,
        GIR_Done,
      // Label 1698: @110960
      GIM_Try, /*On fail goto*//*Label 1699*/ GIMT_Encode4(111025), // Rule ID 2760 //
        GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasFlatAddressSpace),
        GIM_CheckMemoryAddressSpace, /*MI*/0, /*MMO*/0, /*NumAddrSpace*/4, /*AddrSpace*/0, /*AddrSpace*/1, /*AddrSpace*/4, /*AddrSpace*/6,
        GIM_CheckAtomicOrdering, /*MI*/0, /*Order*/(uint8_t)AtomicOrdering::NotAtomic,
        GIM_CheckRegBankForClass, /*MI*/0, /*Op*/0, /*RC*/GIMT_Encode2(AMDGPU::AV_32RegClassID),
        GIM_CheckPointerToAny, /*MI*/0, /*Op*/1, /*SizeInBits*/0,
        GIM_CheckComplexPattern, /*MI*/0, /*Op*/1, /*Renderer*/GIMT_Encode2(0), GIMT_Encode2(GICP_gi_flat_offset),
        // (ld:{ *:[i16] } (FlatOffset:{ *:[iPTR] } i64:{ *:[i64] }:$vaddr, i32:{ *:[i32] }:$offset))<<P:Predicate_unindexedload>><<P:Predicate_sextload>><<P:Predicate_sextloadi8>><<P:Predicate_sextloadi8_flat>>  =>  (FLAT_LOAD_SBYTE:{ *:[i16] } ?:{ *:[i64] }:$vaddr, ?:{ *:[i32] }:$offset)
        GIR_BuildMI, /*InsnID*/0, /*Opcode*/GIMT_Encode2(AMDGPU::FLAT_LOAD_SBYTE),
        GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/0, // DstI[vdst]
        GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/0, // vaddr
        GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/1, // offset
        GIR_AddImm8, /*InsnID*/0, /*Imm*/0,
        GIR_MergeMemOperands, /*InsnID*/0, /*NumInsns*/1, /*MergeInsnID's*/0,
        GIR_ConstrainSelectedInstOperands, /*InsnID*/0,
        GIR_EraseFromParent, /*InsnID*/0,
        // GIR_Coverage, 2760,
        GIR_Done,
      // Label 1699: @111025
      GIM_Reject,
    // Label 1683: @111026
    GIM_Reject,
    // Label 1681: @111027
    GIM_Try, /*On fail goto*//*Label 1700*/ GIMT_Encode4(111100), // Rule ID 2429 //
      GIM_CheckFeatures, GIMT_Encode2(GIFBS_isGFX12Plus),
      GIM_CheckMemorySizeEqualTo, /*MI*/0, /*MMO*/0, /*Size*/GIMT_Encode4(1),
      GIM_CheckAtomicOrdering, /*MI*/0, /*Order*/(uint8_t)AtomicOrdering::NotAtomic,
      GIM_CheckRegBankForClass, /*MI*/0, /*Op*/0, /*RC*/GIMT_Encode2(AMDGPU::SReg_32_XM0_XEXECRegClassID),
      GIM_CheckPointerToAny, /*MI*/0, /*Op*/1, /*SizeInBits*/0,
      GIM_CheckCxxInsnPredicate, /*MI*/0, /*FnId*/GIMT_Encode2(GICXXPred_MI_Predicate_smrd_sextloadi8),
      GIM_CheckComplexPattern, /*MI*/0, /*Op*/1, /*Renderer*/GIMT_Encode2(0), GIMT_Encode2(GICP_gi_smrd_sgpr_imm),
      // (ld:{ *:[i32] } (SMRDSgprImm:{ *:[iPTR] } i64:{ *:[i64] }:$sbase, i32:{ *:[i32] }:$soffset, i32:{ *:[i32] }:$offset))<<P:Predicate_unindexedload>><<P:Predicate_sextload>><<P:Predicate_sextloadi8>><<P:Predicate_smrd_sextloadi8>>  =>  (S_LOAD_I8_SGPR_IMM:{ *:[i32] } ?:{ *:[i64] }:$sbase, ?:{ *:[i32] }:$soffset, ?:{ *:[i32] }:$offset, 0:{ *:[i32] })
      GIR_BuildMI, /*InsnID*/0, /*Opcode*/GIMT_Encode2(AMDGPU::S_LOAD_I8_SGPR_IMM),
      GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/0, // DstI[sdst]
      GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/0, // sbase
      GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/1, // soffset
      GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/2, // offset
      GIR_AddImm8, /*InsnID*/0, /*Imm*/0,
      GIR_MergeMemOperands, /*InsnID*/0, /*NumInsns*/1, /*MergeInsnID's*/0,
      GIR_ConstrainSelectedInstOperands, /*InsnID*/0,
      GIR_EraseFromParent, /*InsnID*/0,
      // GIR_Coverage, 2429,
      GIR_Done,
    // Label 1700: @111100
    GIM_Try, /*On fail goto*//*Label 1701*/ GIMT_Encode4(111173), // Rule ID 2441 //
      GIM_CheckFeatures, GIMT_Encode2(GIFBS_isGFX12Plus),
      GIM_CheckMemorySizeEqualTo, /*MI*/0, /*MMO*/0, /*Size*/GIMT_Encode4(2),
      GIM_CheckAtomicOrdering, /*MI*/0, /*Order*/(uint8_t)AtomicOrdering::NotAtomic,
      GIM_CheckRegBankForClass, /*MI*/0, /*Op*/0, /*RC*/GIMT_Encode2(AMDGPU::SReg_32_XM0_XEXECRegClassID),
      GIM_CheckPointerToAny, /*MI*/0, /*Op*/1, /*SizeInBits*/0,
      GIM_CheckCxxInsnPredicate, /*MI*/0, /*FnId*/GIMT_Encode2(GICXXPred_MI_Predicate_smrd_sextloadi16),
      GIM_CheckComplexPattern, /*MI*/0, /*Op*/1, /*Renderer*/GIMT_Encode2(0), GIMT_Encode2(GICP_gi_smrd_sgpr_imm),
      // (ld:{ *:[i32] } (SMRDSgprImm:{ *:[iPTR] } i64:{ *:[i64] }:$sbase, i32:{ *:[i32] }:$soffset, i32:{ *:[i32] }:$offset))<<P:Predicate_unindexedload>><<P:Predicate_sextload>><<P:Predicate_sextloadi16>><<P:Predicate_smrd_sextloadi16>>  =>  (S_LOAD_I16_SGPR_IMM:{ *:[i32] } ?:{ *:[i64] }:$sbase, ?:{ *:[i32] }:$soffset, ?:{ *:[i32] }:$offset, 0:{ *:[i32] })
      GIR_BuildMI, /*InsnID*/0, /*Opcode*/GIMT_Encode2(AMDGPU::S_LOAD_I16_SGPR_IMM),
      GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/0, // DstI[sdst]
      GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/0, // sbase
      GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/1, // soffset
      GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/2, // offset
      GIR_AddImm8, /*InsnID*/0, /*Imm*/0,
      GIR_MergeMemOperands, /*InsnID*/0, /*NumInsns*/1, /*MergeInsnID's*/0,
      GIR_ConstrainSelectedInstOperands, /*InsnID*/0,
      GIR_EraseFromParent, /*InsnID*/0,
      // GIR_Coverage, 2441,
      GIR_Done,
    // Label 1701: @111173
    GIM_Try, /*On fail goto*//*Label 1702*/ GIMT_Encode4(111241), // Rule ID 2427 //
      GIM_CheckFeatures, GIMT_Encode2(GIFBS_isGFX12Plus),
      GIM_CheckMemorySizeEqualTo, /*MI*/0, /*MMO*/0, /*Size*/GIMT_Encode4(1),
      GIM_CheckAtomicOrdering, /*MI*/0, /*Order*/(uint8_t)AtomicOrdering::NotAtomic,
      GIM_CheckRegBankForClass, /*MI*/0, /*Op*/0, /*RC*/GIMT_Encode2(AMDGPU::SReg_32_XM0_XEXECRegClassID),
      GIM_CheckPointerToAny, /*MI*/0, /*Op*/1, /*SizeInBits*/0,
      GIM_CheckCxxInsnPredicate, /*MI*/0, /*FnId*/GIMT_Encode2(GICXXPred_MI_Predicate_smrd_sextloadi8),
      GIM_CheckComplexPattern, /*MI*/0, /*Op*/1, /*Renderer*/GIMT_Encode2(0), GIMT_Encode2(GICP_gi_smrd_imm),
      // (ld:{ *:[i32] } (SMRDImm:{ *:[iPTR] } i64:{ *:[i64] }:$sbase, i32:{ *:[i32] }:$offset))<<P:Predicate_unindexedload>><<P:Predicate_sextload>><<P:Predicate_sextloadi8>><<P:Predicate_smrd_sextloadi8>>  =>  (S_LOAD_I8_IMM:{ *:[i32] } ?:{ *:[i64] }:$sbase, ?:{ *:[i32] }:$offset, 0:{ *:[i32] })
      GIR_BuildMI, /*InsnID*/0, /*Opcode*/GIMT_Encode2(AMDGPU::S_LOAD_I8_IMM),
      GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/0, // DstI[sdst]
      GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/0, // sbase
      GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/1, // offset
      GIR_AddImm8, /*InsnID*/0, /*Imm*/0,
      GIR_MergeMemOperands, /*InsnID*/0, /*NumInsns*/1, /*MergeInsnID's*/0,
      GIR_ConstrainSelectedInstOperands, /*InsnID*/0,
      GIR_EraseFromParent, /*InsnID*/0,
      // GIR_Coverage, 2427,
      GIR_Done,
    // Label 1702: @111241
    GIM_Try, /*On fail goto*//*Label 1703*/ GIMT_Encode4(111312), // Rule ID 2428 //
      GIM_CheckFeatures, GIMT_Encode2(GIFBS_isGFX12Plus),
      GIM_CheckMemorySizeEqualTo, /*MI*/0, /*MMO*/0, /*Size*/GIMT_Encode4(1),
      GIM_CheckAtomicOrdering, /*MI*/0, /*Order*/(uint8_t)AtomicOrdering::NotAtomic,
      GIM_CheckRegBankForClass, /*MI*/0, /*Op*/0, /*RC*/GIMT_Encode2(AMDGPU::SReg_32_XM0_XEXECRegClassID),
      GIM_CheckPointerToAny, /*MI*/0, /*Op*/1, /*SizeInBits*/0,
      GIM_CheckCxxInsnPredicate, /*MI*/0, /*FnId*/GIMT_Encode2(GICXXPred_MI_Predicate_smrd_sextloadi8),
      GIM_CheckComplexPattern, /*MI*/0, /*Op*/1, /*Renderer*/GIMT_Encode2(0), GIMT_Encode2(GICP_gi_smrd_sgpr),
      // (ld:{ *:[i32] } (SMRDSgpr:{ *:[iPTR] } i64:{ *:[i64] }:$sbase, i32:{ *:[i32] }:$soffset))<<P:Predicate_unindexedload>><<P:Predicate_sextload>><<P:Predicate_sextloadi8>><<P:Predicate_smrd_sextloadi8>>  =>  (S_LOAD_I8_SGPR_IMM:{ *:[i32] } ?:{ *:[i64] }:$sbase, ?:{ *:[i32] }:$soffset, 0:{ *:[i32] }, 0:{ *:[i32] })
      GIR_BuildMI, /*InsnID*/0, /*Opcode*/GIMT_Encode2(AMDGPU::S_LOAD_I8_SGPR_IMM),
      GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/0, // DstI[sdst]
      GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/0, // sbase
      GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/1, // soffset
      GIR_AddImm8, /*InsnID*/0, /*Imm*/0,
      GIR_AddImm8, /*InsnID*/0, /*Imm*/0,
      GIR_MergeMemOperands, /*InsnID*/0, /*NumInsns*/1, /*MergeInsnID's*/0,
      GIR_ConstrainSelectedInstOperands, /*InsnID*/0,
      GIR_EraseFromParent, /*InsnID*/0,
      // GIR_Coverage, 2428,
      GIR_Done,
    // Label 1703: @111312
    GIM_Try, /*On fail goto*//*Label 1704*/ GIMT_Encode4(111380), // Rule ID 2439 //
      GIM_CheckFeatures, GIMT_Encode2(GIFBS_isGFX12Plus),
      GIM_CheckMemorySizeEqualTo, /*MI*/0, /*MMO*/0, /*Size*/GIMT_Encode4(2),
      GIM_CheckAtomicOrdering, /*MI*/0, /*Order*/(uint8_t)AtomicOrdering::NotAtomic,
      GIM_CheckRegBankForClass, /*MI*/0, /*Op*/0, /*RC*/GIMT_Encode2(AMDGPU::SReg_32_XM0_XEXECRegClassID),
      GIM_CheckPointerToAny, /*MI*/0, /*Op*/1, /*SizeInBits*/0,
      GIM_CheckCxxInsnPredicate, /*MI*/0, /*FnId*/GIMT_Encode2(GICXXPred_MI_Predicate_smrd_sextloadi16),
      GIM_CheckComplexPattern, /*MI*/0, /*Op*/1, /*Renderer*/GIMT_Encode2(0), GIMT_Encode2(GICP_gi_smrd_imm),
      // (ld:{ *:[i32] } (SMRDImm:{ *:[iPTR] } i64:{ *:[i64] }:$sbase, i32:{ *:[i32] }:$offset))<<P:Predicate_unindexedload>><<P:Predicate_sextload>><<P:Predicate_sextloadi16>><<P:Predicate_smrd_sextloadi16>>  =>  (S_LOAD_I16_IMM:{ *:[i32] } ?:{ *:[i64] }:$sbase, ?:{ *:[i32] }:$offset, 0:{ *:[i32] })
      GIR_BuildMI, /*InsnID*/0, /*Opcode*/GIMT_Encode2(AMDGPU::S_LOAD_I16_IMM),
      GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/0, // DstI[sdst]
      GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/0, // sbase
      GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/1, // offset
      GIR_AddImm8, /*InsnID*/0, /*Imm*/0,
      GIR_MergeMemOperands, /*InsnID*/0, /*NumInsns*/1, /*MergeInsnID's*/0,
      GIR_ConstrainSelectedInstOperands, /*InsnID*/0,
      GIR_EraseFromParent, /*InsnID*/0,
      // GIR_Coverage, 2439,
      GIR_Done,
    // Label 1704: @111380
    GIM_Try, /*On fail goto*//*Label 1705*/ GIMT_Encode4(111451), // Rule ID 2440 //
      GIM_CheckFeatures, GIMT_Encode2(GIFBS_isGFX12Plus),
      GIM_CheckMemorySizeEqualTo, /*MI*/0, /*MMO*/0, /*Size*/GIMT_Encode4(2),
      GIM_CheckAtomicOrdering, /*MI*/0, /*Order*/(uint8_t)AtomicOrdering::NotAtomic,
      GIM_CheckRegBankForClass, /*MI*/0, /*Op*/0, /*RC*/GIMT_Encode2(AMDGPU::SReg_32_XM0_XEXECRegClassID),
      GIM_CheckPointerToAny, /*MI*/0, /*Op*/1, /*SizeInBits*/0,
      GIM_CheckCxxInsnPredicate, /*MI*/0, /*FnId*/GIMT_Encode2(GICXXPred_MI_Predicate_smrd_sextloadi16),
      GIM_CheckComplexPattern, /*MI*/0, /*Op*/1, /*Renderer*/GIMT_Encode2(0), GIMT_Encode2(GICP_gi_smrd_sgpr),
      // (ld:{ *:[i32] } (SMRDSgpr:{ *:[iPTR] } i64:{ *:[i64] }:$sbase, i32:{ *:[i32] }:$soffset))<<P:Predicate_unindexedload>><<P:Predicate_sextload>><<P:Predicate_sextloadi16>><<P:Predicate_smrd_sextloadi16>>  =>  (S_LOAD_I16_SGPR_IMM:{ *:[i32] } ?:{ *:[i64] }:$sbase, ?:{ *:[i32] }:$soffset, 0:{ *:[i32] }, 0:{ *:[i32] })
      GIR_BuildMI, /*InsnID*/0, /*Opcode*/GIMT_Encode2(AMDGPU::S_LOAD_I16_SGPR_IMM),
      GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/0, // DstI[sdst]
      GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/0, // sbase
      GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/1, // soffset
      GIR_AddImm8, /*InsnID*/0, /*Imm*/0,
      GIR_AddImm8, /*InsnID*/0, /*Imm*/0,
      GIR_MergeMemOperands, /*InsnID*/0, /*NumInsns*/1, /*MergeInsnID's*/0,
      GIR_ConstrainSelectedInstOperands, /*InsnID*/0,
      GIR_EraseFromParent, /*InsnID*/0,
      // GIR_Coverage, 2440,
      GIR_Done,
    // Label 1705: @111451
    GIM_Try, /*On fail goto*//*Label 1706*/ GIMT_Encode4(111514), // Rule ID 2430 //
      GIM_CheckFeatures, GIMT_Encode2(GIFBS_isGFX12Plus),
      GIM_CheckMemorySizeEqualTo, /*MI*/0, /*MMO*/0, /*Size*/GIMT_Encode4(1),
      GIM_CheckAtomicOrdering, /*MI*/0, /*Order*/(uint8_t)AtomicOrdering::NotAtomic,
      GIM_CheckRegBankForClass, /*MI*/0, /*Op*/0, /*RC*/GIMT_Encode2(AMDGPU::SReg_32_XM0_XEXECRegClassID),
      // MIs[0] sbase
      GIM_CheckPointerToAny, /*MI*/0, /*Op*/1, /*SizeInBits*/64,
      GIM_CheckRegBankForClass, /*MI*/0, /*Op*/1, /*RC*/GIMT_Encode2(AMDGPU::SReg_64RegClassID),
      GIM_CheckCxxInsnPredicate, /*MI*/0, /*FnId*/GIMT_Encode2(GICXXPred_MI_Predicate_smrd_sextloadi8),
      // (ld:{ *:[i32] } SReg_64:{ *:[i64] }:$sbase)<<P:Predicate_unindexedload>><<P:Predicate_sextload>><<P:Predicate_sextloadi8>><<P:Predicate_smrd_sextloadi8>>  =>  (S_LOAD_I8_IMM:{ *:[i32] } i64:{ *:[i64] }:$sbase, 0:{ *:[i32] }, 0:{ *:[i32] })
      GIR_BuildMI, /*InsnID*/0, /*Opcode*/GIMT_Encode2(AMDGPU::S_LOAD_I8_IMM),
      GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/0, // DstI[sdst]
      GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/1, // sbase
      GIR_AddImm8, /*InsnID*/0, /*Imm*/0,
      GIR_AddImm8, /*InsnID*/0, /*Imm*/0,
      GIR_MergeMemOperands, /*InsnID*/0, /*NumInsns*/1, /*MergeInsnID's*/0,
      GIR_ConstrainSelectedInstOperands, /*InsnID*/0,
      GIR_EraseFromParent, /*InsnID*/0,
      // GIR_Coverage, 2430,
      GIR_Done,
    // Label 1706: @111514
    GIM_Try, /*On fail goto*//*Label 1707*/ GIMT_Encode4(111577), // Rule ID 2442 //
      GIM_CheckFeatures, GIMT_Encode2(GIFBS_isGFX12Plus),
      GIM_CheckMemorySizeEqualTo, /*MI*/0, /*MMO*/0, /*Size*/GIMT_Encode4(2),
      GIM_CheckAtomicOrdering, /*MI*/0, /*Order*/(uint8_t)AtomicOrdering::NotAtomic,
      GIM_CheckRegBankForClass, /*MI*/0, /*Op*/0, /*RC*/GIMT_Encode2(AMDGPU::SReg_32_XM0_XEXECRegClassID),
      // MIs[0] sbase
      GIM_CheckPointerToAny, /*MI*/0, /*Op*/1, /*SizeInBits*/64,
      GIM_CheckRegBankForClass, /*MI*/0, /*Op*/1, /*RC*/GIMT_Encode2(AMDGPU::SReg_64RegClassID),
      GIM_CheckCxxInsnPredicate, /*MI*/0, /*FnId*/GIMT_Encode2(GICXXPred_MI_Predicate_smrd_sextloadi16),
      // (ld:{ *:[i32] } SReg_64:{ *:[i64] }:$sbase)<<P:Predicate_unindexedload>><<P:Predicate_sextload>><<P:Predicate_sextloadi16>><<P:Predicate_smrd_sextloadi16>>  =>  (S_LOAD_I16_IMM:{ *:[i32] } i64:{ *:[i64] }:$sbase, 0:{ *:[i32] }, 0:{ *:[i32] })
      GIR_BuildMI, /*InsnID*/0, /*Opcode*/GIMT_Encode2(AMDGPU::S_LOAD_I16_IMM),
      GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/0, // DstI[sdst]
      GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/1, // sbase
      GIR_AddImm8, /*InsnID*/0, /*Imm*/0,
      GIR_AddImm8, /*InsnID*/0, /*Imm*/0,
      GIR_MergeMemOperands, /*InsnID*/0, /*NumInsns*/1, /*MergeInsnID's*/0,
      GIR_ConstrainSelectedInstOperands, /*InsnID*/0,
      GIR_EraseFromParent, /*InsnID*/0,
      // GIR_Coverage, 2442,
      GIR_Done,
    // Label 1707: @111577
    GIM_Try, /*On fail goto*//*Label 1708*/ GIMT_Encode4(111654), // Rule ID 5346 //
      GIM_CheckFeatures, GIMT_Encode2(GIFBS_DisableFlatScratch_HasUnrestrictedSOffset),
      GIM_CheckMemorySizeEqualTo, /*MI*/0, /*MMO*/0, /*Size*/GIMT_Encode4(1),
      GIM_CheckMemoryAddressSpace, /*MI*/0, /*MMO*/0, /*NumAddrSpace*/1, /*AddrSpace*/5,
      GIM_CheckAtomicOrdering, /*MI*/0, /*Order*/(uint8_t)AtomicOrdering::NotAtomic,
      GIM_CheckRegBankForClass, /*MI*/0, /*Op*/0, /*RC*/GIMT_Encode2(AMDGPU::AV_32RegClassID),
      GIM_CheckPointerToAny, /*MI*/0, /*Op*/1, /*SizeInBits*/0,
      GIM_CheckComplexPattern, /*MI*/0, /*Op*/1, /*Renderer*/GIMT_Encode2(0), GIMT_Encode2(GICP_gi_mubuf_scratch_offset),
      // (ld:{ *:[i32] } (MUBUFScratchOffset:{ *:[iPTR] } v4i32:{ *:[v4i32] }:$srsrc, i32:{ *:[i32] }:$soffset, i32:{ *:[i32] }:$offset))<<P:Predicate_unindexedload>><<P:Predicate_sextload>><<P:Predicate_sextloadi8>><<P:Predicate_sextloadi8_private>>  =>  (BUFFER_LOAD_SBYTE_OFFSET:{ *:[i32] } ?:{ *:[v4i32] }:$srsrc, ?:{ *:[i32] }:$soffset, ?:{ *:[i32] }:$offset, 0:{ *:[i32] }, 0:{ *:[i1] })
      GIR_BuildMI, /*InsnID*/0, /*Opcode*/GIMT_Encode2(AMDGPU::BUFFER_LOAD_SBYTE_OFFSET),
      GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/0, // DstI[vdata]
      GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/0, // srsrc
      GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/1, // soffset
      GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/2, // offset
      GIR_AddImm8, /*InsnID*/0, /*Imm*/0,
      GIR_AddImm8, /*InsnID*/0, /*Imm*/0,
      GIR_MergeMemOperands, /*InsnID*/0, /*NumInsns*/1, /*MergeInsnID's*/0,
      GIR_ConstrainSelectedInstOperands, /*InsnID*/0,
      GIR_EraseFromParent, /*InsnID*/0,
      // GIR_Coverage, 5346,
      GIR_Done,
    // Label 1708: @111654
    GIM_Try, /*On fail goto*//*Label 1709*/ GIMT_Encode4(111731), // Rule ID 5350 //
      GIM_CheckFeatures, GIMT_Encode2(GIFBS_DisableFlatScratch),
      GIM_CheckMemorySizeEqualTo, /*MI*/0, /*MMO*/0, /*Size*/GIMT_Encode4(1),
      GIM_CheckMemoryAddressSpace, /*MI*/0, /*MMO*/0, /*NumAddrSpace*/1, /*AddrSpace*/5,
      GIM_CheckAtomicOrdering, /*MI*/0, /*Order*/(uint8_t)AtomicOrdering::NotAtomic,
      GIM_CheckRegBankForClass, /*MI*/0, /*Op*/0, /*RC*/GIMT_Encode2(AMDGPU::AV_32RegClassID),
      GIM_CheckPointerToAny, /*MI*/0, /*Op*/1, /*SizeInBits*/0,
      GIM_CheckComplexPattern, /*MI*/0, /*Op*/1, /*Renderer*/GIMT_Encode2(0), GIMT_Encode2(GICP_gi_mubuf_scratch_offset),
      // (ld:{ *:[i32] } (MUBUFScratchOffset:{ *:[iPTR] } v4i32:{ *:[v4i32] }:$srsrc, i32:{ *:[i32] }:$soffset, i32:{ *:[i32] }:$offset))<<P:Predicate_unindexedload>><<P:Predicate_sextload>><<P:Predicate_sextloadi8>><<P:Predicate_sextloadi8_private>>  =>  (BUFFER_LOAD_SBYTE_VBUFFER_OFFSET:{ *:[i32] } ?:{ *:[v4i32] }:$srsrc, ?:{ *:[i32] }:$soffset, ?:{ *:[i32] }:$offset, 0:{ *:[i32] }, 0:{ *:[i1] })
      GIR_BuildMI, /*InsnID*/0, /*Opcode*/GIMT_Encode2(AMDGPU::BUFFER_LOAD_SBYTE_VBUFFER_OFFSET),
      GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/0, // DstI[vdata]
      GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/0, // srsrc
      GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/1, // soffset
      GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/2, // offset
      GIR_AddImm8, /*InsnID*/0, /*Imm*/0,
      GIR_AddImm8, /*InsnID*/0, /*Imm*/0,
      GIR_MergeMemOperands, /*InsnID*/0, /*NumInsns*/1, /*MergeInsnID's*/0,
      GIR_ConstrainSelectedInstOperands, /*InsnID*/0,
      GIR_EraseFromParent, /*InsnID*/0,
      // GIR_Coverage, 5350,
      GIR_Done,
    // Label 1709: @111731
    GIM_Try, /*On fail goto*//*Label 1710*/ GIMT_Encode4(111808), // Rule ID 5372 //
      GIM_CheckFeatures, GIMT_Encode2(GIFBS_DisableFlatScratch_HasUnrestrictedSOffset),
      GIM_CheckMemorySizeEqualTo, /*MI*/0, /*MMO*/0, /*Size*/GIMT_Encode4(2),
      GIM_CheckMemoryAddressSpace, /*MI*/0, /*MMO*/0, /*NumAddrSpace*/1, /*AddrSpace*/5,
      GIM_CheckAtomicOrdering, /*MI*/0, /*Order*/(uint8_t)AtomicOrdering::NotAtomic,
      GIM_CheckRegBankForClass, /*MI*/0, /*Op*/0, /*RC*/GIMT_Encode2(AMDGPU::AV_32RegClassID),
      GIM_CheckPointerToAny, /*MI*/0, /*Op*/1, /*SizeInBits*/0,
      GIM_CheckComplexPattern, /*MI*/0, /*Op*/1, /*Renderer*/GIMT_Encode2(0), GIMT_Encode2(GICP_gi_mubuf_scratch_offset),
      // (ld:{ *:[i32] } (MUBUFScratchOffset:{ *:[iPTR] } v4i32:{ *:[v4i32] }:$srsrc, i32:{ *:[i32] }:$soffset, i32:{ *:[i32] }:$offset))<<P:Predicate_unindexedload>><<P:Predicate_sextload>><<P:Predicate_sextloadi16>><<P:Predicate_sextloadi16_private>>  =>  (BUFFER_LOAD_SSHORT_OFFSET:{ *:[i32] } ?:{ *:[v4i32] }:$srsrc, ?:{ *:[i32] }:$soffset, ?:{ *:[i32] }:$offset, 0:{ *:[i32] }, 0:{ *:[i1] })
      GIR_BuildMI, /*InsnID*/0, /*Opcode*/GIMT_Encode2(AMDGPU::BUFFER_LOAD_SSHORT_OFFSET),
      GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/0, // DstI[vdata]
      GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/0, // srsrc
      GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/1, // soffset
      GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/2, // offset
      GIR_AddImm8, /*InsnID*/0, /*Imm*/0,
      GIR_AddImm8, /*InsnID*/0, /*Imm*/0,
      GIR_MergeMemOperands, /*InsnID*/0, /*NumInsns*/1, /*MergeInsnID's*/0,
      GIR_ConstrainSelectedInstOperands, /*InsnID*/0,
      GIR_EraseFromParent, /*InsnID*/0,
      // GIR_Coverage, 5372,
      GIR_Done,
    // Label 1710: @111808
    GIM_Try, /*On fail goto*//*Label 1711*/ GIMT_Encode4(111885), // Rule ID 5374 //
      GIM_CheckFeatures, GIMT_Encode2(GIFBS_DisableFlatScratch),
      GIM_CheckMemorySizeEqualTo, /*MI*/0, /*MMO*/0, /*Size*/GIMT_Encode4(2),
      GIM_CheckMemoryAddressSpace, /*MI*/0, /*MMO*/0, /*NumAddrSpace*/1, /*AddrSpace*/5,
      GIM_CheckAtomicOrdering, /*MI*/0, /*Order*/(uint8_t)AtomicOrdering::NotAtomic,
      GIM_CheckRegBankForClass, /*MI*/0, /*Op*/0, /*RC*/GIMT_Encode2(AMDGPU::AV_32RegClassID),
      GIM_CheckPointerToAny, /*MI*/0, /*Op*/1, /*SizeInBits*/0,
      GIM_CheckComplexPattern, /*MI*/0, /*Op*/1, /*Renderer*/GIMT_Encode2(0), GIMT_Encode2(GICP_gi_mubuf_scratch_offset),
      // (ld:{ *:[i32] } (MUBUFScratchOffset:{ *:[iPTR] } v4i32:{ *:[v4i32] }:$srsrc, i32:{ *:[i32] }:$soffset, i32:{ *:[i32] }:$offset))<<P:Predicate_unindexedload>><<P:Predicate_sextload>><<P:Predicate_sextloadi16>><<P:Predicate_sextloadi16_private>>  =>  (BUFFER_LOAD_SSHORT_VBUFFER_OFFSET:{ *:[i32] } ?:{ *:[v4i32] }:$srsrc, ?:{ *:[i32] }:$soffset, ?:{ *:[i32] }:$offset, 0:{ *:[i32] }, 0:{ *:[i1] })
      GIR_BuildMI, /*InsnID*/0, /*Opcode*/GIMT_Encode2(AMDGPU::BUFFER_LOAD_SSHORT_VBUFFER_OFFSET),
      GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/0, // DstI[vdata]
      GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/0, // srsrc
      GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/1, // soffset
      GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/2, // offset
      GIR_AddImm8, /*InsnID*/0, /*Imm*/0,
      GIR_AddImm8, /*InsnID*/0, /*Imm*/0,
      GIR_MergeMemOperands, /*InsnID*/0, /*NumInsns*/1, /*MergeInsnID's*/0,
      GIR_ConstrainSelectedInstOperands, /*InsnID*/0,
      GIR_EraseFromParent, /*InsnID*/0,
      // GIR_Coverage, 5374,
      GIR_Done,
    // Label 1711: @111885
    GIM_Try, /*On fail goto*//*Label 1712*/ GIMT_Encode4(111959), // Rule ID 3409 //
      GIM_CheckFeatures, GIMT_Encode2(GIFBS_EnableFlatScratch_HasFlatScratchInsts_HasFlatScratchSVSMode),
      GIM_CheckMemorySizeEqualTo, /*MI*/0, /*MMO*/0, /*Size*/GIMT_Encode4(1),
      GIM_CheckMemoryAddressSpace, /*MI*/0, /*MMO*/0, /*NumAddrSpace*/1, /*AddrSpace*/5,
      GIM_CheckAtomicOrdering, /*MI*/0, /*Order*/(uint8_t)AtomicOrdering::NotAtomic,
      GIM_CheckRegBankForClass, /*MI*/0, /*Op*/0, /*RC*/GIMT_Encode2(AMDGPU::AV_32RegClassID),
      GIM_CheckPointerToAny, /*MI*/0, /*Op*/1, /*SizeInBits*/0,
      GIM_CheckComplexPattern, /*MI*/0, /*Op*/1, /*Renderer*/GIMT_Encode2(0), GIMT_Encode2(GICP_gi_flat_scratch_svaddr),
      // (ld:{ *:[i32] } (ScratchSVAddr:{ *:[iPTR] } VGPR_32:{ *:[i32] }:$vaddr, SGPR_32:{ *:[i32] }:$saddr, i32:{ *:[i32] }:$offset))<<P:Predicate_unindexedload>><<P:Predicate_sextload>><<P:Predicate_sextloadi8>><<P:Predicate_sextloadi8_private>>  =>  (SCRATCH_LOAD_SBYTE_SVS:{ *:[i32] } ?:{ *:[i32] }:$vaddr, ?:{ *:[i32] }:$saddr, ?:{ *:[i32] }:$offset, 0:{ *:[i32] })
      GIR_BuildMI, /*InsnID*/0, /*Opcode*/GIMT_Encode2(AMDGPU::SCRATCH_LOAD_SBYTE_SVS),
      GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/0, // DstI[vdst]
      GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/0, // vaddr
      GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/1, // saddr
      GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/2, // offset
      GIR_AddImm8, /*InsnID*/0, /*Imm*/0,
      GIR_MergeMemOperands, /*InsnID*/0, /*NumInsns*/1, /*MergeInsnID's*/0,
      GIR_ConstrainSelectedInstOperands, /*InsnID*/0,
      GIR_EraseFromParent, /*InsnID*/0,
      // GIR_Coverage, 3409,
      GIR_Done,
    // Label 1712: @111959
    GIM_Try, /*On fail goto*//*Label 1713*/ GIMT_Encode4(112033), // Rule ID 3427 //
      GIM_CheckFeatures, GIMT_Encode2(GIFBS_EnableFlatScratch_HasFlatScratchInsts_HasFlatScratchSVSMode),
      GIM_CheckMemorySizeEqualTo, /*MI*/0, /*MMO*/0, /*Size*/GIMT_Encode4(2),
      GIM_CheckMemoryAddressSpace, /*MI*/0, /*MMO*/0, /*NumAddrSpace*/1, /*AddrSpace*/5,
      GIM_CheckAtomicOrdering, /*MI*/0, /*Order*/(uint8_t)AtomicOrdering::NotAtomic,
      GIM_CheckRegBankForClass, /*MI*/0, /*Op*/0, /*RC*/GIMT_Encode2(AMDGPU::AV_32RegClassID),
      GIM_CheckPointerToAny, /*MI*/0, /*Op*/1, /*SizeInBits*/0,
      GIM_CheckComplexPattern, /*MI*/0, /*Op*/1, /*Renderer*/GIMT_Encode2(0), GIMT_Encode2(GICP_gi_flat_scratch_svaddr),
      // (ld:{ *:[i32] } (ScratchSVAddr:{ *:[iPTR] } VGPR_32:{ *:[i32] }:$vaddr, SGPR_32:{ *:[i32] }:$saddr, i32:{ *:[i32] }:$offset))<<P:Predicate_unindexedload>><<P:Predicate_sextload>><<P:Predicate_sextloadi16>><<P:Predicate_sextloadi16_private>>  =>  (SCRATCH_LOAD_SSHORT_SVS:{ *:[i32] } ?:{ *:[i32] }:$vaddr, ?:{ *:[i32] }:$saddr, ?:{ *:[i32] }:$offset, 0:{ *:[i32] })
      GIR_BuildMI, /*InsnID*/0, /*Opcode*/GIMT_Encode2(AMDGPU::SCRATCH_LOAD_SSHORT_SVS),
      GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/0, // DstI[vdst]
      GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/0, // vaddr
      GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/1, // saddr
      GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/2, // offset
      GIR_AddImm8, /*InsnID*/0, /*Imm*/0,
      GIR_MergeMemOperands, /*InsnID*/0, /*NumInsns*/1, /*MergeInsnID's*/0,
      GIR_ConstrainSelectedInstOperands, /*InsnID*/0,
      GIR_EraseFromParent, /*InsnID*/0,
      // GIR_Coverage, 3427,
      GIR_Done,
    // Label 1713: @112033
    GIM_Try, /*On fail goto*//*Label 1714*/ GIMT_Encode4(112102), // Rule ID 3408 //
      GIM_CheckFeatures, GIMT_Encode2(GIFBS_EnableFlatScratch_HasFlatScratchInsts),
      GIM_CheckMemorySizeEqualTo, /*MI*/0, /*MMO*/0, /*Size*/GIMT_Encode4(1),
      GIM_CheckMemoryAddressSpace, /*MI*/0, /*MMO*/0, /*NumAddrSpace*/1, /*AddrSpace*/5,
      GIM_CheckAtomicOrdering, /*MI*/0, /*Order*/(uint8_t)AtomicOrdering::NotAtomic,
      GIM_CheckRegBankForClass, /*MI*/0, /*Op*/0, /*RC*/GIMT_Encode2(AMDGPU::AV_32RegClassID),
      GIM_CheckPointerToAny, /*MI*/0, /*Op*/1, /*SizeInBits*/0,
      GIM_CheckComplexPattern, /*MI*/0, /*Op*/1, /*Renderer*/GIMT_Encode2(0), GIMT_Encode2(GICP_gi_flat_scratch_saddr),
      // (ld:{ *:[i32] } (ScratchSAddr:{ *:[iPTR] } SGPR_32:{ *:[i32] }:$saddr, i32:{ *:[i32] }:$offset))<<P:Predicate_unindexedload>><<P:Predicate_sextload>><<P:Predicate_sextloadi8>><<P:Predicate_sextloadi8_private>>  =>  (SCRATCH_LOAD_SBYTE_SADDR:{ *:[i32] } ?:{ *:[i32] }:$saddr, ?:{ *:[i32] }:$offset)
      GIR_BuildMI, /*InsnID*/0, /*Opcode*/GIMT_Encode2(AMDGPU::SCRATCH_LOAD_SBYTE_SADDR),
      GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/0, // DstI[vdst]
      GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/0, // saddr
      GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/1, // offset
      GIR_AddImm8, /*InsnID*/0, /*Imm*/0,
      GIR_MergeMemOperands, /*InsnID*/0, /*NumInsns*/1, /*MergeInsnID's*/0,
      GIR_ConstrainSelectedInstOperands, /*InsnID*/0,
      GIR_EraseFromParent, /*InsnID*/0,
      // GIR_Coverage, 3408,
      GIR_Done,
    // Label 1714: @112102
    GIM_Try, /*On fail goto*//*Label 1715*/ GIMT_Encode4(112171), // Rule ID 3426 //
      GIM_CheckFeatures, GIMT_Encode2(GIFBS_EnableFlatScratch_HasFlatScratchInsts),
      GIM_CheckMemorySizeEqualTo, /*MI*/0, /*MMO*/0, /*Size*/GIMT_Encode4(2),
      GIM_CheckMemoryAddressSpace, /*MI*/0, /*MMO*/0, /*NumAddrSpace*/1, /*AddrSpace*/5,
      GIM_CheckAtomicOrdering, /*MI*/0, /*Order*/(uint8_t)AtomicOrdering::NotAtomic,
      GIM_CheckRegBankForClass, /*MI*/0, /*Op*/0, /*RC*/GIMT_Encode2(AMDGPU::AV_32RegClassID),
      GIM_CheckPointerToAny, /*MI*/0, /*Op*/1, /*SizeInBits*/0,
      GIM_CheckComplexPattern, /*MI*/0, /*Op*/1, /*Renderer*/GIMT_Encode2(0), GIMT_Encode2(GICP_gi_flat_scratch_saddr),
      // (ld:{ *:[i32] } (ScratchSAddr:{ *:[iPTR] } SGPR_32:{ *:[i32] }:$saddr, i32:{ *:[i32] }:$offset))<<P:Predicate_unindexedload>><<P:Predicate_sextload>><<P:Predicate_sextloadi16>><<P:Predicate_sextloadi16_private>>  =>  (SCRATCH_LOAD_SSHORT_SADDR:{ *:[i32] } ?:{ *:[i32] }:$saddr, ?:{ *:[i32] }:$offset)
      GIR_BuildMI, /*InsnID*/0, /*Opcode*/GIMT_Encode2(AMDGPU::SCRATCH_LOAD_SSHORT_SADDR),
      GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/0, // DstI[vdst]
      GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/0, // saddr
      GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/1, // offset
      GIR_AddImm8, /*InsnID*/0, /*Imm*/0,
      GIR_MergeMemOperands, /*InsnID*/0, /*NumInsns*/1, /*MergeInsnID's*/0,
      GIR_ConstrainSelectedInstOperands, /*InsnID*/0,
      GIR_EraseFromParent, /*InsnID*/0,
      // GIR_Coverage, 3426,
      GIR_Done,
    // Label 1715: @112171
    GIM_Try, /*On fail goto*//*Label 1716*/ GIMT_Encode4(112240), // Rule ID 3407 //
      GIM_CheckFeatures, GIMT_Encode2(GIFBS_EnableFlatScratch_HasFlatScratchInsts),
      GIM_CheckMemorySizeEqualTo, /*MI*/0, /*MMO*/0, /*Size*/GIMT_Encode4(1),
      GIM_CheckMemoryAddressSpace, /*MI*/0, /*MMO*/0, /*NumAddrSpace*/1, /*AddrSpace*/5,
      GIM_CheckAtomicOrdering, /*MI*/0, /*Order*/(uint8_t)AtomicOrdering::NotAtomic,
      GIM_CheckRegBankForClass, /*MI*/0, /*Op*/0, /*RC*/GIMT_Encode2(AMDGPU::AV_32RegClassID),
      GIM_CheckPointerToAny, /*MI*/0, /*Op*/1, /*SizeInBits*/0,
      GIM_CheckComplexPattern, /*MI*/0, /*Op*/1, /*Renderer*/GIMT_Encode2(0), GIMT_Encode2(GICP_gi_flat_scratch_offset),
      // (ld:{ *:[i32] } (ScratchOffset:{ *:[iPTR] } VGPR_32:{ *:[i32] }:$vaddr, i32:{ *:[i32] }:$offset))<<P:Predicate_unindexedload>><<P:Predicate_sextload>><<P:Predicate_sextloadi8>><<P:Predicate_sextloadi8_private>>  =>  (SCRATCH_LOAD_SBYTE:{ *:[i32] } ?:{ *:[i32] }:$vaddr, ?:{ *:[i32] }:$offset)
      GIR_BuildMI, /*InsnID*/0, /*Opcode*/GIMT_Encode2(AMDGPU::SCRATCH_LOAD_SBYTE),
      GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/0, // DstI[vdst]
      GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/0, // vaddr
      GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/1, // offset
      GIR_AddImm8, /*InsnID*/0, /*Imm*/0,
      GIR_MergeMemOperands, /*InsnID*/0, /*NumInsns*/1, /*MergeInsnID's*/0,
      GIR_ConstrainSelectedInstOperands, /*InsnID*/0,
      GIR_EraseFromParent, /*InsnID*/0,
      // GIR_Coverage, 3407,
      GIR_Done,
    // Label 1716: @112240
    GIM_Try, /*On fail goto*//*Label 1717*/ GIMT_Encode4(112309), // Rule ID 3425 //
      GIM_CheckFeatures, GIMT_Encode2(GIFBS_EnableFlatScratch_HasFlatScratchInsts),
      GIM_CheckMemorySizeEqualTo, /*MI*/0, /*MMO*/0, /*Size*/GIMT_Encode4(2),
      GIM_CheckMemoryAddressSpace, /*MI*/0, /*MMO*/0, /*NumAddrSpace*/1, /*AddrSpace*/5,
      GIM_CheckAtomicOrdering, /*MI*/0, /*Order*/(uint8_t)AtomicOrdering::NotAtomic,
      GIM_CheckRegBankForClass, /*MI*/0, /*Op*/0, /*RC*/GIMT_Encode2(AMDGPU::AV_32RegClassID),
      GIM_CheckPointerToAny, /*MI*/0, /*Op*/1, /*SizeInBits*/0,
      GIM_CheckComplexPattern, /*MI*/0, /*Op*/1, /*Renderer*/GIMT_Encode2(0), GIMT_Encode2(GICP_gi_flat_scratch_offset),
      // (ld:{ *:[i32] } (ScratchOffset:{ *:[iPTR] } VGPR_32:{ *:[i32] }:$vaddr, i32:{ *:[i32] }:$offset))<<P:Predicate_unindexedload>><<P:Predicate_sextload>><<P:Predicate_sextloadi16>><<P:Predicate_sextloadi16_private>>  =>  (SCRATCH_LOAD_SSHORT:{ *:[i32] } ?:{ *:[i32] }:$vaddr, ?:{ *:[i32] }:$offset)
      GIR_BuildMI, /*InsnID*/0, /*Opcode*/GIMT_Encode2(AMDGPU::SCRATCH_LOAD_SSHORT),
      GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/0, // DstI[vdst]
      GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/0, // vaddr
      GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/1, // offset
      GIR_AddImm8, /*InsnID*/0, /*Imm*/0,
      GIR_MergeMemOperands, /*InsnID*/0, /*NumInsns*/1, /*MergeInsnID's*/0,
      GIR_ConstrainSelectedInstOperands, /*InsnID*/0,
      GIR_EraseFromParent, /*InsnID*/0,
      // GIR_Coverage, 3425,
      GIR_Done,
    // Label 1717: @112309
    GIM_Try, /*On fail goto*//*Label 1718*/ GIMT_Encode4(112393), // Rule ID 3668 //
      GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasUnrestrictedSOffset),
      GIM_CheckMemorySizeEqualTo, /*MI*/0, /*MMO*/0, /*Size*/GIMT_Encode4(1),
      GIM_CheckMemoryAddressSpace, /*MI*/0, /*MMO*/0, /*NumAddrSpace*/3, /*AddrSpace*/1, /*AddrSpace*/4, /*AddrSpace*/6,
      GIM_CheckAtomicOrdering, /*MI*/0, /*Order*/(uint8_t)AtomicOrdering::NotAtomic,
      GIM_CheckRegBankForClass, /*MI*/0, /*Op*/0, /*RC*/GIMT_Encode2(AMDGPU::AV_32RegClassID),
      GIM_CheckPointerToAny, /*MI*/0, /*Op*/1, /*SizeInBits*/0,
      GIM_CheckComplexPattern, /*MI*/0, /*Op*/1, /*Renderer*/GIMT_Encode2(0), GIMT_Encode2(GICP_gi_mubuf_addr64),
      // (ld:{ *:[i32] } (MUBUFAddr64:{ *:[iPTR] } v4i32:{ *:[v4i32] }:$srsrc, i64:{ *:[i64] }:$vaddr, i32:{ *:[i32] }:$soffset, i32:{ *:[i32] }:$offset))<<P:Predicate_unindexedload>><<P:Predicate_sextload>><<P:Predicate_sextloadi8>><<P:Predicate_sextloadi8_global>>  =>  (BUFFER_LOAD_SBYTE_ADDR64:{ *:[i32] } i64:{ *:[i64] }:$vaddr, v4i32:{ *:[v4i32] }:$srsrc, i32:{ *:[i32] }:$soffset, i32:{ *:[i32] }:$offset)
      GIR_BuildMI, /*InsnID*/0, /*Opcode*/GIMT_Encode2(AMDGPU::BUFFER_LOAD_SBYTE_ADDR64),
      GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/0, // DstI[vdata]
      GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/1, // vaddr
      GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/0, // srsrc
      GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/2, // soffset
      GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/3, // offset
      GIR_AddImm8, /*InsnID*/0, /*Imm*/0,
      GIR_AddImm8, /*InsnID*/0, /*Imm*/0,
      GIR_MergeMemOperands, /*InsnID*/0, /*NumInsns*/1, /*MergeInsnID's*/0,
      GIR_ConstrainSelectedInstOperands, /*InsnID*/0,
      GIR_EraseFromParent, /*InsnID*/0,
      // GIR_Coverage, 3668,
      GIR_Done,
    // Label 1718: @112393
    GIM_Try, /*On fail goto*//*Label 1719*/ GIMT_Encode4(112474), // Rule ID 3670 //
      GIM_CheckMemorySizeEqualTo, /*MI*/0, /*MMO*/0, /*Size*/GIMT_Encode4(1),
      GIM_CheckMemoryAddressSpace, /*MI*/0, /*MMO*/0, /*NumAddrSpace*/3, /*AddrSpace*/1, /*AddrSpace*/4, /*AddrSpace*/6,
      GIM_CheckAtomicOrdering, /*MI*/0, /*Order*/(uint8_t)AtomicOrdering::NotAtomic,
      GIM_CheckRegBankForClass, /*MI*/0, /*Op*/0, /*RC*/GIMT_Encode2(AMDGPU::AV_32RegClassID),
      GIM_CheckPointerToAny, /*MI*/0, /*Op*/1, /*SizeInBits*/0,
      GIM_CheckComplexPattern, /*MI*/0, /*Op*/1, /*Renderer*/GIMT_Encode2(0), GIMT_Encode2(GICP_gi_mubuf_addr64),
      // (ld:{ *:[i32] } (MUBUFAddr64:{ *:[iPTR] } v4i32:{ *:[v4i32] }:$srsrc, i64:{ *:[i64] }:$vaddr, i32:{ *:[i32] }:$soffset, i32:{ *:[i32] }:$offset))<<P:Predicate_unindexedload>><<P:Predicate_sextload>><<P:Predicate_sextloadi8>><<P:Predicate_sextloadi8_global>>  =>  (BUFFER_LOAD_SBYTE_VBUFFER_ADDR64:{ *:[i32] } i64:{ *:[i64] }:$vaddr, v4i32:{ *:[v4i32] }:$srsrc, i32:{ *:[i32] }:$soffset, i32:{ *:[i32] }:$offset)
      GIR_BuildMI, /*InsnID*/0, /*Opcode*/GIMT_Encode2(AMDGPU::BUFFER_LOAD_SBYTE_VBUFFER_ADDR64),
      GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/0, // DstI[vdata]
      GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/1, // vaddr
      GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/0, // srsrc
      GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/2, // soffset
      GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/3, // offset
      GIR_AddImm8, /*InsnID*/0, /*Imm*/0,
      GIR_AddImm8, /*InsnID*/0, /*Imm*/0,
      GIR_MergeMemOperands, /*InsnID*/0, /*NumInsns*/1, /*MergeInsnID's*/0,
      GIR_ConstrainSelectedInstOperands, /*InsnID*/0,
      GIR_EraseFromParent, /*InsnID*/0,
      // GIR_Coverage, 3670,
      GIR_Done,
    // Label 1719: @112474
    GIM_Try, /*On fail goto*//*Label 1720*/ GIMT_Encode4(112558), // Rule ID 3680 //
      GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasUnrestrictedSOffset),
      GIM_CheckMemorySizeEqualTo, /*MI*/0, /*MMO*/0, /*Size*/GIMT_Encode4(2),
      GIM_CheckMemoryAddressSpace, /*MI*/0, /*MMO*/0, /*NumAddrSpace*/3, /*AddrSpace*/1, /*AddrSpace*/4, /*AddrSpace*/6,
      GIM_CheckAtomicOrdering, /*MI*/0, /*Order*/(uint8_t)AtomicOrdering::NotAtomic,
      GIM_CheckRegBankForClass, /*MI*/0, /*Op*/0, /*RC*/GIMT_Encode2(AMDGPU::AV_32RegClassID),
      GIM_CheckPointerToAny, /*MI*/0, /*Op*/1, /*SizeInBits*/0,
      GIM_CheckComplexPattern, /*MI*/0, /*Op*/1, /*Renderer*/GIMT_Encode2(0), GIMT_Encode2(GICP_gi_mubuf_addr64),
      // (ld:{ *:[i32] } (MUBUFAddr64:{ *:[iPTR] } v4i32:{ *:[v4i32] }:$srsrc, i64:{ *:[i64] }:$vaddr, i32:{ *:[i32] }:$soffset, i32:{ *:[i32] }:$offset))<<P:Predicate_unindexedload>><<P:Predicate_sextload>><<P:Predicate_sextloadi16>><<P:Predicate_sextloadi16_global>>  =>  (BUFFER_LOAD_SSHORT_ADDR64:{ *:[i32] } i64:{ *:[i64] }:$vaddr, v4i32:{ *:[v4i32] }:$srsrc, i32:{ *:[i32] }:$soffset, i32:{ *:[i32] }:$offset)
      GIR_BuildMI, /*InsnID*/0, /*Opcode*/GIMT_Encode2(AMDGPU::BUFFER_LOAD_SSHORT_ADDR64),
      GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/0, // DstI[vdata]
      GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/1, // vaddr
      GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/0, // srsrc
      GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/2, // soffset
      GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/3, // offset
      GIR_AddImm8, /*InsnID*/0, /*Imm*/0,
      GIR_AddImm8, /*InsnID*/0, /*Imm*/0,
      GIR_MergeMemOperands, /*InsnID*/0, /*NumInsns*/1, /*MergeInsnID's*/0,
      GIR_ConstrainSelectedInstOperands, /*InsnID*/0,
      GIR_EraseFromParent, /*InsnID*/0,
      // GIR_Coverage, 3680,
      GIR_Done,
    // Label 1720: @112558
    GIM_Try, /*On fail goto*//*Label 1721*/ GIMT_Encode4(112639), // Rule ID 3682 //
      GIM_CheckMemorySizeEqualTo, /*MI*/0, /*MMO*/0, /*Size*/GIMT_Encode4(2),
      GIM_CheckMemoryAddressSpace, /*MI*/0, /*MMO*/0, /*NumAddrSpace*/3, /*AddrSpace*/1, /*AddrSpace*/4, /*AddrSpace*/6,
      GIM_CheckAtomicOrdering, /*MI*/0, /*Order*/(uint8_t)AtomicOrdering::NotAtomic,
      GIM_CheckRegBankForClass, /*MI*/0, /*Op*/0, /*RC*/GIMT_Encode2(AMDGPU::AV_32RegClassID),
      GIM_CheckPointerToAny, /*MI*/0, /*Op*/1, /*SizeInBits*/0,
      GIM_CheckComplexPattern, /*MI*/0, /*Op*/1, /*Renderer*/GIMT_Encode2(0), GIMT_Encode2(GICP_gi_mubuf_addr64),
      // (ld:{ *:[i32] } (MUBUFAddr64:{ *:[iPTR] } v4i32:{ *:[v4i32] }:$srsrc, i64:{ *:[i64] }:$vaddr, i32:{ *:[i32] }:$soffset, i32:{ *:[i32] }:$offset))<<P:Predicate_unindexedload>><<P:Predicate_sextload>><<P:Predicate_sextloadi16>><<P:Predicate_sextloadi16_global>>  =>  (BUFFER_LOAD_SSHORT_VBUFFER_ADDR64:{ *:[i32] } i64:{ *:[i64] }:$vaddr, v4i32:{ *:[v4i32] }:$srsrc, i32:{ *:[i32] }:$soffset, i32:{ *:[i32] }:$offset)
      GIR_BuildMI, /*InsnID*/0, /*Opcode*/GIMT_Encode2(AMDGPU::BUFFER_LOAD_SSHORT_VBUFFER_ADDR64),
      GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/0, // DstI[vdata]
      GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/1, // vaddr
      GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/0, // srsrc
      GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/2, // soffset
      GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/3, // offset
      GIR_AddImm8, /*InsnID*/0, /*Imm*/0,
      GIR_AddImm8, /*InsnID*/0, /*Imm*/0,
      GIR_MergeMemOperands, /*InsnID*/0, /*NumInsns*/1, /*MergeInsnID's*/0,
      GIR_ConstrainSelectedInstOperands, /*InsnID*/0,
      GIR_EraseFromParent, /*InsnID*/0,
      // GIR_Coverage, 3682,
      GIR_Done,
    // Label 1721: @112639
    GIM_Try, /*On fail goto*//*Label 1722*/ GIMT_Encode4(112722), // Rule ID 5323 //
      GIM_CheckFeatures, GIMT_Encode2(GIFBS_isGFX6GFX7),
      GIM_CheckMemorySizeEqualTo, /*MI*/0, /*MMO*/0, /*Size*/GIMT_Encode4(1),
      GIM_CheckMemoryAddressSpace, /*MI*/0, /*MMO*/0, /*NumAddrSpace*/2, /*AddrSpace*/4, /*AddrSpace*/6,
      GIM_CheckAtomicOrdering, /*MI*/0, /*Order*/(uint8_t)AtomicOrdering::NotAtomic,
      GIM_CheckRegBankForClass, /*MI*/0, /*Op*/0, /*RC*/GIMT_Encode2(AMDGPU::AV_32RegClassID),
      GIM_CheckPointerToAny, /*MI*/0, /*Op*/1, /*SizeInBits*/0,
      GIM_CheckComplexPattern, /*MI*/0, /*Op*/1, /*Renderer*/GIMT_Encode2(0), GIMT_Encode2(GICP_gi_mubuf_addr64),
      // (ld:{ *:[i32] } (MUBUFAddr64:{ *:[iPTR] } v4i32:{ *:[v4i32] }:$srsrc, i64:{ *:[i64] }:$vaddr, i32:{ *:[i32] }:$soffset, i32:{ *:[i32] }:$offset))<<P:Predicate_unindexedload>><<P:Predicate_sextload>><<P:Predicate_sextloadi8>><<P:Predicate_sextloadi8_constant>>  =>  (BUFFER_LOAD_SBYTE_ADDR64:{ *:[i32] } ?:{ *:[i64] }:$vaddr, ?:{ *:[v4i32] }:$srsrc, ?:{ *:[i32] }:$soffset, ?:{ *:[i32] }:$offset)
      GIR_BuildMI, /*InsnID*/0, /*Opcode*/GIMT_Encode2(AMDGPU::BUFFER_LOAD_SBYTE_ADDR64),
      GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/0, // DstI[vdata]
      GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/1, // vaddr
      GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/0, // srsrc
      GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/2, // soffset
      GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/3, // offset
      GIR_AddImm8, /*InsnID*/0, /*Imm*/0,
      GIR_AddImm8, /*InsnID*/0, /*Imm*/0,
      GIR_MergeMemOperands, /*InsnID*/0, /*NumInsns*/1, /*MergeInsnID's*/0,
      GIR_ConstrainSelectedInstOperands, /*InsnID*/0,
      GIR_EraseFromParent, /*InsnID*/0,
      // GIR_Coverage, 5323,
      GIR_Done,
    // Label 1722: @112722
    GIM_Try, /*On fail goto*//*Label 1723*/ GIMT_Encode4(112805), // Rule ID 5326 //
      GIM_CheckFeatures, GIMT_Encode2(GIFBS_isGFX6GFX7),
      GIM_CheckMemorySizeEqualTo, /*MI*/0, /*MMO*/0, /*Size*/GIMT_Encode4(2),
      GIM_CheckMemoryAddressSpace, /*MI*/0, /*MMO*/0, /*NumAddrSpace*/2, /*AddrSpace*/4, /*AddrSpace*/6,
      GIM_CheckAtomicOrdering, /*MI*/0, /*Order*/(uint8_t)AtomicOrdering::NotAtomic,
      GIM_CheckRegBankForClass, /*MI*/0, /*Op*/0, /*RC*/GIMT_Encode2(AMDGPU::AV_32RegClassID),
      GIM_CheckPointerToAny, /*MI*/0, /*Op*/1, /*SizeInBits*/0,
      GIM_CheckComplexPattern, /*MI*/0, /*Op*/1, /*Renderer*/GIMT_Encode2(0), GIMT_Encode2(GICP_gi_mubuf_addr64),
      // (ld:{ *:[i32] } (MUBUFAddr64:{ *:[iPTR] } v4i32:{ *:[v4i32] }:$srsrc, i64:{ *:[i64] }:$vaddr, i32:{ *:[i32] }:$soffset, i32:{ *:[i32] }:$offset))<<P:Predicate_unindexedload>><<P:Predicate_sextload>><<P:Predicate_sextloadi16>><<P:Predicate_sextloadi16_constant>>  =>  (BUFFER_LOAD_SSHORT_ADDR64:{ *:[i32] } ?:{ *:[i64] }:$vaddr, ?:{ *:[v4i32] }:$srsrc, ?:{ *:[i32] }:$soffset, ?:{ *:[i32] }:$offset)
      GIR_BuildMI, /*InsnID*/0, /*Opcode*/GIMT_Encode2(AMDGPU::BUFFER_LOAD_SSHORT_ADDR64),
      GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/0, // DstI[vdata]
      GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/1, // vaddr
      GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/0, // srsrc
      GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/2, // soffset
      GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/3, // offset
      GIR_AddImm8, /*InsnID*/0, /*Imm*/0,
      GIR_AddImm8, /*InsnID*/0, /*Imm*/0,
      GIR_MergeMemOperands, /*InsnID*/0, /*NumInsns*/1, /*MergeInsnID's*/0,
      GIR_ConstrainSelectedInstOperands, /*InsnID*/0,
      GIR_EraseFromParent, /*InsnID*/0,
      // GIR_Coverage, 5326,
      GIR_Done,
    // Label 1723: @112805
    GIM_Try, /*On fail goto*//*Label 1724*/ GIMT_Encode4(112887), // Rule ID 5345 //
      GIM_CheckFeatures, GIMT_Encode2(GIFBS_DisableFlatScratch_HasUnrestrictedSOffset),
      GIM_CheckMemorySizeEqualTo, /*MI*/0, /*MMO*/0, /*Size*/GIMT_Encode4(1),
      GIM_CheckMemoryAddressSpace, /*MI*/0, /*MMO*/0, /*NumAddrSpace*/1, /*AddrSpace*/5,
      GIM_CheckAtomicOrdering, /*MI*/0, /*Order*/(uint8_t)AtomicOrdering::NotAtomic,
      GIM_CheckRegBankForClass, /*MI*/0, /*Op*/0, /*RC*/GIMT_Encode2(AMDGPU::AV_32RegClassID),
      GIM_CheckPointerToAny, /*MI*/0, /*Op*/1, /*SizeInBits*/0,
      GIM_CheckComplexPattern, /*MI*/0, /*Op*/1, /*Renderer*/GIMT_Encode2(0), GIMT_Encode2(GICP_gi_mubuf_scratch_offen),
      // (ld:{ *:[i32] } (MUBUFScratchOffen:{ *:[iPTR] } v4i32:{ *:[v4i32] }:$srsrc, i32:{ *:[i32] }:$vaddr, i32:{ *:[i32] }:$soffset, i32:{ *:[i32] }:$offset))<<P:Predicate_unindexedload>><<P:Predicate_sextload>><<P:Predicate_sextloadi8>><<P:Predicate_sextloadi8_private>>  =>  (BUFFER_LOAD_SBYTE_OFFEN:{ *:[i32] } ?:{ *:[i32] }:$vaddr, ?:{ *:[v4i32] }:$srsrc, ?:{ *:[i32] }:$soffset, ?:{ *:[i32] }:$offset, 0:{ *:[i32] }, 0:{ *:[i1] })
      GIR_BuildMI, /*InsnID*/0, /*Opcode*/GIMT_Encode2(AMDGPU::BUFFER_LOAD_SBYTE_OFFEN),
      GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/0, // DstI[vdata]
      GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/1, // vaddr
      GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/0, // srsrc
      GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/2, // soffset
      GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/3, // offset
      GIR_AddImm8, /*InsnID*/0, /*Imm*/0,
      GIR_AddImm8, /*InsnID*/0, /*Imm*/0,
      GIR_MergeMemOperands, /*InsnID*/0, /*NumInsns*/1, /*MergeInsnID's*/0,
      GIR_ConstrainSelectedInstOperands, /*InsnID*/0,
      GIR_EraseFromParent, /*InsnID*/0,
      // GIR_Coverage, 5345,
      GIR_Done,
    // Label 1724: @112887
    GIM_Try, /*On fail goto*//*Label 1725*/ GIMT_Encode4(112969), // Rule ID 5349 //
      GIM_CheckFeatures, GIMT_Encode2(GIFBS_DisableFlatScratch),
      GIM_CheckMemorySizeEqualTo, /*MI*/0, /*MMO*/0, /*Size*/GIMT_Encode4(1),
      GIM_CheckMemoryAddressSpace, /*MI*/0, /*MMO*/0, /*NumAddrSpace*/1, /*AddrSpace*/5,
      GIM_CheckAtomicOrdering, /*MI*/0, /*Order*/(uint8_t)AtomicOrdering::NotAtomic,
      GIM_CheckRegBankForClass, /*MI*/0, /*Op*/0, /*RC*/GIMT_Encode2(AMDGPU::AV_32RegClassID),
      GIM_CheckPointerToAny, /*MI*/0, /*Op*/1, /*SizeInBits*/0,
      GIM_CheckComplexPattern, /*MI*/0, /*Op*/1, /*Renderer*/GIMT_Encode2(0), GIMT_Encode2(GICP_gi_mubuf_scratch_offen),
      // (ld:{ *:[i32] } (MUBUFScratchOffen:{ *:[iPTR] } v4i32:{ *:[v4i32] }:$srsrc, i32:{ *:[i32] }:$vaddr, i32:{ *:[i32] }:$soffset, i32:{ *:[i32] }:$offset))<<P:Predicate_unindexedload>><<P:Predicate_sextload>><<P:Predicate_sextloadi8>><<P:Predicate_sextloadi8_private>>  =>  (BUFFER_LOAD_SBYTE_VBUFFER_OFFEN:{ *:[i32] } ?:{ *:[i32] }:$vaddr, ?:{ *:[v4i32] }:$srsrc, ?:{ *:[i32] }:$soffset, ?:{ *:[i32] }:$offset, 0:{ *:[i32] }, 0:{ *:[i1] })
      GIR_BuildMI, /*InsnID*/0, /*Opcode*/GIMT_Encode2(AMDGPU::BUFFER_LOAD_SBYTE_VBUFFER_OFFEN),
      GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/0, // DstI[vdata]
      GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/1, // vaddr
      GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/0, // srsrc
      GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/2, // soffset
      GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/3, // offset
      GIR_AddImm8, /*InsnID*/0, /*Imm*/0,
      GIR_AddImm8, /*InsnID*/0, /*Imm*/0,
      GIR_MergeMemOperands, /*InsnID*/0, /*NumInsns*/1, /*MergeInsnID's*/0,
      GIR_ConstrainSelectedInstOperands, /*InsnID*/0,
      GIR_EraseFromParent, /*InsnID*/0,
      // GIR_Coverage, 5349,
      GIR_Done,
    // Label 1725: @112969
    GIM_Try, /*On fail goto*//*Label 1726*/ GIMT_Encode4(113051), // Rule ID 5371 //
      GIM_CheckFeatures, GIMT_Encode2(GIFBS_DisableFlatScratch_HasUnrestrictedSOffset),
      GIM_CheckMemorySizeEqualTo, /*MI*/0, /*MMO*/0, /*Size*/GIMT_Encode4(2),
      GIM_CheckMemoryAddressSpace, /*MI*/0, /*MMO*/0, /*NumAddrSpace*/1, /*AddrSpace*/5,
      GIM_CheckAtomicOrdering, /*MI*/0, /*Order*/(uint8_t)AtomicOrdering::NotAtomic,
      GIM_CheckRegBankForClass, /*MI*/0, /*Op*/0, /*RC*/GIMT_Encode2(AMDGPU::AV_32RegClassID),
      GIM_CheckPointerToAny, /*MI*/0, /*Op*/1, /*SizeInBits*/0,
      GIM_CheckComplexPattern, /*MI*/0, /*Op*/1, /*Renderer*/GIMT_Encode2(0), GIMT_Encode2(GICP_gi_mubuf_scratch_offen),
      // (ld:{ *:[i32] } (MUBUFScratchOffen:{ *:[iPTR] } v4i32:{ *:[v4i32] }:$srsrc, i32:{ *:[i32] }:$vaddr, i32:{ *:[i32] }:$soffset, i32:{ *:[i32] }:$offset))<<P:Predicate_unindexedload>><<P:Predicate_sextload>><<P:Predicate_sextloadi16>><<P:Predicate_sextloadi16_private>>  =>  (BUFFER_LOAD_SSHORT_OFFEN:{ *:[i32] } ?:{ *:[i32] }:$vaddr, ?:{ *:[v4i32] }:$srsrc, ?:{ *:[i32] }:$soffset, ?:{ *:[i32] }:$offset, 0:{ *:[i32] }, 0:{ *:[i1] })
      GIR_BuildMI, /*InsnID*/0, /*Opcode*/GIMT_Encode2(AMDGPU::BUFFER_LOAD_SSHORT_OFFEN),
      GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/0, // DstI[vdata]
      GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/1, // vaddr
      GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/0, // srsrc
      GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/2, // soffset
      GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/3, // offset
      GIR_AddImm8, /*InsnID*/0, /*Imm*/0,
      GIR_AddImm8, /*InsnID*/0, /*Imm*/0,
      GIR_MergeMemOperands, /*InsnID*/0, /*NumInsns*/1, /*MergeInsnID's*/0,
      GIR_ConstrainSelectedInstOperands, /*InsnID*/0,
      GIR_EraseFromParent, /*InsnID*/0,
      // GIR_Coverage, 5371,
      GIR_Done,
    // Label 1726: @113051
    GIM_Try, /*On fail goto*//*Label 1727*/ GIMT_Encode4(113133), // Rule ID 5373 //
      GIM_CheckFeatures, GIMT_Encode2(GIFBS_DisableFlatScratch),
      GIM_CheckMemorySizeEqualTo, /*MI*/0, /*MMO*/0, /*Size*/GIMT_Encode4(2),
      GIM_CheckMemoryAddressSpace, /*MI*/0, /*MMO*/0, /*NumAddrSpace*/1, /*AddrSpace*/5,
      GIM_CheckAtomicOrdering, /*MI*/0, /*Order*/(uint8_t)AtomicOrdering::NotAtomic,
      GIM_CheckRegBankForClass, /*MI*/0, /*Op*/0, /*RC*/GIMT_Encode2(AMDGPU::AV_32RegClassID),
      GIM_CheckPointerToAny, /*MI*/0, /*Op*/1, /*SizeInBits*/0,
      GIM_CheckComplexPattern, /*MI*/0, /*Op*/1, /*Renderer*/GIMT_Encode2(0), GIMT_Encode2(GICP_gi_mubuf_scratch_offen),
      // (ld:{ *:[i32] } (MUBUFScratchOffen:{ *:[iPTR] } v4i32:{ *:[v4i32] }:$srsrc, i32:{ *:[i32] }:$vaddr, i32:{ *:[i32] }:$soffset, i32:{ *:[i32] }:$offset))<<P:Predicate_unindexedload>><<P:Predicate_sextload>><<P:Predicate_sextloadi16>><<P:Predicate_sextloadi16_private>>  =>  (BUFFER_LOAD_SSHORT_VBUFFER_OFFEN:{ *:[i32] } ?:{ *:[i32] }:$vaddr, ?:{ *:[v4i32] }:$srsrc, ?:{ *:[i32] }:$soffset, ?:{ *:[i32] }:$offset, 0:{ *:[i32] }, 0:{ *:[i1] })
      GIR_BuildMI, /*InsnID*/0, /*Opcode*/GIMT_Encode2(AMDGPU::BUFFER_LOAD_SSHORT_VBUFFER_OFFEN),
      GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/0, // DstI[vdata]
      GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/1, // vaddr
      GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/0, // srsrc
      GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/2, // soffset
      GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/3, // offset
      GIR_AddImm8, /*InsnID*/0, /*Imm*/0,
      GIR_AddImm8, /*InsnID*/0, /*Imm*/0,
      GIR_MergeMemOperands, /*InsnID*/0, /*NumInsns*/1, /*MergeInsnID's*/0,
      GIR_ConstrainSelectedInstOperands, /*InsnID*/0,
      GIR_EraseFromParent, /*InsnID*/0,
      // GIR_Coverage, 5373,
      GIR_Done,
    // Label 1727: @113133
    GIM_Try, /*On fail goto*//*Label 1728*/ GIMT_Encode4(113212), // Rule ID 3667 //
      GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasUnrestrictedSOffset),
      GIM_CheckMemorySizeEqualTo, /*MI*/0, /*MMO*/0, /*Size*/GIMT_Encode4(1),
      GIM_CheckMemoryAddressSpace, /*MI*/0, /*MMO*/0, /*NumAddrSpace*/3, /*AddrSpace*/1, /*AddrSpace*/4, /*AddrSpace*/6,
      GIM_CheckAtomicOrdering, /*MI*/0, /*Order*/(uint8_t)AtomicOrdering::NotAtomic,
      GIM_CheckRegBankForClass, /*MI*/0, /*Op*/0, /*RC*/GIMT_Encode2(AMDGPU::AV_32RegClassID),
      GIM_CheckPointerToAny, /*MI*/0, /*Op*/1, /*SizeInBits*/0,
      GIM_CheckComplexPattern, /*MI*/0, /*Op*/1, /*Renderer*/GIMT_Encode2(0), GIMT_Encode2(GICP_gi_mubuf_offset),
      // (ld:{ *:[i32] } (MUBUFOffset:{ *:[iPTR] } v4i32:{ *:[v4i32] }:$srsrc, i32:{ *:[i32] }:$soffset, i32:{ *:[i32] }:$offset))<<P:Predicate_unindexedload>><<P:Predicate_sextload>><<P:Predicate_sextloadi8>><<P:Predicate_sextloadi8_global>>  =>  (BUFFER_LOAD_SBYTE_OFFSET:{ *:[i32] } v4i32:{ *:[v4i32] }:$srsrc, i32:{ *:[i32] }:$soffset, i32:{ *:[i32] }:$offset)
      GIR_BuildMI, /*InsnID*/0, /*Opcode*/GIMT_Encode2(AMDGPU::BUFFER_LOAD_SBYTE_OFFSET),
      GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/0, // DstI[vdata]
      GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/0, // srsrc
      GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/1, // soffset
      GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/2, // offset
      GIR_AddImm8, /*InsnID*/0, /*Imm*/0,
      GIR_AddImm8, /*InsnID*/0, /*Imm*/0,
      GIR_MergeMemOperands, /*InsnID*/0, /*NumInsns*/1, /*MergeInsnID's*/0,
      GIR_ConstrainSelectedInstOperands, /*InsnID*/0,
      GIR_EraseFromParent, /*InsnID*/0,
      // GIR_Coverage, 3667,
      GIR_Done,
    // Label 1728: @113212
    GIM_Try, /*On fail goto*//*Label 1729*/ GIMT_Encode4(113288), // Rule ID 3669 //
      GIM_CheckMemorySizeEqualTo, /*MI*/0, /*MMO*/0, /*Size*/GIMT_Encode4(1),
      GIM_CheckMemoryAddressSpace, /*MI*/0, /*MMO*/0, /*NumAddrSpace*/3, /*AddrSpace*/1, /*AddrSpace*/4, /*AddrSpace*/6,
      GIM_CheckAtomicOrdering, /*MI*/0, /*Order*/(uint8_t)AtomicOrdering::NotAtomic,
      GIM_CheckRegBankForClass, /*MI*/0, /*Op*/0, /*RC*/GIMT_Encode2(AMDGPU::AV_32RegClassID),
      GIM_CheckPointerToAny, /*MI*/0, /*Op*/1, /*SizeInBits*/0,
      GIM_CheckComplexPattern, /*MI*/0, /*Op*/1, /*Renderer*/GIMT_Encode2(0), GIMT_Encode2(GICP_gi_mubuf_offset),
      // (ld:{ *:[i32] } (MUBUFOffset:{ *:[iPTR] } v4i32:{ *:[v4i32] }:$srsrc, i32:{ *:[i32] }:$soffset, i32:{ *:[i32] }:$offset))<<P:Predicate_unindexedload>><<P:Predicate_sextload>><<P:Predicate_sextloadi8>><<P:Predicate_sextloadi8_global>>  =>  (BUFFER_LOAD_SBYTE_VBUFFER_OFFSET:{ *:[i32] } v4i32:{ *:[v4i32] }:$srsrc, i32:{ *:[i32] }:$soffset, i32:{ *:[i32] }:$offset)
      GIR_BuildMI, /*InsnID*/0, /*Opcode*/GIMT_Encode2(AMDGPU::BUFFER_LOAD_SBYTE_VBUFFER_OFFSET),
      GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/0, // DstI[vdata]
      GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/0, // srsrc
      GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/1, // soffset
      GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/2, // offset
      GIR_AddImm8, /*InsnID*/0, /*Imm*/0,
      GIR_AddImm8, /*InsnID*/0, /*Imm*/0,
      GIR_MergeMemOperands, /*InsnID*/0, /*NumInsns*/1, /*MergeInsnID's*/0,
      GIR_ConstrainSelectedInstOperands, /*InsnID*/0,
      GIR_EraseFromParent, /*InsnID*/0,
      // GIR_Coverage, 3669,
      GIR_Done,
    // Label 1729: @113288
    GIM_Try, /*On fail goto*//*Label 1730*/ GIMT_Encode4(113367), // Rule ID 3679 //
      GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasUnrestrictedSOffset),
      GIM_CheckMemorySizeEqualTo, /*MI*/0, /*MMO*/0, /*Size*/GIMT_Encode4(2),
      GIM_CheckMemoryAddressSpace, /*MI*/0, /*MMO*/0, /*NumAddrSpace*/3, /*AddrSpace*/1, /*AddrSpace*/4, /*AddrSpace*/6,
      GIM_CheckAtomicOrdering, /*MI*/0, /*Order*/(uint8_t)AtomicOrdering::NotAtomic,
      GIM_CheckRegBankForClass, /*MI*/0, /*Op*/0, /*RC*/GIMT_Encode2(AMDGPU::AV_32RegClassID),
      GIM_CheckPointerToAny, /*MI*/0, /*Op*/1, /*SizeInBits*/0,
      GIM_CheckComplexPattern, /*MI*/0, /*Op*/1, /*Renderer*/GIMT_Encode2(0), GIMT_Encode2(GICP_gi_mubuf_offset),
      // (ld:{ *:[i32] } (MUBUFOffset:{ *:[iPTR] } v4i32:{ *:[v4i32] }:$srsrc, i32:{ *:[i32] }:$soffset, i32:{ *:[i32] }:$offset))<<P:Predicate_unindexedload>><<P:Predicate_sextload>><<P:Predicate_sextloadi16>><<P:Predicate_sextloadi16_global>>  =>  (BUFFER_LOAD_SSHORT_OFFSET:{ *:[i32] } v4i32:{ *:[v4i32] }:$srsrc, i32:{ *:[i32] }:$soffset, i32:{ *:[i32] }:$offset)
      GIR_BuildMI, /*InsnID*/0, /*Opcode*/GIMT_Encode2(AMDGPU::BUFFER_LOAD_SSHORT_OFFSET),
      GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/0, // DstI[vdata]
      GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/0, // srsrc
      GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/1, // soffset
      GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/2, // offset
      GIR_AddImm8, /*InsnID*/0, /*Imm*/0,
      GIR_AddImm8, /*InsnID*/0, /*Imm*/0,
      GIR_MergeMemOperands, /*InsnID*/0, /*NumInsns*/1, /*MergeInsnID's*/0,
      GIR_ConstrainSelectedInstOperands, /*InsnID*/0,
      GIR_EraseFromParent, /*InsnID*/0,
      // GIR_Coverage, 3679,
      GIR_Done,
    // Label 1730: @113367
    GIM_Try, /*On fail goto*//*Label 1731*/ GIMT_Encode4(113443), // Rule ID 3681 //
      GIM_CheckMemorySizeEqualTo, /*MI*/0, /*MMO*/0, /*Size*/GIMT_Encode4(2),
      GIM_CheckMemoryAddressSpace, /*MI*/0, /*MMO*/0, /*NumAddrSpace*/3, /*AddrSpace*/1, /*AddrSpace*/4, /*AddrSpace*/6,
      GIM_CheckAtomicOrdering, /*MI*/0, /*Order*/(uint8_t)AtomicOrdering::NotAtomic,
      GIM_CheckRegBankForClass, /*MI*/0, /*Op*/0, /*RC*/GIMT_Encode2(AMDGPU::AV_32RegClassID),
      GIM_CheckPointerToAny, /*MI*/0, /*Op*/1, /*SizeInBits*/0,
      GIM_CheckComplexPattern, /*MI*/0, /*Op*/1, /*Renderer*/GIMT_Encode2(0), GIMT_Encode2(GICP_gi_mubuf_offset),
      // (ld:{ *:[i32] } (MUBUFOffset:{ *:[iPTR] } v4i32:{ *:[v4i32] }:$srsrc, i32:{ *:[i32] }:$soffset, i32:{ *:[i32] }:$offset))<<P:Predicate_unindexedload>><<P:Predicate_sextload>><<P:Predicate_sextloadi16>><<P:Predicate_sextloadi16_global>>  =>  (BUFFER_LOAD_SSHORT_VBUFFER_OFFSET:{ *:[i32] } v4i32:{ *:[v4i32] }:$srsrc, i32:{ *:[i32] }:$soffset, i32:{ *:[i32] }:$offset)
      GIR_BuildMI, /*InsnID*/0, /*Opcode*/GIMT_Encode2(AMDGPU::BUFFER_LOAD_SSHORT_VBUFFER_OFFSET),
      GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/0, // DstI[vdata]
      GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/0, // srsrc
      GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/1, // soffset
      GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/2, // offset
      GIR_AddImm8, /*InsnID*/0, /*Imm*/0,
      GIR_AddImm8, /*InsnID*/0, /*Imm*/0,
      GIR_MergeMemOperands, /*InsnID*/0, /*NumInsns*/1, /*MergeInsnID's*/0,
      GIR_ConstrainSelectedInstOperands, /*InsnID*/0,
      GIR_EraseFromParent, /*InsnID*/0,
      // GIR_Coverage, 3681,
      GIR_Done,
    // Label 1731: @113443
    GIM_Try, /*On fail goto*//*Label 1732*/ GIMT_Encode4(113512), // Rule ID 6567 //
      GIM_CheckFeatures, GIMT_Encode2(GIFBS_LDSRequiresM0Init),
      GIM_CheckMemorySizeEqualTo, /*MI*/0, /*MMO*/0, /*Size*/GIMT_Encode4(1),
      GIM_CheckMemoryAddressSpace, /*MI*/0, /*MMO*/0, /*NumAddrSpace*/1, /*AddrSpace*/3,
      GIM_CheckAtomicOrdering, /*MI*/0, /*Order*/(uint8_t)AtomicOrdering::NotAtomic,
      GIM_CheckRegBankForClass, /*MI*/0, /*Op*/0, /*RC*/GIMT_Encode2(AMDGPU::AV_32RegClassID),
      GIM_CheckPointerToAny, /*MI*/0, /*Op*/1, /*SizeInBits*/0,
      GIM_CheckComplexPattern, /*MI*/0, /*Op*/1, /*Renderer*/GIMT_Encode2(0), GIMT_Encode2(GICP_gi_ds_1addr_1offset),
      // (AMDGPUld_glue:{ *:[i32] } (DS1Addr1Offset:{ *:[iPTR] } i32:{ *:[i32] }:$ptr, i32:{ *:[i32] }:$offset))<<P:Predicate_unindexedload_glue>><<P:Predicate_sextload_glue>><<P:Predicate_sextloadi8_glue>><<P:Predicate_sextloadi8_local_m0>>  =>  (DS_READ_I8:{ *:[i32] } ?:{ *:[i32] }:$ptr, offset:{ *:[i32] }:$offset, 0:{ *:[i1] })
      GIR_BuildMI, /*InsnID*/0, /*Opcode*/GIMT_Encode2(AMDGPU::DS_READ_I8),
      GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/0, // DstI[vdst]
      GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/0, // ptr
      GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/1, // offset
      GIR_AddImm8, /*InsnID*/0, /*Imm*/0,
      GIR_MergeMemOperands, /*InsnID*/0, /*NumInsns*/1, /*MergeInsnID's*/0,
      GIR_ConstrainSelectedInstOperands, /*InsnID*/0,
      GIR_EraseFromParent, /*InsnID*/0,
      // GIR_Coverage, 6567,
      GIR_Done,
    // Label 1732: @113512
    GIM_Try, /*On fail goto*//*Label 1733*/ GIMT_Encode4(113581), // Rule ID 6568 //
      GIM_CheckFeatures, GIMT_Encode2(GIFBS_NotLDSRequiresM0Init),
      GIM_CheckMemorySizeEqualTo, /*MI*/0, /*MMO*/0, /*Size*/GIMT_Encode4(1),
      GIM_CheckMemoryAddressSpace, /*MI*/0, /*MMO*/0, /*NumAddrSpace*/1, /*AddrSpace*/3,
      GIM_CheckAtomicOrdering, /*MI*/0, /*Order*/(uint8_t)AtomicOrdering::NotAtomic,
      GIM_CheckRegBankForClass, /*MI*/0, /*Op*/0, /*RC*/GIMT_Encode2(AMDGPU::AV_32RegClassID),
      GIM_CheckPointerToAny, /*MI*/0, /*Op*/1, /*SizeInBits*/0,
      GIM_CheckComplexPattern, /*MI*/0, /*Op*/1, /*Renderer*/GIMT_Encode2(0), GIMT_Encode2(GICP_gi_ds_1addr_1offset),
      // (ld:{ *:[i32] } (DS1Addr1Offset:{ *:[iPTR] } i32:{ *:[i32] }:$ptr, i32:{ *:[i32] }:$offset))<<P:Predicate_unindexedload>><<P:Predicate_sextload>><<P:Predicate_sextloadi8>><<P:Predicate_sextloadi8_local>>  =>  (DS_READ_I8_gfx9:{ *:[i32] } ?:{ *:[i32] }:$ptr, offset:{ *:[i32] }:$offset, 0:{ *:[i1] })
      GIR_BuildMI, /*InsnID*/0, /*Opcode*/GIMT_Encode2(AMDGPU::DS_READ_I8_gfx9),
      GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/0, // DstI[vdst]
      GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/0, // ptr
      GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/1, // offset
      GIR_AddImm8, /*InsnID*/0, /*Imm*/0,
      GIR_MergeMemOperands, /*InsnID*/0, /*NumInsns*/1, /*MergeInsnID's*/0,
      GIR_ConstrainSelectedInstOperands, /*InsnID*/0,
      GIR_EraseFromParent, /*InsnID*/0,
      // GIR_Coverage, 6568,
      GIR_Done,
    // Label 1733: @113581
    GIM_Try, /*On fail goto*//*Label 1734*/ GIMT_Encode4(113650), // Rule ID 6579 //
      GIM_CheckFeatures, GIMT_Encode2(GIFBS_LDSRequiresM0Init),
      GIM_CheckMemorySizeEqualTo, /*MI*/0, /*MMO*/0, /*Size*/GIMT_Encode4(2),
      GIM_CheckMemoryAddressSpace, /*MI*/0, /*MMO*/0, /*NumAddrSpace*/1, /*AddrSpace*/3,
      GIM_CheckAtomicOrdering, /*MI*/0, /*Order*/(uint8_t)AtomicOrdering::NotAtomic,
      GIM_CheckRegBankForClass, /*MI*/0, /*Op*/0, /*RC*/GIMT_Encode2(AMDGPU::AV_32RegClassID),
      GIM_CheckPointerToAny, /*MI*/0, /*Op*/1, /*SizeInBits*/0,
      GIM_CheckComplexPattern, /*MI*/0, /*Op*/1, /*Renderer*/GIMT_Encode2(0), GIMT_Encode2(GICP_gi_ds_1addr_1offset),
      // (AMDGPUld_glue:{ *:[i32] } (DS1Addr1Offset:{ *:[iPTR] } i32:{ *:[i32] }:$ptr, i32:{ *:[i32] }:$offset))<<P:Predicate_unindexedload_glue>><<P:Predicate_sextload_glue>><<P:Predicate_sextloadi16_glue>><<P:Predicate_sextloadi16_local_m0>>  =>  (DS_READ_I16:{ *:[i32] } ?:{ *:[i32] }:$ptr, offset:{ *:[i32] }:$offset, 0:{ *:[i1] })
      GIR_BuildMI, /*InsnID*/0, /*Opcode*/GIMT_Encode2(AMDGPU::DS_READ_I16),
      GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/0, // DstI[vdst]
      GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/0, // ptr
      GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/1, // offset
      GIR_AddImm8, /*InsnID*/0, /*Imm*/0,
      GIR_MergeMemOperands, /*InsnID*/0, /*NumInsns*/1, /*MergeInsnID's*/0,
      GIR_ConstrainSelectedInstOperands, /*InsnID*/0,
      GIR_EraseFromParent, /*InsnID*/0,
      // GIR_Coverage, 6579,
      GIR_Done,
    // Label 1734: @113650
    GIM_Try, /*On fail goto*//*Label 1735*/ GIMT_Encode4(113719), // Rule ID 6580 //
      GIM_CheckFeatures, GIMT_Encode2(GIFBS_NotLDSRequiresM0Init),
      GIM_CheckMemorySizeEqualTo, /*MI*/0, /*MMO*/0, /*Size*/GIMT_Encode4(2),
      GIM_CheckMemoryAddressSpace, /*MI*/0, /*MMO*/0, /*NumAddrSpace*/1, /*AddrSpace*/3,
      GIM_CheckAtomicOrdering, /*MI*/0, /*Order*/(uint8_t)AtomicOrdering::NotAtomic,
      GIM_CheckRegBankForClass, /*MI*/0, /*Op*/0, /*RC*/GIMT_Encode2(AMDGPU::AV_32RegClassID),
      GIM_CheckPointerToAny, /*MI*/0, /*Op*/1, /*SizeInBits*/0,
      GIM_CheckComplexPattern, /*MI*/0, /*Op*/1, /*Renderer*/GIMT_Encode2(0), GIMT_Encode2(GICP_gi_ds_1addr_1offset),
      // (ld:{ *:[i32] } (DS1Addr1Offset:{ *:[iPTR] } i32:{ *:[i32] }:$ptr, i32:{ *:[i32] }:$offset))<<P:Predicate_unindexedload>><<P:Predicate_sextload>><<P:Predicate_sextloadi16>><<P:Predicate_sextloadi16_local>>  =>  (DS_READ_I16_gfx9:{ *:[i32] } ?:{ *:[i32] }:$ptr, offset:{ *:[i32] }:$offset, 0:{ *:[i1] })
      GIR_BuildMI, /*InsnID*/0, /*Opcode*/GIMT_Encode2(AMDGPU::DS_READ_I16_gfx9),
      GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/0, // DstI[vdst]
      GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/0, // ptr
      GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/1, // offset
      GIR_AddImm8, /*InsnID*/0, /*Imm*/0,
      GIR_MergeMemOperands, /*InsnID*/0, /*NumInsns*/1, /*MergeInsnID's*/0,
      GIR_ConstrainSelectedInstOperands, /*InsnID*/0,
      GIR_EraseFromParent, /*InsnID*/0,
      // GIR_Coverage, 6580,
      GIR_Done,
    // Label 1735: @113719
    GIM_Try, /*On fail goto*//*Label 1736*/ GIMT_Encode4(113788), // Rule ID 6581 //
      GIM_CheckFeatures, GIMT_Encode2(GIFBS_LDSRequiresM0Init),
      GIM_CheckMemorySizeEqualTo, /*MI*/0, /*MMO*/0, /*Size*/GIMT_Encode4(2),
      GIM_CheckMemoryAddressSpace, /*MI*/0, /*MMO*/0, /*NumAddrSpace*/1, /*AddrSpace*/3,
      GIM_CheckAtomicOrdering, /*MI*/0, /*Order*/(uint8_t)AtomicOrdering::NotAtomic,
      GIM_CheckRegBankForClass, /*MI*/0, /*Op*/0, /*RC*/GIMT_Encode2(AMDGPU::AV_32RegClassID),
      GIM_CheckPointerToAny, /*MI*/0, /*Op*/1, /*SizeInBits*/0,
      GIM_CheckComplexPattern, /*MI*/0, /*Op*/1, /*Renderer*/GIMT_Encode2(0), GIMT_Encode2(GICP_gi_ds_1addr_1offset),
      // (AMDGPUld_glue:{ *:[i32] } (DS1Addr1Offset:{ *:[iPTR] } i32:{ *:[i32] }:$ptr, i32:{ *:[i32] }:$offset))<<P:Predicate_unindexedload_glue>><<P:Predicate_sextload_glue>><<P:Predicate_sextloadi16_glue>><<P:Predicate_sextloadi16_local_m0>>  =>  (DS_READ_I16:{ *:[i32] } ?:{ *:[i32] }:$ptr, offset:{ *:[i32] }:$offset, 0:{ *:[i1] })
      GIR_BuildMI, /*InsnID*/0, /*Opcode*/GIMT_Encode2(AMDGPU::DS_READ_I16),
      GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/0, // DstI[vdst]
      GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/0, // ptr
      GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/1, // offset
      GIR_AddImm8, /*InsnID*/0, /*Imm*/0,
      GIR_MergeMemOperands, /*InsnID*/0, /*NumInsns*/1, /*MergeInsnID's*/0,
      GIR_ConstrainSelectedInstOperands, /*InsnID*/0,
      GIR_EraseFromParent, /*InsnID*/0,
      // GIR_Coverage, 6581,
      GIR_Done,
    // Label 1736: @113788
    GIM_Try, /*On fail goto*//*Label 1737*/ GIMT_Encode4(113857), // Rule ID 6582 //
      GIM_CheckFeatures, GIMT_Encode2(GIFBS_NotLDSRequiresM0Init),
      GIM_CheckMemorySizeEqualTo, /*MI*/0, /*MMO*/0, /*Size*/GIMT_Encode4(2),
      GIM_CheckMemoryAddressSpace, /*MI*/0, /*MMO*/0, /*NumAddrSpace*/1, /*AddrSpace*/3,
      GIM_CheckAtomicOrdering, /*MI*/0, /*Order*/(uint8_t)AtomicOrdering::NotAtomic,
      GIM_CheckRegBankForClass, /*MI*/0, /*Op*/0, /*RC*/GIMT_Encode2(AMDGPU::AV_32RegClassID),
      GIM_CheckPointerToAny, /*MI*/0, /*Op*/1, /*SizeInBits*/0,
      GIM_CheckComplexPattern, /*MI*/0, /*Op*/1, /*Renderer*/GIMT_Encode2(0), GIMT_Encode2(GICP_gi_ds_1addr_1offset),
      // (ld:{ *:[i32] } (DS1Addr1Offset:{ *:[iPTR] } i32:{ *:[i32] }:$ptr, i32:{ *:[i32] }:$offset))<<P:Predicate_unindexedload>><<P:Predicate_sextload>><<P:Predicate_sextloadi16>><<P:Predicate_sextloadi16_local>>  =>  (DS_READ_I16_gfx9:{ *:[i32] } ?:{ *:[i32] }:$ptr, offset:{ *:[i32] }:$offset, 0:{ *:[i1] })
      GIR_BuildMI, /*InsnID*/0, /*Opcode*/GIMT_Encode2(AMDGPU::DS_READ_I16_gfx9),
      GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/0, // DstI[vdst]
      GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/0, // ptr
      GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/1, // offset
      GIR_AddImm8, /*InsnID*/0, /*Imm*/0,
      GIR_MergeMemOperands, /*InsnID*/0, /*NumInsns*/1, /*MergeInsnID's*/0,
      GIR_ConstrainSelectedInstOperands, /*InsnID*/0,
      GIR_EraseFromParent, /*InsnID*/0,
      // GIR_Coverage, 6582,
      GIR_Done,
    // Label 1737: @113857
    GIM_Try, /*On fail goto*//*Label 1738*/ GIMT_Encode4(113933), // Rule ID 2979 //
      GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasFlatGlobalInsts),
      GIM_CheckMemorySizeEqualTo, /*MI*/0, /*MMO*/0, /*Size*/GIMT_Encode4(1),
      GIM_CheckMemoryAddressSpace, /*MI*/0, /*MMO*/0, /*NumAddrSpace*/3, /*AddrSpace*/1, /*AddrSpace*/4, /*AddrSpace*/6,
      GIM_CheckAtomicOrdering, /*MI*/0, /*Order*/(uint8_t)AtomicOrdering::NotAtomic,
      GIM_CheckRegBankForClass, /*MI*/0, /*Op*/0, /*RC*/GIMT_Encode2(AMDGPU::AV_32RegClassID),
      GIM_CheckPointerToAny, /*MI*/0, /*Op*/1, /*SizeInBits*/0,
      GIM_CheckComplexPattern, /*MI*/0, /*Op*/1, /*Renderer*/GIMT_Encode2(0), GIMT_Encode2(GICP_gi_global_saddr),
      // (ld:{ *:[i32] } (GlobalSAddr:{ *:[iPTR] } SReg_64:{ *:[i64] }:$saddr, VGPR_32:{ *:[i32] }:$voffset, i32:{ *:[i32] }:$offset))<<P:Predicate_unindexedload>><<P:Predicate_sextload>><<P:Predicate_sextloadi8>><<P:Predicate_sextloadi8_global>>  =>  (GLOBAL_LOAD_SBYTE_SADDR:{ *:[i32] } ?:{ *:[i64] }:$saddr, ?:{ *:[i32] }:$voffset, ?:{ *:[i32] }:$offset, 0:{ *:[i32] })
      GIR_BuildMI, /*InsnID*/0, /*Opcode*/GIMT_Encode2(AMDGPU::GLOBAL_LOAD_SBYTE_SADDR),
      GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/0, // DstI[vdst]
      GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/0, // saddr
      GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/1, // voffset
      GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/2, // offset
      GIR_AddImm8, /*InsnID*/0, /*Imm*/0,
      GIR_MergeMemOperands, /*InsnID*/0, /*NumInsns*/1, /*MergeInsnID's*/0,
      GIR_ConstrainSelectedInstOperands, /*InsnID*/0,
      GIR_EraseFromParent, /*InsnID*/0,
      // GIR_Coverage, 2979,
      GIR_Done,
    // Label 1738: @113933
    GIM_Try, /*On fail goto*//*Label 1739*/ GIMT_Encode4(114009), // Rule ID 2991 //
      GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasFlatGlobalInsts),
      GIM_CheckMemorySizeEqualTo, /*MI*/0, /*MMO*/0, /*Size*/GIMT_Encode4(2),
      GIM_CheckMemoryAddressSpace, /*MI*/0, /*MMO*/0, /*NumAddrSpace*/3, /*AddrSpace*/1, /*AddrSpace*/4, /*AddrSpace*/6,
      GIM_CheckAtomicOrdering, /*MI*/0, /*Order*/(uint8_t)AtomicOrdering::NotAtomic,
      GIM_CheckRegBankForClass, /*MI*/0, /*Op*/0, /*RC*/GIMT_Encode2(AMDGPU::AV_32RegClassID),
      GIM_CheckPointerToAny, /*MI*/0, /*Op*/1, /*SizeInBits*/0,
      GIM_CheckComplexPattern, /*MI*/0, /*Op*/1, /*Renderer*/GIMT_Encode2(0), GIMT_Encode2(GICP_gi_global_saddr),
      // (ld:{ *:[i32] } (GlobalSAddr:{ *:[iPTR] } SReg_64:{ *:[i64] }:$saddr, VGPR_32:{ *:[i32] }:$voffset, i32:{ *:[i32] }:$offset))<<P:Predicate_unindexedload>><<P:Predicate_sextload>><<P:Predicate_sextloadi16>><<P:Predicate_sextloadi16_global>>  =>  (GLOBAL_LOAD_SSHORT_SADDR:{ *:[i32] } ?:{ *:[i64] }:$saddr, ?:{ *:[i32] }:$voffset, ?:{ *:[i32] }:$offset, 0:{ *:[i32] })
      GIR_BuildMI, /*InsnID*/0, /*Opcode*/GIMT_Encode2(AMDGPU::GLOBAL_LOAD_SSHORT_SADDR),
      GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/0, // DstI[vdst]
      GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/0, // saddr
      GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/1, // voffset
      GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/2, // offset
      GIR_AddImm8, /*InsnID*/0, /*Imm*/0,
      GIR_MergeMemOperands, /*InsnID*/0, /*NumInsns*/1, /*MergeInsnID's*/0,
      GIR_ConstrainSelectedInstOperands, /*InsnID*/0,
      GIR_EraseFromParent, /*InsnID*/0,
      // GIR_Coverage, 2991,
      GIR_Done,
    // Label 1739: @114009
    GIM_Try, /*On fail goto*//*Label 1740*/ GIMT_Encode4(114080), // Rule ID 2978 //
      GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasFlatGlobalInsts),
      GIM_CheckMemorySizeEqualTo, /*MI*/0, /*MMO*/0, /*Size*/GIMT_Encode4(1),
      GIM_CheckMemoryAddressSpace, /*MI*/0, /*MMO*/0, /*NumAddrSpace*/3, /*AddrSpace*/1, /*AddrSpace*/4, /*AddrSpace*/6,
      GIM_CheckAtomicOrdering, /*MI*/0, /*Order*/(uint8_t)AtomicOrdering::NotAtomic,
      GIM_CheckRegBankForClass, /*MI*/0, /*Op*/0, /*RC*/GIMT_Encode2(AMDGPU::AV_32RegClassID),
      GIM_CheckPointerToAny, /*MI*/0, /*Op*/1, /*SizeInBits*/0,
      GIM_CheckComplexPattern, /*MI*/0, /*Op*/1, /*Renderer*/GIMT_Encode2(0), GIMT_Encode2(GICP_gi_global_offset),
      // (ld:{ *:[i32] } (GlobalOffset:{ *:[iPTR] } VReg_64:{ *:[i64] }:$vaddr, i32:{ *:[i32] }:$offset))<<P:Predicate_unindexedload>><<P:Predicate_sextload>><<P:Predicate_sextloadi8>><<P:Predicate_sextloadi8_global>>  =>  (GLOBAL_LOAD_SBYTE:{ *:[i32] } ?:{ *:[i64] }:$vaddr, ?:{ *:[i32] }:$offset)
      GIR_BuildMI, /*InsnID*/0, /*Opcode*/GIMT_Encode2(AMDGPU::GLOBAL_LOAD_SBYTE),
      GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/0, // DstI[vdst]
      GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/0, // vaddr
      GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/1, // offset
      GIR_AddImm8, /*InsnID*/0, /*Imm*/0,
      GIR_MergeMemOperands, /*InsnID*/0, /*NumInsns*/1, /*MergeInsnID's*/0,
      GIR_ConstrainSelectedInstOperands, /*InsnID*/0,
      GIR_EraseFromParent, /*InsnID*/0,
      // GIR_Coverage, 2978,
      GIR_Done,
    // Label 1740: @114080
    GIM_Try, /*On fail goto*//*Label 1741*/ GIMT_Encode4(114151), // Rule ID 2990 //
      GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasFlatGlobalInsts),
      GIM_CheckMemorySizeEqualTo, /*MI*/0, /*MMO*/0, /*Size*/GIMT_Encode4(2),
      GIM_CheckMemoryAddressSpace, /*MI*/0, /*MMO*/0, /*NumAddrSpace*/3, /*AddrSpace*/1, /*AddrSpace*/4, /*AddrSpace*/6,
      GIM_CheckAtomicOrdering, /*MI*/0, /*Order*/(uint8_t)AtomicOrdering::NotAtomic,
      GIM_CheckRegBankForClass, /*MI*/0, /*Op*/0, /*RC*/GIMT_Encode2(AMDGPU::AV_32RegClassID),
      GIM_CheckPointerToAny, /*MI*/0, /*Op*/1, /*SizeInBits*/0,
      GIM_CheckComplexPattern, /*MI*/0, /*Op*/1, /*Renderer*/GIMT_Encode2(0), GIMT_Encode2(GICP_gi_global_offset),
      // (ld:{ *:[i32] } (GlobalOffset:{ *:[iPTR] } VReg_64:{ *:[i64] }:$vaddr, i32:{ *:[i32] }:$offset))<<P:Predicate_unindexedload>><<P:Predicate_sextload>><<P:Predicate_sextloadi16>><<P:Predicate_sextloadi16_global>>  =>  (GLOBAL_LOAD_SSHORT:{ *:[i32] } ?:{ *:[i64] }:$vaddr, ?:{ *:[i32] }:$offset)
      GIR_BuildMI, /*InsnID*/0, /*Opcode*/GIMT_Encode2(AMDGPU::GLOBAL_LOAD_SSHORT),
      GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/0, // DstI[vdst]
      GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/0, // vaddr
      GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/1, // offset
      GIR_AddImm8, /*InsnID*/0, /*Imm*/0,
      GIR_MergeMemOperands, /*InsnID*/0, /*NumInsns*/1, /*MergeInsnID's*/0,
      GIR_ConstrainSelectedInstOperands, /*InsnID*/0,
      GIR_EraseFromParent, /*InsnID*/0,
      // GIR_Coverage, 2990,
      GIR_Done,
    // Label 1741: @114151
    GIM_Try, /*On fail goto*//*Label 1742*/ GIMT_Encode4(114223), // Rule ID 2757 //
      GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasFlatAddressSpace),
      GIM_CheckMemorySizeEqualTo, /*MI*/0, /*MMO*/0, /*Size*/GIMT_Encode4(1),
      GIM_CheckMemoryAddressSpace, /*MI*/0, /*MMO*/0, /*NumAddrSpace*/4, /*AddrSpace*/0, /*AddrSpace*/1, /*AddrSpace*/4, /*AddrSpace*/6,
      GIM_CheckAtomicOrdering, /*MI*/0, /*Order*/(uint8_t)AtomicOrdering::NotAtomic,
      GIM_CheckRegBankForClass, /*MI*/0, /*Op*/0, /*RC*/GIMT_Encode2(AMDGPU::AV_32RegClassID),
      GIM_CheckPointerToAny, /*MI*/0, /*Op*/1, /*SizeInBits*/0,
      GIM_CheckComplexPattern, /*MI*/0, /*Op*/1, /*Renderer*/GIMT_Encode2(0), GIMT_Encode2(GICP_gi_flat_offset),
      // (ld:{ *:[i32] } (FlatOffset:{ *:[iPTR] } i64:{ *:[i64] }:$vaddr, i32:{ *:[i32] }:$offset))<<P:Predicate_unindexedload>><<P:Predicate_sextload>><<P:Predicate_sextloadi8>><<P:Predicate_sextloadi8_flat>>  =>  (FLAT_LOAD_SBYTE:{ *:[i32] } ?:{ *:[i64] }:$vaddr, ?:{ *:[i32] }:$offset)
      GIR_BuildMI, /*InsnID*/0, /*Opcode*/GIMT_Encode2(AMDGPU::FLAT_LOAD_SBYTE),
      GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/0, // DstI[vdst]
      GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/0, // vaddr
      GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/1, // offset
      GIR_AddImm8, /*InsnID*/0, /*Imm*/0,
      GIR_MergeMemOperands, /*InsnID*/0, /*NumInsns*/1, /*MergeInsnID's*/0,
      GIR_ConstrainSelectedInstOperands, /*InsnID*/0,
      GIR_EraseFromParent, /*InsnID*/0,
      // GIR_Coverage, 2757,
      GIR_Done,
    // Label 1742: @114223
    GIM_Try, /*On fail goto*//*Label 1743*/ GIMT_Encode4(114295), // Rule ID 2764 //
      GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasFlatAddressSpace),
      GIM_CheckMemorySizeEqualTo, /*MI*/0, /*MMO*/0, /*Size*/GIMT_Encode4(2),
      GIM_CheckMemoryAddressSpace, /*MI*/0, /*MMO*/0, /*NumAddrSpace*/4, /*AddrSpace*/0, /*AddrSpace*/1, /*AddrSpace*/4, /*AddrSpace*/6,
      GIM_CheckAtomicOrdering, /*MI*/0, /*Order*/(uint8_t)AtomicOrdering::NotAtomic,
      GIM_CheckRegBankForClass, /*MI*/0, /*Op*/0, /*RC*/GIMT_Encode2(AMDGPU::AV_32RegClassID),
      GIM_CheckPointerToAny, /*MI*/0, /*Op*/1, /*SizeInBits*/0,
      GIM_CheckComplexPattern, /*MI*/0, /*Op*/1, /*Renderer*/GIMT_Encode2(0), GIMT_Encode2(GICP_gi_flat_offset),
      // (ld:{ *:[i32] } (FlatOffset:{ *:[iPTR] } i64:{ *:[i64] }:$vaddr, i32:{ *:[i32] }:$offset))<<P:Predicate_unindexedload>><<P:Predicate_sextload>><<P:Predicate_sextloadi16>><<P:Predicate_sextloadi16_flat>>  =>  (FLAT_LOAD_SSHORT:{ *:[i32] } ?:{ *:[i64] }:$vaddr, ?:{ *:[i32] }:$offset)
      GIR_BuildMI, /*InsnID*/0, /*Opcode*/GIMT_Encode2(AMDGPU::FLAT_LOAD_SSHORT),
      GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/0, // DstI[vdst]
      GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/0, // vaddr
      GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/1, // offset
      GIR_AddImm8, /*InsnID*/0, /*Imm*/0,
      GIR_MergeMemOperands, /*InsnID*/0, /*NumInsns*/1, /*MergeInsnID's*/0,
      GIR_ConstrainSelectedInstOperands, /*InsnID*/0,
      GIR_EraseFromParent, /*InsnID*/0,
      // GIR_Coverage, 2764,
      GIR_Done,
    // Label 1743: @114295
    GIM_Reject,
    // Label 1682: @114296
    GIM_Reject,
    // Label 14: @114297
    GIM_SwitchType, /*MI*/0, /*Op*/0, /*[*/GIMT_Encode2(8), GIMT_Encode2(10), /*)*//*default:*//*Label 1746*/ GIMT_Encode4(118550),
    /*GILLT_s16*//*Label 1744*/ GIMT_Encode4(114316),
    /*GILLT_s32*//*Label 1745*/ GIMT_Encode4(115419),
    // Label 1744: @114316
    GIM_Try, /*On fail goto*//*Label 1747*/ GIMT_Encode4(115418),
      GIM_CheckMemorySizeEqualTo, /*MI*/0, /*MMO*/0, /*Size*/GIMT_Encode4(1),
      GIM_Try, /*On fail goto*//*Label 1748*/ GIMT_Encode4(114398), // Rule ID 5368 //
        GIM_CheckFeatures, GIMT_Encode2(GIFBS_DisableFlatScratch_HasUnrestrictedSOffset),
        GIM_CheckMemoryAddressSpace, /*MI*/0, /*MMO*/0, /*NumAddrSpace*/1, /*AddrSpace*/5,
        GIM_CheckAtomicOrdering, /*MI*/0, /*Order*/(uint8_t)AtomicOrdering::NotAtomic,
        GIM_CheckRegBankForClass, /*MI*/0, /*Op*/0, /*RC*/GIMT_Encode2(AMDGPU::AV_32RegClassID),
        GIM_CheckPointerToAny, /*MI*/0, /*Op*/1, /*SizeInBits*/0,
        GIM_CheckComplexPattern, /*MI*/0, /*Op*/1, /*Renderer*/GIMT_Encode2(0), GIMT_Encode2(GICP_gi_mubuf_scratch_offset),
        // (ld:{ *:[i16] } (MUBUFScratchOffset:{ *:[iPTR] } v4i32:{ *:[v4i32] }:$srsrc, i32:{ *:[i32] }:$soffset, i32:{ *:[i32] }:$offset))<<P:Predicate_unindexedload>><<P:Predicate_zextload>><<P:Predicate_zextloadi8>><<P:Predicate_zextloadi8_private>>  =>  (BUFFER_LOAD_UBYTE_OFFSET:{ *:[i16] } ?:{ *:[v4i32] }:$srsrc, ?:{ *:[i32] }:$soffset, ?:{ *:[i32] }:$offset, 0:{ *:[i32] }, 0:{ *:[i1] })
        GIR_BuildMI, /*InsnID*/0, /*Opcode*/GIMT_Encode2(AMDGPU::BUFFER_LOAD_UBYTE_OFFSET),
        GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/0, // DstI[vdata]
        GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/0, // srsrc
        GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/1, // soffset
        GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/2, // offset
        GIR_AddImm8, /*InsnID*/0, /*Imm*/0,
        GIR_AddImm8, /*InsnID*/0, /*Imm*/0,
        GIR_MergeMemOperands, /*InsnID*/0, /*NumInsns*/1, /*MergeInsnID's*/0,
        GIR_ConstrainSelectedInstOperands, /*InsnID*/0,
        GIR_EraseFromParent, /*InsnID*/0,
        // GIR_Coverage, 5368,
        GIR_Done,
      // Label 1748: @114398
      GIM_Try, /*On fail goto*//*Label 1749*/ GIMT_Encode4(114468), // Rule ID 5370 //
        GIM_CheckFeatures, GIMT_Encode2(GIFBS_DisableFlatScratch),
        GIM_CheckMemoryAddressSpace, /*MI*/0, /*MMO*/0, /*NumAddrSpace*/1, /*AddrSpace*/5,
        GIM_CheckAtomicOrdering, /*MI*/0, /*Order*/(uint8_t)AtomicOrdering::NotAtomic,
        GIM_CheckRegBankForClass, /*MI*/0, /*Op*/0, /*RC*/GIMT_Encode2(AMDGPU::AV_32RegClassID),
        GIM_CheckPointerToAny, /*MI*/0, /*Op*/1, /*SizeInBits*/0,
        GIM_CheckComplexPattern, /*MI*/0, /*Op*/1, /*Renderer*/GIMT_Encode2(0), GIMT_Encode2(GICP_gi_mubuf_scratch_offset),
        // (ld:{ *:[i16] } (MUBUFScratchOffset:{ *:[iPTR] } v4i32:{ *:[v4i32] }:$srsrc, i32:{ *:[i32] }:$soffset, i32:{ *:[i32] }:$offset))<<P:Predicate_unindexedload>><<P:Predicate_zextload>><<P:Predicate_zextloadi8>><<P:Predicate_zextloadi8_private>>  =>  (BUFFER_LOAD_UBYTE_VBUFFER_OFFSET:{ *:[i16] } ?:{ *:[v4i32] }:$srsrc, ?:{ *:[i32] }:$soffset, ?:{ *:[i32] }:$offset, 0:{ *:[i32] }, 0:{ *:[i1] })
        GIR_BuildMI, /*InsnID*/0, /*Opcode*/GIMT_Encode2(AMDGPU::BUFFER_LOAD_UBYTE_VBUFFER_OFFSET),
        GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/0, // DstI[vdata]
        GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/0, // srsrc
        GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/1, // soffset
        GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/2, // offset
        GIR_AddImm8, /*InsnID*/0, /*Imm*/0,
        GIR_AddImm8, /*InsnID*/0, /*Imm*/0,
        GIR_MergeMemOperands, /*InsnID*/0, /*NumInsns*/1, /*MergeInsnID's*/0,
        GIR_ConstrainSelectedInstOperands, /*InsnID*/0,
        GIR_EraseFromParent, /*InsnID*/0,
        // GIR_Coverage, 5370,
        GIR_Done,
      // Label 1749: @114468
      GIM_Try, /*On fail goto*//*Label 1750*/ GIMT_Encode4(114535), // Rule ID 3415 //
        GIM_CheckFeatures, GIMT_Encode2(GIFBS_EnableFlatScratch_HasFlatScratchInsts_HasFlatScratchSVSMode),
        GIM_CheckMemoryAddressSpace, /*MI*/0, /*MMO*/0, /*NumAddrSpace*/1, /*AddrSpace*/5,
        GIM_CheckAtomicOrdering, /*MI*/0, /*Order*/(uint8_t)AtomicOrdering::NotAtomic,
        GIM_CheckRegBankForClass, /*MI*/0, /*Op*/0, /*RC*/GIMT_Encode2(AMDGPU::AV_32RegClassID),
        GIM_CheckPointerToAny, /*MI*/0, /*Op*/1, /*SizeInBits*/0,
        GIM_CheckComplexPattern, /*MI*/0, /*Op*/1, /*Renderer*/GIMT_Encode2(0), GIMT_Encode2(GICP_gi_flat_scratch_svaddr),
        // (ld:{ *:[i16] } (ScratchSVAddr:{ *:[iPTR] } VGPR_32:{ *:[i32] }:$vaddr, SGPR_32:{ *:[i32] }:$saddr, i32:{ *:[i32] }:$offset))<<P:Predicate_unindexedload>><<P:Predicate_zextload>><<P:Predicate_zextloadi8>><<P:Predicate_zextloadi8_private>>  =>  (SCRATCH_LOAD_UBYTE_SVS:{ *:[i16] } ?:{ *:[i32] }:$vaddr, ?:{ *:[i32] }:$saddr, ?:{ *:[i32] }:$offset, 0:{ *:[i32] })
        GIR_BuildMI, /*InsnID*/0, /*Opcode*/GIMT_Encode2(AMDGPU::SCRATCH_LOAD_UBYTE_SVS),
        GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/0, // DstI[vdst]
        GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/0, // vaddr
        GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/1, // saddr
        GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/2, // offset
        GIR_AddImm8, /*InsnID*/0, /*Imm*/0,
        GIR_MergeMemOperands, /*InsnID*/0, /*NumInsns*/1, /*MergeInsnID's*/0,
        GIR_ConstrainSelectedInstOperands, /*InsnID*/0,
        GIR_EraseFromParent, /*InsnID*/0,
        // GIR_Coverage, 3415,
        GIR_Done,
      // Label 1750: @114535
      GIM_Try, /*On fail goto*//*Label 1751*/ GIMT_Encode4(114597), // Rule ID 3414 //
        GIM_CheckFeatures, GIMT_Encode2(GIFBS_EnableFlatScratch_HasFlatScratchInsts),
        GIM_CheckMemoryAddressSpace, /*MI*/0, /*MMO*/0, /*NumAddrSpace*/1, /*AddrSpace*/5,
        GIM_CheckAtomicOrdering, /*MI*/0, /*Order*/(uint8_t)AtomicOrdering::NotAtomic,
        GIM_CheckRegBankForClass, /*MI*/0, /*Op*/0, /*RC*/GIMT_Encode2(AMDGPU::AV_32RegClassID),
        GIM_CheckPointerToAny, /*MI*/0, /*Op*/1, /*SizeInBits*/0,
        GIM_CheckComplexPattern, /*MI*/0, /*Op*/1, /*Renderer*/GIMT_Encode2(0), GIMT_Encode2(GICP_gi_flat_scratch_saddr),
        // (ld:{ *:[i16] } (ScratchSAddr:{ *:[iPTR] } SGPR_32:{ *:[i32] }:$saddr, i32:{ *:[i32] }:$offset))<<P:Predicate_unindexedload>><<P:Predicate_zextload>><<P:Predicate_zextloadi8>><<P:Predicate_zextloadi8_private>>  =>  (SCRATCH_LOAD_UBYTE_SADDR:{ *:[i16] } ?:{ *:[i32] }:$saddr, ?:{ *:[i32] }:$offset)
        GIR_BuildMI, /*InsnID*/0, /*Opcode*/GIMT_Encode2(AMDGPU::SCRATCH_LOAD_UBYTE_SADDR),
        GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/0, // DstI[vdst]
        GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/0, // saddr
        GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/1, // offset
        GIR_AddImm8, /*InsnID*/0, /*Imm*/0,
        GIR_MergeMemOperands, /*InsnID*/0, /*NumInsns*/1, /*MergeInsnID's*/0,
        GIR_ConstrainSelectedInstOperands, /*InsnID*/0,
        GIR_EraseFromParent, /*InsnID*/0,
        // GIR_Coverage, 3414,
        GIR_Done,
      // Label 1751: @114597
      GIM_Try, /*On fail goto*//*Label 1752*/ GIMT_Encode4(114659), // Rule ID 3413 //
        GIM_CheckFeatures, GIMT_Encode2(GIFBS_EnableFlatScratch_HasFlatScratchInsts),
        GIM_CheckMemoryAddressSpace, /*MI*/0, /*MMO*/0, /*NumAddrSpace*/1, /*AddrSpace*/5,
        GIM_CheckAtomicOrdering, /*MI*/0, /*Order*/(uint8_t)AtomicOrdering::NotAtomic,
        GIM_CheckRegBankForClass, /*MI*/0, /*Op*/0, /*RC*/GIMT_Encode2(AMDGPU::AV_32RegClassID),
        GIM_CheckPointerToAny, /*MI*/0, /*Op*/1, /*SizeInBits*/0,
        GIM_CheckComplexPattern, /*MI*/0, /*Op*/1, /*Renderer*/GIMT_Encode2(0), GIMT_Encode2(GICP_gi_flat_scratch_offset),
        // (ld:{ *:[i16] } (ScratchOffset:{ *:[iPTR] } VGPR_32:{ *:[i32] }:$vaddr, i32:{ *:[i32] }:$offset))<<P:Predicate_unindexedload>><<P:Predicate_zextload>><<P:Predicate_zextloadi8>><<P:Predicate_zextloadi8_private>>  =>  (SCRATCH_LOAD_UBYTE:{ *:[i16] } ?:{ *:[i32] }:$vaddr, ?:{ *:[i32] }:$offset)
        GIR_BuildMI, /*InsnID*/0, /*Opcode*/GIMT_Encode2(AMDGPU::SCRATCH_LOAD_UBYTE),
        GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/0, // DstI[vdst]
        GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/0, // vaddr
        GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/1, // offset
        GIR_AddImm8, /*InsnID*/0, /*Imm*/0,
        GIR_MergeMemOperands, /*InsnID*/0, /*NumInsns*/1, /*MergeInsnID's*/0,
        GIR_ConstrainSelectedInstOperands, /*InsnID*/0,
        GIR_EraseFromParent, /*InsnID*/0,
        // GIR_Coverage, 3413,
        GIR_Done,
      // Label 1752: @114659
      GIM_Try, /*On fail goto*//*Label 1753*/ GIMT_Encode4(114734), // Rule ID 5367 //
        GIM_CheckFeatures, GIMT_Encode2(GIFBS_DisableFlatScratch_HasUnrestrictedSOffset),
        GIM_CheckMemoryAddressSpace, /*MI*/0, /*MMO*/0, /*NumAddrSpace*/1, /*AddrSpace*/5,
        GIM_CheckAtomicOrdering, /*MI*/0, /*Order*/(uint8_t)AtomicOrdering::NotAtomic,
        GIM_CheckRegBankForClass, /*MI*/0, /*Op*/0, /*RC*/GIMT_Encode2(AMDGPU::AV_32RegClassID),
        GIM_CheckPointerToAny, /*MI*/0, /*Op*/1, /*SizeInBits*/0,
        GIM_CheckComplexPattern, /*MI*/0, /*Op*/1, /*Renderer*/GIMT_Encode2(0), GIMT_Encode2(GICP_gi_mubuf_scratch_offen),
        // (ld:{ *:[i16] } (MUBUFScratchOffen:{ *:[iPTR] } v4i32:{ *:[v4i32] }:$srsrc, i32:{ *:[i32] }:$vaddr, i32:{ *:[i32] }:$soffset, i32:{ *:[i32] }:$offset))<<P:Predicate_unindexedload>><<P:Predicate_zextload>><<P:Predicate_zextloadi8>><<P:Predicate_zextloadi8_private>>  =>  (BUFFER_LOAD_UBYTE_OFFEN:{ *:[i16] } ?:{ *:[i32] }:$vaddr, ?:{ *:[v4i32] }:$srsrc, ?:{ *:[i32] }:$soffset, ?:{ *:[i32] }:$offset, 0:{ *:[i32] }, 0:{ *:[i1] })
        GIR_BuildMI, /*InsnID*/0, /*Opcode*/GIMT_Encode2(AMDGPU::BUFFER_LOAD_UBYTE_OFFEN),
        GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/0, // DstI[vdata]
        GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/1, // vaddr
        GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/0, // srsrc
        GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/2, // soffset
        GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/3, // offset
        GIR_AddImm8, /*InsnID*/0, /*Imm*/0,
        GIR_AddImm8, /*InsnID*/0, /*Imm*/0,
        GIR_MergeMemOperands, /*InsnID*/0, /*NumInsns*/1, /*MergeInsnID's*/0,
        GIR_ConstrainSelectedInstOperands, /*InsnID*/0,
        GIR_EraseFromParent, /*InsnID*/0,
        // GIR_Coverage, 5367,
        GIR_Done,
      // Label 1753: @114734
      GIM_Try, /*On fail goto*//*Label 1754*/ GIMT_Encode4(114809), // Rule ID 5369 //
        GIM_CheckFeatures, GIMT_Encode2(GIFBS_DisableFlatScratch),
        GIM_CheckMemoryAddressSpace, /*MI*/0, /*MMO*/0, /*NumAddrSpace*/1, /*AddrSpace*/5,
        GIM_CheckAtomicOrdering, /*MI*/0, /*Order*/(uint8_t)AtomicOrdering::NotAtomic,
        GIM_CheckRegBankForClass, /*MI*/0, /*Op*/0, /*RC*/GIMT_Encode2(AMDGPU::AV_32RegClassID),
        GIM_CheckPointerToAny, /*MI*/0, /*Op*/1, /*SizeInBits*/0,
        GIM_CheckComplexPattern, /*MI*/0, /*Op*/1, /*Renderer*/GIMT_Encode2(0), GIMT_Encode2(GICP_gi_mubuf_scratch_offen),
        // (ld:{ *:[i16] } (MUBUFScratchOffen:{ *:[iPTR] } v4i32:{ *:[v4i32] }:$srsrc, i32:{ *:[i32] }:$vaddr, i32:{ *:[i32] }:$soffset, i32:{ *:[i32] }:$offset))<<P:Predicate_unindexedload>><<P:Predicate_zextload>><<P:Predicate_zextloadi8>><<P:Predicate_zextloadi8_private>>  =>  (BUFFER_LOAD_UBYTE_VBUFFER_OFFEN:{ *:[i16] } ?:{ *:[i32] }:$vaddr, ?:{ *:[v4i32] }:$srsrc, ?:{ *:[i32] }:$soffset, ?:{ *:[i32] }:$offset, 0:{ *:[i32] }, 0:{ *:[i1] })
        GIR_BuildMI, /*InsnID*/0, /*Opcode*/GIMT_Encode2(AMDGPU::BUFFER_LOAD_UBYTE_VBUFFER_OFFEN),
        GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/0, // DstI[vdata]
        GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/1, // vaddr
        GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/0, // srsrc
        GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/2, // soffset
        GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/3, // offset
        GIR_AddImm8, /*InsnID*/0, /*Imm*/0,
        GIR_AddImm8, /*InsnID*/0, /*Imm*/0,
        GIR_MergeMemOperands, /*InsnID*/0, /*NumInsns*/1, /*MergeInsnID's*/0,
        GIR_ConstrainSelectedInstOperands, /*InsnID*/0,
        GIR_EraseFromParent, /*InsnID*/0,
        // GIR_Coverage, 5369,
        GIR_Done,
      // Label 1754: @114809
      GIM_Try, /*On fail goto*//*Label 1755*/ GIMT_Encode4(114880), // Rule ID 5335 //
        GIM_CheckFeatures, GIMT_Encode2(GIFBS_Has16BitInsts_HasUnrestrictedSOffset),
        GIM_CheckMemoryAddressSpace, /*MI*/0, /*MMO*/0, /*NumAddrSpace*/2, /*AddrSpace*/4, /*AddrSpace*/6,
        GIM_CheckAtomicOrdering, /*MI*/0, /*Order*/(uint8_t)AtomicOrdering::NotAtomic,
        GIM_CheckRegBankForClass, /*MI*/0, /*Op*/0, /*RC*/GIMT_Encode2(AMDGPU::AV_32RegClassID),
        GIM_CheckPointerToAny, /*MI*/0, /*Op*/1, /*SizeInBits*/0,
        GIM_CheckComplexPattern, /*MI*/0, /*Op*/1, /*Renderer*/GIMT_Encode2(0), GIMT_Encode2(GICP_gi_mubuf_offset),
        // (ld:{ *:[i16] } (MUBUFOffset:{ *:[iPTR] } v4i32:{ *:[v4i32] }:$srsrc, i32:{ *:[i32] }:$soffset, i32:{ *:[i32] }:$offset))<<P:Predicate_unindexedload>><<P:Predicate_zextload>><<P:Predicate_zextloadi8>><<P:Predicate_zextloadi8_constant>>  =>  (BUFFER_LOAD_UBYTE_OFFSET:{ *:[i16] } ?:{ *:[v4i32] }:$srsrc, ?:{ *:[i32] }:$soffset, ?:{ *:[i32] }:$offset)
        GIR_BuildMI, /*InsnID*/0, /*Opcode*/GIMT_Encode2(AMDGPU::BUFFER_LOAD_UBYTE_OFFSET),
        GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/0, // DstI[vdata]
        GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/0, // srsrc
        GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/1, // soffset
        GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/2, // offset
        GIR_AddImm8, /*InsnID*/0, /*Imm*/0,
        GIR_AddImm8, /*InsnID*/0, /*Imm*/0,
        GIR_MergeMemOperands, /*InsnID*/0, /*NumInsns*/1, /*MergeInsnID's*/0,
        GIR_ConstrainSelectedInstOperands, /*InsnID*/0,
        GIR_EraseFromParent, /*InsnID*/0,
        // GIR_Coverage, 5335,
        GIR_Done,
      // Label 1755: @114880
      GIM_Try, /*On fail goto*//*Label 1756*/ GIMT_Encode4(114951), // Rule ID 5336 //
        GIM_CheckFeatures, GIMT_Encode2(GIFBS_Has16BitInsts),
        GIM_CheckMemoryAddressSpace, /*MI*/0, /*MMO*/0, /*NumAddrSpace*/2, /*AddrSpace*/4, /*AddrSpace*/6,
        GIM_CheckAtomicOrdering, /*MI*/0, /*Order*/(uint8_t)AtomicOrdering::NotAtomic,
        GIM_CheckRegBankForClass, /*MI*/0, /*Op*/0, /*RC*/GIMT_Encode2(AMDGPU::AV_32RegClassID),
        GIM_CheckPointerToAny, /*MI*/0, /*Op*/1, /*SizeInBits*/0,
        GIM_CheckComplexPattern, /*MI*/0, /*Op*/1, /*Renderer*/GIMT_Encode2(0), GIMT_Encode2(GICP_gi_mubuf_offset),
        // (ld:{ *:[i16] } (MUBUFOffset:{ *:[iPTR] } v4i32:{ *:[v4i32] }:$srsrc, i32:{ *:[i32] }:$soffset, i32:{ *:[i32] }:$offset))<<P:Predicate_unindexedload>><<P:Predicate_zextload>><<P:Predicate_zextloadi8>><<P:Predicate_zextloadi8_constant>>  =>  (BUFFER_LOAD_UBYTE_VBUFFER_OFFSET:{ *:[i16] } ?:{ *:[v4i32] }:$srsrc, ?:{ *:[i32] }:$soffset, ?:{ *:[i32] }:$offset)
        GIR_BuildMI, /*InsnID*/0, /*Opcode*/GIMT_Encode2(AMDGPU::BUFFER_LOAD_UBYTE_VBUFFER_OFFSET),
        GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/0, // DstI[vdata]
        GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/0, // srsrc
        GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/1, // soffset
        GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/2, // offset
        GIR_AddImm8, /*InsnID*/0, /*Imm*/0,
        GIR_AddImm8, /*InsnID*/0, /*Imm*/0,
        GIR_MergeMemOperands, /*InsnID*/0, /*NumInsns*/1, /*MergeInsnID's*/0,
        GIR_ConstrainSelectedInstOperands, /*InsnID*/0,
        GIR_EraseFromParent, /*InsnID*/0,
        // GIR_Coverage, 5336,
        GIR_Done,
      // Label 1756: @114951
      GIM_Try, /*On fail goto*//*Label 1757*/ GIMT_Encode4(115023), // Rule ID 5341 //
        GIM_CheckFeatures, GIMT_Encode2(GIFBS_Has16BitInsts_HasUnrestrictedSOffset),
        GIM_CheckMemoryAddressSpace, /*MI*/0, /*MMO*/0, /*NumAddrSpace*/3, /*AddrSpace*/1, /*AddrSpace*/4, /*AddrSpace*/6,
        GIM_CheckAtomicOrdering, /*MI*/0, /*Order*/(uint8_t)AtomicOrdering::NotAtomic,
        GIM_CheckRegBankForClass, /*MI*/0, /*Op*/0, /*RC*/GIMT_Encode2(AMDGPU::AV_32RegClassID),
        GIM_CheckPointerToAny, /*MI*/0, /*Op*/1, /*SizeInBits*/0,
        GIM_CheckComplexPattern, /*MI*/0, /*Op*/1, /*Renderer*/GIMT_Encode2(0), GIMT_Encode2(GICP_gi_mubuf_offset),
        // (ld:{ *:[i16] } (MUBUFOffset:{ *:[iPTR] } v4i32:{ *:[v4i32] }:$srsrc, i32:{ *:[i32] }:$soffset, i32:{ *:[i32] }:$offset))<<P:Predicate_unindexedload>><<P:Predicate_zextload>><<P:Predicate_zextloadi8>><<P:Predicate_zextloadi8_global>>  =>  (BUFFER_LOAD_UBYTE_OFFSET:{ *:[i16] } ?:{ *:[v4i32] }:$srsrc, ?:{ *:[i32] }:$soffset, ?:{ *:[i32] }:$offset)
        GIR_BuildMI, /*InsnID*/0, /*Opcode*/GIMT_Encode2(AMDGPU::BUFFER_LOAD_UBYTE_OFFSET),
        GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/0, // DstI[vdata]
        GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/0, // srsrc
        GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/1, // soffset
        GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/2, // offset
        GIR_AddImm8, /*InsnID*/0, /*Imm*/0,
        GIR_AddImm8, /*InsnID*/0, /*Imm*/0,
        GIR_MergeMemOperands, /*InsnID*/0, /*NumInsns*/1, /*MergeInsnID's*/0,
        GIR_ConstrainSelectedInstOperands, /*InsnID*/0,
        GIR_EraseFromParent, /*InsnID*/0,
        // GIR_Coverage, 5341,
        GIR_Done,
      // Label 1757: @115023
      GIM_Try, /*On fail goto*//*Label 1758*/ GIMT_Encode4(115095), // Rule ID 5342 //
        GIM_CheckFeatures, GIMT_Encode2(GIFBS_Has16BitInsts),
        GIM_CheckMemoryAddressSpace, /*MI*/0, /*MMO*/0, /*NumAddrSpace*/3, /*AddrSpace*/1, /*AddrSpace*/4, /*AddrSpace*/6,
        GIM_CheckAtomicOrdering, /*MI*/0, /*Order*/(uint8_t)AtomicOrdering::NotAtomic,
        GIM_CheckRegBankForClass, /*MI*/0, /*Op*/0, /*RC*/GIMT_Encode2(AMDGPU::AV_32RegClassID),
        GIM_CheckPointerToAny, /*MI*/0, /*Op*/1, /*SizeInBits*/0,
        GIM_CheckComplexPattern, /*MI*/0, /*Op*/1, /*Renderer*/GIMT_Encode2(0), GIMT_Encode2(GICP_gi_mubuf_offset),
        // (ld:{ *:[i16] } (MUBUFOffset:{ *:[iPTR] } v4i32:{ *:[v4i32] }:$srsrc, i32:{ *:[i32] }:$soffset, i32:{ *:[i32] }:$offset))<<P:Predicate_unindexedload>><<P:Predicate_zextload>><<P:Predicate_zextloadi8>><<P:Predicate_zextloadi8_global>>  =>  (BUFFER_LOAD_UBYTE_VBUFFER_OFFSET:{ *:[i16] } ?:{ *:[v4i32] }:$srsrc, ?:{ *:[i32] }:$soffset, ?:{ *:[i32] }:$offset)
        GIR_BuildMI, /*InsnID*/0, /*Opcode*/GIMT_Encode2(AMDGPU::BUFFER_LOAD_UBYTE_VBUFFER_OFFSET),
        GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/0, // DstI[vdata]
        GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/0, // srsrc
        GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/1, // soffset
        GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/2, // offset
        GIR_AddImm8, /*InsnID*/0, /*Imm*/0,
        GIR_AddImm8, /*InsnID*/0, /*Imm*/0,
        GIR_MergeMemOperands, /*InsnID*/0, /*NumInsns*/1, /*MergeInsnID's*/0,
        GIR_ConstrainSelectedInstOperands, /*InsnID*/0,
        GIR_EraseFromParent, /*InsnID*/0,
        // GIR_Coverage, 5342,
        GIR_Done,
      // Label 1758: @115095
      GIM_Try, /*On fail goto*//*Label 1759*/ GIMT_Encode4(115157), // Rule ID 6577 //
        GIM_CheckFeatures, GIMT_Encode2(GIFBS_LDSRequiresM0Init),
        GIM_CheckMemoryAddressSpace, /*MI*/0, /*MMO*/0, /*NumAddrSpace*/1, /*AddrSpace*/3,
        GIM_CheckAtomicOrdering, /*MI*/0, /*Order*/(uint8_t)AtomicOrdering::NotAtomic,
        GIM_CheckRegBankForClass, /*MI*/0, /*Op*/0, /*RC*/GIMT_Encode2(AMDGPU::AV_32RegClassID),
        GIM_CheckPointerToAny, /*MI*/0, /*Op*/1, /*SizeInBits*/0,
        GIM_CheckComplexPattern, /*MI*/0, /*Op*/1, /*Renderer*/GIMT_Encode2(0), GIMT_Encode2(GICP_gi_ds_1addr_1offset),
        // (AMDGPUld_glue:{ *:[i16] } (DS1Addr1Offset:{ *:[iPTR] } i32:{ *:[i32] }:$ptr, i32:{ *:[i32] }:$offset))<<P:Predicate_unindexedload_glue>><<P:Predicate_zextload_glue>><<P:Predicate_zextloadi8_glue>><<P:Predicate_zextloadi8_local_m0>>  =>  (DS_READ_U8:{ *:[i16] } ?:{ *:[i32] }:$ptr, offset:{ *:[i32] }:$offset, 0:{ *:[i1] })
        GIR_BuildMI, /*InsnID*/0, /*Opcode*/GIMT_Encode2(AMDGPU::DS_READ_U8),
        GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/0, // DstI[vdst]
        GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/0, // ptr
        GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/1, // offset
        GIR_AddImm8, /*InsnID*/0, /*Imm*/0,
        GIR_MergeMemOperands, /*InsnID*/0, /*NumInsns*/1, /*MergeInsnID's*/0,
        GIR_ConstrainSelectedInstOperands, /*InsnID*/0,
        GIR_EraseFromParent, /*InsnID*/0,
        // GIR_Coverage, 6577,
        GIR_Done,
      // Label 1759: @115157
      GIM_Try, /*On fail goto*//*Label 1760*/ GIMT_Encode4(115219), // Rule ID 6578 //
        GIM_CheckFeatures, GIMT_Encode2(GIFBS_NotLDSRequiresM0Init),
        GIM_CheckMemoryAddressSpace, /*MI*/0, /*MMO*/0, /*NumAddrSpace*/1, /*AddrSpace*/3,
        GIM_CheckAtomicOrdering, /*MI*/0, /*Order*/(uint8_t)AtomicOrdering::NotAtomic,
        GIM_CheckRegBankForClass, /*MI*/0, /*Op*/0, /*RC*/GIMT_Encode2(AMDGPU::AV_32RegClassID),
        GIM_CheckPointerToAny, /*MI*/0, /*Op*/1, /*SizeInBits*/0,
        GIM_CheckComplexPattern, /*MI*/0, /*Op*/1, /*Renderer*/GIMT_Encode2(0), GIMT_Encode2(GICP_gi_ds_1addr_1offset),
        // (ld:{ *:[i16] } (DS1Addr1Offset:{ *:[iPTR] } i32:{ *:[i32] }:$ptr, i32:{ *:[i32] }:$offset))<<P:Predicate_unindexedload>><<P:Predicate_zextload>><<P:Predicate_zextloadi8>><<P:Predicate_zextloadi8_local>>  =>  (DS_READ_U8_gfx9:{ *:[i16] } ?:{ *:[i32] }:$ptr, offset:{ *:[i32] }:$offset, 0:{ *:[i1] })
        GIR_BuildMI, /*InsnID*/0, /*Opcode*/GIMT_Encode2(AMDGPU::DS_READ_U8_gfx9),
        GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/0, // DstI[vdst]
        GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/0, // ptr
        GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/1, // offset
        GIR_AddImm8, /*InsnID*/0, /*Imm*/0,
        GIR_MergeMemOperands, /*InsnID*/0, /*NumInsns*/1, /*MergeInsnID's*/0,
        GIR_ConstrainSelectedInstOperands, /*InsnID*/0,
        GIR_EraseFromParent, /*InsnID*/0,
        // GIR_Coverage, 6578,
        GIR_Done,
      // Label 1760: @115219
      GIM_Try, /*On fail goto*//*Label 1761*/ GIMT_Encode4(115288), // Rule ID 2983 //
        GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasFlatGlobalInsts),
        GIM_CheckMemoryAddressSpace, /*MI*/0, /*MMO*/0, /*NumAddrSpace*/3, /*AddrSpace*/1, /*AddrSpace*/4, /*AddrSpace*/6,
        GIM_CheckAtomicOrdering, /*MI*/0, /*Order*/(uint8_t)AtomicOrdering::NotAtomic,
        GIM_CheckRegBankForClass, /*MI*/0, /*Op*/0, /*RC*/GIMT_Encode2(AMDGPU::AV_32RegClassID),
        GIM_CheckPointerToAny, /*MI*/0, /*Op*/1, /*SizeInBits*/0,
        GIM_CheckComplexPattern, /*MI*/0, /*Op*/1, /*Renderer*/GIMT_Encode2(0), GIMT_Encode2(GICP_gi_global_saddr),
        // (ld:{ *:[i16] } (GlobalSAddr:{ *:[iPTR] } SReg_64:{ *:[i64] }:$saddr, VGPR_32:{ *:[i32] }:$voffset, i32:{ *:[i32] }:$offset))<<P:Predicate_unindexedload>><<P:Predicate_zextload>><<P:Predicate_zextloadi8>><<P:Predicate_zextloadi8_global>>  =>  (GLOBAL_LOAD_UBYTE_SADDR:{ *:[i16] } ?:{ *:[i64] }:$saddr, ?:{ *:[i32] }:$voffset, ?:{ *:[i32] }:$offset, 0:{ *:[i32] })
        GIR_BuildMI, /*InsnID*/0, /*Opcode*/GIMT_Encode2(AMDGPU::GLOBAL_LOAD_UBYTE_SADDR),
        GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/0, // DstI[vdst]
        GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/0, // saddr
        GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/1, // voffset
        GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/2, // offset
        GIR_AddImm8, /*InsnID*/0, /*Imm*/0,
        GIR_MergeMemOperands, /*InsnID*/0, /*NumInsns*/1, /*MergeInsnID's*/0,
        GIR_ConstrainSelectedInstOperands, /*InsnID*/0,
        GIR_EraseFromParent, /*InsnID*/0,
        // GIR_Coverage, 2983,
        GIR_Done,
      // Label 1761: @115288
      GIM_Try, /*On fail goto*//*Label 1762*/ GIMT_Encode4(115352), // Rule ID 2982 //
        GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasFlatGlobalInsts),
        GIM_CheckMemoryAddressSpace, /*MI*/0, /*MMO*/0, /*NumAddrSpace*/3, /*AddrSpace*/1, /*AddrSpace*/4, /*AddrSpace*/6,
        GIM_CheckAtomicOrdering, /*MI*/0, /*Order*/(uint8_t)AtomicOrdering::NotAtomic,
        GIM_CheckRegBankForClass, /*MI*/0, /*Op*/0, /*RC*/GIMT_Encode2(AMDGPU::AV_32RegClassID),
        GIM_CheckPointerToAny, /*MI*/0, /*Op*/1, /*SizeInBits*/0,
        GIM_CheckComplexPattern, /*MI*/0, /*Op*/1, /*Renderer*/GIMT_Encode2(0), GIMT_Encode2(GICP_gi_global_offset),
        // (ld:{ *:[i16] } (GlobalOffset:{ *:[iPTR] } VReg_64:{ *:[i64] }:$vaddr, i32:{ *:[i32] }:$offset))<<P:Predicate_unindexedload>><<P:Predicate_zextload>><<P:Predicate_zextloadi8>><<P:Predicate_zextloadi8_global>>  =>  (GLOBAL_LOAD_UBYTE:{ *:[i16] } ?:{ *:[i64] }:$vaddr, ?:{ *:[i32] }:$offset)
        GIR_BuildMI, /*InsnID*/0, /*Opcode*/GIMT_Encode2(AMDGPU::GLOBAL_LOAD_UBYTE),
        GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/0, // DstI[vdst]
        GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/0, // vaddr
        GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/1, // offset
        GIR_AddImm8, /*InsnID*/0, /*Imm*/0,
        GIR_MergeMemOperands, /*InsnID*/0, /*NumInsns*/1, /*MergeInsnID's*/0,
        GIR_ConstrainSelectedInstOperands, /*InsnID*/0,
        GIR_EraseFromParent, /*InsnID*/0,
        // GIR_Coverage, 2982,
        GIR_Done,
      // Label 1762: @115352
      GIM_Try, /*On fail goto*//*Label 1763*/ GIMT_Encode4(115417), // Rule ID 2759 //
        GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasFlatAddressSpace),
        GIM_CheckMemoryAddressSpace, /*MI*/0, /*MMO*/0, /*NumAddrSpace*/4, /*AddrSpace*/0, /*AddrSpace*/1, /*AddrSpace*/4, /*AddrSpace*/6,
        GIM_CheckAtomicOrdering, /*MI*/0, /*Order*/(uint8_t)AtomicOrdering::NotAtomic,
        GIM_CheckRegBankForClass, /*MI*/0, /*Op*/0, /*RC*/GIMT_Encode2(AMDGPU::AV_32RegClassID),
        GIM_CheckPointerToAny, /*MI*/0, /*Op*/1, /*SizeInBits*/0,
        GIM_CheckComplexPattern, /*MI*/0, /*Op*/1, /*Renderer*/GIMT_Encode2(0), GIMT_Encode2(GICP_gi_flat_offset),
        // (ld:{ *:[i16] } (FlatOffset:{ *:[iPTR] } i64:{ *:[i64] }:$vaddr, i32:{ *:[i32] }:$offset))<<P:Predicate_unindexedload>><<P:Predicate_zextload>><<P:Predicate_zextloadi8>><<P:Predicate_zextloadi8_flat>>  =>  (FLAT_LOAD_UBYTE:{ *:[i16] } ?:{ *:[i64] }:$vaddr, ?:{ *:[i32] }:$offset)
        GIR_BuildMI, /*InsnID*/0, /*Opcode*/GIMT_Encode2(AMDGPU::FLAT_LOAD_UBYTE),
        GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/0, // DstI[vdst]
        GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/0, // vaddr
        GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/1, // offset
        GIR_AddImm8, /*InsnID*/0, /*Imm*/0,
        GIR_MergeMemOperands, /*InsnID*/0, /*NumInsns*/1, /*MergeInsnID's*/0,
        GIR_ConstrainSelectedInstOperands, /*InsnID*/0,
        GIR_EraseFromParent, /*InsnID*/0,
        // GIR_Coverage, 2759,
        GIR_Done,
      // Label 1763: @115417
      GIM_Reject,
    // Label 1747: @115418
    GIM_Reject,
    // Label 1745: @115419
    GIM_Try, /*On fail goto*//*Label 1764*/ GIMT_Encode4(115492), // Rule ID 2425 //
      GIM_CheckFeatures, GIMT_Encode2(GIFBS_isGFX12Plus),
      GIM_CheckMemorySizeEqualTo, /*MI*/0, /*MMO*/0, /*Size*/GIMT_Encode4(1),
      GIM_CheckAtomicOrdering, /*MI*/0, /*Order*/(uint8_t)AtomicOrdering::NotAtomic,
      GIM_CheckRegBankForClass, /*MI*/0, /*Op*/0, /*RC*/GIMT_Encode2(AMDGPU::SReg_32_XM0_XEXECRegClassID),
      GIM_CheckPointerToAny, /*MI*/0, /*Op*/1, /*SizeInBits*/0,
      GIM_CheckCxxInsnPredicate, /*MI*/0, /*FnId*/GIMT_Encode2(GICXXPred_MI_Predicate_smrd_zextloadi8),
      GIM_CheckComplexPattern, /*MI*/0, /*Op*/1, /*Renderer*/GIMT_Encode2(0), GIMT_Encode2(GICP_gi_smrd_sgpr_imm),
      // (ld:{ *:[i32] } (SMRDSgprImm:{ *:[iPTR] } i64:{ *:[i64] }:$sbase, i32:{ *:[i32] }:$soffset, i32:{ *:[i32] }:$offset))<<P:Predicate_unindexedload>><<P:Predicate_zextload>><<P:Predicate_zextloadi8>><<P:Predicate_smrd_zextloadi8>>  =>  (S_LOAD_U8_SGPR_IMM:{ *:[i32] } ?:{ *:[i64] }:$sbase, ?:{ *:[i32] }:$soffset, ?:{ *:[i32] }:$offset, 0:{ *:[i32] })
      GIR_BuildMI, /*InsnID*/0, /*Opcode*/GIMT_Encode2(AMDGPU::S_LOAD_U8_SGPR_IMM),
      GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/0, // DstI[sdst]
      GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/0, // sbase
      GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/1, // soffset
      GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/2, // offset
      GIR_AddImm8, /*InsnID*/0, /*Imm*/0,
      GIR_MergeMemOperands, /*InsnID*/0, /*NumInsns*/1, /*MergeInsnID's*/0,
      GIR_ConstrainSelectedInstOperands, /*InsnID*/0,
      GIR_EraseFromParent, /*InsnID*/0,
      // GIR_Coverage, 2425,
      GIR_Done,
    // Label 1764: @115492
    GIM_Try, /*On fail goto*//*Label 1765*/ GIMT_Encode4(115565), // Rule ID 2437 //
      GIM_CheckFeatures, GIMT_Encode2(GIFBS_isGFX12Plus),
      GIM_CheckMemorySizeEqualTo, /*MI*/0, /*MMO*/0, /*Size*/GIMT_Encode4(2),
      GIM_CheckAtomicOrdering, /*MI*/0, /*Order*/(uint8_t)AtomicOrdering::NotAtomic,
      GIM_CheckRegBankForClass, /*MI*/0, /*Op*/0, /*RC*/GIMT_Encode2(AMDGPU::SReg_32_XM0_XEXECRegClassID),
      GIM_CheckPointerToAny, /*MI*/0, /*Op*/1, /*SizeInBits*/0,
      GIM_CheckCxxInsnPredicate, /*MI*/0, /*FnId*/GIMT_Encode2(GICXXPred_MI_Predicate_smrd_zextloadi16),
      GIM_CheckComplexPattern, /*MI*/0, /*Op*/1, /*Renderer*/GIMT_Encode2(0), GIMT_Encode2(GICP_gi_smrd_sgpr_imm),
      // (ld:{ *:[i32] } (SMRDSgprImm:{ *:[iPTR] } i64:{ *:[i64] }:$sbase, i32:{ *:[i32] }:$soffset, i32:{ *:[i32] }:$offset))<<P:Predicate_unindexedload>><<P:Predicate_zextload>><<P:Predicate_zextloadi16>><<P:Predicate_smrd_zextloadi16>>  =>  (S_LOAD_U16_SGPR_IMM:{ *:[i32] } ?:{ *:[i64] }:$sbase, ?:{ *:[i32] }:$soffset, ?:{ *:[i32] }:$offset, 0:{ *:[i32] })
      GIR_BuildMI, /*InsnID*/0, /*Opcode*/GIMT_Encode2(AMDGPU::S_LOAD_U16_SGPR_IMM),
      GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/0, // DstI[sdst]
      GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/0, // sbase
      GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/1, // soffset
      GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/2, // offset
      GIR_AddImm8, /*InsnID*/0, /*Imm*/0,
      GIR_MergeMemOperands, /*InsnID*/0, /*NumInsns*/1, /*MergeInsnID's*/0,
      GIR_ConstrainSelectedInstOperands, /*InsnID*/0,
      GIR_EraseFromParent, /*InsnID*/0,
      // GIR_Coverage, 2437,
      GIR_Done,
    // Label 1765: @115565
    GIM_Try, /*On fail goto*//*Label 1766*/ GIMT_Encode4(115633), // Rule ID 2423 //
      GIM_CheckFeatures, GIMT_Encode2(GIFBS_isGFX12Plus),
      GIM_CheckMemorySizeEqualTo, /*MI*/0, /*MMO*/0, /*Size*/GIMT_Encode4(1),
      GIM_CheckAtomicOrdering, /*MI*/0, /*Order*/(uint8_t)AtomicOrdering::NotAtomic,
      GIM_CheckRegBankForClass, /*MI*/0, /*Op*/0, /*RC*/GIMT_Encode2(AMDGPU::SReg_32_XM0_XEXECRegClassID),
      GIM_CheckPointerToAny, /*MI*/0, /*Op*/1, /*SizeInBits*/0,
      GIM_CheckCxxInsnPredicate, /*MI*/0, /*FnId*/GIMT_Encode2(GICXXPred_MI_Predicate_smrd_zextloadi8),
      GIM_CheckComplexPattern, /*MI*/0, /*Op*/1, /*Renderer*/GIMT_Encode2(0), GIMT_Encode2(GICP_gi_smrd_imm),
      // (ld:{ *:[i32] } (SMRDImm:{ *:[iPTR] } i64:{ *:[i64] }:$sbase, i32:{ *:[i32] }:$offset))<<P:Predicate_unindexedload>><<P:Predicate_zextload>><<P:Predicate_zextloadi8>><<P:Predicate_smrd_zextloadi8>>  =>  (S_LOAD_U8_IMM:{ *:[i32] } ?:{ *:[i64] }:$sbase, ?:{ *:[i32] }:$offset, 0:{ *:[i32] })
      GIR_BuildMI, /*InsnID*/0, /*Opcode*/GIMT_Encode2(AMDGPU::S_LOAD_U8_IMM),
      GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/0, // DstI[sdst]
      GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/0, // sbase
      GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/1, // offset
      GIR_AddImm8, /*InsnID*/0, /*Imm*/0,
      GIR_MergeMemOperands, /*InsnID*/0, /*NumInsns*/1, /*MergeInsnID's*/0,
      GIR_ConstrainSelectedInstOperands, /*InsnID*/0,
      GIR_EraseFromParent, /*InsnID*/0,
      // GIR_Coverage, 2423,
      GIR_Done,
    // Label 1766: @115633
    GIM_Try, /*On fail goto*//*Label 1767*/ GIMT_Encode4(115704), // Rule ID 2424 //
      GIM_CheckFeatures, GIMT_Encode2(GIFBS_isGFX12Plus),
      GIM_CheckMemorySizeEqualTo, /*MI*/0, /*MMO*/0, /*Size*/GIMT_Encode4(1),
      GIM_CheckAtomicOrdering, /*MI*/0, /*Order*/(uint8_t)AtomicOrdering::NotAtomic,
      GIM_CheckRegBankForClass, /*MI*/0, /*Op*/0, /*RC*/GIMT_Encode2(AMDGPU::SReg_32_XM0_XEXECRegClassID),
      GIM_CheckPointerToAny, /*MI*/0, /*Op*/1, /*SizeInBits*/0,
      GIM_CheckCxxInsnPredicate, /*MI*/0, /*FnId*/GIMT_Encode2(GICXXPred_MI_Predicate_smrd_zextloadi8),
      GIM_CheckComplexPattern, /*MI*/0, /*Op*/1, /*Renderer*/GIMT_Encode2(0), GIMT_Encode2(GICP_gi_smrd_sgpr),
      // (ld:{ *:[i32] } (SMRDSgpr:{ *:[iPTR] } i64:{ *:[i64] }:$sbase, i32:{ *:[i32] }:$soffset))<<P:Predicate_unindexedload>><<P:Predicate_zextload>><<P:Predicate_zextloadi8>><<P:Predicate_smrd_zextloadi8>>  =>  (S_LOAD_U8_SGPR_IMM:{ *:[i32] } ?:{ *:[i64] }:$sbase, ?:{ *:[i32] }:$soffset, 0:{ *:[i32] }, 0:{ *:[i32] })
      GIR_BuildMI, /*InsnID*/0, /*Opcode*/GIMT_Encode2(AMDGPU::S_LOAD_U8_SGPR_IMM),
      GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/0, // DstI[sdst]
      GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/0, // sbase
      GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/1, // soffset
      GIR_AddImm8, /*InsnID*/0, /*Imm*/0,
      GIR_AddImm8, /*InsnID*/0, /*Imm*/0,
      GIR_MergeMemOperands, /*InsnID*/0, /*NumInsns*/1, /*MergeInsnID's*/0,
      GIR_ConstrainSelectedInstOperands, /*InsnID*/0,
      GIR_EraseFromParent, /*InsnID*/0,
      // GIR_Coverage, 2424,
      GIR_Done,
    // Label 1767: @115704
    GIM_Try, /*On fail goto*//*Label 1768*/ GIMT_Encode4(115772), // Rule ID 2435 //
      GIM_CheckFeatures, GIMT_Encode2(GIFBS_isGFX12Plus),
      GIM_CheckMemorySizeEqualTo, /*MI*/0, /*MMO*/0, /*Size*/GIMT_Encode4(2),
      GIM_CheckAtomicOrdering, /*MI*/0, /*Order*/(uint8_t)AtomicOrdering::NotAtomic,
      GIM_CheckRegBankForClass, /*MI*/0, /*Op*/0, /*RC*/GIMT_Encode2(AMDGPU::SReg_32_XM0_XEXECRegClassID),
      GIM_CheckPointerToAny, /*MI*/0, /*Op*/1, /*SizeInBits*/0,
      GIM_CheckCxxInsnPredicate, /*MI*/0, /*FnId*/GIMT_Encode2(GICXXPred_MI_Predicate_smrd_zextloadi16),
      GIM_CheckComplexPattern, /*MI*/0, /*Op*/1, /*Renderer*/GIMT_Encode2(0), GIMT_Encode2(GICP_gi_smrd_imm),
      // (ld:{ *:[i32] } (SMRDImm:{ *:[iPTR] } i64:{ *:[i64] }:$sbase, i32:{ *:[i32] }:$offset))<<P:Predicate_unindexedload>><<P:Predicate_zextload>><<P:Predicate_zextloadi16>><<P:Predicate_smrd_zextloadi16>>  =>  (S_LOAD_U16_IMM:{ *:[i32] } ?:{ *:[i64] }:$sbase, ?:{ *:[i32] }:$offset, 0:{ *:[i32] })
      GIR_BuildMI, /*InsnID*/0, /*Opcode*/GIMT_Encode2(AMDGPU::S_LOAD_U16_IMM),
      GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/0, // DstI[sdst]
      GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/0, // sbase
      GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/1, // offset
      GIR_AddImm8, /*InsnID*/0, /*Imm*/0,
      GIR_MergeMemOperands, /*InsnID*/0, /*NumInsns*/1, /*MergeInsnID's*/0,
      GIR_ConstrainSelectedInstOperands, /*InsnID*/0,
      GIR_EraseFromParent, /*InsnID*/0,
      // GIR_Coverage, 2435,
      GIR_Done,
    // Label 1768: @115772
    GIM_Try, /*On fail goto*//*Label 1769*/ GIMT_Encode4(115843), // Rule ID 2436 //
      GIM_CheckFeatures, GIMT_Encode2(GIFBS_isGFX12Plus),
      GIM_CheckMemorySizeEqualTo, /*MI*/0, /*MMO*/0, /*Size*/GIMT_Encode4(2),
      GIM_CheckAtomicOrdering, /*MI*/0, /*Order*/(uint8_t)AtomicOrdering::NotAtomic,
      GIM_CheckRegBankForClass, /*MI*/0, /*Op*/0, /*RC*/GIMT_Encode2(AMDGPU::SReg_32_XM0_XEXECRegClassID),
      GIM_CheckPointerToAny, /*MI*/0, /*Op*/1, /*SizeInBits*/0,
      GIM_CheckCxxInsnPredicate, /*MI*/0, /*FnId*/GIMT_Encode2(GICXXPred_MI_Predicate_smrd_zextloadi16),
      GIM_CheckComplexPattern, /*MI*/0, /*Op*/1, /*Renderer*/GIMT_Encode2(0), GIMT_Encode2(GICP_gi_smrd_sgpr),
      // (ld:{ *:[i32] } (SMRDSgpr:{ *:[iPTR] } i64:{ *:[i64] }:$sbase, i32:{ *:[i32] }:$soffset))<<P:Predicate_unindexedload>><<P:Predicate_zextload>><<P:Predicate_zextloadi16>><<P:Predicate_smrd_zextloadi16>>  =>  (S_LOAD_U16_SGPR_IMM:{ *:[i32] } ?:{ *:[i64] }:$sbase, ?:{ *:[i32] }:$soffset, 0:{ *:[i32] }, 0:{ *:[i32] })
      GIR_BuildMI, /*InsnID*/0, /*Opcode*/GIMT_Encode2(AMDGPU::S_LOAD_U16_SGPR_IMM),
      GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/0, // DstI[sdst]
      GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/0, // sbase
      GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/1, // soffset
      GIR_AddImm8, /*InsnID*/0, /*Imm*/0,
      GIR_AddImm8, /*InsnID*/0, /*Imm*/0,
      GIR_MergeMemOperands, /*InsnID*/0, /*NumInsns*/1, /*MergeInsnID's*/0,
      GIR_ConstrainSelectedInstOperands, /*InsnID*/0,
      GIR_EraseFromParent, /*InsnID*/0,
      // GIR_Coverage, 2436,
      GIR_Done,
    // Label 1769: @115843
    GIM_Try, /*On fail goto*//*Label 1770*/ GIMT_Encode4(115906), // Rule ID 2426 //
      GIM_CheckFeatures, GIMT_Encode2(GIFBS_isGFX12Plus),
      GIM_CheckMemorySizeEqualTo, /*MI*/0, /*MMO*/0, /*Size*/GIMT_Encode4(1),
      GIM_CheckAtomicOrdering, /*MI*/0, /*Order*/(uint8_t)AtomicOrdering::NotAtomic,
      GIM_CheckRegBankForClass, /*MI*/0, /*Op*/0, /*RC*/GIMT_Encode2(AMDGPU::SReg_32_XM0_XEXECRegClassID),
      // MIs[0] sbase
      GIM_CheckPointerToAny, /*MI*/0, /*Op*/1, /*SizeInBits*/64,
      GIM_CheckRegBankForClass, /*MI*/0, /*Op*/1, /*RC*/GIMT_Encode2(AMDGPU::SReg_64RegClassID),
      GIM_CheckCxxInsnPredicate, /*MI*/0, /*FnId*/GIMT_Encode2(GICXXPred_MI_Predicate_smrd_zextloadi8),
      // (ld:{ *:[i32] } SReg_64:{ *:[i64] }:$sbase)<<P:Predicate_unindexedload>><<P:Predicate_zextload>><<P:Predicate_zextloadi8>><<P:Predicate_smrd_zextloadi8>>  =>  (S_LOAD_U8_IMM:{ *:[i32] } i64:{ *:[i64] }:$sbase, 0:{ *:[i32] }, 0:{ *:[i32] })
      GIR_BuildMI, /*InsnID*/0, /*Opcode*/GIMT_Encode2(AMDGPU::S_LOAD_U8_IMM),
      GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/0, // DstI[sdst]
      GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/1, // sbase
      GIR_AddImm8, /*InsnID*/0, /*Imm*/0,
      GIR_AddImm8, /*InsnID*/0, /*Imm*/0,
      GIR_MergeMemOperands, /*InsnID*/0, /*NumInsns*/1, /*MergeInsnID's*/0,
      GIR_ConstrainSelectedInstOperands, /*InsnID*/0,
      GIR_EraseFromParent, /*InsnID*/0,
      // GIR_Coverage, 2426,
      GIR_Done,
    // Label 1770: @115906
    GIM_Try, /*On fail goto*//*Label 1771*/ GIMT_Encode4(115969), // Rule ID 2438 //
      GIM_CheckFeatures, GIMT_Encode2(GIFBS_isGFX12Plus),
      GIM_CheckMemorySizeEqualTo, /*MI*/0, /*MMO*/0, /*Size*/GIMT_Encode4(2),
      GIM_CheckAtomicOrdering, /*MI*/0, /*Order*/(uint8_t)AtomicOrdering::NotAtomic,
      GIM_CheckRegBankForClass, /*MI*/0, /*Op*/0, /*RC*/GIMT_Encode2(AMDGPU::SReg_32_XM0_XEXECRegClassID),
      // MIs[0] sbase
      GIM_CheckPointerToAny, /*MI*/0, /*Op*/1, /*SizeInBits*/64,
      GIM_CheckRegBankForClass, /*MI*/0, /*Op*/1, /*RC*/GIMT_Encode2(AMDGPU::SReg_64RegClassID),
      GIM_CheckCxxInsnPredicate, /*MI*/0, /*FnId*/GIMT_Encode2(GICXXPred_MI_Predicate_smrd_zextloadi16),
      // (ld:{ *:[i32] } SReg_64:{ *:[i64] }:$sbase)<<P:Predicate_unindexedload>><<P:Predicate_zextload>><<P:Predicate_zextloadi16>><<P:Predicate_smrd_zextloadi16>>  =>  (S_LOAD_U16_IMM:{ *:[i32] } i64:{ *:[i64] }:$sbase, 0:{ *:[i32] }, 0:{ *:[i32] })
      GIR_BuildMI, /*InsnID*/0, /*Opcode*/GIMT_Encode2(AMDGPU::S_LOAD_U16_IMM),
      GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/0, // DstI[sdst]
      GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/1, // sbase
      GIR_AddImm8, /*InsnID*/0, /*Imm*/0,
      GIR_AddImm8, /*InsnID*/0, /*Imm*/0,
      GIR_MergeMemOperands, /*InsnID*/0, /*NumInsns*/1, /*MergeInsnID's*/0,
      GIR_ConstrainSelectedInstOperands, /*InsnID*/0,
      GIR_EraseFromParent, /*InsnID*/0,
      // GIR_Coverage, 2438,
      GIR_Done,
    // Label 1771: @115969
    GIM_Try, /*On fail goto*//*Label 1772*/ GIMT_Encode4(116046), // Rule ID 5356 //
      GIM_CheckFeatures, GIMT_Encode2(GIFBS_DisableFlatScratch_HasUnrestrictedSOffset),
      GIM_CheckMemorySizeEqualTo, /*MI*/0, /*MMO*/0, /*Size*/GIMT_Encode4(1),
      GIM_CheckMemoryAddressSpace, /*MI*/0, /*MMO*/0, /*NumAddrSpace*/1, /*AddrSpace*/5,
      GIM_CheckAtomicOrdering, /*MI*/0, /*Order*/(uint8_t)AtomicOrdering::NotAtomic,
      GIM_CheckRegBankForClass, /*MI*/0, /*Op*/0, /*RC*/GIMT_Encode2(AMDGPU::AV_32RegClassID),
      GIM_CheckPointerToAny, /*MI*/0, /*Op*/1, /*SizeInBits*/0,
      GIM_CheckComplexPattern, /*MI*/0, /*Op*/1, /*Renderer*/GIMT_Encode2(0), GIMT_Encode2(GICP_gi_mubuf_scratch_offset),
      // (ld:{ *:[i32] } (MUBUFScratchOffset:{ *:[iPTR] } v4i32:{ *:[v4i32] }:$srsrc, i32:{ *:[i32] }:$soffset, i32:{ *:[i32] }:$offset))<<P:Predicate_unindexedload>><<P:Predicate_zextload>><<P:Predicate_zextloadi8>><<P:Predicate_zextloadi8_private>>  =>  (BUFFER_LOAD_UBYTE_OFFSET:{ *:[i32] } ?:{ *:[v4i32] }:$srsrc, ?:{ *:[i32] }:$soffset, ?:{ *:[i32] }:$offset, 0:{ *:[i32] }, 0:{ *:[i1] })
      GIR_BuildMI, /*InsnID*/0, /*Opcode*/GIMT_Encode2(AMDGPU::BUFFER_LOAD_UBYTE_OFFSET),
      GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/0, // DstI[vdata]
      GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/0, // srsrc
      GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/1, // soffset
      GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/2, // offset
      GIR_AddImm8, /*InsnID*/0, /*Imm*/0,
      GIR_AddImm8, /*InsnID*/0, /*Imm*/0,
      GIR_MergeMemOperands, /*InsnID*/0, /*NumInsns*/1, /*MergeInsnID's*/0,
      GIR_ConstrainSelectedInstOperands, /*InsnID*/0,
      GIR_EraseFromParent, /*InsnID*/0,
      // GIR_Coverage, 5356,
      GIR_Done,
    // Label 1772: @116046
    GIM_Try, /*On fail goto*//*Label 1773*/ GIMT_Encode4(116123), // Rule ID 5358 //
      GIM_CheckFeatures, GIMT_Encode2(GIFBS_DisableFlatScratch),
      GIM_CheckMemorySizeEqualTo, /*MI*/0, /*MMO*/0, /*Size*/GIMT_Encode4(1),
      GIM_CheckMemoryAddressSpace, /*MI*/0, /*MMO*/0, /*NumAddrSpace*/1, /*AddrSpace*/5,
      GIM_CheckAtomicOrdering, /*MI*/0, /*Order*/(uint8_t)AtomicOrdering::NotAtomic,
      GIM_CheckRegBankForClass, /*MI*/0, /*Op*/0, /*RC*/GIMT_Encode2(AMDGPU::AV_32RegClassID),
      GIM_CheckPointerToAny, /*MI*/0, /*Op*/1, /*SizeInBits*/0,
      GIM_CheckComplexPattern, /*MI*/0, /*Op*/1, /*Renderer*/GIMT_Encode2(0), GIMT_Encode2(GICP_gi_mubuf_scratch_offset),
      // (ld:{ *:[i32] } (MUBUFScratchOffset:{ *:[iPTR] } v4i32:{ *:[v4i32] }:$srsrc, i32:{ *:[i32] }:$soffset, i32:{ *:[i32] }:$offset))<<P:Predicate_unindexedload>><<P:Predicate_zextload>><<P:Predicate_zextloadi8>><<P:Predicate_zextloadi8_private>>  =>  (BUFFER_LOAD_UBYTE_VBUFFER_OFFSET:{ *:[i32] } ?:{ *:[v4i32] }:$srsrc, ?:{ *:[i32] }:$soffset, ?:{ *:[i32] }:$offset, 0:{ *:[i32] }, 0:{ *:[i1] })
      GIR_BuildMI, /*InsnID*/0, /*Opcode*/GIMT_Encode2(AMDGPU::BUFFER_LOAD_UBYTE_VBUFFER_OFFSET),
      GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/0, // DstI[vdata]
      GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/0, // srsrc
      GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/1, // soffset
      GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/2, // offset
      GIR_AddImm8, /*InsnID*/0, /*Imm*/0,
      GIR_AddImm8, /*InsnID*/0, /*Imm*/0,
      GIR_MergeMemOperands, /*InsnID*/0, /*NumInsns*/1, /*MergeInsnID's*/0,
      GIR_ConstrainSelectedInstOperands, /*InsnID*/0,
      GIR_EraseFromParent, /*InsnID*/0,
      // GIR_Coverage, 5358,
      GIR_Done,
    // Label 1773: @116123
    GIM_Try, /*On fail goto*//*Label 1774*/ GIMT_Encode4(116200), // Rule ID 5380 //
      GIM_CheckFeatures, GIMT_Encode2(GIFBS_DisableFlatScratch_HasUnrestrictedSOffset),
      GIM_CheckMemorySizeEqualTo, /*MI*/0, /*MMO*/0, /*Size*/GIMT_Encode4(2),
      GIM_CheckMemoryAddressSpace, /*MI*/0, /*MMO*/0, /*NumAddrSpace*/1, /*AddrSpace*/5,
      GIM_CheckAtomicOrdering, /*MI*/0, /*Order*/(uint8_t)AtomicOrdering::NotAtomic,
      GIM_CheckRegBankForClass, /*MI*/0, /*Op*/0, /*RC*/GIMT_Encode2(AMDGPU::AV_32RegClassID),
      GIM_CheckPointerToAny, /*MI*/0, /*Op*/1, /*SizeInBits*/0,
      GIM_CheckComplexPattern, /*MI*/0, /*Op*/1, /*Renderer*/GIMT_Encode2(0), GIMT_Encode2(GICP_gi_mubuf_scratch_offset),
      // (ld:{ *:[i32] } (MUBUFScratchOffset:{ *:[iPTR] } v4i32:{ *:[v4i32] }:$srsrc, i32:{ *:[i32] }:$soffset, i32:{ *:[i32] }:$offset))<<P:Predicate_unindexedload>><<P:Predicate_zextload>><<P:Predicate_zextloadi16>><<P:Predicate_zextloadi16_private>>  =>  (BUFFER_LOAD_USHORT_OFFSET:{ *:[i32] } ?:{ *:[v4i32] }:$srsrc, ?:{ *:[i32] }:$soffset, ?:{ *:[i32] }:$offset, 0:{ *:[i32] }, 0:{ *:[i1] })
      GIR_BuildMI, /*InsnID*/0, /*Opcode*/GIMT_Encode2(AMDGPU::BUFFER_LOAD_USHORT_OFFSET),
      GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/0, // DstI[vdata]
      GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/0, // srsrc
      GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/1, // soffset
      GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/2, // offset
      GIR_AddImm8, /*InsnID*/0, /*Imm*/0,
      GIR_AddImm8, /*InsnID*/0, /*Imm*/0,
      GIR_MergeMemOperands, /*InsnID*/0, /*NumInsns*/1, /*MergeInsnID's*/0,
      GIR_ConstrainSelectedInstOperands, /*InsnID*/0,
      GIR_EraseFromParent, /*InsnID*/0,
      // GIR_Coverage, 5380,
      GIR_Done,
    // Label 1774: @116200
    GIM_Try, /*On fail goto*//*Label 1775*/ GIMT_Encode4(116277), // Rule ID 5382 //
      GIM_CheckFeatures, GIMT_Encode2(GIFBS_DisableFlatScratch),
      GIM_CheckMemorySizeEqualTo, /*MI*/0, /*MMO*/0, /*Size*/GIMT_Encode4(2),
      GIM_CheckMemoryAddressSpace, /*MI*/0, /*MMO*/0, /*NumAddrSpace*/1, /*AddrSpace*/5,
      GIM_CheckAtomicOrdering, /*MI*/0, /*Order*/(uint8_t)AtomicOrdering::NotAtomic,
      GIM_CheckRegBankForClass, /*MI*/0, /*Op*/0, /*RC*/GIMT_Encode2(AMDGPU::AV_32RegClassID),
      GIM_CheckPointerToAny, /*MI*/0, /*Op*/1, /*SizeInBits*/0,
      GIM_CheckComplexPattern, /*MI*/0, /*Op*/1, /*Renderer*/GIMT_Encode2(0), GIMT_Encode2(GICP_gi_mubuf_scratch_offset),
      // (ld:{ *:[i32] } (MUBUFScratchOffset:{ *:[iPTR] } v4i32:{ *:[v4i32] }:$srsrc, i32:{ *:[i32] }:$soffset, i32:{ *:[i32] }:$offset))<<P:Predicate_unindexedload>><<P:Predicate_zextload>><<P:Predicate_zextloadi16>><<P:Predicate_zextloadi16_private>>  =>  (BUFFER_LOAD_USHORT_VBUFFER_OFFSET:{ *:[i32] } ?:{ *:[v4i32] }:$srsrc, ?:{ *:[i32] }:$soffset, ?:{ *:[i32] }:$offset, 0:{ *:[i32] }, 0:{ *:[i1] })
      GIR_BuildMI, /*InsnID*/0, /*Opcode*/GIMT_Encode2(AMDGPU::BUFFER_LOAD_USHORT_VBUFFER_OFFSET),
      GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/0, // DstI[vdata]
      GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/0, // srsrc
      GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/1, // soffset
      GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/2, // offset
      GIR_AddImm8, /*InsnID*/0, /*Imm*/0,
      GIR_AddImm8, /*InsnID*/0, /*Imm*/0,
      GIR_MergeMemOperands, /*InsnID*/0, /*NumInsns*/1, /*MergeInsnID's*/0,
      GIR_ConstrainSelectedInstOperands, /*InsnID*/0,
      GIR_EraseFromParent, /*InsnID*/0,
      // GIR_Coverage, 5382,
      GIR_Done,
    // Label 1775: @116277
    GIM_Try, /*On fail goto*//*Label 1776*/ GIMT_Encode4(116351), // Rule ID 3406 //
      GIM_CheckFeatures, GIMT_Encode2(GIFBS_EnableFlatScratch_HasFlatScratchInsts_HasFlatScratchSVSMode),
      GIM_CheckMemorySizeEqualTo, /*MI*/0, /*MMO*/0, /*Size*/GIMT_Encode4(1),
      GIM_CheckMemoryAddressSpace, /*MI*/0, /*MMO*/0, /*NumAddrSpace*/1, /*AddrSpace*/5,
      GIM_CheckAtomicOrdering, /*MI*/0, /*Order*/(uint8_t)AtomicOrdering::NotAtomic,
      GIM_CheckRegBankForClass, /*MI*/0, /*Op*/0, /*RC*/GIMT_Encode2(AMDGPU::AV_32RegClassID),
      GIM_CheckPointerToAny, /*MI*/0, /*Op*/1, /*SizeInBits*/0,
      GIM_CheckComplexPattern, /*MI*/0, /*Op*/1, /*Renderer*/GIMT_Encode2(0), GIMT_Encode2(GICP_gi_flat_scratch_svaddr),
      // (ld:{ *:[i32] } (ScratchSVAddr:{ *:[iPTR] } VGPR_32:{ *:[i32] }:$vaddr, SGPR_32:{ *:[i32] }:$saddr, i32:{ *:[i32] }:$offset))<<P:Predicate_unindexedload>><<P:Predicate_zextload>><<P:Predicate_zextloadi8>><<P:Predicate_zextloadi8_private>>  =>  (SCRATCH_LOAD_UBYTE_SVS:{ *:[i32] } ?:{ *:[i32] }:$vaddr, ?:{ *:[i32] }:$saddr, ?:{ *:[i32] }:$offset, 0:{ *:[i32] })
      GIR_BuildMI, /*InsnID*/0, /*Opcode*/GIMT_Encode2(AMDGPU::SCRATCH_LOAD_UBYTE_SVS),
      GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/0, // DstI[vdst]
      GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/0, // vaddr
      GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/1, // saddr
      GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/2, // offset
      GIR_AddImm8, /*InsnID*/0, /*Imm*/0,
      GIR_MergeMemOperands, /*InsnID*/0, /*NumInsns*/1, /*MergeInsnID's*/0,
      GIR_ConstrainSelectedInstOperands, /*InsnID*/0,
      GIR_EraseFromParent, /*InsnID*/0,
      // GIR_Coverage, 3406,
      GIR_Done,
    // Label 1776: @116351
    GIM_Try, /*On fail goto*//*Label 1777*/ GIMT_Encode4(116425), // Rule ID 3424 //
      GIM_CheckFeatures, GIMT_Encode2(GIFBS_EnableFlatScratch_HasFlatScratchInsts_HasFlatScratchSVSMode),
      GIM_CheckMemorySizeEqualTo, /*MI*/0, /*MMO*/0, /*Size*/GIMT_Encode4(2),
      GIM_CheckMemoryAddressSpace, /*MI*/0, /*MMO*/0, /*NumAddrSpace*/1, /*AddrSpace*/5,
      GIM_CheckAtomicOrdering, /*MI*/0, /*Order*/(uint8_t)AtomicOrdering::NotAtomic,
      GIM_CheckRegBankForClass, /*MI*/0, /*Op*/0, /*RC*/GIMT_Encode2(AMDGPU::AV_32RegClassID),
      GIM_CheckPointerToAny, /*MI*/0, /*Op*/1, /*SizeInBits*/0,
      GIM_CheckComplexPattern, /*MI*/0, /*Op*/1, /*Renderer*/GIMT_Encode2(0), GIMT_Encode2(GICP_gi_flat_scratch_svaddr),
      // (ld:{ *:[i32] } (ScratchSVAddr:{ *:[iPTR] } VGPR_32:{ *:[i32] }:$vaddr, SGPR_32:{ *:[i32] }:$saddr, i32:{ *:[i32] }:$offset))<<P:Predicate_unindexedload>><<P:Predicate_zextload>><<P:Predicate_zextloadi16>><<P:Predicate_zextloadi16_private>>  =>  (SCRATCH_LOAD_USHORT_SVS:{ *:[i32] } ?:{ *:[i32] }:$vaddr, ?:{ *:[i32] }:$saddr, ?:{ *:[i32] }:$offset, 0:{ *:[i32] })
      GIR_BuildMI, /*InsnID*/0, /*Opcode*/GIMT_Encode2(AMDGPU::SCRATCH_LOAD_USHORT_SVS),
      GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/0, // DstI[vdst]
      GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/0, // vaddr
      GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/1, // saddr
      GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/2, // offset
      GIR_AddImm8, /*InsnID*/0, /*Imm*/0,
      GIR_MergeMemOperands, /*InsnID*/0, /*NumInsns*/1, /*MergeInsnID's*/0,
      GIR_ConstrainSelectedInstOperands, /*InsnID*/0,
      GIR_EraseFromParent, /*InsnID*/0,
      // GIR_Coverage, 3424,
      GIR_Done,
    // Label 1777: @116425
    GIM_Try, /*On fail goto*//*Label 1778*/ GIMT_Encode4(116494), // Rule ID 3405 //
      GIM_CheckFeatures, GIMT_Encode2(GIFBS_EnableFlatScratch_HasFlatScratchInsts),
      GIM_CheckMemorySizeEqualTo, /*MI*/0, /*MMO*/0, /*Size*/GIMT_Encode4(1),
      GIM_CheckMemoryAddressSpace, /*MI*/0, /*MMO*/0, /*NumAddrSpace*/1, /*AddrSpace*/5,
      GIM_CheckAtomicOrdering, /*MI*/0, /*Order*/(uint8_t)AtomicOrdering::NotAtomic,
      GIM_CheckRegBankForClass, /*MI*/0, /*Op*/0, /*RC*/GIMT_Encode2(AMDGPU::AV_32RegClassID),
      GIM_CheckPointerToAny, /*MI*/0, /*Op*/1, /*SizeInBits*/0,
      GIM_CheckComplexPattern, /*MI*/0, /*Op*/1, /*Renderer*/GIMT_Encode2(0), GIMT_Encode2(GICP_gi_flat_scratch_saddr),
      // (ld:{ *:[i32] } (ScratchSAddr:{ *:[iPTR] } SGPR_32:{ *:[i32] }:$saddr, i32:{ *:[i32] }:$offset))<<P:Predicate_unindexedload>><<P:Predicate_zextload>><<P:Predicate_zextloadi8>><<P:Predicate_zextloadi8_private>>  =>  (SCRATCH_LOAD_UBYTE_SADDR:{ *:[i32] } ?:{ *:[i32] }:$saddr, ?:{ *:[i32] }:$offset)
      GIR_BuildMI, /*InsnID*/0, /*Opcode*/GIMT_Encode2(AMDGPU::SCRATCH_LOAD_UBYTE_SADDR),
      GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/0, // DstI[vdst]
      GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/0, // saddr
      GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/1, // offset
      GIR_AddImm8, /*InsnID*/0, /*Imm*/0,
      GIR_MergeMemOperands, /*InsnID*/0, /*NumInsns*/1, /*MergeInsnID's*/0,
      GIR_ConstrainSelectedInstOperands, /*InsnID*/0,
      GIR_EraseFromParent, /*InsnID*/0,
      // GIR_Coverage, 3405,
      GIR_Done,
    // Label 1778: @116494
    GIM_Try, /*On fail goto*//*Label 1779*/ GIMT_Encode4(116563), // Rule ID 3423 //
      GIM_CheckFeatures, GIMT_Encode2(GIFBS_EnableFlatScratch_HasFlatScratchInsts),
      GIM_CheckMemorySizeEqualTo, /*MI*/0, /*MMO*/0, /*Size*/GIMT_Encode4(2),
      GIM_CheckMemoryAddressSpace, /*MI*/0, /*MMO*/0, /*NumAddrSpace*/1, /*AddrSpace*/5,
      GIM_CheckAtomicOrdering, /*MI*/0, /*Order*/(uint8_t)AtomicOrdering::NotAtomic,
      GIM_CheckRegBankForClass, /*MI*/0, /*Op*/0, /*RC*/GIMT_Encode2(AMDGPU::AV_32RegClassID),
      GIM_CheckPointerToAny, /*MI*/0, /*Op*/1, /*SizeInBits*/0,
      GIM_CheckComplexPattern, /*MI*/0, /*Op*/1, /*Renderer*/GIMT_Encode2(0), GIMT_Encode2(GICP_gi_flat_scratch_saddr),
      // (ld:{ *:[i32] } (ScratchSAddr:{ *:[iPTR] } SGPR_32:{ *:[i32] }:$saddr, i32:{ *:[i32] }:$offset))<<P:Predicate_unindexedload>><<P:Predicate_zextload>><<P:Predicate_zextloadi16>><<P:Predicate_zextloadi16_private>>  =>  (SCRATCH_LOAD_USHORT_SADDR:{ *:[i32] } ?:{ *:[i32] }:$saddr, ?:{ *:[i32] }:$offset)
      GIR_BuildMI, /*InsnID*/0, /*Opcode*/GIMT_Encode2(AMDGPU::SCRATCH_LOAD_USHORT_SADDR),
      GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/0, // DstI[vdst]
      GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/0, // saddr
      GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/1, // offset
      GIR_AddImm8, /*InsnID*/0, /*Imm*/0,
      GIR_MergeMemOperands, /*InsnID*/0, /*NumInsns*/1, /*MergeInsnID's*/0,
      GIR_ConstrainSelectedInstOperands, /*InsnID*/0,
      GIR_EraseFromParent, /*InsnID*/0,
      // GIR_Coverage, 3423,
      GIR_Done,
    // Label 1779: @116563
    GIM_Try, /*On fail goto*//*Label 1780*/ GIMT_Encode4(116632), // Rule ID 3404 //
      GIM_CheckFeatures, GIMT_Encode2(GIFBS_EnableFlatScratch_HasFlatScratchInsts),
      GIM_CheckMemorySizeEqualTo, /*MI*/0, /*MMO*/0, /*Size*/GIMT_Encode4(1),
      GIM_CheckMemoryAddressSpace, /*MI*/0, /*MMO*/0, /*NumAddrSpace*/1, /*AddrSpace*/5,
      GIM_CheckAtomicOrdering, /*MI*/0, /*Order*/(uint8_t)AtomicOrdering::NotAtomic,
      GIM_CheckRegBankForClass, /*MI*/0, /*Op*/0, /*RC*/GIMT_Encode2(AMDGPU::AV_32RegClassID),
      GIM_CheckPointerToAny, /*MI*/0, /*Op*/1, /*SizeInBits*/0,
      GIM_CheckComplexPattern, /*MI*/0, /*Op*/1, /*Renderer*/GIMT_Encode2(0), GIMT_Encode2(GICP_gi_flat_scratch_offset),
      // (ld:{ *:[i32] } (ScratchOffset:{ *:[iPTR] } VGPR_32:{ *:[i32] }:$vaddr, i32:{ *:[i32] }:$offset))<<P:Predicate_unindexedload>><<P:Predicate_zextload>><<P:Predicate_zextloadi8>><<P:Predicate_zextloadi8_private>>  =>  (SCRATCH_LOAD_UBYTE:{ *:[i32] } ?:{ *:[i32] }:$vaddr, ?:{ *:[i32] }:$offset)
      GIR_BuildMI, /*InsnID*/0, /*Opcode*/GIMT_Encode2(AMDGPU::SCRATCH_LOAD_UBYTE),
      GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/0, // DstI[vdst]
      GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/0, // vaddr
      GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/1, // offset
      GIR_AddImm8, /*InsnID*/0, /*Imm*/0,
      GIR_MergeMemOperands, /*InsnID*/0, /*NumInsns*/1, /*MergeInsnID's*/0,
      GIR_ConstrainSelectedInstOperands, /*InsnID*/0,
      GIR_EraseFromParent, /*InsnID*/0,
      // GIR_Coverage, 3404,
      GIR_Done,
    // Label 1780: @116632
    GIM_Try, /*On fail goto*//*Label 1781*/ GIMT_Encode4(116701), // Rule ID 3422 //
      GIM_CheckFeatures, GIMT_Encode2(GIFBS_EnableFlatScratch_HasFlatScratchInsts),
      GIM_CheckMemorySizeEqualTo, /*MI*/0, /*MMO*/0, /*Size*/GIMT_Encode4(2),
      GIM_CheckMemoryAddressSpace, /*MI*/0, /*MMO*/0, /*NumAddrSpace*/1, /*AddrSpace*/5,
      GIM_CheckAtomicOrdering, /*MI*/0, /*Order*/(uint8_t)AtomicOrdering::NotAtomic,
      GIM_CheckRegBankForClass, /*MI*/0, /*Op*/0, /*RC*/GIMT_Encode2(AMDGPU::AV_32RegClassID),
      GIM_CheckPointerToAny, /*MI*/0, /*Op*/1, /*SizeInBits*/0,
      GIM_CheckComplexPattern, /*MI*/0, /*Op*/1, /*Renderer*/GIMT_Encode2(0), GIMT_Encode2(GICP_gi_flat_scratch_offset),
      // (ld:{ *:[i32] } (ScratchOffset:{ *:[iPTR] } VGPR_32:{ *:[i32] }:$vaddr, i32:{ *:[i32] }:$offset))<<P:Predicate_unindexedload>><<P:Predicate_zextload>><<P:Predicate_zextloadi16>><<P:Predicate_zextloadi16_private>>  =>  (SCRATCH_LOAD_USHORT:{ *:[i32] } ?:{ *:[i32] }:$vaddr, ?:{ *:[i32] }:$offset)
      GIR_BuildMI, /*InsnID*/0, /*Opcode*/GIMT_Encode2(AMDGPU::SCRATCH_LOAD_USHORT),
      GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/0, // DstI[vdst]
      GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/0, // vaddr
      GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/1, // offset
      GIR_AddImm8, /*InsnID*/0, /*Imm*/0,
      GIR_MergeMemOperands, /*InsnID*/0, /*NumInsns*/1, /*MergeInsnID's*/0,
      GIR_ConstrainSelectedInstOperands, /*InsnID*/0,
      GIR_EraseFromParent, /*InsnID*/0,
      // GIR_Coverage, 3422,
      GIR_Done,
    // Label 1781: @116701
    GIM_Try, /*On fail goto*//*Label 1782*/ GIMT_Encode4(116785), // Rule ID 3664 //
      GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasUnrestrictedSOffset),
      GIM_CheckMemorySizeEqualTo, /*MI*/0, /*MMO*/0, /*Size*/GIMT_Encode4(1),
      GIM_CheckMemoryAddressSpace, /*MI*/0, /*MMO*/0, /*NumAddrSpace*/3, /*AddrSpace*/1, /*AddrSpace*/4, /*AddrSpace*/6,
      GIM_CheckAtomicOrdering, /*MI*/0, /*Order*/(uint8_t)AtomicOrdering::NotAtomic,
      GIM_CheckRegBankForClass, /*MI*/0, /*Op*/0, /*RC*/GIMT_Encode2(AMDGPU::AV_32RegClassID),
      GIM_CheckPointerToAny, /*MI*/0, /*Op*/1, /*SizeInBits*/0,
      GIM_CheckComplexPattern, /*MI*/0, /*Op*/1, /*Renderer*/GIMT_Encode2(0), GIMT_Encode2(GICP_gi_mubuf_addr64),
      // (ld:{ *:[i32] } (MUBUFAddr64:{ *:[iPTR] } v4i32:{ *:[v4i32] }:$srsrc, i64:{ *:[i64] }:$vaddr, i32:{ *:[i32] }:$soffset, i32:{ *:[i32] }:$offset))<<P:Predicate_unindexedload>><<P:Predicate_zextload>><<P:Predicate_zextloadi8>><<P:Predicate_zextloadi8_global>>  =>  (BUFFER_LOAD_UBYTE_ADDR64:{ *:[i32] } i64:{ *:[i64] }:$vaddr, v4i32:{ *:[v4i32] }:$srsrc, i32:{ *:[i32] }:$soffset, i32:{ *:[i32] }:$offset)
      GIR_BuildMI, /*InsnID*/0, /*Opcode*/GIMT_Encode2(AMDGPU::BUFFER_LOAD_UBYTE_ADDR64),
      GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/0, // DstI[vdata]
      GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/1, // vaddr
      GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/0, // srsrc
      GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/2, // soffset
      GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/3, // offset
      GIR_AddImm8, /*InsnID*/0, /*Imm*/0,
      GIR_AddImm8, /*InsnID*/0, /*Imm*/0,
      GIR_MergeMemOperands, /*InsnID*/0, /*NumInsns*/1, /*MergeInsnID's*/0,
      GIR_ConstrainSelectedInstOperands, /*InsnID*/0,
      GIR_EraseFromParent, /*InsnID*/0,
      // GIR_Coverage, 3664,
      GIR_Done,
    // Label 1782: @116785
    GIM_Try, /*On fail goto*//*Label 1783*/ GIMT_Encode4(116866), // Rule ID 3666 //
      GIM_CheckMemorySizeEqualTo, /*MI*/0, /*MMO*/0, /*Size*/GIMT_Encode4(1),
      GIM_CheckMemoryAddressSpace, /*MI*/0, /*MMO*/0, /*NumAddrSpace*/3, /*AddrSpace*/1, /*AddrSpace*/4, /*AddrSpace*/6,
      GIM_CheckAtomicOrdering, /*MI*/0, /*Order*/(uint8_t)AtomicOrdering::NotAtomic,
      GIM_CheckRegBankForClass, /*MI*/0, /*Op*/0, /*RC*/GIMT_Encode2(AMDGPU::AV_32RegClassID),
      GIM_CheckPointerToAny, /*MI*/0, /*Op*/1, /*SizeInBits*/0,
      GIM_CheckComplexPattern, /*MI*/0, /*Op*/1, /*Renderer*/GIMT_Encode2(0), GIMT_Encode2(GICP_gi_mubuf_addr64),
      // (ld:{ *:[i32] } (MUBUFAddr64:{ *:[iPTR] } v4i32:{ *:[v4i32] }:$srsrc, i64:{ *:[i64] }:$vaddr, i32:{ *:[i32] }:$soffset, i32:{ *:[i32] }:$offset))<<P:Predicate_unindexedload>><<P:Predicate_zextload>><<P:Predicate_zextloadi8>><<P:Predicate_zextloadi8_global>>  =>  (BUFFER_LOAD_UBYTE_VBUFFER_ADDR64:{ *:[i32] } i64:{ *:[i64] }:$vaddr, v4i32:{ *:[v4i32] }:$srsrc, i32:{ *:[i32] }:$soffset, i32:{ *:[i32] }:$offset)
      GIR_BuildMI, /*InsnID*/0, /*Opcode*/GIMT_Encode2(AMDGPU::BUFFER_LOAD_UBYTE_VBUFFER_ADDR64),
      GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/0, // DstI[vdata]
      GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/1, // vaddr
      GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/0, // srsrc
      GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/2, // soffset
      GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/3, // offset
      GIR_AddImm8, /*InsnID*/0, /*Imm*/0,
      GIR_AddImm8, /*InsnID*/0, /*Imm*/0,
      GIR_MergeMemOperands, /*InsnID*/0, /*NumInsns*/1, /*MergeInsnID's*/0,
      GIR_ConstrainSelectedInstOperands, /*InsnID*/0,
      GIR_EraseFromParent, /*InsnID*/0,
      // GIR_Coverage, 3666,
      GIR_Done,
    // Label 1783: @116866
    GIM_Try, /*On fail goto*//*Label 1784*/ GIMT_Encode4(116950), // Rule ID 3676 //
      GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasUnrestrictedSOffset),
      GIM_CheckMemorySizeEqualTo, /*MI*/0, /*MMO*/0, /*Size*/GIMT_Encode4(2),
      GIM_CheckMemoryAddressSpace, /*MI*/0, /*MMO*/0, /*NumAddrSpace*/3, /*AddrSpace*/1, /*AddrSpace*/4, /*AddrSpace*/6,
      GIM_CheckAtomicOrdering, /*MI*/0, /*Order*/(uint8_t)AtomicOrdering::NotAtomic,
      GIM_CheckRegBankForClass, /*MI*/0, /*Op*/0, /*RC*/GIMT_Encode2(AMDGPU::AV_32RegClassID),
      GIM_CheckPointerToAny, /*MI*/0, /*Op*/1, /*SizeInBits*/0,
      GIM_CheckComplexPattern, /*MI*/0, /*Op*/1, /*Renderer*/GIMT_Encode2(0), GIMT_Encode2(GICP_gi_mubuf_addr64),
      // (ld:{ *:[i32] } (MUBUFAddr64:{ *:[iPTR] } v4i32:{ *:[v4i32] }:$srsrc, i64:{ *:[i64] }:$vaddr, i32:{ *:[i32] }:$soffset, i32:{ *:[i32] }:$offset))<<P:Predicate_unindexedload>><<P:Predicate_zextload>><<P:Predicate_zextloadi16>><<P:Predicate_zextloadi16_global>>  =>  (BUFFER_LOAD_USHORT_ADDR64:{ *:[i32] } i64:{ *:[i64] }:$vaddr, v4i32:{ *:[v4i32] }:$srsrc, i32:{ *:[i32] }:$soffset, i32:{ *:[i32] }:$offset)
      GIR_BuildMI, /*InsnID*/0, /*Opcode*/GIMT_Encode2(AMDGPU::BUFFER_LOAD_USHORT_ADDR64),
      GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/0, // DstI[vdata]
      GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/1, // vaddr
      GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/0, // srsrc
      GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/2, // soffset
      GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/3, // offset
      GIR_AddImm8, /*InsnID*/0, /*Imm*/0,
      GIR_AddImm8, /*InsnID*/0, /*Imm*/0,
      GIR_MergeMemOperands, /*InsnID*/0, /*NumInsns*/1, /*MergeInsnID's*/0,
      GIR_ConstrainSelectedInstOperands, /*InsnID*/0,
      GIR_EraseFromParent, /*InsnID*/0,
      // GIR_Coverage, 3676,
      GIR_Done,
    // Label 1784: @116950
    GIM_Try, /*On fail goto*//*Label 1785*/ GIMT_Encode4(117031), // Rule ID 3678 //
      GIM_CheckMemorySizeEqualTo, /*MI*/0, /*MMO*/0, /*Size*/GIMT_Encode4(2),
      GIM_CheckMemoryAddressSpace, /*MI*/0, /*MMO*/0, /*NumAddrSpace*/3, /*AddrSpace*/1, /*AddrSpace*/4, /*AddrSpace*/6,
      GIM_CheckAtomicOrdering, /*MI*/0, /*Order*/(uint8_t)AtomicOrdering::NotAtomic,
      GIM_CheckRegBankForClass, /*MI*/0, /*Op*/0, /*RC*/GIMT_Encode2(AMDGPU::AV_32RegClassID),
      GIM_CheckPointerToAny, /*MI*/0, /*Op*/1, /*SizeInBits*/0,
      GIM_CheckComplexPattern, /*MI*/0, /*Op*/1, /*Renderer*/GIMT_Encode2(0), GIMT_Encode2(GICP_gi_mubuf_addr64),
      // (ld:{ *:[i32] } (MUBUFAddr64:{ *:[iPTR] } v4i32:{ *:[v4i32] }:$srsrc, i64:{ *:[i64] }:$vaddr, i32:{ *:[i32] }:$soffset, i32:{ *:[i32] }:$offset))<<P:Predicate_unindexedload>><<P:Predicate_zextload>><<P:Predicate_zextloadi16>><<P:Predicate_zextloadi16_global>>  =>  (BUFFER_LOAD_USHORT_VBUFFER_ADDR64:{ *:[i32] } i64:{ *:[i64] }:$vaddr, v4i32:{ *:[v4i32] }:$srsrc, i32:{ *:[i32] }:$soffset, i32:{ *:[i32] }:$offset)
      GIR_BuildMI, /*InsnID*/0, /*Opcode*/GIMT_Encode2(AMDGPU::BUFFER_LOAD_USHORT_VBUFFER_ADDR64),
      GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/0, // DstI[vdata]
      GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/1, // vaddr
      GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/0, // srsrc
      GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/2, // soffset
      GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/3, // offset
      GIR_AddImm8, /*InsnID*/0, /*Imm*/0,
      GIR_AddImm8, /*InsnID*/0, /*Imm*/0,
      GIR_MergeMemOperands, /*InsnID*/0, /*NumInsns*/1, /*MergeInsnID's*/0,
      GIR_ConstrainSelectedInstOperands, /*InsnID*/0,
      GIR_EraseFromParent, /*InsnID*/0,
      // GIR_Coverage, 3678,
      GIR_Done,
    // Label 1785: @117031
    GIM_Try, /*On fail goto*//*Label 1786*/ GIMT_Encode4(117114), // Rule ID 5325 //
      GIM_CheckFeatures, GIMT_Encode2(GIFBS_isGFX6GFX7),
      GIM_CheckMemorySizeEqualTo, /*MI*/0, /*MMO*/0, /*Size*/GIMT_Encode4(1),
      GIM_CheckMemoryAddressSpace, /*MI*/0, /*MMO*/0, /*NumAddrSpace*/2, /*AddrSpace*/4, /*AddrSpace*/6,
      GIM_CheckAtomicOrdering, /*MI*/0, /*Order*/(uint8_t)AtomicOrdering::NotAtomic,
      GIM_CheckRegBankForClass, /*MI*/0, /*Op*/0, /*RC*/GIMT_Encode2(AMDGPU::AV_32RegClassID),
      GIM_CheckPointerToAny, /*MI*/0, /*Op*/1, /*SizeInBits*/0,
      GIM_CheckComplexPattern, /*MI*/0, /*Op*/1, /*Renderer*/GIMT_Encode2(0), GIMT_Encode2(GICP_gi_mubuf_addr64),
      // (ld:{ *:[i32] } (MUBUFAddr64:{ *:[iPTR] } v4i32:{ *:[v4i32] }:$srsrc, i64:{ *:[i64] }:$vaddr, i32:{ *:[i32] }:$soffset, i32:{ *:[i32] }:$offset))<<P:Predicate_unindexedload>><<P:Predicate_zextload>><<P:Predicate_zextloadi8>><<P:Predicate_zextloadi8_constant>>  =>  (BUFFER_LOAD_UBYTE_ADDR64:{ *:[i32] } ?:{ *:[i64] }:$vaddr, ?:{ *:[v4i32] }:$srsrc, ?:{ *:[i32] }:$soffset, ?:{ *:[i32] }:$offset)
      GIR_BuildMI, /*InsnID*/0, /*Opcode*/GIMT_Encode2(AMDGPU::BUFFER_LOAD_UBYTE_ADDR64),
      GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/0, // DstI[vdata]
      GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/1, // vaddr
      GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/0, // srsrc
      GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/2, // soffset
      GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/3, // offset
      GIR_AddImm8, /*InsnID*/0, /*Imm*/0,
      GIR_AddImm8, /*InsnID*/0, /*Imm*/0,
      GIR_MergeMemOperands, /*InsnID*/0, /*NumInsns*/1, /*MergeInsnID's*/0,
      GIR_ConstrainSelectedInstOperands, /*InsnID*/0,
      GIR_EraseFromParent, /*InsnID*/0,
      // GIR_Coverage, 5325,
      GIR_Done,
    // Label 1786: @117114
    GIM_Try, /*On fail goto*//*Label 1787*/ GIMT_Encode4(117197), // Rule ID 5328 //
      GIM_CheckFeatures, GIMT_Encode2(GIFBS_isGFX6GFX7),
      GIM_CheckMemorySizeEqualTo, /*MI*/0, /*MMO*/0, /*Size*/GIMT_Encode4(2),
      GIM_CheckMemoryAddressSpace, /*MI*/0, /*MMO*/0, /*NumAddrSpace*/2, /*AddrSpace*/4, /*AddrSpace*/6,
      GIM_CheckAtomicOrdering, /*MI*/0, /*Order*/(uint8_t)AtomicOrdering::NotAtomic,
      GIM_CheckRegBankForClass, /*MI*/0, /*Op*/0, /*RC*/GIMT_Encode2(AMDGPU::AV_32RegClassID),
      GIM_CheckPointerToAny, /*MI*/0, /*Op*/1, /*SizeInBits*/0,
      GIM_CheckComplexPattern, /*MI*/0, /*Op*/1, /*Renderer*/GIMT_Encode2(0), GIMT_Encode2(GICP_gi_mubuf_addr64),
      // (ld:{ *:[i32] } (MUBUFAddr64:{ *:[iPTR] } v4i32:{ *:[v4i32] }:$srsrc, i64:{ *:[i64] }:$vaddr, i32:{ *:[i32] }:$soffset, i32:{ *:[i32] }:$offset))<<P:Predicate_unindexedload>><<P:Predicate_zextload>><<P:Predicate_zextloadi16>><<P:Predicate_zextloadi16_constant>>  =>  (BUFFER_LOAD_USHORT_ADDR64:{ *:[i32] } ?:{ *:[i64] }:$vaddr, ?:{ *:[v4i32] }:$srsrc, ?:{ *:[i32] }:$soffset, ?:{ *:[i32] }:$offset)
      GIR_BuildMI, /*InsnID*/0, /*Opcode*/GIMT_Encode2(AMDGPU::BUFFER_LOAD_USHORT_ADDR64),
      GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/0, // DstI[vdata]
      GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/1, // vaddr
      GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/0, // srsrc
      GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/2, // soffset
      GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/3, // offset
      GIR_AddImm8, /*InsnID*/0, /*Imm*/0,
      GIR_AddImm8, /*InsnID*/0, /*Imm*/0,
      GIR_MergeMemOperands, /*InsnID*/0, /*NumInsns*/1, /*MergeInsnID's*/0,
      GIR_ConstrainSelectedInstOperands, /*InsnID*/0,
      GIR_EraseFromParent, /*InsnID*/0,
      // GIR_Coverage, 5328,
      GIR_Done,
    // Label 1787: @117197
    GIM_Try, /*On fail goto*//*Label 1788*/ GIMT_Encode4(117279), // Rule ID 5355 //
      GIM_CheckFeatures, GIMT_Encode2(GIFBS_DisableFlatScratch_HasUnrestrictedSOffset),
      GIM_CheckMemorySizeEqualTo, /*MI*/0, /*MMO*/0, /*Size*/GIMT_Encode4(1),
      GIM_CheckMemoryAddressSpace, /*MI*/0, /*MMO*/0, /*NumAddrSpace*/1, /*AddrSpace*/5,
      GIM_CheckAtomicOrdering, /*MI*/0, /*Order*/(uint8_t)AtomicOrdering::NotAtomic,
      GIM_CheckRegBankForClass, /*MI*/0, /*Op*/0, /*RC*/GIMT_Encode2(AMDGPU::AV_32RegClassID),
      GIM_CheckPointerToAny, /*MI*/0, /*Op*/1, /*SizeInBits*/0,
      GIM_CheckComplexPattern, /*MI*/0, /*Op*/1, /*Renderer*/GIMT_Encode2(0), GIMT_Encode2(GICP_gi_mubuf_scratch_offen),
      // (ld:{ *:[i32] } (MUBUFScratchOffen:{ *:[iPTR] } v4i32:{ *:[v4i32] }:$srsrc, i32:{ *:[i32] }:$vaddr, i32:{ *:[i32] }:$soffset, i32:{ *:[i32] }:$offset))<<P:Predicate_unindexedload>><<P:Predicate_zextload>><<P:Predicate_zextloadi8>><<P:Predicate_zextloadi8_private>>  =>  (BUFFER_LOAD_UBYTE_OFFEN:{ *:[i32] } ?:{ *:[i32] }:$vaddr, ?:{ *:[v4i32] }:$srsrc, ?:{ *:[i32] }:$soffset, ?:{ *:[i32] }:$offset, 0:{ *:[i32] }, 0:{ *:[i1] })
      GIR_BuildMI, /*InsnID*/0, /*Opcode*/GIMT_Encode2(AMDGPU::BUFFER_LOAD_UBYTE_OFFEN),
      GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/0, // DstI[vdata]
      GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/1, // vaddr
      GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/0, // srsrc
      GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/2, // soffset
      GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/3, // offset
      GIR_AddImm8, /*InsnID*/0, /*Imm*/0,
      GIR_AddImm8, /*InsnID*/0, /*Imm*/0,
      GIR_MergeMemOperands, /*InsnID*/0, /*NumInsns*/1, /*MergeInsnID's*/0,
      GIR_ConstrainSelectedInstOperands, /*InsnID*/0,
      GIR_EraseFromParent, /*InsnID*/0,
      // GIR_Coverage, 5355,
      GIR_Done,
    // Label 1788: @117279
    GIM_Try, /*On fail goto*//*Label 1789*/ GIMT_Encode4(117361), // Rule ID 5357 //
      GIM_CheckFeatures, GIMT_Encode2(GIFBS_DisableFlatScratch),
      GIM_CheckMemorySizeEqualTo, /*MI*/0, /*MMO*/0, /*Size*/GIMT_Encode4(1),
      GIM_CheckMemoryAddressSpace, /*MI*/0, /*MMO*/0, /*NumAddrSpace*/1, /*AddrSpace*/5,
      GIM_CheckAtomicOrdering, /*MI*/0, /*Order*/(uint8_t)AtomicOrdering::NotAtomic,
      GIM_CheckRegBankForClass, /*MI*/0, /*Op*/0, /*RC*/GIMT_Encode2(AMDGPU::AV_32RegClassID),
      GIM_CheckPointerToAny, /*MI*/0, /*Op*/1, /*SizeInBits*/0,
      GIM_CheckComplexPattern, /*MI*/0, /*Op*/1, /*Renderer*/GIMT_Encode2(0), GIMT_Encode2(GICP_gi_mubuf_scratch_offen),
      // (ld:{ *:[i32] } (MUBUFScratchOffen:{ *:[iPTR] } v4i32:{ *:[v4i32] }:$srsrc, i32:{ *:[i32] }:$vaddr, i32:{ *:[i32] }:$soffset, i32:{ *:[i32] }:$offset))<<P:Predicate_unindexedload>><<P:Predicate_zextload>><<P:Predicate_zextloadi8>><<P:Predicate_zextloadi8_private>>  =>  (BUFFER_LOAD_UBYTE_VBUFFER_OFFEN:{ *:[i32] } ?:{ *:[i32] }:$vaddr, ?:{ *:[v4i32] }:$srsrc, ?:{ *:[i32] }:$soffset, ?:{ *:[i32] }:$offset, 0:{ *:[i32] }, 0:{ *:[i1] })
      GIR_BuildMI, /*InsnID*/0, /*Opcode*/GIMT_Encode2(AMDGPU::BUFFER_LOAD_UBYTE_VBUFFER_OFFEN),
      GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/0, // DstI[vdata]
      GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/1, // vaddr
      GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/0, // srsrc
      GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/2, // soffset
      GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/3, // offset
      GIR_AddImm8, /*InsnID*/0, /*Imm*/0,
      GIR_AddImm8, /*InsnID*/0, /*Imm*/0,
      GIR_MergeMemOperands, /*InsnID*/0, /*NumInsns*/1, /*MergeInsnID's*/0,
      GIR_ConstrainSelectedInstOperands, /*InsnID*/0,
      GIR_EraseFromParent, /*InsnID*/0,
      // GIR_Coverage, 5357,
      GIR_Done,
    // Label 1789: @117361
    GIM_Try, /*On fail goto*//*Label 1790*/ GIMT_Encode4(117443), // Rule ID 5379 //
      GIM_CheckFeatures, GIMT_Encode2(GIFBS_DisableFlatScratch_HasUnrestrictedSOffset),
      GIM_CheckMemorySizeEqualTo, /*MI*/0, /*MMO*/0, /*Size*/GIMT_Encode4(2),
      GIM_CheckMemoryAddressSpace, /*MI*/0, /*MMO*/0, /*NumAddrSpace*/1, /*AddrSpace*/5,
      GIM_CheckAtomicOrdering, /*MI*/0, /*Order*/(uint8_t)AtomicOrdering::NotAtomic,
      GIM_CheckRegBankForClass, /*MI*/0, /*Op*/0, /*RC*/GIMT_Encode2(AMDGPU::AV_32RegClassID),
      GIM_CheckPointerToAny, /*MI*/0, /*Op*/1, /*SizeInBits*/0,
      GIM_CheckComplexPattern, /*MI*/0, /*Op*/1, /*Renderer*/GIMT_Encode2(0), GIMT_Encode2(GICP_gi_mubuf_scratch_offen),
      // (ld:{ *:[i32] } (MUBUFScratchOffen:{ *:[iPTR] } v4i32:{ *:[v4i32] }:$srsrc, i32:{ *:[i32] }:$vaddr, i32:{ *:[i32] }:$soffset, i32:{ *:[i32] }:$offset))<<P:Predicate_unindexedload>><<P:Predicate_zextload>><<P:Predicate_zextloadi16>><<P:Predicate_zextloadi16_private>>  =>  (BUFFER_LOAD_USHORT_OFFEN:{ *:[i32] } ?:{ *:[i32] }:$vaddr, ?:{ *:[v4i32] }:$srsrc, ?:{ *:[i32] }:$soffset, ?:{ *:[i32] }:$offset, 0:{ *:[i32] }, 0:{ *:[i1] })
      GIR_BuildMI, /*InsnID*/0, /*Opcode*/GIMT_Encode2(AMDGPU::BUFFER_LOAD_USHORT_OFFEN),
      GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/0, // DstI[vdata]
      GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/1, // vaddr
      GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/0, // srsrc
      GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/2, // soffset
      GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/3, // offset
      GIR_AddImm8, /*InsnID*/0, /*Imm*/0,
      GIR_AddImm8, /*InsnID*/0, /*Imm*/0,
      GIR_MergeMemOperands, /*InsnID*/0, /*NumInsns*/1, /*MergeInsnID's*/0,
      GIR_ConstrainSelectedInstOperands, /*InsnID*/0,
      GIR_EraseFromParent, /*InsnID*/0,
      // GIR_Coverage, 5379,
      GIR_Done,
    // Label 1790: @117443
    GIM_Try, /*On fail goto*//*Label 1791*/ GIMT_Encode4(117525), // Rule ID 5381 //
      GIM_CheckFeatures, GIMT_Encode2(GIFBS_DisableFlatScratch),
      GIM_CheckMemorySizeEqualTo, /*MI*/0, /*MMO*/0, /*Size*/GIMT_Encode4(2),
      GIM_CheckMemoryAddressSpace, /*MI*/0, /*MMO*/0, /*NumAddrSpace*/1, /*AddrSpace*/5,
      GIM_CheckAtomicOrdering, /*MI*/0, /*Order*/(uint8_t)AtomicOrdering::NotAtomic,
      GIM_CheckRegBankForClass, /*MI*/0, /*Op*/0, /*RC*/GIMT_Encode2(AMDGPU::AV_32RegClassID),
      GIM_CheckPointerToAny, /*MI*/0, /*Op*/1, /*SizeInBits*/0,
      GIM_CheckComplexPattern, /*MI*/0, /*Op*/1, /*Renderer*/GIMT_Encode2(0), GIMT_Encode2(GICP_gi_mubuf_scratch_offen),
      // (ld:{ *:[i32] } (MUBUFScratchOffen:{ *:[iPTR] } v4i32:{ *:[v4i32] }:$srsrc, i32:{ *:[i32] }:$vaddr, i32:{ *:[i32] }:$soffset, i32:{ *:[i32] }:$offset))<<P:Predicate_unindexedload>><<P:Predicate_zextload>><<P:Predicate_zextloadi16>><<P:Predicate_zextloadi16_private>>  =>  (BUFFER_LOAD_USHORT_VBUFFER_OFFEN:{ *:[i32] } ?:{ *:[i32] }:$vaddr, ?:{ *:[v4i32] }:$srsrc, ?:{ *:[i32] }:$soffset, ?:{ *:[i32] }:$offset, 0:{ *:[i32] }, 0:{ *:[i1] })
      GIR_BuildMI, /*InsnID*/0, /*Opcode*/GIMT_Encode2(AMDGPU::BUFFER_LOAD_USHORT_VBUFFER_OFFEN),
      GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/0, // DstI[vdata]
      GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/1, // vaddr
      GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/0, // srsrc
      GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/2, // soffset
      GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/3, // offset
      GIR_AddImm8, /*InsnID*/0, /*Imm*/0,
      GIR_AddImm8, /*InsnID*/0, /*Imm*/0,
      GIR_MergeMemOperands, /*InsnID*/0, /*NumInsns*/1, /*MergeInsnID's*/0,
      GIR_ConstrainSelectedInstOperands, /*InsnID*/0,
      GIR_EraseFromParent, /*InsnID*/0,
      // GIR_Coverage, 5381,
      GIR_Done,
    // Label 1791: @117525
    GIM_Try, /*On fail goto*//*Label 1792*/ GIMT_Encode4(117604), // Rule ID 3663 //
      GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasUnrestrictedSOffset),
      GIM_CheckMemorySizeEqualTo, /*MI*/0, /*MMO*/0, /*Size*/GIMT_Encode4(1),
      GIM_CheckMemoryAddressSpace, /*MI*/0, /*MMO*/0, /*NumAddrSpace*/3, /*AddrSpace*/1, /*AddrSpace*/4, /*AddrSpace*/6,
      GIM_CheckAtomicOrdering, /*MI*/0, /*Order*/(uint8_t)AtomicOrdering::NotAtomic,
      GIM_CheckRegBankForClass, /*MI*/0, /*Op*/0, /*RC*/GIMT_Encode2(AMDGPU::AV_32RegClassID),
      GIM_CheckPointerToAny, /*MI*/0, /*Op*/1, /*SizeInBits*/0,
      GIM_CheckComplexPattern, /*MI*/0, /*Op*/1, /*Renderer*/GIMT_Encode2(0), GIMT_Encode2(GICP_gi_mubuf_offset),
      // (ld:{ *:[i32] } (MUBUFOffset:{ *:[iPTR] } v4i32:{ *:[v4i32] }:$srsrc, i32:{ *:[i32] }:$soffset, i32:{ *:[i32] }:$offset))<<P:Predicate_unindexedload>><<P:Predicate_zextload>><<P:Predicate_zextloadi8>><<P:Predicate_zextloadi8_global>>  =>  (BUFFER_LOAD_UBYTE_OFFSET:{ *:[i32] } v4i32:{ *:[v4i32] }:$srsrc, i32:{ *:[i32] }:$soffset, i32:{ *:[i32] }:$offset)
      GIR_BuildMI, /*InsnID*/0, /*Opcode*/GIMT_Encode2(AMDGPU::BUFFER_LOAD_UBYTE_OFFSET),
      GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/0, // DstI[vdata]
      GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/0, // srsrc
      GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/1, // soffset
      GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/2, // offset
      GIR_AddImm8, /*InsnID*/0, /*Imm*/0,
      GIR_AddImm8, /*InsnID*/0, /*Imm*/0,
      GIR_MergeMemOperands, /*InsnID*/0, /*NumInsns*/1, /*MergeInsnID's*/0,
      GIR_ConstrainSelectedInstOperands, /*InsnID*/0,
      GIR_EraseFromParent, /*InsnID*/0,
      // GIR_Coverage, 3663,
      GIR_Done,
    // Label 1792: @117604
    GIM_Try, /*On fail goto*//*Label 1793*/ GIMT_Encode4(117680), // Rule ID 3665 //
      GIM_CheckMemorySizeEqualTo, /*MI*/0, /*MMO*/0, /*Size*/GIMT_Encode4(1),
      GIM_CheckMemoryAddressSpace, /*MI*/0, /*MMO*/0, /*NumAddrSpace*/3, /*AddrSpace*/1, /*AddrSpace*/4, /*AddrSpace*/6,
      GIM_CheckAtomicOrdering, /*MI*/0, /*Order*/(uint8_t)AtomicOrdering::NotAtomic,
      GIM_CheckRegBankForClass, /*MI*/0, /*Op*/0, /*RC*/GIMT_Encode2(AMDGPU::AV_32RegClassID),
      GIM_CheckPointerToAny, /*MI*/0, /*Op*/1, /*SizeInBits*/0,
      GIM_CheckComplexPattern, /*MI*/0, /*Op*/1, /*Renderer*/GIMT_Encode2(0), GIMT_Encode2(GICP_gi_mubuf_offset),
      // (ld:{ *:[i32] } (MUBUFOffset:{ *:[iPTR] } v4i32:{ *:[v4i32] }:$srsrc, i32:{ *:[i32] }:$soffset, i32:{ *:[i32] }:$offset))<<P:Predicate_unindexedload>><<P:Predicate_zextload>><<P:Predicate_zextloadi8>><<P:Predicate_zextloadi8_global>>  =>  (BUFFER_LOAD_UBYTE_VBUFFER_OFFSET:{ *:[i32] } v4i32:{ *:[v4i32] }:$srsrc, i32:{ *:[i32] }:$soffset, i32:{ *:[i32] }:$offset)
      GIR_BuildMI, /*InsnID*/0, /*Opcode*/GIMT_Encode2(AMDGPU::BUFFER_LOAD_UBYTE_VBUFFER_OFFSET),
      GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/0, // DstI[vdata]
      GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/0, // srsrc
      GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/1, // soffset
      GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/2, // offset
      GIR_AddImm8, /*InsnID*/0, /*Imm*/0,
      GIR_AddImm8, /*InsnID*/0, /*Imm*/0,
      GIR_MergeMemOperands, /*InsnID*/0, /*NumInsns*/1, /*MergeInsnID's*/0,
      GIR_ConstrainSelectedInstOperands, /*InsnID*/0,
      GIR_EraseFromParent, /*InsnID*/0,
      // GIR_Coverage, 3665,
      GIR_Done,
    // Label 1793: @117680
    GIM_Try, /*On fail goto*//*Label 1794*/ GIMT_Encode4(117759), // Rule ID 3675 //
      GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasUnrestrictedSOffset),
      GIM_CheckMemorySizeEqualTo, /*MI*/0, /*MMO*/0, /*Size*/GIMT_Encode4(2),
      GIM_CheckMemoryAddressSpace, /*MI*/0, /*MMO*/0, /*NumAddrSpace*/3, /*AddrSpace*/1, /*AddrSpace*/4, /*AddrSpace*/6,
      GIM_CheckAtomicOrdering, /*MI*/0, /*Order*/(uint8_t)AtomicOrdering::NotAtomic,
      GIM_CheckRegBankForClass, /*MI*/0, /*Op*/0, /*RC*/GIMT_Encode2(AMDGPU::AV_32RegClassID),
      GIM_CheckPointerToAny, /*MI*/0, /*Op*/1, /*SizeInBits*/0,
      GIM_CheckComplexPattern, /*MI*/0, /*Op*/1, /*Renderer*/GIMT_Encode2(0), GIMT_Encode2(GICP_gi_mubuf_offset),
      // (ld:{ *:[i32] } (MUBUFOffset:{ *:[iPTR] } v4i32:{ *:[v4i32] }:$srsrc, i32:{ *:[i32] }:$soffset, i32:{ *:[i32] }:$offset))<<P:Predicate_unindexedload>><<P:Predicate_zextload>><<P:Predicate_zextloadi16>><<P:Predicate_zextloadi16_global>>  =>  (BUFFER_LOAD_USHORT_OFFSET:{ *:[i32] } v4i32:{ *:[v4i32] }:$srsrc, i32:{ *:[i32] }:$soffset, i32:{ *:[i32] }:$offset)
      GIR_BuildMI, /*InsnID*/0, /*Opcode*/GIMT_Encode2(AMDGPU::BUFFER_LOAD_USHORT_OFFSET),
      GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/0, // DstI[vdata]
      GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/0, // srsrc
      GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/1, // soffset
      GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/2, // offset
      GIR_AddImm8, /*InsnID*/0, /*Imm*/0,
      GIR_AddImm8, /*InsnID*/0, /*Imm*/0,
      GIR_MergeMemOperands, /*InsnID*/0, /*NumInsns*/1, /*MergeInsnID's*/0,
      GIR_ConstrainSelectedInstOperands, /*InsnID*/0,
      GIR_EraseFromParent, /*InsnID*/0,
      // GIR_Coverage, 3675,
      GIR_Done,
    // Label 1794: @117759
    GIM_Try, /*On fail goto*//*Label 1795*/ GIMT_Encode4(117835), // Rule ID 3677 //
      GIM_CheckMemorySizeEqualTo, /*MI*/0, /*MMO*/0, /*Size*/GIMT_Encode4(2),
      GIM_CheckMemoryAddressSpace, /*MI*/0, /*MMO*/0, /*NumAddrSpace*/3, /*AddrSpace*/1, /*AddrSpace*/4, /*AddrSpace*/6,
      GIM_CheckAtomicOrdering, /*MI*/0, /*Order*/(uint8_t)AtomicOrdering::NotAtomic,
      GIM_CheckRegBankForClass, /*MI*/0, /*Op*/0, /*RC*/GIMT_Encode2(AMDGPU::AV_32RegClassID),
      GIM_CheckPointerToAny, /*MI*/0, /*Op*/1, /*SizeInBits*/0,
      GIM_CheckComplexPattern, /*MI*/0, /*Op*/1, /*Renderer*/GIMT_Encode2(0), GIMT_Encode2(GICP_gi_mubuf_offset),
      // (ld:{ *:[i32] } (MUBUFOffset:{ *:[iPTR] } v4i32:{ *:[v4i32] }:$srsrc, i32:{ *:[i32] }:$soffset, i32:{ *:[i32] }:$offset))<<P:Predicate_unindexedload>><<P:Predicate_zextload>><<P:Predicate_zextloadi16>><<P:Predicate_zextloadi16_global>>  =>  (BUFFER_LOAD_USHORT_VBUFFER_OFFSET:{ *:[i32] } v4i32:{ *:[v4i32] }:$srsrc, i32:{ *:[i32] }:$soffset, i32:{ *:[i32] }:$offset)
      GIR_BuildMI, /*InsnID*/0, /*Opcode*/GIMT_Encode2(AMDGPU::BUFFER_LOAD_USHORT_VBUFFER_OFFSET),
      GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/0, // DstI[vdata]
      GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/0, // srsrc
      GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/1, // soffset
      GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/2, // offset
      GIR_AddImm8, /*InsnID*/0, /*Imm*/0,
      GIR_AddImm8, /*InsnID*/0, /*Imm*/0,
      GIR_MergeMemOperands, /*InsnID*/0, /*NumInsns*/1, /*MergeInsnID's*/0,
      GIR_ConstrainSelectedInstOperands, /*InsnID*/0,
      GIR_EraseFromParent, /*InsnID*/0,
      // GIR_Coverage, 3677,
      GIR_Done,
    // Label 1795: @117835
    GIM_Try, /*On fail goto*//*Label 1796*/ GIMT_Encode4(117904), // Rule ID 6573 //
      GIM_CheckFeatures, GIMT_Encode2(GIFBS_LDSRequiresM0Init),
      GIM_CheckMemorySizeEqualTo, /*MI*/0, /*MMO*/0, /*Size*/GIMT_Encode4(1),
      GIM_CheckMemoryAddressSpace, /*MI*/0, /*MMO*/0, /*NumAddrSpace*/1, /*AddrSpace*/3,
      GIM_CheckAtomicOrdering, /*MI*/0, /*Order*/(uint8_t)AtomicOrdering::NotAtomic,
      GIM_CheckRegBankForClass, /*MI*/0, /*Op*/0, /*RC*/GIMT_Encode2(AMDGPU::AV_32RegClassID),
      GIM_CheckPointerToAny, /*MI*/0, /*Op*/1, /*SizeInBits*/0,
      GIM_CheckComplexPattern, /*MI*/0, /*Op*/1, /*Renderer*/GIMT_Encode2(0), GIMT_Encode2(GICP_gi_ds_1addr_1offset),
      // (AMDGPUld_glue:{ *:[i32] } (DS1Addr1Offset:{ *:[iPTR] } i32:{ *:[i32] }:$ptr, i32:{ *:[i32] }:$offset))<<P:Predicate_unindexedload_glue>><<P:Predicate_zextload_glue>><<P:Predicate_zextloadi8_glue>><<P:Predicate_zextloadi8_local_m0>>  =>  (DS_READ_U8:{ *:[i32] } ?:{ *:[i32] }:$ptr, offset:{ *:[i32] }:$offset, 0:{ *:[i1] })
      GIR_BuildMI, /*InsnID*/0, /*Opcode*/GIMT_Encode2(AMDGPU::DS_READ_U8),
      GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/0, // DstI[vdst]
      GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/0, // ptr
      GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/1, // offset
      GIR_AddImm8, /*InsnID*/0, /*Imm*/0,
      GIR_MergeMemOperands, /*InsnID*/0, /*NumInsns*/1, /*MergeInsnID's*/0,
      GIR_ConstrainSelectedInstOperands, /*InsnID*/0,
      GIR_EraseFromParent, /*InsnID*/0,
      // GIR_Coverage, 6573,
      GIR_Done,
    // Label 1796: @117904
    GIM_Try, /*On fail goto*//*Label 1797*/ GIMT_Encode4(117973), // Rule ID 6574 //
      GIM_CheckFeatures, GIMT_Encode2(GIFBS_NotLDSRequiresM0Init),
      GIM_CheckMemorySizeEqualTo, /*MI*/0, /*MMO*/0, /*Size*/GIMT_Encode4(1),
      GIM_CheckMemoryAddressSpace, /*MI*/0, /*MMO*/0, /*NumAddrSpace*/1, /*AddrSpace*/3,
      GIM_CheckAtomicOrdering, /*MI*/0, /*Order*/(uint8_t)AtomicOrdering::NotAtomic,
      GIM_CheckRegBankForClass, /*MI*/0, /*Op*/0, /*RC*/GIMT_Encode2(AMDGPU::AV_32RegClassID),
      GIM_CheckPointerToAny, /*MI*/0, /*Op*/1, /*SizeInBits*/0,
      GIM_CheckComplexPattern, /*MI*/0, /*Op*/1, /*Renderer*/GIMT_Encode2(0), GIMT_Encode2(GICP_gi_ds_1addr_1offset),
      // (ld:{ *:[i32] } (DS1Addr1Offset:{ *:[iPTR] } i32:{ *:[i32] }:$ptr, i32:{ *:[i32] }:$offset))<<P:Predicate_unindexedload>><<P:Predicate_zextload>><<P:Predicate_zextloadi8>><<P:Predicate_zextloadi8_local>>  =>  (DS_READ_U8_gfx9:{ *:[i32] } ?:{ *:[i32] }:$ptr, offset:{ *:[i32] }:$offset, 0:{ *:[i1] })
      GIR_BuildMI, /*InsnID*/0, /*Opcode*/GIMT_Encode2(AMDGPU::DS_READ_U8_gfx9),
      GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/0, // DstI[vdst]
      GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/0, // ptr
      GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/1, // offset
      GIR_AddImm8, /*InsnID*/0, /*Imm*/0,
      GIR_MergeMemOperands, /*InsnID*/0, /*NumInsns*/1, /*MergeInsnID's*/0,
      GIR_ConstrainSelectedInstOperands, /*InsnID*/0,
      GIR_EraseFromParent, /*InsnID*/0,
      // GIR_Coverage, 6574,
      GIR_Done,
    // Label 1797: @117973
    GIM_Try, /*On fail goto*//*Label 1798*/ GIMT_Encode4(118042), // Rule ID 6585 //
      GIM_CheckFeatures, GIMT_Encode2(GIFBS_LDSRequiresM0Init),
      GIM_CheckMemorySizeEqualTo, /*MI*/0, /*MMO*/0, /*Size*/GIMT_Encode4(2),
      GIM_CheckMemoryAddressSpace, /*MI*/0, /*MMO*/0, /*NumAddrSpace*/1, /*AddrSpace*/3,
      GIM_CheckAtomicOrdering, /*MI*/0, /*Order*/(uint8_t)AtomicOrdering::NotAtomic,
      GIM_CheckRegBankForClass, /*MI*/0, /*Op*/0, /*RC*/GIMT_Encode2(AMDGPU::AV_32RegClassID),
      GIM_CheckPointerToAny, /*MI*/0, /*Op*/1, /*SizeInBits*/0,
      GIM_CheckComplexPattern, /*MI*/0, /*Op*/1, /*Renderer*/GIMT_Encode2(0), GIMT_Encode2(GICP_gi_ds_1addr_1offset),
      // (AMDGPUld_glue:{ *:[i32] } (DS1Addr1Offset:{ *:[iPTR] } i32:{ *:[i32] }:$ptr, i32:{ *:[i32] }:$offset))<<P:Predicate_unindexedload_glue>><<P:Predicate_zextload_glue>><<P:Predicate_zextloadi16_glue>><<P:Predicate_zextloadi16_local_m0>>  =>  (DS_READ_U16:{ *:[i32] } ?:{ *:[i32] }:$ptr, offset:{ *:[i32] }:$offset, 0:{ *:[i1] })
      GIR_BuildMI, /*InsnID*/0, /*Opcode*/GIMT_Encode2(AMDGPU::DS_READ_U16),
      GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/0, // DstI[vdst]
      GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/0, // ptr
      GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/1, // offset
      GIR_AddImm8, /*InsnID*/0, /*Imm*/0,
      GIR_MergeMemOperands, /*InsnID*/0, /*NumInsns*/1, /*MergeInsnID's*/0,
      GIR_ConstrainSelectedInstOperands, /*InsnID*/0,
      GIR_EraseFromParent, /*InsnID*/0,
      // GIR_Coverage, 6585,
      GIR_Done,
    // Label 1798: @118042
    GIM_Try, /*On fail goto*//*Label 1799*/ GIMT_Encode4(118111), // Rule ID 6586 //
      GIM_CheckFeatures, GIMT_Encode2(GIFBS_NotLDSRequiresM0Init),
      GIM_CheckMemorySizeEqualTo, /*MI*/0, /*MMO*/0, /*Size*/GIMT_Encode4(2),
      GIM_CheckMemoryAddressSpace, /*MI*/0, /*MMO*/0, /*NumAddrSpace*/1, /*AddrSpace*/3,
      GIM_CheckAtomicOrdering, /*MI*/0, /*Order*/(uint8_t)AtomicOrdering::NotAtomic,
      GIM_CheckRegBankForClass, /*MI*/0, /*Op*/0, /*RC*/GIMT_Encode2(AMDGPU::AV_32RegClassID),
      GIM_CheckPointerToAny, /*MI*/0, /*Op*/1, /*SizeInBits*/0,
      GIM_CheckComplexPattern, /*MI*/0, /*Op*/1, /*Renderer*/GIMT_Encode2(0), GIMT_Encode2(GICP_gi_ds_1addr_1offset),
      // (ld:{ *:[i32] } (DS1Addr1Offset:{ *:[iPTR] } i32:{ *:[i32] }:$ptr, i32:{ *:[i32] }:$offset))<<P:Predicate_unindexedload>><<P:Predicate_zextload>><<P:Predicate_zextloadi16>><<P:Predicate_zextloadi16_local>>  =>  (DS_READ_U16_gfx9:{ *:[i32] } ?:{ *:[i32] }:$ptr, offset:{ *:[i32] }:$offset, 0:{ *:[i1] })
      GIR_BuildMI, /*InsnID*/0, /*Opcode*/GIMT_Encode2(AMDGPU::DS_READ_U16_gfx9),
      GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/0, // DstI[vdst]
      GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/0, // ptr
      GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/1, // offset
      GIR_AddImm8, /*InsnID*/0, /*Imm*/0,
      GIR_MergeMemOperands, /*InsnID*/0, /*NumInsns*/1, /*MergeInsnID's*/0,
      GIR_ConstrainSelectedInstOperands, /*InsnID*/0,
      GIR_EraseFromParent, /*InsnID*/0,
      // GIR_Coverage, 6586,
      GIR_Done,
    // Label 1799: @118111
    GIM_Try, /*On fail goto*//*Label 1800*/ GIMT_Encode4(118187), // Rule ID 2977 //
      GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasFlatGlobalInsts),
      GIM_CheckMemorySizeEqualTo, /*MI*/0, /*MMO*/0, /*Size*/GIMT_Encode4(1),
      GIM_CheckMemoryAddressSpace, /*MI*/0, /*MMO*/0, /*NumAddrSpace*/3, /*AddrSpace*/1, /*AddrSpace*/4, /*AddrSpace*/6,
      GIM_CheckAtomicOrdering, /*MI*/0, /*Order*/(uint8_t)AtomicOrdering::NotAtomic,
      GIM_CheckRegBankForClass, /*MI*/0, /*Op*/0, /*RC*/GIMT_Encode2(AMDGPU::AV_32RegClassID),
      GIM_CheckPointerToAny, /*MI*/0, /*Op*/1, /*SizeInBits*/0,
      GIM_CheckComplexPattern, /*MI*/0, /*Op*/1, /*Renderer*/GIMT_Encode2(0), GIMT_Encode2(GICP_gi_global_saddr),
      // (ld:{ *:[i32] } (GlobalSAddr:{ *:[iPTR] } SReg_64:{ *:[i64] }:$saddr, VGPR_32:{ *:[i32] }:$voffset, i32:{ *:[i32] }:$offset))<<P:Predicate_unindexedload>><<P:Predicate_zextload>><<P:Predicate_zextloadi8>><<P:Predicate_zextloadi8_global>>  =>  (GLOBAL_LOAD_UBYTE_SADDR:{ *:[i32] } ?:{ *:[i64] }:$saddr, ?:{ *:[i32] }:$voffset, ?:{ *:[i32] }:$offset, 0:{ *:[i32] })
      GIR_BuildMI, /*InsnID*/0, /*Opcode*/GIMT_Encode2(AMDGPU::GLOBAL_LOAD_UBYTE_SADDR),
      GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/0, // DstI[vdst]
      GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/0, // saddr
      GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/1, // voffset
      GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/2, // offset
      GIR_AddImm8, /*InsnID*/0, /*Imm*/0,
      GIR_MergeMemOperands, /*InsnID*/0, /*NumInsns*/1, /*MergeInsnID's*/0,
      GIR_ConstrainSelectedInstOperands, /*InsnID*/0,
      GIR_EraseFromParent, /*InsnID*/0,
      // GIR_Coverage, 2977,
      GIR_Done,
    // Label 1800: @118187
    GIM_Try, /*On fail goto*//*Label 1801*/ GIMT_Encode4(118263), // Rule ID 2989 //
      GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasFlatGlobalInsts),
      GIM_CheckMemorySizeEqualTo, /*MI*/0, /*MMO*/0, /*Size*/GIMT_Encode4(2),
      GIM_CheckMemoryAddressSpace, /*MI*/0, /*MMO*/0, /*NumAddrSpace*/3, /*AddrSpace*/1, /*AddrSpace*/4, /*AddrSpace*/6,
      GIM_CheckAtomicOrdering, /*MI*/0, /*Order*/(uint8_t)AtomicOrdering::NotAtomic,
      GIM_CheckRegBankForClass, /*MI*/0, /*Op*/0, /*RC*/GIMT_Encode2(AMDGPU::AV_32RegClassID),
      GIM_CheckPointerToAny, /*MI*/0, /*Op*/1, /*SizeInBits*/0,
      GIM_CheckComplexPattern, /*MI*/0, /*Op*/1, /*Renderer*/GIMT_Encode2(0), GIMT_Encode2(GICP_gi_global_saddr),
      // (ld:{ *:[i32] } (GlobalSAddr:{ *:[iPTR] } SReg_64:{ *:[i64] }:$saddr, VGPR_32:{ *:[i32] }:$voffset, i32:{ *:[i32] }:$offset))<<P:Predicate_unindexedload>><<P:Predicate_zextload>><<P:Predicate_zextloadi16>><<P:Predicate_zextloadi16_global>>  =>  (GLOBAL_LOAD_USHORT_SADDR:{ *:[i32] } ?:{ *:[i64] }:$saddr, ?:{ *:[i32] }:$voffset, ?:{ *:[i32] }:$offset, 0:{ *:[i32] })
      GIR_BuildMI, /*InsnID*/0, /*Opcode*/GIMT_Encode2(AMDGPU::GLOBAL_LOAD_USHORT_SADDR),
      GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/0, // DstI[vdst]
      GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/0, // saddr
      GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/1, // voffset
      GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/2, // offset
      GIR_AddImm8, /*InsnID*/0, /*Imm*/0,
      GIR_MergeMemOperands, /*InsnID*/0, /*NumInsns*/1, /*MergeInsnID's*/0,
      GIR_ConstrainSelectedInstOperands, /*InsnID*/0,
      GIR_EraseFromParent, /*InsnID*/0,
      // GIR_Coverage, 2989,
      GIR_Done,
    // Label 1801: @118263
    GIM_Try, /*On fail goto*//*Label 1802*/ GIMT_Encode4(118334), // Rule ID 2976 //
      GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasFlatGlobalInsts),
      GIM_CheckMemorySizeEqualTo, /*MI*/0, /*MMO*/0, /*Size*/GIMT_Encode4(1),
      GIM_CheckMemoryAddressSpace, /*MI*/0, /*MMO*/0, /*NumAddrSpace*/3, /*AddrSpace*/1, /*AddrSpace*/4, /*AddrSpace*/6,
      GIM_CheckAtomicOrdering, /*MI*/0, /*Order*/(uint8_t)AtomicOrdering::NotAtomic,
      GIM_CheckRegBankForClass, /*MI*/0, /*Op*/0, /*RC*/GIMT_Encode2(AMDGPU::AV_32RegClassID),
      GIM_CheckPointerToAny, /*MI*/0, /*Op*/1, /*SizeInBits*/0,
      GIM_CheckComplexPattern, /*MI*/0, /*Op*/1, /*Renderer*/GIMT_Encode2(0), GIMT_Encode2(GICP_gi_global_offset),
      // (ld:{ *:[i32] } (GlobalOffset:{ *:[iPTR] } VReg_64:{ *:[i64] }:$vaddr, i32:{ *:[i32] }:$offset))<<P:Predicate_unindexedload>><<P:Predicate_zextload>><<P:Predicate_zextloadi8>><<P:Predicate_zextloadi8_global>>  =>  (GLOBAL_LOAD_UBYTE:{ *:[i32] } ?:{ *:[i64] }:$vaddr, ?:{ *:[i32] }:$offset)
      GIR_BuildMI, /*InsnID*/0, /*Opcode*/GIMT_Encode2(AMDGPU::GLOBAL_LOAD_UBYTE),
      GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/0, // DstI[vdst]
      GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/0, // vaddr
      GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/1, // offset
      GIR_AddImm8, /*InsnID*/0, /*Imm*/0,
      GIR_MergeMemOperands, /*InsnID*/0, /*NumInsns*/1, /*MergeInsnID's*/0,
      GIR_ConstrainSelectedInstOperands, /*InsnID*/0,
      GIR_EraseFromParent, /*InsnID*/0,
      // GIR_Coverage, 2976,
      GIR_Done,
    // Label 1802: @118334
    GIM_Try, /*On fail goto*//*Label 1803*/ GIMT_Encode4(118405), // Rule ID 2988 //
      GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasFlatGlobalInsts),
      GIM_CheckMemorySizeEqualTo, /*MI*/0, /*MMO*/0, /*Size*/GIMT_Encode4(2),
      GIM_CheckMemoryAddressSpace, /*MI*/0, /*MMO*/0, /*NumAddrSpace*/3, /*AddrSpace*/1, /*AddrSpace*/4, /*AddrSpace*/6,
      GIM_CheckAtomicOrdering, /*MI*/0, /*Order*/(uint8_t)AtomicOrdering::NotAtomic,
      GIM_CheckRegBankForClass, /*MI*/0, /*Op*/0, /*RC*/GIMT_Encode2(AMDGPU::AV_32RegClassID),
      GIM_CheckPointerToAny, /*MI*/0, /*Op*/1, /*SizeInBits*/0,
      GIM_CheckComplexPattern, /*MI*/0, /*Op*/1, /*Renderer*/GIMT_Encode2(0), GIMT_Encode2(GICP_gi_global_offset),
      // (ld:{ *:[i32] } (GlobalOffset:{ *:[iPTR] } VReg_64:{ *:[i64] }:$vaddr, i32:{ *:[i32] }:$offset))<<P:Predicate_unindexedload>><<P:Predicate_zextload>><<P:Predicate_zextloadi16>><<P:Predicate_zextloadi16_global>>  =>  (GLOBAL_LOAD_USHORT:{ *:[i32] } ?:{ *:[i64] }:$vaddr, ?:{ *:[i32] }:$offset)
      GIR_BuildMI, /*InsnID*/0, /*Opcode*/GIMT_Encode2(AMDGPU::GLOBAL_LOAD_USHORT),
      GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/0, // DstI[vdst]
      GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/0, // vaddr
      GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/1, // offset
      GIR_AddImm8, /*InsnID*/0, /*Imm*/0,
      GIR_MergeMemOperands, /*InsnID*/0, /*NumInsns*/1, /*MergeInsnID's*/0,
      GIR_ConstrainSelectedInstOperands, /*InsnID*/0,
      GIR_EraseFromParent, /*InsnID*/0,
      // GIR_Coverage, 2988,
      GIR_Done,
    // Label 1803: @118405
    GIM_Try, /*On fail goto*//*Label 1804*/ GIMT_Encode4(118477), // Rule ID 2756 //
      GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasFlatAddressSpace),
      GIM_CheckMemorySizeEqualTo, /*MI*/0, /*MMO*/0, /*Size*/GIMT_Encode4(1),
      GIM_CheckMemoryAddressSpace, /*MI*/0, /*MMO*/0, /*NumAddrSpace*/4, /*AddrSpace*/0, /*AddrSpace*/1, /*AddrSpace*/4, /*AddrSpace*/6,
      GIM_CheckAtomicOrdering, /*MI*/0, /*Order*/(uint8_t)AtomicOrdering::NotAtomic,
      GIM_CheckRegBankForClass, /*MI*/0, /*Op*/0, /*RC*/GIMT_Encode2(AMDGPU::AV_32RegClassID),
      GIM_CheckPointerToAny, /*MI*/0, /*Op*/1, /*SizeInBits*/0,
      GIM_CheckComplexPattern, /*MI*/0, /*Op*/1, /*Renderer*/GIMT_Encode2(0), GIMT_Encode2(GICP_gi_flat_offset),
      // (ld:{ *:[i32] } (FlatOffset:{ *:[iPTR] } i64:{ *:[i64] }:$vaddr, i32:{ *:[i32] }:$offset))<<P:Predicate_unindexedload>><<P:Predicate_zextload>><<P:Predicate_zextloadi8>><<P:Predicate_zextloadi8_flat>>  =>  (FLAT_LOAD_UBYTE:{ *:[i32] } ?:{ *:[i64] }:$vaddr, ?:{ *:[i32] }:$offset)
      GIR_BuildMI, /*InsnID*/0, /*Opcode*/GIMT_Encode2(AMDGPU::FLAT_LOAD_UBYTE),
      GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/0, // DstI[vdst]
      GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/0, // vaddr
      GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/1, // offset
      GIR_AddImm8, /*InsnID*/0, /*Imm*/0,
      GIR_MergeMemOperands, /*InsnID*/0, /*NumInsns*/1, /*MergeInsnID's*/0,
      GIR_ConstrainSelectedInstOperands, /*InsnID*/0,
      GIR_EraseFromParent, /*InsnID*/0,
      // GIR_Coverage, 2756,
      GIR_Done,
    // Label 1804: @118477
    GIM_Try, /*On fail goto*//*Label 1805*/ GIMT_Encode4(118549), // Rule ID 2762 //
      GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasFlatAddressSpace),
      GIM_CheckMemorySizeEqualTo, /*MI*/0, /*MMO*/0, /*Size*/GIMT_Encode4(2),
      GIM_CheckMemoryAddressSpace, /*MI*/0, /*MMO*/0, /*NumAddrSpace*/4, /*AddrSpace*/0, /*AddrSpace*/1, /*AddrSpace*/4, /*AddrSpace*/6,
      GIM_CheckAtomicOrdering, /*MI*/0, /*Order*/(uint8_t)AtomicOrdering::NotAtomic,
      GIM_CheckRegBankForClass, /*MI*/0, /*Op*/0, /*RC*/GIMT_Encode2(AMDGPU::AV_32RegClassID),
      GIM_CheckPointerToAny, /*MI*/0, /*Op*/1, /*SizeInBits*/0,
      GIM_CheckComplexPattern, /*MI*/0, /*Op*/1, /*Renderer*/GIMT_Encode2(0), GIMT_Encode2(GICP_gi_flat_offset),
      // (ld:{ *:[i32] } (FlatOffset:{ *:[iPTR] } i64:{ *:[i64] }:$vaddr, i32:{ *:[i32] }:$offset))<<P:Predicate_unindexedload>><<P:Predicate_zextload>><<P:Predicate_zextloadi16>><<P:Predicate_zextloadi16_flat>>  =>  (FLAT_LOAD_USHORT:{ *:[i32] } ?:{ *:[i64] }:$vaddr, ?:{ *:[i32] }:$offset)
      GIR_BuildMI, /*InsnID*/0, /*Opcode*/GIMT_Encode2(AMDGPU::FLAT_LOAD_USHORT),
      GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/0, // DstI[vdst]
      GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/0, // vaddr
      GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/1, // offset
      GIR_AddImm8, /*InsnID*/0, /*Imm*/0,
      GIR_MergeMemOperands, /*InsnID*/0, /*NumInsns*/1, /*MergeInsnID's*/0,
      GIR_ConstrainSelectedInstOperands, /*InsnID*/0,
      GIR_EraseFromParent, /*InsnID*/0,
      // GIR_Coverage, 2762,
      GIR_Done,
    // Label 1805: @118549
    GIM_Reject,
    // Label 1746: @118550
    GIM_Reject,
    // Label 15: @118551
    GIM_SwitchType, /*MI*/0, /*Op*/0, /*[*/GIMT_Encode2(0), GIMT_Encode2(23), /*)*//*default:*//*Label 1823*/ GIMT_Encode4(157752),
    /*GILLT_p0s64*//*Label 1806*/ GIMT_Encode4(118654),
    /*GILLT_p1s64*//*Label 1807*/ GIMT_Encode4(119778),
    /*GILLT_p2s32*//*Label 1808*/ GIMT_Encode4(120902),
    /*GILLT_p3s32*//*Label 1809*/ GIMT_Encode4(121908),
    /*GILLT_p4s64*//*Label 1810*/ GIMT_Encode4(122914),
    /*GILLT_p5s32*//*Label 1811*/ GIMT_Encode4(124038),
    /*GILLT_p6s32*//*Label 1812*/ GIMT_Encode4(125044), GIMT_Encode4(0),
    /*GILLT_s16*//*Label 1813*/ GIMT_Encode4(126050),
    /*GILLT_s32*//*Label 1814*/ GIMT_Encode4(128743),
    /*GILLT_s64*//*Label 1815*/ GIMT_Encode4(136425),
    /*GILLT_v2s16*//*Label 1816*/ GIMT_Encode4(139075),
    /*GILLT_v2s32*//*Label 1817*/ GIMT_Encode4(142091),
    /*GILLT_v2s64*//*Label 1818*/ GIMT_Encode4(144608),
    /*GILLT_v3s32*//*Label 1819*/ GIMT_Encode4(146855), GIMT_Encode4(0),
    /*GILLT_v4s16*//*Label 1820*/ GIMT_Encode4(148495),
    /*GILLT_v4s32*//*Label 1821*/ GIMT_Encode4(151865), GIMT_Encode4(0), GIMT_Encode4(0), GIMT_Encode4(0), GIMT_Encode4(0),
    /*GILLT_v8s16*//*Label 1822*/ GIMT_Encode4(154382),
    // Label 1806: @118654
    GIM_Try, /*On fail goto*//*Label 1824*/ GIMT_Encode4(118724), // Rule ID 6845 //
      GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasUnalignedAccessMode_LDSRequiresM0Init),
      GIM_CheckMemorySizeEqualToLLT, /*MI*/0, /*MMO*/0, /*OpIdx*/0,
      GIM_CheckMemoryAddressSpace, /*MI*/0, /*MMO*/0, /*NumAddrSpace*/1, /*AddrSpace*/3,
      GIM_CheckMemoryAddressSpace, /*MI*/0, /*MMO*/0, /*NumAddrSpace*/1, /*AddrSpace*/3,
      GIM_CheckAtomicOrdering, /*MI*/0, /*Order*/(uint8_t)AtomicOrdering::NotAtomic,
      GIM_CheckPointerToAny, /*MI*/0, /*Op*/1, /*SizeInBits*/0,
      GIM_CheckCxxInsnPredicate, /*MI*/0, /*FnId*/GIMT_Encode2(GICXXPred_MI_Predicate_store_align_less_than_4_local_m0),
      GIM_CheckComplexPattern, /*MI*/0, /*Op*/1, /*Renderer*/GIMT_Encode2(0), GIMT_Encode2(GICP_gi_ds_1addr_1offset),
      // (AMDGPUst_glue p0:{ *:[i64] }:$value, (DS1Addr1Offset:{ *:[iPTR] } i32:{ *:[i32] }:$ptr, i32:{ *:[i32] }:$offset))<<P:Predicate_unindexedstore_glue>><<P:Predicate_store_glue>><<P:Predicate_store_local_m0>><<P:Predicate_store_align_less_than_4_local_m0>>  =>  (DS_WRITE_B64 ?:{ *:[i32] }:$ptr, anonymous_15036:{ *:[i64] }:$value, offset:{ *:[i32] }:$offset, 0:{ *:[i1] })
      GIR_BuildMI, /*InsnID*/0, /*Opcode*/GIMT_Encode2(AMDGPU::DS_WRITE_B64),
      GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/0, // ptr
      GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/0, // value
      GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/1, // offset
      GIR_AddImm8, /*InsnID*/0, /*Imm*/0,
      GIR_MergeMemOperands, /*InsnID*/0, /*NumInsns*/1, /*MergeInsnID's*/0,
      GIR_ConstrainSelectedInstOperands, /*InsnID*/0,
      GIR_EraseFromParent, /*InsnID*/0,
      // GIR_Coverage, 6845,
      GIR_Done,
    // Label 1824: @118724
    GIM_Try, /*On fail goto*//*Label 1825*/ GIMT_Encode4(118789), // Rule ID 6769 //
      GIM_CheckFeatures, GIMT_Encode2(GIFBS_LDSRequiresM0Init),
      GIM_CheckMemorySizeEqualToLLT, /*MI*/0, /*MMO*/0, /*OpIdx*/0,
      GIM_CheckMemoryAddressSpace, /*MI*/0, /*MMO*/0, /*NumAddrSpace*/1, /*AddrSpace*/3,
      GIM_CheckMemoryAlignment, /*MI*/0, /*MMO*/0, /*MinAlign*/8,
      GIM_CheckAtomicOrdering, /*MI*/0, /*Order*/(uint8_t)AtomicOrdering::NotAtomic,
      GIM_CheckPointerToAny, /*MI*/0, /*Op*/1, /*SizeInBits*/0,
      GIM_CheckComplexPattern, /*MI*/0, /*Op*/1, /*Renderer*/GIMT_Encode2(0), GIMT_Encode2(GICP_gi_ds_1addr_1offset),
      // (AMDGPUst_glue p0:{ *:[i64] }:$value, (DS1Addr1Offset:{ *:[iPTR] } i32:{ *:[i32] }:$ptr, i32:{ *:[i32] }:$offset))<<P:Predicate_unindexedstore_glue>><<P:Predicate_store_glue>><<P:Predicate_store_local_m0>><<P:Predicate_store_align8_local_m0>>  =>  (DS_WRITE_B64 ?:{ *:[i32] }:$ptr, anonymous_15036:{ *:[i64] }:$value, offset:{ *:[i32] }:$offset, 0:{ *:[i1] })
      GIR_BuildMI, /*InsnID*/0, /*Opcode*/GIMT_Encode2(AMDGPU::DS_WRITE_B64),
      GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/0, // ptr
      GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/0, // value
      GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/1, // offset
      GIR_AddImm8, /*InsnID*/0, /*Imm*/0,
      GIR_MergeMemOperands, /*InsnID*/0, /*NumInsns*/1, /*MergeInsnID's*/0,
      GIR_ConstrainSelectedInstOperands, /*InsnID*/0,
      GIR_EraseFromParent, /*InsnID*/0,
      // GIR_Coverage, 6769,
      GIR_Done,
    // Label 1825: @118789
    GIM_Try, /*On fail goto*//*Label 1826*/ GIMT_Encode4(118855), // Rule ID 6846 //
      GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasUnalignedAccessMode_NotLDSRequiresM0Init),
      GIM_CheckMemoryAddressSpace, /*MI*/0, /*MMO*/0, /*NumAddrSpace*/1, /*AddrSpace*/3,
      GIM_CheckMemoryAddressSpace, /*MI*/0, /*MMO*/0, /*NumAddrSpace*/1, /*AddrSpace*/3,
      GIM_CheckAtomicOrdering, /*MI*/0, /*Order*/(uint8_t)AtomicOrdering::NotAtomic,
      GIM_CheckPointerToAny, /*MI*/0, /*Op*/1, /*SizeInBits*/0,
      GIM_CheckCxxInsnPredicate, /*MI*/0, /*FnId*/GIMT_Encode2(GICXXPred_MI_Predicate_store_align_less_than_4_local),
      GIM_CheckComplexPattern, /*MI*/0, /*Op*/1, /*Renderer*/GIMT_Encode2(0), GIMT_Encode2(GICP_gi_ds_1addr_1offset),
      // (st p0:{ *:[i64] }:$value, (DS1Addr1Offset:{ *:[iPTR] } i32:{ *:[i32] }:$ptr, i32:{ *:[i32] }:$offset))<<P:Predicate_unindexedstore>><<P:Predicate_store_local>><<P:Predicate_store_align_less_than_4_local>>  =>  (DS_WRITE_B64_gfx9 ?:{ *:[i32] }:$ptr, anonymous_15036:{ *:[i64] }:$value, offset:{ *:[i32] }:$offset, 0:{ *:[i1] })
      GIR_BuildMI, /*InsnID*/0, /*Opcode*/GIMT_Encode2(AMDGPU::DS_WRITE_B64_gfx9),
      GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/0, // ptr
      GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/0, // value
      GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/1, // offset
      GIR_AddImm8, /*InsnID*/0, /*Imm*/0,
      GIR_MergeMemOperands, /*InsnID*/0, /*NumInsns*/1, /*MergeInsnID's*/0,
      GIR_ConstrainSelectedInstOperands, /*InsnID*/0,
      GIR_EraseFromParent, /*InsnID*/0,
      // GIR_Coverage, 6846,
      GIR_Done,
    // Label 1826: @118855
    GIM_Try, /*On fail goto*//*Label 1827*/ GIMT_Encode4(118916), // Rule ID 6770 //
      GIM_CheckFeatures, GIMT_Encode2(GIFBS_NotLDSRequiresM0Init),
      GIM_CheckMemoryAddressSpace, /*MI*/0, /*MMO*/0, /*NumAddrSpace*/1, /*AddrSpace*/3,
      GIM_CheckMemoryAlignment, /*MI*/0, /*MMO*/0, /*MinAlign*/8,
      GIM_CheckAtomicOrdering, /*MI*/0, /*Order*/(uint8_t)AtomicOrdering::NotAtomic,
      GIM_CheckPointerToAny, /*MI*/0, /*Op*/1, /*SizeInBits*/0,
      GIM_CheckComplexPattern, /*MI*/0, /*Op*/1, /*Renderer*/GIMT_Encode2(0), GIMT_Encode2(GICP_gi_ds_1addr_1offset),
      // (st p0:{ *:[i64] }:$value, (DS1Addr1Offset:{ *:[iPTR] } i32:{ *:[i32] }:$ptr, i32:{ *:[i32] }:$offset))<<P:Predicate_unindexedstore>><<P:Predicate_store_local>><<P:Predicate_store_align8_local>>  =>  (DS_WRITE_B64_gfx9 ?:{ *:[i32] }:$ptr, anonymous_15036:{ *:[i64] }:$value, offset:{ *:[i32] }:$offset, 0:{ *:[i1] })
      GIR_BuildMI, /*InsnID*/0, /*Opcode*/GIMT_Encode2(AMDGPU::DS_WRITE_B64_gfx9),
      GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/0, // ptr
      GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/0, // value
      GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/1, // offset
      GIR_AddImm8, /*InsnID*/0, /*Imm*/0,
      GIR_MergeMemOperands, /*InsnID*/0, /*NumInsns*/1, /*MergeInsnID's*/0,
      GIR_ConstrainSelectedInstOperands, /*InsnID*/0,
      GIR_EraseFromParent, /*InsnID*/0,
      // GIR_Coverage, 6770,
      GIR_Done,
    // Label 1827: @118916
    GIM_Try, /*On fail goto*//*Label 1828*/ GIMT_Encode4(118978), // Rule ID 3529 //
      GIM_CheckFeatures, GIMT_Encode2(GIFBS_EnableFlatScratch_HasFlatScratchInsts_HasFlatScratchSVSMode),
      GIM_CheckMemoryAddressSpace, /*MI*/0, /*MMO*/0, /*NumAddrSpace*/1, /*AddrSpace*/5,
      GIM_CheckAtomicOrdering, /*MI*/0, /*Order*/(uint8_t)AtomicOrdering::NotAtomic,
      GIM_CheckPointerToAny, /*MI*/0, /*Op*/1, /*SizeInBits*/0,
      GIM_CheckComplexPattern, /*MI*/0, /*Op*/1, /*Renderer*/GIMT_Encode2(0), GIMT_Encode2(GICP_gi_flat_scratch_svaddr),
      // (st p0:{ *:[i64] }:$data, (ScratchSVAddr:{ *:[iPTR] } VGPR_32:{ *:[i32] }:$vaddr, SGPR_32:{ *:[i32] }:$saddr, i32:{ *:[i32] }:$offset))<<P:Predicate_unindexedstore>><<P:Predicate_store_private>>  =>  (SCRATCH_STORE_DWORDX2_SVS anonymous_15036:{ *:[i64] }:$data, ?:{ *:[i32] }:$vaddr, ?:{ *:[i32] }:$saddr, ?:{ *:[i32] }:$offset)
      GIR_BuildMI, /*InsnID*/0, /*Opcode*/GIMT_Encode2(AMDGPU::SCRATCH_STORE_DWORDX2_SVS),
      GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/0, // data
      GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/0, // vaddr
      GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/1, // saddr
      GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/2, // offset
      GIR_AddImm8, /*InsnID*/0, /*Imm*/0,
      GIR_MergeMemOperands, /*InsnID*/0, /*NumInsns*/1, /*MergeInsnID's*/0,
      GIR_ConstrainSelectedInstOperands, /*InsnID*/0,
      GIR_EraseFromParent, /*InsnID*/0,
      // GIR_Coverage, 3529,
      GIR_Done,
    // Label 1828: @118978
    GIM_Try, /*On fail goto*//*Label 1829*/ GIMT_Encode4(119035), // Rule ID 3528 //
      GIM_CheckFeatures, GIMT_Encode2(GIFBS_EnableFlatScratch_HasFlatScratchInsts),
      GIM_CheckMemoryAddressSpace, /*MI*/0, /*MMO*/0, /*NumAddrSpace*/1, /*AddrSpace*/5,
      GIM_CheckAtomicOrdering, /*MI*/0, /*Order*/(uint8_t)AtomicOrdering::NotAtomic,
      GIM_CheckPointerToAny, /*MI*/0, /*Op*/1, /*SizeInBits*/0,
      GIM_CheckComplexPattern, /*MI*/0, /*Op*/1, /*Renderer*/GIMT_Encode2(0), GIMT_Encode2(GICP_gi_flat_scratch_saddr),
      // (st p0:{ *:[i64] }:$data, (ScratchSAddr:{ *:[iPTR] } SGPR_32:{ *:[i32] }:$saddr, i32:{ *:[i32] }:$offset))<<P:Predicate_unindexedstore>><<P:Predicate_store_private>>  =>  (SCRATCH_STORE_DWORDX2_SADDR anonymous_15036:{ *:[i64] }:$data, ?:{ *:[i32] }:$saddr, ?:{ *:[i32] }:$offset)
      GIR_BuildMI, /*InsnID*/0, /*Opcode*/GIMT_Encode2(AMDGPU::SCRATCH_STORE_DWORDX2_SADDR),
      GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/0, // data
      GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/0, // saddr
      GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/1, // offset
      GIR_AddImm8, /*InsnID*/0, /*Imm*/0,
      GIR_MergeMemOperands, /*InsnID*/0, /*NumInsns*/1, /*MergeInsnID's*/0,
      GIR_ConstrainSelectedInstOperands, /*InsnID*/0,
      GIR_EraseFromParent, /*InsnID*/0,
      // GIR_Coverage, 3528,
      GIR_Done,
    // Label 1829: @119035
    GIM_Try, /*On fail goto*//*Label 1830*/ GIMT_Encode4(119092), // Rule ID 3527 //
      GIM_CheckFeatures, GIMT_Encode2(GIFBS_EnableFlatScratch_HasFlatScratchInsts),
      GIM_CheckMemoryAddressSpace, /*MI*/0, /*MMO*/0, /*NumAddrSpace*/1, /*AddrSpace*/5,
      GIM_CheckAtomicOrdering, /*MI*/0, /*Order*/(uint8_t)AtomicOrdering::NotAtomic,
      GIM_CheckPointerToAny, /*MI*/0, /*Op*/1, /*SizeInBits*/0,
      GIM_CheckComplexPattern, /*MI*/0, /*Op*/1, /*Renderer*/GIMT_Encode2(0), GIMT_Encode2(GICP_gi_flat_scratch_offset),
      // (st p0:{ *:[i64] }:$data, (ScratchOffset:{ *:[iPTR] } VGPR_32:{ *:[i32] }:$vaddr, i32:{ *:[i32] }:$offset))<<P:Predicate_unindexedstore>><<P:Predicate_store_private>>  =>  (SCRATCH_STORE_DWORDX2 anonymous_15036:{ *:[i64] }:$data, ?:{ *:[i32] }:$vaddr, ?:{ *:[i32] }:$offset)
      GIR_BuildMI, /*InsnID*/0, /*Opcode*/GIMT_Encode2(AMDGPU::SCRATCH_STORE_DWORDX2),
      GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/0, // data
      GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/0, // vaddr
      GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/1, // offset
      GIR_AddImm8, /*InsnID*/0, /*Imm*/0,
      GIR_MergeMemOperands, /*InsnID*/0, /*NumInsns*/1, /*MergeInsnID's*/0,
      GIR_ConstrainSelectedInstOperands, /*InsnID*/0,
      GIR_EraseFromParent, /*InsnID*/0,
      // GIR_Coverage, 3527,
      GIR_Done,
    // Label 1830: @119092
    GIM_Try, /*On fail goto*//*Label 1831*/ GIMT_Encode4(119162), // Rule ID 3866 //
      GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasUnrestrictedSOffset),
      GIM_CheckMemoryAddressSpace, /*MI*/0, /*MMO*/0, /*NumAddrSpace*/1, /*AddrSpace*/1,
      GIM_CheckAtomicOrdering, /*MI*/0, /*Order*/(uint8_t)AtomicOrdering::NotAtomic,
      GIM_CheckPointerToAny, /*MI*/0, /*Op*/1, /*SizeInBits*/0,
      GIM_CheckComplexPattern, /*MI*/0, /*Op*/1, /*Renderer*/GIMT_Encode2(0), GIMT_Encode2(GICP_gi_mubuf_addr64),
      // (st p0:{ *:[i64] }:$vdata, (MUBUFAddr64:{ *:[iPTR] } v4i32:{ *:[v4i32] }:$srsrc, i64:{ *:[i64] }:$vaddr, i32:{ *:[i32] }:$soffset, i32:{ *:[i32] }:$offset))<<P:Predicate_unindexedstore>><<P:Predicate_store_global>>  =>  (BUFFER_STORE_DWORDX2_ADDR64 p0:{ *:[i64] }:$vdata, i64:{ *:[i64] }:$vaddr, v4i32:{ *:[v4i32] }:$srsrc, i32:{ *:[i32] }:$soffset, i32:{ *:[i32] }:$offset)
      GIR_BuildMI, /*InsnID*/0, /*Opcode*/GIMT_Encode2(AMDGPU::BUFFER_STORE_DWORDX2_ADDR64),
      GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/0, // vdata
      GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/1, // vaddr
      GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/0, // srsrc
      GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/2, // soffset
      GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/3, // offset
      GIR_AddImm8, /*InsnID*/0, /*Imm*/0,
      GIR_AddImm8, /*InsnID*/0, /*Imm*/0,
      GIR_MergeMemOperands, /*InsnID*/0, /*NumInsns*/1, /*MergeInsnID's*/0,
      GIR_ConstrainSelectedInstOperands, /*InsnID*/0,
      GIR_EraseFromParent, /*InsnID*/0,
      // GIR_Coverage, 3866,
      GIR_Done,
    // Label 1831: @119162
    GIM_Try, /*On fail goto*//*Label 1832*/ GIMT_Encode4(119229), // Rule ID 3868 //
      GIM_CheckMemoryAddressSpace, /*MI*/0, /*MMO*/0, /*NumAddrSpace*/1, /*AddrSpace*/1,
      GIM_CheckAtomicOrdering, /*MI*/0, /*Order*/(uint8_t)AtomicOrdering::NotAtomic,
      GIM_CheckPointerToAny, /*MI*/0, /*Op*/1, /*SizeInBits*/0,
      GIM_CheckComplexPattern, /*MI*/0, /*Op*/1, /*Renderer*/GIMT_Encode2(0), GIMT_Encode2(GICP_gi_mubuf_addr64),
      // (st p0:{ *:[i64] }:$vdata, (MUBUFAddr64:{ *:[iPTR] } v4i32:{ *:[v4i32] }:$srsrc, i64:{ *:[i64] }:$vaddr, i32:{ *:[i32] }:$soffset, i32:{ *:[i32] }:$offset))<<P:Predicate_unindexedstore>><<P:Predicate_store_global>>  =>  (BUFFER_STORE_DWORDX2_VBUFFER_ADDR64 p0:{ *:[i64] }:$vdata, i64:{ *:[i64] }:$vaddr, v4i32:{ *:[v4i32] }:$srsrc, i32:{ *:[i32] }:$soffset, i32:{ *:[i32] }:$offset)
      GIR_BuildMI, /*InsnID*/0, /*Opcode*/GIMT_Encode2(AMDGPU::BUFFER_STORE_DWORDX2_VBUFFER_ADDR64),
      GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/0, // vdata
      GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/1, // vaddr
      GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/0, // srsrc
      GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/2, // soffset
      GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/3, // offset
      GIR_AddImm8, /*InsnID*/0, /*Imm*/0,
      GIR_AddImm8, /*InsnID*/0, /*Imm*/0,
      GIR_MergeMemOperands, /*InsnID*/0, /*NumInsns*/1, /*MergeInsnID's*/0,
      GIR_ConstrainSelectedInstOperands, /*InsnID*/0,
      GIR_EraseFromParent, /*InsnID*/0,
      // GIR_Coverage, 3868,
      GIR_Done,
    // Label 1832: @119229
    GIM_Try, /*On fail goto*//*Label 1833*/ GIMT_Encode4(119353), // Rule ID 6704 //
      GIM_CheckFeatures, GIMT_Encode2(GIFBS_LDSRequiresM0Init_isGFX7Plus),
      GIM_CheckMemorySizeEqualToLLT, /*MI*/0, /*MMO*/0, /*OpIdx*/0,
      GIM_CheckMemoryAddressSpace, /*MI*/0, /*MMO*/0, /*NumAddrSpace*/1, /*AddrSpace*/3,
      GIM_CheckAtomicOrdering, /*MI*/0, /*Order*/(uint8_t)AtomicOrdering::NotAtomic,
      GIM_CheckPointerToAny, /*MI*/0, /*Op*/1, /*SizeInBits*/0,
      GIM_CheckComplexPattern, /*MI*/0, /*Op*/1, /*Renderer*/GIMT_Encode2(0), GIMT_Encode2(GICP_gi_ds_64bit_4byte_aligned),
      // (AMDGPUst_glue p0:{ *:[i64] }:$value, (DS64Bit4ByteAligned:{ *:[iPTR] } i32:{ *:[i32] }:$ptr, i8:{ *:[i8] }:$offset0, i8:{ *:[i8] }:$offset1))<<P:Predicate_unindexedstore_glue>><<P:Predicate_store_glue>><<P:Predicate_store_local_m0>>  =>  (DS_WRITE2_B32 ?:{ *:[i32] }:$ptr, (EXTRACT_SUBREG:{ *:[i32] } VReg_64:{ *:[i64] }:$value, sub0:{ *:[i32] }), (EXTRACT_SUBREG:{ *:[i32] } VReg_64:{ *:[i64] }:$value, sub1:{ *:[i32] }), ?:{ *:[i8] }:$offset0, ?:{ *:[i8] }:$offset1, 0:{ *:[i1] })
      GIR_MakeTempReg, /*TempRegID*/0, /*TypeID*/GILLT_s32,
      GIR_MakeTempReg, /*TempRegID*/1, /*TypeID*/GILLT_s32,
      GIR_BuildMI, /*InsnID*/2, /*Opcode*/GIMT_Encode2(TargetOpcode::COPY),
      GIR_AddTempRegister, /*InsnID*/2, /*TempRegID*/1, /*TempRegFlags*/GIMT_Encode2(RegState::Define),
      GIR_CopySubReg, /*NewInsnID*/2, /*OldInsnID*/0, /*OpIdx*/0, /*SubRegIdx*/GIMT_Encode2(11), // value
      GIR_ConstrainOperandRC, /*InsnID*/2, /*Op*/0, GIMT_Encode2(AMDGPU::VGPR_32RegClassID),
      GIR_ConstrainOperandRC, /*InsnID*/2, /*Op*/1, GIMT_Encode2(AMDGPU::VReg_64RegClassID),
      GIR_BuildMI, /*InsnID*/1, /*Opcode*/GIMT_Encode2(TargetOpcode::COPY),
      GIR_AddTempRegister, /*InsnID*/1, /*TempRegID*/0, /*TempRegFlags*/GIMT_Encode2(RegState::Define),
      GIR_CopySubReg, /*NewInsnID*/1, /*OldInsnID*/0, /*OpIdx*/0, /*SubRegIdx*/GIMT_Encode2(3), // value
      GIR_ConstrainOperandRC, /*InsnID*/1, /*Op*/0, GIMT_Encode2(AMDGPU::VGPR_32RegClassID),
      GIR_ConstrainOperandRC, /*InsnID*/1, /*Op*/1, GIMT_Encode2(AMDGPU::VReg_64RegClassID),
      GIR_BuildMI, /*InsnID*/0, /*Opcode*/GIMT_Encode2(AMDGPU::DS_WRITE2_B32),
      GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/0, // ptr
      GIR_AddSimpleTempRegister, /*InsnID*/0, /*TempRegID*/0,
      GIR_AddSimpleTempRegister, /*InsnID*/0, /*TempRegID*/1,
      GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/1, // offset0
      GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/2, // offset1
      GIR_AddImm8, /*InsnID*/0, /*Imm*/0,
      GIR_MergeMemOperands, /*InsnID*/0, /*NumInsns*/1, /*MergeInsnID's*/0,
      GIR_ConstrainSelectedInstOperands, /*InsnID*/0,
      GIR_EraseFromParent, /*InsnID*/0,
      // GIR_Coverage, 6704,
      GIR_Done,
    // Label 1833: @119353
    GIM_Try, /*On fail goto*//*Label 1834*/ GIMT_Encode4(119418), // Rule ID 3865 //
      GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasUnrestrictedSOffset),
      GIM_CheckMemoryAddressSpace, /*MI*/0, /*MMO*/0, /*NumAddrSpace*/1, /*AddrSpace*/1,
      GIM_CheckAtomicOrdering, /*MI*/0, /*Order*/(uint8_t)AtomicOrdering::NotAtomic,
      GIM_CheckPointerToAny, /*MI*/0, /*Op*/1, /*SizeInBits*/0,
      GIM_CheckComplexPattern, /*MI*/0, /*Op*/1, /*Renderer*/GIMT_Encode2(0), GIMT_Encode2(GICP_gi_mubuf_offset),
      // (st p0:{ *:[i64] }:$vdata, (MUBUFOffset:{ *:[iPTR] } v4i32:{ *:[v4i32] }:$srsrc, i32:{ *:[i32] }:$soffset, i32:{ *:[i32] }:$offset))<<P:Predicate_unindexedstore>><<P:Predicate_store_global>>  =>  (BUFFER_STORE_DWORDX2_OFFSET p0:{ *:[i64] }:$vdata, v4i32:{ *:[v4i32] }:$srsrc, i32:{ *:[i32] }:$soffset, i32:{ *:[i32] }:$offset)
      GIR_BuildMI, /*InsnID*/0, /*Opcode*/GIMT_Encode2(AMDGPU::BUFFER_STORE_DWORDX2_OFFSET),
      GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/0, // vdata
      GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/0, // srsrc
      GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/1, // soffset
      GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/2, // offset
      GIR_AddImm8, /*InsnID*/0, /*Imm*/0,
      GIR_AddImm8, /*InsnID*/0, /*Imm*/0,
      GIR_MergeMemOperands, /*InsnID*/0, /*NumInsns*/1, /*MergeInsnID's*/0,
      GIR_ConstrainSelectedInstOperands, /*InsnID*/0,
      GIR_EraseFromParent, /*InsnID*/0,
      // GIR_Coverage, 3865,
      GIR_Done,
    // Label 1834: @119418
    GIM_Try, /*On fail goto*//*Label 1835*/ GIMT_Encode4(119480), // Rule ID 3867 //
      GIM_CheckMemoryAddressSpace, /*MI*/0, /*MMO*/0, /*NumAddrSpace*/1, /*AddrSpace*/1,
      GIM_CheckAtomicOrdering, /*MI*/0, /*Order*/(uint8_t)AtomicOrdering::NotAtomic,
      GIM_CheckPointerToAny, /*MI*/0, /*Op*/1, /*SizeInBits*/0,
      GIM_CheckComplexPattern, /*MI*/0, /*Op*/1, /*Renderer*/GIMT_Encode2(0), GIMT_Encode2(GICP_gi_mubuf_offset),
      // (st p0:{ *:[i64] }:$vdata, (MUBUFOffset:{ *:[iPTR] } v4i32:{ *:[v4i32] }:$srsrc, i32:{ *:[i32] }:$soffset, i32:{ *:[i32] }:$offset))<<P:Predicate_unindexedstore>><<P:Predicate_store_global>>  =>  (BUFFER_STORE_DWORDX2_VBUFFER_OFFSET p0:{ *:[i64] }:$vdata, v4i32:{ *:[v4i32] }:$srsrc, i32:{ *:[i32] }:$soffset, i32:{ *:[i32] }:$offset)
      GIR_BuildMI, /*InsnID*/0, /*Opcode*/GIMT_Encode2(AMDGPU::BUFFER_STORE_DWORDX2_VBUFFER_OFFSET),
      GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/0, // vdata
      GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/0, // srsrc
      GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/1, // soffset
      GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/2, // offset
      GIR_AddImm8, /*InsnID*/0, /*Imm*/0,
      GIR_AddImm8, /*InsnID*/0, /*Imm*/0,
      GIR_MergeMemOperands, /*InsnID*/0, /*NumInsns*/1, /*MergeInsnID's*/0,
      GIR_ConstrainSelectedInstOperands, /*InsnID*/0,
      GIR_EraseFromParent, /*InsnID*/0,
      // GIR_Coverage, 3867,
      GIR_Done,
    // Label 1835: @119480
    GIM_Try, /*On fail goto*//*Label 1836*/ GIMT_Encode4(119600), // Rule ID 6706 //
      GIM_CheckFeatures, GIMT_Encode2(GIFBS_NotLDSRequiresM0Init),
      GIM_CheckMemoryAddressSpace, /*MI*/0, /*MMO*/0, /*NumAddrSpace*/1, /*AddrSpace*/3,
      GIM_CheckAtomicOrdering, /*MI*/0, /*Order*/(uint8_t)AtomicOrdering::NotAtomic,
      GIM_CheckPointerToAny, /*MI*/0, /*Op*/1, /*SizeInBits*/0,
      GIM_CheckComplexPattern, /*MI*/0, /*Op*/1, /*Renderer*/GIMT_Encode2(0), GIMT_Encode2(GICP_gi_ds_64bit_4byte_aligned),
      // (st p0:{ *:[i64] }:$value, (DS64Bit4ByteAligned:{ *:[iPTR] } i32:{ *:[i32] }:$ptr, i8:{ *:[i8] }:$offset0, i8:{ *:[i8] }:$offset1))<<P:Predicate_unindexedstore>><<P:Predicate_store_local>>  =>  (DS_WRITE2_B32_gfx9 ?:{ *:[i32] }:$ptr, (EXTRACT_SUBREG:{ *:[i32] } VReg_64:{ *:[i64] }:$value, sub0:{ *:[i32] }), (EXTRACT_SUBREG:{ *:[i32] } VReg_64:{ *:[i64] }:$value, sub1:{ *:[i32] }), ?:{ *:[i8] }:$offset0, ?:{ *:[i8] }:$offset1, 0:{ *:[i1] })
      GIR_MakeTempReg, /*TempRegID*/0, /*TypeID*/GILLT_s32,
      GIR_MakeTempReg, /*TempRegID*/1, /*TypeID*/GILLT_s32,
      GIR_BuildMI, /*InsnID*/2, /*Opcode*/GIMT_Encode2(TargetOpcode::COPY),
      GIR_AddTempRegister, /*InsnID*/2, /*TempRegID*/1, /*TempRegFlags*/GIMT_Encode2(RegState::Define),
      GIR_CopySubReg, /*NewInsnID*/2, /*OldInsnID*/0, /*OpIdx*/0, /*SubRegIdx*/GIMT_Encode2(11), // value
      GIR_ConstrainOperandRC, /*InsnID*/2, /*Op*/0, GIMT_Encode2(AMDGPU::VGPR_32RegClassID),
      GIR_ConstrainOperandRC, /*InsnID*/2, /*Op*/1, GIMT_Encode2(AMDGPU::VReg_64RegClassID),
      GIR_BuildMI, /*InsnID*/1, /*Opcode*/GIMT_Encode2(TargetOpcode::COPY),
      GIR_AddTempRegister, /*InsnID*/1, /*TempRegID*/0, /*TempRegFlags*/GIMT_Encode2(RegState::Define),
      GIR_CopySubReg, /*NewInsnID*/1, /*OldInsnID*/0, /*OpIdx*/0, /*SubRegIdx*/GIMT_Encode2(3), // value
      GIR_ConstrainOperandRC, /*InsnID*/1, /*Op*/0, GIMT_Encode2(AMDGPU::VGPR_32RegClassID),
      GIR_ConstrainOperandRC, /*InsnID*/1, /*Op*/1, GIMT_Encode2(AMDGPU::VReg_64RegClassID),
      GIR_BuildMI, /*InsnID*/0, /*Opcode*/GIMT_Encode2(AMDGPU::DS_WRITE2_B32_gfx9),
      GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/0, // ptr
      GIR_AddSimpleTempRegister, /*InsnID*/0, /*TempRegID*/0,
      GIR_AddSimpleTempRegister, /*InsnID*/0, /*TempRegID*/1,
      GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/1, // offset0
      GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/2, // offset1
      GIR_AddImm8, /*InsnID*/0, /*Imm*/0,
      GIR_MergeMemOperands, /*InsnID*/0, /*NumInsns*/1, /*MergeInsnID's*/0,
      GIR_ConstrainSelectedInstOperands, /*InsnID*/0,
      GIR_EraseFromParent, /*InsnID*/0,
      // GIR_Coverage, 6706,
      GIR_Done,
    // Label 1836: @119600
    GIM_Try, /*On fail goto*//*Label 1837*/ GIMT_Encode4(119662), // Rule ID 3059 //
      GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasFlatGlobalInsts),
      GIM_CheckMemoryAddressSpace, /*MI*/0, /*MMO*/0, /*NumAddrSpace*/1, /*AddrSpace*/1,
      GIM_CheckAtomicOrdering, /*MI*/0, /*Order*/(uint8_t)AtomicOrdering::NotAtomic,
      GIM_CheckPointerToAny, /*MI*/0, /*Op*/1, /*SizeInBits*/0,
      GIM_CheckComplexPattern, /*MI*/0, /*Op*/1, /*Renderer*/GIMT_Encode2(0), GIMT_Encode2(GICP_gi_global_saddr),
      // (st p0:{ *:[i64] }:$data, (GlobalSAddr:{ *:[iPTR] } SReg_64:{ *:[i64] }:$saddr, VGPR_32:{ *:[i32] }:$voffset, i32:{ *:[i32] }:$offset))<<P:Predicate_unindexedstore>><<P:Predicate_store_global>>  =>  (GLOBAL_STORE_DWORDX2_SADDR ?:{ *:[i32] }:$voffset, anonymous_15036:{ *:[i64] }:$data, ?:{ *:[i64] }:$saddr, ?:{ *:[i32] }:$offset)
      GIR_BuildMI, /*InsnID*/0, /*Opcode*/GIMT_Encode2(AMDGPU::GLOBAL_STORE_DWORDX2_SADDR),
      GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/1, // voffset
      GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/0, // data
      GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/0, // saddr
      GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/2, // offset
      GIR_AddImm8, /*InsnID*/0, /*Imm*/0,
      GIR_MergeMemOperands, /*InsnID*/0, /*NumInsns*/1, /*MergeInsnID's*/0,
      GIR_ConstrainSelectedInstOperands, /*InsnID*/0,
      GIR_EraseFromParent, /*InsnID*/0,
      // GIR_Coverage, 3059,
      GIR_Done,
    // Label 1837: @119662
    GIM_Try, /*On fail goto*//*Label 1838*/ GIMT_Encode4(119719), // Rule ID 3058 //
      GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasFlatGlobalInsts),
      GIM_CheckMemoryAddressSpace, /*MI*/0, /*MMO*/0, /*NumAddrSpace*/1, /*AddrSpace*/1,
      GIM_CheckAtomicOrdering, /*MI*/0, /*Order*/(uint8_t)AtomicOrdering::NotAtomic,
      GIM_CheckPointerToAny, /*MI*/0, /*Op*/1, /*SizeInBits*/0,
      GIM_CheckComplexPattern, /*MI*/0, /*Op*/1, /*Renderer*/GIMT_Encode2(0), GIMT_Encode2(GICP_gi_global_offset),
      // (st p0:{ *:[i64] }:$data, (GlobalOffset:{ *:[iPTR] } i64:{ *:[i64] }:$vaddr, i32:{ *:[i32] }:$offset))<<P:Predicate_unindexedstore>><<P:Predicate_store_global>>  =>  (GLOBAL_STORE_DWORDX2 ?:{ *:[i64] }:$vaddr, anonymous_15036:{ *:[i64] }:$data, ?:{ *:[i32] }:$offset)
      GIR_BuildMI, /*InsnID*/0, /*Opcode*/GIMT_Encode2(AMDGPU::GLOBAL_STORE_DWORDX2),
      GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/0, // vaddr
      GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/0, // data
      GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/1, // offset
      GIR_AddImm8, /*InsnID*/0, /*Imm*/0,
      GIR_MergeMemOperands, /*InsnID*/0, /*NumInsns*/1, /*MergeInsnID's*/0,
      GIR_ConstrainSelectedInstOperands, /*InsnID*/0,
      GIR_EraseFromParent, /*InsnID*/0,
      // GIR_Coverage, 3058,
      GIR_Done,
    // Label 1838: @119719
    GIM_Try, /*On fail goto*//*Label 1839*/ GIMT_Encode4(119777), // Rule ID 2802 //
      GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasFlatAddressSpace),
      GIM_CheckMemoryAddressSpace, /*MI*/0, /*MMO*/0, /*NumAddrSpace*/2, /*AddrSpace*/0, /*AddrSpace*/1,
      GIM_CheckAtomicOrdering, /*MI*/0, /*Order*/(uint8_t)AtomicOrdering::NotAtomic,
      GIM_CheckPointerToAny, /*MI*/0, /*Op*/1, /*SizeInBits*/0,
      GIM_CheckComplexPattern, /*MI*/0, /*Op*/1, /*Renderer*/GIMT_Encode2(0), GIMT_Encode2(GICP_gi_flat_offset),
      // (st p0:{ *:[i64] }:$data, (FlatOffset:{ *:[iPTR] } i64:{ *:[i64] }:$vaddr, i32:{ *:[i32] }:$offset))<<P:Predicate_unindexedstore>><<P:Predicate_store_flat>>  =>  (FLAT_STORE_DWORDX2 ?:{ *:[i64] }:$vaddr, anonymous_15036:{ *:[i64] }:$data, ?:{ *:[i32] }:$offset)
      GIR_BuildMI, /*InsnID*/0, /*Opcode*/GIMT_Encode2(AMDGPU::FLAT_STORE_DWORDX2),
      GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/0, // vaddr
      GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/0, // data
      GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/1, // offset
      GIR_AddImm8, /*InsnID*/0, /*Imm*/0,
      GIR_MergeMemOperands, /*InsnID*/0, /*NumInsns*/1, /*MergeInsnID's*/0,
      GIR_ConstrainSelectedInstOperands, /*InsnID*/0,
      GIR_EraseFromParent, /*InsnID*/0,
      // GIR_Coverage, 2802,
      GIR_Done,
    // Label 1839: @119777
    GIM_Reject,
    // Label 1807: @119778
    GIM_Try, /*On fail goto*//*Label 1840*/ GIMT_Encode4(119848), // Rule ID 6849 //
      GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasUnalignedAccessMode_LDSRequiresM0Init),
      GIM_CheckMemorySizeEqualToLLT, /*MI*/0, /*MMO*/0, /*OpIdx*/0,
      GIM_CheckMemoryAddressSpace, /*MI*/0, /*MMO*/0, /*NumAddrSpace*/1, /*AddrSpace*/3,
      GIM_CheckMemoryAddressSpace, /*MI*/0, /*MMO*/0, /*NumAddrSpace*/1, /*AddrSpace*/3,
      GIM_CheckAtomicOrdering, /*MI*/0, /*Order*/(uint8_t)AtomicOrdering::NotAtomic,
      GIM_CheckPointerToAny, /*MI*/0, /*Op*/1, /*SizeInBits*/0,
      GIM_CheckCxxInsnPredicate, /*MI*/0, /*FnId*/GIMT_Encode2(GICXXPred_MI_Predicate_store_align_less_than_4_local_m0),
      GIM_CheckComplexPattern, /*MI*/0, /*Op*/1, /*Renderer*/GIMT_Encode2(0), GIMT_Encode2(GICP_gi_ds_1addr_1offset),
      // (AMDGPUst_glue p1:{ *:[i64] }:$value, (DS1Addr1Offset:{ *:[iPTR] } i32:{ *:[i32] }:$ptr, i32:{ *:[i32] }:$offset))<<P:Predicate_unindexedstore_glue>><<P:Predicate_store_glue>><<P:Predicate_store_local_m0>><<P:Predicate_store_align_less_than_4_local_m0>>  =>  (DS_WRITE_B64 ?:{ *:[i32] }:$ptr, anonymous_15036:{ *:[i64] }:$value, offset:{ *:[i32] }:$offset, 0:{ *:[i1] })
      GIR_BuildMI, /*InsnID*/0, /*Opcode*/GIMT_Encode2(AMDGPU::DS_WRITE_B64),
      GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/0, // ptr
      GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/0, // value
      GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/1, // offset
      GIR_AddImm8, /*InsnID*/0, /*Imm*/0,
      GIR_MergeMemOperands, /*InsnID*/0, /*NumInsns*/1, /*MergeInsnID's*/0,
      GIR_ConstrainSelectedInstOperands, /*InsnID*/0,
      GIR_EraseFromParent, /*InsnID*/0,
      // GIR_Coverage, 6849,
      GIR_Done,
    // Label 1840: @119848
    GIM_Try, /*On fail goto*//*Label 1841*/ GIMT_Encode4(119913), // Rule ID 6773 //
      GIM_CheckFeatures, GIMT_Encode2(GIFBS_LDSRequiresM0Init),
      GIM_CheckMemorySizeEqualToLLT, /*MI*/0, /*MMO*/0, /*OpIdx*/0,
      GIM_CheckMemoryAddressSpace, /*MI*/0, /*MMO*/0, /*NumAddrSpace*/1, /*AddrSpace*/3,
      GIM_CheckMemoryAlignment, /*MI*/0, /*MMO*/0, /*MinAlign*/8,
      GIM_CheckAtomicOrdering, /*MI*/0, /*Order*/(uint8_t)AtomicOrdering::NotAtomic,
      GIM_CheckPointerToAny, /*MI*/0, /*Op*/1, /*SizeInBits*/0,
      GIM_CheckComplexPattern, /*MI*/0, /*Op*/1, /*Renderer*/GIMT_Encode2(0), GIMT_Encode2(GICP_gi_ds_1addr_1offset),
      // (AMDGPUst_glue p1:{ *:[i64] }:$value, (DS1Addr1Offset:{ *:[iPTR] } i32:{ *:[i32] }:$ptr, i32:{ *:[i32] }:$offset))<<P:Predicate_unindexedstore_glue>><<P:Predicate_store_glue>><<P:Predicate_store_local_m0>><<P:Predicate_store_align8_local_m0>>  =>  (DS_WRITE_B64 ?:{ *:[i32] }:$ptr, anonymous_15036:{ *:[i64] }:$value, offset:{ *:[i32] }:$offset, 0:{ *:[i1] })
      GIR_BuildMI, /*InsnID*/0, /*Opcode*/GIMT_Encode2(AMDGPU::DS_WRITE_B64),
      GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/0, // ptr
      GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/0, // value
      GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/1, // offset
      GIR_AddImm8, /*InsnID*/0, /*Imm*/0,
      GIR_MergeMemOperands, /*InsnID*/0, /*NumInsns*/1, /*MergeInsnID's*/0,
      GIR_ConstrainSelectedInstOperands, /*InsnID*/0,
      GIR_EraseFromParent, /*InsnID*/0,
      // GIR_Coverage, 6773,
      GIR_Done,
    // Label 1841: @119913
    GIM_Try, /*On fail goto*//*Label 1842*/ GIMT_Encode4(119979), // Rule ID 6850 //
      GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasUnalignedAccessMode_NotLDSRequiresM0Init),
      GIM_CheckMemoryAddressSpace, /*MI*/0, /*MMO*/0, /*NumAddrSpace*/1, /*AddrSpace*/3,
      GIM_CheckMemoryAddressSpace, /*MI*/0, /*MMO*/0, /*NumAddrSpace*/1, /*AddrSpace*/3,
      GIM_CheckAtomicOrdering, /*MI*/0, /*Order*/(uint8_t)AtomicOrdering::NotAtomic,
      GIM_CheckPointerToAny, /*MI*/0, /*Op*/1, /*SizeInBits*/0,
      GIM_CheckCxxInsnPredicate, /*MI*/0, /*FnId*/GIMT_Encode2(GICXXPred_MI_Predicate_store_align_less_than_4_local),
      GIM_CheckComplexPattern, /*MI*/0, /*Op*/1, /*Renderer*/GIMT_Encode2(0), GIMT_Encode2(GICP_gi_ds_1addr_1offset),
      // (st p1:{ *:[i64] }:$value, (DS1Addr1Offset:{ *:[iPTR] } i32:{ *:[i32] }:$ptr, i32:{ *:[i32] }:$offset))<<P:Predicate_unindexedstore>><<P:Predicate_store_local>><<P:Predicate_store_align_less_than_4_local>>  =>  (DS_WRITE_B64_gfx9 ?:{ *:[i32] }:$ptr, anonymous_15036:{ *:[i64] }:$value, offset:{ *:[i32] }:$offset, 0:{ *:[i1] })
      GIR_BuildMI, /*InsnID*/0, /*Opcode*/GIMT_Encode2(AMDGPU::DS_WRITE_B64_gfx9),
      GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/0, // ptr
      GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/0, // value
      GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/1, // offset
      GIR_AddImm8, /*InsnID*/0, /*Imm*/0,
      GIR_MergeMemOperands, /*InsnID*/0, /*NumInsns*/1, /*MergeInsnID's*/0,
      GIR_ConstrainSelectedInstOperands, /*InsnID*/0,
      GIR_EraseFromParent, /*InsnID*/0,
      // GIR_Coverage, 6850,
      GIR_Done,
    // Label 1842: @119979
    GIM_Try, /*On fail goto*//*Label 1843*/ GIMT_Encode4(120040), // Rule ID 6774 //
      GIM_CheckFeatures, GIMT_Encode2(GIFBS_NotLDSRequiresM0Init),
      GIM_CheckMemoryAddressSpace, /*MI*/0, /*MMO*/0, /*NumAddrSpace*/1, /*AddrSpace*/3,
      GIM_CheckMemoryAlignment, /*MI*/0, /*MMO*/0, /*MinAlign*/8,
      GIM_CheckAtomicOrdering, /*MI*/0, /*Order*/(uint8_t)AtomicOrdering::NotAtomic,
      GIM_CheckPointerToAny, /*MI*/0, /*Op*/1, /*SizeInBits*/0,
      GIM_CheckComplexPattern, /*MI*/0, /*Op*/1, /*Renderer*/GIMT_Encode2(0), GIMT_Encode2(GICP_gi_ds_1addr_1offset),
      // (st p1:{ *:[i64] }:$value, (DS1Addr1Offset:{ *:[iPTR] } i32:{ *:[i32] }:$ptr, i32:{ *:[i32] }:$offset))<<P:Predicate_unindexedstore>><<P:Predicate_store_local>><<P:Predicate_store_align8_local>>  =>  (DS_WRITE_B64_gfx9 ?:{ *:[i32] }:$ptr, anonymous_15036:{ *:[i64] }:$value, offset:{ *:[i32] }:$offset, 0:{ *:[i1] })
      GIR_BuildMI, /*InsnID*/0, /*Opcode*/GIMT_Encode2(AMDGPU::DS_WRITE_B64_gfx9),
      GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/0, // ptr
      GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/0, // value
      GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/1, // offset
      GIR_AddImm8, /*InsnID*/0, /*Imm*/0,
      GIR_MergeMemOperands, /*InsnID*/0, /*NumInsns*/1, /*MergeInsnID's*/0,
      GIR_ConstrainSelectedInstOperands, /*InsnID*/0,
      GIR_EraseFromParent, /*InsnID*/0,
      // GIR_Coverage, 6774,
      GIR_Done,
    // Label 1843: @120040
    GIM_Try, /*On fail goto*//*Label 1844*/ GIMT_Encode4(120102), // Rule ID 3535 //
      GIM_CheckFeatures, GIMT_Encode2(GIFBS_EnableFlatScratch_HasFlatScratchInsts_HasFlatScratchSVSMode),
      GIM_CheckMemoryAddressSpace, /*MI*/0, /*MMO*/0, /*NumAddrSpace*/1, /*AddrSpace*/5,
      GIM_CheckAtomicOrdering, /*MI*/0, /*Order*/(uint8_t)AtomicOrdering::NotAtomic,
      GIM_CheckPointerToAny, /*MI*/0, /*Op*/1, /*SizeInBits*/0,
      GIM_CheckComplexPattern, /*MI*/0, /*Op*/1, /*Renderer*/GIMT_Encode2(0), GIMT_Encode2(GICP_gi_flat_scratch_svaddr),
      // (st p1:{ *:[i64] }:$data, (ScratchSVAddr:{ *:[iPTR] } VGPR_32:{ *:[i32] }:$vaddr, SGPR_32:{ *:[i32] }:$saddr, i32:{ *:[i32] }:$offset))<<P:Predicate_unindexedstore>><<P:Predicate_store_private>>  =>  (SCRATCH_STORE_DWORDX2_SVS anonymous_15036:{ *:[i64] }:$data, ?:{ *:[i32] }:$vaddr, ?:{ *:[i32] }:$saddr, ?:{ *:[i32] }:$offset)
      GIR_BuildMI, /*InsnID*/0, /*Opcode*/GIMT_Encode2(AMDGPU::SCRATCH_STORE_DWORDX2_SVS),
      GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/0, // data
      GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/0, // vaddr
      GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/1, // saddr
      GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/2, // offset
      GIR_AddImm8, /*InsnID*/0, /*Imm*/0,
      GIR_MergeMemOperands, /*InsnID*/0, /*NumInsns*/1, /*MergeInsnID's*/0,
      GIR_ConstrainSelectedInstOperands, /*InsnID*/0,
      GIR_EraseFromParent, /*InsnID*/0,
      // GIR_Coverage, 3535,
      GIR_Done,
    // Label 1844: @120102
    GIM_Try, /*On fail goto*//*Label 1845*/ GIMT_Encode4(120159), // Rule ID 3534 //
      GIM_CheckFeatures, GIMT_Encode2(GIFBS_EnableFlatScratch_HasFlatScratchInsts),
      GIM_CheckMemoryAddressSpace, /*MI*/0, /*MMO*/0, /*NumAddrSpace*/1, /*AddrSpace*/5,
      GIM_CheckAtomicOrdering, /*MI*/0, /*Order*/(uint8_t)AtomicOrdering::NotAtomic,
      GIM_CheckPointerToAny, /*MI*/0, /*Op*/1, /*SizeInBits*/0,
      GIM_CheckComplexPattern, /*MI*/0, /*Op*/1, /*Renderer*/GIMT_Encode2(0), GIMT_Encode2(GICP_gi_flat_scratch_saddr),
      // (st p1:{ *:[i64] }:$data, (ScratchSAddr:{ *:[iPTR] } SGPR_32:{ *:[i32] }:$saddr, i32:{ *:[i32] }:$offset))<<P:Predicate_unindexedstore>><<P:Predicate_store_private>>  =>  (SCRATCH_STORE_DWORDX2_SADDR anonymous_15036:{ *:[i64] }:$data, ?:{ *:[i32] }:$saddr, ?:{ *:[i32] }:$offset)
      GIR_BuildMI, /*InsnID*/0, /*Opcode*/GIMT_Encode2(AMDGPU::SCRATCH_STORE_DWORDX2_SADDR),
      GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/0, // data
      GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/0, // saddr
      GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/1, // offset
      GIR_AddImm8, /*InsnID*/0, /*Imm*/0,
      GIR_MergeMemOperands, /*InsnID*/0, /*NumInsns*/1, /*MergeInsnID's*/0,
      GIR_ConstrainSelectedInstOperands, /*InsnID*/0,
      GIR_EraseFromParent, /*InsnID*/0,
      // GIR_Coverage, 3534,
      GIR_Done,
    // Label 1845: @120159
    GIM_Try, /*On fail goto*//*Label 1846*/ GIMT_Encode4(120216), // Rule ID 3533 //
      GIM_CheckFeatures, GIMT_Encode2(GIFBS_EnableFlatScratch_HasFlatScratchInsts),
      GIM_CheckMemoryAddressSpace, /*MI*/0, /*MMO*/0, /*NumAddrSpace*/1, /*AddrSpace*/5,
      GIM_CheckAtomicOrdering, /*MI*/0, /*Order*/(uint8_t)AtomicOrdering::NotAtomic,
      GIM_CheckPointerToAny, /*MI*/0, /*Op*/1, /*SizeInBits*/0,
      GIM_CheckComplexPattern, /*MI*/0, /*Op*/1, /*Renderer*/GIMT_Encode2(0), GIMT_Encode2(GICP_gi_flat_scratch_offset),
      // (st p1:{ *:[i64] }:$data, (ScratchOffset:{ *:[iPTR] } VGPR_32:{ *:[i32] }:$vaddr, i32:{ *:[i32] }:$offset))<<P:Predicate_unindexedstore>><<P:Predicate_store_private>>  =>  (SCRATCH_STORE_DWORDX2 anonymous_15036:{ *:[i64] }:$data, ?:{ *:[i32] }:$vaddr, ?:{ *:[i32] }:$offset)
      GIR_BuildMI, /*InsnID*/0, /*Opcode*/GIMT_Encode2(AMDGPU::SCRATCH_STORE_DWORDX2),
      GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/0, // data
      GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/0, // vaddr
      GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/1, // offset
      GIR_AddImm8, /*InsnID*/0, /*Imm*/0,
      GIR_MergeMemOperands, /*InsnID*/0, /*NumInsns*/1, /*MergeInsnID's*/0,
      GIR_ConstrainSelectedInstOperands, /*InsnID*/0,
      GIR_EraseFromParent, /*InsnID*/0,
      // GIR_Coverage, 3533,
      GIR_Done,
    // Label 1846: @120216
    GIM_Try, /*On fail goto*//*Label 1847*/ GIMT_Encode4(120286), // Rule ID 3870 //
      GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasUnrestrictedSOffset),
      GIM_CheckMemoryAddressSpace, /*MI*/0, /*MMO*/0, /*NumAddrSpace*/1, /*AddrSpace*/1,
      GIM_CheckAtomicOrdering, /*MI*/0, /*Order*/(uint8_t)AtomicOrdering::NotAtomic,
      GIM_CheckPointerToAny, /*MI*/0, /*Op*/1, /*SizeInBits*/0,
      GIM_CheckComplexPattern, /*MI*/0, /*Op*/1, /*Renderer*/GIMT_Encode2(0), GIMT_Encode2(GICP_gi_mubuf_addr64),
      // (st p1:{ *:[i64] }:$vdata, (MUBUFAddr64:{ *:[iPTR] } v4i32:{ *:[v4i32] }:$srsrc, i64:{ *:[i64] }:$vaddr, i32:{ *:[i32] }:$soffset, i32:{ *:[i32] }:$offset))<<P:Predicate_unindexedstore>><<P:Predicate_store_global>>  =>  (BUFFER_STORE_DWORDX2_ADDR64 p1:{ *:[i64] }:$vdata, i64:{ *:[i64] }:$vaddr, v4i32:{ *:[v4i32] }:$srsrc, i32:{ *:[i32] }:$soffset, i32:{ *:[i32] }:$offset)
      GIR_BuildMI, /*InsnID*/0, /*Opcode*/GIMT_Encode2(AMDGPU::BUFFER_STORE_DWORDX2_ADDR64),
      GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/0, // vdata
      GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/1, // vaddr
      GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/0, // srsrc
      GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/2, // soffset
      GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/3, // offset
      GIR_AddImm8, /*InsnID*/0, /*Imm*/0,
      GIR_AddImm8, /*InsnID*/0, /*Imm*/0,
      GIR_MergeMemOperands, /*InsnID*/0, /*NumInsns*/1, /*MergeInsnID's*/0,
      GIR_ConstrainSelectedInstOperands, /*InsnID*/0,
      GIR_EraseFromParent, /*InsnID*/0,
      // GIR_Coverage, 3870,
      GIR_Done,
    // Label 1847: @120286
    GIM_Try, /*On fail goto*//*Label 1848*/ GIMT_Encode4(120353), // Rule ID 3872 //
      GIM_CheckMemoryAddressSpace, /*MI*/0, /*MMO*/0, /*NumAddrSpace*/1, /*AddrSpace*/1,
      GIM_CheckAtomicOrdering, /*MI*/0, /*Order*/(uint8_t)AtomicOrdering::NotAtomic,
      GIM_CheckPointerToAny, /*MI*/0, /*Op*/1, /*SizeInBits*/0,
      GIM_CheckComplexPattern, /*MI*/0, /*Op*/1, /*Renderer*/GIMT_Encode2(0), GIMT_Encode2(GICP_gi_mubuf_addr64),
      // (st p1:{ *:[i64] }:$vdata, (MUBUFAddr64:{ *:[iPTR] } v4i32:{ *:[v4i32] }:$srsrc, i64:{ *:[i64] }:$vaddr, i32:{ *:[i32] }:$soffset, i32:{ *:[i32] }:$offset))<<P:Predicate_unindexedstore>><<P:Predicate_store_global>>  =>  (BUFFER_STORE_DWORDX2_VBUFFER_ADDR64 p1:{ *:[i64] }:$vdata, i64:{ *:[i64] }:$vaddr, v4i32:{ *:[v4i32] }:$srsrc, i32:{ *:[i32] }:$soffset, i32:{ *:[i32] }:$offset)
      GIR_BuildMI, /*InsnID*/0, /*Opcode*/GIMT_Encode2(AMDGPU::BUFFER_STORE_DWORDX2_VBUFFER_ADDR64),
      GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/0, // vdata
      GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/1, // vaddr
      GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/0, // srsrc
      GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/2, // soffset
      GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/3, // offset
      GIR_AddImm8, /*InsnID*/0, /*Imm*/0,
      GIR_AddImm8, /*InsnID*/0, /*Imm*/0,
      GIR_MergeMemOperands, /*InsnID*/0, /*NumInsns*/1, /*MergeInsnID's*/0,
      GIR_ConstrainSelectedInstOperands, /*InsnID*/0,
      GIR_EraseFromParent, /*InsnID*/0,
      // GIR_Coverage, 3872,
      GIR_Done,
    // Label 1848: @120353
    GIM_Try, /*On fail goto*//*Label 1849*/ GIMT_Encode4(120477), // Rule ID 6708 //
      GIM_CheckFeatures, GIMT_Encode2(GIFBS_LDSRequiresM0Init_isGFX7Plus),
      GIM_CheckMemorySizeEqualToLLT, /*MI*/0, /*MMO*/0, /*OpIdx*/0,
      GIM_CheckMemoryAddressSpace, /*MI*/0, /*MMO*/0, /*NumAddrSpace*/1, /*AddrSpace*/3,
      GIM_CheckAtomicOrdering, /*MI*/0, /*Order*/(uint8_t)AtomicOrdering::NotAtomic,
      GIM_CheckPointerToAny, /*MI*/0, /*Op*/1, /*SizeInBits*/0,
      GIM_CheckComplexPattern, /*MI*/0, /*Op*/1, /*Renderer*/GIMT_Encode2(0), GIMT_Encode2(GICP_gi_ds_64bit_4byte_aligned),
      // (AMDGPUst_glue p1:{ *:[i64] }:$value, (DS64Bit4ByteAligned:{ *:[iPTR] } i32:{ *:[i32] }:$ptr, i8:{ *:[i8] }:$offset0, i8:{ *:[i8] }:$offset1))<<P:Predicate_unindexedstore_glue>><<P:Predicate_store_glue>><<P:Predicate_store_local_m0>>  =>  (DS_WRITE2_B32 ?:{ *:[i32] }:$ptr, (EXTRACT_SUBREG:{ *:[i32] } VReg_64:{ *:[i64] }:$value, sub0:{ *:[i32] }), (EXTRACT_SUBREG:{ *:[i32] } VReg_64:{ *:[i64] }:$value, sub1:{ *:[i32] }), ?:{ *:[i8] }:$offset0, ?:{ *:[i8] }:$offset1, 0:{ *:[i1] })
      GIR_MakeTempReg, /*TempRegID*/0, /*TypeID*/GILLT_s32,
      GIR_MakeTempReg, /*TempRegID*/1, /*TypeID*/GILLT_s32,
      GIR_BuildMI, /*InsnID*/2, /*Opcode*/GIMT_Encode2(TargetOpcode::COPY),
      GIR_AddTempRegister, /*InsnID*/2, /*TempRegID*/1, /*TempRegFlags*/GIMT_Encode2(RegState::Define),
      GIR_CopySubReg, /*NewInsnID*/2, /*OldInsnID*/0, /*OpIdx*/0, /*SubRegIdx*/GIMT_Encode2(11), // value
      GIR_ConstrainOperandRC, /*InsnID*/2, /*Op*/0, GIMT_Encode2(AMDGPU::VGPR_32RegClassID),
      GIR_ConstrainOperandRC, /*InsnID*/2, /*Op*/1, GIMT_Encode2(AMDGPU::VReg_64RegClassID),
      GIR_BuildMI, /*InsnID*/1, /*Opcode*/GIMT_Encode2(TargetOpcode::COPY),
      GIR_AddTempRegister, /*InsnID*/1, /*TempRegID*/0, /*TempRegFlags*/GIMT_Encode2(RegState::Define),
      GIR_CopySubReg, /*NewInsnID*/1, /*OldInsnID*/0, /*OpIdx*/0, /*SubRegIdx*/GIMT_Encode2(3), // value
      GIR_ConstrainOperandRC, /*InsnID*/1, /*Op*/0, GIMT_Encode2(AMDGPU::VGPR_32RegClassID),
      GIR_ConstrainOperandRC, /*InsnID*/1, /*Op*/1, GIMT_Encode2(AMDGPU::VReg_64RegClassID),
      GIR_BuildMI, /*InsnID*/0, /*Opcode*/GIMT_Encode2(AMDGPU::DS_WRITE2_B32),
      GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/0, // ptr
      GIR_AddSimpleTempRegister, /*InsnID*/0, /*TempRegID*/0,
      GIR_AddSimpleTempRegister, /*InsnID*/0, /*TempRegID*/1,
      GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/1, // offset0
      GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/2, // offset1
      GIR_AddImm8, /*InsnID*/0, /*Imm*/0,
      GIR_MergeMemOperands, /*InsnID*/0, /*NumInsns*/1, /*MergeInsnID's*/0,
      GIR_ConstrainSelectedInstOperands, /*InsnID*/0,
      GIR_EraseFromParent, /*InsnID*/0,
      // GIR_Coverage, 6708,
      GIR_Done,
    // Label 1849: @120477
    GIM_Try, /*On fail goto*//*Label 1850*/ GIMT_Encode4(120542), // Rule ID 3869 //
      GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasUnrestrictedSOffset),
      GIM_CheckMemoryAddressSpace, /*MI*/0, /*MMO*/0, /*NumAddrSpace*/1, /*AddrSpace*/1,
      GIM_CheckAtomicOrdering, /*MI*/0, /*Order*/(uint8_t)AtomicOrdering::NotAtomic,
      GIM_CheckPointerToAny, /*MI*/0, /*Op*/1, /*SizeInBits*/0,
      GIM_CheckComplexPattern, /*MI*/0, /*Op*/1, /*Renderer*/GIMT_Encode2(0), GIMT_Encode2(GICP_gi_mubuf_offset),
      // (st p1:{ *:[i64] }:$vdata, (MUBUFOffset:{ *:[iPTR] } v4i32:{ *:[v4i32] }:$srsrc, i32:{ *:[i32] }:$soffset, i32:{ *:[i32] }:$offset))<<P:Predicate_unindexedstore>><<P:Predicate_store_global>>  =>  (BUFFER_STORE_DWORDX2_OFFSET p1:{ *:[i64] }:$vdata, v4i32:{ *:[v4i32] }:$srsrc, i32:{ *:[i32] }:$soffset, i32:{ *:[i32] }:$offset)
      GIR_BuildMI, /*InsnID*/0, /*Opcode*/GIMT_Encode2(AMDGPU::BUFFER_STORE_DWORDX2_OFFSET),
      GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/0, // vdata
      GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/0, // srsrc
      GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/1, // soffset
      GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/2, // offset
      GIR_AddImm8, /*InsnID*/0, /*Imm*/0,
      GIR_AddImm8, /*InsnID*/0, /*Imm*/0,
      GIR_MergeMemOperands, /*InsnID*/0, /*NumInsns*/1, /*MergeInsnID's*/0,
      GIR_ConstrainSelectedInstOperands, /*InsnID*/0,
      GIR_EraseFromParent, /*InsnID*/0,
      // GIR_Coverage, 3869,
      GIR_Done,
    // Label 1850: @120542
    GIM_Try, /*On fail goto*//*Label 1851*/ GIMT_Encode4(120604), // Rule ID 3871 //
      GIM_CheckMemoryAddressSpace, /*MI*/0, /*MMO*/0, /*NumAddrSpace*/1, /*AddrSpace*/1,
      GIM_CheckAtomicOrdering, /*MI*/0, /*Order*/(uint8_t)AtomicOrdering::NotAtomic,
      GIM_CheckPointerToAny, /*MI*/0, /*Op*/1, /*SizeInBits*/0,
      GIM_CheckComplexPattern, /*MI*/0, /*Op*/1, /*Renderer*/GIMT_Encode2(0), GIMT_Encode2(GICP_gi_mubuf_offset),
      // (st p1:{ *:[i64] }:$vdata, (MUBUFOffset:{ *:[iPTR] } v4i32:{ *:[v4i32] }:$srsrc, i32:{ *:[i32] }:$soffset, i32:{ *:[i32] }:$offset))<<P:Predicate_unindexedstore>><<P:Predicate_store_global>>  =>  (BUFFER_STORE_DWORDX2_VBUFFER_OFFSET p1:{ *:[i64] }:$vdata, v4i32:{ *:[v4i32] }:$srsrc, i32:{ *:[i32] }:$soffset, i32:{ *:[i32] }:$offset)
      GIR_BuildMI, /*InsnID*/0, /*Opcode*/GIMT_Encode2(AMDGPU::BUFFER_STORE_DWORDX2_VBUFFER_OFFSET),
      GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/0, // vdata
      GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/0, // srsrc
      GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/1, // soffset
      GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/2, // offset
      GIR_AddImm8, /*InsnID*/0, /*Imm*/0,
      GIR_AddImm8, /*InsnID*/0, /*Imm*/0,
      GIR_MergeMemOperands, /*InsnID*/0, /*NumInsns*/1, /*MergeInsnID's*/0,
      GIR_ConstrainSelectedInstOperands, /*InsnID*/0,
      GIR_EraseFromParent, /*InsnID*/0,
      // GIR_Coverage, 3871,
      GIR_Done,
    // Label 1851: @120604
    GIM_Try, /*On fail goto*//*Label 1852*/ GIMT_Encode4(120724), // Rule ID 6710 //
      GIM_CheckFeatures, GIMT_Encode2(GIFBS_NotLDSRequiresM0Init),
      GIM_CheckMemoryAddressSpace, /*MI*/0, /*MMO*/0, /*NumAddrSpace*/1, /*AddrSpace*/3,
      GIM_CheckAtomicOrdering, /*MI*/0, /*Order*/(uint8_t)AtomicOrdering::NotAtomic,
      GIM_CheckPointerToAny, /*MI*/0, /*Op*/1, /*SizeInBits*/0,
      GIM_CheckComplexPattern, /*MI*/0, /*Op*/1, /*Renderer*/GIMT_Encode2(0), GIMT_Encode2(GICP_gi_ds_64bit_4byte_aligned),
      // (st p1:{ *:[i64] }:$value, (DS64Bit4ByteAligned:{ *:[iPTR] } i32:{ *:[i32] }:$ptr, i8:{ *:[i8] }:$offset0, i8:{ *:[i8] }:$offset1))<<P:Predicate_unindexedstore>><<P:Predicate_store_local>>  =>  (DS_WRITE2_B32_gfx9 ?:{ *:[i32] }:$ptr, (EXTRACT_SUBREG:{ *:[i32] } VReg_64:{ *:[i64] }:$value, sub0:{ *:[i32] }), (EXTRACT_SUBREG:{ *:[i32] } VReg_64:{ *:[i64] }:$value, sub1:{ *:[i32] }), ?:{ *:[i8] }:$offset0, ?:{ *:[i8] }:$offset1, 0:{ *:[i1] })
      GIR_MakeTempReg, /*TempRegID*/0, /*TypeID*/GILLT_s32,
      GIR_MakeTempReg, /*TempRegID*/1, /*TypeID*/GILLT_s32,
      GIR_BuildMI, /*InsnID*/2, /*Opcode*/GIMT_Encode2(TargetOpcode::COPY),
      GIR_AddTempRegister, /*InsnID*/2, /*TempRegID*/1, /*TempRegFlags*/GIMT_Encode2(RegState::Define),
      GIR_CopySubReg, /*NewInsnID*/2, /*OldInsnID*/0, /*OpIdx*/0, /*SubRegIdx*/GIMT_Encode2(11), // value
      GIR_ConstrainOperandRC, /*InsnID*/2, /*Op*/0, GIMT_Encode2(AMDGPU::VGPR_32RegClassID),
      GIR_ConstrainOperandRC, /*InsnID*/2, /*Op*/1, GIMT_Encode2(AMDGPU::VReg_64RegClassID),
      GIR_BuildMI, /*InsnID*/1, /*Opcode*/GIMT_Encode2(TargetOpcode::COPY),
      GIR_AddTempRegister, /*InsnID*/1, /*TempRegID*/0, /*TempRegFlags*/GIMT_Encode2(RegState::Define),
      GIR_CopySubReg, /*NewInsnID*/1, /*OldInsnID*/0, /*OpIdx*/0, /*SubRegIdx*/GIMT_Encode2(3), // value
      GIR_ConstrainOperandRC, /*InsnID*/1, /*Op*/0, GIMT_Encode2(AMDGPU::VGPR_32RegClassID),
      GIR_ConstrainOperandRC, /*InsnID*/1, /*Op*/1, GIMT_Encode2(AMDGPU::VReg_64RegClassID),
      GIR_BuildMI, /*InsnID*/0, /*Opcode*/GIMT_Encode2(AMDGPU::DS_WRITE2_B32_gfx9),
      GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/0, // ptr
      GIR_AddSimpleTempRegister, /*InsnID*/0, /*TempRegID*/0,
      GIR_AddSimpleTempRegister, /*InsnID*/0, /*TempRegID*/1,
      GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/1, // offset0
      GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/2, // offset1
      GIR_AddImm8, /*InsnID*/0, /*Imm*/0,
      GIR_MergeMemOperands, /*InsnID*/0, /*NumInsns*/1, /*MergeInsnID's*/0,
      GIR_ConstrainSelectedInstOperands, /*InsnID*/0,
      GIR_EraseFromParent, /*InsnID*/0,
      // GIR_Coverage, 6710,
      GIR_Done,
    // Label 1852: @120724
    GIM_Try, /*On fail goto*//*Label 1853*/ GIMT_Encode4(120786), // Rule ID 3063 //
      GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasFlatGlobalInsts),
      GIM_CheckMemoryAddressSpace, /*MI*/0, /*MMO*/0, /*NumAddrSpace*/1, /*AddrSpace*/1,
      GIM_CheckAtomicOrdering, /*MI*/0, /*Order*/(uint8_t)AtomicOrdering::NotAtomic,
      GIM_CheckPointerToAny, /*MI*/0, /*Op*/1, /*SizeInBits*/0,
      GIM_CheckComplexPattern, /*MI*/0, /*Op*/1, /*Renderer*/GIMT_Encode2(0), GIMT_Encode2(GICP_gi_global_saddr),
      // (st p1:{ *:[i64] }:$data, (GlobalSAddr:{ *:[iPTR] } SReg_64:{ *:[i64] }:$saddr, VGPR_32:{ *:[i32] }:$voffset, i32:{ *:[i32] }:$offset))<<P:Predicate_unindexedstore>><<P:Predicate_store_global>>  =>  (GLOBAL_STORE_DWORDX2_SADDR ?:{ *:[i32] }:$voffset, anonymous_15036:{ *:[i64] }:$data, ?:{ *:[i64] }:$saddr, ?:{ *:[i32] }:$offset)
      GIR_BuildMI, /*InsnID*/0, /*Opcode*/GIMT_Encode2(AMDGPU::GLOBAL_STORE_DWORDX2_SADDR),
      GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/1, // voffset
      GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/0, // data
      GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/0, // saddr
      GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/2, // offset
      GIR_AddImm8, /*InsnID*/0, /*Imm*/0,
      GIR_MergeMemOperands, /*InsnID*/0, /*NumInsns*/1, /*MergeInsnID's*/0,
      GIR_ConstrainSelectedInstOperands, /*InsnID*/0,
      GIR_EraseFromParent, /*InsnID*/0,
      // GIR_Coverage, 3063,
      GIR_Done,
    // Label 1853: @120786
    GIM_Try, /*On fail goto*//*Label 1854*/ GIMT_Encode4(120843), // Rule ID 3062 //
      GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasFlatGlobalInsts),
      GIM_CheckMemoryAddressSpace, /*MI*/0, /*MMO*/0, /*NumAddrSpace*/1, /*AddrSpace*/1,
      GIM_CheckAtomicOrdering, /*MI*/0, /*Order*/(uint8_t)AtomicOrdering::NotAtomic,
      GIM_CheckPointerToAny, /*MI*/0, /*Op*/1, /*SizeInBits*/0,
      GIM_CheckComplexPattern, /*MI*/0, /*Op*/1, /*Renderer*/GIMT_Encode2(0), GIMT_Encode2(GICP_gi_global_offset),
      // (st p1:{ *:[i64] }:$data, (GlobalOffset:{ *:[iPTR] } i64:{ *:[i64] }:$vaddr, i32:{ *:[i32] }:$offset))<<P:Predicate_unindexedstore>><<P:Predicate_store_global>>  =>  (GLOBAL_STORE_DWORDX2 ?:{ *:[i64] }:$vaddr, anonymous_15036:{ *:[i64] }:$data, ?:{ *:[i32] }:$offset)
      GIR_BuildMI, /*InsnID*/0, /*Opcode*/GIMT_Encode2(AMDGPU::GLOBAL_STORE_DWORDX2),
      GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/0, // vaddr
      GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/0, // data
      GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/1, // offset
      GIR_AddImm8, /*InsnID*/0, /*Imm*/0,
      GIR_MergeMemOperands, /*InsnID*/0, /*NumInsns*/1, /*MergeInsnID's*/0,
      GIR_ConstrainSelectedInstOperands, /*InsnID*/0,
      GIR_EraseFromParent, /*InsnID*/0,
      // GIR_Coverage, 3062,
      GIR_Done,
    // Label 1854: @120843
    GIM_Try, /*On fail goto*//*Label 1855*/ GIMT_Encode4(120901), // Rule ID 2804 //
      GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasFlatAddressSpace),
      GIM_CheckMemoryAddressSpace, /*MI*/0, /*MMO*/0, /*NumAddrSpace*/2, /*AddrSpace*/0, /*AddrSpace*/1,
      GIM_CheckAtomicOrdering, /*MI*/0, /*Order*/(uint8_t)AtomicOrdering::NotAtomic,
      GIM_CheckPointerToAny, /*MI*/0, /*Op*/1, /*SizeInBits*/0,
      GIM_CheckComplexPattern, /*MI*/0, /*Op*/1, /*Renderer*/GIMT_Encode2(0), GIMT_Encode2(GICP_gi_flat_offset),
      // (st p1:{ *:[i64] }:$data, (FlatOffset:{ *:[iPTR] } i64:{ *:[i64] }:$vaddr, i32:{ *:[i32] }:$offset))<<P:Predicate_unindexedstore>><<P:Predicate_store_flat>>  =>  (FLAT_STORE_DWORDX2 ?:{ *:[i64] }:$vaddr, anonymous_15036:{ *:[i64] }:$data, ?:{ *:[i32] }:$offset)
      GIR_BuildMI, /*InsnID*/0, /*Opcode*/GIMT_Encode2(AMDGPU::FLAT_STORE_DWORDX2),
      GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/0, // vaddr
      GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/0, // data
      GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/1, // offset
      GIR_AddImm8, /*InsnID*/0, /*Imm*/0,
      GIR_MergeMemOperands, /*InsnID*/0, /*NumInsns*/1, /*MergeInsnID's*/0,
      GIR_ConstrainSelectedInstOperands, /*InsnID*/0,
      GIR_EraseFromParent, /*InsnID*/0,
      // GIR_Coverage, 2804,
      GIR_Done,
    // Label 1855: @120901
    GIM_Reject,
    // Label 1808: @120902
    GIM_Try, /*On fail goto*//*Label 1856*/ GIMT_Encode4(120967), // Rule ID 5534 //
      GIM_CheckFeatures, GIMT_Encode2(GIFBS_DisableFlatScratch_HasUnrestrictedSOffset),
      GIM_CheckMemoryAddressSpace, /*MI*/0, /*MMO*/0, /*NumAddrSpace*/1, /*AddrSpace*/5,
      GIM_CheckAtomicOrdering, /*MI*/0, /*Order*/(uint8_t)AtomicOrdering::NotAtomic,
      GIM_CheckPointerToAny, /*MI*/0, /*Op*/1, /*SizeInBits*/0,
      GIM_CheckComplexPattern, /*MI*/0, /*Op*/1, /*Renderer*/GIMT_Encode2(0), GIMT_Encode2(GICP_gi_mubuf_scratch_offset),
      // (st p2:{ *:[i32] }:$value, (MUBUFScratchOffset:{ *:[iPTR] } v4i32:{ *:[v4i32] }:$srsrc, i32:{ *:[i32] }:$soffset, i32:{ *:[i32] }:$offset))<<P:Predicate_unindexedstore>><<P:Predicate_store_private>>  =>  (BUFFER_STORE_DWORD_OFFSET VGPR_32:{ *:[i32] }:$value, ?:{ *:[v4i32] }:$srsrc, ?:{ *:[i32] }:$soffset, ?:{ *:[i32] }:$offset, 0:{ *:[i32] }, 0:{ *:[i1] })
      GIR_BuildMI, /*InsnID*/0, /*Opcode*/GIMT_Encode2(AMDGPU::BUFFER_STORE_DWORD_OFFSET),
      GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/0, // value
      GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/0, // srsrc
      GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/1, // soffset
      GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/2, // offset
      GIR_AddImm8, /*InsnID*/0, /*Imm*/0,
      GIR_AddImm8, /*InsnID*/0, /*Imm*/0,
      GIR_MergeMemOperands, /*InsnID*/0, /*NumInsns*/1, /*MergeInsnID's*/0,
      GIR_ConstrainSelectedInstOperands, /*InsnID*/0,
      GIR_EraseFromParent, /*InsnID*/0,
      // GIR_Coverage, 5534,
      GIR_Done,
    // Label 1856: @120967
    GIM_Try, /*On fail goto*//*Label 1857*/ GIMT_Encode4(121032), // Rule ID 5536 //
      GIM_CheckFeatures, GIMT_Encode2(GIFBS_DisableFlatScratch),
      GIM_CheckMemoryAddressSpace, /*MI*/0, /*MMO*/0, /*NumAddrSpace*/1, /*AddrSpace*/5,
      GIM_CheckAtomicOrdering, /*MI*/0, /*Order*/(uint8_t)AtomicOrdering::NotAtomic,
      GIM_CheckPointerToAny, /*MI*/0, /*Op*/1, /*SizeInBits*/0,
      GIM_CheckComplexPattern, /*MI*/0, /*Op*/1, /*Renderer*/GIMT_Encode2(0), GIMT_Encode2(GICP_gi_mubuf_scratch_offset),
      // (st p2:{ *:[i32] }:$value, (MUBUFScratchOffset:{ *:[iPTR] } v4i32:{ *:[v4i32] }:$srsrc, i32:{ *:[i32] }:$soffset, i32:{ *:[i32] }:$offset))<<P:Predicate_unindexedstore>><<P:Predicate_store_private>>  =>  (BUFFER_STORE_DWORD_VBUFFER_OFFSET VGPR_32:{ *:[i32] }:$value, ?:{ *:[v4i32] }:$srsrc, ?:{ *:[i32] }:$soffset, ?:{ *:[i32] }:$offset, 0:{ *:[i32] }, 0:{ *:[i1] })
      GIR_BuildMI, /*InsnID*/0, /*Opcode*/GIMT_Encode2(AMDGPU::BUFFER_STORE_DWORD_VBUFFER_OFFSET),
      GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/0, // value
      GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/0, // srsrc
      GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/1, // soffset
      GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/2, // offset
      GIR_AddImm8, /*InsnID*/0, /*Imm*/0,
      GIR_AddImm8, /*InsnID*/0, /*Imm*/0,
      GIR_MergeMemOperands, /*InsnID*/0, /*NumInsns*/1, /*MergeInsnID's*/0,
      GIR_ConstrainSelectedInstOperands, /*InsnID*/0,
      GIR_EraseFromParent, /*InsnID*/0,
      // GIR_Coverage, 5536,
      GIR_Done,
    // Label 1857: @121032
    GIM_Try, /*On fail goto*//*Label 1858*/ GIMT_Encode4(121094), // Rule ID 3463 //
      GIM_CheckFeatures, GIMT_Encode2(GIFBS_EnableFlatScratch_HasFlatScratchInsts_HasFlatScratchSVSMode),
      GIM_CheckMemoryAddressSpace, /*MI*/0, /*MMO*/0, /*NumAddrSpace*/1, /*AddrSpace*/5,
      GIM_CheckAtomicOrdering, /*MI*/0, /*Order*/(uint8_t)AtomicOrdering::NotAtomic,
      GIM_CheckPointerToAny, /*MI*/0, /*Op*/1, /*SizeInBits*/0,
      GIM_CheckComplexPattern, /*MI*/0, /*Op*/1, /*Renderer*/GIMT_Encode2(0), GIMT_Encode2(GICP_gi_flat_scratch_svaddr),
      // (st p2:{ *:[i32] }:$data, (ScratchSVAddr:{ *:[iPTR] } VGPR_32:{ *:[i32] }:$vaddr, SGPR_32:{ *:[i32] }:$saddr, i32:{ *:[i32] }:$offset))<<P:Predicate_unindexedstore>><<P:Predicate_store_private>>  =>  (SCRATCH_STORE_DWORD_SVS anonymous_15037:{ *:[i32] }:$data, ?:{ *:[i32] }:$vaddr, ?:{ *:[i32] }:$saddr, ?:{ *:[i32] }:$offset)
      GIR_BuildMI, /*InsnID*/0, /*Opcode*/GIMT_Encode2(AMDGPU::SCRATCH_STORE_DWORD_SVS),
      GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/0, // data
      GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/0, // vaddr
      GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/1, // saddr
      GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/2, // offset
      GIR_AddImm8, /*InsnID*/0, /*Imm*/0,
      GIR_MergeMemOperands, /*InsnID*/0, /*NumInsns*/1, /*MergeInsnID's*/0,
      GIR_ConstrainSelectedInstOperands, /*InsnID*/0,
      GIR_EraseFromParent, /*InsnID*/0,
      // GIR_Coverage, 3463,
      GIR_Done,
    // Label 1858: @121094
    GIM_Try, /*On fail goto*//*Label 1859*/ GIMT_Encode4(121151), // Rule ID 3462 //
      GIM_CheckFeatures, GIMT_Encode2(GIFBS_EnableFlatScratch_HasFlatScratchInsts),
      GIM_CheckMemoryAddressSpace, /*MI*/0, /*MMO*/0, /*NumAddrSpace*/1, /*AddrSpace*/5,
      GIM_CheckAtomicOrdering, /*MI*/0, /*Order*/(uint8_t)AtomicOrdering::NotAtomic,
      GIM_CheckPointerToAny, /*MI*/0, /*Op*/1, /*SizeInBits*/0,
      GIM_CheckComplexPattern, /*MI*/0, /*Op*/1, /*Renderer*/GIMT_Encode2(0), GIMT_Encode2(GICP_gi_flat_scratch_saddr),
      // (st p2:{ *:[i32] }:$data, (ScratchSAddr:{ *:[iPTR] } SGPR_32:{ *:[i32] }:$saddr, i32:{ *:[i32] }:$offset))<<P:Predicate_unindexedstore>><<P:Predicate_store_private>>  =>  (SCRATCH_STORE_DWORD_SADDR anonymous_15037:{ *:[i32] }:$data, ?:{ *:[i32] }:$saddr, ?:{ *:[i32] }:$offset)
      GIR_BuildMI, /*InsnID*/0, /*Opcode*/GIMT_Encode2(AMDGPU::SCRATCH_STORE_DWORD_SADDR),
      GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/0, // data
      GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/0, // saddr
      GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/1, // offset
      GIR_AddImm8, /*InsnID*/0, /*Imm*/0,
      GIR_MergeMemOperands, /*InsnID*/0, /*NumInsns*/1, /*MergeInsnID's*/0,
      GIR_ConstrainSelectedInstOperands, /*InsnID*/0,
      GIR_EraseFromParent, /*InsnID*/0,
      // GIR_Coverage, 3462,
      GIR_Done,
    // Label 1859: @121151
    GIM_Try, /*On fail goto*//*Label 1860*/ GIMT_Encode4(121208), // Rule ID 3461 //
      GIM_CheckFeatures, GIMT_Encode2(GIFBS_EnableFlatScratch_HasFlatScratchInsts),
      GIM_CheckMemoryAddressSpace, /*MI*/0, /*MMO*/0, /*NumAddrSpace*/1, /*AddrSpace*/5,
      GIM_CheckAtomicOrdering, /*MI*/0, /*Order*/(uint8_t)AtomicOrdering::NotAtomic,
      GIM_CheckPointerToAny, /*MI*/0, /*Op*/1, /*SizeInBits*/0,
      GIM_CheckComplexPattern, /*MI*/0, /*Op*/1, /*Renderer*/GIMT_Encode2(0), GIMT_Encode2(GICP_gi_flat_scratch_offset),
      // (st p2:{ *:[i32] }:$data, (ScratchOffset:{ *:[iPTR] } VGPR_32:{ *:[i32] }:$vaddr, i32:{ *:[i32] }:$offset))<<P:Predicate_unindexedstore>><<P:Predicate_store_private>>  =>  (SCRATCH_STORE_DWORD anonymous_15037:{ *:[i32] }:$data, ?:{ *:[i32] }:$vaddr, ?:{ *:[i32] }:$offset)
      GIR_BuildMI, /*InsnID*/0, /*Opcode*/GIMT_Encode2(AMDGPU::SCRATCH_STORE_DWORD),
      GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/0, // data
      GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/0, // vaddr
      GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/1, // offset
      GIR_AddImm8, /*InsnID*/0, /*Imm*/0,
      GIR_MergeMemOperands, /*InsnID*/0, /*NumInsns*/1, /*MergeInsnID's*/0,
      GIR_ConstrainSelectedInstOperands, /*InsnID*/0,
      GIR_EraseFromParent, /*InsnID*/0,
      // GIR_Coverage, 3461,
      GIR_Done,
    // Label 1860: @121208
    GIM_Try, /*On fail goto*//*Label 1861*/ GIMT_Encode4(121278), // Rule ID 3822 //
      GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasUnrestrictedSOffset),
      GIM_CheckMemoryAddressSpace, /*MI*/0, /*MMO*/0, /*NumAddrSpace*/1, /*AddrSpace*/1,
      GIM_CheckAtomicOrdering, /*MI*/0, /*Order*/(uint8_t)AtomicOrdering::NotAtomic,
      GIM_CheckPointerToAny, /*MI*/0, /*Op*/1, /*SizeInBits*/0,
      GIM_CheckComplexPattern, /*MI*/0, /*Op*/1, /*Renderer*/GIMT_Encode2(0), GIMT_Encode2(GICP_gi_mubuf_addr64),
      // (st p2:{ *:[i32] }:$vdata, (MUBUFAddr64:{ *:[iPTR] } v4i32:{ *:[v4i32] }:$srsrc, i64:{ *:[i64] }:$vaddr, i32:{ *:[i32] }:$soffset, i32:{ *:[i32] }:$offset))<<P:Predicate_unindexedstore>><<P:Predicate_store_global>>  =>  (BUFFER_STORE_DWORD_ADDR64 p2:{ *:[i32] }:$vdata, i64:{ *:[i64] }:$vaddr, v4i32:{ *:[v4i32] }:$srsrc, i32:{ *:[i32] }:$soffset, i32:{ *:[i32] }:$offset)
      GIR_BuildMI, /*InsnID*/0, /*Opcode*/GIMT_Encode2(AMDGPU::BUFFER_STORE_DWORD_ADDR64),
      GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/0, // vdata
      GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/1, // vaddr
      GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/0, // srsrc
      GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/2, // soffset
      GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/3, // offset
      GIR_AddImm8, /*InsnID*/0, /*Imm*/0,
      GIR_AddImm8, /*InsnID*/0, /*Imm*/0,
      GIR_MergeMemOperands, /*InsnID*/0, /*NumInsns*/1, /*MergeInsnID's*/0,
      GIR_ConstrainSelectedInstOperands, /*InsnID*/0,
      GIR_EraseFromParent, /*InsnID*/0,
      // GIR_Coverage, 3822,
      GIR_Done,
    // Label 1861: @121278
    GIM_Try, /*On fail goto*//*Label 1862*/ GIMT_Encode4(121345), // Rule ID 3824 //
      GIM_CheckMemoryAddressSpace, /*MI*/0, /*MMO*/0, /*NumAddrSpace*/1, /*AddrSpace*/1,
      GIM_CheckAtomicOrdering, /*MI*/0, /*Order*/(uint8_t)AtomicOrdering::NotAtomic,
      GIM_CheckPointerToAny, /*MI*/0, /*Op*/1, /*SizeInBits*/0,
      GIM_CheckComplexPattern, /*MI*/0, /*Op*/1, /*Renderer*/GIMT_Encode2(0), GIMT_Encode2(GICP_gi_mubuf_addr64),
      // (st p2:{ *:[i32] }:$vdata, (MUBUFAddr64:{ *:[iPTR] } v4i32:{ *:[v4i32] }:$srsrc, i64:{ *:[i64] }:$vaddr, i32:{ *:[i32] }:$soffset, i32:{ *:[i32] }:$offset))<<P:Predicate_unindexedstore>><<P:Predicate_store_global>>  =>  (BUFFER_STORE_DWORD_VBUFFER_ADDR64 p2:{ *:[i32] }:$vdata, i64:{ *:[i64] }:$vaddr, v4i32:{ *:[v4i32] }:$srsrc, i32:{ *:[i32] }:$soffset, i32:{ *:[i32] }:$offset)
      GIR_BuildMI, /*InsnID*/0, /*Opcode*/GIMT_Encode2(AMDGPU::BUFFER_STORE_DWORD_VBUFFER_ADDR64),
      GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/0, // vdata
      GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/1, // vaddr
      GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/0, // srsrc
      GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/2, // soffset
      GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/3, // offset
      GIR_AddImm8, /*InsnID*/0, /*Imm*/0,
      GIR_AddImm8, /*InsnID*/0, /*Imm*/0,
      GIR_MergeMemOperands, /*InsnID*/0, /*NumInsns*/1, /*MergeInsnID's*/0,
      GIR_ConstrainSelectedInstOperands, /*InsnID*/0,
      GIR_EraseFromParent, /*InsnID*/0,
      // GIR_Coverage, 3824,
      GIR_Done,
    // Label 1862: @121345
    GIM_Try, /*On fail goto*//*Label 1863*/ GIMT_Encode4(121415), // Rule ID 5533 //
      GIM_CheckFeatures, GIMT_Encode2(GIFBS_DisableFlatScratch_HasUnrestrictedSOffset),
      GIM_CheckMemoryAddressSpace, /*MI*/0, /*MMO*/0, /*NumAddrSpace*/1, /*AddrSpace*/5,
      GIM_CheckAtomicOrdering, /*MI*/0, /*Order*/(uint8_t)AtomicOrdering::NotAtomic,
      GIM_CheckPointerToAny, /*MI*/0, /*Op*/1, /*SizeInBits*/0,
      GIM_CheckComplexPattern, /*MI*/0, /*Op*/1, /*Renderer*/GIMT_Encode2(0), GIMT_Encode2(GICP_gi_mubuf_scratch_offen),
      // (st p2:{ *:[i32] }:$value, (MUBUFScratchOffen:{ *:[iPTR] } v4i32:{ *:[v4i32] }:$srsrc, i32:{ *:[i32] }:$vaddr, i32:{ *:[i32] }:$soffset, i32:{ *:[i32] }:$offset))<<P:Predicate_unindexedstore>><<P:Predicate_store_private>>  =>  (BUFFER_STORE_DWORD_OFFEN VGPR_32:{ *:[i32] }:$value, ?:{ *:[i32] }:$vaddr, ?:{ *:[v4i32] }:$srsrc, ?:{ *:[i32] }:$soffset, ?:{ *:[i32] }:$offset, 0:{ *:[i32] }, 0:{ *:[i1] })
      GIR_BuildMI, /*InsnID*/0, /*Opcode*/GIMT_Encode2(AMDGPU::BUFFER_STORE_DWORD_OFFEN),
      GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/0, // value
      GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/1, // vaddr
      GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/0, // srsrc
      GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/2, // soffset
      GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/3, // offset
      GIR_AddImm8, /*InsnID*/0, /*Imm*/0,
      GIR_AddImm8, /*InsnID*/0, /*Imm*/0,
      GIR_MergeMemOperands, /*InsnID*/0, /*NumInsns*/1, /*MergeInsnID's*/0,
      GIR_ConstrainSelectedInstOperands, /*InsnID*/0,
      GIR_EraseFromParent, /*InsnID*/0,
      // GIR_Coverage, 5533,
      GIR_Done,
    // Label 1863: @121415
    GIM_Try, /*On fail goto*//*Label 1864*/ GIMT_Encode4(121485), // Rule ID 5535 //
      GIM_CheckFeatures, GIMT_Encode2(GIFBS_DisableFlatScratch),
      GIM_CheckMemoryAddressSpace, /*MI*/0, /*MMO*/0, /*NumAddrSpace*/1, /*AddrSpace*/5,
      GIM_CheckAtomicOrdering, /*MI*/0, /*Order*/(uint8_t)AtomicOrdering::NotAtomic,
      GIM_CheckPointerToAny, /*MI*/0, /*Op*/1, /*SizeInBits*/0,
      GIM_CheckComplexPattern, /*MI*/0, /*Op*/1, /*Renderer*/GIMT_Encode2(0), GIMT_Encode2(GICP_gi_mubuf_scratch_offen),
      // (st p2:{ *:[i32] }:$value, (MUBUFScratchOffen:{ *:[iPTR] } v4i32:{ *:[v4i32] }:$srsrc, i32:{ *:[i32] }:$vaddr, i32:{ *:[i32] }:$soffset, i32:{ *:[i32] }:$offset))<<P:Predicate_unindexedstore>><<P:Predicate_store_private>>  =>  (BUFFER_STORE_DWORD_VBUFFER_OFFEN VGPR_32:{ *:[i32] }:$value, ?:{ *:[i32] }:$vaddr, ?:{ *:[v4i32] }:$srsrc, ?:{ *:[i32] }:$soffset, ?:{ *:[i32] }:$offset, 0:{ *:[i32] }, 0:{ *:[i1] })
      GIR_BuildMI, /*InsnID*/0, /*Opcode*/GIMT_Encode2(AMDGPU::BUFFER_STORE_DWORD_VBUFFER_OFFEN),
      GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/0, // value
      GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/1, // vaddr
      GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/0, // srsrc
      GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/2, // soffset
      GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/3, // offset
      GIR_AddImm8, /*InsnID*/0, /*Imm*/0,
      GIR_AddImm8, /*InsnID*/0, /*Imm*/0,
      GIR_MergeMemOperands, /*InsnID*/0, /*NumInsns*/1, /*MergeInsnID's*/0,
      GIR_ConstrainSelectedInstOperands, /*InsnID*/0,
      GIR_EraseFromParent, /*InsnID*/0,
      // GIR_Coverage, 5535,
      GIR_Done,
    // Label 1864: @121485
    GIM_Try, /*On fail goto*//*Label 1865*/ GIMT_Encode4(121550), // Rule ID 3821 //
      GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasUnrestrictedSOffset),
      GIM_CheckMemoryAddressSpace, /*MI*/0, /*MMO*/0, /*NumAddrSpace*/1, /*AddrSpace*/1,
      GIM_CheckAtomicOrdering, /*MI*/0, /*Order*/(uint8_t)AtomicOrdering::NotAtomic,
      GIM_CheckPointerToAny, /*MI*/0, /*Op*/1, /*SizeInBits*/0,
      GIM_CheckComplexPattern, /*MI*/0, /*Op*/1, /*Renderer*/GIMT_Encode2(0), GIMT_Encode2(GICP_gi_mubuf_offset),
      // (st p2:{ *:[i32] }:$vdata, (MUBUFOffset:{ *:[iPTR] } v4i32:{ *:[v4i32] }:$srsrc, i32:{ *:[i32] }:$soffset, i32:{ *:[i32] }:$offset))<<P:Predicate_unindexedstore>><<P:Predicate_store_global>>  =>  (BUFFER_STORE_DWORD_OFFSET p2:{ *:[i32] }:$vdata, v4i32:{ *:[v4i32] }:$srsrc, i32:{ *:[i32] }:$soffset, i32:{ *:[i32] }:$offset)
      GIR_BuildMI, /*InsnID*/0, /*Opcode*/GIMT_Encode2(AMDGPU::BUFFER_STORE_DWORD_OFFSET),
      GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/0, // vdata
      GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/0, // srsrc
      GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/1, // soffset
      GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/2, // offset
      GIR_AddImm8, /*InsnID*/0, /*Imm*/0,
      GIR_AddImm8, /*InsnID*/0, /*Imm*/0,
      GIR_MergeMemOperands, /*InsnID*/0, /*NumInsns*/1, /*MergeInsnID's*/0,
      GIR_ConstrainSelectedInstOperands, /*InsnID*/0,
      GIR_EraseFromParent, /*InsnID*/0,
      // GIR_Coverage, 3821,
      GIR_Done,
    // Label 1865: @121550
    GIM_Try, /*On fail goto*//*Label 1866*/ GIMT_Encode4(121612), // Rule ID 3823 //
      GIM_CheckMemoryAddressSpace, /*MI*/0, /*MMO*/0, /*NumAddrSpace*/1, /*AddrSpace*/1,
      GIM_CheckAtomicOrdering, /*MI*/0, /*Order*/(uint8_t)AtomicOrdering::NotAtomic,
      GIM_CheckPointerToAny, /*MI*/0, /*Op*/1, /*SizeInBits*/0,
      GIM_CheckComplexPattern, /*MI*/0, /*Op*/1, /*Renderer*/GIMT_Encode2(0), GIMT_Encode2(GICP_gi_mubuf_offset),
      // (st p2:{ *:[i32] }:$vdata, (MUBUFOffset:{ *:[iPTR] } v4i32:{ *:[v4i32] }:$srsrc, i32:{ *:[i32] }:$soffset, i32:{ *:[i32] }:$offset))<<P:Predicate_unindexedstore>><<P:Predicate_store_global>>  =>  (BUFFER_STORE_DWORD_VBUFFER_OFFSET p2:{ *:[i32] }:$vdata, v4i32:{ *:[v4i32] }:$srsrc, i32:{ *:[i32] }:$soffset, i32:{ *:[i32] }:$offset)
      GIR_BuildMI, /*InsnID*/0, /*Opcode*/GIMT_Encode2(AMDGPU::BUFFER_STORE_DWORD_VBUFFER_OFFSET),
      GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/0, // vdata
      GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/0, // srsrc
      GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/1, // soffset
      GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/2, // offset
      GIR_AddImm8, /*InsnID*/0, /*Imm*/0,
      GIR_AddImm8, /*InsnID*/0, /*Imm*/0,
      GIR_MergeMemOperands, /*InsnID*/0, /*NumInsns*/1, /*MergeInsnID's*/0,
      GIR_ConstrainSelectedInstOperands, /*InsnID*/0,
      GIR_EraseFromParent, /*InsnID*/0,
      // GIR_Coverage, 3823,
      GIR_Done,
    // Label 1866: @121612
    GIM_Try, /*On fail goto*//*Label 1867*/ GIMT_Encode4(121673), // Rule ID 6649 //
      GIM_CheckFeatures, GIMT_Encode2(GIFBS_LDSRequiresM0Init),
      GIM_CheckMemorySizeEqualToLLT, /*MI*/0, /*MMO*/0, /*OpIdx*/0,
      GIM_CheckMemoryAddressSpace, /*MI*/0, /*MMO*/0, /*NumAddrSpace*/1, /*AddrSpace*/3,
      GIM_CheckAtomicOrdering, /*MI*/0, /*Order*/(uint8_t)AtomicOrdering::NotAtomic,
      GIM_CheckPointerToAny, /*MI*/0, /*Op*/1, /*SizeInBits*/0,
      GIM_CheckComplexPattern, /*MI*/0, /*Op*/1, /*Renderer*/GIMT_Encode2(0), GIMT_Encode2(GICP_gi_ds_1addr_1offset),
      // (AMDGPUst_glue p2:{ *:[i32] }:$value, (DS1Addr1Offset:{ *:[iPTR] } i32:{ *:[i32] }:$ptr, i32:{ *:[i32] }:$offset))<<P:Predicate_unindexedstore_glue>><<P:Predicate_store_glue>><<P:Predicate_store_local_m0>>  =>  (DS_WRITE_B32 ?:{ *:[i32] }:$ptr, anonymous_15037:{ *:[i32] }:$value, offset:{ *:[i32] }:$offset, 0:{ *:[i1] })
      GIR_BuildMI, /*InsnID*/0, /*Opcode*/GIMT_Encode2(AMDGPU::DS_WRITE_B32),
      GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/0, // ptr
      GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/0, // value
      GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/1, // offset
      GIR_AddImm8, /*InsnID*/0, /*Imm*/0,
      GIR_MergeMemOperands, /*InsnID*/0, /*NumInsns*/1, /*MergeInsnID's*/0,
      GIR_ConstrainSelectedInstOperands, /*InsnID*/0,
      GIR_EraseFromParent, /*InsnID*/0,
      // GIR_Coverage, 6649,
      GIR_Done,
    // Label 1867: @121673
    GIM_Try, /*On fail goto*//*Label 1868*/ GIMT_Encode4(121730), // Rule ID 6650 //
      GIM_CheckFeatures, GIMT_Encode2(GIFBS_NotLDSRequiresM0Init),
      GIM_CheckMemoryAddressSpace, /*MI*/0, /*MMO*/0, /*NumAddrSpace*/1, /*AddrSpace*/3,
      GIM_CheckAtomicOrdering, /*MI*/0, /*Order*/(uint8_t)AtomicOrdering::NotAtomic,
      GIM_CheckPointerToAny, /*MI*/0, /*Op*/1, /*SizeInBits*/0,
      GIM_CheckComplexPattern, /*MI*/0, /*Op*/1, /*Renderer*/GIMT_Encode2(0), GIMT_Encode2(GICP_gi_ds_1addr_1offset),
      // (st p2:{ *:[i32] }:$value, (DS1Addr1Offset:{ *:[iPTR] } i32:{ *:[i32] }:$ptr, i32:{ *:[i32] }:$offset))<<P:Predicate_unindexedstore>><<P:Predicate_store_local>>  =>  (DS_WRITE_B32_gfx9 ?:{ *:[i32] }:$ptr, anonymous_15037:{ *:[i32] }:$value, offset:{ *:[i32] }:$offset, 0:{ *:[i1] })
      GIR_BuildMI, /*InsnID*/0, /*Opcode*/GIMT_Encode2(AMDGPU::DS_WRITE_B32_gfx9),
      GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/0, // ptr
      GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/0, // value
      GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/1, // offset
      GIR_AddImm8, /*InsnID*/0, /*Imm*/0,
      GIR_MergeMemOperands, /*InsnID*/0, /*NumInsns*/1, /*MergeInsnID's*/0,
      GIR_ConstrainSelectedInstOperands, /*InsnID*/0,
      GIR_EraseFromParent, /*InsnID*/0,
      // GIR_Coverage, 6650,
      GIR_Done,
    // Label 1868: @121730
    GIM_Try, /*On fail goto*//*Label 1869*/ GIMT_Encode4(121792), // Rule ID 3015 //
      GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasFlatGlobalInsts),
      GIM_CheckMemoryAddressSpace, /*MI*/0, /*MMO*/0, /*NumAddrSpace*/1, /*AddrSpace*/1,
      GIM_CheckAtomicOrdering, /*MI*/0, /*Order*/(uint8_t)AtomicOrdering::NotAtomic,
      GIM_CheckPointerToAny, /*MI*/0, /*Op*/1, /*SizeInBits*/0,
      GIM_CheckComplexPattern, /*MI*/0, /*Op*/1, /*Renderer*/GIMT_Encode2(0), GIMT_Encode2(GICP_gi_global_saddr),
      // (st p2:{ *:[i32] }:$data, (GlobalSAddr:{ *:[iPTR] } SReg_64:{ *:[i64] }:$saddr, VGPR_32:{ *:[i32] }:$voffset, i32:{ *:[i32] }:$offset))<<P:Predicate_unindexedstore>><<P:Predicate_store_global>>  =>  (GLOBAL_STORE_DWORD_SADDR ?:{ *:[i32] }:$voffset, anonymous_15037:{ *:[i32] }:$data, ?:{ *:[i64] }:$saddr, ?:{ *:[i32] }:$offset)
      GIR_BuildMI, /*InsnID*/0, /*Opcode*/GIMT_Encode2(AMDGPU::GLOBAL_STORE_DWORD_SADDR),
      GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/1, // voffset
      GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/0, // data
      GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/0, // saddr
      GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/2, // offset
      GIR_AddImm8, /*InsnID*/0, /*Imm*/0,
      GIR_MergeMemOperands, /*InsnID*/0, /*NumInsns*/1, /*MergeInsnID's*/0,
      GIR_ConstrainSelectedInstOperands, /*InsnID*/0,
      GIR_EraseFromParent, /*InsnID*/0,
      // GIR_Coverage, 3015,
      GIR_Done,
    // Label 1869: @121792
    GIM_Try, /*On fail goto*//*Label 1870*/ GIMT_Encode4(121849), // Rule ID 3014 //
      GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasFlatGlobalInsts),
      GIM_CheckMemoryAddressSpace, /*MI*/0, /*MMO*/0, /*NumAddrSpace*/1, /*AddrSpace*/1,
      GIM_CheckAtomicOrdering, /*MI*/0, /*Order*/(uint8_t)AtomicOrdering::NotAtomic,
      GIM_CheckPointerToAny, /*MI*/0, /*Op*/1, /*SizeInBits*/0,
      GIM_CheckComplexPattern, /*MI*/0, /*Op*/1, /*Renderer*/GIMT_Encode2(0), GIMT_Encode2(GICP_gi_global_offset),
      // (st p2:{ *:[i32] }:$data, (GlobalOffset:{ *:[iPTR] } i64:{ *:[i64] }:$vaddr, i32:{ *:[i32] }:$offset))<<P:Predicate_unindexedstore>><<P:Predicate_store_global>>  =>  (GLOBAL_STORE_DWORD ?:{ *:[i64] }:$vaddr, anonymous_15037:{ *:[i32] }:$data, ?:{ *:[i32] }:$offset)
      GIR_BuildMI, /*InsnID*/0, /*Opcode*/GIMT_Encode2(AMDGPU::GLOBAL_STORE_DWORD),
      GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/0, // vaddr
      GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/0, // data
      GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/1, // offset
      GIR_AddImm8, /*InsnID*/0, /*Imm*/0,
      GIR_MergeMemOperands, /*InsnID*/0, /*NumInsns*/1, /*MergeInsnID's*/0,
      GIR_ConstrainSelectedInstOperands, /*InsnID*/0,
      GIR_EraseFromParent, /*InsnID*/0,
      // GIR_Coverage, 3014,
      GIR_Done,
    // Label 1870: @121849
    GIM_Try, /*On fail goto*//*Label 1871*/ GIMT_Encode4(121907), // Rule ID 2781 //
      GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasFlatAddressSpace),
      GIM_CheckMemoryAddressSpace, /*MI*/0, /*MMO*/0, /*NumAddrSpace*/2, /*AddrSpace*/0, /*AddrSpace*/1,
      GIM_CheckAtomicOrdering, /*MI*/0, /*Order*/(uint8_t)AtomicOrdering::NotAtomic,
      GIM_CheckPointerToAny, /*MI*/0, /*Op*/1, /*SizeInBits*/0,
      GIM_CheckComplexPattern, /*MI*/0, /*Op*/1, /*Renderer*/GIMT_Encode2(0), GIMT_Encode2(GICP_gi_flat_offset),
      // (st p2:{ *:[i32] }:$data, (FlatOffset:{ *:[iPTR] } i64:{ *:[i64] }:$vaddr, i32:{ *:[i32] }:$offset))<<P:Predicate_unindexedstore>><<P:Predicate_store_flat>>  =>  (FLAT_STORE_DWORD ?:{ *:[i64] }:$vaddr, anonymous_15037:{ *:[i32] }:$data, ?:{ *:[i32] }:$offset)
      GIR_BuildMI, /*InsnID*/0, /*Opcode*/GIMT_Encode2(AMDGPU::FLAT_STORE_DWORD),
      GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/0, // vaddr
      GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/0, // data
      GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/1, // offset
      GIR_AddImm8, /*InsnID*/0, /*Imm*/0,
      GIR_MergeMemOperands, /*InsnID*/0, /*NumInsns*/1, /*MergeInsnID's*/0,
      GIR_ConstrainSelectedInstOperands, /*InsnID*/0,
      GIR_EraseFromParent, /*InsnID*/0,
      // GIR_Coverage, 2781,
      GIR_Done,
    // Label 1871: @121907
    GIM_Reject,
    // Label 1809: @121908
    GIM_Try, /*On fail goto*//*Label 1872*/ GIMT_Encode4(121973), // Rule ID 5538 //
      GIM_CheckFeatures, GIMT_Encode2(GIFBS_DisableFlatScratch_HasUnrestrictedSOffset),
      GIM_CheckMemoryAddressSpace, /*MI*/0, /*MMO*/0, /*NumAddrSpace*/1, /*AddrSpace*/5,
      GIM_CheckAtomicOrdering, /*MI*/0, /*Order*/(uint8_t)AtomicOrdering::NotAtomic,
      GIM_CheckPointerToAny, /*MI*/0, /*Op*/1, /*SizeInBits*/0,
      GIM_CheckComplexPattern, /*MI*/0, /*Op*/1, /*Renderer*/GIMT_Encode2(0), GIMT_Encode2(GICP_gi_mubuf_scratch_offset),
      // (st p3:{ *:[i32] }:$value, (MUBUFScratchOffset:{ *:[iPTR] } v4i32:{ *:[v4i32] }:$srsrc, i32:{ *:[i32] }:$soffset, i32:{ *:[i32] }:$offset))<<P:Predicate_unindexedstore>><<P:Predicate_store_private>>  =>  (BUFFER_STORE_DWORD_OFFSET VGPR_32:{ *:[i32] }:$value, ?:{ *:[v4i32] }:$srsrc, ?:{ *:[i32] }:$soffset, ?:{ *:[i32] }:$offset, 0:{ *:[i32] }, 0:{ *:[i1] })
      GIR_BuildMI, /*InsnID*/0, /*Opcode*/GIMT_Encode2(AMDGPU::BUFFER_STORE_DWORD_OFFSET),
      GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/0, // value
      GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/0, // srsrc
      GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/1, // soffset
      GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/2, // offset
      GIR_AddImm8, /*InsnID*/0, /*Imm*/0,
      GIR_AddImm8, /*InsnID*/0, /*Imm*/0,
      GIR_MergeMemOperands, /*InsnID*/0, /*NumInsns*/1, /*MergeInsnID's*/0,
      GIR_ConstrainSelectedInstOperands, /*InsnID*/0,
      GIR_EraseFromParent, /*InsnID*/0,
      // GIR_Coverage, 5538,
      GIR_Done,
    // Label 1872: @121973
    GIM_Try, /*On fail goto*//*Label 1873*/ GIMT_Encode4(122038), // Rule ID 5540 //
      GIM_CheckFeatures, GIMT_Encode2(GIFBS_DisableFlatScratch),
      GIM_CheckMemoryAddressSpace, /*MI*/0, /*MMO*/0, /*NumAddrSpace*/1, /*AddrSpace*/5,
      GIM_CheckAtomicOrdering, /*MI*/0, /*Order*/(uint8_t)AtomicOrdering::NotAtomic,
      GIM_CheckPointerToAny, /*MI*/0, /*Op*/1, /*SizeInBits*/0,
      GIM_CheckComplexPattern, /*MI*/0, /*Op*/1, /*Renderer*/GIMT_Encode2(0), GIMT_Encode2(GICP_gi_mubuf_scratch_offset),
      // (st p3:{ *:[i32] }:$value, (MUBUFScratchOffset:{ *:[iPTR] } v4i32:{ *:[v4i32] }:$srsrc, i32:{ *:[i32] }:$soffset, i32:{ *:[i32] }:$offset))<<P:Predicate_unindexedstore>><<P:Predicate_store_private>>  =>  (BUFFER_STORE_DWORD_VBUFFER_OFFSET VGPR_32:{ *:[i32] }:$value, ?:{ *:[v4i32] }:$srsrc, ?:{ *:[i32] }:$soffset, ?:{ *:[i32] }:$offset, 0:{ *:[i32] }, 0:{ *:[i1] })
      GIR_BuildMI, /*InsnID*/0, /*Opcode*/GIMT_Encode2(AMDGPU::BUFFER_STORE_DWORD_VBUFFER_OFFSET),
      GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/0, // value
      GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/0, // srsrc
      GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/1, // soffset
      GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/2, // offset
      GIR_AddImm8, /*InsnID*/0, /*Imm*/0,
      GIR_AddImm8, /*InsnID*/0, /*Imm*/0,
      GIR_MergeMemOperands, /*InsnID*/0, /*NumInsns*/1, /*MergeInsnID's*/0,
      GIR_ConstrainSelectedInstOperands, /*InsnID*/0,
      GIR_EraseFromParent, /*InsnID*/0,
      // GIR_Coverage, 5540,
      GIR_Done,
    // Label 1873: @122038
    GIM_Try, /*On fail goto*//*Label 1874*/ GIMT_Encode4(122100), // Rule ID 3469 //
      GIM_CheckFeatures, GIMT_Encode2(GIFBS_EnableFlatScratch_HasFlatScratchInsts_HasFlatScratchSVSMode),
      GIM_CheckMemoryAddressSpace, /*MI*/0, /*MMO*/0, /*NumAddrSpace*/1, /*AddrSpace*/5,
      GIM_CheckAtomicOrdering, /*MI*/0, /*Order*/(uint8_t)AtomicOrdering::NotAtomic,
      GIM_CheckPointerToAny, /*MI*/0, /*Op*/1, /*SizeInBits*/0,
      GIM_CheckComplexPattern, /*MI*/0, /*Op*/1, /*Renderer*/GIMT_Encode2(0), GIMT_Encode2(GICP_gi_flat_scratch_svaddr),
      // (st p3:{ *:[i32] }:$data, (ScratchSVAddr:{ *:[iPTR] } VGPR_32:{ *:[i32] }:$vaddr, SGPR_32:{ *:[i32] }:$saddr, i32:{ *:[i32] }:$offset))<<P:Predicate_unindexedstore>><<P:Predicate_store_private>>  =>  (SCRATCH_STORE_DWORD_SVS anonymous_15037:{ *:[i32] }:$data, ?:{ *:[i32] }:$vaddr, ?:{ *:[i32] }:$saddr, ?:{ *:[i32] }:$offset)
      GIR_BuildMI, /*InsnID*/0, /*Opcode*/GIMT_Encode2(AMDGPU::SCRATCH_STORE_DWORD_SVS),
      GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/0, // data
      GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/0, // vaddr
      GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/1, // saddr
      GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/2, // offset
      GIR_AddImm8, /*InsnID*/0, /*Imm*/0,
      GIR_MergeMemOperands, /*InsnID*/0, /*NumInsns*/1, /*MergeInsnID's*/0,
      GIR_ConstrainSelectedInstOperands, /*InsnID*/0,
      GIR_EraseFromParent, /*InsnID*/0,
      // GIR_Coverage, 3469,
      GIR_Done,
    // Label 1874: @122100
    GIM_Try, /*On fail goto*//*Label 1875*/ GIMT_Encode4(122157), // Rule ID 3468 //
      GIM_CheckFeatures, GIMT_Encode2(GIFBS_EnableFlatScratch_HasFlatScratchInsts),
      GIM_CheckMemoryAddressSpace, /*MI*/0, /*MMO*/0, /*NumAddrSpace*/1, /*AddrSpace*/5,
      GIM_CheckAtomicOrdering, /*MI*/0, /*Order*/(uint8_t)AtomicOrdering::NotAtomic,
      GIM_CheckPointerToAny, /*MI*/0, /*Op*/1, /*SizeInBits*/0,
      GIM_CheckComplexPattern, /*MI*/0, /*Op*/1, /*Renderer*/GIMT_Encode2(0), GIMT_Encode2(GICP_gi_flat_scratch_saddr),
      // (st p3:{ *:[i32] }:$data, (ScratchSAddr:{ *:[iPTR] } SGPR_32:{ *:[i32] }:$saddr, i32:{ *:[i32] }:$offset))<<P:Predicate_unindexedstore>><<P:Predicate_store_private>>  =>  (SCRATCH_STORE_DWORD_SADDR anonymous_15037:{ *:[i32] }:$data, ?:{ *:[i32] }:$saddr, ?:{ *:[i32] }:$offset)
      GIR_BuildMI, /*InsnID*/0, /*Opcode*/GIMT_Encode2(AMDGPU::SCRATCH_STORE_DWORD_SADDR),
      GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/0, // data
      GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/0, // saddr
      GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/1, // offset
      GIR_AddImm8, /*InsnID*/0, /*Imm*/0,
      GIR_MergeMemOperands, /*InsnID*/0, /*NumInsns*/1, /*MergeInsnID's*/0,
      GIR_ConstrainSelectedInstOperands, /*InsnID*/0,
      GIR_EraseFromParent, /*InsnID*/0,
      // GIR_Coverage, 3468,
      GIR_Done,
    // Label 1875: @122157
    GIM_Try, /*On fail goto*//*Label 1876*/ GIMT_Encode4(122214), // Rule ID 3467 //
      GIM_CheckFeatures, GIMT_Encode2(GIFBS_EnableFlatScratch_HasFlatScratchInsts),
      GIM_CheckMemoryAddressSpace, /*MI*/0, /*MMO*/0, /*NumAddrSpace*/1, /*AddrSpace*/5,
      GIM_CheckAtomicOrdering, /*MI*/0, /*Order*/(uint8_t)AtomicOrdering::NotAtomic,
      GIM_CheckPointerToAny, /*MI*/0, /*Op*/1, /*SizeInBits*/0,
      GIM_CheckComplexPattern, /*MI*/0, /*Op*/1, /*Renderer*/GIMT_Encode2(0), GIMT_Encode2(GICP_gi_flat_scratch_offset),
      // (st p3:{ *:[i32] }:$data, (ScratchOffset:{ *:[iPTR] } VGPR_32:{ *:[i32] }:$vaddr, i32:{ *:[i32] }:$offset))<<P:Predicate_unindexedstore>><<P:Predicate_store_private>>  =>  (SCRATCH_STORE_DWORD anonymous_15037:{ *:[i32] }:$data, ?:{ *:[i32] }:$vaddr, ?:{ *:[i32] }:$offset)
      GIR_BuildMI, /*InsnID*/0, /*Opcode*/GIMT_Encode2(AMDGPU::SCRATCH_STORE_DWORD),
      GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/0, // data
      GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/0, // vaddr
      GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/1, // offset
      GIR_AddImm8, /*InsnID*/0, /*Imm*/0,
      GIR_MergeMemOperands, /*InsnID*/0, /*NumInsns*/1, /*MergeInsnID's*/0,
      GIR_ConstrainSelectedInstOperands, /*InsnID*/0,
      GIR_EraseFromParent, /*InsnID*/0,
      // GIR_Coverage, 3467,
      GIR_Done,
    // Label 1876: @122214
    GIM_Try, /*On fail goto*//*Label 1877*/ GIMT_Encode4(122284), // Rule ID 3826 //
      GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasUnrestrictedSOffset),
      GIM_CheckMemoryAddressSpace, /*MI*/0, /*MMO*/0, /*NumAddrSpace*/1, /*AddrSpace*/1,
      GIM_CheckAtomicOrdering, /*MI*/0, /*Order*/(uint8_t)AtomicOrdering::NotAtomic,
      GIM_CheckPointerToAny, /*MI*/0, /*Op*/1, /*SizeInBits*/0,
      GIM_CheckComplexPattern, /*MI*/0, /*Op*/1, /*Renderer*/GIMT_Encode2(0), GIMT_Encode2(GICP_gi_mubuf_addr64),
      // (st p3:{ *:[i32] }:$vdata, (MUBUFAddr64:{ *:[iPTR] } v4i32:{ *:[v4i32] }:$srsrc, i64:{ *:[i64] }:$vaddr, i32:{ *:[i32] }:$soffset, i32:{ *:[i32] }:$offset))<<P:Predicate_unindexedstore>><<P:Predicate_store_global>>  =>  (BUFFER_STORE_DWORD_ADDR64 p3:{ *:[i32] }:$vdata, i64:{ *:[i64] }:$vaddr, v4i32:{ *:[v4i32] }:$srsrc, i32:{ *:[i32] }:$soffset, i32:{ *:[i32] }:$offset)
      GIR_BuildMI, /*InsnID*/0, /*Opcode*/GIMT_Encode2(AMDGPU::BUFFER_STORE_DWORD_ADDR64),
      GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/0, // vdata
      GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/1, // vaddr
      GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/0, // srsrc
      GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/2, // soffset
      GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/3, // offset
      GIR_AddImm8, /*InsnID*/0, /*Imm*/0,
      GIR_AddImm8, /*InsnID*/0, /*Imm*/0,
      GIR_MergeMemOperands, /*InsnID*/0, /*NumInsns*/1, /*MergeInsnID's*/0,
      GIR_ConstrainSelectedInstOperands, /*InsnID*/0,
      GIR_EraseFromParent, /*InsnID*/0,
      // GIR_Coverage, 3826,
      GIR_Done,
    // Label 1877: @122284
    GIM_Try, /*On fail goto*//*Label 1878*/ GIMT_Encode4(122351), // Rule ID 3828 //
      GIM_CheckMemoryAddressSpace, /*MI*/0, /*MMO*/0, /*NumAddrSpace*/1, /*AddrSpace*/1,
      GIM_CheckAtomicOrdering, /*MI*/0, /*Order*/(uint8_t)AtomicOrdering::NotAtomic,
      GIM_CheckPointerToAny, /*MI*/0, /*Op*/1, /*SizeInBits*/0,
      GIM_CheckComplexPattern, /*MI*/0, /*Op*/1, /*Renderer*/GIMT_Encode2(0), GIMT_Encode2(GICP_gi_mubuf_addr64),
      // (st p3:{ *:[i32] }:$vdata, (MUBUFAddr64:{ *:[iPTR] } v4i32:{ *:[v4i32] }:$srsrc, i64:{ *:[i64] }:$vaddr, i32:{ *:[i32] }:$soffset, i32:{ *:[i32] }:$offset))<<P:Predicate_unindexedstore>><<P:Predicate_store_global>>  =>  (BUFFER_STORE_DWORD_VBUFFER_ADDR64 p3:{ *:[i32] }:$vdata, i64:{ *:[i64] }:$vaddr, v4i32:{ *:[v4i32] }:$srsrc, i32:{ *:[i32] }:$soffset, i32:{ *:[i32] }:$offset)
      GIR_BuildMI, /*InsnID*/0, /*Opcode*/GIMT_Encode2(AMDGPU::BUFFER_STORE_DWORD_VBUFFER_ADDR64),
      GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/0, // vdata
      GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/1, // vaddr
      GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/0, // srsrc
      GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/2, // soffset
      GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/3, // offset
      GIR_AddImm8, /*InsnID*/0, /*Imm*/0,
      GIR_AddImm8, /*InsnID*/0, /*Imm*/0,
      GIR_MergeMemOperands, /*InsnID*/0, /*NumInsns*/1, /*MergeInsnID's*/0,
      GIR_ConstrainSelectedInstOperands, /*InsnID*/0,
      GIR_EraseFromParent, /*InsnID*/0,
      // GIR_Coverage, 3828,
      GIR_Done,
    // Label 1878: @122351
    GIM_Try, /*On fail goto*//*Label 1879*/ GIMT_Encode4(122421), // Rule ID 5537 //
      GIM_CheckFeatures, GIMT_Encode2(GIFBS_DisableFlatScratch_HasUnrestrictedSOffset),
      GIM_CheckMemoryAddressSpace, /*MI*/0, /*MMO*/0, /*NumAddrSpace*/1, /*AddrSpace*/5,
      GIM_CheckAtomicOrdering, /*MI*/0, /*Order*/(uint8_t)AtomicOrdering::NotAtomic,
      GIM_CheckPointerToAny, /*MI*/0, /*Op*/1, /*SizeInBits*/0,
      GIM_CheckComplexPattern, /*MI*/0, /*Op*/1, /*Renderer*/GIMT_Encode2(0), GIMT_Encode2(GICP_gi_mubuf_scratch_offen),
      // (st p3:{ *:[i32] }:$value, (MUBUFScratchOffen:{ *:[iPTR] } v4i32:{ *:[v4i32] }:$srsrc, i32:{ *:[i32] }:$vaddr, i32:{ *:[i32] }:$soffset, i32:{ *:[i32] }:$offset))<<P:Predicate_unindexedstore>><<P:Predicate_store_private>>  =>  (BUFFER_STORE_DWORD_OFFEN VGPR_32:{ *:[i32] }:$value, ?:{ *:[i32] }:$vaddr, ?:{ *:[v4i32] }:$srsrc, ?:{ *:[i32] }:$soffset, ?:{ *:[i32] }:$offset, 0:{ *:[i32] }, 0:{ *:[i1] })
      GIR_BuildMI, /*InsnID*/0, /*Opcode*/GIMT_Encode2(AMDGPU::BUFFER_STORE_DWORD_OFFEN),
      GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/0, // value
      GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/1, // vaddr
      GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/0, // srsrc
      GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/2, // soffset
      GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/3, // offset
      GIR_AddImm8, /*InsnID*/0, /*Imm*/0,
      GIR_AddImm8, /*InsnID*/0, /*Imm*/0,
      GIR_MergeMemOperands, /*InsnID*/0, /*NumInsns*/1, /*MergeInsnID's*/0,
      GIR_ConstrainSelectedInstOperands, /*InsnID*/0,
      GIR_EraseFromParent, /*InsnID*/0,
      // GIR_Coverage, 5537,
      GIR_Done,
    // Label 1879: @122421
    GIM_Try, /*On fail goto*//*Label 1880*/ GIMT_Encode4(122491), // Rule ID 5539 //
      GIM_CheckFeatures, GIMT_Encode2(GIFBS_DisableFlatScratch),
      GIM_CheckMemoryAddressSpace, /*MI*/0, /*MMO*/0, /*NumAddrSpace*/1, /*AddrSpace*/5,
      GIM_CheckAtomicOrdering, /*MI*/0, /*Order*/(uint8_t)AtomicOrdering::NotAtomic,
      GIM_CheckPointerToAny, /*MI*/0, /*Op*/1, /*SizeInBits*/0,
      GIM_CheckComplexPattern, /*MI*/0, /*Op*/1, /*Renderer*/GIMT_Encode2(0), GIMT_Encode2(GICP_gi_mubuf_scratch_offen),
      // (st p3:{ *:[i32] }:$value, (MUBUFScratchOffen:{ *:[iPTR] } v4i32:{ *:[v4i32] }:$srsrc, i32:{ *:[i32] }:$vaddr, i32:{ *:[i32] }:$soffset, i32:{ *:[i32] }:$offset))<<P:Predicate_unindexedstore>><<P:Predicate_store_private>>  =>  (BUFFER_STORE_DWORD_VBUFFER_OFFEN VGPR_32:{ *:[i32] }:$value, ?:{ *:[i32] }:$vaddr, ?:{ *:[v4i32] }:$srsrc, ?:{ *:[i32] }:$soffset, ?:{ *:[i32] }:$offset, 0:{ *:[i32] }, 0:{ *:[i1] })
      GIR_BuildMI, /*InsnID*/0, /*Opcode*/GIMT_Encode2(AMDGPU::BUFFER_STORE_DWORD_VBUFFER_OFFEN),
      GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/0, // value
      GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/1, // vaddr
      GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/0, // srsrc
      GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/2, // soffset
      GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/3, // offset
      GIR_AddImm8, /*InsnID*/0, /*Imm*/0,
      GIR_AddImm8, /*InsnID*/0, /*Imm*/0,
      GIR_MergeMemOperands, /*InsnID*/0, /*NumInsns*/1, /*MergeInsnID's*/0,
      GIR_ConstrainSelectedInstOperands, /*InsnID*/0,
      GIR_EraseFromParent, /*InsnID*/0,
      // GIR_Coverage, 5539,
      GIR_Done,
    // Label 1880: @122491
    GIM_Try, /*On fail goto*//*Label 1881*/ GIMT_Encode4(122556), // Rule ID 3825 //
      GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasUnrestrictedSOffset),
      GIM_CheckMemoryAddressSpace, /*MI*/0, /*MMO*/0, /*NumAddrSpace*/1, /*AddrSpace*/1,
      GIM_CheckAtomicOrdering, /*MI*/0, /*Order*/(uint8_t)AtomicOrdering::NotAtomic,
      GIM_CheckPointerToAny, /*MI*/0, /*Op*/1, /*SizeInBits*/0,
      GIM_CheckComplexPattern, /*MI*/0, /*Op*/1, /*Renderer*/GIMT_Encode2(0), GIMT_Encode2(GICP_gi_mubuf_offset),
      // (st p3:{ *:[i32] }:$vdata, (MUBUFOffset:{ *:[iPTR] } v4i32:{ *:[v4i32] }:$srsrc, i32:{ *:[i32] }:$soffset, i32:{ *:[i32] }:$offset))<<P:Predicate_unindexedstore>><<P:Predicate_store_global>>  =>  (BUFFER_STORE_DWORD_OFFSET p3:{ *:[i32] }:$vdata, v4i32:{ *:[v4i32] }:$srsrc, i32:{ *:[i32] }:$soffset, i32:{ *:[i32] }:$offset)
      GIR_BuildMI, /*InsnID*/0, /*Opcode*/GIMT_Encode2(AMDGPU::BUFFER_STORE_DWORD_OFFSET),
      GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/0, // vdata
      GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/0, // srsrc
      GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/1, // soffset
      GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/2, // offset
      GIR_AddImm8, /*InsnID*/0, /*Imm*/0,
      GIR_AddImm8, /*InsnID*/0, /*Imm*/0,
      GIR_MergeMemOperands, /*InsnID*/0, /*NumInsns*/1, /*MergeInsnID's*/0,
      GIR_ConstrainSelectedInstOperands, /*InsnID*/0,
      GIR_EraseFromParent, /*InsnID*/0,
      // GIR_Coverage, 3825,
      GIR_Done,
    // Label 1881: @122556
    GIM_Try, /*On fail goto*//*Label 1882*/ GIMT_Encode4(122618), // Rule ID 3827 //
      GIM_CheckMemoryAddressSpace, /*MI*/0, /*MMO*/0, /*NumAddrSpace*/1, /*AddrSpace*/1,
      GIM_CheckAtomicOrdering, /*MI*/0, /*Order*/(uint8_t)AtomicOrdering::NotAtomic,
      GIM_CheckPointerToAny, /*MI*/0, /*Op*/1, /*SizeInBits*/0,
      GIM_CheckComplexPattern, /*MI*/0, /*Op*/1, /*Renderer*/GIMT_Encode2(0), GIMT_Encode2(GICP_gi_mubuf_offset),
      // (st p3:{ *:[i32] }:$vdata, (MUBUFOffset:{ *:[iPTR] } v4i32:{ *:[v4i32] }:$srsrc, i32:{ *:[i32] }:$soffset, i32:{ *:[i32] }:$offset))<<P:Predicate_unindexedstore>><<P:Predicate_store_global>>  =>  (BUFFER_STORE_DWORD_VBUFFER_OFFSET p3:{ *:[i32] }:$vdata, v4i32:{ *:[v4i32] }:$srsrc, i32:{ *:[i32] }:$soffset, i32:{ *:[i32] }:$offset)
      GIR_BuildMI, /*InsnID*/0, /*Opcode*/GIMT_Encode2(AMDGPU::BUFFER_STORE_DWORD_VBUFFER_OFFSET),
      GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/0, // vdata
      GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/0, // srsrc
      GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/1, // soffset
      GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/2, // offset
      GIR_AddImm8, /*InsnID*/0, /*Imm*/0,
      GIR_AddImm8, /*InsnID*/0, /*Imm*/0,
      GIR_MergeMemOperands, /*InsnID*/0, /*NumInsns*/1, /*MergeInsnID's*/0,
      GIR_ConstrainSelectedInstOperands, /*InsnID*/0,
      GIR_EraseFromParent, /*InsnID*/0,
      // GIR_Coverage, 3827,
      GIR_Done,
    // Label 1882: @122618
    GIM_Try, /*On fail goto*//*Label 1883*/ GIMT_Encode4(122679), // Rule ID 6651 //
      GIM_CheckFeatures, GIMT_Encode2(GIFBS_LDSRequiresM0Init),
      GIM_CheckMemorySizeEqualToLLT, /*MI*/0, /*MMO*/0, /*OpIdx*/0,
      GIM_CheckMemoryAddressSpace, /*MI*/0, /*MMO*/0, /*NumAddrSpace*/1, /*AddrSpace*/3,
      GIM_CheckAtomicOrdering, /*MI*/0, /*Order*/(uint8_t)AtomicOrdering::NotAtomic,
      GIM_CheckPointerToAny, /*MI*/0, /*Op*/1, /*SizeInBits*/0,
      GIM_CheckComplexPattern, /*MI*/0, /*Op*/1, /*Renderer*/GIMT_Encode2(0), GIMT_Encode2(GICP_gi_ds_1addr_1offset),
      // (AMDGPUst_glue p3:{ *:[i32] }:$value, (DS1Addr1Offset:{ *:[iPTR] } i32:{ *:[i32] }:$ptr, i32:{ *:[i32] }:$offset))<<P:Predicate_unindexedstore_glue>><<P:Predicate_store_glue>><<P:Predicate_store_local_m0>>  =>  (DS_WRITE_B32 ?:{ *:[i32] }:$ptr, anonymous_15037:{ *:[i32] }:$value, offset:{ *:[i32] }:$offset, 0:{ *:[i1] })
      GIR_BuildMI, /*InsnID*/0, /*Opcode*/GIMT_Encode2(AMDGPU::DS_WRITE_B32),
      GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/0, // ptr
      GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/0, // value
      GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/1, // offset
      GIR_AddImm8, /*InsnID*/0, /*Imm*/0,
      GIR_MergeMemOperands, /*InsnID*/0, /*NumInsns*/1, /*MergeInsnID's*/0,
      GIR_ConstrainSelectedInstOperands, /*InsnID*/0,
      GIR_EraseFromParent, /*InsnID*/0,
      // GIR_Coverage, 6651,
      GIR_Done,
    // Label 1883: @122679
    GIM_Try, /*On fail goto*//*Label 1884*/ GIMT_Encode4(122736), // Rule ID 6652 //
      GIM_CheckFeatures, GIMT_Encode2(GIFBS_NotLDSRequiresM0Init),
      GIM_CheckMemoryAddressSpace, /*MI*/0, /*MMO*/0, /*NumAddrSpace*/1, /*AddrSpace*/3,
      GIM_CheckAtomicOrdering, /*MI*/0, /*Order*/(uint8_t)AtomicOrdering::NotAtomic,
      GIM_CheckPointerToAny, /*MI*/0, /*Op*/1, /*SizeInBits*/0,
      GIM_CheckComplexPattern, /*MI*/0, /*Op*/1, /*Renderer*/GIMT_Encode2(0), GIMT_Encode2(GICP_gi_ds_1addr_1offset),
      // (st p3:{ *:[i32] }:$value, (DS1Addr1Offset:{ *:[iPTR] } i32:{ *:[i32] }:$ptr, i32:{ *:[i32] }:$offset))<<P:Predicate_unindexedstore>><<P:Predicate_store_local>>  =>  (DS_WRITE_B32_gfx9 ?:{ *:[i32] }:$ptr, anonymous_15037:{ *:[i32] }:$value, offset:{ *:[i32] }:$offset, 0:{ *:[i1] })
      GIR_BuildMI, /*InsnID*/0, /*Opcode*/GIMT_Encode2(AMDGPU::DS_WRITE_B32_gfx9),
      GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/0, // ptr
      GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/0, // value
      GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/1, // offset
      GIR_AddImm8, /*InsnID*/0, /*Imm*/0,
      GIR_MergeMemOperands, /*InsnID*/0, /*NumInsns*/1, /*MergeInsnID's*/0,
      GIR_ConstrainSelectedInstOperands, /*InsnID*/0,
      GIR_EraseFromParent, /*InsnID*/0,
      // GIR_Coverage, 6652,
      GIR_Done,
    // Label 1884: @122736
    GIM_Try, /*On fail goto*//*Label 1885*/ GIMT_Encode4(122798), // Rule ID 3019 //
      GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasFlatGlobalInsts),
      GIM_CheckMemoryAddressSpace, /*MI*/0, /*MMO*/0, /*NumAddrSpace*/1, /*AddrSpace*/1,
      GIM_CheckAtomicOrdering, /*MI*/0, /*Order*/(uint8_t)AtomicOrdering::NotAtomic,
      GIM_CheckPointerToAny, /*MI*/0, /*Op*/1, /*SizeInBits*/0,
      GIM_CheckComplexPattern, /*MI*/0, /*Op*/1, /*Renderer*/GIMT_Encode2(0), GIMT_Encode2(GICP_gi_global_saddr),
      // (st p3:{ *:[i32] }:$data, (GlobalSAddr:{ *:[iPTR] } SReg_64:{ *:[i64] }:$saddr, VGPR_32:{ *:[i32] }:$voffset, i32:{ *:[i32] }:$offset))<<P:Predicate_unindexedstore>><<P:Predicate_store_global>>  =>  (GLOBAL_STORE_DWORD_SADDR ?:{ *:[i32] }:$voffset, anonymous_15037:{ *:[i32] }:$data, ?:{ *:[i64] }:$saddr, ?:{ *:[i32] }:$offset)
      GIR_BuildMI, /*InsnID*/0, /*Opcode*/GIMT_Encode2(AMDGPU::GLOBAL_STORE_DWORD_SADDR),
      GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/1, // voffset
      GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/0, // data
      GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/0, // saddr
      GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/2, // offset
      GIR_AddImm8, /*InsnID*/0, /*Imm*/0,
      GIR_MergeMemOperands, /*InsnID*/0, /*NumInsns*/1, /*MergeInsnID's*/0,
      GIR_ConstrainSelectedInstOperands, /*InsnID*/0,
      GIR_EraseFromParent, /*InsnID*/0,
      // GIR_Coverage, 3019,
      GIR_Done,
    // Label 1885: @122798
    GIM_Try, /*On fail goto*//*Label 1886*/ GIMT_Encode4(122855), // Rule ID 3018 //
      GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasFlatGlobalInsts),
      GIM_CheckMemoryAddressSpace, /*MI*/0, /*MMO*/0, /*NumAddrSpace*/1, /*AddrSpace*/1,
      GIM_CheckAtomicOrdering, /*MI*/0, /*Order*/(uint8_t)AtomicOrdering::NotAtomic,
      GIM_CheckPointerToAny, /*MI*/0, /*Op*/1, /*SizeInBits*/0,
      GIM_CheckComplexPattern, /*MI*/0, /*Op*/1, /*Renderer*/GIMT_Encode2(0), GIMT_Encode2(GICP_gi_global_offset),
      // (st p3:{ *:[i32] }:$data, (GlobalOffset:{ *:[iPTR] } i64:{ *:[i64] }:$vaddr, i32:{ *:[i32] }:$offset))<<P:Predicate_unindexedstore>><<P:Predicate_store_global>>  =>  (GLOBAL_STORE_DWORD ?:{ *:[i64] }:$vaddr, anonymous_15037:{ *:[i32] }:$data, ?:{ *:[i32] }:$offset)
      GIR_BuildMI, /*InsnID*/0, /*Opcode*/GIMT_Encode2(AMDGPU::GLOBAL_STORE_DWORD),
      GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/0, // vaddr
      GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/0, // data
      GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/1, // offset
      GIR_AddImm8, /*InsnID*/0, /*Imm*/0,
      GIR_MergeMemOperands, /*InsnID*/0, /*NumInsns*/1, /*MergeInsnID's*/0,
      GIR_ConstrainSelectedInstOperands, /*InsnID*/0,
      GIR_EraseFromParent, /*InsnID*/0,
      // GIR_Coverage, 3018,
      GIR_Done,
    // Label 1886: @122855
    GIM_Try, /*On fail goto*//*Label 1887*/ GIMT_Encode4(122913), // Rule ID 2783 //
      GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasFlatAddressSpace),
      GIM_CheckMemoryAddressSpace, /*MI*/0, /*MMO*/0, /*NumAddrSpace*/2, /*AddrSpace*/0, /*AddrSpace*/1,
      GIM_CheckAtomicOrdering, /*MI*/0, /*Order*/(uint8_t)AtomicOrdering::NotAtomic,
      GIM_CheckPointerToAny, /*MI*/0, /*Op*/1, /*SizeInBits*/0,
      GIM_CheckComplexPattern, /*MI*/0, /*Op*/1, /*Renderer*/GIMT_Encode2(0), GIMT_Encode2(GICP_gi_flat_offset),
      // (st p3:{ *:[i32] }:$data, (FlatOffset:{ *:[iPTR] } i64:{ *:[i64] }:$vaddr, i32:{ *:[i32] }:$offset))<<P:Predicate_unindexedstore>><<P:Predicate_store_flat>>  =>  (FLAT_STORE_DWORD ?:{ *:[i64] }:$vaddr, anonymous_15037:{ *:[i32] }:$data, ?:{ *:[i32] }:$offset)
      GIR_BuildMI, /*InsnID*/0, /*Opcode*/GIMT_Encode2(AMDGPU::FLAT_STORE_DWORD),
      GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/0, // vaddr
      GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/0, // data
      GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/1, // offset
      GIR_AddImm8, /*InsnID*/0, /*Imm*/0,
      GIR_MergeMemOperands, /*InsnID*/0, /*NumInsns*/1, /*MergeInsnID's*/0,
      GIR_ConstrainSelectedInstOperands, /*InsnID*/0,
      GIR_EraseFromParent, /*InsnID*/0,
      // GIR_Coverage, 2783,
      GIR_Done,
    // Label 1887: @122913
    GIM_Reject,
    // Label 1810: @122914
    GIM_Try, /*On fail goto*//*Label 1888*/ GIMT_Encode4(122984), // Rule ID 6853 //
      GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasUnalignedAccessMode_LDSRequiresM0Init),
      GIM_CheckMemorySizeEqualToLLT, /*MI*/0, /*MMO*/0, /*OpIdx*/0,
      GIM_CheckMemoryAddressSpace, /*MI*/0, /*MMO*/0, /*NumAddrSpace*/1, /*AddrSpace*/3,
      GIM_CheckMemoryAddressSpace, /*MI*/0, /*MMO*/0, /*NumAddrSpace*/1, /*AddrSpace*/3,
      GIM_CheckAtomicOrdering, /*MI*/0, /*Order*/(uint8_t)AtomicOrdering::NotAtomic,
      GIM_CheckPointerToAny, /*MI*/0, /*Op*/1, /*SizeInBits*/0,
      GIM_CheckCxxInsnPredicate, /*MI*/0, /*FnId*/GIMT_Encode2(GICXXPred_MI_Predicate_store_align_less_than_4_local_m0),
      GIM_CheckComplexPattern, /*MI*/0, /*Op*/1, /*Renderer*/GIMT_Encode2(0), GIMT_Encode2(GICP_gi_ds_1addr_1offset),
      // (AMDGPUst_glue p4:{ *:[i64] }:$value, (DS1Addr1Offset:{ *:[iPTR] } i32:{ *:[i32] }:$ptr, i32:{ *:[i32] }:$offset))<<P:Predicate_unindexedstore_glue>><<P:Predicate_store_glue>><<P:Predicate_store_local_m0>><<P:Predicate_store_align_less_than_4_local_m0>>  =>  (DS_WRITE_B64 ?:{ *:[i32] }:$ptr, anonymous_15036:{ *:[i64] }:$value, offset:{ *:[i32] }:$offset, 0:{ *:[i1] })
      GIR_BuildMI, /*InsnID*/0, /*Opcode*/GIMT_Encode2(AMDGPU::DS_WRITE_B64),
      GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/0, // ptr
      GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/0, // value
      GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/1, // offset
      GIR_AddImm8, /*InsnID*/0, /*Imm*/0,
      GIR_MergeMemOperands, /*InsnID*/0, /*NumInsns*/1, /*MergeInsnID's*/0,
      GIR_ConstrainSelectedInstOperands, /*InsnID*/0,
      GIR_EraseFromParent, /*InsnID*/0,
      // GIR_Coverage, 6853,
      GIR_Done,
    // Label 1888: @122984
    GIM_Try, /*On fail goto*//*Label 1889*/ GIMT_Encode4(123049), // Rule ID 6777 //
      GIM_CheckFeatures, GIMT_Encode2(GIFBS_LDSRequiresM0Init),
      GIM_CheckMemorySizeEqualToLLT, /*MI*/0, /*MMO*/0, /*OpIdx*/0,
      GIM_CheckMemoryAddressSpace, /*MI*/0, /*MMO*/0, /*NumAddrSpace*/1, /*AddrSpace*/3,
      GIM_CheckMemoryAlignment, /*MI*/0, /*MMO*/0, /*MinAlign*/8,
      GIM_CheckAtomicOrdering, /*MI*/0, /*Order*/(uint8_t)AtomicOrdering::NotAtomic,
      GIM_CheckPointerToAny, /*MI*/0, /*Op*/1, /*SizeInBits*/0,
      GIM_CheckComplexPattern, /*MI*/0, /*Op*/1, /*Renderer*/GIMT_Encode2(0), GIMT_Encode2(GICP_gi_ds_1addr_1offset),
      // (AMDGPUst_glue p4:{ *:[i64] }:$value, (DS1Addr1Offset:{ *:[iPTR] } i32:{ *:[i32] }:$ptr, i32:{ *:[i32] }:$offset))<<P:Predicate_unindexedstore_glue>><<P:Predicate_store_glue>><<P:Predicate_store_local_m0>><<P:Predicate_store_align8_local_m0>>  =>  (DS_WRITE_B64 ?:{ *:[i32] }:$ptr, anonymous_15036:{ *:[i64] }:$value, offset:{ *:[i32] }:$offset, 0:{ *:[i1] })
      GIR_BuildMI, /*InsnID*/0, /*Opcode*/GIMT_Encode2(AMDGPU::DS_WRITE_B64),
      GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/0, // ptr
      GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/0, // value
      GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/1, // offset
      GIR_AddImm8, /*InsnID*/0, /*Imm*/0,
      GIR_MergeMemOperands, /*InsnID*/0, /*NumInsns*/1, /*MergeInsnID's*/0,
      GIR_ConstrainSelectedInstOperands, /*InsnID*/0,
      GIR_EraseFromParent, /*InsnID*/0,
      // GIR_Coverage, 6777,
      GIR_Done,
    // Label 1889: @123049
    GIM_Try, /*On fail goto*//*Label 1890*/ GIMT_Encode4(123115), // Rule ID 6854 //
      GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasUnalignedAccessMode_NotLDSRequiresM0Init),
      GIM_CheckMemoryAddressSpace, /*MI*/0, /*MMO*/0, /*NumAddrSpace*/1, /*AddrSpace*/3,
      GIM_CheckMemoryAddressSpace, /*MI*/0, /*MMO*/0, /*NumAddrSpace*/1, /*AddrSpace*/3,
      GIM_CheckAtomicOrdering, /*MI*/0, /*Order*/(uint8_t)AtomicOrdering::NotAtomic,
      GIM_CheckPointerToAny, /*MI*/0, /*Op*/1, /*SizeInBits*/0,
      GIM_CheckCxxInsnPredicate, /*MI*/0, /*FnId*/GIMT_Encode2(GICXXPred_MI_Predicate_store_align_less_than_4_local),
      GIM_CheckComplexPattern, /*MI*/0, /*Op*/1, /*Renderer*/GIMT_Encode2(0), GIMT_Encode2(GICP_gi_ds_1addr_1offset),
      // (st p4:{ *:[i64] }:$value, (DS1Addr1Offset:{ *:[iPTR] } i32:{ *:[i32] }:$ptr, i32:{ *:[i32] }:$offset))<<P:Predicate_unindexedstore>><<P:Predicate_store_local>><<P:Predicate_store_align_less_than_4_local>>  =>  (DS_WRITE_B64_gfx9 ?:{ *:[i32] }:$ptr, anonymous_15036:{ *:[i64] }:$value, offset:{ *:[i32] }:$offset, 0:{ *:[i1] })
      GIR_BuildMI, /*InsnID*/0, /*Opcode*/GIMT_Encode2(AMDGPU::DS_WRITE_B64_gfx9),
      GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/0, // ptr
      GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/0, // value
      GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/1, // offset
      GIR_AddImm8, /*InsnID*/0, /*Imm*/0,
      GIR_MergeMemOperands, /*InsnID*/0, /*NumInsns*/1, /*MergeInsnID's*/0,
      GIR_ConstrainSelectedInstOperands, /*InsnID*/0,
      GIR_EraseFromParent, /*InsnID*/0,
      // GIR_Coverage, 6854,
      GIR_Done,
    // Label 1890: @123115
    GIM_Try, /*On fail goto*//*Label 1891*/ GIMT_Encode4(123176), // Rule ID 6778 //
      GIM_CheckFeatures, GIMT_Encode2(GIFBS_NotLDSRequiresM0Init),
      GIM_CheckMemoryAddressSpace, /*MI*/0, /*MMO*/0, /*NumAddrSpace*/1, /*AddrSpace*/3,
      GIM_CheckMemoryAlignment, /*MI*/0, /*MMO*/0, /*MinAlign*/8,
      GIM_CheckAtomicOrdering, /*MI*/0, /*Order*/(uint8_t)AtomicOrdering::NotAtomic,
      GIM_CheckPointerToAny, /*MI*/0, /*Op*/1, /*SizeInBits*/0,
      GIM_CheckComplexPattern, /*MI*/0, /*Op*/1, /*Renderer*/GIMT_Encode2(0), GIMT_Encode2(GICP_gi_ds_1addr_1offset),
      // (st p4:{ *:[i64] }:$value, (DS1Addr1Offset:{ *:[iPTR] } i32:{ *:[i32] }:$ptr, i32:{ *:[i32] }:$offset))<<P:Predicate_unindexedstore>><<P:Predicate_store_local>><<P:Predicate_store_align8_local>>  =>  (DS_WRITE_B64_gfx9 ?:{ *:[i32] }:$ptr, anonymous_15036:{ *:[i64] }:$value, offset:{ *:[i32] }:$offset, 0:{ *:[i1] })
      GIR_BuildMI, /*InsnID*/0, /*Opcode*/GIMT_Encode2(AMDGPU::DS_WRITE_B64_gfx9),
      GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/0, // ptr
      GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/0, // value
      GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/1, // offset
      GIR_AddImm8, /*InsnID*/0, /*Imm*/0,
      GIR_MergeMemOperands, /*InsnID*/0, /*NumInsns*/1, /*MergeInsnID's*/0,
      GIR_ConstrainSelectedInstOperands, /*InsnID*/0,
      GIR_EraseFromParent, /*InsnID*/0,
      // GIR_Coverage, 6778,
      GIR_Done,
    // Label 1891: @123176
    GIM_Try, /*On fail goto*//*Label 1892*/ GIMT_Encode4(123238), // Rule ID 3541 //
      GIM_CheckFeatures, GIMT_Encode2(GIFBS_EnableFlatScratch_HasFlatScratchInsts_HasFlatScratchSVSMode),
      GIM_CheckMemoryAddressSpace, /*MI*/0, /*MMO*/0, /*NumAddrSpace*/1, /*AddrSpace*/5,
      GIM_CheckAtomicOrdering, /*MI*/0, /*Order*/(uint8_t)AtomicOrdering::NotAtomic,
      GIM_CheckPointerToAny, /*MI*/0, /*Op*/1, /*SizeInBits*/0,
      GIM_CheckComplexPattern, /*MI*/0, /*Op*/1, /*Renderer*/GIMT_Encode2(0), GIMT_Encode2(GICP_gi_flat_scratch_svaddr),
      // (st p4:{ *:[i64] }:$data, (ScratchSVAddr:{ *:[iPTR] } VGPR_32:{ *:[i32] }:$vaddr, SGPR_32:{ *:[i32] }:$saddr, i32:{ *:[i32] }:$offset))<<P:Predicate_unindexedstore>><<P:Predicate_store_private>>  =>  (SCRATCH_STORE_DWORDX2_SVS anonymous_15036:{ *:[i64] }:$data, ?:{ *:[i32] }:$vaddr, ?:{ *:[i32] }:$saddr, ?:{ *:[i32] }:$offset)
      GIR_BuildMI, /*InsnID*/0, /*Opcode*/GIMT_Encode2(AMDGPU::SCRATCH_STORE_DWORDX2_SVS),
      GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/0, // data
      GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/0, // vaddr
      GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/1, // saddr
      GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/2, // offset
      GIR_AddImm8, /*InsnID*/0, /*Imm*/0,
      GIR_MergeMemOperands, /*InsnID*/0, /*NumInsns*/1, /*MergeInsnID's*/0,
      GIR_ConstrainSelectedInstOperands, /*InsnID*/0,
      GIR_EraseFromParent, /*InsnID*/0,
      // GIR_Coverage, 3541,
      GIR_Done,
    // Label 1892: @123238
    GIM_Try, /*On fail goto*//*Label 1893*/ GIMT_Encode4(123295), // Rule ID 3540 //
      GIM_CheckFeatures, GIMT_Encode2(GIFBS_EnableFlatScratch_HasFlatScratchInsts),
      GIM_CheckMemoryAddressSpace, /*MI*/0, /*MMO*/0, /*NumAddrSpace*/1, /*AddrSpace*/5,
      GIM_CheckAtomicOrdering, /*MI*/0, /*Order*/(uint8_t)AtomicOrdering::NotAtomic,
      GIM_CheckPointerToAny, /*MI*/0, /*Op*/1, /*SizeInBits*/0,
      GIM_CheckComplexPattern, /*MI*/0, /*Op*/1, /*Renderer*/GIMT_Encode2(0), GIMT_Encode2(GICP_gi_flat_scratch_saddr),
      // (st p4:{ *:[i64] }:$data, (ScratchSAddr:{ *:[iPTR] } SGPR_32:{ *:[i32] }:$saddr, i32:{ *:[i32] }:$offset))<<P:Predicate_unindexedstore>><<P:Predicate_store_private>>  =>  (SCRATCH_STORE_DWORDX2_SADDR anonymous_15036:{ *:[i64] }:$data, ?:{ *:[i32] }:$saddr, ?:{ *:[i32] }:$offset)
      GIR_BuildMI, /*InsnID*/0, /*Opcode*/GIMT_Encode2(AMDGPU::SCRATCH_STORE_DWORDX2_SADDR),
      GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/0, // data
      GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/0, // saddr
      GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/1, // offset
      GIR_AddImm8, /*InsnID*/0, /*Imm*/0,
      GIR_MergeMemOperands, /*InsnID*/0, /*NumInsns*/1, /*MergeInsnID's*/0,
      GIR_ConstrainSelectedInstOperands, /*InsnID*/0,
      GIR_EraseFromParent, /*InsnID*/0,
      // GIR_Coverage, 3540,
      GIR_Done,
    // Label 1893: @123295
    GIM_Try, /*On fail goto*//*Label 1894*/ GIMT_Encode4(123352), // Rule ID 3539 //
      GIM_CheckFeatures, GIMT_Encode2(GIFBS_EnableFlatScratch_HasFlatScratchInsts),
      GIM_CheckMemoryAddressSpace, /*MI*/0, /*MMO*/0, /*NumAddrSpace*/1, /*AddrSpace*/5,
      GIM_CheckAtomicOrdering, /*MI*/0, /*Order*/(uint8_t)AtomicOrdering::NotAtomic,
      GIM_CheckPointerToAny, /*MI*/0, /*Op*/1, /*SizeInBits*/0,
      GIM_CheckComplexPattern, /*MI*/0, /*Op*/1, /*Renderer*/GIMT_Encode2(0), GIMT_Encode2(GICP_gi_flat_scratch_offset),
      // (st p4:{ *:[i64] }:$data, (ScratchOffset:{ *:[iPTR] } VGPR_32:{ *:[i32] }:$vaddr, i32:{ *:[i32] }:$offset))<<P:Predicate_unindexedstore>><<P:Predicate_store_private>>  =>  (SCRATCH_STORE_DWORDX2 anonymous_15036:{ *:[i64] }:$data, ?:{ *:[i32] }:$vaddr, ?:{ *:[i32] }:$offset)
      GIR_BuildMI, /*InsnID*/0, /*Opcode*/GIMT_Encode2(AMDGPU::SCRATCH_STORE_DWORDX2),
      GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/0, // data
      GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/0, // vaddr
      GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/1, // offset
      GIR_AddImm8, /*InsnID*/0, /*Imm*/0,
      GIR_MergeMemOperands, /*InsnID*/0, /*NumInsns*/1, /*MergeInsnID's*/0,
      GIR_ConstrainSelectedInstOperands, /*InsnID*/0,
      GIR_EraseFromParent, /*InsnID*/0,
      // GIR_Coverage, 3539,
      GIR_Done,
    // Label 1894: @123352
    GIM_Try, /*On fail goto*//*Label 1895*/ GIMT_Encode4(123422), // Rule ID 3874 //
      GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasUnrestrictedSOffset),
      GIM_CheckMemoryAddressSpace, /*MI*/0, /*MMO*/0, /*NumAddrSpace*/1, /*AddrSpace*/1,
      GIM_CheckAtomicOrdering, /*MI*/0, /*Order*/(uint8_t)AtomicOrdering::NotAtomic,
      GIM_CheckPointerToAny, /*MI*/0, /*Op*/1, /*SizeInBits*/0,
      GIM_CheckComplexPattern, /*MI*/0, /*Op*/1, /*Renderer*/GIMT_Encode2(0), GIMT_Encode2(GICP_gi_mubuf_addr64),
      // (st p4:{ *:[i64] }:$vdata, (MUBUFAddr64:{ *:[iPTR] } v4i32:{ *:[v4i32] }:$srsrc, i64:{ *:[i64] }:$vaddr, i32:{ *:[i32] }:$soffset, i32:{ *:[i32] }:$offset))<<P:Predicate_unindexedstore>><<P:Predicate_store_global>>  =>  (BUFFER_STORE_DWORDX2_ADDR64 p4:{ *:[i64] }:$vdata, i64:{ *:[i64] }:$vaddr, v4i32:{ *:[v4i32] }:$srsrc, i32:{ *:[i32] }:$soffset, i32:{ *:[i32] }:$offset)
      GIR_BuildMI, /*InsnID*/0, /*Opcode*/GIMT_Encode2(AMDGPU::BUFFER_STORE_DWORDX2_ADDR64),
      GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/0, // vdata
      GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/1, // vaddr
      GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/0, // srsrc
      GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/2, // soffset
      GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/3, // offset
      GIR_AddImm8, /*InsnID*/0, /*Imm*/0,
      GIR_AddImm8, /*InsnID*/0, /*Imm*/0,
      GIR_MergeMemOperands, /*InsnID*/0, /*NumInsns*/1, /*MergeInsnID's*/0,
      GIR_ConstrainSelectedInstOperands, /*InsnID*/0,
      GIR_EraseFromParent, /*InsnID*/0,
      // GIR_Coverage, 3874,
      GIR_Done,
    // Label 1895: @123422
    GIM_Try, /*On fail goto*//*Label 1896*/ GIMT_Encode4(123489), // Rule ID 3876 //
      GIM_CheckMemoryAddressSpace, /*MI*/0, /*MMO*/0, /*NumAddrSpace*/1, /*AddrSpace*/1,
      GIM_CheckAtomicOrdering, /*MI*/0, /*Order*/(uint8_t)AtomicOrdering::NotAtomic,
      GIM_CheckPointerToAny, /*MI*/0, /*Op*/1, /*SizeInBits*/0,
      GIM_CheckComplexPattern, /*MI*/0, /*Op*/1, /*Renderer*/GIMT_Encode2(0), GIMT_Encode2(GICP_gi_mubuf_addr64),
      // (st p4:{ *:[i64] }:$vdata, (MUBUFAddr64:{ *:[iPTR] } v4i32:{ *:[v4i32] }:$srsrc, i64:{ *:[i64] }:$vaddr, i32:{ *:[i32] }:$soffset, i32:{ *:[i32] }:$offset))<<P:Predicate_unindexedstore>><<P:Predicate_store_global>>  =>  (BUFFER_STORE_DWORDX2_VBUFFER_ADDR64 p4:{ *:[i64] }:$vdata, i64:{ *:[i64] }:$vaddr, v4i32:{ *:[v4i32] }:$srsrc, i32:{ *:[i32] }:$soffset, i32:{ *:[i32] }:$offset)
      GIR_BuildMI, /*InsnID*/0, /*Opcode*/GIMT_Encode2(AMDGPU::BUFFER_STORE_DWORDX2_VBUFFER_ADDR64),
      GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/0, // vdata
      GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/1, // vaddr
      GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/0, // srsrc
      GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/2, // soffset
      GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/3, // offset
      GIR_AddImm8, /*InsnID*/0, /*Imm*/0,
      GIR_AddImm8, /*InsnID*/0, /*Imm*/0,
      GIR_MergeMemOperands, /*InsnID*/0, /*NumInsns*/1, /*MergeInsnID's*/0,
      GIR_ConstrainSelectedInstOperands, /*InsnID*/0,
      GIR_EraseFromParent, /*InsnID*/0,
      // GIR_Coverage, 3876,
      GIR_Done,
    // Label 1896: @123489
    GIM_Try, /*On fail goto*//*Label 1897*/ GIMT_Encode4(123613), // Rule ID 6712 //
      GIM_CheckFeatures, GIMT_Encode2(GIFBS_LDSRequiresM0Init_isGFX7Plus),
      GIM_CheckMemorySizeEqualToLLT, /*MI*/0, /*MMO*/0, /*OpIdx*/0,
      GIM_CheckMemoryAddressSpace, /*MI*/0, /*MMO*/0, /*NumAddrSpace*/1, /*AddrSpace*/3,
      GIM_CheckAtomicOrdering, /*MI*/0, /*Order*/(uint8_t)AtomicOrdering::NotAtomic,
      GIM_CheckPointerToAny, /*MI*/0, /*Op*/1, /*SizeInBits*/0,
      GIM_CheckComplexPattern, /*MI*/0, /*Op*/1, /*Renderer*/GIMT_Encode2(0), GIMT_Encode2(GICP_gi_ds_64bit_4byte_aligned),
      // (AMDGPUst_glue p4:{ *:[i64] }:$value, (DS64Bit4ByteAligned:{ *:[iPTR] } i32:{ *:[i32] }:$ptr, i8:{ *:[i8] }:$offset0, i8:{ *:[i8] }:$offset1))<<P:Predicate_unindexedstore_glue>><<P:Predicate_store_glue>><<P:Predicate_store_local_m0>>  =>  (DS_WRITE2_B32 ?:{ *:[i32] }:$ptr, (EXTRACT_SUBREG:{ *:[i32] } VReg_64:{ *:[i64] }:$value, sub0:{ *:[i32] }), (EXTRACT_SUBREG:{ *:[i32] } VReg_64:{ *:[i64] }:$value, sub1:{ *:[i32] }), ?:{ *:[i8] }:$offset0, ?:{ *:[i8] }:$offset1, 0:{ *:[i1] })
      GIR_MakeTempReg, /*TempRegID*/0, /*TypeID*/GILLT_s32,
      GIR_MakeTempReg, /*TempRegID*/1, /*TypeID*/GILLT_s32,
      GIR_BuildMI, /*InsnID*/2, /*Opcode*/GIMT_Encode2(TargetOpcode::COPY),
      GIR_AddTempRegister, /*InsnID*/2, /*TempRegID*/1, /*TempRegFlags*/GIMT_Encode2(RegState::Define),
      GIR_CopySubReg, /*NewInsnID*/2, /*OldInsnID*/0, /*OpIdx*/0, /*SubRegIdx*/GIMT_Encode2(11), // value
      GIR_ConstrainOperandRC, /*InsnID*/2, /*Op*/0, GIMT_Encode2(AMDGPU::VGPR_32RegClassID),
      GIR_ConstrainOperandRC, /*InsnID*/2, /*Op*/1, GIMT_Encode2(AMDGPU::VReg_64RegClassID),
      GIR_BuildMI, /*InsnID*/1, /*Opcode*/GIMT_Encode2(TargetOpcode::COPY),
      GIR_AddTempRegister, /*InsnID*/1, /*TempRegID*/0, /*TempRegFlags*/GIMT_Encode2(RegState::Define),
      GIR_CopySubReg, /*NewInsnID*/1, /*OldInsnID*/0, /*OpIdx*/0, /*SubRegIdx*/GIMT_Encode2(3), // value
      GIR_ConstrainOperandRC, /*InsnID*/1, /*Op*/0, GIMT_Encode2(AMDGPU::VGPR_32RegClassID),
      GIR_ConstrainOperandRC, /*InsnID*/1, /*Op*/1, GIMT_Encode2(AMDGPU::VReg_64RegClassID),
      GIR_BuildMI, /*InsnID*/0, /*Opcode*/GIMT_Encode2(AMDGPU::DS_WRITE2_B32),
      GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/0, // ptr
      GIR_AddSimpleTempRegister, /*InsnID*/0, /*TempRegID*/0,
      GIR_AddSimpleTempRegister, /*InsnID*/0, /*TempRegID*/1,
      GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/1, // offset0
      GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/2, // offset1
      GIR_AddImm8, /*InsnID*/0, /*Imm*/0,
      GIR_MergeMemOperands, /*InsnID*/0, /*NumInsns*/1, /*MergeInsnID's*/0,
      GIR_ConstrainSelectedInstOperands, /*InsnID*/0,
      GIR_EraseFromParent, /*InsnID*/0,
      // GIR_Coverage, 6712,
      GIR_Done,
    // Label 1897: @123613
    GIM_Try, /*On fail goto*//*Label 1898*/ GIMT_Encode4(123678), // Rule ID 3873 //
      GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasUnrestrictedSOffset),
      GIM_CheckMemoryAddressSpace, /*MI*/0, /*MMO*/0, /*NumAddrSpace*/1, /*AddrSpace*/1,
      GIM_CheckAtomicOrdering, /*MI*/0, /*Order*/(uint8_t)AtomicOrdering::NotAtomic,
      GIM_CheckPointerToAny, /*MI*/0, /*Op*/1, /*SizeInBits*/0,
      GIM_CheckComplexPattern, /*MI*/0, /*Op*/1, /*Renderer*/GIMT_Encode2(0), GIMT_Encode2(GICP_gi_mubuf_offset),
      // (st p4:{ *:[i64] }:$vdata, (MUBUFOffset:{ *:[iPTR] } v4i32:{ *:[v4i32] }:$srsrc, i32:{ *:[i32] }:$soffset, i32:{ *:[i32] }:$offset))<<P:Predicate_unindexedstore>><<P:Predicate_store_global>>  =>  (BUFFER_STORE_DWORDX2_OFFSET p4:{ *:[i64] }:$vdata, v4i32:{ *:[v4i32] }:$srsrc, i32:{ *:[i32] }:$soffset, i32:{ *:[i32] }:$offset)
      GIR_BuildMI, /*InsnID*/0, /*Opcode*/GIMT_Encode2(AMDGPU::BUFFER_STORE_DWORDX2_OFFSET),
      GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/0, // vdata
      GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/0, // srsrc
      GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/1, // soffset
      GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/2, // offset
      GIR_AddImm8, /*InsnID*/0, /*Imm*/0,
      GIR_AddImm8, /*InsnID*/0, /*Imm*/0,
      GIR_MergeMemOperands, /*InsnID*/0, /*NumInsns*/1, /*MergeInsnID's*/0,
      GIR_ConstrainSelectedInstOperands, /*InsnID*/0,
      GIR_EraseFromParent, /*InsnID*/0,
      // GIR_Coverage, 3873,
      GIR_Done,
    // Label 1898: @123678
    GIM_Try, /*On fail goto*//*Label 1899*/ GIMT_Encode4(123740), // Rule ID 3875 //
      GIM_CheckMemoryAddressSpace, /*MI*/0, /*MMO*/0, /*NumAddrSpace*/1, /*AddrSpace*/1,
      GIM_CheckAtomicOrdering, /*MI*/0, /*Order*/(uint8_t)AtomicOrdering::NotAtomic,
      GIM_CheckPointerToAny, /*MI*/0, /*Op*/1, /*SizeInBits*/0,
      GIM_CheckComplexPattern, /*MI*/0, /*Op*/1, /*Renderer*/GIMT_Encode2(0), GIMT_Encode2(GICP_gi_mubuf_offset),
      // (st p4:{ *:[i64] }:$vdata, (MUBUFOffset:{ *:[iPTR] } v4i32:{ *:[v4i32] }:$srsrc, i32:{ *:[i32] }:$soffset, i32:{ *:[i32] }:$offset))<<P:Predicate_unindexedstore>><<P:Predicate_store_global>>  =>  (BUFFER_STORE_DWORDX2_VBUFFER_OFFSET p4:{ *:[i64] }:$vdata, v4i32:{ *:[v4i32] }:$srsrc, i32:{ *:[i32] }:$soffset, i32:{ *:[i32] }:$offset)
      GIR_BuildMI, /*InsnID*/0, /*Opcode*/GIMT_Encode2(AMDGPU::BUFFER_STORE_DWORDX2_VBUFFER_OFFSET),
      GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/0, // vdata
      GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/0, // srsrc
      GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/1, // soffset
      GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/2, // offset
      GIR_AddImm8, /*InsnID*/0, /*Imm*/0,
      GIR_AddImm8, /*InsnID*/0, /*Imm*/0,
      GIR_MergeMemOperands, /*InsnID*/0, /*NumInsns*/1, /*MergeInsnID's*/0,
      GIR_ConstrainSelectedInstOperands, /*InsnID*/0,
      GIR_EraseFromParent, /*InsnID*/0,
      // GIR_Coverage, 3875,
      GIR_Done,
    // Label 1899: @123740
    GIM_Try, /*On fail goto*//*Label 1900*/ GIMT_Encode4(123860), // Rule ID 6714 //
      GIM_CheckFeatures, GIMT_Encode2(GIFBS_NotLDSRequiresM0Init),
      GIM_CheckMemoryAddressSpace, /*MI*/0, /*MMO*/0, /*NumAddrSpace*/1, /*AddrSpace*/3,
      GIM_CheckAtomicOrdering, /*MI*/0, /*Order*/(uint8_t)AtomicOrdering::NotAtomic,
      GIM_CheckPointerToAny, /*MI*/0, /*Op*/1, /*SizeInBits*/0,
      GIM_CheckComplexPattern, /*MI*/0, /*Op*/1, /*Renderer*/GIMT_Encode2(0), GIMT_Encode2(GICP_gi_ds_64bit_4byte_aligned),
      // (st p4:{ *:[i64] }:$value, (DS64Bit4ByteAligned:{ *:[iPTR] } i32:{ *:[i32] }:$ptr, i8:{ *:[i8] }:$offset0, i8:{ *:[i8] }:$offset1))<<P:Predicate_unindexedstore>><<P:Predicate_store_local>>  =>  (DS_WRITE2_B32_gfx9 ?:{ *:[i32] }:$ptr, (EXTRACT_SUBREG:{ *:[i32] } VReg_64:{ *:[i64] }:$value, sub0:{ *:[i32] }), (EXTRACT_SUBREG:{ *:[i32] } VReg_64:{ *:[i64] }:$value, sub1:{ *:[i32] }), ?:{ *:[i8] }:$offset0, ?:{ *:[i8] }:$offset1, 0:{ *:[i1] })
      GIR_MakeTempReg, /*TempRegID*/0, /*TypeID*/GILLT_s32,
      GIR_MakeTempReg, /*TempRegID*/1, /*TypeID*/GILLT_s32,
      GIR_BuildMI, /*InsnID*/2, /*Opcode*/GIMT_Encode2(TargetOpcode::COPY),
      GIR_AddTempRegister, /*InsnID*/2, /*TempRegID*/1, /*TempRegFlags*/GIMT_Encode2(RegState::Define),
      GIR_CopySubReg, /*NewInsnID*/2, /*OldInsnID*/0, /*OpIdx*/0, /*SubRegIdx*/GIMT_Encode2(11), // value
      GIR_ConstrainOperandRC, /*InsnID*/2, /*Op*/0, GIMT_Encode2(AMDGPU::VGPR_32RegClassID),
      GIR_ConstrainOperandRC, /*InsnID*/2, /*Op*/1, GIMT_Encode2(AMDGPU::VReg_64RegClassID),
      GIR_BuildMI, /*InsnID*/1, /*Opcode*/GIMT_Encode2(TargetOpcode::COPY),
      GIR_AddTempRegister, /*InsnID*/1, /*TempRegID*/0, /*TempRegFlags*/GIMT_Encode2(RegState::Define),
      GIR_CopySubReg, /*NewInsnID*/1, /*OldInsnID*/0, /*OpIdx*/0, /*SubRegIdx*/GIMT_Encode2(3), // value
      GIR_ConstrainOperandRC, /*InsnID*/1, /*Op*/0, GIMT_Encode2(AMDGPU::VGPR_32RegClassID),
      GIR_ConstrainOperandRC, /*InsnID*/1, /*Op*/1, GIMT_Encode2(AMDGPU::VReg_64RegClassID),
      GIR_BuildMI, /*InsnID*/0, /*Opcode*/GIMT_Encode2(AMDGPU::DS_WRITE2_B32_gfx9),
      GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/0, // ptr
      GIR_AddSimpleTempRegister, /*InsnID*/0, /*TempRegID*/0,
      GIR_AddSimpleTempRegister, /*InsnID*/0, /*TempRegID*/1,
      GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/1, // offset0
      GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/2, // offset1
      GIR_AddImm8, /*InsnID*/0, /*Imm*/0,
      GIR_MergeMemOperands, /*InsnID*/0, /*NumInsns*/1, /*MergeInsnID's*/0,
      GIR_ConstrainSelectedInstOperands, /*InsnID*/0,
      GIR_EraseFromParent, /*InsnID*/0,
      // GIR_Coverage, 6714,
      GIR_Done,
    // Label 1900: @123860
    GIM_Try, /*On fail goto*//*Label 1901*/ GIMT_Encode4(123922), // Rule ID 3067 //
      GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasFlatGlobalInsts),
      GIM_CheckMemoryAddressSpace, /*MI*/0, /*MMO*/0, /*NumAddrSpace*/1, /*AddrSpace*/1,
      GIM_CheckAtomicOrdering, /*MI*/0, /*Order*/(uint8_t)AtomicOrdering::NotAtomic,
      GIM_CheckPointerToAny, /*MI*/0, /*Op*/1, /*SizeInBits*/0,
      GIM_CheckComplexPattern, /*MI*/0, /*Op*/1, /*Renderer*/GIMT_Encode2(0), GIMT_Encode2(GICP_gi_global_saddr),
      // (st p4:{ *:[i64] }:$data, (GlobalSAddr:{ *:[iPTR] } SReg_64:{ *:[i64] }:$saddr, VGPR_32:{ *:[i32] }:$voffset, i32:{ *:[i32] }:$offset))<<P:Predicate_unindexedstore>><<P:Predicate_store_global>>  =>  (GLOBAL_STORE_DWORDX2_SADDR ?:{ *:[i32] }:$voffset, anonymous_15036:{ *:[i64] }:$data, ?:{ *:[i64] }:$saddr, ?:{ *:[i32] }:$offset)
      GIR_BuildMI, /*InsnID*/0, /*Opcode*/GIMT_Encode2(AMDGPU::GLOBAL_STORE_DWORDX2_SADDR),
      GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/1, // voffset
      GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/0, // data
      GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/0, // saddr
      GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/2, // offset
      GIR_AddImm8, /*InsnID*/0, /*Imm*/0,
      GIR_MergeMemOperands, /*InsnID*/0, /*NumInsns*/1, /*MergeInsnID's*/0,
      GIR_ConstrainSelectedInstOperands, /*InsnID*/0,
      GIR_EraseFromParent, /*InsnID*/0,
      // GIR_Coverage, 3067,
      GIR_Done,
    // Label 1901: @123922
    GIM_Try, /*On fail goto*//*Label 1902*/ GIMT_Encode4(123979), // Rule ID 3066 //
      GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasFlatGlobalInsts),
      GIM_CheckMemoryAddressSpace, /*MI*/0, /*MMO*/0, /*NumAddrSpace*/1, /*AddrSpace*/1,
      GIM_CheckAtomicOrdering, /*MI*/0, /*Order*/(uint8_t)AtomicOrdering::NotAtomic,
      GIM_CheckPointerToAny, /*MI*/0, /*Op*/1, /*SizeInBits*/0,
      GIM_CheckComplexPattern, /*MI*/0, /*Op*/1, /*Renderer*/GIMT_Encode2(0), GIMT_Encode2(GICP_gi_global_offset),
      // (st p4:{ *:[i64] }:$data, (GlobalOffset:{ *:[iPTR] } i64:{ *:[i64] }:$vaddr, i32:{ *:[i32] }:$offset))<<P:Predicate_unindexedstore>><<P:Predicate_store_global>>  =>  (GLOBAL_STORE_DWORDX2 ?:{ *:[i64] }:$vaddr, anonymous_15036:{ *:[i64] }:$data, ?:{ *:[i32] }:$offset)
      GIR_BuildMI, /*InsnID*/0, /*Opcode*/GIMT_Encode2(AMDGPU::GLOBAL_STORE_DWORDX2),
      GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/0, // vaddr
      GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/0, // data
      GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/1, // offset
      GIR_AddImm8, /*InsnID*/0, /*Imm*/0,
      GIR_MergeMemOperands, /*InsnID*/0, /*NumInsns*/1, /*MergeInsnID's*/0,
      GIR_ConstrainSelectedInstOperands, /*InsnID*/0,
      GIR_EraseFromParent, /*InsnID*/0,
      // GIR_Coverage, 3066,
      GIR_Done,
    // Label 1902: @123979
    GIM_Try, /*On fail goto*//*Label 1903*/ GIMT_Encode4(124037), // Rule ID 2806 //
      GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasFlatAddressSpace),
      GIM_CheckMemoryAddressSpace, /*MI*/0, /*MMO*/0, /*NumAddrSpace*/2, /*AddrSpace*/0, /*AddrSpace*/1,
      GIM_CheckAtomicOrdering, /*MI*/0, /*Order*/(uint8_t)AtomicOrdering::NotAtomic,
      GIM_CheckPointerToAny, /*MI*/0, /*Op*/1, /*SizeInBits*/0,
      GIM_CheckComplexPattern, /*MI*/0, /*Op*/1, /*Renderer*/GIMT_Encode2(0), GIMT_Encode2(GICP_gi_flat_offset),
      // (st p4:{ *:[i64] }:$data, (FlatOffset:{ *:[iPTR] } i64:{ *:[i64] }:$vaddr, i32:{ *:[i32] }:$offset))<<P:Predicate_unindexedstore>><<P:Predicate_store_flat>>  =>  (FLAT_STORE_DWORDX2 ?:{ *:[i64] }:$vaddr, anonymous_15036:{ *:[i64] }:$data, ?:{ *:[i32] }:$offset)
      GIR_BuildMI, /*InsnID*/0, /*Opcode*/GIMT_Encode2(AMDGPU::FLAT_STORE_DWORDX2),
      GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/0, // vaddr
      GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/0, // data
      GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/1, // offset
      GIR_AddImm8, /*InsnID*/0, /*Imm*/0,
      GIR_MergeMemOperands, /*InsnID*/0, /*NumInsns*/1, /*MergeInsnID's*/0,
      GIR_ConstrainSelectedInstOperands, /*InsnID*/0,
      GIR_EraseFromParent, /*InsnID*/0,
      // GIR_Coverage, 2806,
      GIR_Done,
    // Label 1903: @124037
    GIM_Reject,
    // Label 1811: @124038
    GIM_Try, /*On fail goto*//*Label 1904*/ GIMT_Encode4(124103), // Rule ID 5542 //
      GIM_CheckFeatures, GIMT_Encode2(GIFBS_DisableFlatScratch_HasUnrestrictedSOffset),
      GIM_CheckMemoryAddressSpace, /*MI*/0, /*MMO*/0, /*NumAddrSpace*/1, /*AddrSpace*/5,
      GIM_CheckAtomicOrdering, /*MI*/0, /*Order*/(uint8_t)AtomicOrdering::NotAtomic,
      GIM_CheckPointerToAny, /*MI*/0, /*Op*/1, /*SizeInBits*/0,
      GIM_CheckComplexPattern, /*MI*/0, /*Op*/1, /*Renderer*/GIMT_Encode2(0), GIMT_Encode2(GICP_gi_mubuf_scratch_offset),
      // (st p5:{ *:[i32] }:$value, (MUBUFScratchOffset:{ *:[iPTR] } v4i32:{ *:[v4i32] }:$srsrc, i32:{ *:[i32] }:$soffset, i32:{ *:[i32] }:$offset))<<P:Predicate_unindexedstore>><<P:Predicate_store_private>>  =>  (BUFFER_STORE_DWORD_OFFSET VGPR_32:{ *:[i32] }:$value, ?:{ *:[v4i32] }:$srsrc, ?:{ *:[i32] }:$soffset, ?:{ *:[i32] }:$offset, 0:{ *:[i32] }, 0:{ *:[i1] })
      GIR_BuildMI, /*InsnID*/0, /*Opcode*/GIMT_Encode2(AMDGPU::BUFFER_STORE_DWORD_OFFSET),
      GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/0, // value
      GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/0, // srsrc
      GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/1, // soffset
      GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/2, // offset
      GIR_AddImm8, /*InsnID*/0, /*Imm*/0,
      GIR_AddImm8, /*InsnID*/0, /*Imm*/0,
      GIR_MergeMemOperands, /*InsnID*/0, /*NumInsns*/1, /*MergeInsnID's*/0,
      GIR_ConstrainSelectedInstOperands, /*InsnID*/0,
      GIR_EraseFromParent, /*InsnID*/0,
      // GIR_Coverage, 5542,
      GIR_Done,
    // Label 1904: @124103
    GIM_Try, /*On fail goto*//*Label 1905*/ GIMT_Encode4(124168), // Rule ID 5544 //
      GIM_CheckFeatures, GIMT_Encode2(GIFBS_DisableFlatScratch),
      GIM_CheckMemoryAddressSpace, /*MI*/0, /*MMO*/0, /*NumAddrSpace*/1, /*AddrSpace*/5,
      GIM_CheckAtomicOrdering, /*MI*/0, /*Order*/(uint8_t)AtomicOrdering::NotAtomic,
      GIM_CheckPointerToAny, /*MI*/0, /*Op*/1, /*SizeInBits*/0,
      GIM_CheckComplexPattern, /*MI*/0, /*Op*/1, /*Renderer*/GIMT_Encode2(0), GIMT_Encode2(GICP_gi_mubuf_scratch_offset),
      // (st p5:{ *:[i32] }:$value, (MUBUFScratchOffset:{ *:[iPTR] } v4i32:{ *:[v4i32] }:$srsrc, i32:{ *:[i32] }:$soffset, i32:{ *:[i32] }:$offset))<<P:Predicate_unindexedstore>><<P:Predicate_store_private>>  =>  (BUFFER_STORE_DWORD_VBUFFER_OFFSET VGPR_32:{ *:[i32] }:$value, ?:{ *:[v4i32] }:$srsrc, ?:{ *:[i32] }:$soffset, ?:{ *:[i32] }:$offset, 0:{ *:[i32] }, 0:{ *:[i1] })
      GIR_BuildMI, /*InsnID*/0, /*Opcode*/GIMT_Encode2(AMDGPU::BUFFER_STORE_DWORD_VBUFFER_OFFSET),
      GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/0, // value
      GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/0, // srsrc
      GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/1, // soffset
      GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/2, // offset
      GIR_AddImm8, /*InsnID*/0, /*Imm*/0,
      GIR_AddImm8, /*InsnID*/0, /*Imm*/0,
      GIR_MergeMemOperands, /*InsnID*/0, /*NumInsns*/1, /*MergeInsnID's*/0,
      GIR_ConstrainSelectedInstOperands, /*InsnID*/0,
      GIR_EraseFromParent, /*InsnID*/0,
      // GIR_Coverage, 5544,
      GIR_Done,
    // Label 1905: @124168
    GIM_Try, /*On fail goto*//*Label 1906*/ GIMT_Encode4(124230), // Rule ID 3475 //
      GIM_CheckFeatures, GIMT_Encode2(GIFBS_EnableFlatScratch_HasFlatScratchInsts_HasFlatScratchSVSMode),
      GIM_CheckMemoryAddressSpace, /*MI*/0, /*MMO*/0, /*NumAddrSpace*/1, /*AddrSpace*/5,
      GIM_CheckAtomicOrdering, /*MI*/0, /*Order*/(uint8_t)AtomicOrdering::NotAtomic,
      GIM_CheckPointerToAny, /*MI*/0, /*Op*/1, /*SizeInBits*/0,
      GIM_CheckComplexPattern, /*MI*/0, /*Op*/1, /*Renderer*/GIMT_Encode2(0), GIMT_Encode2(GICP_gi_flat_scratch_svaddr),
      // (st p5:{ *:[i32] }:$data, (ScratchSVAddr:{ *:[iPTR] } VGPR_32:{ *:[i32] }:$vaddr, SGPR_32:{ *:[i32] }:$saddr, i32:{ *:[i32] }:$offset))<<P:Predicate_unindexedstore>><<P:Predicate_store_private>>  =>  (SCRATCH_STORE_DWORD_SVS anonymous_15037:{ *:[i32] }:$data, ?:{ *:[i32] }:$vaddr, ?:{ *:[i32] }:$saddr, ?:{ *:[i32] }:$offset)
      GIR_BuildMI, /*InsnID*/0, /*Opcode*/GIMT_Encode2(AMDGPU::SCRATCH_STORE_DWORD_SVS),
      GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/0, // data
      GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/0, // vaddr
      GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/1, // saddr
      GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/2, // offset
      GIR_AddImm8, /*InsnID*/0, /*Imm*/0,
      GIR_MergeMemOperands, /*InsnID*/0, /*NumInsns*/1, /*MergeInsnID's*/0,
      GIR_ConstrainSelectedInstOperands, /*InsnID*/0,
      GIR_EraseFromParent, /*InsnID*/0,
      // GIR_Coverage, 3475,
      GIR_Done,
    // Label 1906: @124230
    GIM_Try, /*On fail goto*//*Label 1907*/ GIMT_Encode4(124287), // Rule ID 3474 //
      GIM_CheckFeatures, GIMT_Encode2(GIFBS_EnableFlatScratch_HasFlatScratchInsts),
      GIM_CheckMemoryAddressSpace, /*MI*/0, /*MMO*/0, /*NumAddrSpace*/1, /*AddrSpace*/5,
      GIM_CheckAtomicOrdering, /*MI*/0, /*Order*/(uint8_t)AtomicOrdering::NotAtomic,
      GIM_CheckPointerToAny, /*MI*/0, /*Op*/1, /*SizeInBits*/0,
      GIM_CheckComplexPattern, /*MI*/0, /*Op*/1, /*Renderer*/GIMT_Encode2(0), GIMT_Encode2(GICP_gi_flat_scratch_saddr),
      // (st p5:{ *:[i32] }:$data, (ScratchSAddr:{ *:[iPTR] } SGPR_32:{ *:[i32] }:$saddr, i32:{ *:[i32] }:$offset))<<P:Predicate_unindexedstore>><<P:Predicate_store_private>>  =>  (SCRATCH_STORE_DWORD_SADDR anonymous_15037:{ *:[i32] }:$data, ?:{ *:[i32] }:$saddr, ?:{ *:[i32] }:$offset)
      GIR_BuildMI, /*InsnID*/0, /*Opcode*/GIMT_Encode2(AMDGPU::SCRATCH_STORE_DWORD_SADDR),
      GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/0, // data
      GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/0, // saddr
      GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/1, // offset
      GIR_AddImm8, /*InsnID*/0, /*Imm*/0,
      GIR_MergeMemOperands, /*InsnID*/0, /*NumInsns*/1, /*MergeInsnID's*/0,
      GIR_ConstrainSelectedInstOperands, /*InsnID*/0,
      GIR_EraseFromParent, /*InsnID*/0,
      // GIR_Coverage, 3474,
      GIR_Done,
    // Label 1907: @124287
    GIM_Try, /*On fail goto*//*Label 1908*/ GIMT_Encode4(124344), // Rule ID 3473 //
      GIM_CheckFeatures, GIMT_Encode2(GIFBS_EnableFlatScratch_HasFlatScratchInsts),
      GIM_CheckMemoryAddressSpace, /*MI*/0, /*MMO*/0, /*NumAddrSpace*/1, /*AddrSpace*/5,
      GIM_CheckAtomicOrdering, /*MI*/0, /*Order*/(uint8_t)AtomicOrdering::NotAtomic,
      GIM_CheckPointerToAny, /*MI*/0, /*Op*/1, /*SizeInBits*/0,
      GIM_CheckComplexPattern, /*MI*/0, /*Op*/1, /*Renderer*/GIMT_Encode2(0), GIMT_Encode2(GICP_gi_flat_scratch_offset),
      // (st p5:{ *:[i32] }:$data, (ScratchOffset:{ *:[iPTR] } VGPR_32:{ *:[i32] }:$vaddr, i32:{ *:[i32] }:$offset))<<P:Predicate_unindexedstore>><<P:Predicate_store_private>>  =>  (SCRATCH_STORE_DWORD anonymous_15037:{ *:[i32] }:$data, ?:{ *:[i32] }:$vaddr, ?:{ *:[i32] }:$offset)
      GIR_BuildMI, /*InsnID*/0, /*Opcode*/GIMT_Encode2(AMDGPU::SCRATCH_STORE_DWORD),
      GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/0, // data
      GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/0, // vaddr
      GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/1, // offset
      GIR_AddImm8, /*InsnID*/0, /*Imm*/0,
      GIR_MergeMemOperands, /*InsnID*/0, /*NumInsns*/1, /*MergeInsnID's*/0,
      GIR_ConstrainSelectedInstOperands, /*InsnID*/0,
      GIR_EraseFromParent, /*InsnID*/0,
      // GIR_Coverage, 3473,
      GIR_Done,
    // Label 1908: @124344
    GIM_Try, /*On fail goto*//*Label 1909*/ GIMT_Encode4(124414), // Rule ID 3830 //
      GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasUnrestrictedSOffset),
      GIM_CheckMemoryAddressSpace, /*MI*/0, /*MMO*/0, /*NumAddrSpace*/1, /*AddrSpace*/1,
      GIM_CheckAtomicOrdering, /*MI*/0, /*Order*/(uint8_t)AtomicOrdering::NotAtomic,
      GIM_CheckPointerToAny, /*MI*/0, /*Op*/1, /*SizeInBits*/0,
      GIM_CheckComplexPattern, /*MI*/0, /*Op*/1, /*Renderer*/GIMT_Encode2(0), GIMT_Encode2(GICP_gi_mubuf_addr64),
      // (st p5:{ *:[i32] }:$vdata, (MUBUFAddr64:{ *:[iPTR] } v4i32:{ *:[v4i32] }:$srsrc, i64:{ *:[i64] }:$vaddr, i32:{ *:[i32] }:$soffset, i32:{ *:[i32] }:$offset))<<P:Predicate_unindexedstore>><<P:Predicate_store_global>>  =>  (BUFFER_STORE_DWORD_ADDR64 p5:{ *:[i32] }:$vdata, i64:{ *:[i64] }:$vaddr, v4i32:{ *:[v4i32] }:$srsrc, i32:{ *:[i32] }:$soffset, i32:{ *:[i32] }:$offset)
      GIR_BuildMI, /*InsnID*/0, /*Opcode*/GIMT_Encode2(AMDGPU::BUFFER_STORE_DWORD_ADDR64),
      GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/0, // vdata
      GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/1, // vaddr
      GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/0, // srsrc
      GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/2, // soffset
      GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/3, // offset
      GIR_AddImm8, /*InsnID*/0, /*Imm*/0,
      GIR_AddImm8, /*InsnID*/0, /*Imm*/0,
      GIR_MergeMemOperands, /*InsnID*/0, /*NumInsns*/1, /*MergeInsnID's*/0,
      GIR_ConstrainSelectedInstOperands, /*InsnID*/0,
      GIR_EraseFromParent, /*InsnID*/0,
      // GIR_Coverage, 3830,
      GIR_Done,
    // Label 1909: @124414
    GIM_Try, /*On fail goto*//*Label 1910*/ GIMT_Encode4(124481), // Rule ID 3832 //
      GIM_CheckMemoryAddressSpace, /*MI*/0, /*MMO*/0, /*NumAddrSpace*/1, /*AddrSpace*/1,
      GIM_CheckAtomicOrdering, /*MI*/0, /*Order*/(uint8_t)AtomicOrdering::NotAtomic,
      GIM_CheckPointerToAny, /*MI*/0, /*Op*/1, /*SizeInBits*/0,
      GIM_CheckComplexPattern, /*MI*/0, /*Op*/1, /*Renderer*/GIMT_Encode2(0), GIMT_Encode2(GICP_gi_mubuf_addr64),
      // (st p5:{ *:[i32] }:$vdata, (MUBUFAddr64:{ *:[iPTR] } v4i32:{ *:[v4i32] }:$srsrc, i64:{ *:[i64] }:$vaddr, i32:{ *:[i32] }:$soffset, i32:{ *:[i32] }:$offset))<<P:Predicate_unindexedstore>><<P:Predicate_store_global>>  =>  (BUFFER_STORE_DWORD_VBUFFER_ADDR64 p5:{ *:[i32] }:$vdata, i64:{ *:[i64] }:$vaddr, v4i32:{ *:[v4i32] }:$srsrc, i32:{ *:[i32] }:$soffset, i32:{ *:[i32] }:$offset)
      GIR_BuildMI, /*InsnID*/0, /*Opcode*/GIMT_Encode2(AMDGPU::BUFFER_STORE_DWORD_VBUFFER_ADDR64),
      GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/0, // vdata
      GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/1, // vaddr
      GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/0, // srsrc
      GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/2, // soffset
      GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/3, // offset
      GIR_AddImm8, /*InsnID*/0, /*Imm*/0,
      GIR_AddImm8, /*InsnID*/0, /*Imm*/0,
      GIR_MergeMemOperands, /*InsnID*/0, /*NumInsns*/1, /*MergeInsnID's*/0,
      GIR_ConstrainSelectedInstOperands, /*InsnID*/0,
      GIR_EraseFromParent, /*InsnID*/0,
      // GIR_Coverage, 3832,
      GIR_Done,
    // Label 1910: @124481
    GIM_Try, /*On fail goto*//*Label 1911*/ GIMT_Encode4(124551), // Rule ID 5541 //
      GIM_CheckFeatures, GIMT_Encode2(GIFBS_DisableFlatScratch_HasUnrestrictedSOffset),
      GIM_CheckMemoryAddressSpace, /*MI*/0, /*MMO*/0, /*NumAddrSpace*/1, /*AddrSpace*/5,
      GIM_CheckAtomicOrdering, /*MI*/0, /*Order*/(uint8_t)AtomicOrdering::NotAtomic,
      GIM_CheckPointerToAny, /*MI*/0, /*Op*/1, /*SizeInBits*/0,
      GIM_CheckComplexPattern, /*MI*/0, /*Op*/1, /*Renderer*/GIMT_Encode2(0), GIMT_Encode2(GICP_gi_mubuf_scratch_offen),
      // (st p5:{ *:[i32] }:$value, (MUBUFScratchOffen:{ *:[iPTR] } v4i32:{ *:[v4i32] }:$srsrc, i32:{ *:[i32] }:$vaddr, i32:{ *:[i32] }:$soffset, i32:{ *:[i32] }:$offset))<<P:Predicate_unindexedstore>><<P:Predicate_store_private>>  =>  (BUFFER_STORE_DWORD_OFFEN VGPR_32:{ *:[i32] }:$value, ?:{ *:[i32] }:$vaddr, ?:{ *:[v4i32] }:$srsrc, ?:{ *:[i32] }:$soffset, ?:{ *:[i32] }:$offset, 0:{ *:[i32] }, 0:{ *:[i1] })
      GIR_BuildMI, /*InsnID*/0, /*Opcode*/GIMT_Encode2(AMDGPU::BUFFER_STORE_DWORD_OFFEN),
      GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/0, // value
      GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/1, // vaddr
      GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/0, // srsrc
      GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/2, // soffset
      GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/3, // offset
      GIR_AddImm8, /*InsnID*/0, /*Imm*/0,
      GIR_AddImm8, /*InsnID*/0, /*Imm*/0,
      GIR_MergeMemOperands, /*InsnID*/0, /*NumInsns*/1, /*MergeInsnID's*/0,
      GIR_ConstrainSelectedInstOperands, /*InsnID*/0,
      GIR_EraseFromParent, /*InsnID*/0,
      // GIR_Coverage, 5541,
      GIR_Done,
    // Label 1911: @124551
    GIM_Try, /*On fail goto*//*Label 1912*/ GIMT_Encode4(124621), // Rule ID 5543 //
      GIM_CheckFeatures, GIMT_Encode2(GIFBS_DisableFlatScratch),
      GIM_CheckMemoryAddressSpace, /*MI*/0, /*MMO*/0, /*NumAddrSpace*/1, /*AddrSpace*/5,
      GIM_CheckAtomicOrdering, /*MI*/0, /*Order*/(uint8_t)AtomicOrdering::NotAtomic,
      GIM_CheckPointerToAny, /*MI*/0, /*Op*/1, /*SizeInBits*/0,
      GIM_CheckComplexPattern, /*MI*/0, /*Op*/1, /*Renderer*/GIMT_Encode2(0), GIMT_Encode2(GICP_gi_mubuf_scratch_offen),
      // (st p5:{ *:[i32] }:$value, (MUBUFScratchOffen:{ *:[iPTR] } v4i32:{ *:[v4i32] }:$srsrc, i32:{ *:[i32] }:$vaddr, i32:{ *:[i32] }:$soffset, i32:{ *:[i32] }:$offset))<<P:Predicate_unindexedstore>><<P:Predicate_store_private>>  =>  (BUFFER_STORE_DWORD_VBUFFER_OFFEN VGPR_32:{ *:[i32] }:$value, ?:{ *:[i32] }:$vaddr, ?:{ *:[v4i32] }:$srsrc, ?:{ *:[i32] }:$soffset, ?:{ *:[i32] }:$offset, 0:{ *:[i32] }, 0:{ *:[i1] })
      GIR_BuildMI, /*InsnID*/0, /*Opcode*/GIMT_Encode2(AMDGPU::BUFFER_STORE_DWORD_VBUFFER_OFFEN),
      GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/0, // value
      GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/1, // vaddr
      GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/0, // srsrc
      GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/2, // soffset
      GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/3, // offset
      GIR_AddImm8, /*InsnID*/0, /*Imm*/0,
      GIR_AddImm8, /*InsnID*/0, /*Imm*/0,
      GIR_MergeMemOperands, /*InsnID*/0, /*NumInsns*/1, /*MergeInsnID's*/0,
      GIR_ConstrainSelectedInstOperands, /*InsnID*/0,
      GIR_EraseFromParent, /*InsnID*/0,
      // GIR_Coverage, 5543,
      GIR_Done,
    // Label 1912: @124621
    GIM_Try, /*On fail goto*//*Label 1913*/ GIMT_Encode4(124686), // Rule ID 3829 //
      GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasUnrestrictedSOffset),
      GIM_CheckMemoryAddressSpace, /*MI*/0, /*MMO*/0, /*NumAddrSpace*/1, /*AddrSpace*/1,
      GIM_CheckAtomicOrdering, /*MI*/0, /*Order*/(uint8_t)AtomicOrdering::NotAtomic,
      GIM_CheckPointerToAny, /*MI*/0, /*Op*/1, /*SizeInBits*/0,
      GIM_CheckComplexPattern, /*MI*/0, /*Op*/1, /*Renderer*/GIMT_Encode2(0), GIMT_Encode2(GICP_gi_mubuf_offset),
      // (st p5:{ *:[i32] }:$vdata, (MUBUFOffset:{ *:[iPTR] } v4i32:{ *:[v4i32] }:$srsrc, i32:{ *:[i32] }:$soffset, i32:{ *:[i32] }:$offset))<<P:Predicate_unindexedstore>><<P:Predicate_store_global>>  =>  (BUFFER_STORE_DWORD_OFFSET p5:{ *:[i32] }:$vdata, v4i32:{ *:[v4i32] }:$srsrc, i32:{ *:[i32] }:$soffset, i32:{ *:[i32] }:$offset)
      GIR_BuildMI, /*InsnID*/0, /*Opcode*/GIMT_Encode2(AMDGPU::BUFFER_STORE_DWORD_OFFSET),
      GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/0, // vdata
      GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/0, // srsrc
      GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/1, // soffset
      GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/2, // offset
      GIR_AddImm8, /*InsnID*/0, /*Imm*/0,
      GIR_AddImm8, /*InsnID*/0, /*Imm*/0,
      GIR_MergeMemOperands, /*InsnID*/0, /*NumInsns*/1, /*MergeInsnID's*/0,
      GIR_ConstrainSelectedInstOperands, /*InsnID*/0,
      GIR_EraseFromParent, /*InsnID*/0,
      // GIR_Coverage, 3829,
      GIR_Done,
    // Label 1913: @124686
    GIM_Try, /*On fail goto*//*Label 1914*/ GIMT_Encode4(124748), // Rule ID 3831 //
      GIM_CheckMemoryAddressSpace, /*MI*/0, /*MMO*/0, /*NumAddrSpace*/1, /*AddrSpace*/1,
      GIM_CheckAtomicOrdering, /*MI*/0, /*Order*/(uint8_t)AtomicOrdering::NotAtomic,
      GIM_CheckPointerToAny, /*MI*/0, /*Op*/1, /*SizeInBits*/0,
      GIM_CheckComplexPattern, /*MI*/0, /*Op*/1, /*Renderer*/GIMT_Encode2(0), GIMT_Encode2(GICP_gi_mubuf_offset),
      // (st p5:{ *:[i32] }:$vdata, (MUBUFOffset:{ *:[iPTR] } v4i32:{ *:[v4i32] }:$srsrc, i32:{ *:[i32] }:$soffset, i32:{ *:[i32] }:$offset))<<P:Predicate_unindexedstore>><<P:Predicate_store_global>>  =>  (BUFFER_STORE_DWORD_VBUFFER_OFFSET p5:{ *:[i32] }:$vdata, v4i32:{ *:[v4i32] }:$srsrc, i32:{ *:[i32] }:$soffset, i32:{ *:[i32] }:$offset)
      GIR_BuildMI, /*InsnID*/0, /*Opcode*/GIMT_Encode2(AMDGPU::BUFFER_STORE_DWORD_VBUFFER_OFFSET),
      GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/0, // vdata
      GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/0, // srsrc
      GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/1, // soffset
      GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/2, // offset
      GIR_AddImm8, /*InsnID*/0, /*Imm*/0,
      GIR_AddImm8, /*InsnID*/0, /*Imm*/0,
      GIR_MergeMemOperands, /*InsnID*/0, /*NumInsns*/1, /*MergeInsnID's*/0,
      GIR_ConstrainSelectedInstOperands, /*InsnID*/0,
      GIR_EraseFromParent, /*InsnID*/0,
      // GIR_Coverage, 3831,
      GIR_Done,
    // Label 1914: @124748
    GIM_Try, /*On fail goto*//*Label 1915*/ GIMT_Encode4(124809), // Rule ID 6653 //
      GIM_CheckFeatures, GIMT_Encode2(GIFBS_LDSRequiresM0Init),
      GIM_CheckMemorySizeEqualToLLT, /*MI*/0, /*MMO*/0, /*OpIdx*/0,
      GIM_CheckMemoryAddressSpace, /*MI*/0, /*MMO*/0, /*NumAddrSpace*/1, /*AddrSpace*/3,
      GIM_CheckAtomicOrdering, /*MI*/0, /*Order*/(uint8_t)AtomicOrdering::NotAtomic,
      GIM_CheckPointerToAny, /*MI*/0, /*Op*/1, /*SizeInBits*/0,
      GIM_CheckComplexPattern, /*MI*/0, /*Op*/1, /*Renderer*/GIMT_Encode2(0), GIMT_Encode2(GICP_gi_ds_1addr_1offset),
      // (AMDGPUst_glue p5:{ *:[i32] }:$value, (DS1Addr1Offset:{ *:[iPTR] } i32:{ *:[i32] }:$ptr, i32:{ *:[i32] }:$offset))<<P:Predicate_unindexedstore_glue>><<P:Predicate_store_glue>><<P:Predicate_store_local_m0>>  =>  (DS_WRITE_B32 ?:{ *:[i32] }:$ptr, anonymous_15037:{ *:[i32] }:$value, offset:{ *:[i32] }:$offset, 0:{ *:[i1] })
      GIR_BuildMI, /*InsnID*/0, /*Opcode*/GIMT_Encode2(AMDGPU::DS_WRITE_B32),
      GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/0, // ptr
      GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/0, // value
      GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/1, // offset
      GIR_AddImm8, /*InsnID*/0, /*Imm*/0,
      GIR_MergeMemOperands, /*InsnID*/0, /*NumInsns*/1, /*MergeInsnID's*/0,
      GIR_ConstrainSelectedInstOperands, /*InsnID*/0,
      GIR_EraseFromParent, /*InsnID*/0,
      // GIR_Coverage, 6653,
      GIR_Done,
    // Label 1915: @124809
    GIM_Try, /*On fail goto*//*Label 1916*/ GIMT_Encode4(124866), // Rule ID 6654 //
      GIM_CheckFeatures, GIMT_Encode2(GIFBS_NotLDSRequiresM0Init),
      GIM_CheckMemoryAddressSpace, /*MI*/0, /*MMO*/0, /*NumAddrSpace*/1, /*AddrSpace*/3,
      GIM_CheckAtomicOrdering, /*MI*/0, /*Order*/(uint8_t)AtomicOrdering::NotAtomic,
      GIM_CheckPointerToAny, /*MI*/0, /*Op*/1, /*SizeInBits*/0,
      GIM_CheckComplexPattern, /*MI*/0, /*Op*/1, /*Renderer*/GIMT_Encode2(0), GIMT_Encode2(GICP_gi_ds_1addr_1offset),
      // (st p5:{ *:[i32] }:$value, (DS1Addr1Offset:{ *:[iPTR] } i32:{ *:[i32] }:$ptr, i32:{ *:[i32] }:$offset))<<P:Predicate_unindexedstore>><<P:Predicate_store_local>>  =>  (DS_WRITE_B32_gfx9 ?:{ *:[i32] }:$ptr, anonymous_15037:{ *:[i32] }:$value, offset:{ *:[i32] }:$offset, 0:{ *:[i1] })
      GIR_BuildMI, /*InsnID*/0, /*Opcode*/GIMT_Encode2(AMDGPU::DS_WRITE_B32_gfx9),
      GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/0, // ptr
      GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/0, // value
      GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/1, // offset
      GIR_AddImm8, /*InsnID*/0, /*Imm*/0,
      GIR_MergeMemOperands, /*InsnID*/0, /*NumInsns*/1, /*MergeInsnID's*/0,
      GIR_ConstrainSelectedInstOperands, /*InsnID*/0,
      GIR_EraseFromParent, /*InsnID*/0,
      // GIR_Coverage, 6654,
      GIR_Done,
    // Label 1916: @124866
    GIM_Try, /*On fail goto*//*Label 1917*/ GIMT_Encode4(124928), // Rule ID 3023 //
      GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasFlatGlobalInsts),
      GIM_CheckMemoryAddressSpace, /*MI*/0, /*MMO*/0, /*NumAddrSpace*/1, /*AddrSpace*/1,
      GIM_CheckAtomicOrdering, /*MI*/0, /*Order*/(uint8_t)AtomicOrdering::NotAtomic,
      GIM_CheckPointerToAny, /*MI*/0, /*Op*/1, /*SizeInBits*/0,
      GIM_CheckComplexPattern, /*MI*/0, /*Op*/1, /*Renderer*/GIMT_Encode2(0), GIMT_Encode2(GICP_gi_global_saddr),
      // (st p5:{ *:[i32] }:$data, (GlobalSAddr:{ *:[iPTR] } SReg_64:{ *:[i64] }:$saddr, VGPR_32:{ *:[i32] }:$voffset, i32:{ *:[i32] }:$offset))<<P:Predicate_unindexedstore>><<P:Predicate_store_global>>  =>  (GLOBAL_STORE_DWORD_SADDR ?:{ *:[i32] }:$voffset, anonymous_15037:{ *:[i32] }:$data, ?:{ *:[i64] }:$saddr, ?:{ *:[i32] }:$offset)
      GIR_BuildMI, /*InsnID*/0, /*Opcode*/GIMT_Encode2(AMDGPU::GLOBAL_STORE_DWORD_SADDR),
      GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/1, // voffset
      GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/0, // data
      GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/0, // saddr
      GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/2, // offset
      GIR_AddImm8, /*InsnID*/0, /*Imm*/0,
      GIR_MergeMemOperands, /*InsnID*/0, /*NumInsns*/1, /*MergeInsnID's*/0,
      GIR_ConstrainSelectedInstOperands, /*InsnID*/0,
      GIR_EraseFromParent, /*InsnID*/0,
      // GIR_Coverage, 3023,
      GIR_Done,
    // Label 1917: @124928
    GIM_Try, /*On fail goto*//*Label 1918*/ GIMT_Encode4(124985), // Rule ID 3022 //
      GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasFlatGlobalInsts),
      GIM_CheckMemoryAddressSpace, /*MI*/0, /*MMO*/0, /*NumAddrSpace*/1, /*AddrSpace*/1,
      GIM_CheckAtomicOrdering, /*MI*/0, /*Order*/(uint8_t)AtomicOrdering::NotAtomic,
      GIM_CheckPointerToAny, /*MI*/0, /*Op*/1, /*SizeInBits*/0,
      GIM_CheckComplexPattern, /*MI*/0, /*Op*/1, /*Renderer*/GIMT_Encode2(0), GIMT_Encode2(GICP_gi_global_offset),
      // (st p5:{ *:[i32] }:$data, (GlobalOffset:{ *:[iPTR] } i64:{ *:[i64] }:$vaddr, i32:{ *:[i32] }:$offset))<<P:Predicate_unindexedstore>><<P:Predicate_store_global>>  =>  (GLOBAL_STORE_DWORD ?:{ *:[i64] }:$vaddr, anonymous_15037:{ *:[i32] }:$data, ?:{ *:[i32] }:$offset)
      GIR_BuildMI, /*InsnID*/0, /*Opcode*/GIMT_Encode2(AMDGPU::GLOBAL_STORE_DWORD),
      GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/0, // vaddr
      GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/0, // data
      GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/1, // offset
      GIR_AddImm8, /*InsnID*/0, /*Imm*/0,
      GIR_MergeMemOperands, /*InsnID*/0, /*NumInsns*/1, /*MergeInsnID's*/0,
      GIR_ConstrainSelectedInstOperands, /*InsnID*/0,
      GIR_EraseFromParent, /*InsnID*/0,
      // GIR_Coverage, 3022,
      GIR_Done,
    // Label 1918: @124985
    GIM_Try, /*On fail goto*//*Label 1919*/ GIMT_Encode4(125043), // Rule ID 2785 //
      GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasFlatAddressSpace),
      GIM_CheckMemoryAddressSpace, /*MI*/0, /*MMO*/0, /*NumAddrSpace*/2, /*AddrSpace*/0, /*AddrSpace*/1,
      GIM_CheckAtomicOrdering, /*MI*/0, /*Order*/(uint8_t)AtomicOrdering::NotAtomic,
      GIM_CheckPointerToAny, /*MI*/0, /*Op*/1, /*SizeInBits*/0,
      GIM_CheckComplexPattern, /*MI*/0, /*Op*/1, /*Renderer*/GIMT_Encode2(0), GIMT_Encode2(GICP_gi_flat_offset),
      // (st p5:{ *:[i32] }:$data, (FlatOffset:{ *:[iPTR] } i64:{ *:[i64] }:$vaddr, i32:{ *:[i32] }:$offset))<<P:Predicate_unindexedstore>><<P:Predicate_store_flat>>  =>  (FLAT_STORE_DWORD ?:{ *:[i64] }:$vaddr, anonymous_15037:{ *:[i32] }:$data, ?:{ *:[i32] }:$offset)
      GIR_BuildMI, /*InsnID*/0, /*Opcode*/GIMT_Encode2(AMDGPU::FLAT_STORE_DWORD),
      GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/0, // vaddr
      GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/0, // data
      GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/1, // offset
      GIR_AddImm8, /*InsnID*/0, /*Imm*/0,
      GIR_MergeMemOperands, /*InsnID*/0, /*NumInsns*/1, /*MergeInsnID's*/0,
      GIR_ConstrainSelectedInstOperands, /*InsnID*/0,
      GIR_EraseFromParent, /*InsnID*/0,
      // GIR_Coverage, 2785,
      GIR_Done,
    // Label 1919: @125043
    GIM_Reject,
    // Label 1812: @125044
    GIM_Try, /*On fail goto*//*Label 1920*/ GIMT_Encode4(125109), // Rule ID 5546 //
      GIM_CheckFeatures, GIMT_Encode2(GIFBS_DisableFlatScratch_HasUnrestrictedSOffset),
      GIM_CheckMemoryAddressSpace, /*MI*/0, /*MMO*/0, /*NumAddrSpace*/1, /*AddrSpace*/5,
      GIM_CheckAtomicOrdering, /*MI*/0, /*Order*/(uint8_t)AtomicOrdering::NotAtomic,
      GIM_CheckPointerToAny, /*MI*/0, /*Op*/1, /*SizeInBits*/0,
      GIM_CheckComplexPattern, /*MI*/0, /*Op*/1, /*Renderer*/GIMT_Encode2(0), GIMT_Encode2(GICP_gi_mubuf_scratch_offset),
      // (st p6:{ *:[i32] }:$value, (MUBUFScratchOffset:{ *:[iPTR] } v4i32:{ *:[v4i32] }:$srsrc, i32:{ *:[i32] }:$soffset, i32:{ *:[i32] }:$offset))<<P:Predicate_unindexedstore>><<P:Predicate_store_private>>  =>  (BUFFER_STORE_DWORD_OFFSET VGPR_32:{ *:[i32] }:$value, ?:{ *:[v4i32] }:$srsrc, ?:{ *:[i32] }:$soffset, ?:{ *:[i32] }:$offset, 0:{ *:[i32] }, 0:{ *:[i1] })
      GIR_BuildMI, /*InsnID*/0, /*Opcode*/GIMT_Encode2(AMDGPU::BUFFER_STORE_DWORD_OFFSET),
      GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/0, // value
      GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/0, // srsrc
      GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/1, // soffset
      GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/2, // offset
      GIR_AddImm8, /*InsnID*/0, /*Imm*/0,
      GIR_AddImm8, /*InsnID*/0, /*Imm*/0,
      GIR_MergeMemOperands, /*InsnID*/0, /*NumInsns*/1, /*MergeInsnID's*/0,
      GIR_ConstrainSelectedInstOperands, /*InsnID*/0,
      GIR_EraseFromParent, /*InsnID*/0,
      // GIR_Coverage, 5546,
      GIR_Done,
    // Label 1920: @125109
    GIM_Try, /*On fail goto*//*Label 1921*/ GIMT_Encode4(125174), // Rule ID 5548 //
      GIM_CheckFeatures, GIMT_Encode2(GIFBS_DisableFlatScratch),
      GIM_CheckMemoryAddressSpace, /*MI*/0, /*MMO*/0, /*NumAddrSpace*/1, /*AddrSpace*/5,
      GIM_CheckAtomicOrdering, /*MI*/0, /*Order*/(uint8_t)AtomicOrdering::NotAtomic,
      GIM_CheckPointerToAny, /*MI*/0, /*Op*/1, /*SizeInBits*/0,
      GIM_CheckComplexPattern, /*MI*/0, /*Op*/1, /*Renderer*/GIMT_Encode2(0), GIMT_Encode2(GICP_gi_mubuf_scratch_offset),
      // (st p6:{ *:[i32] }:$value, (MUBUFScratchOffset:{ *:[iPTR] } v4i32:{ *:[v4i32] }:$srsrc, i32:{ *:[i32] }:$soffset, i32:{ *:[i32] }:$offset))<<P:Predicate_unindexedstore>><<P:Predicate_store_private>>  =>  (BUFFER_STORE_DWORD_VBUFFER_OFFSET VGPR_32:{ *:[i32] }:$value, ?:{ *:[v4i32] }:$srsrc, ?:{ *:[i32] }:$soffset, ?:{ *:[i32] }:$offset, 0:{ *:[i32] }, 0:{ *:[i1] })
      GIR_BuildMI, /*InsnID*/0, /*Opcode*/GIMT_Encode2(AMDGPU::BUFFER_STORE_DWORD_VBUFFER_OFFSET),
      GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/0, // value
      GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/0, // srsrc
      GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/1, // soffset
      GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/2, // offset
      GIR_AddImm8, /*InsnID*/0, /*Imm*/0,
      GIR_AddImm8, /*InsnID*/0, /*Imm*/0,
      GIR_MergeMemOperands, /*InsnID*/0, /*NumInsns*/1, /*MergeInsnID's*/0,
      GIR_ConstrainSelectedInstOperands, /*InsnID*/0,
      GIR_EraseFromParent, /*InsnID*/0,
      // GIR_Coverage, 5548,
      GIR_Done,
    // Label 1921: @125174
    GIM_Try, /*On fail goto*//*Label 1922*/ GIMT_Encode4(125236), // Rule ID 3481 //
      GIM_CheckFeatures, GIMT_Encode2(GIFBS_EnableFlatScratch_HasFlatScratchInsts_HasFlatScratchSVSMode),
      GIM_CheckMemoryAddressSpace, /*MI*/0, /*MMO*/0, /*NumAddrSpace*/1, /*AddrSpace*/5,
      GIM_CheckAtomicOrdering, /*MI*/0, /*Order*/(uint8_t)AtomicOrdering::NotAtomic,
      GIM_CheckPointerToAny, /*MI*/0, /*Op*/1, /*SizeInBits*/0,
      GIM_CheckComplexPattern, /*MI*/0, /*Op*/1, /*Renderer*/GIMT_Encode2(0), GIMT_Encode2(GICP_gi_flat_scratch_svaddr),
      // (st p6:{ *:[i32] }:$data, (ScratchSVAddr:{ *:[iPTR] } VGPR_32:{ *:[i32] }:$vaddr, SGPR_32:{ *:[i32] }:$saddr, i32:{ *:[i32] }:$offset))<<P:Predicate_unindexedstore>><<P:Predicate_store_private>>  =>  (SCRATCH_STORE_DWORD_SVS anonymous_15037:{ *:[i32] }:$data, ?:{ *:[i32] }:$vaddr, ?:{ *:[i32] }:$saddr, ?:{ *:[i32] }:$offset)
      GIR_BuildMI, /*InsnID*/0, /*Opcode*/GIMT_Encode2(AMDGPU::SCRATCH_STORE_DWORD_SVS),
      GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/0, // data
      GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/0, // vaddr
      GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/1, // saddr
      GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/2, // offset
      GIR_AddImm8, /*InsnID*/0, /*Imm*/0,
      GIR_MergeMemOperands, /*InsnID*/0, /*NumInsns*/1, /*MergeInsnID's*/0,
      GIR_ConstrainSelectedInstOperands, /*InsnID*/0,
      GIR_EraseFromParent, /*InsnID*/0,
      // GIR_Coverage, 3481,
      GIR_Done,
    // Label 1922: @125236
    GIM_Try, /*On fail goto*//*Label 1923*/ GIMT_Encode4(125293), // Rule ID 3480 //
      GIM_CheckFeatures, GIMT_Encode2(GIFBS_EnableFlatScratch_HasFlatScratchInsts),
      GIM_CheckMemoryAddressSpace, /*MI*/0, /*MMO*/0, /*NumAddrSpace*/1, /*AddrSpace*/5,
      GIM_CheckAtomicOrdering, /*MI*/0, /*Order*/(uint8_t)AtomicOrdering::NotAtomic,
      GIM_CheckPointerToAny, /*MI*/0, /*Op*/1, /*SizeInBits*/0,
      GIM_CheckComplexPattern, /*MI*/0, /*Op*/1, /*Renderer*/GIMT_Encode2(0), GIMT_Encode2(GICP_gi_flat_scratch_saddr),
      // (st p6:{ *:[i32] }:$data, (ScratchSAddr:{ *:[iPTR] } SGPR_32:{ *:[i32] }:$saddr, i32:{ *:[i32] }:$offset))<<P:Predicate_unindexedstore>><<P:Predicate_store_private>>  =>  (SCRATCH_STORE_DWORD_SADDR anonymous_15037:{ *:[i32] }:$data, ?:{ *:[i32] }:$saddr, ?:{ *:[i32] }:$offset)
      GIR_BuildMI, /*InsnID*/0, /*Opcode*/GIMT_Encode2(AMDGPU::SCRATCH_STORE_DWORD_SADDR),
      GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/0, // data
      GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/0, // saddr
      GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/1, // offset
      GIR_AddImm8, /*InsnID*/0, /*Imm*/0,
      GIR_MergeMemOperands, /*InsnID*/0, /*NumInsns*/1, /*MergeInsnID's*/0,
      GIR_ConstrainSelectedInstOperands, /*InsnID*/0,
      GIR_EraseFromParent, /*InsnID*/0,
      // GIR_Coverage, 3480,
      GIR_Done,
    // Label 1923: @125293
    GIM_Try, /*On fail goto*//*Label 1924*/ GIMT_Encode4(125350), // Rule ID 3479 //
      GIM_CheckFeatures, GIMT_Encode2(GIFBS_EnableFlatScratch_HasFlatScratchInsts),
      GIM_CheckMemoryAddressSpace, /*MI*/0, /*MMO*/0, /*NumAddrSpace*/1, /*AddrSpace*/5,
      GIM_CheckAtomicOrdering, /*MI*/0, /*Order*/(uint8_t)AtomicOrdering::NotAtomic,
      GIM_CheckPointerToAny, /*MI*/0, /*Op*/1, /*SizeInBits*/0,
      GIM_CheckComplexPattern, /*MI*/0, /*Op*/1, /*Renderer*/GIMT_Encode2(0), GIMT_Encode2(GICP_gi_flat_scratch_offset),
      // (st p6:{ *:[i32] }:$data, (ScratchOffset:{ *:[iPTR] } VGPR_32:{ *:[i32] }:$vaddr, i32:{ *:[i32] }:$offset))<<P:Predicate_unindexedstore>><<P:Predicate_store_private>>  =>  (SCRATCH_STORE_DWORD anonymous_15037:{ *:[i32] }:$data, ?:{ *:[i32] }:$vaddr, ?:{ *:[i32] }:$offset)
      GIR_BuildMI, /*InsnID*/0, /*Opcode*/GIMT_Encode2(AMDGPU::SCRATCH_STORE_DWORD),
      GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/0, // data
      GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/0, // vaddr
      GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/1, // offset
      GIR_AddImm8, /*InsnID*/0, /*Imm*/0,
      GIR_MergeMemOperands, /*InsnID*/0, /*NumInsns*/1, /*MergeInsnID's*/0,
      GIR_ConstrainSelectedInstOperands, /*InsnID*/0,
      GIR_EraseFromParent, /*InsnID*/0,
      // GIR_Coverage, 3479,
      GIR_Done,
    // Label 1924: @125350
    GIM_Try, /*On fail goto*//*Label 1925*/ GIMT_Encode4(125420), // Rule ID 3834 //
      GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasUnrestrictedSOffset),
      GIM_CheckMemoryAddressSpace, /*MI*/0, /*MMO*/0, /*NumAddrSpace*/1, /*AddrSpace*/1,
      GIM_CheckAtomicOrdering, /*MI*/0, /*Order*/(uint8_t)AtomicOrdering::NotAtomic,
      GIM_CheckPointerToAny, /*MI*/0, /*Op*/1, /*SizeInBits*/0,
      GIM_CheckComplexPattern, /*MI*/0, /*Op*/1, /*Renderer*/GIMT_Encode2(0), GIMT_Encode2(GICP_gi_mubuf_addr64),
      // (st p6:{ *:[i32] }:$vdata, (MUBUFAddr64:{ *:[iPTR] } v4i32:{ *:[v4i32] }:$srsrc, i64:{ *:[i64] }:$vaddr, i32:{ *:[i32] }:$soffset, i32:{ *:[i32] }:$offset))<<P:Predicate_unindexedstore>><<P:Predicate_store_global>>  =>  (BUFFER_STORE_DWORD_ADDR64 p6:{ *:[i32] }:$vdata, i64:{ *:[i64] }:$vaddr, v4i32:{ *:[v4i32] }:$srsrc, i32:{ *:[i32] }:$soffset, i32:{ *:[i32] }:$offset)
      GIR_BuildMI, /*InsnID*/0, /*Opcode*/GIMT_Encode2(AMDGPU::BUFFER_STORE_DWORD_ADDR64),
      GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/0, // vdata
      GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/1, // vaddr
      GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/0, // srsrc
      GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/2, // soffset
      GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/3, // offset
      GIR_AddImm8, /*InsnID*/0, /*Imm*/0,
      GIR_AddImm8, /*InsnID*/0, /*Imm*/0,
      GIR_MergeMemOperands, /*InsnID*/0, /*NumInsns*/1, /*MergeInsnID's*/0,
      GIR_ConstrainSelectedInstOperands, /*InsnID*/0,
      GIR_EraseFromParent, /*InsnID*/0,
      // GIR_Coverage, 3834,
      GIR_Done,
    // Label 1925: @125420
    GIM_Try, /*On fail goto*//*Label 1926*/ GIMT_Encode4(125487), // Rule ID 3836 //
      GIM_CheckMemoryAddressSpace, /*MI*/0, /*MMO*/0, /*NumAddrSpace*/1, /*AddrSpace*/1,
      GIM_CheckAtomicOrdering, /*MI*/0, /*Order*/(uint8_t)AtomicOrdering::NotAtomic,
      GIM_CheckPointerToAny, /*MI*/0, /*Op*/1, /*SizeInBits*/0,
      GIM_CheckComplexPattern, /*MI*/0, /*Op*/1, /*Renderer*/GIMT_Encode2(0), GIMT_Encode2(GICP_gi_mubuf_addr64),
      // (st p6:{ *:[i32] }:$vdata, (MUBUFAddr64:{ *:[iPTR] } v4i32:{ *:[v4i32] }:$srsrc, i64:{ *:[i64] }:$vaddr, i32:{ *:[i32] }:$soffset, i32:{ *:[i32] }:$offset))<<P:Predicate_unindexedstore>><<P:Predicate_store_global>>  =>  (BUFFER_STORE_DWORD_VBUFFER_ADDR64 p6:{ *:[i32] }:$vdata, i64:{ *:[i64] }:$vaddr, v4i32:{ *:[v4i32] }:$srsrc, i32:{ *:[i32] }:$soffset, i32:{ *:[i32] }:$offset)
      GIR_BuildMI, /*InsnID*/0, /*Opcode*/GIMT_Encode2(AMDGPU::BUFFER_STORE_DWORD_VBUFFER_ADDR64),
      GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/0, // vdata
      GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/1, // vaddr
      GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/0, // srsrc
      GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/2, // soffset
      GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/3, // offset
      GIR_AddImm8, /*InsnID*/0, /*Imm*/0,
      GIR_AddImm8, /*InsnID*/0, /*Imm*/0,
      GIR_MergeMemOperands, /*InsnID*/0, /*NumInsns*/1, /*MergeInsnID's*/0,
      GIR_ConstrainSelectedInstOperands, /*InsnID*/0,
      GIR_EraseFromParent, /*InsnID*/0,
      // GIR_Coverage, 3836,
      GIR_Done,
    // Label 1926: @125487
    GIM_Try, /*On fail goto*//*Label 1927*/ GIMT_Encode4(125557), // Rule ID 5545 //
      GIM_CheckFeatures, GIMT_Encode2(GIFBS_DisableFlatScratch_HasUnrestrictedSOffset),
      GIM_CheckMemoryAddressSpace, /*MI*/0, /*MMO*/0, /*NumAddrSpace*/1, /*AddrSpace*/5,
      GIM_CheckAtomicOrdering, /*MI*/0, /*Order*/(uint8_t)AtomicOrdering::NotAtomic,
      GIM_CheckPointerToAny, /*MI*/0, /*Op*/1, /*SizeInBits*/0,
      GIM_CheckComplexPattern, /*MI*/0, /*Op*/1, /*Renderer*/GIMT_Encode2(0), GIMT_Encode2(GICP_gi_mubuf_scratch_offen),
      // (st p6:{ *:[i32] }:$value, (MUBUFScratchOffen:{ *:[iPTR] } v4i32:{ *:[v4i32] }:$srsrc, i32:{ *:[i32] }:$vaddr, i32:{ *:[i32] }:$soffset, i32:{ *:[i32] }:$offset))<<P:Predicate_unindexedstore>><<P:Predicate_store_private>>  =>  (BUFFER_STORE_DWORD_OFFEN VGPR_32:{ *:[i32] }:$value, ?:{ *:[i32] }:$vaddr, ?:{ *:[v4i32] }:$srsrc, ?:{ *:[i32] }:$soffset, ?:{ *:[i32] }:$offset, 0:{ *:[i32] }, 0:{ *:[i1] })
      GIR_BuildMI, /*InsnID*/0, /*Opcode*/GIMT_Encode2(AMDGPU::BUFFER_STORE_DWORD_OFFEN),
      GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/0, // value
      GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/1, // vaddr
      GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/0, // srsrc
      GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/2, // soffset
      GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/3, // offset
      GIR_AddImm8, /*InsnID*/0, /*Imm*/0,
      GIR_AddImm8, /*InsnID*/0, /*Imm*/0,
      GIR_MergeMemOperands, /*InsnID*/0, /*NumInsns*/1, /*MergeInsnID's*/0,
      GIR_ConstrainSelectedInstOperands, /*InsnID*/0,
      GIR_EraseFromParent, /*InsnID*/0,
      // GIR_Coverage, 5545,
      GIR_Done,
    // Label 1927: @125557
    GIM_Try, /*On fail goto*//*Label 1928*/ GIMT_Encode4(125627), // Rule ID 5547 //
      GIM_CheckFeatures, GIMT_Encode2(GIFBS_DisableFlatScratch),
      GIM_CheckMemoryAddressSpace, /*MI*/0, /*MMO*/0, /*NumAddrSpace*/1, /*AddrSpace*/5,
      GIM_CheckAtomicOrdering, /*MI*/0, /*Order*/(uint8_t)AtomicOrdering::NotAtomic,
      GIM_CheckPointerToAny, /*MI*/0, /*Op*/1, /*SizeInBits*/0,
      GIM_CheckComplexPattern, /*MI*/0, /*Op*/1, /*Renderer*/GIMT_Encode2(0), GIMT_Encode2(GICP_gi_mubuf_scratch_offen),
      // (st p6:{ *:[i32] }:$value, (MUBUFScratchOffen:{ *:[iPTR] } v4i32:{ *:[v4i32] }:$srsrc, i32:{ *:[i32] }:$vaddr, i32:{ *:[i32] }:$soffset, i32:{ *:[i32] }:$offset))<<P:Predicate_unindexedstore>><<P:Predicate_store_private>>  =>  (BUFFER_STORE_DWORD_VBUFFER_OFFEN VGPR_32:{ *:[i32] }:$value, ?:{ *:[i32] }:$vaddr, ?:{ *:[v4i32] }:$srsrc, ?:{ *:[i32] }:$soffset, ?:{ *:[i32] }:$offset, 0:{ *:[i32] }, 0:{ *:[i1] })
      GIR_BuildMI, /*InsnID*/0, /*Opcode*/GIMT_Encode2(AMDGPU::BUFFER_STORE_DWORD_VBUFFER_OFFEN),
      GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/0, // value
      GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/1, // vaddr
      GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/0, // srsrc
      GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/2, // soffset
      GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/3, // offset
      GIR_AddImm8, /*InsnID*/0, /*Imm*/0,
      GIR_AddImm8, /*InsnID*/0, /*Imm*/0,
      GIR_MergeMemOperands, /*InsnID*/0, /*NumInsns*/1, /*MergeInsnID's*/0,
      GIR_ConstrainSelectedInstOperands, /*InsnID*/0,
      GIR_EraseFromParent, /*InsnID*/0,
      // GIR_Coverage, 5547,
      GIR_Done,
    // Label 1928: @125627
    GIM_Try, /*On fail goto*//*Label 1929*/ GIMT_Encode4(125692), // Rule ID 3833 //
      GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasUnrestrictedSOffset),
      GIM_CheckMemoryAddressSpace, /*MI*/0, /*MMO*/0, /*NumAddrSpace*/1, /*AddrSpace*/1,
      GIM_CheckAtomicOrdering, /*MI*/0, /*Order*/(uint8_t)AtomicOrdering::NotAtomic,
      GIM_CheckPointerToAny, /*MI*/0, /*Op*/1, /*SizeInBits*/0,
      GIM_CheckComplexPattern, /*MI*/0, /*Op*/1, /*Renderer*/GIMT_Encode2(0), GIMT_Encode2(GICP_gi_mubuf_offset),
      // (st p6:{ *:[i32] }:$vdata, (MUBUFOffset:{ *:[iPTR] } v4i32:{ *:[v4i32] }:$srsrc, i32:{ *:[i32] }:$soffset, i32:{ *:[i32] }:$offset))<<P:Predicate_unindexedstore>><<P:Predicate_store_global>>  =>  (BUFFER_STORE_DWORD_OFFSET p6:{ *:[i32] }:$vdata, v4i32:{ *:[v4i32] }:$srsrc, i32:{ *:[i32] }:$soffset, i32:{ *:[i32] }:$offset)
      GIR_BuildMI, /*InsnID*/0, /*Opcode*/GIMT_Encode2(AMDGPU::BUFFER_STORE_DWORD_OFFSET),
      GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/0, // vdata
      GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/0, // srsrc
      GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/1, // soffset
      GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/2, // offset
      GIR_AddImm8, /*InsnID*/0, /*Imm*/0,
      GIR_AddImm8, /*InsnID*/0, /*Imm*/0,
      GIR_MergeMemOperands, /*InsnID*/0, /*NumInsns*/1, /*MergeInsnID's*/0,
      GIR_ConstrainSelectedInstOperands, /*InsnID*/0,
      GIR_EraseFromParent, /*InsnID*/0,
      // GIR_Coverage, 3833,
      GIR_Done,
    // Label 1929: @125692
    GIM_Try, /*On fail goto*//*Label 1930*/ GIMT_Encode4(125754), // Rule ID 3835 //
      GIM_CheckMemoryAddressSpace, /*MI*/0, /*MMO*/0, /*NumAddrSpace*/1, /*AddrSpace*/1,
      GIM_CheckAtomicOrdering, /*MI*/0, /*Order*/(uint8_t)AtomicOrdering::NotAtomic,
      GIM_CheckPointerToAny, /*MI*/0, /*Op*/1, /*SizeInBits*/0,
      GIM_CheckComplexPattern, /*MI*/0, /*Op*/1, /*Renderer*/GIMT_Encode2(0), GIMT_Encode2(GICP_gi_mubuf_offset),
      // (st p6:{ *:[i32] }:$vdata, (MUBUFOffset:{ *:[iPTR] } v4i32:{ *:[v4i32] }:$srsrc, i32:{ *:[i32] }:$soffset, i32:{ *:[i32] }:$offset))<<P:Predicate_unindexedstore>><<P:Predicate_store_global>>  =>  (BUFFER_STORE_DWORD_VBUFFER_OFFSET p6:{ *:[i32] }:$vdata, v4i32:{ *:[v4i32] }:$srsrc, i32:{ *:[i32] }:$soffset, i32:{ *:[i32] }:$offset)
      GIR_BuildMI, /*InsnID*/0, /*Opcode*/GIMT_Encode2(AMDGPU::BUFFER_STORE_DWORD_VBUFFER_OFFSET),
      GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/0, // vdata
      GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/0, // srsrc
      GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/1, // soffset
      GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/2, // offset
      GIR_AddImm8, /*InsnID*/0, /*Imm*/0,
      GIR_AddImm8, /*InsnID*/0, /*Imm*/0,
      GIR_MergeMemOperands, /*InsnID*/0, /*NumInsns*/1, /*MergeInsnID's*/0,
      GIR_ConstrainSelectedInstOperands, /*InsnID*/0,
      GIR_EraseFromParent, /*InsnID*/0,
      // GIR_Coverage, 3835,
      GIR_Done,
    // Label 1930: @125754
    GIM_Try, /*On fail goto*//*Label 1931*/ GIMT_Encode4(125815), // Rule ID 6655 //
      GIM_CheckFeatures, GIMT_Encode2(GIFBS_LDSRequiresM0Init),
      GIM_CheckMemorySizeEqualToLLT, /*MI*/0, /*MMO*/0, /*OpIdx*/0,
      GIM_CheckMemoryAddressSpace, /*MI*/0, /*MMO*/0, /*NumAddrSpace*/1, /*AddrSpace*/3,
      GIM_CheckAtomicOrdering, /*MI*/0, /*Order*/(uint8_t)AtomicOrdering::NotAtomic,
      GIM_CheckPointerToAny, /*MI*/0, /*Op*/1, /*SizeInBits*/0,
      GIM_CheckComplexPattern, /*MI*/0, /*Op*/1, /*Renderer*/GIMT_Encode2(0), GIMT_Encode2(GICP_gi_ds_1addr_1offset),
      // (AMDGPUst_glue p6:{ *:[i32] }:$value, (DS1Addr1Offset:{ *:[iPTR] } i32:{ *:[i32] }:$ptr, i32:{ *:[i32] }:$offset))<<P:Predicate_unindexedstore_glue>><<P:Predicate_store_glue>><<P:Predicate_store_local_m0>>  =>  (DS_WRITE_B32 ?:{ *:[i32] }:$ptr, anonymous_15037:{ *:[i32] }:$value, offset:{ *:[i32] }:$offset, 0:{ *:[i1] })
      GIR_BuildMI, /*InsnID*/0, /*Opcode*/GIMT_Encode2(AMDGPU::DS_WRITE_B32),
      GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/0, // ptr
      GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/0, // value
      GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/1, // offset
      GIR_AddImm8, /*InsnID*/0, /*Imm*/0,
      GIR_MergeMemOperands, /*InsnID*/0, /*NumInsns*/1, /*MergeInsnID's*/0,
      GIR_ConstrainSelectedInstOperands, /*InsnID*/0,
      GIR_EraseFromParent, /*InsnID*/0,
      // GIR_Coverage, 6655,
      GIR_Done,
    // Label 1931: @125815
    GIM_Try, /*On fail goto*//*Label 1932*/ GIMT_Encode4(125872), // Rule ID 6656 //
      GIM_CheckFeatures, GIMT_Encode2(GIFBS_NotLDSRequiresM0Init),
      GIM_CheckMemoryAddressSpace, /*MI*/0, /*MMO*/0, /*NumAddrSpace*/1, /*AddrSpace*/3,
      GIM_CheckAtomicOrdering, /*MI*/0, /*Order*/(uint8_t)AtomicOrdering::NotAtomic,
      GIM_CheckPointerToAny, /*MI*/0, /*Op*/1, /*SizeInBits*/0,
      GIM_CheckComplexPattern, /*MI*/0, /*Op*/1, /*Renderer*/GIMT_Encode2(0), GIMT_Encode2(GICP_gi_ds_1addr_1offset),
      // (st p6:{ *:[i32] }:$value, (DS1Addr1Offset:{ *:[iPTR] } i32:{ *:[i32] }:$ptr, i32:{ *:[i32] }:$offset))<<P:Predicate_unindexedstore>><<P:Predicate_store_local>>  =>  (DS_WRITE_B32_gfx9 ?:{ *:[i32] }:$ptr, anonymous_15037:{ *:[i32] }:$value, offset:{ *:[i32] }:$offset, 0:{ *:[i1] })
      GIR_BuildMI, /*InsnID*/0, /*Opcode*/GIMT_Encode2(AMDGPU::DS_WRITE_B32_gfx9),
      GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/0, // ptr
      GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/0, // value
      GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/1, // offset
      GIR_AddImm8, /*InsnID*/0, /*Imm*/0,
      GIR_MergeMemOperands, /*InsnID*/0, /*NumInsns*/1, /*MergeInsnID's*/0,
      GIR_ConstrainSelectedInstOperands, /*InsnID*/0,
      GIR_EraseFromParent, /*InsnID*/0,
      // GIR_Coverage, 6656,
      GIR_Done,
    // Label 1932: @125872
    GIM_Try, /*On fail goto*//*Label 1933*/ GIMT_Encode4(125934), // Rule ID 3027 //
      GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasFlatGlobalInsts),
      GIM_CheckMemoryAddressSpace, /*MI*/0, /*MMO*/0, /*NumAddrSpace*/1, /*AddrSpace*/1,
      GIM_CheckAtomicOrdering, /*MI*/0, /*Order*/(uint8_t)AtomicOrdering::NotAtomic,
      GIM_CheckPointerToAny, /*MI*/0, /*Op*/1, /*SizeInBits*/0,
      GIM_CheckComplexPattern, /*MI*/0, /*Op*/1, /*Renderer*/GIMT_Encode2(0), GIMT_Encode2(GICP_gi_global_saddr),
      // (st p6:{ *:[i32] }:$data, (GlobalSAddr:{ *:[iPTR] } SReg_64:{ *:[i64] }:$saddr, VGPR_32:{ *:[i32] }:$voffset, i32:{ *:[i32] }:$offset))<<P:Predicate_unindexedstore>><<P:Predicate_store_global>>  =>  (GLOBAL_STORE_DWORD_SADDR ?:{ *:[i32] }:$voffset, anonymous_15037:{ *:[i32] }:$data, ?:{ *:[i64] }:$saddr, ?:{ *:[i32] }:$offset)
      GIR_BuildMI, /*InsnID*/0, /*Opcode*/GIMT_Encode2(AMDGPU::GLOBAL_STORE_DWORD_SADDR),
      GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/1, // voffset
      GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/0, // data
      GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/0, // saddr
      GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/2, // offset
      GIR_AddImm8, /*InsnID*/0, /*Imm*/0,
      GIR_MergeMemOperands, /*InsnID*/0, /*NumInsns*/1, /*MergeInsnID's*/0,
      GIR_ConstrainSelectedInstOperands, /*InsnID*/0,
      GIR_EraseFromParent, /*InsnID*/0,
      // GIR_Coverage, 3027,
      GIR_Done,
    // Label 1933: @125934
    GIM_Try, /*On fail goto*//*Label 1934*/ GIMT_Encode4(125991), // Rule ID 3026 //
      GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasFlatGlobalInsts),
      GIM_CheckMemoryAddressSpace, /*MI*/0, /*MMO*/0, /*NumAddrSpace*/1, /*AddrSpace*/1,
      GIM_CheckAtomicOrdering, /*MI*/0, /*Order*/(uint8_t)AtomicOrdering::NotAtomic,
      GIM_CheckPointerToAny, /*MI*/0, /*Op*/1, /*SizeInBits*/0,
      GIM_CheckComplexPattern, /*MI*/0, /*Op*/1, /*Renderer*/GIMT_Encode2(0), GIMT_Encode2(GICP_gi_global_offset),
      // (st p6:{ *:[i32] }:$data, (GlobalOffset:{ *:[iPTR] } i64:{ *:[i64] }:$vaddr, i32:{ *:[i32] }:$offset))<<P:Predicate_unindexedstore>><<P:Predicate_store_global>>  =>  (GLOBAL_STORE_DWORD ?:{ *:[i64] }:$vaddr, anonymous_15037:{ *:[i32] }:$data, ?:{ *:[i32] }:$offset)
      GIR_BuildMI, /*InsnID*/0, /*Opcode*/GIMT_Encode2(AMDGPU::GLOBAL_STORE_DWORD),
      GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/0, // vaddr
      GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/0, // data
      GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/1, // offset
      GIR_AddImm8, /*InsnID*/0, /*Imm*/0,
      GIR_MergeMemOperands, /*InsnID*/0, /*NumInsns*/1, /*MergeInsnID's*/0,
      GIR_ConstrainSelectedInstOperands, /*InsnID*/0,
      GIR_EraseFromParent, /*InsnID*/0,
      // GIR_Coverage, 3026,
      GIR_Done,
    // Label 1934: @125991
    GIM_Try, /*On fail goto*//*Label 1935*/ GIMT_Encode4(126049), // Rule ID 2787 //
      GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasFlatAddressSpace),
      GIM_CheckMemoryAddressSpace, /*MI*/0, /*MMO*/0, /*NumAddrSpace*/2, /*AddrSpace*/0, /*AddrSpace*/1,
      GIM_CheckAtomicOrdering, /*MI*/0, /*Order*/(uint8_t)AtomicOrdering::NotAtomic,
      GIM_CheckPointerToAny, /*MI*/0, /*Op*/1, /*SizeInBits*/0,
      GIM_CheckComplexPattern, /*MI*/0, /*Op*/1, /*Renderer*/GIMT_Encode2(0), GIMT_Encode2(GICP_gi_flat_offset),
      // (st p6:{ *:[i32] }:$data, (FlatOffset:{ *:[iPTR] } i64:{ *:[i64] }:$vaddr, i32:{ *:[i32] }:$offset))<<P:Predicate_unindexedstore>><<P:Predicate_store_flat>>  =>  (FLAT_STORE_DWORD ?:{ *:[i64] }:$vaddr, anonymous_15037:{ *:[i32] }:$data, ?:{ *:[i32] }:$offset)
      GIR_BuildMI, /*InsnID*/0, /*Opcode*/GIMT_Encode2(AMDGPU::FLAT_STORE_DWORD),
      GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/0, // vaddr
      GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/0, // data
      GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/1, // offset
      GIR_AddImm8, /*InsnID*/0, /*Imm*/0,
      GIR_MergeMemOperands, /*InsnID*/0, /*NumInsns*/1, /*MergeInsnID's*/0,
      GIR_ConstrainSelectedInstOperands, /*InsnID*/0,
      GIR_EraseFromParent, /*InsnID*/0,
      // GIR_Coverage, 2787,
      GIR_Done,
    // Label 1935: @126049
    GIM_Reject,
    // Label 1813: @126050
    GIM_Try, /*On fail goto*//*Label 1936*/ GIMT_Encode4(126126), // Rule ID 5506 //
      GIM_CheckFeatures, GIMT_Encode2(GIFBS_DisableFlatScratch_HasUnrestrictedSOffset),
      GIM_CheckMemorySizeLessThanLLT, /*MI*/0, /*MMO*/0, /*OpIdx*/0,
      GIM_CheckMemorySizeEqualTo, /*MI*/0, /*MMO*/0, /*Size*/GIMT_Encode4(1),
      GIM_CheckMemoryAddressSpace, /*MI*/0, /*MMO*/0, /*NumAddrSpace*/1, /*AddrSpace*/5,
      GIM_CheckAtomicOrdering, /*MI*/0, /*Order*/(uint8_t)AtomicOrdering::NotAtomic,
      GIM_CheckPointerToAny, /*MI*/0, /*Op*/1, /*SizeInBits*/0,
      GIM_CheckComplexPattern, /*MI*/0, /*Op*/1, /*Renderer*/GIMT_Encode2(0), GIMT_Encode2(GICP_gi_mubuf_scratch_offset),
      // (st i16:{ *:[i16] }:$value, (MUBUFScratchOffset:{ *:[iPTR] } v4i32:{ *:[v4i32] }:$srsrc, i32:{ *:[i32] }:$soffset, i32:{ *:[i32] }:$offset))<<P:Predicate_unindexedstore>><<P:Predicate_truncstore>><<P:Predicate_truncstorei8>><<P:Predicate_truncstorei8_private>>  =>  (BUFFER_STORE_BYTE_OFFSET VGPR_32:{ *:[i16] }:$value, ?:{ *:[v4i32] }:$srsrc, ?:{ *:[i32] }:$soffset, ?:{ *:[i32] }:$offset, 0:{ *:[i32] }, 0:{ *:[i1] })
      GIR_BuildMI, /*InsnID*/0, /*Opcode*/GIMT_Encode2(AMDGPU::BUFFER_STORE_BYTE_OFFSET),
      GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/0, // value
      GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/0, // srsrc
      GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/1, // soffset
      GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/2, // offset
      GIR_AddImm8, /*InsnID*/0, /*Imm*/0,
      GIR_AddImm8, /*InsnID*/0, /*Imm*/0,
      GIR_MergeMemOperands, /*InsnID*/0, /*NumInsns*/1, /*MergeInsnID's*/0,
      GIR_ConstrainSelectedInstOperands, /*InsnID*/0,
      GIR_EraseFromParent, /*InsnID*/0,
      // GIR_Coverage, 5506,
      GIR_Done,
    // Label 1936: @126126
    GIM_Try, /*On fail goto*//*Label 1937*/ GIMT_Encode4(126202), // Rule ID 5508 //
      GIM_CheckFeatures, GIMT_Encode2(GIFBS_DisableFlatScratch),
      GIM_CheckMemorySizeLessThanLLT, /*MI*/0, /*MMO*/0, /*OpIdx*/0,
      GIM_CheckMemorySizeEqualTo, /*MI*/0, /*MMO*/0, /*Size*/GIMT_Encode4(1),
      GIM_CheckMemoryAddressSpace, /*MI*/0, /*MMO*/0, /*NumAddrSpace*/1, /*AddrSpace*/5,
      GIM_CheckAtomicOrdering, /*MI*/0, /*Order*/(uint8_t)AtomicOrdering::NotAtomic,
      GIM_CheckPointerToAny, /*MI*/0, /*Op*/1, /*SizeInBits*/0,
      GIM_CheckComplexPattern, /*MI*/0, /*Op*/1, /*Renderer*/GIMT_Encode2(0), GIMT_Encode2(GICP_gi_mubuf_scratch_offset),
      // (st i16:{ *:[i16] }:$value, (MUBUFScratchOffset:{ *:[iPTR] } v4i32:{ *:[v4i32] }:$srsrc, i32:{ *:[i32] }:$soffset, i32:{ *:[i32] }:$offset))<<P:Predicate_unindexedstore>><<P:Predicate_truncstore>><<P:Predicate_truncstorei8>><<P:Predicate_truncstorei8_private>>  =>  (BUFFER_STORE_BYTE_VBUFFER_OFFSET VGPR_32:{ *:[i16] }:$value, ?:{ *:[v4i32] }:$srsrc, ?:{ *:[i32] }:$soffset, ?:{ *:[i32] }:$offset, 0:{ *:[i32] }, 0:{ *:[i1] })
      GIR_BuildMI, /*InsnID*/0, /*Opcode*/GIMT_Encode2(AMDGPU::BUFFER_STORE_BYTE_VBUFFER_OFFSET),
      GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/0, // value
      GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/0, // srsrc
      GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/1, // soffset
      GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/2, // offset
      GIR_AddImm8, /*InsnID*/0, /*Imm*/0,
      GIR_AddImm8, /*InsnID*/0, /*Imm*/0,
      GIR_MergeMemOperands, /*InsnID*/0, /*NumInsns*/1, /*MergeInsnID's*/0,
      GIR_ConstrainSelectedInstOperands, /*InsnID*/0,
      GIR_EraseFromParent, /*InsnID*/0,
      // GIR_Coverage, 5508,
      GIR_Done,
    // Label 1937: @126202
    GIM_Try, /*On fail goto*//*Label 1938*/ GIMT_Encode4(126267), // Rule ID 5510 //
      GIM_CheckFeatures, GIMT_Encode2(GIFBS_DisableFlatScratch_HasUnrestrictedSOffset),
      GIM_CheckMemoryAddressSpace, /*MI*/0, /*MMO*/0, /*NumAddrSpace*/1, /*AddrSpace*/5,
      GIM_CheckAtomicOrdering, /*MI*/0, /*Order*/(uint8_t)AtomicOrdering::NotAtomic,
      GIM_CheckPointerToAny, /*MI*/0, /*Op*/1, /*SizeInBits*/0,
      GIM_CheckComplexPattern, /*MI*/0, /*Op*/1, /*Renderer*/GIMT_Encode2(0), GIMT_Encode2(GICP_gi_mubuf_scratch_offset),
      // (st i16:{ *:[i16] }:$value, (MUBUFScratchOffset:{ *:[iPTR] } v4i32:{ *:[v4i32] }:$srsrc, i32:{ *:[i32] }:$soffset, i32:{ *:[i32] }:$offset))<<P:Predicate_unindexedstore>><<P:Predicate_store_private>>  =>  (BUFFER_STORE_SHORT_OFFSET VGPR_32:{ *:[i16] }:$value, ?:{ *:[v4i32] }:$srsrc, ?:{ *:[i32] }:$soffset, ?:{ *:[i32] }:$offset, 0:{ *:[i32] }, 0:{ *:[i1] })
      GIR_BuildMI, /*InsnID*/0, /*Opcode*/GIMT_Encode2(AMDGPU::BUFFER_STORE_SHORT_OFFSET),
      GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/0, // value
      GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/0, // srsrc
      GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/1, // soffset
      GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/2, // offset
      GIR_AddImm8, /*InsnID*/0, /*Imm*/0,
      GIR_AddImm8, /*InsnID*/0, /*Imm*/0,
      GIR_MergeMemOperands, /*InsnID*/0, /*NumInsns*/1, /*MergeInsnID's*/0,
      GIR_ConstrainSelectedInstOperands, /*InsnID*/0,
      GIR_EraseFromParent, /*InsnID*/0,
      // GIR_Coverage, 5510,
      GIR_Done,
    // Label 1938: @126267
    GIM_Try, /*On fail goto*//*Label 1939*/ GIMT_Encode4(126332), // Rule ID 5512 //
      GIM_CheckFeatures, GIMT_Encode2(GIFBS_DisableFlatScratch),
      GIM_CheckMemoryAddressSpace, /*MI*/0, /*MMO*/0, /*NumAddrSpace*/1, /*AddrSpace*/5,
      GIM_CheckAtomicOrdering, /*MI*/0, /*Order*/(uint8_t)AtomicOrdering::NotAtomic,
      GIM_CheckPointerToAny, /*MI*/0, /*Op*/1, /*SizeInBits*/0,
      GIM_CheckComplexPattern, /*MI*/0, /*Op*/1, /*Renderer*/GIMT_Encode2(0), GIMT_Encode2(GICP_gi_mubuf_scratch_offset),
      // (st i16:{ *:[i16] }:$value, (MUBUFScratchOffset:{ *:[iPTR] } v4i32:{ *:[v4i32] }:$srsrc, i32:{ *:[i32] }:$soffset, i32:{ *:[i32] }:$offset))<<P:Predicate_unindexedstore>><<P:Predicate_store_private>>  =>  (BUFFER_STORE_SHORT_VBUFFER_OFFSET VGPR_32:{ *:[i16] }:$value, ?:{ *:[v4i32] }:$srsrc, ?:{ *:[i32] }:$soffset, ?:{ *:[i32] }:$offset, 0:{ *:[i32] }, 0:{ *:[i1] })
      GIR_BuildMI, /*InsnID*/0, /*Opcode*/GIMT_Encode2(AMDGPU::BUFFER_STORE_SHORT_VBUFFER_OFFSET),
      GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/0, // value
      GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/0, // srsrc
      GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/1, // soffset
      GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/2, // offset
      GIR_AddImm8, /*InsnID*/0, /*Imm*/0,
      GIR_AddImm8, /*InsnID*/0, /*Imm*/0,
      GIR_MergeMemOperands, /*InsnID*/0, /*NumInsns*/1, /*MergeInsnID's*/0,
      GIR_ConstrainSelectedInstOperands, /*InsnID*/0,
      GIR_EraseFromParent, /*InsnID*/0,
      // GIR_Coverage, 5512,
      GIR_Done,
    // Label 1939: @126332
    GIM_Try, /*On fail goto*//*Label 1940*/ GIMT_Encode4(126405), // Rule ID 3592 //
      GIM_CheckFeatures, GIMT_Encode2(GIFBS_EnableFlatScratch_HasFlatScratchInsts_HasFlatScratchSVSMode),
      GIM_CheckMemorySizeLessThanLLT, /*MI*/0, /*MMO*/0, /*OpIdx*/0,
      GIM_CheckMemorySizeEqualTo, /*MI*/0, /*MMO*/0, /*Size*/GIMT_Encode4(1),
      GIM_CheckMemoryAddressSpace, /*MI*/0, /*MMO*/0, /*NumAddrSpace*/1, /*AddrSpace*/5,
      GIM_CheckAtomicOrdering, /*MI*/0, /*Order*/(uint8_t)AtomicOrdering::NotAtomic,
      GIM_CheckPointerToAny, /*MI*/0, /*Op*/1, /*SizeInBits*/0,
      GIM_CheckComplexPattern, /*MI*/0, /*Op*/1, /*Renderer*/GIMT_Encode2(0), GIMT_Encode2(GICP_gi_flat_scratch_svaddr),
      // (st i16:{ *:[i16] }:$data, (ScratchSVAddr:{ *:[iPTR] } VGPR_32:{ *:[i32] }:$vaddr, SGPR_32:{ *:[i32] }:$saddr, i32:{ *:[i32] }:$offset))<<P:Predicate_unindexedstore>><<P:Predicate_truncstore>><<P:Predicate_truncstorei8>><<P:Predicate_truncstorei8_private>>  =>  (SCRATCH_STORE_BYTE_SVS anonymous_15037:{ *:[i16] }:$data, ?:{ *:[i32] }:$vaddr, ?:{ *:[i32] }:$saddr, ?:{ *:[i32] }:$offset)
      GIR_BuildMI, /*InsnID*/0, /*Opcode*/GIMT_Encode2(AMDGPU::SCRATCH_STORE_BYTE_SVS),
      GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/0, // data
      GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/0, // vaddr
      GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/1, // saddr
      GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/2, // offset
      GIR_AddImm8, /*InsnID*/0, /*Imm*/0,
      GIR_MergeMemOperands, /*InsnID*/0, /*NumInsns*/1, /*MergeInsnID's*/0,
      GIR_ConstrainSelectedInstOperands, /*InsnID*/0,
      GIR_EraseFromParent, /*InsnID*/0,
      // GIR_Coverage, 3592,
      GIR_Done,
    // Label 1940: @126405
    GIM_Try, /*On fail goto*//*Label 1941*/ GIMT_Encode4(126467), // Rule ID 3598 //
      GIM_CheckFeatures, GIMT_Encode2(GIFBS_EnableFlatScratch_HasFlatScratchInsts_HasFlatScratchSVSMode),
      GIM_CheckMemoryAddressSpace, /*MI*/0, /*MMO*/0, /*NumAddrSpace*/1, /*AddrSpace*/5,
      GIM_CheckAtomicOrdering, /*MI*/0, /*Order*/(uint8_t)AtomicOrdering::NotAtomic,
      GIM_CheckPointerToAny, /*MI*/0, /*Op*/1, /*SizeInBits*/0,
      GIM_CheckComplexPattern, /*MI*/0, /*Op*/1, /*Renderer*/GIMT_Encode2(0), GIMT_Encode2(GICP_gi_flat_scratch_svaddr),
      // (st i16:{ *:[i16] }:$data, (ScratchSVAddr:{ *:[iPTR] } VGPR_32:{ *:[i32] }:$vaddr, SGPR_32:{ *:[i32] }:$saddr, i32:{ *:[i32] }:$offset))<<P:Predicate_unindexedstore>><<P:Predicate_store_private>>  =>  (SCRATCH_STORE_SHORT_SVS anonymous_15037:{ *:[i16] }:$data, ?:{ *:[i32] }:$vaddr, ?:{ *:[i32] }:$saddr, ?:{ *:[i32] }:$offset)
      GIR_BuildMI, /*InsnID*/0, /*Opcode*/GIMT_Encode2(AMDGPU::SCRATCH_STORE_SHORT_SVS),
      GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/0, // data
      GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/0, // vaddr
      GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/1, // saddr
      GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/2, // offset
      GIR_AddImm8, /*InsnID*/0, /*Imm*/0,
      GIR_MergeMemOperands, /*InsnID*/0, /*NumInsns*/1, /*MergeInsnID's*/0,
      GIR_ConstrainSelectedInstOperands, /*InsnID*/0,
      GIR_EraseFromParent, /*InsnID*/0,
      // GIR_Coverage, 3598,
      GIR_Done,
    // Label 1941: @126467
    GIM_Try, /*On fail goto*//*Label 1942*/ GIMT_Encode4(126535), // Rule ID 3591 //
      GIM_CheckFeatures, GIMT_Encode2(GIFBS_EnableFlatScratch_HasFlatScratchInsts),
      GIM_CheckMemorySizeLessThanLLT, /*MI*/0, /*MMO*/0, /*OpIdx*/0,
      GIM_CheckMemorySizeEqualTo, /*MI*/0, /*MMO*/0, /*Size*/GIMT_Encode4(1),
      GIM_CheckMemoryAddressSpace, /*MI*/0, /*MMO*/0, /*NumAddrSpace*/1, /*AddrSpace*/5,
      GIM_CheckAtomicOrdering, /*MI*/0, /*Order*/(uint8_t)AtomicOrdering::NotAtomic,
      GIM_CheckPointerToAny, /*MI*/0, /*Op*/1, /*SizeInBits*/0,
      GIM_CheckComplexPattern, /*MI*/0, /*Op*/1, /*Renderer*/GIMT_Encode2(0), GIMT_Encode2(GICP_gi_flat_scratch_saddr),
      // (st i16:{ *:[i16] }:$data, (ScratchSAddr:{ *:[iPTR] } SGPR_32:{ *:[i32] }:$saddr, i32:{ *:[i32] }:$offset))<<P:Predicate_unindexedstore>><<P:Predicate_truncstore>><<P:Predicate_truncstorei8>><<P:Predicate_truncstorei8_private>>  =>  (SCRATCH_STORE_BYTE_SADDR anonymous_15037:{ *:[i16] }:$data, ?:{ *:[i32] }:$saddr, ?:{ *:[i32] }:$offset)
      GIR_BuildMI, /*InsnID*/0, /*Opcode*/GIMT_Encode2(AMDGPU::SCRATCH_STORE_BYTE_SADDR),
      GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/0, // data
      GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/0, // saddr
      GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/1, // offset
      GIR_AddImm8, /*InsnID*/0, /*Imm*/0,
      GIR_MergeMemOperands, /*InsnID*/0, /*NumInsns*/1, /*MergeInsnID's*/0,
      GIR_ConstrainSelectedInstOperands, /*InsnID*/0,
      GIR_EraseFromParent, /*InsnID*/0,
      // GIR_Coverage, 3591,
      GIR_Done,
    // Label 1942: @126535
    GIM_Try, /*On fail goto*//*Label 1943*/ GIMT_Encode4(126592), // Rule ID 3597 //
      GIM_CheckFeatures, GIMT_Encode2(GIFBS_EnableFlatScratch_HasFlatScratchInsts),
      GIM_CheckMemoryAddressSpace, /*MI*/0, /*MMO*/0, /*NumAddrSpace*/1, /*AddrSpace*/5,
      GIM_CheckAtomicOrdering, /*MI*/0, /*Order*/(uint8_t)AtomicOrdering::NotAtomic,
      GIM_CheckPointerToAny, /*MI*/0, /*Op*/1, /*SizeInBits*/0,
      GIM_CheckComplexPattern, /*MI*/0, /*Op*/1, /*Renderer*/GIMT_Encode2(0), GIMT_Encode2(GICP_gi_flat_scratch_saddr),
      // (st i16:{ *:[i16] }:$data, (ScratchSAddr:{ *:[iPTR] } SGPR_32:{ *:[i32] }:$saddr, i32:{ *:[i32] }:$offset))<<P:Predicate_unindexedstore>><<P:Predicate_store_private>>  =>  (SCRATCH_STORE_SHORT_SADDR anonymous_15037:{ *:[i16] }:$data, ?:{ *:[i32] }:$saddr, ?:{ *:[i32] }:$offset)
      GIR_BuildMI, /*InsnID*/0, /*Opcode*/GIMT_Encode2(AMDGPU::SCRATCH_STORE_SHORT_SADDR),
      GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/0, // data
      GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/0, // saddr
      GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/1, // offset
      GIR_AddImm8, /*InsnID*/0, /*Imm*/0,
      GIR_MergeMemOperands, /*InsnID*/0, /*NumInsns*/1, /*MergeInsnID's*/0,
      GIR_ConstrainSelectedInstOperands, /*InsnID*/0,
      GIR_EraseFromParent, /*InsnID*/0,
      // GIR_Coverage, 3597,
      GIR_Done,
    // Label 1943: @126592
    GIM_Try, /*On fail goto*//*Label 1944*/ GIMT_Encode4(126660), // Rule ID 3590 //
      GIM_CheckFeatures, GIMT_Encode2(GIFBS_EnableFlatScratch_HasFlatScratchInsts),
      GIM_CheckMemorySizeLessThanLLT, /*MI*/0, /*MMO*/0, /*OpIdx*/0,
      GIM_CheckMemorySizeEqualTo, /*MI*/0, /*MMO*/0, /*Size*/GIMT_Encode4(1),
      GIM_CheckMemoryAddressSpace, /*MI*/0, /*MMO*/0, /*NumAddrSpace*/1, /*AddrSpace*/5,
      GIM_CheckAtomicOrdering, /*MI*/0, /*Order*/(uint8_t)AtomicOrdering::NotAtomic,
      GIM_CheckPointerToAny, /*MI*/0, /*Op*/1, /*SizeInBits*/0,
      GIM_CheckComplexPattern, /*MI*/0, /*Op*/1, /*Renderer*/GIMT_Encode2(0), GIMT_Encode2(GICP_gi_flat_scratch_offset),
      // (st i16:{ *:[i16] }:$data, (ScratchOffset:{ *:[iPTR] } VGPR_32:{ *:[i32] }:$vaddr, i32:{ *:[i32] }:$offset))<<P:Predicate_unindexedstore>><<P:Predicate_truncstore>><<P:Predicate_truncstorei8>><<P:Predicate_truncstorei8_private>>  =>  (SCRATCH_STORE_BYTE anonymous_15037:{ *:[i16] }:$data, ?:{ *:[i32] }:$vaddr, ?:{ *:[i32] }:$offset)
      GIR_BuildMI, /*InsnID*/0, /*Opcode*/GIMT_Encode2(AMDGPU::SCRATCH_STORE_BYTE),
      GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/0, // data
      GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/0, // vaddr
      GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/1, // offset
      GIR_AddImm8, /*InsnID*/0, /*Imm*/0,
      GIR_MergeMemOperands, /*InsnID*/0, /*NumInsns*/1, /*MergeInsnID's*/0,
      GIR_ConstrainSelectedInstOperands, /*InsnID*/0,
      GIR_EraseFromParent, /*InsnID*/0,
      // GIR_Coverage, 3590,
      GIR_Done,
    // Label 1944: @126660
    GIM_Try, /*On fail goto*//*Label 1945*/ GIMT_Encode4(126717), // Rule ID 3596 //
      GIM_CheckFeatures, GIMT_Encode2(GIFBS_EnableFlatScratch_HasFlatScratchInsts),
      GIM_CheckMemoryAddressSpace, /*MI*/0, /*MMO*/0, /*NumAddrSpace*/1, /*AddrSpace*/5,
      GIM_CheckAtomicOrdering, /*MI*/0, /*Order*/(uint8_t)AtomicOrdering::NotAtomic,
      GIM_CheckPointerToAny, /*MI*/0, /*Op*/1, /*SizeInBits*/0,
      GIM_CheckComplexPattern, /*MI*/0, /*Op*/1, /*Renderer*/GIMT_Encode2(0), GIMT_Encode2(GICP_gi_flat_scratch_offset),
      // (st i16:{ *:[i16] }:$data, (ScratchOffset:{ *:[iPTR] } VGPR_32:{ *:[i32] }:$vaddr, i32:{ *:[i32] }:$offset))<<P:Predicate_unindexedstore>><<P:Predicate_store_private>>  =>  (SCRATCH_STORE_SHORT anonymous_15037:{ *:[i16] }:$data, ?:{ *:[i32] }:$vaddr, ?:{ *:[i32] }:$offset)
      GIR_BuildMI, /*InsnID*/0, /*Opcode*/GIMT_Encode2(AMDGPU::SCRATCH_STORE_SHORT),
      GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/0, // data
      GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/0, // vaddr
      GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/1, // offset
      GIR_AddImm8, /*InsnID*/0, /*Imm*/0,
      GIR_MergeMemOperands, /*InsnID*/0, /*NumInsns*/1, /*MergeInsnID's*/0,
      GIR_ConstrainSelectedInstOperands, /*InsnID*/0,
      GIR_EraseFromParent, /*InsnID*/0,
      // GIR_Coverage, 3596,
      GIR_Done,
    // Label 1945: @126717
    GIM_Try, /*On fail goto*//*Label 1946*/ GIMT_Encode4(126794), // Rule ID 5483 //
      GIM_CheckFeatures, GIMT_Encode2(GIFBS_isGFX6GFX7),
      GIM_CheckMemorySizeEqualTo, /*MI*/0, /*MMO*/0, /*Size*/GIMT_Encode4(1),
      GIM_CheckMemoryAddressSpace, /*MI*/0, /*MMO*/0, /*NumAddrSpace*/1, /*AddrSpace*/1,
      GIM_CheckAtomicOrderingOrStrongerThan, /*MI*/0, /*Order*/(uint8_t)AtomicOrdering::Unordered,
      GIM_CheckPointerToAny, /*MI*/0, /*Op*/1, /*SizeInBits*/0,
      GIM_CheckComplexPattern, /*MI*/0, /*Op*/1, /*Renderer*/GIMT_Encode2(0), GIMT_Encode2(GICP_gi_mubuf_addr64),
      // (atomic_store i16:{ *:[i16] }:$val, (MUBUFAddr64:{ *:[iPTR] } v4i32:{ *:[v4i32] }:$srsrc, i64:{ *:[i64] }:$vaddr, i32:{ *:[i32] }:$soffset, i32:{ *:[i32] }:$offset))<<P:Predicate_atomic_store_8>><<P:Predicate_atomic_store_8_global>>  =>  (BUFFER_STORE_BYTE_ADDR64 ?:{ *:[i16] }:$val, ?:{ *:[i64] }:$vaddr, ?:{ *:[v4i32] }:$srsrc, ?:{ *:[i32] }:$soffset, ?:{ *:[i32] }:$offset)
      GIR_BuildMI, /*InsnID*/0, /*Opcode*/GIMT_Encode2(AMDGPU::BUFFER_STORE_BYTE_ADDR64),
      GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/0, // val
      GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/1, // vaddr
      GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/0, // srsrc
      GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/2, // soffset
      GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/3, // offset
      GIR_AddImm8, /*InsnID*/0, /*Imm*/0,
      GIR_AddImm8, /*InsnID*/0, /*Imm*/0,
      GIR_MergeMemOperands, /*InsnID*/0, /*NumInsns*/1, /*MergeInsnID's*/0,
      GIR_ConstrainSelectedInstOperands, /*InsnID*/0,
      GIR_EraseFromParent, /*InsnID*/0,
      // GIR_Coverage, 5483,
      GIR_Done,
    // Label 1946: @126794
    GIM_Try, /*On fail goto*//*Label 1947*/ GIMT_Encode4(126871), // Rule ID 5487 //
      GIM_CheckFeatures, GIMT_Encode2(GIFBS_isGFX6GFX7),
      GIM_CheckMemorySizeEqualTo, /*MI*/0, /*MMO*/0, /*Size*/GIMT_Encode4(2),
      GIM_CheckMemoryAddressSpace, /*MI*/0, /*MMO*/0, /*NumAddrSpace*/1, /*AddrSpace*/1,
      GIM_CheckAtomicOrderingOrStrongerThan, /*MI*/0, /*Order*/(uint8_t)AtomicOrdering::Unordered,
      GIM_CheckPointerToAny, /*MI*/0, /*Op*/1, /*SizeInBits*/0,
      GIM_CheckComplexPattern, /*MI*/0, /*Op*/1, /*Renderer*/GIMT_Encode2(0), GIMT_Encode2(GICP_gi_mubuf_addr64),
      // (atomic_store i16:{ *:[i16] }:$val, (MUBUFAddr64:{ *:[iPTR] } v4i32:{ *:[v4i32] }:$srsrc, i64:{ *:[i64] }:$vaddr, i32:{ *:[i32] }:$soffset, i32:{ *:[i32] }:$offset))<<P:Predicate_atomic_store_16>><<P:Predicate_atomic_store_16_global>>  =>  (BUFFER_STORE_SHORT_ADDR64 ?:{ *:[i16] }:$val, ?:{ *:[i64] }:$vaddr, ?:{ *:[v4i32] }:$srsrc, ?:{ *:[i32] }:$soffset, ?:{ *:[i32] }:$offset)
      GIR_BuildMI, /*InsnID*/0, /*Opcode*/GIMT_Encode2(AMDGPU::BUFFER_STORE_SHORT_ADDR64),
      GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/0, // val
      GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/1, // vaddr
      GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/0, // srsrc
      GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/2, // soffset
      GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/3, // offset
      GIR_AddImm8, /*InsnID*/0, /*Imm*/0,
      GIR_AddImm8, /*InsnID*/0, /*Imm*/0,
      GIR_MergeMemOperands, /*InsnID*/0, /*NumInsns*/1, /*MergeInsnID's*/0,
      GIR_ConstrainSelectedInstOperands, /*InsnID*/0,
      GIR_EraseFromParent, /*InsnID*/0,
      // GIR_Coverage, 5487,
      GIR_Done,
    // Label 1947: @126871
    GIM_Try, /*On fail goto*//*Label 1948*/ GIMT_Encode4(126952), // Rule ID 5505 //
      GIM_CheckFeatures, GIMT_Encode2(GIFBS_DisableFlatScratch_HasUnrestrictedSOffset),
      GIM_CheckMemorySizeLessThanLLT, /*MI*/0, /*MMO*/0, /*OpIdx*/0,
      GIM_CheckMemorySizeEqualTo, /*MI*/0, /*MMO*/0, /*Size*/GIMT_Encode4(1),
      GIM_CheckMemoryAddressSpace, /*MI*/0, /*MMO*/0, /*NumAddrSpace*/1, /*AddrSpace*/5,
      GIM_CheckAtomicOrdering, /*MI*/0, /*Order*/(uint8_t)AtomicOrdering::NotAtomic,
      GIM_CheckPointerToAny, /*MI*/0, /*Op*/1, /*SizeInBits*/0,
      GIM_CheckComplexPattern, /*MI*/0, /*Op*/1, /*Renderer*/GIMT_Encode2(0), GIMT_Encode2(GICP_gi_mubuf_scratch_offen),
      // (st i16:{ *:[i16] }:$value, (MUBUFScratchOffen:{ *:[iPTR] } v4i32:{ *:[v4i32] }:$srsrc, i32:{ *:[i32] }:$vaddr, i32:{ *:[i32] }:$soffset, i32:{ *:[i32] }:$offset))<<P:Predicate_unindexedstore>><<P:Predicate_truncstore>><<P:Predicate_truncstorei8>><<P:Predicate_truncstorei8_private>>  =>  (BUFFER_STORE_BYTE_OFFEN VGPR_32:{ *:[i16] }:$value, ?:{ *:[i32] }:$vaddr, ?:{ *:[v4i32] }:$srsrc, ?:{ *:[i32] }:$soffset, ?:{ *:[i32] }:$offset, 0:{ *:[i32] }, 0:{ *:[i1] })
      GIR_BuildMI, /*InsnID*/0, /*Opcode*/GIMT_Encode2(AMDGPU::BUFFER_STORE_BYTE_OFFEN),
      GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/0, // value
      GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/1, // vaddr
      GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/0, // srsrc
      GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/2, // soffset
      GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/3, // offset
      GIR_AddImm8, /*InsnID*/0, /*Imm*/0,
      GIR_AddImm8, /*InsnID*/0, /*Imm*/0,
      GIR_MergeMemOperands, /*InsnID*/0, /*NumInsns*/1, /*MergeInsnID's*/0,
      GIR_ConstrainSelectedInstOperands, /*InsnID*/0,
      GIR_EraseFromParent, /*InsnID*/0,
      // GIR_Coverage, 5505,
      GIR_Done,
    // Label 1948: @126952
    GIM_Try, /*On fail goto*//*Label 1949*/ GIMT_Encode4(127033), // Rule ID 5507 //
      GIM_CheckFeatures, GIMT_Encode2(GIFBS_DisableFlatScratch),
      GIM_CheckMemorySizeLessThanLLT, /*MI*/0, /*MMO*/0, /*OpIdx*/0,
      GIM_CheckMemorySizeEqualTo, /*MI*/0, /*MMO*/0, /*Size*/GIMT_Encode4(1),
      GIM_CheckMemoryAddressSpace, /*MI*/0, /*MMO*/0, /*NumAddrSpace*/1, /*AddrSpace*/5,
      GIM_CheckAtomicOrdering, /*MI*/0, /*Order*/(uint8_t)AtomicOrdering::NotAtomic,
      GIM_CheckPointerToAny, /*MI*/0, /*Op*/1, /*SizeInBits*/0,
      GIM_CheckComplexPattern, /*MI*/0, /*Op*/1, /*Renderer*/GIMT_Encode2(0), GIMT_Encode2(GICP_gi_mubuf_scratch_offen),
      // (st i16:{ *:[i16] }:$value, (MUBUFScratchOffen:{ *:[iPTR] } v4i32:{ *:[v4i32] }:$srsrc, i32:{ *:[i32] }:$vaddr, i32:{ *:[i32] }:$soffset, i32:{ *:[i32] }:$offset))<<P:Predicate_unindexedstore>><<P:Predicate_truncstore>><<P:Predicate_truncstorei8>><<P:Predicate_truncstorei8_private>>  =>  (BUFFER_STORE_BYTE_VBUFFER_OFFEN VGPR_32:{ *:[i16] }:$value, ?:{ *:[i32] }:$vaddr, ?:{ *:[v4i32] }:$srsrc, ?:{ *:[i32] }:$soffset, ?:{ *:[i32] }:$offset, 0:{ *:[i32] }, 0:{ *:[i1] })
      GIR_BuildMI, /*InsnID*/0, /*Opcode*/GIMT_Encode2(AMDGPU::BUFFER_STORE_BYTE_VBUFFER_OFFEN),
      GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/0, // value
      GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/1, // vaddr
      GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/0, // srsrc
      GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/2, // soffset
      GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/3, // offset
      GIR_AddImm8, /*InsnID*/0, /*Imm*/0,
      GIR_AddImm8, /*InsnID*/0, /*Imm*/0,
      GIR_MergeMemOperands, /*InsnID*/0, /*NumInsns*/1, /*MergeInsnID's*/0,
      GIR_ConstrainSelectedInstOperands, /*InsnID*/0,
      GIR_EraseFromParent, /*InsnID*/0,
      // GIR_Coverage, 5507,
      GIR_Done,
    // Label 1949: @127033
    GIM_Try, /*On fail goto*//*Label 1950*/ GIMT_Encode4(127103), // Rule ID 5509 //
      GIM_CheckFeatures, GIMT_Encode2(GIFBS_DisableFlatScratch_HasUnrestrictedSOffset),
      GIM_CheckMemoryAddressSpace, /*MI*/0, /*MMO*/0, /*NumAddrSpace*/1, /*AddrSpace*/5,
      GIM_CheckAtomicOrdering, /*MI*/0, /*Order*/(uint8_t)AtomicOrdering::NotAtomic,
      GIM_CheckPointerToAny, /*MI*/0, /*Op*/1, /*SizeInBits*/0,
      GIM_CheckComplexPattern, /*MI*/0, /*Op*/1, /*Renderer*/GIMT_Encode2(0), GIMT_Encode2(GICP_gi_mubuf_scratch_offen),
      // (st i16:{ *:[i16] }:$value, (MUBUFScratchOffen:{ *:[iPTR] } v4i32:{ *:[v4i32] }:$srsrc, i32:{ *:[i32] }:$vaddr, i32:{ *:[i32] }:$soffset, i32:{ *:[i32] }:$offset))<<P:Predicate_unindexedstore>><<P:Predicate_store_private>>  =>  (BUFFER_STORE_SHORT_OFFEN VGPR_32:{ *:[i16] }:$value, ?:{ *:[i32] }:$vaddr, ?:{ *:[v4i32] }:$srsrc, ?:{ *:[i32] }:$soffset, ?:{ *:[i32] }:$offset, 0:{ *:[i32] }, 0:{ *:[i1] })
      GIR_BuildMI, /*InsnID*/0, /*Opcode*/GIMT_Encode2(AMDGPU::BUFFER_STORE_SHORT_OFFEN),
      GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/0, // value
      GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/1, // vaddr
      GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/0, // srsrc
      GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/2, // soffset
      GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/3, // offset
      GIR_AddImm8, /*InsnID*/0, /*Imm*/0,
      GIR_AddImm8, /*InsnID*/0, /*Imm*/0,
      GIR_MergeMemOperands, /*InsnID*/0, /*NumInsns*/1, /*MergeInsnID's*/0,
      GIR_ConstrainSelectedInstOperands, /*InsnID*/0,
      GIR_EraseFromParent, /*InsnID*/0,
      // GIR_Coverage, 5509,
      GIR_Done,
    // Label 1950: @127103
    GIM_Try, /*On fail goto*//*Label 1951*/ GIMT_Encode4(127173), // Rule ID 5511 //
      GIM_CheckFeatures, GIMT_Encode2(GIFBS_DisableFlatScratch),
      GIM_CheckMemoryAddressSpace, /*MI*/0, /*MMO*/0, /*NumAddrSpace*/1, /*AddrSpace*/5,
      GIM_CheckAtomicOrdering, /*MI*/0, /*Order*/(uint8_t)AtomicOrdering::NotAtomic,
      GIM_CheckPointerToAny, /*MI*/0, /*Op*/1, /*SizeInBits*/0,
      GIM_CheckComplexPattern, /*MI*/0, /*Op*/1, /*Renderer*/GIMT_Encode2(0), GIMT_Encode2(GICP_gi_mubuf_scratch_offen),
      // (st i16:{ *:[i16] }:$value, (MUBUFScratchOffen:{ *:[iPTR] } v4i32:{ *:[v4i32] }:$srsrc, i32:{ *:[i32] }:$vaddr, i32:{ *:[i32] }:$soffset, i32:{ *:[i32] }:$offset))<<P:Predicate_unindexedstore>><<P:Predicate_store_private>>  =>  (BUFFER_STORE_SHORT_VBUFFER_OFFEN VGPR_32:{ *:[i16] }:$value, ?:{ *:[i32] }:$vaddr, ?:{ *:[v4i32] }:$srsrc, ?:{ *:[i32] }:$soffset, ?:{ *:[i32] }:$offset, 0:{ *:[i32] }, 0:{ *:[i1] })
      GIR_BuildMI, /*InsnID*/0, /*Opcode*/GIMT_Encode2(AMDGPU::BUFFER_STORE_SHORT_VBUFFER_OFFEN),
      GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/0, // value
      GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/1, // vaddr
      GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/0, // srsrc
      GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/2, // soffset
      GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/3, // offset
      GIR_AddImm8, /*InsnID*/0, /*Imm*/0,
      GIR_AddImm8, /*InsnID*/0, /*Imm*/0,
      GIR_MergeMemOperands, /*InsnID*/0, /*NumInsns*/1, /*MergeInsnID's*/0,
      GIR_ConstrainSelectedInstOperands, /*InsnID*/0,
      GIR_EraseFromParent, /*InsnID*/0,
      // GIR_Coverage, 5511,
      GIR_Done,
    // Label 1951: @127173
    GIM_Try, /*On fail goto*//*Label 1952*/ GIMT_Encode4(127249), // Rule ID 5493 //
      GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasUnrestrictedSOffset),
      GIM_CheckMemorySizeLessThanLLT, /*MI*/0, /*MMO*/0, /*OpIdx*/0,
      GIM_CheckMemorySizeEqualTo, /*MI*/0, /*MMO*/0, /*Size*/GIMT_Encode4(1),
      GIM_CheckMemoryAddressSpace, /*MI*/0, /*MMO*/0, /*NumAddrSpace*/1, /*AddrSpace*/1,
      GIM_CheckAtomicOrdering, /*MI*/0, /*Order*/(uint8_t)AtomicOrdering::NotAtomic,
      GIM_CheckPointerToAny, /*MI*/0, /*Op*/1, /*SizeInBits*/0,
      GIM_CheckComplexPattern, /*MI*/0, /*Op*/1, /*Renderer*/GIMT_Encode2(0), GIMT_Encode2(GICP_gi_mubuf_offset),
      // (st i16:{ *:[i16] }:$vdata, (MUBUFOffset:{ *:[iPTR] } v4i32:{ *:[v4i32] }:$srsrc, i32:{ *:[i32] }:$soffset, i32:{ *:[i32] }:$offset))<<P:Predicate_unindexedstore>><<P:Predicate_truncstore>><<P:Predicate_truncstorei8>><<P:Predicate_truncstorei8_global>>  =>  (BUFFER_STORE_BYTE_OFFSET ?:{ *:[i16] }:$vdata, ?:{ *:[v4i32] }:$srsrc, ?:{ *:[i32] }:$soffset, ?:{ *:[i32] }:$offset)
      GIR_BuildMI, /*InsnID*/0, /*Opcode*/GIMT_Encode2(AMDGPU::BUFFER_STORE_BYTE_OFFSET),
      GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/0, // vdata
      GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/0, // srsrc
      GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/1, // soffset
      GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/2, // offset
      GIR_AddImm8, /*InsnID*/0, /*Imm*/0,
      GIR_AddImm8, /*InsnID*/0, /*Imm*/0,
      GIR_MergeMemOperands, /*InsnID*/0, /*NumInsns*/1, /*MergeInsnID's*/0,
      GIR_ConstrainSelectedInstOperands, /*InsnID*/0,
      GIR_EraseFromParent, /*InsnID*/0,
      // GIR_Coverage, 5493,
      GIR_Done,
    // Label 1952: @127249
    GIM_Try, /*On fail goto*//*Label 1953*/ GIMT_Encode4(127322), // Rule ID 5494 //
      GIM_CheckMemorySizeLessThanLLT, /*MI*/0, /*MMO*/0, /*OpIdx*/0,
      GIM_CheckMemorySizeEqualTo, /*MI*/0, /*MMO*/0, /*Size*/GIMT_Encode4(1),
      GIM_CheckMemoryAddressSpace, /*MI*/0, /*MMO*/0, /*NumAddrSpace*/1, /*AddrSpace*/1,
      GIM_CheckAtomicOrdering, /*MI*/0, /*Order*/(uint8_t)AtomicOrdering::NotAtomic,
      GIM_CheckPointerToAny, /*MI*/0, /*Op*/1, /*SizeInBits*/0,
      GIM_CheckComplexPattern, /*MI*/0, /*Op*/1, /*Renderer*/GIMT_Encode2(0), GIMT_Encode2(GICP_gi_mubuf_offset),
      // (st i16:{ *:[i16] }:$vdata, (MUBUFOffset:{ *:[iPTR] } v4i32:{ *:[v4i32] }:$srsrc, i32:{ *:[i32] }:$soffset, i32:{ *:[i32] }:$offset))<<P:Predicate_unindexedstore>><<P:Predicate_truncstore>><<P:Predicate_truncstorei8>><<P:Predicate_truncstorei8_global>>  =>  (BUFFER_STORE_BYTE_VBUFFER_OFFSET ?:{ *:[i16] }:$vdata, ?:{ *:[v4i32] }:$srsrc, ?:{ *:[i32] }:$soffset, ?:{ *:[i32] }:$offset)
      GIR_BuildMI, /*InsnID*/0, /*Opcode*/GIMT_Encode2(AMDGPU::BUFFER_STORE_BYTE_VBUFFER_OFFSET),
      GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/0, // vdata
      GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/0, // srsrc
      GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/1, // soffset
      GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/2, // offset
      GIR_AddImm8, /*InsnID*/0, /*Imm*/0,
      GIR_AddImm8, /*InsnID*/0, /*Imm*/0,
      GIR_MergeMemOperands, /*InsnID*/0, /*NumInsns*/1, /*MergeInsnID's*/0,
      GIR_ConstrainSelectedInstOperands, /*InsnID*/0,
      GIR_EraseFromParent, /*InsnID*/0,
      // GIR_Coverage, 5494,
      GIR_Done,
    // Label 1953: @127322
    GIM_Try, /*On fail goto*//*Label 1954*/ GIMT_Encode4(127387), // Rule ID 5495 //
      GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasUnrestrictedSOffset),
      GIM_CheckMemoryAddressSpace, /*MI*/0, /*MMO*/0, /*NumAddrSpace*/1, /*AddrSpace*/1,
      GIM_CheckAtomicOrdering, /*MI*/0, /*Order*/(uint8_t)AtomicOrdering::NotAtomic,
      GIM_CheckPointerToAny, /*MI*/0, /*Op*/1, /*SizeInBits*/0,
      GIM_CheckComplexPattern, /*MI*/0, /*Op*/1, /*Renderer*/GIMT_Encode2(0), GIMT_Encode2(GICP_gi_mubuf_offset),
      // (st i16:{ *:[i16] }:$vdata, (MUBUFOffset:{ *:[iPTR] } v4i32:{ *:[v4i32] }:$srsrc, i32:{ *:[i32] }:$soffset, i32:{ *:[i32] }:$offset))<<P:Predicate_unindexedstore>><<P:Predicate_store_global>>  =>  (BUFFER_STORE_SHORT_OFFSET ?:{ *:[i16] }:$vdata, ?:{ *:[v4i32] }:$srsrc, ?:{ *:[i32] }:$soffset, ?:{ *:[i32] }:$offset)
      GIR_BuildMI, /*InsnID*/0, /*Opcode*/GIMT_Encode2(AMDGPU::BUFFER_STORE_SHORT_OFFSET),
      GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/0, // vdata
      GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/0, // srsrc
      GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/1, // soffset
      GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/2, // offset
      GIR_AddImm8, /*InsnID*/0, /*Imm*/0,
      GIR_AddImm8, /*InsnID*/0, /*Imm*/0,
      GIR_MergeMemOperands, /*InsnID*/0, /*NumInsns*/1, /*MergeInsnID's*/0,
      GIR_ConstrainSelectedInstOperands, /*InsnID*/0,
      GIR_EraseFromParent, /*InsnID*/0,
      // GIR_Coverage, 5495,
      GIR_Done,
    // Label 1954: @127387
    GIM_Try, /*On fail goto*//*Label 1955*/ GIMT_Encode4(127449), // Rule ID 5496 //
      GIM_CheckMemoryAddressSpace, /*MI*/0, /*MMO*/0, /*NumAddrSpace*/1, /*AddrSpace*/1,
      GIM_CheckAtomicOrdering, /*MI*/0, /*Order*/(uint8_t)AtomicOrdering::NotAtomic,
      GIM_CheckPointerToAny, /*MI*/0, /*Op*/1, /*SizeInBits*/0,
      GIM_CheckComplexPattern, /*MI*/0, /*Op*/1, /*Renderer*/GIMT_Encode2(0), GIMT_Encode2(GICP_gi_mubuf_offset),
      // (st i16:{ *:[i16] }:$vdata, (MUBUFOffset:{ *:[iPTR] } v4i32:{ *:[v4i32] }:$srsrc, i32:{ *:[i32] }:$soffset, i32:{ *:[i32] }:$offset))<<P:Predicate_unindexedstore>><<P:Predicate_store_global>>  =>  (BUFFER_STORE_SHORT_VBUFFER_OFFSET ?:{ *:[i16] }:$vdata, ?:{ *:[v4i32] }:$srsrc, ?:{ *:[i32] }:$soffset, ?:{ *:[i32] }:$offset)
      GIR_BuildMI, /*InsnID*/0, /*Opcode*/GIMT_Encode2(AMDGPU::BUFFER_STORE_SHORT_VBUFFER_OFFSET),
      GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/0, // vdata
      GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/0, // srsrc
      GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/1, // soffset
      GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/2, // offset
      GIR_AddImm8, /*InsnID*/0, /*Imm*/0,
      GIR_AddImm8, /*InsnID*/0, /*Imm*/0,
      GIR_MergeMemOperands, /*InsnID*/0, /*NumInsns*/1, /*MergeInsnID's*/0,
      GIR_ConstrainSelectedInstOperands, /*InsnID*/0,
      GIR_EraseFromParent, /*InsnID*/0,
      // GIR_Coverage, 5496,
      GIR_Done,
    // Label 1955: @127449
    GIM_Try, /*On fail goto*//*Label 1956*/ GIMT_Encode4(127513), // Rule ID 6657 //
      GIM_CheckFeatures, GIMT_Encode2(GIFBS_LDSRequiresM0Init),
      GIM_CheckMemorySizeEqualTo, /*MI*/0, /*MMO*/0, /*Size*/GIMT_Encode4(1),
      GIM_CheckMemoryAddressSpace, /*MI*/0, /*MMO*/0, /*NumAddrSpace*/1, /*AddrSpace*/3,
      GIM_CheckAtomicOrderingOrStrongerThan, /*MI*/0, /*Order*/(uint8_t)AtomicOrdering::Unordered,
      GIM_CheckPointerToAny, /*MI*/0, /*Op*/1, /*SizeInBits*/0,
      GIM_CheckComplexPattern, /*MI*/0, /*Op*/1, /*Renderer*/GIMT_Encode2(0), GIMT_Encode2(GICP_gi_ds_1addr_1offset),
      // (AMDGPUatomic_st_glue i16:{ *:[i16] }:$value, (DS1Addr1Offset:{ *:[iPTR] } i32:{ *:[i32] }:$ptr, i32:{ *:[i32] }:$offset))<<P:Predicate_atomic_store_8_glue>><<P:Predicate_atomic_store_8_local_m0>>  =>  (DS_WRITE_B8 ?:{ *:[i32] }:$ptr, anonymous_15037:{ *:[i16] }:$value, offset:{ *:[i32] }:$offset, 0:{ *:[i1] })
      GIR_BuildMI, /*InsnID*/0, /*Opcode*/GIMT_Encode2(AMDGPU::DS_WRITE_B8),
      GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/0, // ptr
      GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/0, // value
      GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/1, // offset
      GIR_AddImm8, /*InsnID*/0, /*Imm*/0,
      GIR_MergeMemOperands, /*InsnID*/0, /*NumInsns*/1, /*MergeInsnID's*/0,
      GIR_ConstrainSelectedInstOperands, /*InsnID*/0,
      GIR_EraseFromParent, /*InsnID*/0,
      // GIR_Coverage, 6657,
      GIR_Done,
    // Label 1956: @127513
    GIM_Try, /*On fail goto*//*Label 1957*/ GIMT_Encode4(127577), // Rule ID 6658 //
      GIM_CheckFeatures, GIMT_Encode2(GIFBS_NotLDSRequiresM0Init),
      GIM_CheckMemorySizeEqualTo, /*MI*/0, /*MMO*/0, /*Size*/GIMT_Encode4(1),
      GIM_CheckMemoryAddressSpace, /*MI*/0, /*MMO*/0, /*NumAddrSpace*/1, /*AddrSpace*/3,
      GIM_CheckAtomicOrderingOrStrongerThan, /*MI*/0, /*Order*/(uint8_t)AtomicOrdering::Unordered,
      GIM_CheckPointerToAny, /*MI*/0, /*Op*/1, /*SizeInBits*/0,
      GIM_CheckComplexPattern, /*MI*/0, /*Op*/1, /*Renderer*/GIMT_Encode2(0), GIMT_Encode2(GICP_gi_ds_1addr_1offset),
      // (atomic_store i16:{ *:[i16] }:$value, (DS1Addr1Offset:{ *:[iPTR] } i32:{ *:[i32] }:$ptr, i32:{ *:[i32] }:$offset))<<P:Predicate_atomic_store_8>><<P:Predicate_atomic_store_8_local>>  =>  (DS_WRITE_B8_gfx9 ?:{ *:[i32] }:$ptr, anonymous_15037:{ *:[i16] }:$value, offset:{ *:[i32] }:$offset, 0:{ *:[i1] })
      GIR_BuildMI, /*InsnID*/0, /*Opcode*/GIMT_Encode2(AMDGPU::DS_WRITE_B8_gfx9),
      GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/0, // ptr
      GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/0, // value
      GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/1, // offset
      GIR_AddImm8, /*InsnID*/0, /*Imm*/0,
      GIR_MergeMemOperands, /*InsnID*/0, /*NumInsns*/1, /*MergeInsnID's*/0,
      GIR_ConstrainSelectedInstOperands, /*InsnID*/0,
      GIR_EraseFromParent, /*InsnID*/0,
      // GIR_Coverage, 6658,
      GIR_Done,
    // Label 1957: @127577
    GIM_Try, /*On fail goto*//*Label 1958*/ GIMT_Encode4(127641), // Rule ID 6661 //
      GIM_CheckFeatures, GIMT_Encode2(GIFBS_LDSRequiresM0Init),
      GIM_CheckMemorySizeEqualTo, /*MI*/0, /*MMO*/0, /*Size*/GIMT_Encode4(2),
      GIM_CheckMemoryAddressSpace, /*MI*/0, /*MMO*/0, /*NumAddrSpace*/1, /*AddrSpace*/3,
      GIM_CheckAtomicOrderingOrStrongerThan, /*MI*/0, /*Order*/(uint8_t)AtomicOrdering::Unordered,
      GIM_CheckPointerToAny, /*MI*/0, /*Op*/1, /*SizeInBits*/0,
      GIM_CheckComplexPattern, /*MI*/0, /*Op*/1, /*Renderer*/GIMT_Encode2(0), GIMT_Encode2(GICP_gi_ds_1addr_1offset),
      // (AMDGPUatomic_st_glue i16:{ *:[i16] }:$value, (DS1Addr1Offset:{ *:[iPTR] } i32:{ *:[i32] }:$ptr, i32:{ *:[i32] }:$offset))<<P:Predicate_atomic_store_16_glue>><<P:Predicate_atomic_store_16_local_m0>>  =>  (DS_WRITE_B16 ?:{ *:[i32] }:$ptr, anonymous_15037:{ *:[i16] }:$value, offset:{ *:[i32] }:$offset, 0:{ *:[i1] })
      GIR_BuildMI, /*InsnID*/0, /*Opcode*/GIMT_Encode2(AMDGPU::DS_WRITE_B16),
      GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/0, // ptr
      GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/0, // value
      GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/1, // offset
      GIR_AddImm8, /*InsnID*/0, /*Imm*/0,
      GIR_MergeMemOperands, /*InsnID*/0, /*NumInsns*/1, /*MergeInsnID's*/0,
      GIR_ConstrainSelectedInstOperands, /*InsnID*/0,
      GIR_EraseFromParent, /*InsnID*/0,
      // GIR_Coverage, 6661,
      GIR_Done,
    // Label 1958: @127641
    GIM_Try, /*On fail goto*//*Label 1959*/ GIMT_Encode4(127705), // Rule ID 6662 //
      GIM_CheckFeatures, GIMT_Encode2(GIFBS_NotLDSRequiresM0Init),
      GIM_CheckMemorySizeEqualTo, /*MI*/0, /*MMO*/0, /*Size*/GIMT_Encode4(2),
      GIM_CheckMemoryAddressSpace, /*MI*/0, /*MMO*/0, /*NumAddrSpace*/1, /*AddrSpace*/3,
      GIM_CheckAtomicOrderingOrStrongerThan, /*MI*/0, /*Order*/(uint8_t)AtomicOrdering::Unordered,
      GIM_CheckPointerToAny, /*MI*/0, /*Op*/1, /*SizeInBits*/0,
      GIM_CheckComplexPattern, /*MI*/0, /*Op*/1, /*Renderer*/GIMT_Encode2(0), GIMT_Encode2(GICP_gi_ds_1addr_1offset),
      // (atomic_store i16:{ *:[i16] }:$value, (DS1Addr1Offset:{ *:[iPTR] } i32:{ *:[i32] }:$ptr, i32:{ *:[i32] }:$offset))<<P:Predicate_atomic_store_16>><<P:Predicate_atomic_store_16_local>>  =>  (DS_WRITE_B16_gfx9 ?:{ *:[i32] }:$ptr, anonymous_15037:{ *:[i16] }:$value, offset:{ *:[i32] }:$offset, 0:{ *:[i1] })
      GIR_BuildMI, /*InsnID*/0, /*Opcode*/GIMT_Encode2(AMDGPU::DS_WRITE_B16_gfx9),
      GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/0, // ptr
      GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/0, // value
      GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/1, // offset
      GIR_AddImm8, /*InsnID*/0, /*Imm*/0,
      GIR_MergeMemOperands, /*InsnID*/0, /*NumInsns*/1, /*MergeInsnID's*/0,
      GIR_ConstrainSelectedInstOperands, /*InsnID*/0,
      GIR_EraseFromParent, /*InsnID*/0,
      // GIR_Coverage, 6662,
      GIR_Done,
    // Label 1959: @127705
    GIM_Try, /*On fail goto*//*Label 1960*/ GIMT_Encode4(127773), // Rule ID 6635 //
      GIM_CheckFeatures, GIMT_Encode2(GIFBS_LDSRequiresM0Init),
      GIM_CheckMemorySizeLessThanLLT, /*MI*/0, /*MMO*/0, /*OpIdx*/0,
      GIM_CheckMemorySizeEqualTo, /*MI*/0, /*MMO*/0, /*Size*/GIMT_Encode4(1),
      GIM_CheckMemoryAddressSpace, /*MI*/0, /*MMO*/0, /*NumAddrSpace*/1, /*AddrSpace*/3,
      GIM_CheckAtomicOrdering, /*MI*/0, /*Order*/(uint8_t)AtomicOrdering::NotAtomic,
      GIM_CheckPointerToAny, /*MI*/0, /*Op*/1, /*SizeInBits*/0,
      GIM_CheckComplexPattern, /*MI*/0, /*Op*/1, /*Renderer*/GIMT_Encode2(0), GIMT_Encode2(GICP_gi_ds_1addr_1offset),
      // (AMDGPUst_glue i16:{ *:[i16] }:$value, (DS1Addr1Offset:{ *:[iPTR] } i32:{ *:[i32] }:$ptr, i32:{ *:[i32] }:$offset))<<P:Predicate_unindexedstore_glue>><<P:Predicate_truncstore_glue>><<P:Predicate_truncstorei8_glue>><<P:Predicate_truncstorei8_local_m0>>  =>  (DS_WRITE_B8 ?:{ *:[i32] }:$ptr, anonymous_15037:{ *:[i16] }:$value, offset:{ *:[i32] }:$offset, 0:{ *:[i1] })
      GIR_BuildMI, /*InsnID*/0, /*Opcode*/GIMT_Encode2(AMDGPU::DS_WRITE_B8),
      GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/0, // ptr
      GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/0, // value
      GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/1, // offset
      GIR_AddImm8, /*InsnID*/0, /*Imm*/0,
      GIR_MergeMemOperands, /*InsnID*/0, /*NumInsns*/1, /*MergeInsnID's*/0,
      GIR_ConstrainSelectedInstOperands, /*InsnID*/0,
      GIR_EraseFromParent, /*InsnID*/0,
      // GIR_Coverage, 6635,
      GIR_Done,
    // Label 1960: @127773
    GIM_Try, /*On fail goto*//*Label 1961*/ GIMT_Encode4(127841), // Rule ID 6636 //
      GIM_CheckFeatures, GIMT_Encode2(GIFBS_NotLDSRequiresM0Init),
      GIM_CheckMemorySizeLessThanLLT, /*MI*/0, /*MMO*/0, /*OpIdx*/0,
      GIM_CheckMemorySizeEqualTo, /*MI*/0, /*MMO*/0, /*Size*/GIMT_Encode4(1),
      GIM_CheckMemoryAddressSpace, /*MI*/0, /*MMO*/0, /*NumAddrSpace*/1, /*AddrSpace*/3,
      GIM_CheckAtomicOrdering, /*MI*/0, /*Order*/(uint8_t)AtomicOrdering::NotAtomic,
      GIM_CheckPointerToAny, /*MI*/0, /*Op*/1, /*SizeInBits*/0,
      GIM_CheckComplexPattern, /*MI*/0, /*Op*/1, /*Renderer*/GIMT_Encode2(0), GIMT_Encode2(GICP_gi_ds_1addr_1offset),
      // (st i16:{ *:[i16] }:$value, (DS1Addr1Offset:{ *:[iPTR] } i32:{ *:[i32] }:$ptr, i32:{ *:[i32] }:$offset))<<P:Predicate_unindexedstore>><<P:Predicate_truncstore>><<P:Predicate_truncstorei8>><<P:Predicate_truncstorei8_local>>  =>  (DS_WRITE_B8_gfx9 ?:{ *:[i32] }:$ptr, anonymous_15037:{ *:[i16] }:$value, offset:{ *:[i32] }:$offset, 0:{ *:[i1] })
      GIR_BuildMI, /*InsnID*/0, /*Opcode*/GIMT_Encode2(AMDGPU::DS_WRITE_B8_gfx9),
      GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/0, // ptr
      GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/0, // value
      GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/1, // offset
      GIR_AddImm8, /*InsnID*/0, /*Imm*/0,
      GIR_MergeMemOperands, /*InsnID*/0, /*NumInsns*/1, /*MergeInsnID's*/0,
      GIR_ConstrainSelectedInstOperands, /*InsnID*/0,
      GIR_EraseFromParent, /*InsnID*/0,
      // GIR_Coverage, 6636,
      GIR_Done,
    // Label 1961: @127841
    GIM_Try, /*On fail goto*//*Label 1962*/ GIMT_Encode4(127902), // Rule ID 6637 //
      GIM_CheckFeatures, GIMT_Encode2(GIFBS_LDSRequiresM0Init),
      GIM_CheckMemorySizeEqualToLLT, /*MI*/0, /*MMO*/0, /*OpIdx*/0,
      GIM_CheckMemoryAddressSpace, /*MI*/0, /*MMO*/0, /*NumAddrSpace*/1, /*AddrSpace*/3,
      GIM_CheckAtomicOrdering, /*MI*/0, /*Order*/(uint8_t)AtomicOrdering::NotAtomic,
      GIM_CheckPointerToAny, /*MI*/0, /*Op*/1, /*SizeInBits*/0,
      GIM_CheckComplexPattern, /*MI*/0, /*Op*/1, /*Renderer*/GIMT_Encode2(0), GIMT_Encode2(GICP_gi_ds_1addr_1offset),
      // (AMDGPUst_glue i16:{ *:[i16] }:$value, (DS1Addr1Offset:{ *:[iPTR] } i32:{ *:[i32] }:$ptr, i32:{ *:[i32] }:$offset))<<P:Predicate_unindexedstore_glue>><<P:Predicate_store_glue>><<P:Predicate_store_local_m0>>  =>  (DS_WRITE_B16 ?:{ *:[i32] }:$ptr, anonymous_15037:{ *:[i16] }:$value, offset:{ *:[i32] }:$offset, 0:{ *:[i1] })
      GIR_BuildMI, /*InsnID*/0, /*Opcode*/GIMT_Encode2(AMDGPU::DS_WRITE_B16),
      GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/0, // ptr
      GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/0, // value
      GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/1, // offset
      GIR_AddImm8, /*InsnID*/0, /*Imm*/0,
      GIR_MergeMemOperands, /*InsnID*/0, /*NumInsns*/1, /*MergeInsnID's*/0,
      GIR_ConstrainSelectedInstOperands, /*InsnID*/0,
      GIR_EraseFromParent, /*InsnID*/0,
      // GIR_Coverage, 6637,
      GIR_Done,
    // Label 1962: @127902
    GIM_Try, /*On fail goto*//*Label 1963*/ GIMT_Encode4(127959), // Rule ID 6638 //
      GIM_CheckFeatures, GIMT_Encode2(GIFBS_NotLDSRequiresM0Init),
      GIM_CheckMemoryAddressSpace, /*MI*/0, /*MMO*/0, /*NumAddrSpace*/1, /*AddrSpace*/3,
      GIM_CheckAtomicOrdering, /*MI*/0, /*Order*/(uint8_t)AtomicOrdering::NotAtomic,
      GIM_CheckPointerToAny, /*MI*/0, /*Op*/1, /*SizeInBits*/0,
      GIM_CheckComplexPattern, /*MI*/0, /*Op*/1, /*Renderer*/GIMT_Encode2(0), GIMT_Encode2(GICP_gi_ds_1addr_1offset),
      // (st i16:{ *:[i16] }:$value, (DS1Addr1Offset:{ *:[iPTR] } i32:{ *:[i32] }:$ptr, i32:{ *:[i32] }:$offset))<<P:Predicate_unindexedstore>><<P:Predicate_store_local>>  =>  (DS_WRITE_B16_gfx9 ?:{ *:[i32] }:$ptr, anonymous_15037:{ *:[i16] }:$value, offset:{ *:[i32] }:$offset, 0:{ *:[i1] })
      GIR_BuildMI, /*InsnID*/0, /*Opcode*/GIMT_Encode2(AMDGPU::DS_WRITE_B16_gfx9),
      GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/0, // ptr
      GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/0, // value
      GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/1, // offset
      GIR_AddImm8, /*InsnID*/0, /*Imm*/0,
      GIR_MergeMemOperands, /*InsnID*/0, /*NumInsns*/1, /*MergeInsnID's*/0,
      GIR_ConstrainSelectedInstOperands, /*InsnID*/0,
      GIR_EraseFromParent, /*InsnID*/0,
      // GIR_Coverage, 6638,
      GIR_Done,
    // Label 1963: @127959
    GIM_Try, /*On fail goto*//*Label 1964*/ GIMT_Encode4(128028), // Rule ID 3141 //
      GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasFlatGlobalInsts),
      GIM_CheckMemorySizeEqualTo, /*MI*/0, /*MMO*/0, /*Size*/GIMT_Encode4(1),
      GIM_CheckMemoryAddressSpace, /*MI*/0, /*MMO*/0, /*NumAddrSpace*/1, /*AddrSpace*/1,
      GIM_CheckAtomicOrderingOrStrongerThan, /*MI*/0, /*Order*/(uint8_t)AtomicOrdering::Unordered,
      GIM_CheckPointerToAny, /*MI*/0, /*Op*/1, /*SizeInBits*/0,
      GIM_CheckComplexPattern, /*MI*/0, /*Op*/1, /*Renderer*/GIMT_Encode2(0), GIMT_Encode2(GICP_gi_global_saddr),
      // (atomic_store i16:{ *:[i16] }:$data, (GlobalSAddr:{ *:[iPTR] } SReg_64:{ *:[i64] }:$saddr, VGPR_32:{ *:[i32] }:$voffset, i32:{ *:[i32] }:$offset))<<P:Predicate_atomic_store_8>><<P:Predicate_atomic_store_8_global>>  =>  (GLOBAL_STORE_BYTE_SADDR ?:{ *:[i32] }:$voffset, anonymous_15037:{ *:[i16] }:$data, ?:{ *:[i64] }:$saddr, ?:{ *:[i32] }:$offset)
      GIR_BuildMI, /*InsnID*/0, /*Opcode*/GIMT_Encode2(AMDGPU::GLOBAL_STORE_BYTE_SADDR),
      GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/1, // voffset
      GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/0, // data
      GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/0, // saddr
      GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/2, // offset
      GIR_AddImm8, /*InsnID*/0, /*Imm*/0,
      GIR_MergeMemOperands, /*InsnID*/0, /*NumInsns*/1, /*MergeInsnID's*/0,
      GIR_ConstrainSelectedInstOperands, /*InsnID*/0,
      GIR_EraseFromParent, /*InsnID*/0,
      // GIR_Coverage, 3141,
      GIR_Done,
    // Label 1964: @128028
    GIM_Try, /*On fail goto*//*Label 1965*/ GIMT_Encode4(128097), // Rule ID 3145 //
      GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasFlatGlobalInsts),
      GIM_CheckMemorySizeEqualTo, /*MI*/0, /*MMO*/0, /*Size*/GIMT_Encode4(2),
      GIM_CheckMemoryAddressSpace, /*MI*/0, /*MMO*/0, /*NumAddrSpace*/1, /*AddrSpace*/1,
      GIM_CheckAtomicOrderingOrStrongerThan, /*MI*/0, /*Order*/(uint8_t)AtomicOrdering::Unordered,
      GIM_CheckPointerToAny, /*MI*/0, /*Op*/1, /*SizeInBits*/0,
      GIM_CheckComplexPattern, /*MI*/0, /*Op*/1, /*Renderer*/GIMT_Encode2(0), GIMT_Encode2(GICP_gi_global_saddr),
      // (atomic_store i16:{ *:[i16] }:$data, (GlobalSAddr:{ *:[iPTR] } SReg_64:{ *:[i64] }:$saddr, VGPR_32:{ *:[i32] }:$voffset, i32:{ *:[i32] }:$offset))<<P:Predicate_atomic_store_16>><<P:Predicate_atomic_store_16_global>>  =>  (GLOBAL_STORE_SHORT_SADDR ?:{ *:[i32] }:$voffset, anonymous_15037:{ *:[i16] }:$data, ?:{ *:[i64] }:$saddr, ?:{ *:[i32] }:$offset)
      GIR_BuildMI, /*InsnID*/0, /*Opcode*/GIMT_Encode2(AMDGPU::GLOBAL_STORE_SHORT_SADDR),
      GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/1, // voffset
      GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/0, // data
      GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/0, // saddr
      GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/2, // offset
      GIR_AddImm8, /*InsnID*/0, /*Imm*/0,
      GIR_MergeMemOperands, /*InsnID*/0, /*NumInsns*/1, /*MergeInsnID's*/0,
      GIR_ConstrainSelectedInstOperands, /*InsnID*/0,
      GIR_EraseFromParent, /*InsnID*/0,
      // GIR_Coverage, 3145,
      GIR_Done,
    // Label 1965: @128097
    GIM_Try, /*On fail goto*//*Label 1966*/ GIMT_Encode4(128170), // Rule ID 3105 //
      GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasFlatGlobalInsts),
      GIM_CheckMemorySizeLessThanLLT, /*MI*/0, /*MMO*/0, /*OpIdx*/0,
      GIM_CheckMemorySizeEqualTo, /*MI*/0, /*MMO*/0, /*Size*/GIMT_Encode4(1),
      GIM_CheckMemoryAddressSpace, /*MI*/0, /*MMO*/0, /*NumAddrSpace*/1, /*AddrSpace*/1,
      GIM_CheckAtomicOrdering, /*MI*/0, /*Order*/(uint8_t)AtomicOrdering::NotAtomic,
      GIM_CheckPointerToAny, /*MI*/0, /*Op*/1, /*SizeInBits*/0,
      GIM_CheckComplexPattern, /*MI*/0, /*Op*/1, /*Renderer*/GIMT_Encode2(0), GIMT_Encode2(GICP_gi_global_saddr),
      // (st i16:{ *:[i16] }:$data, (GlobalSAddr:{ *:[iPTR] } SReg_64:{ *:[i64] }:$saddr, VGPR_32:{ *:[i32] }:$voffset, i32:{ *:[i32] }:$offset))<<P:Predicate_unindexedstore>><<P:Predicate_truncstore>><<P:Predicate_truncstorei8>><<P:Predicate_truncstorei8_global>>  =>  (GLOBAL_STORE_BYTE_SADDR ?:{ *:[i32] }:$voffset, anonymous_15037:{ *:[i16] }:$data, ?:{ *:[i64] }:$saddr, ?:{ *:[i32] }:$offset)
      GIR_BuildMI, /*InsnID*/0, /*Opcode*/GIMT_Encode2(AMDGPU::GLOBAL_STORE_BYTE_SADDR),
      GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/1, // voffset
      GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/0, // data
      GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/0, // saddr
      GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/2, // offset
      GIR_AddImm8, /*InsnID*/0, /*Imm*/0,
      GIR_MergeMemOperands, /*InsnID*/0, /*NumInsns*/1, /*MergeInsnID's*/0,
      GIR_ConstrainSelectedInstOperands, /*InsnID*/0,
      GIR_EraseFromParent, /*InsnID*/0,
      // GIR_Coverage, 3105,
      GIR_Done,
    // Label 1966: @128170
    GIM_Try, /*On fail goto*//*Label 1967*/ GIMT_Encode4(128232), // Rule ID 3109 //
      GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasFlatGlobalInsts),
      GIM_CheckMemoryAddressSpace, /*MI*/0, /*MMO*/0, /*NumAddrSpace*/1, /*AddrSpace*/1,
      GIM_CheckAtomicOrdering, /*MI*/0, /*Order*/(uint8_t)AtomicOrdering::NotAtomic,
      GIM_CheckPointerToAny, /*MI*/0, /*Op*/1, /*SizeInBits*/0,
      GIM_CheckComplexPattern, /*MI*/0, /*Op*/1, /*Renderer*/GIMT_Encode2(0), GIMT_Encode2(GICP_gi_global_saddr),
      // (st i16:{ *:[i16] }:$data, (GlobalSAddr:{ *:[iPTR] } SReg_64:{ *:[i64] }:$saddr, VGPR_32:{ *:[i32] }:$voffset, i32:{ *:[i32] }:$offset))<<P:Predicate_unindexedstore>><<P:Predicate_store_global>>  =>  (GLOBAL_STORE_SHORT_SADDR ?:{ *:[i32] }:$voffset, anonymous_15037:{ *:[i16] }:$data, ?:{ *:[i64] }:$saddr, ?:{ *:[i32] }:$offset)
      GIR_BuildMI, /*InsnID*/0, /*Opcode*/GIMT_Encode2(AMDGPU::GLOBAL_STORE_SHORT_SADDR),
      GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/1, // voffset
      GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/0, // data
      GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/0, // saddr
      GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/2, // offset
      GIR_AddImm8, /*InsnID*/0, /*Imm*/0,
      GIR_MergeMemOperands, /*InsnID*/0, /*NumInsns*/1, /*MergeInsnID's*/0,
      GIR_ConstrainSelectedInstOperands, /*InsnID*/0,
      GIR_EraseFromParent, /*InsnID*/0,
      // GIR_Coverage, 3109,
      GIR_Done,
    // Label 1967: @128232
    GIM_Try, /*On fail goto*//*Label 1968*/ GIMT_Encode4(128296), // Rule ID 3140 //
      GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasFlatGlobalInsts),
      GIM_CheckMemorySizeEqualTo, /*MI*/0, /*MMO*/0, /*Size*/GIMT_Encode4(1),
      GIM_CheckMemoryAddressSpace, /*MI*/0, /*MMO*/0, /*NumAddrSpace*/1, /*AddrSpace*/1,
      GIM_CheckAtomicOrderingOrStrongerThan, /*MI*/0, /*Order*/(uint8_t)AtomicOrdering::Unordered,
      GIM_CheckPointerToAny, /*MI*/0, /*Op*/1, /*SizeInBits*/0,
      GIM_CheckComplexPattern, /*MI*/0, /*Op*/1, /*Renderer*/GIMT_Encode2(0), GIMT_Encode2(GICP_gi_global_offset),
      // (atomic_store i16:{ *:[i16] }:$data, (GlobalOffset:{ *:[iPTR] } i64:{ *:[i64] }:$vaddr, i32:{ *:[i32] }:$offset))<<P:Predicate_atomic_store_8>><<P:Predicate_atomic_store_8_global>>  =>  (GLOBAL_STORE_BYTE ?:{ *:[i64] }:$vaddr, anonymous_15037:{ *:[i16] }:$data, ?:{ *:[i32] }:$offset)
      GIR_BuildMI, /*InsnID*/0, /*Opcode*/GIMT_Encode2(AMDGPU::GLOBAL_STORE_BYTE),
      GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/0, // vaddr
      GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/0, // data
      GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/1, // offset
      GIR_AddImm8, /*InsnID*/0, /*Imm*/0,
      GIR_MergeMemOperands, /*InsnID*/0, /*NumInsns*/1, /*MergeInsnID's*/0,
      GIR_ConstrainSelectedInstOperands, /*InsnID*/0,
      GIR_EraseFromParent, /*InsnID*/0,
      // GIR_Coverage, 3140,
      GIR_Done,
    // Label 1968: @128296
    GIM_Try, /*On fail goto*//*Label 1969*/ GIMT_Encode4(128360), // Rule ID 3144 //
      GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasFlatGlobalInsts),
      GIM_CheckMemorySizeEqualTo, /*MI*/0, /*MMO*/0, /*Size*/GIMT_Encode4(2),
      GIM_CheckMemoryAddressSpace, /*MI*/0, /*MMO*/0, /*NumAddrSpace*/1, /*AddrSpace*/1,
      GIM_CheckAtomicOrderingOrStrongerThan, /*MI*/0, /*Order*/(uint8_t)AtomicOrdering::Unordered,
      GIM_CheckPointerToAny, /*MI*/0, /*Op*/1, /*SizeInBits*/0,
      GIM_CheckComplexPattern, /*MI*/0, /*Op*/1, /*Renderer*/GIMT_Encode2(0), GIMT_Encode2(GICP_gi_global_offset),
      // (atomic_store i16:{ *:[i16] }:$data, (GlobalOffset:{ *:[iPTR] } i64:{ *:[i64] }:$vaddr, i32:{ *:[i32] }:$offset))<<P:Predicate_atomic_store_16>><<P:Predicate_atomic_store_16_global>>  =>  (GLOBAL_STORE_SHORT ?:{ *:[i64] }:$vaddr, anonymous_15037:{ *:[i16] }:$data, ?:{ *:[i32] }:$offset)
      GIR_BuildMI, /*InsnID*/0, /*Opcode*/GIMT_Encode2(AMDGPU::GLOBAL_STORE_SHORT),
      GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/0, // vaddr
      GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/0, // data
      GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/1, // offset
      GIR_AddImm8, /*InsnID*/0, /*Imm*/0,
      GIR_MergeMemOperands, /*InsnID*/0, /*NumInsns*/1, /*MergeInsnID's*/0,
      GIR_ConstrainSelectedInstOperands, /*InsnID*/0,
      GIR_EraseFromParent, /*InsnID*/0,
      // GIR_Coverage, 3144,
      GIR_Done,
    // Label 1969: @128360
    GIM_Try, /*On fail goto*//*Label 1970*/ GIMT_Encode4(128428), // Rule ID 3104 //
      GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasFlatGlobalInsts),
      GIM_CheckMemorySizeLessThanLLT, /*MI*/0, /*MMO*/0, /*OpIdx*/0,
      GIM_CheckMemorySizeEqualTo, /*MI*/0, /*MMO*/0, /*Size*/GIMT_Encode4(1),
      GIM_CheckMemoryAddressSpace, /*MI*/0, /*MMO*/0, /*NumAddrSpace*/1, /*AddrSpace*/1,
      GIM_CheckAtomicOrdering, /*MI*/0, /*Order*/(uint8_t)AtomicOrdering::NotAtomic,
      GIM_CheckPointerToAny, /*MI*/0, /*Op*/1, /*SizeInBits*/0,
      GIM_CheckComplexPattern, /*MI*/0, /*Op*/1, /*Renderer*/GIMT_Encode2(0), GIMT_Encode2(GICP_gi_global_offset),
      // (st i16:{ *:[i16] }:$data, (GlobalOffset:{ *:[iPTR] } i64:{ *:[i64] }:$vaddr, i32:{ *:[i32] }:$offset))<<P:Predicate_unindexedstore>><<P:Predicate_truncstore>><<P:Predicate_truncstorei8>><<P:Predicate_truncstorei8_global>>  =>  (GLOBAL_STORE_BYTE ?:{ *:[i64] }:$vaddr, anonymous_15037:{ *:[i16] }:$data, ?:{ *:[i32] }:$offset)
      GIR_BuildMI, /*InsnID*/0, /*Opcode*/GIMT_Encode2(AMDGPU::GLOBAL_STORE_BYTE),
      GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/0, // vaddr
      GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/0, // data
      GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/1, // offset
      GIR_AddImm8, /*InsnID*/0, /*Imm*/0,
      GIR_MergeMemOperands, /*InsnID*/0, /*NumInsns*/1, /*MergeInsnID's*/0,
      GIR_ConstrainSelectedInstOperands, /*InsnID*/0,
      GIR_EraseFromParent, /*InsnID*/0,
      // GIR_Coverage, 3104,
      GIR_Done,
    // Label 1970: @128428
    GIM_Try, /*On fail goto*//*Label 1971*/ GIMT_Encode4(128485), // Rule ID 3108 //
      GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasFlatGlobalInsts),
      GIM_CheckMemoryAddressSpace, /*MI*/0, /*MMO*/0, /*NumAddrSpace*/1, /*AddrSpace*/1,
      GIM_CheckAtomicOrdering, /*MI*/0, /*Order*/(uint8_t)AtomicOrdering::NotAtomic,
      GIM_CheckPointerToAny, /*MI*/0, /*Op*/1, /*SizeInBits*/0,
      GIM_CheckComplexPattern, /*MI*/0, /*Op*/1, /*Renderer*/GIMT_Encode2(0), GIMT_Encode2(GICP_gi_global_offset),
      // (st i16:{ *:[i16] }:$data, (GlobalOffset:{ *:[iPTR] } i64:{ *:[i64] }:$vaddr, i32:{ *:[i32] }:$offset))<<P:Predicate_unindexedstore>><<P:Predicate_store_global>>  =>  (GLOBAL_STORE_SHORT ?:{ *:[i64] }:$vaddr, anonymous_15037:{ *:[i16] }:$data, ?:{ *:[i32] }:$offset)
      GIR_BuildMI, /*InsnID*/0, /*Opcode*/GIMT_Encode2(AMDGPU::GLOBAL_STORE_SHORT),
      GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/0, // vaddr
      GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/0, // data
      GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/1, // offset
      GIR_AddImm8, /*InsnID*/0, /*Imm*/0,
      GIR_MergeMemOperands, /*InsnID*/0, /*NumInsns*/1, /*MergeInsnID's*/0,
      GIR_ConstrainSelectedInstOperands, /*InsnID*/0,
      GIR_EraseFromParent, /*InsnID*/0,
      // GIR_Coverage, 3108,
      GIR_Done,
    // Label 1971: @128485
    GIM_Try, /*On fail goto*//*Label 1972*/ GIMT_Encode4(128550), // Rule ID 2826 //
      GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasFlatAddressSpace),
      GIM_CheckMemorySizeEqualTo, /*MI*/0, /*MMO*/0, /*Size*/GIMT_Encode4(1),
      GIM_CheckMemoryAddressSpace, /*MI*/0, /*MMO*/0, /*NumAddrSpace*/2, /*AddrSpace*/0, /*AddrSpace*/1,
      GIM_CheckAtomicOrderingOrStrongerThan, /*MI*/0, /*Order*/(uint8_t)AtomicOrdering::Unordered,
      GIM_CheckPointerToAny, /*MI*/0, /*Op*/1, /*SizeInBits*/0,
      GIM_CheckComplexPattern, /*MI*/0, /*Op*/1, /*Renderer*/GIMT_Encode2(0), GIMT_Encode2(GICP_gi_flat_offset),
      // (atomic_store i16:{ *:[i16] }:$data, (FlatOffset:{ *:[iPTR] } i64:{ *:[i64] }:$vaddr, i32:{ *:[i32] }:$offset))<<P:Predicate_atomic_store_8>><<P:Predicate_atomic_store_8_flat>>  =>  (FLAT_STORE_BYTE ?:{ *:[i64] }:$vaddr, anonymous_15037:{ *:[i16] }:$data, ?:{ *:[i32] }:$offset)
      GIR_BuildMI, /*InsnID*/0, /*Opcode*/GIMT_Encode2(AMDGPU::FLAT_STORE_BYTE),
      GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/0, // vaddr
      GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/0, // data
      GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/1, // offset
      GIR_AddImm8, /*InsnID*/0, /*Imm*/0,
      GIR_MergeMemOperands, /*InsnID*/0, /*NumInsns*/1, /*MergeInsnID's*/0,
      GIR_ConstrainSelectedInstOperands, /*InsnID*/0,
      GIR_EraseFromParent, /*InsnID*/0,
      // GIR_Coverage, 2826,
      GIR_Done,
    // Label 1972: @128550
    GIM_Try, /*On fail goto*//*Label 1973*/ GIMT_Encode4(128615), // Rule ID 2828 //
      GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasFlatAddressSpace),
      GIM_CheckMemorySizeEqualTo, /*MI*/0, /*MMO*/0, /*Size*/GIMT_Encode4(2),
      GIM_CheckMemoryAddressSpace, /*MI*/0, /*MMO*/0, /*NumAddrSpace*/2, /*AddrSpace*/0, /*AddrSpace*/1,
      GIM_CheckAtomicOrderingOrStrongerThan, /*MI*/0, /*Order*/(uint8_t)AtomicOrdering::Unordered,
      GIM_CheckPointerToAny, /*MI*/0, /*Op*/1, /*SizeInBits*/0,
      GIM_CheckComplexPattern, /*MI*/0, /*Op*/1, /*Renderer*/GIMT_Encode2(0), GIMT_Encode2(GICP_gi_flat_offset),
      // (atomic_store i16:{ *:[i16] }:$data, (FlatOffset:{ *:[iPTR] } i64:{ *:[i64] }:$vaddr, i32:{ *:[i32] }:$offset))<<P:Predicate_atomic_store_16>><<P:Predicate_atomic_store_16_flat>>  =>  (FLAT_STORE_SHORT ?:{ *:[i64] }:$vaddr, anonymous_15037:{ *:[i16] }:$data, ?:{ *:[i32] }:$offset)
      GIR_BuildMI, /*InsnID*/0, /*Opcode*/GIMT_Encode2(AMDGPU::FLAT_STORE_SHORT),
      GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/0, // vaddr
      GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/0, // data
      GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/1, // offset
      GIR_AddImm8, /*InsnID*/0, /*Imm*/0,
      GIR_MergeMemOperands, /*InsnID*/0, /*NumInsns*/1, /*MergeInsnID's*/0,
      GIR_ConstrainSelectedInstOperands, /*InsnID*/0,
      GIR_EraseFromParent, /*InsnID*/0,
      // GIR_Coverage, 2828,
      GIR_Done,
    // Label 1973: @128615
    GIM_Try, /*On fail goto*//*Label 1974*/ GIMT_Encode4(128684), // Rule ID 2933 //
      GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasFlatAddressSpace),
      GIM_CheckMemorySizeLessThanLLT, /*MI*/0, /*MMO*/0, /*OpIdx*/0,
      GIM_CheckMemorySizeEqualTo, /*MI*/0, /*MMO*/0, /*Size*/GIMT_Encode4(1),
      GIM_CheckMemoryAddressSpace, /*MI*/0, /*MMO*/0, /*NumAddrSpace*/2, /*AddrSpace*/0, /*AddrSpace*/1,
      GIM_CheckAtomicOrdering, /*MI*/0, /*Order*/(uint8_t)AtomicOrdering::NotAtomic,
      GIM_CheckPointerToAny, /*MI*/0, /*Op*/1, /*SizeInBits*/0,
      GIM_CheckComplexPattern, /*MI*/0, /*Op*/1, /*Renderer*/GIMT_Encode2(0), GIMT_Encode2(GICP_gi_flat_offset),
      // (st i16:{ *:[i16] }:$data, (FlatOffset:{ *:[iPTR] } i64:{ *:[i64] }:$vaddr, i32:{ *:[i32] }:$offset))<<P:Predicate_unindexedstore>><<P:Predicate_truncstore>><<P:Predicate_truncstorei8>><<P:Predicate_truncstorei8_flat>>  =>  (FLAT_STORE_BYTE ?:{ *:[i64] }:$vaddr, anonymous_15037:{ *:[i16] }:$data, ?:{ *:[i32] }:$offset)
      GIR_BuildMI, /*InsnID*/0, /*Opcode*/GIMT_Encode2(AMDGPU::FLAT_STORE_BYTE),
      GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/0, // vaddr
      GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/0, // data
      GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/1, // offset
      GIR_AddImm8, /*InsnID*/0, /*Imm*/0,
      GIR_MergeMemOperands, /*InsnID*/0, /*NumInsns*/1, /*MergeInsnID's*/0,
      GIR_ConstrainSelectedInstOperands, /*InsnID*/0,
      GIR_EraseFromParent, /*InsnID*/0,
      // GIR_Coverage, 2933,
      GIR_Done,
    // Label 1974: @128684
    GIM_Try, /*On fail goto*//*Label 1975*/ GIMT_Encode4(128742), // Rule ID 2934 //
      GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasFlatAddressSpace),
      GIM_CheckMemoryAddressSpace, /*MI*/0, /*MMO*/0, /*NumAddrSpace*/2, /*AddrSpace*/0, /*AddrSpace*/1,
      GIM_CheckAtomicOrdering, /*MI*/0, /*Order*/(uint8_t)AtomicOrdering::NotAtomic,
      GIM_CheckPointerToAny, /*MI*/0, /*Op*/1, /*SizeInBits*/0,
      GIM_CheckComplexPattern, /*MI*/0, /*Op*/1, /*Renderer*/GIMT_Encode2(0), GIMT_Encode2(GICP_gi_flat_offset),
      // (st i16:{ *:[i16] }:$data, (FlatOffset:{ *:[iPTR] } i64:{ *:[i64] }:$vaddr, i32:{ *:[i32] }:$offset))<<P:Predicate_unindexedstore>><<P:Predicate_store_flat>>  =>  (FLAT_STORE_SHORT ?:{ *:[i64] }:$vaddr, anonymous_15037:{ *:[i16] }:$data, ?:{ *:[i32] }:$offset)
      GIR_BuildMI, /*InsnID*/0, /*Opcode*/GIMT_Encode2(AMDGPU::FLAT_STORE_SHORT),
      GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/0, // vaddr
      GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/0, // data
      GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/1, // offset
      GIR_AddImm8, /*InsnID*/0, /*Imm*/0,
      GIR_MergeMemOperands, /*InsnID*/0, /*NumInsns*/1, /*MergeInsnID's*/0,
      GIR_ConstrainSelectedInstOperands, /*InsnID*/0,
      GIR_EraseFromParent, /*InsnID*/0,
      // GIR_Coverage, 2934,
      GIR_Done,
    // Label 1975: @128742
    GIM_Reject,
    // Label 1814: @128743
    GIM_Try, /*On fail goto*//*Label 1976*/ GIMT_Encode4(128842), // Rule ID 5562 //
      GIM_CheckFeatures, GIMT_Encode2(GIFBS_DisableFlatScratch_HasD16LoadStore_HasUnrestrictedSOffset),
      GIM_CheckMemorySizeLessThanLLT, /*MI*/0, /*MMO*/0, /*OpIdx*/0,
      GIM_CheckMemorySizeEqualTo, /*MI*/0, /*MMO*/0, /*Size*/GIMT_Encode4(2),
      GIM_CheckMemoryAddressSpace, /*MI*/0, /*MMO*/0, /*NumAddrSpace*/1, /*AddrSpace*/5,
      GIM_CheckAtomicOrdering, /*MI*/0, /*Order*/(uint8_t)AtomicOrdering::NotAtomic,
      GIM_RecordInsn, /*DefineMI*/1, /*MI*/0, /*OpIdx*/0, // MIs[1]
      GIM_CheckOpcode, /*MI*/1, GIMT_Encode2(TargetOpcode::G_LSHR),
      GIM_CheckType, /*MI*/1, /*Op*/1, /*Type*/GILLT_s32,
      GIM_CheckType, /*MI*/1, /*Op*/2, /*Type*/GILLT_s32,
      GIM_CheckConstantInt8, /*MI*/1, /*Op*/2, 16,
      GIM_CheckPointerToAny, /*MI*/0, /*Op*/1, /*SizeInBits*/0,
      GIM_CheckIsSafeToFold, /*InsnID*/1,
      GIM_CheckComplexPattern, /*MI*/0, /*Op*/1, /*Renderer*/GIMT_Encode2(0), GIMT_Encode2(GICP_gi_mubuf_scratch_offset),
      // (st (srl:{ *:[i32] } i32:{ *:[i32] }:$value, 16:{ *:[i32] }), (MUBUFScratchOffset:{ *:[iPTR] } v4i32:{ *:[v4i32] }:$srsrc, i32:{ *:[i32] }:$soffset, i32:{ *:[i32] }:$offset))<<P:Predicate_unindexedstore>><<P:Predicate_truncstore>><<P:Predicate_truncstorei16>><<P:Predicate_store_hi16_private>>  =>  (BUFFER_STORE_SHORT_D16_HI_OFFSET VGPR_32:{ *:[i32] }:$value, ?:{ *:[v4i32] }:$srsrc, ?:{ *:[i32] }:$soffset, ?:{ *:[i32] }:$offset, 0:{ *:[i32] }, 0:{ *:[i1] })
      GIR_BuildMI, /*InsnID*/0, /*Opcode*/GIMT_Encode2(AMDGPU::BUFFER_STORE_SHORT_D16_HI_OFFSET),
      GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/1, /*OpIdx*/1, // value
      GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/0, // srsrc
      GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/1, // soffset
      GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/2, // offset
      GIR_AddImm8, /*InsnID*/0, /*Imm*/0,
      GIR_AddImm8, /*InsnID*/0, /*Imm*/0,
      GIR_MergeMemOperands, /*InsnID*/0, /*NumInsns*/2, /*MergeInsnID's*/0, 1,
      GIR_ConstrainSelectedInstOperands, /*InsnID*/0,
      GIR_EraseFromParent, /*InsnID*/0,
      // GIR_Coverage, 5562,
      GIR_Done,
    // Label 1976: @128842
    GIM_Try, /*On fail goto*//*Label 1977*/ GIMT_Encode4(128941), // Rule ID 5564 //
      GIM_CheckFeatures, GIMT_Encode2(GIFBS_DisableFlatScratch_HasD16LoadStore),
      GIM_CheckMemorySizeLessThanLLT, /*MI*/0, /*MMO*/0, /*OpIdx*/0,
      GIM_CheckMemorySizeEqualTo, /*MI*/0, /*MMO*/0, /*Size*/GIMT_Encode4(2),
      GIM_CheckMemoryAddressSpace, /*MI*/0, /*MMO*/0, /*NumAddrSpace*/1, /*AddrSpace*/5,
      GIM_CheckAtomicOrdering, /*MI*/0, /*Order*/(uint8_t)AtomicOrdering::NotAtomic,
      GIM_RecordInsn, /*DefineMI*/1, /*MI*/0, /*OpIdx*/0, // MIs[1]
      GIM_CheckOpcode, /*MI*/1, GIMT_Encode2(TargetOpcode::G_LSHR),
      GIM_CheckType, /*MI*/1, /*Op*/1, /*Type*/GILLT_s32,
      GIM_CheckType, /*MI*/1, /*Op*/2, /*Type*/GILLT_s32,
      GIM_CheckConstantInt8, /*MI*/1, /*Op*/2, 16,
      GIM_CheckPointerToAny, /*MI*/0, /*Op*/1, /*SizeInBits*/0,
      GIM_CheckIsSafeToFold, /*InsnID*/1,
      GIM_CheckComplexPattern, /*MI*/0, /*Op*/1, /*Renderer*/GIMT_Encode2(0), GIMT_Encode2(GICP_gi_mubuf_scratch_offset),
      // (st (srl:{ *:[i32] } i32:{ *:[i32] }:$value, 16:{ *:[i32] }), (MUBUFScratchOffset:{ *:[iPTR] } v4i32:{ *:[v4i32] }:$srsrc, i32:{ *:[i32] }:$soffset, i32:{ *:[i32] }:$offset))<<P:Predicate_unindexedstore>><<P:Predicate_truncstore>><<P:Predicate_truncstorei16>><<P:Predicate_store_hi16_private>>  =>  (BUFFER_STORE_SHORT_D16_HI_VBUFFER_OFFSET VGPR_32:{ *:[i32] }:$value, ?:{ *:[v4i32] }:$srsrc, ?:{ *:[i32] }:$soffset, ?:{ *:[i32] }:$offset, 0:{ *:[i32] }, 0:{ *:[i1] })
      GIR_BuildMI, /*InsnID*/0, /*Opcode*/GIMT_Encode2(AMDGPU::BUFFER_STORE_SHORT_D16_HI_VBUFFER_OFFSET),
      GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/1, /*OpIdx*/1, // value
      GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/0, // srsrc
      GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/1, // soffset
      GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/2, // offset
      GIR_AddImm8, /*InsnID*/0, /*Imm*/0,
      GIR_AddImm8, /*InsnID*/0, /*Imm*/0,
      GIR_MergeMemOperands, /*InsnID*/0, /*NumInsns*/2, /*MergeInsnID's*/0, 1,
      GIR_ConstrainSelectedInstOperands, /*InsnID*/0,
      GIR_EraseFromParent, /*InsnID*/0,
      // GIR_Coverage, 5564,
      GIR_Done,
    // Label 1977: @128941
    GIM_Try, /*On fail goto*//*Label 1978*/ GIMT_Encode4(129040), // Rule ID 5566 //
      GIM_CheckFeatures, GIMT_Encode2(GIFBS_DisableFlatScratch_HasD16LoadStore_HasUnrestrictedSOffset),
      GIM_CheckMemorySizeLessThanLLT, /*MI*/0, /*MMO*/0, /*OpIdx*/0,
      GIM_CheckMemorySizeEqualTo, /*MI*/0, /*MMO*/0, /*Size*/GIMT_Encode4(1),
      GIM_CheckMemoryAddressSpace, /*MI*/0, /*MMO*/0, /*NumAddrSpace*/1, /*AddrSpace*/5,
      GIM_CheckAtomicOrdering, /*MI*/0, /*Order*/(uint8_t)AtomicOrdering::NotAtomic,
      GIM_RecordInsn, /*DefineMI*/1, /*MI*/0, /*OpIdx*/0, // MIs[1]
      GIM_CheckOpcode, /*MI*/1, GIMT_Encode2(TargetOpcode::G_LSHR),
      GIM_CheckType, /*MI*/1, /*Op*/1, /*Type*/GILLT_s32,
      GIM_CheckType, /*MI*/1, /*Op*/2, /*Type*/GILLT_s32,
      GIM_CheckConstantInt8, /*MI*/1, /*Op*/2, 16,
      GIM_CheckPointerToAny, /*MI*/0, /*Op*/1, /*SizeInBits*/0,
      GIM_CheckIsSafeToFold, /*InsnID*/1,
      GIM_CheckComplexPattern, /*MI*/0, /*Op*/1, /*Renderer*/GIMT_Encode2(0), GIMT_Encode2(GICP_gi_mubuf_scratch_offset),
      // (st (srl:{ *:[i32] } i32:{ *:[i32] }:$value, 16:{ *:[i32] }), (MUBUFScratchOffset:{ *:[iPTR] } v4i32:{ *:[v4i32] }:$srsrc, i32:{ *:[i32] }:$soffset, i32:{ *:[i32] }:$offset))<<P:Predicate_unindexedstore>><<P:Predicate_truncstore>><<P:Predicate_truncstorei8>><<P:Predicate_truncstorei8_hi16_private>>  =>  (BUFFER_STORE_BYTE_D16_HI_OFFSET VGPR_32:{ *:[i32] }:$value, ?:{ *:[v4i32] }:$srsrc, ?:{ *:[i32] }:$soffset, ?:{ *:[i32] }:$offset, 0:{ *:[i32] }, 0:{ *:[i1] })
      GIR_BuildMI, /*InsnID*/0, /*Opcode*/GIMT_Encode2(AMDGPU::BUFFER_STORE_BYTE_D16_HI_OFFSET),
      GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/1, /*OpIdx*/1, // value
      GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/0, // srsrc
      GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/1, // soffset
      GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/2, // offset
      GIR_AddImm8, /*InsnID*/0, /*Imm*/0,
      GIR_AddImm8, /*InsnID*/0, /*Imm*/0,
      GIR_MergeMemOperands, /*InsnID*/0, /*NumInsns*/2, /*MergeInsnID's*/0, 1,
      GIR_ConstrainSelectedInstOperands, /*InsnID*/0,
      GIR_EraseFromParent, /*InsnID*/0,
      // GIR_Coverage, 5566,
      GIR_Done,
    // Label 1978: @129040
    GIM_Try, /*On fail goto*//*Label 1979*/ GIMT_Encode4(129139), // Rule ID 5568 //
      GIM_CheckFeatures, GIMT_Encode2(GIFBS_DisableFlatScratch_HasD16LoadStore),
      GIM_CheckMemorySizeLessThanLLT, /*MI*/0, /*MMO*/0, /*OpIdx*/0,
      GIM_CheckMemorySizeEqualTo, /*MI*/0, /*MMO*/0, /*Size*/GIMT_Encode4(1),
      GIM_CheckMemoryAddressSpace, /*MI*/0, /*MMO*/0, /*NumAddrSpace*/1, /*AddrSpace*/5,
      GIM_CheckAtomicOrdering, /*MI*/0, /*Order*/(uint8_t)AtomicOrdering::NotAtomic,
      GIM_RecordInsn, /*DefineMI*/1, /*MI*/0, /*OpIdx*/0, // MIs[1]
      GIM_CheckOpcode, /*MI*/1, GIMT_Encode2(TargetOpcode::G_LSHR),
      GIM_CheckType, /*MI*/1, /*Op*/1, /*Type*/GILLT_s32,
      GIM_CheckType, /*MI*/1, /*Op*/2, /*Type*/GILLT_s32,
      GIM_CheckConstantInt8, /*MI*/1, /*Op*/2, 16,
      GIM_CheckPointerToAny, /*MI*/0, /*Op*/1, /*SizeInBits*/0,
      GIM_CheckIsSafeToFold, /*InsnID*/1,
      GIM_CheckComplexPattern, /*MI*/0, /*Op*/1, /*Renderer*/GIMT_Encode2(0), GIMT_Encode2(GICP_gi_mubuf_scratch_offset),
      // (st (srl:{ *:[i32] } i32:{ *:[i32] }:$value, 16:{ *:[i32] }), (MUBUFScratchOffset:{ *:[iPTR] } v4i32:{ *:[v4i32] }:$srsrc, i32:{ *:[i32] }:$soffset, i32:{ *:[i32] }:$offset))<<P:Predicate_unindexedstore>><<P:Predicate_truncstore>><<P:Predicate_truncstorei8>><<P:Predicate_truncstorei8_hi16_private>>  =>  (BUFFER_STORE_BYTE_D16_HI_VBUFFER_OFFSET VGPR_32:{ *:[i32] }:$value, ?:{ *:[v4i32] }:$srsrc, ?:{ *:[i32] }:$soffset, ?:{ *:[i32] }:$offset, 0:{ *:[i32] }, 0:{ *:[i1] })
      GIR_BuildMI, /*InsnID*/0, /*Opcode*/GIMT_Encode2(AMDGPU::BUFFER_STORE_BYTE_D16_HI_VBUFFER_OFFSET),
      GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/1, /*OpIdx*/1, // value
      GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/0, // srsrc
      GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/1, // soffset
      GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/2, // offset
      GIR_AddImm8, /*InsnID*/0, /*Imm*/0,
      GIR_AddImm8, /*InsnID*/0, /*Imm*/0,
      GIR_MergeMemOperands, /*InsnID*/0, /*NumInsns*/2, /*MergeInsnID's*/0, 1,
      GIR_ConstrainSelectedInstOperands, /*InsnID*/0,
      GIR_EraseFromParent, /*InsnID*/0,
      // GIR_Coverage, 5568,
      GIR_Done,
    // Label 1979: @129139
    GIM_Try, /*On fail goto*//*Label 1980*/ GIMT_Encode4(129235), // Rule ID 3604 //
      GIM_CheckFeatures, GIMT_Encode2(GIFBS_EnableFlatScratch_HasD16LoadStore_HasFlatScratchInsts_HasFlatScratchSVSMode),
      GIM_CheckMemorySizeLessThanLLT, /*MI*/0, /*MMO*/0, /*OpIdx*/0,
      GIM_CheckMemorySizeEqualTo, /*MI*/0, /*MMO*/0, /*Size*/GIMT_Encode4(2),
      GIM_CheckMemoryAddressSpace, /*MI*/0, /*MMO*/0, /*NumAddrSpace*/1, /*AddrSpace*/5,
      GIM_CheckAtomicOrdering, /*MI*/0, /*Order*/(uint8_t)AtomicOrdering::NotAtomic,
      GIM_RecordInsn, /*DefineMI*/1, /*MI*/0, /*OpIdx*/0, // MIs[1]
      GIM_CheckOpcode, /*MI*/1, GIMT_Encode2(TargetOpcode::G_LSHR),
      GIM_CheckType, /*MI*/1, /*Op*/1, /*Type*/GILLT_s32,
      GIM_CheckType, /*MI*/1, /*Op*/2, /*Type*/GILLT_s32,
      GIM_CheckConstantInt8, /*MI*/1, /*Op*/2, 16,
      GIM_CheckPointerToAny, /*MI*/0, /*Op*/1, /*SizeInBits*/0,
      GIM_CheckIsSafeToFold, /*InsnID*/1,
      GIM_CheckComplexPattern, /*MI*/0, /*Op*/1, /*Renderer*/GIMT_Encode2(0), GIMT_Encode2(GICP_gi_flat_scratch_svaddr),
      // (st (srl:{ *:[i32] } i32:{ *:[i32] }:$data, 16:{ *:[i32] }), (ScratchSVAddr:{ *:[iPTR] } VGPR_32:{ *:[i32] }:$vaddr, SGPR_32:{ *:[i32] }:$saddr, i32:{ *:[i32] }:$offset))<<P:Predicate_unindexedstore>><<P:Predicate_truncstore>><<P:Predicate_truncstorei16>><<P:Predicate_truncstorei16_hi16_private>>  =>  (SCRATCH_STORE_SHORT_D16_HI_SVS anonymous_15037:{ *:[i32] }:$data, ?:{ *:[i32] }:$vaddr, ?:{ *:[i32] }:$saddr, ?:{ *:[i32] }:$offset)
      GIR_BuildMI, /*InsnID*/0, /*Opcode*/GIMT_Encode2(AMDGPU::SCRATCH_STORE_SHORT_D16_HI_SVS),
      GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/1, /*OpIdx*/1, // data
      GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/0, // vaddr
      GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/1, // saddr
      GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/2, // offset
      GIR_AddImm8, /*InsnID*/0, /*Imm*/0,
      GIR_MergeMemOperands, /*InsnID*/0, /*NumInsns*/2, /*MergeInsnID's*/0, 1,
      GIR_ConstrainSelectedInstOperands, /*InsnID*/0,
      GIR_EraseFromParent, /*InsnID*/0,
      // GIR_Coverage, 3604,
      GIR_Done,
    // Label 1980: @129235
    GIM_Try, /*On fail goto*//*Label 1981*/ GIMT_Encode4(129331), // Rule ID 3607 //
      GIM_CheckFeatures, GIMT_Encode2(GIFBS_EnableFlatScratch_HasD16LoadStore_HasFlatScratchInsts_HasFlatScratchSVSMode),
      GIM_CheckMemorySizeLessThanLLT, /*MI*/0, /*MMO*/0, /*OpIdx*/0,
      GIM_CheckMemorySizeEqualTo, /*MI*/0, /*MMO*/0, /*Size*/GIMT_Encode4(1),
      GIM_CheckMemoryAddressSpace, /*MI*/0, /*MMO*/0, /*NumAddrSpace*/1, /*AddrSpace*/5,
      GIM_CheckAtomicOrdering, /*MI*/0, /*Order*/(uint8_t)AtomicOrdering::NotAtomic,
      GIM_RecordInsn, /*DefineMI*/1, /*MI*/0, /*OpIdx*/0, // MIs[1]
      GIM_CheckOpcode, /*MI*/1, GIMT_Encode2(TargetOpcode::G_LSHR),
      GIM_CheckType, /*MI*/1, /*Op*/1, /*Type*/GILLT_s32,
      GIM_CheckType, /*MI*/1, /*Op*/2, /*Type*/GILLT_s32,
      GIM_CheckConstantInt8, /*MI*/1, /*Op*/2, 16,
      GIM_CheckPointerToAny, /*MI*/0, /*Op*/1, /*SizeInBits*/0,
      GIM_CheckIsSafeToFold, /*InsnID*/1,
      GIM_CheckComplexPattern, /*MI*/0, /*Op*/1, /*Renderer*/GIMT_Encode2(0), GIMT_Encode2(GICP_gi_flat_scratch_svaddr),
      // (st (srl:{ *:[i32] } i32:{ *:[i32] }:$data, 16:{ *:[i32] }), (ScratchSVAddr:{ *:[iPTR] } VGPR_32:{ *:[i32] }:$vaddr, SGPR_32:{ *:[i32] }:$saddr, i32:{ *:[i32] }:$offset))<<P:Predicate_unindexedstore>><<P:Predicate_truncstore>><<P:Predicate_truncstorei8>><<P:Predicate_truncstorei8_hi16_private>>  =>  (SCRATCH_STORE_BYTE_D16_HI_SVS anonymous_15037:{ *:[i32] }:$data, ?:{ *:[i32] }:$vaddr, ?:{ *:[i32] }:$saddr, ?:{ *:[i32] }:$offset)
      GIR_BuildMI, /*InsnID*/0, /*Opcode*/GIMT_Encode2(AMDGPU::SCRATCH_STORE_BYTE_D16_HI_SVS),
      GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/1, /*OpIdx*/1, // data
      GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/0, // vaddr
      GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/1, // saddr
      GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/2, // offset
      GIR_AddImm8, /*InsnID*/0, /*Imm*/0,
      GIR_MergeMemOperands, /*InsnID*/0, /*NumInsns*/2, /*MergeInsnID's*/0, 1,
      GIR_ConstrainSelectedInstOperands, /*InsnID*/0,
      GIR_EraseFromParent, /*InsnID*/0,
      // GIR_Coverage, 3607,
      GIR_Done,
    // Label 1981: @129331
    GIM_Try, /*On fail goto*//*Label 1982*/ GIMT_Encode4(129422), // Rule ID 3603 //
      GIM_CheckFeatures, GIMT_Encode2(GIFBS_EnableFlatScratch_HasD16LoadStore_HasFlatScratchInsts),
      GIM_CheckMemorySizeLessThanLLT, /*MI*/0, /*MMO*/0, /*OpIdx*/0,
      GIM_CheckMemorySizeEqualTo, /*MI*/0, /*MMO*/0, /*Size*/GIMT_Encode4(2),
      GIM_CheckMemoryAddressSpace, /*MI*/0, /*MMO*/0, /*NumAddrSpace*/1, /*AddrSpace*/5,
      GIM_CheckAtomicOrdering, /*MI*/0, /*Order*/(uint8_t)AtomicOrdering::NotAtomic,
      GIM_RecordInsn, /*DefineMI*/1, /*MI*/0, /*OpIdx*/0, // MIs[1]
      GIM_CheckOpcode, /*MI*/1, GIMT_Encode2(TargetOpcode::G_LSHR),
      GIM_CheckType, /*MI*/1, /*Op*/1, /*Type*/GILLT_s32,
      GIM_CheckType, /*MI*/1, /*Op*/2, /*Type*/GILLT_s32,
      GIM_CheckConstantInt8, /*MI*/1, /*Op*/2, 16,
      GIM_CheckPointerToAny, /*MI*/0, /*Op*/1, /*SizeInBits*/0,
      GIM_CheckIsSafeToFold, /*InsnID*/1,
      GIM_CheckComplexPattern, /*MI*/0, /*Op*/1, /*Renderer*/GIMT_Encode2(0), GIMT_Encode2(GICP_gi_flat_scratch_saddr),
      // (st (srl:{ *:[i32] } i32:{ *:[i32] }:$data, 16:{ *:[i32] }), (ScratchSAddr:{ *:[iPTR] } SGPR_32:{ *:[i32] }:$saddr, i32:{ *:[i32] }:$offset))<<P:Predicate_unindexedstore>><<P:Predicate_truncstore>><<P:Predicate_truncstorei16>><<P:Predicate_truncstorei16_hi16_private>>  =>  (SCRATCH_STORE_SHORT_D16_HI_SADDR anonymous_15037:{ *:[i32] }:$data, ?:{ *:[i32] }:$saddr, ?:{ *:[i32] }:$offset)
      GIR_BuildMI, /*InsnID*/0, /*Opcode*/GIMT_Encode2(AMDGPU::SCRATCH_STORE_SHORT_D16_HI_SADDR),
      GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/1, /*OpIdx*/1, // data
      GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/0, // saddr
      GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/1, // offset
      GIR_AddImm8, /*InsnID*/0, /*Imm*/0,
      GIR_MergeMemOperands, /*InsnID*/0, /*NumInsns*/2, /*MergeInsnID's*/0, 1,
      GIR_ConstrainSelectedInstOperands, /*InsnID*/0,
      GIR_EraseFromParent, /*InsnID*/0,
      // GIR_Coverage, 3603,
      GIR_Done,
    // Label 1982: @129422
    GIM_Try, /*On fail goto*//*Label 1983*/ GIMT_Encode4(129513), // Rule ID 3606 //
      GIM_CheckFeatures, GIMT_Encode2(GIFBS_EnableFlatScratch_HasD16LoadStore_HasFlatScratchInsts),
      GIM_CheckMemorySizeLessThanLLT, /*MI*/0, /*MMO*/0, /*OpIdx*/0,
      GIM_CheckMemorySizeEqualTo, /*MI*/0, /*MMO*/0, /*Size*/GIMT_Encode4(1),
      GIM_CheckMemoryAddressSpace, /*MI*/0, /*MMO*/0, /*NumAddrSpace*/1, /*AddrSpace*/5,
      GIM_CheckAtomicOrdering, /*MI*/0, /*Order*/(uint8_t)AtomicOrdering::NotAtomic,
      GIM_RecordInsn, /*DefineMI*/1, /*MI*/0, /*OpIdx*/0, // MIs[1]
      GIM_CheckOpcode, /*MI*/1, GIMT_Encode2(TargetOpcode::G_LSHR),
      GIM_CheckType, /*MI*/1, /*Op*/1, /*Type*/GILLT_s32,
      GIM_CheckType, /*MI*/1, /*Op*/2, /*Type*/GILLT_s32,
      GIM_CheckConstantInt8, /*MI*/1, /*Op*/2, 16,
      GIM_CheckPointerToAny, /*MI*/0, /*Op*/1, /*SizeInBits*/0,
      GIM_CheckIsSafeToFold, /*InsnID*/1,
      GIM_CheckComplexPattern, /*MI*/0, /*Op*/1, /*Renderer*/GIMT_Encode2(0), GIMT_Encode2(GICP_gi_flat_scratch_saddr),
      // (st (srl:{ *:[i32] } i32:{ *:[i32] }:$data, 16:{ *:[i32] }), (ScratchSAddr:{ *:[iPTR] } SGPR_32:{ *:[i32] }:$saddr, i32:{ *:[i32] }:$offset))<<P:Predicate_unindexedstore>><<P:Predicate_truncstore>><<P:Predicate_truncstorei8>><<P:Predicate_truncstorei8_hi16_private>>  =>  (SCRATCH_STORE_BYTE_D16_HI_SADDR anonymous_15037:{ *:[i32] }:$data, ?:{ *:[i32] }:$saddr, ?:{ *:[i32] }:$offset)
      GIR_BuildMI, /*InsnID*/0, /*Opcode*/GIMT_Encode2(AMDGPU::SCRATCH_STORE_BYTE_D16_HI_SADDR),
      GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/1, /*OpIdx*/1, // data
      GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/0, // saddr
      GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/1, // offset
      GIR_AddImm8, /*InsnID*/0, /*Imm*/0,
      GIR_MergeMemOperands, /*InsnID*/0, /*NumInsns*/2, /*MergeInsnID's*/0, 1,
      GIR_ConstrainSelectedInstOperands, /*InsnID*/0,
      GIR_EraseFromParent, /*InsnID*/0,
      // GIR_Coverage, 3606,
      GIR_Done,
    // Label 1983: @129513
    GIM_Try, /*On fail goto*//*Label 1984*/ GIMT_Encode4(129604), // Rule ID 3602 //
      GIM_CheckFeatures, GIMT_Encode2(GIFBS_EnableFlatScratch_HasD16LoadStore_HasFlatScratchInsts),
      GIM_CheckMemorySizeLessThanLLT, /*MI*/0, /*MMO*/0, /*OpIdx*/0,
      GIM_CheckMemorySizeEqualTo, /*MI*/0, /*MMO*/0, /*Size*/GIMT_Encode4(2),
      GIM_CheckMemoryAddressSpace, /*MI*/0, /*MMO*/0, /*NumAddrSpace*/1, /*AddrSpace*/5,
      GIM_CheckAtomicOrdering, /*MI*/0, /*Order*/(uint8_t)AtomicOrdering::NotAtomic,
      GIM_RecordInsn, /*DefineMI*/1, /*MI*/0, /*OpIdx*/0, // MIs[1]
      GIM_CheckOpcode, /*MI*/1, GIMT_Encode2(TargetOpcode::G_LSHR),
      GIM_CheckType, /*MI*/1, /*Op*/1, /*Type*/GILLT_s32,
      GIM_CheckType, /*MI*/1, /*Op*/2, /*Type*/GILLT_s32,
      GIM_CheckConstantInt8, /*MI*/1, /*Op*/2, 16,
      GIM_CheckPointerToAny, /*MI*/0, /*Op*/1, /*SizeInBits*/0,
      GIM_CheckIsSafeToFold, /*InsnID*/1,
      GIM_CheckComplexPattern, /*MI*/0, /*Op*/1, /*Renderer*/GIMT_Encode2(0), GIMT_Encode2(GICP_gi_flat_scratch_offset),
      // (st (srl:{ *:[i32] } i32:{ *:[i32] }:$data, 16:{ *:[i32] }), (ScratchOffset:{ *:[iPTR] } VGPR_32:{ *:[i32] }:$vaddr, i32:{ *:[i32] }:$offset))<<P:Predicate_unindexedstore>><<P:Predicate_truncstore>><<P:Predicate_truncstorei16>><<P:Predicate_truncstorei16_hi16_private>>  =>  (SCRATCH_STORE_SHORT_D16_HI anonymous_15037:{ *:[i32] }:$data, ?:{ *:[i32] }:$vaddr, ?:{ *:[i32] }:$offset)
      GIR_BuildMI, /*InsnID*/0, /*Opcode*/GIMT_Encode2(AMDGPU::SCRATCH_STORE_SHORT_D16_HI),
      GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/1, /*OpIdx*/1, // data
      GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/0, // vaddr
      GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/1, // offset
      GIR_AddImm8, /*InsnID*/0, /*Imm*/0,
      GIR_MergeMemOperands, /*InsnID*/0, /*NumInsns*/2, /*MergeInsnID's*/0, 1,
      GIR_ConstrainSelectedInstOperands, /*InsnID*/0,
      GIR_EraseFromParent, /*InsnID*/0,
      // GIR_Coverage, 3602,
      GIR_Done,
    // Label 1984: @129604
    GIM_Try, /*On fail goto*//*Label 1985*/ GIMT_Encode4(129695), // Rule ID 3605 //
      GIM_CheckFeatures, GIMT_Encode2(GIFBS_EnableFlatScratch_HasD16LoadStore_HasFlatScratchInsts),
      GIM_CheckMemorySizeLessThanLLT, /*MI*/0, /*MMO*/0, /*OpIdx*/0,
      GIM_CheckMemorySizeEqualTo, /*MI*/0, /*MMO*/0, /*Size*/GIMT_Encode4(1),
      GIM_CheckMemoryAddressSpace, /*MI*/0, /*MMO*/0, /*NumAddrSpace*/1, /*AddrSpace*/5,
      GIM_CheckAtomicOrdering, /*MI*/0, /*Order*/(uint8_t)AtomicOrdering::NotAtomic,
      GIM_RecordInsn, /*DefineMI*/1, /*MI*/0, /*OpIdx*/0, // MIs[1]
      GIM_CheckOpcode, /*MI*/1, GIMT_Encode2(TargetOpcode::G_LSHR),
      GIM_CheckType, /*MI*/1, /*Op*/1, /*Type*/GILLT_s32,
      GIM_CheckType, /*MI*/1, /*Op*/2, /*Type*/GILLT_s32,
      GIM_CheckConstantInt8, /*MI*/1, /*Op*/2, 16,
      GIM_CheckPointerToAny, /*MI*/0, /*Op*/1, /*SizeInBits*/0,
      GIM_CheckIsSafeToFold, /*InsnID*/1,
      GIM_CheckComplexPattern, /*MI*/0, /*Op*/1, /*Renderer*/GIMT_Encode2(0), GIMT_Encode2(GICP_gi_flat_scratch_offset),
      // (st (srl:{ *:[i32] } i32:{ *:[i32] }:$data, 16:{ *:[i32] }), (ScratchOffset:{ *:[iPTR] } VGPR_32:{ *:[i32] }:$vaddr, i32:{ *:[i32] }:$offset))<<P:Predicate_unindexedstore>><<P:Predicate_truncstore>><<P:Predicate_truncstorei8>><<P:Predicate_truncstorei8_hi16_private>>  =>  (SCRATCH_STORE_BYTE_D16_HI anonymous_15037:{ *:[i32] }:$data, ?:{ *:[i32] }:$vaddr, ?:{ *:[i32] }:$offset)
      GIR_BuildMI, /*InsnID*/0, /*Opcode*/GIMT_Encode2(AMDGPU::SCRATCH_STORE_BYTE_D16_HI),
      GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/1, /*OpIdx*/1, // data
      GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/0, // vaddr
      GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/1, // offset
      GIR_AddImm8, /*InsnID*/0, /*Imm*/0,
      GIR_MergeMemOperands, /*InsnID*/0, /*NumInsns*/2, /*MergeInsnID's*/0, 1,
      GIR_ConstrainSelectedInstOperands, /*InsnID*/0,
      GIR_EraseFromParent, /*InsnID*/0,
      // GIR_Coverage, 3605,
      GIR_Done,
    // Label 1985: @129695
    GIM_Try, /*On fail goto*//*Label 1986*/ GIMT_Encode4(129799), // Rule ID 5561 //
      GIM_CheckFeatures, GIMT_Encode2(GIFBS_DisableFlatScratch_HasD16LoadStore_HasUnrestrictedSOffset),
      GIM_CheckMemorySizeLessThanLLT, /*MI*/0, /*MMO*/0, /*OpIdx*/0,
      GIM_CheckMemorySizeEqualTo, /*MI*/0, /*MMO*/0, /*Size*/GIMT_Encode4(2),
      GIM_CheckMemoryAddressSpace, /*MI*/0, /*MMO*/0, /*NumAddrSpace*/1, /*AddrSpace*/5,
      GIM_CheckAtomicOrdering, /*MI*/0, /*Order*/(uint8_t)AtomicOrdering::NotAtomic,
      GIM_RecordInsn, /*DefineMI*/1, /*MI*/0, /*OpIdx*/0, // MIs[1]
      GIM_CheckOpcode, /*MI*/1, GIMT_Encode2(TargetOpcode::G_LSHR),
      GIM_CheckType, /*MI*/1, /*Op*/1, /*Type*/GILLT_s32,
      GIM_CheckType, /*MI*/1, /*Op*/2, /*Type*/GILLT_s32,
      GIM_CheckConstantInt8, /*MI*/1, /*Op*/2, 16,
      GIM_CheckPointerToAny, /*MI*/0, /*Op*/1, /*SizeInBits*/0,
      GIM_CheckIsSafeToFold, /*InsnID*/1,
      GIM_CheckComplexPattern, /*MI*/0, /*Op*/1, /*Renderer*/GIMT_Encode2(0), GIMT_Encode2(GICP_gi_mubuf_scratch_offen),
      // (st (srl:{ *:[i32] } i32:{ *:[i32] }:$value, 16:{ *:[i32] }), (MUBUFScratchOffen:{ *:[iPTR] } v4i32:{ *:[v4i32] }:$srsrc, i32:{ *:[i32] }:$vaddr, i32:{ *:[i32] }:$soffset, i32:{ *:[i32] }:$offset))<<P:Predicate_unindexedstore>><<P:Predicate_truncstore>><<P:Predicate_truncstorei16>><<P:Predicate_store_hi16_private>>  =>  (BUFFER_STORE_SHORT_D16_HI_OFFEN VGPR_32:{ *:[i32] }:$value, ?:{ *:[i32] }:$vaddr, ?:{ *:[v4i32] }:$srsrc, ?:{ *:[i32] }:$soffset, ?:{ *:[i32] }:$offset, 0:{ *:[i32] }, 0:{ *:[i1] })
      GIR_BuildMI, /*InsnID*/0, /*Opcode*/GIMT_Encode2(AMDGPU::BUFFER_STORE_SHORT_D16_HI_OFFEN),
      GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/1, /*OpIdx*/1, // value
      GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/1, // vaddr
      GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/0, // srsrc
      GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/2, // soffset
      GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/3, // offset
      GIR_AddImm8, /*InsnID*/0, /*Imm*/0,
      GIR_AddImm8, /*InsnID*/0, /*Imm*/0,
      GIR_MergeMemOperands, /*InsnID*/0, /*NumInsns*/2, /*MergeInsnID's*/0, 1,
      GIR_ConstrainSelectedInstOperands, /*InsnID*/0,
      GIR_EraseFromParent, /*InsnID*/0,
      // GIR_Coverage, 5561,
      GIR_Done,
    // Label 1986: @129799
    GIM_Try, /*On fail goto*//*Label 1987*/ GIMT_Encode4(129903), // Rule ID 5563 //
      GIM_CheckFeatures, GIMT_Encode2(GIFBS_DisableFlatScratch_HasD16LoadStore),
      GIM_CheckMemorySizeLessThanLLT, /*MI*/0, /*MMO*/0, /*OpIdx*/0,
      GIM_CheckMemorySizeEqualTo, /*MI*/0, /*MMO*/0, /*Size*/GIMT_Encode4(2),
      GIM_CheckMemoryAddressSpace, /*MI*/0, /*MMO*/0, /*NumAddrSpace*/1, /*AddrSpace*/5,
      GIM_CheckAtomicOrdering, /*MI*/0, /*Order*/(uint8_t)AtomicOrdering::NotAtomic,
      GIM_RecordInsn, /*DefineMI*/1, /*MI*/0, /*OpIdx*/0, // MIs[1]
      GIM_CheckOpcode, /*MI*/1, GIMT_Encode2(TargetOpcode::G_LSHR),
      GIM_CheckType, /*MI*/1, /*Op*/1, /*Type*/GILLT_s32,
      GIM_CheckType, /*MI*/1, /*Op*/2, /*Type*/GILLT_s32,
      GIM_CheckConstantInt8, /*MI*/1, /*Op*/2, 16,
      GIM_CheckPointerToAny, /*MI*/0, /*Op*/1, /*SizeInBits*/0,
      GIM_CheckIsSafeToFold, /*InsnID*/1,
      GIM_CheckComplexPattern, /*MI*/0, /*Op*/1, /*Renderer*/GIMT_Encode2(0), GIMT_Encode2(GICP_gi_mubuf_scratch_offen),
      // (st (srl:{ *:[i32] } i32:{ *:[i32] }:$value, 16:{ *:[i32] }), (MUBUFScratchOffen:{ *:[iPTR] } v4i32:{ *:[v4i32] }:$srsrc, i32:{ *:[i32] }:$vaddr, i32:{ *:[i32] }:$soffset, i32:{ *:[i32] }:$offset))<<P:Predicate_unindexedstore>><<P:Predicate_truncstore>><<P:Predicate_truncstorei16>><<P:Predicate_store_hi16_private>>  =>  (BUFFER_STORE_SHORT_D16_HI_VBUFFER_OFFEN VGPR_32:{ *:[i32] }:$value, ?:{ *:[i32] }:$vaddr, ?:{ *:[v4i32] }:$srsrc, ?:{ *:[i32] }:$soffset, ?:{ *:[i32] }:$offset, 0:{ *:[i32] }, 0:{ *:[i1] })
      GIR_BuildMI, /*InsnID*/0, /*Opcode*/GIMT_Encode2(AMDGPU::BUFFER_STORE_SHORT_D16_HI_VBUFFER_OFFEN),
      GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/1, /*OpIdx*/1, // value
      GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/1, // vaddr
      GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/0, // srsrc
      GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/2, // soffset
      GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/3, // offset
      GIR_AddImm8, /*InsnID*/0, /*Imm*/0,
      GIR_AddImm8, /*InsnID*/0, /*Imm*/0,
      GIR_MergeMemOperands, /*InsnID*/0, /*NumInsns*/2, /*MergeInsnID's*/0, 1,
      GIR_ConstrainSelectedInstOperands, /*InsnID*/0,
      GIR_EraseFromParent, /*InsnID*/0,
      // GIR_Coverage, 5563,
      GIR_Done,
    // Label 1987: @129903
    GIM_Try, /*On fail goto*//*Label 1988*/ GIMT_Encode4(130007), // Rule ID 5565 //
      GIM_CheckFeatures, GIMT_Encode2(GIFBS_DisableFlatScratch_HasD16LoadStore_HasUnrestrictedSOffset),
      GIM_CheckMemorySizeLessThanLLT, /*MI*/0, /*MMO*/0, /*OpIdx*/0,
      GIM_CheckMemorySizeEqualTo, /*MI*/0, /*MMO*/0, /*Size*/GIMT_Encode4(1),
      GIM_CheckMemoryAddressSpace, /*MI*/0, /*MMO*/0, /*NumAddrSpace*/1, /*AddrSpace*/5,
      GIM_CheckAtomicOrdering, /*MI*/0, /*Order*/(uint8_t)AtomicOrdering::NotAtomic,
      GIM_RecordInsn, /*DefineMI*/1, /*MI*/0, /*OpIdx*/0, // MIs[1]
      GIM_CheckOpcode, /*MI*/1, GIMT_Encode2(TargetOpcode::G_LSHR),
      GIM_CheckType, /*MI*/1, /*Op*/1, /*Type*/GILLT_s32,
      GIM_CheckType, /*MI*/1, /*Op*/2, /*Type*/GILLT_s32,
      GIM_CheckConstantInt8, /*MI*/1, /*Op*/2, 16,
      GIM_CheckPointerToAny, /*MI*/0, /*Op*/1, /*SizeInBits*/0,
      GIM_CheckIsSafeToFold, /*InsnID*/1,
      GIM_CheckComplexPattern, /*MI*/0, /*Op*/1, /*Renderer*/GIMT_Encode2(0), GIMT_Encode2(GICP_gi_mubuf_scratch_offen),
      // (st (srl:{ *:[i32] } i32:{ *:[i32] }:$value, 16:{ *:[i32] }), (MUBUFScratchOffen:{ *:[iPTR] } v4i32:{ *:[v4i32] }:$srsrc, i32:{ *:[i32] }:$vaddr, i32:{ *:[i32] }:$soffset, i32:{ *:[i32] }:$offset))<<P:Predicate_unindexedstore>><<P:Predicate_truncstore>><<P:Predicate_truncstorei8>><<P:Predicate_truncstorei8_hi16_private>>  =>  (BUFFER_STORE_BYTE_D16_HI_OFFEN VGPR_32:{ *:[i32] }:$value, ?:{ *:[i32] }:$vaddr, ?:{ *:[v4i32] }:$srsrc, ?:{ *:[i32] }:$soffset, ?:{ *:[i32] }:$offset, 0:{ *:[i32] }, 0:{ *:[i1] })
      GIR_BuildMI, /*InsnID*/0, /*Opcode*/GIMT_Encode2(AMDGPU::BUFFER_STORE_BYTE_D16_HI_OFFEN),
      GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/1, /*OpIdx*/1, // value
      GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/1, // vaddr
      GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/0, // srsrc
      GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/2, // soffset
      GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/3, // offset
      GIR_AddImm8, /*InsnID*/0, /*Imm*/0,
      GIR_AddImm8, /*InsnID*/0, /*Imm*/0,
      GIR_MergeMemOperands, /*InsnID*/0, /*NumInsns*/2, /*MergeInsnID's*/0, 1,
      GIR_ConstrainSelectedInstOperands, /*InsnID*/0,
      GIR_EraseFromParent, /*InsnID*/0,
      // GIR_Coverage, 5565,
      GIR_Done,
    // Label 1988: @130007
    GIM_Try, /*On fail goto*//*Label 1989*/ GIMT_Encode4(130111), // Rule ID 5567 //
      GIM_CheckFeatures, GIMT_Encode2(GIFBS_DisableFlatScratch_HasD16LoadStore),
      GIM_CheckMemorySizeLessThanLLT, /*MI*/0, /*MMO*/0, /*OpIdx*/0,
      GIM_CheckMemorySizeEqualTo, /*MI*/0, /*MMO*/0, /*Size*/GIMT_Encode4(1),
      GIM_CheckMemoryAddressSpace, /*MI*/0, /*MMO*/0, /*NumAddrSpace*/1, /*AddrSpace*/5,
      GIM_CheckAtomicOrdering, /*MI*/0, /*Order*/(uint8_t)AtomicOrdering::NotAtomic,
      GIM_RecordInsn, /*DefineMI*/1, /*MI*/0, /*OpIdx*/0, // MIs[1]
      GIM_CheckOpcode, /*MI*/1, GIMT_Encode2(TargetOpcode::G_LSHR),
      GIM_CheckType, /*MI*/1, /*Op*/1, /*Type*/GILLT_s32,
      GIM_CheckType, /*MI*/1, /*Op*/2, /*Type*/GILLT_s32,
      GIM_CheckConstantInt8, /*MI*/1, /*Op*/2, 16,
      GIM_CheckPointerToAny, /*MI*/0, /*Op*/1, /*SizeInBits*/0,
      GIM_CheckIsSafeToFold, /*InsnID*/1,
      GIM_CheckComplexPattern, /*MI*/0, /*Op*/1, /*Renderer*/GIMT_Encode2(0), GIMT_Encode2(GICP_gi_mubuf_scratch_offen),
      // (st (srl:{ *:[i32] } i32:{ *:[i32] }:$value, 16:{ *:[i32] }), (MUBUFScratchOffen:{ *:[iPTR] } v4i32:{ *:[v4i32] }:$srsrc, i32:{ *:[i32] }:$vaddr, i32:{ *:[i32] }:$soffset, i32:{ *:[i32] }:$offset))<<P:Predicate_unindexedstore>><<P:Predicate_truncstore>><<P:Predicate_truncstorei8>><<P:Predicate_truncstorei8_hi16_private>>  =>  (BUFFER_STORE_BYTE_D16_HI_VBUFFER_OFFEN VGPR_32:{ *:[i32] }:$value, ?:{ *:[i32] }:$vaddr, ?:{ *:[v4i32] }:$srsrc, ?:{ *:[i32] }:$soffset, ?:{ *:[i32] }:$offset, 0:{ *:[i32] }, 0:{ *:[i1] })
      GIR_BuildMI, /*InsnID*/0, /*Opcode*/GIMT_Encode2(AMDGPU::BUFFER_STORE_BYTE_D16_HI_VBUFFER_OFFEN),
      GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/1, /*OpIdx*/1, // value
      GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/1, // vaddr
      GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/0, // srsrc
      GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/2, // soffset
      GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/3, // offset
      GIR_AddImm8, /*InsnID*/0, /*Imm*/0,
      GIR_AddImm8, /*InsnID*/0, /*Imm*/0,
      GIR_MergeMemOperands, /*InsnID*/0, /*NumInsns*/2, /*MergeInsnID's*/0, 1,
      GIR_ConstrainSelectedInstOperands, /*InsnID*/0,
      GIR_EraseFromParent, /*InsnID*/0,
      // GIR_Coverage, 5567,
      GIR_Done,
    // Label 1989: @130111
    GIM_Try, /*On fail goto*//*Label 1990*/ GIMT_Encode4(130187), // Rule ID 5498 //
      GIM_CheckFeatures, GIMT_Encode2(GIFBS_DisableFlatScratch_HasUnrestrictedSOffset),
      GIM_CheckMemorySizeLessThanLLT, /*MI*/0, /*MMO*/0, /*OpIdx*/0,
      GIM_CheckMemorySizeEqualTo, /*MI*/0, /*MMO*/0, /*Size*/GIMT_Encode4(1),
      GIM_CheckMemoryAddressSpace, /*MI*/0, /*MMO*/0, /*NumAddrSpace*/1, /*AddrSpace*/5,
      GIM_CheckAtomicOrdering, /*MI*/0, /*Order*/(uint8_t)AtomicOrdering::NotAtomic,
      GIM_CheckPointerToAny, /*MI*/0, /*Op*/1, /*SizeInBits*/0,
      GIM_CheckComplexPattern, /*MI*/0, /*Op*/1, /*Renderer*/GIMT_Encode2(0), GIMT_Encode2(GICP_gi_mubuf_scratch_offset),
      // (st i32:{ *:[i32] }:$value, (MUBUFScratchOffset:{ *:[iPTR] } v4i32:{ *:[v4i32] }:$srsrc, i32:{ *:[i32] }:$soffset, i32:{ *:[i32] }:$offset))<<P:Predicate_unindexedstore>><<P:Predicate_truncstore>><<P:Predicate_truncstorei8>><<P:Predicate_truncstorei8_private>>  =>  (BUFFER_STORE_BYTE_OFFSET VGPR_32:{ *:[i32] }:$value, ?:{ *:[v4i32] }:$srsrc, ?:{ *:[i32] }:$soffset, ?:{ *:[i32] }:$offset, 0:{ *:[i32] }, 0:{ *:[i1] })
      GIR_BuildMI, /*InsnID*/0, /*Opcode*/GIMT_Encode2(AMDGPU::BUFFER_STORE_BYTE_OFFSET),
      GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/0, // value
      GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/0, // srsrc
      GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/1, // soffset
      GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/2, // offset
      GIR_AddImm8, /*InsnID*/0, /*Imm*/0,
      GIR_AddImm8, /*InsnID*/0, /*Imm*/0,
      GIR_MergeMemOperands, /*InsnID*/0, /*NumInsns*/1, /*MergeInsnID's*/0,
      GIR_ConstrainSelectedInstOperands, /*InsnID*/0,
      GIR_EraseFromParent, /*InsnID*/0,
      // GIR_Coverage, 5498,
      GIR_Done,
    // Label 1990: @130187
    GIM_Try, /*On fail goto*//*Label 1991*/ GIMT_Encode4(130263), // Rule ID 5500 //
      GIM_CheckFeatures, GIMT_Encode2(GIFBS_DisableFlatScratch),
      GIM_CheckMemorySizeLessThanLLT, /*MI*/0, /*MMO*/0, /*OpIdx*/0,
      GIM_CheckMemorySizeEqualTo, /*MI*/0, /*MMO*/0, /*Size*/GIMT_Encode4(1),
      GIM_CheckMemoryAddressSpace, /*MI*/0, /*MMO*/0, /*NumAddrSpace*/1, /*AddrSpace*/5,
      GIM_CheckAtomicOrdering, /*MI*/0, /*Order*/(uint8_t)AtomicOrdering::NotAtomic,
      GIM_CheckPointerToAny, /*MI*/0, /*Op*/1, /*SizeInBits*/0,
      GIM_CheckComplexPattern, /*MI*/0, /*Op*/1, /*Renderer*/GIMT_Encode2(0), GIMT_Encode2(GICP_gi_mubuf_scratch_offset),
      // (st i32:{ *:[i32] }:$value, (MUBUFScratchOffset:{ *:[iPTR] } v4i32:{ *:[v4i32] }:$srsrc, i32:{ *:[i32] }:$soffset, i32:{ *:[i32] }:$offset))<<P:Predicate_unindexedstore>><<P:Predicate_truncstore>><<P:Predicate_truncstorei8>><<P:Predicate_truncstorei8_private>>  =>  (BUFFER_STORE_BYTE_VBUFFER_OFFSET VGPR_32:{ *:[i32] }:$value, ?:{ *:[v4i32] }:$srsrc, ?:{ *:[i32] }:$soffset, ?:{ *:[i32] }:$offset, 0:{ *:[i32] }, 0:{ *:[i1] })
      GIR_BuildMI, /*InsnID*/0, /*Opcode*/GIMT_Encode2(AMDGPU::BUFFER_STORE_BYTE_VBUFFER_OFFSET),
      GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/0, // value
      GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/0, // srsrc
      GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/1, // soffset
      GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/2, // offset
      GIR_AddImm8, /*InsnID*/0, /*Imm*/0,
      GIR_AddImm8, /*InsnID*/0, /*Imm*/0,
      GIR_MergeMemOperands, /*InsnID*/0, /*NumInsns*/1, /*MergeInsnID's*/0,
      GIR_ConstrainSelectedInstOperands, /*InsnID*/0,
      GIR_EraseFromParent, /*InsnID*/0,
      // GIR_Coverage, 5500,
      GIR_Done,
    // Label 1991: @130263
    GIM_Try, /*On fail goto*//*Label 1992*/ GIMT_Encode4(130339), // Rule ID 5502 //
      GIM_CheckFeatures, GIMT_Encode2(GIFBS_DisableFlatScratch_HasUnrestrictedSOffset),
      GIM_CheckMemorySizeLessThanLLT, /*MI*/0, /*MMO*/0, /*OpIdx*/0,
      GIM_CheckMemorySizeEqualTo, /*MI*/0, /*MMO*/0, /*Size*/GIMT_Encode4(2),
      GIM_CheckMemoryAddressSpace, /*MI*/0, /*MMO*/0, /*NumAddrSpace*/1, /*AddrSpace*/5,
      GIM_CheckAtomicOrdering, /*MI*/0, /*Order*/(uint8_t)AtomicOrdering::NotAtomic,
      GIM_CheckPointerToAny, /*MI*/0, /*Op*/1, /*SizeInBits*/0,
      GIM_CheckComplexPattern, /*MI*/0, /*Op*/1, /*Renderer*/GIMT_Encode2(0), GIMT_Encode2(GICP_gi_mubuf_scratch_offset),
      // (st i32:{ *:[i32] }:$value, (MUBUFScratchOffset:{ *:[iPTR] } v4i32:{ *:[v4i32] }:$srsrc, i32:{ *:[i32] }:$soffset, i32:{ *:[i32] }:$offset))<<P:Predicate_unindexedstore>><<P:Predicate_truncstore>><<P:Predicate_truncstorei16>><<P:Predicate_truncstorei16_private>>  =>  (BUFFER_STORE_SHORT_OFFSET VGPR_32:{ *:[i32] }:$value, ?:{ *:[v4i32] }:$srsrc, ?:{ *:[i32] }:$soffset, ?:{ *:[i32] }:$offset, 0:{ *:[i32] }, 0:{ *:[i1] })
      GIR_BuildMI, /*InsnID*/0, /*Opcode*/GIMT_Encode2(AMDGPU::BUFFER_STORE_SHORT_OFFSET),
      GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/0, // value
      GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/0, // srsrc
      GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/1, // soffset
      GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/2, // offset
      GIR_AddImm8, /*InsnID*/0, /*Imm*/0,
      GIR_AddImm8, /*InsnID*/0, /*Imm*/0,
      GIR_MergeMemOperands, /*InsnID*/0, /*NumInsns*/1, /*MergeInsnID's*/0,
      GIR_ConstrainSelectedInstOperands, /*InsnID*/0,
      GIR_EraseFromParent, /*InsnID*/0,
      // GIR_Coverage, 5502,
      GIR_Done,
    // Label 1992: @130339
    GIM_Try, /*On fail goto*//*Label 1993*/ GIMT_Encode4(130415), // Rule ID 5504 //
      GIM_CheckFeatures, GIMT_Encode2(GIFBS_DisableFlatScratch),
      GIM_CheckMemorySizeLessThanLLT, /*MI*/0, /*MMO*/0, /*OpIdx*/0,
      GIM_CheckMemorySizeEqualTo, /*MI*/0, /*MMO*/0, /*Size*/GIMT_Encode4(2),
      GIM_CheckMemoryAddressSpace, /*MI*/0, /*MMO*/0, /*NumAddrSpace*/1, /*AddrSpace*/5,
      GIM_CheckAtomicOrdering, /*MI*/0, /*Order*/(uint8_t)AtomicOrdering::NotAtomic,
      GIM_CheckPointerToAny, /*MI*/0, /*Op*/1, /*SizeInBits*/0,
      GIM_CheckComplexPattern, /*MI*/0, /*Op*/1, /*Renderer*/GIMT_Encode2(0), GIMT_Encode2(GICP_gi_mubuf_scratch_offset),
      // (st i32:{ *:[i32] }:$value, (MUBUFScratchOffset:{ *:[iPTR] } v4i32:{ *:[v4i32] }:$srsrc, i32:{ *:[i32] }:$soffset, i32:{ *:[i32] }:$offset))<<P:Predicate_unindexedstore>><<P:Predicate_truncstore>><<P:Predicate_truncstorei16>><<P:Predicate_truncstorei16_private>>  =>  (BUFFER_STORE_SHORT_VBUFFER_OFFSET VGPR_32:{ *:[i32] }:$value, ?:{ *:[v4i32] }:$srsrc, ?:{ *:[i32] }:$soffset, ?:{ *:[i32] }:$offset, 0:{ *:[i32] }, 0:{ *:[i1] })
      GIR_BuildMI, /*InsnID*/0, /*Opcode*/GIMT_Encode2(AMDGPU::BUFFER_STORE_SHORT_VBUFFER_OFFSET),
      GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/0, // value
      GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/0, // srsrc
      GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/1, // soffset
      GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/2, // offset
      GIR_AddImm8, /*InsnID*/0, /*Imm*/0,
      GIR_AddImm8, /*InsnID*/0, /*Imm*/0,
      GIR_MergeMemOperands, /*InsnID*/0, /*NumInsns*/1, /*MergeInsnID's*/0,
      GIR_ConstrainSelectedInstOperands, /*InsnID*/0,
      GIR_EraseFromParent, /*InsnID*/0,
      // GIR_Coverage, 5504,
      GIR_Done,
    // Label 1993: @130415
    GIM_Try, /*On fail goto*//*Label 1994*/ GIMT_Encode4(130480), // Rule ID 5514 //
      GIM_CheckFeatures, GIMT_Encode2(GIFBS_DisableFlatScratch_HasUnrestrictedSOffset),
      GIM_CheckMemoryAddressSpace, /*MI*/0, /*MMO*/0, /*NumAddrSpace*/1, /*AddrSpace*/5,
      GIM_CheckAtomicOrdering, /*MI*/0, /*Order*/(uint8_t)AtomicOrdering::NotAtomic,
      GIM_CheckPointerToAny, /*MI*/0, /*Op*/1, /*SizeInBits*/0,
      GIM_CheckComplexPattern, /*MI*/0, /*Op*/1, /*Renderer*/GIMT_Encode2(0), GIMT_Encode2(GICP_gi_mubuf_scratch_offset),
      // (st i32:{ *:[i32] }:$value, (MUBUFScratchOffset:{ *:[iPTR] } v4i32:{ *:[v4i32] }:$srsrc, i32:{ *:[i32] }:$soffset, i32:{ *:[i32] }:$offset))<<P:Predicate_unindexedstore>><<P:Predicate_store_private>>  =>  (BUFFER_STORE_DWORD_OFFSET VGPR_32:{ *:[i32] }:$value, ?:{ *:[v4i32] }:$srsrc, ?:{ *:[i32] }:$soffset, ?:{ *:[i32] }:$offset, 0:{ *:[i32] }, 0:{ *:[i1] })
      GIR_BuildMI, /*InsnID*/0, /*Opcode*/GIMT_Encode2(AMDGPU::BUFFER_STORE_DWORD_OFFSET),
      GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/0, // value
      GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/0, // srsrc
      GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/1, // soffset
      GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/2, // offset
      GIR_AddImm8, /*InsnID*/0, /*Imm*/0,
      GIR_AddImm8, /*InsnID*/0, /*Imm*/0,
      GIR_MergeMemOperands, /*InsnID*/0, /*NumInsns*/1, /*MergeInsnID's*/0,
      GIR_ConstrainSelectedInstOperands, /*InsnID*/0,
      GIR_EraseFromParent, /*InsnID*/0,
      // GIR_Coverage, 5514,
      GIR_Done,
    // Label 1994: @130480
    GIM_Try, /*On fail goto*//*Label 1995*/ GIMT_Encode4(130545), // Rule ID 5516 //
      GIM_CheckFeatures, GIMT_Encode2(GIFBS_DisableFlatScratch),
      GIM_CheckMemoryAddressSpace, /*MI*/0, /*MMO*/0, /*NumAddrSpace*/1, /*AddrSpace*/5,
      GIM_CheckAtomicOrdering, /*MI*/0, /*Order*/(uint8_t)AtomicOrdering::NotAtomic,
      GIM_CheckPointerToAny, /*MI*/0, /*Op*/1, /*SizeInBits*/0,
      GIM_CheckComplexPattern, /*MI*/0, /*Op*/1, /*Renderer*/GIMT_Encode2(0), GIMT_Encode2(GICP_gi_mubuf_scratch_offset),
      // (st i32:{ *:[i32] }:$value, (MUBUFScratchOffset:{ *:[iPTR] } v4i32:{ *:[v4i32] }:$srsrc, i32:{ *:[i32] }:$soffset, i32:{ *:[i32] }:$offset))<<P:Predicate_unindexedstore>><<P:Predicate_store_private>>  =>  (BUFFER_STORE_DWORD_VBUFFER_OFFSET VGPR_32:{ *:[i32] }:$value, ?:{ *:[v4i32] }:$srsrc, ?:{ *:[i32] }:$soffset, ?:{ *:[i32] }:$offset, 0:{ *:[i32] }, 0:{ *:[i1] })
      GIR_BuildMI, /*InsnID*/0, /*Opcode*/GIMT_Encode2(AMDGPU::BUFFER_STORE_DWORD_VBUFFER_OFFSET),
      GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/0, // value
      GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/0, // srsrc
      GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/1, // soffset
      GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/2, // offset
      GIR_AddImm8, /*InsnID*/0, /*Imm*/0,
      GIR_AddImm8, /*InsnID*/0, /*Imm*/0,
      GIR_MergeMemOperands, /*InsnID*/0, /*NumInsns*/1, /*MergeInsnID's*/0,
      GIR_ConstrainSelectedInstOperands, /*InsnID*/0,
      GIR_EraseFromParent, /*InsnID*/0,
      // GIR_Coverage, 5516,
      GIR_Done,
    // Label 1995: @130545
    GIM_Try, /*On fail goto*//*Label 1996*/ GIMT_Encode4(130610), // Rule ID 5518 //
      GIM_CheckFeatures, GIMT_Encode2(GIFBS_DisableFlatScratch_HasUnrestrictedSOffset),
      GIM_CheckMemoryAddressSpace, /*MI*/0, /*MMO*/0, /*NumAddrSpace*/1, /*AddrSpace*/5,
      GIM_CheckAtomicOrdering, /*MI*/0, /*Order*/(uint8_t)AtomicOrdering::NotAtomic,
      GIM_CheckPointerToAny, /*MI*/0, /*Op*/1, /*SizeInBits*/0,
      GIM_CheckComplexPattern, /*MI*/0, /*Op*/1, /*Renderer*/GIMT_Encode2(0), GIMT_Encode2(GICP_gi_mubuf_scratch_offset),
      // (st f32:{ *:[f32] }:$value, (MUBUFScratchOffset:{ *:[iPTR] } v4i32:{ *:[v4i32] }:$srsrc, i32:{ *:[i32] }:$soffset, i32:{ *:[i32] }:$offset))<<P:Predicate_unindexedstore>><<P:Predicate_store_private>>  =>  (BUFFER_STORE_DWORD_OFFSET VGPR_32:{ *:[f32] }:$value, ?:{ *:[v4i32] }:$srsrc, ?:{ *:[i32] }:$soffset, ?:{ *:[i32] }:$offset, 0:{ *:[i32] }, 0:{ *:[i1] })
      GIR_BuildMI, /*InsnID*/0, /*Opcode*/GIMT_Encode2(AMDGPU::BUFFER_STORE_DWORD_OFFSET),
      GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/0, // value
      GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/0, // srsrc
      GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/1, // soffset
      GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/2, // offset
      GIR_AddImm8, /*InsnID*/0, /*Imm*/0,
      GIR_AddImm8, /*InsnID*/0, /*Imm*/0,
      GIR_MergeMemOperands, /*InsnID*/0, /*NumInsns*/1, /*MergeInsnID's*/0,
      GIR_ConstrainSelectedInstOperands, /*InsnID*/0,
      GIR_EraseFromParent, /*InsnID*/0,
      // GIR_Coverage, 5518,
      GIR_Done,
    // Label 1996: @130610
    GIM_Try, /*On fail goto*//*Label 1997*/ GIMT_Encode4(130675), // Rule ID 5520 //
      GIM_CheckFeatures, GIMT_Encode2(GIFBS_DisableFlatScratch),
      GIM_CheckMemoryAddressSpace, /*MI*/0, /*MMO*/0, /*NumAddrSpace*/1, /*AddrSpace*/5,
      GIM_CheckAtomicOrdering, /*MI*/0, /*Order*/(uint8_t)AtomicOrdering::NotAtomic,
      GIM_CheckPointerToAny, /*MI*/0, /*Op*/1, /*SizeInBits*/0,
      GIM_CheckComplexPattern, /*MI*/0, /*Op*/1, /*Renderer*/GIMT_Encode2(0), GIMT_Encode2(GICP_gi_mubuf_scratch_offset),
      // (st f32:{ *:[f32] }:$value, (MUBUFScratchOffset:{ *:[iPTR] } v4i32:{ *:[v4i32] }:$srsrc, i32:{ *:[i32] }:$soffset, i32:{ *:[i32] }:$offset))<<P:Predicate_unindexedstore>><<P:Predicate_store_private>>  =>  (BUFFER_STORE_DWORD_VBUFFER_OFFSET VGPR_32:{ *:[f32] }:$value, ?:{ *:[v4i32] }:$srsrc, ?:{ *:[i32] }:$soffset, ?:{ *:[i32] }:$offset, 0:{ *:[i32] }, 0:{ *:[i1] })
      GIR_BuildMI, /*InsnID*/0, /*Opcode*/GIMT_Encode2(AMDGPU::BUFFER_STORE_DWORD_VBUFFER_OFFSET),
      GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/0, // value
      GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/0, // srsrc
      GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/1, // soffset
      GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/2, // offset
      GIR_AddImm8, /*InsnID*/0, /*Imm*/0,
      GIR_AddImm8, /*InsnID*/0, /*Imm*/0,
      GIR_MergeMemOperands, /*InsnID*/0, /*NumInsns*/1, /*MergeInsnID's*/0,
      GIR_ConstrainSelectedInstOperands, /*InsnID*/0,
      GIR_EraseFromParent, /*InsnID*/0,
      // GIR_Coverage, 5520,
      GIR_Done,
    // Label 1997: @130675
    GIM_Try, /*On fail goto*//*Label 1998*/ GIMT_Encode4(130748), // Rule ID 3589 //
      GIM_CheckFeatures, GIMT_Encode2(GIFBS_EnableFlatScratch_HasFlatScratchInsts_HasFlatScratchSVSMode),
      GIM_CheckMemorySizeLessThanLLT, /*MI*/0, /*MMO*/0, /*OpIdx*/0,
      GIM_CheckMemorySizeEqualTo, /*MI*/0, /*MMO*/0, /*Size*/GIMT_Encode4(1),
      GIM_CheckMemoryAddressSpace, /*MI*/0, /*MMO*/0, /*NumAddrSpace*/1, /*AddrSpace*/5,
      GIM_CheckAtomicOrdering, /*MI*/0, /*Order*/(uint8_t)AtomicOrdering::NotAtomic,
      GIM_CheckPointerToAny, /*MI*/0, /*Op*/1, /*SizeInBits*/0,
      GIM_CheckComplexPattern, /*MI*/0, /*Op*/1, /*Renderer*/GIMT_Encode2(0), GIMT_Encode2(GICP_gi_flat_scratch_svaddr),
      // (st i32:{ *:[i32] }:$data, (ScratchSVAddr:{ *:[iPTR] } VGPR_32:{ *:[i32] }:$vaddr, SGPR_32:{ *:[i32] }:$saddr, i32:{ *:[i32] }:$offset))<<P:Predicate_unindexedstore>><<P:Predicate_truncstore>><<P:Predicate_truncstorei8>><<P:Predicate_truncstorei8_private>>  =>  (SCRATCH_STORE_BYTE_SVS anonymous_15037:{ *:[i32] }:$data, ?:{ *:[i32] }:$vaddr, ?:{ *:[i32] }:$saddr, ?:{ *:[i32] }:$offset)
      GIR_BuildMI, /*InsnID*/0, /*Opcode*/GIMT_Encode2(AMDGPU::SCRATCH_STORE_BYTE_SVS),
      GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/0, // data
      GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/0, // vaddr
      GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/1, // saddr
      GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/2, // offset
      GIR_AddImm8, /*InsnID*/0, /*Imm*/0,
      GIR_MergeMemOperands, /*InsnID*/0, /*NumInsns*/1, /*MergeInsnID's*/0,
      GIR_ConstrainSelectedInstOperands, /*InsnID*/0,
      GIR_EraseFromParent, /*InsnID*/0,
      // GIR_Coverage, 3589,
      GIR_Done,
    // Label 1998: @130748
    GIM_Try, /*On fail goto*//*Label 1999*/ GIMT_Encode4(130821), // Rule ID 3595 //
      GIM_CheckFeatures, GIMT_Encode2(GIFBS_EnableFlatScratch_HasFlatScratchInsts_HasFlatScratchSVSMode),
      GIM_CheckMemorySizeLessThanLLT, /*MI*/0, /*MMO*/0, /*OpIdx*/0,
      GIM_CheckMemorySizeEqualTo, /*MI*/0, /*MMO*/0, /*Size*/GIMT_Encode4(2),
      GIM_CheckMemoryAddressSpace, /*MI*/0, /*MMO*/0, /*NumAddrSpace*/1, /*AddrSpace*/5,
      GIM_CheckAtomicOrdering, /*MI*/0, /*Order*/(uint8_t)AtomicOrdering::NotAtomic,
      GIM_CheckPointerToAny, /*MI*/0, /*Op*/1, /*SizeInBits*/0,
      GIM_CheckComplexPattern, /*MI*/0, /*Op*/1, /*Renderer*/GIMT_Encode2(0), GIMT_Encode2(GICP_gi_flat_scratch_svaddr),
      // (st i32:{ *:[i32] }:$data, (ScratchSVAddr:{ *:[iPTR] } VGPR_32:{ *:[i32] }:$vaddr, SGPR_32:{ *:[i32] }:$saddr, i32:{ *:[i32] }:$offset))<<P:Predicate_unindexedstore>><<P:Predicate_truncstore>><<P:Predicate_truncstorei16>><<P:Predicate_truncstorei16_private>>  =>  (SCRATCH_STORE_SHORT_SVS anonymous_15037:{ *:[i32] }:$data, ?:{ *:[i32] }:$vaddr, ?:{ *:[i32] }:$saddr, ?:{ *:[i32] }:$offset)
      GIR_BuildMI, /*InsnID*/0, /*Opcode*/GIMT_Encode2(AMDGPU::SCRATCH_STORE_SHORT_SVS),
      GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/0, // data
      GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/0, // vaddr
      GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/1, // saddr
      GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/2, // offset
      GIR_AddImm8, /*InsnID*/0, /*Imm*/0,
      GIR_MergeMemOperands, /*InsnID*/0, /*NumInsns*/1, /*MergeInsnID's*/0,
      GIR_ConstrainSelectedInstOperands, /*InsnID*/0,
      GIR_EraseFromParent, /*InsnID*/0,
      // GIR_Coverage, 3595,
      GIR_Done,
    // Label 1999: @130821
    GIM_Try, /*On fail goto*//*Label 2000*/ GIMT_Encode4(130883), // Rule ID 2964 //
      GIM_CheckFeatures, GIMT_Encode2(GIFBS_EnableFlatScratch_HasFlatScratchInsts_HasFlatScratchSVSMode),
      GIM_CheckMemoryAddressSpace, /*MI*/0, /*MMO*/0, /*NumAddrSpace*/1, /*AddrSpace*/5,
      GIM_CheckAtomicOrdering, /*MI*/0, /*Order*/(uint8_t)AtomicOrdering::NotAtomic,
      GIM_CheckPointerToAny, /*MI*/0, /*Op*/1, /*SizeInBits*/0,
      GIM_CheckComplexPattern, /*MI*/0, /*Op*/1, /*Renderer*/GIMT_Encode2(0), GIMT_Encode2(GICP_gi_flat_scratch_svaddr),
      // (st i32:{ *:[i32] }:$data, (ScratchSVAddr:{ *:[iPTR] } VGPR_32:{ *:[i32] }:$vaddr, SGPR_32:{ *:[i32] }:$saddr, i32:{ *:[i32] }:$offset))<<P:Predicate_unindexedstore>><<P:Predicate_store_private>>  =>  (SCRATCH_STORE_DWORD_SVS anonymous_15037:{ *:[i32] }:$data, ?:{ *:[i32] }:$vaddr, ?:{ *:[i32] }:$saddr, ?:{ *:[i32] }:$offset)
      GIR_BuildMI, /*InsnID*/0, /*Opcode*/GIMT_Encode2(AMDGPU::SCRATCH_STORE_DWORD_SVS),
      GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/0, // data
      GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/0, // vaddr
      GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/1, // saddr
      GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/2, // offset
      GIR_AddImm8, /*InsnID*/0, /*Imm*/0,
      GIR_MergeMemOperands, /*InsnID*/0, /*NumInsns*/1, /*MergeInsnID's*/0,
      GIR_ConstrainSelectedInstOperands, /*InsnID*/0,
      GIR_EraseFromParent, /*InsnID*/0,
      // GIR_Coverage, 2964,
      GIR_Done,
    // Label 2000: @130883
    GIM_Try, /*On fail goto*//*Label 2001*/ GIMT_Encode4(130945), // Rule ID 3439 //
      GIM_CheckFeatures, GIMT_Encode2(GIFBS_EnableFlatScratch_HasFlatScratchInsts_HasFlatScratchSVSMode),
      GIM_CheckMemoryAddressSpace, /*MI*/0, /*MMO*/0, /*NumAddrSpace*/1, /*AddrSpace*/5,
      GIM_CheckAtomicOrdering, /*MI*/0, /*Order*/(uint8_t)AtomicOrdering::NotAtomic,
      GIM_CheckPointerToAny, /*MI*/0, /*Op*/1, /*SizeInBits*/0,
      GIM_CheckComplexPattern, /*MI*/0, /*Op*/1, /*Renderer*/GIMT_Encode2(0), GIMT_Encode2(GICP_gi_flat_scratch_svaddr),
      // (st f32:{ *:[f32] }:$data, (ScratchSVAddr:{ *:[iPTR] } VGPR_32:{ *:[i32] }:$vaddr, SGPR_32:{ *:[i32] }:$saddr, i32:{ *:[i32] }:$offset))<<P:Predicate_unindexedstore>><<P:Predicate_store_private>>  =>  (SCRATCH_STORE_DWORD_SVS anonymous_15037:{ *:[f32] }:$data, ?:{ *:[i32] }:$vaddr, ?:{ *:[i32] }:$saddr, ?:{ *:[i32] }:$offset)
      GIR_BuildMI, /*InsnID*/0, /*Opcode*/GIMT_Encode2(AMDGPU::SCRATCH_STORE_DWORD_SVS),
      GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/0, // data
      GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/0, // vaddr
      GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/1, // saddr
      GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/2, // offset
      GIR_AddImm8, /*InsnID*/0, /*Imm*/0,
      GIR_MergeMemOperands, /*InsnID*/0, /*NumInsns*/1, /*MergeInsnID's*/0,
      GIR_ConstrainSelectedInstOperands, /*InsnID*/0,
      GIR_EraseFromParent, /*InsnID*/0,
      // GIR_Coverage, 3439,
      GIR_Done,
    // Label 2001: @130945
    GIM_Try, /*On fail goto*//*Label 2002*/ GIMT_Encode4(131013), // Rule ID 3588 //
      GIM_CheckFeatures, GIMT_Encode2(GIFBS_EnableFlatScratch_HasFlatScratchInsts),
      GIM_CheckMemorySizeLessThanLLT, /*MI*/0, /*MMO*/0, /*OpIdx*/0,
      GIM_CheckMemorySizeEqualTo, /*MI*/0, /*MMO*/0, /*Size*/GIMT_Encode4(1),
      GIM_CheckMemoryAddressSpace, /*MI*/0, /*MMO*/0, /*NumAddrSpace*/1, /*AddrSpace*/5,
      GIM_CheckAtomicOrdering, /*MI*/0, /*Order*/(uint8_t)AtomicOrdering::NotAtomic,
      GIM_CheckPointerToAny, /*MI*/0, /*Op*/1, /*SizeInBits*/0,
      GIM_CheckComplexPattern, /*MI*/0, /*Op*/1, /*Renderer*/GIMT_Encode2(0), GIMT_Encode2(GICP_gi_flat_scratch_saddr),
      // (st i32:{ *:[i32] }:$data, (ScratchSAddr:{ *:[iPTR] } SGPR_32:{ *:[i32] }:$saddr, i32:{ *:[i32] }:$offset))<<P:Predicate_unindexedstore>><<P:Predicate_truncstore>><<P:Predicate_truncstorei8>><<P:Predicate_truncstorei8_private>>  =>  (SCRATCH_STORE_BYTE_SADDR anonymous_15037:{ *:[i32] }:$data, ?:{ *:[i32] }:$saddr, ?:{ *:[i32] }:$offset)
      GIR_BuildMI, /*InsnID*/0, /*Opcode*/GIMT_Encode2(AMDGPU::SCRATCH_STORE_BYTE_SADDR),
      GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/0, // data
      GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/0, // saddr
      GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/1, // offset
      GIR_AddImm8, /*InsnID*/0, /*Imm*/0,
      GIR_MergeMemOperands, /*InsnID*/0, /*NumInsns*/1, /*MergeInsnID's*/0,
      GIR_ConstrainSelectedInstOperands, /*InsnID*/0,
      GIR_EraseFromParent, /*InsnID*/0,
      // GIR_Coverage, 3588,
      GIR_Done,
    // Label 2002: @131013
    GIM_Try, /*On fail goto*//*Label 2003*/ GIMT_Encode4(131081), // Rule ID 3594 //
      GIM_CheckFeatures, GIMT_Encode2(GIFBS_EnableFlatScratch_HasFlatScratchInsts),
      GIM_CheckMemorySizeLessThanLLT, /*MI*/0, /*MMO*/0, /*OpIdx*/0,
      GIM_CheckMemorySizeEqualTo, /*MI*/0, /*MMO*/0, /*Size*/GIMT_Encode4(2),
      GIM_CheckMemoryAddressSpace, /*MI*/0, /*MMO*/0, /*NumAddrSpace*/1, /*AddrSpace*/5,
      GIM_CheckAtomicOrdering, /*MI*/0, /*Order*/(uint8_t)AtomicOrdering::NotAtomic,
      GIM_CheckPointerToAny, /*MI*/0, /*Op*/1, /*SizeInBits*/0,
      GIM_CheckComplexPattern, /*MI*/0, /*Op*/1, /*Renderer*/GIMT_Encode2(0), GIMT_Encode2(GICP_gi_flat_scratch_saddr),
      // (st i32:{ *:[i32] }:$data, (ScratchSAddr:{ *:[iPTR] } SGPR_32:{ *:[i32] }:$saddr, i32:{ *:[i32] }:$offset))<<P:Predicate_unindexedstore>><<P:Predicate_truncstore>><<P:Predicate_truncstorei16>><<P:Predicate_truncstorei16_private>>  =>  (SCRATCH_STORE_SHORT_SADDR anonymous_15037:{ *:[i32] }:$data, ?:{ *:[i32] }:$saddr, ?:{ *:[i32] }:$offset)
      GIR_BuildMI, /*InsnID*/0, /*Opcode*/GIMT_Encode2(AMDGPU::SCRATCH_STORE_SHORT_SADDR),
      GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/0, // data
      GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/0, // saddr
      GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/1, // offset
      GIR_AddImm8, /*InsnID*/0, /*Imm*/0,
      GIR_MergeMemOperands, /*InsnID*/0, /*NumInsns*/1, /*MergeInsnID's*/0,
      GIR_ConstrainSelectedInstOperands, /*InsnID*/0,
      GIR_EraseFromParent, /*InsnID*/0,
      // GIR_Coverage, 3594,
      GIR_Done,
    // Label 2003: @131081
    GIM_Try, /*On fail goto*//*Label 2004*/ GIMT_Encode4(131138), // Rule ID 2963 //
      GIM_CheckFeatures, GIMT_Encode2(GIFBS_EnableFlatScratch_HasFlatScratchInsts),
      GIM_CheckMemoryAddressSpace, /*MI*/0, /*MMO*/0, /*NumAddrSpace*/1, /*AddrSpace*/5,
      GIM_CheckAtomicOrdering, /*MI*/0, /*Order*/(uint8_t)AtomicOrdering::NotAtomic,
      GIM_CheckPointerToAny, /*MI*/0, /*Op*/1, /*SizeInBits*/0,
      GIM_CheckComplexPattern, /*MI*/0, /*Op*/1, /*Renderer*/GIMT_Encode2(0), GIMT_Encode2(GICP_gi_flat_scratch_saddr),
      // (st i32:{ *:[i32] }:$data, (ScratchSAddr:{ *:[iPTR] } SGPR_32:{ *:[i32] }:$saddr, i32:{ *:[i32] }:$offset))<<P:Predicate_unindexedstore>><<P:Predicate_store_private>>  =>  (SCRATCH_STORE_DWORD_SADDR anonymous_15037:{ *:[i32] }:$data, ?:{ *:[i32] }:$saddr, ?:{ *:[i32] }:$offset)
      GIR_BuildMI, /*InsnID*/0, /*Opcode*/GIMT_Encode2(AMDGPU::SCRATCH_STORE_DWORD_SADDR),
      GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/0, // data
      GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/0, // saddr
      GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/1, // offset
      GIR_AddImm8, /*InsnID*/0, /*Imm*/0,
      GIR_MergeMemOperands, /*InsnID*/0, /*NumInsns*/1, /*MergeInsnID's*/0,
      GIR_ConstrainSelectedInstOperands, /*InsnID*/0,
      GIR_EraseFromParent, /*InsnID*/0,
      // GIR_Coverage, 2963,
      GIR_Done,
    // Label 2004: @131138
    GIM_Try, /*On fail goto*//*Label 2005*/ GIMT_Encode4(131195), // Rule ID 3438 //
      GIM_CheckFeatures, GIMT_Encode2(GIFBS_EnableFlatScratch_HasFlatScratchInsts),
      GIM_CheckMemoryAddressSpace, /*MI*/0, /*MMO*/0, /*NumAddrSpace*/1, /*AddrSpace*/5,
      GIM_CheckAtomicOrdering, /*MI*/0, /*Order*/(uint8_t)AtomicOrdering::NotAtomic,
      GIM_CheckPointerToAny, /*MI*/0, /*Op*/1, /*SizeInBits*/0,
      GIM_CheckComplexPattern, /*MI*/0, /*Op*/1, /*Renderer*/GIMT_Encode2(0), GIMT_Encode2(GICP_gi_flat_scratch_saddr),
      // (st f32:{ *:[f32] }:$data, (ScratchSAddr:{ *:[iPTR] } SGPR_32:{ *:[i32] }:$saddr, i32:{ *:[i32] }:$offset))<<P:Predicate_unindexedstore>><<P:Predicate_store_private>>  =>  (SCRATCH_STORE_DWORD_SADDR anonymous_15037:{ *:[f32] }:$data, ?:{ *:[i32] }:$saddr, ?:{ *:[i32] }:$offset)
      GIR_BuildMI, /*InsnID*/0, /*Opcode*/GIMT_Encode2(AMDGPU::SCRATCH_STORE_DWORD_SADDR),
      GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/0, // data
      GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/0, // saddr
      GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/1, // offset
      GIR_AddImm8, /*InsnID*/0, /*Imm*/0,
      GIR_MergeMemOperands, /*InsnID*/0, /*NumInsns*/1, /*MergeInsnID's*/0,
      GIR_ConstrainSelectedInstOperands, /*InsnID*/0,
      GIR_EraseFromParent, /*InsnID*/0,
      // GIR_Coverage, 3438,
      GIR_Done,
    // Label 2005: @131195
    GIM_Try, /*On fail goto*//*Label 2006*/ GIMT_Encode4(131263), // Rule ID 3587 //
      GIM_CheckFeatures, GIMT_Encode2(GIFBS_EnableFlatScratch_HasFlatScratchInsts),
      GIM_CheckMemorySizeLessThanLLT, /*MI*/0, /*MMO*/0, /*OpIdx*/0,
      GIM_CheckMemorySizeEqualTo, /*MI*/0, /*MMO*/0, /*Size*/GIMT_Encode4(1),
      GIM_CheckMemoryAddressSpace, /*MI*/0, /*MMO*/0, /*NumAddrSpace*/1, /*AddrSpace*/5,
      GIM_CheckAtomicOrdering, /*MI*/0, /*Order*/(uint8_t)AtomicOrdering::NotAtomic,
      GIM_CheckPointerToAny, /*MI*/0, /*Op*/1, /*SizeInBits*/0,
      GIM_CheckComplexPattern, /*MI*/0, /*Op*/1, /*Renderer*/GIMT_Encode2(0), GIMT_Encode2(GICP_gi_flat_scratch_offset),
      // (st i32:{ *:[i32] }:$data, (ScratchOffset:{ *:[iPTR] } VGPR_32:{ *:[i32] }:$vaddr, i32:{ *:[i32] }:$offset))<<P:Predicate_unindexedstore>><<P:Predicate_truncstore>><<P:Predicate_truncstorei8>><<P:Predicate_truncstorei8_private>>  =>  (SCRATCH_STORE_BYTE anonymous_15037:{ *:[i32] }:$data, ?:{ *:[i32] }:$vaddr, ?:{ *:[i32] }:$offset)
      GIR_BuildMI, /*InsnID*/0, /*Opcode*/GIMT_Encode2(AMDGPU::SCRATCH_STORE_BYTE),
      GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/0, // data
      GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/0, // vaddr
      GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/1, // offset
      GIR_AddImm8, /*InsnID*/0, /*Imm*/0,
      GIR_MergeMemOperands, /*InsnID*/0, /*NumInsns*/1, /*MergeInsnID's*/0,
      GIR_ConstrainSelectedInstOperands, /*InsnID*/0,
      GIR_EraseFromParent, /*InsnID*/0,
      // GIR_Coverage, 3587,
      GIR_Done,
    // Label 2006: @131263
    GIM_Try, /*On fail goto*//*Label 2007*/ GIMT_Encode4(131331), // Rule ID 3593 //
      GIM_CheckFeatures, GIMT_Encode2(GIFBS_EnableFlatScratch_HasFlatScratchInsts),
      GIM_CheckMemorySizeLessThanLLT, /*MI*/0, /*MMO*/0, /*OpIdx*/0,
      GIM_CheckMemorySizeEqualTo, /*MI*/0, /*MMO*/0, /*Size*/GIMT_Encode4(2),
      GIM_CheckMemoryAddressSpace, /*MI*/0, /*MMO*/0, /*NumAddrSpace*/1, /*AddrSpace*/5,
      GIM_CheckAtomicOrdering, /*MI*/0, /*Order*/(uint8_t)AtomicOrdering::NotAtomic,
      GIM_CheckPointerToAny, /*MI*/0, /*Op*/1, /*SizeInBits*/0,
      GIM_CheckComplexPattern, /*MI*/0, /*Op*/1, /*Renderer*/GIMT_Encode2(0), GIMT_Encode2(GICP_gi_flat_scratch_offset),
      // (st i32:{ *:[i32] }:$data, (ScratchOffset:{ *:[iPTR] } VGPR_32:{ *:[i32] }:$vaddr, i32:{ *:[i32] }:$offset))<<P:Predicate_unindexedstore>><<P:Predicate_truncstore>><<P:Predicate_truncstorei16>><<P:Predicate_truncstorei16_private>>  =>  (SCRATCH_STORE_SHORT anonymous_15037:{ *:[i32] }:$data, ?:{ *:[i32] }:$vaddr, ?:{ *:[i32] }:$offset)
      GIR_BuildMI, /*InsnID*/0, /*Opcode*/GIMT_Encode2(AMDGPU::SCRATCH_STORE_SHORT),
      GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/0, // data
      GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/0, // vaddr
      GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/1, // offset
      GIR_AddImm8, /*InsnID*/0, /*Imm*/0,
      GIR_MergeMemOperands, /*InsnID*/0, /*NumInsns*/1, /*MergeInsnID's*/0,
      GIR_ConstrainSelectedInstOperands, /*InsnID*/0,
      GIR_EraseFromParent, /*InsnID*/0,
      // GIR_Coverage, 3593,
      GIR_Done,
    // Label 2007: @131331
    GIM_Try, /*On fail goto*//*Label 2008*/ GIMT_Encode4(131388), // Rule ID 2962 //
      GIM_CheckFeatures, GIMT_Encode2(GIFBS_EnableFlatScratch_HasFlatScratchInsts),
      GIM_CheckMemoryAddressSpace, /*MI*/0, /*MMO*/0, /*NumAddrSpace*/1, /*AddrSpace*/5,
      GIM_CheckAtomicOrdering, /*MI*/0, /*Order*/(uint8_t)AtomicOrdering::NotAtomic,
      GIM_CheckPointerToAny, /*MI*/0, /*Op*/1, /*SizeInBits*/0,
      GIM_CheckComplexPattern, /*MI*/0, /*Op*/1, /*Renderer*/GIMT_Encode2(0), GIMT_Encode2(GICP_gi_flat_scratch_offset),
      // (st i32:{ *:[i32] }:$data, (ScratchOffset:{ *:[iPTR] } VGPR_32:{ *:[i32] }:$vaddr, i32:{ *:[i32] }:$offset))<<P:Predicate_unindexedstore>><<P:Predicate_store_private>>  =>  (SCRATCH_STORE_DWORD anonymous_15037:{ *:[i32] }:$data, ?:{ *:[i32] }:$vaddr, ?:{ *:[i32] }:$offset)
      GIR_BuildMI, /*InsnID*/0, /*Opcode*/GIMT_Encode2(AMDGPU::SCRATCH_STORE_DWORD),
      GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/0, // data
      GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/0, // vaddr
      GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/1, // offset
      GIR_AddImm8, /*InsnID*/0, /*Imm*/0,
      GIR_MergeMemOperands, /*InsnID*/0, /*NumInsns*/1, /*MergeInsnID's*/0,
      GIR_ConstrainSelectedInstOperands, /*InsnID*/0,
      GIR_EraseFromParent, /*InsnID*/0,
      // GIR_Coverage, 2962,
      GIR_Done,
    // Label 2008: @131388
    GIM_Try, /*On fail goto*//*Label 2009*/ GIMT_Encode4(131445), // Rule ID 3437 //
      GIM_CheckFeatures, GIMT_Encode2(GIFBS_EnableFlatScratch_HasFlatScratchInsts),
      GIM_CheckMemoryAddressSpace, /*MI*/0, /*MMO*/0, /*NumAddrSpace*/1, /*AddrSpace*/5,
      GIM_CheckAtomicOrdering, /*MI*/0, /*Order*/(uint8_t)AtomicOrdering::NotAtomic,
      GIM_CheckPointerToAny, /*MI*/0, /*Op*/1, /*SizeInBits*/0,
      GIM_CheckComplexPattern, /*MI*/0, /*Op*/1, /*Renderer*/GIMT_Encode2(0), GIMT_Encode2(GICP_gi_flat_scratch_offset),
      // (st f32:{ *:[f32] }:$data, (ScratchOffset:{ *:[iPTR] } VGPR_32:{ *:[i32] }:$vaddr, i32:{ *:[i32] }:$offset))<<P:Predicate_unindexedstore>><<P:Predicate_store_private>>  =>  (SCRATCH_STORE_DWORD anonymous_15037:{ *:[f32] }:$data, ?:{ *:[i32] }:$vaddr, ?:{ *:[i32] }:$offset)
      GIR_BuildMI, /*InsnID*/0, /*Opcode*/GIMT_Encode2(AMDGPU::SCRATCH_STORE_DWORD),
      GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/0, // data
      GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/0, // vaddr
      GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/1, // offset
      GIR_AddImm8, /*InsnID*/0, /*Imm*/0,
      GIR_MergeMemOperands, /*InsnID*/0, /*NumInsns*/1, /*MergeInsnID's*/0,
      GIR_ConstrainSelectedInstOperands, /*InsnID*/0,
      GIR_EraseFromParent, /*InsnID*/0,
      // GIR_Coverage, 3437,
      GIR_Done,
    // Label 2009: @131445
    GIM_Try, /*On fail goto*//*Label 2010*/ GIMT_Encode4(131536), // Rule ID 6669 //
      GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasD16LoadStore),
      GIM_CheckMemorySizeLessThanLLT, /*MI*/0, /*MMO*/0, /*OpIdx*/0,
      GIM_CheckMemorySizeEqualTo, /*MI*/0, /*MMO*/0, /*Size*/GIMT_Encode4(2),
      GIM_CheckMemoryAddressSpace, /*MI*/0, /*MMO*/0, /*NumAddrSpace*/1, /*AddrSpace*/3,
      GIM_CheckAtomicOrdering, /*MI*/0, /*Order*/(uint8_t)AtomicOrdering::NotAtomic,
      GIM_RecordInsn, /*DefineMI*/1, /*MI*/0, /*OpIdx*/0, // MIs[1]
      GIM_CheckOpcode, /*MI*/1, GIMT_Encode2(TargetOpcode::G_LSHR),
      GIM_CheckType, /*MI*/1, /*Op*/1, /*Type*/GILLT_s32,
      GIM_CheckType, /*MI*/1, /*Op*/2, /*Type*/GILLT_s32,
      GIM_CheckConstantInt8, /*MI*/1, /*Op*/2, 16,
      GIM_CheckPointerToAny, /*MI*/0, /*Op*/1, /*SizeInBits*/0,
      GIM_CheckIsSafeToFold, /*InsnID*/1,
      GIM_CheckComplexPattern, /*MI*/0, /*Op*/1, /*Renderer*/GIMT_Encode2(0), GIMT_Encode2(GICP_gi_ds_1addr_1offset),
      // (st (srl:{ *:[i32] } i32:{ *:[i32] }:$value, 16:{ *:[i32] }), (DS1Addr1Offset:{ *:[iPTR] } i32:{ *:[i32] }:$ptr, i32:{ *:[i32] }:$offset))<<P:Predicate_unindexedstore>><<P:Predicate_truncstore>><<P:Predicate_truncstorei16>><<P:Predicate_store_hi16_local>>  =>  (DS_WRITE_B16_D16_HI ?:{ *:[i32] }:$ptr, anonymous_15037:{ *:[i32] }:$value, offset:{ *:[i32] }:$offset, 0:{ *:[i1] })
      GIR_BuildMI, /*InsnID*/0, /*Opcode*/GIMT_Encode2(AMDGPU::DS_WRITE_B16_D16_HI),
      GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/0, // ptr
      GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/1, /*OpIdx*/1, // value
      GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/1, // offset
      GIR_AddImm8, /*InsnID*/0, /*Imm*/0,
      GIR_MergeMemOperands, /*InsnID*/0, /*NumInsns*/2, /*MergeInsnID's*/0, 1,
      GIR_ConstrainSelectedInstOperands, /*InsnID*/0,
      GIR_EraseFromParent, /*InsnID*/0,
      // GIR_Coverage, 6669,
      GIR_Done,
    // Label 2010: @131536
    GIM_Try, /*On fail goto*//*Label 2011*/ GIMT_Encode4(131627), // Rule ID 6670 //
      GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasD16LoadStore),
      GIM_CheckMemorySizeLessThanLLT, /*MI*/0, /*MMO*/0, /*OpIdx*/0,
      GIM_CheckMemorySizeEqualTo, /*MI*/0, /*MMO*/0, /*Size*/GIMT_Encode4(1),
      GIM_CheckMemoryAddressSpace, /*MI*/0, /*MMO*/0, /*NumAddrSpace*/1, /*AddrSpace*/3,
      GIM_CheckAtomicOrdering, /*MI*/0, /*Order*/(uint8_t)AtomicOrdering::NotAtomic,
      GIM_RecordInsn, /*DefineMI*/1, /*MI*/0, /*OpIdx*/0, // MIs[1]
      GIM_CheckOpcode, /*MI*/1, GIMT_Encode2(TargetOpcode::G_LSHR),
      GIM_CheckType, /*MI*/1, /*Op*/1, /*Type*/GILLT_s32,
      GIM_CheckType, /*MI*/1, /*Op*/2, /*Type*/GILLT_s32,
      GIM_CheckConstantInt8, /*MI*/1, /*Op*/2, 16,
      GIM_CheckPointerToAny, /*MI*/0, /*Op*/1, /*SizeInBits*/0,
      GIM_CheckIsSafeToFold, /*InsnID*/1,
      GIM_CheckComplexPattern, /*MI*/0, /*Op*/1, /*Renderer*/GIMT_Encode2(0), GIMT_Encode2(GICP_gi_ds_1addr_1offset),
      // (st (srl:{ *:[i32] } i32:{ *:[i32] }:$value, 16:{ *:[i32] }), (DS1Addr1Offset:{ *:[iPTR] } i32:{ *:[i32] }:$ptr, i32:{ *:[i32] }:$offset))<<P:Predicate_unindexedstore>><<P:Predicate_truncstore>><<P:Predicate_truncstorei8>><<P:Predicate_truncstorei8_hi16_local>>  =>  (DS_WRITE_B8_D16_HI ?:{ *:[i32] }:$ptr, anonymous_15037:{ *:[i32] }:$value, offset:{ *:[i32] }:$offset, 0:{ *:[i1] })
      GIR_BuildMI, /*InsnID*/0, /*Opcode*/GIMT_Encode2(AMDGPU::DS_WRITE_B8_D16_HI),
      GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/0, // ptr
      GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/1, /*OpIdx*/1, // value
      GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/1, // offset
      GIR_AddImm8, /*InsnID*/0, /*Imm*/0,
      GIR_MergeMemOperands, /*InsnID*/0, /*NumInsns*/2, /*MergeInsnID's*/0, 1,
      GIR_ConstrainSelectedInstOperands, /*InsnID*/0,
      GIR_EraseFromParent, /*InsnID*/0,
      // GIR_Coverage, 6670,
      GIR_Done,
    // Label 2011: @131627
    GIM_Try, /*On fail goto*//*Label 2012*/ GIMT_Encode4(131704), // Rule ID 5481 //
      GIM_CheckFeatures, GIMT_Encode2(GIFBS_isGFX6GFX7),
      GIM_CheckMemorySizeEqualTo, /*MI*/0, /*MMO*/0, /*Size*/GIMT_Encode4(1),
      GIM_CheckMemoryAddressSpace, /*MI*/0, /*MMO*/0, /*NumAddrSpace*/1, /*AddrSpace*/1,
      GIM_CheckAtomicOrderingOrStrongerThan, /*MI*/0, /*Order*/(uint8_t)AtomicOrdering::Unordered,
      GIM_CheckPointerToAny, /*MI*/0, /*Op*/1, /*SizeInBits*/0,
      GIM_CheckComplexPattern, /*MI*/0, /*Op*/1, /*Renderer*/GIMT_Encode2(0), GIMT_Encode2(GICP_gi_mubuf_addr64),
      // (atomic_store i32:{ *:[i32] }:$val, (MUBUFAddr64:{ *:[iPTR] } v4i32:{ *:[v4i32] }:$srsrc, i64:{ *:[i64] }:$vaddr, i32:{ *:[i32] }:$soffset, i32:{ *:[i32] }:$offset))<<P:Predicate_atomic_store_8>><<P:Predicate_atomic_store_8_global>>  =>  (BUFFER_STORE_BYTE_ADDR64 ?:{ *:[i32] }:$val, ?:{ *:[i64] }:$vaddr, ?:{ *:[v4i32] }:$srsrc, ?:{ *:[i32] }:$soffset, ?:{ *:[i32] }:$offset)
      GIR_BuildMI, /*InsnID*/0, /*Opcode*/GIMT_Encode2(AMDGPU::BUFFER_STORE_BYTE_ADDR64),
      GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/0, // val
      GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/1, // vaddr
      GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/0, // srsrc
      GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/2, // soffset
      GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/3, // offset
      GIR_AddImm8, /*InsnID*/0, /*Imm*/0,
      GIR_AddImm8, /*InsnID*/0, /*Imm*/0,
      GIR_MergeMemOperands, /*InsnID*/0, /*NumInsns*/1, /*MergeInsnID's*/0,
      GIR_ConstrainSelectedInstOperands, /*InsnID*/0,
      GIR_EraseFromParent, /*InsnID*/0,
      // GIR_Coverage, 5481,
      GIR_Done,
    // Label 2012: @131704
    GIM_Try, /*On fail goto*//*Label 2013*/ GIMT_Encode4(131781), // Rule ID 5485 //
      GIM_CheckFeatures, GIMT_Encode2(GIFBS_isGFX6GFX7),
      GIM_CheckMemorySizeEqualTo, /*MI*/0, /*MMO*/0, /*Size*/GIMT_Encode4(2),
      GIM_CheckMemoryAddressSpace, /*MI*/0, /*MMO*/0, /*NumAddrSpace*/1, /*AddrSpace*/1,
      GIM_CheckAtomicOrderingOrStrongerThan, /*MI*/0, /*Order*/(uint8_t)AtomicOrdering::Unordered,
      GIM_CheckPointerToAny, /*MI*/0, /*Op*/1, /*SizeInBits*/0,
      GIM_CheckComplexPattern, /*MI*/0, /*Op*/1, /*Renderer*/GIMT_Encode2(0), GIMT_Encode2(GICP_gi_mubuf_addr64),
      // (atomic_store i32:{ *:[i32] }:$val, (MUBUFAddr64:{ *:[iPTR] } v4i32:{ *:[v4i32] }:$srsrc, i64:{ *:[i64] }:$vaddr, i32:{ *:[i32] }:$soffset, i32:{ *:[i32] }:$offset))<<P:Predicate_atomic_store_16>><<P:Predicate_atomic_store_16_global>>  =>  (BUFFER_STORE_SHORT_ADDR64 ?:{ *:[i32] }:$val, ?:{ *:[i64] }:$vaddr, ?:{ *:[v4i32] }:$srsrc, ?:{ *:[i32] }:$soffset, ?:{ *:[i32] }:$offset)
      GIR_BuildMI, /*InsnID*/0, /*Opcode*/GIMT_Encode2(AMDGPU::BUFFER_STORE_SHORT_ADDR64),
      GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/0, // val
      GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/1, // vaddr
      GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/0, // srsrc
      GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/2, // soffset
      GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/3, // offset
      GIR_AddImm8, /*InsnID*/0, /*Imm*/0,
      GIR_AddImm8, /*InsnID*/0, /*Imm*/0,
      GIR_MergeMemOperands, /*InsnID*/0, /*NumInsns*/1, /*MergeInsnID's*/0,
      GIR_ConstrainSelectedInstOperands, /*InsnID*/0,
      GIR_EraseFromParent, /*InsnID*/0,
      // GIR_Coverage, 5485,
      GIR_Done,
    // Label 2013: @131781
    GIM_Try, /*On fail goto*//*Label 2014*/ GIMT_Encode4(131858), // Rule ID 5489 //
      GIM_CheckFeatures, GIMT_Encode2(GIFBS_isGFX6GFX7),
      GIM_CheckMemorySizeEqualTo, /*MI*/0, /*MMO*/0, /*Size*/GIMT_Encode4(4),
      GIM_CheckMemoryAddressSpace, /*MI*/0, /*MMO*/0, /*NumAddrSpace*/1, /*AddrSpace*/1,
      GIM_CheckAtomicOrderingOrStrongerThan, /*MI*/0, /*Order*/(uint8_t)AtomicOrdering::Unordered,
      GIM_CheckPointerToAny, /*MI*/0, /*Op*/1, /*SizeInBits*/0,
      GIM_CheckComplexPattern, /*MI*/0, /*Op*/1, /*Renderer*/GIMT_Encode2(0), GIMT_Encode2(GICP_gi_mubuf_addr64),
      // (atomic_store i32:{ *:[i32] }:$val, (MUBUFAddr64:{ *:[iPTR] } v4i32:{ *:[v4i32] }:$srsrc, i64:{ *:[i64] }:$vaddr, i32:{ *:[i32] }:$soffset, i32:{ *:[i32] }:$offset))<<P:Predicate_atomic_store_32>><<P:Predicate_atomic_store_32_global>>  =>  (BUFFER_STORE_DWORD_ADDR64 ?:{ *:[i32] }:$val, ?:{ *:[i64] }:$vaddr, ?:{ *:[v4i32] }:$srsrc, ?:{ *:[i32] }:$soffset, ?:{ *:[i32] }:$offset)
      GIR_BuildMI, /*InsnID*/0, /*Opcode*/GIMT_Encode2(AMDGPU::BUFFER_STORE_DWORD_ADDR64),
      GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/0, // val
      GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/1, // vaddr
      GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/0, // srsrc
      GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/2, // soffset
      GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/3, // offset
      GIR_AddImm8, /*InsnID*/0, /*Imm*/0,
      GIR_AddImm8, /*InsnID*/0, /*Imm*/0,
      GIR_MergeMemOperands, /*InsnID*/0, /*NumInsns*/1, /*MergeInsnID's*/0,
      GIR_ConstrainSelectedInstOperands, /*InsnID*/0,
      GIR_EraseFromParent, /*InsnID*/0,
      // GIR_Coverage, 5489,
      GIR_Done,
    // Label 2014: @131858
    GIM_Try, /*On fail goto*//*Label 2015*/ GIMT_Encode4(131939), // Rule ID 3644 //
      GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasUnrestrictedSOffset),
      GIM_CheckMemorySizeLessThanLLT, /*MI*/0, /*MMO*/0, /*OpIdx*/0,
      GIM_CheckMemorySizeEqualTo, /*MI*/0, /*MMO*/0, /*Size*/GIMT_Encode4(1),
      GIM_CheckMemoryAddressSpace, /*MI*/0, /*MMO*/0, /*NumAddrSpace*/1, /*AddrSpace*/1,
      GIM_CheckAtomicOrdering, /*MI*/0, /*Order*/(uint8_t)AtomicOrdering::NotAtomic,
      GIM_CheckPointerToAny, /*MI*/0, /*Op*/1, /*SizeInBits*/0,
      GIM_CheckComplexPattern, /*MI*/0, /*Op*/1, /*Renderer*/GIMT_Encode2(0), GIMT_Encode2(GICP_gi_mubuf_addr64),
      // (st i32:{ *:[i32] }:$vdata, (MUBUFAddr64:{ *:[iPTR] } v4i32:{ *:[v4i32] }:$srsrc, i64:{ *:[i64] }:$vaddr, i32:{ *:[i32] }:$soffset, i32:{ *:[i32] }:$offset))<<P:Predicate_unindexedstore>><<P:Predicate_truncstore>><<P:Predicate_truncstorei8>><<P:Predicate_truncstorei8_global>>  =>  (BUFFER_STORE_BYTE_ADDR64 i32:{ *:[i32] }:$vdata, i64:{ *:[i64] }:$vaddr, v4i32:{ *:[v4i32] }:$srsrc, i32:{ *:[i32] }:$soffset, i32:{ *:[i32] }:$offset)
      GIR_BuildMI, /*InsnID*/0, /*Opcode*/GIMT_Encode2(AMDGPU::BUFFER_STORE_BYTE_ADDR64),
      GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/0, // vdata
      GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/1, // vaddr
      GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/0, // srsrc
      GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/2, // soffset
      GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/3, // offset
      GIR_AddImm8, /*InsnID*/0, /*Imm*/0,
      GIR_AddImm8, /*InsnID*/0, /*Imm*/0,
      GIR_MergeMemOperands, /*InsnID*/0, /*NumInsns*/1, /*MergeInsnID's*/0,
      GIR_ConstrainSelectedInstOperands, /*InsnID*/0,
      GIR_EraseFromParent, /*InsnID*/0,
      // GIR_Coverage, 3644,
      GIR_Done,
    // Label 2015: @131939
    GIM_Try, /*On fail goto*//*Label 2016*/ GIMT_Encode4(132017), // Rule ID 3796 //
      GIM_CheckMemorySizeLessThanLLT, /*MI*/0, /*MMO*/0, /*OpIdx*/0,
      GIM_CheckMemorySizeEqualTo, /*MI*/0, /*MMO*/0, /*Size*/GIMT_Encode4(1),
      GIM_CheckMemoryAddressSpace, /*MI*/0, /*MMO*/0, /*NumAddrSpace*/1, /*AddrSpace*/1,
      GIM_CheckAtomicOrdering, /*MI*/0, /*Order*/(uint8_t)AtomicOrdering::NotAtomic,
      GIM_CheckPointerToAny, /*MI*/0, /*Op*/1, /*SizeInBits*/0,
      GIM_CheckComplexPattern, /*MI*/0, /*Op*/1, /*Renderer*/GIMT_Encode2(0), GIMT_Encode2(GICP_gi_mubuf_addr64),
      // (st i32:{ *:[i32] }:$vdata, (MUBUFAddr64:{ *:[iPTR] } v4i32:{ *:[v4i32] }:$srsrc, i64:{ *:[i64] }:$vaddr, i32:{ *:[i32] }:$soffset, i32:{ *:[i32] }:$offset))<<P:Predicate_unindexedstore>><<P:Predicate_truncstore>><<P:Predicate_truncstorei8>><<P:Predicate_truncstorei8_global>>  =>  (BUFFER_STORE_BYTE_VBUFFER_ADDR64 i32:{ *:[i32] }:$vdata, i64:{ *:[i64] }:$vaddr, v4i32:{ *:[v4i32] }:$srsrc, i32:{ *:[i32] }:$soffset, i32:{ *:[i32] }:$offset)
      GIR_BuildMI, /*InsnID*/0, /*Opcode*/GIMT_Encode2(AMDGPU::BUFFER_STORE_BYTE_VBUFFER_ADDR64),
      GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/0, // vdata
      GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/1, // vaddr
      GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/0, // srsrc
      GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/2, // soffset
      GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/3, // offset
      GIR_AddImm8, /*InsnID*/0, /*Imm*/0,
      GIR_AddImm8, /*InsnID*/0, /*Imm*/0,
      GIR_MergeMemOperands, /*InsnID*/0, /*NumInsns*/1, /*MergeInsnID's*/0,
      GIR_ConstrainSelectedInstOperands, /*InsnID*/0,
      GIR_EraseFromParent, /*InsnID*/0,
      // GIR_Coverage, 3796,
      GIR_Done,
    // Label 2016: @132017
    GIM_Try, /*On fail goto*//*Label 2017*/ GIMT_Encode4(132098), // Rule ID 3798 //
      GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasUnrestrictedSOffset),
      GIM_CheckMemorySizeLessThanLLT, /*MI*/0, /*MMO*/0, /*OpIdx*/0,
      GIM_CheckMemorySizeEqualTo, /*MI*/0, /*MMO*/0, /*Size*/GIMT_Encode4(2),
      GIM_CheckMemoryAddressSpace, /*MI*/0, /*MMO*/0, /*NumAddrSpace*/1, /*AddrSpace*/1,
      GIM_CheckAtomicOrdering, /*MI*/0, /*Order*/(uint8_t)AtomicOrdering::NotAtomic,
      GIM_CheckPointerToAny, /*MI*/0, /*Op*/1, /*SizeInBits*/0,
      GIM_CheckComplexPattern, /*MI*/0, /*Op*/1, /*Renderer*/GIMT_Encode2(0), GIMT_Encode2(GICP_gi_mubuf_addr64),
      // (st i32:{ *:[i32] }:$vdata, (MUBUFAddr64:{ *:[iPTR] } v4i32:{ *:[v4i32] }:$srsrc, i64:{ *:[i64] }:$vaddr, i32:{ *:[i32] }:$soffset, i32:{ *:[i32] }:$offset))<<P:Predicate_unindexedstore>><<P:Predicate_truncstore>><<P:Predicate_truncstorei16>><<P:Predicate_truncstorei16_global>>  =>  (BUFFER_STORE_SHORT_ADDR64 i32:{ *:[i32] }:$vdata, i64:{ *:[i64] }:$vaddr, v4i32:{ *:[v4i32] }:$srsrc, i32:{ *:[i32] }:$soffset, i32:{ *:[i32] }:$offset)
      GIR_BuildMI, /*InsnID*/0, /*Opcode*/GIMT_Encode2(AMDGPU::BUFFER_STORE_SHORT_ADDR64),
      GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/0, // vdata
      GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/1, // vaddr
      GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/0, // srsrc
      GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/2, // soffset
      GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/3, // offset
      GIR_AddImm8, /*InsnID*/0, /*Imm*/0,
      GIR_AddImm8, /*InsnID*/0, /*Imm*/0,
      GIR_MergeMemOperands, /*InsnID*/0, /*NumInsns*/1, /*MergeInsnID's*/0,
      GIR_ConstrainSelectedInstOperands, /*InsnID*/0,
      GIR_EraseFromParent, /*InsnID*/0,
      // GIR_Coverage, 3798,
      GIR_Done,
    // Label 2017: @132098
    GIM_Try, /*On fail goto*//*Label 2018*/ GIMT_Encode4(132176), // Rule ID 3800 //
      GIM_CheckMemorySizeLessThanLLT, /*MI*/0, /*MMO*/0, /*OpIdx*/0,
      GIM_CheckMemorySizeEqualTo, /*MI*/0, /*MMO*/0, /*Size*/GIMT_Encode4(2),
      GIM_CheckMemoryAddressSpace, /*MI*/0, /*MMO*/0, /*NumAddrSpace*/1, /*AddrSpace*/1,
      GIM_CheckAtomicOrdering, /*MI*/0, /*Order*/(uint8_t)AtomicOrdering::NotAtomic,
      GIM_CheckPointerToAny, /*MI*/0, /*Op*/1, /*SizeInBits*/0,
      GIM_CheckComplexPattern, /*MI*/0, /*Op*/1, /*Renderer*/GIMT_Encode2(0), GIMT_Encode2(GICP_gi_mubuf_addr64),
      // (st i32:{ *:[i32] }:$vdata, (MUBUFAddr64:{ *:[iPTR] } v4i32:{ *:[v4i32] }:$srsrc, i64:{ *:[i64] }:$vaddr, i32:{ *:[i32] }:$soffset, i32:{ *:[i32] }:$offset))<<P:Predicate_unindexedstore>><<P:Predicate_truncstore>><<P:Predicate_truncstorei16>><<P:Predicate_truncstorei16_global>>  =>  (BUFFER_STORE_SHORT_VBUFFER_ADDR64 i32:{ *:[i32] }:$vdata, i64:{ *:[i64] }:$vaddr, v4i32:{ *:[v4i32] }:$srsrc, i32:{ *:[i32] }:$soffset, i32:{ *:[i32] }:$offset)
      GIR_BuildMI, /*InsnID*/0, /*Opcode*/GIMT_Encode2(AMDGPU::BUFFER_STORE_SHORT_VBUFFER_ADDR64),
      GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/0, // vdata
      GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/1, // vaddr
      GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/0, // srsrc
      GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/2, // soffset
      GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/3, // offset
      GIR_AddImm8, /*InsnID*/0, /*Imm*/0,
      GIR_AddImm8, /*InsnID*/0, /*Imm*/0,
      GIR_MergeMemOperands, /*InsnID*/0, /*NumInsns*/1, /*MergeInsnID's*/0,
      GIR_ConstrainSelectedInstOperands, /*InsnID*/0,
      GIR_EraseFromParent, /*InsnID*/0,
      // GIR_Coverage, 3800,
      GIR_Done,
    // Label 2018: @132176
    GIM_Try, /*On fail goto*//*Label 2019*/ GIMT_Encode4(132257), // Rule ID 5497 //
      GIM_CheckFeatures, GIMT_Encode2(GIFBS_DisableFlatScratch_HasUnrestrictedSOffset),
      GIM_CheckMemorySizeLessThanLLT, /*MI*/0, /*MMO*/0, /*OpIdx*/0,
      GIM_CheckMemorySizeEqualTo, /*MI*/0, /*MMO*/0, /*Size*/GIMT_Encode4(1),
      GIM_CheckMemoryAddressSpace, /*MI*/0, /*MMO*/0, /*NumAddrSpace*/1, /*AddrSpace*/5,
      GIM_CheckAtomicOrdering, /*MI*/0, /*Order*/(uint8_t)AtomicOrdering::NotAtomic,
      GIM_CheckPointerToAny, /*MI*/0, /*Op*/1, /*SizeInBits*/0,
      GIM_CheckComplexPattern, /*MI*/0, /*Op*/1, /*Renderer*/GIMT_Encode2(0), GIMT_Encode2(GICP_gi_mubuf_scratch_offen),
      // (st i32:{ *:[i32] }:$value, (MUBUFScratchOffen:{ *:[iPTR] } v4i32:{ *:[v4i32] }:$srsrc, i32:{ *:[i32] }:$vaddr, i32:{ *:[i32] }:$soffset, i32:{ *:[i32] }:$offset))<<P:Predicate_unindexedstore>><<P:Predicate_truncstore>><<P:Predicate_truncstorei8>><<P:Predicate_truncstorei8_private>>  =>  (BUFFER_STORE_BYTE_OFFEN VGPR_32:{ *:[i32] }:$value, ?:{ *:[i32] }:$vaddr, ?:{ *:[v4i32] }:$srsrc, ?:{ *:[i32] }:$soffset, ?:{ *:[i32] }:$offset, 0:{ *:[i32] }, 0:{ *:[i1] })
      GIR_BuildMI, /*InsnID*/0, /*Opcode*/GIMT_Encode2(AMDGPU::BUFFER_STORE_BYTE_OFFEN),
      GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/0, // value
      GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/1, // vaddr
      GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/0, // srsrc
      GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/2, // soffset
      GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/3, // offset
      GIR_AddImm8, /*InsnID*/0, /*Imm*/0,
      GIR_AddImm8, /*InsnID*/0, /*Imm*/0,
      GIR_MergeMemOperands, /*InsnID*/0, /*NumInsns*/1, /*MergeInsnID's*/0,
      GIR_ConstrainSelectedInstOperands, /*InsnID*/0,
      GIR_EraseFromParent, /*InsnID*/0,
      // GIR_Coverage, 5497,
      GIR_Done,
    // Label 2019: @132257
    GIM_Try, /*On fail goto*//*Label 2020*/ GIMT_Encode4(132338), // Rule ID 5499 //
      GIM_CheckFeatures, GIMT_Encode2(GIFBS_DisableFlatScratch),
      GIM_CheckMemorySizeLessThanLLT, /*MI*/0, /*MMO*/0, /*OpIdx*/0,
      GIM_CheckMemorySizeEqualTo, /*MI*/0, /*MMO*/0, /*Size*/GIMT_Encode4(1),
      GIM_CheckMemoryAddressSpace, /*MI*/0, /*MMO*/0, /*NumAddrSpace*/1, /*AddrSpace*/5,
      GIM_CheckAtomicOrdering, /*MI*/0, /*Order*/(uint8_t)AtomicOrdering::NotAtomic,
      GIM_CheckPointerToAny, /*MI*/0, /*Op*/1, /*SizeInBits*/0,
      GIM_CheckComplexPattern, /*MI*/0, /*Op*/1, /*Renderer*/GIMT_Encode2(0), GIMT_Encode2(GICP_gi_mubuf_scratch_offen),
      // (st i32:{ *:[i32] }:$value, (MUBUFScratchOffen:{ *:[iPTR] } v4i32:{ *:[v4i32] }:$srsrc, i32:{ *:[i32] }:$vaddr, i32:{ *:[i32] }:$soffset, i32:{ *:[i32] }:$offset))<<P:Predicate_unindexedstore>><<P:Predicate_truncstore>><<P:Predicate_truncstorei8>><<P:Predicate_truncstorei8_private>>  =>  (BUFFER_STORE_BYTE_VBUFFER_OFFEN VGPR_32:{ *:[i32] }:$value, ?:{ *:[i32] }:$vaddr, ?:{ *:[v4i32] }:$srsrc, ?:{ *:[i32] }:$soffset, ?:{ *:[i32] }:$offset, 0:{ *:[i32] }, 0:{ *:[i1] })
      GIR_BuildMI, /*InsnID*/0, /*Opcode*/GIMT_Encode2(AMDGPU::BUFFER_STORE_BYTE_VBUFFER_OFFEN),
      GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/0, // value
      GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/1, // vaddr
      GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/0, // srsrc
      GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/2, // soffset
      GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/3, // offset
      GIR_AddImm8, /*InsnID*/0, /*Imm*/0,
      GIR_AddImm8, /*InsnID*/0, /*Imm*/0,
      GIR_MergeMemOperands, /*InsnID*/0, /*NumInsns*/1, /*MergeInsnID's*/0,
      GIR_ConstrainSelectedInstOperands, /*InsnID*/0,
      GIR_EraseFromParent, /*InsnID*/0,
      // GIR_Coverage, 5499,
      GIR_Done,
    // Label 2020: @132338
    GIM_Try, /*On fail goto*//*Label 2021*/ GIMT_Encode4(132419), // Rule ID 5501 //
      GIM_CheckFeatures, GIMT_Encode2(GIFBS_DisableFlatScratch_HasUnrestrictedSOffset),
      GIM_CheckMemorySizeLessThanLLT, /*MI*/0, /*MMO*/0, /*OpIdx*/0,
      GIM_CheckMemorySizeEqualTo, /*MI*/0, /*MMO*/0, /*Size*/GIMT_Encode4(2),
      GIM_CheckMemoryAddressSpace, /*MI*/0, /*MMO*/0, /*NumAddrSpace*/1, /*AddrSpace*/5,
      GIM_CheckAtomicOrdering, /*MI*/0, /*Order*/(uint8_t)AtomicOrdering::NotAtomic,
      GIM_CheckPointerToAny, /*MI*/0, /*Op*/1, /*SizeInBits*/0,
      GIM_CheckComplexPattern, /*MI*/0, /*Op*/1, /*Renderer*/GIMT_Encode2(0), GIMT_Encode2(GICP_gi_mubuf_scratch_offen),
      // (st i32:{ *:[i32] }:$value, (MUBUFScratchOffen:{ *:[iPTR] } v4i32:{ *:[v4i32] }:$srsrc, i32:{ *:[i32] }:$vaddr, i32:{ *:[i32] }:$soffset, i32:{ *:[i32] }:$offset))<<P:Predicate_unindexedstore>><<P:Predicate_truncstore>><<P:Predicate_truncstorei16>><<P:Predicate_truncstorei16_private>>  =>  (BUFFER_STORE_SHORT_OFFEN VGPR_32:{ *:[i32] }:$value, ?:{ *:[i32] }:$vaddr, ?:{ *:[v4i32] }:$srsrc, ?:{ *:[i32] }:$soffset, ?:{ *:[i32] }:$offset, 0:{ *:[i32] }, 0:{ *:[i1] })
      GIR_BuildMI, /*InsnID*/0, /*Opcode*/GIMT_Encode2(AMDGPU::BUFFER_STORE_SHORT_OFFEN),
      GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/0, // value
      GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/1, // vaddr
      GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/0, // srsrc
      GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/2, // soffset
      GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/3, // offset
      GIR_AddImm8, /*InsnID*/0, /*Imm*/0,
      GIR_AddImm8, /*InsnID*/0, /*Imm*/0,
      GIR_MergeMemOperands, /*InsnID*/0, /*NumInsns*/1, /*MergeInsnID's*/0,
      GIR_ConstrainSelectedInstOperands, /*InsnID*/0,
      GIR_EraseFromParent, /*InsnID*/0,
      // GIR_Coverage, 5501,
      GIR_Done,
    // Label 2021: @132419
    GIM_Try, /*On fail goto*//*Label 2022*/ GIMT_Encode4(132500), // Rule ID 5503 //
      GIM_CheckFeatures, GIMT_Encode2(GIFBS_DisableFlatScratch),
      GIM_CheckMemorySizeLessThanLLT, /*MI*/0, /*MMO*/0, /*OpIdx*/0,
      GIM_CheckMemorySizeEqualTo, /*MI*/0, /*MMO*/0, /*Size*/GIMT_Encode4(2),
      GIM_CheckMemoryAddressSpace, /*MI*/0, /*MMO*/0, /*NumAddrSpace*/1, /*AddrSpace*/5,
      GIM_CheckAtomicOrdering, /*MI*/0, /*Order*/(uint8_t)AtomicOrdering::NotAtomic,
      GIM_CheckPointerToAny, /*MI*/0, /*Op*/1, /*SizeInBits*/0,
      GIM_CheckComplexPattern, /*MI*/0, /*Op*/1, /*Renderer*/GIMT_Encode2(0), GIMT_Encode2(GICP_gi_mubuf_scratch_offen),
      // (st i32:{ *:[i32] }:$value, (MUBUFScratchOffen:{ *:[iPTR] } v4i32:{ *:[v4i32] }:$srsrc, i32:{ *:[i32] }:$vaddr, i32:{ *:[i32] }:$soffset, i32:{ *:[i32] }:$offset))<<P:Predicate_unindexedstore>><<P:Predicate_truncstore>><<P:Predicate_truncstorei16>><<P:Predicate_truncstorei16_private>>  =>  (BUFFER_STORE_SHORT_VBUFFER_OFFEN VGPR_32:{ *:[i32] }:$value, ?:{ *:[i32] }:$vaddr, ?:{ *:[v4i32] }:$srsrc, ?:{ *:[i32] }:$soffset, ?:{ *:[i32] }:$offset, 0:{ *:[i32] }, 0:{ *:[i1] })
      GIR_BuildMI, /*InsnID*/0, /*Opcode*/GIMT_Encode2(AMDGPU::BUFFER_STORE_SHORT_VBUFFER_OFFEN),
      GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/0, // value
      GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/1, // vaddr
      GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/0, // srsrc
      GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/2, // soffset
      GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/3, // offset
      GIR_AddImm8, /*InsnID*/0, /*Imm*/0,
      GIR_AddImm8, /*InsnID*/0, /*Imm*/0,
      GIR_MergeMemOperands, /*InsnID*/0, /*NumInsns*/1, /*MergeInsnID's*/0,
      GIR_ConstrainSelectedInstOperands, /*InsnID*/0,
      GIR_EraseFromParent, /*InsnID*/0,
      // GIR_Coverage, 5503,
      GIR_Done,
    // Label 2022: @132500
    GIM_Try, /*On fail goto*//*Label 2023*/ GIMT_Encode4(132570), // Rule ID 3802 //
      GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasUnrestrictedSOffset),
      GIM_CheckMemoryAddressSpace, /*MI*/0, /*MMO*/0, /*NumAddrSpace*/1, /*AddrSpace*/1,
      GIM_CheckAtomicOrdering, /*MI*/0, /*Order*/(uint8_t)AtomicOrdering::NotAtomic,
      GIM_CheckPointerToAny, /*MI*/0, /*Op*/1, /*SizeInBits*/0,
      GIM_CheckComplexPattern, /*MI*/0, /*Op*/1, /*Renderer*/GIMT_Encode2(0), GIMT_Encode2(GICP_gi_mubuf_addr64),
      // (st i32:{ *:[i32] }:$vdata, (MUBUFAddr64:{ *:[iPTR] } v4i32:{ *:[v4i32] }:$srsrc, i64:{ *:[i64] }:$vaddr, i32:{ *:[i32] }:$soffset, i32:{ *:[i32] }:$offset))<<P:Predicate_unindexedstore>><<P:Predicate_store_global>>  =>  (BUFFER_STORE_DWORD_ADDR64 i32:{ *:[i32] }:$vdata, i64:{ *:[i64] }:$vaddr, v4i32:{ *:[v4i32] }:$srsrc, i32:{ *:[i32] }:$soffset, i32:{ *:[i32] }:$offset)
      GIR_BuildMI, /*InsnID*/0, /*Opcode*/GIMT_Encode2(AMDGPU::BUFFER_STORE_DWORD_ADDR64),
      GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/0, // vdata
      GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/1, // vaddr
      GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/0, // srsrc
      GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/2, // soffset
      GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/3, // offset
      GIR_AddImm8, /*InsnID*/0, /*Imm*/0,
      GIR_AddImm8, /*InsnID*/0, /*Imm*/0,
      GIR_MergeMemOperands, /*InsnID*/0, /*NumInsns*/1, /*MergeInsnID's*/0,
      GIR_ConstrainSelectedInstOperands, /*InsnID*/0,
      GIR_EraseFromParent, /*InsnID*/0,
      // GIR_Coverage, 3802,
      GIR_Done,
    // Label 2023: @132570
    GIM_Try, /*On fail goto*//*Label 2024*/ GIMT_Encode4(132637), // Rule ID 3804 //
      GIM_CheckMemoryAddressSpace, /*MI*/0, /*MMO*/0, /*NumAddrSpace*/1, /*AddrSpace*/1,
      GIM_CheckAtomicOrdering, /*MI*/0, /*Order*/(uint8_t)AtomicOrdering::NotAtomic,
      GIM_CheckPointerToAny, /*MI*/0, /*Op*/1, /*SizeInBits*/0,
      GIM_CheckComplexPattern, /*MI*/0, /*Op*/1, /*Renderer*/GIMT_Encode2(0), GIMT_Encode2(GICP_gi_mubuf_addr64),
      // (st i32:{ *:[i32] }:$vdata, (MUBUFAddr64:{ *:[iPTR] } v4i32:{ *:[v4i32] }:$srsrc, i64:{ *:[i64] }:$vaddr, i32:{ *:[i32] }:$soffset, i32:{ *:[i32] }:$offset))<<P:Predicate_unindexedstore>><<P:Predicate_store_global>>  =>  (BUFFER_STORE_DWORD_VBUFFER_ADDR64 i32:{ *:[i32] }:$vdata, i64:{ *:[i64] }:$vaddr, v4i32:{ *:[v4i32] }:$srsrc, i32:{ *:[i32] }:$soffset, i32:{ *:[i32] }:$offset)
      GIR_BuildMI, /*InsnID*/0, /*Opcode*/GIMT_Encode2(AMDGPU::BUFFER_STORE_DWORD_VBUFFER_ADDR64),
      GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/0, // vdata
      GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/1, // vaddr
      GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/0, // srsrc
      GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/2, // soffset
      GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/3, // offset
      GIR_AddImm8, /*InsnID*/0, /*Imm*/0,
      GIR_AddImm8, /*InsnID*/0, /*Imm*/0,
      GIR_MergeMemOperands, /*InsnID*/0, /*NumInsns*/1, /*MergeInsnID's*/0,
      GIR_ConstrainSelectedInstOperands, /*InsnID*/0,
      GIR_EraseFromParent, /*InsnID*/0,
      // GIR_Coverage, 3804,
      GIR_Done,
    // Label 2024: @132637
    GIM_Try, /*On fail goto*//*Label 2025*/ GIMT_Encode4(132707), // Rule ID 3806 //
      GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasUnrestrictedSOffset),
      GIM_CheckMemoryAddressSpace, /*MI*/0, /*MMO*/0, /*NumAddrSpace*/1, /*AddrSpace*/1,
      GIM_CheckAtomicOrdering, /*MI*/0, /*Order*/(uint8_t)AtomicOrdering::NotAtomic,
      GIM_CheckPointerToAny, /*MI*/0, /*Op*/1, /*SizeInBits*/0,
      GIM_CheckComplexPattern, /*MI*/0, /*Op*/1, /*Renderer*/GIMT_Encode2(0), GIMT_Encode2(GICP_gi_mubuf_addr64),
      // (st f32:{ *:[f32] }:$vdata, (MUBUFAddr64:{ *:[iPTR] } v4i32:{ *:[v4i32] }:$srsrc, i64:{ *:[i64] }:$vaddr, i32:{ *:[i32] }:$soffset, i32:{ *:[i32] }:$offset))<<P:Predicate_unindexedstore>><<P:Predicate_store_global>>  =>  (BUFFER_STORE_DWORD_ADDR64 f32:{ *:[f32] }:$vdata, i64:{ *:[i64] }:$vaddr, v4i32:{ *:[v4i32] }:$srsrc, i32:{ *:[i32] }:$soffset, i32:{ *:[i32] }:$offset)
      GIR_BuildMI, /*InsnID*/0, /*Opcode*/GIMT_Encode2(AMDGPU::BUFFER_STORE_DWORD_ADDR64),
      GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/0, // vdata
      GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/1, // vaddr
      GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/0, // srsrc
      GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/2, // soffset
      GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/3, // offset
      GIR_AddImm8, /*InsnID*/0, /*Imm*/0,
      GIR_AddImm8, /*InsnID*/0, /*Imm*/0,
      GIR_MergeMemOperands, /*InsnID*/0, /*NumInsns*/1, /*MergeInsnID's*/0,
      GIR_ConstrainSelectedInstOperands, /*InsnID*/0,
      GIR_EraseFromParent, /*InsnID*/0,
      // GIR_Coverage, 3806,
      GIR_Done,
    // Label 2025: @132707
    GIM_Try, /*On fail goto*//*Label 2026*/ GIMT_Encode4(132774), // Rule ID 3808 //
      GIM_CheckMemoryAddressSpace, /*MI*/0, /*MMO*/0, /*NumAddrSpace*/1, /*AddrSpace*/1,
      GIM_CheckAtomicOrdering, /*MI*/0, /*Order*/(uint8_t)AtomicOrdering::NotAtomic,
      GIM_CheckPointerToAny, /*MI*/0, /*Op*/1, /*SizeInBits*/0,
      GIM_CheckComplexPattern, /*MI*/0, /*Op*/1, /*Renderer*/GIMT_Encode2(0), GIMT_Encode2(GICP_gi_mubuf_addr64),
      // (st f32:{ *:[f32] }:$vdata, (MUBUFAddr64:{ *:[iPTR] } v4i32:{ *:[v4i32] }:$srsrc, i64:{ *:[i64] }:$vaddr, i32:{ *:[i32] }:$soffset, i32:{ *:[i32] }:$offset))<<P:Predicate_unindexedstore>><<P:Predicate_store_global>>  =>  (BUFFER_STORE_DWORD_VBUFFER_ADDR64 f32:{ *:[f32] }:$vdata, i64:{ *:[i64] }:$vaddr, v4i32:{ *:[v4i32] }:$srsrc, i32:{ *:[i32] }:$soffset, i32:{ *:[i32] }:$offset)
      GIR_BuildMI, /*InsnID*/0, /*Opcode*/GIMT_Encode2(AMDGPU::BUFFER_STORE_DWORD_VBUFFER_ADDR64),
      GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/0, // vdata
      GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/1, // vaddr
      GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/0, // srsrc
      GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/2, // soffset
      GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/3, // offset
      GIR_AddImm8, /*InsnID*/0, /*Imm*/0,
      GIR_AddImm8, /*InsnID*/0, /*Imm*/0,
      GIR_MergeMemOperands, /*InsnID*/0, /*NumInsns*/1, /*MergeInsnID's*/0,
      GIR_ConstrainSelectedInstOperands, /*InsnID*/0,
      GIR_EraseFromParent, /*InsnID*/0,
      // GIR_Coverage, 3808,
      GIR_Done,
    // Label 2026: @132774
    GIM_Try, /*On fail goto*//*Label 2027*/ GIMT_Encode4(132844), // Rule ID 5513 //
      GIM_CheckFeatures, GIMT_Encode2(GIFBS_DisableFlatScratch_HasUnrestrictedSOffset),
      GIM_CheckMemoryAddressSpace, /*MI*/0, /*MMO*/0, /*NumAddrSpace*/1, /*AddrSpace*/5,
      GIM_CheckAtomicOrdering, /*MI*/0, /*Order*/(uint8_t)AtomicOrdering::NotAtomic,
      GIM_CheckPointerToAny, /*MI*/0, /*Op*/1, /*SizeInBits*/0,
      GIM_CheckComplexPattern, /*MI*/0, /*Op*/1, /*Renderer*/GIMT_Encode2(0), GIMT_Encode2(GICP_gi_mubuf_scratch_offen),
      // (st i32:{ *:[i32] }:$value, (MUBUFScratchOffen:{ *:[iPTR] } v4i32:{ *:[v4i32] }:$srsrc, i32:{ *:[i32] }:$vaddr, i32:{ *:[i32] }:$soffset, i32:{ *:[i32] }:$offset))<<P:Predicate_unindexedstore>><<P:Predicate_store_private>>  =>  (BUFFER_STORE_DWORD_OFFEN VGPR_32:{ *:[i32] }:$value, ?:{ *:[i32] }:$vaddr, ?:{ *:[v4i32] }:$srsrc, ?:{ *:[i32] }:$soffset, ?:{ *:[i32] }:$offset, 0:{ *:[i32] }, 0:{ *:[i1] })
      GIR_BuildMI, /*InsnID*/0, /*Opcode*/GIMT_Encode2(AMDGPU::BUFFER_STORE_DWORD_OFFEN),
      GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/0, // value
      GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/1, // vaddr
      GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/0, // srsrc
      GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/2, // soffset
      GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/3, // offset
      GIR_AddImm8, /*InsnID*/0, /*Imm*/0,
      GIR_AddImm8, /*InsnID*/0, /*Imm*/0,
      GIR_MergeMemOperands, /*InsnID*/0, /*NumInsns*/1, /*MergeInsnID's*/0,
      GIR_ConstrainSelectedInstOperands, /*InsnID*/0,
      GIR_EraseFromParent, /*InsnID*/0,
      // GIR_Coverage, 5513,
      GIR_Done,
    // Label 2027: @132844
    GIM_Try, /*On fail goto*//*Label 2028*/ GIMT_Encode4(132914), // Rule ID 5515 //
      GIM_CheckFeatures, GIMT_Encode2(GIFBS_DisableFlatScratch),
      GIM_CheckMemoryAddressSpace, /*MI*/0, /*MMO*/0, /*NumAddrSpace*/1, /*AddrSpace*/5,
      GIM_CheckAtomicOrdering, /*MI*/0, /*Order*/(uint8_t)AtomicOrdering::NotAtomic,
      GIM_CheckPointerToAny, /*MI*/0, /*Op*/1, /*SizeInBits*/0,
      GIM_CheckComplexPattern, /*MI*/0, /*Op*/1, /*Renderer*/GIMT_Encode2(0), GIMT_Encode2(GICP_gi_mubuf_scratch_offen),
      // (st i32:{ *:[i32] }:$value, (MUBUFScratchOffen:{ *:[iPTR] } v4i32:{ *:[v4i32] }:$srsrc, i32:{ *:[i32] }:$vaddr, i32:{ *:[i32] }:$soffset, i32:{ *:[i32] }:$offset))<<P:Predicate_unindexedstore>><<P:Predicate_store_private>>  =>  (BUFFER_STORE_DWORD_VBUFFER_OFFEN VGPR_32:{ *:[i32] }:$value, ?:{ *:[i32] }:$vaddr, ?:{ *:[v4i32] }:$srsrc, ?:{ *:[i32] }:$soffset, ?:{ *:[i32] }:$offset, 0:{ *:[i32] }, 0:{ *:[i1] })
      GIR_BuildMI, /*InsnID*/0, /*Opcode*/GIMT_Encode2(AMDGPU::BUFFER_STORE_DWORD_VBUFFER_OFFEN),
      GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/0, // value
      GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/1, // vaddr
      GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/0, // srsrc
      GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/2, // soffset
      GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/3, // offset
      GIR_AddImm8, /*InsnID*/0, /*Imm*/0,
      GIR_AddImm8, /*InsnID*/0, /*Imm*/0,
      GIR_MergeMemOperands, /*InsnID*/0, /*NumInsns*/1, /*MergeInsnID's*/0,
      GIR_ConstrainSelectedInstOperands, /*InsnID*/0,
      GIR_EraseFromParent, /*InsnID*/0,
      // GIR_Coverage, 5515,
      GIR_Done,
    // Label 2028: @132914
    GIM_Try, /*On fail goto*//*Label 2029*/ GIMT_Encode4(132984), // Rule ID 5517 //
      GIM_CheckFeatures, GIMT_Encode2(GIFBS_DisableFlatScratch_HasUnrestrictedSOffset),
      GIM_CheckMemoryAddressSpace, /*MI*/0, /*MMO*/0, /*NumAddrSpace*/1, /*AddrSpace*/5,
      GIM_CheckAtomicOrdering, /*MI*/0, /*Order*/(uint8_t)AtomicOrdering::NotAtomic,
      GIM_CheckPointerToAny, /*MI*/0, /*Op*/1, /*SizeInBits*/0,
      GIM_CheckComplexPattern, /*MI*/0, /*Op*/1, /*Renderer*/GIMT_Encode2(0), GIMT_Encode2(GICP_gi_mubuf_scratch_offen),
      // (st f32:{ *:[f32] }:$value, (MUBUFScratchOffen:{ *:[iPTR] } v4i32:{ *:[v4i32] }:$srsrc, i32:{ *:[i32] }:$vaddr, i32:{ *:[i32] }:$soffset, i32:{ *:[i32] }:$offset))<<P:Predicate_unindexedstore>><<P:Predicate_store_private>>  =>  (BUFFER_STORE_DWORD_OFFEN VGPR_32:{ *:[f32] }:$value, ?:{ *:[i32] }:$vaddr, ?:{ *:[v4i32] }:$srsrc, ?:{ *:[i32] }:$soffset, ?:{ *:[i32] }:$offset, 0:{ *:[i32] }, 0:{ *:[i1] })
      GIR_BuildMI, /*InsnID*/0, /*Opcode*/GIMT_Encode2(AMDGPU::BUFFER_STORE_DWORD_OFFEN),
      GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/0, // value
      GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/1, // vaddr
      GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/0, // srsrc
      GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/2, // soffset
      GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/3, // offset
      GIR_AddImm8, /*InsnID*/0, /*Imm*/0,
      GIR_AddImm8, /*InsnID*/0, /*Imm*/0,
      GIR_MergeMemOperands, /*InsnID*/0, /*NumInsns*/1, /*MergeInsnID's*/0,
      GIR_ConstrainSelectedInstOperands, /*InsnID*/0,
      GIR_EraseFromParent, /*InsnID*/0,
      // GIR_Coverage, 5517,
      GIR_Done,
    // Label 2029: @132984
    GIM_Try, /*On fail goto*//*Label 2030*/ GIMT_Encode4(133054), // Rule ID 5519 //
      GIM_CheckFeatures, GIMT_Encode2(GIFBS_DisableFlatScratch),
      GIM_CheckMemoryAddressSpace, /*MI*/0, /*MMO*/0, /*NumAddrSpace*/1, /*AddrSpace*/5,
      GIM_CheckAtomicOrdering, /*MI*/0, /*Order*/(uint8_t)AtomicOrdering::NotAtomic,
      GIM_CheckPointerToAny, /*MI*/0, /*Op*/1, /*SizeInBits*/0,
      GIM_CheckComplexPattern, /*MI*/0, /*Op*/1, /*Renderer*/GIMT_Encode2(0), GIMT_Encode2(GICP_gi_mubuf_scratch_offen),
      // (st f32:{ *:[f32] }:$value, (MUBUFScratchOffen:{ *:[iPTR] } v4i32:{ *:[v4i32] }:$srsrc, i32:{ *:[i32] }:$vaddr, i32:{ *:[i32] }:$soffset, i32:{ *:[i32] }:$offset))<<P:Predicate_unindexedstore>><<P:Predicate_store_private>>  =>  (BUFFER_STORE_DWORD_VBUFFER_OFFEN VGPR_32:{ *:[f32] }:$value, ?:{ *:[i32] }:$vaddr, ?:{ *:[v4i32] }:$srsrc, ?:{ *:[i32] }:$soffset, ?:{ *:[i32] }:$offset, 0:{ *:[i32] }, 0:{ *:[i1] })
      GIR_BuildMI, /*InsnID*/0, /*Opcode*/GIMT_Encode2(AMDGPU::BUFFER_STORE_DWORD_VBUFFER_OFFEN),
      GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/0, // value
      GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/1, // vaddr
      GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/0, // srsrc
      GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/2, // soffset
      GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/3, // offset
      GIR_AddImm8, /*InsnID*/0, /*Imm*/0,
      GIR_AddImm8, /*InsnID*/0, /*Imm*/0,
      GIR_MergeMemOperands, /*InsnID*/0, /*NumInsns*/1, /*MergeInsnID's*/0,
      GIR_ConstrainSelectedInstOperands, /*InsnID*/0,
      GIR_EraseFromParent, /*InsnID*/0,
      // GIR_Coverage, 5519,
      GIR_Done,
    // Label 2030: @133054
    GIM_Try, /*On fail goto*//*Label 2031*/ GIMT_Encode4(133150), // Rule ID 3113 //
      GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasD16LoadStore),
      GIM_CheckMemorySizeLessThanLLT, /*MI*/0, /*MMO*/0, /*OpIdx*/0,
      GIM_CheckMemorySizeEqualTo, /*MI*/0, /*MMO*/0, /*Size*/GIMT_Encode4(2),
      GIM_CheckMemoryAddressSpace, /*MI*/0, /*MMO*/0, /*NumAddrSpace*/1, /*AddrSpace*/1,
      GIM_CheckAtomicOrdering, /*MI*/0, /*Order*/(uint8_t)AtomicOrdering::NotAtomic,
      GIM_RecordInsn, /*DefineMI*/1, /*MI*/0, /*OpIdx*/0, // MIs[1]
      GIM_CheckOpcode, /*MI*/1, GIMT_Encode2(TargetOpcode::G_LSHR),
      GIM_CheckType, /*MI*/1, /*Op*/1, /*Type*/GILLT_s32,
      GIM_CheckType, /*MI*/1, /*Op*/2, /*Type*/GILLT_s32,
      GIM_CheckConstantInt8, /*MI*/1, /*Op*/2, 16,
      GIM_CheckPointerToAny, /*MI*/0, /*Op*/1, /*SizeInBits*/0,
      GIM_CheckIsSafeToFold, /*InsnID*/1,
      GIM_CheckComplexPattern, /*MI*/0, /*Op*/1, /*Renderer*/GIMT_Encode2(0), GIMT_Encode2(GICP_gi_global_saddr),
      // (st (srl:{ *:[i32] } i32:{ *:[i32] }:$data, 16:{ *:[i32] }), (GlobalSAddr:{ *:[iPTR] } SReg_64:{ *:[i64] }:$saddr, VGPR_32:{ *:[i32] }:$voffset, i32:{ *:[i32] }:$offset))<<P:Predicate_unindexedstore>><<P:Predicate_truncstore>><<P:Predicate_truncstorei16>><<P:Predicate_truncstorei16_hi16_global>>  =>  (GLOBAL_STORE_SHORT_D16_HI_SADDR ?:{ *:[i32] }:$voffset, anonymous_15037:{ *:[i32] }:$data, ?:{ *:[i64] }:$saddr, ?:{ *:[i32] }:$offset)
      GIR_BuildMI, /*InsnID*/0, /*Opcode*/GIMT_Encode2(AMDGPU::GLOBAL_STORE_SHORT_D16_HI_SADDR),
      GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/1, // voffset
      GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/1, /*OpIdx*/1, // data
      GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/0, // saddr
      GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/2, // offset
      GIR_AddImm8, /*InsnID*/0, /*Imm*/0,
      GIR_MergeMemOperands, /*InsnID*/0, /*NumInsns*/2, /*MergeInsnID's*/0, 1,
      GIR_ConstrainSelectedInstOperands, /*InsnID*/0,
      GIR_EraseFromParent, /*InsnID*/0,
      // GIR_Coverage, 3113,
      GIR_Done,
    // Label 2031: @133150
    GIM_Try, /*On fail goto*//*Label 2032*/ GIMT_Encode4(133246), // Rule ID 3115 //
      GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasD16LoadStore),
      GIM_CheckMemorySizeLessThanLLT, /*MI*/0, /*MMO*/0, /*OpIdx*/0,
      GIM_CheckMemorySizeEqualTo, /*MI*/0, /*MMO*/0, /*Size*/GIMT_Encode4(1),
      GIM_CheckMemoryAddressSpace, /*MI*/0, /*MMO*/0, /*NumAddrSpace*/1, /*AddrSpace*/1,
      GIM_CheckAtomicOrdering, /*MI*/0, /*Order*/(uint8_t)AtomicOrdering::NotAtomic,
      GIM_RecordInsn, /*DefineMI*/1, /*MI*/0, /*OpIdx*/0, // MIs[1]
      GIM_CheckOpcode, /*MI*/1, GIMT_Encode2(TargetOpcode::G_LSHR),
      GIM_CheckType, /*MI*/1, /*Op*/1, /*Type*/GILLT_s32,
      GIM_CheckType, /*MI*/1, /*Op*/2, /*Type*/GILLT_s32,
      GIM_CheckConstantInt8, /*MI*/1, /*Op*/2, 16,
      GIM_CheckPointerToAny, /*MI*/0, /*Op*/1, /*SizeInBits*/0,
      GIM_CheckIsSafeToFold, /*InsnID*/1,
      GIM_CheckComplexPattern, /*MI*/0, /*Op*/1, /*Renderer*/GIMT_Encode2(0), GIMT_Encode2(GICP_gi_global_saddr),
      // (st (srl:{ *:[i32] } i32:{ *:[i32] }:$data, 16:{ *:[i32] }), (GlobalSAddr:{ *:[iPTR] } SReg_64:{ *:[i64] }:$saddr, VGPR_32:{ *:[i32] }:$voffset, i32:{ *:[i32] }:$offset))<<P:Predicate_unindexedstore>><<P:Predicate_truncstore>><<P:Predicate_truncstorei8>><<P:Predicate_truncstorei8_hi16_global>>  =>  (GLOBAL_STORE_BYTE_D16_HI_SADDR ?:{ *:[i32] }:$voffset, anonymous_15037:{ *:[i32] }:$data, ?:{ *:[i64] }:$saddr, ?:{ *:[i32] }:$offset)
      GIR_BuildMI, /*InsnID*/0, /*Opcode*/GIMT_Encode2(AMDGPU::GLOBAL_STORE_BYTE_D16_HI_SADDR),
      GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/1, // voffset
      GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/1, /*OpIdx*/1, // data
      GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/0, // saddr
      GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/2, // offset
      GIR_AddImm8, /*InsnID*/0, /*Imm*/0,
      GIR_MergeMemOperands, /*InsnID*/0, /*NumInsns*/2, /*MergeInsnID's*/0, 1,
      GIR_ConstrainSelectedInstOperands, /*InsnID*/0,
      GIR_EraseFromParent, /*InsnID*/0,
      // GIR_Coverage, 3115,
      GIR_Done,
    // Label 2032: @133246
    GIM_Try, /*On fail goto*//*Label 2033*/ GIMT_Encode4(133322), // Rule ID 3643 //
      GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasUnrestrictedSOffset),
      GIM_CheckMemorySizeLessThanLLT, /*MI*/0, /*MMO*/0, /*OpIdx*/0,
      GIM_CheckMemorySizeEqualTo, /*MI*/0, /*MMO*/0, /*Size*/GIMT_Encode4(1),
      GIM_CheckMemoryAddressSpace, /*MI*/0, /*MMO*/0, /*NumAddrSpace*/1, /*AddrSpace*/1,
      GIM_CheckAtomicOrdering, /*MI*/0, /*Order*/(uint8_t)AtomicOrdering::NotAtomic,
      GIM_CheckPointerToAny, /*MI*/0, /*Op*/1, /*SizeInBits*/0,
      GIM_CheckComplexPattern, /*MI*/0, /*Op*/1, /*Renderer*/GIMT_Encode2(0), GIMT_Encode2(GICP_gi_mubuf_offset),
      // (st i32:{ *:[i32] }:$vdata, (MUBUFOffset:{ *:[iPTR] } v4i32:{ *:[v4i32] }:$srsrc, i32:{ *:[i32] }:$soffset, i32:{ *:[i32] }:$offset))<<P:Predicate_unindexedstore>><<P:Predicate_truncstore>><<P:Predicate_truncstorei8>><<P:Predicate_truncstorei8_global>>  =>  (BUFFER_STORE_BYTE_OFFSET i32:{ *:[i32] }:$vdata, v4i32:{ *:[v4i32] }:$srsrc, i32:{ *:[i32] }:$soffset, i32:{ *:[i32] }:$offset)
      GIR_BuildMI, /*InsnID*/0, /*Opcode*/GIMT_Encode2(AMDGPU::BUFFER_STORE_BYTE_OFFSET),
      GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/0, // vdata
      GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/0, // srsrc
      GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/1, // soffset
      GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/2, // offset
      GIR_AddImm8, /*InsnID*/0, /*Imm*/0,
      GIR_AddImm8, /*InsnID*/0, /*Imm*/0,
      GIR_MergeMemOperands, /*InsnID*/0, /*NumInsns*/1, /*MergeInsnID's*/0,
      GIR_ConstrainSelectedInstOperands, /*InsnID*/0,
      GIR_EraseFromParent, /*InsnID*/0,
      // GIR_Coverage, 3643,
      GIR_Done,
    // Label 2033: @133322
    GIM_Try, /*On fail goto*//*Label 2034*/ GIMT_Encode4(133395), // Rule ID 3795 //
      GIM_CheckMemorySizeLessThanLLT, /*MI*/0, /*MMO*/0, /*OpIdx*/0,
      GIM_CheckMemorySizeEqualTo, /*MI*/0, /*MMO*/0, /*Size*/GIMT_Encode4(1),
      GIM_CheckMemoryAddressSpace, /*MI*/0, /*MMO*/0, /*NumAddrSpace*/1, /*AddrSpace*/1,
      GIM_CheckAtomicOrdering, /*MI*/0, /*Order*/(uint8_t)AtomicOrdering::NotAtomic,
      GIM_CheckPointerToAny, /*MI*/0, /*Op*/1, /*SizeInBits*/0,
      GIM_CheckComplexPattern, /*MI*/0, /*Op*/1, /*Renderer*/GIMT_Encode2(0), GIMT_Encode2(GICP_gi_mubuf_offset),
      // (st i32:{ *:[i32] }:$vdata, (MUBUFOffset:{ *:[iPTR] } v4i32:{ *:[v4i32] }:$srsrc, i32:{ *:[i32] }:$soffset, i32:{ *:[i32] }:$offset))<<P:Predicate_unindexedstore>><<P:Predicate_truncstore>><<P:Predicate_truncstorei8>><<P:Predicate_truncstorei8_global>>  =>  (BUFFER_STORE_BYTE_VBUFFER_OFFSET i32:{ *:[i32] }:$vdata, v4i32:{ *:[v4i32] }:$srsrc, i32:{ *:[i32] }:$soffset, i32:{ *:[i32] }:$offset)
      GIR_BuildMI, /*InsnID*/0, /*Opcode*/GIMT_Encode2(AMDGPU::BUFFER_STORE_BYTE_VBUFFER_OFFSET),
      GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/0, // vdata
      GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/0, // srsrc
      GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/1, // soffset
      GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/2, // offset
      GIR_AddImm8, /*InsnID*/0, /*Imm*/0,
      GIR_AddImm8, /*InsnID*/0, /*Imm*/0,
      GIR_MergeMemOperands, /*InsnID*/0, /*NumInsns*/1, /*MergeInsnID's*/0,
      GIR_ConstrainSelectedInstOperands, /*InsnID*/0,
      GIR_EraseFromParent, /*InsnID*/0,
      // GIR_Coverage, 3795,
      GIR_Done,
    // Label 2034: @133395
    GIM_Try, /*On fail goto*//*Label 2035*/ GIMT_Encode4(133471), // Rule ID 3797 //
      GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasUnrestrictedSOffset),
      GIM_CheckMemorySizeLessThanLLT, /*MI*/0, /*MMO*/0, /*OpIdx*/0,
      GIM_CheckMemorySizeEqualTo, /*MI*/0, /*MMO*/0, /*Size*/GIMT_Encode4(2),
      GIM_CheckMemoryAddressSpace, /*MI*/0, /*MMO*/0, /*NumAddrSpace*/1, /*AddrSpace*/1,
      GIM_CheckAtomicOrdering, /*MI*/0, /*Order*/(uint8_t)AtomicOrdering::NotAtomic,
      GIM_CheckPointerToAny, /*MI*/0, /*Op*/1, /*SizeInBits*/0,
      GIM_CheckComplexPattern, /*MI*/0, /*Op*/1, /*Renderer*/GIMT_Encode2(0), GIMT_Encode2(GICP_gi_mubuf_offset),
      // (st i32:{ *:[i32] }:$vdata, (MUBUFOffset:{ *:[iPTR] } v4i32:{ *:[v4i32] }:$srsrc, i32:{ *:[i32] }:$soffset, i32:{ *:[i32] }:$offset))<<P:Predicate_unindexedstore>><<P:Predicate_truncstore>><<P:Predicate_truncstorei16>><<P:Predicate_truncstorei16_global>>  =>  (BUFFER_STORE_SHORT_OFFSET i32:{ *:[i32] }:$vdata, v4i32:{ *:[v4i32] }:$srsrc, i32:{ *:[i32] }:$soffset, i32:{ *:[i32] }:$offset)
      GIR_BuildMI, /*InsnID*/0, /*Opcode*/GIMT_Encode2(AMDGPU::BUFFER_STORE_SHORT_OFFSET),
      GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/0, // vdata
      GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/0, // srsrc
      GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/1, // soffset
      GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/2, // offset
      GIR_AddImm8, /*InsnID*/0, /*Imm*/0,
      GIR_AddImm8, /*InsnID*/0, /*Imm*/0,
      GIR_MergeMemOperands, /*InsnID*/0, /*NumInsns*/1, /*MergeInsnID's*/0,
      GIR_ConstrainSelectedInstOperands, /*InsnID*/0,
      GIR_EraseFromParent, /*InsnID*/0,
      // GIR_Coverage, 3797,
      GIR_Done,
    // Label 2035: @133471
    GIM_Try, /*On fail goto*//*Label 2036*/ GIMT_Encode4(133544), // Rule ID 3799 //
      GIM_CheckMemorySizeLessThanLLT, /*MI*/0, /*MMO*/0, /*OpIdx*/0,
      GIM_CheckMemorySizeEqualTo, /*MI*/0, /*MMO*/0, /*Size*/GIMT_Encode4(2),
      GIM_CheckMemoryAddressSpace, /*MI*/0, /*MMO*/0, /*NumAddrSpace*/1, /*AddrSpace*/1,
      GIM_CheckAtomicOrdering, /*MI*/0, /*Order*/(uint8_t)AtomicOrdering::NotAtomic,
      GIM_CheckPointerToAny, /*MI*/0, /*Op*/1, /*SizeInBits*/0,
      GIM_CheckComplexPattern, /*MI*/0, /*Op*/1, /*Renderer*/GIMT_Encode2(0), GIMT_Encode2(GICP_gi_mubuf_offset),
      // (st i32:{ *:[i32] }:$vdata, (MUBUFOffset:{ *:[iPTR] } v4i32:{ *:[v4i32] }:$srsrc, i32:{ *:[i32] }:$soffset, i32:{ *:[i32] }:$offset))<<P:Predicate_unindexedstore>><<P:Predicate_truncstore>><<P:Predicate_truncstorei16>><<P:Predicate_truncstorei16_global>>  =>  (BUFFER_STORE_SHORT_VBUFFER_OFFSET i32:{ *:[i32] }:$vdata, v4i32:{ *:[v4i32] }:$srsrc, i32:{ *:[i32] }:$soffset, i32:{ *:[i32] }:$offset)
      GIR_BuildMI, /*InsnID*/0, /*Opcode*/GIMT_Encode2(AMDGPU::BUFFER_STORE_SHORT_VBUFFER_OFFSET),
      GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/0, // vdata
      GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/0, // srsrc
      GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/1, // soffset
      GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/2, // offset
      GIR_AddImm8, /*InsnID*/0, /*Imm*/0,
      GIR_AddImm8, /*InsnID*/0, /*Imm*/0,
      GIR_MergeMemOperands, /*InsnID*/0, /*NumInsns*/1, /*MergeInsnID's*/0,
      GIR_ConstrainSelectedInstOperands, /*InsnID*/0,
      GIR_EraseFromParent, /*InsnID*/0,
      // GIR_Coverage, 3799,
      GIR_Done,
    // Label 2036: @133544
    GIM_Try, /*On fail goto*//*Label 2037*/ GIMT_Encode4(133609), // Rule ID 3801 //
      GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasUnrestrictedSOffset),
      GIM_CheckMemoryAddressSpace, /*MI*/0, /*MMO*/0, /*NumAddrSpace*/1, /*AddrSpace*/1,
      GIM_CheckAtomicOrdering, /*MI*/0, /*Order*/(uint8_t)AtomicOrdering::NotAtomic,
      GIM_CheckPointerToAny, /*MI*/0, /*Op*/1, /*SizeInBits*/0,
      GIM_CheckComplexPattern, /*MI*/0, /*Op*/1, /*Renderer*/GIMT_Encode2(0), GIMT_Encode2(GICP_gi_mubuf_offset),
      // (st i32:{ *:[i32] }:$vdata, (MUBUFOffset:{ *:[iPTR] } v4i32:{ *:[v4i32] }:$srsrc, i32:{ *:[i32] }:$soffset, i32:{ *:[i32] }:$offset))<<P:Predicate_unindexedstore>><<P:Predicate_store_global>>  =>  (BUFFER_STORE_DWORD_OFFSET i32:{ *:[i32] }:$vdata, v4i32:{ *:[v4i32] }:$srsrc, i32:{ *:[i32] }:$soffset, i32:{ *:[i32] }:$offset)
      GIR_BuildMI, /*InsnID*/0, /*Opcode*/GIMT_Encode2(AMDGPU::BUFFER_STORE_DWORD_OFFSET),
      GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/0, // vdata
      GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/0, // srsrc
      GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/1, // soffset
      GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/2, // offset
      GIR_AddImm8, /*InsnID*/0, /*Imm*/0,
      GIR_AddImm8, /*InsnID*/0, /*Imm*/0,
      GIR_MergeMemOperands, /*InsnID*/0, /*NumInsns*/1, /*MergeInsnID's*/0,
      GIR_ConstrainSelectedInstOperands, /*InsnID*/0,
      GIR_EraseFromParent, /*InsnID*/0,
      // GIR_Coverage, 3801,
      GIR_Done,
    // Label 2037: @133609
    GIM_Try, /*On fail goto*//*Label 2038*/ GIMT_Encode4(133671), // Rule ID 3803 //
      GIM_CheckMemoryAddressSpace, /*MI*/0, /*MMO*/0, /*NumAddrSpace*/1, /*AddrSpace*/1,
      GIM_CheckAtomicOrdering, /*MI*/0, /*Order*/(uint8_t)AtomicOrdering::NotAtomic,
      GIM_CheckPointerToAny, /*MI*/0, /*Op*/1, /*SizeInBits*/0,
      GIM_CheckComplexPattern, /*MI*/0, /*Op*/1, /*Renderer*/GIMT_Encode2(0), GIMT_Encode2(GICP_gi_mubuf_offset),
      // (st i32:{ *:[i32] }:$vdata, (MUBUFOffset:{ *:[iPTR] } v4i32:{ *:[v4i32] }:$srsrc, i32:{ *:[i32] }:$soffset, i32:{ *:[i32] }:$offset))<<P:Predicate_unindexedstore>><<P:Predicate_store_global>>  =>  (BUFFER_STORE_DWORD_VBUFFER_OFFSET i32:{ *:[i32] }:$vdata, v4i32:{ *:[v4i32] }:$srsrc, i32:{ *:[i32] }:$soffset, i32:{ *:[i32] }:$offset)
      GIR_BuildMI, /*InsnID*/0, /*Opcode*/GIMT_Encode2(AMDGPU::BUFFER_STORE_DWORD_VBUFFER_OFFSET),
      GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/0, // vdata
      GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/0, // srsrc
      GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/1, // soffset
      GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/2, // offset
      GIR_AddImm8, /*InsnID*/0, /*Imm*/0,
      GIR_AddImm8, /*InsnID*/0, /*Imm*/0,
      GIR_MergeMemOperands, /*InsnID*/0, /*NumInsns*/1, /*MergeInsnID's*/0,
      GIR_ConstrainSelectedInstOperands, /*InsnID*/0,
      GIR_EraseFromParent, /*InsnID*/0,
      // GIR_Coverage, 3803,
      GIR_Done,
    // Label 2038: @133671
    GIM_Try, /*On fail goto*//*Label 2039*/ GIMT_Encode4(133736), // Rule ID 3805 //
      GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasUnrestrictedSOffset),
      GIM_CheckMemoryAddressSpace, /*MI*/0, /*MMO*/0, /*NumAddrSpace*/1, /*AddrSpace*/1,
      GIM_CheckAtomicOrdering, /*MI*/0, /*Order*/(uint8_t)AtomicOrdering::NotAtomic,
      GIM_CheckPointerToAny, /*MI*/0, /*Op*/1, /*SizeInBits*/0,
      GIM_CheckComplexPattern, /*MI*/0, /*Op*/1, /*Renderer*/GIMT_Encode2(0), GIMT_Encode2(GICP_gi_mubuf_offset),
      // (st f32:{ *:[f32] }:$vdata, (MUBUFOffset:{ *:[iPTR] } v4i32:{ *:[v4i32] }:$srsrc, i32:{ *:[i32] }:$soffset, i32:{ *:[i32] }:$offset))<<P:Predicate_unindexedstore>><<P:Predicate_store_global>>  =>  (BUFFER_STORE_DWORD_OFFSET f32:{ *:[f32] }:$vdata, v4i32:{ *:[v4i32] }:$srsrc, i32:{ *:[i32] }:$soffset, i32:{ *:[i32] }:$offset)
      GIR_BuildMI, /*InsnID*/0, /*Opcode*/GIMT_Encode2(AMDGPU::BUFFER_STORE_DWORD_OFFSET),
      GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/0, // vdata
      GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/0, // srsrc
      GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/1, // soffset
      GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/2, // offset
      GIR_AddImm8, /*InsnID*/0, /*Imm*/0,
      GIR_AddImm8, /*InsnID*/0, /*Imm*/0,
      GIR_MergeMemOperands, /*InsnID*/0, /*NumInsns*/1, /*MergeInsnID's*/0,
      GIR_ConstrainSelectedInstOperands, /*InsnID*/0,
      GIR_EraseFromParent, /*InsnID*/0,
      // GIR_Coverage, 3805,
      GIR_Done,
    // Label 2039: @133736
    GIM_Try, /*On fail goto*//*Label 2040*/ GIMT_Encode4(133798), // Rule ID 3807 //
      GIM_CheckMemoryAddressSpace, /*MI*/0, /*MMO*/0, /*NumAddrSpace*/1, /*AddrSpace*/1,
      GIM_CheckAtomicOrdering, /*MI*/0, /*Order*/(uint8_t)AtomicOrdering::NotAtomic,
      GIM_CheckPointerToAny, /*MI*/0, /*Op*/1, /*SizeInBits*/0,
      GIM_CheckComplexPattern, /*MI*/0, /*Op*/1, /*Renderer*/GIMT_Encode2(0), GIMT_Encode2(GICP_gi_mubuf_offset),
      // (st f32:{ *:[f32] }:$vdata, (MUBUFOffset:{ *:[iPTR] } v4i32:{ *:[v4i32] }:$srsrc, i32:{ *:[i32] }:$soffset, i32:{ *:[i32] }:$offset))<<P:Predicate_unindexedstore>><<P:Predicate_store_global>>  =>  (BUFFER_STORE_DWORD_VBUFFER_OFFSET f32:{ *:[f32] }:$vdata, v4i32:{ *:[v4i32] }:$srsrc, i32:{ *:[i32] }:$soffset, i32:{ *:[i32] }:$offset)
      GIR_BuildMI, /*InsnID*/0, /*Opcode*/GIMT_Encode2(AMDGPU::BUFFER_STORE_DWORD_VBUFFER_OFFSET),
      GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/0, // vdata
      GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/0, // srsrc
      GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/1, // soffset
      GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/2, // offset
      GIR_AddImm8, /*InsnID*/0, /*Imm*/0,
      GIR_AddImm8, /*InsnID*/0, /*Imm*/0,
      GIR_MergeMemOperands, /*InsnID*/0, /*NumInsns*/1, /*MergeInsnID's*/0,
      GIR_ConstrainSelectedInstOperands, /*InsnID*/0,
      GIR_EraseFromParent, /*InsnID*/0,
      // GIR_Coverage, 3807,
      GIR_Done,
    // Label 2040: @133798
    GIM_Try, /*On fail goto*//*Label 2041*/ GIMT_Encode4(133889), // Rule ID 3112 //
      GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasD16LoadStore),
      GIM_CheckMemorySizeLessThanLLT, /*MI*/0, /*MMO*/0, /*OpIdx*/0,
      GIM_CheckMemorySizeEqualTo, /*MI*/0, /*MMO*/0, /*Size*/GIMT_Encode4(2),
      GIM_CheckMemoryAddressSpace, /*MI*/0, /*MMO*/0, /*NumAddrSpace*/1, /*AddrSpace*/1,
      GIM_CheckAtomicOrdering, /*MI*/0, /*Order*/(uint8_t)AtomicOrdering::NotAtomic,
      GIM_RecordInsn, /*DefineMI*/1, /*MI*/0, /*OpIdx*/0, // MIs[1]
      GIM_CheckOpcode, /*MI*/1, GIMT_Encode2(TargetOpcode::G_LSHR),
      GIM_CheckType, /*MI*/1, /*Op*/1, /*Type*/GILLT_s32,
      GIM_CheckType, /*MI*/1, /*Op*/2, /*Type*/GILLT_s32,
      GIM_CheckConstantInt8, /*MI*/1, /*Op*/2, 16,
      GIM_CheckPointerToAny, /*MI*/0, /*Op*/1, /*SizeInBits*/0,
      GIM_CheckIsSafeToFold, /*InsnID*/1,
      GIM_CheckComplexPattern, /*MI*/0, /*Op*/1, /*Renderer*/GIMT_Encode2(0), GIMT_Encode2(GICP_gi_global_offset),
      // (st (srl:{ *:[i32] } i32:{ *:[i32] }:$data, 16:{ *:[i32] }), (GlobalOffset:{ *:[iPTR] } i64:{ *:[i64] }:$vaddr, i32:{ *:[i32] }:$offset))<<P:Predicate_unindexedstore>><<P:Predicate_truncstore>><<P:Predicate_truncstorei16>><<P:Predicate_truncstorei16_hi16_global>>  =>  (GLOBAL_STORE_SHORT_D16_HI ?:{ *:[i64] }:$vaddr, anonymous_15037:{ *:[i32] }:$data, ?:{ *:[i32] }:$offset)
      GIR_BuildMI, /*InsnID*/0, /*Opcode*/GIMT_Encode2(AMDGPU::GLOBAL_STORE_SHORT_D16_HI),
      GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/0, // vaddr
      GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/1, /*OpIdx*/1, // data
      GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/1, // offset
      GIR_AddImm8, /*InsnID*/0, /*Imm*/0,
      GIR_MergeMemOperands, /*InsnID*/0, /*NumInsns*/2, /*MergeInsnID's*/0, 1,
      GIR_ConstrainSelectedInstOperands, /*InsnID*/0,
      GIR_EraseFromParent, /*InsnID*/0,
      // GIR_Coverage, 3112,
      GIR_Done,
    // Label 2041: @133889
    GIM_Try, /*On fail goto*//*Label 2042*/ GIMT_Encode4(133980), // Rule ID 3114 //
      GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasD16LoadStore),
      GIM_CheckMemorySizeLessThanLLT, /*MI*/0, /*MMO*/0, /*OpIdx*/0,
      GIM_CheckMemorySizeEqualTo, /*MI*/0, /*MMO*/0, /*Size*/GIMT_Encode4(1),
      GIM_CheckMemoryAddressSpace, /*MI*/0, /*MMO*/0, /*NumAddrSpace*/1, /*AddrSpace*/1,
      GIM_CheckAtomicOrdering, /*MI*/0, /*Order*/(uint8_t)AtomicOrdering::NotAtomic,
      GIM_RecordInsn, /*DefineMI*/1, /*MI*/0, /*OpIdx*/0, // MIs[1]
      GIM_CheckOpcode, /*MI*/1, GIMT_Encode2(TargetOpcode::G_LSHR),
      GIM_CheckType, /*MI*/1, /*Op*/1, /*Type*/GILLT_s32,
      GIM_CheckType, /*MI*/1, /*Op*/2, /*Type*/GILLT_s32,
      GIM_CheckConstantInt8, /*MI*/1, /*Op*/2, 16,
      GIM_CheckPointerToAny, /*MI*/0, /*Op*/1, /*SizeInBits*/0,
      GIM_CheckIsSafeToFold, /*InsnID*/1,
      GIM_CheckComplexPattern, /*MI*/0, /*Op*/1, /*Renderer*/GIMT_Encode2(0), GIMT_Encode2(GICP_gi_global_offset),
      // (st (srl:{ *:[i32] } i32:{ *:[i32] }:$data, 16:{ *:[i32] }), (GlobalOffset:{ *:[iPTR] } i64:{ *:[i64] }:$vaddr, i32:{ *:[i32] }:$offset))<<P:Predicate_unindexedstore>><<P:Predicate_truncstore>><<P:Predicate_truncstorei8>><<P:Predicate_truncstorei8_hi16_global>>  =>  (GLOBAL_STORE_BYTE_D16_HI ?:{ *:[i64] }:$vaddr, anonymous_15037:{ *:[i32] }:$data, ?:{ *:[i32] }:$offset)
      GIR_BuildMI, /*InsnID*/0, /*Opcode*/GIMT_Encode2(AMDGPU::GLOBAL_STORE_BYTE_D16_HI),
      GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/0, // vaddr
      GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/1, /*OpIdx*/1, // data
      GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/1, // offset
      GIR_AddImm8, /*InsnID*/0, /*Imm*/0,
      GIR_MergeMemOperands, /*InsnID*/0, /*NumInsns*/2, /*MergeInsnID's*/0, 1,
      GIR_ConstrainSelectedInstOperands, /*InsnID*/0,
      GIR_EraseFromParent, /*InsnID*/0,
      // GIR_Coverage, 3114,
      GIR_Done,
    // Label 2042: @133980
    GIM_Try, /*On fail goto*//*Label 2043*/ GIMT_Encode4(134044), // Rule ID 6659 //
      GIM_CheckFeatures, GIMT_Encode2(GIFBS_LDSRequiresM0Init),
      GIM_CheckMemorySizeEqualTo, /*MI*/0, /*MMO*/0, /*Size*/GIMT_Encode4(1),
      GIM_CheckMemoryAddressSpace, /*MI*/0, /*MMO*/0, /*NumAddrSpace*/1, /*AddrSpace*/3,
      GIM_CheckAtomicOrderingOrStrongerThan, /*MI*/0, /*Order*/(uint8_t)AtomicOrdering::Unordered,
      GIM_CheckPointerToAny, /*MI*/0, /*Op*/1, /*SizeInBits*/0,
      GIM_CheckComplexPattern, /*MI*/0, /*Op*/1, /*Renderer*/GIMT_Encode2(0), GIMT_Encode2(GICP_gi_ds_1addr_1offset),
      // (AMDGPUatomic_st_glue i32:{ *:[i32] }:$value, (DS1Addr1Offset:{ *:[iPTR] } i32:{ *:[i32] }:$ptr, i32:{ *:[i32] }:$offset))<<P:Predicate_atomic_store_8_glue>><<P:Predicate_atomic_store_8_local_m0>>  =>  (DS_WRITE_B8 ?:{ *:[i32] }:$ptr, anonymous_15037:{ *:[i32] }:$value, offset:{ *:[i32] }:$offset, 0:{ *:[i1] })
      GIR_BuildMI, /*InsnID*/0, /*Opcode*/GIMT_Encode2(AMDGPU::DS_WRITE_B8),
      GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/0, // ptr
      GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/0, // value
      GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/1, // offset
      GIR_AddImm8, /*InsnID*/0, /*Imm*/0,
      GIR_MergeMemOperands, /*InsnID*/0, /*NumInsns*/1, /*MergeInsnID's*/0,
      GIR_ConstrainSelectedInstOperands, /*InsnID*/0,
      GIR_EraseFromParent, /*InsnID*/0,
      // GIR_Coverage, 6659,
      GIR_Done,
    // Label 2043: @134044
    GIM_Try, /*On fail goto*//*Label 2044*/ GIMT_Encode4(134108), // Rule ID 6660 //
      GIM_CheckFeatures, GIMT_Encode2(GIFBS_NotLDSRequiresM0Init),
      GIM_CheckMemorySizeEqualTo, /*MI*/0, /*MMO*/0, /*Size*/GIMT_Encode4(1),
      GIM_CheckMemoryAddressSpace, /*MI*/0, /*MMO*/0, /*NumAddrSpace*/1, /*AddrSpace*/3,
      GIM_CheckAtomicOrderingOrStrongerThan, /*MI*/0, /*Order*/(uint8_t)AtomicOrdering::Unordered,
      GIM_CheckPointerToAny, /*MI*/0, /*Op*/1, /*SizeInBits*/0,
      GIM_CheckComplexPattern, /*MI*/0, /*Op*/1, /*Renderer*/GIMT_Encode2(0), GIMT_Encode2(GICP_gi_ds_1addr_1offset),
      // (atomic_store i32:{ *:[i32] }:$value, (DS1Addr1Offset:{ *:[iPTR] } i32:{ *:[i32] }:$ptr, i32:{ *:[i32] }:$offset))<<P:Predicate_atomic_store_8>><<P:Predicate_atomic_store_8_local>>  =>  (DS_WRITE_B8_gfx9 ?:{ *:[i32] }:$ptr, anonymous_15037:{ *:[i32] }:$value, offset:{ *:[i32] }:$offset, 0:{ *:[i1] })
      GIR_BuildMI, /*InsnID*/0, /*Opcode*/GIMT_Encode2(AMDGPU::DS_WRITE_B8_gfx9),
      GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/0, // ptr
      GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/0, // value
      GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/1, // offset
      GIR_AddImm8, /*InsnID*/0, /*Imm*/0,
      GIR_MergeMemOperands, /*InsnID*/0, /*NumInsns*/1, /*MergeInsnID's*/0,
      GIR_ConstrainSelectedInstOperands, /*InsnID*/0,
      GIR_EraseFromParent, /*InsnID*/0,
      // GIR_Coverage, 6660,
      GIR_Done,
    // Label 2044: @134108
    GIM_Try, /*On fail goto*//*Label 2045*/ GIMT_Encode4(134172), // Rule ID 6663 //
      GIM_CheckFeatures, GIMT_Encode2(GIFBS_LDSRequiresM0Init),
      GIM_CheckMemorySizeEqualTo, /*MI*/0, /*MMO*/0, /*Size*/GIMT_Encode4(2),
      GIM_CheckMemoryAddressSpace, /*MI*/0, /*MMO*/0, /*NumAddrSpace*/1, /*AddrSpace*/3,
      GIM_CheckAtomicOrderingOrStrongerThan, /*MI*/0, /*Order*/(uint8_t)AtomicOrdering::Unordered,
      GIM_CheckPointerToAny, /*MI*/0, /*Op*/1, /*SizeInBits*/0,
      GIM_CheckComplexPattern, /*MI*/0, /*Op*/1, /*Renderer*/GIMT_Encode2(0), GIMT_Encode2(GICP_gi_ds_1addr_1offset),
      // (AMDGPUatomic_st_glue i32:{ *:[i32] }:$value, (DS1Addr1Offset:{ *:[iPTR] } i32:{ *:[i32] }:$ptr, i32:{ *:[i32] }:$offset))<<P:Predicate_atomic_store_16_glue>><<P:Predicate_atomic_store_16_local_m0>>  =>  (DS_WRITE_B16 ?:{ *:[i32] }:$ptr, anonymous_15037:{ *:[i32] }:$value, offset:{ *:[i32] }:$offset, 0:{ *:[i1] })
      GIR_BuildMI, /*InsnID*/0, /*Opcode*/GIMT_Encode2(AMDGPU::DS_WRITE_B16),
      GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/0, // ptr
      GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/0, // value
      GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/1, // offset
      GIR_AddImm8, /*InsnID*/0, /*Imm*/0,
      GIR_MergeMemOperands, /*InsnID*/0, /*NumInsns*/1, /*MergeInsnID's*/0,
      GIR_ConstrainSelectedInstOperands, /*InsnID*/0,
      GIR_EraseFromParent, /*InsnID*/0,
      // GIR_Coverage, 6663,
      GIR_Done,
    // Label 2045: @134172
    GIM_Try, /*On fail goto*//*Label 2046*/ GIMT_Encode4(134236), // Rule ID 6664 //
      GIM_CheckFeatures, GIMT_Encode2(GIFBS_NotLDSRequiresM0Init),
      GIM_CheckMemorySizeEqualTo, /*MI*/0, /*MMO*/0, /*Size*/GIMT_Encode4(2),
      GIM_CheckMemoryAddressSpace, /*MI*/0, /*MMO*/0, /*NumAddrSpace*/1, /*AddrSpace*/3,
      GIM_CheckAtomicOrderingOrStrongerThan, /*MI*/0, /*Order*/(uint8_t)AtomicOrdering::Unordered,
      GIM_CheckPointerToAny, /*MI*/0, /*Op*/1, /*SizeInBits*/0,
      GIM_CheckComplexPattern, /*MI*/0, /*Op*/1, /*Renderer*/GIMT_Encode2(0), GIMT_Encode2(GICP_gi_ds_1addr_1offset),
      // (atomic_store i32:{ *:[i32] }:$value, (DS1Addr1Offset:{ *:[iPTR] } i32:{ *:[i32] }:$ptr, i32:{ *:[i32] }:$offset))<<P:Predicate_atomic_store_16>><<P:Predicate_atomic_store_16_local>>  =>  (DS_WRITE_B16_gfx9 ?:{ *:[i32] }:$ptr, anonymous_15037:{ *:[i32] }:$value, offset:{ *:[i32] }:$offset, 0:{ *:[i1] })
      GIR_BuildMI, /*InsnID*/0, /*Opcode*/GIMT_Encode2(AMDGPU::DS_WRITE_B16_gfx9),
      GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/0, // ptr
      GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/0, // value
      GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/1, // offset
      GIR_AddImm8, /*InsnID*/0, /*Imm*/0,
      GIR_MergeMemOperands, /*InsnID*/0, /*NumInsns*/1, /*MergeInsnID's*/0,
      GIR_ConstrainSelectedInstOperands, /*InsnID*/0,
      GIR_EraseFromParent, /*InsnID*/0,
      // GIR_Coverage, 6664,
      GIR_Done,
    // Label 2046: @134236
    GIM_Try, /*On fail goto*//*Label 2047*/ GIMT_Encode4(134300), // Rule ID 6665 //
      GIM_CheckFeatures, GIMT_Encode2(GIFBS_LDSRequiresM0Init),
      GIM_CheckMemorySizeEqualTo, /*MI*/0, /*MMO*/0, /*Size*/GIMT_Encode4(4),
      GIM_CheckMemoryAddressSpace, /*MI*/0, /*MMO*/0, /*NumAddrSpace*/1, /*AddrSpace*/3,
      GIM_CheckAtomicOrderingOrStrongerThan, /*MI*/0, /*Order*/(uint8_t)AtomicOrdering::Unordered,
      GIM_CheckPointerToAny, /*MI*/0, /*Op*/1, /*SizeInBits*/0,
      GIM_CheckComplexPattern, /*MI*/0, /*Op*/1, /*Renderer*/GIMT_Encode2(0), GIMT_Encode2(GICP_gi_ds_1addr_1offset),
      // (AMDGPUatomic_st_glue i32:{ *:[i32] }:$value, (DS1Addr1Offset:{ *:[iPTR] } i32:{ *:[i32] }:$ptr, i32:{ *:[i32] }:$offset))<<P:Predicate_atomic_store_32_glue>><<P:Predicate_atomic_store_32_local_m0>>  =>  (DS_WRITE_B32 ?:{ *:[i32] }:$ptr, anonymous_15037:{ *:[i32] }:$value, offset:{ *:[i32] }:$offset, 0:{ *:[i1] })
      GIR_BuildMI, /*InsnID*/0, /*Opcode*/GIMT_Encode2(AMDGPU::DS_WRITE_B32),
      GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/0, // ptr
      GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/0, // value
      GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/1, // offset
      GIR_AddImm8, /*InsnID*/0, /*Imm*/0,
      GIR_MergeMemOperands, /*InsnID*/0, /*NumInsns*/1, /*MergeInsnID's*/0,
      GIR_ConstrainSelectedInstOperands, /*InsnID*/0,
      GIR_EraseFromParent, /*InsnID*/0,
      // GIR_Coverage, 6665,
      GIR_Done,
    // Label 2047: @134300
    GIM_Try, /*On fail goto*//*Label 2048*/ GIMT_Encode4(134364), // Rule ID 6666 //
      GIM_CheckFeatures, GIMT_Encode2(GIFBS_NotLDSRequiresM0Init),
      GIM_CheckMemorySizeEqualTo, /*MI*/0, /*MMO*/0, /*Size*/GIMT_Encode4(4),
      GIM_CheckMemoryAddressSpace, /*MI*/0, /*MMO*/0, /*NumAddrSpace*/1, /*AddrSpace*/3,
      GIM_CheckAtomicOrderingOrStrongerThan, /*MI*/0, /*Order*/(uint8_t)AtomicOrdering::Unordered,
      GIM_CheckPointerToAny, /*MI*/0, /*Op*/1, /*SizeInBits*/0,
      GIM_CheckComplexPattern, /*MI*/0, /*Op*/1, /*Renderer*/GIMT_Encode2(0), GIMT_Encode2(GICP_gi_ds_1addr_1offset),
      // (atomic_store i32:{ *:[i32] }:$value, (DS1Addr1Offset:{ *:[iPTR] } i32:{ *:[i32] }:$ptr, i32:{ *:[i32] }:$offset))<<P:Predicate_atomic_store_32>><<P:Predicate_atomic_store_32_local>>  =>  (DS_WRITE_B32_gfx9 ?:{ *:[i32] }:$ptr, anonymous_15037:{ *:[i32] }:$value, offset:{ *:[i32] }:$offset, 0:{ *:[i1] })
      GIR_BuildMI, /*InsnID*/0, /*Opcode*/GIMT_Encode2(AMDGPU::DS_WRITE_B32_gfx9),
      GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/0, // ptr
      GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/0, // value
      GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/1, // offset
      GIR_AddImm8, /*InsnID*/0, /*Imm*/0,
      GIR_MergeMemOperands, /*InsnID*/0, /*NumInsns*/1, /*MergeInsnID's*/0,
      GIR_ConstrainSelectedInstOperands, /*InsnID*/0,
      GIR_EraseFromParent, /*InsnID*/0,
      // GIR_Coverage, 6666,
      GIR_Done,
    // Label 2048: @134364
    GIM_Try, /*On fail goto*//*Label 2049*/ GIMT_Encode4(134432), // Rule ID 6631 //
      GIM_CheckFeatures, GIMT_Encode2(GIFBS_LDSRequiresM0Init),
      GIM_CheckMemorySizeLessThanLLT, /*MI*/0, /*MMO*/0, /*OpIdx*/0,
      GIM_CheckMemorySizeEqualTo, /*MI*/0, /*MMO*/0, /*Size*/GIMT_Encode4(1),
      GIM_CheckMemoryAddressSpace, /*MI*/0, /*MMO*/0, /*NumAddrSpace*/1, /*AddrSpace*/3,
      GIM_CheckAtomicOrdering, /*MI*/0, /*Order*/(uint8_t)AtomicOrdering::NotAtomic,
      GIM_CheckPointerToAny, /*MI*/0, /*Op*/1, /*SizeInBits*/0,
      GIM_CheckComplexPattern, /*MI*/0, /*Op*/1, /*Renderer*/GIMT_Encode2(0), GIMT_Encode2(GICP_gi_ds_1addr_1offset),
      // (AMDGPUst_glue i32:{ *:[i32] }:$value, (DS1Addr1Offset:{ *:[iPTR] } i32:{ *:[i32] }:$ptr, i32:{ *:[i32] }:$offset))<<P:Predicate_unindexedstore_glue>><<P:Predicate_truncstore_glue>><<P:Predicate_truncstorei8_glue>><<P:Predicate_truncstorei8_local_m0>>  =>  (DS_WRITE_B8 ?:{ *:[i32] }:$ptr, anonymous_15037:{ *:[i32] }:$value, offset:{ *:[i32] }:$offset, 0:{ *:[i1] })
      GIR_BuildMI, /*InsnID*/0, /*Opcode*/GIMT_Encode2(AMDGPU::DS_WRITE_B8),
      GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/0, // ptr
      GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/0, // value
      GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/1, // offset
      GIR_AddImm8, /*InsnID*/0, /*Imm*/0,
      GIR_MergeMemOperands, /*InsnID*/0, /*NumInsns*/1, /*MergeInsnID's*/0,
      GIR_ConstrainSelectedInstOperands, /*InsnID*/0,
      GIR_EraseFromParent, /*InsnID*/0,
      // GIR_Coverage, 6631,
      GIR_Done,
    // Label 2049: @134432
    GIM_Try, /*On fail goto*//*Label 2050*/ GIMT_Encode4(134500), // Rule ID 6632 //
      GIM_CheckFeatures, GIMT_Encode2(GIFBS_NotLDSRequiresM0Init),
      GIM_CheckMemorySizeLessThanLLT, /*MI*/0, /*MMO*/0, /*OpIdx*/0,
      GIM_CheckMemorySizeEqualTo, /*MI*/0, /*MMO*/0, /*Size*/GIMT_Encode4(1),
      GIM_CheckMemoryAddressSpace, /*MI*/0, /*MMO*/0, /*NumAddrSpace*/1, /*AddrSpace*/3,
      GIM_CheckAtomicOrdering, /*MI*/0, /*Order*/(uint8_t)AtomicOrdering::NotAtomic,
      GIM_CheckPointerToAny, /*MI*/0, /*Op*/1, /*SizeInBits*/0,
      GIM_CheckComplexPattern, /*MI*/0, /*Op*/1, /*Renderer*/GIMT_Encode2(0), GIMT_Encode2(GICP_gi_ds_1addr_1offset),
      // (st i32:{ *:[i32] }:$value, (DS1Addr1Offset:{ *:[iPTR] } i32:{ *:[i32] }:$ptr, i32:{ *:[i32] }:$offset))<<P:Predicate_unindexedstore>><<P:Predicate_truncstore>><<P:Predicate_truncstorei8>><<P:Predicate_truncstorei8_local>>  =>  (DS_WRITE_B8_gfx9 ?:{ *:[i32] }:$ptr, anonymous_15037:{ *:[i32] }:$value, offset:{ *:[i32] }:$offset, 0:{ *:[i1] })
      GIR_BuildMI, /*InsnID*/0, /*Opcode*/GIMT_Encode2(AMDGPU::DS_WRITE_B8_gfx9),
      GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/0, // ptr
      GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/0, // value
      GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/1, // offset
      GIR_AddImm8, /*InsnID*/0, /*Imm*/0,
      GIR_MergeMemOperands, /*InsnID*/0, /*NumInsns*/1, /*MergeInsnID's*/0,
      GIR_ConstrainSelectedInstOperands, /*InsnID*/0,
      GIR_EraseFromParent, /*InsnID*/0,
      // GIR_Coverage, 6632,
      GIR_Done,
    // Label 2050: @134500
    GIM_Try, /*On fail goto*//*Label 2051*/ GIMT_Encode4(134568), // Rule ID 6633 //
      GIM_CheckFeatures, GIMT_Encode2(GIFBS_LDSRequiresM0Init),
      GIM_CheckMemorySizeLessThanLLT, /*MI*/0, /*MMO*/0, /*OpIdx*/0,
      GIM_CheckMemorySizeEqualTo, /*MI*/0, /*MMO*/0, /*Size*/GIMT_Encode4(2),
      GIM_CheckMemoryAddressSpace, /*MI*/0, /*MMO*/0, /*NumAddrSpace*/1, /*AddrSpace*/3,
      GIM_CheckAtomicOrdering, /*MI*/0, /*Order*/(uint8_t)AtomicOrdering::NotAtomic,
      GIM_CheckPointerToAny, /*MI*/0, /*Op*/1, /*SizeInBits*/0,
      GIM_CheckComplexPattern, /*MI*/0, /*Op*/1, /*Renderer*/GIMT_Encode2(0), GIMT_Encode2(GICP_gi_ds_1addr_1offset),
      // (AMDGPUst_glue i32:{ *:[i32] }:$value, (DS1Addr1Offset:{ *:[iPTR] } i32:{ *:[i32] }:$ptr, i32:{ *:[i32] }:$offset))<<P:Predicate_unindexedstore_glue>><<P:Predicate_truncstore_glue>><<P:Predicate_truncstorei16_glue>><<P:Predicate_truncstorei16_local_m0>>  =>  (DS_WRITE_B16 ?:{ *:[i32] }:$ptr, anonymous_15037:{ *:[i32] }:$value, offset:{ *:[i32] }:$offset, 0:{ *:[i1] })
      GIR_BuildMI, /*InsnID*/0, /*Opcode*/GIMT_Encode2(AMDGPU::DS_WRITE_B16),
      GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/0, // ptr
      GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/0, // value
      GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/1, // offset
      GIR_AddImm8, /*InsnID*/0, /*Imm*/0,
      GIR_MergeMemOperands, /*InsnID*/0, /*NumInsns*/1, /*MergeInsnID's*/0,
      GIR_ConstrainSelectedInstOperands, /*InsnID*/0,
      GIR_EraseFromParent, /*InsnID*/0,
      // GIR_Coverage, 6633,
      GIR_Done,
    // Label 2051: @134568
    GIM_Try, /*On fail goto*//*Label 2052*/ GIMT_Encode4(134636), // Rule ID 6634 //
      GIM_CheckFeatures, GIMT_Encode2(GIFBS_NotLDSRequiresM0Init),
      GIM_CheckMemorySizeLessThanLLT, /*MI*/0, /*MMO*/0, /*OpIdx*/0,
      GIM_CheckMemorySizeEqualTo, /*MI*/0, /*MMO*/0, /*Size*/GIMT_Encode4(2),
      GIM_CheckMemoryAddressSpace, /*MI*/0, /*MMO*/0, /*NumAddrSpace*/1, /*AddrSpace*/3,
      GIM_CheckAtomicOrdering, /*MI*/0, /*Order*/(uint8_t)AtomicOrdering::NotAtomic,
      GIM_CheckPointerToAny, /*MI*/0, /*Op*/1, /*SizeInBits*/0,
      GIM_CheckComplexPattern, /*MI*/0, /*Op*/1, /*Renderer*/GIMT_Encode2(0), GIMT_Encode2(GICP_gi_ds_1addr_1offset),
      // (st i32:{ *:[i32] }:$value, (DS1Addr1Offset:{ *:[iPTR] } i32:{ *:[i32] }:$ptr, i32:{ *:[i32] }:$offset))<<P:Predicate_unindexedstore>><<P:Predicate_truncstore>><<P:Predicate_truncstorei16>><<P:Predicate_truncstorei16_local>>  =>  (DS_WRITE_B16_gfx9 ?:{ *:[i32] }:$ptr, anonymous_15037:{ *:[i32] }:$value, offset:{ *:[i32] }:$offset, 0:{ *:[i1] })
      GIR_BuildMI, /*InsnID*/0, /*Opcode*/GIMT_Encode2(AMDGPU::DS_WRITE_B16_gfx9),
      GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/0, // ptr
      GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/0, // value
      GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/1, // offset
      GIR_AddImm8, /*InsnID*/0, /*Imm*/0,
      GIR_MergeMemOperands, /*InsnID*/0, /*NumInsns*/1, /*MergeInsnID's*/0,
      GIR_ConstrainSelectedInstOperands, /*InsnID*/0,
      GIR_EraseFromParent, /*InsnID*/0,
      // GIR_Coverage, 6634,
      GIR_Done,
    // Label 2052: @134636
    GIM_Try, /*On fail goto*//*Label 2053*/ GIMT_Encode4(134697), // Rule ID 6639 //
      GIM_CheckFeatures, GIMT_Encode2(GIFBS_LDSRequiresM0Init),
      GIM_CheckMemorySizeEqualToLLT, /*MI*/0, /*MMO*/0, /*OpIdx*/0,
      GIM_CheckMemoryAddressSpace, /*MI*/0, /*MMO*/0, /*NumAddrSpace*/1, /*AddrSpace*/3,
      GIM_CheckAtomicOrdering, /*MI*/0, /*Order*/(uint8_t)AtomicOrdering::NotAtomic,
      GIM_CheckPointerToAny, /*MI*/0, /*Op*/1, /*SizeInBits*/0,
      GIM_CheckComplexPattern, /*MI*/0, /*Op*/1, /*Renderer*/GIMT_Encode2(0), GIMT_Encode2(GICP_gi_ds_1addr_1offset),
      // (AMDGPUst_glue i32:{ *:[i32] }:$value, (DS1Addr1Offset:{ *:[iPTR] } i32:{ *:[i32] }:$ptr, i32:{ *:[i32] }:$offset))<<P:Predicate_unindexedstore_glue>><<P:Predicate_store_glue>><<P:Predicate_store_local_m0>>  =>  (DS_WRITE_B32 ?:{ *:[i32] }:$ptr, anonymous_15037:{ *:[i32] }:$value, offset:{ *:[i32] }:$offset, 0:{ *:[i1] })
      GIR_BuildMI, /*InsnID*/0, /*Opcode*/GIMT_Encode2(AMDGPU::DS_WRITE_B32),
      GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/0, // ptr
      GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/0, // value
      GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/1, // offset
      GIR_AddImm8, /*InsnID*/0, /*Imm*/0,
      GIR_MergeMemOperands, /*InsnID*/0, /*NumInsns*/1, /*MergeInsnID's*/0,
      GIR_ConstrainSelectedInstOperands, /*InsnID*/0,
      GIR_EraseFromParent, /*InsnID*/0,
      // GIR_Coverage, 6639,
      GIR_Done,
    // Label 2053: @134697
    GIM_Try, /*On fail goto*//*Label 2054*/ GIMT_Encode4(134758), // Rule ID 6641 //
      GIM_CheckFeatures, GIMT_Encode2(GIFBS_LDSRequiresM0Init),
      GIM_CheckMemorySizeEqualToLLT, /*MI*/0, /*MMO*/0, /*OpIdx*/0,
      GIM_CheckMemoryAddressSpace, /*MI*/0, /*MMO*/0, /*NumAddrSpace*/1, /*AddrSpace*/3,
      GIM_CheckAtomicOrdering, /*MI*/0, /*Order*/(uint8_t)AtomicOrdering::NotAtomic,
      GIM_CheckPointerToAny, /*MI*/0, /*Op*/1, /*SizeInBits*/0,
      GIM_CheckComplexPattern, /*MI*/0, /*Op*/1, /*Renderer*/GIMT_Encode2(0), GIMT_Encode2(GICP_gi_ds_1addr_1offset),
      // (AMDGPUst_glue f32:{ *:[f32] }:$value, (DS1Addr1Offset:{ *:[iPTR] } i32:{ *:[i32] }:$ptr, i32:{ *:[i32] }:$offset))<<P:Predicate_unindexedstore_glue>><<P:Predicate_store_glue>><<P:Predicate_store_local_m0>>  =>  (DS_WRITE_B32 ?:{ *:[i32] }:$ptr, anonymous_15037:{ *:[f32] }:$value, offset:{ *:[i32] }:$offset, 0:{ *:[i1] })
      GIR_BuildMI, /*InsnID*/0, /*Opcode*/GIMT_Encode2(AMDGPU::DS_WRITE_B32),
      GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/0, // ptr
      GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/0, // value
      GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/1, // offset
      GIR_AddImm8, /*InsnID*/0, /*Imm*/0,
      GIR_MergeMemOperands, /*InsnID*/0, /*NumInsns*/1, /*MergeInsnID's*/0,
      GIR_ConstrainSelectedInstOperands, /*InsnID*/0,
      GIR_EraseFromParent, /*InsnID*/0,
      // GIR_Coverage, 6641,
      GIR_Done,
    // Label 2054: @134758
    GIM_Try, /*On fail goto*//*Label 2055*/ GIMT_Encode4(134815), // Rule ID 6640 //
      GIM_CheckFeatures, GIMT_Encode2(GIFBS_NotLDSRequiresM0Init),
      GIM_CheckMemoryAddressSpace, /*MI*/0, /*MMO*/0, /*NumAddrSpace*/1, /*AddrSpace*/3,
      GIM_CheckAtomicOrdering, /*MI*/0, /*Order*/(uint8_t)AtomicOrdering::NotAtomic,
      GIM_CheckPointerToAny, /*MI*/0, /*Op*/1, /*SizeInBits*/0,
      GIM_CheckComplexPattern, /*MI*/0, /*Op*/1, /*Renderer*/GIMT_Encode2(0), GIMT_Encode2(GICP_gi_ds_1addr_1offset),
      // (st i32:{ *:[i32] }:$value, (DS1Addr1Offset:{ *:[iPTR] } i32:{ *:[i32] }:$ptr, i32:{ *:[i32] }:$offset))<<P:Predicate_unindexedstore>><<P:Predicate_store_local>>  =>  (DS_WRITE_B32_gfx9 ?:{ *:[i32] }:$ptr, anonymous_15037:{ *:[i32] }:$value, offset:{ *:[i32] }:$offset, 0:{ *:[i1] })
      GIR_BuildMI, /*InsnID*/0, /*Opcode*/GIMT_Encode2(AMDGPU::DS_WRITE_B32_gfx9),
      GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/0, // ptr
      GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/0, // value
      GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/1, // offset
      GIR_AddImm8, /*InsnID*/0, /*Imm*/0,
      GIR_MergeMemOperands, /*InsnID*/0, /*NumInsns*/1, /*MergeInsnID's*/0,
      GIR_ConstrainSelectedInstOperands, /*InsnID*/0,
      GIR_EraseFromParent, /*InsnID*/0,
      // GIR_Coverage, 6640,
      GIR_Done,
    // Label 2055: @134815
    GIM_Try, /*On fail goto*//*Label 2056*/ GIMT_Encode4(134872), // Rule ID 6642 //
      GIM_CheckFeatures, GIMT_Encode2(GIFBS_NotLDSRequiresM0Init),
      GIM_CheckMemoryAddressSpace, /*MI*/0, /*MMO*/0, /*NumAddrSpace*/1, /*AddrSpace*/3,
      GIM_CheckAtomicOrdering, /*MI*/0, /*Order*/(uint8_t)AtomicOrdering::NotAtomic,
      GIM_CheckPointerToAny, /*MI*/0, /*Op*/1, /*SizeInBits*/0,
      GIM_CheckComplexPattern, /*MI*/0, /*Op*/1, /*Renderer*/GIMT_Encode2(0), GIMT_Encode2(GICP_gi_ds_1addr_1offset),
      // (st f32:{ *:[f32] }:$value, (DS1Addr1Offset:{ *:[iPTR] } i32:{ *:[i32] }:$ptr, i32:{ *:[i32] }:$offset))<<P:Predicate_unindexedstore>><<P:Predicate_store_local>>  =>  (DS_WRITE_B32_gfx9 ?:{ *:[i32] }:$ptr, anonymous_15037:{ *:[f32] }:$value, offset:{ *:[i32] }:$offset, 0:{ *:[i1] })
      GIR_BuildMI, /*InsnID*/0, /*Opcode*/GIMT_Encode2(AMDGPU::DS_WRITE_B32_gfx9),
      GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/0, // ptr
      GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/0, // value
      GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/1, // offset
      GIR_AddImm8, /*InsnID*/0, /*Imm*/0,
      GIR_MergeMemOperands, /*InsnID*/0, /*NumInsns*/1, /*MergeInsnID's*/0,
      GIR_ConstrainSelectedInstOperands, /*InsnID*/0,
      GIR_EraseFromParent, /*InsnID*/0,
      // GIR_Coverage, 6642,
      GIR_Done,
    // Label 2056: @134872
    GIM_Try, /*On fail goto*//*Label 2057*/ GIMT_Encode4(134941), // Rule ID 3139 //
      GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasFlatGlobalInsts),
      GIM_CheckMemorySizeEqualTo, /*MI*/0, /*MMO*/0, /*Size*/GIMT_Encode4(1),
      GIM_CheckMemoryAddressSpace, /*MI*/0, /*MMO*/0, /*NumAddrSpace*/1, /*AddrSpace*/1,
      GIM_CheckAtomicOrderingOrStrongerThan, /*MI*/0, /*Order*/(uint8_t)AtomicOrdering::Unordered,
      GIM_CheckPointerToAny, /*MI*/0, /*Op*/1, /*SizeInBits*/0,
      GIM_CheckComplexPattern, /*MI*/0, /*Op*/1, /*Renderer*/GIMT_Encode2(0), GIMT_Encode2(GICP_gi_global_saddr),
      // (atomic_store i32:{ *:[i32] }:$data, (GlobalSAddr:{ *:[iPTR] } SReg_64:{ *:[i64] }:$saddr, VGPR_32:{ *:[i32] }:$voffset, i32:{ *:[i32] }:$offset))<<P:Predicate_atomic_store_8>><<P:Predicate_atomic_store_8_global>>  =>  (GLOBAL_STORE_BYTE_SADDR ?:{ *:[i32] }:$voffset, anonymous_15037:{ *:[i32] }:$data, ?:{ *:[i64] }:$saddr, ?:{ *:[i32] }:$offset)
      GIR_BuildMI, /*InsnID*/0, /*Opcode*/GIMT_Encode2(AMDGPU::GLOBAL_STORE_BYTE_SADDR),
      GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/1, // voffset
      GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/0, // data
      GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/0, // saddr
      GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/2, // offset
      GIR_AddImm8, /*InsnID*/0, /*Imm*/0,
      GIR_MergeMemOperands, /*InsnID*/0, /*NumInsns*/1, /*MergeInsnID's*/0,
      GIR_ConstrainSelectedInstOperands, /*InsnID*/0,
      GIR_EraseFromParent, /*InsnID*/0,
      // GIR_Coverage, 3139,
      GIR_Done,
    // Label 2057: @134941
    GIM_Try, /*On fail goto*//*Label 2058*/ GIMT_Encode4(135010), // Rule ID 3143 //
      GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasFlatGlobalInsts),
      GIM_CheckMemorySizeEqualTo, /*MI*/0, /*MMO*/0, /*Size*/GIMT_Encode4(2),
      GIM_CheckMemoryAddressSpace, /*MI*/0, /*MMO*/0, /*NumAddrSpace*/1, /*AddrSpace*/1,
      GIM_CheckAtomicOrderingOrStrongerThan, /*MI*/0, /*Order*/(uint8_t)AtomicOrdering::Unordered,
      GIM_CheckPointerToAny, /*MI*/0, /*Op*/1, /*SizeInBits*/0,
      GIM_CheckComplexPattern, /*MI*/0, /*Op*/1, /*Renderer*/GIMT_Encode2(0), GIMT_Encode2(GICP_gi_global_saddr),
      // (atomic_store i32:{ *:[i32] }:$data, (GlobalSAddr:{ *:[iPTR] } SReg_64:{ *:[i64] }:$saddr, VGPR_32:{ *:[i32] }:$voffset, i32:{ *:[i32] }:$offset))<<P:Predicate_atomic_store_16>><<P:Predicate_atomic_store_16_global>>  =>  (GLOBAL_STORE_SHORT_SADDR ?:{ *:[i32] }:$voffset, anonymous_15037:{ *:[i32] }:$data, ?:{ *:[i64] }:$saddr, ?:{ *:[i32] }:$offset)
      GIR_BuildMI, /*InsnID*/0, /*Opcode*/GIMT_Encode2(AMDGPU::GLOBAL_STORE_SHORT_SADDR),
      GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/1, // voffset
      GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/0, // data
      GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/0, // saddr
      GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/2, // offset
      GIR_AddImm8, /*InsnID*/0, /*Imm*/0,
      GIR_MergeMemOperands, /*InsnID*/0, /*NumInsns*/1, /*MergeInsnID's*/0,
      GIR_ConstrainSelectedInstOperands, /*InsnID*/0,
      GIR_EraseFromParent, /*InsnID*/0,
      // GIR_Coverage, 3143,
      GIR_Done,
    // Label 2058: @135010
    GIM_Try, /*On fail goto*//*Label 2059*/ GIMT_Encode4(135079), // Rule ID 3147 //
      GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasFlatGlobalInsts),
      GIM_CheckMemorySizeEqualTo, /*MI*/0, /*MMO*/0, /*Size*/GIMT_Encode4(4),
      GIM_CheckMemoryAddressSpace, /*MI*/0, /*MMO*/0, /*NumAddrSpace*/1, /*AddrSpace*/1,
      GIM_CheckAtomicOrderingOrStrongerThan, /*MI*/0, /*Order*/(uint8_t)AtomicOrdering::Unordered,
      GIM_CheckPointerToAny, /*MI*/0, /*Op*/1, /*SizeInBits*/0,
      GIM_CheckComplexPattern, /*MI*/0, /*Op*/1, /*Renderer*/GIMT_Encode2(0), GIMT_Encode2(GICP_gi_global_saddr),
      // (atomic_store i32:{ *:[i32] }:$data, (GlobalSAddr:{ *:[iPTR] } SReg_64:{ *:[i64] }:$saddr, VGPR_32:{ *:[i32] }:$voffset, i32:{ *:[i32] }:$offset))<<P:Predicate_atomic_store_32>><<P:Predicate_atomic_store_32_global>>  =>  (GLOBAL_STORE_DWORD_SADDR ?:{ *:[i32] }:$voffset, anonymous_15037:{ *:[i32] }:$data, ?:{ *:[i64] }:$saddr, ?:{ *:[i32] }:$offset)
      GIR_BuildMI, /*InsnID*/0, /*Opcode*/GIMT_Encode2(AMDGPU::GLOBAL_STORE_DWORD_SADDR),
      GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/1, // voffset
      GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/0, // data
      GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/0, // saddr
      GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/2, // offset
      GIR_AddImm8, /*InsnID*/0, /*Imm*/0,
      GIR_MergeMemOperands, /*InsnID*/0, /*NumInsns*/1, /*MergeInsnID's*/0,
      GIR_ConstrainSelectedInstOperands, /*InsnID*/0,
      GIR_EraseFromParent, /*InsnID*/0,
      // GIR_Coverage, 3147,
      GIR_Done,
    // Label 2059: @135079
    GIM_Try, /*On fail goto*//*Label 2060*/ GIMT_Encode4(135152), // Rule ID 3103 //
      GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasFlatGlobalInsts),
      GIM_CheckMemorySizeLessThanLLT, /*MI*/0, /*MMO*/0, /*OpIdx*/0,
      GIM_CheckMemorySizeEqualTo, /*MI*/0, /*MMO*/0, /*Size*/GIMT_Encode4(1),
      GIM_CheckMemoryAddressSpace, /*MI*/0, /*MMO*/0, /*NumAddrSpace*/1, /*AddrSpace*/1,
      GIM_CheckAtomicOrdering, /*MI*/0, /*Order*/(uint8_t)AtomicOrdering::NotAtomic,
      GIM_CheckPointerToAny, /*MI*/0, /*Op*/1, /*SizeInBits*/0,
      GIM_CheckComplexPattern, /*MI*/0, /*Op*/1, /*Renderer*/GIMT_Encode2(0), GIMT_Encode2(GICP_gi_global_saddr),
      // (st i32:{ *:[i32] }:$data, (GlobalSAddr:{ *:[iPTR] } SReg_64:{ *:[i64] }:$saddr, VGPR_32:{ *:[i32] }:$voffset, i32:{ *:[i32] }:$offset))<<P:Predicate_unindexedstore>><<P:Predicate_truncstore>><<P:Predicate_truncstorei8>><<P:Predicate_truncstorei8_global>>  =>  (GLOBAL_STORE_BYTE_SADDR ?:{ *:[i32] }:$voffset, anonymous_15037:{ *:[i32] }:$data, ?:{ *:[i64] }:$saddr, ?:{ *:[i32] }:$offset)
      GIR_BuildMI, /*InsnID*/0, /*Opcode*/GIMT_Encode2(AMDGPU::GLOBAL_STORE_BYTE_SADDR),
      GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/1, // voffset
      GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/0, // data
      GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/0, // saddr
      GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/2, // offset
      GIR_AddImm8, /*InsnID*/0, /*Imm*/0,
      GIR_MergeMemOperands, /*InsnID*/0, /*NumInsns*/1, /*MergeInsnID's*/0,
      GIR_ConstrainSelectedInstOperands, /*InsnID*/0,
      GIR_EraseFromParent, /*InsnID*/0,
      // GIR_Coverage, 3103,
      GIR_Done,
    // Label 2060: @135152
    GIM_Try, /*On fail goto*//*Label 2061*/ GIMT_Encode4(135225), // Rule ID 3107 //
      GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasFlatGlobalInsts),
      GIM_CheckMemorySizeLessThanLLT, /*MI*/0, /*MMO*/0, /*OpIdx*/0,
      GIM_CheckMemorySizeEqualTo, /*MI*/0, /*MMO*/0, /*Size*/GIMT_Encode4(2),
      GIM_CheckMemoryAddressSpace, /*MI*/0, /*MMO*/0, /*NumAddrSpace*/1, /*AddrSpace*/1,
      GIM_CheckAtomicOrdering, /*MI*/0, /*Order*/(uint8_t)AtomicOrdering::NotAtomic,
      GIM_CheckPointerToAny, /*MI*/0, /*Op*/1, /*SizeInBits*/0,
      GIM_CheckComplexPattern, /*MI*/0, /*Op*/1, /*Renderer*/GIMT_Encode2(0), GIMT_Encode2(GICP_gi_global_saddr),
      // (st i32:{ *:[i32] }:$data, (GlobalSAddr:{ *:[iPTR] } SReg_64:{ *:[i64] }:$saddr, VGPR_32:{ *:[i32] }:$voffset, i32:{ *:[i32] }:$offset))<<P:Predicate_unindexedstore>><<P:Predicate_truncstore>><<P:Predicate_truncstorei16>><<P:Predicate_truncstorei16_global>>  =>  (GLOBAL_STORE_SHORT_SADDR ?:{ *:[i32] }:$voffset, anonymous_15037:{ *:[i32] }:$data, ?:{ *:[i64] }:$saddr, ?:{ *:[i32] }:$offset)
      GIR_BuildMI, /*InsnID*/0, /*Opcode*/GIMT_Encode2(AMDGPU::GLOBAL_STORE_SHORT_SADDR),
      GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/1, // voffset
      GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/0, // data
      GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/0, // saddr
      GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/2, // offset
      GIR_AddImm8, /*InsnID*/0, /*Imm*/0,
      GIR_MergeMemOperands, /*InsnID*/0, /*NumInsns*/1, /*MergeInsnID's*/0,
      GIR_ConstrainSelectedInstOperands, /*InsnID*/0,
      GIR_EraseFromParent, /*InsnID*/0,
      // GIR_Coverage, 3107,
      GIR_Done,
    // Label 2061: @135225
    GIM_Try, /*On fail goto*//*Label 2062*/ GIMT_Encode4(135287), // Rule ID 2954 //
      GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasFlatGlobalInsts),
      GIM_CheckMemoryAddressSpace, /*MI*/0, /*MMO*/0, /*NumAddrSpace*/1, /*AddrSpace*/1,
      GIM_CheckAtomicOrdering, /*MI*/0, /*Order*/(uint8_t)AtomicOrdering::NotAtomic,
      GIM_CheckPointerToAny, /*MI*/0, /*Op*/1, /*SizeInBits*/0,
      GIM_CheckComplexPattern, /*MI*/0, /*Op*/1, /*Renderer*/GIMT_Encode2(0), GIMT_Encode2(GICP_gi_global_saddr),
      // (st i32:{ *:[i32] }:$data, (GlobalSAddr:{ *:[iPTR] } SReg_64:{ *:[i64] }:$saddr, VGPR_32:{ *:[i32] }:$voffset, i32:{ *:[i32] }:$offset))<<P:Predicate_unindexedstore>><<P:Predicate_store_global>>  =>  (GLOBAL_STORE_DWORD_SADDR ?:{ *:[i32] }:$voffset, anonymous_15037:{ *:[i32] }:$data, ?:{ *:[i64] }:$saddr, ?:{ *:[i32] }:$offset)
      GIR_BuildMI, /*InsnID*/0, /*Opcode*/GIMT_Encode2(AMDGPU::GLOBAL_STORE_DWORD_SADDR),
      GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/1, // voffset
      GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/0, // data
      GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/0, // saddr
      GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/2, // offset
      GIR_AddImm8, /*InsnID*/0, /*Imm*/0,
      GIR_MergeMemOperands, /*InsnID*/0, /*NumInsns*/1, /*MergeInsnID's*/0,
      GIR_ConstrainSelectedInstOperands, /*InsnID*/0,
      GIR_EraseFromParent, /*InsnID*/0,
      // GIR_Coverage, 2954,
      GIR_Done,
    // Label 2062: @135287
    GIM_Try, /*On fail goto*//*Label 2063*/ GIMT_Encode4(135349), // Rule ID 2999 //
      GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasFlatGlobalInsts),
      GIM_CheckMemoryAddressSpace, /*MI*/0, /*MMO*/0, /*NumAddrSpace*/1, /*AddrSpace*/1,
      GIM_CheckAtomicOrdering, /*MI*/0, /*Order*/(uint8_t)AtomicOrdering::NotAtomic,
      GIM_CheckPointerToAny, /*MI*/0, /*Op*/1, /*SizeInBits*/0,
      GIM_CheckComplexPattern, /*MI*/0, /*Op*/1, /*Renderer*/GIMT_Encode2(0), GIMT_Encode2(GICP_gi_global_saddr),
      // (st f32:{ *:[f32] }:$data, (GlobalSAddr:{ *:[iPTR] } SReg_64:{ *:[i64] }:$saddr, VGPR_32:{ *:[i32] }:$voffset, i32:{ *:[i32] }:$offset))<<P:Predicate_unindexedstore>><<P:Predicate_store_global>>  =>  (GLOBAL_STORE_DWORD_SADDR ?:{ *:[i32] }:$voffset, anonymous_15037:{ *:[f32] }:$data, ?:{ *:[i64] }:$saddr, ?:{ *:[i32] }:$offset)
      GIR_BuildMI, /*InsnID*/0, /*Opcode*/GIMT_Encode2(AMDGPU::GLOBAL_STORE_DWORD_SADDR),
      GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/1, // voffset
      GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/0, // data
      GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/0, // saddr
      GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/2, // offset
      GIR_AddImm8, /*InsnID*/0, /*Imm*/0,
      GIR_MergeMemOperands, /*InsnID*/0, /*NumInsns*/1, /*MergeInsnID's*/0,
      GIR_ConstrainSelectedInstOperands, /*InsnID*/0,
      GIR_EraseFromParent, /*InsnID*/0,
      // GIR_Coverage, 2999,
      GIR_Done,
    // Label 2063: @135349
    GIM_Try, /*On fail goto*//*Label 2064*/ GIMT_Encode4(135413), // Rule ID 3138 //
      GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasFlatGlobalInsts),
      GIM_CheckMemorySizeEqualTo, /*MI*/0, /*MMO*/0, /*Size*/GIMT_Encode4(1),
      GIM_CheckMemoryAddressSpace, /*MI*/0, /*MMO*/0, /*NumAddrSpace*/1, /*AddrSpace*/1,
      GIM_CheckAtomicOrderingOrStrongerThan, /*MI*/0, /*Order*/(uint8_t)AtomicOrdering::Unordered,
      GIM_CheckPointerToAny, /*MI*/0, /*Op*/1, /*SizeInBits*/0,
      GIM_CheckComplexPattern, /*MI*/0, /*Op*/1, /*Renderer*/GIMT_Encode2(0), GIMT_Encode2(GICP_gi_global_offset),
      // (atomic_store i32:{ *:[i32] }:$data, (GlobalOffset:{ *:[iPTR] } i64:{ *:[i64] }:$vaddr, i32:{ *:[i32] }:$offset))<<P:Predicate_atomic_store_8>><<P:Predicate_atomic_store_8_global>>  =>  (GLOBAL_STORE_BYTE ?:{ *:[i64] }:$vaddr, anonymous_15037:{ *:[i32] }:$data, ?:{ *:[i32] }:$offset)
      GIR_BuildMI, /*InsnID*/0, /*Opcode*/GIMT_Encode2(AMDGPU::GLOBAL_STORE_BYTE),
      GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/0, // vaddr
      GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/0, // data
      GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/1, // offset
      GIR_AddImm8, /*InsnID*/0, /*Imm*/0,
      GIR_MergeMemOperands, /*InsnID*/0, /*NumInsns*/1, /*MergeInsnID's*/0,
      GIR_ConstrainSelectedInstOperands, /*InsnID*/0,
      GIR_EraseFromParent, /*InsnID*/0,
      // GIR_Coverage, 3138,
      GIR_Done,
    // Label 2064: @135413
    GIM_Try, /*On fail goto*//*Label 2065*/ GIMT_Encode4(135477), // Rule ID 3142 //
      GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasFlatGlobalInsts),
      GIM_CheckMemorySizeEqualTo, /*MI*/0, /*MMO*/0, /*Size*/GIMT_Encode4(2),
      GIM_CheckMemoryAddressSpace, /*MI*/0, /*MMO*/0, /*NumAddrSpace*/1, /*AddrSpace*/1,
      GIM_CheckAtomicOrderingOrStrongerThan, /*MI*/0, /*Order*/(uint8_t)AtomicOrdering::Unordered,
      GIM_CheckPointerToAny, /*MI*/0, /*Op*/1, /*SizeInBits*/0,
      GIM_CheckComplexPattern, /*MI*/0, /*Op*/1, /*Renderer*/GIMT_Encode2(0), GIMT_Encode2(GICP_gi_global_offset),
      // (atomic_store i32:{ *:[i32] }:$data, (GlobalOffset:{ *:[iPTR] } i64:{ *:[i64] }:$vaddr, i32:{ *:[i32] }:$offset))<<P:Predicate_atomic_store_16>><<P:Predicate_atomic_store_16_global>>  =>  (GLOBAL_STORE_SHORT ?:{ *:[i64] }:$vaddr, anonymous_15037:{ *:[i32] }:$data, ?:{ *:[i32] }:$offset)
      GIR_BuildMI, /*InsnID*/0, /*Opcode*/GIMT_Encode2(AMDGPU::GLOBAL_STORE_SHORT),
      GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/0, // vaddr
      GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/0, // data
      GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/1, // offset
      GIR_AddImm8, /*InsnID*/0, /*Imm*/0,
      GIR_MergeMemOperands, /*InsnID*/0, /*NumInsns*/1, /*MergeInsnID's*/0,
      GIR_ConstrainSelectedInstOperands, /*InsnID*/0,
      GIR_EraseFromParent, /*InsnID*/0,
      // GIR_Coverage, 3142,
      GIR_Done,
    // Label 2065: @135477
    GIM_Try, /*On fail goto*//*Label 2066*/ GIMT_Encode4(135541), // Rule ID 3146 //
      GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasFlatGlobalInsts),
      GIM_CheckMemorySizeEqualTo, /*MI*/0, /*MMO*/0, /*Size*/GIMT_Encode4(4),
      GIM_CheckMemoryAddressSpace, /*MI*/0, /*MMO*/0, /*NumAddrSpace*/1, /*AddrSpace*/1,
      GIM_CheckAtomicOrderingOrStrongerThan, /*MI*/0, /*Order*/(uint8_t)AtomicOrdering::Unordered,
      GIM_CheckPointerToAny, /*MI*/0, /*Op*/1, /*SizeInBits*/0,
      GIM_CheckComplexPattern, /*MI*/0, /*Op*/1, /*Renderer*/GIMT_Encode2(0), GIMT_Encode2(GICP_gi_global_offset),
      // (atomic_store i32:{ *:[i32] }:$data, (GlobalOffset:{ *:[iPTR] } i64:{ *:[i64] }:$vaddr, i32:{ *:[i32] }:$offset))<<P:Predicate_atomic_store_32>><<P:Predicate_atomic_store_32_global>>  =>  (GLOBAL_STORE_DWORD ?:{ *:[i64] }:$vaddr, anonymous_15037:{ *:[i32] }:$data, ?:{ *:[i32] }:$offset)
      GIR_BuildMI, /*InsnID*/0, /*Opcode*/GIMT_Encode2(AMDGPU::GLOBAL_STORE_DWORD),
      GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/0, // vaddr
      GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/0, // data
      GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/1, // offset
      GIR_AddImm8, /*InsnID*/0, /*Imm*/0,
      GIR_MergeMemOperands, /*InsnID*/0, /*NumInsns*/1, /*MergeInsnID's*/0,
      GIR_ConstrainSelectedInstOperands, /*InsnID*/0,
      GIR_EraseFromParent, /*InsnID*/0,
      // GIR_Coverage, 3146,
      GIR_Done,
    // Label 2066: @135541
    GIM_Try, /*On fail goto*//*Label 2067*/ GIMT_Encode4(135609), // Rule ID 3102 //
      GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasFlatGlobalInsts),
      GIM_CheckMemorySizeLessThanLLT, /*MI*/0, /*MMO*/0, /*OpIdx*/0,
      GIM_CheckMemorySizeEqualTo, /*MI*/0, /*MMO*/0, /*Size*/GIMT_Encode4(1),
      GIM_CheckMemoryAddressSpace, /*MI*/0, /*MMO*/0, /*NumAddrSpace*/1, /*AddrSpace*/1,
      GIM_CheckAtomicOrdering, /*MI*/0, /*Order*/(uint8_t)AtomicOrdering::NotAtomic,
      GIM_CheckPointerToAny, /*MI*/0, /*Op*/1, /*SizeInBits*/0,
      GIM_CheckComplexPattern, /*MI*/0, /*Op*/1, /*Renderer*/GIMT_Encode2(0), GIMT_Encode2(GICP_gi_global_offset),
      // (st i32:{ *:[i32] }:$data, (GlobalOffset:{ *:[iPTR] } i64:{ *:[i64] }:$vaddr, i32:{ *:[i32] }:$offset))<<P:Predicate_unindexedstore>><<P:Predicate_truncstore>><<P:Predicate_truncstorei8>><<P:Predicate_truncstorei8_global>>  =>  (GLOBAL_STORE_BYTE ?:{ *:[i64] }:$vaddr, anonymous_15037:{ *:[i32] }:$data, ?:{ *:[i32] }:$offset)
      GIR_BuildMI, /*InsnID*/0, /*Opcode*/GIMT_Encode2(AMDGPU::GLOBAL_STORE_BYTE),
      GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/0, // vaddr
      GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/0, // data
      GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/1, // offset
      GIR_AddImm8, /*InsnID*/0, /*Imm*/0,
      GIR_MergeMemOperands, /*InsnID*/0, /*NumInsns*/1, /*MergeInsnID's*/0,
      GIR_ConstrainSelectedInstOperands, /*InsnID*/0,
      GIR_EraseFromParent, /*InsnID*/0,
      // GIR_Coverage, 3102,
      GIR_Done,
    // Label 2067: @135609
    GIM_Try, /*On fail goto*//*Label 2068*/ GIMT_Encode4(135677), // Rule ID 3106 //
      GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasFlatGlobalInsts),
      GIM_CheckMemorySizeLessThanLLT, /*MI*/0, /*MMO*/0, /*OpIdx*/0,
      GIM_CheckMemorySizeEqualTo, /*MI*/0, /*MMO*/0, /*Size*/GIMT_Encode4(2),
      GIM_CheckMemoryAddressSpace, /*MI*/0, /*MMO*/0, /*NumAddrSpace*/1, /*AddrSpace*/1,
      GIM_CheckAtomicOrdering, /*MI*/0, /*Order*/(uint8_t)AtomicOrdering::NotAtomic,
      GIM_CheckPointerToAny, /*MI*/0, /*Op*/1, /*SizeInBits*/0,
      GIM_CheckComplexPattern, /*MI*/0, /*Op*/1, /*Renderer*/GIMT_Encode2(0), GIMT_Encode2(GICP_gi_global_offset),
      // (st i32:{ *:[i32] }:$data, (GlobalOffset:{ *:[iPTR] } i64:{ *:[i64] }:$vaddr, i32:{ *:[i32] }:$offset))<<P:Predicate_unindexedstore>><<P:Predicate_truncstore>><<P:Predicate_truncstorei16>><<P:Predicate_truncstorei16_global>>  =>  (GLOBAL_STORE_SHORT ?:{ *:[i64] }:$vaddr, anonymous_15037:{ *:[i32] }:$data, ?:{ *:[i32] }:$offset)
      GIR_BuildMI, /*InsnID*/0, /*Opcode*/GIMT_Encode2(AMDGPU::GLOBAL_STORE_SHORT),
      GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/0, // vaddr
      GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/0, // data
      GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/1, // offset
      GIR_AddImm8, /*InsnID*/0, /*Imm*/0,
      GIR_MergeMemOperands, /*InsnID*/0, /*NumInsns*/1, /*MergeInsnID's*/0,
      GIR_ConstrainSelectedInstOperands, /*InsnID*/0,
      GIR_EraseFromParent, /*InsnID*/0,
      // GIR_Coverage, 3106,
      GIR_Done,
    // Label 2068: @135677
    GIM_Try, /*On fail goto*//*Label 2069*/ GIMT_Encode4(135734), // Rule ID 2953 //
      GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasFlatGlobalInsts),
      GIM_CheckMemoryAddressSpace, /*MI*/0, /*MMO*/0, /*NumAddrSpace*/1, /*AddrSpace*/1,
      GIM_CheckAtomicOrdering, /*MI*/0, /*Order*/(uint8_t)AtomicOrdering::NotAtomic,
      GIM_CheckPointerToAny, /*MI*/0, /*Op*/1, /*SizeInBits*/0,
      GIM_CheckComplexPattern, /*MI*/0, /*Op*/1, /*Renderer*/GIMT_Encode2(0), GIMT_Encode2(GICP_gi_global_offset),
      // (st i32:{ *:[i32] }:$data, (GlobalOffset:{ *:[iPTR] } i64:{ *:[i64] }:$vaddr, i32:{ *:[i32] }:$offset))<<P:Predicate_unindexedstore>><<P:Predicate_store_global>>  =>  (GLOBAL_STORE_DWORD ?:{ *:[i64] }:$vaddr, anonymous_15037:{ *:[i32] }:$data, ?:{ *:[i32] }:$offset)
      GIR_BuildMI, /*InsnID*/0, /*Opcode*/GIMT_Encode2(AMDGPU::GLOBAL_STORE_DWORD),
      GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/0, // vaddr
      GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/0, // data
      GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/1, // offset
      GIR_AddImm8, /*InsnID*/0, /*Imm*/0,
      GIR_MergeMemOperands, /*InsnID*/0, /*NumInsns*/1, /*MergeInsnID's*/0,
      GIR_ConstrainSelectedInstOperands, /*InsnID*/0,
      GIR_EraseFromParent, /*InsnID*/0,
      // GIR_Coverage, 2953,
      GIR_Done,
    // Label 2069: @135734
    GIM_Try, /*On fail goto*//*Label 2070*/ GIMT_Encode4(135791), // Rule ID 2998 //
      GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasFlatGlobalInsts),
      GIM_CheckMemoryAddressSpace, /*MI*/0, /*MMO*/0, /*NumAddrSpace*/1, /*AddrSpace*/1,
      GIM_CheckAtomicOrdering, /*MI*/0, /*Order*/(uint8_t)AtomicOrdering::NotAtomic,
      GIM_CheckPointerToAny, /*MI*/0, /*Op*/1, /*SizeInBits*/0,
      GIM_CheckComplexPattern, /*MI*/0, /*Op*/1, /*Renderer*/GIMT_Encode2(0), GIMT_Encode2(GICP_gi_global_offset),
      // (st f32:{ *:[f32] }:$data, (GlobalOffset:{ *:[iPTR] } i64:{ *:[i64] }:$vaddr, i32:{ *:[i32] }:$offset))<<P:Predicate_unindexedstore>><<P:Predicate_store_global>>  =>  (GLOBAL_STORE_DWORD ?:{ *:[i64] }:$vaddr, anonymous_15037:{ *:[f32] }:$data, ?:{ *:[i32] }:$offset)
      GIR_BuildMI, /*InsnID*/0, /*Opcode*/GIMT_Encode2(AMDGPU::GLOBAL_STORE_DWORD),
      GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/0, // vaddr
      GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/0, // data
      GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/1, // offset
      GIR_AddImm8, /*InsnID*/0, /*Imm*/0,
      GIR_MergeMemOperands, /*InsnID*/0, /*NumInsns*/1, /*MergeInsnID's*/0,
      GIR_ConstrainSelectedInstOperands, /*InsnID*/0,
      GIR_EraseFromParent, /*InsnID*/0,
      // GIR_Coverage, 2998,
      GIR_Done,
    // Label 2070: @135791
    GIM_Try, /*On fail goto*//*Label 2071*/ GIMT_Encode4(135883), // Rule ID 2935 //
      GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasD16LoadStore),
      GIM_CheckMemorySizeLessThanLLT, /*MI*/0, /*MMO*/0, /*OpIdx*/0,
      GIM_CheckMemorySizeEqualTo, /*MI*/0, /*MMO*/0, /*Size*/GIMT_Encode4(2),
      GIM_CheckMemoryAddressSpace, /*MI*/0, /*MMO*/0, /*NumAddrSpace*/2, /*AddrSpace*/0, /*AddrSpace*/1,
      GIM_CheckAtomicOrdering, /*MI*/0, /*Order*/(uint8_t)AtomicOrdering::NotAtomic,
      GIM_RecordInsn, /*DefineMI*/1, /*MI*/0, /*OpIdx*/0, // MIs[1]
      GIM_CheckOpcode, /*MI*/1, GIMT_Encode2(TargetOpcode::G_LSHR),
      GIM_CheckType, /*MI*/1, /*Op*/1, /*Type*/GILLT_s32,
      GIM_CheckType, /*MI*/1, /*Op*/2, /*Type*/GILLT_s32,
      GIM_CheckConstantInt8, /*MI*/1, /*Op*/2, 16,
      GIM_CheckPointerToAny, /*MI*/0, /*Op*/1, /*SizeInBits*/0,
      GIM_CheckIsSafeToFold, /*InsnID*/1,
      GIM_CheckComplexPattern, /*MI*/0, /*Op*/1, /*Renderer*/GIMT_Encode2(0), GIMT_Encode2(GICP_gi_flat_offset),
      // (st (srl:{ *:[i32] } i32:{ *:[i32] }:$data, 16:{ *:[i32] }), (FlatOffset:{ *:[iPTR] } i64:{ *:[i64] }:$vaddr, i32:{ *:[i32] }:$offset))<<P:Predicate_unindexedstore>><<P:Predicate_truncstore>><<P:Predicate_truncstorei16>><<P:Predicate_truncstorei16_hi16_flat>>  =>  (FLAT_STORE_SHORT_D16_HI ?:{ *:[i64] }:$vaddr, anonymous_15037:{ *:[i32] }:$data, ?:{ *:[i32] }:$offset)
      GIR_BuildMI, /*InsnID*/0, /*Opcode*/GIMT_Encode2(AMDGPU::FLAT_STORE_SHORT_D16_HI),
      GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/0, // vaddr
      GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/1, /*OpIdx*/1, // data
      GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/1, // offset
      GIR_AddImm8, /*InsnID*/0, /*Imm*/0,
      GIR_MergeMemOperands, /*InsnID*/0, /*NumInsns*/2, /*MergeInsnID's*/0, 1,
      GIR_ConstrainSelectedInstOperands, /*InsnID*/0,
      GIR_EraseFromParent, /*InsnID*/0,
      // GIR_Coverage, 2935,
      GIR_Done,
    // Label 2071: @135883
    GIM_Try, /*On fail goto*//*Label 2072*/ GIMT_Encode4(135975), // Rule ID 2936 //
      GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasD16LoadStore),
      GIM_CheckMemorySizeLessThanLLT, /*MI*/0, /*MMO*/0, /*OpIdx*/0,
      GIM_CheckMemorySizeEqualTo, /*MI*/0, /*MMO*/0, /*Size*/GIMT_Encode4(1),
      GIM_CheckMemoryAddressSpace, /*MI*/0, /*MMO*/0, /*NumAddrSpace*/2, /*AddrSpace*/0, /*AddrSpace*/1,
      GIM_CheckAtomicOrdering, /*MI*/0, /*Order*/(uint8_t)AtomicOrdering::NotAtomic,
      GIM_RecordInsn, /*DefineMI*/1, /*MI*/0, /*OpIdx*/0, // MIs[1]
      GIM_CheckOpcode, /*MI*/1, GIMT_Encode2(TargetOpcode::G_LSHR),
      GIM_CheckType, /*MI*/1, /*Op*/1, /*Type*/GILLT_s32,
      GIM_CheckType, /*MI*/1, /*Op*/2, /*Type*/GILLT_s32,
      GIM_CheckConstantInt8, /*MI*/1, /*Op*/2, 16,
      GIM_CheckPointerToAny, /*MI*/0, /*Op*/1, /*SizeInBits*/0,
      GIM_CheckIsSafeToFold, /*InsnID*/1,
      GIM_CheckComplexPattern, /*MI*/0, /*Op*/1, /*Renderer*/GIMT_Encode2(0), GIMT_Encode2(GICP_gi_flat_offset),
      // (st (srl:{ *:[i32] } i32:{ *:[i32] }:$data, 16:{ *:[i32] }), (FlatOffset:{ *:[iPTR] } i64:{ *:[i64] }:$vaddr, i32:{ *:[i32] }:$offset))<<P:Predicate_unindexedstore>><<P:Predicate_truncstore>><<P:Predicate_truncstorei8>><<P:Predicate_truncstorei8_hi16_flat>>  =>  (FLAT_STORE_BYTE_D16_HI ?:{ *:[i64] }:$vaddr, anonymous_15037:{ *:[i32] }:$data, ?:{ *:[i32] }:$offset)
      GIR_BuildMI, /*InsnID*/0, /*Opcode*/GIMT_Encode2(AMDGPU::FLAT_STORE_BYTE_D16_HI),
      GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/0, // vaddr
      GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/1, /*OpIdx*/1, // data
      GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/1, // offset
      GIR_AddImm8, /*InsnID*/0, /*Imm*/0,
      GIR_MergeMemOperands, /*InsnID*/0, /*NumInsns*/2, /*MergeInsnID's*/0, 1,
      GIR_ConstrainSelectedInstOperands, /*InsnID*/0,
      GIR_EraseFromParent, /*InsnID*/0,
      // GIR_Coverage, 2936,
      GIR_Done,
    // Label 2072: @135975
    GIM_Try, /*On fail goto*//*Label 2073*/ GIMT_Encode4(136040), // Rule ID 2823 //
      GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasFlatAddressSpace),
      GIM_CheckMemorySizeEqualTo, /*MI*/0, /*MMO*/0, /*Size*/GIMT_Encode4(4),
      GIM_CheckMemoryAddressSpace, /*MI*/0, /*MMO*/0, /*NumAddrSpace*/2, /*AddrSpace*/0, /*AddrSpace*/1,
      GIM_CheckAtomicOrderingOrStrongerThan, /*MI*/0, /*Order*/(uint8_t)AtomicOrdering::Unordered,
      GIM_CheckPointerToAny, /*MI*/0, /*Op*/1, /*SizeInBits*/0,
      GIM_CheckComplexPattern, /*MI*/0, /*Op*/1, /*Renderer*/GIMT_Encode2(0), GIMT_Encode2(GICP_gi_flat_offset),
      // (atomic_store i32:{ *:[i32] }:$data, (FlatOffset:{ *:[iPTR] } i64:{ *:[i64] }:$vaddr, i32:{ *:[i32] }:$offset))<<P:Predicate_atomic_store_32>><<P:Predicate_atomic_store_32_flat>>  =>  (FLAT_STORE_DWORD ?:{ *:[i64] }:$vaddr, anonymous_15037:{ *:[i32] }:$data, ?:{ *:[i32] }:$offset)
      GIR_BuildMI, /*InsnID*/0, /*Opcode*/GIMT_Encode2(AMDGPU::FLAT_STORE_DWORD),
      GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/0, // vaddr
      GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/0, // data
      GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/1, // offset
      GIR_AddImm8, /*InsnID*/0, /*Imm*/0,
      GIR_MergeMemOperands, /*InsnID*/0, /*NumInsns*/1, /*MergeInsnID's*/0,
      GIR_ConstrainSelectedInstOperands, /*InsnID*/0,
      GIR_EraseFromParent, /*InsnID*/0,
      // GIR_Coverage, 2823,
      GIR_Done,
    // Label 2073: @136040
    GIM_Try, /*On fail goto*//*Label 2074*/ GIMT_Encode4(136105), // Rule ID 2825 //
      GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasFlatAddressSpace),
      GIM_CheckMemorySizeEqualTo, /*MI*/0, /*MMO*/0, /*Size*/GIMT_Encode4(1),
      GIM_CheckMemoryAddressSpace, /*MI*/0, /*MMO*/0, /*NumAddrSpace*/2, /*AddrSpace*/0, /*AddrSpace*/1,
      GIM_CheckAtomicOrderingOrStrongerThan, /*MI*/0, /*Order*/(uint8_t)AtomicOrdering::Unordered,
      GIM_CheckPointerToAny, /*MI*/0, /*Op*/1, /*SizeInBits*/0,
      GIM_CheckComplexPattern, /*MI*/0, /*Op*/1, /*Renderer*/GIMT_Encode2(0), GIMT_Encode2(GICP_gi_flat_offset),
      // (atomic_store i32:{ *:[i32] }:$data, (FlatOffset:{ *:[iPTR] } i64:{ *:[i64] }:$vaddr, i32:{ *:[i32] }:$offset))<<P:Predicate_atomic_store_8>><<P:Predicate_atomic_store_8_flat>>  =>  (FLAT_STORE_BYTE ?:{ *:[i64] }:$vaddr, anonymous_15037:{ *:[i32] }:$data, ?:{ *:[i32] }:$offset)
      GIR_BuildMI, /*InsnID*/0, /*Opcode*/GIMT_Encode2(AMDGPU::FLAT_STORE_BYTE),
      GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/0, // vaddr
      GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/0, // data
      GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/1, // offset
      GIR_AddImm8, /*InsnID*/0, /*Imm*/0,
      GIR_MergeMemOperands, /*InsnID*/0, /*NumInsns*/1, /*MergeInsnID's*/0,
      GIR_ConstrainSelectedInstOperands, /*InsnID*/0,
      GIR_EraseFromParent, /*InsnID*/0,
      // GIR_Coverage, 2825,
      GIR_Done,
    // Label 2074: @136105
    GIM_Try, /*On fail goto*//*Label 2075*/ GIMT_Encode4(136170), // Rule ID 2827 //
      GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasFlatAddressSpace),
      GIM_CheckMemorySizeEqualTo, /*MI*/0, /*MMO*/0, /*Size*/GIMT_Encode4(2),
      GIM_CheckMemoryAddressSpace, /*MI*/0, /*MMO*/0, /*NumAddrSpace*/2, /*AddrSpace*/0, /*AddrSpace*/1,
      GIM_CheckAtomicOrderingOrStrongerThan, /*MI*/0, /*Order*/(uint8_t)AtomicOrdering::Unordered,
      GIM_CheckPointerToAny, /*MI*/0, /*Op*/1, /*SizeInBits*/0,
      GIM_CheckComplexPattern, /*MI*/0, /*Op*/1, /*Renderer*/GIMT_Encode2(0), GIMT_Encode2(GICP_gi_flat_offset),
      // (atomic_store i32:{ *:[i32] }:$data, (FlatOffset:{ *:[iPTR] } i64:{ *:[i64] }:$vaddr, i32:{ *:[i32] }:$offset))<<P:Predicate_atomic_store_16>><<P:Predicate_atomic_store_16_flat>>  =>  (FLAT_STORE_SHORT ?:{ *:[i64] }:$vaddr, anonymous_15037:{ *:[i32] }:$data, ?:{ *:[i32] }:$offset)
      GIR_BuildMI, /*InsnID*/0, /*Opcode*/GIMT_Encode2(AMDGPU::FLAT_STORE_SHORT),
      GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/0, // vaddr
      GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/0, // data
      GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/1, // offset
      GIR_AddImm8, /*InsnID*/0, /*Imm*/0,
      GIR_MergeMemOperands, /*InsnID*/0, /*NumInsns*/1, /*MergeInsnID's*/0,
      GIR_ConstrainSelectedInstOperands, /*InsnID*/0,
      GIR_EraseFromParent, /*InsnID*/0,
      // GIR_Coverage, 2827,
      GIR_Done,
    // Label 2075: @136170
    GIM_Try, /*On fail goto*//*Label 2076*/ GIMT_Encode4(136239), // Rule ID 2768 //
      GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasFlatAddressSpace),
      GIM_CheckMemorySizeLessThanLLT, /*MI*/0, /*MMO*/0, /*OpIdx*/0,
      GIM_CheckMemorySizeEqualTo, /*MI*/0, /*MMO*/0, /*Size*/GIMT_Encode4(1),
      GIM_CheckMemoryAddressSpace, /*MI*/0, /*MMO*/0, /*NumAddrSpace*/2, /*AddrSpace*/0, /*AddrSpace*/1,
      GIM_CheckAtomicOrdering, /*MI*/0, /*Order*/(uint8_t)AtomicOrdering::NotAtomic,
      GIM_CheckPointerToAny, /*MI*/0, /*Op*/1, /*SizeInBits*/0,
      GIM_CheckComplexPattern, /*MI*/0, /*Op*/1, /*Renderer*/GIMT_Encode2(0), GIMT_Encode2(GICP_gi_flat_offset),
      // (st i32:{ *:[i32] }:$data, (FlatOffset:{ *:[iPTR] } i64:{ *:[i64] }:$vaddr, i32:{ *:[i32] }:$offset))<<P:Predicate_unindexedstore>><<P:Predicate_truncstore>><<P:Predicate_truncstorei8>><<P:Predicate_truncstorei8_flat>>  =>  (FLAT_STORE_BYTE ?:{ *:[i64] }:$vaddr, anonymous_15037:{ *:[i32] }:$data, ?:{ *:[i32] }:$offset)
      GIR_BuildMI, /*InsnID*/0, /*Opcode*/GIMT_Encode2(AMDGPU::FLAT_STORE_BYTE),
      GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/0, // vaddr
      GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/0, // data
      GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/1, // offset
      GIR_AddImm8, /*InsnID*/0, /*Imm*/0,
      GIR_MergeMemOperands, /*InsnID*/0, /*NumInsns*/1, /*MergeInsnID's*/0,
      GIR_ConstrainSelectedInstOperands, /*InsnID*/0,
      GIR_EraseFromParent, /*InsnID*/0,
      // GIR_Coverage, 2768,
      GIR_Done,
    // Label 2076: @136239
    GIM_Try, /*On fail goto*//*Label 2077*/ GIMT_Encode4(136308), // Rule ID 2769 //
      GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasFlatAddressSpace),
      GIM_CheckMemorySizeLessThanLLT, /*MI*/0, /*MMO*/0, /*OpIdx*/0,
      GIM_CheckMemorySizeEqualTo, /*MI*/0, /*MMO*/0, /*Size*/GIMT_Encode4(2),
      GIM_CheckMemoryAddressSpace, /*MI*/0, /*MMO*/0, /*NumAddrSpace*/2, /*AddrSpace*/0, /*AddrSpace*/1,
      GIM_CheckAtomicOrdering, /*MI*/0, /*Order*/(uint8_t)AtomicOrdering::NotAtomic,
      GIM_CheckPointerToAny, /*MI*/0, /*Op*/1, /*SizeInBits*/0,
      GIM_CheckComplexPattern, /*MI*/0, /*Op*/1, /*Renderer*/GIMT_Encode2(0), GIMT_Encode2(GICP_gi_flat_offset),
      // (st i32:{ *:[i32] }:$data, (FlatOffset:{ *:[iPTR] } i64:{ *:[i64] }:$vaddr, i32:{ *:[i32] }:$offset))<<P:Predicate_unindexedstore>><<P:Predicate_truncstore>><<P:Predicate_truncstorei16>><<P:Predicate_truncstorei16_flat>>  =>  (FLAT_STORE_SHORT ?:{ *:[i64] }:$vaddr, anonymous_15037:{ *:[i32] }:$data, ?:{ *:[i32] }:$offset)
      GIR_BuildMI, /*InsnID*/0, /*Opcode*/GIMT_Encode2(AMDGPU::FLAT_STORE_SHORT),
      GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/0, // vaddr
      GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/0, // data
      GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/1, // offset
      GIR_AddImm8, /*InsnID*/0, /*Imm*/0,
      GIR_MergeMemOperands, /*InsnID*/0, /*NumInsns*/1, /*MergeInsnID's*/0,
      GIR_ConstrainSelectedInstOperands, /*InsnID*/0,
      GIR_EraseFromParent, /*InsnID*/0,
      // GIR_Coverage, 2769,
      GIR_Done,
    // Label 2077: @136308
    GIM_Try, /*On fail goto*//*Label 2078*/ GIMT_Encode4(136366), // Rule ID 2771 //
      GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasFlatAddressSpace),
      GIM_CheckMemoryAddressSpace, /*MI*/0, /*MMO*/0, /*NumAddrSpace*/2, /*AddrSpace*/0, /*AddrSpace*/1,
      GIM_CheckAtomicOrdering, /*MI*/0, /*Order*/(uint8_t)AtomicOrdering::NotAtomic,
      GIM_CheckPointerToAny, /*MI*/0, /*Op*/1, /*SizeInBits*/0,
      GIM_CheckComplexPattern, /*MI*/0, /*Op*/1, /*Renderer*/GIMT_Encode2(0), GIMT_Encode2(GICP_gi_flat_offset),
      // (st i32:{ *:[i32] }:$data, (FlatOffset:{ *:[iPTR] } i64:{ *:[i64] }:$vaddr, i32:{ *:[i32] }:$offset))<<P:Predicate_unindexedstore>><<P:Predicate_store_flat>>  =>  (FLAT_STORE_DWORD ?:{ *:[i64] }:$vaddr, anonymous_15037:{ *:[i32] }:$data, ?:{ *:[i32] }:$offset)
      GIR_BuildMI, /*InsnID*/0, /*Opcode*/GIMT_Encode2(AMDGPU::FLAT_STORE_DWORD),
      GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/0, // vaddr
      GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/0, // data
      GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/1, // offset
      GIR_AddImm8, /*InsnID*/0, /*Imm*/0,
      GIR_MergeMemOperands, /*InsnID*/0, /*NumInsns*/1, /*MergeInsnID's*/0,
      GIR_ConstrainSelectedInstOperands, /*InsnID*/0,
      GIR_EraseFromParent, /*InsnID*/0,
      // GIR_Coverage, 2771,
      GIR_Done,
    // Label 2078: @136366
    GIM_Try, /*On fail goto*//*Label 2079*/ GIMT_Encode4(136424), // Rule ID 2773 //
      GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasFlatAddressSpace),
      GIM_CheckMemoryAddressSpace, /*MI*/0, /*MMO*/0, /*NumAddrSpace*/2, /*AddrSpace*/0, /*AddrSpace*/1,
      GIM_CheckAtomicOrdering, /*MI*/0, /*Order*/(uint8_t)AtomicOrdering::NotAtomic,
      GIM_CheckPointerToAny, /*MI*/0, /*Op*/1, /*SizeInBits*/0,
      GIM_CheckComplexPattern, /*MI*/0, /*Op*/1, /*Renderer*/GIMT_Encode2(0), GIMT_Encode2(GICP_gi_flat_offset),
      // (st f32:{ *:[f32] }:$data, (FlatOffset:{ *:[iPTR] } i64:{ *:[i64] }:$vaddr, i32:{ *:[i32] }:$offset))<<P:Predicate_unindexedstore>><<P:Predicate_store_flat>>  =>  (FLAT_STORE_DWORD ?:{ *:[i64] }:$vaddr, anonymous_15037:{ *:[f32] }:$data, ?:{ *:[i32] }:$offset)
      GIR_BuildMI, /*InsnID*/0, /*Opcode*/GIMT_Encode2(AMDGPU::FLAT_STORE_DWORD),
      GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/0, // vaddr
      GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/0, // data
      GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/1, // offset
      GIR_AddImm8, /*InsnID*/0, /*Imm*/0,
      GIR_MergeMemOperands, /*InsnID*/0, /*NumInsns*/1, /*MergeInsnID's*/0,
      GIR_ConstrainSelectedInstOperands, /*InsnID*/0,
      GIR_EraseFromParent, /*InsnID*/0,
      // GIR_Coverage, 2773,
      GIR_Done,
    // Label 2079: @136424
    GIM_Reject,
    // Label 1815: @136425
    GIM_Try, /*On fail goto*//*Label 2080*/ GIMT_Encode4(136495), // Rule ID 6817 //
      GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasUnalignedAccessMode_LDSRequiresM0Init),
      GIM_CheckMemorySizeEqualToLLT, /*MI*/0, /*MMO*/0, /*OpIdx*/0,
      GIM_CheckMemoryAddressSpace, /*MI*/0, /*MMO*/0, /*NumAddrSpace*/1, /*AddrSpace*/3,
      GIM_CheckMemoryAddressSpace, /*MI*/0, /*MMO*/0, /*NumAddrSpace*/1, /*AddrSpace*/3,
      GIM_CheckAtomicOrdering, /*MI*/0, /*Order*/(uint8_t)AtomicOrdering::NotAtomic,
      GIM_CheckPointerToAny, /*MI*/0, /*Op*/1, /*SizeInBits*/0,
      GIM_CheckCxxInsnPredicate, /*MI*/0, /*FnId*/GIMT_Encode2(GICXXPred_MI_Predicate_store_align_less_than_4_local_m0),
      GIM_CheckComplexPattern, /*MI*/0, /*Op*/1, /*Renderer*/GIMT_Encode2(0), GIMT_Encode2(GICP_gi_ds_1addr_1offset),
      // (AMDGPUst_glue i64:{ *:[i64] }:$value, (DS1Addr1Offset:{ *:[iPTR] } i32:{ *:[i32] }:$ptr, i32:{ *:[i32] }:$offset))<<P:Predicate_unindexedstore_glue>><<P:Predicate_store_glue>><<P:Predicate_store_local_m0>><<P:Predicate_store_align_less_than_4_local_m0>>  =>  (DS_WRITE_B64 ?:{ *:[i32] }:$ptr, anonymous_15036:{ *:[i64] }:$value, offset:{ *:[i32] }:$offset, 0:{ *:[i1] })
      GIR_BuildMI, /*InsnID*/0, /*Opcode*/GIMT_Encode2(AMDGPU::DS_WRITE_B64),
      GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/0, // ptr
      GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/0, // value
      GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/1, // offset
      GIR_AddImm8, /*InsnID*/0, /*Imm*/0,
      GIR_MergeMemOperands, /*InsnID*/0, /*NumInsns*/1, /*MergeInsnID's*/0,
      GIR_ConstrainSelectedInstOperands, /*InsnID*/0,
      GIR_EraseFromParent, /*InsnID*/0,
      // GIR_Coverage, 6817,
      GIR_Done,
    // Label 2080: @136495
    GIM_Try, /*On fail goto*//*Label 2081*/ GIMT_Encode4(136565), // Rule ID 6821 //
      GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasUnalignedAccessMode_LDSRequiresM0Init),
      GIM_CheckMemorySizeEqualToLLT, /*MI*/0, /*MMO*/0, /*OpIdx*/0,
      GIM_CheckMemoryAddressSpace, /*MI*/0, /*MMO*/0, /*NumAddrSpace*/1, /*AddrSpace*/3,
      GIM_CheckMemoryAddressSpace, /*MI*/0, /*MMO*/0, /*NumAddrSpace*/1, /*AddrSpace*/3,
      GIM_CheckAtomicOrdering, /*MI*/0, /*Order*/(uint8_t)AtomicOrdering::NotAtomic,
      GIM_CheckPointerToAny, /*MI*/0, /*Op*/1, /*SizeInBits*/0,
      GIM_CheckCxxInsnPredicate, /*MI*/0, /*FnId*/GIMT_Encode2(GICXXPred_MI_Predicate_store_align_less_than_4_local_m0),
      GIM_CheckComplexPattern, /*MI*/0, /*Op*/1, /*Renderer*/GIMT_Encode2(0), GIMT_Encode2(GICP_gi_ds_1addr_1offset),
      // (AMDGPUst_glue f64:{ *:[f64] }:$value, (DS1Addr1Offset:{ *:[iPTR] } i32:{ *:[i32] }:$ptr, i32:{ *:[i32] }:$offset))<<P:Predicate_unindexedstore_glue>><<P:Predicate_store_glue>><<P:Predicate_store_local_m0>><<P:Predicate_store_align_less_than_4_local_m0>>  =>  (DS_WRITE_B64 ?:{ *:[i32] }:$ptr, anonymous_15036:{ *:[f64] }:$value, offset:{ *:[i32] }:$offset, 0:{ *:[i1] })
      GIR_BuildMI, /*InsnID*/0, /*Opcode*/GIMT_Encode2(AMDGPU::DS_WRITE_B64),
      GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/0, // ptr
      GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/0, // value
      GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/1, // offset
      GIR_AddImm8, /*InsnID*/0, /*Imm*/0,
      GIR_MergeMemOperands, /*InsnID*/0, /*NumInsns*/1, /*MergeInsnID's*/0,
      GIR_ConstrainSelectedInstOperands, /*InsnID*/0,
      GIR_EraseFromParent, /*InsnID*/0,
      // GIR_Coverage, 6821,
      GIR_Done,
    // Label 2081: @136565
    GIM_Try, /*On fail goto*//*Label 2082*/ GIMT_Encode4(136630), // Rule ID 6741 //
      GIM_CheckFeatures, GIMT_Encode2(GIFBS_LDSRequiresM0Init),
      GIM_CheckMemorySizeEqualToLLT, /*MI*/0, /*MMO*/0, /*OpIdx*/0,
      GIM_CheckMemoryAddressSpace, /*MI*/0, /*MMO*/0, /*NumAddrSpace*/1, /*AddrSpace*/3,
      GIM_CheckMemoryAlignment, /*MI*/0, /*MMO*/0, /*MinAlign*/8,
      GIM_CheckAtomicOrdering, /*MI*/0, /*Order*/(uint8_t)AtomicOrdering::NotAtomic,
      GIM_CheckPointerToAny, /*MI*/0, /*Op*/1, /*SizeInBits*/0,
      GIM_CheckComplexPattern, /*MI*/0, /*Op*/1, /*Renderer*/GIMT_Encode2(0), GIMT_Encode2(GICP_gi_ds_1addr_1offset),
      // (AMDGPUst_glue i64:{ *:[i64] }:$value, (DS1Addr1Offset:{ *:[iPTR] } i32:{ *:[i32] }:$ptr, i32:{ *:[i32] }:$offset))<<P:Predicate_unindexedstore_glue>><<P:Predicate_store_glue>><<P:Predicate_store_local_m0>><<P:Predicate_store_align8_local_m0>>  =>  (DS_WRITE_B64 ?:{ *:[i32] }:$ptr, anonymous_15036:{ *:[i64] }:$value, offset:{ *:[i32] }:$offset, 0:{ *:[i1] })
      GIR_BuildMI, /*InsnID*/0, /*Opcode*/GIMT_Encode2(AMDGPU::DS_WRITE_B64),
      GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/0, // ptr
      GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/0, // value
      GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/1, // offset
      GIR_AddImm8, /*InsnID*/0, /*Imm*/0,
      GIR_MergeMemOperands, /*InsnID*/0, /*NumInsns*/1, /*MergeInsnID's*/0,
      GIR_ConstrainSelectedInstOperands, /*InsnID*/0,
      GIR_EraseFromParent, /*InsnID*/0,
      // GIR_Coverage, 6741,
      GIR_Done,
    // Label 2082: @136630
    GIM_Try, /*On fail goto*//*Label 2083*/ GIMT_Encode4(136695), // Rule ID 6745 //
      GIM_CheckFeatures, GIMT_Encode2(GIFBS_LDSRequiresM0Init),
      GIM_CheckMemorySizeEqualToLLT, /*MI*/0, /*MMO*/0, /*OpIdx*/0,
      GIM_CheckMemoryAddressSpace, /*MI*/0, /*MMO*/0, /*NumAddrSpace*/1, /*AddrSpace*/3,
      GIM_CheckMemoryAlignment, /*MI*/0, /*MMO*/0, /*MinAlign*/8,
      GIM_CheckAtomicOrdering, /*MI*/0, /*Order*/(uint8_t)AtomicOrdering::NotAtomic,
      GIM_CheckPointerToAny, /*MI*/0, /*Op*/1, /*SizeInBits*/0,
      GIM_CheckComplexPattern, /*MI*/0, /*Op*/1, /*Renderer*/GIMT_Encode2(0), GIMT_Encode2(GICP_gi_ds_1addr_1offset),
      // (AMDGPUst_glue f64:{ *:[f64] }:$value, (DS1Addr1Offset:{ *:[iPTR] } i32:{ *:[i32] }:$ptr, i32:{ *:[i32] }:$offset))<<P:Predicate_unindexedstore_glue>><<P:Predicate_store_glue>><<P:Predicate_store_local_m0>><<P:Predicate_store_align8_local_m0>>  =>  (DS_WRITE_B64 ?:{ *:[i32] }:$ptr, anonymous_15036:{ *:[f64] }:$value, offset:{ *:[i32] }:$offset, 0:{ *:[i1] })
      GIR_BuildMI, /*InsnID*/0, /*Opcode*/GIMT_Encode2(AMDGPU::DS_WRITE_B64),
      GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/0, // ptr
      GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/0, // value
      GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/1, // offset
      GIR_AddImm8, /*InsnID*/0, /*Imm*/0,
      GIR_MergeMemOperands, /*InsnID*/0, /*NumInsns*/1, /*MergeInsnID's*/0,
      GIR_ConstrainSelectedInstOperands, /*InsnID*/0,
      GIR_EraseFromParent, /*InsnID*/0,
      // GIR_Coverage, 6745,
      GIR_Done,
    // Label 2083: @136695
    GIM_Try, /*On fail goto*//*Label 2084*/ GIMT_Encode4(136761), // Rule ID 6818 //
      GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasUnalignedAccessMode_NotLDSRequiresM0Init),
      GIM_CheckMemoryAddressSpace, /*MI*/0, /*MMO*/0, /*NumAddrSpace*/1, /*AddrSpace*/3,
      GIM_CheckMemoryAddressSpace, /*MI*/0, /*MMO*/0, /*NumAddrSpace*/1, /*AddrSpace*/3,
      GIM_CheckAtomicOrdering, /*MI*/0, /*Order*/(uint8_t)AtomicOrdering::NotAtomic,
      GIM_CheckPointerToAny, /*MI*/0, /*Op*/1, /*SizeInBits*/0,
      GIM_CheckCxxInsnPredicate, /*MI*/0, /*FnId*/GIMT_Encode2(GICXXPred_MI_Predicate_store_align_less_than_4_local),
      GIM_CheckComplexPattern, /*MI*/0, /*Op*/1, /*Renderer*/GIMT_Encode2(0), GIMT_Encode2(GICP_gi_ds_1addr_1offset),
      // (st i64:{ *:[i64] }:$value, (DS1Addr1Offset:{ *:[iPTR] } i32:{ *:[i32] }:$ptr, i32:{ *:[i32] }:$offset))<<P:Predicate_unindexedstore>><<P:Predicate_store_local>><<P:Predicate_store_align_less_than_4_local>>  =>  (DS_WRITE_B64_gfx9 ?:{ *:[i32] }:$ptr, anonymous_15036:{ *:[i64] }:$value, offset:{ *:[i32] }:$offset, 0:{ *:[i1] })
      GIR_BuildMI, /*InsnID*/0, /*Opcode*/GIMT_Encode2(AMDGPU::DS_WRITE_B64_gfx9),
      GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/0, // ptr
      GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/0, // value
      GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/1, // offset
      GIR_AddImm8, /*InsnID*/0, /*Imm*/0,
      GIR_MergeMemOperands, /*InsnID*/0, /*NumInsns*/1, /*MergeInsnID's*/0,
      GIR_ConstrainSelectedInstOperands, /*InsnID*/0,
      GIR_EraseFromParent, /*InsnID*/0,
      // GIR_Coverage, 6818,
      GIR_Done,
    // Label 2084: @136761
    GIM_Try, /*On fail goto*//*Label 2085*/ GIMT_Encode4(136827), // Rule ID 6822 //
      GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasUnalignedAccessMode_NotLDSRequiresM0Init),
      GIM_CheckMemoryAddressSpace, /*MI*/0, /*MMO*/0, /*NumAddrSpace*/1, /*AddrSpace*/3,
      GIM_CheckMemoryAddressSpace, /*MI*/0, /*MMO*/0, /*NumAddrSpace*/1, /*AddrSpace*/3,
      GIM_CheckAtomicOrdering, /*MI*/0, /*Order*/(uint8_t)AtomicOrdering::NotAtomic,
      GIM_CheckPointerToAny, /*MI*/0, /*Op*/1, /*SizeInBits*/0,
      GIM_CheckCxxInsnPredicate, /*MI*/0, /*FnId*/GIMT_Encode2(GICXXPred_MI_Predicate_store_align_less_than_4_local),
      GIM_CheckComplexPattern, /*MI*/0, /*Op*/1, /*Renderer*/GIMT_Encode2(0), GIMT_Encode2(GICP_gi_ds_1addr_1offset),
      // (st f64:{ *:[f64] }:$value, (DS1Addr1Offset:{ *:[iPTR] } i32:{ *:[i32] }:$ptr, i32:{ *:[i32] }:$offset))<<P:Predicate_unindexedstore>><<P:Predicate_store_local>><<P:Predicate_store_align_less_than_4_local>>  =>  (DS_WRITE_B64_gfx9 ?:{ *:[i32] }:$ptr, anonymous_15036:{ *:[f64] }:$value, offset:{ *:[i32] }:$offset, 0:{ *:[i1] })
      GIR_BuildMI, /*InsnID*/0, /*Opcode*/GIMT_Encode2(AMDGPU::DS_WRITE_B64_gfx9),
      GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/0, // ptr
      GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/0, // value
      GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/1, // offset
      GIR_AddImm8, /*InsnID*/0, /*Imm*/0,
      GIR_MergeMemOperands, /*InsnID*/0, /*NumInsns*/1, /*MergeInsnID's*/0,
      GIR_ConstrainSelectedInstOperands, /*InsnID*/0,
      GIR_EraseFromParent, /*InsnID*/0,
      // GIR_Coverage, 6822,
      GIR_Done,
    // Label 2085: @136827
    GIM_Try, /*On fail goto*//*Label 2086*/ GIMT_Encode4(136888), // Rule ID 6742 //
      GIM_CheckFeatures, GIMT_Encode2(GIFBS_NotLDSRequiresM0Init),
      GIM_CheckMemoryAddressSpace, /*MI*/0, /*MMO*/0, /*NumAddrSpace*/1, /*AddrSpace*/3,
      GIM_CheckMemoryAlignment, /*MI*/0, /*MMO*/0, /*MinAlign*/8,
      GIM_CheckAtomicOrdering, /*MI*/0, /*Order*/(uint8_t)AtomicOrdering::NotAtomic,
      GIM_CheckPointerToAny, /*MI*/0, /*Op*/1, /*SizeInBits*/0,
      GIM_CheckComplexPattern, /*MI*/0, /*Op*/1, /*Renderer*/GIMT_Encode2(0), GIMT_Encode2(GICP_gi_ds_1addr_1offset),
      // (st i64:{ *:[i64] }:$value, (DS1Addr1Offset:{ *:[iPTR] } i32:{ *:[i32] }:$ptr, i32:{ *:[i32] }:$offset))<<P:Predicate_unindexedstore>><<P:Predicate_store_local>><<P:Predicate_store_align8_local>>  =>  (DS_WRITE_B64_gfx9 ?:{ *:[i32] }:$ptr, anonymous_15036:{ *:[i64] }:$value, offset:{ *:[i32] }:$offset, 0:{ *:[i1] })
      GIR_BuildMI, /*InsnID*/0, /*Opcode*/GIMT_Encode2(AMDGPU::DS_WRITE_B64_gfx9),
      GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/0, // ptr
      GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/0, // value
      GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/1, // offset
      GIR_AddImm8, /*InsnID*/0, /*Imm*/0,
      GIR_MergeMemOperands, /*InsnID*/0, /*NumInsns*/1, /*MergeInsnID's*/0,
      GIR_ConstrainSelectedInstOperands, /*InsnID*/0,
      GIR_EraseFromParent, /*InsnID*/0,
      // GIR_Coverage, 6742,
      GIR_Done,
    // Label 2086: @136888
    GIM_Try, /*On fail goto*//*Label 2087*/ GIMT_Encode4(136949), // Rule ID 6746 //
      GIM_CheckFeatures, GIMT_Encode2(GIFBS_NotLDSRequiresM0Init),
      GIM_CheckMemoryAddressSpace, /*MI*/0, /*MMO*/0, /*NumAddrSpace*/1, /*AddrSpace*/3,
      GIM_CheckMemoryAlignment, /*MI*/0, /*MMO*/0, /*MinAlign*/8,
      GIM_CheckAtomicOrdering, /*MI*/0, /*Order*/(uint8_t)AtomicOrdering::NotAtomic,
      GIM_CheckPointerToAny, /*MI*/0, /*Op*/1, /*SizeInBits*/0,
      GIM_CheckComplexPattern, /*MI*/0, /*Op*/1, /*Renderer*/GIMT_Encode2(0), GIMT_Encode2(GICP_gi_ds_1addr_1offset),
      // (st f64:{ *:[f64] }:$value, (DS1Addr1Offset:{ *:[iPTR] } i32:{ *:[i32] }:$ptr, i32:{ *:[i32] }:$offset))<<P:Predicate_unindexedstore>><<P:Predicate_store_local>><<P:Predicate_store_align8_local>>  =>  (DS_WRITE_B64_gfx9 ?:{ *:[i32] }:$ptr, anonymous_15036:{ *:[f64] }:$value, offset:{ *:[i32] }:$offset, 0:{ *:[i1] })
      GIR_BuildMI, /*InsnID*/0, /*Opcode*/GIMT_Encode2(AMDGPU::DS_WRITE_B64_gfx9),
      GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/0, // ptr
      GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/0, // value
      GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/1, // offset
      GIR_AddImm8, /*InsnID*/0, /*Imm*/0,
      GIR_MergeMemOperands, /*InsnID*/0, /*NumInsns*/1, /*MergeInsnID's*/0,
      GIR_ConstrainSelectedInstOperands, /*InsnID*/0,
      GIR_EraseFromParent, /*InsnID*/0,
      // GIR_Coverage, 6746,
      GIR_Done,
    // Label 2087: @136949
    GIM_Try, /*On fail goto*//*Label 2088*/ GIMT_Encode4(137011), // Rule ID 3487 //
      GIM_CheckFeatures, GIMT_Encode2(GIFBS_EnableFlatScratch_HasFlatScratchInsts_HasFlatScratchSVSMode),
      GIM_CheckMemoryAddressSpace, /*MI*/0, /*MMO*/0, /*NumAddrSpace*/1, /*AddrSpace*/5,
      GIM_CheckAtomicOrdering, /*MI*/0, /*Order*/(uint8_t)AtomicOrdering::NotAtomic,
      GIM_CheckPointerToAny, /*MI*/0, /*Op*/1, /*SizeInBits*/0,
      GIM_CheckComplexPattern, /*MI*/0, /*Op*/1, /*Renderer*/GIMT_Encode2(0), GIMT_Encode2(GICP_gi_flat_scratch_svaddr),
      // (st i64:{ *:[i64] }:$data, (ScratchSVAddr:{ *:[iPTR] } VGPR_32:{ *:[i32] }:$vaddr, SGPR_32:{ *:[i32] }:$saddr, i32:{ *:[i32] }:$offset))<<P:Predicate_unindexedstore>><<P:Predicate_store_private>>  =>  (SCRATCH_STORE_DWORDX2_SVS anonymous_15036:{ *:[i64] }:$data, ?:{ *:[i32] }:$vaddr, ?:{ *:[i32] }:$saddr, ?:{ *:[i32] }:$offset)
      GIR_BuildMI, /*InsnID*/0, /*Opcode*/GIMT_Encode2(AMDGPU::SCRATCH_STORE_DWORDX2_SVS),
      GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/0, // data
      GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/0, // vaddr
      GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/1, // saddr
      GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/2, // offset
      GIR_AddImm8, /*InsnID*/0, /*Imm*/0,
      GIR_MergeMemOperands, /*InsnID*/0, /*NumInsns*/1, /*MergeInsnID's*/0,
      GIR_ConstrainSelectedInstOperands, /*InsnID*/0,
      GIR_EraseFromParent, /*InsnID*/0,
      // GIR_Coverage, 3487,
      GIR_Done,
    // Label 2088: @137011
    GIM_Try, /*On fail goto*//*Label 2089*/ GIMT_Encode4(137073), // Rule ID 3493 //
      GIM_CheckFeatures, GIMT_Encode2(GIFBS_EnableFlatScratch_HasFlatScratchInsts_HasFlatScratchSVSMode),
      GIM_CheckMemoryAddressSpace, /*MI*/0, /*MMO*/0, /*NumAddrSpace*/1, /*AddrSpace*/5,
      GIM_CheckAtomicOrdering, /*MI*/0, /*Order*/(uint8_t)AtomicOrdering::NotAtomic,
      GIM_CheckPointerToAny, /*MI*/0, /*Op*/1, /*SizeInBits*/0,
      GIM_CheckComplexPattern, /*MI*/0, /*Op*/1, /*Renderer*/GIMT_Encode2(0), GIMT_Encode2(GICP_gi_flat_scratch_svaddr),
      // (st f64:{ *:[f64] }:$data, (ScratchSVAddr:{ *:[iPTR] } VGPR_32:{ *:[i32] }:$vaddr, SGPR_32:{ *:[i32] }:$saddr, i32:{ *:[i32] }:$offset))<<P:Predicate_unindexedstore>><<P:Predicate_store_private>>  =>  (SCRATCH_STORE_DWORDX2_SVS anonymous_15036:{ *:[f64] }:$data, ?:{ *:[i32] }:$vaddr, ?:{ *:[i32] }:$saddr, ?:{ *:[i32] }:$offset)
      GIR_BuildMI, /*InsnID*/0, /*Opcode*/GIMT_Encode2(AMDGPU::SCRATCH_STORE_DWORDX2_SVS),
      GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/0, // data
      GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/0, // vaddr
      GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/1, // saddr
      GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/2, // offset
      GIR_AddImm8, /*InsnID*/0, /*Imm*/0,
      GIR_MergeMemOperands, /*InsnID*/0, /*NumInsns*/1, /*MergeInsnID's*/0,
      GIR_ConstrainSelectedInstOperands, /*InsnID*/0,
      GIR_EraseFromParent, /*InsnID*/0,
      // GIR_Coverage, 3493,
      GIR_Done,
    // Label 2089: @137073
    GIM_Try, /*On fail goto*//*Label 2090*/ GIMT_Encode4(137130), // Rule ID 3486 //
      GIM_CheckFeatures, GIMT_Encode2(GIFBS_EnableFlatScratch_HasFlatScratchInsts),
      GIM_CheckMemoryAddressSpace, /*MI*/0, /*MMO*/0, /*NumAddrSpace*/1, /*AddrSpace*/5,
      GIM_CheckAtomicOrdering, /*MI*/0, /*Order*/(uint8_t)AtomicOrdering::NotAtomic,
      GIM_CheckPointerToAny, /*MI*/0, /*Op*/1, /*SizeInBits*/0,
      GIM_CheckComplexPattern, /*MI*/0, /*Op*/1, /*Renderer*/GIMT_Encode2(0), GIMT_Encode2(GICP_gi_flat_scratch_saddr),
      // (st i64:{ *:[i64] }:$data, (ScratchSAddr:{ *:[iPTR] } SGPR_32:{ *:[i32] }:$saddr, i32:{ *:[i32] }:$offset))<<P:Predicate_unindexedstore>><<P:Predicate_store_private>>  =>  (SCRATCH_STORE_DWORDX2_SADDR anonymous_15036:{ *:[i64] }:$data, ?:{ *:[i32] }:$saddr, ?:{ *:[i32] }:$offset)
      GIR_BuildMI, /*InsnID*/0, /*Opcode*/GIMT_Encode2(AMDGPU::SCRATCH_STORE_DWORDX2_SADDR),
      GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/0, // data
      GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/0, // saddr
      GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/1, // offset
      GIR_AddImm8, /*InsnID*/0, /*Imm*/0,
      GIR_MergeMemOperands, /*InsnID*/0, /*NumInsns*/1, /*MergeInsnID's*/0,
      GIR_ConstrainSelectedInstOperands, /*InsnID*/0,
      GIR_EraseFromParent, /*InsnID*/0,
      // GIR_Coverage, 3486,
      GIR_Done,
    // Label 2090: @137130
    GIM_Try, /*On fail goto*//*Label 2091*/ GIMT_Encode4(137187), // Rule ID 3492 //
      GIM_CheckFeatures, GIMT_Encode2(GIFBS_EnableFlatScratch_HasFlatScratchInsts),
      GIM_CheckMemoryAddressSpace, /*MI*/0, /*MMO*/0, /*NumAddrSpace*/1, /*AddrSpace*/5,
      GIM_CheckAtomicOrdering, /*MI*/0, /*Order*/(uint8_t)AtomicOrdering::NotAtomic,
      GIM_CheckPointerToAny, /*MI*/0, /*Op*/1, /*SizeInBits*/0,
      GIM_CheckComplexPattern, /*MI*/0, /*Op*/1, /*Renderer*/GIMT_Encode2(0), GIMT_Encode2(GICP_gi_flat_scratch_saddr),
      // (st f64:{ *:[f64] }:$data, (ScratchSAddr:{ *:[iPTR] } SGPR_32:{ *:[i32] }:$saddr, i32:{ *:[i32] }:$offset))<<P:Predicate_unindexedstore>><<P:Predicate_store_private>>  =>  (SCRATCH_STORE_DWORDX2_SADDR anonymous_15036:{ *:[f64] }:$data, ?:{ *:[i32] }:$saddr, ?:{ *:[i32] }:$offset)
      GIR_BuildMI, /*InsnID*/0, /*Opcode*/GIMT_Encode2(AMDGPU::SCRATCH_STORE_DWORDX2_SADDR),
      GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/0, // data
      GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/0, // saddr
      GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/1, // offset
      GIR_AddImm8, /*InsnID*/0, /*Imm*/0,
      GIR_MergeMemOperands, /*InsnID*/0, /*NumInsns*/1, /*MergeInsnID's*/0,
      GIR_ConstrainSelectedInstOperands, /*InsnID*/0,
      GIR_EraseFromParent, /*InsnID*/0,
      // GIR_Coverage, 3492,
      GIR_Done,
    // Label 2091: @137187
    GIM_Try, /*On fail goto*//*Label 2092*/ GIMT_Encode4(137244), // Rule ID 3485 //
      GIM_CheckFeatures, GIMT_Encode2(GIFBS_EnableFlatScratch_HasFlatScratchInsts),
      GIM_CheckMemoryAddressSpace, /*MI*/0, /*MMO*/0, /*NumAddrSpace*/1, /*AddrSpace*/5,
      GIM_CheckAtomicOrdering, /*MI*/0, /*Order*/(uint8_t)AtomicOrdering::NotAtomic,
      GIM_CheckPointerToAny, /*MI*/0, /*Op*/1, /*SizeInBits*/0,
      GIM_CheckComplexPattern, /*MI*/0, /*Op*/1, /*Renderer*/GIMT_Encode2(0), GIMT_Encode2(GICP_gi_flat_scratch_offset),
      // (st i64:{ *:[i64] }:$data, (ScratchOffset:{ *:[iPTR] } VGPR_32:{ *:[i32] }:$vaddr, i32:{ *:[i32] }:$offset))<<P:Predicate_unindexedstore>><<P:Predicate_store_private>>  =>  (SCRATCH_STORE_DWORDX2 anonymous_15036:{ *:[i64] }:$data, ?:{ *:[i32] }:$vaddr, ?:{ *:[i32] }:$offset)
      GIR_BuildMI, /*InsnID*/0, /*Opcode*/GIMT_Encode2(AMDGPU::SCRATCH_STORE_DWORDX2),
      GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/0, // data
      GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/0, // vaddr
      GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/1, // offset
      GIR_AddImm8, /*InsnID*/0, /*Imm*/0,
      GIR_MergeMemOperands, /*InsnID*/0, /*NumInsns*/1, /*MergeInsnID's*/0,
      GIR_ConstrainSelectedInstOperands, /*InsnID*/0,
      GIR_EraseFromParent, /*InsnID*/0,
      // GIR_Coverage, 3485,
      GIR_Done,
    // Label 2092: @137244
    GIM_Try, /*On fail goto*//*Label 2093*/ GIMT_Encode4(137301), // Rule ID 3491 //
      GIM_CheckFeatures, GIMT_Encode2(GIFBS_EnableFlatScratch_HasFlatScratchInsts),
      GIM_CheckMemoryAddressSpace, /*MI*/0, /*MMO*/0, /*NumAddrSpace*/1, /*AddrSpace*/5,
      GIM_CheckAtomicOrdering, /*MI*/0, /*Order*/(uint8_t)AtomicOrdering::NotAtomic,
      GIM_CheckPointerToAny, /*MI*/0, /*Op*/1, /*SizeInBits*/0,
      GIM_CheckComplexPattern, /*MI*/0, /*Op*/1, /*Renderer*/GIMT_Encode2(0), GIMT_Encode2(GICP_gi_flat_scratch_offset),
      // (st f64:{ *:[f64] }:$data, (ScratchOffset:{ *:[iPTR] } VGPR_32:{ *:[i32] }:$vaddr, i32:{ *:[i32] }:$offset))<<P:Predicate_unindexedstore>><<P:Predicate_store_private>>  =>  (SCRATCH_STORE_DWORDX2 anonymous_15036:{ *:[f64] }:$data, ?:{ *:[i32] }:$vaddr, ?:{ *:[i32] }:$offset)
      GIR_BuildMI, /*InsnID*/0, /*Opcode*/GIMT_Encode2(AMDGPU::SCRATCH_STORE_DWORDX2),
      GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/0, // data
      GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/0, // vaddr
      GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/1, // offset
      GIR_AddImm8, /*InsnID*/0, /*Imm*/0,
      GIR_MergeMemOperands, /*InsnID*/0, /*NumInsns*/1, /*MergeInsnID's*/0,
      GIR_ConstrainSelectedInstOperands, /*InsnID*/0,
      GIR_EraseFromParent, /*InsnID*/0,
      // GIR_Coverage, 3491,
      GIR_Done,
    // Label 2093: @137301
    GIM_Try, /*On fail goto*//*Label 2094*/ GIMT_Encode4(137378), // Rule ID 5491 //
      GIM_CheckFeatures, GIMT_Encode2(GIFBS_isGFX6GFX7),
      GIM_CheckMemorySizeEqualTo, /*MI*/0, /*MMO*/0, /*Size*/GIMT_Encode4(8),
      GIM_CheckMemoryAddressSpace, /*MI*/0, /*MMO*/0, /*NumAddrSpace*/1, /*AddrSpace*/1,
      GIM_CheckAtomicOrderingOrStrongerThan, /*MI*/0, /*Order*/(uint8_t)AtomicOrdering::Unordered,
      GIM_CheckPointerToAny, /*MI*/0, /*Op*/1, /*SizeInBits*/0,
      GIM_CheckComplexPattern, /*MI*/0, /*Op*/1, /*Renderer*/GIMT_Encode2(0), GIMT_Encode2(GICP_gi_mubuf_addr64),
      // (atomic_store i64:{ *:[i64] }:$val, (MUBUFAddr64:{ *:[iPTR] } v4i32:{ *:[v4i32] }:$srsrc, i64:{ *:[i64] }:$vaddr, i32:{ *:[i32] }:$soffset, i32:{ *:[i32] }:$offset))<<P:Predicate_atomic_store_64>><<P:Predicate_atomic_store_64_global>>  =>  (BUFFER_STORE_DWORDX2_ADDR64 ?:{ *:[i64] }:$val, ?:{ *:[i64] }:$vaddr, ?:{ *:[v4i32] }:$srsrc, ?:{ *:[i32] }:$soffset, ?:{ *:[i32] }:$offset)
      GIR_BuildMI, /*InsnID*/0, /*Opcode*/GIMT_Encode2(AMDGPU::BUFFER_STORE_DWORDX2_ADDR64),
      GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/0, // val
      GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/1, // vaddr
      GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/0, // srsrc
      GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/2, // soffset
      GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/3, // offset
      GIR_AddImm8, /*InsnID*/0, /*Imm*/0,
      GIR_AddImm8, /*InsnID*/0, /*Imm*/0,
      GIR_MergeMemOperands, /*InsnID*/0, /*NumInsns*/1, /*MergeInsnID's*/0,
      GIR_ConstrainSelectedInstOperands, /*InsnID*/0,
      GIR_EraseFromParent, /*InsnID*/0,
      // GIR_Coverage, 5491,
      GIR_Done,
    // Label 2094: @137378
    GIM_Try, /*On fail goto*//*Label 2095*/ GIMT_Encode4(137448), // Rule ID 3838 //
      GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasUnrestrictedSOffset),
      GIM_CheckMemoryAddressSpace, /*MI*/0, /*MMO*/0, /*NumAddrSpace*/1, /*AddrSpace*/1,
      GIM_CheckAtomicOrdering, /*MI*/0, /*Order*/(uint8_t)AtomicOrdering::NotAtomic,
      GIM_CheckPointerToAny, /*MI*/0, /*Op*/1, /*SizeInBits*/0,
      GIM_CheckComplexPattern, /*MI*/0, /*Op*/1, /*Renderer*/GIMT_Encode2(0), GIMT_Encode2(GICP_gi_mubuf_addr64),
      // (st i64:{ *:[i64] }:$vdata, (MUBUFAddr64:{ *:[iPTR] } v4i32:{ *:[v4i32] }:$srsrc, i64:{ *:[i64] }:$vaddr, i32:{ *:[i32] }:$soffset, i32:{ *:[i32] }:$offset))<<P:Predicate_unindexedstore>><<P:Predicate_store_global>>  =>  (BUFFER_STORE_DWORDX2_ADDR64 i64:{ *:[i64] }:$vdata, i64:{ *:[i64] }:$vaddr, v4i32:{ *:[v4i32] }:$srsrc, i32:{ *:[i32] }:$soffset, i32:{ *:[i32] }:$offset)
      GIR_BuildMI, /*InsnID*/0, /*Opcode*/GIMT_Encode2(AMDGPU::BUFFER_STORE_DWORDX2_ADDR64),
      GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/0, // vdata
      GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/1, // vaddr
      GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/0, // srsrc
      GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/2, // soffset
      GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/3, // offset
      GIR_AddImm8, /*InsnID*/0, /*Imm*/0,
      GIR_AddImm8, /*InsnID*/0, /*Imm*/0,
      GIR_MergeMemOperands, /*InsnID*/0, /*NumInsns*/1, /*MergeInsnID's*/0,
      GIR_ConstrainSelectedInstOperands, /*InsnID*/0,
      GIR_EraseFromParent, /*InsnID*/0,
      // GIR_Coverage, 3838,
      GIR_Done,
    // Label 2095: @137448
    GIM_Try, /*On fail goto*//*Label 2096*/ GIMT_Encode4(137515), // Rule ID 3840 //
      GIM_CheckMemoryAddressSpace, /*MI*/0, /*MMO*/0, /*NumAddrSpace*/1, /*AddrSpace*/1,
      GIM_CheckAtomicOrdering, /*MI*/0, /*Order*/(uint8_t)AtomicOrdering::NotAtomic,
      GIM_CheckPointerToAny, /*MI*/0, /*Op*/1, /*SizeInBits*/0,
      GIM_CheckComplexPattern, /*MI*/0, /*Op*/1, /*Renderer*/GIMT_Encode2(0), GIMT_Encode2(GICP_gi_mubuf_addr64),
      // (st i64:{ *:[i64] }:$vdata, (MUBUFAddr64:{ *:[iPTR] } v4i32:{ *:[v4i32] }:$srsrc, i64:{ *:[i64] }:$vaddr, i32:{ *:[i32] }:$soffset, i32:{ *:[i32] }:$offset))<<P:Predicate_unindexedstore>><<P:Predicate_store_global>>  =>  (BUFFER_STORE_DWORDX2_VBUFFER_ADDR64 i64:{ *:[i64] }:$vdata, i64:{ *:[i64] }:$vaddr, v4i32:{ *:[v4i32] }:$srsrc, i32:{ *:[i32] }:$soffset, i32:{ *:[i32] }:$offset)
      GIR_BuildMI, /*InsnID*/0, /*Opcode*/GIMT_Encode2(AMDGPU::BUFFER_STORE_DWORDX2_VBUFFER_ADDR64),
      GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/0, // vdata
      GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/1, // vaddr
      GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/0, // srsrc
      GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/2, // soffset
      GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/3, // offset
      GIR_AddImm8, /*InsnID*/0, /*Imm*/0,
      GIR_AddImm8, /*InsnID*/0, /*Imm*/0,
      GIR_MergeMemOperands, /*InsnID*/0, /*NumInsns*/1, /*MergeInsnID's*/0,
      GIR_ConstrainSelectedInstOperands, /*InsnID*/0,
      GIR_EraseFromParent, /*InsnID*/0,
      // GIR_Coverage, 3840,
      GIR_Done,
    // Label 2096: @137515
    GIM_Try, /*On fail goto*//*Label 2097*/ GIMT_Encode4(137585), // Rule ID 3842 //
      GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasUnrestrictedSOffset),
      GIM_CheckMemoryAddressSpace, /*MI*/0, /*MMO*/0, /*NumAddrSpace*/1, /*AddrSpace*/1,
      GIM_CheckAtomicOrdering, /*MI*/0, /*Order*/(uint8_t)AtomicOrdering::NotAtomic,
      GIM_CheckPointerToAny, /*MI*/0, /*Op*/1, /*SizeInBits*/0,
      GIM_CheckComplexPattern, /*MI*/0, /*Op*/1, /*Renderer*/GIMT_Encode2(0), GIMT_Encode2(GICP_gi_mubuf_addr64),
      // (st f64:{ *:[f64] }:$vdata, (MUBUFAddr64:{ *:[iPTR] } v4i32:{ *:[v4i32] }:$srsrc, i64:{ *:[i64] }:$vaddr, i32:{ *:[i32] }:$soffset, i32:{ *:[i32] }:$offset))<<P:Predicate_unindexedstore>><<P:Predicate_store_global>>  =>  (BUFFER_STORE_DWORDX2_ADDR64 f64:{ *:[f64] }:$vdata, i64:{ *:[i64] }:$vaddr, v4i32:{ *:[v4i32] }:$srsrc, i32:{ *:[i32] }:$soffset, i32:{ *:[i32] }:$offset)
      GIR_BuildMI, /*InsnID*/0, /*Opcode*/GIMT_Encode2(AMDGPU::BUFFER_STORE_DWORDX2_ADDR64),
      GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/0, // vdata
      GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/1, // vaddr
      GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/0, // srsrc
      GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/2, // soffset
      GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/3, // offset
      GIR_AddImm8, /*InsnID*/0, /*Imm*/0,
      GIR_AddImm8, /*InsnID*/0, /*Imm*/0,
      GIR_MergeMemOperands, /*InsnID*/0, /*NumInsns*/1, /*MergeInsnID's*/0,
      GIR_ConstrainSelectedInstOperands, /*InsnID*/0,
      GIR_EraseFromParent, /*InsnID*/0,
      // GIR_Coverage, 3842,
      GIR_Done,
    // Label 2097: @137585
    GIM_Try, /*On fail goto*//*Label 2098*/ GIMT_Encode4(137652), // Rule ID 3844 //
      GIM_CheckMemoryAddressSpace, /*MI*/0, /*MMO*/0, /*NumAddrSpace*/1, /*AddrSpace*/1,
      GIM_CheckAtomicOrdering, /*MI*/0, /*Order*/(uint8_t)AtomicOrdering::NotAtomic,
      GIM_CheckPointerToAny, /*MI*/0, /*Op*/1, /*SizeInBits*/0,
      GIM_CheckComplexPattern, /*MI*/0, /*Op*/1, /*Renderer*/GIMT_Encode2(0), GIMT_Encode2(GICP_gi_mubuf_addr64),
      // (st f64:{ *:[f64] }:$vdata, (MUBUFAddr64:{ *:[iPTR] } v4i32:{ *:[v4i32] }:$srsrc, i64:{ *:[i64] }:$vaddr, i32:{ *:[i32] }:$soffset, i32:{ *:[i32] }:$offset))<<P:Predicate_unindexedstore>><<P:Predicate_store_global>>  =>  (BUFFER_STORE_DWORDX2_VBUFFER_ADDR64 f64:{ *:[f64] }:$vdata, i64:{ *:[i64] }:$vaddr, v4i32:{ *:[v4i32] }:$srsrc, i32:{ *:[i32] }:$soffset, i32:{ *:[i32] }:$offset)
      GIR_BuildMI, /*InsnID*/0, /*Opcode*/GIMT_Encode2(AMDGPU::BUFFER_STORE_DWORDX2_VBUFFER_ADDR64),
      GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/0, // vdata
      GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/1, // vaddr
      GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/0, // srsrc
      GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/2, // soffset
      GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/3, // offset
      GIR_AddImm8, /*InsnID*/0, /*Imm*/0,
      GIR_AddImm8, /*InsnID*/0, /*Imm*/0,
      GIR_MergeMemOperands, /*InsnID*/0, /*NumInsns*/1, /*MergeInsnID's*/0,
      GIR_ConstrainSelectedInstOperands, /*InsnID*/0,
      GIR_EraseFromParent, /*InsnID*/0,
      // GIR_Coverage, 3844,
      GIR_Done,
    // Label 2098: @137652
    GIM_Try, /*On fail goto*//*Label 2099*/ GIMT_Encode4(137776), // Rule ID 6672 //
      GIM_CheckFeatures, GIMT_Encode2(GIFBS_LDSRequiresM0Init_isGFX7Plus),
      GIM_CheckMemorySizeEqualToLLT, /*MI*/0, /*MMO*/0, /*OpIdx*/0,
      GIM_CheckMemoryAddressSpace, /*MI*/0, /*MMO*/0, /*NumAddrSpace*/1, /*AddrSpace*/3,
      GIM_CheckAtomicOrdering, /*MI*/0, /*Order*/(uint8_t)AtomicOrdering::NotAtomic,
      GIM_CheckPointerToAny, /*MI*/0, /*Op*/1, /*SizeInBits*/0,
      GIM_CheckComplexPattern, /*MI*/0, /*Op*/1, /*Renderer*/GIMT_Encode2(0), GIMT_Encode2(GICP_gi_ds_64bit_4byte_aligned),
      // (AMDGPUst_glue i64:{ *:[i64] }:$value, (DS64Bit4ByteAligned:{ *:[iPTR] } i32:{ *:[i32] }:$ptr, i8:{ *:[i8] }:$offset0, i8:{ *:[i8] }:$offset1))<<P:Predicate_unindexedstore_glue>><<P:Predicate_store_glue>><<P:Predicate_store_local_m0>>  =>  (DS_WRITE2_B32 ?:{ *:[i32] }:$ptr, (EXTRACT_SUBREG:{ *:[i32] } VReg_64:{ *:[i64] }:$value, sub0:{ *:[i32] }), (EXTRACT_SUBREG:{ *:[i32] } VReg_64:{ *:[i64] }:$value, sub1:{ *:[i32] }), ?:{ *:[i8] }:$offset0, ?:{ *:[i8] }:$offset1, 0:{ *:[i1] })
      GIR_MakeTempReg, /*TempRegID*/0, /*TypeID*/GILLT_s32,
      GIR_MakeTempReg, /*TempRegID*/1, /*TypeID*/GILLT_s32,
      GIR_BuildMI, /*InsnID*/2, /*Opcode*/GIMT_Encode2(TargetOpcode::COPY),
      GIR_AddTempRegister, /*InsnID*/2, /*TempRegID*/1, /*TempRegFlags*/GIMT_Encode2(RegState::Define),
      GIR_CopySubReg, /*NewInsnID*/2, /*OldInsnID*/0, /*OpIdx*/0, /*SubRegIdx*/GIMT_Encode2(11), // value
      GIR_ConstrainOperandRC, /*InsnID*/2, /*Op*/0, GIMT_Encode2(AMDGPU::VGPR_32RegClassID),
      GIR_ConstrainOperandRC, /*InsnID*/2, /*Op*/1, GIMT_Encode2(AMDGPU::VReg_64RegClassID),
      GIR_BuildMI, /*InsnID*/1, /*Opcode*/GIMT_Encode2(TargetOpcode::COPY),
      GIR_AddTempRegister, /*InsnID*/1, /*TempRegID*/0, /*TempRegFlags*/GIMT_Encode2(RegState::Define),
      GIR_CopySubReg, /*NewInsnID*/1, /*OldInsnID*/0, /*OpIdx*/0, /*SubRegIdx*/GIMT_Encode2(3), // value
      GIR_ConstrainOperandRC, /*InsnID*/1, /*Op*/0, GIMT_Encode2(AMDGPU::VGPR_32RegClassID),
      GIR_ConstrainOperandRC, /*InsnID*/1, /*Op*/1, GIMT_Encode2(AMDGPU::VReg_64RegClassID),
      GIR_BuildMI, /*InsnID*/0, /*Opcode*/GIMT_Encode2(AMDGPU::DS_WRITE2_B32),
      GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/0, // ptr
      GIR_AddSimpleTempRegister, /*InsnID*/0, /*TempRegID*/0,
      GIR_AddSimpleTempRegister, /*InsnID*/0, /*TempRegID*/1,
      GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/1, // offset0
      GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/2, // offset1
      GIR_AddImm8, /*InsnID*/0, /*Imm*/0,
      GIR_MergeMemOperands, /*InsnID*/0, /*NumInsns*/1, /*MergeInsnID's*/0,
      GIR_ConstrainSelectedInstOperands, /*InsnID*/0,
      GIR_EraseFromParent, /*InsnID*/0,
      // GIR_Coverage, 6672,
      GIR_Done,
    // Label 2099: @137776
    GIM_Try, /*On fail goto*//*Label 2100*/ GIMT_Encode4(137900), // Rule ID 6680 //
      GIM_CheckFeatures, GIMT_Encode2(GIFBS_LDSRequiresM0Init_isGFX7Plus),
      GIM_CheckMemorySizeEqualToLLT, /*MI*/0, /*MMO*/0, /*OpIdx*/0,
      GIM_CheckMemoryAddressSpace, /*MI*/0, /*MMO*/0, /*NumAddrSpace*/1, /*AddrSpace*/3,
      GIM_CheckAtomicOrdering, /*MI*/0, /*Order*/(uint8_t)AtomicOrdering::NotAtomic,
      GIM_CheckPointerToAny, /*MI*/0, /*Op*/1, /*SizeInBits*/0,
      GIM_CheckComplexPattern, /*MI*/0, /*Op*/1, /*Renderer*/GIMT_Encode2(0), GIMT_Encode2(GICP_gi_ds_64bit_4byte_aligned),
      // (AMDGPUst_glue f64:{ *:[f64] }:$value, (DS64Bit4ByteAligned:{ *:[iPTR] } i32:{ *:[i32] }:$ptr, i8:{ *:[i8] }:$offset0, i8:{ *:[i8] }:$offset1))<<P:Predicate_unindexedstore_glue>><<P:Predicate_store_glue>><<P:Predicate_store_local_m0>>  =>  (DS_WRITE2_B32 ?:{ *:[i32] }:$ptr, (EXTRACT_SUBREG:{ *:[i32] } VReg_64:{ *:[f64] }:$value, sub0:{ *:[i32] }), (EXTRACT_SUBREG:{ *:[i32] } VReg_64:{ *:[f64] }:$value, sub1:{ *:[i32] }), ?:{ *:[i8] }:$offset0, ?:{ *:[i8] }:$offset1, 0:{ *:[i1] })
      GIR_MakeTempReg, /*TempRegID*/0, /*TypeID*/GILLT_s32,
      GIR_MakeTempReg, /*TempRegID*/1, /*TypeID*/GILLT_s32,
      GIR_BuildMI, /*InsnID*/2, /*Opcode*/GIMT_Encode2(TargetOpcode::COPY),
      GIR_AddTempRegister, /*InsnID*/2, /*TempRegID*/1, /*TempRegFlags*/GIMT_Encode2(RegState::Define),
      GIR_CopySubReg, /*NewInsnID*/2, /*OldInsnID*/0, /*OpIdx*/0, /*SubRegIdx*/GIMT_Encode2(11), // value
      GIR_ConstrainOperandRC, /*InsnID*/2, /*Op*/0, GIMT_Encode2(AMDGPU::VGPR_32RegClassID),
      GIR_ConstrainOperandRC, /*InsnID*/2, /*Op*/1, GIMT_Encode2(AMDGPU::VReg_64RegClassID),
      GIR_BuildMI, /*InsnID*/1, /*Opcode*/GIMT_Encode2(TargetOpcode::COPY),
      GIR_AddTempRegister, /*InsnID*/1, /*TempRegID*/0, /*TempRegFlags*/GIMT_Encode2(RegState::Define),
      GIR_CopySubReg, /*NewInsnID*/1, /*OldInsnID*/0, /*OpIdx*/0, /*SubRegIdx*/GIMT_Encode2(3), // value
      GIR_ConstrainOperandRC, /*InsnID*/1, /*Op*/0, GIMT_Encode2(AMDGPU::VGPR_32RegClassID),
      GIR_ConstrainOperandRC, /*InsnID*/1, /*Op*/1, GIMT_Encode2(AMDGPU::VReg_64RegClassID),
      GIR_BuildMI, /*InsnID*/0, /*Opcode*/GIMT_Encode2(AMDGPU::DS_WRITE2_B32),
      GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/0, // ptr
      GIR_AddSimpleTempRegister, /*InsnID*/0, /*TempRegID*/0,
      GIR_AddSimpleTempRegister, /*InsnID*/0, /*TempRegID*/1,
      GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/1, // offset0
      GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/2, // offset1
      GIR_AddImm8, /*InsnID*/0, /*Imm*/0,
      GIR_MergeMemOperands, /*InsnID*/0, /*NumInsns*/1, /*MergeInsnID's*/0,
      GIR_ConstrainSelectedInstOperands, /*InsnID*/0,
      GIR_EraseFromParent, /*InsnID*/0,
      // GIR_Coverage, 6680,
      GIR_Done,
    // Label 2100: @137900
    GIM_Try, /*On fail goto*//*Label 2101*/ GIMT_Encode4(137965), // Rule ID 3837 //
      GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasUnrestrictedSOffset),
      GIM_CheckMemoryAddressSpace, /*MI*/0, /*MMO*/0, /*NumAddrSpace*/1, /*AddrSpace*/1,
      GIM_CheckAtomicOrdering, /*MI*/0, /*Order*/(uint8_t)AtomicOrdering::NotAtomic,
      GIM_CheckPointerToAny, /*MI*/0, /*Op*/1, /*SizeInBits*/0,
      GIM_CheckComplexPattern, /*MI*/0, /*Op*/1, /*Renderer*/GIMT_Encode2(0), GIMT_Encode2(GICP_gi_mubuf_offset),
      // (st i64:{ *:[i64] }:$vdata, (MUBUFOffset:{ *:[iPTR] } v4i32:{ *:[v4i32] }:$srsrc, i32:{ *:[i32] }:$soffset, i32:{ *:[i32] }:$offset))<<P:Predicate_unindexedstore>><<P:Predicate_store_global>>  =>  (BUFFER_STORE_DWORDX2_OFFSET i64:{ *:[i64] }:$vdata, v4i32:{ *:[v4i32] }:$srsrc, i32:{ *:[i32] }:$soffset, i32:{ *:[i32] }:$offset)
      GIR_BuildMI, /*InsnID*/0, /*Opcode*/GIMT_Encode2(AMDGPU::BUFFER_STORE_DWORDX2_OFFSET),
      GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/0, // vdata
      GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/0, // srsrc
      GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/1, // soffset
      GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/2, // offset
      GIR_AddImm8, /*InsnID*/0, /*Imm*/0,
      GIR_AddImm8, /*InsnID*/0, /*Imm*/0,
      GIR_MergeMemOperands, /*InsnID*/0, /*NumInsns*/1, /*MergeInsnID's*/0,
      GIR_ConstrainSelectedInstOperands, /*InsnID*/0,
      GIR_EraseFromParent, /*InsnID*/0,
      // GIR_Coverage, 3837,
      GIR_Done,
    // Label 2101: @137965
    GIM_Try, /*On fail goto*//*Label 2102*/ GIMT_Encode4(138027), // Rule ID 3839 //
      GIM_CheckMemoryAddressSpace, /*MI*/0, /*MMO*/0, /*NumAddrSpace*/1, /*AddrSpace*/1,
      GIM_CheckAtomicOrdering, /*MI*/0, /*Order*/(uint8_t)AtomicOrdering::NotAtomic,
      GIM_CheckPointerToAny, /*MI*/0, /*Op*/1, /*SizeInBits*/0,
      GIM_CheckComplexPattern, /*MI*/0, /*Op*/1, /*Renderer*/GIMT_Encode2(0), GIMT_Encode2(GICP_gi_mubuf_offset),
      // (st i64:{ *:[i64] }:$vdata, (MUBUFOffset:{ *:[iPTR] } v4i32:{ *:[v4i32] }:$srsrc, i32:{ *:[i32] }:$soffset, i32:{ *:[i32] }:$offset))<<P:Predicate_unindexedstore>><<P:Predicate_store_global>>  =>  (BUFFER_STORE_DWORDX2_VBUFFER_OFFSET i64:{ *:[i64] }:$vdata, v4i32:{ *:[v4i32] }:$srsrc, i32:{ *:[i32] }:$soffset, i32:{ *:[i32] }:$offset)
      GIR_BuildMI, /*InsnID*/0, /*Opcode*/GIMT_Encode2(AMDGPU::BUFFER_STORE_DWORDX2_VBUFFER_OFFSET),
      GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/0, // vdata
      GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/0, // srsrc
      GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/1, // soffset
      GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/2, // offset
      GIR_AddImm8, /*InsnID*/0, /*Imm*/0,
      GIR_AddImm8, /*InsnID*/0, /*Imm*/0,
      GIR_MergeMemOperands, /*InsnID*/0, /*NumInsns*/1, /*MergeInsnID's*/0,
      GIR_ConstrainSelectedInstOperands, /*InsnID*/0,
      GIR_EraseFromParent, /*InsnID*/0,
      // GIR_Coverage, 3839,
      GIR_Done,
    // Label 2102: @138027
    GIM_Try, /*On fail goto*//*Label 2103*/ GIMT_Encode4(138092), // Rule ID 3841 //
      GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasUnrestrictedSOffset),
      GIM_CheckMemoryAddressSpace, /*MI*/0, /*MMO*/0, /*NumAddrSpace*/1, /*AddrSpace*/1,
      GIM_CheckAtomicOrdering, /*MI*/0, /*Order*/(uint8_t)AtomicOrdering::NotAtomic,
      GIM_CheckPointerToAny, /*MI*/0, /*Op*/1, /*SizeInBits*/0,
      GIM_CheckComplexPattern, /*MI*/0, /*Op*/1, /*Renderer*/GIMT_Encode2(0), GIMT_Encode2(GICP_gi_mubuf_offset),
      // (st f64:{ *:[f64] }:$vdata, (MUBUFOffset:{ *:[iPTR] } v4i32:{ *:[v4i32] }:$srsrc, i32:{ *:[i32] }:$soffset, i32:{ *:[i32] }:$offset))<<P:Predicate_unindexedstore>><<P:Predicate_store_global>>  =>  (BUFFER_STORE_DWORDX2_OFFSET f64:{ *:[f64] }:$vdata, v4i32:{ *:[v4i32] }:$srsrc, i32:{ *:[i32] }:$soffset, i32:{ *:[i32] }:$offset)
      GIR_BuildMI, /*InsnID*/0, /*Opcode*/GIMT_Encode2(AMDGPU::BUFFER_STORE_DWORDX2_OFFSET),
      GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/0, // vdata
      GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/0, // srsrc
      GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/1, // soffset
      GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/2, // offset
      GIR_AddImm8, /*InsnID*/0, /*Imm*/0,
      GIR_AddImm8, /*InsnID*/0, /*Imm*/0,
      GIR_MergeMemOperands, /*InsnID*/0, /*NumInsns*/1, /*MergeInsnID's*/0,
      GIR_ConstrainSelectedInstOperands, /*InsnID*/0,
      GIR_EraseFromParent, /*InsnID*/0,
      // GIR_Coverage, 3841,
      GIR_Done,
    // Label 2103: @138092
    GIM_Try, /*On fail goto*//*Label 2104*/ GIMT_Encode4(138154), // Rule ID 3843 //
      GIM_CheckMemoryAddressSpace, /*MI*/0, /*MMO*/0, /*NumAddrSpace*/1, /*AddrSpace*/1,
      GIM_CheckAtomicOrdering, /*MI*/0, /*Order*/(uint8_t)AtomicOrdering::NotAtomic,
      GIM_CheckPointerToAny, /*MI*/0, /*Op*/1, /*SizeInBits*/0,
      GIM_CheckComplexPattern, /*MI*/0, /*Op*/1, /*Renderer*/GIMT_Encode2(0), GIMT_Encode2(GICP_gi_mubuf_offset),
      // (st f64:{ *:[f64] }:$vdata, (MUBUFOffset:{ *:[iPTR] } v4i32:{ *:[v4i32] }:$srsrc, i32:{ *:[i32] }:$soffset, i32:{ *:[i32] }:$offset))<<P:Predicate_unindexedstore>><<P:Predicate_store_global>>  =>  (BUFFER_STORE_DWORDX2_VBUFFER_OFFSET f64:{ *:[f64] }:$vdata, v4i32:{ *:[v4i32] }:$srsrc, i32:{ *:[i32] }:$soffset, i32:{ *:[i32] }:$offset)
      GIR_BuildMI, /*InsnID*/0, /*Opcode*/GIMT_Encode2(AMDGPU::BUFFER_STORE_DWORDX2_VBUFFER_OFFSET),
      GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/0, // vdata
      GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/0, // srsrc
      GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/1, // soffset
      GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/2, // offset
      GIR_AddImm8, /*InsnID*/0, /*Imm*/0,
      GIR_AddImm8, /*InsnID*/0, /*Imm*/0,
      GIR_MergeMemOperands, /*InsnID*/0, /*NumInsns*/1, /*MergeInsnID's*/0,
      GIR_ConstrainSelectedInstOperands, /*InsnID*/0,
      GIR_EraseFromParent, /*InsnID*/0,
      // GIR_Coverage, 3843,
      GIR_Done,
    // Label 2104: @138154
    GIM_Try, /*On fail goto*//*Label 2105*/ GIMT_Encode4(138274), // Rule ID 6674 //
      GIM_CheckFeatures, GIMT_Encode2(GIFBS_NotLDSRequiresM0Init),
      GIM_CheckMemoryAddressSpace, /*MI*/0, /*MMO*/0, /*NumAddrSpace*/1, /*AddrSpace*/3,
      GIM_CheckAtomicOrdering, /*MI*/0, /*Order*/(uint8_t)AtomicOrdering::NotAtomic,
      GIM_CheckPointerToAny, /*MI*/0, /*Op*/1, /*SizeInBits*/0,
      GIM_CheckComplexPattern, /*MI*/0, /*Op*/1, /*Renderer*/GIMT_Encode2(0), GIMT_Encode2(GICP_gi_ds_64bit_4byte_aligned),
      // (st i64:{ *:[i64] }:$value, (DS64Bit4ByteAligned:{ *:[iPTR] } i32:{ *:[i32] }:$ptr, i8:{ *:[i8] }:$offset0, i8:{ *:[i8] }:$offset1))<<P:Predicate_unindexedstore>><<P:Predicate_store_local>>  =>  (DS_WRITE2_B32_gfx9 ?:{ *:[i32] }:$ptr, (EXTRACT_SUBREG:{ *:[i32] } VReg_64:{ *:[i64] }:$value, sub0:{ *:[i32] }), (EXTRACT_SUBREG:{ *:[i32] } VReg_64:{ *:[i64] }:$value, sub1:{ *:[i32] }), ?:{ *:[i8] }:$offset0, ?:{ *:[i8] }:$offset1, 0:{ *:[i1] })
      GIR_MakeTempReg, /*TempRegID*/0, /*TypeID*/GILLT_s32,
      GIR_MakeTempReg, /*TempRegID*/1, /*TypeID*/GILLT_s32,
      GIR_BuildMI, /*InsnID*/2, /*Opcode*/GIMT_Encode2(TargetOpcode::COPY),
      GIR_AddTempRegister, /*InsnID*/2, /*TempRegID*/1, /*TempRegFlags*/GIMT_Encode2(RegState::Define),
      GIR_CopySubReg, /*NewInsnID*/2, /*OldInsnID*/0, /*OpIdx*/0, /*SubRegIdx*/GIMT_Encode2(11), // value
      GIR_ConstrainOperandRC, /*InsnID*/2, /*Op*/0, GIMT_Encode2(AMDGPU::VGPR_32RegClassID),
      GIR_ConstrainOperandRC, /*InsnID*/2, /*Op*/1, GIMT_Encode2(AMDGPU::VReg_64RegClassID),
      GIR_BuildMI, /*InsnID*/1, /*Opcode*/GIMT_Encode2(TargetOpcode::COPY),
      GIR_AddTempRegister, /*InsnID*/1, /*TempRegID*/0, /*TempRegFlags*/GIMT_Encode2(RegState::Define),
      GIR_CopySubReg, /*NewInsnID*/1, /*OldInsnID*/0, /*OpIdx*/0, /*SubRegIdx*/GIMT_Encode2(3), // value
      GIR_ConstrainOperandRC, /*InsnID*/1, /*Op*/0, GIMT_Encode2(AMDGPU::VGPR_32RegClassID),
      GIR_ConstrainOperandRC, /*InsnID*/1, /*Op*/1, GIMT_Encode2(AMDGPU::VReg_64RegClassID),
      GIR_BuildMI, /*InsnID*/0, /*Opcode*/GIMT_Encode2(AMDGPU::DS_WRITE2_B32_gfx9),
      GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/0, // ptr
      GIR_AddSimpleTempRegister, /*InsnID*/0, /*TempRegID*/0,
      GIR_AddSimpleTempRegister, /*InsnID*/0, /*TempRegID*/1,
      GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/1, // offset0
      GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/2, // offset1
      GIR_AddImm8, /*InsnID*/0, /*Imm*/0,
      GIR_MergeMemOperands, /*InsnID*/0, /*NumInsns*/1, /*MergeInsnID's*/0,
      GIR_ConstrainSelectedInstOperands, /*InsnID*/0,
      GIR_EraseFromParent, /*InsnID*/0,
      // GIR_Coverage, 6674,
      GIR_Done,
    // Label 2105: @138274
    GIM_Try, /*On fail goto*//*Label 2106*/ GIMT_Encode4(138394), // Rule ID 6682 //
      GIM_CheckFeatures, GIMT_Encode2(GIFBS_NotLDSRequiresM0Init),
      GIM_CheckMemoryAddressSpace, /*MI*/0, /*MMO*/0, /*NumAddrSpace*/1, /*AddrSpace*/3,
      GIM_CheckAtomicOrdering, /*MI*/0, /*Order*/(uint8_t)AtomicOrdering::NotAtomic,
      GIM_CheckPointerToAny, /*MI*/0, /*Op*/1, /*SizeInBits*/0,
      GIM_CheckComplexPattern, /*MI*/0, /*Op*/1, /*Renderer*/GIMT_Encode2(0), GIMT_Encode2(GICP_gi_ds_64bit_4byte_aligned),
      // (st f64:{ *:[f64] }:$value, (DS64Bit4ByteAligned:{ *:[iPTR] } i32:{ *:[i32] }:$ptr, i8:{ *:[i8] }:$offset0, i8:{ *:[i8] }:$offset1))<<P:Predicate_unindexedstore>><<P:Predicate_store_local>>  =>  (DS_WRITE2_B32_gfx9 ?:{ *:[i32] }:$ptr, (EXTRACT_SUBREG:{ *:[i32] } VReg_64:{ *:[f64] }:$value, sub0:{ *:[i32] }), (EXTRACT_SUBREG:{ *:[i32] } VReg_64:{ *:[f64] }:$value, sub1:{ *:[i32] }), ?:{ *:[i8] }:$offset0, ?:{ *:[i8] }:$offset1, 0:{ *:[i1] })
      GIR_MakeTempReg, /*TempRegID*/0, /*TypeID*/GILLT_s32,
      GIR_MakeTempReg, /*TempRegID*/1, /*TypeID*/GILLT_s32,
      GIR_BuildMI, /*InsnID*/2, /*Opcode*/GIMT_Encode2(TargetOpcode::COPY),
      GIR_AddTempRegister, /*InsnID*/2, /*TempRegID*/1, /*TempRegFlags*/GIMT_Encode2(RegState::Define),
      GIR_CopySubReg, /*NewInsnID*/2, /*OldInsnID*/0, /*OpIdx*/0, /*SubRegIdx*/GIMT_Encode2(11), // value
      GIR_ConstrainOperandRC, /*InsnID*/2, /*Op*/0, GIMT_Encode2(AMDGPU::VGPR_32RegClassID),
      GIR_ConstrainOperandRC, /*InsnID*/2, /*Op*/1, GIMT_Encode2(AMDGPU::VReg_64RegClassID),
      GIR_BuildMI, /*InsnID*/1, /*Opcode*/GIMT_Encode2(TargetOpcode::COPY),
      GIR_AddTempRegister, /*InsnID*/1, /*TempRegID*/0, /*TempRegFlags*/GIMT_Encode2(RegState::Define),
      GIR_CopySubReg, /*NewInsnID*/1, /*OldInsnID*/0, /*OpIdx*/0, /*SubRegIdx*/GIMT_Encode2(3), // value
      GIR_ConstrainOperandRC, /*InsnID*/1, /*Op*/0, GIMT_Encode2(AMDGPU::VGPR_32RegClassID),
      GIR_ConstrainOperandRC, /*InsnID*/1, /*Op*/1, GIMT_Encode2(AMDGPU::VReg_64RegClassID),
      GIR_BuildMI, /*InsnID*/0, /*Opcode*/GIMT_Encode2(AMDGPU::DS_WRITE2_B32_gfx9),
      GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/0, // ptr
      GIR_AddSimpleTempRegister, /*InsnID*/0, /*TempRegID*/0,
      GIR_AddSimpleTempRegister, /*InsnID*/0, /*TempRegID*/1,
      GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/1, // offset0
      GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/2, // offset1
      GIR_AddImm8, /*InsnID*/0, /*Imm*/0,
      GIR_MergeMemOperands, /*InsnID*/0, /*NumInsns*/1, /*MergeInsnID's*/0,
      GIR_ConstrainSelectedInstOperands, /*InsnID*/0,
      GIR_EraseFromParent, /*InsnID*/0,
      // GIR_Coverage, 6682,
      GIR_Done,
    // Label 2106: @138394
    GIM_Try, /*On fail goto*//*Label 2107*/ GIMT_Encode4(138458), // Rule ID 6667 //
      GIM_CheckFeatures, GIMT_Encode2(GIFBS_LDSRequiresM0Init),
      GIM_CheckMemorySizeEqualTo, /*MI*/0, /*MMO*/0, /*Size*/GIMT_Encode4(8),
      GIM_CheckMemoryAddressSpace, /*MI*/0, /*MMO*/0, /*NumAddrSpace*/1, /*AddrSpace*/3,
      GIM_CheckAtomicOrderingOrStrongerThan, /*MI*/0, /*Order*/(uint8_t)AtomicOrdering::Unordered,
      GIM_CheckPointerToAny, /*MI*/0, /*Op*/1, /*SizeInBits*/0,
      GIM_CheckComplexPattern, /*MI*/0, /*Op*/1, /*Renderer*/GIMT_Encode2(0), GIMT_Encode2(GICP_gi_ds_1addr_1offset),
      // (AMDGPUatomic_st_glue i64:{ *:[i64] }:$value, (DS1Addr1Offset:{ *:[iPTR] } i32:{ *:[i32] }:$ptr, i32:{ *:[i32] }:$offset))<<P:Predicate_atomic_store_64_glue>><<P:Predicate_atomic_store_64_local_m0>>  =>  (DS_WRITE_B64 ?:{ *:[i32] }:$ptr, anonymous_15036:{ *:[i64] }:$value, offset:{ *:[i32] }:$offset, 0:{ *:[i1] })
      GIR_BuildMI, /*InsnID*/0, /*Opcode*/GIMT_Encode2(AMDGPU::DS_WRITE_B64),
      GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/0, // ptr
      GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/0, // value
      GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/1, // offset
      GIR_AddImm8, /*InsnID*/0, /*Imm*/0,
      GIR_MergeMemOperands, /*InsnID*/0, /*NumInsns*/1, /*MergeInsnID's*/0,
      GIR_ConstrainSelectedInstOperands, /*InsnID*/0,
      GIR_EraseFromParent, /*InsnID*/0,
      // GIR_Coverage, 6667,
      GIR_Done,
    // Label 2107: @138458
    GIM_Try, /*On fail goto*//*Label 2108*/ GIMT_Encode4(138522), // Rule ID 6668 //
      GIM_CheckFeatures, GIMT_Encode2(GIFBS_NotLDSRequiresM0Init),
      GIM_CheckMemorySizeEqualTo, /*MI*/0, /*MMO*/0, /*Size*/GIMT_Encode4(8),
      GIM_CheckMemoryAddressSpace, /*MI*/0, /*MMO*/0, /*NumAddrSpace*/1, /*AddrSpace*/3,
      GIM_CheckAtomicOrderingOrStrongerThan, /*MI*/0, /*Order*/(uint8_t)AtomicOrdering::Unordered,
      GIM_CheckPointerToAny, /*MI*/0, /*Op*/1, /*SizeInBits*/0,
      GIM_CheckComplexPattern, /*MI*/0, /*Op*/1, /*Renderer*/GIMT_Encode2(0), GIMT_Encode2(GICP_gi_ds_1addr_1offset),
      // (atomic_store i64:{ *:[i64] }:$value, (DS1Addr1Offset:{ *:[iPTR] } i32:{ *:[i32] }:$ptr, i32:{ *:[i32] }:$offset))<<P:Predicate_atomic_store_64>><<P:Predicate_atomic_store_64_local>>  =>  (DS_WRITE_B64_gfx9 ?:{ *:[i32] }:$ptr, anonymous_15036:{ *:[i64] }:$value, offset:{ *:[i32] }:$offset, 0:{ *:[i1] })
      GIR_BuildMI, /*InsnID*/0, /*Opcode*/GIMT_Encode2(AMDGPU::DS_WRITE_B64_gfx9),
      GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/0, // ptr
      GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/0, // value
      GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/1, // offset
      GIR_AddImm8, /*InsnID*/0, /*Imm*/0,
      GIR_MergeMemOperands, /*InsnID*/0, /*NumInsns*/1, /*MergeInsnID's*/0,
      GIR_ConstrainSelectedInstOperands, /*InsnID*/0,
      GIR_EraseFromParent, /*InsnID*/0,
      // GIR_Coverage, 6668,
      GIR_Done,
    // Label 2108: @138522
    GIM_Try, /*On fail goto*//*Label 2109*/ GIMT_Encode4(138591), // Rule ID 3149 //
      GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasFlatGlobalInsts),
      GIM_CheckMemorySizeEqualTo, /*MI*/0, /*MMO*/0, /*Size*/GIMT_Encode4(8),
      GIM_CheckMemoryAddressSpace, /*MI*/0, /*MMO*/0, /*NumAddrSpace*/1, /*AddrSpace*/1,
      GIM_CheckAtomicOrderingOrStrongerThan, /*MI*/0, /*Order*/(uint8_t)AtomicOrdering::Unordered,
      GIM_CheckPointerToAny, /*MI*/0, /*Op*/1, /*SizeInBits*/0,
      GIM_CheckComplexPattern, /*MI*/0, /*Op*/1, /*Renderer*/GIMT_Encode2(0), GIMT_Encode2(GICP_gi_global_saddr),
      // (atomic_store i64:{ *:[i64] }:$data, (GlobalSAddr:{ *:[iPTR] } SReg_64:{ *:[i64] }:$saddr, VGPR_32:{ *:[i32] }:$voffset, i32:{ *:[i32] }:$offset))<<P:Predicate_atomic_store_64>><<P:Predicate_atomic_store_64_global>>  =>  (GLOBAL_STORE_DWORDX2_SADDR ?:{ *:[i32] }:$voffset, anonymous_15036:{ *:[i64] }:$data, ?:{ *:[i64] }:$saddr, ?:{ *:[i32] }:$offset)
      GIR_BuildMI, /*InsnID*/0, /*Opcode*/GIMT_Encode2(AMDGPU::GLOBAL_STORE_DWORDX2_SADDR),
      GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/1, // voffset
      GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/0, // data
      GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/0, // saddr
      GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/2, // offset
      GIR_AddImm8, /*InsnID*/0, /*Imm*/0,
      GIR_MergeMemOperands, /*InsnID*/0, /*NumInsns*/1, /*MergeInsnID's*/0,
      GIR_ConstrainSelectedInstOperands, /*InsnID*/0,
      GIR_EraseFromParent, /*InsnID*/0,
      // GIR_Coverage, 3149,
      GIR_Done,
    // Label 2109: @138591
    GIM_Try, /*On fail goto*//*Label 2110*/ GIMT_Encode4(138653), // Rule ID 3031 //
      GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasFlatGlobalInsts),
      GIM_CheckMemoryAddressSpace, /*MI*/0, /*MMO*/0, /*NumAddrSpace*/1, /*AddrSpace*/1,
      GIM_CheckAtomicOrdering, /*MI*/0, /*Order*/(uint8_t)AtomicOrdering::NotAtomic,
      GIM_CheckPointerToAny, /*MI*/0, /*Op*/1, /*SizeInBits*/0,
      GIM_CheckComplexPattern, /*MI*/0, /*Op*/1, /*Renderer*/GIMT_Encode2(0), GIMT_Encode2(GICP_gi_global_saddr),
      // (st i64:{ *:[i64] }:$data, (GlobalSAddr:{ *:[iPTR] } SReg_64:{ *:[i64] }:$saddr, VGPR_32:{ *:[i32] }:$voffset, i32:{ *:[i32] }:$offset))<<P:Predicate_unindexedstore>><<P:Predicate_store_global>>  =>  (GLOBAL_STORE_DWORDX2_SADDR ?:{ *:[i32] }:$voffset, anonymous_15036:{ *:[i64] }:$data, ?:{ *:[i64] }:$saddr, ?:{ *:[i32] }:$offset)
      GIR_BuildMI, /*InsnID*/0, /*Opcode*/GIMT_Encode2(AMDGPU::GLOBAL_STORE_DWORDX2_SADDR),
      GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/1, // voffset
      GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/0, // data
      GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/0, // saddr
      GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/2, // offset
      GIR_AddImm8, /*InsnID*/0, /*Imm*/0,
      GIR_MergeMemOperands, /*InsnID*/0, /*NumInsns*/1, /*MergeInsnID's*/0,
      GIR_ConstrainSelectedInstOperands, /*InsnID*/0,
      GIR_EraseFromParent, /*InsnID*/0,
      // GIR_Coverage, 3031,
      GIR_Done,
    // Label 2110: @138653
    GIM_Try, /*On fail goto*//*Label 2111*/ GIMT_Encode4(138715), // Rule ID 3035 //
      GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasFlatGlobalInsts),
      GIM_CheckMemoryAddressSpace, /*MI*/0, /*MMO*/0, /*NumAddrSpace*/1, /*AddrSpace*/1,
      GIM_CheckAtomicOrdering, /*MI*/0, /*Order*/(uint8_t)AtomicOrdering::NotAtomic,
      GIM_CheckPointerToAny, /*MI*/0, /*Op*/1, /*SizeInBits*/0,
      GIM_CheckComplexPattern, /*MI*/0, /*Op*/1, /*Renderer*/GIMT_Encode2(0), GIMT_Encode2(GICP_gi_global_saddr),
      // (st f64:{ *:[f64] }:$data, (GlobalSAddr:{ *:[iPTR] } SReg_64:{ *:[i64] }:$saddr, VGPR_32:{ *:[i32] }:$voffset, i32:{ *:[i32] }:$offset))<<P:Predicate_unindexedstore>><<P:Predicate_store_global>>  =>  (GLOBAL_STORE_DWORDX2_SADDR ?:{ *:[i32] }:$voffset, anonymous_15036:{ *:[f64] }:$data, ?:{ *:[i64] }:$saddr, ?:{ *:[i32] }:$offset)
      GIR_BuildMI, /*InsnID*/0, /*Opcode*/GIMT_Encode2(AMDGPU::GLOBAL_STORE_DWORDX2_SADDR),
      GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/1, // voffset
      GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/0, // data
      GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/0, // saddr
      GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/2, // offset
      GIR_AddImm8, /*InsnID*/0, /*Imm*/0,
      GIR_MergeMemOperands, /*InsnID*/0, /*NumInsns*/1, /*MergeInsnID's*/0,
      GIR_ConstrainSelectedInstOperands, /*InsnID*/0,
      GIR_EraseFromParent, /*InsnID*/0,
      // GIR_Coverage, 3035,
      GIR_Done,
    // Label 2111: @138715
    GIM_Try, /*On fail goto*//*Label 2112*/ GIMT_Encode4(138779), // Rule ID 3148 //
      GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasFlatGlobalInsts),
      GIM_CheckMemorySizeEqualTo, /*MI*/0, /*MMO*/0, /*Size*/GIMT_Encode4(8),
      GIM_CheckMemoryAddressSpace, /*MI*/0, /*MMO*/0, /*NumAddrSpace*/1, /*AddrSpace*/1,
      GIM_CheckAtomicOrderingOrStrongerThan, /*MI*/0, /*Order*/(uint8_t)AtomicOrdering::Unordered,
      GIM_CheckPointerToAny, /*MI*/0, /*Op*/1, /*SizeInBits*/0,
      GIM_CheckComplexPattern, /*MI*/0, /*Op*/1, /*Renderer*/GIMT_Encode2(0), GIMT_Encode2(GICP_gi_global_offset),
      // (atomic_store i64:{ *:[i64] }:$data, (GlobalOffset:{ *:[iPTR] } i64:{ *:[i64] }:$vaddr, i32:{ *:[i32] }:$offset))<<P:Predicate_atomic_store_64>><<P:Predicate_atomic_store_64_global>>  =>  (GLOBAL_STORE_DWORDX2 ?:{ *:[i64] }:$vaddr, anonymous_15036:{ *:[i64] }:$data, ?:{ *:[i32] }:$offset)
      GIR_BuildMI, /*InsnID*/0, /*Opcode*/GIMT_Encode2(AMDGPU::GLOBAL_STORE_DWORDX2),
      GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/0, // vaddr
      GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/0, // data
      GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/1, // offset
      GIR_AddImm8, /*InsnID*/0, /*Imm*/0,
      GIR_MergeMemOperands, /*InsnID*/0, /*NumInsns*/1, /*MergeInsnID's*/0,
      GIR_ConstrainSelectedInstOperands, /*InsnID*/0,
      GIR_EraseFromParent, /*InsnID*/0,
      // GIR_Coverage, 3148,
      GIR_Done,
    // Label 2112: @138779
    GIM_Try, /*On fail goto*//*Label 2113*/ GIMT_Encode4(138836), // Rule ID 3030 //
      GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasFlatGlobalInsts),
      GIM_CheckMemoryAddressSpace, /*MI*/0, /*MMO*/0, /*NumAddrSpace*/1, /*AddrSpace*/1,
      GIM_CheckAtomicOrdering, /*MI*/0, /*Order*/(uint8_t)AtomicOrdering::NotAtomic,
      GIM_CheckPointerToAny, /*MI*/0, /*Op*/1, /*SizeInBits*/0,
      GIM_CheckComplexPattern, /*MI*/0, /*Op*/1, /*Renderer*/GIMT_Encode2(0), GIMT_Encode2(GICP_gi_global_offset),
      // (st i64:{ *:[i64] }:$data, (GlobalOffset:{ *:[iPTR] } i64:{ *:[i64] }:$vaddr, i32:{ *:[i32] }:$offset))<<P:Predicate_unindexedstore>><<P:Predicate_store_global>>  =>  (GLOBAL_STORE_DWORDX2 ?:{ *:[i64] }:$vaddr, anonymous_15036:{ *:[i64] }:$data, ?:{ *:[i32] }:$offset)
      GIR_BuildMI, /*InsnID*/0, /*Opcode*/GIMT_Encode2(AMDGPU::GLOBAL_STORE_DWORDX2),
      GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/0, // vaddr
      GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/0, // data
      GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/1, // offset
      GIR_AddImm8, /*InsnID*/0, /*Imm*/0,
      GIR_MergeMemOperands, /*InsnID*/0, /*NumInsns*/1, /*MergeInsnID's*/0,
      GIR_ConstrainSelectedInstOperands, /*InsnID*/0,
      GIR_EraseFromParent, /*InsnID*/0,
      // GIR_Coverage, 3030,
      GIR_Done,
    // Label 2113: @138836
    GIM_Try, /*On fail goto*//*Label 2114*/ GIMT_Encode4(138893), // Rule ID 3034 //
      GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasFlatGlobalInsts),
      GIM_CheckMemoryAddressSpace, /*MI*/0, /*MMO*/0, /*NumAddrSpace*/1, /*AddrSpace*/1,
      GIM_CheckAtomicOrdering, /*MI*/0, /*Order*/(uint8_t)AtomicOrdering::NotAtomic,
      GIM_CheckPointerToAny, /*MI*/0, /*Op*/1, /*SizeInBits*/0,
      GIM_CheckComplexPattern, /*MI*/0, /*Op*/1, /*Renderer*/GIMT_Encode2(0), GIMT_Encode2(GICP_gi_global_offset),
      // (st f64:{ *:[f64] }:$data, (GlobalOffset:{ *:[iPTR] } i64:{ *:[i64] }:$vaddr, i32:{ *:[i32] }:$offset))<<P:Predicate_unindexedstore>><<P:Predicate_store_global>>  =>  (GLOBAL_STORE_DWORDX2 ?:{ *:[i64] }:$vaddr, anonymous_15036:{ *:[f64] }:$data, ?:{ *:[i32] }:$offset)
      GIR_BuildMI, /*InsnID*/0, /*Opcode*/GIMT_Encode2(AMDGPU::GLOBAL_STORE_DWORDX2),
      GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/0, // vaddr
      GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/0, // data
      GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/1, // offset
      GIR_AddImm8, /*InsnID*/0, /*Imm*/0,
      GIR_MergeMemOperands, /*InsnID*/0, /*NumInsns*/1, /*MergeInsnID's*/0,
      GIR_ConstrainSelectedInstOperands, /*InsnID*/0,
      GIR_EraseFromParent, /*InsnID*/0,
      // GIR_Coverage, 3034,
      GIR_Done,
    // Label 2114: @138893
    GIM_Try, /*On fail goto*//*Label 2115*/ GIMT_Encode4(138958), // Rule ID 2824 //
      GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasFlatAddressSpace),
      GIM_CheckMemorySizeEqualTo, /*MI*/0, /*MMO*/0, /*Size*/GIMT_Encode4(8),
      GIM_CheckMemoryAddressSpace, /*MI*/0, /*MMO*/0, /*NumAddrSpace*/2, /*AddrSpace*/0, /*AddrSpace*/1,
      GIM_CheckAtomicOrderingOrStrongerThan, /*MI*/0, /*Order*/(uint8_t)AtomicOrdering::Unordered,
      GIM_CheckPointerToAny, /*MI*/0, /*Op*/1, /*SizeInBits*/0,
      GIM_CheckComplexPattern, /*MI*/0, /*Op*/1, /*Renderer*/GIMT_Encode2(0), GIMT_Encode2(GICP_gi_flat_offset),
      // (atomic_store i64:{ *:[i64] }:$data, (FlatOffset:{ *:[iPTR] } i64:{ *:[i64] }:$vaddr, i32:{ *:[i32] }:$offset))<<P:Predicate_atomic_store_64>><<P:Predicate_atomic_store_64_flat>>  =>  (FLAT_STORE_DWORDX2 ?:{ *:[i64] }:$vaddr, anonymous_15036:{ *:[i64] }:$data, ?:{ *:[i32] }:$offset)
      GIR_BuildMI, /*InsnID*/0, /*Opcode*/GIMT_Encode2(AMDGPU::FLAT_STORE_DWORDX2),
      GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/0, // vaddr
      GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/0, // data
      GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/1, // offset
      GIR_AddImm8, /*InsnID*/0, /*Imm*/0,
      GIR_MergeMemOperands, /*InsnID*/0, /*NumInsns*/1, /*MergeInsnID's*/0,
      GIR_ConstrainSelectedInstOperands, /*InsnID*/0,
      GIR_EraseFromParent, /*InsnID*/0,
      // GIR_Coverage, 2824,
      GIR_Done,
    // Label 2115: @138958
    GIM_Try, /*On fail goto*//*Label 2116*/ GIMT_Encode4(139016), // Rule ID 2788 //
      GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasFlatAddressSpace),
      GIM_CheckMemoryAddressSpace, /*MI*/0, /*MMO*/0, /*NumAddrSpace*/2, /*AddrSpace*/0, /*AddrSpace*/1,
      GIM_CheckAtomicOrdering, /*MI*/0, /*Order*/(uint8_t)AtomicOrdering::NotAtomic,
      GIM_CheckPointerToAny, /*MI*/0, /*Op*/1, /*SizeInBits*/0,
      GIM_CheckComplexPattern, /*MI*/0, /*Op*/1, /*Renderer*/GIMT_Encode2(0), GIMT_Encode2(GICP_gi_flat_offset),
      // (st i64:{ *:[i64] }:$data, (FlatOffset:{ *:[iPTR] } i64:{ *:[i64] }:$vaddr, i32:{ *:[i32] }:$offset))<<P:Predicate_unindexedstore>><<P:Predicate_store_flat>>  =>  (FLAT_STORE_DWORDX2 ?:{ *:[i64] }:$vaddr, anonymous_15036:{ *:[i64] }:$data, ?:{ *:[i32] }:$offset)
      GIR_BuildMI, /*InsnID*/0, /*Opcode*/GIMT_Encode2(AMDGPU::FLAT_STORE_DWORDX2),
      GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/0, // vaddr
      GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/0, // data
      GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/1, // offset
      GIR_AddImm8, /*InsnID*/0, /*Imm*/0,
      GIR_MergeMemOperands, /*InsnID*/0, /*NumInsns*/1, /*MergeInsnID's*/0,
      GIR_ConstrainSelectedInstOperands, /*InsnID*/0,
      GIR_EraseFromParent, /*InsnID*/0,
      // GIR_Coverage, 2788,
      GIR_Done,
    // Label 2116: @139016
    GIM_Try, /*On fail goto*//*Label 2117*/ GIMT_Encode4(139074), // Rule ID 2790 //
      GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasFlatAddressSpace),
      GIM_CheckMemoryAddressSpace, /*MI*/0, /*MMO*/0, /*NumAddrSpace*/2, /*AddrSpace*/0, /*AddrSpace*/1,
      GIM_CheckAtomicOrdering, /*MI*/0, /*Order*/(uint8_t)AtomicOrdering::NotAtomic,
      GIM_CheckPointerToAny, /*MI*/0, /*Op*/1, /*SizeInBits*/0,
      GIM_CheckComplexPattern, /*MI*/0, /*Op*/1, /*Renderer*/GIMT_Encode2(0), GIMT_Encode2(GICP_gi_flat_offset),
      // (st f64:{ *:[f64] }:$data, (FlatOffset:{ *:[iPTR] } i64:{ *:[i64] }:$vaddr, i32:{ *:[i32] }:$offset))<<P:Predicate_unindexedstore>><<P:Predicate_store_flat>>  =>  (FLAT_STORE_DWORDX2 ?:{ *:[i64] }:$vaddr, anonymous_15036:{ *:[f64] }:$data, ?:{ *:[i32] }:$offset)
      GIR_BuildMI, /*InsnID*/0, /*Opcode*/GIMT_Encode2(AMDGPU::FLAT_STORE_DWORDX2),
      GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/0, // vaddr
      GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/0, // data
      GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/1, // offset
      GIR_AddImm8, /*InsnID*/0, /*Imm*/0,
      GIR_MergeMemOperands, /*InsnID*/0, /*NumInsns*/1, /*MergeInsnID's*/0,
      GIR_ConstrainSelectedInstOperands, /*InsnID*/0,
      GIR_EraseFromParent, /*InsnID*/0,
      // GIR_Coverage, 2790,
      GIR_Done,
    // Label 2117: @139074
    GIM_Reject,
    // Label 1816: @139075
    GIM_Try, /*On fail goto*//*Label 2118*/ GIMT_Encode4(139140), // Rule ID 5522 //
      GIM_CheckFeatures, GIMT_Encode2(GIFBS_DisableFlatScratch_HasUnrestrictedSOffset),
      GIM_CheckMemoryAddressSpace, /*MI*/0, /*MMO*/0, /*NumAddrSpace*/1, /*AddrSpace*/5,
      GIM_CheckAtomicOrdering, /*MI*/0, /*Order*/(uint8_t)AtomicOrdering::NotAtomic,
      GIM_CheckPointerToAny, /*MI*/0, /*Op*/1, /*SizeInBits*/0,
      GIM_CheckComplexPattern, /*MI*/0, /*Op*/1, /*Renderer*/GIMT_Encode2(0), GIMT_Encode2(GICP_gi_mubuf_scratch_offset),
      // (st v2i16:{ *:[v2i16] }:$value, (MUBUFScratchOffset:{ *:[iPTR] } v4i32:{ *:[v4i32] }:$srsrc, i32:{ *:[i32] }:$soffset, i32:{ *:[i32] }:$offset))<<P:Predicate_unindexedstore>><<P:Predicate_store_private>>  =>  (BUFFER_STORE_DWORD_OFFSET VGPR_32:{ *:[v2i16] }:$value, ?:{ *:[v4i32] }:$srsrc, ?:{ *:[i32] }:$soffset, ?:{ *:[i32] }:$offset, 0:{ *:[i32] }, 0:{ *:[i1] })
      GIR_BuildMI, /*InsnID*/0, /*Opcode*/GIMT_Encode2(AMDGPU::BUFFER_STORE_DWORD_OFFSET),
      GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/0, // value
      GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/0, // srsrc
      GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/1, // soffset
      GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/2, // offset
      GIR_AddImm8, /*InsnID*/0, /*Imm*/0,
      GIR_AddImm8, /*InsnID*/0, /*Imm*/0,
      GIR_MergeMemOperands, /*InsnID*/0, /*NumInsns*/1, /*MergeInsnID's*/0,
      GIR_ConstrainSelectedInstOperands, /*InsnID*/0,
      GIR_EraseFromParent, /*InsnID*/0,
      // GIR_Coverage, 5522,
      GIR_Done,
    // Label 2118: @139140
    GIM_Try, /*On fail goto*//*Label 2119*/ GIMT_Encode4(139205), // Rule ID 5524 //
      GIM_CheckFeatures, GIMT_Encode2(GIFBS_DisableFlatScratch),
      GIM_CheckMemoryAddressSpace, /*MI*/0, /*MMO*/0, /*NumAddrSpace*/1, /*AddrSpace*/5,
      GIM_CheckAtomicOrdering, /*MI*/0, /*Order*/(uint8_t)AtomicOrdering::NotAtomic,
      GIM_CheckPointerToAny, /*MI*/0, /*Op*/1, /*SizeInBits*/0,
      GIM_CheckComplexPattern, /*MI*/0, /*Op*/1, /*Renderer*/GIMT_Encode2(0), GIMT_Encode2(GICP_gi_mubuf_scratch_offset),
      // (st v2i16:{ *:[v2i16] }:$value, (MUBUFScratchOffset:{ *:[iPTR] } v4i32:{ *:[v4i32] }:$srsrc, i32:{ *:[i32] }:$soffset, i32:{ *:[i32] }:$offset))<<P:Predicate_unindexedstore>><<P:Predicate_store_private>>  =>  (BUFFER_STORE_DWORD_VBUFFER_OFFSET VGPR_32:{ *:[v2i16] }:$value, ?:{ *:[v4i32] }:$srsrc, ?:{ *:[i32] }:$soffset, ?:{ *:[i32] }:$offset, 0:{ *:[i32] }, 0:{ *:[i1] })
      GIR_BuildMI, /*InsnID*/0, /*Opcode*/GIMT_Encode2(AMDGPU::BUFFER_STORE_DWORD_VBUFFER_OFFSET),
      GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/0, // value
      GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/0, // srsrc
      GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/1, // soffset
      GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/2, // offset
      GIR_AddImm8, /*InsnID*/0, /*Imm*/0,
      GIR_AddImm8, /*InsnID*/0, /*Imm*/0,
      GIR_MergeMemOperands, /*InsnID*/0, /*NumInsns*/1, /*MergeInsnID's*/0,
      GIR_ConstrainSelectedInstOperands, /*InsnID*/0,
      GIR_EraseFromParent, /*InsnID*/0,
      // GIR_Coverage, 5524,
      GIR_Done,
    // Label 2119: @139205
    GIM_Try, /*On fail goto*//*Label 2120*/ GIMT_Encode4(139270), // Rule ID 5526 //
      GIM_CheckFeatures, GIMT_Encode2(GIFBS_DisableFlatScratch_HasUnrestrictedSOffset),
      GIM_CheckMemoryAddressSpace, /*MI*/0, /*MMO*/0, /*NumAddrSpace*/1, /*AddrSpace*/5,
      GIM_CheckAtomicOrdering, /*MI*/0, /*Order*/(uint8_t)AtomicOrdering::NotAtomic,
      GIM_CheckPointerToAny, /*MI*/0, /*Op*/1, /*SizeInBits*/0,
      GIM_CheckComplexPattern, /*MI*/0, /*Op*/1, /*Renderer*/GIMT_Encode2(0), GIMT_Encode2(GICP_gi_mubuf_scratch_offset),
      // (st v2f16:{ *:[v2f16] }:$value, (MUBUFScratchOffset:{ *:[iPTR] } v4i32:{ *:[v4i32] }:$srsrc, i32:{ *:[i32] }:$soffset, i32:{ *:[i32] }:$offset))<<P:Predicate_unindexedstore>><<P:Predicate_store_private>>  =>  (BUFFER_STORE_DWORD_OFFSET VGPR_32:{ *:[v2f16] }:$value, ?:{ *:[v4i32] }:$srsrc, ?:{ *:[i32] }:$soffset, ?:{ *:[i32] }:$offset, 0:{ *:[i32] }, 0:{ *:[i1] })
      GIR_BuildMI, /*InsnID*/0, /*Opcode*/GIMT_Encode2(AMDGPU::BUFFER_STORE_DWORD_OFFSET),
      GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/0, // value
      GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/0, // srsrc
      GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/1, // soffset
      GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/2, // offset
      GIR_AddImm8, /*InsnID*/0, /*Imm*/0,
      GIR_AddImm8, /*InsnID*/0, /*Imm*/0,
      GIR_MergeMemOperands, /*InsnID*/0, /*NumInsns*/1, /*MergeInsnID's*/0,
      GIR_ConstrainSelectedInstOperands, /*InsnID*/0,
      GIR_EraseFromParent, /*InsnID*/0,
      // GIR_Coverage, 5526,
      GIR_Done,
    // Label 2120: @139270
    GIM_Try, /*On fail goto*//*Label 2121*/ GIMT_Encode4(139335), // Rule ID 5528 //
      GIM_CheckFeatures, GIMT_Encode2(GIFBS_DisableFlatScratch),
      GIM_CheckMemoryAddressSpace, /*MI*/0, /*MMO*/0, /*NumAddrSpace*/1, /*AddrSpace*/5,
      GIM_CheckAtomicOrdering, /*MI*/0, /*Order*/(uint8_t)AtomicOrdering::NotAtomic,
      GIM_CheckPointerToAny, /*MI*/0, /*Op*/1, /*SizeInBits*/0,
      GIM_CheckComplexPattern, /*MI*/0, /*Op*/1, /*Renderer*/GIMT_Encode2(0), GIMT_Encode2(GICP_gi_mubuf_scratch_offset),
      // (st v2f16:{ *:[v2f16] }:$value, (MUBUFScratchOffset:{ *:[iPTR] } v4i32:{ *:[v4i32] }:$srsrc, i32:{ *:[i32] }:$soffset, i32:{ *:[i32] }:$offset))<<P:Predicate_unindexedstore>><<P:Predicate_store_private>>  =>  (BUFFER_STORE_DWORD_VBUFFER_OFFSET VGPR_32:{ *:[v2f16] }:$value, ?:{ *:[v4i32] }:$srsrc, ?:{ *:[i32] }:$soffset, ?:{ *:[i32] }:$offset, 0:{ *:[i32] }, 0:{ *:[i1] })
      GIR_BuildMI, /*InsnID*/0, /*Opcode*/GIMT_Encode2(AMDGPU::BUFFER_STORE_DWORD_VBUFFER_OFFSET),
      GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/0, // value
      GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/0, // srsrc
      GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/1, // soffset
      GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/2, // offset
      GIR_AddImm8, /*InsnID*/0, /*Imm*/0,
      GIR_AddImm8, /*InsnID*/0, /*Imm*/0,
      GIR_MergeMemOperands, /*InsnID*/0, /*NumInsns*/1, /*MergeInsnID's*/0,
      GIR_ConstrainSelectedInstOperands, /*InsnID*/0,
      GIR_EraseFromParent, /*InsnID*/0,
      // GIR_Coverage, 5528,
      GIR_Done,
    // Label 2121: @139335
    GIM_Try, /*On fail goto*//*Label 2122*/ GIMT_Encode4(139400), // Rule ID 5530 //
      GIM_CheckFeatures, GIMT_Encode2(GIFBS_DisableFlatScratch_HasUnrestrictedSOffset),
      GIM_CheckMemoryAddressSpace, /*MI*/0, /*MMO*/0, /*NumAddrSpace*/1, /*AddrSpace*/5,
      GIM_CheckAtomicOrdering, /*MI*/0, /*Order*/(uint8_t)AtomicOrdering::NotAtomic,
      GIM_CheckPointerToAny, /*MI*/0, /*Op*/1, /*SizeInBits*/0,
      GIM_CheckComplexPattern, /*MI*/0, /*Op*/1, /*Renderer*/GIMT_Encode2(0), GIMT_Encode2(GICP_gi_mubuf_scratch_offset),
      // (st v2bf16:{ *:[v2bf16] }:$value, (MUBUFScratchOffset:{ *:[iPTR] } v4i32:{ *:[v4i32] }:$srsrc, i32:{ *:[i32] }:$soffset, i32:{ *:[i32] }:$offset))<<P:Predicate_unindexedstore>><<P:Predicate_store_private>>  =>  (BUFFER_STORE_DWORD_OFFSET VGPR_32:{ *:[v2bf16] }:$value, ?:{ *:[v4i32] }:$srsrc, ?:{ *:[i32] }:$soffset, ?:{ *:[i32] }:$offset, 0:{ *:[i32] }, 0:{ *:[i1] })
      GIR_BuildMI, /*InsnID*/0, /*Opcode*/GIMT_Encode2(AMDGPU::BUFFER_STORE_DWORD_OFFSET),
      GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/0, // value
      GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/0, // srsrc
      GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/1, // soffset
      GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/2, // offset
      GIR_AddImm8, /*InsnID*/0, /*Imm*/0,
      GIR_AddImm8, /*InsnID*/0, /*Imm*/0,
      GIR_MergeMemOperands, /*InsnID*/0, /*NumInsns*/1, /*MergeInsnID's*/0,
      GIR_ConstrainSelectedInstOperands, /*InsnID*/0,
      GIR_EraseFromParent, /*InsnID*/0,
      // GIR_Coverage, 5530,
      GIR_Done,
    // Label 2122: @139400
    GIM_Try, /*On fail goto*//*Label 2123*/ GIMT_Encode4(139465), // Rule ID 5532 //
      GIM_CheckFeatures, GIMT_Encode2(GIFBS_DisableFlatScratch),
      GIM_CheckMemoryAddressSpace, /*MI*/0, /*MMO*/0, /*NumAddrSpace*/1, /*AddrSpace*/5,
      GIM_CheckAtomicOrdering, /*MI*/0, /*Order*/(uint8_t)AtomicOrdering::NotAtomic,
      GIM_CheckPointerToAny, /*MI*/0, /*Op*/1, /*SizeInBits*/0,
      GIM_CheckComplexPattern, /*MI*/0, /*Op*/1, /*Renderer*/GIMT_Encode2(0), GIMT_Encode2(GICP_gi_mubuf_scratch_offset),
      // (st v2bf16:{ *:[v2bf16] }:$value, (MUBUFScratchOffset:{ *:[iPTR] } v4i32:{ *:[v4i32] }:$srsrc, i32:{ *:[i32] }:$soffset, i32:{ *:[i32] }:$offset))<<P:Predicate_unindexedstore>><<P:Predicate_store_private>>  =>  (BUFFER_STORE_DWORD_VBUFFER_OFFSET VGPR_32:{ *:[v2bf16] }:$value, ?:{ *:[v4i32] }:$srsrc, ?:{ *:[i32] }:$soffset, ?:{ *:[i32] }:$offset, 0:{ *:[i32] }, 0:{ *:[i1] })
      GIR_BuildMI, /*InsnID*/0, /*Opcode*/GIMT_Encode2(AMDGPU::BUFFER_STORE_DWORD_VBUFFER_OFFSET),
      GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/0, // value
      GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/0, // srsrc
      GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/1, // soffset
      GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/2, // offset
      GIR_AddImm8, /*InsnID*/0, /*Imm*/0,
      GIR_AddImm8, /*InsnID*/0, /*Imm*/0,
      GIR_MergeMemOperands, /*InsnID*/0, /*NumInsns*/1, /*MergeInsnID's*/0,
      GIR_ConstrainSelectedInstOperands, /*InsnID*/0,
      GIR_EraseFromParent, /*InsnID*/0,
      // GIR_Coverage, 5532,
      GIR_Done,
    // Label 2123: @139465
    GIM_Try, /*On fail goto*//*Label 2124*/ GIMT_Encode4(139527), // Rule ID 3445 //
      GIM_CheckFeatures, GIMT_Encode2(GIFBS_EnableFlatScratch_HasFlatScratchInsts_HasFlatScratchSVSMode),
      GIM_CheckMemoryAddressSpace, /*MI*/0, /*MMO*/0, /*NumAddrSpace*/1, /*AddrSpace*/5,
      GIM_CheckAtomicOrdering, /*MI*/0, /*Order*/(uint8_t)AtomicOrdering::NotAtomic,
      GIM_CheckPointerToAny, /*MI*/0, /*Op*/1, /*SizeInBits*/0,
      GIM_CheckComplexPattern, /*MI*/0, /*Op*/1, /*Renderer*/GIMT_Encode2(0), GIMT_Encode2(GICP_gi_flat_scratch_svaddr),
      // (st v2i16:{ *:[v2i16] }:$data, (ScratchSVAddr:{ *:[iPTR] } VGPR_32:{ *:[i32] }:$vaddr, SGPR_32:{ *:[i32] }:$saddr, i32:{ *:[i32] }:$offset))<<P:Predicate_unindexedstore>><<P:Predicate_store_private>>  =>  (SCRATCH_STORE_DWORD_SVS anonymous_15037:{ *:[v2i16] }:$data, ?:{ *:[i32] }:$vaddr, ?:{ *:[i32] }:$saddr, ?:{ *:[i32] }:$offset)
      GIR_BuildMI, /*InsnID*/0, /*Opcode*/GIMT_Encode2(AMDGPU::SCRATCH_STORE_DWORD_SVS),
      GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/0, // data
      GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/0, // vaddr
      GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/1, // saddr
      GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/2, // offset
      GIR_AddImm8, /*InsnID*/0, /*Imm*/0,
      GIR_MergeMemOperands, /*InsnID*/0, /*NumInsns*/1, /*MergeInsnID's*/0,
      GIR_ConstrainSelectedInstOperands, /*InsnID*/0,
      GIR_EraseFromParent, /*InsnID*/0,
      // GIR_Coverage, 3445,
      GIR_Done,
    // Label 2124: @139527
    GIM_Try, /*On fail goto*//*Label 2125*/ GIMT_Encode4(139589), // Rule ID 3451 //
      GIM_CheckFeatures, GIMT_Encode2(GIFBS_EnableFlatScratch_HasFlatScratchInsts_HasFlatScratchSVSMode),
      GIM_CheckMemoryAddressSpace, /*MI*/0, /*MMO*/0, /*NumAddrSpace*/1, /*AddrSpace*/5,
      GIM_CheckAtomicOrdering, /*MI*/0, /*Order*/(uint8_t)AtomicOrdering::NotAtomic,
      GIM_CheckPointerToAny, /*MI*/0, /*Op*/1, /*SizeInBits*/0,
      GIM_CheckComplexPattern, /*MI*/0, /*Op*/1, /*Renderer*/GIMT_Encode2(0), GIMT_Encode2(GICP_gi_flat_scratch_svaddr),
      // (st v2f16:{ *:[v2f16] }:$data, (ScratchSVAddr:{ *:[iPTR] } VGPR_32:{ *:[i32] }:$vaddr, SGPR_32:{ *:[i32] }:$saddr, i32:{ *:[i32] }:$offset))<<P:Predicate_unindexedstore>><<P:Predicate_store_private>>  =>  (SCRATCH_STORE_DWORD_SVS anonymous_15037:{ *:[v2f16] }:$data, ?:{ *:[i32] }:$vaddr, ?:{ *:[i32] }:$saddr, ?:{ *:[i32] }:$offset)
      GIR_BuildMI, /*InsnID*/0, /*Opcode*/GIMT_Encode2(AMDGPU::SCRATCH_STORE_DWORD_SVS),
      GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/0, // data
      GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/0, // vaddr
      GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/1, // saddr
      GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/2, // offset
      GIR_AddImm8, /*InsnID*/0, /*Imm*/0,
      GIR_MergeMemOperands, /*InsnID*/0, /*NumInsns*/1, /*MergeInsnID's*/0,
      GIR_ConstrainSelectedInstOperands, /*InsnID*/0,
      GIR_EraseFromParent, /*InsnID*/0,
      // GIR_Coverage, 3451,
      GIR_Done,
    // Label 2125: @139589
    GIM_Try, /*On fail goto*//*Label 2126*/ GIMT_Encode4(139651), // Rule ID 3457 //
      GIM_CheckFeatures, GIMT_Encode2(GIFBS_EnableFlatScratch_HasFlatScratchInsts_HasFlatScratchSVSMode),
      GIM_CheckMemoryAddressSpace, /*MI*/0, /*MMO*/0, /*NumAddrSpace*/1, /*AddrSpace*/5,
      GIM_CheckAtomicOrdering, /*MI*/0, /*Order*/(uint8_t)AtomicOrdering::NotAtomic,
      GIM_CheckPointerToAny, /*MI*/0, /*Op*/1, /*SizeInBits*/0,
      GIM_CheckComplexPattern, /*MI*/0, /*Op*/1, /*Renderer*/GIMT_Encode2(0), GIMT_Encode2(GICP_gi_flat_scratch_svaddr),
      // (st v2bf16:{ *:[v2bf16] }:$data, (ScratchSVAddr:{ *:[iPTR] } VGPR_32:{ *:[i32] }:$vaddr, SGPR_32:{ *:[i32] }:$saddr, i32:{ *:[i32] }:$offset))<<P:Predicate_unindexedstore>><<P:Predicate_store_private>>  =>  (SCRATCH_STORE_DWORD_SVS anonymous_15037:{ *:[v2bf16] }:$data, ?:{ *:[i32] }:$vaddr, ?:{ *:[i32] }:$saddr, ?:{ *:[i32] }:$offset)
      GIR_BuildMI, /*InsnID*/0, /*Opcode*/GIMT_Encode2(AMDGPU::SCRATCH_STORE_DWORD_SVS),
      GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/0, // data
      GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/0, // vaddr
      GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/1, // saddr
      GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/2, // offset
      GIR_AddImm8, /*InsnID*/0, /*Imm*/0,
      GIR_MergeMemOperands, /*InsnID*/0, /*NumInsns*/1, /*MergeInsnID's*/0,
      GIR_ConstrainSelectedInstOperands, /*InsnID*/0,
      GIR_EraseFromParent, /*InsnID*/0,
      // GIR_Coverage, 3457,
      GIR_Done,
    // Label 2126: @139651
    GIM_Try, /*On fail goto*//*Label 2127*/ GIMT_Encode4(139708), // Rule ID 3444 //
      GIM_CheckFeatures, GIMT_Encode2(GIFBS_EnableFlatScratch_HasFlatScratchInsts),
      GIM_CheckMemoryAddressSpace, /*MI*/0, /*MMO*/0, /*NumAddrSpace*/1, /*AddrSpace*/5,
      GIM_CheckAtomicOrdering, /*MI*/0, /*Order*/(uint8_t)AtomicOrdering::NotAtomic,
      GIM_CheckPointerToAny, /*MI*/0, /*Op*/1, /*SizeInBits*/0,
      GIM_CheckComplexPattern, /*MI*/0, /*Op*/1, /*Renderer*/GIMT_Encode2(0), GIMT_Encode2(GICP_gi_flat_scratch_saddr),
      // (st v2i16:{ *:[v2i16] }:$data, (ScratchSAddr:{ *:[iPTR] } SGPR_32:{ *:[i32] }:$saddr, i32:{ *:[i32] }:$offset))<<P:Predicate_unindexedstore>><<P:Predicate_store_private>>  =>  (SCRATCH_STORE_DWORD_SADDR anonymous_15037:{ *:[v2i16] }:$data, ?:{ *:[i32] }:$saddr, ?:{ *:[i32] }:$offset)
      GIR_BuildMI, /*InsnID*/0, /*Opcode*/GIMT_Encode2(AMDGPU::SCRATCH_STORE_DWORD_SADDR),
      GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/0, // data
      GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/0, // saddr
      GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/1, // offset
      GIR_AddImm8, /*InsnID*/0, /*Imm*/0,
      GIR_MergeMemOperands, /*InsnID*/0, /*NumInsns*/1, /*MergeInsnID's*/0,
      GIR_ConstrainSelectedInstOperands, /*InsnID*/0,
      GIR_EraseFromParent, /*InsnID*/0,
      // GIR_Coverage, 3444,
      GIR_Done,
    // Label 2127: @139708
    GIM_Try, /*On fail goto*//*Label 2128*/ GIMT_Encode4(139765), // Rule ID 3450 //
      GIM_CheckFeatures, GIMT_Encode2(GIFBS_EnableFlatScratch_HasFlatScratchInsts),
      GIM_CheckMemoryAddressSpace, /*MI*/0, /*MMO*/0, /*NumAddrSpace*/1, /*AddrSpace*/5,
      GIM_CheckAtomicOrdering, /*MI*/0, /*Order*/(uint8_t)AtomicOrdering::NotAtomic,
      GIM_CheckPointerToAny, /*MI*/0, /*Op*/1, /*SizeInBits*/0,
      GIM_CheckComplexPattern, /*MI*/0, /*Op*/1, /*Renderer*/GIMT_Encode2(0), GIMT_Encode2(GICP_gi_flat_scratch_saddr),
      // (st v2f16:{ *:[v2f16] }:$data, (ScratchSAddr:{ *:[iPTR] } SGPR_32:{ *:[i32] }:$saddr, i32:{ *:[i32] }:$offset))<<P:Predicate_unindexedstore>><<P:Predicate_store_private>>  =>  (SCRATCH_STORE_DWORD_SADDR anonymous_15037:{ *:[v2f16] }:$data, ?:{ *:[i32] }:$saddr, ?:{ *:[i32] }:$offset)
      GIR_BuildMI, /*InsnID*/0, /*Opcode*/GIMT_Encode2(AMDGPU::SCRATCH_STORE_DWORD_SADDR),
      GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/0, // data
      GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/0, // saddr
      GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/1, // offset
      GIR_AddImm8, /*InsnID*/0, /*Imm*/0,
      GIR_MergeMemOperands, /*InsnID*/0, /*NumInsns*/1, /*MergeInsnID's*/0,
      GIR_ConstrainSelectedInstOperands, /*InsnID*/0,
      GIR_EraseFromParent, /*InsnID*/0,
      // GIR_Coverage, 3450,
      GIR_Done,
    // Label 2128: @139765
    GIM_Try, /*On fail goto*//*Label 2129*/ GIMT_Encode4(139822), // Rule ID 3456 //
      GIM_CheckFeatures, GIMT_Encode2(GIFBS_EnableFlatScratch_HasFlatScratchInsts),
      GIM_CheckMemoryAddressSpace, /*MI*/0, /*MMO*/0, /*NumAddrSpace*/1, /*AddrSpace*/5,
      GIM_CheckAtomicOrdering, /*MI*/0, /*Order*/(uint8_t)AtomicOrdering::NotAtomic,
      GIM_CheckPointerToAny, /*MI*/0, /*Op*/1, /*SizeInBits*/0,
      GIM_CheckComplexPattern, /*MI*/0, /*Op*/1, /*Renderer*/GIMT_Encode2(0), GIMT_Encode2(GICP_gi_flat_scratch_saddr),
      // (st v2bf16:{ *:[v2bf16] }:$data, (ScratchSAddr:{ *:[iPTR] } SGPR_32:{ *:[i32] }:$saddr, i32:{ *:[i32] }:$offset))<<P:Predicate_unindexedstore>><<P:Predicate_store_private>>  =>  (SCRATCH_STORE_DWORD_SADDR anonymous_15037:{ *:[v2bf16] }:$data, ?:{ *:[i32] }:$saddr, ?:{ *:[i32] }:$offset)
      GIR_BuildMI, /*InsnID*/0, /*Opcode*/GIMT_Encode2(AMDGPU::SCRATCH_STORE_DWORD_SADDR),
      GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/0, // data
      GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/0, // saddr
      GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/1, // offset
      GIR_AddImm8, /*InsnID*/0, /*Imm*/0,
      GIR_MergeMemOperands, /*InsnID*/0, /*NumInsns*/1, /*MergeInsnID's*/0,
      GIR_ConstrainSelectedInstOperands, /*InsnID*/0,
      GIR_EraseFromParent, /*InsnID*/0,
      // GIR_Coverage, 3456,
      GIR_Done,
    // Label 2129: @139822
    GIM_Try, /*On fail goto*//*Label 2130*/ GIMT_Encode4(139879), // Rule ID 3443 //
      GIM_CheckFeatures, GIMT_Encode2(GIFBS_EnableFlatScratch_HasFlatScratchInsts),
      GIM_CheckMemoryAddressSpace, /*MI*/0, /*MMO*/0, /*NumAddrSpace*/1, /*AddrSpace*/5,
      GIM_CheckAtomicOrdering, /*MI*/0, /*Order*/(uint8_t)AtomicOrdering::NotAtomic,
      GIM_CheckPointerToAny, /*MI*/0, /*Op*/1, /*SizeInBits*/0,
      GIM_CheckComplexPattern, /*MI*/0, /*Op*/1, /*Renderer*/GIMT_Encode2(0), GIMT_Encode2(GICP_gi_flat_scratch_offset),
      // (st v2i16:{ *:[v2i16] }:$data, (ScratchOffset:{ *:[iPTR] } VGPR_32:{ *:[i32] }:$vaddr, i32:{ *:[i32] }:$offset))<<P:Predicate_unindexedstore>><<P:Predicate_store_private>>  =>  (SCRATCH_STORE_DWORD anonymous_15037:{ *:[v2i16] }:$data, ?:{ *:[i32] }:$vaddr, ?:{ *:[i32] }:$offset)
      GIR_BuildMI, /*InsnID*/0, /*Opcode*/GIMT_Encode2(AMDGPU::SCRATCH_STORE_DWORD),
      GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/0, // data
      GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/0, // vaddr
      GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/1, // offset
      GIR_AddImm8, /*InsnID*/0, /*Imm*/0,
      GIR_MergeMemOperands, /*InsnID*/0, /*NumInsns*/1, /*MergeInsnID's*/0,
      GIR_ConstrainSelectedInstOperands, /*InsnID*/0,
      GIR_EraseFromParent, /*InsnID*/0,
      // GIR_Coverage, 3443,
      GIR_Done,
    // Label 2130: @139879
    GIM_Try, /*On fail goto*//*Label 2131*/ GIMT_Encode4(139936), // Rule ID 3449 //
      GIM_CheckFeatures, GIMT_Encode2(GIFBS_EnableFlatScratch_HasFlatScratchInsts),
      GIM_CheckMemoryAddressSpace, /*MI*/0, /*MMO*/0, /*NumAddrSpace*/1, /*AddrSpace*/5,
      GIM_CheckAtomicOrdering, /*MI*/0, /*Order*/(uint8_t)AtomicOrdering::NotAtomic,
      GIM_CheckPointerToAny, /*MI*/0, /*Op*/1, /*SizeInBits*/0,
      GIM_CheckComplexPattern, /*MI*/0, /*Op*/1, /*Renderer*/GIMT_Encode2(0), GIMT_Encode2(GICP_gi_flat_scratch_offset),
      // (st v2f16:{ *:[v2f16] }:$data, (ScratchOffset:{ *:[iPTR] } VGPR_32:{ *:[i32] }:$vaddr, i32:{ *:[i32] }:$offset))<<P:Predicate_unindexedstore>><<P:Predicate_store_private>>  =>  (SCRATCH_STORE_DWORD anonymous_15037:{ *:[v2f16] }:$data, ?:{ *:[i32] }:$vaddr, ?:{ *:[i32] }:$offset)
      GIR_BuildMI, /*InsnID*/0, /*Opcode*/GIMT_Encode2(AMDGPU::SCRATCH_STORE_DWORD),
      GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/0, // data
      GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/0, // vaddr
      GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/1, // offset
      GIR_AddImm8, /*InsnID*/0, /*Imm*/0,
      GIR_MergeMemOperands, /*InsnID*/0, /*NumInsns*/1, /*MergeInsnID's*/0,
      GIR_ConstrainSelectedInstOperands, /*InsnID*/0,
      GIR_EraseFromParent, /*InsnID*/0,
      // GIR_Coverage, 3449,
      GIR_Done,
    // Label 2131: @139936
    GIM_Try, /*On fail goto*//*Label 2132*/ GIMT_Encode4(139993), // Rule ID 3455 //
      GIM_CheckFeatures, GIMT_Encode2(GIFBS_EnableFlatScratch_HasFlatScratchInsts),
      GIM_CheckMemoryAddressSpace, /*MI*/0, /*MMO*/0, /*NumAddrSpace*/1, /*AddrSpace*/5,
      GIM_CheckAtomicOrdering, /*MI*/0, /*Order*/(uint8_t)AtomicOrdering::NotAtomic,
      GIM_CheckPointerToAny, /*MI*/0, /*Op*/1, /*SizeInBits*/0,
      GIM_CheckComplexPattern, /*MI*/0, /*Op*/1, /*Renderer*/GIMT_Encode2(0), GIMT_Encode2(GICP_gi_flat_scratch_offset),
      // (st v2bf16:{ *:[v2bf16] }:$data, (ScratchOffset:{ *:[iPTR] } VGPR_32:{ *:[i32] }:$vaddr, i32:{ *:[i32] }:$offset))<<P:Predicate_unindexedstore>><<P:Predicate_store_private>>  =>  (SCRATCH_STORE_DWORD anonymous_15037:{ *:[v2bf16] }:$data, ?:{ *:[i32] }:$vaddr, ?:{ *:[i32] }:$offset)
      GIR_BuildMI, /*InsnID*/0, /*Opcode*/GIMT_Encode2(AMDGPU::SCRATCH_STORE_DWORD),
      GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/0, // data
      GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/0, // vaddr
      GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/1, // offset
      GIR_AddImm8, /*InsnID*/0, /*Imm*/0,
      GIR_MergeMemOperands, /*InsnID*/0, /*NumInsns*/1, /*MergeInsnID's*/0,
      GIR_ConstrainSelectedInstOperands, /*InsnID*/0,
      GIR_EraseFromParent, /*InsnID*/0,
      // GIR_Coverage, 3455,
      GIR_Done,
    // Label 2132: @139993
    GIM_Try, /*On fail goto*//*Label 2133*/ GIMT_Encode4(140063), // Rule ID 3810 //
      GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasUnrestrictedSOffset),
      GIM_CheckMemoryAddressSpace, /*MI*/0, /*MMO*/0, /*NumAddrSpace*/1, /*AddrSpace*/1,
      GIM_CheckAtomicOrdering, /*MI*/0, /*Order*/(uint8_t)AtomicOrdering::NotAtomic,
      GIM_CheckPointerToAny, /*MI*/0, /*Op*/1, /*SizeInBits*/0,
      GIM_CheckComplexPattern, /*MI*/0, /*Op*/1, /*Renderer*/GIMT_Encode2(0), GIMT_Encode2(GICP_gi_mubuf_addr64),
      // (st v2i16:{ *:[v2i16] }:$vdata, (MUBUFAddr64:{ *:[iPTR] } v4i32:{ *:[v4i32] }:$srsrc, i64:{ *:[i64] }:$vaddr, i32:{ *:[i32] }:$soffset, i32:{ *:[i32] }:$offset))<<P:Predicate_unindexedstore>><<P:Predicate_store_global>>  =>  (BUFFER_STORE_DWORD_ADDR64 v2i16:{ *:[v2i16] }:$vdata, i64:{ *:[i64] }:$vaddr, v4i32:{ *:[v4i32] }:$srsrc, i32:{ *:[i32] }:$soffset, i32:{ *:[i32] }:$offset)
      GIR_BuildMI, /*InsnID*/0, /*Opcode*/GIMT_Encode2(AMDGPU::BUFFER_STORE_DWORD_ADDR64),
      GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/0, // vdata
      GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/1, // vaddr
      GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/0, // srsrc
      GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/2, // soffset
      GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/3, // offset
      GIR_AddImm8, /*InsnID*/0, /*Imm*/0,
      GIR_AddImm8, /*InsnID*/0, /*Imm*/0,
      GIR_MergeMemOperands, /*InsnID*/0, /*NumInsns*/1, /*MergeInsnID's*/0,
      GIR_ConstrainSelectedInstOperands, /*InsnID*/0,
      GIR_EraseFromParent, /*InsnID*/0,
      // GIR_Coverage, 3810,
      GIR_Done,
    // Label 2133: @140063
    GIM_Try, /*On fail goto*//*Label 2134*/ GIMT_Encode4(140130), // Rule ID 3812 //
      GIM_CheckMemoryAddressSpace, /*MI*/0, /*MMO*/0, /*NumAddrSpace*/1, /*AddrSpace*/1,
      GIM_CheckAtomicOrdering, /*MI*/0, /*Order*/(uint8_t)AtomicOrdering::NotAtomic,
      GIM_CheckPointerToAny, /*MI*/0, /*Op*/1, /*SizeInBits*/0,
      GIM_CheckComplexPattern, /*MI*/0, /*Op*/1, /*Renderer*/GIMT_Encode2(0), GIMT_Encode2(GICP_gi_mubuf_addr64),
      // (st v2i16:{ *:[v2i16] }:$vdata, (MUBUFAddr64:{ *:[iPTR] } v4i32:{ *:[v4i32] }:$srsrc, i64:{ *:[i64] }:$vaddr, i32:{ *:[i32] }:$soffset, i32:{ *:[i32] }:$offset))<<P:Predicate_unindexedstore>><<P:Predicate_store_global>>  =>  (BUFFER_STORE_DWORD_VBUFFER_ADDR64 v2i16:{ *:[v2i16] }:$vdata, i64:{ *:[i64] }:$vaddr, v4i32:{ *:[v4i32] }:$srsrc, i32:{ *:[i32] }:$soffset, i32:{ *:[i32] }:$offset)
      GIR_BuildMI, /*InsnID*/0, /*Opcode*/GIMT_Encode2(AMDGPU::BUFFER_STORE_DWORD_VBUFFER_ADDR64),
      GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/0, // vdata
      GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/1, // vaddr
      GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/0, // srsrc
      GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/2, // soffset
      GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/3, // offset
      GIR_AddImm8, /*InsnID*/0, /*Imm*/0,
      GIR_AddImm8, /*InsnID*/0, /*Imm*/0,
      GIR_MergeMemOperands, /*InsnID*/0, /*NumInsns*/1, /*MergeInsnID's*/0,
      GIR_ConstrainSelectedInstOperands, /*InsnID*/0,
      GIR_EraseFromParent, /*InsnID*/0,
      // GIR_Coverage, 3812,
      GIR_Done,
    // Label 2134: @140130
    GIM_Try, /*On fail goto*//*Label 2135*/ GIMT_Encode4(140200), // Rule ID 3814 //
      GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasUnrestrictedSOffset),
      GIM_CheckMemoryAddressSpace, /*MI*/0, /*MMO*/0, /*NumAddrSpace*/1, /*AddrSpace*/1,
      GIM_CheckAtomicOrdering, /*MI*/0, /*Order*/(uint8_t)AtomicOrdering::NotAtomic,
      GIM_CheckPointerToAny, /*MI*/0, /*Op*/1, /*SizeInBits*/0,
      GIM_CheckComplexPattern, /*MI*/0, /*Op*/1, /*Renderer*/GIMT_Encode2(0), GIMT_Encode2(GICP_gi_mubuf_addr64),
      // (st v2f16:{ *:[v2f16] }:$vdata, (MUBUFAddr64:{ *:[iPTR] } v4i32:{ *:[v4i32] }:$srsrc, i64:{ *:[i64] }:$vaddr, i32:{ *:[i32] }:$soffset, i32:{ *:[i32] }:$offset))<<P:Predicate_unindexedstore>><<P:Predicate_store_global>>  =>  (BUFFER_STORE_DWORD_ADDR64 v2f16:{ *:[v2f16] }:$vdata, i64:{ *:[i64] }:$vaddr, v4i32:{ *:[v4i32] }:$srsrc, i32:{ *:[i32] }:$soffset, i32:{ *:[i32] }:$offset)
      GIR_BuildMI, /*InsnID*/0, /*Opcode*/GIMT_Encode2(AMDGPU::BUFFER_STORE_DWORD_ADDR64),
      GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/0, // vdata
      GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/1, // vaddr
      GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/0, // srsrc
      GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/2, // soffset
      GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/3, // offset
      GIR_AddImm8, /*InsnID*/0, /*Imm*/0,
      GIR_AddImm8, /*InsnID*/0, /*Imm*/0,
      GIR_MergeMemOperands, /*InsnID*/0, /*NumInsns*/1, /*MergeInsnID's*/0,
      GIR_ConstrainSelectedInstOperands, /*InsnID*/0,
      GIR_EraseFromParent, /*InsnID*/0,
      // GIR_Coverage, 3814,
      GIR_Done,
    // Label 2135: @140200
    GIM_Try, /*On fail goto*//*Label 2136*/ GIMT_Encode4(140267), // Rule ID 3816 //
      GIM_CheckMemoryAddressSpace, /*MI*/0, /*MMO*/0, /*NumAddrSpace*/1, /*AddrSpace*/1,
      GIM_CheckAtomicOrdering, /*MI*/0, /*Order*/(uint8_t)AtomicOrdering::NotAtomic,
      GIM_CheckPointerToAny, /*MI*/0, /*Op*/1, /*SizeInBits*/0,
      GIM_CheckComplexPattern, /*MI*/0, /*Op*/1, /*Renderer*/GIMT_Encode2(0), GIMT_Encode2(GICP_gi_mubuf_addr64),
      // (st v2f16:{ *:[v2f16] }:$vdata, (MUBUFAddr64:{ *:[iPTR] } v4i32:{ *:[v4i32] }:$srsrc, i64:{ *:[i64] }:$vaddr, i32:{ *:[i32] }:$soffset, i32:{ *:[i32] }:$offset))<<P:Predicate_unindexedstore>><<P:Predicate_store_global>>  =>  (BUFFER_STORE_DWORD_VBUFFER_ADDR64 v2f16:{ *:[v2f16] }:$vdata, i64:{ *:[i64] }:$vaddr, v4i32:{ *:[v4i32] }:$srsrc, i32:{ *:[i32] }:$soffset, i32:{ *:[i32] }:$offset)
      GIR_BuildMI, /*InsnID*/0, /*Opcode*/GIMT_Encode2(AMDGPU::BUFFER_STORE_DWORD_VBUFFER_ADDR64),
      GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/0, // vdata
      GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/1, // vaddr
      GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/0, // srsrc
      GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/2, // soffset
      GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/3, // offset
      GIR_AddImm8, /*InsnID*/0, /*Imm*/0,
      GIR_AddImm8, /*InsnID*/0, /*Imm*/0,
      GIR_MergeMemOperands, /*InsnID*/0, /*NumInsns*/1, /*MergeInsnID's*/0,
      GIR_ConstrainSelectedInstOperands, /*InsnID*/0,
      GIR_EraseFromParent, /*InsnID*/0,
      // GIR_Coverage, 3816,
      GIR_Done,
    // Label 2136: @140267
    GIM_Try, /*On fail goto*//*Label 2137*/ GIMT_Encode4(140337), // Rule ID 3818 //
      GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasUnrestrictedSOffset),
      GIM_CheckMemoryAddressSpace, /*MI*/0, /*MMO*/0, /*NumAddrSpace*/1, /*AddrSpace*/1,
      GIM_CheckAtomicOrdering, /*MI*/0, /*Order*/(uint8_t)AtomicOrdering::NotAtomic,
      GIM_CheckPointerToAny, /*MI*/0, /*Op*/1, /*SizeInBits*/0,
      GIM_CheckComplexPattern, /*MI*/0, /*Op*/1, /*Renderer*/GIMT_Encode2(0), GIMT_Encode2(GICP_gi_mubuf_addr64),
      // (st v2bf16:{ *:[v2bf16] }:$vdata, (MUBUFAddr64:{ *:[iPTR] } v4i32:{ *:[v4i32] }:$srsrc, i64:{ *:[i64] }:$vaddr, i32:{ *:[i32] }:$soffset, i32:{ *:[i32] }:$offset))<<P:Predicate_unindexedstore>><<P:Predicate_store_global>>  =>  (BUFFER_STORE_DWORD_ADDR64 v2bf16:{ *:[v2bf16] }:$vdata, i64:{ *:[i64] }:$vaddr, v4i32:{ *:[v4i32] }:$srsrc, i32:{ *:[i32] }:$soffset, i32:{ *:[i32] }:$offset)
      GIR_BuildMI, /*InsnID*/0, /*Opcode*/GIMT_Encode2(AMDGPU::BUFFER_STORE_DWORD_ADDR64),
      GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/0, // vdata
      GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/1, // vaddr
      GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/0, // srsrc
      GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/2, // soffset
      GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/3, // offset
      GIR_AddImm8, /*InsnID*/0, /*Imm*/0,
      GIR_AddImm8, /*InsnID*/0, /*Imm*/0,
      GIR_MergeMemOperands, /*InsnID*/0, /*NumInsns*/1, /*MergeInsnID's*/0,
      GIR_ConstrainSelectedInstOperands, /*InsnID*/0,
      GIR_EraseFromParent, /*InsnID*/0,
      // GIR_Coverage, 3818,
      GIR_Done,
    // Label 2137: @140337
    GIM_Try, /*On fail goto*//*Label 2138*/ GIMT_Encode4(140404), // Rule ID 3820 //
      GIM_CheckMemoryAddressSpace, /*MI*/0, /*MMO*/0, /*NumAddrSpace*/1, /*AddrSpace*/1,
      GIM_CheckAtomicOrdering, /*MI*/0, /*Order*/(uint8_t)AtomicOrdering::NotAtomic,
      GIM_CheckPointerToAny, /*MI*/0, /*Op*/1, /*SizeInBits*/0,
      GIM_CheckComplexPattern, /*MI*/0, /*Op*/1, /*Renderer*/GIMT_Encode2(0), GIMT_Encode2(GICP_gi_mubuf_addr64),
      // (st v2bf16:{ *:[v2bf16] }:$vdata, (MUBUFAddr64:{ *:[iPTR] } v4i32:{ *:[v4i32] }:$srsrc, i64:{ *:[i64] }:$vaddr, i32:{ *:[i32] }:$soffset, i32:{ *:[i32] }:$offset))<<P:Predicate_unindexedstore>><<P:Predicate_store_global>>  =>  (BUFFER_STORE_DWORD_VBUFFER_ADDR64 v2bf16:{ *:[v2bf16] }:$vdata, i64:{ *:[i64] }:$vaddr, v4i32:{ *:[v4i32] }:$srsrc, i32:{ *:[i32] }:$soffset, i32:{ *:[i32] }:$offset)
      GIR_BuildMI, /*InsnID*/0, /*Opcode*/GIMT_Encode2(AMDGPU::BUFFER_STORE_DWORD_VBUFFER_ADDR64),
      GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/0, // vdata
      GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/1, // vaddr
      GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/0, // srsrc
      GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/2, // soffset
      GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/3, // offset
      GIR_AddImm8, /*InsnID*/0, /*Imm*/0,
      GIR_AddImm8, /*InsnID*/0, /*Imm*/0,
      GIR_MergeMemOperands, /*InsnID*/0, /*NumInsns*/1, /*MergeInsnID's*/0,
      GIR_ConstrainSelectedInstOperands, /*InsnID*/0,
      GIR_EraseFromParent, /*InsnID*/0,
      // GIR_Coverage, 3820,
      GIR_Done,
    // Label 2138: @140404
    GIM_Try, /*On fail goto*//*Label 2139*/ GIMT_Encode4(140474), // Rule ID 5521 //
      GIM_CheckFeatures, GIMT_Encode2(GIFBS_DisableFlatScratch_HasUnrestrictedSOffset),
      GIM_CheckMemoryAddressSpace, /*MI*/0, /*MMO*/0, /*NumAddrSpace*/1, /*AddrSpace*/5,
      GIM_CheckAtomicOrdering, /*MI*/0, /*Order*/(uint8_t)AtomicOrdering::NotAtomic,
      GIM_CheckPointerToAny, /*MI*/0, /*Op*/1, /*SizeInBits*/0,
      GIM_CheckComplexPattern, /*MI*/0, /*Op*/1, /*Renderer*/GIMT_Encode2(0), GIMT_Encode2(GICP_gi_mubuf_scratch_offen),
      // (st v2i16:{ *:[v2i16] }:$value, (MUBUFScratchOffen:{ *:[iPTR] } v4i32:{ *:[v4i32] }:$srsrc, i32:{ *:[i32] }:$vaddr, i32:{ *:[i32] }:$soffset, i32:{ *:[i32] }:$offset))<<P:Predicate_unindexedstore>><<P:Predicate_store_private>>  =>  (BUFFER_STORE_DWORD_OFFEN VGPR_32:{ *:[v2i16] }:$value, ?:{ *:[i32] }:$vaddr, ?:{ *:[v4i32] }:$srsrc, ?:{ *:[i32] }:$soffset, ?:{ *:[i32] }:$offset, 0:{ *:[i32] }, 0:{ *:[i1] })
      GIR_BuildMI, /*InsnID*/0, /*Opcode*/GIMT_Encode2(AMDGPU::BUFFER_STORE_DWORD_OFFEN),
      GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/0, // value
      GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/1, // vaddr
      GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/0, // srsrc
      GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/2, // soffset
      GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/3, // offset
      GIR_AddImm8, /*InsnID*/0, /*Imm*/0,
      GIR_AddImm8, /*InsnID*/0, /*Imm*/0,
      GIR_MergeMemOperands, /*InsnID*/0, /*NumInsns*/1, /*MergeInsnID's*/0,
      GIR_ConstrainSelectedInstOperands, /*InsnID*/0,
      GIR_EraseFromParent, /*InsnID*/0,
      // GIR_Coverage, 5521,
      GIR_Done,
    // Label 2139: @140474
    GIM_Try, /*On fail goto*//*Label 2140*/ GIMT_Encode4(140544), // Rule ID 5523 //
      GIM_CheckFeatures, GIMT_Encode2(GIFBS_DisableFlatScratch),
      GIM_CheckMemoryAddressSpace, /*MI*/0, /*MMO*/0, /*NumAddrSpace*/1, /*AddrSpace*/5,
      GIM_CheckAtomicOrdering, /*MI*/0, /*Order*/(uint8_t)AtomicOrdering::NotAtomic,
      GIM_CheckPointerToAny, /*MI*/0, /*Op*/1, /*SizeInBits*/0,
      GIM_CheckComplexPattern, /*MI*/0, /*Op*/1, /*Renderer*/GIMT_Encode2(0), GIMT_Encode2(GICP_gi_mubuf_scratch_offen),
      // (st v2i16:{ *:[v2i16] }:$value, (MUBUFScratchOffen:{ *:[iPTR] } v4i32:{ *:[v4i32] }:$srsrc, i32:{ *:[i32] }:$vaddr, i32:{ *:[i32] }:$soffset, i32:{ *:[i32] }:$offset))<<P:Predicate_unindexedstore>><<P:Predicate_store_private>>  =>  (BUFFER_STORE_DWORD_VBUFFER_OFFEN VGPR_32:{ *:[v2i16] }:$value, ?:{ *:[i32] }:$vaddr, ?:{ *:[v4i32] }:$srsrc, ?:{ *:[i32] }:$soffset, ?:{ *:[i32] }:$offset, 0:{ *:[i32] }, 0:{ *:[i1] })
      GIR_BuildMI, /*InsnID*/0, /*Opcode*/GIMT_Encode2(AMDGPU::BUFFER_STORE_DWORD_VBUFFER_OFFEN),
      GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/0, // value
      GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/1, // vaddr
      GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/0, // srsrc
      GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/2, // soffset
      GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/3, // offset
      GIR_AddImm8, /*InsnID*/0, /*Imm*/0,
      GIR_AddImm8, /*InsnID*/0, /*Imm*/0,
      GIR_MergeMemOperands, /*InsnID*/0, /*NumInsns*/1, /*MergeInsnID's*/0,
      GIR_ConstrainSelectedInstOperands, /*InsnID*/0,
      GIR_EraseFromParent, /*InsnID*/0,
      // GIR_Coverage, 5523,
      GIR_Done,
    // Label 2140: @140544
    GIM_Try, /*On fail goto*//*Label 2141*/ GIMT_Encode4(140614), // Rule ID 5525 //
      GIM_CheckFeatures, GIMT_Encode2(GIFBS_DisableFlatScratch_HasUnrestrictedSOffset),
      GIM_CheckMemoryAddressSpace, /*MI*/0, /*MMO*/0, /*NumAddrSpace*/1, /*AddrSpace*/5,
      GIM_CheckAtomicOrdering, /*MI*/0, /*Order*/(uint8_t)AtomicOrdering::NotAtomic,
      GIM_CheckPointerToAny, /*MI*/0, /*Op*/1, /*SizeInBits*/0,
      GIM_CheckComplexPattern, /*MI*/0, /*Op*/1, /*Renderer*/GIMT_Encode2(0), GIMT_Encode2(GICP_gi_mubuf_scratch_offen),
      // (st v2f16:{ *:[v2f16] }:$value, (MUBUFScratchOffen:{ *:[iPTR] } v4i32:{ *:[v4i32] }:$srsrc, i32:{ *:[i32] }:$vaddr, i32:{ *:[i32] }:$soffset, i32:{ *:[i32] }:$offset))<<P:Predicate_unindexedstore>><<P:Predicate_store_private>>  =>  (BUFFER_STORE_DWORD_OFFEN VGPR_32:{ *:[v2f16] }:$value, ?:{ *:[i32] }:$vaddr, ?:{ *:[v4i32] }:$srsrc, ?:{ *:[i32] }:$soffset, ?:{ *:[i32] }:$offset, 0:{ *:[i32] }, 0:{ *:[i1] })
      GIR_BuildMI, /*InsnID*/0, /*Opcode*/GIMT_Encode2(AMDGPU::BUFFER_STORE_DWORD_OFFEN),
      GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/0, // value
      GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/1, // vaddr
      GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/0, // srsrc
      GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/2, // soffset
      GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/3, // offset
      GIR_AddImm8, /*InsnID*/0, /*Imm*/0,
      GIR_AddImm8, /*InsnID*/0, /*Imm*/0,
      GIR_MergeMemOperands, /*InsnID*/0, /*NumInsns*/1, /*MergeInsnID's*/0,
      GIR_ConstrainSelectedInstOperands, /*InsnID*/0,
      GIR_EraseFromParent, /*InsnID*/0,
      // GIR_Coverage, 5525,
      GIR_Done,
    // Label 2141: @140614
    GIM_Try, /*On fail goto*//*Label 2142*/ GIMT_Encode4(140684), // Rule ID 5527 //
      GIM_CheckFeatures, GIMT_Encode2(GIFBS_DisableFlatScratch),
      GIM_CheckMemoryAddressSpace, /*MI*/0, /*MMO*/0, /*NumAddrSpace*/1, /*AddrSpace*/5,
      GIM_CheckAtomicOrdering, /*MI*/0, /*Order*/(uint8_t)AtomicOrdering::NotAtomic,
      GIM_CheckPointerToAny, /*MI*/0, /*Op*/1, /*SizeInBits*/0,
      GIM_CheckComplexPattern, /*MI*/0, /*Op*/1, /*Renderer*/GIMT_Encode2(0), GIMT_Encode2(GICP_gi_mubuf_scratch_offen),
      // (st v2f16:{ *:[v2f16] }:$value, (MUBUFScratchOffen:{ *:[iPTR] } v4i32:{ *:[v4i32] }:$srsrc, i32:{ *:[i32] }:$vaddr, i32:{ *:[i32] }:$soffset, i32:{ *:[i32] }:$offset))<<P:Predicate_unindexedstore>><<P:Predicate_store_private>>  =>  (BUFFER_STORE_DWORD_VBUFFER_OFFEN VGPR_32:{ *:[v2f16] }:$value, ?:{ *:[i32] }:$vaddr, ?:{ *:[v4i32] }:$srsrc, ?:{ *:[i32] }:$soffset, ?:{ *:[i32] }:$offset, 0:{ *:[i32] }, 0:{ *:[i1] })
      GIR_BuildMI, /*InsnID*/0, /*Opcode*/GIMT_Encode2(AMDGPU::BUFFER_STORE_DWORD_VBUFFER_OFFEN),
      GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/0, // value
      GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/1, // vaddr
      GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/0, // srsrc
      GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/2, // soffset
      GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/3, // offset
      GIR_AddImm8, /*InsnID*/0, /*Imm*/0,
      GIR_AddImm8, /*InsnID*/0, /*Imm*/0,
      GIR_MergeMemOperands, /*InsnID*/0, /*NumInsns*/1, /*MergeInsnID's*/0,
      GIR_ConstrainSelectedInstOperands, /*InsnID*/0,
      GIR_EraseFromParent, /*InsnID*/0,
      // GIR_Coverage, 5527,
      GIR_Done,
    // Label 2142: @140684
    GIM_Try, /*On fail goto*//*Label 2143*/ GIMT_Encode4(140754), // Rule ID 5529 //
      GIM_CheckFeatures, GIMT_Encode2(GIFBS_DisableFlatScratch_HasUnrestrictedSOffset),
      GIM_CheckMemoryAddressSpace, /*MI*/0, /*MMO*/0, /*NumAddrSpace*/1, /*AddrSpace*/5,
      GIM_CheckAtomicOrdering, /*MI*/0, /*Order*/(uint8_t)AtomicOrdering::NotAtomic,
      GIM_CheckPointerToAny, /*MI*/0, /*Op*/1, /*SizeInBits*/0,
      GIM_CheckComplexPattern, /*MI*/0, /*Op*/1, /*Renderer*/GIMT_Encode2(0), GIMT_Encode2(GICP_gi_mubuf_scratch_offen),
      // (st v2bf16:{ *:[v2bf16] }:$value, (MUBUFScratchOffen:{ *:[iPTR] } v4i32:{ *:[v4i32] }:$srsrc, i32:{ *:[i32] }:$vaddr, i32:{ *:[i32] }:$soffset, i32:{ *:[i32] }:$offset))<<P:Predicate_unindexedstore>><<P:Predicate_store_private>>  =>  (BUFFER_STORE_DWORD_OFFEN VGPR_32:{ *:[v2bf16] }:$value, ?:{ *:[i32] }:$vaddr, ?:{ *:[v4i32] }:$srsrc, ?:{ *:[i32] }:$soffset, ?:{ *:[i32] }:$offset, 0:{ *:[i32] }, 0:{ *:[i1] })
      GIR_BuildMI, /*InsnID*/0, /*Opcode*/GIMT_Encode2(AMDGPU::BUFFER_STORE_DWORD_OFFEN),
      GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/0, // value
      GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/1, // vaddr
      GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/0, // srsrc
      GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/2, // soffset
      GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/3, // offset
      GIR_AddImm8, /*InsnID*/0, /*Imm*/0,
      GIR_AddImm8, /*InsnID*/0, /*Imm*/0,
      GIR_MergeMemOperands, /*InsnID*/0, /*NumInsns*/1, /*MergeInsnID's*/0,
      GIR_ConstrainSelectedInstOperands, /*InsnID*/0,
      GIR_EraseFromParent, /*InsnID*/0,
      // GIR_Coverage, 5529,
      GIR_Done,
    // Label 2143: @140754
    GIM_Try, /*On fail goto*//*Label 2144*/ GIMT_Encode4(140824), // Rule ID 5531 //
      GIM_CheckFeatures, GIMT_Encode2(GIFBS_DisableFlatScratch),
      GIM_CheckMemoryAddressSpace, /*MI*/0, /*MMO*/0, /*NumAddrSpace*/1, /*AddrSpace*/5,
      GIM_CheckAtomicOrdering, /*MI*/0, /*Order*/(uint8_t)AtomicOrdering::NotAtomic,
      GIM_CheckPointerToAny, /*MI*/0, /*Op*/1, /*SizeInBits*/0,
      GIM_CheckComplexPattern, /*MI*/0, /*Op*/1, /*Renderer*/GIMT_Encode2(0), GIMT_Encode2(GICP_gi_mubuf_scratch_offen),
      // (st v2bf16:{ *:[v2bf16] }:$value, (MUBUFScratchOffen:{ *:[iPTR] } v4i32:{ *:[v4i32] }:$srsrc, i32:{ *:[i32] }:$vaddr, i32:{ *:[i32] }:$soffset, i32:{ *:[i32] }:$offset))<<P:Predicate_unindexedstore>><<P:Predicate_store_private>>  =>  (BUFFER_STORE_DWORD_VBUFFER_OFFEN VGPR_32:{ *:[v2bf16] }:$value, ?:{ *:[i32] }:$vaddr, ?:{ *:[v4i32] }:$srsrc, ?:{ *:[i32] }:$soffset, ?:{ *:[i32] }:$offset, 0:{ *:[i32] }, 0:{ *:[i1] })
      GIR_BuildMI, /*InsnID*/0, /*Opcode*/GIMT_Encode2(AMDGPU::BUFFER_STORE_DWORD_VBUFFER_OFFEN),
      GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/0, // value
      GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/1, // vaddr
      GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/0, // srsrc
      GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/2, // soffset
      GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/3, // offset
      GIR_AddImm8, /*InsnID*/0, /*Imm*/0,
      GIR_AddImm8, /*InsnID*/0, /*Imm*/0,
      GIR_MergeMemOperands, /*InsnID*/0, /*NumInsns*/1, /*MergeInsnID's*/0,
      GIR_ConstrainSelectedInstOperands, /*InsnID*/0,
      GIR_EraseFromParent, /*InsnID*/0,
      // GIR_Coverage, 5531,
      GIR_Done,
    // Label 2144: @140824
    GIM_Try, /*On fail goto*//*Label 2145*/ GIMT_Encode4(140889), // Rule ID 3809 //
      GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasUnrestrictedSOffset),
      GIM_CheckMemoryAddressSpace, /*MI*/0, /*MMO*/0, /*NumAddrSpace*/1, /*AddrSpace*/1,
      GIM_CheckAtomicOrdering, /*MI*/0, /*Order*/(uint8_t)AtomicOrdering::NotAtomic,
      GIM_CheckPointerToAny, /*MI*/0, /*Op*/1, /*SizeInBits*/0,
      GIM_CheckComplexPattern, /*MI*/0, /*Op*/1, /*Renderer*/GIMT_Encode2(0), GIMT_Encode2(GICP_gi_mubuf_offset),
      // (st v2i16:{ *:[v2i16] }:$vdata, (MUBUFOffset:{ *:[iPTR] } v4i32:{ *:[v4i32] }:$srsrc, i32:{ *:[i32] }:$soffset, i32:{ *:[i32] }:$offset))<<P:Predicate_unindexedstore>><<P:Predicate_store_global>>  =>  (BUFFER_STORE_DWORD_OFFSET v2i16:{ *:[v2i16] }:$vdata, v4i32:{ *:[v4i32] }:$srsrc, i32:{ *:[i32] }:$soffset, i32:{ *:[i32] }:$offset)
      GIR_BuildMI, /*InsnID*/0, /*Opcode*/GIMT_Encode2(AMDGPU::BUFFER_STORE_DWORD_OFFSET),
      GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/0, // vdata
      GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/0, // srsrc
      GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/1, // soffset
      GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/2, // offset
      GIR_AddImm8, /*InsnID*/0, /*Imm*/0,
      GIR_AddImm8, /*InsnID*/0, /*Imm*/0,
      GIR_MergeMemOperands, /*InsnID*/0, /*NumInsns*/1, /*MergeInsnID's*/0,
      GIR_ConstrainSelectedInstOperands, /*InsnID*/0,
      GIR_EraseFromParent, /*InsnID*/0,
      // GIR_Coverage, 3809,
      GIR_Done,
    // Label 2145: @140889
    GIM_Try, /*On fail goto*//*Label 2146*/ GIMT_Encode4(140951), // Rule ID 3811 //
      GIM_CheckMemoryAddressSpace, /*MI*/0, /*MMO*/0, /*NumAddrSpace*/1, /*AddrSpace*/1,
      GIM_CheckAtomicOrdering, /*MI*/0, /*Order*/(uint8_t)AtomicOrdering::NotAtomic,
      GIM_CheckPointerToAny, /*MI*/0, /*Op*/1, /*SizeInBits*/0,
      GIM_CheckComplexPattern, /*MI*/0, /*Op*/1, /*Renderer*/GIMT_Encode2(0), GIMT_Encode2(GICP_gi_mubuf_offset),
      // (st v2i16:{ *:[v2i16] }:$vdata, (MUBUFOffset:{ *:[iPTR] } v4i32:{ *:[v4i32] }:$srsrc, i32:{ *:[i32] }:$soffset, i32:{ *:[i32] }:$offset))<<P:Predicate_unindexedstore>><<P:Predicate_store_global>>  =>  (BUFFER_STORE_DWORD_VBUFFER_OFFSET v2i16:{ *:[v2i16] }:$vdata, v4i32:{ *:[v4i32] }:$srsrc, i32:{ *:[i32] }:$soffset, i32:{ *:[i32] }:$offset)
      GIR_BuildMI, /*InsnID*/0, /*Opcode*/GIMT_Encode2(AMDGPU::BUFFER_STORE_DWORD_VBUFFER_OFFSET),
      GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/0, // vdata
      GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/0, // srsrc
      GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/1, // soffset
      GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/2, // offset
      GIR_AddImm8, /*InsnID*/0, /*Imm*/0,
      GIR_AddImm8, /*InsnID*/0, /*Imm*/0,
      GIR_MergeMemOperands, /*InsnID*/0, /*NumInsns*/1, /*MergeInsnID's*/0,
      GIR_ConstrainSelectedInstOperands, /*InsnID*/0,
      GIR_EraseFromParent, /*InsnID*/0,
      // GIR_Coverage, 3811,
      GIR_Done,
    // Label 2146: @140951
    GIM_Try, /*On fail goto*//*Label 2147*/ GIMT_Encode4(141016), // Rule ID 3813 //
      GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasUnrestrictedSOffset),
      GIM_CheckMemoryAddressSpace, /*MI*/0, /*MMO*/0, /*NumAddrSpace*/1, /*AddrSpace*/1,
      GIM_CheckAtomicOrdering, /*MI*/0, /*Order*/(uint8_t)AtomicOrdering::NotAtomic,
      GIM_CheckPointerToAny, /*MI*/0, /*Op*/1, /*SizeInBits*/0,
      GIM_CheckComplexPattern, /*MI*/0, /*Op*/1, /*Renderer*/GIMT_Encode2(0), GIMT_Encode2(GICP_gi_mubuf_offset),
      // (st v2f16:{ *:[v2f16] }:$vdata, (MUBUFOffset:{ *:[iPTR] } v4i32:{ *:[v4i32] }:$srsrc, i32:{ *:[i32] }:$soffset, i32:{ *:[i32] }:$offset))<<P:Predicate_unindexedstore>><<P:Predicate_store_global>>  =>  (BUFFER_STORE_DWORD_OFFSET v2f16:{ *:[v2f16] }:$vdata, v4i32:{ *:[v4i32] }:$srsrc, i32:{ *:[i32] }:$soffset, i32:{ *:[i32] }:$offset)
      GIR_BuildMI, /*InsnID*/0, /*Opcode*/GIMT_Encode2(AMDGPU::BUFFER_STORE_DWORD_OFFSET),
      GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/0, // vdata
      GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/0, // srsrc
      GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/1, // soffset
      GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/2, // offset
      GIR_AddImm8, /*InsnID*/0, /*Imm*/0,
      GIR_AddImm8, /*InsnID*/0, /*Imm*/0,
      GIR_MergeMemOperands, /*InsnID*/0, /*NumInsns*/1, /*MergeInsnID's*/0,
      GIR_ConstrainSelectedInstOperands, /*InsnID*/0,
      GIR_EraseFromParent, /*InsnID*/0,
      // GIR_Coverage, 3813,
      GIR_Done,
    // Label 2147: @141016
    GIM_Try, /*On fail goto*//*Label 2148*/ GIMT_Encode4(141078), // Rule ID 3815 //
      GIM_CheckMemoryAddressSpace, /*MI*/0, /*MMO*/0, /*NumAddrSpace*/1, /*AddrSpace*/1,
      GIM_CheckAtomicOrdering, /*MI*/0, /*Order*/(uint8_t)AtomicOrdering::NotAtomic,
      GIM_CheckPointerToAny, /*MI*/0, /*Op*/1, /*SizeInBits*/0,
      GIM_CheckComplexPattern, /*MI*/0, /*Op*/1, /*Renderer*/GIMT_Encode2(0), GIMT_Encode2(GICP_gi_mubuf_offset),
      // (st v2f16:{ *:[v2f16] }:$vdata, (MUBUFOffset:{ *:[iPTR] } v4i32:{ *:[v4i32] }:$srsrc, i32:{ *:[i32] }:$soffset, i32:{ *:[i32] }:$offset))<<P:Predicate_unindexedstore>><<P:Predicate_store_global>>  =>  (BUFFER_STORE_DWORD_VBUFFER_OFFSET v2f16:{ *:[v2f16] }:$vdata, v4i32:{ *:[v4i32] }:$srsrc, i32:{ *:[i32] }:$soffset, i32:{ *:[i32] }:$offset)
      GIR_BuildMI, /*InsnID*/0, /*Opcode*/GIMT_Encode2(AMDGPU::BUFFER_STORE_DWORD_VBUFFER_OFFSET),
      GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/0, // vdata
      GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/0, // srsrc
      GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/1, // soffset
      GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/2, // offset
      GIR_AddImm8, /*InsnID*/0, /*Imm*/0,
      GIR_AddImm8, /*InsnID*/0, /*Imm*/0,
      GIR_MergeMemOperands, /*InsnID*/0, /*NumInsns*/1, /*MergeInsnID's*/0,
      GIR_ConstrainSelectedInstOperands, /*InsnID*/0,
      GIR_EraseFromParent, /*InsnID*/0,
      // GIR_Coverage, 3815,
      GIR_Done,
    // Label 2148: @141078
    GIM_Try, /*On fail goto*//*Label 2149*/ GIMT_Encode4(141143), // Rule ID 3817 //
      GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasUnrestrictedSOffset),
      GIM_CheckMemoryAddressSpace, /*MI*/0, /*MMO*/0, /*NumAddrSpace*/1, /*AddrSpace*/1,
      GIM_CheckAtomicOrdering, /*MI*/0, /*Order*/(uint8_t)AtomicOrdering::NotAtomic,
      GIM_CheckPointerToAny, /*MI*/0, /*Op*/1, /*SizeInBits*/0,
      GIM_CheckComplexPattern, /*MI*/0, /*Op*/1, /*Renderer*/GIMT_Encode2(0), GIMT_Encode2(GICP_gi_mubuf_offset),
      // (st v2bf16:{ *:[v2bf16] }:$vdata, (MUBUFOffset:{ *:[iPTR] } v4i32:{ *:[v4i32] }:$srsrc, i32:{ *:[i32] }:$soffset, i32:{ *:[i32] }:$offset))<<P:Predicate_unindexedstore>><<P:Predicate_store_global>>  =>  (BUFFER_STORE_DWORD_OFFSET v2bf16:{ *:[v2bf16] }:$vdata, v4i32:{ *:[v4i32] }:$srsrc, i32:{ *:[i32] }:$soffset, i32:{ *:[i32] }:$offset)
      GIR_BuildMI, /*InsnID*/0, /*Opcode*/GIMT_Encode2(AMDGPU::BUFFER_STORE_DWORD_OFFSET),
      GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/0, // vdata
      GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/0, // srsrc
      GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/1, // soffset
      GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/2, // offset
      GIR_AddImm8, /*InsnID*/0, /*Imm*/0,
      GIR_AddImm8, /*InsnID*/0, /*Imm*/0,
      GIR_MergeMemOperands, /*InsnID*/0, /*NumInsns*/1, /*MergeInsnID's*/0,
      GIR_ConstrainSelectedInstOperands, /*InsnID*/0,
      GIR_EraseFromParent, /*InsnID*/0,
      // GIR_Coverage, 3817,
      GIR_Done,
    // Label 2149: @141143
    GIM_Try, /*On fail goto*//*Label 2150*/ GIMT_Encode4(141205), // Rule ID 3819 //
      GIM_CheckMemoryAddressSpace, /*MI*/0, /*MMO*/0, /*NumAddrSpace*/1, /*AddrSpace*/1,
      GIM_CheckAtomicOrdering, /*MI*/0, /*Order*/(uint8_t)AtomicOrdering::NotAtomic,
      GIM_CheckPointerToAny, /*MI*/0, /*Op*/1, /*SizeInBits*/0,
      GIM_CheckComplexPattern, /*MI*/0, /*Op*/1, /*Renderer*/GIMT_Encode2(0), GIMT_Encode2(GICP_gi_mubuf_offset),
      // (st v2bf16:{ *:[v2bf16] }:$vdata, (MUBUFOffset:{ *:[iPTR] } v4i32:{ *:[v4i32] }:$srsrc, i32:{ *:[i32] }:$soffset, i32:{ *:[i32] }:$offset))<<P:Predicate_unindexedstore>><<P:Predicate_store_global>>  =>  (BUFFER_STORE_DWORD_VBUFFER_OFFSET v2bf16:{ *:[v2bf16] }:$vdata, v4i32:{ *:[v4i32] }:$srsrc, i32:{ *:[i32] }:$soffset, i32:{ *:[i32] }:$offset)
      GIR_BuildMI, /*InsnID*/0, /*Opcode*/GIMT_Encode2(AMDGPU::BUFFER_STORE_DWORD_VBUFFER_OFFSET),
      GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/0, // vdata
      GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/0, // srsrc
      GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/1, // soffset
      GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/2, // offset
      GIR_AddImm8, /*InsnID*/0, /*Imm*/0,
      GIR_AddImm8, /*InsnID*/0, /*Imm*/0,
      GIR_MergeMemOperands, /*InsnID*/0, /*NumInsns*/1, /*MergeInsnID's*/0,
      GIR_ConstrainSelectedInstOperands, /*InsnID*/0,
      GIR_EraseFromParent, /*InsnID*/0,
      // GIR_Coverage, 3819,
      GIR_Done,
    // Label 2150: @141205
    GIM_Try, /*On fail goto*//*Label 2151*/ GIMT_Encode4(141266), // Rule ID 6643 //
      GIM_CheckFeatures, GIMT_Encode2(GIFBS_LDSRequiresM0Init),
      GIM_CheckMemorySizeEqualToLLT, /*MI*/0, /*MMO*/0, /*OpIdx*/0,
      GIM_CheckMemoryAddressSpace, /*MI*/0, /*MMO*/0, /*NumAddrSpace*/1, /*AddrSpace*/3,
      GIM_CheckAtomicOrdering, /*MI*/0, /*Order*/(uint8_t)AtomicOrdering::NotAtomic,
      GIM_CheckPointerToAny, /*MI*/0, /*Op*/1, /*SizeInBits*/0,
      GIM_CheckComplexPattern, /*MI*/0, /*Op*/1, /*Renderer*/GIMT_Encode2(0), GIMT_Encode2(GICP_gi_ds_1addr_1offset),
      // (AMDGPUst_glue v2i16:{ *:[v2i16] }:$value, (DS1Addr1Offset:{ *:[iPTR] } i32:{ *:[i32] }:$ptr, i32:{ *:[i32] }:$offset))<<P:Predicate_unindexedstore_glue>><<P:Predicate_store_glue>><<P:Predicate_store_local_m0>>  =>  (DS_WRITE_B32 ?:{ *:[i32] }:$ptr, anonymous_15037:{ *:[v2i16] }:$value, offset:{ *:[i32] }:$offset, 0:{ *:[i1] })
      GIR_BuildMI, /*InsnID*/0, /*Opcode*/GIMT_Encode2(AMDGPU::DS_WRITE_B32),
      GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/0, // ptr
      GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/0, // value
      GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/1, // offset
      GIR_AddImm8, /*InsnID*/0, /*Imm*/0,
      GIR_MergeMemOperands, /*InsnID*/0, /*NumInsns*/1, /*MergeInsnID's*/0,
      GIR_ConstrainSelectedInstOperands, /*InsnID*/0,
      GIR_EraseFromParent, /*InsnID*/0,
      // GIR_Coverage, 6643,
      GIR_Done,
    // Label 2151: @141266
    GIM_Try, /*On fail goto*//*Label 2152*/ GIMT_Encode4(141327), // Rule ID 6645 //
      GIM_CheckFeatures, GIMT_Encode2(GIFBS_LDSRequiresM0Init),
      GIM_CheckMemorySizeEqualToLLT, /*MI*/0, /*MMO*/0, /*OpIdx*/0,
      GIM_CheckMemoryAddressSpace, /*MI*/0, /*MMO*/0, /*NumAddrSpace*/1, /*AddrSpace*/3,
      GIM_CheckAtomicOrdering, /*MI*/0, /*Order*/(uint8_t)AtomicOrdering::NotAtomic,
      GIM_CheckPointerToAny, /*MI*/0, /*Op*/1, /*SizeInBits*/0,
      GIM_CheckComplexPattern, /*MI*/0, /*Op*/1, /*Renderer*/GIMT_Encode2(0), GIMT_Encode2(GICP_gi_ds_1addr_1offset),
      // (AMDGPUst_glue v2f16:{ *:[v2f16] }:$value, (DS1Addr1Offset:{ *:[iPTR] } i32:{ *:[i32] }:$ptr, i32:{ *:[i32] }:$offset))<<P:Predicate_unindexedstore_glue>><<P:Predicate_store_glue>><<P:Predicate_store_local_m0>>  =>  (DS_WRITE_B32 ?:{ *:[i32] }:$ptr, anonymous_15037:{ *:[v2f16] }:$value, offset:{ *:[i32] }:$offset, 0:{ *:[i1] })
      GIR_BuildMI, /*InsnID*/0, /*Opcode*/GIMT_Encode2(AMDGPU::DS_WRITE_B32),
      GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/0, // ptr
      GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/0, // value
      GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/1, // offset
      GIR_AddImm8, /*InsnID*/0, /*Imm*/0,
      GIR_MergeMemOperands, /*InsnID*/0, /*NumInsns*/1, /*MergeInsnID's*/0,
      GIR_ConstrainSelectedInstOperands, /*InsnID*/0,
      GIR_EraseFromParent, /*InsnID*/0,
      // GIR_Coverage, 6645,
      GIR_Done,
    // Label 2152: @141327
    GIM_Try, /*On fail goto*//*Label 2153*/ GIMT_Encode4(141388), // Rule ID 6647 //
      GIM_CheckFeatures, GIMT_Encode2(GIFBS_LDSRequiresM0Init),
      GIM_CheckMemorySizeEqualToLLT, /*MI*/0, /*MMO*/0, /*OpIdx*/0,
      GIM_CheckMemoryAddressSpace, /*MI*/0, /*MMO*/0, /*NumAddrSpace*/1, /*AddrSpace*/3,
      GIM_CheckAtomicOrdering, /*MI*/0, /*Order*/(uint8_t)AtomicOrdering::NotAtomic,
      GIM_CheckPointerToAny, /*MI*/0, /*Op*/1, /*SizeInBits*/0,
      GIM_CheckComplexPattern, /*MI*/0, /*Op*/1, /*Renderer*/GIMT_Encode2(0), GIMT_Encode2(GICP_gi_ds_1addr_1offset),
      // (AMDGPUst_glue v2bf16:{ *:[v2bf16] }:$value, (DS1Addr1Offset:{ *:[iPTR] } i32:{ *:[i32] }:$ptr, i32:{ *:[i32] }:$offset))<<P:Predicate_unindexedstore_glue>><<P:Predicate_store_glue>><<P:Predicate_store_local_m0>>  =>  (DS_WRITE_B32 ?:{ *:[i32] }:$ptr, anonymous_15037:{ *:[v2bf16] }:$value, offset:{ *:[i32] }:$offset, 0:{ *:[i1] })
      GIR_BuildMI, /*InsnID*/0, /*Opcode*/GIMT_Encode2(AMDGPU::DS_WRITE_B32),
      GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/0, // ptr
      GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/0, // value
      GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/1, // offset
      GIR_AddImm8, /*InsnID*/0, /*Imm*/0,
      GIR_MergeMemOperands, /*InsnID*/0, /*NumInsns*/1, /*MergeInsnID's*/0,
      GIR_ConstrainSelectedInstOperands, /*InsnID*/0,
      GIR_EraseFromParent, /*InsnID*/0,
      // GIR_Coverage, 6647,
      GIR_Done,
    // Label 2153: @141388
    GIM_Try, /*On fail goto*//*Label 2154*/ GIMT_Encode4(141445), // Rule ID 6644 //
      GIM_CheckFeatures, GIMT_Encode2(GIFBS_NotLDSRequiresM0Init),
      GIM_CheckMemoryAddressSpace, /*MI*/0, /*MMO*/0, /*NumAddrSpace*/1, /*AddrSpace*/3,
      GIM_CheckAtomicOrdering, /*MI*/0, /*Order*/(uint8_t)AtomicOrdering::NotAtomic,
      GIM_CheckPointerToAny, /*MI*/0, /*Op*/1, /*SizeInBits*/0,
      GIM_CheckComplexPattern, /*MI*/0, /*Op*/1, /*Renderer*/GIMT_Encode2(0), GIMT_Encode2(GICP_gi_ds_1addr_1offset),
      // (st v2i16:{ *:[v2i16] }:$value, (DS1Addr1Offset:{ *:[iPTR] } i32:{ *:[i32] }:$ptr, i32:{ *:[i32] }:$offset))<<P:Predicate_unindexedstore>><<P:Predicate_store_local>>  =>  (DS_WRITE_B32_gfx9 ?:{ *:[i32] }:$ptr, anonymous_15037:{ *:[v2i16] }:$value, offset:{ *:[i32] }:$offset, 0:{ *:[i1] })
      GIR_BuildMI, /*InsnID*/0, /*Opcode*/GIMT_Encode2(AMDGPU::DS_WRITE_B32_gfx9),
      GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/0, // ptr
      GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/0, // value
      GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/1, // offset
      GIR_AddImm8, /*InsnID*/0, /*Imm*/0,
      GIR_MergeMemOperands, /*InsnID*/0, /*NumInsns*/1, /*MergeInsnID's*/0,
      GIR_ConstrainSelectedInstOperands, /*InsnID*/0,
      GIR_EraseFromParent, /*InsnID*/0,
      // GIR_Coverage, 6644,
      GIR_Done,
    // Label 2154: @141445
    GIM_Try, /*On fail goto*//*Label 2155*/ GIMT_Encode4(141502), // Rule ID 6646 //
      GIM_CheckFeatures, GIMT_Encode2(GIFBS_NotLDSRequiresM0Init),
      GIM_CheckMemoryAddressSpace, /*MI*/0, /*MMO*/0, /*NumAddrSpace*/1, /*AddrSpace*/3,
      GIM_CheckAtomicOrdering, /*MI*/0, /*Order*/(uint8_t)AtomicOrdering::NotAtomic,
      GIM_CheckPointerToAny, /*MI*/0, /*Op*/1, /*SizeInBits*/0,
      GIM_CheckComplexPattern, /*MI*/0, /*Op*/1, /*Renderer*/GIMT_Encode2(0), GIMT_Encode2(GICP_gi_ds_1addr_1offset),
      // (st v2f16:{ *:[v2f16] }:$value, (DS1Addr1Offset:{ *:[iPTR] } i32:{ *:[i32] }:$ptr, i32:{ *:[i32] }:$offset))<<P:Predicate_unindexedstore>><<P:Predicate_store_local>>  =>  (DS_WRITE_B32_gfx9 ?:{ *:[i32] }:$ptr, anonymous_15037:{ *:[v2f16] }:$value, offset:{ *:[i32] }:$offset, 0:{ *:[i1] })
      GIR_BuildMI, /*InsnID*/0, /*Opcode*/GIMT_Encode2(AMDGPU::DS_WRITE_B32_gfx9),
      GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/0, // ptr
      GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/0, // value
      GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/1, // offset
      GIR_AddImm8, /*InsnID*/0, /*Imm*/0,
      GIR_MergeMemOperands, /*InsnID*/0, /*NumInsns*/1, /*MergeInsnID's*/0,
      GIR_ConstrainSelectedInstOperands, /*InsnID*/0,
      GIR_EraseFromParent, /*InsnID*/0,
      // GIR_Coverage, 6646,
      GIR_Done,
    // Label 2155: @141502
    GIM_Try, /*On fail goto*//*Label 2156*/ GIMT_Encode4(141559), // Rule ID 6648 //
      GIM_CheckFeatures, GIMT_Encode2(GIFBS_NotLDSRequiresM0Init),
      GIM_CheckMemoryAddressSpace, /*MI*/0, /*MMO*/0, /*NumAddrSpace*/1, /*AddrSpace*/3,
      GIM_CheckAtomicOrdering, /*MI*/0, /*Order*/(uint8_t)AtomicOrdering::NotAtomic,
      GIM_CheckPointerToAny, /*MI*/0, /*Op*/1, /*SizeInBits*/0,
      GIM_CheckComplexPattern, /*MI*/0, /*Op*/1, /*Renderer*/GIMT_Encode2(0), GIMT_Encode2(GICP_gi_ds_1addr_1offset),
      // (st v2bf16:{ *:[v2bf16] }:$value, (DS1Addr1Offset:{ *:[iPTR] } i32:{ *:[i32] }:$ptr, i32:{ *:[i32] }:$offset))<<P:Predicate_unindexedstore>><<P:Predicate_store_local>>  =>  (DS_WRITE_B32_gfx9 ?:{ *:[i32] }:$ptr, anonymous_15037:{ *:[v2bf16] }:$value, offset:{ *:[i32] }:$offset, 0:{ *:[i1] })
      GIR_BuildMI, /*InsnID*/0, /*Opcode*/GIMT_Encode2(AMDGPU::DS_WRITE_B32_gfx9),
      GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/0, // ptr
      GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/0, // value
      GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/1, // offset
      GIR_AddImm8, /*InsnID*/0, /*Imm*/0,
      GIR_MergeMemOperands, /*InsnID*/0, /*NumInsns*/1, /*MergeInsnID's*/0,
      GIR_ConstrainSelectedInstOperands, /*InsnID*/0,
      GIR_EraseFromParent, /*InsnID*/0,
      // GIR_Coverage, 6648,
      GIR_Done,
    // Label 2156: @141559
    GIM_Try, /*On fail goto*//*Label 2157*/ GIMT_Encode4(141621), // Rule ID 3003 //
      GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasFlatGlobalInsts),
      GIM_CheckMemoryAddressSpace, /*MI*/0, /*MMO*/0, /*NumAddrSpace*/1, /*AddrSpace*/1,
      GIM_CheckAtomicOrdering, /*MI*/0, /*Order*/(uint8_t)AtomicOrdering::NotAtomic,
      GIM_CheckPointerToAny, /*MI*/0, /*Op*/1, /*SizeInBits*/0,
      GIM_CheckComplexPattern, /*MI*/0, /*Op*/1, /*Renderer*/GIMT_Encode2(0), GIMT_Encode2(GICP_gi_global_saddr),
      // (st v2i16:{ *:[v2i16] }:$data, (GlobalSAddr:{ *:[iPTR] } SReg_64:{ *:[i64] }:$saddr, VGPR_32:{ *:[i32] }:$voffset, i32:{ *:[i32] }:$offset))<<P:Predicate_unindexedstore>><<P:Predicate_store_global>>  =>  (GLOBAL_STORE_DWORD_SADDR ?:{ *:[i32] }:$voffset, anonymous_15037:{ *:[v2i16] }:$data, ?:{ *:[i64] }:$saddr, ?:{ *:[i32] }:$offset)
      GIR_BuildMI, /*InsnID*/0, /*Opcode*/GIMT_Encode2(AMDGPU::GLOBAL_STORE_DWORD_SADDR),
      GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/1, // voffset
      GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/0, // data
      GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/0, // saddr
      GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/2, // offset
      GIR_AddImm8, /*InsnID*/0, /*Imm*/0,
      GIR_MergeMemOperands, /*InsnID*/0, /*NumInsns*/1, /*MergeInsnID's*/0,
      GIR_ConstrainSelectedInstOperands, /*InsnID*/0,
      GIR_EraseFromParent, /*InsnID*/0,
      // GIR_Coverage, 3003,
      GIR_Done,
    // Label 2157: @141621
    GIM_Try, /*On fail goto*//*Label 2158*/ GIMT_Encode4(141683), // Rule ID 3007 //
      GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasFlatGlobalInsts),
      GIM_CheckMemoryAddressSpace, /*MI*/0, /*MMO*/0, /*NumAddrSpace*/1, /*AddrSpace*/1,
      GIM_CheckAtomicOrdering, /*MI*/0, /*Order*/(uint8_t)AtomicOrdering::NotAtomic,
      GIM_CheckPointerToAny, /*MI*/0, /*Op*/1, /*SizeInBits*/0,
      GIM_CheckComplexPattern, /*MI*/0, /*Op*/1, /*Renderer*/GIMT_Encode2(0), GIMT_Encode2(GICP_gi_global_saddr),
      // (st v2f16:{ *:[v2f16] }:$data, (GlobalSAddr:{ *:[iPTR] } SReg_64:{ *:[i64] }:$saddr, VGPR_32:{ *:[i32] }:$voffset, i32:{ *:[i32] }:$offset))<<P:Predicate_unindexedstore>><<P:Predicate_store_global>>  =>  (GLOBAL_STORE_DWORD_SADDR ?:{ *:[i32] }:$voffset, anonymous_15037:{ *:[v2f16] }:$data, ?:{ *:[i64] }:$saddr, ?:{ *:[i32] }:$offset)
      GIR_BuildMI, /*InsnID*/0, /*Opcode*/GIMT_Encode2(AMDGPU::GLOBAL_STORE_DWORD_SADDR),
      GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/1, // voffset
      GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/0, // data
      GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/0, // saddr
      GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/2, // offset
      GIR_AddImm8, /*InsnID*/0, /*Imm*/0,
      GIR_MergeMemOperands, /*InsnID*/0, /*NumInsns*/1, /*MergeInsnID's*/0,
      GIR_ConstrainSelectedInstOperands, /*InsnID*/0,
      GIR_EraseFromParent, /*InsnID*/0,
      // GIR_Coverage, 3007,
      GIR_Done,
    // Label 2158: @141683
    GIM_Try, /*On fail goto*//*Label 2159*/ GIMT_Encode4(141745), // Rule ID 3011 //
      GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasFlatGlobalInsts),
      GIM_CheckMemoryAddressSpace, /*MI*/0, /*MMO*/0, /*NumAddrSpace*/1, /*AddrSpace*/1,
      GIM_CheckAtomicOrdering, /*MI*/0, /*Order*/(uint8_t)AtomicOrdering::NotAtomic,
      GIM_CheckPointerToAny, /*MI*/0, /*Op*/1, /*SizeInBits*/0,
      GIM_CheckComplexPattern, /*MI*/0, /*Op*/1, /*Renderer*/GIMT_Encode2(0), GIMT_Encode2(GICP_gi_global_saddr),
      // (st v2bf16:{ *:[v2bf16] }:$data, (GlobalSAddr:{ *:[iPTR] } SReg_64:{ *:[i64] }:$saddr, VGPR_32:{ *:[i32] }:$voffset, i32:{ *:[i32] }:$offset))<<P:Predicate_unindexedstore>><<P:Predicate_store_global>>  =>  (GLOBAL_STORE_DWORD_SADDR ?:{ *:[i32] }:$voffset, anonymous_15037:{ *:[v2bf16] }:$data, ?:{ *:[i64] }:$saddr, ?:{ *:[i32] }:$offset)
      GIR_BuildMI, /*InsnID*/0, /*Opcode*/GIMT_Encode2(AMDGPU::GLOBAL_STORE_DWORD_SADDR),
      GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/1, // voffset
      GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/0, // data
      GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/0, // saddr
      GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/2, // offset
      GIR_AddImm8, /*InsnID*/0, /*Imm*/0,
      GIR_MergeMemOperands, /*InsnID*/0, /*NumInsns*/1, /*MergeInsnID's*/0,
      GIR_ConstrainSelectedInstOperands, /*InsnID*/0,
      GIR_EraseFromParent, /*InsnID*/0,
      // GIR_Coverage, 3011,
      GIR_Done,
    // Label 2159: @141745
    GIM_Try, /*On fail goto*//*Label 2160*/ GIMT_Encode4(141802), // Rule ID 3002 //
      GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasFlatGlobalInsts),
      GIM_CheckMemoryAddressSpace, /*MI*/0, /*MMO*/0, /*NumAddrSpace*/1, /*AddrSpace*/1,
      GIM_CheckAtomicOrdering, /*MI*/0, /*Order*/(uint8_t)AtomicOrdering::NotAtomic,
      GIM_CheckPointerToAny, /*MI*/0, /*Op*/1, /*SizeInBits*/0,
      GIM_CheckComplexPattern, /*MI*/0, /*Op*/1, /*Renderer*/GIMT_Encode2(0), GIMT_Encode2(GICP_gi_global_offset),
      // (st v2i16:{ *:[v2i16] }:$data, (GlobalOffset:{ *:[iPTR] } i64:{ *:[i64] }:$vaddr, i32:{ *:[i32] }:$offset))<<P:Predicate_unindexedstore>><<P:Predicate_store_global>>  =>  (GLOBAL_STORE_DWORD ?:{ *:[i64] }:$vaddr, anonymous_15037:{ *:[v2i16] }:$data, ?:{ *:[i32] }:$offset)
      GIR_BuildMI, /*InsnID*/0, /*Opcode*/GIMT_Encode2(AMDGPU::GLOBAL_STORE_DWORD),
      GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/0, // vaddr
      GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/0, // data
      GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/1, // offset
      GIR_AddImm8, /*InsnID*/0, /*Imm*/0,
      GIR_MergeMemOperands, /*InsnID*/0, /*NumInsns*/1, /*MergeInsnID's*/0,
      GIR_ConstrainSelectedInstOperands, /*InsnID*/0,
      GIR_EraseFromParent, /*InsnID*/0,
      // GIR_Coverage, 3002,
      GIR_Done,
    // Label 2160: @141802
    GIM_Try, /*On fail goto*//*Label 2161*/ GIMT_Encode4(141859), // Rule ID 3006 //
      GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasFlatGlobalInsts),
      GIM_CheckMemoryAddressSpace, /*MI*/0, /*MMO*/0, /*NumAddrSpace*/1, /*AddrSpace*/1,
      GIM_CheckAtomicOrdering, /*MI*/0, /*Order*/(uint8_t)AtomicOrdering::NotAtomic,
      GIM_CheckPointerToAny, /*MI*/0, /*Op*/1, /*SizeInBits*/0,
      GIM_CheckComplexPattern, /*MI*/0, /*Op*/1, /*Renderer*/GIMT_Encode2(0), GIMT_Encode2(GICP_gi_global_offset),
      // (st v2f16:{ *:[v2f16] }:$data, (GlobalOffset:{ *:[iPTR] } i64:{ *:[i64] }:$vaddr, i32:{ *:[i32] }:$offset))<<P:Predicate_unindexedstore>><<P:Predicate_store_global>>  =>  (GLOBAL_STORE_DWORD ?:{ *:[i64] }:$vaddr, anonymous_15037:{ *:[v2f16] }:$data, ?:{ *:[i32] }:$offset)
      GIR_BuildMI, /*InsnID*/0, /*Opcode*/GIMT_Encode2(AMDGPU::GLOBAL_STORE_DWORD),
      GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/0, // vaddr
      GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/0, // data
      GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/1, // offset
      GIR_AddImm8, /*InsnID*/0, /*Imm*/0,
      GIR_MergeMemOperands, /*InsnID*/0, /*NumInsns*/1, /*MergeInsnID's*/0,
      GIR_ConstrainSelectedInstOperands, /*InsnID*/0,
      GIR_EraseFromParent, /*InsnID*/0,
      // GIR_Coverage, 3006,
      GIR_Done,
    // Label 2161: @141859
    GIM_Try, /*On fail goto*//*Label 2162*/ GIMT_Encode4(141916), // Rule ID 3010 //
      GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasFlatGlobalInsts),
      GIM_CheckMemoryAddressSpace, /*MI*/0, /*MMO*/0, /*NumAddrSpace*/1, /*AddrSpace*/1,
      GIM_CheckAtomicOrdering, /*MI*/0, /*Order*/(uint8_t)AtomicOrdering::NotAtomic,
      GIM_CheckPointerToAny, /*MI*/0, /*Op*/1, /*SizeInBits*/0,
      GIM_CheckComplexPattern, /*MI*/0, /*Op*/1, /*Renderer*/GIMT_Encode2(0), GIMT_Encode2(GICP_gi_global_offset),
      // (st v2bf16:{ *:[v2bf16] }:$data, (GlobalOffset:{ *:[iPTR] } i64:{ *:[i64] }:$vaddr, i32:{ *:[i32] }:$offset))<<P:Predicate_unindexedstore>><<P:Predicate_store_global>>  =>  (GLOBAL_STORE_DWORD ?:{ *:[i64] }:$vaddr, anonymous_15037:{ *:[v2bf16] }:$data, ?:{ *:[i32] }:$offset)
      GIR_BuildMI, /*InsnID*/0, /*Opcode*/GIMT_Encode2(AMDGPU::GLOBAL_STORE_DWORD),
      GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/0, // vaddr
      GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/0, // data
      GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/1, // offset
      GIR_AddImm8, /*InsnID*/0, /*Imm*/0,
      GIR_MergeMemOperands, /*InsnID*/0, /*NumInsns*/1, /*MergeInsnID's*/0,
      GIR_ConstrainSelectedInstOperands, /*InsnID*/0,
      GIR_EraseFromParent, /*InsnID*/0,
      // GIR_Coverage, 3010,
      GIR_Done,
    // Label 2162: @141916
    GIM_Try, /*On fail goto*//*Label 2163*/ GIMT_Encode4(141974), // Rule ID 2775 //
      GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasFlatAddressSpace),
      GIM_CheckMemoryAddressSpace, /*MI*/0, /*MMO*/0, /*NumAddrSpace*/2, /*AddrSpace*/0, /*AddrSpace*/1,
      GIM_CheckAtomicOrdering, /*MI*/0, /*Order*/(uint8_t)AtomicOrdering::NotAtomic,
      GIM_CheckPointerToAny, /*MI*/0, /*Op*/1, /*SizeInBits*/0,
      GIM_CheckComplexPattern, /*MI*/0, /*Op*/1, /*Renderer*/GIMT_Encode2(0), GIMT_Encode2(GICP_gi_flat_offset),
      // (st v2i16:{ *:[v2i16] }:$data, (FlatOffset:{ *:[iPTR] } i64:{ *:[i64] }:$vaddr, i32:{ *:[i32] }:$offset))<<P:Predicate_unindexedstore>><<P:Predicate_store_flat>>  =>  (FLAT_STORE_DWORD ?:{ *:[i64] }:$vaddr, anonymous_15037:{ *:[v2i16] }:$data, ?:{ *:[i32] }:$offset)
      GIR_BuildMI, /*InsnID*/0, /*Opcode*/GIMT_Encode2(AMDGPU::FLAT_STORE_DWORD),
      GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/0, // vaddr
      GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/0, // data
      GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/1, // offset
      GIR_AddImm8, /*InsnID*/0, /*Imm*/0,
      GIR_MergeMemOperands, /*InsnID*/0, /*NumInsns*/1, /*MergeInsnID's*/0,
      GIR_ConstrainSelectedInstOperands, /*InsnID*/0,
      GIR_EraseFromParent, /*InsnID*/0,
      // GIR_Coverage, 2775,
      GIR_Done,
    // Label 2163: @141974
    GIM_Try, /*On fail goto*//*Label 2164*/ GIMT_Encode4(142032), // Rule ID 2777 //
      GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasFlatAddressSpace),
      GIM_CheckMemoryAddressSpace, /*MI*/0, /*MMO*/0, /*NumAddrSpace*/2, /*AddrSpace*/0, /*AddrSpace*/1,
      GIM_CheckAtomicOrdering, /*MI*/0, /*Order*/(uint8_t)AtomicOrdering::NotAtomic,
      GIM_CheckPointerToAny, /*MI*/0, /*Op*/1, /*SizeInBits*/0,
      GIM_CheckComplexPattern, /*MI*/0, /*Op*/1, /*Renderer*/GIMT_Encode2(0), GIMT_Encode2(GICP_gi_flat_offset),
      // (st v2f16:{ *:[v2f16] }:$data, (FlatOffset:{ *:[iPTR] } i64:{ *:[i64] }:$vaddr, i32:{ *:[i32] }:$offset))<<P:Predicate_unindexedstore>><<P:Predicate_store_flat>>  =>  (FLAT_STORE_DWORD ?:{ *:[i64] }:$vaddr, anonymous_15037:{ *:[v2f16] }:$data, ?:{ *:[i32] }:$offset)
      GIR_BuildMI, /*InsnID*/0, /*Opcode*/GIMT_Encode2(AMDGPU::FLAT_STORE_DWORD),
      GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/0, // vaddr
      GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/0, // data
      GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/1, // offset
      GIR_AddImm8, /*InsnID*/0, /*Imm*/0,
      GIR_MergeMemOperands, /*InsnID*/0, /*NumInsns*/1, /*MergeInsnID's*/0,
      GIR_ConstrainSelectedInstOperands, /*InsnID*/0,
      GIR_EraseFromParent, /*InsnID*/0,
      // GIR_Coverage, 2777,
      GIR_Done,
    // Label 2164: @142032
    GIM_Try, /*On fail goto*//*Label 2165*/ GIMT_Encode4(142090), // Rule ID 2779 //
      GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasFlatAddressSpace),
      GIM_CheckMemoryAddressSpace, /*MI*/0, /*MMO*/0, /*NumAddrSpace*/2, /*AddrSpace*/0, /*AddrSpace*/1,
      GIM_CheckAtomicOrdering, /*MI*/0, /*Order*/(uint8_t)AtomicOrdering::NotAtomic,
      GIM_CheckPointerToAny, /*MI*/0, /*Op*/1, /*SizeInBits*/0,
      GIM_CheckComplexPattern, /*MI*/0, /*Op*/1, /*Renderer*/GIMT_Encode2(0), GIMT_Encode2(GICP_gi_flat_offset),
      // (st v2bf16:{ *:[v2bf16] }:$data, (FlatOffset:{ *:[iPTR] } i64:{ *:[i64] }:$vaddr, i32:{ *:[i32] }:$offset))<<P:Predicate_unindexedstore>><<P:Predicate_store_flat>>  =>  (FLAT_STORE_DWORD ?:{ *:[i64] }:$vaddr, anonymous_15037:{ *:[v2bf16] }:$data, ?:{ *:[i32] }:$offset)
      GIR_BuildMI, /*InsnID*/0, /*Opcode*/GIMT_Encode2(AMDGPU::FLAT_STORE_DWORD),
      GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/0, // vaddr
      GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/0, // data
      GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/1, // offset
      GIR_AddImm8, /*InsnID*/0, /*Imm*/0,
      GIR_MergeMemOperands, /*InsnID*/0, /*NumInsns*/1, /*MergeInsnID's*/0,
      GIR_ConstrainSelectedInstOperands, /*InsnID*/0,
      GIR_EraseFromParent, /*InsnID*/0,
      // GIR_Coverage, 2779,
      GIR_Done,
    // Label 2165: @142090
    GIM_Reject,
    // Label 1817: @142091
    GIM_Try, /*On fail goto*//*Label 2166*/ GIMT_Encode4(142161), // Rule ID 6825 //
      GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasUnalignedAccessMode_LDSRequiresM0Init),
      GIM_CheckMemorySizeEqualToLLT, /*MI*/0, /*MMO*/0, /*OpIdx*/0,
      GIM_CheckMemoryAddressSpace, /*MI*/0, /*MMO*/0, /*NumAddrSpace*/1, /*AddrSpace*/3,
      GIM_CheckMemoryAddressSpace, /*MI*/0, /*MMO*/0, /*NumAddrSpace*/1, /*AddrSpace*/3,
      GIM_CheckAtomicOrdering, /*MI*/0, /*Order*/(uint8_t)AtomicOrdering::NotAtomic,
      GIM_CheckPointerToAny, /*MI*/0, /*Op*/1, /*SizeInBits*/0,
      GIM_CheckCxxInsnPredicate, /*MI*/0, /*FnId*/GIMT_Encode2(GICXXPred_MI_Predicate_store_align_less_than_4_local_m0),
      GIM_CheckComplexPattern, /*MI*/0, /*Op*/1, /*Renderer*/GIMT_Encode2(0), GIMT_Encode2(GICP_gi_ds_1addr_1offset),
      // (AMDGPUst_glue v2i32:{ *:[v2i32] }:$value, (DS1Addr1Offset:{ *:[iPTR] } i32:{ *:[i32] }:$ptr, i32:{ *:[i32] }:$offset))<<P:Predicate_unindexedstore_glue>><<P:Predicate_store_glue>><<P:Predicate_store_local_m0>><<P:Predicate_store_align_less_than_4_local_m0>>  =>  (DS_WRITE_B64 ?:{ *:[i32] }:$ptr, anonymous_15036:{ *:[v2i32] }:$value, offset:{ *:[i32] }:$offset, 0:{ *:[i1] })
      GIR_BuildMI, /*InsnID*/0, /*Opcode*/GIMT_Encode2(AMDGPU::DS_WRITE_B64),
      GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/0, // ptr
      GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/0, // value
      GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/1, // offset
      GIR_AddImm8, /*InsnID*/0, /*Imm*/0,
      GIR_MergeMemOperands, /*InsnID*/0, /*NumInsns*/1, /*MergeInsnID's*/0,
      GIR_ConstrainSelectedInstOperands, /*InsnID*/0,
      GIR_EraseFromParent, /*InsnID*/0,
      // GIR_Coverage, 6825,
      GIR_Done,
    // Label 2166: @142161
    GIM_Try, /*On fail goto*//*Label 2167*/ GIMT_Encode4(142231), // Rule ID 6829 //
      GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasUnalignedAccessMode_LDSRequiresM0Init),
      GIM_CheckMemorySizeEqualToLLT, /*MI*/0, /*MMO*/0, /*OpIdx*/0,
      GIM_CheckMemoryAddressSpace, /*MI*/0, /*MMO*/0, /*NumAddrSpace*/1, /*AddrSpace*/3,
      GIM_CheckMemoryAddressSpace, /*MI*/0, /*MMO*/0, /*NumAddrSpace*/1, /*AddrSpace*/3,
      GIM_CheckAtomicOrdering, /*MI*/0, /*Order*/(uint8_t)AtomicOrdering::NotAtomic,
      GIM_CheckPointerToAny, /*MI*/0, /*Op*/1, /*SizeInBits*/0,
      GIM_CheckCxxInsnPredicate, /*MI*/0, /*FnId*/GIMT_Encode2(GICXXPred_MI_Predicate_store_align_less_than_4_local_m0),
      GIM_CheckComplexPattern, /*MI*/0, /*Op*/1, /*Renderer*/GIMT_Encode2(0), GIMT_Encode2(GICP_gi_ds_1addr_1offset),
      // (AMDGPUst_glue v2f32:{ *:[v2f32] }:$value, (DS1Addr1Offset:{ *:[iPTR] } i32:{ *:[i32] }:$ptr, i32:{ *:[i32] }:$offset))<<P:Predicate_unindexedstore_glue>><<P:Predicate_store_glue>><<P:Predicate_store_local_m0>><<P:Predicate_store_align_less_than_4_local_m0>>  =>  (DS_WRITE_B64 ?:{ *:[i32] }:$ptr, anonymous_15036:{ *:[v2f32] }:$value, offset:{ *:[i32] }:$offset, 0:{ *:[i1] })
      GIR_BuildMI, /*InsnID*/0, /*Opcode*/GIMT_Encode2(AMDGPU::DS_WRITE_B64),
      GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/0, // ptr
      GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/0, // value
      GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/1, // offset
      GIR_AddImm8, /*InsnID*/0, /*Imm*/0,
      GIR_MergeMemOperands, /*InsnID*/0, /*NumInsns*/1, /*MergeInsnID's*/0,
      GIR_ConstrainSelectedInstOperands, /*InsnID*/0,
      GIR_EraseFromParent, /*InsnID*/0,
      // GIR_Coverage, 6829,
      GIR_Done,
    // Label 2167: @142231
    GIM_Try, /*On fail goto*//*Label 2168*/ GIMT_Encode4(142296), // Rule ID 6749 //
      GIM_CheckFeatures, GIMT_Encode2(GIFBS_LDSRequiresM0Init),
      GIM_CheckMemorySizeEqualToLLT, /*MI*/0, /*MMO*/0, /*OpIdx*/0,
      GIM_CheckMemoryAddressSpace, /*MI*/0, /*MMO*/0, /*NumAddrSpace*/1, /*AddrSpace*/3,
      GIM_CheckMemoryAlignment, /*MI*/0, /*MMO*/0, /*MinAlign*/8,
      GIM_CheckAtomicOrdering, /*MI*/0, /*Order*/(uint8_t)AtomicOrdering::NotAtomic,
      GIM_CheckPointerToAny, /*MI*/0, /*Op*/1, /*SizeInBits*/0,
      GIM_CheckComplexPattern, /*MI*/0, /*Op*/1, /*Renderer*/GIMT_Encode2(0), GIMT_Encode2(GICP_gi_ds_1addr_1offset),
      // (AMDGPUst_glue v2i32:{ *:[v2i32] }:$value, (DS1Addr1Offset:{ *:[iPTR] } i32:{ *:[i32] }:$ptr, i32:{ *:[i32] }:$offset))<<P:Predicate_unindexedstore_glue>><<P:Predicate_store_glue>><<P:Predicate_store_local_m0>><<P:Predicate_store_align8_local_m0>>  =>  (DS_WRITE_B64 ?:{ *:[i32] }:$ptr, anonymous_15036:{ *:[v2i32] }:$value, offset:{ *:[i32] }:$offset, 0:{ *:[i1] })
      GIR_BuildMI, /*InsnID*/0, /*Opcode*/GIMT_Encode2(AMDGPU::DS_WRITE_B64),
      GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/0, // ptr
      GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/0, // value
      GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/1, // offset
      GIR_AddImm8, /*InsnID*/0, /*Imm*/0,
      GIR_MergeMemOperands, /*InsnID*/0, /*NumInsns*/1, /*MergeInsnID's*/0,
      GIR_ConstrainSelectedInstOperands, /*InsnID*/0,
      GIR_EraseFromParent, /*InsnID*/0,
      // GIR_Coverage, 6749,
      GIR_Done,
    // Label 2168: @142296
    GIM_Try, /*On fail goto*//*Label 2169*/ GIMT_Encode4(142361), // Rule ID 6753 //
      GIM_CheckFeatures, GIMT_Encode2(GIFBS_LDSRequiresM0Init),
      GIM_CheckMemorySizeEqualToLLT, /*MI*/0, /*MMO*/0, /*OpIdx*/0,
      GIM_CheckMemoryAddressSpace, /*MI*/0, /*MMO*/0, /*NumAddrSpace*/1, /*AddrSpace*/3,
      GIM_CheckMemoryAlignment, /*MI*/0, /*MMO*/0, /*MinAlign*/8,
      GIM_CheckAtomicOrdering, /*MI*/0, /*Order*/(uint8_t)AtomicOrdering::NotAtomic,
      GIM_CheckPointerToAny, /*MI*/0, /*Op*/1, /*SizeInBits*/0,
      GIM_CheckComplexPattern, /*MI*/0, /*Op*/1, /*Renderer*/GIMT_Encode2(0), GIMT_Encode2(GICP_gi_ds_1addr_1offset),
      // (AMDGPUst_glue v2f32:{ *:[v2f32] }:$value, (DS1Addr1Offset:{ *:[iPTR] } i32:{ *:[i32] }:$ptr, i32:{ *:[i32] }:$offset))<<P:Predicate_unindexedstore_glue>><<P:Predicate_store_glue>><<P:Predicate_store_local_m0>><<P:Predicate_store_align8_local_m0>>  =>  (DS_WRITE_B64 ?:{ *:[i32] }:$ptr, anonymous_15036:{ *:[v2f32] }:$value, offset:{ *:[i32] }:$offset, 0:{ *:[i1] })
      GIR_BuildMI, /*InsnID*/0, /*Opcode*/GIMT_Encode2(AMDGPU::DS_WRITE_B64),
      GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/0, // ptr
      GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/0, // value
      GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/1, // offset
      GIR_AddImm8, /*InsnID*/0, /*Imm*/0,
      GIR_MergeMemOperands, /*InsnID*/0, /*NumInsns*/1, /*MergeInsnID's*/0,
      GIR_ConstrainSelectedInstOperands, /*InsnID*/0,
      GIR_EraseFromParent, /*InsnID*/0,
      // GIR_Coverage, 6753,
      GIR_Done,
    // Label 2169: @142361
    GIM_Try, /*On fail goto*//*Label 2170*/ GIMT_Encode4(142427), // Rule ID 6826 //
      GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasUnalignedAccessMode_NotLDSRequiresM0Init),
      GIM_CheckMemoryAddressSpace, /*MI*/0, /*MMO*/0, /*NumAddrSpace*/1, /*AddrSpace*/3,
      GIM_CheckMemoryAddressSpace, /*MI*/0, /*MMO*/0, /*NumAddrSpace*/1, /*AddrSpace*/3,
      GIM_CheckAtomicOrdering, /*MI*/0, /*Order*/(uint8_t)AtomicOrdering::NotAtomic,
      GIM_CheckPointerToAny, /*MI*/0, /*Op*/1, /*SizeInBits*/0,
      GIM_CheckCxxInsnPredicate, /*MI*/0, /*FnId*/GIMT_Encode2(GICXXPred_MI_Predicate_store_align_less_than_4_local),
      GIM_CheckComplexPattern, /*MI*/0, /*Op*/1, /*Renderer*/GIMT_Encode2(0), GIMT_Encode2(GICP_gi_ds_1addr_1offset),
      // (st v2i32:{ *:[v2i32] }:$value, (DS1Addr1Offset:{ *:[iPTR] } i32:{ *:[i32] }:$ptr, i32:{ *:[i32] }:$offset))<<P:Predicate_unindexedstore>><<P:Predicate_store_local>><<P:Predicate_store_align_less_than_4_local>>  =>  (DS_WRITE_B64_gfx9 ?:{ *:[i32] }:$ptr, anonymous_15036:{ *:[v2i32] }:$value, offset:{ *:[i32] }:$offset, 0:{ *:[i1] })
      GIR_BuildMI, /*InsnID*/0, /*Opcode*/GIMT_Encode2(AMDGPU::DS_WRITE_B64_gfx9),
      GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/0, // ptr
      GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/0, // value
      GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/1, // offset
      GIR_AddImm8, /*InsnID*/0, /*Imm*/0,
      GIR_MergeMemOperands, /*InsnID*/0, /*NumInsns*/1, /*MergeInsnID's*/0,
      GIR_ConstrainSelectedInstOperands, /*InsnID*/0,
      GIR_EraseFromParent, /*InsnID*/0,
      // GIR_Coverage, 6826,
      GIR_Done,
    // Label 2170: @142427
    GIM_Try, /*On fail goto*//*Label 2171*/ GIMT_Encode4(142493), // Rule ID 6830 //
      GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasUnalignedAccessMode_NotLDSRequiresM0Init),
      GIM_CheckMemoryAddressSpace, /*MI*/0, /*MMO*/0, /*NumAddrSpace*/1, /*AddrSpace*/3,
      GIM_CheckMemoryAddressSpace, /*MI*/0, /*MMO*/0, /*NumAddrSpace*/1, /*AddrSpace*/3,
      GIM_CheckAtomicOrdering, /*MI*/0, /*Order*/(uint8_t)AtomicOrdering::NotAtomic,
      GIM_CheckPointerToAny, /*MI*/0, /*Op*/1, /*SizeInBits*/0,
      GIM_CheckCxxInsnPredicate, /*MI*/0, /*FnId*/GIMT_Encode2(GICXXPred_MI_Predicate_store_align_less_than_4_local),
      GIM_CheckComplexPattern, /*MI*/0, /*Op*/1, /*Renderer*/GIMT_Encode2(0), GIMT_Encode2(GICP_gi_ds_1addr_1offset),
      // (st v2f32:{ *:[v2f32] }:$value, (DS1Addr1Offset:{ *:[iPTR] } i32:{ *:[i32] }:$ptr, i32:{ *:[i32] }:$offset))<<P:Predicate_unindexedstore>><<P:Predicate_store_local>><<P:Predicate_store_align_less_than_4_local>>  =>  (DS_WRITE_B64_gfx9 ?:{ *:[i32] }:$ptr, anonymous_15036:{ *:[v2f32] }:$value, offset:{ *:[i32] }:$offset, 0:{ *:[i1] })
      GIR_BuildMI, /*InsnID*/0, /*Opcode*/GIMT_Encode2(AMDGPU::DS_WRITE_B64_gfx9),
      GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/0, // ptr
      GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/0, // value
      GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/1, // offset
      GIR_AddImm8, /*InsnID*/0, /*Imm*/0,
      GIR_MergeMemOperands, /*InsnID*/0, /*NumInsns*/1, /*MergeInsnID's*/0,
      GIR_ConstrainSelectedInstOperands, /*InsnID*/0,
      GIR_EraseFromParent, /*InsnID*/0,
      // GIR_Coverage, 6830,
      GIR_Done,
    // Label 2171: @142493
    GIM_Try, /*On fail goto*//*Label 2172*/ GIMT_Encode4(142554), // Rule ID 6750 //
      GIM_CheckFeatures, GIMT_Encode2(GIFBS_NotLDSRequiresM0Init),
      GIM_CheckMemoryAddressSpace, /*MI*/0, /*MMO*/0, /*NumAddrSpace*/1, /*AddrSpace*/3,
      GIM_CheckMemoryAlignment, /*MI*/0, /*MMO*/0, /*MinAlign*/8,
      GIM_CheckAtomicOrdering, /*MI*/0, /*Order*/(uint8_t)AtomicOrdering::NotAtomic,
      GIM_CheckPointerToAny, /*MI*/0, /*Op*/1, /*SizeInBits*/0,
      GIM_CheckComplexPattern, /*MI*/0, /*Op*/1, /*Renderer*/GIMT_Encode2(0), GIMT_Encode2(GICP_gi_ds_1addr_1offset),
      // (st v2i32:{ *:[v2i32] }:$value, (DS1Addr1Offset:{ *:[iPTR] } i32:{ *:[i32] }:$ptr, i32:{ *:[i32] }:$offset))<<P:Predicate_unindexedstore>><<P:Predicate_store_local>><<P:Predicate_store_align8_local>>  =>  (DS_WRITE_B64_gfx9 ?:{ *:[i32] }:$ptr, anonymous_15036:{ *:[v2i32] }:$value, offset:{ *:[i32] }:$offset, 0:{ *:[i1] })
      GIR_BuildMI, /*InsnID*/0, /*Opcode*/GIMT_Encode2(AMDGPU::DS_WRITE_B64_gfx9),
      GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/0, // ptr
      GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/0, // value
      GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/1, // offset
      GIR_AddImm8, /*InsnID*/0, /*Imm*/0,
      GIR_MergeMemOperands, /*InsnID*/0, /*NumInsns*/1, /*MergeInsnID's*/0,
      GIR_ConstrainSelectedInstOperands, /*InsnID*/0,
      GIR_EraseFromParent, /*InsnID*/0,
      // GIR_Coverage, 6750,
      GIR_Done,
    // Label 2172: @142554
    GIM_Try, /*On fail goto*//*Label 2173*/ GIMT_Encode4(142615), // Rule ID 6754 //
      GIM_CheckFeatures, GIMT_Encode2(GIFBS_NotLDSRequiresM0Init),
      GIM_CheckMemoryAddressSpace, /*MI*/0, /*MMO*/0, /*NumAddrSpace*/1, /*AddrSpace*/3,
      GIM_CheckMemoryAlignment, /*MI*/0, /*MMO*/0, /*MinAlign*/8,
      GIM_CheckAtomicOrdering, /*MI*/0, /*Order*/(uint8_t)AtomicOrdering::NotAtomic,
      GIM_CheckPointerToAny, /*MI*/0, /*Op*/1, /*SizeInBits*/0,
      GIM_CheckComplexPattern, /*MI*/0, /*Op*/1, /*Renderer*/GIMT_Encode2(0), GIMT_Encode2(GICP_gi_ds_1addr_1offset),
      // (st v2f32:{ *:[v2f32] }:$value, (DS1Addr1Offset:{ *:[iPTR] } i32:{ *:[i32] }:$ptr, i32:{ *:[i32] }:$offset))<<P:Predicate_unindexedstore>><<P:Predicate_store_local>><<P:Predicate_store_align8_local>>  =>  (DS_WRITE_B64_gfx9 ?:{ *:[i32] }:$ptr, anonymous_15036:{ *:[v2f32] }:$value, offset:{ *:[i32] }:$offset, 0:{ *:[i1] })
      GIR_BuildMI, /*InsnID*/0, /*Opcode*/GIMT_Encode2(AMDGPU::DS_WRITE_B64_gfx9),
      GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/0, // ptr
      GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/0, // value
      GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/1, // offset
      GIR_AddImm8, /*InsnID*/0, /*Imm*/0,
      GIR_MergeMemOperands, /*InsnID*/0, /*NumInsns*/1, /*MergeInsnID's*/0,
      GIR_ConstrainSelectedInstOperands, /*InsnID*/0,
      GIR_EraseFromParent, /*InsnID*/0,
      // GIR_Coverage, 6754,
      GIR_Done,
    // Label 2173: @142615
    GIM_Try, /*On fail goto*//*Label 2174*/ GIMT_Encode4(142680), // Rule ID 5550 //
      GIM_CheckFeatures, GIMT_Encode2(GIFBS_DisableFlatScratch_HasUnrestrictedSOffset),
      GIM_CheckMemoryAddressSpace, /*MI*/0, /*MMO*/0, /*NumAddrSpace*/1, /*AddrSpace*/5,
      GIM_CheckAtomicOrdering, /*MI*/0, /*Order*/(uint8_t)AtomicOrdering::NotAtomic,
      GIM_CheckPointerToAny, /*MI*/0, /*Op*/1, /*SizeInBits*/0,
      GIM_CheckComplexPattern, /*MI*/0, /*Op*/1, /*Renderer*/GIMT_Encode2(0), GIMT_Encode2(GICP_gi_mubuf_scratch_offset),
      // (st v2i32:{ *:[v2i32] }:$value, (MUBUFScratchOffset:{ *:[iPTR] } v4i32:{ *:[v4i32] }:$srsrc, i32:{ *:[i32] }:$soffset, i32:{ *:[i32] }:$offset))<<P:Predicate_unindexedstore>><<P:Predicate_store_private>>  =>  (BUFFER_STORE_DWORDX2_OFFSET VReg_64:{ *:[v2i32] }:$value, ?:{ *:[v4i32] }:$srsrc, ?:{ *:[i32] }:$soffset, ?:{ *:[i32] }:$offset, 0:{ *:[i32] }, 0:{ *:[i1] })
      GIR_BuildMI, /*InsnID*/0, /*Opcode*/GIMT_Encode2(AMDGPU::BUFFER_STORE_DWORDX2_OFFSET),
      GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/0, // value
      GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/0, // srsrc
      GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/1, // soffset
      GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/2, // offset
      GIR_AddImm8, /*InsnID*/0, /*Imm*/0,
      GIR_AddImm8, /*InsnID*/0, /*Imm*/0,
      GIR_MergeMemOperands, /*InsnID*/0, /*NumInsns*/1, /*MergeInsnID's*/0,
      GIR_ConstrainSelectedInstOperands, /*InsnID*/0,
      GIR_EraseFromParent, /*InsnID*/0,
      // GIR_Coverage, 5550,
      GIR_Done,
    // Label 2174: @142680
    GIM_Try, /*On fail goto*//*Label 2175*/ GIMT_Encode4(142745), // Rule ID 5552 //
      GIM_CheckFeatures, GIMT_Encode2(GIFBS_DisableFlatScratch),
      GIM_CheckMemoryAddressSpace, /*MI*/0, /*MMO*/0, /*NumAddrSpace*/1, /*AddrSpace*/5,
      GIM_CheckAtomicOrdering, /*MI*/0, /*Order*/(uint8_t)AtomicOrdering::NotAtomic,
      GIM_CheckPointerToAny, /*MI*/0, /*Op*/1, /*SizeInBits*/0,
      GIM_CheckComplexPattern, /*MI*/0, /*Op*/1, /*Renderer*/GIMT_Encode2(0), GIMT_Encode2(GICP_gi_mubuf_scratch_offset),
      // (st v2i32:{ *:[v2i32] }:$value, (MUBUFScratchOffset:{ *:[iPTR] } v4i32:{ *:[v4i32] }:$srsrc, i32:{ *:[i32] }:$soffset, i32:{ *:[i32] }:$offset))<<P:Predicate_unindexedstore>><<P:Predicate_store_private>>  =>  (BUFFER_STORE_DWORDX2_VBUFFER_OFFSET VReg_64:{ *:[v2i32] }:$value, ?:{ *:[v4i32] }:$srsrc, ?:{ *:[i32] }:$soffset, ?:{ *:[i32] }:$offset, 0:{ *:[i32] }, 0:{ *:[i1] })
      GIR_BuildMI, /*InsnID*/0, /*Opcode*/GIMT_Encode2(AMDGPU::BUFFER_STORE_DWORDX2_VBUFFER_OFFSET),
      GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/0, // value
      GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/0, // srsrc
      GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/1, // soffset
      GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/2, // offset
      GIR_AddImm8, /*InsnID*/0, /*Imm*/0,
      GIR_AddImm8, /*InsnID*/0, /*Imm*/0,
      GIR_MergeMemOperands, /*InsnID*/0, /*NumInsns*/1, /*MergeInsnID's*/0,
      GIR_ConstrainSelectedInstOperands, /*InsnID*/0,
      GIR_EraseFromParent, /*InsnID*/0,
      // GIR_Coverage, 5552,
      GIR_Done,
    // Label 2175: @142745
    GIM_Try, /*On fail goto*//*Label 2176*/ GIMT_Encode4(142807), // Rule ID 3499 //
      GIM_CheckFeatures, GIMT_Encode2(GIFBS_EnableFlatScratch_HasFlatScratchInsts_HasFlatScratchSVSMode),
      GIM_CheckMemoryAddressSpace, /*MI*/0, /*MMO*/0, /*NumAddrSpace*/1, /*AddrSpace*/5,
      GIM_CheckAtomicOrdering, /*MI*/0, /*Order*/(uint8_t)AtomicOrdering::NotAtomic,
      GIM_CheckPointerToAny, /*MI*/0, /*Op*/1, /*SizeInBits*/0,
      GIM_CheckComplexPattern, /*MI*/0, /*Op*/1, /*Renderer*/GIMT_Encode2(0), GIMT_Encode2(GICP_gi_flat_scratch_svaddr),
      // (st v2i32:{ *:[v2i32] }:$data, (ScratchSVAddr:{ *:[iPTR] } VGPR_32:{ *:[i32] }:$vaddr, SGPR_32:{ *:[i32] }:$saddr, i32:{ *:[i32] }:$offset))<<P:Predicate_unindexedstore>><<P:Predicate_store_private>>  =>  (SCRATCH_STORE_DWORDX2_SVS anonymous_15036:{ *:[v2i32] }:$data, ?:{ *:[i32] }:$vaddr, ?:{ *:[i32] }:$saddr, ?:{ *:[i32] }:$offset)
      GIR_BuildMI, /*InsnID*/0, /*Opcode*/GIMT_Encode2(AMDGPU::SCRATCH_STORE_DWORDX2_SVS),
      GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/0, // data
      GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/0, // vaddr
      GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/1, // saddr
      GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/2, // offset
      GIR_AddImm8, /*InsnID*/0, /*Imm*/0,
      GIR_MergeMemOperands, /*InsnID*/0, /*NumInsns*/1, /*MergeInsnID's*/0,
      GIR_ConstrainSelectedInstOperands, /*InsnID*/0,
      GIR_EraseFromParent, /*InsnID*/0,
      // GIR_Coverage, 3499,
      GIR_Done,
    // Label 2176: @142807
    GIM_Try, /*On fail goto*//*Label 2177*/ GIMT_Encode4(142869), // Rule ID 3505 //
      GIM_CheckFeatures, GIMT_Encode2(GIFBS_EnableFlatScratch_HasFlatScratchInsts_HasFlatScratchSVSMode),
      GIM_CheckMemoryAddressSpace, /*MI*/0, /*MMO*/0, /*NumAddrSpace*/1, /*AddrSpace*/5,
      GIM_CheckAtomicOrdering, /*MI*/0, /*Order*/(uint8_t)AtomicOrdering::NotAtomic,
      GIM_CheckPointerToAny, /*MI*/0, /*Op*/1, /*SizeInBits*/0,
      GIM_CheckComplexPattern, /*MI*/0, /*Op*/1, /*Renderer*/GIMT_Encode2(0), GIMT_Encode2(GICP_gi_flat_scratch_svaddr),
      // (st v2f32:{ *:[v2f32] }:$data, (ScratchSVAddr:{ *:[iPTR] } VGPR_32:{ *:[i32] }:$vaddr, SGPR_32:{ *:[i32] }:$saddr, i32:{ *:[i32] }:$offset))<<P:Predicate_unindexedstore>><<P:Predicate_store_private>>  =>  (SCRATCH_STORE_DWORDX2_SVS anonymous_15036:{ *:[v2f32] }:$data, ?:{ *:[i32] }:$vaddr, ?:{ *:[i32] }:$saddr, ?:{ *:[i32] }:$offset)
      GIR_BuildMI, /*InsnID*/0, /*Opcode*/GIMT_Encode2(AMDGPU::SCRATCH_STORE_DWORDX2_SVS),
      GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/0, // data
      GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/0, // vaddr
      GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/1, // saddr
      GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/2, // offset
      GIR_AddImm8, /*InsnID*/0, /*Imm*/0,
      GIR_MergeMemOperands, /*InsnID*/0, /*NumInsns*/1, /*MergeInsnID's*/0,
      GIR_ConstrainSelectedInstOperands, /*InsnID*/0,
      GIR_EraseFromParent, /*InsnID*/0,
      // GIR_Coverage, 3505,
      GIR_Done,
    // Label 2177: @142869
    GIM_Try, /*On fail goto*//*Label 2178*/ GIMT_Encode4(142926), // Rule ID 3498 //
      GIM_CheckFeatures, GIMT_Encode2(GIFBS_EnableFlatScratch_HasFlatScratchInsts),
      GIM_CheckMemoryAddressSpace, /*MI*/0, /*MMO*/0, /*NumAddrSpace*/1, /*AddrSpace*/5,
      GIM_CheckAtomicOrdering, /*MI*/0, /*Order*/(uint8_t)AtomicOrdering::NotAtomic,
      GIM_CheckPointerToAny, /*MI*/0, /*Op*/1, /*SizeInBits*/0,
      GIM_CheckComplexPattern, /*MI*/0, /*Op*/1, /*Renderer*/GIMT_Encode2(0), GIMT_Encode2(GICP_gi_flat_scratch_saddr),
      // (st v2i32:{ *:[v2i32] }:$data, (ScratchSAddr:{ *:[iPTR] } SGPR_32:{ *:[i32] }:$saddr, i32:{ *:[i32] }:$offset))<<P:Predicate_unindexedstore>><<P:Predicate_store_private>>  =>  (SCRATCH_STORE_DWORDX2_SADDR anonymous_15036:{ *:[v2i32] }:$data, ?:{ *:[i32] }:$saddr, ?:{ *:[i32] }:$offset)
      GIR_BuildMI, /*InsnID*/0, /*Opcode*/GIMT_Encode2(AMDGPU::SCRATCH_STORE_DWORDX2_SADDR),
      GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/0, // data
      GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/0, // saddr
      GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/1, // offset
      GIR_AddImm8, /*InsnID*/0, /*Imm*/0,
      GIR_MergeMemOperands, /*InsnID*/0, /*NumInsns*/1, /*MergeInsnID's*/0,
      GIR_ConstrainSelectedInstOperands, /*InsnID*/0,
      GIR_EraseFromParent, /*InsnID*/0,
      // GIR_Coverage, 3498,
      GIR_Done,
    // Label 2178: @142926
    GIM_Try, /*On fail goto*//*Label 2179*/ GIMT_Encode4(142983), // Rule ID 3504 //
      GIM_CheckFeatures, GIMT_Encode2(GIFBS_EnableFlatScratch_HasFlatScratchInsts),
      GIM_CheckMemoryAddressSpace, /*MI*/0, /*MMO*/0, /*NumAddrSpace*/1, /*AddrSpace*/5,
      GIM_CheckAtomicOrdering, /*MI*/0, /*Order*/(uint8_t)AtomicOrdering::NotAtomic,
      GIM_CheckPointerToAny, /*MI*/0, /*Op*/1, /*SizeInBits*/0,
      GIM_CheckComplexPattern, /*MI*/0, /*Op*/1, /*Renderer*/GIMT_Encode2(0), GIMT_Encode2(GICP_gi_flat_scratch_saddr),
      // (st v2f32:{ *:[v2f32] }:$data, (ScratchSAddr:{ *:[iPTR] } SGPR_32:{ *:[i32] }:$saddr, i32:{ *:[i32] }:$offset))<<P:Predicate_unindexedstore>><<P:Predicate_store_private>>  =>  (SCRATCH_STORE_DWORDX2_SADDR anonymous_15036:{ *:[v2f32] }:$data, ?:{ *:[i32] }:$saddr, ?:{ *:[i32] }:$offset)
      GIR_BuildMI, /*InsnID*/0, /*Opcode*/GIMT_Encode2(AMDGPU::SCRATCH_STORE_DWORDX2_SADDR),
      GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/0, // data
      GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/0, // saddr
      GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/1, // offset
      GIR_AddImm8, /*InsnID*/0, /*Imm*/0,
      GIR_MergeMemOperands, /*InsnID*/0, /*NumInsns*/1, /*MergeInsnID's*/0,
      GIR_ConstrainSelectedInstOperands, /*InsnID*/0,
      GIR_EraseFromParent, /*InsnID*/0,
      // GIR_Coverage, 3504,
      GIR_Done,
    // Label 2179: @142983
    GIM_Try, /*On fail goto*//*Label 2180*/ GIMT_Encode4(143040), // Rule ID 3497 //
      GIM_CheckFeatures, GIMT_Encode2(GIFBS_EnableFlatScratch_HasFlatScratchInsts),
      GIM_CheckMemoryAddressSpace, /*MI*/0, /*MMO*/0, /*NumAddrSpace*/1, /*AddrSpace*/5,
      GIM_CheckAtomicOrdering, /*MI*/0, /*Order*/(uint8_t)AtomicOrdering::NotAtomic,
      GIM_CheckPointerToAny, /*MI*/0, /*Op*/1, /*SizeInBits*/0,
      GIM_CheckComplexPattern, /*MI*/0, /*Op*/1, /*Renderer*/GIMT_Encode2(0), GIMT_Encode2(GICP_gi_flat_scratch_offset),
      // (st v2i32:{ *:[v2i32] }:$data, (ScratchOffset:{ *:[iPTR] } VGPR_32:{ *:[i32] }:$vaddr, i32:{ *:[i32] }:$offset))<<P:Predicate_unindexedstore>><<P:Predicate_store_private>>  =>  (SCRATCH_STORE_DWORDX2 anonymous_15036:{ *:[v2i32] }:$data, ?:{ *:[i32] }:$vaddr, ?:{ *:[i32] }:$offset)
      GIR_BuildMI, /*InsnID*/0, /*Opcode*/GIMT_Encode2(AMDGPU::SCRATCH_STORE_DWORDX2),
      GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/0, // data
      GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/0, // vaddr
      GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/1, // offset
      GIR_AddImm8, /*InsnID*/0, /*Imm*/0,
      GIR_MergeMemOperands, /*InsnID*/0, /*NumInsns*/1, /*MergeInsnID's*/0,
      GIR_ConstrainSelectedInstOperands, /*InsnID*/0,
      GIR_EraseFromParent, /*InsnID*/0,
      // GIR_Coverage, 3497,
      GIR_Done,
    // Label 2180: @143040
    GIM_Try, /*On fail goto*//*Label 2181*/ GIMT_Encode4(143097), // Rule ID 3503 //
      GIM_CheckFeatures, GIMT_Encode2(GIFBS_EnableFlatScratch_HasFlatScratchInsts),
      GIM_CheckMemoryAddressSpace, /*MI*/0, /*MMO*/0, /*NumAddrSpace*/1, /*AddrSpace*/5,
      GIM_CheckAtomicOrdering, /*MI*/0, /*Order*/(uint8_t)AtomicOrdering::NotAtomic,
      GIM_CheckPointerToAny, /*MI*/0, /*Op*/1, /*SizeInBits*/0,
      GIM_CheckComplexPattern, /*MI*/0, /*Op*/1, /*Renderer*/GIMT_Encode2(0), GIMT_Encode2(GICP_gi_flat_scratch_offset),
      // (st v2f32:{ *:[v2f32] }:$data, (ScratchOffset:{ *:[iPTR] } VGPR_32:{ *:[i32] }:$vaddr, i32:{ *:[i32] }:$offset))<<P:Predicate_unindexedstore>><<P:Predicate_store_private>>  =>  (SCRATCH_STORE_DWORDX2 anonymous_15036:{ *:[v2f32] }:$data, ?:{ *:[i32] }:$vaddr, ?:{ *:[i32] }:$offset)
      GIR_BuildMI, /*InsnID*/0, /*Opcode*/GIMT_Encode2(AMDGPU::SCRATCH_STORE_DWORDX2),
      GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/0, // data
      GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/0, // vaddr
      GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/1, // offset
      GIR_AddImm8, /*InsnID*/0, /*Imm*/0,
      GIR_MergeMemOperands, /*InsnID*/0, /*NumInsns*/1, /*MergeInsnID's*/0,
      GIR_ConstrainSelectedInstOperands, /*InsnID*/0,
      GIR_EraseFromParent, /*InsnID*/0,
      // GIR_Coverage, 3503,
      GIR_Done,
    // Label 2181: @143097
    GIM_Try, /*On fail goto*//*Label 2182*/ GIMT_Encode4(143167), // Rule ID 3846 //
      GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasUnrestrictedSOffset),
      GIM_CheckMemoryAddressSpace, /*MI*/0, /*MMO*/0, /*NumAddrSpace*/1, /*AddrSpace*/1,
      GIM_CheckAtomicOrdering, /*MI*/0, /*Order*/(uint8_t)AtomicOrdering::NotAtomic,
      GIM_CheckPointerToAny, /*MI*/0, /*Op*/1, /*SizeInBits*/0,
      GIM_CheckComplexPattern, /*MI*/0, /*Op*/1, /*Renderer*/GIMT_Encode2(0), GIMT_Encode2(GICP_gi_mubuf_addr64),
      // (st v2i32:{ *:[v2i32] }:$vdata, (MUBUFAddr64:{ *:[iPTR] } v4i32:{ *:[v4i32] }:$srsrc, i64:{ *:[i64] }:$vaddr, i32:{ *:[i32] }:$soffset, i32:{ *:[i32] }:$offset))<<P:Predicate_unindexedstore>><<P:Predicate_store_global>>  =>  (BUFFER_STORE_DWORDX2_ADDR64 v2i32:{ *:[v2i32] }:$vdata, i64:{ *:[i64] }:$vaddr, v4i32:{ *:[v4i32] }:$srsrc, i32:{ *:[i32] }:$soffset, i32:{ *:[i32] }:$offset)
      GIR_BuildMI, /*InsnID*/0, /*Opcode*/GIMT_Encode2(AMDGPU::BUFFER_STORE_DWORDX2_ADDR64),
      GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/0, // vdata
      GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/1, // vaddr
      GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/0, // srsrc
      GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/2, // soffset
      GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/3, // offset
      GIR_AddImm8, /*InsnID*/0, /*Imm*/0,
      GIR_AddImm8, /*InsnID*/0, /*Imm*/0,
      GIR_MergeMemOperands, /*InsnID*/0, /*NumInsns*/1, /*MergeInsnID's*/0,
      GIR_ConstrainSelectedInstOperands, /*InsnID*/0,
      GIR_EraseFromParent, /*InsnID*/0,
      // GIR_Coverage, 3846,
      GIR_Done,
    // Label 2182: @143167
    GIM_Try, /*On fail goto*//*Label 2183*/ GIMT_Encode4(143234), // Rule ID 3848 //
      GIM_CheckMemoryAddressSpace, /*MI*/0, /*MMO*/0, /*NumAddrSpace*/1, /*AddrSpace*/1,
      GIM_CheckAtomicOrdering, /*MI*/0, /*Order*/(uint8_t)AtomicOrdering::NotAtomic,
      GIM_CheckPointerToAny, /*MI*/0, /*Op*/1, /*SizeInBits*/0,
      GIM_CheckComplexPattern, /*MI*/0, /*Op*/1, /*Renderer*/GIMT_Encode2(0), GIMT_Encode2(GICP_gi_mubuf_addr64),
      // (st v2i32:{ *:[v2i32] }:$vdata, (MUBUFAddr64:{ *:[iPTR] } v4i32:{ *:[v4i32] }:$srsrc, i64:{ *:[i64] }:$vaddr, i32:{ *:[i32] }:$soffset, i32:{ *:[i32] }:$offset))<<P:Predicate_unindexedstore>><<P:Predicate_store_global>>  =>  (BUFFER_STORE_DWORDX2_VBUFFER_ADDR64 v2i32:{ *:[v2i32] }:$vdata, i64:{ *:[i64] }:$vaddr, v4i32:{ *:[v4i32] }:$srsrc, i32:{ *:[i32] }:$soffset, i32:{ *:[i32] }:$offset)
      GIR_BuildMI, /*InsnID*/0, /*Opcode*/GIMT_Encode2(AMDGPU::BUFFER_STORE_DWORDX2_VBUFFER_ADDR64),
      GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/0, // vdata
      GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/1, // vaddr
      GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/0, // srsrc
      GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/2, // soffset
      GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/3, // offset
      GIR_AddImm8, /*InsnID*/0, /*Imm*/0,
      GIR_AddImm8, /*InsnID*/0, /*Imm*/0,
      GIR_MergeMemOperands, /*InsnID*/0, /*NumInsns*/1, /*MergeInsnID's*/0,
      GIR_ConstrainSelectedInstOperands, /*InsnID*/0,
      GIR_EraseFromParent, /*InsnID*/0,
      // GIR_Coverage, 3848,
      GIR_Done,
    // Label 2183: @143234
    GIM_Try, /*On fail goto*//*Label 2184*/ GIMT_Encode4(143304), // Rule ID 3850 //
      GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasUnrestrictedSOffset),
      GIM_CheckMemoryAddressSpace, /*MI*/0, /*MMO*/0, /*NumAddrSpace*/1, /*AddrSpace*/1,
      GIM_CheckAtomicOrdering, /*MI*/0, /*Order*/(uint8_t)AtomicOrdering::NotAtomic,
      GIM_CheckPointerToAny, /*MI*/0, /*Op*/1, /*SizeInBits*/0,
      GIM_CheckComplexPattern, /*MI*/0, /*Op*/1, /*Renderer*/GIMT_Encode2(0), GIMT_Encode2(GICP_gi_mubuf_addr64),
      // (st v2f32:{ *:[v2f32] }:$vdata, (MUBUFAddr64:{ *:[iPTR] } v4i32:{ *:[v4i32] }:$srsrc, i64:{ *:[i64] }:$vaddr, i32:{ *:[i32] }:$soffset, i32:{ *:[i32] }:$offset))<<P:Predicate_unindexedstore>><<P:Predicate_store_global>>  =>  (BUFFER_STORE_DWORDX2_ADDR64 v2f32:{ *:[v2f32] }:$vdata, i64:{ *:[i64] }:$vaddr, v4i32:{ *:[v4i32] }:$srsrc, i32:{ *:[i32] }:$soffset, i32:{ *:[i32] }:$offset)
      GIR_BuildMI, /*InsnID*/0, /*Opcode*/GIMT_Encode2(AMDGPU::BUFFER_STORE_DWORDX2_ADDR64),
      GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/0, // vdata
      GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/1, // vaddr
      GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/0, // srsrc
      GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/2, // soffset
      GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/3, // offset
      GIR_AddImm8, /*InsnID*/0, /*Imm*/0,
      GIR_AddImm8, /*InsnID*/0, /*Imm*/0,
      GIR_MergeMemOperands, /*InsnID*/0, /*NumInsns*/1, /*MergeInsnID's*/0,
      GIR_ConstrainSelectedInstOperands, /*InsnID*/0,
      GIR_EraseFromParent, /*InsnID*/0,
      // GIR_Coverage, 3850,
      GIR_Done,
    // Label 2184: @143304
    GIM_Try, /*On fail goto*//*Label 2185*/ GIMT_Encode4(143371), // Rule ID 3852 //
      GIM_CheckMemoryAddressSpace, /*MI*/0, /*MMO*/0, /*NumAddrSpace*/1, /*AddrSpace*/1,
      GIM_CheckAtomicOrdering, /*MI*/0, /*Order*/(uint8_t)AtomicOrdering::NotAtomic,
      GIM_CheckPointerToAny, /*MI*/0, /*Op*/1, /*SizeInBits*/0,
      GIM_CheckComplexPattern, /*MI*/0, /*Op*/1, /*Renderer*/GIMT_Encode2(0), GIMT_Encode2(GICP_gi_mubuf_addr64),
      // (st v2f32:{ *:[v2f32] }:$vdata, (MUBUFAddr64:{ *:[iPTR] } v4i32:{ *:[v4i32] }:$srsrc, i64:{ *:[i64] }:$vaddr, i32:{ *:[i32] }:$soffset, i32:{ *:[i32] }:$offset))<<P:Predicate_unindexedstore>><<P:Predicate_store_global>>  =>  (BUFFER_STORE_DWORDX2_VBUFFER_ADDR64 v2f32:{ *:[v2f32] }:$vdata, i64:{ *:[i64] }:$vaddr, v4i32:{ *:[v4i32] }:$srsrc, i32:{ *:[i32] }:$soffset, i32:{ *:[i32] }:$offset)
      GIR_BuildMI, /*InsnID*/0, /*Opcode*/GIMT_Encode2(AMDGPU::BUFFER_STORE_DWORDX2_VBUFFER_ADDR64),
      GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/0, // vdata
      GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/1, // vaddr
      GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/0, // srsrc
      GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/2, // soffset
      GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/3, // offset
      GIR_AddImm8, /*InsnID*/0, /*Imm*/0,
      GIR_AddImm8, /*InsnID*/0, /*Imm*/0,
      GIR_MergeMemOperands, /*InsnID*/0, /*NumInsns*/1, /*MergeInsnID's*/0,
      GIR_ConstrainSelectedInstOperands, /*InsnID*/0,
      GIR_EraseFromParent, /*InsnID*/0,
      // GIR_Coverage, 3852,
      GIR_Done,
    // Label 2185: @143371
    GIM_Try, /*On fail goto*//*Label 2186*/ GIMT_Encode4(143441), // Rule ID 5549 //
      GIM_CheckFeatures, GIMT_Encode2(GIFBS_DisableFlatScratch_HasUnrestrictedSOffset),
      GIM_CheckMemoryAddressSpace, /*MI*/0, /*MMO*/0, /*NumAddrSpace*/1, /*AddrSpace*/5,
      GIM_CheckAtomicOrdering, /*MI*/0, /*Order*/(uint8_t)AtomicOrdering::NotAtomic,
      GIM_CheckPointerToAny, /*MI*/0, /*Op*/1, /*SizeInBits*/0,
      GIM_CheckComplexPattern, /*MI*/0, /*Op*/1, /*Renderer*/GIMT_Encode2(0), GIMT_Encode2(GICP_gi_mubuf_scratch_offen),
      // (st v2i32:{ *:[v2i32] }:$value, (MUBUFScratchOffen:{ *:[iPTR] } v4i32:{ *:[v4i32] }:$srsrc, i32:{ *:[i32] }:$vaddr, i32:{ *:[i32] }:$soffset, i32:{ *:[i32] }:$offset))<<P:Predicate_unindexedstore>><<P:Predicate_store_private>>  =>  (BUFFER_STORE_DWORDX2_OFFEN VReg_64:{ *:[v2i32] }:$value, ?:{ *:[i32] }:$vaddr, ?:{ *:[v4i32] }:$srsrc, ?:{ *:[i32] }:$soffset, ?:{ *:[i32] }:$offset, 0:{ *:[i32] }, 0:{ *:[i1] })
      GIR_BuildMI, /*InsnID*/0, /*Opcode*/GIMT_Encode2(AMDGPU::BUFFER_STORE_DWORDX2_OFFEN),
      GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/0, // value
      GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/1, // vaddr
      GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/0, // srsrc
      GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/2, // soffset
      GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/3, // offset
      GIR_AddImm8, /*InsnID*/0, /*Imm*/0,
      GIR_AddImm8, /*InsnID*/0, /*Imm*/0,
      GIR_MergeMemOperands, /*InsnID*/0, /*NumInsns*/1, /*MergeInsnID's*/0,
      GIR_ConstrainSelectedInstOperands, /*InsnID*/0,
      GIR_EraseFromParent, /*InsnID*/0,
      // GIR_Coverage, 5549,
      GIR_Done,
    // Label 2186: @143441
    GIM_Try, /*On fail goto*//*Label 2187*/ GIMT_Encode4(143511), // Rule ID 5551 //
      GIM_CheckFeatures, GIMT_Encode2(GIFBS_DisableFlatScratch),
      GIM_CheckMemoryAddressSpace, /*MI*/0, /*MMO*/0, /*NumAddrSpace*/1, /*AddrSpace*/5,
      GIM_CheckAtomicOrdering, /*MI*/0, /*Order*/(uint8_t)AtomicOrdering::NotAtomic,
      GIM_CheckPointerToAny, /*MI*/0, /*Op*/1, /*SizeInBits*/0,
      GIM_CheckComplexPattern, /*MI*/0, /*Op*/1, /*Renderer*/GIMT_Encode2(0), GIMT_Encode2(GICP_gi_mubuf_scratch_offen),
      // (st v2i32:{ *:[v2i32] }:$value, (MUBUFScratchOffen:{ *:[iPTR] } v4i32:{ *:[v4i32] }:$srsrc, i32:{ *:[i32] }:$vaddr, i32:{ *:[i32] }:$soffset, i32:{ *:[i32] }:$offset))<<P:Predicate_unindexedstore>><<P:Predicate_store_private>>  =>  (BUFFER_STORE_DWORDX2_VBUFFER_OFFEN VReg_64:{ *:[v2i32] }:$value, ?:{ *:[i32] }:$vaddr, ?:{ *:[v4i32] }:$srsrc, ?:{ *:[i32] }:$soffset, ?:{ *:[i32] }:$offset, 0:{ *:[i32] }, 0:{ *:[i1] })
      GIR_BuildMI, /*InsnID*/0, /*Opcode*/GIMT_Encode2(AMDGPU::BUFFER_STORE_DWORDX2_VBUFFER_OFFEN),
      GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/0, // value
      GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/1, // vaddr
      GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/0, // srsrc
      GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/2, // soffset
      GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/3, // offset
      GIR_AddImm8, /*InsnID*/0, /*Imm*/0,
      GIR_AddImm8, /*InsnID*/0, /*Imm*/0,
      GIR_MergeMemOperands, /*InsnID*/0, /*NumInsns*/1, /*MergeInsnID's*/0,
      GIR_ConstrainSelectedInstOperands, /*InsnID*/0,
      GIR_EraseFromParent, /*InsnID*/0,
      // GIR_Coverage, 5551,
      GIR_Done,
    // Label 2187: @143511
    GIM_Try, /*On fail goto*//*Label 2188*/ GIMT_Encode4(143635), // Rule ID 6684 //
      GIM_CheckFeatures, GIMT_Encode2(GIFBS_LDSRequiresM0Init_isGFX7Plus),
      GIM_CheckMemorySizeEqualToLLT, /*MI*/0, /*MMO*/0, /*OpIdx*/0,
      GIM_CheckMemoryAddressSpace, /*MI*/0, /*MMO*/0, /*NumAddrSpace*/1, /*AddrSpace*/3,
      GIM_CheckAtomicOrdering, /*MI*/0, /*Order*/(uint8_t)AtomicOrdering::NotAtomic,
      GIM_CheckPointerToAny, /*MI*/0, /*Op*/1, /*SizeInBits*/0,
      GIM_CheckComplexPattern, /*MI*/0, /*Op*/1, /*Renderer*/GIMT_Encode2(0), GIMT_Encode2(GICP_gi_ds_64bit_4byte_aligned),
      // (AMDGPUst_glue v2i32:{ *:[v2i32] }:$value, (DS64Bit4ByteAligned:{ *:[iPTR] } i32:{ *:[i32] }:$ptr, i8:{ *:[i8] }:$offset0, i8:{ *:[i8] }:$offset1))<<P:Predicate_unindexedstore_glue>><<P:Predicate_store_glue>><<P:Predicate_store_local_m0>>  =>  (DS_WRITE2_B32 ?:{ *:[i32] }:$ptr, (EXTRACT_SUBREG:{ *:[i32] } VReg_64:{ *:[v2i32] }:$value, sub0:{ *:[i32] }), (EXTRACT_SUBREG:{ *:[i32] } VReg_64:{ *:[v2i32] }:$value, sub1:{ *:[i32] }), ?:{ *:[i8] }:$offset0, ?:{ *:[i8] }:$offset1, 0:{ *:[i1] })
      GIR_MakeTempReg, /*TempRegID*/0, /*TypeID*/GILLT_s32,
      GIR_MakeTempReg, /*TempRegID*/1, /*TypeID*/GILLT_s32,
      GIR_BuildMI, /*InsnID*/2, /*Opcode*/GIMT_Encode2(TargetOpcode::COPY),
      GIR_AddTempRegister, /*InsnID*/2, /*TempRegID*/1, /*TempRegFlags*/GIMT_Encode2(RegState::Define),
      GIR_CopySubReg, /*NewInsnID*/2, /*OldInsnID*/0, /*OpIdx*/0, /*SubRegIdx*/GIMT_Encode2(11), // value
      GIR_ConstrainOperandRC, /*InsnID*/2, /*Op*/0, GIMT_Encode2(AMDGPU::VGPR_32RegClassID),
      GIR_ConstrainOperandRC, /*InsnID*/2, /*Op*/1, GIMT_Encode2(AMDGPU::VReg_64RegClassID),
      GIR_BuildMI, /*InsnID*/1, /*Opcode*/GIMT_Encode2(TargetOpcode::COPY),
      GIR_AddTempRegister, /*InsnID*/1, /*TempRegID*/0, /*TempRegFlags*/GIMT_Encode2(RegState::Define),
      GIR_CopySubReg, /*NewInsnID*/1, /*OldInsnID*/0, /*OpIdx*/0, /*SubRegIdx*/GIMT_Encode2(3), // value
      GIR_ConstrainOperandRC, /*InsnID*/1, /*Op*/0, GIMT_Encode2(AMDGPU::VGPR_32RegClassID),
      GIR_ConstrainOperandRC, /*InsnID*/1, /*Op*/1, GIMT_Encode2(AMDGPU::VReg_64RegClassID),
      GIR_BuildMI, /*InsnID*/0, /*Opcode*/GIMT_Encode2(AMDGPU::DS_WRITE2_B32),
      GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/0, // ptr
      GIR_AddSimpleTempRegister, /*InsnID*/0, /*TempRegID*/0,
      GIR_AddSimpleTempRegister, /*InsnID*/0, /*TempRegID*/1,
      GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/1, // offset0
      GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/2, // offset1
      GIR_AddImm8, /*InsnID*/0, /*Imm*/0,
      GIR_MergeMemOperands, /*InsnID*/0, /*NumInsns*/1, /*MergeInsnID's*/0,
      GIR_ConstrainSelectedInstOperands, /*InsnID*/0,
      GIR_EraseFromParent, /*InsnID*/0,
      // GIR_Coverage, 6684,
      GIR_Done,
    // Label 2188: @143635
    GIM_Try, /*On fail goto*//*Label 2189*/ GIMT_Encode4(143759), // Rule ID 6688 //
      GIM_CheckFeatures, GIMT_Encode2(GIFBS_LDSRequiresM0Init_isGFX7Plus),
      GIM_CheckMemorySizeEqualToLLT, /*MI*/0, /*MMO*/0, /*OpIdx*/0,
      GIM_CheckMemoryAddressSpace, /*MI*/0, /*MMO*/0, /*NumAddrSpace*/1, /*AddrSpace*/3,
      GIM_CheckAtomicOrdering, /*MI*/0, /*Order*/(uint8_t)AtomicOrdering::NotAtomic,
      GIM_CheckPointerToAny, /*MI*/0, /*Op*/1, /*SizeInBits*/0,
      GIM_CheckComplexPattern, /*MI*/0, /*Op*/1, /*Renderer*/GIMT_Encode2(0), GIMT_Encode2(GICP_gi_ds_64bit_4byte_aligned),
      // (AMDGPUst_glue v2f32:{ *:[v2f32] }:$value, (DS64Bit4ByteAligned:{ *:[iPTR] } i32:{ *:[i32] }:$ptr, i8:{ *:[i8] }:$offset0, i8:{ *:[i8] }:$offset1))<<P:Predicate_unindexedstore_glue>><<P:Predicate_store_glue>><<P:Predicate_store_local_m0>>  =>  (DS_WRITE2_B32 ?:{ *:[i32] }:$ptr, (EXTRACT_SUBREG:{ *:[i32] } VReg_64:{ *:[v2f32] }:$value, sub0:{ *:[i32] }), (EXTRACT_SUBREG:{ *:[i32] } VReg_64:{ *:[v2f32] }:$value, sub1:{ *:[i32] }), ?:{ *:[i8] }:$offset0, ?:{ *:[i8] }:$offset1, 0:{ *:[i1] })
      GIR_MakeTempReg, /*TempRegID*/0, /*TypeID*/GILLT_s32,
      GIR_MakeTempReg, /*TempRegID*/1, /*TypeID*/GILLT_s32,
      GIR_BuildMI, /*InsnID*/2, /*Opcode*/GIMT_Encode2(TargetOpcode::COPY),
      GIR_AddTempRegister, /*InsnID*/2, /*TempRegID*/1, /*TempRegFlags*/GIMT_Encode2(RegState::Define),
      GIR_CopySubReg, /*NewInsnID*/2, /*OldInsnID*/0, /*OpIdx*/0, /*SubRegIdx*/GIMT_Encode2(11), // value
      GIR_ConstrainOperandRC, /*InsnID*/2, /*Op*/0, GIMT_Encode2(AMDGPU::VGPR_32RegClassID),
      GIR_ConstrainOperandRC, /*InsnID*/2, /*Op*/1, GIMT_Encode2(AMDGPU::VReg_64RegClassID),
      GIR_BuildMI, /*InsnID*/1, /*Opcode*/GIMT_Encode2(TargetOpcode::COPY),
      GIR_AddTempRegister, /*InsnID*/1, /*TempRegID*/0, /*TempRegFlags*/GIMT_Encode2(RegState::Define),
      GIR_CopySubReg, /*NewInsnID*/1, /*OldInsnID*/0, /*OpIdx*/0, /*SubRegIdx*/GIMT_Encode2(3), // value
      GIR_ConstrainOperandRC, /*InsnID*/1, /*Op*/0, GIMT_Encode2(AMDGPU::VGPR_32RegClassID),
      GIR_ConstrainOperandRC, /*InsnID*/1, /*Op*/1, GIMT_Encode2(AMDGPU::VReg_64RegClassID),
      GIR_BuildMI, /*InsnID*/0, /*Opcode*/GIMT_Encode2(AMDGPU::DS_WRITE2_B32),
      GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/0, // ptr
      GIR_AddSimpleTempRegister, /*InsnID*/0, /*TempRegID*/0,
      GIR_AddSimpleTempRegister, /*InsnID*/0, /*TempRegID*/1,
      GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/1, // offset0
      GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/2, // offset1
      GIR_AddImm8, /*InsnID*/0, /*Imm*/0,
      GIR_MergeMemOperands, /*InsnID*/0, /*NumInsns*/1, /*MergeInsnID's*/0,
      GIR_ConstrainSelectedInstOperands, /*InsnID*/0,
      GIR_EraseFromParent, /*InsnID*/0,
      // GIR_Coverage, 6688,
      GIR_Done,
    // Label 2189: @143759
    GIM_Try, /*On fail goto*//*Label 2190*/ GIMT_Encode4(143824), // Rule ID 3845 //
      GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasUnrestrictedSOffset),
      GIM_CheckMemoryAddressSpace, /*MI*/0, /*MMO*/0, /*NumAddrSpace*/1, /*AddrSpace*/1,
      GIM_CheckAtomicOrdering, /*MI*/0, /*Order*/(uint8_t)AtomicOrdering::NotAtomic,
      GIM_CheckPointerToAny, /*MI*/0, /*Op*/1, /*SizeInBits*/0,
      GIM_CheckComplexPattern, /*MI*/0, /*Op*/1, /*Renderer*/GIMT_Encode2(0), GIMT_Encode2(GICP_gi_mubuf_offset),
      // (st v2i32:{ *:[v2i32] }:$vdata, (MUBUFOffset:{ *:[iPTR] } v4i32:{ *:[v4i32] }:$srsrc, i32:{ *:[i32] }:$soffset, i32:{ *:[i32] }:$offset))<<P:Predicate_unindexedstore>><<P:Predicate_store_global>>  =>  (BUFFER_STORE_DWORDX2_OFFSET v2i32:{ *:[v2i32] }:$vdata, v4i32:{ *:[v4i32] }:$srsrc, i32:{ *:[i32] }:$soffset, i32:{ *:[i32] }:$offset)
      GIR_BuildMI, /*InsnID*/0, /*Opcode*/GIMT_Encode2(AMDGPU::BUFFER_STORE_DWORDX2_OFFSET),
      GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/0, // vdata
      GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/0, // srsrc
      GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/1, // soffset
      GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/2, // offset
      GIR_AddImm8, /*InsnID*/0, /*Imm*/0,
      GIR_AddImm8, /*InsnID*/0, /*Imm*/0,
      GIR_MergeMemOperands, /*InsnID*/0, /*NumInsns*/1, /*MergeInsnID's*/0,
      GIR_ConstrainSelectedInstOperands, /*InsnID*/0,
      GIR_EraseFromParent, /*InsnID*/0,
      // GIR_Coverage, 3845,
      GIR_Done,
    // Label 2190: @143824
    GIM_Try, /*On fail goto*//*Label 2191*/ GIMT_Encode4(143886), // Rule ID 3847 //
      GIM_CheckMemoryAddressSpace, /*MI*/0, /*MMO*/0, /*NumAddrSpace*/1, /*AddrSpace*/1,
      GIM_CheckAtomicOrdering, /*MI*/0, /*Order*/(uint8_t)AtomicOrdering::NotAtomic,
      GIM_CheckPointerToAny, /*MI*/0, /*Op*/1, /*SizeInBits*/0,
      GIM_CheckComplexPattern, /*MI*/0, /*Op*/1, /*Renderer*/GIMT_Encode2(0), GIMT_Encode2(GICP_gi_mubuf_offset),
      // (st v2i32:{ *:[v2i32] }:$vdata, (MUBUFOffset:{ *:[iPTR] } v4i32:{ *:[v4i32] }:$srsrc, i32:{ *:[i32] }:$soffset, i32:{ *:[i32] }:$offset))<<P:Predicate_unindexedstore>><<P:Predicate_store_global>>  =>  (BUFFER_STORE_DWORDX2_VBUFFER_OFFSET v2i32:{ *:[v2i32] }:$vdata, v4i32:{ *:[v4i32] }:$srsrc, i32:{ *:[i32] }:$soffset, i32:{ *:[i32] }:$offset)
      GIR_BuildMI, /*InsnID*/0, /*Opcode*/GIMT_Encode2(AMDGPU::BUFFER_STORE_DWORDX2_VBUFFER_OFFSET),
      GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/0, // vdata
      GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/0, // srsrc
      GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/1, // soffset
      GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/2, // offset
      GIR_AddImm8, /*InsnID*/0, /*Imm*/0,
      GIR_AddImm8, /*InsnID*/0, /*Imm*/0,
      GIR_MergeMemOperands, /*InsnID*/0, /*NumInsns*/1, /*MergeInsnID's*/0,
      GIR_ConstrainSelectedInstOperands, /*InsnID*/0,
      GIR_EraseFromParent, /*InsnID*/0,
      // GIR_Coverage, 3847,
      GIR_Done,
    // Label 2191: @143886
    GIM_Try, /*On fail goto*//*Label 2192*/ GIMT_Encode4(143951), // Rule ID 3849 //
      GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasUnrestrictedSOffset),
      GIM_CheckMemoryAddressSpace, /*MI*/0, /*MMO*/0, /*NumAddrSpace*/1, /*AddrSpace*/1,
      GIM_CheckAtomicOrdering, /*MI*/0, /*Order*/(uint8_t)AtomicOrdering::NotAtomic,
      GIM_CheckPointerToAny, /*MI*/0, /*Op*/1, /*SizeInBits*/0,
      GIM_CheckComplexPattern, /*MI*/0, /*Op*/1, /*Renderer*/GIMT_Encode2(0), GIMT_Encode2(GICP_gi_mubuf_offset),
      // (st v2f32:{ *:[v2f32] }:$vdata, (MUBUFOffset:{ *:[iPTR] } v4i32:{ *:[v4i32] }:$srsrc, i32:{ *:[i32] }:$soffset, i32:{ *:[i32] }:$offset))<<P:Predicate_unindexedstore>><<P:Predicate_store_global>>  =>  (BUFFER_STORE_DWORDX2_OFFSET v2f32:{ *:[v2f32] }:$vdata, v4i32:{ *:[v4i32] }:$srsrc, i32:{ *:[i32] }:$soffset, i32:{ *:[i32] }:$offset)
      GIR_BuildMI, /*InsnID*/0, /*Opcode*/GIMT_Encode2(AMDGPU::BUFFER_STORE_DWORDX2_OFFSET),
      GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/0, // vdata
      GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/0, // srsrc
      GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/1, // soffset
      GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/2, // offset
      GIR_AddImm8, /*InsnID*/0, /*Imm*/0,
      GIR_AddImm8, /*InsnID*/0, /*Imm*/0,
      GIR_MergeMemOperands, /*InsnID*/0, /*NumInsns*/1, /*MergeInsnID's*/0,
      GIR_ConstrainSelectedInstOperands, /*InsnID*/0,
      GIR_EraseFromParent, /*InsnID*/0,
      // GIR_Coverage, 3849,
      GIR_Done,
    // Label 2192: @143951
    GIM_Try, /*On fail goto*//*Label 2193*/ GIMT_Encode4(144013), // Rule ID 3851 //
      GIM_CheckMemoryAddressSpace, /*MI*/0, /*MMO*/0, /*NumAddrSpace*/1, /*AddrSpace*/1,
      GIM_CheckAtomicOrdering, /*MI*/0, /*Order*/(uint8_t)AtomicOrdering::NotAtomic,
      GIM_CheckPointerToAny, /*MI*/0, /*Op*/1, /*SizeInBits*/0,
      GIM_CheckComplexPattern, /*MI*/0, /*Op*/1, /*Renderer*/GIMT_Encode2(0), GIMT_Encode2(GICP_gi_mubuf_offset),
      // (st v2f32:{ *:[v2f32] }:$vdata, (MUBUFOffset:{ *:[iPTR] } v4i32:{ *:[v4i32] }:$srsrc, i32:{ *:[i32] }:$soffset, i32:{ *:[i32] }:$offset))<<P:Predicate_unindexedstore>><<P:Predicate_store_global>>  =>  (BUFFER_STORE_DWORDX2_VBUFFER_OFFSET v2f32:{ *:[v2f32] }:$vdata, v4i32:{ *:[v4i32] }:$srsrc, i32:{ *:[i32] }:$soffset, i32:{ *:[i32] }:$offset)
      GIR_BuildMI, /*InsnID*/0, /*Opcode*/GIMT_Encode2(AMDGPU::BUFFER_STORE_DWORDX2_VBUFFER_OFFSET),
      GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/0, // vdata
      GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/0, // srsrc
      GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/1, // soffset
      GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/2, // offset
      GIR_AddImm8, /*InsnID*/0, /*Imm*/0,
      GIR_AddImm8, /*InsnID*/0, /*Imm*/0,
      GIR_MergeMemOperands, /*InsnID*/0, /*NumInsns*/1, /*MergeInsnID's*/0,
      GIR_ConstrainSelectedInstOperands, /*InsnID*/0,
      GIR_EraseFromParent, /*InsnID*/0,
      // GIR_Coverage, 3851,
      GIR_Done,
    // Label 2193: @144013
    GIM_Try, /*On fail goto*//*Label 2194*/ GIMT_Encode4(144133), // Rule ID 6686 //
      GIM_CheckFeatures, GIMT_Encode2(GIFBS_NotLDSRequiresM0Init),
      GIM_CheckMemoryAddressSpace, /*MI*/0, /*MMO*/0, /*NumAddrSpace*/1, /*AddrSpace*/3,
      GIM_CheckAtomicOrdering, /*MI*/0, /*Order*/(uint8_t)AtomicOrdering::NotAtomic,
      GIM_CheckPointerToAny, /*MI*/0, /*Op*/1, /*SizeInBits*/0,
      GIM_CheckComplexPattern, /*MI*/0, /*Op*/1, /*Renderer*/GIMT_Encode2(0), GIMT_Encode2(GICP_gi_ds_64bit_4byte_aligned),
      // (st v2i32:{ *:[v2i32] }:$value, (DS64Bit4ByteAligned:{ *:[iPTR] } i32:{ *:[i32] }:$ptr, i8:{ *:[i8] }:$offset0, i8:{ *:[i8] }:$offset1))<<P:Predicate_unindexedstore>><<P:Predicate_store_local>>  =>  (DS_WRITE2_B32_gfx9 ?:{ *:[i32] }:$ptr, (EXTRACT_SUBREG:{ *:[i32] } VReg_64:{ *:[v2i32] }:$value, sub0:{ *:[i32] }), (EXTRACT_SUBREG:{ *:[i32] } VReg_64:{ *:[v2i32] }:$value, sub1:{ *:[i32] }), ?:{ *:[i8] }:$offset0, ?:{ *:[i8] }:$offset1, 0:{ *:[i1] })
      GIR_MakeTempReg, /*TempRegID*/0, /*TypeID*/GILLT_s32,
      GIR_MakeTempReg, /*TempRegID*/1, /*TypeID*/GILLT_s32,
      GIR_BuildMI, /*InsnID*/2, /*Opcode*/GIMT_Encode2(TargetOpcode::COPY),
      GIR_AddTempRegister, /*InsnID*/2, /*TempRegID*/1, /*TempRegFlags*/GIMT_Encode2(RegState::Define),
      GIR_CopySubReg, /*NewInsnID*/2, /*OldInsnID*/0, /*OpIdx*/0, /*SubRegIdx*/GIMT_Encode2(11), // value
      GIR_ConstrainOperandRC, /*InsnID*/2, /*Op*/0, GIMT_Encode2(AMDGPU::VGPR_32RegClassID),
      GIR_ConstrainOperandRC, /*InsnID*/2, /*Op*/1, GIMT_Encode2(AMDGPU::VReg_64RegClassID),
      GIR_BuildMI, /*InsnID*/1, /*Opcode*/GIMT_Encode2(TargetOpcode::COPY),
      GIR_AddTempRegister, /*InsnID*/1, /*TempRegID*/0, /*TempRegFlags*/GIMT_Encode2(RegState::Define),
      GIR_CopySubReg, /*NewInsnID*/1, /*OldInsnID*/0, /*OpIdx*/0, /*SubRegIdx*/GIMT_Encode2(3), // value
      GIR_ConstrainOperandRC, /*InsnID*/1, /*Op*/0, GIMT_Encode2(AMDGPU::VGPR_32RegClassID),
      GIR_ConstrainOperandRC, /*InsnID*/1, /*Op*/1, GIMT_Encode2(AMDGPU::VReg_64RegClassID),
      GIR_BuildMI, /*InsnID*/0, /*Opcode*/GIMT_Encode2(AMDGPU::DS_WRITE2_B32_gfx9),
      GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/0, // ptr
      GIR_AddSimpleTempRegister, /*InsnID*/0, /*TempRegID*/0,
      GIR_AddSimpleTempRegister, /*InsnID*/0, /*TempRegID*/1,
      GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/1, // offset0
      GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/2, // offset1
      GIR_AddImm8, /*InsnID*/0, /*Imm*/0,
      GIR_MergeMemOperands, /*InsnID*/0, /*NumInsns*/1, /*MergeInsnID's*/0,
      GIR_ConstrainSelectedInstOperands, /*InsnID*/0,
      GIR_EraseFromParent, /*InsnID*/0,
      // GIR_Coverage, 6686,
      GIR_Done,
    // Label 2194: @144133
    GIM_Try, /*On fail goto*//*Label 2195*/ GIMT_Encode4(144253), // Rule ID 6690 //
      GIM_CheckFeatures, GIMT_Encode2(GIFBS_NotLDSRequiresM0Init),
      GIM_CheckMemoryAddressSpace, /*MI*/0, /*MMO*/0, /*NumAddrSpace*/1, /*AddrSpace*/3,
      GIM_CheckAtomicOrdering, /*MI*/0, /*Order*/(uint8_t)AtomicOrdering::NotAtomic,
      GIM_CheckPointerToAny, /*MI*/0, /*Op*/1, /*SizeInBits*/0,
      GIM_CheckComplexPattern, /*MI*/0, /*Op*/1, /*Renderer*/GIMT_Encode2(0), GIMT_Encode2(GICP_gi_ds_64bit_4byte_aligned),
      // (st v2f32:{ *:[v2f32] }:$value, (DS64Bit4ByteAligned:{ *:[iPTR] } i32:{ *:[i32] }:$ptr, i8:{ *:[i8] }:$offset0, i8:{ *:[i8] }:$offset1))<<P:Predicate_unindexedstore>><<P:Predicate_store_local>>  =>  (DS_WRITE2_B32_gfx9 ?:{ *:[i32] }:$ptr, (EXTRACT_SUBREG:{ *:[i32] } VReg_64:{ *:[v2f32] }:$value, sub0:{ *:[i32] }), (EXTRACT_SUBREG:{ *:[i32] } VReg_64:{ *:[v2f32] }:$value, sub1:{ *:[i32] }), ?:{ *:[i8] }:$offset0, ?:{ *:[i8] }:$offset1, 0:{ *:[i1] })
      GIR_MakeTempReg, /*TempRegID*/0, /*TypeID*/GILLT_s32,
      GIR_MakeTempReg, /*TempRegID*/1, /*TypeID*/GILLT_s32,
      GIR_BuildMI, /*InsnID*/2, /*Opcode*/GIMT_Encode2(TargetOpcode::COPY),
      GIR_AddTempRegister, /*InsnID*/2, /*TempRegID*/1, /*TempRegFlags*/GIMT_Encode2(RegState::Define),
      GIR_CopySubReg, /*NewInsnID*/2, /*OldInsnID*/0, /*OpIdx*/0, /*SubRegIdx*/GIMT_Encode2(11), // value
      GIR_ConstrainOperandRC, /*InsnID*/2, /*Op*/0, GIMT_Encode2(AMDGPU::VGPR_32RegClassID),
      GIR_ConstrainOperandRC, /*InsnID*/2, /*Op*/1, GIMT_Encode2(AMDGPU::VReg_64RegClassID),
      GIR_BuildMI, /*InsnID*/1, /*Opcode*/GIMT_Encode2(TargetOpcode::COPY),
      GIR_AddTempRegister, /*InsnID*/1, /*TempRegID*/0, /*TempRegFlags*/GIMT_Encode2(RegState::Define),
      GIR_CopySubReg, /*NewInsnID*/1, /*OldInsnID*/0, /*OpIdx*/0, /*SubRegIdx*/GIMT_Encode2(3), // value
      GIR_ConstrainOperandRC, /*InsnID*/1, /*Op*/0, GIMT_Encode2(AMDGPU::VGPR_32RegClassID),
      GIR_ConstrainOperandRC, /*InsnID*/1, /*Op*/1, GIMT_Encode2(AMDGPU::VReg_64RegClassID),
      GIR_BuildMI, /*InsnID*/0, /*Opcode*/GIMT_Encode2(AMDGPU::DS_WRITE2_B32_gfx9),
      GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/0, // ptr
      GIR_AddSimpleTempRegister, /*InsnID*/0, /*TempRegID*/0,
      GIR_AddSimpleTempRegister, /*InsnID*/0, /*TempRegID*/1,
      GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/1, // offset0
      GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/2, // offset1
      GIR_AddImm8, /*InsnID*/0, /*Imm*/0,
      GIR_MergeMemOperands, /*InsnID*/0, /*NumInsns*/1, /*MergeInsnID's*/0,
      GIR_ConstrainSelectedInstOperands, /*InsnID*/0,
      GIR_EraseFromParent, /*InsnID*/0,
      // GIR_Coverage, 6690,
      GIR_Done,
    // Label 2195: @144253
    GIM_Try, /*On fail goto*//*Label 2196*/ GIMT_Encode4(144315), // Rule ID 3039 //
      GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasFlatGlobalInsts),
      GIM_CheckMemoryAddressSpace, /*MI*/0, /*MMO*/0, /*NumAddrSpace*/1, /*AddrSpace*/1,
      GIM_CheckAtomicOrdering, /*MI*/0, /*Order*/(uint8_t)AtomicOrdering::NotAtomic,
      GIM_CheckPointerToAny, /*MI*/0, /*Op*/1, /*SizeInBits*/0,
      GIM_CheckComplexPattern, /*MI*/0, /*Op*/1, /*Renderer*/GIMT_Encode2(0), GIMT_Encode2(GICP_gi_global_saddr),
      // (st v2i32:{ *:[v2i32] }:$data, (GlobalSAddr:{ *:[iPTR] } SReg_64:{ *:[i64] }:$saddr, VGPR_32:{ *:[i32] }:$voffset, i32:{ *:[i32] }:$offset))<<P:Predicate_unindexedstore>><<P:Predicate_store_global>>  =>  (GLOBAL_STORE_DWORDX2_SADDR ?:{ *:[i32] }:$voffset, anonymous_15036:{ *:[v2i32] }:$data, ?:{ *:[i64] }:$saddr, ?:{ *:[i32] }:$offset)
      GIR_BuildMI, /*InsnID*/0, /*Opcode*/GIMT_Encode2(AMDGPU::GLOBAL_STORE_DWORDX2_SADDR),
      GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/1, // voffset
      GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/0, // data
      GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/0, // saddr
      GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/2, // offset
      GIR_AddImm8, /*InsnID*/0, /*Imm*/0,
      GIR_MergeMemOperands, /*InsnID*/0, /*NumInsns*/1, /*MergeInsnID's*/0,
      GIR_ConstrainSelectedInstOperands, /*InsnID*/0,
      GIR_EraseFromParent, /*InsnID*/0,
      // GIR_Coverage, 3039,
      GIR_Done,
    // Label 2196: @144315
    GIM_Try, /*On fail goto*//*Label 2197*/ GIMT_Encode4(144377), // Rule ID 3043 //
      GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasFlatGlobalInsts),
      GIM_CheckMemoryAddressSpace, /*MI*/0, /*MMO*/0, /*NumAddrSpace*/1, /*AddrSpace*/1,
      GIM_CheckAtomicOrdering, /*MI*/0, /*Order*/(uint8_t)AtomicOrdering::NotAtomic,
      GIM_CheckPointerToAny, /*MI*/0, /*Op*/1, /*SizeInBits*/0,
      GIM_CheckComplexPattern, /*MI*/0, /*Op*/1, /*Renderer*/GIMT_Encode2(0), GIMT_Encode2(GICP_gi_global_saddr),
      // (st v2f32:{ *:[v2f32] }:$data, (GlobalSAddr:{ *:[iPTR] } SReg_64:{ *:[i64] }:$saddr, VGPR_32:{ *:[i32] }:$voffset, i32:{ *:[i32] }:$offset))<<P:Predicate_unindexedstore>><<P:Predicate_store_global>>  =>  (GLOBAL_STORE_DWORDX2_SADDR ?:{ *:[i32] }:$voffset, anonymous_15036:{ *:[v2f32] }:$data, ?:{ *:[i64] }:$saddr, ?:{ *:[i32] }:$offset)
      GIR_BuildMI, /*InsnID*/0, /*Opcode*/GIMT_Encode2(AMDGPU::GLOBAL_STORE_DWORDX2_SADDR),
      GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/1, // voffset
      GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/0, // data
      GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/0, // saddr
      GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/2, // offset
      GIR_AddImm8, /*InsnID*/0, /*Imm*/0,
      GIR_MergeMemOperands, /*InsnID*/0, /*NumInsns*/1, /*MergeInsnID's*/0,
      GIR_ConstrainSelectedInstOperands, /*InsnID*/0,
      GIR_EraseFromParent, /*InsnID*/0,
      // GIR_Coverage, 3043,
      GIR_Done,
    // Label 2197: @144377
    GIM_Try, /*On fail goto*//*Label 2198*/ GIMT_Encode4(144434), // Rule ID 3038 //
      GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasFlatGlobalInsts),
      GIM_CheckMemoryAddressSpace, /*MI*/0, /*MMO*/0, /*NumAddrSpace*/1, /*AddrSpace*/1,
      GIM_CheckAtomicOrdering, /*MI*/0, /*Order*/(uint8_t)AtomicOrdering::NotAtomic,
      GIM_CheckPointerToAny, /*MI*/0, /*Op*/1, /*SizeInBits*/0,
      GIM_CheckComplexPattern, /*MI*/0, /*Op*/1, /*Renderer*/GIMT_Encode2(0), GIMT_Encode2(GICP_gi_global_offset),
      // (st v2i32:{ *:[v2i32] }:$data, (GlobalOffset:{ *:[iPTR] } i64:{ *:[i64] }:$vaddr, i32:{ *:[i32] }:$offset))<<P:Predicate_unindexedstore>><<P:Predicate_store_global>>  =>  (GLOBAL_STORE_DWORDX2 ?:{ *:[i64] }:$vaddr, anonymous_15036:{ *:[v2i32] }:$data, ?:{ *:[i32] }:$offset)
      GIR_BuildMI, /*InsnID*/0, /*Opcode*/GIMT_Encode2(AMDGPU::GLOBAL_STORE_DWORDX2),
      GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/0, // vaddr
      GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/0, // data
      GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/1, // offset
      GIR_AddImm8, /*InsnID*/0, /*Imm*/0,
      GIR_MergeMemOperands, /*InsnID*/0, /*NumInsns*/1, /*MergeInsnID's*/0,
      GIR_ConstrainSelectedInstOperands, /*InsnID*/0,
      GIR_EraseFromParent, /*InsnID*/0,
      // GIR_Coverage, 3038,
      GIR_Done,
    // Label 2198: @144434
    GIM_Try, /*On fail goto*//*Label 2199*/ GIMT_Encode4(144491), // Rule ID 3042 //
      GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasFlatGlobalInsts),
      GIM_CheckMemoryAddressSpace, /*MI*/0, /*MMO*/0, /*NumAddrSpace*/1, /*AddrSpace*/1,
      GIM_CheckAtomicOrdering, /*MI*/0, /*Order*/(uint8_t)AtomicOrdering::NotAtomic,
      GIM_CheckPointerToAny, /*MI*/0, /*Op*/1, /*SizeInBits*/0,
      GIM_CheckComplexPattern, /*MI*/0, /*Op*/1, /*Renderer*/GIMT_Encode2(0), GIMT_Encode2(GICP_gi_global_offset),
      // (st v2f32:{ *:[v2f32] }:$data, (GlobalOffset:{ *:[iPTR] } i64:{ *:[i64] }:$vaddr, i32:{ *:[i32] }:$offset))<<P:Predicate_unindexedstore>><<P:Predicate_store_global>>  =>  (GLOBAL_STORE_DWORDX2 ?:{ *:[i64] }:$vaddr, anonymous_15036:{ *:[v2f32] }:$data, ?:{ *:[i32] }:$offset)
      GIR_BuildMI, /*InsnID*/0, /*Opcode*/GIMT_Encode2(AMDGPU::GLOBAL_STORE_DWORDX2),
      GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/0, // vaddr
      GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/0, // data
      GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/1, // offset
      GIR_AddImm8, /*InsnID*/0, /*Imm*/0,
      GIR_MergeMemOperands, /*InsnID*/0, /*NumInsns*/1, /*MergeInsnID's*/0,
      GIR_ConstrainSelectedInstOperands, /*InsnID*/0,
      GIR_EraseFromParent, /*InsnID*/0,
      // GIR_Coverage, 3042,
      GIR_Done,
    // Label 2199: @144491
    GIM_Try, /*On fail goto*//*Label 2200*/ GIMT_Encode4(144549), // Rule ID 2792 //
      GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasFlatAddressSpace),
      GIM_CheckMemoryAddressSpace, /*MI*/0, /*MMO*/0, /*NumAddrSpace*/2, /*AddrSpace*/0, /*AddrSpace*/1,
      GIM_CheckAtomicOrdering, /*MI*/0, /*Order*/(uint8_t)AtomicOrdering::NotAtomic,
      GIM_CheckPointerToAny, /*MI*/0, /*Op*/1, /*SizeInBits*/0,
      GIM_CheckComplexPattern, /*MI*/0, /*Op*/1, /*Renderer*/GIMT_Encode2(0), GIMT_Encode2(GICP_gi_flat_offset),
      // (st v2i32:{ *:[v2i32] }:$data, (FlatOffset:{ *:[iPTR] } i64:{ *:[i64] }:$vaddr, i32:{ *:[i32] }:$offset))<<P:Predicate_unindexedstore>><<P:Predicate_store_flat>>  =>  (FLAT_STORE_DWORDX2 ?:{ *:[i64] }:$vaddr, anonymous_15036:{ *:[v2i32] }:$data, ?:{ *:[i32] }:$offset)
      GIR_BuildMI, /*InsnID*/0, /*Opcode*/GIMT_Encode2(AMDGPU::FLAT_STORE_DWORDX2),
      GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/0, // vaddr
      GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/0, // data
      GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/1, // offset
      GIR_AddImm8, /*InsnID*/0, /*Imm*/0,
      GIR_MergeMemOperands, /*InsnID*/0, /*NumInsns*/1, /*MergeInsnID's*/0,
      GIR_ConstrainSelectedInstOperands, /*InsnID*/0,
      GIR_EraseFromParent, /*InsnID*/0,
      // GIR_Coverage, 2792,
      GIR_Done,
    // Label 2200: @144549
    GIM_Try, /*On fail goto*//*Label 2201*/ GIMT_Encode4(144607), // Rule ID 2794 //
      GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasFlatAddressSpace),
      GIM_CheckMemoryAddressSpace, /*MI*/0, /*MMO*/0, /*NumAddrSpace*/2, /*AddrSpace*/0, /*AddrSpace*/1,
      GIM_CheckAtomicOrdering, /*MI*/0, /*Order*/(uint8_t)AtomicOrdering::NotAtomic,
      GIM_CheckPointerToAny, /*MI*/0, /*Op*/1, /*SizeInBits*/0,
      GIM_CheckComplexPattern, /*MI*/0, /*Op*/1, /*Renderer*/GIMT_Encode2(0), GIMT_Encode2(GICP_gi_flat_offset),
      // (st v2f32:{ *:[v2f32] }:$data, (FlatOffset:{ *:[iPTR] } i64:{ *:[i64] }:$vaddr, i32:{ *:[i32] }:$offset))<<P:Predicate_unindexedstore>><<P:Predicate_store_flat>>  =>  (FLAT_STORE_DWORDX2 ?:{ *:[i64] }:$vaddr, anonymous_15036:{ *:[v2f32] }:$data, ?:{ *:[i32] }:$offset)
      GIR_BuildMI, /*InsnID*/0, /*Opcode*/GIMT_Encode2(AMDGPU::FLAT_STORE_DWORDX2),
      GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/0, // vaddr
      GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/0, // data
      GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/1, // offset
      GIR_AddImm8, /*InsnID*/0, /*Imm*/0,
      GIR_MergeMemOperands, /*InsnID*/0, /*NumInsns*/1, /*MergeInsnID's*/0,
      GIR_ConstrainSelectedInstOperands, /*InsnID*/0,
      GIR_EraseFromParent, /*InsnID*/0,
      // GIR_Coverage, 2794,
      GIR_Done,
    // Label 2201: @144607
    GIM_Reject,
    // Label 1818: @144608
    GIM_Try, /*On fail goto*//*Label 2202*/ GIMT_Encode4(144678), // Rule ID 6873 //
      GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasUnalignedAccessMode_LDSRequiresM0Init),
      GIM_CheckMemorySizeEqualToLLT, /*MI*/0, /*MMO*/0, /*OpIdx*/0,
      GIM_CheckMemoryAddressSpace, /*MI*/0, /*MMO*/0, /*NumAddrSpace*/1, /*AddrSpace*/3,
      GIM_CheckMemoryAddressSpace, /*MI*/0, /*MMO*/0, /*NumAddrSpace*/1, /*AddrSpace*/3,
      GIM_CheckAtomicOrdering, /*MI*/0, /*Order*/(uint8_t)AtomicOrdering::NotAtomic,
      GIM_CheckPointerToAny, /*MI*/0, /*Op*/1, /*SizeInBits*/0,
      GIM_CheckCxxInsnPredicate, /*MI*/0, /*FnId*/GIMT_Encode2(GICXXPred_MI_Predicate_store_align_less_than_4_local_m0),
      GIM_CheckComplexPattern, /*MI*/0, /*Op*/1, /*Renderer*/GIMT_Encode2(0), GIMT_Encode2(GICP_gi_ds_1addr_1offset),
      // (AMDGPUst_glue v2i64:{ *:[v2i64] }:$value, (DS1Addr1Offset:{ *:[iPTR] } i32:{ *:[i32] }:$ptr, i32:{ *:[i32] }:$offset))<<P:Predicate_unindexedstore_glue>><<P:Predicate_store_glue>><<P:Predicate_store_local_m0>><<P:Predicate_store_align_less_than_4_local_m0>>  =>  (DS_WRITE_B128 ?:{ *:[i32] }:$ptr, anonymous_15034:{ *:[v2i64] }:$value, offset:{ *:[i32] }:$offset, 0:{ *:[i1] })
      GIR_BuildMI, /*InsnID*/0, /*Opcode*/GIMT_Encode2(AMDGPU::DS_WRITE_B128),
      GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/0, // ptr
      GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/0, // value
      GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/1, // offset
      GIR_AddImm8, /*InsnID*/0, /*Imm*/0,
      GIR_MergeMemOperands, /*InsnID*/0, /*NumInsns*/1, /*MergeInsnID's*/0,
      GIR_ConstrainSelectedInstOperands, /*InsnID*/0,
      GIR_EraseFromParent, /*InsnID*/0,
      // GIR_Coverage, 6873,
      GIR_Done,
    // Label 2202: @144678
    GIM_Try, /*On fail goto*//*Label 2203*/ GIMT_Encode4(144748), // Rule ID 6877 //
      GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasUnalignedAccessMode_LDSRequiresM0Init),
      GIM_CheckMemorySizeEqualToLLT, /*MI*/0, /*MMO*/0, /*OpIdx*/0,
      GIM_CheckMemoryAddressSpace, /*MI*/0, /*MMO*/0, /*NumAddrSpace*/1, /*AddrSpace*/3,
      GIM_CheckMemoryAddressSpace, /*MI*/0, /*MMO*/0, /*NumAddrSpace*/1, /*AddrSpace*/3,
      GIM_CheckAtomicOrdering, /*MI*/0, /*Order*/(uint8_t)AtomicOrdering::NotAtomic,
      GIM_CheckPointerToAny, /*MI*/0, /*Op*/1, /*SizeInBits*/0,
      GIM_CheckCxxInsnPredicate, /*MI*/0, /*FnId*/GIMT_Encode2(GICXXPred_MI_Predicate_store_align_less_than_4_local_m0),
      GIM_CheckComplexPattern, /*MI*/0, /*Op*/1, /*Renderer*/GIMT_Encode2(0), GIMT_Encode2(GICP_gi_ds_1addr_1offset),
      // (AMDGPUst_glue v2f64:{ *:[v2f64] }:$value, (DS1Addr1Offset:{ *:[iPTR] } i32:{ *:[i32] }:$ptr, i32:{ *:[i32] }:$offset))<<P:Predicate_unindexedstore_glue>><<P:Predicate_store_glue>><<P:Predicate_store_local_m0>><<P:Predicate_store_align_less_than_4_local_m0>>  =>  (DS_WRITE_B128 ?:{ *:[i32] }:$ptr, anonymous_15034:{ *:[v2f64] }:$value, offset:{ *:[i32] }:$offset, 0:{ *:[i1] })
      GIR_BuildMI, /*InsnID*/0, /*Opcode*/GIMT_Encode2(AMDGPU::DS_WRITE_B128),
      GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/0, // ptr
      GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/0, // value
      GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/1, // offset
      GIR_AddImm8, /*InsnID*/0, /*Imm*/0,
      GIR_MergeMemOperands, /*InsnID*/0, /*NumInsns*/1, /*MergeInsnID's*/0,
      GIR_ConstrainSelectedInstOperands, /*InsnID*/0,
      GIR_EraseFromParent, /*InsnID*/0,
      // GIR_Coverage, 6877,
      GIR_Done,
    // Label 2203: @144748
    GIM_Try, /*On fail goto*//*Label 2204*/ GIMT_Encode4(144813), // Rule ID 6797 //
      GIM_CheckFeatures, GIMT_Encode2(GIFBS_LDSRequiresM0Init_isGFX7Plus),
      GIM_CheckMemorySizeEqualToLLT, /*MI*/0, /*MMO*/0, /*OpIdx*/0,
      GIM_CheckMemoryAddressSpace, /*MI*/0, /*MMO*/0, /*NumAddrSpace*/1, /*AddrSpace*/3,
      GIM_CheckMemoryAlignment, /*MI*/0, /*MMO*/0, /*MinAlign*/16,
      GIM_CheckAtomicOrdering, /*MI*/0, /*Order*/(uint8_t)AtomicOrdering::NotAtomic,
      GIM_CheckPointerToAny, /*MI*/0, /*Op*/1, /*SizeInBits*/0,
      GIM_CheckComplexPattern, /*MI*/0, /*Op*/1, /*Renderer*/GIMT_Encode2(0), GIMT_Encode2(GICP_gi_ds_1addr_1offset),
      // (AMDGPUst_glue v2i64:{ *:[v2i64] }:$value, (DS1Addr1Offset:{ *:[iPTR] } i32:{ *:[i32] }:$ptr, i32:{ *:[i32] }:$offset))<<P:Predicate_unindexedstore_glue>><<P:Predicate_store_glue>><<P:Predicate_store_local_m0>><<P:Predicate_store_align16_local_m0>>  =>  (DS_WRITE_B128 ?:{ *:[i32] }:$ptr, anonymous_15034:{ *:[v2i64] }:$value, offset:{ *:[i32] }:$offset, 0:{ *:[i1] })
      GIR_BuildMI, /*InsnID*/0, /*Opcode*/GIMT_Encode2(AMDGPU::DS_WRITE_B128),
      GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/0, // ptr
      GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/0, // value
      GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/1, // offset
      GIR_AddImm8, /*InsnID*/0, /*Imm*/0,
      GIR_MergeMemOperands, /*InsnID*/0, /*NumInsns*/1, /*MergeInsnID's*/0,
      GIR_ConstrainSelectedInstOperands, /*InsnID*/0,
      GIR_EraseFromParent, /*InsnID*/0,
      // GIR_Coverage, 6797,
      GIR_Done,
    // Label 2204: @144813
    GIM_Try, /*On fail goto*//*Label 2205*/ GIMT_Encode4(144878), // Rule ID 6801 //
      GIM_CheckFeatures, GIMT_Encode2(GIFBS_LDSRequiresM0Init_isGFX7Plus),
      GIM_CheckMemorySizeEqualToLLT, /*MI*/0, /*MMO*/0, /*OpIdx*/0,
      GIM_CheckMemoryAddressSpace, /*MI*/0, /*MMO*/0, /*NumAddrSpace*/1, /*AddrSpace*/3,
      GIM_CheckMemoryAlignment, /*MI*/0, /*MMO*/0, /*MinAlign*/16,
      GIM_CheckAtomicOrdering, /*MI*/0, /*Order*/(uint8_t)AtomicOrdering::NotAtomic,
      GIM_CheckPointerToAny, /*MI*/0, /*Op*/1, /*SizeInBits*/0,
      GIM_CheckComplexPattern, /*MI*/0, /*Op*/1, /*Renderer*/GIMT_Encode2(0), GIMT_Encode2(GICP_gi_ds_1addr_1offset),
      // (AMDGPUst_glue v2f64:{ *:[v2f64] }:$value, (DS1Addr1Offset:{ *:[iPTR] } i32:{ *:[i32] }:$ptr, i32:{ *:[i32] }:$offset))<<P:Predicate_unindexedstore_glue>><<P:Predicate_store_glue>><<P:Predicate_store_local_m0>><<P:Predicate_store_align16_local_m0>>  =>  (DS_WRITE_B128 ?:{ *:[i32] }:$ptr, anonymous_15034:{ *:[v2f64] }:$value, offset:{ *:[i32] }:$offset, 0:{ *:[i1] })
      GIR_BuildMI, /*InsnID*/0, /*Opcode*/GIMT_Encode2(AMDGPU::DS_WRITE_B128),
      GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/0, // ptr
      GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/0, // value
      GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/1, // offset
      GIR_AddImm8, /*InsnID*/0, /*Imm*/0,
      GIR_MergeMemOperands, /*InsnID*/0, /*NumInsns*/1, /*MergeInsnID's*/0,
      GIR_ConstrainSelectedInstOperands, /*InsnID*/0,
      GIR_EraseFromParent, /*InsnID*/0,
      // GIR_Coverage, 6801,
      GIR_Done,
    // Label 2205: @144878
    GIM_Try, /*On fail goto*//*Label 2206*/ GIMT_Encode4(144944), // Rule ID 6874 //
      GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasUnalignedAccessMode_NotLDSRequiresM0Init),
      GIM_CheckMemoryAddressSpace, /*MI*/0, /*MMO*/0, /*NumAddrSpace*/1, /*AddrSpace*/3,
      GIM_CheckMemoryAddressSpace, /*MI*/0, /*MMO*/0, /*NumAddrSpace*/1, /*AddrSpace*/3,
      GIM_CheckAtomicOrdering, /*MI*/0, /*Order*/(uint8_t)AtomicOrdering::NotAtomic,
      GIM_CheckPointerToAny, /*MI*/0, /*Op*/1, /*SizeInBits*/0,
      GIM_CheckCxxInsnPredicate, /*MI*/0, /*FnId*/GIMT_Encode2(GICXXPred_MI_Predicate_store_align_less_than_4_local),
      GIM_CheckComplexPattern, /*MI*/0, /*Op*/1, /*Renderer*/GIMT_Encode2(0), GIMT_Encode2(GICP_gi_ds_1addr_1offset),
      // (st v2i64:{ *:[v2i64] }:$value, (DS1Addr1Offset:{ *:[iPTR] } i32:{ *:[i32] }:$ptr, i32:{ *:[i32] }:$offset))<<P:Predicate_unindexedstore>><<P:Predicate_store_local>><<P:Predicate_store_align_less_than_4_local>>  =>  (DS_WRITE_B128_gfx9 ?:{ *:[i32] }:$ptr, anonymous_15034:{ *:[v2i64] }:$value, offset:{ *:[i32] }:$offset, 0:{ *:[i1] })
      GIR_BuildMI, /*InsnID*/0, /*Opcode*/GIMT_Encode2(AMDGPU::DS_WRITE_B128_gfx9),
      GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/0, // ptr
      GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/0, // value
      GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/1, // offset
      GIR_AddImm8, /*InsnID*/0, /*Imm*/0,
      GIR_MergeMemOperands, /*InsnID*/0, /*NumInsns*/1, /*MergeInsnID's*/0,
      GIR_ConstrainSelectedInstOperands, /*InsnID*/0,
      GIR_EraseFromParent, /*InsnID*/0,
      // GIR_Coverage, 6874,
      GIR_Done,
    // Label 2206: @144944
    GIM_Try, /*On fail goto*//*Label 2207*/ GIMT_Encode4(145010), // Rule ID 6878 //
      GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasUnalignedAccessMode_NotLDSRequiresM0Init),
      GIM_CheckMemoryAddressSpace, /*MI*/0, /*MMO*/0, /*NumAddrSpace*/1, /*AddrSpace*/3,
      GIM_CheckMemoryAddressSpace, /*MI*/0, /*MMO*/0, /*NumAddrSpace*/1, /*AddrSpace*/3,
      GIM_CheckAtomicOrdering, /*MI*/0, /*Order*/(uint8_t)AtomicOrdering::NotAtomic,
      GIM_CheckPointerToAny, /*MI*/0, /*Op*/1, /*SizeInBits*/0,
      GIM_CheckCxxInsnPredicate, /*MI*/0, /*FnId*/GIMT_Encode2(GICXXPred_MI_Predicate_store_align_less_than_4_local),
      GIM_CheckComplexPattern, /*MI*/0, /*Op*/1, /*Renderer*/GIMT_Encode2(0), GIMT_Encode2(GICP_gi_ds_1addr_1offset),
      // (st v2f64:{ *:[v2f64] }:$value, (DS1Addr1Offset:{ *:[iPTR] } i32:{ *:[i32] }:$ptr, i32:{ *:[i32] }:$offset))<<P:Predicate_unindexedstore>><<P:Predicate_store_local>><<P:Predicate_store_align_less_than_4_local>>  =>  (DS_WRITE_B128_gfx9 ?:{ *:[i32] }:$ptr, anonymous_15034:{ *:[v2f64] }:$value, offset:{ *:[i32] }:$offset, 0:{ *:[i1] })
      GIR_BuildMI, /*InsnID*/0, /*Opcode*/GIMT_Encode2(AMDGPU::DS_WRITE_B128_gfx9),
      GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/0, // ptr
      GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/0, // value
      GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/1, // offset
      GIR_AddImm8, /*InsnID*/0, /*Imm*/0,
      GIR_MergeMemOperands, /*InsnID*/0, /*NumInsns*/1, /*MergeInsnID's*/0,
      GIR_ConstrainSelectedInstOperands, /*InsnID*/0,
      GIR_EraseFromParent, /*InsnID*/0,
      // GIR_Coverage, 6878,
      GIR_Done,
    // Label 2207: @145010
    GIM_Try, /*On fail goto*//*Label 2208*/ GIMT_Encode4(145071), // Rule ID 6798 //
      GIM_CheckFeatures, GIMT_Encode2(GIFBS_NotLDSRequiresM0Init_isGFX7Plus),
      GIM_CheckMemoryAddressSpace, /*MI*/0, /*MMO*/0, /*NumAddrSpace*/1, /*AddrSpace*/3,
      GIM_CheckMemoryAlignment, /*MI*/0, /*MMO*/0, /*MinAlign*/16,
      GIM_CheckAtomicOrdering, /*MI*/0, /*Order*/(uint8_t)AtomicOrdering::NotAtomic,
      GIM_CheckPointerToAny, /*MI*/0, /*Op*/1, /*SizeInBits*/0,
      GIM_CheckComplexPattern, /*MI*/0, /*Op*/1, /*Renderer*/GIMT_Encode2(0), GIMT_Encode2(GICP_gi_ds_1addr_1offset),
      // (st v2i64:{ *:[v2i64] }:$value, (DS1Addr1Offset:{ *:[iPTR] } i32:{ *:[i32] }:$ptr, i32:{ *:[i32] }:$offset))<<P:Predicate_unindexedstore>><<P:Predicate_store_local>><<P:Predicate_store_align16_local>>  =>  (DS_WRITE_B128_gfx9 ?:{ *:[i32] }:$ptr, anonymous_15034:{ *:[v2i64] }:$value, offset:{ *:[i32] }:$offset, 0:{ *:[i1] })
      GIR_BuildMI, /*InsnID*/0, /*Opcode*/GIMT_Encode2(AMDGPU::DS_WRITE_B128_gfx9),
      GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/0, // ptr
      GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/0, // value
      GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/1, // offset
      GIR_AddImm8, /*InsnID*/0, /*Imm*/0,
      GIR_MergeMemOperands, /*InsnID*/0, /*NumInsns*/1, /*MergeInsnID's*/0,
      GIR_ConstrainSelectedInstOperands, /*InsnID*/0,
      GIR_EraseFromParent, /*InsnID*/0,
      // GIR_Coverage, 6798,
      GIR_Done,
    // Label 2208: @145071
    GIM_Try, /*On fail goto*//*Label 2209*/ GIMT_Encode4(145132), // Rule ID 6802 //
      GIM_CheckFeatures, GIMT_Encode2(GIFBS_NotLDSRequiresM0Init_isGFX7Plus),
      GIM_CheckMemoryAddressSpace, /*MI*/0, /*MMO*/0, /*NumAddrSpace*/1, /*AddrSpace*/3,
      GIM_CheckMemoryAlignment, /*MI*/0, /*MMO*/0, /*MinAlign*/16,
      GIM_CheckAtomicOrdering, /*MI*/0, /*Order*/(uint8_t)AtomicOrdering::NotAtomic,
      GIM_CheckPointerToAny, /*MI*/0, /*Op*/1, /*SizeInBits*/0,
      GIM_CheckComplexPattern, /*MI*/0, /*Op*/1, /*Renderer*/GIMT_Encode2(0), GIMT_Encode2(GICP_gi_ds_1addr_1offset),
      // (st v2f64:{ *:[v2f64] }:$value, (DS1Addr1Offset:{ *:[iPTR] } i32:{ *:[i32] }:$ptr, i32:{ *:[i32] }:$offset))<<P:Predicate_unindexedstore>><<P:Predicate_store_local>><<P:Predicate_store_align16_local>>  =>  (DS_WRITE_B128_gfx9 ?:{ *:[i32] }:$ptr, anonymous_15034:{ *:[v2f64] }:$value, offset:{ *:[i32] }:$offset, 0:{ *:[i1] })
      GIR_BuildMI, /*InsnID*/0, /*Opcode*/GIMT_Encode2(AMDGPU::DS_WRITE_B128_gfx9),
      GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/0, // ptr
      GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/0, // value
      GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/1, // offset
      GIR_AddImm8, /*InsnID*/0, /*Imm*/0,
      GIR_MergeMemOperands, /*InsnID*/0, /*NumInsns*/1, /*MergeInsnID's*/0,
      GIR_ConstrainSelectedInstOperands, /*InsnID*/0,
      GIR_EraseFromParent, /*InsnID*/0,
      // GIR_Coverage, 6802,
      GIR_Done,
    // Label 2209: @145132
    GIM_Try, /*On fail goto*//*Label 2210*/ GIMT_Encode4(145194), // Rule ID 3562 //
      GIM_CheckFeatures, GIMT_Encode2(GIFBS_EnableFlatScratch_HasFlatScratchInsts_HasFlatScratchSVSMode),
      GIM_CheckMemoryAddressSpace, /*MI*/0, /*MMO*/0, /*NumAddrSpace*/1, /*AddrSpace*/5,
      GIM_CheckAtomicOrdering, /*MI*/0, /*Order*/(uint8_t)AtomicOrdering::NotAtomic,
      GIM_CheckPointerToAny, /*MI*/0, /*Op*/1, /*SizeInBits*/0,
      GIM_CheckComplexPattern, /*MI*/0, /*Op*/1, /*Renderer*/GIMT_Encode2(0), GIMT_Encode2(GICP_gi_flat_scratch_svaddr),
      // (st v2i64:{ *:[v2i64] }:$data, (ScratchSVAddr:{ *:[iPTR] } VGPR_32:{ *:[i32] }:$vaddr, SGPR_32:{ *:[i32] }:$saddr, i32:{ *:[i32] }:$offset))<<P:Predicate_unindexedstore>><<P:Predicate_store_private>>  =>  (SCRATCH_STORE_DWORDX4_SVS anonymous_15034:{ *:[v2i64] }:$data, ?:{ *:[i32] }:$vaddr, ?:{ *:[i32] }:$saddr, ?:{ *:[i32] }:$offset)
      GIR_BuildMI, /*InsnID*/0, /*Opcode*/GIMT_Encode2(AMDGPU::SCRATCH_STORE_DWORDX4_SVS),
      GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/0, // data
      GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/0, // vaddr
      GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/1, // saddr
      GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/2, // offset
      GIR_AddImm8, /*InsnID*/0, /*Imm*/0,
      GIR_MergeMemOperands, /*InsnID*/0, /*NumInsns*/1, /*MergeInsnID's*/0,
      GIR_ConstrainSelectedInstOperands, /*InsnID*/0,
      GIR_EraseFromParent, /*InsnID*/0,
      // GIR_Coverage, 3562,
      GIR_Done,
    // Label 2210: @145194
    GIM_Try, /*On fail goto*//*Label 2211*/ GIMT_Encode4(145256), // Rule ID 3568 //
      GIM_CheckFeatures, GIMT_Encode2(GIFBS_EnableFlatScratch_HasFlatScratchInsts_HasFlatScratchSVSMode),
      GIM_CheckMemoryAddressSpace, /*MI*/0, /*MMO*/0, /*NumAddrSpace*/1, /*AddrSpace*/5,
      GIM_CheckAtomicOrdering, /*MI*/0, /*Order*/(uint8_t)AtomicOrdering::NotAtomic,
      GIM_CheckPointerToAny, /*MI*/0, /*Op*/1, /*SizeInBits*/0,
      GIM_CheckComplexPattern, /*MI*/0, /*Op*/1, /*Renderer*/GIMT_Encode2(0), GIMT_Encode2(GICP_gi_flat_scratch_svaddr),
      // (st v2f64:{ *:[v2f64] }:$data, (ScratchSVAddr:{ *:[iPTR] } VGPR_32:{ *:[i32] }:$vaddr, SGPR_32:{ *:[i32] }:$saddr, i32:{ *:[i32] }:$offset))<<P:Predicate_unindexedstore>><<P:Predicate_store_private>>  =>  (SCRATCH_STORE_DWORDX4_SVS anonymous_15034:{ *:[v2f64] }:$data, ?:{ *:[i32] }:$vaddr, ?:{ *:[i32] }:$saddr, ?:{ *:[i32] }:$offset)
      GIR_BuildMI, /*InsnID*/0, /*Opcode*/GIMT_Encode2(AMDGPU::SCRATCH_STORE_DWORDX4_SVS),
      GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/0, // data
      GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/0, // vaddr
      GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/1, // saddr
      GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/2, // offset
      GIR_AddImm8, /*InsnID*/0, /*Imm*/0,
      GIR_MergeMemOperands, /*InsnID*/0, /*NumInsns*/1, /*MergeInsnID's*/0,
      GIR_ConstrainSelectedInstOperands, /*InsnID*/0,
      GIR_EraseFromParent, /*InsnID*/0,
      // GIR_Coverage, 3568,
      GIR_Done,
    // Label 2211: @145256
    GIM_Try, /*On fail goto*//*Label 2212*/ GIMT_Encode4(145313), // Rule ID 3561 //
      GIM_CheckFeatures, GIMT_Encode2(GIFBS_EnableFlatScratch_HasFlatScratchInsts),
      GIM_CheckMemoryAddressSpace, /*MI*/0, /*MMO*/0, /*NumAddrSpace*/1, /*AddrSpace*/5,
      GIM_CheckAtomicOrdering, /*MI*/0, /*Order*/(uint8_t)AtomicOrdering::NotAtomic,
      GIM_CheckPointerToAny, /*MI*/0, /*Op*/1, /*SizeInBits*/0,
      GIM_CheckComplexPattern, /*MI*/0, /*Op*/1, /*Renderer*/GIMT_Encode2(0), GIMT_Encode2(GICP_gi_flat_scratch_saddr),
      // (st v2i64:{ *:[v2i64] }:$data, (ScratchSAddr:{ *:[iPTR] } SGPR_32:{ *:[i32] }:$saddr, i32:{ *:[i32] }:$offset))<<P:Predicate_unindexedstore>><<P:Predicate_store_private>>  =>  (SCRATCH_STORE_DWORDX4_SADDR anonymous_15034:{ *:[v2i64] }:$data, ?:{ *:[i32] }:$saddr, ?:{ *:[i32] }:$offset)
      GIR_BuildMI, /*InsnID*/0, /*Opcode*/GIMT_Encode2(AMDGPU::SCRATCH_STORE_DWORDX4_SADDR),
      GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/0, // data
      GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/0, // saddr
      GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/1, // offset
      GIR_AddImm8, /*InsnID*/0, /*Imm*/0,
      GIR_MergeMemOperands, /*InsnID*/0, /*NumInsns*/1, /*MergeInsnID's*/0,
      GIR_ConstrainSelectedInstOperands, /*InsnID*/0,
      GIR_EraseFromParent, /*InsnID*/0,
      // GIR_Coverage, 3561,
      GIR_Done,
    // Label 2212: @145313
    GIM_Try, /*On fail goto*//*Label 2213*/ GIMT_Encode4(145370), // Rule ID 3567 //
      GIM_CheckFeatures, GIMT_Encode2(GIFBS_EnableFlatScratch_HasFlatScratchInsts),
      GIM_CheckMemoryAddressSpace, /*MI*/0, /*MMO*/0, /*NumAddrSpace*/1, /*AddrSpace*/5,
      GIM_CheckAtomicOrdering, /*MI*/0, /*Order*/(uint8_t)AtomicOrdering::NotAtomic,
      GIM_CheckPointerToAny, /*MI*/0, /*Op*/1, /*SizeInBits*/0,
      GIM_CheckComplexPattern, /*MI*/0, /*Op*/1, /*Renderer*/GIMT_Encode2(0), GIMT_Encode2(GICP_gi_flat_scratch_saddr),
      // (st v2f64:{ *:[v2f64] }:$data, (ScratchSAddr:{ *:[iPTR] } SGPR_32:{ *:[i32] }:$saddr, i32:{ *:[i32] }:$offset))<<P:Predicate_unindexedstore>><<P:Predicate_store_private>>  =>  (SCRATCH_STORE_DWORDX4_SADDR anonymous_15034:{ *:[v2f64] }:$data, ?:{ *:[i32] }:$saddr, ?:{ *:[i32] }:$offset)
      GIR_BuildMI, /*InsnID*/0, /*Opcode*/GIMT_Encode2(AMDGPU::SCRATCH_STORE_DWORDX4_SADDR),
      GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/0, // data
      GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/0, // saddr
      GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/1, // offset
      GIR_AddImm8, /*InsnID*/0, /*Imm*/0,
      GIR_MergeMemOperands, /*InsnID*/0, /*NumInsns*/1, /*MergeInsnID's*/0,
      GIR_ConstrainSelectedInstOperands, /*InsnID*/0,
      GIR_EraseFromParent, /*InsnID*/0,
      // GIR_Coverage, 3567,
      GIR_Done,
    // Label 2213: @145370
    GIM_Try, /*On fail goto*//*Label 2214*/ GIMT_Encode4(145427), // Rule ID 3560 //
      GIM_CheckFeatures, GIMT_Encode2(GIFBS_EnableFlatScratch_HasFlatScratchInsts),
      GIM_CheckMemoryAddressSpace, /*MI*/0, /*MMO*/0, /*NumAddrSpace*/1, /*AddrSpace*/5,
      GIM_CheckAtomicOrdering, /*MI*/0, /*Order*/(uint8_t)AtomicOrdering::NotAtomic,
      GIM_CheckPointerToAny, /*MI*/0, /*Op*/1, /*SizeInBits*/0,
      GIM_CheckComplexPattern, /*MI*/0, /*Op*/1, /*Renderer*/GIMT_Encode2(0), GIMT_Encode2(GICP_gi_flat_scratch_offset),
      // (st v2i64:{ *:[v2i64] }:$data, (ScratchOffset:{ *:[iPTR] } VGPR_32:{ *:[i32] }:$vaddr, i32:{ *:[i32] }:$offset))<<P:Predicate_unindexedstore>><<P:Predicate_store_private>>  =>  (SCRATCH_STORE_DWORDX4 anonymous_15034:{ *:[v2i64] }:$data, ?:{ *:[i32] }:$vaddr, ?:{ *:[i32] }:$offset)
      GIR_BuildMI, /*InsnID*/0, /*Opcode*/GIMT_Encode2(AMDGPU::SCRATCH_STORE_DWORDX4),
      GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/0, // data
      GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/0, // vaddr
      GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/1, // offset
      GIR_AddImm8, /*InsnID*/0, /*Imm*/0,
      GIR_MergeMemOperands, /*InsnID*/0, /*NumInsns*/1, /*MergeInsnID's*/0,
      GIR_ConstrainSelectedInstOperands, /*InsnID*/0,
      GIR_EraseFromParent, /*InsnID*/0,
      // GIR_Coverage, 3560,
      GIR_Done,
    // Label 2214: @145427
    GIM_Try, /*On fail goto*//*Label 2215*/ GIMT_Encode4(145484), // Rule ID 3566 //
      GIM_CheckFeatures, GIMT_Encode2(GIFBS_EnableFlatScratch_HasFlatScratchInsts),
      GIM_CheckMemoryAddressSpace, /*MI*/0, /*MMO*/0, /*NumAddrSpace*/1, /*AddrSpace*/5,
      GIM_CheckAtomicOrdering, /*MI*/0, /*Order*/(uint8_t)AtomicOrdering::NotAtomic,
      GIM_CheckPointerToAny, /*MI*/0, /*Op*/1, /*SizeInBits*/0,
      GIM_CheckComplexPattern, /*MI*/0, /*Op*/1, /*Renderer*/GIMT_Encode2(0), GIMT_Encode2(GICP_gi_flat_scratch_offset),
      // (st v2f64:{ *:[v2f64] }:$data, (ScratchOffset:{ *:[iPTR] } VGPR_32:{ *:[i32] }:$vaddr, i32:{ *:[i32] }:$offset))<<P:Predicate_unindexedstore>><<P:Predicate_store_private>>  =>  (SCRATCH_STORE_DWORDX4 anonymous_15034:{ *:[v2f64] }:$data, ?:{ *:[i32] }:$vaddr, ?:{ *:[i32] }:$offset)
      GIR_BuildMI, /*InsnID*/0, /*Opcode*/GIMT_Encode2(AMDGPU::SCRATCH_STORE_DWORDX4),
      GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/0, // data
      GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/0, // vaddr
      GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/1, // offset
      GIR_AddImm8, /*InsnID*/0, /*Imm*/0,
      GIR_MergeMemOperands, /*InsnID*/0, /*NumInsns*/1, /*MergeInsnID's*/0,
      GIR_ConstrainSelectedInstOperands, /*InsnID*/0,
      GIR_EraseFromParent, /*InsnID*/0,
      // GIR_Coverage, 3566,
      GIR_Done,
    // Label 2215: @145484
    GIM_Try, /*On fail goto*//*Label 2216*/ GIMT_Encode4(145554), // Rule ID 3894 //
      GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasUnrestrictedSOffset),
      GIM_CheckMemoryAddressSpace, /*MI*/0, /*MMO*/0, /*NumAddrSpace*/1, /*AddrSpace*/1,
      GIM_CheckAtomicOrdering, /*MI*/0, /*Order*/(uint8_t)AtomicOrdering::NotAtomic,
      GIM_CheckPointerToAny, /*MI*/0, /*Op*/1, /*SizeInBits*/0,
      GIM_CheckComplexPattern, /*MI*/0, /*Op*/1, /*Renderer*/GIMT_Encode2(0), GIMT_Encode2(GICP_gi_mubuf_addr64),
      // (st v2i64:{ *:[v2i64] }:$vdata, (MUBUFAddr64:{ *:[iPTR] } v4i32:{ *:[v4i32] }:$srsrc, i64:{ *:[i64] }:$vaddr, i32:{ *:[i32] }:$soffset, i32:{ *:[i32] }:$offset))<<P:Predicate_unindexedstore>><<P:Predicate_store_global>>  =>  (BUFFER_STORE_DWORDX4_ADDR64 v2i64:{ *:[v2i64] }:$vdata, i64:{ *:[i64] }:$vaddr, v4i32:{ *:[v4i32] }:$srsrc, i32:{ *:[i32] }:$soffset, i32:{ *:[i32] }:$offset)
      GIR_BuildMI, /*InsnID*/0, /*Opcode*/GIMT_Encode2(AMDGPU::BUFFER_STORE_DWORDX4_ADDR64),
      GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/0, // vdata
      GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/1, // vaddr
      GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/0, // srsrc
      GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/2, // soffset
      GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/3, // offset
      GIR_AddImm8, /*InsnID*/0, /*Imm*/0,
      GIR_AddImm8, /*InsnID*/0, /*Imm*/0,
      GIR_MergeMemOperands, /*InsnID*/0, /*NumInsns*/1, /*MergeInsnID's*/0,
      GIR_ConstrainSelectedInstOperands, /*InsnID*/0,
      GIR_EraseFromParent, /*InsnID*/0,
      // GIR_Coverage, 3894,
      GIR_Done,
    // Label 2216: @145554
    GIM_Try, /*On fail goto*//*Label 2217*/ GIMT_Encode4(145621), // Rule ID 3896 //
      GIM_CheckMemoryAddressSpace, /*MI*/0, /*MMO*/0, /*NumAddrSpace*/1, /*AddrSpace*/1,
      GIM_CheckAtomicOrdering, /*MI*/0, /*Order*/(uint8_t)AtomicOrdering::NotAtomic,
      GIM_CheckPointerToAny, /*MI*/0, /*Op*/1, /*SizeInBits*/0,
      GIM_CheckComplexPattern, /*MI*/0, /*Op*/1, /*Renderer*/GIMT_Encode2(0), GIMT_Encode2(GICP_gi_mubuf_addr64),
      // (st v2i64:{ *:[v2i64] }:$vdata, (MUBUFAddr64:{ *:[iPTR] } v4i32:{ *:[v4i32] }:$srsrc, i64:{ *:[i64] }:$vaddr, i32:{ *:[i32] }:$soffset, i32:{ *:[i32] }:$offset))<<P:Predicate_unindexedstore>><<P:Predicate_store_global>>  =>  (BUFFER_STORE_DWORDX4_VBUFFER_ADDR64 v2i64:{ *:[v2i64] }:$vdata, i64:{ *:[i64] }:$vaddr, v4i32:{ *:[v4i32] }:$srsrc, i32:{ *:[i32] }:$soffset, i32:{ *:[i32] }:$offset)
      GIR_BuildMI, /*InsnID*/0, /*Opcode*/GIMT_Encode2(AMDGPU::BUFFER_STORE_DWORDX4_VBUFFER_ADDR64),
      GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/0, // vdata
      GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/1, // vaddr
      GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/0, // srsrc
      GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/2, // soffset
      GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/3, // offset
      GIR_AddImm8, /*InsnID*/0, /*Imm*/0,
      GIR_AddImm8, /*InsnID*/0, /*Imm*/0,
      GIR_MergeMemOperands, /*InsnID*/0, /*NumInsns*/1, /*MergeInsnID's*/0,
      GIR_ConstrainSelectedInstOperands, /*InsnID*/0,
      GIR_EraseFromParent, /*InsnID*/0,
      // GIR_Coverage, 3896,
      GIR_Done,
    // Label 2217: @145621
    GIM_Try, /*On fail goto*//*Label 2218*/ GIMT_Encode4(145691), // Rule ID 3898 //
      GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasUnrestrictedSOffset),
      GIM_CheckMemoryAddressSpace, /*MI*/0, /*MMO*/0, /*NumAddrSpace*/1, /*AddrSpace*/1,
      GIM_CheckAtomicOrdering, /*MI*/0, /*Order*/(uint8_t)AtomicOrdering::NotAtomic,
      GIM_CheckPointerToAny, /*MI*/0, /*Op*/1, /*SizeInBits*/0,
      GIM_CheckComplexPattern, /*MI*/0, /*Op*/1, /*Renderer*/GIMT_Encode2(0), GIMT_Encode2(GICP_gi_mubuf_addr64),
      // (st v2f64:{ *:[v2f64] }:$vdata, (MUBUFAddr64:{ *:[iPTR] } v4i32:{ *:[v4i32] }:$srsrc, i64:{ *:[i64] }:$vaddr, i32:{ *:[i32] }:$soffset, i32:{ *:[i32] }:$offset))<<P:Predicate_unindexedstore>><<P:Predicate_store_global>>  =>  (BUFFER_STORE_DWORDX4_ADDR64 v2f64:{ *:[v2f64] }:$vdata, i64:{ *:[i64] }:$vaddr, v4i32:{ *:[v4i32] }:$srsrc, i32:{ *:[i32] }:$soffset, i32:{ *:[i32] }:$offset)
      GIR_BuildMI, /*InsnID*/0, /*Opcode*/GIMT_Encode2(AMDGPU::BUFFER_STORE_DWORDX4_ADDR64),
      GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/0, // vdata
      GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/1, // vaddr
      GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/0, // srsrc
      GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/2, // soffset
      GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/3, // offset
      GIR_AddImm8, /*InsnID*/0, /*Imm*/0,
      GIR_AddImm8, /*InsnID*/0, /*Imm*/0,
      GIR_MergeMemOperands, /*InsnID*/0, /*NumInsns*/1, /*MergeInsnID's*/0,
      GIR_ConstrainSelectedInstOperands, /*InsnID*/0,
      GIR_EraseFromParent, /*InsnID*/0,
      // GIR_Coverage, 3898,
      GIR_Done,
    // Label 2218: @145691
    GIM_Try, /*On fail goto*//*Label 2219*/ GIMT_Encode4(145758), // Rule ID 3900 //
      GIM_CheckMemoryAddressSpace, /*MI*/0, /*MMO*/0, /*NumAddrSpace*/1, /*AddrSpace*/1,
      GIM_CheckAtomicOrdering, /*MI*/0, /*Order*/(uint8_t)AtomicOrdering::NotAtomic,
      GIM_CheckPointerToAny, /*MI*/0, /*Op*/1, /*SizeInBits*/0,
      GIM_CheckComplexPattern, /*MI*/0, /*Op*/1, /*Renderer*/GIMT_Encode2(0), GIMT_Encode2(GICP_gi_mubuf_addr64),
      // (st v2f64:{ *:[v2f64] }:$vdata, (MUBUFAddr64:{ *:[iPTR] } v4i32:{ *:[v4i32] }:$srsrc, i64:{ *:[i64] }:$vaddr, i32:{ *:[i32] }:$soffset, i32:{ *:[i32] }:$offset))<<P:Predicate_unindexedstore>><<P:Predicate_store_global>>  =>  (BUFFER_STORE_DWORDX4_VBUFFER_ADDR64 v2f64:{ *:[v2f64] }:$vdata, i64:{ *:[i64] }:$vaddr, v4i32:{ *:[v4i32] }:$srsrc, i32:{ *:[i32] }:$soffset, i32:{ *:[i32] }:$offset)
      GIR_BuildMI, /*InsnID*/0, /*Opcode*/GIMT_Encode2(AMDGPU::BUFFER_STORE_DWORDX4_VBUFFER_ADDR64),
      GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/0, // vdata
      GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/1, // vaddr
      GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/0, // srsrc
      GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/2, // soffset
      GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/3, // offset
      GIR_AddImm8, /*InsnID*/0, /*Imm*/0,
      GIR_AddImm8, /*InsnID*/0, /*Imm*/0,
      GIR_MergeMemOperands, /*InsnID*/0, /*NumInsns*/1, /*MergeInsnID's*/0,
      GIR_ConstrainSelectedInstOperands, /*InsnID*/0,
      GIR_EraseFromParent, /*InsnID*/0,
      // GIR_Coverage, 3900,
      GIR_Done,
    // Label 2219: @145758
    GIM_Try, /*On fail goto*//*Label 2220*/ GIMT_Encode4(145882), // Rule ID 6720 //
      GIM_CheckFeatures, GIMT_Encode2(GIFBS_LDSRequiresM0Init_isGFX7Plus),
      GIM_CheckMemorySizeEqualToLLT, /*MI*/0, /*MMO*/0, /*OpIdx*/0,
      GIM_CheckMemoryAddressSpace, /*MI*/0, /*MMO*/0, /*NumAddrSpace*/1, /*AddrSpace*/3,
      GIM_CheckAtomicOrdering, /*MI*/0, /*Order*/(uint8_t)AtomicOrdering::NotAtomic,
      GIM_CheckPointerToAny, /*MI*/0, /*Op*/1, /*SizeInBits*/0,
      GIM_CheckComplexPattern, /*MI*/0, /*Op*/1, /*Renderer*/GIMT_Encode2(0), GIMT_Encode2(GICP_gi_ds_128bit_8byte_aligned),
      // (AMDGPUst_glue v2i64:{ *:[v2i64] }:$value, (DS128Bit8ByteAligned:{ *:[iPTR] } i32:{ *:[i32] }:$ptr, i8:{ *:[i8] }:$offset0, i8:{ *:[i8] }:$offset1))<<P:Predicate_unindexedstore_glue>><<P:Predicate_store_glue>><<P:Predicate_store_local_m0>>  =>  (DS_WRITE2_B64 ?:{ *:[i32] }:$ptr, (EXTRACT_SUBREG:{ *:[i64] } VReg_128:{ *:[v2i64] }:$value, sub0_sub1:{ *:[i32] }), (EXTRACT_SUBREG:{ *:[i64] } VReg_128:{ *:[v2i64] }:$value, sub2_sub3:{ *:[i32] }), ?:{ *:[i8] }:$offset0, ?:{ *:[i8] }:$offset1, 0:{ *:[i1] })
      GIR_MakeTempReg, /*TempRegID*/0, /*TypeID*/GILLT_s64,
      GIR_MakeTempReg, /*TempRegID*/1, /*TypeID*/GILLT_s64,
      GIR_BuildMI, /*InsnID*/2, /*Opcode*/GIMT_Encode2(TargetOpcode::COPY),
      GIR_AddTempRegister, /*InsnID*/2, /*TempRegID*/1, /*TempRegFlags*/GIMT_Encode2(RegState::Define),
      GIR_CopySubReg, /*NewInsnID*/2, /*OldInsnID*/0, /*OpIdx*/0, /*SubRegIdx*/GIMT_Encode2(24), // value
      GIR_ConstrainOperandRC, /*InsnID*/2, /*Op*/0, GIMT_Encode2(AMDGPU::VReg_64RegClassID),
      GIR_ConstrainOperandRC, /*InsnID*/2, /*Op*/1, GIMT_Encode2(AMDGPU::VReg_128RegClassID),
      GIR_BuildMI, /*InsnID*/1, /*Opcode*/GIMT_Encode2(TargetOpcode::COPY),
      GIR_AddTempRegister, /*InsnID*/1, /*TempRegID*/0, /*TempRegFlags*/GIMT_Encode2(RegState::Define),
      GIR_CopySubReg, /*NewInsnID*/1, /*OldInsnID*/0, /*OpIdx*/0, /*SubRegIdx*/GIMT_Encode2(4), // value
      GIR_ConstrainOperandRC, /*InsnID*/1, /*Op*/0, GIMT_Encode2(AMDGPU::VReg_64RegClassID),
      GIR_ConstrainOperandRC, /*InsnID*/1, /*Op*/1, GIMT_Encode2(AMDGPU::VReg_128RegClassID),
      GIR_BuildMI, /*InsnID*/0, /*Opcode*/GIMT_Encode2(AMDGPU::DS_WRITE2_B64),
      GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/0, // ptr
      GIR_AddSimpleTempRegister, /*InsnID*/0, /*TempRegID*/0,
      GIR_AddSimpleTempRegister, /*InsnID*/0, /*TempRegID*/1,
      GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/1, // offset0
      GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/2, // offset1
      GIR_AddImm8, /*InsnID*/0, /*Imm*/0,
      GIR_MergeMemOperands, /*InsnID*/0, /*NumInsns*/1, /*MergeInsnID's*/0,
      GIR_ConstrainSelectedInstOperands, /*InsnID*/0,
      GIR_EraseFromParent, /*InsnID*/0,
      // GIR_Coverage, 6720,
      GIR_Done,
    // Label 2220: @145882
    GIM_Try, /*On fail goto*//*Label 2221*/ GIMT_Encode4(146006), // Rule ID 6724 //
      GIM_CheckFeatures, GIMT_Encode2(GIFBS_LDSRequiresM0Init_isGFX7Plus),
      GIM_CheckMemorySizeEqualToLLT, /*MI*/0, /*MMO*/0, /*OpIdx*/0,
      GIM_CheckMemoryAddressSpace, /*MI*/0, /*MMO*/0, /*NumAddrSpace*/1, /*AddrSpace*/3,
      GIM_CheckAtomicOrdering, /*MI*/0, /*Order*/(uint8_t)AtomicOrdering::NotAtomic,
      GIM_CheckPointerToAny, /*MI*/0, /*Op*/1, /*SizeInBits*/0,
      GIM_CheckComplexPattern, /*MI*/0, /*Op*/1, /*Renderer*/GIMT_Encode2(0), GIMT_Encode2(GICP_gi_ds_128bit_8byte_aligned),
      // (AMDGPUst_glue v2f64:{ *:[v2f64] }:$value, (DS128Bit8ByteAligned:{ *:[iPTR] } i32:{ *:[i32] }:$ptr, i8:{ *:[i8] }:$offset0, i8:{ *:[i8] }:$offset1))<<P:Predicate_unindexedstore_glue>><<P:Predicate_store_glue>><<P:Predicate_store_local_m0>>  =>  (DS_WRITE2_B64 ?:{ *:[i32] }:$ptr, (EXTRACT_SUBREG:{ *:[i64] } VReg_128:{ *:[v2f64] }:$value, sub0_sub1:{ *:[i32] }), (EXTRACT_SUBREG:{ *:[i64] } VReg_128:{ *:[v2f64] }:$value, sub2_sub3:{ *:[i32] }), ?:{ *:[i8] }:$offset0, ?:{ *:[i8] }:$offset1, 0:{ *:[i1] })
      GIR_MakeTempReg, /*TempRegID*/0, /*TypeID*/GILLT_s64,
      GIR_MakeTempReg, /*TempRegID*/1, /*TypeID*/GILLT_s64,
      GIR_BuildMI, /*InsnID*/2, /*Opcode*/GIMT_Encode2(TargetOpcode::COPY),
      GIR_AddTempRegister, /*InsnID*/2, /*TempRegID*/1, /*TempRegFlags*/GIMT_Encode2(RegState::Define),
      GIR_CopySubReg, /*NewInsnID*/2, /*OldInsnID*/0, /*OpIdx*/0, /*SubRegIdx*/GIMT_Encode2(24), // value
      GIR_ConstrainOperandRC, /*InsnID*/2, /*Op*/0, GIMT_Encode2(AMDGPU::VReg_64RegClassID),
      GIR_ConstrainOperandRC, /*InsnID*/2, /*Op*/1, GIMT_Encode2(AMDGPU::VReg_128RegClassID),
      GIR_BuildMI, /*InsnID*/1, /*Opcode*/GIMT_Encode2(TargetOpcode::COPY),
      GIR_AddTempRegister, /*InsnID*/1, /*TempRegID*/0, /*TempRegFlags*/GIMT_Encode2(RegState::Define),
      GIR_CopySubReg, /*NewInsnID*/1, /*OldInsnID*/0, /*OpIdx*/0, /*SubRegIdx*/GIMT_Encode2(4), // value
      GIR_ConstrainOperandRC, /*InsnID*/1, /*Op*/0, GIMT_Encode2(AMDGPU::VReg_64RegClassID),
      GIR_ConstrainOperandRC, /*InsnID*/1, /*Op*/1, GIMT_Encode2(AMDGPU::VReg_128RegClassID),
      GIR_BuildMI, /*InsnID*/0, /*Opcode*/GIMT_Encode2(AMDGPU::DS_WRITE2_B64),
      GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/0, // ptr
      GIR_AddSimpleTempRegister, /*InsnID*/0, /*TempRegID*/0,
      GIR_AddSimpleTempRegister, /*InsnID*/0, /*TempRegID*/1,
      GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/1, // offset0
      GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/2, // offset1
      GIR_AddImm8, /*InsnID*/0, /*Imm*/0,
      GIR_MergeMemOperands, /*InsnID*/0, /*NumInsns*/1, /*MergeInsnID's*/0,
      GIR_ConstrainSelectedInstOperands, /*InsnID*/0,
      GIR_EraseFromParent, /*InsnID*/0,
      // GIR_Coverage, 6724,
      GIR_Done,
    // Label 2221: @146006
    GIM_Try, /*On fail goto*//*Label 2222*/ GIMT_Encode4(146071), // Rule ID 3893 //
      GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasUnrestrictedSOffset),
      GIM_CheckMemoryAddressSpace, /*MI*/0, /*MMO*/0, /*NumAddrSpace*/1, /*AddrSpace*/1,
      GIM_CheckAtomicOrdering, /*MI*/0, /*Order*/(uint8_t)AtomicOrdering::NotAtomic,
      GIM_CheckPointerToAny, /*MI*/0, /*Op*/1, /*SizeInBits*/0,
      GIM_CheckComplexPattern, /*MI*/0, /*Op*/1, /*Renderer*/GIMT_Encode2(0), GIMT_Encode2(GICP_gi_mubuf_offset),
      // (st v2i64:{ *:[v2i64] }:$vdata, (MUBUFOffset:{ *:[iPTR] } v4i32:{ *:[v4i32] }:$srsrc, i32:{ *:[i32] }:$soffset, i32:{ *:[i32] }:$offset))<<P:Predicate_unindexedstore>><<P:Predicate_store_global>>  =>  (BUFFER_STORE_DWORDX4_OFFSET v2i64:{ *:[v2i64] }:$vdata, v4i32:{ *:[v4i32] }:$srsrc, i32:{ *:[i32] }:$soffset, i32:{ *:[i32] }:$offset)
      GIR_BuildMI, /*InsnID*/0, /*Opcode*/GIMT_Encode2(AMDGPU::BUFFER_STORE_DWORDX4_OFFSET),
      GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/0, // vdata
      GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/0, // srsrc
      GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/1, // soffset
      GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/2, // offset
      GIR_AddImm8, /*InsnID*/0, /*Imm*/0,
      GIR_AddImm8, /*InsnID*/0, /*Imm*/0,
      GIR_MergeMemOperands, /*InsnID*/0, /*NumInsns*/1, /*MergeInsnID's*/0,
      GIR_ConstrainSelectedInstOperands, /*InsnID*/0,
      GIR_EraseFromParent, /*InsnID*/0,
      // GIR_Coverage, 3893,
      GIR_Done,
    // Label 2222: @146071
    GIM_Try, /*On fail goto*//*Label 2223*/ GIMT_Encode4(146133), // Rule ID 3895 //
      GIM_CheckMemoryAddressSpace, /*MI*/0, /*MMO*/0, /*NumAddrSpace*/1, /*AddrSpace*/1,
      GIM_CheckAtomicOrdering, /*MI*/0, /*Order*/(uint8_t)AtomicOrdering::NotAtomic,
      GIM_CheckPointerToAny, /*MI*/0, /*Op*/1, /*SizeInBits*/0,
      GIM_CheckComplexPattern, /*MI*/0, /*Op*/1, /*Renderer*/GIMT_Encode2(0), GIMT_Encode2(GICP_gi_mubuf_offset),
      // (st v2i64:{ *:[v2i64] }:$vdata, (MUBUFOffset:{ *:[iPTR] } v4i32:{ *:[v4i32] }:$srsrc, i32:{ *:[i32] }:$soffset, i32:{ *:[i32] }:$offset))<<P:Predicate_unindexedstore>><<P:Predicate_store_global>>  =>  (BUFFER_STORE_DWORDX4_VBUFFER_OFFSET v2i64:{ *:[v2i64] }:$vdata, v4i32:{ *:[v4i32] }:$srsrc, i32:{ *:[i32] }:$soffset, i32:{ *:[i32] }:$offset)
      GIR_BuildMI, /*InsnID*/0, /*Opcode*/GIMT_Encode2(AMDGPU::BUFFER_STORE_DWORDX4_VBUFFER_OFFSET),
      GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/0, // vdata
      GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/0, // srsrc
      GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/1, // soffset
      GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/2, // offset
      GIR_AddImm8, /*InsnID*/0, /*Imm*/0,
      GIR_AddImm8, /*InsnID*/0, /*Imm*/0,
      GIR_MergeMemOperands, /*InsnID*/0, /*NumInsns*/1, /*MergeInsnID's*/0,
      GIR_ConstrainSelectedInstOperands, /*InsnID*/0,
      GIR_EraseFromParent, /*InsnID*/0,
      // GIR_Coverage, 3895,
      GIR_Done,
    // Label 2223: @146133
    GIM_Try, /*On fail goto*//*Label 2224*/ GIMT_Encode4(146198), // Rule ID 3897 //
      GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasUnrestrictedSOffset),
      GIM_CheckMemoryAddressSpace, /*MI*/0, /*MMO*/0, /*NumAddrSpace*/1, /*AddrSpace*/1,
      GIM_CheckAtomicOrdering, /*MI*/0, /*Order*/(uint8_t)AtomicOrdering::NotAtomic,
      GIM_CheckPointerToAny, /*MI*/0, /*Op*/1, /*SizeInBits*/0,
      GIM_CheckComplexPattern, /*MI*/0, /*Op*/1, /*Renderer*/GIMT_Encode2(0), GIMT_Encode2(GICP_gi_mubuf_offset),
      // (st v2f64:{ *:[v2f64] }:$vdata, (MUBUFOffset:{ *:[iPTR] } v4i32:{ *:[v4i32] }:$srsrc, i32:{ *:[i32] }:$soffset, i32:{ *:[i32] }:$offset))<<P:Predicate_unindexedstore>><<P:Predicate_store_global>>  =>  (BUFFER_STORE_DWORDX4_OFFSET v2f64:{ *:[v2f64] }:$vdata, v4i32:{ *:[v4i32] }:$srsrc, i32:{ *:[i32] }:$soffset, i32:{ *:[i32] }:$offset)
      GIR_BuildMI, /*InsnID*/0, /*Opcode*/GIMT_Encode2(AMDGPU::BUFFER_STORE_DWORDX4_OFFSET),
      GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/0, // vdata
      GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/0, // srsrc
      GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/1, // soffset
      GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/2, // offset
      GIR_AddImm8, /*InsnID*/0, /*Imm*/0,
      GIR_AddImm8, /*InsnID*/0, /*Imm*/0,
      GIR_MergeMemOperands, /*InsnID*/0, /*NumInsns*/1, /*MergeInsnID's*/0,
      GIR_ConstrainSelectedInstOperands, /*InsnID*/0,
      GIR_EraseFromParent, /*InsnID*/0,
      // GIR_Coverage, 3897,
      GIR_Done,
    // Label 2224: @146198
    GIM_Try, /*On fail goto*//*Label 2225*/ GIMT_Encode4(146260), // Rule ID 3899 //
      GIM_CheckMemoryAddressSpace, /*MI*/0, /*MMO*/0, /*NumAddrSpace*/1, /*AddrSpace*/1,
      GIM_CheckAtomicOrdering, /*MI*/0, /*Order*/(uint8_t)AtomicOrdering::NotAtomic,
      GIM_CheckPointerToAny, /*MI*/0, /*Op*/1, /*SizeInBits*/0,
      GIM_CheckComplexPattern, /*MI*/0, /*Op*/1, /*Renderer*/GIMT_Encode2(0), GIMT_Encode2(GICP_gi_mubuf_offset),
      // (st v2f64:{ *:[v2f64] }:$vdata, (MUBUFOffset:{ *:[iPTR] } v4i32:{ *:[v4i32] }:$srsrc, i32:{ *:[i32] }:$soffset, i32:{ *:[i32] }:$offset))<<P:Predicate_unindexedstore>><<P:Predicate_store_global>>  =>  (BUFFER_STORE_DWORDX4_VBUFFER_OFFSET v2f64:{ *:[v2f64] }:$vdata, v4i32:{ *:[v4i32] }:$srsrc, i32:{ *:[i32] }:$soffset, i32:{ *:[i32] }:$offset)
      GIR_BuildMI, /*InsnID*/0, /*Opcode*/GIMT_Encode2(AMDGPU::BUFFER_STORE_DWORDX4_VBUFFER_OFFSET),
      GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/0, // vdata
      GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/0, // srsrc
      GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/1, // soffset
      GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/2, // offset
      GIR_AddImm8, /*InsnID*/0, /*Imm*/0,
      GIR_AddImm8, /*InsnID*/0, /*Imm*/0,
      GIR_MergeMemOperands, /*InsnID*/0, /*NumInsns*/1, /*MergeInsnID's*/0,
      GIR_ConstrainSelectedInstOperands, /*InsnID*/0,
      GIR_EraseFromParent, /*InsnID*/0,
      // GIR_Coverage, 3899,
      GIR_Done,
    // Label 2225: @146260
    GIM_Try, /*On fail goto*//*Label 2226*/ GIMT_Encode4(146380), // Rule ID 6722 //
      GIM_CheckFeatures, GIMT_Encode2(GIFBS_NotLDSRequiresM0Init),
      GIM_CheckMemoryAddressSpace, /*MI*/0, /*MMO*/0, /*NumAddrSpace*/1, /*AddrSpace*/3,
      GIM_CheckAtomicOrdering, /*MI*/0, /*Order*/(uint8_t)AtomicOrdering::NotAtomic,
      GIM_CheckPointerToAny, /*MI*/0, /*Op*/1, /*SizeInBits*/0,
      GIM_CheckComplexPattern, /*MI*/0, /*Op*/1, /*Renderer*/GIMT_Encode2(0), GIMT_Encode2(GICP_gi_ds_128bit_8byte_aligned),
      // (st v2i64:{ *:[v2i64] }:$value, (DS128Bit8ByteAligned:{ *:[iPTR] } i32:{ *:[i32] }:$ptr, i8:{ *:[i8] }:$offset0, i8:{ *:[i8] }:$offset1))<<P:Predicate_unindexedstore>><<P:Predicate_store_local>>  =>  (DS_WRITE2_B64_gfx9 ?:{ *:[i32] }:$ptr, (EXTRACT_SUBREG:{ *:[i64] } VReg_128:{ *:[v2i64] }:$value, sub0_sub1:{ *:[i32] }), (EXTRACT_SUBREG:{ *:[i64] } VReg_128:{ *:[v2i64] }:$value, sub2_sub3:{ *:[i32] }), ?:{ *:[i8] }:$offset0, ?:{ *:[i8] }:$offset1, 0:{ *:[i1] })
      GIR_MakeTempReg, /*TempRegID*/0, /*TypeID*/GILLT_s64,
      GIR_MakeTempReg, /*TempRegID*/1, /*TypeID*/GILLT_s64,
      GIR_BuildMI, /*InsnID*/2, /*Opcode*/GIMT_Encode2(TargetOpcode::COPY),
      GIR_AddTempRegister, /*InsnID*/2, /*TempRegID*/1, /*TempRegFlags*/GIMT_Encode2(RegState::Define),
      GIR_CopySubReg, /*NewInsnID*/2, /*OldInsnID*/0, /*OpIdx*/0, /*SubRegIdx*/GIMT_Encode2(24), // value
      GIR_ConstrainOperandRC, /*InsnID*/2, /*Op*/0, GIMT_Encode2(AMDGPU::VReg_64RegClassID),
      GIR_ConstrainOperandRC, /*InsnID*/2, /*Op*/1, GIMT_Encode2(AMDGPU::VReg_128RegClassID),
      GIR_BuildMI, /*InsnID*/1, /*Opcode*/GIMT_Encode2(TargetOpcode::COPY),
      GIR_AddTempRegister, /*InsnID*/1, /*TempRegID*/0, /*TempRegFlags*/GIMT_Encode2(RegState::Define),
      GIR_CopySubReg, /*NewInsnID*/1, /*OldInsnID*/0, /*OpIdx*/0, /*SubRegIdx*/GIMT_Encode2(4), // value
      GIR_ConstrainOperandRC, /*InsnID*/1, /*Op*/0, GIMT_Encode2(AMDGPU::VReg_64RegClassID),
      GIR_ConstrainOperandRC, /*InsnID*/1, /*Op*/1, GIMT_Encode2(AMDGPU::VReg_128RegClassID),
      GIR_BuildMI, /*InsnID*/0, /*Opcode*/GIMT_Encode2(AMDGPU::DS_WRITE2_B64_gfx9),
      GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/0, // ptr
      GIR_AddSimpleTempRegister, /*InsnID*/0, /*TempRegID*/0,
      GIR_AddSimpleTempRegister, /*InsnID*/0, /*TempRegID*/1,
      GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/1, // offset0
      GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/2, // offset1
      GIR_AddImm8, /*InsnID*/0, /*Imm*/0,
      GIR_MergeMemOperands, /*InsnID*/0, /*NumInsns*/1, /*MergeInsnID's*/0,
      GIR_ConstrainSelectedInstOperands, /*InsnID*/0,
      GIR_EraseFromParent, /*InsnID*/0,
      // GIR_Coverage, 6722,
      GIR_Done,
    // Label 2226: @146380
    GIM_Try, /*On fail goto*//*Label 2227*/ GIMT_Encode4(146500), // Rule ID 6726 //
      GIM_CheckFeatures, GIMT_Encode2(GIFBS_NotLDSRequiresM0Init),
      GIM_CheckMemoryAddressSpace, /*MI*/0, /*MMO*/0, /*NumAddrSpace*/1, /*AddrSpace*/3,
      GIM_CheckAtomicOrdering, /*MI*/0, /*Order*/(uint8_t)AtomicOrdering::NotAtomic,
      GIM_CheckPointerToAny, /*MI*/0, /*Op*/1, /*SizeInBits*/0,
      GIM_CheckComplexPattern, /*MI*/0, /*Op*/1, /*Renderer*/GIMT_Encode2(0), GIMT_Encode2(GICP_gi_ds_128bit_8byte_aligned),
      // (st v2f64:{ *:[v2f64] }:$value, (DS128Bit8ByteAligned:{ *:[iPTR] } i32:{ *:[i32] }:$ptr, i8:{ *:[i8] }:$offset0, i8:{ *:[i8] }:$offset1))<<P:Predicate_unindexedstore>><<P:Predicate_store_local>>  =>  (DS_WRITE2_B64_gfx9 ?:{ *:[i32] }:$ptr, (EXTRACT_SUBREG:{ *:[i64] } VReg_128:{ *:[v2f64] }:$value, sub0_sub1:{ *:[i32] }), (EXTRACT_SUBREG:{ *:[i64] } VReg_128:{ *:[v2f64] }:$value, sub2_sub3:{ *:[i32] }), ?:{ *:[i8] }:$offset0, ?:{ *:[i8] }:$offset1, 0:{ *:[i1] })
      GIR_MakeTempReg, /*TempRegID*/0, /*TypeID*/GILLT_s64,
      GIR_MakeTempReg, /*TempRegID*/1, /*TypeID*/GILLT_s64,
      GIR_BuildMI, /*InsnID*/2, /*Opcode*/GIMT_Encode2(TargetOpcode::COPY),
      GIR_AddTempRegister, /*InsnID*/2, /*TempRegID*/1, /*TempRegFlags*/GIMT_Encode2(RegState::Define),
      GIR_CopySubReg, /*NewInsnID*/2, /*OldInsnID*/0, /*OpIdx*/0, /*SubRegIdx*/GIMT_Encode2(24), // value
      GIR_ConstrainOperandRC, /*InsnID*/2, /*Op*/0, GIMT_Encode2(AMDGPU::VReg_64RegClassID),
      GIR_ConstrainOperandRC, /*InsnID*/2, /*Op*/1, GIMT_Encode2(AMDGPU::VReg_128RegClassID),
      GIR_BuildMI, /*InsnID*/1, /*Opcode*/GIMT_Encode2(TargetOpcode::COPY),
      GIR_AddTempRegister, /*InsnID*/1, /*TempRegID*/0, /*TempRegFlags*/GIMT_Encode2(RegState::Define),
      GIR_CopySubReg, /*NewInsnID*/1, /*OldInsnID*/0, /*OpIdx*/0, /*SubRegIdx*/GIMT_Encode2(4), // value
      GIR_ConstrainOperandRC, /*InsnID*/1, /*Op*/0, GIMT_Encode2(AMDGPU::VReg_64RegClassID),
      GIR_ConstrainOperandRC, /*InsnID*/1, /*Op*/1, GIMT_Encode2(AMDGPU::VReg_128RegClassID),
      GIR_BuildMI, /*InsnID*/0, /*Opcode*/GIMT_Encode2(AMDGPU::DS_WRITE2_B64_gfx9),
      GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/0, // ptr
      GIR_AddSimpleTempRegister, /*InsnID*/0, /*TempRegID*/0,
      GIR_AddSimpleTempRegister, /*InsnID*/0, /*TempRegID*/1,
      GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/1, // offset0
      GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/2, // offset1
      GIR_AddImm8, /*InsnID*/0, /*Imm*/0,
      GIR_MergeMemOperands, /*InsnID*/0, /*NumInsns*/1, /*MergeInsnID's*/0,
      GIR_ConstrainSelectedInstOperands, /*InsnID*/0,
      GIR_EraseFromParent, /*InsnID*/0,
      // GIR_Coverage, 6726,
      GIR_Done,
    // Label 2227: @146500
    GIM_Try, /*On fail goto*//*Label 2228*/ GIMT_Encode4(146562), // Rule ID 3081 //
      GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasFlatGlobalInsts),
      GIM_CheckMemoryAddressSpace, /*MI*/0, /*MMO*/0, /*NumAddrSpace*/1, /*AddrSpace*/1,
      GIM_CheckAtomicOrdering, /*MI*/0, /*Order*/(uint8_t)AtomicOrdering::NotAtomic,
      GIM_CheckPointerToAny, /*MI*/0, /*Op*/1, /*SizeInBits*/0,
      GIM_CheckComplexPattern, /*MI*/0, /*Op*/1, /*Renderer*/GIMT_Encode2(0), GIMT_Encode2(GICP_gi_global_saddr),
      // (st v2i64:{ *:[v2i64] }:$data, (GlobalSAddr:{ *:[iPTR] } SReg_64:{ *:[i64] }:$saddr, VGPR_32:{ *:[i32] }:$voffset, i32:{ *:[i32] }:$offset))<<P:Predicate_unindexedstore>><<P:Predicate_store_global>>  =>  (GLOBAL_STORE_DWORDX4_SADDR ?:{ *:[i32] }:$voffset, anonymous_15034:{ *:[v2i64] }:$data, ?:{ *:[i64] }:$saddr, ?:{ *:[i32] }:$offset)
      GIR_BuildMI, /*InsnID*/0, /*Opcode*/GIMT_Encode2(AMDGPU::GLOBAL_STORE_DWORDX4_SADDR),
      GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/1, // voffset
      GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/0, // data
      GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/0, // saddr
      GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/2, // offset
      GIR_AddImm8, /*InsnID*/0, /*Imm*/0,
      GIR_MergeMemOperands, /*InsnID*/0, /*NumInsns*/1, /*MergeInsnID's*/0,
      GIR_ConstrainSelectedInstOperands, /*InsnID*/0,
      GIR_EraseFromParent, /*InsnID*/0,
      // GIR_Coverage, 3081,
      GIR_Done,
    // Label 2228: @146562
    GIM_Try, /*On fail goto*//*Label 2229*/ GIMT_Encode4(146624), // Rule ID 3085 //
      GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasFlatGlobalInsts),
      GIM_CheckMemoryAddressSpace, /*MI*/0, /*MMO*/0, /*NumAddrSpace*/1, /*AddrSpace*/1,
      GIM_CheckAtomicOrdering, /*MI*/0, /*Order*/(uint8_t)AtomicOrdering::NotAtomic,
      GIM_CheckPointerToAny, /*MI*/0, /*Op*/1, /*SizeInBits*/0,
      GIM_CheckComplexPattern, /*MI*/0, /*Op*/1, /*Renderer*/GIMT_Encode2(0), GIMT_Encode2(GICP_gi_global_saddr),
      // (st v2f64:{ *:[v2f64] }:$data, (GlobalSAddr:{ *:[iPTR] } SReg_64:{ *:[i64] }:$saddr, VGPR_32:{ *:[i32] }:$voffset, i32:{ *:[i32] }:$offset))<<P:Predicate_unindexedstore>><<P:Predicate_store_global>>  =>  (GLOBAL_STORE_DWORDX4_SADDR ?:{ *:[i32] }:$voffset, anonymous_15034:{ *:[v2f64] }:$data, ?:{ *:[i64] }:$saddr, ?:{ *:[i32] }:$offset)
      GIR_BuildMI, /*InsnID*/0, /*Opcode*/GIMT_Encode2(AMDGPU::GLOBAL_STORE_DWORDX4_SADDR),
      GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/1, // voffset
      GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/0, // data
      GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/0, // saddr
      GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/2, // offset
      GIR_AddImm8, /*InsnID*/0, /*Imm*/0,
      GIR_MergeMemOperands, /*InsnID*/0, /*NumInsns*/1, /*MergeInsnID's*/0,
      GIR_ConstrainSelectedInstOperands, /*InsnID*/0,
      GIR_EraseFromParent, /*InsnID*/0,
      // GIR_Coverage, 3085,
      GIR_Done,
    // Label 2229: @146624
    GIM_Try, /*On fail goto*//*Label 2230*/ GIMT_Encode4(146681), // Rule ID 3080 //
      GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasFlatGlobalInsts),
      GIM_CheckMemoryAddressSpace, /*MI*/0, /*MMO*/0, /*NumAddrSpace*/1, /*AddrSpace*/1,
      GIM_CheckAtomicOrdering, /*MI*/0, /*Order*/(uint8_t)AtomicOrdering::NotAtomic,
      GIM_CheckPointerToAny, /*MI*/0, /*Op*/1, /*SizeInBits*/0,
      GIM_CheckComplexPattern, /*MI*/0, /*Op*/1, /*Renderer*/GIMT_Encode2(0), GIMT_Encode2(GICP_gi_global_offset),
      // (st v2i64:{ *:[v2i64] }:$data, (GlobalOffset:{ *:[iPTR] } i64:{ *:[i64] }:$vaddr, i32:{ *:[i32] }:$offset))<<P:Predicate_unindexedstore>><<P:Predicate_store_global>>  =>  (GLOBAL_STORE_DWORDX4 ?:{ *:[i64] }:$vaddr, anonymous_15034:{ *:[v2i64] }:$data, ?:{ *:[i32] }:$offset)
      GIR_BuildMI, /*InsnID*/0, /*Opcode*/GIMT_Encode2(AMDGPU::GLOBAL_STORE_DWORDX4),
      GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/0, // vaddr
      GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/0, // data
      GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/1, // offset
      GIR_AddImm8, /*InsnID*/0, /*Imm*/0,
      GIR_MergeMemOperands, /*InsnID*/0, /*NumInsns*/1, /*MergeInsnID's*/0,
      GIR_ConstrainSelectedInstOperands, /*InsnID*/0,
      GIR_EraseFromParent, /*InsnID*/0,
      // GIR_Coverage, 3080,
      GIR_Done,
    // Label 2230: @146681
    GIM_Try, /*On fail goto*//*Label 2231*/ GIMT_Encode4(146738), // Rule ID 3084 //
      GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasFlatGlobalInsts),
      GIM_CheckMemoryAddressSpace, /*MI*/0, /*MMO*/0, /*NumAddrSpace*/1, /*AddrSpace*/1,
      GIM_CheckAtomicOrdering, /*MI*/0, /*Order*/(uint8_t)AtomicOrdering::NotAtomic,
      GIM_CheckPointerToAny, /*MI*/0, /*Op*/1, /*SizeInBits*/0,
      GIM_CheckComplexPattern, /*MI*/0, /*Op*/1, /*Renderer*/GIMT_Encode2(0), GIMT_Encode2(GICP_gi_global_offset),
      // (st v2f64:{ *:[v2f64] }:$data, (GlobalOffset:{ *:[iPTR] } i64:{ *:[i64] }:$vaddr, i32:{ *:[i32] }:$offset))<<P:Predicate_unindexedstore>><<P:Predicate_store_global>>  =>  (GLOBAL_STORE_DWORDX4 ?:{ *:[i64] }:$vaddr, anonymous_15034:{ *:[v2f64] }:$data, ?:{ *:[i32] }:$offset)
      GIR_BuildMI, /*InsnID*/0, /*Opcode*/GIMT_Encode2(AMDGPU::GLOBAL_STORE_DWORDX4),
      GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/0, // vaddr
      GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/0, // data
      GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/1, // offset
      GIR_AddImm8, /*InsnID*/0, /*Imm*/0,
      GIR_MergeMemOperands, /*InsnID*/0, /*NumInsns*/1, /*MergeInsnID's*/0,
      GIR_ConstrainSelectedInstOperands, /*InsnID*/0,
      GIR_EraseFromParent, /*InsnID*/0,
      // GIR_Coverage, 3084,
      GIR_Done,
    // Label 2231: @146738
    GIM_Try, /*On fail goto*//*Label 2232*/ GIMT_Encode4(146796), // Rule ID 2814 //
      GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasFlatAddressSpace),
      GIM_CheckMemoryAddressSpace, /*MI*/0, /*MMO*/0, /*NumAddrSpace*/2, /*AddrSpace*/0, /*AddrSpace*/1,
      GIM_CheckAtomicOrdering, /*MI*/0, /*Order*/(uint8_t)AtomicOrdering::NotAtomic,
      GIM_CheckPointerToAny, /*MI*/0, /*Op*/1, /*SizeInBits*/0,
      GIM_CheckComplexPattern, /*MI*/0, /*Op*/1, /*Renderer*/GIMT_Encode2(0), GIMT_Encode2(GICP_gi_flat_offset),
      // (st v2i64:{ *:[v2i64] }:$data, (FlatOffset:{ *:[iPTR] } i64:{ *:[i64] }:$vaddr, i32:{ *:[i32] }:$offset))<<P:Predicate_unindexedstore>><<P:Predicate_store_flat>>  =>  (FLAT_STORE_DWORDX4 ?:{ *:[i64] }:$vaddr, anonymous_15034:{ *:[v2i64] }:$data, ?:{ *:[i32] }:$offset)
      GIR_BuildMI, /*InsnID*/0, /*Opcode*/GIMT_Encode2(AMDGPU::FLAT_STORE_DWORDX4),
      GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/0, // vaddr
      GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/0, // data
      GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/1, // offset
      GIR_AddImm8, /*InsnID*/0, /*Imm*/0,
      GIR_MergeMemOperands, /*InsnID*/0, /*NumInsns*/1, /*MergeInsnID's*/0,
      GIR_ConstrainSelectedInstOperands, /*InsnID*/0,
      GIR_EraseFromParent, /*InsnID*/0,
      // GIR_Coverage, 2814,
      GIR_Done,
    // Label 2232: @146796
    GIM_Try, /*On fail goto*//*Label 2233*/ GIMT_Encode4(146854), // Rule ID 2816 //
      GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasFlatAddressSpace),
      GIM_CheckMemoryAddressSpace, /*MI*/0, /*MMO*/0, /*NumAddrSpace*/2, /*AddrSpace*/0, /*AddrSpace*/1,
      GIM_CheckAtomicOrdering, /*MI*/0, /*Order*/(uint8_t)AtomicOrdering::NotAtomic,
      GIM_CheckPointerToAny, /*MI*/0, /*Op*/1, /*SizeInBits*/0,
      GIM_CheckComplexPattern, /*MI*/0, /*Op*/1, /*Renderer*/GIMT_Encode2(0), GIMT_Encode2(GICP_gi_flat_offset),
      // (st v2f64:{ *:[v2f64] }:$data, (FlatOffset:{ *:[iPTR] } i64:{ *:[i64] }:$vaddr, i32:{ *:[i32] }:$offset))<<P:Predicate_unindexedstore>><<P:Predicate_store_flat>>  =>  (FLAT_STORE_DWORDX4 ?:{ *:[i64] }:$vaddr, anonymous_15034:{ *:[v2f64] }:$data, ?:{ *:[i32] }:$offset)
      GIR_BuildMI, /*InsnID*/0, /*Opcode*/GIMT_Encode2(AMDGPU::FLAT_STORE_DWORDX4),
      GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/0, // vaddr
      GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/0, // data
      GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/1, // offset
      GIR_AddImm8, /*InsnID*/0, /*Imm*/0,
      GIR_MergeMemOperands, /*InsnID*/0, /*NumInsns*/1, /*MergeInsnID's*/0,
      GIR_ConstrainSelectedInstOperands, /*InsnID*/0,
      GIR_EraseFromParent, /*InsnID*/0,
      // GIR_Coverage, 2816,
      GIR_Done,
    // Label 2233: @146854
    GIM_Reject,
    // Label 1819: @146855
    GIM_Try, /*On fail goto*//*Label 2234*/ GIMT_Encode4(146916), // Rule ID 6857 //
      GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasUnalignedAccessMode_LDSRequiresM0Init),
      GIM_CheckMemorySizeEqualToLLT, /*MI*/0, /*MMO*/0, /*OpIdx*/0,
      GIM_CheckMemoryAddressSpace, /*MI*/0, /*MMO*/0, /*NumAddrSpace*/1, /*AddrSpace*/3,
      GIM_CheckAtomicOrdering, /*MI*/0, /*Order*/(uint8_t)AtomicOrdering::NotAtomic,
      GIM_CheckPointerToAny, /*MI*/0, /*Op*/1, /*SizeInBits*/0,
      GIM_CheckComplexPattern, /*MI*/0, /*Op*/1, /*Renderer*/GIMT_Encode2(0), GIMT_Encode2(GICP_gi_ds_1addr_1offset),
      // (AMDGPUst_glue v3i32:{ *:[v3i32] }:$value, (DS1Addr1Offset:{ *:[iPTR] } i32:{ *:[i32] }:$ptr, i32:{ *:[i32] }:$offset))<<P:Predicate_unindexedstore_glue>><<P:Predicate_store_glue>><<P:Predicate_store_local_m0>>  =>  (DS_WRITE_B96 ?:{ *:[i32] }:$ptr, anonymous_15035:{ *:[v3i32] }:$value, offset:{ *:[i32] }:$offset, 0:{ *:[i1] })
      GIR_BuildMI, /*InsnID*/0, /*Opcode*/GIMT_Encode2(AMDGPU::DS_WRITE_B96),
      GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/0, // ptr
      GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/0, // value
      GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/1, // offset
      GIR_AddImm8, /*InsnID*/0, /*Imm*/0,
      GIR_MergeMemOperands, /*InsnID*/0, /*NumInsns*/1, /*MergeInsnID's*/0,
      GIR_ConstrainSelectedInstOperands, /*InsnID*/0,
      GIR_EraseFromParent, /*InsnID*/0,
      // GIR_Coverage, 6857,
      GIR_Done,
    // Label 2234: @146916
    GIM_Try, /*On fail goto*//*Label 2235*/ GIMT_Encode4(146977), // Rule ID 6861 //
      GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasUnalignedAccessMode_LDSRequiresM0Init),
      GIM_CheckMemorySizeEqualToLLT, /*MI*/0, /*MMO*/0, /*OpIdx*/0,
      GIM_CheckMemoryAddressSpace, /*MI*/0, /*MMO*/0, /*NumAddrSpace*/1, /*AddrSpace*/3,
      GIM_CheckAtomicOrdering, /*MI*/0, /*Order*/(uint8_t)AtomicOrdering::NotAtomic,
      GIM_CheckPointerToAny, /*MI*/0, /*Op*/1, /*SizeInBits*/0,
      GIM_CheckComplexPattern, /*MI*/0, /*Op*/1, /*Renderer*/GIMT_Encode2(0), GIMT_Encode2(GICP_gi_ds_1addr_1offset),
      // (AMDGPUst_glue v3f32:{ *:[v3f32] }:$value, (DS1Addr1Offset:{ *:[iPTR] } i32:{ *:[i32] }:$ptr, i32:{ *:[i32] }:$offset))<<P:Predicate_unindexedstore_glue>><<P:Predicate_store_glue>><<P:Predicate_store_local_m0>>  =>  (DS_WRITE_B96 ?:{ *:[i32] }:$ptr, anonymous_15035:{ *:[v3f32] }:$value, offset:{ *:[i32] }:$offset, 0:{ *:[i1] })
      GIR_BuildMI, /*InsnID*/0, /*Opcode*/GIMT_Encode2(AMDGPU::DS_WRITE_B96),
      GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/0, // ptr
      GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/0, // value
      GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/1, // offset
      GIR_AddImm8, /*InsnID*/0, /*Imm*/0,
      GIR_MergeMemOperands, /*InsnID*/0, /*NumInsns*/1, /*MergeInsnID's*/0,
      GIR_ConstrainSelectedInstOperands, /*InsnID*/0,
      GIR_EraseFromParent, /*InsnID*/0,
      // GIR_Coverage, 6861,
      GIR_Done,
    // Label 2235: @146977
    GIM_Try, /*On fail goto*//*Label 2236*/ GIMT_Encode4(147042), // Rule ID 6781 //
      GIM_CheckFeatures, GIMT_Encode2(GIFBS_LDSRequiresM0Init_isGFX7Plus),
      GIM_CheckMemorySizeEqualToLLT, /*MI*/0, /*MMO*/0, /*OpIdx*/0,
      GIM_CheckMemoryAddressSpace, /*MI*/0, /*MMO*/0, /*NumAddrSpace*/1, /*AddrSpace*/3,
      GIM_CheckMemoryAlignment, /*MI*/0, /*MMO*/0, /*MinAlign*/16,
      GIM_CheckAtomicOrdering, /*MI*/0, /*Order*/(uint8_t)AtomicOrdering::NotAtomic,
      GIM_CheckPointerToAny, /*MI*/0, /*Op*/1, /*SizeInBits*/0,
      GIM_CheckComplexPattern, /*MI*/0, /*Op*/1, /*Renderer*/GIMT_Encode2(0), GIMT_Encode2(GICP_gi_ds_1addr_1offset),
      // (AMDGPUst_glue v3i32:{ *:[v3i32] }:$value, (DS1Addr1Offset:{ *:[iPTR] } i32:{ *:[i32] }:$ptr, i32:{ *:[i32] }:$offset))<<P:Predicate_unindexedstore_glue>><<P:Predicate_store_glue>><<P:Predicate_store_local_m0>><<P:Predicate_store_align16_local_m0>>  =>  (DS_WRITE_B96 ?:{ *:[i32] }:$ptr, anonymous_15035:{ *:[v3i32] }:$value, offset:{ *:[i32] }:$offset, 0:{ *:[i1] })
      GIR_BuildMI, /*InsnID*/0, /*Opcode*/GIMT_Encode2(AMDGPU::DS_WRITE_B96),
      GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/0, // ptr
      GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/0, // value
      GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/1, // offset
      GIR_AddImm8, /*InsnID*/0, /*Imm*/0,
      GIR_MergeMemOperands, /*InsnID*/0, /*NumInsns*/1, /*MergeInsnID's*/0,
      GIR_ConstrainSelectedInstOperands, /*InsnID*/0,
      GIR_EraseFromParent, /*InsnID*/0,
      // GIR_Coverage, 6781,
      GIR_Done,
    // Label 2236: @147042
    GIM_Try, /*On fail goto*//*Label 2237*/ GIMT_Encode4(147107), // Rule ID 6785 //
      GIM_CheckFeatures, GIMT_Encode2(GIFBS_LDSRequiresM0Init_isGFX7Plus),
      GIM_CheckMemorySizeEqualToLLT, /*MI*/0, /*MMO*/0, /*OpIdx*/0,
      GIM_CheckMemoryAddressSpace, /*MI*/0, /*MMO*/0, /*NumAddrSpace*/1, /*AddrSpace*/3,
      GIM_CheckMemoryAlignment, /*MI*/0, /*MMO*/0, /*MinAlign*/16,
      GIM_CheckAtomicOrdering, /*MI*/0, /*Order*/(uint8_t)AtomicOrdering::NotAtomic,
      GIM_CheckPointerToAny, /*MI*/0, /*Op*/1, /*SizeInBits*/0,
      GIM_CheckComplexPattern, /*MI*/0, /*Op*/1, /*Renderer*/GIMT_Encode2(0), GIMT_Encode2(GICP_gi_ds_1addr_1offset),
      // (AMDGPUst_glue v3f32:{ *:[v3f32] }:$value, (DS1Addr1Offset:{ *:[iPTR] } i32:{ *:[i32] }:$ptr, i32:{ *:[i32] }:$offset))<<P:Predicate_unindexedstore_glue>><<P:Predicate_store_glue>><<P:Predicate_store_local_m0>><<P:Predicate_store_align16_local_m0>>  =>  (DS_WRITE_B96 ?:{ *:[i32] }:$ptr, anonymous_15035:{ *:[v3f32] }:$value, offset:{ *:[i32] }:$offset, 0:{ *:[i1] })
      GIR_BuildMI, /*InsnID*/0, /*Opcode*/GIMT_Encode2(AMDGPU::DS_WRITE_B96),
      GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/0, // ptr
      GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/0, // value
      GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/1, // offset
      GIR_AddImm8, /*InsnID*/0, /*Imm*/0,
      GIR_MergeMemOperands, /*InsnID*/0, /*NumInsns*/1, /*MergeInsnID's*/0,
      GIR_ConstrainSelectedInstOperands, /*InsnID*/0,
      GIR_EraseFromParent, /*InsnID*/0,
      // GIR_Coverage, 6785,
      GIR_Done,
    // Label 2237: @147107
    GIM_Try, /*On fail goto*//*Label 2238*/ GIMT_Encode4(147164), // Rule ID 6858 //
      GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasUnalignedAccessMode_NotLDSRequiresM0Init),
      GIM_CheckMemoryAddressSpace, /*MI*/0, /*MMO*/0, /*NumAddrSpace*/1, /*AddrSpace*/3,
      GIM_CheckAtomicOrdering, /*MI*/0, /*Order*/(uint8_t)AtomicOrdering::NotAtomic,
      GIM_CheckPointerToAny, /*MI*/0, /*Op*/1, /*SizeInBits*/0,
      GIM_CheckComplexPattern, /*MI*/0, /*Op*/1, /*Renderer*/GIMT_Encode2(0), GIMT_Encode2(GICP_gi_ds_1addr_1offset),
      // (st v3i32:{ *:[v3i32] }:$value, (DS1Addr1Offset:{ *:[iPTR] } i32:{ *:[i32] }:$ptr, i32:{ *:[i32] }:$offset))<<P:Predicate_unindexedstore>><<P:Predicate_store_local>>  =>  (DS_WRITE_B96_gfx9 ?:{ *:[i32] }:$ptr, anonymous_15035:{ *:[v3i32] }:$value, offset:{ *:[i32] }:$offset, 0:{ *:[i1] })
      GIR_BuildMI, /*InsnID*/0, /*Opcode*/GIMT_Encode2(AMDGPU::DS_WRITE_B96_gfx9),
      GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/0, // ptr
      GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/0, // value
      GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/1, // offset
      GIR_AddImm8, /*InsnID*/0, /*Imm*/0,
      GIR_MergeMemOperands, /*InsnID*/0, /*NumInsns*/1, /*MergeInsnID's*/0,
      GIR_ConstrainSelectedInstOperands, /*InsnID*/0,
      GIR_EraseFromParent, /*InsnID*/0,
      // GIR_Coverage, 6858,
      GIR_Done,
    // Label 2238: @147164
    GIM_Try, /*On fail goto*//*Label 2239*/ GIMT_Encode4(147221), // Rule ID 6862 //
      GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasUnalignedAccessMode_NotLDSRequiresM0Init),
      GIM_CheckMemoryAddressSpace, /*MI*/0, /*MMO*/0, /*NumAddrSpace*/1, /*AddrSpace*/3,
      GIM_CheckAtomicOrdering, /*MI*/0, /*Order*/(uint8_t)AtomicOrdering::NotAtomic,
      GIM_CheckPointerToAny, /*MI*/0, /*Op*/1, /*SizeInBits*/0,
      GIM_CheckComplexPattern, /*MI*/0, /*Op*/1, /*Renderer*/GIMT_Encode2(0), GIMT_Encode2(GICP_gi_ds_1addr_1offset),
      // (st v3f32:{ *:[v3f32] }:$value, (DS1Addr1Offset:{ *:[iPTR] } i32:{ *:[i32] }:$ptr, i32:{ *:[i32] }:$offset))<<P:Predicate_unindexedstore>><<P:Predicate_store_local>>  =>  (DS_WRITE_B96_gfx9 ?:{ *:[i32] }:$ptr, anonymous_15035:{ *:[v3f32] }:$value, offset:{ *:[i32] }:$offset, 0:{ *:[i1] })
      GIR_BuildMI, /*InsnID*/0, /*Opcode*/GIMT_Encode2(AMDGPU::DS_WRITE_B96_gfx9),
      GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/0, // ptr
      GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/0, // value
      GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/1, // offset
      GIR_AddImm8, /*InsnID*/0, /*Imm*/0,
      GIR_MergeMemOperands, /*InsnID*/0, /*NumInsns*/1, /*MergeInsnID's*/0,
      GIR_ConstrainSelectedInstOperands, /*InsnID*/0,
      GIR_EraseFromParent, /*InsnID*/0,
      // GIR_Coverage, 6862,
      GIR_Done,
    // Label 2239: @147221
    GIM_Try, /*On fail goto*//*Label 2240*/ GIMT_Encode4(147282), // Rule ID 6782 //
      GIM_CheckFeatures, GIMT_Encode2(GIFBS_NotLDSRequiresM0Init_isGFX7Plus),
      GIM_CheckMemoryAddressSpace, /*MI*/0, /*MMO*/0, /*NumAddrSpace*/1, /*AddrSpace*/3,
      GIM_CheckMemoryAlignment, /*MI*/0, /*MMO*/0, /*MinAlign*/16,
      GIM_CheckAtomicOrdering, /*MI*/0, /*Order*/(uint8_t)AtomicOrdering::NotAtomic,
      GIM_CheckPointerToAny, /*MI*/0, /*Op*/1, /*SizeInBits*/0,
      GIM_CheckComplexPattern, /*MI*/0, /*Op*/1, /*Renderer*/GIMT_Encode2(0), GIMT_Encode2(GICP_gi_ds_1addr_1offset),
      // (st v3i32:{ *:[v3i32] }:$value, (DS1Addr1Offset:{ *:[iPTR] } i32:{ *:[i32] }:$ptr, i32:{ *:[i32] }:$offset))<<P:Predicate_unindexedstore>><<P:Predicate_store_local>><<P:Predicate_store_align16_local>>  =>  (DS_WRITE_B96_gfx9 ?:{ *:[i32] }:$ptr, anonymous_15035:{ *:[v3i32] }:$value, offset:{ *:[i32] }:$offset, 0:{ *:[i1] })
      GIR_BuildMI, /*InsnID*/0, /*Opcode*/GIMT_Encode2(AMDGPU::DS_WRITE_B96_gfx9),
      GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/0, // ptr
      GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/0, // value
      GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/1, // offset
      GIR_AddImm8, /*InsnID*/0, /*Imm*/0,
      GIR_MergeMemOperands, /*InsnID*/0, /*NumInsns*/1, /*MergeInsnID's*/0,
      GIR_ConstrainSelectedInstOperands, /*InsnID*/0,
      GIR_EraseFromParent, /*InsnID*/0,
      // GIR_Coverage, 6782,
      GIR_Done,
    // Label 2240: @147282
    GIM_Try, /*On fail goto*//*Label 2241*/ GIMT_Encode4(147343), // Rule ID 6786 //
      GIM_CheckFeatures, GIMT_Encode2(GIFBS_NotLDSRequiresM0Init_isGFX7Plus),
      GIM_CheckMemoryAddressSpace, /*MI*/0, /*MMO*/0, /*NumAddrSpace*/1, /*AddrSpace*/3,
      GIM_CheckMemoryAlignment, /*MI*/0, /*MMO*/0, /*MinAlign*/16,
      GIM_CheckAtomicOrdering, /*MI*/0, /*Order*/(uint8_t)AtomicOrdering::NotAtomic,
      GIM_CheckPointerToAny, /*MI*/0, /*Op*/1, /*SizeInBits*/0,
      GIM_CheckComplexPattern, /*MI*/0, /*Op*/1, /*Renderer*/GIMT_Encode2(0), GIMT_Encode2(GICP_gi_ds_1addr_1offset),
      // (st v3f32:{ *:[v3f32] }:$value, (DS1Addr1Offset:{ *:[iPTR] } i32:{ *:[i32] }:$ptr, i32:{ *:[i32] }:$offset))<<P:Predicate_unindexedstore>><<P:Predicate_store_local>><<P:Predicate_store_align16_local>>  =>  (DS_WRITE_B96_gfx9 ?:{ *:[i32] }:$ptr, anonymous_15035:{ *:[v3f32] }:$value, offset:{ *:[i32] }:$offset, 0:{ *:[i1] })
      GIR_BuildMI, /*InsnID*/0, /*Opcode*/GIMT_Encode2(AMDGPU::DS_WRITE_B96_gfx9),
      GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/0, // ptr
      GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/0, // value
      GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/1, // offset
      GIR_AddImm8, /*InsnID*/0, /*Imm*/0,
      GIR_MergeMemOperands, /*InsnID*/0, /*NumInsns*/1, /*MergeInsnID's*/0,
      GIR_ConstrainSelectedInstOperands, /*InsnID*/0,
      GIR_EraseFromParent, /*InsnID*/0,
      // GIR_Coverage, 6786,
      GIR_Done,
    // Label 2241: @147343
    GIM_Try, /*On fail goto*//*Label 2242*/ GIMT_Encode4(147408), // Rule ID 5554 //
      GIM_CheckFeatures, GIMT_Encode2(GIFBS_DisableFlatScratch_HasUnrestrictedSOffset),
      GIM_CheckMemoryAddressSpace, /*MI*/0, /*MMO*/0, /*NumAddrSpace*/1, /*AddrSpace*/5,
      GIM_CheckAtomicOrdering, /*MI*/0, /*Order*/(uint8_t)AtomicOrdering::NotAtomic,
      GIM_CheckPointerToAny, /*MI*/0, /*Op*/1, /*SizeInBits*/0,
      GIM_CheckComplexPattern, /*MI*/0, /*Op*/1, /*Renderer*/GIMT_Encode2(0), GIMT_Encode2(GICP_gi_mubuf_scratch_offset),
      // (st v3i32:{ *:[v3i32] }:$value, (MUBUFScratchOffset:{ *:[iPTR] } v4i32:{ *:[v4i32] }:$srsrc, i32:{ *:[i32] }:$soffset, i32:{ *:[i32] }:$offset))<<P:Predicate_unindexedstore>><<P:Predicate_store_private>>  =>  (BUFFER_STORE_DWORDX3_OFFSET VReg_96:{ *:[v3i32] }:$value, ?:{ *:[v4i32] }:$srsrc, ?:{ *:[i32] }:$soffset, ?:{ *:[i32] }:$offset, 0:{ *:[i32] }, 0:{ *:[i1] })
      GIR_BuildMI, /*InsnID*/0, /*Opcode*/GIMT_Encode2(AMDGPU::BUFFER_STORE_DWORDX3_OFFSET),
      GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/0, // value
      GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/0, // srsrc
      GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/1, // soffset
      GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/2, // offset
      GIR_AddImm8, /*InsnID*/0, /*Imm*/0,
      GIR_AddImm8, /*InsnID*/0, /*Imm*/0,
      GIR_MergeMemOperands, /*InsnID*/0, /*NumInsns*/1, /*MergeInsnID's*/0,
      GIR_ConstrainSelectedInstOperands, /*InsnID*/0,
      GIR_EraseFromParent, /*InsnID*/0,
      // GIR_Coverage, 5554,
      GIR_Done,
    // Label 2242: @147408
    GIM_Try, /*On fail goto*//*Label 2243*/ GIMT_Encode4(147473), // Rule ID 5556 //
      GIM_CheckFeatures, GIMT_Encode2(GIFBS_DisableFlatScratch),
      GIM_CheckMemoryAddressSpace, /*MI*/0, /*MMO*/0, /*NumAddrSpace*/1, /*AddrSpace*/5,
      GIM_CheckAtomicOrdering, /*MI*/0, /*Order*/(uint8_t)AtomicOrdering::NotAtomic,
      GIM_CheckPointerToAny, /*MI*/0, /*Op*/1, /*SizeInBits*/0,
      GIM_CheckComplexPattern, /*MI*/0, /*Op*/1, /*Renderer*/GIMT_Encode2(0), GIMT_Encode2(GICP_gi_mubuf_scratch_offset),
      // (st v3i32:{ *:[v3i32] }:$value, (MUBUFScratchOffset:{ *:[iPTR] } v4i32:{ *:[v4i32] }:$srsrc, i32:{ *:[i32] }:$soffset, i32:{ *:[i32] }:$offset))<<P:Predicate_unindexedstore>><<P:Predicate_store_private>>  =>  (BUFFER_STORE_DWORDX3_VBUFFER_OFFSET VReg_96:{ *:[v3i32] }:$value, ?:{ *:[v4i32] }:$srsrc, ?:{ *:[i32] }:$soffset, ?:{ *:[i32] }:$offset, 0:{ *:[i32] }, 0:{ *:[i1] })
      GIR_BuildMI, /*InsnID*/0, /*Opcode*/GIMT_Encode2(AMDGPU::BUFFER_STORE_DWORDX3_VBUFFER_OFFSET),
      GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/0, // value
      GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/0, // srsrc
      GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/1, // soffset
      GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/2, // offset
      GIR_AddImm8, /*InsnID*/0, /*Imm*/0,
      GIR_AddImm8, /*InsnID*/0, /*Imm*/0,
      GIR_MergeMemOperands, /*InsnID*/0, /*NumInsns*/1, /*MergeInsnID's*/0,
      GIR_ConstrainSelectedInstOperands, /*InsnID*/0,
      GIR_EraseFromParent, /*InsnID*/0,
      // GIR_Coverage, 5556,
      GIR_Done,
    // Label 2243: @147473
    GIM_Try, /*On fail goto*//*Label 2244*/ GIMT_Encode4(147535), // Rule ID 3601 //
      GIM_CheckFeatures, GIMT_Encode2(GIFBS_EnableFlatScratch_HasFlatScratchInsts_HasFlatScratchSVSMode),
      GIM_CheckMemoryAddressSpace, /*MI*/0, /*MMO*/0, /*NumAddrSpace*/1, /*AddrSpace*/5,
      GIM_CheckAtomicOrdering, /*MI*/0, /*Order*/(uint8_t)AtomicOrdering::NotAtomic,
      GIM_CheckPointerToAny, /*MI*/0, /*Op*/1, /*SizeInBits*/0,
      GIM_CheckComplexPattern, /*MI*/0, /*Op*/1, /*Renderer*/GIMT_Encode2(0), GIMT_Encode2(GICP_gi_flat_scratch_svaddr),
      // (st v3i32:{ *:[v3i32] }:$data, (ScratchSVAddr:{ *:[iPTR] } VGPR_32:{ *:[i32] }:$vaddr, SGPR_32:{ *:[i32] }:$saddr, i32:{ *:[i32] }:$offset))<<P:Predicate_unindexedstore>><<P:Predicate_store_private>>  =>  (SCRATCH_STORE_DWORDX3_SVS anonymous_15035:{ *:[v3i32] }:$data, ?:{ *:[i32] }:$vaddr, ?:{ *:[i32] }:$saddr, ?:{ *:[i32] }:$offset)
      GIR_BuildMI, /*InsnID*/0, /*Opcode*/GIMT_Encode2(AMDGPU::SCRATCH_STORE_DWORDX3_SVS),
      GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/0, // data
      GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/0, // vaddr
      GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/1, // saddr
      GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/2, // offset
      GIR_AddImm8, /*InsnID*/0, /*Imm*/0,
      GIR_MergeMemOperands, /*InsnID*/0, /*NumInsns*/1, /*MergeInsnID's*/0,
      GIR_ConstrainSelectedInstOperands, /*InsnID*/0,
      GIR_EraseFromParent, /*InsnID*/0,
      // GIR_Coverage, 3601,
      GIR_Done,
    // Label 2244: @147535
    GIM_Try, /*On fail goto*//*Label 2245*/ GIMT_Encode4(147592), // Rule ID 3600 //
      GIM_CheckFeatures, GIMT_Encode2(GIFBS_EnableFlatScratch_HasFlatScratchInsts),
      GIM_CheckMemoryAddressSpace, /*MI*/0, /*MMO*/0, /*NumAddrSpace*/1, /*AddrSpace*/5,
      GIM_CheckAtomicOrdering, /*MI*/0, /*Order*/(uint8_t)AtomicOrdering::NotAtomic,
      GIM_CheckPointerToAny, /*MI*/0, /*Op*/1, /*SizeInBits*/0,
      GIM_CheckComplexPattern, /*MI*/0, /*Op*/1, /*Renderer*/GIMT_Encode2(0), GIMT_Encode2(GICP_gi_flat_scratch_saddr),
      // (st v3i32:{ *:[v3i32] }:$data, (ScratchSAddr:{ *:[iPTR] } SGPR_32:{ *:[i32] }:$saddr, i32:{ *:[i32] }:$offset))<<P:Predicate_unindexedstore>><<P:Predicate_store_private>>  =>  (SCRATCH_STORE_DWORDX3_SADDR anonymous_15035:{ *:[v3i32] }:$data, ?:{ *:[i32] }:$saddr, ?:{ *:[i32] }:$offset)
      GIR_BuildMI, /*InsnID*/0, /*Opcode*/GIMT_Encode2(AMDGPU::SCRATCH_STORE_DWORDX3_SADDR),
      GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/0, // data
      GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/0, // saddr
      GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/1, // offset
      GIR_AddImm8, /*InsnID*/0, /*Imm*/0,
      GIR_MergeMemOperands, /*InsnID*/0, /*NumInsns*/1, /*MergeInsnID's*/0,
      GIR_ConstrainSelectedInstOperands, /*InsnID*/0,
      GIR_EraseFromParent, /*InsnID*/0,
      // GIR_Coverage, 3600,
      GIR_Done,
    // Label 2245: @147592
    GIM_Try, /*On fail goto*//*Label 2246*/ GIMT_Encode4(147649), // Rule ID 3599 //
      GIM_CheckFeatures, GIMT_Encode2(GIFBS_EnableFlatScratch_HasFlatScratchInsts),
      GIM_CheckMemoryAddressSpace, /*MI*/0, /*MMO*/0, /*NumAddrSpace*/1, /*AddrSpace*/5,
      GIM_CheckAtomicOrdering, /*MI*/0, /*Order*/(uint8_t)AtomicOrdering::NotAtomic,
      GIM_CheckPointerToAny, /*MI*/0, /*Op*/1, /*SizeInBits*/0,
      GIM_CheckComplexPattern, /*MI*/0, /*Op*/1, /*Renderer*/GIMT_Encode2(0), GIMT_Encode2(GICP_gi_flat_scratch_offset),
      // (st v3i32:{ *:[v3i32] }:$data, (ScratchOffset:{ *:[iPTR] } VGPR_32:{ *:[i32] }:$vaddr, i32:{ *:[i32] }:$offset))<<P:Predicate_unindexedstore>><<P:Predicate_store_private>>  =>  (SCRATCH_STORE_DWORDX3 anonymous_15035:{ *:[v3i32] }:$data, ?:{ *:[i32] }:$vaddr, ?:{ *:[i32] }:$offset)
      GIR_BuildMI, /*InsnID*/0, /*Opcode*/GIMT_Encode2(AMDGPU::SCRATCH_STORE_DWORDX3),
      GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/0, // data
      GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/0, // vaddr
      GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/1, // offset
      GIR_AddImm8, /*InsnID*/0, /*Imm*/0,
      GIR_MergeMemOperands, /*InsnID*/0, /*NumInsns*/1, /*MergeInsnID's*/0,
      GIR_ConstrainSelectedInstOperands, /*InsnID*/0,
      GIR_EraseFromParent, /*InsnID*/0,
      // GIR_Coverage, 3599,
      GIR_Done,
    // Label 2246: @147649
    GIM_Try, /*On fail goto*//*Label 2247*/ GIMT_Encode4(147719), // Rule ID 3878 //
      GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasUnrestrictedSOffset),
      GIM_CheckMemoryAddressSpace, /*MI*/0, /*MMO*/0, /*NumAddrSpace*/1, /*AddrSpace*/1,
      GIM_CheckAtomicOrdering, /*MI*/0, /*Order*/(uint8_t)AtomicOrdering::NotAtomic,
      GIM_CheckPointerToAny, /*MI*/0, /*Op*/1, /*SizeInBits*/0,
      GIM_CheckComplexPattern, /*MI*/0, /*Op*/1, /*Renderer*/GIMT_Encode2(0), GIMT_Encode2(GICP_gi_mubuf_addr64),
      // (st v3i32:{ *:[v3i32] }:$vdata, (MUBUFAddr64:{ *:[iPTR] } v4i32:{ *:[v4i32] }:$srsrc, i64:{ *:[i64] }:$vaddr, i32:{ *:[i32] }:$soffset, i32:{ *:[i32] }:$offset))<<P:Predicate_unindexedstore>><<P:Predicate_store_global>>  =>  (BUFFER_STORE_DWORDX3_ADDR64 v3i32:{ *:[v3i32] }:$vdata, i64:{ *:[i64] }:$vaddr, v4i32:{ *:[v4i32] }:$srsrc, i32:{ *:[i32] }:$soffset, i32:{ *:[i32] }:$offset)
      GIR_BuildMI, /*InsnID*/0, /*Opcode*/GIMT_Encode2(AMDGPU::BUFFER_STORE_DWORDX3_ADDR64),
      GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/0, // vdata
      GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/1, // vaddr
      GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/0, // srsrc
      GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/2, // soffset
      GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/3, // offset
      GIR_AddImm8, /*InsnID*/0, /*Imm*/0,
      GIR_AddImm8, /*InsnID*/0, /*Imm*/0,
      GIR_MergeMemOperands, /*InsnID*/0, /*NumInsns*/1, /*MergeInsnID's*/0,
      GIR_ConstrainSelectedInstOperands, /*InsnID*/0,
      GIR_EraseFromParent, /*InsnID*/0,
      // GIR_Coverage, 3878,
      GIR_Done,
    // Label 2247: @147719
    GIM_Try, /*On fail goto*//*Label 2248*/ GIMT_Encode4(147786), // Rule ID 3880 //
      GIM_CheckMemoryAddressSpace, /*MI*/0, /*MMO*/0, /*NumAddrSpace*/1, /*AddrSpace*/1,
      GIM_CheckAtomicOrdering, /*MI*/0, /*Order*/(uint8_t)AtomicOrdering::NotAtomic,
      GIM_CheckPointerToAny, /*MI*/0, /*Op*/1, /*SizeInBits*/0,
      GIM_CheckComplexPattern, /*MI*/0, /*Op*/1, /*Renderer*/GIMT_Encode2(0), GIMT_Encode2(GICP_gi_mubuf_addr64),
      // (st v3i32:{ *:[v3i32] }:$vdata, (MUBUFAddr64:{ *:[iPTR] } v4i32:{ *:[v4i32] }:$srsrc, i64:{ *:[i64] }:$vaddr, i32:{ *:[i32] }:$soffset, i32:{ *:[i32] }:$offset))<<P:Predicate_unindexedstore>><<P:Predicate_store_global>>  =>  (BUFFER_STORE_DWORDX3_VBUFFER_ADDR64 v3i32:{ *:[v3i32] }:$vdata, i64:{ *:[i64] }:$vaddr, v4i32:{ *:[v4i32] }:$srsrc, i32:{ *:[i32] }:$soffset, i32:{ *:[i32] }:$offset)
      GIR_BuildMI, /*InsnID*/0, /*Opcode*/GIMT_Encode2(AMDGPU::BUFFER_STORE_DWORDX3_VBUFFER_ADDR64),
      GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/0, // vdata
      GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/1, // vaddr
      GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/0, // srsrc
      GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/2, // soffset
      GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/3, // offset
      GIR_AddImm8, /*InsnID*/0, /*Imm*/0,
      GIR_AddImm8, /*InsnID*/0, /*Imm*/0,
      GIR_MergeMemOperands, /*InsnID*/0, /*NumInsns*/1, /*MergeInsnID's*/0,
      GIR_ConstrainSelectedInstOperands, /*InsnID*/0,
      GIR_EraseFromParent, /*InsnID*/0,
      // GIR_Coverage, 3880,
      GIR_Done,
    // Label 2248: @147786
    GIM_Try, /*On fail goto*//*Label 2249*/ GIMT_Encode4(147856), // Rule ID 3882 //
      GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasUnrestrictedSOffset),
      GIM_CheckMemoryAddressSpace, /*MI*/0, /*MMO*/0, /*NumAddrSpace*/1, /*AddrSpace*/1,
      GIM_CheckAtomicOrdering, /*MI*/0, /*Order*/(uint8_t)AtomicOrdering::NotAtomic,
      GIM_CheckPointerToAny, /*MI*/0, /*Op*/1, /*SizeInBits*/0,
      GIM_CheckComplexPattern, /*MI*/0, /*Op*/1, /*Renderer*/GIMT_Encode2(0), GIMT_Encode2(GICP_gi_mubuf_addr64),
      // (st v3f32:{ *:[v3f32] }:$vdata, (MUBUFAddr64:{ *:[iPTR] } v4i32:{ *:[v4i32] }:$srsrc, i64:{ *:[i64] }:$vaddr, i32:{ *:[i32] }:$soffset, i32:{ *:[i32] }:$offset))<<P:Predicate_unindexedstore>><<P:Predicate_store_global>>  =>  (BUFFER_STORE_DWORDX3_ADDR64 v3f32:{ *:[v3f32] }:$vdata, i64:{ *:[i64] }:$vaddr, v4i32:{ *:[v4i32] }:$srsrc, i32:{ *:[i32] }:$soffset, i32:{ *:[i32] }:$offset)
      GIR_BuildMI, /*InsnID*/0, /*Opcode*/GIMT_Encode2(AMDGPU::BUFFER_STORE_DWORDX3_ADDR64),
      GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/0, // vdata
      GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/1, // vaddr
      GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/0, // srsrc
      GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/2, // soffset
      GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/3, // offset
      GIR_AddImm8, /*InsnID*/0, /*Imm*/0,
      GIR_AddImm8, /*InsnID*/0, /*Imm*/0,
      GIR_MergeMemOperands, /*InsnID*/0, /*NumInsns*/1, /*MergeInsnID's*/0,
      GIR_ConstrainSelectedInstOperands, /*InsnID*/0,
      GIR_EraseFromParent, /*InsnID*/0,
      // GIR_Coverage, 3882,
      GIR_Done,
    // Label 2249: @147856
    GIM_Try, /*On fail goto*//*Label 2250*/ GIMT_Encode4(147923), // Rule ID 3884 //
      GIM_CheckMemoryAddressSpace, /*MI*/0, /*MMO*/0, /*NumAddrSpace*/1, /*AddrSpace*/1,
      GIM_CheckAtomicOrdering, /*MI*/0, /*Order*/(uint8_t)AtomicOrdering::NotAtomic,
      GIM_CheckPointerToAny, /*MI*/0, /*Op*/1, /*SizeInBits*/0,
      GIM_CheckComplexPattern, /*MI*/0, /*Op*/1, /*Renderer*/GIMT_Encode2(0), GIMT_Encode2(GICP_gi_mubuf_addr64),
      // (st v3f32:{ *:[v3f32] }:$vdata, (MUBUFAddr64:{ *:[iPTR] } v4i32:{ *:[v4i32] }:$srsrc, i64:{ *:[i64] }:$vaddr, i32:{ *:[i32] }:$soffset, i32:{ *:[i32] }:$offset))<<P:Predicate_unindexedstore>><<P:Predicate_store_global>>  =>  (BUFFER_STORE_DWORDX3_VBUFFER_ADDR64 v3f32:{ *:[v3f32] }:$vdata, i64:{ *:[i64] }:$vaddr, v4i32:{ *:[v4i32] }:$srsrc, i32:{ *:[i32] }:$soffset, i32:{ *:[i32] }:$offset)
      GIR_BuildMI, /*InsnID*/0, /*Opcode*/GIMT_Encode2(AMDGPU::BUFFER_STORE_DWORDX3_VBUFFER_ADDR64),
      GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/0, // vdata
      GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/1, // vaddr
      GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/0, // srsrc
      GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/2, // soffset
      GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/3, // offset
      GIR_AddImm8, /*InsnID*/0, /*Imm*/0,
      GIR_AddImm8, /*InsnID*/0, /*Imm*/0,
      GIR_MergeMemOperands, /*InsnID*/0, /*NumInsns*/1, /*MergeInsnID's*/0,
      GIR_ConstrainSelectedInstOperands, /*InsnID*/0,
      GIR_EraseFromParent, /*InsnID*/0,
      // GIR_Coverage, 3884,
      GIR_Done,
    // Label 2250: @147923
    GIM_Try, /*On fail goto*//*Label 2251*/ GIMT_Encode4(147993), // Rule ID 5553 //
      GIM_CheckFeatures, GIMT_Encode2(GIFBS_DisableFlatScratch_HasUnrestrictedSOffset),
      GIM_CheckMemoryAddressSpace, /*MI*/0, /*MMO*/0, /*NumAddrSpace*/1, /*AddrSpace*/5,
      GIM_CheckAtomicOrdering, /*MI*/0, /*Order*/(uint8_t)AtomicOrdering::NotAtomic,
      GIM_CheckPointerToAny, /*MI*/0, /*Op*/1, /*SizeInBits*/0,
      GIM_CheckComplexPattern, /*MI*/0, /*Op*/1, /*Renderer*/GIMT_Encode2(0), GIMT_Encode2(GICP_gi_mubuf_scratch_offen),
      // (st v3i32:{ *:[v3i32] }:$value, (MUBUFScratchOffen:{ *:[iPTR] } v4i32:{ *:[v4i32] }:$srsrc, i32:{ *:[i32] }:$vaddr, i32:{ *:[i32] }:$soffset, i32:{ *:[i32] }:$offset))<<P:Predicate_unindexedstore>><<P:Predicate_store_private>>  =>  (BUFFER_STORE_DWORDX3_OFFEN VReg_96:{ *:[v3i32] }:$value, ?:{ *:[i32] }:$vaddr, ?:{ *:[v4i32] }:$srsrc, ?:{ *:[i32] }:$soffset, ?:{ *:[i32] }:$offset, 0:{ *:[i32] }, 0:{ *:[i1] })
      GIR_BuildMI, /*InsnID*/0, /*Opcode*/GIMT_Encode2(AMDGPU::BUFFER_STORE_DWORDX3_OFFEN),
      GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/0, // value
      GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/1, // vaddr
      GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/0, // srsrc
      GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/2, // soffset
      GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/3, // offset
      GIR_AddImm8, /*InsnID*/0, /*Imm*/0,
      GIR_AddImm8, /*InsnID*/0, /*Imm*/0,
      GIR_MergeMemOperands, /*InsnID*/0, /*NumInsns*/1, /*MergeInsnID's*/0,
      GIR_ConstrainSelectedInstOperands, /*InsnID*/0,
      GIR_EraseFromParent, /*InsnID*/0,
      // GIR_Coverage, 5553,
      GIR_Done,
    // Label 2251: @147993
    GIM_Try, /*On fail goto*//*Label 2252*/ GIMT_Encode4(148063), // Rule ID 5555 //
      GIM_CheckFeatures, GIMT_Encode2(GIFBS_DisableFlatScratch),
      GIM_CheckMemoryAddressSpace, /*MI*/0, /*MMO*/0, /*NumAddrSpace*/1, /*AddrSpace*/5,
      GIM_CheckAtomicOrdering, /*MI*/0, /*Order*/(uint8_t)AtomicOrdering::NotAtomic,
      GIM_CheckPointerToAny, /*MI*/0, /*Op*/1, /*SizeInBits*/0,
      GIM_CheckComplexPattern, /*MI*/0, /*Op*/1, /*Renderer*/GIMT_Encode2(0), GIMT_Encode2(GICP_gi_mubuf_scratch_offen),
      // (st v3i32:{ *:[v3i32] }:$value, (MUBUFScratchOffen:{ *:[iPTR] } v4i32:{ *:[v4i32] }:$srsrc, i32:{ *:[i32] }:$vaddr, i32:{ *:[i32] }:$soffset, i32:{ *:[i32] }:$offset))<<P:Predicate_unindexedstore>><<P:Predicate_store_private>>  =>  (BUFFER_STORE_DWORDX3_VBUFFER_OFFEN VReg_96:{ *:[v3i32] }:$value, ?:{ *:[i32] }:$vaddr, ?:{ *:[v4i32] }:$srsrc, ?:{ *:[i32] }:$soffset, ?:{ *:[i32] }:$offset, 0:{ *:[i32] }, 0:{ *:[i1] })
      GIR_BuildMI, /*InsnID*/0, /*Opcode*/GIMT_Encode2(AMDGPU::BUFFER_STORE_DWORDX3_VBUFFER_OFFEN),
      GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/0, // value
      GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/1, // vaddr
      GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/0, // srsrc
      GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/2, // soffset
      GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/3, // offset
      GIR_AddImm8, /*InsnID*/0, /*Imm*/0,
      GIR_AddImm8, /*InsnID*/0, /*Imm*/0,
      GIR_MergeMemOperands, /*InsnID*/0, /*NumInsns*/1, /*MergeInsnID's*/0,
      GIR_ConstrainSelectedInstOperands, /*InsnID*/0,
      GIR_EraseFromParent, /*InsnID*/0,
      // GIR_Coverage, 5555,
      GIR_Done,
    // Label 2252: @148063
    GIM_Try, /*On fail goto*//*Label 2253*/ GIMT_Encode4(148128), // Rule ID 3877 //
      GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasUnrestrictedSOffset),
      GIM_CheckMemoryAddressSpace, /*MI*/0, /*MMO*/0, /*NumAddrSpace*/1, /*AddrSpace*/1,
      GIM_CheckAtomicOrdering, /*MI*/0, /*Order*/(uint8_t)AtomicOrdering::NotAtomic,
      GIM_CheckPointerToAny, /*MI*/0, /*Op*/1, /*SizeInBits*/0,
      GIM_CheckComplexPattern, /*MI*/0, /*Op*/1, /*Renderer*/GIMT_Encode2(0), GIMT_Encode2(GICP_gi_mubuf_offset),
      // (st v3i32:{ *:[v3i32] }:$vdata, (MUBUFOffset:{ *:[iPTR] } v4i32:{ *:[v4i32] }:$srsrc, i32:{ *:[i32] }:$soffset, i32:{ *:[i32] }:$offset))<<P:Predicate_unindexedstore>><<P:Predicate_store_global>>  =>  (BUFFER_STORE_DWORDX3_OFFSET v3i32:{ *:[v3i32] }:$vdata, v4i32:{ *:[v4i32] }:$srsrc, i32:{ *:[i32] }:$soffset, i32:{ *:[i32] }:$offset)
      GIR_BuildMI, /*InsnID*/0, /*Opcode*/GIMT_Encode2(AMDGPU::BUFFER_STORE_DWORDX3_OFFSET),
      GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/0, // vdata
      GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/0, // srsrc
      GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/1, // soffset
      GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/2, // offset
      GIR_AddImm8, /*InsnID*/0, /*Imm*/0,
      GIR_AddImm8, /*InsnID*/0, /*Imm*/0,
      GIR_MergeMemOperands, /*InsnID*/0, /*NumInsns*/1, /*MergeInsnID's*/0,
      GIR_ConstrainSelectedInstOperands, /*InsnID*/0,
      GIR_EraseFromParent, /*InsnID*/0,
      // GIR_Coverage, 3877,
      GIR_Done,
    // Label 2253: @148128
    GIM_Try, /*On fail goto*//*Label 2254*/ GIMT_Encode4(148190), // Rule ID 3879 //
      GIM_CheckMemoryAddressSpace, /*MI*/0, /*MMO*/0, /*NumAddrSpace*/1, /*AddrSpace*/1,
      GIM_CheckAtomicOrdering, /*MI*/0, /*Order*/(uint8_t)AtomicOrdering::NotAtomic,
      GIM_CheckPointerToAny, /*MI*/0, /*Op*/1, /*SizeInBits*/0,
      GIM_CheckComplexPattern, /*MI*/0, /*Op*/1, /*Renderer*/GIMT_Encode2(0), GIMT_Encode2(GICP_gi_mubuf_offset),
      // (st v3i32:{ *:[v3i32] }:$vdata, (MUBUFOffset:{ *:[iPTR] } v4i32:{ *:[v4i32] }:$srsrc, i32:{ *:[i32] }:$soffset, i32:{ *:[i32] }:$offset))<<P:Predicate_unindexedstore>><<P:Predicate_store_global>>  =>  (BUFFER_STORE_DWORDX3_VBUFFER_OFFSET v3i32:{ *:[v3i32] }:$vdata, v4i32:{ *:[v4i32] }:$srsrc, i32:{ *:[i32] }:$soffset, i32:{ *:[i32] }:$offset)
      GIR_BuildMI, /*InsnID*/0, /*Opcode*/GIMT_Encode2(AMDGPU::BUFFER_STORE_DWORDX3_VBUFFER_OFFSET),
      GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/0, // vdata
      GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/0, // srsrc
      GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/1, // soffset
      GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/2, // offset
      GIR_AddImm8, /*InsnID*/0, /*Imm*/0,
      GIR_AddImm8, /*InsnID*/0, /*Imm*/0,
      GIR_MergeMemOperands, /*InsnID*/0, /*NumInsns*/1, /*MergeInsnID's*/0,
      GIR_ConstrainSelectedInstOperands, /*InsnID*/0,
      GIR_EraseFromParent, /*InsnID*/0,
      // GIR_Coverage, 3879,
      GIR_Done,
    // Label 2254: @148190
    GIM_Try, /*On fail goto*//*Label 2255*/ GIMT_Encode4(148255), // Rule ID 3881 //
      GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasUnrestrictedSOffset),
      GIM_CheckMemoryAddressSpace, /*MI*/0, /*MMO*/0, /*NumAddrSpace*/1, /*AddrSpace*/1,
      GIM_CheckAtomicOrdering, /*MI*/0, /*Order*/(uint8_t)AtomicOrdering::NotAtomic,
      GIM_CheckPointerToAny, /*MI*/0, /*Op*/1, /*SizeInBits*/0,
      GIM_CheckComplexPattern, /*MI*/0, /*Op*/1, /*Renderer*/GIMT_Encode2(0), GIMT_Encode2(GICP_gi_mubuf_offset),
      // (st v3f32:{ *:[v3f32] }:$vdata, (MUBUFOffset:{ *:[iPTR] } v4i32:{ *:[v4i32] }:$srsrc, i32:{ *:[i32] }:$soffset, i32:{ *:[i32] }:$offset))<<P:Predicate_unindexedstore>><<P:Predicate_store_global>>  =>  (BUFFER_STORE_DWORDX3_OFFSET v3f32:{ *:[v3f32] }:$vdata, v4i32:{ *:[v4i32] }:$srsrc, i32:{ *:[i32] }:$soffset, i32:{ *:[i32] }:$offset)
      GIR_BuildMI, /*InsnID*/0, /*Opcode*/GIMT_Encode2(AMDGPU::BUFFER_STORE_DWORDX3_OFFSET),
      GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/0, // vdata
      GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/0, // srsrc
      GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/1, // soffset
      GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/2, // offset
      GIR_AddImm8, /*InsnID*/0, /*Imm*/0,
      GIR_AddImm8, /*InsnID*/0, /*Imm*/0,
      GIR_MergeMemOperands, /*InsnID*/0, /*NumInsns*/1, /*MergeInsnID's*/0,
      GIR_ConstrainSelectedInstOperands, /*InsnID*/0,
      GIR_EraseFromParent, /*InsnID*/0,
      // GIR_Coverage, 3881,
      GIR_Done,
    // Label 2255: @148255
    GIM_Try, /*On fail goto*//*Label 2256*/ GIMT_Encode4(148317), // Rule ID 3883 //
      GIM_CheckMemoryAddressSpace, /*MI*/0, /*MMO*/0, /*NumAddrSpace*/1, /*AddrSpace*/1,
      GIM_CheckAtomicOrdering, /*MI*/0, /*Order*/(uint8_t)AtomicOrdering::NotAtomic,
      GIM_CheckPointerToAny, /*MI*/0, /*Op*/1, /*SizeInBits*/0,
      GIM_CheckComplexPattern, /*MI*/0, /*Op*/1, /*Renderer*/GIMT_Encode2(0), GIMT_Encode2(GICP_gi_mubuf_offset),
      // (st v3f32:{ *:[v3f32] }:$vdata, (MUBUFOffset:{ *:[iPTR] } v4i32:{ *:[v4i32] }:$srsrc, i32:{ *:[i32] }:$soffset, i32:{ *:[i32] }:$offset))<<P:Predicate_unindexedstore>><<P:Predicate_store_global>>  =>  (BUFFER_STORE_DWORDX3_VBUFFER_OFFSET v3f32:{ *:[v3f32] }:$vdata, v4i32:{ *:[v4i32] }:$srsrc, i32:{ *:[i32] }:$soffset, i32:{ *:[i32] }:$offset)
      GIR_BuildMI, /*InsnID*/0, /*Opcode*/GIMT_Encode2(AMDGPU::BUFFER_STORE_DWORDX3_VBUFFER_OFFSET),
      GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/0, // vdata
      GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/0, // srsrc
      GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/1, // soffset
      GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/2, // offset
      GIR_AddImm8, /*InsnID*/0, /*Imm*/0,
      GIR_AddImm8, /*InsnID*/0, /*Imm*/0,
      GIR_MergeMemOperands, /*InsnID*/0, /*NumInsns*/1, /*MergeInsnID's*/0,
      GIR_ConstrainSelectedInstOperands, /*InsnID*/0,
      GIR_EraseFromParent, /*InsnID*/0,
      // GIR_Coverage, 3883,
      GIR_Done,
    // Label 2256: @148317
    GIM_Try, /*On fail goto*//*Label 2257*/ GIMT_Encode4(148379), // Rule ID 3111 //
      GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasFlatGlobalInsts),
      GIM_CheckMemoryAddressSpace, /*MI*/0, /*MMO*/0, /*NumAddrSpace*/1, /*AddrSpace*/1,
      GIM_CheckAtomicOrdering, /*MI*/0, /*Order*/(uint8_t)AtomicOrdering::NotAtomic,
      GIM_CheckPointerToAny, /*MI*/0, /*Op*/1, /*SizeInBits*/0,
      GIM_CheckComplexPattern, /*MI*/0, /*Op*/1, /*Renderer*/GIMT_Encode2(0), GIMT_Encode2(GICP_gi_global_saddr),
      // (st v3i32:{ *:[v3i32] }:$data, (GlobalSAddr:{ *:[iPTR] } SReg_64:{ *:[i64] }:$saddr, VGPR_32:{ *:[i32] }:$voffset, i32:{ *:[i32] }:$offset))<<P:Predicate_unindexedstore>><<P:Predicate_store_global>>  =>  (GLOBAL_STORE_DWORDX3_SADDR ?:{ *:[i32] }:$voffset, anonymous_15035:{ *:[v3i32] }:$data, ?:{ *:[i64] }:$saddr, ?:{ *:[i32] }:$offset)
      GIR_BuildMI, /*InsnID*/0, /*Opcode*/GIMT_Encode2(AMDGPU::GLOBAL_STORE_DWORDX3_SADDR),
      GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/1, // voffset
      GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/0, // data
      GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/0, // saddr
      GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/2, // offset
      GIR_AddImm8, /*InsnID*/0, /*Imm*/0,
      GIR_MergeMemOperands, /*InsnID*/0, /*NumInsns*/1, /*MergeInsnID's*/0,
      GIR_ConstrainSelectedInstOperands, /*InsnID*/0,
      GIR_EraseFromParent, /*InsnID*/0,
      // GIR_Coverage, 3111,
      GIR_Done,
    // Label 2257: @148379
    GIM_Try, /*On fail goto*//*Label 2258*/ GIMT_Encode4(148436), // Rule ID 3110 //
      GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasFlatGlobalInsts),
      GIM_CheckMemoryAddressSpace, /*MI*/0, /*MMO*/0, /*NumAddrSpace*/1, /*AddrSpace*/1,
      GIM_CheckAtomicOrdering, /*MI*/0, /*Order*/(uint8_t)AtomicOrdering::NotAtomic,
      GIM_CheckPointerToAny, /*MI*/0, /*Op*/1, /*SizeInBits*/0,
      GIM_CheckComplexPattern, /*MI*/0, /*Op*/1, /*Renderer*/GIMT_Encode2(0), GIMT_Encode2(GICP_gi_global_offset),
      // (st v3i32:{ *:[v3i32] }:$data, (GlobalOffset:{ *:[iPTR] } i64:{ *:[i64] }:$vaddr, i32:{ *:[i32] }:$offset))<<P:Predicate_unindexedstore>><<P:Predicate_store_global>>  =>  (GLOBAL_STORE_DWORDX3 ?:{ *:[i64] }:$vaddr, anonymous_15035:{ *:[v3i32] }:$data, ?:{ *:[i32] }:$offset)
      GIR_BuildMI, /*InsnID*/0, /*Opcode*/GIMT_Encode2(AMDGPU::GLOBAL_STORE_DWORDX3),
      GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/0, // vaddr
      GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/0, // data
      GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/1, // offset
      GIR_AddImm8, /*InsnID*/0, /*Imm*/0,
      GIR_MergeMemOperands, /*InsnID*/0, /*NumInsns*/1, /*MergeInsnID's*/0,
      GIR_ConstrainSelectedInstOperands, /*InsnID*/0,
      GIR_EraseFromParent, /*InsnID*/0,
      // GIR_Coverage, 3110,
      GIR_Done,
    // Label 2258: @148436
    GIM_Try, /*On fail goto*//*Label 2259*/ GIMT_Encode4(148494), // Rule ID 2808 //
      GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasFlatAddressSpace),
      GIM_CheckMemoryAddressSpace, /*MI*/0, /*MMO*/0, /*NumAddrSpace*/2, /*AddrSpace*/0, /*AddrSpace*/1,
      GIM_CheckAtomicOrdering, /*MI*/0, /*Order*/(uint8_t)AtomicOrdering::NotAtomic,
      GIM_CheckPointerToAny, /*MI*/0, /*Op*/1, /*SizeInBits*/0,
      GIM_CheckComplexPattern, /*MI*/0, /*Op*/1, /*Renderer*/GIMT_Encode2(0), GIMT_Encode2(GICP_gi_flat_offset),
      // (st v3i32:{ *:[v3i32] }:$data, (FlatOffset:{ *:[iPTR] } i64:{ *:[i64] }:$vaddr, i32:{ *:[i32] }:$offset))<<P:Predicate_unindexedstore>><<P:Predicate_store_flat>>  =>  (FLAT_STORE_DWORDX3 ?:{ *:[i64] }:$vaddr, anonymous_15035:{ *:[v3i32] }:$data, ?:{ *:[i32] }:$offset)
      GIR_BuildMI, /*InsnID*/0, /*Opcode*/GIMT_Encode2(AMDGPU::FLAT_STORE_DWORDX3),
      GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/0, // vaddr
      GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/0, // data
      GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/1, // offset
      GIR_AddImm8, /*InsnID*/0, /*Imm*/0,
      GIR_MergeMemOperands, /*InsnID*/0, /*NumInsns*/1, /*MergeInsnID's*/0,
      GIR_ConstrainSelectedInstOperands, /*InsnID*/0,
      GIR_EraseFromParent, /*InsnID*/0,
      // GIR_Coverage, 2808,
      GIR_Done,
    // Label 2259: @148494
    GIM_Reject,
    // Label 1820: @148495
    GIM_Try, /*On fail goto*//*Label 2260*/ GIMT_Encode4(148565), // Rule ID 6833 //
      GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasUnalignedAccessMode_LDSRequiresM0Init),
      GIM_CheckMemorySizeEqualToLLT, /*MI*/0, /*MMO*/0, /*OpIdx*/0,
      GIM_CheckMemoryAddressSpace, /*MI*/0, /*MMO*/0, /*NumAddrSpace*/1, /*AddrSpace*/3,
      GIM_CheckMemoryAddressSpace, /*MI*/0, /*MMO*/0, /*NumAddrSpace*/1, /*AddrSpace*/3,
      GIM_CheckAtomicOrdering, /*MI*/0, /*Order*/(uint8_t)AtomicOrdering::NotAtomic,
      GIM_CheckPointerToAny, /*MI*/0, /*Op*/1, /*SizeInBits*/0,
      GIM_CheckCxxInsnPredicate, /*MI*/0, /*FnId*/GIMT_Encode2(GICXXPred_MI_Predicate_store_align_less_than_4_local_m0),
      GIM_CheckComplexPattern, /*MI*/0, /*Op*/1, /*Renderer*/GIMT_Encode2(0), GIMT_Encode2(GICP_gi_ds_1addr_1offset),
      // (AMDGPUst_glue v4f16:{ *:[v4f16] }:$value, (DS1Addr1Offset:{ *:[iPTR] } i32:{ *:[i32] }:$ptr, i32:{ *:[i32] }:$offset))<<P:Predicate_unindexedstore_glue>><<P:Predicate_store_glue>><<P:Predicate_store_local_m0>><<P:Predicate_store_align_less_than_4_local_m0>>  =>  (DS_WRITE_B64 ?:{ *:[i32] }:$ptr, anonymous_15036:{ *:[v4f16] }:$value, offset:{ *:[i32] }:$offset, 0:{ *:[i1] })
      GIR_BuildMI, /*InsnID*/0, /*Opcode*/GIMT_Encode2(AMDGPU::DS_WRITE_B64),
      GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/0, // ptr
      GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/0, // value
      GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/1, // offset
      GIR_AddImm8, /*InsnID*/0, /*Imm*/0,
      GIR_MergeMemOperands, /*InsnID*/0, /*NumInsns*/1, /*MergeInsnID's*/0,
      GIR_ConstrainSelectedInstOperands, /*InsnID*/0,
      GIR_EraseFromParent, /*InsnID*/0,
      // GIR_Coverage, 6833,
      GIR_Done,
    // Label 2260: @148565
    GIM_Try, /*On fail goto*//*Label 2261*/ GIMT_Encode4(148635), // Rule ID 6837 //
      GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasUnalignedAccessMode_LDSRequiresM0Init),
      GIM_CheckMemorySizeEqualToLLT, /*MI*/0, /*MMO*/0, /*OpIdx*/0,
      GIM_CheckMemoryAddressSpace, /*MI*/0, /*MMO*/0, /*NumAddrSpace*/1, /*AddrSpace*/3,
      GIM_CheckMemoryAddressSpace, /*MI*/0, /*MMO*/0, /*NumAddrSpace*/1, /*AddrSpace*/3,
      GIM_CheckAtomicOrdering, /*MI*/0, /*Order*/(uint8_t)AtomicOrdering::NotAtomic,
      GIM_CheckPointerToAny, /*MI*/0, /*Op*/1, /*SizeInBits*/0,
      GIM_CheckCxxInsnPredicate, /*MI*/0, /*FnId*/GIMT_Encode2(GICXXPred_MI_Predicate_store_align_less_than_4_local_m0),
      GIM_CheckComplexPattern, /*MI*/0, /*Op*/1, /*Renderer*/GIMT_Encode2(0), GIMT_Encode2(GICP_gi_ds_1addr_1offset),
      // (AMDGPUst_glue v4bf16:{ *:[v4bf16] }:$value, (DS1Addr1Offset:{ *:[iPTR] } i32:{ *:[i32] }:$ptr, i32:{ *:[i32] }:$offset))<<P:Predicate_unindexedstore_glue>><<P:Predicate_store_glue>><<P:Predicate_store_local_m0>><<P:Predicate_store_align_less_than_4_local_m0>>  =>  (DS_WRITE_B64 ?:{ *:[i32] }:$ptr, anonymous_15036:{ *:[v4bf16] }:$value, offset:{ *:[i32] }:$offset, 0:{ *:[i1] })
      GIR_BuildMI, /*InsnID*/0, /*Opcode*/GIMT_Encode2(AMDGPU::DS_WRITE_B64),
      GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/0, // ptr
      GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/0, // value
      GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/1, // offset
      GIR_AddImm8, /*InsnID*/0, /*Imm*/0,
      GIR_MergeMemOperands, /*InsnID*/0, /*NumInsns*/1, /*MergeInsnID's*/0,
      GIR_ConstrainSelectedInstOperands, /*InsnID*/0,
      GIR_EraseFromParent, /*InsnID*/0,
      // GIR_Coverage, 6837,
      GIR_Done,
    // Label 2261: @148635
    GIM_Try, /*On fail goto*//*Label 2262*/ GIMT_Encode4(148705), // Rule ID 6841 //
      GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasUnalignedAccessMode_LDSRequiresM0Init),
      GIM_CheckMemorySizeEqualToLLT, /*MI*/0, /*MMO*/0, /*OpIdx*/0,
      GIM_CheckMemoryAddressSpace, /*MI*/0, /*MMO*/0, /*NumAddrSpace*/1, /*AddrSpace*/3,
      GIM_CheckMemoryAddressSpace, /*MI*/0, /*MMO*/0, /*NumAddrSpace*/1, /*AddrSpace*/3,
      GIM_CheckAtomicOrdering, /*MI*/0, /*Order*/(uint8_t)AtomicOrdering::NotAtomic,
      GIM_CheckPointerToAny, /*MI*/0, /*Op*/1, /*SizeInBits*/0,
      GIM_CheckCxxInsnPredicate, /*MI*/0, /*FnId*/GIMT_Encode2(GICXXPred_MI_Predicate_store_align_less_than_4_local_m0),
      GIM_CheckComplexPattern, /*MI*/0, /*Op*/1, /*Renderer*/GIMT_Encode2(0), GIMT_Encode2(GICP_gi_ds_1addr_1offset),
      // (AMDGPUst_glue v4i16:{ *:[v4i16] }:$value, (DS1Addr1Offset:{ *:[iPTR] } i32:{ *:[i32] }:$ptr, i32:{ *:[i32] }:$offset))<<P:Predicate_unindexedstore_glue>><<P:Predicate_store_glue>><<P:Predicate_store_local_m0>><<P:Predicate_store_align_less_than_4_local_m0>>  =>  (DS_WRITE_B64 ?:{ *:[i32] }:$ptr, anonymous_15036:{ *:[v4i16] }:$value, offset:{ *:[i32] }:$offset, 0:{ *:[i1] })
      GIR_BuildMI, /*InsnID*/0, /*Opcode*/GIMT_Encode2(AMDGPU::DS_WRITE_B64),
      GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/0, // ptr
      GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/0, // value
      GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/1, // offset
      GIR_AddImm8, /*InsnID*/0, /*Imm*/0,
      GIR_MergeMemOperands, /*InsnID*/0, /*NumInsns*/1, /*MergeInsnID's*/0,
      GIR_ConstrainSelectedInstOperands, /*InsnID*/0,
      GIR_EraseFromParent, /*InsnID*/0,
      // GIR_Coverage, 6841,
      GIR_Done,
    // Label 2262: @148705
    GIM_Try, /*On fail goto*//*Label 2263*/ GIMT_Encode4(148770), // Rule ID 6757 //
      GIM_CheckFeatures, GIMT_Encode2(GIFBS_LDSRequiresM0Init),
      GIM_CheckMemorySizeEqualToLLT, /*MI*/0, /*MMO*/0, /*OpIdx*/0,
      GIM_CheckMemoryAddressSpace, /*MI*/0, /*MMO*/0, /*NumAddrSpace*/1, /*AddrSpace*/3,
      GIM_CheckMemoryAlignment, /*MI*/0, /*MMO*/0, /*MinAlign*/8,
      GIM_CheckAtomicOrdering, /*MI*/0, /*Order*/(uint8_t)AtomicOrdering::NotAtomic,
      GIM_CheckPointerToAny, /*MI*/0, /*Op*/1, /*SizeInBits*/0,
      GIM_CheckComplexPattern, /*MI*/0, /*Op*/1, /*Renderer*/GIMT_Encode2(0), GIMT_Encode2(GICP_gi_ds_1addr_1offset),
      // (AMDGPUst_glue v4f16:{ *:[v4f16] }:$value, (DS1Addr1Offset:{ *:[iPTR] } i32:{ *:[i32] }:$ptr, i32:{ *:[i32] }:$offset))<<P:Predicate_unindexedstore_glue>><<P:Predicate_store_glue>><<P:Predicate_store_local_m0>><<P:Predicate_store_align8_local_m0>>  =>  (DS_WRITE_B64 ?:{ *:[i32] }:$ptr, anonymous_15036:{ *:[v4f16] }:$value, offset:{ *:[i32] }:$offset, 0:{ *:[i1] })
      GIR_BuildMI, /*InsnID*/0, /*Opcode*/GIMT_Encode2(AMDGPU::DS_WRITE_B64),
      GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/0, // ptr
      GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/0, // value
      GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/1, // offset
      GIR_AddImm8, /*InsnID*/0, /*Imm*/0,
      GIR_MergeMemOperands, /*InsnID*/0, /*NumInsns*/1, /*MergeInsnID's*/0,
      GIR_ConstrainSelectedInstOperands, /*InsnID*/0,
      GIR_EraseFromParent, /*InsnID*/0,
      // GIR_Coverage, 6757,
      GIR_Done,
    // Label 2263: @148770
    GIM_Try, /*On fail goto*//*Label 2264*/ GIMT_Encode4(148835), // Rule ID 6761 //
      GIM_CheckFeatures, GIMT_Encode2(GIFBS_LDSRequiresM0Init),
      GIM_CheckMemorySizeEqualToLLT, /*MI*/0, /*MMO*/0, /*OpIdx*/0,
      GIM_CheckMemoryAddressSpace, /*MI*/0, /*MMO*/0, /*NumAddrSpace*/1, /*AddrSpace*/3,
      GIM_CheckMemoryAlignment, /*MI*/0, /*MMO*/0, /*MinAlign*/8,
      GIM_CheckAtomicOrdering, /*MI*/0, /*Order*/(uint8_t)AtomicOrdering::NotAtomic,
      GIM_CheckPointerToAny, /*MI*/0, /*Op*/1, /*SizeInBits*/0,
      GIM_CheckComplexPattern, /*MI*/0, /*Op*/1, /*Renderer*/GIMT_Encode2(0), GIMT_Encode2(GICP_gi_ds_1addr_1offset),
      // (AMDGPUst_glue v4bf16:{ *:[v4bf16] }:$value, (DS1Addr1Offset:{ *:[iPTR] } i32:{ *:[i32] }:$ptr, i32:{ *:[i32] }:$offset))<<P:Predicate_unindexedstore_glue>><<P:Predicate_store_glue>><<P:Predicate_store_local_m0>><<P:Predicate_store_align8_local_m0>>  =>  (DS_WRITE_B64 ?:{ *:[i32] }:$ptr, anonymous_15036:{ *:[v4bf16] }:$value, offset:{ *:[i32] }:$offset, 0:{ *:[i1] })
      GIR_BuildMI, /*InsnID*/0, /*Opcode*/GIMT_Encode2(AMDGPU::DS_WRITE_B64),
      GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/0, // ptr
      GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/0, // value
      GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/1, // offset
      GIR_AddImm8, /*InsnID*/0, /*Imm*/0,
      GIR_MergeMemOperands, /*InsnID*/0, /*NumInsns*/1, /*MergeInsnID's*/0,
      GIR_ConstrainSelectedInstOperands, /*InsnID*/0,
      GIR_EraseFromParent, /*InsnID*/0,
      // GIR_Coverage, 6761,
      GIR_Done,
    // Label 2264: @148835
    GIM_Try, /*On fail goto*//*Label 2265*/ GIMT_Encode4(148900), // Rule ID 6765 //
      GIM_CheckFeatures, GIMT_Encode2(GIFBS_LDSRequiresM0Init),
      GIM_CheckMemorySizeEqualToLLT, /*MI*/0, /*MMO*/0, /*OpIdx*/0,
      GIM_CheckMemoryAddressSpace, /*MI*/0, /*MMO*/0, /*NumAddrSpace*/1, /*AddrSpace*/3,
      GIM_CheckMemoryAlignment, /*MI*/0, /*MMO*/0, /*MinAlign*/8,
      GIM_CheckAtomicOrdering, /*MI*/0, /*Order*/(uint8_t)AtomicOrdering::NotAtomic,
      GIM_CheckPointerToAny, /*MI*/0, /*Op*/1, /*SizeInBits*/0,
      GIM_CheckComplexPattern, /*MI*/0, /*Op*/1, /*Renderer*/GIMT_Encode2(0), GIMT_Encode2(GICP_gi_ds_1addr_1offset),
      // (AMDGPUst_glue v4i16:{ *:[v4i16] }:$value, (DS1Addr1Offset:{ *:[iPTR] } i32:{ *:[i32] }:$ptr, i32:{ *:[i32] }:$offset))<<P:Predicate_unindexedstore_glue>><<P:Predicate_store_glue>><<P:Predicate_store_local_m0>><<P:Predicate_store_align8_local_m0>>  =>  (DS_WRITE_B64 ?:{ *:[i32] }:$ptr, anonymous_15036:{ *:[v4i16] }:$value, offset:{ *:[i32] }:$offset, 0:{ *:[i1] })
      GIR_BuildMI, /*InsnID*/0, /*Opcode*/GIMT_Encode2(AMDGPU::DS_WRITE_B64),
      GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/0, // ptr
      GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/0, // value
      GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/1, // offset
      GIR_AddImm8, /*InsnID*/0, /*Imm*/0,
      GIR_MergeMemOperands, /*InsnID*/0, /*NumInsns*/1, /*MergeInsnID's*/0,
      GIR_ConstrainSelectedInstOperands, /*InsnID*/0,
      GIR_EraseFromParent, /*InsnID*/0,
      // GIR_Coverage, 6765,
      GIR_Done,
    // Label 2265: @148900
    GIM_Try, /*On fail goto*//*Label 2266*/ GIMT_Encode4(148966), // Rule ID 6834 //
      GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasUnalignedAccessMode_NotLDSRequiresM0Init),
      GIM_CheckMemoryAddressSpace, /*MI*/0, /*MMO*/0, /*NumAddrSpace*/1, /*AddrSpace*/3,
      GIM_CheckMemoryAddressSpace, /*MI*/0, /*MMO*/0, /*NumAddrSpace*/1, /*AddrSpace*/3,
      GIM_CheckAtomicOrdering, /*MI*/0, /*Order*/(uint8_t)AtomicOrdering::NotAtomic,
      GIM_CheckPointerToAny, /*MI*/0, /*Op*/1, /*SizeInBits*/0,
      GIM_CheckCxxInsnPredicate, /*MI*/0, /*FnId*/GIMT_Encode2(GICXXPred_MI_Predicate_store_align_less_than_4_local),
      GIM_CheckComplexPattern, /*MI*/0, /*Op*/1, /*Renderer*/GIMT_Encode2(0), GIMT_Encode2(GICP_gi_ds_1addr_1offset),
      // (st v4f16:{ *:[v4f16] }:$value, (DS1Addr1Offset:{ *:[iPTR] } i32:{ *:[i32] }:$ptr, i32:{ *:[i32] }:$offset))<<P:Predicate_unindexedstore>><<P:Predicate_store_local>><<P:Predicate_store_align_less_than_4_local>>  =>  (DS_WRITE_B64_gfx9 ?:{ *:[i32] }:$ptr, anonymous_15036:{ *:[v4f16] }:$value, offset:{ *:[i32] }:$offset, 0:{ *:[i1] })
      GIR_BuildMI, /*InsnID*/0, /*Opcode*/GIMT_Encode2(AMDGPU::DS_WRITE_B64_gfx9),
      GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/0, // ptr
      GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/0, // value
      GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/1, // offset
      GIR_AddImm8, /*InsnID*/0, /*Imm*/0,
      GIR_MergeMemOperands, /*InsnID*/0, /*NumInsns*/1, /*MergeInsnID's*/0,
      GIR_ConstrainSelectedInstOperands, /*InsnID*/0,
      GIR_EraseFromParent, /*InsnID*/0,
      // GIR_Coverage, 6834,
      GIR_Done,
    // Label 2266: @148966
    GIM_Try, /*On fail goto*//*Label 2267*/ GIMT_Encode4(149032), // Rule ID 6838 //
      GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasUnalignedAccessMode_NotLDSRequiresM0Init),
      GIM_CheckMemoryAddressSpace, /*MI*/0, /*MMO*/0, /*NumAddrSpace*/1, /*AddrSpace*/3,
      GIM_CheckMemoryAddressSpace, /*MI*/0, /*MMO*/0, /*NumAddrSpace*/1, /*AddrSpace*/3,
      GIM_CheckAtomicOrdering, /*MI*/0, /*Order*/(uint8_t)AtomicOrdering::NotAtomic,
      GIM_CheckPointerToAny, /*MI*/0, /*Op*/1, /*SizeInBits*/0,
      GIM_CheckCxxInsnPredicate, /*MI*/0, /*FnId*/GIMT_Encode2(GICXXPred_MI_Predicate_store_align_less_than_4_local),
      GIM_CheckComplexPattern, /*MI*/0, /*Op*/1, /*Renderer*/GIMT_Encode2(0), GIMT_Encode2(GICP_gi_ds_1addr_1offset),
      // (st v4bf16:{ *:[v4bf16] }:$value, (DS1Addr1Offset:{ *:[iPTR] } i32:{ *:[i32] }:$ptr, i32:{ *:[i32] }:$offset))<<P:Predicate_unindexedstore>><<P:Predicate_store_local>><<P:Predicate_store_align_less_than_4_local>>  =>  (DS_WRITE_B64_gfx9 ?:{ *:[i32] }:$ptr, anonymous_15036:{ *:[v4bf16] }:$value, offset:{ *:[i32] }:$offset, 0:{ *:[i1] })
      GIR_BuildMI, /*InsnID*/0, /*Opcode*/GIMT_Encode2(AMDGPU::DS_WRITE_B64_gfx9),
      GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/0, // ptr
      GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/0, // value
      GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/1, // offset
      GIR_AddImm8, /*InsnID*/0, /*Imm*/0,
      GIR_MergeMemOperands, /*InsnID*/0, /*NumInsns*/1, /*MergeInsnID's*/0,
      GIR_ConstrainSelectedInstOperands, /*InsnID*/0,
      GIR_EraseFromParent, /*InsnID*/0,
      // GIR_Coverage, 6838,
      GIR_Done,
    // Label 2267: @149032
    GIM_Try, /*On fail goto*//*Label 2268*/ GIMT_Encode4(149098), // Rule ID 6842 //
      GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasUnalignedAccessMode_NotLDSRequiresM0Init),
      GIM_CheckMemoryAddressSpace, /*MI*/0, /*MMO*/0, /*NumAddrSpace*/1, /*AddrSpace*/3,
      GIM_CheckMemoryAddressSpace, /*MI*/0, /*MMO*/0, /*NumAddrSpace*/1, /*AddrSpace*/3,
      GIM_CheckAtomicOrdering, /*MI*/0, /*Order*/(uint8_t)AtomicOrdering::NotAtomic,
      GIM_CheckPointerToAny, /*MI*/0, /*Op*/1, /*SizeInBits*/0,
      GIM_CheckCxxInsnPredicate, /*MI*/0, /*FnId*/GIMT_Encode2(GICXXPred_MI_Predicate_store_align_less_than_4_local),
      GIM_CheckComplexPattern, /*MI*/0, /*Op*/1, /*Renderer*/GIMT_Encode2(0), GIMT_Encode2(GICP_gi_ds_1addr_1offset),
      // (st v4i16:{ *:[v4i16] }:$value, (DS1Addr1Offset:{ *:[iPTR] } i32:{ *:[i32] }:$ptr, i32:{ *:[i32] }:$offset))<<P:Predicate_unindexedstore>><<P:Predicate_store_local>><<P:Predicate_store_align_less_than_4_local>>  =>  (DS_WRITE_B64_gfx9 ?:{ *:[i32] }:$ptr, anonymous_15036:{ *:[v4i16] }:$value, offset:{ *:[i32] }:$offset, 0:{ *:[i1] })
      GIR_BuildMI, /*InsnID*/0, /*Opcode*/GIMT_Encode2(AMDGPU::DS_WRITE_B64_gfx9),
      GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/0, // ptr
      GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/0, // value
      GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/1, // offset
      GIR_AddImm8, /*InsnID*/0, /*Imm*/0,
      GIR_MergeMemOperands, /*InsnID*/0, /*NumInsns*/1, /*MergeInsnID's*/0,
      GIR_ConstrainSelectedInstOperands, /*InsnID*/0,
      GIR_EraseFromParent, /*InsnID*/0,
      // GIR_Coverage, 6842,
      GIR_Done,
    // Label 2268: @149098
    GIM_Try, /*On fail goto*//*Label 2269*/ GIMT_Encode4(149159), // Rule ID 6758 //
      GIM_CheckFeatures, GIMT_Encode2(GIFBS_NotLDSRequiresM0Init),
      GIM_CheckMemoryAddressSpace, /*MI*/0, /*MMO*/0, /*NumAddrSpace*/1, /*AddrSpace*/3,
      GIM_CheckMemoryAlignment, /*MI*/0, /*MMO*/0, /*MinAlign*/8,
      GIM_CheckAtomicOrdering, /*MI*/0, /*Order*/(uint8_t)AtomicOrdering::NotAtomic,
      GIM_CheckPointerToAny, /*MI*/0, /*Op*/1, /*SizeInBits*/0,
      GIM_CheckComplexPattern, /*MI*/0, /*Op*/1, /*Renderer*/GIMT_Encode2(0), GIMT_Encode2(GICP_gi_ds_1addr_1offset),
      // (st v4f16:{ *:[v4f16] }:$value, (DS1Addr1Offset:{ *:[iPTR] } i32:{ *:[i32] }:$ptr, i32:{ *:[i32] }:$offset))<<P:Predicate_unindexedstore>><<P:Predicate_store_local>><<P:Predicate_store_align8_local>>  =>  (DS_WRITE_B64_gfx9 ?:{ *:[i32] }:$ptr, anonymous_15036:{ *:[v4f16] }:$value, offset:{ *:[i32] }:$offset, 0:{ *:[i1] })
      GIR_BuildMI, /*InsnID*/0, /*Opcode*/GIMT_Encode2(AMDGPU::DS_WRITE_B64_gfx9),
      GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/0, // ptr
      GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/0, // value
      GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/1, // offset
      GIR_AddImm8, /*InsnID*/0, /*Imm*/0,
      GIR_MergeMemOperands, /*InsnID*/0, /*NumInsns*/1, /*MergeInsnID's*/0,
      GIR_ConstrainSelectedInstOperands, /*InsnID*/0,
      GIR_EraseFromParent, /*InsnID*/0,
      // GIR_Coverage, 6758,
      GIR_Done,
    // Label 2269: @149159
    GIM_Try, /*On fail goto*//*Label 2270*/ GIMT_Encode4(149220), // Rule ID 6762 //
      GIM_CheckFeatures, GIMT_Encode2(GIFBS_NotLDSRequiresM0Init),
      GIM_CheckMemoryAddressSpace, /*MI*/0, /*MMO*/0, /*NumAddrSpace*/1, /*AddrSpace*/3,
      GIM_CheckMemoryAlignment, /*MI*/0, /*MMO*/0, /*MinAlign*/8,
      GIM_CheckAtomicOrdering, /*MI*/0, /*Order*/(uint8_t)AtomicOrdering::NotAtomic,
      GIM_CheckPointerToAny, /*MI*/0, /*Op*/1, /*SizeInBits*/0,
      GIM_CheckComplexPattern, /*MI*/0, /*Op*/1, /*Renderer*/GIMT_Encode2(0), GIMT_Encode2(GICP_gi_ds_1addr_1offset),
      // (st v4bf16:{ *:[v4bf16] }:$value, (DS1Addr1Offset:{ *:[iPTR] } i32:{ *:[i32] }:$ptr, i32:{ *:[i32] }:$offset))<<P:Predicate_unindexedstore>><<P:Predicate_store_local>><<P:Predicate_store_align8_local>>  =>  (DS_WRITE_B64_gfx9 ?:{ *:[i32] }:$ptr, anonymous_15036:{ *:[v4bf16] }:$value, offset:{ *:[i32] }:$offset, 0:{ *:[i1] })
      GIR_BuildMI, /*InsnID*/0, /*Opcode*/GIMT_Encode2(AMDGPU::DS_WRITE_B64_gfx9),
      GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/0, // ptr
      GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/0, // value
      GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/1, // offset
      GIR_AddImm8, /*InsnID*/0, /*Imm*/0,
      GIR_MergeMemOperands, /*InsnID*/0, /*NumInsns*/1, /*MergeInsnID's*/0,
      GIR_ConstrainSelectedInstOperands, /*InsnID*/0,
      GIR_EraseFromParent, /*InsnID*/0,
      // GIR_Coverage, 6762,
      GIR_Done,
    // Label 2270: @149220
    GIM_Try, /*On fail goto*//*Label 2271*/ GIMT_Encode4(149281), // Rule ID 6766 //
      GIM_CheckFeatures, GIMT_Encode2(GIFBS_NotLDSRequiresM0Init),
      GIM_CheckMemoryAddressSpace, /*MI*/0, /*MMO*/0, /*NumAddrSpace*/1, /*AddrSpace*/3,
      GIM_CheckMemoryAlignment, /*MI*/0, /*MMO*/0, /*MinAlign*/8,
      GIM_CheckAtomicOrdering, /*MI*/0, /*Order*/(uint8_t)AtomicOrdering::NotAtomic,
      GIM_CheckPointerToAny, /*MI*/0, /*Op*/1, /*SizeInBits*/0,
      GIM_CheckComplexPattern, /*MI*/0, /*Op*/1, /*Renderer*/GIMT_Encode2(0), GIMT_Encode2(GICP_gi_ds_1addr_1offset),
      // (st v4i16:{ *:[v4i16] }:$value, (DS1Addr1Offset:{ *:[iPTR] } i32:{ *:[i32] }:$ptr, i32:{ *:[i32] }:$offset))<<P:Predicate_unindexedstore>><<P:Predicate_store_local>><<P:Predicate_store_align8_local>>  =>  (DS_WRITE_B64_gfx9 ?:{ *:[i32] }:$ptr, anonymous_15036:{ *:[v4i16] }:$value, offset:{ *:[i32] }:$offset, 0:{ *:[i1] })
      GIR_BuildMI, /*InsnID*/0, /*Opcode*/GIMT_Encode2(AMDGPU::DS_WRITE_B64_gfx9),
      GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/0, // ptr
      GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/0, // value
      GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/1, // offset
      GIR_AddImm8, /*InsnID*/0, /*Imm*/0,
      GIR_MergeMemOperands, /*InsnID*/0, /*NumInsns*/1, /*MergeInsnID's*/0,
      GIR_ConstrainSelectedInstOperands, /*InsnID*/0,
      GIR_EraseFromParent, /*InsnID*/0,
      // GIR_Coverage, 6766,
      GIR_Done,
    // Label 2271: @149281
    GIM_Try, /*On fail goto*//*Label 2272*/ GIMT_Encode4(149343), // Rule ID 3511 //
      GIM_CheckFeatures, GIMT_Encode2(GIFBS_EnableFlatScratch_HasFlatScratchInsts_HasFlatScratchSVSMode),
      GIM_CheckMemoryAddressSpace, /*MI*/0, /*MMO*/0, /*NumAddrSpace*/1, /*AddrSpace*/5,
      GIM_CheckAtomicOrdering, /*MI*/0, /*Order*/(uint8_t)AtomicOrdering::NotAtomic,
      GIM_CheckPointerToAny, /*MI*/0, /*Op*/1, /*SizeInBits*/0,
      GIM_CheckComplexPattern, /*MI*/0, /*Op*/1, /*Renderer*/GIMT_Encode2(0), GIMT_Encode2(GICP_gi_flat_scratch_svaddr),
      // (st v4f16:{ *:[v4f16] }:$data, (ScratchSVAddr:{ *:[iPTR] } VGPR_32:{ *:[i32] }:$vaddr, SGPR_32:{ *:[i32] }:$saddr, i32:{ *:[i32] }:$offset))<<P:Predicate_unindexedstore>><<P:Predicate_store_private>>  =>  (SCRATCH_STORE_DWORDX2_SVS anonymous_15036:{ *:[v4f16] }:$data, ?:{ *:[i32] }:$vaddr, ?:{ *:[i32] }:$saddr, ?:{ *:[i32] }:$offset)
      GIR_BuildMI, /*InsnID*/0, /*Opcode*/GIMT_Encode2(AMDGPU::SCRATCH_STORE_DWORDX2_SVS),
      GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/0, // data
      GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/0, // vaddr
      GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/1, // saddr
      GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/2, // offset
      GIR_AddImm8, /*InsnID*/0, /*Imm*/0,
      GIR_MergeMemOperands, /*InsnID*/0, /*NumInsns*/1, /*MergeInsnID's*/0,
      GIR_ConstrainSelectedInstOperands, /*InsnID*/0,
      GIR_EraseFromParent, /*InsnID*/0,
      // GIR_Coverage, 3511,
      GIR_Done,
    // Label 2272: @149343
    GIM_Try, /*On fail goto*//*Label 2273*/ GIMT_Encode4(149405), // Rule ID 3517 //
      GIM_CheckFeatures, GIMT_Encode2(GIFBS_EnableFlatScratch_HasFlatScratchInsts_HasFlatScratchSVSMode),
      GIM_CheckMemoryAddressSpace, /*MI*/0, /*MMO*/0, /*NumAddrSpace*/1, /*AddrSpace*/5,
      GIM_CheckAtomicOrdering, /*MI*/0, /*Order*/(uint8_t)AtomicOrdering::NotAtomic,
      GIM_CheckPointerToAny, /*MI*/0, /*Op*/1, /*SizeInBits*/0,
      GIM_CheckComplexPattern, /*MI*/0, /*Op*/1, /*Renderer*/GIMT_Encode2(0), GIMT_Encode2(GICP_gi_flat_scratch_svaddr),
      // (st v4bf16:{ *:[v4bf16] }:$data, (ScratchSVAddr:{ *:[iPTR] } VGPR_32:{ *:[i32] }:$vaddr, SGPR_32:{ *:[i32] }:$saddr, i32:{ *:[i32] }:$offset))<<P:Predicate_unindexedstore>><<P:Predicate_store_private>>  =>  (SCRATCH_STORE_DWORDX2_SVS anonymous_15036:{ *:[v4bf16] }:$data, ?:{ *:[i32] }:$vaddr, ?:{ *:[i32] }:$saddr, ?:{ *:[i32] }:$offset)
      GIR_BuildMI, /*InsnID*/0, /*Opcode*/GIMT_Encode2(AMDGPU::SCRATCH_STORE_DWORDX2_SVS),
      GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/0, // data
      GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/0, // vaddr
      GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/1, // saddr
      GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/2, // offset
      GIR_AddImm8, /*InsnID*/0, /*Imm*/0,
      GIR_MergeMemOperands, /*InsnID*/0, /*NumInsns*/1, /*MergeInsnID's*/0,
      GIR_ConstrainSelectedInstOperands, /*InsnID*/0,
      GIR_EraseFromParent, /*InsnID*/0,
      // GIR_Coverage, 3517,
      GIR_Done,
    // Label 2273: @149405
    GIM_Try, /*On fail goto*//*Label 2274*/ GIMT_Encode4(149467), // Rule ID 3523 //
      GIM_CheckFeatures, GIMT_Encode2(GIFBS_EnableFlatScratch_HasFlatScratchInsts_HasFlatScratchSVSMode),
      GIM_CheckMemoryAddressSpace, /*MI*/0, /*MMO*/0, /*NumAddrSpace*/1, /*AddrSpace*/5,
      GIM_CheckAtomicOrdering, /*MI*/0, /*Order*/(uint8_t)AtomicOrdering::NotAtomic,
      GIM_CheckPointerToAny, /*MI*/0, /*Op*/1, /*SizeInBits*/0,
      GIM_CheckComplexPattern, /*MI*/0, /*Op*/1, /*Renderer*/GIMT_Encode2(0), GIMT_Encode2(GICP_gi_flat_scratch_svaddr),
      // (st v4i16:{ *:[v4i16] }:$data, (ScratchSVAddr:{ *:[iPTR] } VGPR_32:{ *:[i32] }:$vaddr, SGPR_32:{ *:[i32] }:$saddr, i32:{ *:[i32] }:$offset))<<P:Predicate_unindexedstore>><<P:Predicate_store_private>>  =>  (SCRATCH_STORE_DWORDX2_SVS anonymous_15036:{ *:[v4i16] }:$data, ?:{ *:[i32] }:$vaddr, ?:{ *:[i32] }:$saddr, ?:{ *:[i32] }:$offset)
      GIR_BuildMI, /*InsnID*/0, /*Opcode*/GIMT_Encode2(AMDGPU::SCRATCH_STORE_DWORDX2_SVS),
      GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/0, // data
      GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/0, // vaddr
      GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/1, // saddr
      GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/2, // offset
      GIR_AddImm8, /*InsnID*/0, /*Imm*/0,
      GIR_MergeMemOperands, /*InsnID*/0, /*NumInsns*/1, /*MergeInsnID's*/0,
      GIR_ConstrainSelectedInstOperands, /*InsnID*/0,
      GIR_EraseFromParent, /*InsnID*/0,
      // GIR_Coverage, 3523,
      GIR_Done,
    // Label 2274: @149467
    GIM_Try, /*On fail goto*//*Label 2275*/ GIMT_Encode4(149524), // Rule ID 3510 //
      GIM_CheckFeatures, GIMT_Encode2(GIFBS_EnableFlatScratch_HasFlatScratchInsts),
      GIM_CheckMemoryAddressSpace, /*MI*/0, /*MMO*/0, /*NumAddrSpace*/1, /*AddrSpace*/5,
      GIM_CheckAtomicOrdering, /*MI*/0, /*Order*/(uint8_t)AtomicOrdering::NotAtomic,
      GIM_CheckPointerToAny, /*MI*/0, /*Op*/1, /*SizeInBits*/0,
      GIM_CheckComplexPattern, /*MI*/0, /*Op*/1, /*Renderer*/GIMT_Encode2(0), GIMT_Encode2(GICP_gi_flat_scratch_saddr),
      // (st v4f16:{ *:[v4f16] }:$data, (ScratchSAddr:{ *:[iPTR] } SGPR_32:{ *:[i32] }:$saddr, i32:{ *:[i32] }:$offset))<<P:Predicate_unindexedstore>><<P:Predicate_store_private>>  =>  (SCRATCH_STORE_DWORDX2_SADDR anonymous_15036:{ *:[v4f16] }:$data, ?:{ *:[i32] }:$saddr, ?:{ *:[i32] }:$offset)
      GIR_BuildMI, /*InsnID*/0, /*Opcode*/GIMT_Encode2(AMDGPU::SCRATCH_STORE_DWORDX2_SADDR),
      GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/0, // data
      GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/0, // saddr
      GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/1, // offset
      GIR_AddImm8, /*InsnID*/0, /*Imm*/0,
      GIR_MergeMemOperands, /*InsnID*/0, /*NumInsns*/1, /*MergeInsnID's*/0,
      GIR_ConstrainSelectedInstOperands, /*InsnID*/0,
      GIR_EraseFromParent, /*InsnID*/0,
      // GIR_Coverage, 3510,
      GIR_Done,
    // Label 2275: @149524
    GIM_Try, /*On fail goto*//*Label 2276*/ GIMT_Encode4(149581), // Rule ID 3516 //
      GIM_CheckFeatures, GIMT_Encode2(GIFBS_EnableFlatScratch_HasFlatScratchInsts),
      GIM_CheckMemoryAddressSpace, /*MI*/0, /*MMO*/0, /*NumAddrSpace*/1, /*AddrSpace*/5,
      GIM_CheckAtomicOrdering, /*MI*/0, /*Order*/(uint8_t)AtomicOrdering::NotAtomic,
      GIM_CheckPointerToAny, /*MI*/0, /*Op*/1, /*SizeInBits*/0,
      GIM_CheckComplexPattern, /*MI*/0, /*Op*/1, /*Renderer*/GIMT_Encode2(0), GIMT_Encode2(GICP_gi_flat_scratch_saddr),
      // (st v4bf16:{ *:[v4bf16] }:$data, (ScratchSAddr:{ *:[iPTR] } SGPR_32:{ *:[i32] }:$saddr, i32:{ *:[i32] }:$offset))<<P:Predicate_unindexedstore>><<P:Predicate_store_private>>  =>  (SCRATCH_STORE_DWORDX2_SADDR anonymous_15036:{ *:[v4bf16] }:$data, ?:{ *:[i32] }:$saddr, ?:{ *:[i32] }:$offset)
      GIR_BuildMI, /*InsnID*/0, /*Opcode*/GIMT_Encode2(AMDGPU::SCRATCH_STORE_DWORDX2_SADDR),
      GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/0, // data
      GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/0, // saddr
      GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/1, // offset
      GIR_AddImm8, /*InsnID*/0, /*Imm*/0,
      GIR_MergeMemOperands, /*InsnID*/0, /*NumInsns*/1, /*MergeInsnID's*/0,
      GIR_ConstrainSelectedInstOperands, /*InsnID*/0,
      GIR_EraseFromParent, /*InsnID*/0,
      // GIR_Coverage, 3516,
      GIR_Done,
    // Label 2276: @149581
    GIM_Try, /*On fail goto*//*Label 2277*/ GIMT_Encode4(149638), // Rule ID 3522 //
      GIM_CheckFeatures, GIMT_Encode2(GIFBS_EnableFlatScratch_HasFlatScratchInsts),
      GIM_CheckMemoryAddressSpace, /*MI*/0, /*MMO*/0, /*NumAddrSpace*/1, /*AddrSpace*/5,
      GIM_CheckAtomicOrdering, /*MI*/0, /*Order*/(uint8_t)AtomicOrdering::NotAtomic,
      GIM_CheckPointerToAny, /*MI*/0, /*Op*/1, /*SizeInBits*/0,
      GIM_CheckComplexPattern, /*MI*/0, /*Op*/1, /*Renderer*/GIMT_Encode2(0), GIMT_Encode2(GICP_gi_flat_scratch_saddr),
      // (st v4i16:{ *:[v4i16] }:$data, (ScratchSAddr:{ *:[iPTR] } SGPR_32:{ *:[i32] }:$saddr, i32:{ *:[i32] }:$offset))<<P:Predicate_unindexedstore>><<P:Predicate_store_private>>  =>  (SCRATCH_STORE_DWORDX2_SADDR anonymous_15036:{ *:[v4i16] }:$data, ?:{ *:[i32] }:$saddr, ?:{ *:[i32] }:$offset)
      GIR_BuildMI, /*InsnID*/0, /*Opcode*/GIMT_Encode2(AMDGPU::SCRATCH_STORE_DWORDX2_SADDR),
      GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/0, // data
      GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/0, // saddr
      GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/1, // offset
      GIR_AddImm8, /*InsnID*/0, /*Imm*/0,
      GIR_MergeMemOperands, /*InsnID*/0, /*NumInsns*/1, /*MergeInsnID's*/0,
      GIR_ConstrainSelectedInstOperands, /*InsnID*/0,
      GIR_EraseFromParent, /*InsnID*/0,
      // GIR_Coverage, 3522,
      GIR_Done,
    // Label 2277: @149638
    GIM_Try, /*On fail goto*//*Label 2278*/ GIMT_Encode4(149695), // Rule ID 3509 //
      GIM_CheckFeatures, GIMT_Encode2(GIFBS_EnableFlatScratch_HasFlatScratchInsts),
      GIM_CheckMemoryAddressSpace, /*MI*/0, /*MMO*/0, /*NumAddrSpace*/1, /*AddrSpace*/5,
      GIM_CheckAtomicOrdering, /*MI*/0, /*Order*/(uint8_t)AtomicOrdering::NotAtomic,
      GIM_CheckPointerToAny, /*MI*/0, /*Op*/1, /*SizeInBits*/0,
      GIM_CheckComplexPattern, /*MI*/0, /*Op*/1, /*Renderer*/GIMT_Encode2(0), GIMT_Encode2(GICP_gi_flat_scratch_offset),
      // (st v4f16:{ *:[v4f16] }:$data, (ScratchOffset:{ *:[iPTR] } VGPR_32:{ *:[i32] }:$vaddr, i32:{ *:[i32] }:$offset))<<P:Predicate_unindexedstore>><<P:Predicate_store_private>>  =>  (SCRATCH_STORE_DWORDX2 anonymous_15036:{ *:[v4f16] }:$data, ?:{ *:[i32] }:$vaddr, ?:{ *:[i32] }:$offset)
      GIR_BuildMI, /*InsnID*/0, /*Opcode*/GIMT_Encode2(AMDGPU::SCRATCH_STORE_DWORDX2),
      GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/0, // data
      GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/0, // vaddr
      GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/1, // offset
      GIR_AddImm8, /*InsnID*/0, /*Imm*/0,
      GIR_MergeMemOperands, /*InsnID*/0, /*NumInsns*/1, /*MergeInsnID's*/0,
      GIR_ConstrainSelectedInstOperands, /*InsnID*/0,
      GIR_EraseFromParent, /*InsnID*/0,
      // GIR_Coverage, 3509,
      GIR_Done,
    // Label 2278: @149695
    GIM_Try, /*On fail goto*//*Label 2279*/ GIMT_Encode4(149752), // Rule ID 3515 //
      GIM_CheckFeatures, GIMT_Encode2(GIFBS_EnableFlatScratch_HasFlatScratchInsts),
      GIM_CheckMemoryAddressSpace, /*MI*/0, /*MMO*/0, /*NumAddrSpace*/1, /*AddrSpace*/5,
      GIM_CheckAtomicOrdering, /*MI*/0, /*Order*/(uint8_t)AtomicOrdering::NotAtomic,
      GIM_CheckPointerToAny, /*MI*/0, /*Op*/1, /*SizeInBits*/0,
      GIM_CheckComplexPattern, /*MI*/0, /*Op*/1, /*Renderer*/GIMT_Encode2(0), GIMT_Encode2(GICP_gi_flat_scratch_offset),
      // (st v4bf16:{ *:[v4bf16] }:$data, (ScratchOffset:{ *:[iPTR] } VGPR_32:{ *:[i32] }:$vaddr, i32:{ *:[i32] }:$offset))<<P:Predicate_unindexedstore>><<P:Predicate_store_private>>  =>  (SCRATCH_STORE_DWORDX2 anonymous_15036:{ *:[v4bf16] }:$data, ?:{ *:[i32] }:$vaddr, ?:{ *:[i32] }:$offset)
      GIR_BuildMI, /*InsnID*/0, /*Opcode*/GIMT_Encode2(AMDGPU::SCRATCH_STORE_DWORDX2),
      GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/0, // data
      GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/0, // vaddr
      GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/1, // offset
      GIR_AddImm8, /*InsnID*/0, /*Imm*/0,
      GIR_MergeMemOperands, /*InsnID*/0, /*NumInsns*/1, /*MergeInsnID's*/0,
      GIR_ConstrainSelectedInstOperands, /*InsnID*/0,
      GIR_EraseFromParent, /*InsnID*/0,
      // GIR_Coverage, 3515,
      GIR_Done,
    // Label 2279: @149752
    GIM_Try, /*On fail goto*//*Label 2280*/ GIMT_Encode4(149809), // Rule ID 3521 //
      GIM_CheckFeatures, GIMT_Encode2(GIFBS_EnableFlatScratch_HasFlatScratchInsts),
      GIM_CheckMemoryAddressSpace, /*MI*/0, /*MMO*/0, /*NumAddrSpace*/1, /*AddrSpace*/5,
      GIM_CheckAtomicOrdering, /*MI*/0, /*Order*/(uint8_t)AtomicOrdering::NotAtomic,
      GIM_CheckPointerToAny, /*MI*/0, /*Op*/1, /*SizeInBits*/0,
      GIM_CheckComplexPattern, /*MI*/0, /*Op*/1, /*Renderer*/GIMT_Encode2(0), GIMT_Encode2(GICP_gi_flat_scratch_offset),
      // (st v4i16:{ *:[v4i16] }:$data, (ScratchOffset:{ *:[iPTR] } VGPR_32:{ *:[i32] }:$vaddr, i32:{ *:[i32] }:$offset))<<P:Predicate_unindexedstore>><<P:Predicate_store_private>>  =>  (SCRATCH_STORE_DWORDX2 anonymous_15036:{ *:[v4i16] }:$data, ?:{ *:[i32] }:$vaddr, ?:{ *:[i32] }:$offset)
      GIR_BuildMI, /*InsnID*/0, /*Opcode*/GIMT_Encode2(AMDGPU::SCRATCH_STORE_DWORDX2),
      GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/0, // data
      GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/0, // vaddr
      GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/1, // offset
      GIR_AddImm8, /*InsnID*/0, /*Imm*/0,
      GIR_MergeMemOperands, /*InsnID*/0, /*NumInsns*/1, /*MergeInsnID's*/0,
      GIR_ConstrainSelectedInstOperands, /*InsnID*/0,
      GIR_EraseFromParent, /*InsnID*/0,
      // GIR_Coverage, 3521,
      GIR_Done,
    // Label 2280: @149809
    GIM_Try, /*On fail goto*//*Label 2281*/ GIMT_Encode4(149879), // Rule ID 3854 //
      GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasUnrestrictedSOffset),
      GIM_CheckMemoryAddressSpace, /*MI*/0, /*MMO*/0, /*NumAddrSpace*/1, /*AddrSpace*/1,
      GIM_CheckAtomicOrdering, /*MI*/0, /*Order*/(uint8_t)AtomicOrdering::NotAtomic,
      GIM_CheckPointerToAny, /*MI*/0, /*Op*/1, /*SizeInBits*/0,
      GIM_CheckComplexPattern, /*MI*/0, /*Op*/1, /*Renderer*/GIMT_Encode2(0), GIMT_Encode2(GICP_gi_mubuf_addr64),
      // (st v4f16:{ *:[v4f16] }:$vdata, (MUBUFAddr64:{ *:[iPTR] } v4i32:{ *:[v4i32] }:$srsrc, i64:{ *:[i64] }:$vaddr, i32:{ *:[i32] }:$soffset, i32:{ *:[i32] }:$offset))<<P:Predicate_unindexedstore>><<P:Predicate_store_global>>  =>  (BUFFER_STORE_DWORDX2_ADDR64 v4f16:{ *:[v4f16] }:$vdata, i64:{ *:[i64] }:$vaddr, v4i32:{ *:[v4i32] }:$srsrc, i32:{ *:[i32] }:$soffset, i32:{ *:[i32] }:$offset)
      GIR_BuildMI, /*InsnID*/0, /*Opcode*/GIMT_Encode2(AMDGPU::BUFFER_STORE_DWORDX2_ADDR64),
      GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/0, // vdata
      GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/1, // vaddr
      GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/0, // srsrc
      GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/2, // soffset
      GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/3, // offset
      GIR_AddImm8, /*InsnID*/0, /*Imm*/0,
      GIR_AddImm8, /*InsnID*/0, /*Imm*/0,
      GIR_MergeMemOperands, /*InsnID*/0, /*NumInsns*/1, /*MergeInsnID's*/0,
      GIR_ConstrainSelectedInstOperands, /*InsnID*/0,
      GIR_EraseFromParent, /*InsnID*/0,
      // GIR_Coverage, 3854,
      GIR_Done,
    // Label 2281: @149879
    GIM_Try, /*On fail goto*//*Label 2282*/ GIMT_Encode4(149946), // Rule ID 3856 //
      GIM_CheckMemoryAddressSpace, /*MI*/0, /*MMO*/0, /*NumAddrSpace*/1, /*AddrSpace*/1,
      GIM_CheckAtomicOrdering, /*MI*/0, /*Order*/(uint8_t)AtomicOrdering::NotAtomic,
      GIM_CheckPointerToAny, /*MI*/0, /*Op*/1, /*SizeInBits*/0,
      GIM_CheckComplexPattern, /*MI*/0, /*Op*/1, /*Renderer*/GIMT_Encode2(0), GIMT_Encode2(GICP_gi_mubuf_addr64),
      // (st v4f16:{ *:[v4f16] }:$vdata, (MUBUFAddr64:{ *:[iPTR] } v4i32:{ *:[v4i32] }:$srsrc, i64:{ *:[i64] }:$vaddr, i32:{ *:[i32] }:$soffset, i32:{ *:[i32] }:$offset))<<P:Predicate_unindexedstore>><<P:Predicate_store_global>>  =>  (BUFFER_STORE_DWORDX2_VBUFFER_ADDR64 v4f16:{ *:[v4f16] }:$vdata, i64:{ *:[i64] }:$vaddr, v4i32:{ *:[v4i32] }:$srsrc, i32:{ *:[i32] }:$soffset, i32:{ *:[i32] }:$offset)
      GIR_BuildMI, /*InsnID*/0, /*Opcode*/GIMT_Encode2(AMDGPU::BUFFER_STORE_DWORDX2_VBUFFER_ADDR64),
      GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/0, // vdata
      GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/1, // vaddr
      GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/0, // srsrc
      GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/2, // soffset
      GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/3, // offset
      GIR_AddImm8, /*InsnID*/0, /*Imm*/0,
      GIR_AddImm8, /*InsnID*/0, /*Imm*/0,
      GIR_MergeMemOperands, /*InsnID*/0, /*NumInsns*/1, /*MergeInsnID's*/0,
      GIR_ConstrainSelectedInstOperands, /*InsnID*/0,
      GIR_EraseFromParent, /*InsnID*/0,
      // GIR_Coverage, 3856,
      GIR_Done,
    // Label 2282: @149946
    GIM_Try, /*On fail goto*//*Label 2283*/ GIMT_Encode4(150016), // Rule ID 3858 //
      GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasUnrestrictedSOffset),
      GIM_CheckMemoryAddressSpace, /*MI*/0, /*MMO*/0, /*NumAddrSpace*/1, /*AddrSpace*/1,
      GIM_CheckAtomicOrdering, /*MI*/0, /*Order*/(uint8_t)AtomicOrdering::NotAtomic,
      GIM_CheckPointerToAny, /*MI*/0, /*Op*/1, /*SizeInBits*/0,
      GIM_CheckComplexPattern, /*MI*/0, /*Op*/1, /*Renderer*/GIMT_Encode2(0), GIMT_Encode2(GICP_gi_mubuf_addr64),
      // (st v4bf16:{ *:[v4bf16] }:$vdata, (MUBUFAddr64:{ *:[iPTR] } v4i32:{ *:[v4i32] }:$srsrc, i64:{ *:[i64] }:$vaddr, i32:{ *:[i32] }:$soffset, i32:{ *:[i32] }:$offset))<<P:Predicate_unindexedstore>><<P:Predicate_store_global>>  =>  (BUFFER_STORE_DWORDX2_ADDR64 v4bf16:{ *:[v4bf16] }:$vdata, i64:{ *:[i64] }:$vaddr, v4i32:{ *:[v4i32] }:$srsrc, i32:{ *:[i32] }:$soffset, i32:{ *:[i32] }:$offset)
      GIR_BuildMI, /*InsnID*/0, /*Opcode*/GIMT_Encode2(AMDGPU::BUFFER_STORE_DWORDX2_ADDR64),
      GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/0, // vdata
      GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/1, // vaddr
      GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/0, // srsrc
      GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/2, // soffset
      GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/3, // offset
      GIR_AddImm8, /*InsnID*/0, /*Imm*/0,
      GIR_AddImm8, /*InsnID*/0, /*Imm*/0,
      GIR_MergeMemOperands, /*InsnID*/0, /*NumInsns*/1, /*MergeInsnID's*/0,
      GIR_ConstrainSelectedInstOperands, /*InsnID*/0,
      GIR_EraseFromParent, /*InsnID*/0,
      // GIR_Coverage, 3858,
      GIR_Done,
    // Label 2283: @150016
    GIM_Try, /*On fail goto*//*Label 2284*/ GIMT_Encode4(150083), // Rule ID 3860 //
      GIM_CheckMemoryAddressSpace, /*MI*/0, /*MMO*/0, /*NumAddrSpace*/1, /*AddrSpace*/1,
      GIM_CheckAtomicOrdering, /*MI*/0, /*Order*/(uint8_t)AtomicOrdering::NotAtomic,
      GIM_CheckPointerToAny, /*MI*/0, /*Op*/1, /*SizeInBits*/0,
      GIM_CheckComplexPattern, /*MI*/0, /*Op*/1, /*Renderer*/GIMT_Encode2(0), GIMT_Encode2(GICP_gi_mubuf_addr64),
      // (st v4bf16:{ *:[v4bf16] }:$vdata, (MUBUFAddr64:{ *:[iPTR] } v4i32:{ *:[v4i32] }:$srsrc, i64:{ *:[i64] }:$vaddr, i32:{ *:[i32] }:$soffset, i32:{ *:[i32] }:$offset))<<P:Predicate_unindexedstore>><<P:Predicate_store_global>>  =>  (BUFFER_STORE_DWORDX2_VBUFFER_ADDR64 v4bf16:{ *:[v4bf16] }:$vdata, i64:{ *:[i64] }:$vaddr, v4i32:{ *:[v4i32] }:$srsrc, i32:{ *:[i32] }:$soffset, i32:{ *:[i32] }:$offset)
      GIR_BuildMI, /*InsnID*/0, /*Opcode*/GIMT_Encode2(AMDGPU::BUFFER_STORE_DWORDX2_VBUFFER_ADDR64),
      GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/0, // vdata
      GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/1, // vaddr
      GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/0, // srsrc
      GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/2, // soffset
      GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/3, // offset
      GIR_AddImm8, /*InsnID*/0, /*Imm*/0,
      GIR_AddImm8, /*InsnID*/0, /*Imm*/0,
      GIR_MergeMemOperands, /*InsnID*/0, /*NumInsns*/1, /*MergeInsnID's*/0,
      GIR_ConstrainSelectedInstOperands, /*InsnID*/0,
      GIR_EraseFromParent, /*InsnID*/0,
      // GIR_Coverage, 3860,
      GIR_Done,
    // Label 2284: @150083
    GIM_Try, /*On fail goto*//*Label 2285*/ GIMT_Encode4(150153), // Rule ID 3862 //
      GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasUnrestrictedSOffset),
      GIM_CheckMemoryAddressSpace, /*MI*/0, /*MMO*/0, /*NumAddrSpace*/1, /*AddrSpace*/1,
      GIM_CheckAtomicOrdering, /*MI*/0, /*Order*/(uint8_t)AtomicOrdering::NotAtomic,
      GIM_CheckPointerToAny, /*MI*/0, /*Op*/1, /*SizeInBits*/0,
      GIM_CheckComplexPattern, /*MI*/0, /*Op*/1, /*Renderer*/GIMT_Encode2(0), GIMT_Encode2(GICP_gi_mubuf_addr64),
      // (st v4i16:{ *:[v4i16] }:$vdata, (MUBUFAddr64:{ *:[iPTR] } v4i32:{ *:[v4i32] }:$srsrc, i64:{ *:[i64] }:$vaddr, i32:{ *:[i32] }:$soffset, i32:{ *:[i32] }:$offset))<<P:Predicate_unindexedstore>><<P:Predicate_store_global>>  =>  (BUFFER_STORE_DWORDX2_ADDR64 v4i16:{ *:[v4i16] }:$vdata, i64:{ *:[i64] }:$vaddr, v4i32:{ *:[v4i32] }:$srsrc, i32:{ *:[i32] }:$soffset, i32:{ *:[i32] }:$offset)
      GIR_BuildMI, /*InsnID*/0, /*Opcode*/GIMT_Encode2(AMDGPU::BUFFER_STORE_DWORDX2_ADDR64),
      GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/0, // vdata
      GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/1, // vaddr
      GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/0, // srsrc
      GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/2, // soffset
      GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/3, // offset
      GIR_AddImm8, /*InsnID*/0, /*Imm*/0,
      GIR_AddImm8, /*InsnID*/0, /*Imm*/0,
      GIR_MergeMemOperands, /*InsnID*/0, /*NumInsns*/1, /*MergeInsnID's*/0,
      GIR_ConstrainSelectedInstOperands, /*InsnID*/0,
      GIR_EraseFromParent, /*InsnID*/0,
      // GIR_Coverage, 3862,
      GIR_Done,
    // Label 2285: @150153
    GIM_Try, /*On fail goto*//*Label 2286*/ GIMT_Encode4(150220), // Rule ID 3864 //
      GIM_CheckMemoryAddressSpace, /*MI*/0, /*MMO*/0, /*NumAddrSpace*/1, /*AddrSpace*/1,
      GIM_CheckAtomicOrdering, /*MI*/0, /*Order*/(uint8_t)AtomicOrdering::NotAtomic,
      GIM_CheckPointerToAny, /*MI*/0, /*Op*/1, /*SizeInBits*/0,
      GIM_CheckComplexPattern, /*MI*/0, /*Op*/1, /*Renderer*/GIMT_Encode2(0), GIMT_Encode2(GICP_gi_mubuf_addr64),
      // (st v4i16:{ *:[v4i16] }:$vdata, (MUBUFAddr64:{ *:[iPTR] } v4i32:{ *:[v4i32] }:$srsrc, i64:{ *:[i64] }:$vaddr, i32:{ *:[i32] }:$soffset, i32:{ *:[i32] }:$offset))<<P:Predicate_unindexedstore>><<P:Predicate_store_global>>  =>  (BUFFER_STORE_DWORDX2_VBUFFER_ADDR64 v4i16:{ *:[v4i16] }:$vdata, i64:{ *:[i64] }:$vaddr, v4i32:{ *:[v4i32] }:$srsrc, i32:{ *:[i32] }:$soffset, i32:{ *:[i32] }:$offset)
      GIR_BuildMI, /*InsnID*/0, /*Opcode*/GIMT_Encode2(AMDGPU::BUFFER_STORE_DWORDX2_VBUFFER_ADDR64),
      GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/0, // vdata
      GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/1, // vaddr
      GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/0, // srsrc
      GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/2, // soffset
      GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/3, // offset
      GIR_AddImm8, /*InsnID*/0, /*Imm*/0,
      GIR_AddImm8, /*InsnID*/0, /*Imm*/0,
      GIR_MergeMemOperands, /*InsnID*/0, /*NumInsns*/1, /*MergeInsnID's*/0,
      GIR_ConstrainSelectedInstOperands, /*InsnID*/0,
      GIR_EraseFromParent, /*InsnID*/0,
      // GIR_Coverage, 3864,
      GIR_Done,
    // Label 2286: @150220
    GIM_Try, /*On fail goto*//*Label 2287*/ GIMT_Encode4(150344), // Rule ID 6692 //
      GIM_CheckFeatures, GIMT_Encode2(GIFBS_LDSRequiresM0Init_isGFX7Plus),
      GIM_CheckMemorySizeEqualToLLT, /*MI*/0, /*MMO*/0, /*OpIdx*/0,
      GIM_CheckMemoryAddressSpace, /*MI*/0, /*MMO*/0, /*NumAddrSpace*/1, /*AddrSpace*/3,
      GIM_CheckAtomicOrdering, /*MI*/0, /*Order*/(uint8_t)AtomicOrdering::NotAtomic,
      GIM_CheckPointerToAny, /*MI*/0, /*Op*/1, /*SizeInBits*/0,
      GIM_CheckComplexPattern, /*MI*/0, /*Op*/1, /*Renderer*/GIMT_Encode2(0), GIMT_Encode2(GICP_gi_ds_64bit_4byte_aligned),
      // (AMDGPUst_glue v4f16:{ *:[v4f16] }:$value, (DS64Bit4ByteAligned:{ *:[iPTR] } i32:{ *:[i32] }:$ptr, i8:{ *:[i8] }:$offset0, i8:{ *:[i8] }:$offset1))<<P:Predicate_unindexedstore_glue>><<P:Predicate_store_glue>><<P:Predicate_store_local_m0>>  =>  (DS_WRITE2_B32 ?:{ *:[i32] }:$ptr, (EXTRACT_SUBREG:{ *:[i32] } VReg_64:{ *:[v4f16] }:$value, sub0:{ *:[i32] }), (EXTRACT_SUBREG:{ *:[i32] } VReg_64:{ *:[v4f16] }:$value, sub1:{ *:[i32] }), ?:{ *:[i8] }:$offset0, ?:{ *:[i8] }:$offset1, 0:{ *:[i1] })
      GIR_MakeTempReg, /*TempRegID*/0, /*TypeID*/GILLT_s32,
      GIR_MakeTempReg, /*TempRegID*/1, /*TypeID*/GILLT_s32,
      GIR_BuildMI, /*InsnID*/2, /*Opcode*/GIMT_Encode2(TargetOpcode::COPY),
      GIR_AddTempRegister, /*InsnID*/2, /*TempRegID*/1, /*TempRegFlags*/GIMT_Encode2(RegState::Define),
      GIR_CopySubReg, /*NewInsnID*/2, /*OldInsnID*/0, /*OpIdx*/0, /*SubRegIdx*/GIMT_Encode2(11), // value
      GIR_ConstrainOperandRC, /*InsnID*/2, /*Op*/0, GIMT_Encode2(AMDGPU::VGPR_32RegClassID),
      GIR_ConstrainOperandRC, /*InsnID*/2, /*Op*/1, GIMT_Encode2(AMDGPU::VReg_64RegClassID),
      GIR_BuildMI, /*InsnID*/1, /*Opcode*/GIMT_Encode2(TargetOpcode::COPY),
      GIR_AddTempRegister, /*InsnID*/1, /*TempRegID*/0, /*TempRegFlags*/GIMT_Encode2(RegState::Define),
      GIR_CopySubReg, /*NewInsnID*/1, /*OldInsnID*/0, /*OpIdx*/0, /*SubRegIdx*/GIMT_Encode2(3), // value
      GIR_ConstrainOperandRC, /*InsnID*/1, /*Op*/0, GIMT_Encode2(AMDGPU::VGPR_32RegClassID),
      GIR_ConstrainOperandRC, /*InsnID*/1, /*Op*/1, GIMT_Encode2(AMDGPU::VReg_64RegClassID),
      GIR_BuildMI, /*InsnID*/0, /*Opcode*/GIMT_Encode2(AMDGPU::DS_WRITE2_B32),
      GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/0, // ptr
      GIR_AddSimpleTempRegister, /*InsnID*/0, /*TempRegID*/0,
      GIR_AddSimpleTempRegister, /*InsnID*/0, /*TempRegID*/1,
      GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/1, // offset0
      GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/2, // offset1
      GIR_AddImm8, /*InsnID*/0, /*Imm*/0,
      GIR_MergeMemOperands, /*InsnID*/0, /*NumInsns*/1, /*MergeInsnID's*/0,
      GIR_ConstrainSelectedInstOperands, /*InsnID*/0,
      GIR_EraseFromParent, /*InsnID*/0,
      // GIR_Coverage, 6692,
      GIR_Done,
    // Label 2287: @150344
    GIM_Try, /*On fail goto*//*Label 2288*/ GIMT_Encode4(150468), // Rule ID 6696 //
      GIM_CheckFeatures, GIMT_Encode2(GIFBS_LDSRequiresM0Init_isGFX7Plus),
      GIM_CheckMemorySizeEqualToLLT, /*MI*/0, /*MMO*/0, /*OpIdx*/0,
      GIM_CheckMemoryAddressSpace, /*MI*/0, /*MMO*/0, /*NumAddrSpace*/1, /*AddrSpace*/3,
      GIM_CheckAtomicOrdering, /*MI*/0, /*Order*/(uint8_t)AtomicOrdering::NotAtomic,
      GIM_CheckPointerToAny, /*MI*/0, /*Op*/1, /*SizeInBits*/0,
      GIM_CheckComplexPattern, /*MI*/0, /*Op*/1, /*Renderer*/GIMT_Encode2(0), GIMT_Encode2(GICP_gi_ds_64bit_4byte_aligned),
      // (AMDGPUst_glue v4bf16:{ *:[v4bf16] }:$value, (DS64Bit4ByteAligned:{ *:[iPTR] } i32:{ *:[i32] }:$ptr, i8:{ *:[i8] }:$offset0, i8:{ *:[i8] }:$offset1))<<P:Predicate_unindexedstore_glue>><<P:Predicate_store_glue>><<P:Predicate_store_local_m0>>  =>  (DS_WRITE2_B32 ?:{ *:[i32] }:$ptr, (EXTRACT_SUBREG:{ *:[i32] } VReg_64:{ *:[v4bf16] }:$value, sub0:{ *:[i32] }), (EXTRACT_SUBREG:{ *:[i32] } VReg_64:{ *:[v4bf16] }:$value, sub1:{ *:[i32] }), ?:{ *:[i8] }:$offset0, ?:{ *:[i8] }:$offset1, 0:{ *:[i1] })
      GIR_MakeTempReg, /*TempRegID*/0, /*TypeID*/GILLT_s32,
      GIR_MakeTempReg, /*TempRegID*/1, /*TypeID*/GILLT_s32,
      GIR_BuildMI, /*InsnID*/2, /*Opcode*/GIMT_Encode2(TargetOpcode::COPY),
      GIR_AddTempRegister, /*InsnID*/2, /*TempRegID*/1, /*TempRegFlags*/GIMT_Encode2(RegState::Define),
      GIR_CopySubReg, /*NewInsnID*/2, /*OldInsnID*/0, /*OpIdx*/0, /*SubRegIdx*/GIMT_Encode2(11), // value
      GIR_ConstrainOperandRC, /*InsnID*/2, /*Op*/0, GIMT_Encode2(AMDGPU::VGPR_32RegClassID),
      GIR_ConstrainOperandRC, /*InsnID*/2, /*Op*/1, GIMT_Encode2(AMDGPU::VReg_64RegClassID),
      GIR_BuildMI, /*InsnID*/1, /*Opcode*/GIMT_Encode2(TargetOpcode::COPY),
      GIR_AddTempRegister, /*InsnID*/1, /*TempRegID*/0, /*TempRegFlags*/GIMT_Encode2(RegState::Define),
      GIR_CopySubReg, /*NewInsnID*/1, /*OldInsnID*/0, /*OpIdx*/0, /*SubRegIdx*/GIMT_Encode2(3), // value
      GIR_ConstrainOperandRC, /*InsnID*/1, /*Op*/0, GIMT_Encode2(AMDGPU::VGPR_32RegClassID),
      GIR_ConstrainOperandRC, /*InsnID*/1, /*Op*/1, GIMT_Encode2(AMDGPU::VReg_64RegClassID),
      GIR_BuildMI, /*InsnID*/0, /*Opcode*/GIMT_Encode2(AMDGPU::DS_WRITE2_B32),
      GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/0, // ptr
      GIR_AddSimpleTempRegister, /*InsnID*/0, /*TempRegID*/0,
      GIR_AddSimpleTempRegister, /*InsnID*/0, /*TempRegID*/1,
      GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/1, // offset0
      GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/2, // offset1
      GIR_AddImm8, /*InsnID*/0, /*Imm*/0,
      GIR_MergeMemOperands, /*InsnID*/0, /*NumInsns*/1, /*MergeInsnID's*/0,
      GIR_ConstrainSelectedInstOperands, /*InsnID*/0,
      GIR_EraseFromParent, /*InsnID*/0,
      // GIR_Coverage, 6696,
      GIR_Done,
    // Label 2288: @150468
    GIM_Try, /*On fail goto*//*Label 2289*/ GIMT_Encode4(150592), // Rule ID 6700 //
      GIM_CheckFeatures, GIMT_Encode2(GIFBS_LDSRequiresM0Init_isGFX7Plus),
      GIM_CheckMemorySizeEqualToLLT, /*MI*/0, /*MMO*/0, /*OpIdx*/0,
      GIM_CheckMemoryAddressSpace, /*MI*/0, /*MMO*/0, /*NumAddrSpace*/1, /*AddrSpace*/3,
      GIM_CheckAtomicOrdering, /*MI*/0, /*Order*/(uint8_t)AtomicOrdering::NotAtomic,
      GIM_CheckPointerToAny, /*MI*/0, /*Op*/1, /*SizeInBits*/0,
      GIM_CheckComplexPattern, /*MI*/0, /*Op*/1, /*Renderer*/GIMT_Encode2(0), GIMT_Encode2(GICP_gi_ds_64bit_4byte_aligned),
      // (AMDGPUst_glue v4i16:{ *:[v4i16] }:$value, (DS64Bit4ByteAligned:{ *:[iPTR] } i32:{ *:[i32] }:$ptr, i8:{ *:[i8] }:$offset0, i8:{ *:[i8] }:$offset1))<<P:Predicate_unindexedstore_glue>><<P:Predicate_store_glue>><<P:Predicate_store_local_m0>>  =>  (DS_WRITE2_B32 ?:{ *:[i32] }:$ptr, (EXTRACT_SUBREG:{ *:[i32] } VReg_64:{ *:[v4i16] }:$value, sub0:{ *:[i32] }), (EXTRACT_SUBREG:{ *:[i32] } VReg_64:{ *:[v4i16] }:$value, sub1:{ *:[i32] }), ?:{ *:[i8] }:$offset0, ?:{ *:[i8] }:$offset1, 0:{ *:[i1] })
      GIR_MakeTempReg, /*TempRegID*/0, /*TypeID*/GILLT_s32,
      GIR_MakeTempReg, /*TempRegID*/1, /*TypeID*/GILLT_s32,
      GIR_BuildMI, /*InsnID*/2, /*Opcode*/GIMT_Encode2(TargetOpcode::COPY),
      GIR_AddTempRegister, /*InsnID*/2, /*TempRegID*/1, /*TempRegFlags*/GIMT_Encode2(RegState::Define),
      GIR_CopySubReg, /*NewInsnID*/2, /*OldInsnID*/0, /*OpIdx*/0, /*SubRegIdx*/GIMT_Encode2(11), // value
      GIR_ConstrainOperandRC, /*InsnID*/2, /*Op*/0, GIMT_Encode2(AMDGPU::VGPR_32RegClassID),
      GIR_ConstrainOperandRC, /*InsnID*/2, /*Op*/1, GIMT_Encode2(AMDGPU::VReg_64RegClassID),
      GIR_BuildMI, /*InsnID*/1, /*Opcode*/GIMT_Encode2(TargetOpcode::COPY),
      GIR_AddTempRegister, /*InsnID*/1, /*TempRegID*/0, /*TempRegFlags*/GIMT_Encode2(RegState::Define),
      GIR_CopySubReg, /*NewInsnID*/1, /*OldInsnID*/0, /*OpIdx*/0, /*SubRegIdx*/GIMT_Encode2(3), // value
      GIR_ConstrainOperandRC, /*InsnID*/1, /*Op*/0, GIMT_Encode2(AMDGPU::VGPR_32RegClassID),
      GIR_ConstrainOperandRC, /*InsnID*/1, /*Op*/1, GIMT_Encode2(AMDGPU::VReg_64RegClassID),
      GIR_BuildMI, /*InsnID*/0, /*Opcode*/GIMT_Encode2(AMDGPU::DS_WRITE2_B32),
      GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/0, // ptr
      GIR_AddSimpleTempRegister, /*InsnID*/0, /*TempRegID*/0,
      GIR_AddSimpleTempRegister, /*InsnID*/0, /*TempRegID*/1,
      GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/1, // offset0
      GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/2, // offset1
      GIR_AddImm8, /*InsnID*/0, /*Imm*/0,
      GIR_MergeMemOperands, /*InsnID*/0, /*NumInsns*/1, /*MergeInsnID's*/0,
      GIR_ConstrainSelectedInstOperands, /*InsnID*/0,
      GIR_EraseFromParent, /*InsnID*/0,
      // GIR_Coverage, 6700,
      GIR_Done,
    // Label 2289: @150592
    GIM_Try, /*On fail goto*//*Label 2290*/ GIMT_Encode4(150657), // Rule ID 3853 //
      GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasUnrestrictedSOffset),
      GIM_CheckMemoryAddressSpace, /*MI*/0, /*MMO*/0, /*NumAddrSpace*/1, /*AddrSpace*/1,
      GIM_CheckAtomicOrdering, /*MI*/0, /*Order*/(uint8_t)AtomicOrdering::NotAtomic,
      GIM_CheckPointerToAny, /*MI*/0, /*Op*/1, /*SizeInBits*/0,
      GIM_CheckComplexPattern, /*MI*/0, /*Op*/1, /*Renderer*/GIMT_Encode2(0), GIMT_Encode2(GICP_gi_mubuf_offset),
      // (st v4f16:{ *:[v4f16] }:$vdata, (MUBUFOffset:{ *:[iPTR] } v4i32:{ *:[v4i32] }:$srsrc, i32:{ *:[i32] }:$soffset, i32:{ *:[i32] }:$offset))<<P:Predicate_unindexedstore>><<P:Predicate_store_global>>  =>  (BUFFER_STORE_DWORDX2_OFFSET v4f16:{ *:[v4f16] }:$vdata, v4i32:{ *:[v4i32] }:$srsrc, i32:{ *:[i32] }:$soffset, i32:{ *:[i32] }:$offset)
      GIR_BuildMI, /*InsnID*/0, /*Opcode*/GIMT_Encode2(AMDGPU::BUFFER_STORE_DWORDX2_OFFSET),
      GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/0, // vdata
      GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/0, // srsrc
      GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/1, // soffset
      GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/2, // offset
      GIR_AddImm8, /*InsnID*/0, /*Imm*/0,
      GIR_AddImm8, /*InsnID*/0, /*Imm*/0,
      GIR_MergeMemOperands, /*InsnID*/0, /*NumInsns*/1, /*MergeInsnID's*/0,
      GIR_ConstrainSelectedInstOperands, /*InsnID*/0,
      GIR_EraseFromParent, /*InsnID*/0,
      // GIR_Coverage, 3853,
      GIR_Done,
    // Label 2290: @150657
    GIM_Try, /*On fail goto*//*Label 2291*/ GIMT_Encode4(150719), // Rule ID 3855 //
      GIM_CheckMemoryAddressSpace, /*MI*/0, /*MMO*/0, /*NumAddrSpace*/1, /*AddrSpace*/1,
      GIM_CheckAtomicOrdering, /*MI*/0, /*Order*/(uint8_t)AtomicOrdering::NotAtomic,
      GIM_CheckPointerToAny, /*MI*/0, /*Op*/1, /*SizeInBits*/0,
      GIM_CheckComplexPattern, /*MI*/0, /*Op*/1, /*Renderer*/GIMT_Encode2(0), GIMT_Encode2(GICP_gi_mubuf_offset),
      // (st v4f16:{ *:[v4f16] }:$vdata, (MUBUFOffset:{ *:[iPTR] } v4i32:{ *:[v4i32] }:$srsrc, i32:{ *:[i32] }:$soffset, i32:{ *:[i32] }:$offset))<<P:Predicate_unindexedstore>><<P:Predicate_store_global>>  =>  (BUFFER_STORE_DWORDX2_VBUFFER_OFFSET v4f16:{ *:[v4f16] }:$vdata, v4i32:{ *:[v4i32] }:$srsrc, i32:{ *:[i32] }:$soffset, i32:{ *:[i32] }:$offset)
      GIR_BuildMI, /*InsnID*/0, /*Opcode*/GIMT_Encode2(AMDGPU::BUFFER_STORE_DWORDX2_VBUFFER_OFFSET),
      GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/0, // vdata
      GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/0, // srsrc
      GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/1, // soffset
      GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/2, // offset
      GIR_AddImm8, /*InsnID*/0, /*Imm*/0,
      GIR_AddImm8, /*InsnID*/0, /*Imm*/0,
      GIR_MergeMemOperands, /*InsnID*/0, /*NumInsns*/1, /*MergeInsnID's*/0,
      GIR_ConstrainSelectedInstOperands, /*InsnID*/0,
      GIR_EraseFromParent, /*InsnID*/0,
      // GIR_Coverage, 3855,
      GIR_Done,
    // Label 2291: @150719
    GIM_Try, /*On fail goto*//*Label 2292*/ GIMT_Encode4(150784), // Rule ID 3857 //
      GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasUnrestrictedSOffset),
      GIM_CheckMemoryAddressSpace, /*MI*/0, /*MMO*/0, /*NumAddrSpace*/1, /*AddrSpace*/1,
      GIM_CheckAtomicOrdering, /*MI*/0, /*Order*/(uint8_t)AtomicOrdering::NotAtomic,
      GIM_CheckPointerToAny, /*MI*/0, /*Op*/1, /*SizeInBits*/0,
      GIM_CheckComplexPattern, /*MI*/0, /*Op*/1, /*Renderer*/GIMT_Encode2(0), GIMT_Encode2(GICP_gi_mubuf_offset),
      // (st v4bf16:{ *:[v4bf16] }:$vdata, (MUBUFOffset:{ *:[iPTR] } v4i32:{ *:[v4i32] }:$srsrc, i32:{ *:[i32] }:$soffset, i32:{ *:[i32] }:$offset))<<P:Predicate_unindexedstore>><<P:Predicate_store_global>>  =>  (BUFFER_STORE_DWORDX2_OFFSET v4bf16:{ *:[v4bf16] }:$vdata, v4i32:{ *:[v4i32] }:$srsrc, i32:{ *:[i32] }:$soffset, i32:{ *:[i32] }:$offset)
      GIR_BuildMI, /*InsnID*/0, /*Opcode*/GIMT_Encode2(AMDGPU::BUFFER_STORE_DWORDX2_OFFSET),
      GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/0, // vdata
      GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/0, // srsrc
      GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/1, // soffset
      GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/2, // offset
      GIR_AddImm8, /*InsnID*/0, /*Imm*/0,
      GIR_AddImm8, /*InsnID*/0, /*Imm*/0,
      GIR_MergeMemOperands, /*InsnID*/0, /*NumInsns*/1, /*MergeInsnID's*/0,
      GIR_ConstrainSelectedInstOperands, /*InsnID*/0,
      GIR_EraseFromParent, /*InsnID*/0,
      // GIR_Coverage, 3857,
      GIR_Done,
    // Label 2292: @150784
    GIM_Try, /*On fail goto*//*Label 2293*/ GIMT_Encode4(150846), // Rule ID 3859 //
      GIM_CheckMemoryAddressSpace, /*MI*/0, /*MMO*/0, /*NumAddrSpace*/1, /*AddrSpace*/1,
      GIM_CheckAtomicOrdering, /*MI*/0, /*Order*/(uint8_t)AtomicOrdering::NotAtomic,
      GIM_CheckPointerToAny, /*MI*/0, /*Op*/1, /*SizeInBits*/0,
      GIM_CheckComplexPattern, /*MI*/0, /*Op*/1, /*Renderer*/GIMT_Encode2(0), GIMT_Encode2(GICP_gi_mubuf_offset),
      // (st v4bf16:{ *:[v4bf16] }:$vdata, (MUBUFOffset:{ *:[iPTR] } v4i32:{ *:[v4i32] }:$srsrc, i32:{ *:[i32] }:$soffset, i32:{ *:[i32] }:$offset))<<P:Predicate_unindexedstore>><<P:Predicate_store_global>>  =>  (BUFFER_STORE_DWORDX2_VBUFFER_OFFSET v4bf16:{ *:[v4bf16] }:$vdata, v4i32:{ *:[v4i32] }:$srsrc, i32:{ *:[i32] }:$soffset, i32:{ *:[i32] }:$offset)
      GIR_BuildMI, /*InsnID*/0, /*Opcode*/GIMT_Encode2(AMDGPU::BUFFER_STORE_DWORDX2_VBUFFER_OFFSET),
      GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/0, // vdata
      GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/0, // srsrc
      GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/1, // soffset
      GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/2, // offset
      GIR_AddImm8, /*InsnID*/0, /*Imm*/0,
      GIR_AddImm8, /*InsnID*/0, /*Imm*/0,
      GIR_MergeMemOperands, /*InsnID*/0, /*NumInsns*/1, /*MergeInsnID's*/0,
      GIR_ConstrainSelectedInstOperands, /*InsnID*/0,
      GIR_EraseFromParent, /*InsnID*/0,
      // GIR_Coverage, 3859,
      GIR_Done,
    // Label 2293: @150846
    GIM_Try, /*On fail goto*//*Label 2294*/ GIMT_Encode4(150911), // Rule ID 3861 //
      GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasUnrestrictedSOffset),
      GIM_CheckMemoryAddressSpace, /*MI*/0, /*MMO*/0, /*NumAddrSpace*/1, /*AddrSpace*/1,
      GIM_CheckAtomicOrdering, /*MI*/0, /*Order*/(uint8_t)AtomicOrdering::NotAtomic,
      GIM_CheckPointerToAny, /*MI*/0, /*Op*/1, /*SizeInBits*/0,
      GIM_CheckComplexPattern, /*MI*/0, /*Op*/1, /*Renderer*/GIMT_Encode2(0), GIMT_Encode2(GICP_gi_mubuf_offset),
      // (st v4i16:{ *:[v4i16] }:$vdata, (MUBUFOffset:{ *:[iPTR] } v4i32:{ *:[v4i32] }:$srsrc, i32:{ *:[i32] }:$soffset, i32:{ *:[i32] }:$offset))<<P:Predicate_unindexedstore>><<P:Predicate_store_global>>  =>  (BUFFER_STORE_DWORDX2_OFFSET v4i16:{ *:[v4i16] }:$vdata, v4i32:{ *:[v4i32] }:$srsrc, i32:{ *:[i32] }:$soffset, i32:{ *:[i32] }:$offset)
      GIR_BuildMI, /*InsnID*/0, /*Opcode*/GIMT_Encode2(AMDGPU::BUFFER_STORE_DWORDX2_OFFSET),
      GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/0, // vdata
      GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/0, // srsrc
      GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/1, // soffset
      GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/2, // offset
      GIR_AddImm8, /*InsnID*/0, /*Imm*/0,
      GIR_AddImm8, /*InsnID*/0, /*Imm*/0,
      GIR_MergeMemOperands, /*InsnID*/0, /*NumInsns*/1, /*MergeInsnID's*/0,
      GIR_ConstrainSelectedInstOperands, /*InsnID*/0,
      GIR_EraseFromParent, /*InsnID*/0,
      // GIR_Coverage, 3861,
      GIR_Done,
    // Label 2294: @150911
    GIM_Try, /*On fail goto*//*Label 2295*/ GIMT_Encode4(150973), // Rule ID 3863 //
      GIM_CheckMemoryAddressSpace, /*MI*/0, /*MMO*/0, /*NumAddrSpace*/1, /*AddrSpace*/1,
      GIM_CheckAtomicOrdering, /*MI*/0, /*Order*/(uint8_t)AtomicOrdering::NotAtomic,
      GIM_CheckPointerToAny, /*MI*/0, /*Op*/1, /*SizeInBits*/0,
      GIM_CheckComplexPattern, /*MI*/0, /*Op*/1, /*Renderer*/GIMT_Encode2(0), GIMT_Encode2(GICP_gi_mubuf_offset),
      // (st v4i16:{ *:[v4i16] }:$vdata, (MUBUFOffset:{ *:[iPTR] } v4i32:{ *:[v4i32] }:$srsrc, i32:{ *:[i32] }:$soffset, i32:{ *:[i32] }:$offset))<<P:Predicate_unindexedstore>><<P:Predicate_store_global>>  =>  (BUFFER_STORE_DWORDX2_VBUFFER_OFFSET v4i16:{ *:[v4i16] }:$vdata, v4i32:{ *:[v4i32] }:$srsrc, i32:{ *:[i32] }:$soffset, i32:{ *:[i32] }:$offset)
      GIR_BuildMI, /*InsnID*/0, /*Opcode*/GIMT_Encode2(AMDGPU::BUFFER_STORE_DWORDX2_VBUFFER_OFFSET),
      GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/0, // vdata
      GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/0, // srsrc
      GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/1, // soffset
      GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/2, // offset
      GIR_AddImm8, /*InsnID*/0, /*Imm*/0,
      GIR_AddImm8, /*InsnID*/0, /*Imm*/0,
      GIR_MergeMemOperands, /*InsnID*/0, /*NumInsns*/1, /*MergeInsnID's*/0,
      GIR_ConstrainSelectedInstOperands, /*InsnID*/0,
      GIR_EraseFromParent, /*InsnID*/0,
      // GIR_Coverage, 3863,
      GIR_Done,
    // Label 2295: @150973
    GIM_Try, /*On fail goto*//*Label 2296*/ GIMT_Encode4(151093), // Rule ID 6694 //
      GIM_CheckFeatures, GIMT_Encode2(GIFBS_NotLDSRequiresM0Init),
      GIM_CheckMemoryAddressSpace, /*MI*/0, /*MMO*/0, /*NumAddrSpace*/1, /*AddrSpace*/3,
      GIM_CheckAtomicOrdering, /*MI*/0, /*Order*/(uint8_t)AtomicOrdering::NotAtomic,
      GIM_CheckPointerToAny, /*MI*/0, /*Op*/1, /*SizeInBits*/0,
      GIM_CheckComplexPattern, /*MI*/0, /*Op*/1, /*Renderer*/GIMT_Encode2(0), GIMT_Encode2(GICP_gi_ds_64bit_4byte_aligned),
      // (st v4f16:{ *:[v4f16] }:$value, (DS64Bit4ByteAligned:{ *:[iPTR] } i32:{ *:[i32] }:$ptr, i8:{ *:[i8] }:$offset0, i8:{ *:[i8] }:$offset1))<<P:Predicate_unindexedstore>><<P:Predicate_store_local>>  =>  (DS_WRITE2_B32_gfx9 ?:{ *:[i32] }:$ptr, (EXTRACT_SUBREG:{ *:[i32] } VReg_64:{ *:[v4f16] }:$value, sub0:{ *:[i32] }), (EXTRACT_SUBREG:{ *:[i32] } VReg_64:{ *:[v4f16] }:$value, sub1:{ *:[i32] }), ?:{ *:[i8] }:$offset0, ?:{ *:[i8] }:$offset1, 0:{ *:[i1] })
      GIR_MakeTempReg, /*TempRegID*/0, /*TypeID*/GILLT_s32,
      GIR_MakeTempReg, /*TempRegID*/1, /*TypeID*/GILLT_s32,
      GIR_BuildMI, /*InsnID*/2, /*Opcode*/GIMT_Encode2(TargetOpcode::COPY),
      GIR_AddTempRegister, /*InsnID*/2, /*TempRegID*/1, /*TempRegFlags*/GIMT_Encode2(RegState::Define),
      GIR_CopySubReg, /*NewInsnID*/2, /*OldInsnID*/0, /*OpIdx*/0, /*SubRegIdx*/GIMT_Encode2(11), // value
      GIR_ConstrainOperandRC, /*InsnID*/2, /*Op*/0, GIMT_Encode2(AMDGPU::VGPR_32RegClassID),
      GIR_ConstrainOperandRC, /*InsnID*/2, /*Op*/1, GIMT_Encode2(AMDGPU::VReg_64RegClassID),
      GIR_BuildMI, /*InsnID*/1, /*Opcode*/GIMT_Encode2(TargetOpcode::COPY),
      GIR_AddTempRegister, /*InsnID*/1, /*TempRegID*/0, /*TempRegFlags*/GIMT_Encode2(RegState::Define),
      GIR_CopySubReg, /*NewInsnID*/1, /*OldInsnID*/0, /*OpIdx*/0, /*SubRegIdx*/GIMT_Encode2(3), // value
      GIR_ConstrainOperandRC, /*InsnID*/1, /*Op*/0, GIMT_Encode2(AMDGPU::VGPR_32RegClassID),
      GIR_ConstrainOperandRC, /*InsnID*/1, /*Op*/1, GIMT_Encode2(AMDGPU::VReg_64RegClassID),
      GIR_BuildMI, /*InsnID*/0, /*Opcode*/GIMT_Encode2(AMDGPU::DS_WRITE2_B32_gfx9),
      GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/0, // ptr
      GIR_AddSimpleTempRegister, /*InsnID*/0, /*TempRegID*/0,
      GIR_AddSimpleTempRegister, /*InsnID*/0, /*TempRegID*/1,
      GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/1, // offset0
      GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/2, // offset1
      GIR_AddImm8, /*InsnID*/0, /*Imm*/0,
      GIR_MergeMemOperands, /*InsnID*/0, /*NumInsns*/1, /*MergeInsnID's*/0,
      GIR_ConstrainSelectedInstOperands, /*InsnID*/0,
      GIR_EraseFromParent, /*InsnID*/0,
      // GIR_Coverage, 6694,
      GIR_Done,
    // Label 2296: @151093
    GIM_Try, /*On fail goto*//*Label 2297*/ GIMT_Encode4(151213), // Rule ID 6698 //
      GIM_CheckFeatures, GIMT_Encode2(GIFBS_NotLDSRequiresM0Init),
      GIM_CheckMemoryAddressSpace, /*MI*/0, /*MMO*/0, /*NumAddrSpace*/1, /*AddrSpace*/3,
      GIM_CheckAtomicOrdering, /*MI*/0, /*Order*/(uint8_t)AtomicOrdering::NotAtomic,
      GIM_CheckPointerToAny, /*MI*/0, /*Op*/1, /*SizeInBits*/0,
      GIM_CheckComplexPattern, /*MI*/0, /*Op*/1, /*Renderer*/GIMT_Encode2(0), GIMT_Encode2(GICP_gi_ds_64bit_4byte_aligned),
      // (st v4bf16:{ *:[v4bf16] }:$value, (DS64Bit4ByteAligned:{ *:[iPTR] } i32:{ *:[i32] }:$ptr, i8:{ *:[i8] }:$offset0, i8:{ *:[i8] }:$offset1))<<P:Predicate_unindexedstore>><<P:Predicate_store_local>>  =>  (DS_WRITE2_B32_gfx9 ?:{ *:[i32] }:$ptr, (EXTRACT_SUBREG:{ *:[i32] } VReg_64:{ *:[v4bf16] }:$value, sub0:{ *:[i32] }), (EXTRACT_SUBREG:{ *:[i32] } VReg_64:{ *:[v4bf16] }:$value, sub1:{ *:[i32] }), ?:{ *:[i8] }:$offset0, ?:{ *:[i8] }:$offset1, 0:{ *:[i1] })
      GIR_MakeTempReg, /*TempRegID*/0, /*TypeID*/GILLT_s32,
      GIR_MakeTempReg, /*TempRegID*/1, /*TypeID*/GILLT_s32,
      GIR_BuildMI, /*InsnID*/2, /*Opcode*/GIMT_Encode2(TargetOpcode::COPY),
      GIR_AddTempRegister, /*InsnID*/2, /*TempRegID*/1, /*TempRegFlags*/GIMT_Encode2(RegState::Define),
      GIR_CopySubReg, /*NewInsnID*/2, /*OldInsnID*/0, /*OpIdx*/0, /*SubRegIdx*/GIMT_Encode2(11), // value
      GIR_ConstrainOperandRC, /*InsnID*/2, /*Op*/0, GIMT_Encode2(AMDGPU::VGPR_32RegClassID),
      GIR_ConstrainOperandRC, /*InsnID*/2, /*Op*/1, GIMT_Encode2(AMDGPU::VReg_64RegClassID),
      GIR_BuildMI, /*InsnID*/1, /*Opcode*/GIMT_Encode2(TargetOpcode::COPY),
      GIR_AddTempRegister, /*InsnID*/1, /*TempRegID*/0, /*TempRegFlags*/GIMT_Encode2(RegState::Define),
      GIR_CopySubReg, /*NewInsnID*/1, /*OldInsnID*/0, /*OpIdx*/0, /*SubRegIdx*/GIMT_Encode2(3), // value
      GIR_ConstrainOperandRC, /*InsnID*/1, /*Op*/0, GIMT_Encode2(AMDGPU::VGPR_32RegClassID),
      GIR_ConstrainOperandRC, /*InsnID*/1, /*Op*/1, GIMT_Encode2(AMDGPU::VReg_64RegClassID),
      GIR_BuildMI, /*InsnID*/0, /*Opcode*/GIMT_Encode2(AMDGPU::DS_WRITE2_B32_gfx9),
      GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/0, // ptr
      GIR_AddSimpleTempRegister, /*InsnID*/0, /*TempRegID*/0,
      GIR_AddSimpleTempRegister, /*InsnID*/0, /*TempRegID*/1,
      GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/1, // offset0
      GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/2, // offset1
      GIR_AddImm8, /*InsnID*/0, /*Imm*/0,
      GIR_MergeMemOperands, /*InsnID*/0, /*NumInsns*/1, /*MergeInsnID's*/0,
      GIR_ConstrainSelectedInstOperands, /*InsnID*/0,
      GIR_EraseFromParent, /*InsnID*/0,
      // GIR_Coverage, 6698,
      GIR_Done,
    // Label 2297: @151213
    GIM_Try, /*On fail goto*//*Label 2298*/ GIMT_Encode4(151333), // Rule ID 6702 //
      GIM_CheckFeatures, GIMT_Encode2(GIFBS_NotLDSRequiresM0Init),
      GIM_CheckMemoryAddressSpace, /*MI*/0, /*MMO*/0, /*NumAddrSpace*/1, /*AddrSpace*/3,
      GIM_CheckAtomicOrdering, /*MI*/0, /*Order*/(uint8_t)AtomicOrdering::NotAtomic,
      GIM_CheckPointerToAny, /*MI*/0, /*Op*/1, /*SizeInBits*/0,
      GIM_CheckComplexPattern, /*MI*/0, /*Op*/1, /*Renderer*/GIMT_Encode2(0), GIMT_Encode2(GICP_gi_ds_64bit_4byte_aligned),
      // (st v4i16:{ *:[v4i16] }:$value, (DS64Bit4ByteAligned:{ *:[iPTR] } i32:{ *:[i32] }:$ptr, i8:{ *:[i8] }:$offset0, i8:{ *:[i8] }:$offset1))<<P:Predicate_unindexedstore>><<P:Predicate_store_local>>  =>  (DS_WRITE2_B32_gfx9 ?:{ *:[i32] }:$ptr, (EXTRACT_SUBREG:{ *:[i32] } VReg_64:{ *:[v4i16] }:$value, sub0:{ *:[i32] }), (EXTRACT_SUBREG:{ *:[i32] } VReg_64:{ *:[v4i16] }:$value, sub1:{ *:[i32] }), ?:{ *:[i8] }:$offset0, ?:{ *:[i8] }:$offset1, 0:{ *:[i1] })
      GIR_MakeTempReg, /*TempRegID*/0, /*TypeID*/GILLT_s32,
      GIR_MakeTempReg, /*TempRegID*/1, /*TypeID*/GILLT_s32,
      GIR_BuildMI, /*InsnID*/2, /*Opcode*/GIMT_Encode2(TargetOpcode::COPY),
      GIR_AddTempRegister, /*InsnID*/2, /*TempRegID*/1, /*TempRegFlags*/GIMT_Encode2(RegState::Define),
      GIR_CopySubReg, /*NewInsnID*/2, /*OldInsnID*/0, /*OpIdx*/0, /*SubRegIdx*/GIMT_Encode2(11), // value
      GIR_ConstrainOperandRC, /*InsnID*/2, /*Op*/0, GIMT_Encode2(AMDGPU::VGPR_32RegClassID),
      GIR_ConstrainOperandRC, /*InsnID*/2, /*Op*/1, GIMT_Encode2(AMDGPU::VReg_64RegClassID),
      GIR_BuildMI, /*InsnID*/1, /*Opcode*/GIMT_Encode2(TargetOpcode::COPY),
      GIR_AddTempRegister, /*InsnID*/1, /*TempRegID*/0, /*TempRegFlags*/GIMT_Encode2(RegState::Define),
      GIR_CopySubReg, /*NewInsnID*/1, /*OldInsnID*/0, /*OpIdx*/0, /*SubRegIdx*/GIMT_Encode2(3), // value
      GIR_ConstrainOperandRC, /*InsnID*/1, /*Op*/0, GIMT_Encode2(AMDGPU::VGPR_32RegClassID),
      GIR_ConstrainOperandRC, /*InsnID*/1, /*Op*/1, GIMT_Encode2(AMDGPU::VReg_64RegClassID),
      GIR_BuildMI, /*InsnID*/0, /*Opcode*/GIMT_Encode2(AMDGPU::DS_WRITE2_B32_gfx9),
      GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/0, // ptr
      GIR_AddSimpleTempRegister, /*InsnID*/0, /*TempRegID*/0,
      GIR_AddSimpleTempRegister, /*InsnID*/0, /*TempRegID*/1,
      GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/1, // offset0
      GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/2, // offset1
      GIR_AddImm8, /*InsnID*/0, /*Imm*/0,
      GIR_MergeMemOperands, /*InsnID*/0, /*NumInsns*/1, /*MergeInsnID's*/0,
      GIR_ConstrainSelectedInstOperands, /*InsnID*/0,
      GIR_EraseFromParent, /*InsnID*/0,
      // GIR_Coverage, 6702,
      GIR_Done,
    // Label 2298: @151333
    GIM_Try, /*On fail goto*//*Label 2299*/ GIMT_Encode4(151395), // Rule ID 3047 //
      GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasFlatGlobalInsts),
      GIM_CheckMemoryAddressSpace, /*MI*/0, /*MMO*/0, /*NumAddrSpace*/1, /*AddrSpace*/1,
      GIM_CheckAtomicOrdering, /*MI*/0, /*Order*/(uint8_t)AtomicOrdering::NotAtomic,
      GIM_CheckPointerToAny, /*MI*/0, /*Op*/1, /*SizeInBits*/0,
      GIM_CheckComplexPattern, /*MI*/0, /*Op*/1, /*Renderer*/GIMT_Encode2(0), GIMT_Encode2(GICP_gi_global_saddr),
      // (st v4f16:{ *:[v4f16] }:$data, (GlobalSAddr:{ *:[iPTR] } SReg_64:{ *:[i64] }:$saddr, VGPR_32:{ *:[i32] }:$voffset, i32:{ *:[i32] }:$offset))<<P:Predicate_unindexedstore>><<P:Predicate_store_global>>  =>  (GLOBAL_STORE_DWORDX2_SADDR ?:{ *:[i32] }:$voffset, anonymous_15036:{ *:[v4f16] }:$data, ?:{ *:[i64] }:$saddr, ?:{ *:[i32] }:$offset)
      GIR_BuildMI, /*InsnID*/0, /*Opcode*/GIMT_Encode2(AMDGPU::GLOBAL_STORE_DWORDX2_SADDR),
      GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/1, // voffset
      GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/0, // data
      GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/0, // saddr
      GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/2, // offset
      GIR_AddImm8, /*InsnID*/0, /*Imm*/0,
      GIR_MergeMemOperands, /*InsnID*/0, /*NumInsns*/1, /*MergeInsnID's*/0,
      GIR_ConstrainSelectedInstOperands, /*InsnID*/0,
      GIR_EraseFromParent, /*InsnID*/0,
      // GIR_Coverage, 3047,
      GIR_Done,
    // Label 2299: @151395
    GIM_Try, /*On fail goto*//*Label 2300*/ GIMT_Encode4(151457), // Rule ID 3051 //
      GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasFlatGlobalInsts),
      GIM_CheckMemoryAddressSpace, /*MI*/0, /*MMO*/0, /*NumAddrSpace*/1, /*AddrSpace*/1,
      GIM_CheckAtomicOrdering, /*MI*/0, /*Order*/(uint8_t)AtomicOrdering::NotAtomic,
      GIM_CheckPointerToAny, /*MI*/0, /*Op*/1, /*SizeInBits*/0,
      GIM_CheckComplexPattern, /*MI*/0, /*Op*/1, /*Renderer*/GIMT_Encode2(0), GIMT_Encode2(GICP_gi_global_saddr),
      // (st v4bf16:{ *:[v4bf16] }:$data, (GlobalSAddr:{ *:[iPTR] } SReg_64:{ *:[i64] }:$saddr, VGPR_32:{ *:[i32] }:$voffset, i32:{ *:[i32] }:$offset))<<P:Predicate_unindexedstore>><<P:Predicate_store_global>>  =>  (GLOBAL_STORE_DWORDX2_SADDR ?:{ *:[i32] }:$voffset, anonymous_15036:{ *:[v4bf16] }:$data, ?:{ *:[i64] }:$saddr, ?:{ *:[i32] }:$offset)
      GIR_BuildMI, /*InsnID*/0, /*Opcode*/GIMT_Encode2(AMDGPU::GLOBAL_STORE_DWORDX2_SADDR),
      GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/1, // voffset
      GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/0, // data
      GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/0, // saddr
      GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/2, // offset
      GIR_AddImm8, /*InsnID*/0, /*Imm*/0,
      GIR_MergeMemOperands, /*InsnID*/0, /*NumInsns*/1, /*MergeInsnID's*/0,
      GIR_ConstrainSelectedInstOperands, /*InsnID*/0,
      GIR_EraseFromParent, /*InsnID*/0,
      // GIR_Coverage, 3051,
      GIR_Done,
    // Label 2300: @151457
    GIM_Try, /*On fail goto*//*Label 2301*/ GIMT_Encode4(151519), // Rule ID 3055 //
      GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasFlatGlobalInsts),
      GIM_CheckMemoryAddressSpace, /*MI*/0, /*MMO*/0, /*NumAddrSpace*/1, /*AddrSpace*/1,
      GIM_CheckAtomicOrdering, /*MI*/0, /*Order*/(uint8_t)AtomicOrdering::NotAtomic,
      GIM_CheckPointerToAny, /*MI*/0, /*Op*/1, /*SizeInBits*/0,
      GIM_CheckComplexPattern, /*MI*/0, /*Op*/1, /*Renderer*/GIMT_Encode2(0), GIMT_Encode2(GICP_gi_global_saddr),
      // (st v4i16:{ *:[v4i16] }:$data, (GlobalSAddr:{ *:[iPTR] } SReg_64:{ *:[i64] }:$saddr, VGPR_32:{ *:[i32] }:$voffset, i32:{ *:[i32] }:$offset))<<P:Predicate_unindexedstore>><<P:Predicate_store_global>>  =>  (GLOBAL_STORE_DWORDX2_SADDR ?:{ *:[i32] }:$voffset, anonymous_15036:{ *:[v4i16] }:$data, ?:{ *:[i64] }:$saddr, ?:{ *:[i32] }:$offset)
      GIR_BuildMI, /*InsnID*/0, /*Opcode*/GIMT_Encode2(AMDGPU::GLOBAL_STORE_DWORDX2_SADDR),
      GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/1, // voffset
      GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/0, // data
      GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/0, // saddr
      GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/2, // offset
      GIR_AddImm8, /*InsnID*/0, /*Imm*/0,
      GIR_MergeMemOperands, /*InsnID*/0, /*NumInsns*/1, /*MergeInsnID's*/0,
      GIR_ConstrainSelectedInstOperands, /*InsnID*/0,
      GIR_EraseFromParent, /*InsnID*/0,
      // GIR_Coverage, 3055,
      GIR_Done,
    // Label 2301: @151519
    GIM_Try, /*On fail goto*//*Label 2302*/ GIMT_Encode4(151576), // Rule ID 3046 //
      GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasFlatGlobalInsts),
      GIM_CheckMemoryAddressSpace, /*MI*/0, /*MMO*/0, /*NumAddrSpace*/1, /*AddrSpace*/1,
      GIM_CheckAtomicOrdering, /*MI*/0, /*Order*/(uint8_t)AtomicOrdering::NotAtomic,
      GIM_CheckPointerToAny, /*MI*/0, /*Op*/1, /*SizeInBits*/0,
      GIM_CheckComplexPattern, /*MI*/0, /*Op*/1, /*Renderer*/GIMT_Encode2(0), GIMT_Encode2(GICP_gi_global_offset),
      // (st v4f16:{ *:[v4f16] }:$data, (GlobalOffset:{ *:[iPTR] } i64:{ *:[i64] }:$vaddr, i32:{ *:[i32] }:$offset))<<P:Predicate_unindexedstore>><<P:Predicate_store_global>>  =>  (GLOBAL_STORE_DWORDX2 ?:{ *:[i64] }:$vaddr, anonymous_15036:{ *:[v4f16] }:$data, ?:{ *:[i32] }:$offset)
      GIR_BuildMI, /*InsnID*/0, /*Opcode*/GIMT_Encode2(AMDGPU::GLOBAL_STORE_DWORDX2),
      GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/0, // vaddr
      GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/0, // data
      GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/1, // offset
      GIR_AddImm8, /*InsnID*/0, /*Imm*/0,
      GIR_MergeMemOperands, /*InsnID*/0, /*NumInsns*/1, /*MergeInsnID's*/0,
      GIR_ConstrainSelectedInstOperands, /*InsnID*/0,
      GIR_EraseFromParent, /*InsnID*/0,
      // GIR_Coverage, 3046,
      GIR_Done,
    // Label 2302: @151576
    GIM_Try, /*On fail goto*//*Label 2303*/ GIMT_Encode4(151633), // Rule ID 3050 //
      GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasFlatGlobalInsts),
      GIM_CheckMemoryAddressSpace, /*MI*/0, /*MMO*/0, /*NumAddrSpace*/1, /*AddrSpace*/1,
      GIM_CheckAtomicOrdering, /*MI*/0, /*Order*/(uint8_t)AtomicOrdering::NotAtomic,
      GIM_CheckPointerToAny, /*MI*/0, /*Op*/1, /*SizeInBits*/0,
      GIM_CheckComplexPattern, /*MI*/0, /*Op*/1, /*Renderer*/GIMT_Encode2(0), GIMT_Encode2(GICP_gi_global_offset),
      // (st v4bf16:{ *:[v4bf16] }:$data, (GlobalOffset:{ *:[iPTR] } i64:{ *:[i64] }:$vaddr, i32:{ *:[i32] }:$offset))<<P:Predicate_unindexedstore>><<P:Predicate_store_global>>  =>  (GLOBAL_STORE_DWORDX2 ?:{ *:[i64] }:$vaddr, anonymous_15036:{ *:[v4bf16] }:$data, ?:{ *:[i32] }:$offset)
      GIR_BuildMI, /*InsnID*/0, /*Opcode*/GIMT_Encode2(AMDGPU::GLOBAL_STORE_DWORDX2),
      GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/0, // vaddr
      GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/0, // data
      GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/1, // offset
      GIR_AddImm8, /*InsnID*/0, /*Imm*/0,
      GIR_MergeMemOperands, /*InsnID*/0, /*NumInsns*/1, /*MergeInsnID's*/0,
      GIR_ConstrainSelectedInstOperands, /*InsnID*/0,
      GIR_EraseFromParent, /*InsnID*/0,
      // GIR_Coverage, 3050,
      GIR_Done,
    // Label 2303: @151633
    GIM_Try, /*On fail goto*//*Label 2304*/ GIMT_Encode4(151690), // Rule ID 3054 //
      GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasFlatGlobalInsts),
      GIM_CheckMemoryAddressSpace, /*MI*/0, /*MMO*/0, /*NumAddrSpace*/1, /*AddrSpace*/1,
      GIM_CheckAtomicOrdering, /*MI*/0, /*Order*/(uint8_t)AtomicOrdering::NotAtomic,
      GIM_CheckPointerToAny, /*MI*/0, /*Op*/1, /*SizeInBits*/0,
      GIM_CheckComplexPattern, /*MI*/0, /*Op*/1, /*Renderer*/GIMT_Encode2(0), GIMT_Encode2(GICP_gi_global_offset),
      // (st v4i16:{ *:[v4i16] }:$data, (GlobalOffset:{ *:[iPTR] } i64:{ *:[i64] }:$vaddr, i32:{ *:[i32] }:$offset))<<P:Predicate_unindexedstore>><<P:Predicate_store_global>>  =>  (GLOBAL_STORE_DWORDX2 ?:{ *:[i64] }:$vaddr, anonymous_15036:{ *:[v4i16] }:$data, ?:{ *:[i32] }:$offset)
      GIR_BuildMI, /*InsnID*/0, /*Opcode*/GIMT_Encode2(AMDGPU::GLOBAL_STORE_DWORDX2),
      GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/0, // vaddr
      GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/0, // data
      GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/1, // offset
      GIR_AddImm8, /*InsnID*/0, /*Imm*/0,
      GIR_MergeMemOperands, /*InsnID*/0, /*NumInsns*/1, /*MergeInsnID's*/0,
      GIR_ConstrainSelectedInstOperands, /*InsnID*/0,
      GIR_EraseFromParent, /*InsnID*/0,
      // GIR_Coverage, 3054,
      GIR_Done,
    // Label 2304: @151690
    GIM_Try, /*On fail goto*//*Label 2305*/ GIMT_Encode4(151748), // Rule ID 2796 //
      GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasFlatAddressSpace),
      GIM_CheckMemoryAddressSpace, /*MI*/0, /*MMO*/0, /*NumAddrSpace*/2, /*AddrSpace*/0, /*AddrSpace*/1,
      GIM_CheckAtomicOrdering, /*MI*/0, /*Order*/(uint8_t)AtomicOrdering::NotAtomic,
      GIM_CheckPointerToAny, /*MI*/0, /*Op*/1, /*SizeInBits*/0,
      GIM_CheckComplexPattern, /*MI*/0, /*Op*/1, /*Renderer*/GIMT_Encode2(0), GIMT_Encode2(GICP_gi_flat_offset),
      // (st v4f16:{ *:[v4f16] }:$data, (FlatOffset:{ *:[iPTR] } i64:{ *:[i64] }:$vaddr, i32:{ *:[i32] }:$offset))<<P:Predicate_unindexedstore>><<P:Predicate_store_flat>>  =>  (FLAT_STORE_DWORDX2 ?:{ *:[i64] }:$vaddr, anonymous_15036:{ *:[v4f16] }:$data, ?:{ *:[i32] }:$offset)
      GIR_BuildMI, /*InsnID*/0, /*Opcode*/GIMT_Encode2(AMDGPU::FLAT_STORE_DWORDX2),
      GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/0, // vaddr
      GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/0, // data
      GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/1, // offset
      GIR_AddImm8, /*InsnID*/0, /*Imm*/0,
      GIR_MergeMemOperands, /*InsnID*/0, /*NumInsns*/1, /*MergeInsnID's*/0,
      GIR_ConstrainSelectedInstOperands, /*InsnID*/0,
      GIR_EraseFromParent, /*InsnID*/0,
      // GIR_Coverage, 2796,
      GIR_Done,
    // Label 2305: @151748
    GIM_Try, /*On fail goto*//*Label 2306*/ GIMT_Encode4(151806), // Rule ID 2798 //
      GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasFlatAddressSpace),
      GIM_CheckMemoryAddressSpace, /*MI*/0, /*MMO*/0, /*NumAddrSpace*/2, /*AddrSpace*/0, /*AddrSpace*/1,
      GIM_CheckAtomicOrdering, /*MI*/0, /*Order*/(uint8_t)AtomicOrdering::NotAtomic,
      GIM_CheckPointerToAny, /*MI*/0, /*Op*/1, /*SizeInBits*/0,
      GIM_CheckComplexPattern, /*MI*/0, /*Op*/1, /*Renderer*/GIMT_Encode2(0), GIMT_Encode2(GICP_gi_flat_offset),
      // (st v4bf16:{ *:[v4bf16] }:$data, (FlatOffset:{ *:[iPTR] } i64:{ *:[i64] }:$vaddr, i32:{ *:[i32] }:$offset))<<P:Predicate_unindexedstore>><<P:Predicate_store_flat>>  =>  (FLAT_STORE_DWORDX2 ?:{ *:[i64] }:$vaddr, anonymous_15036:{ *:[v4bf16] }:$data, ?:{ *:[i32] }:$offset)
      GIR_BuildMI, /*InsnID*/0, /*Opcode*/GIMT_Encode2(AMDGPU::FLAT_STORE_DWORDX2),
      GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/0, // vaddr
      GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/0, // data
      GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/1, // offset
      GIR_AddImm8, /*InsnID*/0, /*Imm*/0,
      GIR_MergeMemOperands, /*InsnID*/0, /*NumInsns*/1, /*MergeInsnID's*/0,
      GIR_ConstrainSelectedInstOperands, /*InsnID*/0,
      GIR_EraseFromParent, /*InsnID*/0,
      // GIR_Coverage, 2798,
      GIR_Done,
    // Label 2306: @151806
    GIM_Try, /*On fail goto*//*Label 2307*/ GIMT_Encode4(151864), // Rule ID 2800 //
      GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasFlatAddressSpace),
      GIM_CheckMemoryAddressSpace, /*MI*/0, /*MMO*/0, /*NumAddrSpace*/2, /*AddrSpace*/0, /*AddrSpace*/1,
      GIM_CheckAtomicOrdering, /*MI*/0, /*Order*/(uint8_t)AtomicOrdering::NotAtomic,
      GIM_CheckPointerToAny, /*MI*/0, /*Op*/1, /*SizeInBits*/0,
      GIM_CheckComplexPattern, /*MI*/0, /*Op*/1, /*Renderer*/GIMT_Encode2(0), GIMT_Encode2(GICP_gi_flat_offset),
      // (st v4i16:{ *:[v4i16] }:$data, (FlatOffset:{ *:[iPTR] } i64:{ *:[i64] }:$vaddr, i32:{ *:[i32] }:$offset))<<P:Predicate_unindexedstore>><<P:Predicate_store_flat>>  =>  (FLAT_STORE_DWORDX2 ?:{ *:[i64] }:$vaddr, anonymous_15036:{ *:[v4i16] }:$data, ?:{ *:[i32] }:$offset)
      GIR_BuildMI, /*InsnID*/0, /*Opcode*/GIMT_Encode2(AMDGPU::FLAT_STORE_DWORDX2),
      GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/0, // vaddr
      GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/0, // data
      GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/1, // offset
      GIR_AddImm8, /*InsnID*/0, /*Imm*/0,
      GIR_MergeMemOperands, /*InsnID*/0, /*NumInsns*/1, /*MergeInsnID's*/0,
      GIR_ConstrainSelectedInstOperands, /*InsnID*/0,
      GIR_EraseFromParent, /*InsnID*/0,
      // GIR_Coverage, 2800,
      GIR_Done,
    // Label 2307: @151864
    GIM_Reject,
    // Label 1821: @151865
    GIM_Try, /*On fail goto*//*Label 2308*/ GIMT_Encode4(151935), // Rule ID 6865 //
      GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasUnalignedAccessMode_LDSRequiresM0Init),
      GIM_CheckMemorySizeEqualToLLT, /*MI*/0, /*MMO*/0, /*OpIdx*/0,
      GIM_CheckMemoryAddressSpace, /*MI*/0, /*MMO*/0, /*NumAddrSpace*/1, /*AddrSpace*/3,
      GIM_CheckMemoryAddressSpace, /*MI*/0, /*MMO*/0, /*NumAddrSpace*/1, /*AddrSpace*/3,
      GIM_CheckAtomicOrdering, /*MI*/0, /*Order*/(uint8_t)AtomicOrdering::NotAtomic,
      GIM_CheckPointerToAny, /*MI*/0, /*Op*/1, /*SizeInBits*/0,
      GIM_CheckCxxInsnPredicate, /*MI*/0, /*FnId*/GIMT_Encode2(GICXXPred_MI_Predicate_store_align_less_than_4_local_m0),
      GIM_CheckComplexPattern, /*MI*/0, /*Op*/1, /*Renderer*/GIMT_Encode2(0), GIMT_Encode2(GICP_gi_ds_1addr_1offset),
      // (AMDGPUst_glue v4i32:{ *:[v4i32] }:$value, (DS1Addr1Offset:{ *:[iPTR] } i32:{ *:[i32] }:$ptr, i32:{ *:[i32] }:$offset))<<P:Predicate_unindexedstore_glue>><<P:Predicate_store_glue>><<P:Predicate_store_local_m0>><<P:Predicate_store_align_less_than_4_local_m0>>  =>  (DS_WRITE_B128 ?:{ *:[i32] }:$ptr, anonymous_15034:{ *:[v4i32] }:$value, offset:{ *:[i32] }:$offset, 0:{ *:[i1] })
      GIR_BuildMI, /*InsnID*/0, /*Opcode*/GIMT_Encode2(AMDGPU::DS_WRITE_B128),
      GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/0, // ptr
      GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/0, // value
      GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/1, // offset
      GIR_AddImm8, /*InsnID*/0, /*Imm*/0,
      GIR_MergeMemOperands, /*InsnID*/0, /*NumInsns*/1, /*MergeInsnID's*/0,
      GIR_ConstrainSelectedInstOperands, /*InsnID*/0,
      GIR_EraseFromParent, /*InsnID*/0,
      // GIR_Coverage, 6865,
      GIR_Done,
    // Label 2308: @151935
    GIM_Try, /*On fail goto*//*Label 2309*/ GIMT_Encode4(152005), // Rule ID 6869 //
      GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasUnalignedAccessMode_LDSRequiresM0Init),
      GIM_CheckMemorySizeEqualToLLT, /*MI*/0, /*MMO*/0, /*OpIdx*/0,
      GIM_CheckMemoryAddressSpace, /*MI*/0, /*MMO*/0, /*NumAddrSpace*/1, /*AddrSpace*/3,
      GIM_CheckMemoryAddressSpace, /*MI*/0, /*MMO*/0, /*NumAddrSpace*/1, /*AddrSpace*/3,
      GIM_CheckAtomicOrdering, /*MI*/0, /*Order*/(uint8_t)AtomicOrdering::NotAtomic,
      GIM_CheckPointerToAny, /*MI*/0, /*Op*/1, /*SizeInBits*/0,
      GIM_CheckCxxInsnPredicate, /*MI*/0, /*FnId*/GIMT_Encode2(GICXXPred_MI_Predicate_store_align_less_than_4_local_m0),
      GIM_CheckComplexPattern, /*MI*/0, /*Op*/1, /*Renderer*/GIMT_Encode2(0), GIMT_Encode2(GICP_gi_ds_1addr_1offset),
      // (AMDGPUst_glue v4f32:{ *:[v4f32] }:$value, (DS1Addr1Offset:{ *:[iPTR] } i32:{ *:[i32] }:$ptr, i32:{ *:[i32] }:$offset))<<P:Predicate_unindexedstore_glue>><<P:Predicate_store_glue>><<P:Predicate_store_local_m0>><<P:Predicate_store_align_less_than_4_local_m0>>  =>  (DS_WRITE_B128 ?:{ *:[i32] }:$ptr, anonymous_15034:{ *:[v4f32] }:$value, offset:{ *:[i32] }:$offset, 0:{ *:[i1] })
      GIR_BuildMI, /*InsnID*/0, /*Opcode*/GIMT_Encode2(AMDGPU::DS_WRITE_B128),
      GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/0, // ptr
      GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/0, // value
      GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/1, // offset
      GIR_AddImm8, /*InsnID*/0, /*Imm*/0,
      GIR_MergeMemOperands, /*InsnID*/0, /*NumInsns*/1, /*MergeInsnID's*/0,
      GIR_ConstrainSelectedInstOperands, /*InsnID*/0,
      GIR_EraseFromParent, /*InsnID*/0,
      // GIR_Coverage, 6869,
      GIR_Done,
    // Label 2309: @152005
    GIM_Try, /*On fail goto*//*Label 2310*/ GIMT_Encode4(152070), // Rule ID 6789 //
      GIM_CheckFeatures, GIMT_Encode2(GIFBS_LDSRequiresM0Init_isGFX7Plus),
      GIM_CheckMemorySizeEqualToLLT, /*MI*/0, /*MMO*/0, /*OpIdx*/0,
      GIM_CheckMemoryAddressSpace, /*MI*/0, /*MMO*/0, /*NumAddrSpace*/1, /*AddrSpace*/3,
      GIM_CheckMemoryAlignment, /*MI*/0, /*MMO*/0, /*MinAlign*/16,
      GIM_CheckAtomicOrdering, /*MI*/0, /*Order*/(uint8_t)AtomicOrdering::NotAtomic,
      GIM_CheckPointerToAny, /*MI*/0, /*Op*/1, /*SizeInBits*/0,
      GIM_CheckComplexPattern, /*MI*/0, /*Op*/1, /*Renderer*/GIMT_Encode2(0), GIMT_Encode2(GICP_gi_ds_1addr_1offset),
      // (AMDGPUst_glue v4i32:{ *:[v4i32] }:$value, (DS1Addr1Offset:{ *:[iPTR] } i32:{ *:[i32] }:$ptr, i32:{ *:[i32] }:$offset))<<P:Predicate_unindexedstore_glue>><<P:Predicate_store_glue>><<P:Predicate_store_local_m0>><<P:Predicate_store_align16_local_m0>>  =>  (DS_WRITE_B128 ?:{ *:[i32] }:$ptr, anonymous_15034:{ *:[v4i32] }:$value, offset:{ *:[i32] }:$offset, 0:{ *:[i1] })
      GIR_BuildMI, /*InsnID*/0, /*Opcode*/GIMT_Encode2(AMDGPU::DS_WRITE_B128),
      GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/0, // ptr
      GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/0, // value
      GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/1, // offset
      GIR_AddImm8, /*InsnID*/0, /*Imm*/0,
      GIR_MergeMemOperands, /*InsnID*/0, /*NumInsns*/1, /*MergeInsnID's*/0,
      GIR_ConstrainSelectedInstOperands, /*InsnID*/0,
      GIR_EraseFromParent, /*InsnID*/0,
      // GIR_Coverage, 6789,
      GIR_Done,
    // Label 2310: @152070
    GIM_Try, /*On fail goto*//*Label 2311*/ GIMT_Encode4(152135), // Rule ID 6793 //
      GIM_CheckFeatures, GIMT_Encode2(GIFBS_LDSRequiresM0Init_isGFX7Plus),
      GIM_CheckMemorySizeEqualToLLT, /*MI*/0, /*MMO*/0, /*OpIdx*/0,
      GIM_CheckMemoryAddressSpace, /*MI*/0, /*MMO*/0, /*NumAddrSpace*/1, /*AddrSpace*/3,
      GIM_CheckMemoryAlignment, /*MI*/0, /*MMO*/0, /*MinAlign*/16,
      GIM_CheckAtomicOrdering, /*MI*/0, /*Order*/(uint8_t)AtomicOrdering::NotAtomic,
      GIM_CheckPointerToAny, /*MI*/0, /*Op*/1, /*SizeInBits*/0,
      GIM_CheckComplexPattern, /*MI*/0, /*Op*/1, /*Renderer*/GIMT_Encode2(0), GIMT_Encode2(GICP_gi_ds_1addr_1offset),
      // (AMDGPUst_glue v4f32:{ *:[v4f32] }:$value, (DS1Addr1Offset:{ *:[iPTR] } i32:{ *:[i32] }:$ptr, i32:{ *:[i32] }:$offset))<<P:Predicate_unindexedstore_glue>><<P:Predicate_store_glue>><<P:Predicate_store_local_m0>><<P:Predicate_store_align16_local_m0>>  =>  (DS_WRITE_B128 ?:{ *:[i32] }:$ptr, anonymous_15034:{ *:[v4f32] }:$value, offset:{ *:[i32] }:$offset, 0:{ *:[i1] })
      GIR_BuildMI, /*InsnID*/0, /*Opcode*/GIMT_Encode2(AMDGPU::DS_WRITE_B128),
      GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/0, // ptr
      GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/0, // value
      GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/1, // offset
      GIR_AddImm8, /*InsnID*/0, /*Imm*/0,
      GIR_MergeMemOperands, /*InsnID*/0, /*NumInsns*/1, /*MergeInsnID's*/0,
      GIR_ConstrainSelectedInstOperands, /*InsnID*/0,
      GIR_EraseFromParent, /*InsnID*/0,
      // GIR_Coverage, 6793,
      GIR_Done,
    // Label 2311: @152135
    GIM_Try, /*On fail goto*//*Label 2312*/ GIMT_Encode4(152201), // Rule ID 6866 //
      GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasUnalignedAccessMode_NotLDSRequiresM0Init),
      GIM_CheckMemoryAddressSpace, /*MI*/0, /*MMO*/0, /*NumAddrSpace*/1, /*AddrSpace*/3,
      GIM_CheckMemoryAddressSpace, /*MI*/0, /*MMO*/0, /*NumAddrSpace*/1, /*AddrSpace*/3,
      GIM_CheckAtomicOrdering, /*MI*/0, /*Order*/(uint8_t)AtomicOrdering::NotAtomic,
      GIM_CheckPointerToAny, /*MI*/0, /*Op*/1, /*SizeInBits*/0,
      GIM_CheckCxxInsnPredicate, /*MI*/0, /*FnId*/GIMT_Encode2(GICXXPred_MI_Predicate_store_align_less_than_4_local),
      GIM_CheckComplexPattern, /*MI*/0, /*Op*/1, /*Renderer*/GIMT_Encode2(0), GIMT_Encode2(GICP_gi_ds_1addr_1offset),
      // (st v4i32:{ *:[v4i32] }:$value, (DS1Addr1Offset:{ *:[iPTR] } i32:{ *:[i32] }:$ptr, i32:{ *:[i32] }:$offset))<<P:Predicate_unindexedstore>><<P:Predicate_store_local>><<P:Predicate_store_align_less_than_4_local>>  =>  (DS_WRITE_B128_gfx9 ?:{ *:[i32] }:$ptr, anonymous_15034:{ *:[v4i32] }:$value, offset:{ *:[i32] }:$offset, 0:{ *:[i1] })
      GIR_BuildMI, /*InsnID*/0, /*Opcode*/GIMT_Encode2(AMDGPU::DS_WRITE_B128_gfx9),
      GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/0, // ptr
      GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/0, // value
      GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/1, // offset
      GIR_AddImm8, /*InsnID*/0, /*Imm*/0,
      GIR_MergeMemOperands, /*InsnID*/0, /*NumInsns*/1, /*MergeInsnID's*/0,
      GIR_ConstrainSelectedInstOperands, /*InsnID*/0,
      GIR_EraseFromParent, /*InsnID*/0,
      // GIR_Coverage, 6866,
      GIR_Done,
    // Label 2312: @152201
    GIM_Try, /*On fail goto*//*Label 2313*/ GIMT_Encode4(152267), // Rule ID 6870 //
      GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasUnalignedAccessMode_NotLDSRequiresM0Init),
      GIM_CheckMemoryAddressSpace, /*MI*/0, /*MMO*/0, /*NumAddrSpace*/1, /*AddrSpace*/3,
      GIM_CheckMemoryAddressSpace, /*MI*/0, /*MMO*/0, /*NumAddrSpace*/1, /*AddrSpace*/3,
      GIM_CheckAtomicOrdering, /*MI*/0, /*Order*/(uint8_t)AtomicOrdering::NotAtomic,
      GIM_CheckPointerToAny, /*MI*/0, /*Op*/1, /*SizeInBits*/0,
      GIM_CheckCxxInsnPredicate, /*MI*/0, /*FnId*/GIMT_Encode2(GICXXPred_MI_Predicate_store_align_less_than_4_local),
      GIM_CheckComplexPattern, /*MI*/0, /*Op*/1, /*Renderer*/GIMT_Encode2(0), GIMT_Encode2(GICP_gi_ds_1addr_1offset),
      // (st v4f32:{ *:[v4f32] }:$value, (DS1Addr1Offset:{ *:[iPTR] } i32:{ *:[i32] }:$ptr, i32:{ *:[i32] }:$offset))<<P:Predicate_unindexedstore>><<P:Predicate_store_local>><<P:Predicate_store_align_less_than_4_local>>  =>  (DS_WRITE_B128_gfx9 ?:{ *:[i32] }:$ptr, anonymous_15034:{ *:[v4f32] }:$value, offset:{ *:[i32] }:$offset, 0:{ *:[i1] })
      GIR_BuildMI, /*InsnID*/0, /*Opcode*/GIMT_Encode2(AMDGPU::DS_WRITE_B128_gfx9),
      GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/0, // ptr
      GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/0, // value
      GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/1, // offset
      GIR_AddImm8, /*InsnID*/0, /*Imm*/0,
      GIR_MergeMemOperands, /*InsnID*/0, /*NumInsns*/1, /*MergeInsnID's*/0,
      GIR_ConstrainSelectedInstOperands, /*InsnID*/0,
      GIR_EraseFromParent, /*InsnID*/0,
      // GIR_Coverage, 6870,
      GIR_Done,
    // Label 2313: @152267
    GIM_Try, /*On fail goto*//*Label 2314*/ GIMT_Encode4(152328), // Rule ID 6790 //
      GIM_CheckFeatures, GIMT_Encode2(GIFBS_NotLDSRequiresM0Init_isGFX7Plus),
      GIM_CheckMemoryAddressSpace, /*MI*/0, /*MMO*/0, /*NumAddrSpace*/1, /*AddrSpace*/3,
      GIM_CheckMemoryAlignment, /*MI*/0, /*MMO*/0, /*MinAlign*/16,
      GIM_CheckAtomicOrdering, /*MI*/0, /*Order*/(uint8_t)AtomicOrdering::NotAtomic,
      GIM_CheckPointerToAny, /*MI*/0, /*Op*/1, /*SizeInBits*/0,
      GIM_CheckComplexPattern, /*MI*/0, /*Op*/1, /*Renderer*/GIMT_Encode2(0), GIMT_Encode2(GICP_gi_ds_1addr_1offset),
      // (st v4i32:{ *:[v4i32] }:$value, (DS1Addr1Offset:{ *:[iPTR] } i32:{ *:[i32] }:$ptr, i32:{ *:[i32] }:$offset))<<P:Predicate_unindexedstore>><<P:Predicate_store_local>><<P:Predicate_store_align16_local>>  =>  (DS_WRITE_B128_gfx9 ?:{ *:[i32] }:$ptr, anonymous_15034:{ *:[v4i32] }:$value, offset:{ *:[i32] }:$offset, 0:{ *:[i1] })
      GIR_BuildMI, /*InsnID*/0, /*Opcode*/GIMT_Encode2(AMDGPU::DS_WRITE_B128_gfx9),
      GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/0, // ptr
      GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/0, // value
      GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/1, // offset
      GIR_AddImm8, /*InsnID*/0, /*Imm*/0,
      GIR_MergeMemOperands, /*InsnID*/0, /*NumInsns*/1, /*MergeInsnID's*/0,
      GIR_ConstrainSelectedInstOperands, /*InsnID*/0,
      GIR_EraseFromParent, /*InsnID*/0,
      // GIR_Coverage, 6790,
      GIR_Done,
    // Label 2314: @152328
    GIM_Try, /*On fail goto*//*Label 2315*/ GIMT_Encode4(152389), // Rule ID 6794 //
      GIM_CheckFeatures, GIMT_Encode2(GIFBS_NotLDSRequiresM0Init_isGFX7Plus),
      GIM_CheckMemoryAddressSpace, /*MI*/0, /*MMO*/0, /*NumAddrSpace*/1, /*AddrSpace*/3,
      GIM_CheckMemoryAlignment, /*MI*/0, /*MMO*/0, /*MinAlign*/16,
      GIM_CheckAtomicOrdering, /*MI*/0, /*Order*/(uint8_t)AtomicOrdering::NotAtomic,
      GIM_CheckPointerToAny, /*MI*/0, /*Op*/1, /*SizeInBits*/0,
      GIM_CheckComplexPattern, /*MI*/0, /*Op*/1, /*Renderer*/GIMT_Encode2(0), GIMT_Encode2(GICP_gi_ds_1addr_1offset),
      // (st v4f32:{ *:[v4f32] }:$value, (DS1Addr1Offset:{ *:[iPTR] } i32:{ *:[i32] }:$ptr, i32:{ *:[i32] }:$offset))<<P:Predicate_unindexedstore>><<P:Predicate_store_local>><<P:Predicate_store_align16_local>>  =>  (DS_WRITE_B128_gfx9 ?:{ *:[i32] }:$ptr, anonymous_15034:{ *:[v4f32] }:$value, offset:{ *:[i32] }:$offset, 0:{ *:[i1] })
      GIR_BuildMI, /*InsnID*/0, /*Opcode*/GIMT_Encode2(AMDGPU::DS_WRITE_B128_gfx9),
      GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/0, // ptr
      GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/0, // value
      GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/1, // offset
      GIR_AddImm8, /*InsnID*/0, /*Imm*/0,
      GIR_MergeMemOperands, /*InsnID*/0, /*NumInsns*/1, /*MergeInsnID's*/0,
      GIR_ConstrainSelectedInstOperands, /*InsnID*/0,
      GIR_EraseFromParent, /*InsnID*/0,
      // GIR_Coverage, 6794,
      GIR_Done,
    // Label 2315: @152389
    GIM_Try, /*On fail goto*//*Label 2316*/ GIMT_Encode4(152454), // Rule ID 5558 //
      GIM_CheckFeatures, GIMT_Encode2(GIFBS_DisableFlatScratch_HasUnrestrictedSOffset),
      GIM_CheckMemoryAddressSpace, /*MI*/0, /*MMO*/0, /*NumAddrSpace*/1, /*AddrSpace*/5,
      GIM_CheckAtomicOrdering, /*MI*/0, /*Order*/(uint8_t)AtomicOrdering::NotAtomic,
      GIM_CheckPointerToAny, /*MI*/0, /*Op*/1, /*SizeInBits*/0,
      GIM_CheckComplexPattern, /*MI*/0, /*Op*/1, /*Renderer*/GIMT_Encode2(0), GIMT_Encode2(GICP_gi_mubuf_scratch_offset),
      // (st v4i32:{ *:[v4i32] }:$value, (MUBUFScratchOffset:{ *:[iPTR] } v4i32:{ *:[v4i32] }:$srsrc, i32:{ *:[i32] }:$soffset, i32:{ *:[i32] }:$offset))<<P:Predicate_unindexedstore>><<P:Predicate_store_private>>  =>  (BUFFER_STORE_DWORDX4_OFFSET VReg_128:{ *:[v4i32] }:$value, ?:{ *:[v4i32] }:$srsrc, ?:{ *:[i32] }:$soffset, ?:{ *:[i32] }:$offset, 0:{ *:[i32] }, 0:{ *:[i1] })
      GIR_BuildMI, /*InsnID*/0, /*Opcode*/GIMT_Encode2(AMDGPU::BUFFER_STORE_DWORDX4_OFFSET),
      GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/0, // value
      GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/0, // srsrc
      GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/1, // soffset
      GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/2, // offset
      GIR_AddImm8, /*InsnID*/0, /*Imm*/0,
      GIR_AddImm8, /*InsnID*/0, /*Imm*/0,
      GIR_MergeMemOperands, /*InsnID*/0, /*NumInsns*/1, /*MergeInsnID's*/0,
      GIR_ConstrainSelectedInstOperands, /*InsnID*/0,
      GIR_EraseFromParent, /*InsnID*/0,
      // GIR_Coverage, 5558,
      GIR_Done,
    // Label 2316: @152454
    GIM_Try, /*On fail goto*//*Label 2317*/ GIMT_Encode4(152519), // Rule ID 5560 //
      GIM_CheckFeatures, GIMT_Encode2(GIFBS_DisableFlatScratch),
      GIM_CheckMemoryAddressSpace, /*MI*/0, /*MMO*/0, /*NumAddrSpace*/1, /*AddrSpace*/5,
      GIM_CheckAtomicOrdering, /*MI*/0, /*Order*/(uint8_t)AtomicOrdering::NotAtomic,
      GIM_CheckPointerToAny, /*MI*/0, /*Op*/1, /*SizeInBits*/0,
      GIM_CheckComplexPattern, /*MI*/0, /*Op*/1, /*Renderer*/GIMT_Encode2(0), GIMT_Encode2(GICP_gi_mubuf_scratch_offset),
      // (st v4i32:{ *:[v4i32] }:$value, (MUBUFScratchOffset:{ *:[iPTR] } v4i32:{ *:[v4i32] }:$srsrc, i32:{ *:[i32] }:$soffset, i32:{ *:[i32] }:$offset))<<P:Predicate_unindexedstore>><<P:Predicate_store_private>>  =>  (BUFFER_STORE_DWORDX4_VBUFFER_OFFSET VReg_128:{ *:[v4i32] }:$value, ?:{ *:[v4i32] }:$srsrc, ?:{ *:[i32] }:$soffset, ?:{ *:[i32] }:$offset, 0:{ *:[i32] }, 0:{ *:[i1] })
      GIR_BuildMI, /*InsnID*/0, /*Opcode*/GIMT_Encode2(AMDGPU::BUFFER_STORE_DWORDX4_VBUFFER_OFFSET),
      GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/0, // value
      GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/0, // srsrc
      GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/1, // soffset
      GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/2, // offset
      GIR_AddImm8, /*InsnID*/0, /*Imm*/0,
      GIR_AddImm8, /*InsnID*/0, /*Imm*/0,
      GIR_MergeMemOperands, /*InsnID*/0, /*NumInsns*/1, /*MergeInsnID's*/0,
      GIR_ConstrainSelectedInstOperands, /*InsnID*/0,
      GIR_EraseFromParent, /*InsnID*/0,
      // GIR_Coverage, 5560,
      GIR_Done,
    // Label 2317: @152519
    GIM_Try, /*On fail goto*//*Label 2318*/ GIMT_Encode4(152581), // Rule ID 3550 //
      GIM_CheckFeatures, GIMT_Encode2(GIFBS_EnableFlatScratch_HasFlatScratchInsts_HasFlatScratchSVSMode),
      GIM_CheckMemoryAddressSpace, /*MI*/0, /*MMO*/0, /*NumAddrSpace*/1, /*AddrSpace*/5,
      GIM_CheckAtomicOrdering, /*MI*/0, /*Order*/(uint8_t)AtomicOrdering::NotAtomic,
      GIM_CheckPointerToAny, /*MI*/0, /*Op*/1, /*SizeInBits*/0,
      GIM_CheckComplexPattern, /*MI*/0, /*Op*/1, /*Renderer*/GIMT_Encode2(0), GIMT_Encode2(GICP_gi_flat_scratch_svaddr),
      // (st v4i32:{ *:[v4i32] }:$data, (ScratchSVAddr:{ *:[iPTR] } VGPR_32:{ *:[i32] }:$vaddr, SGPR_32:{ *:[i32] }:$saddr, i32:{ *:[i32] }:$offset))<<P:Predicate_unindexedstore>><<P:Predicate_store_private>>  =>  (SCRATCH_STORE_DWORDX4_SVS anonymous_15034:{ *:[v4i32] }:$data, ?:{ *:[i32] }:$vaddr, ?:{ *:[i32] }:$saddr, ?:{ *:[i32] }:$offset)
      GIR_BuildMI, /*InsnID*/0, /*Opcode*/GIMT_Encode2(AMDGPU::SCRATCH_STORE_DWORDX4_SVS),
      GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/0, // data
      GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/0, // vaddr
      GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/1, // saddr
      GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/2, // offset
      GIR_AddImm8, /*InsnID*/0, /*Imm*/0,
      GIR_MergeMemOperands, /*InsnID*/0, /*NumInsns*/1, /*MergeInsnID's*/0,
      GIR_ConstrainSelectedInstOperands, /*InsnID*/0,
      GIR_EraseFromParent, /*InsnID*/0,
      // GIR_Coverage, 3550,
      GIR_Done,
    // Label 2318: @152581
    GIM_Try, /*On fail goto*//*Label 2319*/ GIMT_Encode4(152643), // Rule ID 3556 //
      GIM_CheckFeatures, GIMT_Encode2(GIFBS_EnableFlatScratch_HasFlatScratchInsts_HasFlatScratchSVSMode),
      GIM_CheckMemoryAddressSpace, /*MI*/0, /*MMO*/0, /*NumAddrSpace*/1, /*AddrSpace*/5,
      GIM_CheckAtomicOrdering, /*MI*/0, /*Order*/(uint8_t)AtomicOrdering::NotAtomic,
      GIM_CheckPointerToAny, /*MI*/0, /*Op*/1, /*SizeInBits*/0,
      GIM_CheckComplexPattern, /*MI*/0, /*Op*/1, /*Renderer*/GIMT_Encode2(0), GIMT_Encode2(GICP_gi_flat_scratch_svaddr),
      // (st v4f32:{ *:[v4f32] }:$data, (ScratchSVAddr:{ *:[iPTR] } VGPR_32:{ *:[i32] }:$vaddr, SGPR_32:{ *:[i32] }:$saddr, i32:{ *:[i32] }:$offset))<<P:Predicate_unindexedstore>><<P:Predicate_store_private>>  =>  (SCRATCH_STORE_DWORDX4_SVS anonymous_15034:{ *:[v4f32] }:$data, ?:{ *:[i32] }:$vaddr, ?:{ *:[i32] }:$saddr, ?:{ *:[i32] }:$offset)
      GIR_BuildMI, /*InsnID*/0, /*Opcode*/GIMT_Encode2(AMDGPU::SCRATCH_STORE_DWORDX4_SVS),
      GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/0, // data
      GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/0, // vaddr
      GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/1, // saddr
      GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/2, // offset
      GIR_AddImm8, /*InsnID*/0, /*Imm*/0,
      GIR_MergeMemOperands, /*InsnID*/0, /*NumInsns*/1, /*MergeInsnID's*/0,
      GIR_ConstrainSelectedInstOperands, /*InsnID*/0,
      GIR_EraseFromParent, /*InsnID*/0,
      // GIR_Coverage, 3556,
      GIR_Done,
    // Label 2319: @152643
    GIM_Try, /*On fail goto*//*Label 2320*/ GIMT_Encode4(152700), // Rule ID 3549 //
      GIM_CheckFeatures, GIMT_Encode2(GIFBS_EnableFlatScratch_HasFlatScratchInsts),
      GIM_CheckMemoryAddressSpace, /*MI*/0, /*MMO*/0, /*NumAddrSpace*/1, /*AddrSpace*/5,
      GIM_CheckAtomicOrdering, /*MI*/0, /*Order*/(uint8_t)AtomicOrdering::NotAtomic,
      GIM_CheckPointerToAny, /*MI*/0, /*Op*/1, /*SizeInBits*/0,
      GIM_CheckComplexPattern, /*MI*/0, /*Op*/1, /*Renderer*/GIMT_Encode2(0), GIMT_Encode2(GICP_gi_flat_scratch_saddr),
      // (st v4i32:{ *:[v4i32] }:$data, (ScratchSAddr:{ *:[iPTR] } SGPR_32:{ *:[i32] }:$saddr, i32:{ *:[i32] }:$offset))<<P:Predicate_unindexedstore>><<P:Predicate_store_private>>  =>  (SCRATCH_STORE_DWORDX4_SADDR anonymous_15034:{ *:[v4i32] }:$data, ?:{ *:[i32] }:$saddr, ?:{ *:[i32] }:$offset)
      GIR_BuildMI, /*InsnID*/0, /*Opcode*/GIMT_Encode2(AMDGPU::SCRATCH_STORE_DWORDX4_SADDR),
      GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/0, // data
      GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/0, // saddr
      GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/1, // offset
      GIR_AddImm8, /*InsnID*/0, /*Imm*/0,
      GIR_MergeMemOperands, /*InsnID*/0, /*NumInsns*/1, /*MergeInsnID's*/0,
      GIR_ConstrainSelectedInstOperands, /*InsnID*/0,
      GIR_EraseFromParent, /*InsnID*/0,
      // GIR_Coverage, 3549,
      GIR_Done,
    // Label 2320: @152700
    GIM_Try, /*On fail goto*//*Label 2321*/ GIMT_Encode4(152757), // Rule ID 3555 //
      GIM_CheckFeatures, GIMT_Encode2(GIFBS_EnableFlatScratch_HasFlatScratchInsts),
      GIM_CheckMemoryAddressSpace, /*MI*/0, /*MMO*/0, /*NumAddrSpace*/1, /*AddrSpace*/5,
      GIM_CheckAtomicOrdering, /*MI*/0, /*Order*/(uint8_t)AtomicOrdering::NotAtomic,
      GIM_CheckPointerToAny, /*MI*/0, /*Op*/1, /*SizeInBits*/0,
      GIM_CheckComplexPattern, /*MI*/0, /*Op*/1, /*Renderer*/GIMT_Encode2(0), GIMT_Encode2(GICP_gi_flat_scratch_saddr),
      // (st v4f32:{ *:[v4f32] }:$data, (ScratchSAddr:{ *:[iPTR] } SGPR_32:{ *:[i32] }:$saddr, i32:{ *:[i32] }:$offset))<<P:Predicate_unindexedstore>><<P:Predicate_store_private>>  =>  (SCRATCH_STORE_DWORDX4_SADDR anonymous_15034:{ *:[v4f32] }:$data, ?:{ *:[i32] }:$saddr, ?:{ *:[i32] }:$offset)
      GIR_BuildMI, /*InsnID*/0, /*Opcode*/GIMT_Encode2(AMDGPU::SCRATCH_STORE_DWORDX4_SADDR),
      GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/0, // data
      GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/0, // saddr
      GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/1, // offset
      GIR_AddImm8, /*InsnID*/0, /*Imm*/0,
      GIR_MergeMemOperands, /*InsnID*/0, /*NumInsns*/1, /*MergeInsnID's*/0,
      GIR_ConstrainSelectedInstOperands, /*InsnID*/0,
      GIR_EraseFromParent, /*InsnID*/0,
      // GIR_Coverage, 3555,
      GIR_Done,
    // Label 2321: @152757
    GIM_Try, /*On fail goto*//*Label 2322*/ GIMT_Encode4(152814), // Rule ID 3548 //
      GIM_CheckFeatures, GIMT_Encode2(GIFBS_EnableFlatScratch_HasFlatScratchInsts),
      GIM_CheckMemoryAddressSpace, /*MI*/0, /*MMO*/0, /*NumAddrSpace*/1, /*AddrSpace*/5,
      GIM_CheckAtomicOrdering, /*MI*/0, /*Order*/(uint8_t)AtomicOrdering::NotAtomic,
      GIM_CheckPointerToAny, /*MI*/0, /*Op*/1, /*SizeInBits*/0,
      GIM_CheckComplexPattern, /*MI*/0, /*Op*/1, /*Renderer*/GIMT_Encode2(0), GIMT_Encode2(GICP_gi_flat_scratch_offset),
      // (st v4i32:{ *:[v4i32] }:$data, (ScratchOffset:{ *:[iPTR] } VGPR_32:{ *:[i32] }:$vaddr, i32:{ *:[i32] }:$offset))<<P:Predicate_unindexedstore>><<P:Predicate_store_private>>  =>  (SCRATCH_STORE_DWORDX4 anonymous_15034:{ *:[v4i32] }:$data, ?:{ *:[i32] }:$vaddr, ?:{ *:[i32] }:$offset)
      GIR_BuildMI, /*InsnID*/0, /*Opcode*/GIMT_Encode2(AMDGPU::SCRATCH_STORE_DWORDX4),
      GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/0, // data
      GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/0, // vaddr
      GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/1, // offset
      GIR_AddImm8, /*InsnID*/0, /*Imm*/0,
      GIR_MergeMemOperands, /*InsnID*/0, /*NumInsns*/1, /*MergeInsnID's*/0,
      GIR_ConstrainSelectedInstOperands, /*InsnID*/0,
      GIR_EraseFromParent, /*InsnID*/0,
      // GIR_Coverage, 3548,
      GIR_Done,
    // Label 2322: @152814
    GIM_Try, /*On fail goto*//*Label 2323*/ GIMT_Encode4(152871), // Rule ID 3554 //
      GIM_CheckFeatures, GIMT_Encode2(GIFBS_EnableFlatScratch_HasFlatScratchInsts),
      GIM_CheckMemoryAddressSpace, /*MI*/0, /*MMO*/0, /*NumAddrSpace*/1, /*AddrSpace*/5,
      GIM_CheckAtomicOrdering, /*MI*/0, /*Order*/(uint8_t)AtomicOrdering::NotAtomic,
      GIM_CheckPointerToAny, /*MI*/0, /*Op*/1, /*SizeInBits*/0,
      GIM_CheckComplexPattern, /*MI*/0, /*Op*/1, /*Renderer*/GIMT_Encode2(0), GIMT_Encode2(GICP_gi_flat_scratch_offset),
      // (st v4f32:{ *:[v4f32] }:$data, (ScratchOffset:{ *:[iPTR] } VGPR_32:{ *:[i32] }:$vaddr, i32:{ *:[i32] }:$offset))<<P:Predicate_unindexedstore>><<P:Predicate_store_private>>  =>  (SCRATCH_STORE_DWORDX4 anonymous_15034:{ *:[v4f32] }:$data, ?:{ *:[i32] }:$vaddr, ?:{ *:[i32] }:$offset)
      GIR_BuildMI, /*InsnID*/0, /*Opcode*/GIMT_Encode2(AMDGPU::SCRATCH_STORE_DWORDX4),
      GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/0, // data
      GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/0, // vaddr
      GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/1, // offset
      GIR_AddImm8, /*InsnID*/0, /*Imm*/0,
      GIR_MergeMemOperands, /*InsnID*/0, /*NumInsns*/1, /*MergeInsnID's*/0,
      GIR_ConstrainSelectedInstOperands, /*InsnID*/0,
      GIR_EraseFromParent, /*InsnID*/0,
      // GIR_Coverage, 3554,
      GIR_Done,
    // Label 2323: @152871
    GIM_Try, /*On fail goto*//*Label 2324*/ GIMT_Encode4(152941), // Rule ID 3886 //
      GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasUnrestrictedSOffset),
      GIM_CheckMemoryAddressSpace, /*MI*/0, /*MMO*/0, /*NumAddrSpace*/1, /*AddrSpace*/1,
      GIM_CheckAtomicOrdering, /*MI*/0, /*Order*/(uint8_t)AtomicOrdering::NotAtomic,
      GIM_CheckPointerToAny, /*MI*/0, /*Op*/1, /*SizeInBits*/0,
      GIM_CheckComplexPattern, /*MI*/0, /*Op*/1, /*Renderer*/GIMT_Encode2(0), GIMT_Encode2(GICP_gi_mubuf_addr64),
      // (st v4i32:{ *:[v4i32] }:$vdata, (MUBUFAddr64:{ *:[iPTR] } v4i32:{ *:[v4i32] }:$srsrc, i64:{ *:[i64] }:$vaddr, i32:{ *:[i32] }:$soffset, i32:{ *:[i32] }:$offset))<<P:Predicate_unindexedstore>><<P:Predicate_store_global>>  =>  (BUFFER_STORE_DWORDX4_ADDR64 v4i32:{ *:[v4i32] }:$vdata, i64:{ *:[i64] }:$vaddr, v4i32:{ *:[v4i32] }:$srsrc, i32:{ *:[i32] }:$soffset, i32:{ *:[i32] }:$offset)
      GIR_BuildMI, /*InsnID*/0, /*Opcode*/GIMT_Encode2(AMDGPU::BUFFER_STORE_DWORDX4_ADDR64),
      GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/0, // vdata
      GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/1, // vaddr
      GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/0, // srsrc
      GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/2, // soffset
      GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/3, // offset
      GIR_AddImm8, /*InsnID*/0, /*Imm*/0,
      GIR_AddImm8, /*InsnID*/0, /*Imm*/0,
      GIR_MergeMemOperands, /*InsnID*/0, /*NumInsns*/1, /*MergeInsnID's*/0,
      GIR_ConstrainSelectedInstOperands, /*InsnID*/0,
      GIR_EraseFromParent, /*InsnID*/0,
      // GIR_Coverage, 3886,
      GIR_Done,
    // Label 2324: @152941
    GIM_Try, /*On fail goto*//*Label 2325*/ GIMT_Encode4(153008), // Rule ID 3888 //
      GIM_CheckMemoryAddressSpace, /*MI*/0, /*MMO*/0, /*NumAddrSpace*/1, /*AddrSpace*/1,
      GIM_CheckAtomicOrdering, /*MI*/0, /*Order*/(uint8_t)AtomicOrdering::NotAtomic,
      GIM_CheckPointerToAny, /*MI*/0, /*Op*/1, /*SizeInBits*/0,
      GIM_CheckComplexPattern, /*MI*/0, /*Op*/1, /*Renderer*/GIMT_Encode2(0), GIMT_Encode2(GICP_gi_mubuf_addr64),
      // (st v4i32:{ *:[v4i32] }:$vdata, (MUBUFAddr64:{ *:[iPTR] } v4i32:{ *:[v4i32] }:$srsrc, i64:{ *:[i64] }:$vaddr, i32:{ *:[i32] }:$soffset, i32:{ *:[i32] }:$offset))<<P:Predicate_unindexedstore>><<P:Predicate_store_global>>  =>  (BUFFER_STORE_DWORDX4_VBUFFER_ADDR64 v4i32:{ *:[v4i32] }:$vdata, i64:{ *:[i64] }:$vaddr, v4i32:{ *:[v4i32] }:$srsrc, i32:{ *:[i32] }:$soffset, i32:{ *:[i32] }:$offset)
      GIR_BuildMI, /*InsnID*/0, /*Opcode*/GIMT_Encode2(AMDGPU::BUFFER_STORE_DWORDX4_VBUFFER_ADDR64),
      GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/0, // vdata
      GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/1, // vaddr
      GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/0, // srsrc
      GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/2, // soffset
      GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/3, // offset
      GIR_AddImm8, /*InsnID*/0, /*Imm*/0,
      GIR_AddImm8, /*InsnID*/0, /*Imm*/0,
      GIR_MergeMemOperands, /*InsnID*/0, /*NumInsns*/1, /*MergeInsnID's*/0,
      GIR_ConstrainSelectedInstOperands, /*InsnID*/0,
      GIR_EraseFromParent, /*InsnID*/0,
      // GIR_Coverage, 3888,
      GIR_Done,
    // Label 2325: @153008
    GIM_Try, /*On fail goto*//*Label 2326*/ GIMT_Encode4(153078), // Rule ID 3890 //
      GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasUnrestrictedSOffset),
      GIM_CheckMemoryAddressSpace, /*MI*/0, /*MMO*/0, /*NumAddrSpace*/1, /*AddrSpace*/1,
      GIM_CheckAtomicOrdering, /*MI*/0, /*Order*/(uint8_t)AtomicOrdering::NotAtomic,
      GIM_CheckPointerToAny, /*MI*/0, /*Op*/1, /*SizeInBits*/0,
      GIM_CheckComplexPattern, /*MI*/0, /*Op*/1, /*Renderer*/GIMT_Encode2(0), GIMT_Encode2(GICP_gi_mubuf_addr64),
      // (st v4f32:{ *:[v4f32] }:$vdata, (MUBUFAddr64:{ *:[iPTR] } v4i32:{ *:[v4i32] }:$srsrc, i64:{ *:[i64] }:$vaddr, i32:{ *:[i32] }:$soffset, i32:{ *:[i32] }:$offset))<<P:Predicate_unindexedstore>><<P:Predicate_store_global>>  =>  (BUFFER_STORE_DWORDX4_ADDR64 v4f32:{ *:[v4f32] }:$vdata, i64:{ *:[i64] }:$vaddr, v4i32:{ *:[v4i32] }:$srsrc, i32:{ *:[i32] }:$soffset, i32:{ *:[i32] }:$offset)
      GIR_BuildMI, /*InsnID*/0, /*Opcode*/GIMT_Encode2(AMDGPU::BUFFER_STORE_DWORDX4_ADDR64),
      GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/0, // vdata
      GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/1, // vaddr
      GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/0, // srsrc
      GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/2, // soffset
      GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/3, // offset
      GIR_AddImm8, /*InsnID*/0, /*Imm*/0,
      GIR_AddImm8, /*InsnID*/0, /*Imm*/0,
      GIR_MergeMemOperands, /*InsnID*/0, /*NumInsns*/1, /*MergeInsnID's*/0,
      GIR_ConstrainSelectedInstOperands, /*InsnID*/0,
      GIR_EraseFromParent, /*InsnID*/0,
      // GIR_Coverage, 3890,
      GIR_Done,
    // Label 2326: @153078
    GIM_Try, /*On fail goto*//*Label 2327*/ GIMT_Encode4(153145), // Rule ID 3892 //
      GIM_CheckMemoryAddressSpace, /*MI*/0, /*MMO*/0, /*NumAddrSpace*/1, /*AddrSpace*/1,
      GIM_CheckAtomicOrdering, /*MI*/0, /*Order*/(uint8_t)AtomicOrdering::NotAtomic,
      GIM_CheckPointerToAny, /*MI*/0, /*Op*/1, /*SizeInBits*/0,
      GIM_CheckComplexPattern, /*MI*/0, /*Op*/1, /*Renderer*/GIMT_Encode2(0), GIMT_Encode2(GICP_gi_mubuf_addr64),
      // (st v4f32:{ *:[v4f32] }:$vdata, (MUBUFAddr64:{ *:[iPTR] } v4i32:{ *:[v4i32] }:$srsrc, i64:{ *:[i64] }:$vaddr, i32:{ *:[i32] }:$soffset, i32:{ *:[i32] }:$offset))<<P:Predicate_unindexedstore>><<P:Predicate_store_global>>  =>  (BUFFER_STORE_DWORDX4_VBUFFER_ADDR64 v4f32:{ *:[v4f32] }:$vdata, i64:{ *:[i64] }:$vaddr, v4i32:{ *:[v4i32] }:$srsrc, i32:{ *:[i32] }:$soffset, i32:{ *:[i32] }:$offset)
      GIR_BuildMI, /*InsnID*/0, /*Opcode*/GIMT_Encode2(AMDGPU::BUFFER_STORE_DWORDX4_VBUFFER_ADDR64),
      GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/0, // vdata
      GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/1, // vaddr
      GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/0, // srsrc
      GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/2, // soffset
      GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/3, // offset
      GIR_AddImm8, /*InsnID*/0, /*Imm*/0,
      GIR_AddImm8, /*InsnID*/0, /*Imm*/0,
      GIR_MergeMemOperands, /*InsnID*/0, /*NumInsns*/1, /*MergeInsnID's*/0,
      GIR_ConstrainSelectedInstOperands, /*InsnID*/0,
      GIR_EraseFromParent, /*InsnID*/0,
      // GIR_Coverage, 3892,
      GIR_Done,
    // Label 2327: @153145
    GIM_Try, /*On fail goto*//*Label 2328*/ GIMT_Encode4(153215), // Rule ID 5557 //
      GIM_CheckFeatures, GIMT_Encode2(GIFBS_DisableFlatScratch_HasUnrestrictedSOffset),
      GIM_CheckMemoryAddressSpace, /*MI*/0, /*MMO*/0, /*NumAddrSpace*/1, /*AddrSpace*/5,
      GIM_CheckAtomicOrdering, /*MI*/0, /*Order*/(uint8_t)AtomicOrdering::NotAtomic,
      GIM_CheckPointerToAny, /*MI*/0, /*Op*/1, /*SizeInBits*/0,
      GIM_CheckComplexPattern, /*MI*/0, /*Op*/1, /*Renderer*/GIMT_Encode2(0), GIMT_Encode2(GICP_gi_mubuf_scratch_offen),
      // (st v4i32:{ *:[v4i32] }:$value, (MUBUFScratchOffen:{ *:[iPTR] } v4i32:{ *:[v4i32] }:$srsrc, i32:{ *:[i32] }:$vaddr, i32:{ *:[i32] }:$soffset, i32:{ *:[i32] }:$offset))<<P:Predicate_unindexedstore>><<P:Predicate_store_private>>  =>  (BUFFER_STORE_DWORDX4_OFFEN VReg_128:{ *:[v4i32] }:$value, ?:{ *:[i32] }:$vaddr, ?:{ *:[v4i32] }:$srsrc, ?:{ *:[i32] }:$soffset, ?:{ *:[i32] }:$offset, 0:{ *:[i32] }, 0:{ *:[i1] })
      GIR_BuildMI, /*InsnID*/0, /*Opcode*/GIMT_Encode2(AMDGPU::BUFFER_STORE_DWORDX4_OFFEN),
      GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/0, // value
      GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/1, // vaddr
      GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/0, // srsrc
      GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/2, // soffset
      GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/3, // offset
      GIR_AddImm8, /*InsnID*/0, /*Imm*/0,
      GIR_AddImm8, /*InsnID*/0, /*Imm*/0,
      GIR_MergeMemOperands, /*InsnID*/0, /*NumInsns*/1, /*MergeInsnID's*/0,
      GIR_ConstrainSelectedInstOperands, /*InsnID*/0,
      GIR_EraseFromParent, /*InsnID*/0,
      // GIR_Coverage, 5557,
      GIR_Done,
    // Label 2328: @153215
    GIM_Try, /*On fail goto*//*Label 2329*/ GIMT_Encode4(153285), // Rule ID 5559 //
      GIM_CheckFeatures, GIMT_Encode2(GIFBS_DisableFlatScratch),
      GIM_CheckMemoryAddressSpace, /*MI*/0, /*MMO*/0, /*NumAddrSpace*/1, /*AddrSpace*/5,
      GIM_CheckAtomicOrdering, /*MI*/0, /*Order*/(uint8_t)AtomicOrdering::NotAtomic,
      GIM_CheckPointerToAny, /*MI*/0, /*Op*/1, /*SizeInBits*/0,
      GIM_CheckComplexPattern, /*MI*/0, /*Op*/1, /*Renderer*/GIMT_Encode2(0), GIMT_Encode2(GICP_gi_mubuf_scratch_offen),
      // (st v4i32:{ *:[v4i32] }:$value, (MUBUFScratchOffen:{ *:[iPTR] } v4i32:{ *:[v4i32] }:$srsrc, i32:{ *:[i32] }:$vaddr, i32:{ *:[i32] }:$soffset, i32:{ *:[i32] }:$offset))<<P:Predicate_unindexedstore>><<P:Predicate_store_private>>  =>  (BUFFER_STORE_DWORDX4_VBUFFER_OFFEN VReg_128:{ *:[v4i32] }:$value, ?:{ *:[i32] }:$vaddr, ?:{ *:[v4i32] }:$srsrc, ?:{ *:[i32] }:$soffset, ?:{ *:[i32] }:$offset, 0:{ *:[i32] }, 0:{ *:[i1] })
      GIR_BuildMI, /*InsnID*/0, /*Opcode*/GIMT_Encode2(AMDGPU::BUFFER_STORE_DWORDX4_VBUFFER_OFFEN),
      GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/0, // value
      GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/1, // vaddr
      GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/0, // srsrc
      GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/2, // soffset
      GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/3, // offset
      GIR_AddImm8, /*InsnID*/0, /*Imm*/0,
      GIR_AddImm8, /*InsnID*/0, /*Imm*/0,
      GIR_MergeMemOperands, /*InsnID*/0, /*NumInsns*/1, /*MergeInsnID's*/0,
      GIR_ConstrainSelectedInstOperands, /*InsnID*/0,
      GIR_EraseFromParent, /*InsnID*/0,
      // GIR_Coverage, 5559,
      GIR_Done,
    // Label 2329: @153285
    GIM_Try, /*On fail goto*//*Label 2330*/ GIMT_Encode4(153409), // Rule ID 6676 //
      GIM_CheckFeatures, GIMT_Encode2(GIFBS_LDSRequiresM0Init_isGFX7Plus),
      GIM_CheckMemorySizeEqualToLLT, /*MI*/0, /*MMO*/0, /*OpIdx*/0,
      GIM_CheckMemoryAddressSpace, /*MI*/0, /*MMO*/0, /*NumAddrSpace*/1, /*AddrSpace*/3,
      GIM_CheckAtomicOrdering, /*MI*/0, /*Order*/(uint8_t)AtomicOrdering::NotAtomic,
      GIM_CheckPointerToAny, /*MI*/0, /*Op*/1, /*SizeInBits*/0,
      GIM_CheckComplexPattern, /*MI*/0, /*Op*/1, /*Renderer*/GIMT_Encode2(0), GIMT_Encode2(GICP_gi_ds_128bit_8byte_aligned),
      // (AMDGPUst_glue v4i32:{ *:[v4i32] }:$value, (DS128Bit8ByteAligned:{ *:[iPTR] } i32:{ *:[i32] }:$ptr, i8:{ *:[i8] }:$offset0, i8:{ *:[i8] }:$offset1))<<P:Predicate_unindexedstore_glue>><<P:Predicate_store_glue>><<P:Predicate_store_local_m0>>  =>  (DS_WRITE2_B64 ?:{ *:[i32] }:$ptr, (EXTRACT_SUBREG:{ *:[i64] } VReg_128:{ *:[v4i32] }:$value, sub0_sub1:{ *:[i32] }), (EXTRACT_SUBREG:{ *:[i64] } VReg_128:{ *:[v4i32] }:$value, sub2_sub3:{ *:[i32] }), ?:{ *:[i8] }:$offset0, ?:{ *:[i8] }:$offset1, 0:{ *:[i1] })
      GIR_MakeTempReg, /*TempRegID*/0, /*TypeID*/GILLT_s64,
      GIR_MakeTempReg, /*TempRegID*/1, /*TypeID*/GILLT_s64,
      GIR_BuildMI, /*InsnID*/2, /*Opcode*/GIMT_Encode2(TargetOpcode::COPY),
      GIR_AddTempRegister, /*InsnID*/2, /*TempRegID*/1, /*TempRegFlags*/GIMT_Encode2(RegState::Define),
      GIR_CopySubReg, /*NewInsnID*/2, /*OldInsnID*/0, /*OpIdx*/0, /*SubRegIdx*/GIMT_Encode2(24), // value
      GIR_ConstrainOperandRC, /*InsnID*/2, /*Op*/0, GIMT_Encode2(AMDGPU::VReg_64RegClassID),
      GIR_ConstrainOperandRC, /*InsnID*/2, /*Op*/1, GIMT_Encode2(AMDGPU::VReg_128RegClassID),
      GIR_BuildMI, /*InsnID*/1, /*Opcode*/GIMT_Encode2(TargetOpcode::COPY),
      GIR_AddTempRegister, /*InsnID*/1, /*TempRegID*/0, /*TempRegFlags*/GIMT_Encode2(RegState::Define),
      GIR_CopySubReg, /*NewInsnID*/1, /*OldInsnID*/0, /*OpIdx*/0, /*SubRegIdx*/GIMT_Encode2(4), // value
      GIR_ConstrainOperandRC, /*InsnID*/1, /*Op*/0, GIMT_Encode2(AMDGPU::VReg_64RegClassID),
      GIR_ConstrainOperandRC, /*InsnID*/1, /*Op*/1, GIMT_Encode2(AMDGPU::VReg_128RegClassID),
      GIR_BuildMI, /*InsnID*/0, /*Opcode*/GIMT_Encode2(AMDGPU::DS_WRITE2_B64),
      GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/0, // ptr
      GIR_AddSimpleTempRegister, /*InsnID*/0, /*TempRegID*/0,
      GIR_AddSimpleTempRegister, /*InsnID*/0, /*TempRegID*/1,
      GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/1, // offset0
      GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/2, // offset1
      GIR_AddImm8, /*InsnID*/0, /*Imm*/0,
      GIR_MergeMemOperands, /*InsnID*/0, /*NumInsns*/1, /*MergeInsnID's*/0,
      GIR_ConstrainSelectedInstOperands, /*InsnID*/0,
      GIR_EraseFromParent, /*InsnID*/0,
      // GIR_Coverage, 6676,
      GIR_Done,
    // Label 2330: @153409
    GIM_Try, /*On fail goto*//*Label 2331*/ GIMT_Encode4(153533), // Rule ID 6716 //
      GIM_CheckFeatures, GIMT_Encode2(GIFBS_LDSRequiresM0Init_isGFX7Plus),
      GIM_CheckMemorySizeEqualToLLT, /*MI*/0, /*MMO*/0, /*OpIdx*/0,
      GIM_CheckMemoryAddressSpace, /*MI*/0, /*MMO*/0, /*NumAddrSpace*/1, /*AddrSpace*/3,
      GIM_CheckAtomicOrdering, /*MI*/0, /*Order*/(uint8_t)AtomicOrdering::NotAtomic,
      GIM_CheckPointerToAny, /*MI*/0, /*Op*/1, /*SizeInBits*/0,
      GIM_CheckComplexPattern, /*MI*/0, /*Op*/1, /*Renderer*/GIMT_Encode2(0), GIMT_Encode2(GICP_gi_ds_128bit_8byte_aligned),
      // (AMDGPUst_glue v4f32:{ *:[v4f32] }:$value, (DS128Bit8ByteAligned:{ *:[iPTR] } i32:{ *:[i32] }:$ptr, i8:{ *:[i8] }:$offset0, i8:{ *:[i8] }:$offset1))<<P:Predicate_unindexedstore_glue>><<P:Predicate_store_glue>><<P:Predicate_store_local_m0>>  =>  (DS_WRITE2_B64 ?:{ *:[i32] }:$ptr, (EXTRACT_SUBREG:{ *:[i64] } VReg_128:{ *:[v4f32] }:$value, sub0_sub1:{ *:[i32] }), (EXTRACT_SUBREG:{ *:[i64] } VReg_128:{ *:[v4f32] }:$value, sub2_sub3:{ *:[i32] }), ?:{ *:[i8] }:$offset0, ?:{ *:[i8] }:$offset1, 0:{ *:[i1] })
      GIR_MakeTempReg, /*TempRegID*/0, /*TypeID*/GILLT_s64,
      GIR_MakeTempReg, /*TempRegID*/1, /*TypeID*/GILLT_s64,
      GIR_BuildMI, /*InsnID*/2, /*Opcode*/GIMT_Encode2(TargetOpcode::COPY),
      GIR_AddTempRegister, /*InsnID*/2, /*TempRegID*/1, /*TempRegFlags*/GIMT_Encode2(RegState::Define),
      GIR_CopySubReg, /*NewInsnID*/2, /*OldInsnID*/0, /*OpIdx*/0, /*SubRegIdx*/GIMT_Encode2(24), // value
      GIR_ConstrainOperandRC, /*InsnID*/2, /*Op*/0, GIMT_Encode2(AMDGPU::VReg_64RegClassID),
      GIR_ConstrainOperandRC, /*InsnID*/2, /*Op*/1, GIMT_Encode2(AMDGPU::VReg_128RegClassID),
      GIR_BuildMI, /*InsnID*/1, /*Opcode*/GIMT_Encode2(TargetOpcode::COPY),
      GIR_AddTempRegister, /*InsnID*/1, /*TempRegID*/0, /*TempRegFlags*/GIMT_Encode2(RegState::Define),
      GIR_CopySubReg, /*NewInsnID*/1, /*OldInsnID*/0, /*OpIdx*/0, /*SubRegIdx*/GIMT_Encode2(4), // value
      GIR_ConstrainOperandRC, /*InsnID*/1, /*Op*/0, GIMT_Encode2(AMDGPU::VReg_64RegClassID),
      GIR_ConstrainOperandRC, /*InsnID*/1, /*Op*/1, GIMT_Encode2(AMDGPU::VReg_128RegClassID),
      GIR_BuildMI, /*InsnID*/0, /*Opcode*/GIMT_Encode2(AMDGPU::DS_WRITE2_B64),
      GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/0, // ptr
      GIR_AddSimpleTempRegister, /*InsnID*/0, /*TempRegID*/0,
      GIR_AddSimpleTempRegister, /*InsnID*/0, /*TempRegID*/1,
      GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/1, // offset0
      GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/2, // offset1
      GIR_AddImm8, /*InsnID*/0, /*Imm*/0,
      GIR_MergeMemOperands, /*InsnID*/0, /*NumInsns*/1, /*MergeInsnID's*/0,
      GIR_ConstrainSelectedInstOperands, /*InsnID*/0,
      GIR_EraseFromParent, /*InsnID*/0,
      // GIR_Coverage, 6716,
      GIR_Done,
    // Label 2331: @153533
    GIM_Try, /*On fail goto*//*Label 2332*/ GIMT_Encode4(153598), // Rule ID 3885 //
      GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasUnrestrictedSOffset),
      GIM_CheckMemoryAddressSpace, /*MI*/0, /*MMO*/0, /*NumAddrSpace*/1, /*AddrSpace*/1,
      GIM_CheckAtomicOrdering, /*MI*/0, /*Order*/(uint8_t)AtomicOrdering::NotAtomic,
      GIM_CheckPointerToAny, /*MI*/0, /*Op*/1, /*SizeInBits*/0,
      GIM_CheckComplexPattern, /*MI*/0, /*Op*/1, /*Renderer*/GIMT_Encode2(0), GIMT_Encode2(GICP_gi_mubuf_offset),
      // (st v4i32:{ *:[v4i32] }:$vdata, (MUBUFOffset:{ *:[iPTR] } v4i32:{ *:[v4i32] }:$srsrc, i32:{ *:[i32] }:$soffset, i32:{ *:[i32] }:$offset))<<P:Predicate_unindexedstore>><<P:Predicate_store_global>>  =>  (BUFFER_STORE_DWORDX4_OFFSET v4i32:{ *:[v4i32] }:$vdata, v4i32:{ *:[v4i32] }:$srsrc, i32:{ *:[i32] }:$soffset, i32:{ *:[i32] }:$offset)
      GIR_BuildMI, /*InsnID*/0, /*Opcode*/GIMT_Encode2(AMDGPU::BUFFER_STORE_DWORDX4_OFFSET),
      GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/0, // vdata
      GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/0, // srsrc
      GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/1, // soffset
      GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/2, // offset
      GIR_AddImm8, /*InsnID*/0, /*Imm*/0,
      GIR_AddImm8, /*InsnID*/0, /*Imm*/0,
      GIR_MergeMemOperands, /*InsnID*/0, /*NumInsns*/1, /*MergeInsnID's*/0,
      GIR_ConstrainSelectedInstOperands, /*InsnID*/0,
      GIR_EraseFromParent, /*InsnID*/0,
      // GIR_Coverage, 3885,
      GIR_Done,
    // Label 2332: @153598
    GIM_Try, /*On fail goto*//*Label 2333*/ GIMT_Encode4(153660), // Rule ID 3887 //
      GIM_CheckMemoryAddressSpace, /*MI*/0, /*MMO*/0, /*NumAddrSpace*/1, /*AddrSpace*/1,
      GIM_CheckAtomicOrdering, /*MI*/0, /*Order*/(uint8_t)AtomicOrdering::NotAtomic,
      GIM_CheckPointerToAny, /*MI*/0, /*Op*/1, /*SizeInBits*/0,
      GIM_CheckComplexPattern, /*MI*/0, /*Op*/1, /*Renderer*/GIMT_Encode2(0), GIMT_Encode2(GICP_gi_mubuf_offset),
      // (st v4i32:{ *:[v4i32] }:$vdata, (MUBUFOffset:{ *:[iPTR] } v4i32:{ *:[v4i32] }:$srsrc, i32:{ *:[i32] }:$soffset, i32:{ *:[i32] }:$offset))<<P:Predicate_unindexedstore>><<P:Predicate_store_global>>  =>  (BUFFER_STORE_DWORDX4_VBUFFER_OFFSET v4i32:{ *:[v4i32] }:$vdata, v4i32:{ *:[v4i32] }:$srsrc, i32:{ *:[i32] }:$soffset, i32:{ *:[i32] }:$offset)
      GIR_BuildMI, /*InsnID*/0, /*Opcode*/GIMT_Encode2(AMDGPU::BUFFER_STORE_DWORDX4_VBUFFER_OFFSET),
      GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/0, // vdata
      GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/0, // srsrc
      GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/1, // soffset
      GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/2, // offset
      GIR_AddImm8, /*InsnID*/0, /*Imm*/0,
      GIR_AddImm8, /*InsnID*/0, /*Imm*/0,
      GIR_MergeMemOperands, /*InsnID*/0, /*NumInsns*/1, /*MergeInsnID's*/0,
      GIR_ConstrainSelectedInstOperands, /*InsnID*/0,
      GIR_EraseFromParent, /*InsnID*/0,
      // GIR_Coverage, 3887,
      GIR_Done,
    // Label 2333: @153660
    GIM_Try, /*On fail goto*//*Label 2334*/ GIMT_Encode4(153725), // Rule ID 3889 //
      GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasUnrestrictedSOffset),
      GIM_CheckMemoryAddressSpace, /*MI*/0, /*MMO*/0, /*NumAddrSpace*/1, /*AddrSpace*/1,
      GIM_CheckAtomicOrdering, /*MI*/0, /*Order*/(uint8_t)AtomicOrdering::NotAtomic,
      GIM_CheckPointerToAny, /*MI*/0, /*Op*/1, /*SizeInBits*/0,
      GIM_CheckComplexPattern, /*MI*/0, /*Op*/1, /*Renderer*/GIMT_Encode2(0), GIMT_Encode2(GICP_gi_mubuf_offset),
      // (st v4f32:{ *:[v4f32] }:$vdata, (MUBUFOffset:{ *:[iPTR] } v4i32:{ *:[v4i32] }:$srsrc, i32:{ *:[i32] }:$soffset, i32:{ *:[i32] }:$offset))<<P:Predicate_unindexedstore>><<P:Predicate_store_global>>  =>  (BUFFER_STORE_DWORDX4_OFFSET v4f32:{ *:[v4f32] }:$vdata, v4i32:{ *:[v4i32] }:$srsrc, i32:{ *:[i32] }:$soffset, i32:{ *:[i32] }:$offset)
      GIR_BuildMI, /*InsnID*/0, /*Opcode*/GIMT_Encode2(AMDGPU::BUFFER_STORE_DWORDX4_OFFSET),
      GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/0, // vdata
      GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/0, // srsrc
      GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/1, // soffset
      GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/2, // offset
      GIR_AddImm8, /*InsnID*/0, /*Imm*/0,
      GIR_AddImm8, /*InsnID*/0, /*Imm*/0,
      GIR_MergeMemOperands, /*InsnID*/0, /*NumInsns*/1, /*MergeInsnID's*/0,
      GIR_ConstrainSelectedInstOperands, /*InsnID*/0,
      GIR_EraseFromParent, /*InsnID*/0,
      // GIR_Coverage, 3889,
      GIR_Done,
    // Label 2334: @153725
    GIM_Try, /*On fail goto*//*Label 2335*/ GIMT_Encode4(153787), // Rule ID 3891 //
      GIM_CheckMemoryAddressSpace, /*MI*/0, /*MMO*/0, /*NumAddrSpace*/1, /*AddrSpace*/1,
      GIM_CheckAtomicOrdering, /*MI*/0, /*Order*/(uint8_t)AtomicOrdering::NotAtomic,
      GIM_CheckPointerToAny, /*MI*/0, /*Op*/1, /*SizeInBits*/0,
      GIM_CheckComplexPattern, /*MI*/0, /*Op*/1, /*Renderer*/GIMT_Encode2(0), GIMT_Encode2(GICP_gi_mubuf_offset),
      // (st v4f32:{ *:[v4f32] }:$vdata, (MUBUFOffset:{ *:[iPTR] } v4i32:{ *:[v4i32] }:$srsrc, i32:{ *:[i32] }:$soffset, i32:{ *:[i32] }:$offset))<<P:Predicate_unindexedstore>><<P:Predicate_store_global>>  =>  (BUFFER_STORE_DWORDX4_VBUFFER_OFFSET v4f32:{ *:[v4f32] }:$vdata, v4i32:{ *:[v4i32] }:$srsrc, i32:{ *:[i32] }:$soffset, i32:{ *:[i32] }:$offset)
      GIR_BuildMI, /*InsnID*/0, /*Opcode*/GIMT_Encode2(AMDGPU::BUFFER_STORE_DWORDX4_VBUFFER_OFFSET),
      GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/0, // vdata
      GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/0, // srsrc
      GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/1, // soffset
      GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/2, // offset
      GIR_AddImm8, /*InsnID*/0, /*Imm*/0,
      GIR_AddImm8, /*InsnID*/0, /*Imm*/0,
      GIR_MergeMemOperands, /*InsnID*/0, /*NumInsns*/1, /*MergeInsnID's*/0,
      GIR_ConstrainSelectedInstOperands, /*InsnID*/0,
      GIR_EraseFromParent, /*InsnID*/0,
      // GIR_Coverage, 3891,
      GIR_Done,
    // Label 2335: @153787
    GIM_Try, /*On fail goto*//*Label 2336*/ GIMT_Encode4(153907), // Rule ID 6678 //
      GIM_CheckFeatures, GIMT_Encode2(GIFBS_NotLDSRequiresM0Init),
      GIM_CheckMemoryAddressSpace, /*MI*/0, /*MMO*/0, /*NumAddrSpace*/1, /*AddrSpace*/3,
      GIM_CheckAtomicOrdering, /*MI*/0, /*Order*/(uint8_t)AtomicOrdering::NotAtomic,
      GIM_CheckPointerToAny, /*MI*/0, /*Op*/1, /*SizeInBits*/0,
      GIM_CheckComplexPattern, /*MI*/0, /*Op*/1, /*Renderer*/GIMT_Encode2(0), GIMT_Encode2(GICP_gi_ds_128bit_8byte_aligned),
      // (st v4i32:{ *:[v4i32] }:$value, (DS128Bit8ByteAligned:{ *:[iPTR] } i32:{ *:[i32] }:$ptr, i8:{ *:[i8] }:$offset0, i8:{ *:[i8] }:$offset1))<<P:Predicate_unindexedstore>><<P:Predicate_store_local>>  =>  (DS_WRITE2_B64_gfx9 ?:{ *:[i32] }:$ptr, (EXTRACT_SUBREG:{ *:[i64] } VReg_128:{ *:[v4i32] }:$value, sub0_sub1:{ *:[i32] }), (EXTRACT_SUBREG:{ *:[i64] } VReg_128:{ *:[v4i32] }:$value, sub2_sub3:{ *:[i32] }), ?:{ *:[i8] }:$offset0, ?:{ *:[i8] }:$offset1, 0:{ *:[i1] })
      GIR_MakeTempReg, /*TempRegID*/0, /*TypeID*/GILLT_s64,
      GIR_MakeTempReg, /*TempRegID*/1, /*TypeID*/GILLT_s64,
      GIR_BuildMI, /*InsnID*/2, /*Opcode*/GIMT_Encode2(TargetOpcode::COPY),
      GIR_AddTempRegister, /*InsnID*/2, /*TempRegID*/1, /*TempRegFlags*/GIMT_Encode2(RegState::Define),
      GIR_CopySubReg, /*NewInsnID*/2, /*OldInsnID*/0, /*OpIdx*/0, /*SubRegIdx*/GIMT_Encode2(24), // value
      GIR_ConstrainOperandRC, /*InsnID*/2, /*Op*/0, GIMT_Encode2(AMDGPU::VReg_64RegClassID),
      GIR_ConstrainOperandRC, /*InsnID*/2, /*Op*/1, GIMT_Encode2(AMDGPU::VReg_128RegClassID),
      GIR_BuildMI, /*InsnID*/1, /*Opcode*/GIMT_Encode2(TargetOpcode::COPY),
      GIR_AddTempRegister, /*InsnID*/1, /*TempRegID*/0, /*TempRegFlags*/GIMT_Encode2(RegState::Define),
      GIR_CopySubReg, /*NewInsnID*/1, /*OldInsnID*/0, /*OpIdx*/0, /*SubRegIdx*/GIMT_Encode2(4), // value
      GIR_ConstrainOperandRC, /*InsnID*/1, /*Op*/0, GIMT_Encode2(AMDGPU::VReg_64RegClassID),
      GIR_ConstrainOperandRC, /*InsnID*/1, /*Op*/1, GIMT_Encode2(AMDGPU::VReg_128RegClassID),
      GIR_BuildMI, /*InsnID*/0, /*Opcode*/GIMT_Encode2(AMDGPU::DS_WRITE2_B64_gfx9),
      GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/0, // ptr
      GIR_AddSimpleTempRegister, /*InsnID*/0, /*TempRegID*/0,
      GIR_AddSimpleTempRegister, /*InsnID*/0, /*TempRegID*/1,
      GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/1, // offset0
      GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/2, // offset1
      GIR_AddImm8, /*InsnID*/0, /*Imm*/0,
      GIR_MergeMemOperands, /*InsnID*/0, /*NumInsns*/1, /*MergeInsnID's*/0,
      GIR_ConstrainSelectedInstOperands, /*InsnID*/0,
      GIR_EraseFromParent, /*InsnID*/0,
      // GIR_Coverage, 6678,
      GIR_Done,
    // Label 2336: @153907
    GIM_Try, /*On fail goto*//*Label 2337*/ GIMT_Encode4(154027), // Rule ID 6718 //
      GIM_CheckFeatures, GIMT_Encode2(GIFBS_NotLDSRequiresM0Init),
      GIM_CheckMemoryAddressSpace, /*MI*/0, /*MMO*/0, /*NumAddrSpace*/1, /*AddrSpace*/3,
      GIM_CheckAtomicOrdering, /*MI*/0, /*Order*/(uint8_t)AtomicOrdering::NotAtomic,
      GIM_CheckPointerToAny, /*MI*/0, /*Op*/1, /*SizeInBits*/0,
      GIM_CheckComplexPattern, /*MI*/0, /*Op*/1, /*Renderer*/GIMT_Encode2(0), GIMT_Encode2(GICP_gi_ds_128bit_8byte_aligned),
      // (st v4f32:{ *:[v4f32] }:$value, (DS128Bit8ByteAligned:{ *:[iPTR] } i32:{ *:[i32] }:$ptr, i8:{ *:[i8] }:$offset0, i8:{ *:[i8] }:$offset1))<<P:Predicate_unindexedstore>><<P:Predicate_store_local>>  =>  (DS_WRITE2_B64_gfx9 ?:{ *:[i32] }:$ptr, (EXTRACT_SUBREG:{ *:[i64] } VReg_128:{ *:[v4f32] }:$value, sub0_sub1:{ *:[i32] }), (EXTRACT_SUBREG:{ *:[i64] } VReg_128:{ *:[v4f32] }:$value, sub2_sub3:{ *:[i32] }), ?:{ *:[i8] }:$offset0, ?:{ *:[i8] }:$offset1, 0:{ *:[i1] })
      GIR_MakeTempReg, /*TempRegID*/0, /*TypeID*/GILLT_s64,
      GIR_MakeTempReg, /*TempRegID*/1, /*TypeID*/GILLT_s64,
      GIR_BuildMI, /*InsnID*/2, /*Opcode*/GIMT_Encode2(TargetOpcode::COPY),
      GIR_AddTempRegister, /*InsnID*/2, /*TempRegID*/1, /*TempRegFlags*/GIMT_Encode2(RegState::Define),
      GIR_CopySubReg, /*NewInsnID*/2, /*OldInsnID*/0, /*OpIdx*/0, /*SubRegIdx*/GIMT_Encode2(24), // value
      GIR_ConstrainOperandRC, /*InsnID*/2, /*Op*/0, GIMT_Encode2(AMDGPU::VReg_64RegClassID),
      GIR_ConstrainOperandRC, /*InsnID*/2, /*Op*/1, GIMT_Encode2(AMDGPU::VReg_128RegClassID),
      GIR_BuildMI, /*InsnID*/1, /*Opcode*/GIMT_Encode2(TargetOpcode::COPY),
      GIR_AddTempRegister, /*InsnID*/1, /*TempRegID*/0, /*TempRegFlags*/GIMT_Encode2(RegState::Define),
      GIR_CopySubReg, /*NewInsnID*/1, /*OldInsnID*/0, /*OpIdx*/0, /*SubRegIdx*/GIMT_Encode2(4), // value
      GIR_ConstrainOperandRC, /*InsnID*/1, /*Op*/0, GIMT_Encode2(AMDGPU::VReg_64RegClassID),
      GIR_ConstrainOperandRC, /*InsnID*/1, /*Op*/1, GIMT_Encode2(AMDGPU::VReg_128RegClassID),
      GIR_BuildMI, /*InsnID*/0, /*Opcode*/GIMT_Encode2(AMDGPU::DS_WRITE2_B64_gfx9),
      GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/0, // ptr
      GIR_AddSimpleTempRegister, /*InsnID*/0, /*TempRegID*/0,
      GIR_AddSimpleTempRegister, /*InsnID*/0, /*TempRegID*/1,
      GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/1, // offset0
      GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/2, // offset1
      GIR_AddImm8, /*InsnID*/0, /*Imm*/0,
      GIR_MergeMemOperands, /*InsnID*/0, /*NumInsns*/1, /*MergeInsnID's*/0,
      GIR_ConstrainSelectedInstOperands, /*InsnID*/0,
      GIR_EraseFromParent, /*InsnID*/0,
      // GIR_Coverage, 6718,
      GIR_Done,
    // Label 2337: @154027
    GIM_Try, /*On fail goto*//*Label 2338*/ GIMT_Encode4(154089), // Rule ID 3073 //
      GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasFlatGlobalInsts),
      GIM_CheckMemoryAddressSpace, /*MI*/0, /*MMO*/0, /*NumAddrSpace*/1, /*AddrSpace*/1,
      GIM_CheckAtomicOrdering, /*MI*/0, /*Order*/(uint8_t)AtomicOrdering::NotAtomic,
      GIM_CheckPointerToAny, /*MI*/0, /*Op*/1, /*SizeInBits*/0,
      GIM_CheckComplexPattern, /*MI*/0, /*Op*/1, /*Renderer*/GIMT_Encode2(0), GIMT_Encode2(GICP_gi_global_saddr),
      // (st v4i32:{ *:[v4i32] }:$data, (GlobalSAddr:{ *:[iPTR] } SReg_64:{ *:[i64] }:$saddr, VGPR_32:{ *:[i32] }:$voffset, i32:{ *:[i32] }:$offset))<<P:Predicate_unindexedstore>><<P:Predicate_store_global>>  =>  (GLOBAL_STORE_DWORDX4_SADDR ?:{ *:[i32] }:$voffset, anonymous_15034:{ *:[v4i32] }:$data, ?:{ *:[i64] }:$saddr, ?:{ *:[i32] }:$offset)
      GIR_BuildMI, /*InsnID*/0, /*Opcode*/GIMT_Encode2(AMDGPU::GLOBAL_STORE_DWORDX4_SADDR),
      GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/1, // voffset
      GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/0, // data
      GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/0, // saddr
      GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/2, // offset
      GIR_AddImm8, /*InsnID*/0, /*Imm*/0,
      GIR_MergeMemOperands, /*InsnID*/0, /*NumInsns*/1, /*MergeInsnID's*/0,
      GIR_ConstrainSelectedInstOperands, /*InsnID*/0,
      GIR_EraseFromParent, /*InsnID*/0,
      // GIR_Coverage, 3073,
      GIR_Done,
    // Label 2338: @154089
    GIM_Try, /*On fail goto*//*Label 2339*/ GIMT_Encode4(154151), // Rule ID 3077 //
      GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasFlatGlobalInsts),
      GIM_CheckMemoryAddressSpace, /*MI*/0, /*MMO*/0, /*NumAddrSpace*/1, /*AddrSpace*/1,
      GIM_CheckAtomicOrdering, /*MI*/0, /*Order*/(uint8_t)AtomicOrdering::NotAtomic,
      GIM_CheckPointerToAny, /*MI*/0, /*Op*/1, /*SizeInBits*/0,
      GIM_CheckComplexPattern, /*MI*/0, /*Op*/1, /*Renderer*/GIMT_Encode2(0), GIMT_Encode2(GICP_gi_global_saddr),
      // (st v4f32:{ *:[v4f32] }:$data, (GlobalSAddr:{ *:[iPTR] } SReg_64:{ *:[i64] }:$saddr, VGPR_32:{ *:[i32] }:$voffset, i32:{ *:[i32] }:$offset))<<P:Predicate_unindexedstore>><<P:Predicate_store_global>>  =>  (GLOBAL_STORE_DWORDX4_SADDR ?:{ *:[i32] }:$voffset, anonymous_15034:{ *:[v4f32] }:$data, ?:{ *:[i64] }:$saddr, ?:{ *:[i32] }:$offset)
      GIR_BuildMI, /*InsnID*/0, /*Opcode*/GIMT_Encode2(AMDGPU::GLOBAL_STORE_DWORDX4_SADDR),
      GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/1, // voffset
      GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/0, // data
      GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/0, // saddr
      GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/2, // offset
      GIR_AddImm8, /*InsnID*/0, /*Imm*/0,
      GIR_MergeMemOperands, /*InsnID*/0, /*NumInsns*/1, /*MergeInsnID's*/0,
      GIR_ConstrainSelectedInstOperands, /*InsnID*/0,
      GIR_EraseFromParent, /*InsnID*/0,
      // GIR_Coverage, 3077,
      GIR_Done,
    // Label 2339: @154151
    GIM_Try, /*On fail goto*//*Label 2340*/ GIMT_Encode4(154208), // Rule ID 3072 //
      GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasFlatGlobalInsts),
      GIM_CheckMemoryAddressSpace, /*MI*/0, /*MMO*/0, /*NumAddrSpace*/1, /*AddrSpace*/1,
      GIM_CheckAtomicOrdering, /*MI*/0, /*Order*/(uint8_t)AtomicOrdering::NotAtomic,
      GIM_CheckPointerToAny, /*MI*/0, /*Op*/1, /*SizeInBits*/0,
      GIM_CheckComplexPattern, /*MI*/0, /*Op*/1, /*Renderer*/GIMT_Encode2(0), GIMT_Encode2(GICP_gi_global_offset),
      // (st v4i32:{ *:[v4i32] }:$data, (GlobalOffset:{ *:[iPTR] } i64:{ *:[i64] }:$vaddr, i32:{ *:[i32] }:$offset))<<P:Predicate_unindexedstore>><<P:Predicate_store_global>>  =>  (GLOBAL_STORE_DWORDX4 ?:{ *:[i64] }:$vaddr, anonymous_15034:{ *:[v4i32] }:$data, ?:{ *:[i32] }:$offset)
      GIR_BuildMI, /*InsnID*/0, /*Opcode*/GIMT_Encode2(AMDGPU::GLOBAL_STORE_DWORDX4),
      GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/0, // vaddr
      GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/0, // data
      GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/1, // offset
      GIR_AddImm8, /*InsnID*/0, /*Imm*/0,
      GIR_MergeMemOperands, /*InsnID*/0, /*NumInsns*/1, /*MergeInsnID's*/0,
      GIR_ConstrainSelectedInstOperands, /*InsnID*/0,
      GIR_EraseFromParent, /*InsnID*/0,
      // GIR_Coverage, 3072,
      GIR_Done,
    // Label 2340: @154208
    GIM_Try, /*On fail goto*//*Label 2341*/ GIMT_Encode4(154265), // Rule ID 3076 //
      GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasFlatGlobalInsts),
      GIM_CheckMemoryAddressSpace, /*MI*/0, /*MMO*/0, /*NumAddrSpace*/1, /*AddrSpace*/1,
      GIM_CheckAtomicOrdering, /*MI*/0, /*Order*/(uint8_t)AtomicOrdering::NotAtomic,
      GIM_CheckPointerToAny, /*MI*/0, /*Op*/1, /*SizeInBits*/0,
      GIM_CheckComplexPattern, /*MI*/0, /*Op*/1, /*Renderer*/GIMT_Encode2(0), GIMT_Encode2(GICP_gi_global_offset),
      // (st v4f32:{ *:[v4f32] }:$data, (GlobalOffset:{ *:[iPTR] } i64:{ *:[i64] }:$vaddr, i32:{ *:[i32] }:$offset))<<P:Predicate_unindexedstore>><<P:Predicate_store_global>>  =>  (GLOBAL_STORE_DWORDX4 ?:{ *:[i64] }:$vaddr, anonymous_15034:{ *:[v4f32] }:$data, ?:{ *:[i32] }:$offset)
      GIR_BuildMI, /*InsnID*/0, /*Opcode*/GIMT_Encode2(AMDGPU::GLOBAL_STORE_DWORDX4),
      GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/0, // vaddr
      GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/0, // data
      GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/1, // offset
      GIR_AddImm8, /*InsnID*/0, /*Imm*/0,
      GIR_MergeMemOperands, /*InsnID*/0, /*NumInsns*/1, /*MergeInsnID's*/0,
      GIR_ConstrainSelectedInstOperands, /*InsnID*/0,
      GIR_EraseFromParent, /*InsnID*/0,
      // GIR_Coverage, 3076,
      GIR_Done,
    // Label 2341: @154265
    GIM_Try, /*On fail goto*//*Label 2342*/ GIMT_Encode4(154323), // Rule ID 2810 //
      GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasFlatAddressSpace),
      GIM_CheckMemoryAddressSpace, /*MI*/0, /*MMO*/0, /*NumAddrSpace*/2, /*AddrSpace*/0, /*AddrSpace*/1,
      GIM_CheckAtomicOrdering, /*MI*/0, /*Order*/(uint8_t)AtomicOrdering::NotAtomic,
      GIM_CheckPointerToAny, /*MI*/0, /*Op*/1, /*SizeInBits*/0,
      GIM_CheckComplexPattern, /*MI*/0, /*Op*/1, /*Renderer*/GIMT_Encode2(0), GIMT_Encode2(GICP_gi_flat_offset),
      // (st v4i32:{ *:[v4i32] }:$data, (FlatOffset:{ *:[iPTR] } i64:{ *:[i64] }:$vaddr, i32:{ *:[i32] }:$offset))<<P:Predicate_unindexedstore>><<P:Predicate_store_flat>>  =>  (FLAT_STORE_DWORDX4 ?:{ *:[i64] }:$vaddr, anonymous_15034:{ *:[v4i32] }:$data, ?:{ *:[i32] }:$offset)
      GIR_BuildMI, /*InsnID*/0, /*Opcode*/GIMT_Encode2(AMDGPU::FLAT_STORE_DWORDX4),
      GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/0, // vaddr
      GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/0, // data
      GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/1, // offset
      GIR_AddImm8, /*InsnID*/0, /*Imm*/0,
      GIR_MergeMemOperands, /*InsnID*/0, /*NumInsns*/1, /*MergeInsnID's*/0,
      GIR_ConstrainSelectedInstOperands, /*InsnID*/0,
      GIR_EraseFromParent, /*InsnID*/0,
      // GIR_Coverage, 2810,
      GIR_Done,
    // Label 2342: @154323
    GIM_Try, /*On fail goto*//*Label 2343*/ GIMT_Encode4(154381), // Rule ID 2812 //
      GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasFlatAddressSpace),
      GIM_CheckMemoryAddressSpace, /*MI*/0, /*MMO*/0, /*NumAddrSpace*/2, /*AddrSpace*/0, /*AddrSpace*/1,
      GIM_CheckAtomicOrdering, /*MI*/0, /*Order*/(uint8_t)AtomicOrdering::NotAtomic,
      GIM_CheckPointerToAny, /*MI*/0, /*Op*/1, /*SizeInBits*/0,
      GIM_CheckComplexPattern, /*MI*/0, /*Op*/1, /*Renderer*/GIMT_Encode2(0), GIMT_Encode2(GICP_gi_flat_offset),
      // (st v4f32:{ *:[v4f32] }:$data, (FlatOffset:{ *:[iPTR] } i64:{ *:[i64] }:$vaddr, i32:{ *:[i32] }:$offset))<<P:Predicate_unindexedstore>><<P:Predicate_store_flat>>  =>  (FLAT_STORE_DWORDX4 ?:{ *:[i64] }:$vaddr, anonymous_15034:{ *:[v4f32] }:$data, ?:{ *:[i32] }:$offset)
      GIR_BuildMI, /*InsnID*/0, /*Opcode*/GIMT_Encode2(AMDGPU::FLAT_STORE_DWORDX4),
      GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/0, // vaddr
      GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/0, // data
      GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/1, // offset
      GIR_AddImm8, /*InsnID*/0, /*Imm*/0,
      GIR_MergeMemOperands, /*InsnID*/0, /*NumInsns*/1, /*MergeInsnID's*/0,
      GIR_ConstrainSelectedInstOperands, /*InsnID*/0,
      GIR_EraseFromParent, /*InsnID*/0,
      // GIR_Coverage, 2812,
      GIR_Done,
    // Label 2343: @154381
    GIM_Reject,
    // Label 1822: @154382
    GIM_Try, /*On fail goto*//*Label 2344*/ GIMT_Encode4(154452), // Rule ID 6881 //
      GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasUnalignedAccessMode_LDSRequiresM0Init),
      GIM_CheckMemorySizeEqualToLLT, /*MI*/0, /*MMO*/0, /*OpIdx*/0,
      GIM_CheckMemoryAddressSpace, /*MI*/0, /*MMO*/0, /*NumAddrSpace*/1, /*AddrSpace*/3,
      GIM_CheckMemoryAddressSpace, /*MI*/0, /*MMO*/0, /*NumAddrSpace*/1, /*AddrSpace*/3,
      GIM_CheckAtomicOrdering, /*MI*/0, /*Order*/(uint8_t)AtomicOrdering::NotAtomic,
      GIM_CheckPointerToAny, /*MI*/0, /*Op*/1, /*SizeInBits*/0,
      GIM_CheckCxxInsnPredicate, /*MI*/0, /*FnId*/GIMT_Encode2(GICXXPred_MI_Predicate_store_align_less_than_4_local_m0),
      GIM_CheckComplexPattern, /*MI*/0, /*Op*/1, /*Renderer*/GIMT_Encode2(0), GIMT_Encode2(GICP_gi_ds_1addr_1offset),
      // (AMDGPUst_glue v8i16:{ *:[v8i16] }:$value, (DS1Addr1Offset:{ *:[iPTR] } i32:{ *:[i32] }:$ptr, i32:{ *:[i32] }:$offset))<<P:Predicate_unindexedstore_glue>><<P:Predicate_store_glue>><<P:Predicate_store_local_m0>><<P:Predicate_store_align_less_than_4_local_m0>>  =>  (DS_WRITE_B128 ?:{ *:[i32] }:$ptr, anonymous_15034:{ *:[v8i16] }:$value, offset:{ *:[i32] }:$offset, 0:{ *:[i1] })
      GIR_BuildMI, /*InsnID*/0, /*Opcode*/GIMT_Encode2(AMDGPU::DS_WRITE_B128),
      GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/0, // ptr
      GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/0, // value
      GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/1, // offset
      GIR_AddImm8, /*InsnID*/0, /*Imm*/0,
      GIR_MergeMemOperands, /*InsnID*/0, /*NumInsns*/1, /*MergeInsnID's*/0,
      GIR_ConstrainSelectedInstOperands, /*InsnID*/0,
      GIR_EraseFromParent, /*InsnID*/0,
      // GIR_Coverage, 6881,
      GIR_Done,
    // Label 2344: @154452
    GIM_Try, /*On fail goto*//*Label 2345*/ GIMT_Encode4(154522), // Rule ID 6885 //
      GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasUnalignedAccessMode_LDSRequiresM0Init),
      GIM_CheckMemorySizeEqualToLLT, /*MI*/0, /*MMO*/0, /*OpIdx*/0,
      GIM_CheckMemoryAddressSpace, /*MI*/0, /*MMO*/0, /*NumAddrSpace*/1, /*AddrSpace*/3,
      GIM_CheckMemoryAddressSpace, /*MI*/0, /*MMO*/0, /*NumAddrSpace*/1, /*AddrSpace*/3,
      GIM_CheckAtomicOrdering, /*MI*/0, /*Order*/(uint8_t)AtomicOrdering::NotAtomic,
      GIM_CheckPointerToAny, /*MI*/0, /*Op*/1, /*SizeInBits*/0,
      GIM_CheckCxxInsnPredicate, /*MI*/0, /*FnId*/GIMT_Encode2(GICXXPred_MI_Predicate_store_align_less_than_4_local_m0),
      GIM_CheckComplexPattern, /*MI*/0, /*Op*/1, /*Renderer*/GIMT_Encode2(0), GIMT_Encode2(GICP_gi_ds_1addr_1offset),
      // (AMDGPUst_glue v8f16:{ *:[v8f16] }:$value, (DS1Addr1Offset:{ *:[iPTR] } i32:{ *:[i32] }:$ptr, i32:{ *:[i32] }:$offset))<<P:Predicate_unindexedstore_glue>><<P:Predicate_store_glue>><<P:Predicate_store_local_m0>><<P:Predicate_store_align_less_than_4_local_m0>>  =>  (DS_WRITE_B128 ?:{ *:[i32] }:$ptr, anonymous_15034:{ *:[v8f16] }:$value, offset:{ *:[i32] }:$offset, 0:{ *:[i1] })
      GIR_BuildMI, /*InsnID*/0, /*Opcode*/GIMT_Encode2(AMDGPU::DS_WRITE_B128),
      GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/0, // ptr
      GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/0, // value
      GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/1, // offset
      GIR_AddImm8, /*InsnID*/0, /*Imm*/0,
      GIR_MergeMemOperands, /*InsnID*/0, /*NumInsns*/1, /*MergeInsnID's*/0,
      GIR_ConstrainSelectedInstOperands, /*InsnID*/0,
      GIR_EraseFromParent, /*InsnID*/0,
      // GIR_Coverage, 6885,
      GIR_Done,
    // Label 2345: @154522
    GIM_Try, /*On fail goto*//*Label 2346*/ GIMT_Encode4(154592), // Rule ID 6889 //
      GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasUnalignedAccessMode_LDSRequiresM0Init),
      GIM_CheckMemorySizeEqualToLLT, /*MI*/0, /*MMO*/0, /*OpIdx*/0,
      GIM_CheckMemoryAddressSpace, /*MI*/0, /*MMO*/0, /*NumAddrSpace*/1, /*AddrSpace*/3,
      GIM_CheckMemoryAddressSpace, /*MI*/0, /*MMO*/0, /*NumAddrSpace*/1, /*AddrSpace*/3,
      GIM_CheckAtomicOrdering, /*MI*/0, /*Order*/(uint8_t)AtomicOrdering::NotAtomic,
      GIM_CheckPointerToAny, /*MI*/0, /*Op*/1, /*SizeInBits*/0,
      GIM_CheckCxxInsnPredicate, /*MI*/0, /*FnId*/GIMT_Encode2(GICXXPred_MI_Predicate_store_align_less_than_4_local_m0),
      GIM_CheckComplexPattern, /*MI*/0, /*Op*/1, /*Renderer*/GIMT_Encode2(0), GIMT_Encode2(GICP_gi_ds_1addr_1offset),
      // (AMDGPUst_glue v8bf16:{ *:[v8bf16] }:$value, (DS1Addr1Offset:{ *:[iPTR] } i32:{ *:[i32] }:$ptr, i32:{ *:[i32] }:$offset))<<P:Predicate_unindexedstore_glue>><<P:Predicate_store_glue>><<P:Predicate_store_local_m0>><<P:Predicate_store_align_less_than_4_local_m0>>  =>  (DS_WRITE_B128 ?:{ *:[i32] }:$ptr, anonymous_15034:{ *:[v8bf16] }:$value, offset:{ *:[i32] }:$offset, 0:{ *:[i1] })
      GIR_BuildMI, /*InsnID*/0, /*Opcode*/GIMT_Encode2(AMDGPU::DS_WRITE_B128),
      GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/0, // ptr
      GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/0, // value
      GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/1, // offset
      GIR_AddImm8, /*InsnID*/0, /*Imm*/0,
      GIR_MergeMemOperands, /*InsnID*/0, /*NumInsns*/1, /*MergeInsnID's*/0,
      GIR_ConstrainSelectedInstOperands, /*InsnID*/0,
      GIR_EraseFromParent, /*InsnID*/0,
      // GIR_Coverage, 6889,
      GIR_Done,
    // Label 2346: @154592
    GIM_Try, /*On fail goto*//*Label 2347*/ GIMT_Encode4(154657), // Rule ID 6805 //
      GIM_CheckFeatures, GIMT_Encode2(GIFBS_LDSRequiresM0Init_isGFX7Plus),
      GIM_CheckMemorySizeEqualToLLT, /*MI*/0, /*MMO*/0, /*OpIdx*/0,
      GIM_CheckMemoryAddressSpace, /*MI*/0, /*MMO*/0, /*NumAddrSpace*/1, /*AddrSpace*/3,
      GIM_CheckMemoryAlignment, /*MI*/0, /*MMO*/0, /*MinAlign*/16,
      GIM_CheckAtomicOrdering, /*MI*/0, /*Order*/(uint8_t)AtomicOrdering::NotAtomic,
      GIM_CheckPointerToAny, /*MI*/0, /*Op*/1, /*SizeInBits*/0,
      GIM_CheckComplexPattern, /*MI*/0, /*Op*/1, /*Renderer*/GIMT_Encode2(0), GIMT_Encode2(GICP_gi_ds_1addr_1offset),
      // (AMDGPUst_glue v8i16:{ *:[v8i16] }:$value, (DS1Addr1Offset:{ *:[iPTR] } i32:{ *:[i32] }:$ptr, i32:{ *:[i32] }:$offset))<<P:Predicate_unindexedstore_glue>><<P:Predicate_store_glue>><<P:Predicate_store_local_m0>><<P:Predicate_store_align16_local_m0>>  =>  (DS_WRITE_B128 ?:{ *:[i32] }:$ptr, anonymous_15034:{ *:[v8i16] }:$value, offset:{ *:[i32] }:$offset, 0:{ *:[i1] })
      GIR_BuildMI, /*InsnID*/0, /*Opcode*/GIMT_Encode2(AMDGPU::DS_WRITE_B128),
      GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/0, // ptr
      GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/0, // value
      GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/1, // offset
      GIR_AddImm8, /*InsnID*/0, /*Imm*/0,
      GIR_MergeMemOperands, /*InsnID*/0, /*NumInsns*/1, /*MergeInsnID's*/0,
      GIR_ConstrainSelectedInstOperands, /*InsnID*/0,
      GIR_EraseFromParent, /*InsnID*/0,
      // GIR_Coverage, 6805,
      GIR_Done,
    // Label 2347: @154657
    GIM_Try, /*On fail goto*//*Label 2348*/ GIMT_Encode4(154722), // Rule ID 6809 //
      GIM_CheckFeatures, GIMT_Encode2(GIFBS_LDSRequiresM0Init_isGFX7Plus),
      GIM_CheckMemorySizeEqualToLLT, /*MI*/0, /*MMO*/0, /*OpIdx*/0,
      GIM_CheckMemoryAddressSpace, /*MI*/0, /*MMO*/0, /*NumAddrSpace*/1, /*AddrSpace*/3,
      GIM_CheckMemoryAlignment, /*MI*/0, /*MMO*/0, /*MinAlign*/16,
      GIM_CheckAtomicOrdering, /*MI*/0, /*Order*/(uint8_t)AtomicOrdering::NotAtomic,
      GIM_CheckPointerToAny, /*MI*/0, /*Op*/1, /*SizeInBits*/0,
      GIM_CheckComplexPattern, /*MI*/0, /*Op*/1, /*Renderer*/GIMT_Encode2(0), GIMT_Encode2(GICP_gi_ds_1addr_1offset),
      // (AMDGPUst_glue v8f16:{ *:[v8f16] }:$value, (DS1Addr1Offset:{ *:[iPTR] } i32:{ *:[i32] }:$ptr, i32:{ *:[i32] }:$offset))<<P:Predicate_unindexedstore_glue>><<P:Predicate_store_glue>><<P:Predicate_store_local_m0>><<P:Predicate_store_align16_local_m0>>  =>  (DS_WRITE_B128 ?:{ *:[i32] }:$ptr, anonymous_15034:{ *:[v8f16] }:$value, offset:{ *:[i32] }:$offset, 0:{ *:[i1] })
      GIR_BuildMI, /*InsnID*/0, /*Opcode*/GIMT_Encode2(AMDGPU::DS_WRITE_B128),
      GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/0, // ptr
      GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/0, // value
      GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/1, // offset
      GIR_AddImm8, /*InsnID*/0, /*Imm*/0,
      GIR_MergeMemOperands, /*InsnID*/0, /*NumInsns*/1, /*MergeInsnID's*/0,
      GIR_ConstrainSelectedInstOperands, /*InsnID*/0,
      GIR_EraseFromParent, /*InsnID*/0,
      // GIR_Coverage, 6809,
      GIR_Done,
    // Label 2348: @154722
    GIM_Try, /*On fail goto*//*Label 2349*/ GIMT_Encode4(154787), // Rule ID 6813 //
      GIM_CheckFeatures, GIMT_Encode2(GIFBS_LDSRequiresM0Init_isGFX7Plus),
      GIM_CheckMemorySizeEqualToLLT, /*MI*/0, /*MMO*/0, /*OpIdx*/0,
      GIM_CheckMemoryAddressSpace, /*MI*/0, /*MMO*/0, /*NumAddrSpace*/1, /*AddrSpace*/3,
      GIM_CheckMemoryAlignment, /*MI*/0, /*MMO*/0, /*MinAlign*/16,
      GIM_CheckAtomicOrdering, /*MI*/0, /*Order*/(uint8_t)AtomicOrdering::NotAtomic,
      GIM_CheckPointerToAny, /*MI*/0, /*Op*/1, /*SizeInBits*/0,
      GIM_CheckComplexPattern, /*MI*/0, /*Op*/1, /*Renderer*/GIMT_Encode2(0), GIMT_Encode2(GICP_gi_ds_1addr_1offset),
      // (AMDGPUst_glue v8bf16:{ *:[v8bf16] }:$value, (DS1Addr1Offset:{ *:[iPTR] } i32:{ *:[i32] }:$ptr, i32:{ *:[i32] }:$offset))<<P:Predicate_unindexedstore_glue>><<P:Predicate_store_glue>><<P:Predicate_store_local_m0>><<P:Predicate_store_align16_local_m0>>  =>  (DS_WRITE_B128 ?:{ *:[i32] }:$ptr, anonymous_15034:{ *:[v8bf16] }:$value, offset:{ *:[i32] }:$offset, 0:{ *:[i1] })
      GIR_BuildMI, /*InsnID*/0, /*Opcode*/GIMT_Encode2(AMDGPU::DS_WRITE_B128),
      GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/0, // ptr
      GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/0, // value
      GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/1, // offset
      GIR_AddImm8, /*InsnID*/0, /*Imm*/0,
      GIR_MergeMemOperands, /*InsnID*/0, /*NumInsns*/1, /*MergeInsnID's*/0,
      GIR_ConstrainSelectedInstOperands, /*InsnID*/0,
      GIR_EraseFromParent, /*InsnID*/0,
      // GIR_Coverage, 6813,
      GIR_Done,
    // Label 2349: @154787
    GIM_Try, /*On fail goto*//*Label 2350*/ GIMT_Encode4(154853), // Rule ID 6882 //
      GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasUnalignedAccessMode_NotLDSRequiresM0Init),
      GIM_CheckMemoryAddressSpace, /*MI*/0, /*MMO*/0, /*NumAddrSpace*/1, /*AddrSpace*/3,
      GIM_CheckMemoryAddressSpace, /*MI*/0, /*MMO*/0, /*NumAddrSpace*/1, /*AddrSpace*/3,
      GIM_CheckAtomicOrdering, /*MI*/0, /*Order*/(uint8_t)AtomicOrdering::NotAtomic,
      GIM_CheckPointerToAny, /*MI*/0, /*Op*/1, /*SizeInBits*/0,
      GIM_CheckCxxInsnPredicate, /*MI*/0, /*FnId*/GIMT_Encode2(GICXXPred_MI_Predicate_store_align_less_than_4_local),
      GIM_CheckComplexPattern, /*MI*/0, /*Op*/1, /*Renderer*/GIMT_Encode2(0), GIMT_Encode2(GICP_gi_ds_1addr_1offset),
      // (st v8i16:{ *:[v8i16] }:$value, (DS1Addr1Offset:{ *:[iPTR] } i32:{ *:[i32] }:$ptr, i32:{ *:[i32] }:$offset))<<P:Predicate_unindexedstore>><<P:Predicate_store_local>><<P:Predicate_store_align_less_than_4_local>>  =>  (DS_WRITE_B128_gfx9 ?:{ *:[i32] }:$ptr, anonymous_15034:{ *:[v8i16] }:$value, offset:{ *:[i32] }:$offset, 0:{ *:[i1] })
      GIR_BuildMI, /*InsnID*/0, /*Opcode*/GIMT_Encode2(AMDGPU::DS_WRITE_B128_gfx9),
      GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/0, // ptr
      GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/0, // value
      GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/1, // offset
      GIR_AddImm8, /*InsnID*/0, /*Imm*/0,
      GIR_MergeMemOperands, /*InsnID*/0, /*NumInsns*/1, /*MergeInsnID's*/0,
      GIR_ConstrainSelectedInstOperands, /*InsnID*/0,
      GIR_EraseFromParent, /*InsnID*/0,
      // GIR_Coverage, 6882,
      GIR_Done,
    // Label 2350: @154853
    GIM_Try, /*On fail goto*//*Label 2351*/ GIMT_Encode4(154919), // Rule ID 6886 //
      GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasUnalignedAccessMode_NotLDSRequiresM0Init),
      GIM_CheckMemoryAddressSpace, /*MI*/0, /*MMO*/0, /*NumAddrSpace*/1, /*AddrSpace*/3,
      GIM_CheckMemoryAddressSpace, /*MI*/0, /*MMO*/0, /*NumAddrSpace*/1, /*AddrSpace*/3,
      GIM_CheckAtomicOrdering, /*MI*/0, /*Order*/(uint8_t)AtomicOrdering::NotAtomic,
      GIM_CheckPointerToAny, /*MI*/0, /*Op*/1, /*SizeInBits*/0,
      GIM_CheckCxxInsnPredicate, /*MI*/0, /*FnId*/GIMT_Encode2(GICXXPred_MI_Predicate_store_align_less_than_4_local),
      GIM_CheckComplexPattern, /*MI*/0, /*Op*/1, /*Renderer*/GIMT_Encode2(0), GIMT_Encode2(GICP_gi_ds_1addr_1offset),
      // (st v8f16:{ *:[v8f16] }:$value, (DS1Addr1Offset:{ *:[iPTR] } i32:{ *:[i32] }:$ptr, i32:{ *:[i32] }:$offset))<<P:Predicate_unindexedstore>><<P:Predicate_store_local>><<P:Predicate_store_align_less_than_4_local>>  =>  (DS_WRITE_B128_gfx9 ?:{ *:[i32] }:$ptr, anonymous_15034:{ *:[v8f16] }:$value, offset:{ *:[i32] }:$offset, 0:{ *:[i1] })
      GIR_BuildMI, /*InsnID*/0, /*Opcode*/GIMT_Encode2(AMDGPU::DS_WRITE_B128_gfx9),
      GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/0, // ptr
      GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/0, // value
      GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/1, // offset
      GIR_AddImm8, /*InsnID*/0, /*Imm*/0,
      GIR_MergeMemOperands, /*InsnID*/0, /*NumInsns*/1, /*MergeInsnID's*/0,
      GIR_ConstrainSelectedInstOperands, /*InsnID*/0,
      GIR_EraseFromParent, /*InsnID*/0,
      // GIR_Coverage, 6886,
      GIR_Done,
    // Label 2351: @154919
    GIM_Try, /*On fail goto*//*Label 2352*/ GIMT_Encode4(154985), // Rule ID 6890 //
      GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasUnalignedAccessMode_NotLDSRequiresM0Init),
      GIM_CheckMemoryAddressSpace, /*MI*/0, /*MMO*/0, /*NumAddrSpace*/1, /*AddrSpace*/3,
      GIM_CheckMemoryAddressSpace, /*MI*/0, /*MMO*/0, /*NumAddrSpace*/1, /*AddrSpace*/3,
      GIM_CheckAtomicOrdering, /*MI*/0, /*Order*/(uint8_t)AtomicOrdering::NotAtomic,
      GIM_CheckPointerToAny, /*MI*/0, /*Op*/1, /*SizeInBits*/0,
      GIM_CheckCxxInsnPredicate, /*MI*/0, /*FnId*/GIMT_Encode2(GICXXPred_MI_Predicate_store_align_less_than_4_local),
      GIM_CheckComplexPattern, /*MI*/0, /*Op*/1, /*Renderer*/GIMT_Encode2(0), GIMT_Encode2(GICP_gi_ds_1addr_1offset),
      // (st v8bf16:{ *:[v8bf16] }:$value, (DS1Addr1Offset:{ *:[iPTR] } i32:{ *:[i32] }:$ptr, i32:{ *:[i32] }:$offset))<<P:Predicate_unindexedstore>><<P:Predicate_store_local>><<P:Predicate_store_align_less_than_4_local>>  =>  (DS_WRITE_B128_gfx9 ?:{ *:[i32] }:$ptr, anonymous_15034:{ *:[v8bf16] }:$value, offset:{ *:[i32] }:$offset, 0:{ *:[i1] })
      GIR_BuildMI, /*InsnID*/0, /*Opcode*/GIMT_Encode2(AMDGPU::DS_WRITE_B128_gfx9),
      GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/0, // ptr
      GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/0, // value
      GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/1, // offset
      GIR_AddImm8, /*InsnID*/0, /*Imm*/0,
      GIR_MergeMemOperands, /*InsnID*/0, /*NumInsns*/1, /*MergeInsnID's*/0,
      GIR_ConstrainSelectedInstOperands, /*InsnID*/0,
      GIR_EraseFromParent, /*InsnID*/0,
      // GIR_Coverage, 6890,
      GIR_Done,
    // Label 2352: @154985
    GIM_Try, /*On fail goto*//*Label 2353*/ GIMT_Encode4(155046), // Rule ID 6806 //
      GIM_CheckFeatures, GIMT_Encode2(GIFBS_NotLDSRequiresM0Init_isGFX7Plus),
      GIM_CheckMemoryAddressSpace, /*MI*/0, /*MMO*/0, /*NumAddrSpace*/1, /*AddrSpace*/3,
      GIM_CheckMemoryAlignment, /*MI*/0, /*MMO*/0, /*MinAlign*/16,
      GIM_CheckAtomicOrdering, /*MI*/0, /*Order*/(uint8_t)AtomicOrdering::NotAtomic,
      GIM_CheckPointerToAny, /*MI*/0, /*Op*/1, /*SizeInBits*/0,
      GIM_CheckComplexPattern, /*MI*/0, /*Op*/1, /*Renderer*/GIMT_Encode2(0), GIMT_Encode2(GICP_gi_ds_1addr_1offset),
      // (st v8i16:{ *:[v8i16] }:$value, (DS1Addr1Offset:{ *:[iPTR] } i32:{ *:[i32] }:$ptr, i32:{ *:[i32] }:$offset))<<P:Predicate_unindexedstore>><<P:Predicate_store_local>><<P:Predicate_store_align16_local>>  =>  (DS_WRITE_B128_gfx9 ?:{ *:[i32] }:$ptr, anonymous_15034:{ *:[v8i16] }:$value, offset:{ *:[i32] }:$offset, 0:{ *:[i1] })
      GIR_BuildMI, /*InsnID*/0, /*Opcode*/GIMT_Encode2(AMDGPU::DS_WRITE_B128_gfx9),
      GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/0, // ptr
      GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/0, // value
      GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/1, // offset
      GIR_AddImm8, /*InsnID*/0, /*Imm*/0,
      GIR_MergeMemOperands, /*InsnID*/0, /*NumInsns*/1, /*MergeInsnID's*/0,
      GIR_ConstrainSelectedInstOperands, /*InsnID*/0,
      GIR_EraseFromParent, /*InsnID*/0,
      // GIR_Coverage, 6806,
      GIR_Done,
    // Label 2353: @155046
    GIM_Try, /*On fail goto*//*Label 2354*/ GIMT_Encode4(155107), // Rule ID 6810 //
      GIM_CheckFeatures, GIMT_Encode2(GIFBS_NotLDSRequiresM0Init_isGFX7Plus),
      GIM_CheckMemoryAddressSpace, /*MI*/0, /*MMO*/0, /*NumAddrSpace*/1, /*AddrSpace*/3,
      GIM_CheckMemoryAlignment, /*MI*/0, /*MMO*/0, /*MinAlign*/16,
      GIM_CheckAtomicOrdering, /*MI*/0, /*Order*/(uint8_t)AtomicOrdering::NotAtomic,
      GIM_CheckPointerToAny, /*MI*/0, /*Op*/1, /*SizeInBits*/0,
      GIM_CheckComplexPattern, /*MI*/0, /*Op*/1, /*Renderer*/GIMT_Encode2(0), GIMT_Encode2(GICP_gi_ds_1addr_1offset),
      // (st v8f16:{ *:[v8f16] }:$value, (DS1Addr1Offset:{ *:[iPTR] } i32:{ *:[i32] }:$ptr, i32:{ *:[i32] }:$offset))<<P:Predicate_unindexedstore>><<P:Predicate_store_local>><<P:Predicate_store_align16_local>>  =>  (DS_WRITE_B128_gfx9 ?:{ *:[i32] }:$ptr, anonymous_15034:{ *:[v8f16] }:$value, offset:{ *:[i32] }:$offset, 0:{ *:[i1] })
      GIR_BuildMI, /*InsnID*/0, /*Opcode*/GIMT_Encode2(AMDGPU::DS_WRITE_B128_gfx9),
      GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/0, // ptr
      GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/0, // value
      GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/1, // offset
      GIR_AddImm8, /*InsnID*/0, /*Imm*/0,
      GIR_MergeMemOperands, /*InsnID*/0, /*NumInsns*/1, /*MergeInsnID's*/0,
      GIR_ConstrainSelectedInstOperands, /*InsnID*/0,
      GIR_EraseFromParent, /*InsnID*/0,
      // GIR_Coverage, 6810,
      GIR_Done,
    // Label 2354: @155107
    GIM_Try, /*On fail goto*//*Label 2355*/ GIMT_Encode4(155168), // Rule ID 6814 //
      GIM_CheckFeatures, GIMT_Encode2(GIFBS_NotLDSRequiresM0Init_isGFX7Plus),
      GIM_CheckMemoryAddressSpace, /*MI*/0, /*MMO*/0, /*NumAddrSpace*/1, /*AddrSpace*/3,
      GIM_CheckMemoryAlignment, /*MI*/0, /*MMO*/0, /*MinAlign*/16,
      GIM_CheckAtomicOrdering, /*MI*/0, /*Order*/(uint8_t)AtomicOrdering::NotAtomic,
      GIM_CheckPointerToAny, /*MI*/0, /*Op*/1, /*SizeInBits*/0,
      GIM_CheckComplexPattern, /*MI*/0, /*Op*/1, /*Renderer*/GIMT_Encode2(0), GIMT_Encode2(GICP_gi_ds_1addr_1offset),
      // (st v8bf16:{ *:[v8bf16] }:$value, (DS1Addr1Offset:{ *:[iPTR] } i32:{ *:[i32] }:$ptr, i32:{ *:[i32] }:$offset))<<P:Predicate_unindexedstore>><<P:Predicate_store_local>><<P:Predicate_store_align16_local>>  =>  (DS_WRITE_B128_gfx9 ?:{ *:[i32] }:$ptr, anonymous_15034:{ *:[v8bf16] }:$value, offset:{ *:[i32] }:$offset, 0:{ *:[i1] })
      GIR_BuildMI, /*InsnID*/0, /*Opcode*/GIMT_Encode2(AMDGPU::DS_WRITE_B128_gfx9),
      GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/0, // ptr
      GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/0, // value
      GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/1, // offset
      GIR_AddImm8, /*InsnID*/0, /*Imm*/0,
      GIR_MergeMemOperands, /*InsnID*/0, /*NumInsns*/1, /*MergeInsnID's*/0,
      GIR_ConstrainSelectedInstOperands, /*InsnID*/0,
      GIR_EraseFromParent, /*InsnID*/0,
      // GIR_Coverage, 6814,
      GIR_Done,
    // Label 2355: @155168
    GIM_Try, /*On fail goto*//*Label 2356*/ GIMT_Encode4(155230), // Rule ID 3574 //
      GIM_CheckFeatures, GIMT_Encode2(GIFBS_EnableFlatScratch_HasFlatScratchInsts_HasFlatScratchSVSMode),
      GIM_CheckMemoryAddressSpace, /*MI*/0, /*MMO*/0, /*NumAddrSpace*/1, /*AddrSpace*/5,
      GIM_CheckAtomicOrdering, /*MI*/0, /*Order*/(uint8_t)AtomicOrdering::NotAtomic,
      GIM_CheckPointerToAny, /*MI*/0, /*Op*/1, /*SizeInBits*/0,
      GIM_CheckComplexPattern, /*MI*/0, /*Op*/1, /*Renderer*/GIMT_Encode2(0), GIMT_Encode2(GICP_gi_flat_scratch_svaddr),
      // (st v8i16:{ *:[v8i16] }:$data, (ScratchSVAddr:{ *:[iPTR] } VGPR_32:{ *:[i32] }:$vaddr, SGPR_32:{ *:[i32] }:$saddr, i32:{ *:[i32] }:$offset))<<P:Predicate_unindexedstore>><<P:Predicate_store_private>>  =>  (SCRATCH_STORE_DWORDX4_SVS anonymous_15034:{ *:[v8i16] }:$data, ?:{ *:[i32] }:$vaddr, ?:{ *:[i32] }:$saddr, ?:{ *:[i32] }:$offset)
      GIR_BuildMI, /*InsnID*/0, /*Opcode*/GIMT_Encode2(AMDGPU::SCRATCH_STORE_DWORDX4_SVS),
      GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/0, // data
      GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/0, // vaddr
      GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/1, // saddr
      GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/2, // offset
      GIR_AddImm8, /*InsnID*/0, /*Imm*/0,
      GIR_MergeMemOperands, /*InsnID*/0, /*NumInsns*/1, /*MergeInsnID's*/0,
      GIR_ConstrainSelectedInstOperands, /*InsnID*/0,
      GIR_EraseFromParent, /*InsnID*/0,
      // GIR_Coverage, 3574,
      GIR_Done,
    // Label 2356: @155230
    GIM_Try, /*On fail goto*//*Label 2357*/ GIMT_Encode4(155292), // Rule ID 3580 //
      GIM_CheckFeatures, GIMT_Encode2(GIFBS_EnableFlatScratch_HasFlatScratchInsts_HasFlatScratchSVSMode),
      GIM_CheckMemoryAddressSpace, /*MI*/0, /*MMO*/0, /*NumAddrSpace*/1, /*AddrSpace*/5,
      GIM_CheckAtomicOrdering, /*MI*/0, /*Order*/(uint8_t)AtomicOrdering::NotAtomic,
      GIM_CheckPointerToAny, /*MI*/0, /*Op*/1, /*SizeInBits*/0,
      GIM_CheckComplexPattern, /*MI*/0, /*Op*/1, /*Renderer*/GIMT_Encode2(0), GIMT_Encode2(GICP_gi_flat_scratch_svaddr),
      // (st v8f16:{ *:[v8f16] }:$data, (ScratchSVAddr:{ *:[iPTR] } VGPR_32:{ *:[i32] }:$vaddr, SGPR_32:{ *:[i32] }:$saddr, i32:{ *:[i32] }:$offset))<<P:Predicate_unindexedstore>><<P:Predicate_store_private>>  =>  (SCRATCH_STORE_DWORDX4_SVS anonymous_15034:{ *:[v8f16] }:$data, ?:{ *:[i32] }:$vaddr, ?:{ *:[i32] }:$saddr, ?:{ *:[i32] }:$offset)
      GIR_BuildMI, /*InsnID*/0, /*Opcode*/GIMT_Encode2(AMDGPU::SCRATCH_STORE_DWORDX4_SVS),
      GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/0, // data
      GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/0, // vaddr
      GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/1, // saddr
      GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/2, // offset
      GIR_AddImm8, /*InsnID*/0, /*Imm*/0,
      GIR_MergeMemOperands, /*InsnID*/0, /*NumInsns*/1, /*MergeInsnID's*/0,
      GIR_ConstrainSelectedInstOperands, /*InsnID*/0,
      GIR_EraseFromParent, /*InsnID*/0,
      // GIR_Coverage, 3580,
      GIR_Done,
    // Label 2357: @155292
    GIM_Try, /*On fail goto*//*Label 2358*/ GIMT_Encode4(155354), // Rule ID 3586 //
      GIM_CheckFeatures, GIMT_Encode2(GIFBS_EnableFlatScratch_HasFlatScratchInsts_HasFlatScratchSVSMode),
      GIM_CheckMemoryAddressSpace, /*MI*/0, /*MMO*/0, /*NumAddrSpace*/1, /*AddrSpace*/5,
      GIM_CheckAtomicOrdering, /*MI*/0, /*Order*/(uint8_t)AtomicOrdering::NotAtomic,
      GIM_CheckPointerToAny, /*MI*/0, /*Op*/1, /*SizeInBits*/0,
      GIM_CheckComplexPattern, /*MI*/0, /*Op*/1, /*Renderer*/GIMT_Encode2(0), GIMT_Encode2(GICP_gi_flat_scratch_svaddr),
      // (st v8bf16:{ *:[v8bf16] }:$data, (ScratchSVAddr:{ *:[iPTR] } VGPR_32:{ *:[i32] }:$vaddr, SGPR_32:{ *:[i32] }:$saddr, i32:{ *:[i32] }:$offset))<<P:Predicate_unindexedstore>><<P:Predicate_store_private>>  =>  (SCRATCH_STORE_DWORDX4_SVS anonymous_15034:{ *:[v8bf16] }:$data, ?:{ *:[i32] }:$vaddr, ?:{ *:[i32] }:$saddr, ?:{ *:[i32] }:$offset)
      GIR_BuildMI, /*InsnID*/0, /*Opcode*/GIMT_Encode2(AMDGPU::SCRATCH_STORE_DWORDX4_SVS),
      GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/0, // data
      GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/0, // vaddr
      GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/1, // saddr
      GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/2, // offset
      GIR_AddImm8, /*InsnID*/0, /*Imm*/0,
      GIR_MergeMemOperands, /*InsnID*/0, /*NumInsns*/1, /*MergeInsnID's*/0,
      GIR_ConstrainSelectedInstOperands, /*InsnID*/0,
      GIR_EraseFromParent, /*InsnID*/0,
      // GIR_Coverage, 3586,
      GIR_Done,
    // Label 2358: @155354
    GIM_Try, /*On fail goto*//*Label 2359*/ GIMT_Encode4(155411), // Rule ID 3573 //
      GIM_CheckFeatures, GIMT_Encode2(GIFBS_EnableFlatScratch_HasFlatScratchInsts),
      GIM_CheckMemoryAddressSpace, /*MI*/0, /*MMO*/0, /*NumAddrSpace*/1, /*AddrSpace*/5,
      GIM_CheckAtomicOrdering, /*MI*/0, /*Order*/(uint8_t)AtomicOrdering::NotAtomic,
      GIM_CheckPointerToAny, /*MI*/0, /*Op*/1, /*SizeInBits*/0,
      GIM_CheckComplexPattern, /*MI*/0, /*Op*/1, /*Renderer*/GIMT_Encode2(0), GIMT_Encode2(GICP_gi_flat_scratch_saddr),
      // (st v8i16:{ *:[v8i16] }:$data, (ScratchSAddr:{ *:[iPTR] } SGPR_32:{ *:[i32] }:$saddr, i32:{ *:[i32] }:$offset))<<P:Predicate_unindexedstore>><<P:Predicate_store_private>>  =>  (SCRATCH_STORE_DWORDX4_SADDR anonymous_15034:{ *:[v8i16] }:$data, ?:{ *:[i32] }:$saddr, ?:{ *:[i32] }:$offset)
      GIR_BuildMI, /*InsnID*/0, /*Opcode*/GIMT_Encode2(AMDGPU::SCRATCH_STORE_DWORDX4_SADDR),
      GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/0, // data
      GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/0, // saddr
      GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/1, // offset
      GIR_AddImm8, /*InsnID*/0, /*Imm*/0,
      GIR_MergeMemOperands, /*InsnID*/0, /*NumInsns*/1, /*MergeInsnID's*/0,
      GIR_ConstrainSelectedInstOperands, /*InsnID*/0,
      GIR_EraseFromParent, /*InsnID*/0,
      // GIR_Coverage, 3573,
      GIR_Done,
    // Label 2359: @155411
    GIM_Try, /*On fail goto*//*Label 2360*/ GIMT_Encode4(155468), // Rule ID 3579 //
      GIM_CheckFeatures, GIMT_Encode2(GIFBS_EnableFlatScratch_HasFlatScratchInsts),
      GIM_CheckMemoryAddressSpace, /*MI*/0, /*MMO*/0, /*NumAddrSpace*/1, /*AddrSpace*/5,
      GIM_CheckAtomicOrdering, /*MI*/0, /*Order*/(uint8_t)AtomicOrdering::NotAtomic,
      GIM_CheckPointerToAny, /*MI*/0, /*Op*/1, /*SizeInBits*/0,
      GIM_CheckComplexPattern, /*MI*/0, /*Op*/1, /*Renderer*/GIMT_Encode2(0), GIMT_Encode2(GICP_gi_flat_scratch_saddr),
      // (st v8f16:{ *:[v8f16] }:$data, (ScratchSAddr:{ *:[iPTR] } SGPR_32:{ *:[i32] }:$saddr, i32:{ *:[i32] }:$offset))<<P:Predicate_unindexedstore>><<P:Predicate_store_private>>  =>  (SCRATCH_STORE_DWORDX4_SADDR anonymous_15034:{ *:[v8f16] }:$data, ?:{ *:[i32] }:$saddr, ?:{ *:[i32] }:$offset)
      GIR_BuildMI, /*InsnID*/0, /*Opcode*/GIMT_Encode2(AMDGPU::SCRATCH_STORE_DWORDX4_SADDR),
      GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/0, // data
      GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/0, // saddr
      GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/1, // offset
      GIR_AddImm8, /*InsnID*/0, /*Imm*/0,
      GIR_MergeMemOperands, /*InsnID*/0, /*NumInsns*/1, /*MergeInsnID's*/0,
      GIR_ConstrainSelectedInstOperands, /*InsnID*/0,
      GIR_EraseFromParent, /*InsnID*/0,
      // GIR_Coverage, 3579,
      GIR_Done,
    // Label 2360: @155468
    GIM_Try, /*On fail goto*//*Label 2361*/ GIMT_Encode4(155525), // Rule ID 3585 //
      GIM_CheckFeatures, GIMT_Encode2(GIFBS_EnableFlatScratch_HasFlatScratchInsts),
      GIM_CheckMemoryAddressSpace, /*MI*/0, /*MMO*/0, /*NumAddrSpace*/1, /*AddrSpace*/5,
      GIM_CheckAtomicOrdering, /*MI*/0, /*Order*/(uint8_t)AtomicOrdering::NotAtomic,
      GIM_CheckPointerToAny, /*MI*/0, /*Op*/1, /*SizeInBits*/0,
      GIM_CheckComplexPattern, /*MI*/0, /*Op*/1, /*Renderer*/GIMT_Encode2(0), GIMT_Encode2(GICP_gi_flat_scratch_saddr),
      // (st v8bf16:{ *:[v8bf16] }:$data, (ScratchSAddr:{ *:[iPTR] } SGPR_32:{ *:[i32] }:$saddr, i32:{ *:[i32] }:$offset))<<P:Predicate_unindexedstore>><<P:Predicate_store_private>>  =>  (SCRATCH_STORE_DWORDX4_SADDR anonymous_15034:{ *:[v8bf16] }:$data, ?:{ *:[i32] }:$saddr, ?:{ *:[i32] }:$offset)
      GIR_BuildMI, /*InsnID*/0, /*Opcode*/GIMT_Encode2(AMDGPU::SCRATCH_STORE_DWORDX4_SADDR),
      GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/0, // data
      GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/0, // saddr
      GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/1, // offset
      GIR_AddImm8, /*InsnID*/0, /*Imm*/0,
      GIR_MergeMemOperands, /*InsnID*/0, /*NumInsns*/1, /*MergeInsnID's*/0,
      GIR_ConstrainSelectedInstOperands, /*InsnID*/0,
      GIR_EraseFromParent, /*InsnID*/0,
      // GIR_Coverage, 3585,
      GIR_Done,
    // Label 2361: @155525
    GIM_Try, /*On fail goto*//*Label 2362*/ GIMT_Encode4(155582), // Rule ID 3572 //
      GIM_CheckFeatures, GIMT_Encode2(GIFBS_EnableFlatScratch_HasFlatScratchInsts),
      GIM_CheckMemoryAddressSpace, /*MI*/0, /*MMO*/0, /*NumAddrSpace*/1, /*AddrSpace*/5,
      GIM_CheckAtomicOrdering, /*MI*/0, /*Order*/(uint8_t)AtomicOrdering::NotAtomic,
      GIM_CheckPointerToAny, /*MI*/0, /*Op*/1, /*SizeInBits*/0,
      GIM_CheckComplexPattern, /*MI*/0, /*Op*/1, /*Renderer*/GIMT_Encode2(0), GIMT_Encode2(GICP_gi_flat_scratch_offset),
      // (st v8i16:{ *:[v8i16] }:$data, (ScratchOffset:{ *:[iPTR] } VGPR_32:{ *:[i32] }:$vaddr, i32:{ *:[i32] }:$offset))<<P:Predicate_unindexedstore>><<P:Predicate_store_private>>  =>  (SCRATCH_STORE_DWORDX4 anonymous_15034:{ *:[v8i16] }:$data, ?:{ *:[i32] }:$vaddr, ?:{ *:[i32] }:$offset)
      GIR_BuildMI, /*InsnID*/0, /*Opcode*/GIMT_Encode2(AMDGPU::SCRATCH_STORE_DWORDX4),
      GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/0, // data
      GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/0, // vaddr
      GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/1, // offset
      GIR_AddImm8, /*InsnID*/0, /*Imm*/0,
      GIR_MergeMemOperands, /*InsnID*/0, /*NumInsns*/1, /*MergeInsnID's*/0,
      GIR_ConstrainSelectedInstOperands, /*InsnID*/0,
      GIR_EraseFromParent, /*InsnID*/0,
      // GIR_Coverage, 3572,
      GIR_Done,
    // Label 2362: @155582
    GIM_Try, /*On fail goto*//*Label 2363*/ GIMT_Encode4(155639), // Rule ID 3578 //
      GIM_CheckFeatures, GIMT_Encode2(GIFBS_EnableFlatScratch_HasFlatScratchInsts),
      GIM_CheckMemoryAddressSpace, /*MI*/0, /*MMO*/0, /*NumAddrSpace*/1, /*AddrSpace*/5,
      GIM_CheckAtomicOrdering, /*MI*/0, /*Order*/(uint8_t)AtomicOrdering::NotAtomic,
      GIM_CheckPointerToAny, /*MI*/0, /*Op*/1, /*SizeInBits*/0,
      GIM_CheckComplexPattern, /*MI*/0, /*Op*/1, /*Renderer*/GIMT_Encode2(0), GIMT_Encode2(GICP_gi_flat_scratch_offset),
      // (st v8f16:{ *:[v8f16] }:$data, (ScratchOffset:{ *:[iPTR] } VGPR_32:{ *:[i32] }:$vaddr, i32:{ *:[i32] }:$offset))<<P:Predicate_unindexedstore>><<P:Predicate_store_private>>  =>  (SCRATCH_STORE_DWORDX4 anonymous_15034:{ *:[v8f16] }:$data, ?:{ *:[i32] }:$vaddr, ?:{ *:[i32] }:$offset)
      GIR_BuildMI, /*InsnID*/0, /*Opcode*/GIMT_Encode2(AMDGPU::SCRATCH_STORE_DWORDX4),
      GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/0, // data
      GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/0, // vaddr
      GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/1, // offset
      GIR_AddImm8, /*InsnID*/0, /*Imm*/0,
      GIR_MergeMemOperands, /*InsnID*/0, /*NumInsns*/1, /*MergeInsnID's*/0,
      GIR_ConstrainSelectedInstOperands, /*InsnID*/0,
      GIR_EraseFromParent, /*InsnID*/0,
      // GIR_Coverage, 3578,
      GIR_Done,
    // Label 2363: @155639
    GIM_Try, /*On fail goto*//*Label 2364*/ GIMT_Encode4(155696), // Rule ID 3584 //
      GIM_CheckFeatures, GIMT_Encode2(GIFBS_EnableFlatScratch_HasFlatScratchInsts),
      GIM_CheckMemoryAddressSpace, /*MI*/0, /*MMO*/0, /*NumAddrSpace*/1, /*AddrSpace*/5,
      GIM_CheckAtomicOrdering, /*MI*/0, /*Order*/(uint8_t)AtomicOrdering::NotAtomic,
      GIM_CheckPointerToAny, /*MI*/0, /*Op*/1, /*SizeInBits*/0,
      GIM_CheckComplexPattern, /*MI*/0, /*Op*/1, /*Renderer*/GIMT_Encode2(0), GIMT_Encode2(GICP_gi_flat_scratch_offset),
      // (st v8bf16:{ *:[v8bf16] }:$data, (ScratchOffset:{ *:[iPTR] } VGPR_32:{ *:[i32] }:$vaddr, i32:{ *:[i32] }:$offset))<<P:Predicate_unindexedstore>><<P:Predicate_store_private>>  =>  (SCRATCH_STORE_DWORDX4 anonymous_15034:{ *:[v8bf16] }:$data, ?:{ *:[i32] }:$vaddr, ?:{ *:[i32] }:$offset)
      GIR_BuildMI, /*InsnID*/0, /*Opcode*/GIMT_Encode2(AMDGPU::SCRATCH_STORE_DWORDX4),
      GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/0, // data
      GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/0, // vaddr
      GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/1, // offset
      GIR_AddImm8, /*InsnID*/0, /*Imm*/0,
      GIR_MergeMemOperands, /*InsnID*/0, /*NumInsns*/1, /*MergeInsnID's*/0,
      GIR_ConstrainSelectedInstOperands, /*InsnID*/0,
      GIR_EraseFromParent, /*InsnID*/0,
      // GIR_Coverage, 3584,
      GIR_Done,
    // Label 2364: @155696
    GIM_Try, /*On fail goto*//*Label 2365*/ GIMT_Encode4(155766), // Rule ID 3902 //
      GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasUnrestrictedSOffset),
      GIM_CheckMemoryAddressSpace, /*MI*/0, /*MMO*/0, /*NumAddrSpace*/1, /*AddrSpace*/1,
      GIM_CheckAtomicOrdering, /*MI*/0, /*Order*/(uint8_t)AtomicOrdering::NotAtomic,
      GIM_CheckPointerToAny, /*MI*/0, /*Op*/1, /*SizeInBits*/0,
      GIM_CheckComplexPattern, /*MI*/0, /*Op*/1, /*Renderer*/GIMT_Encode2(0), GIMT_Encode2(GICP_gi_mubuf_addr64),
      // (st v8i16:{ *:[v8i16] }:$vdata, (MUBUFAddr64:{ *:[iPTR] } v4i32:{ *:[v4i32] }:$srsrc, i64:{ *:[i64] }:$vaddr, i32:{ *:[i32] }:$soffset, i32:{ *:[i32] }:$offset))<<P:Predicate_unindexedstore>><<P:Predicate_store_global>>  =>  (BUFFER_STORE_DWORDX4_ADDR64 v8i16:{ *:[v8i16] }:$vdata, i64:{ *:[i64] }:$vaddr, v4i32:{ *:[v4i32] }:$srsrc, i32:{ *:[i32] }:$soffset, i32:{ *:[i32] }:$offset)
      GIR_BuildMI, /*InsnID*/0, /*Opcode*/GIMT_Encode2(AMDGPU::BUFFER_STORE_DWORDX4_ADDR64),
      GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/0, // vdata
      GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/1, // vaddr
      GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/0, // srsrc
      GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/2, // soffset
      GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/3, // offset
      GIR_AddImm8, /*InsnID*/0, /*Imm*/0,
      GIR_AddImm8, /*InsnID*/0, /*Imm*/0,
      GIR_MergeMemOperands, /*InsnID*/0, /*NumInsns*/1, /*MergeInsnID's*/0,
      GIR_ConstrainSelectedInstOperands, /*InsnID*/0,
      GIR_EraseFromParent, /*InsnID*/0,
      // GIR_Coverage, 3902,
      GIR_Done,
    // Label 2365: @155766
    GIM_Try, /*On fail goto*//*Label 2366*/ GIMT_Encode4(155833), // Rule ID 3904 //
      GIM_CheckMemoryAddressSpace, /*MI*/0, /*MMO*/0, /*NumAddrSpace*/1, /*AddrSpace*/1,
      GIM_CheckAtomicOrdering, /*MI*/0, /*Order*/(uint8_t)AtomicOrdering::NotAtomic,
      GIM_CheckPointerToAny, /*MI*/0, /*Op*/1, /*SizeInBits*/0,
      GIM_CheckComplexPattern, /*MI*/0, /*Op*/1, /*Renderer*/GIMT_Encode2(0), GIMT_Encode2(GICP_gi_mubuf_addr64),
      // (st v8i16:{ *:[v8i16] }:$vdata, (MUBUFAddr64:{ *:[iPTR] } v4i32:{ *:[v4i32] }:$srsrc, i64:{ *:[i64] }:$vaddr, i32:{ *:[i32] }:$soffset, i32:{ *:[i32] }:$offset))<<P:Predicate_unindexedstore>><<P:Predicate_store_global>>  =>  (BUFFER_STORE_DWORDX4_VBUFFER_ADDR64 v8i16:{ *:[v8i16] }:$vdata, i64:{ *:[i64] }:$vaddr, v4i32:{ *:[v4i32] }:$srsrc, i32:{ *:[i32] }:$soffset, i32:{ *:[i32] }:$offset)
      GIR_BuildMI, /*InsnID*/0, /*Opcode*/GIMT_Encode2(AMDGPU::BUFFER_STORE_DWORDX4_VBUFFER_ADDR64),
      GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/0, // vdata
      GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/1, // vaddr
      GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/0, // srsrc
      GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/2, // soffset
      GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/3, // offset
      GIR_AddImm8, /*InsnID*/0, /*Imm*/0,
      GIR_AddImm8, /*InsnID*/0, /*Imm*/0,
      GIR_MergeMemOperands, /*InsnID*/0, /*NumInsns*/1, /*MergeInsnID's*/0,
      GIR_ConstrainSelectedInstOperands, /*InsnID*/0,
      GIR_EraseFromParent, /*InsnID*/0,
      // GIR_Coverage, 3904,
      GIR_Done,
    // Label 2366: @155833
    GIM_Try, /*On fail goto*//*Label 2367*/ GIMT_Encode4(155903), // Rule ID 3906 //
      GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasUnrestrictedSOffset),
      GIM_CheckMemoryAddressSpace, /*MI*/0, /*MMO*/0, /*NumAddrSpace*/1, /*AddrSpace*/1,
      GIM_CheckAtomicOrdering, /*MI*/0, /*Order*/(uint8_t)AtomicOrdering::NotAtomic,
      GIM_CheckPointerToAny, /*MI*/0, /*Op*/1, /*SizeInBits*/0,
      GIM_CheckComplexPattern, /*MI*/0, /*Op*/1, /*Renderer*/GIMT_Encode2(0), GIMT_Encode2(GICP_gi_mubuf_addr64),
      // (st v8f16:{ *:[v8f16] }:$vdata, (MUBUFAddr64:{ *:[iPTR] } v4i32:{ *:[v4i32] }:$srsrc, i64:{ *:[i64] }:$vaddr, i32:{ *:[i32] }:$soffset, i32:{ *:[i32] }:$offset))<<P:Predicate_unindexedstore>><<P:Predicate_store_global>>  =>  (BUFFER_STORE_DWORDX4_ADDR64 v8f16:{ *:[v8f16] }:$vdata, i64:{ *:[i64] }:$vaddr, v4i32:{ *:[v4i32] }:$srsrc, i32:{ *:[i32] }:$soffset, i32:{ *:[i32] }:$offset)
      GIR_BuildMI, /*InsnID*/0, /*Opcode*/GIMT_Encode2(AMDGPU::BUFFER_STORE_DWORDX4_ADDR64),
      GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/0, // vdata
      GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/1, // vaddr
      GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/0, // srsrc
      GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/2, // soffset
      GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/3, // offset
      GIR_AddImm8, /*InsnID*/0, /*Imm*/0,
      GIR_AddImm8, /*InsnID*/0, /*Imm*/0,
      GIR_MergeMemOperands, /*InsnID*/0, /*NumInsns*/1, /*MergeInsnID's*/0,
      GIR_ConstrainSelectedInstOperands, /*InsnID*/0,
      GIR_EraseFromParent, /*InsnID*/0,
      // GIR_Coverage, 3906,
      GIR_Done,
    // Label 2367: @155903
    GIM_Try, /*On fail goto*//*Label 2368*/ GIMT_Encode4(155970), // Rule ID 3908 //
      GIM_CheckMemoryAddressSpace, /*MI*/0, /*MMO*/0, /*NumAddrSpace*/1, /*AddrSpace*/1,
      GIM_CheckAtomicOrdering, /*MI*/0, /*Order*/(uint8_t)AtomicOrdering::NotAtomic,
      GIM_CheckPointerToAny, /*MI*/0, /*Op*/1, /*SizeInBits*/0,
      GIM_CheckComplexPattern, /*MI*/0, /*Op*/1, /*Renderer*/GIMT_Encode2(0), GIMT_Encode2(GICP_gi_mubuf_addr64),
      // (st v8f16:{ *:[v8f16] }:$vdata, (MUBUFAddr64:{ *:[iPTR] } v4i32:{ *:[v4i32] }:$srsrc, i64:{ *:[i64] }:$vaddr, i32:{ *:[i32] }:$soffset, i32:{ *:[i32] }:$offset))<<P:Predicate_unindexedstore>><<P:Predicate_store_global>>  =>  (BUFFER_STORE_DWORDX4_VBUFFER_ADDR64 v8f16:{ *:[v8f16] }:$vdata, i64:{ *:[i64] }:$vaddr, v4i32:{ *:[v4i32] }:$srsrc, i32:{ *:[i32] }:$soffset, i32:{ *:[i32] }:$offset)
      GIR_BuildMI, /*InsnID*/0, /*Opcode*/GIMT_Encode2(AMDGPU::BUFFER_STORE_DWORDX4_VBUFFER_ADDR64),
      GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/0, // vdata
      GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/1, // vaddr
      GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/0, // srsrc
      GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/2, // soffset
      GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/3, // offset
      GIR_AddImm8, /*InsnID*/0, /*Imm*/0,
      GIR_AddImm8, /*InsnID*/0, /*Imm*/0,
      GIR_MergeMemOperands, /*InsnID*/0, /*NumInsns*/1, /*MergeInsnID's*/0,
      GIR_ConstrainSelectedInstOperands, /*InsnID*/0,
      GIR_EraseFromParent, /*InsnID*/0,
      // GIR_Coverage, 3908,
      GIR_Done,
    // Label 2368: @155970
    GIM_Try, /*On fail goto*//*Label 2369*/ GIMT_Encode4(156040), // Rule ID 3910 //
      GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasUnrestrictedSOffset),
      GIM_CheckMemoryAddressSpace, /*MI*/0, /*MMO*/0, /*NumAddrSpace*/1, /*AddrSpace*/1,
      GIM_CheckAtomicOrdering, /*MI*/0, /*Order*/(uint8_t)AtomicOrdering::NotAtomic,
      GIM_CheckPointerToAny, /*MI*/0, /*Op*/1, /*SizeInBits*/0,
      GIM_CheckComplexPattern, /*MI*/0, /*Op*/1, /*Renderer*/GIMT_Encode2(0), GIMT_Encode2(GICP_gi_mubuf_addr64),
      // (st v8bf16:{ *:[v8bf16] }:$vdata, (MUBUFAddr64:{ *:[iPTR] } v4i32:{ *:[v4i32] }:$srsrc, i64:{ *:[i64] }:$vaddr, i32:{ *:[i32] }:$soffset, i32:{ *:[i32] }:$offset))<<P:Predicate_unindexedstore>><<P:Predicate_store_global>>  =>  (BUFFER_STORE_DWORDX4_ADDR64 v8bf16:{ *:[v8bf16] }:$vdata, i64:{ *:[i64] }:$vaddr, v4i32:{ *:[v4i32] }:$srsrc, i32:{ *:[i32] }:$soffset, i32:{ *:[i32] }:$offset)
      GIR_BuildMI, /*InsnID*/0, /*Opcode*/GIMT_Encode2(AMDGPU::BUFFER_STORE_DWORDX4_ADDR64),
      GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/0, // vdata
      GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/1, // vaddr
      GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/0, // srsrc
      GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/2, // soffset
      GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/3, // offset
      GIR_AddImm8, /*InsnID*/0, /*Imm*/0,
      GIR_AddImm8, /*InsnID*/0, /*Imm*/0,
      GIR_MergeMemOperands, /*InsnID*/0, /*NumInsns*/1, /*MergeInsnID's*/0,
      GIR_ConstrainSelectedInstOperands, /*InsnID*/0,
      GIR_EraseFromParent, /*InsnID*/0,
      // GIR_Coverage, 3910,
      GIR_Done,
    // Label 2369: @156040
    GIM_Try, /*On fail goto*//*Label 2370*/ GIMT_Encode4(156107), // Rule ID 3912 //
      GIM_CheckMemoryAddressSpace, /*MI*/0, /*MMO*/0, /*NumAddrSpace*/1, /*AddrSpace*/1,
      GIM_CheckAtomicOrdering, /*MI*/0, /*Order*/(uint8_t)AtomicOrdering::NotAtomic,
      GIM_CheckPointerToAny, /*MI*/0, /*Op*/1, /*SizeInBits*/0,
      GIM_CheckComplexPattern, /*MI*/0, /*Op*/1, /*Renderer*/GIMT_Encode2(0), GIMT_Encode2(GICP_gi_mubuf_addr64),
      // (st v8bf16:{ *:[v8bf16] }:$vdata, (MUBUFAddr64:{ *:[iPTR] } v4i32:{ *:[v4i32] }:$srsrc, i64:{ *:[i64] }:$vaddr, i32:{ *:[i32] }:$soffset, i32:{ *:[i32] }:$offset))<<P:Predicate_unindexedstore>><<P:Predicate_store_global>>  =>  (BUFFER_STORE_DWORDX4_VBUFFER_ADDR64 v8bf16:{ *:[v8bf16] }:$vdata, i64:{ *:[i64] }:$vaddr, v4i32:{ *:[v4i32] }:$srsrc, i32:{ *:[i32] }:$soffset, i32:{ *:[i32] }:$offset)
      GIR_BuildMI, /*InsnID*/0, /*Opcode*/GIMT_Encode2(AMDGPU::BUFFER_STORE_DWORDX4_VBUFFER_ADDR64),
      GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/0, // vdata
      GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/1, // vaddr
      GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/0, // srsrc
      GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/2, // soffset
      GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/3, // offset
      GIR_AddImm8, /*InsnID*/0, /*Imm*/0,
      GIR_AddImm8, /*InsnID*/0, /*Imm*/0,
      GIR_MergeMemOperands, /*InsnID*/0, /*NumInsns*/1, /*MergeInsnID's*/0,
      GIR_ConstrainSelectedInstOperands, /*InsnID*/0,
      GIR_EraseFromParent, /*InsnID*/0,
      // GIR_Coverage, 3912,
      GIR_Done,
    // Label 2370: @156107
    GIM_Try, /*On fail goto*//*Label 2371*/ GIMT_Encode4(156231), // Rule ID 6728 //
      GIM_CheckFeatures, GIMT_Encode2(GIFBS_LDSRequiresM0Init_isGFX7Plus),
      GIM_CheckMemorySizeEqualToLLT, /*MI*/0, /*MMO*/0, /*OpIdx*/0,
      GIM_CheckMemoryAddressSpace, /*MI*/0, /*MMO*/0, /*NumAddrSpace*/1, /*AddrSpace*/3,
      GIM_CheckAtomicOrdering, /*MI*/0, /*Order*/(uint8_t)AtomicOrdering::NotAtomic,
      GIM_CheckPointerToAny, /*MI*/0, /*Op*/1, /*SizeInBits*/0,
      GIM_CheckComplexPattern, /*MI*/0, /*Op*/1, /*Renderer*/GIMT_Encode2(0), GIMT_Encode2(GICP_gi_ds_128bit_8byte_aligned),
      // (AMDGPUst_glue v8i16:{ *:[v8i16] }:$value, (DS128Bit8ByteAligned:{ *:[iPTR] } i32:{ *:[i32] }:$ptr, i8:{ *:[i8] }:$offset0, i8:{ *:[i8] }:$offset1))<<P:Predicate_unindexedstore_glue>><<P:Predicate_store_glue>><<P:Predicate_store_local_m0>>  =>  (DS_WRITE2_B64 ?:{ *:[i32] }:$ptr, (EXTRACT_SUBREG:{ *:[i64] } VReg_128:{ *:[v8i16] }:$value, sub0_sub1:{ *:[i32] }), (EXTRACT_SUBREG:{ *:[i64] } VReg_128:{ *:[v8i16] }:$value, sub2_sub3:{ *:[i32] }), ?:{ *:[i8] }:$offset0, ?:{ *:[i8] }:$offset1, 0:{ *:[i1] })
      GIR_MakeTempReg, /*TempRegID*/0, /*TypeID*/GILLT_s64,
      GIR_MakeTempReg, /*TempRegID*/1, /*TypeID*/GILLT_s64,
      GIR_BuildMI, /*InsnID*/2, /*Opcode*/GIMT_Encode2(TargetOpcode::COPY),
      GIR_AddTempRegister, /*InsnID*/2, /*TempRegID*/1, /*TempRegFlags*/GIMT_Encode2(RegState::Define),
      GIR_CopySubReg, /*NewInsnID*/2, /*OldInsnID*/0, /*OpIdx*/0, /*SubRegIdx*/GIMT_Encode2(24), // value
      GIR_ConstrainOperandRC, /*InsnID*/2, /*Op*/0, GIMT_Encode2(AMDGPU::VReg_64RegClassID),
      GIR_ConstrainOperandRC, /*InsnID*/2, /*Op*/1, GIMT_Encode2(AMDGPU::VReg_128RegClassID),
      GIR_BuildMI, /*InsnID*/1, /*Opcode*/GIMT_Encode2(TargetOpcode::COPY),
      GIR_AddTempRegister, /*InsnID*/1, /*TempRegID*/0, /*TempRegFlags*/GIMT_Encode2(RegState::Define),
      GIR_CopySubReg, /*NewInsnID*/1, /*OldInsnID*/0, /*OpIdx*/0, /*SubRegIdx*/GIMT_Encode2(4), // value
      GIR_ConstrainOperandRC, /*InsnID*/1, /*Op*/0, GIMT_Encode2(AMDGPU::VReg_64RegClassID),
      GIR_ConstrainOperandRC, /*InsnID*/1, /*Op*/1, GIMT_Encode2(AMDGPU::VReg_128RegClassID),
      GIR_BuildMI, /*InsnID*/0, /*Opcode*/GIMT_Encode2(AMDGPU::DS_WRITE2_B64),
      GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/0, // ptr
      GIR_AddSimpleTempRegister, /*InsnID*/0, /*TempRegID*/0,
      GIR_AddSimpleTempRegister, /*InsnID*/0, /*TempRegID*/1,
      GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/1, // offset0
      GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/2, // offset1
      GIR_AddImm8, /*InsnID*/0, /*Imm*/0,
      GIR_MergeMemOperands, /*InsnID*/0, /*NumInsns*/1, /*MergeInsnID's*/0,
      GIR_ConstrainSelectedInstOperands, /*InsnID*/0,
      GIR_EraseFromParent, /*InsnID*/0,
      // GIR_Coverage, 6728,
      GIR_Done,
    // Label 2371: @156231
    GIM_Try, /*On fail goto*//*Label 2372*/ GIMT_Encode4(156355), // Rule ID 6732 //
      GIM_CheckFeatures, GIMT_Encode2(GIFBS_LDSRequiresM0Init_isGFX7Plus),
      GIM_CheckMemorySizeEqualToLLT, /*MI*/0, /*MMO*/0, /*OpIdx*/0,
      GIM_CheckMemoryAddressSpace, /*MI*/0, /*MMO*/0, /*NumAddrSpace*/1, /*AddrSpace*/3,
      GIM_CheckAtomicOrdering, /*MI*/0, /*Order*/(uint8_t)AtomicOrdering::NotAtomic,
      GIM_CheckPointerToAny, /*MI*/0, /*Op*/1, /*SizeInBits*/0,
      GIM_CheckComplexPattern, /*MI*/0, /*Op*/1, /*Renderer*/GIMT_Encode2(0), GIMT_Encode2(GICP_gi_ds_128bit_8byte_aligned),
      // (AMDGPUst_glue v8f16:{ *:[v8f16] }:$value, (DS128Bit8ByteAligned:{ *:[iPTR] } i32:{ *:[i32] }:$ptr, i8:{ *:[i8] }:$offset0, i8:{ *:[i8] }:$offset1))<<P:Predicate_unindexedstore_glue>><<P:Predicate_store_glue>><<P:Predicate_store_local_m0>>  =>  (DS_WRITE2_B64 ?:{ *:[i32] }:$ptr, (EXTRACT_SUBREG:{ *:[i64] } VReg_128:{ *:[v8f16] }:$value, sub0_sub1:{ *:[i32] }), (EXTRACT_SUBREG:{ *:[i64] } VReg_128:{ *:[v8f16] }:$value, sub2_sub3:{ *:[i32] }), ?:{ *:[i8] }:$offset0, ?:{ *:[i8] }:$offset1, 0:{ *:[i1] })
      GIR_MakeTempReg, /*TempRegID*/0, /*TypeID*/GILLT_s64,
      GIR_MakeTempReg, /*TempRegID*/1, /*TypeID*/GILLT_s64,
      GIR_BuildMI, /*InsnID*/2, /*Opcode*/GIMT_Encode2(TargetOpcode::COPY),
      GIR_AddTempRegister, /*InsnID*/2, /*TempRegID*/1, /*TempRegFlags*/GIMT_Encode2(RegState::Define),
      GIR_CopySubReg, /*NewInsnID*/2, /*OldInsnID*/0, /*OpIdx*/0, /*SubRegIdx*/GIMT_Encode2(24), // value
      GIR_ConstrainOperandRC, /*InsnID*/2, /*Op*/0, GIMT_Encode2(AMDGPU::VReg_64RegClassID),
      GIR_ConstrainOperandRC, /*InsnID*/2, /*Op*/1, GIMT_Encode2(AMDGPU::VReg_128RegClassID),
      GIR_BuildMI, /*InsnID*/1, /*Opcode*/GIMT_Encode2(TargetOpcode::COPY),
      GIR_AddTempRegister, /*InsnID*/1, /*TempRegID*/0, /*TempRegFlags*/GIMT_Encode2(RegState::Define),
      GIR_CopySubReg, /*NewInsnID*/1, /*OldInsnID*/0, /*OpIdx*/0, /*SubRegIdx*/GIMT_Encode2(4), // value
      GIR_ConstrainOperandRC, /*InsnID*/1, /*Op*/0, GIMT_Encode2(AMDGPU::VReg_64RegClassID),
      GIR_ConstrainOperandRC, /*InsnID*/1, /*Op*/1, GIMT_Encode2(AMDGPU::VReg_128RegClassID),
      GIR_BuildMI, /*InsnID*/0, /*Opcode*/GIMT_Encode2(AMDGPU::DS_WRITE2_B64),
      GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/0, // ptr
      GIR_AddSimpleTempRegister, /*InsnID*/0, /*TempRegID*/0,
      GIR_AddSimpleTempRegister, /*InsnID*/0, /*TempRegID*/1,
      GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/1, // offset0
      GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/2, // offset1
      GIR_AddImm8, /*InsnID*/0, /*Imm*/0,
      GIR_MergeMemOperands, /*InsnID*/0, /*NumInsns*/1, /*MergeInsnID's*/0,
      GIR_ConstrainSelectedInstOperands, /*InsnID*/0,
      GIR_EraseFromParent, /*InsnID*/0,
      // GIR_Coverage, 6732,
      GIR_Done,
    // Label 2372: @156355
    GIM_Try, /*On fail goto*//*Label 2373*/ GIMT_Encode4(156479), // Rule ID 6736 //
      GIM_CheckFeatures, GIMT_Encode2(GIFBS_LDSRequiresM0Init_isGFX7Plus),
      GIM_CheckMemorySizeEqualToLLT, /*MI*/0, /*MMO*/0, /*OpIdx*/0,
      GIM_CheckMemoryAddressSpace, /*MI*/0, /*MMO*/0, /*NumAddrSpace*/1, /*AddrSpace*/3,
      GIM_CheckAtomicOrdering, /*MI*/0, /*Order*/(uint8_t)AtomicOrdering::NotAtomic,
      GIM_CheckPointerToAny, /*MI*/0, /*Op*/1, /*SizeInBits*/0,
      GIM_CheckComplexPattern, /*MI*/0, /*Op*/1, /*Renderer*/GIMT_Encode2(0), GIMT_Encode2(GICP_gi_ds_128bit_8byte_aligned),
      // (AMDGPUst_glue v8bf16:{ *:[v8bf16] }:$value, (DS128Bit8ByteAligned:{ *:[iPTR] } i32:{ *:[i32] }:$ptr, i8:{ *:[i8] }:$offset0, i8:{ *:[i8] }:$offset1))<<P:Predicate_unindexedstore_glue>><<P:Predicate_store_glue>><<P:Predicate_store_local_m0>>  =>  (DS_WRITE2_B64 ?:{ *:[i32] }:$ptr, (EXTRACT_SUBREG:{ *:[i64] } VReg_128:{ *:[v8bf16] }:$value, sub0_sub1:{ *:[i32] }), (EXTRACT_SUBREG:{ *:[i64] } VReg_128:{ *:[v8bf16] }:$value, sub2_sub3:{ *:[i32] }), ?:{ *:[i8] }:$offset0, ?:{ *:[i8] }:$offset1, 0:{ *:[i1] })
      GIR_MakeTempReg, /*TempRegID*/0, /*TypeID*/GILLT_s64,
      GIR_MakeTempReg, /*TempRegID*/1, /*TypeID*/GILLT_s64,
      GIR_BuildMI, /*InsnID*/2, /*Opcode*/GIMT_Encode2(TargetOpcode::COPY),
      GIR_AddTempRegister, /*InsnID*/2, /*TempRegID*/1, /*TempRegFlags*/GIMT_Encode2(RegState::Define),
      GIR_CopySubReg, /*NewInsnID*/2, /*OldInsnID*/0, /*OpIdx*/0, /*SubRegIdx*/GIMT_Encode2(24), // value
      GIR_ConstrainOperandRC, /*InsnID*/2, /*Op*/0, GIMT_Encode2(AMDGPU::VReg_64RegClassID),
      GIR_ConstrainOperandRC, /*InsnID*/2, /*Op*/1, GIMT_Encode2(AMDGPU::VReg_128RegClassID),
      GIR_BuildMI, /*InsnID*/1, /*Opcode*/GIMT_Encode2(TargetOpcode::COPY),
      GIR_AddTempRegister, /*InsnID*/1, /*TempRegID*/0, /*TempRegFlags*/GIMT_Encode2(RegState::Define),
      GIR_CopySubReg, /*NewInsnID*/1, /*OldInsnID*/0, /*OpIdx*/0, /*SubRegIdx*/GIMT_Encode2(4), // value
      GIR_ConstrainOperandRC, /*InsnID*/1, /*Op*/0, GIMT_Encode2(AMDGPU::VReg_64RegClassID),
      GIR_ConstrainOperandRC, /*InsnID*/1, /*Op*/1, GIMT_Encode2(AMDGPU::VReg_128RegClassID),
      GIR_BuildMI, /*InsnID*/0, /*Opcode*/GIMT_Encode2(AMDGPU::DS_WRITE2_B64),
      GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/0, // ptr
      GIR_AddSimpleTempRegister, /*InsnID*/0, /*TempRegID*/0,
      GIR_AddSimpleTempRegister, /*InsnID*/0, /*TempRegID*/1,
      GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/1, // offset0
      GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/2, // offset1
      GIR_AddImm8, /*InsnID*/0, /*Imm*/0,
      GIR_MergeMemOperands, /*InsnID*/0, /*NumInsns*/1, /*MergeInsnID's*/0,
      GIR_ConstrainSelectedInstOperands, /*InsnID*/0,
      GIR_EraseFromParent, /*InsnID*/0,
      // GIR_Coverage, 6736,
      GIR_Done,
    // Label 2373: @156479
    GIM_Try, /*On fail goto*//*Label 2374*/ GIMT_Encode4(156544), // Rule ID 3901 //
      GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasUnrestrictedSOffset),
      GIM_CheckMemoryAddressSpace, /*MI*/0, /*MMO*/0, /*NumAddrSpace*/1, /*AddrSpace*/1,
      GIM_CheckAtomicOrdering, /*MI*/0, /*Order*/(uint8_t)AtomicOrdering::NotAtomic,
      GIM_CheckPointerToAny, /*MI*/0, /*Op*/1, /*SizeInBits*/0,
      GIM_CheckComplexPattern, /*MI*/0, /*Op*/1, /*Renderer*/GIMT_Encode2(0), GIMT_Encode2(GICP_gi_mubuf_offset),
      // (st v8i16:{ *:[v8i16] }:$vdata, (MUBUFOffset:{ *:[iPTR] } v4i32:{ *:[v4i32] }:$srsrc, i32:{ *:[i32] }:$soffset, i32:{ *:[i32] }:$offset))<<P:Predicate_unindexedstore>><<P:Predicate_store_global>>  =>  (BUFFER_STORE_DWORDX4_OFFSET v8i16:{ *:[v8i16] }:$vdata, v4i32:{ *:[v4i32] }:$srsrc, i32:{ *:[i32] }:$soffset, i32:{ *:[i32] }:$offset)
      GIR_BuildMI, /*InsnID*/0, /*Opcode*/GIMT_Encode2(AMDGPU::BUFFER_STORE_DWORDX4_OFFSET),
      GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/0, // vdata
      GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/0, // srsrc
      GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/1, // soffset
      GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/2, // offset
      GIR_AddImm8, /*InsnID*/0, /*Imm*/0,
      GIR_AddImm8, /*InsnID*/0, /*Imm*/0,
      GIR_MergeMemOperands, /*InsnID*/0, /*NumInsns*/1, /*MergeInsnID's*/0,
      GIR_ConstrainSelectedInstOperands, /*InsnID*/0,
      GIR_EraseFromParent, /*InsnID*/0,
      // GIR_Coverage, 3901,
      GIR_Done,
    // Label 2374: @156544
    GIM_Try, /*On fail goto*//*Label 2375*/ GIMT_Encode4(156606), // Rule ID 3903 //
      GIM_CheckMemoryAddressSpace, /*MI*/0, /*MMO*/0, /*NumAddrSpace*/1, /*AddrSpace*/1,
      GIM_CheckAtomicOrdering, /*MI*/0, /*Order*/(uint8_t)AtomicOrdering::NotAtomic,
      GIM_CheckPointerToAny, /*MI*/0, /*Op*/1, /*SizeInBits*/0,
      GIM_CheckComplexPattern, /*MI*/0, /*Op*/1, /*Renderer*/GIMT_Encode2(0), GIMT_Encode2(GICP_gi_mubuf_offset),
      // (st v8i16:{ *:[v8i16] }:$vdata, (MUBUFOffset:{ *:[iPTR] } v4i32:{ *:[v4i32] }:$srsrc, i32:{ *:[i32] }:$soffset, i32:{ *:[i32] }:$offset))<<P:Predicate_unindexedstore>><<P:Predicate_store_global>>  =>  (BUFFER_STORE_DWORDX4_VBUFFER_OFFSET v8i16:{ *:[v8i16] }:$vdata, v4i32:{ *:[v4i32] }:$srsrc, i32:{ *:[i32] }:$soffset, i32:{ *:[i32] }:$offset)
      GIR_BuildMI, /*InsnID*/0, /*Opcode*/GIMT_Encode2(AMDGPU::BUFFER_STORE_DWORDX4_VBUFFER_OFFSET),
      GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/0, // vdata
      GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/0, // srsrc
      GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/1, // soffset
      GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/2, // offset
      GIR_AddImm8, /*InsnID*/0, /*Imm*/0,
      GIR_AddImm8, /*InsnID*/0, /*Imm*/0,
      GIR_MergeMemOperands, /*InsnID*/0, /*NumInsns*/1, /*MergeInsnID's*/0,
      GIR_ConstrainSelectedInstOperands, /*InsnID*/0,
      GIR_EraseFromParent, /*InsnID*/0,
      // GIR_Coverage, 3903,
      GIR_Done,
    // Label 2375: @156606
    GIM_Try, /*On fail goto*//*Label 2376*/ GIMT_Encode4(156671), // Rule ID 3905 //
      GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasUnrestrictedSOffset),
      GIM_CheckMemoryAddressSpace, /*MI*/0, /*MMO*/0, /*NumAddrSpace*/1, /*AddrSpace*/1,
      GIM_CheckAtomicOrdering, /*MI*/0, /*Order*/(uint8_t)AtomicOrdering::NotAtomic,
      GIM_CheckPointerToAny, /*MI*/0, /*Op*/1, /*SizeInBits*/0,
      GIM_CheckComplexPattern, /*MI*/0, /*Op*/1, /*Renderer*/GIMT_Encode2(0), GIMT_Encode2(GICP_gi_mubuf_offset),
      // (st v8f16:{ *:[v8f16] }:$vdata, (MUBUFOffset:{ *:[iPTR] } v4i32:{ *:[v4i32] }:$srsrc, i32:{ *:[i32] }:$soffset, i32:{ *:[i32] }:$offset))<<P:Predicate_unindexedstore>><<P:Predicate_store_global>>  =>  (BUFFER_STORE_DWORDX4_OFFSET v8f16:{ *:[v8f16] }:$vdata, v4i32:{ *:[v4i32] }:$srsrc, i32:{ *:[i32] }:$soffset, i32:{ *:[i32] }:$offset)
      GIR_BuildMI, /*InsnID*/0, /*Opcode*/GIMT_Encode2(AMDGPU::BUFFER_STORE_DWORDX4_OFFSET),
      GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/0, // vdata
      GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/0, // srsrc
      GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/1, // soffset
      GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/2, // offset
      GIR_AddImm8, /*InsnID*/0, /*Imm*/0,
      GIR_AddImm8, /*InsnID*/0, /*Imm*/0,
      GIR_MergeMemOperands, /*InsnID*/0, /*NumInsns*/1, /*MergeInsnID's*/0,
      GIR_ConstrainSelectedInstOperands, /*InsnID*/0,
      GIR_EraseFromParent, /*InsnID*/0,
      // GIR_Coverage, 3905,
      GIR_Done,
    // Label 2376: @156671
    GIM_Try, /*On fail goto*//*Label 2377*/ GIMT_Encode4(156733), // Rule ID 3907 //
      GIM_CheckMemoryAddressSpace, /*MI*/0, /*MMO*/0, /*NumAddrSpace*/1, /*AddrSpace*/1,
      GIM_CheckAtomicOrdering, /*MI*/0, /*Order*/(uint8_t)AtomicOrdering::NotAtomic,
      GIM_CheckPointerToAny, /*MI*/0, /*Op*/1, /*SizeInBits*/0,
      GIM_CheckComplexPattern, /*MI*/0, /*Op*/1, /*Renderer*/GIMT_Encode2(0), GIMT_Encode2(GICP_gi_mubuf_offset),
      // (st v8f16:{ *:[v8f16] }:$vdata, (MUBUFOffset:{ *:[iPTR] } v4i32:{ *:[v4i32] }:$srsrc, i32:{ *:[i32] }:$soffset, i32:{ *:[i32] }:$offset))<<P:Predicate_unindexedstore>><<P:Predicate_store_global>>  =>  (BUFFER_STORE_DWORDX4_VBUFFER_OFFSET v8f16:{ *:[v8f16] }:$vdata, v4i32:{ *:[v4i32] }:$srsrc, i32:{ *:[i32] }:$soffset, i32:{ *:[i32] }:$offset)
      GIR_BuildMI, /*InsnID*/0, /*Opcode*/GIMT_Encode2(AMDGPU::BUFFER_STORE_DWORDX4_VBUFFER_OFFSET),
      GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/0, // vdata
      GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/0, // srsrc
      GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/1, // soffset
      GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/2, // offset
      GIR_AddImm8, /*InsnID*/0, /*Imm*/0,
      GIR_AddImm8, /*InsnID*/0, /*Imm*/0,
      GIR_MergeMemOperands, /*InsnID*/0, /*NumInsns*/1, /*MergeInsnID's*/0,
      GIR_ConstrainSelectedInstOperands, /*InsnID*/0,
      GIR_EraseFromParent, /*InsnID*/0,
      // GIR_Coverage, 3907,
      GIR_Done,
    // Label 2377: @156733
    GIM_Try, /*On fail goto*//*Label 2378*/ GIMT_Encode4(156798), // Rule ID 3909 //
      GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasUnrestrictedSOffset),
      GIM_CheckMemoryAddressSpace, /*MI*/0, /*MMO*/0, /*NumAddrSpace*/1, /*AddrSpace*/1,
      GIM_CheckAtomicOrdering, /*MI*/0, /*Order*/(uint8_t)AtomicOrdering::NotAtomic,
      GIM_CheckPointerToAny, /*MI*/0, /*Op*/1, /*SizeInBits*/0,
      GIM_CheckComplexPattern, /*MI*/0, /*Op*/1, /*Renderer*/GIMT_Encode2(0), GIMT_Encode2(GICP_gi_mubuf_offset),
      // (st v8bf16:{ *:[v8bf16] }:$vdata, (MUBUFOffset:{ *:[iPTR] } v4i32:{ *:[v4i32] }:$srsrc, i32:{ *:[i32] }:$soffset, i32:{ *:[i32] }:$offset))<<P:Predicate_unindexedstore>><<P:Predicate_store_global>>  =>  (BUFFER_STORE_DWORDX4_OFFSET v8bf16:{ *:[v8bf16] }:$vdata, v4i32:{ *:[v4i32] }:$srsrc, i32:{ *:[i32] }:$soffset, i32:{ *:[i32] }:$offset)
      GIR_BuildMI, /*InsnID*/0, /*Opcode*/GIMT_Encode2(AMDGPU::BUFFER_STORE_DWORDX4_OFFSET),
      GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/0, // vdata
      GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/0, // srsrc
      GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/1, // soffset
      GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/2, // offset
      GIR_AddImm8, /*InsnID*/0, /*Imm*/0,
      GIR_AddImm8, /*InsnID*/0, /*Imm*/0,
      GIR_MergeMemOperands, /*InsnID*/0, /*NumInsns*/1, /*MergeInsnID's*/0,
      GIR_ConstrainSelectedInstOperands, /*InsnID*/0,
      GIR_EraseFromParent, /*InsnID*/0,
      // GIR_Coverage, 3909,
      GIR_Done,
    // Label 2378: @156798
    GIM_Try, /*On fail goto*//*Label 2379*/ GIMT_Encode4(156860), // Rule ID 3911 //
      GIM_CheckMemoryAddressSpace, /*MI*/0, /*MMO*/0, /*NumAddrSpace*/1, /*AddrSpace*/1,
      GIM_CheckAtomicOrdering, /*MI*/0, /*Order*/(uint8_t)AtomicOrdering::NotAtomic,
      GIM_CheckPointerToAny, /*MI*/0, /*Op*/1, /*SizeInBits*/0,
      GIM_CheckComplexPattern, /*MI*/0, /*Op*/1, /*Renderer*/GIMT_Encode2(0), GIMT_Encode2(GICP_gi_mubuf_offset),
      // (st v8bf16:{ *:[v8bf16] }:$vdata, (MUBUFOffset:{ *:[iPTR] } v4i32:{ *:[v4i32] }:$srsrc, i32:{ *:[i32] }:$soffset, i32:{ *:[i32] }:$offset))<<P:Predicate_unindexedstore>><<P:Predicate_store_global>>  =>  (BUFFER_STORE_DWORDX4_VBUFFER_OFFSET v8bf16:{ *:[v8bf16] }:$vdata, v4i32:{ *:[v4i32] }:$srsrc, i32:{ *:[i32] }:$soffset, i32:{ *:[i32] }:$offset)
      GIR_BuildMI, /*InsnID*/0, /*Opcode*/GIMT_Encode2(AMDGPU::BUFFER_STORE_DWORDX4_VBUFFER_OFFSET),
      GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/0, // vdata
      GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/0, // srsrc
      GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/1, // soffset
      GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/2, // offset
      GIR_AddImm8, /*InsnID*/0, /*Imm*/0,
      GIR_AddImm8, /*InsnID*/0, /*Imm*/0,
      GIR_MergeMemOperands, /*InsnID*/0, /*NumInsns*/1, /*MergeInsnID's*/0,
      GIR_ConstrainSelectedInstOperands, /*InsnID*/0,
      GIR_EraseFromParent, /*InsnID*/0,
      // GIR_Coverage, 3911,
      GIR_Done,
    // Label 2379: @156860
    GIM_Try, /*On fail goto*//*Label 2380*/ GIMT_Encode4(156980), // Rule ID 6730 //
      GIM_CheckFeatures, GIMT_Encode2(GIFBS_NotLDSRequiresM0Init),
      GIM_CheckMemoryAddressSpace, /*MI*/0, /*MMO*/0, /*NumAddrSpace*/1, /*AddrSpace*/3,
      GIM_CheckAtomicOrdering, /*MI*/0, /*Order*/(uint8_t)AtomicOrdering::NotAtomic,
      GIM_CheckPointerToAny, /*MI*/0, /*Op*/1, /*SizeInBits*/0,
      GIM_CheckComplexPattern, /*MI*/0, /*Op*/1, /*Renderer*/GIMT_Encode2(0), GIMT_Encode2(GICP_gi_ds_128bit_8byte_aligned),
      // (st v8i16:{ *:[v8i16] }:$value, (DS128Bit8ByteAligned:{ *:[iPTR] } i32:{ *:[i32] }:$ptr, i8:{ *:[i8] }:$offset0, i8:{ *:[i8] }:$offset1))<<P:Predicate_unindexedstore>><<P:Predicate_store_local>>  =>  (DS_WRITE2_B64_gfx9 ?:{ *:[i32] }:$ptr, (EXTRACT_SUBREG:{ *:[i64] } VReg_128:{ *:[v8i16] }:$value, sub0_sub1:{ *:[i32] }), (EXTRACT_SUBREG:{ *:[i64] } VReg_128:{ *:[v8i16] }:$value, sub2_sub3:{ *:[i32] }), ?:{ *:[i8] }:$offset0, ?:{ *:[i8] }:$offset1, 0:{ *:[i1] })
      GIR_MakeTempReg, /*TempRegID*/0, /*TypeID*/GILLT_s64,
      GIR_MakeTempReg, /*TempRegID*/1, /*TypeID*/GILLT_s64,
      GIR_BuildMI, /*InsnID*/2, /*Opcode*/GIMT_Encode2(TargetOpcode::COPY),
      GIR_AddTempRegister, /*InsnID*/2, /*TempRegID*/1, /*TempRegFlags*/GIMT_Encode2(RegState::Define),
      GIR_CopySubReg, /*NewInsnID*/2, /*OldInsnID*/0, /*OpIdx*/0, /*SubRegIdx*/GIMT_Encode2(24), // value
      GIR_ConstrainOperandRC, /*InsnID*/2, /*Op*/0, GIMT_Encode2(AMDGPU::VReg_64RegClassID),
      GIR_ConstrainOperandRC, /*InsnID*/2, /*Op*/1, GIMT_Encode2(AMDGPU::VReg_128RegClassID),
      GIR_BuildMI, /*InsnID*/1, /*Opcode*/GIMT_Encode2(TargetOpcode::COPY),
      GIR_AddTempRegister, /*InsnID*/1, /*TempRegID*/0, /*TempRegFlags*/GIMT_Encode2(RegState::Define),
      GIR_CopySubReg, /*NewInsnID*/1, /*OldInsnID*/0, /*OpIdx*/0, /*SubRegIdx*/GIMT_Encode2(4), // value
      GIR_ConstrainOperandRC, /*InsnID*/1, /*Op*/0, GIMT_Encode2(AMDGPU::VReg_64RegClassID),
      GIR_ConstrainOperandRC, /*InsnID*/1, /*Op*/1, GIMT_Encode2(AMDGPU::VReg_128RegClassID),
      GIR_BuildMI, /*InsnID*/0, /*Opcode*/GIMT_Encode2(AMDGPU::DS_WRITE2_B64_gfx9),
      GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/0, // ptr
      GIR_AddSimpleTempRegister, /*InsnID*/0, /*TempRegID*/0,
      GIR_AddSimpleTempRegister, /*InsnID*/0, /*TempRegID*/1,
      GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/1, // offset0
      GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/2, // offset1
      GIR_AddImm8, /*InsnID*/0, /*Imm*/0,
      GIR_MergeMemOperands, /*InsnID*/0, /*NumInsns*/1, /*MergeInsnID's*/0,
      GIR_ConstrainSelectedInstOperands, /*InsnID*/0,
      GIR_EraseFromParent, /*InsnID*/0,
      // GIR_Coverage, 6730,
      GIR_Done,
    // Label 2380: @156980
    GIM_Try, /*On fail goto*//*Label 2381*/ GIMT_Encode4(157100), // Rule ID 6734 //
      GIM_CheckFeatures, GIMT_Encode2(GIFBS_NotLDSRequiresM0Init),
      GIM_CheckMemoryAddressSpace, /*MI*/0, /*MMO*/0, /*NumAddrSpace*/1, /*AddrSpace*/3,
      GIM_CheckAtomicOrdering, /*MI*/0, /*Order*/(uint8_t)AtomicOrdering::NotAtomic,
      GIM_CheckPointerToAny, /*MI*/0, /*Op*/1, /*SizeInBits*/0,
      GIM_CheckComplexPattern, /*MI*/0, /*Op*/1, /*Renderer*/GIMT_Encode2(0), GIMT_Encode2(GICP_gi_ds_128bit_8byte_aligned),
      // (st v8f16:{ *:[v8f16] }:$value, (DS128Bit8ByteAligned:{ *:[iPTR] } i32:{ *:[i32] }:$ptr, i8:{ *:[i8] }:$offset0, i8:{ *:[i8] }:$offset1))<<P:Predicate_unindexedstore>><<P:Predicate_store_local>>  =>  (DS_WRITE2_B64_gfx9 ?:{ *:[i32] }:$ptr, (EXTRACT_SUBREG:{ *:[i64] } VReg_128:{ *:[v8f16] }:$value, sub0_sub1:{ *:[i32] }), (EXTRACT_SUBREG:{ *:[i64] } VReg_128:{ *:[v8f16] }:$value, sub2_sub3:{ *:[i32] }), ?:{ *:[i8] }:$offset0, ?:{ *:[i8] }:$offset1, 0:{ *:[i1] })
      GIR_MakeTempReg, /*TempRegID*/0, /*TypeID*/GILLT_s64,
      GIR_MakeTempReg, /*TempRegID*/1, /*TypeID*/GILLT_s64,
      GIR_BuildMI, /*InsnID*/2, /*Opcode*/GIMT_Encode2(TargetOpcode::COPY),
      GIR_AddTempRegister, /*InsnID*/2, /*TempRegID*/1, /*TempRegFlags*/GIMT_Encode2(RegState::Define),
      GIR_CopySubReg, /*NewInsnID*/2, /*OldInsnID*/0, /*OpIdx*/0, /*SubRegIdx*/GIMT_Encode2(24), // value
      GIR_ConstrainOperandRC, /*InsnID*/2, /*Op*/0, GIMT_Encode2(AMDGPU::VReg_64RegClassID),
      GIR_ConstrainOperandRC, /*InsnID*/2, /*Op*/1, GIMT_Encode2(AMDGPU::VReg_128RegClassID),
      GIR_BuildMI, /*InsnID*/1, /*Opcode*/GIMT_Encode2(TargetOpcode::COPY),
      GIR_AddTempRegister, /*InsnID*/1, /*TempRegID*/0, /*TempRegFlags*/GIMT_Encode2(RegState::Define),
      GIR_CopySubReg, /*NewInsnID*/1, /*OldInsnID*/0, /*OpIdx*/0, /*SubRegIdx*/GIMT_Encode2(4), // value
      GIR_ConstrainOperandRC, /*InsnID*/1, /*Op*/0, GIMT_Encode2(AMDGPU::VReg_64RegClassID),
      GIR_ConstrainOperandRC, /*InsnID*/1, /*Op*/1, GIMT_Encode2(AMDGPU::VReg_128RegClassID),
      GIR_BuildMI, /*InsnID*/0, /*Opcode*/GIMT_Encode2(AMDGPU::DS_WRITE2_B64_gfx9),
      GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/0, // ptr
      GIR_AddSimpleTempRegister, /*InsnID*/0, /*TempRegID*/0,
      GIR_AddSimpleTempRegister, /*InsnID*/0, /*TempRegID*/1,
      GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/1, // offset0
      GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/2, // offset1
      GIR_AddImm8, /*InsnID*/0, /*Imm*/0,
      GIR_MergeMemOperands, /*InsnID*/0, /*NumInsns*/1, /*MergeInsnID's*/0,
      GIR_ConstrainSelectedInstOperands, /*InsnID*/0,
      GIR_EraseFromParent, /*InsnID*/0,
      // GIR_Coverage, 6734,
      GIR_Done,
    // Label 2381: @157100
    GIM_Try, /*On fail goto*//*Label 2382*/ GIMT_Encode4(157220), // Rule ID 6738 //
      GIM_CheckFeatures, GIMT_Encode2(GIFBS_NotLDSRequiresM0Init),
      GIM_CheckMemoryAddressSpace, /*MI*/0, /*MMO*/0, /*NumAddrSpace*/1, /*AddrSpace*/3,
      GIM_CheckAtomicOrdering, /*MI*/0, /*Order*/(uint8_t)AtomicOrdering::NotAtomic,
      GIM_CheckPointerToAny, /*MI*/0, /*Op*/1, /*SizeInBits*/0,
      GIM_CheckComplexPattern, /*MI*/0, /*Op*/1, /*Renderer*/GIMT_Encode2(0), GIMT_Encode2(GICP_gi_ds_128bit_8byte_aligned),
      // (st v8bf16:{ *:[v8bf16] }:$value, (DS128Bit8ByteAligned:{ *:[iPTR] } i32:{ *:[i32] }:$ptr, i8:{ *:[i8] }:$offset0, i8:{ *:[i8] }:$offset1))<<P:Predicate_unindexedstore>><<P:Predicate_store_local>>  =>  (DS_WRITE2_B64_gfx9 ?:{ *:[i32] }:$ptr, (EXTRACT_SUBREG:{ *:[i64] } VReg_128:{ *:[v8bf16] }:$value, sub0_sub1:{ *:[i32] }), (EXTRACT_SUBREG:{ *:[i64] } VReg_128:{ *:[v8bf16] }:$value, sub2_sub3:{ *:[i32] }), ?:{ *:[i8] }:$offset0, ?:{ *:[i8] }:$offset1, 0:{ *:[i1] })
      GIR_MakeTempReg, /*TempRegID*/0, /*TypeID*/GILLT_s64,
      GIR_MakeTempReg, /*TempRegID*/1, /*TypeID*/GILLT_s64,
      GIR_BuildMI, /*InsnID*/2, /*Opcode*/GIMT_Encode2(TargetOpcode::COPY),
      GIR_AddTempRegister, /*InsnID*/2, /*TempRegID*/1, /*TempRegFlags*/GIMT_Encode2(RegState::Define),
      GIR_CopySubReg, /*NewInsnID*/2, /*OldInsnID*/0, /*OpIdx*/0, /*SubRegIdx*/GIMT_Encode2(24), // value
      GIR_ConstrainOperandRC, /*InsnID*/2, /*Op*/0, GIMT_Encode2(AMDGPU::VReg_64RegClassID),
      GIR_ConstrainOperandRC, /*InsnID*/2, /*Op*/1, GIMT_Encode2(AMDGPU::VReg_128RegClassID),
      GIR_BuildMI, /*InsnID*/1, /*Opcode*/GIMT_Encode2(TargetOpcode::COPY),
      GIR_AddTempRegister, /*InsnID*/1, /*TempRegID*/0, /*TempRegFlags*/GIMT_Encode2(RegState::Define),
      GIR_CopySubReg, /*NewInsnID*/1, /*OldInsnID*/0, /*OpIdx*/0, /*SubRegIdx*/GIMT_Encode2(4), // value
      GIR_ConstrainOperandRC, /*InsnID*/1, /*Op*/0, GIMT_Encode2(AMDGPU::VReg_64RegClassID),
      GIR_ConstrainOperandRC, /*InsnID*/1, /*Op*/1, GIMT_Encode2(AMDGPU::VReg_128RegClassID),
      GIR_BuildMI, /*InsnID*/0, /*Opcode*/GIMT_Encode2(AMDGPU::DS_WRITE2_B64_gfx9),
      GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/0, // ptr
      GIR_AddSimpleTempRegister, /*InsnID*/0, /*TempRegID*/0,
      GIR_AddSimpleTempRegister, /*InsnID*/0, /*TempRegID*/1,
      GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/1, // offset0
      GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/2, // offset1
      GIR_AddImm8, /*InsnID*/0, /*Imm*/0,
      GIR_MergeMemOperands, /*InsnID*/0, /*NumInsns*/1, /*MergeInsnID's*/0,
      GIR_ConstrainSelectedInstOperands, /*InsnID*/0,
      GIR_EraseFromParent, /*InsnID*/0,
      // GIR_Coverage, 6738,
      GIR_Done,
    // Label 2382: @157220
    GIM_Try, /*On fail goto*//*Label 2383*/ GIMT_Encode4(157282), // Rule ID 3089 //
      GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasFlatGlobalInsts),
      GIM_CheckMemoryAddressSpace, /*MI*/0, /*MMO*/0, /*NumAddrSpace*/1, /*AddrSpace*/1,
      GIM_CheckAtomicOrdering, /*MI*/0, /*Order*/(uint8_t)AtomicOrdering::NotAtomic,
      GIM_CheckPointerToAny, /*MI*/0, /*Op*/1, /*SizeInBits*/0,
      GIM_CheckComplexPattern, /*MI*/0, /*Op*/1, /*Renderer*/GIMT_Encode2(0), GIMT_Encode2(GICP_gi_global_saddr),
      // (st v8i16:{ *:[v8i16] }:$data, (GlobalSAddr:{ *:[iPTR] } SReg_64:{ *:[i64] }:$saddr, VGPR_32:{ *:[i32] }:$voffset, i32:{ *:[i32] }:$offset))<<P:Predicate_unindexedstore>><<P:Predicate_store_global>>  =>  (GLOBAL_STORE_DWORDX4_SADDR ?:{ *:[i32] }:$voffset, anonymous_15034:{ *:[v8i16] }:$data, ?:{ *:[i64] }:$saddr, ?:{ *:[i32] }:$offset)
      GIR_BuildMI, /*InsnID*/0, /*Opcode*/GIMT_Encode2(AMDGPU::GLOBAL_STORE_DWORDX4_SADDR),
      GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/1, // voffset
      GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/0, // data
      GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/0, // saddr
      GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/2, // offset
      GIR_AddImm8, /*InsnID*/0, /*Imm*/0,
      GIR_MergeMemOperands, /*InsnID*/0, /*NumInsns*/1, /*MergeInsnID's*/0,
      GIR_ConstrainSelectedInstOperands, /*InsnID*/0,
      GIR_EraseFromParent, /*InsnID*/0,
      // GIR_Coverage, 3089,
      GIR_Done,
    // Label 2383: @157282
    GIM_Try, /*On fail goto*//*Label 2384*/ GIMT_Encode4(157344), // Rule ID 3093 //
      GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasFlatGlobalInsts),
      GIM_CheckMemoryAddressSpace, /*MI*/0, /*MMO*/0, /*NumAddrSpace*/1, /*AddrSpace*/1,
      GIM_CheckAtomicOrdering, /*MI*/0, /*Order*/(uint8_t)AtomicOrdering::NotAtomic,
      GIM_CheckPointerToAny, /*MI*/0, /*Op*/1, /*SizeInBits*/0,
      GIM_CheckComplexPattern, /*MI*/0, /*Op*/1, /*Renderer*/GIMT_Encode2(0), GIMT_Encode2(GICP_gi_global_saddr),
      // (st v8f16:{ *:[v8f16] }:$data, (GlobalSAddr:{ *:[iPTR] } SReg_64:{ *:[i64] }:$saddr, VGPR_32:{ *:[i32] }:$voffset, i32:{ *:[i32] }:$offset))<<P:Predicate_unindexedstore>><<P:Predicate_store_global>>  =>  (GLOBAL_STORE_DWORDX4_SADDR ?:{ *:[i32] }:$voffset, anonymous_15034:{ *:[v8f16] }:$data, ?:{ *:[i64] }:$saddr, ?:{ *:[i32] }:$offset)
      GIR_BuildMI, /*InsnID*/0, /*Opcode*/GIMT_Encode2(AMDGPU::GLOBAL_STORE_DWORDX4_SADDR),
      GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/1, // voffset
      GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/0, // data
      GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/0, // saddr
      GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/2, // offset
      GIR_AddImm8, /*InsnID*/0, /*Imm*/0,
      GIR_MergeMemOperands, /*InsnID*/0, /*NumInsns*/1, /*MergeInsnID's*/0,
      GIR_ConstrainSelectedInstOperands, /*InsnID*/0,
      GIR_EraseFromParent, /*InsnID*/0,
      // GIR_Coverage, 3093,
      GIR_Done,
    // Label 2384: @157344
    GIM_Try, /*On fail goto*//*Label 2385*/ GIMT_Encode4(157406), // Rule ID 3097 //
      GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasFlatGlobalInsts),
      GIM_CheckMemoryAddressSpace, /*MI*/0, /*MMO*/0, /*NumAddrSpace*/1, /*AddrSpace*/1,
      GIM_CheckAtomicOrdering, /*MI*/0, /*Order*/(uint8_t)AtomicOrdering::NotAtomic,
      GIM_CheckPointerToAny, /*MI*/0, /*Op*/1, /*SizeInBits*/0,
      GIM_CheckComplexPattern, /*MI*/0, /*Op*/1, /*Renderer*/GIMT_Encode2(0), GIMT_Encode2(GICP_gi_global_saddr),
      // (st v8bf16:{ *:[v8bf16] }:$data, (GlobalSAddr:{ *:[iPTR] } SReg_64:{ *:[i64] }:$saddr, VGPR_32:{ *:[i32] }:$voffset, i32:{ *:[i32] }:$offset))<<P:Predicate_unindexedstore>><<P:Predicate_store_global>>  =>  (GLOBAL_STORE_DWORDX4_SADDR ?:{ *:[i32] }:$voffset, anonymous_15034:{ *:[v8bf16] }:$data, ?:{ *:[i64] }:$saddr, ?:{ *:[i32] }:$offset)
      GIR_BuildMI, /*InsnID*/0, /*Opcode*/GIMT_Encode2(AMDGPU::GLOBAL_STORE_DWORDX4_SADDR),
      GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/1, // voffset
      GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/0, // data
      GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/0, // saddr
      GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/2, // offset
      GIR_AddImm8, /*InsnID*/0, /*Imm*/0,
      GIR_MergeMemOperands, /*InsnID*/0, /*NumInsns*/1, /*MergeInsnID's*/0,
      GIR_ConstrainSelectedInstOperands, /*InsnID*/0,
      GIR_EraseFromParent, /*InsnID*/0,
      // GIR_Coverage, 3097,
      GIR_Done,
    // Label 2385: @157406
    GIM_Try, /*On fail goto*//*Label 2386*/ GIMT_Encode4(157463), // Rule ID 3088 //
      GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasFlatGlobalInsts),
      GIM_CheckMemoryAddressSpace, /*MI*/0, /*MMO*/0, /*NumAddrSpace*/1, /*AddrSpace*/1,
      GIM_CheckAtomicOrdering, /*MI*/0, /*Order*/(uint8_t)AtomicOrdering::NotAtomic,
      GIM_CheckPointerToAny, /*MI*/0, /*Op*/1, /*SizeInBits*/0,
      GIM_CheckComplexPattern, /*MI*/0, /*Op*/1, /*Renderer*/GIMT_Encode2(0), GIMT_Encode2(GICP_gi_global_offset),
      // (st v8i16:{ *:[v8i16] }:$data, (GlobalOffset:{ *:[iPTR] } i64:{ *:[i64] }:$vaddr, i32:{ *:[i32] }:$offset))<<P:Predicate_unindexedstore>><<P:Predicate_store_global>>  =>  (GLOBAL_STORE_DWORDX4 ?:{ *:[i64] }:$vaddr, anonymous_15034:{ *:[v8i16] }:$data, ?:{ *:[i32] }:$offset)
      GIR_BuildMI, /*InsnID*/0, /*Opcode*/GIMT_Encode2(AMDGPU::GLOBAL_STORE_DWORDX4),
      GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/0, // vaddr
      GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/0, // data
      GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/1, // offset
      GIR_AddImm8, /*InsnID*/0, /*Imm*/0,
      GIR_MergeMemOperands, /*InsnID*/0, /*NumInsns*/1, /*MergeInsnID's*/0,
      GIR_ConstrainSelectedInstOperands, /*InsnID*/0,
      GIR_EraseFromParent, /*InsnID*/0,
      // GIR_Coverage, 3088,
      GIR_Done,
    // Label 2386: @157463
    GIM_Try, /*On fail goto*//*Label 2387*/ GIMT_Encode4(157520), // Rule ID 3092 //
      GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasFlatGlobalInsts),
      GIM_CheckMemoryAddressSpace, /*MI*/0, /*MMO*/0, /*NumAddrSpace*/1, /*AddrSpace*/1,
      GIM_CheckAtomicOrdering, /*MI*/0, /*Order*/(uint8_t)AtomicOrdering::NotAtomic,
      GIM_CheckPointerToAny, /*MI*/0, /*Op*/1, /*SizeInBits*/0,
      GIM_CheckComplexPattern, /*MI*/0, /*Op*/1, /*Renderer*/GIMT_Encode2(0), GIMT_Encode2(GICP_gi_global_offset),
      // (st v8f16:{ *:[v8f16] }:$data, (GlobalOffset:{ *:[iPTR] } i64:{ *:[i64] }:$vaddr, i32:{ *:[i32] }:$offset))<<P:Predicate_unindexedstore>><<P:Predicate_store_global>>  =>  (GLOBAL_STORE_DWORDX4 ?:{ *:[i64] }:$vaddr, anonymous_15034:{ *:[v8f16] }:$data, ?:{ *:[i32] }:$offset)
      GIR_BuildMI, /*InsnID*/0, /*Opcode*/GIMT_Encode2(AMDGPU::GLOBAL_STORE_DWORDX4),
      GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/0, // vaddr
      GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/0, // data
      GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/1, // offset
      GIR_AddImm8, /*InsnID*/0, /*Imm*/0,
      GIR_MergeMemOperands, /*InsnID*/0, /*NumInsns*/1, /*MergeInsnID's*/0,
      GIR_ConstrainSelectedInstOperands, /*InsnID*/0,
      GIR_EraseFromParent, /*InsnID*/0,
      // GIR_Coverage, 3092,
      GIR_Done,
    // Label 2387: @157520
    GIM_Try, /*On fail goto*//*Label 2388*/ GIMT_Encode4(157577), // Rule ID 3096 //
      GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasFlatGlobalInsts),
      GIM_CheckMemoryAddressSpace, /*MI*/0, /*MMO*/0, /*NumAddrSpace*/1, /*AddrSpace*/1,
      GIM_CheckAtomicOrdering, /*MI*/0, /*Order*/(uint8_t)AtomicOrdering::NotAtomic,
      GIM_CheckPointerToAny, /*MI*/0, /*Op*/1, /*SizeInBits*/0,
      GIM_CheckComplexPattern, /*MI*/0, /*Op*/1, /*Renderer*/GIMT_Encode2(0), GIMT_Encode2(GICP_gi_global_offset),
      // (st v8bf16:{ *:[v8bf16] }:$data, (GlobalOffset:{ *:[iPTR] } i64:{ *:[i64] }:$vaddr, i32:{ *:[i32] }:$offset))<<P:Predicate_unindexedstore>><<P:Predicate_store_global>>  =>  (GLOBAL_STORE_DWORDX4 ?:{ *:[i64] }:$vaddr, anonymous_15034:{ *:[v8bf16] }:$data, ?:{ *:[i32] }:$offset)
      GIR_BuildMI, /*InsnID*/0, /*Opcode*/GIMT_Encode2(AMDGPU::GLOBAL_STORE_DWORDX4),
      GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/0, // vaddr
      GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/0, // data
      GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/1, // offset
      GIR_AddImm8, /*InsnID*/0, /*Imm*/0,
      GIR_MergeMemOperands, /*InsnID*/0, /*NumInsns*/1, /*MergeInsnID's*/0,
      GIR_ConstrainSelectedInstOperands, /*InsnID*/0,
      GIR_EraseFromParent, /*InsnID*/0,
      // GIR_Coverage, 3096,
      GIR_Done,
    // Label 2388: @157577
    GIM_Try, /*On fail goto*//*Label 2389*/ GIMT_Encode4(157635), // Rule ID 2818 //
      GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasFlatAddressSpace),
      GIM_CheckMemoryAddressSpace, /*MI*/0, /*MMO*/0, /*NumAddrSpace*/2, /*AddrSpace*/0, /*AddrSpace*/1,
      GIM_CheckAtomicOrdering, /*MI*/0, /*Order*/(uint8_t)AtomicOrdering::NotAtomic,
      GIM_CheckPointerToAny, /*MI*/0, /*Op*/1, /*SizeInBits*/0,
      GIM_CheckComplexPattern, /*MI*/0, /*Op*/1, /*Renderer*/GIMT_Encode2(0), GIMT_Encode2(GICP_gi_flat_offset),
      // (st v8i16:{ *:[v8i16] }:$data, (FlatOffset:{ *:[iPTR] } i64:{ *:[i64] }:$vaddr, i32:{ *:[i32] }:$offset))<<P:Predicate_unindexedstore>><<P:Predicate_store_flat>>  =>  (FLAT_STORE_DWORDX4 ?:{ *:[i64] }:$vaddr, anonymous_15034:{ *:[v8i16] }:$data, ?:{ *:[i32] }:$offset)
      GIR_BuildMI, /*InsnID*/0, /*Opcode*/GIMT_Encode2(AMDGPU::FLAT_STORE_DWORDX4),
      GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/0, // vaddr
      GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/0, // data
      GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/1, // offset
      GIR_AddImm8, /*InsnID*/0, /*Imm*/0,
      GIR_MergeMemOperands, /*InsnID*/0, /*NumInsns*/1, /*MergeInsnID's*/0,
      GIR_ConstrainSelectedInstOperands, /*InsnID*/0,
      GIR_EraseFromParent, /*InsnID*/0,
      // GIR_Coverage, 2818,
      GIR_Done,
    // Label 2389: @157635
    GIM_Try, /*On fail goto*//*Label 2390*/ GIMT_Encode4(157693), // Rule ID 2820 //
      GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasFlatAddressSpace),
      GIM_CheckMemoryAddressSpace, /*MI*/0, /*MMO*/0, /*NumAddrSpace*/2, /*AddrSpace*/0, /*AddrSpace*/1,
      GIM_CheckAtomicOrdering, /*MI*/0, /*Order*/(uint8_t)AtomicOrdering::NotAtomic,
      GIM_CheckPointerToAny, /*MI*/0, /*Op*/1, /*SizeInBits*/0,
      GIM_CheckComplexPattern, /*MI*/0, /*Op*/1, /*Renderer*/GIMT_Encode2(0), GIMT_Encode2(GICP_gi_flat_offset),
      // (st v8f16:{ *:[v8f16] }:$data, (FlatOffset:{ *:[iPTR] } i64:{ *:[i64] }:$vaddr, i32:{ *:[i32] }:$offset))<<P:Predicate_unindexedstore>><<P:Predicate_store_flat>>  =>  (FLAT_STORE_DWORDX4 ?:{ *:[i64] }:$vaddr, anonymous_15034:{ *:[v8f16] }:$data, ?:{ *:[i32] }:$offset)
      GIR_BuildMI, /*InsnID*/0, /*Opcode*/GIMT_Encode2(AMDGPU::FLAT_STORE_DWORDX4),
      GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/0, // vaddr
      GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/0, // data
      GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/1, // offset
      GIR_AddImm8, /*InsnID*/0, /*Imm*/0,
      GIR_MergeMemOperands, /*InsnID*/0, /*NumInsns*/1, /*MergeInsnID's*/0,
      GIR_ConstrainSelectedInstOperands, /*InsnID*/0,
      GIR_EraseFromParent, /*InsnID*/0,
      // GIR_Coverage, 2820,
      GIR_Done,
    // Label 2390: @157693
    GIM_Try, /*On fail goto*//*Label 2391*/ GIMT_Encode4(157751), // Rule ID 2822 //
      GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasFlatAddressSpace),
      GIM_CheckMemoryAddressSpace, /*MI*/0, /*MMO*/0, /*NumAddrSpace*/2, /*AddrSpace*/0, /*AddrSpace*/1,
      GIM_CheckAtomicOrdering, /*MI*/0, /*Order*/(uint8_t)AtomicOrdering::NotAtomic,
      GIM_CheckPointerToAny, /*MI*/0, /*Op*/1, /*SizeInBits*/0,
      GIM_CheckComplexPattern, /*MI*/0, /*Op*/1, /*Renderer*/GIMT_Encode2(0), GIMT_Encode2(GICP_gi_flat_offset),
      // (st v8bf16:{ *:[v8bf16] }:$data, (FlatOffset:{ *:[iPTR] } i64:{ *:[i64] }:$vaddr, i32:{ *:[i32] }:$offset))<<P:Predicate_unindexedstore>><<P:Predicate_store_flat>>  =>  (FLAT_STORE_DWORDX4 ?:{ *:[i64] }:$vaddr, anonymous_15034:{ *:[v8bf16] }:$data, ?:{ *:[i32] }:$offset)
      GIR_BuildMI, /*InsnID*/0, /*Opcode*/GIMT_Encode2(AMDGPU::FLAT_STORE_DWORDX4),
      GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/0, // vaddr
      GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/0, // data
      GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/1, // offset
      GIR_AddImm8, /*InsnID*/0, /*Imm*/0,
      GIR_MergeMemOperands, /*InsnID*/0, /*NumInsns*/1, /*MergeInsnID's*/0,
      GIR_ConstrainSelectedInstOperands, /*InsnID*/0,
      GIR_EraseFromParent, /*InsnID*/0,
      // GIR_Coverage, 2822,
      GIR_Done,
    // Label 2391: @157751
    GIM_Reject,
    // Label 1823: @157752
    GIM_Reject,
    // Label 16: @157753
    GIM_SwitchType, /*MI*/0, /*Op*/0, /*[*/GIMT_Encode2(9), GIMT_Encode2(11), /*)*//*default:*//*Label 2394*/ GIMT_Encode4(159072),
    /*GILLT_s32*//*Label 2392*/ GIMT_Encode4(157772),
    /*GILLT_s64*//*Label 2393*/ GIMT_Encode4(158422),
    // Label 2392: @157772
    GIM_Try, /*On fail goto*//*Label 2395*/ GIMT_Encode4(158421),
      GIM_CheckType, /*MI*/0, /*Op*/2, /*Type*/GILLT_s32,
      GIM_CheckType, /*MI*/0, /*Op*/3, /*Type*/GILLT_s32,
      GIM_Try, /*On fail goto*//*Label 2396*/ GIMT_Encode4(157845), // Rule ID 6901 //
        GIM_CheckFeatures, GIMT_Encode2(GIFBS_LDSRequiresM0Init_isGFX6GFX7GFX8GFX9GFX10),
        GIM_CheckMemoryAddressSpace, /*MI*/0, /*MMO*/0, /*NumAddrSpace*/1, /*AddrSpace*/3,
        GIM_CheckHasNoUse, /*MI*/0,
        GIM_CheckPointerToAny, /*MI*/0, /*Op*/1, /*SizeInBits*/0,
        GIM_CheckComplexPattern, /*MI*/0, /*Op*/1, /*Renderer*/GIMT_Encode2(0), GIMT_Encode2(GICP_gi_ds_1addr_1offset),
        // (atomic_cmp_swap_glue:{ *:[i32] } (DS1Addr1Offset:{ *:[iPTR] } i32:{ *:[i32] }:$ptr, i32:{ *:[i32] }:$offset), i32:{ *:[i32] }:$cmp, i32:{ *:[i32] }:$swap)<<P:Predicate_atomic_cmp_swap_local_m0_noret_32>>  =>  (DS_CMPST_B32 ?:{ *:[i32] }:$ptr, anonymous_15037:{ *:[i32] }:$cmp, anonymous_15037:{ *:[i32] }:$swap, offset:{ *:[i32] }:$offset, 0:{ *:[i1] })
        GIR_BuildMI, /*InsnID*/0, /*Opcode*/GIMT_Encode2(AMDGPU::DS_CMPST_B32),
        GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/0, // ptr
        GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/2, // cmp
        GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/3, // swap
        GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/1, // offset
        GIR_AddImm8, /*InsnID*/0, /*Imm*/0,
        GIR_MergeMemOperands, /*InsnID*/0, /*NumInsns*/1, /*MergeInsnID's*/0,
        GIR_ConstrainSelectedInstOperands, /*InsnID*/0,
        GIR_EraseFromParent, /*InsnID*/0,
        // GIR_Coverage, 6901,
        GIR_Done,
      // Label 2396: @157845
      GIM_Try, /*On fail goto*//*Label 2397*/ GIMT_Encode4(157905), // Rule ID 6903 //
        GIM_CheckFeatures, GIMT_Encode2(GIFBS_NotLDSRequiresM0Init_isGFX6GFX7GFX8GFX9GFX10),
        GIM_CheckMemoryAddressSpace, /*MI*/0, /*MMO*/0, /*NumAddrSpace*/1, /*AddrSpace*/3,
        GIM_CheckHasNoUse, /*MI*/0,
        GIM_CheckPointerToAny, /*MI*/0, /*Op*/1, /*SizeInBits*/0,
        GIM_CheckComplexPattern, /*MI*/0, /*Op*/1, /*Renderer*/GIMT_Encode2(0), GIMT_Encode2(GICP_gi_ds_1addr_1offset),
        // (atomic_cmp_swap:{ *:[i32] } (DS1Addr1Offset:{ *:[iPTR] } i32:{ *:[i32] }:$ptr, i32:{ *:[i32] }:$offset), i32:{ *:[i32] }:$cmp, i32:{ *:[i32] }:$swap)<<P:Predicate_atomic_cmp_swap_local_noret_32>>  =>  (DS_CMPST_B32_gfx9 ?:{ *:[i32] }:$ptr, anonymous_15037:{ *:[i32] }:$cmp, anonymous_15037:{ *:[i32] }:$swap, offset:{ *:[i32] }:$offset, 0:{ *:[i1] })
        GIR_BuildMI, /*InsnID*/0, /*Opcode*/GIMT_Encode2(AMDGPU::DS_CMPST_B32_gfx9),
        GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/0, // ptr
        GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/2, // cmp
        GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/3, // swap
        GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/1, // offset
        GIR_AddImm8, /*InsnID*/0, /*Imm*/0,
        GIR_MergeMemOperands, /*InsnID*/0, /*NumInsns*/1, /*MergeInsnID's*/0,
        GIR_ConstrainSelectedInstOperands, /*InsnID*/0,
        GIR_EraseFromParent, /*InsnID*/0,
        // GIR_Coverage, 6903,
        GIR_Done,
      // Label 2397: @157905
      GIM_Try, /*On fail goto*//*Label 2398*/ GIMT_Encode4(157965), // Rule ID 6905 //
        GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasGDS_isGFX6GFX7GFX8GFX9GFX10),
        GIM_CheckMemoryAddressSpace, /*MI*/0, /*MMO*/0, /*NumAddrSpace*/1, /*AddrSpace*/2,
        GIM_CheckHasNoUse, /*MI*/0,
        GIM_CheckPointerToAny, /*MI*/0, /*Op*/1, /*SizeInBits*/0,
        GIM_CheckComplexPattern, /*MI*/0, /*Op*/1, /*Renderer*/GIMT_Encode2(0), GIMT_Encode2(GICP_gi_ds_1addr_1offset),
        // (atomic_cmp_swap_glue:{ *:[i32] } (DS1Addr1Offset:{ *:[iPTR] } i32:{ *:[i32] }:$ptr, i32:{ *:[i32] }:$offset), i32:{ *:[i32] }:$cmp, i32:{ *:[i32] }:$swap)<<P:Predicate_atomic_cmp_swap_region_m0_noret_32>>  =>  (DS_CMPST_B32 ?:{ *:[i32] }:$ptr, anonymous_15037:{ *:[i32] }:$cmp, anonymous_15037:{ *:[i32] }:$swap, offset:{ *:[i32] }:$offset, 1:{ *:[i1] })
        GIR_BuildMI, /*InsnID*/0, /*Opcode*/GIMT_Encode2(AMDGPU::DS_CMPST_B32),
        GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/0, // ptr
        GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/2, // cmp
        GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/3, // swap
        GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/1, // offset
        GIR_AddImm8, /*InsnID*/0, /*Imm*/1,
        GIR_MergeMemOperands, /*InsnID*/0, /*NumInsns*/1, /*MergeInsnID's*/0,
        GIR_ConstrainSelectedInstOperands, /*InsnID*/0,
        GIR_EraseFromParent, /*InsnID*/0,
        // GIR_Coverage, 6905,
        GIR_Done,
      // Label 2398: @157965
      GIM_Try, /*On fail goto*//*Label 2399*/ GIMT_Encode4(158025), // Rule ID 6907 //
        GIM_CheckFeatures, GIMT_Encode2(GIFBS_isGFX11Plus),
        GIM_CheckMemoryAddressSpace, /*MI*/0, /*MMO*/0, /*NumAddrSpace*/1, /*AddrSpace*/3,
        GIM_CheckHasNoUse, /*MI*/0,
        GIM_CheckPointerToAny, /*MI*/0, /*Op*/1, /*SizeInBits*/0,
        GIM_CheckComplexPattern, /*MI*/0, /*Op*/1, /*Renderer*/GIMT_Encode2(0), GIMT_Encode2(GICP_gi_ds_1addr_1offset),
        // (atomic_cmp_swap:{ *:[i32] } (DS1Addr1Offset:{ *:[iPTR] } i32:{ *:[i32] }:$ptr, i32:{ *:[i32] }:$offset), i32:{ *:[i32] }:$cmp, i32:{ *:[i32] }:$swap)<<P:Predicate_atomic_cmp_swap_local_noret_32>>  =>  (DS_CMPSTORE_B32_gfx9 ?:{ *:[i32] }:$ptr, anonymous_15037:{ *:[i32] }:$swap, anonymous_15037:{ *:[i32] }:$cmp, offset:{ *:[i32] }:$offset, 0:{ *:[i1] })
        GIR_BuildMI, /*InsnID*/0, /*Opcode*/GIMT_Encode2(AMDGPU::DS_CMPSTORE_B32_gfx9),
        GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/0, // ptr
        GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/3, // swap
        GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/2, // cmp
        GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/1, // offset
        GIR_AddImm8, /*InsnID*/0, /*Imm*/0,
        GIR_MergeMemOperands, /*InsnID*/0, /*NumInsns*/1, /*MergeInsnID's*/0,
        GIR_ConstrainSelectedInstOperands, /*InsnID*/0,
        GIR_EraseFromParent, /*InsnID*/0,
        // GIR_Coverage, 6907,
        GIR_Done,
      // Label 2399: @158025
      GIM_Try, /*On fail goto*//*Label 2400*/ GIMT_Encode4(158085), // Rule ID 6909 //
        GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasGDS_isGFX11Plus),
        GIM_CheckMemoryAddressSpace, /*MI*/0, /*MMO*/0, /*NumAddrSpace*/1, /*AddrSpace*/2,
        GIM_CheckHasNoUse, /*MI*/0,
        GIM_CheckPointerToAny, /*MI*/0, /*Op*/1, /*SizeInBits*/0,
        GIM_CheckComplexPattern, /*MI*/0, /*Op*/1, /*Renderer*/GIMT_Encode2(0), GIMT_Encode2(GICP_gi_ds_1addr_1offset),
        // (atomic_cmp_swap_glue:{ *:[i32] } (DS1Addr1Offset:{ *:[iPTR] } i32:{ *:[i32] }:$ptr, i32:{ *:[i32] }:$offset), i32:{ *:[i32] }:$cmp, i32:{ *:[i32] }:$swap)<<P:Predicate_atomic_cmp_swap_region_m0_noret_32>>  =>  (DS_CMPSTORE_B32 ?:{ *:[i32] }:$ptr, anonymous_15037:{ *:[i32] }:$swap, anonymous_15037:{ *:[i32] }:$cmp, offset:{ *:[i32] }:$offset, 1:{ *:[i1] })
        GIR_BuildMI, /*InsnID*/0, /*Opcode*/GIMT_Encode2(AMDGPU::DS_CMPSTORE_B32),
        GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/0, // ptr
        GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/3, // swap
        GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/2, // cmp
        GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/1, // offset
        GIR_AddImm8, /*InsnID*/0, /*Imm*/1,
        GIR_MergeMemOperands, /*InsnID*/0, /*NumInsns*/1, /*MergeInsnID's*/0,
        GIR_ConstrainSelectedInstOperands, /*InsnID*/0,
        GIR_EraseFromParent, /*InsnID*/0,
        // GIR_Coverage, 6909,
        GIR_Done,
      // Label 2400: @158085
      GIM_Try, /*On fail goto*//*Label 2401*/ GIMT_Encode4(158152), // Rule ID 6900 //
        GIM_CheckFeatures, GIMT_Encode2(GIFBS_LDSRequiresM0Init_isGFX6GFX7GFX8GFX9GFX10),
        GIM_CheckMemoryAddressSpace, /*MI*/0, /*MMO*/0, /*NumAddrSpace*/1, /*AddrSpace*/3,
        GIM_CheckRegBankForClass, /*MI*/0, /*Op*/0, /*RC*/GIMT_Encode2(AMDGPU::AV_32RegClassID),
        GIM_CheckPointerToAny, /*MI*/0, /*Op*/1, /*SizeInBits*/0,
        GIM_CheckComplexPattern, /*MI*/0, /*Op*/1, /*Renderer*/GIMT_Encode2(0), GIMT_Encode2(GICP_gi_ds_1addr_1offset),
        // (atomic_cmp_swap_glue:{ *:[i32] } (DS1Addr1Offset:{ *:[iPTR] } i32:{ *:[i32] }:$ptr, i32:{ *:[i32] }:$offset), i32:{ *:[i32] }:$cmp, i32:{ *:[i32] }:$swap)<<P:Predicate_atomic_cmp_swap_local_m0_32>>  =>  (DS_CMPST_RTN_B32:{ *:[i32] } ?:{ *:[i32] }:$ptr, anonymous_15037:{ *:[i32] }:$cmp, anonymous_15037:{ *:[i32] }:$swap, offset:{ *:[i32] }:$offset, 0:{ *:[i1] })
        GIR_BuildMI, /*InsnID*/0, /*Opcode*/GIMT_Encode2(AMDGPU::DS_CMPST_RTN_B32),
        GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/0, // DstI[vdst]
        GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/0, // ptr
        GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/2, // cmp
        GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/3, // swap
        GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/1, // offset
        GIR_AddImm8, /*InsnID*/0, /*Imm*/0,
        GIR_MergeMemOperands, /*InsnID*/0, /*NumInsns*/1, /*MergeInsnID's*/0,
        GIR_ConstrainSelectedInstOperands, /*InsnID*/0,
        GIR_EraseFromParent, /*InsnID*/0,
        // GIR_Coverage, 6900,
        GIR_Done,
      // Label 2401: @158152
      GIM_Try, /*On fail goto*//*Label 2402*/ GIMT_Encode4(158219), // Rule ID 6902 //
        GIM_CheckFeatures, GIMT_Encode2(GIFBS_NotLDSRequiresM0Init_isGFX6GFX7GFX8GFX9GFX10),
        GIM_CheckMemoryAddressSpace, /*MI*/0, /*MMO*/0, /*NumAddrSpace*/1, /*AddrSpace*/3,
        GIM_CheckRegBankForClass, /*MI*/0, /*Op*/0, /*RC*/GIMT_Encode2(AMDGPU::AV_32RegClassID),
        GIM_CheckPointerToAny, /*MI*/0, /*Op*/1, /*SizeInBits*/0,
        GIM_CheckComplexPattern, /*MI*/0, /*Op*/1, /*Renderer*/GIMT_Encode2(0), GIMT_Encode2(GICP_gi_ds_1addr_1offset),
        // (atomic_cmp_swap:{ *:[i32] } (DS1Addr1Offset:{ *:[iPTR] } i32:{ *:[i32] }:$ptr, i32:{ *:[i32] }:$offset), i32:{ *:[i32] }:$cmp, i32:{ *:[i32] }:$swap)<<P:Predicate_atomic_cmp_swap_local_32>>  =>  (DS_CMPST_RTN_B32_gfx9:{ *:[i32] } ?:{ *:[i32] }:$ptr, anonymous_15037:{ *:[i32] }:$cmp, anonymous_15037:{ *:[i32] }:$swap, offset:{ *:[i32] }:$offset, 0:{ *:[i1] })
        GIR_BuildMI, /*InsnID*/0, /*Opcode*/GIMT_Encode2(AMDGPU::DS_CMPST_RTN_B32_gfx9),
        GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/0, // DstI[vdst]
        GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/0, // ptr
        GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/2, // cmp
        GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/3, // swap
        GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/1, // offset
        GIR_AddImm8, /*InsnID*/0, /*Imm*/0,
        GIR_MergeMemOperands, /*InsnID*/0, /*NumInsns*/1, /*MergeInsnID's*/0,
        GIR_ConstrainSelectedInstOperands, /*InsnID*/0,
        GIR_EraseFromParent, /*InsnID*/0,
        // GIR_Coverage, 6902,
        GIR_Done,
      // Label 2402: @158219
      GIM_Try, /*On fail goto*//*Label 2403*/ GIMT_Encode4(158286), // Rule ID 6904 //
        GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasGDS_isGFX6GFX7GFX8GFX9GFX10),
        GIM_CheckMemoryAddressSpace, /*MI*/0, /*MMO*/0, /*NumAddrSpace*/1, /*AddrSpace*/2,
        GIM_CheckRegBankForClass, /*MI*/0, /*Op*/0, /*RC*/GIMT_Encode2(AMDGPU::AV_32RegClassID),
        GIM_CheckPointerToAny, /*MI*/0, /*Op*/1, /*SizeInBits*/0,
        GIM_CheckComplexPattern, /*MI*/0, /*Op*/1, /*Renderer*/GIMT_Encode2(0), GIMT_Encode2(GICP_gi_ds_1addr_1offset),
        // (atomic_cmp_swap_glue:{ *:[i32] } (DS1Addr1Offset:{ *:[iPTR] } i32:{ *:[i32] }:$ptr, i32:{ *:[i32] }:$offset), i32:{ *:[i32] }:$cmp, i32:{ *:[i32] }:$swap)<<P:Predicate_atomic_cmp_swap_region_m0_32>>  =>  (DS_CMPST_RTN_B32:{ *:[i32] } ?:{ *:[i32] }:$ptr, anonymous_15037:{ *:[i32] }:$cmp, anonymous_15037:{ *:[i32] }:$swap, offset:{ *:[i32] }:$offset, 1:{ *:[i1] })
        GIR_BuildMI, /*InsnID*/0, /*Opcode*/GIMT_Encode2(AMDGPU::DS_CMPST_RTN_B32),
        GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/0, // DstI[vdst]
        GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/0, // ptr
        GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/2, // cmp
        GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/3, // swap
        GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/1, // offset
        GIR_AddImm8, /*InsnID*/0, /*Imm*/1,
        GIR_MergeMemOperands, /*InsnID*/0, /*NumInsns*/1, /*MergeInsnID's*/0,
        GIR_ConstrainSelectedInstOperands, /*InsnID*/0,
        GIR_EraseFromParent, /*InsnID*/0,
        // GIR_Coverage, 6904,
        GIR_Done,
      // Label 2403: @158286
      GIM_Try, /*On fail goto*//*Label 2404*/ GIMT_Encode4(158353), // Rule ID 6906 //
        GIM_CheckFeatures, GIMT_Encode2(GIFBS_isGFX11Plus),
        GIM_CheckMemoryAddressSpace, /*MI*/0, /*MMO*/0, /*NumAddrSpace*/1, /*AddrSpace*/3,
        GIM_CheckRegBankForClass, /*MI*/0, /*Op*/0, /*RC*/GIMT_Encode2(AMDGPU::AV_32RegClassID),
        GIM_CheckPointerToAny, /*MI*/0, /*Op*/1, /*SizeInBits*/0,
        GIM_CheckComplexPattern, /*MI*/0, /*Op*/1, /*Renderer*/GIMT_Encode2(0), GIMT_Encode2(GICP_gi_ds_1addr_1offset),
        // (atomic_cmp_swap:{ *:[i32] } (DS1Addr1Offset:{ *:[iPTR] } i32:{ *:[i32] }:$ptr, i32:{ *:[i32] }:$offset), i32:{ *:[i32] }:$cmp, i32:{ *:[i32] }:$swap)<<P:Predicate_atomic_cmp_swap_local_32>>  =>  (DS_CMPSTORE_RTN_B32_gfx9:{ *:[i32] } ?:{ *:[i32] }:$ptr, anonymous_15037:{ *:[i32] }:$swap, anonymous_15037:{ *:[i32] }:$cmp, offset:{ *:[i32] }:$offset, 0:{ *:[i1] })
        GIR_BuildMI, /*InsnID*/0, /*Opcode*/GIMT_Encode2(AMDGPU::DS_CMPSTORE_RTN_B32_gfx9),
        GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/0, // DstI[vdst]
        GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/0, // ptr
        GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/3, // swap
        GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/2, // cmp
        GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/1, // offset
        GIR_AddImm8, /*InsnID*/0, /*Imm*/0,
        GIR_MergeMemOperands, /*InsnID*/0, /*NumInsns*/1, /*MergeInsnID's*/0,
        GIR_ConstrainSelectedInstOperands, /*InsnID*/0,
        GIR_EraseFromParent, /*InsnID*/0,
        // GIR_Coverage, 6906,
        GIR_Done,
      // Label 2404: @158353
      GIM_Try, /*On fail goto*//*Label 2405*/ GIMT_Encode4(158420), // Rule ID 6908 //
        GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasGDS_isGFX11Plus),
        GIM_CheckMemoryAddressSpace, /*MI*/0, /*MMO*/0, /*NumAddrSpace*/1, /*AddrSpace*/2,
        GIM_CheckRegBankForClass, /*MI*/0, /*Op*/0, /*RC*/GIMT_Encode2(AMDGPU::AV_32RegClassID),
        GIM_CheckPointerToAny, /*MI*/0, /*Op*/1, /*SizeInBits*/0,
        GIM_CheckComplexPattern, /*MI*/0, /*Op*/1, /*Renderer*/GIMT_Encode2(0), GIMT_Encode2(GICP_gi_ds_1addr_1offset),
        // (atomic_cmp_swap_glue:{ *:[i32] } (DS1Addr1Offset:{ *:[iPTR] } i32:{ *:[i32] }:$ptr, i32:{ *:[i32] }:$offset), i32:{ *:[i32] }:$cmp, i32:{ *:[i32] }:$swap)<<P:Predicate_atomic_cmp_swap_region_m0_32>>  =>  (DS_CMPSTORE_RTN_B32:{ *:[i32] } ?:{ *:[i32] }:$ptr, anonymous_15037:{ *:[i32] }:$swap, anonymous_15037:{ *:[i32] }:$cmp, offset:{ *:[i32] }:$offset, 1:{ *:[i1] })
        GIR_BuildMI, /*InsnID*/0, /*Opcode*/GIMT_Encode2(AMDGPU::DS_CMPSTORE_RTN_B32),
        GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/0, // DstI[vdst]
        GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/0, // ptr
        GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/3, // swap
        GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/2, // cmp
        GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/1, // offset
        GIR_AddImm8, /*InsnID*/0, /*Imm*/1,
        GIR_MergeMemOperands, /*InsnID*/0, /*NumInsns*/1, /*MergeInsnID's*/0,
        GIR_ConstrainSelectedInstOperands, /*InsnID*/0,
        GIR_EraseFromParent, /*InsnID*/0,
        // GIR_Coverage, 6908,
        GIR_Done,
      // Label 2405: @158420
      GIM_Reject,
    // Label 2395: @158421
    GIM_Reject,
    // Label 2393: @158422
    GIM_Try, /*On fail goto*//*Label 2406*/ GIMT_Encode4(159071),
      GIM_CheckType, /*MI*/0, /*Op*/2, /*Type*/GILLT_s64,
      GIM_CheckType, /*MI*/0, /*Op*/3, /*Type*/GILLT_s64,
      GIM_Try, /*On fail goto*//*Label 2407*/ GIMT_Encode4(158495), // Rule ID 7070 //
        GIM_CheckFeatures, GIMT_Encode2(GIFBS_LDSRequiresM0Init_isGFX6GFX7GFX8GFX9GFX10),
        GIM_CheckMemoryAddressSpace, /*MI*/0, /*MMO*/0, /*NumAddrSpace*/1, /*AddrSpace*/3,
        GIM_CheckHasNoUse, /*MI*/0,
        GIM_CheckPointerToAny, /*MI*/0, /*Op*/1, /*SizeInBits*/0,
        GIM_CheckComplexPattern, /*MI*/0, /*Op*/1, /*Renderer*/GIMT_Encode2(0), GIMT_Encode2(GICP_gi_ds_1addr_1offset),
        // (atomic_cmp_swap_glue:{ *:[i64] } (DS1Addr1Offset:{ *:[iPTR] } i32:{ *:[i32] }:$ptr, i32:{ *:[i32] }:$offset), i64:{ *:[i64] }:$cmp, i64:{ *:[i64] }:$swap)<<P:Predicate_atomic_cmp_swap_local_m0_noret_64>>  =>  (DS_CMPST_B64 ?:{ *:[i32] }:$ptr, anonymous_15036:{ *:[i64] }:$cmp, anonymous_15036:{ *:[i64] }:$swap, offset:{ *:[i32] }:$offset, 0:{ *:[i1] })
        GIR_BuildMI, /*InsnID*/0, /*Opcode*/GIMT_Encode2(AMDGPU::DS_CMPST_B64),
        GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/0, // ptr
        GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/2, // cmp
        GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/3, // swap
        GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/1, // offset
        GIR_AddImm8, /*InsnID*/0, /*Imm*/0,
        GIR_MergeMemOperands, /*InsnID*/0, /*NumInsns*/1, /*MergeInsnID's*/0,
        GIR_ConstrainSelectedInstOperands, /*InsnID*/0,
        GIR_EraseFromParent, /*InsnID*/0,
        // GIR_Coverage, 7070,
        GIR_Done,
      // Label 2407: @158495
      GIM_Try, /*On fail goto*//*Label 2408*/ GIMT_Encode4(158555), // Rule ID 7072 //
        GIM_CheckFeatures, GIMT_Encode2(GIFBS_NotLDSRequiresM0Init_isGFX6GFX7GFX8GFX9GFX10),
        GIM_CheckMemoryAddressSpace, /*MI*/0, /*MMO*/0, /*NumAddrSpace*/1, /*AddrSpace*/3,
        GIM_CheckHasNoUse, /*MI*/0,
        GIM_CheckPointerToAny, /*MI*/0, /*Op*/1, /*SizeInBits*/0,
        GIM_CheckComplexPattern, /*MI*/0, /*Op*/1, /*Renderer*/GIMT_Encode2(0), GIMT_Encode2(GICP_gi_ds_1addr_1offset),
        // (atomic_cmp_swap:{ *:[i64] } (DS1Addr1Offset:{ *:[iPTR] } i32:{ *:[i32] }:$ptr, i32:{ *:[i32] }:$offset), i64:{ *:[i64] }:$cmp, i64:{ *:[i64] }:$swap)<<P:Predicate_atomic_cmp_swap_local_noret_64>>  =>  (DS_CMPST_B64_gfx9 ?:{ *:[i32] }:$ptr, anonymous_15036:{ *:[i64] }:$cmp, anonymous_15036:{ *:[i64] }:$swap, offset:{ *:[i32] }:$offset, 0:{ *:[i1] })
        GIR_BuildMI, /*InsnID*/0, /*Opcode*/GIMT_Encode2(AMDGPU::DS_CMPST_B64_gfx9),
        GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/0, // ptr
        GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/2, // cmp
        GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/3, // swap
        GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/1, // offset
        GIR_AddImm8, /*InsnID*/0, /*Imm*/0,
        GIR_MergeMemOperands, /*InsnID*/0, /*NumInsns*/1, /*MergeInsnID's*/0,
        GIR_ConstrainSelectedInstOperands, /*InsnID*/0,
        GIR_EraseFromParent, /*InsnID*/0,
        // GIR_Coverage, 7072,
        GIR_Done,
      // Label 2408: @158555
      GIM_Try, /*On fail goto*//*Label 2409*/ GIMT_Encode4(158615), // Rule ID 7074 //
        GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasGDS_isGFX6GFX7GFX8GFX9GFX10),
        GIM_CheckMemoryAddressSpace, /*MI*/0, /*MMO*/0, /*NumAddrSpace*/1, /*AddrSpace*/2,
        GIM_CheckHasNoUse, /*MI*/0,
        GIM_CheckPointerToAny, /*MI*/0, /*Op*/1, /*SizeInBits*/0,
        GIM_CheckComplexPattern, /*MI*/0, /*Op*/1, /*Renderer*/GIMT_Encode2(0), GIMT_Encode2(GICP_gi_ds_1addr_1offset),
        // (atomic_cmp_swap_glue:{ *:[i64] } (DS1Addr1Offset:{ *:[iPTR] } i32:{ *:[i32] }:$ptr, i32:{ *:[i32] }:$offset), i64:{ *:[i64] }:$cmp, i64:{ *:[i64] }:$swap)<<P:Predicate_atomic_cmp_swap_region_m0_noret_64>>  =>  (DS_CMPST_B64 ?:{ *:[i32] }:$ptr, anonymous_15036:{ *:[i64] }:$cmp, anonymous_15036:{ *:[i64] }:$swap, offset:{ *:[i32] }:$offset, 1:{ *:[i1] })
        GIR_BuildMI, /*InsnID*/0, /*Opcode*/GIMT_Encode2(AMDGPU::DS_CMPST_B64),
        GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/0, // ptr
        GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/2, // cmp
        GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/3, // swap
        GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/1, // offset
        GIR_AddImm8, /*InsnID*/0, /*Imm*/1,
        GIR_MergeMemOperands, /*InsnID*/0, /*NumInsns*/1, /*MergeInsnID's*/0,
        GIR_ConstrainSelectedInstOperands, /*InsnID*/0,
        GIR_EraseFromParent, /*InsnID*/0,
        // GIR_Coverage, 7074,
        GIR_Done,
      // Label 2409: @158615
      GIM_Try, /*On fail goto*//*Label 2410*/ GIMT_Encode4(158675), // Rule ID 7076 //
        GIM_CheckFeatures, GIMT_Encode2(GIFBS_isGFX11Plus),
        GIM_CheckMemoryAddressSpace, /*MI*/0, /*MMO*/0, /*NumAddrSpace*/1, /*AddrSpace*/3,
        GIM_CheckHasNoUse, /*MI*/0,
        GIM_CheckPointerToAny, /*MI*/0, /*Op*/1, /*SizeInBits*/0,
        GIM_CheckComplexPattern, /*MI*/0, /*Op*/1, /*Renderer*/GIMT_Encode2(0), GIMT_Encode2(GICP_gi_ds_1addr_1offset),
        // (atomic_cmp_swap:{ *:[i64] } (DS1Addr1Offset:{ *:[iPTR] } i32:{ *:[i32] }:$ptr, i32:{ *:[i32] }:$offset), i64:{ *:[i64] }:$cmp, i64:{ *:[i64] }:$swap)<<P:Predicate_atomic_cmp_swap_local_noret_64>>  =>  (DS_CMPSTORE_B64_gfx9 ?:{ *:[i32] }:$ptr, anonymous_15036:{ *:[i64] }:$swap, anonymous_15036:{ *:[i64] }:$cmp, offset:{ *:[i32] }:$offset, 0:{ *:[i1] })
        GIR_BuildMI, /*InsnID*/0, /*Opcode*/GIMT_Encode2(AMDGPU::DS_CMPSTORE_B64_gfx9),
        GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/0, // ptr
        GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/3, // swap
        GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/2, // cmp
        GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/1, // offset
        GIR_AddImm8, /*InsnID*/0, /*Imm*/0,
        GIR_MergeMemOperands, /*InsnID*/0, /*NumInsns*/1, /*MergeInsnID's*/0,
        GIR_ConstrainSelectedInstOperands, /*InsnID*/0,
        GIR_EraseFromParent, /*InsnID*/0,
        // GIR_Coverage, 7076,
        GIR_Done,
      // Label 2410: @158675
      GIM_Try, /*On fail goto*//*Label 2411*/ GIMT_Encode4(158735), // Rule ID 7078 //
        GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasGDS_isGFX11Plus),
        GIM_CheckMemoryAddressSpace, /*MI*/0, /*MMO*/0, /*NumAddrSpace*/1, /*AddrSpace*/2,
        GIM_CheckHasNoUse, /*MI*/0,
        GIM_CheckPointerToAny, /*MI*/0, /*Op*/1, /*SizeInBits*/0,
        GIM_CheckComplexPattern, /*MI*/0, /*Op*/1, /*Renderer*/GIMT_Encode2(0), GIMT_Encode2(GICP_gi_ds_1addr_1offset),
        // (atomic_cmp_swap_glue:{ *:[i64] } (DS1Addr1Offset:{ *:[iPTR] } i32:{ *:[i32] }:$ptr, i32:{ *:[i32] }:$offset), i64:{ *:[i64] }:$cmp, i64:{ *:[i64] }:$swap)<<P:Predicate_atomic_cmp_swap_region_m0_noret_64>>  =>  (DS_CMPSTORE_B64 ?:{ *:[i32] }:$ptr, anonymous_15036:{ *:[i64] }:$swap, anonymous_15036:{ *:[i64] }:$cmp, offset:{ *:[i32] }:$offset, 1:{ *:[i1] })
        GIR_BuildMI, /*InsnID*/0, /*Opcode*/GIMT_Encode2(AMDGPU::DS_CMPSTORE_B64),
        GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/0, // ptr
        GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/3, // swap
        GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/2, // cmp
        GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/1, // offset
        GIR_AddImm8, /*InsnID*/0, /*Imm*/1,
        GIR_MergeMemOperands, /*InsnID*/0, /*NumInsns*/1, /*MergeInsnID's*/0,
        GIR_ConstrainSelectedInstOperands, /*InsnID*/0,
        GIR_EraseFromParent, /*InsnID*/0,
        // GIR_Coverage, 7078,
        GIR_Done,
      // Label 2411: @158735
      GIM_Try, /*On fail goto*//*Label 2412*/ GIMT_Encode4(158802), // Rule ID 7069 //
        GIM_CheckFeatures, GIMT_Encode2(GIFBS_LDSRequiresM0Init_isGFX6GFX7GFX8GFX9GFX10),
        GIM_CheckMemoryAddressSpace, /*MI*/0, /*MMO*/0, /*NumAddrSpace*/1, /*AddrSpace*/3,
        GIM_CheckRegBankForClass, /*MI*/0, /*Op*/0, /*RC*/GIMT_Encode2(AMDGPU::AV_64RegClassID),
        GIM_CheckPointerToAny, /*MI*/0, /*Op*/1, /*SizeInBits*/0,
        GIM_CheckComplexPattern, /*MI*/0, /*Op*/1, /*Renderer*/GIMT_Encode2(0), GIMT_Encode2(GICP_gi_ds_1addr_1offset),
        // (atomic_cmp_swap_glue:{ *:[i64] } (DS1Addr1Offset:{ *:[iPTR] } i32:{ *:[i32] }:$ptr, i32:{ *:[i32] }:$offset), i64:{ *:[i64] }:$cmp, i64:{ *:[i64] }:$swap)<<P:Predicate_atomic_cmp_swap_local_m0_64>>  =>  (DS_CMPST_RTN_B64:{ *:[i64] } ?:{ *:[i32] }:$ptr, anonymous_15036:{ *:[i64] }:$cmp, anonymous_15036:{ *:[i64] }:$swap, offset:{ *:[i32] }:$offset, 0:{ *:[i1] })
        GIR_BuildMI, /*InsnID*/0, /*Opcode*/GIMT_Encode2(AMDGPU::DS_CMPST_RTN_B64),
        GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/0, // DstI[vdst]
        GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/0, // ptr
        GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/2, // cmp
        GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/3, // swap
        GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/1, // offset
        GIR_AddImm8, /*InsnID*/0, /*Imm*/0,
        GIR_MergeMemOperands, /*InsnID*/0, /*NumInsns*/1, /*MergeInsnID's*/0,
        GIR_ConstrainSelectedInstOperands, /*InsnID*/0,
        GIR_EraseFromParent, /*InsnID*/0,
        // GIR_Coverage, 7069,
        GIR_Done,
      // Label 2412: @158802
      GIM_Try, /*On fail goto*//*Label 2413*/ GIMT_Encode4(158869), // Rule ID 7071 //
        GIM_CheckFeatures, GIMT_Encode2(GIFBS_NotLDSRequiresM0Init_isGFX6GFX7GFX8GFX9GFX10),
        GIM_CheckMemoryAddressSpace, /*MI*/0, /*MMO*/0, /*NumAddrSpace*/1, /*AddrSpace*/3,
        GIM_CheckRegBankForClass, /*MI*/0, /*Op*/0, /*RC*/GIMT_Encode2(AMDGPU::AV_64RegClassID),
        GIM_CheckPointerToAny, /*MI*/0, /*Op*/1, /*SizeInBits*/0,
        GIM_CheckComplexPattern, /*MI*/0, /*Op*/1, /*Renderer*/GIMT_Encode2(0), GIMT_Encode2(GICP_gi_ds_1addr_1offset),
        // (atomic_cmp_swap:{ *:[i64] } (DS1Addr1Offset:{ *:[iPTR] } i32:{ *:[i32] }:$ptr, i32:{ *:[i32] }:$offset), i64:{ *:[i64] }:$cmp, i64:{ *:[i64] }:$swap)<<P:Predicate_atomic_cmp_swap_local_64>>  =>  (DS_CMPST_RTN_B64_gfx9:{ *:[i64] } ?:{ *:[i32] }:$ptr, anonymous_15036:{ *:[i64] }:$cmp, anonymous_15036:{ *:[i64] }:$swap, offset:{ *:[i32] }:$offset, 0:{ *:[i1] })
        GIR_BuildMI, /*InsnID*/0, /*Opcode*/GIMT_Encode2(AMDGPU::DS_CMPST_RTN_B64_gfx9),
        GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/0, // DstI[vdst]
        GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/0, // ptr
        GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/2, // cmp
        GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/3, // swap
        GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/1, // offset
        GIR_AddImm8, /*InsnID*/0, /*Imm*/0,
        GIR_MergeMemOperands, /*InsnID*/0, /*NumInsns*/1, /*MergeInsnID's*/0,
        GIR_ConstrainSelectedInstOperands, /*InsnID*/0,
        GIR_EraseFromParent, /*InsnID*/0,
        // GIR_Coverage, 7071,
        GIR_Done,
      // Label 2413: @158869
      GIM_Try, /*On fail goto*//*Label 2414*/ GIMT_Encode4(158936), // Rule ID 7073 //
        GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasGDS_isGFX6GFX7GFX8GFX9GFX10),
        GIM_CheckMemoryAddressSpace, /*MI*/0, /*MMO*/0, /*NumAddrSpace*/1, /*AddrSpace*/2,
        GIM_CheckRegBankForClass, /*MI*/0, /*Op*/0, /*RC*/GIMT_Encode2(AMDGPU::AV_64RegClassID),
        GIM_CheckPointerToAny, /*MI*/0, /*Op*/1, /*SizeInBits*/0,
        GIM_CheckComplexPattern, /*MI*/0, /*Op*/1, /*Renderer*/GIMT_Encode2(0), GIMT_Encode2(GICP_gi_ds_1addr_1offset),
        // (atomic_cmp_swap_glue:{ *:[i64] } (DS1Addr1Offset:{ *:[iPTR] } i32:{ *:[i32] }:$ptr, i32:{ *:[i32] }:$offset), i64:{ *:[i64] }:$cmp, i64:{ *:[i64] }:$swap)<<P:Predicate_atomic_cmp_swap_region_m0_64>>  =>  (DS_CMPST_RTN_B64:{ *:[i64] } ?:{ *:[i32] }:$ptr, anonymous_15036:{ *:[i64] }:$cmp, anonymous_15036:{ *:[i64] }:$swap, offset:{ *:[i32] }:$offset, 1:{ *:[i1] })
        GIR_BuildMI, /*InsnID*/0, /*Opcode*/GIMT_Encode2(AMDGPU::DS_CMPST_RTN_B64),
        GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/0, // DstI[vdst]
        GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/0, // ptr
        GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/2, // cmp
        GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/3, // swap
        GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/1, // offset
        GIR_AddImm8, /*InsnID*/0, /*Imm*/1,
        GIR_MergeMemOperands, /*InsnID*/0, /*NumInsns*/1, /*MergeInsnID's*/0,
        GIR_ConstrainSelectedInstOperands, /*InsnID*/0,
        GIR_EraseFromParent, /*InsnID*/0,
        // GIR_Coverage, 7073,
        GIR_Done,
      // Label 2414: @158936
      GIM_Try, /*On fail goto*//*Label 2415*/ GIMT_Encode4(159003), // Rule ID 7075 //
        GIM_CheckFeatures, GIMT_Encode2(GIFBS_isGFX11Plus),
        GIM_CheckMemoryAddressSpace, /*MI*/0, /*MMO*/0, /*NumAddrSpace*/1, /*AddrSpace*/3,
        GIM_CheckRegBankForClass, /*MI*/0, /*Op*/0, /*RC*/GIMT_Encode2(AMDGPU::AV_64RegClassID),
        GIM_CheckPointerToAny, /*MI*/0, /*Op*/1, /*SizeInBits*/0,
        GIM_CheckComplexPattern, /*MI*/0, /*Op*/1, /*Renderer*/GIMT_Encode2(0), GIMT_Encode2(GICP_gi_ds_1addr_1offset),
        // (atomic_cmp_swap:{ *:[i64] } (DS1Addr1Offset:{ *:[iPTR] } i32:{ *:[i32] }:$ptr, i32:{ *:[i32] }:$offset), i64:{ *:[i64] }:$cmp, i64:{ *:[i64] }:$swap)<<P:Predicate_atomic_cmp_swap_local_64>>  =>  (DS_CMPSTORE_RTN_B64_gfx9:{ *:[i64] } ?:{ *:[i32] }:$ptr, anonymous_15036:{ *:[i64] }:$swap, anonymous_15036:{ *:[i64] }:$cmp, offset:{ *:[i32] }:$offset, 0:{ *:[i1] })
        GIR_BuildMI, /*InsnID*/0, /*Opcode*/GIMT_Encode2(AMDGPU::DS_CMPSTORE_RTN_B64_gfx9),
        GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/0, // DstI[vdst]
        GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/0, // ptr
        GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/3, // swap
        GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/2, // cmp
        GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/1, // offset
        GIR_AddImm8, /*InsnID*/0, /*Imm*/0,
        GIR_MergeMemOperands, /*InsnID*/0, /*NumInsns*/1, /*MergeInsnID's*/0,
        GIR_ConstrainSelectedInstOperands, /*InsnID*/0,
        GIR_EraseFromParent, /*InsnID*/0,
        // GIR_Coverage, 7075,
        GIR_Done,
      // Label 2415: @159003
      GIM_Try, /*On fail goto*//*Label 2416*/ GIMT_Encode4(159070), // Rule ID 7077 //
        GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasGDS_isGFX11Plus),
        GIM_CheckMemoryAddressSpace, /*MI*/0, /*MMO*/0, /*NumAddrSpace*/1, /*AddrSpace*/2,
        GIM_CheckRegBankForClass, /*MI*/0, /*Op*/0, /*RC*/GIMT_Encode2(AMDGPU::AV_64RegClassID),
        GIM_CheckPointerToAny, /*MI*/0, /*Op*/1, /*SizeInBits*/0,
        GIM_CheckComplexPattern, /*MI*/0, /*Op*/1, /*Renderer*/GIMT_Encode2(0), GIMT_Encode2(GICP_gi_ds_1addr_1offset),
        // (atomic_cmp_swap_glue:{ *:[i64] } (DS1Addr1Offset:{ *:[iPTR] } i32:{ *:[i32] }:$ptr, i32:{ *:[i32] }:$offset), i64:{ *:[i64] }:$cmp, i64:{ *:[i64] }:$swap)<<P:Predicate_atomic_cmp_swap_region_m0_64>>  =>  (DS_CMPSTORE_RTN_B64:{ *:[i64] } ?:{ *:[i32] }:$ptr, anonymous_15036:{ *:[i64] }:$swap, anonymous_15036:{ *:[i64] }:$cmp, offset:{ *:[i32] }:$offset, 1:{ *:[i1] })
        GIR_BuildMI, /*InsnID*/0, /*Opcode*/GIMT_Encode2(AMDGPU::DS_CMPSTORE_RTN_B64),
        GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/0, // DstI[vdst]
        GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/0, // ptr
        GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/3, // swap
        GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/2, // cmp
        GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/1, // offset
        GIR_AddImm8, /*InsnID*/0, /*Imm*/1,
        GIR_MergeMemOperands, /*InsnID*/0, /*NumInsns*/1, /*MergeInsnID's*/0,
        GIR_ConstrainSelectedInstOperands, /*InsnID*/0,
        GIR_EraseFromParent, /*InsnID*/0,
        // GIR_Coverage, 7077,
        GIR_Done,
      // Label 2416: @159070
      GIM_Reject,
    // Label 2406: @159071
    GIM_Reject,
    // Label 2394: @159072
    GIM_Reject,
    // Label 17: @159073
    GIM_SwitchType, /*MI*/0, /*Op*/0, /*[*/GIMT_Encode2(9), GIMT_Encode2(11), /*)*//*default:*//*Label 2419*/ GIMT_Encode4(161580),
    /*GILLT_s32*//*Label 2417*/ GIMT_Encode4(159092),
    /*GILLT_s64*//*Label 2418*/ GIMT_Encode4(160336),
    // Label 2417: @159092
    GIM_Try, /*On fail goto*//*Label 2420*/ GIMT_Encode4(160335),
      GIM_CheckType, /*MI*/0, /*Op*/2, /*Type*/GILLT_s32,
      GIM_Try, /*On fail goto*//*Label 2421*/ GIMT_Encode4(159169), // Rule ID 4510 //
        GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasUnrestrictedSOffset),
        GIM_CheckMemoryAddressSpace, /*MI*/0, /*MMO*/0, /*NumAddrSpace*/3, /*AddrSpace*/1, /*AddrSpace*/4, /*AddrSpace*/6,
        GIM_CheckHasNoUse, /*MI*/0,
        GIM_CheckPointerToAny, /*MI*/0, /*Op*/1, /*SizeInBits*/0,
        GIM_CheckComplexPattern, /*MI*/0, /*Op*/1, /*Renderer*/GIMT_Encode2(0), GIMT_Encode2(GICP_gi_mubuf_addr64),
        // (atomic_swap:{ *:[i32] } (MUBUFAddr64:{ *:[iPTR] } v4i32:{ *:[v4i32] }:$srsrc, i64:{ *:[i64] }:$vaddr, i32:{ *:[i32] }:$soffset, i32:{ *:[i32] }:$offset), i32:{ *:[i32] }:$vdata_in)<<P:Predicate_atomic_swap_global_noret_32>>  =>  (BUFFER_ATOMIC_SWAP_ADDR64 anonymous_15037:{ *:[i32] }:$vdata_in, VReg_64:{ *:[i64] }:$vaddr, SReg_128:{ *:[v4i32] }:$srsrc, SCSrc_b32:{ *:[i32] }:$soffset, offset:{ *:[i32] }:$offset)
        GIR_BuildMI, /*InsnID*/0, /*Opcode*/GIMT_Encode2(AMDGPU::BUFFER_ATOMIC_SWAP_ADDR64),
        GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/2, // vdata_in
        GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/1, // vaddr
        GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/0, // srsrc
        GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/2, // soffset
        GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/3, // offset
        GIR_AddImm8, /*InsnID*/0, /*Imm*/0,
        GIR_MergeMemOperands, /*InsnID*/0, /*NumInsns*/1, /*MergeInsnID's*/0,
        GIR_ConstrainSelectedInstOperands, /*InsnID*/0,
        GIR_EraseFromParent, /*InsnID*/0,
        // GIR_Coverage, 4510,
        GIR_Done,
      // Label 2421: @159169
      GIM_Try, /*On fail goto*//*Label 2422*/ GIMT_Encode4(159234), // Rule ID 4514 //
        GIM_CheckMemoryAddressSpace, /*MI*/0, /*MMO*/0, /*NumAddrSpace*/3, /*AddrSpace*/1, /*AddrSpace*/4, /*AddrSpace*/6,
        GIM_CheckHasNoUse, /*MI*/0,
        GIM_CheckPointerToAny, /*MI*/0, /*Op*/1, /*SizeInBits*/0,
        GIM_CheckComplexPattern, /*MI*/0, /*Op*/1, /*Renderer*/GIMT_Encode2(0), GIMT_Encode2(GICP_gi_mubuf_addr64),
        // (atomic_swap:{ *:[i32] } (MUBUFAddr64:{ *:[iPTR] } v4i32:{ *:[v4i32] }:$srsrc, i64:{ *:[i64] }:$vaddr, i32:{ *:[i32] }:$soffset, i32:{ *:[i32] }:$offset), i32:{ *:[i32] }:$vdata_in)<<P:Predicate_atomic_swap_global_noret_32>>  =>  (BUFFER_ATOMIC_SWAP_VBUFFER_ADDR64 anonymous_15037:{ *:[i32] }:$vdata_in, VReg_64:{ *:[i64] }:$vaddr, SReg_128:{ *:[v4i32] }:$srsrc, SCSrc_b32:{ *:[i32] }:$soffset, offset:{ *:[i32] }:$offset)
        GIR_BuildMI, /*InsnID*/0, /*Opcode*/GIMT_Encode2(AMDGPU::BUFFER_ATOMIC_SWAP_VBUFFER_ADDR64),
        GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/2, // vdata_in
        GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/1, // vaddr
        GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/0, // srsrc
        GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/2, // soffset
        GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/3, // offset
        GIR_AddImm8, /*InsnID*/0, /*Imm*/0,
        GIR_MergeMemOperands, /*InsnID*/0, /*NumInsns*/1, /*MergeInsnID's*/0,
        GIR_ConstrainSelectedInstOperands, /*InsnID*/0,
        GIR_EraseFromParent, /*InsnID*/0,
        // GIR_Coverage, 4514,
        GIR_Done,
      // Label 2422: @159234
      GIM_Try, /*On fail goto*//*Label 2423*/ GIMT_Encode4(159309), // Rule ID 4506 //
        GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasUnrestrictedSOffset),
        GIM_CheckMemoryAddressSpace, /*MI*/0, /*MMO*/0, /*NumAddrSpace*/3, /*AddrSpace*/1, /*AddrSpace*/4, /*AddrSpace*/6,
        GIM_CheckRegBankForClass, /*MI*/0, /*Op*/0, /*RC*/GIMT_Encode2(AMDGPU::AV_32RegClassID),
        GIM_CheckPointerToAny, /*MI*/0, /*Op*/1, /*SizeInBits*/0,
        GIM_CheckComplexPattern, /*MI*/0, /*Op*/1, /*Renderer*/GIMT_Encode2(0), GIMT_Encode2(GICP_gi_mubuf_addr64),
        // (atomic_swap:{ *:[i32] } (MUBUFAddr64:{ *:[iPTR] } v4i32:{ *:[v4i32] }:$srsrc, i64:{ *:[i64] }:$vaddr, i32:{ *:[i32] }:$soffset, i32:{ *:[i32] }:$offset), i32:{ *:[i32] }:$vdata_in)<<P:Predicate_atomic_swap_global_32>>  =>  (BUFFER_ATOMIC_SWAP_ADDR64_RTN:{ *:[i32] } anonymous_15037:{ *:[i32] }:$vdata_in, VReg_64:{ *:[i64] }:$vaddr, SReg_128:{ *:[v4i32] }:$srsrc, SCSrc_b32:{ *:[i32] }:$soffset, offset:{ *:[i32] }:$offset)
        GIR_BuildMI, /*InsnID*/0, /*Opcode*/GIMT_Encode2(AMDGPU::BUFFER_ATOMIC_SWAP_ADDR64_RTN),
        GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/0, // DstI[vdata]
        GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/2, // vdata_in
        GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/1, // vaddr
        GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/0, // srsrc
        GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/2, // soffset
        GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/3, // offset
        GIR_AddImm8, /*InsnID*/0, /*Imm*/1,
        GIR_MergeMemOperands, /*InsnID*/0, /*NumInsns*/1, /*MergeInsnID's*/0,
        GIR_ConstrainSelectedInstOperands, /*InsnID*/0,
        GIR_EraseFromParent, /*InsnID*/0,
        // GIR_Coverage, 4506,
        GIR_Done,
      // Label 2423: @159309
      GIM_Try, /*On fail goto*//*Label 2424*/ GIMT_Encode4(159381), // Rule ID 4512 //
        GIM_CheckMemoryAddressSpace, /*MI*/0, /*MMO*/0, /*NumAddrSpace*/3, /*AddrSpace*/1, /*AddrSpace*/4, /*AddrSpace*/6,
        GIM_CheckRegBankForClass, /*MI*/0, /*Op*/0, /*RC*/GIMT_Encode2(AMDGPU::AV_32RegClassID),
        GIM_CheckPointerToAny, /*MI*/0, /*Op*/1, /*SizeInBits*/0,
        GIM_CheckComplexPattern, /*MI*/0, /*Op*/1, /*Renderer*/GIMT_Encode2(0), GIMT_Encode2(GICP_gi_mubuf_addr64),
        // (atomic_swap:{ *:[i32] } (MUBUFAddr64:{ *:[iPTR] } v4i32:{ *:[v4i32] }:$srsrc, i64:{ *:[i64] }:$vaddr, i32:{ *:[i32] }:$soffset, i32:{ *:[i32] }:$offset), i32:{ *:[i32] }:$vdata_in)<<P:Predicate_atomic_swap_global_32>>  =>  (BUFFER_ATOMIC_SWAP_VBUFFER_ADDR64_RTN:{ *:[i32] } anonymous_15037:{ *:[i32] }:$vdata_in, VReg_64:{ *:[i64] }:$vaddr, SReg_128:{ *:[v4i32] }:$srsrc, SCSrc_b32:{ *:[i32] }:$soffset, offset:{ *:[i32] }:$offset)
        GIR_BuildMI, /*InsnID*/0, /*Opcode*/GIMT_Encode2(AMDGPU::BUFFER_ATOMIC_SWAP_VBUFFER_ADDR64_RTN),
        GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/0, // DstI[vdata]
        GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/2, // vdata_in
        GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/1, // vaddr
        GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/0, // srsrc
        GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/2, // soffset
        GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/3, // offset
        GIR_AddImm8, /*InsnID*/0, /*Imm*/1,
        GIR_MergeMemOperands, /*InsnID*/0, /*NumInsns*/1, /*MergeInsnID's*/0,
        GIR_ConstrainSelectedInstOperands, /*InsnID*/0,
        GIR_EraseFromParent, /*InsnID*/0,
        // GIR_Coverage, 4512,
        GIR_Done,
      // Label 2424: @159381
      GIM_Try, /*On fail goto*//*Label 2425*/ GIMT_Encode4(159444), // Rule ID 4509 //
        GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasUnrestrictedSOffset),
        GIM_CheckMemoryAddressSpace, /*MI*/0, /*MMO*/0, /*NumAddrSpace*/3, /*AddrSpace*/1, /*AddrSpace*/4, /*AddrSpace*/6,
        GIM_CheckHasNoUse, /*MI*/0,
        GIM_CheckPointerToAny, /*MI*/0, /*Op*/1, /*SizeInBits*/0,
        GIM_CheckComplexPattern, /*MI*/0, /*Op*/1, /*Renderer*/GIMT_Encode2(0), GIMT_Encode2(GICP_gi_mubuf_offset),
        // (atomic_swap:{ *:[i32] } (MUBUFOffset:{ *:[iPTR] } v4i32:{ *:[v4i32] }:$srsrc, i32:{ *:[i32] }:$soffset, i32:{ *:[i32] }:$offset), i32:{ *:[i32] }:$vdata_in)<<P:Predicate_atomic_swap_global_noret_32>>  =>  (BUFFER_ATOMIC_SWAP_OFFSET anonymous_15037:{ *:[i32] }:$vdata_in, SReg_128:{ *:[v4i32] }:$srsrc, SCSrc_b32:{ *:[i32] }:$soffset, offset:{ *:[i32] }:$offset)
        GIR_BuildMI, /*InsnID*/0, /*Opcode*/GIMT_Encode2(AMDGPU::BUFFER_ATOMIC_SWAP_OFFSET),
        GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/2, // vdata_in
        GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/0, // srsrc
        GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/1, // soffset
        GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/2, // offset
        GIR_AddImm8, /*InsnID*/0, /*Imm*/0,
        GIR_MergeMemOperands, /*InsnID*/0, /*NumInsns*/1, /*MergeInsnID's*/0,
        GIR_ConstrainSelectedInstOperands, /*InsnID*/0,
        GIR_EraseFromParent, /*InsnID*/0,
        // GIR_Coverage, 4509,
        GIR_Done,
      // Label 2425: @159444
      GIM_Try, /*On fail goto*//*Label 2426*/ GIMT_Encode4(159504), // Rule ID 4513 //
        GIM_CheckMemoryAddressSpace, /*MI*/0, /*MMO*/0, /*NumAddrSpace*/3, /*AddrSpace*/1, /*AddrSpace*/4, /*AddrSpace*/6,
        GIM_CheckHasNoUse, /*MI*/0,
        GIM_CheckPointerToAny, /*MI*/0, /*Op*/1, /*SizeInBits*/0,
        GIM_CheckComplexPattern, /*MI*/0, /*Op*/1, /*Renderer*/GIMT_Encode2(0), GIMT_Encode2(GICP_gi_mubuf_offset),
        // (atomic_swap:{ *:[i32] } (MUBUFOffset:{ *:[iPTR] } v4i32:{ *:[v4i32] }:$srsrc, i32:{ *:[i32] }:$soffset, i32:{ *:[i32] }:$offset), i32:{ *:[i32] }:$vdata_in)<<P:Predicate_atomic_swap_global_noret_32>>  =>  (BUFFER_ATOMIC_SWAP_VBUFFER_OFFSET anonymous_15037:{ *:[i32] }:$vdata_in, SReg_128:{ *:[v4i32] }:$srsrc, SCSrc_b32:{ *:[i32] }:$soffset, offset:{ *:[i32] }:$offset)
        GIR_BuildMI, /*InsnID*/0, /*Opcode*/GIMT_Encode2(AMDGPU::BUFFER_ATOMIC_SWAP_VBUFFER_OFFSET),
        GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/2, // vdata_in
        GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/0, // srsrc
        GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/1, // soffset
        GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/2, // offset
        GIR_AddImm8, /*InsnID*/0, /*Imm*/0,
        GIR_MergeMemOperands, /*InsnID*/0, /*NumInsns*/1, /*MergeInsnID's*/0,
        GIR_ConstrainSelectedInstOperands, /*InsnID*/0,
        GIR_EraseFromParent, /*InsnID*/0,
        // GIR_Coverage, 4513,
        GIR_Done,
      // Label 2426: @159504
      GIM_Try, /*On fail goto*//*Label 2427*/ GIMT_Encode4(159574), // Rule ID 4505 //
        GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasUnrestrictedSOffset),
        GIM_CheckMemoryAddressSpace, /*MI*/0, /*MMO*/0, /*NumAddrSpace*/3, /*AddrSpace*/1, /*AddrSpace*/4, /*AddrSpace*/6,
        GIM_CheckRegBankForClass, /*MI*/0, /*Op*/0, /*RC*/GIMT_Encode2(AMDGPU::AV_32RegClassID),
        GIM_CheckPointerToAny, /*MI*/0, /*Op*/1, /*SizeInBits*/0,
        GIM_CheckComplexPattern, /*MI*/0, /*Op*/1, /*Renderer*/GIMT_Encode2(0), GIMT_Encode2(GICP_gi_mubuf_offset),
        // (atomic_swap:{ *:[i32] } (MUBUFOffset:{ *:[iPTR] } v4i32:{ *:[v4i32] }:$srsrc, i32:{ *:[i32] }:$soffset, i32:{ *:[i32] }:$offset), i32:{ *:[i32] }:$vdata_in)<<P:Predicate_atomic_swap_global_32>>  =>  (BUFFER_ATOMIC_SWAP_OFFSET_RTN:{ *:[i32] } anonymous_15037:{ *:[i32] }:$vdata_in, SReg_128:{ *:[v4i32] }:$srsrc, SCSrc_b32:{ *:[i32] }:$soffset, offset:{ *:[i32] }:$offset)
        GIR_BuildMI, /*InsnID*/0, /*Opcode*/GIMT_Encode2(AMDGPU::BUFFER_ATOMIC_SWAP_OFFSET_RTN),
        GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/0, // DstI[vdata]
        GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/2, // vdata_in
        GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/0, // srsrc
        GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/1, // soffset
        GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/2, // offset
        GIR_AddImm8, /*InsnID*/0, /*Imm*/1,
        GIR_MergeMemOperands, /*InsnID*/0, /*NumInsns*/1, /*MergeInsnID's*/0,
        GIR_ConstrainSelectedInstOperands, /*InsnID*/0,
        GIR_EraseFromParent, /*InsnID*/0,
        // GIR_Coverage, 4505,
        GIR_Done,
      // Label 2427: @159574
      GIM_Try, /*On fail goto*//*Label 2428*/ GIMT_Encode4(159641), // Rule ID 4511 //
        GIM_CheckMemoryAddressSpace, /*MI*/0, /*MMO*/0, /*NumAddrSpace*/3, /*AddrSpace*/1, /*AddrSpace*/4, /*AddrSpace*/6,
        GIM_CheckRegBankForClass, /*MI*/0, /*Op*/0, /*RC*/GIMT_Encode2(AMDGPU::AV_32RegClassID),
        GIM_CheckPointerToAny, /*MI*/0, /*Op*/1, /*SizeInBits*/0,
        GIM_CheckComplexPattern, /*MI*/0, /*Op*/1, /*Renderer*/GIMT_Encode2(0), GIMT_Encode2(GICP_gi_mubuf_offset),
        // (atomic_swap:{ *:[i32] } (MUBUFOffset:{ *:[iPTR] } v4i32:{ *:[v4i32] }:$srsrc, i32:{ *:[i32] }:$soffset, i32:{ *:[i32] }:$offset), i32:{ *:[i32] }:$vdata_in)<<P:Predicate_atomic_swap_global_32>>  =>  (BUFFER_ATOMIC_SWAP_VBUFFER_OFFSET_RTN:{ *:[i32] } anonymous_15037:{ *:[i32] }:$vdata_in, SReg_128:{ *:[v4i32] }:$srsrc, SCSrc_b32:{ *:[i32] }:$soffset, offset:{ *:[i32] }:$offset)
        GIR_BuildMI, /*InsnID*/0, /*Opcode*/GIMT_Encode2(AMDGPU::BUFFER_ATOMIC_SWAP_VBUFFER_OFFSET_RTN),
        GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/0, // DstI[vdata]
        GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/2, // vdata_in
        GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/0, // srsrc
        GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/1, // soffset
        GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/2, // offset
        GIR_AddImm8, /*InsnID*/0, /*Imm*/1,
        GIR_MergeMemOperands, /*InsnID*/0, /*NumInsns*/1, /*MergeInsnID's*/0,
        GIR_ConstrainSelectedInstOperands, /*InsnID*/0,
        GIR_EraseFromParent, /*InsnID*/0,
        // GIR_Coverage, 4511,
        GIR_Done,
      // Label 2428: @159641
      GIM_Try, /*On fail goto*//*Label 2429*/ GIMT_Encode4(159704), // Rule ID 6891 //
        GIM_CheckFeatures, GIMT_Encode2(GIFBS_LDSRequiresM0Init),
        GIM_CheckMemoryAddressSpace, /*MI*/0, /*MMO*/0, /*NumAddrSpace*/1, /*AddrSpace*/3,
        GIM_CheckRegBankForClass, /*MI*/0, /*Op*/0, /*RC*/GIMT_Encode2(AMDGPU::AV_32RegClassID),
        GIM_CheckPointerToAny, /*MI*/0, /*Op*/1, /*SizeInBits*/0,
        GIM_CheckComplexPattern, /*MI*/0, /*Op*/1, /*Renderer*/GIMT_Encode2(0), GIMT_Encode2(GICP_gi_ds_1addr_1offset),
        // (atomic_swap_glue:{ *:[i32] } (DS1Addr1Offset:{ *:[iPTR] } i32:{ *:[i32] }:$ptr, i32:{ *:[i32] }:$offset), i32:{ *:[i32] }:$value)<<P:Predicate_atomic_swap_local_m0_32>>  =>  (DS_WRXCHG_RTN_B32:{ *:[i32] } ?:{ *:[i32] }:$ptr, anonymous_15037:{ *:[i32] }:$value, offset:{ *:[i32] }:$offset, 0:{ *:[i1] })
        GIR_BuildMI, /*InsnID*/0, /*Opcode*/GIMT_Encode2(AMDGPU::DS_WRXCHG_RTN_B32),
        GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/0, // DstI[vdst]
        GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/0, // ptr
        GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/2, // value
        GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/1, // offset
        GIR_AddImm8, /*InsnID*/0, /*Imm*/0,
        GIR_MergeMemOperands, /*InsnID*/0, /*NumInsns*/1, /*MergeInsnID's*/0,
        GIR_ConstrainSelectedInstOperands, /*InsnID*/0,
        GIR_EraseFromParent, /*InsnID*/0,
        // GIR_Coverage, 6891,
        GIR_Done,
      // Label 2429: @159704
      GIM_Try, /*On fail goto*//*Label 2430*/ GIMT_Encode4(159767), // Rule ID 6892 //
        GIM_CheckFeatures, GIMT_Encode2(GIFBS_NotLDSRequiresM0Init),
        GIM_CheckMemoryAddressSpace, /*MI*/0, /*MMO*/0, /*NumAddrSpace*/1, /*AddrSpace*/3,
        GIM_CheckRegBankForClass, /*MI*/0, /*Op*/0, /*RC*/GIMT_Encode2(AMDGPU::AV_32RegClassID),
        GIM_CheckPointerToAny, /*MI*/0, /*Op*/1, /*SizeInBits*/0,
        GIM_CheckComplexPattern, /*MI*/0, /*Op*/1, /*Renderer*/GIMT_Encode2(0), GIMT_Encode2(GICP_gi_ds_1addr_1offset),
        // (atomic_swap:{ *:[i32] } (DS1Addr1Offset:{ *:[iPTR] } i32:{ *:[i32] }:$ptr, i32:{ *:[i32] }:$offset), i32:{ *:[i32] }:$value)<<P:Predicate_atomic_swap_local_32>>  =>  (DS_WRXCHG_RTN_B32_gfx9:{ *:[i32] } ?:{ *:[i32] }:$ptr, anonymous_15037:{ *:[i32] }:$value, offset:{ *:[i32] }:$offset, 0:{ *:[i1] })
        GIR_BuildMI, /*InsnID*/0, /*Opcode*/GIMT_Encode2(AMDGPU::DS_WRXCHG_RTN_B32_gfx9),
        GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/0, // DstI[vdst]
        GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/0, // ptr
        GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/2, // value
        GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/1, // offset
        GIR_AddImm8, /*InsnID*/0, /*Imm*/0,
        GIR_MergeMemOperands, /*InsnID*/0, /*NumInsns*/1, /*MergeInsnID's*/0,
        GIR_ConstrainSelectedInstOperands, /*InsnID*/0,
        GIR_EraseFromParent, /*InsnID*/0,
        // GIR_Coverage, 6892,
        GIR_Done,
      // Label 2430: @159767
      GIM_Try, /*On fail goto*//*Label 2431*/ GIMT_Encode4(159830), // Rule ID 6893 //
        GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasGDS),
        GIM_CheckMemoryAddressSpace, /*MI*/0, /*MMO*/0, /*NumAddrSpace*/1, /*AddrSpace*/2,
        GIM_CheckRegBankForClass, /*MI*/0, /*Op*/0, /*RC*/GIMT_Encode2(AMDGPU::AV_32RegClassID),
        GIM_CheckPointerToAny, /*MI*/0, /*Op*/1, /*SizeInBits*/0,
        GIM_CheckComplexPattern, /*MI*/0, /*Op*/1, /*Renderer*/GIMT_Encode2(0), GIMT_Encode2(GICP_gi_ds_1addr_1offset),
        // (atomic_swap_glue:{ *:[i32] } (DS1Addr1Offset:{ *:[iPTR] } i32:{ *:[i32] }:$ptr, i32:{ *:[i32] }:$offset), i32:{ *:[i32] }:$value)<<P:Predicate_atomic_swap_region_m0_32>>  =>  (DS_WRXCHG_RTN_B32:{ *:[i32] } ?:{ *:[i32] }:$ptr, anonymous_15037:{ *:[i32] }:$value, offset:{ *:[i32] }:$offset, 1:{ *:[i1] })
        GIR_BuildMI, /*InsnID*/0, /*Opcode*/GIMT_Encode2(AMDGPU::DS_WRXCHG_RTN_B32),
        GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/0, // DstI[vdst]
        GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/0, // ptr
        GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/2, // value
        GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/1, // offset
        GIR_AddImm8, /*InsnID*/0, /*Imm*/1,
        GIR_MergeMemOperands, /*InsnID*/0, /*NumInsns*/1, /*MergeInsnID's*/0,
        GIR_ConstrainSelectedInstOperands, /*InsnID*/0,
        GIR_EraseFromParent, /*InsnID*/0,
        // GIR_Coverage, 6893,
        GIR_Done,
      // Label 2431: @159830
      GIM_Try, /*On fail goto*//*Label 2432*/ GIMT_Encode4(159893), // Rule ID 3187 //
        GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasFlatGlobalInsts),
        GIM_CheckMemoryAddressSpace, /*MI*/0, /*MMO*/0, /*NumAddrSpace*/3, /*AddrSpace*/1, /*AddrSpace*/4, /*AddrSpace*/6,
        GIM_CheckHasNoUse, /*MI*/0,
        GIM_CheckPointerToAny, /*MI*/0, /*Op*/1, /*SizeInBits*/0,
        GIM_CheckComplexPattern, /*MI*/0, /*Op*/1, /*Renderer*/GIMT_Encode2(0), GIMT_Encode2(GICP_gi_global_saddr),
        // (atomic_swap:{ *:[i32] } (GlobalSAddr:{ *:[iPTR] } SReg_64:{ *:[i64] }:$saddr, VGPR_32:{ *:[i32] }:$voffset, i32:{ *:[i32] }:$offset), i32:{ *:[i32] }:$data)<<P:Predicate_atomic_swap_global_noret_32>>  =>  (GLOBAL_ATOMIC_SWAP_SADDR ?:{ *:[i32] }:$voffset, anonymous_15037:{ *:[i32] }:$data, ?:{ *:[i64] }:$saddr, ?:{ *:[i32] }:$offset)
        GIR_BuildMI, /*InsnID*/0, /*Opcode*/GIMT_Encode2(AMDGPU::GLOBAL_ATOMIC_SWAP_SADDR),
        GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/1, // voffset
        GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/2, // data
        GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/0, // saddr
        GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/2, // offset
        GIR_AddImm8, /*InsnID*/0, /*Imm*/0,
        GIR_MergeMemOperands, /*InsnID*/0, /*NumInsns*/1, /*MergeInsnID's*/0,
        GIR_ConstrainSelectedInstOperands, /*InsnID*/0,
        GIR_EraseFromParent, /*InsnID*/0,
        // GIR_Coverage, 3187,
        GIR_Done,
      // Label 2432: @159893
      GIM_Try, /*On fail goto*//*Label 2433*/ GIMT_Encode4(159963), // Rule ID 3189 //
        GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasFlatGlobalInsts),
        GIM_CheckMemoryAddressSpace, /*MI*/0, /*MMO*/0, /*NumAddrSpace*/3, /*AddrSpace*/1, /*AddrSpace*/4, /*AddrSpace*/6,
        GIM_CheckRegBankForClass, /*MI*/0, /*Op*/0, /*RC*/GIMT_Encode2(AMDGPU::AV_32RegClassID),
        GIM_CheckPointerToAny, /*MI*/0, /*Op*/1, /*SizeInBits*/0,
        GIM_CheckComplexPattern, /*MI*/0, /*Op*/1, /*Renderer*/GIMT_Encode2(0), GIMT_Encode2(GICP_gi_global_saddr),
        // (atomic_swap:{ *:[i32] } (GlobalSAddr:{ *:[iPTR] } SReg_64:{ *:[i64] }:$saddr, VGPR_32:{ *:[i32] }:$voffset, i32:{ *:[i32] }:$offset), i32:{ *:[i32] }:$data)<<P:Predicate_atomic_swap_global_32>>  =>  (GLOBAL_ATOMIC_SWAP_SADDR_RTN:{ *:[i32] } ?:{ *:[i32] }:$voffset, anonymous_15037:{ *:[i32] }:$data, ?:{ *:[i64] }:$saddr, ?:{ *:[i32] }:$offset)
        GIR_BuildMI, /*InsnID*/0, /*Opcode*/GIMT_Encode2(AMDGPU::GLOBAL_ATOMIC_SWAP_SADDR_RTN),
        GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/0, // DstI[vdst]
        GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/1, // voffset
        GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/2, // data
        GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/0, // saddr
        GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/2, // offset
        GIR_AddImm8, /*InsnID*/0, /*Imm*/1,
        GIR_MergeMemOperands, /*InsnID*/0, /*NumInsns*/1, /*MergeInsnID's*/0,
        GIR_ConstrainSelectedInstOperands, /*InsnID*/0,
        GIR_EraseFromParent, /*InsnID*/0,
        // GIR_Coverage, 3189,
        GIR_Done,
      // Label 2433: @159963
      GIM_Try, /*On fail goto*//*Label 2434*/ GIMT_Encode4(160021), // Rule ID 3186 //
        GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasFlatGlobalInsts),
        GIM_CheckMemoryAddressSpace, /*MI*/0, /*MMO*/0, /*NumAddrSpace*/3, /*AddrSpace*/1, /*AddrSpace*/4, /*AddrSpace*/6,
        GIM_CheckHasNoUse, /*MI*/0,
        GIM_CheckPointerToAny, /*MI*/0, /*Op*/1, /*SizeInBits*/0,
        GIM_CheckComplexPattern, /*MI*/0, /*Op*/1, /*Renderer*/GIMT_Encode2(0), GIMT_Encode2(GICP_gi_global_offset),
        // (atomic_swap:{ *:[i32] } (GlobalOffset:{ *:[iPTR] } i64:{ *:[i64] }:$vaddr, i32:{ *:[i32] }:$offset), i32:{ *:[i32] }:$data)<<P:Predicate_atomic_swap_global_noret_32>>  =>  (GLOBAL_ATOMIC_SWAP VReg_64:{ *:[i64] }:$vaddr, anonymous_15037:{ *:[i32] }:$data, ?:{ *:[i32] }:$offset)
        GIR_BuildMI, /*InsnID*/0, /*Opcode*/GIMT_Encode2(AMDGPU::GLOBAL_ATOMIC_SWAP),
        GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/0, // vaddr
        GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/2, // data
        GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/1, // offset
        GIR_AddImm8, /*InsnID*/0, /*Imm*/0,
        GIR_MergeMemOperands, /*InsnID*/0, /*NumInsns*/1, /*MergeInsnID's*/0,
        GIR_ConstrainSelectedInstOperands, /*InsnID*/0,
        GIR_EraseFromParent, /*InsnID*/0,
        // GIR_Coverage, 3186,
        GIR_Done,
      // Label 2434: @160021
      GIM_Try, /*On fail goto*//*Label 2435*/ GIMT_Encode4(160086), // Rule ID 3188 //
        GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasFlatGlobalInsts),
        GIM_CheckMemoryAddressSpace, /*MI*/0, /*MMO*/0, /*NumAddrSpace*/3, /*AddrSpace*/1, /*AddrSpace*/4, /*AddrSpace*/6,
        GIM_CheckRegBankForClass, /*MI*/0, /*Op*/0, /*RC*/GIMT_Encode2(AMDGPU::AV_32RegClassID),
        GIM_CheckPointerToAny, /*MI*/0, /*Op*/1, /*SizeInBits*/0,
        GIM_CheckComplexPattern, /*MI*/0, /*Op*/1, /*Renderer*/GIMT_Encode2(0), GIMT_Encode2(GICP_gi_global_offset),
        // (atomic_swap:{ *:[i32] } (GlobalOffset:{ *:[iPTR] } i64:{ *:[i64] }:$vaddr, i32:{ *:[i32] }:$offset), i32:{ *:[i32] }:$data)<<P:Predicate_atomic_swap_global_32>>  =>  (GLOBAL_ATOMIC_SWAP_RTN:{ *:[i32] } VReg_64:{ *:[i64] }:$vaddr, anonymous_15037:{ *:[i32] }:$data, ?:{ *:[i32] }:$offset)
        GIR_BuildMI, /*InsnID*/0, /*Opcode*/GIMT_Encode2(AMDGPU::GLOBAL_ATOMIC_SWAP_RTN),
        GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/0, // DstI[vdst]
        GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/0, // vaddr
        GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/2, // data
        GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/1, // offset
        GIR_AddImm8, /*InsnID*/0, /*Imm*/1,
        GIR_MergeMemOperands, /*InsnID*/0, /*NumInsns*/1, /*MergeInsnID's*/0,
        GIR_ConstrainSelectedInstOperands, /*InsnID*/0,
        GIR_EraseFromParent, /*InsnID*/0,
        // GIR_Coverage, 3188,
        GIR_Done,
      // Label 2435: @160086
      GIM_Try, /*On fail goto*//*Label 2436*/ GIMT_Encode4(160145), // Rule ID 2848 //
        GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasFlatAddressSpace),
        GIM_CheckMemoryAddressSpace, /*MI*/0, /*MMO*/0, /*NumAddrSpace*/4, /*AddrSpace*/0, /*AddrSpace*/1, /*AddrSpace*/4, /*AddrSpace*/6,
        GIM_CheckHasNoUse, /*MI*/0,
        GIM_CheckPointerToAny, /*MI*/0, /*Op*/1, /*SizeInBits*/0,
        GIM_CheckComplexPattern, /*MI*/0, /*Op*/1, /*Renderer*/GIMT_Encode2(0), GIMT_Encode2(GICP_gi_flat_offset),
        // (atomic_swap:{ *:[i32] } (FlatOffset:{ *:[iPTR] } i64:{ *:[i64] }:$vaddr, i32:{ *:[i32] }:$offset), i32:{ *:[i32] }:$data)<<P:Predicate_atomic_swap_flat_noret_32>>  =>  (FLAT_ATOMIC_SWAP VReg_64:{ *:[i64] }:$vaddr, anonymous_15037:{ *:[i32] }:$data, ?:{ *:[i32] }:$offset)
        GIR_BuildMI, /*InsnID*/0, /*Opcode*/GIMT_Encode2(AMDGPU::FLAT_ATOMIC_SWAP),
        GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/0, // vaddr
        GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/2, // data
        GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/1, // offset
        GIR_AddImm8, /*InsnID*/0, /*Imm*/0,
        GIR_MergeMemOperands, /*InsnID*/0, /*NumInsns*/1, /*MergeInsnID's*/0,
        GIR_ConstrainSelectedInstOperands, /*InsnID*/0,
        GIR_EraseFromParent, /*InsnID*/0,
        // GIR_Coverage, 2848,
        GIR_Done,
      // Label 2436: @160145
      GIM_Try, /*On fail goto*//*Label 2437*/ GIMT_Encode4(160203), // Rule ID 2900 //
        GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasFlatAddressSpace),
        GIM_CheckMemoryAddressSpace, /*MI*/0, /*MMO*/0, /*NumAddrSpace*/3, /*AddrSpace*/1, /*AddrSpace*/4, /*AddrSpace*/6,
        GIM_CheckHasNoUse, /*MI*/0,
        GIM_CheckPointerToAny, /*MI*/0, /*Op*/1, /*SizeInBits*/0,
        GIM_CheckComplexPattern, /*MI*/0, /*Op*/1, /*Renderer*/GIMT_Encode2(0), GIMT_Encode2(GICP_gi_flat_offset),
        // (atomic_swap:{ *:[i32] } (FlatOffset:{ *:[iPTR] } i64:{ *:[i64] }:$vaddr, i32:{ *:[i32] }:$offset), i32:{ *:[i32] }:$data)<<P:Predicate_atomic_swap_global_noret_32>>  =>  (FLAT_ATOMIC_SWAP VReg_64:{ *:[i64] }:$vaddr, anonymous_15037:{ *:[i32] }:$data, ?:{ *:[i32] }:$offset)
        GIR_BuildMI, /*InsnID*/0, /*Opcode*/GIMT_Encode2(AMDGPU::FLAT_ATOMIC_SWAP),
        GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/0, // vaddr
        GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/2, // data
        GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/1, // offset
        GIR_AddImm8, /*InsnID*/0, /*Imm*/0,
        GIR_MergeMemOperands, /*InsnID*/0, /*NumInsns*/1, /*MergeInsnID's*/0,
        GIR_ConstrainSelectedInstOperands, /*InsnID*/0,
        GIR_EraseFromParent, /*InsnID*/0,
        // GIR_Coverage, 2900,
        GIR_Done,
      // Label 2437: @160203
      GIM_Try, /*On fail goto*//*Label 2438*/ GIMT_Encode4(160269), // Rule ID 2847 //
        GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasFlatAddressSpace),
        GIM_CheckMemoryAddressSpace, /*MI*/0, /*MMO*/0, /*NumAddrSpace*/4, /*AddrSpace*/0, /*AddrSpace*/1, /*AddrSpace*/4, /*AddrSpace*/6,
        GIM_CheckRegBankForClass, /*MI*/0, /*Op*/0, /*RC*/GIMT_Encode2(AMDGPU::AV_32RegClassID),
        GIM_CheckPointerToAny, /*MI*/0, /*Op*/1, /*SizeInBits*/0,
        GIM_CheckComplexPattern, /*MI*/0, /*Op*/1, /*Renderer*/GIMT_Encode2(0), GIMT_Encode2(GICP_gi_flat_offset),
        // (atomic_swap:{ *:[i32] } (FlatOffset:{ *:[iPTR] } i64:{ *:[i64] }:$vaddr, i32:{ *:[i32] }:$offset), i32:{ *:[i32] }:$data)<<P:Predicate_atomic_swap_flat_32>>  =>  (FLAT_ATOMIC_SWAP_RTN:{ *:[i32] } VReg_64:{ *:[i64] }:$vaddr, anonymous_15037:{ *:[i32] }:$data, ?:{ *:[i32] }:$offset)
        GIR_BuildMI, /*InsnID*/0, /*Opcode*/GIMT_Encode2(AMDGPU::FLAT_ATOMIC_SWAP_RTN),
        GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/0, // DstI[vdst]
        GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/0, // vaddr
        GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/2, // data
        GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/1, // offset
        GIR_AddImm8, /*InsnID*/0, /*Imm*/1,
        GIR_MergeMemOperands, /*InsnID*/0, /*NumInsns*/1, /*MergeInsnID's*/0,
        GIR_ConstrainSelectedInstOperands, /*InsnID*/0,
        GIR_EraseFromParent, /*InsnID*/0,
        // GIR_Coverage, 2847,
        GIR_Done,
      // Label 2438: @160269
      GIM_Try, /*On fail goto*//*Label 2439*/ GIMT_Encode4(160334), // Rule ID 2899 //
        GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasFlatAddressSpace),
        GIM_CheckMemoryAddressSpace, /*MI*/0, /*MMO*/0, /*NumAddrSpace*/3, /*AddrSpace*/1, /*AddrSpace*/4, /*AddrSpace*/6,
        GIM_CheckRegBankForClass, /*MI*/0, /*Op*/0, /*RC*/GIMT_Encode2(AMDGPU::AV_32RegClassID),
        GIM_CheckPointerToAny, /*MI*/0, /*Op*/1, /*SizeInBits*/0,
        GIM_CheckComplexPattern, /*MI*/0, /*Op*/1, /*Renderer*/GIMT_Encode2(0), GIMT_Encode2(GICP_gi_flat_offset),
        // (atomic_swap:{ *:[i32] } (FlatOffset:{ *:[iPTR] } i64:{ *:[i64] }:$vaddr, i32:{ *:[i32] }:$offset), i32:{ *:[i32] }:$data)<<P:Predicate_atomic_swap_global_32>>  =>  (FLAT_ATOMIC_SWAP_RTN:{ *:[i32] } VReg_64:{ *:[i64] }:$vaddr, anonymous_15037:{ *:[i32] }:$data, ?:{ *:[i32] }:$offset)
        GIR_BuildMI, /*InsnID*/0, /*Opcode*/GIMT_Encode2(AMDGPU::FLAT_ATOMIC_SWAP_RTN),
        GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/0, // DstI[vdst]
        GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/0, // vaddr
        GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/2, // data
        GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/1, // offset
        GIR_AddImm8, /*InsnID*/0, /*Imm*/1,
        GIR_MergeMemOperands, /*InsnID*/0, /*NumInsns*/1, /*MergeInsnID's*/0,
        GIR_ConstrainSelectedInstOperands, /*InsnID*/0,
        GIR_EraseFromParent, /*InsnID*/0,
        // GIR_Coverage, 2899,
        GIR_Done,
      // Label 2439: @160334
      GIM_Reject,
    // Label 2420: @160335
    GIM_Reject,
    // Label 2418: @160336
    GIM_Try, /*On fail goto*//*Label 2440*/ GIMT_Encode4(161579),
      GIM_CheckType, /*MI*/0, /*Op*/2, /*Type*/GILLT_s64,
      GIM_Try, /*On fail goto*//*Label 2441*/ GIMT_Encode4(160413), // Rule ID 4606 //
        GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasUnrestrictedSOffset),
        GIM_CheckMemoryAddressSpace, /*MI*/0, /*MMO*/0, /*NumAddrSpace*/3, /*AddrSpace*/1, /*AddrSpace*/4, /*AddrSpace*/6,
        GIM_CheckHasNoUse, /*MI*/0,
        GIM_CheckPointerToAny, /*MI*/0, /*Op*/1, /*SizeInBits*/0,
        GIM_CheckComplexPattern, /*MI*/0, /*Op*/1, /*Renderer*/GIMT_Encode2(0), GIMT_Encode2(GICP_gi_mubuf_addr64),
        // (atomic_swap:{ *:[i64] } (MUBUFAddr64:{ *:[iPTR] } v4i32:{ *:[v4i32] }:$srsrc, i64:{ *:[i64] }:$vaddr, i32:{ *:[i32] }:$soffset, i32:{ *:[i32] }:$offset), i64:{ *:[i64] }:$vdata_in)<<P:Predicate_atomic_swap_global_noret_64>>  =>  (BUFFER_ATOMIC_SWAP_X2_ADDR64 anonymous_15036:{ *:[i64] }:$vdata_in, VReg_64:{ *:[i64] }:$vaddr, SReg_128:{ *:[v4i32] }:$srsrc, SCSrc_b32:{ *:[i32] }:$soffset, offset:{ *:[i32] }:$offset)
        GIR_BuildMI, /*InsnID*/0, /*Opcode*/GIMT_Encode2(AMDGPU::BUFFER_ATOMIC_SWAP_X2_ADDR64),
        GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/2, // vdata_in
        GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/1, // vaddr
        GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/0, // srsrc
        GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/2, // soffset
        GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/3, // offset
        GIR_AddImm8, /*InsnID*/0, /*Imm*/0,
        GIR_MergeMemOperands, /*InsnID*/0, /*NumInsns*/1, /*MergeInsnID's*/0,
        GIR_ConstrainSelectedInstOperands, /*InsnID*/0,
        GIR_EraseFromParent, /*InsnID*/0,
        // GIR_Coverage, 4606,
        GIR_Done,
      // Label 2441: @160413
      GIM_Try, /*On fail goto*//*Label 2442*/ GIMT_Encode4(160478), // Rule ID 4610 //
        GIM_CheckMemoryAddressSpace, /*MI*/0, /*MMO*/0, /*NumAddrSpace*/3, /*AddrSpace*/1, /*AddrSpace*/4, /*AddrSpace*/6,
        GIM_CheckHasNoUse, /*MI*/0,
        GIM_CheckPointerToAny, /*MI*/0, /*Op*/1, /*SizeInBits*/0,
        GIM_CheckComplexPattern, /*MI*/0, /*Op*/1, /*Renderer*/GIMT_Encode2(0), GIMT_Encode2(GICP_gi_mubuf_addr64),
        // (atomic_swap:{ *:[i64] } (MUBUFAddr64:{ *:[iPTR] } v4i32:{ *:[v4i32] }:$srsrc, i64:{ *:[i64] }:$vaddr, i32:{ *:[i32] }:$soffset, i32:{ *:[i32] }:$offset), i64:{ *:[i64] }:$vdata_in)<<P:Predicate_atomic_swap_global_noret_64>>  =>  (BUFFER_ATOMIC_SWAP_X2_VBUFFER_ADDR64 anonymous_15036:{ *:[i64] }:$vdata_in, VReg_64:{ *:[i64] }:$vaddr, SReg_128:{ *:[v4i32] }:$srsrc, SCSrc_b32:{ *:[i32] }:$soffset, offset:{ *:[i32] }:$offset)
        GIR_BuildMI, /*InsnID*/0, /*Opcode*/GIMT_Encode2(AMDGPU::BUFFER_ATOMIC_SWAP_X2_VBUFFER_ADDR64),
        GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/2, // vdata_in
        GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/1, // vaddr
        GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/0, // srsrc
        GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/2, // soffset
        GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/3, // offset
        GIR_AddImm8, /*InsnID*/0, /*Imm*/0,
        GIR_MergeMemOperands, /*InsnID*/0, /*NumInsns*/1, /*MergeInsnID's*/0,
        GIR_ConstrainSelectedInstOperands, /*InsnID*/0,
        GIR_EraseFromParent, /*InsnID*/0,
        // GIR_Coverage, 4610,
        GIR_Done,
      // Label 2442: @160478
      GIM_Try, /*On fail goto*//*Label 2443*/ GIMT_Encode4(160553), // Rule ID 4604 //
        GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasUnrestrictedSOffset),
        GIM_CheckMemoryAddressSpace, /*MI*/0, /*MMO*/0, /*NumAddrSpace*/3, /*AddrSpace*/1, /*AddrSpace*/4, /*AddrSpace*/6,
        GIM_CheckRegBankForClass, /*MI*/0, /*Op*/0, /*RC*/GIMT_Encode2(AMDGPU::AV_64RegClassID),
        GIM_CheckPointerToAny, /*MI*/0, /*Op*/1, /*SizeInBits*/0,
        GIM_CheckComplexPattern, /*MI*/0, /*Op*/1, /*Renderer*/GIMT_Encode2(0), GIMT_Encode2(GICP_gi_mubuf_addr64),
        // (atomic_swap:{ *:[i64] } (MUBUFAddr64:{ *:[iPTR] } v4i32:{ *:[v4i32] }:$srsrc, i64:{ *:[i64] }:$vaddr, i32:{ *:[i32] }:$soffset, i32:{ *:[i32] }:$offset), i64:{ *:[i64] }:$vdata_in)<<P:Predicate_atomic_swap_global_64>>  =>  (BUFFER_ATOMIC_SWAP_X2_ADDR64_RTN:{ *:[i64] } anonymous_15036:{ *:[i64] }:$vdata_in, VReg_64:{ *:[i64] }:$vaddr, SReg_128:{ *:[v4i32] }:$srsrc, SCSrc_b32:{ *:[i32] }:$soffset, offset:{ *:[i32] }:$offset)
        GIR_BuildMI, /*InsnID*/0, /*Opcode*/GIMT_Encode2(AMDGPU::BUFFER_ATOMIC_SWAP_X2_ADDR64_RTN),
        GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/0, // DstI[vdata]
        GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/2, // vdata_in
        GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/1, // vaddr
        GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/0, // srsrc
        GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/2, // soffset
        GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/3, // offset
        GIR_AddImm8, /*InsnID*/0, /*Imm*/1,
        GIR_MergeMemOperands, /*InsnID*/0, /*NumInsns*/1, /*MergeInsnID's*/0,
        GIR_ConstrainSelectedInstOperands, /*InsnID*/0,
        GIR_EraseFromParent, /*InsnID*/0,
        // GIR_Coverage, 4604,
        GIR_Done,
      // Label 2443: @160553
      GIM_Try, /*On fail goto*//*Label 2444*/ GIMT_Encode4(160625), // Rule ID 4608 //
        GIM_CheckMemoryAddressSpace, /*MI*/0, /*MMO*/0, /*NumAddrSpace*/3, /*AddrSpace*/1, /*AddrSpace*/4, /*AddrSpace*/6,
        GIM_CheckRegBankForClass, /*MI*/0, /*Op*/0, /*RC*/GIMT_Encode2(AMDGPU::AV_64RegClassID),
        GIM_CheckPointerToAny, /*MI*/0, /*Op*/1, /*SizeInBits*/0,
        GIM_CheckComplexPattern, /*MI*/0, /*Op*/1, /*Renderer*/GIMT_Encode2(0), GIMT_Encode2(GICP_gi_mubuf_addr64),
        // (atomic_swap:{ *:[i64] } (MUBUFAddr64:{ *:[iPTR] } v4i32:{ *:[v4i32] }:$srsrc, i64:{ *:[i64] }:$vaddr, i32:{ *:[i32] }:$soffset, i32:{ *:[i32] }:$offset), i64:{ *:[i64] }:$vdata_in)<<P:Predicate_atomic_swap_global_64>>  =>  (BUFFER_ATOMIC_SWAP_X2_VBUFFER_ADDR64_RTN:{ *:[i64] } anonymous_15036:{ *:[i64] }:$vdata_in, VReg_64:{ *:[i64] }:$vaddr, SReg_128:{ *:[v4i32] }:$srsrc, SCSrc_b32:{ *:[i32] }:$soffset, offset:{ *:[i32] }:$offset)
        GIR_BuildMI, /*InsnID*/0, /*Opcode*/GIMT_Encode2(AMDGPU::BUFFER_ATOMIC_SWAP_X2_VBUFFER_ADDR64_RTN),
        GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/0, // DstI[vdata]
        GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/2, // vdata_in
        GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/1, // vaddr
        GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/0, // srsrc
        GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/2, // soffset
        GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/3, // offset
        GIR_AddImm8, /*InsnID*/0, /*Imm*/1,
        GIR_MergeMemOperands, /*InsnID*/0, /*NumInsns*/1, /*MergeInsnID's*/0,
        GIR_ConstrainSelectedInstOperands, /*InsnID*/0,
        GIR_EraseFromParent, /*InsnID*/0,
        // GIR_Coverage, 4608,
        GIR_Done,
      // Label 2444: @160625
      GIM_Try, /*On fail goto*//*Label 2445*/ GIMT_Encode4(160688), // Rule ID 4605 //
        GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasUnrestrictedSOffset),
        GIM_CheckMemoryAddressSpace, /*MI*/0, /*MMO*/0, /*NumAddrSpace*/3, /*AddrSpace*/1, /*AddrSpace*/4, /*AddrSpace*/6,
        GIM_CheckHasNoUse, /*MI*/0,
        GIM_CheckPointerToAny, /*MI*/0, /*Op*/1, /*SizeInBits*/0,
        GIM_CheckComplexPattern, /*MI*/0, /*Op*/1, /*Renderer*/GIMT_Encode2(0), GIMT_Encode2(GICP_gi_mubuf_offset),
        // (atomic_swap:{ *:[i64] } (MUBUFOffset:{ *:[iPTR] } v4i32:{ *:[v4i32] }:$srsrc, i32:{ *:[i32] }:$soffset, i32:{ *:[i32] }:$offset), i64:{ *:[i64] }:$vdata_in)<<P:Predicate_atomic_swap_global_noret_64>>  =>  (BUFFER_ATOMIC_SWAP_X2_OFFSET anonymous_15036:{ *:[i64] }:$vdata_in, SReg_128:{ *:[v4i32] }:$srsrc, SCSrc_b32:{ *:[i32] }:$soffset, offset:{ *:[i32] }:$offset)
        GIR_BuildMI, /*InsnID*/0, /*Opcode*/GIMT_Encode2(AMDGPU::BUFFER_ATOMIC_SWAP_X2_OFFSET),
        GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/2, // vdata_in
        GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/0, // srsrc
        GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/1, // soffset
        GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/2, // offset
        GIR_AddImm8, /*InsnID*/0, /*Imm*/0,
        GIR_MergeMemOperands, /*InsnID*/0, /*NumInsns*/1, /*MergeInsnID's*/0,
        GIR_ConstrainSelectedInstOperands, /*InsnID*/0,
        GIR_EraseFromParent, /*InsnID*/0,
        // GIR_Coverage, 4605,
        GIR_Done,
      // Label 2445: @160688
      GIM_Try, /*On fail goto*//*Label 2446*/ GIMT_Encode4(160748), // Rule ID 4609 //
        GIM_CheckMemoryAddressSpace, /*MI*/0, /*MMO*/0, /*NumAddrSpace*/3, /*AddrSpace*/1, /*AddrSpace*/4, /*AddrSpace*/6,
        GIM_CheckHasNoUse, /*MI*/0,
        GIM_CheckPointerToAny, /*MI*/0, /*Op*/1, /*SizeInBits*/0,
        GIM_CheckComplexPattern, /*MI*/0, /*Op*/1, /*Renderer*/GIMT_Encode2(0), GIMT_Encode2(GICP_gi_mubuf_offset),
        // (atomic_swap:{ *:[i64] } (MUBUFOffset:{ *:[iPTR] } v4i32:{ *:[v4i32] }:$srsrc, i32:{ *:[i32] }:$soffset, i32:{ *:[i32] }:$offset), i64:{ *:[i64] }:$vdata_in)<<P:Predicate_atomic_swap_global_noret_64>>  =>  (BUFFER_ATOMIC_SWAP_X2_VBUFFER_OFFSET anonymous_15036:{ *:[i64] }:$vdata_in, SReg_128:{ *:[v4i32] }:$srsrc, SCSrc_b32:{ *:[i32] }:$soffset, offset:{ *:[i32] }:$offset)
        GIR_BuildMI, /*InsnID*/0, /*Opcode*/GIMT_Encode2(AMDGPU::BUFFER_ATOMIC_SWAP_X2_VBUFFER_OFFSET),
        GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/2, // vdata_in
        GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/0, // srsrc
        GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/1, // soffset
        GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/2, // offset
        GIR_AddImm8, /*InsnID*/0, /*Imm*/0,
        GIR_MergeMemOperands, /*InsnID*/0, /*NumInsns*/1, /*MergeInsnID's*/0,
        GIR_ConstrainSelectedInstOperands, /*InsnID*/0,
        GIR_EraseFromParent, /*InsnID*/0,
        // GIR_Coverage, 4609,
        GIR_Done,
      // Label 2446: @160748
      GIM_Try, /*On fail goto*//*Label 2447*/ GIMT_Encode4(160818), // Rule ID 4603 //
        GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasUnrestrictedSOffset),
        GIM_CheckMemoryAddressSpace, /*MI*/0, /*MMO*/0, /*NumAddrSpace*/3, /*AddrSpace*/1, /*AddrSpace*/4, /*AddrSpace*/6,
        GIM_CheckRegBankForClass, /*MI*/0, /*Op*/0, /*RC*/GIMT_Encode2(AMDGPU::AV_64RegClassID),
        GIM_CheckPointerToAny, /*MI*/0, /*Op*/1, /*SizeInBits*/0,
        GIM_CheckComplexPattern, /*MI*/0, /*Op*/1, /*Renderer*/GIMT_Encode2(0), GIMT_Encode2(GICP_gi_mubuf_offset),
        // (atomic_swap:{ *:[i64] } (MUBUFOffset:{ *:[iPTR] } v4i32:{ *:[v4i32] }:$srsrc, i32:{ *:[i32] }:$soffset, i32:{ *:[i32] }:$offset), i64:{ *:[i64] }:$vdata_in)<<P:Predicate_atomic_swap_global_64>>  =>  (BUFFER_ATOMIC_SWAP_X2_OFFSET_RTN:{ *:[i64] } anonymous_15036:{ *:[i64] }:$vdata_in, SReg_128:{ *:[v4i32] }:$srsrc, SCSrc_b32:{ *:[i32] }:$soffset, offset:{ *:[i32] }:$offset)
        GIR_BuildMI, /*InsnID*/0, /*Opcode*/GIMT_Encode2(AMDGPU::BUFFER_ATOMIC_SWAP_X2_OFFSET_RTN),
        GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/0, // DstI[vdata]
        GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/2, // vdata_in
        GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/0, // srsrc
        GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/1, // soffset
        GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/2, // offset
        GIR_AddImm8, /*InsnID*/0, /*Imm*/1,
        GIR_MergeMemOperands, /*InsnID*/0, /*NumInsns*/1, /*MergeInsnID's*/0,
        GIR_ConstrainSelectedInstOperands, /*InsnID*/0,
        GIR_EraseFromParent, /*InsnID*/0,
        // GIR_Coverage, 4603,
        GIR_Done,
      // Label 2447: @160818
      GIM_Try, /*On fail goto*//*Label 2448*/ GIMT_Encode4(160885), // Rule ID 4607 //
        GIM_CheckMemoryAddressSpace, /*MI*/0, /*MMO*/0, /*NumAddrSpace*/3, /*AddrSpace*/1, /*AddrSpace*/4, /*AddrSpace*/6,
        GIM_CheckRegBankForClass, /*MI*/0, /*Op*/0, /*RC*/GIMT_Encode2(AMDGPU::AV_64RegClassID),
        GIM_CheckPointerToAny, /*MI*/0, /*Op*/1, /*SizeInBits*/0,
        GIM_CheckComplexPattern, /*MI*/0, /*Op*/1, /*Renderer*/GIMT_Encode2(0), GIMT_Encode2(GICP_gi_mubuf_offset),
        // (atomic_swap:{ *:[i64] } (MUBUFOffset:{ *:[iPTR] } v4i32:{ *:[v4i32] }:$srsrc, i32:{ *:[i32] }:$soffset, i32:{ *:[i32] }:$offset), i64:{ *:[i64] }:$vdata_in)<<P:Predicate_atomic_swap_global_64>>  =>  (BUFFER_ATOMIC_SWAP_X2_VBUFFER_OFFSET_RTN:{ *:[i64] } anonymous_15036:{ *:[i64] }:$vdata_in, SReg_128:{ *:[v4i32] }:$srsrc, SCSrc_b32:{ *:[i32] }:$soffset, offset:{ *:[i32] }:$offset)
        GIR_BuildMI, /*InsnID*/0, /*Opcode*/GIMT_Encode2(AMDGPU::BUFFER_ATOMIC_SWAP_X2_VBUFFER_OFFSET_RTN),
        GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/0, // DstI[vdata]
        GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/2, // vdata_in
        GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/0, // srsrc
        GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/1, // soffset
        GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/2, // offset
        GIR_AddImm8, /*InsnID*/0, /*Imm*/1,
        GIR_MergeMemOperands, /*InsnID*/0, /*NumInsns*/1, /*MergeInsnID's*/0,
        GIR_ConstrainSelectedInstOperands, /*InsnID*/0,
        GIR_EraseFromParent, /*InsnID*/0,
        // GIR_Coverage, 4607,
        GIR_Done,
      // Label 2448: @160885
      GIM_Try, /*On fail goto*//*Label 2449*/ GIMT_Encode4(160948), // Rule ID 6988 //
        GIM_CheckFeatures, GIMT_Encode2(GIFBS_LDSRequiresM0Init),
        GIM_CheckMemoryAddressSpace, /*MI*/0, /*MMO*/0, /*NumAddrSpace*/1, /*AddrSpace*/3,
        GIM_CheckRegBankForClass, /*MI*/0, /*Op*/0, /*RC*/GIMT_Encode2(AMDGPU::AV_64RegClassID),
        GIM_CheckPointerToAny, /*MI*/0, /*Op*/1, /*SizeInBits*/0,
        GIM_CheckComplexPattern, /*MI*/0, /*Op*/1, /*Renderer*/GIMT_Encode2(0), GIMT_Encode2(GICP_gi_ds_1addr_1offset),
        // (atomic_swap_glue:{ *:[i64] } (DS1Addr1Offset:{ *:[iPTR] } i32:{ *:[i32] }:$ptr, i32:{ *:[i32] }:$offset), i64:{ *:[i64] }:$value)<<P:Predicate_atomic_swap_local_m0_64>>  =>  (DS_WRXCHG_RTN_B64:{ *:[i64] } ?:{ *:[i32] }:$ptr, anonymous_15036:{ *:[i64] }:$value, offset:{ *:[i32] }:$offset, 0:{ *:[i1] })
        GIR_BuildMI, /*InsnID*/0, /*Opcode*/GIMT_Encode2(AMDGPU::DS_WRXCHG_RTN_B64),
        GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/0, // DstI[vdst]
        GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/0, // ptr
        GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/2, // value
        GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/1, // offset
        GIR_AddImm8, /*InsnID*/0, /*Imm*/0,
        GIR_MergeMemOperands, /*InsnID*/0, /*NumInsns*/1, /*MergeInsnID's*/0,
        GIR_ConstrainSelectedInstOperands, /*InsnID*/0,
        GIR_EraseFromParent, /*InsnID*/0,
        // GIR_Coverage, 6988,
        GIR_Done,
      // Label 2449: @160948
      GIM_Try, /*On fail goto*//*Label 2450*/ GIMT_Encode4(161011), // Rule ID 6989 //
        GIM_CheckFeatures, GIMT_Encode2(GIFBS_NotLDSRequiresM0Init),
        GIM_CheckMemoryAddressSpace, /*MI*/0, /*MMO*/0, /*NumAddrSpace*/1, /*AddrSpace*/3,
        GIM_CheckRegBankForClass, /*MI*/0, /*Op*/0, /*RC*/GIMT_Encode2(AMDGPU::AV_64RegClassID),
        GIM_CheckPointerToAny, /*MI*/0, /*Op*/1, /*SizeInBits*/0,
        GIM_CheckComplexPattern, /*MI*/0, /*Op*/1, /*Renderer*/GIMT_Encode2(0), GIMT_Encode2(GICP_gi_ds_1addr_1offset),
        // (atomic_swap:{ *:[i64] } (DS1Addr1Offset:{ *:[iPTR] } i32:{ *:[i32] }:$ptr, i32:{ *:[i32] }:$offset), i64:{ *:[i64] }:$value)<<P:Predicate_atomic_swap_local_64>>  =>  (DS_WRXCHG_RTN_B64_gfx9:{ *:[i64] } ?:{ *:[i32] }:$ptr, anonymous_15036:{ *:[i64] }:$value, offset:{ *:[i32] }:$offset, 0:{ *:[i1] })
        GIR_BuildMI, /*InsnID*/0, /*Opcode*/GIMT_Encode2(AMDGPU::DS_WRXCHG_RTN_B64_gfx9),
        GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/0, // DstI[vdst]
        GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/0, // ptr
        GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/2, // value
        GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/1, // offset
        GIR_AddImm8, /*InsnID*/0, /*Imm*/0,
        GIR_MergeMemOperands, /*InsnID*/0, /*NumInsns*/1, /*MergeInsnID's*/0,
        GIR_ConstrainSelectedInstOperands, /*InsnID*/0,
        GIR_EraseFromParent, /*InsnID*/0,
        // GIR_Coverage, 6989,
        GIR_Done,
      // Label 2450: @161011
      GIM_Try, /*On fail goto*//*Label 2451*/ GIMT_Encode4(161074), // Rule ID 6990 //
        GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasGDS),
        GIM_CheckMemoryAddressSpace, /*MI*/0, /*MMO*/0, /*NumAddrSpace*/1, /*AddrSpace*/2,
        GIM_CheckRegBankForClass, /*MI*/0, /*Op*/0, /*RC*/GIMT_Encode2(AMDGPU::AV_64RegClassID),
        GIM_CheckPointerToAny, /*MI*/0, /*Op*/1, /*SizeInBits*/0,
        GIM_CheckComplexPattern, /*MI*/0, /*Op*/1, /*Renderer*/GIMT_Encode2(0), GIMT_Encode2(GICP_gi_ds_1addr_1offset),
        // (atomic_swap_glue:{ *:[i64] } (DS1Addr1Offset:{ *:[iPTR] } i32:{ *:[i32] }:$ptr, i32:{ *:[i32] }:$offset), i64:{ *:[i64] }:$value)<<P:Predicate_atomic_swap_region_m0_64>>  =>  (DS_WRXCHG_RTN_B64:{ *:[i64] } ?:{ *:[i32] }:$ptr, anonymous_15036:{ *:[i64] }:$value, offset:{ *:[i32] }:$offset, 1:{ *:[i1] })
        GIR_BuildMI, /*InsnID*/0, /*Opcode*/GIMT_Encode2(AMDGPU::DS_WRXCHG_RTN_B64),
        GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/0, // DstI[vdst]
        GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/0, // ptr
        GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/2, // value
        GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/1, // offset
        GIR_AddImm8, /*InsnID*/0, /*Imm*/1,
        GIR_MergeMemOperands, /*InsnID*/0, /*NumInsns*/1, /*MergeInsnID's*/0,
        GIR_ConstrainSelectedInstOperands, /*InsnID*/0,
        GIR_EraseFromParent, /*InsnID*/0,
        // GIR_Coverage, 6990,
        GIR_Done,
      // Label 2451: @161074
      GIM_Try, /*On fail goto*//*Label 2452*/ GIMT_Encode4(161137), // Rule ID 3243 //
        GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasFlatGlobalInsts),
        GIM_CheckMemoryAddressSpace, /*MI*/0, /*MMO*/0, /*NumAddrSpace*/3, /*AddrSpace*/1, /*AddrSpace*/4, /*AddrSpace*/6,
        GIM_CheckHasNoUse, /*MI*/0,
        GIM_CheckPointerToAny, /*MI*/0, /*Op*/1, /*SizeInBits*/0,
        GIM_CheckComplexPattern, /*MI*/0, /*Op*/1, /*Renderer*/GIMT_Encode2(0), GIMT_Encode2(GICP_gi_global_saddr),
        // (atomic_swap:{ *:[i64] } (GlobalSAddr:{ *:[iPTR] } SReg_64:{ *:[i64] }:$saddr, VGPR_32:{ *:[i32] }:$voffset, i32:{ *:[i32] }:$offset), i64:{ *:[i64] }:$data)<<P:Predicate_atomic_swap_global_noret_64>>  =>  (GLOBAL_ATOMIC_SWAP_X2_SADDR ?:{ *:[i32] }:$voffset, anonymous_15036:{ *:[i64] }:$data, ?:{ *:[i64] }:$saddr, ?:{ *:[i32] }:$offset)
        GIR_BuildMI, /*InsnID*/0, /*Opcode*/GIMT_Encode2(AMDGPU::GLOBAL_ATOMIC_SWAP_X2_SADDR),
        GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/1, // voffset
        GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/2, // data
        GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/0, // saddr
        GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/2, // offset
        GIR_AddImm8, /*InsnID*/0, /*Imm*/0,
        GIR_MergeMemOperands, /*InsnID*/0, /*NumInsns*/1, /*MergeInsnID's*/0,
        GIR_ConstrainSelectedInstOperands, /*InsnID*/0,
        GIR_EraseFromParent, /*InsnID*/0,
        // GIR_Coverage, 3243,
        GIR_Done,
      // Label 2452: @161137
      GIM_Try, /*On fail goto*//*Label 2453*/ GIMT_Encode4(161207), // Rule ID 3245 //
        GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasFlatGlobalInsts),
        GIM_CheckMemoryAddressSpace, /*MI*/0, /*MMO*/0, /*NumAddrSpace*/3, /*AddrSpace*/1, /*AddrSpace*/4, /*AddrSpace*/6,
        GIM_CheckRegBankForClass, /*MI*/0, /*Op*/0, /*RC*/GIMT_Encode2(AMDGPU::AV_64RegClassID),
        GIM_CheckPointerToAny, /*MI*/0, /*Op*/1, /*SizeInBits*/0,
        GIM_CheckComplexPattern, /*MI*/0, /*Op*/1, /*Renderer*/GIMT_Encode2(0), GIMT_Encode2(GICP_gi_global_saddr),
        // (atomic_swap:{ *:[i64] } (GlobalSAddr:{ *:[iPTR] } SReg_64:{ *:[i64] }:$saddr, VGPR_32:{ *:[i32] }:$voffset, i32:{ *:[i32] }:$offset), i64:{ *:[i64] }:$data)<<P:Predicate_atomic_swap_global_64>>  =>  (GLOBAL_ATOMIC_SWAP_X2_SADDR_RTN:{ *:[i64] } ?:{ *:[i32] }:$voffset, anonymous_15036:{ *:[i64] }:$data, ?:{ *:[i64] }:$saddr, ?:{ *:[i32] }:$offset)
        GIR_BuildMI, /*InsnID*/0, /*Opcode*/GIMT_Encode2(AMDGPU::GLOBAL_ATOMIC_SWAP_X2_SADDR_RTN),
        GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/0, // DstI[vdst]
        GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/1, // voffset
        GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/2, // data
        GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/0, // saddr
        GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/2, // offset
        GIR_AddImm8, /*InsnID*/0, /*Imm*/1,
        GIR_MergeMemOperands, /*InsnID*/0, /*NumInsns*/1, /*MergeInsnID's*/0,
        GIR_ConstrainSelectedInstOperands, /*InsnID*/0,
        GIR_EraseFromParent, /*InsnID*/0,
        // GIR_Coverage, 3245,
        GIR_Done,
      // Label 2453: @161207
      GIM_Try, /*On fail goto*//*Label 2454*/ GIMT_Encode4(161265), // Rule ID 3242 //
        GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasFlatGlobalInsts),
        GIM_CheckMemoryAddressSpace, /*MI*/0, /*MMO*/0, /*NumAddrSpace*/3, /*AddrSpace*/1, /*AddrSpace*/4, /*AddrSpace*/6,
        GIM_CheckHasNoUse, /*MI*/0,
        GIM_CheckPointerToAny, /*MI*/0, /*Op*/1, /*SizeInBits*/0,
        GIM_CheckComplexPattern, /*MI*/0, /*Op*/1, /*Renderer*/GIMT_Encode2(0), GIMT_Encode2(GICP_gi_global_offset),
        // (atomic_swap:{ *:[i64] } (GlobalOffset:{ *:[iPTR] } i64:{ *:[i64] }:$vaddr, i32:{ *:[i32] }:$offset), i64:{ *:[i64] }:$data)<<P:Predicate_atomic_swap_global_noret_64>>  =>  (GLOBAL_ATOMIC_SWAP_X2 VReg_64:{ *:[i64] }:$vaddr, anonymous_15036:{ *:[i64] }:$data, ?:{ *:[i32] }:$offset)
        GIR_BuildMI, /*InsnID*/0, /*Opcode*/GIMT_Encode2(AMDGPU::GLOBAL_ATOMIC_SWAP_X2),
        GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/0, // vaddr
        GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/2, // data
        GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/1, // offset
        GIR_AddImm8, /*InsnID*/0, /*Imm*/0,
        GIR_MergeMemOperands, /*InsnID*/0, /*NumInsns*/1, /*MergeInsnID's*/0,
        GIR_ConstrainSelectedInstOperands, /*InsnID*/0,
        GIR_EraseFromParent, /*InsnID*/0,
        // GIR_Coverage, 3242,
        GIR_Done,
      // Label 2454: @161265
      GIM_Try, /*On fail goto*//*Label 2455*/ GIMT_Encode4(161330), // Rule ID 3244 //
        GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasFlatGlobalInsts),
        GIM_CheckMemoryAddressSpace, /*MI*/0, /*MMO*/0, /*NumAddrSpace*/3, /*AddrSpace*/1, /*AddrSpace*/4, /*AddrSpace*/6,
        GIM_CheckRegBankForClass, /*MI*/0, /*Op*/0, /*RC*/GIMT_Encode2(AMDGPU::AV_64RegClassID),
        GIM_CheckPointerToAny, /*MI*/0, /*Op*/1, /*SizeInBits*/0,
        GIM_CheckComplexPattern, /*MI*/0, /*Op*/1, /*Renderer*/GIMT_Encode2(0), GIMT_Encode2(GICP_gi_global_offset),
        // (atomic_swap:{ *:[i64] } (GlobalOffset:{ *:[iPTR] } i64:{ *:[i64] }:$vaddr, i32:{ *:[i32] }:$offset), i64:{ *:[i64] }:$data)<<P:Predicate_atomic_swap_global_64>>  =>  (GLOBAL_ATOMIC_SWAP_X2_RTN:{ *:[i64] } VReg_64:{ *:[i64] }:$vaddr, anonymous_15036:{ *:[i64] }:$data, ?:{ *:[i32] }:$offset)
        GIR_BuildMI, /*InsnID*/0, /*Opcode*/GIMT_Encode2(AMDGPU::GLOBAL_ATOMIC_SWAP_X2_RTN),
        GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/0, // DstI[vdst]
        GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/0, // vaddr
        GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/2, // data
        GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/1, // offset
        GIR_AddImm8, /*InsnID*/0, /*Imm*/1,
        GIR_MergeMemOperands, /*InsnID*/0, /*NumInsns*/1, /*MergeInsnID's*/0,
        GIR_ConstrainSelectedInstOperands, /*InsnID*/0,
        GIR_EraseFromParent, /*InsnID*/0,
        // GIR_Coverage, 3244,
        GIR_Done,
      // Label 2455: @161330
      GIM_Try, /*On fail goto*//*Label 2456*/ GIMT_Encode4(161389), // Rule ID 2874 //
        GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasFlatAddressSpace),
        GIM_CheckMemoryAddressSpace, /*MI*/0, /*MMO*/0, /*NumAddrSpace*/4, /*AddrSpace*/0, /*AddrSpace*/1, /*AddrSpace*/4, /*AddrSpace*/6,
        GIM_CheckHasNoUse, /*MI*/0,
        GIM_CheckPointerToAny, /*MI*/0, /*Op*/1, /*SizeInBits*/0,
        GIM_CheckComplexPattern, /*MI*/0, /*Op*/1, /*Renderer*/GIMT_Encode2(0), GIMT_Encode2(GICP_gi_flat_offset),
        // (atomic_swap:{ *:[i64] } (FlatOffset:{ *:[iPTR] } i64:{ *:[i64] }:$vaddr, i32:{ *:[i32] }:$offset), i64:{ *:[i64] }:$data)<<P:Predicate_atomic_swap_flat_noret_64>>  =>  (FLAT_ATOMIC_SWAP_X2 VReg_64:{ *:[i64] }:$vaddr, anonymous_15036:{ *:[i64] }:$data, ?:{ *:[i32] }:$offset)
        GIR_BuildMI, /*InsnID*/0, /*Opcode*/GIMT_Encode2(AMDGPU::FLAT_ATOMIC_SWAP_X2),
        GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/0, // vaddr
        GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/2, // data
        GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/1, // offset
        GIR_AddImm8, /*InsnID*/0, /*Imm*/0,
        GIR_MergeMemOperands, /*InsnID*/0, /*NumInsns*/1, /*MergeInsnID's*/0,
        GIR_ConstrainSelectedInstOperands, /*InsnID*/0,
        GIR_EraseFromParent, /*InsnID*/0,
        // GIR_Coverage, 2874,
        GIR_Done,
      // Label 2456: @161389
      GIM_Try, /*On fail goto*//*Label 2457*/ GIMT_Encode4(161447), // Rule ID 2926 //
        GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasFlatAddressSpace),
        GIM_CheckMemoryAddressSpace, /*MI*/0, /*MMO*/0, /*NumAddrSpace*/3, /*AddrSpace*/1, /*AddrSpace*/4, /*AddrSpace*/6,
        GIM_CheckHasNoUse, /*MI*/0,
        GIM_CheckPointerToAny, /*MI*/0, /*Op*/1, /*SizeInBits*/0,
        GIM_CheckComplexPattern, /*MI*/0, /*Op*/1, /*Renderer*/GIMT_Encode2(0), GIMT_Encode2(GICP_gi_flat_offset),
        // (atomic_swap:{ *:[i64] } (FlatOffset:{ *:[iPTR] } i64:{ *:[i64] }:$vaddr, i32:{ *:[i32] }:$offset), i64:{ *:[i64] }:$data)<<P:Predicate_atomic_swap_global_noret_64>>  =>  (FLAT_ATOMIC_SWAP_X2 VReg_64:{ *:[i64] }:$vaddr, anonymous_15036:{ *:[i64] }:$data, ?:{ *:[i32] }:$offset)
        GIR_BuildMI, /*InsnID*/0, /*Opcode*/GIMT_Encode2(AMDGPU::FLAT_ATOMIC_SWAP_X2),
        GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/0, // vaddr
        GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/2, // data
        GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/1, // offset
        GIR_AddImm8, /*InsnID*/0, /*Imm*/0,
        GIR_MergeMemOperands, /*InsnID*/0, /*NumInsns*/1, /*MergeInsnID's*/0,
        GIR_ConstrainSelectedInstOperands, /*InsnID*/0,
        GIR_EraseFromParent, /*InsnID*/0,
        // GIR_Coverage, 2926,
        GIR_Done,
      // Label 2457: @161447
      GIM_Try, /*On fail goto*//*Label 2458*/ GIMT_Encode4(161513), // Rule ID 2873 //
        GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasFlatAddressSpace),
        GIM_CheckMemoryAddressSpace, /*MI*/0, /*MMO*/0, /*NumAddrSpace*/4, /*AddrSpace*/0, /*AddrSpace*/1, /*AddrSpace*/4, /*AddrSpace*/6,
        GIM_CheckRegBankForClass, /*MI*/0, /*Op*/0, /*RC*/GIMT_Encode2(AMDGPU::AV_64RegClassID),
        GIM_CheckPointerToAny, /*MI*/0, /*Op*/1, /*SizeInBits*/0,
        GIM_CheckComplexPattern, /*MI*/0, /*Op*/1, /*Renderer*/GIMT_Encode2(0), GIMT_Encode2(GICP_gi_flat_offset),
        // (atomic_swap:{ *:[i64] } (FlatOffset:{ *:[iPTR] } i64:{ *:[i64] }:$vaddr, i32:{ *:[i32] }:$offset), i64:{ *:[i64] }:$data)<<P:Predicate_atomic_swap_flat_64>>  =>  (FLAT_ATOMIC_SWAP_X2_RTN:{ *:[i64] } VReg_64:{ *:[i64] }:$vaddr, anonymous_15036:{ *:[i64] }:$data, ?:{ *:[i32] }:$offset)
        GIR_BuildMI, /*InsnID*/0, /*Opcode*/GIMT_Encode2(AMDGPU::FLAT_ATOMIC_SWAP_X2_RTN),
        GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/0, // DstI[vdst]
        GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/0, // vaddr
        GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/2, // data
        GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/1, // offset
        GIR_AddImm8, /*InsnID*/0, /*Imm*/1,
        GIR_MergeMemOperands, /*InsnID*/0, /*NumInsns*/1, /*MergeInsnID's*/0,
        GIR_ConstrainSelectedInstOperands, /*InsnID*/0,
        GIR_EraseFromParent, /*InsnID*/0,
        // GIR_Coverage, 2873,
        GIR_Done,
      // Label 2458: @161513
      GIM_Try, /*On fail goto*//*Label 2459*/ GIMT_Encode4(161578), // Rule ID 2925 //
        GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasFlatAddressSpace),
        GIM_CheckMemoryAddressSpace, /*MI*/0, /*MMO*/0, /*NumAddrSpace*/3, /*AddrSpace*/1, /*AddrSpace*/4, /*AddrSpace*/6,
        GIM_CheckRegBankForClass, /*MI*/0, /*Op*/0, /*RC*/GIMT_Encode2(AMDGPU::AV_64RegClassID),
        GIM_CheckPointerToAny, /*MI*/0, /*Op*/1, /*SizeInBits*/0,
        GIM_CheckComplexPattern, /*MI*/0, /*Op*/1, /*Renderer*/GIMT_Encode2(0), GIMT_Encode2(GICP_gi_flat_offset),
        // (atomic_swap:{ *:[i64] } (FlatOffset:{ *:[iPTR] } i64:{ *:[i64] }:$vaddr, i32:{ *:[i32] }:$offset), i64:{ *:[i64] }:$data)<<P:Predicate_atomic_swap_global_64>>  =>  (FLAT_ATOMIC_SWAP_X2_RTN:{ *:[i64] } VReg_64:{ *:[i64] }:$vaddr, anonymous_15036:{ *:[i64] }:$data, ?:{ *:[i32] }:$offset)
        GIR_BuildMI, /*InsnID*/0, /*Opcode*/GIMT_Encode2(AMDGPU::FLAT_ATOMIC_SWAP_X2_RTN),
        GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/0, // DstI[vdst]
        GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/0, // vaddr
        GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/2, // data
        GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/1, // offset
        GIR_AddImm8, /*InsnID*/0, /*Imm*/1,
        GIR_MergeMemOperands, /*InsnID*/0, /*NumInsns*/1, /*MergeInsnID's*/0,
        GIR_ConstrainSelectedInstOperands, /*InsnID*/0,
        GIR_EraseFromParent, /*InsnID*/0,
        // GIR_Coverage, 2925,
        GIR_Done,
      // Label 2459: @161578
      GIM_Reject,
    // Label 2440: @161579
    GIM_Reject,
    // Label 2419: @161580
    GIM_Reject,
    // Label 18: @161581
    GIM_SwitchType, /*MI*/0, /*Op*/0, /*[*/GIMT_Encode2(9), GIMT_Encode2(11), /*)*//*default:*//*Label 2462*/ GIMT_Encode4(164424),
    /*GILLT_s32*//*Label 2460*/ GIMT_Encode4(161600),
    /*GILLT_s64*//*Label 2461*/ GIMT_Encode4(163012),
    // Label 2460: @161600
    GIM_Try, /*On fail goto*//*Label 2463*/ GIMT_Encode4(163011),
      GIM_CheckType, /*MI*/0, /*Op*/2, /*Type*/GILLT_s32,
      GIM_Try, /*On fail goto*//*Label 2464*/ GIMT_Encode4(161677), // Rule ID 4518 //
        GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasUnrestrictedSOffset),
        GIM_CheckMemoryAddressSpace, /*MI*/0, /*MMO*/0, /*NumAddrSpace*/3, /*AddrSpace*/1, /*AddrSpace*/4, /*AddrSpace*/6,
        GIM_CheckHasNoUse, /*MI*/0,
        GIM_CheckPointerToAny, /*MI*/0, /*Op*/1, /*SizeInBits*/0,
        GIM_CheckComplexPattern, /*MI*/0, /*Op*/1, /*Renderer*/GIMT_Encode2(0), GIMT_Encode2(GICP_gi_mubuf_addr64),
        // (atomic_load_add:{ *:[i32] } (MUBUFAddr64:{ *:[iPTR] } v4i32:{ *:[v4i32] }:$srsrc, i64:{ *:[i64] }:$vaddr, i32:{ *:[i32] }:$soffset, i32:{ *:[i32] }:$offset), i32:{ *:[i32] }:$vdata_in)<<P:Predicate_atomic_load_add_global_noret_32>>  =>  (BUFFER_ATOMIC_ADD_ADDR64 anonymous_15037:{ *:[i32] }:$vdata_in, VReg_64:{ *:[i64] }:$vaddr, SReg_128:{ *:[v4i32] }:$srsrc, SCSrc_b32:{ *:[i32] }:$soffset, offset:{ *:[i32] }:$offset)
        GIR_BuildMI, /*InsnID*/0, /*Opcode*/GIMT_Encode2(AMDGPU::BUFFER_ATOMIC_ADD_ADDR64),
        GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/2, // vdata_in
        GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/1, // vaddr
        GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/0, // srsrc
        GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/2, // soffset
        GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/3, // offset
        GIR_AddImm8, /*InsnID*/0, /*Imm*/0,
        GIR_MergeMemOperands, /*InsnID*/0, /*NumInsns*/1, /*MergeInsnID's*/0,
        GIR_ConstrainSelectedInstOperands, /*InsnID*/0,
        GIR_EraseFromParent, /*InsnID*/0,
        // GIR_Coverage, 4518,
        GIR_Done,
      // Label 2464: @161677
      GIM_Try, /*On fail goto*//*Label 2465*/ GIMT_Encode4(161742), // Rule ID 4522 //
        GIM_CheckMemoryAddressSpace, /*MI*/0, /*MMO*/0, /*NumAddrSpace*/3, /*AddrSpace*/1, /*AddrSpace*/4, /*AddrSpace*/6,
        GIM_CheckHasNoUse, /*MI*/0,
        GIM_CheckPointerToAny, /*MI*/0, /*Op*/1, /*SizeInBits*/0,
        GIM_CheckComplexPattern, /*MI*/0, /*Op*/1, /*Renderer*/GIMT_Encode2(0), GIMT_Encode2(GICP_gi_mubuf_addr64),
        // (atomic_load_add:{ *:[i32] } (MUBUFAddr64:{ *:[iPTR] } v4i32:{ *:[v4i32] }:$srsrc, i64:{ *:[i64] }:$vaddr, i32:{ *:[i32] }:$soffset, i32:{ *:[i32] }:$offset), i32:{ *:[i32] }:$vdata_in)<<P:Predicate_atomic_load_add_global_noret_32>>  =>  (BUFFER_ATOMIC_ADD_VBUFFER_ADDR64 anonymous_15037:{ *:[i32] }:$vdata_in, VReg_64:{ *:[i64] }:$vaddr, SReg_128:{ *:[v4i32] }:$srsrc, SCSrc_b32:{ *:[i32] }:$soffset, offset:{ *:[i32] }:$offset)
        GIR_BuildMI, /*InsnID*/0, /*Opcode*/GIMT_Encode2(AMDGPU::BUFFER_ATOMIC_ADD_VBUFFER_ADDR64),
        GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/2, // vdata_in
        GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/1, // vaddr
        GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/0, // srsrc
        GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/2, // soffset
        GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/3, // offset
        GIR_AddImm8, /*InsnID*/0, /*Imm*/0,
        GIR_MergeMemOperands, /*InsnID*/0, /*NumInsns*/1, /*MergeInsnID's*/0,
        GIR_ConstrainSelectedInstOperands, /*InsnID*/0,
        GIR_EraseFromParent, /*InsnID*/0,
        // GIR_Coverage, 4522,
        GIR_Done,
      // Label 2465: @161742
      GIM_Try, /*On fail goto*//*Label 2466*/ GIMT_Encode4(161817), // Rule ID 4516 //
        GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasUnrestrictedSOffset),
        GIM_CheckMemoryAddressSpace, /*MI*/0, /*MMO*/0, /*NumAddrSpace*/3, /*AddrSpace*/1, /*AddrSpace*/4, /*AddrSpace*/6,
        GIM_CheckRegBankForClass, /*MI*/0, /*Op*/0, /*RC*/GIMT_Encode2(AMDGPU::AV_32RegClassID),
        GIM_CheckPointerToAny, /*MI*/0, /*Op*/1, /*SizeInBits*/0,
        GIM_CheckComplexPattern, /*MI*/0, /*Op*/1, /*Renderer*/GIMT_Encode2(0), GIMT_Encode2(GICP_gi_mubuf_addr64),
        // (atomic_load_add:{ *:[i32] } (MUBUFAddr64:{ *:[iPTR] } v4i32:{ *:[v4i32] }:$srsrc, i64:{ *:[i64] }:$vaddr, i32:{ *:[i32] }:$soffset, i32:{ *:[i32] }:$offset), i32:{ *:[i32] }:$vdata_in)<<P:Predicate_atomic_load_add_global_32>>  =>  (BUFFER_ATOMIC_ADD_ADDR64_RTN:{ *:[i32] } anonymous_15037:{ *:[i32] }:$vdata_in, VReg_64:{ *:[i64] }:$vaddr, SReg_128:{ *:[v4i32] }:$srsrc, SCSrc_b32:{ *:[i32] }:$soffset, offset:{ *:[i32] }:$offset)
        GIR_BuildMI, /*InsnID*/0, /*Opcode*/GIMT_Encode2(AMDGPU::BUFFER_ATOMIC_ADD_ADDR64_RTN),
        GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/0, // DstI[vdata]
        GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/2, // vdata_in
        GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/1, // vaddr
        GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/0, // srsrc
        GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/2, // soffset
        GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/3, // offset
        GIR_AddImm8, /*InsnID*/0, /*Imm*/1,
        GIR_MergeMemOperands, /*InsnID*/0, /*NumInsns*/1, /*MergeInsnID's*/0,
        GIR_ConstrainSelectedInstOperands, /*InsnID*/0,
        GIR_EraseFromParent, /*InsnID*/0,
        // GIR_Coverage, 4516,
        GIR_Done,
      // Label 2466: @161817
      GIM_Try, /*On fail goto*//*Label 2467*/ GIMT_Encode4(161889), // Rule ID 4520 //
        GIM_CheckMemoryAddressSpace, /*MI*/0, /*MMO*/0, /*NumAddrSpace*/3, /*AddrSpace*/1, /*AddrSpace*/4, /*AddrSpace*/6,
        GIM_CheckRegBankForClass, /*MI*/0, /*Op*/0, /*RC*/GIMT_Encode2(AMDGPU::AV_32RegClassID),
        GIM_CheckPointerToAny, /*MI*/0, /*Op*/1, /*SizeInBits*/0,
        GIM_CheckComplexPattern, /*MI*/0, /*Op*/1, /*Renderer*/GIMT_Encode2(0), GIMT_Encode2(GICP_gi_mubuf_addr64),
        // (atomic_load_add:{ *:[i32] } (MUBUFAddr64:{ *:[iPTR] } v4i32:{ *:[v4i32] }:$srsrc, i64:{ *:[i64] }:$vaddr, i32:{ *:[i32] }:$soffset, i32:{ *:[i32] }:$offset), i32:{ *:[i32] }:$vdata_in)<<P:Predicate_atomic_load_add_global_32>>  =>  (BUFFER_ATOMIC_ADD_VBUFFER_ADDR64_RTN:{ *:[i32] } anonymous_15037:{ *:[i32] }:$vdata_in, VReg_64:{ *:[i64] }:$vaddr, SReg_128:{ *:[v4i32] }:$srsrc, SCSrc_b32:{ *:[i32] }:$soffset, offset:{ *:[i32] }:$offset)
        GIR_BuildMI, /*InsnID*/0, /*Opcode*/GIMT_Encode2(AMDGPU::BUFFER_ATOMIC_ADD_VBUFFER_ADDR64_RTN),
        GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/0, // DstI[vdata]
        GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/2, // vdata_in
        GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/1, // vaddr
        GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/0, // srsrc
        GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/2, // soffset
        GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/3, // offset
        GIR_AddImm8, /*InsnID*/0, /*Imm*/1,
        GIR_MergeMemOperands, /*InsnID*/0, /*NumInsns*/1, /*MergeInsnID's*/0,
        GIR_ConstrainSelectedInstOperands, /*InsnID*/0,
        GIR_EraseFromParent, /*InsnID*/0,
        // GIR_Coverage, 4520,
        GIR_Done,
      // Label 2467: @161889
      GIM_Try, /*On fail goto*//*Label 2468*/ GIMT_Encode4(161952), // Rule ID 4517 //
        GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasUnrestrictedSOffset),
        GIM_CheckMemoryAddressSpace, /*MI*/0, /*MMO*/0, /*NumAddrSpace*/3, /*AddrSpace*/1, /*AddrSpace*/4, /*AddrSpace*/6,
        GIM_CheckHasNoUse, /*MI*/0,
        GIM_CheckPointerToAny, /*MI*/0, /*Op*/1, /*SizeInBits*/0,
        GIM_CheckComplexPattern, /*MI*/0, /*Op*/1, /*Renderer*/GIMT_Encode2(0), GIMT_Encode2(GICP_gi_mubuf_offset),
        // (atomic_load_add:{ *:[i32] } (MUBUFOffset:{ *:[iPTR] } v4i32:{ *:[v4i32] }:$srsrc, i32:{ *:[i32] }:$soffset, i32:{ *:[i32] }:$offset), i32:{ *:[i32] }:$vdata_in)<<P:Predicate_atomic_load_add_global_noret_32>>  =>  (BUFFER_ATOMIC_ADD_OFFSET anonymous_15037:{ *:[i32] }:$vdata_in, SReg_128:{ *:[v4i32] }:$srsrc, SCSrc_b32:{ *:[i32] }:$soffset, offset:{ *:[i32] }:$offset)
        GIR_BuildMI, /*InsnID*/0, /*Opcode*/GIMT_Encode2(AMDGPU::BUFFER_ATOMIC_ADD_OFFSET),
        GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/2, // vdata_in
        GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/0, // srsrc
        GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/1, // soffset
        GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/2, // offset
        GIR_AddImm8, /*InsnID*/0, /*Imm*/0,
        GIR_MergeMemOperands, /*InsnID*/0, /*NumInsns*/1, /*MergeInsnID's*/0,
        GIR_ConstrainSelectedInstOperands, /*InsnID*/0,
        GIR_EraseFromParent, /*InsnID*/0,
        // GIR_Coverage, 4517,
        GIR_Done,
      // Label 2468: @161952
      GIM_Try, /*On fail goto*//*Label 2469*/ GIMT_Encode4(162012), // Rule ID 4521 //
        GIM_CheckMemoryAddressSpace, /*MI*/0, /*MMO*/0, /*NumAddrSpace*/3, /*AddrSpace*/1, /*AddrSpace*/4, /*AddrSpace*/6,
        GIM_CheckHasNoUse, /*MI*/0,
        GIM_CheckPointerToAny, /*MI*/0, /*Op*/1, /*SizeInBits*/0,
        GIM_CheckComplexPattern, /*MI*/0, /*Op*/1, /*Renderer*/GIMT_Encode2(0), GIMT_Encode2(GICP_gi_mubuf_offset),
        // (atomic_load_add:{ *:[i32] } (MUBUFOffset:{ *:[iPTR] } v4i32:{ *:[v4i32] }:$srsrc, i32:{ *:[i32] }:$soffset, i32:{ *:[i32] }:$offset), i32:{ *:[i32] }:$vdata_in)<<P:Predicate_atomic_load_add_global_noret_32>>  =>  (BUFFER_ATOMIC_ADD_VBUFFER_OFFSET anonymous_15037:{ *:[i32] }:$vdata_in, SReg_128:{ *:[v4i32] }:$srsrc, SCSrc_b32:{ *:[i32] }:$soffset, offset:{ *:[i32] }:$offset)
        GIR_BuildMI, /*InsnID*/0, /*Opcode*/GIMT_Encode2(AMDGPU::BUFFER_ATOMIC_ADD_VBUFFER_OFFSET),
        GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/2, // vdata_in
        GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/0, // srsrc
        GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/1, // soffset
        GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/2, // offset
        GIR_AddImm8, /*InsnID*/0, /*Imm*/0,
        GIR_MergeMemOperands, /*InsnID*/0, /*NumInsns*/1, /*MergeInsnID's*/0,
        GIR_ConstrainSelectedInstOperands, /*InsnID*/0,
        GIR_EraseFromParent, /*InsnID*/0,
        // GIR_Coverage, 4521,
        GIR_Done,
      // Label 2469: @162012
      GIM_Try, /*On fail goto*//*Label 2470*/ GIMT_Encode4(162082), // Rule ID 4515 //
        GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasUnrestrictedSOffset),
        GIM_CheckMemoryAddressSpace, /*MI*/0, /*MMO*/0, /*NumAddrSpace*/3, /*AddrSpace*/1, /*AddrSpace*/4, /*AddrSpace*/6,
        GIM_CheckRegBankForClass, /*MI*/0, /*Op*/0, /*RC*/GIMT_Encode2(AMDGPU::AV_32RegClassID),
        GIM_CheckPointerToAny, /*MI*/0, /*Op*/1, /*SizeInBits*/0,
        GIM_CheckComplexPattern, /*MI*/0, /*Op*/1, /*Renderer*/GIMT_Encode2(0), GIMT_Encode2(GICP_gi_mubuf_offset),
        // (atomic_load_add:{ *:[i32] } (MUBUFOffset:{ *:[iPTR] } v4i32:{ *:[v4i32] }:$srsrc, i32:{ *:[i32] }:$soffset, i32:{ *:[i32] }:$offset), i32:{ *:[i32] }:$vdata_in)<<P:Predicate_atomic_load_add_global_32>>  =>  (BUFFER_ATOMIC_ADD_OFFSET_RTN:{ *:[i32] } anonymous_15037:{ *:[i32] }:$vdata_in, SReg_128:{ *:[v4i32] }:$srsrc, SCSrc_b32:{ *:[i32] }:$soffset, offset:{ *:[i32] }:$offset)
        GIR_BuildMI, /*InsnID*/0, /*Opcode*/GIMT_Encode2(AMDGPU::BUFFER_ATOMIC_ADD_OFFSET_RTN),
        GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/0, // DstI[vdata]
        GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/2, // vdata_in
        GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/0, // srsrc
        GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/1, // soffset
        GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/2, // offset
        GIR_AddImm8, /*InsnID*/0, /*Imm*/1,
        GIR_MergeMemOperands, /*InsnID*/0, /*NumInsns*/1, /*MergeInsnID's*/0,
        GIR_ConstrainSelectedInstOperands, /*InsnID*/0,
        GIR_EraseFromParent, /*InsnID*/0,
        // GIR_Coverage, 4515,
        GIR_Done,
      // Label 2470: @162082
      GIM_Try, /*On fail goto*//*Label 2471*/ GIMT_Encode4(162149), // Rule ID 4519 //
        GIM_CheckMemoryAddressSpace, /*MI*/0, /*MMO*/0, /*NumAddrSpace*/3, /*AddrSpace*/1, /*AddrSpace*/4, /*AddrSpace*/6,
        GIM_CheckRegBankForClass, /*MI*/0, /*Op*/0, /*RC*/GIMT_Encode2(AMDGPU::AV_32RegClassID),
        GIM_CheckPointerToAny, /*MI*/0, /*Op*/1, /*SizeInBits*/0,
        GIM_CheckComplexPattern, /*MI*/0, /*Op*/1, /*Renderer*/GIMT_Encode2(0), GIMT_Encode2(GICP_gi_mubuf_offset),
        // (atomic_load_add:{ *:[i32] } (MUBUFOffset:{ *:[iPTR] } v4i32:{ *:[v4i32] }:$srsrc, i32:{ *:[i32] }:$soffset, i32:{ *:[i32] }:$offset), i32:{ *:[i32] }:$vdata_in)<<P:Predicate_atomic_load_add_global_32>>  =>  (BUFFER_ATOMIC_ADD_VBUFFER_OFFSET_RTN:{ *:[i32] } anonymous_15037:{ *:[i32] }:$vdata_in, SReg_128:{ *:[v4i32] }:$srsrc, SCSrc_b32:{ *:[i32] }:$soffset, offset:{ *:[i32] }:$offset)
        GIR_BuildMI, /*InsnID*/0, /*Opcode*/GIMT_Encode2(AMDGPU::BUFFER_ATOMIC_ADD_VBUFFER_OFFSET_RTN),
        GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/0, // DstI[vdata]
        GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/2, // vdata_in
        GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/0, // srsrc
        GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/1, // soffset
        GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/2, // offset
        GIR_AddImm8, /*InsnID*/0, /*Imm*/1,
        GIR_MergeMemOperands, /*InsnID*/0, /*NumInsns*/1, /*MergeInsnID's*/0,
        GIR_ConstrainSelectedInstOperands, /*InsnID*/0,
        GIR_EraseFromParent, /*InsnID*/0,
        // GIR_Coverage, 4519,
        GIR_Done,
      // Label 2471: @162149
      GIM_Try, /*On fail goto*//*Label 2472*/ GIMT_Encode4(162205), // Rule ID 6895 //
        GIM_CheckFeatures, GIMT_Encode2(GIFBS_LDSRequiresM0Init),
        GIM_CheckMemoryAddressSpace, /*MI*/0, /*MMO*/0, /*NumAddrSpace*/1, /*AddrSpace*/3,
        GIM_CheckHasNoUse, /*MI*/0,
        GIM_CheckPointerToAny, /*MI*/0, /*Op*/1, /*SizeInBits*/0,
        GIM_CheckComplexPattern, /*MI*/0, /*Op*/1, /*Renderer*/GIMT_Encode2(0), GIMT_Encode2(GICP_gi_ds_1addr_1offset),
        // (atomic_load_add_glue:{ *:[i32] } (DS1Addr1Offset:{ *:[iPTR] } i32:{ *:[i32] }:$ptr, i32:{ *:[i32] }:$offset), i32:{ *:[i32] }:$value)<<P:Predicate_atomic_load_add_local_m0_noret_32>>  =>  (DS_ADD_U32 ?:{ *:[i32] }:$ptr, anonymous_15037:{ *:[i32] }:$value, offset:{ *:[i32] }:$offset, 0:{ *:[i1] })
        GIR_BuildMI, /*InsnID*/0, /*Opcode*/GIMT_Encode2(AMDGPU::DS_ADD_U32),
        GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/0, // ptr
        GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/2, // value
        GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/1, // offset
        GIR_AddImm8, /*InsnID*/0, /*Imm*/0,
        GIR_MergeMemOperands, /*InsnID*/0, /*NumInsns*/1, /*MergeInsnID's*/0,
        GIR_ConstrainSelectedInstOperands, /*InsnID*/0,
        GIR_EraseFromParent, /*InsnID*/0,
        // GIR_Coverage, 6895,
        GIR_Done,
      // Label 2472: @162205
      GIM_Try, /*On fail goto*//*Label 2473*/ GIMT_Encode4(162261), // Rule ID 6897 //
        GIM_CheckFeatures, GIMT_Encode2(GIFBS_NotLDSRequiresM0Init),
        GIM_CheckMemoryAddressSpace, /*MI*/0, /*MMO*/0, /*NumAddrSpace*/1, /*AddrSpace*/3,
        GIM_CheckHasNoUse, /*MI*/0,
        GIM_CheckPointerToAny, /*MI*/0, /*Op*/1, /*SizeInBits*/0,
        GIM_CheckComplexPattern, /*MI*/0, /*Op*/1, /*Renderer*/GIMT_Encode2(0), GIMT_Encode2(GICP_gi_ds_1addr_1offset),
        // (atomic_load_add:{ *:[i32] } (DS1Addr1Offset:{ *:[iPTR] } i32:{ *:[i32] }:$ptr, i32:{ *:[i32] }:$offset), i32:{ *:[i32] }:$value)<<P:Predicate_atomic_load_add_local_noret_32>>  =>  (DS_ADD_U32_gfx9 ?:{ *:[i32] }:$ptr, anonymous_15037:{ *:[i32] }:$value, offset:{ *:[i32] }:$offset, 0:{ *:[i1] })
        GIR_BuildMI, /*InsnID*/0, /*Opcode*/GIMT_Encode2(AMDGPU::DS_ADD_U32_gfx9),
        GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/0, // ptr
        GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/2, // value
        GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/1, // offset
        GIR_AddImm8, /*InsnID*/0, /*Imm*/0,
        GIR_MergeMemOperands, /*InsnID*/0, /*NumInsns*/1, /*MergeInsnID's*/0,
        GIR_ConstrainSelectedInstOperands, /*InsnID*/0,
        GIR_EraseFromParent, /*InsnID*/0,
        // GIR_Coverage, 6897,
        GIR_Done,
      // Label 2473: @162261
      GIM_Try, /*On fail goto*//*Label 2474*/ GIMT_Encode4(162317), // Rule ID 6899 //
        GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasGDS),
        GIM_CheckMemoryAddressSpace, /*MI*/0, /*MMO*/0, /*NumAddrSpace*/1, /*AddrSpace*/2,
        GIM_CheckHasNoUse, /*MI*/0,
        GIM_CheckPointerToAny, /*MI*/0, /*Op*/1, /*SizeInBits*/0,
        GIM_CheckComplexPattern, /*MI*/0, /*Op*/1, /*Renderer*/GIMT_Encode2(0), GIMT_Encode2(GICP_gi_ds_1addr_1offset),
        // (atomic_load_add_glue:{ *:[i32] } (DS1Addr1Offset:{ *:[iPTR] } i32:{ *:[i32] }:$ptr, i32:{ *:[i32] }:$offset), i32:{ *:[i32] }:$value)<<P:Predicate_atomic_load_add_region_m0_noret_32>>  =>  (DS_ADD_U32 ?:{ *:[i32] }:$ptr, anonymous_15037:{ *:[i32] }:$value, offset:{ *:[i32] }:$offset, 1:{ *:[i1] })
        GIR_BuildMI, /*InsnID*/0, /*Opcode*/GIMT_Encode2(AMDGPU::DS_ADD_U32),
        GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/0, // ptr
        GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/2, // value
        GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/1, // offset
        GIR_AddImm8, /*InsnID*/0, /*Imm*/1,
        GIR_MergeMemOperands, /*InsnID*/0, /*NumInsns*/1, /*MergeInsnID's*/0,
        GIR_ConstrainSelectedInstOperands, /*InsnID*/0,
        GIR_EraseFromParent, /*InsnID*/0,
        // GIR_Coverage, 6899,
        GIR_Done,
      // Label 2474: @162317
      GIM_Try, /*On fail goto*//*Label 2475*/ GIMT_Encode4(162380), // Rule ID 6894 //
        GIM_CheckFeatures, GIMT_Encode2(GIFBS_LDSRequiresM0Init),
        GIM_CheckMemoryAddressSpace, /*MI*/0, /*MMO*/0, /*NumAddrSpace*/1, /*AddrSpace*/3,
        GIM_CheckRegBankForClass, /*MI*/0, /*Op*/0, /*RC*/GIMT_Encode2(AMDGPU::AV_32RegClassID),
        GIM_CheckPointerToAny, /*MI*/0, /*Op*/1, /*SizeInBits*/0,
        GIM_CheckComplexPattern, /*MI*/0, /*Op*/1, /*Renderer*/GIMT_Encode2(0), GIMT_Encode2(GICP_gi_ds_1addr_1offset),
        // (atomic_load_add_glue:{ *:[i32] } (DS1Addr1Offset:{ *:[iPTR] } i32:{ *:[i32] }:$ptr, i32:{ *:[i32] }:$offset), i32:{ *:[i32] }:$value)<<P:Predicate_atomic_load_add_local_m0_32>>  =>  (DS_ADD_RTN_U32:{ *:[i32] } ?:{ *:[i32] }:$ptr, anonymous_15037:{ *:[i32] }:$value, offset:{ *:[i32] }:$offset, 0:{ *:[i1] })
        GIR_BuildMI, /*InsnID*/0, /*Opcode*/GIMT_Encode2(AMDGPU::DS_ADD_RTN_U32),
        GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/0, // DstI[vdst]
        GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/0, // ptr
        GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/2, // value
        GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/1, // offset
        GIR_AddImm8, /*InsnID*/0, /*Imm*/0,
        GIR_MergeMemOperands, /*InsnID*/0, /*NumInsns*/1, /*MergeInsnID's*/0,
        GIR_ConstrainSelectedInstOperands, /*InsnID*/0,
        GIR_EraseFromParent, /*InsnID*/0,
        // GIR_Coverage, 6894,
        GIR_Done,
      // Label 2475: @162380
      GIM_Try, /*On fail goto*//*Label 2476*/ GIMT_Encode4(162443), // Rule ID 6896 //
        GIM_CheckFeatures, GIMT_Encode2(GIFBS_NotLDSRequiresM0Init),
        GIM_CheckMemoryAddressSpace, /*MI*/0, /*MMO*/0, /*NumAddrSpace*/1, /*AddrSpace*/3,
        GIM_CheckRegBankForClass, /*MI*/0, /*Op*/0, /*RC*/GIMT_Encode2(AMDGPU::AV_32RegClassID),
        GIM_CheckPointerToAny, /*MI*/0, /*Op*/1, /*SizeInBits*/0,
        GIM_CheckComplexPattern, /*MI*/0, /*Op*/1, /*Renderer*/GIMT_Encode2(0), GIMT_Encode2(GICP_gi_ds_1addr_1offset),
        // (atomic_load_add:{ *:[i32] } (DS1Addr1Offset:{ *:[iPTR] } i32:{ *:[i32] }:$ptr, i32:{ *:[i32] }:$offset), i32:{ *:[i32] }:$value)<<P:Predicate_atomic_load_add_local_32>>  =>  (DS_ADD_RTN_U32_gfx9:{ *:[i32] } ?:{ *:[i32] }:$ptr, anonymous_15037:{ *:[i32] }:$value, offset:{ *:[i32] }:$offset, 0:{ *:[i1] })
        GIR_BuildMI, /*InsnID*/0, /*Opcode*/GIMT_Encode2(AMDGPU::DS_ADD_RTN_U32_gfx9),
        GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/0, // DstI[vdst]
        GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/0, // ptr
        GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/2, // value
        GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/1, // offset
        GIR_AddImm8, /*InsnID*/0, /*Imm*/0,
        GIR_MergeMemOperands, /*InsnID*/0, /*NumInsns*/1, /*MergeInsnID's*/0,
        GIR_ConstrainSelectedInstOperands, /*InsnID*/0,
        GIR_EraseFromParent, /*InsnID*/0,
        // GIR_Coverage, 6896,
        GIR_Done,
      // Label 2476: @162443
      GIM_Try, /*On fail goto*//*Label 2477*/ GIMT_Encode4(162506), // Rule ID 6898 //
        GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasGDS),
        GIM_CheckMemoryAddressSpace, /*MI*/0, /*MMO*/0, /*NumAddrSpace*/1, /*AddrSpace*/2,
        GIM_CheckRegBankForClass, /*MI*/0, /*Op*/0, /*RC*/GIMT_Encode2(AMDGPU::AV_32RegClassID),
        GIM_CheckPointerToAny, /*MI*/0, /*Op*/1, /*SizeInBits*/0,
        GIM_CheckComplexPattern, /*MI*/0, /*Op*/1, /*Renderer*/GIMT_Encode2(0), GIMT_Encode2(GICP_gi_ds_1addr_1offset),
        // (atomic_load_add_glue:{ *:[i32] } (DS1Addr1Offset:{ *:[iPTR] } i32:{ *:[i32] }:$ptr, i32:{ *:[i32] }:$offset), i32:{ *:[i32] }:$value)<<P:Predicate_atomic_load_add_region_m0_32>>  =>  (DS_ADD_RTN_U32:{ *:[i32] } ?:{ *:[i32] }:$ptr, anonymous_15037:{ *:[i32] }:$value, offset:{ *:[i32] }:$offset, 1:{ *:[i1] })
        GIR_BuildMI, /*InsnID*/0, /*Opcode*/GIMT_Encode2(AMDGPU::DS_ADD_RTN_U32),
        GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/0, // DstI[vdst]
        GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/0, // ptr
        GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/2, // value
        GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/1, // offset
        GIR_AddImm8, /*InsnID*/0, /*Imm*/1,
        GIR_MergeMemOperands, /*InsnID*/0, /*NumInsns*/1, /*MergeInsnID's*/0,
        GIR_ConstrainSelectedInstOperands, /*InsnID*/0,
        GIR_EraseFromParent, /*InsnID*/0,
        // GIR_Coverage, 6898,
        GIR_Done,
      // Label 2477: @162506
      GIM_Try, /*On fail goto*//*Label 2478*/ GIMT_Encode4(162569), // Rule ID 2956 //
        GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasFlatGlobalInsts),
        GIM_CheckMemoryAddressSpace, /*MI*/0, /*MMO*/0, /*NumAddrSpace*/3, /*AddrSpace*/1, /*AddrSpace*/4, /*AddrSpace*/6,
        GIM_CheckHasNoUse, /*MI*/0,
        GIM_CheckPointerToAny, /*MI*/0, /*Op*/1, /*SizeInBits*/0,
        GIM_CheckComplexPattern, /*MI*/0, /*Op*/1, /*Renderer*/GIMT_Encode2(0), GIMT_Encode2(GICP_gi_global_saddr),
        // (atomic_load_add:{ *:[i32] } (GlobalSAddr:{ *:[iPTR] } SReg_64:{ *:[i64] }:$saddr, VGPR_32:{ *:[i32] }:$voffset, i32:{ *:[i32] }:$offset), i32:{ *:[i32] }:$data)<<P:Predicate_atomic_load_add_global_noret_32>>  =>  (GLOBAL_ATOMIC_ADD_SADDR ?:{ *:[i32] }:$voffset, anonymous_15037:{ *:[i32] }:$data, ?:{ *:[i64] }:$saddr, ?:{ *:[i32] }:$offset)
        GIR_BuildMI, /*InsnID*/0, /*Opcode*/GIMT_Encode2(AMDGPU::GLOBAL_ATOMIC_ADD_SADDR),
        GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/1, // voffset
        GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/2, // data
        GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/0, // saddr
        GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/2, // offset
        GIR_AddImm8, /*InsnID*/0, /*Imm*/0,
        GIR_MergeMemOperands, /*InsnID*/0, /*NumInsns*/1, /*MergeInsnID's*/0,
        GIR_ConstrainSelectedInstOperands, /*InsnID*/0,
        GIR_EraseFromParent, /*InsnID*/0,
        // GIR_Coverage, 2956,
        GIR_Done,
      // Label 2478: @162569
      GIM_Try, /*On fail goto*//*Label 2479*/ GIMT_Encode4(162639), // Rule ID 2958 //
        GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasFlatGlobalInsts),
        GIM_CheckMemoryAddressSpace, /*MI*/0, /*MMO*/0, /*NumAddrSpace*/3, /*AddrSpace*/1, /*AddrSpace*/4, /*AddrSpace*/6,
        GIM_CheckRegBankForClass, /*MI*/0, /*Op*/0, /*RC*/GIMT_Encode2(AMDGPU::AV_32RegClassID),
        GIM_CheckPointerToAny, /*MI*/0, /*Op*/1, /*SizeInBits*/0,
        GIM_CheckComplexPattern, /*MI*/0, /*Op*/1, /*Renderer*/GIMT_Encode2(0), GIMT_Encode2(GICP_gi_global_saddr),
        // (atomic_load_add:{ *:[i32] } (GlobalSAddr:{ *:[iPTR] } SReg_64:{ *:[i64] }:$saddr, VGPR_32:{ *:[i32] }:$voffset, i32:{ *:[i32] }:$offset), i32:{ *:[i32] }:$data)<<P:Predicate_atomic_load_add_global_32>>  =>  (GLOBAL_ATOMIC_ADD_SADDR_RTN:{ *:[i32] } ?:{ *:[i32] }:$voffset, anonymous_15037:{ *:[i32] }:$data, ?:{ *:[i64] }:$saddr, ?:{ *:[i32] }:$offset)
        GIR_BuildMI, /*InsnID*/0, /*Opcode*/GIMT_Encode2(AMDGPU::GLOBAL_ATOMIC_ADD_SADDR_RTN),
        GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/0, // DstI[vdst]
        GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/1, // voffset
        GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/2, // data
        GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/0, // saddr
        GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/2, // offset
        GIR_AddImm8, /*InsnID*/0, /*Imm*/1,
        GIR_MergeMemOperands, /*InsnID*/0, /*NumInsns*/1, /*MergeInsnID's*/0,
        GIR_ConstrainSelectedInstOperands, /*InsnID*/0,
        GIR_EraseFromParent, /*InsnID*/0,
        // GIR_Coverage, 2958,
        GIR_Done,
      // Label 2479: @162639
      GIM_Try, /*On fail goto*//*Label 2480*/ GIMT_Encode4(162697), // Rule ID 2955 //
        GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasFlatGlobalInsts),
        GIM_CheckMemoryAddressSpace, /*MI*/0, /*MMO*/0, /*NumAddrSpace*/3, /*AddrSpace*/1, /*AddrSpace*/4, /*AddrSpace*/6,
        GIM_CheckHasNoUse, /*MI*/0,
        GIM_CheckPointerToAny, /*MI*/0, /*Op*/1, /*SizeInBits*/0,
        GIM_CheckComplexPattern, /*MI*/0, /*Op*/1, /*Renderer*/GIMT_Encode2(0), GIMT_Encode2(GICP_gi_global_offset),
        // (atomic_load_add:{ *:[i32] } (GlobalOffset:{ *:[iPTR] } i64:{ *:[i64] }:$vaddr, i32:{ *:[i32] }:$offset), i32:{ *:[i32] }:$data)<<P:Predicate_atomic_load_add_global_noret_32>>  =>  (GLOBAL_ATOMIC_ADD VReg_64:{ *:[i64] }:$vaddr, anonymous_15037:{ *:[i32] }:$data, ?:{ *:[i32] }:$offset)
        GIR_BuildMI, /*InsnID*/0, /*Opcode*/GIMT_Encode2(AMDGPU::GLOBAL_ATOMIC_ADD),
        GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/0, // vaddr
        GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/2, // data
        GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/1, // offset
        GIR_AddImm8, /*InsnID*/0, /*Imm*/0,
        GIR_MergeMemOperands, /*InsnID*/0, /*NumInsns*/1, /*MergeInsnID's*/0,
        GIR_ConstrainSelectedInstOperands, /*InsnID*/0,
        GIR_EraseFromParent, /*InsnID*/0,
        // GIR_Coverage, 2955,
        GIR_Done,
      // Label 2480: @162697
      GIM_Try, /*On fail goto*//*Label 2481*/ GIMT_Encode4(162762), // Rule ID 2957 //
        GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasFlatGlobalInsts),
        GIM_CheckMemoryAddressSpace, /*MI*/0, /*MMO*/0, /*NumAddrSpace*/3, /*AddrSpace*/1, /*AddrSpace*/4, /*AddrSpace*/6,
        GIM_CheckRegBankForClass, /*MI*/0, /*Op*/0, /*RC*/GIMT_Encode2(AMDGPU::AV_32RegClassID),
        GIM_CheckPointerToAny, /*MI*/0, /*Op*/1, /*SizeInBits*/0,
        GIM_CheckComplexPattern, /*MI*/0, /*Op*/1, /*Renderer*/GIMT_Encode2(0), GIMT_Encode2(GICP_gi_global_offset),
        // (atomic_load_add:{ *:[i32] } (GlobalOffset:{ *:[iPTR] } i64:{ *:[i64] }:$vaddr, i32:{ *:[i32] }:$offset), i32:{ *:[i32] }:$data)<<P:Predicate_atomic_load_add_global_32>>  =>  (GLOBAL_ATOMIC_ADD_RTN:{ *:[i32] } VReg_64:{ *:[i64] }:$vaddr, anonymous_15037:{ *:[i32] }:$data, ?:{ *:[i32] }:$offset)
        GIR_BuildMI, /*InsnID*/0, /*Opcode*/GIMT_Encode2(AMDGPU::GLOBAL_ATOMIC_ADD_RTN),
        GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/0, // DstI[vdst]
        GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/0, // vaddr
        GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/2, // data
        GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/1, // offset
        GIR_AddImm8, /*InsnID*/0, /*Imm*/1,
        GIR_MergeMemOperands, /*InsnID*/0, /*NumInsns*/1, /*MergeInsnID's*/0,
        GIR_ConstrainSelectedInstOperands, /*InsnID*/0,
        GIR_EraseFromParent, /*InsnID*/0,
        // GIR_Coverage, 2957,
        GIR_Done,
      // Label 2481: @162762
      GIM_Try, /*On fail goto*//*Label 2482*/ GIMT_Encode4(162821), // Rule ID 2745 //
        GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasFlatAddressSpace),
        GIM_CheckMemoryAddressSpace, /*MI*/0, /*MMO*/0, /*NumAddrSpace*/4, /*AddrSpace*/0, /*AddrSpace*/1, /*AddrSpace*/4, /*AddrSpace*/6,
        GIM_CheckHasNoUse, /*MI*/0,
        GIM_CheckPointerToAny, /*MI*/0, /*Op*/1, /*SizeInBits*/0,
        GIM_CheckComplexPattern, /*MI*/0, /*Op*/1, /*Renderer*/GIMT_Encode2(0), GIMT_Encode2(GICP_gi_flat_offset),
        // (atomic_load_add:{ *:[i32] } (FlatOffset:{ *:[iPTR] } i64:{ *:[i64] }:$vaddr, i32:{ *:[i32] }:$offset), i32:{ *:[i32] }:$data)<<P:Predicate_atomic_load_add_flat_noret_32>>  =>  (FLAT_ATOMIC_ADD VReg_64:{ *:[i64] }:$vaddr, anonymous_15037:{ *:[i32] }:$data, ?:{ *:[i32] }:$offset)
        GIR_BuildMI, /*InsnID*/0, /*Opcode*/GIMT_Encode2(AMDGPU::FLAT_ATOMIC_ADD),
        GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/0, // vaddr
        GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/2, // data
        GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/1, // offset
        GIR_AddImm8, /*InsnID*/0, /*Imm*/0,
        GIR_MergeMemOperands, /*InsnID*/0, /*NumInsns*/1, /*MergeInsnID's*/0,
        GIR_ConstrainSelectedInstOperands, /*InsnID*/0,
        GIR_EraseFromParent, /*InsnID*/0,
        // GIR_Coverage, 2745,
        GIR_Done,
      // Label 2482: @162821
      GIM_Try, /*On fail goto*//*Label 2483*/ GIMT_Encode4(162879), // Rule ID 2880 //
        GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasFlatAddressSpace),
        GIM_CheckMemoryAddressSpace, /*MI*/0, /*MMO*/0, /*NumAddrSpace*/3, /*AddrSpace*/1, /*AddrSpace*/4, /*AddrSpace*/6,
        GIM_CheckHasNoUse, /*MI*/0,
        GIM_CheckPointerToAny, /*MI*/0, /*Op*/1, /*SizeInBits*/0,
        GIM_CheckComplexPattern, /*MI*/0, /*Op*/1, /*Renderer*/GIMT_Encode2(0), GIMT_Encode2(GICP_gi_flat_offset),
        // (atomic_load_add:{ *:[i32] } (FlatOffset:{ *:[iPTR] } i64:{ *:[i64] }:$vaddr, i32:{ *:[i32] }:$offset), i32:{ *:[i32] }:$data)<<P:Predicate_atomic_load_add_global_noret_32>>  =>  (FLAT_ATOMIC_ADD VReg_64:{ *:[i64] }:$vaddr, anonymous_15037:{ *:[i32] }:$data, ?:{ *:[i32] }:$offset)
        GIR_BuildMI, /*InsnID*/0, /*Opcode*/GIMT_Encode2(AMDGPU::FLAT_ATOMIC_ADD),
        GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/0, // vaddr
        GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/2, // data
        GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/1, // offset
        GIR_AddImm8, /*InsnID*/0, /*Imm*/0,
        GIR_MergeMemOperands, /*InsnID*/0, /*NumInsns*/1, /*MergeInsnID's*/0,
        GIR_ConstrainSelectedInstOperands, /*InsnID*/0,
        GIR_EraseFromParent, /*InsnID*/0,
        // GIR_Coverage, 2880,
        GIR_Done,
      // Label 2483: @162879
      GIM_Try, /*On fail goto*//*Label 2484*/ GIMT_Encode4(162945), // Rule ID 2746 //
        GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasFlatAddressSpace),
        GIM_CheckMemoryAddressSpace, /*MI*/0, /*MMO*/0, /*NumAddrSpace*/4, /*AddrSpace*/0, /*AddrSpace*/1, /*AddrSpace*/4, /*AddrSpace*/6,
        GIM_CheckRegBankForClass, /*MI*/0, /*Op*/0, /*RC*/GIMT_Encode2(AMDGPU::AV_32RegClassID),
        GIM_CheckPointerToAny, /*MI*/0, /*Op*/1, /*SizeInBits*/0,
        GIM_CheckComplexPattern, /*MI*/0, /*Op*/1, /*Renderer*/GIMT_Encode2(0), GIMT_Encode2(GICP_gi_flat_offset),
        // (atomic_load_add:{ *:[i32] } (FlatOffset:{ *:[iPTR] } i64:{ *:[i64] }:$vaddr, i32:{ *:[i32] }:$offset), i32:{ *:[i32] }:$data)<<P:Predicate_atomic_load_add_flat_32>>  =>  (FLAT_ATOMIC_ADD_RTN:{ *:[i32] } VReg_64:{ *:[i64] }:$vaddr, anonymous_15037:{ *:[i32] }:$data, ?:{ *:[i32] }:$offset)
        GIR_BuildMI, /*InsnID*/0, /*Opcode*/GIMT_Encode2(AMDGPU::FLAT_ATOMIC_ADD_RTN),
        GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/0, // DstI[vdst]
        GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/0, // vaddr
        GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/2, // data
        GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/1, // offset
        GIR_AddImm8, /*InsnID*/0, /*Imm*/1,
        GIR_MergeMemOperands, /*InsnID*/0, /*NumInsns*/1, /*MergeInsnID's*/0,
        GIR_ConstrainSelectedInstOperands, /*InsnID*/0,
        GIR_EraseFromParent, /*InsnID*/0,
        // GIR_Coverage, 2746,
        GIR_Done,
      // Label 2484: @162945
      GIM_Try, /*On fail goto*//*Label 2485*/ GIMT_Encode4(163010), // Rule ID 2879 //
        GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasFlatAddressSpace),
        GIM_CheckMemoryAddressSpace, /*MI*/0, /*MMO*/0, /*NumAddrSpace*/3, /*AddrSpace*/1, /*AddrSpace*/4, /*AddrSpace*/6,
        GIM_CheckRegBankForClass, /*MI*/0, /*Op*/0, /*RC*/GIMT_Encode2(AMDGPU::AV_32RegClassID),
        GIM_CheckPointerToAny, /*MI*/0, /*Op*/1, /*SizeInBits*/0,
        GIM_CheckComplexPattern, /*MI*/0, /*Op*/1, /*Renderer*/GIMT_Encode2(0), GIMT_Encode2(GICP_gi_flat_offset),
        // (atomic_load_add:{ *:[i32] } (FlatOffset:{ *:[iPTR] } i64:{ *:[i64] }:$vaddr, i32:{ *:[i32] }:$offset), i32:{ *:[i32] }:$data)<<P:Predicate_atomic_load_add_global_32>>  =>  (FLAT_ATOMIC_ADD_RTN:{ *:[i32] } VReg_64:{ *:[i64] }:$vaddr, anonymous_15037:{ *:[i32] }:$data, ?:{ *:[i32] }:$offset)
        GIR_BuildMI, /*InsnID*/0, /*Opcode*/GIMT_Encode2(AMDGPU::FLAT_ATOMIC_ADD_RTN),
        GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/0, // DstI[vdst]
        GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/0, // vaddr
        GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/2, // data
        GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/1, // offset
        GIR_AddImm8, /*InsnID*/0, /*Imm*/1,
        GIR_MergeMemOperands, /*InsnID*/0, /*NumInsns*/1, /*MergeInsnID's*/0,
        GIR_ConstrainSelectedInstOperands, /*InsnID*/0,
        GIR_EraseFromParent, /*InsnID*/0,
        // GIR_Coverage, 2879,
        GIR_Done,
      // Label 2485: @163010
      GIM_Reject,
    // Label 2463: @163011
    GIM_Reject,
    // Label 2461: @163012
    GIM_Try, /*On fail goto*//*Label 2486*/ GIMT_Encode4(164423),
      GIM_CheckType, /*MI*/0, /*Op*/2, /*Type*/GILLT_s64,
      GIM_Try, /*On fail goto*//*Label 2487*/ GIMT_Encode4(163089), // Rule ID 4614 //
        GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasUnrestrictedSOffset),
        GIM_CheckMemoryAddressSpace, /*MI*/0, /*MMO*/0, /*NumAddrSpace*/3, /*AddrSpace*/1, /*AddrSpace*/4, /*AddrSpace*/6,
        GIM_CheckHasNoUse, /*MI*/0,
        GIM_CheckPointerToAny, /*MI*/0, /*Op*/1, /*SizeInBits*/0,
        GIM_CheckComplexPattern, /*MI*/0, /*Op*/1, /*Renderer*/GIMT_Encode2(0), GIMT_Encode2(GICP_gi_mubuf_addr64),
        // (atomic_load_add:{ *:[i64] } (MUBUFAddr64:{ *:[iPTR] } v4i32:{ *:[v4i32] }:$srsrc, i64:{ *:[i64] }:$vaddr, i32:{ *:[i32] }:$soffset, i32:{ *:[i32] }:$offset), i64:{ *:[i64] }:$vdata_in)<<P:Predicate_atomic_load_add_global_noret_64>>  =>  (BUFFER_ATOMIC_ADD_X2_ADDR64 anonymous_15036:{ *:[i64] }:$vdata_in, VReg_64:{ *:[i64] }:$vaddr, SReg_128:{ *:[v4i32] }:$srsrc, SCSrc_b32:{ *:[i32] }:$soffset, offset:{ *:[i32] }:$offset)
        GIR_BuildMI, /*InsnID*/0, /*Opcode*/GIMT_Encode2(AMDGPU::BUFFER_ATOMIC_ADD_X2_ADDR64),
        GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/2, // vdata_in
        GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/1, // vaddr
        GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/0, // srsrc
        GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/2, // soffset
        GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/3, // offset
        GIR_AddImm8, /*InsnID*/0, /*Imm*/0,
        GIR_MergeMemOperands, /*InsnID*/0, /*NumInsns*/1, /*MergeInsnID's*/0,
        GIR_ConstrainSelectedInstOperands, /*InsnID*/0,
        GIR_EraseFromParent, /*InsnID*/0,
        // GIR_Coverage, 4614,
        GIR_Done,
      // Label 2487: @163089
      GIM_Try, /*On fail goto*//*Label 2488*/ GIMT_Encode4(163154), // Rule ID 4618 //
        GIM_CheckMemoryAddressSpace, /*MI*/0, /*MMO*/0, /*NumAddrSpace*/3, /*AddrSpace*/1, /*AddrSpace*/4, /*AddrSpace*/6,
        GIM_CheckHasNoUse, /*MI*/0,
        GIM_CheckPointerToAny, /*MI*/0, /*Op*/1, /*SizeInBits*/0,
        GIM_CheckComplexPattern, /*MI*/0, /*Op*/1, /*Renderer*/GIMT_Encode2(0), GIMT_Encode2(GICP_gi_mubuf_addr64),
        // (atomic_load_add:{ *:[i64] } (MUBUFAddr64:{ *:[iPTR] } v4i32:{ *:[v4i32] }:$srsrc, i64:{ *:[i64] }:$vaddr, i32:{ *:[i32] }:$soffset, i32:{ *:[i32] }:$offset), i64:{ *:[i64] }:$vdata_in)<<P:Predicate_atomic_load_add_global_noret_64>>  =>  (BUFFER_ATOMIC_ADD_X2_VBUFFER_ADDR64 anonymous_15036:{ *:[i64] }:$vdata_in, VReg_64:{ *:[i64] }:$vaddr, SReg_128:{ *:[v4i32] }:$srsrc, SCSrc_b32:{ *:[i32] }:$soffset, offset:{ *:[i32] }:$offset)
        GIR_BuildMI, /*InsnID*/0, /*Opcode*/GIMT_Encode2(AMDGPU::BUFFER_ATOMIC_ADD_X2_VBUFFER_ADDR64),
        GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/2, // vdata_in
        GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/1, // vaddr
        GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/0, // srsrc
        GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/2, // soffset
        GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/3, // offset
        GIR_AddImm8, /*InsnID*/0, /*Imm*/0,
        GIR_MergeMemOperands, /*InsnID*/0, /*NumInsns*/1, /*MergeInsnID's*/0,
        GIR_ConstrainSelectedInstOperands, /*InsnID*/0,
        GIR_EraseFromParent, /*InsnID*/0,
        // GIR_Coverage, 4618,
        GIR_Done,
      // Label 2488: @163154
      GIM_Try, /*On fail goto*//*Label 2489*/ GIMT_Encode4(163229), // Rule ID 4612 //
        GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasUnrestrictedSOffset),
        GIM_CheckMemoryAddressSpace, /*MI*/0, /*MMO*/0, /*NumAddrSpace*/3, /*AddrSpace*/1, /*AddrSpace*/4, /*AddrSpace*/6,
        GIM_CheckRegBankForClass, /*MI*/0, /*Op*/0, /*RC*/GIMT_Encode2(AMDGPU::AV_64RegClassID),
        GIM_CheckPointerToAny, /*MI*/0, /*Op*/1, /*SizeInBits*/0,
        GIM_CheckComplexPattern, /*MI*/0, /*Op*/1, /*Renderer*/GIMT_Encode2(0), GIMT_Encode2(GICP_gi_mubuf_addr64),
        // (atomic_load_add:{ *:[i64] } (MUBUFAddr64:{ *:[iPTR] } v4i32:{ *:[v4i32] }:$srsrc, i64:{ *:[i64] }:$vaddr, i32:{ *:[i32] }:$soffset, i32:{ *:[i32] }:$offset), i64:{ *:[i64] }:$vdata_in)<<P:Predicate_atomic_load_add_global_64>>  =>  (BUFFER_ATOMIC_ADD_X2_ADDR64_RTN:{ *:[i64] } anonymous_15036:{ *:[i64] }:$vdata_in, VReg_64:{ *:[i64] }:$vaddr, SReg_128:{ *:[v4i32] }:$srsrc, SCSrc_b32:{ *:[i32] }:$soffset, offset:{ *:[i32] }:$offset)
        GIR_BuildMI, /*InsnID*/0, /*Opcode*/GIMT_Encode2(AMDGPU::BUFFER_ATOMIC_ADD_X2_ADDR64_RTN),
        GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/0, // DstI[vdata]
        GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/2, // vdata_in
        GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/1, // vaddr
        GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/0, // srsrc
        GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/2, // soffset
        GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/3, // offset
        GIR_AddImm8, /*InsnID*/0, /*Imm*/1,
        GIR_MergeMemOperands, /*InsnID*/0, /*NumInsns*/1, /*MergeInsnID's*/0,
        GIR_ConstrainSelectedInstOperands, /*InsnID*/0,
        GIR_EraseFromParent, /*InsnID*/0,
        // GIR_Coverage, 4612,
        GIR_Done,
      // Label 2489: @163229
      GIM_Try, /*On fail goto*//*Label 2490*/ GIMT_Encode4(163301), // Rule ID 4616 //
        GIM_CheckMemoryAddressSpace, /*MI*/0, /*MMO*/0, /*NumAddrSpace*/3, /*AddrSpace*/1, /*AddrSpace*/4, /*AddrSpace*/6,
        GIM_CheckRegBankForClass, /*MI*/0, /*Op*/0, /*RC*/GIMT_Encode2(AMDGPU::AV_64RegClassID),
        GIM_CheckPointerToAny, /*MI*/0, /*Op*/1, /*SizeInBits*/0,
        GIM_CheckComplexPattern, /*MI*/0, /*Op*/1, /*Renderer*/GIMT_Encode2(0), GIMT_Encode2(GICP_gi_mubuf_addr64),
        // (atomic_load_add:{ *:[i64] } (MUBUFAddr64:{ *:[iPTR] } v4i32:{ *:[v4i32] }:$srsrc, i64:{ *:[i64] }:$vaddr, i32:{ *:[i32] }:$soffset, i32:{ *:[i32] }:$offset), i64:{ *:[i64] }:$vdata_in)<<P:Predicate_atomic_load_add_global_64>>  =>  (BUFFER_ATOMIC_ADD_X2_VBUFFER_ADDR64_RTN:{ *:[i64] } anonymous_15036:{ *:[i64] }:$vdata_in, VReg_64:{ *:[i64] }:$vaddr, SReg_128:{ *:[v4i32] }:$srsrc, SCSrc_b32:{ *:[i32] }:$soffset, offset:{ *:[i32] }:$offset)
        GIR_BuildMI, /*InsnID*/0, /*Opcode*/GIMT_Encode2(AMDGPU::BUFFER_ATOMIC_ADD_X2_VBUFFER_ADDR64_RTN),
        GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/0, // DstI[vdata]
        GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/2, // vdata_in
        GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/1, // vaddr
        GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/0, // srsrc
        GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/2, // soffset
        GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/3, // offset
        GIR_AddImm8, /*InsnID*/0, /*Imm*/1,
        GIR_MergeMemOperands, /*InsnID*/0, /*NumInsns*/1, /*MergeInsnID's*/0,
        GIR_ConstrainSelectedInstOperands, /*InsnID*/0,
        GIR_EraseFromParent, /*InsnID*/0,
        // GIR_Coverage, 4616,
        GIR_Done,
      // Label 2490: @163301
      GIM_Try, /*On fail goto*//*Label 2491*/ GIMT_Encode4(163364), // Rule ID 4613 //
        GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasUnrestrictedSOffset),
        GIM_CheckMemoryAddressSpace, /*MI*/0, /*MMO*/0, /*NumAddrSpace*/3, /*AddrSpace*/1, /*AddrSpace*/4, /*AddrSpace*/6,
        GIM_CheckHasNoUse, /*MI*/0,
        GIM_CheckPointerToAny, /*MI*/0, /*Op*/1, /*SizeInBits*/0,
        GIM_CheckComplexPattern, /*MI*/0, /*Op*/1, /*Renderer*/GIMT_Encode2(0), GIMT_Encode2(GICP_gi_mubuf_offset),
        // (atomic_load_add:{ *:[i64] } (MUBUFOffset:{ *:[iPTR] } v4i32:{ *:[v4i32] }:$srsrc, i32:{ *:[i32] }:$soffset, i32:{ *:[i32] }:$offset), i64:{ *:[i64] }:$vdata_in)<<P:Predicate_atomic_load_add_global_noret_64>>  =>  (BUFFER_ATOMIC_ADD_X2_OFFSET anonymous_15036:{ *:[i64] }:$vdata_in, SReg_128:{ *:[v4i32] }:$srsrc, SCSrc_b32:{ *:[i32] }:$soffset, offset:{ *:[i32] }:$offset)
        GIR_BuildMI, /*InsnID*/0, /*Opcode*/GIMT_Encode2(AMDGPU::BUFFER_ATOMIC_ADD_X2_OFFSET),
        GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/2, // vdata_in
        GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/0, // srsrc
        GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/1, // soffset
        GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/2, // offset
        GIR_AddImm8, /*InsnID*/0, /*Imm*/0,
        GIR_MergeMemOperands, /*InsnID*/0, /*NumInsns*/1, /*MergeInsnID's*/0,
        GIR_ConstrainSelectedInstOperands, /*InsnID*/0,
        GIR_EraseFromParent, /*InsnID*/0,
        // GIR_Coverage, 4613,
        GIR_Done,
      // Label 2491: @163364
      GIM_Try, /*On fail goto*//*Label 2492*/ GIMT_Encode4(163424), // Rule ID 4617 //
        GIM_CheckMemoryAddressSpace, /*MI*/0, /*MMO*/0, /*NumAddrSpace*/3, /*AddrSpace*/1, /*AddrSpace*/4, /*AddrSpace*/6,
        GIM_CheckHasNoUse, /*MI*/0,
        GIM_CheckPointerToAny, /*MI*/0, /*Op*/1, /*SizeInBits*/0,
        GIM_CheckComplexPattern, /*MI*/0, /*Op*/1, /*Renderer*/GIMT_Encode2(0), GIMT_Encode2(GICP_gi_mubuf_offset),
        // (atomic_load_add:{ *:[i64] } (MUBUFOffset:{ *:[iPTR] } v4i32:{ *:[v4i32] }:$srsrc, i32:{ *:[i32] }:$soffset, i32:{ *:[i32] }:$offset), i64:{ *:[i64] }:$vdata_in)<<P:Predicate_atomic_load_add_global_noret_64>>  =>  (BUFFER_ATOMIC_ADD_X2_VBUFFER_OFFSET anonymous_15036:{ *:[i64] }:$vdata_in, SReg_128:{ *:[v4i32] }:$srsrc, SCSrc_b32:{ *:[i32] }:$soffset, offset:{ *:[i32] }:$offset)
        GIR_BuildMI, /*InsnID*/0, /*Opcode*/GIMT_Encode2(AMDGPU::BUFFER_ATOMIC_ADD_X2_VBUFFER_OFFSET),
        GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/2, // vdata_in
        GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/0, // srsrc
        GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/1, // soffset
        GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/2, // offset
        GIR_AddImm8, /*InsnID*/0, /*Imm*/0,
        GIR_MergeMemOperands, /*InsnID*/0, /*NumInsns*/1, /*MergeInsnID's*/0,
        GIR_ConstrainSelectedInstOperands, /*InsnID*/0,
        GIR_EraseFromParent, /*InsnID*/0,
        // GIR_Coverage, 4617,
        GIR_Done,
      // Label 2492: @163424
      GIM_Try, /*On fail goto*//*Label 2493*/ GIMT_Encode4(163494), // Rule ID 4611 //
        GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasUnrestrictedSOffset),
        GIM_CheckMemoryAddressSpace, /*MI*/0, /*MMO*/0, /*NumAddrSpace*/3, /*AddrSpace*/1, /*AddrSpace*/4, /*AddrSpace*/6,
        GIM_CheckRegBankForClass, /*MI*/0, /*Op*/0, /*RC*/GIMT_Encode2(AMDGPU::AV_64RegClassID),
        GIM_CheckPointerToAny, /*MI*/0, /*Op*/1, /*SizeInBits*/0,
        GIM_CheckComplexPattern, /*MI*/0, /*Op*/1, /*Renderer*/GIMT_Encode2(0), GIMT_Encode2(GICP_gi_mubuf_offset),
        // (atomic_load_add:{ *:[i64] } (MUBUFOffset:{ *:[iPTR] } v4i32:{ *:[v4i32] }:$srsrc, i32:{ *:[i32] }:$soffset, i32:{ *:[i32] }:$offset), i64:{ *:[i64] }:$vdata_in)<<P:Predicate_atomic_load_add_global_64>>  =>  (BUFFER_ATOMIC_ADD_X2_OFFSET_RTN:{ *:[i64] } anonymous_15036:{ *:[i64] }:$vdata_in, SReg_128:{ *:[v4i32] }:$srsrc, SCSrc_b32:{ *:[i32] }:$soffset, offset:{ *:[i32] }:$offset)
        GIR_BuildMI, /*InsnID*/0, /*Opcode*/GIMT_Encode2(AMDGPU::BUFFER_ATOMIC_ADD_X2_OFFSET_RTN),
        GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/0, // DstI[vdata]
        GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/2, // vdata_in
        GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/0, // srsrc
        GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/1, // soffset
        GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/2, // offset
        GIR_AddImm8, /*InsnID*/0, /*Imm*/1,
        GIR_MergeMemOperands, /*InsnID*/0, /*NumInsns*/1, /*MergeInsnID's*/0,
        GIR_ConstrainSelectedInstOperands, /*InsnID*/0,
        GIR_EraseFromParent, /*InsnID*/0,
        // GIR_Coverage, 4611,
        GIR_Done,
      // Label 2493: @163494
      GIM_Try, /*On fail goto*//*Label 2494*/ GIMT_Encode4(163561), // Rule ID 4615 //
        GIM_CheckMemoryAddressSpace, /*MI*/0, /*MMO*/0, /*NumAddrSpace*/3, /*AddrSpace*/1, /*AddrSpace*/4, /*AddrSpace*/6,
        GIM_CheckRegBankForClass, /*MI*/0, /*Op*/0, /*RC*/GIMT_Encode2(AMDGPU::AV_64RegClassID),
        GIM_CheckPointerToAny, /*MI*/0, /*Op*/1, /*SizeInBits*/0,
        GIM_CheckComplexPattern, /*MI*/0, /*Op*/1, /*Renderer*/GIMT_Encode2(0), GIMT_Encode2(GICP_gi_mubuf_offset),
        // (atomic_load_add:{ *:[i64] } (MUBUFOffset:{ *:[iPTR] } v4i32:{ *:[v4i32] }:$srsrc, i32:{ *:[i32] }:$soffset, i32:{ *:[i32] }:$offset), i64:{ *:[i64] }:$vdata_in)<<P:Predicate_atomic_load_add_global_64>>  =>  (BUFFER_ATOMIC_ADD_X2_VBUFFER_OFFSET_RTN:{ *:[i64] } anonymous_15036:{ *:[i64] }:$vdata_in, SReg_128:{ *:[v4i32] }:$srsrc, SCSrc_b32:{ *:[i32] }:$soffset, offset:{ *:[i32] }:$offset)
        GIR_BuildMI, /*InsnID*/0, /*Opcode*/GIMT_Encode2(AMDGPU::BUFFER_ATOMIC_ADD_X2_VBUFFER_OFFSET_RTN),
        GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/0, // DstI[vdata]
        GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/2, // vdata_in
        GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/0, // srsrc
        GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/1, // soffset
        GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/2, // offset
        GIR_AddImm8, /*InsnID*/0, /*Imm*/1,
        GIR_MergeMemOperands, /*InsnID*/0, /*NumInsns*/1, /*MergeInsnID's*/0,
        GIR_ConstrainSelectedInstOperands, /*InsnID*/0,
        GIR_EraseFromParent, /*InsnID*/0,
        // GIR_Coverage, 4615,
        GIR_Done,
      // Label 2494: @163561
      GIM_Try, /*On fail goto*//*Label 2495*/ GIMT_Encode4(163617), // Rule ID 6992 //
        GIM_CheckFeatures, GIMT_Encode2(GIFBS_LDSRequiresM0Init),
        GIM_CheckMemoryAddressSpace, /*MI*/0, /*MMO*/0, /*NumAddrSpace*/1, /*AddrSpace*/3,
        GIM_CheckHasNoUse, /*MI*/0,
        GIM_CheckPointerToAny, /*MI*/0, /*Op*/1, /*SizeInBits*/0,
        GIM_CheckComplexPattern, /*MI*/0, /*Op*/1, /*Renderer*/GIMT_Encode2(0), GIMT_Encode2(GICP_gi_ds_1addr_1offset),
        // (atomic_load_add_glue:{ *:[i64] } (DS1Addr1Offset:{ *:[iPTR] } i32:{ *:[i32] }:$ptr, i32:{ *:[i32] }:$offset), i64:{ *:[i64] }:$value)<<P:Predicate_atomic_load_add_local_m0_noret_64>>  =>  (DS_ADD_U64 ?:{ *:[i32] }:$ptr, anonymous_15036:{ *:[i64] }:$value, offset:{ *:[i32] }:$offset, 0:{ *:[i1] })
        GIR_BuildMI, /*InsnID*/0, /*Opcode*/GIMT_Encode2(AMDGPU::DS_ADD_U64),
        GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/0, // ptr
        GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/2, // value
        GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/1, // offset
        GIR_AddImm8, /*InsnID*/0, /*Imm*/0,
        GIR_MergeMemOperands, /*InsnID*/0, /*NumInsns*/1, /*MergeInsnID's*/0,
        GIR_ConstrainSelectedInstOperands, /*InsnID*/0,
        GIR_EraseFromParent, /*InsnID*/0,
        // GIR_Coverage, 6992,
        GIR_Done,
      // Label 2495: @163617
      GIM_Try, /*On fail goto*//*Label 2496*/ GIMT_Encode4(163673), // Rule ID 6994 //
        GIM_CheckFeatures, GIMT_Encode2(GIFBS_NotLDSRequiresM0Init),
        GIM_CheckMemoryAddressSpace, /*MI*/0, /*MMO*/0, /*NumAddrSpace*/1, /*AddrSpace*/3,
        GIM_CheckHasNoUse, /*MI*/0,
        GIM_CheckPointerToAny, /*MI*/0, /*Op*/1, /*SizeInBits*/0,
        GIM_CheckComplexPattern, /*MI*/0, /*Op*/1, /*Renderer*/GIMT_Encode2(0), GIMT_Encode2(GICP_gi_ds_1addr_1offset),
        // (atomic_load_add:{ *:[i64] } (DS1Addr1Offset:{ *:[iPTR] } i32:{ *:[i32] }:$ptr, i32:{ *:[i32] }:$offset), i64:{ *:[i64] }:$value)<<P:Predicate_atomic_load_add_local_noret_64>>  =>  (DS_ADD_U64_gfx9 ?:{ *:[i32] }:$ptr, anonymous_15036:{ *:[i64] }:$value, offset:{ *:[i32] }:$offset, 0:{ *:[i1] })
        GIR_BuildMI, /*InsnID*/0, /*Opcode*/GIMT_Encode2(AMDGPU::DS_ADD_U64_gfx9),
        GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/0, // ptr
        GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/2, // value
        GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/1, // offset
        GIR_AddImm8, /*InsnID*/0, /*Imm*/0,
        GIR_MergeMemOperands, /*InsnID*/0, /*NumInsns*/1, /*MergeInsnID's*/0,
        GIR_ConstrainSelectedInstOperands, /*InsnID*/0,
        GIR_EraseFromParent, /*InsnID*/0,
        // GIR_Coverage, 6994,
        GIR_Done,
      // Label 2496: @163673
      GIM_Try, /*On fail goto*//*Label 2497*/ GIMT_Encode4(163729), // Rule ID 6996 //
        GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasGDS),
        GIM_CheckMemoryAddressSpace, /*MI*/0, /*MMO*/0, /*NumAddrSpace*/1, /*AddrSpace*/2,
        GIM_CheckHasNoUse, /*MI*/0,
        GIM_CheckPointerToAny, /*MI*/0, /*Op*/1, /*SizeInBits*/0,
        GIM_CheckComplexPattern, /*MI*/0, /*Op*/1, /*Renderer*/GIMT_Encode2(0), GIMT_Encode2(GICP_gi_ds_1addr_1offset),
        // (atomic_load_add_glue:{ *:[i64] } (DS1Addr1Offset:{ *:[iPTR] } i32:{ *:[i32] }:$ptr, i32:{ *:[i32] }:$offset), i64:{ *:[i64] }:$value)<<P:Predicate_atomic_load_add_region_m0_noret_64>>  =>  (DS_ADD_U64 ?:{ *:[i32] }:$ptr, anonymous_15036:{ *:[i64] }:$value, offset:{ *:[i32] }:$offset, 1:{ *:[i1] })
        GIR_BuildMI, /*InsnID*/0, /*Opcode*/GIMT_Encode2(AMDGPU::DS_ADD_U64),
        GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/0, // ptr
        GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/2, // value
        GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/1, // offset
        GIR_AddImm8, /*InsnID*/0, /*Imm*/1,
        GIR_MergeMemOperands, /*InsnID*/0, /*NumInsns*/1, /*MergeInsnID's*/0,
        GIR_ConstrainSelectedInstOperands, /*InsnID*/0,
        GIR_EraseFromParent, /*InsnID*/0,
        // GIR_Coverage, 6996,
        GIR_Done,
      // Label 2497: @163729
      GIM_Try, /*On fail goto*//*Label 2498*/ GIMT_Encode4(163792), // Rule ID 6991 //
        GIM_CheckFeatures, GIMT_Encode2(GIFBS_LDSRequiresM0Init),
        GIM_CheckMemoryAddressSpace, /*MI*/0, /*MMO*/0, /*NumAddrSpace*/1, /*AddrSpace*/3,
        GIM_CheckRegBankForClass, /*MI*/0, /*Op*/0, /*RC*/GIMT_Encode2(AMDGPU::AV_64RegClassID),
        GIM_CheckPointerToAny, /*MI*/0, /*Op*/1, /*SizeInBits*/0,
        GIM_CheckComplexPattern, /*MI*/0, /*Op*/1, /*Renderer*/GIMT_Encode2(0), GIMT_Encode2(GICP_gi_ds_1addr_1offset),
        // (atomic_load_add_glue:{ *:[i64] } (DS1Addr1Offset:{ *:[iPTR] } i32:{ *:[i32] }:$ptr, i32:{ *:[i32] }:$offset), i64:{ *:[i64] }:$value)<<P:Predicate_atomic_load_add_local_m0_64>>  =>  (DS_ADD_RTN_U64:{ *:[i64] } ?:{ *:[i32] }:$ptr, anonymous_15036:{ *:[i64] }:$value, offset:{ *:[i32] }:$offset, 0:{ *:[i1] })
        GIR_BuildMI, /*InsnID*/0, /*Opcode*/GIMT_Encode2(AMDGPU::DS_ADD_RTN_U64),
        GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/0, // DstI[vdst]
        GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/0, // ptr
        GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/2, // value
        GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/1, // offset
        GIR_AddImm8, /*InsnID*/0, /*Imm*/0,
        GIR_MergeMemOperands, /*InsnID*/0, /*NumInsns*/1, /*MergeInsnID's*/0,
        GIR_ConstrainSelectedInstOperands, /*InsnID*/0,
        GIR_EraseFromParent, /*InsnID*/0,
        // GIR_Coverage, 6991,
        GIR_Done,
      // Label 2498: @163792
      GIM_Try, /*On fail goto*//*Label 2499*/ GIMT_Encode4(163855), // Rule ID 6993 //
        GIM_CheckFeatures, GIMT_Encode2(GIFBS_NotLDSRequiresM0Init),
        GIM_CheckMemoryAddressSpace, /*MI*/0, /*MMO*/0, /*NumAddrSpace*/1, /*AddrSpace*/3,
        GIM_CheckRegBankForClass, /*MI*/0, /*Op*/0, /*RC*/GIMT_Encode2(AMDGPU::AV_64RegClassID),
        GIM_CheckPointerToAny, /*MI*/0, /*Op*/1, /*SizeInBits*/0,
        GIM_CheckComplexPattern, /*MI*/0, /*Op*/1, /*Renderer*/GIMT_Encode2(0), GIMT_Encode2(GICP_gi_ds_1addr_1offset),
        // (atomic_load_add:{ *:[i64] } (DS1Addr1Offset:{ *:[iPTR] } i32:{ *:[i32] }:$ptr, i32:{ *:[i32] }:$offset), i64:{ *:[i64] }:$value)<<P:Predicate_atomic_load_add_local_64>>  =>  (DS_ADD_RTN_U64_gfx9:{ *:[i64] } ?:{ *:[i32] }:$ptr, anonymous_15036:{ *:[i64] }:$value, offset:{ *:[i32] }:$offset, 0:{ *:[i1] })
        GIR_BuildMI, /*InsnID*/0, /*Opcode*/GIMT_Encode2(AMDGPU::DS_ADD_RTN_U64_gfx9),
        GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/0, // DstI[vdst]
        GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/0, // ptr
        GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/2, // value
        GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/1, // offset
        GIR_AddImm8, /*InsnID*/0, /*Imm*/0,
        GIR_MergeMemOperands, /*InsnID*/0, /*NumInsns*/1, /*MergeInsnID's*/0,
        GIR_ConstrainSelectedInstOperands, /*InsnID*/0,
        GIR_EraseFromParent, /*InsnID*/0,
        // GIR_Coverage, 6993,
        GIR_Done,
      // Label 2499: @163855
      GIM_Try, /*On fail goto*//*Label 2500*/ GIMT_Encode4(163918), // Rule ID 6995 //
        GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasGDS),
        GIM_CheckMemoryAddressSpace, /*MI*/0, /*MMO*/0, /*NumAddrSpace*/1, /*AddrSpace*/2,
        GIM_CheckRegBankForClass, /*MI*/0, /*Op*/0, /*RC*/GIMT_Encode2(AMDGPU::AV_64RegClassID),
        GIM_CheckPointerToAny, /*MI*/0, /*Op*/1, /*SizeInBits*/0,
        GIM_CheckComplexPattern, /*MI*/0, /*Op*/1, /*Renderer*/GIMT_Encode2(0), GIMT_Encode2(GICP_gi_ds_1addr_1offset),
        // (atomic_load_add_glue:{ *:[i64] } (DS1Addr1Offset:{ *:[iPTR] } i32:{ *:[i32] }:$ptr, i32:{ *:[i32] }:$offset), i64:{ *:[i64] }:$value)<<P:Predicate_atomic_load_add_region_m0_64>>  =>  (DS_ADD_RTN_U64:{ *:[i64] } ?:{ *:[i32] }:$ptr, anonymous_15036:{ *:[i64] }:$value, offset:{ *:[i32] }:$offset, 1:{ *:[i1] })
        GIR_BuildMI, /*InsnID*/0, /*Opcode*/GIMT_Encode2(AMDGPU::DS_ADD_RTN_U64),
        GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/0, // DstI[vdst]
        GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/0, // ptr
        GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/2, // value
        GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/1, // offset
        GIR_AddImm8, /*InsnID*/0, /*Imm*/1,
        GIR_MergeMemOperands, /*InsnID*/0, /*NumInsns*/1, /*MergeInsnID's*/0,
        GIR_ConstrainSelectedInstOperands, /*InsnID*/0,
        GIR_EraseFromParent, /*InsnID*/0,
        // GIR_Coverage, 6995,
        GIR_Done,
      // Label 2500: @163918
      GIM_Try, /*On fail goto*//*Label 2501*/ GIMT_Encode4(163981), // Rule ID 3203 //
        GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasFlatGlobalInsts),
        GIM_CheckMemoryAddressSpace, /*MI*/0, /*MMO*/0, /*NumAddrSpace*/3, /*AddrSpace*/1, /*AddrSpace*/4, /*AddrSpace*/6,
        GIM_CheckHasNoUse, /*MI*/0,
        GIM_CheckPointerToAny, /*MI*/0, /*Op*/1, /*SizeInBits*/0,
        GIM_CheckComplexPattern, /*MI*/0, /*Op*/1, /*Renderer*/GIMT_Encode2(0), GIMT_Encode2(GICP_gi_global_saddr),
        // (atomic_load_add:{ *:[i64] } (GlobalSAddr:{ *:[iPTR] } SReg_64:{ *:[i64] }:$saddr, VGPR_32:{ *:[i32] }:$voffset, i32:{ *:[i32] }:$offset), i64:{ *:[i64] }:$data)<<P:Predicate_atomic_load_add_global_noret_64>>  =>  (GLOBAL_ATOMIC_ADD_X2_SADDR ?:{ *:[i32] }:$voffset, anonymous_15036:{ *:[i64] }:$data, ?:{ *:[i64] }:$saddr, ?:{ *:[i32] }:$offset)
        GIR_BuildMI, /*InsnID*/0, /*Opcode*/GIMT_Encode2(AMDGPU::GLOBAL_ATOMIC_ADD_X2_SADDR),
        GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/1, // voffset
        GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/2, // data
        GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/0, // saddr
        GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/2, // offset
        GIR_AddImm8, /*InsnID*/0, /*Imm*/0,
        GIR_MergeMemOperands, /*InsnID*/0, /*NumInsns*/1, /*MergeInsnID's*/0,
        GIR_ConstrainSelectedInstOperands, /*InsnID*/0,
        GIR_EraseFromParent, /*InsnID*/0,
        // GIR_Coverage, 3203,
        GIR_Done,
      // Label 2501: @163981
      GIM_Try, /*On fail goto*//*Label 2502*/ GIMT_Encode4(164051), // Rule ID 3205 //
        GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasFlatGlobalInsts),
        GIM_CheckMemoryAddressSpace, /*MI*/0, /*MMO*/0, /*NumAddrSpace*/3, /*AddrSpace*/1, /*AddrSpace*/4, /*AddrSpace*/6,
        GIM_CheckRegBankForClass, /*MI*/0, /*Op*/0, /*RC*/GIMT_Encode2(AMDGPU::AV_64RegClassID),
        GIM_CheckPointerToAny, /*MI*/0, /*Op*/1, /*SizeInBits*/0,
        GIM_CheckComplexPattern, /*MI*/0, /*Op*/1, /*Renderer*/GIMT_Encode2(0), GIMT_Encode2(GICP_gi_global_saddr),
        // (atomic_load_add:{ *:[i64] } (GlobalSAddr:{ *:[iPTR] } SReg_64:{ *:[i64] }:$saddr, VGPR_32:{ *:[i32] }:$voffset, i32:{ *:[i32] }:$offset), i64:{ *:[i64] }:$data)<<P:Predicate_atomic_load_add_global_64>>  =>  (GLOBAL_ATOMIC_ADD_X2_SADDR_RTN:{ *:[i64] } ?:{ *:[i32] }:$voffset, anonymous_15036:{ *:[i64] }:$data, ?:{ *:[i64] }:$saddr, ?:{ *:[i32] }:$offset)
        GIR_BuildMI, /*InsnID*/0, /*Opcode*/GIMT_Encode2(AMDGPU::GLOBAL_ATOMIC_ADD_X2_SADDR_RTN),
        GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/0, // DstI[vdst]
        GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/1, // voffset
        GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/2, // data
        GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/0, // saddr
        GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/2, // offset
        GIR_AddImm8, /*InsnID*/0, /*Imm*/1,
        GIR_MergeMemOperands, /*InsnID*/0, /*NumInsns*/1, /*MergeInsnID's*/0,
        GIR_ConstrainSelectedInstOperands, /*InsnID*/0,
        GIR_EraseFromParent, /*InsnID*/0,
        // GIR_Coverage, 3205,
        GIR_Done,
      // Label 2502: @164051
      GIM_Try, /*On fail goto*//*Label 2503*/ GIMT_Encode4(164109), // Rule ID 3202 //
        GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasFlatGlobalInsts),
        GIM_CheckMemoryAddressSpace, /*MI*/0, /*MMO*/0, /*NumAddrSpace*/3, /*AddrSpace*/1, /*AddrSpace*/4, /*AddrSpace*/6,
        GIM_CheckHasNoUse, /*MI*/0,
        GIM_CheckPointerToAny, /*MI*/0, /*Op*/1, /*SizeInBits*/0,
        GIM_CheckComplexPattern, /*MI*/0, /*Op*/1, /*Renderer*/GIMT_Encode2(0), GIMT_Encode2(GICP_gi_global_offset),
        // (atomic_load_add:{ *:[i64] } (GlobalOffset:{ *:[iPTR] } i64:{ *:[i64] }:$vaddr, i32:{ *:[i32] }:$offset), i64:{ *:[i64] }:$data)<<P:Predicate_atomic_load_add_global_noret_64>>  =>  (GLOBAL_ATOMIC_ADD_X2 VReg_64:{ *:[i64] }:$vaddr, anonymous_15036:{ *:[i64] }:$data, ?:{ *:[i32] }:$offset)
        GIR_BuildMI, /*InsnID*/0, /*Opcode*/GIMT_Encode2(AMDGPU::GLOBAL_ATOMIC_ADD_X2),
        GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/0, // vaddr
        GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/2, // data
        GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/1, // offset
        GIR_AddImm8, /*InsnID*/0, /*Imm*/0,
        GIR_MergeMemOperands, /*InsnID*/0, /*NumInsns*/1, /*MergeInsnID's*/0,
        GIR_ConstrainSelectedInstOperands, /*InsnID*/0,
        GIR_EraseFromParent, /*InsnID*/0,
        // GIR_Coverage, 3202,
        GIR_Done,
      // Label 2503: @164109
      GIM_Try, /*On fail goto*//*Label 2504*/ GIMT_Encode4(164174), // Rule ID 3204 //
        GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasFlatGlobalInsts),
        GIM_CheckMemoryAddressSpace, /*MI*/0, /*MMO*/0, /*NumAddrSpace*/3, /*AddrSpace*/1, /*AddrSpace*/4, /*AddrSpace*/6,
        GIM_CheckRegBankForClass, /*MI*/0, /*Op*/0, /*RC*/GIMT_Encode2(AMDGPU::AV_64RegClassID),
        GIM_CheckPointerToAny, /*MI*/0, /*Op*/1, /*SizeInBits*/0,
        GIM_CheckComplexPattern, /*MI*/0, /*Op*/1, /*Renderer*/GIMT_Encode2(0), GIMT_Encode2(GICP_gi_global_offset),
        // (atomic_load_add:{ *:[i64] } (GlobalOffset:{ *:[iPTR] } i64:{ *:[i64] }:$vaddr, i32:{ *:[i32] }:$offset), i64:{ *:[i64] }:$data)<<P:Predicate_atomic_load_add_global_64>>  =>  (GLOBAL_ATOMIC_ADD_X2_RTN:{ *:[i64] } VReg_64:{ *:[i64] }:$vaddr, anonymous_15036:{ *:[i64] }:$data, ?:{ *:[i32] }:$offset)
        GIR_BuildMI, /*InsnID*/0, /*Opcode*/GIMT_Encode2(AMDGPU::GLOBAL_ATOMIC_ADD_X2_RTN),
        GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/0, // DstI[vdst]
        GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/0, // vaddr
        GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/2, // data
        GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/1, // offset
        GIR_AddImm8, /*InsnID*/0, /*Imm*/1,
        GIR_MergeMemOperands, /*InsnID*/0, /*NumInsns*/1, /*MergeInsnID's*/0,
        GIR_ConstrainSelectedInstOperands, /*InsnID*/0,
        GIR_EraseFromParent, /*InsnID*/0,
        // GIR_Coverage, 3204,
        GIR_Done,
      // Label 2504: @164174
      GIM_Try, /*On fail goto*//*Label 2505*/ GIMT_Encode4(164233), // Rule ID 2854 //
        GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasFlatAddressSpace),
        GIM_CheckMemoryAddressSpace, /*MI*/0, /*MMO*/0, /*NumAddrSpace*/4, /*AddrSpace*/0, /*AddrSpace*/1, /*AddrSpace*/4, /*AddrSpace*/6,
        GIM_CheckHasNoUse, /*MI*/0,
        GIM_CheckPointerToAny, /*MI*/0, /*Op*/1, /*SizeInBits*/0,
        GIM_CheckComplexPattern, /*MI*/0, /*Op*/1, /*Renderer*/GIMT_Encode2(0), GIMT_Encode2(GICP_gi_flat_offset),
        // (atomic_load_add:{ *:[i64] } (FlatOffset:{ *:[iPTR] } i64:{ *:[i64] }:$vaddr, i32:{ *:[i32] }:$offset), i64:{ *:[i64] }:$data)<<P:Predicate_atomic_load_add_flat_noret_64>>  =>  (FLAT_ATOMIC_ADD_X2 VReg_64:{ *:[i64] }:$vaddr, anonymous_15036:{ *:[i64] }:$data, ?:{ *:[i32] }:$offset)
        GIR_BuildMI, /*InsnID*/0, /*Opcode*/GIMT_Encode2(AMDGPU::FLAT_ATOMIC_ADD_X2),
        GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/0, // vaddr
        GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/2, // data
        GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/1, // offset
        GIR_AddImm8, /*InsnID*/0, /*Imm*/0,
        GIR_MergeMemOperands, /*InsnID*/0, /*NumInsns*/1, /*MergeInsnID's*/0,
        GIR_ConstrainSelectedInstOperands, /*InsnID*/0,
        GIR_EraseFromParent, /*InsnID*/0,
        // GIR_Coverage, 2854,
        GIR_Done,
      // Label 2505: @164233
      GIM_Try, /*On fail goto*//*Label 2506*/ GIMT_Encode4(164291), // Rule ID 2906 //
        GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasFlatAddressSpace),
        GIM_CheckMemoryAddressSpace, /*MI*/0, /*MMO*/0, /*NumAddrSpace*/3, /*AddrSpace*/1, /*AddrSpace*/4, /*AddrSpace*/6,
        GIM_CheckHasNoUse, /*MI*/0,
        GIM_CheckPointerToAny, /*MI*/0, /*Op*/1, /*SizeInBits*/0,
        GIM_CheckComplexPattern, /*MI*/0, /*Op*/1, /*Renderer*/GIMT_Encode2(0), GIMT_Encode2(GICP_gi_flat_offset),
        // (atomic_load_add:{ *:[i64] } (FlatOffset:{ *:[iPTR] } i64:{ *:[i64] }:$vaddr, i32:{ *:[i32] }:$offset), i64:{ *:[i64] }:$data)<<P:Predicate_atomic_load_add_global_noret_64>>  =>  (FLAT_ATOMIC_ADD_X2 VReg_64:{ *:[i64] }:$vaddr, anonymous_15036:{ *:[i64] }:$data, ?:{ *:[i32] }:$offset)
        GIR_BuildMI, /*InsnID*/0, /*Opcode*/GIMT_Encode2(AMDGPU::FLAT_ATOMIC_ADD_X2),
        GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/0, // vaddr
        GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/2, // data
        GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/1, // offset
        GIR_AddImm8, /*InsnID*/0, /*Imm*/0,
        GIR_MergeMemOperands, /*InsnID*/0, /*NumInsns*/1, /*MergeInsnID's*/0,
        GIR_ConstrainSelectedInstOperands, /*InsnID*/0,
        GIR_EraseFromParent, /*InsnID*/0,
        // GIR_Coverage, 2906,
        GIR_Done,
      // Label 2506: @164291
      GIM_Try, /*On fail goto*//*Label 2507*/ GIMT_Encode4(164357), // Rule ID 2853 //
        GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasFlatAddressSpace),
        GIM_CheckMemoryAddressSpace, /*MI*/0, /*MMO*/0, /*NumAddrSpace*/4, /*AddrSpace*/0, /*AddrSpace*/1, /*AddrSpace*/4, /*AddrSpace*/6,
        GIM_CheckRegBankForClass, /*MI*/0, /*Op*/0, /*RC*/GIMT_Encode2(AMDGPU::AV_64RegClassID),
        GIM_CheckPointerToAny, /*MI*/0, /*Op*/1, /*SizeInBits*/0,
        GIM_CheckComplexPattern, /*MI*/0, /*Op*/1, /*Renderer*/GIMT_Encode2(0), GIMT_Encode2(GICP_gi_flat_offset),
        // (atomic_load_add:{ *:[i64] } (FlatOffset:{ *:[iPTR] } i64:{ *:[i64] }:$vaddr, i32:{ *:[i32] }:$offset), i64:{ *:[i64] }:$data)<<P:Predicate_atomic_load_add_flat_64>>  =>  (FLAT_ATOMIC_ADD_X2_RTN:{ *:[i64] } VReg_64:{ *:[i64] }:$vaddr, anonymous_15036:{ *:[i64] }:$data, ?:{ *:[i32] }:$offset)
        GIR_BuildMI, /*InsnID*/0, /*Opcode*/GIMT_Encode2(AMDGPU::FLAT_ATOMIC_ADD_X2_RTN),
        GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/0, // DstI[vdst]
        GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/0, // vaddr
        GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/2, // data
        GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/1, // offset
        GIR_AddImm8, /*InsnID*/0, /*Imm*/1,
        GIR_MergeMemOperands, /*InsnID*/0, /*NumInsns*/1, /*MergeInsnID's*/0,
        GIR_ConstrainSelectedInstOperands, /*InsnID*/0,
        GIR_EraseFromParent, /*InsnID*/0,
        // GIR_Coverage, 2853,
        GIR_Done,
      // Label 2507: @164357
      GIM_Try, /*On fail goto*//*Label 2508*/ GIMT_Encode4(164422), // Rule ID 2905 //
        GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasFlatAddressSpace),
        GIM_CheckMemoryAddressSpace, /*MI*/0, /*MMO*/0, /*NumAddrSpace*/3, /*AddrSpace*/1, /*AddrSpace*/4, /*AddrSpace*/6,
        GIM_CheckRegBankForClass, /*MI*/0, /*Op*/0, /*RC*/GIMT_Encode2(AMDGPU::AV_64RegClassID),
        GIM_CheckPointerToAny, /*MI*/0, /*Op*/1, /*SizeInBits*/0,
        GIM_CheckComplexPattern, /*MI*/0, /*Op*/1, /*Renderer*/GIMT_Encode2(0), GIMT_Encode2(GICP_gi_flat_offset),
        // (atomic_load_add:{ *:[i64] } (FlatOffset:{ *:[iPTR] } i64:{ *:[i64] }:$vaddr, i32:{ *:[i32] }:$offset), i64:{ *:[i64] }:$data)<<P:Predicate_atomic_load_add_global_64>>  =>  (FLAT_ATOMIC_ADD_X2_RTN:{ *:[i64] } VReg_64:{ *:[i64] }:$vaddr, anonymous_15036:{ *:[i64] }:$data, ?:{ *:[i32] }:$offset)
        GIR_BuildMI, /*InsnID*/0, /*Opcode*/GIMT_Encode2(AMDGPU::FLAT_ATOMIC_ADD_X2_RTN),
        GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/0, // DstI[vdst]
        GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/0, // vaddr
        GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/2, // data
        GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/1, // offset
        GIR_AddImm8, /*InsnID*/0, /*Imm*/1,
        GIR_MergeMemOperands, /*InsnID*/0, /*NumInsns*/1, /*MergeInsnID's*/0,
        GIR_ConstrainSelectedInstOperands, /*InsnID*/0,
        GIR_EraseFromParent, /*InsnID*/0,
        // GIR_Coverage, 2905,
        GIR_Done,
      // Label 2508: @164422
      GIM_Reject,
    // Label 2486: @164423
    GIM_Reject,
    // Label 2462: @164424
    GIM_Reject,
    // Label 19: @164425
    GIM_SwitchType, /*MI*/0, /*Op*/0, /*[*/GIMT_Encode2(9), GIMT_Encode2(11), /*)*//*default:*//*Label 2511*/ GIMT_Encode4(167268),
    /*GILLT_s32*//*Label 2509*/ GIMT_Encode4(164444),
    /*GILLT_s64*//*Label 2510*/ GIMT_Encode4(165856),
    // Label 2509: @164444
    GIM_Try, /*On fail goto*//*Label 2512*/ GIMT_Encode4(165855),
      GIM_CheckType, /*MI*/0, /*Op*/2, /*Type*/GILLT_s32,
      GIM_Try, /*On fail goto*//*Label 2513*/ GIMT_Encode4(164521), // Rule ID 4526 //
        GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasUnrestrictedSOffset),
        GIM_CheckMemoryAddressSpace, /*MI*/0, /*MMO*/0, /*NumAddrSpace*/3, /*AddrSpace*/1, /*AddrSpace*/4, /*AddrSpace*/6,
        GIM_CheckHasNoUse, /*MI*/0,
        GIM_CheckPointerToAny, /*MI*/0, /*Op*/1, /*SizeInBits*/0,
        GIM_CheckComplexPattern, /*MI*/0, /*Op*/1, /*Renderer*/GIMT_Encode2(0), GIMT_Encode2(GICP_gi_mubuf_addr64),
        // (atomic_load_sub:{ *:[i32] } (MUBUFAddr64:{ *:[iPTR] } v4i32:{ *:[v4i32] }:$srsrc, i64:{ *:[i64] }:$vaddr, i32:{ *:[i32] }:$soffset, i32:{ *:[i32] }:$offset), i32:{ *:[i32] }:$vdata_in)<<P:Predicate_atomic_load_sub_global_noret_32>>  =>  (BUFFER_ATOMIC_SUB_ADDR64 anonymous_15037:{ *:[i32] }:$vdata_in, VReg_64:{ *:[i64] }:$vaddr, SReg_128:{ *:[v4i32] }:$srsrc, SCSrc_b32:{ *:[i32] }:$soffset, offset:{ *:[i32] }:$offset)
        GIR_BuildMI, /*InsnID*/0, /*Opcode*/GIMT_Encode2(AMDGPU::BUFFER_ATOMIC_SUB_ADDR64),
        GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/2, // vdata_in
        GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/1, // vaddr
        GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/0, // srsrc
        GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/2, // soffset
        GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/3, // offset
        GIR_AddImm8, /*InsnID*/0, /*Imm*/0,
        GIR_MergeMemOperands, /*InsnID*/0, /*NumInsns*/1, /*MergeInsnID's*/0,
        GIR_ConstrainSelectedInstOperands, /*InsnID*/0,
        GIR_EraseFromParent, /*InsnID*/0,
        // GIR_Coverage, 4526,
        GIR_Done,
      // Label 2513: @164521
      GIM_Try, /*On fail goto*//*Label 2514*/ GIMT_Encode4(164586), // Rule ID 4530 //
        GIM_CheckMemoryAddressSpace, /*MI*/0, /*MMO*/0, /*NumAddrSpace*/3, /*AddrSpace*/1, /*AddrSpace*/4, /*AddrSpace*/6,
        GIM_CheckHasNoUse, /*MI*/0,
        GIM_CheckPointerToAny, /*MI*/0, /*Op*/1, /*SizeInBits*/0,
        GIM_CheckComplexPattern, /*MI*/0, /*Op*/1, /*Renderer*/GIMT_Encode2(0), GIMT_Encode2(GICP_gi_mubuf_addr64),
        // (atomic_load_sub:{ *:[i32] } (MUBUFAddr64:{ *:[iPTR] } v4i32:{ *:[v4i32] }:$srsrc, i64:{ *:[i64] }:$vaddr, i32:{ *:[i32] }:$soffset, i32:{ *:[i32] }:$offset), i32:{ *:[i32] }:$vdata_in)<<P:Predicate_atomic_load_sub_global_noret_32>>  =>  (BUFFER_ATOMIC_SUB_VBUFFER_ADDR64 anonymous_15037:{ *:[i32] }:$vdata_in, VReg_64:{ *:[i64] }:$vaddr, SReg_128:{ *:[v4i32] }:$srsrc, SCSrc_b32:{ *:[i32] }:$soffset, offset:{ *:[i32] }:$offset)
        GIR_BuildMI, /*InsnID*/0, /*Opcode*/GIMT_Encode2(AMDGPU::BUFFER_ATOMIC_SUB_VBUFFER_ADDR64),
        GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/2, // vdata_in
        GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/1, // vaddr
        GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/0, // srsrc
        GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/2, // soffset
        GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/3, // offset
        GIR_AddImm8, /*InsnID*/0, /*Imm*/0,
        GIR_MergeMemOperands, /*InsnID*/0, /*NumInsns*/1, /*MergeInsnID's*/0,
        GIR_ConstrainSelectedInstOperands, /*InsnID*/0,
        GIR_EraseFromParent, /*InsnID*/0,
        // GIR_Coverage, 4530,
        GIR_Done,
      // Label 2514: @164586
      GIM_Try, /*On fail goto*//*Label 2515*/ GIMT_Encode4(164661), // Rule ID 4524 //
        GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasUnrestrictedSOffset),
        GIM_CheckMemoryAddressSpace, /*MI*/0, /*MMO*/0, /*NumAddrSpace*/3, /*AddrSpace*/1, /*AddrSpace*/4, /*AddrSpace*/6,
        GIM_CheckRegBankForClass, /*MI*/0, /*Op*/0, /*RC*/GIMT_Encode2(AMDGPU::AV_32RegClassID),
        GIM_CheckPointerToAny, /*MI*/0, /*Op*/1, /*SizeInBits*/0,
        GIM_CheckComplexPattern, /*MI*/0, /*Op*/1, /*Renderer*/GIMT_Encode2(0), GIMT_Encode2(GICP_gi_mubuf_addr64),
        // (atomic_load_sub:{ *:[i32] } (MUBUFAddr64:{ *:[iPTR] } v4i32:{ *:[v4i32] }:$srsrc, i64:{ *:[i64] }:$vaddr, i32:{ *:[i32] }:$soffset, i32:{ *:[i32] }:$offset), i32:{ *:[i32] }:$vdata_in)<<P:Predicate_atomic_load_sub_global_32>>  =>  (BUFFER_ATOMIC_SUB_ADDR64_RTN:{ *:[i32] } anonymous_15037:{ *:[i32] }:$vdata_in, VReg_64:{ *:[i64] }:$vaddr, SReg_128:{ *:[v4i32] }:$srsrc, SCSrc_b32:{ *:[i32] }:$soffset, offset:{ *:[i32] }:$offset)
        GIR_BuildMI, /*InsnID*/0, /*Opcode*/GIMT_Encode2(AMDGPU::BUFFER_ATOMIC_SUB_ADDR64_RTN),
        GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/0, // DstI[vdata]
        GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/2, // vdata_in
        GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/1, // vaddr
        GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/0, // srsrc
        GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/2, // soffset
        GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/3, // offset
        GIR_AddImm8, /*InsnID*/0, /*Imm*/1,
        GIR_MergeMemOperands, /*InsnID*/0, /*NumInsns*/1, /*MergeInsnID's*/0,
        GIR_ConstrainSelectedInstOperands, /*InsnID*/0,
        GIR_EraseFromParent, /*InsnID*/0,
        // GIR_Coverage, 4524,
        GIR_Done,
      // Label 2515: @164661
      GIM_Try, /*On fail goto*//*Label 2516*/ GIMT_Encode4(164733), // Rule ID 4528 //
        GIM_CheckMemoryAddressSpace, /*MI*/0, /*MMO*/0, /*NumAddrSpace*/3, /*AddrSpace*/1, /*AddrSpace*/4, /*AddrSpace*/6,
        GIM_CheckRegBankForClass, /*MI*/0, /*Op*/0, /*RC*/GIMT_Encode2(AMDGPU::AV_32RegClassID),
        GIM_CheckPointerToAny, /*MI*/0, /*Op*/1, /*SizeInBits*/0,
        GIM_CheckComplexPattern, /*MI*/0, /*Op*/1, /*Renderer*/GIMT_Encode2(0), GIMT_Encode2(GICP_gi_mubuf_addr64),
        // (atomic_load_sub:{ *:[i32] } (MUBUFAddr64:{ *:[iPTR] } v4i32:{ *:[v4i32] }:$srsrc, i64:{ *:[i64] }:$vaddr, i32:{ *:[i32] }:$soffset, i32:{ *:[i32] }:$offset), i32:{ *:[i32] }:$vdata_in)<<P:Predicate_atomic_load_sub_global_32>>  =>  (BUFFER_ATOMIC_SUB_VBUFFER_ADDR64_RTN:{ *:[i32] } anonymous_15037:{ *:[i32] }:$vdata_in, VReg_64:{ *:[i64] }:$vaddr, SReg_128:{ *:[v4i32] }:$srsrc, SCSrc_b32:{ *:[i32] }:$soffset, offset:{ *:[i32] }:$offset)
        GIR_BuildMI, /*InsnID*/0, /*Opcode*/GIMT_Encode2(AMDGPU::BUFFER_ATOMIC_SUB_VBUFFER_ADDR64_RTN),
        GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/0, // DstI[vdata]
        GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/2, // vdata_in
        GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/1, // vaddr
        GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/0, // srsrc
        GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/2, // soffset
        GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/3, // offset
        GIR_AddImm8, /*InsnID*/0, /*Imm*/1,
        GIR_MergeMemOperands, /*InsnID*/0, /*NumInsns*/1, /*MergeInsnID's*/0,
        GIR_ConstrainSelectedInstOperands, /*InsnID*/0,
        GIR_EraseFromParent, /*InsnID*/0,
        // GIR_Coverage, 4528,
        GIR_Done,
      // Label 2516: @164733
      GIM_Try, /*On fail goto*//*Label 2517*/ GIMT_Encode4(164796), // Rule ID 4525 //
        GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasUnrestrictedSOffset),
        GIM_CheckMemoryAddressSpace, /*MI*/0, /*MMO*/0, /*NumAddrSpace*/3, /*AddrSpace*/1, /*AddrSpace*/4, /*AddrSpace*/6,
        GIM_CheckHasNoUse, /*MI*/0,
        GIM_CheckPointerToAny, /*MI*/0, /*Op*/1, /*SizeInBits*/0,
        GIM_CheckComplexPattern, /*MI*/0, /*Op*/1, /*Renderer*/GIMT_Encode2(0), GIMT_Encode2(GICP_gi_mubuf_offset),
        // (atomic_load_sub:{ *:[i32] } (MUBUFOffset:{ *:[iPTR] } v4i32:{ *:[v4i32] }:$srsrc, i32:{ *:[i32] }:$soffset, i32:{ *:[i32] }:$offset), i32:{ *:[i32] }:$vdata_in)<<P:Predicate_atomic_load_sub_global_noret_32>>  =>  (BUFFER_ATOMIC_SUB_OFFSET anonymous_15037:{ *:[i32] }:$vdata_in, SReg_128:{ *:[v4i32] }:$srsrc, SCSrc_b32:{ *:[i32] }:$soffset, offset:{ *:[i32] }:$offset)
        GIR_BuildMI, /*InsnID*/0, /*Opcode*/GIMT_Encode2(AMDGPU::BUFFER_ATOMIC_SUB_OFFSET),
        GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/2, // vdata_in
        GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/0, // srsrc
        GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/1, // soffset
        GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/2, // offset
        GIR_AddImm8, /*InsnID*/0, /*Imm*/0,
        GIR_MergeMemOperands, /*InsnID*/0, /*NumInsns*/1, /*MergeInsnID's*/0,
        GIR_ConstrainSelectedInstOperands, /*InsnID*/0,
        GIR_EraseFromParent, /*InsnID*/0,
        // GIR_Coverage, 4525,
        GIR_Done,
      // Label 2517: @164796
      GIM_Try, /*On fail goto*//*Label 2518*/ GIMT_Encode4(164856), // Rule ID 4529 //
        GIM_CheckMemoryAddressSpace, /*MI*/0, /*MMO*/0, /*NumAddrSpace*/3, /*AddrSpace*/1, /*AddrSpace*/4, /*AddrSpace*/6,
        GIM_CheckHasNoUse, /*MI*/0,
        GIM_CheckPointerToAny, /*MI*/0, /*Op*/1, /*SizeInBits*/0,
        GIM_CheckComplexPattern, /*MI*/0, /*Op*/1, /*Renderer*/GIMT_Encode2(0), GIMT_Encode2(GICP_gi_mubuf_offset),
        // (atomic_load_sub:{ *:[i32] } (MUBUFOffset:{ *:[iPTR] } v4i32:{ *:[v4i32] }:$srsrc, i32:{ *:[i32] }:$soffset, i32:{ *:[i32] }:$offset), i32:{ *:[i32] }:$vdata_in)<<P:Predicate_atomic_load_sub_global_noret_32>>  =>  (BUFFER_ATOMIC_SUB_VBUFFER_OFFSET anonymous_15037:{ *:[i32] }:$vdata_in, SReg_128:{ *:[v4i32] }:$srsrc, SCSrc_b32:{ *:[i32] }:$soffset, offset:{ *:[i32] }:$offset)
        GIR_BuildMI, /*InsnID*/0, /*Opcode*/GIMT_Encode2(AMDGPU::BUFFER_ATOMIC_SUB_VBUFFER_OFFSET),
        GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/2, // vdata_in
        GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/0, // srsrc
        GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/1, // soffset
        GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/2, // offset
        GIR_AddImm8, /*InsnID*/0, /*Imm*/0,
        GIR_MergeMemOperands, /*InsnID*/0, /*NumInsns*/1, /*MergeInsnID's*/0,
        GIR_ConstrainSelectedInstOperands, /*InsnID*/0,
        GIR_EraseFromParent, /*InsnID*/0,
        // GIR_Coverage, 4529,
        GIR_Done,
      // Label 2518: @164856
      GIM_Try, /*On fail goto*//*Label 2519*/ GIMT_Encode4(164926), // Rule ID 4523 //
        GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasUnrestrictedSOffset),
        GIM_CheckMemoryAddressSpace, /*MI*/0, /*MMO*/0, /*NumAddrSpace*/3, /*AddrSpace*/1, /*AddrSpace*/4, /*AddrSpace*/6,
        GIM_CheckRegBankForClass, /*MI*/0, /*Op*/0, /*RC*/GIMT_Encode2(AMDGPU::AV_32RegClassID),
        GIM_CheckPointerToAny, /*MI*/0, /*Op*/1, /*SizeInBits*/0,
        GIM_CheckComplexPattern, /*MI*/0, /*Op*/1, /*Renderer*/GIMT_Encode2(0), GIMT_Encode2(GICP_gi_mubuf_offset),
        // (atomic_load_sub:{ *:[i32] } (MUBUFOffset:{ *:[iPTR] } v4i32:{ *:[v4i32] }:$srsrc, i32:{ *:[i32] }:$soffset, i32:{ *:[i32] }:$offset), i32:{ *:[i32] }:$vdata_in)<<P:Predicate_atomic_load_sub_global_32>>  =>  (BUFFER_ATOMIC_SUB_OFFSET_RTN:{ *:[i32] } anonymous_15037:{ *:[i32] }:$vdata_in, SReg_128:{ *:[v4i32] }:$srsrc, SCSrc_b32:{ *:[i32] }:$soffset, offset:{ *:[i32] }:$offset)
        GIR_BuildMI, /*InsnID*/0, /*Opcode*/GIMT_Encode2(AMDGPU::BUFFER_ATOMIC_SUB_OFFSET_RTN),
        GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/0, // DstI[vdata]
        GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/2, // vdata_in
        GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/0, // srsrc
        GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/1, // soffset
        GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/2, // offset
        GIR_AddImm8, /*InsnID*/0, /*Imm*/1,
        GIR_MergeMemOperands, /*InsnID*/0, /*NumInsns*/1, /*MergeInsnID's*/0,
        GIR_ConstrainSelectedInstOperands, /*InsnID*/0,
        GIR_EraseFromParent, /*InsnID*/0,
        // GIR_Coverage, 4523,
        GIR_Done,
      // Label 2519: @164926
      GIM_Try, /*On fail goto*//*Label 2520*/ GIMT_Encode4(164993), // Rule ID 4527 //
        GIM_CheckMemoryAddressSpace, /*MI*/0, /*MMO*/0, /*NumAddrSpace*/3, /*AddrSpace*/1, /*AddrSpace*/4, /*AddrSpace*/6,
        GIM_CheckRegBankForClass, /*MI*/0, /*Op*/0, /*RC*/GIMT_Encode2(AMDGPU::AV_32RegClassID),
        GIM_CheckPointerToAny, /*MI*/0, /*Op*/1, /*SizeInBits*/0,
        GIM_CheckComplexPattern, /*MI*/0, /*Op*/1, /*Renderer*/GIMT_Encode2(0), GIMT_Encode2(GICP_gi_mubuf_offset),
        // (atomic_load_sub:{ *:[i32] } (MUBUFOffset:{ *:[iPTR] } v4i32:{ *:[v4i32] }:$srsrc, i32:{ *:[i32] }:$soffset, i32:{ *:[i32] }:$offset), i32:{ *:[i32] }:$vdata_in)<<P:Predicate_atomic_load_sub_global_32>>  =>  (BUFFER_ATOMIC_SUB_VBUFFER_OFFSET_RTN:{ *:[i32] } anonymous_15037:{ *:[i32] }:$vdata_in, SReg_128:{ *:[v4i32] }:$srsrc, SCSrc_b32:{ *:[i32] }:$soffset, offset:{ *:[i32] }:$offset)
        GIR_BuildMI, /*InsnID*/0, /*Opcode*/GIMT_Encode2(AMDGPU::BUFFER_ATOMIC_SUB_VBUFFER_OFFSET_RTN),
        GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/0, // DstI[vdata]
        GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/2, // vdata_in
        GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/0, // srsrc
        GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/1, // soffset
        GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/2, // offset
        GIR_AddImm8, /*InsnID*/0, /*Imm*/1,
        GIR_MergeMemOperands, /*InsnID*/0, /*NumInsns*/1, /*MergeInsnID's*/0,
        GIR_ConstrainSelectedInstOperands, /*InsnID*/0,
        GIR_EraseFromParent, /*InsnID*/0,
        // GIR_Coverage, 4527,
        GIR_Done,
      // Label 2520: @164993
      GIM_Try, /*On fail goto*//*Label 2521*/ GIMT_Encode4(165049), // Rule ID 6911 //
        GIM_CheckFeatures, GIMT_Encode2(GIFBS_LDSRequiresM0Init),
        GIM_CheckMemoryAddressSpace, /*MI*/0, /*MMO*/0, /*NumAddrSpace*/1, /*AddrSpace*/3,
        GIM_CheckHasNoUse, /*MI*/0,
        GIM_CheckPointerToAny, /*MI*/0, /*Op*/1, /*SizeInBits*/0,
        GIM_CheckComplexPattern, /*MI*/0, /*Op*/1, /*Renderer*/GIMT_Encode2(0), GIMT_Encode2(GICP_gi_ds_1addr_1offset),
        // (atomic_load_sub_glue:{ *:[i32] } (DS1Addr1Offset:{ *:[iPTR] } i32:{ *:[i32] }:$ptr, i32:{ *:[i32] }:$offset), i32:{ *:[i32] }:$value)<<P:Predicate_atomic_load_sub_local_m0_noret_32>>  =>  (DS_SUB_U32 ?:{ *:[i32] }:$ptr, anonymous_15037:{ *:[i32] }:$value, offset:{ *:[i32] }:$offset, 0:{ *:[i1] })
        GIR_BuildMI, /*InsnID*/0, /*Opcode*/GIMT_Encode2(AMDGPU::DS_SUB_U32),
        GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/0, // ptr
        GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/2, // value
        GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/1, // offset
        GIR_AddImm8, /*InsnID*/0, /*Imm*/0,
        GIR_MergeMemOperands, /*InsnID*/0, /*NumInsns*/1, /*MergeInsnID's*/0,
        GIR_ConstrainSelectedInstOperands, /*InsnID*/0,
        GIR_EraseFromParent, /*InsnID*/0,
        // GIR_Coverage, 6911,
        GIR_Done,
      // Label 2521: @165049
      GIM_Try, /*On fail goto*//*Label 2522*/ GIMT_Encode4(165105), // Rule ID 6913 //
        GIM_CheckFeatures, GIMT_Encode2(GIFBS_NotLDSRequiresM0Init),
        GIM_CheckMemoryAddressSpace, /*MI*/0, /*MMO*/0, /*NumAddrSpace*/1, /*AddrSpace*/3,
        GIM_CheckHasNoUse, /*MI*/0,
        GIM_CheckPointerToAny, /*MI*/0, /*Op*/1, /*SizeInBits*/0,
        GIM_CheckComplexPattern, /*MI*/0, /*Op*/1, /*Renderer*/GIMT_Encode2(0), GIMT_Encode2(GICP_gi_ds_1addr_1offset),
        // (atomic_load_sub:{ *:[i32] } (DS1Addr1Offset:{ *:[iPTR] } i32:{ *:[i32] }:$ptr, i32:{ *:[i32] }:$offset), i32:{ *:[i32] }:$value)<<P:Predicate_atomic_load_sub_local_noret_32>>  =>  (DS_SUB_U32_gfx9 ?:{ *:[i32] }:$ptr, anonymous_15037:{ *:[i32] }:$value, offset:{ *:[i32] }:$offset, 0:{ *:[i1] })
        GIR_BuildMI, /*InsnID*/0, /*Opcode*/GIMT_Encode2(AMDGPU::DS_SUB_U32_gfx9),
        GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/0, // ptr
        GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/2, // value
        GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/1, // offset
        GIR_AddImm8, /*InsnID*/0, /*Imm*/0,
        GIR_MergeMemOperands, /*InsnID*/0, /*NumInsns*/1, /*MergeInsnID's*/0,
        GIR_ConstrainSelectedInstOperands, /*InsnID*/0,
        GIR_EraseFromParent, /*InsnID*/0,
        // GIR_Coverage, 6913,
        GIR_Done,
      // Label 2522: @165105
      GIM_Try, /*On fail goto*//*Label 2523*/ GIMT_Encode4(165161), // Rule ID 6915 //
        GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasGDS),
        GIM_CheckMemoryAddressSpace, /*MI*/0, /*MMO*/0, /*NumAddrSpace*/1, /*AddrSpace*/2,
        GIM_CheckHasNoUse, /*MI*/0,
        GIM_CheckPointerToAny, /*MI*/0, /*Op*/1, /*SizeInBits*/0,
        GIM_CheckComplexPattern, /*MI*/0, /*Op*/1, /*Renderer*/GIMT_Encode2(0), GIMT_Encode2(GICP_gi_ds_1addr_1offset),
        // (atomic_load_sub_glue:{ *:[i32] } (DS1Addr1Offset:{ *:[iPTR] } i32:{ *:[i32] }:$ptr, i32:{ *:[i32] }:$offset), i32:{ *:[i32] }:$value)<<P:Predicate_atomic_load_sub_region_m0_noret_32>>  =>  (DS_SUB_U32 ?:{ *:[i32] }:$ptr, anonymous_15037:{ *:[i32] }:$value, offset:{ *:[i32] }:$offset, 1:{ *:[i1] })
        GIR_BuildMI, /*InsnID*/0, /*Opcode*/GIMT_Encode2(AMDGPU::DS_SUB_U32),
        GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/0, // ptr
        GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/2, // value
        GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/1, // offset
        GIR_AddImm8, /*InsnID*/0, /*Imm*/1,
        GIR_MergeMemOperands, /*InsnID*/0, /*NumInsns*/1, /*MergeInsnID's*/0,
        GIR_ConstrainSelectedInstOperands, /*InsnID*/0,
        GIR_EraseFromParent, /*InsnID*/0,
        // GIR_Coverage, 6915,
        GIR_Done,
      // Label 2523: @165161
      GIM_Try, /*On fail goto*//*Label 2524*/ GIMT_Encode4(165224), // Rule ID 6910 //
        GIM_CheckFeatures, GIMT_Encode2(GIFBS_LDSRequiresM0Init),
        GIM_CheckMemoryAddressSpace, /*MI*/0, /*MMO*/0, /*NumAddrSpace*/1, /*AddrSpace*/3,
        GIM_CheckRegBankForClass, /*MI*/0, /*Op*/0, /*RC*/GIMT_Encode2(AMDGPU::AV_32RegClassID),
        GIM_CheckPointerToAny, /*MI*/0, /*Op*/1, /*SizeInBits*/0,
        GIM_CheckComplexPattern, /*MI*/0, /*Op*/1, /*Renderer*/GIMT_Encode2(0), GIMT_Encode2(GICP_gi_ds_1addr_1offset),
        // (atomic_load_sub_glue:{ *:[i32] } (DS1Addr1Offset:{ *:[iPTR] } i32:{ *:[i32] }:$ptr, i32:{ *:[i32] }:$offset), i32:{ *:[i32] }:$value)<<P:Predicate_atomic_load_sub_local_m0_32>>  =>  (DS_SUB_RTN_U32:{ *:[i32] } ?:{ *:[i32] }:$ptr, anonymous_15037:{ *:[i32] }:$value, offset:{ *:[i32] }:$offset, 0:{ *:[i1] })
        GIR_BuildMI, /*InsnID*/0, /*Opcode*/GIMT_Encode2(AMDGPU::DS_SUB_RTN_U32),
        GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/0, // DstI[vdst]
        GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/0, // ptr
        GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/2, // value
        GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/1, // offset
        GIR_AddImm8, /*InsnID*/0, /*Imm*/0,
        GIR_MergeMemOperands, /*InsnID*/0, /*NumInsns*/1, /*MergeInsnID's*/0,
        GIR_ConstrainSelectedInstOperands, /*InsnID*/0,
        GIR_EraseFromParent, /*InsnID*/0,
        // GIR_Coverage, 6910,
        GIR_Done,
      // Label 2524: @165224
      GIM_Try, /*On fail goto*//*Label 2525*/ GIMT_Encode4(165287), // Rule ID 6912 //
        GIM_CheckFeatures, GIMT_Encode2(GIFBS_NotLDSRequiresM0Init),
        GIM_CheckMemoryAddressSpace, /*MI*/0, /*MMO*/0, /*NumAddrSpace*/1, /*AddrSpace*/3,
        GIM_CheckRegBankForClass, /*MI*/0, /*Op*/0, /*RC*/GIMT_Encode2(AMDGPU::AV_32RegClassID),
        GIM_CheckPointerToAny, /*MI*/0, /*Op*/1, /*SizeInBits*/0,
        GIM_CheckComplexPattern, /*MI*/0, /*Op*/1, /*Renderer*/GIMT_Encode2(0), GIMT_Encode2(GICP_gi_ds_1addr_1offset),
        // (atomic_load_sub:{ *:[i32] } (DS1Addr1Offset:{ *:[iPTR] } i32:{ *:[i32] }:$ptr, i32:{ *:[i32] }:$offset), i32:{ *:[i32] }:$value)<<P:Predicate_atomic_load_sub_local_32>>  =>  (DS_SUB_RTN_U32_gfx9:{ *:[i32] } ?:{ *:[i32] }:$ptr, anonymous_15037:{ *:[i32] }:$value, offset:{ *:[i32] }:$offset, 0:{ *:[i1] })
        GIR_BuildMI, /*InsnID*/0, /*Opcode*/GIMT_Encode2(AMDGPU::DS_SUB_RTN_U32_gfx9),
        GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/0, // DstI[vdst]
        GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/0, // ptr
        GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/2, // value
        GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/1, // offset
        GIR_AddImm8, /*InsnID*/0, /*Imm*/0,
        GIR_MergeMemOperands, /*InsnID*/0, /*NumInsns*/1, /*MergeInsnID's*/0,
        GIR_ConstrainSelectedInstOperands, /*InsnID*/0,
        GIR_EraseFromParent, /*InsnID*/0,
        // GIR_Coverage, 6912,
        GIR_Done,
      // Label 2525: @165287
      GIM_Try, /*On fail goto*//*Label 2526*/ GIMT_Encode4(165350), // Rule ID 6914 //
        GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasGDS),
        GIM_CheckMemoryAddressSpace, /*MI*/0, /*MMO*/0, /*NumAddrSpace*/1, /*AddrSpace*/2,
        GIM_CheckRegBankForClass, /*MI*/0, /*Op*/0, /*RC*/GIMT_Encode2(AMDGPU::AV_32RegClassID),
        GIM_CheckPointerToAny, /*MI*/0, /*Op*/1, /*SizeInBits*/0,
        GIM_CheckComplexPattern, /*MI*/0, /*Op*/1, /*Renderer*/GIMT_Encode2(0), GIMT_Encode2(GICP_gi_ds_1addr_1offset),
        // (atomic_load_sub_glue:{ *:[i32] } (DS1Addr1Offset:{ *:[iPTR] } i32:{ *:[i32] }:$ptr, i32:{ *:[i32] }:$offset), i32:{ *:[i32] }:$value)<<P:Predicate_atomic_load_sub_region_m0_32>>  =>  (DS_SUB_RTN_U32:{ *:[i32] } ?:{ *:[i32] }:$ptr, anonymous_15037:{ *:[i32] }:$value, offset:{ *:[i32] }:$offset, 1:{ *:[i1] })
        GIR_BuildMI, /*InsnID*/0, /*Opcode*/GIMT_Encode2(AMDGPU::DS_SUB_RTN_U32),
        GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/0, // DstI[vdst]
        GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/0, // ptr
        GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/2, // value
        GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/1, // offset
        GIR_AddImm8, /*InsnID*/0, /*Imm*/1,
        GIR_MergeMemOperands, /*InsnID*/0, /*NumInsns*/1, /*MergeInsnID's*/0,
        GIR_ConstrainSelectedInstOperands, /*InsnID*/0,
        GIR_EraseFromParent, /*InsnID*/0,
        // GIR_Coverage, 6914,
        GIR_Done,
      // Label 2526: @165350
      GIM_Try, /*On fail goto*//*Label 2527*/ GIMT_Encode4(165413), // Rule ID 3151 //
        GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasFlatGlobalInsts),
        GIM_CheckMemoryAddressSpace, /*MI*/0, /*MMO*/0, /*NumAddrSpace*/3, /*AddrSpace*/1, /*AddrSpace*/4, /*AddrSpace*/6,
        GIM_CheckHasNoUse, /*MI*/0,
        GIM_CheckPointerToAny, /*MI*/0, /*Op*/1, /*SizeInBits*/0,
        GIM_CheckComplexPattern, /*MI*/0, /*Op*/1, /*Renderer*/GIMT_Encode2(0), GIMT_Encode2(GICP_gi_global_saddr),
        // (atomic_load_sub:{ *:[i32] } (GlobalSAddr:{ *:[iPTR] } SReg_64:{ *:[i64] }:$saddr, VGPR_32:{ *:[i32] }:$voffset, i32:{ *:[i32] }:$offset), i32:{ *:[i32] }:$data)<<P:Predicate_atomic_load_sub_global_noret_32>>  =>  (GLOBAL_ATOMIC_SUB_SADDR ?:{ *:[i32] }:$voffset, anonymous_15037:{ *:[i32] }:$data, ?:{ *:[i64] }:$saddr, ?:{ *:[i32] }:$offset)
        GIR_BuildMI, /*InsnID*/0, /*Opcode*/GIMT_Encode2(AMDGPU::GLOBAL_ATOMIC_SUB_SADDR),
        GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/1, // voffset
        GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/2, // data
        GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/0, // saddr
        GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/2, // offset
        GIR_AddImm8, /*InsnID*/0, /*Imm*/0,
        GIR_MergeMemOperands, /*InsnID*/0, /*NumInsns*/1, /*MergeInsnID's*/0,
        GIR_ConstrainSelectedInstOperands, /*InsnID*/0,
        GIR_EraseFromParent, /*InsnID*/0,
        // GIR_Coverage, 3151,
        GIR_Done,
      // Label 2527: @165413
      GIM_Try, /*On fail goto*//*Label 2528*/ GIMT_Encode4(165483), // Rule ID 3153 //
        GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasFlatGlobalInsts),
        GIM_CheckMemoryAddressSpace, /*MI*/0, /*MMO*/0, /*NumAddrSpace*/3, /*AddrSpace*/1, /*AddrSpace*/4, /*AddrSpace*/6,
        GIM_CheckRegBankForClass, /*MI*/0, /*Op*/0, /*RC*/GIMT_Encode2(AMDGPU::AV_32RegClassID),
        GIM_CheckPointerToAny, /*MI*/0, /*Op*/1, /*SizeInBits*/0,
        GIM_CheckComplexPattern, /*MI*/0, /*Op*/1, /*Renderer*/GIMT_Encode2(0), GIMT_Encode2(GICP_gi_global_saddr),
        // (atomic_load_sub:{ *:[i32] } (GlobalSAddr:{ *:[iPTR] } SReg_64:{ *:[i64] }:$saddr, VGPR_32:{ *:[i32] }:$voffset, i32:{ *:[i32] }:$offset), i32:{ *:[i32] }:$data)<<P:Predicate_atomic_load_sub_global_32>>  =>  (GLOBAL_ATOMIC_SUB_SADDR_RTN:{ *:[i32] } ?:{ *:[i32] }:$voffset, anonymous_15037:{ *:[i32] }:$data, ?:{ *:[i64] }:$saddr, ?:{ *:[i32] }:$offset)
        GIR_BuildMI, /*InsnID*/0, /*Opcode*/GIMT_Encode2(AMDGPU::GLOBAL_ATOMIC_SUB_SADDR_RTN),
        GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/0, // DstI[vdst]
        GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/1, // voffset
        GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/2, // data
        GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/0, // saddr
        GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/2, // offset
        GIR_AddImm8, /*InsnID*/0, /*Imm*/1,
        GIR_MergeMemOperands, /*InsnID*/0, /*NumInsns*/1, /*MergeInsnID's*/0,
        GIR_ConstrainSelectedInstOperands, /*InsnID*/0,
        GIR_EraseFromParent, /*InsnID*/0,
        // GIR_Coverage, 3153,
        GIR_Done,
      // Label 2528: @165483
      GIM_Try, /*On fail goto*//*Label 2529*/ GIMT_Encode4(165541), // Rule ID 3150 //
        GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasFlatGlobalInsts),
        GIM_CheckMemoryAddressSpace, /*MI*/0, /*MMO*/0, /*NumAddrSpace*/3, /*AddrSpace*/1, /*AddrSpace*/4, /*AddrSpace*/6,
        GIM_CheckHasNoUse, /*MI*/0,
        GIM_CheckPointerToAny, /*MI*/0, /*Op*/1, /*SizeInBits*/0,
        GIM_CheckComplexPattern, /*MI*/0, /*Op*/1, /*Renderer*/GIMT_Encode2(0), GIMT_Encode2(GICP_gi_global_offset),
        // (atomic_load_sub:{ *:[i32] } (GlobalOffset:{ *:[iPTR] } i64:{ *:[i64] }:$vaddr, i32:{ *:[i32] }:$offset), i32:{ *:[i32] }:$data)<<P:Predicate_atomic_load_sub_global_noret_32>>  =>  (GLOBAL_ATOMIC_SUB VReg_64:{ *:[i64] }:$vaddr, anonymous_15037:{ *:[i32] }:$data, ?:{ *:[i32] }:$offset)
        GIR_BuildMI, /*InsnID*/0, /*Opcode*/GIMT_Encode2(AMDGPU::GLOBAL_ATOMIC_SUB),
        GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/0, // vaddr
        GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/2, // data
        GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/1, // offset
        GIR_AddImm8, /*InsnID*/0, /*Imm*/0,
        GIR_MergeMemOperands, /*InsnID*/0, /*NumInsns*/1, /*MergeInsnID's*/0,
        GIR_ConstrainSelectedInstOperands, /*InsnID*/0,
        GIR_EraseFromParent, /*InsnID*/0,
        // GIR_Coverage, 3150,
        GIR_Done,
      // Label 2529: @165541
      GIM_Try, /*On fail goto*//*Label 2530*/ GIMT_Encode4(165606), // Rule ID 3152 //
        GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasFlatGlobalInsts),
        GIM_CheckMemoryAddressSpace, /*MI*/0, /*MMO*/0, /*NumAddrSpace*/3, /*AddrSpace*/1, /*AddrSpace*/4, /*AddrSpace*/6,
        GIM_CheckRegBankForClass, /*MI*/0, /*Op*/0, /*RC*/GIMT_Encode2(AMDGPU::AV_32RegClassID),
        GIM_CheckPointerToAny, /*MI*/0, /*Op*/1, /*SizeInBits*/0,
        GIM_CheckComplexPattern, /*MI*/0, /*Op*/1, /*Renderer*/GIMT_Encode2(0), GIMT_Encode2(GICP_gi_global_offset),
        // (atomic_load_sub:{ *:[i32] } (GlobalOffset:{ *:[iPTR] } i64:{ *:[i64] }:$vaddr, i32:{ *:[i32] }:$offset), i32:{ *:[i32] }:$data)<<P:Predicate_atomic_load_sub_global_32>>  =>  (GLOBAL_ATOMIC_SUB_RTN:{ *:[i32] } VReg_64:{ *:[i64] }:$vaddr, anonymous_15037:{ *:[i32] }:$data, ?:{ *:[i32] }:$offset)
        GIR_BuildMI, /*InsnID*/0, /*Opcode*/GIMT_Encode2(AMDGPU::GLOBAL_ATOMIC_SUB_RTN),
        GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/0, // DstI[vdst]
        GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/0, // vaddr
        GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/2, // data
        GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/1, // offset
        GIR_AddImm8, /*InsnID*/0, /*Imm*/1,
        GIR_MergeMemOperands, /*InsnID*/0, /*NumInsns*/1, /*MergeInsnID's*/0,
        GIR_ConstrainSelectedInstOperands, /*InsnID*/0,
        GIR_EraseFromParent, /*InsnID*/0,
        // GIR_Coverage, 3152,
        GIR_Done,
      // Label 2530: @165606
      GIM_Try, /*On fail goto*//*Label 2531*/ GIMT_Encode4(165665), // Rule ID 2830 //
        GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasFlatAddressSpace),
        GIM_CheckMemoryAddressSpace, /*MI*/0, /*MMO*/0, /*NumAddrSpace*/4, /*AddrSpace*/0, /*AddrSpace*/1, /*AddrSpace*/4, /*AddrSpace*/6,
        GIM_CheckHasNoUse, /*MI*/0,
        GIM_CheckPointerToAny, /*MI*/0, /*Op*/1, /*SizeInBits*/0,
        GIM_CheckComplexPattern, /*MI*/0, /*Op*/1, /*Renderer*/GIMT_Encode2(0), GIMT_Encode2(GICP_gi_flat_offset),
        // (atomic_load_sub:{ *:[i32] } (FlatOffset:{ *:[iPTR] } i64:{ *:[i64] }:$vaddr, i32:{ *:[i32] }:$offset), i32:{ *:[i32] }:$data)<<P:Predicate_atomic_load_sub_flat_noret_32>>  =>  (FLAT_ATOMIC_SUB VReg_64:{ *:[i64] }:$vaddr, anonymous_15037:{ *:[i32] }:$data, ?:{ *:[i32] }:$offset)
        GIR_BuildMI, /*InsnID*/0, /*Opcode*/GIMT_Encode2(AMDGPU::FLAT_ATOMIC_SUB),
        GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/0, // vaddr
        GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/2, // data
        GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/1, // offset
        GIR_AddImm8, /*InsnID*/0, /*Imm*/0,
        GIR_MergeMemOperands, /*InsnID*/0, /*NumInsns*/1, /*MergeInsnID's*/0,
        GIR_ConstrainSelectedInstOperands, /*InsnID*/0,
        GIR_EraseFromParent, /*InsnID*/0,
        // GIR_Coverage, 2830,
        GIR_Done,
      // Label 2531: @165665
      GIM_Try, /*On fail goto*//*Label 2532*/ GIMT_Encode4(165723), // Rule ID 2882 //
        GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasFlatAddressSpace),
        GIM_CheckMemoryAddressSpace, /*MI*/0, /*MMO*/0, /*NumAddrSpace*/3, /*AddrSpace*/1, /*AddrSpace*/4, /*AddrSpace*/6,
        GIM_CheckHasNoUse, /*MI*/0,
        GIM_CheckPointerToAny, /*MI*/0, /*Op*/1, /*SizeInBits*/0,
        GIM_CheckComplexPattern, /*MI*/0, /*Op*/1, /*Renderer*/GIMT_Encode2(0), GIMT_Encode2(GICP_gi_flat_offset),
        // (atomic_load_sub:{ *:[i32] } (FlatOffset:{ *:[iPTR] } i64:{ *:[i64] }:$vaddr, i32:{ *:[i32] }:$offset), i32:{ *:[i32] }:$data)<<P:Predicate_atomic_load_sub_global_noret_32>>  =>  (FLAT_ATOMIC_SUB VReg_64:{ *:[i64] }:$vaddr, anonymous_15037:{ *:[i32] }:$data, ?:{ *:[i32] }:$offset)
        GIR_BuildMI, /*InsnID*/0, /*Opcode*/GIMT_Encode2(AMDGPU::FLAT_ATOMIC_SUB),
        GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/0, // vaddr
        GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/2, // data
        GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/1, // offset
        GIR_AddImm8, /*InsnID*/0, /*Imm*/0,
        GIR_MergeMemOperands, /*InsnID*/0, /*NumInsns*/1, /*MergeInsnID's*/0,
        GIR_ConstrainSelectedInstOperands, /*InsnID*/0,
        GIR_EraseFromParent, /*InsnID*/0,
        // GIR_Coverage, 2882,
        GIR_Done,
      // Label 2532: @165723
      GIM_Try, /*On fail goto*//*Label 2533*/ GIMT_Encode4(165789), // Rule ID 2829 //
        GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasFlatAddressSpace),
        GIM_CheckMemoryAddressSpace, /*MI*/0, /*MMO*/0, /*NumAddrSpace*/4, /*AddrSpace*/0, /*AddrSpace*/1, /*AddrSpace*/4, /*AddrSpace*/6,
        GIM_CheckRegBankForClass, /*MI*/0, /*Op*/0, /*RC*/GIMT_Encode2(AMDGPU::AV_32RegClassID),
        GIM_CheckPointerToAny, /*MI*/0, /*Op*/1, /*SizeInBits*/0,
        GIM_CheckComplexPattern, /*MI*/0, /*Op*/1, /*Renderer*/GIMT_Encode2(0), GIMT_Encode2(GICP_gi_flat_offset),
        // (atomic_load_sub:{ *:[i32] } (FlatOffset:{ *:[iPTR] } i64:{ *:[i64] }:$vaddr, i32:{ *:[i32] }:$offset), i32:{ *:[i32] }:$data)<<P:Predicate_atomic_load_sub_flat_32>>  =>  (FLAT_ATOMIC_SUB_RTN:{ *:[i32] } VReg_64:{ *:[i64] }:$vaddr, anonymous_15037:{ *:[i32] }:$data, ?:{ *:[i32] }:$offset)
        GIR_BuildMI, /*InsnID*/0, /*Opcode*/GIMT_Encode2(AMDGPU::FLAT_ATOMIC_SUB_RTN),
        GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/0, // DstI[vdst]
        GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/0, // vaddr
        GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/2, // data
        GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/1, // offset
        GIR_AddImm8, /*InsnID*/0, /*Imm*/1,
        GIR_MergeMemOperands, /*InsnID*/0, /*NumInsns*/1, /*MergeInsnID's*/0,
        GIR_ConstrainSelectedInstOperands, /*InsnID*/0,
        GIR_EraseFromParent, /*InsnID*/0,
        // GIR_Coverage, 2829,
        GIR_Done,
      // Label 2533: @165789
      GIM_Try, /*On fail goto*//*Label 2534*/ GIMT_Encode4(165854), // Rule ID 2881 //
        GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasFlatAddressSpace),
        GIM_CheckMemoryAddressSpace, /*MI*/0, /*MMO*/0, /*NumAddrSpace*/3, /*AddrSpace*/1, /*AddrSpace*/4, /*AddrSpace*/6,
        GIM_CheckRegBankForClass, /*MI*/0, /*Op*/0, /*RC*/GIMT_Encode2(AMDGPU::AV_32RegClassID),
        GIM_CheckPointerToAny, /*MI*/0, /*Op*/1, /*SizeInBits*/0,
        GIM_CheckComplexPattern, /*MI*/0, /*Op*/1, /*Renderer*/GIMT_Encode2(0), GIMT_Encode2(GICP_gi_flat_offset),
        // (atomic_load_sub:{ *:[i32] } (FlatOffset:{ *:[iPTR] } i64:{ *:[i64] }:$vaddr, i32:{ *:[i32] }:$offset), i32:{ *:[i32] }:$data)<<P:Predicate_atomic_load_sub_global_32>>  =>  (FLAT_ATOMIC_SUB_RTN:{ *:[i32] } VReg_64:{ *:[i64] }:$vaddr, anonymous_15037:{ *:[i32] }:$data, ?:{ *:[i32] }:$offset)
        GIR_BuildMI, /*InsnID*/0, /*Opcode*/GIMT_Encode2(AMDGPU::FLAT_ATOMIC_SUB_RTN),
        GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/0, // DstI[vdst]
        GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/0, // vaddr
        GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/2, // data
        GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/1, // offset
        GIR_AddImm8, /*InsnID*/0, /*Imm*/1,
        GIR_MergeMemOperands, /*InsnID*/0, /*NumInsns*/1, /*MergeInsnID's*/0,
        GIR_ConstrainSelectedInstOperands, /*InsnID*/0,
        GIR_EraseFromParent, /*InsnID*/0,
        // GIR_Coverage, 2881,
        GIR_Done,
      // Label 2534: @165854
      GIM_Reject,
    // Label 2512: @165855
    GIM_Reject,
    // Label 2510: @165856
    GIM_Try, /*On fail goto*//*Label 2535*/ GIMT_Encode4(167267),
      GIM_CheckType, /*MI*/0, /*Op*/2, /*Type*/GILLT_s64,
      GIM_Try, /*On fail goto*//*Label 2536*/ GIMT_Encode4(165933), // Rule ID 4622 //
        GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasUnrestrictedSOffset),
        GIM_CheckMemoryAddressSpace, /*MI*/0, /*MMO*/0, /*NumAddrSpace*/3, /*AddrSpace*/1, /*AddrSpace*/4, /*AddrSpace*/6,
        GIM_CheckHasNoUse, /*MI*/0,
        GIM_CheckPointerToAny, /*MI*/0, /*Op*/1, /*SizeInBits*/0,
        GIM_CheckComplexPattern, /*MI*/0, /*Op*/1, /*Renderer*/GIMT_Encode2(0), GIMT_Encode2(GICP_gi_mubuf_addr64),
        // (atomic_load_sub:{ *:[i64] } (MUBUFAddr64:{ *:[iPTR] } v4i32:{ *:[v4i32] }:$srsrc, i64:{ *:[i64] }:$vaddr, i32:{ *:[i32] }:$soffset, i32:{ *:[i32] }:$offset), i64:{ *:[i64] }:$vdata_in)<<P:Predicate_atomic_load_sub_global_noret_64>>  =>  (BUFFER_ATOMIC_SUB_X2_ADDR64 anonymous_15036:{ *:[i64] }:$vdata_in, VReg_64:{ *:[i64] }:$vaddr, SReg_128:{ *:[v4i32] }:$srsrc, SCSrc_b32:{ *:[i32] }:$soffset, offset:{ *:[i32] }:$offset)
        GIR_BuildMI, /*InsnID*/0, /*Opcode*/GIMT_Encode2(AMDGPU::BUFFER_ATOMIC_SUB_X2_ADDR64),
        GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/2, // vdata_in
        GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/1, // vaddr
        GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/0, // srsrc
        GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/2, // soffset
        GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/3, // offset
        GIR_AddImm8, /*InsnID*/0, /*Imm*/0,
        GIR_MergeMemOperands, /*InsnID*/0, /*NumInsns*/1, /*MergeInsnID's*/0,
        GIR_ConstrainSelectedInstOperands, /*InsnID*/0,
        GIR_EraseFromParent, /*InsnID*/0,
        // GIR_Coverage, 4622,
        GIR_Done,
      // Label 2536: @165933
      GIM_Try, /*On fail goto*//*Label 2537*/ GIMT_Encode4(165998), // Rule ID 4626 //
        GIM_CheckMemoryAddressSpace, /*MI*/0, /*MMO*/0, /*NumAddrSpace*/3, /*AddrSpace*/1, /*AddrSpace*/4, /*AddrSpace*/6,
        GIM_CheckHasNoUse, /*MI*/0,
        GIM_CheckPointerToAny, /*MI*/0, /*Op*/1, /*SizeInBits*/0,
        GIM_CheckComplexPattern, /*MI*/0, /*Op*/1, /*Renderer*/GIMT_Encode2(0), GIMT_Encode2(GICP_gi_mubuf_addr64),
        // (atomic_load_sub:{ *:[i64] } (MUBUFAddr64:{ *:[iPTR] } v4i32:{ *:[v4i32] }:$srsrc, i64:{ *:[i64] }:$vaddr, i32:{ *:[i32] }:$soffset, i32:{ *:[i32] }:$offset), i64:{ *:[i64] }:$vdata_in)<<P:Predicate_atomic_load_sub_global_noret_64>>  =>  (BUFFER_ATOMIC_SUB_X2_VBUFFER_ADDR64 anonymous_15036:{ *:[i64] }:$vdata_in, VReg_64:{ *:[i64] }:$vaddr, SReg_128:{ *:[v4i32] }:$srsrc, SCSrc_b32:{ *:[i32] }:$soffset, offset:{ *:[i32] }:$offset)
        GIR_BuildMI, /*InsnID*/0, /*Opcode*/GIMT_Encode2(AMDGPU::BUFFER_ATOMIC_SUB_X2_VBUFFER_ADDR64),
        GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/2, // vdata_in
        GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/1, // vaddr
        GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/0, // srsrc
        GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/2, // soffset
        GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/3, // offset
        GIR_AddImm8, /*InsnID*/0, /*Imm*/0,
        GIR_MergeMemOperands, /*InsnID*/0, /*NumInsns*/1, /*MergeInsnID's*/0,
        GIR_ConstrainSelectedInstOperands, /*InsnID*/0,
        GIR_EraseFromParent, /*InsnID*/0,
        // GIR_Coverage, 4626,
        GIR_Done,
      // Label 2537: @165998
      GIM_Try, /*On fail goto*//*Label 2538*/ GIMT_Encode4(166073), // Rule ID 4620 //
        GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasUnrestrictedSOffset),
        GIM_CheckMemoryAddressSpace, /*MI*/0, /*MMO*/0, /*NumAddrSpace*/3, /*AddrSpace*/1, /*AddrSpace*/4, /*AddrSpace*/6,
        GIM_CheckRegBankForClass, /*MI*/0, /*Op*/0, /*RC*/GIMT_Encode2(AMDGPU::AV_64RegClassID),
        GIM_CheckPointerToAny, /*MI*/0, /*Op*/1, /*SizeInBits*/0,
        GIM_CheckComplexPattern, /*MI*/0, /*Op*/1, /*Renderer*/GIMT_Encode2(0), GIMT_Encode2(GICP_gi_mubuf_addr64),
        // (atomic_load_sub:{ *:[i64] } (MUBUFAddr64:{ *:[iPTR] } v4i32:{ *:[v4i32] }:$srsrc, i64:{ *:[i64] }:$vaddr, i32:{ *:[i32] }:$soffset, i32:{ *:[i32] }:$offset), i64:{ *:[i64] }:$vdata_in)<<P:Predicate_atomic_load_sub_global_64>>  =>  (BUFFER_ATOMIC_SUB_X2_ADDR64_RTN:{ *:[i64] } anonymous_15036:{ *:[i64] }:$vdata_in, VReg_64:{ *:[i64] }:$vaddr, SReg_128:{ *:[v4i32] }:$srsrc, SCSrc_b32:{ *:[i32] }:$soffset, offset:{ *:[i32] }:$offset)
        GIR_BuildMI, /*InsnID*/0, /*Opcode*/GIMT_Encode2(AMDGPU::BUFFER_ATOMIC_SUB_X2_ADDR64_RTN),
        GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/0, // DstI[vdata]
        GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/2, // vdata_in
        GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/1, // vaddr
        GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/0, // srsrc
        GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/2, // soffset
        GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/3, // offset
        GIR_AddImm8, /*InsnID*/0, /*Imm*/1,
        GIR_MergeMemOperands, /*InsnID*/0, /*NumInsns*/1, /*MergeInsnID's*/0,
        GIR_ConstrainSelectedInstOperands, /*InsnID*/0,
        GIR_EraseFromParent, /*InsnID*/0,
        // GIR_Coverage, 4620,
        GIR_Done,
      // Label 2538: @166073
      GIM_Try, /*On fail goto*//*Label 2539*/ GIMT_Encode4(166145), // Rule ID 4624 //
        GIM_CheckMemoryAddressSpace, /*MI*/0, /*MMO*/0, /*NumAddrSpace*/3, /*AddrSpace*/1, /*AddrSpace*/4, /*AddrSpace*/6,
        GIM_CheckRegBankForClass, /*MI*/0, /*Op*/0, /*RC*/GIMT_Encode2(AMDGPU::AV_64RegClassID),
        GIM_CheckPointerToAny, /*MI*/0, /*Op*/1, /*SizeInBits*/0,
        GIM_CheckComplexPattern, /*MI*/0, /*Op*/1, /*Renderer*/GIMT_Encode2(0), GIMT_Encode2(GICP_gi_mubuf_addr64),
        // (atomic_load_sub:{ *:[i64] } (MUBUFAddr64:{ *:[iPTR] } v4i32:{ *:[v4i32] }:$srsrc, i64:{ *:[i64] }:$vaddr, i32:{ *:[i32] }:$soffset, i32:{ *:[i32] }:$offset), i64:{ *:[i64] }:$vdata_in)<<P:Predicate_atomic_load_sub_global_64>>  =>  (BUFFER_ATOMIC_SUB_X2_VBUFFER_ADDR64_RTN:{ *:[i64] } anonymous_15036:{ *:[i64] }:$vdata_in, VReg_64:{ *:[i64] }:$vaddr, SReg_128:{ *:[v4i32] }:$srsrc, SCSrc_b32:{ *:[i32] }:$soffset, offset:{ *:[i32] }:$offset)
        GIR_BuildMI, /*InsnID*/0, /*Opcode*/GIMT_Encode2(AMDGPU::BUFFER_ATOMIC_SUB_X2_VBUFFER_ADDR64_RTN),
        GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/0, // DstI[vdata]
        GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/2, // vdata_in
        GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/1, // vaddr
        GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/0, // srsrc
        GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/2, // soffset
        GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/3, // offset
        GIR_AddImm8, /*InsnID*/0, /*Imm*/1,
        GIR_MergeMemOperands, /*InsnID*/0, /*NumInsns*/1, /*MergeInsnID's*/0,
        GIR_ConstrainSelectedInstOperands, /*InsnID*/0,
        GIR_EraseFromParent, /*InsnID*/0,
        // GIR_Coverage, 4624,
        GIR_Done,
      // Label 2539: @166145
      GIM_Try, /*On fail goto*//*Label 2540*/ GIMT_Encode4(166208), // Rule ID 4621 //
        GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasUnrestrictedSOffset),
        GIM_CheckMemoryAddressSpace, /*MI*/0, /*MMO*/0, /*NumAddrSpace*/3, /*AddrSpace*/1, /*AddrSpace*/4, /*AddrSpace*/6,
        GIM_CheckHasNoUse, /*MI*/0,
        GIM_CheckPointerToAny, /*MI*/0, /*Op*/1, /*SizeInBits*/0,
        GIM_CheckComplexPattern, /*MI*/0, /*Op*/1, /*Renderer*/GIMT_Encode2(0), GIMT_Encode2(GICP_gi_mubuf_offset),
        // (atomic_load_sub:{ *:[i64] } (MUBUFOffset:{ *:[iPTR] } v4i32:{ *:[v4i32] }:$srsrc, i32:{ *:[i32] }:$soffset, i32:{ *:[i32] }:$offset), i64:{ *:[i64] }:$vdata_in)<<P:Predicate_atomic_load_sub_global_noret_64>>  =>  (BUFFER_ATOMIC_SUB_X2_OFFSET anonymous_15036:{ *:[i64] }:$vdata_in, SReg_128:{ *:[v4i32] }:$srsrc, SCSrc_b32:{ *:[i32] }:$soffset, offset:{ *:[i32] }:$offset)
        GIR_BuildMI, /*InsnID*/0, /*Opcode*/GIMT_Encode2(AMDGPU::BUFFER_ATOMIC_SUB_X2_OFFSET),
        GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/2, // vdata_in
        GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/0, // srsrc
        GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/1, // soffset
        GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/2, // offset
        GIR_AddImm8, /*InsnID*/0, /*Imm*/0,
        GIR_MergeMemOperands, /*InsnID*/0, /*NumInsns*/1, /*MergeInsnID's*/0,
        GIR_ConstrainSelectedInstOperands, /*InsnID*/0,
        GIR_EraseFromParent, /*InsnID*/0,
        // GIR_Coverage, 4621,
        GIR_Done,
      // Label 2540: @166208
      GIM_Try, /*On fail goto*//*Label 2541*/ GIMT_Encode4(166268), // Rule ID 4625 //
        GIM_CheckMemoryAddressSpace, /*MI*/0, /*MMO*/0, /*NumAddrSpace*/3, /*AddrSpace*/1, /*AddrSpace*/4, /*AddrSpace*/6,
        GIM_CheckHasNoUse, /*MI*/0,
        GIM_CheckPointerToAny, /*MI*/0, /*Op*/1, /*SizeInBits*/0,
        GIM_CheckComplexPattern, /*MI*/0, /*Op*/1, /*Renderer*/GIMT_Encode2(0), GIMT_Encode2(GICP_gi_mubuf_offset),
        // (atomic_load_sub:{ *:[i64] } (MUBUFOffset:{ *:[iPTR] } v4i32:{ *:[v4i32] }:$srsrc, i32:{ *:[i32] }:$soffset, i32:{ *:[i32] }:$offset), i64:{ *:[i64] }:$vdata_in)<<P:Predicate_atomic_load_sub_global_noret_64>>  =>  (BUFFER_ATOMIC_SUB_X2_VBUFFER_OFFSET anonymous_15036:{ *:[i64] }:$vdata_in, SReg_128:{ *:[v4i32] }:$srsrc, SCSrc_b32:{ *:[i32] }:$soffset, offset:{ *:[i32] }:$offset)
        GIR_BuildMI, /*InsnID*/0, /*Opcode*/GIMT_Encode2(AMDGPU::BUFFER_ATOMIC_SUB_X2_VBUFFER_OFFSET),
        GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/2, // vdata_in
        GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/0, // srsrc
        GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/1, // soffset
        GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/2, // offset
        GIR_AddImm8, /*InsnID*/0, /*Imm*/0,
        GIR_MergeMemOperands, /*InsnID*/0, /*NumInsns*/1, /*MergeInsnID's*/0,
        GIR_ConstrainSelectedInstOperands, /*InsnID*/0,
        GIR_EraseFromParent, /*InsnID*/0,
        // GIR_Coverage, 4625,
        GIR_Done,
      // Label 2541: @166268
      GIM_Try, /*On fail goto*//*Label 2542*/ GIMT_Encode4(166338), // Rule ID 4619 //
        GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasUnrestrictedSOffset),
        GIM_CheckMemoryAddressSpace, /*MI*/0, /*MMO*/0, /*NumAddrSpace*/3, /*AddrSpace*/1, /*AddrSpace*/4, /*AddrSpace*/6,
        GIM_CheckRegBankForClass, /*MI*/0, /*Op*/0, /*RC*/GIMT_Encode2(AMDGPU::AV_64RegClassID),
        GIM_CheckPointerToAny, /*MI*/0, /*Op*/1, /*SizeInBits*/0,
        GIM_CheckComplexPattern, /*MI*/0, /*Op*/1, /*Renderer*/GIMT_Encode2(0), GIMT_Encode2(GICP_gi_mubuf_offset),
        // (atomic_load_sub:{ *:[i64] } (MUBUFOffset:{ *:[iPTR] } v4i32:{ *:[v4i32] }:$srsrc, i32:{ *:[i32] }:$soffset, i32:{ *:[i32] }:$offset), i64:{ *:[i64] }:$vdata_in)<<P:Predicate_atomic_load_sub_global_64>>  =>  (BUFFER_ATOMIC_SUB_X2_OFFSET_RTN:{ *:[i64] } anonymous_15036:{ *:[i64] }:$vdata_in, SReg_128:{ *:[v4i32] }:$srsrc, SCSrc_b32:{ *:[i32] }:$soffset, offset:{ *:[i32] }:$offset)
        GIR_BuildMI, /*InsnID*/0, /*Opcode*/GIMT_Encode2(AMDGPU::BUFFER_ATOMIC_SUB_X2_OFFSET_RTN),
        GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/0, // DstI[vdata]
        GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/2, // vdata_in
        GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/0, // srsrc
        GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/1, // soffset
        GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/2, // offset
        GIR_AddImm8, /*InsnID*/0, /*Imm*/1,
        GIR_MergeMemOperands, /*InsnID*/0, /*NumInsns*/1, /*MergeInsnID's*/0,
        GIR_ConstrainSelectedInstOperands, /*InsnID*/0,
        GIR_EraseFromParent, /*InsnID*/0,
        // GIR_Coverage, 4619,
        GIR_Done,
      // Label 2542: @166338
      GIM_Try, /*On fail goto*//*Label 2543*/ GIMT_Encode4(166405), // Rule ID 4623 //
        GIM_CheckMemoryAddressSpace, /*MI*/0, /*MMO*/0, /*NumAddrSpace*/3, /*AddrSpace*/1, /*AddrSpace*/4, /*AddrSpace*/6,
        GIM_CheckRegBankForClass, /*MI*/0, /*Op*/0, /*RC*/GIMT_Encode2(AMDGPU::AV_64RegClassID),
        GIM_CheckPointerToAny, /*MI*/0, /*Op*/1, /*SizeInBits*/0,
        GIM_CheckComplexPattern, /*MI*/0, /*Op*/1, /*Renderer*/GIMT_Encode2(0), GIMT_Encode2(GICP_gi_mubuf_offset),
        // (atomic_load_sub:{ *:[i64] } (MUBUFOffset:{ *:[iPTR] } v4i32:{ *:[v4i32] }:$srsrc, i32:{ *:[i32] }:$soffset, i32:{ *:[i32] }:$offset), i64:{ *:[i64] }:$vdata_in)<<P:Predicate_atomic_load_sub_global_64>>  =>  (BUFFER_ATOMIC_SUB_X2_VBUFFER_OFFSET_RTN:{ *:[i64] } anonymous_15036:{ *:[i64] }:$vdata_in, SReg_128:{ *:[v4i32] }:$srsrc, SCSrc_b32:{ *:[i32] }:$soffset, offset:{ *:[i32] }:$offset)
        GIR_BuildMI, /*InsnID*/0, /*Opcode*/GIMT_Encode2(AMDGPU::BUFFER_ATOMIC_SUB_X2_VBUFFER_OFFSET_RTN),
        GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/0, // DstI[vdata]
        GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/2, // vdata_in
        GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/0, // srsrc
        GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/1, // soffset
        GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/2, // offset
        GIR_AddImm8, /*InsnID*/0, /*Imm*/1,
        GIR_MergeMemOperands, /*InsnID*/0, /*NumInsns*/1, /*MergeInsnID's*/0,
        GIR_ConstrainSelectedInstOperands, /*InsnID*/0,
        GIR_EraseFromParent, /*InsnID*/0,
        // GIR_Coverage, 4623,
        GIR_Done,
      // Label 2543: @166405
      GIM_Try, /*On fail goto*//*Label 2544*/ GIMT_Encode4(166461), // Rule ID 6998 //
        GIM_CheckFeatures, GIMT_Encode2(GIFBS_LDSRequiresM0Init),
        GIM_CheckMemoryAddressSpace, /*MI*/0, /*MMO*/0, /*NumAddrSpace*/1, /*AddrSpace*/3,
        GIM_CheckHasNoUse, /*MI*/0,
        GIM_CheckPointerToAny, /*MI*/0, /*Op*/1, /*SizeInBits*/0,
        GIM_CheckComplexPattern, /*MI*/0, /*Op*/1, /*Renderer*/GIMT_Encode2(0), GIMT_Encode2(GICP_gi_ds_1addr_1offset),
        // (atomic_load_sub_glue:{ *:[i64] } (DS1Addr1Offset:{ *:[iPTR] } i32:{ *:[i32] }:$ptr, i32:{ *:[i32] }:$offset), i64:{ *:[i64] }:$value)<<P:Predicate_atomic_load_sub_local_m0_noret_64>>  =>  (DS_SUB_U64 ?:{ *:[i32] }:$ptr, anonymous_15036:{ *:[i64] }:$value, offset:{ *:[i32] }:$offset, 0:{ *:[i1] })
        GIR_BuildMI, /*InsnID*/0, /*Opcode*/GIMT_Encode2(AMDGPU::DS_SUB_U64),
        GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/0, // ptr
        GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/2, // value
        GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/1, // offset
        GIR_AddImm8, /*InsnID*/0, /*Imm*/0,
        GIR_MergeMemOperands, /*InsnID*/0, /*NumInsns*/1, /*MergeInsnID's*/0,
        GIR_ConstrainSelectedInstOperands, /*InsnID*/0,
        GIR_EraseFromParent, /*InsnID*/0,
        // GIR_Coverage, 6998,
        GIR_Done,
      // Label 2544: @166461
      GIM_Try, /*On fail goto*//*Label 2545*/ GIMT_Encode4(166517), // Rule ID 7000 //
        GIM_CheckFeatures, GIMT_Encode2(GIFBS_NotLDSRequiresM0Init),
        GIM_CheckMemoryAddressSpace, /*MI*/0, /*MMO*/0, /*NumAddrSpace*/1, /*AddrSpace*/3,
        GIM_CheckHasNoUse, /*MI*/0,
        GIM_CheckPointerToAny, /*MI*/0, /*Op*/1, /*SizeInBits*/0,
        GIM_CheckComplexPattern, /*MI*/0, /*Op*/1, /*Renderer*/GIMT_Encode2(0), GIMT_Encode2(GICP_gi_ds_1addr_1offset),
        // (atomic_load_sub:{ *:[i64] } (DS1Addr1Offset:{ *:[iPTR] } i32:{ *:[i32] }:$ptr, i32:{ *:[i32] }:$offset), i64:{ *:[i64] }:$value)<<P:Predicate_atomic_load_sub_local_noret_64>>  =>  (DS_SUB_U64_gfx9 ?:{ *:[i32] }:$ptr, anonymous_15036:{ *:[i64] }:$value, offset:{ *:[i32] }:$offset, 0:{ *:[i1] })
        GIR_BuildMI, /*InsnID*/0, /*Opcode*/GIMT_Encode2(AMDGPU::DS_SUB_U64_gfx9),
        GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/0, // ptr
        GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/2, // value
        GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/1, // offset
        GIR_AddImm8, /*InsnID*/0, /*Imm*/0,
        GIR_MergeMemOperands, /*InsnID*/0, /*NumInsns*/1, /*MergeInsnID's*/0,
        GIR_ConstrainSelectedInstOperands, /*InsnID*/0,
        GIR_EraseFromParent, /*InsnID*/0,
        // GIR_Coverage, 7000,
        GIR_Done,
      // Label 2545: @166517
      GIM_Try, /*On fail goto*//*Label 2546*/ GIMT_Encode4(166573), // Rule ID 7002 //
        GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasGDS),
        GIM_CheckMemoryAddressSpace, /*MI*/0, /*MMO*/0, /*NumAddrSpace*/1, /*AddrSpace*/2,
        GIM_CheckHasNoUse, /*MI*/0,
        GIM_CheckPointerToAny, /*MI*/0, /*Op*/1, /*SizeInBits*/0,
        GIM_CheckComplexPattern, /*MI*/0, /*Op*/1, /*Renderer*/GIMT_Encode2(0), GIMT_Encode2(GICP_gi_ds_1addr_1offset),
        // (atomic_load_sub_glue:{ *:[i64] } (DS1Addr1Offset:{ *:[iPTR] } i32:{ *:[i32] }:$ptr, i32:{ *:[i32] }:$offset), i64:{ *:[i64] }:$value)<<P:Predicate_atomic_load_sub_region_m0_noret_64>>  =>  (DS_SUB_U64 ?:{ *:[i32] }:$ptr, anonymous_15036:{ *:[i64] }:$value, offset:{ *:[i32] }:$offset, 1:{ *:[i1] })
        GIR_BuildMI, /*InsnID*/0, /*Opcode*/GIMT_Encode2(AMDGPU::DS_SUB_U64),
        GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/0, // ptr
        GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/2, // value
        GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/1, // offset
        GIR_AddImm8, /*InsnID*/0, /*Imm*/1,
        GIR_MergeMemOperands, /*InsnID*/0, /*NumInsns*/1, /*MergeInsnID's*/0,
        GIR_ConstrainSelectedInstOperands, /*InsnID*/0,
        GIR_EraseFromParent, /*InsnID*/0,
        // GIR_Coverage, 7002,
        GIR_Done,
      // Label 2546: @166573
      GIM_Try, /*On fail goto*//*Label 2547*/ GIMT_Encode4(166636), // Rule ID 6997 //
        GIM_CheckFeatures, GIMT_Encode2(GIFBS_LDSRequiresM0Init),
        GIM_CheckMemoryAddressSpace, /*MI*/0, /*MMO*/0, /*NumAddrSpace*/1, /*AddrSpace*/3,
        GIM_CheckRegBankForClass, /*MI*/0, /*Op*/0, /*RC*/GIMT_Encode2(AMDGPU::AV_64RegClassID),
        GIM_CheckPointerToAny, /*MI*/0, /*Op*/1, /*SizeInBits*/0,
        GIM_CheckComplexPattern, /*MI*/0, /*Op*/1, /*Renderer*/GIMT_Encode2(0), GIMT_Encode2(GICP_gi_ds_1addr_1offset),
        // (atomic_load_sub_glue:{ *:[i64] } (DS1Addr1Offset:{ *:[iPTR] } i32:{ *:[i32] }:$ptr, i32:{ *:[i32] }:$offset), i64:{ *:[i64] }:$value)<<P:Predicate_atomic_load_sub_local_m0_64>>  =>  (DS_SUB_RTN_U64:{ *:[i64] } ?:{ *:[i32] }:$ptr, anonymous_15036:{ *:[i64] }:$value, offset:{ *:[i32] }:$offset, 0:{ *:[i1] })
        GIR_BuildMI, /*InsnID*/0, /*Opcode*/GIMT_Encode2(AMDGPU::DS_SUB_RTN_U64),
        GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/0, // DstI[vdst]
        GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/0, // ptr
        GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/2, // value
        GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/1, // offset
        GIR_AddImm8, /*InsnID*/0, /*Imm*/0,
        GIR_MergeMemOperands, /*InsnID*/0, /*NumInsns*/1, /*MergeInsnID's*/0,
        GIR_ConstrainSelectedInstOperands, /*InsnID*/0,
        GIR_EraseFromParent, /*InsnID*/0,
        // GIR_Coverage, 6997,
        GIR_Done,
      // Label 2547: @166636
      GIM_Try, /*On fail goto*//*Label 2548*/ GIMT_Encode4(166699), // Rule ID 6999 //
        GIM_CheckFeatures, GIMT_Encode2(GIFBS_NotLDSRequiresM0Init),
        GIM_CheckMemoryAddressSpace, /*MI*/0, /*MMO*/0, /*NumAddrSpace*/1, /*AddrSpace*/3,
        GIM_CheckRegBankForClass, /*MI*/0, /*Op*/0, /*RC*/GIMT_Encode2(AMDGPU::AV_64RegClassID),
        GIM_CheckPointerToAny, /*MI*/0, /*Op*/1, /*SizeInBits*/0,
        GIM_CheckComplexPattern, /*MI*/0, /*Op*/1, /*Renderer*/GIMT_Encode2(0), GIMT_Encode2(GICP_gi_ds_1addr_1offset),
        // (atomic_load_sub:{ *:[i64] } (DS1Addr1Offset:{ *:[iPTR] } i32:{ *:[i32] }:$ptr, i32:{ *:[i32] }:$offset), i64:{ *:[i64] }:$value)<<P:Predicate_atomic_load_sub_local_64>>  =>  (DS_SUB_RTN_U64_gfx9:{ *:[i64] } ?:{ *:[i32] }:$ptr, anonymous_15036:{ *:[i64] }:$value, offset:{ *:[i32] }:$offset, 0:{ *:[i1] })
        GIR_BuildMI, /*InsnID*/0, /*Opcode*/GIMT_Encode2(AMDGPU::DS_SUB_RTN_U64_gfx9),
        GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/0, // DstI[vdst]
        GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/0, // ptr
        GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/2, // value
        GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/1, // offset
        GIR_AddImm8, /*InsnID*/0, /*Imm*/0,
        GIR_MergeMemOperands, /*InsnID*/0, /*NumInsns*/1, /*MergeInsnID's*/0,
        GIR_ConstrainSelectedInstOperands, /*InsnID*/0,
        GIR_EraseFromParent, /*InsnID*/0,
        // GIR_Coverage, 6999,
        GIR_Done,
      // Label 2548: @166699
      GIM_Try, /*On fail goto*//*Label 2549*/ GIMT_Encode4(166762), // Rule ID 7001 //
        GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasGDS),
        GIM_CheckMemoryAddressSpace, /*MI*/0, /*MMO*/0, /*NumAddrSpace*/1, /*AddrSpace*/2,
        GIM_CheckRegBankForClass, /*MI*/0, /*Op*/0, /*RC*/GIMT_Encode2(AMDGPU::AV_64RegClassID),
        GIM_CheckPointerToAny, /*MI*/0, /*Op*/1, /*SizeInBits*/0,
        GIM_CheckComplexPattern, /*MI*/0, /*Op*/1, /*Renderer*/GIMT_Encode2(0), GIMT_Encode2(GICP_gi_ds_1addr_1offset),
        // (atomic_load_sub_glue:{ *:[i64] } (DS1Addr1Offset:{ *:[iPTR] } i32:{ *:[i32] }:$ptr, i32:{ *:[i32] }:$offset), i64:{ *:[i64] }:$value)<<P:Predicate_atomic_load_sub_region_m0_64>>  =>  (DS_SUB_RTN_U64:{ *:[i64] } ?:{ *:[i32] }:$ptr, anonymous_15036:{ *:[i64] }:$value, offset:{ *:[i32] }:$offset, 1:{ *:[i1] })
        GIR_BuildMI, /*InsnID*/0, /*Opcode*/GIMT_Encode2(AMDGPU::DS_SUB_RTN_U64),
        GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/0, // DstI[vdst]
        GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/0, // ptr
        GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/2, // value
        GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/1, // offset
        GIR_AddImm8, /*InsnID*/0, /*Imm*/1,
        GIR_MergeMemOperands, /*InsnID*/0, /*NumInsns*/1, /*MergeInsnID's*/0,
        GIR_ConstrainSelectedInstOperands, /*InsnID*/0,
        GIR_EraseFromParent, /*InsnID*/0,
        // GIR_Coverage, 7001,
        GIR_Done,
      // Label 2549: @166762
      GIM_Try, /*On fail goto*//*Label 2550*/ GIMT_Encode4(166825), // Rule ID 3207 //
        GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasFlatGlobalInsts),
        GIM_CheckMemoryAddressSpace, /*MI*/0, /*MMO*/0, /*NumAddrSpace*/3, /*AddrSpace*/1, /*AddrSpace*/4, /*AddrSpace*/6,
        GIM_CheckHasNoUse, /*MI*/0,
        GIM_CheckPointerToAny, /*MI*/0, /*Op*/1, /*SizeInBits*/0,
        GIM_CheckComplexPattern, /*MI*/0, /*Op*/1, /*Renderer*/GIMT_Encode2(0), GIMT_Encode2(GICP_gi_global_saddr),
        // (atomic_load_sub:{ *:[i64] } (GlobalSAddr:{ *:[iPTR] } SReg_64:{ *:[i64] }:$saddr, VGPR_32:{ *:[i32] }:$voffset, i32:{ *:[i32] }:$offset), i64:{ *:[i64] }:$data)<<P:Predicate_atomic_load_sub_global_noret_64>>  =>  (GLOBAL_ATOMIC_SUB_X2_SADDR ?:{ *:[i32] }:$voffset, anonymous_15036:{ *:[i64] }:$data, ?:{ *:[i64] }:$saddr, ?:{ *:[i32] }:$offset)
        GIR_BuildMI, /*InsnID*/0, /*Opcode*/GIMT_Encode2(AMDGPU::GLOBAL_ATOMIC_SUB_X2_SADDR),
        GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/1, // voffset
        GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/2, // data
        GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/0, // saddr
        GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/2, // offset
        GIR_AddImm8, /*InsnID*/0, /*Imm*/0,
        GIR_MergeMemOperands, /*InsnID*/0, /*NumInsns*/1, /*MergeInsnID's*/0,
        GIR_ConstrainSelectedInstOperands, /*InsnID*/0,
        GIR_EraseFromParent, /*InsnID*/0,
        // GIR_Coverage, 3207,
        GIR_Done,
      // Label 2550: @166825
      GIM_Try, /*On fail goto*//*Label 2551*/ GIMT_Encode4(166895), // Rule ID 3209 //
        GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasFlatGlobalInsts),
        GIM_CheckMemoryAddressSpace, /*MI*/0, /*MMO*/0, /*NumAddrSpace*/3, /*AddrSpace*/1, /*AddrSpace*/4, /*AddrSpace*/6,
        GIM_CheckRegBankForClass, /*MI*/0, /*Op*/0, /*RC*/GIMT_Encode2(AMDGPU::AV_64RegClassID),
        GIM_CheckPointerToAny, /*MI*/0, /*Op*/1, /*SizeInBits*/0,
        GIM_CheckComplexPattern, /*MI*/0, /*Op*/1, /*Renderer*/GIMT_Encode2(0), GIMT_Encode2(GICP_gi_global_saddr),
        // (atomic_load_sub:{ *:[i64] } (GlobalSAddr:{ *:[iPTR] } SReg_64:{ *:[i64] }:$saddr, VGPR_32:{ *:[i32] }:$voffset, i32:{ *:[i32] }:$offset), i64:{ *:[i64] }:$data)<<P:Predicate_atomic_load_sub_global_64>>  =>  (GLOBAL_ATOMIC_SUB_X2_SADDR_RTN:{ *:[i64] } ?:{ *:[i32] }:$voffset, anonymous_15036:{ *:[i64] }:$data, ?:{ *:[i64] }:$saddr, ?:{ *:[i32] }:$offset)
        GIR_BuildMI, /*InsnID*/0, /*Opcode*/GIMT_Encode2(AMDGPU::GLOBAL_ATOMIC_SUB_X2_SADDR_RTN),
        GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/0, // DstI[vdst]
        GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/1, // voffset
        GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/2, // data
        GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/0, // saddr
        GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/2, // offset
        GIR_AddImm8, /*InsnID*/0, /*Imm*/1,
        GIR_MergeMemOperands, /*InsnID*/0, /*NumInsns*/1, /*MergeInsnID's*/0,
        GIR_ConstrainSelectedInstOperands, /*InsnID*/0,
        GIR_EraseFromParent, /*InsnID*/0,
        // GIR_Coverage, 3209,
        GIR_Done,
      // Label 2551: @166895
      GIM_Try, /*On fail goto*//*Label 2552*/ GIMT_Encode4(166953), // Rule ID 3206 //
        GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasFlatGlobalInsts),
        GIM_CheckMemoryAddressSpace, /*MI*/0, /*MMO*/0, /*NumAddrSpace*/3, /*AddrSpace*/1, /*AddrSpace*/4, /*AddrSpace*/6,
        GIM_CheckHasNoUse, /*MI*/0,
        GIM_CheckPointerToAny, /*MI*/0, /*Op*/1, /*SizeInBits*/0,
        GIM_CheckComplexPattern, /*MI*/0, /*Op*/1, /*Renderer*/GIMT_Encode2(0), GIMT_Encode2(GICP_gi_global_offset),
        // (atomic_load_sub:{ *:[i64] } (GlobalOffset:{ *:[iPTR] } i64:{ *:[i64] }:$vaddr, i32:{ *:[i32] }:$offset), i64:{ *:[i64] }:$data)<<P:Predicate_atomic_load_sub_global_noret_64>>  =>  (GLOBAL_ATOMIC_SUB_X2 VReg_64:{ *:[i64] }:$vaddr, anonymous_15036:{ *:[i64] }:$data, ?:{ *:[i32] }:$offset)
        GIR_BuildMI, /*InsnID*/0, /*Opcode*/GIMT_Encode2(AMDGPU::GLOBAL_ATOMIC_SUB_X2),
        GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/0, // vaddr
        GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/2, // data
        GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/1, // offset
        GIR_AddImm8, /*InsnID*/0, /*Imm*/0,
        GIR_MergeMemOperands, /*InsnID*/0, /*NumInsns*/1, /*MergeInsnID's*/0,
        GIR_ConstrainSelectedInstOperands, /*InsnID*/0,
        GIR_EraseFromParent, /*InsnID*/0,
        // GIR_Coverage, 3206,
        GIR_Done,
      // Label 2552: @166953
      GIM_Try, /*On fail goto*//*Label 2553*/ GIMT_Encode4(167018), // Rule ID 3208 //
        GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasFlatGlobalInsts),
        GIM_CheckMemoryAddressSpace, /*MI*/0, /*MMO*/0, /*NumAddrSpace*/3, /*AddrSpace*/1, /*AddrSpace*/4, /*AddrSpace*/6,
        GIM_CheckRegBankForClass, /*MI*/0, /*Op*/0, /*RC*/GIMT_Encode2(AMDGPU::AV_64RegClassID),
        GIM_CheckPointerToAny, /*MI*/0, /*Op*/1, /*SizeInBits*/0,
        GIM_CheckComplexPattern, /*MI*/0, /*Op*/1, /*Renderer*/GIMT_Encode2(0), GIMT_Encode2(GICP_gi_global_offset),
        // (atomic_load_sub:{ *:[i64] } (GlobalOffset:{ *:[iPTR] } i64:{ *:[i64] }:$vaddr, i32:{ *:[i32] }:$offset), i64:{ *:[i64] }:$data)<<P:Predicate_atomic_load_sub_global_64>>  =>  (GLOBAL_ATOMIC_SUB_X2_RTN:{ *:[i64] } VReg_64:{ *:[i64] }:$vaddr, anonymous_15036:{ *:[i64] }:$data, ?:{ *:[i32] }:$offset)
        GIR_BuildMI, /*InsnID*/0, /*Opcode*/GIMT_Encode2(AMDGPU::GLOBAL_ATOMIC_SUB_X2_RTN),
        GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/0, // DstI[vdst]
        GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/0, // vaddr
        GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/2, // data
        GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/1, // offset
        GIR_AddImm8, /*InsnID*/0, /*Imm*/1,
        GIR_MergeMemOperands, /*InsnID*/0, /*NumInsns*/1, /*MergeInsnID's*/0,
        GIR_ConstrainSelectedInstOperands, /*InsnID*/0,
        GIR_EraseFromParent, /*InsnID*/0,
        // GIR_Coverage, 3208,
        GIR_Done,
      // Label 2553: @167018
      GIM_Try, /*On fail goto*//*Label 2554*/ GIMT_Encode4(167077), // Rule ID 2856 //
        GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasFlatAddressSpace),
        GIM_CheckMemoryAddressSpace, /*MI*/0, /*MMO*/0, /*NumAddrSpace*/4, /*AddrSpace*/0, /*AddrSpace*/1, /*AddrSpace*/4, /*AddrSpace*/6,
        GIM_CheckHasNoUse, /*MI*/0,
        GIM_CheckPointerToAny, /*MI*/0, /*Op*/1, /*SizeInBits*/0,
        GIM_CheckComplexPattern, /*MI*/0, /*Op*/1, /*Renderer*/GIMT_Encode2(0), GIMT_Encode2(GICP_gi_flat_offset),
        // (atomic_load_sub:{ *:[i64] } (FlatOffset:{ *:[iPTR] } i64:{ *:[i64] }:$vaddr, i32:{ *:[i32] }:$offset), i64:{ *:[i64] }:$data)<<P:Predicate_atomic_load_sub_flat_noret_64>>  =>  (FLAT_ATOMIC_SUB_X2 VReg_64:{ *:[i64] }:$vaddr, anonymous_15036:{ *:[i64] }:$data, ?:{ *:[i32] }:$offset)
        GIR_BuildMI, /*InsnID*/0, /*Opcode*/GIMT_Encode2(AMDGPU::FLAT_ATOMIC_SUB_X2),
        GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/0, // vaddr
        GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/2, // data
        GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/1, // offset
        GIR_AddImm8, /*InsnID*/0, /*Imm*/0,
        GIR_MergeMemOperands, /*InsnID*/0, /*NumInsns*/1, /*MergeInsnID's*/0,
        GIR_ConstrainSelectedInstOperands, /*InsnID*/0,
        GIR_EraseFromParent, /*InsnID*/0,
        // GIR_Coverage, 2856,
        GIR_Done,
      // Label 2554: @167077
      GIM_Try, /*On fail goto*//*Label 2555*/ GIMT_Encode4(167135), // Rule ID 2908 //
        GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasFlatAddressSpace),
        GIM_CheckMemoryAddressSpace, /*MI*/0, /*MMO*/0, /*NumAddrSpace*/3, /*AddrSpace*/1, /*AddrSpace*/4, /*AddrSpace*/6,
        GIM_CheckHasNoUse, /*MI*/0,
        GIM_CheckPointerToAny, /*MI*/0, /*Op*/1, /*SizeInBits*/0,
        GIM_CheckComplexPattern, /*MI*/0, /*Op*/1, /*Renderer*/GIMT_Encode2(0), GIMT_Encode2(GICP_gi_flat_offset),
        // (atomic_load_sub:{ *:[i64] } (FlatOffset:{ *:[iPTR] } i64:{ *:[i64] }:$vaddr, i32:{ *:[i32] }:$offset), i64:{ *:[i64] }:$data)<<P:Predicate_atomic_load_sub_global_noret_64>>  =>  (FLAT_ATOMIC_SUB_X2 VReg_64:{ *:[i64] }:$vaddr, anonymous_15036:{ *:[i64] }:$data, ?:{ *:[i32] }:$offset)
        GIR_BuildMI, /*InsnID*/0, /*Opcode*/GIMT_Encode2(AMDGPU::FLAT_ATOMIC_SUB_X2),
        GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/0, // vaddr
        GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/2, // data
        GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/1, // offset
        GIR_AddImm8, /*InsnID*/0, /*Imm*/0,
        GIR_MergeMemOperands, /*InsnID*/0, /*NumInsns*/1, /*MergeInsnID's*/0,
        GIR_ConstrainSelectedInstOperands, /*InsnID*/0,
        GIR_EraseFromParent, /*InsnID*/0,
        // GIR_Coverage, 2908,
        GIR_Done,
      // Label 2555: @167135
      GIM_Try, /*On fail goto*//*Label 2556*/ GIMT_Encode4(167201), // Rule ID 2855 //
        GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasFlatAddressSpace),
        GIM_CheckMemoryAddressSpace, /*MI*/0, /*MMO*/0, /*NumAddrSpace*/4, /*AddrSpace*/0, /*AddrSpace*/1, /*AddrSpace*/4, /*AddrSpace*/6,
        GIM_CheckRegBankForClass, /*MI*/0, /*Op*/0, /*RC*/GIMT_Encode2(AMDGPU::AV_64RegClassID),
        GIM_CheckPointerToAny, /*MI*/0, /*Op*/1, /*SizeInBits*/0,
        GIM_CheckComplexPattern, /*MI*/0, /*Op*/1, /*Renderer*/GIMT_Encode2(0), GIMT_Encode2(GICP_gi_flat_offset),
        // (atomic_load_sub:{ *:[i64] } (FlatOffset:{ *:[iPTR] } i64:{ *:[i64] }:$vaddr, i32:{ *:[i32] }:$offset), i64:{ *:[i64] }:$data)<<P:Predicate_atomic_load_sub_flat_64>>  =>  (FLAT_ATOMIC_SUB_X2_RTN:{ *:[i64] } VReg_64:{ *:[i64] }:$vaddr, anonymous_15036:{ *:[i64] }:$data, ?:{ *:[i32] }:$offset)
        GIR_BuildMI, /*InsnID*/0, /*Opcode*/GIMT_Encode2(AMDGPU::FLAT_ATOMIC_SUB_X2_RTN),
        GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/0, // DstI[vdst]
        GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/0, // vaddr
        GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/2, // data
        GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/1, // offset
        GIR_AddImm8, /*InsnID*/0, /*Imm*/1,
        GIR_MergeMemOperands, /*InsnID*/0, /*NumInsns*/1, /*MergeInsnID's*/0,
        GIR_ConstrainSelectedInstOperands, /*InsnID*/0,
        GIR_EraseFromParent, /*InsnID*/0,
        // GIR_Coverage, 2855,
        GIR_Done,
      // Label 2556: @167201
      GIM_Try, /*On fail goto*//*Label 2557*/ GIMT_Encode4(167266), // Rule ID 2907 //
        GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasFlatAddressSpace),
        GIM_CheckMemoryAddressSpace, /*MI*/0, /*MMO*/0, /*NumAddrSpace*/3, /*AddrSpace*/1, /*AddrSpace*/4, /*AddrSpace*/6,
        GIM_CheckRegBankForClass, /*MI*/0, /*Op*/0, /*RC*/GIMT_Encode2(AMDGPU::AV_64RegClassID),
        GIM_CheckPointerToAny, /*MI*/0, /*Op*/1, /*SizeInBits*/0,
        GIM_CheckComplexPattern, /*MI*/0, /*Op*/1, /*Renderer*/GIMT_Encode2(0), GIMT_Encode2(GICP_gi_flat_offset),
        // (atomic_load_sub:{ *:[i64] } (FlatOffset:{ *:[iPTR] } i64:{ *:[i64] }:$vaddr, i32:{ *:[i32] }:$offset), i64:{ *:[i64] }:$data)<<P:Predicate_atomic_load_sub_global_64>>  =>  (FLAT_ATOMIC_SUB_X2_RTN:{ *:[i64] } VReg_64:{ *:[i64] }:$vaddr, anonymous_15036:{ *:[i64] }:$data, ?:{ *:[i32] }:$offset)
        GIR_BuildMI, /*InsnID*/0, /*Opcode*/GIMT_Encode2(AMDGPU::FLAT_ATOMIC_SUB_X2_RTN),
        GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/0, // DstI[vdst]
        GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/0, // vaddr
        GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/2, // data
        GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/1, // offset
        GIR_AddImm8, /*InsnID*/0, /*Imm*/1,
        GIR_MergeMemOperands, /*InsnID*/0, /*NumInsns*/1, /*MergeInsnID's*/0,
        GIR_ConstrainSelectedInstOperands, /*InsnID*/0,
        GIR_EraseFromParent, /*InsnID*/0,
        // GIR_Coverage, 2907,
        GIR_Done,
      // Label 2557: @167266
      GIM_Reject,
    // Label 2535: @167267
    GIM_Reject,
    // Label 2511: @167268
    GIM_Reject,
    // Label 20: @167269
    GIM_SwitchType, /*MI*/0, /*Op*/0, /*[*/GIMT_Encode2(9), GIMT_Encode2(11), /*)*//*default:*//*Label 2560*/ GIMT_Encode4(170112),
    /*GILLT_s32*//*Label 2558*/ GIMT_Encode4(167288),
    /*GILLT_s64*//*Label 2559*/ GIMT_Encode4(168700),
    // Label 2558: @167288
    GIM_Try, /*On fail goto*//*Label 2561*/ GIMT_Encode4(168699),
      GIM_CheckType, /*MI*/0, /*Op*/2, /*Type*/GILLT_s32,
      GIM_Try, /*On fail goto*//*Label 2562*/ GIMT_Encode4(167365), // Rule ID 4566 //
        GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasUnrestrictedSOffset),
        GIM_CheckMemoryAddressSpace, /*MI*/0, /*MMO*/0, /*NumAddrSpace*/3, /*AddrSpace*/1, /*AddrSpace*/4, /*AddrSpace*/6,
        GIM_CheckHasNoUse, /*MI*/0,
        GIM_CheckPointerToAny, /*MI*/0, /*Op*/1, /*SizeInBits*/0,
        GIM_CheckComplexPattern, /*MI*/0, /*Op*/1, /*Renderer*/GIMT_Encode2(0), GIMT_Encode2(GICP_gi_mubuf_addr64),
        // (atomic_load_and:{ *:[i32] } (MUBUFAddr64:{ *:[iPTR] } v4i32:{ *:[v4i32] }:$srsrc, i64:{ *:[i64] }:$vaddr, i32:{ *:[i32] }:$soffset, i32:{ *:[i32] }:$offset), i32:{ *:[i32] }:$vdata_in)<<P:Predicate_atomic_load_and_global_noret_32>>  =>  (BUFFER_ATOMIC_AND_ADDR64 anonymous_15037:{ *:[i32] }:$vdata_in, VReg_64:{ *:[i64] }:$vaddr, SReg_128:{ *:[v4i32] }:$srsrc, SCSrc_b32:{ *:[i32] }:$soffset, offset:{ *:[i32] }:$offset)
        GIR_BuildMI, /*InsnID*/0, /*Opcode*/GIMT_Encode2(AMDGPU::BUFFER_ATOMIC_AND_ADDR64),
        GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/2, // vdata_in
        GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/1, // vaddr
        GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/0, // srsrc
        GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/2, // soffset
        GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/3, // offset
        GIR_AddImm8, /*InsnID*/0, /*Imm*/0,
        GIR_MergeMemOperands, /*InsnID*/0, /*NumInsns*/1, /*MergeInsnID's*/0,
        GIR_ConstrainSelectedInstOperands, /*InsnID*/0,
        GIR_EraseFromParent, /*InsnID*/0,
        // GIR_Coverage, 4566,
        GIR_Done,
      // Label 2562: @167365
      GIM_Try, /*On fail goto*//*Label 2563*/ GIMT_Encode4(167430), // Rule ID 4570 //
        GIM_CheckMemoryAddressSpace, /*MI*/0, /*MMO*/0, /*NumAddrSpace*/3, /*AddrSpace*/1, /*AddrSpace*/4, /*AddrSpace*/6,
        GIM_CheckHasNoUse, /*MI*/0,
        GIM_CheckPointerToAny, /*MI*/0, /*Op*/1, /*SizeInBits*/0,
        GIM_CheckComplexPattern, /*MI*/0, /*Op*/1, /*Renderer*/GIMT_Encode2(0), GIMT_Encode2(GICP_gi_mubuf_addr64),
        // (atomic_load_and:{ *:[i32] } (MUBUFAddr64:{ *:[iPTR] } v4i32:{ *:[v4i32] }:$srsrc, i64:{ *:[i64] }:$vaddr, i32:{ *:[i32] }:$soffset, i32:{ *:[i32] }:$offset), i32:{ *:[i32] }:$vdata_in)<<P:Predicate_atomic_load_and_global_noret_32>>  =>  (BUFFER_ATOMIC_AND_VBUFFER_ADDR64 anonymous_15037:{ *:[i32] }:$vdata_in, VReg_64:{ *:[i64] }:$vaddr, SReg_128:{ *:[v4i32] }:$srsrc, SCSrc_b32:{ *:[i32] }:$soffset, offset:{ *:[i32] }:$offset)
        GIR_BuildMI, /*InsnID*/0, /*Opcode*/GIMT_Encode2(AMDGPU::BUFFER_ATOMIC_AND_VBUFFER_ADDR64),
        GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/2, // vdata_in
        GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/1, // vaddr
        GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/0, // srsrc
        GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/2, // soffset
        GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/3, // offset
        GIR_AddImm8, /*InsnID*/0, /*Imm*/0,
        GIR_MergeMemOperands, /*InsnID*/0, /*NumInsns*/1, /*MergeInsnID's*/0,
        GIR_ConstrainSelectedInstOperands, /*InsnID*/0,
        GIR_EraseFromParent, /*InsnID*/0,
        // GIR_Coverage, 4570,
        GIR_Done,
      // Label 2563: @167430
      GIM_Try, /*On fail goto*//*Label 2564*/ GIMT_Encode4(167505), // Rule ID 4564 //
        GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasUnrestrictedSOffset),
        GIM_CheckMemoryAddressSpace, /*MI*/0, /*MMO*/0, /*NumAddrSpace*/3, /*AddrSpace*/1, /*AddrSpace*/4, /*AddrSpace*/6,
        GIM_CheckRegBankForClass, /*MI*/0, /*Op*/0, /*RC*/GIMT_Encode2(AMDGPU::AV_32RegClassID),
        GIM_CheckPointerToAny, /*MI*/0, /*Op*/1, /*SizeInBits*/0,
        GIM_CheckComplexPattern, /*MI*/0, /*Op*/1, /*Renderer*/GIMT_Encode2(0), GIMT_Encode2(GICP_gi_mubuf_addr64),
        // (atomic_load_and:{ *:[i32] } (MUBUFAddr64:{ *:[iPTR] } v4i32:{ *:[v4i32] }:$srsrc, i64:{ *:[i64] }:$vaddr, i32:{ *:[i32] }:$soffset, i32:{ *:[i32] }:$offset), i32:{ *:[i32] }:$vdata_in)<<P:Predicate_atomic_load_and_global_32>>  =>  (BUFFER_ATOMIC_AND_ADDR64_RTN:{ *:[i32] } anonymous_15037:{ *:[i32] }:$vdata_in, VReg_64:{ *:[i64] }:$vaddr, SReg_128:{ *:[v4i32] }:$srsrc, SCSrc_b32:{ *:[i32] }:$soffset, offset:{ *:[i32] }:$offset)
        GIR_BuildMI, /*InsnID*/0, /*Opcode*/GIMT_Encode2(AMDGPU::BUFFER_ATOMIC_AND_ADDR64_RTN),
        GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/0, // DstI[vdata]
        GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/2, // vdata_in
        GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/1, // vaddr
        GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/0, // srsrc
        GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/2, // soffset
        GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/3, // offset
        GIR_AddImm8, /*InsnID*/0, /*Imm*/1,
        GIR_MergeMemOperands, /*InsnID*/0, /*NumInsns*/1, /*MergeInsnID's*/0,
        GIR_ConstrainSelectedInstOperands, /*InsnID*/0,
        GIR_EraseFromParent, /*InsnID*/0,
        // GIR_Coverage, 4564,
        GIR_Done,
      // Label 2564: @167505
      GIM_Try, /*On fail goto*//*Label 2565*/ GIMT_Encode4(167577), // Rule ID 4568 //
        GIM_CheckMemoryAddressSpace, /*MI*/0, /*MMO*/0, /*NumAddrSpace*/3, /*AddrSpace*/1, /*AddrSpace*/4, /*AddrSpace*/6,
        GIM_CheckRegBankForClass, /*MI*/0, /*Op*/0, /*RC*/GIMT_Encode2(AMDGPU::AV_32RegClassID),
        GIM_CheckPointerToAny, /*MI*/0, /*Op*/1, /*SizeInBits*/0,
        GIM_CheckComplexPattern, /*MI*/0, /*Op*/1, /*Renderer*/GIMT_Encode2(0), GIMT_Encode2(GICP_gi_mubuf_addr64),
        // (atomic_load_and:{ *:[i32] } (MUBUFAddr64:{ *:[iPTR] } v4i32:{ *:[v4i32] }:$srsrc, i64:{ *:[i64] }:$vaddr, i32:{ *:[i32] }:$soffset, i32:{ *:[i32] }:$offset), i32:{ *:[i32] }:$vdata_in)<<P:Predicate_atomic_load_and_global_32>>  =>  (BUFFER_ATOMIC_AND_VBUFFER_ADDR64_RTN:{ *:[i32] } anonymous_15037:{ *:[i32] }:$vdata_in, VReg_64:{ *:[i64] }:$vaddr, SReg_128:{ *:[v4i32] }:$srsrc, SCSrc_b32:{ *:[i32] }:$soffset, offset:{ *:[i32] }:$offset)
        GIR_BuildMI, /*InsnID*/0, /*Opcode*/GIMT_Encode2(AMDGPU::BUFFER_ATOMIC_AND_VBUFFER_ADDR64_RTN),
        GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/0, // DstI[vdata]
        GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/2, // vdata_in
        GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/1, // vaddr
        GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/0, // srsrc
        GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/2, // soffset
        GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/3, // offset
        GIR_AddImm8, /*InsnID*/0, /*Imm*/1,
        GIR_MergeMemOperands, /*InsnID*/0, /*NumInsns*/1, /*MergeInsnID's*/0,
        GIR_ConstrainSelectedInstOperands, /*InsnID*/0,
        GIR_EraseFromParent, /*InsnID*/0,
        // GIR_Coverage, 4568,
        GIR_Done,
      // Label 2565: @167577
      GIM_Try, /*On fail goto*//*Label 2566*/ GIMT_Encode4(167640), // Rule ID 4565 //
        GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasUnrestrictedSOffset),
        GIM_CheckMemoryAddressSpace, /*MI*/0, /*MMO*/0, /*NumAddrSpace*/3, /*AddrSpace*/1, /*AddrSpace*/4, /*AddrSpace*/6,
        GIM_CheckHasNoUse, /*MI*/0,
        GIM_CheckPointerToAny, /*MI*/0, /*Op*/1, /*SizeInBits*/0,
        GIM_CheckComplexPattern, /*MI*/0, /*Op*/1, /*Renderer*/GIMT_Encode2(0), GIMT_Encode2(GICP_gi_mubuf_offset),
        // (atomic_load_and:{ *:[i32] } (MUBUFOffset:{ *:[iPTR] } v4i32:{ *:[v4i32] }:$srsrc, i32:{ *:[i32] }:$soffset, i32:{ *:[i32] }:$offset), i32:{ *:[i32] }:$vdata_in)<<P:Predicate_atomic_load_and_global_noret_32>>  =>  (BUFFER_ATOMIC_AND_OFFSET anonymous_15037:{ *:[i32] }:$vdata_in, SReg_128:{ *:[v4i32] }:$srsrc, SCSrc_b32:{ *:[i32] }:$soffset, offset:{ *:[i32] }:$offset)
        GIR_BuildMI, /*InsnID*/0, /*Opcode*/GIMT_Encode2(AMDGPU::BUFFER_ATOMIC_AND_OFFSET),
        GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/2, // vdata_in
        GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/0, // srsrc
        GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/1, // soffset
        GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/2, // offset
        GIR_AddImm8, /*InsnID*/0, /*Imm*/0,
        GIR_MergeMemOperands, /*InsnID*/0, /*NumInsns*/1, /*MergeInsnID's*/0,
        GIR_ConstrainSelectedInstOperands, /*InsnID*/0,
        GIR_EraseFromParent, /*InsnID*/0,
        // GIR_Coverage, 4565,
        GIR_Done,
      // Label 2566: @167640
      GIM_Try, /*On fail goto*//*Label 2567*/ GIMT_Encode4(167700), // Rule ID 4569 //
        GIM_CheckMemoryAddressSpace, /*MI*/0, /*MMO*/0, /*NumAddrSpace*/3, /*AddrSpace*/1, /*AddrSpace*/4, /*AddrSpace*/6,
        GIM_CheckHasNoUse, /*MI*/0,
        GIM_CheckPointerToAny, /*MI*/0, /*Op*/1, /*SizeInBits*/0,
        GIM_CheckComplexPattern, /*MI*/0, /*Op*/1, /*Renderer*/GIMT_Encode2(0), GIMT_Encode2(GICP_gi_mubuf_offset),
        // (atomic_load_and:{ *:[i32] } (MUBUFOffset:{ *:[iPTR] } v4i32:{ *:[v4i32] }:$srsrc, i32:{ *:[i32] }:$soffset, i32:{ *:[i32] }:$offset), i32:{ *:[i32] }:$vdata_in)<<P:Predicate_atomic_load_and_global_noret_32>>  =>  (BUFFER_ATOMIC_AND_VBUFFER_OFFSET anonymous_15037:{ *:[i32] }:$vdata_in, SReg_128:{ *:[v4i32] }:$srsrc, SCSrc_b32:{ *:[i32] }:$soffset, offset:{ *:[i32] }:$offset)
        GIR_BuildMI, /*InsnID*/0, /*Opcode*/GIMT_Encode2(AMDGPU::BUFFER_ATOMIC_AND_VBUFFER_OFFSET),
        GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/2, // vdata_in
        GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/0, // srsrc
        GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/1, // soffset
        GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/2, // offset
        GIR_AddImm8, /*InsnID*/0, /*Imm*/0,
        GIR_MergeMemOperands, /*InsnID*/0, /*NumInsns*/1, /*MergeInsnID's*/0,
        GIR_ConstrainSelectedInstOperands, /*InsnID*/0,
        GIR_EraseFromParent, /*InsnID*/0,
        // GIR_Coverage, 4569,
        GIR_Done,
      // Label 2567: @167700
      GIM_Try, /*On fail goto*//*Label 2568*/ GIMT_Encode4(167770), // Rule ID 4563 //
        GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasUnrestrictedSOffset),
        GIM_CheckMemoryAddressSpace, /*MI*/0, /*MMO*/0, /*NumAddrSpace*/3, /*AddrSpace*/1, /*AddrSpace*/4, /*AddrSpace*/6,
        GIM_CheckRegBankForClass, /*MI*/0, /*Op*/0, /*RC*/GIMT_Encode2(AMDGPU::AV_32RegClassID),
        GIM_CheckPointerToAny, /*MI*/0, /*Op*/1, /*SizeInBits*/0,
        GIM_CheckComplexPattern, /*MI*/0, /*Op*/1, /*Renderer*/GIMT_Encode2(0), GIMT_Encode2(GICP_gi_mubuf_offset),
        // (atomic_load_and:{ *:[i32] } (MUBUFOffset:{ *:[iPTR] } v4i32:{ *:[v4i32] }:$srsrc, i32:{ *:[i32] }:$soffset, i32:{ *:[i32] }:$offset), i32:{ *:[i32] }:$vdata_in)<<P:Predicate_atomic_load_and_global_32>>  =>  (BUFFER_ATOMIC_AND_OFFSET_RTN:{ *:[i32] } anonymous_15037:{ *:[i32] }:$vdata_in, SReg_128:{ *:[v4i32] }:$srsrc, SCSrc_b32:{ *:[i32] }:$soffset, offset:{ *:[i32] }:$offset)
        GIR_BuildMI, /*InsnID*/0, /*Opcode*/GIMT_Encode2(AMDGPU::BUFFER_ATOMIC_AND_OFFSET_RTN),
        GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/0, // DstI[vdata]
        GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/2, // vdata_in
        GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/0, // srsrc
        GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/1, // soffset
        GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/2, // offset
        GIR_AddImm8, /*InsnID*/0, /*Imm*/1,
        GIR_MergeMemOperands, /*InsnID*/0, /*NumInsns*/1, /*MergeInsnID's*/0,
        GIR_ConstrainSelectedInstOperands, /*InsnID*/0,
        GIR_EraseFromParent, /*InsnID*/0,
        // GIR_Coverage, 4563,
        GIR_Done,
      // Label 2568: @167770
      GIM_Try, /*On fail goto*//*Label 2569*/ GIMT_Encode4(167837), // Rule ID 4567 //
        GIM_CheckMemoryAddressSpace, /*MI*/0, /*MMO*/0, /*NumAddrSpace*/3, /*AddrSpace*/1, /*AddrSpace*/4, /*AddrSpace*/6,
        GIM_CheckRegBankForClass, /*MI*/0, /*Op*/0, /*RC*/GIMT_Encode2(AMDGPU::AV_32RegClassID),
        GIM_CheckPointerToAny, /*MI*/0, /*Op*/1, /*SizeInBits*/0,
        GIM_CheckComplexPattern, /*MI*/0, /*Op*/1, /*Renderer*/GIMT_Encode2(0), GIMT_Encode2(GICP_gi_mubuf_offset),
        // (atomic_load_and:{ *:[i32] } (MUBUFOffset:{ *:[iPTR] } v4i32:{ *:[v4i32] }:$srsrc, i32:{ *:[i32] }:$soffset, i32:{ *:[i32] }:$offset), i32:{ *:[i32] }:$vdata_in)<<P:Predicate_atomic_load_and_global_32>>  =>  (BUFFER_ATOMIC_AND_VBUFFER_OFFSET_RTN:{ *:[i32] } anonymous_15037:{ *:[i32] }:$vdata_in, SReg_128:{ *:[v4i32] }:$srsrc, SCSrc_b32:{ *:[i32] }:$soffset, offset:{ *:[i32] }:$offset)
        GIR_BuildMI, /*InsnID*/0, /*Opcode*/GIMT_Encode2(AMDGPU::BUFFER_ATOMIC_AND_VBUFFER_OFFSET_RTN),
        GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/0, // DstI[vdata]
        GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/2, // vdata_in
        GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/0, // srsrc
        GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/1, // soffset
        GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/2, // offset
        GIR_AddImm8, /*InsnID*/0, /*Imm*/1,
        GIR_MergeMemOperands, /*InsnID*/0, /*NumInsns*/1, /*MergeInsnID's*/0,
        GIR_ConstrainSelectedInstOperands, /*InsnID*/0,
        GIR_EraseFromParent, /*InsnID*/0,
        // GIR_Coverage, 4567,
        GIR_Done,
      // Label 2569: @167837
      GIM_Try, /*On fail goto*//*Label 2570*/ GIMT_Encode4(167893), // Rule ID 6929 //
        GIM_CheckFeatures, GIMT_Encode2(GIFBS_LDSRequiresM0Init),
        GIM_CheckMemoryAddressSpace, /*MI*/0, /*MMO*/0, /*NumAddrSpace*/1, /*AddrSpace*/3,
        GIM_CheckHasNoUse, /*MI*/0,
        GIM_CheckPointerToAny, /*MI*/0, /*Op*/1, /*SizeInBits*/0,
        GIM_CheckComplexPattern, /*MI*/0, /*Op*/1, /*Renderer*/GIMT_Encode2(0), GIMT_Encode2(GICP_gi_ds_1addr_1offset),
        // (atomic_load_and_glue:{ *:[i32] } (DS1Addr1Offset:{ *:[iPTR] } i32:{ *:[i32] }:$ptr, i32:{ *:[i32] }:$offset), i32:{ *:[i32] }:$value)<<P:Predicate_atomic_load_and_local_m0_noret_32>>  =>  (DS_AND_B32 ?:{ *:[i32] }:$ptr, anonymous_15037:{ *:[i32] }:$value, offset:{ *:[i32] }:$offset, 0:{ *:[i1] })
        GIR_BuildMI, /*InsnID*/0, /*Opcode*/GIMT_Encode2(AMDGPU::DS_AND_B32),
        GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/0, // ptr
        GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/2, // value
        GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/1, // offset
        GIR_AddImm8, /*InsnID*/0, /*Imm*/0,
        GIR_MergeMemOperands, /*InsnID*/0, /*NumInsns*/1, /*MergeInsnID's*/0,
        GIR_ConstrainSelectedInstOperands, /*InsnID*/0,
        GIR_EraseFromParent, /*InsnID*/0,
        // GIR_Coverage, 6929,
        GIR_Done,
      // Label 2570: @167893
      GIM_Try, /*On fail goto*//*Label 2571*/ GIMT_Encode4(167949), // Rule ID 6931 //
        GIM_CheckFeatures, GIMT_Encode2(GIFBS_NotLDSRequiresM0Init),
        GIM_CheckMemoryAddressSpace, /*MI*/0, /*MMO*/0, /*NumAddrSpace*/1, /*AddrSpace*/3,
        GIM_CheckHasNoUse, /*MI*/0,
        GIM_CheckPointerToAny, /*MI*/0, /*Op*/1, /*SizeInBits*/0,
        GIM_CheckComplexPattern, /*MI*/0, /*Op*/1, /*Renderer*/GIMT_Encode2(0), GIMT_Encode2(GICP_gi_ds_1addr_1offset),
        // (atomic_load_and:{ *:[i32] } (DS1Addr1Offset:{ *:[iPTR] } i32:{ *:[i32] }:$ptr, i32:{ *:[i32] }:$offset), i32:{ *:[i32] }:$value)<<P:Predicate_atomic_load_and_local_noret_32>>  =>  (DS_AND_B32_gfx9 ?:{ *:[i32] }:$ptr, anonymous_15037:{ *:[i32] }:$value, offset:{ *:[i32] }:$offset, 0:{ *:[i1] })
        GIR_BuildMI, /*InsnID*/0, /*Opcode*/GIMT_Encode2(AMDGPU::DS_AND_B32_gfx9),
        GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/0, // ptr
        GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/2, // value
        GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/1, // offset
        GIR_AddImm8, /*InsnID*/0, /*Imm*/0,
        GIR_MergeMemOperands, /*InsnID*/0, /*NumInsns*/1, /*MergeInsnID's*/0,
        GIR_ConstrainSelectedInstOperands, /*InsnID*/0,
        GIR_EraseFromParent, /*InsnID*/0,
        // GIR_Coverage, 6931,
        GIR_Done,
      // Label 2571: @167949
      GIM_Try, /*On fail goto*//*Label 2572*/ GIMT_Encode4(168005), // Rule ID 6933 //
        GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasGDS),
        GIM_CheckMemoryAddressSpace, /*MI*/0, /*MMO*/0, /*NumAddrSpace*/1, /*AddrSpace*/2,
        GIM_CheckHasNoUse, /*MI*/0,
        GIM_CheckPointerToAny, /*MI*/0, /*Op*/1, /*SizeInBits*/0,
        GIM_CheckComplexPattern, /*MI*/0, /*Op*/1, /*Renderer*/GIMT_Encode2(0), GIMT_Encode2(GICP_gi_ds_1addr_1offset),
        // (atomic_load_and_glue:{ *:[i32] } (DS1Addr1Offset:{ *:[iPTR] } i32:{ *:[i32] }:$ptr, i32:{ *:[i32] }:$offset), i32:{ *:[i32] }:$value)<<P:Predicate_atomic_load_and_region_m0_noret_32>>  =>  (DS_AND_B32 ?:{ *:[i32] }:$ptr, anonymous_15037:{ *:[i32] }:$value, offset:{ *:[i32] }:$offset, 1:{ *:[i1] })
        GIR_BuildMI, /*InsnID*/0, /*Opcode*/GIMT_Encode2(AMDGPU::DS_AND_B32),
        GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/0, // ptr
        GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/2, // value
        GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/1, // offset
        GIR_AddImm8, /*InsnID*/0, /*Imm*/1,
        GIR_MergeMemOperands, /*InsnID*/0, /*NumInsns*/1, /*MergeInsnID's*/0,
        GIR_ConstrainSelectedInstOperands, /*InsnID*/0,
        GIR_EraseFromParent, /*InsnID*/0,
        // GIR_Coverage, 6933,
        GIR_Done,
      // Label 2572: @168005
      GIM_Try, /*On fail goto*//*Label 2573*/ GIMT_Encode4(168068), // Rule ID 6928 //
        GIM_CheckFeatures, GIMT_Encode2(GIFBS_LDSRequiresM0Init),
        GIM_CheckMemoryAddressSpace, /*MI*/0, /*MMO*/0, /*NumAddrSpace*/1, /*AddrSpace*/3,
        GIM_CheckRegBankForClass, /*MI*/0, /*Op*/0, /*RC*/GIMT_Encode2(AMDGPU::AV_32RegClassID),
        GIM_CheckPointerToAny, /*MI*/0, /*Op*/1, /*SizeInBits*/0,
        GIM_CheckComplexPattern, /*MI*/0, /*Op*/1, /*Renderer*/GIMT_Encode2(0), GIMT_Encode2(GICP_gi_ds_1addr_1offset),
        // (atomic_load_and_glue:{ *:[i32] } (DS1Addr1Offset:{ *:[iPTR] } i32:{ *:[i32] }:$ptr, i32:{ *:[i32] }:$offset), i32:{ *:[i32] }:$value)<<P:Predicate_atomic_load_and_local_m0_32>>  =>  (DS_AND_RTN_B32:{ *:[i32] } ?:{ *:[i32] }:$ptr, anonymous_15037:{ *:[i32] }:$value, offset:{ *:[i32] }:$offset, 0:{ *:[i1] })
        GIR_BuildMI, /*InsnID*/0, /*Opcode*/GIMT_Encode2(AMDGPU::DS_AND_RTN_B32),
        GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/0, // DstI[vdst]
        GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/0, // ptr
        GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/2, // value
        GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/1, // offset
        GIR_AddImm8, /*InsnID*/0, /*Imm*/0,
        GIR_MergeMemOperands, /*InsnID*/0, /*NumInsns*/1, /*MergeInsnID's*/0,
        GIR_ConstrainSelectedInstOperands, /*InsnID*/0,
        GIR_EraseFromParent, /*InsnID*/0,
        // GIR_Coverage, 6928,
        GIR_Done,
      // Label 2573: @168068
      GIM_Try, /*On fail goto*//*Label 2574*/ GIMT_Encode4(168131), // Rule ID 6930 //
        GIM_CheckFeatures, GIMT_Encode2(GIFBS_NotLDSRequiresM0Init),
        GIM_CheckMemoryAddressSpace, /*MI*/0, /*MMO*/0, /*NumAddrSpace*/1, /*AddrSpace*/3,
        GIM_CheckRegBankForClass, /*MI*/0, /*Op*/0, /*RC*/GIMT_Encode2(AMDGPU::AV_32RegClassID),
        GIM_CheckPointerToAny, /*MI*/0, /*Op*/1, /*SizeInBits*/0,
        GIM_CheckComplexPattern, /*MI*/0, /*Op*/1, /*Renderer*/GIMT_Encode2(0), GIMT_Encode2(GICP_gi_ds_1addr_1offset),
        // (atomic_load_and:{ *:[i32] } (DS1Addr1Offset:{ *:[iPTR] } i32:{ *:[i32] }:$ptr, i32:{ *:[i32] }:$offset), i32:{ *:[i32] }:$value)<<P:Predicate_atomic_load_and_local_32>>  =>  (DS_AND_RTN_B32_gfx9:{ *:[i32] } ?:{ *:[i32] }:$ptr, anonymous_15037:{ *:[i32] }:$value, offset:{ *:[i32] }:$offset, 0:{ *:[i1] })
        GIR_BuildMI, /*InsnID*/0, /*Opcode*/GIMT_Encode2(AMDGPU::DS_AND_RTN_B32_gfx9),
        GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/0, // DstI[vdst]
        GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/0, // ptr
        GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/2, // value
        GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/1, // offset
        GIR_AddImm8, /*InsnID*/0, /*Imm*/0,
        GIR_MergeMemOperands, /*InsnID*/0, /*NumInsns*/1, /*MergeInsnID's*/0,
        GIR_ConstrainSelectedInstOperands, /*InsnID*/0,
        GIR_EraseFromParent, /*InsnID*/0,
        // GIR_Coverage, 6930,
        GIR_Done,
      // Label 2574: @168131
      GIM_Try, /*On fail goto*//*Label 2575*/ GIMT_Encode4(168194), // Rule ID 6932 //
        GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasGDS),
        GIM_CheckMemoryAddressSpace, /*MI*/0, /*MMO*/0, /*NumAddrSpace*/1, /*AddrSpace*/2,
        GIM_CheckRegBankForClass, /*MI*/0, /*Op*/0, /*RC*/GIMT_Encode2(AMDGPU::AV_32RegClassID),
        GIM_CheckPointerToAny, /*MI*/0, /*Op*/1, /*SizeInBits*/0,
        GIM_CheckComplexPattern, /*MI*/0, /*Op*/1, /*Renderer*/GIMT_Encode2(0), GIMT_Encode2(GICP_gi_ds_1addr_1offset),
        // (atomic_load_and_glue:{ *:[i32] } (DS1Addr1Offset:{ *:[iPTR] } i32:{ *:[i32] }:$ptr, i32:{ *:[i32] }:$offset), i32:{ *:[i32] }:$value)<<P:Predicate_atomic_load_and_region_m0_32>>  =>  (DS_AND_RTN_B32:{ *:[i32] } ?:{ *:[i32] }:$ptr, anonymous_15037:{ *:[i32] }:$value, offset:{ *:[i32] }:$offset, 1:{ *:[i1] })
        GIR_BuildMI, /*InsnID*/0, /*Opcode*/GIMT_Encode2(AMDGPU::DS_AND_RTN_B32),
        GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/0, // DstI[vdst]
        GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/0, // ptr
        GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/2, // value
        GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/1, // offset
        GIR_AddImm8, /*InsnID*/0, /*Imm*/1,
        GIR_MergeMemOperands, /*InsnID*/0, /*NumInsns*/1, /*MergeInsnID's*/0,
        GIR_ConstrainSelectedInstOperands, /*InsnID*/0,
        GIR_EraseFromParent, /*InsnID*/0,
        // GIR_Coverage, 6932,
        GIR_Done,
      // Label 2575: @168194
      GIM_Try, /*On fail goto*//*Label 2576*/ GIMT_Encode4(168257), // Rule ID 3163 //
        GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasFlatGlobalInsts),
        GIM_CheckMemoryAddressSpace, /*MI*/0, /*MMO*/0, /*NumAddrSpace*/3, /*AddrSpace*/1, /*AddrSpace*/4, /*AddrSpace*/6,
        GIM_CheckHasNoUse, /*MI*/0,
        GIM_CheckPointerToAny, /*MI*/0, /*Op*/1, /*SizeInBits*/0,
        GIM_CheckComplexPattern, /*MI*/0, /*Op*/1, /*Renderer*/GIMT_Encode2(0), GIMT_Encode2(GICP_gi_global_saddr),
        // (atomic_load_and:{ *:[i32] } (GlobalSAddr:{ *:[iPTR] } SReg_64:{ *:[i64] }:$saddr, VGPR_32:{ *:[i32] }:$voffset, i32:{ *:[i32] }:$offset), i32:{ *:[i32] }:$data)<<P:Predicate_atomic_load_and_global_noret_32>>  =>  (GLOBAL_ATOMIC_AND_SADDR ?:{ *:[i32] }:$voffset, anonymous_15037:{ *:[i32] }:$data, ?:{ *:[i64] }:$saddr, ?:{ *:[i32] }:$offset)
        GIR_BuildMI, /*InsnID*/0, /*Opcode*/GIMT_Encode2(AMDGPU::GLOBAL_ATOMIC_AND_SADDR),
        GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/1, // voffset
        GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/2, // data
        GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/0, // saddr
        GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/2, // offset
        GIR_AddImm8, /*InsnID*/0, /*Imm*/0,
        GIR_MergeMemOperands, /*InsnID*/0, /*NumInsns*/1, /*MergeInsnID's*/0,
        GIR_ConstrainSelectedInstOperands, /*InsnID*/0,
        GIR_EraseFromParent, /*InsnID*/0,
        // GIR_Coverage, 3163,
        GIR_Done,
      // Label 2576: @168257
      GIM_Try, /*On fail goto*//*Label 2577*/ GIMT_Encode4(168327), // Rule ID 3165 //
        GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasFlatGlobalInsts),
        GIM_CheckMemoryAddressSpace, /*MI*/0, /*MMO*/0, /*NumAddrSpace*/3, /*AddrSpace*/1, /*AddrSpace*/4, /*AddrSpace*/6,
        GIM_CheckRegBankForClass, /*MI*/0, /*Op*/0, /*RC*/GIMT_Encode2(AMDGPU::AV_32RegClassID),
        GIM_CheckPointerToAny, /*MI*/0, /*Op*/1, /*SizeInBits*/0,
        GIM_CheckComplexPattern, /*MI*/0, /*Op*/1, /*Renderer*/GIMT_Encode2(0), GIMT_Encode2(GICP_gi_global_saddr),
        // (atomic_load_and:{ *:[i32] } (GlobalSAddr:{ *:[iPTR] } SReg_64:{ *:[i64] }:$saddr, VGPR_32:{ *:[i32] }:$voffset, i32:{ *:[i32] }:$offset), i32:{ *:[i32] }:$data)<<P:Predicate_atomic_load_and_global_32>>  =>  (GLOBAL_ATOMIC_AND_SADDR_RTN:{ *:[i32] } ?:{ *:[i32] }:$voffset, anonymous_15037:{ *:[i32] }:$data, ?:{ *:[i64] }:$saddr, ?:{ *:[i32] }:$offset)
        GIR_BuildMI, /*InsnID*/0, /*Opcode*/GIMT_Encode2(AMDGPU::GLOBAL_ATOMIC_AND_SADDR_RTN),
        GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/0, // DstI[vdst]
        GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/1, // voffset
        GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/2, // data
        GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/0, // saddr
        GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/2, // offset
        GIR_AddImm8, /*InsnID*/0, /*Imm*/1,
        GIR_MergeMemOperands, /*InsnID*/0, /*NumInsns*/1, /*MergeInsnID's*/0,
        GIR_ConstrainSelectedInstOperands, /*InsnID*/0,
        GIR_EraseFromParent, /*InsnID*/0,
        // GIR_Coverage, 3165,
        GIR_Done,
      // Label 2577: @168327
      GIM_Try, /*On fail goto*//*Label 2578*/ GIMT_Encode4(168385), // Rule ID 3162 //
        GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasFlatGlobalInsts),
        GIM_CheckMemoryAddressSpace, /*MI*/0, /*MMO*/0, /*NumAddrSpace*/3, /*AddrSpace*/1, /*AddrSpace*/4, /*AddrSpace*/6,
        GIM_CheckHasNoUse, /*MI*/0,
        GIM_CheckPointerToAny, /*MI*/0, /*Op*/1, /*SizeInBits*/0,
        GIM_CheckComplexPattern, /*MI*/0, /*Op*/1, /*Renderer*/GIMT_Encode2(0), GIMT_Encode2(GICP_gi_global_offset),
        // (atomic_load_and:{ *:[i32] } (GlobalOffset:{ *:[iPTR] } i64:{ *:[i64] }:$vaddr, i32:{ *:[i32] }:$offset), i32:{ *:[i32] }:$data)<<P:Predicate_atomic_load_and_global_noret_32>>  =>  (GLOBAL_ATOMIC_AND VReg_64:{ *:[i64] }:$vaddr, anonymous_15037:{ *:[i32] }:$data, ?:{ *:[i32] }:$offset)
        GIR_BuildMI, /*InsnID*/0, /*Opcode*/GIMT_Encode2(AMDGPU::GLOBAL_ATOMIC_AND),
        GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/0, // vaddr
        GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/2, // data
        GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/1, // offset
        GIR_AddImm8, /*InsnID*/0, /*Imm*/0,
        GIR_MergeMemOperands, /*InsnID*/0, /*NumInsns*/1, /*MergeInsnID's*/0,
        GIR_ConstrainSelectedInstOperands, /*InsnID*/0,
        GIR_EraseFromParent, /*InsnID*/0,
        // GIR_Coverage, 3162,
        GIR_Done,
      // Label 2578: @168385
      GIM_Try, /*On fail goto*//*Label 2579*/ GIMT_Encode4(168450), // Rule ID 3164 //
        GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasFlatGlobalInsts),
        GIM_CheckMemoryAddressSpace, /*MI*/0, /*MMO*/0, /*NumAddrSpace*/3, /*AddrSpace*/1, /*AddrSpace*/4, /*AddrSpace*/6,
        GIM_CheckRegBankForClass, /*MI*/0, /*Op*/0, /*RC*/GIMT_Encode2(AMDGPU::AV_32RegClassID),
        GIM_CheckPointerToAny, /*MI*/0, /*Op*/1, /*SizeInBits*/0,
        GIM_CheckComplexPattern, /*MI*/0, /*Op*/1, /*Renderer*/GIMT_Encode2(0), GIMT_Encode2(GICP_gi_global_offset),
        // (atomic_load_and:{ *:[i32] } (GlobalOffset:{ *:[iPTR] } i64:{ *:[i64] }:$vaddr, i32:{ *:[i32] }:$offset), i32:{ *:[i32] }:$data)<<P:Predicate_atomic_load_and_global_32>>  =>  (GLOBAL_ATOMIC_AND_RTN:{ *:[i32] } VReg_64:{ *:[i64] }:$vaddr, anonymous_15037:{ *:[i32] }:$data, ?:{ *:[i32] }:$offset)
        GIR_BuildMI, /*InsnID*/0, /*Opcode*/GIMT_Encode2(AMDGPU::GLOBAL_ATOMIC_AND_RTN),
        GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/0, // DstI[vdst]
        GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/0, // vaddr
        GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/2, // data
        GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/1, // offset
        GIR_AddImm8, /*InsnID*/0, /*Imm*/1,
        GIR_MergeMemOperands, /*InsnID*/0, /*NumInsns*/1, /*MergeInsnID's*/0,
        GIR_ConstrainSelectedInstOperands, /*InsnID*/0,
        GIR_EraseFromParent, /*InsnID*/0,
        // GIR_Coverage, 3164,
        GIR_Done,
      // Label 2579: @168450
      GIM_Try, /*On fail goto*//*Label 2580*/ GIMT_Encode4(168509), // Rule ID 2836 //
        GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasFlatAddressSpace),
        GIM_CheckMemoryAddressSpace, /*MI*/0, /*MMO*/0, /*NumAddrSpace*/4, /*AddrSpace*/0, /*AddrSpace*/1, /*AddrSpace*/4, /*AddrSpace*/6,
        GIM_CheckHasNoUse, /*MI*/0,
        GIM_CheckPointerToAny, /*MI*/0, /*Op*/1, /*SizeInBits*/0,
        GIM_CheckComplexPattern, /*MI*/0, /*Op*/1, /*Renderer*/GIMT_Encode2(0), GIMT_Encode2(GICP_gi_flat_offset),
        // (atomic_load_and:{ *:[i32] } (FlatOffset:{ *:[iPTR] } i64:{ *:[i64] }:$vaddr, i32:{ *:[i32] }:$offset), i32:{ *:[i32] }:$data)<<P:Predicate_atomic_load_and_flat_noret_32>>  =>  (FLAT_ATOMIC_AND VReg_64:{ *:[i64] }:$vaddr, anonymous_15037:{ *:[i32] }:$data, ?:{ *:[i32] }:$offset)
        GIR_BuildMI, /*InsnID*/0, /*Opcode*/GIMT_Encode2(AMDGPU::FLAT_ATOMIC_AND),
        GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/0, // vaddr
        GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/2, // data
        GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/1, // offset
        GIR_AddImm8, /*InsnID*/0, /*Imm*/0,
        GIR_MergeMemOperands, /*InsnID*/0, /*NumInsns*/1, /*MergeInsnID's*/0,
        GIR_ConstrainSelectedInstOperands, /*InsnID*/0,
        GIR_EraseFromParent, /*InsnID*/0,
        // GIR_Coverage, 2836,
        GIR_Done,
      // Label 2580: @168509
      GIM_Try, /*On fail goto*//*Label 2581*/ GIMT_Encode4(168567), // Rule ID 2888 //
        GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasFlatAddressSpace),
        GIM_CheckMemoryAddressSpace, /*MI*/0, /*MMO*/0, /*NumAddrSpace*/3, /*AddrSpace*/1, /*AddrSpace*/4, /*AddrSpace*/6,
        GIM_CheckHasNoUse, /*MI*/0,
        GIM_CheckPointerToAny, /*MI*/0, /*Op*/1, /*SizeInBits*/0,
        GIM_CheckComplexPattern, /*MI*/0, /*Op*/1, /*Renderer*/GIMT_Encode2(0), GIMT_Encode2(GICP_gi_flat_offset),
        // (atomic_load_and:{ *:[i32] } (FlatOffset:{ *:[iPTR] } i64:{ *:[i64] }:$vaddr, i32:{ *:[i32] }:$offset), i32:{ *:[i32] }:$data)<<P:Predicate_atomic_load_and_global_noret_32>>  =>  (FLAT_ATOMIC_AND VReg_64:{ *:[i64] }:$vaddr, anonymous_15037:{ *:[i32] }:$data, ?:{ *:[i32] }:$offset)
        GIR_BuildMI, /*InsnID*/0, /*Opcode*/GIMT_Encode2(AMDGPU::FLAT_ATOMIC_AND),
        GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/0, // vaddr
        GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/2, // data
        GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/1, // offset
        GIR_AddImm8, /*InsnID*/0, /*Imm*/0,
        GIR_MergeMemOperands, /*InsnID*/0, /*NumInsns*/1, /*MergeInsnID's*/0,
        GIR_ConstrainSelectedInstOperands, /*InsnID*/0,
        GIR_EraseFromParent, /*InsnID*/0,
        // GIR_Coverage, 2888,
        GIR_Done,
      // Label 2581: @168567
      GIM_Try, /*On fail goto*//*Label 2582*/ GIMT_Encode4(168633), // Rule ID 2835 //
        GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasFlatAddressSpace),
        GIM_CheckMemoryAddressSpace, /*MI*/0, /*MMO*/0, /*NumAddrSpace*/4, /*AddrSpace*/0, /*AddrSpace*/1, /*AddrSpace*/4, /*AddrSpace*/6,
        GIM_CheckRegBankForClass, /*MI*/0, /*Op*/0, /*RC*/GIMT_Encode2(AMDGPU::AV_32RegClassID),
        GIM_CheckPointerToAny, /*MI*/0, /*Op*/1, /*SizeInBits*/0,
        GIM_CheckComplexPattern, /*MI*/0, /*Op*/1, /*Renderer*/GIMT_Encode2(0), GIMT_Encode2(GICP_gi_flat_offset),
        // (atomic_load_and:{ *:[i32] } (FlatOffset:{ *:[iPTR] } i64:{ *:[i64] }:$vaddr, i32:{ *:[i32] }:$offset), i32:{ *:[i32] }:$data)<<P:Predicate_atomic_load_and_flat_32>>  =>  (FLAT_ATOMIC_AND_RTN:{ *:[i32] } VReg_64:{ *:[i64] }:$vaddr, anonymous_15037:{ *:[i32] }:$data, ?:{ *:[i32] }:$offset)
        GIR_BuildMI, /*InsnID*/0, /*Opcode*/GIMT_Encode2(AMDGPU::FLAT_ATOMIC_AND_RTN),
        GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/0, // DstI[vdst]
        GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/0, // vaddr
        GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/2, // data
        GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/1, // offset
        GIR_AddImm8, /*InsnID*/0, /*Imm*/1,
        GIR_MergeMemOperands, /*InsnID*/0, /*NumInsns*/1, /*MergeInsnID's*/0,
        GIR_ConstrainSelectedInstOperands, /*InsnID*/0,
        GIR_EraseFromParent, /*InsnID*/0,
        // GIR_Coverage, 2835,
        GIR_Done,
      // Label 2582: @168633
      GIM_Try, /*On fail goto*//*Label 2583*/ GIMT_Encode4(168698), // Rule ID 2887 //
        GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasFlatAddressSpace),
        GIM_CheckMemoryAddressSpace, /*MI*/0, /*MMO*/0, /*NumAddrSpace*/3, /*AddrSpace*/1, /*AddrSpace*/4, /*AddrSpace*/6,
        GIM_CheckRegBankForClass, /*MI*/0, /*Op*/0, /*RC*/GIMT_Encode2(AMDGPU::AV_32RegClassID),
        GIM_CheckPointerToAny, /*MI*/0, /*Op*/1, /*SizeInBits*/0,
        GIM_CheckComplexPattern, /*MI*/0, /*Op*/1, /*Renderer*/GIMT_Encode2(0), GIMT_Encode2(GICP_gi_flat_offset),
        // (atomic_load_and:{ *:[i32] } (FlatOffset:{ *:[iPTR] } i64:{ *:[i64] }:$vaddr, i32:{ *:[i32] }:$offset), i32:{ *:[i32] }:$data)<<P:Predicate_atomic_load_and_global_32>>  =>  (FLAT_ATOMIC_AND_RTN:{ *:[i32] } VReg_64:{ *:[i64] }:$vaddr, anonymous_15037:{ *:[i32] }:$data, ?:{ *:[i32] }:$offset)
        GIR_BuildMI, /*InsnID*/0, /*Opcode*/GIMT_Encode2(AMDGPU::FLAT_ATOMIC_AND_RTN),
        GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/0, // DstI[vdst]
        GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/0, // vaddr
        GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/2, // data
        GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/1, // offset
        GIR_AddImm8, /*InsnID*/0, /*Imm*/1,
        GIR_MergeMemOperands, /*InsnID*/0, /*NumInsns*/1, /*MergeInsnID's*/0,
        GIR_ConstrainSelectedInstOperands, /*InsnID*/0,
        GIR_EraseFromParent, /*InsnID*/0,
        // GIR_Coverage, 2887,
        GIR_Done,
      // Label 2583: @168698
      GIM_Reject,
    // Label 2561: @168699
    GIM_Reject,
    // Label 2559: @168700
    GIM_Try, /*On fail goto*//*Label 2584*/ GIMT_Encode4(170111),
      GIM_CheckType, /*MI*/0, /*Op*/2, /*Type*/GILLT_s64,
      GIM_Try, /*On fail goto*//*Label 2585*/ GIMT_Encode4(168777), // Rule ID 4662 //
        GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasUnrestrictedSOffset),
        GIM_CheckMemoryAddressSpace, /*MI*/0, /*MMO*/0, /*NumAddrSpace*/3, /*AddrSpace*/1, /*AddrSpace*/4, /*AddrSpace*/6,
        GIM_CheckHasNoUse, /*MI*/0,
        GIM_CheckPointerToAny, /*MI*/0, /*Op*/1, /*SizeInBits*/0,
        GIM_CheckComplexPattern, /*MI*/0, /*Op*/1, /*Renderer*/GIMT_Encode2(0), GIMT_Encode2(GICP_gi_mubuf_addr64),
        // (atomic_load_and:{ *:[i64] } (MUBUFAddr64:{ *:[iPTR] } v4i32:{ *:[v4i32] }:$srsrc, i64:{ *:[i64] }:$vaddr, i32:{ *:[i32] }:$soffset, i32:{ *:[i32] }:$offset), i64:{ *:[i64] }:$vdata_in)<<P:Predicate_atomic_load_and_global_noret_64>>  =>  (BUFFER_ATOMIC_AND_X2_ADDR64 anonymous_15036:{ *:[i64] }:$vdata_in, VReg_64:{ *:[i64] }:$vaddr, SReg_128:{ *:[v4i32] }:$srsrc, SCSrc_b32:{ *:[i32] }:$soffset, offset:{ *:[i32] }:$offset)
        GIR_BuildMI, /*InsnID*/0, /*Opcode*/GIMT_Encode2(AMDGPU::BUFFER_ATOMIC_AND_X2_ADDR64),
        GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/2, // vdata_in
        GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/1, // vaddr
        GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/0, // srsrc
        GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/2, // soffset
        GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/3, // offset
        GIR_AddImm8, /*InsnID*/0, /*Imm*/0,
        GIR_MergeMemOperands, /*InsnID*/0, /*NumInsns*/1, /*MergeInsnID's*/0,
        GIR_ConstrainSelectedInstOperands, /*InsnID*/0,
        GIR_EraseFromParent, /*InsnID*/0,
        // GIR_Coverage, 4662,
        GIR_Done,
      // Label 2585: @168777
      GIM_Try, /*On fail goto*//*Label 2586*/ GIMT_Encode4(168842), // Rule ID 4666 //
        GIM_CheckMemoryAddressSpace, /*MI*/0, /*MMO*/0, /*NumAddrSpace*/3, /*AddrSpace*/1, /*AddrSpace*/4, /*AddrSpace*/6,
        GIM_CheckHasNoUse, /*MI*/0,
        GIM_CheckPointerToAny, /*MI*/0, /*Op*/1, /*SizeInBits*/0,
        GIM_CheckComplexPattern, /*MI*/0, /*Op*/1, /*Renderer*/GIMT_Encode2(0), GIMT_Encode2(GICP_gi_mubuf_addr64),
        // (atomic_load_and:{ *:[i64] } (MUBUFAddr64:{ *:[iPTR] } v4i32:{ *:[v4i32] }:$srsrc, i64:{ *:[i64] }:$vaddr, i32:{ *:[i32] }:$soffset, i32:{ *:[i32] }:$offset), i64:{ *:[i64] }:$vdata_in)<<P:Predicate_atomic_load_and_global_noret_64>>  =>  (BUFFER_ATOMIC_AND_X2_VBUFFER_ADDR64 anonymous_15036:{ *:[i64] }:$vdata_in, VReg_64:{ *:[i64] }:$vaddr, SReg_128:{ *:[v4i32] }:$srsrc, SCSrc_b32:{ *:[i32] }:$soffset, offset:{ *:[i32] }:$offset)
        GIR_BuildMI, /*InsnID*/0, /*Opcode*/GIMT_Encode2(AMDGPU::BUFFER_ATOMIC_AND_X2_VBUFFER_ADDR64),
        GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/2, // vdata_in
        GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/1, // vaddr
        GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/0, // srsrc
        GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/2, // soffset
        GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/3, // offset
        GIR_AddImm8, /*InsnID*/0, /*Imm*/0,
        GIR_MergeMemOperands, /*InsnID*/0, /*NumInsns*/1, /*MergeInsnID's*/0,
        GIR_ConstrainSelectedInstOperands, /*InsnID*/0,
        GIR_EraseFromParent, /*InsnID*/0,
        // GIR_Coverage, 4666,
        GIR_Done,
      // Label 2586: @168842
      GIM_Try, /*On fail goto*//*Label 2587*/ GIMT_Encode4(168917), // Rule ID 4660 //
        GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasUnrestrictedSOffset),
        GIM_CheckMemoryAddressSpace, /*MI*/0, /*MMO*/0, /*NumAddrSpace*/3, /*AddrSpace*/1, /*AddrSpace*/4, /*AddrSpace*/6,
        GIM_CheckRegBankForClass, /*MI*/0, /*Op*/0, /*RC*/GIMT_Encode2(AMDGPU::AV_64RegClassID),
        GIM_CheckPointerToAny, /*MI*/0, /*Op*/1, /*SizeInBits*/0,
        GIM_CheckComplexPattern, /*MI*/0, /*Op*/1, /*Renderer*/GIMT_Encode2(0), GIMT_Encode2(GICP_gi_mubuf_addr64),
        // (atomic_load_and:{ *:[i64] } (MUBUFAddr64:{ *:[iPTR] } v4i32:{ *:[v4i32] }:$srsrc, i64:{ *:[i64] }:$vaddr, i32:{ *:[i32] }:$soffset, i32:{ *:[i32] }:$offset), i64:{ *:[i64] }:$vdata_in)<<P:Predicate_atomic_load_and_global_64>>  =>  (BUFFER_ATOMIC_AND_X2_ADDR64_RTN:{ *:[i64] } anonymous_15036:{ *:[i64] }:$vdata_in, VReg_64:{ *:[i64] }:$vaddr, SReg_128:{ *:[v4i32] }:$srsrc, SCSrc_b32:{ *:[i32] }:$soffset, offset:{ *:[i32] }:$offset)
        GIR_BuildMI, /*InsnID*/0, /*Opcode*/GIMT_Encode2(AMDGPU::BUFFER_ATOMIC_AND_X2_ADDR64_RTN),
        GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/0, // DstI[vdata]
        GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/2, // vdata_in
        GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/1, // vaddr
        GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/0, // srsrc
        GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/2, // soffset
        GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/3, // offset
        GIR_AddImm8, /*InsnID*/0, /*Imm*/1,
        GIR_MergeMemOperands, /*InsnID*/0, /*NumInsns*/1, /*MergeInsnID's*/0,
        GIR_ConstrainSelectedInstOperands, /*InsnID*/0,
        GIR_EraseFromParent, /*InsnID*/0,
        // GIR_Coverage, 4660,
        GIR_Done,
      // Label 2587: @168917
      GIM_Try, /*On fail goto*//*Label 2588*/ GIMT_Encode4(168989), // Rule ID 4664 //
        GIM_CheckMemoryAddressSpace, /*MI*/0, /*MMO*/0, /*NumAddrSpace*/3, /*AddrSpace*/1, /*AddrSpace*/4, /*AddrSpace*/6,
        GIM_CheckRegBankForClass, /*MI*/0, /*Op*/0, /*RC*/GIMT_Encode2(AMDGPU::AV_64RegClassID),
        GIM_CheckPointerToAny, /*MI*/0, /*Op*/1, /*SizeInBits*/0,
        GIM_CheckComplexPattern, /*MI*/0, /*Op*/1, /*Renderer*/GIMT_Encode2(0), GIMT_Encode2(GICP_gi_mubuf_addr64),
        // (atomic_load_and:{ *:[i64] } (MUBUFAddr64:{ *:[iPTR] } v4i32:{ *:[v4i32] }:$srsrc, i64:{ *:[i64] }:$vaddr, i32:{ *:[i32] }:$soffset, i32:{ *:[i32] }:$offset), i64:{ *:[i64] }:$vdata_in)<<P:Predicate_atomic_load_and_global_64>>  =>  (BUFFER_ATOMIC_AND_X2_VBUFFER_ADDR64_RTN:{ *:[i64] } anonymous_15036:{ *:[i64] }:$vdata_in, VReg_64:{ *:[i64] }:$vaddr, SReg_128:{ *:[v4i32] }:$srsrc, SCSrc_b32:{ *:[i32] }:$soffset, offset:{ *:[i32] }:$offset)
        GIR_BuildMI, /*InsnID*/0, /*Opcode*/GIMT_Encode2(AMDGPU::BUFFER_ATOMIC_AND_X2_VBUFFER_ADDR64_RTN),
        GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/0, // DstI[vdata]
        GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/2, // vdata_in
        GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/1, // vaddr
        GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/0, // srsrc
        GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/2, // soffset
        GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/3, // offset
        GIR_AddImm8, /*InsnID*/0, /*Imm*/1,
        GIR_MergeMemOperands, /*InsnID*/0, /*NumInsns*/1, /*MergeInsnID's*/0,
        GIR_ConstrainSelectedInstOperands, /*InsnID*/0,
        GIR_EraseFromParent, /*InsnID*/0,
        // GIR_Coverage, 4664,
        GIR_Done,
      // Label 2588: @168989
      GIM_Try, /*On fail goto*//*Label 2589*/ GIMT_Encode4(169052), // Rule ID 4661 //
        GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasUnrestrictedSOffset),
        GIM_CheckMemoryAddressSpace, /*MI*/0, /*MMO*/0, /*NumAddrSpace*/3, /*AddrSpace*/1, /*AddrSpace*/4, /*AddrSpace*/6,
        GIM_CheckHasNoUse, /*MI*/0,
        GIM_CheckPointerToAny, /*MI*/0, /*Op*/1, /*SizeInBits*/0,
        GIM_CheckComplexPattern, /*MI*/0, /*Op*/1, /*Renderer*/GIMT_Encode2(0), GIMT_Encode2(GICP_gi_mubuf_offset),
        // (atomic_load_and:{ *:[i64] } (MUBUFOffset:{ *:[iPTR] } v4i32:{ *:[v4i32] }:$srsrc, i32:{ *:[i32] }:$soffset, i32:{ *:[i32] }:$offset), i64:{ *:[i64] }:$vdata_in)<<P:Predicate_atomic_load_and_global_noret_64>>  =>  (BUFFER_ATOMIC_AND_X2_OFFSET anonymous_15036:{ *:[i64] }:$vdata_in, SReg_128:{ *:[v4i32] }:$srsrc, SCSrc_b32:{ *:[i32] }:$soffset, offset:{ *:[i32] }:$offset)
        GIR_BuildMI, /*InsnID*/0, /*Opcode*/GIMT_Encode2(AMDGPU::BUFFER_ATOMIC_AND_X2_OFFSET),
        GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/2, // vdata_in
        GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/0, // srsrc
        GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/1, // soffset
        GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/2, // offset
        GIR_AddImm8, /*InsnID*/0, /*Imm*/0,
        GIR_MergeMemOperands, /*InsnID*/0, /*NumInsns*/1, /*MergeInsnID's*/0,
        GIR_ConstrainSelectedInstOperands, /*InsnID*/0,
        GIR_EraseFromParent, /*InsnID*/0,
        // GIR_Coverage, 4661,
        GIR_Done,
      // Label 2589: @169052
      GIM_Try, /*On fail goto*//*Label 2590*/ GIMT_Encode4(169112), // Rule ID 4665 //
        GIM_CheckMemoryAddressSpace, /*MI*/0, /*MMO*/0, /*NumAddrSpace*/3, /*AddrSpace*/1, /*AddrSpace*/4, /*AddrSpace*/6,
        GIM_CheckHasNoUse, /*MI*/0,
        GIM_CheckPointerToAny, /*MI*/0, /*Op*/1, /*SizeInBits*/0,
        GIM_CheckComplexPattern, /*MI*/0, /*Op*/1, /*Renderer*/GIMT_Encode2(0), GIMT_Encode2(GICP_gi_mubuf_offset),
        // (atomic_load_and:{ *:[i64] } (MUBUFOffset:{ *:[iPTR] } v4i32:{ *:[v4i32] }:$srsrc, i32:{ *:[i32] }:$soffset, i32:{ *:[i32] }:$offset), i64:{ *:[i64] }:$vdata_in)<<P:Predicate_atomic_load_and_global_noret_64>>  =>  (BUFFER_ATOMIC_AND_X2_VBUFFER_OFFSET anonymous_15036:{ *:[i64] }:$vdata_in, SReg_128:{ *:[v4i32] }:$srsrc, SCSrc_b32:{ *:[i32] }:$soffset, offset:{ *:[i32] }:$offset)
        GIR_BuildMI, /*InsnID*/0, /*Opcode*/GIMT_Encode2(AMDGPU::BUFFER_ATOMIC_AND_X2_VBUFFER_OFFSET),
        GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/2, // vdata_in
        GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/0, // srsrc
        GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/1, // soffset
        GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/2, // offset
        GIR_AddImm8, /*InsnID*/0, /*Imm*/0,
        GIR_MergeMemOperands, /*InsnID*/0, /*NumInsns*/1, /*MergeInsnID's*/0,
        GIR_ConstrainSelectedInstOperands, /*InsnID*/0,
        GIR_EraseFromParent, /*InsnID*/0,
        // GIR_Coverage, 4665,
        GIR_Done,
      // Label 2590: @169112
      GIM_Try, /*On fail goto*//*Label 2591*/ GIMT_Encode4(169182), // Rule ID 4659 //
        GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasUnrestrictedSOffset),
        GIM_CheckMemoryAddressSpace, /*MI*/0, /*MMO*/0, /*NumAddrSpace*/3, /*AddrSpace*/1, /*AddrSpace*/4, /*AddrSpace*/6,
        GIM_CheckRegBankForClass, /*MI*/0, /*Op*/0, /*RC*/GIMT_Encode2(AMDGPU::AV_64RegClassID),
        GIM_CheckPointerToAny, /*MI*/0, /*Op*/1, /*SizeInBits*/0,
        GIM_CheckComplexPattern, /*MI*/0, /*Op*/1, /*Renderer*/GIMT_Encode2(0), GIMT_Encode2(GICP_gi_mubuf_offset),
        // (atomic_load_and:{ *:[i64] } (MUBUFOffset:{ *:[iPTR] } v4i32:{ *:[v4i32] }:$srsrc, i32:{ *:[i32] }:$soffset, i32:{ *:[i32] }:$offset), i64:{ *:[i64] }:$vdata_in)<<P:Predicate_atomic_load_and_global_64>>  =>  (BUFFER_ATOMIC_AND_X2_OFFSET_RTN:{ *:[i64] } anonymous_15036:{ *:[i64] }:$vdata_in, SReg_128:{ *:[v4i32] }:$srsrc, SCSrc_b32:{ *:[i32] }:$soffset, offset:{ *:[i32] }:$offset)
        GIR_BuildMI, /*InsnID*/0, /*Opcode*/GIMT_Encode2(AMDGPU::BUFFER_ATOMIC_AND_X2_OFFSET_RTN),
        GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/0, // DstI[vdata]
        GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/2, // vdata_in
        GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/0, // srsrc
        GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/1, // soffset
        GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/2, // offset
        GIR_AddImm8, /*InsnID*/0, /*Imm*/1,
        GIR_MergeMemOperands, /*InsnID*/0, /*NumInsns*/1, /*MergeInsnID's*/0,
        GIR_ConstrainSelectedInstOperands, /*InsnID*/0,
        GIR_EraseFromParent, /*InsnID*/0,
        // GIR_Coverage, 4659,
        GIR_Done,
      // Label 2591: @169182
      GIM_Try, /*On fail goto*//*Label 2592*/ GIMT_Encode4(169249), // Rule ID 4663 //
        GIM_CheckMemoryAddressSpace, /*MI*/0, /*MMO*/0, /*NumAddrSpace*/3, /*AddrSpace*/1, /*AddrSpace*/4, /*AddrSpace*/6,
        GIM_CheckRegBankForClass, /*MI*/0, /*Op*/0, /*RC*/GIMT_Encode2(AMDGPU::AV_64RegClassID),
        GIM_CheckPointerToAny, /*MI*/0, /*Op*/1, /*SizeInBits*/0,
        GIM_CheckComplexPattern, /*MI*/0, /*Op*/1, /*Renderer*/GIMT_Encode2(0), GIMT_Encode2(GICP_gi_mubuf_offset),
        // (atomic_load_and:{ *:[i64] } (MUBUFOffset:{ *:[iPTR] } v4i32:{ *:[v4i32] }:$srsrc, i32:{ *:[i32] }:$soffset, i32:{ *:[i32] }:$offset), i64:{ *:[i64] }:$vdata_in)<<P:Predicate_atomic_load_and_global_64>>  =>  (BUFFER_ATOMIC_AND_X2_VBUFFER_OFFSET_RTN:{ *:[i64] } anonymous_15036:{ *:[i64] }:$vdata_in, SReg_128:{ *:[v4i32] }:$srsrc, SCSrc_b32:{ *:[i32] }:$soffset, offset:{ *:[i32] }:$offset)
        GIR_BuildMI, /*InsnID*/0, /*Opcode*/GIMT_Encode2(AMDGPU::BUFFER_ATOMIC_AND_X2_VBUFFER_OFFSET_RTN),
        GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/0, // DstI[vdata]
        GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/2, // vdata_in
        GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/0, // srsrc
        GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/1, // soffset
        GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/2, // offset
        GIR_AddImm8, /*InsnID*/0, /*Imm*/1,
        GIR_MergeMemOperands, /*InsnID*/0, /*NumInsns*/1, /*MergeInsnID's*/0,
        GIR_ConstrainSelectedInstOperands, /*InsnID*/0,
        GIR_EraseFromParent, /*InsnID*/0,
        // GIR_Coverage, 4663,
        GIR_Done,
      // Label 2592: @169249
      GIM_Try, /*On fail goto*//*Label 2593*/ GIMT_Encode4(169305), // Rule ID 7016 //
        GIM_CheckFeatures, GIMT_Encode2(GIFBS_LDSRequiresM0Init),
        GIM_CheckMemoryAddressSpace, /*MI*/0, /*MMO*/0, /*NumAddrSpace*/1, /*AddrSpace*/3,
        GIM_CheckHasNoUse, /*MI*/0,
        GIM_CheckPointerToAny, /*MI*/0, /*Op*/1, /*SizeInBits*/0,
        GIM_CheckComplexPattern, /*MI*/0, /*Op*/1, /*Renderer*/GIMT_Encode2(0), GIMT_Encode2(GICP_gi_ds_1addr_1offset),
        // (atomic_load_and_glue:{ *:[i64] } (DS1Addr1Offset:{ *:[iPTR] } i32:{ *:[i32] }:$ptr, i32:{ *:[i32] }:$offset), i64:{ *:[i64] }:$value)<<P:Predicate_atomic_load_and_local_m0_noret_64>>  =>  (DS_AND_B64 ?:{ *:[i32] }:$ptr, anonymous_15036:{ *:[i64] }:$value, offset:{ *:[i32] }:$offset, 0:{ *:[i1] })
        GIR_BuildMI, /*InsnID*/0, /*Opcode*/GIMT_Encode2(AMDGPU::DS_AND_B64),
        GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/0, // ptr
        GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/2, // value
        GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/1, // offset
        GIR_AddImm8, /*InsnID*/0, /*Imm*/0,
        GIR_MergeMemOperands, /*InsnID*/0, /*NumInsns*/1, /*MergeInsnID's*/0,
        GIR_ConstrainSelectedInstOperands, /*InsnID*/0,
        GIR_EraseFromParent, /*InsnID*/0,
        // GIR_Coverage, 7016,
        GIR_Done,
      // Label 2593: @169305
      GIM_Try, /*On fail goto*//*Label 2594*/ GIMT_Encode4(169361), // Rule ID 7018 //
        GIM_CheckFeatures, GIMT_Encode2(GIFBS_NotLDSRequiresM0Init),
        GIM_CheckMemoryAddressSpace, /*MI*/0, /*MMO*/0, /*NumAddrSpace*/1, /*AddrSpace*/3,
        GIM_CheckHasNoUse, /*MI*/0,
        GIM_CheckPointerToAny, /*MI*/0, /*Op*/1, /*SizeInBits*/0,
        GIM_CheckComplexPattern, /*MI*/0, /*Op*/1, /*Renderer*/GIMT_Encode2(0), GIMT_Encode2(GICP_gi_ds_1addr_1offset),
        // (atomic_load_and:{ *:[i64] } (DS1Addr1Offset:{ *:[iPTR] } i32:{ *:[i32] }:$ptr, i32:{ *:[i32] }:$offset), i64:{ *:[i64] }:$value)<<P:Predicate_atomic_load_and_local_noret_64>>  =>  (DS_AND_B64_gfx9 ?:{ *:[i32] }:$ptr, anonymous_15036:{ *:[i64] }:$value, offset:{ *:[i32] }:$offset, 0:{ *:[i1] })
        GIR_BuildMI, /*InsnID*/0, /*Opcode*/GIMT_Encode2(AMDGPU::DS_AND_B64_gfx9),
        GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/0, // ptr
        GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/2, // value
        GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/1, // offset
        GIR_AddImm8, /*InsnID*/0, /*Imm*/0,
        GIR_MergeMemOperands, /*InsnID*/0, /*NumInsns*/1, /*MergeInsnID's*/0,
        GIR_ConstrainSelectedInstOperands, /*InsnID*/0,
        GIR_EraseFromParent, /*InsnID*/0,
        // GIR_Coverage, 7018,
        GIR_Done,
      // Label 2594: @169361
      GIM_Try, /*On fail goto*//*Label 2595*/ GIMT_Encode4(169417), // Rule ID 7020 //
        GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasGDS),
        GIM_CheckMemoryAddressSpace, /*MI*/0, /*MMO*/0, /*NumAddrSpace*/1, /*AddrSpace*/2,
        GIM_CheckHasNoUse, /*MI*/0,
        GIM_CheckPointerToAny, /*MI*/0, /*Op*/1, /*SizeInBits*/0,
        GIM_CheckComplexPattern, /*MI*/0, /*Op*/1, /*Renderer*/GIMT_Encode2(0), GIMT_Encode2(GICP_gi_ds_1addr_1offset),
        // (atomic_load_and_glue:{ *:[i64] } (DS1Addr1Offset:{ *:[iPTR] } i32:{ *:[i32] }:$ptr, i32:{ *:[i32] }:$offset), i64:{ *:[i64] }:$value)<<P:Predicate_atomic_load_and_region_m0_noret_64>>  =>  (DS_AND_B64 ?:{ *:[i32] }:$ptr, anonymous_15036:{ *:[i64] }:$value, offset:{ *:[i32] }:$offset, 1:{ *:[i1] })
        GIR_BuildMI, /*InsnID*/0, /*Opcode*/GIMT_Encode2(AMDGPU::DS_AND_B64),
        GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/0, // ptr
        GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/2, // value
        GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/1, // offset
        GIR_AddImm8, /*InsnID*/0, /*Imm*/1,
        GIR_MergeMemOperands, /*InsnID*/0, /*NumInsns*/1, /*MergeInsnID's*/0,
        GIR_ConstrainSelectedInstOperands, /*InsnID*/0,
        GIR_EraseFromParent, /*InsnID*/0,
        // GIR_Coverage, 7020,
        GIR_Done,
      // Label 2595: @169417
      GIM_Try, /*On fail goto*//*Label 2596*/ GIMT_Encode4(169480), // Rule ID 7015 //
        GIM_CheckFeatures, GIMT_Encode2(GIFBS_LDSRequiresM0Init),
        GIM_CheckMemoryAddressSpace, /*MI*/0, /*MMO*/0, /*NumAddrSpace*/1, /*AddrSpace*/3,
        GIM_CheckRegBankForClass, /*MI*/0, /*Op*/0, /*RC*/GIMT_Encode2(AMDGPU::AV_64RegClassID),
        GIM_CheckPointerToAny, /*MI*/0, /*Op*/1, /*SizeInBits*/0,
        GIM_CheckComplexPattern, /*MI*/0, /*Op*/1, /*Renderer*/GIMT_Encode2(0), GIMT_Encode2(GICP_gi_ds_1addr_1offset),
        // (atomic_load_and_glue:{ *:[i64] } (DS1Addr1Offset:{ *:[iPTR] } i32:{ *:[i32] }:$ptr, i32:{ *:[i32] }:$offset), i64:{ *:[i64] }:$value)<<P:Predicate_atomic_load_and_local_m0_64>>  =>  (DS_AND_RTN_B64:{ *:[i64] } ?:{ *:[i32] }:$ptr, anonymous_15036:{ *:[i64] }:$value, offset:{ *:[i32] }:$offset, 0:{ *:[i1] })
        GIR_BuildMI, /*InsnID*/0, /*Opcode*/GIMT_Encode2(AMDGPU::DS_AND_RTN_B64),
        GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/0, // DstI[vdst]
        GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/0, // ptr
        GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/2, // value
        GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/1, // offset
        GIR_AddImm8, /*InsnID*/0, /*Imm*/0,
        GIR_MergeMemOperands, /*InsnID*/0, /*NumInsns*/1, /*MergeInsnID's*/0,
        GIR_ConstrainSelectedInstOperands, /*InsnID*/0,
        GIR_EraseFromParent, /*InsnID*/0,
        // GIR_Coverage, 7015,
        GIR_Done,
      // Label 2596: @169480
      GIM_Try, /*On fail goto*//*Label 2597*/ GIMT_Encode4(169543), // Rule ID 7017 //
        GIM_CheckFeatures, GIMT_Encode2(GIFBS_NotLDSRequiresM0Init),
        GIM_CheckMemoryAddressSpace, /*MI*/0, /*MMO*/0, /*NumAddrSpace*/1, /*AddrSpace*/3,
        GIM_CheckRegBankForClass, /*MI*/0, /*Op*/0, /*RC*/GIMT_Encode2(AMDGPU::AV_64RegClassID),
        GIM_CheckPointerToAny, /*MI*/0, /*Op*/1, /*SizeInBits*/0,
        GIM_CheckComplexPattern, /*MI*/0, /*Op*/1, /*Renderer*/GIMT_Encode2(0), GIMT_Encode2(GICP_gi_ds_1addr_1offset),
        // (atomic_load_and:{ *:[i64] } (DS1Addr1Offset:{ *:[iPTR] } i32:{ *:[i32] }:$ptr, i32:{ *:[i32] }:$offset), i64:{ *:[i64] }:$value)<<P:Predicate_atomic_load_and_local_64>>  =>  (DS_AND_RTN_B64_gfx9:{ *:[i64] } ?:{ *:[i32] }:$ptr, anonymous_15036:{ *:[i64] }:$value, offset:{ *:[i32] }:$offset, 0:{ *:[i1] })
        GIR_BuildMI, /*InsnID*/0, /*Opcode*/GIMT_Encode2(AMDGPU::DS_AND_RTN_B64_gfx9),
        GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/0, // DstI[vdst]
        GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/0, // ptr
        GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/2, // value
        GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/1, // offset
        GIR_AddImm8, /*InsnID*/0, /*Imm*/0,
        GIR_MergeMemOperands, /*InsnID*/0, /*NumInsns*/1, /*MergeInsnID's*/0,
        GIR_ConstrainSelectedInstOperands, /*InsnID*/0,
        GIR_EraseFromParent, /*InsnID*/0,
        // GIR_Coverage, 7017,
        GIR_Done,
      // Label 2597: @169543
      GIM_Try, /*On fail goto*//*Label 2598*/ GIMT_Encode4(169606), // Rule ID 7019 //
        GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasGDS),
        GIM_CheckMemoryAddressSpace, /*MI*/0, /*MMO*/0, /*NumAddrSpace*/1, /*AddrSpace*/2,
        GIM_CheckRegBankForClass, /*MI*/0, /*Op*/0, /*RC*/GIMT_Encode2(AMDGPU::AV_64RegClassID),
        GIM_CheckPointerToAny, /*MI*/0, /*Op*/1, /*SizeInBits*/0,
        GIM_CheckComplexPattern, /*MI*/0, /*Op*/1, /*Renderer*/GIMT_Encode2(0), GIMT_Encode2(GICP_gi_ds_1addr_1offset),
        // (atomic_load_and_glue:{ *:[i64] } (DS1Addr1Offset:{ *:[iPTR] } i32:{ *:[i32] }:$ptr, i32:{ *:[i32] }:$offset), i64:{ *:[i64] }:$value)<<P:Predicate_atomic_load_and_region_m0_64>>  =>  (DS_AND_RTN_B64:{ *:[i64] } ?:{ *:[i32] }:$ptr, anonymous_15036:{ *:[i64] }:$value, offset:{ *:[i32] }:$offset, 1:{ *:[i1] })
        GIR_BuildMI, /*InsnID*/0, /*Opcode*/GIMT_Encode2(AMDGPU::DS_AND_RTN_B64),
        GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/0, // DstI[vdst]
        GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/0, // ptr
        GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/2, // value
        GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/1, // offset
        GIR_AddImm8, /*InsnID*/0, /*Imm*/1,
        GIR_MergeMemOperands, /*InsnID*/0, /*NumInsns*/1, /*MergeInsnID's*/0,
        GIR_ConstrainSelectedInstOperands, /*InsnID*/0,
        GIR_EraseFromParent, /*InsnID*/0,
        // GIR_Coverage, 7019,
        GIR_Done,
      // Label 2598: @169606
      GIM_Try, /*On fail goto*//*Label 2599*/ GIMT_Encode4(169669), // Rule ID 3219 //
        GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasFlatGlobalInsts),
        GIM_CheckMemoryAddressSpace, /*MI*/0, /*MMO*/0, /*NumAddrSpace*/3, /*AddrSpace*/1, /*AddrSpace*/4, /*AddrSpace*/6,
        GIM_CheckHasNoUse, /*MI*/0,
        GIM_CheckPointerToAny, /*MI*/0, /*Op*/1, /*SizeInBits*/0,
        GIM_CheckComplexPattern, /*MI*/0, /*Op*/1, /*Renderer*/GIMT_Encode2(0), GIMT_Encode2(GICP_gi_global_saddr),
        // (atomic_load_and:{ *:[i64] } (GlobalSAddr:{ *:[iPTR] } SReg_64:{ *:[i64] }:$saddr, VGPR_32:{ *:[i32] }:$voffset, i32:{ *:[i32] }:$offset), i64:{ *:[i64] }:$data)<<P:Predicate_atomic_load_and_global_noret_64>>  =>  (GLOBAL_ATOMIC_AND_X2_SADDR ?:{ *:[i32] }:$voffset, anonymous_15036:{ *:[i64] }:$data, ?:{ *:[i64] }:$saddr, ?:{ *:[i32] }:$offset)
        GIR_BuildMI, /*InsnID*/0, /*Opcode*/GIMT_Encode2(AMDGPU::GLOBAL_ATOMIC_AND_X2_SADDR),
        GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/1, // voffset
        GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/2, // data
        GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/0, // saddr
        GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/2, // offset
        GIR_AddImm8, /*InsnID*/0, /*Imm*/0,
        GIR_MergeMemOperands, /*InsnID*/0, /*NumInsns*/1, /*MergeInsnID's*/0,
        GIR_ConstrainSelectedInstOperands, /*InsnID*/0,
        GIR_EraseFromParent, /*InsnID*/0,
        // GIR_Coverage, 3219,
        GIR_Done,
      // Label 2599: @169669
      GIM_Try, /*On fail goto*//*Label 2600*/ GIMT_Encode4(169739), // Rule ID 3221 //
        GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasFlatGlobalInsts),
        GIM_CheckMemoryAddressSpace, /*MI*/0, /*MMO*/0, /*NumAddrSpace*/3, /*AddrSpace*/1, /*AddrSpace*/4, /*AddrSpace*/6,
        GIM_CheckRegBankForClass, /*MI*/0, /*Op*/0, /*RC*/GIMT_Encode2(AMDGPU::AV_64RegClassID),
        GIM_CheckPointerToAny, /*MI*/0, /*Op*/1, /*SizeInBits*/0,
        GIM_CheckComplexPattern, /*MI*/0, /*Op*/1, /*Renderer*/GIMT_Encode2(0), GIMT_Encode2(GICP_gi_global_saddr),
        // (atomic_load_and:{ *:[i64] } (GlobalSAddr:{ *:[iPTR] } SReg_64:{ *:[i64] }:$saddr, VGPR_32:{ *:[i32] }:$voffset, i32:{ *:[i32] }:$offset), i64:{ *:[i64] }:$data)<<P:Predicate_atomic_load_and_global_64>>  =>  (GLOBAL_ATOMIC_AND_X2_SADDR_RTN:{ *:[i64] } ?:{ *:[i32] }:$voffset, anonymous_15036:{ *:[i64] }:$data, ?:{ *:[i64] }:$saddr, ?:{ *:[i32] }:$offset)
        GIR_BuildMI, /*InsnID*/0, /*Opcode*/GIMT_Encode2(AMDGPU::GLOBAL_ATOMIC_AND_X2_SADDR_RTN),
        GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/0, // DstI[vdst]
        GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/1, // voffset
        GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/2, // data
        GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/0, // saddr
        GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/2, // offset
        GIR_AddImm8, /*InsnID*/0, /*Imm*/1,
        GIR_MergeMemOperands, /*InsnID*/0, /*NumInsns*/1, /*MergeInsnID's*/0,
        GIR_ConstrainSelectedInstOperands, /*InsnID*/0,
        GIR_EraseFromParent, /*InsnID*/0,
        // GIR_Coverage, 3221,
        GIR_Done,
      // Label 2600: @169739
      GIM_Try, /*On fail goto*//*Label 2601*/ GIMT_Encode4(169797), // Rule ID 3218 //
        GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasFlatGlobalInsts),
        GIM_CheckMemoryAddressSpace, /*MI*/0, /*MMO*/0, /*NumAddrSpace*/3, /*AddrSpace*/1, /*AddrSpace*/4, /*AddrSpace*/6,
        GIM_CheckHasNoUse, /*MI*/0,
        GIM_CheckPointerToAny, /*MI*/0, /*Op*/1, /*SizeInBits*/0,
        GIM_CheckComplexPattern, /*MI*/0, /*Op*/1, /*Renderer*/GIMT_Encode2(0), GIMT_Encode2(GICP_gi_global_offset),
        // (atomic_load_and:{ *:[i64] } (GlobalOffset:{ *:[iPTR] } i64:{ *:[i64] }:$vaddr, i32:{ *:[i32] }:$offset), i64:{ *:[i64] }:$data)<<P:Predicate_atomic_load_and_global_noret_64>>  =>  (GLOBAL_ATOMIC_AND_X2 VReg_64:{ *:[i64] }:$vaddr, anonymous_15036:{ *:[i64] }:$data, ?:{ *:[i32] }:$offset)
        GIR_BuildMI, /*InsnID*/0, /*Opcode*/GIMT_Encode2(AMDGPU::GLOBAL_ATOMIC_AND_X2),
        GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/0, // vaddr
        GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/2, // data
        GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/1, // offset
        GIR_AddImm8, /*InsnID*/0, /*Imm*/0,
        GIR_MergeMemOperands, /*InsnID*/0, /*NumInsns*/1, /*MergeInsnID's*/0,
        GIR_ConstrainSelectedInstOperands, /*InsnID*/0,
        GIR_EraseFromParent, /*InsnID*/0,
        // GIR_Coverage, 3218,
        GIR_Done,
      // Label 2601: @169797
      GIM_Try, /*On fail goto*//*Label 2602*/ GIMT_Encode4(169862), // Rule ID 3220 //
        GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasFlatGlobalInsts),
        GIM_CheckMemoryAddressSpace, /*MI*/0, /*MMO*/0, /*NumAddrSpace*/3, /*AddrSpace*/1, /*AddrSpace*/4, /*AddrSpace*/6,
        GIM_CheckRegBankForClass, /*MI*/0, /*Op*/0, /*RC*/GIMT_Encode2(AMDGPU::AV_64RegClassID),
        GIM_CheckPointerToAny, /*MI*/0, /*Op*/1, /*SizeInBits*/0,
        GIM_CheckComplexPattern, /*MI*/0, /*Op*/1, /*Renderer*/GIMT_Encode2(0), GIMT_Encode2(GICP_gi_global_offset),
        // (atomic_load_and:{ *:[i64] } (GlobalOffset:{ *:[iPTR] } i64:{ *:[i64] }:$vaddr, i32:{ *:[i32] }:$offset), i64:{ *:[i64] }:$data)<<P:Predicate_atomic_load_and_global_64>>  =>  (GLOBAL_ATOMIC_AND_X2_RTN:{ *:[i64] } VReg_64:{ *:[i64] }:$vaddr, anonymous_15036:{ *:[i64] }:$data, ?:{ *:[i32] }:$offset)
        GIR_BuildMI, /*InsnID*/0, /*Opcode*/GIMT_Encode2(AMDGPU::GLOBAL_ATOMIC_AND_X2_RTN),
        GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/0, // DstI[vdst]
        GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/0, // vaddr
        GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/2, // data
        GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/1, // offset
        GIR_AddImm8, /*InsnID*/0, /*Imm*/1,
        GIR_MergeMemOperands, /*InsnID*/0, /*NumInsns*/1, /*MergeInsnID's*/0,
        GIR_ConstrainSelectedInstOperands, /*InsnID*/0,
        GIR_EraseFromParent, /*InsnID*/0,
        // GIR_Coverage, 3220,
        GIR_Done,
      // Label 2602: @169862
      GIM_Try, /*On fail goto*//*Label 2603*/ GIMT_Encode4(169921), // Rule ID 2862 //
        GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasFlatAddressSpace),
        GIM_CheckMemoryAddressSpace, /*MI*/0, /*MMO*/0, /*NumAddrSpace*/4, /*AddrSpace*/0, /*AddrSpace*/1, /*AddrSpace*/4, /*AddrSpace*/6,
        GIM_CheckHasNoUse, /*MI*/0,
        GIM_CheckPointerToAny, /*MI*/0, /*Op*/1, /*SizeInBits*/0,
        GIM_CheckComplexPattern, /*MI*/0, /*Op*/1, /*Renderer*/GIMT_Encode2(0), GIMT_Encode2(GICP_gi_flat_offset),
        // (atomic_load_and:{ *:[i64] } (FlatOffset:{ *:[iPTR] } i64:{ *:[i64] }:$vaddr, i32:{ *:[i32] }:$offset), i64:{ *:[i64] }:$data)<<P:Predicate_atomic_load_and_flat_noret_64>>  =>  (FLAT_ATOMIC_AND_X2 VReg_64:{ *:[i64] }:$vaddr, anonymous_15036:{ *:[i64] }:$data, ?:{ *:[i32] }:$offset)
        GIR_BuildMI, /*InsnID*/0, /*Opcode*/GIMT_Encode2(AMDGPU::FLAT_ATOMIC_AND_X2),
        GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/0, // vaddr
        GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/2, // data
        GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/1, // offset
        GIR_AddImm8, /*InsnID*/0, /*Imm*/0,
        GIR_MergeMemOperands, /*InsnID*/0, /*NumInsns*/1, /*MergeInsnID's*/0,
        GIR_ConstrainSelectedInstOperands, /*InsnID*/0,
        GIR_EraseFromParent, /*InsnID*/0,
        // GIR_Coverage, 2862,
        GIR_Done,
      // Label 2603: @169921
      GIM_Try, /*On fail goto*//*Label 2604*/ GIMT_Encode4(169979), // Rule ID 2914 //
        GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasFlatAddressSpace),
        GIM_CheckMemoryAddressSpace, /*MI*/0, /*MMO*/0, /*NumAddrSpace*/3, /*AddrSpace*/1, /*AddrSpace*/4, /*AddrSpace*/6,
        GIM_CheckHasNoUse, /*MI*/0,
        GIM_CheckPointerToAny, /*MI*/0, /*Op*/1, /*SizeInBits*/0,
        GIM_CheckComplexPattern, /*MI*/0, /*Op*/1, /*Renderer*/GIMT_Encode2(0), GIMT_Encode2(GICP_gi_flat_offset),
        // (atomic_load_and:{ *:[i64] } (FlatOffset:{ *:[iPTR] } i64:{ *:[i64] }:$vaddr, i32:{ *:[i32] }:$offset), i64:{ *:[i64] }:$data)<<P:Predicate_atomic_load_and_global_noret_64>>  =>  (FLAT_ATOMIC_AND_X2 VReg_64:{ *:[i64] }:$vaddr, anonymous_15036:{ *:[i64] }:$data, ?:{ *:[i32] }:$offset)
        GIR_BuildMI, /*InsnID*/0, /*Opcode*/GIMT_Encode2(AMDGPU::FLAT_ATOMIC_AND_X2),
        GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/0, // vaddr
        GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/2, // data
        GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/1, // offset
        GIR_AddImm8, /*InsnID*/0, /*Imm*/0,
        GIR_MergeMemOperands, /*InsnID*/0, /*NumInsns*/1, /*MergeInsnID's*/0,
        GIR_ConstrainSelectedInstOperands, /*InsnID*/0,
        GIR_EraseFromParent, /*InsnID*/0,
        // GIR_Coverage, 2914,
        GIR_Done,
      // Label 2604: @169979
      GIM_Try, /*On fail goto*//*Label 2605*/ GIMT_Encode4(170045), // Rule ID 2861 //
        GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasFlatAddressSpace),
        GIM_CheckMemoryAddressSpace, /*MI*/0, /*MMO*/0, /*NumAddrSpace*/4, /*AddrSpace*/0, /*AddrSpace*/1, /*AddrSpace*/4, /*AddrSpace*/6,
        GIM_CheckRegBankForClass, /*MI*/0, /*Op*/0, /*RC*/GIMT_Encode2(AMDGPU::AV_64RegClassID),
        GIM_CheckPointerToAny, /*MI*/0, /*Op*/1, /*SizeInBits*/0,
        GIM_CheckComplexPattern, /*MI*/0, /*Op*/1, /*Renderer*/GIMT_Encode2(0), GIMT_Encode2(GICP_gi_flat_offset),
        // (atomic_load_and:{ *:[i64] } (FlatOffset:{ *:[iPTR] } i64:{ *:[i64] }:$vaddr, i32:{ *:[i32] }:$offset), i64:{ *:[i64] }:$data)<<P:Predicate_atomic_load_and_flat_64>>  =>  (FLAT_ATOMIC_AND_X2_RTN:{ *:[i64] } VReg_64:{ *:[i64] }:$vaddr, anonymous_15036:{ *:[i64] }:$data, ?:{ *:[i32] }:$offset)
        GIR_BuildMI, /*InsnID*/0, /*Opcode*/GIMT_Encode2(AMDGPU::FLAT_ATOMIC_AND_X2_RTN),
        GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/0, // DstI[vdst]
        GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/0, // vaddr
        GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/2, // data
        GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/1, // offset
        GIR_AddImm8, /*InsnID*/0, /*Imm*/1,
        GIR_MergeMemOperands, /*InsnID*/0, /*NumInsns*/1, /*MergeInsnID's*/0,
        GIR_ConstrainSelectedInstOperands, /*InsnID*/0,
        GIR_EraseFromParent, /*InsnID*/0,
        // GIR_Coverage, 2861,
        GIR_Done,
      // Label 2605: @170045
      GIM_Try, /*On fail goto*//*Label 2606*/ GIMT_Encode4(170110), // Rule ID 2913 //
        GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasFlatAddressSpace),
        GIM_CheckMemoryAddressSpace, /*MI*/0, /*MMO*/0, /*NumAddrSpace*/3, /*AddrSpace*/1, /*AddrSpace*/4, /*AddrSpace*/6,
        GIM_CheckRegBankForClass, /*MI*/0, /*Op*/0, /*RC*/GIMT_Encode2(AMDGPU::AV_64RegClassID),
        GIM_CheckPointerToAny, /*MI*/0, /*Op*/1, /*SizeInBits*/0,
        GIM_CheckComplexPattern, /*MI*/0, /*Op*/1, /*Renderer*/GIMT_Encode2(0), GIMT_Encode2(GICP_gi_flat_offset),
        // (atomic_load_and:{ *:[i64] } (FlatOffset:{ *:[iPTR] } i64:{ *:[i64] }:$vaddr, i32:{ *:[i32] }:$offset), i64:{ *:[i64] }:$data)<<P:Predicate_atomic_load_and_global_64>>  =>  (FLAT_ATOMIC_AND_X2_RTN:{ *:[i64] } VReg_64:{ *:[i64] }:$vaddr, anonymous_15036:{ *:[i64] }:$data, ?:{ *:[i32] }:$offset)
        GIR_BuildMI, /*InsnID*/0, /*Opcode*/GIMT_Encode2(AMDGPU::FLAT_ATOMIC_AND_X2_RTN),
        GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/0, // DstI[vdst]
        GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/0, // vaddr
        GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/2, // data
        GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/1, // offset
        GIR_AddImm8, /*InsnID*/0, /*Imm*/1,
        GIR_MergeMemOperands, /*InsnID*/0, /*NumInsns*/1, /*MergeInsnID's*/0,
        GIR_ConstrainSelectedInstOperands, /*InsnID*/0,
        GIR_EraseFromParent, /*InsnID*/0,
        // GIR_Coverage, 2913,
        GIR_Done,
      // Label 2606: @170110
      GIM_Reject,
    // Label 2584: @170111
    GIM_Reject,
    // Label 2560: @170112
    GIM_Reject,
    // Label 21: @170113
    GIM_SwitchType, /*MI*/0, /*Op*/0, /*[*/GIMT_Encode2(9), GIMT_Encode2(11), /*)*//*default:*//*Label 2609*/ GIMT_Encode4(172956),
    /*GILLT_s32*//*Label 2607*/ GIMT_Encode4(170132),
    /*GILLT_s64*//*Label 2608*/ GIMT_Encode4(171544),
    // Label 2607: @170132
    GIM_Try, /*On fail goto*//*Label 2610*/ GIMT_Encode4(171543),
      GIM_CheckType, /*MI*/0, /*Op*/2, /*Type*/GILLT_s32,
      GIM_Try, /*On fail goto*//*Label 2611*/ GIMT_Encode4(170209), // Rule ID 4574 //
        GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasUnrestrictedSOffset),
        GIM_CheckMemoryAddressSpace, /*MI*/0, /*MMO*/0, /*NumAddrSpace*/3, /*AddrSpace*/1, /*AddrSpace*/4, /*AddrSpace*/6,
        GIM_CheckHasNoUse, /*MI*/0,
        GIM_CheckPointerToAny, /*MI*/0, /*Op*/1, /*SizeInBits*/0,
        GIM_CheckComplexPattern, /*MI*/0, /*Op*/1, /*Renderer*/GIMT_Encode2(0), GIMT_Encode2(GICP_gi_mubuf_addr64),
        // (atomic_load_or:{ *:[i32] } (MUBUFAddr64:{ *:[iPTR] } v4i32:{ *:[v4i32] }:$srsrc, i64:{ *:[i64] }:$vaddr, i32:{ *:[i32] }:$soffset, i32:{ *:[i32] }:$offset), i32:{ *:[i32] }:$vdata_in)<<P:Predicate_atomic_load_or_global_noret_32>>  =>  (BUFFER_ATOMIC_OR_ADDR64 anonymous_15037:{ *:[i32] }:$vdata_in, VReg_64:{ *:[i64] }:$vaddr, SReg_128:{ *:[v4i32] }:$srsrc, SCSrc_b32:{ *:[i32] }:$soffset, offset:{ *:[i32] }:$offset)
        GIR_BuildMI, /*InsnID*/0, /*Opcode*/GIMT_Encode2(AMDGPU::BUFFER_ATOMIC_OR_ADDR64),
        GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/2, // vdata_in
        GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/1, // vaddr
        GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/0, // srsrc
        GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/2, // soffset
        GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/3, // offset
        GIR_AddImm8, /*InsnID*/0, /*Imm*/0,
        GIR_MergeMemOperands, /*InsnID*/0, /*NumInsns*/1, /*MergeInsnID's*/0,
        GIR_ConstrainSelectedInstOperands, /*InsnID*/0,
        GIR_EraseFromParent, /*InsnID*/0,
        // GIR_Coverage, 4574,
        GIR_Done,
      // Label 2611: @170209
      GIM_Try, /*On fail goto*//*Label 2612*/ GIMT_Encode4(170274), // Rule ID 4578 //
        GIM_CheckMemoryAddressSpace, /*MI*/0, /*MMO*/0, /*NumAddrSpace*/3, /*AddrSpace*/1, /*AddrSpace*/4, /*AddrSpace*/6,
        GIM_CheckHasNoUse, /*MI*/0,
        GIM_CheckPointerToAny, /*MI*/0, /*Op*/1, /*SizeInBits*/0,
        GIM_CheckComplexPattern, /*MI*/0, /*Op*/1, /*Renderer*/GIMT_Encode2(0), GIMT_Encode2(GICP_gi_mubuf_addr64),
        // (atomic_load_or:{ *:[i32] } (MUBUFAddr64:{ *:[iPTR] } v4i32:{ *:[v4i32] }:$srsrc, i64:{ *:[i64] }:$vaddr, i32:{ *:[i32] }:$soffset, i32:{ *:[i32] }:$offset), i32:{ *:[i32] }:$vdata_in)<<P:Predicate_atomic_load_or_global_noret_32>>  =>  (BUFFER_ATOMIC_OR_VBUFFER_ADDR64 anonymous_15037:{ *:[i32] }:$vdata_in, VReg_64:{ *:[i64] }:$vaddr, SReg_128:{ *:[v4i32] }:$srsrc, SCSrc_b32:{ *:[i32] }:$soffset, offset:{ *:[i32] }:$offset)
        GIR_BuildMI, /*InsnID*/0, /*Opcode*/GIMT_Encode2(AMDGPU::BUFFER_ATOMIC_OR_VBUFFER_ADDR64),
        GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/2, // vdata_in
        GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/1, // vaddr
        GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/0, // srsrc
        GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/2, // soffset
        GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/3, // offset
        GIR_AddImm8, /*InsnID*/0, /*Imm*/0,
        GIR_MergeMemOperands, /*InsnID*/0, /*NumInsns*/1, /*MergeInsnID's*/0,
        GIR_ConstrainSelectedInstOperands, /*InsnID*/0,
        GIR_EraseFromParent, /*InsnID*/0,
        // GIR_Coverage, 4578,
        GIR_Done,
      // Label 2612: @170274
      GIM_Try, /*On fail goto*//*Label 2613*/ GIMT_Encode4(170349), // Rule ID 4572 //
        GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasUnrestrictedSOffset),
        GIM_CheckMemoryAddressSpace, /*MI*/0, /*MMO*/0, /*NumAddrSpace*/3, /*AddrSpace*/1, /*AddrSpace*/4, /*AddrSpace*/6,
        GIM_CheckRegBankForClass, /*MI*/0, /*Op*/0, /*RC*/GIMT_Encode2(AMDGPU::AV_32RegClassID),
        GIM_CheckPointerToAny, /*MI*/0, /*Op*/1, /*SizeInBits*/0,
        GIM_CheckComplexPattern, /*MI*/0, /*Op*/1, /*Renderer*/GIMT_Encode2(0), GIMT_Encode2(GICP_gi_mubuf_addr64),
        // (atomic_load_or:{ *:[i32] } (MUBUFAddr64:{ *:[iPTR] } v4i32:{ *:[v4i32] }:$srsrc, i64:{ *:[i64] }:$vaddr, i32:{ *:[i32] }:$soffset, i32:{ *:[i32] }:$offset), i32:{ *:[i32] }:$vdata_in)<<P:Predicate_atomic_load_or_global_32>>  =>  (BUFFER_ATOMIC_OR_ADDR64_RTN:{ *:[i32] } anonymous_15037:{ *:[i32] }:$vdata_in, VReg_64:{ *:[i64] }:$vaddr, SReg_128:{ *:[v4i32] }:$srsrc, SCSrc_b32:{ *:[i32] }:$soffset, offset:{ *:[i32] }:$offset)
        GIR_BuildMI, /*InsnID*/0, /*Opcode*/GIMT_Encode2(AMDGPU::BUFFER_ATOMIC_OR_ADDR64_RTN),
        GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/0, // DstI[vdata]
        GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/2, // vdata_in
        GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/1, // vaddr
        GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/0, // srsrc
        GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/2, // soffset
        GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/3, // offset
        GIR_AddImm8, /*InsnID*/0, /*Imm*/1,
        GIR_MergeMemOperands, /*InsnID*/0, /*NumInsns*/1, /*MergeInsnID's*/0,
        GIR_ConstrainSelectedInstOperands, /*InsnID*/0,
        GIR_EraseFromParent, /*InsnID*/0,
        // GIR_Coverage, 4572,
        GIR_Done,
      // Label 2613: @170349
      GIM_Try, /*On fail goto*//*Label 2614*/ GIMT_Encode4(170421), // Rule ID 4576 //
        GIM_CheckMemoryAddressSpace, /*MI*/0, /*MMO*/0, /*NumAddrSpace*/3, /*AddrSpace*/1, /*AddrSpace*/4, /*AddrSpace*/6,
        GIM_CheckRegBankForClass, /*MI*/0, /*Op*/0, /*RC*/GIMT_Encode2(AMDGPU::AV_32RegClassID),
        GIM_CheckPointerToAny, /*MI*/0, /*Op*/1, /*SizeInBits*/0,
        GIM_CheckComplexPattern, /*MI*/0, /*Op*/1, /*Renderer*/GIMT_Encode2(0), GIMT_Encode2(GICP_gi_mubuf_addr64),
        // (atomic_load_or:{ *:[i32] } (MUBUFAddr64:{ *:[iPTR] } v4i32:{ *:[v4i32] }:$srsrc, i64:{ *:[i64] }:$vaddr, i32:{ *:[i32] }:$soffset, i32:{ *:[i32] }:$offset), i32:{ *:[i32] }:$vdata_in)<<P:Predicate_atomic_load_or_global_32>>  =>  (BUFFER_ATOMIC_OR_VBUFFER_ADDR64_RTN:{ *:[i32] } anonymous_15037:{ *:[i32] }:$vdata_in, VReg_64:{ *:[i64] }:$vaddr, SReg_128:{ *:[v4i32] }:$srsrc, SCSrc_b32:{ *:[i32] }:$soffset, offset:{ *:[i32] }:$offset)
        GIR_BuildMI, /*InsnID*/0, /*Opcode*/GIMT_Encode2(AMDGPU::BUFFER_ATOMIC_OR_VBUFFER_ADDR64_RTN),
        GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/0, // DstI[vdata]
        GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/2, // vdata_in
        GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/1, // vaddr
        GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/0, // srsrc
        GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/2, // soffset
        GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/3, // offset
        GIR_AddImm8, /*InsnID*/0, /*Imm*/1,
        GIR_MergeMemOperands, /*InsnID*/0, /*NumInsns*/1, /*MergeInsnID's*/0,
        GIR_ConstrainSelectedInstOperands, /*InsnID*/0,
        GIR_EraseFromParent, /*InsnID*/0,
        // GIR_Coverage, 4576,
        GIR_Done,
      // Label 2614: @170421
      GIM_Try, /*On fail goto*//*Label 2615*/ GIMT_Encode4(170484), // Rule ID 4573 //
        GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasUnrestrictedSOffset),
        GIM_CheckMemoryAddressSpace, /*MI*/0, /*MMO*/0, /*NumAddrSpace*/3, /*AddrSpace*/1, /*AddrSpace*/4, /*AddrSpace*/6,
        GIM_CheckHasNoUse, /*MI*/0,
        GIM_CheckPointerToAny, /*MI*/0, /*Op*/1, /*SizeInBits*/0,
        GIM_CheckComplexPattern, /*MI*/0, /*Op*/1, /*Renderer*/GIMT_Encode2(0), GIMT_Encode2(GICP_gi_mubuf_offset),
        // (atomic_load_or:{ *:[i32] } (MUBUFOffset:{ *:[iPTR] } v4i32:{ *:[v4i32] }:$srsrc, i32:{ *:[i32] }:$soffset, i32:{ *:[i32] }:$offset), i32:{ *:[i32] }:$vdata_in)<<P:Predicate_atomic_load_or_global_noret_32>>  =>  (BUFFER_ATOMIC_OR_OFFSET anonymous_15037:{ *:[i32] }:$vdata_in, SReg_128:{ *:[v4i32] }:$srsrc, SCSrc_b32:{ *:[i32] }:$soffset, offset:{ *:[i32] }:$offset)
        GIR_BuildMI, /*InsnID*/0, /*Opcode*/GIMT_Encode2(AMDGPU::BUFFER_ATOMIC_OR_OFFSET),
        GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/2, // vdata_in
        GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/0, // srsrc
        GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/1, // soffset
        GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/2, // offset
        GIR_AddImm8, /*InsnID*/0, /*Imm*/0,
        GIR_MergeMemOperands, /*InsnID*/0, /*NumInsns*/1, /*MergeInsnID's*/0,
        GIR_ConstrainSelectedInstOperands, /*InsnID*/0,
        GIR_EraseFromParent, /*InsnID*/0,
        // GIR_Coverage, 4573,
        GIR_Done,
      // Label 2615: @170484
      GIM_Try, /*On fail goto*//*Label 2616*/ GIMT_Encode4(170544), // Rule ID 4577 //
        GIM_CheckMemoryAddressSpace, /*MI*/0, /*MMO*/0, /*NumAddrSpace*/3, /*AddrSpace*/1, /*AddrSpace*/4, /*AddrSpace*/6,
        GIM_CheckHasNoUse, /*MI*/0,
        GIM_CheckPointerToAny, /*MI*/0, /*Op*/1, /*SizeInBits*/0,
        GIM_CheckComplexPattern, /*MI*/0, /*Op*/1, /*Renderer*/GIMT_Encode2(0), GIMT_Encode2(GICP_gi_mubuf_offset),
        // (atomic_load_or:{ *:[i32] } (MUBUFOffset:{ *:[iPTR] } v4i32:{ *:[v4i32] }:$srsrc, i32:{ *:[i32] }:$soffset, i32:{ *:[i32] }:$offset), i32:{ *:[i32] }:$vdata_in)<<P:Predicate_atomic_load_or_global_noret_32>>  =>  (BUFFER_ATOMIC_OR_VBUFFER_OFFSET anonymous_15037:{ *:[i32] }:$vdata_in, SReg_128:{ *:[v4i32] }:$srsrc, SCSrc_b32:{ *:[i32] }:$soffset, offset:{ *:[i32] }:$offset)
        GIR_BuildMI, /*InsnID*/0, /*Opcode*/GIMT_Encode2(AMDGPU::BUFFER_ATOMIC_OR_VBUFFER_OFFSET),
        GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/2, // vdata_in
        GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/0, // srsrc
        GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/1, // soffset
        GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/2, // offset
        GIR_AddImm8, /*InsnID*/0, /*Imm*/0,
        GIR_MergeMemOperands, /*InsnID*/0, /*NumInsns*/1, /*MergeInsnID's*/0,
        GIR_ConstrainSelectedInstOperands, /*InsnID*/0,
        GIR_EraseFromParent, /*InsnID*/0,
        // GIR_Coverage, 4577,
        GIR_Done,
      // Label 2616: @170544
      GIM_Try, /*On fail goto*//*Label 2617*/ GIMT_Encode4(170614), // Rule ID 4571 //
        GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasUnrestrictedSOffset),
        GIM_CheckMemoryAddressSpace, /*MI*/0, /*MMO*/0, /*NumAddrSpace*/3, /*AddrSpace*/1, /*AddrSpace*/4, /*AddrSpace*/6,
        GIM_CheckRegBankForClass, /*MI*/0, /*Op*/0, /*RC*/GIMT_Encode2(AMDGPU::AV_32RegClassID),
        GIM_CheckPointerToAny, /*MI*/0, /*Op*/1, /*SizeInBits*/0,
        GIM_CheckComplexPattern, /*MI*/0, /*Op*/1, /*Renderer*/GIMT_Encode2(0), GIMT_Encode2(GICP_gi_mubuf_offset),
        // (atomic_load_or:{ *:[i32] } (MUBUFOffset:{ *:[iPTR] } v4i32:{ *:[v4i32] }:$srsrc, i32:{ *:[i32] }:$soffset, i32:{ *:[i32] }:$offset), i32:{ *:[i32] }:$vdata_in)<<P:Predicate_atomic_load_or_global_32>>  =>  (BUFFER_ATOMIC_OR_OFFSET_RTN:{ *:[i32] } anonymous_15037:{ *:[i32] }:$vdata_in, SReg_128:{ *:[v4i32] }:$srsrc, SCSrc_b32:{ *:[i32] }:$soffset, offset:{ *:[i32] }:$offset)
        GIR_BuildMI, /*InsnID*/0, /*Opcode*/GIMT_Encode2(AMDGPU::BUFFER_ATOMIC_OR_OFFSET_RTN),
        GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/0, // DstI[vdata]
        GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/2, // vdata_in
        GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/0, // srsrc
        GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/1, // soffset
        GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/2, // offset
        GIR_AddImm8, /*InsnID*/0, /*Imm*/1,
        GIR_MergeMemOperands, /*InsnID*/0, /*NumInsns*/1, /*MergeInsnID's*/0,
        GIR_ConstrainSelectedInstOperands, /*InsnID*/0,
        GIR_EraseFromParent, /*InsnID*/0,
        // GIR_Coverage, 4571,
        GIR_Done,
      // Label 2617: @170614
      GIM_Try, /*On fail goto*//*Label 2618*/ GIMT_Encode4(170681), // Rule ID 4575 //
        GIM_CheckMemoryAddressSpace, /*MI*/0, /*MMO*/0, /*NumAddrSpace*/3, /*AddrSpace*/1, /*AddrSpace*/4, /*AddrSpace*/6,
        GIM_CheckRegBankForClass, /*MI*/0, /*Op*/0, /*RC*/GIMT_Encode2(AMDGPU::AV_32RegClassID),
        GIM_CheckPointerToAny, /*MI*/0, /*Op*/1, /*SizeInBits*/0,
        GIM_CheckComplexPattern, /*MI*/0, /*Op*/1, /*Renderer*/GIMT_Encode2(0), GIMT_Encode2(GICP_gi_mubuf_offset),
        // (atomic_load_or:{ *:[i32] } (MUBUFOffset:{ *:[iPTR] } v4i32:{ *:[v4i32] }:$srsrc, i32:{ *:[i32] }:$soffset, i32:{ *:[i32] }:$offset), i32:{ *:[i32] }:$vdata_in)<<P:Predicate_atomic_load_or_global_32>>  =>  (BUFFER_ATOMIC_OR_VBUFFER_OFFSET_RTN:{ *:[i32] } anonymous_15037:{ *:[i32] }:$vdata_in, SReg_128:{ *:[v4i32] }:$srsrc, SCSrc_b32:{ *:[i32] }:$soffset, offset:{ *:[i32] }:$offset)
        GIR_BuildMI, /*InsnID*/0, /*Opcode*/GIMT_Encode2(AMDGPU::BUFFER_ATOMIC_OR_VBUFFER_OFFSET_RTN),
        GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/0, // DstI[vdata]
        GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/2, // vdata_in
        GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/0, // srsrc
        GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/1, // soffset
        GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/2, // offset
        GIR_AddImm8, /*InsnID*/0, /*Imm*/1,
        GIR_MergeMemOperands, /*InsnID*/0, /*NumInsns*/1, /*MergeInsnID's*/0,
        GIR_ConstrainSelectedInstOperands, /*InsnID*/0,
        GIR_EraseFromParent, /*InsnID*/0,
        // GIR_Coverage, 4575,
        GIR_Done,
      // Label 2618: @170681
      GIM_Try, /*On fail goto*//*Label 2619*/ GIMT_Encode4(170737), // Rule ID 6935 //
        GIM_CheckFeatures, GIMT_Encode2(GIFBS_LDSRequiresM0Init),
        GIM_CheckMemoryAddressSpace, /*MI*/0, /*MMO*/0, /*NumAddrSpace*/1, /*AddrSpace*/3,
        GIM_CheckHasNoUse, /*MI*/0,
        GIM_CheckPointerToAny, /*MI*/0, /*Op*/1, /*SizeInBits*/0,
        GIM_CheckComplexPattern, /*MI*/0, /*Op*/1, /*Renderer*/GIMT_Encode2(0), GIMT_Encode2(GICP_gi_ds_1addr_1offset),
        // (atomic_load_or_glue:{ *:[i32] } (DS1Addr1Offset:{ *:[iPTR] } i32:{ *:[i32] }:$ptr, i32:{ *:[i32] }:$offset), i32:{ *:[i32] }:$value)<<P:Predicate_atomic_load_or_local_m0_noret_32>>  =>  (DS_OR_B32 ?:{ *:[i32] }:$ptr, anonymous_15037:{ *:[i32] }:$value, offset:{ *:[i32] }:$offset, 0:{ *:[i1] })
        GIR_BuildMI, /*InsnID*/0, /*Opcode*/GIMT_Encode2(AMDGPU::DS_OR_B32),
        GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/0, // ptr
        GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/2, // value
        GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/1, // offset
        GIR_AddImm8, /*InsnID*/0, /*Imm*/0,
        GIR_MergeMemOperands, /*InsnID*/0, /*NumInsns*/1, /*MergeInsnID's*/0,
        GIR_ConstrainSelectedInstOperands, /*InsnID*/0,
        GIR_EraseFromParent, /*InsnID*/0,
        // GIR_Coverage, 6935,
        GIR_Done,
      // Label 2619: @170737
      GIM_Try, /*On fail goto*//*Label 2620*/ GIMT_Encode4(170793), // Rule ID 6937 //
        GIM_CheckFeatures, GIMT_Encode2(GIFBS_NotLDSRequiresM0Init),
        GIM_CheckMemoryAddressSpace, /*MI*/0, /*MMO*/0, /*NumAddrSpace*/1, /*AddrSpace*/3,
        GIM_CheckHasNoUse, /*MI*/0,
        GIM_CheckPointerToAny, /*MI*/0, /*Op*/1, /*SizeInBits*/0,
        GIM_CheckComplexPattern, /*MI*/0, /*Op*/1, /*Renderer*/GIMT_Encode2(0), GIMT_Encode2(GICP_gi_ds_1addr_1offset),
        // (atomic_load_or:{ *:[i32] } (DS1Addr1Offset:{ *:[iPTR] } i32:{ *:[i32] }:$ptr, i32:{ *:[i32] }:$offset), i32:{ *:[i32] }:$value)<<P:Predicate_atomic_load_or_local_noret_32>>  =>  (DS_OR_B32_gfx9 ?:{ *:[i32] }:$ptr, anonymous_15037:{ *:[i32] }:$value, offset:{ *:[i32] }:$offset, 0:{ *:[i1] })
        GIR_BuildMI, /*InsnID*/0, /*Opcode*/GIMT_Encode2(AMDGPU::DS_OR_B32_gfx9),
        GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/0, // ptr
        GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/2, // value
        GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/1, // offset
        GIR_AddImm8, /*InsnID*/0, /*Imm*/0,
        GIR_MergeMemOperands, /*InsnID*/0, /*NumInsns*/1, /*MergeInsnID's*/0,
        GIR_ConstrainSelectedInstOperands, /*InsnID*/0,
        GIR_EraseFromParent, /*InsnID*/0,
        // GIR_Coverage, 6937,
        GIR_Done,
      // Label 2620: @170793
      GIM_Try, /*On fail goto*//*Label 2621*/ GIMT_Encode4(170849), // Rule ID 6939 //
        GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasGDS),
        GIM_CheckMemoryAddressSpace, /*MI*/0, /*MMO*/0, /*NumAddrSpace*/1, /*AddrSpace*/2,
        GIM_CheckHasNoUse, /*MI*/0,
        GIM_CheckPointerToAny, /*MI*/0, /*Op*/1, /*SizeInBits*/0,
        GIM_CheckComplexPattern, /*MI*/0, /*Op*/1, /*Renderer*/GIMT_Encode2(0), GIMT_Encode2(GICP_gi_ds_1addr_1offset),
        // (atomic_load_or_glue:{ *:[i32] } (DS1Addr1Offset:{ *:[iPTR] } i32:{ *:[i32] }:$ptr, i32:{ *:[i32] }:$offset), i32:{ *:[i32] }:$value)<<P:Predicate_atomic_load_or_region_m0_noret_32>>  =>  (DS_OR_B32 ?:{ *:[i32] }:$ptr, anonymous_15037:{ *:[i32] }:$value, offset:{ *:[i32] }:$offset, 1:{ *:[i1] })
        GIR_BuildMI, /*InsnID*/0, /*Opcode*/GIMT_Encode2(AMDGPU::DS_OR_B32),
        GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/0, // ptr
        GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/2, // value
        GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/1, // offset
        GIR_AddImm8, /*InsnID*/0, /*Imm*/1,
        GIR_MergeMemOperands, /*InsnID*/0, /*NumInsns*/1, /*MergeInsnID's*/0,
        GIR_ConstrainSelectedInstOperands, /*InsnID*/0,
        GIR_EraseFromParent, /*InsnID*/0,
        // GIR_Coverage, 6939,
        GIR_Done,
      // Label 2621: @170849
      GIM_Try, /*On fail goto*//*Label 2622*/ GIMT_Encode4(170912), // Rule ID 6934 //
        GIM_CheckFeatures, GIMT_Encode2(GIFBS_LDSRequiresM0Init),
        GIM_CheckMemoryAddressSpace, /*MI*/0, /*MMO*/0, /*NumAddrSpace*/1, /*AddrSpace*/3,
        GIM_CheckRegBankForClass, /*MI*/0, /*Op*/0, /*RC*/GIMT_Encode2(AMDGPU::AV_32RegClassID),
        GIM_CheckPointerToAny, /*MI*/0, /*Op*/1, /*SizeInBits*/0,
        GIM_CheckComplexPattern, /*MI*/0, /*Op*/1, /*Renderer*/GIMT_Encode2(0), GIMT_Encode2(GICP_gi_ds_1addr_1offset),
        // (atomic_load_or_glue:{ *:[i32] } (DS1Addr1Offset:{ *:[iPTR] } i32:{ *:[i32] }:$ptr, i32:{ *:[i32] }:$offset), i32:{ *:[i32] }:$value)<<P:Predicate_atomic_load_or_local_m0_32>>  =>  (DS_OR_RTN_B32:{ *:[i32] } ?:{ *:[i32] }:$ptr, anonymous_15037:{ *:[i32] }:$value, offset:{ *:[i32] }:$offset, 0:{ *:[i1] })
        GIR_BuildMI, /*InsnID*/0, /*Opcode*/GIMT_Encode2(AMDGPU::DS_OR_RTN_B32),
        GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/0, // DstI[vdst]
        GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/0, // ptr
        GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/2, // value
        GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/1, // offset
        GIR_AddImm8, /*InsnID*/0, /*Imm*/0,
        GIR_MergeMemOperands, /*InsnID*/0, /*NumInsns*/1, /*MergeInsnID's*/0,
        GIR_ConstrainSelectedInstOperands, /*InsnID*/0,
        GIR_EraseFromParent, /*InsnID*/0,
        // GIR_Coverage, 6934,
        GIR_Done,
      // Label 2622: @170912
      GIM_Try, /*On fail goto*//*Label 2623*/ GIMT_Encode4(170975), // Rule ID 6936 //
        GIM_CheckFeatures, GIMT_Encode2(GIFBS_NotLDSRequiresM0Init),
        GIM_CheckMemoryAddressSpace, /*MI*/0, /*MMO*/0, /*NumAddrSpace*/1, /*AddrSpace*/3,
        GIM_CheckRegBankForClass, /*MI*/0, /*Op*/0, /*RC*/GIMT_Encode2(AMDGPU::AV_32RegClassID),
        GIM_CheckPointerToAny, /*MI*/0, /*Op*/1, /*SizeInBits*/0,
        GIM_CheckComplexPattern, /*MI*/0, /*Op*/1, /*Renderer*/GIMT_Encode2(0), GIMT_Encode2(GICP_gi_ds_1addr_1offset),
        // (atomic_load_or:{ *:[i32] } (DS1Addr1Offset:{ *:[iPTR] } i32:{ *:[i32] }:$ptr, i32:{ *:[i32] }:$offset), i32:{ *:[i32] }:$value)<<P:Predicate_atomic_load_or_local_32>>  =>  (DS_OR_RTN_B32_gfx9:{ *:[i32] } ?:{ *:[i32] }:$ptr, anonymous_15037:{ *:[i32] }:$value, offset:{ *:[i32] }:$offset, 0:{ *:[i1] })
        GIR_BuildMI, /*InsnID*/0, /*Opcode*/GIMT_Encode2(AMDGPU::DS_OR_RTN_B32_gfx9),
        GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/0, // DstI[vdst]
        GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/0, // ptr
        GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/2, // value
        GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/1, // offset
        GIR_AddImm8, /*InsnID*/0, /*Imm*/0,
        GIR_MergeMemOperands, /*InsnID*/0, /*NumInsns*/1, /*MergeInsnID's*/0,
        GIR_ConstrainSelectedInstOperands, /*InsnID*/0,
        GIR_EraseFromParent, /*InsnID*/0,
        // GIR_Coverage, 6936,
        GIR_Done,
      // Label 2623: @170975
      GIM_Try, /*On fail goto*//*Label 2624*/ GIMT_Encode4(171038), // Rule ID 6938 //
        GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasGDS),
        GIM_CheckMemoryAddressSpace, /*MI*/0, /*MMO*/0, /*NumAddrSpace*/1, /*AddrSpace*/2,
        GIM_CheckRegBankForClass, /*MI*/0, /*Op*/0, /*RC*/GIMT_Encode2(AMDGPU::AV_32RegClassID),
        GIM_CheckPointerToAny, /*MI*/0, /*Op*/1, /*SizeInBits*/0,
        GIM_CheckComplexPattern, /*MI*/0, /*Op*/1, /*Renderer*/GIMT_Encode2(0), GIMT_Encode2(GICP_gi_ds_1addr_1offset),
        // (atomic_load_or_glue:{ *:[i32] } (DS1Addr1Offset:{ *:[iPTR] } i32:{ *:[i32] }:$ptr, i32:{ *:[i32] }:$offset), i32:{ *:[i32] }:$value)<<P:Predicate_atomic_load_or_region_m0_32>>  =>  (DS_OR_RTN_B32:{ *:[i32] } ?:{ *:[i32] }:$ptr, anonymous_15037:{ *:[i32] }:$value, offset:{ *:[i32] }:$offset, 1:{ *:[i1] })
        GIR_BuildMI, /*InsnID*/0, /*Opcode*/GIMT_Encode2(AMDGPU::DS_OR_RTN_B32),
        GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/0, // DstI[vdst]
        GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/0, // ptr
        GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/2, // value
        GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/1, // offset
        GIR_AddImm8, /*InsnID*/0, /*Imm*/1,
        GIR_MergeMemOperands, /*InsnID*/0, /*NumInsns*/1, /*MergeInsnID's*/0,
        GIR_ConstrainSelectedInstOperands, /*InsnID*/0,
        GIR_EraseFromParent, /*InsnID*/0,
        // GIR_Coverage, 6938,
        GIR_Done,
      // Label 2624: @171038
      GIM_Try, /*On fail goto*//*Label 2625*/ GIMT_Encode4(171101), // Rule ID 3183 //
        GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasFlatGlobalInsts),
        GIM_CheckMemoryAddressSpace, /*MI*/0, /*MMO*/0, /*NumAddrSpace*/3, /*AddrSpace*/1, /*AddrSpace*/4, /*AddrSpace*/6,
        GIM_CheckHasNoUse, /*MI*/0,
        GIM_CheckPointerToAny, /*MI*/0, /*Op*/1, /*SizeInBits*/0,
        GIM_CheckComplexPattern, /*MI*/0, /*Op*/1, /*Renderer*/GIMT_Encode2(0), GIMT_Encode2(GICP_gi_global_saddr),
        // (atomic_load_or:{ *:[i32] } (GlobalSAddr:{ *:[iPTR] } SReg_64:{ *:[i64] }:$saddr, VGPR_32:{ *:[i32] }:$voffset, i32:{ *:[i32] }:$offset), i32:{ *:[i32] }:$data)<<P:Predicate_atomic_load_or_global_noret_32>>  =>  (GLOBAL_ATOMIC_OR_SADDR ?:{ *:[i32] }:$voffset, anonymous_15037:{ *:[i32] }:$data, ?:{ *:[i64] }:$saddr, ?:{ *:[i32] }:$offset)
        GIR_BuildMI, /*InsnID*/0, /*Opcode*/GIMT_Encode2(AMDGPU::GLOBAL_ATOMIC_OR_SADDR),
        GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/1, // voffset
        GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/2, // data
        GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/0, // saddr
        GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/2, // offset
        GIR_AddImm8, /*InsnID*/0, /*Imm*/0,
        GIR_MergeMemOperands, /*InsnID*/0, /*NumInsns*/1, /*MergeInsnID's*/0,
        GIR_ConstrainSelectedInstOperands, /*InsnID*/0,
        GIR_EraseFromParent, /*InsnID*/0,
        // GIR_Coverage, 3183,
        GIR_Done,
      // Label 2625: @171101
      GIM_Try, /*On fail goto*//*Label 2626*/ GIMT_Encode4(171171), // Rule ID 3185 //
        GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasFlatGlobalInsts),
        GIM_CheckMemoryAddressSpace, /*MI*/0, /*MMO*/0, /*NumAddrSpace*/3, /*AddrSpace*/1, /*AddrSpace*/4, /*AddrSpace*/6,
        GIM_CheckRegBankForClass, /*MI*/0, /*Op*/0, /*RC*/GIMT_Encode2(AMDGPU::AV_32RegClassID),
        GIM_CheckPointerToAny, /*MI*/0, /*Op*/1, /*SizeInBits*/0,
        GIM_CheckComplexPattern, /*MI*/0, /*Op*/1, /*Renderer*/GIMT_Encode2(0), GIMT_Encode2(GICP_gi_global_saddr),
        // (atomic_load_or:{ *:[i32] } (GlobalSAddr:{ *:[iPTR] } SReg_64:{ *:[i64] }:$saddr, VGPR_32:{ *:[i32] }:$voffset, i32:{ *:[i32] }:$offset), i32:{ *:[i32] }:$data)<<P:Predicate_atomic_load_or_global_32>>  =>  (GLOBAL_ATOMIC_OR_SADDR_RTN:{ *:[i32] } ?:{ *:[i32] }:$voffset, anonymous_15037:{ *:[i32] }:$data, ?:{ *:[i64] }:$saddr, ?:{ *:[i32] }:$offset)
        GIR_BuildMI, /*InsnID*/0, /*Opcode*/GIMT_Encode2(AMDGPU::GLOBAL_ATOMIC_OR_SADDR_RTN),
        GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/0, // DstI[vdst]
        GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/1, // voffset
        GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/2, // data
        GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/0, // saddr
        GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/2, // offset
        GIR_AddImm8, /*InsnID*/0, /*Imm*/1,
        GIR_MergeMemOperands, /*InsnID*/0, /*NumInsns*/1, /*MergeInsnID's*/0,
        GIR_ConstrainSelectedInstOperands, /*InsnID*/0,
        GIR_EraseFromParent, /*InsnID*/0,
        // GIR_Coverage, 3185,
        GIR_Done,
      // Label 2626: @171171
      GIM_Try, /*On fail goto*//*Label 2627*/ GIMT_Encode4(171229), // Rule ID 3182 //
        GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasFlatGlobalInsts),
        GIM_CheckMemoryAddressSpace, /*MI*/0, /*MMO*/0, /*NumAddrSpace*/3, /*AddrSpace*/1, /*AddrSpace*/4, /*AddrSpace*/6,
        GIM_CheckHasNoUse, /*MI*/0,
        GIM_CheckPointerToAny, /*MI*/0, /*Op*/1, /*SizeInBits*/0,
        GIM_CheckComplexPattern, /*MI*/0, /*Op*/1, /*Renderer*/GIMT_Encode2(0), GIMT_Encode2(GICP_gi_global_offset),
        // (atomic_load_or:{ *:[i32] } (GlobalOffset:{ *:[iPTR] } i64:{ *:[i64] }:$vaddr, i32:{ *:[i32] }:$offset), i32:{ *:[i32] }:$data)<<P:Predicate_atomic_load_or_global_noret_32>>  =>  (GLOBAL_ATOMIC_OR VReg_64:{ *:[i64] }:$vaddr, anonymous_15037:{ *:[i32] }:$data, ?:{ *:[i32] }:$offset)
        GIR_BuildMI, /*InsnID*/0, /*Opcode*/GIMT_Encode2(AMDGPU::GLOBAL_ATOMIC_OR),
        GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/0, // vaddr
        GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/2, // data
        GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/1, // offset
        GIR_AddImm8, /*InsnID*/0, /*Imm*/0,
        GIR_MergeMemOperands, /*InsnID*/0, /*NumInsns*/1, /*MergeInsnID's*/0,
        GIR_ConstrainSelectedInstOperands, /*InsnID*/0,
        GIR_EraseFromParent, /*InsnID*/0,
        // GIR_Coverage, 3182,
        GIR_Done,
      // Label 2627: @171229
      GIM_Try, /*On fail goto*//*Label 2628*/ GIMT_Encode4(171294), // Rule ID 3184 //
        GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasFlatGlobalInsts),
        GIM_CheckMemoryAddressSpace, /*MI*/0, /*MMO*/0, /*NumAddrSpace*/3, /*AddrSpace*/1, /*AddrSpace*/4, /*AddrSpace*/6,
        GIM_CheckRegBankForClass, /*MI*/0, /*Op*/0, /*RC*/GIMT_Encode2(AMDGPU::AV_32RegClassID),
        GIM_CheckPointerToAny, /*MI*/0, /*Op*/1, /*SizeInBits*/0,
        GIM_CheckComplexPattern, /*MI*/0, /*Op*/1, /*Renderer*/GIMT_Encode2(0), GIMT_Encode2(GICP_gi_global_offset),
        // (atomic_load_or:{ *:[i32] } (GlobalOffset:{ *:[iPTR] } i64:{ *:[i64] }:$vaddr, i32:{ *:[i32] }:$offset), i32:{ *:[i32] }:$data)<<P:Predicate_atomic_load_or_global_32>>  =>  (GLOBAL_ATOMIC_OR_RTN:{ *:[i32] } VReg_64:{ *:[i64] }:$vaddr, anonymous_15037:{ *:[i32] }:$data, ?:{ *:[i32] }:$offset)
        GIR_BuildMI, /*InsnID*/0, /*Opcode*/GIMT_Encode2(AMDGPU::GLOBAL_ATOMIC_OR_RTN),
        GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/0, // DstI[vdst]
        GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/0, // vaddr
        GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/2, // data
        GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/1, // offset
        GIR_AddImm8, /*InsnID*/0, /*Imm*/1,
        GIR_MergeMemOperands, /*InsnID*/0, /*NumInsns*/1, /*MergeInsnID's*/0,
        GIR_ConstrainSelectedInstOperands, /*InsnID*/0,
        GIR_EraseFromParent, /*InsnID*/0,
        // GIR_Coverage, 3184,
        GIR_Done,
      // Label 2628: @171294
      GIM_Try, /*On fail goto*//*Label 2629*/ GIMT_Encode4(171353), // Rule ID 2846 //
        GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasFlatAddressSpace),
        GIM_CheckMemoryAddressSpace, /*MI*/0, /*MMO*/0, /*NumAddrSpace*/4, /*AddrSpace*/0, /*AddrSpace*/1, /*AddrSpace*/4, /*AddrSpace*/6,
        GIM_CheckHasNoUse, /*MI*/0,
        GIM_CheckPointerToAny, /*MI*/0, /*Op*/1, /*SizeInBits*/0,
        GIM_CheckComplexPattern, /*MI*/0, /*Op*/1, /*Renderer*/GIMT_Encode2(0), GIMT_Encode2(GICP_gi_flat_offset),
        // (atomic_load_or:{ *:[i32] } (FlatOffset:{ *:[iPTR] } i64:{ *:[i64] }:$vaddr, i32:{ *:[i32] }:$offset), i32:{ *:[i32] }:$data)<<P:Predicate_atomic_load_or_flat_noret_32>>  =>  (FLAT_ATOMIC_OR VReg_64:{ *:[i64] }:$vaddr, anonymous_15037:{ *:[i32] }:$data, ?:{ *:[i32] }:$offset)
        GIR_BuildMI, /*InsnID*/0, /*Opcode*/GIMT_Encode2(AMDGPU::FLAT_ATOMIC_OR),
        GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/0, // vaddr
        GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/2, // data
        GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/1, // offset
        GIR_AddImm8, /*InsnID*/0, /*Imm*/0,
        GIR_MergeMemOperands, /*InsnID*/0, /*NumInsns*/1, /*MergeInsnID's*/0,
        GIR_ConstrainSelectedInstOperands, /*InsnID*/0,
        GIR_EraseFromParent, /*InsnID*/0,
        // GIR_Coverage, 2846,
        GIR_Done,
      // Label 2629: @171353
      GIM_Try, /*On fail goto*//*Label 2630*/ GIMT_Encode4(171411), // Rule ID 2898 //
        GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasFlatAddressSpace),
        GIM_CheckMemoryAddressSpace, /*MI*/0, /*MMO*/0, /*NumAddrSpace*/3, /*AddrSpace*/1, /*AddrSpace*/4, /*AddrSpace*/6,
        GIM_CheckHasNoUse, /*MI*/0,
        GIM_CheckPointerToAny, /*MI*/0, /*Op*/1, /*SizeInBits*/0,
        GIM_CheckComplexPattern, /*MI*/0, /*Op*/1, /*Renderer*/GIMT_Encode2(0), GIMT_Encode2(GICP_gi_flat_offset),
        // (atomic_load_or:{ *:[i32] } (FlatOffset:{ *:[iPTR] } i64:{ *:[i64] }:$vaddr, i32:{ *:[i32] }:$offset), i32:{ *:[i32] }:$data)<<P:Predicate_atomic_load_or_global_noret_32>>  =>  (FLAT_ATOMIC_OR VReg_64:{ *:[i64] }:$vaddr, anonymous_15037:{ *:[i32] }:$data, ?:{ *:[i32] }:$offset)
        GIR_BuildMI, /*InsnID*/0, /*Opcode*/GIMT_Encode2(AMDGPU::FLAT_ATOMIC_OR),
        GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/0, // vaddr
        GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/2, // data
        GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/1, // offset
        GIR_AddImm8, /*InsnID*/0, /*Imm*/0,
        GIR_MergeMemOperands, /*InsnID*/0, /*NumInsns*/1, /*MergeInsnID's*/0,
        GIR_ConstrainSelectedInstOperands, /*InsnID*/0,
        GIR_EraseFromParent, /*InsnID*/0,
        // GIR_Coverage, 2898,
        GIR_Done,
      // Label 2630: @171411
      GIM_Try, /*On fail goto*//*Label 2631*/ GIMT_Encode4(171477), // Rule ID 2845 //
        GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasFlatAddressSpace),
        GIM_CheckMemoryAddressSpace, /*MI*/0, /*MMO*/0, /*NumAddrSpace*/4, /*AddrSpace*/0, /*AddrSpace*/1, /*AddrSpace*/4, /*AddrSpace*/6,
        GIM_CheckRegBankForClass, /*MI*/0, /*Op*/0, /*RC*/GIMT_Encode2(AMDGPU::AV_32RegClassID),
        GIM_CheckPointerToAny, /*MI*/0, /*Op*/1, /*SizeInBits*/0,
        GIM_CheckComplexPattern, /*MI*/0, /*Op*/1, /*Renderer*/GIMT_Encode2(0), GIMT_Encode2(GICP_gi_flat_offset),
        // (atomic_load_or:{ *:[i32] } (FlatOffset:{ *:[iPTR] } i64:{ *:[i64] }:$vaddr, i32:{ *:[i32] }:$offset), i32:{ *:[i32] }:$data)<<P:Predicate_atomic_load_or_flat_32>>  =>  (FLAT_ATOMIC_OR_RTN:{ *:[i32] } VReg_64:{ *:[i64] }:$vaddr, anonymous_15037:{ *:[i32] }:$data, ?:{ *:[i32] }:$offset)
        GIR_BuildMI, /*InsnID*/0, /*Opcode*/GIMT_Encode2(AMDGPU::FLAT_ATOMIC_OR_RTN),
        GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/0, // DstI[vdst]
        GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/0, // vaddr
        GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/2, // data
        GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/1, // offset
        GIR_AddImm8, /*InsnID*/0, /*Imm*/1,
        GIR_MergeMemOperands, /*InsnID*/0, /*NumInsns*/1, /*MergeInsnID's*/0,
        GIR_ConstrainSelectedInstOperands, /*InsnID*/0,
        GIR_EraseFromParent, /*InsnID*/0,
        // GIR_Coverage, 2845,
        GIR_Done,
      // Label 2631: @171477
      GIM_Try, /*On fail goto*//*Label 2632*/ GIMT_Encode4(171542), // Rule ID 2897 //
        GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasFlatAddressSpace),
        GIM_CheckMemoryAddressSpace, /*MI*/0, /*MMO*/0, /*NumAddrSpace*/3, /*AddrSpace*/1, /*AddrSpace*/4, /*AddrSpace*/6,
        GIM_CheckRegBankForClass, /*MI*/0, /*Op*/0, /*RC*/GIMT_Encode2(AMDGPU::AV_32RegClassID),
        GIM_CheckPointerToAny, /*MI*/0, /*Op*/1, /*SizeInBits*/0,
        GIM_CheckComplexPattern, /*MI*/0, /*Op*/1, /*Renderer*/GIMT_Encode2(0), GIMT_Encode2(GICP_gi_flat_offset),
        // (atomic_load_or:{ *:[i32] } (FlatOffset:{ *:[iPTR] } i64:{ *:[i64] }:$vaddr, i32:{ *:[i32] }:$offset), i32:{ *:[i32] }:$data)<<P:Predicate_atomic_load_or_global_32>>  =>  (FLAT_ATOMIC_OR_RTN:{ *:[i32] } VReg_64:{ *:[i64] }:$vaddr, anonymous_15037:{ *:[i32] }:$data, ?:{ *:[i32] }:$offset)
        GIR_BuildMI, /*InsnID*/0, /*Opcode*/GIMT_Encode2(AMDGPU::FLAT_ATOMIC_OR_RTN),
        GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/0, // DstI[vdst]
        GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/0, // vaddr
        GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/2, // data
        GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/1, // offset
        GIR_AddImm8, /*InsnID*/0, /*Imm*/1,
        GIR_MergeMemOperands, /*InsnID*/0, /*NumInsns*/1, /*MergeInsnID's*/0,
        GIR_ConstrainSelectedInstOperands, /*InsnID*/0,
        GIR_EraseFromParent, /*InsnID*/0,
        // GIR_Coverage, 2897,
        GIR_Done,
      // Label 2632: @171542
      GIM_Reject,
    // Label 2610: @171543
    GIM_Reject,
    // Label 2608: @171544
    GIM_Try, /*On fail goto*//*Label 2633*/ GIMT_Encode4(172955),
      GIM_CheckType, /*MI*/0, /*Op*/2, /*Type*/GILLT_s64,
      GIM_Try, /*On fail goto*//*Label 2634*/ GIMT_Encode4(171621), // Rule ID 4670 //
        GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasUnrestrictedSOffset),
        GIM_CheckMemoryAddressSpace, /*MI*/0, /*MMO*/0, /*NumAddrSpace*/3, /*AddrSpace*/1, /*AddrSpace*/4, /*AddrSpace*/6,
        GIM_CheckHasNoUse, /*MI*/0,
        GIM_CheckPointerToAny, /*MI*/0, /*Op*/1, /*SizeInBits*/0,
        GIM_CheckComplexPattern, /*MI*/0, /*Op*/1, /*Renderer*/GIMT_Encode2(0), GIMT_Encode2(GICP_gi_mubuf_addr64),
        // (atomic_load_or:{ *:[i64] } (MUBUFAddr64:{ *:[iPTR] } v4i32:{ *:[v4i32] }:$srsrc, i64:{ *:[i64] }:$vaddr, i32:{ *:[i32] }:$soffset, i32:{ *:[i32] }:$offset), i64:{ *:[i64] }:$vdata_in)<<P:Predicate_atomic_load_or_global_noret_64>>  =>  (BUFFER_ATOMIC_OR_X2_ADDR64 anonymous_15036:{ *:[i64] }:$vdata_in, VReg_64:{ *:[i64] }:$vaddr, SReg_128:{ *:[v4i32] }:$srsrc, SCSrc_b32:{ *:[i32] }:$soffset, offset:{ *:[i32] }:$offset)
        GIR_BuildMI, /*InsnID*/0, /*Opcode*/GIMT_Encode2(AMDGPU::BUFFER_ATOMIC_OR_X2_ADDR64),
        GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/2, // vdata_in
        GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/1, // vaddr
        GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/0, // srsrc
        GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/2, // soffset
        GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/3, // offset
        GIR_AddImm8, /*InsnID*/0, /*Imm*/0,
        GIR_MergeMemOperands, /*InsnID*/0, /*NumInsns*/1, /*MergeInsnID's*/0,
        GIR_ConstrainSelectedInstOperands, /*InsnID*/0,
        GIR_EraseFromParent, /*InsnID*/0,
        // GIR_Coverage, 4670,
        GIR_Done,
      // Label 2634: @171621
      GIM_Try, /*On fail goto*//*Label 2635*/ GIMT_Encode4(171686), // Rule ID 4674 //
        GIM_CheckMemoryAddressSpace, /*MI*/0, /*MMO*/0, /*NumAddrSpace*/3, /*AddrSpace*/1, /*AddrSpace*/4, /*AddrSpace*/6,
        GIM_CheckHasNoUse, /*MI*/0,
        GIM_CheckPointerToAny, /*MI*/0, /*Op*/1, /*SizeInBits*/0,
        GIM_CheckComplexPattern, /*MI*/0, /*Op*/1, /*Renderer*/GIMT_Encode2(0), GIMT_Encode2(GICP_gi_mubuf_addr64),
        // (atomic_load_or:{ *:[i64] } (MUBUFAddr64:{ *:[iPTR] } v4i32:{ *:[v4i32] }:$srsrc, i64:{ *:[i64] }:$vaddr, i32:{ *:[i32] }:$soffset, i32:{ *:[i32] }:$offset), i64:{ *:[i64] }:$vdata_in)<<P:Predicate_atomic_load_or_global_noret_64>>  =>  (BUFFER_ATOMIC_OR_X2_VBUFFER_ADDR64 anonymous_15036:{ *:[i64] }:$vdata_in, VReg_64:{ *:[i64] }:$vaddr, SReg_128:{ *:[v4i32] }:$srsrc, SCSrc_b32:{ *:[i32] }:$soffset, offset:{ *:[i32] }:$offset)
        GIR_BuildMI, /*InsnID*/0, /*Opcode*/GIMT_Encode2(AMDGPU::BUFFER_ATOMIC_OR_X2_VBUFFER_ADDR64),
        GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/2, // vdata_in
        GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/1, // vaddr
        GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/0, // srsrc
        GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/2, // soffset
        GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/3, // offset
        GIR_AddImm8, /*InsnID*/0, /*Imm*/0,
        GIR_MergeMemOperands, /*InsnID*/0, /*NumInsns*/1, /*MergeInsnID's*/0,
        GIR_ConstrainSelectedInstOperands, /*InsnID*/0,
        GIR_EraseFromParent, /*InsnID*/0,
        // GIR_Coverage, 4674,
        GIR_Done,
      // Label 2635: @171686
      GIM_Try, /*On fail goto*//*Label 2636*/ GIMT_Encode4(171761), // Rule ID 4668 //
        GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasUnrestrictedSOffset),
        GIM_CheckMemoryAddressSpace, /*MI*/0, /*MMO*/0, /*NumAddrSpace*/3, /*AddrSpace*/1, /*AddrSpace*/4, /*AddrSpace*/6,
        GIM_CheckRegBankForClass, /*MI*/0, /*Op*/0, /*RC*/GIMT_Encode2(AMDGPU::AV_64RegClassID),
        GIM_CheckPointerToAny, /*MI*/0, /*Op*/1, /*SizeInBits*/0,
        GIM_CheckComplexPattern, /*MI*/0, /*Op*/1, /*Renderer*/GIMT_Encode2(0), GIMT_Encode2(GICP_gi_mubuf_addr64),
        // (atomic_load_or:{ *:[i64] } (MUBUFAddr64:{ *:[iPTR] } v4i32:{ *:[v4i32] }:$srsrc, i64:{ *:[i64] }:$vaddr, i32:{ *:[i32] }:$soffset, i32:{ *:[i32] }:$offset), i64:{ *:[i64] }:$vdata_in)<<P:Predicate_atomic_load_or_global_64>>  =>  (BUFFER_ATOMIC_OR_X2_ADDR64_RTN:{ *:[i64] } anonymous_15036:{ *:[i64] }:$vdata_in, VReg_64:{ *:[i64] }:$vaddr, SReg_128:{ *:[v4i32] }:$srsrc, SCSrc_b32:{ *:[i32] }:$soffset, offset:{ *:[i32] }:$offset)
        GIR_BuildMI, /*InsnID*/0, /*Opcode*/GIMT_Encode2(AMDGPU::BUFFER_ATOMIC_OR_X2_ADDR64_RTN),
        GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/0, // DstI[vdata]
        GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/2, // vdata_in
        GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/1, // vaddr
        GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/0, // srsrc
        GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/2, // soffset
        GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/3, // offset
        GIR_AddImm8, /*InsnID*/0, /*Imm*/1,
        GIR_MergeMemOperands, /*InsnID*/0, /*NumInsns*/1, /*MergeInsnID's*/0,
        GIR_ConstrainSelectedInstOperands, /*InsnID*/0,
        GIR_EraseFromParent, /*InsnID*/0,
        // GIR_Coverage, 4668,
        GIR_Done,
      // Label 2636: @171761
      GIM_Try, /*On fail goto*//*Label 2637*/ GIMT_Encode4(171833), // Rule ID 4672 //
        GIM_CheckMemoryAddressSpace, /*MI*/0, /*MMO*/0, /*NumAddrSpace*/3, /*AddrSpace*/1, /*AddrSpace*/4, /*AddrSpace*/6,
        GIM_CheckRegBankForClass, /*MI*/0, /*Op*/0, /*RC*/GIMT_Encode2(AMDGPU::AV_64RegClassID),
        GIM_CheckPointerToAny, /*MI*/0, /*Op*/1, /*SizeInBits*/0,
        GIM_CheckComplexPattern, /*MI*/0, /*Op*/1, /*Renderer*/GIMT_Encode2(0), GIMT_Encode2(GICP_gi_mubuf_addr64),
        // (atomic_load_or:{ *:[i64] } (MUBUFAddr64:{ *:[iPTR] } v4i32:{ *:[v4i32] }:$srsrc, i64:{ *:[i64] }:$vaddr, i32:{ *:[i32] }:$soffset, i32:{ *:[i32] }:$offset), i64:{ *:[i64] }:$vdata_in)<<P:Predicate_atomic_load_or_global_64>>  =>  (BUFFER_ATOMIC_OR_X2_VBUFFER_ADDR64_RTN:{ *:[i64] } anonymous_15036:{ *:[i64] }:$vdata_in, VReg_64:{ *:[i64] }:$vaddr, SReg_128:{ *:[v4i32] }:$srsrc, SCSrc_b32:{ *:[i32] }:$soffset, offset:{ *:[i32] }:$offset)
        GIR_BuildMI, /*InsnID*/0, /*Opcode*/GIMT_Encode2(AMDGPU::BUFFER_ATOMIC_OR_X2_VBUFFER_ADDR64_RTN),
        GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/0, // DstI[vdata]
        GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/2, // vdata_in
        GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/1, // vaddr
        GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/0, // srsrc
        GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/2, // soffset
        GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/3, // offset
        GIR_AddImm8, /*InsnID*/0, /*Imm*/1,
        GIR_MergeMemOperands, /*InsnID*/0, /*NumInsns*/1, /*MergeInsnID's*/0,
        GIR_ConstrainSelectedInstOperands, /*InsnID*/0,
        GIR_EraseFromParent, /*InsnID*/0,
        // GIR_Coverage, 4672,
        GIR_Done,
      // Label 2637: @171833
      GIM_Try, /*On fail goto*//*Label 2638*/ GIMT_Encode4(171896), // Rule ID 4669 //
        GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasUnrestrictedSOffset),
        GIM_CheckMemoryAddressSpace, /*MI*/0, /*MMO*/0, /*NumAddrSpace*/3, /*AddrSpace*/1, /*AddrSpace*/4, /*AddrSpace*/6,
        GIM_CheckHasNoUse, /*MI*/0,
        GIM_CheckPointerToAny, /*MI*/0, /*Op*/1, /*SizeInBits*/0,
        GIM_CheckComplexPattern, /*MI*/0, /*Op*/1, /*Renderer*/GIMT_Encode2(0), GIMT_Encode2(GICP_gi_mubuf_offset),
        // (atomic_load_or:{ *:[i64] } (MUBUFOffset:{ *:[iPTR] } v4i32:{ *:[v4i32] }:$srsrc, i32:{ *:[i32] }:$soffset, i32:{ *:[i32] }:$offset), i64:{ *:[i64] }:$vdata_in)<<P:Predicate_atomic_load_or_global_noret_64>>  =>  (BUFFER_ATOMIC_OR_X2_OFFSET anonymous_15036:{ *:[i64] }:$vdata_in, SReg_128:{ *:[v4i32] }:$srsrc, SCSrc_b32:{ *:[i32] }:$soffset, offset:{ *:[i32] }:$offset)
        GIR_BuildMI, /*InsnID*/0, /*Opcode*/GIMT_Encode2(AMDGPU::BUFFER_ATOMIC_OR_X2_OFFSET),
        GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/2, // vdata_in
        GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/0, // srsrc
        GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/1, // soffset
        GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/2, // offset
        GIR_AddImm8, /*InsnID*/0, /*Imm*/0,
        GIR_MergeMemOperands, /*InsnID*/0, /*NumInsns*/1, /*MergeInsnID's*/0,
        GIR_ConstrainSelectedInstOperands, /*InsnID*/0,
        GIR_EraseFromParent, /*InsnID*/0,
        // GIR_Coverage, 4669,
        GIR_Done,
      // Label 2638: @171896
      GIM_Try, /*On fail goto*//*Label 2639*/ GIMT_Encode4(171956), // Rule ID 4673 //
        GIM_CheckMemoryAddressSpace, /*MI*/0, /*MMO*/0, /*NumAddrSpace*/3, /*AddrSpace*/1, /*AddrSpace*/4, /*AddrSpace*/6,
        GIM_CheckHasNoUse, /*MI*/0,
        GIM_CheckPointerToAny, /*MI*/0, /*Op*/1, /*SizeInBits*/0,
        GIM_CheckComplexPattern, /*MI*/0, /*Op*/1, /*Renderer*/GIMT_Encode2(0), GIMT_Encode2(GICP_gi_mubuf_offset),
        // (atomic_load_or:{ *:[i64] } (MUBUFOffset:{ *:[iPTR] } v4i32:{ *:[v4i32] }:$srsrc, i32:{ *:[i32] }:$soffset, i32:{ *:[i32] }:$offset), i64:{ *:[i64] }:$vdata_in)<<P:Predicate_atomic_load_or_global_noret_64>>  =>  (BUFFER_ATOMIC_OR_X2_VBUFFER_OFFSET anonymous_15036:{ *:[i64] }:$vdata_in, SReg_128:{ *:[v4i32] }:$srsrc, SCSrc_b32:{ *:[i32] }:$soffset, offset:{ *:[i32] }:$offset)
        GIR_BuildMI, /*InsnID*/0, /*Opcode*/GIMT_Encode2(AMDGPU::BUFFER_ATOMIC_OR_X2_VBUFFER_OFFSET),
        GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/2, // vdata_in
        GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/0, // srsrc
        GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/1, // soffset
        GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/2, // offset
        GIR_AddImm8, /*InsnID*/0, /*Imm*/0,
        GIR_MergeMemOperands, /*InsnID*/0, /*NumInsns*/1, /*MergeInsnID's*/0,
        GIR_ConstrainSelectedInstOperands, /*InsnID*/0,
        GIR_EraseFromParent, /*InsnID*/0,
        // GIR_Coverage, 4673,
        GIR_Done,
      // Label 2639: @171956
      GIM_Try, /*On fail goto*//*Label 2640*/ GIMT_Encode4(172026), // Rule ID 4667 //
        GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasUnrestrictedSOffset),
        GIM_CheckMemoryAddressSpace, /*MI*/0, /*MMO*/0, /*NumAddrSpace*/3, /*AddrSpace*/1, /*AddrSpace*/4, /*AddrSpace*/6,
        GIM_CheckRegBankForClass, /*MI*/0, /*Op*/0, /*RC*/GIMT_Encode2(AMDGPU::AV_64RegClassID),
        GIM_CheckPointerToAny, /*MI*/0, /*Op*/1, /*SizeInBits*/0,
        GIM_CheckComplexPattern, /*MI*/0, /*Op*/1, /*Renderer*/GIMT_Encode2(0), GIMT_Encode2(GICP_gi_mubuf_offset),
        // (atomic_load_or:{ *:[i64] } (MUBUFOffset:{ *:[iPTR] } v4i32:{ *:[v4i32] }:$srsrc, i32:{ *:[i32] }:$soffset, i32:{ *:[i32] }:$offset), i64:{ *:[i64] }:$vdata_in)<<P:Predicate_atomic_load_or_global_64>>  =>  (BUFFER_ATOMIC_OR_X2_OFFSET_RTN:{ *:[i64] } anonymous_15036:{ *:[i64] }:$vdata_in, SReg_128:{ *:[v4i32] }:$srsrc, SCSrc_b32:{ *:[i32] }:$soffset, offset:{ *:[i32] }:$offset)
        GIR_BuildMI, /*InsnID*/0, /*Opcode*/GIMT_Encode2(AMDGPU::BUFFER_ATOMIC_OR_X2_OFFSET_RTN),
        GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/0, // DstI[vdata]
        GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/2, // vdata_in
        GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/0, // srsrc
        GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/1, // soffset
        GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/2, // offset
        GIR_AddImm8, /*InsnID*/0, /*Imm*/1,
        GIR_MergeMemOperands, /*InsnID*/0, /*NumInsns*/1, /*MergeInsnID's*/0,
        GIR_ConstrainSelectedInstOperands, /*InsnID*/0,
        GIR_EraseFromParent, /*InsnID*/0,
        // GIR_Coverage, 4667,
        GIR_Done,
      // Label 2640: @172026
      GIM_Try, /*On fail goto*//*Label 2641*/ GIMT_Encode4(172093), // Rule ID 4671 //
        GIM_CheckMemoryAddressSpace, /*MI*/0, /*MMO*/0, /*NumAddrSpace*/3, /*AddrSpace*/1, /*AddrSpace*/4, /*AddrSpace*/6,
        GIM_CheckRegBankForClass, /*MI*/0, /*Op*/0, /*RC*/GIMT_Encode2(AMDGPU::AV_64RegClassID),
        GIM_CheckPointerToAny, /*MI*/0, /*Op*/1, /*SizeInBits*/0,
        GIM_CheckComplexPattern, /*MI*/0, /*Op*/1, /*Renderer*/GIMT_Encode2(0), GIMT_Encode2(GICP_gi_mubuf_offset),
        // (atomic_load_or:{ *:[i64] } (MUBUFOffset:{ *:[iPTR] } v4i32:{ *:[v4i32] }:$srsrc, i32:{ *:[i32] }:$soffset, i32:{ *:[i32] }:$offset), i64:{ *:[i64] }:$vdata_in)<<P:Predicate_atomic_load_or_global_64>>  =>  (BUFFER_ATOMIC_OR_X2_VBUFFER_OFFSET_RTN:{ *:[i64] } anonymous_15036:{ *:[i64] }:$vdata_in, SReg_128:{ *:[v4i32] }:$srsrc, SCSrc_b32:{ *:[i32] }:$soffset, offset:{ *:[i32] }:$offset)
        GIR_BuildMI, /*InsnID*/0, /*Opcode*/GIMT_Encode2(AMDGPU::BUFFER_ATOMIC_OR_X2_VBUFFER_OFFSET_RTN),
        GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/0, // DstI[vdata]
        GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/2, // vdata_in
        GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/0, // srsrc
        GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/1, // soffset
        GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/2, // offset
        GIR_AddImm8, /*InsnID*/0, /*Imm*/1,
        GIR_MergeMemOperands, /*InsnID*/0, /*NumInsns*/1, /*MergeInsnID's*/0,
        GIR_ConstrainSelectedInstOperands, /*InsnID*/0,
        GIR_EraseFromParent, /*InsnID*/0,
        // GIR_Coverage, 4671,
        GIR_Done,
      // Label 2641: @172093
      GIM_Try, /*On fail goto*//*Label 2642*/ GIMT_Encode4(172149), // Rule ID 7022 //
        GIM_CheckFeatures, GIMT_Encode2(GIFBS_LDSRequiresM0Init),
        GIM_CheckMemoryAddressSpace, /*MI*/0, /*MMO*/0, /*NumAddrSpace*/1, /*AddrSpace*/3,
        GIM_CheckHasNoUse, /*MI*/0,
        GIM_CheckPointerToAny, /*MI*/0, /*Op*/1, /*SizeInBits*/0,
        GIM_CheckComplexPattern, /*MI*/0, /*Op*/1, /*Renderer*/GIMT_Encode2(0), GIMT_Encode2(GICP_gi_ds_1addr_1offset),
        // (atomic_load_or_glue:{ *:[i64] } (DS1Addr1Offset:{ *:[iPTR] } i32:{ *:[i32] }:$ptr, i32:{ *:[i32] }:$offset), i64:{ *:[i64] }:$value)<<P:Predicate_atomic_load_or_local_m0_noret_64>>  =>  (DS_OR_B64 ?:{ *:[i32] }:$ptr, anonymous_15036:{ *:[i64] }:$value, offset:{ *:[i32] }:$offset, 0:{ *:[i1] })
        GIR_BuildMI, /*InsnID*/0, /*Opcode*/GIMT_Encode2(AMDGPU::DS_OR_B64),
        GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/0, // ptr
        GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/2, // value
        GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/1, // offset
        GIR_AddImm8, /*InsnID*/0, /*Imm*/0,
        GIR_MergeMemOperands, /*InsnID*/0, /*NumInsns*/1, /*MergeInsnID's*/0,
        GIR_ConstrainSelectedInstOperands, /*InsnID*/0,
        GIR_EraseFromParent, /*InsnID*/0,
        // GIR_Coverage, 7022,
        GIR_Done,
      // Label 2642: @172149
      GIM_Try, /*On fail goto*//*Label 2643*/ GIMT_Encode4(172205), // Rule ID 7024 //
        GIM_CheckFeatures, GIMT_Encode2(GIFBS_NotLDSRequiresM0Init),
        GIM_CheckMemoryAddressSpace, /*MI*/0, /*MMO*/0, /*NumAddrSpace*/1, /*AddrSpace*/3,
        GIM_CheckHasNoUse, /*MI*/0,
        GIM_CheckPointerToAny, /*MI*/0, /*Op*/1, /*SizeInBits*/0,
        GIM_CheckComplexPattern, /*MI*/0, /*Op*/1, /*Renderer*/GIMT_Encode2(0), GIMT_Encode2(GICP_gi_ds_1addr_1offset),
        // (atomic_load_or:{ *:[i64] } (DS1Addr1Offset:{ *:[iPTR] } i32:{ *:[i32] }:$ptr, i32:{ *:[i32] }:$offset), i64:{ *:[i64] }:$value)<<P:Predicate_atomic_load_or_local_noret_64>>  =>  (DS_OR_B64_gfx9 ?:{ *:[i32] }:$ptr, anonymous_15036:{ *:[i64] }:$value, offset:{ *:[i32] }:$offset, 0:{ *:[i1] })
        GIR_BuildMI, /*InsnID*/0, /*Opcode*/GIMT_Encode2(AMDGPU::DS_OR_B64_gfx9),
        GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/0, // ptr
        GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/2, // value
        GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/1, // offset
        GIR_AddImm8, /*InsnID*/0, /*Imm*/0,
        GIR_MergeMemOperands, /*InsnID*/0, /*NumInsns*/1, /*MergeInsnID's*/0,
        GIR_ConstrainSelectedInstOperands, /*InsnID*/0,
        GIR_EraseFromParent, /*InsnID*/0,
        // GIR_Coverage, 7024,
        GIR_Done,
      // Label 2643: @172205
      GIM_Try, /*On fail goto*//*Label 2644*/ GIMT_Encode4(172261), // Rule ID 7026 //
        GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasGDS),
        GIM_CheckMemoryAddressSpace, /*MI*/0, /*MMO*/0, /*NumAddrSpace*/1, /*AddrSpace*/2,
        GIM_CheckHasNoUse, /*MI*/0,
        GIM_CheckPointerToAny, /*MI*/0, /*Op*/1, /*SizeInBits*/0,
        GIM_CheckComplexPattern, /*MI*/0, /*Op*/1, /*Renderer*/GIMT_Encode2(0), GIMT_Encode2(GICP_gi_ds_1addr_1offset),
        // (atomic_load_or_glue:{ *:[i64] } (DS1Addr1Offset:{ *:[iPTR] } i32:{ *:[i32] }:$ptr, i32:{ *:[i32] }:$offset), i64:{ *:[i64] }:$value)<<P:Predicate_atomic_load_or_region_m0_noret_64>>  =>  (DS_OR_B64 ?:{ *:[i32] }:$ptr, anonymous_15036:{ *:[i64] }:$value, offset:{ *:[i32] }:$offset, 1:{ *:[i1] })
        GIR_BuildMI, /*InsnID*/0, /*Opcode*/GIMT_Encode2(AMDGPU::DS_OR_B64),
        GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/0, // ptr
        GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/2, // value
        GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/1, // offset
        GIR_AddImm8, /*InsnID*/0, /*Imm*/1,
        GIR_MergeMemOperands, /*InsnID*/0, /*NumInsns*/1, /*MergeInsnID's*/0,
        GIR_ConstrainSelectedInstOperands, /*InsnID*/0,
        GIR_EraseFromParent, /*InsnID*/0,
        // GIR_Coverage, 7026,
        GIR_Done,
      // Label 2644: @172261
      GIM_Try, /*On fail goto*//*Label 2645*/ GIMT_Encode4(172324), // Rule ID 7021 //
        GIM_CheckFeatures, GIMT_Encode2(GIFBS_LDSRequiresM0Init),
        GIM_CheckMemoryAddressSpace, /*MI*/0, /*MMO*/0, /*NumAddrSpace*/1, /*AddrSpace*/3,
        GIM_CheckRegBankForClass, /*MI*/0, /*Op*/0, /*RC*/GIMT_Encode2(AMDGPU::AV_64RegClassID),
        GIM_CheckPointerToAny, /*MI*/0, /*Op*/1, /*SizeInBits*/0,
        GIM_CheckComplexPattern, /*MI*/0, /*Op*/1, /*Renderer*/GIMT_Encode2(0), GIMT_Encode2(GICP_gi_ds_1addr_1offset),
        // (atomic_load_or_glue:{ *:[i64] } (DS1Addr1Offset:{ *:[iPTR] } i32:{ *:[i32] }:$ptr, i32:{ *:[i32] }:$offset), i64:{ *:[i64] }:$value)<<P:Predicate_atomic_load_or_local_m0_64>>  =>  (DS_OR_RTN_B64:{ *:[i64] } ?:{ *:[i32] }:$ptr, anonymous_15036:{ *:[i64] }:$value, offset:{ *:[i32] }:$offset, 0:{ *:[i1] })
        GIR_BuildMI, /*InsnID*/0, /*Opcode*/GIMT_Encode2(AMDGPU::DS_OR_RTN_B64),
        GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/0, // DstI[vdst]
        GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/0, // ptr
        GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/2, // value
        GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/1, // offset
        GIR_AddImm8, /*InsnID*/0, /*Imm*/0,
        GIR_MergeMemOperands, /*InsnID*/0, /*NumInsns*/1, /*MergeInsnID's*/0,
        GIR_ConstrainSelectedInstOperands, /*InsnID*/0,
        GIR_EraseFromParent, /*InsnID*/0,
        // GIR_Coverage, 7021,
        GIR_Done,
      // Label 2645: @172324
      GIM_Try, /*On fail goto*//*Label 2646*/ GIMT_Encode4(172387), // Rule ID 7023 //
        GIM_CheckFeatures, GIMT_Encode2(GIFBS_NotLDSRequiresM0Init),
        GIM_CheckMemoryAddressSpace, /*MI*/0, /*MMO*/0, /*NumAddrSpace*/1, /*AddrSpace*/3,
        GIM_CheckRegBankForClass, /*MI*/0, /*Op*/0, /*RC*/GIMT_Encode2(AMDGPU::AV_64RegClassID),
        GIM_CheckPointerToAny, /*MI*/0, /*Op*/1, /*SizeInBits*/0,
        GIM_CheckComplexPattern, /*MI*/0, /*Op*/1, /*Renderer*/GIMT_Encode2(0), GIMT_Encode2(GICP_gi_ds_1addr_1offset),
        // (atomic_load_or:{ *:[i64] } (DS1Addr1Offset:{ *:[iPTR] } i32:{ *:[i32] }:$ptr, i32:{ *:[i32] }:$offset), i64:{ *:[i64] }:$value)<<P:Predicate_atomic_load_or_local_64>>  =>  (DS_OR_RTN_B64_gfx9:{ *:[i64] } ?:{ *:[i32] }:$ptr, anonymous_15036:{ *:[i64] }:$value, offset:{ *:[i32] }:$offset, 0:{ *:[i1] })
        GIR_BuildMI, /*InsnID*/0, /*Opcode*/GIMT_Encode2(AMDGPU::DS_OR_RTN_B64_gfx9),
        GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/0, // DstI[vdst]
        GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/0, // ptr
        GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/2, // value
        GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/1, // offset
        GIR_AddImm8, /*InsnID*/0, /*Imm*/0,
        GIR_MergeMemOperands, /*InsnID*/0, /*NumInsns*/1, /*MergeInsnID's*/0,
        GIR_ConstrainSelectedInstOperands, /*InsnID*/0,
        GIR_EraseFromParent, /*InsnID*/0,
        // GIR_Coverage, 7023,
        GIR_Done,
      // Label 2646: @172387
      GIM_Try, /*On fail goto*//*Label 2647*/ GIMT_Encode4(172450), // Rule ID 7025 //
        GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasGDS),
        GIM_CheckMemoryAddressSpace, /*MI*/0, /*MMO*/0, /*NumAddrSpace*/1, /*AddrSpace*/2,
        GIM_CheckRegBankForClass, /*MI*/0, /*Op*/0, /*RC*/GIMT_Encode2(AMDGPU::AV_64RegClassID),
        GIM_CheckPointerToAny, /*MI*/0, /*Op*/1, /*SizeInBits*/0,
        GIM_CheckComplexPattern, /*MI*/0, /*Op*/1, /*Renderer*/GIMT_Encode2(0), GIMT_Encode2(GICP_gi_ds_1addr_1offset),
        // (atomic_load_or_glue:{ *:[i64] } (DS1Addr1Offset:{ *:[iPTR] } i32:{ *:[i32] }:$ptr, i32:{ *:[i32] }:$offset), i64:{ *:[i64] }:$value)<<P:Predicate_atomic_load_or_region_m0_64>>  =>  (DS_OR_RTN_B64:{ *:[i64] } ?:{ *:[i32] }:$ptr, anonymous_15036:{ *:[i64] }:$value, offset:{ *:[i32] }:$offset, 1:{ *:[i1] })
        GIR_BuildMI, /*InsnID*/0, /*Opcode*/GIMT_Encode2(AMDGPU::DS_OR_RTN_B64),
        GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/0, // DstI[vdst]
        GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/0, // ptr
        GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/2, // value
        GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/1, // offset
        GIR_AddImm8, /*InsnID*/0, /*Imm*/1,
        GIR_MergeMemOperands, /*InsnID*/0, /*NumInsns*/1, /*MergeInsnID's*/0,
        GIR_ConstrainSelectedInstOperands, /*InsnID*/0,
        GIR_EraseFromParent, /*InsnID*/0,
        // GIR_Coverage, 7025,
        GIR_Done,
      // Label 2647: @172450
      GIM_Try, /*On fail goto*//*Label 2648*/ GIMT_Encode4(172513), // Rule ID 3239 //
        GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasFlatGlobalInsts),
        GIM_CheckMemoryAddressSpace, /*MI*/0, /*MMO*/0, /*NumAddrSpace*/3, /*AddrSpace*/1, /*AddrSpace*/4, /*AddrSpace*/6,
        GIM_CheckHasNoUse, /*MI*/0,
        GIM_CheckPointerToAny, /*MI*/0, /*Op*/1, /*SizeInBits*/0,
        GIM_CheckComplexPattern, /*MI*/0, /*Op*/1, /*Renderer*/GIMT_Encode2(0), GIMT_Encode2(GICP_gi_global_saddr),
        // (atomic_load_or:{ *:[i64] } (GlobalSAddr:{ *:[iPTR] } SReg_64:{ *:[i64] }:$saddr, VGPR_32:{ *:[i32] }:$voffset, i32:{ *:[i32] }:$offset), i64:{ *:[i64] }:$data)<<P:Predicate_atomic_load_or_global_noret_64>>  =>  (GLOBAL_ATOMIC_OR_X2_SADDR ?:{ *:[i32] }:$voffset, anonymous_15036:{ *:[i64] }:$data, ?:{ *:[i64] }:$saddr, ?:{ *:[i32] }:$offset)
        GIR_BuildMI, /*InsnID*/0, /*Opcode*/GIMT_Encode2(AMDGPU::GLOBAL_ATOMIC_OR_X2_SADDR),
        GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/1, // voffset
        GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/2, // data
        GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/0, // saddr
        GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/2, // offset
        GIR_AddImm8, /*InsnID*/0, /*Imm*/0,
        GIR_MergeMemOperands, /*InsnID*/0, /*NumInsns*/1, /*MergeInsnID's*/0,
        GIR_ConstrainSelectedInstOperands, /*InsnID*/0,
        GIR_EraseFromParent, /*InsnID*/0,
        // GIR_Coverage, 3239,
        GIR_Done,
      // Label 2648: @172513
      GIM_Try, /*On fail goto*//*Label 2649*/ GIMT_Encode4(172583), // Rule ID 3241 //
        GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasFlatGlobalInsts),
        GIM_CheckMemoryAddressSpace, /*MI*/0, /*MMO*/0, /*NumAddrSpace*/3, /*AddrSpace*/1, /*AddrSpace*/4, /*AddrSpace*/6,
        GIM_CheckRegBankForClass, /*MI*/0, /*Op*/0, /*RC*/GIMT_Encode2(AMDGPU::AV_64RegClassID),
        GIM_CheckPointerToAny, /*MI*/0, /*Op*/1, /*SizeInBits*/0,
        GIM_CheckComplexPattern, /*MI*/0, /*Op*/1, /*Renderer*/GIMT_Encode2(0), GIMT_Encode2(GICP_gi_global_saddr),
        // (atomic_load_or:{ *:[i64] } (GlobalSAddr:{ *:[iPTR] } SReg_64:{ *:[i64] }:$saddr, VGPR_32:{ *:[i32] }:$voffset, i32:{ *:[i32] }:$offset), i64:{ *:[i64] }:$data)<<P:Predicate_atomic_load_or_global_64>>  =>  (GLOBAL_ATOMIC_OR_X2_SADDR_RTN:{ *:[i64] } ?:{ *:[i32] }:$voffset, anonymous_15036:{ *:[i64] }:$data, ?:{ *:[i64] }:$saddr, ?:{ *:[i32] }:$offset)
        GIR_BuildMI, /*InsnID*/0, /*Opcode*/GIMT_Encode2(AMDGPU::GLOBAL_ATOMIC_OR_X2_SADDR_RTN),
        GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/0, // DstI[vdst]
        GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/1, // voffset
        GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/2, // data
        GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/0, // saddr
        GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/2, // offset
        GIR_AddImm8, /*InsnID*/0, /*Imm*/1,
        GIR_MergeMemOperands, /*InsnID*/0, /*NumInsns*/1, /*MergeInsnID's*/0,
        GIR_ConstrainSelectedInstOperands, /*InsnID*/0,
        GIR_EraseFromParent, /*InsnID*/0,
        // GIR_Coverage, 3241,
        GIR_Done,
      // Label 2649: @172583
      GIM_Try, /*On fail goto*//*Label 2650*/ GIMT_Encode4(172641), // Rule ID 3238 //
        GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasFlatGlobalInsts),
        GIM_CheckMemoryAddressSpace, /*MI*/0, /*MMO*/0, /*NumAddrSpace*/3, /*AddrSpace*/1, /*AddrSpace*/4, /*AddrSpace*/6,
        GIM_CheckHasNoUse, /*MI*/0,
        GIM_CheckPointerToAny, /*MI*/0, /*Op*/1, /*SizeInBits*/0,
        GIM_CheckComplexPattern, /*MI*/0, /*Op*/1, /*Renderer*/GIMT_Encode2(0), GIMT_Encode2(GICP_gi_global_offset),
        // (atomic_load_or:{ *:[i64] } (GlobalOffset:{ *:[iPTR] } i64:{ *:[i64] }:$vaddr, i32:{ *:[i32] }:$offset), i64:{ *:[i64] }:$data)<<P:Predicate_atomic_load_or_global_noret_64>>  =>  (GLOBAL_ATOMIC_OR_X2 VReg_64:{ *:[i64] }:$vaddr, anonymous_15036:{ *:[i64] }:$data, ?:{ *:[i32] }:$offset)
        GIR_BuildMI, /*InsnID*/0, /*Opcode*/GIMT_Encode2(AMDGPU::GLOBAL_ATOMIC_OR_X2),
        GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/0, // vaddr
        GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/2, // data
        GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/1, // offset
        GIR_AddImm8, /*InsnID*/0, /*Imm*/0,
        GIR_MergeMemOperands, /*InsnID*/0, /*NumInsns*/1, /*MergeInsnID's*/0,
        GIR_ConstrainSelectedInstOperands, /*InsnID*/0,
        GIR_EraseFromParent, /*InsnID*/0,
        // GIR_Coverage, 3238,
        GIR_Done,
      // Label 2650: @172641
      GIM_Try, /*On fail goto*//*Label 2651*/ GIMT_Encode4(172706), // Rule ID 3240 //
        GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasFlatGlobalInsts),
        GIM_CheckMemoryAddressSpace, /*MI*/0, /*MMO*/0, /*NumAddrSpace*/3, /*AddrSpace*/1, /*AddrSpace*/4, /*AddrSpace*/6,
        GIM_CheckRegBankForClass, /*MI*/0, /*Op*/0, /*RC*/GIMT_Encode2(AMDGPU::AV_64RegClassID),
        GIM_CheckPointerToAny, /*MI*/0, /*Op*/1, /*SizeInBits*/0,
        GIM_CheckComplexPattern, /*MI*/0, /*Op*/1, /*Renderer*/GIMT_Encode2(0), GIMT_Encode2(GICP_gi_global_offset),
        // (atomic_load_or:{ *:[i64] } (GlobalOffset:{ *:[iPTR] } i64:{ *:[i64] }:$vaddr, i32:{ *:[i32] }:$offset), i64:{ *:[i64] }:$data)<<P:Predicate_atomic_load_or_global_64>>  =>  (GLOBAL_ATOMIC_OR_X2_RTN:{ *:[i64] } VReg_64:{ *:[i64] }:$vaddr, anonymous_15036:{ *:[i64] }:$data, ?:{ *:[i32] }:$offset)
        GIR_BuildMI, /*InsnID*/0, /*Opcode*/GIMT_Encode2(AMDGPU::GLOBAL_ATOMIC_OR_X2_RTN),
        GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/0, // DstI[vdst]
        GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/0, // vaddr
        GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/2, // data
        GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/1, // offset
        GIR_AddImm8, /*InsnID*/0, /*Imm*/1,
        GIR_MergeMemOperands, /*InsnID*/0, /*NumInsns*/1, /*MergeInsnID's*/0,
        GIR_ConstrainSelectedInstOperands, /*InsnID*/0,
        GIR_EraseFromParent, /*InsnID*/0,
        // GIR_Coverage, 3240,
        GIR_Done,
      // Label 2651: @172706
      GIM_Try, /*On fail goto*//*Label 2652*/ GIMT_Encode4(172765), // Rule ID 2872 //
        GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasFlatAddressSpace),
        GIM_CheckMemoryAddressSpace, /*MI*/0, /*MMO*/0, /*NumAddrSpace*/4, /*AddrSpace*/0, /*AddrSpace*/1, /*AddrSpace*/4, /*AddrSpace*/6,
        GIM_CheckHasNoUse, /*MI*/0,
        GIM_CheckPointerToAny, /*MI*/0, /*Op*/1, /*SizeInBits*/0,
        GIM_CheckComplexPattern, /*MI*/0, /*Op*/1, /*Renderer*/GIMT_Encode2(0), GIMT_Encode2(GICP_gi_flat_offset),
        // (atomic_load_or:{ *:[i64] } (FlatOffset:{ *:[iPTR] } i64:{ *:[i64] }:$vaddr, i32:{ *:[i32] }:$offset), i64:{ *:[i64] }:$data)<<P:Predicate_atomic_load_or_flat_noret_64>>  =>  (FLAT_ATOMIC_OR_X2 VReg_64:{ *:[i64] }:$vaddr, anonymous_15036:{ *:[i64] }:$data, ?:{ *:[i32] }:$offset)
        GIR_BuildMI, /*InsnID*/0, /*Opcode*/GIMT_Encode2(AMDGPU::FLAT_ATOMIC_OR_X2),
        GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/0, // vaddr
        GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/2, // data
        GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/1, // offset
        GIR_AddImm8, /*InsnID*/0, /*Imm*/0,
        GIR_MergeMemOperands, /*InsnID*/0, /*NumInsns*/1, /*MergeInsnID's*/0,
        GIR_ConstrainSelectedInstOperands, /*InsnID*/0,
        GIR_EraseFromParent, /*InsnID*/0,
        // GIR_Coverage, 2872,
        GIR_Done,
      // Label 2652: @172765
      GIM_Try, /*On fail goto*//*Label 2653*/ GIMT_Encode4(172823), // Rule ID 2924 //
        GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasFlatAddressSpace),
        GIM_CheckMemoryAddressSpace, /*MI*/0, /*MMO*/0, /*NumAddrSpace*/3, /*AddrSpace*/1, /*AddrSpace*/4, /*AddrSpace*/6,
        GIM_CheckHasNoUse, /*MI*/0,
        GIM_CheckPointerToAny, /*MI*/0, /*Op*/1, /*SizeInBits*/0,
        GIM_CheckComplexPattern, /*MI*/0, /*Op*/1, /*Renderer*/GIMT_Encode2(0), GIMT_Encode2(GICP_gi_flat_offset),
        // (atomic_load_or:{ *:[i64] } (FlatOffset:{ *:[iPTR] } i64:{ *:[i64] }:$vaddr, i32:{ *:[i32] }:$offset), i64:{ *:[i64] }:$data)<<P:Predicate_atomic_load_or_global_noret_64>>  =>  (FLAT_ATOMIC_OR_X2 VReg_64:{ *:[i64] }:$vaddr, anonymous_15036:{ *:[i64] }:$data, ?:{ *:[i32] }:$offset)
        GIR_BuildMI, /*InsnID*/0, /*Opcode*/GIMT_Encode2(AMDGPU::FLAT_ATOMIC_OR_X2),
        GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/0, // vaddr
        GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/2, // data
        GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/1, // offset
        GIR_AddImm8, /*InsnID*/0, /*Imm*/0,
        GIR_MergeMemOperands, /*InsnID*/0, /*NumInsns*/1, /*MergeInsnID's*/0,
        GIR_ConstrainSelectedInstOperands, /*InsnID*/0,
        GIR_EraseFromParent, /*InsnID*/0,
        // GIR_Coverage, 2924,
        GIR_Done,
      // Label 2653: @172823
      GIM_Try, /*On fail goto*//*Label 2654*/ GIMT_Encode4(172889), // Rule ID 2871 //
        GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasFlatAddressSpace),
        GIM_CheckMemoryAddressSpace, /*MI*/0, /*MMO*/0, /*NumAddrSpace*/4, /*AddrSpace*/0, /*AddrSpace*/1, /*AddrSpace*/4, /*AddrSpace*/6,
        GIM_CheckRegBankForClass, /*MI*/0, /*Op*/0, /*RC*/GIMT_Encode2(AMDGPU::AV_64RegClassID),
        GIM_CheckPointerToAny, /*MI*/0, /*Op*/1, /*SizeInBits*/0,
        GIM_CheckComplexPattern, /*MI*/0, /*Op*/1, /*Renderer*/GIMT_Encode2(0), GIMT_Encode2(GICP_gi_flat_offset),
        // (atomic_load_or:{ *:[i64] } (FlatOffset:{ *:[iPTR] } i64:{ *:[i64] }:$vaddr, i32:{ *:[i32] }:$offset), i64:{ *:[i64] }:$data)<<P:Predicate_atomic_load_or_flat_64>>  =>  (FLAT_ATOMIC_OR_X2_RTN:{ *:[i64] } VReg_64:{ *:[i64] }:$vaddr, anonymous_15036:{ *:[i64] }:$data, ?:{ *:[i32] }:$offset)
        GIR_BuildMI, /*InsnID*/0, /*Opcode*/GIMT_Encode2(AMDGPU::FLAT_ATOMIC_OR_X2_RTN),
        GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/0, // DstI[vdst]
        GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/0, // vaddr
        GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/2, // data
        GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/1, // offset
        GIR_AddImm8, /*InsnID*/0, /*Imm*/1,
        GIR_MergeMemOperands, /*InsnID*/0, /*NumInsns*/1, /*MergeInsnID's*/0,
        GIR_ConstrainSelectedInstOperands, /*InsnID*/0,
        GIR_EraseFromParent, /*InsnID*/0,
        // GIR_Coverage, 2871,
        GIR_Done,
      // Label 2654: @172889
      GIM_Try, /*On fail goto*//*Label 2655*/ GIMT_Encode4(172954), // Rule ID 2923 //
        GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasFlatAddressSpace),
        GIM_CheckMemoryAddressSpace, /*MI*/0, /*MMO*/0, /*NumAddrSpace*/3, /*AddrSpace*/1, /*AddrSpace*/4, /*AddrSpace*/6,
        GIM_CheckRegBankForClass, /*MI*/0, /*Op*/0, /*RC*/GIMT_Encode2(AMDGPU::AV_64RegClassID),
        GIM_CheckPointerToAny, /*MI*/0, /*Op*/1, /*SizeInBits*/0,
        GIM_CheckComplexPattern, /*MI*/0, /*Op*/1, /*Renderer*/GIMT_Encode2(0), GIMT_Encode2(GICP_gi_flat_offset),
        // (atomic_load_or:{ *:[i64] } (FlatOffset:{ *:[iPTR] } i64:{ *:[i64] }:$vaddr, i32:{ *:[i32] }:$offset), i64:{ *:[i64] }:$data)<<P:Predicate_atomic_load_or_global_64>>  =>  (FLAT_ATOMIC_OR_X2_RTN:{ *:[i64] } VReg_64:{ *:[i64] }:$vaddr, anonymous_15036:{ *:[i64] }:$data, ?:{ *:[i32] }:$offset)
        GIR_BuildMI, /*InsnID*/0, /*Opcode*/GIMT_Encode2(AMDGPU::FLAT_ATOMIC_OR_X2_RTN),
        GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/0, // DstI[vdst]
        GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/0, // vaddr
        GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/2, // data
        GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/1, // offset
        GIR_AddImm8, /*InsnID*/0, /*Imm*/1,
        GIR_MergeMemOperands, /*InsnID*/0, /*NumInsns*/1, /*MergeInsnID's*/0,
        GIR_ConstrainSelectedInstOperands, /*InsnID*/0,
        GIR_EraseFromParent, /*InsnID*/0,
        // GIR_Coverage, 2923,
        GIR_Done,
      // Label 2655: @172954
      GIM_Reject,
    // Label 2633: @172955
    GIM_Reject,
    // Label 2609: @172956
    GIM_Reject,
    // Label 22: @172957
    GIM_SwitchType, /*MI*/0, /*Op*/0, /*[*/GIMT_Encode2(9), GIMT_Encode2(11), /*)*//*default:*//*Label 2658*/ GIMT_Encode4(175800),
    /*GILLT_s32*//*Label 2656*/ GIMT_Encode4(172976),
    /*GILLT_s64*//*Label 2657*/ GIMT_Encode4(174388),
    // Label 2656: @172976
    GIM_Try, /*On fail goto*//*Label 2659*/ GIMT_Encode4(174387),
      GIM_CheckType, /*MI*/0, /*Op*/2, /*Type*/GILLT_s32,
      GIM_Try, /*On fail goto*//*Label 2660*/ GIMT_Encode4(173053), // Rule ID 4582 //
        GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasUnrestrictedSOffset),
        GIM_CheckMemoryAddressSpace, /*MI*/0, /*MMO*/0, /*NumAddrSpace*/3, /*AddrSpace*/1, /*AddrSpace*/4, /*AddrSpace*/6,
        GIM_CheckHasNoUse, /*MI*/0,
        GIM_CheckPointerToAny, /*MI*/0, /*Op*/1, /*SizeInBits*/0,
        GIM_CheckComplexPattern, /*MI*/0, /*Op*/1, /*Renderer*/GIMT_Encode2(0), GIMT_Encode2(GICP_gi_mubuf_addr64),
        // (atomic_load_xor:{ *:[i32] } (MUBUFAddr64:{ *:[iPTR] } v4i32:{ *:[v4i32] }:$srsrc, i64:{ *:[i64] }:$vaddr, i32:{ *:[i32] }:$soffset, i32:{ *:[i32] }:$offset), i32:{ *:[i32] }:$vdata_in)<<P:Predicate_atomic_load_xor_global_noret_32>>  =>  (BUFFER_ATOMIC_XOR_ADDR64 anonymous_15037:{ *:[i32] }:$vdata_in, VReg_64:{ *:[i64] }:$vaddr, SReg_128:{ *:[v4i32] }:$srsrc, SCSrc_b32:{ *:[i32] }:$soffset, offset:{ *:[i32] }:$offset)
        GIR_BuildMI, /*InsnID*/0, /*Opcode*/GIMT_Encode2(AMDGPU::BUFFER_ATOMIC_XOR_ADDR64),
        GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/2, // vdata_in
        GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/1, // vaddr
        GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/0, // srsrc
        GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/2, // soffset
        GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/3, // offset
        GIR_AddImm8, /*InsnID*/0, /*Imm*/0,
        GIR_MergeMemOperands, /*InsnID*/0, /*NumInsns*/1, /*MergeInsnID's*/0,
        GIR_ConstrainSelectedInstOperands, /*InsnID*/0,
        GIR_EraseFromParent, /*InsnID*/0,
        // GIR_Coverage, 4582,
        GIR_Done,
      // Label 2660: @173053
      GIM_Try, /*On fail goto*//*Label 2661*/ GIMT_Encode4(173118), // Rule ID 4586 //
        GIM_CheckMemoryAddressSpace, /*MI*/0, /*MMO*/0, /*NumAddrSpace*/3, /*AddrSpace*/1, /*AddrSpace*/4, /*AddrSpace*/6,
        GIM_CheckHasNoUse, /*MI*/0,
        GIM_CheckPointerToAny, /*MI*/0, /*Op*/1, /*SizeInBits*/0,
        GIM_CheckComplexPattern, /*MI*/0, /*Op*/1, /*Renderer*/GIMT_Encode2(0), GIMT_Encode2(GICP_gi_mubuf_addr64),
        // (atomic_load_xor:{ *:[i32] } (MUBUFAddr64:{ *:[iPTR] } v4i32:{ *:[v4i32] }:$srsrc, i64:{ *:[i64] }:$vaddr, i32:{ *:[i32] }:$soffset, i32:{ *:[i32] }:$offset), i32:{ *:[i32] }:$vdata_in)<<P:Predicate_atomic_load_xor_global_noret_32>>  =>  (BUFFER_ATOMIC_XOR_VBUFFER_ADDR64 anonymous_15037:{ *:[i32] }:$vdata_in, VReg_64:{ *:[i64] }:$vaddr, SReg_128:{ *:[v4i32] }:$srsrc, SCSrc_b32:{ *:[i32] }:$soffset, offset:{ *:[i32] }:$offset)
        GIR_BuildMI, /*InsnID*/0, /*Opcode*/GIMT_Encode2(AMDGPU::BUFFER_ATOMIC_XOR_VBUFFER_ADDR64),
        GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/2, // vdata_in
        GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/1, // vaddr
        GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/0, // srsrc
        GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/2, // soffset
        GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/3, // offset
        GIR_AddImm8, /*InsnID*/0, /*Imm*/0,
        GIR_MergeMemOperands, /*InsnID*/0, /*NumInsns*/1, /*MergeInsnID's*/0,
        GIR_ConstrainSelectedInstOperands, /*InsnID*/0,
        GIR_EraseFromParent, /*InsnID*/0,
        // GIR_Coverage, 4586,
        GIR_Done,
      // Label 2661: @173118
      GIM_Try, /*On fail goto*//*Label 2662*/ GIMT_Encode4(173193), // Rule ID 4580 //
        GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasUnrestrictedSOffset),
        GIM_CheckMemoryAddressSpace, /*MI*/0, /*MMO*/0, /*NumAddrSpace*/3, /*AddrSpace*/1, /*AddrSpace*/4, /*AddrSpace*/6,
        GIM_CheckRegBankForClass, /*MI*/0, /*Op*/0, /*RC*/GIMT_Encode2(AMDGPU::AV_32RegClassID),
        GIM_CheckPointerToAny, /*MI*/0, /*Op*/1, /*SizeInBits*/0,
        GIM_CheckComplexPattern, /*MI*/0, /*Op*/1, /*Renderer*/GIMT_Encode2(0), GIMT_Encode2(GICP_gi_mubuf_addr64),
        // (atomic_load_xor:{ *:[i32] } (MUBUFAddr64:{ *:[iPTR] } v4i32:{ *:[v4i32] }:$srsrc, i64:{ *:[i64] }:$vaddr, i32:{ *:[i32] }:$soffset, i32:{ *:[i32] }:$offset), i32:{ *:[i32] }:$vdata_in)<<P:Predicate_atomic_load_xor_global_32>>  =>  (BUFFER_ATOMIC_XOR_ADDR64_RTN:{ *:[i32] } anonymous_15037:{ *:[i32] }:$vdata_in, VReg_64:{ *:[i64] }:$vaddr, SReg_128:{ *:[v4i32] }:$srsrc, SCSrc_b32:{ *:[i32] }:$soffset, offset:{ *:[i32] }:$offset)
        GIR_BuildMI, /*InsnID*/0, /*Opcode*/GIMT_Encode2(AMDGPU::BUFFER_ATOMIC_XOR_ADDR64_RTN),
        GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/0, // DstI[vdata]
        GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/2, // vdata_in
        GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/1, // vaddr
        GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/0, // srsrc
        GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/2, // soffset
        GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/3, // offset
        GIR_AddImm8, /*InsnID*/0, /*Imm*/1,
        GIR_MergeMemOperands, /*InsnID*/0, /*NumInsns*/1, /*MergeInsnID's*/0,
        GIR_ConstrainSelectedInstOperands, /*InsnID*/0,
        GIR_EraseFromParent, /*InsnID*/0,
        // GIR_Coverage, 4580,
        GIR_Done,
      // Label 2662: @173193
      GIM_Try, /*On fail goto*//*Label 2663*/ GIMT_Encode4(173265), // Rule ID 4584 //
        GIM_CheckMemoryAddressSpace, /*MI*/0, /*MMO*/0, /*NumAddrSpace*/3, /*AddrSpace*/1, /*AddrSpace*/4, /*AddrSpace*/6,
        GIM_CheckRegBankForClass, /*MI*/0, /*Op*/0, /*RC*/GIMT_Encode2(AMDGPU::AV_32RegClassID),
        GIM_CheckPointerToAny, /*MI*/0, /*Op*/1, /*SizeInBits*/0,
        GIM_CheckComplexPattern, /*MI*/0, /*Op*/1, /*Renderer*/GIMT_Encode2(0), GIMT_Encode2(GICP_gi_mubuf_addr64),
        // (atomic_load_xor:{ *:[i32] } (MUBUFAddr64:{ *:[iPTR] } v4i32:{ *:[v4i32] }:$srsrc, i64:{ *:[i64] }:$vaddr, i32:{ *:[i32] }:$soffset, i32:{ *:[i32] }:$offset), i32:{ *:[i32] }:$vdata_in)<<P:Predicate_atomic_load_xor_global_32>>  =>  (BUFFER_ATOMIC_XOR_VBUFFER_ADDR64_RTN:{ *:[i32] } anonymous_15037:{ *:[i32] }:$vdata_in, VReg_64:{ *:[i64] }:$vaddr, SReg_128:{ *:[v4i32] }:$srsrc, SCSrc_b32:{ *:[i32] }:$soffset, offset:{ *:[i32] }:$offset)
        GIR_BuildMI, /*InsnID*/0, /*Opcode*/GIMT_Encode2(AMDGPU::BUFFER_ATOMIC_XOR_VBUFFER_ADDR64_RTN),
        GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/0, // DstI[vdata]
        GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/2, // vdata_in
        GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/1, // vaddr
        GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/0, // srsrc
        GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/2, // soffset
        GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/3, // offset
        GIR_AddImm8, /*InsnID*/0, /*Imm*/1,
        GIR_MergeMemOperands, /*InsnID*/0, /*NumInsns*/1, /*MergeInsnID's*/0,
        GIR_ConstrainSelectedInstOperands, /*InsnID*/0,
        GIR_EraseFromParent, /*InsnID*/0,
        // GIR_Coverage, 4584,
        GIR_Done,
      // Label 2663: @173265
      GIM_Try, /*On fail goto*//*Label 2664*/ GIMT_Encode4(173328), // Rule ID 4581 //
        GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasUnrestrictedSOffset),
        GIM_CheckMemoryAddressSpace, /*MI*/0, /*MMO*/0, /*NumAddrSpace*/3, /*AddrSpace*/1, /*AddrSpace*/4, /*AddrSpace*/6,
        GIM_CheckHasNoUse, /*MI*/0,
        GIM_CheckPointerToAny, /*MI*/0, /*Op*/1, /*SizeInBits*/0,
        GIM_CheckComplexPattern, /*MI*/0, /*Op*/1, /*Renderer*/GIMT_Encode2(0), GIMT_Encode2(GICP_gi_mubuf_offset),
        // (atomic_load_xor:{ *:[i32] } (MUBUFOffset:{ *:[iPTR] } v4i32:{ *:[v4i32] }:$srsrc, i32:{ *:[i32] }:$soffset, i32:{ *:[i32] }:$offset), i32:{ *:[i32] }:$vdata_in)<<P:Predicate_atomic_load_xor_global_noret_32>>  =>  (BUFFER_ATOMIC_XOR_OFFSET anonymous_15037:{ *:[i32] }:$vdata_in, SReg_128:{ *:[v4i32] }:$srsrc, SCSrc_b32:{ *:[i32] }:$soffset, offset:{ *:[i32] }:$offset)
        GIR_BuildMI, /*InsnID*/0, /*Opcode*/GIMT_Encode2(AMDGPU::BUFFER_ATOMIC_XOR_OFFSET),
        GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/2, // vdata_in
        GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/0, // srsrc
        GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/1, // soffset
        GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/2, // offset
        GIR_AddImm8, /*InsnID*/0, /*Imm*/0,
        GIR_MergeMemOperands, /*InsnID*/0, /*NumInsns*/1, /*MergeInsnID's*/0,
        GIR_ConstrainSelectedInstOperands, /*InsnID*/0,
        GIR_EraseFromParent, /*InsnID*/0,
        // GIR_Coverage, 4581,
        GIR_Done,
      // Label 2664: @173328
      GIM_Try, /*On fail goto*//*Label 2665*/ GIMT_Encode4(173388), // Rule ID 4585 //
        GIM_CheckMemoryAddressSpace, /*MI*/0, /*MMO*/0, /*NumAddrSpace*/3, /*AddrSpace*/1, /*AddrSpace*/4, /*AddrSpace*/6,
        GIM_CheckHasNoUse, /*MI*/0,
        GIM_CheckPointerToAny, /*MI*/0, /*Op*/1, /*SizeInBits*/0,
        GIM_CheckComplexPattern, /*MI*/0, /*Op*/1, /*Renderer*/GIMT_Encode2(0), GIMT_Encode2(GICP_gi_mubuf_offset),
        // (atomic_load_xor:{ *:[i32] } (MUBUFOffset:{ *:[iPTR] } v4i32:{ *:[v4i32] }:$srsrc, i32:{ *:[i32] }:$soffset, i32:{ *:[i32] }:$offset), i32:{ *:[i32] }:$vdata_in)<<P:Predicate_atomic_load_xor_global_noret_32>>  =>  (BUFFER_ATOMIC_XOR_VBUFFER_OFFSET anonymous_15037:{ *:[i32] }:$vdata_in, SReg_128:{ *:[v4i32] }:$srsrc, SCSrc_b32:{ *:[i32] }:$soffset, offset:{ *:[i32] }:$offset)
        GIR_BuildMI, /*InsnID*/0, /*Opcode*/GIMT_Encode2(AMDGPU::BUFFER_ATOMIC_XOR_VBUFFER_OFFSET),
        GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/2, // vdata_in
        GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/0, // srsrc
        GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/1, // soffset
        GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/2, // offset
        GIR_AddImm8, /*InsnID*/0, /*Imm*/0,
        GIR_MergeMemOperands, /*InsnID*/0, /*NumInsns*/1, /*MergeInsnID's*/0,
        GIR_ConstrainSelectedInstOperands, /*InsnID*/0,
        GIR_EraseFromParent, /*InsnID*/0,
        // GIR_Coverage, 4585,
        GIR_Done,
      // Label 2665: @173388
      GIM_Try, /*On fail goto*//*Label 2666*/ GIMT_Encode4(173458), // Rule ID 4579 //
        GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasUnrestrictedSOffset),
        GIM_CheckMemoryAddressSpace, /*MI*/0, /*MMO*/0, /*NumAddrSpace*/3, /*AddrSpace*/1, /*AddrSpace*/4, /*AddrSpace*/6,
        GIM_CheckRegBankForClass, /*MI*/0, /*Op*/0, /*RC*/GIMT_Encode2(AMDGPU::AV_32RegClassID),
        GIM_CheckPointerToAny, /*MI*/0, /*Op*/1, /*SizeInBits*/0,
        GIM_CheckComplexPattern, /*MI*/0, /*Op*/1, /*Renderer*/GIMT_Encode2(0), GIMT_Encode2(GICP_gi_mubuf_offset),
        // (atomic_load_xor:{ *:[i32] } (MUBUFOffset:{ *:[iPTR] } v4i32:{ *:[v4i32] }:$srsrc, i32:{ *:[i32] }:$soffset, i32:{ *:[i32] }:$offset), i32:{ *:[i32] }:$vdata_in)<<P:Predicate_atomic_load_xor_global_32>>  =>  (BUFFER_ATOMIC_XOR_OFFSET_RTN:{ *:[i32] } anonymous_15037:{ *:[i32] }:$vdata_in, SReg_128:{ *:[v4i32] }:$srsrc, SCSrc_b32:{ *:[i32] }:$soffset, offset:{ *:[i32] }:$offset)
        GIR_BuildMI, /*InsnID*/0, /*Opcode*/GIMT_Encode2(AMDGPU::BUFFER_ATOMIC_XOR_OFFSET_RTN),
        GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/0, // DstI[vdata]
        GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/2, // vdata_in
        GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/0, // srsrc
        GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/1, // soffset
        GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/2, // offset
        GIR_AddImm8, /*InsnID*/0, /*Imm*/1,
        GIR_MergeMemOperands, /*InsnID*/0, /*NumInsns*/1, /*MergeInsnID's*/0,
        GIR_ConstrainSelectedInstOperands, /*InsnID*/0,
        GIR_EraseFromParent, /*InsnID*/0,
        // GIR_Coverage, 4579,
        GIR_Done,
      // Label 2666: @173458
      GIM_Try, /*On fail goto*//*Label 2667*/ GIMT_Encode4(173525), // Rule ID 4583 //
        GIM_CheckMemoryAddressSpace, /*MI*/0, /*MMO*/0, /*NumAddrSpace*/3, /*AddrSpace*/1, /*AddrSpace*/4, /*AddrSpace*/6,
        GIM_CheckRegBankForClass, /*MI*/0, /*Op*/0, /*RC*/GIMT_Encode2(AMDGPU::AV_32RegClassID),
        GIM_CheckPointerToAny, /*MI*/0, /*Op*/1, /*SizeInBits*/0,
        GIM_CheckComplexPattern, /*MI*/0, /*Op*/1, /*Renderer*/GIMT_Encode2(0), GIMT_Encode2(GICP_gi_mubuf_offset),
        // (atomic_load_xor:{ *:[i32] } (MUBUFOffset:{ *:[iPTR] } v4i32:{ *:[v4i32] }:$srsrc, i32:{ *:[i32] }:$soffset, i32:{ *:[i32] }:$offset), i32:{ *:[i32] }:$vdata_in)<<P:Predicate_atomic_load_xor_global_32>>  =>  (BUFFER_ATOMIC_XOR_VBUFFER_OFFSET_RTN:{ *:[i32] } anonymous_15037:{ *:[i32] }:$vdata_in, SReg_128:{ *:[v4i32] }:$srsrc, SCSrc_b32:{ *:[i32] }:$soffset, offset:{ *:[i32] }:$offset)
        GIR_BuildMI, /*InsnID*/0, /*Opcode*/GIMT_Encode2(AMDGPU::BUFFER_ATOMIC_XOR_VBUFFER_OFFSET_RTN),
        GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/0, // DstI[vdata]
        GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/2, // vdata_in
        GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/0, // srsrc
        GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/1, // soffset
        GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/2, // offset
        GIR_AddImm8, /*InsnID*/0, /*Imm*/1,
        GIR_MergeMemOperands, /*InsnID*/0, /*NumInsns*/1, /*MergeInsnID's*/0,
        GIR_ConstrainSelectedInstOperands, /*InsnID*/0,
        GIR_EraseFromParent, /*InsnID*/0,
        // GIR_Coverage, 4583,
        GIR_Done,
      // Label 2667: @173525
      GIM_Try, /*On fail goto*//*Label 2668*/ GIMT_Encode4(173581), // Rule ID 6941 //
        GIM_CheckFeatures, GIMT_Encode2(GIFBS_LDSRequiresM0Init),
        GIM_CheckMemoryAddressSpace, /*MI*/0, /*MMO*/0, /*NumAddrSpace*/1, /*AddrSpace*/3,
        GIM_CheckHasNoUse, /*MI*/0,
        GIM_CheckPointerToAny, /*MI*/0, /*Op*/1, /*SizeInBits*/0,
        GIM_CheckComplexPattern, /*MI*/0, /*Op*/1, /*Renderer*/GIMT_Encode2(0), GIMT_Encode2(GICP_gi_ds_1addr_1offset),
        // (atomic_load_xor_glue:{ *:[i32] } (DS1Addr1Offset:{ *:[iPTR] } i32:{ *:[i32] }:$ptr, i32:{ *:[i32] }:$offset), i32:{ *:[i32] }:$value)<<P:Predicate_atomic_load_xor_local_m0_noret_32>>  =>  (DS_XOR_B32 ?:{ *:[i32] }:$ptr, anonymous_15037:{ *:[i32] }:$value, offset:{ *:[i32] }:$offset, 0:{ *:[i1] })
        GIR_BuildMI, /*InsnID*/0, /*Opcode*/GIMT_Encode2(AMDGPU::DS_XOR_B32),
        GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/0, // ptr
        GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/2, // value
        GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/1, // offset
        GIR_AddImm8, /*InsnID*/0, /*Imm*/0,
        GIR_MergeMemOperands, /*InsnID*/0, /*NumInsns*/1, /*MergeInsnID's*/0,
        GIR_ConstrainSelectedInstOperands, /*InsnID*/0,
        GIR_EraseFromParent, /*InsnID*/0,
        // GIR_Coverage, 6941,
        GIR_Done,
      // Label 2668: @173581
      GIM_Try, /*On fail goto*//*Label 2669*/ GIMT_Encode4(173637), // Rule ID 6943 //
        GIM_CheckFeatures, GIMT_Encode2(GIFBS_NotLDSRequiresM0Init),
        GIM_CheckMemoryAddressSpace, /*MI*/0, /*MMO*/0, /*NumAddrSpace*/1, /*AddrSpace*/3,
        GIM_CheckHasNoUse, /*MI*/0,
        GIM_CheckPointerToAny, /*MI*/0, /*Op*/1, /*SizeInBits*/0,
        GIM_CheckComplexPattern, /*MI*/0, /*Op*/1, /*Renderer*/GIMT_Encode2(0), GIMT_Encode2(GICP_gi_ds_1addr_1offset),
        // (atomic_load_xor:{ *:[i32] } (DS1Addr1Offset:{ *:[iPTR] } i32:{ *:[i32] }:$ptr, i32:{ *:[i32] }:$offset), i32:{ *:[i32] }:$value)<<P:Predicate_atomic_load_xor_local_noret_32>>  =>  (DS_XOR_B32_gfx9 ?:{ *:[i32] }:$ptr, anonymous_15037:{ *:[i32] }:$value, offset:{ *:[i32] }:$offset, 0:{ *:[i1] })
        GIR_BuildMI, /*InsnID*/0, /*Opcode*/GIMT_Encode2(AMDGPU::DS_XOR_B32_gfx9),
        GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/0, // ptr
        GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/2, // value
        GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/1, // offset
        GIR_AddImm8, /*InsnID*/0, /*Imm*/0,
        GIR_MergeMemOperands, /*InsnID*/0, /*NumInsns*/1, /*MergeInsnID's*/0,
        GIR_ConstrainSelectedInstOperands, /*InsnID*/0,
        GIR_EraseFromParent, /*InsnID*/0,
        // GIR_Coverage, 6943,
        GIR_Done,
      // Label 2669: @173637
      GIM_Try, /*On fail goto*//*Label 2670*/ GIMT_Encode4(173693), // Rule ID 6945 //
        GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasGDS),
        GIM_CheckMemoryAddressSpace, /*MI*/0, /*MMO*/0, /*NumAddrSpace*/1, /*AddrSpace*/2,
        GIM_CheckHasNoUse, /*MI*/0,
        GIM_CheckPointerToAny, /*MI*/0, /*Op*/1, /*SizeInBits*/0,
        GIM_CheckComplexPattern, /*MI*/0, /*Op*/1, /*Renderer*/GIMT_Encode2(0), GIMT_Encode2(GICP_gi_ds_1addr_1offset),
        // (atomic_load_xor_glue:{ *:[i32] } (DS1Addr1Offset:{ *:[iPTR] } i32:{ *:[i32] }:$ptr, i32:{ *:[i32] }:$offset), i32:{ *:[i32] }:$value)<<P:Predicate_atomic_load_xor_region_m0_noret_32>>  =>  (DS_XOR_B32 ?:{ *:[i32] }:$ptr, anonymous_15037:{ *:[i32] }:$value, offset:{ *:[i32] }:$offset, 1:{ *:[i1] })
        GIR_BuildMI, /*InsnID*/0, /*Opcode*/GIMT_Encode2(AMDGPU::DS_XOR_B32),
        GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/0, // ptr
        GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/2, // value
        GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/1, // offset
        GIR_AddImm8, /*InsnID*/0, /*Imm*/1,
        GIR_MergeMemOperands, /*InsnID*/0, /*NumInsns*/1, /*MergeInsnID's*/0,
        GIR_ConstrainSelectedInstOperands, /*InsnID*/0,
        GIR_EraseFromParent, /*InsnID*/0,
        // GIR_Coverage, 6945,
        GIR_Done,
      // Label 2670: @173693
      GIM_Try, /*On fail goto*//*Label 2671*/ GIMT_Encode4(173756), // Rule ID 6940 //
        GIM_CheckFeatures, GIMT_Encode2(GIFBS_LDSRequiresM0Init),
        GIM_CheckMemoryAddressSpace, /*MI*/0, /*MMO*/0, /*NumAddrSpace*/1, /*AddrSpace*/3,
        GIM_CheckRegBankForClass, /*MI*/0, /*Op*/0, /*RC*/GIMT_Encode2(AMDGPU::AV_32RegClassID),
        GIM_CheckPointerToAny, /*MI*/0, /*Op*/1, /*SizeInBits*/0,
        GIM_CheckComplexPattern, /*MI*/0, /*Op*/1, /*Renderer*/GIMT_Encode2(0), GIMT_Encode2(GICP_gi_ds_1addr_1offset),
        // (atomic_load_xor_glue:{ *:[i32] } (DS1Addr1Offset:{ *:[iPTR] } i32:{ *:[i32] }:$ptr, i32:{ *:[i32] }:$offset), i32:{ *:[i32] }:$value)<<P:Predicate_atomic_load_xor_local_m0_32>>  =>  (DS_XOR_RTN_B32:{ *:[i32] } ?:{ *:[i32] }:$ptr, anonymous_15037:{ *:[i32] }:$value, offset:{ *:[i32] }:$offset, 0:{ *:[i1] })
        GIR_BuildMI, /*InsnID*/0, /*Opcode*/GIMT_Encode2(AMDGPU::DS_XOR_RTN_B32),
        GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/0, // DstI[vdst]
        GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/0, // ptr
        GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/2, // value
        GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/1, // offset
        GIR_AddImm8, /*InsnID*/0, /*Imm*/0,
        GIR_MergeMemOperands, /*InsnID*/0, /*NumInsns*/1, /*MergeInsnID's*/0,
        GIR_ConstrainSelectedInstOperands, /*InsnID*/0,
        GIR_EraseFromParent, /*InsnID*/0,
        // GIR_Coverage, 6940,
        GIR_Done,
      // Label 2671: @173756
      GIM_Try, /*On fail goto*//*Label 2672*/ GIMT_Encode4(173819), // Rule ID 6942 //
        GIM_CheckFeatures, GIMT_Encode2(GIFBS_NotLDSRequiresM0Init),
        GIM_CheckMemoryAddressSpace, /*MI*/0, /*MMO*/0, /*NumAddrSpace*/1, /*AddrSpace*/3,
        GIM_CheckRegBankForClass, /*MI*/0, /*Op*/0, /*RC*/GIMT_Encode2(AMDGPU::AV_32RegClassID),
        GIM_CheckPointerToAny, /*MI*/0, /*Op*/1, /*SizeInBits*/0,
        GIM_CheckComplexPattern, /*MI*/0, /*Op*/1, /*Renderer*/GIMT_Encode2(0), GIMT_Encode2(GICP_gi_ds_1addr_1offset),
        // (atomic_load_xor:{ *:[i32] } (DS1Addr1Offset:{ *:[iPTR] } i32:{ *:[i32] }:$ptr, i32:{ *:[i32] }:$offset), i32:{ *:[i32] }:$value)<<P:Predicate_atomic_load_xor_local_32>>  =>  (DS_XOR_RTN_B32_gfx9:{ *:[i32] } ?:{ *:[i32] }:$ptr, anonymous_15037:{ *:[i32] }:$value, offset:{ *:[i32] }:$offset, 0:{ *:[i1] })
        GIR_BuildMI, /*InsnID*/0, /*Opcode*/GIMT_Encode2(AMDGPU::DS_XOR_RTN_B32_gfx9),
        GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/0, // DstI[vdst]
        GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/0, // ptr
        GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/2, // value
        GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/1, // offset
        GIR_AddImm8, /*InsnID*/0, /*Imm*/0,
        GIR_MergeMemOperands, /*InsnID*/0, /*NumInsns*/1, /*MergeInsnID's*/0,
        GIR_ConstrainSelectedInstOperands, /*InsnID*/0,
        GIR_EraseFromParent, /*InsnID*/0,
        // GIR_Coverage, 6942,
        GIR_Done,
      // Label 2672: @173819
      GIM_Try, /*On fail goto*//*Label 2673*/ GIMT_Encode4(173882), // Rule ID 6944 //
        GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasGDS),
        GIM_CheckMemoryAddressSpace, /*MI*/0, /*MMO*/0, /*NumAddrSpace*/1, /*AddrSpace*/2,
        GIM_CheckRegBankForClass, /*MI*/0, /*Op*/0, /*RC*/GIMT_Encode2(AMDGPU::AV_32RegClassID),
        GIM_CheckPointerToAny, /*MI*/0, /*Op*/1, /*SizeInBits*/0,
        GIM_CheckComplexPattern, /*MI*/0, /*Op*/1, /*Renderer*/GIMT_Encode2(0), GIMT_Encode2(GICP_gi_ds_1addr_1offset),
        // (atomic_load_xor_glue:{ *:[i32] } (DS1Addr1Offset:{ *:[iPTR] } i32:{ *:[i32] }:$ptr, i32:{ *:[i32] }:$offset), i32:{ *:[i32] }:$value)<<P:Predicate_atomic_load_xor_region_m0_32>>  =>  (DS_XOR_RTN_B32:{ *:[i32] } ?:{ *:[i32] }:$ptr, anonymous_15037:{ *:[i32] }:$value, offset:{ *:[i32] }:$offset, 1:{ *:[i1] })
        GIR_BuildMI, /*InsnID*/0, /*Opcode*/GIMT_Encode2(AMDGPU::DS_XOR_RTN_B32),
        GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/0, // DstI[vdst]
        GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/0, // ptr
        GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/2, // value
        GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/1, // offset
        GIR_AddImm8, /*InsnID*/0, /*Imm*/1,
        GIR_MergeMemOperands, /*InsnID*/0, /*NumInsns*/1, /*MergeInsnID's*/0,
        GIR_ConstrainSelectedInstOperands, /*InsnID*/0,
        GIR_EraseFromParent, /*InsnID*/0,
        // GIR_Coverage, 6944,
        GIR_Done,
      // Label 2673: @173882
      GIM_Try, /*On fail goto*//*Label 2674*/ GIMT_Encode4(173945), // Rule ID 3195 //
        GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasFlatGlobalInsts),
        GIM_CheckMemoryAddressSpace, /*MI*/0, /*MMO*/0, /*NumAddrSpace*/3, /*AddrSpace*/1, /*AddrSpace*/4, /*AddrSpace*/6,
        GIM_CheckHasNoUse, /*MI*/0,
        GIM_CheckPointerToAny, /*MI*/0, /*Op*/1, /*SizeInBits*/0,
        GIM_CheckComplexPattern, /*MI*/0, /*Op*/1, /*Renderer*/GIMT_Encode2(0), GIMT_Encode2(GICP_gi_global_saddr),
        // (atomic_load_xor:{ *:[i32] } (GlobalSAddr:{ *:[iPTR] } SReg_64:{ *:[i64] }:$saddr, VGPR_32:{ *:[i32] }:$voffset, i32:{ *:[i32] }:$offset), i32:{ *:[i32] }:$data)<<P:Predicate_atomic_load_xor_global_noret_32>>  =>  (GLOBAL_ATOMIC_XOR_SADDR ?:{ *:[i32] }:$voffset, anonymous_15037:{ *:[i32] }:$data, ?:{ *:[i64] }:$saddr, ?:{ *:[i32] }:$offset)
        GIR_BuildMI, /*InsnID*/0, /*Opcode*/GIMT_Encode2(AMDGPU::GLOBAL_ATOMIC_XOR_SADDR),
        GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/1, // voffset
        GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/2, // data
        GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/0, // saddr
        GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/2, // offset
        GIR_AddImm8, /*InsnID*/0, /*Imm*/0,
        GIR_MergeMemOperands, /*InsnID*/0, /*NumInsns*/1, /*MergeInsnID's*/0,
        GIR_ConstrainSelectedInstOperands, /*InsnID*/0,
        GIR_EraseFromParent, /*InsnID*/0,
        // GIR_Coverage, 3195,
        GIR_Done,
      // Label 2674: @173945
      GIM_Try, /*On fail goto*//*Label 2675*/ GIMT_Encode4(174015), // Rule ID 3197 //
        GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasFlatGlobalInsts),
        GIM_CheckMemoryAddressSpace, /*MI*/0, /*MMO*/0, /*NumAddrSpace*/3, /*AddrSpace*/1, /*AddrSpace*/4, /*AddrSpace*/6,
        GIM_CheckRegBankForClass, /*MI*/0, /*Op*/0, /*RC*/GIMT_Encode2(AMDGPU::AV_32RegClassID),
        GIM_CheckPointerToAny, /*MI*/0, /*Op*/1, /*SizeInBits*/0,
        GIM_CheckComplexPattern, /*MI*/0, /*Op*/1, /*Renderer*/GIMT_Encode2(0), GIMT_Encode2(GICP_gi_global_saddr),
        // (atomic_load_xor:{ *:[i32] } (GlobalSAddr:{ *:[iPTR] } SReg_64:{ *:[i64] }:$saddr, VGPR_32:{ *:[i32] }:$voffset, i32:{ *:[i32] }:$offset), i32:{ *:[i32] }:$data)<<P:Predicate_atomic_load_xor_global_32>>  =>  (GLOBAL_ATOMIC_XOR_SADDR_RTN:{ *:[i32] } ?:{ *:[i32] }:$voffset, anonymous_15037:{ *:[i32] }:$data, ?:{ *:[i64] }:$saddr, ?:{ *:[i32] }:$offset)
        GIR_BuildMI, /*InsnID*/0, /*Opcode*/GIMT_Encode2(AMDGPU::GLOBAL_ATOMIC_XOR_SADDR_RTN),
        GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/0, // DstI[vdst]
        GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/1, // voffset
        GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/2, // data
        GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/0, // saddr
        GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/2, // offset
        GIR_AddImm8, /*InsnID*/0, /*Imm*/1,
        GIR_MergeMemOperands, /*InsnID*/0, /*NumInsns*/1, /*MergeInsnID's*/0,
        GIR_ConstrainSelectedInstOperands, /*InsnID*/0,
        GIR_EraseFromParent, /*InsnID*/0,
        // GIR_Coverage, 3197,
        GIR_Done,
      // Label 2675: @174015
      GIM_Try, /*On fail goto*//*Label 2676*/ GIMT_Encode4(174073), // Rule ID 3194 //
        GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasFlatGlobalInsts),
        GIM_CheckMemoryAddressSpace, /*MI*/0, /*MMO*/0, /*NumAddrSpace*/3, /*AddrSpace*/1, /*AddrSpace*/4, /*AddrSpace*/6,
        GIM_CheckHasNoUse, /*MI*/0,
        GIM_CheckPointerToAny, /*MI*/0, /*Op*/1, /*SizeInBits*/0,
        GIM_CheckComplexPattern, /*MI*/0, /*Op*/1, /*Renderer*/GIMT_Encode2(0), GIMT_Encode2(GICP_gi_global_offset),
        // (atomic_load_xor:{ *:[i32] } (GlobalOffset:{ *:[iPTR] } i64:{ *:[i64] }:$vaddr, i32:{ *:[i32] }:$offset), i32:{ *:[i32] }:$data)<<P:Predicate_atomic_load_xor_global_noret_32>>  =>  (GLOBAL_ATOMIC_XOR VReg_64:{ *:[i64] }:$vaddr, anonymous_15037:{ *:[i32] }:$data, ?:{ *:[i32] }:$offset)
        GIR_BuildMI, /*InsnID*/0, /*Opcode*/GIMT_Encode2(AMDGPU::GLOBAL_ATOMIC_XOR),
        GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/0, // vaddr
        GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/2, // data
        GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/1, // offset
        GIR_AddImm8, /*InsnID*/0, /*Imm*/0,
        GIR_MergeMemOperands, /*InsnID*/0, /*NumInsns*/1, /*MergeInsnID's*/0,
        GIR_ConstrainSelectedInstOperands, /*InsnID*/0,
        GIR_EraseFromParent, /*InsnID*/0,
        // GIR_Coverage, 3194,
        GIR_Done,
      // Label 2676: @174073
      GIM_Try, /*On fail goto*//*Label 2677*/ GIMT_Encode4(174138), // Rule ID 3196 //
        GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasFlatGlobalInsts),
        GIM_CheckMemoryAddressSpace, /*MI*/0, /*MMO*/0, /*NumAddrSpace*/3, /*AddrSpace*/1, /*AddrSpace*/4, /*AddrSpace*/6,
        GIM_CheckRegBankForClass, /*MI*/0, /*Op*/0, /*RC*/GIMT_Encode2(AMDGPU::AV_32RegClassID),
        GIM_CheckPointerToAny, /*MI*/0, /*Op*/1, /*SizeInBits*/0,
        GIM_CheckComplexPattern, /*MI*/0, /*Op*/1, /*Renderer*/GIMT_Encode2(0), GIMT_Encode2(GICP_gi_global_offset),
        // (atomic_load_xor:{ *:[i32] } (GlobalOffset:{ *:[iPTR] } i64:{ *:[i64] }:$vaddr, i32:{ *:[i32] }:$offset), i32:{ *:[i32] }:$data)<<P:Predicate_atomic_load_xor_global_32>>  =>  (GLOBAL_ATOMIC_XOR_RTN:{ *:[i32] } VReg_64:{ *:[i64] }:$vaddr, anonymous_15037:{ *:[i32] }:$data, ?:{ *:[i32] }:$offset)
        GIR_BuildMI, /*InsnID*/0, /*Opcode*/GIMT_Encode2(AMDGPU::GLOBAL_ATOMIC_XOR_RTN),
        GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/0, // DstI[vdst]
        GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/0, // vaddr
        GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/2, // data
        GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/1, // offset
        GIR_AddImm8, /*InsnID*/0, /*Imm*/1,
        GIR_MergeMemOperands, /*InsnID*/0, /*NumInsns*/1, /*MergeInsnID's*/0,
        GIR_ConstrainSelectedInstOperands, /*InsnID*/0,
        GIR_EraseFromParent, /*InsnID*/0,
        // GIR_Coverage, 3196,
        GIR_Done,
      // Label 2677: @174138
      GIM_Try, /*On fail goto*//*Label 2678*/ GIMT_Encode4(174197), // Rule ID 2852 //
        GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasFlatAddressSpace),
        GIM_CheckMemoryAddressSpace, /*MI*/0, /*MMO*/0, /*NumAddrSpace*/4, /*AddrSpace*/0, /*AddrSpace*/1, /*AddrSpace*/4, /*AddrSpace*/6,
        GIM_CheckHasNoUse, /*MI*/0,
        GIM_CheckPointerToAny, /*MI*/0, /*Op*/1, /*SizeInBits*/0,
        GIM_CheckComplexPattern, /*MI*/0, /*Op*/1, /*Renderer*/GIMT_Encode2(0), GIMT_Encode2(GICP_gi_flat_offset),
        // (atomic_load_xor:{ *:[i32] } (FlatOffset:{ *:[iPTR] } i64:{ *:[i64] }:$vaddr, i32:{ *:[i32] }:$offset), i32:{ *:[i32] }:$data)<<P:Predicate_atomic_load_xor_flat_noret_32>>  =>  (FLAT_ATOMIC_XOR VReg_64:{ *:[i64] }:$vaddr, anonymous_15037:{ *:[i32] }:$data, ?:{ *:[i32] }:$offset)
        GIR_BuildMI, /*InsnID*/0, /*Opcode*/GIMT_Encode2(AMDGPU::FLAT_ATOMIC_XOR),
        GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/0, // vaddr
        GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/2, // data
        GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/1, // offset
        GIR_AddImm8, /*InsnID*/0, /*Imm*/0,
        GIR_MergeMemOperands, /*InsnID*/0, /*NumInsns*/1, /*MergeInsnID's*/0,
        GIR_ConstrainSelectedInstOperands, /*InsnID*/0,
        GIR_EraseFromParent, /*InsnID*/0,
        // GIR_Coverage, 2852,
        GIR_Done,
      // Label 2678: @174197
      GIM_Try, /*On fail goto*//*Label 2679*/ GIMT_Encode4(174255), // Rule ID 2904 //
        GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasFlatAddressSpace),
        GIM_CheckMemoryAddressSpace, /*MI*/0, /*MMO*/0, /*NumAddrSpace*/3, /*AddrSpace*/1, /*AddrSpace*/4, /*AddrSpace*/6,
        GIM_CheckHasNoUse, /*MI*/0,
        GIM_CheckPointerToAny, /*MI*/0, /*Op*/1, /*SizeInBits*/0,
        GIM_CheckComplexPattern, /*MI*/0, /*Op*/1, /*Renderer*/GIMT_Encode2(0), GIMT_Encode2(GICP_gi_flat_offset),
        // (atomic_load_xor:{ *:[i32] } (FlatOffset:{ *:[iPTR] } i64:{ *:[i64] }:$vaddr, i32:{ *:[i32] }:$offset), i32:{ *:[i32] }:$data)<<P:Predicate_atomic_load_xor_global_noret_32>>  =>  (FLAT_ATOMIC_XOR VReg_64:{ *:[i64] }:$vaddr, anonymous_15037:{ *:[i32] }:$data, ?:{ *:[i32] }:$offset)
        GIR_BuildMI, /*InsnID*/0, /*Opcode*/GIMT_Encode2(AMDGPU::FLAT_ATOMIC_XOR),
        GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/0, // vaddr
        GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/2, // data
        GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/1, // offset
        GIR_AddImm8, /*InsnID*/0, /*Imm*/0,
        GIR_MergeMemOperands, /*InsnID*/0, /*NumInsns*/1, /*MergeInsnID's*/0,
        GIR_ConstrainSelectedInstOperands, /*InsnID*/0,
        GIR_EraseFromParent, /*InsnID*/0,
        // GIR_Coverage, 2904,
        GIR_Done,
      // Label 2679: @174255
      GIM_Try, /*On fail goto*//*Label 2680*/ GIMT_Encode4(174321), // Rule ID 2851 //
        GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasFlatAddressSpace),
        GIM_CheckMemoryAddressSpace, /*MI*/0, /*MMO*/0, /*NumAddrSpace*/4, /*AddrSpace*/0, /*AddrSpace*/1, /*AddrSpace*/4, /*AddrSpace*/6,
        GIM_CheckRegBankForClass, /*MI*/0, /*Op*/0, /*RC*/GIMT_Encode2(AMDGPU::AV_32RegClassID),
        GIM_CheckPointerToAny, /*MI*/0, /*Op*/1, /*SizeInBits*/0,
        GIM_CheckComplexPattern, /*MI*/0, /*Op*/1, /*Renderer*/GIMT_Encode2(0), GIMT_Encode2(GICP_gi_flat_offset),
        // (atomic_load_xor:{ *:[i32] } (FlatOffset:{ *:[iPTR] } i64:{ *:[i64] }:$vaddr, i32:{ *:[i32] }:$offset), i32:{ *:[i32] }:$data)<<P:Predicate_atomic_load_xor_flat_32>>  =>  (FLAT_ATOMIC_XOR_RTN:{ *:[i32] } VReg_64:{ *:[i64] }:$vaddr, anonymous_15037:{ *:[i32] }:$data, ?:{ *:[i32] }:$offset)
        GIR_BuildMI, /*InsnID*/0, /*Opcode*/GIMT_Encode2(AMDGPU::FLAT_ATOMIC_XOR_RTN),
        GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/0, // DstI[vdst]
        GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/0, // vaddr
        GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/2, // data
        GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/1, // offset
        GIR_AddImm8, /*InsnID*/0, /*Imm*/1,
        GIR_MergeMemOperands, /*InsnID*/0, /*NumInsns*/1, /*MergeInsnID's*/0,
        GIR_ConstrainSelectedInstOperands, /*InsnID*/0,
        GIR_EraseFromParent, /*InsnID*/0,
        // GIR_Coverage, 2851,
        GIR_Done,
      // Label 2680: @174321
      GIM_Try, /*On fail goto*//*Label 2681*/ GIMT_Encode4(174386), // Rule ID 2903 //
        GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasFlatAddressSpace),
        GIM_CheckMemoryAddressSpace, /*MI*/0, /*MMO*/0, /*NumAddrSpace*/3, /*AddrSpace*/1, /*AddrSpace*/4, /*AddrSpace*/6,
        GIM_CheckRegBankForClass, /*MI*/0, /*Op*/0, /*RC*/GIMT_Encode2(AMDGPU::AV_32RegClassID),
        GIM_CheckPointerToAny, /*MI*/0, /*Op*/1, /*SizeInBits*/0,
        GIM_CheckComplexPattern, /*MI*/0, /*Op*/1, /*Renderer*/GIMT_Encode2(0), GIMT_Encode2(GICP_gi_flat_offset),
        // (atomic_load_xor:{ *:[i32] } (FlatOffset:{ *:[iPTR] } i64:{ *:[i64] }:$vaddr, i32:{ *:[i32] }:$offset), i32:{ *:[i32] }:$data)<<P:Predicate_atomic_load_xor_global_32>>  =>  (FLAT_ATOMIC_XOR_RTN:{ *:[i32] } VReg_64:{ *:[i64] }:$vaddr, anonymous_15037:{ *:[i32] }:$data, ?:{ *:[i32] }:$offset)
        GIR_BuildMI, /*InsnID*/0, /*Opcode*/GIMT_Encode2(AMDGPU::FLAT_ATOMIC_XOR_RTN),
        GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/0, // DstI[vdst]
        GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/0, // vaddr
        GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/2, // data
        GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/1, // offset
        GIR_AddImm8, /*InsnID*/0, /*Imm*/1,
        GIR_MergeMemOperands, /*InsnID*/0, /*NumInsns*/1, /*MergeInsnID's*/0,
        GIR_ConstrainSelectedInstOperands, /*InsnID*/0,
        GIR_EraseFromParent, /*InsnID*/0,
        // GIR_Coverage, 2903,
        GIR_Done,
      // Label 2681: @174386
      GIM_Reject,
    // Label 2659: @174387
    GIM_Reject,
    // Label 2657: @174388
    GIM_Try, /*On fail goto*//*Label 2682*/ GIMT_Encode4(175799),
      GIM_CheckType, /*MI*/0, /*Op*/2, /*Type*/GILLT_s64,
      GIM_Try, /*On fail goto*//*Label 2683*/ GIMT_Encode4(174465), // Rule ID 4678 //
        GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasUnrestrictedSOffset),
        GIM_CheckMemoryAddressSpace, /*MI*/0, /*MMO*/0, /*NumAddrSpace*/3, /*AddrSpace*/1, /*AddrSpace*/4, /*AddrSpace*/6,
        GIM_CheckHasNoUse, /*MI*/0,
        GIM_CheckPointerToAny, /*MI*/0, /*Op*/1, /*SizeInBits*/0,
        GIM_CheckComplexPattern, /*MI*/0, /*Op*/1, /*Renderer*/GIMT_Encode2(0), GIMT_Encode2(GICP_gi_mubuf_addr64),
        // (atomic_load_xor:{ *:[i64] } (MUBUFAddr64:{ *:[iPTR] } v4i32:{ *:[v4i32] }:$srsrc, i64:{ *:[i64] }:$vaddr, i32:{ *:[i32] }:$soffset, i32:{ *:[i32] }:$offset), i64:{ *:[i64] }:$vdata_in)<<P:Predicate_atomic_load_xor_global_noret_64>>  =>  (BUFFER_ATOMIC_XOR_X2_ADDR64 anonymous_15036:{ *:[i64] }:$vdata_in, VReg_64:{ *:[i64] }:$vaddr, SReg_128:{ *:[v4i32] }:$srsrc, SCSrc_b32:{ *:[i32] }:$soffset, offset:{ *:[i32] }:$offset)
        GIR_BuildMI, /*InsnID*/0, /*Opcode*/GIMT_Encode2(AMDGPU::BUFFER_ATOMIC_XOR_X2_ADDR64),
        GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/2, // vdata_in
        GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/1, // vaddr
        GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/0, // srsrc
        GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/2, // soffset
        GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/3, // offset
        GIR_AddImm8, /*InsnID*/0, /*Imm*/0,
        GIR_MergeMemOperands, /*InsnID*/0, /*NumInsns*/1, /*MergeInsnID's*/0,
        GIR_ConstrainSelectedInstOperands, /*InsnID*/0,
        GIR_EraseFromParent, /*InsnID*/0,
        // GIR_Coverage, 4678,
        GIR_Done,
      // Label 2683: @174465
      GIM_Try, /*On fail goto*//*Label 2684*/ GIMT_Encode4(174530), // Rule ID 4682 //
        GIM_CheckMemoryAddressSpace, /*MI*/0, /*MMO*/0, /*NumAddrSpace*/3, /*AddrSpace*/1, /*AddrSpace*/4, /*AddrSpace*/6,
        GIM_CheckHasNoUse, /*MI*/0,
        GIM_CheckPointerToAny, /*MI*/0, /*Op*/1, /*SizeInBits*/0,
        GIM_CheckComplexPattern, /*MI*/0, /*Op*/1, /*Renderer*/GIMT_Encode2(0), GIMT_Encode2(GICP_gi_mubuf_addr64),
        // (atomic_load_xor:{ *:[i64] } (MUBUFAddr64:{ *:[iPTR] } v4i32:{ *:[v4i32] }:$srsrc, i64:{ *:[i64] }:$vaddr, i32:{ *:[i32] }:$soffset, i32:{ *:[i32] }:$offset), i64:{ *:[i64] }:$vdata_in)<<P:Predicate_atomic_load_xor_global_noret_64>>  =>  (BUFFER_ATOMIC_XOR_X2_VBUFFER_ADDR64 anonymous_15036:{ *:[i64] }:$vdata_in, VReg_64:{ *:[i64] }:$vaddr, SReg_128:{ *:[v4i32] }:$srsrc, SCSrc_b32:{ *:[i32] }:$soffset, offset:{ *:[i32] }:$offset)
        GIR_BuildMI, /*InsnID*/0, /*Opcode*/GIMT_Encode2(AMDGPU::BUFFER_ATOMIC_XOR_X2_VBUFFER_ADDR64),
        GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/2, // vdata_in
        GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/1, // vaddr
        GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/0, // srsrc
        GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/2, // soffset
        GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/3, // offset
        GIR_AddImm8, /*InsnID*/0, /*Imm*/0,
        GIR_MergeMemOperands, /*InsnID*/0, /*NumInsns*/1, /*MergeInsnID's*/0,
        GIR_ConstrainSelectedInstOperands, /*InsnID*/0,
        GIR_EraseFromParent, /*InsnID*/0,
        // GIR_Coverage, 4682,
        GIR_Done,
      // Label 2684: @174530
      GIM_Try, /*On fail goto*//*Label 2685*/ GIMT_Encode4(174605), // Rule ID 4676 //
        GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasUnrestrictedSOffset),
        GIM_CheckMemoryAddressSpace, /*MI*/0, /*MMO*/0, /*NumAddrSpace*/3, /*AddrSpace*/1, /*AddrSpace*/4, /*AddrSpace*/6,
        GIM_CheckRegBankForClass, /*MI*/0, /*Op*/0, /*RC*/GIMT_Encode2(AMDGPU::AV_64RegClassID),
        GIM_CheckPointerToAny, /*MI*/0, /*Op*/1, /*SizeInBits*/0,
        GIM_CheckComplexPattern, /*MI*/0, /*Op*/1, /*Renderer*/GIMT_Encode2(0), GIMT_Encode2(GICP_gi_mubuf_addr64),
        // (atomic_load_xor:{ *:[i64] } (MUBUFAddr64:{ *:[iPTR] } v4i32:{ *:[v4i32] }:$srsrc, i64:{ *:[i64] }:$vaddr, i32:{ *:[i32] }:$soffset, i32:{ *:[i32] }:$offset), i64:{ *:[i64] }:$vdata_in)<<P:Predicate_atomic_load_xor_global_64>>  =>  (BUFFER_ATOMIC_XOR_X2_ADDR64_RTN:{ *:[i64] } anonymous_15036:{ *:[i64] }:$vdata_in, VReg_64:{ *:[i64] }:$vaddr, SReg_128:{ *:[v4i32] }:$srsrc, SCSrc_b32:{ *:[i32] }:$soffset, offset:{ *:[i32] }:$offset)
        GIR_BuildMI, /*InsnID*/0, /*Opcode*/GIMT_Encode2(AMDGPU::BUFFER_ATOMIC_XOR_X2_ADDR64_RTN),
        GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/0, // DstI[vdata]
        GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/2, // vdata_in
        GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/1, // vaddr
        GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/0, // srsrc
        GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/2, // soffset
        GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/3, // offset
        GIR_AddImm8, /*InsnID*/0, /*Imm*/1,
        GIR_MergeMemOperands, /*InsnID*/0, /*NumInsns*/1, /*MergeInsnID's*/0,
        GIR_ConstrainSelectedInstOperands, /*InsnID*/0,
        GIR_EraseFromParent, /*InsnID*/0,
        // GIR_Coverage, 4676,
        GIR_Done,
      // Label 2685: @174605
      GIM_Try, /*On fail goto*//*Label 2686*/ GIMT_Encode4(174677), // Rule ID 4680 //
        GIM_CheckMemoryAddressSpace, /*MI*/0, /*MMO*/0, /*NumAddrSpace*/3, /*AddrSpace*/1, /*AddrSpace*/4, /*AddrSpace*/6,
        GIM_CheckRegBankForClass, /*MI*/0, /*Op*/0, /*RC*/GIMT_Encode2(AMDGPU::AV_64RegClassID),
        GIM_CheckPointerToAny, /*MI*/0, /*Op*/1, /*SizeInBits*/0,
        GIM_CheckComplexPattern, /*MI*/0, /*Op*/1, /*Renderer*/GIMT_Encode2(0), GIMT_Encode2(GICP_gi_mubuf_addr64),
        // (atomic_load_xor:{ *:[i64] } (MUBUFAddr64:{ *:[iPTR] } v4i32:{ *:[v4i32] }:$srsrc, i64:{ *:[i64] }:$vaddr, i32:{ *:[i32] }:$soffset, i32:{ *:[i32] }:$offset), i64:{ *:[i64] }:$vdata_in)<<P:Predicate_atomic_load_xor_global_64>>  =>  (BUFFER_ATOMIC_XOR_X2_VBUFFER_ADDR64_RTN:{ *:[i64] } anonymous_15036:{ *:[i64] }:$vdata_in, VReg_64:{ *:[i64] }:$vaddr, SReg_128:{ *:[v4i32] }:$srsrc, SCSrc_b32:{ *:[i32] }:$soffset, offset:{ *:[i32] }:$offset)
        GIR_BuildMI, /*InsnID*/0, /*Opcode*/GIMT_Encode2(AMDGPU::BUFFER_ATOMIC_XOR_X2_VBUFFER_ADDR64_RTN),
        GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/0, // DstI[vdata]
        GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/2, // vdata_in
        GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/1, // vaddr
        GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/0, // srsrc
        GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/2, // soffset
        GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/3, // offset
        GIR_AddImm8, /*InsnID*/0, /*Imm*/1,
        GIR_MergeMemOperands, /*InsnID*/0, /*NumInsns*/1, /*MergeInsnID's*/0,
        GIR_ConstrainSelectedInstOperands, /*InsnID*/0,
        GIR_EraseFromParent, /*InsnID*/0,
        // GIR_Coverage, 4680,
        GIR_Done,
      // Label 2686: @174677
      GIM_Try, /*On fail goto*//*Label 2687*/ GIMT_Encode4(174740), // Rule ID 4677 //
        GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasUnrestrictedSOffset),
        GIM_CheckMemoryAddressSpace, /*MI*/0, /*MMO*/0, /*NumAddrSpace*/3, /*AddrSpace*/1, /*AddrSpace*/4, /*AddrSpace*/6,
        GIM_CheckHasNoUse, /*MI*/0,
        GIM_CheckPointerToAny, /*MI*/0, /*Op*/1, /*SizeInBits*/0,
        GIM_CheckComplexPattern, /*MI*/0, /*Op*/1, /*Renderer*/GIMT_Encode2(0), GIMT_Encode2(GICP_gi_mubuf_offset),
        // (atomic_load_xor:{ *:[i64] } (MUBUFOffset:{ *:[iPTR] } v4i32:{ *:[v4i32] }:$srsrc, i32:{ *:[i32] }:$soffset, i32:{ *:[i32] }:$offset), i64:{ *:[i64] }:$vdata_in)<<P:Predicate_atomic_load_xor_global_noret_64>>  =>  (BUFFER_ATOMIC_XOR_X2_OFFSET anonymous_15036:{ *:[i64] }:$vdata_in, SReg_128:{ *:[v4i32] }:$srsrc, SCSrc_b32:{ *:[i32] }:$soffset, offset:{ *:[i32] }:$offset)
        GIR_BuildMI, /*InsnID*/0, /*Opcode*/GIMT_Encode2(AMDGPU::BUFFER_ATOMIC_XOR_X2_OFFSET),
        GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/2, // vdata_in
        GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/0, // srsrc
        GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/1, // soffset
        GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/2, // offset
        GIR_AddImm8, /*InsnID*/0, /*Imm*/0,
        GIR_MergeMemOperands, /*InsnID*/0, /*NumInsns*/1, /*MergeInsnID's*/0,
        GIR_ConstrainSelectedInstOperands, /*InsnID*/0,
        GIR_EraseFromParent, /*InsnID*/0,
        // GIR_Coverage, 4677,
        GIR_Done,
      // Label 2687: @174740
      GIM_Try, /*On fail goto*//*Label 2688*/ GIMT_Encode4(174800), // Rule ID 4681 //
        GIM_CheckMemoryAddressSpace, /*MI*/0, /*MMO*/0, /*NumAddrSpace*/3, /*AddrSpace*/1, /*AddrSpace*/4, /*AddrSpace*/6,
        GIM_CheckHasNoUse, /*MI*/0,
        GIM_CheckPointerToAny, /*MI*/0, /*Op*/1, /*SizeInBits*/0,
        GIM_CheckComplexPattern, /*MI*/0, /*Op*/1, /*Renderer*/GIMT_Encode2(0), GIMT_Encode2(GICP_gi_mubuf_offset),
        // (atomic_load_xor:{ *:[i64] } (MUBUFOffset:{ *:[iPTR] } v4i32:{ *:[v4i32] }:$srsrc, i32:{ *:[i32] }:$soffset, i32:{ *:[i32] }:$offset), i64:{ *:[i64] }:$vdata_in)<<P:Predicate_atomic_load_xor_global_noret_64>>  =>  (BUFFER_ATOMIC_XOR_X2_VBUFFER_OFFSET anonymous_15036:{ *:[i64] }:$vdata_in, SReg_128:{ *:[v4i32] }:$srsrc, SCSrc_b32:{ *:[i32] }:$soffset, offset:{ *:[i32] }:$offset)
        GIR_BuildMI, /*InsnID*/0, /*Opcode*/GIMT_Encode2(AMDGPU::BUFFER_ATOMIC_XOR_X2_VBUFFER_OFFSET),
        GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/2, // vdata_in
        GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/0, // srsrc
        GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/1, // soffset
        GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/2, // offset
        GIR_AddImm8, /*InsnID*/0, /*Imm*/0,
        GIR_MergeMemOperands, /*InsnID*/0, /*NumInsns*/1, /*MergeInsnID's*/0,
        GIR_ConstrainSelectedInstOperands, /*InsnID*/0,
        GIR_EraseFromParent, /*InsnID*/0,
        // GIR_Coverage, 4681,
        GIR_Done,
      // Label 2688: @174800
      GIM_Try, /*On fail goto*//*Label 2689*/ GIMT_Encode4(174870), // Rule ID 4675 //
        GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasUnrestrictedSOffset),
        GIM_CheckMemoryAddressSpace, /*MI*/0, /*MMO*/0, /*NumAddrSpace*/3, /*AddrSpace*/1, /*AddrSpace*/4, /*AddrSpace*/6,
        GIM_CheckRegBankForClass, /*MI*/0, /*Op*/0, /*RC*/GIMT_Encode2(AMDGPU::AV_64RegClassID),
        GIM_CheckPointerToAny, /*MI*/0, /*Op*/1, /*SizeInBits*/0,
        GIM_CheckComplexPattern, /*MI*/0, /*Op*/1, /*Renderer*/GIMT_Encode2(0), GIMT_Encode2(GICP_gi_mubuf_offset),
        // (atomic_load_xor:{ *:[i64] } (MUBUFOffset:{ *:[iPTR] } v4i32:{ *:[v4i32] }:$srsrc, i32:{ *:[i32] }:$soffset, i32:{ *:[i32] }:$offset), i64:{ *:[i64] }:$vdata_in)<<P:Predicate_atomic_load_xor_global_64>>  =>  (BUFFER_ATOMIC_XOR_X2_OFFSET_RTN:{ *:[i64] } anonymous_15036:{ *:[i64] }:$vdata_in, SReg_128:{ *:[v4i32] }:$srsrc, SCSrc_b32:{ *:[i32] }:$soffset, offset:{ *:[i32] }:$offset)
        GIR_BuildMI, /*InsnID*/0, /*Opcode*/GIMT_Encode2(AMDGPU::BUFFER_ATOMIC_XOR_X2_OFFSET_RTN),
        GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/0, // DstI[vdata]
        GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/2, // vdata_in
        GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/0, // srsrc
        GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/1, // soffset
        GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/2, // offset
        GIR_AddImm8, /*InsnID*/0, /*Imm*/1,
        GIR_MergeMemOperands, /*InsnID*/0, /*NumInsns*/1, /*MergeInsnID's*/0,
        GIR_ConstrainSelectedInstOperands, /*InsnID*/0,
        GIR_EraseFromParent, /*InsnID*/0,
        // GIR_Coverage, 4675,
        GIR_Done,
      // Label 2689: @174870
      GIM_Try, /*On fail goto*//*Label 2690*/ GIMT_Encode4(174937), // Rule ID 4679 //
        GIM_CheckMemoryAddressSpace, /*MI*/0, /*MMO*/0, /*NumAddrSpace*/3, /*AddrSpace*/1, /*AddrSpace*/4, /*AddrSpace*/6,
        GIM_CheckRegBankForClass, /*MI*/0, /*Op*/0, /*RC*/GIMT_Encode2(AMDGPU::AV_64RegClassID),
        GIM_CheckPointerToAny, /*MI*/0, /*Op*/1, /*SizeInBits*/0,
        GIM_CheckComplexPattern, /*MI*/0, /*Op*/1, /*Renderer*/GIMT_Encode2(0), GIMT_Encode2(GICP_gi_mubuf_offset),
        // (atomic_load_xor:{ *:[i64] } (MUBUFOffset:{ *:[iPTR] } v4i32:{ *:[v4i32] }:$srsrc, i32:{ *:[i32] }:$soffset, i32:{ *:[i32] }:$offset), i64:{ *:[i64] }:$vdata_in)<<P:Predicate_atomic_load_xor_global_64>>  =>  (BUFFER_ATOMIC_XOR_X2_VBUFFER_OFFSET_RTN:{ *:[i64] } anonymous_15036:{ *:[i64] }:$vdata_in, SReg_128:{ *:[v4i32] }:$srsrc, SCSrc_b32:{ *:[i32] }:$soffset, offset:{ *:[i32] }:$offset)
        GIR_BuildMI, /*InsnID*/0, /*Opcode*/GIMT_Encode2(AMDGPU::BUFFER_ATOMIC_XOR_X2_VBUFFER_OFFSET_RTN),
        GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/0, // DstI[vdata]
        GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/2, // vdata_in
        GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/0, // srsrc
        GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/1, // soffset
        GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/2, // offset
        GIR_AddImm8, /*InsnID*/0, /*Imm*/1,
        GIR_MergeMemOperands, /*InsnID*/0, /*NumInsns*/1, /*MergeInsnID's*/0,
        GIR_ConstrainSelectedInstOperands, /*InsnID*/0,
        GIR_EraseFromParent, /*InsnID*/0,
        // GIR_Coverage, 4679,
        GIR_Done,
      // Label 2690: @174937
      GIM_Try, /*On fail goto*//*Label 2691*/ GIMT_Encode4(174993), // Rule ID 7028 //
        GIM_CheckFeatures, GIMT_Encode2(GIFBS_LDSRequiresM0Init),
        GIM_CheckMemoryAddressSpace, /*MI*/0, /*MMO*/0, /*NumAddrSpace*/1, /*AddrSpace*/3,
        GIM_CheckHasNoUse, /*MI*/0,
        GIM_CheckPointerToAny, /*MI*/0, /*Op*/1, /*SizeInBits*/0,
        GIM_CheckComplexPattern, /*MI*/0, /*Op*/1, /*Renderer*/GIMT_Encode2(0), GIMT_Encode2(GICP_gi_ds_1addr_1offset),
        // (atomic_load_xor_glue:{ *:[i64] } (DS1Addr1Offset:{ *:[iPTR] } i32:{ *:[i32] }:$ptr, i32:{ *:[i32] }:$offset), i64:{ *:[i64] }:$value)<<P:Predicate_atomic_load_xor_local_m0_noret_64>>  =>  (DS_XOR_B64 ?:{ *:[i32] }:$ptr, anonymous_15036:{ *:[i64] }:$value, offset:{ *:[i32] }:$offset, 0:{ *:[i1] })
        GIR_BuildMI, /*InsnID*/0, /*Opcode*/GIMT_Encode2(AMDGPU::DS_XOR_B64),
        GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/0, // ptr
        GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/2, // value
        GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/1, // offset
        GIR_AddImm8, /*InsnID*/0, /*Imm*/0,
        GIR_MergeMemOperands, /*InsnID*/0, /*NumInsns*/1, /*MergeInsnID's*/0,
        GIR_ConstrainSelectedInstOperands, /*InsnID*/0,
        GIR_EraseFromParent, /*InsnID*/0,
        // GIR_Coverage, 7028,
        GIR_Done,
      // Label 2691: @174993
      GIM_Try, /*On fail goto*//*Label 2692*/ GIMT_Encode4(175049), // Rule ID 7030 //
        GIM_CheckFeatures, GIMT_Encode2(GIFBS_NotLDSRequiresM0Init),
        GIM_CheckMemoryAddressSpace, /*MI*/0, /*MMO*/0, /*NumAddrSpace*/1, /*AddrSpace*/3,
        GIM_CheckHasNoUse, /*MI*/0,
        GIM_CheckPointerToAny, /*MI*/0, /*Op*/1, /*SizeInBits*/0,
        GIM_CheckComplexPattern, /*MI*/0, /*Op*/1, /*Renderer*/GIMT_Encode2(0), GIMT_Encode2(GICP_gi_ds_1addr_1offset),
        // (atomic_load_xor:{ *:[i64] } (DS1Addr1Offset:{ *:[iPTR] } i32:{ *:[i32] }:$ptr, i32:{ *:[i32] }:$offset), i64:{ *:[i64] }:$value)<<P:Predicate_atomic_load_xor_local_noret_64>>  =>  (DS_XOR_B64_gfx9 ?:{ *:[i32] }:$ptr, anonymous_15036:{ *:[i64] }:$value, offset:{ *:[i32] }:$offset, 0:{ *:[i1] })
        GIR_BuildMI, /*InsnID*/0, /*Opcode*/GIMT_Encode2(AMDGPU::DS_XOR_B64_gfx9),
        GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/0, // ptr
        GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/2, // value
        GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/1, // offset
        GIR_AddImm8, /*InsnID*/0, /*Imm*/0,
        GIR_MergeMemOperands, /*InsnID*/0, /*NumInsns*/1, /*MergeInsnID's*/0,
        GIR_ConstrainSelectedInstOperands, /*InsnID*/0,
        GIR_EraseFromParent, /*InsnID*/0,
        // GIR_Coverage, 7030,
        GIR_Done,
      // Label 2692: @175049
      GIM_Try, /*On fail goto*//*Label 2693*/ GIMT_Encode4(175105), // Rule ID 7032 //
        GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasGDS),
        GIM_CheckMemoryAddressSpace, /*MI*/0, /*MMO*/0, /*NumAddrSpace*/1, /*AddrSpace*/2,
        GIM_CheckHasNoUse, /*MI*/0,
        GIM_CheckPointerToAny, /*MI*/0, /*Op*/1, /*SizeInBits*/0,
        GIM_CheckComplexPattern, /*MI*/0, /*Op*/1, /*Renderer*/GIMT_Encode2(0), GIMT_Encode2(GICP_gi_ds_1addr_1offset),
        // (atomic_load_xor_glue:{ *:[i64] } (DS1Addr1Offset:{ *:[iPTR] } i32:{ *:[i32] }:$ptr, i32:{ *:[i32] }:$offset), i64:{ *:[i64] }:$value)<<P:Predicate_atomic_load_xor_region_m0_noret_64>>  =>  (DS_XOR_B64 ?:{ *:[i32] }:$ptr, anonymous_15036:{ *:[i64] }:$value, offset:{ *:[i32] }:$offset, 1:{ *:[i1] })
        GIR_BuildMI, /*InsnID*/0, /*Opcode*/GIMT_Encode2(AMDGPU::DS_XOR_B64),
        GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/0, // ptr
        GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/2, // value
        GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/1, // offset
        GIR_AddImm8, /*InsnID*/0, /*Imm*/1,
        GIR_MergeMemOperands, /*InsnID*/0, /*NumInsns*/1, /*MergeInsnID's*/0,
        GIR_ConstrainSelectedInstOperands, /*InsnID*/0,
        GIR_EraseFromParent, /*InsnID*/0,
        // GIR_Coverage, 7032,
        GIR_Done,
      // Label 2693: @175105
      GIM_Try, /*On fail goto*//*Label 2694*/ GIMT_Encode4(175168), // Rule ID 7027 //
        GIM_CheckFeatures, GIMT_Encode2(GIFBS_LDSRequiresM0Init),
        GIM_CheckMemoryAddressSpace, /*MI*/0, /*MMO*/0, /*NumAddrSpace*/1, /*AddrSpace*/3,
        GIM_CheckRegBankForClass, /*MI*/0, /*Op*/0, /*RC*/GIMT_Encode2(AMDGPU::AV_64RegClassID),
        GIM_CheckPointerToAny, /*MI*/0, /*Op*/1, /*SizeInBits*/0,
        GIM_CheckComplexPattern, /*MI*/0, /*Op*/1, /*Renderer*/GIMT_Encode2(0), GIMT_Encode2(GICP_gi_ds_1addr_1offset),
        // (atomic_load_xor_glue:{ *:[i64] } (DS1Addr1Offset:{ *:[iPTR] } i32:{ *:[i32] }:$ptr, i32:{ *:[i32] }:$offset), i64:{ *:[i64] }:$value)<<P:Predicate_atomic_load_xor_local_m0_64>>  =>  (DS_XOR_RTN_B64:{ *:[i64] } ?:{ *:[i32] }:$ptr, anonymous_15036:{ *:[i64] }:$value, offset:{ *:[i32] }:$offset, 0:{ *:[i1] })
        GIR_BuildMI, /*InsnID*/0, /*Opcode*/GIMT_Encode2(AMDGPU::DS_XOR_RTN_B64),
        GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/0, // DstI[vdst]
        GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/0, // ptr
        GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/2, // value
        GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/1, // offset
        GIR_AddImm8, /*InsnID*/0, /*Imm*/0,
        GIR_MergeMemOperands, /*InsnID*/0, /*NumInsns*/1, /*MergeInsnID's*/0,
        GIR_ConstrainSelectedInstOperands, /*InsnID*/0,
        GIR_EraseFromParent, /*InsnID*/0,
        // GIR_Coverage, 7027,
        GIR_Done,
      // Label 2694: @175168
      GIM_Try, /*On fail goto*//*Label 2695*/ GIMT_Encode4(175231), // Rule ID 7029 //
        GIM_CheckFeatures, GIMT_Encode2(GIFBS_NotLDSRequiresM0Init),
        GIM_CheckMemoryAddressSpace, /*MI*/0, /*MMO*/0, /*NumAddrSpace*/1, /*AddrSpace*/3,
        GIM_CheckRegBankForClass, /*MI*/0, /*Op*/0, /*RC*/GIMT_Encode2(AMDGPU::AV_64RegClassID),
        GIM_CheckPointerToAny, /*MI*/0, /*Op*/1, /*SizeInBits*/0,
        GIM_CheckComplexPattern, /*MI*/0, /*Op*/1, /*Renderer*/GIMT_Encode2(0), GIMT_Encode2(GICP_gi_ds_1addr_1offset),
        // (atomic_load_xor:{ *:[i64] } (DS1Addr1Offset:{ *:[iPTR] } i32:{ *:[i32] }:$ptr, i32:{ *:[i32] }:$offset), i64:{ *:[i64] }:$value)<<P:Predicate_atomic_load_xor_local_64>>  =>  (DS_XOR_RTN_B64_gfx9:{ *:[i64] } ?:{ *:[i32] }:$ptr, anonymous_15036:{ *:[i64] }:$value, offset:{ *:[i32] }:$offset, 0:{ *:[i1] })
        GIR_BuildMI, /*InsnID*/0, /*Opcode*/GIMT_Encode2(AMDGPU::DS_XOR_RTN_B64_gfx9),
        GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/0, // DstI[vdst]
        GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/0, // ptr
        GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/2, // value
        GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/1, // offset
        GIR_AddImm8, /*InsnID*/0, /*Imm*/0,
        GIR_MergeMemOperands, /*InsnID*/0, /*NumInsns*/1, /*MergeInsnID's*/0,
        GIR_ConstrainSelectedInstOperands, /*InsnID*/0,
        GIR_EraseFromParent, /*InsnID*/0,
        // GIR_Coverage, 7029,
        GIR_Done,
      // Label 2695: @175231
      GIM_Try, /*On fail goto*//*Label 2696*/ GIMT_Encode4(175294), // Rule ID 7031 //
        GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasGDS),
        GIM_CheckMemoryAddressSpace, /*MI*/0, /*MMO*/0, /*NumAddrSpace*/1, /*AddrSpace*/2,
        GIM_CheckRegBankForClass, /*MI*/0, /*Op*/0, /*RC*/GIMT_Encode2(AMDGPU::AV_64RegClassID),
        GIM_CheckPointerToAny, /*MI*/0, /*Op*/1, /*SizeInBits*/0,
        GIM_CheckComplexPattern, /*MI*/0, /*Op*/1, /*Renderer*/GIMT_Encode2(0), GIMT_Encode2(GICP_gi_ds_1addr_1offset),
        // (atomic_load_xor_glue:{ *:[i64] } (DS1Addr1Offset:{ *:[iPTR] } i32:{ *:[i32] }:$ptr, i32:{ *:[i32] }:$offset), i64:{ *:[i64] }:$value)<<P:Predicate_atomic_load_xor_region_m0_64>>  =>  (DS_XOR_RTN_B64:{ *:[i64] } ?:{ *:[i32] }:$ptr, anonymous_15036:{ *:[i64] }:$value, offset:{ *:[i32] }:$offset, 1:{ *:[i1] })
        GIR_BuildMI, /*InsnID*/0, /*Opcode*/GIMT_Encode2(AMDGPU::DS_XOR_RTN_B64),
        GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/0, // DstI[vdst]
        GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/0, // ptr
        GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/2, // value
        GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/1, // offset
        GIR_AddImm8, /*InsnID*/0, /*Imm*/1,
        GIR_MergeMemOperands, /*InsnID*/0, /*NumInsns*/1, /*MergeInsnID's*/0,
        GIR_ConstrainSelectedInstOperands, /*InsnID*/0,
        GIR_EraseFromParent, /*InsnID*/0,
        // GIR_Coverage, 7031,
        GIR_Done,
      // Label 2696: @175294
      GIM_Try, /*On fail goto*//*Label 2697*/ GIMT_Encode4(175357), // Rule ID 3251 //
        GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasFlatGlobalInsts),
        GIM_CheckMemoryAddressSpace, /*MI*/0, /*MMO*/0, /*NumAddrSpace*/3, /*AddrSpace*/1, /*AddrSpace*/4, /*AddrSpace*/6,
        GIM_CheckHasNoUse, /*MI*/0,
        GIM_CheckPointerToAny, /*MI*/0, /*Op*/1, /*SizeInBits*/0,
        GIM_CheckComplexPattern, /*MI*/0, /*Op*/1, /*Renderer*/GIMT_Encode2(0), GIMT_Encode2(GICP_gi_global_saddr),
        // (atomic_load_xor:{ *:[i64] } (GlobalSAddr:{ *:[iPTR] } SReg_64:{ *:[i64] }:$saddr, VGPR_32:{ *:[i32] }:$voffset, i32:{ *:[i32] }:$offset), i64:{ *:[i64] }:$data)<<P:Predicate_atomic_load_xor_global_noret_64>>  =>  (GLOBAL_ATOMIC_XOR_X2_SADDR ?:{ *:[i32] }:$voffset, anonymous_15036:{ *:[i64] }:$data, ?:{ *:[i64] }:$saddr, ?:{ *:[i32] }:$offset)
        GIR_BuildMI, /*InsnID*/0, /*Opcode*/GIMT_Encode2(AMDGPU::GLOBAL_ATOMIC_XOR_X2_SADDR),
        GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/1, // voffset
        GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/2, // data
        GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/0, // saddr
        GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/2, // offset
        GIR_AddImm8, /*InsnID*/0, /*Imm*/0,
        GIR_MergeMemOperands, /*InsnID*/0, /*NumInsns*/1, /*MergeInsnID's*/0,
        GIR_ConstrainSelectedInstOperands, /*InsnID*/0,
        GIR_EraseFromParent, /*InsnID*/0,
        // GIR_Coverage, 3251,
        GIR_Done,
      // Label 2697: @175357
      GIM_Try, /*On fail goto*//*Label 2698*/ GIMT_Encode4(175427), // Rule ID 3253 //
        GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasFlatGlobalInsts),
        GIM_CheckMemoryAddressSpace, /*MI*/0, /*MMO*/0, /*NumAddrSpace*/3, /*AddrSpace*/1, /*AddrSpace*/4, /*AddrSpace*/6,
        GIM_CheckRegBankForClass, /*MI*/0, /*Op*/0, /*RC*/GIMT_Encode2(AMDGPU::AV_64RegClassID),
        GIM_CheckPointerToAny, /*MI*/0, /*Op*/1, /*SizeInBits*/0,
        GIM_CheckComplexPattern, /*MI*/0, /*Op*/1, /*Renderer*/GIMT_Encode2(0), GIMT_Encode2(GICP_gi_global_saddr),
        // (atomic_load_xor:{ *:[i64] } (GlobalSAddr:{ *:[iPTR] } SReg_64:{ *:[i64] }:$saddr, VGPR_32:{ *:[i32] }:$voffset, i32:{ *:[i32] }:$offset), i64:{ *:[i64] }:$data)<<P:Predicate_atomic_load_xor_global_64>>  =>  (GLOBAL_ATOMIC_XOR_X2_SADDR_RTN:{ *:[i64] } ?:{ *:[i32] }:$voffset, anonymous_15036:{ *:[i64] }:$data, ?:{ *:[i64] }:$saddr, ?:{ *:[i32] }:$offset)
        GIR_BuildMI, /*InsnID*/0, /*Opcode*/GIMT_Encode2(AMDGPU::GLOBAL_ATOMIC_XOR_X2_SADDR_RTN),
        GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/0, // DstI[vdst]
        GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/1, // voffset
        GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/2, // data
        GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/0, // saddr
        GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/2, // offset
        GIR_AddImm8, /*InsnID*/0, /*Imm*/1,
        GIR_MergeMemOperands, /*InsnID*/0, /*NumInsns*/1, /*MergeInsnID's*/0,
        GIR_ConstrainSelectedInstOperands, /*InsnID*/0,
        GIR_EraseFromParent, /*InsnID*/0,
        // GIR_Coverage, 3253,
        GIR_Done,
      // Label 2698: @175427
      GIM_Try, /*On fail goto*//*Label 2699*/ GIMT_Encode4(175485), // Rule ID 3250 //
        GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasFlatGlobalInsts),
        GIM_CheckMemoryAddressSpace, /*MI*/0, /*MMO*/0, /*NumAddrSpace*/3, /*AddrSpace*/1, /*AddrSpace*/4, /*AddrSpace*/6,
        GIM_CheckHasNoUse, /*MI*/0,
        GIM_CheckPointerToAny, /*MI*/0, /*Op*/1, /*SizeInBits*/0,
        GIM_CheckComplexPattern, /*MI*/0, /*Op*/1, /*Renderer*/GIMT_Encode2(0), GIMT_Encode2(GICP_gi_global_offset),
        // (atomic_load_xor:{ *:[i64] } (GlobalOffset:{ *:[iPTR] } i64:{ *:[i64] }:$vaddr, i32:{ *:[i32] }:$offset), i64:{ *:[i64] }:$data)<<P:Predicate_atomic_load_xor_global_noret_64>>  =>  (GLOBAL_ATOMIC_XOR_X2 VReg_64:{ *:[i64] }:$vaddr, anonymous_15036:{ *:[i64] }:$data, ?:{ *:[i32] }:$offset)
        GIR_BuildMI, /*InsnID*/0, /*Opcode*/GIMT_Encode2(AMDGPU::GLOBAL_ATOMIC_XOR_X2),
        GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/0, // vaddr
        GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/2, // data
        GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/1, // offset
        GIR_AddImm8, /*InsnID*/0, /*Imm*/0,
        GIR_MergeMemOperands, /*InsnID*/0, /*NumInsns*/1, /*MergeInsnID's*/0,
        GIR_ConstrainSelectedInstOperands, /*InsnID*/0,
        GIR_EraseFromParent, /*InsnID*/0,
        // GIR_Coverage, 3250,
        GIR_Done,
      // Label 2699: @175485
      GIM_Try, /*On fail goto*//*Label 2700*/ GIMT_Encode4(175550), // Rule ID 3252 //
        GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasFlatGlobalInsts),
        GIM_CheckMemoryAddressSpace, /*MI*/0, /*MMO*/0, /*NumAddrSpace*/3, /*AddrSpace*/1, /*AddrSpace*/4, /*AddrSpace*/6,
        GIM_CheckRegBankForClass, /*MI*/0, /*Op*/0, /*RC*/GIMT_Encode2(AMDGPU::AV_64RegClassID),
        GIM_CheckPointerToAny, /*MI*/0, /*Op*/1, /*SizeInBits*/0,
        GIM_CheckComplexPattern, /*MI*/0, /*Op*/1, /*Renderer*/GIMT_Encode2(0), GIMT_Encode2(GICP_gi_global_offset),
        // (atomic_load_xor:{ *:[i64] } (GlobalOffset:{ *:[iPTR] } i64:{ *:[i64] }:$vaddr, i32:{ *:[i32] }:$offset), i64:{ *:[i64] }:$data)<<P:Predicate_atomic_load_xor_global_64>>  =>  (GLOBAL_ATOMIC_XOR_X2_RTN:{ *:[i64] } VReg_64:{ *:[i64] }:$vaddr, anonymous_15036:{ *:[i64] }:$data, ?:{ *:[i32] }:$offset)
        GIR_BuildMI, /*InsnID*/0, /*Opcode*/GIMT_Encode2(AMDGPU::GLOBAL_ATOMIC_XOR_X2_RTN),
        GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/0, // DstI[vdst]
        GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/0, // vaddr
        GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/2, // data
        GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/1, // offset
        GIR_AddImm8, /*InsnID*/0, /*Imm*/1,
        GIR_MergeMemOperands, /*InsnID*/0, /*NumInsns*/1, /*MergeInsnID's*/0,
        GIR_ConstrainSelectedInstOperands, /*InsnID*/0,
        GIR_EraseFromParent, /*InsnID*/0,
        // GIR_Coverage, 3252,
        GIR_Done,
      // Label 2700: @175550
      GIM_Try, /*On fail goto*//*Label 2701*/ GIMT_Encode4(175609), // Rule ID 2878 //
        GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasFlatAddressSpace),
        GIM_CheckMemoryAddressSpace, /*MI*/0, /*MMO*/0, /*NumAddrSpace*/4, /*AddrSpace*/0, /*AddrSpace*/1, /*AddrSpace*/4, /*AddrSpace*/6,
        GIM_CheckHasNoUse, /*MI*/0,
        GIM_CheckPointerToAny, /*MI*/0, /*Op*/1, /*SizeInBits*/0,
        GIM_CheckComplexPattern, /*MI*/0, /*Op*/1, /*Renderer*/GIMT_Encode2(0), GIMT_Encode2(GICP_gi_flat_offset),
        // (atomic_load_xor:{ *:[i64] } (FlatOffset:{ *:[iPTR] } i64:{ *:[i64] }:$vaddr, i32:{ *:[i32] }:$offset), i64:{ *:[i64] }:$data)<<P:Predicate_atomic_load_xor_flat_noret_64>>  =>  (FLAT_ATOMIC_XOR_X2 VReg_64:{ *:[i64] }:$vaddr, anonymous_15036:{ *:[i64] }:$data, ?:{ *:[i32] }:$offset)
        GIR_BuildMI, /*InsnID*/0, /*Opcode*/GIMT_Encode2(AMDGPU::FLAT_ATOMIC_XOR_X2),
        GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/0, // vaddr
        GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/2, // data
        GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/1, // offset
        GIR_AddImm8, /*InsnID*/0, /*Imm*/0,
        GIR_MergeMemOperands, /*InsnID*/0, /*NumInsns*/1, /*MergeInsnID's*/0,
        GIR_ConstrainSelectedInstOperands, /*InsnID*/0,
        GIR_EraseFromParent, /*InsnID*/0,
        // GIR_Coverage, 2878,
        GIR_Done,
      // Label 2701: @175609
      GIM_Try, /*On fail goto*//*Label 2702*/ GIMT_Encode4(175667), // Rule ID 2930 //
        GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasFlatAddressSpace),
        GIM_CheckMemoryAddressSpace, /*MI*/0, /*MMO*/0, /*NumAddrSpace*/3, /*AddrSpace*/1, /*AddrSpace*/4, /*AddrSpace*/6,
        GIM_CheckHasNoUse, /*MI*/0,
        GIM_CheckPointerToAny, /*MI*/0, /*Op*/1, /*SizeInBits*/0,
        GIM_CheckComplexPattern, /*MI*/0, /*Op*/1, /*Renderer*/GIMT_Encode2(0), GIMT_Encode2(GICP_gi_flat_offset),
        // (atomic_load_xor:{ *:[i64] } (FlatOffset:{ *:[iPTR] } i64:{ *:[i64] }:$vaddr, i32:{ *:[i32] }:$offset), i64:{ *:[i64] }:$data)<<P:Predicate_atomic_load_xor_global_noret_64>>  =>  (FLAT_ATOMIC_XOR_X2 VReg_64:{ *:[i64] }:$vaddr, anonymous_15036:{ *:[i64] }:$data, ?:{ *:[i32] }:$offset)
        GIR_BuildMI, /*InsnID*/0, /*Opcode*/GIMT_Encode2(AMDGPU::FLAT_ATOMIC_XOR_X2),
        GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/0, // vaddr
        GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/2, // data
        GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/1, // offset
        GIR_AddImm8, /*InsnID*/0, /*Imm*/0,
        GIR_MergeMemOperands, /*InsnID*/0, /*NumInsns*/1, /*MergeInsnID's*/0,
        GIR_ConstrainSelectedInstOperands, /*InsnID*/0,
        GIR_EraseFromParent, /*InsnID*/0,
        // GIR_Coverage, 2930,
        GIR_Done,
      // Label 2702: @175667
      GIM_Try, /*On fail goto*//*Label 2703*/ GIMT_Encode4(175733), // Rule ID 2877 //
        GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasFlatAddressSpace),
        GIM_CheckMemoryAddressSpace, /*MI*/0, /*MMO*/0, /*NumAddrSpace*/4, /*AddrSpace*/0, /*AddrSpace*/1, /*AddrSpace*/4, /*AddrSpace*/6,
        GIM_CheckRegBankForClass, /*MI*/0, /*Op*/0, /*RC*/GIMT_Encode2(AMDGPU::AV_64RegClassID),
        GIM_CheckPointerToAny, /*MI*/0, /*Op*/1, /*SizeInBits*/0,
        GIM_CheckComplexPattern, /*MI*/0, /*Op*/1, /*Renderer*/GIMT_Encode2(0), GIMT_Encode2(GICP_gi_flat_offset),
        // (atomic_load_xor:{ *:[i64] } (FlatOffset:{ *:[iPTR] } i64:{ *:[i64] }:$vaddr, i32:{ *:[i32] }:$offset), i64:{ *:[i64] }:$data)<<P:Predicate_atomic_load_xor_flat_64>>  =>  (FLAT_ATOMIC_XOR_X2_RTN:{ *:[i64] } VReg_64:{ *:[i64] }:$vaddr, anonymous_15036:{ *:[i64] }:$data, ?:{ *:[i32] }:$offset)
        GIR_BuildMI, /*InsnID*/0, /*Opcode*/GIMT_Encode2(AMDGPU::FLAT_ATOMIC_XOR_X2_RTN),
        GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/0, // DstI[vdst]
        GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/0, // vaddr
        GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/2, // data
        GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/1, // offset
        GIR_AddImm8, /*InsnID*/0, /*Imm*/1,
        GIR_MergeMemOperands, /*InsnID*/0, /*NumInsns*/1, /*MergeInsnID's*/0,
        GIR_ConstrainSelectedInstOperands, /*InsnID*/0,
        GIR_EraseFromParent, /*InsnID*/0,
        // GIR_Coverage, 2877,
        GIR_Done,
      // Label 2703: @175733
      GIM_Try, /*On fail goto*//*Label 2704*/ GIMT_Encode4(175798), // Rule ID 2929 //
        GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasFlatAddressSpace),
        GIM_CheckMemoryAddressSpace, /*MI*/0, /*MMO*/0, /*NumAddrSpace*/3, /*AddrSpace*/1, /*AddrSpace*/4, /*AddrSpace*/6,
        GIM_CheckRegBankForClass, /*MI*/0, /*Op*/0, /*RC*/GIMT_Encode2(AMDGPU::AV_64RegClassID),
        GIM_CheckPointerToAny, /*MI*/0, /*Op*/1, /*SizeInBits*/0,
        GIM_CheckComplexPattern, /*MI*/0, /*Op*/1, /*Renderer*/GIMT_Encode2(0), GIMT_Encode2(GICP_gi_flat_offset),
        // (atomic_load_xor:{ *:[i64] } (FlatOffset:{ *:[iPTR] } i64:{ *:[i64] }:$vaddr, i32:{ *:[i32] }:$offset), i64:{ *:[i64] }:$data)<<P:Predicate_atomic_load_xor_global_64>>  =>  (FLAT_ATOMIC_XOR_X2_RTN:{ *:[i64] } VReg_64:{ *:[i64] }:$vaddr, anonymous_15036:{ *:[i64] }:$data, ?:{ *:[i32] }:$offset)
        GIR_BuildMI, /*InsnID*/0, /*Opcode*/GIMT_Encode2(AMDGPU::FLAT_ATOMIC_XOR_X2_RTN),
        GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/0, // DstI[vdst]
        GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/0, // vaddr
        GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/2, // data
        GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/1, // offset
        GIR_AddImm8, /*InsnID*/0, /*Imm*/1,
        GIR_MergeMemOperands, /*InsnID*/0, /*NumInsns*/1, /*MergeInsnID's*/0,
        GIR_ConstrainSelectedInstOperands, /*InsnID*/0,
        GIR_EraseFromParent, /*InsnID*/0,
        // GIR_Coverage, 2929,
        GIR_Done,
      // Label 2704: @175798
      GIM_Reject,
    // Label 2682: @175799
    GIM_Reject,
    // Label 2658: @175800
    GIM_Reject,
    // Label 23: @175801
    GIM_SwitchType, /*MI*/0, /*Op*/0, /*[*/GIMT_Encode2(9), GIMT_Encode2(11), /*)*//*default:*//*Label 2707*/ GIMT_Encode4(178644),
    /*GILLT_s32*//*Label 2705*/ GIMT_Encode4(175820),
    /*GILLT_s64*//*Label 2706*/ GIMT_Encode4(177232),
    // Label 2705: @175820
    GIM_Try, /*On fail goto*//*Label 2708*/ GIMT_Encode4(177231),
      GIM_CheckType, /*MI*/0, /*Op*/2, /*Type*/GILLT_s32,
      GIM_Try, /*On fail goto*//*Label 2709*/ GIMT_Encode4(175897), // Rule ID 4550 //
        GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasUnrestrictedSOffset),
        GIM_CheckMemoryAddressSpace, /*MI*/0, /*MMO*/0, /*NumAddrSpace*/3, /*AddrSpace*/1, /*AddrSpace*/4, /*AddrSpace*/6,
        GIM_CheckHasNoUse, /*MI*/0,
        GIM_CheckPointerToAny, /*MI*/0, /*Op*/1, /*SizeInBits*/0,
        GIM_CheckComplexPattern, /*MI*/0, /*Op*/1, /*Renderer*/GIMT_Encode2(0), GIMT_Encode2(GICP_gi_mubuf_addr64),
        // (atomic_load_max:{ *:[i32] } (MUBUFAddr64:{ *:[iPTR] } v4i32:{ *:[v4i32] }:$srsrc, i64:{ *:[i64] }:$vaddr, i32:{ *:[i32] }:$soffset, i32:{ *:[i32] }:$offset), i32:{ *:[i32] }:$vdata_in)<<P:Predicate_atomic_load_max_global_noret_32>>  =>  (BUFFER_ATOMIC_SMAX_ADDR64 anonymous_15037:{ *:[i32] }:$vdata_in, VReg_64:{ *:[i64] }:$vaddr, SReg_128:{ *:[v4i32] }:$srsrc, SCSrc_b32:{ *:[i32] }:$soffset, offset:{ *:[i32] }:$offset)
        GIR_BuildMI, /*InsnID*/0, /*Opcode*/GIMT_Encode2(AMDGPU::BUFFER_ATOMIC_SMAX_ADDR64),
        GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/2, // vdata_in
        GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/1, // vaddr
        GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/0, // srsrc
        GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/2, // soffset
        GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/3, // offset
        GIR_AddImm8, /*InsnID*/0, /*Imm*/0,
        GIR_MergeMemOperands, /*InsnID*/0, /*NumInsns*/1, /*MergeInsnID's*/0,
        GIR_ConstrainSelectedInstOperands, /*InsnID*/0,
        GIR_EraseFromParent, /*InsnID*/0,
        // GIR_Coverage, 4550,
        GIR_Done,
      // Label 2709: @175897
      GIM_Try, /*On fail goto*//*Label 2710*/ GIMT_Encode4(175962), // Rule ID 4554 //
        GIM_CheckMemoryAddressSpace, /*MI*/0, /*MMO*/0, /*NumAddrSpace*/3, /*AddrSpace*/1, /*AddrSpace*/4, /*AddrSpace*/6,
        GIM_CheckHasNoUse, /*MI*/0,
        GIM_CheckPointerToAny, /*MI*/0, /*Op*/1, /*SizeInBits*/0,
        GIM_CheckComplexPattern, /*MI*/0, /*Op*/1, /*Renderer*/GIMT_Encode2(0), GIMT_Encode2(GICP_gi_mubuf_addr64),
        // (atomic_load_max:{ *:[i32] } (MUBUFAddr64:{ *:[iPTR] } v4i32:{ *:[v4i32] }:$srsrc, i64:{ *:[i64] }:$vaddr, i32:{ *:[i32] }:$soffset, i32:{ *:[i32] }:$offset), i32:{ *:[i32] }:$vdata_in)<<P:Predicate_atomic_load_max_global_noret_32>>  =>  (BUFFER_ATOMIC_SMAX_VBUFFER_ADDR64 anonymous_15037:{ *:[i32] }:$vdata_in, VReg_64:{ *:[i64] }:$vaddr, SReg_128:{ *:[v4i32] }:$srsrc, SCSrc_b32:{ *:[i32] }:$soffset, offset:{ *:[i32] }:$offset)
        GIR_BuildMI, /*InsnID*/0, /*Opcode*/GIMT_Encode2(AMDGPU::BUFFER_ATOMIC_SMAX_VBUFFER_ADDR64),
        GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/2, // vdata_in
        GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/1, // vaddr
        GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/0, // srsrc
        GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/2, // soffset
        GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/3, // offset
        GIR_AddImm8, /*InsnID*/0, /*Imm*/0,
        GIR_MergeMemOperands, /*InsnID*/0, /*NumInsns*/1, /*MergeInsnID's*/0,
        GIR_ConstrainSelectedInstOperands, /*InsnID*/0,
        GIR_EraseFromParent, /*InsnID*/0,
        // GIR_Coverage, 4554,
        GIR_Done,
      // Label 2710: @175962
      GIM_Try, /*On fail goto*//*Label 2711*/ GIMT_Encode4(176037), // Rule ID 4548 //
        GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasUnrestrictedSOffset),
        GIM_CheckMemoryAddressSpace, /*MI*/0, /*MMO*/0, /*NumAddrSpace*/3, /*AddrSpace*/1, /*AddrSpace*/4, /*AddrSpace*/6,
        GIM_CheckRegBankForClass, /*MI*/0, /*Op*/0, /*RC*/GIMT_Encode2(AMDGPU::AV_32RegClassID),
        GIM_CheckPointerToAny, /*MI*/0, /*Op*/1, /*SizeInBits*/0,
        GIM_CheckComplexPattern, /*MI*/0, /*Op*/1, /*Renderer*/GIMT_Encode2(0), GIMT_Encode2(GICP_gi_mubuf_addr64),
        // (atomic_load_max:{ *:[i32] } (MUBUFAddr64:{ *:[iPTR] } v4i32:{ *:[v4i32] }:$srsrc, i64:{ *:[i64] }:$vaddr, i32:{ *:[i32] }:$soffset, i32:{ *:[i32] }:$offset), i32:{ *:[i32] }:$vdata_in)<<P:Predicate_atomic_load_max_global_32>>  =>  (BUFFER_ATOMIC_SMAX_ADDR64_RTN:{ *:[i32] } anonymous_15037:{ *:[i32] }:$vdata_in, VReg_64:{ *:[i64] }:$vaddr, SReg_128:{ *:[v4i32] }:$srsrc, SCSrc_b32:{ *:[i32] }:$soffset, offset:{ *:[i32] }:$offset)
        GIR_BuildMI, /*InsnID*/0, /*Opcode*/GIMT_Encode2(AMDGPU::BUFFER_ATOMIC_SMAX_ADDR64_RTN),
        GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/0, // DstI[vdata]
        GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/2, // vdata_in
        GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/1, // vaddr
        GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/0, // srsrc
        GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/2, // soffset
        GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/3, // offset
        GIR_AddImm8, /*InsnID*/0, /*Imm*/1,
        GIR_MergeMemOperands, /*InsnID*/0, /*NumInsns*/1, /*MergeInsnID's*/0,
        GIR_ConstrainSelectedInstOperands, /*InsnID*/0,
        GIR_EraseFromParent, /*InsnID*/0,
        // GIR_Coverage, 4548,
        GIR_Done,
      // Label 2711: @176037
      GIM_Try, /*On fail goto*//*Label 2712*/ GIMT_Encode4(176109), // Rule ID 4552 //
        GIM_CheckMemoryAddressSpace, /*MI*/0, /*MMO*/0, /*NumAddrSpace*/3, /*AddrSpace*/1, /*AddrSpace*/4, /*AddrSpace*/6,
        GIM_CheckRegBankForClass, /*MI*/0, /*Op*/0, /*RC*/GIMT_Encode2(AMDGPU::AV_32RegClassID),
        GIM_CheckPointerToAny, /*MI*/0, /*Op*/1, /*SizeInBits*/0,
        GIM_CheckComplexPattern, /*MI*/0, /*Op*/1, /*Renderer*/GIMT_Encode2(0), GIMT_Encode2(GICP_gi_mubuf_addr64),
        // (atomic_load_max:{ *:[i32] } (MUBUFAddr64:{ *:[iPTR] } v4i32:{ *:[v4i32] }:$srsrc, i64:{ *:[i64] }:$vaddr, i32:{ *:[i32] }:$soffset, i32:{ *:[i32] }:$offset), i32:{ *:[i32] }:$vdata_in)<<P:Predicate_atomic_load_max_global_32>>  =>  (BUFFER_ATOMIC_SMAX_VBUFFER_ADDR64_RTN:{ *:[i32] } anonymous_15037:{ *:[i32] }:$vdata_in, VReg_64:{ *:[i64] }:$vaddr, SReg_128:{ *:[v4i32] }:$srsrc, SCSrc_b32:{ *:[i32] }:$soffset, offset:{ *:[i32] }:$offset)
        GIR_BuildMI, /*InsnID*/0, /*Opcode*/GIMT_Encode2(AMDGPU::BUFFER_ATOMIC_SMAX_VBUFFER_ADDR64_RTN),
        GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/0, // DstI[vdata]
        GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/2, // vdata_in
        GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/1, // vaddr
        GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/0, // srsrc
        GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/2, // soffset
        GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/3, // offset
        GIR_AddImm8, /*InsnID*/0, /*Imm*/1,
        GIR_MergeMemOperands, /*InsnID*/0, /*NumInsns*/1, /*MergeInsnID's*/0,
        GIR_ConstrainSelectedInstOperands, /*InsnID*/0,
        GIR_EraseFromParent, /*InsnID*/0,
        // GIR_Coverage, 4552,
        GIR_Done,
      // Label 2712: @176109
      GIM_Try, /*On fail goto*//*Label 2713*/ GIMT_Encode4(176172), // Rule ID 4549 //
        GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasUnrestrictedSOffset),
        GIM_CheckMemoryAddressSpace, /*MI*/0, /*MMO*/0, /*NumAddrSpace*/3, /*AddrSpace*/1, /*AddrSpace*/4, /*AddrSpace*/6,
        GIM_CheckHasNoUse, /*MI*/0,
        GIM_CheckPointerToAny, /*MI*/0, /*Op*/1, /*SizeInBits*/0,
        GIM_CheckComplexPattern, /*MI*/0, /*Op*/1, /*Renderer*/GIMT_Encode2(0), GIMT_Encode2(GICP_gi_mubuf_offset),
        // (atomic_load_max:{ *:[i32] } (MUBUFOffset:{ *:[iPTR] } v4i32:{ *:[v4i32] }:$srsrc, i32:{ *:[i32] }:$soffset, i32:{ *:[i32] }:$offset), i32:{ *:[i32] }:$vdata_in)<<P:Predicate_atomic_load_max_global_noret_32>>  =>  (BUFFER_ATOMIC_SMAX_OFFSET anonymous_15037:{ *:[i32] }:$vdata_in, SReg_128:{ *:[v4i32] }:$srsrc, SCSrc_b32:{ *:[i32] }:$soffset, offset:{ *:[i32] }:$offset)
        GIR_BuildMI, /*InsnID*/0, /*Opcode*/GIMT_Encode2(AMDGPU::BUFFER_ATOMIC_SMAX_OFFSET),
        GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/2, // vdata_in
        GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/0, // srsrc
        GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/1, // soffset
        GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/2, // offset
        GIR_AddImm8, /*InsnID*/0, /*Imm*/0,
        GIR_MergeMemOperands, /*InsnID*/0, /*NumInsns*/1, /*MergeInsnID's*/0,
        GIR_ConstrainSelectedInstOperands, /*InsnID*/0,
        GIR_EraseFromParent, /*InsnID*/0,
        // GIR_Coverage, 4549,
        GIR_Done,
      // Label 2713: @176172
      GIM_Try, /*On fail goto*//*Label 2714*/ GIMT_Encode4(176232), // Rule ID 4553 //
        GIM_CheckMemoryAddressSpace, /*MI*/0, /*MMO*/0, /*NumAddrSpace*/3, /*AddrSpace*/1, /*AddrSpace*/4, /*AddrSpace*/6,
        GIM_CheckHasNoUse, /*MI*/0,
        GIM_CheckPointerToAny, /*MI*/0, /*Op*/1, /*SizeInBits*/0,
        GIM_CheckComplexPattern, /*MI*/0, /*Op*/1, /*Renderer*/GIMT_Encode2(0), GIMT_Encode2(GICP_gi_mubuf_offset),
        // (atomic_load_max:{ *:[i32] } (MUBUFOffset:{ *:[iPTR] } v4i32:{ *:[v4i32] }:$srsrc, i32:{ *:[i32] }:$soffset, i32:{ *:[i32] }:$offset), i32:{ *:[i32] }:$vdata_in)<<P:Predicate_atomic_load_max_global_noret_32>>  =>  (BUFFER_ATOMIC_SMAX_VBUFFER_OFFSET anonymous_15037:{ *:[i32] }:$vdata_in, SReg_128:{ *:[v4i32] }:$srsrc, SCSrc_b32:{ *:[i32] }:$soffset, offset:{ *:[i32] }:$offset)
        GIR_BuildMI, /*InsnID*/0, /*Opcode*/GIMT_Encode2(AMDGPU::BUFFER_ATOMIC_SMAX_VBUFFER_OFFSET),
        GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/2, // vdata_in
        GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/0, // srsrc
        GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/1, // soffset
        GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/2, // offset
        GIR_AddImm8, /*InsnID*/0, /*Imm*/0,
        GIR_MergeMemOperands, /*InsnID*/0, /*NumInsns*/1, /*MergeInsnID's*/0,
        GIR_ConstrainSelectedInstOperands, /*InsnID*/0,
        GIR_EraseFromParent, /*InsnID*/0,
        // GIR_Coverage, 4553,
        GIR_Done,
      // Label 2714: @176232
      GIM_Try, /*On fail goto*//*Label 2715*/ GIMT_Encode4(176302), // Rule ID 4547 //
        GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasUnrestrictedSOffset),
        GIM_CheckMemoryAddressSpace, /*MI*/0, /*MMO*/0, /*NumAddrSpace*/3, /*AddrSpace*/1, /*AddrSpace*/4, /*AddrSpace*/6,
        GIM_CheckRegBankForClass, /*MI*/0, /*Op*/0, /*RC*/GIMT_Encode2(AMDGPU::AV_32RegClassID),
        GIM_CheckPointerToAny, /*MI*/0, /*Op*/1, /*SizeInBits*/0,
        GIM_CheckComplexPattern, /*MI*/0, /*Op*/1, /*Renderer*/GIMT_Encode2(0), GIMT_Encode2(GICP_gi_mubuf_offset),
        // (atomic_load_max:{ *:[i32] } (MUBUFOffset:{ *:[iPTR] } v4i32:{ *:[v4i32] }:$srsrc, i32:{ *:[i32] }:$soffset, i32:{ *:[i32] }:$offset), i32:{ *:[i32] }:$vdata_in)<<P:Predicate_atomic_load_max_global_32>>  =>  (BUFFER_ATOMIC_SMAX_OFFSET_RTN:{ *:[i32] } anonymous_15037:{ *:[i32] }:$vdata_in, SReg_128:{ *:[v4i32] }:$srsrc, SCSrc_b32:{ *:[i32] }:$soffset, offset:{ *:[i32] }:$offset)
        GIR_BuildMI, /*InsnID*/0, /*Opcode*/GIMT_Encode2(AMDGPU::BUFFER_ATOMIC_SMAX_OFFSET_RTN),
        GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/0, // DstI[vdata]
        GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/2, // vdata_in
        GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/0, // srsrc
        GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/1, // soffset
        GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/2, // offset
        GIR_AddImm8, /*InsnID*/0, /*Imm*/1,
        GIR_MergeMemOperands, /*InsnID*/0, /*NumInsns*/1, /*MergeInsnID's*/0,
        GIR_ConstrainSelectedInstOperands, /*InsnID*/0,
        GIR_EraseFromParent, /*InsnID*/0,
        // GIR_Coverage, 4547,
        GIR_Done,
      // Label 2715: @176302
      GIM_Try, /*On fail goto*//*Label 2716*/ GIMT_Encode4(176369), // Rule ID 4551 //
        GIM_CheckMemoryAddressSpace, /*MI*/0, /*MMO*/0, /*NumAddrSpace*/3, /*AddrSpace*/1, /*AddrSpace*/4, /*AddrSpace*/6,
        GIM_CheckRegBankForClass, /*MI*/0, /*Op*/0, /*RC*/GIMT_Encode2(AMDGPU::AV_32RegClassID),
        GIM_CheckPointerToAny, /*MI*/0, /*Op*/1, /*SizeInBits*/0,
        GIM_CheckComplexPattern, /*MI*/0, /*Op*/1, /*Renderer*/GIMT_Encode2(0), GIMT_Encode2(GICP_gi_mubuf_offset),
        // (atomic_load_max:{ *:[i32] } (MUBUFOffset:{ *:[iPTR] } v4i32:{ *:[v4i32] }:$srsrc, i32:{ *:[i32] }:$soffset, i32:{ *:[i32] }:$offset), i32:{ *:[i32] }:$vdata_in)<<P:Predicate_atomic_load_max_global_32>>  =>  (BUFFER_ATOMIC_SMAX_VBUFFER_OFFSET_RTN:{ *:[i32] } anonymous_15037:{ *:[i32] }:$vdata_in, SReg_128:{ *:[v4i32] }:$srsrc, SCSrc_b32:{ *:[i32] }:$soffset, offset:{ *:[i32] }:$offset)
        GIR_BuildMI, /*InsnID*/0, /*Opcode*/GIMT_Encode2(AMDGPU::BUFFER_ATOMIC_SMAX_VBUFFER_OFFSET_RTN),
        GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/0, // DstI[vdata]
        GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/2, // vdata_in
        GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/0, // srsrc
        GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/1, // soffset
        GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/2, // offset
        GIR_AddImm8, /*InsnID*/0, /*Imm*/1,
        GIR_MergeMemOperands, /*InsnID*/0, /*NumInsns*/1, /*MergeInsnID's*/0,
        GIR_ConstrainSelectedInstOperands, /*InsnID*/0,
        GIR_EraseFromParent, /*InsnID*/0,
        // GIR_Coverage, 4551,
        GIR_Done,
      // Label 2716: @176369
      GIM_Try, /*On fail goto*//*Label 2717*/ GIMT_Encode4(176425), // Rule ID 6953 //
        GIM_CheckFeatures, GIMT_Encode2(GIFBS_LDSRequiresM0Init),
        GIM_CheckMemoryAddressSpace, /*MI*/0, /*MMO*/0, /*NumAddrSpace*/1, /*AddrSpace*/3,
        GIM_CheckHasNoUse, /*MI*/0,
        GIM_CheckPointerToAny, /*MI*/0, /*Op*/1, /*SizeInBits*/0,
        GIM_CheckComplexPattern, /*MI*/0, /*Op*/1, /*Renderer*/GIMT_Encode2(0), GIMT_Encode2(GICP_gi_ds_1addr_1offset),
        // (atomic_load_max_glue:{ *:[i32] } (DS1Addr1Offset:{ *:[iPTR] } i32:{ *:[i32] }:$ptr, i32:{ *:[i32] }:$offset), i32:{ *:[i32] }:$value)<<P:Predicate_atomic_load_max_local_m0_noret_32>>  =>  (DS_MAX_I32 ?:{ *:[i32] }:$ptr, anonymous_15037:{ *:[i32] }:$value, offset:{ *:[i32] }:$offset, 0:{ *:[i1] })
        GIR_BuildMI, /*InsnID*/0, /*Opcode*/GIMT_Encode2(AMDGPU::DS_MAX_I32),
        GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/0, // ptr
        GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/2, // value
        GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/1, // offset
        GIR_AddImm8, /*InsnID*/0, /*Imm*/0,
        GIR_MergeMemOperands, /*InsnID*/0, /*NumInsns*/1, /*MergeInsnID's*/0,
        GIR_ConstrainSelectedInstOperands, /*InsnID*/0,
        GIR_EraseFromParent, /*InsnID*/0,
        // GIR_Coverage, 6953,
        GIR_Done,
      // Label 2717: @176425
      GIM_Try, /*On fail goto*//*Label 2718*/ GIMT_Encode4(176481), // Rule ID 6955 //
        GIM_CheckFeatures, GIMT_Encode2(GIFBS_NotLDSRequiresM0Init),
        GIM_CheckMemoryAddressSpace, /*MI*/0, /*MMO*/0, /*NumAddrSpace*/1, /*AddrSpace*/3,
        GIM_CheckHasNoUse, /*MI*/0,
        GIM_CheckPointerToAny, /*MI*/0, /*Op*/1, /*SizeInBits*/0,
        GIM_CheckComplexPattern, /*MI*/0, /*Op*/1, /*Renderer*/GIMT_Encode2(0), GIMT_Encode2(GICP_gi_ds_1addr_1offset),
        // (atomic_load_max:{ *:[i32] } (DS1Addr1Offset:{ *:[iPTR] } i32:{ *:[i32] }:$ptr, i32:{ *:[i32] }:$offset), i32:{ *:[i32] }:$value)<<P:Predicate_atomic_load_max_local_noret_32>>  =>  (DS_MAX_I32_gfx9 ?:{ *:[i32] }:$ptr, anonymous_15037:{ *:[i32] }:$value, offset:{ *:[i32] }:$offset, 0:{ *:[i1] })
        GIR_BuildMI, /*InsnID*/0, /*Opcode*/GIMT_Encode2(AMDGPU::DS_MAX_I32_gfx9),
        GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/0, // ptr
        GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/2, // value
        GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/1, // offset
        GIR_AddImm8, /*InsnID*/0, /*Imm*/0,
        GIR_MergeMemOperands, /*InsnID*/0, /*NumInsns*/1, /*MergeInsnID's*/0,
        GIR_ConstrainSelectedInstOperands, /*InsnID*/0,
        GIR_EraseFromParent, /*InsnID*/0,
        // GIR_Coverage, 6955,
        GIR_Done,
      // Label 2718: @176481
      GIM_Try, /*On fail goto*//*Label 2719*/ GIMT_Encode4(176537), // Rule ID 6957 //
        GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasGDS),
        GIM_CheckMemoryAddressSpace, /*MI*/0, /*MMO*/0, /*NumAddrSpace*/1, /*AddrSpace*/2,
        GIM_CheckHasNoUse, /*MI*/0,
        GIM_CheckPointerToAny, /*MI*/0, /*Op*/1, /*SizeInBits*/0,
        GIM_CheckComplexPattern, /*MI*/0, /*Op*/1, /*Renderer*/GIMT_Encode2(0), GIMT_Encode2(GICP_gi_ds_1addr_1offset),
        // (atomic_load_max_glue:{ *:[i32] } (DS1Addr1Offset:{ *:[iPTR] } i32:{ *:[i32] }:$ptr, i32:{ *:[i32] }:$offset), i32:{ *:[i32] }:$value)<<P:Predicate_atomic_load_max_region_m0_noret_32>>  =>  (DS_MAX_I32 ?:{ *:[i32] }:$ptr, anonymous_15037:{ *:[i32] }:$value, offset:{ *:[i32] }:$offset, 1:{ *:[i1] })
        GIR_BuildMI, /*InsnID*/0, /*Opcode*/GIMT_Encode2(AMDGPU::DS_MAX_I32),
        GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/0, // ptr
        GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/2, // value
        GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/1, // offset
        GIR_AddImm8, /*InsnID*/0, /*Imm*/1,
        GIR_MergeMemOperands, /*InsnID*/0, /*NumInsns*/1, /*MergeInsnID's*/0,
        GIR_ConstrainSelectedInstOperands, /*InsnID*/0,
        GIR_EraseFromParent, /*InsnID*/0,
        // GIR_Coverage, 6957,
        GIR_Done,
      // Label 2719: @176537
      GIM_Try, /*On fail goto*//*Label 2720*/ GIMT_Encode4(176600), // Rule ID 6952 //
        GIM_CheckFeatures, GIMT_Encode2(GIFBS_LDSRequiresM0Init),
        GIM_CheckMemoryAddressSpace, /*MI*/0, /*MMO*/0, /*NumAddrSpace*/1, /*AddrSpace*/3,
        GIM_CheckRegBankForClass, /*MI*/0, /*Op*/0, /*RC*/GIMT_Encode2(AMDGPU::AV_32RegClassID),
        GIM_CheckPointerToAny, /*MI*/0, /*Op*/1, /*SizeInBits*/0,
        GIM_CheckComplexPattern, /*MI*/0, /*Op*/1, /*Renderer*/GIMT_Encode2(0), GIMT_Encode2(GICP_gi_ds_1addr_1offset),
        // (atomic_load_max_glue:{ *:[i32] } (DS1Addr1Offset:{ *:[iPTR] } i32:{ *:[i32] }:$ptr, i32:{ *:[i32] }:$offset), i32:{ *:[i32] }:$value)<<P:Predicate_atomic_load_max_local_m0_32>>  =>  (DS_MAX_RTN_I32:{ *:[i32] } ?:{ *:[i32] }:$ptr, anonymous_15037:{ *:[i32] }:$value, offset:{ *:[i32] }:$offset, 0:{ *:[i1] })
        GIR_BuildMI, /*InsnID*/0, /*Opcode*/GIMT_Encode2(AMDGPU::DS_MAX_RTN_I32),
        GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/0, // DstI[vdst]
        GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/0, // ptr
        GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/2, // value
        GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/1, // offset
        GIR_AddImm8, /*InsnID*/0, /*Imm*/0,
        GIR_MergeMemOperands, /*InsnID*/0, /*NumInsns*/1, /*MergeInsnID's*/0,
        GIR_ConstrainSelectedInstOperands, /*InsnID*/0,
        GIR_EraseFromParent, /*InsnID*/0,
        // GIR_Coverage, 6952,
        GIR_Done,
      // Label 2720: @176600
      GIM_Try, /*On fail goto*//*Label 2721*/ GIMT_Encode4(176663), // Rule ID 6954 //
        GIM_CheckFeatures, GIMT_Encode2(GIFBS_NotLDSRequiresM0Init),
        GIM_CheckMemoryAddressSpace, /*MI*/0, /*MMO*/0, /*NumAddrSpace*/1, /*AddrSpace*/3,
        GIM_CheckRegBankForClass, /*MI*/0, /*Op*/0, /*RC*/GIMT_Encode2(AMDGPU::AV_32RegClassID),
        GIM_CheckPointerToAny, /*MI*/0, /*Op*/1, /*SizeInBits*/0,
        GIM_CheckComplexPattern, /*MI*/0, /*Op*/1, /*Renderer*/GIMT_Encode2(0), GIMT_Encode2(GICP_gi_ds_1addr_1offset),
        // (atomic_load_max:{ *:[i32] } (DS1Addr1Offset:{ *:[iPTR] } i32:{ *:[i32] }:$ptr, i32:{ *:[i32] }:$offset), i32:{ *:[i32] }:$value)<<P:Predicate_atomic_load_max_local_32>>  =>  (DS_MAX_RTN_I32_gfx9:{ *:[i32] } ?:{ *:[i32] }:$ptr, anonymous_15037:{ *:[i32] }:$value, offset:{ *:[i32] }:$offset, 0:{ *:[i1] })
        GIR_BuildMI, /*InsnID*/0, /*Opcode*/GIMT_Encode2(AMDGPU::DS_MAX_RTN_I32_gfx9),
        GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/0, // DstI[vdst]
        GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/0, // ptr
        GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/2, // value
        GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/1, // offset
        GIR_AddImm8, /*InsnID*/0, /*Imm*/0,
        GIR_MergeMemOperands, /*InsnID*/0, /*NumInsns*/1, /*MergeInsnID's*/0,
        GIR_ConstrainSelectedInstOperands, /*InsnID*/0,
        GIR_EraseFromParent, /*InsnID*/0,
        // GIR_Coverage, 6954,
        GIR_Done,
      // Label 2721: @176663
      GIM_Try, /*On fail goto*//*Label 2722*/ GIMT_Encode4(176726), // Rule ID 6956 //
        GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasGDS),
        GIM_CheckMemoryAddressSpace, /*MI*/0, /*MMO*/0, /*NumAddrSpace*/1, /*AddrSpace*/2,
        GIM_CheckRegBankForClass, /*MI*/0, /*Op*/0, /*RC*/GIMT_Encode2(AMDGPU::AV_32RegClassID),
        GIM_CheckPointerToAny, /*MI*/0, /*Op*/1, /*SizeInBits*/0,
        GIM_CheckComplexPattern, /*MI*/0, /*Op*/1, /*Renderer*/GIMT_Encode2(0), GIMT_Encode2(GICP_gi_ds_1addr_1offset),
        // (atomic_load_max_glue:{ *:[i32] } (DS1Addr1Offset:{ *:[iPTR] } i32:{ *:[i32] }:$ptr, i32:{ *:[i32] }:$offset), i32:{ *:[i32] }:$value)<<P:Predicate_atomic_load_max_region_m0_32>>  =>  (DS_MAX_RTN_I32:{ *:[i32] } ?:{ *:[i32] }:$ptr, anonymous_15037:{ *:[i32] }:$value, offset:{ *:[i32] }:$offset, 1:{ *:[i1] })
        GIR_BuildMI, /*InsnID*/0, /*Opcode*/GIMT_Encode2(AMDGPU::DS_MAX_RTN_I32),
        GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/0, // DstI[vdst]
        GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/0, // ptr
        GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/2, // value
        GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/1, // offset
        GIR_AddImm8, /*InsnID*/0, /*Imm*/1,
        GIR_MergeMemOperands, /*InsnID*/0, /*NumInsns*/1, /*MergeInsnID's*/0,
        GIR_ConstrainSelectedInstOperands, /*InsnID*/0,
        GIR_EraseFromParent, /*InsnID*/0,
        // GIR_Coverage, 6956,
        GIR_Done,
      // Label 2722: @176726
      GIM_Try, /*On fail goto*//*Label 2723*/ GIMT_Encode4(176789), // Rule ID 3167 //
        GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasFlatGlobalInsts),
        GIM_CheckMemoryAddressSpace, /*MI*/0, /*MMO*/0, /*NumAddrSpace*/3, /*AddrSpace*/1, /*AddrSpace*/4, /*AddrSpace*/6,
        GIM_CheckHasNoUse, /*MI*/0,
        GIM_CheckPointerToAny, /*MI*/0, /*Op*/1, /*SizeInBits*/0,
        GIM_CheckComplexPattern, /*MI*/0, /*Op*/1, /*Renderer*/GIMT_Encode2(0), GIMT_Encode2(GICP_gi_global_saddr),
        // (atomic_load_max:{ *:[i32] } (GlobalSAddr:{ *:[iPTR] } SReg_64:{ *:[i64] }:$saddr, VGPR_32:{ *:[i32] }:$voffset, i32:{ *:[i32] }:$offset), i32:{ *:[i32] }:$data)<<P:Predicate_atomic_load_max_global_noret_32>>  =>  (GLOBAL_ATOMIC_SMAX_SADDR ?:{ *:[i32] }:$voffset, anonymous_15037:{ *:[i32] }:$data, ?:{ *:[i64] }:$saddr, ?:{ *:[i32] }:$offset)
        GIR_BuildMI, /*InsnID*/0, /*Opcode*/GIMT_Encode2(AMDGPU::GLOBAL_ATOMIC_SMAX_SADDR),
        GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/1, // voffset
        GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/2, // data
        GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/0, // saddr
        GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/2, // offset
        GIR_AddImm8, /*InsnID*/0, /*Imm*/0,
        GIR_MergeMemOperands, /*InsnID*/0, /*NumInsns*/1, /*MergeInsnID's*/0,
        GIR_ConstrainSelectedInstOperands, /*InsnID*/0,
        GIR_EraseFromParent, /*InsnID*/0,
        // GIR_Coverage, 3167,
        GIR_Done,
      // Label 2723: @176789
      GIM_Try, /*On fail goto*//*Label 2724*/ GIMT_Encode4(176859), // Rule ID 3169 //
        GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasFlatGlobalInsts),
        GIM_CheckMemoryAddressSpace, /*MI*/0, /*MMO*/0, /*NumAddrSpace*/3, /*AddrSpace*/1, /*AddrSpace*/4, /*AddrSpace*/6,
        GIM_CheckRegBankForClass, /*MI*/0, /*Op*/0, /*RC*/GIMT_Encode2(AMDGPU::AV_32RegClassID),
        GIM_CheckPointerToAny, /*MI*/0, /*Op*/1, /*SizeInBits*/0,
        GIM_CheckComplexPattern, /*MI*/0, /*Op*/1, /*Renderer*/GIMT_Encode2(0), GIMT_Encode2(GICP_gi_global_saddr),
        // (atomic_load_max:{ *:[i32] } (GlobalSAddr:{ *:[iPTR] } SReg_64:{ *:[i64] }:$saddr, VGPR_32:{ *:[i32] }:$voffset, i32:{ *:[i32] }:$offset), i32:{ *:[i32] }:$data)<<P:Predicate_atomic_load_max_global_32>>  =>  (GLOBAL_ATOMIC_SMAX_SADDR_RTN:{ *:[i32] } ?:{ *:[i32] }:$voffset, anonymous_15037:{ *:[i32] }:$data, ?:{ *:[i64] }:$saddr, ?:{ *:[i32] }:$offset)
        GIR_BuildMI, /*InsnID*/0, /*Opcode*/GIMT_Encode2(AMDGPU::GLOBAL_ATOMIC_SMAX_SADDR_RTN),
        GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/0, // DstI[vdst]
        GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/1, // voffset
        GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/2, // data
        GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/0, // saddr
        GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/2, // offset
        GIR_AddImm8, /*InsnID*/0, /*Imm*/1,
        GIR_MergeMemOperands, /*InsnID*/0, /*NumInsns*/1, /*MergeInsnID's*/0,
        GIR_ConstrainSelectedInstOperands, /*InsnID*/0,
        GIR_EraseFromParent, /*InsnID*/0,
        // GIR_Coverage, 3169,
        GIR_Done,
      // Label 2724: @176859
      GIM_Try, /*On fail goto*//*Label 2725*/ GIMT_Encode4(176917), // Rule ID 3166 //
        GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasFlatGlobalInsts),
        GIM_CheckMemoryAddressSpace, /*MI*/0, /*MMO*/0, /*NumAddrSpace*/3, /*AddrSpace*/1, /*AddrSpace*/4, /*AddrSpace*/6,
        GIM_CheckHasNoUse, /*MI*/0,
        GIM_CheckPointerToAny, /*MI*/0, /*Op*/1, /*SizeInBits*/0,
        GIM_CheckComplexPattern, /*MI*/0, /*Op*/1, /*Renderer*/GIMT_Encode2(0), GIMT_Encode2(GICP_gi_global_offset),
        // (atomic_load_max:{ *:[i32] } (GlobalOffset:{ *:[iPTR] } i64:{ *:[i64] }:$vaddr, i32:{ *:[i32] }:$offset), i32:{ *:[i32] }:$data)<<P:Predicate_atomic_load_max_global_noret_32>>  =>  (GLOBAL_ATOMIC_SMAX VReg_64:{ *:[i64] }:$vaddr, anonymous_15037:{ *:[i32] }:$data, ?:{ *:[i32] }:$offset)
        GIR_BuildMI, /*InsnID*/0, /*Opcode*/GIMT_Encode2(AMDGPU::GLOBAL_ATOMIC_SMAX),
        GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/0, // vaddr
        GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/2, // data
        GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/1, // offset
        GIR_AddImm8, /*InsnID*/0, /*Imm*/0,
        GIR_MergeMemOperands, /*InsnID*/0, /*NumInsns*/1, /*MergeInsnID's*/0,
        GIR_ConstrainSelectedInstOperands, /*InsnID*/0,
        GIR_EraseFromParent, /*InsnID*/0,
        // GIR_Coverage, 3166,
        GIR_Done,
      // Label 2725: @176917
      GIM_Try, /*On fail goto*//*Label 2726*/ GIMT_Encode4(176982), // Rule ID 3168 //
        GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasFlatGlobalInsts),
        GIM_CheckMemoryAddressSpace, /*MI*/0, /*MMO*/0, /*NumAddrSpace*/3, /*AddrSpace*/1, /*AddrSpace*/4, /*AddrSpace*/6,
        GIM_CheckRegBankForClass, /*MI*/0, /*Op*/0, /*RC*/GIMT_Encode2(AMDGPU::AV_32RegClassID),
        GIM_CheckPointerToAny, /*MI*/0, /*Op*/1, /*SizeInBits*/0,
        GIM_CheckComplexPattern, /*MI*/0, /*Op*/1, /*Renderer*/GIMT_Encode2(0), GIMT_Encode2(GICP_gi_global_offset),
        // (atomic_load_max:{ *:[i32] } (GlobalOffset:{ *:[iPTR] } i64:{ *:[i64] }:$vaddr, i32:{ *:[i32] }:$offset), i32:{ *:[i32] }:$data)<<P:Predicate_atomic_load_max_global_32>>  =>  (GLOBAL_ATOMIC_SMAX_RTN:{ *:[i32] } VReg_64:{ *:[i64] }:$vaddr, anonymous_15037:{ *:[i32] }:$data, ?:{ *:[i32] }:$offset)
        GIR_BuildMI, /*InsnID*/0, /*Opcode*/GIMT_Encode2(AMDGPU::GLOBAL_ATOMIC_SMAX_RTN),
        GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/0, // DstI[vdst]
        GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/0, // vaddr
        GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/2, // data
        GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/1, // offset
        GIR_AddImm8, /*InsnID*/0, /*Imm*/1,
        GIR_MergeMemOperands, /*InsnID*/0, /*NumInsns*/1, /*MergeInsnID's*/0,
        GIR_ConstrainSelectedInstOperands, /*InsnID*/0,
        GIR_EraseFromParent, /*InsnID*/0,
        // GIR_Coverage, 3168,
        GIR_Done,
      // Label 2726: @176982
      GIM_Try, /*On fail goto*//*Label 2727*/ GIMT_Encode4(177041), // Rule ID 2838 //
        GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasFlatAddressSpace),
        GIM_CheckMemoryAddressSpace, /*MI*/0, /*MMO*/0, /*NumAddrSpace*/4, /*AddrSpace*/0, /*AddrSpace*/1, /*AddrSpace*/4, /*AddrSpace*/6,
        GIM_CheckHasNoUse, /*MI*/0,
        GIM_CheckPointerToAny, /*MI*/0, /*Op*/1, /*SizeInBits*/0,
        GIM_CheckComplexPattern, /*MI*/0, /*Op*/1, /*Renderer*/GIMT_Encode2(0), GIMT_Encode2(GICP_gi_flat_offset),
        // (atomic_load_max:{ *:[i32] } (FlatOffset:{ *:[iPTR] } i64:{ *:[i64] }:$vaddr, i32:{ *:[i32] }:$offset), i32:{ *:[i32] }:$data)<<P:Predicate_atomic_load_max_flat_noret_32>>  =>  (FLAT_ATOMIC_SMAX VReg_64:{ *:[i64] }:$vaddr, anonymous_15037:{ *:[i32] }:$data, ?:{ *:[i32] }:$offset)
        GIR_BuildMI, /*InsnID*/0, /*Opcode*/GIMT_Encode2(AMDGPU::FLAT_ATOMIC_SMAX),
        GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/0, // vaddr
        GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/2, // data
        GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/1, // offset
        GIR_AddImm8, /*InsnID*/0, /*Imm*/0,
        GIR_MergeMemOperands, /*InsnID*/0, /*NumInsns*/1, /*MergeInsnID's*/0,
        GIR_ConstrainSelectedInstOperands, /*InsnID*/0,
        GIR_EraseFromParent, /*InsnID*/0,
        // GIR_Coverage, 2838,
        GIR_Done,
      // Label 2727: @177041
      GIM_Try, /*On fail goto*//*Label 2728*/ GIMT_Encode4(177099), // Rule ID 2890 //
        GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasFlatAddressSpace),
        GIM_CheckMemoryAddressSpace, /*MI*/0, /*MMO*/0, /*NumAddrSpace*/3, /*AddrSpace*/1, /*AddrSpace*/4, /*AddrSpace*/6,
        GIM_CheckHasNoUse, /*MI*/0,
        GIM_CheckPointerToAny, /*MI*/0, /*Op*/1, /*SizeInBits*/0,
        GIM_CheckComplexPattern, /*MI*/0, /*Op*/1, /*Renderer*/GIMT_Encode2(0), GIMT_Encode2(GICP_gi_flat_offset),
        // (atomic_load_max:{ *:[i32] } (FlatOffset:{ *:[iPTR] } i64:{ *:[i64] }:$vaddr, i32:{ *:[i32] }:$offset), i32:{ *:[i32] }:$data)<<P:Predicate_atomic_load_max_global_noret_32>>  =>  (FLAT_ATOMIC_SMAX VReg_64:{ *:[i64] }:$vaddr, anonymous_15037:{ *:[i32] }:$data, ?:{ *:[i32] }:$offset)
        GIR_BuildMI, /*InsnID*/0, /*Opcode*/GIMT_Encode2(AMDGPU::FLAT_ATOMIC_SMAX),
        GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/0, // vaddr
        GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/2, // data
        GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/1, // offset
        GIR_AddImm8, /*InsnID*/0, /*Imm*/0,
        GIR_MergeMemOperands, /*InsnID*/0, /*NumInsns*/1, /*MergeInsnID's*/0,
        GIR_ConstrainSelectedInstOperands, /*InsnID*/0,
        GIR_EraseFromParent, /*InsnID*/0,
        // GIR_Coverage, 2890,
        GIR_Done,
      // Label 2728: @177099
      GIM_Try, /*On fail goto*//*Label 2729*/ GIMT_Encode4(177165), // Rule ID 2837 //
        GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasFlatAddressSpace),
        GIM_CheckMemoryAddressSpace, /*MI*/0, /*MMO*/0, /*NumAddrSpace*/4, /*AddrSpace*/0, /*AddrSpace*/1, /*AddrSpace*/4, /*AddrSpace*/6,
        GIM_CheckRegBankForClass, /*MI*/0, /*Op*/0, /*RC*/GIMT_Encode2(AMDGPU::AV_32RegClassID),
        GIM_CheckPointerToAny, /*MI*/0, /*Op*/1, /*SizeInBits*/0,
        GIM_CheckComplexPattern, /*MI*/0, /*Op*/1, /*Renderer*/GIMT_Encode2(0), GIMT_Encode2(GICP_gi_flat_offset),
        // (atomic_load_max:{ *:[i32] } (FlatOffset:{ *:[iPTR] } i64:{ *:[i64] }:$vaddr, i32:{ *:[i32] }:$offset), i32:{ *:[i32] }:$data)<<P:Predicate_atomic_load_max_flat_32>>  =>  (FLAT_ATOMIC_SMAX_RTN:{ *:[i32] } VReg_64:{ *:[i64] }:$vaddr, anonymous_15037:{ *:[i32] }:$data, ?:{ *:[i32] }:$offset)
        GIR_BuildMI, /*InsnID*/0, /*Opcode*/GIMT_Encode2(AMDGPU::FLAT_ATOMIC_SMAX_RTN),
        GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/0, // DstI[vdst]
        GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/0, // vaddr
        GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/2, // data
        GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/1, // offset
        GIR_AddImm8, /*InsnID*/0, /*Imm*/1,
        GIR_MergeMemOperands, /*InsnID*/0, /*NumInsns*/1, /*MergeInsnID's*/0,
        GIR_ConstrainSelectedInstOperands, /*InsnID*/0,
        GIR_EraseFromParent, /*InsnID*/0,
        // GIR_Coverage, 2837,
        GIR_Done,
      // Label 2729: @177165
      GIM_Try, /*On fail goto*//*Label 2730*/ GIMT_Encode4(177230), // Rule ID 2889 //
        GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasFlatAddressSpace),
        GIM_CheckMemoryAddressSpace, /*MI*/0, /*MMO*/0, /*NumAddrSpace*/3, /*AddrSpace*/1, /*AddrSpace*/4, /*AddrSpace*/6,
        GIM_CheckRegBankForClass, /*MI*/0, /*Op*/0, /*RC*/GIMT_Encode2(AMDGPU::AV_32RegClassID),
        GIM_CheckPointerToAny, /*MI*/0, /*Op*/1, /*SizeInBits*/0,
        GIM_CheckComplexPattern, /*MI*/0, /*Op*/1, /*Renderer*/GIMT_Encode2(0), GIMT_Encode2(GICP_gi_flat_offset),
        // (atomic_load_max:{ *:[i32] } (FlatOffset:{ *:[iPTR] } i64:{ *:[i64] }:$vaddr, i32:{ *:[i32] }:$offset), i32:{ *:[i32] }:$data)<<P:Predicate_atomic_load_max_global_32>>  =>  (FLAT_ATOMIC_SMAX_RTN:{ *:[i32] } VReg_64:{ *:[i64] }:$vaddr, anonymous_15037:{ *:[i32] }:$data, ?:{ *:[i32] }:$offset)
        GIR_BuildMI, /*InsnID*/0, /*Opcode*/GIMT_Encode2(AMDGPU::FLAT_ATOMIC_SMAX_RTN),
        GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/0, // DstI[vdst]
        GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/0, // vaddr
        GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/2, // data
        GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/1, // offset
        GIR_AddImm8, /*InsnID*/0, /*Imm*/1,
        GIR_MergeMemOperands, /*InsnID*/0, /*NumInsns*/1, /*MergeInsnID's*/0,
        GIR_ConstrainSelectedInstOperands, /*InsnID*/0,
        GIR_EraseFromParent, /*InsnID*/0,
        // GIR_Coverage, 2889,
        GIR_Done,
      // Label 2730: @177230
      GIM_Reject,
    // Label 2708: @177231
    GIM_Reject,
    // Label 2706: @177232
    GIM_Try, /*On fail goto*//*Label 2731*/ GIMT_Encode4(178643),
      GIM_CheckType, /*MI*/0, /*Op*/2, /*Type*/GILLT_s64,
      GIM_Try, /*On fail goto*//*Label 2732*/ GIMT_Encode4(177309), // Rule ID 4646 //
        GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasUnrestrictedSOffset),
        GIM_CheckMemoryAddressSpace, /*MI*/0, /*MMO*/0, /*NumAddrSpace*/3, /*AddrSpace*/1, /*AddrSpace*/4, /*AddrSpace*/6,
        GIM_CheckHasNoUse, /*MI*/0,
        GIM_CheckPointerToAny, /*MI*/0, /*Op*/1, /*SizeInBits*/0,
        GIM_CheckComplexPattern, /*MI*/0, /*Op*/1, /*Renderer*/GIMT_Encode2(0), GIMT_Encode2(GICP_gi_mubuf_addr64),
        // (atomic_load_max:{ *:[i64] } (MUBUFAddr64:{ *:[iPTR] } v4i32:{ *:[v4i32] }:$srsrc, i64:{ *:[i64] }:$vaddr, i32:{ *:[i32] }:$soffset, i32:{ *:[i32] }:$offset), i64:{ *:[i64] }:$vdata_in)<<P:Predicate_atomic_load_max_global_noret_64>>  =>  (BUFFER_ATOMIC_SMAX_X2_ADDR64 anonymous_15036:{ *:[i64] }:$vdata_in, VReg_64:{ *:[i64] }:$vaddr, SReg_128:{ *:[v4i32] }:$srsrc, SCSrc_b32:{ *:[i32] }:$soffset, offset:{ *:[i32] }:$offset)
        GIR_BuildMI, /*InsnID*/0, /*Opcode*/GIMT_Encode2(AMDGPU::BUFFER_ATOMIC_SMAX_X2_ADDR64),
        GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/2, // vdata_in
        GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/1, // vaddr
        GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/0, // srsrc
        GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/2, // soffset
        GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/3, // offset
        GIR_AddImm8, /*InsnID*/0, /*Imm*/0,
        GIR_MergeMemOperands, /*InsnID*/0, /*NumInsns*/1, /*MergeInsnID's*/0,
        GIR_ConstrainSelectedInstOperands, /*InsnID*/0,
        GIR_EraseFromParent, /*InsnID*/0,
        // GIR_Coverage, 4646,
        GIR_Done,
      // Label 2732: @177309
      GIM_Try, /*On fail goto*//*Label 2733*/ GIMT_Encode4(177374), // Rule ID 4650 //
        GIM_CheckMemoryAddressSpace, /*MI*/0, /*MMO*/0, /*NumAddrSpace*/3, /*AddrSpace*/1, /*AddrSpace*/4, /*AddrSpace*/6,
        GIM_CheckHasNoUse, /*MI*/0,
        GIM_CheckPointerToAny, /*MI*/0, /*Op*/1, /*SizeInBits*/0,
        GIM_CheckComplexPattern, /*MI*/0, /*Op*/1, /*Renderer*/GIMT_Encode2(0), GIMT_Encode2(GICP_gi_mubuf_addr64),
        // (atomic_load_max:{ *:[i64] } (MUBUFAddr64:{ *:[iPTR] } v4i32:{ *:[v4i32] }:$srsrc, i64:{ *:[i64] }:$vaddr, i32:{ *:[i32] }:$soffset, i32:{ *:[i32] }:$offset), i64:{ *:[i64] }:$vdata_in)<<P:Predicate_atomic_load_max_global_noret_64>>  =>  (BUFFER_ATOMIC_SMAX_X2_VBUFFER_ADDR64 anonymous_15036:{ *:[i64] }:$vdata_in, VReg_64:{ *:[i64] }:$vaddr, SReg_128:{ *:[v4i32] }:$srsrc, SCSrc_b32:{ *:[i32] }:$soffset, offset:{ *:[i32] }:$offset)
        GIR_BuildMI, /*InsnID*/0, /*Opcode*/GIMT_Encode2(AMDGPU::BUFFER_ATOMIC_SMAX_X2_VBUFFER_ADDR64),
        GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/2, // vdata_in
        GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/1, // vaddr
        GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/0, // srsrc
        GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/2, // soffset
        GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/3, // offset
        GIR_AddImm8, /*InsnID*/0, /*Imm*/0,
        GIR_MergeMemOperands, /*InsnID*/0, /*NumInsns*/1, /*MergeInsnID's*/0,
        GIR_ConstrainSelectedInstOperands, /*InsnID*/0,
        GIR_EraseFromParent, /*InsnID*/0,
        // GIR_Coverage, 4650,
        GIR_Done,
      // Label 2733: @177374
      GIM_Try, /*On fail goto*//*Label 2734*/ GIMT_Encode4(177449), // Rule ID 4644 //
        GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasUnrestrictedSOffset),
        GIM_CheckMemoryAddressSpace, /*MI*/0, /*MMO*/0, /*NumAddrSpace*/3, /*AddrSpace*/1, /*AddrSpace*/4, /*AddrSpace*/6,
        GIM_CheckRegBankForClass, /*MI*/0, /*Op*/0, /*RC*/GIMT_Encode2(AMDGPU::AV_64RegClassID),
        GIM_CheckPointerToAny, /*MI*/0, /*Op*/1, /*SizeInBits*/0,
        GIM_CheckComplexPattern, /*MI*/0, /*Op*/1, /*Renderer*/GIMT_Encode2(0), GIMT_Encode2(GICP_gi_mubuf_addr64),
        // (atomic_load_max:{ *:[i64] } (MUBUFAddr64:{ *:[iPTR] } v4i32:{ *:[v4i32] }:$srsrc, i64:{ *:[i64] }:$vaddr, i32:{ *:[i32] }:$soffset, i32:{ *:[i32] }:$offset), i64:{ *:[i64] }:$vdata_in)<<P:Predicate_atomic_load_max_global_64>>  =>  (BUFFER_ATOMIC_SMAX_X2_ADDR64_RTN:{ *:[i64] } anonymous_15036:{ *:[i64] }:$vdata_in, VReg_64:{ *:[i64] }:$vaddr, SReg_128:{ *:[v4i32] }:$srsrc, SCSrc_b32:{ *:[i32] }:$soffset, offset:{ *:[i32] }:$offset)
        GIR_BuildMI, /*InsnID*/0, /*Opcode*/GIMT_Encode2(AMDGPU::BUFFER_ATOMIC_SMAX_X2_ADDR64_RTN),
        GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/0, // DstI[vdata]
        GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/2, // vdata_in
        GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/1, // vaddr
        GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/0, // srsrc
        GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/2, // soffset
        GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/3, // offset
        GIR_AddImm8, /*InsnID*/0, /*Imm*/1,
        GIR_MergeMemOperands, /*InsnID*/0, /*NumInsns*/1, /*MergeInsnID's*/0,
        GIR_ConstrainSelectedInstOperands, /*InsnID*/0,
        GIR_EraseFromParent, /*InsnID*/0,
        // GIR_Coverage, 4644,
        GIR_Done,
      // Label 2734: @177449
      GIM_Try, /*On fail goto*//*Label 2735*/ GIMT_Encode4(177521), // Rule ID 4648 //
        GIM_CheckMemoryAddressSpace, /*MI*/0, /*MMO*/0, /*NumAddrSpace*/3, /*AddrSpace*/1, /*AddrSpace*/4, /*AddrSpace*/6,
        GIM_CheckRegBankForClass, /*MI*/0, /*Op*/0, /*RC*/GIMT_Encode2(AMDGPU::AV_64RegClassID),
        GIM_CheckPointerToAny, /*MI*/0, /*Op*/1, /*SizeInBits*/0,
        GIM_CheckComplexPattern, /*MI*/0, /*Op*/1, /*Renderer*/GIMT_Encode2(0), GIMT_Encode2(GICP_gi_mubuf_addr64),
        // (atomic_load_max:{ *:[i64] } (MUBUFAddr64:{ *:[iPTR] } v4i32:{ *:[v4i32] }:$srsrc, i64:{ *:[i64] }:$vaddr, i32:{ *:[i32] }:$soffset, i32:{ *:[i32] }:$offset), i64:{ *:[i64] }:$vdata_in)<<P:Predicate_atomic_load_max_global_64>>  =>  (BUFFER_ATOMIC_SMAX_X2_VBUFFER_ADDR64_RTN:{ *:[i64] } anonymous_15036:{ *:[i64] }:$vdata_in, VReg_64:{ *:[i64] }:$vaddr, SReg_128:{ *:[v4i32] }:$srsrc, SCSrc_b32:{ *:[i32] }:$soffset, offset:{ *:[i32] }:$offset)
        GIR_BuildMI, /*InsnID*/0, /*Opcode*/GIMT_Encode2(AMDGPU::BUFFER_ATOMIC_SMAX_X2_VBUFFER_ADDR64_RTN),
        GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/0, // DstI[vdata]
        GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/2, // vdata_in
        GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/1, // vaddr
        GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/0, // srsrc
        GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/2, // soffset
        GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/3, // offset
        GIR_AddImm8, /*InsnID*/0, /*Imm*/1,
        GIR_MergeMemOperands, /*InsnID*/0, /*NumInsns*/1, /*MergeInsnID's*/0,
        GIR_ConstrainSelectedInstOperands, /*InsnID*/0,
        GIR_EraseFromParent, /*InsnID*/0,
        // GIR_Coverage, 4648,
        GIR_Done,
      // Label 2735: @177521
      GIM_Try, /*On fail goto*//*Label 2736*/ GIMT_Encode4(177584), // Rule ID 4645 //
        GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasUnrestrictedSOffset),
        GIM_CheckMemoryAddressSpace, /*MI*/0, /*MMO*/0, /*NumAddrSpace*/3, /*AddrSpace*/1, /*AddrSpace*/4, /*AddrSpace*/6,
        GIM_CheckHasNoUse, /*MI*/0,
        GIM_CheckPointerToAny, /*MI*/0, /*Op*/1, /*SizeInBits*/0,
        GIM_CheckComplexPattern, /*MI*/0, /*Op*/1, /*Renderer*/GIMT_Encode2(0), GIMT_Encode2(GICP_gi_mubuf_offset),
        // (atomic_load_max:{ *:[i64] } (MUBUFOffset:{ *:[iPTR] } v4i32:{ *:[v4i32] }:$srsrc, i32:{ *:[i32] }:$soffset, i32:{ *:[i32] }:$offset), i64:{ *:[i64] }:$vdata_in)<<P:Predicate_atomic_load_max_global_noret_64>>  =>  (BUFFER_ATOMIC_SMAX_X2_OFFSET anonymous_15036:{ *:[i64] }:$vdata_in, SReg_128:{ *:[v4i32] }:$srsrc, SCSrc_b32:{ *:[i32] }:$soffset, offset:{ *:[i32] }:$offset)
        GIR_BuildMI, /*InsnID*/0, /*Opcode*/GIMT_Encode2(AMDGPU::BUFFER_ATOMIC_SMAX_X2_OFFSET),
        GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/2, // vdata_in
        GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/0, // srsrc
        GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/1, // soffset
        GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/2, // offset
        GIR_AddImm8, /*InsnID*/0, /*Imm*/0,
        GIR_MergeMemOperands, /*InsnID*/0, /*NumInsns*/1, /*MergeInsnID's*/0,
        GIR_ConstrainSelectedInstOperands, /*InsnID*/0,
        GIR_EraseFromParent, /*InsnID*/0,
        // GIR_Coverage, 4645,
        GIR_Done,
      // Label 2736: @177584
      GIM_Try, /*On fail goto*//*Label 2737*/ GIMT_Encode4(177644), // Rule ID 4649 //
        GIM_CheckMemoryAddressSpace, /*MI*/0, /*MMO*/0, /*NumAddrSpace*/3, /*AddrSpace*/1, /*AddrSpace*/4, /*AddrSpace*/6,
        GIM_CheckHasNoUse, /*MI*/0,
        GIM_CheckPointerToAny, /*MI*/0, /*Op*/1, /*SizeInBits*/0,
        GIM_CheckComplexPattern, /*MI*/0, /*Op*/1, /*Renderer*/GIMT_Encode2(0), GIMT_Encode2(GICP_gi_mubuf_offset),
        // (atomic_load_max:{ *:[i64] } (MUBUFOffset:{ *:[iPTR] } v4i32:{ *:[v4i32] }:$srsrc, i32:{ *:[i32] }:$soffset, i32:{ *:[i32] }:$offset), i64:{ *:[i64] }:$vdata_in)<<P:Predicate_atomic_load_max_global_noret_64>>  =>  (BUFFER_ATOMIC_SMAX_X2_VBUFFER_OFFSET anonymous_15036:{ *:[i64] }:$vdata_in, SReg_128:{ *:[v4i32] }:$srsrc, SCSrc_b32:{ *:[i32] }:$soffset, offset:{ *:[i32] }:$offset)
        GIR_BuildMI, /*InsnID*/0, /*Opcode*/GIMT_Encode2(AMDGPU::BUFFER_ATOMIC_SMAX_X2_VBUFFER_OFFSET),
        GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/2, // vdata_in
        GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/0, // srsrc
        GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/1, // soffset
        GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/2, // offset
        GIR_AddImm8, /*InsnID*/0, /*Imm*/0,
        GIR_MergeMemOperands, /*InsnID*/0, /*NumInsns*/1, /*MergeInsnID's*/0,
        GIR_ConstrainSelectedInstOperands, /*InsnID*/0,
        GIR_EraseFromParent, /*InsnID*/0,
        // GIR_Coverage, 4649,
        GIR_Done,
      // Label 2737: @177644
      GIM_Try, /*On fail goto*//*Label 2738*/ GIMT_Encode4(177714), // Rule ID 4643 //
        GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasUnrestrictedSOffset),
        GIM_CheckMemoryAddressSpace, /*MI*/0, /*MMO*/0, /*NumAddrSpace*/3, /*AddrSpace*/1, /*AddrSpace*/4, /*AddrSpace*/6,
        GIM_CheckRegBankForClass, /*MI*/0, /*Op*/0, /*RC*/GIMT_Encode2(AMDGPU::AV_64RegClassID),
        GIM_CheckPointerToAny, /*MI*/0, /*Op*/1, /*SizeInBits*/0,
        GIM_CheckComplexPattern, /*MI*/0, /*Op*/1, /*Renderer*/GIMT_Encode2(0), GIMT_Encode2(GICP_gi_mubuf_offset),
        // (atomic_load_max:{ *:[i64] } (MUBUFOffset:{ *:[iPTR] } v4i32:{ *:[v4i32] }:$srsrc, i32:{ *:[i32] }:$soffset, i32:{ *:[i32] }:$offset), i64:{ *:[i64] }:$vdata_in)<<P:Predicate_atomic_load_max_global_64>>  =>  (BUFFER_ATOMIC_SMAX_X2_OFFSET_RTN:{ *:[i64] } anonymous_15036:{ *:[i64] }:$vdata_in, SReg_128:{ *:[v4i32] }:$srsrc, SCSrc_b32:{ *:[i32] }:$soffset, offset:{ *:[i32] }:$offset)
        GIR_BuildMI, /*InsnID*/0, /*Opcode*/GIMT_Encode2(AMDGPU::BUFFER_ATOMIC_SMAX_X2_OFFSET_RTN),
        GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/0, // DstI[vdata]
        GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/2, // vdata_in
        GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/0, // srsrc
        GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/1, // soffset
        GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/2, // offset
        GIR_AddImm8, /*InsnID*/0, /*Imm*/1,
        GIR_MergeMemOperands, /*InsnID*/0, /*NumInsns*/1, /*MergeInsnID's*/0,
        GIR_ConstrainSelectedInstOperands, /*InsnID*/0,
        GIR_EraseFromParent, /*InsnID*/0,
        // GIR_Coverage, 4643,
        GIR_Done,
      // Label 2738: @177714
      GIM_Try, /*On fail goto*//*Label 2739*/ GIMT_Encode4(177781), // Rule ID 4647 //
        GIM_CheckMemoryAddressSpace, /*MI*/0, /*MMO*/0, /*NumAddrSpace*/3, /*AddrSpace*/1, /*AddrSpace*/4, /*AddrSpace*/6,
        GIM_CheckRegBankForClass, /*MI*/0, /*Op*/0, /*RC*/GIMT_Encode2(AMDGPU::AV_64RegClassID),
        GIM_CheckPointerToAny, /*MI*/0, /*Op*/1, /*SizeInBits*/0,
        GIM_CheckComplexPattern, /*MI*/0, /*Op*/1, /*Renderer*/GIMT_Encode2(0), GIMT_Encode2(GICP_gi_mubuf_offset),
        // (atomic_load_max:{ *:[i64] } (MUBUFOffset:{ *:[iPTR] } v4i32:{ *:[v4i32] }:$srsrc, i32:{ *:[i32] }:$soffset, i32:{ *:[i32] }:$offset), i64:{ *:[i64] }:$vdata_in)<<P:Predicate_atomic_load_max_global_64>>  =>  (BUFFER_ATOMIC_SMAX_X2_VBUFFER_OFFSET_RTN:{ *:[i64] } anonymous_15036:{ *:[i64] }:$vdata_in, SReg_128:{ *:[v4i32] }:$srsrc, SCSrc_b32:{ *:[i32] }:$soffset, offset:{ *:[i32] }:$offset)
        GIR_BuildMI, /*InsnID*/0, /*Opcode*/GIMT_Encode2(AMDGPU::BUFFER_ATOMIC_SMAX_X2_VBUFFER_OFFSET_RTN),
        GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/0, // DstI[vdata]
        GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/2, // vdata_in
        GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/0, // srsrc
        GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/1, // soffset
        GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/2, // offset
        GIR_AddImm8, /*InsnID*/0, /*Imm*/1,
        GIR_MergeMemOperands, /*InsnID*/0, /*NumInsns*/1, /*MergeInsnID's*/0,
        GIR_ConstrainSelectedInstOperands, /*InsnID*/0,
        GIR_EraseFromParent, /*InsnID*/0,
        // GIR_Coverage, 4647,
        GIR_Done,
      // Label 2739: @177781
      GIM_Try, /*On fail goto*//*Label 2740*/ GIMT_Encode4(177837), // Rule ID 7040 //
        GIM_CheckFeatures, GIMT_Encode2(GIFBS_LDSRequiresM0Init),
        GIM_CheckMemoryAddressSpace, /*MI*/0, /*MMO*/0, /*NumAddrSpace*/1, /*AddrSpace*/3,
        GIM_CheckHasNoUse, /*MI*/0,
        GIM_CheckPointerToAny, /*MI*/0, /*Op*/1, /*SizeInBits*/0,
        GIM_CheckComplexPattern, /*MI*/0, /*Op*/1, /*Renderer*/GIMT_Encode2(0), GIMT_Encode2(GICP_gi_ds_1addr_1offset),
        // (atomic_load_max_glue:{ *:[i64] } (DS1Addr1Offset:{ *:[iPTR] } i32:{ *:[i32] }:$ptr, i32:{ *:[i32] }:$offset), i64:{ *:[i64] }:$value)<<P:Predicate_atomic_load_max_local_m0_noret_64>>  =>  (DS_MAX_I64 ?:{ *:[i32] }:$ptr, anonymous_15036:{ *:[i64] }:$value, offset:{ *:[i32] }:$offset, 0:{ *:[i1] })
        GIR_BuildMI, /*InsnID*/0, /*Opcode*/GIMT_Encode2(AMDGPU::DS_MAX_I64),
        GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/0, // ptr
        GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/2, // value
        GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/1, // offset
        GIR_AddImm8, /*InsnID*/0, /*Imm*/0,
        GIR_MergeMemOperands, /*InsnID*/0, /*NumInsns*/1, /*MergeInsnID's*/0,
        GIR_ConstrainSelectedInstOperands, /*InsnID*/0,
        GIR_EraseFromParent, /*InsnID*/0,
        // GIR_Coverage, 7040,
        GIR_Done,
      // Label 2740: @177837
      GIM_Try, /*On fail goto*//*Label 2741*/ GIMT_Encode4(177893), // Rule ID 7042 //
        GIM_CheckFeatures, GIMT_Encode2(GIFBS_NotLDSRequiresM0Init),
        GIM_CheckMemoryAddressSpace, /*MI*/0, /*MMO*/0, /*NumAddrSpace*/1, /*AddrSpace*/3,
        GIM_CheckHasNoUse, /*MI*/0,
        GIM_CheckPointerToAny, /*MI*/0, /*Op*/1, /*SizeInBits*/0,
        GIM_CheckComplexPattern, /*MI*/0, /*Op*/1, /*Renderer*/GIMT_Encode2(0), GIMT_Encode2(GICP_gi_ds_1addr_1offset),
        // (atomic_load_max:{ *:[i64] } (DS1Addr1Offset:{ *:[iPTR] } i32:{ *:[i32] }:$ptr, i32:{ *:[i32] }:$offset), i64:{ *:[i64] }:$value)<<P:Predicate_atomic_load_max_local_noret_64>>  =>  (DS_MAX_I64_gfx9 ?:{ *:[i32] }:$ptr, anonymous_15036:{ *:[i64] }:$value, offset:{ *:[i32] }:$offset, 0:{ *:[i1] })
        GIR_BuildMI, /*InsnID*/0, /*Opcode*/GIMT_Encode2(AMDGPU::DS_MAX_I64_gfx9),
        GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/0, // ptr
        GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/2, // value
        GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/1, // offset
        GIR_AddImm8, /*InsnID*/0, /*Imm*/0,
        GIR_MergeMemOperands, /*InsnID*/0, /*NumInsns*/1, /*MergeInsnID's*/0,
        GIR_ConstrainSelectedInstOperands, /*InsnID*/0,
        GIR_EraseFromParent, /*InsnID*/0,
        // GIR_Coverage, 7042,
        GIR_Done,
      // Label 2741: @177893
      GIM_Try, /*On fail goto*//*Label 2742*/ GIMT_Encode4(177949), // Rule ID 7044 //
        GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasGDS),
        GIM_CheckMemoryAddressSpace, /*MI*/0, /*MMO*/0, /*NumAddrSpace*/1, /*AddrSpace*/2,
        GIM_CheckHasNoUse, /*MI*/0,
        GIM_CheckPointerToAny, /*MI*/0, /*Op*/1, /*SizeInBits*/0,
        GIM_CheckComplexPattern, /*MI*/0, /*Op*/1, /*Renderer*/GIMT_Encode2(0), GIMT_Encode2(GICP_gi_ds_1addr_1offset),
        // (atomic_load_max_glue:{ *:[i64] } (DS1Addr1Offset:{ *:[iPTR] } i32:{ *:[i32] }:$ptr, i32:{ *:[i32] }:$offset), i64:{ *:[i64] }:$value)<<P:Predicate_atomic_load_max_region_m0_noret_64>>  =>  (DS_MAX_I64 ?:{ *:[i32] }:$ptr, anonymous_15036:{ *:[i64] }:$value, offset:{ *:[i32] }:$offset, 1:{ *:[i1] })
        GIR_BuildMI, /*InsnID*/0, /*Opcode*/GIMT_Encode2(AMDGPU::DS_MAX_I64),
        GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/0, // ptr
        GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/2, // value
        GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/1, // offset
        GIR_AddImm8, /*InsnID*/0, /*Imm*/1,
        GIR_MergeMemOperands, /*InsnID*/0, /*NumInsns*/1, /*MergeInsnID's*/0,
        GIR_ConstrainSelectedInstOperands, /*InsnID*/0,
        GIR_EraseFromParent, /*InsnID*/0,
        // GIR_Coverage, 7044,
        GIR_Done,
      // Label 2742: @177949
      GIM_Try, /*On fail goto*//*Label 2743*/ GIMT_Encode4(178012), // Rule ID 7039 //
        GIM_CheckFeatures, GIMT_Encode2(GIFBS_LDSRequiresM0Init),
        GIM_CheckMemoryAddressSpace, /*MI*/0, /*MMO*/0, /*NumAddrSpace*/1, /*AddrSpace*/3,
        GIM_CheckRegBankForClass, /*MI*/0, /*Op*/0, /*RC*/GIMT_Encode2(AMDGPU::AV_64RegClassID),
        GIM_CheckPointerToAny, /*MI*/0, /*Op*/1, /*SizeInBits*/0,
        GIM_CheckComplexPattern, /*MI*/0, /*Op*/1, /*Renderer*/GIMT_Encode2(0), GIMT_Encode2(GICP_gi_ds_1addr_1offset),
        // (atomic_load_max_glue:{ *:[i64] } (DS1Addr1Offset:{ *:[iPTR] } i32:{ *:[i32] }:$ptr, i32:{ *:[i32] }:$offset), i64:{ *:[i64] }:$value)<<P:Predicate_atomic_load_max_local_m0_64>>  =>  (DS_MAX_RTN_I64:{ *:[i64] } ?:{ *:[i32] }:$ptr, anonymous_15036:{ *:[i64] }:$value, offset:{ *:[i32] }:$offset, 0:{ *:[i1] })
        GIR_BuildMI, /*InsnID*/0, /*Opcode*/GIMT_Encode2(AMDGPU::DS_MAX_RTN_I64),
        GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/0, // DstI[vdst]
        GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/0, // ptr
        GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/2, // value
        GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/1, // offset
        GIR_AddImm8, /*InsnID*/0, /*Imm*/0,
        GIR_MergeMemOperands, /*InsnID*/0, /*NumInsns*/1, /*MergeInsnID's*/0,
        GIR_ConstrainSelectedInstOperands, /*InsnID*/0,
        GIR_EraseFromParent, /*InsnID*/0,
        // GIR_Coverage, 7039,
        GIR_Done,
      // Label 2743: @178012
      GIM_Try, /*On fail goto*//*Label 2744*/ GIMT_Encode4(178075), // Rule ID 7041 //
        GIM_CheckFeatures, GIMT_Encode2(GIFBS_NotLDSRequiresM0Init),
        GIM_CheckMemoryAddressSpace, /*MI*/0, /*MMO*/0, /*NumAddrSpace*/1, /*AddrSpace*/3,
        GIM_CheckRegBankForClass, /*MI*/0, /*Op*/0, /*RC*/GIMT_Encode2(AMDGPU::AV_64RegClassID),
        GIM_CheckPointerToAny, /*MI*/0, /*Op*/1, /*SizeInBits*/0,
        GIM_CheckComplexPattern, /*MI*/0, /*Op*/1, /*Renderer*/GIMT_Encode2(0), GIMT_Encode2(GICP_gi_ds_1addr_1offset),
        // (atomic_load_max:{ *:[i64] } (DS1Addr1Offset:{ *:[iPTR] } i32:{ *:[i32] }:$ptr, i32:{ *:[i32] }:$offset), i64:{ *:[i64] }:$value)<<P:Predicate_atomic_load_max_local_64>>  =>  (DS_MAX_RTN_I64_gfx9:{ *:[i64] } ?:{ *:[i32] }:$ptr, anonymous_15036:{ *:[i64] }:$value, offset:{ *:[i32] }:$offset, 0:{ *:[i1] })
        GIR_BuildMI, /*InsnID*/0, /*Opcode*/GIMT_Encode2(AMDGPU::DS_MAX_RTN_I64_gfx9),
        GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/0, // DstI[vdst]
        GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/0, // ptr
        GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/2, // value
        GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/1, // offset
        GIR_AddImm8, /*InsnID*/0, /*Imm*/0,
        GIR_MergeMemOperands, /*InsnID*/0, /*NumInsns*/1, /*MergeInsnID's*/0,
        GIR_ConstrainSelectedInstOperands, /*InsnID*/0,
        GIR_EraseFromParent, /*InsnID*/0,
        // GIR_Coverage, 7041,
        GIR_Done,
      // Label 2744: @178075
      GIM_Try, /*On fail goto*//*Label 2745*/ GIMT_Encode4(178138), // Rule ID 7043 //
        GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasGDS),
        GIM_CheckMemoryAddressSpace, /*MI*/0, /*MMO*/0, /*NumAddrSpace*/1, /*AddrSpace*/2,
        GIM_CheckRegBankForClass, /*MI*/0, /*Op*/0, /*RC*/GIMT_Encode2(AMDGPU::AV_64RegClassID),
        GIM_CheckPointerToAny, /*MI*/0, /*Op*/1, /*SizeInBits*/0,
        GIM_CheckComplexPattern, /*MI*/0, /*Op*/1, /*Renderer*/GIMT_Encode2(0), GIMT_Encode2(GICP_gi_ds_1addr_1offset),
        // (atomic_load_max_glue:{ *:[i64] } (DS1Addr1Offset:{ *:[iPTR] } i32:{ *:[i32] }:$ptr, i32:{ *:[i32] }:$offset), i64:{ *:[i64] }:$value)<<P:Predicate_atomic_load_max_region_m0_64>>  =>  (DS_MAX_RTN_I64:{ *:[i64] } ?:{ *:[i32] }:$ptr, anonymous_15036:{ *:[i64] }:$value, offset:{ *:[i32] }:$offset, 1:{ *:[i1] })
        GIR_BuildMI, /*InsnID*/0, /*Opcode*/GIMT_Encode2(AMDGPU::DS_MAX_RTN_I64),
        GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/0, // DstI[vdst]
        GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/0, // ptr
        GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/2, // value
        GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/1, // offset
        GIR_AddImm8, /*InsnID*/0, /*Imm*/1,
        GIR_MergeMemOperands, /*InsnID*/0, /*NumInsns*/1, /*MergeInsnID's*/0,
        GIR_ConstrainSelectedInstOperands, /*InsnID*/0,
        GIR_EraseFromParent, /*InsnID*/0,
        // GIR_Coverage, 7043,
        GIR_Done,
      // Label 2745: @178138
      GIM_Try, /*On fail goto*//*Label 2746*/ GIMT_Encode4(178201), // Rule ID 3223 //
        GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasFlatGlobalInsts),
        GIM_CheckMemoryAddressSpace, /*MI*/0, /*MMO*/0, /*NumAddrSpace*/3, /*AddrSpace*/1, /*AddrSpace*/4, /*AddrSpace*/6,
        GIM_CheckHasNoUse, /*MI*/0,
        GIM_CheckPointerToAny, /*MI*/0, /*Op*/1, /*SizeInBits*/0,
        GIM_CheckComplexPattern, /*MI*/0, /*Op*/1, /*Renderer*/GIMT_Encode2(0), GIMT_Encode2(GICP_gi_global_saddr),
        // (atomic_load_max:{ *:[i64] } (GlobalSAddr:{ *:[iPTR] } SReg_64:{ *:[i64] }:$saddr, VGPR_32:{ *:[i32] }:$voffset, i32:{ *:[i32] }:$offset), i64:{ *:[i64] }:$data)<<P:Predicate_atomic_load_max_global_noret_64>>  =>  (GLOBAL_ATOMIC_SMAX_X2_SADDR ?:{ *:[i32] }:$voffset, anonymous_15036:{ *:[i64] }:$data, ?:{ *:[i64] }:$saddr, ?:{ *:[i32] }:$offset)
        GIR_BuildMI, /*InsnID*/0, /*Opcode*/GIMT_Encode2(AMDGPU::GLOBAL_ATOMIC_SMAX_X2_SADDR),
        GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/1, // voffset
        GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/2, // data
        GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/0, // saddr
        GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/2, // offset
        GIR_AddImm8, /*InsnID*/0, /*Imm*/0,
        GIR_MergeMemOperands, /*InsnID*/0, /*NumInsns*/1, /*MergeInsnID's*/0,
        GIR_ConstrainSelectedInstOperands, /*InsnID*/0,
        GIR_EraseFromParent, /*InsnID*/0,
        // GIR_Coverage, 3223,
        GIR_Done,
      // Label 2746: @178201
      GIM_Try, /*On fail goto*//*Label 2747*/ GIMT_Encode4(178271), // Rule ID 3225 //
        GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasFlatGlobalInsts),
        GIM_CheckMemoryAddressSpace, /*MI*/0, /*MMO*/0, /*NumAddrSpace*/3, /*AddrSpace*/1, /*AddrSpace*/4, /*AddrSpace*/6,
        GIM_CheckRegBankForClass, /*MI*/0, /*Op*/0, /*RC*/GIMT_Encode2(AMDGPU::AV_64RegClassID),
        GIM_CheckPointerToAny, /*MI*/0, /*Op*/1, /*SizeInBits*/0,
        GIM_CheckComplexPattern, /*MI*/0, /*Op*/1, /*Renderer*/GIMT_Encode2(0), GIMT_Encode2(GICP_gi_global_saddr),
        // (atomic_load_max:{ *:[i64] } (GlobalSAddr:{ *:[iPTR] } SReg_64:{ *:[i64] }:$saddr, VGPR_32:{ *:[i32] }:$voffset, i32:{ *:[i32] }:$offset), i64:{ *:[i64] }:$data)<<P:Predicate_atomic_load_max_global_64>>  =>  (GLOBAL_ATOMIC_SMAX_X2_SADDR_RTN:{ *:[i64] } ?:{ *:[i32] }:$voffset, anonymous_15036:{ *:[i64] }:$data, ?:{ *:[i64] }:$saddr, ?:{ *:[i32] }:$offset)
        GIR_BuildMI, /*InsnID*/0, /*Opcode*/GIMT_Encode2(AMDGPU::GLOBAL_ATOMIC_SMAX_X2_SADDR_RTN),
        GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/0, // DstI[vdst]
        GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/1, // voffset
        GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/2, // data
        GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/0, // saddr
        GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/2, // offset
        GIR_AddImm8, /*InsnID*/0, /*Imm*/1,
        GIR_MergeMemOperands, /*InsnID*/0, /*NumInsns*/1, /*MergeInsnID's*/0,
        GIR_ConstrainSelectedInstOperands, /*InsnID*/0,
        GIR_EraseFromParent, /*InsnID*/0,
        // GIR_Coverage, 3225,
        GIR_Done,
      // Label 2747: @178271
      GIM_Try, /*On fail goto*//*Label 2748*/ GIMT_Encode4(178329), // Rule ID 3222 //
        GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasFlatGlobalInsts),
        GIM_CheckMemoryAddressSpace, /*MI*/0, /*MMO*/0, /*NumAddrSpace*/3, /*AddrSpace*/1, /*AddrSpace*/4, /*AddrSpace*/6,
        GIM_CheckHasNoUse, /*MI*/0,
        GIM_CheckPointerToAny, /*MI*/0, /*Op*/1, /*SizeInBits*/0,
        GIM_CheckComplexPattern, /*MI*/0, /*Op*/1, /*Renderer*/GIMT_Encode2(0), GIMT_Encode2(GICP_gi_global_offset),
        // (atomic_load_max:{ *:[i64] } (GlobalOffset:{ *:[iPTR] } i64:{ *:[i64] }:$vaddr, i32:{ *:[i32] }:$offset), i64:{ *:[i64] }:$data)<<P:Predicate_atomic_load_max_global_noret_64>>  =>  (GLOBAL_ATOMIC_SMAX_X2 VReg_64:{ *:[i64] }:$vaddr, anonymous_15036:{ *:[i64] }:$data, ?:{ *:[i32] }:$offset)
        GIR_BuildMI, /*InsnID*/0, /*Opcode*/GIMT_Encode2(AMDGPU::GLOBAL_ATOMIC_SMAX_X2),
        GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/0, // vaddr
        GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/2, // data
        GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/1, // offset
        GIR_AddImm8, /*InsnID*/0, /*Imm*/0,
        GIR_MergeMemOperands, /*InsnID*/0, /*NumInsns*/1, /*MergeInsnID's*/0,
        GIR_ConstrainSelectedInstOperands, /*InsnID*/0,
        GIR_EraseFromParent, /*InsnID*/0,
        // GIR_Coverage, 3222,
        GIR_Done,
      // Label 2748: @178329
      GIM_Try, /*On fail goto*//*Label 2749*/ GIMT_Encode4(178394), // Rule ID 3224 //
        GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasFlatGlobalInsts),
        GIM_CheckMemoryAddressSpace, /*MI*/0, /*MMO*/0, /*NumAddrSpace*/3, /*AddrSpace*/1, /*AddrSpace*/4, /*AddrSpace*/6,
        GIM_CheckRegBankForClass, /*MI*/0, /*Op*/0, /*RC*/GIMT_Encode2(AMDGPU::AV_64RegClassID),
        GIM_CheckPointerToAny, /*MI*/0, /*Op*/1, /*SizeInBits*/0,
        GIM_CheckComplexPattern, /*MI*/0, /*Op*/1, /*Renderer*/GIMT_Encode2(0), GIMT_Encode2(GICP_gi_global_offset),
        // (atomic_load_max:{ *:[i64] } (GlobalOffset:{ *:[iPTR] } i64:{ *:[i64] }:$vaddr, i32:{ *:[i32] }:$offset), i64:{ *:[i64] }:$data)<<P:Predicate_atomic_load_max_global_64>>  =>  (GLOBAL_ATOMIC_SMAX_X2_RTN:{ *:[i64] } VReg_64:{ *:[i64] }:$vaddr, anonymous_15036:{ *:[i64] }:$data, ?:{ *:[i32] }:$offset)
        GIR_BuildMI, /*InsnID*/0, /*Opcode*/GIMT_Encode2(AMDGPU::GLOBAL_ATOMIC_SMAX_X2_RTN),
        GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/0, // DstI[vdst]
        GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/0, // vaddr
        GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/2, // data
        GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/1, // offset
        GIR_AddImm8, /*InsnID*/0, /*Imm*/1,
        GIR_MergeMemOperands, /*InsnID*/0, /*NumInsns*/1, /*MergeInsnID's*/0,
        GIR_ConstrainSelectedInstOperands, /*InsnID*/0,
        GIR_EraseFromParent, /*InsnID*/0,
        // GIR_Coverage, 3224,
        GIR_Done,
      // Label 2749: @178394
      GIM_Try, /*On fail goto*//*Label 2750*/ GIMT_Encode4(178453), // Rule ID 2864 //
        GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasFlatAddressSpace),
        GIM_CheckMemoryAddressSpace, /*MI*/0, /*MMO*/0, /*NumAddrSpace*/4, /*AddrSpace*/0, /*AddrSpace*/1, /*AddrSpace*/4, /*AddrSpace*/6,
        GIM_CheckHasNoUse, /*MI*/0,
        GIM_CheckPointerToAny, /*MI*/0, /*Op*/1, /*SizeInBits*/0,
        GIM_CheckComplexPattern, /*MI*/0, /*Op*/1, /*Renderer*/GIMT_Encode2(0), GIMT_Encode2(GICP_gi_flat_offset),
        // (atomic_load_max:{ *:[i64] } (FlatOffset:{ *:[iPTR] } i64:{ *:[i64] }:$vaddr, i32:{ *:[i32] }:$offset), i64:{ *:[i64] }:$data)<<P:Predicate_atomic_load_max_flat_noret_64>>  =>  (FLAT_ATOMIC_SMAX_X2 VReg_64:{ *:[i64] }:$vaddr, anonymous_15036:{ *:[i64] }:$data, ?:{ *:[i32] }:$offset)
        GIR_BuildMI, /*InsnID*/0, /*Opcode*/GIMT_Encode2(AMDGPU::FLAT_ATOMIC_SMAX_X2),
        GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/0, // vaddr
        GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/2, // data
        GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/1, // offset
        GIR_AddImm8, /*InsnID*/0, /*Imm*/0,
        GIR_MergeMemOperands, /*InsnID*/0, /*NumInsns*/1, /*MergeInsnID's*/0,
        GIR_ConstrainSelectedInstOperands, /*InsnID*/0,
        GIR_EraseFromParent, /*InsnID*/0,
        // GIR_Coverage, 2864,
        GIR_Done,
      // Label 2750: @178453
      GIM_Try, /*On fail goto*//*Label 2751*/ GIMT_Encode4(178511), // Rule ID 2916 //
        GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasFlatAddressSpace),
        GIM_CheckMemoryAddressSpace, /*MI*/0, /*MMO*/0, /*NumAddrSpace*/3, /*AddrSpace*/1, /*AddrSpace*/4, /*AddrSpace*/6,
        GIM_CheckHasNoUse, /*MI*/0,
        GIM_CheckPointerToAny, /*MI*/0, /*Op*/1, /*SizeInBits*/0,
        GIM_CheckComplexPattern, /*MI*/0, /*Op*/1, /*Renderer*/GIMT_Encode2(0), GIMT_Encode2(GICP_gi_flat_offset),
        // (atomic_load_max:{ *:[i64] } (FlatOffset:{ *:[iPTR] } i64:{ *:[i64] }:$vaddr, i32:{ *:[i32] }:$offset), i64:{ *:[i64] }:$data)<<P:Predicate_atomic_load_max_global_noret_64>>  =>  (FLAT_ATOMIC_SMAX_X2 VReg_64:{ *:[i64] }:$vaddr, anonymous_15036:{ *:[i64] }:$data, ?:{ *:[i32] }:$offset)
        GIR_BuildMI, /*InsnID*/0, /*Opcode*/GIMT_Encode2(AMDGPU::FLAT_ATOMIC_SMAX_X2),
        GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/0, // vaddr
        GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/2, // data
        GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/1, // offset
        GIR_AddImm8, /*InsnID*/0, /*Imm*/0,
        GIR_MergeMemOperands, /*InsnID*/0, /*NumInsns*/1, /*MergeInsnID's*/0,
        GIR_ConstrainSelectedInstOperands, /*InsnID*/0,
        GIR_EraseFromParent, /*InsnID*/0,
        // GIR_Coverage, 2916,
        GIR_Done,
      // Label 2751: @178511
      GIM_Try, /*On fail goto*//*Label 2752*/ GIMT_Encode4(178577), // Rule ID 2863 //
        GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasFlatAddressSpace),
        GIM_CheckMemoryAddressSpace, /*MI*/0, /*MMO*/0, /*NumAddrSpace*/4, /*AddrSpace*/0, /*AddrSpace*/1, /*AddrSpace*/4, /*AddrSpace*/6,
        GIM_CheckRegBankForClass, /*MI*/0, /*Op*/0, /*RC*/GIMT_Encode2(AMDGPU::AV_64RegClassID),
        GIM_CheckPointerToAny, /*MI*/0, /*Op*/1, /*SizeInBits*/0,
        GIM_CheckComplexPattern, /*MI*/0, /*Op*/1, /*Renderer*/GIMT_Encode2(0), GIMT_Encode2(GICP_gi_flat_offset),
        // (atomic_load_max:{ *:[i64] } (FlatOffset:{ *:[iPTR] } i64:{ *:[i64] }:$vaddr, i32:{ *:[i32] }:$offset), i64:{ *:[i64] }:$data)<<P:Predicate_atomic_load_max_flat_64>>  =>  (FLAT_ATOMIC_SMAX_X2_RTN:{ *:[i64] } VReg_64:{ *:[i64] }:$vaddr, anonymous_15036:{ *:[i64] }:$data, ?:{ *:[i32] }:$offset)
        GIR_BuildMI, /*InsnID*/0, /*Opcode*/GIMT_Encode2(AMDGPU::FLAT_ATOMIC_SMAX_X2_RTN),
        GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/0, // DstI[vdst]
        GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/0, // vaddr
        GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/2, // data
        GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/1, // offset
        GIR_AddImm8, /*InsnID*/0, /*Imm*/1,
        GIR_MergeMemOperands, /*InsnID*/0, /*NumInsns*/1, /*MergeInsnID's*/0,
        GIR_ConstrainSelectedInstOperands, /*InsnID*/0,
        GIR_EraseFromParent, /*InsnID*/0,
        // GIR_Coverage, 2863,
        GIR_Done,
      // Label 2752: @178577
      GIM_Try, /*On fail goto*//*Label 2753*/ GIMT_Encode4(178642), // Rule ID 2915 //
        GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasFlatAddressSpace),
        GIM_CheckMemoryAddressSpace, /*MI*/0, /*MMO*/0, /*NumAddrSpace*/3, /*AddrSpace*/1, /*AddrSpace*/4, /*AddrSpace*/6,
        GIM_CheckRegBankForClass, /*MI*/0, /*Op*/0, /*RC*/GIMT_Encode2(AMDGPU::AV_64RegClassID),
        GIM_CheckPointerToAny, /*MI*/0, /*Op*/1, /*SizeInBits*/0,
        GIM_CheckComplexPattern, /*MI*/0, /*Op*/1, /*Renderer*/GIMT_Encode2(0), GIMT_Encode2(GICP_gi_flat_offset),
        // (atomic_load_max:{ *:[i64] } (FlatOffset:{ *:[iPTR] } i64:{ *:[i64] }:$vaddr, i32:{ *:[i32] }:$offset), i64:{ *:[i64] }:$data)<<P:Predicate_atomic_load_max_global_64>>  =>  (FLAT_ATOMIC_SMAX_X2_RTN:{ *:[i64] } VReg_64:{ *:[i64] }:$vaddr, anonymous_15036:{ *:[i64] }:$data, ?:{ *:[i32] }:$offset)
        GIR_BuildMI, /*InsnID*/0, /*Opcode*/GIMT_Encode2(AMDGPU::FLAT_ATOMIC_SMAX_X2_RTN),
        GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/0, // DstI[vdst]
        GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/0, // vaddr
        GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/2, // data
        GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/1, // offset
        GIR_AddImm8, /*InsnID*/0, /*Imm*/1,
        GIR_MergeMemOperands, /*InsnID*/0, /*NumInsns*/1, /*MergeInsnID's*/0,
        GIR_ConstrainSelectedInstOperands, /*InsnID*/0,
        GIR_EraseFromParent, /*InsnID*/0,
        // GIR_Coverage, 2915,
        GIR_Done,
      // Label 2753: @178642
      GIM_Reject,
    // Label 2731: @178643
    GIM_Reject,
    // Label 2707: @178644
    GIM_Reject,
    // Label 24: @178645
    GIM_SwitchType, /*MI*/0, /*Op*/0, /*[*/GIMT_Encode2(9), GIMT_Encode2(11), /*)*//*default:*//*Label 2756*/ GIMT_Encode4(181488),
    /*GILLT_s32*//*Label 2754*/ GIMT_Encode4(178664),
    /*GILLT_s64*//*Label 2755*/ GIMT_Encode4(180076),
    // Label 2754: @178664
    GIM_Try, /*On fail goto*//*Label 2757*/ GIMT_Encode4(180075),
      GIM_CheckType, /*MI*/0, /*Op*/2, /*Type*/GILLT_s32,
      GIM_Try, /*On fail goto*//*Label 2758*/ GIMT_Encode4(178741), // Rule ID 4534 //
        GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasUnrestrictedSOffset),
        GIM_CheckMemoryAddressSpace, /*MI*/0, /*MMO*/0, /*NumAddrSpace*/3, /*AddrSpace*/1, /*AddrSpace*/4, /*AddrSpace*/6,
        GIM_CheckHasNoUse, /*MI*/0,
        GIM_CheckPointerToAny, /*MI*/0, /*Op*/1, /*SizeInBits*/0,
        GIM_CheckComplexPattern, /*MI*/0, /*Op*/1, /*Renderer*/GIMT_Encode2(0), GIMT_Encode2(GICP_gi_mubuf_addr64),
        // (atomic_load_min:{ *:[i32] } (MUBUFAddr64:{ *:[iPTR] } v4i32:{ *:[v4i32] }:$srsrc, i64:{ *:[i64] }:$vaddr, i32:{ *:[i32] }:$soffset, i32:{ *:[i32] }:$offset), i32:{ *:[i32] }:$vdata_in)<<P:Predicate_atomic_load_min_global_noret_32>>  =>  (BUFFER_ATOMIC_SMIN_ADDR64 anonymous_15037:{ *:[i32] }:$vdata_in, VReg_64:{ *:[i64] }:$vaddr, SReg_128:{ *:[v4i32] }:$srsrc, SCSrc_b32:{ *:[i32] }:$soffset, offset:{ *:[i32] }:$offset)
        GIR_BuildMI, /*InsnID*/0, /*Opcode*/GIMT_Encode2(AMDGPU::BUFFER_ATOMIC_SMIN_ADDR64),
        GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/2, // vdata_in
        GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/1, // vaddr
        GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/0, // srsrc
        GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/2, // soffset
        GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/3, // offset
        GIR_AddImm8, /*InsnID*/0, /*Imm*/0,
        GIR_MergeMemOperands, /*InsnID*/0, /*NumInsns*/1, /*MergeInsnID's*/0,
        GIR_ConstrainSelectedInstOperands, /*InsnID*/0,
        GIR_EraseFromParent, /*InsnID*/0,
        // GIR_Coverage, 4534,
        GIR_Done,
      // Label 2758: @178741
      GIM_Try, /*On fail goto*//*Label 2759*/ GIMT_Encode4(178806), // Rule ID 4538 //
        GIM_CheckMemoryAddressSpace, /*MI*/0, /*MMO*/0, /*NumAddrSpace*/3, /*AddrSpace*/1, /*AddrSpace*/4, /*AddrSpace*/6,
        GIM_CheckHasNoUse, /*MI*/0,
        GIM_CheckPointerToAny, /*MI*/0, /*Op*/1, /*SizeInBits*/0,
        GIM_CheckComplexPattern, /*MI*/0, /*Op*/1, /*Renderer*/GIMT_Encode2(0), GIMT_Encode2(GICP_gi_mubuf_addr64),
        // (atomic_load_min:{ *:[i32] } (MUBUFAddr64:{ *:[iPTR] } v4i32:{ *:[v4i32] }:$srsrc, i64:{ *:[i64] }:$vaddr, i32:{ *:[i32] }:$soffset, i32:{ *:[i32] }:$offset), i32:{ *:[i32] }:$vdata_in)<<P:Predicate_atomic_load_min_global_noret_32>>  =>  (BUFFER_ATOMIC_SMIN_VBUFFER_ADDR64 anonymous_15037:{ *:[i32] }:$vdata_in, VReg_64:{ *:[i64] }:$vaddr, SReg_128:{ *:[v4i32] }:$srsrc, SCSrc_b32:{ *:[i32] }:$soffset, offset:{ *:[i32] }:$offset)
        GIR_BuildMI, /*InsnID*/0, /*Opcode*/GIMT_Encode2(AMDGPU::BUFFER_ATOMIC_SMIN_VBUFFER_ADDR64),
        GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/2, // vdata_in
        GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/1, // vaddr
        GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/0, // srsrc
        GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/2, // soffset
        GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/3, // offset
        GIR_AddImm8, /*InsnID*/0, /*Imm*/0,
        GIR_MergeMemOperands, /*InsnID*/0, /*NumInsns*/1, /*MergeInsnID's*/0,
        GIR_ConstrainSelectedInstOperands, /*InsnID*/0,
        GIR_EraseFromParent, /*InsnID*/0,
        // GIR_Coverage, 4538,
        GIR_Done,
      // Label 2759: @178806
      GIM_Try, /*On fail goto*//*Label 2760*/ GIMT_Encode4(178881), // Rule ID 4532 //
        GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasUnrestrictedSOffset),
        GIM_CheckMemoryAddressSpace, /*MI*/0, /*MMO*/0, /*NumAddrSpace*/3, /*AddrSpace*/1, /*AddrSpace*/4, /*AddrSpace*/6,
        GIM_CheckRegBankForClass, /*MI*/0, /*Op*/0, /*RC*/GIMT_Encode2(AMDGPU::AV_32RegClassID),
        GIM_CheckPointerToAny, /*MI*/0, /*Op*/1, /*SizeInBits*/0,
        GIM_CheckComplexPattern, /*MI*/0, /*Op*/1, /*Renderer*/GIMT_Encode2(0), GIMT_Encode2(GICP_gi_mubuf_addr64),
        // (atomic_load_min:{ *:[i32] } (MUBUFAddr64:{ *:[iPTR] } v4i32:{ *:[v4i32] }:$srsrc, i64:{ *:[i64] }:$vaddr, i32:{ *:[i32] }:$soffset, i32:{ *:[i32] }:$offset), i32:{ *:[i32] }:$vdata_in)<<P:Predicate_atomic_load_min_global_32>>  =>  (BUFFER_ATOMIC_SMIN_ADDR64_RTN:{ *:[i32] } anonymous_15037:{ *:[i32] }:$vdata_in, VReg_64:{ *:[i64] }:$vaddr, SReg_128:{ *:[v4i32] }:$srsrc, SCSrc_b32:{ *:[i32] }:$soffset, offset:{ *:[i32] }:$offset)
        GIR_BuildMI, /*InsnID*/0, /*Opcode*/GIMT_Encode2(AMDGPU::BUFFER_ATOMIC_SMIN_ADDR64_RTN),
        GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/0, // DstI[vdata]
        GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/2, // vdata_in
        GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/1, // vaddr
        GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/0, // srsrc
        GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/2, // soffset
        GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/3, // offset
        GIR_AddImm8, /*InsnID*/0, /*Imm*/1,
        GIR_MergeMemOperands, /*InsnID*/0, /*NumInsns*/1, /*MergeInsnID's*/0,
        GIR_ConstrainSelectedInstOperands, /*InsnID*/0,
        GIR_EraseFromParent, /*InsnID*/0,
        // GIR_Coverage, 4532,
        GIR_Done,
      // Label 2760: @178881
      GIM_Try, /*On fail goto*//*Label 2761*/ GIMT_Encode4(178953), // Rule ID 4536 //
        GIM_CheckMemoryAddressSpace, /*MI*/0, /*MMO*/0, /*NumAddrSpace*/3, /*AddrSpace*/1, /*AddrSpace*/4, /*AddrSpace*/6,
        GIM_CheckRegBankForClass, /*MI*/0, /*Op*/0, /*RC*/GIMT_Encode2(AMDGPU::AV_32RegClassID),
        GIM_CheckPointerToAny, /*MI*/0, /*Op*/1, /*SizeInBits*/0,
        GIM_CheckComplexPattern, /*MI*/0, /*Op*/1, /*Renderer*/GIMT_Encode2(0), GIMT_Encode2(GICP_gi_mubuf_addr64),
        // (atomic_load_min:{ *:[i32] } (MUBUFAddr64:{ *:[iPTR] } v4i32:{ *:[v4i32] }:$srsrc, i64:{ *:[i64] }:$vaddr, i32:{ *:[i32] }:$soffset, i32:{ *:[i32] }:$offset), i32:{ *:[i32] }:$vdata_in)<<P:Predicate_atomic_load_min_global_32>>  =>  (BUFFER_ATOMIC_SMIN_VBUFFER_ADDR64_RTN:{ *:[i32] } anonymous_15037:{ *:[i32] }:$vdata_in, VReg_64:{ *:[i64] }:$vaddr, SReg_128:{ *:[v4i32] }:$srsrc, SCSrc_b32:{ *:[i32] }:$soffset, offset:{ *:[i32] }:$offset)
        GIR_BuildMI, /*InsnID*/0, /*Opcode*/GIMT_Encode2(AMDGPU::BUFFER_ATOMIC_SMIN_VBUFFER_ADDR64_RTN),
        GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/0, // DstI[vdata]
        GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/2, // vdata_in
        GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/1, // vaddr
        GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/0, // srsrc
        GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/2, // soffset
        GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/3, // offset
        GIR_AddImm8, /*InsnID*/0, /*Imm*/1,
        GIR_MergeMemOperands, /*InsnID*/0, /*NumInsns*/1, /*MergeInsnID's*/0,
        GIR_ConstrainSelectedInstOperands, /*InsnID*/0,
        GIR_EraseFromParent, /*InsnID*/0,
        // GIR_Coverage, 4536,
        GIR_Done,
      // Label 2761: @178953
      GIM_Try, /*On fail goto*//*Label 2762*/ GIMT_Encode4(179016), // Rule ID 4533 //
        GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasUnrestrictedSOffset),
        GIM_CheckMemoryAddressSpace, /*MI*/0, /*MMO*/0, /*NumAddrSpace*/3, /*AddrSpace*/1, /*AddrSpace*/4, /*AddrSpace*/6,
        GIM_CheckHasNoUse, /*MI*/0,
        GIM_CheckPointerToAny, /*MI*/0, /*Op*/1, /*SizeInBits*/0,
        GIM_CheckComplexPattern, /*MI*/0, /*Op*/1, /*Renderer*/GIMT_Encode2(0), GIMT_Encode2(GICP_gi_mubuf_offset),
        // (atomic_load_min:{ *:[i32] } (MUBUFOffset:{ *:[iPTR] } v4i32:{ *:[v4i32] }:$srsrc, i32:{ *:[i32] }:$soffset, i32:{ *:[i32] }:$offset), i32:{ *:[i32] }:$vdata_in)<<P:Predicate_atomic_load_min_global_noret_32>>  =>  (BUFFER_ATOMIC_SMIN_OFFSET anonymous_15037:{ *:[i32] }:$vdata_in, SReg_128:{ *:[v4i32] }:$srsrc, SCSrc_b32:{ *:[i32] }:$soffset, offset:{ *:[i32] }:$offset)
        GIR_BuildMI, /*InsnID*/0, /*Opcode*/GIMT_Encode2(AMDGPU::BUFFER_ATOMIC_SMIN_OFFSET),
        GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/2, // vdata_in
        GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/0, // srsrc
        GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/1, // soffset
        GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/2, // offset
        GIR_AddImm8, /*InsnID*/0, /*Imm*/0,
        GIR_MergeMemOperands, /*InsnID*/0, /*NumInsns*/1, /*MergeInsnID's*/0,
        GIR_ConstrainSelectedInstOperands, /*InsnID*/0,
        GIR_EraseFromParent, /*InsnID*/0,
        // GIR_Coverage, 4533,
        GIR_Done,
      // Label 2762: @179016
      GIM_Try, /*On fail goto*//*Label 2763*/ GIMT_Encode4(179076), // Rule ID 4537 //
        GIM_CheckMemoryAddressSpace, /*MI*/0, /*MMO*/0, /*NumAddrSpace*/3, /*AddrSpace*/1, /*AddrSpace*/4, /*AddrSpace*/6,
        GIM_CheckHasNoUse, /*MI*/0,
        GIM_CheckPointerToAny, /*MI*/0, /*Op*/1, /*SizeInBits*/0,
        GIM_CheckComplexPattern, /*MI*/0, /*Op*/1, /*Renderer*/GIMT_Encode2(0), GIMT_Encode2(GICP_gi_mubuf_offset),
        // (atomic_load_min:{ *:[i32] } (MUBUFOffset:{ *:[iPTR] } v4i32:{ *:[v4i32] }:$srsrc, i32:{ *:[i32] }:$soffset, i32:{ *:[i32] }:$offset), i32:{ *:[i32] }:$vdata_in)<<P:Predicate_atomic_load_min_global_noret_32>>  =>  (BUFFER_ATOMIC_SMIN_VBUFFER_OFFSET anonymous_15037:{ *:[i32] }:$vdata_in, SReg_128:{ *:[v4i32] }:$srsrc, SCSrc_b32:{ *:[i32] }:$soffset, offset:{ *:[i32] }:$offset)
        GIR_BuildMI, /*InsnID*/0, /*Opcode*/GIMT_Encode2(AMDGPU::BUFFER_ATOMIC_SMIN_VBUFFER_OFFSET),
        GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/2, // vdata_in
        GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/0, // srsrc
        GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/1, // soffset
        GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/2, // offset
        GIR_AddImm8, /*InsnID*/0, /*Imm*/0,
        GIR_MergeMemOperands, /*InsnID*/0, /*NumInsns*/1, /*MergeInsnID's*/0,
        GIR_ConstrainSelectedInstOperands, /*InsnID*/0,
        GIR_EraseFromParent, /*InsnID*/0,
        // GIR_Coverage, 4537,
        GIR_Done,
      // Label 2763: @179076
      GIM_Try, /*On fail goto*//*Label 2764*/ GIMT_Encode4(179146), // Rule ID 4531 //
        GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasUnrestrictedSOffset),
        GIM_CheckMemoryAddressSpace, /*MI*/0, /*MMO*/0, /*NumAddrSpace*/3, /*AddrSpace*/1, /*AddrSpace*/4, /*AddrSpace*/6,
        GIM_CheckRegBankForClass, /*MI*/0, /*Op*/0, /*RC*/GIMT_Encode2(AMDGPU::AV_32RegClassID),
        GIM_CheckPointerToAny, /*MI*/0, /*Op*/1, /*SizeInBits*/0,
        GIM_CheckComplexPattern, /*MI*/0, /*Op*/1, /*Renderer*/GIMT_Encode2(0), GIMT_Encode2(GICP_gi_mubuf_offset),
        // (atomic_load_min:{ *:[i32] } (MUBUFOffset:{ *:[iPTR] } v4i32:{ *:[v4i32] }:$srsrc, i32:{ *:[i32] }:$soffset, i32:{ *:[i32] }:$offset), i32:{ *:[i32] }:$vdata_in)<<P:Predicate_atomic_load_min_global_32>>  =>  (BUFFER_ATOMIC_SMIN_OFFSET_RTN:{ *:[i32] } anonymous_15037:{ *:[i32] }:$vdata_in, SReg_128:{ *:[v4i32] }:$srsrc, SCSrc_b32:{ *:[i32] }:$soffset, offset:{ *:[i32] }:$offset)
        GIR_BuildMI, /*InsnID*/0, /*Opcode*/GIMT_Encode2(AMDGPU::BUFFER_ATOMIC_SMIN_OFFSET_RTN),
        GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/0, // DstI[vdata]
        GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/2, // vdata_in
        GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/0, // srsrc
        GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/1, // soffset
        GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/2, // offset
        GIR_AddImm8, /*InsnID*/0, /*Imm*/1,
        GIR_MergeMemOperands, /*InsnID*/0, /*NumInsns*/1, /*MergeInsnID's*/0,
        GIR_ConstrainSelectedInstOperands, /*InsnID*/0,
        GIR_EraseFromParent, /*InsnID*/0,
        // GIR_Coverage, 4531,
        GIR_Done,
      // Label 2764: @179146
      GIM_Try, /*On fail goto*//*Label 2765*/ GIMT_Encode4(179213), // Rule ID 4535 //
        GIM_CheckMemoryAddressSpace, /*MI*/0, /*MMO*/0, /*NumAddrSpace*/3, /*AddrSpace*/1, /*AddrSpace*/4, /*AddrSpace*/6,
        GIM_CheckRegBankForClass, /*MI*/0, /*Op*/0, /*RC*/GIMT_Encode2(AMDGPU::AV_32RegClassID),
        GIM_CheckPointerToAny, /*MI*/0, /*Op*/1, /*SizeInBits*/0,
        GIM_CheckComplexPattern, /*MI*/0, /*Op*/1, /*Renderer*/GIMT_Encode2(0), GIMT_Encode2(GICP_gi_mubuf_offset),
        // (atomic_load_min:{ *:[i32] } (MUBUFOffset:{ *:[iPTR] } v4i32:{ *:[v4i32] }:$srsrc, i32:{ *:[i32] }:$soffset, i32:{ *:[i32] }:$offset), i32:{ *:[i32] }:$vdata_in)<<P:Predicate_atomic_load_min_global_32>>  =>  (BUFFER_ATOMIC_SMIN_VBUFFER_OFFSET_RTN:{ *:[i32] } anonymous_15037:{ *:[i32] }:$vdata_in, SReg_128:{ *:[v4i32] }:$srsrc, SCSrc_b32:{ *:[i32] }:$soffset, offset:{ *:[i32] }:$offset)
        GIR_BuildMI, /*InsnID*/0, /*Opcode*/GIMT_Encode2(AMDGPU::BUFFER_ATOMIC_SMIN_VBUFFER_OFFSET_RTN),
        GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/0, // DstI[vdata]
        GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/2, // vdata_in
        GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/0, // srsrc
        GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/1, // soffset
        GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/2, // offset
        GIR_AddImm8, /*InsnID*/0, /*Imm*/1,
        GIR_MergeMemOperands, /*InsnID*/0, /*NumInsns*/1, /*MergeInsnID's*/0,
        GIR_ConstrainSelectedInstOperands, /*InsnID*/0,
        GIR_EraseFromParent, /*InsnID*/0,
        // GIR_Coverage, 4535,
        GIR_Done,
      // Label 2765: @179213
      GIM_Try, /*On fail goto*//*Label 2766*/ GIMT_Encode4(179269), // Rule ID 6947 //
        GIM_CheckFeatures, GIMT_Encode2(GIFBS_LDSRequiresM0Init),
        GIM_CheckMemoryAddressSpace, /*MI*/0, /*MMO*/0, /*NumAddrSpace*/1, /*AddrSpace*/3,
        GIM_CheckHasNoUse, /*MI*/0,
        GIM_CheckPointerToAny, /*MI*/0, /*Op*/1, /*SizeInBits*/0,
        GIM_CheckComplexPattern, /*MI*/0, /*Op*/1, /*Renderer*/GIMT_Encode2(0), GIMT_Encode2(GICP_gi_ds_1addr_1offset),
        // (atomic_load_min_glue:{ *:[i32] } (DS1Addr1Offset:{ *:[iPTR] } i32:{ *:[i32] }:$ptr, i32:{ *:[i32] }:$offset), i32:{ *:[i32] }:$value)<<P:Predicate_atomic_load_min_local_m0_noret_32>>  =>  (DS_MIN_I32 ?:{ *:[i32] }:$ptr, anonymous_15037:{ *:[i32] }:$value, offset:{ *:[i32] }:$offset, 0:{ *:[i1] })
        GIR_BuildMI, /*InsnID*/0, /*Opcode*/GIMT_Encode2(AMDGPU::DS_MIN_I32),
        GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/0, // ptr
        GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/2, // value
        GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/1, // offset
        GIR_AddImm8, /*InsnID*/0, /*Imm*/0,
        GIR_MergeMemOperands, /*InsnID*/0, /*NumInsns*/1, /*MergeInsnID's*/0,
        GIR_ConstrainSelectedInstOperands, /*InsnID*/0,
        GIR_EraseFromParent, /*InsnID*/0,
        // GIR_Coverage, 6947,
        GIR_Done,
      // Label 2766: @179269
      GIM_Try, /*On fail goto*//*Label 2767*/ GIMT_Encode4(179325), // Rule ID 6949 //
        GIM_CheckFeatures, GIMT_Encode2(GIFBS_NotLDSRequiresM0Init),
        GIM_CheckMemoryAddressSpace, /*MI*/0, /*MMO*/0, /*NumAddrSpace*/1, /*AddrSpace*/3,
        GIM_CheckHasNoUse, /*MI*/0,
        GIM_CheckPointerToAny, /*MI*/0, /*Op*/1, /*SizeInBits*/0,
        GIM_CheckComplexPattern, /*MI*/0, /*Op*/1, /*Renderer*/GIMT_Encode2(0), GIMT_Encode2(GICP_gi_ds_1addr_1offset),
        // (atomic_load_min:{ *:[i32] } (DS1Addr1Offset:{ *:[iPTR] } i32:{ *:[i32] }:$ptr, i32:{ *:[i32] }:$offset), i32:{ *:[i32] }:$value)<<P:Predicate_atomic_load_min_local_noret_32>>  =>  (DS_MIN_I32_gfx9 ?:{ *:[i32] }:$ptr, anonymous_15037:{ *:[i32] }:$value, offset:{ *:[i32] }:$offset, 0:{ *:[i1] })
        GIR_BuildMI, /*InsnID*/0, /*Opcode*/GIMT_Encode2(AMDGPU::DS_MIN_I32_gfx9),
        GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/0, // ptr
        GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/2, // value
        GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/1, // offset
        GIR_AddImm8, /*InsnID*/0, /*Imm*/0,
        GIR_MergeMemOperands, /*InsnID*/0, /*NumInsns*/1, /*MergeInsnID's*/0,
        GIR_ConstrainSelectedInstOperands, /*InsnID*/0,
        GIR_EraseFromParent, /*InsnID*/0,
        // GIR_Coverage, 6949,
        GIR_Done,
      // Label 2767: @179325
      GIM_Try, /*On fail goto*//*Label 2768*/ GIMT_Encode4(179381), // Rule ID 6951 //
        GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasGDS),
        GIM_CheckMemoryAddressSpace, /*MI*/0, /*MMO*/0, /*NumAddrSpace*/1, /*AddrSpace*/2,
        GIM_CheckHasNoUse, /*MI*/0,
        GIM_CheckPointerToAny, /*MI*/0, /*Op*/1, /*SizeInBits*/0,
        GIM_CheckComplexPattern, /*MI*/0, /*Op*/1, /*Renderer*/GIMT_Encode2(0), GIMT_Encode2(GICP_gi_ds_1addr_1offset),
        // (atomic_load_min_glue:{ *:[i32] } (DS1Addr1Offset:{ *:[iPTR] } i32:{ *:[i32] }:$ptr, i32:{ *:[i32] }:$offset), i32:{ *:[i32] }:$value)<<P:Predicate_atomic_load_min_region_m0_noret_32>>  =>  (DS_MIN_I32 ?:{ *:[i32] }:$ptr, anonymous_15037:{ *:[i32] }:$value, offset:{ *:[i32] }:$offset, 1:{ *:[i1] })
        GIR_BuildMI, /*InsnID*/0, /*Opcode*/GIMT_Encode2(AMDGPU::DS_MIN_I32),
        GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/0, // ptr
        GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/2, // value
        GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/1, // offset
        GIR_AddImm8, /*InsnID*/0, /*Imm*/1,
        GIR_MergeMemOperands, /*InsnID*/0, /*NumInsns*/1, /*MergeInsnID's*/0,
        GIR_ConstrainSelectedInstOperands, /*InsnID*/0,
        GIR_EraseFromParent, /*InsnID*/0,
        // GIR_Coverage, 6951,
        GIR_Done,
      // Label 2768: @179381
      GIM_Try, /*On fail goto*//*Label 2769*/ GIMT_Encode4(179444), // Rule ID 6946 //
        GIM_CheckFeatures, GIMT_Encode2(GIFBS_LDSRequiresM0Init),
        GIM_CheckMemoryAddressSpace, /*MI*/0, /*MMO*/0, /*NumAddrSpace*/1, /*AddrSpace*/3,
        GIM_CheckRegBankForClass, /*MI*/0, /*Op*/0, /*RC*/GIMT_Encode2(AMDGPU::AV_32RegClassID),
        GIM_CheckPointerToAny, /*MI*/0, /*Op*/1, /*SizeInBits*/0,
        GIM_CheckComplexPattern, /*MI*/0, /*Op*/1, /*Renderer*/GIMT_Encode2(0), GIMT_Encode2(GICP_gi_ds_1addr_1offset),
        // (atomic_load_min_glue:{ *:[i32] } (DS1Addr1Offset:{ *:[iPTR] } i32:{ *:[i32] }:$ptr, i32:{ *:[i32] }:$offset), i32:{ *:[i32] }:$value)<<P:Predicate_atomic_load_min_local_m0_32>>  =>  (DS_MIN_RTN_I32:{ *:[i32] } ?:{ *:[i32] }:$ptr, anonymous_15037:{ *:[i32] }:$value, offset:{ *:[i32] }:$offset, 0:{ *:[i1] })
        GIR_BuildMI, /*InsnID*/0, /*Opcode*/GIMT_Encode2(AMDGPU::DS_MIN_RTN_I32),
        GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/0, // DstI[vdst]
        GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/0, // ptr
        GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/2, // value
        GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/1, // offset
        GIR_AddImm8, /*InsnID*/0, /*Imm*/0,
        GIR_MergeMemOperands, /*InsnID*/0, /*NumInsns*/1, /*MergeInsnID's*/0,
        GIR_ConstrainSelectedInstOperands, /*InsnID*/0,
        GIR_EraseFromParent, /*InsnID*/0,
        // GIR_Coverage, 6946,
        GIR_Done,
      // Label 2769: @179444
      GIM_Try, /*On fail goto*//*Label 2770*/ GIMT_Encode4(179507), // Rule ID 6948 //
        GIM_CheckFeatures, GIMT_Encode2(GIFBS_NotLDSRequiresM0Init),
        GIM_CheckMemoryAddressSpace, /*MI*/0, /*MMO*/0, /*NumAddrSpace*/1, /*AddrSpace*/3,
        GIM_CheckRegBankForClass, /*MI*/0, /*Op*/0, /*RC*/GIMT_Encode2(AMDGPU::AV_32RegClassID),
        GIM_CheckPointerToAny, /*MI*/0, /*Op*/1, /*SizeInBits*/0,
        GIM_CheckComplexPattern, /*MI*/0, /*Op*/1, /*Renderer*/GIMT_Encode2(0), GIMT_Encode2(GICP_gi_ds_1addr_1offset),
        // (atomic_load_min:{ *:[i32] } (DS1Addr1Offset:{ *:[iPTR] } i32:{ *:[i32] }:$ptr, i32:{ *:[i32] }:$offset), i32:{ *:[i32] }:$value)<<P:Predicate_atomic_load_min_local_32>>  =>  (DS_MIN_RTN_I32_gfx9:{ *:[i32] } ?:{ *:[i32] }:$ptr, anonymous_15037:{ *:[i32] }:$value, offset:{ *:[i32] }:$offset, 0:{ *:[i1] })
        GIR_BuildMI, /*InsnID*/0, /*Opcode*/GIMT_Encode2(AMDGPU::DS_MIN_RTN_I32_gfx9),
        GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/0, // DstI[vdst]
        GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/0, // ptr
        GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/2, // value
        GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/1, // offset
        GIR_AddImm8, /*InsnID*/0, /*Imm*/0,
        GIR_MergeMemOperands, /*InsnID*/0, /*NumInsns*/1, /*MergeInsnID's*/0,
        GIR_ConstrainSelectedInstOperands, /*InsnID*/0,
        GIR_EraseFromParent, /*InsnID*/0,
        // GIR_Coverage, 6948,
        GIR_Done,
      // Label 2770: @179507
      GIM_Try, /*On fail goto*//*Label 2771*/ GIMT_Encode4(179570), // Rule ID 6950 //
        GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasGDS),
        GIM_CheckMemoryAddressSpace, /*MI*/0, /*MMO*/0, /*NumAddrSpace*/1, /*AddrSpace*/2,
        GIM_CheckRegBankForClass, /*MI*/0, /*Op*/0, /*RC*/GIMT_Encode2(AMDGPU::AV_32RegClassID),
        GIM_CheckPointerToAny, /*MI*/0, /*Op*/1, /*SizeInBits*/0,
        GIM_CheckComplexPattern, /*MI*/0, /*Op*/1, /*Renderer*/GIMT_Encode2(0), GIMT_Encode2(GICP_gi_ds_1addr_1offset),
        // (atomic_load_min_glue:{ *:[i32] } (DS1Addr1Offset:{ *:[iPTR] } i32:{ *:[i32] }:$ptr, i32:{ *:[i32] }:$offset), i32:{ *:[i32] }:$value)<<P:Predicate_atomic_load_min_region_m0_32>>  =>  (DS_MIN_RTN_I32:{ *:[i32] } ?:{ *:[i32] }:$ptr, anonymous_15037:{ *:[i32] }:$value, offset:{ *:[i32] }:$offset, 1:{ *:[i1] })
        GIR_BuildMI, /*InsnID*/0, /*Opcode*/GIMT_Encode2(AMDGPU::DS_MIN_RTN_I32),
        GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/0, // DstI[vdst]
        GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/0, // ptr
        GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/2, // value
        GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/1, // offset
        GIR_AddImm8, /*InsnID*/0, /*Imm*/1,
        GIR_MergeMemOperands, /*InsnID*/0, /*NumInsns*/1, /*MergeInsnID's*/0,
        GIR_ConstrainSelectedInstOperands, /*InsnID*/0,
        GIR_EraseFromParent, /*InsnID*/0,
        // GIR_Coverage, 6950,
        GIR_Done,
      // Label 2771: @179570
      GIM_Try, /*On fail goto*//*Label 2772*/ GIMT_Encode4(179633), // Rule ID 3175 //
        GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasFlatGlobalInsts),
        GIM_CheckMemoryAddressSpace, /*MI*/0, /*MMO*/0, /*NumAddrSpace*/3, /*AddrSpace*/1, /*AddrSpace*/4, /*AddrSpace*/6,
        GIM_CheckHasNoUse, /*MI*/0,
        GIM_CheckPointerToAny, /*MI*/0, /*Op*/1, /*SizeInBits*/0,
        GIM_CheckComplexPattern, /*MI*/0, /*Op*/1, /*Renderer*/GIMT_Encode2(0), GIMT_Encode2(GICP_gi_global_saddr),
        // (atomic_load_min:{ *:[i32] } (GlobalSAddr:{ *:[iPTR] } SReg_64:{ *:[i64] }:$saddr, VGPR_32:{ *:[i32] }:$voffset, i32:{ *:[i32] }:$offset), i32:{ *:[i32] }:$data)<<P:Predicate_atomic_load_min_global_noret_32>>  =>  (GLOBAL_ATOMIC_SMIN_SADDR ?:{ *:[i32] }:$voffset, anonymous_15037:{ *:[i32] }:$data, ?:{ *:[i64] }:$saddr, ?:{ *:[i32] }:$offset)
        GIR_BuildMI, /*InsnID*/0, /*Opcode*/GIMT_Encode2(AMDGPU::GLOBAL_ATOMIC_SMIN_SADDR),
        GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/1, // voffset
        GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/2, // data
        GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/0, // saddr
        GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/2, // offset
        GIR_AddImm8, /*InsnID*/0, /*Imm*/0,
        GIR_MergeMemOperands, /*InsnID*/0, /*NumInsns*/1, /*MergeInsnID's*/0,
        GIR_ConstrainSelectedInstOperands, /*InsnID*/0,
        GIR_EraseFromParent, /*InsnID*/0,
        // GIR_Coverage, 3175,
        GIR_Done,
      // Label 2772: @179633
      GIM_Try, /*On fail goto*//*Label 2773*/ GIMT_Encode4(179703), // Rule ID 3177 //
        GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasFlatGlobalInsts),
        GIM_CheckMemoryAddressSpace, /*MI*/0, /*MMO*/0, /*NumAddrSpace*/3, /*AddrSpace*/1, /*AddrSpace*/4, /*AddrSpace*/6,
        GIM_CheckRegBankForClass, /*MI*/0, /*Op*/0, /*RC*/GIMT_Encode2(AMDGPU::AV_32RegClassID),
        GIM_CheckPointerToAny, /*MI*/0, /*Op*/1, /*SizeInBits*/0,
        GIM_CheckComplexPattern, /*MI*/0, /*Op*/1, /*Renderer*/GIMT_Encode2(0), GIMT_Encode2(GICP_gi_global_saddr),
        // (atomic_load_min:{ *:[i32] } (GlobalSAddr:{ *:[iPTR] } SReg_64:{ *:[i64] }:$saddr, VGPR_32:{ *:[i32] }:$voffset, i32:{ *:[i32] }:$offset), i32:{ *:[i32] }:$data)<<P:Predicate_atomic_load_min_global_32>>  =>  (GLOBAL_ATOMIC_SMIN_SADDR_RTN:{ *:[i32] } ?:{ *:[i32] }:$voffset, anonymous_15037:{ *:[i32] }:$data, ?:{ *:[i64] }:$saddr, ?:{ *:[i32] }:$offset)
        GIR_BuildMI, /*InsnID*/0, /*Opcode*/GIMT_Encode2(AMDGPU::GLOBAL_ATOMIC_SMIN_SADDR_RTN),
        GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/0, // DstI[vdst]
        GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/1, // voffset
        GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/2, // data
        GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/0, // saddr
        GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/2, // offset
        GIR_AddImm8, /*InsnID*/0, /*Imm*/1,
        GIR_MergeMemOperands, /*InsnID*/0, /*NumInsns*/1, /*MergeInsnID's*/0,
        GIR_ConstrainSelectedInstOperands, /*InsnID*/0,
        GIR_EraseFromParent, /*InsnID*/0,
        // GIR_Coverage, 3177,
        GIR_Done,
      // Label 2773: @179703
      GIM_Try, /*On fail goto*//*Label 2774*/ GIMT_Encode4(179761), // Rule ID 3174 //
        GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasFlatGlobalInsts),
        GIM_CheckMemoryAddressSpace, /*MI*/0, /*MMO*/0, /*NumAddrSpace*/3, /*AddrSpace*/1, /*AddrSpace*/4, /*AddrSpace*/6,
        GIM_CheckHasNoUse, /*MI*/0,
        GIM_CheckPointerToAny, /*MI*/0, /*Op*/1, /*SizeInBits*/0,
        GIM_CheckComplexPattern, /*MI*/0, /*Op*/1, /*Renderer*/GIMT_Encode2(0), GIMT_Encode2(GICP_gi_global_offset),
        // (atomic_load_min:{ *:[i32] } (GlobalOffset:{ *:[iPTR] } i64:{ *:[i64] }:$vaddr, i32:{ *:[i32] }:$offset), i32:{ *:[i32] }:$data)<<P:Predicate_atomic_load_min_global_noret_32>>  =>  (GLOBAL_ATOMIC_SMIN VReg_64:{ *:[i64] }:$vaddr, anonymous_15037:{ *:[i32] }:$data, ?:{ *:[i32] }:$offset)
        GIR_BuildMI, /*InsnID*/0, /*Opcode*/GIMT_Encode2(AMDGPU::GLOBAL_ATOMIC_SMIN),
        GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/0, // vaddr
        GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/2, // data
        GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/1, // offset
        GIR_AddImm8, /*InsnID*/0, /*Imm*/0,
        GIR_MergeMemOperands, /*InsnID*/0, /*NumInsns*/1, /*MergeInsnID's*/0,
        GIR_ConstrainSelectedInstOperands, /*InsnID*/0,
        GIR_EraseFromParent, /*InsnID*/0,
        // GIR_Coverage, 3174,
        GIR_Done,
      // Label 2774: @179761
      GIM_Try, /*On fail goto*//*Label 2775*/ GIMT_Encode4(179826), // Rule ID 3176 //
        GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasFlatGlobalInsts),
        GIM_CheckMemoryAddressSpace, /*MI*/0, /*MMO*/0, /*NumAddrSpace*/3, /*AddrSpace*/1, /*AddrSpace*/4, /*AddrSpace*/6,
        GIM_CheckRegBankForClass, /*MI*/0, /*Op*/0, /*RC*/GIMT_Encode2(AMDGPU::AV_32RegClassID),
        GIM_CheckPointerToAny, /*MI*/0, /*Op*/1, /*SizeInBits*/0,
        GIM_CheckComplexPattern, /*MI*/0, /*Op*/1, /*Renderer*/GIMT_Encode2(0), GIMT_Encode2(GICP_gi_global_offset),
        // (atomic_load_min:{ *:[i32] } (GlobalOffset:{ *:[iPTR] } i64:{ *:[i64] }:$vaddr, i32:{ *:[i32] }:$offset), i32:{ *:[i32] }:$data)<<P:Predicate_atomic_load_min_global_32>>  =>  (GLOBAL_ATOMIC_SMIN_RTN:{ *:[i32] } VReg_64:{ *:[i64] }:$vaddr, anonymous_15037:{ *:[i32] }:$data, ?:{ *:[i32] }:$offset)
        GIR_BuildMI, /*InsnID*/0, /*Opcode*/GIMT_Encode2(AMDGPU::GLOBAL_ATOMIC_SMIN_RTN),
        GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/0, // DstI[vdst]
        GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/0, // vaddr
        GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/2, // data
        GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/1, // offset
        GIR_AddImm8, /*InsnID*/0, /*Imm*/1,
        GIR_MergeMemOperands, /*InsnID*/0, /*NumInsns*/1, /*MergeInsnID's*/0,
        GIR_ConstrainSelectedInstOperands, /*InsnID*/0,
        GIR_EraseFromParent, /*InsnID*/0,
        // GIR_Coverage, 3176,
        GIR_Done,
      // Label 2775: @179826
      GIM_Try, /*On fail goto*//*Label 2776*/ GIMT_Encode4(179885), // Rule ID 2842 //
        GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasFlatAddressSpace),
        GIM_CheckMemoryAddressSpace, /*MI*/0, /*MMO*/0, /*NumAddrSpace*/4, /*AddrSpace*/0, /*AddrSpace*/1, /*AddrSpace*/4, /*AddrSpace*/6,
        GIM_CheckHasNoUse, /*MI*/0,
        GIM_CheckPointerToAny, /*MI*/0, /*Op*/1, /*SizeInBits*/0,
        GIM_CheckComplexPattern, /*MI*/0, /*Op*/1, /*Renderer*/GIMT_Encode2(0), GIMT_Encode2(GICP_gi_flat_offset),
        // (atomic_load_min:{ *:[i32] } (FlatOffset:{ *:[iPTR] } i64:{ *:[i64] }:$vaddr, i32:{ *:[i32] }:$offset), i32:{ *:[i32] }:$data)<<P:Predicate_atomic_load_min_flat_noret_32>>  =>  (FLAT_ATOMIC_SMIN VReg_64:{ *:[i64] }:$vaddr, anonymous_15037:{ *:[i32] }:$data, ?:{ *:[i32] }:$offset)
        GIR_BuildMI, /*InsnID*/0, /*Opcode*/GIMT_Encode2(AMDGPU::FLAT_ATOMIC_SMIN),
        GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/0, // vaddr
        GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/2, // data
        GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/1, // offset
        GIR_AddImm8, /*InsnID*/0, /*Imm*/0,
        GIR_MergeMemOperands, /*InsnID*/0, /*NumInsns*/1, /*MergeInsnID's*/0,
        GIR_ConstrainSelectedInstOperands, /*InsnID*/0,
        GIR_EraseFromParent, /*InsnID*/0,
        // GIR_Coverage, 2842,
        GIR_Done,
      // Label 2776: @179885
      GIM_Try, /*On fail goto*//*Label 2777*/ GIMT_Encode4(179943), // Rule ID 2894 //
        GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasFlatAddressSpace),
        GIM_CheckMemoryAddressSpace, /*MI*/0, /*MMO*/0, /*NumAddrSpace*/3, /*AddrSpace*/1, /*AddrSpace*/4, /*AddrSpace*/6,
        GIM_CheckHasNoUse, /*MI*/0,
        GIM_CheckPointerToAny, /*MI*/0, /*Op*/1, /*SizeInBits*/0,
        GIM_CheckComplexPattern, /*MI*/0, /*Op*/1, /*Renderer*/GIMT_Encode2(0), GIMT_Encode2(GICP_gi_flat_offset),
        // (atomic_load_min:{ *:[i32] } (FlatOffset:{ *:[iPTR] } i64:{ *:[i64] }:$vaddr, i32:{ *:[i32] }:$offset), i32:{ *:[i32] }:$data)<<P:Predicate_atomic_load_min_global_noret_32>>  =>  (FLAT_ATOMIC_SMIN VReg_64:{ *:[i64] }:$vaddr, anonymous_15037:{ *:[i32] }:$data, ?:{ *:[i32] }:$offset)
        GIR_BuildMI, /*InsnID*/0, /*Opcode*/GIMT_Encode2(AMDGPU::FLAT_ATOMIC_SMIN),
        GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/0, // vaddr
        GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/2, // data
        GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/1, // offset
        GIR_AddImm8, /*InsnID*/0, /*Imm*/0,
        GIR_MergeMemOperands, /*InsnID*/0, /*NumInsns*/1, /*MergeInsnID's*/0,
        GIR_ConstrainSelectedInstOperands, /*InsnID*/0,
        GIR_EraseFromParent, /*InsnID*/0,
        // GIR_Coverage, 2894,
        GIR_Done,
      // Label 2777: @179943
      GIM_Try, /*On fail goto*//*Label 2778*/ GIMT_Encode4(180009), // Rule ID 2841 //
        GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasFlatAddressSpace),
        GIM_CheckMemoryAddressSpace, /*MI*/0, /*MMO*/0, /*NumAddrSpace*/4, /*AddrSpace*/0, /*AddrSpace*/1, /*AddrSpace*/4, /*AddrSpace*/6,
        GIM_CheckRegBankForClass, /*MI*/0, /*Op*/0, /*RC*/GIMT_Encode2(AMDGPU::AV_32RegClassID),
        GIM_CheckPointerToAny, /*MI*/0, /*Op*/1, /*SizeInBits*/0,
        GIM_CheckComplexPattern, /*MI*/0, /*Op*/1, /*Renderer*/GIMT_Encode2(0), GIMT_Encode2(GICP_gi_flat_offset),
        // (atomic_load_min:{ *:[i32] } (FlatOffset:{ *:[iPTR] } i64:{ *:[i64] }:$vaddr, i32:{ *:[i32] }:$offset), i32:{ *:[i32] }:$data)<<P:Predicate_atomic_load_min_flat_32>>  =>  (FLAT_ATOMIC_SMIN_RTN:{ *:[i32] } VReg_64:{ *:[i64] }:$vaddr, anonymous_15037:{ *:[i32] }:$data, ?:{ *:[i32] }:$offset)
        GIR_BuildMI, /*InsnID*/0, /*Opcode*/GIMT_Encode2(AMDGPU::FLAT_ATOMIC_SMIN_RTN),
        GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/0, // DstI[vdst]
        GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/0, // vaddr
        GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/2, // data
        GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/1, // offset
        GIR_AddImm8, /*InsnID*/0, /*Imm*/1,
        GIR_MergeMemOperands, /*InsnID*/0, /*NumInsns*/1, /*MergeInsnID's*/0,
        GIR_ConstrainSelectedInstOperands, /*InsnID*/0,
        GIR_EraseFromParent, /*InsnID*/0,
        // GIR_Coverage, 2841,
        GIR_Done,
      // Label 2778: @180009
      GIM_Try, /*On fail goto*//*Label 2779*/ GIMT_Encode4(180074), // Rule ID 2893 //
        GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasFlatAddressSpace),
        GIM_CheckMemoryAddressSpace, /*MI*/0, /*MMO*/0, /*NumAddrSpace*/3, /*AddrSpace*/1, /*AddrSpace*/4, /*AddrSpace*/6,
        GIM_CheckRegBankForClass, /*MI*/0, /*Op*/0, /*RC*/GIMT_Encode2(AMDGPU::AV_32RegClassID),
        GIM_CheckPointerToAny, /*MI*/0, /*Op*/1, /*SizeInBits*/0,
        GIM_CheckComplexPattern, /*MI*/0, /*Op*/1, /*Renderer*/GIMT_Encode2(0), GIMT_Encode2(GICP_gi_flat_offset),
        // (atomic_load_min:{ *:[i32] } (FlatOffset:{ *:[iPTR] } i64:{ *:[i64] }:$vaddr, i32:{ *:[i32] }:$offset), i32:{ *:[i32] }:$data)<<P:Predicate_atomic_load_min_global_32>>  =>  (FLAT_ATOMIC_SMIN_RTN:{ *:[i32] } VReg_64:{ *:[i64] }:$vaddr, anonymous_15037:{ *:[i32] }:$data, ?:{ *:[i32] }:$offset)
        GIR_BuildMI, /*InsnID*/0, /*Opcode*/GIMT_Encode2(AMDGPU::FLAT_ATOMIC_SMIN_RTN),
        GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/0, // DstI[vdst]
        GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/0, // vaddr
        GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/2, // data
        GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/1, // offset
        GIR_AddImm8, /*InsnID*/0, /*Imm*/1,
        GIR_MergeMemOperands, /*InsnID*/0, /*NumInsns*/1, /*MergeInsnID's*/0,
        GIR_ConstrainSelectedInstOperands, /*InsnID*/0,
        GIR_EraseFromParent, /*InsnID*/0,
        // GIR_Coverage, 2893,
        GIR_Done,
      // Label 2779: @180074
      GIM_Reject,
    // Label 2757: @180075
    GIM_Reject,
    // Label 2755: @180076
    GIM_Try, /*On fail goto*//*Label 2780*/ GIMT_Encode4(181487),
      GIM_CheckType, /*MI*/0, /*Op*/2, /*Type*/GILLT_s64,
      GIM_Try, /*On fail goto*//*Label 2781*/ GIMT_Encode4(180153), // Rule ID 4630 //
        GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasUnrestrictedSOffset),
        GIM_CheckMemoryAddressSpace, /*MI*/0, /*MMO*/0, /*NumAddrSpace*/3, /*AddrSpace*/1, /*AddrSpace*/4, /*AddrSpace*/6,
        GIM_CheckHasNoUse, /*MI*/0,
        GIM_CheckPointerToAny, /*MI*/0, /*Op*/1, /*SizeInBits*/0,
        GIM_CheckComplexPattern, /*MI*/0, /*Op*/1, /*Renderer*/GIMT_Encode2(0), GIMT_Encode2(GICP_gi_mubuf_addr64),
        // (atomic_load_min:{ *:[i64] } (MUBUFAddr64:{ *:[iPTR] } v4i32:{ *:[v4i32] }:$srsrc, i64:{ *:[i64] }:$vaddr, i32:{ *:[i32] }:$soffset, i32:{ *:[i32] }:$offset), i64:{ *:[i64] }:$vdata_in)<<P:Predicate_atomic_load_min_global_noret_64>>  =>  (BUFFER_ATOMIC_SMIN_X2_ADDR64 anonymous_15036:{ *:[i64] }:$vdata_in, VReg_64:{ *:[i64] }:$vaddr, SReg_128:{ *:[v4i32] }:$srsrc, SCSrc_b32:{ *:[i32] }:$soffset, offset:{ *:[i32] }:$offset)
        GIR_BuildMI, /*InsnID*/0, /*Opcode*/GIMT_Encode2(AMDGPU::BUFFER_ATOMIC_SMIN_X2_ADDR64),
        GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/2, // vdata_in
        GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/1, // vaddr
        GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/0, // srsrc
        GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/2, // soffset
        GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/3, // offset
        GIR_AddImm8, /*InsnID*/0, /*Imm*/0,
        GIR_MergeMemOperands, /*InsnID*/0, /*NumInsns*/1, /*MergeInsnID's*/0,
        GIR_ConstrainSelectedInstOperands, /*InsnID*/0,
        GIR_EraseFromParent, /*InsnID*/0,
        // GIR_Coverage, 4630,
        GIR_Done,
      // Label 2781: @180153
      GIM_Try, /*On fail goto*//*Label 2782*/ GIMT_Encode4(180218), // Rule ID 4634 //
        GIM_CheckMemoryAddressSpace, /*MI*/0, /*MMO*/0, /*NumAddrSpace*/3, /*AddrSpace*/1, /*AddrSpace*/4, /*AddrSpace*/6,
        GIM_CheckHasNoUse, /*MI*/0,
        GIM_CheckPointerToAny, /*MI*/0, /*Op*/1, /*SizeInBits*/0,
        GIM_CheckComplexPattern, /*MI*/0, /*Op*/1, /*Renderer*/GIMT_Encode2(0), GIMT_Encode2(GICP_gi_mubuf_addr64),
        // (atomic_load_min:{ *:[i64] } (MUBUFAddr64:{ *:[iPTR] } v4i32:{ *:[v4i32] }:$srsrc, i64:{ *:[i64] }:$vaddr, i32:{ *:[i32] }:$soffset, i32:{ *:[i32] }:$offset), i64:{ *:[i64] }:$vdata_in)<<P:Predicate_atomic_load_min_global_noret_64>>  =>  (BUFFER_ATOMIC_SMIN_X2_VBUFFER_ADDR64 anonymous_15036:{ *:[i64] }:$vdata_in, VReg_64:{ *:[i64] }:$vaddr, SReg_128:{ *:[v4i32] }:$srsrc, SCSrc_b32:{ *:[i32] }:$soffset, offset:{ *:[i32] }:$offset)
        GIR_BuildMI, /*InsnID*/0, /*Opcode*/GIMT_Encode2(AMDGPU::BUFFER_ATOMIC_SMIN_X2_VBUFFER_ADDR64),
        GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/2, // vdata_in
        GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/1, // vaddr
        GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/0, // srsrc
        GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/2, // soffset
        GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/3, // offset
        GIR_AddImm8, /*InsnID*/0, /*Imm*/0,
        GIR_MergeMemOperands, /*InsnID*/0, /*NumInsns*/1, /*MergeInsnID's*/0,
        GIR_ConstrainSelectedInstOperands, /*InsnID*/0,
        GIR_EraseFromParent, /*InsnID*/0,
        // GIR_Coverage, 4634,
        GIR_Done,
      // Label 2782: @180218
      GIM_Try, /*On fail goto*//*Label 2783*/ GIMT_Encode4(180293), // Rule ID 4628 //
        GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasUnrestrictedSOffset),
        GIM_CheckMemoryAddressSpace, /*MI*/0, /*MMO*/0, /*NumAddrSpace*/3, /*AddrSpace*/1, /*AddrSpace*/4, /*AddrSpace*/6,
        GIM_CheckRegBankForClass, /*MI*/0, /*Op*/0, /*RC*/GIMT_Encode2(AMDGPU::AV_64RegClassID),
        GIM_CheckPointerToAny, /*MI*/0, /*Op*/1, /*SizeInBits*/0,
        GIM_CheckComplexPattern, /*MI*/0, /*Op*/1, /*Renderer*/GIMT_Encode2(0), GIMT_Encode2(GICP_gi_mubuf_addr64),
        // (atomic_load_min:{ *:[i64] } (MUBUFAddr64:{ *:[iPTR] } v4i32:{ *:[v4i32] }:$srsrc, i64:{ *:[i64] }:$vaddr, i32:{ *:[i32] }:$soffset, i32:{ *:[i32] }:$offset), i64:{ *:[i64] }:$vdata_in)<<P:Predicate_atomic_load_min_global_64>>  =>  (BUFFER_ATOMIC_SMIN_X2_ADDR64_RTN:{ *:[i64] } anonymous_15036:{ *:[i64] }:$vdata_in, VReg_64:{ *:[i64] }:$vaddr, SReg_128:{ *:[v4i32] }:$srsrc, SCSrc_b32:{ *:[i32] }:$soffset, offset:{ *:[i32] }:$offset)
        GIR_BuildMI, /*InsnID*/0, /*Opcode*/GIMT_Encode2(AMDGPU::BUFFER_ATOMIC_SMIN_X2_ADDR64_RTN),
        GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/0, // DstI[vdata]
        GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/2, // vdata_in
        GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/1, // vaddr
        GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/0, // srsrc
        GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/2, // soffset
        GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/3, // offset
        GIR_AddImm8, /*InsnID*/0, /*Imm*/1,
        GIR_MergeMemOperands, /*InsnID*/0, /*NumInsns*/1, /*MergeInsnID's*/0,
        GIR_ConstrainSelectedInstOperands, /*InsnID*/0,
        GIR_EraseFromParent, /*InsnID*/0,
        // GIR_Coverage, 4628,
        GIR_Done,
      // Label 2783: @180293
      GIM_Try, /*On fail goto*//*Label 2784*/ GIMT_Encode4(180365), // Rule ID 4632 //
        GIM_CheckMemoryAddressSpace, /*MI*/0, /*MMO*/0, /*NumAddrSpace*/3, /*AddrSpace*/1, /*AddrSpace*/4, /*AddrSpace*/6,
        GIM_CheckRegBankForClass, /*MI*/0, /*Op*/0, /*RC*/GIMT_Encode2(AMDGPU::AV_64RegClassID),
        GIM_CheckPointerToAny, /*MI*/0, /*Op*/1, /*SizeInBits*/0,
        GIM_CheckComplexPattern, /*MI*/0, /*Op*/1, /*Renderer*/GIMT_Encode2(0), GIMT_Encode2(GICP_gi_mubuf_addr64),
        // (atomic_load_min:{ *:[i64] } (MUBUFAddr64:{ *:[iPTR] } v4i32:{ *:[v4i32] }:$srsrc, i64:{ *:[i64] }:$vaddr, i32:{ *:[i32] }:$soffset, i32:{ *:[i32] }:$offset), i64:{ *:[i64] }:$vdata_in)<<P:Predicate_atomic_load_min_global_64>>  =>  (BUFFER_ATOMIC_SMIN_X2_VBUFFER_ADDR64_RTN:{ *:[i64] } anonymous_15036:{ *:[i64] }:$vdata_in, VReg_64:{ *:[i64] }:$vaddr, SReg_128:{ *:[v4i32] }:$srsrc, SCSrc_b32:{ *:[i32] }:$soffset, offset:{ *:[i32] }:$offset)
        GIR_BuildMI, /*InsnID*/0, /*Opcode*/GIMT_Encode2(AMDGPU::BUFFER_ATOMIC_SMIN_X2_VBUFFER_ADDR64_RTN),
        GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/0, // DstI[vdata]
        GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/2, // vdata_in
        GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/1, // vaddr
        GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/0, // srsrc
        GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/2, // soffset
        GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/3, // offset
        GIR_AddImm8, /*InsnID*/0, /*Imm*/1,
        GIR_MergeMemOperands, /*InsnID*/0, /*NumInsns*/1, /*MergeInsnID's*/0,
        GIR_ConstrainSelectedInstOperands, /*InsnID*/0,
        GIR_EraseFromParent, /*InsnID*/0,
        // GIR_Coverage, 4632,
        GIR_Done,
      // Label 2784: @180365
      GIM_Try, /*On fail goto*//*Label 2785*/ GIMT_Encode4(180428), // Rule ID 4629 //
        GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasUnrestrictedSOffset),
        GIM_CheckMemoryAddressSpace, /*MI*/0, /*MMO*/0, /*NumAddrSpace*/3, /*AddrSpace*/1, /*AddrSpace*/4, /*AddrSpace*/6,
        GIM_CheckHasNoUse, /*MI*/0,
        GIM_CheckPointerToAny, /*MI*/0, /*Op*/1, /*SizeInBits*/0,
        GIM_CheckComplexPattern, /*MI*/0, /*Op*/1, /*Renderer*/GIMT_Encode2(0), GIMT_Encode2(GICP_gi_mubuf_offset),
        // (atomic_load_min:{ *:[i64] } (MUBUFOffset:{ *:[iPTR] } v4i32:{ *:[v4i32] }:$srsrc, i32:{ *:[i32] }:$soffset, i32:{ *:[i32] }:$offset), i64:{ *:[i64] }:$vdata_in)<<P:Predicate_atomic_load_min_global_noret_64>>  =>  (BUFFER_ATOMIC_SMIN_X2_OFFSET anonymous_15036:{ *:[i64] }:$vdata_in, SReg_128:{ *:[v4i32] }:$srsrc, SCSrc_b32:{ *:[i32] }:$soffset, offset:{ *:[i32] }:$offset)
        GIR_BuildMI, /*InsnID*/0, /*Opcode*/GIMT_Encode2(AMDGPU::BUFFER_ATOMIC_SMIN_X2_OFFSET),
        GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/2, // vdata_in
        GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/0, // srsrc
        GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/1, // soffset
        GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/2, // offset
        GIR_AddImm8, /*InsnID*/0, /*Imm*/0,
        GIR_MergeMemOperands, /*InsnID*/0, /*NumInsns*/1, /*MergeInsnID's*/0,
        GIR_ConstrainSelectedInstOperands, /*InsnID*/0,
        GIR_EraseFromParent, /*InsnID*/0,
        // GIR_Coverage, 4629,
        GIR_Done,
      // Label 2785: @180428
      GIM_Try, /*On fail goto*//*Label 2786*/ GIMT_Encode4(180488), // Rule ID 4633 //
        GIM_CheckMemoryAddressSpace, /*MI*/0, /*MMO*/0, /*NumAddrSpace*/3, /*AddrSpace*/1, /*AddrSpace*/4, /*AddrSpace*/6,
        GIM_CheckHasNoUse, /*MI*/0,
        GIM_CheckPointerToAny, /*MI*/0, /*Op*/1, /*SizeInBits*/0,
        GIM_CheckComplexPattern, /*MI*/0, /*Op*/1, /*Renderer*/GIMT_Encode2(0), GIMT_Encode2(GICP_gi_mubuf_offset),
        // (atomic_load_min:{ *:[i64] } (MUBUFOffset:{ *:[iPTR] } v4i32:{ *:[v4i32] }:$srsrc, i32:{ *:[i32] }:$soffset, i32:{ *:[i32] }:$offset), i64:{ *:[i64] }:$vdata_in)<<P:Predicate_atomic_load_min_global_noret_64>>  =>  (BUFFER_ATOMIC_SMIN_X2_VBUFFER_OFFSET anonymous_15036:{ *:[i64] }:$vdata_in, SReg_128:{ *:[v4i32] }:$srsrc, SCSrc_b32:{ *:[i32] }:$soffset, offset:{ *:[i32] }:$offset)
        GIR_BuildMI, /*InsnID*/0, /*Opcode*/GIMT_Encode2(AMDGPU::BUFFER_ATOMIC_SMIN_X2_VBUFFER_OFFSET),
        GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/2, // vdata_in
        GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/0, // srsrc
        GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/1, // soffset
        GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/2, // offset
        GIR_AddImm8, /*InsnID*/0, /*Imm*/0,
        GIR_MergeMemOperands, /*InsnID*/0, /*NumInsns*/1, /*MergeInsnID's*/0,
        GIR_ConstrainSelectedInstOperands, /*InsnID*/0,
        GIR_EraseFromParent, /*InsnID*/0,
        // GIR_Coverage, 4633,
        GIR_Done,
      // Label 2786: @180488
      GIM_Try, /*On fail goto*//*Label 2787*/ GIMT_Encode4(180558), // Rule ID 4627 //
        GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasUnrestrictedSOffset),
        GIM_CheckMemoryAddressSpace, /*MI*/0, /*MMO*/0, /*NumAddrSpace*/3, /*AddrSpace*/1, /*AddrSpace*/4, /*AddrSpace*/6,
        GIM_CheckRegBankForClass, /*MI*/0, /*Op*/0, /*RC*/GIMT_Encode2(AMDGPU::AV_64RegClassID),
        GIM_CheckPointerToAny, /*MI*/0, /*Op*/1, /*SizeInBits*/0,
        GIM_CheckComplexPattern, /*MI*/0, /*Op*/1, /*Renderer*/GIMT_Encode2(0), GIMT_Encode2(GICP_gi_mubuf_offset),
        // (atomic_load_min:{ *:[i64] } (MUBUFOffset:{ *:[iPTR] } v4i32:{ *:[v4i32] }:$srsrc, i32:{ *:[i32] }:$soffset, i32:{ *:[i32] }:$offset), i64:{ *:[i64] }:$vdata_in)<<P:Predicate_atomic_load_min_global_64>>  =>  (BUFFER_ATOMIC_SMIN_X2_OFFSET_RTN:{ *:[i64] } anonymous_15036:{ *:[i64] }:$vdata_in, SReg_128:{ *:[v4i32] }:$srsrc, SCSrc_b32:{ *:[i32] }:$soffset, offset:{ *:[i32] }:$offset)
        GIR_BuildMI, /*InsnID*/0, /*Opcode*/GIMT_Encode2(AMDGPU::BUFFER_ATOMIC_SMIN_X2_OFFSET_RTN),
        GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/0, // DstI[vdata]
        GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/2, // vdata_in
        GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/0, // srsrc
        GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/1, // soffset
        GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/2, // offset
        GIR_AddImm8, /*InsnID*/0, /*Imm*/1,
        GIR_MergeMemOperands, /*InsnID*/0, /*NumInsns*/1, /*MergeInsnID's*/0,
        GIR_ConstrainSelectedInstOperands, /*InsnID*/0,
        GIR_EraseFromParent, /*InsnID*/0,
        // GIR_Coverage, 4627,
        GIR_Done,
      // Label 2787: @180558
      GIM_Try, /*On fail goto*//*Label 2788*/ GIMT_Encode4(180625), // Rule ID 4631 //
        GIM_CheckMemoryAddressSpace, /*MI*/0, /*MMO*/0, /*NumAddrSpace*/3, /*AddrSpace*/1, /*AddrSpace*/4, /*AddrSpace*/6,
        GIM_CheckRegBankForClass, /*MI*/0, /*Op*/0, /*RC*/GIMT_Encode2(AMDGPU::AV_64RegClassID),
        GIM_CheckPointerToAny, /*MI*/0, /*Op*/1, /*SizeInBits*/0,
        GIM_CheckComplexPattern, /*MI*/0, /*Op*/1, /*Renderer*/GIMT_Encode2(0), GIMT_Encode2(GICP_gi_mubuf_offset),
        // (atomic_load_min:{ *:[i64] } (MUBUFOffset:{ *:[iPTR] } v4i32:{ *:[v4i32] }:$srsrc, i32:{ *:[i32] }:$soffset, i32:{ *:[i32] }:$offset), i64:{ *:[i64] }:$vdata_in)<<P:Predicate_atomic_load_min_global_64>>  =>  (BUFFER_ATOMIC_SMIN_X2_VBUFFER_OFFSET_RTN:{ *:[i64] } anonymous_15036:{ *:[i64] }:$vdata_in, SReg_128:{ *:[v4i32] }:$srsrc, SCSrc_b32:{ *:[i32] }:$soffset, offset:{ *:[i32] }:$offset)
        GIR_BuildMI, /*InsnID*/0, /*Opcode*/GIMT_Encode2(AMDGPU::BUFFER_ATOMIC_SMIN_X2_VBUFFER_OFFSET_RTN),
        GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/0, // DstI[vdata]
        GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/2, // vdata_in
        GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/0, // srsrc
        GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/1, // soffset
        GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/2, // offset
        GIR_AddImm8, /*InsnID*/0, /*Imm*/1,
        GIR_MergeMemOperands, /*InsnID*/0, /*NumInsns*/1, /*MergeInsnID's*/0,
        GIR_ConstrainSelectedInstOperands, /*InsnID*/0,
        GIR_EraseFromParent, /*InsnID*/0,
        // GIR_Coverage, 4631,
        GIR_Done,
      // Label 2788: @180625
      GIM_Try, /*On fail goto*//*Label 2789*/ GIMT_Encode4(180681), // Rule ID 7034 //
        GIM_CheckFeatures, GIMT_Encode2(GIFBS_LDSRequiresM0Init),
        GIM_CheckMemoryAddressSpace, /*MI*/0, /*MMO*/0, /*NumAddrSpace*/1, /*AddrSpace*/3,
        GIM_CheckHasNoUse, /*MI*/0,
        GIM_CheckPointerToAny, /*MI*/0, /*Op*/1, /*SizeInBits*/0,
        GIM_CheckComplexPattern, /*MI*/0, /*Op*/1, /*Renderer*/GIMT_Encode2(0), GIMT_Encode2(GICP_gi_ds_1addr_1offset),
        // (atomic_load_min_glue:{ *:[i64] } (DS1Addr1Offset:{ *:[iPTR] } i32:{ *:[i32] }:$ptr, i32:{ *:[i32] }:$offset), i64:{ *:[i64] }:$value)<<P:Predicate_atomic_load_min_local_m0_noret_64>>  =>  (DS_MIN_I64 ?:{ *:[i32] }:$ptr, anonymous_15036:{ *:[i64] }:$value, offset:{ *:[i32] }:$offset, 0:{ *:[i1] })
        GIR_BuildMI, /*InsnID*/0, /*Opcode*/GIMT_Encode2(AMDGPU::DS_MIN_I64),
        GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/0, // ptr
        GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/2, // value
        GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/1, // offset
        GIR_AddImm8, /*InsnID*/0, /*Imm*/0,
        GIR_MergeMemOperands, /*InsnID*/0, /*NumInsns*/1, /*MergeInsnID's*/0,
        GIR_ConstrainSelectedInstOperands, /*InsnID*/0,
        GIR_EraseFromParent, /*InsnID*/0,
        // GIR_Coverage, 7034,
        GIR_Done,
      // Label 2789: @180681
      GIM_Try, /*On fail goto*//*Label 2790*/ GIMT_Encode4(180737), // Rule ID 7036 //
        GIM_CheckFeatures, GIMT_Encode2(GIFBS_NotLDSRequiresM0Init),
        GIM_CheckMemoryAddressSpace, /*MI*/0, /*MMO*/0, /*NumAddrSpace*/1, /*AddrSpace*/3,
        GIM_CheckHasNoUse, /*MI*/0,
        GIM_CheckPointerToAny, /*MI*/0, /*Op*/1, /*SizeInBits*/0,
        GIM_CheckComplexPattern, /*MI*/0, /*Op*/1, /*Renderer*/GIMT_Encode2(0), GIMT_Encode2(GICP_gi_ds_1addr_1offset),
        // (atomic_load_min:{ *:[i64] } (DS1Addr1Offset:{ *:[iPTR] } i32:{ *:[i32] }:$ptr, i32:{ *:[i32] }:$offset), i64:{ *:[i64] }:$value)<<P:Predicate_atomic_load_min_local_noret_64>>  =>  (DS_MIN_I64_gfx9 ?:{ *:[i32] }:$ptr, anonymous_15036:{ *:[i64] }:$value, offset:{ *:[i32] }:$offset, 0:{ *:[i1] })
        GIR_BuildMI, /*InsnID*/0, /*Opcode*/GIMT_Encode2(AMDGPU::DS_MIN_I64_gfx9),
        GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/0, // ptr
        GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/2, // value
        GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/1, // offset
        GIR_AddImm8, /*InsnID*/0, /*Imm*/0,
        GIR_MergeMemOperands, /*InsnID*/0, /*NumInsns*/1, /*MergeInsnID's*/0,
        GIR_ConstrainSelectedInstOperands, /*InsnID*/0,
        GIR_EraseFromParent, /*InsnID*/0,
        // GIR_Coverage, 7036,
        GIR_Done,
      // Label 2790: @180737
      GIM_Try, /*On fail goto*//*Label 2791*/ GIMT_Encode4(180793), // Rule ID 7038 //
        GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasGDS),
        GIM_CheckMemoryAddressSpace, /*MI*/0, /*MMO*/0, /*NumAddrSpace*/1, /*AddrSpace*/2,
        GIM_CheckHasNoUse, /*MI*/0,
        GIM_CheckPointerToAny, /*MI*/0, /*Op*/1, /*SizeInBits*/0,
        GIM_CheckComplexPattern, /*MI*/0, /*Op*/1, /*Renderer*/GIMT_Encode2(0), GIMT_Encode2(GICP_gi_ds_1addr_1offset),
        // (atomic_load_min_glue:{ *:[i64] } (DS1Addr1Offset:{ *:[iPTR] } i32:{ *:[i32] }:$ptr, i32:{ *:[i32] }:$offset), i64:{ *:[i64] }:$value)<<P:Predicate_atomic_load_min_region_m0_noret_64>>  =>  (DS_MIN_I64 ?:{ *:[i32] }:$ptr, anonymous_15036:{ *:[i64] }:$value, offset:{ *:[i32] }:$offset, 1:{ *:[i1] })
        GIR_BuildMI, /*InsnID*/0, /*Opcode*/GIMT_Encode2(AMDGPU::DS_MIN_I64),
        GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/0, // ptr
        GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/2, // value
        GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/1, // offset
        GIR_AddImm8, /*InsnID*/0, /*Imm*/1,
        GIR_MergeMemOperands, /*InsnID*/0, /*NumInsns*/1, /*MergeInsnID's*/0,
        GIR_ConstrainSelectedInstOperands, /*InsnID*/0,
        GIR_EraseFromParent, /*InsnID*/0,
        // GIR_Coverage, 7038,
        GIR_Done,
      // Label 2791: @180793
      GIM_Try, /*On fail goto*//*Label 2792*/ GIMT_Encode4(180856), // Rule ID 7033 //
        GIM_CheckFeatures, GIMT_Encode2(GIFBS_LDSRequiresM0Init),
        GIM_CheckMemoryAddressSpace, /*MI*/0, /*MMO*/0, /*NumAddrSpace*/1, /*AddrSpace*/3,
        GIM_CheckRegBankForClass, /*MI*/0, /*Op*/0, /*RC*/GIMT_Encode2(AMDGPU::AV_64RegClassID),
        GIM_CheckPointerToAny, /*MI*/0, /*Op*/1, /*SizeInBits*/0,
        GIM_CheckComplexPattern, /*MI*/0, /*Op*/1, /*Renderer*/GIMT_Encode2(0), GIMT_Encode2(GICP_gi_ds_1addr_1offset),
        // (atomic_load_min_glue:{ *:[i64] } (DS1Addr1Offset:{ *:[iPTR] } i32:{ *:[i32] }:$ptr, i32:{ *:[i32] }:$offset), i64:{ *:[i64] }:$value)<<P:Predicate_atomic_load_min_local_m0_64>>  =>  (DS_MIN_RTN_I64:{ *:[i64] } ?:{ *:[i32] }:$ptr, anonymous_15036:{ *:[i64] }:$value, offset:{ *:[i32] }:$offset, 0:{ *:[i1] })
        GIR_BuildMI, /*InsnID*/0, /*Opcode*/GIMT_Encode2(AMDGPU::DS_MIN_RTN_I64),
        GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/0, // DstI[vdst]
        GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/0, // ptr
        GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/2, // value
        GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/1, // offset
        GIR_AddImm8, /*InsnID*/0, /*Imm*/0,
        GIR_MergeMemOperands, /*InsnID*/0, /*NumInsns*/1, /*MergeInsnID's*/0,
        GIR_ConstrainSelectedInstOperands, /*InsnID*/0,
        GIR_EraseFromParent, /*InsnID*/0,
        // GIR_Coverage, 7033,
        GIR_Done,
      // Label 2792: @180856
      GIM_Try, /*On fail goto*//*Label 2793*/ GIMT_Encode4(180919), // Rule ID 7035 //
        GIM_CheckFeatures, GIMT_Encode2(GIFBS_NotLDSRequiresM0Init),
        GIM_CheckMemoryAddressSpace, /*MI*/0, /*MMO*/0, /*NumAddrSpace*/1, /*AddrSpace*/3,
        GIM_CheckRegBankForClass, /*MI*/0, /*Op*/0, /*RC*/GIMT_Encode2(AMDGPU::AV_64RegClassID),
        GIM_CheckPointerToAny, /*MI*/0, /*Op*/1, /*SizeInBits*/0,
        GIM_CheckComplexPattern, /*MI*/0, /*Op*/1, /*Renderer*/GIMT_Encode2(0), GIMT_Encode2(GICP_gi_ds_1addr_1offset),
        // (atomic_load_min:{ *:[i64] } (DS1Addr1Offset:{ *:[iPTR] } i32:{ *:[i32] }:$ptr, i32:{ *:[i32] }:$offset), i64:{ *:[i64] }:$value)<<P:Predicate_atomic_load_min_local_64>>  =>  (DS_MIN_RTN_I64_gfx9:{ *:[i64] } ?:{ *:[i32] }:$ptr, anonymous_15036:{ *:[i64] }:$value, offset:{ *:[i32] }:$offset, 0:{ *:[i1] })
        GIR_BuildMI, /*InsnID*/0, /*Opcode*/GIMT_Encode2(AMDGPU::DS_MIN_RTN_I64_gfx9),
        GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/0, // DstI[vdst]
        GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/0, // ptr
        GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/2, // value
        GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/1, // offset
        GIR_AddImm8, /*InsnID*/0, /*Imm*/0,
        GIR_MergeMemOperands, /*InsnID*/0, /*NumInsns*/1, /*MergeInsnID's*/0,
        GIR_ConstrainSelectedInstOperands, /*InsnID*/0,
        GIR_EraseFromParent, /*InsnID*/0,
        // GIR_Coverage, 7035,
        GIR_Done,
      // Label 2793: @180919
      GIM_Try, /*On fail goto*//*Label 2794*/ GIMT_Encode4(180982), // Rule ID 7037 //
        GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasGDS),
        GIM_CheckMemoryAddressSpace, /*MI*/0, /*MMO*/0, /*NumAddrSpace*/1, /*AddrSpace*/2,
        GIM_CheckRegBankForClass, /*MI*/0, /*Op*/0, /*RC*/GIMT_Encode2(AMDGPU::AV_64RegClassID),
        GIM_CheckPointerToAny, /*MI*/0, /*Op*/1, /*SizeInBits*/0,
        GIM_CheckComplexPattern, /*MI*/0, /*Op*/1, /*Renderer*/GIMT_Encode2(0), GIMT_Encode2(GICP_gi_ds_1addr_1offset),
        // (atomic_load_min_glue:{ *:[i64] } (DS1Addr1Offset:{ *:[iPTR] } i32:{ *:[i32] }:$ptr, i32:{ *:[i32] }:$offset), i64:{ *:[i64] }:$value)<<P:Predicate_atomic_load_min_region_m0_64>>  =>  (DS_MIN_RTN_I64:{ *:[i64] } ?:{ *:[i32] }:$ptr, anonymous_15036:{ *:[i64] }:$value, offset:{ *:[i32] }:$offset, 1:{ *:[i1] })
        GIR_BuildMI, /*InsnID*/0, /*Opcode*/GIMT_Encode2(AMDGPU::DS_MIN_RTN_I64),
        GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/0, // DstI[vdst]
        GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/0, // ptr
        GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/2, // value
        GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/1, // offset
        GIR_AddImm8, /*InsnID*/0, /*Imm*/1,
        GIR_MergeMemOperands, /*InsnID*/0, /*NumInsns*/1, /*MergeInsnID's*/0,
        GIR_ConstrainSelectedInstOperands, /*InsnID*/0,
        GIR_EraseFromParent, /*InsnID*/0,
        // GIR_Coverage, 7037,
        GIR_Done,
      // Label 2794: @180982
      GIM_Try, /*On fail goto*//*Label 2795*/ GIMT_Encode4(181045), // Rule ID 3231 //
        GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasFlatGlobalInsts),
        GIM_CheckMemoryAddressSpace, /*MI*/0, /*MMO*/0, /*NumAddrSpace*/3, /*AddrSpace*/1, /*AddrSpace*/4, /*AddrSpace*/6,
        GIM_CheckHasNoUse, /*MI*/0,
        GIM_CheckPointerToAny, /*MI*/0, /*Op*/1, /*SizeInBits*/0,
        GIM_CheckComplexPattern, /*MI*/0, /*Op*/1, /*Renderer*/GIMT_Encode2(0), GIMT_Encode2(GICP_gi_global_saddr),
        // (atomic_load_min:{ *:[i64] } (GlobalSAddr:{ *:[iPTR] } SReg_64:{ *:[i64] }:$saddr, VGPR_32:{ *:[i32] }:$voffset, i32:{ *:[i32] }:$offset), i64:{ *:[i64] }:$data)<<P:Predicate_atomic_load_min_global_noret_64>>  =>  (GLOBAL_ATOMIC_SMIN_X2_SADDR ?:{ *:[i32] }:$voffset, anonymous_15036:{ *:[i64] }:$data, ?:{ *:[i64] }:$saddr, ?:{ *:[i32] }:$offset)
        GIR_BuildMI, /*InsnID*/0, /*Opcode*/GIMT_Encode2(AMDGPU::GLOBAL_ATOMIC_SMIN_X2_SADDR),
        GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/1, // voffset
        GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/2, // data
        GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/0, // saddr
        GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/2, // offset
        GIR_AddImm8, /*InsnID*/0, /*Imm*/0,
        GIR_MergeMemOperands, /*InsnID*/0, /*NumInsns*/1, /*MergeInsnID's*/0,
        GIR_ConstrainSelectedInstOperands, /*InsnID*/0,
        GIR_EraseFromParent, /*InsnID*/0,
        // GIR_Coverage, 3231,
        GIR_Done,
      // Label 2795: @181045
      GIM_Try, /*On fail goto*//*Label 2796*/ GIMT_Encode4(181115), // Rule ID 3233 //
        GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasFlatGlobalInsts),
        GIM_CheckMemoryAddressSpace, /*MI*/0, /*MMO*/0, /*NumAddrSpace*/3, /*AddrSpace*/1, /*AddrSpace*/4, /*AddrSpace*/6,
        GIM_CheckRegBankForClass, /*MI*/0, /*Op*/0, /*RC*/GIMT_Encode2(AMDGPU::AV_64RegClassID),
        GIM_CheckPointerToAny, /*MI*/0, /*Op*/1, /*SizeInBits*/0,
        GIM_CheckComplexPattern, /*MI*/0, /*Op*/1, /*Renderer*/GIMT_Encode2(0), GIMT_Encode2(GICP_gi_global_saddr),
        // (atomic_load_min:{ *:[i64] } (GlobalSAddr:{ *:[iPTR] } SReg_64:{ *:[i64] }:$saddr, VGPR_32:{ *:[i32] }:$voffset, i32:{ *:[i32] }:$offset), i64:{ *:[i64] }:$data)<<P:Predicate_atomic_load_min_global_64>>  =>  (GLOBAL_ATOMIC_SMIN_X2_SADDR_RTN:{ *:[i64] } ?:{ *:[i32] }:$voffset, anonymous_15036:{ *:[i64] }:$data, ?:{ *:[i64] }:$saddr, ?:{ *:[i32] }:$offset)
        GIR_BuildMI, /*InsnID*/0, /*Opcode*/GIMT_Encode2(AMDGPU::GLOBAL_ATOMIC_SMIN_X2_SADDR_RTN),
        GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/0, // DstI[vdst]
        GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/1, // voffset
        GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/2, // data
        GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/0, // saddr
        GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/2, // offset
        GIR_AddImm8, /*InsnID*/0, /*Imm*/1,
        GIR_MergeMemOperands, /*InsnID*/0, /*NumInsns*/1, /*MergeInsnID's*/0,
        GIR_ConstrainSelectedInstOperands, /*InsnID*/0,
        GIR_EraseFromParent, /*InsnID*/0,
        // GIR_Coverage, 3233,
        GIR_Done,
      // Label 2796: @181115
      GIM_Try, /*On fail goto*//*Label 2797*/ GIMT_Encode4(181173), // Rule ID 3230 //
        GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasFlatGlobalInsts),
        GIM_CheckMemoryAddressSpace, /*MI*/0, /*MMO*/0, /*NumAddrSpace*/3, /*AddrSpace*/1, /*AddrSpace*/4, /*AddrSpace*/6,
        GIM_CheckHasNoUse, /*MI*/0,
        GIM_CheckPointerToAny, /*MI*/0, /*Op*/1, /*SizeInBits*/0,
        GIM_CheckComplexPattern, /*MI*/0, /*Op*/1, /*Renderer*/GIMT_Encode2(0), GIMT_Encode2(GICP_gi_global_offset),
        // (atomic_load_min:{ *:[i64] } (GlobalOffset:{ *:[iPTR] } i64:{ *:[i64] }:$vaddr, i32:{ *:[i32] }:$offset), i64:{ *:[i64] }:$data)<<P:Predicate_atomic_load_min_global_noret_64>>  =>  (GLOBAL_ATOMIC_SMIN_X2 VReg_64:{ *:[i64] }:$vaddr, anonymous_15036:{ *:[i64] }:$data, ?:{ *:[i32] }:$offset)
        GIR_BuildMI, /*InsnID*/0, /*Opcode*/GIMT_Encode2(AMDGPU::GLOBAL_ATOMIC_SMIN_X2),
        GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/0, // vaddr
        GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/2, // data
        GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/1, // offset
        GIR_AddImm8, /*InsnID*/0, /*Imm*/0,
        GIR_MergeMemOperands, /*InsnID*/0, /*NumInsns*/1, /*MergeInsnID's*/0,
        GIR_ConstrainSelectedInstOperands, /*InsnID*/0,
        GIR_EraseFromParent, /*InsnID*/0,
        // GIR_Coverage, 3230,
        GIR_Done,
      // Label 2797: @181173
      GIM_Try, /*On fail goto*//*Label 2798*/ GIMT_Encode4(181238), // Rule ID 3232 //
        GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasFlatGlobalInsts),
        GIM_CheckMemoryAddressSpace, /*MI*/0, /*MMO*/0, /*NumAddrSpace*/3, /*AddrSpace*/1, /*AddrSpace*/4, /*AddrSpace*/6,
        GIM_CheckRegBankForClass, /*MI*/0, /*Op*/0, /*RC*/GIMT_Encode2(AMDGPU::AV_64RegClassID),
        GIM_CheckPointerToAny, /*MI*/0, /*Op*/1, /*SizeInBits*/0,
        GIM_CheckComplexPattern, /*MI*/0, /*Op*/1, /*Renderer*/GIMT_Encode2(0), GIMT_Encode2(GICP_gi_global_offset),
        // (atomic_load_min:{ *:[i64] } (GlobalOffset:{ *:[iPTR] } i64:{ *:[i64] }:$vaddr, i32:{ *:[i32] }:$offset), i64:{ *:[i64] }:$data)<<P:Predicate_atomic_load_min_global_64>>  =>  (GLOBAL_ATOMIC_SMIN_X2_RTN:{ *:[i64] } VReg_64:{ *:[i64] }:$vaddr, anonymous_15036:{ *:[i64] }:$data, ?:{ *:[i32] }:$offset)
        GIR_BuildMI, /*InsnID*/0, /*Opcode*/GIMT_Encode2(AMDGPU::GLOBAL_ATOMIC_SMIN_X2_RTN),
        GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/0, // DstI[vdst]
        GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/0, // vaddr
        GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/2, // data
        GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/1, // offset
        GIR_AddImm8, /*InsnID*/0, /*Imm*/1,
        GIR_MergeMemOperands, /*InsnID*/0, /*NumInsns*/1, /*MergeInsnID's*/0,
        GIR_ConstrainSelectedInstOperands, /*InsnID*/0,
        GIR_EraseFromParent, /*InsnID*/0,
        // GIR_Coverage, 3232,
        GIR_Done,
      // Label 2798: @181238
      GIM_Try, /*On fail goto*//*Label 2799*/ GIMT_Encode4(181297), // Rule ID 2868 //
        GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasFlatAddressSpace),
        GIM_CheckMemoryAddressSpace, /*MI*/0, /*MMO*/0, /*NumAddrSpace*/4, /*AddrSpace*/0, /*AddrSpace*/1, /*AddrSpace*/4, /*AddrSpace*/6,
        GIM_CheckHasNoUse, /*MI*/0,
        GIM_CheckPointerToAny, /*MI*/0, /*Op*/1, /*SizeInBits*/0,
        GIM_CheckComplexPattern, /*MI*/0, /*Op*/1, /*Renderer*/GIMT_Encode2(0), GIMT_Encode2(GICP_gi_flat_offset),
        // (atomic_load_min:{ *:[i64] } (FlatOffset:{ *:[iPTR] } i64:{ *:[i64] }:$vaddr, i32:{ *:[i32] }:$offset), i64:{ *:[i64] }:$data)<<P:Predicate_atomic_load_min_flat_noret_64>>  =>  (FLAT_ATOMIC_SMIN_X2 VReg_64:{ *:[i64] }:$vaddr, anonymous_15036:{ *:[i64] }:$data, ?:{ *:[i32] }:$offset)
        GIR_BuildMI, /*InsnID*/0, /*Opcode*/GIMT_Encode2(AMDGPU::FLAT_ATOMIC_SMIN_X2),
        GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/0, // vaddr
        GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/2, // data
        GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/1, // offset
        GIR_AddImm8, /*InsnID*/0, /*Imm*/0,
        GIR_MergeMemOperands, /*InsnID*/0, /*NumInsns*/1, /*MergeInsnID's*/0,
        GIR_ConstrainSelectedInstOperands, /*InsnID*/0,
        GIR_EraseFromParent, /*InsnID*/0,
        // GIR_Coverage, 2868,
        GIR_Done,
      // Label 2799: @181297
      GIM_Try, /*On fail goto*//*Label 2800*/ GIMT_Encode4(181355), // Rule ID 2920 //
        GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasFlatAddressSpace),
        GIM_CheckMemoryAddressSpace, /*MI*/0, /*MMO*/0, /*NumAddrSpace*/3, /*AddrSpace*/1, /*AddrSpace*/4, /*AddrSpace*/6,
        GIM_CheckHasNoUse, /*MI*/0,
        GIM_CheckPointerToAny, /*MI*/0, /*Op*/1, /*SizeInBits*/0,
        GIM_CheckComplexPattern, /*MI*/0, /*Op*/1, /*Renderer*/GIMT_Encode2(0), GIMT_Encode2(GICP_gi_flat_offset),
        // (atomic_load_min:{ *:[i64] } (FlatOffset:{ *:[iPTR] } i64:{ *:[i64] }:$vaddr, i32:{ *:[i32] }:$offset), i64:{ *:[i64] }:$data)<<P:Predicate_atomic_load_min_global_noret_64>>  =>  (FLAT_ATOMIC_SMIN_X2 VReg_64:{ *:[i64] }:$vaddr, anonymous_15036:{ *:[i64] }:$data, ?:{ *:[i32] }:$offset)
        GIR_BuildMI, /*InsnID*/0, /*Opcode*/GIMT_Encode2(AMDGPU::FLAT_ATOMIC_SMIN_X2),
        GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/0, // vaddr
        GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/2, // data
        GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/1, // offset
        GIR_AddImm8, /*InsnID*/0, /*Imm*/0,
        GIR_MergeMemOperands, /*InsnID*/0, /*NumInsns*/1, /*MergeInsnID's*/0,
        GIR_ConstrainSelectedInstOperands, /*InsnID*/0,
        GIR_EraseFromParent, /*InsnID*/0,
        // GIR_Coverage, 2920,
        GIR_Done,
      // Label 2800: @181355
      GIM_Try, /*On fail goto*//*Label 2801*/ GIMT_Encode4(181421), // Rule ID 2867 //
        GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasFlatAddressSpace),
        GIM_CheckMemoryAddressSpace, /*MI*/0, /*MMO*/0, /*NumAddrSpace*/4, /*AddrSpace*/0, /*AddrSpace*/1, /*AddrSpace*/4, /*AddrSpace*/6,
        GIM_CheckRegBankForClass, /*MI*/0, /*Op*/0, /*RC*/GIMT_Encode2(AMDGPU::AV_64RegClassID),
        GIM_CheckPointerToAny, /*MI*/0, /*Op*/1, /*SizeInBits*/0,
        GIM_CheckComplexPattern, /*MI*/0, /*Op*/1, /*Renderer*/GIMT_Encode2(0), GIMT_Encode2(GICP_gi_flat_offset),
        // (atomic_load_min:{ *:[i64] } (FlatOffset:{ *:[iPTR] } i64:{ *:[i64] }:$vaddr, i32:{ *:[i32] }:$offset), i64:{ *:[i64] }:$data)<<P:Predicate_atomic_load_min_flat_64>>  =>  (FLAT_ATOMIC_SMIN_X2_RTN:{ *:[i64] } VReg_64:{ *:[i64] }:$vaddr, anonymous_15036:{ *:[i64] }:$data, ?:{ *:[i32] }:$offset)
        GIR_BuildMI, /*InsnID*/0, /*Opcode*/GIMT_Encode2(AMDGPU::FLAT_ATOMIC_SMIN_X2_RTN),
        GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/0, // DstI[vdst]
        GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/0, // vaddr
        GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/2, // data
        GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/1, // offset
        GIR_AddImm8, /*InsnID*/0, /*Imm*/1,
        GIR_MergeMemOperands, /*InsnID*/0, /*NumInsns*/1, /*MergeInsnID's*/0,
        GIR_ConstrainSelectedInstOperands, /*InsnID*/0,
        GIR_EraseFromParent, /*InsnID*/0,
        // GIR_Coverage, 2867,
        GIR_Done,
      // Label 2801: @181421
      GIM_Try, /*On fail goto*//*Label 2802*/ GIMT_Encode4(181486), // Rule ID 2919 //
        GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasFlatAddressSpace),
        GIM_CheckMemoryAddressSpace, /*MI*/0, /*MMO*/0, /*NumAddrSpace*/3, /*AddrSpace*/1, /*AddrSpace*/4, /*AddrSpace*/6,
        GIM_CheckRegBankForClass, /*MI*/0, /*Op*/0, /*RC*/GIMT_Encode2(AMDGPU::AV_64RegClassID),
        GIM_CheckPointerToAny, /*MI*/0, /*Op*/1, /*SizeInBits*/0,
        GIM_CheckComplexPattern, /*MI*/0, /*Op*/1, /*Renderer*/GIMT_Encode2(0), GIMT_Encode2(GICP_gi_flat_offset),
        // (atomic_load_min:{ *:[i64] } (FlatOffset:{ *:[iPTR] } i64:{ *:[i64] }:$vaddr, i32:{ *:[i32] }:$offset), i64:{ *:[i64] }:$data)<<P:Predicate_atomic_load_min_global_64>>  =>  (FLAT_ATOMIC_SMIN_X2_RTN:{ *:[i64] } VReg_64:{ *:[i64] }:$vaddr, anonymous_15036:{ *:[i64] }:$data, ?:{ *:[i32] }:$offset)
        GIR_BuildMI, /*InsnID*/0, /*Opcode*/GIMT_Encode2(AMDGPU::FLAT_ATOMIC_SMIN_X2_RTN),
        GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/0, // DstI[vdst]
        GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/0, // vaddr
        GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/2, // data
        GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/1, // offset
        GIR_AddImm8, /*InsnID*/0, /*Imm*/1,
        GIR_MergeMemOperands, /*InsnID*/0, /*NumInsns*/1, /*MergeInsnID's*/0,
        GIR_ConstrainSelectedInstOperands, /*InsnID*/0,
        GIR_EraseFromParent, /*InsnID*/0,
        // GIR_Coverage, 2919,
        GIR_Done,
      // Label 2802: @181486
      GIM_Reject,
    // Label 2780: @181487
    GIM_Reject,
    // Label 2756: @181488
    GIM_Reject,
    // Label 25: @181489
    GIM_SwitchType, /*MI*/0, /*Op*/0, /*[*/GIMT_Encode2(9), GIMT_Encode2(11), /*)*//*default:*//*Label 2805*/ GIMT_Encode4(184332),
    /*GILLT_s32*//*Label 2803*/ GIMT_Encode4(181508),
    /*GILLT_s64*//*Label 2804*/ GIMT_Encode4(182920),
    // Label 2803: @181508
    GIM_Try, /*On fail goto*//*Label 2806*/ GIMT_Encode4(182919),
      GIM_CheckType, /*MI*/0, /*Op*/2, /*Type*/GILLT_s32,
      GIM_Try, /*On fail goto*//*Label 2807*/ GIMT_Encode4(181585), // Rule ID 4558 //
        GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasUnrestrictedSOffset),
        GIM_CheckMemoryAddressSpace, /*MI*/0, /*MMO*/0, /*NumAddrSpace*/3, /*AddrSpace*/1, /*AddrSpace*/4, /*AddrSpace*/6,
        GIM_CheckHasNoUse, /*MI*/0,
        GIM_CheckPointerToAny, /*MI*/0, /*Op*/1, /*SizeInBits*/0,
        GIM_CheckComplexPattern, /*MI*/0, /*Op*/1, /*Renderer*/GIMT_Encode2(0), GIMT_Encode2(GICP_gi_mubuf_addr64),
        // (atomic_load_umax:{ *:[i32] } (MUBUFAddr64:{ *:[iPTR] } v4i32:{ *:[v4i32] }:$srsrc, i64:{ *:[i64] }:$vaddr, i32:{ *:[i32] }:$soffset, i32:{ *:[i32] }:$offset), i32:{ *:[i32] }:$vdata_in)<<P:Predicate_atomic_load_umax_global_noret_32>>  =>  (BUFFER_ATOMIC_UMAX_ADDR64 anonymous_15037:{ *:[i32] }:$vdata_in, VReg_64:{ *:[i64] }:$vaddr, SReg_128:{ *:[v4i32] }:$srsrc, SCSrc_b32:{ *:[i32] }:$soffset, offset:{ *:[i32] }:$offset)
        GIR_BuildMI, /*InsnID*/0, /*Opcode*/GIMT_Encode2(AMDGPU::BUFFER_ATOMIC_UMAX_ADDR64),
        GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/2, // vdata_in
        GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/1, // vaddr
        GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/0, // srsrc
        GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/2, // soffset
        GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/3, // offset
        GIR_AddImm8, /*InsnID*/0, /*Imm*/0,
        GIR_MergeMemOperands, /*InsnID*/0, /*NumInsns*/1, /*MergeInsnID's*/0,
        GIR_ConstrainSelectedInstOperands, /*InsnID*/0,
        GIR_EraseFromParent, /*InsnID*/0,
        // GIR_Coverage, 4558,
        GIR_Done,
      // Label 2807: @181585
      GIM_Try, /*On fail goto*//*Label 2808*/ GIMT_Encode4(181650), // Rule ID 4562 //
        GIM_CheckMemoryAddressSpace, /*MI*/0, /*MMO*/0, /*NumAddrSpace*/3, /*AddrSpace*/1, /*AddrSpace*/4, /*AddrSpace*/6,
        GIM_CheckHasNoUse, /*MI*/0,
        GIM_CheckPointerToAny, /*MI*/0, /*Op*/1, /*SizeInBits*/0,
        GIM_CheckComplexPattern, /*MI*/0, /*Op*/1, /*Renderer*/GIMT_Encode2(0), GIMT_Encode2(GICP_gi_mubuf_addr64),
        // (atomic_load_umax:{ *:[i32] } (MUBUFAddr64:{ *:[iPTR] } v4i32:{ *:[v4i32] }:$srsrc, i64:{ *:[i64] }:$vaddr, i32:{ *:[i32] }:$soffset, i32:{ *:[i32] }:$offset), i32:{ *:[i32] }:$vdata_in)<<P:Predicate_atomic_load_umax_global_noret_32>>  =>  (BUFFER_ATOMIC_UMAX_VBUFFER_ADDR64 anonymous_15037:{ *:[i32] }:$vdata_in, VReg_64:{ *:[i64] }:$vaddr, SReg_128:{ *:[v4i32] }:$srsrc, SCSrc_b32:{ *:[i32] }:$soffset, offset:{ *:[i32] }:$offset)
        GIR_BuildMI, /*InsnID*/0, /*Opcode*/GIMT_Encode2(AMDGPU::BUFFER_ATOMIC_UMAX_VBUFFER_ADDR64),
        GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/2, // vdata_in
        GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/1, // vaddr
        GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/0, // srsrc
        GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/2, // soffset
        GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/3, // offset
        GIR_AddImm8, /*InsnID*/0, /*Imm*/0,
        GIR_MergeMemOperands, /*InsnID*/0, /*NumInsns*/1, /*MergeInsnID's*/0,
        GIR_ConstrainSelectedInstOperands, /*InsnID*/0,
        GIR_EraseFromParent, /*InsnID*/0,
        // GIR_Coverage, 4562,
        GIR_Done,
      // Label 2808: @181650
      GIM_Try, /*On fail goto*//*Label 2809*/ GIMT_Encode4(181725), // Rule ID 4556 //
        GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasUnrestrictedSOffset),
        GIM_CheckMemoryAddressSpace, /*MI*/0, /*MMO*/0, /*NumAddrSpace*/3, /*AddrSpace*/1, /*AddrSpace*/4, /*AddrSpace*/6,
        GIM_CheckRegBankForClass, /*MI*/0, /*Op*/0, /*RC*/GIMT_Encode2(AMDGPU::AV_32RegClassID),
        GIM_CheckPointerToAny, /*MI*/0, /*Op*/1, /*SizeInBits*/0,
        GIM_CheckComplexPattern, /*MI*/0, /*Op*/1, /*Renderer*/GIMT_Encode2(0), GIMT_Encode2(GICP_gi_mubuf_addr64),
        // (atomic_load_umax:{ *:[i32] } (MUBUFAddr64:{ *:[iPTR] } v4i32:{ *:[v4i32] }:$srsrc, i64:{ *:[i64] }:$vaddr, i32:{ *:[i32] }:$soffset, i32:{ *:[i32] }:$offset), i32:{ *:[i32] }:$vdata_in)<<P:Predicate_atomic_load_umax_global_32>>  =>  (BUFFER_ATOMIC_UMAX_ADDR64_RTN:{ *:[i32] } anonymous_15037:{ *:[i32] }:$vdata_in, VReg_64:{ *:[i64] }:$vaddr, SReg_128:{ *:[v4i32] }:$srsrc, SCSrc_b32:{ *:[i32] }:$soffset, offset:{ *:[i32] }:$offset)
        GIR_BuildMI, /*InsnID*/0, /*Opcode*/GIMT_Encode2(AMDGPU::BUFFER_ATOMIC_UMAX_ADDR64_RTN),
        GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/0, // DstI[vdata]
        GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/2, // vdata_in
        GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/1, // vaddr
        GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/0, // srsrc
        GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/2, // soffset
        GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/3, // offset
        GIR_AddImm8, /*InsnID*/0, /*Imm*/1,
        GIR_MergeMemOperands, /*InsnID*/0, /*NumInsns*/1, /*MergeInsnID's*/0,
        GIR_ConstrainSelectedInstOperands, /*InsnID*/0,
        GIR_EraseFromParent, /*InsnID*/0,
        // GIR_Coverage, 4556,
        GIR_Done,
      // Label 2809: @181725
      GIM_Try, /*On fail goto*//*Label 2810*/ GIMT_Encode4(181797), // Rule ID 4560 //
        GIM_CheckMemoryAddressSpace, /*MI*/0, /*MMO*/0, /*NumAddrSpace*/3, /*AddrSpace*/1, /*AddrSpace*/4, /*AddrSpace*/6,
        GIM_CheckRegBankForClass, /*MI*/0, /*Op*/0, /*RC*/GIMT_Encode2(AMDGPU::AV_32RegClassID),
        GIM_CheckPointerToAny, /*MI*/0, /*Op*/1, /*SizeInBits*/0,
        GIM_CheckComplexPattern, /*MI*/0, /*Op*/1, /*Renderer*/GIMT_Encode2(0), GIMT_Encode2(GICP_gi_mubuf_addr64),
        // (atomic_load_umax:{ *:[i32] } (MUBUFAddr64:{ *:[iPTR] } v4i32:{ *:[v4i32] }:$srsrc, i64:{ *:[i64] }:$vaddr, i32:{ *:[i32] }:$soffset, i32:{ *:[i32] }:$offset), i32:{ *:[i32] }:$vdata_in)<<P:Predicate_atomic_load_umax_global_32>>  =>  (BUFFER_ATOMIC_UMAX_VBUFFER_ADDR64_RTN:{ *:[i32] } anonymous_15037:{ *:[i32] }:$vdata_in, VReg_64:{ *:[i64] }:$vaddr, SReg_128:{ *:[v4i32] }:$srsrc, SCSrc_b32:{ *:[i32] }:$soffset, offset:{ *:[i32] }:$offset)
        GIR_BuildMI, /*InsnID*/0, /*Opcode*/GIMT_Encode2(AMDGPU::BUFFER_ATOMIC_UMAX_VBUFFER_ADDR64_RTN),
        GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/0, // DstI[vdata]
        GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/2, // vdata_in
        GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/1, // vaddr
        GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/0, // srsrc
        GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/2, // soffset
        GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/3, // offset
        GIR_AddImm8, /*InsnID*/0, /*Imm*/1,
        GIR_MergeMemOperands, /*InsnID*/0, /*NumInsns*/1, /*MergeInsnID's*/0,
        GIR_ConstrainSelectedInstOperands, /*InsnID*/0,
        GIR_EraseFromParent, /*InsnID*/0,
        // GIR_Coverage, 4560,
        GIR_Done,
      // Label 2810: @181797
      GIM_Try, /*On fail goto*//*Label 2811*/ GIMT_Encode4(181860), // Rule ID 4557 //
        GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasUnrestrictedSOffset),
        GIM_CheckMemoryAddressSpace, /*MI*/0, /*MMO*/0, /*NumAddrSpace*/3, /*AddrSpace*/1, /*AddrSpace*/4, /*AddrSpace*/6,
        GIM_CheckHasNoUse, /*MI*/0,
        GIM_CheckPointerToAny, /*MI*/0, /*Op*/1, /*SizeInBits*/0,
        GIM_CheckComplexPattern, /*MI*/0, /*Op*/1, /*Renderer*/GIMT_Encode2(0), GIMT_Encode2(GICP_gi_mubuf_offset),
        // (atomic_load_umax:{ *:[i32] } (MUBUFOffset:{ *:[iPTR] } v4i32:{ *:[v4i32] }:$srsrc, i32:{ *:[i32] }:$soffset, i32:{ *:[i32] }:$offset), i32:{ *:[i32] }:$vdata_in)<<P:Predicate_atomic_load_umax_global_noret_32>>  =>  (BUFFER_ATOMIC_UMAX_OFFSET anonymous_15037:{ *:[i32] }:$vdata_in, SReg_128:{ *:[v4i32] }:$srsrc, SCSrc_b32:{ *:[i32] }:$soffset, offset:{ *:[i32] }:$offset)
        GIR_BuildMI, /*InsnID*/0, /*Opcode*/GIMT_Encode2(AMDGPU::BUFFER_ATOMIC_UMAX_OFFSET),
        GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/2, // vdata_in
        GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/0, // srsrc
        GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/1, // soffset
        GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/2, // offset
        GIR_AddImm8, /*InsnID*/0, /*Imm*/0,
        GIR_MergeMemOperands, /*InsnID*/0, /*NumInsns*/1, /*MergeInsnID's*/0,
        GIR_ConstrainSelectedInstOperands, /*InsnID*/0,
        GIR_EraseFromParent, /*InsnID*/0,
        // GIR_Coverage, 4557,
        GIR_Done,
      // Label 2811: @181860
      GIM_Try, /*On fail goto*//*Label 2812*/ GIMT_Encode4(181920), // Rule ID 4561 //
        GIM_CheckMemoryAddressSpace, /*MI*/0, /*MMO*/0, /*NumAddrSpace*/3, /*AddrSpace*/1, /*AddrSpace*/4, /*AddrSpace*/6,
        GIM_CheckHasNoUse, /*MI*/0,
        GIM_CheckPointerToAny, /*MI*/0, /*Op*/1, /*SizeInBits*/0,
        GIM_CheckComplexPattern, /*MI*/0, /*Op*/1, /*Renderer*/GIMT_Encode2(0), GIMT_Encode2(GICP_gi_mubuf_offset),
        // (atomic_load_umax:{ *:[i32] } (MUBUFOffset:{ *:[iPTR] } v4i32:{ *:[v4i32] }:$srsrc, i32:{ *:[i32] }:$soffset, i32:{ *:[i32] }:$offset), i32:{ *:[i32] }:$vdata_in)<<P:Predicate_atomic_load_umax_global_noret_32>>  =>  (BUFFER_ATOMIC_UMAX_VBUFFER_OFFSET anonymous_15037:{ *:[i32] }:$vdata_in, SReg_128:{ *:[v4i32] }:$srsrc, SCSrc_b32:{ *:[i32] }:$soffset, offset:{ *:[i32] }:$offset)
        GIR_BuildMI, /*InsnID*/0, /*Opcode*/GIMT_Encode2(AMDGPU::BUFFER_ATOMIC_UMAX_VBUFFER_OFFSET),
        GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/2, // vdata_in
        GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/0, // srsrc
        GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/1, // soffset
        GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/2, // offset
        GIR_AddImm8, /*InsnID*/0, /*Imm*/0,
        GIR_MergeMemOperands, /*InsnID*/0, /*NumInsns*/1, /*MergeInsnID's*/0,
        GIR_ConstrainSelectedInstOperands, /*InsnID*/0,
        GIR_EraseFromParent, /*InsnID*/0,
        // GIR_Coverage, 4561,
        GIR_Done,
      // Label 2812: @181920
      GIM_Try, /*On fail goto*//*Label 2813*/ GIMT_Encode4(181990), // Rule ID 4555 //
        GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasUnrestrictedSOffset),
        GIM_CheckMemoryAddressSpace, /*MI*/0, /*MMO*/0, /*NumAddrSpace*/3, /*AddrSpace*/1, /*AddrSpace*/4, /*AddrSpace*/6,
        GIM_CheckRegBankForClass, /*MI*/0, /*Op*/0, /*RC*/GIMT_Encode2(AMDGPU::AV_32RegClassID),
        GIM_CheckPointerToAny, /*MI*/0, /*Op*/1, /*SizeInBits*/0,
        GIM_CheckComplexPattern, /*MI*/0, /*Op*/1, /*Renderer*/GIMT_Encode2(0), GIMT_Encode2(GICP_gi_mubuf_offset),
        // (atomic_load_umax:{ *:[i32] } (MUBUFOffset:{ *:[iPTR] } v4i32:{ *:[v4i32] }:$srsrc, i32:{ *:[i32] }:$soffset, i32:{ *:[i32] }:$offset), i32:{ *:[i32] }:$vdata_in)<<P:Predicate_atomic_load_umax_global_32>>  =>  (BUFFER_ATOMIC_UMAX_OFFSET_RTN:{ *:[i32] } anonymous_15037:{ *:[i32] }:$vdata_in, SReg_128:{ *:[v4i32] }:$srsrc, SCSrc_b32:{ *:[i32] }:$soffset, offset:{ *:[i32] }:$offset)
        GIR_BuildMI, /*InsnID*/0, /*Opcode*/GIMT_Encode2(AMDGPU::BUFFER_ATOMIC_UMAX_OFFSET_RTN),
        GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/0, // DstI[vdata]
        GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/2, // vdata_in
        GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/0, // srsrc
        GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/1, // soffset
        GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/2, // offset
        GIR_AddImm8, /*InsnID*/0, /*Imm*/1,
        GIR_MergeMemOperands, /*InsnID*/0, /*NumInsns*/1, /*MergeInsnID's*/0,
        GIR_ConstrainSelectedInstOperands, /*InsnID*/0,
        GIR_EraseFromParent, /*InsnID*/0,
        // GIR_Coverage, 4555,
        GIR_Done,
      // Label 2813: @181990
      GIM_Try, /*On fail goto*//*Label 2814*/ GIMT_Encode4(182057), // Rule ID 4559 //
        GIM_CheckMemoryAddressSpace, /*MI*/0, /*MMO*/0, /*NumAddrSpace*/3, /*AddrSpace*/1, /*AddrSpace*/4, /*AddrSpace*/6,
        GIM_CheckRegBankForClass, /*MI*/0, /*Op*/0, /*RC*/GIMT_Encode2(AMDGPU::AV_32RegClassID),
        GIM_CheckPointerToAny, /*MI*/0, /*Op*/1, /*SizeInBits*/0,
        GIM_CheckComplexPattern, /*MI*/0, /*Op*/1, /*Renderer*/GIMT_Encode2(0), GIMT_Encode2(GICP_gi_mubuf_offset),
        // (atomic_load_umax:{ *:[i32] } (MUBUFOffset:{ *:[iPTR] } v4i32:{ *:[v4i32] }:$srsrc, i32:{ *:[i32] }:$soffset, i32:{ *:[i32] }:$offset), i32:{ *:[i32] }:$vdata_in)<<P:Predicate_atomic_load_umax_global_32>>  =>  (BUFFER_ATOMIC_UMAX_VBUFFER_OFFSET_RTN:{ *:[i32] } anonymous_15037:{ *:[i32] }:$vdata_in, SReg_128:{ *:[v4i32] }:$srsrc, SCSrc_b32:{ *:[i32] }:$soffset, offset:{ *:[i32] }:$offset)
        GIR_BuildMI, /*InsnID*/0, /*Opcode*/GIMT_Encode2(AMDGPU::BUFFER_ATOMIC_UMAX_VBUFFER_OFFSET_RTN),
        GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/0, // DstI[vdata]
        GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/2, // vdata_in
        GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/0, // srsrc
        GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/1, // soffset
        GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/2, // offset
        GIR_AddImm8, /*InsnID*/0, /*Imm*/1,
        GIR_MergeMemOperands, /*InsnID*/0, /*NumInsns*/1, /*MergeInsnID's*/0,
        GIR_ConstrainSelectedInstOperands, /*InsnID*/0,
        GIR_EraseFromParent, /*InsnID*/0,
        // GIR_Coverage, 4559,
        GIR_Done,
      // Label 2814: @182057
      GIM_Try, /*On fail goto*//*Label 2815*/ GIMT_Encode4(182113), // Rule ID 6965 //
        GIM_CheckFeatures, GIMT_Encode2(GIFBS_LDSRequiresM0Init),
        GIM_CheckMemoryAddressSpace, /*MI*/0, /*MMO*/0, /*NumAddrSpace*/1, /*AddrSpace*/3,
        GIM_CheckHasNoUse, /*MI*/0,
        GIM_CheckPointerToAny, /*MI*/0, /*Op*/1, /*SizeInBits*/0,
        GIM_CheckComplexPattern, /*MI*/0, /*Op*/1, /*Renderer*/GIMT_Encode2(0), GIMT_Encode2(GICP_gi_ds_1addr_1offset),
        // (atomic_load_umax_glue:{ *:[i32] } (DS1Addr1Offset:{ *:[iPTR] } i32:{ *:[i32] }:$ptr, i32:{ *:[i32] }:$offset), i32:{ *:[i32] }:$value)<<P:Predicate_atomic_load_umax_local_m0_noret_32>>  =>  (DS_MAX_U32 ?:{ *:[i32] }:$ptr, anonymous_15037:{ *:[i32] }:$value, offset:{ *:[i32] }:$offset, 0:{ *:[i1] })
        GIR_BuildMI, /*InsnID*/0, /*Opcode*/GIMT_Encode2(AMDGPU::DS_MAX_U32),
        GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/0, // ptr
        GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/2, // value
        GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/1, // offset
        GIR_AddImm8, /*InsnID*/0, /*Imm*/0,
        GIR_MergeMemOperands, /*InsnID*/0, /*NumInsns*/1, /*MergeInsnID's*/0,
        GIR_ConstrainSelectedInstOperands, /*InsnID*/0,
        GIR_EraseFromParent, /*InsnID*/0,
        // GIR_Coverage, 6965,
        GIR_Done,
      // Label 2815: @182113
      GIM_Try, /*On fail goto*//*Label 2816*/ GIMT_Encode4(182169), // Rule ID 6967 //
        GIM_CheckFeatures, GIMT_Encode2(GIFBS_NotLDSRequiresM0Init),
        GIM_CheckMemoryAddressSpace, /*MI*/0, /*MMO*/0, /*NumAddrSpace*/1, /*AddrSpace*/3,
        GIM_CheckHasNoUse, /*MI*/0,
        GIM_CheckPointerToAny, /*MI*/0, /*Op*/1, /*SizeInBits*/0,
        GIM_CheckComplexPattern, /*MI*/0, /*Op*/1, /*Renderer*/GIMT_Encode2(0), GIMT_Encode2(GICP_gi_ds_1addr_1offset),
        // (atomic_load_umax:{ *:[i32] } (DS1Addr1Offset:{ *:[iPTR] } i32:{ *:[i32] }:$ptr, i32:{ *:[i32] }:$offset), i32:{ *:[i32] }:$value)<<P:Predicate_atomic_load_umax_local_noret_32>>  =>  (DS_MAX_U32_gfx9 ?:{ *:[i32] }:$ptr, anonymous_15037:{ *:[i32] }:$value, offset:{ *:[i32] }:$offset, 0:{ *:[i1] })
        GIR_BuildMI, /*InsnID*/0, /*Opcode*/GIMT_Encode2(AMDGPU::DS_MAX_U32_gfx9),
        GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/0, // ptr
        GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/2, // value
        GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/1, // offset
        GIR_AddImm8, /*InsnID*/0, /*Imm*/0,
        GIR_MergeMemOperands, /*InsnID*/0, /*NumInsns*/1, /*MergeInsnID's*/0,
        GIR_ConstrainSelectedInstOperands, /*InsnID*/0,
        GIR_EraseFromParent, /*InsnID*/0,
        // GIR_Coverage, 6967,
        GIR_Done,
      // Label 2816: @182169
      GIM_Try, /*On fail goto*//*Label 2817*/ GIMT_Encode4(182225), // Rule ID 6969 //
        GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasGDS),
        GIM_CheckMemoryAddressSpace, /*MI*/0, /*MMO*/0, /*NumAddrSpace*/1, /*AddrSpace*/2,
        GIM_CheckHasNoUse, /*MI*/0,
        GIM_CheckPointerToAny, /*MI*/0, /*Op*/1, /*SizeInBits*/0,
        GIM_CheckComplexPattern, /*MI*/0, /*Op*/1, /*Renderer*/GIMT_Encode2(0), GIMT_Encode2(GICP_gi_ds_1addr_1offset),
        // (atomic_load_umax_glue:{ *:[i32] } (DS1Addr1Offset:{ *:[iPTR] } i32:{ *:[i32] }:$ptr, i32:{ *:[i32] }:$offset), i32:{ *:[i32] }:$value)<<P:Predicate_atomic_load_umax_region_m0_noret_32>>  =>  (DS_MAX_U32 ?:{ *:[i32] }:$ptr, anonymous_15037:{ *:[i32] }:$value, offset:{ *:[i32] }:$offset, 1:{ *:[i1] })
        GIR_BuildMI, /*InsnID*/0, /*Opcode*/GIMT_Encode2(AMDGPU::DS_MAX_U32),
        GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/0, // ptr
        GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/2, // value
        GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/1, // offset
        GIR_AddImm8, /*InsnID*/0, /*Imm*/1,
        GIR_MergeMemOperands, /*InsnID*/0, /*NumInsns*/1, /*MergeInsnID's*/0,
        GIR_ConstrainSelectedInstOperands, /*InsnID*/0,
        GIR_EraseFromParent, /*InsnID*/0,
        // GIR_Coverage, 6969,
        GIR_Done,
      // Label 2817: @182225
      GIM_Try, /*On fail goto*//*Label 2818*/ GIMT_Encode4(182288), // Rule ID 6964 //
        GIM_CheckFeatures, GIMT_Encode2(GIFBS_LDSRequiresM0Init),
        GIM_CheckMemoryAddressSpace, /*MI*/0, /*MMO*/0, /*NumAddrSpace*/1, /*AddrSpace*/3,
        GIM_CheckRegBankForClass, /*MI*/0, /*Op*/0, /*RC*/GIMT_Encode2(AMDGPU::AV_32RegClassID),
        GIM_CheckPointerToAny, /*MI*/0, /*Op*/1, /*SizeInBits*/0,
        GIM_CheckComplexPattern, /*MI*/0, /*Op*/1, /*Renderer*/GIMT_Encode2(0), GIMT_Encode2(GICP_gi_ds_1addr_1offset),
        // (atomic_load_umax_glue:{ *:[i32] } (DS1Addr1Offset:{ *:[iPTR] } i32:{ *:[i32] }:$ptr, i32:{ *:[i32] }:$offset), i32:{ *:[i32] }:$value)<<P:Predicate_atomic_load_umax_local_m0_32>>  =>  (DS_MAX_RTN_U32:{ *:[i32] } ?:{ *:[i32] }:$ptr, anonymous_15037:{ *:[i32] }:$value, offset:{ *:[i32] }:$offset, 0:{ *:[i1] })
        GIR_BuildMI, /*InsnID*/0, /*Opcode*/GIMT_Encode2(AMDGPU::DS_MAX_RTN_U32),
        GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/0, // DstI[vdst]
        GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/0, // ptr
        GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/2, // value
        GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/1, // offset
        GIR_AddImm8, /*InsnID*/0, /*Imm*/0,
        GIR_MergeMemOperands, /*InsnID*/0, /*NumInsns*/1, /*MergeInsnID's*/0,
        GIR_ConstrainSelectedInstOperands, /*InsnID*/0,
        GIR_EraseFromParent, /*InsnID*/0,
        // GIR_Coverage, 6964,
        GIR_Done,
      // Label 2818: @182288
      GIM_Try, /*On fail goto*//*Label 2819*/ GIMT_Encode4(182351), // Rule ID 6966 //
        GIM_CheckFeatures, GIMT_Encode2(GIFBS_NotLDSRequiresM0Init),
        GIM_CheckMemoryAddressSpace, /*MI*/0, /*MMO*/0, /*NumAddrSpace*/1, /*AddrSpace*/3,
        GIM_CheckRegBankForClass, /*MI*/0, /*Op*/0, /*RC*/GIMT_Encode2(AMDGPU::AV_32RegClassID),
        GIM_CheckPointerToAny, /*MI*/0, /*Op*/1, /*SizeInBits*/0,
        GIM_CheckComplexPattern, /*MI*/0, /*Op*/1, /*Renderer*/GIMT_Encode2(0), GIMT_Encode2(GICP_gi_ds_1addr_1offset),
        // (atomic_load_umax:{ *:[i32] } (DS1Addr1Offset:{ *:[iPTR] } i32:{ *:[i32] }:$ptr, i32:{ *:[i32] }:$offset), i32:{ *:[i32] }:$value)<<P:Predicate_atomic_load_umax_local_32>>  =>  (DS_MAX_RTN_U32_gfx9:{ *:[i32] } ?:{ *:[i32] }:$ptr, anonymous_15037:{ *:[i32] }:$value, offset:{ *:[i32] }:$offset, 0:{ *:[i1] })
        GIR_BuildMI, /*InsnID*/0, /*Opcode*/GIMT_Encode2(AMDGPU::DS_MAX_RTN_U32_gfx9),
        GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/0, // DstI[vdst]
        GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/0, // ptr
        GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/2, // value
        GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/1, // offset
        GIR_AddImm8, /*InsnID*/0, /*Imm*/0,
        GIR_MergeMemOperands, /*InsnID*/0, /*NumInsns*/1, /*MergeInsnID's*/0,
        GIR_ConstrainSelectedInstOperands, /*InsnID*/0,
        GIR_EraseFromParent, /*InsnID*/0,
        // GIR_Coverage, 6966,
        GIR_Done,
      // Label 2819: @182351
      GIM_Try, /*On fail goto*//*Label 2820*/ GIMT_Encode4(182414), // Rule ID 6968 //
        GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasGDS),
        GIM_CheckMemoryAddressSpace, /*MI*/0, /*MMO*/0, /*NumAddrSpace*/1, /*AddrSpace*/2,
        GIM_CheckRegBankForClass, /*MI*/0, /*Op*/0, /*RC*/GIMT_Encode2(AMDGPU::AV_32RegClassID),
        GIM_CheckPointerToAny, /*MI*/0, /*Op*/1, /*SizeInBits*/0,
        GIM_CheckComplexPattern, /*MI*/0, /*Op*/1, /*Renderer*/GIMT_Encode2(0), GIMT_Encode2(GICP_gi_ds_1addr_1offset),
        // (atomic_load_umax_glue:{ *:[i32] } (DS1Addr1Offset:{ *:[iPTR] } i32:{ *:[i32] }:$ptr, i32:{ *:[i32] }:$offset), i32:{ *:[i32] }:$value)<<P:Predicate_atomic_load_umax_region_m0_32>>  =>  (DS_MAX_RTN_U32:{ *:[i32] } ?:{ *:[i32] }:$ptr, anonymous_15037:{ *:[i32] }:$value, offset:{ *:[i32] }:$offset, 1:{ *:[i1] })
        GIR_BuildMI, /*InsnID*/0, /*Opcode*/GIMT_Encode2(AMDGPU::DS_MAX_RTN_U32),
        GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/0, // DstI[vdst]
        GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/0, // ptr
        GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/2, // value
        GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/1, // offset
        GIR_AddImm8, /*InsnID*/0, /*Imm*/1,
        GIR_MergeMemOperands, /*InsnID*/0, /*NumInsns*/1, /*MergeInsnID's*/0,
        GIR_ConstrainSelectedInstOperands, /*InsnID*/0,
        GIR_EraseFromParent, /*InsnID*/0,
        // GIR_Coverage, 6968,
        GIR_Done,
      // Label 2820: @182414
      GIM_Try, /*On fail goto*//*Label 2821*/ GIMT_Encode4(182477), // Rule ID 3171 //
        GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasFlatGlobalInsts),
        GIM_CheckMemoryAddressSpace, /*MI*/0, /*MMO*/0, /*NumAddrSpace*/3, /*AddrSpace*/1, /*AddrSpace*/4, /*AddrSpace*/6,
        GIM_CheckHasNoUse, /*MI*/0,
        GIM_CheckPointerToAny, /*MI*/0, /*Op*/1, /*SizeInBits*/0,
        GIM_CheckComplexPattern, /*MI*/0, /*Op*/1, /*Renderer*/GIMT_Encode2(0), GIMT_Encode2(GICP_gi_global_saddr),
        // (atomic_load_umax:{ *:[i32] } (GlobalSAddr:{ *:[iPTR] } SReg_64:{ *:[i64] }:$saddr, VGPR_32:{ *:[i32] }:$voffset, i32:{ *:[i32] }:$offset), i32:{ *:[i32] }:$data)<<P:Predicate_atomic_load_umax_global_noret_32>>  =>  (GLOBAL_ATOMIC_UMAX_SADDR ?:{ *:[i32] }:$voffset, anonymous_15037:{ *:[i32] }:$data, ?:{ *:[i64] }:$saddr, ?:{ *:[i32] }:$offset)
        GIR_BuildMI, /*InsnID*/0, /*Opcode*/GIMT_Encode2(AMDGPU::GLOBAL_ATOMIC_UMAX_SADDR),
        GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/1, // voffset
        GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/2, // data
        GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/0, // saddr
        GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/2, // offset
        GIR_AddImm8, /*InsnID*/0, /*Imm*/0,
        GIR_MergeMemOperands, /*InsnID*/0, /*NumInsns*/1, /*MergeInsnID's*/0,
        GIR_ConstrainSelectedInstOperands, /*InsnID*/0,
        GIR_EraseFromParent, /*InsnID*/0,
        // GIR_Coverage, 3171,
        GIR_Done,
      // Label 2821: @182477
      GIM_Try, /*On fail goto*//*Label 2822*/ GIMT_Encode4(182547), // Rule ID 3173 //
        GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasFlatGlobalInsts),
        GIM_CheckMemoryAddressSpace, /*MI*/0, /*MMO*/0, /*NumAddrSpace*/3, /*AddrSpace*/1, /*AddrSpace*/4, /*AddrSpace*/6,
        GIM_CheckRegBankForClass, /*MI*/0, /*Op*/0, /*RC*/GIMT_Encode2(AMDGPU::AV_32RegClassID),
        GIM_CheckPointerToAny, /*MI*/0, /*Op*/1, /*SizeInBits*/0,
        GIM_CheckComplexPattern, /*MI*/0, /*Op*/1, /*Renderer*/GIMT_Encode2(0), GIMT_Encode2(GICP_gi_global_saddr),
        // (atomic_load_umax:{ *:[i32] } (GlobalSAddr:{ *:[iPTR] } SReg_64:{ *:[i64] }:$saddr, VGPR_32:{ *:[i32] }:$voffset, i32:{ *:[i32] }:$offset), i32:{ *:[i32] }:$data)<<P:Predicate_atomic_load_umax_global_32>>  =>  (GLOBAL_ATOMIC_UMAX_SADDR_RTN:{ *:[i32] } ?:{ *:[i32] }:$voffset, anonymous_15037:{ *:[i32] }:$data, ?:{ *:[i64] }:$saddr, ?:{ *:[i32] }:$offset)
        GIR_BuildMI, /*InsnID*/0, /*Opcode*/GIMT_Encode2(AMDGPU::GLOBAL_ATOMIC_UMAX_SADDR_RTN),
        GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/0, // DstI[vdst]
        GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/1, // voffset
        GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/2, // data
        GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/0, // saddr
        GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/2, // offset
        GIR_AddImm8, /*InsnID*/0, /*Imm*/1,
        GIR_MergeMemOperands, /*InsnID*/0, /*NumInsns*/1, /*MergeInsnID's*/0,
        GIR_ConstrainSelectedInstOperands, /*InsnID*/0,
        GIR_EraseFromParent, /*InsnID*/0,
        // GIR_Coverage, 3173,
        GIR_Done,
      // Label 2822: @182547
      GIM_Try, /*On fail goto*//*Label 2823*/ GIMT_Encode4(182605), // Rule ID 3170 //
        GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasFlatGlobalInsts),
        GIM_CheckMemoryAddressSpace, /*MI*/0, /*MMO*/0, /*NumAddrSpace*/3, /*AddrSpace*/1, /*AddrSpace*/4, /*AddrSpace*/6,
        GIM_CheckHasNoUse, /*MI*/0,
        GIM_CheckPointerToAny, /*MI*/0, /*Op*/1, /*SizeInBits*/0,
        GIM_CheckComplexPattern, /*MI*/0, /*Op*/1, /*Renderer*/GIMT_Encode2(0), GIMT_Encode2(GICP_gi_global_offset),
        // (atomic_load_umax:{ *:[i32] } (GlobalOffset:{ *:[iPTR] } i64:{ *:[i64] }:$vaddr, i32:{ *:[i32] }:$offset), i32:{ *:[i32] }:$data)<<P:Predicate_atomic_load_umax_global_noret_32>>  =>  (GLOBAL_ATOMIC_UMAX VReg_64:{ *:[i64] }:$vaddr, anonymous_15037:{ *:[i32] }:$data, ?:{ *:[i32] }:$offset)
        GIR_BuildMI, /*InsnID*/0, /*Opcode*/GIMT_Encode2(AMDGPU::GLOBAL_ATOMIC_UMAX),
        GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/0, // vaddr
        GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/2, // data
        GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/1, // offset
        GIR_AddImm8, /*InsnID*/0, /*Imm*/0,
        GIR_MergeMemOperands, /*InsnID*/0, /*NumInsns*/1, /*MergeInsnID's*/0,
        GIR_ConstrainSelectedInstOperands, /*InsnID*/0,
        GIR_EraseFromParent, /*InsnID*/0,
        // GIR_Coverage, 3170,
        GIR_Done,
      // Label 2823: @182605
      GIM_Try, /*On fail goto*//*Label 2824*/ GIMT_Encode4(182670), // Rule ID 3172 //
        GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasFlatGlobalInsts),
        GIM_CheckMemoryAddressSpace, /*MI*/0, /*MMO*/0, /*NumAddrSpace*/3, /*AddrSpace*/1, /*AddrSpace*/4, /*AddrSpace*/6,
        GIM_CheckRegBankForClass, /*MI*/0, /*Op*/0, /*RC*/GIMT_Encode2(AMDGPU::AV_32RegClassID),
        GIM_CheckPointerToAny, /*MI*/0, /*Op*/1, /*SizeInBits*/0,
        GIM_CheckComplexPattern, /*MI*/0, /*Op*/1, /*Renderer*/GIMT_Encode2(0), GIMT_Encode2(GICP_gi_global_offset),
        // (atomic_load_umax:{ *:[i32] } (GlobalOffset:{ *:[iPTR] } i64:{ *:[i64] }:$vaddr, i32:{ *:[i32] }:$offset), i32:{ *:[i32] }:$data)<<P:Predicate_atomic_load_umax_global_32>>  =>  (GLOBAL_ATOMIC_UMAX_RTN:{ *:[i32] } VReg_64:{ *:[i64] }:$vaddr, anonymous_15037:{ *:[i32] }:$data, ?:{ *:[i32] }:$offset)
        GIR_BuildMI, /*InsnID*/0, /*Opcode*/GIMT_Encode2(AMDGPU::GLOBAL_ATOMIC_UMAX_RTN),
        GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/0, // DstI[vdst]
        GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/0, // vaddr
        GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/2, // data
        GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/1, // offset
        GIR_AddImm8, /*InsnID*/0, /*Imm*/1,
        GIR_MergeMemOperands, /*InsnID*/0, /*NumInsns*/1, /*MergeInsnID's*/0,
        GIR_ConstrainSelectedInstOperands, /*InsnID*/0,
        GIR_EraseFromParent, /*InsnID*/0,
        // GIR_Coverage, 3172,
        GIR_Done,
      // Label 2824: @182670
      GIM_Try, /*On fail goto*//*Label 2825*/ GIMT_Encode4(182729), // Rule ID 2840 //
        GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasFlatAddressSpace),
        GIM_CheckMemoryAddressSpace, /*MI*/0, /*MMO*/0, /*NumAddrSpace*/4, /*AddrSpace*/0, /*AddrSpace*/1, /*AddrSpace*/4, /*AddrSpace*/6,
        GIM_CheckHasNoUse, /*MI*/0,
        GIM_CheckPointerToAny, /*MI*/0, /*Op*/1, /*SizeInBits*/0,
        GIM_CheckComplexPattern, /*MI*/0, /*Op*/1, /*Renderer*/GIMT_Encode2(0), GIMT_Encode2(GICP_gi_flat_offset),
        // (atomic_load_umax:{ *:[i32] } (FlatOffset:{ *:[iPTR] } i64:{ *:[i64] }:$vaddr, i32:{ *:[i32] }:$offset), i32:{ *:[i32] }:$data)<<P:Predicate_atomic_load_umax_flat_noret_32>>  =>  (FLAT_ATOMIC_UMAX VReg_64:{ *:[i64] }:$vaddr, anonymous_15037:{ *:[i32] }:$data, ?:{ *:[i32] }:$offset)
        GIR_BuildMI, /*InsnID*/0, /*Opcode*/GIMT_Encode2(AMDGPU::FLAT_ATOMIC_UMAX),
        GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/0, // vaddr
        GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/2, // data
        GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/1, // offset
        GIR_AddImm8, /*InsnID*/0, /*Imm*/0,
        GIR_MergeMemOperands, /*InsnID*/0, /*NumInsns*/1, /*MergeInsnID's*/0,
        GIR_ConstrainSelectedInstOperands, /*InsnID*/0,
        GIR_EraseFromParent, /*InsnID*/0,
        // GIR_Coverage, 2840,
        GIR_Done,
      // Label 2825: @182729
      GIM_Try, /*On fail goto*//*Label 2826*/ GIMT_Encode4(182787), // Rule ID 2892 //
        GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasFlatAddressSpace),
        GIM_CheckMemoryAddressSpace, /*MI*/0, /*MMO*/0, /*NumAddrSpace*/3, /*AddrSpace*/1, /*AddrSpace*/4, /*AddrSpace*/6,
        GIM_CheckHasNoUse, /*MI*/0,
        GIM_CheckPointerToAny, /*MI*/0, /*Op*/1, /*SizeInBits*/0,
        GIM_CheckComplexPattern, /*MI*/0, /*Op*/1, /*Renderer*/GIMT_Encode2(0), GIMT_Encode2(GICP_gi_flat_offset),
        // (atomic_load_umax:{ *:[i32] } (FlatOffset:{ *:[iPTR] } i64:{ *:[i64] }:$vaddr, i32:{ *:[i32] }:$offset), i32:{ *:[i32] }:$data)<<P:Predicate_atomic_load_umax_global_noret_32>>  =>  (FLAT_ATOMIC_UMAX VReg_64:{ *:[i64] }:$vaddr, anonymous_15037:{ *:[i32] }:$data, ?:{ *:[i32] }:$offset)
        GIR_BuildMI, /*InsnID*/0, /*Opcode*/GIMT_Encode2(AMDGPU::FLAT_ATOMIC_UMAX),
        GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/0, // vaddr
        GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/2, // data
        GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/1, // offset
        GIR_AddImm8, /*InsnID*/0, /*Imm*/0,
        GIR_MergeMemOperands, /*InsnID*/0, /*NumInsns*/1, /*MergeInsnID's*/0,
        GIR_ConstrainSelectedInstOperands, /*InsnID*/0,
        GIR_EraseFromParent, /*InsnID*/0,
        // GIR_Coverage, 2892,
        GIR_Done,
      // Label 2826: @182787
      GIM_Try, /*On fail goto*//*Label 2827*/ GIMT_Encode4(182853), // Rule ID 2839 //
        GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasFlatAddressSpace),
        GIM_CheckMemoryAddressSpace, /*MI*/0, /*MMO*/0, /*NumAddrSpace*/4, /*AddrSpace*/0, /*AddrSpace*/1, /*AddrSpace*/4, /*AddrSpace*/6,
        GIM_CheckRegBankForClass, /*MI*/0, /*Op*/0, /*RC*/GIMT_Encode2(AMDGPU::AV_32RegClassID),
        GIM_CheckPointerToAny, /*MI*/0, /*Op*/1, /*SizeInBits*/0,
        GIM_CheckComplexPattern, /*MI*/0, /*Op*/1, /*Renderer*/GIMT_Encode2(0), GIMT_Encode2(GICP_gi_flat_offset),
        // (atomic_load_umax:{ *:[i32] } (FlatOffset:{ *:[iPTR] } i64:{ *:[i64] }:$vaddr, i32:{ *:[i32] }:$offset), i32:{ *:[i32] }:$data)<<P:Predicate_atomic_load_umax_flat_32>>  =>  (FLAT_ATOMIC_UMAX_RTN:{ *:[i32] } VReg_64:{ *:[i64] }:$vaddr, anonymous_15037:{ *:[i32] }:$data, ?:{ *:[i32] }:$offset)
        GIR_BuildMI, /*InsnID*/0, /*Opcode*/GIMT_Encode2(AMDGPU::FLAT_ATOMIC_UMAX_RTN),
        GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/0, // DstI[vdst]
        GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/0, // vaddr
        GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/2, // data
        GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/1, // offset
        GIR_AddImm8, /*InsnID*/0, /*Imm*/1,
        GIR_MergeMemOperands, /*InsnID*/0, /*NumInsns*/1, /*MergeInsnID's*/0,
        GIR_ConstrainSelectedInstOperands, /*InsnID*/0,
        GIR_EraseFromParent, /*InsnID*/0,
        // GIR_Coverage, 2839,
        GIR_Done,
      // Label 2827: @182853
      GIM_Try, /*On fail goto*//*Label 2828*/ GIMT_Encode4(182918), // Rule ID 2891 //
        GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasFlatAddressSpace),
        GIM_CheckMemoryAddressSpace, /*MI*/0, /*MMO*/0, /*NumAddrSpace*/3, /*AddrSpace*/1, /*AddrSpace*/4, /*AddrSpace*/6,
        GIM_CheckRegBankForClass, /*MI*/0, /*Op*/0, /*RC*/GIMT_Encode2(AMDGPU::AV_32RegClassID),
        GIM_CheckPointerToAny, /*MI*/0, /*Op*/1, /*SizeInBits*/0,
        GIM_CheckComplexPattern, /*MI*/0, /*Op*/1, /*Renderer*/GIMT_Encode2(0), GIMT_Encode2(GICP_gi_flat_offset),
        // (atomic_load_umax:{ *:[i32] } (FlatOffset:{ *:[iPTR] } i64:{ *:[i64] }:$vaddr, i32:{ *:[i32] }:$offset), i32:{ *:[i32] }:$data)<<P:Predicate_atomic_load_umax_global_32>>  =>  (FLAT_ATOMIC_UMAX_RTN:{ *:[i32] } VReg_64:{ *:[i64] }:$vaddr, anonymous_15037:{ *:[i32] }:$data, ?:{ *:[i32] }:$offset)
        GIR_BuildMI, /*InsnID*/0, /*Opcode*/GIMT_Encode2(AMDGPU::FLAT_ATOMIC_UMAX_RTN),
        GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/0, // DstI[vdst]
        GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/0, // vaddr
        GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/2, // data
        GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/1, // offset
        GIR_AddImm8, /*InsnID*/0, /*Imm*/1,
        GIR_MergeMemOperands, /*InsnID*/0, /*NumInsns*/1, /*MergeInsnID's*/0,
        GIR_ConstrainSelectedInstOperands, /*InsnID*/0,
        GIR_EraseFromParent, /*InsnID*/0,
        // GIR_Coverage, 2891,
        GIR_Done,
      // Label 2828: @182918
      GIM_Reject,
    // Label 2806: @182919
    GIM_Reject,
    // Label 2804: @182920
    GIM_Try, /*On fail goto*//*Label 2829*/ GIMT_Encode4(184331),
      GIM_CheckType, /*MI*/0, /*Op*/2, /*Type*/GILLT_s64,
      GIM_Try, /*On fail goto*//*Label 2830*/ GIMT_Encode4(182997), // Rule ID 4654 //
        GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasUnrestrictedSOffset),
        GIM_CheckMemoryAddressSpace, /*MI*/0, /*MMO*/0, /*NumAddrSpace*/3, /*AddrSpace*/1, /*AddrSpace*/4, /*AddrSpace*/6,
        GIM_CheckHasNoUse, /*MI*/0,
        GIM_CheckPointerToAny, /*MI*/0, /*Op*/1, /*SizeInBits*/0,
        GIM_CheckComplexPattern, /*MI*/0, /*Op*/1, /*Renderer*/GIMT_Encode2(0), GIMT_Encode2(GICP_gi_mubuf_addr64),
        // (atomic_load_umax:{ *:[i64] } (MUBUFAddr64:{ *:[iPTR] } v4i32:{ *:[v4i32] }:$srsrc, i64:{ *:[i64] }:$vaddr, i32:{ *:[i32] }:$soffset, i32:{ *:[i32] }:$offset), i64:{ *:[i64] }:$vdata_in)<<P:Predicate_atomic_load_umax_global_noret_64>>  =>  (BUFFER_ATOMIC_UMAX_X2_ADDR64 anonymous_15036:{ *:[i64] }:$vdata_in, VReg_64:{ *:[i64] }:$vaddr, SReg_128:{ *:[v4i32] }:$srsrc, SCSrc_b32:{ *:[i32] }:$soffset, offset:{ *:[i32] }:$offset)
        GIR_BuildMI, /*InsnID*/0, /*Opcode*/GIMT_Encode2(AMDGPU::BUFFER_ATOMIC_UMAX_X2_ADDR64),
        GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/2, // vdata_in
        GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/1, // vaddr
        GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/0, // srsrc
        GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/2, // soffset
        GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/3, // offset
        GIR_AddImm8, /*InsnID*/0, /*Imm*/0,
        GIR_MergeMemOperands, /*InsnID*/0, /*NumInsns*/1, /*MergeInsnID's*/0,
        GIR_ConstrainSelectedInstOperands, /*InsnID*/0,
        GIR_EraseFromParent, /*InsnID*/0,
        // GIR_Coverage, 4654,
        GIR_Done,
      // Label 2830: @182997
      GIM_Try, /*On fail goto*//*Label 2831*/ GIMT_Encode4(183062), // Rule ID 4658 //
        GIM_CheckMemoryAddressSpace, /*MI*/0, /*MMO*/0, /*NumAddrSpace*/3, /*AddrSpace*/1, /*AddrSpace*/4, /*AddrSpace*/6,
        GIM_CheckHasNoUse, /*MI*/0,
        GIM_CheckPointerToAny, /*MI*/0, /*Op*/1, /*SizeInBits*/0,
        GIM_CheckComplexPattern, /*MI*/0, /*Op*/1, /*Renderer*/GIMT_Encode2(0), GIMT_Encode2(GICP_gi_mubuf_addr64),
        // (atomic_load_umax:{ *:[i64] } (MUBUFAddr64:{ *:[iPTR] } v4i32:{ *:[v4i32] }:$srsrc, i64:{ *:[i64] }:$vaddr, i32:{ *:[i32] }:$soffset, i32:{ *:[i32] }:$offset), i64:{ *:[i64] }:$vdata_in)<<P:Predicate_atomic_load_umax_global_noret_64>>  =>  (BUFFER_ATOMIC_UMAX_X2_VBUFFER_ADDR64 anonymous_15036:{ *:[i64] }:$vdata_in, VReg_64:{ *:[i64] }:$vaddr, SReg_128:{ *:[v4i32] }:$srsrc, SCSrc_b32:{ *:[i32] }:$soffset, offset:{ *:[i32] }:$offset)
        GIR_BuildMI, /*InsnID*/0, /*Opcode*/GIMT_Encode2(AMDGPU::BUFFER_ATOMIC_UMAX_X2_VBUFFER_ADDR64),
        GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/2, // vdata_in
        GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/1, // vaddr
        GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/0, // srsrc
        GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/2, // soffset
        GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/3, // offset
        GIR_AddImm8, /*InsnID*/0, /*Imm*/0,
        GIR_MergeMemOperands, /*InsnID*/0, /*NumInsns*/1, /*MergeInsnID's*/0,
        GIR_ConstrainSelectedInstOperands, /*InsnID*/0,
        GIR_EraseFromParent, /*InsnID*/0,
        // GIR_Coverage, 4658,
        GIR_Done,
      // Label 2831: @183062
      GIM_Try, /*On fail goto*//*Label 2832*/ GIMT_Encode4(183137), // Rule ID 4652 //
        GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasUnrestrictedSOffset),
        GIM_CheckMemoryAddressSpace, /*MI*/0, /*MMO*/0, /*NumAddrSpace*/3, /*AddrSpace*/1, /*AddrSpace*/4, /*AddrSpace*/6,
        GIM_CheckRegBankForClass, /*MI*/0, /*Op*/0, /*RC*/GIMT_Encode2(AMDGPU::AV_64RegClassID),
        GIM_CheckPointerToAny, /*MI*/0, /*Op*/1, /*SizeInBits*/0,
        GIM_CheckComplexPattern, /*MI*/0, /*Op*/1, /*Renderer*/GIMT_Encode2(0), GIMT_Encode2(GICP_gi_mubuf_addr64),
        // (atomic_load_umax:{ *:[i64] } (MUBUFAddr64:{ *:[iPTR] } v4i32:{ *:[v4i32] }:$srsrc, i64:{ *:[i64] }:$vaddr, i32:{ *:[i32] }:$soffset, i32:{ *:[i32] }:$offset), i64:{ *:[i64] }:$vdata_in)<<P:Predicate_atomic_load_umax_global_64>>  =>  (BUFFER_ATOMIC_UMAX_X2_ADDR64_RTN:{ *:[i64] } anonymous_15036:{ *:[i64] }:$vdata_in, VReg_64:{ *:[i64] }:$vaddr, SReg_128:{ *:[v4i32] }:$srsrc, SCSrc_b32:{ *:[i32] }:$soffset, offset:{ *:[i32] }:$offset)
        GIR_BuildMI, /*InsnID*/0, /*Opcode*/GIMT_Encode2(AMDGPU::BUFFER_ATOMIC_UMAX_X2_ADDR64_RTN),
        GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/0, // DstI[vdata]
        GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/2, // vdata_in
        GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/1, // vaddr
        GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/0, // srsrc
        GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/2, // soffset
        GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/3, // offset
        GIR_AddImm8, /*InsnID*/0, /*Imm*/1,
        GIR_MergeMemOperands, /*InsnID*/0, /*NumInsns*/1, /*MergeInsnID's*/0,
        GIR_ConstrainSelectedInstOperands, /*InsnID*/0,
        GIR_EraseFromParent, /*InsnID*/0,
        // GIR_Coverage, 4652,
        GIR_Done,
      // Label 2832: @183137
      GIM_Try, /*On fail goto*//*Label 2833*/ GIMT_Encode4(183209), // Rule ID 4656 //
        GIM_CheckMemoryAddressSpace, /*MI*/0, /*MMO*/0, /*NumAddrSpace*/3, /*AddrSpace*/1, /*AddrSpace*/4, /*AddrSpace*/6,
        GIM_CheckRegBankForClass, /*MI*/0, /*Op*/0, /*RC*/GIMT_Encode2(AMDGPU::AV_64RegClassID),
        GIM_CheckPointerToAny, /*MI*/0, /*Op*/1, /*SizeInBits*/0,
        GIM_CheckComplexPattern, /*MI*/0, /*Op*/1, /*Renderer*/GIMT_Encode2(0), GIMT_Encode2(GICP_gi_mubuf_addr64),
        // (atomic_load_umax:{ *:[i64] } (MUBUFAddr64:{ *:[iPTR] } v4i32:{ *:[v4i32] }:$srsrc, i64:{ *:[i64] }:$vaddr, i32:{ *:[i32] }:$soffset, i32:{ *:[i32] }:$offset), i64:{ *:[i64] }:$vdata_in)<<P:Predicate_atomic_load_umax_global_64>>  =>  (BUFFER_ATOMIC_UMAX_X2_VBUFFER_ADDR64_RTN:{ *:[i64] } anonymous_15036:{ *:[i64] }:$vdata_in, VReg_64:{ *:[i64] }:$vaddr, SReg_128:{ *:[v4i32] }:$srsrc, SCSrc_b32:{ *:[i32] }:$soffset, offset:{ *:[i32] }:$offset)
        GIR_BuildMI, /*InsnID*/0, /*Opcode*/GIMT_Encode2(AMDGPU::BUFFER_ATOMIC_UMAX_X2_VBUFFER_ADDR64_RTN),
        GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/0, // DstI[vdata]
        GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/2, // vdata_in
        GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/1, // vaddr
        GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/0, // srsrc
        GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/2, // soffset
        GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/3, // offset
        GIR_AddImm8, /*InsnID*/0, /*Imm*/1,
        GIR_MergeMemOperands, /*InsnID*/0, /*NumInsns*/1, /*MergeInsnID's*/0,
        GIR_ConstrainSelectedInstOperands, /*InsnID*/0,
        GIR_EraseFromParent, /*InsnID*/0,
        // GIR_Coverage, 4656,
        GIR_Done,
      // Label 2833: @183209
      GIM_Try, /*On fail goto*//*Label 2834*/ GIMT_Encode4(183272), // Rule ID 4653 //
        GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasUnrestrictedSOffset),
        GIM_CheckMemoryAddressSpace, /*MI*/0, /*MMO*/0, /*NumAddrSpace*/3, /*AddrSpace*/1, /*AddrSpace*/4, /*AddrSpace*/6,
        GIM_CheckHasNoUse, /*MI*/0,
        GIM_CheckPointerToAny, /*MI*/0, /*Op*/1, /*SizeInBits*/0,
        GIM_CheckComplexPattern, /*MI*/0, /*Op*/1, /*Renderer*/GIMT_Encode2(0), GIMT_Encode2(GICP_gi_mubuf_offset),
        // (atomic_load_umax:{ *:[i64] } (MUBUFOffset:{ *:[iPTR] } v4i32:{ *:[v4i32] }:$srsrc, i32:{ *:[i32] }:$soffset, i32:{ *:[i32] }:$offset), i64:{ *:[i64] }:$vdata_in)<<P:Predicate_atomic_load_umax_global_noret_64>>  =>  (BUFFER_ATOMIC_UMAX_X2_OFFSET anonymous_15036:{ *:[i64] }:$vdata_in, SReg_128:{ *:[v4i32] }:$srsrc, SCSrc_b32:{ *:[i32] }:$soffset, offset:{ *:[i32] }:$offset)
        GIR_BuildMI, /*InsnID*/0, /*Opcode*/GIMT_Encode2(AMDGPU::BUFFER_ATOMIC_UMAX_X2_OFFSET),
        GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/2, // vdata_in
        GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/0, // srsrc
        GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/1, // soffset
        GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/2, // offset
        GIR_AddImm8, /*InsnID*/0, /*Imm*/0,
        GIR_MergeMemOperands, /*InsnID*/0, /*NumInsns*/1, /*MergeInsnID's*/0,
        GIR_ConstrainSelectedInstOperands, /*InsnID*/0,
        GIR_EraseFromParent, /*InsnID*/0,
        // GIR_Coverage, 4653,
        GIR_Done,
      // Label 2834: @183272
      GIM_Try, /*On fail goto*//*Label 2835*/ GIMT_Encode4(183332), // Rule ID 4657 //
        GIM_CheckMemoryAddressSpace, /*MI*/0, /*MMO*/0, /*NumAddrSpace*/3, /*AddrSpace*/1, /*AddrSpace*/4, /*AddrSpace*/6,
        GIM_CheckHasNoUse, /*MI*/0,
        GIM_CheckPointerToAny, /*MI*/0, /*Op*/1, /*SizeInBits*/0,
        GIM_CheckComplexPattern, /*MI*/0, /*Op*/1, /*Renderer*/GIMT_Encode2(0), GIMT_Encode2(GICP_gi_mubuf_offset),
        // (atomic_load_umax:{ *:[i64] } (MUBUFOffset:{ *:[iPTR] } v4i32:{ *:[v4i32] }:$srsrc, i32:{ *:[i32] }:$soffset, i32:{ *:[i32] }:$offset), i64:{ *:[i64] }:$vdata_in)<<P:Predicate_atomic_load_umax_global_noret_64>>  =>  (BUFFER_ATOMIC_UMAX_X2_VBUFFER_OFFSET anonymous_15036:{ *:[i64] }:$vdata_in, SReg_128:{ *:[v4i32] }:$srsrc, SCSrc_b32:{ *:[i32] }:$soffset, offset:{ *:[i32] }:$offset)
        GIR_BuildMI, /*InsnID*/0, /*Opcode*/GIMT_Encode2(AMDGPU::BUFFER_ATOMIC_UMAX_X2_VBUFFER_OFFSET),
        GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/2, // vdata_in
        GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/0, // srsrc
        GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/1, // soffset
        GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/2, // offset
        GIR_AddImm8, /*InsnID*/0, /*Imm*/0,
        GIR_MergeMemOperands, /*InsnID*/0, /*NumInsns*/1, /*MergeInsnID's*/0,
        GIR_ConstrainSelectedInstOperands, /*InsnID*/0,
        GIR_EraseFromParent, /*InsnID*/0,
        // GIR_Coverage, 4657,
        GIR_Done,
      // Label 2835: @183332
      GIM_Try, /*On fail goto*//*Label 2836*/ GIMT_Encode4(183402), // Rule ID 4651 //
        GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasUnrestrictedSOffset),
        GIM_CheckMemoryAddressSpace, /*MI*/0, /*MMO*/0, /*NumAddrSpace*/3, /*AddrSpace*/1, /*AddrSpace*/4, /*AddrSpace*/6,
        GIM_CheckRegBankForClass, /*MI*/0, /*Op*/0, /*RC*/GIMT_Encode2(AMDGPU::AV_64RegClassID),
        GIM_CheckPointerToAny, /*MI*/0, /*Op*/1, /*SizeInBits*/0,
        GIM_CheckComplexPattern, /*MI*/0, /*Op*/1, /*Renderer*/GIMT_Encode2(0), GIMT_Encode2(GICP_gi_mubuf_offset),
        // (atomic_load_umax:{ *:[i64] } (MUBUFOffset:{ *:[iPTR] } v4i32:{ *:[v4i32] }:$srsrc, i32:{ *:[i32] }:$soffset, i32:{ *:[i32] }:$offset), i64:{ *:[i64] }:$vdata_in)<<P:Predicate_atomic_load_umax_global_64>>  =>  (BUFFER_ATOMIC_UMAX_X2_OFFSET_RTN:{ *:[i64] } anonymous_15036:{ *:[i64] }:$vdata_in, SReg_128:{ *:[v4i32] }:$srsrc, SCSrc_b32:{ *:[i32] }:$soffset, offset:{ *:[i32] }:$offset)
        GIR_BuildMI, /*InsnID*/0, /*Opcode*/GIMT_Encode2(AMDGPU::BUFFER_ATOMIC_UMAX_X2_OFFSET_RTN),
        GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/0, // DstI[vdata]
        GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/2, // vdata_in
        GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/0, // srsrc
        GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/1, // soffset
        GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/2, // offset
        GIR_AddImm8, /*InsnID*/0, /*Imm*/1,
        GIR_MergeMemOperands, /*InsnID*/0, /*NumInsns*/1, /*MergeInsnID's*/0,
        GIR_ConstrainSelectedInstOperands, /*InsnID*/0,
        GIR_EraseFromParent, /*InsnID*/0,
        // GIR_Coverage, 4651,
        GIR_Done,
      // Label 2836: @183402
      GIM_Try, /*On fail goto*//*Label 2837*/ GIMT_Encode4(183469), // Rule ID 4655 //
        GIM_CheckMemoryAddressSpace, /*MI*/0, /*MMO*/0, /*NumAddrSpace*/3, /*AddrSpace*/1, /*AddrSpace*/4, /*AddrSpace*/6,
        GIM_CheckRegBankForClass, /*MI*/0, /*Op*/0, /*RC*/GIMT_Encode2(AMDGPU::AV_64RegClassID),
        GIM_CheckPointerToAny, /*MI*/0, /*Op*/1, /*SizeInBits*/0,
        GIM_CheckComplexPattern, /*MI*/0, /*Op*/1, /*Renderer*/GIMT_Encode2(0), GIMT_Encode2(GICP_gi_mubuf_offset),
        // (atomic_load_umax:{ *:[i64] } (MUBUFOffset:{ *:[iPTR] } v4i32:{ *:[v4i32] }:$srsrc, i32:{ *:[i32] }:$soffset, i32:{ *:[i32] }:$offset), i64:{ *:[i64] }:$vdata_in)<<P:Predicate_atomic_load_umax_global_64>>  =>  (BUFFER_ATOMIC_UMAX_X2_VBUFFER_OFFSET_RTN:{ *:[i64] } anonymous_15036:{ *:[i64] }:$vdata_in, SReg_128:{ *:[v4i32] }:$srsrc, SCSrc_b32:{ *:[i32] }:$soffset, offset:{ *:[i32] }:$offset)
        GIR_BuildMI, /*InsnID*/0, /*Opcode*/GIMT_Encode2(AMDGPU::BUFFER_ATOMIC_UMAX_X2_VBUFFER_OFFSET_RTN),
        GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/0, // DstI[vdata]
        GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/2, // vdata_in
        GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/0, // srsrc
        GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/1, // soffset
        GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/2, // offset
        GIR_AddImm8, /*InsnID*/0, /*Imm*/1,
        GIR_MergeMemOperands, /*InsnID*/0, /*NumInsns*/1, /*MergeInsnID's*/0,
        GIR_ConstrainSelectedInstOperands, /*InsnID*/0,
        GIR_EraseFromParent, /*InsnID*/0,
        // GIR_Coverage, 4655,
        GIR_Done,
      // Label 2837: @183469
      GIM_Try, /*On fail goto*//*Label 2838*/ GIMT_Encode4(183525), // Rule ID 7052 //
        GIM_CheckFeatures, GIMT_Encode2(GIFBS_LDSRequiresM0Init),
        GIM_CheckMemoryAddressSpace, /*MI*/0, /*MMO*/0, /*NumAddrSpace*/1, /*AddrSpace*/3,
        GIM_CheckHasNoUse, /*MI*/0,
        GIM_CheckPointerToAny, /*MI*/0, /*Op*/1, /*SizeInBits*/0,
        GIM_CheckComplexPattern, /*MI*/0, /*Op*/1, /*Renderer*/GIMT_Encode2(0), GIMT_Encode2(GICP_gi_ds_1addr_1offset),
        // (atomic_load_umax_glue:{ *:[i64] } (DS1Addr1Offset:{ *:[iPTR] } i32:{ *:[i32] }:$ptr, i32:{ *:[i32] }:$offset), i64:{ *:[i64] }:$value)<<P:Predicate_atomic_load_umax_local_m0_noret_64>>  =>  (DS_MAX_U64 ?:{ *:[i32] }:$ptr, anonymous_15036:{ *:[i64] }:$value, offset:{ *:[i32] }:$offset, 0:{ *:[i1] })
        GIR_BuildMI, /*InsnID*/0, /*Opcode*/GIMT_Encode2(AMDGPU::DS_MAX_U64),
        GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/0, // ptr
        GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/2, // value
        GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/1, // offset
        GIR_AddImm8, /*InsnID*/0, /*Imm*/0,
        GIR_MergeMemOperands, /*InsnID*/0, /*NumInsns*/1, /*MergeInsnID's*/0,
        GIR_ConstrainSelectedInstOperands, /*InsnID*/0,
        GIR_EraseFromParent, /*InsnID*/0,
        // GIR_Coverage, 7052,
        GIR_Done,
      // Label 2838: @183525
      GIM_Try, /*On fail goto*//*Label 2839*/ GIMT_Encode4(183581), // Rule ID 7054 //
        GIM_CheckFeatures, GIMT_Encode2(GIFBS_NotLDSRequiresM0Init),
        GIM_CheckMemoryAddressSpace, /*MI*/0, /*MMO*/0, /*NumAddrSpace*/1, /*AddrSpace*/3,
        GIM_CheckHasNoUse, /*MI*/0,
        GIM_CheckPointerToAny, /*MI*/0, /*Op*/1, /*SizeInBits*/0,
        GIM_CheckComplexPattern, /*MI*/0, /*Op*/1, /*Renderer*/GIMT_Encode2(0), GIMT_Encode2(GICP_gi_ds_1addr_1offset),
        // (atomic_load_umax:{ *:[i64] } (DS1Addr1Offset:{ *:[iPTR] } i32:{ *:[i32] }:$ptr, i32:{ *:[i32] }:$offset), i64:{ *:[i64] }:$value)<<P:Predicate_atomic_load_umax_local_noret_64>>  =>  (DS_MAX_U64_gfx9 ?:{ *:[i32] }:$ptr, anonymous_15036:{ *:[i64] }:$value, offset:{ *:[i32] }:$offset, 0:{ *:[i1] })
        GIR_BuildMI, /*InsnID*/0, /*Opcode*/GIMT_Encode2(AMDGPU::DS_MAX_U64_gfx9),
        GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/0, // ptr
        GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/2, // value
        GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/1, // offset
        GIR_AddImm8, /*InsnID*/0, /*Imm*/0,
        GIR_MergeMemOperands, /*InsnID*/0, /*NumInsns*/1, /*MergeInsnID's*/0,
        GIR_ConstrainSelectedInstOperands, /*InsnID*/0,
        GIR_EraseFromParent, /*InsnID*/0,
        // GIR_Coverage, 7054,
        GIR_Done,
      // Label 2839: @183581
      GIM_Try, /*On fail goto*//*Label 2840*/ GIMT_Encode4(183637), // Rule ID 7056 //
        GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasGDS),
        GIM_CheckMemoryAddressSpace, /*MI*/0, /*MMO*/0, /*NumAddrSpace*/1, /*AddrSpace*/2,
        GIM_CheckHasNoUse, /*MI*/0,
        GIM_CheckPointerToAny, /*MI*/0, /*Op*/1, /*SizeInBits*/0,
        GIM_CheckComplexPattern, /*MI*/0, /*Op*/1, /*Renderer*/GIMT_Encode2(0), GIMT_Encode2(GICP_gi_ds_1addr_1offset),
        // (atomic_load_umax_glue:{ *:[i64] } (DS1Addr1Offset:{ *:[iPTR] } i32:{ *:[i32] }:$ptr, i32:{ *:[i32] }:$offset), i64:{ *:[i64] }:$value)<<P:Predicate_atomic_load_umax_region_m0_noret_64>>  =>  (DS_MAX_U64 ?:{ *:[i32] }:$ptr, anonymous_15036:{ *:[i64] }:$value, offset:{ *:[i32] }:$offset, 1:{ *:[i1] })
        GIR_BuildMI, /*InsnID*/0, /*Opcode*/GIMT_Encode2(AMDGPU::DS_MAX_U64),
        GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/0, // ptr
        GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/2, // value
        GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/1, // offset
        GIR_AddImm8, /*InsnID*/0, /*Imm*/1,
        GIR_MergeMemOperands, /*InsnID*/0, /*NumInsns*/1, /*MergeInsnID's*/0,
        GIR_ConstrainSelectedInstOperands, /*InsnID*/0,
        GIR_EraseFromParent, /*InsnID*/0,
        // GIR_Coverage, 7056,
        GIR_Done,
      // Label 2840: @183637
      GIM_Try, /*On fail goto*//*Label 2841*/ GIMT_Encode4(183700), // Rule ID 7051 //
        GIM_CheckFeatures, GIMT_Encode2(GIFBS_LDSRequiresM0Init),
        GIM_CheckMemoryAddressSpace, /*MI*/0, /*MMO*/0, /*NumAddrSpace*/1, /*AddrSpace*/3,
        GIM_CheckRegBankForClass, /*MI*/0, /*Op*/0, /*RC*/GIMT_Encode2(AMDGPU::AV_64RegClassID),
        GIM_CheckPointerToAny, /*MI*/0, /*Op*/1, /*SizeInBits*/0,
        GIM_CheckComplexPattern, /*MI*/0, /*Op*/1, /*Renderer*/GIMT_Encode2(0), GIMT_Encode2(GICP_gi_ds_1addr_1offset),
        // (atomic_load_umax_glue:{ *:[i64] } (DS1Addr1Offset:{ *:[iPTR] } i32:{ *:[i32] }:$ptr, i32:{ *:[i32] }:$offset), i64:{ *:[i64] }:$value)<<P:Predicate_atomic_load_umax_local_m0_64>>  =>  (DS_MAX_RTN_U64:{ *:[i64] } ?:{ *:[i32] }:$ptr, anonymous_15036:{ *:[i64] }:$value, offset:{ *:[i32] }:$offset, 0:{ *:[i1] })
        GIR_BuildMI, /*InsnID*/0, /*Opcode*/GIMT_Encode2(AMDGPU::DS_MAX_RTN_U64),
        GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/0, // DstI[vdst]
        GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/0, // ptr
        GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/2, // value
        GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/1, // offset
        GIR_AddImm8, /*InsnID*/0, /*Imm*/0,
        GIR_MergeMemOperands, /*InsnID*/0, /*NumInsns*/1, /*MergeInsnID's*/0,
        GIR_ConstrainSelectedInstOperands, /*InsnID*/0,
        GIR_EraseFromParent, /*InsnID*/0,
        // GIR_Coverage, 7051,
        GIR_Done,
      // Label 2841: @183700
      GIM_Try, /*On fail goto*//*Label 2842*/ GIMT_Encode4(183763), // Rule ID 7053 //
        GIM_CheckFeatures, GIMT_Encode2(GIFBS_NotLDSRequiresM0Init),
        GIM_CheckMemoryAddressSpace, /*MI*/0, /*MMO*/0, /*NumAddrSpace*/1, /*AddrSpace*/3,
        GIM_CheckRegBankForClass, /*MI*/0, /*Op*/0, /*RC*/GIMT_Encode2(AMDGPU::AV_64RegClassID),
        GIM_CheckPointerToAny, /*MI*/0, /*Op*/1, /*SizeInBits*/0,
        GIM_CheckComplexPattern, /*MI*/0, /*Op*/1, /*Renderer*/GIMT_Encode2(0), GIMT_Encode2(GICP_gi_ds_1addr_1offset),
        // (atomic_load_umax:{ *:[i64] } (DS1Addr1Offset:{ *:[iPTR] } i32:{ *:[i32] }:$ptr, i32:{ *:[i32] }:$offset), i64:{ *:[i64] }:$value)<<P:Predicate_atomic_load_umax_local_64>>  =>  (DS_MAX_RTN_U64_gfx9:{ *:[i64] } ?:{ *:[i32] }:$ptr, anonymous_15036:{ *:[i64] }:$value, offset:{ *:[i32] }:$offset, 0:{ *:[i1] })
        GIR_BuildMI, /*InsnID*/0, /*Opcode*/GIMT_Encode2(AMDGPU::DS_MAX_RTN_U64_gfx9),
        GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/0, // DstI[vdst]
        GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/0, // ptr
        GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/2, // value
        GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/1, // offset
        GIR_AddImm8, /*InsnID*/0, /*Imm*/0,
        GIR_MergeMemOperands, /*InsnID*/0, /*NumInsns*/1, /*MergeInsnID's*/0,
        GIR_ConstrainSelectedInstOperands, /*InsnID*/0,
        GIR_EraseFromParent, /*InsnID*/0,
        // GIR_Coverage, 7053,
        GIR_Done,
      // Label 2842: @183763
      GIM_Try, /*On fail goto*//*Label 2843*/ GIMT_Encode4(183826), // Rule ID 7055 //
        GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasGDS),
        GIM_CheckMemoryAddressSpace, /*MI*/0, /*MMO*/0, /*NumAddrSpace*/1, /*AddrSpace*/2,
        GIM_CheckRegBankForClass, /*MI*/0, /*Op*/0, /*RC*/GIMT_Encode2(AMDGPU::AV_64RegClassID),
        GIM_CheckPointerToAny, /*MI*/0, /*Op*/1, /*SizeInBits*/0,
        GIM_CheckComplexPattern, /*MI*/0, /*Op*/1, /*Renderer*/GIMT_Encode2(0), GIMT_Encode2(GICP_gi_ds_1addr_1offset),
        // (atomic_load_umax_glue:{ *:[i64] } (DS1Addr1Offset:{ *:[iPTR] } i32:{ *:[i32] }:$ptr, i32:{ *:[i32] }:$offset), i64:{ *:[i64] }:$value)<<P:Predicate_atomic_load_umax_region_m0_64>>  =>  (DS_MAX_RTN_U64:{ *:[i64] } ?:{ *:[i32] }:$ptr, anonymous_15036:{ *:[i64] }:$value, offset:{ *:[i32] }:$offset, 1:{ *:[i1] })
        GIR_BuildMI, /*InsnID*/0, /*Opcode*/GIMT_Encode2(AMDGPU::DS_MAX_RTN_U64),
        GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/0, // DstI[vdst]
        GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/0, // ptr
        GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/2, // value
        GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/1, // offset
        GIR_AddImm8, /*InsnID*/0, /*Imm*/1,
        GIR_MergeMemOperands, /*InsnID*/0, /*NumInsns*/1, /*MergeInsnID's*/0,
        GIR_ConstrainSelectedInstOperands, /*InsnID*/0,
        GIR_EraseFromParent, /*InsnID*/0,
        // GIR_Coverage, 7055,
        GIR_Done,
      // Label 2843: @183826
      GIM_Try, /*On fail goto*//*Label 2844*/ GIMT_Encode4(183889), // Rule ID 3227 //
        GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasFlatGlobalInsts),
        GIM_CheckMemoryAddressSpace, /*MI*/0, /*MMO*/0, /*NumAddrSpace*/3, /*AddrSpace*/1, /*AddrSpace*/4, /*AddrSpace*/6,
        GIM_CheckHasNoUse, /*MI*/0,
        GIM_CheckPointerToAny, /*MI*/0, /*Op*/1, /*SizeInBits*/0,
        GIM_CheckComplexPattern, /*MI*/0, /*Op*/1, /*Renderer*/GIMT_Encode2(0), GIMT_Encode2(GICP_gi_global_saddr),
        // (atomic_load_umax:{ *:[i64] } (GlobalSAddr:{ *:[iPTR] } SReg_64:{ *:[i64] }:$saddr, VGPR_32:{ *:[i32] }:$voffset, i32:{ *:[i32] }:$offset), i64:{ *:[i64] }:$data)<<P:Predicate_atomic_load_umax_global_noret_64>>  =>  (GLOBAL_ATOMIC_UMAX_X2_SADDR ?:{ *:[i32] }:$voffset, anonymous_15036:{ *:[i64] }:$data, ?:{ *:[i64] }:$saddr, ?:{ *:[i32] }:$offset)
        GIR_BuildMI, /*InsnID*/0, /*Opcode*/GIMT_Encode2(AMDGPU::GLOBAL_ATOMIC_UMAX_X2_SADDR),
        GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/1, // voffset
        GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/2, // data
        GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/0, // saddr
        GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/2, // offset
        GIR_AddImm8, /*InsnID*/0, /*Imm*/0,
        GIR_MergeMemOperands, /*InsnID*/0, /*NumInsns*/1, /*MergeInsnID's*/0,
        GIR_ConstrainSelectedInstOperands, /*InsnID*/0,
        GIR_EraseFromParent, /*InsnID*/0,
        // GIR_Coverage, 3227,
        GIR_Done,
      // Label 2844: @183889
      GIM_Try, /*On fail goto*//*Label 2845*/ GIMT_Encode4(183959), // Rule ID 3229 //
        GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasFlatGlobalInsts),
        GIM_CheckMemoryAddressSpace, /*MI*/0, /*MMO*/0, /*NumAddrSpace*/3, /*AddrSpace*/1, /*AddrSpace*/4, /*AddrSpace*/6,
        GIM_CheckRegBankForClass, /*MI*/0, /*Op*/0, /*RC*/GIMT_Encode2(AMDGPU::AV_64RegClassID),
        GIM_CheckPointerToAny, /*MI*/0, /*Op*/1, /*SizeInBits*/0,
        GIM_CheckComplexPattern, /*MI*/0, /*Op*/1, /*Renderer*/GIMT_Encode2(0), GIMT_Encode2(GICP_gi_global_saddr),
        // (atomic_load_umax:{ *:[i64] } (GlobalSAddr:{ *:[iPTR] } SReg_64:{ *:[i64] }:$saddr, VGPR_32:{ *:[i32] }:$voffset, i32:{ *:[i32] }:$offset), i64:{ *:[i64] }:$data)<<P:Predicate_atomic_load_umax_global_64>>  =>  (GLOBAL_ATOMIC_UMAX_X2_SADDR_RTN:{ *:[i64] } ?:{ *:[i32] }:$voffset, anonymous_15036:{ *:[i64] }:$data, ?:{ *:[i64] }:$saddr, ?:{ *:[i32] }:$offset)
        GIR_BuildMI, /*InsnID*/0, /*Opcode*/GIMT_Encode2(AMDGPU::GLOBAL_ATOMIC_UMAX_X2_SADDR_RTN),
        GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/0, // DstI[vdst]
        GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/1, // voffset
        GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/2, // data
        GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/0, // saddr
        GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/2, // offset
        GIR_AddImm8, /*InsnID*/0, /*Imm*/1,
        GIR_MergeMemOperands, /*InsnID*/0, /*NumInsns*/1, /*MergeInsnID's*/0,
        GIR_ConstrainSelectedInstOperands, /*InsnID*/0,
        GIR_EraseFromParent, /*InsnID*/0,
        // GIR_Coverage, 3229,
        GIR_Done,
      // Label 2845: @183959
      GIM_Try, /*On fail goto*//*Label 2846*/ GIMT_Encode4(184017), // Rule ID 3226 //
        GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasFlatGlobalInsts),
        GIM_CheckMemoryAddressSpace, /*MI*/0, /*MMO*/0, /*NumAddrSpace*/3, /*AddrSpace*/1, /*AddrSpace*/4, /*AddrSpace*/6,
        GIM_CheckHasNoUse, /*MI*/0,
        GIM_CheckPointerToAny, /*MI*/0, /*Op*/1, /*SizeInBits*/0,
        GIM_CheckComplexPattern, /*MI*/0, /*Op*/1, /*Renderer*/GIMT_Encode2(0), GIMT_Encode2(GICP_gi_global_offset),
        // (atomic_load_umax:{ *:[i64] } (GlobalOffset:{ *:[iPTR] } i64:{ *:[i64] }:$vaddr, i32:{ *:[i32] }:$offset), i64:{ *:[i64] }:$data)<<P:Predicate_atomic_load_umax_global_noret_64>>  =>  (GLOBAL_ATOMIC_UMAX_X2 VReg_64:{ *:[i64] }:$vaddr, anonymous_15036:{ *:[i64] }:$data, ?:{ *:[i32] }:$offset)
        GIR_BuildMI, /*InsnID*/0, /*Opcode*/GIMT_Encode2(AMDGPU::GLOBAL_ATOMIC_UMAX_X2),
        GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/0, // vaddr
        GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/2, // data
        GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/1, // offset
        GIR_AddImm8, /*InsnID*/0, /*Imm*/0,
        GIR_MergeMemOperands, /*InsnID*/0, /*NumInsns*/1, /*MergeInsnID's*/0,
        GIR_ConstrainSelectedInstOperands, /*InsnID*/0,
        GIR_EraseFromParent, /*InsnID*/0,
        // GIR_Coverage, 3226,
        GIR_Done,
      // Label 2846: @184017
      GIM_Try, /*On fail goto*//*Label 2847*/ GIMT_Encode4(184082), // Rule ID 3228 //
        GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasFlatGlobalInsts),
        GIM_CheckMemoryAddressSpace, /*MI*/0, /*MMO*/0, /*NumAddrSpace*/3, /*AddrSpace*/1, /*AddrSpace*/4, /*AddrSpace*/6,
        GIM_CheckRegBankForClass, /*MI*/0, /*Op*/0, /*RC*/GIMT_Encode2(AMDGPU::AV_64RegClassID),
        GIM_CheckPointerToAny, /*MI*/0, /*Op*/1, /*SizeInBits*/0,
        GIM_CheckComplexPattern, /*MI*/0, /*Op*/1, /*Renderer*/GIMT_Encode2(0), GIMT_Encode2(GICP_gi_global_offset),
        // (atomic_load_umax:{ *:[i64] } (GlobalOffset:{ *:[iPTR] } i64:{ *:[i64] }:$vaddr, i32:{ *:[i32] }:$offset), i64:{ *:[i64] }:$data)<<P:Predicate_atomic_load_umax_global_64>>  =>  (GLOBAL_ATOMIC_UMAX_X2_RTN:{ *:[i64] } VReg_64:{ *:[i64] }:$vaddr, anonymous_15036:{ *:[i64] }:$data, ?:{ *:[i32] }:$offset)
        GIR_BuildMI, /*InsnID*/0, /*Opcode*/GIMT_Encode2(AMDGPU::GLOBAL_ATOMIC_UMAX_X2_RTN),
        GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/0, // DstI[vdst]
        GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/0, // vaddr
        GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/2, // data
        GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/1, // offset
        GIR_AddImm8, /*InsnID*/0, /*Imm*/1,
        GIR_MergeMemOperands, /*InsnID*/0, /*NumInsns*/1, /*MergeInsnID's*/0,
        GIR_ConstrainSelectedInstOperands, /*InsnID*/0,
        GIR_EraseFromParent, /*InsnID*/0,
        // GIR_Coverage, 3228,
        GIR_Done,
      // Label 2847: @184082
      GIM_Try, /*On fail goto*//*Label 2848*/ GIMT_Encode4(184141), // Rule ID 2866 //
        GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasFlatAddressSpace),
        GIM_CheckMemoryAddressSpace, /*MI*/0, /*MMO*/0, /*NumAddrSpace*/4, /*AddrSpace*/0, /*AddrSpace*/1, /*AddrSpace*/4, /*AddrSpace*/6,
        GIM_CheckHasNoUse, /*MI*/0,
        GIM_CheckPointerToAny, /*MI*/0, /*Op*/1, /*SizeInBits*/0,
        GIM_CheckComplexPattern, /*MI*/0, /*Op*/1, /*Renderer*/GIMT_Encode2(0), GIMT_Encode2(GICP_gi_flat_offset),
        // (atomic_load_umax:{ *:[i64] } (FlatOffset:{ *:[iPTR] } i64:{ *:[i64] }:$vaddr, i32:{ *:[i32] }:$offset), i64:{ *:[i64] }:$data)<<P:Predicate_atomic_load_umax_flat_noret_64>>  =>  (FLAT_ATOMIC_UMAX_X2 VReg_64:{ *:[i64] }:$vaddr, anonymous_15036:{ *:[i64] }:$data, ?:{ *:[i32] }:$offset)
        GIR_BuildMI, /*InsnID*/0, /*Opcode*/GIMT_Encode2(AMDGPU::FLAT_ATOMIC_UMAX_X2),
        GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/0, // vaddr
        GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/2, // data
        GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/1, // offset
        GIR_AddImm8, /*InsnID*/0, /*Imm*/0,
        GIR_MergeMemOperands, /*InsnID*/0, /*NumInsns*/1, /*MergeInsnID's*/0,
        GIR_ConstrainSelectedInstOperands, /*InsnID*/0,
        GIR_EraseFromParent, /*InsnID*/0,
        // GIR_Coverage, 2866,
        GIR_Done,
      // Label 2848: @184141
      GIM_Try, /*On fail goto*//*Label 2849*/ GIMT_Encode4(184199), // Rule ID 2918 //
        GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasFlatAddressSpace),
        GIM_CheckMemoryAddressSpace, /*MI*/0, /*MMO*/0, /*NumAddrSpace*/3, /*AddrSpace*/1, /*AddrSpace*/4, /*AddrSpace*/6,
        GIM_CheckHasNoUse, /*MI*/0,
        GIM_CheckPointerToAny, /*MI*/0, /*Op*/1, /*SizeInBits*/0,
        GIM_CheckComplexPattern, /*MI*/0, /*Op*/1, /*Renderer*/GIMT_Encode2(0), GIMT_Encode2(GICP_gi_flat_offset),
        // (atomic_load_umax:{ *:[i64] } (FlatOffset:{ *:[iPTR] } i64:{ *:[i64] }:$vaddr, i32:{ *:[i32] }:$offset), i64:{ *:[i64] }:$data)<<P:Predicate_atomic_load_umax_global_noret_64>>  =>  (FLAT_ATOMIC_UMAX_X2 VReg_64:{ *:[i64] }:$vaddr, anonymous_15036:{ *:[i64] }:$data, ?:{ *:[i32] }:$offset)
        GIR_BuildMI, /*InsnID*/0, /*Opcode*/GIMT_Encode2(AMDGPU::FLAT_ATOMIC_UMAX_X2),
        GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/0, // vaddr
        GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/2, // data
        GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/1, // offset
        GIR_AddImm8, /*InsnID*/0, /*Imm*/0,
        GIR_MergeMemOperands, /*InsnID*/0, /*NumInsns*/1, /*MergeInsnID's*/0,
        GIR_ConstrainSelectedInstOperands, /*InsnID*/0,
        GIR_EraseFromParent, /*InsnID*/0,
        // GIR_Coverage, 2918,
        GIR_Done,
      // Label 2849: @184199
      GIM_Try, /*On fail goto*//*Label 2850*/ GIMT_Encode4(184265), // Rule ID 2865 //
        GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasFlatAddressSpace),
        GIM_CheckMemoryAddressSpace, /*MI*/0, /*MMO*/0, /*NumAddrSpace*/4, /*AddrSpace*/0, /*AddrSpace*/1, /*AddrSpace*/4, /*AddrSpace*/6,
        GIM_CheckRegBankForClass, /*MI*/0, /*Op*/0, /*RC*/GIMT_Encode2(AMDGPU::AV_64RegClassID),
        GIM_CheckPointerToAny, /*MI*/0, /*Op*/1, /*SizeInBits*/0,
        GIM_CheckComplexPattern, /*MI*/0, /*Op*/1, /*Renderer*/GIMT_Encode2(0), GIMT_Encode2(GICP_gi_flat_offset),
        // (atomic_load_umax:{ *:[i64] } (FlatOffset:{ *:[iPTR] } i64:{ *:[i64] }:$vaddr, i32:{ *:[i32] }:$offset), i64:{ *:[i64] }:$data)<<P:Predicate_atomic_load_umax_flat_64>>  =>  (FLAT_ATOMIC_UMAX_X2_RTN:{ *:[i64] } VReg_64:{ *:[i64] }:$vaddr, anonymous_15036:{ *:[i64] }:$data, ?:{ *:[i32] }:$offset)
        GIR_BuildMI, /*InsnID*/0, /*Opcode*/GIMT_Encode2(AMDGPU::FLAT_ATOMIC_UMAX_X2_RTN),
        GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/0, // DstI[vdst]
        GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/0, // vaddr
        GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/2, // data
        GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/1, // offset
        GIR_AddImm8, /*InsnID*/0, /*Imm*/1,
        GIR_MergeMemOperands, /*InsnID*/0, /*NumInsns*/1, /*MergeInsnID's*/0,
        GIR_ConstrainSelectedInstOperands, /*InsnID*/0,
        GIR_EraseFromParent, /*InsnID*/0,
        // GIR_Coverage, 2865,
        GIR_Done,
      // Label 2850: @184265
      GIM_Try, /*On fail goto*//*Label 2851*/ GIMT_Encode4(184330), // Rule ID 2917 //
        GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasFlatAddressSpace),
        GIM_CheckMemoryAddressSpace, /*MI*/0, /*MMO*/0, /*NumAddrSpace*/3, /*AddrSpace*/1, /*AddrSpace*/4, /*AddrSpace*/6,
        GIM_CheckRegBankForClass, /*MI*/0, /*Op*/0, /*RC*/GIMT_Encode2(AMDGPU::AV_64RegClassID),
        GIM_CheckPointerToAny, /*MI*/0, /*Op*/1, /*SizeInBits*/0,
        GIM_CheckComplexPattern, /*MI*/0, /*Op*/1, /*Renderer*/GIMT_Encode2(0), GIMT_Encode2(GICP_gi_flat_offset),
        // (atomic_load_umax:{ *:[i64] } (FlatOffset:{ *:[iPTR] } i64:{ *:[i64] }:$vaddr, i32:{ *:[i32] }:$offset), i64:{ *:[i64] }:$data)<<P:Predicate_atomic_load_umax_global_64>>  =>  (FLAT_ATOMIC_UMAX_X2_RTN:{ *:[i64] } VReg_64:{ *:[i64] }:$vaddr, anonymous_15036:{ *:[i64] }:$data, ?:{ *:[i32] }:$offset)
        GIR_BuildMI, /*InsnID*/0, /*Opcode*/GIMT_Encode2(AMDGPU::FLAT_ATOMIC_UMAX_X2_RTN),
        GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/0, // DstI[vdst]
        GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/0, // vaddr
        GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/2, // data
        GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/1, // offset
        GIR_AddImm8, /*InsnID*/0, /*Imm*/1,
        GIR_MergeMemOperands, /*InsnID*/0, /*NumInsns*/1, /*MergeInsnID's*/0,
        GIR_ConstrainSelectedInstOperands, /*InsnID*/0,
        GIR_EraseFromParent, /*InsnID*/0,
        // GIR_Coverage, 2917,
        GIR_Done,
      // Label 2851: @184330
      GIM_Reject,
    // Label 2829: @184331
    GIM_Reject,
    // Label 2805: @184332
    GIM_Reject,
    // Label 26: @184333
    GIM_SwitchType, /*MI*/0, /*Op*/0, /*[*/GIMT_Encode2(9), GIMT_Encode2(11), /*)*//*default:*//*Label 2854*/ GIMT_Encode4(187176),
    /*GILLT_s32*//*Label 2852*/ GIMT_Encode4(184352),
    /*GILLT_s64*//*Label 2853*/ GIMT_Encode4(185764),
    // Label 2852: @184352
    GIM_Try, /*On fail goto*//*Label 2855*/ GIMT_Encode4(185763),
      GIM_CheckType, /*MI*/0, /*Op*/2, /*Type*/GILLT_s32,
      GIM_Try, /*On fail goto*//*Label 2856*/ GIMT_Encode4(184429), // Rule ID 4542 //
        GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasUnrestrictedSOffset),
        GIM_CheckMemoryAddressSpace, /*MI*/0, /*MMO*/0, /*NumAddrSpace*/3, /*AddrSpace*/1, /*AddrSpace*/4, /*AddrSpace*/6,
        GIM_CheckHasNoUse, /*MI*/0,
        GIM_CheckPointerToAny, /*MI*/0, /*Op*/1, /*SizeInBits*/0,
        GIM_CheckComplexPattern, /*MI*/0, /*Op*/1, /*Renderer*/GIMT_Encode2(0), GIMT_Encode2(GICP_gi_mubuf_addr64),
        // (atomic_load_umin:{ *:[i32] } (MUBUFAddr64:{ *:[iPTR] } v4i32:{ *:[v4i32] }:$srsrc, i64:{ *:[i64] }:$vaddr, i32:{ *:[i32] }:$soffset, i32:{ *:[i32] }:$offset), i32:{ *:[i32] }:$vdata_in)<<P:Predicate_atomic_load_umin_global_noret_32>>  =>  (BUFFER_ATOMIC_UMIN_ADDR64 anonymous_15037:{ *:[i32] }:$vdata_in, VReg_64:{ *:[i64] }:$vaddr, SReg_128:{ *:[v4i32] }:$srsrc, SCSrc_b32:{ *:[i32] }:$soffset, offset:{ *:[i32] }:$offset)
        GIR_BuildMI, /*InsnID*/0, /*Opcode*/GIMT_Encode2(AMDGPU::BUFFER_ATOMIC_UMIN_ADDR64),
        GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/2, // vdata_in
        GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/1, // vaddr
        GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/0, // srsrc
        GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/2, // soffset
        GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/3, // offset
        GIR_AddImm8, /*InsnID*/0, /*Imm*/0,
        GIR_MergeMemOperands, /*InsnID*/0, /*NumInsns*/1, /*MergeInsnID's*/0,
        GIR_ConstrainSelectedInstOperands, /*InsnID*/0,
        GIR_EraseFromParent, /*InsnID*/0,
        // GIR_Coverage, 4542,
        GIR_Done,
      // Label 2856: @184429
      GIM_Try, /*On fail goto*//*Label 2857*/ GIMT_Encode4(184494), // Rule ID 4546 //
        GIM_CheckMemoryAddressSpace, /*MI*/0, /*MMO*/0, /*NumAddrSpace*/3, /*AddrSpace*/1, /*AddrSpace*/4, /*AddrSpace*/6,
        GIM_CheckHasNoUse, /*MI*/0,
        GIM_CheckPointerToAny, /*MI*/0, /*Op*/1, /*SizeInBits*/0,
        GIM_CheckComplexPattern, /*MI*/0, /*Op*/1, /*Renderer*/GIMT_Encode2(0), GIMT_Encode2(GICP_gi_mubuf_addr64),
        // (atomic_load_umin:{ *:[i32] } (MUBUFAddr64:{ *:[iPTR] } v4i32:{ *:[v4i32] }:$srsrc, i64:{ *:[i64] }:$vaddr, i32:{ *:[i32] }:$soffset, i32:{ *:[i32] }:$offset), i32:{ *:[i32] }:$vdata_in)<<P:Predicate_atomic_load_umin_global_noret_32>>  =>  (BUFFER_ATOMIC_UMIN_VBUFFER_ADDR64 anonymous_15037:{ *:[i32] }:$vdata_in, VReg_64:{ *:[i64] }:$vaddr, SReg_128:{ *:[v4i32] }:$srsrc, SCSrc_b32:{ *:[i32] }:$soffset, offset:{ *:[i32] }:$offset)
        GIR_BuildMI, /*InsnID*/0, /*Opcode*/GIMT_Encode2(AMDGPU::BUFFER_ATOMIC_UMIN_VBUFFER_ADDR64),
        GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/2, // vdata_in
        GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/1, // vaddr
        GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/0, // srsrc
        GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/2, // soffset
        GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/3, // offset
        GIR_AddImm8, /*InsnID*/0, /*Imm*/0,
        GIR_MergeMemOperands, /*InsnID*/0, /*NumInsns*/1, /*MergeInsnID's*/0,
        GIR_ConstrainSelectedInstOperands, /*InsnID*/0,
        GIR_EraseFromParent, /*InsnID*/0,
        // GIR_Coverage, 4546,
        GIR_Done,
      // Label 2857: @184494
      GIM_Try, /*On fail goto*//*Label 2858*/ GIMT_Encode4(184569), // Rule ID 4540 //
        GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasUnrestrictedSOffset),
        GIM_CheckMemoryAddressSpace, /*MI*/0, /*MMO*/0, /*NumAddrSpace*/3, /*AddrSpace*/1, /*AddrSpace*/4, /*AddrSpace*/6,
        GIM_CheckRegBankForClass, /*MI*/0, /*Op*/0, /*RC*/GIMT_Encode2(AMDGPU::AV_32RegClassID),
        GIM_CheckPointerToAny, /*MI*/0, /*Op*/1, /*SizeInBits*/0,
        GIM_CheckComplexPattern, /*MI*/0, /*Op*/1, /*Renderer*/GIMT_Encode2(0), GIMT_Encode2(GICP_gi_mubuf_addr64),
        // (atomic_load_umin:{ *:[i32] } (MUBUFAddr64:{ *:[iPTR] } v4i32:{ *:[v4i32] }:$srsrc, i64:{ *:[i64] }:$vaddr, i32:{ *:[i32] }:$soffset, i32:{ *:[i32] }:$offset), i32:{ *:[i32] }:$vdata_in)<<P:Predicate_atomic_load_umin_global_32>>  =>  (BUFFER_ATOMIC_UMIN_ADDR64_RTN:{ *:[i32] } anonymous_15037:{ *:[i32] }:$vdata_in, VReg_64:{ *:[i64] }:$vaddr, SReg_128:{ *:[v4i32] }:$srsrc, SCSrc_b32:{ *:[i32] }:$soffset, offset:{ *:[i32] }:$offset)
        GIR_BuildMI, /*InsnID*/0, /*Opcode*/GIMT_Encode2(AMDGPU::BUFFER_ATOMIC_UMIN_ADDR64_RTN),
        GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/0, // DstI[vdata]
        GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/2, // vdata_in
        GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/1, // vaddr
        GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/0, // srsrc
        GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/2, // soffset
        GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/3, // offset
        GIR_AddImm8, /*InsnID*/0, /*Imm*/1,
        GIR_MergeMemOperands, /*InsnID*/0, /*NumInsns*/1, /*MergeInsnID's*/0,
        GIR_ConstrainSelectedInstOperands, /*InsnID*/0,
        GIR_EraseFromParent, /*InsnID*/0,
        // GIR_Coverage, 4540,
        GIR_Done,
      // Label 2858: @184569
      GIM_Try, /*On fail goto*//*Label 2859*/ GIMT_Encode4(184641), // Rule ID 4544 //
        GIM_CheckMemoryAddressSpace, /*MI*/0, /*MMO*/0, /*NumAddrSpace*/3, /*AddrSpace*/1, /*AddrSpace*/4, /*AddrSpace*/6,
        GIM_CheckRegBankForClass, /*MI*/0, /*Op*/0, /*RC*/GIMT_Encode2(AMDGPU::AV_32RegClassID),
        GIM_CheckPointerToAny, /*MI*/0, /*Op*/1, /*SizeInBits*/0,
        GIM_CheckComplexPattern, /*MI*/0, /*Op*/1, /*Renderer*/GIMT_Encode2(0), GIMT_Encode2(GICP_gi_mubuf_addr64),
        // (atomic_load_umin:{ *:[i32] } (MUBUFAddr64:{ *:[iPTR] } v4i32:{ *:[v4i32] }:$srsrc, i64:{ *:[i64] }:$vaddr, i32:{ *:[i32] }:$soffset, i32:{ *:[i32] }:$offset), i32:{ *:[i32] }:$vdata_in)<<P:Predicate_atomic_load_umin_global_32>>  =>  (BUFFER_ATOMIC_UMIN_VBUFFER_ADDR64_RTN:{ *:[i32] } anonymous_15037:{ *:[i32] }:$vdata_in, VReg_64:{ *:[i64] }:$vaddr, SReg_128:{ *:[v4i32] }:$srsrc, SCSrc_b32:{ *:[i32] }:$soffset, offset:{ *:[i32] }:$offset)
        GIR_BuildMI, /*InsnID*/0, /*Opcode*/GIMT_Encode2(AMDGPU::BUFFER_ATOMIC_UMIN_VBUFFER_ADDR64_RTN),
        GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/0, // DstI[vdata]
        GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/2, // vdata_in
        GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/1, // vaddr
        GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/0, // srsrc
        GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/2, // soffset
        GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/3, // offset
        GIR_AddImm8, /*InsnID*/0, /*Imm*/1,
        GIR_MergeMemOperands, /*InsnID*/0, /*NumInsns*/1, /*MergeInsnID's*/0,
        GIR_ConstrainSelectedInstOperands, /*InsnID*/0,
        GIR_EraseFromParent, /*InsnID*/0,
        // GIR_Coverage, 4544,
        GIR_Done,
      // Label 2859: @184641
      GIM_Try, /*On fail goto*//*Label 2860*/ GIMT_Encode4(184704), // Rule ID 4541 //
        GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasUnrestrictedSOffset),
        GIM_CheckMemoryAddressSpace, /*MI*/0, /*MMO*/0, /*NumAddrSpace*/3, /*AddrSpace*/1, /*AddrSpace*/4, /*AddrSpace*/6,
        GIM_CheckHasNoUse, /*MI*/0,
        GIM_CheckPointerToAny, /*MI*/0, /*Op*/1, /*SizeInBits*/0,
        GIM_CheckComplexPattern, /*MI*/0, /*Op*/1, /*Renderer*/GIMT_Encode2(0), GIMT_Encode2(GICP_gi_mubuf_offset),
        // (atomic_load_umin:{ *:[i32] } (MUBUFOffset:{ *:[iPTR] } v4i32:{ *:[v4i32] }:$srsrc, i32:{ *:[i32] }:$soffset, i32:{ *:[i32] }:$offset), i32:{ *:[i32] }:$vdata_in)<<P:Predicate_atomic_load_umin_global_noret_32>>  =>  (BUFFER_ATOMIC_UMIN_OFFSET anonymous_15037:{ *:[i32] }:$vdata_in, SReg_128:{ *:[v4i32] }:$srsrc, SCSrc_b32:{ *:[i32] }:$soffset, offset:{ *:[i32] }:$offset)
        GIR_BuildMI, /*InsnID*/0, /*Opcode*/GIMT_Encode2(AMDGPU::BUFFER_ATOMIC_UMIN_OFFSET),
        GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/2, // vdata_in
        GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/0, // srsrc
        GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/1, // soffset
        GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/2, // offset
        GIR_AddImm8, /*InsnID*/0, /*Imm*/0,
        GIR_MergeMemOperands, /*InsnID*/0, /*NumInsns*/1, /*MergeInsnID's*/0,
        GIR_ConstrainSelectedInstOperands, /*InsnID*/0,
        GIR_EraseFromParent, /*InsnID*/0,
        // GIR_Coverage, 4541,
        GIR_Done,
      // Label 2860: @184704
      GIM_Try, /*On fail goto*//*Label 2861*/ GIMT_Encode4(184764), // Rule ID 4545 //
        GIM_CheckMemoryAddressSpace, /*MI*/0, /*MMO*/0, /*NumAddrSpace*/3, /*AddrSpace*/1, /*AddrSpace*/4, /*AddrSpace*/6,
        GIM_CheckHasNoUse, /*MI*/0,
        GIM_CheckPointerToAny, /*MI*/0, /*Op*/1, /*SizeInBits*/0,
        GIM_CheckComplexPattern, /*MI*/0, /*Op*/1, /*Renderer*/GIMT_Encode2(0), GIMT_Encode2(GICP_gi_mubuf_offset),
        // (atomic_load_umin:{ *:[i32] } (MUBUFOffset:{ *:[iPTR] } v4i32:{ *:[v4i32] }:$srsrc, i32:{ *:[i32] }:$soffset, i32:{ *:[i32] }:$offset), i32:{ *:[i32] }:$vdata_in)<<P:Predicate_atomic_load_umin_global_noret_32>>  =>  (BUFFER_ATOMIC_UMIN_VBUFFER_OFFSET anonymous_15037:{ *:[i32] }:$vdata_in, SReg_128:{ *:[v4i32] }:$srsrc, SCSrc_b32:{ *:[i32] }:$soffset, offset:{ *:[i32] }:$offset)
        GIR_BuildMI, /*InsnID*/0, /*Opcode*/GIMT_Encode2(AMDGPU::BUFFER_ATOMIC_UMIN_VBUFFER_OFFSET),
        GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/2, // vdata_in
        GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/0, // srsrc
        GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/1, // soffset
        GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/2, // offset
        GIR_AddImm8, /*InsnID*/0, /*Imm*/0,
        GIR_MergeMemOperands, /*InsnID*/0, /*NumInsns*/1, /*MergeInsnID's*/0,
        GIR_ConstrainSelectedInstOperands, /*InsnID*/0,
        GIR_EraseFromParent, /*InsnID*/0,
        // GIR_Coverage, 4545,
        GIR_Done,
      // Label 2861: @184764
      GIM_Try, /*On fail goto*//*Label 2862*/ GIMT_Encode4(184834), // Rule ID 4539 //
        GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasUnrestrictedSOffset),
        GIM_CheckMemoryAddressSpace, /*MI*/0, /*MMO*/0, /*NumAddrSpace*/3, /*AddrSpace*/1, /*AddrSpace*/4, /*AddrSpace*/6,
        GIM_CheckRegBankForClass, /*MI*/0, /*Op*/0, /*RC*/GIMT_Encode2(AMDGPU::AV_32RegClassID),
        GIM_CheckPointerToAny, /*MI*/0, /*Op*/1, /*SizeInBits*/0,
        GIM_CheckComplexPattern, /*MI*/0, /*Op*/1, /*Renderer*/GIMT_Encode2(0), GIMT_Encode2(GICP_gi_mubuf_offset),
        // (atomic_load_umin:{ *:[i32] } (MUBUFOffset:{ *:[iPTR] } v4i32:{ *:[v4i32] }:$srsrc, i32:{ *:[i32] }:$soffset, i32:{ *:[i32] }:$offset), i32:{ *:[i32] }:$vdata_in)<<P:Predicate_atomic_load_umin_global_32>>  =>  (BUFFER_ATOMIC_UMIN_OFFSET_RTN:{ *:[i32] } anonymous_15037:{ *:[i32] }:$vdata_in, SReg_128:{ *:[v4i32] }:$srsrc, SCSrc_b32:{ *:[i32] }:$soffset, offset:{ *:[i32] }:$offset)
        GIR_BuildMI, /*InsnID*/0, /*Opcode*/GIMT_Encode2(AMDGPU::BUFFER_ATOMIC_UMIN_OFFSET_RTN),
        GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/0, // DstI[vdata]
        GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/2, // vdata_in
        GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/0, // srsrc
        GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/1, // soffset
        GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/2, // offset
        GIR_AddImm8, /*InsnID*/0, /*Imm*/1,
        GIR_MergeMemOperands, /*InsnID*/0, /*NumInsns*/1, /*MergeInsnID's*/0,
        GIR_ConstrainSelectedInstOperands, /*InsnID*/0,
        GIR_EraseFromParent, /*InsnID*/0,
        // GIR_Coverage, 4539,
        GIR_Done,
      // Label 2862: @184834
      GIM_Try, /*On fail goto*//*Label 2863*/ GIMT_Encode4(184901), // Rule ID 4543 //
        GIM_CheckMemoryAddressSpace, /*MI*/0, /*MMO*/0, /*NumAddrSpace*/3, /*AddrSpace*/1, /*AddrSpace*/4, /*AddrSpace*/6,
        GIM_CheckRegBankForClass, /*MI*/0, /*Op*/0, /*RC*/GIMT_Encode2(AMDGPU::AV_32RegClassID),
        GIM_CheckPointerToAny, /*MI*/0, /*Op*/1, /*SizeInBits*/0,
        GIM_CheckComplexPattern, /*MI*/0, /*Op*/1, /*Renderer*/GIMT_Encode2(0), GIMT_Encode2(GICP_gi_mubuf_offset),
        // (atomic_load_umin:{ *:[i32] } (MUBUFOffset:{ *:[iPTR] } v4i32:{ *:[v4i32] }:$srsrc, i32:{ *:[i32] }:$soffset, i32:{ *:[i32] }:$offset), i32:{ *:[i32] }:$vdata_in)<<P:Predicate_atomic_load_umin_global_32>>  =>  (BUFFER_ATOMIC_UMIN_VBUFFER_OFFSET_RTN:{ *:[i32] } anonymous_15037:{ *:[i32] }:$vdata_in, SReg_128:{ *:[v4i32] }:$srsrc, SCSrc_b32:{ *:[i32] }:$soffset, offset:{ *:[i32] }:$offset)
        GIR_BuildMI, /*InsnID*/0, /*Opcode*/GIMT_Encode2(AMDGPU::BUFFER_ATOMIC_UMIN_VBUFFER_OFFSET_RTN),
        GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/0, // DstI[vdata]
        GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/2, // vdata_in
        GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/0, // srsrc
        GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/1, // soffset
        GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/2, // offset
        GIR_AddImm8, /*InsnID*/0, /*Imm*/1,
        GIR_MergeMemOperands, /*InsnID*/0, /*NumInsns*/1, /*MergeInsnID's*/0,
        GIR_ConstrainSelectedInstOperands, /*InsnID*/0,
        GIR_EraseFromParent, /*InsnID*/0,
        // GIR_Coverage, 4543,
        GIR_Done,
      // Label 2863: @184901
      GIM_Try, /*On fail goto*//*Label 2864*/ GIMT_Encode4(184957), // Rule ID 6959 //
        GIM_CheckFeatures, GIMT_Encode2(GIFBS_LDSRequiresM0Init),
        GIM_CheckMemoryAddressSpace, /*MI*/0, /*MMO*/0, /*NumAddrSpace*/1, /*AddrSpace*/3,
        GIM_CheckHasNoUse, /*MI*/0,
        GIM_CheckPointerToAny, /*MI*/0, /*Op*/1, /*SizeInBits*/0,
        GIM_CheckComplexPattern, /*MI*/0, /*Op*/1, /*Renderer*/GIMT_Encode2(0), GIMT_Encode2(GICP_gi_ds_1addr_1offset),
        // (atomic_load_umin_glue:{ *:[i32] } (DS1Addr1Offset:{ *:[iPTR] } i32:{ *:[i32] }:$ptr, i32:{ *:[i32] }:$offset), i32:{ *:[i32] }:$value)<<P:Predicate_atomic_load_umin_local_m0_noret_32>>  =>  (DS_MIN_U32 ?:{ *:[i32] }:$ptr, anonymous_15037:{ *:[i32] }:$value, offset:{ *:[i32] }:$offset, 0:{ *:[i1] })
        GIR_BuildMI, /*InsnID*/0, /*Opcode*/GIMT_Encode2(AMDGPU::DS_MIN_U32),
        GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/0, // ptr
        GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/2, // value
        GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/1, // offset
        GIR_AddImm8, /*InsnID*/0, /*Imm*/0,
        GIR_MergeMemOperands, /*InsnID*/0, /*NumInsns*/1, /*MergeInsnID's*/0,
        GIR_ConstrainSelectedInstOperands, /*InsnID*/0,
        GIR_EraseFromParent, /*InsnID*/0,
        // GIR_Coverage, 6959,
        GIR_Done,
      // Label 2864: @184957
      GIM_Try, /*On fail goto*//*Label 2865*/ GIMT_Encode4(185013), // Rule ID 6961 //
        GIM_CheckFeatures, GIMT_Encode2(GIFBS_NotLDSRequiresM0Init),
        GIM_CheckMemoryAddressSpace, /*MI*/0, /*MMO*/0, /*NumAddrSpace*/1, /*AddrSpace*/3,
        GIM_CheckHasNoUse, /*MI*/0,
        GIM_CheckPointerToAny, /*MI*/0, /*Op*/1, /*SizeInBits*/0,
        GIM_CheckComplexPattern, /*MI*/0, /*Op*/1, /*Renderer*/GIMT_Encode2(0), GIMT_Encode2(GICP_gi_ds_1addr_1offset),
        // (atomic_load_umin:{ *:[i32] } (DS1Addr1Offset:{ *:[iPTR] } i32:{ *:[i32] }:$ptr, i32:{ *:[i32] }:$offset), i32:{ *:[i32] }:$value)<<P:Predicate_atomic_load_umin_local_noret_32>>  =>  (DS_MIN_U32_gfx9 ?:{ *:[i32] }:$ptr, anonymous_15037:{ *:[i32] }:$value, offset:{ *:[i32] }:$offset, 0:{ *:[i1] })
        GIR_BuildMI, /*InsnID*/0, /*Opcode*/GIMT_Encode2(AMDGPU::DS_MIN_U32_gfx9),
        GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/0, // ptr
        GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/2, // value
        GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/1, // offset
        GIR_AddImm8, /*InsnID*/0, /*Imm*/0,
        GIR_MergeMemOperands, /*InsnID*/0, /*NumInsns*/1, /*MergeInsnID's*/0,
        GIR_ConstrainSelectedInstOperands, /*InsnID*/0,
        GIR_EraseFromParent, /*InsnID*/0,
        // GIR_Coverage, 6961,
        GIR_Done,
      // Label 2865: @185013
      GIM_Try, /*On fail goto*//*Label 2866*/ GIMT_Encode4(185069), // Rule ID 6963 //
        GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasGDS),
        GIM_CheckMemoryAddressSpace, /*MI*/0, /*MMO*/0, /*NumAddrSpace*/1, /*AddrSpace*/2,
        GIM_CheckHasNoUse, /*MI*/0,
        GIM_CheckPointerToAny, /*MI*/0, /*Op*/1, /*SizeInBits*/0,
        GIM_CheckComplexPattern, /*MI*/0, /*Op*/1, /*Renderer*/GIMT_Encode2(0), GIMT_Encode2(GICP_gi_ds_1addr_1offset),
        // (atomic_load_umin_glue:{ *:[i32] } (DS1Addr1Offset:{ *:[iPTR] } i32:{ *:[i32] }:$ptr, i32:{ *:[i32] }:$offset), i32:{ *:[i32] }:$value)<<P:Predicate_atomic_load_umin_region_m0_noret_32>>  =>  (DS_MIN_U32 ?:{ *:[i32] }:$ptr, anonymous_15037:{ *:[i32] }:$value, offset:{ *:[i32] }:$offset, 1:{ *:[i1] })
        GIR_BuildMI, /*InsnID*/0, /*Opcode*/GIMT_Encode2(AMDGPU::DS_MIN_U32),
        GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/0, // ptr
        GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/2, // value
        GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/1, // offset
        GIR_AddImm8, /*InsnID*/0, /*Imm*/1,
        GIR_MergeMemOperands, /*InsnID*/0, /*NumInsns*/1, /*MergeInsnID's*/0,
        GIR_ConstrainSelectedInstOperands, /*InsnID*/0,
        GIR_EraseFromParent, /*InsnID*/0,
        // GIR_Coverage, 6963,
        GIR_Done,
      // Label 2866: @185069
      GIM_Try, /*On fail goto*//*Label 2867*/ GIMT_Encode4(185132), // Rule ID 6958 //
        GIM_CheckFeatures, GIMT_Encode2(GIFBS_LDSRequiresM0Init),
        GIM_CheckMemoryAddressSpace, /*MI*/0, /*MMO*/0, /*NumAddrSpace*/1, /*AddrSpace*/3,
        GIM_CheckRegBankForClass, /*MI*/0, /*Op*/0, /*RC*/GIMT_Encode2(AMDGPU::AV_32RegClassID),
        GIM_CheckPointerToAny, /*MI*/0, /*Op*/1, /*SizeInBits*/0,
        GIM_CheckComplexPattern, /*MI*/0, /*Op*/1, /*Renderer*/GIMT_Encode2(0), GIMT_Encode2(GICP_gi_ds_1addr_1offset),
        // (atomic_load_umin_glue:{ *:[i32] } (DS1Addr1Offset:{ *:[iPTR] } i32:{ *:[i32] }:$ptr, i32:{ *:[i32] }:$offset), i32:{ *:[i32] }:$value)<<P:Predicate_atomic_load_umin_local_m0_32>>  =>  (DS_MIN_RTN_U32:{ *:[i32] } ?:{ *:[i32] }:$ptr, anonymous_15037:{ *:[i32] }:$value, offset:{ *:[i32] }:$offset, 0:{ *:[i1] })
        GIR_BuildMI, /*InsnID*/0, /*Opcode*/GIMT_Encode2(AMDGPU::DS_MIN_RTN_U32),
        GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/0, // DstI[vdst]
        GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/0, // ptr
        GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/2, // value
        GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/1, // offset
        GIR_AddImm8, /*InsnID*/0, /*Imm*/0,
        GIR_MergeMemOperands, /*InsnID*/0, /*NumInsns*/1, /*MergeInsnID's*/0,
        GIR_ConstrainSelectedInstOperands, /*InsnID*/0,
        GIR_EraseFromParent, /*InsnID*/0,
        // GIR_Coverage, 6958,
        GIR_Done,
      // Label 2867: @185132
      GIM_Try, /*On fail goto*//*Label 2868*/ GIMT_Encode4(185195), // Rule ID 6960 //
        GIM_CheckFeatures, GIMT_Encode2(GIFBS_NotLDSRequiresM0Init),
        GIM_CheckMemoryAddressSpace, /*MI*/0, /*MMO*/0, /*NumAddrSpace*/1, /*AddrSpace*/3,
        GIM_CheckRegBankForClass, /*MI*/0, /*Op*/0, /*RC*/GIMT_Encode2(AMDGPU::AV_32RegClassID),
        GIM_CheckPointerToAny, /*MI*/0, /*Op*/1, /*SizeInBits*/0,
        GIM_CheckComplexPattern, /*MI*/0, /*Op*/1, /*Renderer*/GIMT_Encode2(0), GIMT_Encode2(GICP_gi_ds_1addr_1offset),
        // (atomic_load_umin:{ *:[i32] } (DS1Addr1Offset:{ *:[iPTR] } i32:{ *:[i32] }:$ptr, i32:{ *:[i32] }:$offset), i32:{ *:[i32] }:$value)<<P:Predicate_atomic_load_umin_local_32>>  =>  (DS_MIN_RTN_U32_gfx9:{ *:[i32] } ?:{ *:[i32] }:$ptr, anonymous_15037:{ *:[i32] }:$value, offset:{ *:[i32] }:$offset, 0:{ *:[i1] })
        GIR_BuildMI, /*InsnID*/0, /*Opcode*/GIMT_Encode2(AMDGPU::DS_MIN_RTN_U32_gfx9),
        GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/0, // DstI[vdst]
        GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/0, // ptr
        GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/2, // value
        GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/1, // offset
        GIR_AddImm8, /*InsnID*/0, /*Imm*/0,
        GIR_MergeMemOperands, /*InsnID*/0, /*NumInsns*/1, /*MergeInsnID's*/0,
        GIR_ConstrainSelectedInstOperands, /*InsnID*/0,
        GIR_EraseFromParent, /*InsnID*/0,
        // GIR_Coverage, 6960,
        GIR_Done,
      // Label 2868: @185195
      GIM_Try, /*On fail goto*//*Label 2869*/ GIMT_Encode4(185258), // Rule ID 6962 //
        GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasGDS),
        GIM_CheckMemoryAddressSpace, /*MI*/0, /*MMO*/0, /*NumAddrSpace*/1, /*AddrSpace*/2,
        GIM_CheckRegBankForClass, /*MI*/0, /*Op*/0, /*RC*/GIMT_Encode2(AMDGPU::AV_32RegClassID),
        GIM_CheckPointerToAny, /*MI*/0, /*Op*/1, /*SizeInBits*/0,
        GIM_CheckComplexPattern, /*MI*/0, /*Op*/1, /*Renderer*/GIMT_Encode2(0), GIMT_Encode2(GICP_gi_ds_1addr_1offset),
        // (atomic_load_umin_glue:{ *:[i32] } (DS1Addr1Offset:{ *:[iPTR] } i32:{ *:[i32] }:$ptr, i32:{ *:[i32] }:$offset), i32:{ *:[i32] }:$value)<<P:Predicate_atomic_load_umin_region_m0_32>>  =>  (DS_MIN_RTN_U32:{ *:[i32] } ?:{ *:[i32] }:$ptr, anonymous_15037:{ *:[i32] }:$value, offset:{ *:[i32] }:$offset, 1:{ *:[i1] })
        GIR_BuildMI, /*InsnID*/0, /*Opcode*/GIMT_Encode2(AMDGPU::DS_MIN_RTN_U32),
        GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/0, // DstI[vdst]
        GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/0, // ptr
        GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/2, // value
        GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/1, // offset
        GIR_AddImm8, /*InsnID*/0, /*Imm*/1,
        GIR_MergeMemOperands, /*InsnID*/0, /*NumInsns*/1, /*MergeInsnID's*/0,
        GIR_ConstrainSelectedInstOperands, /*InsnID*/0,
        GIR_EraseFromParent, /*InsnID*/0,
        // GIR_Coverage, 6962,
        GIR_Done,
      // Label 2869: @185258
      GIM_Try, /*On fail goto*//*Label 2870*/ GIMT_Encode4(185321), // Rule ID 3179 //
        GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasFlatGlobalInsts),
        GIM_CheckMemoryAddressSpace, /*MI*/0, /*MMO*/0, /*NumAddrSpace*/3, /*AddrSpace*/1, /*AddrSpace*/4, /*AddrSpace*/6,
        GIM_CheckHasNoUse, /*MI*/0,
        GIM_CheckPointerToAny, /*MI*/0, /*Op*/1, /*SizeInBits*/0,
        GIM_CheckComplexPattern, /*MI*/0, /*Op*/1, /*Renderer*/GIMT_Encode2(0), GIMT_Encode2(GICP_gi_global_saddr),
        // (atomic_load_umin:{ *:[i32] } (GlobalSAddr:{ *:[iPTR] } SReg_64:{ *:[i64] }:$saddr, VGPR_32:{ *:[i32] }:$voffset, i32:{ *:[i32] }:$offset), i32:{ *:[i32] }:$data)<<P:Predicate_atomic_load_umin_global_noret_32>>  =>  (GLOBAL_ATOMIC_UMIN_SADDR ?:{ *:[i32] }:$voffset, anonymous_15037:{ *:[i32] }:$data, ?:{ *:[i64] }:$saddr, ?:{ *:[i32] }:$offset)
        GIR_BuildMI, /*InsnID*/0, /*Opcode*/GIMT_Encode2(AMDGPU::GLOBAL_ATOMIC_UMIN_SADDR),
        GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/1, // voffset
        GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/2, // data
        GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/0, // saddr
        GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/2, // offset
        GIR_AddImm8, /*InsnID*/0, /*Imm*/0,
        GIR_MergeMemOperands, /*InsnID*/0, /*NumInsns*/1, /*MergeInsnID's*/0,
        GIR_ConstrainSelectedInstOperands, /*InsnID*/0,
        GIR_EraseFromParent, /*InsnID*/0,
        // GIR_Coverage, 3179,
        GIR_Done,
      // Label 2870: @185321
      GIM_Try, /*On fail goto*//*Label 2871*/ GIMT_Encode4(185391), // Rule ID 3181 //
        GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasFlatGlobalInsts),
        GIM_CheckMemoryAddressSpace, /*MI*/0, /*MMO*/0, /*NumAddrSpace*/3, /*AddrSpace*/1, /*AddrSpace*/4, /*AddrSpace*/6,
        GIM_CheckRegBankForClass, /*MI*/0, /*Op*/0, /*RC*/GIMT_Encode2(AMDGPU::AV_32RegClassID),
        GIM_CheckPointerToAny, /*MI*/0, /*Op*/1, /*SizeInBits*/0,
        GIM_CheckComplexPattern, /*MI*/0, /*Op*/1, /*Renderer*/GIMT_Encode2(0), GIMT_Encode2(GICP_gi_global_saddr),
        // (atomic_load_umin:{ *:[i32] } (GlobalSAddr:{ *:[iPTR] } SReg_64:{ *:[i64] }:$saddr, VGPR_32:{ *:[i32] }:$voffset, i32:{ *:[i32] }:$offset), i32:{ *:[i32] }:$data)<<P:Predicate_atomic_load_umin_global_32>>  =>  (GLOBAL_ATOMIC_UMIN_SADDR_RTN:{ *:[i32] } ?:{ *:[i32] }:$voffset, anonymous_15037:{ *:[i32] }:$data, ?:{ *:[i64] }:$saddr, ?:{ *:[i32] }:$offset)
        GIR_BuildMI, /*InsnID*/0, /*Opcode*/GIMT_Encode2(AMDGPU::GLOBAL_ATOMIC_UMIN_SADDR_RTN),
        GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/0, // DstI[vdst]
        GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/1, // voffset
        GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/2, // data
        GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/0, // saddr
        GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/2, // offset
        GIR_AddImm8, /*InsnID*/0, /*Imm*/1,
        GIR_MergeMemOperands, /*InsnID*/0, /*NumInsns*/1, /*MergeInsnID's*/0,
        GIR_ConstrainSelectedInstOperands, /*InsnID*/0,
        GIR_EraseFromParent, /*InsnID*/0,
        // GIR_Coverage, 3181,
        GIR_Done,
      // Label 2871: @185391
      GIM_Try, /*On fail goto*//*Label 2872*/ GIMT_Encode4(185449), // Rule ID 3178 //
        GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasFlatGlobalInsts),
        GIM_CheckMemoryAddressSpace, /*MI*/0, /*MMO*/0, /*NumAddrSpace*/3, /*AddrSpace*/1, /*AddrSpace*/4, /*AddrSpace*/6,
        GIM_CheckHasNoUse, /*MI*/0,
        GIM_CheckPointerToAny, /*MI*/0, /*Op*/1, /*SizeInBits*/0,
        GIM_CheckComplexPattern, /*MI*/0, /*Op*/1, /*Renderer*/GIMT_Encode2(0), GIMT_Encode2(GICP_gi_global_offset),
        // (atomic_load_umin:{ *:[i32] } (GlobalOffset:{ *:[iPTR] } i64:{ *:[i64] }:$vaddr, i32:{ *:[i32] }:$offset), i32:{ *:[i32] }:$data)<<P:Predicate_atomic_load_umin_global_noret_32>>  =>  (GLOBAL_ATOMIC_UMIN VReg_64:{ *:[i64] }:$vaddr, anonymous_15037:{ *:[i32] }:$data, ?:{ *:[i32] }:$offset)
        GIR_BuildMI, /*InsnID*/0, /*Opcode*/GIMT_Encode2(AMDGPU::GLOBAL_ATOMIC_UMIN),
        GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/0, // vaddr
        GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/2, // data
        GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/1, // offset
        GIR_AddImm8, /*InsnID*/0, /*Imm*/0,
        GIR_MergeMemOperands, /*InsnID*/0, /*NumInsns*/1, /*MergeInsnID's*/0,
        GIR_ConstrainSelectedInstOperands, /*InsnID*/0,
        GIR_EraseFromParent, /*InsnID*/0,
        // GIR_Coverage, 3178,
        GIR_Done,
      // Label 2872: @185449
      GIM_Try, /*On fail goto*//*Label 2873*/ GIMT_Encode4(185514), // Rule ID 3180 //
        GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasFlatGlobalInsts),
        GIM_CheckMemoryAddressSpace, /*MI*/0, /*MMO*/0, /*NumAddrSpace*/3, /*AddrSpace*/1, /*AddrSpace*/4, /*AddrSpace*/6,
        GIM_CheckRegBankForClass, /*MI*/0, /*Op*/0, /*RC*/GIMT_Encode2(AMDGPU::AV_32RegClassID),
        GIM_CheckPointerToAny, /*MI*/0, /*Op*/1, /*SizeInBits*/0,
        GIM_CheckComplexPattern, /*MI*/0, /*Op*/1, /*Renderer*/GIMT_Encode2(0), GIMT_Encode2(GICP_gi_global_offset),
        // (atomic_load_umin:{ *:[i32] } (GlobalOffset:{ *:[iPTR] } i64:{ *:[i64] }:$vaddr, i32:{ *:[i32] }:$offset), i32:{ *:[i32] }:$data)<<P:Predicate_atomic_load_umin_global_32>>  =>  (GLOBAL_ATOMIC_UMIN_RTN:{ *:[i32] } VReg_64:{ *:[i64] }:$vaddr, anonymous_15037:{ *:[i32] }:$data, ?:{ *:[i32] }:$offset)
        GIR_BuildMI, /*InsnID*/0, /*Opcode*/GIMT_Encode2(AMDGPU::GLOBAL_ATOMIC_UMIN_RTN),
        GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/0, // DstI[vdst]
        GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/0, // vaddr
        GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/2, // data
        GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/1, // offset
        GIR_AddImm8, /*InsnID*/0, /*Imm*/1,
        GIR_MergeMemOperands, /*InsnID*/0, /*NumInsns*/1, /*MergeInsnID's*/0,
        GIR_ConstrainSelectedInstOperands, /*InsnID*/0,
        GIR_EraseFromParent, /*InsnID*/0,
        // GIR_Coverage, 3180,
        GIR_Done,
      // Label 2873: @185514
      GIM_Try, /*On fail goto*//*Label 2874*/ GIMT_Encode4(185573), // Rule ID 2844 //
        GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasFlatAddressSpace),
        GIM_CheckMemoryAddressSpace, /*MI*/0, /*MMO*/0, /*NumAddrSpace*/4, /*AddrSpace*/0, /*AddrSpace*/1, /*AddrSpace*/4, /*AddrSpace*/6,
        GIM_CheckHasNoUse, /*MI*/0,
        GIM_CheckPointerToAny, /*MI*/0, /*Op*/1, /*SizeInBits*/0,
        GIM_CheckComplexPattern, /*MI*/0, /*Op*/1, /*Renderer*/GIMT_Encode2(0), GIMT_Encode2(GICP_gi_flat_offset),
        // (atomic_load_umin:{ *:[i32] } (FlatOffset:{ *:[iPTR] } i64:{ *:[i64] }:$vaddr, i32:{ *:[i32] }:$offset), i32:{ *:[i32] }:$data)<<P:Predicate_atomic_load_umin_flat_noret_32>>  =>  (FLAT_ATOMIC_UMIN VReg_64:{ *:[i64] }:$vaddr, anonymous_15037:{ *:[i32] }:$data, ?:{ *:[i32] }:$offset)
        GIR_BuildMI, /*InsnID*/0, /*Opcode*/GIMT_Encode2(AMDGPU::FLAT_ATOMIC_UMIN),
        GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/0, // vaddr
        GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/2, // data
        GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/1, // offset
        GIR_AddImm8, /*InsnID*/0, /*Imm*/0,
        GIR_MergeMemOperands, /*InsnID*/0, /*NumInsns*/1, /*MergeInsnID's*/0,
        GIR_ConstrainSelectedInstOperands, /*InsnID*/0,
        GIR_EraseFromParent, /*InsnID*/0,
        // GIR_Coverage, 2844,
        GIR_Done,
      // Label 2874: @185573
      GIM_Try, /*On fail goto*//*Label 2875*/ GIMT_Encode4(185631), // Rule ID 2896 //
        GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasFlatAddressSpace),
        GIM_CheckMemoryAddressSpace, /*MI*/0, /*MMO*/0, /*NumAddrSpace*/3, /*AddrSpace*/1, /*AddrSpace*/4, /*AddrSpace*/6,
        GIM_CheckHasNoUse, /*MI*/0,
        GIM_CheckPointerToAny, /*MI*/0, /*Op*/1, /*SizeInBits*/0,
        GIM_CheckComplexPattern, /*MI*/0, /*Op*/1, /*Renderer*/GIMT_Encode2(0), GIMT_Encode2(GICP_gi_flat_offset),
        // (atomic_load_umin:{ *:[i32] } (FlatOffset:{ *:[iPTR] } i64:{ *:[i64] }:$vaddr, i32:{ *:[i32] }:$offset), i32:{ *:[i32] }:$data)<<P:Predicate_atomic_load_umin_global_noret_32>>  =>  (FLAT_ATOMIC_UMIN VReg_64:{ *:[i64] }:$vaddr, anonymous_15037:{ *:[i32] }:$data, ?:{ *:[i32] }:$offset)
        GIR_BuildMI, /*InsnID*/0, /*Opcode*/GIMT_Encode2(AMDGPU::FLAT_ATOMIC_UMIN),
        GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/0, // vaddr
        GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/2, // data
        GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/1, // offset
        GIR_AddImm8, /*InsnID*/0, /*Imm*/0,
        GIR_MergeMemOperands, /*InsnID*/0, /*NumInsns*/1, /*MergeInsnID's*/0,
        GIR_ConstrainSelectedInstOperands, /*InsnID*/0,
        GIR_EraseFromParent, /*InsnID*/0,
        // GIR_Coverage, 2896,
        GIR_Done,
      // Label 2875: @185631
      GIM_Try, /*On fail goto*//*Label 2876*/ GIMT_Encode4(185697), // Rule ID 2843 //
        GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasFlatAddressSpace),
        GIM_CheckMemoryAddressSpace, /*MI*/0, /*MMO*/0, /*NumAddrSpace*/4, /*AddrSpace*/0, /*AddrSpace*/1, /*AddrSpace*/4, /*AddrSpace*/6,
        GIM_CheckRegBankForClass, /*MI*/0, /*Op*/0, /*RC*/GIMT_Encode2(AMDGPU::AV_32RegClassID),
        GIM_CheckPointerToAny, /*MI*/0, /*Op*/1, /*SizeInBits*/0,
        GIM_CheckComplexPattern, /*MI*/0, /*Op*/1, /*Renderer*/GIMT_Encode2(0), GIMT_Encode2(GICP_gi_flat_offset),
        // (atomic_load_umin:{ *:[i32] } (FlatOffset:{ *:[iPTR] } i64:{ *:[i64] }:$vaddr, i32:{ *:[i32] }:$offset), i32:{ *:[i32] }:$data)<<P:Predicate_atomic_load_umin_flat_32>>  =>  (FLAT_ATOMIC_UMIN_RTN:{ *:[i32] } VReg_64:{ *:[i64] }:$vaddr, anonymous_15037:{ *:[i32] }:$data, ?:{ *:[i32] }:$offset)
        GIR_BuildMI, /*InsnID*/0, /*Opcode*/GIMT_Encode2(AMDGPU::FLAT_ATOMIC_UMIN_RTN),
        GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/0, // DstI[vdst]
        GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/0, // vaddr
        GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/2, // data
        GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/1, // offset
        GIR_AddImm8, /*InsnID*/0, /*Imm*/1,
        GIR_MergeMemOperands, /*InsnID*/0, /*NumInsns*/1, /*MergeInsnID's*/0,
        GIR_ConstrainSelectedInstOperands, /*InsnID*/0,
        GIR_EraseFromParent, /*InsnID*/0,
        // GIR_Coverage, 2843,
        GIR_Done,
      // Label 2876: @185697
      GIM_Try, /*On fail goto*//*Label 2877*/ GIMT_Encode4(185762), // Rule ID 2895 //
        GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasFlatAddressSpace),
        GIM_CheckMemoryAddressSpace, /*MI*/0, /*MMO*/0, /*NumAddrSpace*/3, /*AddrSpace*/1, /*AddrSpace*/4, /*AddrSpace*/6,
        GIM_CheckRegBankForClass, /*MI*/0, /*Op*/0, /*RC*/GIMT_Encode2(AMDGPU::AV_32RegClassID),
        GIM_CheckPointerToAny, /*MI*/0, /*Op*/1, /*SizeInBits*/0,
        GIM_CheckComplexPattern, /*MI*/0, /*Op*/1, /*Renderer*/GIMT_Encode2(0), GIMT_Encode2(GICP_gi_flat_offset),
        // (atomic_load_umin:{ *:[i32] } (FlatOffset:{ *:[iPTR] } i64:{ *:[i64] }:$vaddr, i32:{ *:[i32] }:$offset), i32:{ *:[i32] }:$data)<<P:Predicate_atomic_load_umin_global_32>>  =>  (FLAT_ATOMIC_UMIN_RTN:{ *:[i32] } VReg_64:{ *:[i64] }:$vaddr, anonymous_15037:{ *:[i32] }:$data, ?:{ *:[i32] }:$offset)
        GIR_BuildMI, /*InsnID*/0, /*Opcode*/GIMT_Encode2(AMDGPU::FLAT_ATOMIC_UMIN_RTN),
        GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/0, // DstI[vdst]
        GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/0, // vaddr
        GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/2, // data
        GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/1, // offset
        GIR_AddImm8, /*InsnID*/0, /*Imm*/1,
        GIR_MergeMemOperands, /*InsnID*/0, /*NumInsns*/1, /*MergeInsnID's*/0,
        GIR_ConstrainSelectedInstOperands, /*InsnID*/0,
        GIR_EraseFromParent, /*InsnID*/0,
        // GIR_Coverage, 2895,
        GIR_Done,
      // Label 2877: @185762
      GIM_Reject,
    // Label 2855: @185763
    GIM_Reject,
    // Label 2853: @185764
    GIM_Try, /*On fail goto*//*Label 2878*/ GIMT_Encode4(187175),
      GIM_CheckType, /*MI*/0, /*Op*/2, /*Type*/GILLT_s64,
      GIM_Try, /*On fail goto*//*Label 2879*/ GIMT_Encode4(185841), // Rule ID 4638 //
        GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasUnrestrictedSOffset),
        GIM_CheckMemoryAddressSpace, /*MI*/0, /*MMO*/0, /*NumAddrSpace*/3, /*AddrSpace*/1, /*AddrSpace*/4, /*AddrSpace*/6,
        GIM_CheckHasNoUse, /*MI*/0,
        GIM_CheckPointerToAny, /*MI*/0, /*Op*/1, /*SizeInBits*/0,
        GIM_CheckComplexPattern, /*MI*/0, /*Op*/1, /*Renderer*/GIMT_Encode2(0), GIMT_Encode2(GICP_gi_mubuf_addr64),
        // (atomic_load_umin:{ *:[i64] } (MUBUFAddr64:{ *:[iPTR] } v4i32:{ *:[v4i32] }:$srsrc, i64:{ *:[i64] }:$vaddr, i32:{ *:[i32] }:$soffset, i32:{ *:[i32] }:$offset), i64:{ *:[i64] }:$vdata_in)<<P:Predicate_atomic_load_umin_global_noret_64>>  =>  (BUFFER_ATOMIC_UMIN_X2_ADDR64 anonymous_15036:{ *:[i64] }:$vdata_in, VReg_64:{ *:[i64] }:$vaddr, SReg_128:{ *:[v4i32] }:$srsrc, SCSrc_b32:{ *:[i32] }:$soffset, offset:{ *:[i32] }:$offset)
        GIR_BuildMI, /*InsnID*/0, /*Opcode*/GIMT_Encode2(AMDGPU::BUFFER_ATOMIC_UMIN_X2_ADDR64),
        GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/2, // vdata_in
        GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/1, // vaddr
        GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/0, // srsrc
        GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/2, // soffset
        GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/3, // offset
        GIR_AddImm8, /*InsnID*/0, /*Imm*/0,
        GIR_MergeMemOperands, /*InsnID*/0, /*NumInsns*/1, /*MergeInsnID's*/0,
        GIR_ConstrainSelectedInstOperands, /*InsnID*/0,
        GIR_EraseFromParent, /*InsnID*/0,
        // GIR_Coverage, 4638,
        GIR_Done,
      // Label 2879: @185841
      GIM_Try, /*On fail goto*//*Label 2880*/ GIMT_Encode4(185906), // Rule ID 4642 //
        GIM_CheckMemoryAddressSpace, /*MI*/0, /*MMO*/0, /*NumAddrSpace*/3, /*AddrSpace*/1, /*AddrSpace*/4, /*AddrSpace*/6,
        GIM_CheckHasNoUse, /*MI*/0,
        GIM_CheckPointerToAny, /*MI*/0, /*Op*/1, /*SizeInBits*/0,
        GIM_CheckComplexPattern, /*MI*/0, /*Op*/1, /*Renderer*/GIMT_Encode2(0), GIMT_Encode2(GICP_gi_mubuf_addr64),
        // (atomic_load_umin:{ *:[i64] } (MUBUFAddr64:{ *:[iPTR] } v4i32:{ *:[v4i32] }:$srsrc, i64:{ *:[i64] }:$vaddr, i32:{ *:[i32] }:$soffset, i32:{ *:[i32] }:$offset), i64:{ *:[i64] }:$vdata_in)<<P:Predicate_atomic_load_umin_global_noret_64>>  =>  (BUFFER_ATOMIC_UMIN_X2_VBUFFER_ADDR64 anonymous_15036:{ *:[i64] }:$vdata_in, VReg_64:{ *:[i64] }:$vaddr, SReg_128:{ *:[v4i32] }:$srsrc, SCSrc_b32:{ *:[i32] }:$soffset, offset:{ *:[i32] }:$offset)
        GIR_BuildMI, /*InsnID*/0, /*Opcode*/GIMT_Encode2(AMDGPU::BUFFER_ATOMIC_UMIN_X2_VBUFFER_ADDR64),
        GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/2, // vdata_in
        GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/1, // vaddr
        GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/0, // srsrc
        GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/2, // soffset
        GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/3, // offset
        GIR_AddImm8, /*InsnID*/0, /*Imm*/0,
        GIR_MergeMemOperands, /*InsnID*/0, /*NumInsns*/1, /*MergeInsnID's*/0,
        GIR_ConstrainSelectedInstOperands, /*InsnID*/0,
        GIR_EraseFromParent, /*InsnID*/0,
        // GIR_Coverage, 4642,
        GIR_Done,
      // Label 2880: @185906
      GIM_Try, /*On fail goto*//*Label 2881*/ GIMT_Encode4(185981), // Rule ID 4636 //
        GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasUnrestrictedSOffset),
        GIM_CheckMemoryAddressSpace, /*MI*/0, /*MMO*/0, /*NumAddrSpace*/3, /*AddrSpace*/1, /*AddrSpace*/4, /*AddrSpace*/6,
        GIM_CheckRegBankForClass, /*MI*/0, /*Op*/0, /*RC*/GIMT_Encode2(AMDGPU::AV_64RegClassID),
        GIM_CheckPointerToAny, /*MI*/0, /*Op*/1, /*SizeInBits*/0,
        GIM_CheckComplexPattern, /*MI*/0, /*Op*/1, /*Renderer*/GIMT_Encode2(0), GIMT_Encode2(GICP_gi_mubuf_addr64),
        // (atomic_load_umin:{ *:[i64] } (MUBUFAddr64:{ *:[iPTR] } v4i32:{ *:[v4i32] }:$srsrc, i64:{ *:[i64] }:$vaddr, i32:{ *:[i32] }:$soffset, i32:{ *:[i32] }:$offset), i64:{ *:[i64] }:$vdata_in)<<P:Predicate_atomic_load_umin_global_64>>  =>  (BUFFER_ATOMIC_UMIN_X2_ADDR64_RTN:{ *:[i64] } anonymous_15036:{ *:[i64] }:$vdata_in, VReg_64:{ *:[i64] }:$vaddr, SReg_128:{ *:[v4i32] }:$srsrc, SCSrc_b32:{ *:[i32] }:$soffset, offset:{ *:[i32] }:$offset)
        GIR_BuildMI, /*InsnID*/0, /*Opcode*/GIMT_Encode2(AMDGPU::BUFFER_ATOMIC_UMIN_X2_ADDR64_RTN),
        GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/0, // DstI[vdata]
        GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/2, // vdata_in
        GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/1, // vaddr
        GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/0, // srsrc
        GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/2, // soffset
        GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/3, // offset
        GIR_AddImm8, /*InsnID*/0, /*Imm*/1,
        GIR_MergeMemOperands, /*InsnID*/0, /*NumInsns*/1, /*MergeInsnID's*/0,
        GIR_ConstrainSelectedInstOperands, /*InsnID*/0,
        GIR_EraseFromParent, /*InsnID*/0,
        // GIR_Coverage, 4636,
        GIR_Done,
      // Label 2881: @185981
      GIM_Try, /*On fail goto*//*Label 2882*/ GIMT_Encode4(186053), // Rule ID 4640 //
        GIM_CheckMemoryAddressSpace, /*MI*/0, /*MMO*/0, /*NumAddrSpace*/3, /*AddrSpace*/1, /*AddrSpace*/4, /*AddrSpace*/6,
        GIM_CheckRegBankForClass, /*MI*/0, /*Op*/0, /*RC*/GIMT_Encode2(AMDGPU::AV_64RegClassID),
        GIM_CheckPointerToAny, /*MI*/0, /*Op*/1, /*SizeInBits*/0,
        GIM_CheckComplexPattern, /*MI*/0, /*Op*/1, /*Renderer*/GIMT_Encode2(0), GIMT_Encode2(GICP_gi_mubuf_addr64),
        // (atomic_load_umin:{ *:[i64] } (MUBUFAddr64:{ *:[iPTR] } v4i32:{ *:[v4i32] }:$srsrc, i64:{ *:[i64] }:$vaddr, i32:{ *:[i32] }:$soffset, i32:{ *:[i32] }:$offset), i64:{ *:[i64] }:$vdata_in)<<P:Predicate_atomic_load_umin_global_64>>  =>  (BUFFER_ATOMIC_UMIN_X2_VBUFFER_ADDR64_RTN:{ *:[i64] } anonymous_15036:{ *:[i64] }:$vdata_in, VReg_64:{ *:[i64] }:$vaddr, SReg_128:{ *:[v4i32] }:$srsrc, SCSrc_b32:{ *:[i32] }:$soffset, offset:{ *:[i32] }:$offset)
        GIR_BuildMI, /*InsnID*/0, /*Opcode*/GIMT_Encode2(AMDGPU::BUFFER_ATOMIC_UMIN_X2_VBUFFER_ADDR64_RTN),
        GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/0, // DstI[vdata]
        GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/2, // vdata_in
        GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/1, // vaddr
        GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/0, // srsrc
        GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/2, // soffset
        GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/3, // offset
        GIR_AddImm8, /*InsnID*/0, /*Imm*/1,
        GIR_MergeMemOperands, /*InsnID*/0, /*NumInsns*/1, /*MergeInsnID's*/0,
        GIR_ConstrainSelectedInstOperands, /*InsnID*/0,
        GIR_EraseFromParent, /*InsnID*/0,
        // GIR_Coverage, 4640,
        GIR_Done,
      // Label 2882: @186053
      GIM_Try, /*On fail goto*//*Label 2883*/ GIMT_Encode4(186116), // Rule ID 4637 //
        GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasUnrestrictedSOffset),
        GIM_CheckMemoryAddressSpace, /*MI*/0, /*MMO*/0, /*NumAddrSpace*/3, /*AddrSpace*/1, /*AddrSpace*/4, /*AddrSpace*/6,
        GIM_CheckHasNoUse, /*MI*/0,
        GIM_CheckPointerToAny, /*MI*/0, /*Op*/1, /*SizeInBits*/0,
        GIM_CheckComplexPattern, /*MI*/0, /*Op*/1, /*Renderer*/GIMT_Encode2(0), GIMT_Encode2(GICP_gi_mubuf_offset),
        // (atomic_load_umin:{ *:[i64] } (MUBUFOffset:{ *:[iPTR] } v4i32:{ *:[v4i32] }:$srsrc, i32:{ *:[i32] }:$soffset, i32:{ *:[i32] }:$offset), i64:{ *:[i64] }:$vdata_in)<<P:Predicate_atomic_load_umin_global_noret_64>>  =>  (BUFFER_ATOMIC_UMIN_X2_OFFSET anonymous_15036:{ *:[i64] }:$vdata_in, SReg_128:{ *:[v4i32] }:$srsrc, SCSrc_b32:{ *:[i32] }:$soffset, offset:{ *:[i32] }:$offset)
        GIR_BuildMI, /*InsnID*/0, /*Opcode*/GIMT_Encode2(AMDGPU::BUFFER_ATOMIC_UMIN_X2_OFFSET),
        GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/2, // vdata_in
        GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/0, // srsrc
        GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/1, // soffset
        GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/2, // offset
        GIR_AddImm8, /*InsnID*/0, /*Imm*/0,
        GIR_MergeMemOperands, /*InsnID*/0, /*NumInsns*/1, /*MergeInsnID's*/0,
        GIR_ConstrainSelectedInstOperands, /*InsnID*/0,
        GIR_EraseFromParent, /*InsnID*/0,
        // GIR_Coverage, 4637,
        GIR_Done,
      // Label 2883: @186116
      GIM_Try, /*On fail goto*//*Label 2884*/ GIMT_Encode4(186176), // Rule ID 4641 //
        GIM_CheckMemoryAddressSpace, /*MI*/0, /*MMO*/0, /*NumAddrSpace*/3, /*AddrSpace*/1, /*AddrSpace*/4, /*AddrSpace*/6,
        GIM_CheckHasNoUse, /*MI*/0,
        GIM_CheckPointerToAny, /*MI*/0, /*Op*/1, /*SizeInBits*/0,
        GIM_CheckComplexPattern, /*MI*/0, /*Op*/1, /*Renderer*/GIMT_Encode2(0), GIMT_Encode2(GICP_gi_mubuf_offset),
        // (atomic_load_umin:{ *:[i64] } (MUBUFOffset:{ *:[iPTR] } v4i32:{ *:[v4i32] }:$srsrc, i32:{ *:[i32] }:$soffset, i32:{ *:[i32] }:$offset), i64:{ *:[i64] }:$vdata_in)<<P:Predicate_atomic_load_umin_global_noret_64>>  =>  (BUFFER_ATOMIC_UMIN_X2_VBUFFER_OFFSET anonymous_15036:{ *:[i64] }:$vdata_in, SReg_128:{ *:[v4i32] }:$srsrc, SCSrc_b32:{ *:[i32] }:$soffset, offset:{ *:[i32] }:$offset)
        GIR_BuildMI, /*InsnID*/0, /*Opcode*/GIMT_Encode2(AMDGPU::BUFFER_ATOMIC_UMIN_X2_VBUFFER_OFFSET),
        GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/2, // vdata_in
        GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/0, // srsrc
        GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/1, // soffset
        GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/2, // offset
        GIR_AddImm8, /*InsnID*/0, /*Imm*/0,
        GIR_MergeMemOperands, /*InsnID*/0, /*NumInsns*/1, /*MergeInsnID's*/0,
        GIR_ConstrainSelectedInstOperands, /*InsnID*/0,
        GIR_EraseFromParent, /*InsnID*/0,
        // GIR_Coverage, 4641,
        GIR_Done,
      // Label 2884: @186176
      GIM_Try, /*On fail goto*//*Label 2885*/ GIMT_Encode4(186246), // Rule ID 4635 //
        GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasUnrestrictedSOffset),
        GIM_CheckMemoryAddressSpace, /*MI*/0, /*MMO*/0, /*NumAddrSpace*/3, /*AddrSpace*/1, /*AddrSpace*/4, /*AddrSpace*/6,
        GIM_CheckRegBankForClass, /*MI*/0, /*Op*/0, /*RC*/GIMT_Encode2(AMDGPU::AV_64RegClassID),
        GIM_CheckPointerToAny, /*MI*/0, /*Op*/1, /*SizeInBits*/0,
        GIM_CheckComplexPattern, /*MI*/0, /*Op*/1, /*Renderer*/GIMT_Encode2(0), GIMT_Encode2(GICP_gi_mubuf_offset),
        // (atomic_load_umin:{ *:[i64] } (MUBUFOffset:{ *:[iPTR] } v4i32:{ *:[v4i32] }:$srsrc, i32:{ *:[i32] }:$soffset, i32:{ *:[i32] }:$offset), i64:{ *:[i64] }:$vdata_in)<<P:Predicate_atomic_load_umin_global_64>>  =>  (BUFFER_ATOMIC_UMIN_X2_OFFSET_RTN:{ *:[i64] } anonymous_15036:{ *:[i64] }:$vdata_in, SReg_128:{ *:[v4i32] }:$srsrc, SCSrc_b32:{ *:[i32] }:$soffset, offset:{ *:[i32] }:$offset)
        GIR_BuildMI, /*InsnID*/0, /*Opcode*/GIMT_Encode2(AMDGPU::BUFFER_ATOMIC_UMIN_X2_OFFSET_RTN),
        GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/0, // DstI[vdata]
        GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/2, // vdata_in
        GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/0, // srsrc
        GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/1, // soffset
        GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/2, // offset
        GIR_AddImm8, /*InsnID*/0, /*Imm*/1,
        GIR_MergeMemOperands, /*InsnID*/0, /*NumInsns*/1, /*MergeInsnID's*/0,
        GIR_ConstrainSelectedInstOperands, /*InsnID*/0,
        GIR_EraseFromParent, /*InsnID*/0,
        // GIR_Coverage, 4635,
        GIR_Done,
      // Label 2885: @186246
      GIM_Try, /*On fail goto*//*Label 2886*/ GIMT_Encode4(186313), // Rule ID 4639 //
        GIM_CheckMemoryAddressSpace, /*MI*/0, /*MMO*/0, /*NumAddrSpace*/3, /*AddrSpace*/1, /*AddrSpace*/4, /*AddrSpace*/6,
        GIM_CheckRegBankForClass, /*MI*/0, /*Op*/0, /*RC*/GIMT_Encode2(AMDGPU::AV_64RegClassID),
        GIM_CheckPointerToAny, /*MI*/0, /*Op*/1, /*SizeInBits*/0,
        GIM_CheckComplexPattern, /*MI*/0, /*Op*/1, /*Renderer*/GIMT_Encode2(0), GIMT_Encode2(GICP_gi_mubuf_offset),
        // (atomic_load_umin:{ *:[i64] } (MUBUFOffset:{ *:[iPTR] } v4i32:{ *:[v4i32] }:$srsrc, i32:{ *:[i32] }:$soffset, i32:{ *:[i32] }:$offset), i64:{ *:[i64] }:$vdata_in)<<P:Predicate_atomic_load_umin_global_64>>  =>  (BUFFER_ATOMIC_UMIN_X2_VBUFFER_OFFSET_RTN:{ *:[i64] } anonymous_15036:{ *:[i64] }:$vdata_in, SReg_128:{ *:[v4i32] }:$srsrc, SCSrc_b32:{ *:[i32] }:$soffset, offset:{ *:[i32] }:$offset)
        GIR_BuildMI, /*InsnID*/0, /*Opcode*/GIMT_Encode2(AMDGPU::BUFFER_ATOMIC_UMIN_X2_VBUFFER_OFFSET_RTN),
        GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/0, // DstI[vdata]
        GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/2, // vdata_in
        GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/0, // srsrc
        GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/1, // soffset
        GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/2, // offset
        GIR_AddImm8, /*InsnID*/0, /*Imm*/1,
        GIR_MergeMemOperands, /*InsnID*/0, /*NumInsns*/1, /*MergeInsnID's*/0,
        GIR_ConstrainSelectedInstOperands, /*InsnID*/0,
        GIR_EraseFromParent, /*InsnID*/0,
        // GIR_Coverage, 4639,
        GIR_Done,
      // Label 2886: @186313
      GIM_Try, /*On fail goto*//*Label 2887*/ GIMT_Encode4(186369), // Rule ID 7046 //
        GIM_CheckFeatures, GIMT_Encode2(GIFBS_LDSRequiresM0Init),
        GIM_CheckMemoryAddressSpace, /*MI*/0, /*MMO*/0, /*NumAddrSpace*/1, /*AddrSpace*/3,
        GIM_CheckHasNoUse, /*MI*/0,
        GIM_CheckPointerToAny, /*MI*/0, /*Op*/1, /*SizeInBits*/0,
        GIM_CheckComplexPattern, /*MI*/0, /*Op*/1, /*Renderer*/GIMT_Encode2(0), GIMT_Encode2(GICP_gi_ds_1addr_1offset),
        // (atomic_load_umin_glue:{ *:[i64] } (DS1Addr1Offset:{ *:[iPTR] } i32:{ *:[i32] }:$ptr, i32:{ *:[i32] }:$offset), i64:{ *:[i64] }:$value)<<P:Predicate_atomic_load_umin_local_m0_noret_64>>  =>  (DS_MIN_U64 ?:{ *:[i32] }:$ptr, anonymous_15036:{ *:[i64] }:$value, offset:{ *:[i32] }:$offset, 0:{ *:[i1] })
        GIR_BuildMI, /*InsnID*/0, /*Opcode*/GIMT_Encode2(AMDGPU::DS_MIN_U64),
        GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/0, // ptr
        GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/2, // value
        GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/1, // offset
        GIR_AddImm8, /*InsnID*/0, /*Imm*/0,
        GIR_MergeMemOperands, /*InsnID*/0, /*NumInsns*/1, /*MergeInsnID's*/0,
        GIR_ConstrainSelectedInstOperands, /*InsnID*/0,
        GIR_EraseFromParent, /*InsnID*/0,
        // GIR_Coverage, 7046,
        GIR_Done,
      // Label 2887: @186369
      GIM_Try, /*On fail goto*//*Label 2888*/ GIMT_Encode4(186425), // Rule ID 7048 //
        GIM_CheckFeatures, GIMT_Encode2(GIFBS_NotLDSRequiresM0Init),
        GIM_CheckMemoryAddressSpace, /*MI*/0, /*MMO*/0, /*NumAddrSpace*/1, /*AddrSpace*/3,
        GIM_CheckHasNoUse, /*MI*/0,
        GIM_CheckPointerToAny, /*MI*/0, /*Op*/1, /*SizeInBits*/0,
        GIM_CheckComplexPattern, /*MI*/0, /*Op*/1, /*Renderer*/GIMT_Encode2(0), GIMT_Encode2(GICP_gi_ds_1addr_1offset),
        // (atomic_load_umin:{ *:[i64] } (DS1Addr1Offset:{ *:[iPTR] } i32:{ *:[i32] }:$ptr, i32:{ *:[i32] }:$offset), i64:{ *:[i64] }:$value)<<P:Predicate_atomic_load_umin_local_noret_64>>  =>  (DS_MIN_U64_gfx9 ?:{ *:[i32] }:$ptr, anonymous_15036:{ *:[i64] }:$value, offset:{ *:[i32] }:$offset, 0:{ *:[i1] })
        GIR_BuildMI, /*InsnID*/0, /*Opcode*/GIMT_Encode2(AMDGPU::DS_MIN_U64_gfx9),
        GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/0, // ptr
        GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/2, // value
        GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/1, // offset
        GIR_AddImm8, /*InsnID*/0, /*Imm*/0,
        GIR_MergeMemOperands, /*InsnID*/0, /*NumInsns*/1, /*MergeInsnID's*/0,
        GIR_ConstrainSelectedInstOperands, /*InsnID*/0,
        GIR_EraseFromParent, /*InsnID*/0,
        // GIR_Coverage, 7048,
        GIR_Done,
      // Label 2888: @186425
      GIM_Try, /*On fail goto*//*Label 2889*/ GIMT_Encode4(186481), // Rule ID 7050 //
        GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasGDS),
        GIM_CheckMemoryAddressSpace, /*MI*/0, /*MMO*/0, /*NumAddrSpace*/1, /*AddrSpace*/2,
        GIM_CheckHasNoUse, /*MI*/0,
        GIM_CheckPointerToAny, /*MI*/0, /*Op*/1, /*SizeInBits*/0,
        GIM_CheckComplexPattern, /*MI*/0, /*Op*/1, /*Renderer*/GIMT_Encode2(0), GIMT_Encode2(GICP_gi_ds_1addr_1offset),
        // (atomic_load_umin_glue:{ *:[i64] } (DS1Addr1Offset:{ *:[iPTR] } i32:{ *:[i32] }:$ptr, i32:{ *:[i32] }:$offset), i64:{ *:[i64] }:$value)<<P:Predicate_atomic_load_umin_region_m0_noret_64>>  =>  (DS_MIN_U64 ?:{ *:[i32] }:$ptr, anonymous_15036:{ *:[i64] }:$value, offset:{ *:[i32] }:$offset, 1:{ *:[i1] })
        GIR_BuildMI, /*InsnID*/0, /*Opcode*/GIMT_Encode2(AMDGPU::DS_MIN_U64),
        GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/0, // ptr
        GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/2, // value
        GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/1, // offset
        GIR_AddImm8, /*InsnID*/0, /*Imm*/1,
        GIR_MergeMemOperands, /*InsnID*/0, /*NumInsns*/1, /*MergeInsnID's*/0,
        GIR_ConstrainSelectedInstOperands, /*InsnID*/0,
        GIR_EraseFromParent, /*InsnID*/0,
        // GIR_Coverage, 7050,
        GIR_Done,
      // Label 2889: @186481
      GIM_Try, /*On fail goto*//*Label 2890*/ GIMT_Encode4(186544), // Rule ID 7045 //
        GIM_CheckFeatures, GIMT_Encode2(GIFBS_LDSRequiresM0Init),
        GIM_CheckMemoryAddressSpace, /*MI*/0, /*MMO*/0, /*NumAddrSpace*/1, /*AddrSpace*/3,
        GIM_CheckRegBankForClass, /*MI*/0, /*Op*/0, /*RC*/GIMT_Encode2(AMDGPU::AV_64RegClassID),
        GIM_CheckPointerToAny, /*MI*/0, /*Op*/1, /*SizeInBits*/0,
        GIM_CheckComplexPattern, /*MI*/0, /*Op*/1, /*Renderer*/GIMT_Encode2(0), GIMT_Encode2(GICP_gi_ds_1addr_1offset),
        // (atomic_load_umin_glue:{ *:[i64] } (DS1Addr1Offset:{ *:[iPTR] } i32:{ *:[i32] }:$ptr, i32:{ *:[i32] }:$offset), i64:{ *:[i64] }:$value)<<P:Predicate_atomic_load_umin_local_m0_64>>  =>  (DS_MIN_RTN_U64:{ *:[i64] } ?:{ *:[i32] }:$ptr, anonymous_15036:{ *:[i64] }:$value, offset:{ *:[i32] }:$offset, 0:{ *:[i1] })
        GIR_BuildMI, /*InsnID*/0, /*Opcode*/GIMT_Encode2(AMDGPU::DS_MIN_RTN_U64),
        GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/0, // DstI[vdst]
        GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/0, // ptr
        GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/2, // value
        GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/1, // offset
        GIR_AddImm8, /*InsnID*/0, /*Imm*/0,
        GIR_MergeMemOperands, /*InsnID*/0, /*NumInsns*/1, /*MergeInsnID's*/0,
        GIR_ConstrainSelectedInstOperands, /*InsnID*/0,
        GIR_EraseFromParent, /*InsnID*/0,
        // GIR_Coverage, 7045,
        GIR_Done,
      // Label 2890: @186544
      GIM_Try, /*On fail goto*//*Label 2891*/ GIMT_Encode4(186607), // Rule ID 7047 //
        GIM_CheckFeatures, GIMT_Encode2(GIFBS_NotLDSRequiresM0Init),
        GIM_CheckMemoryAddressSpace, /*MI*/0, /*MMO*/0, /*NumAddrSpace*/1, /*AddrSpace*/3,
        GIM_CheckRegBankForClass, /*MI*/0, /*Op*/0, /*RC*/GIMT_Encode2(AMDGPU::AV_64RegClassID),
        GIM_CheckPointerToAny, /*MI*/0, /*Op*/1, /*SizeInBits*/0,
        GIM_CheckComplexPattern, /*MI*/0, /*Op*/1, /*Renderer*/GIMT_Encode2(0), GIMT_Encode2(GICP_gi_ds_1addr_1offset),
        // (atomic_load_umin:{ *:[i64] } (DS1Addr1Offset:{ *:[iPTR] } i32:{ *:[i32] }:$ptr, i32:{ *:[i32] }:$offset), i64:{ *:[i64] }:$value)<<P:Predicate_atomic_load_umin_local_64>>  =>  (DS_MIN_RTN_U64_gfx9:{ *:[i64] } ?:{ *:[i32] }:$ptr, anonymous_15036:{ *:[i64] }:$value, offset:{ *:[i32] }:$offset, 0:{ *:[i1] })
        GIR_BuildMI, /*InsnID*/0, /*Opcode*/GIMT_Encode2(AMDGPU::DS_MIN_RTN_U64_gfx9),
        GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/0, // DstI[vdst]
        GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/0, // ptr
        GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/2, // value
        GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/1, // offset
        GIR_AddImm8, /*InsnID*/0, /*Imm*/0,
        GIR_MergeMemOperands, /*InsnID*/0, /*NumInsns*/1, /*MergeInsnID's*/0,
        GIR_ConstrainSelectedInstOperands, /*InsnID*/0,
        GIR_EraseFromParent, /*InsnID*/0,
        // GIR_Coverage, 7047,
        GIR_Done,
      // Label 2891: @186607
      GIM_Try, /*On fail goto*//*Label 2892*/ GIMT_Encode4(186670), // Rule ID 7049 //
        GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasGDS),
        GIM_CheckMemoryAddressSpace, /*MI*/0, /*MMO*/0, /*NumAddrSpace*/1, /*AddrSpace*/2,
        GIM_CheckRegBankForClass, /*MI*/0, /*Op*/0, /*RC*/GIMT_Encode2(AMDGPU::AV_64RegClassID),
        GIM_CheckPointerToAny, /*MI*/0, /*Op*/1, /*SizeInBits*/0,
        GIM_CheckComplexPattern, /*MI*/0, /*Op*/1, /*Renderer*/GIMT_Encode2(0), GIMT_Encode2(GICP_gi_ds_1addr_1offset),
        // (atomic_load_umin_glue:{ *:[i64] } (DS1Addr1Offset:{ *:[iPTR] } i32:{ *:[i32] }:$ptr, i32:{ *:[i32] }:$offset), i64:{ *:[i64] }:$value)<<P:Predicate_atomic_load_umin_region_m0_64>>  =>  (DS_MIN_RTN_U64:{ *:[i64] } ?:{ *:[i32] }:$ptr, anonymous_15036:{ *:[i64] }:$value, offset:{ *:[i32] }:$offset, 1:{ *:[i1] })
        GIR_BuildMI, /*InsnID*/0, /*Opcode*/GIMT_Encode2(AMDGPU::DS_MIN_RTN_U64),
        GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/0, // DstI[vdst]
        GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/0, // ptr
        GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/2, // value
        GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/1, // offset
        GIR_AddImm8, /*InsnID*/0, /*Imm*/1,
        GIR_MergeMemOperands, /*InsnID*/0, /*NumInsns*/1, /*MergeInsnID's*/0,
        GIR_ConstrainSelectedInstOperands, /*InsnID*/0,
        GIR_EraseFromParent, /*InsnID*/0,
        // GIR_Coverage, 7049,
        GIR_Done,
      // Label 2892: @186670
      GIM_Try, /*On fail goto*//*Label 2893*/ GIMT_Encode4(186733), // Rule ID 3235 //
        GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasFlatGlobalInsts),
        GIM_CheckMemoryAddressSpace, /*MI*/0, /*MMO*/0, /*NumAddrSpace*/3, /*AddrSpace*/1, /*AddrSpace*/4, /*AddrSpace*/6,
        GIM_CheckHasNoUse, /*MI*/0,
        GIM_CheckPointerToAny, /*MI*/0, /*Op*/1, /*SizeInBits*/0,
        GIM_CheckComplexPattern, /*MI*/0, /*Op*/1, /*Renderer*/GIMT_Encode2(0), GIMT_Encode2(GICP_gi_global_saddr),
        // (atomic_load_umin:{ *:[i64] } (GlobalSAddr:{ *:[iPTR] } SReg_64:{ *:[i64] }:$saddr, VGPR_32:{ *:[i32] }:$voffset, i32:{ *:[i32] }:$offset), i64:{ *:[i64] }:$data)<<P:Predicate_atomic_load_umin_global_noret_64>>  =>  (GLOBAL_ATOMIC_UMIN_X2_SADDR ?:{ *:[i32] }:$voffset, anonymous_15036:{ *:[i64] }:$data, ?:{ *:[i64] }:$saddr, ?:{ *:[i32] }:$offset)
        GIR_BuildMI, /*InsnID*/0, /*Opcode*/GIMT_Encode2(AMDGPU::GLOBAL_ATOMIC_UMIN_X2_SADDR),
        GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/1, // voffset
        GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/2, // data
        GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/0, // saddr
        GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/2, // offset
        GIR_AddImm8, /*InsnID*/0, /*Imm*/0,
        GIR_MergeMemOperands, /*InsnID*/0, /*NumInsns*/1, /*MergeInsnID's*/0,
        GIR_ConstrainSelectedInstOperands, /*InsnID*/0,
        GIR_EraseFromParent, /*InsnID*/0,
        // GIR_Coverage, 3235,
        GIR_Done,
      // Label 2893: @186733
      GIM_Try, /*On fail goto*//*Label 2894*/ GIMT_Encode4(186803), // Rule ID 3237 //
        GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasFlatGlobalInsts),
        GIM_CheckMemoryAddressSpace, /*MI*/0, /*MMO*/0, /*NumAddrSpace*/3, /*AddrSpace*/1, /*AddrSpace*/4, /*AddrSpace*/6,
        GIM_CheckRegBankForClass, /*MI*/0, /*Op*/0, /*RC*/GIMT_Encode2(AMDGPU::AV_64RegClassID),
        GIM_CheckPointerToAny, /*MI*/0, /*Op*/1, /*SizeInBits*/0,
        GIM_CheckComplexPattern, /*MI*/0, /*Op*/1, /*Renderer*/GIMT_Encode2(0), GIMT_Encode2(GICP_gi_global_saddr),
        // (atomic_load_umin:{ *:[i64] } (GlobalSAddr:{ *:[iPTR] } SReg_64:{ *:[i64] }:$saddr, VGPR_32:{ *:[i32] }:$voffset, i32:{ *:[i32] }:$offset), i64:{ *:[i64] }:$data)<<P:Predicate_atomic_load_umin_global_64>>  =>  (GLOBAL_ATOMIC_UMIN_X2_SADDR_RTN:{ *:[i64] } ?:{ *:[i32] }:$voffset, anonymous_15036:{ *:[i64] }:$data, ?:{ *:[i64] }:$saddr, ?:{ *:[i32] }:$offset)
        GIR_BuildMI, /*InsnID*/0, /*Opcode*/GIMT_Encode2(AMDGPU::GLOBAL_ATOMIC_UMIN_X2_SADDR_RTN),
        GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/0, // DstI[vdst]
        GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/1, // voffset
        GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/2, // data
        GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/0, // saddr
        GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/2, // offset
        GIR_AddImm8, /*InsnID*/0, /*Imm*/1,
        GIR_MergeMemOperands, /*InsnID*/0, /*NumInsns*/1, /*MergeInsnID's*/0,
        GIR_ConstrainSelectedInstOperands, /*InsnID*/0,
        GIR_EraseFromParent, /*InsnID*/0,
        // GIR_Coverage, 3237,
        GIR_Done,
      // Label 2894: @186803
      GIM_Try, /*On fail goto*//*Label 2895*/ GIMT_Encode4(186861), // Rule ID 3234 //
        GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasFlatGlobalInsts),
        GIM_CheckMemoryAddressSpace, /*MI*/0, /*MMO*/0, /*NumAddrSpace*/3, /*AddrSpace*/1, /*AddrSpace*/4, /*AddrSpace*/6,
        GIM_CheckHasNoUse, /*MI*/0,
        GIM_CheckPointerToAny, /*MI*/0, /*Op*/1, /*SizeInBits*/0,
        GIM_CheckComplexPattern, /*MI*/0, /*Op*/1, /*Renderer*/GIMT_Encode2(0), GIMT_Encode2(GICP_gi_global_offset),
        // (atomic_load_umin:{ *:[i64] } (GlobalOffset:{ *:[iPTR] } i64:{ *:[i64] }:$vaddr, i32:{ *:[i32] }:$offset), i64:{ *:[i64] }:$data)<<P:Predicate_atomic_load_umin_global_noret_64>>  =>  (GLOBAL_ATOMIC_UMIN_X2 VReg_64:{ *:[i64] }:$vaddr, anonymous_15036:{ *:[i64] }:$data, ?:{ *:[i32] }:$offset)
        GIR_BuildMI, /*InsnID*/0, /*Opcode*/GIMT_Encode2(AMDGPU::GLOBAL_ATOMIC_UMIN_X2),
        GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/0, // vaddr
        GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/2, // data
        GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/1, // offset
        GIR_AddImm8, /*InsnID*/0, /*Imm*/0,
        GIR_MergeMemOperands, /*InsnID*/0, /*NumInsns*/1, /*MergeInsnID's*/0,
        GIR_ConstrainSelectedInstOperands, /*InsnID*/0,
        GIR_EraseFromParent, /*InsnID*/0,
        // GIR_Coverage, 3234,
        GIR_Done,
      // Label 2895: @186861
      GIM_Try, /*On fail goto*//*Label 2896*/ GIMT_Encode4(186926), // Rule ID 3236 //
        GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasFlatGlobalInsts),
        GIM_CheckMemoryAddressSpace, /*MI*/0, /*MMO*/0, /*NumAddrSpace*/3, /*AddrSpace*/1, /*AddrSpace*/4, /*AddrSpace*/6,
        GIM_CheckRegBankForClass, /*MI*/0, /*Op*/0, /*RC*/GIMT_Encode2(AMDGPU::AV_64RegClassID),
        GIM_CheckPointerToAny, /*MI*/0, /*Op*/1, /*SizeInBits*/0,
        GIM_CheckComplexPattern, /*MI*/0, /*Op*/1, /*Renderer*/GIMT_Encode2(0), GIMT_Encode2(GICP_gi_global_offset),
        // (atomic_load_umin:{ *:[i64] } (GlobalOffset:{ *:[iPTR] } i64:{ *:[i64] }:$vaddr, i32:{ *:[i32] }:$offset), i64:{ *:[i64] }:$data)<<P:Predicate_atomic_load_umin_global_64>>  =>  (GLOBAL_ATOMIC_UMIN_X2_RTN:{ *:[i64] } VReg_64:{ *:[i64] }:$vaddr, anonymous_15036:{ *:[i64] }:$data, ?:{ *:[i32] }:$offset)
        GIR_BuildMI, /*InsnID*/0, /*Opcode*/GIMT_Encode2(AMDGPU::GLOBAL_ATOMIC_UMIN_X2_RTN),
        GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/0, // DstI[vdst]
        GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/0, // vaddr
        GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/2, // data
        GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/1, // offset
        GIR_AddImm8, /*InsnID*/0, /*Imm*/1,
        GIR_MergeMemOperands, /*InsnID*/0, /*NumInsns*/1, /*MergeInsnID's*/0,
        GIR_ConstrainSelectedInstOperands, /*InsnID*/0,
        GIR_EraseFromParent, /*InsnID*/0,
        // GIR_Coverage, 3236,
        GIR_Done,
      // Label 2896: @186926
      GIM_Try, /*On fail goto*//*Label 2897*/ GIMT_Encode4(186985), // Rule ID 2870 //
        GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasFlatAddressSpace),
        GIM_CheckMemoryAddressSpace, /*MI*/0, /*MMO*/0, /*NumAddrSpace*/4, /*AddrSpace*/0, /*AddrSpace*/1, /*AddrSpace*/4, /*AddrSpace*/6,
        GIM_CheckHasNoUse, /*MI*/0,
        GIM_CheckPointerToAny, /*MI*/0, /*Op*/1, /*SizeInBits*/0,
        GIM_CheckComplexPattern, /*MI*/0, /*Op*/1, /*Renderer*/GIMT_Encode2(0), GIMT_Encode2(GICP_gi_flat_offset),
        // (atomic_load_umin:{ *:[i64] } (FlatOffset:{ *:[iPTR] } i64:{ *:[i64] }:$vaddr, i32:{ *:[i32] }:$offset), i64:{ *:[i64] }:$data)<<P:Predicate_atomic_load_umin_flat_noret_64>>  =>  (FLAT_ATOMIC_UMIN_X2 VReg_64:{ *:[i64] }:$vaddr, anonymous_15036:{ *:[i64] }:$data, ?:{ *:[i32] }:$offset)
        GIR_BuildMI, /*InsnID*/0, /*Opcode*/GIMT_Encode2(AMDGPU::FLAT_ATOMIC_UMIN_X2),
        GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/0, // vaddr
        GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/2, // data
        GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/1, // offset
        GIR_AddImm8, /*InsnID*/0, /*Imm*/0,
        GIR_MergeMemOperands, /*InsnID*/0, /*NumInsns*/1, /*MergeInsnID's*/0,
        GIR_ConstrainSelectedInstOperands, /*InsnID*/0,
        GIR_EraseFromParent, /*InsnID*/0,
        // GIR_Coverage, 2870,
        GIR_Done,
      // Label 2897: @186985
      GIM_Try, /*On fail goto*//*Label 2898*/ GIMT_Encode4(187043), // Rule ID 2922 //
        GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasFlatAddressSpace),
        GIM_CheckMemoryAddressSpace, /*MI*/0, /*MMO*/0, /*NumAddrSpace*/3, /*AddrSpace*/1, /*AddrSpace*/4, /*AddrSpace*/6,
        GIM_CheckHasNoUse, /*MI*/0,
        GIM_CheckPointerToAny, /*MI*/0, /*Op*/1, /*SizeInBits*/0,
        GIM_CheckComplexPattern, /*MI*/0, /*Op*/1, /*Renderer*/GIMT_Encode2(0), GIMT_Encode2(GICP_gi_flat_offset),
        // (atomic_load_umin:{ *:[i64] } (FlatOffset:{ *:[iPTR] } i64:{ *:[i64] }:$vaddr, i32:{ *:[i32] }:$offset), i64:{ *:[i64] }:$data)<<P:Predicate_atomic_load_umin_global_noret_64>>  =>  (FLAT_ATOMIC_UMIN_X2 VReg_64:{ *:[i64] }:$vaddr, anonymous_15036:{ *:[i64] }:$data, ?:{ *:[i32] }:$offset)
        GIR_BuildMI, /*InsnID*/0, /*Opcode*/GIMT_Encode2(AMDGPU::FLAT_ATOMIC_UMIN_X2),
        GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/0, // vaddr
        GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/2, // data
        GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/1, // offset
        GIR_AddImm8, /*InsnID*/0, /*Imm*/0,
        GIR_MergeMemOperands, /*InsnID*/0, /*NumInsns*/1, /*MergeInsnID's*/0,
        GIR_ConstrainSelectedInstOperands, /*InsnID*/0,
        GIR_EraseFromParent, /*InsnID*/0,
        // GIR_Coverage, 2922,
        GIR_Done,
      // Label 2898: @187043
      GIM_Try, /*On fail goto*//*Label 2899*/ GIMT_Encode4(187109), // Rule ID 2869 //
        GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasFlatAddressSpace),
        GIM_CheckMemoryAddressSpace, /*MI*/0, /*MMO*/0, /*NumAddrSpace*/4, /*AddrSpace*/0, /*AddrSpace*/1, /*AddrSpace*/4, /*AddrSpace*/6,
        GIM_CheckRegBankForClass, /*MI*/0, /*Op*/0, /*RC*/GIMT_Encode2(AMDGPU::AV_64RegClassID),
        GIM_CheckPointerToAny, /*MI*/0, /*Op*/1, /*SizeInBits*/0,
        GIM_CheckComplexPattern, /*MI*/0, /*Op*/1, /*Renderer*/GIMT_Encode2(0), GIMT_Encode2(GICP_gi_flat_offset),
        // (atomic_load_umin:{ *:[i64] } (FlatOffset:{ *:[iPTR] } i64:{ *:[i64] }:$vaddr, i32:{ *:[i32] }:$offset), i64:{ *:[i64] }:$data)<<P:Predicate_atomic_load_umin_flat_64>>  =>  (FLAT_ATOMIC_UMIN_X2_RTN:{ *:[i64] } VReg_64:{ *:[i64] }:$vaddr, anonymous_15036:{ *:[i64] }:$data, ?:{ *:[i32] }:$offset)
        GIR_BuildMI, /*InsnID*/0, /*Opcode*/GIMT_Encode2(AMDGPU::FLAT_ATOMIC_UMIN_X2_RTN),
        GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/0, // DstI[vdst]
        GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/0, // vaddr
        GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/2, // data
        GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/1, // offset
        GIR_AddImm8, /*InsnID*/0, /*Imm*/1,
        GIR_MergeMemOperands, /*InsnID*/0, /*NumInsns*/1, /*MergeInsnID's*/0,
        GIR_ConstrainSelectedInstOperands, /*InsnID*/0,
        GIR_EraseFromParent, /*InsnID*/0,
        // GIR_Coverage, 2869,
        GIR_Done,
      // Label 2899: @187109
      GIM_Try, /*On fail goto*//*Label 2900*/ GIMT_Encode4(187174), // Rule ID 2921 //
        GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasFlatAddressSpace),
        GIM_CheckMemoryAddressSpace, /*MI*/0, /*MMO*/0, /*NumAddrSpace*/3, /*AddrSpace*/1, /*AddrSpace*/4, /*AddrSpace*/6,
        GIM_CheckRegBankForClass, /*MI*/0, /*Op*/0, /*RC*/GIMT_Encode2(AMDGPU::AV_64RegClassID),
        GIM_CheckPointerToAny, /*MI*/0, /*Op*/1, /*SizeInBits*/0,
        GIM_CheckComplexPattern, /*MI*/0, /*Op*/1, /*Renderer*/GIMT_Encode2(0), GIMT_Encode2(GICP_gi_flat_offset),
        // (atomic_load_umin:{ *:[i64] } (FlatOffset:{ *:[iPTR] } i64:{ *:[i64] }:$vaddr, i32:{ *:[i32] }:$offset), i64:{ *:[i64] }:$data)<<P:Predicate_atomic_load_umin_global_64>>  =>  (FLAT_ATOMIC_UMIN_X2_RTN:{ *:[i64] } VReg_64:{ *:[i64] }:$vaddr, anonymous_15036:{ *:[i64] }:$data, ?:{ *:[i32] }:$offset)
        GIR_BuildMI, /*InsnID*/0, /*Opcode*/GIMT_Encode2(AMDGPU::FLAT_ATOMIC_UMIN_X2_RTN),
        GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/0, // DstI[vdst]
        GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/0, // vaddr
        GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/2, // data
        GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/1, // offset
        GIR_AddImm8, /*InsnID*/0, /*Imm*/1,
        GIR_MergeMemOperands, /*InsnID*/0, /*NumInsns*/1, /*MergeInsnID's*/0,
        GIR_ConstrainSelectedInstOperands, /*InsnID*/0,
        GIR_EraseFromParent, /*InsnID*/0,
        // GIR_Coverage, 2921,
        GIR_Done,
      // Label 2900: @187174
      GIM_Reject,
    // Label 2878: @187175
    GIM_Reject,
    // Label 2854: @187176
    GIM_Reject,
    // Label 27: @187177
    GIM_SwitchType, /*MI*/0, /*Op*/0, /*[*/GIMT_Encode2(9), GIMT_Encode2(12), /*)*//*default:*//*Label 2904*/ GIMT_Encode4(188585),
    /*GILLT_s32*//*Label 2901*/ GIMT_Encode4(187200),
    /*GILLT_s64*//*Label 2902*/ GIMT_Encode4(187949),
    /*GILLT_v2s16*//*Label 2903*/ GIMT_Encode4(188460),
    // Label 2901: @187200
    GIM_Try, /*On fail goto*//*Label 2905*/ GIMT_Encode4(187948),
      GIM_CheckType, /*MI*/0, /*Op*/2, /*Type*/GILLT_s32,
      GIM_Try, /*On fail goto*//*Label 2906*/ GIMT_Encode4(187265), // Rule ID 6983 //
        GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasLDSFPAtomicAdd_LDSRequiresM0Init),
        GIM_CheckMemoryAddressSpace, /*MI*/0, /*MMO*/0, /*NumAddrSpace*/1, /*AddrSpace*/3,
        GIM_CheckHasNoUse, /*MI*/0,
        GIM_CheckPointerToAny, /*MI*/0, /*Op*/1, /*SizeInBits*/0,
        GIM_CheckComplexPattern, /*MI*/0, /*Op*/1, /*Renderer*/GIMT_Encode2(0), GIMT_Encode2(GICP_gi_ds_1addr_1offset),
        // (atomic_load_fadd_glue:{ *:[f32] } (DS1Addr1Offset:{ *:[iPTR] } i32:{ *:[i32] }:$ptr, i32:{ *:[i32] }:$offset), f32:{ *:[f32] }:$value)<<P:Predicate_atomic_load_fadd_local_m0_noret_32>>  =>  (DS_ADD_F32 ?:{ *:[i32] }:$ptr, anonymous_15037:{ *:[f32] }:$value, offset:{ *:[i32] }:$offset, 0:{ *:[i1] })
        GIR_BuildMI, /*InsnID*/0, /*Opcode*/GIMT_Encode2(AMDGPU::DS_ADD_F32),
        GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/0, // ptr
        GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/2, // value
        GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/1, // offset
        GIR_AddImm8, /*InsnID*/0, /*Imm*/0,
        GIR_MergeMemOperands, /*InsnID*/0, /*NumInsns*/1, /*MergeInsnID's*/0,
        GIR_ConstrainSelectedInstOperands, /*InsnID*/0,
        GIR_EraseFromParent, /*InsnID*/0,
        // GIR_Coverage, 6983,
        GIR_Done,
      // Label 2906: @187265
      GIM_Try, /*On fail goto*//*Label 2907*/ GIMT_Encode4(187321), // Rule ID 6985 //
        GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasLDSFPAtomicAdd_NotLDSRequiresM0Init),
        GIM_CheckMemoryAddressSpace, /*MI*/0, /*MMO*/0, /*NumAddrSpace*/1, /*AddrSpace*/3,
        GIM_CheckHasNoUse, /*MI*/0,
        GIM_CheckPointerToAny, /*MI*/0, /*Op*/1, /*SizeInBits*/0,
        GIM_CheckComplexPattern, /*MI*/0, /*Op*/1, /*Renderer*/GIMT_Encode2(0), GIMT_Encode2(GICP_gi_ds_1addr_1offset),
        // (atomic_load_fadd:{ *:[f32] } (DS1Addr1Offset:{ *:[iPTR] } i32:{ *:[i32] }:$ptr, i32:{ *:[i32] }:$offset), f32:{ *:[f32] }:$value)<<P:Predicate_atomic_load_fadd_local_noret_32>>  =>  (DS_ADD_F32_gfx9 ?:{ *:[i32] }:$ptr, anonymous_15037:{ *:[f32] }:$value, offset:{ *:[i32] }:$offset, 0:{ *:[i1] })
        GIR_BuildMI, /*InsnID*/0, /*Opcode*/GIMT_Encode2(AMDGPU::DS_ADD_F32_gfx9),
        GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/0, // ptr
        GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/2, // value
        GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/1, // offset
        GIR_AddImm8, /*InsnID*/0, /*Imm*/0,
        GIR_MergeMemOperands, /*InsnID*/0, /*NumInsns*/1, /*MergeInsnID's*/0,
        GIR_ConstrainSelectedInstOperands, /*InsnID*/0,
        GIR_EraseFromParent, /*InsnID*/0,
        // GIR_Coverage, 6985,
        GIR_Done,
      // Label 2907: @187321
      GIM_Try, /*On fail goto*//*Label 2908*/ GIMT_Encode4(187377), // Rule ID 6987 //
        GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasGDS_HasLDSFPAtomicAdd),
        GIM_CheckMemoryAddressSpace, /*MI*/0, /*MMO*/0, /*NumAddrSpace*/1, /*AddrSpace*/2,
        GIM_CheckHasNoUse, /*MI*/0,
        GIM_CheckPointerToAny, /*MI*/0, /*Op*/1, /*SizeInBits*/0,
        GIM_CheckComplexPattern, /*MI*/0, /*Op*/1, /*Renderer*/GIMT_Encode2(0), GIMT_Encode2(GICP_gi_ds_1addr_1offset),
        // (atomic_load_fadd_glue:{ *:[f32] } (DS1Addr1Offset:{ *:[iPTR] } i32:{ *:[i32] }:$ptr, i32:{ *:[i32] }:$offset), f32:{ *:[f32] }:$value)<<P:Predicate_atomic_load_fadd_region_m0_noret_32>>  =>  (DS_ADD_F32 ?:{ *:[i32] }:$ptr, anonymous_15037:{ *:[f32] }:$value, offset:{ *:[i32] }:$offset, 1:{ *:[i1] })
        GIR_BuildMI, /*InsnID*/0, /*Opcode*/GIMT_Encode2(AMDGPU::DS_ADD_F32),
        GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/0, // ptr
        GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/2, // value
        GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/1, // offset
        GIR_AddImm8, /*InsnID*/0, /*Imm*/1,
        GIR_MergeMemOperands, /*InsnID*/0, /*NumInsns*/1, /*MergeInsnID's*/0,
        GIR_ConstrainSelectedInstOperands, /*InsnID*/0,
        GIR_EraseFromParent, /*InsnID*/0,
        // GIR_Coverage, 6987,
        GIR_Done,
      // Label 2908: @187377
      GIM_Try, /*On fail goto*//*Label 2909*/ GIMT_Encode4(187440), // Rule ID 6982 //
        GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasLDSFPAtomicAdd_LDSRequiresM0Init),
        GIM_CheckMemoryAddressSpace, /*MI*/0, /*MMO*/0, /*NumAddrSpace*/1, /*AddrSpace*/3,
        GIM_CheckRegBankForClass, /*MI*/0, /*Op*/0, /*RC*/GIMT_Encode2(AMDGPU::AV_32RegClassID),
        GIM_CheckPointerToAny, /*MI*/0, /*Op*/1, /*SizeInBits*/0,
        GIM_CheckComplexPattern, /*MI*/0, /*Op*/1, /*Renderer*/GIMT_Encode2(0), GIMT_Encode2(GICP_gi_ds_1addr_1offset),
        // (atomic_load_fadd_glue:{ *:[f32] } (DS1Addr1Offset:{ *:[iPTR] } i32:{ *:[i32] }:$ptr, i32:{ *:[i32] }:$offset), f32:{ *:[f32] }:$value)<<P:Predicate_atomic_load_fadd_local_m0_32>>  =>  (DS_ADD_RTN_F32:{ *:[f32] } ?:{ *:[i32] }:$ptr, anonymous_15037:{ *:[f32] }:$value, offset:{ *:[i32] }:$offset, 0:{ *:[i1] })
        GIR_BuildMI, /*InsnID*/0, /*Opcode*/GIMT_Encode2(AMDGPU::DS_ADD_RTN_F32),
        GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/0, // DstI[vdst]
        GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/0, // ptr
        GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/2, // value
        GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/1, // offset
        GIR_AddImm8, /*InsnID*/0, /*Imm*/0,
        GIR_MergeMemOperands, /*InsnID*/0, /*NumInsns*/1, /*MergeInsnID's*/0,
        GIR_ConstrainSelectedInstOperands, /*InsnID*/0,
        GIR_EraseFromParent, /*InsnID*/0,
        // GIR_Coverage, 6982,
        GIR_Done,
      // Label 2909: @187440
      GIM_Try, /*On fail goto*//*Label 2910*/ GIMT_Encode4(187503), // Rule ID 6984 //
        GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasLDSFPAtomicAdd_NotLDSRequiresM0Init),
        GIM_CheckMemoryAddressSpace, /*MI*/0, /*MMO*/0, /*NumAddrSpace*/1, /*AddrSpace*/3,
        GIM_CheckRegBankForClass, /*MI*/0, /*Op*/0, /*RC*/GIMT_Encode2(AMDGPU::AV_32RegClassID),
        GIM_CheckPointerToAny, /*MI*/0, /*Op*/1, /*SizeInBits*/0,
        GIM_CheckComplexPattern, /*MI*/0, /*Op*/1, /*Renderer*/GIMT_Encode2(0), GIMT_Encode2(GICP_gi_ds_1addr_1offset),
        // (atomic_load_fadd:{ *:[f32] } (DS1Addr1Offset:{ *:[iPTR] } i32:{ *:[i32] }:$ptr, i32:{ *:[i32] }:$offset), f32:{ *:[f32] }:$value)<<P:Predicate_atomic_load_fadd_local_32>>  =>  (DS_ADD_RTN_F32_gfx9:{ *:[f32] } ?:{ *:[i32] }:$ptr, anonymous_15037:{ *:[f32] }:$value, offset:{ *:[i32] }:$offset, 0:{ *:[i1] })
        GIR_BuildMI, /*InsnID*/0, /*Opcode*/GIMT_Encode2(AMDGPU::DS_ADD_RTN_F32_gfx9),
        GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/0, // DstI[vdst]
        GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/0, // ptr
        GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/2, // value
        GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/1, // offset
        GIR_AddImm8, /*InsnID*/0, /*Imm*/0,
        GIR_MergeMemOperands, /*InsnID*/0, /*NumInsns*/1, /*MergeInsnID's*/0,
        GIR_ConstrainSelectedInstOperands, /*InsnID*/0,
        GIR_EraseFromParent, /*InsnID*/0,
        // GIR_Coverage, 6984,
        GIR_Done,
      // Label 2910: @187503
      GIM_Try, /*On fail goto*//*Label 2911*/ GIMT_Encode4(187566), // Rule ID 6986 //
        GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasGDS_HasLDSFPAtomicAdd),
        GIM_CheckMemoryAddressSpace, /*MI*/0, /*MMO*/0, /*NumAddrSpace*/1, /*AddrSpace*/2,
        GIM_CheckRegBankForClass, /*MI*/0, /*Op*/0, /*RC*/GIMT_Encode2(AMDGPU::AV_32RegClassID),
        GIM_CheckPointerToAny, /*MI*/0, /*Op*/1, /*SizeInBits*/0,
        GIM_CheckComplexPattern, /*MI*/0, /*Op*/1, /*Renderer*/GIMT_Encode2(0), GIMT_Encode2(GICP_gi_ds_1addr_1offset),
        // (atomic_load_fadd_glue:{ *:[f32] } (DS1Addr1Offset:{ *:[iPTR] } i32:{ *:[i32] }:$ptr, i32:{ *:[i32] }:$offset), f32:{ *:[f32] }:$value)<<P:Predicate_atomic_load_fadd_region_m0_32>>  =>  (DS_ADD_RTN_F32:{ *:[f32] } ?:{ *:[i32] }:$ptr, anonymous_15037:{ *:[f32] }:$value, offset:{ *:[i32] }:$offset, 1:{ *:[i1] })
        GIR_BuildMI, /*InsnID*/0, /*Opcode*/GIMT_Encode2(AMDGPU::DS_ADD_RTN_F32),
        GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/0, // DstI[vdst]
        GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/0, // ptr
        GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/2, // value
        GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/1, // offset
        GIR_AddImm8, /*InsnID*/0, /*Imm*/1,
        GIR_MergeMemOperands, /*InsnID*/0, /*NumInsns*/1, /*MergeInsnID's*/0,
        GIR_ConstrainSelectedInstOperands, /*InsnID*/0,
        GIR_EraseFromParent, /*InsnID*/0,
        // GIR_Coverage, 6986,
        GIR_Done,
      // Label 2911: @187566
      GIM_Try, /*On fail goto*//*Label 2912*/ GIMT_Encode4(187629), // Rule ID 3335 //
        GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasAtomicFaddNoRtnInsts),
        GIM_CheckMemoryAddressSpace, /*MI*/0, /*MMO*/0, /*NumAddrSpace*/3, /*AddrSpace*/1, /*AddrSpace*/4, /*AddrSpace*/6,
        GIM_CheckHasNoUse, /*MI*/0,
        GIM_CheckPointerToAny, /*MI*/0, /*Op*/1, /*SizeInBits*/0,
        GIM_CheckComplexPattern, /*MI*/0, /*Op*/1, /*Renderer*/GIMT_Encode2(0), GIMT_Encode2(GICP_gi_global_saddr),
        // (atomic_load_fadd:{ *:[f32] } (GlobalSAddr:{ *:[iPTR] } SReg_64:{ *:[i64] }:$saddr, VGPR_32:{ *:[i32] }:$voffset, i32:{ *:[i32] }:$offset), f32:{ *:[f32] }:$data)<<P:Predicate_atomic_load_fadd_global_noret_32>>  =>  (GLOBAL_ATOMIC_ADD_F32_SADDR ?:{ *:[i32] }:$voffset, anonymous_15037:{ *:[f32] }:$data, ?:{ *:[i64] }:$saddr, ?:{ *:[i32] }:$offset)
        GIR_BuildMI, /*InsnID*/0, /*Opcode*/GIMT_Encode2(AMDGPU::GLOBAL_ATOMIC_ADD_F32_SADDR),
        GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/1, // voffset
        GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/2, // data
        GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/0, // saddr
        GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/2, // offset
        GIR_AddImm8, /*InsnID*/0, /*Imm*/0,
        GIR_MergeMemOperands, /*InsnID*/0, /*NumInsns*/1, /*MergeInsnID's*/0,
        GIR_ConstrainSelectedInstOperands, /*InsnID*/0,
        GIR_EraseFromParent, /*InsnID*/0,
        // GIR_Coverage, 3335,
        GIR_Done,
      // Label 2912: @187629
      GIM_Try, /*On fail goto*//*Label 2913*/ GIMT_Encode4(187699), // Rule ID 3345 //
        GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasAtomicFaddRtnInsts),
        GIM_CheckMemoryAddressSpace, /*MI*/0, /*MMO*/0, /*NumAddrSpace*/3, /*AddrSpace*/1, /*AddrSpace*/4, /*AddrSpace*/6,
        GIM_CheckRegBankForClass, /*MI*/0, /*Op*/0, /*RC*/GIMT_Encode2(AMDGPU::AV_32RegClassID),
        GIM_CheckPointerToAny, /*MI*/0, /*Op*/1, /*SizeInBits*/0,
        GIM_CheckComplexPattern, /*MI*/0, /*Op*/1, /*Renderer*/GIMT_Encode2(0), GIMT_Encode2(GICP_gi_global_saddr),
        // (atomic_load_fadd:{ *:[f32] } (GlobalSAddr:{ *:[iPTR] } SReg_64:{ *:[i64] }:$saddr, VGPR_32:{ *:[i32] }:$voffset, i32:{ *:[i32] }:$offset), f32:{ *:[f32] }:$data)<<P:Predicate_atomic_load_fadd_global_32>>  =>  (GLOBAL_ATOMIC_ADD_F32_SADDR_RTN:{ *:[f32] } ?:{ *:[i32] }:$voffset, anonymous_15037:{ *:[f32] }:$data, ?:{ *:[i64] }:$saddr, ?:{ *:[i32] }:$offset)
        GIR_BuildMI, /*InsnID*/0, /*Opcode*/GIMT_Encode2(AMDGPU::GLOBAL_ATOMIC_ADD_F32_SADDR_RTN),
        GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/0, // DstI[vdst]
        GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/1, // voffset
        GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/2, // data
        GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/0, // saddr
        GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/2, // offset
        GIR_AddImm8, /*InsnID*/0, /*Imm*/1,
        GIR_MergeMemOperands, /*InsnID*/0, /*NumInsns*/1, /*MergeInsnID's*/0,
        GIR_ConstrainSelectedInstOperands, /*InsnID*/0,
        GIR_EraseFromParent, /*InsnID*/0,
        // GIR_Coverage, 3345,
        GIR_Done,
      // Label 2913: @187699
      GIM_Try, /*On fail goto*//*Label 2914*/ GIMT_Encode4(187757), // Rule ID 3334 //
        GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasAtomicFaddNoRtnInsts),
        GIM_CheckMemoryAddressSpace, /*MI*/0, /*MMO*/0, /*NumAddrSpace*/3, /*AddrSpace*/1, /*AddrSpace*/4, /*AddrSpace*/6,
        GIM_CheckHasNoUse, /*MI*/0,
        GIM_CheckPointerToAny, /*MI*/0, /*Op*/1, /*SizeInBits*/0,
        GIM_CheckComplexPattern, /*MI*/0, /*Op*/1, /*Renderer*/GIMT_Encode2(0), GIMT_Encode2(GICP_gi_global_offset),
        // (atomic_load_fadd:{ *:[f32] } (GlobalOffset:{ *:[iPTR] } i64:{ *:[i64] }:$vaddr, i32:{ *:[i32] }:$offset), f32:{ *:[f32] }:$data)<<P:Predicate_atomic_load_fadd_global_noret_32>>  =>  (GLOBAL_ATOMIC_ADD_F32 VReg_64:{ *:[i64] }:$vaddr, anonymous_15037:{ *:[f32] }:$data, ?:{ *:[i32] }:$offset)
        GIR_BuildMI, /*InsnID*/0, /*Opcode*/GIMT_Encode2(AMDGPU::GLOBAL_ATOMIC_ADD_F32),
        GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/0, // vaddr
        GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/2, // data
        GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/1, // offset
        GIR_AddImm8, /*InsnID*/0, /*Imm*/0,
        GIR_MergeMemOperands, /*InsnID*/0, /*NumInsns*/1, /*MergeInsnID's*/0,
        GIR_ConstrainSelectedInstOperands, /*InsnID*/0,
        GIR_EraseFromParent, /*InsnID*/0,
        // GIR_Coverage, 3334,
        GIR_Done,
      // Label 2914: @187757
      GIM_Try, /*On fail goto*//*Label 2915*/ GIMT_Encode4(187822), // Rule ID 3344 //
        GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasAtomicFaddRtnInsts),
        GIM_CheckMemoryAddressSpace, /*MI*/0, /*MMO*/0, /*NumAddrSpace*/3, /*AddrSpace*/1, /*AddrSpace*/4, /*AddrSpace*/6,
        GIM_CheckRegBankForClass, /*MI*/0, /*Op*/0, /*RC*/GIMT_Encode2(AMDGPU::AV_32RegClassID),
        GIM_CheckPointerToAny, /*MI*/0, /*Op*/1, /*SizeInBits*/0,
        GIM_CheckComplexPattern, /*MI*/0, /*Op*/1, /*Renderer*/GIMT_Encode2(0), GIMT_Encode2(GICP_gi_global_offset),
        // (atomic_load_fadd:{ *:[f32] } (GlobalOffset:{ *:[iPTR] } i64:{ *:[i64] }:$vaddr, i32:{ *:[i32] }:$offset), f32:{ *:[f32] }:$data)<<P:Predicate_atomic_load_fadd_global_32>>  =>  (GLOBAL_ATOMIC_ADD_F32_RTN:{ *:[f32] } VReg_64:{ *:[i64] }:$vaddr, anonymous_15037:{ *:[f32] }:$data, ?:{ *:[i32] }:$offset)
        GIR_BuildMI, /*InsnID*/0, /*Opcode*/GIMT_Encode2(AMDGPU::GLOBAL_ATOMIC_ADD_F32_RTN),
        GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/0, // DstI[vdst]
        GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/0, // vaddr
        GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/2, // data
        GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/1, // offset
        GIR_AddImm8, /*InsnID*/0, /*Imm*/1,
        GIR_MergeMemOperands, /*InsnID*/0, /*NumInsns*/1, /*MergeInsnID's*/0,
        GIR_ConstrainSelectedInstOperands, /*InsnID*/0,
        GIR_EraseFromParent, /*InsnID*/0,
        // GIR_Coverage, 3344,
        GIR_Done,
      // Label 2915: @187822
      GIM_Try, /*On fail goto*//*Label 2916*/ GIMT_Encode4(187881), // Rule ID 3393 //
        GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasFlatAtomicFaddF32Inst),
        GIM_CheckMemoryAddressSpace, /*MI*/0, /*MMO*/0, /*NumAddrSpace*/4, /*AddrSpace*/0, /*AddrSpace*/1, /*AddrSpace*/4, /*AddrSpace*/6,
        GIM_CheckHasNoUse, /*MI*/0,
        GIM_CheckPointerToAny, /*MI*/0, /*Op*/1, /*SizeInBits*/0,
        GIM_CheckComplexPattern, /*MI*/0, /*Op*/1, /*Renderer*/GIMT_Encode2(0), GIMT_Encode2(GICP_gi_global_offset),
        // (atomic_load_fadd:{ *:[f32] } (GlobalOffset:{ *:[iPTR] } i64:{ *:[i64] }:$vaddr, i32:{ *:[i32] }:$offset), f32:{ *:[f32] }:$data)<<P:Predicate_atomic_load_fadd_flat_noret_32>>  =>  (FLAT_ATOMIC_ADD_F32 VReg_64:{ *:[i64] }:$vaddr, anonymous_15037:{ *:[f32] }:$data, ?:{ *:[i32] }:$offset)
        GIR_BuildMI, /*InsnID*/0, /*Opcode*/GIMT_Encode2(AMDGPU::FLAT_ATOMIC_ADD_F32),
        GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/0, // vaddr
        GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/2, // data
        GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/1, // offset
        GIR_AddImm8, /*InsnID*/0, /*Imm*/0,
        GIR_MergeMemOperands, /*InsnID*/0, /*NumInsns*/1, /*MergeInsnID's*/0,
        GIR_ConstrainSelectedInstOperands, /*InsnID*/0,
        GIR_EraseFromParent, /*InsnID*/0,
        // GIR_Coverage, 3393,
        GIR_Done,
      // Label 2916: @187881
      GIM_Try, /*On fail goto*//*Label 2917*/ GIMT_Encode4(187947), // Rule ID 3392 //
        GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasFlatAtomicFaddF32Inst),
        GIM_CheckMemoryAddressSpace, /*MI*/0, /*MMO*/0, /*NumAddrSpace*/4, /*AddrSpace*/0, /*AddrSpace*/1, /*AddrSpace*/4, /*AddrSpace*/6,
        GIM_CheckRegBankForClass, /*MI*/0, /*Op*/0, /*RC*/GIMT_Encode2(AMDGPU::AV_32RegClassID),
        GIM_CheckPointerToAny, /*MI*/0, /*Op*/1, /*SizeInBits*/0,
        GIM_CheckComplexPattern, /*MI*/0, /*Op*/1, /*Renderer*/GIMT_Encode2(0), GIMT_Encode2(GICP_gi_global_offset),
        // (atomic_load_fadd:{ *:[f32] } (GlobalOffset:{ *:[iPTR] } i64:{ *:[i64] }:$vaddr, i32:{ *:[i32] }:$offset), f32:{ *:[f32] }:$data)<<P:Predicate_atomic_load_fadd_flat_32>>  =>  (FLAT_ATOMIC_ADD_F32_RTN:{ *:[f32] } VReg_64:{ *:[i64] }:$vaddr, anonymous_15037:{ *:[f32] }:$data, ?:{ *:[i32] }:$offset)
        GIR_BuildMI, /*InsnID*/0, /*Opcode*/GIMT_Encode2(AMDGPU::FLAT_ATOMIC_ADD_F32_RTN),
        GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/0, // DstI[vdst]
        GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/0, // vaddr
        GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/2, // data
        GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/1, // offset
        GIR_AddImm8, /*InsnID*/0, /*Imm*/1,
        GIR_MergeMemOperands, /*InsnID*/0, /*NumInsns*/1, /*MergeInsnID's*/0,
        GIR_ConstrainSelectedInstOperands, /*InsnID*/0,
        GIR_EraseFromParent, /*InsnID*/0,
        // GIR_Coverage, 3392,
        GIR_Done,
      // Label 2917: @187947
      GIM_Reject,
    // Label 2905: @187948
    GIM_Reject,
    // Label 2902: @187949
    GIM_Try, /*On fail goto*//*Label 2918*/ GIMT_Encode4(188459),
      GIM_CheckType, /*MI*/0, /*Op*/2, /*Type*/GILLT_s64,
      GIM_Try, /*On fail goto*//*Label 2919*/ GIMT_Encode4(188014), // Rule ID 7080 //
        GIM_CheckFeatures, GIMT_Encode2(GIFBS_isGFX90APlus),
        GIM_CheckMemoryAddressSpace, /*MI*/0, /*MMO*/0, /*NumAddrSpace*/1, /*AddrSpace*/3,
        GIM_CheckHasNoUse, /*MI*/0,
        GIM_CheckPointerToAny, /*MI*/0, /*Op*/1, /*SizeInBits*/0,
        GIM_CheckComplexPattern, /*MI*/0, /*Op*/1, /*Renderer*/GIMT_Encode2(0), GIMT_Encode2(GICP_gi_ds_1addr_1offset),
        // (atomic_load_fadd:{ *:[f64] } (DS1Addr1Offset:{ *:[iPTR] } i32:{ *:[i32] }:$ptr, i32:{ *:[i32] }:$offset), f64:{ *:[f64] }:$value)<<P:Predicate_atomic_load_fadd_local_noret_64>>  =>  (DS_ADD_F64 ?:{ *:[i32] }:$ptr, anonymous_15036:{ *:[f64] }:$value, offset:{ *:[i32] }:$offset, 0:{ *:[i1] })
        GIR_BuildMI, /*InsnID*/0, /*Opcode*/GIMT_Encode2(AMDGPU::DS_ADD_F64),
        GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/0, // ptr
        GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/2, // value
        GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/1, // offset
        GIR_AddImm8, /*InsnID*/0, /*Imm*/0,
        GIR_MergeMemOperands, /*InsnID*/0, /*NumInsns*/1, /*MergeInsnID's*/0,
        GIR_ConstrainSelectedInstOperands, /*InsnID*/0,
        GIR_EraseFromParent, /*InsnID*/0,
        // GIR_Coverage, 7080,
        GIR_Done,
      // Label 2919: @188014
      GIM_Try, /*On fail goto*//*Label 2920*/ GIMT_Encode4(188077), // Rule ID 7079 //
        GIM_CheckFeatures, GIMT_Encode2(GIFBS_isGFX90APlus),
        GIM_CheckMemoryAddressSpace, /*MI*/0, /*MMO*/0, /*NumAddrSpace*/1, /*AddrSpace*/3,
        GIM_CheckRegBankForClass, /*MI*/0, /*Op*/0, /*RC*/GIMT_Encode2(AMDGPU::AV_64RegClassID),
        GIM_CheckPointerToAny, /*MI*/0, /*Op*/1, /*SizeInBits*/0,
        GIM_CheckComplexPattern, /*MI*/0, /*Op*/1, /*Renderer*/GIMT_Encode2(0), GIMT_Encode2(GICP_gi_ds_1addr_1offset),
        // (atomic_load_fadd:{ *:[f64] } (DS1Addr1Offset:{ *:[iPTR] } i32:{ *:[i32] }:$ptr, i32:{ *:[i32] }:$offset), f64:{ *:[f64] }:$value)<<P:Predicate_atomic_load_fadd_local_64>>  =>  (DS_ADD_RTN_F64:{ *:[f64] } ?:{ *:[i32] }:$ptr, anonymous_15036:{ *:[f64] }:$value, offset:{ *:[i32] }:$offset, 0:{ *:[i1] })
        GIR_BuildMI, /*InsnID*/0, /*Opcode*/GIMT_Encode2(AMDGPU::DS_ADD_RTN_F64),
        GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/0, // DstI[vdst]
        GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/0, // ptr
        GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/2, // value
        GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/1, // offset
        GIR_AddImm8, /*InsnID*/0, /*Imm*/0,
        GIR_MergeMemOperands, /*InsnID*/0, /*NumInsns*/1, /*MergeInsnID's*/0,
        GIR_ConstrainSelectedInstOperands, /*InsnID*/0,
        GIR_EraseFromParent, /*InsnID*/0,
        // GIR_Coverage, 7079,
        GIR_Done,
      // Label 2920: @188077
      GIM_Try, /*On fail goto*//*Label 2921*/ GIMT_Encode4(188140), // Rule ID 3355 //
        GIM_CheckFeatures, GIMT_Encode2(GIFBS_isGFX90APlus),
        GIM_CheckMemoryAddressSpace, /*MI*/0, /*MMO*/0, /*NumAddrSpace*/3, /*AddrSpace*/1, /*AddrSpace*/4, /*AddrSpace*/6,
        GIM_CheckHasNoUse, /*MI*/0,
        GIM_CheckPointerToAny, /*MI*/0, /*Op*/1, /*SizeInBits*/0,
        GIM_CheckComplexPattern, /*MI*/0, /*Op*/1, /*Renderer*/GIMT_Encode2(0), GIMT_Encode2(GICP_gi_global_saddr),
        // (atomic_load_fadd:{ *:[f64] } (GlobalSAddr:{ *:[iPTR] } SReg_64:{ *:[i64] }:$saddr, VGPR_32:{ *:[i32] }:$voffset, i32:{ *:[i32] }:$offset), f64:{ *:[f64] }:$data)<<P:Predicate_atomic_load_fadd_global_noret_64>>  =>  (GLOBAL_ATOMIC_ADD_F64_SADDR ?:{ *:[i32] }:$voffset, anonymous_15036:{ *:[f64] }:$data, ?:{ *:[i64] }:$saddr, ?:{ *:[i32] }:$offset)
        GIR_BuildMI, /*InsnID*/0, /*Opcode*/GIMT_Encode2(AMDGPU::GLOBAL_ATOMIC_ADD_F64_SADDR),
        GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/1, // voffset
        GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/2, // data
        GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/0, // saddr
        GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/2, // offset
        GIR_AddImm8, /*InsnID*/0, /*Imm*/0,
        GIR_MergeMemOperands, /*InsnID*/0, /*NumInsns*/1, /*MergeInsnID's*/0,
        GIR_ConstrainSelectedInstOperands, /*InsnID*/0,
        GIR_EraseFromParent, /*InsnID*/0,
        // GIR_Coverage, 3355,
        GIR_Done,
      // Label 2921: @188140
      GIM_Try, /*On fail goto*//*Label 2922*/ GIMT_Encode4(188210), // Rule ID 3357 //
        GIM_CheckFeatures, GIMT_Encode2(GIFBS_isGFX90APlus),
        GIM_CheckMemoryAddressSpace, /*MI*/0, /*MMO*/0, /*NumAddrSpace*/3, /*AddrSpace*/1, /*AddrSpace*/4, /*AddrSpace*/6,
        GIM_CheckRegBankForClass, /*MI*/0, /*Op*/0, /*RC*/GIMT_Encode2(AMDGPU::AV_64RegClassID),
        GIM_CheckPointerToAny, /*MI*/0, /*Op*/1, /*SizeInBits*/0,
        GIM_CheckComplexPattern, /*MI*/0, /*Op*/1, /*Renderer*/GIMT_Encode2(0), GIMT_Encode2(GICP_gi_global_saddr),
        // (atomic_load_fadd:{ *:[f64] } (GlobalSAddr:{ *:[iPTR] } SReg_64:{ *:[i64] }:$saddr, VGPR_32:{ *:[i32] }:$voffset, i32:{ *:[i32] }:$offset), f64:{ *:[f64] }:$data)<<P:Predicate_atomic_load_fadd_global_64>>  =>  (GLOBAL_ATOMIC_ADD_F64_SADDR_RTN:{ *:[f64] } ?:{ *:[i32] }:$voffset, anonymous_15036:{ *:[f64] }:$data, ?:{ *:[i64] }:$saddr, ?:{ *:[i32] }:$offset)
        GIR_BuildMI, /*InsnID*/0, /*Opcode*/GIMT_Encode2(AMDGPU::GLOBAL_ATOMIC_ADD_F64_SADDR_RTN),
        GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/0, // DstI[vdst]
        GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/1, // voffset
        GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/2, // data
        GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/0, // saddr
        GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/2, // offset
        GIR_AddImm8, /*InsnID*/0, /*Imm*/1,
        GIR_MergeMemOperands, /*InsnID*/0, /*NumInsns*/1, /*MergeInsnID's*/0,
        GIR_ConstrainSelectedInstOperands, /*InsnID*/0,
        GIR_EraseFromParent, /*InsnID*/0,
        // GIR_Coverage, 3357,
        GIR_Done,
      // Label 2922: @188210
      GIM_Try, /*On fail goto*//*Label 2923*/ GIMT_Encode4(188268), // Rule ID 3354 //
        GIM_CheckFeatures, GIMT_Encode2(GIFBS_isGFX90APlus),
        GIM_CheckMemoryAddressSpace, /*MI*/0, /*MMO*/0, /*NumAddrSpace*/3, /*AddrSpace*/1, /*AddrSpace*/4, /*AddrSpace*/6,
        GIM_CheckHasNoUse, /*MI*/0,
        GIM_CheckPointerToAny, /*MI*/0, /*Op*/1, /*SizeInBits*/0,
        GIM_CheckComplexPattern, /*MI*/0, /*Op*/1, /*Renderer*/GIMT_Encode2(0), GIMT_Encode2(GICP_gi_global_offset),
        // (atomic_load_fadd:{ *:[f64] } (GlobalOffset:{ *:[iPTR] } i64:{ *:[i64] }:$vaddr, i32:{ *:[i32] }:$offset), f64:{ *:[f64] }:$data)<<P:Predicate_atomic_load_fadd_global_noret_64>>  =>  (GLOBAL_ATOMIC_ADD_F64 VReg_64:{ *:[i64] }:$vaddr, anonymous_15036:{ *:[f64] }:$data, ?:{ *:[i32] }:$offset)
        GIR_BuildMI, /*InsnID*/0, /*Opcode*/GIMT_Encode2(AMDGPU::GLOBAL_ATOMIC_ADD_F64),
        GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/0, // vaddr
        GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/2, // data
        GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/1, // offset
        GIR_AddImm8, /*InsnID*/0, /*Imm*/0,
        GIR_MergeMemOperands, /*InsnID*/0, /*NumInsns*/1, /*MergeInsnID's*/0,
        GIR_ConstrainSelectedInstOperands, /*InsnID*/0,
        GIR_EraseFromParent, /*InsnID*/0,
        // GIR_Coverage, 3354,
        GIR_Done,
      // Label 2923: @188268
      GIM_Try, /*On fail goto*//*Label 2924*/ GIMT_Encode4(188333), // Rule ID 3356 //
        GIM_CheckFeatures, GIMT_Encode2(GIFBS_isGFX90APlus),
        GIM_CheckMemoryAddressSpace, /*MI*/0, /*MMO*/0, /*NumAddrSpace*/3, /*AddrSpace*/1, /*AddrSpace*/4, /*AddrSpace*/6,
        GIM_CheckRegBankForClass, /*MI*/0, /*Op*/0, /*RC*/GIMT_Encode2(AMDGPU::AV_64RegClassID),
        GIM_CheckPointerToAny, /*MI*/0, /*Op*/1, /*SizeInBits*/0,
        GIM_CheckComplexPattern, /*MI*/0, /*Op*/1, /*Renderer*/GIMT_Encode2(0), GIMT_Encode2(GICP_gi_global_offset),
        // (atomic_load_fadd:{ *:[f64] } (GlobalOffset:{ *:[iPTR] } i64:{ *:[i64] }:$vaddr, i32:{ *:[i32] }:$offset), f64:{ *:[f64] }:$data)<<P:Predicate_atomic_load_fadd_global_64>>  =>  (GLOBAL_ATOMIC_ADD_F64_RTN:{ *:[f64] } VReg_64:{ *:[i64] }:$vaddr, anonymous_15036:{ *:[f64] }:$data, ?:{ *:[i32] }:$offset)
        GIR_BuildMI, /*InsnID*/0, /*Opcode*/GIMT_Encode2(AMDGPU::GLOBAL_ATOMIC_ADD_F64_RTN),
        GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/0, // DstI[vdst]
        GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/0, // vaddr
        GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/2, // data
        GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/1, // offset
        GIR_AddImm8, /*InsnID*/0, /*Imm*/1,
        GIR_MergeMemOperands, /*InsnID*/0, /*NumInsns*/1, /*MergeInsnID's*/0,
        GIR_ConstrainSelectedInstOperands, /*InsnID*/0,
        GIR_EraseFromParent, /*InsnID*/0,
        // GIR_Coverage, 3356,
        GIR_Done,
      // Label 2924: @188333
      GIM_Try, /*On fail goto*//*Label 2925*/ GIMT_Encode4(188392), // Rule ID 3383 //
        GIM_CheckFeatures, GIMT_Encode2(GIFBS_isGFX90APlus),
        GIM_CheckMemoryAddressSpace, /*MI*/0, /*MMO*/0, /*NumAddrSpace*/4, /*AddrSpace*/0, /*AddrSpace*/1, /*AddrSpace*/4, /*AddrSpace*/6,
        GIM_CheckHasNoUse, /*MI*/0,
        GIM_CheckPointerToAny, /*MI*/0, /*Op*/1, /*SizeInBits*/0,
        GIM_CheckComplexPattern, /*MI*/0, /*Op*/1, /*Renderer*/GIMT_Encode2(0), GIMT_Encode2(GICP_gi_global_offset),
        // (atomic_load_fadd:{ *:[f64] } (GlobalOffset:{ *:[iPTR] } i64:{ *:[i64] }:$vaddr, i32:{ *:[i32] }:$offset), f64:{ *:[f64] }:$data)<<P:Predicate_atomic_load_fadd_flat_noret_64>>  =>  (FLAT_ATOMIC_ADD_F64 VReg_64:{ *:[i64] }:$vaddr, anonymous_15036:{ *:[f64] }:$data, ?:{ *:[i32] }:$offset)
        GIR_BuildMI, /*InsnID*/0, /*Opcode*/GIMT_Encode2(AMDGPU::FLAT_ATOMIC_ADD_F64),
        GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/0, // vaddr
        GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/2, // data
        GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/1, // offset
        GIR_AddImm8, /*InsnID*/0, /*Imm*/0,
        GIR_MergeMemOperands, /*InsnID*/0, /*NumInsns*/1, /*MergeInsnID's*/0,
        GIR_ConstrainSelectedInstOperands, /*InsnID*/0,
        GIR_EraseFromParent, /*InsnID*/0,
        // GIR_Coverage, 3383,
        GIR_Done,
      // Label 2925: @188392
      GIM_Try, /*On fail goto*//*Label 2926*/ GIMT_Encode4(188458), // Rule ID 3382 //
        GIM_CheckFeatures, GIMT_Encode2(GIFBS_isGFX90APlus),
        GIM_CheckMemoryAddressSpace, /*MI*/0, /*MMO*/0, /*NumAddrSpace*/4, /*AddrSpace*/0, /*AddrSpace*/1, /*AddrSpace*/4, /*AddrSpace*/6,
        GIM_CheckRegBankForClass, /*MI*/0, /*Op*/0, /*RC*/GIMT_Encode2(AMDGPU::AV_64RegClassID),
        GIM_CheckPointerToAny, /*MI*/0, /*Op*/1, /*SizeInBits*/0,
        GIM_CheckComplexPattern, /*MI*/0, /*Op*/1, /*Renderer*/GIMT_Encode2(0), GIMT_Encode2(GICP_gi_global_offset),
        // (atomic_load_fadd:{ *:[f64] } (GlobalOffset:{ *:[iPTR] } i64:{ *:[i64] }:$vaddr, i32:{ *:[i32] }:$offset), f64:{ *:[f64] }:$data)<<P:Predicate_atomic_load_fadd_flat_64>>  =>  (FLAT_ATOMIC_ADD_F64_RTN:{ *:[f64] } VReg_64:{ *:[i64] }:$vaddr, anonymous_15036:{ *:[f64] }:$data, ?:{ *:[i32] }:$offset)
        GIR_BuildMI, /*InsnID*/0, /*Opcode*/GIMT_Encode2(AMDGPU::FLAT_ATOMIC_ADD_F64_RTN),
        GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/0, // DstI[vdst]
        GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/0, // vaddr
        GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/2, // data
        GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/1, // offset
        GIR_AddImm8, /*InsnID*/0, /*Imm*/1,
        GIR_MergeMemOperands, /*InsnID*/0, /*NumInsns*/1, /*MergeInsnID's*/0,
        GIR_ConstrainSelectedInstOperands, /*InsnID*/0,
        GIR_EraseFromParent, /*InsnID*/0,
        // GIR_Coverage, 3382,
        GIR_Done,
      // Label 2926: @188458
      GIM_Reject,
    // Label 2918: @188459
    GIM_Reject,
    // Label 2903: @188460
    GIM_Try, /*On fail goto*//*Label 2927*/ GIMT_Encode4(188584),
      GIM_CheckType, /*MI*/0, /*Op*/2, /*Type*/GILLT_v2s16,
      GIM_CheckMemoryAddressSpace, /*MI*/0, /*MMO*/0, /*NumAddrSpace*/1, /*AddrSpace*/3,
      GIM_Try, /*On fail goto*//*Label 2928*/ GIMT_Encode4(188525), // Rule ID 7084 //
        GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasAtomicDsPkAdd16Insts),
        GIM_CheckHasNoUse, /*MI*/0,
        GIM_CheckPointerToAny, /*MI*/0, /*Op*/1, /*SizeInBits*/0,
        GIM_CheckComplexPattern, /*MI*/0, /*Op*/1, /*Renderer*/GIMT_Encode2(0), GIMT_Encode2(GICP_gi_ds_1addr_1offset),
        // (atomic_load_fadd:{ *:[v2f16] } (DS1Addr1Offset:{ *:[iPTR] } i32:{ *:[i32] }:$ptr, i32:{ *:[i32] }:$offset), v2f16:{ *:[v2f16] }:$value)<<P:Predicate_atomic_load_fadd_v2f16_local_noret_32>>  =>  (DS_PK_ADD_F16 ?:{ *:[i32] }:$ptr, anonymous_15037:{ *:[v2f16] }:$value, offset:{ *:[i32] }:$offset, 0:{ *:[i1] })
        GIR_BuildMI, /*InsnID*/0, /*Opcode*/GIMT_Encode2(AMDGPU::DS_PK_ADD_F16),
        GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/0, // ptr
        GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/2, // value
        GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/1, // offset
        GIR_AddImm8, /*InsnID*/0, /*Imm*/0,
        GIR_MergeMemOperands, /*InsnID*/0, /*NumInsns*/1, /*MergeInsnID's*/0,
        GIR_ConstrainSelectedInstOperands, /*InsnID*/0,
        GIR_EraseFromParent, /*InsnID*/0,
        // GIR_Coverage, 7084,
        GIR_Done,
      // Label 2928: @188525
      GIM_Try, /*On fail goto*//*Label 2929*/ GIMT_Encode4(188583), // Rule ID 7083 //
        GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasAtomicDsPkAdd16Insts),
        GIM_CheckRegBankForClass, /*MI*/0, /*Op*/0, /*RC*/GIMT_Encode2(AMDGPU::AV_32RegClassID),
        GIM_CheckPointerToAny, /*MI*/0, /*Op*/1, /*SizeInBits*/0,
        GIM_CheckComplexPattern, /*MI*/0, /*Op*/1, /*Renderer*/GIMT_Encode2(0), GIMT_Encode2(GICP_gi_ds_1addr_1offset),
        // (atomic_load_fadd:{ *:[v2f16] } (DS1Addr1Offset:{ *:[iPTR] } i32:{ *:[i32] }:$ptr, i32:{ *:[i32] }:$offset), v2f16:{ *:[v2f16] }:$value)<<P:Predicate_atomic_load_fadd_v2f16_local_32>>  =>  (DS_PK_ADD_RTN_F16:{ *:[v2f16] } ?:{ *:[i32] }:$ptr, anonymous_15037:{ *:[v2f16] }:$value, offset:{ *:[i32] }:$offset, 0:{ *:[i1] })
        GIR_BuildMI, /*InsnID*/0, /*Opcode*/GIMT_Encode2(AMDGPU::DS_PK_ADD_RTN_F16),
        GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/0, // DstI[vdst]
        GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/0, // ptr
        GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/2, // value
        GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/1, // offset
        GIR_AddImm8, /*InsnID*/0, /*Imm*/0,
        GIR_MergeMemOperands, /*InsnID*/0, /*NumInsns*/1, /*MergeInsnID's*/0,
        GIR_ConstrainSelectedInstOperands, /*InsnID*/0,
        GIR_EraseFromParent, /*InsnID*/0,
        // GIR_Coverage, 7083,
        GIR_Done,
      // Label 2929: @188583
      GIM_Reject,
    // Label 2927: @188584
    GIM_Reject,
    // Label 2904: @188585
    GIM_Reject,
    // Label 28: @188586
    GIM_SwitchType, /*MI*/0, /*Op*/0, /*[*/GIMT_Encode2(9), GIMT_Encode2(11), /*)*//*default:*//*Label 2932*/ GIMT_Encode4(191429),
    /*GILLT_s32*//*Label 2930*/ GIMT_Encode4(188605),
    /*GILLT_s64*//*Label 2931*/ GIMT_Encode4(190017),
    // Label 2930: @188605
    GIM_Try, /*On fail goto*//*Label 2933*/ GIMT_Encode4(190016),
      GIM_CheckType, /*MI*/0, /*Op*/2, /*Type*/GILLT_s32,
      GIM_Try, /*On fail goto*//*Label 2934*/ GIMT_Encode4(188682), // Rule ID 4590 //
        GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasUnrestrictedSOffset),
        GIM_CheckMemoryAddressSpace, /*MI*/0, /*MMO*/0, /*NumAddrSpace*/3, /*AddrSpace*/1, /*AddrSpace*/4, /*AddrSpace*/6,
        GIM_CheckHasNoUse, /*MI*/0,
        GIM_CheckPointerToAny, /*MI*/0, /*Op*/1, /*SizeInBits*/0,
        GIM_CheckComplexPattern, /*MI*/0, /*Op*/1, /*Renderer*/GIMT_Encode2(0), GIMT_Encode2(GICP_gi_mubuf_addr64),
        // (atomic_load_uinc_wrap:{ *:[i32] } (MUBUFAddr64:{ *:[iPTR] } v4i32:{ *:[v4i32] }:$srsrc, i64:{ *:[i64] }:$vaddr, i32:{ *:[i32] }:$soffset, i32:{ *:[i32] }:$offset), i32:{ *:[i32] }:$vdata_in)<<P:Predicate_atomic_load_uinc_wrap_global_noret_32>>  =>  (BUFFER_ATOMIC_INC_ADDR64 anonymous_15037:{ *:[i32] }:$vdata_in, VReg_64:{ *:[i64] }:$vaddr, SReg_128:{ *:[v4i32] }:$srsrc, SCSrc_b32:{ *:[i32] }:$soffset, offset:{ *:[i32] }:$offset)
        GIR_BuildMI, /*InsnID*/0, /*Opcode*/GIMT_Encode2(AMDGPU::BUFFER_ATOMIC_INC_ADDR64),
        GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/2, // vdata_in
        GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/1, // vaddr
        GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/0, // srsrc
        GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/2, // soffset
        GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/3, // offset
        GIR_AddImm8, /*InsnID*/0, /*Imm*/0,
        GIR_MergeMemOperands, /*InsnID*/0, /*NumInsns*/1, /*MergeInsnID's*/0,
        GIR_ConstrainSelectedInstOperands, /*InsnID*/0,
        GIR_EraseFromParent, /*InsnID*/0,
        // GIR_Coverage, 4590,
        GIR_Done,
      // Label 2934: @188682
      GIM_Try, /*On fail goto*//*Label 2935*/ GIMT_Encode4(188747), // Rule ID 4594 //
        GIM_CheckMemoryAddressSpace, /*MI*/0, /*MMO*/0, /*NumAddrSpace*/3, /*AddrSpace*/1, /*AddrSpace*/4, /*AddrSpace*/6,
        GIM_CheckHasNoUse, /*MI*/0,
        GIM_CheckPointerToAny, /*MI*/0, /*Op*/1, /*SizeInBits*/0,
        GIM_CheckComplexPattern, /*MI*/0, /*Op*/1, /*Renderer*/GIMT_Encode2(0), GIMT_Encode2(GICP_gi_mubuf_addr64),
        // (atomic_load_uinc_wrap:{ *:[i32] } (MUBUFAddr64:{ *:[iPTR] } v4i32:{ *:[v4i32] }:$srsrc, i64:{ *:[i64] }:$vaddr, i32:{ *:[i32] }:$soffset, i32:{ *:[i32] }:$offset), i32:{ *:[i32] }:$vdata_in)<<P:Predicate_atomic_load_uinc_wrap_global_noret_32>>  =>  (BUFFER_ATOMIC_INC_VBUFFER_ADDR64 anonymous_15037:{ *:[i32] }:$vdata_in, VReg_64:{ *:[i64] }:$vaddr, SReg_128:{ *:[v4i32] }:$srsrc, SCSrc_b32:{ *:[i32] }:$soffset, offset:{ *:[i32] }:$offset)
        GIR_BuildMI, /*InsnID*/0, /*Opcode*/GIMT_Encode2(AMDGPU::BUFFER_ATOMIC_INC_VBUFFER_ADDR64),
        GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/2, // vdata_in
        GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/1, // vaddr
        GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/0, // srsrc
        GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/2, // soffset
        GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/3, // offset
        GIR_AddImm8, /*InsnID*/0, /*Imm*/0,
        GIR_MergeMemOperands, /*InsnID*/0, /*NumInsns*/1, /*MergeInsnID's*/0,
        GIR_ConstrainSelectedInstOperands, /*InsnID*/0,
        GIR_EraseFromParent, /*InsnID*/0,
        // GIR_Coverage, 4594,
        GIR_Done,
      // Label 2935: @188747
      GIM_Try, /*On fail goto*//*Label 2936*/ GIMT_Encode4(188822), // Rule ID 4588 //
        GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasUnrestrictedSOffset),
        GIM_CheckMemoryAddressSpace, /*MI*/0, /*MMO*/0, /*NumAddrSpace*/3, /*AddrSpace*/1, /*AddrSpace*/4, /*AddrSpace*/6,
        GIM_CheckRegBankForClass, /*MI*/0, /*Op*/0, /*RC*/GIMT_Encode2(AMDGPU::AV_32RegClassID),
        GIM_CheckPointerToAny, /*MI*/0, /*Op*/1, /*SizeInBits*/0,
        GIM_CheckComplexPattern, /*MI*/0, /*Op*/1, /*Renderer*/GIMT_Encode2(0), GIMT_Encode2(GICP_gi_mubuf_addr64),
        // (atomic_load_uinc_wrap:{ *:[i32] } (MUBUFAddr64:{ *:[iPTR] } v4i32:{ *:[v4i32] }:$srsrc, i64:{ *:[i64] }:$vaddr, i32:{ *:[i32] }:$soffset, i32:{ *:[i32] }:$offset), i32:{ *:[i32] }:$vdata_in)<<P:Predicate_atomic_load_uinc_wrap_global_32>>  =>  (BUFFER_ATOMIC_INC_ADDR64_RTN:{ *:[i32] } anonymous_15037:{ *:[i32] }:$vdata_in, VReg_64:{ *:[i64] }:$vaddr, SReg_128:{ *:[v4i32] }:$srsrc, SCSrc_b32:{ *:[i32] }:$soffset, offset:{ *:[i32] }:$offset)
        GIR_BuildMI, /*InsnID*/0, /*Opcode*/GIMT_Encode2(AMDGPU::BUFFER_ATOMIC_INC_ADDR64_RTN),
        GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/0, // DstI[vdata]
        GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/2, // vdata_in
        GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/1, // vaddr
        GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/0, // srsrc
        GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/2, // soffset
        GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/3, // offset
        GIR_AddImm8, /*InsnID*/0, /*Imm*/1,
        GIR_MergeMemOperands, /*InsnID*/0, /*NumInsns*/1, /*MergeInsnID's*/0,
        GIR_ConstrainSelectedInstOperands, /*InsnID*/0,
        GIR_EraseFromParent, /*InsnID*/0,
        // GIR_Coverage, 4588,
        GIR_Done,
      // Label 2936: @188822
      GIM_Try, /*On fail goto*//*Label 2937*/ GIMT_Encode4(188894), // Rule ID 4592 //
        GIM_CheckMemoryAddressSpace, /*MI*/0, /*MMO*/0, /*NumAddrSpace*/3, /*AddrSpace*/1, /*AddrSpace*/4, /*AddrSpace*/6,
        GIM_CheckRegBankForClass, /*MI*/0, /*Op*/0, /*RC*/GIMT_Encode2(AMDGPU::AV_32RegClassID),
        GIM_CheckPointerToAny, /*MI*/0, /*Op*/1, /*SizeInBits*/0,
        GIM_CheckComplexPattern, /*MI*/0, /*Op*/1, /*Renderer*/GIMT_Encode2(0), GIMT_Encode2(GICP_gi_mubuf_addr64),
        // (atomic_load_uinc_wrap:{ *:[i32] } (MUBUFAddr64:{ *:[iPTR] } v4i32:{ *:[v4i32] }:$srsrc, i64:{ *:[i64] }:$vaddr, i32:{ *:[i32] }:$soffset, i32:{ *:[i32] }:$offset), i32:{ *:[i32] }:$vdata_in)<<P:Predicate_atomic_load_uinc_wrap_global_32>>  =>  (BUFFER_ATOMIC_INC_VBUFFER_ADDR64_RTN:{ *:[i32] } anonymous_15037:{ *:[i32] }:$vdata_in, VReg_64:{ *:[i64] }:$vaddr, SReg_128:{ *:[v4i32] }:$srsrc, SCSrc_b32:{ *:[i32] }:$soffset, offset:{ *:[i32] }:$offset)
        GIR_BuildMI, /*InsnID*/0, /*Opcode*/GIMT_Encode2(AMDGPU::BUFFER_ATOMIC_INC_VBUFFER_ADDR64_RTN),
        GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/0, // DstI[vdata]
        GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/2, // vdata_in
        GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/1, // vaddr
        GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/0, // srsrc
        GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/2, // soffset
        GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/3, // offset
        GIR_AddImm8, /*InsnID*/0, /*Imm*/1,
        GIR_MergeMemOperands, /*InsnID*/0, /*NumInsns*/1, /*MergeInsnID's*/0,
        GIR_ConstrainSelectedInstOperands, /*InsnID*/0,
        GIR_EraseFromParent, /*InsnID*/0,
        // GIR_Coverage, 4592,
        GIR_Done,
      // Label 2937: @188894
      GIM_Try, /*On fail goto*//*Label 2938*/ GIMT_Encode4(188957), // Rule ID 4589 //
        GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasUnrestrictedSOffset),
        GIM_CheckMemoryAddressSpace, /*MI*/0, /*MMO*/0, /*NumAddrSpace*/3, /*AddrSpace*/1, /*AddrSpace*/4, /*AddrSpace*/6,
        GIM_CheckHasNoUse, /*MI*/0,
        GIM_CheckPointerToAny, /*MI*/0, /*Op*/1, /*SizeInBits*/0,
        GIM_CheckComplexPattern, /*MI*/0, /*Op*/1, /*Renderer*/GIMT_Encode2(0), GIMT_Encode2(GICP_gi_mubuf_offset),
        // (atomic_load_uinc_wrap:{ *:[i32] } (MUBUFOffset:{ *:[iPTR] } v4i32:{ *:[v4i32] }:$srsrc, i32:{ *:[i32] }:$soffset, i32:{ *:[i32] }:$offset), i32:{ *:[i32] }:$vdata_in)<<P:Predicate_atomic_load_uinc_wrap_global_noret_32>>  =>  (BUFFER_ATOMIC_INC_OFFSET anonymous_15037:{ *:[i32] }:$vdata_in, SReg_128:{ *:[v4i32] }:$srsrc, SCSrc_b32:{ *:[i32] }:$soffset, offset:{ *:[i32] }:$offset)
        GIR_BuildMI, /*InsnID*/0, /*Opcode*/GIMT_Encode2(AMDGPU::BUFFER_ATOMIC_INC_OFFSET),
        GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/2, // vdata_in
        GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/0, // srsrc
        GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/1, // soffset
        GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/2, // offset
        GIR_AddImm8, /*InsnID*/0, /*Imm*/0,
        GIR_MergeMemOperands, /*InsnID*/0, /*NumInsns*/1, /*MergeInsnID's*/0,
        GIR_ConstrainSelectedInstOperands, /*InsnID*/0,
        GIR_EraseFromParent, /*InsnID*/0,
        // GIR_Coverage, 4589,
        GIR_Done,
      // Label 2938: @188957
      GIM_Try, /*On fail goto*//*Label 2939*/ GIMT_Encode4(189017), // Rule ID 4593 //
        GIM_CheckMemoryAddressSpace, /*MI*/0, /*MMO*/0, /*NumAddrSpace*/3, /*AddrSpace*/1, /*AddrSpace*/4, /*AddrSpace*/6,
        GIM_CheckHasNoUse, /*MI*/0,
        GIM_CheckPointerToAny, /*MI*/0, /*Op*/1, /*SizeInBits*/0,
        GIM_CheckComplexPattern, /*MI*/0, /*Op*/1, /*Renderer*/GIMT_Encode2(0), GIMT_Encode2(GICP_gi_mubuf_offset),
        // (atomic_load_uinc_wrap:{ *:[i32] } (MUBUFOffset:{ *:[iPTR] } v4i32:{ *:[v4i32] }:$srsrc, i32:{ *:[i32] }:$soffset, i32:{ *:[i32] }:$offset), i32:{ *:[i32] }:$vdata_in)<<P:Predicate_atomic_load_uinc_wrap_global_noret_32>>  =>  (BUFFER_ATOMIC_INC_VBUFFER_OFFSET anonymous_15037:{ *:[i32] }:$vdata_in, SReg_128:{ *:[v4i32] }:$srsrc, SCSrc_b32:{ *:[i32] }:$soffset, offset:{ *:[i32] }:$offset)
        GIR_BuildMI, /*InsnID*/0, /*Opcode*/GIMT_Encode2(AMDGPU::BUFFER_ATOMIC_INC_VBUFFER_OFFSET),
        GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/2, // vdata_in
        GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/0, // srsrc
        GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/1, // soffset
        GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/2, // offset
        GIR_AddImm8, /*InsnID*/0, /*Imm*/0,
        GIR_MergeMemOperands, /*InsnID*/0, /*NumInsns*/1, /*MergeInsnID's*/0,
        GIR_ConstrainSelectedInstOperands, /*InsnID*/0,
        GIR_EraseFromParent, /*InsnID*/0,
        // GIR_Coverage, 4593,
        GIR_Done,
      // Label 2939: @189017
      GIM_Try, /*On fail goto*//*Label 2940*/ GIMT_Encode4(189087), // Rule ID 4587 //
        GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasUnrestrictedSOffset),
        GIM_CheckMemoryAddressSpace, /*MI*/0, /*MMO*/0, /*NumAddrSpace*/3, /*AddrSpace*/1, /*AddrSpace*/4, /*AddrSpace*/6,
        GIM_CheckRegBankForClass, /*MI*/0, /*Op*/0, /*RC*/GIMT_Encode2(AMDGPU::AV_32RegClassID),
        GIM_CheckPointerToAny, /*MI*/0, /*Op*/1, /*SizeInBits*/0,
        GIM_CheckComplexPattern, /*MI*/0, /*Op*/1, /*Renderer*/GIMT_Encode2(0), GIMT_Encode2(GICP_gi_mubuf_offset),
        // (atomic_load_uinc_wrap:{ *:[i32] } (MUBUFOffset:{ *:[iPTR] } v4i32:{ *:[v4i32] }:$srsrc, i32:{ *:[i32] }:$soffset, i32:{ *:[i32] }:$offset), i32:{ *:[i32] }:$vdata_in)<<P:Predicate_atomic_load_uinc_wrap_global_32>>  =>  (BUFFER_ATOMIC_INC_OFFSET_RTN:{ *:[i32] } anonymous_15037:{ *:[i32] }:$vdata_in, SReg_128:{ *:[v4i32] }:$srsrc, SCSrc_b32:{ *:[i32] }:$soffset, offset:{ *:[i32] }:$offset)
        GIR_BuildMI, /*InsnID*/0, /*Opcode*/GIMT_Encode2(AMDGPU::BUFFER_ATOMIC_INC_OFFSET_RTN),
        GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/0, // DstI[vdata]
        GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/2, // vdata_in
        GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/0, // srsrc
        GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/1, // soffset
        GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/2, // offset
        GIR_AddImm8, /*InsnID*/0, /*Imm*/1,
        GIR_MergeMemOperands, /*InsnID*/0, /*NumInsns*/1, /*MergeInsnID's*/0,
        GIR_ConstrainSelectedInstOperands, /*InsnID*/0,
        GIR_EraseFromParent, /*InsnID*/0,
        // GIR_Coverage, 4587,
        GIR_Done,
      // Label 2940: @189087
      GIM_Try, /*On fail goto*//*Label 2941*/ GIMT_Encode4(189154), // Rule ID 4591 //
        GIM_CheckMemoryAddressSpace, /*MI*/0, /*MMO*/0, /*NumAddrSpace*/3, /*AddrSpace*/1, /*AddrSpace*/4, /*AddrSpace*/6,
        GIM_CheckRegBankForClass, /*MI*/0, /*Op*/0, /*RC*/GIMT_Encode2(AMDGPU::AV_32RegClassID),
        GIM_CheckPointerToAny, /*MI*/0, /*Op*/1, /*SizeInBits*/0,
        GIM_CheckComplexPattern, /*MI*/0, /*Op*/1, /*Renderer*/GIMT_Encode2(0), GIMT_Encode2(GICP_gi_mubuf_offset),
        // (atomic_load_uinc_wrap:{ *:[i32] } (MUBUFOffset:{ *:[iPTR] } v4i32:{ *:[v4i32] }:$srsrc, i32:{ *:[i32] }:$soffset, i32:{ *:[i32] }:$offset), i32:{ *:[i32] }:$vdata_in)<<P:Predicate_atomic_load_uinc_wrap_global_32>>  =>  (BUFFER_ATOMIC_INC_VBUFFER_OFFSET_RTN:{ *:[i32] } anonymous_15037:{ *:[i32] }:$vdata_in, SReg_128:{ *:[v4i32] }:$srsrc, SCSrc_b32:{ *:[i32] }:$soffset, offset:{ *:[i32] }:$offset)
        GIR_BuildMI, /*InsnID*/0, /*Opcode*/GIMT_Encode2(AMDGPU::BUFFER_ATOMIC_INC_VBUFFER_OFFSET_RTN),
        GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/0, // DstI[vdata]
        GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/2, // vdata_in
        GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/0, // srsrc
        GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/1, // soffset
        GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/2, // offset
        GIR_AddImm8, /*InsnID*/0, /*Imm*/1,
        GIR_MergeMemOperands, /*InsnID*/0, /*NumInsns*/1, /*MergeInsnID's*/0,
        GIR_ConstrainSelectedInstOperands, /*InsnID*/0,
        GIR_EraseFromParent, /*InsnID*/0,
        // GIR_Coverage, 4591,
        GIR_Done,
      // Label 2941: @189154
      GIM_Try, /*On fail goto*//*Label 2942*/ GIMT_Encode4(189210), // Rule ID 6917 //
        GIM_CheckFeatures, GIMT_Encode2(GIFBS_LDSRequiresM0Init),
        GIM_CheckMemoryAddressSpace, /*MI*/0, /*MMO*/0, /*NumAddrSpace*/1, /*AddrSpace*/3,
        GIM_CheckHasNoUse, /*MI*/0,
        GIM_CheckPointerToAny, /*MI*/0, /*Op*/1, /*SizeInBits*/0,
        GIM_CheckComplexPattern, /*MI*/0, /*Op*/1, /*Renderer*/GIMT_Encode2(0), GIMT_Encode2(GICP_gi_ds_1addr_1offset),
        // (atomic_load_uinc_wrap_glue:{ *:[i32] } (DS1Addr1Offset:{ *:[iPTR] } i32:{ *:[i32] }:$ptr, i32:{ *:[i32] }:$offset), i32:{ *:[i32] }:$value)<<P:Predicate_atomic_load_uinc_wrap_local_m0_noret_32>>  =>  (DS_INC_U32 ?:{ *:[i32] }:$ptr, anonymous_15037:{ *:[i32] }:$value, offset:{ *:[i32] }:$offset, 0:{ *:[i1] })
        GIR_BuildMI, /*InsnID*/0, /*Opcode*/GIMT_Encode2(AMDGPU::DS_INC_U32),
        GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/0, // ptr
        GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/2, // value
        GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/1, // offset
        GIR_AddImm8, /*InsnID*/0, /*Imm*/0,
        GIR_MergeMemOperands, /*InsnID*/0, /*NumInsns*/1, /*MergeInsnID's*/0,
        GIR_ConstrainSelectedInstOperands, /*InsnID*/0,
        GIR_EraseFromParent, /*InsnID*/0,
        // GIR_Coverage, 6917,
        GIR_Done,
      // Label 2942: @189210
      GIM_Try, /*On fail goto*//*Label 2943*/ GIMT_Encode4(189266), // Rule ID 6919 //
        GIM_CheckFeatures, GIMT_Encode2(GIFBS_NotLDSRequiresM0Init),
        GIM_CheckMemoryAddressSpace, /*MI*/0, /*MMO*/0, /*NumAddrSpace*/1, /*AddrSpace*/3,
        GIM_CheckHasNoUse, /*MI*/0,
        GIM_CheckPointerToAny, /*MI*/0, /*Op*/1, /*SizeInBits*/0,
        GIM_CheckComplexPattern, /*MI*/0, /*Op*/1, /*Renderer*/GIMT_Encode2(0), GIMT_Encode2(GICP_gi_ds_1addr_1offset),
        // (atomic_load_uinc_wrap:{ *:[i32] } (DS1Addr1Offset:{ *:[iPTR] } i32:{ *:[i32] }:$ptr, i32:{ *:[i32] }:$offset), i32:{ *:[i32] }:$value)<<P:Predicate_atomic_load_uinc_wrap_local_noret_32>>  =>  (DS_INC_U32_gfx9 ?:{ *:[i32] }:$ptr, anonymous_15037:{ *:[i32] }:$value, offset:{ *:[i32] }:$offset, 0:{ *:[i1] })
        GIR_BuildMI, /*InsnID*/0, /*Opcode*/GIMT_Encode2(AMDGPU::DS_INC_U32_gfx9),
        GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/0, // ptr
        GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/2, // value
        GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/1, // offset
        GIR_AddImm8, /*InsnID*/0, /*Imm*/0,
        GIR_MergeMemOperands, /*InsnID*/0, /*NumInsns*/1, /*MergeInsnID's*/0,
        GIR_ConstrainSelectedInstOperands, /*InsnID*/0,
        GIR_EraseFromParent, /*InsnID*/0,
        // GIR_Coverage, 6919,
        GIR_Done,
      // Label 2943: @189266
      GIM_Try, /*On fail goto*//*Label 2944*/ GIMT_Encode4(189322), // Rule ID 6921 //
        GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasGDS),
        GIM_CheckMemoryAddressSpace, /*MI*/0, /*MMO*/0, /*NumAddrSpace*/1, /*AddrSpace*/2,
        GIM_CheckHasNoUse, /*MI*/0,
        GIM_CheckPointerToAny, /*MI*/0, /*Op*/1, /*SizeInBits*/0,
        GIM_CheckComplexPattern, /*MI*/0, /*Op*/1, /*Renderer*/GIMT_Encode2(0), GIMT_Encode2(GICP_gi_ds_1addr_1offset),
        // (atomic_load_uinc_wrap_glue:{ *:[i32] } (DS1Addr1Offset:{ *:[iPTR] } i32:{ *:[i32] }:$ptr, i32:{ *:[i32] }:$offset), i32:{ *:[i32] }:$value)<<P:Predicate_atomic_load_uinc_wrap_region_m0_noret_32>>  =>  (DS_INC_U32 ?:{ *:[i32] }:$ptr, anonymous_15037:{ *:[i32] }:$value, offset:{ *:[i32] }:$offset, 1:{ *:[i1] })
        GIR_BuildMI, /*InsnID*/0, /*Opcode*/GIMT_Encode2(AMDGPU::DS_INC_U32),
        GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/0, // ptr
        GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/2, // value
        GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/1, // offset
        GIR_AddImm8, /*InsnID*/0, /*Imm*/1,
        GIR_MergeMemOperands, /*InsnID*/0, /*NumInsns*/1, /*MergeInsnID's*/0,
        GIR_ConstrainSelectedInstOperands, /*InsnID*/0,
        GIR_EraseFromParent, /*InsnID*/0,
        // GIR_Coverage, 6921,
        GIR_Done,
      // Label 2944: @189322
      GIM_Try, /*On fail goto*//*Label 2945*/ GIMT_Encode4(189385), // Rule ID 6916 //
        GIM_CheckFeatures, GIMT_Encode2(GIFBS_LDSRequiresM0Init),
        GIM_CheckMemoryAddressSpace, /*MI*/0, /*MMO*/0, /*NumAddrSpace*/1, /*AddrSpace*/3,
        GIM_CheckRegBankForClass, /*MI*/0, /*Op*/0, /*RC*/GIMT_Encode2(AMDGPU::AV_32RegClassID),
        GIM_CheckPointerToAny, /*MI*/0, /*Op*/1, /*SizeInBits*/0,
        GIM_CheckComplexPattern, /*MI*/0, /*Op*/1, /*Renderer*/GIMT_Encode2(0), GIMT_Encode2(GICP_gi_ds_1addr_1offset),
        // (atomic_load_uinc_wrap_glue:{ *:[i32] } (DS1Addr1Offset:{ *:[iPTR] } i32:{ *:[i32] }:$ptr, i32:{ *:[i32] }:$offset), i32:{ *:[i32] }:$value)<<P:Predicate_atomic_load_uinc_wrap_local_m0_32>>  =>  (DS_INC_RTN_U32:{ *:[i32] } ?:{ *:[i32] }:$ptr, anonymous_15037:{ *:[i32] }:$value, offset:{ *:[i32] }:$offset, 0:{ *:[i1] })
        GIR_BuildMI, /*InsnID*/0, /*Opcode*/GIMT_Encode2(AMDGPU::DS_INC_RTN_U32),
        GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/0, // DstI[vdst]
        GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/0, // ptr
        GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/2, // value
        GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/1, // offset
        GIR_AddImm8, /*InsnID*/0, /*Imm*/0,
        GIR_MergeMemOperands, /*InsnID*/0, /*NumInsns*/1, /*MergeInsnID's*/0,
        GIR_ConstrainSelectedInstOperands, /*InsnID*/0,
        GIR_EraseFromParent, /*InsnID*/0,
        // GIR_Coverage, 6916,
        GIR_Done,
      // Label 2945: @189385
      GIM_Try, /*On fail goto*//*Label 2946*/ GIMT_Encode4(189448), // Rule ID 6918 //
        GIM_CheckFeatures, GIMT_Encode2(GIFBS_NotLDSRequiresM0Init),
        GIM_CheckMemoryAddressSpace, /*MI*/0, /*MMO*/0, /*NumAddrSpace*/1, /*AddrSpace*/3,
        GIM_CheckRegBankForClass, /*MI*/0, /*Op*/0, /*RC*/GIMT_Encode2(AMDGPU::AV_32RegClassID),
        GIM_CheckPointerToAny, /*MI*/0, /*Op*/1, /*SizeInBits*/0,
        GIM_CheckComplexPattern, /*MI*/0, /*Op*/1, /*Renderer*/GIMT_Encode2(0), GIMT_Encode2(GICP_gi_ds_1addr_1offset),
        // (atomic_load_uinc_wrap:{ *:[i32] } (DS1Addr1Offset:{ *:[iPTR] } i32:{ *:[i32] }:$ptr, i32:{ *:[i32] }:$offset), i32:{ *:[i32] }:$value)<<P:Predicate_atomic_load_uinc_wrap_local_32>>  =>  (DS_INC_RTN_U32_gfx9:{ *:[i32] } ?:{ *:[i32] }:$ptr, anonymous_15037:{ *:[i32] }:$value, offset:{ *:[i32] }:$offset, 0:{ *:[i1] })
        GIR_BuildMI, /*InsnID*/0, /*Opcode*/GIMT_Encode2(AMDGPU::DS_INC_RTN_U32_gfx9),
        GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/0, // DstI[vdst]
        GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/0, // ptr
        GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/2, // value
        GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/1, // offset
        GIR_AddImm8, /*InsnID*/0, /*Imm*/0,
        GIR_MergeMemOperands, /*InsnID*/0, /*NumInsns*/1, /*MergeInsnID's*/0,
        GIR_ConstrainSelectedInstOperands, /*InsnID*/0,
        GIR_EraseFromParent, /*InsnID*/0,
        // GIR_Coverage, 6918,
        GIR_Done,
      // Label 2946: @189448
      GIM_Try, /*On fail goto*//*Label 2947*/ GIMT_Encode4(189511), // Rule ID 6920 //
        GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasGDS),
        GIM_CheckMemoryAddressSpace, /*MI*/0, /*MMO*/0, /*NumAddrSpace*/1, /*AddrSpace*/2,
        GIM_CheckRegBankForClass, /*MI*/0, /*Op*/0, /*RC*/GIMT_Encode2(AMDGPU::AV_32RegClassID),
        GIM_CheckPointerToAny, /*MI*/0, /*Op*/1, /*SizeInBits*/0,
        GIM_CheckComplexPattern, /*MI*/0, /*Op*/1, /*Renderer*/GIMT_Encode2(0), GIMT_Encode2(GICP_gi_ds_1addr_1offset),
        // (atomic_load_uinc_wrap_glue:{ *:[i32] } (DS1Addr1Offset:{ *:[iPTR] } i32:{ *:[i32] }:$ptr, i32:{ *:[i32] }:$offset), i32:{ *:[i32] }:$value)<<P:Predicate_atomic_load_uinc_wrap_region_m0_32>>  =>  (DS_INC_RTN_U32:{ *:[i32] } ?:{ *:[i32] }:$ptr, anonymous_15037:{ *:[i32] }:$value, offset:{ *:[i32] }:$offset, 1:{ *:[i1] })
        GIR_BuildMI, /*InsnID*/0, /*Opcode*/GIMT_Encode2(AMDGPU::DS_INC_RTN_U32),
        GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/0, // DstI[vdst]
        GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/0, // ptr
        GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/2, // value
        GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/1, // offset
        GIR_AddImm8, /*InsnID*/0, /*Imm*/1,
        GIR_MergeMemOperands, /*InsnID*/0, /*NumInsns*/1, /*MergeInsnID's*/0,
        GIR_ConstrainSelectedInstOperands, /*InsnID*/0,
        GIR_EraseFromParent, /*InsnID*/0,
        // GIR_Coverage, 6920,
        GIR_Done,
      // Label 2947: @189511
      GIM_Try, /*On fail goto*//*Label 2948*/ GIMT_Encode4(189574), // Rule ID 3155 //
        GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasFlatGlobalInsts),
        GIM_CheckMemoryAddressSpace, /*MI*/0, /*MMO*/0, /*NumAddrSpace*/3, /*AddrSpace*/1, /*AddrSpace*/4, /*AddrSpace*/6,
        GIM_CheckHasNoUse, /*MI*/0,
        GIM_CheckPointerToAny, /*MI*/0, /*Op*/1, /*SizeInBits*/0,
        GIM_CheckComplexPattern, /*MI*/0, /*Op*/1, /*Renderer*/GIMT_Encode2(0), GIMT_Encode2(GICP_gi_global_saddr),
        // (atomic_load_uinc_wrap:{ *:[i32] } (GlobalSAddr:{ *:[iPTR] } SReg_64:{ *:[i64] }:$saddr, VGPR_32:{ *:[i32] }:$voffset, i32:{ *:[i32] }:$offset), i32:{ *:[i32] }:$data)<<P:Predicate_atomic_load_uinc_wrap_global_noret_32>>  =>  (GLOBAL_ATOMIC_INC_SADDR ?:{ *:[i32] }:$voffset, anonymous_15037:{ *:[i32] }:$data, ?:{ *:[i64] }:$saddr, ?:{ *:[i32] }:$offset)
        GIR_BuildMI, /*InsnID*/0, /*Opcode*/GIMT_Encode2(AMDGPU::GLOBAL_ATOMIC_INC_SADDR),
        GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/1, // voffset
        GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/2, // data
        GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/0, // saddr
        GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/2, // offset
        GIR_AddImm8, /*InsnID*/0, /*Imm*/0,
        GIR_MergeMemOperands, /*InsnID*/0, /*NumInsns*/1, /*MergeInsnID's*/0,
        GIR_ConstrainSelectedInstOperands, /*InsnID*/0,
        GIR_EraseFromParent, /*InsnID*/0,
        // GIR_Coverage, 3155,
        GIR_Done,
      // Label 2948: @189574
      GIM_Try, /*On fail goto*//*Label 2949*/ GIMT_Encode4(189644), // Rule ID 3157 //
        GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasFlatGlobalInsts),
        GIM_CheckMemoryAddressSpace, /*MI*/0, /*MMO*/0, /*NumAddrSpace*/3, /*AddrSpace*/1, /*AddrSpace*/4, /*AddrSpace*/6,
        GIM_CheckRegBankForClass, /*MI*/0, /*Op*/0, /*RC*/GIMT_Encode2(AMDGPU::AV_32RegClassID),
        GIM_CheckPointerToAny, /*MI*/0, /*Op*/1, /*SizeInBits*/0,
        GIM_CheckComplexPattern, /*MI*/0, /*Op*/1, /*Renderer*/GIMT_Encode2(0), GIMT_Encode2(GICP_gi_global_saddr),
        // (atomic_load_uinc_wrap:{ *:[i32] } (GlobalSAddr:{ *:[iPTR] } SReg_64:{ *:[i64] }:$saddr, VGPR_32:{ *:[i32] }:$voffset, i32:{ *:[i32] }:$offset), i32:{ *:[i32] }:$data)<<P:Predicate_atomic_load_uinc_wrap_global_32>>  =>  (GLOBAL_ATOMIC_INC_SADDR_RTN:{ *:[i32] } ?:{ *:[i32] }:$voffset, anonymous_15037:{ *:[i32] }:$data, ?:{ *:[i64] }:$saddr, ?:{ *:[i32] }:$offset)
        GIR_BuildMI, /*InsnID*/0, /*Opcode*/GIMT_Encode2(AMDGPU::GLOBAL_ATOMIC_INC_SADDR_RTN),
        GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/0, // DstI[vdst]
        GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/1, // voffset
        GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/2, // data
        GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/0, // saddr
        GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/2, // offset
        GIR_AddImm8, /*InsnID*/0, /*Imm*/1,
        GIR_MergeMemOperands, /*InsnID*/0, /*NumInsns*/1, /*MergeInsnID's*/0,
        GIR_ConstrainSelectedInstOperands, /*InsnID*/0,
        GIR_EraseFromParent, /*InsnID*/0,
        // GIR_Coverage, 3157,
        GIR_Done,
      // Label 2949: @189644
      GIM_Try, /*On fail goto*//*Label 2950*/ GIMT_Encode4(189702), // Rule ID 3154 //
        GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasFlatGlobalInsts),
        GIM_CheckMemoryAddressSpace, /*MI*/0, /*MMO*/0, /*NumAddrSpace*/3, /*AddrSpace*/1, /*AddrSpace*/4, /*AddrSpace*/6,
        GIM_CheckHasNoUse, /*MI*/0,
        GIM_CheckPointerToAny, /*MI*/0, /*Op*/1, /*SizeInBits*/0,
        GIM_CheckComplexPattern, /*MI*/0, /*Op*/1, /*Renderer*/GIMT_Encode2(0), GIMT_Encode2(GICP_gi_global_offset),
        // (atomic_load_uinc_wrap:{ *:[i32] } (GlobalOffset:{ *:[iPTR] } i64:{ *:[i64] }:$vaddr, i32:{ *:[i32] }:$offset), i32:{ *:[i32] }:$data)<<P:Predicate_atomic_load_uinc_wrap_global_noret_32>>  =>  (GLOBAL_ATOMIC_INC VReg_64:{ *:[i64] }:$vaddr, anonymous_15037:{ *:[i32] }:$data, ?:{ *:[i32] }:$offset)
        GIR_BuildMI, /*InsnID*/0, /*Opcode*/GIMT_Encode2(AMDGPU::GLOBAL_ATOMIC_INC),
        GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/0, // vaddr
        GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/2, // data
        GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/1, // offset
        GIR_AddImm8, /*InsnID*/0, /*Imm*/0,
        GIR_MergeMemOperands, /*InsnID*/0, /*NumInsns*/1, /*MergeInsnID's*/0,
        GIR_ConstrainSelectedInstOperands, /*InsnID*/0,
        GIR_EraseFromParent, /*InsnID*/0,
        // GIR_Coverage, 3154,
        GIR_Done,
      // Label 2950: @189702
      GIM_Try, /*On fail goto*//*Label 2951*/ GIMT_Encode4(189767), // Rule ID 3156 //
        GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasFlatGlobalInsts),
        GIM_CheckMemoryAddressSpace, /*MI*/0, /*MMO*/0, /*NumAddrSpace*/3, /*AddrSpace*/1, /*AddrSpace*/4, /*AddrSpace*/6,
        GIM_CheckRegBankForClass, /*MI*/0, /*Op*/0, /*RC*/GIMT_Encode2(AMDGPU::AV_32RegClassID),
        GIM_CheckPointerToAny, /*MI*/0, /*Op*/1, /*SizeInBits*/0,
        GIM_CheckComplexPattern, /*MI*/0, /*Op*/1, /*Renderer*/GIMT_Encode2(0), GIMT_Encode2(GICP_gi_global_offset),
        // (atomic_load_uinc_wrap:{ *:[i32] } (GlobalOffset:{ *:[iPTR] } i64:{ *:[i64] }:$vaddr, i32:{ *:[i32] }:$offset), i32:{ *:[i32] }:$data)<<P:Predicate_atomic_load_uinc_wrap_global_32>>  =>  (GLOBAL_ATOMIC_INC_RTN:{ *:[i32] } VReg_64:{ *:[i64] }:$vaddr, anonymous_15037:{ *:[i32] }:$data, ?:{ *:[i32] }:$offset)
        GIR_BuildMI, /*InsnID*/0, /*Opcode*/GIMT_Encode2(AMDGPU::GLOBAL_ATOMIC_INC_RTN),
        GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/0, // DstI[vdst]
        GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/0, // vaddr
        GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/2, // data
        GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/1, // offset
        GIR_AddImm8, /*InsnID*/0, /*Imm*/1,
        GIR_MergeMemOperands, /*InsnID*/0, /*NumInsns*/1, /*MergeInsnID's*/0,
        GIR_ConstrainSelectedInstOperands, /*InsnID*/0,
        GIR_EraseFromParent, /*InsnID*/0,
        // GIR_Coverage, 3156,
        GIR_Done,
      // Label 2951: @189767
      GIM_Try, /*On fail goto*//*Label 2952*/ GIMT_Encode4(189826), // Rule ID 2832 //
        GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasFlatAddressSpace),
        GIM_CheckMemoryAddressSpace, /*MI*/0, /*MMO*/0, /*NumAddrSpace*/4, /*AddrSpace*/0, /*AddrSpace*/1, /*AddrSpace*/4, /*AddrSpace*/6,
        GIM_CheckHasNoUse, /*MI*/0,
        GIM_CheckPointerToAny, /*MI*/0, /*Op*/1, /*SizeInBits*/0,
        GIM_CheckComplexPattern, /*MI*/0, /*Op*/1, /*Renderer*/GIMT_Encode2(0), GIMT_Encode2(GICP_gi_flat_offset),
        // (atomic_load_uinc_wrap:{ *:[i32] } (FlatOffset:{ *:[iPTR] } i64:{ *:[i64] }:$vaddr, i32:{ *:[i32] }:$offset), i32:{ *:[i32] }:$data)<<P:Predicate_atomic_load_uinc_wrap_flat_noret_32>>  =>  (FLAT_ATOMIC_INC VReg_64:{ *:[i64] }:$vaddr, anonymous_15037:{ *:[i32] }:$data, ?:{ *:[i32] }:$offset)
        GIR_BuildMI, /*InsnID*/0, /*Opcode*/GIMT_Encode2(AMDGPU::FLAT_ATOMIC_INC),
        GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/0, // vaddr
        GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/2, // data
        GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/1, // offset
        GIR_AddImm8, /*InsnID*/0, /*Imm*/0,
        GIR_MergeMemOperands, /*InsnID*/0, /*NumInsns*/1, /*MergeInsnID's*/0,
        GIR_ConstrainSelectedInstOperands, /*InsnID*/0,
        GIR_EraseFromParent, /*InsnID*/0,
        // GIR_Coverage, 2832,
        GIR_Done,
      // Label 2952: @189826
      GIM_Try, /*On fail goto*//*Label 2953*/ GIMT_Encode4(189884), // Rule ID 2884 //
        GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasFlatAddressSpace),
        GIM_CheckMemoryAddressSpace, /*MI*/0, /*MMO*/0, /*NumAddrSpace*/3, /*AddrSpace*/1, /*AddrSpace*/4, /*AddrSpace*/6,
        GIM_CheckHasNoUse, /*MI*/0,
        GIM_CheckPointerToAny, /*MI*/0, /*Op*/1, /*SizeInBits*/0,
        GIM_CheckComplexPattern, /*MI*/0, /*Op*/1, /*Renderer*/GIMT_Encode2(0), GIMT_Encode2(GICP_gi_flat_offset),
        // (atomic_load_uinc_wrap:{ *:[i32] } (FlatOffset:{ *:[iPTR] } i64:{ *:[i64] }:$vaddr, i32:{ *:[i32] }:$offset), i32:{ *:[i32] }:$data)<<P:Predicate_atomic_load_uinc_wrap_global_noret_32>>  =>  (FLAT_ATOMIC_INC VReg_64:{ *:[i64] }:$vaddr, anonymous_15037:{ *:[i32] }:$data, ?:{ *:[i32] }:$offset)
        GIR_BuildMI, /*InsnID*/0, /*Opcode*/GIMT_Encode2(AMDGPU::FLAT_ATOMIC_INC),
        GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/0, // vaddr
        GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/2, // data
        GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/1, // offset
        GIR_AddImm8, /*InsnID*/0, /*Imm*/0,
        GIR_MergeMemOperands, /*InsnID*/0, /*NumInsns*/1, /*MergeInsnID's*/0,
        GIR_ConstrainSelectedInstOperands, /*InsnID*/0,
        GIR_EraseFromParent, /*InsnID*/0,
        // GIR_Coverage, 2884,
        GIR_Done,
      // Label 2953: @189884
      GIM_Try, /*On fail goto*//*Label 2954*/ GIMT_Encode4(189950), // Rule ID 2831 //
        GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasFlatAddressSpace),
        GIM_CheckMemoryAddressSpace, /*MI*/0, /*MMO*/0, /*NumAddrSpace*/4, /*AddrSpace*/0, /*AddrSpace*/1, /*AddrSpace*/4, /*AddrSpace*/6,
        GIM_CheckRegBankForClass, /*MI*/0, /*Op*/0, /*RC*/GIMT_Encode2(AMDGPU::AV_32RegClassID),
        GIM_CheckPointerToAny, /*MI*/0, /*Op*/1, /*SizeInBits*/0,
        GIM_CheckComplexPattern, /*MI*/0, /*Op*/1, /*Renderer*/GIMT_Encode2(0), GIMT_Encode2(GICP_gi_flat_offset),
        // (atomic_load_uinc_wrap:{ *:[i32] } (FlatOffset:{ *:[iPTR] } i64:{ *:[i64] }:$vaddr, i32:{ *:[i32] }:$offset), i32:{ *:[i32] }:$data)<<P:Predicate_atomic_load_uinc_wrap_flat_32>>  =>  (FLAT_ATOMIC_INC_RTN:{ *:[i32] } VReg_64:{ *:[i64] }:$vaddr, anonymous_15037:{ *:[i32] }:$data, ?:{ *:[i32] }:$offset)
        GIR_BuildMI, /*InsnID*/0, /*Opcode*/GIMT_Encode2(AMDGPU::FLAT_ATOMIC_INC_RTN),
        GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/0, // DstI[vdst]
        GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/0, // vaddr
        GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/2, // data
        GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/1, // offset
        GIR_AddImm8, /*InsnID*/0, /*Imm*/1,
        GIR_MergeMemOperands, /*InsnID*/0, /*NumInsns*/1, /*MergeInsnID's*/0,
        GIR_ConstrainSelectedInstOperands, /*InsnID*/0,
        GIR_EraseFromParent, /*InsnID*/0,
        // GIR_Coverage, 2831,
        GIR_Done,
      // Label 2954: @189950
      GIM_Try, /*On fail goto*//*Label 2955*/ GIMT_Encode4(190015), // Rule ID 2883 //
        GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasFlatAddressSpace),
        GIM_CheckMemoryAddressSpace, /*MI*/0, /*MMO*/0, /*NumAddrSpace*/3, /*AddrSpace*/1, /*AddrSpace*/4, /*AddrSpace*/6,
        GIM_CheckRegBankForClass, /*MI*/0, /*Op*/0, /*RC*/GIMT_Encode2(AMDGPU::AV_32RegClassID),
        GIM_CheckPointerToAny, /*MI*/0, /*Op*/1, /*SizeInBits*/0,
        GIM_CheckComplexPattern, /*MI*/0, /*Op*/1, /*Renderer*/GIMT_Encode2(0), GIMT_Encode2(GICP_gi_flat_offset),
        // (atomic_load_uinc_wrap:{ *:[i32] } (FlatOffset:{ *:[iPTR] } i64:{ *:[i64] }:$vaddr, i32:{ *:[i32] }:$offset), i32:{ *:[i32] }:$data)<<P:Predicate_atomic_load_uinc_wrap_global_32>>  =>  (FLAT_ATOMIC_INC_RTN:{ *:[i32] } VReg_64:{ *:[i64] }:$vaddr, anonymous_15037:{ *:[i32] }:$data, ?:{ *:[i32] }:$offset)
        GIR_BuildMI, /*InsnID*/0, /*Opcode*/GIMT_Encode2(AMDGPU::FLAT_ATOMIC_INC_RTN),
        GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/0, // DstI[vdst]
        GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/0, // vaddr
        GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/2, // data
        GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/1, // offset
        GIR_AddImm8, /*InsnID*/0, /*Imm*/1,
        GIR_MergeMemOperands, /*InsnID*/0, /*NumInsns*/1, /*MergeInsnID's*/0,
        GIR_ConstrainSelectedInstOperands, /*InsnID*/0,
        GIR_EraseFromParent, /*InsnID*/0,
        // GIR_Coverage, 2883,
        GIR_Done,
      // Label 2955: @190015
      GIM_Reject,
    // Label 2933: @190016
    GIM_Reject,
    // Label 2931: @190017
    GIM_Try, /*On fail goto*//*Label 2956*/ GIMT_Encode4(191428),
      GIM_CheckType, /*MI*/0, /*Op*/2, /*Type*/GILLT_s64,
      GIM_Try, /*On fail goto*//*Label 2957*/ GIMT_Encode4(190094), // Rule ID 4686 //
        GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasUnrestrictedSOffset),
        GIM_CheckMemoryAddressSpace, /*MI*/0, /*MMO*/0, /*NumAddrSpace*/3, /*AddrSpace*/1, /*AddrSpace*/4, /*AddrSpace*/6,
        GIM_CheckHasNoUse, /*MI*/0,
        GIM_CheckPointerToAny, /*MI*/0, /*Op*/1, /*SizeInBits*/0,
        GIM_CheckComplexPattern, /*MI*/0, /*Op*/1, /*Renderer*/GIMT_Encode2(0), GIMT_Encode2(GICP_gi_mubuf_addr64),
        // (atomic_load_uinc_wrap:{ *:[i64] } (MUBUFAddr64:{ *:[iPTR] } v4i32:{ *:[v4i32] }:$srsrc, i64:{ *:[i64] }:$vaddr, i32:{ *:[i32] }:$soffset, i32:{ *:[i32] }:$offset), i64:{ *:[i64] }:$vdata_in)<<P:Predicate_atomic_load_uinc_wrap_global_noret_64>>  =>  (BUFFER_ATOMIC_INC_X2_ADDR64 anonymous_15036:{ *:[i64] }:$vdata_in, VReg_64:{ *:[i64] }:$vaddr, SReg_128:{ *:[v4i32] }:$srsrc, SCSrc_b32:{ *:[i32] }:$soffset, offset:{ *:[i32] }:$offset)
        GIR_BuildMI, /*InsnID*/0, /*Opcode*/GIMT_Encode2(AMDGPU::BUFFER_ATOMIC_INC_X2_ADDR64),
        GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/2, // vdata_in
        GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/1, // vaddr
        GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/0, // srsrc
        GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/2, // soffset
        GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/3, // offset
        GIR_AddImm8, /*InsnID*/0, /*Imm*/0,
        GIR_MergeMemOperands, /*InsnID*/0, /*NumInsns*/1, /*MergeInsnID's*/0,
        GIR_ConstrainSelectedInstOperands, /*InsnID*/0,
        GIR_EraseFromParent, /*InsnID*/0,
        // GIR_Coverage, 4686,
        GIR_Done,
      // Label 2957: @190094
      GIM_Try, /*On fail goto*//*Label 2958*/ GIMT_Encode4(190159), // Rule ID 4690 //
        GIM_CheckMemoryAddressSpace, /*MI*/0, /*MMO*/0, /*NumAddrSpace*/3, /*AddrSpace*/1, /*AddrSpace*/4, /*AddrSpace*/6,
        GIM_CheckHasNoUse, /*MI*/0,
        GIM_CheckPointerToAny, /*MI*/0, /*Op*/1, /*SizeInBits*/0,
        GIM_CheckComplexPattern, /*MI*/0, /*Op*/1, /*Renderer*/GIMT_Encode2(0), GIMT_Encode2(GICP_gi_mubuf_addr64),
        // (atomic_load_uinc_wrap:{ *:[i64] } (MUBUFAddr64:{ *:[iPTR] } v4i32:{ *:[v4i32] }:$srsrc, i64:{ *:[i64] }:$vaddr, i32:{ *:[i32] }:$soffset, i32:{ *:[i32] }:$offset), i64:{ *:[i64] }:$vdata_in)<<P:Predicate_atomic_load_uinc_wrap_global_noret_64>>  =>  (BUFFER_ATOMIC_INC_X2_VBUFFER_ADDR64 anonymous_15036:{ *:[i64] }:$vdata_in, VReg_64:{ *:[i64] }:$vaddr, SReg_128:{ *:[v4i32] }:$srsrc, SCSrc_b32:{ *:[i32] }:$soffset, offset:{ *:[i32] }:$offset)
        GIR_BuildMI, /*InsnID*/0, /*Opcode*/GIMT_Encode2(AMDGPU::BUFFER_ATOMIC_INC_X2_VBUFFER_ADDR64),
        GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/2, // vdata_in
        GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/1, // vaddr
        GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/0, // srsrc
        GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/2, // soffset
        GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/3, // offset
        GIR_AddImm8, /*InsnID*/0, /*Imm*/0,
        GIR_MergeMemOperands, /*InsnID*/0, /*NumInsns*/1, /*MergeInsnID's*/0,
        GIR_ConstrainSelectedInstOperands, /*InsnID*/0,
        GIR_EraseFromParent, /*InsnID*/0,
        // GIR_Coverage, 4690,
        GIR_Done,
      // Label 2958: @190159
      GIM_Try, /*On fail goto*//*Label 2959*/ GIMT_Encode4(190234), // Rule ID 4684 //
        GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasUnrestrictedSOffset),
        GIM_CheckMemoryAddressSpace, /*MI*/0, /*MMO*/0, /*NumAddrSpace*/3, /*AddrSpace*/1, /*AddrSpace*/4, /*AddrSpace*/6,
        GIM_CheckRegBankForClass, /*MI*/0, /*Op*/0, /*RC*/GIMT_Encode2(AMDGPU::AV_64RegClassID),
        GIM_CheckPointerToAny, /*MI*/0, /*Op*/1, /*SizeInBits*/0,
        GIM_CheckComplexPattern, /*MI*/0, /*Op*/1, /*Renderer*/GIMT_Encode2(0), GIMT_Encode2(GICP_gi_mubuf_addr64),
        // (atomic_load_uinc_wrap:{ *:[i64] } (MUBUFAddr64:{ *:[iPTR] } v4i32:{ *:[v4i32] }:$srsrc, i64:{ *:[i64] }:$vaddr, i32:{ *:[i32] }:$soffset, i32:{ *:[i32] }:$offset), i64:{ *:[i64] }:$vdata_in)<<P:Predicate_atomic_load_uinc_wrap_global_64>>  =>  (BUFFER_ATOMIC_INC_X2_ADDR64_RTN:{ *:[i64] } anonymous_15036:{ *:[i64] }:$vdata_in, VReg_64:{ *:[i64] }:$vaddr, SReg_128:{ *:[v4i32] }:$srsrc, SCSrc_b32:{ *:[i32] }:$soffset, offset:{ *:[i32] }:$offset)
        GIR_BuildMI, /*InsnID*/0, /*Opcode*/GIMT_Encode2(AMDGPU::BUFFER_ATOMIC_INC_X2_ADDR64_RTN),
        GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/0, // DstI[vdata]
        GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/2, // vdata_in
        GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/1, // vaddr
        GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/0, // srsrc
        GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/2, // soffset
        GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/3, // offset
        GIR_AddImm8, /*InsnID*/0, /*Imm*/1,
        GIR_MergeMemOperands, /*InsnID*/0, /*NumInsns*/1, /*MergeInsnID's*/0,
        GIR_ConstrainSelectedInstOperands, /*InsnID*/0,
        GIR_EraseFromParent, /*InsnID*/0,
        // GIR_Coverage, 4684,
        GIR_Done,
      // Label 2959: @190234
      GIM_Try, /*On fail goto*//*Label 2960*/ GIMT_Encode4(190306), // Rule ID 4688 //
        GIM_CheckMemoryAddressSpace, /*MI*/0, /*MMO*/0, /*NumAddrSpace*/3, /*AddrSpace*/1, /*AddrSpace*/4, /*AddrSpace*/6,
        GIM_CheckRegBankForClass, /*MI*/0, /*Op*/0, /*RC*/GIMT_Encode2(AMDGPU::AV_64RegClassID),
        GIM_CheckPointerToAny, /*MI*/0, /*Op*/1, /*SizeInBits*/0,
        GIM_CheckComplexPattern, /*MI*/0, /*Op*/1, /*Renderer*/GIMT_Encode2(0), GIMT_Encode2(GICP_gi_mubuf_addr64),
        // (atomic_load_uinc_wrap:{ *:[i64] } (MUBUFAddr64:{ *:[iPTR] } v4i32:{ *:[v4i32] }:$srsrc, i64:{ *:[i64] }:$vaddr, i32:{ *:[i32] }:$soffset, i32:{ *:[i32] }:$offset), i64:{ *:[i64] }:$vdata_in)<<P:Predicate_atomic_load_uinc_wrap_global_64>>  =>  (BUFFER_ATOMIC_INC_X2_VBUFFER_ADDR64_RTN:{ *:[i64] } anonymous_15036:{ *:[i64] }:$vdata_in, VReg_64:{ *:[i64] }:$vaddr, SReg_128:{ *:[v4i32] }:$srsrc, SCSrc_b32:{ *:[i32] }:$soffset, offset:{ *:[i32] }:$offset)
        GIR_BuildMI, /*InsnID*/0, /*Opcode*/GIMT_Encode2(AMDGPU::BUFFER_ATOMIC_INC_X2_VBUFFER_ADDR64_RTN),
        GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/0, // DstI[vdata]
        GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/2, // vdata_in
        GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/1, // vaddr
        GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/0, // srsrc
        GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/2, // soffset
        GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/3, // offset
        GIR_AddImm8, /*InsnID*/0, /*Imm*/1,
        GIR_MergeMemOperands, /*InsnID*/0, /*NumInsns*/1, /*MergeInsnID's*/0,
        GIR_ConstrainSelectedInstOperands, /*InsnID*/0,
        GIR_EraseFromParent, /*InsnID*/0,
        // GIR_Coverage, 4688,
        GIR_Done,
      // Label 2960: @190306
      GIM_Try, /*On fail goto*//*Label 2961*/ GIMT_Encode4(190369), // Rule ID 4685 //
        GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasUnrestrictedSOffset),
        GIM_CheckMemoryAddressSpace, /*MI*/0, /*MMO*/0, /*NumAddrSpace*/3, /*AddrSpace*/1, /*AddrSpace*/4, /*AddrSpace*/6,
        GIM_CheckHasNoUse, /*MI*/0,
        GIM_CheckPointerToAny, /*MI*/0, /*Op*/1, /*SizeInBits*/0,
        GIM_CheckComplexPattern, /*MI*/0, /*Op*/1, /*Renderer*/GIMT_Encode2(0), GIMT_Encode2(GICP_gi_mubuf_offset),
        // (atomic_load_uinc_wrap:{ *:[i64] } (MUBUFOffset:{ *:[iPTR] } v4i32:{ *:[v4i32] }:$srsrc, i32:{ *:[i32] }:$soffset, i32:{ *:[i32] }:$offset), i64:{ *:[i64] }:$vdata_in)<<P:Predicate_atomic_load_uinc_wrap_global_noret_64>>  =>  (BUFFER_ATOMIC_INC_X2_OFFSET anonymous_15036:{ *:[i64] }:$vdata_in, SReg_128:{ *:[v4i32] }:$srsrc, SCSrc_b32:{ *:[i32] }:$soffset, offset:{ *:[i32] }:$offset)
        GIR_BuildMI, /*InsnID*/0, /*Opcode*/GIMT_Encode2(AMDGPU::BUFFER_ATOMIC_INC_X2_OFFSET),
        GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/2, // vdata_in
        GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/0, // srsrc
        GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/1, // soffset
        GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/2, // offset
        GIR_AddImm8, /*InsnID*/0, /*Imm*/0,
        GIR_MergeMemOperands, /*InsnID*/0, /*NumInsns*/1, /*MergeInsnID's*/0,
        GIR_ConstrainSelectedInstOperands, /*InsnID*/0,
        GIR_EraseFromParent, /*InsnID*/0,
        // GIR_Coverage, 4685,
        GIR_Done,
      // Label 2961: @190369
      GIM_Try, /*On fail goto*//*Label 2962*/ GIMT_Encode4(190429), // Rule ID 4689 //
        GIM_CheckMemoryAddressSpace, /*MI*/0, /*MMO*/0, /*NumAddrSpace*/3, /*AddrSpace*/1, /*AddrSpace*/4, /*AddrSpace*/6,
        GIM_CheckHasNoUse, /*MI*/0,
        GIM_CheckPointerToAny, /*MI*/0, /*Op*/1, /*SizeInBits*/0,
        GIM_CheckComplexPattern, /*MI*/0, /*Op*/1, /*Renderer*/GIMT_Encode2(0), GIMT_Encode2(GICP_gi_mubuf_offset),
        // (atomic_load_uinc_wrap:{ *:[i64] } (MUBUFOffset:{ *:[iPTR] } v4i32:{ *:[v4i32] }:$srsrc, i32:{ *:[i32] }:$soffset, i32:{ *:[i32] }:$offset), i64:{ *:[i64] }:$vdata_in)<<P:Predicate_atomic_load_uinc_wrap_global_noret_64>>  =>  (BUFFER_ATOMIC_INC_X2_VBUFFER_OFFSET anonymous_15036:{ *:[i64] }:$vdata_in, SReg_128:{ *:[v4i32] }:$srsrc, SCSrc_b32:{ *:[i32] }:$soffset, offset:{ *:[i32] }:$offset)
        GIR_BuildMI, /*InsnID*/0, /*Opcode*/GIMT_Encode2(AMDGPU::BUFFER_ATOMIC_INC_X2_VBUFFER_OFFSET),
        GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/2, // vdata_in
        GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/0, // srsrc
        GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/1, // soffset
        GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/2, // offset
        GIR_AddImm8, /*InsnID*/0, /*Imm*/0,
        GIR_MergeMemOperands, /*InsnID*/0, /*NumInsns*/1, /*MergeInsnID's*/0,
        GIR_ConstrainSelectedInstOperands, /*InsnID*/0,
        GIR_EraseFromParent, /*InsnID*/0,
        // GIR_Coverage, 4689,
        GIR_Done,
      // Label 2962: @190429
      GIM_Try, /*On fail goto*//*Label 2963*/ GIMT_Encode4(190499), // Rule ID 4683 //
        GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasUnrestrictedSOffset),
        GIM_CheckMemoryAddressSpace, /*MI*/0, /*MMO*/0, /*NumAddrSpace*/3, /*AddrSpace*/1, /*AddrSpace*/4, /*AddrSpace*/6,
        GIM_CheckRegBankForClass, /*MI*/0, /*Op*/0, /*RC*/GIMT_Encode2(AMDGPU::AV_64RegClassID),
        GIM_CheckPointerToAny, /*MI*/0, /*Op*/1, /*SizeInBits*/0,
        GIM_CheckComplexPattern, /*MI*/0, /*Op*/1, /*Renderer*/GIMT_Encode2(0), GIMT_Encode2(GICP_gi_mubuf_offset),
        // (atomic_load_uinc_wrap:{ *:[i64] } (MUBUFOffset:{ *:[iPTR] } v4i32:{ *:[v4i32] }:$srsrc, i32:{ *:[i32] }:$soffset, i32:{ *:[i32] }:$offset), i64:{ *:[i64] }:$vdata_in)<<P:Predicate_atomic_load_uinc_wrap_global_64>>  =>  (BUFFER_ATOMIC_INC_X2_OFFSET_RTN:{ *:[i64] } anonymous_15036:{ *:[i64] }:$vdata_in, SReg_128:{ *:[v4i32] }:$srsrc, SCSrc_b32:{ *:[i32] }:$soffset, offset:{ *:[i32] }:$offset)
        GIR_BuildMI, /*InsnID*/0, /*Opcode*/GIMT_Encode2(AMDGPU::BUFFER_ATOMIC_INC_X2_OFFSET_RTN),
        GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/0, // DstI[vdata]
        GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/2, // vdata_in
        GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/0, // srsrc
        GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/1, // soffset
        GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/2, // offset
        GIR_AddImm8, /*InsnID*/0, /*Imm*/1,
        GIR_MergeMemOperands, /*InsnID*/0, /*NumInsns*/1, /*MergeInsnID's*/0,
        GIR_ConstrainSelectedInstOperands, /*InsnID*/0,
        GIR_EraseFromParent, /*InsnID*/0,
        // GIR_Coverage, 4683,
        GIR_Done,
      // Label 2963: @190499
      GIM_Try, /*On fail goto*//*Label 2964*/ GIMT_Encode4(190566), // Rule ID 4687 //
        GIM_CheckMemoryAddressSpace, /*MI*/0, /*MMO*/0, /*NumAddrSpace*/3, /*AddrSpace*/1, /*AddrSpace*/4, /*AddrSpace*/6,
        GIM_CheckRegBankForClass, /*MI*/0, /*Op*/0, /*RC*/GIMT_Encode2(AMDGPU::AV_64RegClassID),
        GIM_CheckPointerToAny, /*MI*/0, /*Op*/1, /*SizeInBits*/0,
        GIM_CheckComplexPattern, /*MI*/0, /*Op*/1, /*Renderer*/GIMT_Encode2(0), GIMT_Encode2(GICP_gi_mubuf_offset),
        // (atomic_load_uinc_wrap:{ *:[i64] } (MUBUFOffset:{ *:[iPTR] } v4i32:{ *:[v4i32] }:$srsrc, i32:{ *:[i32] }:$soffset, i32:{ *:[i32] }:$offset), i64:{ *:[i64] }:$vdata_in)<<P:Predicate_atomic_load_uinc_wrap_global_64>>  =>  (BUFFER_ATOMIC_INC_X2_VBUFFER_OFFSET_RTN:{ *:[i64] } anonymous_15036:{ *:[i64] }:$vdata_in, SReg_128:{ *:[v4i32] }:$srsrc, SCSrc_b32:{ *:[i32] }:$soffset, offset:{ *:[i32] }:$offset)
        GIR_BuildMI, /*InsnID*/0, /*Opcode*/GIMT_Encode2(AMDGPU::BUFFER_ATOMIC_INC_X2_VBUFFER_OFFSET_RTN),
        GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/0, // DstI[vdata]
        GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/2, // vdata_in
        GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/0, // srsrc
        GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/1, // soffset
        GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/2, // offset
        GIR_AddImm8, /*InsnID*/0, /*Imm*/1,
        GIR_MergeMemOperands, /*InsnID*/0, /*NumInsns*/1, /*MergeInsnID's*/0,
        GIR_ConstrainSelectedInstOperands, /*InsnID*/0,
        GIR_EraseFromParent, /*InsnID*/0,
        // GIR_Coverage, 4687,
        GIR_Done,
      // Label 2964: @190566
      GIM_Try, /*On fail goto*//*Label 2965*/ GIMT_Encode4(190622), // Rule ID 7004 //
        GIM_CheckFeatures, GIMT_Encode2(GIFBS_LDSRequiresM0Init),
        GIM_CheckMemoryAddressSpace, /*MI*/0, /*MMO*/0, /*NumAddrSpace*/1, /*AddrSpace*/3,
        GIM_CheckHasNoUse, /*MI*/0,
        GIM_CheckPointerToAny, /*MI*/0, /*Op*/1, /*SizeInBits*/0,
        GIM_CheckComplexPattern, /*MI*/0, /*Op*/1, /*Renderer*/GIMT_Encode2(0), GIMT_Encode2(GICP_gi_ds_1addr_1offset),
        // (atomic_load_uinc_wrap_glue:{ *:[i64] } (DS1Addr1Offset:{ *:[iPTR] } i32:{ *:[i32] }:$ptr, i32:{ *:[i32] }:$offset), i64:{ *:[i64] }:$value)<<P:Predicate_atomic_load_uinc_wrap_local_m0_noret_64>>  =>  (DS_INC_U64 ?:{ *:[i32] }:$ptr, anonymous_15036:{ *:[i64] }:$value, offset:{ *:[i32] }:$offset, 0:{ *:[i1] })
        GIR_BuildMI, /*InsnID*/0, /*Opcode*/GIMT_Encode2(AMDGPU::DS_INC_U64),
        GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/0, // ptr
        GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/2, // value
        GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/1, // offset
        GIR_AddImm8, /*InsnID*/0, /*Imm*/0,
        GIR_MergeMemOperands, /*InsnID*/0, /*NumInsns*/1, /*MergeInsnID's*/0,
        GIR_ConstrainSelectedInstOperands, /*InsnID*/0,
        GIR_EraseFromParent, /*InsnID*/0,
        // GIR_Coverage, 7004,
        GIR_Done,
      // Label 2965: @190622
      GIM_Try, /*On fail goto*//*Label 2966*/ GIMT_Encode4(190678), // Rule ID 7006 //
        GIM_CheckFeatures, GIMT_Encode2(GIFBS_NotLDSRequiresM0Init),
        GIM_CheckMemoryAddressSpace, /*MI*/0, /*MMO*/0, /*NumAddrSpace*/1, /*AddrSpace*/3,
        GIM_CheckHasNoUse, /*MI*/0,
        GIM_CheckPointerToAny, /*MI*/0, /*Op*/1, /*SizeInBits*/0,
        GIM_CheckComplexPattern, /*MI*/0, /*Op*/1, /*Renderer*/GIMT_Encode2(0), GIMT_Encode2(GICP_gi_ds_1addr_1offset),
        // (atomic_load_uinc_wrap:{ *:[i64] } (DS1Addr1Offset:{ *:[iPTR] } i32:{ *:[i32] }:$ptr, i32:{ *:[i32] }:$offset), i64:{ *:[i64] }:$value)<<P:Predicate_atomic_load_uinc_wrap_local_noret_64>>  =>  (DS_INC_U64_gfx9 ?:{ *:[i32] }:$ptr, anonymous_15036:{ *:[i64] }:$value, offset:{ *:[i32] }:$offset, 0:{ *:[i1] })
        GIR_BuildMI, /*InsnID*/0, /*Opcode*/GIMT_Encode2(AMDGPU::DS_INC_U64_gfx9),
        GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/0, // ptr
        GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/2, // value
        GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/1, // offset
        GIR_AddImm8, /*InsnID*/0, /*Imm*/0,
        GIR_MergeMemOperands, /*InsnID*/0, /*NumInsns*/1, /*MergeInsnID's*/0,
        GIR_ConstrainSelectedInstOperands, /*InsnID*/0,
        GIR_EraseFromParent, /*InsnID*/0,
        // GIR_Coverage, 7006,
        GIR_Done,
      // Label 2966: @190678
      GIM_Try, /*On fail goto*//*Label 2967*/ GIMT_Encode4(190734), // Rule ID 7008 //
        GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasGDS),
        GIM_CheckMemoryAddressSpace, /*MI*/0, /*MMO*/0, /*NumAddrSpace*/1, /*AddrSpace*/2,
        GIM_CheckHasNoUse, /*MI*/0,
        GIM_CheckPointerToAny, /*MI*/0, /*Op*/1, /*SizeInBits*/0,
        GIM_CheckComplexPattern, /*MI*/0, /*Op*/1, /*Renderer*/GIMT_Encode2(0), GIMT_Encode2(GICP_gi_ds_1addr_1offset),
        // (atomic_load_uinc_wrap_glue:{ *:[i64] } (DS1Addr1Offset:{ *:[iPTR] } i32:{ *:[i32] }:$ptr, i32:{ *:[i32] }:$offset), i64:{ *:[i64] }:$value)<<P:Predicate_atomic_load_uinc_wrap_region_m0_noret_64>>  =>  (DS_INC_U64 ?:{ *:[i32] }:$ptr, anonymous_15036:{ *:[i64] }:$value, offset:{ *:[i32] }:$offset, 1:{ *:[i1] })
        GIR_BuildMI, /*InsnID*/0, /*Opcode*/GIMT_Encode2(AMDGPU::DS_INC_U64),
        GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/0, // ptr
        GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/2, // value
        GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/1, // offset
        GIR_AddImm8, /*InsnID*/0, /*Imm*/1,
        GIR_MergeMemOperands, /*InsnID*/0, /*NumInsns*/1, /*MergeInsnID's*/0,
        GIR_ConstrainSelectedInstOperands, /*InsnID*/0,
        GIR_EraseFromParent, /*InsnID*/0,
        // GIR_Coverage, 7008,
        GIR_Done,
      // Label 2967: @190734
      GIM_Try, /*On fail goto*//*Label 2968*/ GIMT_Encode4(190797), // Rule ID 7003 //
        GIM_CheckFeatures, GIMT_Encode2(GIFBS_LDSRequiresM0Init),
        GIM_CheckMemoryAddressSpace, /*MI*/0, /*MMO*/0, /*NumAddrSpace*/1, /*AddrSpace*/3,
        GIM_CheckRegBankForClass, /*MI*/0, /*Op*/0, /*RC*/GIMT_Encode2(AMDGPU::AV_64RegClassID),
        GIM_CheckPointerToAny, /*MI*/0, /*Op*/1, /*SizeInBits*/0,
        GIM_CheckComplexPattern, /*MI*/0, /*Op*/1, /*Renderer*/GIMT_Encode2(0), GIMT_Encode2(GICP_gi_ds_1addr_1offset),
        // (atomic_load_uinc_wrap_glue:{ *:[i64] } (DS1Addr1Offset:{ *:[iPTR] } i32:{ *:[i32] }:$ptr, i32:{ *:[i32] }:$offset), i64:{ *:[i64] }:$value)<<P:Predicate_atomic_load_uinc_wrap_local_m0_64>>  =>  (DS_INC_RTN_U64:{ *:[i64] } ?:{ *:[i32] }:$ptr, anonymous_15036:{ *:[i64] }:$value, offset:{ *:[i32] }:$offset, 0:{ *:[i1] })
        GIR_BuildMI, /*InsnID*/0, /*Opcode*/GIMT_Encode2(AMDGPU::DS_INC_RTN_U64),
        GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/0, // DstI[vdst]
        GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/0, // ptr
        GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/2, // value
        GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/1, // offset
        GIR_AddImm8, /*InsnID*/0, /*Imm*/0,
        GIR_MergeMemOperands, /*InsnID*/0, /*NumInsns*/1, /*MergeInsnID's*/0,
        GIR_ConstrainSelectedInstOperands, /*InsnID*/0,
        GIR_EraseFromParent, /*InsnID*/0,
        // GIR_Coverage, 7003,
        GIR_Done,
      // Label 2968: @190797
      GIM_Try, /*On fail goto*//*Label 2969*/ GIMT_Encode4(190860), // Rule ID 7005 //
        GIM_CheckFeatures, GIMT_Encode2(GIFBS_NotLDSRequiresM0Init),
        GIM_CheckMemoryAddressSpace, /*MI*/0, /*MMO*/0, /*NumAddrSpace*/1, /*AddrSpace*/3,
        GIM_CheckRegBankForClass, /*MI*/0, /*Op*/0, /*RC*/GIMT_Encode2(AMDGPU::AV_64RegClassID),
        GIM_CheckPointerToAny, /*MI*/0, /*Op*/1, /*SizeInBits*/0,
        GIM_CheckComplexPattern, /*MI*/0, /*Op*/1, /*Renderer*/GIMT_Encode2(0), GIMT_Encode2(GICP_gi_ds_1addr_1offset),
        // (atomic_load_uinc_wrap:{ *:[i64] } (DS1Addr1Offset:{ *:[iPTR] } i32:{ *:[i32] }:$ptr, i32:{ *:[i32] }:$offset), i64:{ *:[i64] }:$value)<<P:Predicate_atomic_load_uinc_wrap_local_64>>  =>  (DS_INC_RTN_U64_gfx9:{ *:[i64] } ?:{ *:[i32] }:$ptr, anonymous_15036:{ *:[i64] }:$value, offset:{ *:[i32] }:$offset, 0:{ *:[i1] })
        GIR_BuildMI, /*InsnID*/0, /*Opcode*/GIMT_Encode2(AMDGPU::DS_INC_RTN_U64_gfx9),
        GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/0, // DstI[vdst]
        GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/0, // ptr
        GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/2, // value
        GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/1, // offset
        GIR_AddImm8, /*InsnID*/0, /*Imm*/0,
        GIR_MergeMemOperands, /*InsnID*/0, /*NumInsns*/1, /*MergeInsnID's*/0,
        GIR_ConstrainSelectedInstOperands, /*InsnID*/0,
        GIR_EraseFromParent, /*InsnID*/0,
        // GIR_Coverage, 7005,
        GIR_Done,
      // Label 2969: @190860
      GIM_Try, /*On fail goto*//*Label 2970*/ GIMT_Encode4(190923), // Rule ID 7007 //
        GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasGDS),
        GIM_CheckMemoryAddressSpace, /*MI*/0, /*MMO*/0, /*NumAddrSpace*/1, /*AddrSpace*/2,
        GIM_CheckRegBankForClass, /*MI*/0, /*Op*/0, /*RC*/GIMT_Encode2(AMDGPU::AV_64RegClassID),
        GIM_CheckPointerToAny, /*MI*/0, /*Op*/1, /*SizeInBits*/0,
        GIM_CheckComplexPattern, /*MI*/0, /*Op*/1, /*Renderer*/GIMT_Encode2(0), GIMT_Encode2(GICP_gi_ds_1addr_1offset),
        // (atomic_load_uinc_wrap_glue:{ *:[i64] } (DS1Addr1Offset:{ *:[iPTR] } i32:{ *:[i32] }:$ptr, i32:{ *:[i32] }:$offset), i64:{ *:[i64] }:$value)<<P:Predicate_atomic_load_uinc_wrap_region_m0_64>>  =>  (DS_INC_RTN_U64:{ *:[i64] } ?:{ *:[i32] }:$ptr, anonymous_15036:{ *:[i64] }:$value, offset:{ *:[i32] }:$offset, 1:{ *:[i1] })
        GIR_BuildMI, /*InsnID*/0, /*Opcode*/GIMT_Encode2(AMDGPU::DS_INC_RTN_U64),
        GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/0, // DstI[vdst]
        GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/0, // ptr
        GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/2, // value
        GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/1, // offset
        GIR_AddImm8, /*InsnID*/0, /*Imm*/1,
        GIR_MergeMemOperands, /*InsnID*/0, /*NumInsns*/1, /*MergeInsnID's*/0,
        GIR_ConstrainSelectedInstOperands, /*InsnID*/0,
        GIR_EraseFromParent, /*InsnID*/0,
        // GIR_Coverage, 7007,
        GIR_Done,
      // Label 2970: @190923
      GIM_Try, /*On fail goto*//*Label 2971*/ GIMT_Encode4(190986), // Rule ID 3211 //
        GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasFlatGlobalInsts),
        GIM_CheckMemoryAddressSpace, /*MI*/0, /*MMO*/0, /*NumAddrSpace*/3, /*AddrSpace*/1, /*AddrSpace*/4, /*AddrSpace*/6,
        GIM_CheckHasNoUse, /*MI*/0,
        GIM_CheckPointerToAny, /*MI*/0, /*Op*/1, /*SizeInBits*/0,
        GIM_CheckComplexPattern, /*MI*/0, /*Op*/1, /*Renderer*/GIMT_Encode2(0), GIMT_Encode2(GICP_gi_global_saddr),
        // (atomic_load_uinc_wrap:{ *:[i64] } (GlobalSAddr:{ *:[iPTR] } SReg_64:{ *:[i64] }:$saddr, VGPR_32:{ *:[i32] }:$voffset, i32:{ *:[i32] }:$offset), i64:{ *:[i64] }:$data)<<P:Predicate_atomic_load_uinc_wrap_global_noret_64>>  =>  (GLOBAL_ATOMIC_INC_X2_SADDR ?:{ *:[i32] }:$voffset, anonymous_15036:{ *:[i64] }:$data, ?:{ *:[i64] }:$saddr, ?:{ *:[i32] }:$offset)
        GIR_BuildMI, /*InsnID*/0, /*Opcode*/GIMT_Encode2(AMDGPU::GLOBAL_ATOMIC_INC_X2_SADDR),
        GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/1, // voffset
        GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/2, // data
        GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/0, // saddr
        GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/2, // offset
        GIR_AddImm8, /*InsnID*/0, /*Imm*/0,
        GIR_MergeMemOperands, /*InsnID*/0, /*NumInsns*/1, /*MergeInsnID's*/0,
        GIR_ConstrainSelectedInstOperands, /*InsnID*/0,
        GIR_EraseFromParent, /*InsnID*/0,
        // GIR_Coverage, 3211,
        GIR_Done,
      // Label 2971: @190986
      GIM_Try, /*On fail goto*//*Label 2972*/ GIMT_Encode4(191056), // Rule ID 3213 //
        GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasFlatGlobalInsts),
        GIM_CheckMemoryAddressSpace, /*MI*/0, /*MMO*/0, /*NumAddrSpace*/3, /*AddrSpace*/1, /*AddrSpace*/4, /*AddrSpace*/6,
        GIM_CheckRegBankForClass, /*MI*/0, /*Op*/0, /*RC*/GIMT_Encode2(AMDGPU::AV_64RegClassID),
        GIM_CheckPointerToAny, /*MI*/0, /*Op*/1, /*SizeInBits*/0,
        GIM_CheckComplexPattern, /*MI*/0, /*Op*/1, /*Renderer*/GIMT_Encode2(0), GIMT_Encode2(GICP_gi_global_saddr),
        // (atomic_load_uinc_wrap:{ *:[i64] } (GlobalSAddr:{ *:[iPTR] } SReg_64:{ *:[i64] }:$saddr, VGPR_32:{ *:[i32] }:$voffset, i32:{ *:[i32] }:$offset), i64:{ *:[i64] }:$data)<<P:Predicate_atomic_load_uinc_wrap_global_64>>  =>  (GLOBAL_ATOMIC_INC_X2_SADDR_RTN:{ *:[i64] } ?:{ *:[i32] }:$voffset, anonymous_15036:{ *:[i64] }:$data, ?:{ *:[i64] }:$saddr, ?:{ *:[i32] }:$offset)
        GIR_BuildMI, /*InsnID*/0, /*Opcode*/GIMT_Encode2(AMDGPU::GLOBAL_ATOMIC_INC_X2_SADDR_RTN),
        GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/0, // DstI[vdst]
        GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/1, // voffset
        GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/2, // data
        GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/0, // saddr
        GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/2, // offset
        GIR_AddImm8, /*InsnID*/0, /*Imm*/1,
        GIR_MergeMemOperands, /*InsnID*/0, /*NumInsns*/1, /*MergeInsnID's*/0,
        GIR_ConstrainSelectedInstOperands, /*InsnID*/0,
        GIR_EraseFromParent, /*InsnID*/0,
        // GIR_Coverage, 3213,
        GIR_Done,
      // Label 2972: @191056
      GIM_Try, /*On fail goto*//*Label 2973*/ GIMT_Encode4(191114), // Rule ID 3210 //
        GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasFlatGlobalInsts),
        GIM_CheckMemoryAddressSpace, /*MI*/0, /*MMO*/0, /*NumAddrSpace*/3, /*AddrSpace*/1, /*AddrSpace*/4, /*AddrSpace*/6,
        GIM_CheckHasNoUse, /*MI*/0,
        GIM_CheckPointerToAny, /*MI*/0, /*Op*/1, /*SizeInBits*/0,
        GIM_CheckComplexPattern, /*MI*/0, /*Op*/1, /*Renderer*/GIMT_Encode2(0), GIMT_Encode2(GICP_gi_global_offset),
        // (atomic_load_uinc_wrap:{ *:[i64] } (GlobalOffset:{ *:[iPTR] } i64:{ *:[i64] }:$vaddr, i32:{ *:[i32] }:$offset), i64:{ *:[i64] }:$data)<<P:Predicate_atomic_load_uinc_wrap_global_noret_64>>  =>  (GLOBAL_ATOMIC_INC_X2 VReg_64:{ *:[i64] }:$vaddr, anonymous_15036:{ *:[i64] }:$data, ?:{ *:[i32] }:$offset)
        GIR_BuildMI, /*InsnID*/0, /*Opcode*/GIMT_Encode2(AMDGPU::GLOBAL_ATOMIC_INC_X2),
        GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/0, // vaddr
        GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/2, // data
        GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/1, // offset
        GIR_AddImm8, /*InsnID*/0, /*Imm*/0,
        GIR_MergeMemOperands, /*InsnID*/0, /*NumInsns*/1, /*MergeInsnID's*/0,
        GIR_ConstrainSelectedInstOperands, /*InsnID*/0,
        GIR_EraseFromParent, /*InsnID*/0,
        // GIR_Coverage, 3210,
        GIR_Done,
      // Label 2973: @191114
      GIM_Try, /*On fail goto*//*Label 2974*/ GIMT_Encode4(191179), // Rule ID 3212 //
        GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasFlatGlobalInsts),
        GIM_CheckMemoryAddressSpace, /*MI*/0, /*MMO*/0, /*NumAddrSpace*/3, /*AddrSpace*/1, /*AddrSpace*/4, /*AddrSpace*/6,
        GIM_CheckRegBankForClass, /*MI*/0, /*Op*/0, /*RC*/GIMT_Encode2(AMDGPU::AV_64RegClassID),
        GIM_CheckPointerToAny, /*MI*/0, /*Op*/1, /*SizeInBits*/0,
        GIM_CheckComplexPattern, /*MI*/0, /*Op*/1, /*Renderer*/GIMT_Encode2(0), GIMT_Encode2(GICP_gi_global_offset),
        // (atomic_load_uinc_wrap:{ *:[i64] } (GlobalOffset:{ *:[iPTR] } i64:{ *:[i64] }:$vaddr, i32:{ *:[i32] }:$offset), i64:{ *:[i64] }:$data)<<P:Predicate_atomic_load_uinc_wrap_global_64>>  =>  (GLOBAL_ATOMIC_INC_X2_RTN:{ *:[i64] } VReg_64:{ *:[i64] }:$vaddr, anonymous_15036:{ *:[i64] }:$data, ?:{ *:[i32] }:$offset)
        GIR_BuildMI, /*InsnID*/0, /*Opcode*/GIMT_Encode2(AMDGPU::GLOBAL_ATOMIC_INC_X2_RTN),
        GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/0, // DstI[vdst]
        GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/0, // vaddr
        GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/2, // data
        GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/1, // offset
        GIR_AddImm8, /*InsnID*/0, /*Imm*/1,
        GIR_MergeMemOperands, /*InsnID*/0, /*NumInsns*/1, /*MergeInsnID's*/0,
        GIR_ConstrainSelectedInstOperands, /*InsnID*/0,
        GIR_EraseFromParent, /*InsnID*/0,
        // GIR_Coverage, 3212,
        GIR_Done,
      // Label 2974: @191179
      GIM_Try, /*On fail goto*//*Label 2975*/ GIMT_Encode4(191238), // Rule ID 2858 //
        GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasFlatAddressSpace),
        GIM_CheckMemoryAddressSpace, /*MI*/0, /*MMO*/0, /*NumAddrSpace*/4, /*AddrSpace*/0, /*AddrSpace*/1, /*AddrSpace*/4, /*AddrSpace*/6,
        GIM_CheckHasNoUse, /*MI*/0,
        GIM_CheckPointerToAny, /*MI*/0, /*Op*/1, /*SizeInBits*/0,
        GIM_CheckComplexPattern, /*MI*/0, /*Op*/1, /*Renderer*/GIMT_Encode2(0), GIMT_Encode2(GICP_gi_flat_offset),
        // (atomic_load_uinc_wrap:{ *:[i64] } (FlatOffset:{ *:[iPTR] } i64:{ *:[i64] }:$vaddr, i32:{ *:[i32] }:$offset), i64:{ *:[i64] }:$data)<<P:Predicate_atomic_load_uinc_wrap_flat_noret_64>>  =>  (FLAT_ATOMIC_INC_X2 VReg_64:{ *:[i64] }:$vaddr, anonymous_15036:{ *:[i64] }:$data, ?:{ *:[i32] }:$offset)
        GIR_BuildMI, /*InsnID*/0, /*Opcode*/GIMT_Encode2(AMDGPU::FLAT_ATOMIC_INC_X2),
        GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/0, // vaddr
        GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/2, // data
        GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/1, // offset
        GIR_AddImm8, /*InsnID*/0, /*Imm*/0,
        GIR_MergeMemOperands, /*InsnID*/0, /*NumInsns*/1, /*MergeInsnID's*/0,
        GIR_ConstrainSelectedInstOperands, /*InsnID*/0,
        GIR_EraseFromParent, /*InsnID*/0,
        // GIR_Coverage, 2858,
        GIR_Done,
      // Label 2975: @191238
      GIM_Try, /*On fail goto*//*Label 2976*/ GIMT_Encode4(191296), // Rule ID 2910 //
        GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasFlatAddressSpace),
        GIM_CheckMemoryAddressSpace, /*MI*/0, /*MMO*/0, /*NumAddrSpace*/3, /*AddrSpace*/1, /*AddrSpace*/4, /*AddrSpace*/6,
        GIM_CheckHasNoUse, /*MI*/0,
        GIM_CheckPointerToAny, /*MI*/0, /*Op*/1, /*SizeInBits*/0,
        GIM_CheckComplexPattern, /*MI*/0, /*Op*/1, /*Renderer*/GIMT_Encode2(0), GIMT_Encode2(GICP_gi_flat_offset),
        // (atomic_load_uinc_wrap:{ *:[i64] } (FlatOffset:{ *:[iPTR] } i64:{ *:[i64] }:$vaddr, i32:{ *:[i32] }:$offset), i64:{ *:[i64] }:$data)<<P:Predicate_atomic_load_uinc_wrap_global_noret_64>>  =>  (FLAT_ATOMIC_INC_X2 VReg_64:{ *:[i64] }:$vaddr, anonymous_15036:{ *:[i64] }:$data, ?:{ *:[i32] }:$offset)
        GIR_BuildMI, /*InsnID*/0, /*Opcode*/GIMT_Encode2(AMDGPU::FLAT_ATOMIC_INC_X2),
        GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/0, // vaddr
        GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/2, // data
        GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/1, // offset
        GIR_AddImm8, /*InsnID*/0, /*Imm*/0,
        GIR_MergeMemOperands, /*InsnID*/0, /*NumInsns*/1, /*MergeInsnID's*/0,
        GIR_ConstrainSelectedInstOperands, /*InsnID*/0,
        GIR_EraseFromParent, /*InsnID*/0,
        // GIR_Coverage, 2910,
        GIR_Done,
      // Label 2976: @191296
      GIM_Try, /*On fail goto*//*Label 2977*/ GIMT_Encode4(191362), // Rule ID 2857 //
        GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasFlatAddressSpace),
        GIM_CheckMemoryAddressSpace, /*MI*/0, /*MMO*/0, /*NumAddrSpace*/4, /*AddrSpace*/0, /*AddrSpace*/1, /*AddrSpace*/4, /*AddrSpace*/6,
        GIM_CheckRegBankForClass, /*MI*/0, /*Op*/0, /*RC*/GIMT_Encode2(AMDGPU::AV_64RegClassID),
        GIM_CheckPointerToAny, /*MI*/0, /*Op*/1, /*SizeInBits*/0,
        GIM_CheckComplexPattern, /*MI*/0, /*Op*/1, /*Renderer*/GIMT_Encode2(0), GIMT_Encode2(GICP_gi_flat_offset),
        // (atomic_load_uinc_wrap:{ *:[i64] } (FlatOffset:{ *:[iPTR] } i64:{ *:[i64] }:$vaddr, i32:{ *:[i32] }:$offset), i64:{ *:[i64] }:$data)<<P:Predicate_atomic_load_uinc_wrap_flat_64>>  =>  (FLAT_ATOMIC_INC_X2_RTN:{ *:[i64] } VReg_64:{ *:[i64] }:$vaddr, anonymous_15036:{ *:[i64] }:$data, ?:{ *:[i32] }:$offset)
        GIR_BuildMI, /*InsnID*/0, /*Opcode*/GIMT_Encode2(AMDGPU::FLAT_ATOMIC_INC_X2_RTN),
        GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/0, // DstI[vdst]
        GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/0, // vaddr
        GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/2, // data
        GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/1, // offset
        GIR_AddImm8, /*InsnID*/0, /*Imm*/1,
        GIR_MergeMemOperands, /*InsnID*/0, /*NumInsns*/1, /*MergeInsnID's*/0,
        GIR_ConstrainSelectedInstOperands, /*InsnID*/0,
        GIR_EraseFromParent, /*InsnID*/0,
        // GIR_Coverage, 2857,
        GIR_Done,
      // Label 2977: @191362
      GIM_Try, /*On fail goto*//*Label 2978*/ GIMT_Encode4(191427), // Rule ID 2909 //
        GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasFlatAddressSpace),
        GIM_CheckMemoryAddressSpace, /*MI*/0, /*MMO*/0, /*NumAddrSpace*/3, /*AddrSpace*/1, /*AddrSpace*/4, /*AddrSpace*/6,
        GIM_CheckRegBankForClass, /*MI*/0, /*Op*/0, /*RC*/GIMT_Encode2(AMDGPU::AV_64RegClassID),
        GIM_CheckPointerToAny, /*MI*/0, /*Op*/1, /*SizeInBits*/0,
        GIM_CheckComplexPattern, /*MI*/0, /*Op*/1, /*Renderer*/GIMT_Encode2(0), GIMT_Encode2(GICP_gi_flat_offset),
        // (atomic_load_uinc_wrap:{ *:[i64] } (FlatOffset:{ *:[iPTR] } i64:{ *:[i64] }:$vaddr, i32:{ *:[i32] }:$offset), i64:{ *:[i64] }:$data)<<P:Predicate_atomic_load_uinc_wrap_global_64>>  =>  (FLAT_ATOMIC_INC_X2_RTN:{ *:[i64] } VReg_64:{ *:[i64] }:$vaddr, anonymous_15036:{ *:[i64] }:$data, ?:{ *:[i32] }:$offset)
        GIR_BuildMI, /*InsnID*/0, /*Opcode*/GIMT_Encode2(AMDGPU::FLAT_ATOMIC_INC_X2_RTN),
        GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/0, // DstI[vdst]
        GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/0, // vaddr
        GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/2, // data
        GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/1, // offset
        GIR_AddImm8, /*InsnID*/0, /*Imm*/1,
        GIR_MergeMemOperands, /*InsnID*/0, /*NumInsns*/1, /*MergeInsnID's*/0,
        GIR_ConstrainSelectedInstOperands, /*InsnID*/0,
        GIR_EraseFromParent, /*InsnID*/0,
        // GIR_Coverage, 2909,
        GIR_Done,
      // Label 2978: @191427
      GIM_Reject,
    // Label 2956: @191428
    GIM_Reject,
    // Label 2932: @191429
    GIM_Reject,
    // Label 29: @191430
    GIM_SwitchType, /*MI*/0, /*Op*/0, /*[*/GIMT_Encode2(9), GIMT_Encode2(11), /*)*//*default:*//*Label 2981*/ GIMT_Encode4(194273),
    /*GILLT_s32*//*Label 2979*/ GIMT_Encode4(191449),
    /*GILLT_s64*//*Label 2980*/ GIMT_Encode4(192861),
    // Label 2979: @191449
    GIM_Try, /*On fail goto*//*Label 2982*/ GIMT_Encode4(192860),
      GIM_CheckType, /*MI*/0, /*Op*/2, /*Type*/GILLT_s32,
      GIM_Try, /*On fail goto*//*Label 2983*/ GIMT_Encode4(191526), // Rule ID 4598 //
        GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasUnrestrictedSOffset),
        GIM_CheckMemoryAddressSpace, /*MI*/0, /*MMO*/0, /*NumAddrSpace*/3, /*AddrSpace*/1, /*AddrSpace*/4, /*AddrSpace*/6,
        GIM_CheckHasNoUse, /*MI*/0,
        GIM_CheckPointerToAny, /*MI*/0, /*Op*/1, /*SizeInBits*/0,
        GIM_CheckComplexPattern, /*MI*/0, /*Op*/1, /*Renderer*/GIMT_Encode2(0), GIMT_Encode2(GICP_gi_mubuf_addr64),
        // (atomic_load_udec_wrap:{ *:[i32] } (MUBUFAddr64:{ *:[iPTR] } v4i32:{ *:[v4i32] }:$srsrc, i64:{ *:[i64] }:$vaddr, i32:{ *:[i32] }:$soffset, i32:{ *:[i32] }:$offset), i32:{ *:[i32] }:$vdata_in)<<P:Predicate_atomic_load_udec_wrap_global_noret_32>>  =>  (BUFFER_ATOMIC_DEC_ADDR64 anonymous_15037:{ *:[i32] }:$vdata_in, VReg_64:{ *:[i64] }:$vaddr, SReg_128:{ *:[v4i32] }:$srsrc, SCSrc_b32:{ *:[i32] }:$soffset, offset:{ *:[i32] }:$offset)
        GIR_BuildMI, /*InsnID*/0, /*Opcode*/GIMT_Encode2(AMDGPU::BUFFER_ATOMIC_DEC_ADDR64),
        GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/2, // vdata_in
        GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/1, // vaddr
        GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/0, // srsrc
        GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/2, // soffset
        GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/3, // offset
        GIR_AddImm8, /*InsnID*/0, /*Imm*/0,
        GIR_MergeMemOperands, /*InsnID*/0, /*NumInsns*/1, /*MergeInsnID's*/0,
        GIR_ConstrainSelectedInstOperands, /*InsnID*/0,
        GIR_EraseFromParent, /*InsnID*/0,
        // GIR_Coverage, 4598,
        GIR_Done,
      // Label 2983: @191526
      GIM_Try, /*On fail goto*//*Label 2984*/ GIMT_Encode4(191591), // Rule ID 4602 //
        GIM_CheckMemoryAddressSpace, /*MI*/0, /*MMO*/0, /*NumAddrSpace*/3, /*AddrSpace*/1, /*AddrSpace*/4, /*AddrSpace*/6,
        GIM_CheckHasNoUse, /*MI*/0,
        GIM_CheckPointerToAny, /*MI*/0, /*Op*/1, /*SizeInBits*/0,
        GIM_CheckComplexPattern, /*MI*/0, /*Op*/1, /*Renderer*/GIMT_Encode2(0), GIMT_Encode2(GICP_gi_mubuf_addr64),
        // (atomic_load_udec_wrap:{ *:[i32] } (MUBUFAddr64:{ *:[iPTR] } v4i32:{ *:[v4i32] }:$srsrc, i64:{ *:[i64] }:$vaddr, i32:{ *:[i32] }:$soffset, i32:{ *:[i32] }:$offset), i32:{ *:[i32] }:$vdata_in)<<P:Predicate_atomic_load_udec_wrap_global_noret_32>>  =>  (BUFFER_ATOMIC_DEC_VBUFFER_ADDR64 anonymous_15037:{ *:[i32] }:$vdata_in, VReg_64:{ *:[i64] }:$vaddr, SReg_128:{ *:[v4i32] }:$srsrc, SCSrc_b32:{ *:[i32] }:$soffset, offset:{ *:[i32] }:$offset)
        GIR_BuildMI, /*InsnID*/0, /*Opcode*/GIMT_Encode2(AMDGPU::BUFFER_ATOMIC_DEC_VBUFFER_ADDR64),
        GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/2, // vdata_in
        GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/1, // vaddr
        GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/0, // srsrc
        GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/2, // soffset
        GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/3, // offset
        GIR_AddImm8, /*InsnID*/0, /*Imm*/0,
        GIR_MergeMemOperands, /*InsnID*/0, /*NumInsns*/1, /*MergeInsnID's*/0,
        GIR_ConstrainSelectedInstOperands, /*InsnID*/0,
        GIR_EraseFromParent, /*InsnID*/0,
        // GIR_Coverage, 4602,
        GIR_Done,
      // Label 2984: @191591
      GIM_Try, /*On fail goto*//*Label 2985*/ GIMT_Encode4(191666), // Rule ID 4596 //
        GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasUnrestrictedSOffset),
        GIM_CheckMemoryAddressSpace, /*MI*/0, /*MMO*/0, /*NumAddrSpace*/3, /*AddrSpace*/1, /*AddrSpace*/4, /*AddrSpace*/6,
        GIM_CheckRegBankForClass, /*MI*/0, /*Op*/0, /*RC*/GIMT_Encode2(AMDGPU::AV_32RegClassID),
        GIM_CheckPointerToAny, /*MI*/0, /*Op*/1, /*SizeInBits*/0,
        GIM_CheckComplexPattern, /*MI*/0, /*Op*/1, /*Renderer*/GIMT_Encode2(0), GIMT_Encode2(GICP_gi_mubuf_addr64),
        // (atomic_load_udec_wrap:{ *:[i32] } (MUBUFAddr64:{ *:[iPTR] } v4i32:{ *:[v4i32] }:$srsrc, i64:{ *:[i64] }:$vaddr, i32:{ *:[i32] }:$soffset, i32:{ *:[i32] }:$offset), i32:{ *:[i32] }:$vdata_in)<<P:Predicate_atomic_load_udec_wrap_global_32>>  =>  (BUFFER_ATOMIC_DEC_ADDR64_RTN:{ *:[i32] } anonymous_15037:{ *:[i32] }:$vdata_in, VReg_64:{ *:[i64] }:$vaddr, SReg_128:{ *:[v4i32] }:$srsrc, SCSrc_b32:{ *:[i32] }:$soffset, offset:{ *:[i32] }:$offset)
        GIR_BuildMI, /*InsnID*/0, /*Opcode*/GIMT_Encode2(AMDGPU::BUFFER_ATOMIC_DEC_ADDR64_RTN),
        GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/0, // DstI[vdata]
        GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/2, // vdata_in
        GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/1, // vaddr
        GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/0, // srsrc
        GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/2, // soffset
        GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/3, // offset
        GIR_AddImm8, /*InsnID*/0, /*Imm*/1,
        GIR_MergeMemOperands, /*InsnID*/0, /*NumInsns*/1, /*MergeInsnID's*/0,
        GIR_ConstrainSelectedInstOperands, /*InsnID*/0,
        GIR_EraseFromParent, /*InsnID*/0,
        // GIR_Coverage, 4596,
        GIR_Done,
      // Label 2985: @191666
      GIM_Try, /*On fail goto*//*Label 2986*/ GIMT_Encode4(191738), // Rule ID 4600 //
        GIM_CheckMemoryAddressSpace, /*MI*/0, /*MMO*/0, /*NumAddrSpace*/3, /*AddrSpace*/1, /*AddrSpace*/4, /*AddrSpace*/6,
        GIM_CheckRegBankForClass, /*MI*/0, /*Op*/0, /*RC*/GIMT_Encode2(AMDGPU::AV_32RegClassID),
        GIM_CheckPointerToAny, /*MI*/0, /*Op*/1, /*SizeInBits*/0,
        GIM_CheckComplexPattern, /*MI*/0, /*Op*/1, /*Renderer*/GIMT_Encode2(0), GIMT_Encode2(GICP_gi_mubuf_addr64),
        // (atomic_load_udec_wrap:{ *:[i32] } (MUBUFAddr64:{ *:[iPTR] } v4i32:{ *:[v4i32] }:$srsrc, i64:{ *:[i64] }:$vaddr, i32:{ *:[i32] }:$soffset, i32:{ *:[i32] }:$offset), i32:{ *:[i32] }:$vdata_in)<<P:Predicate_atomic_load_udec_wrap_global_32>>  =>  (BUFFER_ATOMIC_DEC_VBUFFER_ADDR64_RTN:{ *:[i32] } anonymous_15037:{ *:[i32] }:$vdata_in, VReg_64:{ *:[i64] }:$vaddr, SReg_128:{ *:[v4i32] }:$srsrc, SCSrc_b32:{ *:[i32] }:$soffset, offset:{ *:[i32] }:$offset)
        GIR_BuildMI, /*InsnID*/0, /*Opcode*/GIMT_Encode2(AMDGPU::BUFFER_ATOMIC_DEC_VBUFFER_ADDR64_RTN),
        GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/0, // DstI[vdata]
        GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/2, // vdata_in
        GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/1, // vaddr
        GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/0, // srsrc
        GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/2, // soffset
        GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/3, // offset
        GIR_AddImm8, /*InsnID*/0, /*Imm*/1,
        GIR_MergeMemOperands, /*InsnID*/0, /*NumInsns*/1, /*MergeInsnID's*/0,
        GIR_ConstrainSelectedInstOperands, /*InsnID*/0,
        GIR_EraseFromParent, /*InsnID*/0,
        // GIR_Coverage, 4600,
        GIR_Done,
      // Label 2986: @191738
      GIM_Try, /*On fail goto*//*Label 2987*/ GIMT_Encode4(191801), // Rule ID 4597 //
        GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasUnrestrictedSOffset),
        GIM_CheckMemoryAddressSpace, /*MI*/0, /*MMO*/0, /*NumAddrSpace*/3, /*AddrSpace*/1, /*AddrSpace*/4, /*AddrSpace*/6,
        GIM_CheckHasNoUse, /*MI*/0,
        GIM_CheckPointerToAny, /*MI*/0, /*Op*/1, /*SizeInBits*/0,
        GIM_CheckComplexPattern, /*MI*/0, /*Op*/1, /*Renderer*/GIMT_Encode2(0), GIMT_Encode2(GICP_gi_mubuf_offset),
        // (atomic_load_udec_wrap:{ *:[i32] } (MUBUFOffset:{ *:[iPTR] } v4i32:{ *:[v4i32] }:$srsrc, i32:{ *:[i32] }:$soffset, i32:{ *:[i32] }:$offset), i32:{ *:[i32] }:$vdata_in)<<P:Predicate_atomic_load_udec_wrap_global_noret_32>>  =>  (BUFFER_ATOMIC_DEC_OFFSET anonymous_15037:{ *:[i32] }:$vdata_in, SReg_128:{ *:[v4i32] }:$srsrc, SCSrc_b32:{ *:[i32] }:$soffset, offset:{ *:[i32] }:$offset)
        GIR_BuildMI, /*InsnID*/0, /*Opcode*/GIMT_Encode2(AMDGPU::BUFFER_ATOMIC_DEC_OFFSET),
        GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/2, // vdata_in
        GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/0, // srsrc
        GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/1, // soffset
        GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/2, // offset
        GIR_AddImm8, /*InsnID*/0, /*Imm*/0,
        GIR_MergeMemOperands, /*InsnID*/0, /*NumInsns*/1, /*MergeInsnID's*/0,
        GIR_ConstrainSelectedInstOperands, /*InsnID*/0,
        GIR_EraseFromParent, /*InsnID*/0,
        // GIR_Coverage, 4597,
        GIR_Done,
      // Label 2987: @191801
      GIM_Try, /*On fail goto*//*Label 2988*/ GIMT_Encode4(191861), // Rule ID 4601 //
        GIM_CheckMemoryAddressSpace, /*MI*/0, /*MMO*/0, /*NumAddrSpace*/3, /*AddrSpace*/1, /*AddrSpace*/4, /*AddrSpace*/6,
        GIM_CheckHasNoUse, /*MI*/0,
        GIM_CheckPointerToAny, /*MI*/0, /*Op*/1, /*SizeInBits*/0,
        GIM_CheckComplexPattern, /*MI*/0, /*Op*/1, /*Renderer*/GIMT_Encode2(0), GIMT_Encode2(GICP_gi_mubuf_offset),
        // (atomic_load_udec_wrap:{ *:[i32] } (MUBUFOffset:{ *:[iPTR] } v4i32:{ *:[v4i32] }:$srsrc, i32:{ *:[i32] }:$soffset, i32:{ *:[i32] }:$offset), i32:{ *:[i32] }:$vdata_in)<<P:Predicate_atomic_load_udec_wrap_global_noret_32>>  =>  (BUFFER_ATOMIC_DEC_VBUFFER_OFFSET anonymous_15037:{ *:[i32] }:$vdata_in, SReg_128:{ *:[v4i32] }:$srsrc, SCSrc_b32:{ *:[i32] }:$soffset, offset:{ *:[i32] }:$offset)
        GIR_BuildMI, /*InsnID*/0, /*Opcode*/GIMT_Encode2(AMDGPU::BUFFER_ATOMIC_DEC_VBUFFER_OFFSET),
        GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/2, // vdata_in
        GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/0, // srsrc
        GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/1, // soffset
        GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/2, // offset
        GIR_AddImm8, /*InsnID*/0, /*Imm*/0,
        GIR_MergeMemOperands, /*InsnID*/0, /*NumInsns*/1, /*MergeInsnID's*/0,
        GIR_ConstrainSelectedInstOperands, /*InsnID*/0,
        GIR_EraseFromParent, /*InsnID*/0,
        // GIR_Coverage, 4601,
        GIR_Done,
      // Label 2988: @191861
      GIM_Try, /*On fail goto*//*Label 2989*/ GIMT_Encode4(191931), // Rule ID 4595 //
        GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasUnrestrictedSOffset),
        GIM_CheckMemoryAddressSpace, /*MI*/0, /*MMO*/0, /*NumAddrSpace*/3, /*AddrSpace*/1, /*AddrSpace*/4, /*AddrSpace*/6,
        GIM_CheckRegBankForClass, /*MI*/0, /*Op*/0, /*RC*/GIMT_Encode2(AMDGPU::AV_32RegClassID),
        GIM_CheckPointerToAny, /*MI*/0, /*Op*/1, /*SizeInBits*/0,
        GIM_CheckComplexPattern, /*MI*/0, /*Op*/1, /*Renderer*/GIMT_Encode2(0), GIMT_Encode2(GICP_gi_mubuf_offset),
        // (atomic_load_udec_wrap:{ *:[i32] } (MUBUFOffset:{ *:[iPTR] } v4i32:{ *:[v4i32] }:$srsrc, i32:{ *:[i32] }:$soffset, i32:{ *:[i32] }:$offset), i32:{ *:[i32] }:$vdata_in)<<P:Predicate_atomic_load_udec_wrap_global_32>>  =>  (BUFFER_ATOMIC_DEC_OFFSET_RTN:{ *:[i32] } anonymous_15037:{ *:[i32] }:$vdata_in, SReg_128:{ *:[v4i32] }:$srsrc, SCSrc_b32:{ *:[i32] }:$soffset, offset:{ *:[i32] }:$offset)
        GIR_BuildMI, /*InsnID*/0, /*Opcode*/GIMT_Encode2(AMDGPU::BUFFER_ATOMIC_DEC_OFFSET_RTN),
        GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/0, // DstI[vdata]
        GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/2, // vdata_in
        GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/0, // srsrc
        GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/1, // soffset
        GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/2, // offset
        GIR_AddImm8, /*InsnID*/0, /*Imm*/1,
        GIR_MergeMemOperands, /*InsnID*/0, /*NumInsns*/1, /*MergeInsnID's*/0,
        GIR_ConstrainSelectedInstOperands, /*InsnID*/0,
        GIR_EraseFromParent, /*InsnID*/0,
        // GIR_Coverage, 4595,
        GIR_Done,
      // Label 2989: @191931
      GIM_Try, /*On fail goto*//*Label 2990*/ GIMT_Encode4(191998), // Rule ID 4599 //
        GIM_CheckMemoryAddressSpace, /*MI*/0, /*MMO*/0, /*NumAddrSpace*/3, /*AddrSpace*/1, /*AddrSpace*/4, /*AddrSpace*/6,
        GIM_CheckRegBankForClass, /*MI*/0, /*Op*/0, /*RC*/GIMT_Encode2(AMDGPU::AV_32RegClassID),
        GIM_CheckPointerToAny, /*MI*/0, /*Op*/1, /*SizeInBits*/0,
        GIM_CheckComplexPattern, /*MI*/0, /*Op*/1, /*Renderer*/GIMT_Encode2(0), GIMT_Encode2(GICP_gi_mubuf_offset),
        // (atomic_load_udec_wrap:{ *:[i32] } (MUBUFOffset:{ *:[iPTR] } v4i32:{ *:[v4i32] }:$srsrc, i32:{ *:[i32] }:$soffset, i32:{ *:[i32] }:$offset), i32:{ *:[i32] }:$vdata_in)<<P:Predicate_atomic_load_udec_wrap_global_32>>  =>  (BUFFER_ATOMIC_DEC_VBUFFER_OFFSET_RTN:{ *:[i32] } anonymous_15037:{ *:[i32] }:$vdata_in, SReg_128:{ *:[v4i32] }:$srsrc, SCSrc_b32:{ *:[i32] }:$soffset, offset:{ *:[i32] }:$offset)
        GIR_BuildMI, /*InsnID*/0, /*Opcode*/GIMT_Encode2(AMDGPU::BUFFER_ATOMIC_DEC_VBUFFER_OFFSET_RTN),
        GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/0, // DstI[vdata]
        GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/2, // vdata_in
        GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/0, // srsrc
        GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/1, // soffset
        GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/2, // offset
        GIR_AddImm8, /*InsnID*/0, /*Imm*/1,
        GIR_MergeMemOperands, /*InsnID*/0, /*NumInsns*/1, /*MergeInsnID's*/0,
        GIR_ConstrainSelectedInstOperands, /*InsnID*/0,
        GIR_EraseFromParent, /*InsnID*/0,
        // GIR_Coverage, 4599,
        GIR_Done,
      // Label 2990: @191998
      GIM_Try, /*On fail goto*//*Label 2991*/ GIMT_Encode4(192054), // Rule ID 6923 //
        GIM_CheckFeatures, GIMT_Encode2(GIFBS_LDSRequiresM0Init),
        GIM_CheckMemoryAddressSpace, /*MI*/0, /*MMO*/0, /*NumAddrSpace*/1, /*AddrSpace*/3,
        GIM_CheckHasNoUse, /*MI*/0,
        GIM_CheckPointerToAny, /*MI*/0, /*Op*/1, /*SizeInBits*/0,
        GIM_CheckComplexPattern, /*MI*/0, /*Op*/1, /*Renderer*/GIMT_Encode2(0), GIMT_Encode2(GICP_gi_ds_1addr_1offset),
        // (atomic_load_udec_wrap_glue:{ *:[i32] } (DS1Addr1Offset:{ *:[iPTR] } i32:{ *:[i32] }:$ptr, i32:{ *:[i32] }:$offset), i32:{ *:[i32] }:$value)<<P:Predicate_atomic_load_udec_wrap_local_m0_noret_32>>  =>  (DS_DEC_U32 ?:{ *:[i32] }:$ptr, anonymous_15037:{ *:[i32] }:$value, offset:{ *:[i32] }:$offset, 0:{ *:[i1] })
        GIR_BuildMI, /*InsnID*/0, /*Opcode*/GIMT_Encode2(AMDGPU::DS_DEC_U32),
        GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/0, // ptr
        GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/2, // value
        GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/1, // offset
        GIR_AddImm8, /*InsnID*/0, /*Imm*/0,
        GIR_MergeMemOperands, /*InsnID*/0, /*NumInsns*/1, /*MergeInsnID's*/0,
        GIR_ConstrainSelectedInstOperands, /*InsnID*/0,
        GIR_EraseFromParent, /*InsnID*/0,
        // GIR_Coverage, 6923,
        GIR_Done,
      // Label 2991: @192054
      GIM_Try, /*On fail goto*//*Label 2992*/ GIMT_Encode4(192110), // Rule ID 6925 //
        GIM_CheckFeatures, GIMT_Encode2(GIFBS_NotLDSRequiresM0Init),
        GIM_CheckMemoryAddressSpace, /*MI*/0, /*MMO*/0, /*NumAddrSpace*/1, /*AddrSpace*/3,
        GIM_CheckHasNoUse, /*MI*/0,
        GIM_CheckPointerToAny, /*MI*/0, /*Op*/1, /*SizeInBits*/0,
        GIM_CheckComplexPattern, /*MI*/0, /*Op*/1, /*Renderer*/GIMT_Encode2(0), GIMT_Encode2(GICP_gi_ds_1addr_1offset),
        // (atomic_load_udec_wrap:{ *:[i32] } (DS1Addr1Offset:{ *:[iPTR] } i32:{ *:[i32] }:$ptr, i32:{ *:[i32] }:$offset), i32:{ *:[i32] }:$value)<<P:Predicate_atomic_load_udec_wrap_local_noret_32>>  =>  (DS_DEC_U32_gfx9 ?:{ *:[i32] }:$ptr, anonymous_15037:{ *:[i32] }:$value, offset:{ *:[i32] }:$offset, 0:{ *:[i1] })
        GIR_BuildMI, /*InsnID*/0, /*Opcode*/GIMT_Encode2(AMDGPU::DS_DEC_U32_gfx9),
        GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/0, // ptr
        GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/2, // value
        GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/1, // offset
        GIR_AddImm8, /*InsnID*/0, /*Imm*/0,
        GIR_MergeMemOperands, /*InsnID*/0, /*NumInsns*/1, /*MergeInsnID's*/0,
        GIR_ConstrainSelectedInstOperands, /*InsnID*/0,
        GIR_EraseFromParent, /*InsnID*/0,
        // GIR_Coverage, 6925,
        GIR_Done,
      // Label 2992: @192110
      GIM_Try, /*On fail goto*//*Label 2993*/ GIMT_Encode4(192166), // Rule ID 6927 //
        GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasGDS),
        GIM_CheckMemoryAddressSpace, /*MI*/0, /*MMO*/0, /*NumAddrSpace*/1, /*AddrSpace*/2,
        GIM_CheckHasNoUse, /*MI*/0,
        GIM_CheckPointerToAny, /*MI*/0, /*Op*/1, /*SizeInBits*/0,
        GIM_CheckComplexPattern, /*MI*/0, /*Op*/1, /*Renderer*/GIMT_Encode2(0), GIMT_Encode2(GICP_gi_ds_1addr_1offset),
        // (atomic_load_udec_wrap_glue:{ *:[i32] } (DS1Addr1Offset:{ *:[iPTR] } i32:{ *:[i32] }:$ptr, i32:{ *:[i32] }:$offset), i32:{ *:[i32] }:$value)<<P:Predicate_atomic_load_udec_wrap_region_m0_noret_32>>  =>  (DS_DEC_U32 ?:{ *:[i32] }:$ptr, anonymous_15037:{ *:[i32] }:$value, offset:{ *:[i32] }:$offset, 1:{ *:[i1] })
        GIR_BuildMI, /*InsnID*/0, /*Opcode*/GIMT_Encode2(AMDGPU::DS_DEC_U32),
        GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/0, // ptr
        GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/2, // value
        GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/1, // offset
        GIR_AddImm8, /*InsnID*/0, /*Imm*/1,
        GIR_MergeMemOperands, /*InsnID*/0, /*NumInsns*/1, /*MergeInsnID's*/0,
        GIR_ConstrainSelectedInstOperands, /*InsnID*/0,
        GIR_EraseFromParent, /*InsnID*/0,
        // GIR_Coverage, 6927,
        GIR_Done,
      // Label 2993: @192166
      GIM_Try, /*On fail goto*//*Label 2994*/ GIMT_Encode4(192229), // Rule ID 6922 //
        GIM_CheckFeatures, GIMT_Encode2(GIFBS_LDSRequiresM0Init),
        GIM_CheckMemoryAddressSpace, /*MI*/0, /*MMO*/0, /*NumAddrSpace*/1, /*AddrSpace*/3,
        GIM_CheckRegBankForClass, /*MI*/0, /*Op*/0, /*RC*/GIMT_Encode2(AMDGPU::AV_32RegClassID),
        GIM_CheckPointerToAny, /*MI*/0, /*Op*/1, /*SizeInBits*/0,
        GIM_CheckComplexPattern, /*MI*/0, /*Op*/1, /*Renderer*/GIMT_Encode2(0), GIMT_Encode2(GICP_gi_ds_1addr_1offset),
        // (atomic_load_udec_wrap_glue:{ *:[i32] } (DS1Addr1Offset:{ *:[iPTR] } i32:{ *:[i32] }:$ptr, i32:{ *:[i32] }:$offset), i32:{ *:[i32] }:$value)<<P:Predicate_atomic_load_udec_wrap_local_m0_32>>  =>  (DS_DEC_RTN_U32:{ *:[i32] } ?:{ *:[i32] }:$ptr, anonymous_15037:{ *:[i32] }:$value, offset:{ *:[i32] }:$offset, 0:{ *:[i1] })
        GIR_BuildMI, /*InsnID*/0, /*Opcode*/GIMT_Encode2(AMDGPU::DS_DEC_RTN_U32),
        GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/0, // DstI[vdst]
        GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/0, // ptr
        GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/2, // value
        GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/1, // offset
        GIR_AddImm8, /*InsnID*/0, /*Imm*/0,
        GIR_MergeMemOperands, /*InsnID*/0, /*NumInsns*/1, /*MergeInsnID's*/0,
        GIR_ConstrainSelectedInstOperands, /*InsnID*/0,
        GIR_EraseFromParent, /*InsnID*/0,
        // GIR_Coverage, 6922,
        GIR_Done,
      // Label 2994: @192229
      GIM_Try, /*On fail goto*//*Label 2995*/ GIMT_Encode4(192292), // Rule ID 6924 //
        GIM_CheckFeatures, GIMT_Encode2(GIFBS_NotLDSRequiresM0Init),
        GIM_CheckMemoryAddressSpace, /*MI*/0, /*MMO*/0, /*NumAddrSpace*/1, /*AddrSpace*/3,
        GIM_CheckRegBankForClass, /*MI*/0, /*Op*/0, /*RC*/GIMT_Encode2(AMDGPU::AV_32RegClassID),
        GIM_CheckPointerToAny, /*MI*/0, /*Op*/1, /*SizeInBits*/0,
        GIM_CheckComplexPattern, /*MI*/0, /*Op*/1, /*Renderer*/GIMT_Encode2(0), GIMT_Encode2(GICP_gi_ds_1addr_1offset),
        // (atomic_load_udec_wrap:{ *:[i32] } (DS1Addr1Offset:{ *:[iPTR] } i32:{ *:[i32] }:$ptr, i32:{ *:[i32] }:$offset), i32:{ *:[i32] }:$value)<<P:Predicate_atomic_load_udec_wrap_local_32>>  =>  (DS_DEC_RTN_U32_gfx9:{ *:[i32] } ?:{ *:[i32] }:$ptr, anonymous_15037:{ *:[i32] }:$value, offset:{ *:[i32] }:$offset, 0:{ *:[i1] })
        GIR_BuildMI, /*InsnID*/0, /*Opcode*/GIMT_Encode2(AMDGPU::DS_DEC_RTN_U32_gfx9),
        GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/0, // DstI[vdst]
        GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/0, // ptr
        GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/2, // value
        GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/1, // offset
        GIR_AddImm8, /*InsnID*/0, /*Imm*/0,
        GIR_MergeMemOperands, /*InsnID*/0, /*NumInsns*/1, /*MergeInsnID's*/0,
        GIR_ConstrainSelectedInstOperands, /*InsnID*/0,
        GIR_EraseFromParent, /*InsnID*/0,
        // GIR_Coverage, 6924,
        GIR_Done,
      // Label 2995: @192292
      GIM_Try, /*On fail goto*//*Label 2996*/ GIMT_Encode4(192355), // Rule ID 6926 //
        GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasGDS),
        GIM_CheckMemoryAddressSpace, /*MI*/0, /*MMO*/0, /*NumAddrSpace*/1, /*AddrSpace*/2,
        GIM_CheckRegBankForClass, /*MI*/0, /*Op*/0, /*RC*/GIMT_Encode2(AMDGPU::AV_32RegClassID),
        GIM_CheckPointerToAny, /*MI*/0, /*Op*/1, /*SizeInBits*/0,
        GIM_CheckComplexPattern, /*MI*/0, /*Op*/1, /*Renderer*/GIMT_Encode2(0), GIMT_Encode2(GICP_gi_ds_1addr_1offset),
        // (atomic_load_udec_wrap_glue:{ *:[i32] } (DS1Addr1Offset:{ *:[iPTR] } i32:{ *:[i32] }:$ptr, i32:{ *:[i32] }:$offset), i32:{ *:[i32] }:$value)<<P:Predicate_atomic_load_udec_wrap_region_m0_32>>  =>  (DS_DEC_RTN_U32:{ *:[i32] } ?:{ *:[i32] }:$ptr, anonymous_15037:{ *:[i32] }:$value, offset:{ *:[i32] }:$offset, 1:{ *:[i1] })
        GIR_BuildMI, /*InsnID*/0, /*Opcode*/GIMT_Encode2(AMDGPU::DS_DEC_RTN_U32),
        GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/0, // DstI[vdst]
        GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/0, // ptr
        GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/2, // value
        GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/1, // offset
        GIR_AddImm8, /*InsnID*/0, /*Imm*/1,
        GIR_MergeMemOperands, /*InsnID*/0, /*NumInsns*/1, /*MergeInsnID's*/0,
        GIR_ConstrainSelectedInstOperands, /*InsnID*/0,
        GIR_EraseFromParent, /*InsnID*/0,
        // GIR_Coverage, 6926,
        GIR_Done,
      // Label 2996: @192355
      GIM_Try, /*On fail goto*//*Label 2997*/ GIMT_Encode4(192418), // Rule ID 3159 //
        GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasFlatGlobalInsts),
        GIM_CheckMemoryAddressSpace, /*MI*/0, /*MMO*/0, /*NumAddrSpace*/3, /*AddrSpace*/1, /*AddrSpace*/4, /*AddrSpace*/6,
        GIM_CheckHasNoUse, /*MI*/0,
        GIM_CheckPointerToAny, /*MI*/0, /*Op*/1, /*SizeInBits*/0,
        GIM_CheckComplexPattern, /*MI*/0, /*Op*/1, /*Renderer*/GIMT_Encode2(0), GIMT_Encode2(GICP_gi_global_saddr),
        // (atomic_load_udec_wrap:{ *:[i32] } (GlobalSAddr:{ *:[iPTR] } SReg_64:{ *:[i64] }:$saddr, VGPR_32:{ *:[i32] }:$voffset, i32:{ *:[i32] }:$offset), i32:{ *:[i32] }:$data)<<P:Predicate_atomic_load_udec_wrap_global_noret_32>>  =>  (GLOBAL_ATOMIC_DEC_SADDR ?:{ *:[i32] }:$voffset, anonymous_15037:{ *:[i32] }:$data, ?:{ *:[i64] }:$saddr, ?:{ *:[i32] }:$offset)
        GIR_BuildMI, /*InsnID*/0, /*Opcode*/GIMT_Encode2(AMDGPU::GLOBAL_ATOMIC_DEC_SADDR),
        GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/1, // voffset
        GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/2, // data
        GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/0, // saddr
        GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/2, // offset
        GIR_AddImm8, /*InsnID*/0, /*Imm*/0,
        GIR_MergeMemOperands, /*InsnID*/0, /*NumInsns*/1, /*MergeInsnID's*/0,
        GIR_ConstrainSelectedInstOperands, /*InsnID*/0,
        GIR_EraseFromParent, /*InsnID*/0,
        // GIR_Coverage, 3159,
        GIR_Done,
      // Label 2997: @192418
      GIM_Try, /*On fail goto*//*Label 2998*/ GIMT_Encode4(192488), // Rule ID 3161 //
        GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasFlatGlobalInsts),
        GIM_CheckMemoryAddressSpace, /*MI*/0, /*MMO*/0, /*NumAddrSpace*/3, /*AddrSpace*/1, /*AddrSpace*/4, /*AddrSpace*/6,
        GIM_CheckRegBankForClass, /*MI*/0, /*Op*/0, /*RC*/GIMT_Encode2(AMDGPU::AV_32RegClassID),
        GIM_CheckPointerToAny, /*MI*/0, /*Op*/1, /*SizeInBits*/0,
        GIM_CheckComplexPattern, /*MI*/0, /*Op*/1, /*Renderer*/GIMT_Encode2(0), GIMT_Encode2(GICP_gi_global_saddr),
        // (atomic_load_udec_wrap:{ *:[i32] } (GlobalSAddr:{ *:[iPTR] } SReg_64:{ *:[i64] }:$saddr, VGPR_32:{ *:[i32] }:$voffset, i32:{ *:[i32] }:$offset), i32:{ *:[i32] }:$data)<<P:Predicate_atomic_load_udec_wrap_global_32>>  =>  (GLOBAL_ATOMIC_DEC_SADDR_RTN:{ *:[i32] } ?:{ *:[i32] }:$voffset, anonymous_15037:{ *:[i32] }:$data, ?:{ *:[i64] }:$saddr, ?:{ *:[i32] }:$offset)
        GIR_BuildMI, /*InsnID*/0, /*Opcode*/GIMT_Encode2(AMDGPU::GLOBAL_ATOMIC_DEC_SADDR_RTN),
        GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/0, // DstI[vdst]
        GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/1, // voffset
        GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/2, // data
        GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/0, // saddr
        GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/2, // offset
        GIR_AddImm8, /*InsnID*/0, /*Imm*/1,
        GIR_MergeMemOperands, /*InsnID*/0, /*NumInsns*/1, /*MergeInsnID's*/0,
        GIR_ConstrainSelectedInstOperands, /*InsnID*/0,
        GIR_EraseFromParent, /*InsnID*/0,
        // GIR_Coverage, 3161,
        GIR_Done,
      // Label 2998: @192488
      GIM_Try, /*On fail goto*//*Label 2999*/ GIMT_Encode4(192546), // Rule ID 3158 //
        GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasFlatGlobalInsts),
        GIM_CheckMemoryAddressSpace, /*MI*/0, /*MMO*/0, /*NumAddrSpace*/3, /*AddrSpace*/1, /*AddrSpace*/4, /*AddrSpace*/6,
        GIM_CheckHasNoUse, /*MI*/0,
        GIM_CheckPointerToAny, /*MI*/0, /*Op*/1, /*SizeInBits*/0,
        GIM_CheckComplexPattern, /*MI*/0, /*Op*/1, /*Renderer*/GIMT_Encode2(0), GIMT_Encode2(GICP_gi_global_offset),
        // (atomic_load_udec_wrap:{ *:[i32] } (GlobalOffset:{ *:[iPTR] } i64:{ *:[i64] }:$vaddr, i32:{ *:[i32] }:$offset), i32:{ *:[i32] }:$data)<<P:Predicate_atomic_load_udec_wrap_global_noret_32>>  =>  (GLOBAL_ATOMIC_DEC VReg_64:{ *:[i64] }:$vaddr, anonymous_15037:{ *:[i32] }:$data, ?:{ *:[i32] }:$offset)
        GIR_BuildMI, /*InsnID*/0, /*Opcode*/GIMT_Encode2(AMDGPU::GLOBAL_ATOMIC_DEC),
        GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/0, // vaddr
        GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/2, // data
        GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/1, // offset
        GIR_AddImm8, /*InsnID*/0, /*Imm*/0,
        GIR_MergeMemOperands, /*InsnID*/0, /*NumInsns*/1, /*MergeInsnID's*/0,
        GIR_ConstrainSelectedInstOperands, /*InsnID*/0,
        GIR_EraseFromParent, /*InsnID*/0,
        // GIR_Coverage, 3158,
        GIR_Done,
      // Label 2999: @192546
      GIM_Try, /*On fail goto*//*Label 3000*/ GIMT_Encode4(192611), // Rule ID 3160 //
        GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasFlatGlobalInsts),
        GIM_CheckMemoryAddressSpace, /*MI*/0, /*MMO*/0, /*NumAddrSpace*/3, /*AddrSpace*/1, /*AddrSpace*/4, /*AddrSpace*/6,
        GIM_CheckRegBankForClass, /*MI*/0, /*Op*/0, /*RC*/GIMT_Encode2(AMDGPU::AV_32RegClassID),
        GIM_CheckPointerToAny, /*MI*/0, /*Op*/1, /*SizeInBits*/0,
        GIM_CheckComplexPattern, /*MI*/0, /*Op*/1, /*Renderer*/GIMT_Encode2(0), GIMT_Encode2(GICP_gi_global_offset),
        // (atomic_load_udec_wrap:{ *:[i32] } (GlobalOffset:{ *:[iPTR] } i64:{ *:[i64] }:$vaddr, i32:{ *:[i32] }:$offset), i32:{ *:[i32] }:$data)<<P:Predicate_atomic_load_udec_wrap_global_32>>  =>  (GLOBAL_ATOMIC_DEC_RTN:{ *:[i32] } VReg_64:{ *:[i64] }:$vaddr, anonymous_15037:{ *:[i32] }:$data, ?:{ *:[i32] }:$offset)
        GIR_BuildMI, /*InsnID*/0, /*Opcode*/GIMT_Encode2(AMDGPU::GLOBAL_ATOMIC_DEC_RTN),
        GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/0, // DstI[vdst]
        GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/0, // vaddr
        GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/2, // data
        GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/1, // offset
        GIR_AddImm8, /*InsnID*/0, /*Imm*/1,
        GIR_MergeMemOperands, /*InsnID*/0, /*NumInsns*/1, /*MergeInsnID's*/0,
        GIR_ConstrainSelectedInstOperands, /*InsnID*/0,
        GIR_EraseFromParent, /*InsnID*/0,
        // GIR_Coverage, 3160,
        GIR_Done,
      // Label 3000: @192611
      GIM_Try, /*On fail goto*//*Label 3001*/ GIMT_Encode4(192670), // Rule ID 2834 //
        GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasFlatAddressSpace),
        GIM_CheckMemoryAddressSpace, /*MI*/0, /*MMO*/0, /*NumAddrSpace*/4, /*AddrSpace*/0, /*AddrSpace*/1, /*AddrSpace*/4, /*AddrSpace*/6,
        GIM_CheckHasNoUse, /*MI*/0,
        GIM_CheckPointerToAny, /*MI*/0, /*Op*/1, /*SizeInBits*/0,
        GIM_CheckComplexPattern, /*MI*/0, /*Op*/1, /*Renderer*/GIMT_Encode2(0), GIMT_Encode2(GICP_gi_flat_offset),
        // (atomic_load_udec_wrap:{ *:[i32] } (FlatOffset:{ *:[iPTR] } i64:{ *:[i64] }:$vaddr, i32:{ *:[i32] }:$offset), i32:{ *:[i32] }:$data)<<P:Predicate_atomic_load_udec_wrap_flat_noret_32>>  =>  (FLAT_ATOMIC_DEC VReg_64:{ *:[i64] }:$vaddr, anonymous_15037:{ *:[i32] }:$data, ?:{ *:[i32] }:$offset)
        GIR_BuildMI, /*InsnID*/0, /*Opcode*/GIMT_Encode2(AMDGPU::FLAT_ATOMIC_DEC),
        GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/0, // vaddr
        GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/2, // data
        GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/1, // offset
        GIR_AddImm8, /*InsnID*/0, /*Imm*/0,
        GIR_MergeMemOperands, /*InsnID*/0, /*NumInsns*/1, /*MergeInsnID's*/0,
        GIR_ConstrainSelectedInstOperands, /*InsnID*/0,
        GIR_EraseFromParent, /*InsnID*/0,
        // GIR_Coverage, 2834,
        GIR_Done,
      // Label 3001: @192670
      GIM_Try, /*On fail goto*//*Label 3002*/ GIMT_Encode4(192728), // Rule ID 2886 //
        GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasFlatAddressSpace),
        GIM_CheckMemoryAddressSpace, /*MI*/0, /*MMO*/0, /*NumAddrSpace*/3, /*AddrSpace*/1, /*AddrSpace*/4, /*AddrSpace*/6,
        GIM_CheckHasNoUse, /*MI*/0,
        GIM_CheckPointerToAny, /*MI*/0, /*Op*/1, /*SizeInBits*/0,
        GIM_CheckComplexPattern, /*MI*/0, /*Op*/1, /*Renderer*/GIMT_Encode2(0), GIMT_Encode2(GICP_gi_flat_offset),
        // (atomic_load_udec_wrap:{ *:[i32] } (FlatOffset:{ *:[iPTR] } i64:{ *:[i64] }:$vaddr, i32:{ *:[i32] }:$offset), i32:{ *:[i32] }:$data)<<P:Predicate_atomic_load_udec_wrap_global_noret_32>>  =>  (FLAT_ATOMIC_DEC VReg_64:{ *:[i64] }:$vaddr, anonymous_15037:{ *:[i32] }:$data, ?:{ *:[i32] }:$offset)
        GIR_BuildMI, /*InsnID*/0, /*Opcode*/GIMT_Encode2(AMDGPU::FLAT_ATOMIC_DEC),
        GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/0, // vaddr
        GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/2, // data
        GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/1, // offset
        GIR_AddImm8, /*InsnID*/0, /*Imm*/0,
        GIR_MergeMemOperands, /*InsnID*/0, /*NumInsns*/1, /*MergeInsnID's*/0,
        GIR_ConstrainSelectedInstOperands, /*InsnID*/0,
        GIR_EraseFromParent, /*InsnID*/0,
        // GIR_Coverage, 2886,
        GIR_Done,
      // Label 3002: @192728
      GIM_Try, /*On fail goto*//*Label 3003*/ GIMT_Encode4(192794), // Rule ID 2833 //
        GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasFlatAddressSpace),
        GIM_CheckMemoryAddressSpace, /*MI*/0, /*MMO*/0, /*NumAddrSpace*/4, /*AddrSpace*/0, /*AddrSpace*/1, /*AddrSpace*/4, /*AddrSpace*/6,
        GIM_CheckRegBankForClass, /*MI*/0, /*Op*/0, /*RC*/GIMT_Encode2(AMDGPU::AV_32RegClassID),
        GIM_CheckPointerToAny, /*MI*/0, /*Op*/1, /*SizeInBits*/0,
        GIM_CheckComplexPattern, /*MI*/0, /*Op*/1, /*Renderer*/GIMT_Encode2(0), GIMT_Encode2(GICP_gi_flat_offset),
        // (atomic_load_udec_wrap:{ *:[i32] } (FlatOffset:{ *:[iPTR] } i64:{ *:[i64] }:$vaddr, i32:{ *:[i32] }:$offset), i32:{ *:[i32] }:$data)<<P:Predicate_atomic_load_udec_wrap_flat_32>>  =>  (FLAT_ATOMIC_DEC_RTN:{ *:[i32] } VReg_64:{ *:[i64] }:$vaddr, anonymous_15037:{ *:[i32] }:$data, ?:{ *:[i32] }:$offset)
        GIR_BuildMI, /*InsnID*/0, /*Opcode*/GIMT_Encode2(AMDGPU::FLAT_ATOMIC_DEC_RTN),
        GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/0, // DstI[vdst]
        GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/0, // vaddr
        GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/2, // data
        GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/1, // offset
        GIR_AddImm8, /*InsnID*/0, /*Imm*/1,
        GIR_MergeMemOperands, /*InsnID*/0, /*NumInsns*/1, /*MergeInsnID's*/0,
        GIR_ConstrainSelectedInstOperands, /*InsnID*/0,
        GIR_EraseFromParent, /*InsnID*/0,
        // GIR_Coverage, 2833,
        GIR_Done,
      // Label 3003: @192794
      GIM_Try, /*On fail goto*//*Label 3004*/ GIMT_Encode4(192859), // Rule ID 2885 //
        GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasFlatAddressSpace),
        GIM_CheckMemoryAddressSpace, /*MI*/0, /*MMO*/0, /*NumAddrSpace*/3, /*AddrSpace*/1, /*AddrSpace*/4, /*AddrSpace*/6,
        GIM_CheckRegBankForClass, /*MI*/0, /*Op*/0, /*RC*/GIMT_Encode2(AMDGPU::AV_32RegClassID),
        GIM_CheckPointerToAny, /*MI*/0, /*Op*/1, /*SizeInBits*/0,
        GIM_CheckComplexPattern, /*MI*/0, /*Op*/1, /*Renderer*/GIMT_Encode2(0), GIMT_Encode2(GICP_gi_flat_offset),
        // (atomic_load_udec_wrap:{ *:[i32] } (FlatOffset:{ *:[iPTR] } i64:{ *:[i64] }:$vaddr, i32:{ *:[i32] }:$offset), i32:{ *:[i32] }:$data)<<P:Predicate_atomic_load_udec_wrap_global_32>>  =>  (FLAT_ATOMIC_DEC_RTN:{ *:[i32] } VReg_64:{ *:[i64] }:$vaddr, anonymous_15037:{ *:[i32] }:$data, ?:{ *:[i32] }:$offset)
        GIR_BuildMI, /*InsnID*/0, /*Opcode*/GIMT_Encode2(AMDGPU::FLAT_ATOMIC_DEC_RTN),
        GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/0, // DstI[vdst]
        GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/0, // vaddr
        GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/2, // data
        GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/1, // offset
        GIR_AddImm8, /*InsnID*/0, /*Imm*/1,
        GIR_MergeMemOperands, /*InsnID*/0, /*NumInsns*/1, /*MergeInsnID's*/0,
        GIR_ConstrainSelectedInstOperands, /*InsnID*/0,
        GIR_EraseFromParent, /*InsnID*/0,
        // GIR_Coverage, 2885,
        GIR_Done,
      // Label 3004: @192859
      GIM_Reject,
    // Label 2982: @192860
    GIM_Reject,
    // Label 2980: @192861
    GIM_Try, /*On fail goto*//*Label 3005*/ GIMT_Encode4(194272),
      GIM_CheckType, /*MI*/0, /*Op*/2, /*Type*/GILLT_s64,
      GIM_Try, /*On fail goto*//*Label 3006*/ GIMT_Encode4(192938), // Rule ID 4694 //
        GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasUnrestrictedSOffset),
        GIM_CheckMemoryAddressSpace, /*MI*/0, /*MMO*/0, /*NumAddrSpace*/3, /*AddrSpace*/1, /*AddrSpace*/4, /*AddrSpace*/6,
        GIM_CheckHasNoUse, /*MI*/0,
        GIM_CheckPointerToAny, /*MI*/0, /*Op*/1, /*SizeInBits*/0,
        GIM_CheckComplexPattern, /*MI*/0, /*Op*/1, /*Renderer*/GIMT_Encode2(0), GIMT_Encode2(GICP_gi_mubuf_addr64),
        // (atomic_load_udec_wrap:{ *:[i64] } (MUBUFAddr64:{ *:[iPTR] } v4i32:{ *:[v4i32] }:$srsrc, i64:{ *:[i64] }:$vaddr, i32:{ *:[i32] }:$soffset, i32:{ *:[i32] }:$offset), i64:{ *:[i64] }:$vdata_in)<<P:Predicate_atomic_load_udec_wrap_global_noret_64>>  =>  (BUFFER_ATOMIC_DEC_X2_ADDR64 anonymous_15036:{ *:[i64] }:$vdata_in, VReg_64:{ *:[i64] }:$vaddr, SReg_128:{ *:[v4i32] }:$srsrc, SCSrc_b32:{ *:[i32] }:$soffset, offset:{ *:[i32] }:$offset)
        GIR_BuildMI, /*InsnID*/0, /*Opcode*/GIMT_Encode2(AMDGPU::BUFFER_ATOMIC_DEC_X2_ADDR64),
        GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/2, // vdata_in
        GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/1, // vaddr
        GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/0, // srsrc
        GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/2, // soffset
        GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/3, // offset
        GIR_AddImm8, /*InsnID*/0, /*Imm*/0,
        GIR_MergeMemOperands, /*InsnID*/0, /*NumInsns*/1, /*MergeInsnID's*/0,
        GIR_ConstrainSelectedInstOperands, /*InsnID*/0,
        GIR_EraseFromParent, /*InsnID*/0,
        // GIR_Coverage, 4694,
        GIR_Done,
      // Label 3006: @192938
      GIM_Try, /*On fail goto*//*Label 3007*/ GIMT_Encode4(193003), // Rule ID 4698 //
        GIM_CheckMemoryAddressSpace, /*MI*/0, /*MMO*/0, /*NumAddrSpace*/3, /*AddrSpace*/1, /*AddrSpace*/4, /*AddrSpace*/6,
        GIM_CheckHasNoUse, /*MI*/0,
        GIM_CheckPointerToAny, /*MI*/0, /*Op*/1, /*SizeInBits*/0,
        GIM_CheckComplexPattern, /*MI*/0, /*Op*/1, /*Renderer*/GIMT_Encode2(0), GIMT_Encode2(GICP_gi_mubuf_addr64),
        // (atomic_load_udec_wrap:{ *:[i64] } (MUBUFAddr64:{ *:[iPTR] } v4i32:{ *:[v4i32] }:$srsrc, i64:{ *:[i64] }:$vaddr, i32:{ *:[i32] }:$soffset, i32:{ *:[i32] }:$offset), i64:{ *:[i64] }:$vdata_in)<<P:Predicate_atomic_load_udec_wrap_global_noret_64>>  =>  (BUFFER_ATOMIC_DEC_X2_VBUFFER_ADDR64 anonymous_15036:{ *:[i64] }:$vdata_in, VReg_64:{ *:[i64] }:$vaddr, SReg_128:{ *:[v4i32] }:$srsrc, SCSrc_b32:{ *:[i32] }:$soffset, offset:{ *:[i32] }:$offset)
        GIR_BuildMI, /*InsnID*/0, /*Opcode*/GIMT_Encode2(AMDGPU::BUFFER_ATOMIC_DEC_X2_VBUFFER_ADDR64),
        GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/2, // vdata_in
        GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/1, // vaddr
        GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/0, // srsrc
        GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/2, // soffset
        GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/3, // offset
        GIR_AddImm8, /*InsnID*/0, /*Imm*/0,
        GIR_MergeMemOperands, /*InsnID*/0, /*NumInsns*/1, /*MergeInsnID's*/0,
        GIR_ConstrainSelectedInstOperands, /*InsnID*/0,
        GIR_EraseFromParent, /*InsnID*/0,
        // GIR_Coverage, 4698,
        GIR_Done,
      // Label 3007: @193003
      GIM_Try, /*On fail goto*//*Label 3008*/ GIMT_Encode4(193078), // Rule ID 4692 //
        GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasUnrestrictedSOffset),
        GIM_CheckMemoryAddressSpace, /*MI*/0, /*MMO*/0, /*NumAddrSpace*/3, /*AddrSpace*/1, /*AddrSpace*/4, /*AddrSpace*/6,
        GIM_CheckRegBankForClass, /*MI*/0, /*Op*/0, /*RC*/GIMT_Encode2(AMDGPU::AV_64RegClassID),
        GIM_CheckPointerToAny, /*MI*/0, /*Op*/1, /*SizeInBits*/0,
        GIM_CheckComplexPattern, /*MI*/0, /*Op*/1, /*Renderer*/GIMT_Encode2(0), GIMT_Encode2(GICP_gi_mubuf_addr64),
        // (atomic_load_udec_wrap:{ *:[i64] } (MUBUFAddr64:{ *:[iPTR] } v4i32:{ *:[v4i32] }:$srsrc, i64:{ *:[i64] }:$vaddr, i32:{ *:[i32] }:$soffset, i32:{ *:[i32] }:$offset), i64:{ *:[i64] }:$vdata_in)<<P:Predicate_atomic_load_udec_wrap_global_64>>  =>  (BUFFER_ATOMIC_DEC_X2_ADDR64_RTN:{ *:[i64] } anonymous_15036:{ *:[i64] }:$vdata_in, VReg_64:{ *:[i64] }:$vaddr, SReg_128:{ *:[v4i32] }:$srsrc, SCSrc_b32:{ *:[i32] }:$soffset, offset:{ *:[i32] }:$offset)
        GIR_BuildMI, /*InsnID*/0, /*Opcode*/GIMT_Encode2(AMDGPU::BUFFER_ATOMIC_DEC_X2_ADDR64_RTN),
        GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/0, // DstI[vdata]
        GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/2, // vdata_in
        GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/1, // vaddr
        GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/0, // srsrc
        GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/2, // soffset
        GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/3, // offset
        GIR_AddImm8, /*InsnID*/0, /*Imm*/1,
        GIR_MergeMemOperands, /*InsnID*/0, /*NumInsns*/1, /*MergeInsnID's*/0,
        GIR_ConstrainSelectedInstOperands, /*InsnID*/0,
        GIR_EraseFromParent, /*InsnID*/0,
        // GIR_Coverage, 4692,
        GIR_Done,
      // Label 3008: @193078
      GIM_Try, /*On fail goto*//*Label 3009*/ GIMT_Encode4(193150), // Rule ID 4696 //
        GIM_CheckMemoryAddressSpace, /*MI*/0, /*MMO*/0, /*NumAddrSpace*/3, /*AddrSpace*/1, /*AddrSpace*/4, /*AddrSpace*/6,
        GIM_CheckRegBankForClass, /*MI*/0, /*Op*/0, /*RC*/GIMT_Encode2(AMDGPU::AV_64RegClassID),
        GIM_CheckPointerToAny, /*MI*/0, /*Op*/1, /*SizeInBits*/0,
        GIM_CheckComplexPattern, /*MI*/0, /*Op*/1, /*Renderer*/GIMT_Encode2(0), GIMT_Encode2(GICP_gi_mubuf_addr64),
        // (atomic_load_udec_wrap:{ *:[i64] } (MUBUFAddr64:{ *:[iPTR] } v4i32:{ *:[v4i32] }:$srsrc, i64:{ *:[i64] }:$vaddr, i32:{ *:[i32] }:$soffset, i32:{ *:[i32] }:$offset), i64:{ *:[i64] }:$vdata_in)<<P:Predicate_atomic_load_udec_wrap_global_64>>  =>  (BUFFER_ATOMIC_DEC_X2_VBUFFER_ADDR64_RTN:{ *:[i64] } anonymous_15036:{ *:[i64] }:$vdata_in, VReg_64:{ *:[i64] }:$vaddr, SReg_128:{ *:[v4i32] }:$srsrc, SCSrc_b32:{ *:[i32] }:$soffset, offset:{ *:[i32] }:$offset)
        GIR_BuildMI, /*InsnID*/0, /*Opcode*/GIMT_Encode2(AMDGPU::BUFFER_ATOMIC_DEC_X2_VBUFFER_ADDR64_RTN),
        GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/0, // DstI[vdata]
        GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/2, // vdata_in
        GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/1, // vaddr
        GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/0, // srsrc
        GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/2, // soffset
        GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/3, // offset
        GIR_AddImm8, /*InsnID*/0, /*Imm*/1,
        GIR_MergeMemOperands, /*InsnID*/0, /*NumInsns*/1, /*MergeInsnID's*/0,
        GIR_ConstrainSelectedInstOperands, /*InsnID*/0,
        GIR_EraseFromParent, /*InsnID*/0,
        // GIR_Coverage, 4696,
        GIR_Done,
      // Label 3009: @193150
      GIM_Try, /*On fail goto*//*Label 3010*/ GIMT_Encode4(193213), // Rule ID 4693 //
        GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasUnrestrictedSOffset),
        GIM_CheckMemoryAddressSpace, /*MI*/0, /*MMO*/0, /*NumAddrSpace*/3, /*AddrSpace*/1, /*AddrSpace*/4, /*AddrSpace*/6,
        GIM_CheckHasNoUse, /*MI*/0,
        GIM_CheckPointerToAny, /*MI*/0, /*Op*/1, /*SizeInBits*/0,
        GIM_CheckComplexPattern, /*MI*/0, /*Op*/1, /*Renderer*/GIMT_Encode2(0), GIMT_Encode2(GICP_gi_mubuf_offset),
        // (atomic_load_udec_wrap:{ *:[i64] } (MUBUFOffset:{ *:[iPTR] } v4i32:{ *:[v4i32] }:$srsrc, i32:{ *:[i32] }:$soffset, i32:{ *:[i32] }:$offset), i64:{ *:[i64] }:$vdata_in)<<P:Predicate_atomic_load_udec_wrap_global_noret_64>>  =>  (BUFFER_ATOMIC_DEC_X2_OFFSET anonymous_15036:{ *:[i64] }:$vdata_in, SReg_128:{ *:[v4i32] }:$srsrc, SCSrc_b32:{ *:[i32] }:$soffset, offset:{ *:[i32] }:$offset)
        GIR_BuildMI, /*InsnID*/0, /*Opcode*/GIMT_Encode2(AMDGPU::BUFFER_ATOMIC_DEC_X2_OFFSET),
        GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/2, // vdata_in
        GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/0, // srsrc
        GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/1, // soffset
        GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/2, // offset
        GIR_AddImm8, /*InsnID*/0, /*Imm*/0,
        GIR_MergeMemOperands, /*InsnID*/0, /*NumInsns*/1, /*MergeInsnID's*/0,
        GIR_ConstrainSelectedInstOperands, /*InsnID*/0,
        GIR_EraseFromParent, /*InsnID*/0,
        // GIR_Coverage, 4693,
        GIR_Done,
      // Label 3010: @193213
      GIM_Try, /*On fail goto*//*Label 3011*/ GIMT_Encode4(193273), // Rule ID 4697 //
        GIM_CheckMemoryAddressSpace, /*MI*/0, /*MMO*/0, /*NumAddrSpace*/3, /*AddrSpace*/1, /*AddrSpace*/4, /*AddrSpace*/6,
        GIM_CheckHasNoUse, /*MI*/0,
        GIM_CheckPointerToAny, /*MI*/0, /*Op*/1, /*SizeInBits*/0,
        GIM_CheckComplexPattern, /*MI*/0, /*Op*/1, /*Renderer*/GIMT_Encode2(0), GIMT_Encode2(GICP_gi_mubuf_offset),
        // (atomic_load_udec_wrap:{ *:[i64] } (MUBUFOffset:{ *:[iPTR] } v4i32:{ *:[v4i32] }:$srsrc, i32:{ *:[i32] }:$soffset, i32:{ *:[i32] }:$offset), i64:{ *:[i64] }:$vdata_in)<<P:Predicate_atomic_load_udec_wrap_global_noret_64>>  =>  (BUFFER_ATOMIC_DEC_X2_VBUFFER_OFFSET anonymous_15036:{ *:[i64] }:$vdata_in, SReg_128:{ *:[v4i32] }:$srsrc, SCSrc_b32:{ *:[i32] }:$soffset, offset:{ *:[i32] }:$offset)
        GIR_BuildMI, /*InsnID*/0, /*Opcode*/GIMT_Encode2(AMDGPU::BUFFER_ATOMIC_DEC_X2_VBUFFER_OFFSET),
        GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/2, // vdata_in
        GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/0, // srsrc
        GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/1, // soffset
        GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/2, // offset
        GIR_AddImm8, /*InsnID*/0, /*Imm*/0,
        GIR_MergeMemOperands, /*InsnID*/0, /*NumInsns*/1, /*MergeInsnID's*/0,
        GIR_ConstrainSelectedInstOperands, /*InsnID*/0,
        GIR_EraseFromParent, /*InsnID*/0,
        // GIR_Coverage, 4697,
        GIR_Done,
      // Label 3011: @193273
      GIM_Try, /*On fail goto*//*Label 3012*/ GIMT_Encode4(193343), // Rule ID 4691 //
        GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasUnrestrictedSOffset),
        GIM_CheckMemoryAddressSpace, /*MI*/0, /*MMO*/0, /*NumAddrSpace*/3, /*AddrSpace*/1, /*AddrSpace*/4, /*AddrSpace*/6,
        GIM_CheckRegBankForClass, /*MI*/0, /*Op*/0, /*RC*/GIMT_Encode2(AMDGPU::AV_64RegClassID),
        GIM_CheckPointerToAny, /*MI*/0, /*Op*/1, /*SizeInBits*/0,
        GIM_CheckComplexPattern, /*MI*/0, /*Op*/1, /*Renderer*/GIMT_Encode2(0), GIMT_Encode2(GICP_gi_mubuf_offset),
        // (atomic_load_udec_wrap:{ *:[i64] } (MUBUFOffset:{ *:[iPTR] } v4i32:{ *:[v4i32] }:$srsrc, i32:{ *:[i32] }:$soffset, i32:{ *:[i32] }:$offset), i64:{ *:[i64] }:$vdata_in)<<P:Predicate_atomic_load_udec_wrap_global_64>>  =>  (BUFFER_ATOMIC_DEC_X2_OFFSET_RTN:{ *:[i64] } anonymous_15036:{ *:[i64] }:$vdata_in, SReg_128:{ *:[v4i32] }:$srsrc, SCSrc_b32:{ *:[i32] }:$soffset, offset:{ *:[i32] }:$offset)
        GIR_BuildMI, /*InsnID*/0, /*Opcode*/GIMT_Encode2(AMDGPU::BUFFER_ATOMIC_DEC_X2_OFFSET_RTN),
        GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/0, // DstI[vdata]
        GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/2, // vdata_in
        GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/0, // srsrc
        GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/1, // soffset
        GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/2, // offset
        GIR_AddImm8, /*InsnID*/0, /*Imm*/1,
        GIR_MergeMemOperands, /*InsnID*/0, /*NumInsns*/1, /*MergeInsnID's*/0,
        GIR_ConstrainSelectedInstOperands, /*InsnID*/0,
        GIR_EraseFromParent, /*InsnID*/0,
        // GIR_Coverage, 4691,
        GIR_Done,
      // Label 3012: @193343
      GIM_Try, /*On fail goto*//*Label 3013*/ GIMT_Encode4(193410), // Rule ID 4695 //
        GIM_CheckMemoryAddressSpace, /*MI*/0, /*MMO*/0, /*NumAddrSpace*/3, /*AddrSpace*/1, /*AddrSpace*/4, /*AddrSpace*/6,
        GIM_CheckRegBankForClass, /*MI*/0, /*Op*/0, /*RC*/GIMT_Encode2(AMDGPU::AV_64RegClassID),
        GIM_CheckPointerToAny, /*MI*/0, /*Op*/1, /*SizeInBits*/0,
        GIM_CheckComplexPattern, /*MI*/0, /*Op*/1, /*Renderer*/GIMT_Encode2(0), GIMT_Encode2(GICP_gi_mubuf_offset),
        // (atomic_load_udec_wrap:{ *:[i64] } (MUBUFOffset:{ *:[iPTR] } v4i32:{ *:[v4i32] }:$srsrc, i32:{ *:[i32] }:$soffset, i32:{ *:[i32] }:$offset), i64:{ *:[i64] }:$vdata_in)<<P:Predicate_atomic_load_udec_wrap_global_64>>  =>  (BUFFER_ATOMIC_DEC_X2_VBUFFER_OFFSET_RTN:{ *:[i64] } anonymous_15036:{ *:[i64] }:$vdata_in, SReg_128:{ *:[v4i32] }:$srsrc, SCSrc_b32:{ *:[i32] }:$soffset, offset:{ *:[i32] }:$offset)
        GIR_BuildMI, /*InsnID*/0, /*Opcode*/GIMT_Encode2(AMDGPU::BUFFER_ATOMIC_DEC_X2_VBUFFER_OFFSET_RTN),
        GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/0, // DstI[vdata]
        GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/2, // vdata_in
        GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/0, // srsrc
        GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/1, // soffset
        GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/2, // offset
        GIR_AddImm8, /*InsnID*/0, /*Imm*/1,
        GIR_MergeMemOperands, /*InsnID*/0, /*NumInsns*/1, /*MergeInsnID's*/0,
        GIR_ConstrainSelectedInstOperands, /*InsnID*/0,
        GIR_EraseFromParent, /*InsnID*/0,
        // GIR_Coverage, 4695,
        GIR_Done,
      // Label 3013: @193410
      GIM_Try, /*On fail goto*//*Label 3014*/ GIMT_Encode4(193466), // Rule ID 7010 //
        GIM_CheckFeatures, GIMT_Encode2(GIFBS_LDSRequiresM0Init),
        GIM_CheckMemoryAddressSpace, /*MI*/0, /*MMO*/0, /*NumAddrSpace*/1, /*AddrSpace*/3,
        GIM_CheckHasNoUse, /*MI*/0,
        GIM_CheckPointerToAny, /*MI*/0, /*Op*/1, /*SizeInBits*/0,
        GIM_CheckComplexPattern, /*MI*/0, /*Op*/1, /*Renderer*/GIMT_Encode2(0), GIMT_Encode2(GICP_gi_ds_1addr_1offset),
        // (atomic_load_udec_wrap_glue:{ *:[i64] } (DS1Addr1Offset:{ *:[iPTR] } i32:{ *:[i32] }:$ptr, i32:{ *:[i32] }:$offset), i64:{ *:[i64] }:$value)<<P:Predicate_atomic_load_udec_wrap_local_m0_noret_64>>  =>  (DS_DEC_U64 ?:{ *:[i32] }:$ptr, anonymous_15036:{ *:[i64] }:$value, offset:{ *:[i32] }:$offset, 0:{ *:[i1] })
        GIR_BuildMI, /*InsnID*/0, /*Opcode*/GIMT_Encode2(AMDGPU::DS_DEC_U64),
        GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/0, // ptr
        GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/2, // value
        GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/1, // offset
        GIR_AddImm8, /*InsnID*/0, /*Imm*/0,
        GIR_MergeMemOperands, /*InsnID*/0, /*NumInsns*/1, /*MergeInsnID's*/0,
        GIR_ConstrainSelectedInstOperands, /*InsnID*/0,
        GIR_EraseFromParent, /*InsnID*/0,
        // GIR_Coverage, 7010,
        GIR_Done,
      // Label 3014: @193466
      GIM_Try, /*On fail goto*//*Label 3015*/ GIMT_Encode4(193522), // Rule ID 7012 //
        GIM_CheckFeatures, GIMT_Encode2(GIFBS_NotLDSRequiresM0Init),
        GIM_CheckMemoryAddressSpace, /*MI*/0, /*MMO*/0, /*NumAddrSpace*/1, /*AddrSpace*/3,
        GIM_CheckHasNoUse, /*MI*/0,
        GIM_CheckPointerToAny, /*MI*/0, /*Op*/1, /*SizeInBits*/0,
        GIM_CheckComplexPattern, /*MI*/0, /*Op*/1, /*Renderer*/GIMT_Encode2(0), GIMT_Encode2(GICP_gi_ds_1addr_1offset),
        // (atomic_load_udec_wrap:{ *:[i64] } (DS1Addr1Offset:{ *:[iPTR] } i32:{ *:[i32] }:$ptr, i32:{ *:[i32] }:$offset), i64:{ *:[i64] }:$value)<<P:Predicate_atomic_load_udec_wrap_local_noret_64>>  =>  (DS_DEC_U64_gfx9 ?:{ *:[i32] }:$ptr, anonymous_15036:{ *:[i64] }:$value, offset:{ *:[i32] }:$offset, 0:{ *:[i1] })
        GIR_BuildMI, /*InsnID*/0, /*Opcode*/GIMT_Encode2(AMDGPU::DS_DEC_U64_gfx9),
        GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/0, // ptr
        GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/2, // value
        GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/1, // offset
        GIR_AddImm8, /*InsnID*/0, /*Imm*/0,
        GIR_MergeMemOperands, /*InsnID*/0, /*NumInsns*/1, /*MergeInsnID's*/0,
        GIR_ConstrainSelectedInstOperands, /*InsnID*/0,
        GIR_EraseFromParent, /*InsnID*/0,
        // GIR_Coverage, 7012,
        GIR_Done,
      // Label 3015: @193522
      GIM_Try, /*On fail goto*//*Label 3016*/ GIMT_Encode4(193578), // Rule ID 7014 //
        GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasGDS),
        GIM_CheckMemoryAddressSpace, /*MI*/0, /*MMO*/0, /*NumAddrSpace*/1, /*AddrSpace*/2,
        GIM_CheckHasNoUse, /*MI*/0,
        GIM_CheckPointerToAny, /*MI*/0, /*Op*/1, /*SizeInBits*/0,
        GIM_CheckComplexPattern, /*MI*/0, /*Op*/1, /*Renderer*/GIMT_Encode2(0), GIMT_Encode2(GICP_gi_ds_1addr_1offset),
        // (atomic_load_udec_wrap_glue:{ *:[i64] } (DS1Addr1Offset:{ *:[iPTR] } i32:{ *:[i32] }:$ptr, i32:{ *:[i32] }:$offset), i64:{ *:[i64] }:$value)<<P:Predicate_atomic_load_udec_wrap_region_m0_noret_64>>  =>  (DS_DEC_U64 ?:{ *:[i32] }:$ptr, anonymous_15036:{ *:[i64] }:$value, offset:{ *:[i32] }:$offset, 1:{ *:[i1] })
        GIR_BuildMI, /*InsnID*/0, /*Opcode*/GIMT_Encode2(AMDGPU::DS_DEC_U64),
        GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/0, // ptr
        GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/2, // value
        GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/1, // offset
        GIR_AddImm8, /*InsnID*/0, /*Imm*/1,
        GIR_MergeMemOperands, /*InsnID*/0, /*NumInsns*/1, /*MergeInsnID's*/0,
        GIR_ConstrainSelectedInstOperands, /*InsnID*/0,
        GIR_EraseFromParent, /*InsnID*/0,
        // GIR_Coverage, 7014,
        GIR_Done,
      // Label 3016: @193578
      GIM_Try, /*On fail goto*//*Label 3017*/ GIMT_Encode4(193641), // Rule ID 7009 //
        GIM_CheckFeatures, GIMT_Encode2(GIFBS_LDSRequiresM0Init),
        GIM_CheckMemoryAddressSpace, /*MI*/0, /*MMO*/0, /*NumAddrSpace*/1, /*AddrSpace*/3,
        GIM_CheckRegBankForClass, /*MI*/0, /*Op*/0, /*RC*/GIMT_Encode2(AMDGPU::AV_64RegClassID),
        GIM_CheckPointerToAny, /*MI*/0, /*Op*/1, /*SizeInBits*/0,
        GIM_CheckComplexPattern, /*MI*/0, /*Op*/1, /*Renderer*/GIMT_Encode2(0), GIMT_Encode2(GICP_gi_ds_1addr_1offset),
        // (atomic_load_udec_wrap_glue:{ *:[i64] } (DS1Addr1Offset:{ *:[iPTR] } i32:{ *:[i32] }:$ptr, i32:{ *:[i32] }:$offset), i64:{ *:[i64] }:$value)<<P:Predicate_atomic_load_udec_wrap_local_m0_64>>  =>  (DS_DEC_RTN_U64:{ *:[i64] } ?:{ *:[i32] }:$ptr, anonymous_15036:{ *:[i64] }:$value, offset:{ *:[i32] }:$offset, 0:{ *:[i1] })
        GIR_BuildMI, /*InsnID*/0, /*Opcode*/GIMT_Encode2(AMDGPU::DS_DEC_RTN_U64),
        GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/0, // DstI[vdst]
        GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/0, // ptr
        GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/2, // value
        GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/1, // offset
        GIR_AddImm8, /*InsnID*/0, /*Imm*/0,
        GIR_MergeMemOperands, /*InsnID*/0, /*NumInsns*/1, /*MergeInsnID's*/0,
        GIR_ConstrainSelectedInstOperands, /*InsnID*/0,
        GIR_EraseFromParent, /*InsnID*/0,
        // GIR_Coverage, 7009,
        GIR_Done,
      // Label 3017: @193641
      GIM_Try, /*On fail goto*//*Label 3018*/ GIMT_Encode4(193704), // Rule ID 7011 //
        GIM_CheckFeatures, GIMT_Encode2(GIFBS_NotLDSRequiresM0Init),
        GIM_CheckMemoryAddressSpace, /*MI*/0, /*MMO*/0, /*NumAddrSpace*/1, /*AddrSpace*/3,
        GIM_CheckRegBankForClass, /*MI*/0, /*Op*/0, /*RC*/GIMT_Encode2(AMDGPU::AV_64RegClassID),
        GIM_CheckPointerToAny, /*MI*/0, /*Op*/1, /*SizeInBits*/0,
        GIM_CheckComplexPattern, /*MI*/0, /*Op*/1, /*Renderer*/GIMT_Encode2(0), GIMT_Encode2(GICP_gi_ds_1addr_1offset),
        // (atomic_load_udec_wrap:{ *:[i64] } (DS1Addr1Offset:{ *:[iPTR] } i32:{ *:[i32] }:$ptr, i32:{ *:[i32] }:$offset), i64:{ *:[i64] }:$value)<<P:Predicate_atomic_load_udec_wrap_local_64>>  =>  (DS_DEC_RTN_U64_gfx9:{ *:[i64] } ?:{ *:[i32] }:$ptr, anonymous_15036:{ *:[i64] }:$value, offset:{ *:[i32] }:$offset, 0:{ *:[i1] })
        GIR_BuildMI, /*InsnID*/0, /*Opcode*/GIMT_Encode2(AMDGPU::DS_DEC_RTN_U64_gfx9),
        GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/0, // DstI[vdst]
        GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/0, // ptr
        GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/2, // value
        GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/1, // offset
        GIR_AddImm8, /*InsnID*/0, /*Imm*/0,
        GIR_MergeMemOperands, /*InsnID*/0, /*NumInsns*/1, /*MergeInsnID's*/0,
        GIR_ConstrainSelectedInstOperands, /*InsnID*/0,
        GIR_EraseFromParent, /*InsnID*/0,
        // GIR_Coverage, 7011,
        GIR_Done,
      // Label 3018: @193704
      GIM_Try, /*On fail goto*//*Label 3019*/ GIMT_Encode4(193767), // Rule ID 7013 //
        GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasGDS),
        GIM_CheckMemoryAddressSpace, /*MI*/0, /*MMO*/0, /*NumAddrSpace*/1, /*AddrSpace*/2,
        GIM_CheckRegBankForClass, /*MI*/0, /*Op*/0, /*RC*/GIMT_Encode2(AMDGPU::AV_64RegClassID),
        GIM_CheckPointerToAny, /*MI*/0, /*Op*/1, /*SizeInBits*/0,
        GIM_CheckComplexPattern, /*MI*/0, /*Op*/1, /*Renderer*/GIMT_Encode2(0), GIMT_Encode2(GICP_gi_ds_1addr_1offset),
        // (atomic_load_udec_wrap_glue:{ *:[i64] } (DS1Addr1Offset:{ *:[iPTR] } i32:{ *:[i32] }:$ptr, i32:{ *:[i32] }:$offset), i64:{ *:[i64] }:$value)<<P:Predicate_atomic_load_udec_wrap_region_m0_64>>  =>  (DS_DEC_RTN_U64:{ *:[i64] } ?:{ *:[i32] }:$ptr, anonymous_15036:{ *:[i64] }:$value, offset:{ *:[i32] }:$offset, 1:{ *:[i1] })
        GIR_BuildMI, /*InsnID*/0, /*Opcode*/GIMT_Encode2(AMDGPU::DS_DEC_RTN_U64),
        GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/0, // DstI[vdst]
        GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/0, // ptr
        GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/2, // value
        GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/1, // offset
        GIR_AddImm8, /*InsnID*/0, /*Imm*/1,
        GIR_MergeMemOperands, /*InsnID*/0, /*NumInsns*/1, /*MergeInsnID's*/0,
        GIR_ConstrainSelectedInstOperands, /*InsnID*/0,
        GIR_EraseFromParent, /*InsnID*/0,
        // GIR_Coverage, 7013,
        GIR_Done,
      // Label 3019: @193767
      GIM_Try, /*On fail goto*//*Label 3020*/ GIMT_Encode4(193830), // Rule ID 3215 //
        GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasFlatGlobalInsts),
        GIM_CheckMemoryAddressSpace, /*MI*/0, /*MMO*/0, /*NumAddrSpace*/3, /*AddrSpace*/1, /*AddrSpace*/4, /*AddrSpace*/6,
        GIM_CheckHasNoUse, /*MI*/0,
        GIM_CheckPointerToAny, /*MI*/0, /*Op*/1, /*SizeInBits*/0,
        GIM_CheckComplexPattern, /*MI*/0, /*Op*/1, /*Renderer*/GIMT_Encode2(0), GIMT_Encode2(GICP_gi_global_saddr),
        // (atomic_load_udec_wrap:{ *:[i64] } (GlobalSAddr:{ *:[iPTR] } SReg_64:{ *:[i64] }:$saddr, VGPR_32:{ *:[i32] }:$voffset, i32:{ *:[i32] }:$offset), i64:{ *:[i64] }:$data)<<P:Predicate_atomic_load_udec_wrap_global_noret_64>>  =>  (GLOBAL_ATOMIC_DEC_X2_SADDR ?:{ *:[i32] }:$voffset, anonymous_15036:{ *:[i64] }:$data, ?:{ *:[i64] }:$saddr, ?:{ *:[i32] }:$offset)
        GIR_BuildMI, /*InsnID*/0, /*Opcode*/GIMT_Encode2(AMDGPU::GLOBAL_ATOMIC_DEC_X2_SADDR),
        GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/1, // voffset
        GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/2, // data
        GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/0, // saddr
        GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/2, // offset
        GIR_AddImm8, /*InsnID*/0, /*Imm*/0,
        GIR_MergeMemOperands, /*InsnID*/0, /*NumInsns*/1, /*MergeInsnID's*/0,
        GIR_ConstrainSelectedInstOperands, /*InsnID*/0,
        GIR_EraseFromParent, /*InsnID*/0,
        // GIR_Coverage, 3215,
        GIR_Done,
      // Label 3020: @193830
      GIM_Try, /*On fail goto*//*Label 3021*/ GIMT_Encode4(193900), // Rule ID 3217 //
        GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasFlatGlobalInsts),
        GIM_CheckMemoryAddressSpace, /*MI*/0, /*MMO*/0, /*NumAddrSpace*/3, /*AddrSpace*/1, /*AddrSpace*/4, /*AddrSpace*/6,
        GIM_CheckRegBankForClass, /*MI*/0, /*Op*/0, /*RC*/GIMT_Encode2(AMDGPU::AV_64RegClassID),
        GIM_CheckPointerToAny, /*MI*/0, /*Op*/1, /*SizeInBits*/0,
        GIM_CheckComplexPattern, /*MI*/0, /*Op*/1, /*Renderer*/GIMT_Encode2(0), GIMT_Encode2(GICP_gi_global_saddr),
        // (atomic_load_udec_wrap:{ *:[i64] } (GlobalSAddr:{ *:[iPTR] } SReg_64:{ *:[i64] }:$saddr, VGPR_32:{ *:[i32] }:$voffset, i32:{ *:[i32] }:$offset), i64:{ *:[i64] }:$data)<<P:Predicate_atomic_load_udec_wrap_global_64>>  =>  (GLOBAL_ATOMIC_DEC_X2_SADDR_RTN:{ *:[i64] } ?:{ *:[i32] }:$voffset, anonymous_15036:{ *:[i64] }:$data, ?:{ *:[i64] }:$saddr, ?:{ *:[i32] }:$offset)
        GIR_BuildMI, /*InsnID*/0, /*Opcode*/GIMT_Encode2(AMDGPU::GLOBAL_ATOMIC_DEC_X2_SADDR_RTN),
        GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/0, // DstI[vdst]
        GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/1, // voffset
        GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/2, // data
        GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/0, // saddr
        GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/2, // offset
        GIR_AddImm8, /*InsnID*/0, /*Imm*/1,
        GIR_MergeMemOperands, /*InsnID*/0, /*NumInsns*/1, /*MergeInsnID's*/0,
        GIR_ConstrainSelectedInstOperands, /*InsnID*/0,
        GIR_EraseFromParent, /*InsnID*/0,
        // GIR_Coverage, 3217,
        GIR_Done,
      // Label 3021: @193900
      GIM_Try, /*On fail goto*//*Label 3022*/ GIMT_Encode4(193958), // Rule ID 3214 //
        GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasFlatGlobalInsts),
        GIM_CheckMemoryAddressSpace, /*MI*/0, /*MMO*/0, /*NumAddrSpace*/3, /*AddrSpace*/1, /*AddrSpace*/4, /*AddrSpace*/6,
        GIM_CheckHasNoUse, /*MI*/0,
        GIM_CheckPointerToAny, /*MI*/0, /*Op*/1, /*SizeInBits*/0,
        GIM_CheckComplexPattern, /*MI*/0, /*Op*/1, /*Renderer*/GIMT_Encode2(0), GIMT_Encode2(GICP_gi_global_offset),
        // (atomic_load_udec_wrap:{ *:[i64] } (GlobalOffset:{ *:[iPTR] } i64:{ *:[i64] }:$vaddr, i32:{ *:[i32] }:$offset), i64:{ *:[i64] }:$data)<<P:Predicate_atomic_load_udec_wrap_global_noret_64>>  =>  (GLOBAL_ATOMIC_DEC_X2 VReg_64:{ *:[i64] }:$vaddr, anonymous_15036:{ *:[i64] }:$data, ?:{ *:[i32] }:$offset)
        GIR_BuildMI, /*InsnID*/0, /*Opcode*/GIMT_Encode2(AMDGPU::GLOBAL_ATOMIC_DEC_X2),
        GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/0, // vaddr
        GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/2, // data
        GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/1, // offset
        GIR_AddImm8, /*InsnID*/0, /*Imm*/0,
        GIR_MergeMemOperands, /*InsnID*/0, /*NumInsns*/1, /*MergeInsnID's*/0,
        GIR_ConstrainSelectedInstOperands, /*InsnID*/0,
        GIR_EraseFromParent, /*InsnID*/0,
        // GIR_Coverage, 3214,
        GIR_Done,
      // Label 3022: @193958
      GIM_Try, /*On fail goto*//*Label 3023*/ GIMT_Encode4(194023), // Rule ID 3216 //
        GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasFlatGlobalInsts),
        GIM_CheckMemoryAddressSpace, /*MI*/0, /*MMO*/0, /*NumAddrSpace*/3, /*AddrSpace*/1, /*AddrSpace*/4, /*AddrSpace*/6,
        GIM_CheckRegBankForClass, /*MI*/0, /*Op*/0, /*RC*/GIMT_Encode2(AMDGPU::AV_64RegClassID),
        GIM_CheckPointerToAny, /*MI*/0, /*Op*/1, /*SizeInBits*/0,
        GIM_CheckComplexPattern, /*MI*/0, /*Op*/1, /*Renderer*/GIMT_Encode2(0), GIMT_Encode2(GICP_gi_global_offset),
        // (atomic_load_udec_wrap:{ *:[i64] } (GlobalOffset:{ *:[iPTR] } i64:{ *:[i64] }:$vaddr, i32:{ *:[i32] }:$offset), i64:{ *:[i64] }:$data)<<P:Predicate_atomic_load_udec_wrap_global_64>>  =>  (GLOBAL_ATOMIC_DEC_X2_RTN:{ *:[i64] } VReg_64:{ *:[i64] }:$vaddr, anonymous_15036:{ *:[i64] }:$data, ?:{ *:[i32] }:$offset)
        GIR_BuildMI, /*InsnID*/0, /*Opcode*/GIMT_Encode2(AMDGPU::GLOBAL_ATOMIC_DEC_X2_RTN),
        GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/0, // DstI[vdst]
        GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/0, // vaddr
        GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/2, // data
        GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/1, // offset
        GIR_AddImm8, /*InsnID*/0, /*Imm*/1,
        GIR_MergeMemOperands, /*InsnID*/0, /*NumInsns*/1, /*MergeInsnID's*/0,
        GIR_ConstrainSelectedInstOperands, /*InsnID*/0,
        GIR_EraseFromParent, /*InsnID*/0,
        // GIR_Coverage, 3216,
        GIR_Done,
      // Label 3023: @194023
      GIM_Try, /*On fail goto*//*Label 3024*/ GIMT_Encode4(194082), // Rule ID 2860 //
        GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasFlatAddressSpace),
        GIM_CheckMemoryAddressSpace, /*MI*/0, /*MMO*/0, /*NumAddrSpace*/4, /*AddrSpace*/0, /*AddrSpace*/1, /*AddrSpace*/4, /*AddrSpace*/6,
        GIM_CheckHasNoUse, /*MI*/0,
        GIM_CheckPointerToAny, /*MI*/0, /*Op*/1, /*SizeInBits*/0,
        GIM_CheckComplexPattern, /*MI*/0, /*Op*/1, /*Renderer*/GIMT_Encode2(0), GIMT_Encode2(GICP_gi_flat_offset),
        // (atomic_load_udec_wrap:{ *:[i64] } (FlatOffset:{ *:[iPTR] } i64:{ *:[i64] }:$vaddr, i32:{ *:[i32] }:$offset), i64:{ *:[i64] }:$data)<<P:Predicate_atomic_load_udec_wrap_flat_noret_64>>  =>  (FLAT_ATOMIC_DEC_X2 VReg_64:{ *:[i64] }:$vaddr, anonymous_15036:{ *:[i64] }:$data, ?:{ *:[i32] }:$offset)
        GIR_BuildMI, /*InsnID*/0, /*Opcode*/GIMT_Encode2(AMDGPU::FLAT_ATOMIC_DEC_X2),
        GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/0, // vaddr
        GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/2, // data
        GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/1, // offset
        GIR_AddImm8, /*InsnID*/0, /*Imm*/0,
        GIR_MergeMemOperands, /*InsnID*/0, /*NumInsns*/1, /*MergeInsnID's*/0,
        GIR_ConstrainSelectedInstOperands, /*InsnID*/0,
        GIR_EraseFromParent, /*InsnID*/0,
        // GIR_Coverage, 2860,
        GIR_Done,
      // Label 3024: @194082
      GIM_Try, /*On fail goto*//*Label 3025*/ GIMT_Encode4(194140), // Rule ID 2912 //
        GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasFlatAddressSpace),
        GIM_CheckMemoryAddressSpace, /*MI*/0, /*MMO*/0, /*NumAddrSpace*/3, /*AddrSpace*/1, /*AddrSpace*/4, /*AddrSpace*/6,
        GIM_CheckHasNoUse, /*MI*/0,
        GIM_CheckPointerToAny, /*MI*/0, /*Op*/1, /*SizeInBits*/0,
        GIM_CheckComplexPattern, /*MI*/0, /*Op*/1, /*Renderer*/GIMT_Encode2(0), GIMT_Encode2(GICP_gi_flat_offset),
        // (atomic_load_udec_wrap:{ *:[i64] } (FlatOffset:{ *:[iPTR] } i64:{ *:[i64] }:$vaddr, i32:{ *:[i32] }:$offset), i64:{ *:[i64] }:$data)<<P:Predicate_atomic_load_udec_wrap_global_noret_64>>  =>  (FLAT_ATOMIC_DEC_X2 VReg_64:{ *:[i64] }:$vaddr, anonymous_15036:{ *:[i64] }:$data, ?:{ *:[i32] }:$offset)
        GIR_BuildMI, /*InsnID*/0, /*Opcode*/GIMT_Encode2(AMDGPU::FLAT_ATOMIC_DEC_X2),
        GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/0, // vaddr
        GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/2, // data
        GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/1, // offset
        GIR_AddImm8, /*InsnID*/0, /*Imm*/0,
        GIR_MergeMemOperands, /*InsnID*/0, /*NumInsns*/1, /*MergeInsnID's*/0,
        GIR_ConstrainSelectedInstOperands, /*InsnID*/0,
        GIR_EraseFromParent, /*InsnID*/0,
        // GIR_Coverage, 2912,
        GIR_Done,
      // Label 3025: @194140
      GIM_Try, /*On fail goto*//*Label 3026*/ GIMT_Encode4(194206), // Rule ID 2859 //
        GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasFlatAddressSpace),
        GIM_CheckMemoryAddressSpace, /*MI*/0, /*MMO*/0, /*NumAddrSpace*/4, /*AddrSpace*/0, /*AddrSpace*/1, /*AddrSpace*/4, /*AddrSpace*/6,
        GIM_CheckRegBankForClass, /*MI*/0, /*Op*/0, /*RC*/GIMT_Encode2(AMDGPU::AV_64RegClassID),
        GIM_CheckPointerToAny, /*MI*/0, /*Op*/1, /*SizeInBits*/0,
        GIM_CheckComplexPattern, /*MI*/0, /*Op*/1, /*Renderer*/GIMT_Encode2(0), GIMT_Encode2(GICP_gi_flat_offset),
        // (atomic_load_udec_wrap:{ *:[i64] } (FlatOffset:{ *:[iPTR] } i64:{ *:[i64] }:$vaddr, i32:{ *:[i32] }:$offset), i64:{ *:[i64] }:$data)<<P:Predicate_atomic_load_udec_wrap_flat_64>>  =>  (FLAT_ATOMIC_DEC_X2_RTN:{ *:[i64] } VReg_64:{ *:[i64] }:$vaddr, anonymous_15036:{ *:[i64] }:$data, ?:{ *:[i32] }:$offset)
        GIR_BuildMI, /*InsnID*/0, /*Opcode*/GIMT_Encode2(AMDGPU::FLAT_ATOMIC_DEC_X2_RTN),
        GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/0, // DstI[vdst]
        GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/0, // vaddr
        GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/2, // data
        GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/1, // offset
        GIR_AddImm8, /*InsnID*/0, /*Imm*/1,
        GIR_MergeMemOperands, /*InsnID*/0, /*NumInsns*/1, /*MergeInsnID's*/0,
        GIR_ConstrainSelectedInstOperands, /*InsnID*/0,
        GIR_EraseFromParent, /*InsnID*/0,
        // GIR_Coverage, 2859,
        GIR_Done,
      // Label 3026: @194206
      GIM_Try, /*On fail goto*//*Label 3027*/ GIMT_Encode4(194271), // Rule ID 2911 //
        GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasFlatAddressSpace),
        GIM_CheckMemoryAddressSpace, /*MI*/0, /*MMO*/0, /*NumAddrSpace*/3, /*AddrSpace*/1, /*AddrSpace*/4, /*AddrSpace*/6,
        GIM_CheckRegBankForClass, /*MI*/0, /*Op*/0, /*RC*/GIMT_Encode2(AMDGPU::AV_64RegClassID),
        GIM_CheckPointerToAny, /*MI*/0, /*Op*/1, /*SizeInBits*/0,
        GIM_CheckComplexPattern, /*MI*/0, /*Op*/1, /*Renderer*/GIMT_Encode2(0), GIMT_Encode2(GICP_gi_flat_offset),
        // (atomic_load_udec_wrap:{ *:[i64] } (FlatOffset:{ *:[iPTR] } i64:{ *:[i64] }:$vaddr, i32:{ *:[i32] }:$offset), i64:{ *:[i64] }:$data)<<P:Predicate_atomic_load_udec_wrap_global_64>>  =>  (FLAT_ATOMIC_DEC_X2_RTN:{ *:[i64] } VReg_64:{ *:[i64] }:$vaddr, anonymous_15036:{ *:[i64] }:$data, ?:{ *:[i32] }:$offset)
        GIR_BuildMI, /*InsnID*/0, /*Opcode*/GIMT_Encode2(AMDGPU::FLAT_ATOMIC_DEC_X2_RTN),
        GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/0, // DstI[vdst]
        GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/0, // vaddr
        GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/2, // data
        GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/1, // offset
        GIR_AddImm8, /*InsnID*/0, /*Imm*/1,
        GIR_MergeMemOperands, /*InsnID*/0, /*NumInsns*/1, /*MergeInsnID's*/0,
        GIR_ConstrainSelectedInstOperands, /*InsnID*/0,
        GIR_EraseFromParent, /*InsnID*/0,
        // GIR_Coverage, 2911,
        GIR_Done,
      // Label 3027: @194271
      GIM_Reject,
    // Label 3005: @194272
    GIM_Reject,
    // Label 2981: @194273
    GIM_Reject,
    // Label 30: @194274
    GIM_Try, /*On fail goto*//*Label 3028*/ GIMT_Encode4(194293), // Rule ID 1109 //
      // MIs[0] ordering
      GIM_CheckIsImm, /*MI*/0, /*Op*/0,
      // MIs[0] scope
      GIM_CheckIsImm, /*MI*/0, /*Op*/1,
      // (atomic_fence (timm:{ *:[i32] }):$ordering, (timm:{ *:[i32] }):$scope)  =>  (ATOMIC_FENCE (timm:{ *:[i32] }):$ordering, (timm:{ *:[i32] }):$scope)
      GIR_MutateOpcode, /*InsnID*/0, /*RecycleInsnID*/0, /*Opcode*/GIMT_Encode2(AMDGPU::ATOMIC_FENCE),
      GIR_ConstrainSelectedInstOperands, /*InsnID*/0,
      // GIR_Coverage, 1109,
      GIR_Done,
    // Label 3028: @194293
    GIM_Reject,
    // Label 31: @194294
    GIM_Try, /*On fail goto*//*Label 3029*/ GIMT_Encode4(194761),
      GIM_CheckCxxInsnPredicate, /*MI*/0, /*FnId*/GIMT_Encode2(GICXXPred_MI_Predicate_smrd_prefetch),
      GIM_Try, /*On fail goto*//*Label 3030*/ GIMT_Encode4(194420),
        GIM_CheckPointerToAny, /*MI*/0, /*Op*/0, /*SizeInBits*/0,
        GIM_CheckIsImm, /*MI*/0, /*Op*/1,
        GIM_CheckIsImm, /*MI*/0, /*Op*/2,
        GIM_CheckIsImm, /*MI*/0, /*Op*/3,
        GIM_Try, /*On fail goto*//*Label 3031*/ GIMT_Encode4(194370), // Rule ID 2739 //
          GIM_CheckImmOperandPredicate, /*MI*/0, /*MO*/3, /*Predicate*/GIMT_Encode2(GICXXPred_I64_Predicate_i32imm_zero),
          GIM_CheckComplexPattern, /*MI*/0, /*Op*/0, /*Renderer*/GIMT_Encode2(0), GIMT_Encode2(GICP_gi_smrd_imm),
          // (prefetch (SMRDImm:{ *:[iPTR] } i64:{ *:[i64] }:$sbase, i32:{ *:[i32] }:$offset), (timm:{ *:[i32] }), (timm:{ *:[i32] }), (timm:{ *:[i32] })<<P:Predicate_i32imm_zero>>)<<P:Predicate_smrd_prefetch>>  =>  (S_PREFETCH_INST ?:{ *:[i64] }:$sbase, ?:{ *:[i32] }:$offset, SGPR_NULL:{ *:[i32] }, 0:{ *:[i8] })
          GIR_BuildMI, /*InsnID*/0, /*Opcode*/GIMT_Encode2(AMDGPU::S_PREFETCH_INST),
          GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/0, // sbase
          GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/1, // offset
          GIR_AddRegister, /*InsnID*/0, GIMT_Encode2(AMDGPU::SGPR_NULL), /*AddRegisterRegFlags*/GIMT_Encode2(0),
          GIR_AddImm8, /*InsnID*/0, /*Imm*/0,
          GIR_MergeMemOperands, /*InsnID*/0, /*NumInsns*/1, /*MergeInsnID's*/0,
          GIR_ConstrainSelectedInstOperands, /*InsnID*/0,
          GIR_EraseFromParent, /*InsnID*/0,
          // GIR_Coverage, 2739,
          GIR_Done,
        // Label 3031: @194370
        GIM_Try, /*On fail goto*//*Label 3032*/ GIMT_Encode4(194419), // Rule ID 2742 //
          GIM_CheckImmOperandPredicate, /*MI*/0, /*MO*/3, /*Predicate*/GIMT_Encode2(GICXXPred_I64_Predicate_i32imm_one),
          GIM_CheckComplexPattern, /*MI*/0, /*Op*/0, /*Renderer*/GIMT_Encode2(0), GIMT_Encode2(GICP_gi_smrd_imm),
          // (prefetch (SMRDImm:{ *:[iPTR] } i64:{ *:[i64] }:$sbase, i32:{ *:[i32] }:$offset), (timm:{ *:[i32] }), (timm:{ *:[i32] }), (timm:{ *:[i32] })<<P:Predicate_i32imm_one>>)<<P:Predicate_smrd_prefetch>>  =>  (S_PREFETCH_DATA ?:{ *:[i64] }:$sbase, ?:{ *:[i32] }:$offset, SGPR_NULL:{ *:[i32] }, 0:{ *:[i8] })
          GIR_BuildMI, /*InsnID*/0, /*Opcode*/GIMT_Encode2(AMDGPU::S_PREFETCH_DATA),
          GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/0, // sbase
          GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/1, // offset
          GIR_AddRegister, /*InsnID*/0, GIMT_Encode2(AMDGPU::SGPR_NULL), /*AddRegisterRegFlags*/GIMT_Encode2(0),
          GIR_AddImm8, /*InsnID*/0, /*Imm*/0,
          GIR_MergeMemOperands, /*InsnID*/0, /*NumInsns*/1, /*MergeInsnID's*/0,
          GIR_ConstrainSelectedInstOperands, /*InsnID*/0,
          GIR_EraseFromParent, /*InsnID*/0,
          // GIR_Coverage, 2742,
          GIR_Done,
        // Label 3032: @194419
        GIM_Reject,
      // Label 3030: @194420
      GIM_Try, /*On fail goto*//*Label 3033*/ GIMT_Encode4(194477), // Rule ID 2740 //
        // MIs[0] sbase
        GIM_CheckPointerToAny, /*MI*/0, /*Op*/0, /*SizeInBits*/64,
        GIM_CheckRegBankForClass, /*MI*/0, /*Op*/0, /*RC*/GIMT_Encode2(AMDGPU::SReg_64RegClassID),
        // MIs[0] Operand 1
        GIM_CheckIsImm, /*MI*/0, /*Op*/1,
        // MIs[0] Operand 2
        GIM_CheckIsImm, /*MI*/0, /*Op*/2,
        // MIs[0] Operand 3
        GIM_CheckIsImm, /*MI*/0, /*Op*/3,
        GIM_CheckImmOperandPredicate, /*MI*/0, /*MO*/3, /*Predicate*/GIMT_Encode2(GICXXPred_I64_Predicate_i32imm_zero),
        // (prefetch SReg_64:{ *:[i64] }:$sbase, (timm:{ *:[i32] }), (timm:{ *:[i32] }), (timm:{ *:[i32] })<<P:Predicate_i32imm_zero>>)<<P:Predicate_smrd_prefetch>>  =>  (S_PREFETCH_INST ?:{ *:[i64] }:$sbase, 0:{ *:[i32] }, SGPR_NULL:{ *:[i32] }, 0:{ *:[i8] })
        GIR_BuildMI, /*InsnID*/0, /*Opcode*/GIMT_Encode2(AMDGPU::S_PREFETCH_INST),
        GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/0, // sbase
        GIR_AddImm8, /*InsnID*/0, /*Imm*/0,
        GIR_AddRegister, /*InsnID*/0, GIMT_Encode2(AMDGPU::SGPR_NULL), /*AddRegisterRegFlags*/GIMT_Encode2(0),
        GIR_AddImm8, /*InsnID*/0, /*Imm*/0,
        GIR_MergeMemOperands, /*InsnID*/0, /*NumInsns*/1, /*MergeInsnID's*/0,
        GIR_ConstrainSelectedInstOperands, /*InsnID*/0,
        GIR_EraseFromParent, /*InsnID*/0,
        // GIR_Coverage, 2740,
        GIR_Done,
      // Label 3033: @194477
      GIM_Try, /*On fail goto*//*Label 3034*/ GIMT_Encode4(194590), // Rule ID 2741 //
        // MIs[0] sbase
        GIM_CheckPointerToAny, /*MI*/0, /*Op*/0, /*SizeInBits*/32,
        GIM_CheckRegBankForClass, /*MI*/0, /*Op*/0, /*RC*/GIMT_Encode2(AMDGPU::SReg_32RegClassID),
        // MIs[0] Operand 1
        GIM_CheckIsImm, /*MI*/0, /*Op*/1,
        // MIs[0] Operand 2
        GIM_CheckIsImm, /*MI*/0, /*Op*/2,
        // MIs[0] Operand 3
        GIM_CheckIsImm, /*MI*/0, /*Op*/3,
        GIM_CheckImmOperandPredicate, /*MI*/0, /*MO*/3, /*Predicate*/GIMT_Encode2(GICXXPred_I64_Predicate_i32imm_zero),
        // (prefetch SReg_32:{ *:[i32] }:$sbase, (timm:{ *:[i32] }), (timm:{ *:[i32] }), (timm:{ *:[i32] })<<P:Predicate_i32imm_zero>>)<<P:Predicate_smrd_prefetch>>  =>  (S_PREFETCH_INST (REG_SEQUENCE:{ *:[i64] } SReg_64:{ *:[i32] }, ?:{ *:[i32] }:$sbase, sub0:{ *:[i32] }, (S_MOV_B32:{ *:[i32] } 0:{ *:[i32] }), sub1:{ *:[i32] }), 0:{ *:[i32] }, SGPR_NULL:{ *:[i32] }, 0:{ *:[i8] })
        GIR_MakeTempReg, /*TempRegID*/0, /*TypeID*/GILLT_s64,
        GIR_MakeTempReg, /*TempRegID*/1, /*TypeID*/GILLT_s32,
        GIR_BuildMI, /*InsnID*/2, /*Opcode*/GIMT_Encode2(AMDGPU::S_MOV_B32),
        GIR_AddTempRegister, /*InsnID*/2, /*TempRegID*/1, /*TempRegFlags*/GIMT_Encode2(RegState::Define),
        GIR_AddImm8, /*InsnID*/2, /*Imm*/0,
        GIR_ConstrainSelectedInstOperands, /*InsnID*/2,
        GIR_BuildMI, /*InsnID*/1, /*Opcode*/GIMT_Encode2(TargetOpcode::REG_SEQUENCE),
        GIR_AddTempRegister, /*InsnID*/1, /*TempRegID*/0, /*TempRegFlags*/GIMT_Encode2(RegState::Define),
        GIR_Copy, /*NewInsnID*/1, /*OldInsnID*/0, /*OpIdx*/0, // sbase
        GIR_AddImm8, /*InsnID*/1, /*SubRegIndex*/3,
        GIR_AddSimpleTempRegister, /*InsnID*/1, /*TempRegID*/1,
        GIR_AddImm8, /*InsnID*/1, /*SubRegIndex*/11,
        GIR_ConstrainOperandRC, /*InsnID*/1, /*Op*/0, GIMT_Encode2(AMDGPU::SReg_64RegClassID),
        GIR_ConstrainOperandRC, /*InsnID*/1, /*Op*/1, GIMT_Encode2(AMDGPU::SReg_32_XEXEC_HI_and_SReg_32_XM0RegClassID),
        GIR_ConstrainOperandRC, /*InsnID*/1, /*Op*/3, GIMT_Encode2(AMDGPU::SReg_32_XM0RegClassID),
        GIR_BuildMI, /*InsnID*/0, /*Opcode*/GIMT_Encode2(AMDGPU::S_PREFETCH_INST),
        GIR_AddSimpleTempRegister, /*InsnID*/0, /*TempRegID*/0,
        GIR_AddImm8, /*InsnID*/0, /*Imm*/0,
        GIR_AddRegister, /*InsnID*/0, GIMT_Encode2(AMDGPU::SGPR_NULL), /*AddRegisterRegFlags*/GIMT_Encode2(0),
        GIR_AddImm8, /*InsnID*/0, /*Imm*/0,
        GIR_MergeMemOperands, /*InsnID*/0, /*NumInsns*/1, /*MergeInsnID's*/0,
        GIR_ConstrainSelectedInstOperands, /*InsnID*/0,
        GIR_EraseFromParent, /*InsnID*/0,
        // GIR_Coverage, 2741,
        GIR_Done,
      // Label 3034: @194590
      GIM_Try, /*On fail goto*//*Label 3035*/ GIMT_Encode4(194647), // Rule ID 2743 //
        // MIs[0] sbase
        GIM_CheckPointerToAny, /*MI*/0, /*Op*/0, /*SizeInBits*/64,
        GIM_CheckRegBankForClass, /*MI*/0, /*Op*/0, /*RC*/GIMT_Encode2(AMDGPU::SReg_64RegClassID),
        // MIs[0] Operand 1
        GIM_CheckIsImm, /*MI*/0, /*Op*/1,
        // MIs[0] Operand 2
        GIM_CheckIsImm, /*MI*/0, /*Op*/2,
        // MIs[0] Operand 3
        GIM_CheckIsImm, /*MI*/0, /*Op*/3,
        GIM_CheckImmOperandPredicate, /*MI*/0, /*MO*/3, /*Predicate*/GIMT_Encode2(GICXXPred_I64_Predicate_i32imm_one),
        // (prefetch SReg_64:{ *:[i64] }:$sbase, (timm:{ *:[i32] }), (timm:{ *:[i32] }), (timm:{ *:[i32] })<<P:Predicate_i32imm_one>>)<<P:Predicate_smrd_prefetch>>  =>  (S_PREFETCH_DATA ?:{ *:[i64] }:$sbase, 0:{ *:[i32] }, SGPR_NULL:{ *:[i32] }, 0:{ *:[i8] })
        GIR_BuildMI, /*InsnID*/0, /*Opcode*/GIMT_Encode2(AMDGPU::S_PREFETCH_DATA),
        GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/0, // sbase
        GIR_AddImm8, /*InsnID*/0, /*Imm*/0,
        GIR_AddRegister, /*InsnID*/0, GIMT_Encode2(AMDGPU::SGPR_NULL), /*AddRegisterRegFlags*/GIMT_Encode2(0),
        GIR_AddImm8, /*InsnID*/0, /*Imm*/0,
        GIR_MergeMemOperands, /*InsnID*/0, /*NumInsns*/1, /*MergeInsnID's*/0,
        GIR_ConstrainSelectedInstOperands, /*InsnID*/0,
        GIR_EraseFromParent, /*InsnID*/0,
        // GIR_Coverage, 2743,
        GIR_Done,
      // Label 3035: @194647
      GIM_Try, /*On fail goto*//*Label 3036*/ GIMT_Encode4(194760), // Rule ID 2744 //
        // MIs[0] sbase
        GIM_CheckPointerToAny, /*MI*/0, /*Op*/0, /*SizeInBits*/32,
        GIM_CheckRegBankForClass, /*MI*/0, /*Op*/0, /*RC*/GIMT_Encode2(AMDGPU::SReg_32RegClassID),
        // MIs[0] Operand 1
        GIM_CheckIsImm, /*MI*/0, /*Op*/1,
        // MIs[0] Operand 2
        GIM_CheckIsImm, /*MI*/0, /*Op*/2,
        // MIs[0] Operand 3
        GIM_CheckIsImm, /*MI*/0, /*Op*/3,
        GIM_CheckImmOperandPredicate, /*MI*/0, /*MO*/3, /*Predicate*/GIMT_Encode2(GICXXPred_I64_Predicate_i32imm_one),
        // (prefetch SReg_32:{ *:[i32] }:$sbase, (timm:{ *:[i32] }), (timm:{ *:[i32] }), (timm:{ *:[i32] })<<P:Predicate_i32imm_one>>)<<P:Predicate_smrd_prefetch>>  =>  (S_PREFETCH_DATA (REG_SEQUENCE:{ *:[i64] } SReg_64:{ *:[i32] }, ?:{ *:[i32] }:$sbase, sub0:{ *:[i32] }, (S_MOV_B32:{ *:[i32] } 0:{ *:[i32] }), sub1:{ *:[i32] }), 0:{ *:[i32] }, SGPR_NULL:{ *:[i32] }, 0:{ *:[i8] })
        GIR_MakeTempReg, /*TempRegID*/0, /*TypeID*/GILLT_s64,
        GIR_MakeTempReg, /*TempRegID*/1, /*TypeID*/GILLT_s32,
        GIR_BuildMI, /*InsnID*/2, /*Opcode*/GIMT_Encode2(AMDGPU::S_MOV_B32),
        GIR_AddTempRegister, /*InsnID*/2, /*TempRegID*/1, /*TempRegFlags*/GIMT_Encode2(RegState::Define),
        GIR_AddImm8, /*InsnID*/2, /*Imm*/0,
        GIR_ConstrainSelectedInstOperands, /*InsnID*/2,
        GIR_BuildMI, /*InsnID*/1, /*Opcode*/GIMT_Encode2(TargetOpcode::REG_SEQUENCE),
        GIR_AddTempRegister, /*InsnID*/1, /*TempRegID*/0, /*TempRegFlags*/GIMT_Encode2(RegState::Define),
        GIR_Copy, /*NewInsnID*/1, /*OldInsnID*/0, /*OpIdx*/0, // sbase
        GIR_AddImm8, /*InsnID*/1, /*SubRegIndex*/3,
        GIR_AddSimpleTempRegister, /*InsnID*/1, /*TempRegID*/1,
        GIR_AddImm8, /*InsnID*/1, /*SubRegIndex*/11,
        GIR_ConstrainOperandRC, /*InsnID*/1, /*Op*/0, GIMT_Encode2(AMDGPU::SReg_64RegClassID),
        GIR_ConstrainOperandRC, /*InsnID*/1, /*Op*/1, GIMT_Encode2(AMDGPU::SReg_32_XEXEC_HI_and_SReg_32_XM0RegClassID),
        GIR_ConstrainOperandRC, /*InsnID*/1, /*Op*/3, GIMT_Encode2(AMDGPU::SReg_32_XM0RegClassID),
        GIR_BuildMI, /*InsnID*/0, /*Opcode*/GIMT_Encode2(AMDGPU::S_PREFETCH_DATA),
        GIR_AddSimpleTempRegister, /*InsnID*/0, /*TempRegID*/0,
        GIR_AddImm8, /*InsnID*/0, /*Imm*/0,
        GIR_AddRegister, /*InsnID*/0, GIMT_Encode2(AMDGPU::SGPR_NULL), /*AddRegisterRegFlags*/GIMT_Encode2(0),
        GIR_AddImm8, /*InsnID*/0, /*Imm*/0,
        GIR_MergeMemOperands, /*InsnID*/0, /*NumInsns*/1, /*MergeInsnID's*/0,
        GIR_ConstrainSelectedInstOperands, /*InsnID*/0,
        GIR_EraseFromParent, /*InsnID*/0,
        // GIR_Coverage, 2744,
        GIR_Done,
      // Label 3036: @194760
      GIM_Reject,
    // Label 3029: @194761
    GIM_Reject,
    // Label 32: @194762
    GIM_Try, /*On fail goto*//*Label 3037*/ GIMT_Encode4(194867),
      GIM_CheckNumOperands, /*MI*/0, /*Expected*/2,
      GIM_Try, /*On fail goto*//*Label 3038*/ GIMT_Encode4(194802), // Rule ID 20 //
        GIM_CheckIntrinsicID, /*MI*/0, /*Op*/1, GIMT_Encode2(Intrinsic::amdgcn_s_getpc),
        GIM_CheckType, /*MI*/0, /*Op*/0, /*Type*/GILLT_s64,
        GIM_CheckRegBankForClass, /*MI*/0, /*Op*/0, /*RC*/GIMT_Encode2(AMDGPU::SReg_64RegClassID),
        // (intrinsic_wo_chain:{ *:[i64] } 2673:{ *:[iPTR] })  =>  (S_GETPC_B64_pseudo:{ *:[i64] })
        GIR_BuildMI, /*InsnID*/0, /*Opcode*/GIMT_Encode2(AMDGPU::S_GETPC_B64_pseudo),
        GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/0, // DstI[sdst]
        GIR_ConstrainSelectedInstOperands, /*InsnID*/0,
        GIR_EraseFromParent, /*InsnID*/0,
        // GIR_Coverage, 20,
        GIR_Done,
      // Label 3038: @194802
      GIM_Try, /*On fail goto*//*Label 3039*/ GIMT_Encode4(194834), // Rule ID 1121 //
        GIM_CheckIntrinsicID, /*MI*/0, /*Op*/1, GIMT_Encode2(Intrinsic::amdgcn_groupstaticsize),
        GIM_CheckType, /*MI*/0, /*Op*/0, /*Type*/GILLT_s32,
        GIM_CheckRegBankForClass, /*MI*/0, /*Op*/0, /*RC*/GIMT_Encode2(AMDGPU::SReg_32RegClassID),
        // (intrinsic_wo_chain:{ *:[i32] } 1987:{ *:[iPTR] })  =>  (GET_GROUPSTATICSIZE:{ *:[i32] })
        GIR_BuildMI, /*InsnID*/0, /*Opcode*/GIMT_Encode2(AMDGPU::GET_GROUPSTATICSIZE),
        GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/0, // DstI[sdst]
        GIR_ConstrainSelectedInstOperands, /*InsnID*/0,
        GIR_EraseFromParent, /*InsnID*/0,
        // GIR_Coverage, 1121,
        GIR_Done,
      // Label 3039: @194834
      GIM_Try, /*On fail goto*//*Label 3040*/ GIMT_Encode4(194866), // Rule ID 1129 //
        GIM_CheckIntrinsicID, /*MI*/0, /*Op*/1, GIMT_Encode2(Intrinsic::amdgcn_ps_live),
        GIM_CheckType, /*MI*/0, /*Op*/0, /*Type*/GILLT_s1,
        GIM_CheckRegBankForClass, /*MI*/0, /*Op*/0, /*RC*/GIMT_Encode2(AMDGPU::SReg_1RegClassID),
        // (intrinsic_wo_chain:{ *:[i1] } 2594:{ *:[iPTR] })  =>  (SI_PS_LIVE:{ *:[i1] })
        GIR_BuildMI, /*InsnID*/0, /*Opcode*/GIMT_Encode2(AMDGPU::SI_PS_LIVE),
        GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/0, // DstI[dst]
        GIR_ConstrainSelectedInstOperands, /*InsnID*/0,
        GIR_EraseFromParent, /*InsnID*/0,
        // GIR_Coverage, 1129,
        GIR_Done,
      // Label 3040: @194866
      GIM_Reject,
    // Label 3037: @194867
    GIM_Try, /*On fail goto*//*Label 3041*/ GIMT_Encode4(199015),
      GIM_CheckNumOperands, /*MI*/0, /*Expected*/3,
      GIM_Try, /*On fail goto*//*Label 3042*/ GIMT_Encode4(194965), // Rule ID 2226 //
        GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasPseudoScalarTrans),
        GIM_CheckIntrinsicID, /*MI*/0, /*Op*/1, GIMT_Encode2(Intrinsic::amdgcn_exp2),
        GIM_CheckType, /*MI*/0, /*Op*/0, /*Type*/GILLT_s16,
        GIM_CheckType, /*MI*/0, /*Op*/2, /*Type*/GILLT_s16,
        GIM_CheckRegBankForClass, /*MI*/0, /*Op*/0, /*RC*/GIMT_Encode2(AMDGPU::SReg_32_XEXECRegClassID),
        GIM_CheckCxxInsnPredicate, /*MI*/0, /*FnId*/GIMT_Encode2(GICXXPred_MI_Predicate_anonymous_23778),
        GIM_CheckComplexPattern, /*MI*/0, /*Op*/2, /*Renderer*/GIMT_Encode2(0), GIMT_Encode2(GICP_gi_vop3mods0),
        // (intrinsic_wo_chain:{ *:[f16] } 1957:{ *:[iPTR] }, (VOP3Mods0:{ *:[f16] } f16:{ *:[f16] }:$src0, i32:{ *:[i32] }:$src0_modifiers, i1:{ *:[i1] }:$clamp, i32:{ *:[i32] }:$omod))<<P:Predicate_anonymous_23778>>  =>  (COPY_TO_REGCLASS:{ *:[f16] } (V_S_EXP_F16_e64:{ *:[f32] } i32:{ *:[i32] }:$src0_modifiers, f16:{ *:[f16] }:$src0, i1:{ *:[i1] }:$clamp, i32:{ *:[i32] }:$omod), SReg_32_XEXEC:{ *:[i32] })
        GIR_MakeTempReg, /*TempRegID*/0, /*TypeID*/GILLT_s32,
        GIR_BuildMI, /*InsnID*/1, /*Opcode*/GIMT_Encode2(AMDGPU::V_S_EXP_F16_e64),
        GIR_AddTempRegister, /*InsnID*/1, /*TempRegID*/0, /*TempRegFlags*/GIMT_Encode2(RegState::Define),
        GIR_ComplexSubOperandRenderer, /*InsnID*/1, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/1, // src0_modifiers
        GIR_ComplexSubOperandRenderer, /*InsnID*/1, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/0, // src0
        GIR_ComplexSubOperandRenderer, /*InsnID*/1, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/2, // clamp
        GIR_ComplexSubOperandRenderer, /*InsnID*/1, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/3, // omod
        GIR_ConstrainSelectedInstOperands, /*InsnID*/1,
        GIR_BuildMI, /*InsnID*/0, /*Opcode*/GIMT_Encode2(TargetOpcode::COPY),
        GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/0, // DstI[dst]
        GIR_AddSimpleTempRegister, /*InsnID*/0, /*TempRegID*/0,
        GIR_ConstrainOperandRC, /*InsnID*/0, /*Op*/0, GIMT_Encode2(AMDGPU::SReg_32_XEXECRegClassID),
        GIR_EraseFromParent, /*InsnID*/0,
        // GIR_Coverage, 2226,
        GIR_Done,
      // Label 3042: @194965
      GIM_Try, /*On fail goto*//*Label 3043*/ GIMT_Encode4(195055), // Rule ID 2228 //
        GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasPseudoScalarTrans),
        GIM_CheckIntrinsicID, /*MI*/0, /*Op*/1, GIMT_Encode2(Intrinsic::amdgcn_log),
        GIM_CheckType, /*MI*/0, /*Op*/0, /*Type*/GILLT_s16,
        GIM_CheckType, /*MI*/0, /*Op*/2, /*Type*/GILLT_s16,
        GIM_CheckRegBankForClass, /*MI*/0, /*Op*/0, /*RC*/GIMT_Encode2(AMDGPU::SReg_32_XEXECRegClassID),
        GIM_CheckCxxInsnPredicate, /*MI*/0, /*FnId*/GIMT_Encode2(GICXXPred_MI_Predicate_anonymous_23780),
        GIM_CheckComplexPattern, /*MI*/0, /*Op*/2, /*Renderer*/GIMT_Encode2(0), GIMT_Encode2(GICP_gi_vop3mods0),
        // (intrinsic_wo_chain:{ *:[f16] } 2534:{ *:[iPTR] }, (VOP3Mods0:{ *:[f16] } f16:{ *:[f16] }:$src0, i32:{ *:[i32] }:$src0_modifiers, i1:{ *:[i1] }:$clamp, i32:{ *:[i32] }:$omod))<<P:Predicate_anonymous_23780>>  =>  (COPY_TO_REGCLASS:{ *:[f16] } (V_S_LOG_F16_e64:{ *:[f32] } i32:{ *:[i32] }:$src0_modifiers, f16:{ *:[f16] }:$src0, i1:{ *:[i1] }:$clamp, i32:{ *:[i32] }:$omod), SReg_32_XEXEC:{ *:[i32] })
        GIR_MakeTempReg, /*TempRegID*/0, /*TypeID*/GILLT_s32,
        GIR_BuildMI, /*InsnID*/1, /*Opcode*/GIMT_Encode2(AMDGPU::V_S_LOG_F16_e64),
        GIR_AddTempRegister, /*InsnID*/1, /*TempRegID*/0, /*TempRegFlags*/GIMT_Encode2(RegState::Define),
        GIR_ComplexSubOperandRenderer, /*InsnID*/1, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/1, // src0_modifiers
        GIR_ComplexSubOperandRenderer, /*InsnID*/1, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/0, // src0
        GIR_ComplexSubOperandRenderer, /*InsnID*/1, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/2, // clamp
        GIR_ComplexSubOperandRenderer, /*InsnID*/1, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/3, // omod
        GIR_ConstrainSelectedInstOperands, /*InsnID*/1,
        GIR_BuildMI, /*InsnID*/0, /*Opcode*/GIMT_Encode2(TargetOpcode::COPY),
        GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/0, // DstI[dst]
        GIR_AddSimpleTempRegister, /*InsnID*/0, /*TempRegID*/0,
        GIR_ConstrainOperandRC, /*InsnID*/0, /*Op*/0, GIMT_Encode2(AMDGPU::SReg_32_XEXECRegClassID),
        GIR_EraseFromParent, /*InsnID*/0,
        // GIR_Coverage, 2228,
        GIR_Done,
      // Label 3043: @195055
      GIM_Try, /*On fail goto*//*Label 3044*/ GIMT_Encode4(195145), // Rule ID 2230 //
        GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasPseudoScalarTrans),
        GIM_CheckIntrinsicID, /*MI*/0, /*Op*/1, GIMT_Encode2(Intrinsic::amdgcn_rcp),
        GIM_CheckType, /*MI*/0, /*Op*/0, /*Type*/GILLT_s16,
        GIM_CheckType, /*MI*/0, /*Op*/2, /*Type*/GILLT_s16,
        GIM_CheckRegBankForClass, /*MI*/0, /*Op*/0, /*RC*/GIMT_Encode2(AMDGPU::SReg_32_XEXECRegClassID),
        GIM_CheckCxxInsnPredicate, /*MI*/0, /*FnId*/GIMT_Encode2(GICXXPred_MI_Predicate_anonymous_23772),
        GIM_CheckComplexPattern, /*MI*/0, /*Op*/2, /*Renderer*/GIMT_Encode2(0), GIMT_Encode2(GICP_gi_vop3mods0),
        // (intrinsic_wo_chain:{ *:[f16] } 2647:{ *:[iPTR] }, (VOP3Mods0:{ *:[f16] } f16:{ *:[f16] }:$src0, i32:{ *:[i32] }:$src0_modifiers, i1:{ *:[i1] }:$clamp, i32:{ *:[i32] }:$omod))<<P:Predicate_anonymous_23772>>  =>  (COPY_TO_REGCLASS:{ *:[f16] } (V_S_RCP_F16_e64:{ *:[f32] } i32:{ *:[i32] }:$src0_modifiers, f16:{ *:[f16] }:$src0, i1:{ *:[i1] }:$clamp, i32:{ *:[i32] }:$omod), SReg_32_XEXEC:{ *:[i32] })
        GIR_MakeTempReg, /*TempRegID*/0, /*TypeID*/GILLT_s32,
        GIR_BuildMI, /*InsnID*/1, /*Opcode*/GIMT_Encode2(AMDGPU::V_S_RCP_F16_e64),
        GIR_AddTempRegister, /*InsnID*/1, /*TempRegID*/0, /*TempRegFlags*/GIMT_Encode2(RegState::Define),
        GIR_ComplexSubOperandRenderer, /*InsnID*/1, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/1, // src0_modifiers
        GIR_ComplexSubOperandRenderer, /*InsnID*/1, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/0, // src0
        GIR_ComplexSubOperandRenderer, /*InsnID*/1, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/2, // clamp
        GIR_ComplexSubOperandRenderer, /*InsnID*/1, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/3, // omod
        GIR_ConstrainSelectedInstOperands, /*InsnID*/1,
        GIR_BuildMI, /*InsnID*/0, /*Opcode*/GIMT_Encode2(TargetOpcode::COPY),
        GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/0, // DstI[dst]
        GIR_AddSimpleTempRegister, /*InsnID*/0, /*TempRegID*/0,
        GIR_ConstrainOperandRC, /*InsnID*/0, /*Op*/0, GIMT_Encode2(AMDGPU::SReg_32_XEXECRegClassID),
        GIR_EraseFromParent, /*InsnID*/0,
        // GIR_Coverage, 2230,
        GIR_Done,
      // Label 3044: @195145
      GIM_Try, /*On fail goto*//*Label 3045*/ GIMT_Encode4(195235), // Rule ID 2232 //
        GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasPseudoScalarTrans),
        GIM_CheckIntrinsicID, /*MI*/0, /*Op*/1, GIMT_Encode2(Intrinsic::amdgcn_rsq),
        GIM_CheckType, /*MI*/0, /*Op*/0, /*Type*/GILLT_s16,
        GIM_CheckType, /*MI*/0, /*Op*/2, /*Type*/GILLT_s16,
        GIM_CheckRegBankForClass, /*MI*/0, /*Op*/0, /*RC*/GIMT_Encode2(AMDGPU::SReg_32_XEXECRegClassID),
        GIM_CheckCxxInsnPredicate, /*MI*/0, /*FnId*/GIMT_Encode2(GICXXPred_MI_Predicate_anonymous_23774),
        GIM_CheckComplexPattern, /*MI*/0, /*Op*/2, /*Renderer*/GIMT_Encode2(0), GIMT_Encode2(GICP_gi_vop3mods0),
        // (intrinsic_wo_chain:{ *:[f16] } 2652:{ *:[iPTR] }, (VOP3Mods0:{ *:[f16] } f16:{ *:[f16] }:$src0, i32:{ *:[i32] }:$src0_modifiers, i1:{ *:[i1] }:$clamp, i32:{ *:[i32] }:$omod))<<P:Predicate_anonymous_23774>>  =>  (COPY_TO_REGCLASS:{ *:[f16] } (V_S_RSQ_F16_e64:{ *:[f32] } i32:{ *:[i32] }:$src0_modifiers, f16:{ *:[f16] }:$src0, i1:{ *:[i1] }:$clamp, i32:{ *:[i32] }:$omod), SReg_32_XEXEC:{ *:[i32] })
        GIR_MakeTempReg, /*TempRegID*/0, /*TypeID*/GILLT_s32,
        GIR_BuildMI, /*InsnID*/1, /*Opcode*/GIMT_Encode2(AMDGPU::V_S_RSQ_F16_e64),
        GIR_AddTempRegister, /*InsnID*/1, /*TempRegID*/0, /*TempRegFlags*/GIMT_Encode2(RegState::Define),
        GIR_ComplexSubOperandRenderer, /*InsnID*/1, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/1, // src0_modifiers
        GIR_ComplexSubOperandRenderer, /*InsnID*/1, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/0, // src0
        GIR_ComplexSubOperandRenderer, /*InsnID*/1, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/2, // clamp
        GIR_ComplexSubOperandRenderer, /*InsnID*/1, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/3, // omod
        GIR_ConstrainSelectedInstOperands, /*InsnID*/1,
        GIR_BuildMI, /*InsnID*/0, /*Opcode*/GIMT_Encode2(TargetOpcode::COPY),
        GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/0, // DstI[dst]
        GIR_AddSimpleTempRegister, /*InsnID*/0, /*TempRegID*/0,
        GIR_ConstrainOperandRC, /*InsnID*/0, /*Op*/0, GIMT_Encode2(AMDGPU::SReg_32_XEXECRegClassID),
        GIR_EraseFromParent, /*InsnID*/0,
        // GIR_Coverage, 2232,
        GIR_Done,
      // Label 3045: @195235
      GIM_Try, /*On fail goto*//*Label 3046*/ GIMT_Encode4(195325), // Rule ID 2235 //
        GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasPseudoScalarTrans),
        GIM_CheckIntrinsicID, /*MI*/0, /*Op*/1, GIMT_Encode2(Intrinsic::amdgcn_sqrt),
        GIM_CheckType, /*MI*/0, /*Op*/0, /*Type*/GILLT_s16,
        GIM_CheckType, /*MI*/0, /*Op*/2, /*Type*/GILLT_s16,
        GIM_CheckRegBankForClass, /*MI*/0, /*Op*/0, /*RC*/GIMT_Encode2(AMDGPU::SReg_32_XEXECRegClassID),
        GIM_CheckCxxInsnPredicate, /*MI*/0, /*FnId*/GIMT_Encode2(GICXXPred_MI_Predicate_anonymous_23776),
        GIM_CheckComplexPattern, /*MI*/0, /*Op*/2, /*Renderer*/GIMT_Encode2(0), GIMT_Encode2(GICP_gi_vop3mods0),
        // (intrinsic_wo_chain:{ *:[f16] } 2729:{ *:[iPTR] }, (VOP3Mods0:{ *:[f16] } f16:{ *:[f16] }:$src0, i32:{ *:[i32] }:$src0_modifiers, i1:{ *:[i1] }:$clamp, i32:{ *:[i32] }:$omod))<<P:Predicate_anonymous_23776>>  =>  (COPY_TO_REGCLASS:{ *:[f16] } (V_S_SQRT_F16_e64:{ *:[f32] } i32:{ *:[i32] }:$src0_modifiers, f16:{ *:[f16] }:$src0, i1:{ *:[i1] }:$clamp, i32:{ *:[i32] }:$omod), SReg_32_XEXEC:{ *:[i32] })
        GIR_MakeTempReg, /*TempRegID*/0, /*TypeID*/GILLT_s32,
        GIR_BuildMI, /*InsnID*/1, /*Opcode*/GIMT_Encode2(AMDGPU::V_S_SQRT_F16_e64),
        GIR_AddTempRegister, /*InsnID*/1, /*TempRegID*/0, /*TempRegFlags*/GIMT_Encode2(RegState::Define),
        GIR_ComplexSubOperandRenderer, /*InsnID*/1, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/1, // src0_modifiers
        GIR_ComplexSubOperandRenderer, /*InsnID*/1, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/0, // src0
        GIR_ComplexSubOperandRenderer, /*InsnID*/1, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/2, // clamp
        GIR_ComplexSubOperandRenderer, /*InsnID*/1, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/3, // omod
        GIR_ConstrainSelectedInstOperands, /*InsnID*/1,
        GIR_BuildMI, /*InsnID*/0, /*Opcode*/GIMT_Encode2(TargetOpcode::COPY),
        GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/0, // DstI[dst]
        GIR_AddSimpleTempRegister, /*InsnID*/0, /*TempRegID*/0,
        GIR_ConstrainOperandRC, /*InsnID*/0, /*Op*/0, GIMT_Encode2(AMDGPU::SReg_32_XEXECRegClassID),
        GIR_EraseFromParent, /*InsnID*/0,
        // GIR_Coverage, 2235,
        GIR_Done,
      // Label 3046: @195325
      GIM_Try, /*On fail goto*//*Label 3047*/ GIMT_Encode4(195369), // Rule ID 16 //
        GIM_CheckIntrinsicID, /*MI*/0, /*Op*/1, GIMT_Encode2(Intrinsic::amdgcn_sffbh),
        GIM_CheckType, /*MI*/0, /*Op*/0, /*Type*/GILLT_s32,
        GIM_CheckType, /*MI*/0, /*Op*/2, /*Type*/GILLT_s32,
        GIM_CheckRegBankForClass, /*MI*/0, /*Op*/0, /*RC*/GIMT_Encode2(AMDGPU::SReg_32RegClassID),
        GIM_CheckCxxInsnPredicate, /*MI*/0, /*FnId*/GIMT_Encode2(GICXXPred_MI_Predicate_anonymous_17571),
        // (intrinsic_wo_chain:{ *:[i32] } 2712:{ *:[iPTR] }, i32:{ *:[i32] }:$src0)<<P:Predicate_anonymous_17571>>  =>  (S_FLBIT_I32:{ *:[i32] } i32:{ *:[i32] }:$src0)
        GIR_BuildMI, /*InsnID*/0, /*Opcode*/GIMT_Encode2(AMDGPU::S_FLBIT_I32),
        GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/0, // DstI[sdst]
        GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/2, // src0
        GIR_ConstrainSelectedInstOperands, /*InsnID*/0,
        GIR_EraseFromParent, /*InsnID*/0,
        // GIR_Coverage, 16,
        GIR_Done,
      // Label 3047: @195369
      GIM_Try, /*On fail goto*//*Label 3048*/ GIMT_Encode4(195439), // Rule ID 948 //
        GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasPseudoScalarTrans),
        GIM_CheckIntrinsicID, /*MI*/0, /*Op*/1, GIMT_Encode2(Intrinsic::amdgcn_exp2),
        GIM_CheckType, /*MI*/0, /*Op*/0, /*Type*/GILLT_s32,
        GIM_CheckType, /*MI*/0, /*Op*/2, /*Type*/GILLT_s32,
        GIM_CheckRegBankForClass, /*MI*/0, /*Op*/0, /*RC*/GIMT_Encode2(AMDGPU::SReg_32_XEXECRegClassID),
        GIM_CheckCxxInsnPredicate, /*MI*/0, /*FnId*/GIMT_Encode2(GICXXPred_MI_Predicate_anonymous_23764),
        GIM_CheckComplexPattern, /*MI*/0, /*Op*/2, /*Renderer*/GIMT_Encode2(0), GIMT_Encode2(GICP_gi_vop3mods0),
        // (intrinsic_wo_chain:{ *:[f32] } 1957:{ *:[iPTR] }, (VOP3Mods0:{ *:[f32] } f32:{ *:[f32] }:$src0, i32:{ *:[i32] }:$src0_modifiers, i1:{ *:[i1] }:$clamp, i32:{ *:[i32] }:$omod))<<P:Predicate_anonymous_23764>>  =>  (V_S_EXP_F32_e64:{ *:[f32] } i32:{ *:[i32] }:$src0_modifiers, f32:{ *:[f32] }:$src0, i1:{ *:[i1] }:$clamp, i32:{ *:[i32] }:$omod)
        GIR_BuildMI, /*InsnID*/0, /*Opcode*/GIMT_Encode2(AMDGPU::V_S_EXP_F32_e64),
        GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/0, // DstI[vdst]
        GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/1, // src0_modifiers
        GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/0, // src0
        GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/2, // clamp
        GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/3, // omod
        GIR_ConstrainSelectedInstOperands, /*InsnID*/0,
        GIR_EraseFromParent, /*InsnID*/0,
        // GIR_Coverage, 948,
        GIR_Done,
      // Label 3048: @195439
      GIM_Try, /*On fail goto*//*Label 3049*/ GIMT_Encode4(195509), // Rule ID 950 //
        GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasPseudoScalarTrans),
        GIM_CheckIntrinsicID, /*MI*/0, /*Op*/1, GIMT_Encode2(Intrinsic::amdgcn_log),
        GIM_CheckType, /*MI*/0, /*Op*/0, /*Type*/GILLT_s32,
        GIM_CheckType, /*MI*/0, /*Op*/2, /*Type*/GILLT_s32,
        GIM_CheckRegBankForClass, /*MI*/0, /*Op*/0, /*RC*/GIMT_Encode2(AMDGPU::SReg_32_XEXECRegClassID),
        GIM_CheckCxxInsnPredicate, /*MI*/0, /*FnId*/GIMT_Encode2(GICXXPred_MI_Predicate_anonymous_23770),
        GIM_CheckComplexPattern, /*MI*/0, /*Op*/2, /*Renderer*/GIMT_Encode2(0), GIMT_Encode2(GICP_gi_vop3mods0),
        // (intrinsic_wo_chain:{ *:[f32] } 2534:{ *:[iPTR] }, (VOP3Mods0:{ *:[f32] } f32:{ *:[f32] }:$src0, i32:{ *:[i32] }:$src0_modifiers, i1:{ *:[i1] }:$clamp, i32:{ *:[i32] }:$omod))<<P:Predicate_anonymous_23770>>  =>  (V_S_LOG_F32_e64:{ *:[f32] } i32:{ *:[i32] }:$src0_modifiers, f32:{ *:[f32] }:$src0, i1:{ *:[i1] }:$clamp, i32:{ *:[i32] }:$omod)
        GIR_BuildMI, /*InsnID*/0, /*Opcode*/GIMT_Encode2(AMDGPU::V_S_LOG_F32_e64),
        GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/0, // DstI[vdst]
        GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/1, // src0_modifiers
        GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/0, // src0
        GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/2, // clamp
        GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/3, // omod
        GIR_ConstrainSelectedInstOperands, /*InsnID*/0,
        GIR_EraseFromParent, /*InsnID*/0,
        // GIR_Coverage, 950,
        GIR_Done,
      // Label 3049: @195509
      GIM_Try, /*On fail goto*//*Label 3050*/ GIMT_Encode4(195579), // Rule ID 952 //
        GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasPseudoScalarTrans),
        GIM_CheckIntrinsicID, /*MI*/0, /*Op*/1, GIMT_Encode2(Intrinsic::amdgcn_rcp),
        GIM_CheckType, /*MI*/0, /*Op*/0, /*Type*/GILLT_s32,
        GIM_CheckType, /*MI*/0, /*Op*/2, /*Type*/GILLT_s32,
        GIM_CheckRegBankForClass, /*MI*/0, /*Op*/0, /*RC*/GIMT_Encode2(AMDGPU::SReg_32_XEXECRegClassID),
        GIM_CheckCxxInsnPredicate, /*MI*/0, /*FnId*/GIMT_Encode2(GICXXPred_MI_Predicate_anonymous_23772),
        GIM_CheckComplexPattern, /*MI*/0, /*Op*/2, /*Renderer*/GIMT_Encode2(0), GIMT_Encode2(GICP_gi_vop3mods0),
        // (intrinsic_wo_chain:{ *:[f32] } 2647:{ *:[iPTR] }, (VOP3Mods0:{ *:[f32] } f32:{ *:[f32] }:$src0, i32:{ *:[i32] }:$src0_modifiers, i1:{ *:[i1] }:$clamp, i32:{ *:[i32] }:$omod))<<P:Predicate_anonymous_23772>>  =>  (V_S_RCP_F32_e64:{ *:[f32] } i32:{ *:[i32] }:$src0_modifiers, f32:{ *:[f32] }:$src0, i1:{ *:[i1] }:$clamp, i32:{ *:[i32] }:$omod)
        GIR_BuildMI, /*InsnID*/0, /*Opcode*/GIMT_Encode2(AMDGPU::V_S_RCP_F32_e64),
        GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/0, // DstI[vdst]
        GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/1, // src0_modifiers
        GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/0, // src0
        GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/2, // clamp
        GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/3, // omod
        GIR_ConstrainSelectedInstOperands, /*InsnID*/0,
        GIR_EraseFromParent, /*InsnID*/0,
        // GIR_Coverage, 952,
        GIR_Done,
      // Label 3050: @195579
      GIM_Try, /*On fail goto*//*Label 3051*/ GIMT_Encode4(195649), // Rule ID 954 //
        GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasPseudoScalarTrans),
        GIM_CheckIntrinsicID, /*MI*/0, /*Op*/1, GIMT_Encode2(Intrinsic::amdgcn_rsq),
        GIM_CheckType, /*MI*/0, /*Op*/0, /*Type*/GILLT_s32,
        GIM_CheckType, /*MI*/0, /*Op*/2, /*Type*/GILLT_s32,
        GIM_CheckRegBankForClass, /*MI*/0, /*Op*/0, /*RC*/GIMT_Encode2(AMDGPU::SReg_32_XEXECRegClassID),
        GIM_CheckCxxInsnPredicate, /*MI*/0, /*FnId*/GIMT_Encode2(GICXXPred_MI_Predicate_anonymous_23774),
        GIM_CheckComplexPattern, /*MI*/0, /*Op*/2, /*Renderer*/GIMT_Encode2(0), GIMT_Encode2(GICP_gi_vop3mods0),
        // (intrinsic_wo_chain:{ *:[f32] } 2652:{ *:[iPTR] }, (VOP3Mods0:{ *:[f32] } f32:{ *:[f32] }:$src0, i32:{ *:[i32] }:$src0_modifiers, i1:{ *:[i1] }:$clamp, i32:{ *:[i32] }:$omod))<<P:Predicate_anonymous_23774>>  =>  (V_S_RSQ_F32_e64:{ *:[f32] } i32:{ *:[i32] }:$src0_modifiers, f32:{ *:[f32] }:$src0, i1:{ *:[i1] }:$clamp, i32:{ *:[i32] }:$omod)
        GIR_BuildMI, /*InsnID*/0, /*Opcode*/GIMT_Encode2(AMDGPU::V_S_RSQ_F32_e64),
        GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/0, // DstI[vdst]
        GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/1, // src0_modifiers
        GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/0, // src0
        GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/2, // clamp
        GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/3, // omod
        GIR_ConstrainSelectedInstOperands, /*InsnID*/0,
        GIR_EraseFromParent, /*InsnID*/0,
        // GIR_Coverage, 954,
        GIR_Done,
      // Label 3051: @195649
      GIM_Try, /*On fail goto*//*Label 3052*/ GIMT_Encode4(195719), // Rule ID 957 //
        GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasPseudoScalarTrans),
        GIM_CheckIntrinsicID, /*MI*/0, /*Op*/1, GIMT_Encode2(Intrinsic::amdgcn_sqrt),
        GIM_CheckType, /*MI*/0, /*Op*/0, /*Type*/GILLT_s32,
        GIM_CheckType, /*MI*/0, /*Op*/2, /*Type*/GILLT_s32,
        GIM_CheckRegBankForClass, /*MI*/0, /*Op*/0, /*RC*/GIMT_Encode2(AMDGPU::SReg_32_XEXECRegClassID),
        GIM_CheckCxxInsnPredicate, /*MI*/0, /*FnId*/GIMT_Encode2(GICXXPred_MI_Predicate_anonymous_23776),
        GIM_CheckComplexPattern, /*MI*/0, /*Op*/2, /*Renderer*/GIMT_Encode2(0), GIMT_Encode2(GICP_gi_vop3mods0),
        // (intrinsic_wo_chain:{ *:[f32] } 2729:{ *:[iPTR] }, (VOP3Mods0:{ *:[f32] } f32:{ *:[f32] }:$src0, i32:{ *:[i32] }:$src0_modifiers, i1:{ *:[i1] }:$clamp, i32:{ *:[i32] }:$omod))<<P:Predicate_anonymous_23776>>  =>  (V_S_SQRT_F32_e64:{ *:[f32] } i32:{ *:[i32] }:$src0_modifiers, f32:{ *:[f32] }:$src0, i1:{ *:[i1] }:$clamp, i32:{ *:[i32] }:$omod)
        GIR_BuildMI, /*InsnID*/0, /*Opcode*/GIMT_Encode2(AMDGPU::V_S_SQRT_F32_e64),
        GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/0, // DstI[vdst]
        GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/1, // src0_modifiers
        GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/0, // src0
        GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/2, // clamp
        GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/3, // omod
        GIR_ConstrainSelectedInstOperands, /*InsnID*/0,
        GIR_EraseFromParent, /*InsnID*/0,
        // GIR_Coverage, 957,
        GIR_Done,
      // Label 3052: @195719
      GIM_Try, /*On fail goto*//*Label 3053*/ GIMT_Encode4(195782), // Rule ID 599 //
        GIM_CheckIntrinsicID, /*MI*/0, /*Op*/1, GIMT_Encode2(Intrinsic::amdgcn_fract),
        GIM_CheckType, /*MI*/0, /*Op*/0, /*Type*/GILLT_s32,
        GIM_CheckType, /*MI*/0, /*Op*/2, /*Type*/GILLT_s32,
        GIM_CheckRegBankForClass, /*MI*/0, /*Op*/0, /*RC*/GIMT_Encode2(AMDGPU::VGPR_32RegClassID),
        GIM_CheckComplexPattern, /*MI*/0, /*Op*/2, /*Renderer*/GIMT_Encode2(0), GIMT_Encode2(GICP_gi_vop3mods0),
        // (intrinsic_wo_chain:{ *:[f32] } 1974:{ *:[iPTR] }, (VOP3Mods0:{ *:[f32] } f32:{ *:[f32] }:$src0, i32:{ *:[i32] }:$src0_modifiers, i1:{ *:[i1] }:$clamp, i32:{ *:[i32] }:$omod))  =>  (V_FRACT_F32_e64:{ *:[f32] } i32:{ *:[i32] }:$src0_modifiers, f32:{ *:[f32] }:$src0, i1:{ *:[i1] }:$clamp, i32:{ *:[i32] }:$omod)
        GIR_BuildMI, /*InsnID*/0, /*Opcode*/GIMT_Encode2(AMDGPU::V_FRACT_F32_e64),
        GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/0, // DstI[vdst]
        GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/1, // src0_modifiers
        GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/0, // src0
        GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/2, // clamp
        GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/3, // omod
        GIR_ConstrainSelectedInstOperands, /*InsnID*/0,
        GIR_EraseFromParent, /*InsnID*/0,
        // GIR_Coverage, 599,
        GIR_Done,
      // Label 3053: @195782
      GIM_Try, /*On fail goto*//*Label 3054*/ GIMT_Encode4(195845), // Rule ID 605 //
        GIM_CheckIntrinsicID, /*MI*/0, /*Op*/1, GIMT_Encode2(Intrinsic::amdgcn_exp2),
        GIM_CheckType, /*MI*/0, /*Op*/0, /*Type*/GILLT_s32,
        GIM_CheckType, /*MI*/0, /*Op*/2, /*Type*/GILLT_s32,
        GIM_CheckRegBankForClass, /*MI*/0, /*Op*/0, /*RC*/GIMT_Encode2(AMDGPU::VGPR_32RegClassID),
        GIM_CheckComplexPattern, /*MI*/0, /*Op*/2, /*Renderer*/GIMT_Encode2(0), GIMT_Encode2(GICP_gi_vop3mods0),
        // (intrinsic_wo_chain:{ *:[f32] } 1957:{ *:[iPTR] }, (VOP3Mods0:{ *:[f32] } f32:{ *:[f32] }:$src0, i32:{ *:[i32] }:$src0_modifiers, i1:{ *:[i1] }:$clamp, i32:{ *:[i32] }:$omod))  =>  (V_EXP_F32_e64:{ *:[f32] } i32:{ *:[i32] }:$src0_modifiers, f32:{ *:[f32] }:$src0, i1:{ *:[i1] }:$clamp, i32:{ *:[i32] }:$omod)
        GIR_BuildMI, /*InsnID*/0, /*Opcode*/GIMT_Encode2(AMDGPU::V_EXP_F32_e64),
        GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/0, // DstI[vdst]
        GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/1, // src0_modifiers
        GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/0, // src0
        GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/2, // clamp
        GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/3, // omod
        GIR_ConstrainSelectedInstOperands, /*InsnID*/0,
        GIR_EraseFromParent, /*InsnID*/0,
        // GIR_Coverage, 605,
        GIR_Done,
      // Label 3054: @195845
      GIM_Try, /*On fail goto*//*Label 3055*/ GIMT_Encode4(195908), // Rule ID 607 //
        GIM_CheckIntrinsicID, /*MI*/0, /*Op*/1, GIMT_Encode2(Intrinsic::amdgcn_log),
        GIM_CheckType, /*MI*/0, /*Op*/0, /*Type*/GILLT_s32,
        GIM_CheckType, /*MI*/0, /*Op*/2, /*Type*/GILLT_s32,
        GIM_CheckRegBankForClass, /*MI*/0, /*Op*/0, /*RC*/GIMT_Encode2(AMDGPU::VGPR_32RegClassID),
        GIM_CheckComplexPattern, /*MI*/0, /*Op*/2, /*Renderer*/GIMT_Encode2(0), GIMT_Encode2(GICP_gi_vop3mods0),
        // (intrinsic_wo_chain:{ *:[f32] } 2534:{ *:[iPTR] }, (VOP3Mods0:{ *:[f32] } f32:{ *:[f32] }:$src0, i32:{ *:[i32] }:$src0_modifiers, i1:{ *:[i1] }:$clamp, i32:{ *:[i32] }:$omod))  =>  (V_LOG_F32_e64:{ *:[f32] } i32:{ *:[i32] }:$src0_modifiers, f32:{ *:[f32] }:$src0, i1:{ *:[i1] }:$clamp, i32:{ *:[i32] }:$omod)
        GIR_BuildMI, /*InsnID*/0, /*Opcode*/GIMT_Encode2(AMDGPU::V_LOG_F32_e64),
        GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/0, // DstI[vdst]
        GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/1, // src0_modifiers
        GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/0, // src0
        GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/2, // clamp
        GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/3, // omod
        GIR_ConstrainSelectedInstOperands, /*InsnID*/0,
        GIR_EraseFromParent, /*InsnID*/0,
        // GIR_Coverage, 607,
        GIR_Done,
      // Label 3055: @195908
      GIM_Try, /*On fail goto*//*Label 3056*/ GIMT_Encode4(195971), // Rule ID 609 //
        GIM_CheckIntrinsicID, /*MI*/0, /*Op*/1, GIMT_Encode2(Intrinsic::amdgcn_rcp),
        GIM_CheckType, /*MI*/0, /*Op*/0, /*Type*/GILLT_s32,
        GIM_CheckType, /*MI*/0, /*Op*/2, /*Type*/GILLT_s32,
        GIM_CheckRegBankForClass, /*MI*/0, /*Op*/0, /*RC*/GIMT_Encode2(AMDGPU::VGPR_32RegClassID),
        GIM_CheckComplexPattern, /*MI*/0, /*Op*/2, /*Renderer*/GIMT_Encode2(0), GIMT_Encode2(GICP_gi_vop3mods0),
        // (intrinsic_wo_chain:{ *:[f32] } 2647:{ *:[iPTR] }, (VOP3Mods0:{ *:[f32] } f32:{ *:[f32] }:$src0, i32:{ *:[i32] }:$src0_modifiers, i1:{ *:[i1] }:$clamp, i32:{ *:[i32] }:$omod))  =>  (V_RCP_F32_e64:{ *:[f32] } i32:{ *:[i32] }:$src0_modifiers, f32:{ *:[f32] }:$src0, i1:{ *:[i1] }:$clamp, i32:{ *:[i32] }:$omod)
        GIR_BuildMI, /*InsnID*/0, /*Opcode*/GIMT_Encode2(AMDGPU::V_RCP_F32_e64),
        GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/0, // DstI[vdst]
        GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/1, // src0_modifiers
        GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/0, // src0
        GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/2, // clamp
        GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/3, // omod
        GIR_ConstrainSelectedInstOperands, /*InsnID*/0,
        GIR_EraseFromParent, /*InsnID*/0,
        // GIR_Coverage, 609,
        GIR_Done,
      // Label 3056: @195971
      GIM_Try, /*On fail goto*//*Label 3057*/ GIMT_Encode4(196034), // Rule ID 612 //
        GIM_CheckIntrinsicID, /*MI*/0, /*Op*/1, GIMT_Encode2(Intrinsic::amdgcn_rsq),
        GIM_CheckType, /*MI*/0, /*Op*/0, /*Type*/GILLT_s32,
        GIM_CheckType, /*MI*/0, /*Op*/2, /*Type*/GILLT_s32,
        GIM_CheckRegBankForClass, /*MI*/0, /*Op*/0, /*RC*/GIMT_Encode2(AMDGPU::VGPR_32RegClassID),
        GIM_CheckComplexPattern, /*MI*/0, /*Op*/2, /*Renderer*/GIMT_Encode2(0), GIMT_Encode2(GICP_gi_vop3mods0),
        // (intrinsic_wo_chain:{ *:[f32] } 2652:{ *:[iPTR] }, (VOP3Mods0:{ *:[f32] } f32:{ *:[f32] }:$src0, i32:{ *:[i32] }:$src0_modifiers, i1:{ *:[i1] }:$clamp, i32:{ *:[i32] }:$omod))  =>  (V_RSQ_F32_e64:{ *:[f32] } i32:{ *:[i32] }:$src0_modifiers, f32:{ *:[f32] }:$src0, i1:{ *:[i1] }:$clamp, i32:{ *:[i32] }:$omod)
        GIR_BuildMI, /*InsnID*/0, /*Opcode*/GIMT_Encode2(AMDGPU::V_RSQ_F32_e64),
        GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/0, // DstI[vdst]
        GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/1, // src0_modifiers
        GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/0, // src0
        GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/2, // clamp
        GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/3, // omod
        GIR_ConstrainSelectedInstOperands, /*InsnID*/0,
        GIR_EraseFromParent, /*InsnID*/0,
        // GIR_Coverage, 612,
        GIR_Done,
      // Label 3057: @196034
      GIM_Try, /*On fail goto*//*Label 3058*/ GIMT_Encode4(196097), // Rule ID 614 //
        GIM_CheckIntrinsicID, /*MI*/0, /*Op*/1, GIMT_Encode2(Intrinsic::amdgcn_sqrt),
        GIM_CheckType, /*MI*/0, /*Op*/0, /*Type*/GILLT_s32,
        GIM_CheckType, /*MI*/0, /*Op*/2, /*Type*/GILLT_s32,
        GIM_CheckRegBankForClass, /*MI*/0, /*Op*/0, /*RC*/GIMT_Encode2(AMDGPU::VGPR_32RegClassID),
        GIM_CheckComplexPattern, /*MI*/0, /*Op*/2, /*Renderer*/GIMT_Encode2(0), GIMT_Encode2(GICP_gi_vop3mods0),
        // (intrinsic_wo_chain:{ *:[f32] } 2729:{ *:[iPTR] }, (VOP3Mods0:{ *:[f32] } f32:{ *:[f32] }:$src0, i32:{ *:[i32] }:$src0_modifiers, i1:{ *:[i1] }:$clamp, i32:{ *:[i32] }:$omod))  =>  (V_SQRT_F32_e64:{ *:[f32] } i32:{ *:[i32] }:$src0_modifiers, f32:{ *:[f32] }:$src0, i1:{ *:[i1] }:$clamp, i32:{ *:[i32] }:$omod)
        GIR_BuildMI, /*InsnID*/0, /*Opcode*/GIMT_Encode2(AMDGPU::V_SQRT_F32_e64),
        GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/0, // DstI[vdst]
        GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/1, // src0_modifiers
        GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/0, // src0
        GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/2, // clamp
        GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/3, // omod
        GIR_ConstrainSelectedInstOperands, /*InsnID*/0,
        GIR_EraseFromParent, /*InsnID*/0,
        // GIR_Coverage, 614,
        GIR_Done,
      // Label 3058: @196097
      GIM_Try, /*On fail goto*//*Label 3059*/ GIMT_Encode4(196160), // Rule ID 615 //
        GIM_CheckIntrinsicID, /*MI*/0, /*Op*/1, GIMT_Encode2(Intrinsic::amdgcn_rcp),
        GIM_CheckType, /*MI*/0, /*Op*/0, /*Type*/GILLT_s64,
        GIM_CheckType, /*MI*/0, /*Op*/2, /*Type*/GILLT_s64,
        GIM_CheckRegBankForClass, /*MI*/0, /*Op*/0, /*RC*/GIMT_Encode2(AMDGPU::VReg_64RegClassID),
        GIM_CheckComplexPattern, /*MI*/0, /*Op*/2, /*Renderer*/GIMT_Encode2(0), GIMT_Encode2(GICP_gi_vop3mods0),
        // (intrinsic_wo_chain:{ *:[f64] } 2647:{ *:[iPTR] }, (VOP3Mods0:{ *:[f64] } f64:{ *:[f64] }:$src0, i32:{ *:[i32] }:$src0_modifiers, i1:{ *:[i1] }:$clamp, i32:{ *:[i32] }:$omod))  =>  (V_RCP_F64_e64:{ *:[f64] } i32:{ *:[i32] }:$src0_modifiers, f64:{ *:[f64] }:$src0, i1:{ *:[i1] }:$clamp, i32:{ *:[i32] }:$omod)
        GIR_BuildMI, /*InsnID*/0, /*Opcode*/GIMT_Encode2(AMDGPU::V_RCP_F64_e64),
        GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/0, // DstI[vdst]
        GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/1, // src0_modifiers
        GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/0, // src0
        GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/2, // clamp
        GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/3, // omod
        GIR_ConstrainSelectedInstOperands, /*InsnID*/0,
        GIR_EraseFromParent, /*InsnID*/0,
        // GIR_Coverage, 615,
        GIR_Done,
      // Label 3059: @196160
      GIM_Try, /*On fail goto*//*Label 3060*/ GIMT_Encode4(196223), // Rule ID 617 //
        GIM_CheckIntrinsicID, /*MI*/0, /*Op*/1, GIMT_Encode2(Intrinsic::amdgcn_rsq),
        GIM_CheckType, /*MI*/0, /*Op*/0, /*Type*/GILLT_s64,
        GIM_CheckType, /*MI*/0, /*Op*/2, /*Type*/GILLT_s64,
        GIM_CheckRegBankForClass, /*MI*/0, /*Op*/0, /*RC*/GIMT_Encode2(AMDGPU::VReg_64RegClassID),
        GIM_CheckComplexPattern, /*MI*/0, /*Op*/2, /*Renderer*/GIMT_Encode2(0), GIMT_Encode2(GICP_gi_vop3mods0),
        // (intrinsic_wo_chain:{ *:[f64] } 2652:{ *:[iPTR] }, (VOP3Mods0:{ *:[f64] } f64:{ *:[f64] }:$src0, i32:{ *:[i32] }:$src0_modifiers, i1:{ *:[i1] }:$clamp, i32:{ *:[i32] }:$omod))  =>  (V_RSQ_F64_e64:{ *:[f64] } i32:{ *:[i32] }:$src0_modifiers, f64:{ *:[f64] }:$src0, i1:{ *:[i1] }:$clamp, i32:{ *:[i32] }:$omod)
        GIR_BuildMI, /*InsnID*/0, /*Opcode*/GIMT_Encode2(AMDGPU::V_RSQ_F64_e64),
        GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/0, // DstI[vdst]
        GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/1, // src0_modifiers
        GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/0, // src0
        GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/2, // clamp
        GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/3, // omod
        GIR_ConstrainSelectedInstOperands, /*InsnID*/0,
        GIR_EraseFromParent, /*InsnID*/0,
        // GIR_Coverage, 617,
        GIR_Done,
      // Label 3060: @196223
      GIM_Try, /*On fail goto*//*Label 3061*/ GIMT_Encode4(196286), // Rule ID 619 //
        GIM_CheckIntrinsicID, /*MI*/0, /*Op*/1, GIMT_Encode2(Intrinsic::amdgcn_sqrt),
        GIM_CheckType, /*MI*/0, /*Op*/0, /*Type*/GILLT_s64,
        GIM_CheckType, /*MI*/0, /*Op*/2, /*Type*/GILLT_s64,
        GIM_CheckRegBankForClass, /*MI*/0, /*Op*/0, /*RC*/GIMT_Encode2(AMDGPU::VReg_64RegClassID),
        GIM_CheckComplexPattern, /*MI*/0, /*Op*/2, /*Renderer*/GIMT_Encode2(0), GIMT_Encode2(GICP_gi_vop3mods0),
        // (intrinsic_wo_chain:{ *:[f64] } 2729:{ *:[iPTR] }, (VOP3Mods0:{ *:[f64] } f64:{ *:[f64] }:$src0, i32:{ *:[i32] }:$src0_modifiers, i1:{ *:[i1] }:$clamp, i32:{ *:[i32] }:$omod))  =>  (V_SQRT_F64_e64:{ *:[f64] } i32:{ *:[i32] }:$src0_modifiers, f64:{ *:[f64] }:$src0, i1:{ *:[i1] }:$clamp, i32:{ *:[i32] }:$omod)
        GIR_BuildMI, /*InsnID*/0, /*Opcode*/GIMT_Encode2(AMDGPU::V_SQRT_F64_e64),
        GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/0, // DstI[vdst]
        GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/1, // src0_modifiers
        GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/0, // src0
        GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/2, // clamp
        GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/3, // omod
        GIR_ConstrainSelectedInstOperands, /*InsnID*/0,
        GIR_EraseFromParent, /*InsnID*/0,
        // GIR_Coverage, 619,
        GIR_Done,
      // Label 3061: @196286
      GIM_Try, /*On fail goto*//*Label 3062*/ GIMT_Encode4(196349), // Rule ID 620 //
        GIM_CheckIntrinsicID, /*MI*/0, /*Op*/1, GIMT_Encode2(Intrinsic::amdgcn_sin),
        GIM_CheckType, /*MI*/0, /*Op*/0, /*Type*/GILLT_s32,
        GIM_CheckType, /*MI*/0, /*Op*/2, /*Type*/GILLT_s32,
        GIM_CheckRegBankForClass, /*MI*/0, /*Op*/0, /*RC*/GIMT_Encode2(AMDGPU::VGPR_32RegClassID),
        GIM_CheckComplexPattern, /*MI*/0, /*Op*/2, /*Renderer*/GIMT_Encode2(0), GIMT_Encode2(GICP_gi_vop3mods0),
        // (intrinsic_wo_chain:{ *:[f32] } 2713:{ *:[iPTR] }, (VOP3Mods0:{ *:[f32] } f32:{ *:[f32] }:$src0, i32:{ *:[i32] }:$src0_modifiers, i1:{ *:[i1] }:$clamp, i32:{ *:[i32] }:$omod))  =>  (V_SIN_F32_e64:{ *:[f32] } i32:{ *:[i32] }:$src0_modifiers, f32:{ *:[f32] }:$src0, i1:{ *:[i1] }:$clamp, i32:{ *:[i32] }:$omod)
        GIR_BuildMI, /*InsnID*/0, /*Opcode*/GIMT_Encode2(AMDGPU::V_SIN_F32_e64),
        GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/0, // DstI[vdst]
        GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/1, // src0_modifiers
        GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/0, // src0
        GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/2, // clamp
        GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/3, // omod
        GIR_ConstrainSelectedInstOperands, /*InsnID*/0,
        GIR_EraseFromParent, /*InsnID*/0,
        // GIR_Coverage, 620,
        GIR_Done,
      // Label 3062: @196349
      GIM_Try, /*On fail goto*//*Label 3063*/ GIMT_Encode4(196412), // Rule ID 622 //
        GIM_CheckIntrinsicID, /*MI*/0, /*Op*/1, GIMT_Encode2(Intrinsic::amdgcn_cos),
        GIM_CheckType, /*MI*/0, /*Op*/0, /*Type*/GILLT_s32,
        GIM_CheckType, /*MI*/0, /*Op*/2, /*Type*/GILLT_s32,
        GIM_CheckRegBankForClass, /*MI*/0, /*Op*/0, /*RC*/GIMT_Encode2(AMDGPU::VGPR_32RegClassID),
        GIM_CheckComplexPattern, /*MI*/0, /*Op*/2, /*Renderer*/GIMT_Encode2(0), GIMT_Encode2(GICP_gi_vop3mods0),
        // (intrinsic_wo_chain:{ *:[f32] } 1902:{ *:[iPTR] }, (VOP3Mods0:{ *:[f32] } f32:{ *:[f32] }:$src0, i32:{ *:[i32] }:$src0_modifiers, i1:{ *:[i1] }:$clamp, i32:{ *:[i32] }:$omod))  =>  (V_COS_F32_e64:{ *:[f32] } i32:{ *:[i32] }:$src0_modifiers, f32:{ *:[f32] }:$src0, i1:{ *:[i1] }:$clamp, i32:{ *:[i32] }:$omod)
        GIR_BuildMI, /*InsnID*/0, /*Opcode*/GIMT_Encode2(AMDGPU::V_COS_F32_e64),
        GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/0, // DstI[vdst]
        GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/1, // src0_modifiers
        GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/0, // src0
        GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/2, // clamp
        GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/3, // omod
        GIR_ConstrainSelectedInstOperands, /*InsnID*/0,
        GIR_EraseFromParent, /*InsnID*/0,
        // GIR_Coverage, 622,
        GIR_Done,
      // Label 3063: @196412
      GIM_Try, /*On fail goto*//*Label 3064*/ GIMT_Encode4(196460), // Rule ID 629 //
        GIM_CheckIntrinsicID, /*MI*/0, /*Op*/1, GIMT_Encode2(Intrinsic::amdgcn_sffbh),
        GIM_CheckType, /*MI*/0, /*Op*/0, /*Type*/GILLT_s32,
        GIM_CheckType, /*MI*/0, /*Op*/2, /*Type*/GILLT_s32,
        GIM_CheckRegBankForClass, /*MI*/0, /*Op*/0, /*RC*/GIMT_Encode2(AMDGPU::VGPR_32RegClassID),
        GIM_CheckComplexPattern, /*MI*/0, /*Op*/2, /*Renderer*/GIMT_Encode2(0), GIMT_Encode2(GICP_gi_vop3mods0),
        // (intrinsic_wo_chain:{ *:[i32] } 2712:{ *:[iPTR] }, (VOP3Mods0:{ *:[i32] } i32:{ *:[i32] }:$src0))  =>  (V_FFBH_I32_e64:{ *:[i32] } i32:{ *:[i32] }:$src0)
        GIR_BuildMI, /*InsnID*/0, /*Opcode*/GIMT_Encode2(AMDGPU::V_FFBH_I32_e64),
        GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/0, // DstI[vdst]
        GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/0, // src0
        GIR_ConstrainSelectedInstOperands, /*InsnID*/0,
        GIR_EraseFromParent, /*InsnID*/0,
        // GIR_Coverage, 629,
        GIR_Done,
      // Label 3064: @196460
      GIM_Try, /*On fail goto*//*Label 3065*/ GIMT_Encode4(196523), // Rule ID 631 //
        GIM_CheckIntrinsicID, /*MI*/0, /*Op*/1, GIMT_Encode2(Intrinsic::amdgcn_frexp_exp),
        GIM_CheckType, /*MI*/0, /*Op*/0, /*Type*/GILLT_s32,
        GIM_CheckType, /*MI*/0, /*Op*/2, /*Type*/GILLT_s64,
        GIM_CheckRegBankForClass, /*MI*/0, /*Op*/0, /*RC*/GIMT_Encode2(AMDGPU::VGPR_32RegClassID),
        GIM_CheckComplexPattern, /*MI*/0, /*Op*/2, /*Renderer*/GIMT_Encode2(0), GIMT_Encode2(GICP_gi_vop3mods0),
        // (intrinsic_wo_chain:{ *:[i32] } 1975:{ *:[iPTR] }, (VOP3Mods0:{ *:[f64] } f64:{ *:[f64] }:$src0, i32:{ *:[i32] }:$src0_modifiers, i1:{ *:[i1] }:$clamp, i32:{ *:[i32] }:$omod))  =>  (V_FREXP_EXP_I32_F64_e64:{ *:[i32] } i32:{ *:[i32] }:$src0_modifiers, f64:{ *:[f64] }:$src0, i1:{ *:[i1] }:$clamp, i32:{ *:[i32] }:$omod)
        GIR_BuildMI, /*InsnID*/0, /*Opcode*/GIMT_Encode2(AMDGPU::V_FREXP_EXP_I32_F64_e64),
        GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/0, // DstI[vdst]
        GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/1, // src0_modifiers
        GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/0, // src0
        GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/2, // clamp
        GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/3, // omod
        GIR_ConstrainSelectedInstOperands, /*InsnID*/0,
        GIR_EraseFromParent, /*InsnID*/0,
        // GIR_Coverage, 631,
        GIR_Done,
      // Label 3065: @196523
      GIM_Try, /*On fail goto*//*Label 3066*/ GIMT_Encode4(196586), // Rule ID 632 //
        GIM_CheckIntrinsicID, /*MI*/0, /*Op*/1, GIMT_Encode2(Intrinsic::amdgcn_frexp_mant),
        GIM_CheckType, /*MI*/0, /*Op*/0, /*Type*/GILLT_s64,
        GIM_CheckType, /*MI*/0, /*Op*/2, /*Type*/GILLT_s64,
        GIM_CheckRegBankForClass, /*MI*/0, /*Op*/0, /*RC*/GIMT_Encode2(AMDGPU::VReg_64RegClassID),
        GIM_CheckComplexPattern, /*MI*/0, /*Op*/2, /*Renderer*/GIMT_Encode2(0), GIMT_Encode2(GICP_gi_vop3mods0),
        // (intrinsic_wo_chain:{ *:[f64] } 1976:{ *:[iPTR] }, (VOP3Mods0:{ *:[f64] } f64:{ *:[f64] }:$src0, i32:{ *:[i32] }:$src0_modifiers, i1:{ *:[i1] }:$clamp, i32:{ *:[i32] }:$omod))  =>  (V_FREXP_MANT_F64_e64:{ *:[f64] } i32:{ *:[i32] }:$src0_modifiers, f64:{ *:[f64] }:$src0, i1:{ *:[i1] }:$clamp, i32:{ *:[i32] }:$omod)
        GIR_BuildMI, /*InsnID*/0, /*Opcode*/GIMT_Encode2(AMDGPU::V_FREXP_MANT_F64_e64),
        GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/0, // DstI[vdst]
        GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/1, // src0_modifiers
        GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/0, // src0
        GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/2, // clamp
        GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/3, // omod
        GIR_ConstrainSelectedInstOperands, /*InsnID*/0,
        GIR_EraseFromParent, /*InsnID*/0,
        // GIR_Coverage, 632,
        GIR_Done,
      // Label 3066: @196586
      GIM_Try, /*On fail goto*//*Label 3067*/ GIMT_Encode4(196649), // Rule ID 633 //
        GIM_CheckIntrinsicID, /*MI*/0, /*Op*/1, GIMT_Encode2(Intrinsic::amdgcn_fract),
        GIM_CheckType, /*MI*/0, /*Op*/0, /*Type*/GILLT_s64,
        GIM_CheckType, /*MI*/0, /*Op*/2, /*Type*/GILLT_s64,
        GIM_CheckRegBankForClass, /*MI*/0, /*Op*/0, /*RC*/GIMT_Encode2(AMDGPU::VReg_64RegClassID),
        GIM_CheckComplexPattern, /*MI*/0, /*Op*/2, /*Renderer*/GIMT_Encode2(0), GIMT_Encode2(GICP_gi_vop3mods0),
        // (intrinsic_wo_chain:{ *:[f64] } 1974:{ *:[iPTR] }, (VOP3Mods0:{ *:[f64] } f64:{ *:[f64] }:$src0, i32:{ *:[i32] }:$src0_modifiers, i1:{ *:[i1] }:$clamp, i32:{ *:[i32] }:$omod))  =>  (V_FRACT_F64_e64:{ *:[f64] } i32:{ *:[i32] }:$src0_modifiers, f64:{ *:[f64] }:$src0, i1:{ *:[i1] }:$clamp, i32:{ *:[i32] }:$omod)
        GIR_BuildMI, /*InsnID*/0, /*Opcode*/GIMT_Encode2(AMDGPU::V_FRACT_F64_e64),
        GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/0, // DstI[vdst]
        GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/1, // src0_modifiers
        GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/0, // src0
        GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/2, // clamp
        GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/3, // omod
        GIR_ConstrainSelectedInstOperands, /*InsnID*/0,
        GIR_EraseFromParent, /*InsnID*/0,
        // GIR_Coverage, 633,
        GIR_Done,
      // Label 3067: @196649
      GIM_Try, /*On fail goto*//*Label 3068*/ GIMT_Encode4(196707), // Rule ID 635 //
        GIM_CheckIntrinsicID, /*MI*/0, /*Op*/1, GIMT_Encode2(Intrinsic::amdgcn_frexp_exp),
        GIM_CheckType, /*MI*/0, /*Op*/0, /*Type*/GILLT_s32,
        GIM_CheckType, /*MI*/0, /*Op*/2, /*Type*/GILLT_s32,
        GIM_CheckRegBankForClass, /*MI*/0, /*Op*/0, /*RC*/GIMT_Encode2(AMDGPU::VGPR_32RegClassID),
        GIM_CheckComplexPattern, /*MI*/0, /*Op*/2, /*Renderer*/GIMT_Encode2(0), GIMT_Encode2(GICP_gi_vop3mods0),
        // (intrinsic_wo_chain:{ *:[i32] } 1975:{ *:[iPTR] }, (VOP3Mods0:{ *:[f32] } f32:{ *:[f32] }:$src0, i32:{ *:[i32] }:$src0_modifiers, i1:{ *:[i1] }:$clamp))  =>  (V_FREXP_EXP_I32_F32_e64:{ *:[i32] } i32:{ *:[i32] }:$src0_modifiers, f32:{ *:[f32] }:$src0, i1:{ *:[i1] }:$clamp)
        GIR_BuildMI, /*InsnID*/0, /*Opcode*/GIMT_Encode2(AMDGPU::V_FREXP_EXP_I32_F32_e64),
        GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/0, // DstI[vdst]
        GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/1, // src0_modifiers
        GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/0, // src0
        GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/2, // clamp
        GIR_ConstrainSelectedInstOperands, /*InsnID*/0,
        GIR_EraseFromParent, /*InsnID*/0,
        // GIR_Coverage, 635,
        GIR_Done,
      // Label 3068: @196707
      GIM_Try, /*On fail goto*//*Label 3069*/ GIMT_Encode4(196770), // Rule ID 636 //
        GIM_CheckIntrinsicID, /*MI*/0, /*Op*/1, GIMT_Encode2(Intrinsic::amdgcn_frexp_mant),
        GIM_CheckType, /*MI*/0, /*Op*/0, /*Type*/GILLT_s32,
        GIM_CheckType, /*MI*/0, /*Op*/2, /*Type*/GILLT_s32,
        GIM_CheckRegBankForClass, /*MI*/0, /*Op*/0, /*RC*/GIMT_Encode2(AMDGPU::VGPR_32RegClassID),
        GIM_CheckComplexPattern, /*MI*/0, /*Op*/2, /*Renderer*/GIMT_Encode2(0), GIMT_Encode2(GICP_gi_vop3mods0),
        // (intrinsic_wo_chain:{ *:[f32] } 1976:{ *:[iPTR] }, (VOP3Mods0:{ *:[f32] } f32:{ *:[f32] }:$src0, i32:{ *:[i32] }:$src0_modifiers, i1:{ *:[i1] }:$clamp, i32:{ *:[i32] }:$omod))  =>  (V_FREXP_MANT_F32_e64:{ *:[f32] } i32:{ *:[i32] }:$src0_modifiers, f32:{ *:[f32] }:$src0, i1:{ *:[i1] }:$clamp, i32:{ *:[i32] }:$omod)
        GIR_BuildMI, /*InsnID*/0, /*Opcode*/GIMT_Encode2(AMDGPU::V_FREXP_MANT_F32_e64),
        GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/0, // DstI[vdst]
        GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/1, // src0_modifiers
        GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/0, // src0
        GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/2, // clamp
        GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/3, // omod
        GIR_ConstrainSelectedInstOperands, /*InsnID*/0,
        GIR_EraseFromParent, /*InsnID*/0,
        // GIR_Coverage, 636,
        GIR_Done,
      // Label 3069: @196770
      GIM_Try, /*On fail goto*//*Label 3070*/ GIMT_Encode4(196836), // Rule ID 637 //
        GIM_CheckFeatures, GIMT_Encode2(GIFBS_isGFX6GFX7),
        GIM_CheckIntrinsicID, /*MI*/0, /*Op*/1, GIMT_Encode2(Intrinsic::amdgcn_log_clamp),
        GIM_CheckType, /*MI*/0, /*Op*/0, /*Type*/GILLT_s32,
        GIM_CheckType, /*MI*/0, /*Op*/2, /*Type*/GILLT_s32,
        GIM_CheckRegBankForClass, /*MI*/0, /*Op*/0, /*RC*/GIMT_Encode2(AMDGPU::VGPR_32RegClassID),
        GIM_CheckComplexPattern, /*MI*/0, /*Op*/2, /*Renderer*/GIMT_Encode2(0), GIMT_Encode2(GICP_gi_vop3mods0),
        // (intrinsic_wo_chain:{ *:[f32] } 2535:{ *:[iPTR] }, (VOP3Mods0:{ *:[f32] } f32:{ *:[f32] }:$src0, i32:{ *:[i32] }:$src0_modifiers, i1:{ *:[i1] }:$clamp, i32:{ *:[i32] }:$omod))  =>  (V_LOG_CLAMP_F32_e64:{ *:[f32] } i32:{ *:[i32] }:$src0_modifiers, f32:{ *:[f32] }:$src0, i1:{ *:[i1] }:$clamp, i32:{ *:[i32] }:$omod)
        GIR_BuildMI, /*InsnID*/0, /*Opcode*/GIMT_Encode2(AMDGPU::V_LOG_CLAMP_F32_e64),
        GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/0, // DstI[vdst]
        GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/1, // src0_modifiers
        GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/0, // src0
        GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/2, // clamp
        GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/3, // omod
        GIR_ConstrainSelectedInstOperands, /*InsnID*/0,
        GIR_EraseFromParent, /*InsnID*/0,
        // GIR_Coverage, 637,
        GIR_Done,
      // Label 3070: @196836
      GIM_Try, /*On fail goto*//*Label 3071*/ GIMT_Encode4(196902), // Rule ID 638 //
        GIM_CheckFeatures, GIMT_Encode2(GIFBS_isGFX6GFX7),
        GIM_CheckIntrinsicID, /*MI*/0, /*Op*/1, GIMT_Encode2(Intrinsic::amdgcn_rcp_legacy),
        GIM_CheckType, /*MI*/0, /*Op*/0, /*Type*/GILLT_s32,
        GIM_CheckType, /*MI*/0, /*Op*/2, /*Type*/GILLT_s32,
        GIM_CheckRegBankForClass, /*MI*/0, /*Op*/0, /*RC*/GIMT_Encode2(AMDGPU::VGPR_32RegClassID),
        GIM_CheckComplexPattern, /*MI*/0, /*Op*/2, /*Renderer*/GIMT_Encode2(0), GIMT_Encode2(GICP_gi_vop3mods0),
        // (intrinsic_wo_chain:{ *:[f32] } 2648:{ *:[iPTR] }, (VOP3Mods0:{ *:[f32] } f32:{ *:[f32] }:$src0, i32:{ *:[i32] }:$src0_modifiers, i1:{ *:[i1] }:$clamp, i32:{ *:[i32] }:$omod))  =>  (V_RCP_LEGACY_F32_e64:{ *:[f32] } i32:{ *:[i32] }:$src0_modifiers, f32:{ *:[f32] }:$src0, i1:{ *:[i1] }:$clamp, i32:{ *:[i32] }:$omod)
        GIR_BuildMI, /*InsnID*/0, /*Opcode*/GIMT_Encode2(AMDGPU::V_RCP_LEGACY_F32_e64),
        GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/0, // DstI[vdst]
        GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/1, // src0_modifiers
        GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/0, // src0
        GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/2, // clamp
        GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/3, // omod
        GIR_ConstrainSelectedInstOperands, /*InsnID*/0,
        GIR_EraseFromParent, /*InsnID*/0,
        // GIR_Coverage, 638,
        GIR_Done,
      // Label 3071: @196902
      GIM_Try, /*On fail goto*//*Label 3072*/ GIMT_Encode4(196968), // Rule ID 640 //
        GIM_CheckFeatures, GIMT_Encode2(GIFBS_isGFX6GFX7),
        GIM_CheckIntrinsicID, /*MI*/0, /*Op*/1, GIMT_Encode2(Intrinsic::amdgcn_rsq_clamp),
        GIM_CheckType, /*MI*/0, /*Op*/0, /*Type*/GILLT_s32,
        GIM_CheckType, /*MI*/0, /*Op*/2, /*Type*/GILLT_s32,
        GIM_CheckRegBankForClass, /*MI*/0, /*Op*/0, /*RC*/GIMT_Encode2(AMDGPU::VGPR_32RegClassID),
        GIM_CheckComplexPattern, /*MI*/0, /*Op*/2, /*Renderer*/GIMT_Encode2(0), GIMT_Encode2(GICP_gi_vop3mods0),
        // (intrinsic_wo_chain:{ *:[f32] } 2653:{ *:[iPTR] }, (VOP3Mods0:{ *:[f32] } f32:{ *:[f32] }:$src0, i32:{ *:[i32] }:$src0_modifiers, i1:{ *:[i1] }:$clamp, i32:{ *:[i32] }:$omod))  =>  (V_RSQ_CLAMP_F32_e64:{ *:[f32] } i32:{ *:[i32] }:$src0_modifiers, f32:{ *:[f32] }:$src0, i1:{ *:[i1] }:$clamp, i32:{ *:[i32] }:$omod)
        GIR_BuildMI, /*InsnID*/0, /*Opcode*/GIMT_Encode2(AMDGPU::V_RSQ_CLAMP_F32_e64),
        GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/0, // DstI[vdst]
        GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/1, // src0_modifiers
        GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/0, // src0
        GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/2, // clamp
        GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/3, // omod
        GIR_ConstrainSelectedInstOperands, /*InsnID*/0,
        GIR_EraseFromParent, /*InsnID*/0,
        // GIR_Coverage, 640,
        GIR_Done,
      // Label 3072: @196968
      GIM_Try, /*On fail goto*//*Label 3073*/ GIMT_Encode4(197034), // Rule ID 642 //
        GIM_CheckFeatures, GIMT_Encode2(GIFBS_isGFX6GFX7),
        GIM_CheckIntrinsicID, /*MI*/0, /*Op*/1, GIMT_Encode2(Intrinsic::amdgcn_rsq_legacy),
        GIM_CheckType, /*MI*/0, /*Op*/0, /*Type*/GILLT_s32,
        GIM_CheckType, /*MI*/0, /*Op*/2, /*Type*/GILLT_s32,
        GIM_CheckRegBankForClass, /*MI*/0, /*Op*/0, /*RC*/GIMT_Encode2(AMDGPU::VGPR_32RegClassID),
        GIM_CheckComplexPattern, /*MI*/0, /*Op*/2, /*Renderer*/GIMT_Encode2(0), GIMT_Encode2(GICP_gi_vop3mods0),
        // (intrinsic_wo_chain:{ *:[f32] } 2654:{ *:[iPTR] }, (VOP3Mods0:{ *:[f32] } f32:{ *:[f32] }:$src0, i32:{ *:[i32] }:$src0_modifiers, i1:{ *:[i1] }:$clamp, i32:{ *:[i32] }:$omod))  =>  (V_RSQ_LEGACY_F32_e64:{ *:[f32] } i32:{ *:[i32] }:$src0_modifiers, f32:{ *:[f32] }:$src0, i1:{ *:[i1] }:$clamp, i32:{ *:[i32] }:$omod)
        GIR_BuildMI, /*InsnID*/0, /*Opcode*/GIMT_Encode2(AMDGPU::V_RSQ_LEGACY_F32_e64),
        GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/0, // DstI[vdst]
        GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/1, // src0_modifiers
        GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/0, // src0
        GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/2, // clamp
        GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/3, // omod
        GIR_ConstrainSelectedInstOperands, /*InsnID*/0,
        GIR_EraseFromParent, /*InsnID*/0,
        // GIR_Coverage, 642,
        GIR_Done,
      // Label 3073: @197034
      GIM_Try, /*On fail goto*//*Label 3074*/ GIMT_Encode4(197100), // Rule ID 643 //
        GIM_CheckFeatures, GIMT_Encode2(GIFBS_isGFX6GFX7),
        GIM_CheckIntrinsicID, /*MI*/0, /*Op*/1, GIMT_Encode2(Intrinsic::amdgcn_rsq_clamp),
        GIM_CheckType, /*MI*/0, /*Op*/0, /*Type*/GILLT_s64,
        GIM_CheckType, /*MI*/0, /*Op*/2, /*Type*/GILLT_s64,
        GIM_CheckRegBankForClass, /*MI*/0, /*Op*/0, /*RC*/GIMT_Encode2(AMDGPU::VReg_64RegClassID),
        GIM_CheckComplexPattern, /*MI*/0, /*Op*/2, /*Renderer*/GIMT_Encode2(0), GIMT_Encode2(GICP_gi_vop3mods0),
        // (intrinsic_wo_chain:{ *:[f64] } 2653:{ *:[iPTR] }, (VOP3Mods0:{ *:[f64] } f64:{ *:[f64] }:$src0, i32:{ *:[i32] }:$src0_modifiers, i1:{ *:[i1] }:$clamp, i32:{ *:[i32] }:$omod))  =>  (V_RSQ_CLAMP_F64_e64:{ *:[f64] } i32:{ *:[i32] }:$src0_modifiers, f64:{ *:[f64] }:$src0, i1:{ *:[i1] }:$clamp, i32:{ *:[i32] }:$omod)
        GIR_BuildMI, /*InsnID*/0, /*Opcode*/GIMT_Encode2(AMDGPU::V_RSQ_CLAMP_F64_e64),
        GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/0, // DstI[vdst]
        GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/1, // src0_modifiers
        GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/0, // src0
        GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/2, // clamp
        GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/3, // omod
        GIR_ConstrainSelectedInstOperands, /*InsnID*/0,
        GIR_EraseFromParent, /*InsnID*/0,
        // GIR_Coverage, 643,
        GIR_Done,
      // Label 3074: @197100
      GIM_Try, /*On fail goto*//*Label 3075*/ GIMT_Encode4(197166), // Rule ID 657 //
        GIM_CheckFeatures, GIMT_Encode2(GIFBS_Has16BitInsts_NotHasTrue16BitInsts),
        GIM_CheckIntrinsicID, /*MI*/0, /*Op*/1, GIMT_Encode2(Intrinsic::amdgcn_rcp),
        GIM_CheckType, /*MI*/0, /*Op*/0, /*Type*/GILLT_s16,
        GIM_CheckType, /*MI*/0, /*Op*/2, /*Type*/GILLT_s16,
        GIM_CheckRegBankForClass, /*MI*/0, /*Op*/0, /*RC*/GIMT_Encode2(AMDGPU::VGPR_32RegClassID),
        GIM_CheckComplexPattern, /*MI*/0, /*Op*/2, /*Renderer*/GIMT_Encode2(0), GIMT_Encode2(GICP_gi_vop3mods0),
        // (intrinsic_wo_chain:{ *:[f16] } 2647:{ *:[iPTR] }, (VOP3Mods0:{ *:[f16] } f16:{ *:[f16] }:$src0, i32:{ *:[i32] }:$src0_modifiers, i1:{ *:[i1] }:$clamp, i32:{ *:[i32] }:$omod))  =>  (V_RCP_F16_e64:{ *:[f16] } i32:{ *:[i32] }:$src0_modifiers, f16:{ *:[f16] }:$src0, i1:{ *:[i1] }:$clamp, i32:{ *:[i32] }:$omod)
        GIR_BuildMI, /*InsnID*/0, /*Opcode*/GIMT_Encode2(AMDGPU::V_RCP_F16_e64),
        GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/0, // DstI[vdst]
        GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/1, // src0_modifiers
        GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/0, // src0
        GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/2, // clamp
        GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/3, // omod
        GIR_ConstrainSelectedInstOperands, /*InsnID*/0,
        GIR_EraseFromParent, /*InsnID*/0,
        // GIR_Coverage, 657,
        GIR_Done,
      // Label 3075: @197166
      GIM_Try, /*On fail goto*//*Label 3076*/ GIMT_Encode4(197232), // Rule ID 659 //
        GIM_CheckFeatures, GIMT_Encode2(GIFBS_UseRealTrue16Insts),
        GIM_CheckIntrinsicID, /*MI*/0, /*Op*/1, GIMT_Encode2(Intrinsic::amdgcn_rcp),
        GIM_CheckType, /*MI*/0, /*Op*/0, /*Type*/GILLT_s16,
        GIM_CheckType, /*MI*/0, /*Op*/2, /*Type*/GILLT_s16,
        GIM_CheckRegBankForClass, /*MI*/0, /*Op*/0, /*RC*/GIMT_Encode2(AMDGPU::VGPR_16RegClassID),
        GIM_CheckComplexPattern, /*MI*/0, /*Op*/2, /*Renderer*/GIMT_Encode2(0), GIMT_Encode2(GICP_gi_vop3mods0),
        // (intrinsic_wo_chain:{ *:[f16] } 2647:{ *:[iPTR] }, (VOP3Mods0:{ *:[f16] } f16:{ *:[f16] }:$src0, i32:{ *:[i32] }:$src0_modifiers, i1:{ *:[i1] }:$clamp, i32:{ *:[i32] }:$omod))  =>  (V_RCP_F16_t16_e64:{ *:[f16] } i32:{ *:[i32] }:$src0_modifiers, f16:{ *:[f16] }:$src0, i1:{ *:[i1] }:$clamp, i32:{ *:[i32] }:$omod)
        GIR_BuildMI, /*InsnID*/0, /*Opcode*/GIMT_Encode2(AMDGPU::V_RCP_F16_t16_e64),
        GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/0, // DstI[vdst]
        GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/1, // src0_modifiers
        GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/0, // src0
        GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/2, // clamp
        GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/3, // omod
        GIR_ConstrainSelectedInstOperands, /*InsnID*/0,
        GIR_EraseFromParent, /*InsnID*/0,
        // GIR_Coverage, 659,
        GIR_Done,
      // Label 3076: @197232
      GIM_Try, /*On fail goto*//*Label 3077*/ GIMT_Encode4(197298), // Rule ID 661 //
        GIM_CheckFeatures, GIMT_Encode2(GIFBS_UseFakeTrue16Insts),
        GIM_CheckIntrinsicID, /*MI*/0, /*Op*/1, GIMT_Encode2(Intrinsic::amdgcn_rcp),
        GIM_CheckType, /*MI*/0, /*Op*/0, /*Type*/GILLT_s16,
        GIM_CheckType, /*MI*/0, /*Op*/2, /*Type*/GILLT_s16,
        GIM_CheckRegBankForClass, /*MI*/0, /*Op*/0, /*RC*/GIMT_Encode2(AMDGPU::VGPR_32RegClassID),
        GIM_CheckComplexPattern, /*MI*/0, /*Op*/2, /*Renderer*/GIMT_Encode2(0), GIMT_Encode2(GICP_gi_vop3mods0),
        // (intrinsic_wo_chain:{ *:[f16] } 2647:{ *:[iPTR] }, (VOP3Mods0:{ *:[f16] } f16:{ *:[f16] }:$src0, i32:{ *:[i32] }:$src0_modifiers, i1:{ *:[i1] }:$clamp, i32:{ *:[i32] }:$omod))  =>  (V_RCP_F16_fake16_e64:{ *:[f16] } i32:{ *:[i32] }:$src0_modifiers, f16:{ *:[f16] }:$src0, i1:{ *:[i1] }:$clamp, i32:{ *:[i32] }:$omod)
        GIR_BuildMI, /*InsnID*/0, /*Opcode*/GIMT_Encode2(AMDGPU::V_RCP_F16_fake16_e64),
        GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/0, // DstI[vdst]
        GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/1, // src0_modifiers
        GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/0, // src0
        GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/2, // clamp
        GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/3, // omod
        GIR_ConstrainSelectedInstOperands, /*InsnID*/0,
        GIR_EraseFromParent, /*InsnID*/0,
        // GIR_Coverage, 661,
        GIR_Done,
      // Label 3077: @197298
      GIM_Try, /*On fail goto*//*Label 3078*/ GIMT_Encode4(197364), // Rule ID 664 //
        GIM_CheckFeatures, GIMT_Encode2(GIFBS_Has16BitInsts_NotHasTrue16BitInsts),
        GIM_CheckIntrinsicID, /*MI*/0, /*Op*/1, GIMT_Encode2(Intrinsic::amdgcn_sqrt),
        GIM_CheckType, /*MI*/0, /*Op*/0, /*Type*/GILLT_s16,
        GIM_CheckType, /*MI*/0, /*Op*/2, /*Type*/GILLT_s16,
        GIM_CheckRegBankForClass, /*MI*/0, /*Op*/0, /*RC*/GIMT_Encode2(AMDGPU::VGPR_32RegClassID),
        GIM_CheckComplexPattern, /*MI*/0, /*Op*/2, /*Renderer*/GIMT_Encode2(0), GIMT_Encode2(GICP_gi_vop3mods0),
        // (intrinsic_wo_chain:{ *:[f16] } 2729:{ *:[iPTR] }, (VOP3Mods0:{ *:[f16] } f16:{ *:[f16] }:$src0, i32:{ *:[i32] }:$src0_modifiers, i1:{ *:[i1] }:$clamp, i32:{ *:[i32] }:$omod))  =>  (V_SQRT_F16_e64:{ *:[f16] } i32:{ *:[i32] }:$src0_modifiers, f16:{ *:[f16] }:$src0, i1:{ *:[i1] }:$clamp, i32:{ *:[i32] }:$omod)
        GIR_BuildMI, /*InsnID*/0, /*Opcode*/GIMT_Encode2(AMDGPU::V_SQRT_F16_e64),
        GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/0, // DstI[vdst]
        GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/1, // src0_modifiers
        GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/0, // src0
        GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/2, // clamp
        GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/3, // omod
        GIR_ConstrainSelectedInstOperands, /*InsnID*/0,
        GIR_EraseFromParent, /*InsnID*/0,
        // GIR_Coverage, 664,
        GIR_Done,
      // Label 3078: @197364
      GIM_Try, /*On fail goto*//*Label 3079*/ GIMT_Encode4(197430), // Rule ID 666 //
        GIM_CheckFeatures, GIMT_Encode2(GIFBS_UseRealTrue16Insts),
        GIM_CheckIntrinsicID, /*MI*/0, /*Op*/1, GIMT_Encode2(Intrinsic::amdgcn_sqrt),
        GIM_CheckType, /*MI*/0, /*Op*/0, /*Type*/GILLT_s16,
        GIM_CheckType, /*MI*/0, /*Op*/2, /*Type*/GILLT_s16,
        GIM_CheckRegBankForClass, /*MI*/0, /*Op*/0, /*RC*/GIMT_Encode2(AMDGPU::VGPR_16RegClassID),
        GIM_CheckComplexPattern, /*MI*/0, /*Op*/2, /*Renderer*/GIMT_Encode2(0), GIMT_Encode2(GICP_gi_vop3mods0),
        // (intrinsic_wo_chain:{ *:[f16] } 2729:{ *:[iPTR] }, (VOP3Mods0:{ *:[f16] } f16:{ *:[f16] }:$src0, i32:{ *:[i32] }:$src0_modifiers, i1:{ *:[i1] }:$clamp, i32:{ *:[i32] }:$omod))  =>  (V_SQRT_F16_t16_e64:{ *:[f16] } i32:{ *:[i32] }:$src0_modifiers, f16:{ *:[f16] }:$src0, i1:{ *:[i1] }:$clamp, i32:{ *:[i32] }:$omod)
        GIR_BuildMI, /*InsnID*/0, /*Opcode*/GIMT_Encode2(AMDGPU::V_SQRT_F16_t16_e64),
        GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/0, // DstI[vdst]
        GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/1, // src0_modifiers
        GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/0, // src0
        GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/2, // clamp
        GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/3, // omod
        GIR_ConstrainSelectedInstOperands, /*InsnID*/0,
        GIR_EraseFromParent, /*InsnID*/0,
        // GIR_Coverage, 666,
        GIR_Done,
      // Label 3079: @197430
      GIM_Try, /*On fail goto*//*Label 3080*/ GIMT_Encode4(197496), // Rule ID 668 //
        GIM_CheckFeatures, GIMT_Encode2(GIFBS_UseFakeTrue16Insts),
        GIM_CheckIntrinsicID, /*MI*/0, /*Op*/1, GIMT_Encode2(Intrinsic::amdgcn_sqrt),
        GIM_CheckType, /*MI*/0, /*Op*/0, /*Type*/GILLT_s16,
        GIM_CheckType, /*MI*/0, /*Op*/2, /*Type*/GILLT_s16,
        GIM_CheckRegBankForClass, /*MI*/0, /*Op*/0, /*RC*/GIMT_Encode2(AMDGPU::VGPR_32RegClassID),
        GIM_CheckComplexPattern, /*MI*/0, /*Op*/2, /*Renderer*/GIMT_Encode2(0), GIMT_Encode2(GICP_gi_vop3mods0),
        // (intrinsic_wo_chain:{ *:[f16] } 2729:{ *:[iPTR] }, (VOP3Mods0:{ *:[f16] } f16:{ *:[f16] }:$src0, i32:{ *:[i32] }:$src0_modifiers, i1:{ *:[i1] }:$clamp, i32:{ *:[i32] }:$omod))  =>  (V_SQRT_F16_fake16_e64:{ *:[f16] } i32:{ *:[i32] }:$src0_modifiers, f16:{ *:[f16] }:$src0, i1:{ *:[i1] }:$clamp, i32:{ *:[i32] }:$omod)
        GIR_BuildMI, /*InsnID*/0, /*Opcode*/GIMT_Encode2(AMDGPU::V_SQRT_F16_fake16_e64),
        GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/0, // DstI[vdst]
        GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/1, // src0_modifiers
        GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/0, // src0
        GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/2, // clamp
        GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/3, // omod
        GIR_ConstrainSelectedInstOperands, /*InsnID*/0,
        GIR_EraseFromParent, /*InsnID*/0,
        // GIR_Coverage, 668,
        GIR_Done,
      // Label 3080: @197496
      GIM_Try, /*On fail goto*//*Label 3081*/ GIMT_Encode4(197562), // Rule ID 669 //
        GIM_CheckFeatures, GIMT_Encode2(GIFBS_Has16BitInsts_NotHasTrue16BitInsts),
        GIM_CheckIntrinsicID, /*MI*/0, /*Op*/1, GIMT_Encode2(Intrinsic::amdgcn_rsq),
        GIM_CheckType, /*MI*/0, /*Op*/0, /*Type*/GILLT_s16,
        GIM_CheckType, /*MI*/0, /*Op*/2, /*Type*/GILLT_s16,
        GIM_CheckRegBankForClass, /*MI*/0, /*Op*/0, /*RC*/GIMT_Encode2(AMDGPU::VGPR_32RegClassID),
        GIM_CheckComplexPattern, /*MI*/0, /*Op*/2, /*Renderer*/GIMT_Encode2(0), GIMT_Encode2(GICP_gi_vop3mods0),
        // (intrinsic_wo_chain:{ *:[f16] } 2652:{ *:[iPTR] }, (VOP3Mods0:{ *:[f16] } f16:{ *:[f16] }:$src0, i32:{ *:[i32] }:$src0_modifiers, i1:{ *:[i1] }:$clamp, i32:{ *:[i32] }:$omod))  =>  (V_RSQ_F16_e64:{ *:[f16] } i32:{ *:[i32] }:$src0_modifiers, f16:{ *:[f16] }:$src0, i1:{ *:[i1] }:$clamp, i32:{ *:[i32] }:$omod)
        GIR_BuildMI, /*InsnID*/0, /*Opcode*/GIMT_Encode2(AMDGPU::V_RSQ_F16_e64),
        GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/0, // DstI[vdst]
        GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/1, // src0_modifiers
        GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/0, // src0
        GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/2, // clamp
        GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/3, // omod
        GIR_ConstrainSelectedInstOperands, /*InsnID*/0,
        GIR_EraseFromParent, /*InsnID*/0,
        // GIR_Coverage, 669,
        GIR_Done,
      // Label 3081: @197562
      GIM_Try, /*On fail goto*//*Label 3082*/ GIMT_Encode4(197628), // Rule ID 671 //
        GIM_CheckFeatures, GIMT_Encode2(GIFBS_UseRealTrue16Insts),
        GIM_CheckIntrinsicID, /*MI*/0, /*Op*/1, GIMT_Encode2(Intrinsic::amdgcn_rsq),
        GIM_CheckType, /*MI*/0, /*Op*/0, /*Type*/GILLT_s16,
        GIM_CheckType, /*MI*/0, /*Op*/2, /*Type*/GILLT_s16,
        GIM_CheckRegBankForClass, /*MI*/0, /*Op*/0, /*RC*/GIMT_Encode2(AMDGPU::VGPR_16RegClassID),
        GIM_CheckComplexPattern, /*MI*/0, /*Op*/2, /*Renderer*/GIMT_Encode2(0), GIMT_Encode2(GICP_gi_vop3mods0),
        // (intrinsic_wo_chain:{ *:[f16] } 2652:{ *:[iPTR] }, (VOP3Mods0:{ *:[f16] } f16:{ *:[f16] }:$src0, i32:{ *:[i32] }:$src0_modifiers, i1:{ *:[i1] }:$clamp, i32:{ *:[i32] }:$omod))  =>  (V_RSQ_F16_t16_e64:{ *:[f16] } i32:{ *:[i32] }:$src0_modifiers, f16:{ *:[f16] }:$src0, i1:{ *:[i1] }:$clamp, i32:{ *:[i32] }:$omod)
        GIR_BuildMI, /*InsnID*/0, /*Opcode*/GIMT_Encode2(AMDGPU::V_RSQ_F16_t16_e64),
        GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/0, // DstI[vdst]
        GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/1, // src0_modifiers
        GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/0, // src0
        GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/2, // clamp
        GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/3, // omod
        GIR_ConstrainSelectedInstOperands, /*InsnID*/0,
        GIR_EraseFromParent, /*InsnID*/0,
        // GIR_Coverage, 671,
        GIR_Done,
      // Label 3082: @197628
      GIM_Try, /*On fail goto*//*Label 3083*/ GIMT_Encode4(197694), // Rule ID 673 //
        GIM_CheckFeatures, GIMT_Encode2(GIFBS_UseFakeTrue16Insts),
        GIM_CheckIntrinsicID, /*MI*/0, /*Op*/1, GIMT_Encode2(Intrinsic::amdgcn_rsq),
        GIM_CheckType, /*MI*/0, /*Op*/0, /*Type*/GILLT_s16,
        GIM_CheckType, /*MI*/0, /*Op*/2, /*Type*/GILLT_s16,
        GIM_CheckRegBankForClass, /*MI*/0, /*Op*/0, /*RC*/GIMT_Encode2(AMDGPU::VGPR_32RegClassID),
        GIM_CheckComplexPattern, /*MI*/0, /*Op*/2, /*Renderer*/GIMT_Encode2(0), GIMT_Encode2(GICP_gi_vop3mods0),
        // (intrinsic_wo_chain:{ *:[f16] } 2652:{ *:[iPTR] }, (VOP3Mods0:{ *:[f16] } f16:{ *:[f16] }:$src0, i32:{ *:[i32] }:$src0_modifiers, i1:{ *:[i1] }:$clamp, i32:{ *:[i32] }:$omod))  =>  (V_RSQ_F16_fake16_e64:{ *:[f16] } i32:{ *:[i32] }:$src0_modifiers, f16:{ *:[f16] }:$src0, i1:{ *:[i1] }:$clamp, i32:{ *:[i32] }:$omod)
        GIR_BuildMI, /*InsnID*/0, /*Opcode*/GIMT_Encode2(AMDGPU::V_RSQ_F16_fake16_e64),
        GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/0, // DstI[vdst]
        GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/1, // src0_modifiers
        GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/0, // src0
        GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/2, // clamp
        GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/3, // omod
        GIR_ConstrainSelectedInstOperands, /*InsnID*/0,
        GIR_EraseFromParent, /*InsnID*/0,
        // GIR_Coverage, 673,
        GIR_Done,
      // Label 3083: @197694
      GIM_Try, /*On fail goto*//*Label 3084*/ GIMT_Encode4(197760), // Rule ID 675 //
        GIM_CheckFeatures, GIMT_Encode2(GIFBS_Has16BitInsts_NotHasTrue16BitInsts),
        GIM_CheckIntrinsicID, /*MI*/0, /*Op*/1, GIMT_Encode2(Intrinsic::amdgcn_log),
        GIM_CheckType, /*MI*/0, /*Op*/0, /*Type*/GILLT_s16,
        GIM_CheckType, /*MI*/0, /*Op*/2, /*Type*/GILLT_s16,
        GIM_CheckRegBankForClass, /*MI*/0, /*Op*/0, /*RC*/GIMT_Encode2(AMDGPU::VGPR_32RegClassID),
        GIM_CheckComplexPattern, /*MI*/0, /*Op*/2, /*Renderer*/GIMT_Encode2(0), GIMT_Encode2(GICP_gi_vop3mods0),
        // (intrinsic_wo_chain:{ *:[f16] } 2534:{ *:[iPTR] }, (VOP3Mods0:{ *:[f16] } f16:{ *:[f16] }:$src0, i32:{ *:[i32] }:$src0_modifiers, i1:{ *:[i1] }:$clamp, i32:{ *:[i32] }:$omod))  =>  (V_LOG_F16_e64:{ *:[f16] } i32:{ *:[i32] }:$src0_modifiers, f16:{ *:[f16] }:$src0, i1:{ *:[i1] }:$clamp, i32:{ *:[i32] }:$omod)
        GIR_BuildMI, /*InsnID*/0, /*Opcode*/GIMT_Encode2(AMDGPU::V_LOG_F16_e64),
        GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/0, // DstI[vdst]
        GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/1, // src0_modifiers
        GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/0, // src0
        GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/2, // clamp
        GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/3, // omod
        GIR_ConstrainSelectedInstOperands, /*InsnID*/0,
        GIR_EraseFromParent, /*InsnID*/0,
        // GIR_Coverage, 675,
        GIR_Done,
      // Label 3084: @197760
      GIM_Try, /*On fail goto*//*Label 3085*/ GIMT_Encode4(197826), // Rule ID 677 //
        GIM_CheckFeatures, GIMT_Encode2(GIFBS_UseRealTrue16Insts),
        GIM_CheckIntrinsicID, /*MI*/0, /*Op*/1, GIMT_Encode2(Intrinsic::amdgcn_log),
        GIM_CheckType, /*MI*/0, /*Op*/0, /*Type*/GILLT_s16,
        GIM_CheckType, /*MI*/0, /*Op*/2, /*Type*/GILLT_s16,
        GIM_CheckRegBankForClass, /*MI*/0, /*Op*/0, /*RC*/GIMT_Encode2(AMDGPU::VGPR_16RegClassID),
        GIM_CheckComplexPattern, /*MI*/0, /*Op*/2, /*Renderer*/GIMT_Encode2(0), GIMT_Encode2(GICP_gi_vop3mods0),
        // (intrinsic_wo_chain:{ *:[f16] } 2534:{ *:[iPTR] }, (VOP3Mods0:{ *:[f16] } f16:{ *:[f16] }:$src0, i32:{ *:[i32] }:$src0_modifiers, i1:{ *:[i1] }:$clamp, i32:{ *:[i32] }:$omod))  =>  (V_LOG_F16_t16_e64:{ *:[f16] } i32:{ *:[i32] }:$src0_modifiers, f16:{ *:[f16] }:$src0, i1:{ *:[i1] }:$clamp, i32:{ *:[i32] }:$omod)
        GIR_BuildMI, /*InsnID*/0, /*Opcode*/GIMT_Encode2(AMDGPU::V_LOG_F16_t16_e64),
        GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/0, // DstI[vdst]
        GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/1, // src0_modifiers
        GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/0, // src0
        GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/2, // clamp
        GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/3, // omod
        GIR_ConstrainSelectedInstOperands, /*InsnID*/0,
        GIR_EraseFromParent, /*InsnID*/0,
        // GIR_Coverage, 677,
        GIR_Done,
      // Label 3085: @197826
      GIM_Try, /*On fail goto*//*Label 3086*/ GIMT_Encode4(197892), // Rule ID 679 //
        GIM_CheckFeatures, GIMT_Encode2(GIFBS_UseFakeTrue16Insts),
        GIM_CheckIntrinsicID, /*MI*/0, /*Op*/1, GIMT_Encode2(Intrinsic::amdgcn_log),
        GIM_CheckType, /*MI*/0, /*Op*/0, /*Type*/GILLT_s16,
        GIM_CheckType, /*MI*/0, /*Op*/2, /*Type*/GILLT_s16,
        GIM_CheckRegBankForClass, /*MI*/0, /*Op*/0, /*RC*/GIMT_Encode2(AMDGPU::VGPR_32RegClassID),
        GIM_CheckComplexPattern, /*MI*/0, /*Op*/2, /*Renderer*/GIMT_Encode2(0), GIMT_Encode2(GICP_gi_vop3mods0),
        // (intrinsic_wo_chain:{ *:[f16] } 2534:{ *:[iPTR] }, (VOP3Mods0:{ *:[f16] } f16:{ *:[f16] }:$src0, i32:{ *:[i32] }:$src0_modifiers, i1:{ *:[i1] }:$clamp, i32:{ *:[i32] }:$omod))  =>  (V_LOG_F16_fake16_e64:{ *:[f16] } i32:{ *:[i32] }:$src0_modifiers, f16:{ *:[f16] }:$src0, i1:{ *:[i1] }:$clamp, i32:{ *:[i32] }:$omod)
        GIR_BuildMI, /*InsnID*/0, /*Opcode*/GIMT_Encode2(AMDGPU::V_LOG_F16_fake16_e64),
        GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/0, // DstI[vdst]
        GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/1, // src0_modifiers
        GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/0, // src0
        GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/2, // clamp
        GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/3, // omod
        GIR_ConstrainSelectedInstOperands, /*InsnID*/0,
        GIR_EraseFromParent, /*InsnID*/0,
        // GIR_Coverage, 679,
        GIR_Done,
      // Label 3086: @197892
      GIM_Try, /*On fail goto*//*Label 3087*/ GIMT_Encode4(197958), // Rule ID 681 //
        GIM_CheckFeatures, GIMT_Encode2(GIFBS_Has16BitInsts_NotHasTrue16BitInsts),
        GIM_CheckIntrinsicID, /*MI*/0, /*Op*/1, GIMT_Encode2(Intrinsic::amdgcn_exp2),
        GIM_CheckType, /*MI*/0, /*Op*/0, /*Type*/GILLT_s16,
        GIM_CheckType, /*MI*/0, /*Op*/2, /*Type*/GILLT_s16,
        GIM_CheckRegBankForClass, /*MI*/0, /*Op*/0, /*RC*/GIMT_Encode2(AMDGPU::VGPR_32RegClassID),
        GIM_CheckComplexPattern, /*MI*/0, /*Op*/2, /*Renderer*/GIMT_Encode2(0), GIMT_Encode2(GICP_gi_vop3mods0),
        // (intrinsic_wo_chain:{ *:[f16] } 1957:{ *:[iPTR] }, (VOP3Mods0:{ *:[f16] } f16:{ *:[f16] }:$src0, i32:{ *:[i32] }:$src0_modifiers, i1:{ *:[i1] }:$clamp, i32:{ *:[i32] }:$omod))  =>  (V_EXP_F16_e64:{ *:[f16] } i32:{ *:[i32] }:$src0_modifiers, f16:{ *:[f16] }:$src0, i1:{ *:[i1] }:$clamp, i32:{ *:[i32] }:$omod)
        GIR_BuildMI, /*InsnID*/0, /*Opcode*/GIMT_Encode2(AMDGPU::V_EXP_F16_e64),
        GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/0, // DstI[vdst]
        GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/1, // src0_modifiers
        GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/0, // src0
        GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/2, // clamp
        GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/3, // omod
        GIR_ConstrainSelectedInstOperands, /*InsnID*/0,
        GIR_EraseFromParent, /*InsnID*/0,
        // GIR_Coverage, 681,
        GIR_Done,
      // Label 3087: @197958
      GIM_Try, /*On fail goto*//*Label 3088*/ GIMT_Encode4(198024), // Rule ID 683 //
        GIM_CheckFeatures, GIMT_Encode2(GIFBS_UseRealTrue16Insts),
        GIM_CheckIntrinsicID, /*MI*/0, /*Op*/1, GIMT_Encode2(Intrinsic::amdgcn_exp2),
        GIM_CheckType, /*MI*/0, /*Op*/0, /*Type*/GILLT_s16,
        GIM_CheckType, /*MI*/0, /*Op*/2, /*Type*/GILLT_s16,
        GIM_CheckRegBankForClass, /*MI*/0, /*Op*/0, /*RC*/GIMT_Encode2(AMDGPU::VGPR_16RegClassID),
        GIM_CheckComplexPattern, /*MI*/0, /*Op*/2, /*Renderer*/GIMT_Encode2(0), GIMT_Encode2(GICP_gi_vop3mods0),
        // (intrinsic_wo_chain:{ *:[f16] } 1957:{ *:[iPTR] }, (VOP3Mods0:{ *:[f16] } f16:{ *:[f16] }:$src0, i32:{ *:[i32] }:$src0_modifiers, i1:{ *:[i1] }:$clamp, i32:{ *:[i32] }:$omod))  =>  (V_EXP_F16_t16_e64:{ *:[f16] } i32:{ *:[i32] }:$src0_modifiers, f16:{ *:[f16] }:$src0, i1:{ *:[i1] }:$clamp, i32:{ *:[i32] }:$omod)
        GIR_BuildMI, /*InsnID*/0, /*Opcode*/GIMT_Encode2(AMDGPU::V_EXP_F16_t16_e64),
        GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/0, // DstI[vdst]
        GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/1, // src0_modifiers
        GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/0, // src0
        GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/2, // clamp
        GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/3, // omod
        GIR_ConstrainSelectedInstOperands, /*InsnID*/0,
        GIR_EraseFromParent, /*InsnID*/0,
        // GIR_Coverage, 683,
        GIR_Done,
      // Label 3088: @198024
      GIM_Try, /*On fail goto*//*Label 3089*/ GIMT_Encode4(198090), // Rule ID 685 //
        GIM_CheckFeatures, GIMT_Encode2(GIFBS_UseFakeTrue16Insts),
        GIM_CheckIntrinsicID, /*MI*/0, /*Op*/1, GIMT_Encode2(Intrinsic::amdgcn_exp2),
        GIM_CheckType, /*MI*/0, /*Op*/0, /*Type*/GILLT_s16,
        GIM_CheckType, /*MI*/0, /*Op*/2, /*Type*/GILLT_s16,
        GIM_CheckRegBankForClass, /*MI*/0, /*Op*/0, /*RC*/GIMT_Encode2(AMDGPU::VGPR_32RegClassID),
        GIM_CheckComplexPattern, /*MI*/0, /*Op*/2, /*Renderer*/GIMT_Encode2(0), GIMT_Encode2(GICP_gi_vop3mods0),
        // (intrinsic_wo_chain:{ *:[f16] } 1957:{ *:[iPTR] }, (VOP3Mods0:{ *:[f16] } f16:{ *:[f16] }:$src0, i32:{ *:[i32] }:$src0_modifiers, i1:{ *:[i1] }:$clamp, i32:{ *:[i32] }:$omod))  =>  (V_EXP_F16_fake16_e64:{ *:[f16] } i32:{ *:[i32] }:$src0_modifiers, f16:{ *:[f16] }:$src0, i1:{ *:[i1] }:$clamp, i32:{ *:[i32] }:$omod)
        GIR_BuildMI, /*InsnID*/0, /*Opcode*/GIMT_Encode2(AMDGPU::V_EXP_F16_fake16_e64),
        GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/0, // DstI[vdst]
        GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/1, // src0_modifiers
        GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/0, // src0
        GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/2, // clamp
        GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/3, // omod
        GIR_ConstrainSelectedInstOperands, /*InsnID*/0,
        GIR_EraseFromParent, /*InsnID*/0,
        // GIR_Coverage, 685,
        GIR_Done,
      // Label 3089: @198090
      GIM_Try, /*On fail goto*//*Label 3090*/ GIMT_Encode4(198156), // Rule ID 687 //
        GIM_CheckFeatures, GIMT_Encode2(GIFBS_Has16BitInsts_NotHasTrue16BitInsts),
        GIM_CheckIntrinsicID, /*MI*/0, /*Op*/1, GIMT_Encode2(Intrinsic::amdgcn_sin),
        GIM_CheckType, /*MI*/0, /*Op*/0, /*Type*/GILLT_s16,
        GIM_CheckType, /*MI*/0, /*Op*/2, /*Type*/GILLT_s16,
        GIM_CheckRegBankForClass, /*MI*/0, /*Op*/0, /*RC*/GIMT_Encode2(AMDGPU::VGPR_32RegClassID),
        GIM_CheckComplexPattern, /*MI*/0, /*Op*/2, /*Renderer*/GIMT_Encode2(0), GIMT_Encode2(GICP_gi_vop3mods0),
        // (intrinsic_wo_chain:{ *:[f16] } 2713:{ *:[iPTR] }, (VOP3Mods0:{ *:[f16] } f16:{ *:[f16] }:$src0, i32:{ *:[i32] }:$src0_modifiers, i1:{ *:[i1] }:$clamp, i32:{ *:[i32] }:$omod))  =>  (V_SIN_F16_e64:{ *:[f16] } i32:{ *:[i32] }:$src0_modifiers, f16:{ *:[f16] }:$src0, i1:{ *:[i1] }:$clamp, i32:{ *:[i32] }:$omod)
        GIR_BuildMI, /*InsnID*/0, /*Opcode*/GIMT_Encode2(AMDGPU::V_SIN_F16_e64),
        GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/0, // DstI[vdst]
        GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/1, // src0_modifiers
        GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/0, // src0
        GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/2, // clamp
        GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/3, // omod
        GIR_ConstrainSelectedInstOperands, /*InsnID*/0,
        GIR_EraseFromParent, /*InsnID*/0,
        // GIR_Coverage, 687,
        GIR_Done,
      // Label 3090: @198156
      GIM_Try, /*On fail goto*//*Label 3091*/ GIMT_Encode4(198222), // Rule ID 689 //
        GIM_CheckFeatures, GIMT_Encode2(GIFBS_UseRealTrue16Insts),
        GIM_CheckIntrinsicID, /*MI*/0, /*Op*/1, GIMT_Encode2(Intrinsic::amdgcn_sin),
        GIM_CheckType, /*MI*/0, /*Op*/0, /*Type*/GILLT_s16,
        GIM_CheckType, /*MI*/0, /*Op*/2, /*Type*/GILLT_s16,
        GIM_CheckRegBankForClass, /*MI*/0, /*Op*/0, /*RC*/GIMT_Encode2(AMDGPU::VGPR_16RegClassID),
        GIM_CheckComplexPattern, /*MI*/0, /*Op*/2, /*Renderer*/GIMT_Encode2(0), GIMT_Encode2(GICP_gi_vop3mods0),
        // (intrinsic_wo_chain:{ *:[f16] } 2713:{ *:[iPTR] }, (VOP3Mods0:{ *:[f16] } f16:{ *:[f16] }:$src0, i32:{ *:[i32] }:$src0_modifiers, i1:{ *:[i1] }:$clamp, i32:{ *:[i32] }:$omod))  =>  (V_SIN_F16_t16_e64:{ *:[f16] } i32:{ *:[i32] }:$src0_modifiers, f16:{ *:[f16] }:$src0, i1:{ *:[i1] }:$clamp, i32:{ *:[i32] }:$omod)
        GIR_BuildMI, /*InsnID*/0, /*Opcode*/GIMT_Encode2(AMDGPU::V_SIN_F16_t16_e64),
        GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/0, // DstI[vdst]
        GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/1, // src0_modifiers
        GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/0, // src0
        GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/2, // clamp
        GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/3, // omod
        GIR_ConstrainSelectedInstOperands, /*InsnID*/0,
        GIR_EraseFromParent, /*InsnID*/0,
        // GIR_Coverage, 689,
        GIR_Done,
      // Label 3091: @198222
      GIM_Try, /*On fail goto*//*Label 3092*/ GIMT_Encode4(198288), // Rule ID 691 //
        GIM_CheckFeatures, GIMT_Encode2(GIFBS_UseFakeTrue16Insts),
        GIM_CheckIntrinsicID, /*MI*/0, /*Op*/1, GIMT_Encode2(Intrinsic::amdgcn_sin),
        GIM_CheckType, /*MI*/0, /*Op*/0, /*Type*/GILLT_s16,
        GIM_CheckType, /*MI*/0, /*Op*/2, /*Type*/GILLT_s16,
        GIM_CheckRegBankForClass, /*MI*/0, /*Op*/0, /*RC*/GIMT_Encode2(AMDGPU::VGPR_32RegClassID),
        GIM_CheckComplexPattern, /*MI*/0, /*Op*/2, /*Renderer*/GIMT_Encode2(0), GIMT_Encode2(GICP_gi_vop3mods0),
        // (intrinsic_wo_chain:{ *:[f16] } 2713:{ *:[iPTR] }, (VOP3Mods0:{ *:[f16] } f16:{ *:[f16] }:$src0, i32:{ *:[i32] }:$src0_modifiers, i1:{ *:[i1] }:$clamp, i32:{ *:[i32] }:$omod))  =>  (V_SIN_F16_fake16_e64:{ *:[f16] } i32:{ *:[i32] }:$src0_modifiers, f16:{ *:[f16] }:$src0, i1:{ *:[i1] }:$clamp, i32:{ *:[i32] }:$omod)
        GIR_BuildMI, /*InsnID*/0, /*Opcode*/GIMT_Encode2(AMDGPU::V_SIN_F16_fake16_e64),
        GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/0, // DstI[vdst]
        GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/1, // src0_modifiers
        GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/0, // src0
        GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/2, // clamp
        GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/3, // omod
        GIR_ConstrainSelectedInstOperands, /*InsnID*/0,
        GIR_EraseFromParent, /*InsnID*/0,
        // GIR_Coverage, 691,
        GIR_Done,
      // Label 3092: @198288
      GIM_Try, /*On fail goto*//*Label 3093*/ GIMT_Encode4(198354), // Rule ID 693 //
        GIM_CheckFeatures, GIMT_Encode2(GIFBS_Has16BitInsts_NotHasTrue16BitInsts),
        GIM_CheckIntrinsicID, /*MI*/0, /*Op*/1, GIMT_Encode2(Intrinsic::amdgcn_cos),
        GIM_CheckType, /*MI*/0, /*Op*/0, /*Type*/GILLT_s16,
        GIM_CheckType, /*MI*/0, /*Op*/2, /*Type*/GILLT_s16,
        GIM_CheckRegBankForClass, /*MI*/0, /*Op*/0, /*RC*/GIMT_Encode2(AMDGPU::VGPR_32RegClassID),
        GIM_CheckComplexPattern, /*MI*/0, /*Op*/2, /*Renderer*/GIMT_Encode2(0), GIMT_Encode2(GICP_gi_vop3mods0),
        // (intrinsic_wo_chain:{ *:[f16] } 1902:{ *:[iPTR] }, (VOP3Mods0:{ *:[f16] } f16:{ *:[f16] }:$src0, i32:{ *:[i32] }:$src0_modifiers, i1:{ *:[i1] }:$clamp, i32:{ *:[i32] }:$omod))  =>  (V_COS_F16_e64:{ *:[f16] } i32:{ *:[i32] }:$src0_modifiers, f16:{ *:[f16] }:$src0, i1:{ *:[i1] }:$clamp, i32:{ *:[i32] }:$omod)
        GIR_BuildMI, /*InsnID*/0, /*Opcode*/GIMT_Encode2(AMDGPU::V_COS_F16_e64),
        GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/0, // DstI[vdst]
        GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/1, // src0_modifiers
        GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/0, // src0
        GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/2, // clamp
        GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/3, // omod
        GIR_ConstrainSelectedInstOperands, /*InsnID*/0,
        GIR_EraseFromParent, /*InsnID*/0,
        // GIR_Coverage, 693,
        GIR_Done,
      // Label 3093: @198354
      GIM_Try, /*On fail goto*//*Label 3094*/ GIMT_Encode4(198420), // Rule ID 695 //
        GIM_CheckFeatures, GIMT_Encode2(GIFBS_UseRealTrue16Insts),
        GIM_CheckIntrinsicID, /*MI*/0, /*Op*/1, GIMT_Encode2(Intrinsic::amdgcn_cos),
        GIM_CheckType, /*MI*/0, /*Op*/0, /*Type*/GILLT_s16,
        GIM_CheckType, /*MI*/0, /*Op*/2, /*Type*/GILLT_s16,
        GIM_CheckRegBankForClass, /*MI*/0, /*Op*/0, /*RC*/GIMT_Encode2(AMDGPU::VGPR_16RegClassID),
        GIM_CheckComplexPattern, /*MI*/0, /*Op*/2, /*Renderer*/GIMT_Encode2(0), GIMT_Encode2(GICP_gi_vop3mods0),
        // (intrinsic_wo_chain:{ *:[f16] } 1902:{ *:[iPTR] }, (VOP3Mods0:{ *:[f16] } f16:{ *:[f16] }:$src0, i32:{ *:[i32] }:$src0_modifiers, i1:{ *:[i1] }:$clamp, i32:{ *:[i32] }:$omod))  =>  (V_COS_F16_t16_e64:{ *:[f16] } i32:{ *:[i32] }:$src0_modifiers, f16:{ *:[f16] }:$src0, i1:{ *:[i1] }:$clamp, i32:{ *:[i32] }:$omod)
        GIR_BuildMI, /*InsnID*/0, /*Opcode*/GIMT_Encode2(AMDGPU::V_COS_F16_t16_e64),
        GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/0, // DstI[vdst]
        GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/1, // src0_modifiers
        GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/0, // src0
        GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/2, // clamp
        GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/3, // omod
        GIR_ConstrainSelectedInstOperands, /*InsnID*/0,
        GIR_EraseFromParent, /*InsnID*/0,
        // GIR_Coverage, 695,
        GIR_Done,
      // Label 3094: @198420
      GIM_Try, /*On fail goto*//*Label 3095*/ GIMT_Encode4(198486), // Rule ID 697 //
        GIM_CheckFeatures, GIMT_Encode2(GIFBS_UseFakeTrue16Insts),
        GIM_CheckIntrinsicID, /*MI*/0, /*Op*/1, GIMT_Encode2(Intrinsic::amdgcn_cos),
        GIM_CheckType, /*MI*/0, /*Op*/0, /*Type*/GILLT_s16,
        GIM_CheckType, /*MI*/0, /*Op*/2, /*Type*/GILLT_s16,
        GIM_CheckRegBankForClass, /*MI*/0, /*Op*/0, /*RC*/GIMT_Encode2(AMDGPU::VGPR_32RegClassID),
        GIM_CheckComplexPattern, /*MI*/0, /*Op*/2, /*Renderer*/GIMT_Encode2(0), GIMT_Encode2(GICP_gi_vop3mods0),
        // (intrinsic_wo_chain:{ *:[f16] } 1902:{ *:[iPTR] }, (VOP3Mods0:{ *:[f16] } f16:{ *:[f16] }:$src0, i32:{ *:[i32] }:$src0_modifiers, i1:{ *:[i1] }:$clamp, i32:{ *:[i32] }:$omod))  =>  (V_COS_F16_fake16_e64:{ *:[f16] } i32:{ *:[i32] }:$src0_modifiers, f16:{ *:[f16] }:$src0, i1:{ *:[i1] }:$clamp, i32:{ *:[i32] }:$omod)
        GIR_BuildMI, /*InsnID*/0, /*Opcode*/GIMT_Encode2(AMDGPU::V_COS_F16_fake16_e64),
        GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/0, // DstI[vdst]
        GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/1, // src0_modifiers
        GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/0, // src0
        GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/2, // clamp
        GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/3, // omod
        GIR_ConstrainSelectedInstOperands, /*InsnID*/0,
        GIR_EraseFromParent, /*InsnID*/0,
        // GIR_Coverage, 697,
        GIR_Done,
      // Label 3095: @198486
      GIM_Try, /*On fail goto*//*Label 3096*/ GIMT_Encode4(198552), // Rule ID 699 //
        GIM_CheckFeatures, GIMT_Encode2(GIFBS_Has16BitInsts_NotHasTrue16BitInsts),
        GIM_CheckIntrinsicID, /*MI*/0, /*Op*/1, GIMT_Encode2(Intrinsic::amdgcn_frexp_mant),
        GIM_CheckType, /*MI*/0, /*Op*/0, /*Type*/GILLT_s16,
        GIM_CheckType, /*MI*/0, /*Op*/2, /*Type*/GILLT_s16,
        GIM_CheckRegBankForClass, /*MI*/0, /*Op*/0, /*RC*/GIMT_Encode2(AMDGPU::VGPR_32RegClassID),
        GIM_CheckComplexPattern, /*MI*/0, /*Op*/2, /*Renderer*/GIMT_Encode2(0), GIMT_Encode2(GICP_gi_vop3mods0),
        // (intrinsic_wo_chain:{ *:[f16] } 1976:{ *:[iPTR] }, (VOP3Mods0:{ *:[f16] } f16:{ *:[f16] }:$src0, i32:{ *:[i32] }:$src0_modifiers, i1:{ *:[i1] }:$clamp, i32:{ *:[i32] }:$omod))  =>  (V_FREXP_MANT_F16_e64:{ *:[f16] } i32:{ *:[i32] }:$src0_modifiers, f16:{ *:[f16] }:$src0, i1:{ *:[i1] }:$clamp, i32:{ *:[i32] }:$omod)
        GIR_BuildMI, /*InsnID*/0, /*Opcode*/GIMT_Encode2(AMDGPU::V_FREXP_MANT_F16_e64),
        GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/0, // DstI[vdst]
        GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/1, // src0_modifiers
        GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/0, // src0
        GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/2, // clamp
        GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/3, // omod
        GIR_ConstrainSelectedInstOperands, /*InsnID*/0,
        GIR_EraseFromParent, /*InsnID*/0,
        // GIR_Coverage, 699,
        GIR_Done,
      // Label 3096: @198552
      GIM_Try, /*On fail goto*//*Label 3097*/ GIMT_Encode4(198618), // Rule ID 700 //
        GIM_CheckFeatures, GIMT_Encode2(GIFBS_UseRealTrue16Insts),
        GIM_CheckIntrinsicID, /*MI*/0, /*Op*/1, GIMT_Encode2(Intrinsic::amdgcn_frexp_mant),
        GIM_CheckType, /*MI*/0, /*Op*/0, /*Type*/GILLT_s16,
        GIM_CheckType, /*MI*/0, /*Op*/2, /*Type*/GILLT_s16,
        GIM_CheckRegBankForClass, /*MI*/0, /*Op*/0, /*RC*/GIMT_Encode2(AMDGPU::VGPR_16RegClassID),
        GIM_CheckComplexPattern, /*MI*/0, /*Op*/2, /*Renderer*/GIMT_Encode2(0), GIMT_Encode2(GICP_gi_vop3mods0),
        // (intrinsic_wo_chain:{ *:[f16] } 1976:{ *:[iPTR] }, (VOP3Mods0:{ *:[f16] } f16:{ *:[f16] }:$src0, i32:{ *:[i32] }:$src0_modifiers, i1:{ *:[i1] }:$clamp, i32:{ *:[i32] }:$omod))  =>  (V_FREXP_MANT_F16_t16_e64:{ *:[f16] } i32:{ *:[i32] }:$src0_modifiers, f16:{ *:[f16] }:$src0, i1:{ *:[i1] }:$clamp, i32:{ *:[i32] }:$omod)
        GIR_BuildMI, /*InsnID*/0, /*Opcode*/GIMT_Encode2(AMDGPU::V_FREXP_MANT_F16_t16_e64),
        GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/0, // DstI[vdst]
        GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/1, // src0_modifiers
        GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/0, // src0
        GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/2, // clamp
        GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/3, // omod
        GIR_ConstrainSelectedInstOperands, /*InsnID*/0,
        GIR_EraseFromParent, /*InsnID*/0,
        // GIR_Coverage, 700,
        GIR_Done,
      // Label 3097: @198618
      GIM_Try, /*On fail goto*//*Label 3098*/ GIMT_Encode4(198684), // Rule ID 701 //
        GIM_CheckFeatures, GIMT_Encode2(GIFBS_UseFakeTrue16Insts),
        GIM_CheckIntrinsicID, /*MI*/0, /*Op*/1, GIMT_Encode2(Intrinsic::amdgcn_frexp_mant),
        GIM_CheckType, /*MI*/0, /*Op*/0, /*Type*/GILLT_s16,
        GIM_CheckType, /*MI*/0, /*Op*/2, /*Type*/GILLT_s16,
        GIM_CheckRegBankForClass, /*MI*/0, /*Op*/0, /*RC*/GIMT_Encode2(AMDGPU::VGPR_32RegClassID),
        GIM_CheckComplexPattern, /*MI*/0, /*Op*/2, /*Renderer*/GIMT_Encode2(0), GIMT_Encode2(GICP_gi_vop3mods0),
        // (intrinsic_wo_chain:{ *:[f16] } 1976:{ *:[iPTR] }, (VOP3Mods0:{ *:[f16] } f16:{ *:[f16] }:$src0, i32:{ *:[i32] }:$src0_modifiers, i1:{ *:[i1] }:$clamp, i32:{ *:[i32] }:$omod))  =>  (V_FREXP_MANT_F16_fake16_e64:{ *:[f16] } i32:{ *:[i32] }:$src0_modifiers, f16:{ *:[f16] }:$src0, i1:{ *:[i1] }:$clamp, i32:{ *:[i32] }:$omod)
        GIR_BuildMI, /*InsnID*/0, /*Opcode*/GIMT_Encode2(AMDGPU::V_FREXP_MANT_F16_fake16_e64),
        GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/0, // DstI[vdst]
        GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/1, // src0_modifiers
        GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/0, // src0
        GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/2, // clamp
        GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/3, // omod
        GIR_ConstrainSelectedInstOperands, /*InsnID*/0,
        GIR_EraseFromParent, /*InsnID*/0,
        // GIR_Coverage, 701,
        GIR_Done,
      // Label 3098: @198684
      GIM_Try, /*On fail goto*//*Label 3099*/ GIMT_Encode4(198750), // Rule ID 702 //
        GIM_CheckFeatures, GIMT_Encode2(GIFBS_Has16BitInsts_NotHasTrue16BitInsts),
        GIM_CheckIntrinsicID, /*MI*/0, /*Op*/1, GIMT_Encode2(Intrinsic::amdgcn_frexp_exp),
        GIM_CheckType, /*MI*/0, /*Op*/0, /*Type*/GILLT_s16,
        GIM_CheckType, /*MI*/0, /*Op*/2, /*Type*/GILLT_s16,
        GIM_CheckRegBankForClass, /*MI*/0, /*Op*/0, /*RC*/GIMT_Encode2(AMDGPU::VGPR_32RegClassID),
        GIM_CheckComplexPattern, /*MI*/0, /*Op*/2, /*Renderer*/GIMT_Encode2(0), GIMT_Encode2(GICP_gi_vop3mods0),
        // (intrinsic_wo_chain:{ *:[i16] } 1975:{ *:[iPTR] }, (VOP3Mods0:{ *:[f16] } f16:{ *:[f16] }:$src0, i32:{ *:[i32] }:$src0_modifiers, i1:{ *:[i1] }:$clamp, i32:{ *:[i32] }:$omod))  =>  (V_FREXP_EXP_I16_F16_e64:{ *:[i16] } i32:{ *:[i32] }:$src0_modifiers, f16:{ *:[f16] }:$src0, i1:{ *:[i1] }:$clamp, i32:{ *:[i32] }:$omod)
        GIR_BuildMI, /*InsnID*/0, /*Opcode*/GIMT_Encode2(AMDGPU::V_FREXP_EXP_I16_F16_e64),
        GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/0, // DstI[vdst]
        GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/1, // src0_modifiers
        GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/0, // src0
        GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/2, // clamp
        GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/3, // omod
        GIR_ConstrainSelectedInstOperands, /*InsnID*/0,
        GIR_EraseFromParent, /*InsnID*/0,
        // GIR_Coverage, 702,
        GIR_Done,
      // Label 3099: @198750
      GIM_Try, /*On fail goto*//*Label 3100*/ GIMT_Encode4(198816), // Rule ID 703 //
        GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasTrue16BitInsts),
        GIM_CheckIntrinsicID, /*MI*/0, /*Op*/1, GIMT_Encode2(Intrinsic::amdgcn_frexp_exp),
        GIM_CheckType, /*MI*/0, /*Op*/0, /*Type*/GILLT_s16,
        GIM_CheckType, /*MI*/0, /*Op*/2, /*Type*/GILLT_s16,
        GIM_CheckRegBankForClass, /*MI*/0, /*Op*/0, /*RC*/GIMT_Encode2(AMDGPU::VGPR_32RegClassID),
        GIM_CheckComplexPattern, /*MI*/0, /*Op*/2, /*Renderer*/GIMT_Encode2(0), GIMT_Encode2(GICP_gi_vop3mods0),
        // (intrinsic_wo_chain:{ *:[i16] } 1975:{ *:[iPTR] }, (VOP3Mods0:{ *:[f16] } f16:{ *:[f16] }:$src0, i32:{ *:[i32] }:$src0_modifiers, i1:{ *:[i1] }:$clamp, i32:{ *:[i32] }:$omod))  =>  (V_FREXP_EXP_I16_F16_t16_e64:{ *:[i16] } i32:{ *:[i32] }:$src0_modifiers, f16:{ *:[f16] }:$src0, i1:{ *:[i1] }:$clamp, i32:{ *:[i32] }:$omod)
        GIR_BuildMI, /*InsnID*/0, /*Opcode*/GIMT_Encode2(AMDGPU::V_FREXP_EXP_I16_F16_t16_e64),
        GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/0, // DstI[vdst]
        GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/1, // src0_modifiers
        GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/0, // src0
        GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/2, // clamp
        GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/3, // omod
        GIR_ConstrainSelectedInstOperands, /*InsnID*/0,
        GIR_EraseFromParent, /*InsnID*/0,
        // GIR_Coverage, 703,
        GIR_Done,
      // Label 3100: @198816
      GIM_Try, /*On fail goto*//*Label 3101*/ GIMT_Encode4(198882), // Rule ID 716 //
        GIM_CheckFeatures, GIMT_Encode2(GIFBS_Has16BitInsts_NotHasTrue16BitInsts),
        GIM_CheckIntrinsicID, /*MI*/0, /*Op*/1, GIMT_Encode2(Intrinsic::amdgcn_fract),
        GIM_CheckType, /*MI*/0, /*Op*/0, /*Type*/GILLT_s16,
        GIM_CheckType, /*MI*/0, /*Op*/2, /*Type*/GILLT_s16,
        GIM_CheckRegBankForClass, /*MI*/0, /*Op*/0, /*RC*/GIMT_Encode2(AMDGPU::VGPR_32RegClassID),
        GIM_CheckComplexPattern, /*MI*/0, /*Op*/2, /*Renderer*/GIMT_Encode2(0), GIMT_Encode2(GICP_gi_vop3mods0),
        // (intrinsic_wo_chain:{ *:[f16] } 1974:{ *:[iPTR] }, (VOP3Mods0:{ *:[f16] } f16:{ *:[f16] }:$src0, i32:{ *:[i32] }:$src0_modifiers, i1:{ *:[i1] }:$clamp, i32:{ *:[i32] }:$omod))  =>  (V_FRACT_F16_e64:{ *:[f16] } i32:{ *:[i32] }:$src0_modifiers, f16:{ *:[f16] }:$src0, i1:{ *:[i1] }:$clamp, i32:{ *:[i32] }:$omod)
        GIR_BuildMI, /*InsnID*/0, /*Opcode*/GIMT_Encode2(AMDGPU::V_FRACT_F16_e64),
        GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/0, // DstI[vdst]
        GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/1, // src0_modifiers
        GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/0, // src0
        GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/2, // clamp
        GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/3, // omod
        GIR_ConstrainSelectedInstOperands, /*InsnID*/0,
        GIR_EraseFromParent, /*InsnID*/0,
        // GIR_Coverage, 716,
        GIR_Done,
      // Label 3101: @198882
      GIM_Try, /*On fail goto*//*Label 3102*/ GIMT_Encode4(198948), // Rule ID 718 //
        GIM_CheckFeatures, GIMT_Encode2(GIFBS_UseRealTrue16Insts),
        GIM_CheckIntrinsicID, /*MI*/0, /*Op*/1, GIMT_Encode2(Intrinsic::amdgcn_fract),
        GIM_CheckType, /*MI*/0, /*Op*/0, /*Type*/GILLT_s16,
        GIM_CheckType, /*MI*/0, /*Op*/2, /*Type*/GILLT_s16,
        GIM_CheckRegBankForClass, /*MI*/0, /*Op*/0, /*RC*/GIMT_Encode2(AMDGPU::VGPR_16RegClassID),
        GIM_CheckComplexPattern, /*MI*/0, /*Op*/2, /*Renderer*/GIMT_Encode2(0), GIMT_Encode2(GICP_gi_vop3mods0),
        // (intrinsic_wo_chain:{ *:[f16] } 1974:{ *:[iPTR] }, (VOP3Mods0:{ *:[f16] } f16:{ *:[f16] }:$src0, i32:{ *:[i32] }:$src0_modifiers, i1:{ *:[i1] }:$clamp, i32:{ *:[i32] }:$omod))  =>  (V_FRACT_F16_t16_e64:{ *:[f16] } i32:{ *:[i32] }:$src0_modifiers, f16:{ *:[f16] }:$src0, i1:{ *:[i1] }:$clamp, i32:{ *:[i32] }:$omod)
        GIR_BuildMI, /*InsnID*/0, /*Opcode*/GIMT_Encode2(AMDGPU::V_FRACT_F16_t16_e64),
        GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/0, // DstI[vdst]
        GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/1, // src0_modifiers
        GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/0, // src0
        GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/2, // clamp
        GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/3, // omod
        GIR_ConstrainSelectedInstOperands, /*InsnID*/0,
        GIR_EraseFromParent, /*InsnID*/0,
        // GIR_Coverage, 718,
        GIR_Done,
      // Label 3102: @198948
      GIM_Try, /*On fail goto*//*Label 3103*/ GIMT_Encode4(199014), // Rule ID 720 //
        GIM_CheckFeatures, GIMT_Encode2(GIFBS_UseFakeTrue16Insts),
        GIM_CheckIntrinsicID, /*MI*/0, /*Op*/1, GIMT_Encode2(Intrinsic::amdgcn_fract),
        GIM_CheckType, /*MI*/0, /*Op*/0, /*Type*/GILLT_s16,
        GIM_CheckType, /*MI*/0, /*Op*/2, /*Type*/GILLT_s16,
        GIM_CheckRegBankForClass, /*MI*/0, /*Op*/0, /*RC*/GIMT_Encode2(AMDGPU::VGPR_32RegClassID),
        GIM_CheckComplexPattern, /*MI*/0, /*Op*/2, /*Renderer*/GIMT_Encode2(0), GIMT_Encode2(GICP_gi_vop3mods0),
        // (intrinsic_wo_chain:{ *:[f16] } 1974:{ *:[iPTR] }, (VOP3Mods0:{ *:[f16] } f16:{ *:[f16] }:$src0, i32:{ *:[i32] }:$src0_modifiers, i1:{ *:[i1] }:$clamp, i32:{ *:[i32] }:$omod))  =>  (V_FRACT_F16_fake16_e64:{ *:[f16] } i32:{ *:[i32] }:$src0_modifiers, f16:{ *:[f16] }:$src0, i1:{ *:[i1] }:$clamp, i32:{ *:[i32] }:$omod)
        GIR_BuildMI, /*InsnID*/0, /*Opcode*/GIMT_Encode2(AMDGPU::V_FRACT_F16_fake16_e64),
        GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/0, // DstI[vdst]
        GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/1, // src0_modifiers
        GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/0, // src0
        GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/2, // clamp
        GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/3, // omod
        GIR_ConstrainSelectedInstOperands, /*InsnID*/0,
        GIR_EraseFromParent, /*InsnID*/0,
        // GIR_Coverage, 720,
        GIR_Done,
      // Label 3103: @199014
      GIM_Reject,
    // Label 3041: @199015
    GIM_Try, /*On fail goto*//*Label 3104*/ GIMT_Encode4(202281),
      GIM_CheckNumOperands, /*MI*/0, /*Expected*/4,
      GIM_Try, /*On fail goto*//*Label 3105*/ GIMT_Encode4(199089), // Rule ID 2054 //
        GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasCvtFP8VOP1Bug_isGFX9Only),
        GIM_CheckIntrinsicID, /*MI*/0, /*Op*/1, GIMT_Encode2(Intrinsic::amdgcn_cvt_f32_fp8),
        GIM_CheckType, /*MI*/0, /*Op*/0, /*Type*/GILLT_s32,
        GIM_CheckType, /*MI*/0, /*Op*/2, /*Type*/GILLT_s32,
        GIM_CheckRegBankForClass, /*MI*/0, /*Op*/0, /*RC*/GIMT_Encode2(AMDGPU::VGPR_32RegClassID),
        // MIs[0] Operand 3
        GIM_CheckLiteralInt, /*MI*/0, /*Op*/3, GIMT_Encode8(0),
        // (intrinsic_wo_chain:{ *:[f32] } 1909:{ *:[iPTR] }, i32:{ *:[i32] }:$src, 0:{ *:[i32] })  =>  (V_CVT_F32_FP8_sdwa:{ *:[f32] } 0:{ *:[i32] }, ?:{ *:[i32] }:$src, 0:{ *:[i1] }, 0:{ *:[i32] }, 0:{ *:[i32] })
        GIR_BuildMI, /*InsnID*/0, /*Opcode*/GIMT_Encode2(AMDGPU::V_CVT_F32_FP8_sdwa),
        GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/0, // DstI[vdst]
        GIR_AddImm8, /*InsnID*/0, /*Imm*/0,
        GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/2, // src
        GIR_AddImm8, /*InsnID*/0, /*Imm*/0,
        GIR_AddImm8, /*InsnID*/0, /*Imm*/0,
        GIR_AddImm8, /*InsnID*/0, /*Imm*/0,
        GIR_ConstrainSelectedInstOperands, /*InsnID*/0,
        GIR_EraseFromParent, /*InsnID*/0,
        // GIR_Coverage, 2054,
        GIR_Done,
      // Label 3105: @199089
      GIM_Try, /*On fail goto*//*Label 3106*/ GIMT_Encode4(199155), // Rule ID 2055 //
        GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasCvtFP8VOP1Bug_isGFX9Only),
        GIM_CheckIntrinsicID, /*MI*/0, /*Op*/1, GIMT_Encode2(Intrinsic::amdgcn_cvt_f32_bf8),
        GIM_CheckType, /*MI*/0, /*Op*/0, /*Type*/GILLT_s32,
        GIM_CheckType, /*MI*/0, /*Op*/2, /*Type*/GILLT_s32,
        GIM_CheckRegBankForClass, /*MI*/0, /*Op*/0, /*RC*/GIMT_Encode2(AMDGPU::VGPR_32RegClassID),
        // MIs[0] Operand 3
        GIM_CheckLiteralInt, /*MI*/0, /*Op*/3, GIMT_Encode8(0),
        // (intrinsic_wo_chain:{ *:[f32] } 1908:{ *:[iPTR] }, i32:{ *:[i32] }:$src, 0:{ *:[i32] })  =>  (V_CVT_F32_BF8_sdwa:{ *:[f32] } 0:{ *:[i32] }, ?:{ *:[i32] }:$src, 0:{ *:[i1] }, 0:{ *:[i32] }, 0:{ *:[i32] })
        GIR_BuildMI, /*InsnID*/0, /*Opcode*/GIMT_Encode2(AMDGPU::V_CVT_F32_BF8_sdwa),
        GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/0, // DstI[vdst]
        GIR_AddImm8, /*InsnID*/0, /*Imm*/0,
        GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/2, // src
        GIR_AddImm8, /*InsnID*/0, /*Imm*/0,
        GIR_AddImm8, /*InsnID*/0, /*Imm*/0,
        GIR_AddImm8, /*InsnID*/0, /*Imm*/0,
        GIR_ConstrainSelectedInstOperands, /*InsnID*/0,
        GIR_EraseFromParent, /*InsnID*/0,
        // GIR_Coverage, 2055,
        GIR_Done,
      // Label 3106: @199155
      GIM_Try, /*On fail goto*//*Label 3107*/ GIMT_Encode4(199209), // Rule ID 2056 //
        GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasNoCvtFP8VOP1Bug_isGFX9Only),
        GIM_CheckIntrinsicID, /*MI*/0, /*Op*/1, GIMT_Encode2(Intrinsic::amdgcn_cvt_f32_fp8),
        GIM_CheckType, /*MI*/0, /*Op*/0, /*Type*/GILLT_s32,
        GIM_CheckType, /*MI*/0, /*Op*/2, /*Type*/GILLT_s32,
        GIM_CheckRegBankForClass, /*MI*/0, /*Op*/0, /*RC*/GIMT_Encode2(AMDGPU::VGPR_32RegClassID),
        // MIs[0] Operand 3
        GIM_CheckLiteralInt, /*MI*/0, /*Op*/3, GIMT_Encode8(0),
        // (intrinsic_wo_chain:{ *:[f32] } 1909:{ *:[iPTR] }, i32:{ *:[i32] }:$src, 0:{ *:[i32] })  =>  (V_CVT_F32_FP8_e32:{ *:[f32] } ?:{ *:[i32] }:$src)
        GIR_BuildMI, /*InsnID*/0, /*Opcode*/GIMT_Encode2(AMDGPU::V_CVT_F32_FP8_e32),
        GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/0, // DstI[vdst]
        GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/2, // src
        GIR_ConstrainSelectedInstOperands, /*InsnID*/0,
        GIR_EraseFromParent, /*InsnID*/0,
        // GIR_Coverage, 2056,
        GIR_Done,
      // Label 3107: @199209
      GIM_Try, /*On fail goto*//*Label 3108*/ GIMT_Encode4(199263), // Rule ID 2057 //
        GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasNoCvtFP8VOP1Bug_isGFX9Only),
        GIM_CheckIntrinsicID, /*MI*/0, /*Op*/1, GIMT_Encode2(Intrinsic::amdgcn_cvt_f32_bf8),
        GIM_CheckType, /*MI*/0, /*Op*/0, /*Type*/GILLT_s32,
        GIM_CheckType, /*MI*/0, /*Op*/2, /*Type*/GILLT_s32,
        GIM_CheckRegBankForClass, /*MI*/0, /*Op*/0, /*RC*/GIMT_Encode2(AMDGPU::VGPR_32RegClassID),
        // MIs[0] Operand 3
        GIM_CheckLiteralInt, /*MI*/0, /*Op*/3, GIMT_Encode8(0),
        // (intrinsic_wo_chain:{ *:[f32] } 1908:{ *:[iPTR] }, i32:{ *:[i32] }:$src, 0:{ *:[i32] })  =>  (V_CVT_F32_BF8_e32:{ *:[f32] } ?:{ *:[i32] }:$src)
        GIR_BuildMI, /*InsnID*/0, /*Opcode*/GIMT_Encode2(AMDGPU::V_CVT_F32_BF8_e32),
        GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/0, // DstI[vdst]
        GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/2, // src
        GIR_ConstrainSelectedInstOperands, /*InsnID*/0,
        GIR_EraseFromParent, /*InsnID*/0,
        // GIR_Coverage, 2057,
        GIR_Done,
      // Label 3108: @199263
      GIM_Try, /*On fail goto*//*Label 3109*/ GIMT_Encode4(199329), // Rule ID 2058 //
        GIM_CheckFeatures, GIMT_Encode2(GIFBS_isGFX9Only),
        GIM_CheckIntrinsicID, /*MI*/0, /*Op*/1, GIMT_Encode2(Intrinsic::amdgcn_cvt_f32_fp8),
        GIM_CheckType, /*MI*/0, /*Op*/0, /*Type*/GILLT_s32,
        GIM_CheckType, /*MI*/0, /*Op*/2, /*Type*/GILLT_s32,
        GIM_CheckRegBankForClass, /*MI*/0, /*Op*/0, /*RC*/GIMT_Encode2(AMDGPU::VGPR_32RegClassID),
        // MIs[0] Operand 3
        GIM_CheckLiteralInt, /*MI*/0, /*Op*/3, GIMT_Encode8(1),
        // (intrinsic_wo_chain:{ *:[f32] } 1909:{ *:[iPTR] }, i32:{ *:[i32] }:$src, 1:{ *:[i32] })  =>  (V_CVT_F32_FP8_sdwa:{ *:[f32] } 0:{ *:[i32] }, ?:{ *:[i32] }:$src, 0:{ *:[i1] }, 0:{ *:[i32] }, 1:{ *:[i32] })
        GIR_BuildMI, /*InsnID*/0, /*Opcode*/GIMT_Encode2(AMDGPU::V_CVT_F32_FP8_sdwa),
        GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/0, // DstI[vdst]
        GIR_AddImm8, /*InsnID*/0, /*Imm*/0,
        GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/2, // src
        GIR_AddImm8, /*InsnID*/0, /*Imm*/0,
        GIR_AddImm8, /*InsnID*/0, /*Imm*/0,
        GIR_AddImm8, /*InsnID*/0, /*Imm*/1,
        GIR_ConstrainSelectedInstOperands, /*InsnID*/0,
        GIR_EraseFromParent, /*InsnID*/0,
        // GIR_Coverage, 2058,
        GIR_Done,
      // Label 3109: @199329
      GIM_Try, /*On fail goto*//*Label 3110*/ GIMT_Encode4(199395), // Rule ID 2059 //
        GIM_CheckFeatures, GIMT_Encode2(GIFBS_isGFX9Only),
        GIM_CheckIntrinsicID, /*MI*/0, /*Op*/1, GIMT_Encode2(Intrinsic::amdgcn_cvt_f32_bf8),
        GIM_CheckType, /*MI*/0, /*Op*/0, /*Type*/GILLT_s32,
        GIM_CheckType, /*MI*/0, /*Op*/2, /*Type*/GILLT_s32,
        GIM_CheckRegBankForClass, /*MI*/0, /*Op*/0, /*RC*/GIMT_Encode2(AMDGPU::VGPR_32RegClassID),
        // MIs[0] Operand 3
        GIM_CheckLiteralInt, /*MI*/0, /*Op*/3, GIMT_Encode8(1),
        // (intrinsic_wo_chain:{ *:[f32] } 1908:{ *:[iPTR] }, i32:{ *:[i32] }:$src, 1:{ *:[i32] })  =>  (V_CVT_F32_BF8_sdwa:{ *:[f32] } 0:{ *:[i32] }, ?:{ *:[i32] }:$src, 0:{ *:[i1] }, 0:{ *:[i32] }, 1:{ *:[i32] })
        GIR_BuildMI, /*InsnID*/0, /*Opcode*/GIMT_Encode2(AMDGPU::V_CVT_F32_BF8_sdwa),
        GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/0, // DstI[vdst]
        GIR_AddImm8, /*InsnID*/0, /*Imm*/0,
        GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/2, // src
        GIR_AddImm8, /*InsnID*/0, /*Imm*/0,
        GIR_AddImm8, /*InsnID*/0, /*Imm*/0,
        GIR_AddImm8, /*InsnID*/0, /*Imm*/1,
        GIR_ConstrainSelectedInstOperands, /*InsnID*/0,
        GIR_EraseFromParent, /*InsnID*/0,
        // GIR_Coverage, 2059,
        GIR_Done,
      // Label 3110: @199395
      GIM_Try, /*On fail goto*//*Label 3111*/ GIMT_Encode4(199461), // Rule ID 2060 //
        GIM_CheckFeatures, GIMT_Encode2(GIFBS_isGFX9Only),
        GIM_CheckIntrinsicID, /*MI*/0, /*Op*/1, GIMT_Encode2(Intrinsic::amdgcn_cvt_f32_fp8),
        GIM_CheckType, /*MI*/0, /*Op*/0, /*Type*/GILLT_s32,
        GIM_CheckType, /*MI*/0, /*Op*/2, /*Type*/GILLT_s32,
        GIM_CheckRegBankForClass, /*MI*/0, /*Op*/0, /*RC*/GIMT_Encode2(AMDGPU::VGPR_32RegClassID),
        // MIs[0] Operand 3
        GIM_CheckLiteralInt, /*MI*/0, /*Op*/3, GIMT_Encode8(2),
        // (intrinsic_wo_chain:{ *:[f32] } 1909:{ *:[iPTR] }, i32:{ *:[i32] }:$src, 2:{ *:[i32] })  =>  (V_CVT_F32_FP8_sdwa:{ *:[f32] } 0:{ *:[i32] }, ?:{ *:[i32] }:$src, 0:{ *:[i1] }, 0:{ *:[i32] }, 2:{ *:[i32] })
        GIR_BuildMI, /*InsnID*/0, /*Opcode*/GIMT_Encode2(AMDGPU::V_CVT_F32_FP8_sdwa),
        GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/0, // DstI[vdst]
        GIR_AddImm8, /*InsnID*/0, /*Imm*/0,
        GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/2, // src
        GIR_AddImm8, /*InsnID*/0, /*Imm*/0,
        GIR_AddImm8, /*InsnID*/0, /*Imm*/0,
        GIR_AddImm8, /*InsnID*/0, /*Imm*/2,
        GIR_ConstrainSelectedInstOperands, /*InsnID*/0,
        GIR_EraseFromParent, /*InsnID*/0,
        // GIR_Coverage, 2060,
        GIR_Done,
      // Label 3111: @199461
      GIM_Try, /*On fail goto*//*Label 3112*/ GIMT_Encode4(199527), // Rule ID 2061 //
        GIM_CheckFeatures, GIMT_Encode2(GIFBS_isGFX9Only),
        GIM_CheckIntrinsicID, /*MI*/0, /*Op*/1, GIMT_Encode2(Intrinsic::amdgcn_cvt_f32_bf8),
        GIM_CheckType, /*MI*/0, /*Op*/0, /*Type*/GILLT_s32,
        GIM_CheckType, /*MI*/0, /*Op*/2, /*Type*/GILLT_s32,
        GIM_CheckRegBankForClass, /*MI*/0, /*Op*/0, /*RC*/GIMT_Encode2(AMDGPU::VGPR_32RegClassID),
        // MIs[0] Operand 3
        GIM_CheckLiteralInt, /*MI*/0, /*Op*/3, GIMT_Encode8(2),
        // (intrinsic_wo_chain:{ *:[f32] } 1908:{ *:[iPTR] }, i32:{ *:[i32] }:$src, 2:{ *:[i32] })  =>  (V_CVT_F32_BF8_sdwa:{ *:[f32] } 0:{ *:[i32] }, ?:{ *:[i32] }:$src, 0:{ *:[i1] }, 0:{ *:[i32] }, 2:{ *:[i32] })
        GIR_BuildMI, /*InsnID*/0, /*Opcode*/GIMT_Encode2(AMDGPU::V_CVT_F32_BF8_sdwa),
        GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/0, // DstI[vdst]
        GIR_AddImm8, /*InsnID*/0, /*Imm*/0,
        GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/2, // src
        GIR_AddImm8, /*InsnID*/0, /*Imm*/0,
        GIR_AddImm8, /*InsnID*/0, /*Imm*/0,
        GIR_AddImm8, /*InsnID*/0, /*Imm*/2,
        GIR_ConstrainSelectedInstOperands, /*InsnID*/0,
        GIR_EraseFromParent, /*InsnID*/0,
        // GIR_Coverage, 2061,
        GIR_Done,
      // Label 3112: @199527
      GIM_Try, /*On fail goto*//*Label 3113*/ GIMT_Encode4(199593), // Rule ID 2062 //
        GIM_CheckFeatures, GIMT_Encode2(GIFBS_isGFX9Only),
        GIM_CheckIntrinsicID, /*MI*/0, /*Op*/1, GIMT_Encode2(Intrinsic::amdgcn_cvt_f32_fp8),
        GIM_CheckType, /*MI*/0, /*Op*/0, /*Type*/GILLT_s32,
        GIM_CheckType, /*MI*/0, /*Op*/2, /*Type*/GILLT_s32,
        GIM_CheckRegBankForClass, /*MI*/0, /*Op*/0, /*RC*/GIMT_Encode2(AMDGPU::VGPR_32RegClassID),
        // MIs[0] Operand 3
        GIM_CheckLiteralInt, /*MI*/0, /*Op*/3, GIMT_Encode8(3),
        // (intrinsic_wo_chain:{ *:[f32] } 1909:{ *:[iPTR] }, i32:{ *:[i32] }:$src, 3:{ *:[i32] })  =>  (V_CVT_F32_FP8_sdwa:{ *:[f32] } 0:{ *:[i32] }, ?:{ *:[i32] }:$src, 0:{ *:[i1] }, 0:{ *:[i32] }, 3:{ *:[i32] })
        GIR_BuildMI, /*InsnID*/0, /*Opcode*/GIMT_Encode2(AMDGPU::V_CVT_F32_FP8_sdwa),
        GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/0, // DstI[vdst]
        GIR_AddImm8, /*InsnID*/0, /*Imm*/0,
        GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/2, // src
        GIR_AddImm8, /*InsnID*/0, /*Imm*/0,
        GIR_AddImm8, /*InsnID*/0, /*Imm*/0,
        GIR_AddImm8, /*InsnID*/0, /*Imm*/3,
        GIR_ConstrainSelectedInstOperands, /*InsnID*/0,
        GIR_EraseFromParent, /*InsnID*/0,
        // GIR_Coverage, 2062,
        GIR_Done,
      // Label 3113: @199593
      GIM_Try, /*On fail goto*//*Label 3114*/ GIMT_Encode4(199659), // Rule ID 2063 //
        GIM_CheckFeatures, GIMT_Encode2(GIFBS_isGFX9Only),
        GIM_CheckIntrinsicID, /*MI*/0, /*Op*/1, GIMT_Encode2(Intrinsic::amdgcn_cvt_f32_bf8),
        GIM_CheckType, /*MI*/0, /*Op*/0, /*Type*/GILLT_s32,
        GIM_CheckType, /*MI*/0, /*Op*/2, /*Type*/GILLT_s32,
        GIM_CheckRegBankForClass, /*MI*/0, /*Op*/0, /*RC*/GIMT_Encode2(AMDGPU::VGPR_32RegClassID),
        // MIs[0] Operand 3
        GIM_CheckLiteralInt, /*MI*/0, /*Op*/3, GIMT_Encode8(3),
        // (intrinsic_wo_chain:{ *:[f32] } 1908:{ *:[iPTR] }, i32:{ *:[i32] }:$src, 3:{ *:[i32] })  =>  (V_CVT_F32_BF8_sdwa:{ *:[f32] } 0:{ *:[i32] }, ?:{ *:[i32] }:$src, 0:{ *:[i1] }, 0:{ *:[i32] }, 3:{ *:[i32] })
        GIR_BuildMI, /*InsnID*/0, /*Opcode*/GIMT_Encode2(AMDGPU::V_CVT_F32_BF8_sdwa),
        GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/0, // DstI[vdst]
        GIR_AddImm8, /*InsnID*/0, /*Imm*/0,
        GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/2, // src
        GIR_AddImm8, /*InsnID*/0, /*Imm*/0,
        GIR_AddImm8, /*InsnID*/0, /*Imm*/0,
        GIR_AddImm8, /*InsnID*/0, /*Imm*/3,
        GIR_ConstrainSelectedInstOperands, /*InsnID*/0,
        GIR_EraseFromParent, /*InsnID*/0,
        // GIR_Coverage, 2063,
        GIR_Done,
      // Label 3114: @199659
      GIM_Try, /*On fail goto*//*Label 3115*/ GIMT_Encode4(199713), // Rule ID 2064 //
        GIM_CheckFeatures, GIMT_Encode2(GIFBS_isGFX9Only),
        GIM_CheckIntrinsicID, /*MI*/0, /*Op*/1, GIMT_Encode2(Intrinsic::amdgcn_cvt_pk_f32_fp8),
        GIM_CheckType, /*MI*/0, /*Op*/0, /*Type*/GILLT_v2s32,
        GIM_CheckType, /*MI*/0, /*Op*/2, /*Type*/GILLT_s32,
        GIM_CheckRegBankForClass, /*MI*/0, /*Op*/0, /*RC*/GIMT_Encode2(AMDGPU::VReg_64RegClassID),
        // MIs[0] Operand 3
        GIM_CheckLiteralInt, /*MI*/0, /*Op*/3, GIMT_Encode8(0),
        // (intrinsic_wo_chain:{ *:[v2f32] } 1912:{ *:[iPTR] }, i32:{ *:[i32] }:$src, 0:{ *:[i1] })  =>  (V_CVT_PK_F32_FP8_e32:{ *:[v2f32] } ?:{ *:[i32] }:$src)
        GIR_BuildMI, /*InsnID*/0, /*Opcode*/GIMT_Encode2(AMDGPU::V_CVT_PK_F32_FP8_e32),
        GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/0, // DstI[vdst]
        GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/2, // src
        GIR_ConstrainSelectedInstOperands, /*InsnID*/0,
        GIR_EraseFromParent, /*InsnID*/0,
        // GIR_Coverage, 2064,
        GIR_Done,
      // Label 3115: @199713
      GIM_Try, /*On fail goto*//*Label 3116*/ GIMT_Encode4(199767), // Rule ID 2065 //
        GIM_CheckFeatures, GIMT_Encode2(GIFBS_isGFX9Only),
        GIM_CheckIntrinsicID, /*MI*/0, /*Op*/1, GIMT_Encode2(Intrinsic::amdgcn_cvt_pk_f32_bf8),
        GIM_CheckType, /*MI*/0, /*Op*/0, /*Type*/GILLT_v2s32,
        GIM_CheckType, /*MI*/0, /*Op*/2, /*Type*/GILLT_s32,
        GIM_CheckRegBankForClass, /*MI*/0, /*Op*/0, /*RC*/GIMT_Encode2(AMDGPU::VReg_64RegClassID),
        // MIs[0] Operand 3
        GIM_CheckLiteralInt, /*MI*/0, /*Op*/3, GIMT_Encode8(0),
        // (intrinsic_wo_chain:{ *:[v2f32] } 1911:{ *:[iPTR] }, i32:{ *:[i32] }:$src, 0:{ *:[i1] })  =>  (V_CVT_PK_F32_BF8_e32:{ *:[v2f32] } ?:{ *:[i32] }:$src)
        GIR_BuildMI, /*InsnID*/0, /*Opcode*/GIMT_Encode2(AMDGPU::V_CVT_PK_F32_BF8_e32),
        GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/0, // DstI[vdst]
        GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/2, // src
        GIR_ConstrainSelectedInstOperands, /*InsnID*/0,
        GIR_EraseFromParent, /*InsnID*/0,
        // GIR_Coverage, 2065,
        GIR_Done,
      // Label 3116: @199767
      GIM_Try, /*On fail goto*//*Label 3117*/ GIMT_Encode4(199833), // Rule ID 2066 //
        GIM_CheckFeatures, GIMT_Encode2(GIFBS_isGFX9Only),
        GIM_CheckIntrinsicID, /*MI*/0, /*Op*/1, GIMT_Encode2(Intrinsic::amdgcn_cvt_pk_f32_fp8),
        GIM_CheckType, /*MI*/0, /*Op*/0, /*Type*/GILLT_v2s32,
        GIM_CheckType, /*MI*/0, /*Op*/2, /*Type*/GILLT_s32,
        GIM_CheckRegBankForClass, /*MI*/0, /*Op*/0, /*RC*/GIMT_Encode2(AMDGPU::VReg_64RegClassID),
        // MIs[0] Operand 3
        GIM_CheckLiteralInt, /*MI*/0, /*Op*/3, GIMT_Encode8(-1),
        // (intrinsic_wo_chain:{ *:[v2f32] } 1912:{ *:[iPTR] }, i32:{ *:[i32] }:$src, -1:{ *:[i1] })  =>  (V_CVT_PK_F32_FP8_sdwa:{ *:[v2f32] } 0:{ *:[i32] }, ?:{ *:[i32] }:$src, 0:{ *:[i1] }, 0:{ *:[i32] }, 5:{ *:[i32] })
        GIR_BuildMI, /*InsnID*/0, /*Opcode*/GIMT_Encode2(AMDGPU::V_CVT_PK_F32_FP8_sdwa),
        GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/0, // DstI[vdst]
        GIR_AddImm8, /*InsnID*/0, /*Imm*/0,
        GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/2, // src
        GIR_AddImm8, /*InsnID*/0, /*Imm*/0,
        GIR_AddImm8, /*InsnID*/0, /*Imm*/0,
        GIR_AddImm8, /*InsnID*/0, /*Imm*/5,
        GIR_ConstrainSelectedInstOperands, /*InsnID*/0,
        GIR_EraseFromParent, /*InsnID*/0,
        // GIR_Coverage, 2066,
        GIR_Done,
      // Label 3117: @199833
      GIM_Try, /*On fail goto*//*Label 3118*/ GIMT_Encode4(199899), // Rule ID 2067 //
        GIM_CheckFeatures, GIMT_Encode2(GIFBS_isGFX9Only),
        GIM_CheckIntrinsicID, /*MI*/0, /*Op*/1, GIMT_Encode2(Intrinsic::amdgcn_cvt_pk_f32_bf8),
        GIM_CheckType, /*MI*/0, /*Op*/0, /*Type*/GILLT_v2s32,
        GIM_CheckType, /*MI*/0, /*Op*/2, /*Type*/GILLT_s32,
        GIM_CheckRegBankForClass, /*MI*/0, /*Op*/0, /*RC*/GIMT_Encode2(AMDGPU::VReg_64RegClassID),
        // MIs[0] Operand 3
        GIM_CheckLiteralInt, /*MI*/0, /*Op*/3, GIMT_Encode8(-1),
        // (intrinsic_wo_chain:{ *:[v2f32] } 1911:{ *:[iPTR] }, i32:{ *:[i32] }:$src, -1:{ *:[i1] })  =>  (V_CVT_PK_F32_BF8_sdwa:{ *:[v2f32] } 0:{ *:[i32] }, ?:{ *:[i32] }:$src, 0:{ *:[i1] }, 0:{ *:[i32] }, 5:{ *:[i32] })
        GIR_BuildMI, /*InsnID*/0, /*Opcode*/GIMT_Encode2(AMDGPU::V_CVT_PK_F32_BF8_sdwa),
        GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/0, // DstI[vdst]
        GIR_AddImm8, /*InsnID*/0, /*Imm*/0,
        GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/2, // src
        GIR_AddImm8, /*InsnID*/0, /*Imm*/0,
        GIR_AddImm8, /*InsnID*/0, /*Imm*/0,
        GIR_AddImm8, /*InsnID*/0, /*Imm*/5,
        GIR_ConstrainSelectedInstOperands, /*InsnID*/0,
        GIR_EraseFromParent, /*InsnID*/0,
        // GIR_Coverage, 2067,
        GIR_Done,
      // Label 3118: @199899
      GIM_Try, /*On fail goto*//*Label 3119*/ GIMT_Encode4(199953), // Rule ID 2068 //
        GIM_CheckFeatures, GIMT_Encode2(GIFBS_isGFX12Plus),
        GIM_CheckIntrinsicID, /*MI*/0, /*Op*/1, GIMT_Encode2(Intrinsic::amdgcn_cvt_f32_fp8),
        GIM_CheckType, /*MI*/0, /*Op*/0, /*Type*/GILLT_s32,
        GIM_CheckType, /*MI*/0, /*Op*/2, /*Type*/GILLT_s32,
        GIM_CheckRegBankForClass, /*MI*/0, /*Op*/0, /*RC*/GIMT_Encode2(AMDGPU::VGPR_32RegClassID),
        // MIs[0] Operand 3
        GIM_CheckLiteralInt, /*MI*/0, /*Op*/3, GIMT_Encode8(0),
        // (intrinsic_wo_chain:{ *:[f32] } 1909:{ *:[iPTR] }, i32:{ *:[i32] }:$src, 0:{ *:[i32] })  =>  (V_CVT_F32_FP8_e32:{ *:[f32] } ?:{ *:[i32] }:$src)
        GIR_BuildMI, /*InsnID*/0, /*Opcode*/GIMT_Encode2(AMDGPU::V_CVT_F32_FP8_e32),
        GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/0, // DstI[vdst]
        GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/2, // src
        GIR_ConstrainSelectedInstOperands, /*InsnID*/0,
        GIR_EraseFromParent, /*InsnID*/0,
        // GIR_Coverage, 2068,
        GIR_Done,
      // Label 3119: @199953
      GIM_Try, /*On fail goto*//*Label 3120*/ GIMT_Encode4(200007), // Rule ID 2069 //
        GIM_CheckFeatures, GIMT_Encode2(GIFBS_isGFX12Plus),
        GIM_CheckIntrinsicID, /*MI*/0, /*Op*/1, GIMT_Encode2(Intrinsic::amdgcn_cvt_f32_bf8),
        GIM_CheckType, /*MI*/0, /*Op*/0, /*Type*/GILLT_s32,
        GIM_CheckType, /*MI*/0, /*Op*/2, /*Type*/GILLT_s32,
        GIM_CheckRegBankForClass, /*MI*/0, /*Op*/0, /*RC*/GIMT_Encode2(AMDGPU::VGPR_32RegClassID),
        // MIs[0] Operand 3
        GIM_CheckLiteralInt, /*MI*/0, /*Op*/3, GIMT_Encode8(0),
        // (intrinsic_wo_chain:{ *:[f32] } 1908:{ *:[iPTR] }, i32:{ *:[i32] }:$src, 0:{ *:[i32] })  =>  (V_CVT_F32_BF8_e32:{ *:[f32] } ?:{ *:[i32] }:$src)
        GIR_BuildMI, /*InsnID*/0, /*Opcode*/GIMT_Encode2(AMDGPU::V_CVT_F32_BF8_e32),
        GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/0, // DstI[vdst]
        GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/2, // src
        GIR_ConstrainSelectedInstOperands, /*InsnID*/0,
        GIR_EraseFromParent, /*InsnID*/0,
        // GIR_Coverage, 2069,
        GIR_Done,
      // Label 3120: @200007
      GIM_Try, /*On fail goto*//*Label 3121*/ GIMT_Encode4(200067), // Rule ID 2070 //
        GIM_CheckFeatures, GIMT_Encode2(GIFBS_isGFX12Plus),
        GIM_CheckIntrinsicID, /*MI*/0, /*Op*/1, GIMT_Encode2(Intrinsic::amdgcn_cvt_f32_fp8),
        GIM_CheckType, /*MI*/0, /*Op*/0, /*Type*/GILLT_s32,
        GIM_CheckType, /*MI*/0, /*Op*/2, /*Type*/GILLT_s32,
        GIM_CheckRegBankForClass, /*MI*/0, /*Op*/0, /*RC*/GIMT_Encode2(AMDGPU::VGPR_32RegClassID),
        // MIs[0] Operand 3
        GIM_CheckLiteralInt, /*MI*/0, /*Op*/3, GIMT_Encode8(1),
        // (intrinsic_wo_chain:{ *:[f32] } 1909:{ *:[iPTR] }, i32:{ *:[i32] }:$src, 1:{ *:[i32] })  =>  (V_CVT_F32_FP8_OP_SEL_e64:{ *:[f32] } 4:{ *:[i32] }, ?:{ *:[i32] }:$src, 0:{ *:[i32] })
        GIR_BuildMI, /*InsnID*/0, /*Opcode*/GIMT_Encode2(AMDGPU::V_CVT_F32_FP8_OP_SEL_e64),
        GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/0, // DstI[vdst]
        GIR_AddImm8, /*InsnID*/0, /*Imm*/4,
        GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/2, // src
        GIR_AddImm8, /*InsnID*/0, /*Imm*/0,
        GIR_ConstrainSelectedInstOperands, /*InsnID*/0,
        GIR_EraseFromParent, /*InsnID*/0,
        // GIR_Coverage, 2070,
        GIR_Done,
      // Label 3121: @200067
      GIM_Try, /*On fail goto*//*Label 3122*/ GIMT_Encode4(200127), // Rule ID 2071 //
        GIM_CheckFeatures, GIMT_Encode2(GIFBS_isGFX12Plus),
        GIM_CheckIntrinsicID, /*MI*/0, /*Op*/1, GIMT_Encode2(Intrinsic::amdgcn_cvt_f32_bf8),
        GIM_CheckType, /*MI*/0, /*Op*/0, /*Type*/GILLT_s32,
        GIM_CheckType, /*MI*/0, /*Op*/2, /*Type*/GILLT_s32,
        GIM_CheckRegBankForClass, /*MI*/0, /*Op*/0, /*RC*/GIMT_Encode2(AMDGPU::VGPR_32RegClassID),
        // MIs[0] Operand 3
        GIM_CheckLiteralInt, /*MI*/0, /*Op*/3, GIMT_Encode8(1),
        // (intrinsic_wo_chain:{ *:[f32] } 1908:{ *:[iPTR] }, i32:{ *:[i32] }:$src, 1:{ *:[i32] })  =>  (V_CVT_F32_BF8_OP_SEL_e64:{ *:[f32] } 4:{ *:[i32] }, ?:{ *:[i32] }:$src, 0:{ *:[i32] })
        GIR_BuildMI, /*InsnID*/0, /*Opcode*/GIMT_Encode2(AMDGPU::V_CVT_F32_BF8_OP_SEL_e64),
        GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/0, // DstI[vdst]
        GIR_AddImm8, /*InsnID*/0, /*Imm*/4,
        GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/2, // src
        GIR_AddImm8, /*InsnID*/0, /*Imm*/0,
        GIR_ConstrainSelectedInstOperands, /*InsnID*/0,
        GIR_EraseFromParent, /*InsnID*/0,
        // GIR_Coverage, 2071,
        GIR_Done,
      // Label 3122: @200127
      GIM_Try, /*On fail goto*//*Label 3123*/ GIMT_Encode4(200187), // Rule ID 2072 //
        GIM_CheckFeatures, GIMT_Encode2(GIFBS_isGFX12Plus),
        GIM_CheckIntrinsicID, /*MI*/0, /*Op*/1, GIMT_Encode2(Intrinsic::amdgcn_cvt_f32_fp8),
        GIM_CheckType, /*MI*/0, /*Op*/0, /*Type*/GILLT_s32,
        GIM_CheckType, /*MI*/0, /*Op*/2, /*Type*/GILLT_s32,
        GIM_CheckRegBankForClass, /*MI*/0, /*Op*/0, /*RC*/GIMT_Encode2(AMDGPU::VGPR_32RegClassID),
        // MIs[0] Operand 3
        GIM_CheckLiteralInt, /*MI*/0, /*Op*/3, GIMT_Encode8(2),
        // (intrinsic_wo_chain:{ *:[f32] } 1909:{ *:[iPTR] }, i32:{ *:[i32] }:$src, 2:{ *:[i32] })  =>  (V_CVT_F32_FP8_OP_SEL_e64:{ *:[f32] } 8:{ *:[i32] }, ?:{ *:[i32] }:$src, 0:{ *:[i32] })
        GIR_BuildMI, /*InsnID*/0, /*Opcode*/GIMT_Encode2(AMDGPU::V_CVT_F32_FP8_OP_SEL_e64),
        GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/0, // DstI[vdst]
        GIR_AddImm8, /*InsnID*/0, /*Imm*/8,
        GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/2, // src
        GIR_AddImm8, /*InsnID*/0, /*Imm*/0,
        GIR_ConstrainSelectedInstOperands, /*InsnID*/0,
        GIR_EraseFromParent, /*InsnID*/0,
        // GIR_Coverage, 2072,
        GIR_Done,
      // Label 3123: @200187
      GIM_Try, /*On fail goto*//*Label 3124*/ GIMT_Encode4(200247), // Rule ID 2073 //
        GIM_CheckFeatures, GIMT_Encode2(GIFBS_isGFX12Plus),
        GIM_CheckIntrinsicID, /*MI*/0, /*Op*/1, GIMT_Encode2(Intrinsic::amdgcn_cvt_f32_bf8),
        GIM_CheckType, /*MI*/0, /*Op*/0, /*Type*/GILLT_s32,
        GIM_CheckType, /*MI*/0, /*Op*/2, /*Type*/GILLT_s32,
        GIM_CheckRegBankForClass, /*MI*/0, /*Op*/0, /*RC*/GIMT_Encode2(AMDGPU::VGPR_32RegClassID),
        // MIs[0] Operand 3
        GIM_CheckLiteralInt, /*MI*/0, /*Op*/3, GIMT_Encode8(2),
        // (intrinsic_wo_chain:{ *:[f32] } 1908:{ *:[iPTR] }, i32:{ *:[i32] }:$src, 2:{ *:[i32] })  =>  (V_CVT_F32_BF8_OP_SEL_e64:{ *:[f32] } 8:{ *:[i32] }, ?:{ *:[i32] }:$src, 0:{ *:[i32] })
        GIR_BuildMI, /*InsnID*/0, /*Opcode*/GIMT_Encode2(AMDGPU::V_CVT_F32_BF8_OP_SEL_e64),
        GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/0, // DstI[vdst]
        GIR_AddImm8, /*InsnID*/0, /*Imm*/8,
        GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/2, // src
        GIR_AddImm8, /*InsnID*/0, /*Imm*/0,
        GIR_ConstrainSelectedInstOperands, /*InsnID*/0,
        GIR_EraseFromParent, /*InsnID*/0,
        // GIR_Coverage, 2073,
        GIR_Done,
      // Label 3124: @200247
      GIM_Try, /*On fail goto*//*Label 3125*/ GIMT_Encode4(200307), // Rule ID 2074 //
        GIM_CheckFeatures, GIMT_Encode2(GIFBS_isGFX12Plus),
        GIM_CheckIntrinsicID, /*MI*/0, /*Op*/1, GIMT_Encode2(Intrinsic::amdgcn_cvt_f32_fp8),
        GIM_CheckType, /*MI*/0, /*Op*/0, /*Type*/GILLT_s32,
        GIM_CheckType, /*MI*/0, /*Op*/2, /*Type*/GILLT_s32,
        GIM_CheckRegBankForClass, /*MI*/0, /*Op*/0, /*RC*/GIMT_Encode2(AMDGPU::VGPR_32RegClassID),
        // MIs[0] Operand 3
        GIM_CheckLiteralInt, /*MI*/0, /*Op*/3, GIMT_Encode8(3),
        // (intrinsic_wo_chain:{ *:[f32] } 1909:{ *:[iPTR] }, i32:{ *:[i32] }:$src, 3:{ *:[i32] })  =>  (V_CVT_F32_FP8_OP_SEL_e64:{ *:[f32] } 12:{ *:[i32] }, ?:{ *:[i32] }:$src, 0:{ *:[i32] })
        GIR_BuildMI, /*InsnID*/0, /*Opcode*/GIMT_Encode2(AMDGPU::V_CVT_F32_FP8_OP_SEL_e64),
        GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/0, // DstI[vdst]
        GIR_AddImm8, /*InsnID*/0, /*Imm*/12,
        GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/2, // src
        GIR_AddImm8, /*InsnID*/0, /*Imm*/0,
        GIR_ConstrainSelectedInstOperands, /*InsnID*/0,
        GIR_EraseFromParent, /*InsnID*/0,
        // GIR_Coverage, 2074,
        GIR_Done,
      // Label 3125: @200307
      GIM_Try, /*On fail goto*//*Label 3126*/ GIMT_Encode4(200367), // Rule ID 2075 //
        GIM_CheckFeatures, GIMT_Encode2(GIFBS_isGFX12Plus),
        GIM_CheckIntrinsicID, /*MI*/0, /*Op*/1, GIMT_Encode2(Intrinsic::amdgcn_cvt_f32_bf8),
        GIM_CheckType, /*MI*/0, /*Op*/0, /*Type*/GILLT_s32,
        GIM_CheckType, /*MI*/0, /*Op*/2, /*Type*/GILLT_s32,
        GIM_CheckRegBankForClass, /*MI*/0, /*Op*/0, /*RC*/GIMT_Encode2(AMDGPU::VGPR_32RegClassID),
        // MIs[0] Operand 3
        GIM_CheckLiteralInt, /*MI*/0, /*Op*/3, GIMT_Encode8(3),
        // (intrinsic_wo_chain:{ *:[f32] } 1908:{ *:[iPTR] }, i32:{ *:[i32] }:$src, 3:{ *:[i32] })  =>  (V_CVT_F32_BF8_OP_SEL_e64:{ *:[f32] } 12:{ *:[i32] }, ?:{ *:[i32] }:$src, 0:{ *:[i32] })
        GIR_BuildMI, /*InsnID*/0, /*Opcode*/GIMT_Encode2(AMDGPU::V_CVT_F32_BF8_OP_SEL_e64),
        GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/0, // DstI[vdst]
        GIR_AddImm8, /*InsnID*/0, /*Imm*/12,
        GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/2, // src
        GIR_AddImm8, /*InsnID*/0, /*Imm*/0,
        GIR_ConstrainSelectedInstOperands, /*InsnID*/0,
        GIR_EraseFromParent, /*InsnID*/0,
        // GIR_Coverage, 2075,
        GIR_Done,
      // Label 3126: @200367
      GIM_Try, /*On fail goto*//*Label 3127*/ GIMT_Encode4(200421), // Rule ID 2076 //
        GIM_CheckFeatures, GIMT_Encode2(GIFBS_isGFX12Plus),
        GIM_CheckIntrinsicID, /*MI*/0, /*Op*/1, GIMT_Encode2(Intrinsic::amdgcn_cvt_pk_f32_fp8),
        GIM_CheckType, /*MI*/0, /*Op*/0, /*Type*/GILLT_v2s32,
        GIM_CheckType, /*MI*/0, /*Op*/2, /*Type*/GILLT_s32,
        GIM_CheckRegBankForClass, /*MI*/0, /*Op*/0, /*RC*/GIMT_Encode2(AMDGPU::VReg_64RegClassID),
        // MIs[0] Operand 3
        GIM_CheckLiteralInt, /*MI*/0, /*Op*/3, GIMT_Encode8(0),
        // (intrinsic_wo_chain:{ *:[v2f32] } 1912:{ *:[iPTR] }, i32:{ *:[i32] }:$src, 0:{ *:[i1] })  =>  (V_CVT_PK_F32_FP8_e32:{ *:[v2f32] } ?:{ *:[i32] }:$src)
        GIR_BuildMI, /*InsnID*/0, /*Opcode*/GIMT_Encode2(AMDGPU::V_CVT_PK_F32_FP8_e32),
        GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/0, // DstI[vdst]
        GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/2, // src
        GIR_ConstrainSelectedInstOperands, /*InsnID*/0,
        GIR_EraseFromParent, /*InsnID*/0,
        // GIR_Coverage, 2076,
        GIR_Done,
      // Label 3127: @200421
      GIM_Try, /*On fail goto*//*Label 3128*/ GIMT_Encode4(200475), // Rule ID 2077 //
        GIM_CheckFeatures, GIMT_Encode2(GIFBS_isGFX12Plus),
        GIM_CheckIntrinsicID, /*MI*/0, /*Op*/1, GIMT_Encode2(Intrinsic::amdgcn_cvt_pk_f32_bf8),
        GIM_CheckType, /*MI*/0, /*Op*/0, /*Type*/GILLT_v2s32,
        GIM_CheckType, /*MI*/0, /*Op*/2, /*Type*/GILLT_s32,
        GIM_CheckRegBankForClass, /*MI*/0, /*Op*/0, /*RC*/GIMT_Encode2(AMDGPU::VReg_64RegClassID),
        // MIs[0] Operand 3
        GIM_CheckLiteralInt, /*MI*/0, /*Op*/3, GIMT_Encode8(0),
        // (intrinsic_wo_chain:{ *:[v2f32] } 1911:{ *:[iPTR] }, i32:{ *:[i32] }:$src, 0:{ *:[i1] })  =>  (V_CVT_PK_F32_BF8_e32:{ *:[v2f32] } ?:{ *:[i32] }:$src)
        GIR_BuildMI, /*InsnID*/0, /*Opcode*/GIMT_Encode2(AMDGPU::V_CVT_PK_F32_BF8_e32),
        GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/0, // DstI[vdst]
        GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/2, // src
        GIR_ConstrainSelectedInstOperands, /*InsnID*/0,
        GIR_EraseFromParent, /*InsnID*/0,
        // GIR_Coverage, 2077,
        GIR_Done,
      // Label 3128: @200475
      GIM_Try, /*On fail goto*//*Label 3129*/ GIMT_Encode4(200541), // Rule ID 2078 //
        GIM_CheckFeatures, GIMT_Encode2(GIFBS_isGFX12Plus),
        GIM_CheckIntrinsicID, /*MI*/0, /*Op*/1, GIMT_Encode2(Intrinsic::amdgcn_cvt_pk_f32_fp8),
        GIM_CheckType, /*MI*/0, /*Op*/0, /*Type*/GILLT_v2s32,
        GIM_CheckType, /*MI*/0, /*Op*/2, /*Type*/GILLT_s32,
        GIM_CheckRegBankForClass, /*MI*/0, /*Op*/0, /*RC*/GIMT_Encode2(AMDGPU::VReg_64RegClassID),
        // MIs[0] Operand 3
        GIM_CheckLiteralInt, /*MI*/0, /*Op*/3, GIMT_Encode8(-1),
        // (intrinsic_wo_chain:{ *:[v2f32] } 1912:{ *:[iPTR] }, i32:{ *:[i32] }:$src, -1:{ *:[i1] })  =>  (V_CVT_PK_F32_FP8_OP_SEL_e64:{ *:[v2f32] } 4:{ *:[i32] }, ?:{ *:[i32] }:$src, 0:{ *:[i1] }, 0:{ *:[i32] }, 0:{ *:[i32] })
        GIR_BuildMI, /*InsnID*/0, /*Opcode*/GIMT_Encode2(AMDGPU::V_CVT_PK_F32_FP8_OP_SEL_e64),
        GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/0, // DstI[vdst]
        GIR_AddImm8, /*InsnID*/0, /*Imm*/4,
        GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/2, // src
        GIR_AddImm8, /*InsnID*/0, /*Imm*/0,
        GIR_AddImm8, /*InsnID*/0, /*Imm*/0,
        GIR_AddImm8, /*InsnID*/0, /*Imm*/0,
        GIR_ConstrainSelectedInstOperands, /*InsnID*/0,
        GIR_EraseFromParent, /*InsnID*/0,
        // GIR_Coverage, 2078,
        GIR_Done,
      // Label 3129: @200541
      GIM_Try, /*On fail goto*//*Label 3130*/ GIMT_Encode4(200607), // Rule ID 2079 //
        GIM_CheckFeatures, GIMT_Encode2(GIFBS_isGFX12Plus),
        GIM_CheckIntrinsicID, /*MI*/0, /*Op*/1, GIMT_Encode2(Intrinsic::amdgcn_cvt_pk_f32_bf8),
        GIM_CheckType, /*MI*/0, /*Op*/0, /*Type*/GILLT_v2s32,
        GIM_CheckType, /*MI*/0, /*Op*/2, /*Type*/GILLT_s32,
        GIM_CheckRegBankForClass, /*MI*/0, /*Op*/0, /*RC*/GIMT_Encode2(AMDGPU::VReg_64RegClassID),
        // MIs[0] Operand 3
        GIM_CheckLiteralInt, /*MI*/0, /*Op*/3, GIMT_Encode8(-1),
        // (intrinsic_wo_chain:{ *:[v2f32] } 1911:{ *:[iPTR] }, i32:{ *:[i32] }:$src, -1:{ *:[i1] })  =>  (V_CVT_PK_F32_BF8_OP_SEL_e64:{ *:[v2f32] } 4:{ *:[i32] }, ?:{ *:[i32] }:$src, 0:{ *:[i1] }, 0:{ *:[i32] }, 0:{ *:[i32] })
        GIR_BuildMI, /*InsnID*/0, /*Opcode*/GIMT_Encode2(AMDGPU::V_CVT_PK_F32_BF8_OP_SEL_e64),
        GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/0, // DstI[vdst]
        GIR_AddImm8, /*InsnID*/0, /*Imm*/4,
        GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/2, // src
        GIR_AddImm8, /*InsnID*/0, /*Imm*/0,
        GIR_AddImm8, /*InsnID*/0, /*Imm*/0,
        GIR_AddImm8, /*InsnID*/0, /*Imm*/0,
        GIR_ConstrainSelectedInstOperands, /*InsnID*/0,
        GIR_EraseFromParent, /*InsnID*/0,
        // GIR_Coverage, 2079,
        GIR_Done,
      // Label 3130: @200607
      GIM_Try, /*On fail goto*//*Label 3131*/ GIMT_Encode4(200672), // Rule ID 110 //
        GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasSALUFloatInsts),
        GIM_CheckIntrinsicID, /*MI*/0, /*Op*/1, GIMT_Encode2(Intrinsic::amdgcn_cvt_pkrtz),
        GIM_CheckType, /*MI*/0, /*Op*/0, /*Type*/GILLT_v2s16,
        GIM_CheckType, /*MI*/0, /*Op*/2, /*Type*/GILLT_s32,
        GIM_CheckType, /*MI*/0, /*Op*/3, /*Type*/GILLT_s32,
        GIM_CheckRegBankForClass, /*MI*/0, /*Op*/0, /*RC*/GIMT_Encode2(AMDGPU::SReg_32RegClassID),
        GIM_CheckRegBankForClass, /*MI*/0, /*Op*/2, /*RC*/GIMT_Encode2(AMDGPU::SReg_32RegClassID),
        GIM_CheckRegBankForClass, /*MI*/0, /*Op*/3, /*RC*/GIMT_Encode2(AMDGPU::SReg_32RegClassID),
        GIM_CheckCxxInsnPredicate, /*MI*/0, /*FnId*/GIMT_Encode2(GICXXPred_MI_Predicate_anonymous_17635),
        // (intrinsic_wo_chain:{ *:[v2f16] } 1919:{ *:[iPTR] }, SSrc_f32:{ *:[f32] }:$src0, SSrc_f32:{ *:[f32] }:$src1)<<P:Predicate_anonymous_17635>>  =>  (S_CVT_PK_RTZ_F16_F32:{ *:[v2f16] } SSrc_f32:{ *:[f32] }:$src0, SSrc_f32:{ *:[f32] }:$src1)
        GIR_BuildMI, /*InsnID*/0, /*Opcode*/GIMT_Encode2(AMDGPU::S_CVT_PK_RTZ_F16_F32),
        GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/0, // DstI[sdst]
        GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/2, // src0
        GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/3, // src1
        GIR_ConstrainSelectedInstOperands, /*InsnID*/0,
        GIR_EraseFromParent, /*InsnID*/0,
        // GIR_Coverage, 110,
        GIR_Done,
      // Label 3131: @200672
      GIM_Try, /*On fail goto*//*Label 3132*/ GIMT_Encode4(200784), // Rule ID 2107 //
        GIM_CheckIntrinsicID, /*MI*/0, /*Op*/1, GIMT_Encode2(Intrinsic::amdgcn_mul_i24),
        GIM_CheckType, /*MI*/0, /*Op*/0, /*Type*/GILLT_s64,
        GIM_CheckType, /*MI*/0, /*Op*/2, /*Type*/GILLT_s32,
        GIM_CheckType, /*MI*/0, /*Op*/3, /*Type*/GILLT_s32,
        GIM_CheckRegBankForClass, /*MI*/0, /*Op*/0, /*RC*/GIMT_Encode2(AMDGPU::VReg_64RegClassID),
        // (intrinsic_wo_chain:{ *:[i64] } 2584:{ *:[iPTR] }, i32:{ *:[i32] }:$src0, i32:{ *:[i32] }:$src1)  =>  (REG_SEQUENCE:{ *:[i64] } VReg_64:{ *:[i32] }, (V_MUL_I32_I24_e64:{ *:[i16] } ?:{ *:[i32] }:$src0, ?:{ *:[i32] }:$src1), sub0:{ *:[i32] }, (V_MUL_HI_I32_I24_e64:{ *:[i16] } ?:{ *:[i32] }:$src0, ?:{ *:[i32] }:$src1), sub1:{ *:[i32] })
        GIR_MakeTempReg, /*TempRegID*/0, /*TypeID*/GILLT_s16,
        GIR_MakeTempReg, /*TempRegID*/1, /*TypeID*/GILLT_s16,
        GIR_BuildMI, /*InsnID*/2, /*Opcode*/GIMT_Encode2(AMDGPU::V_MUL_HI_I32_I24_e64),
        GIR_AddTempRegister, /*InsnID*/2, /*TempRegID*/1, /*TempRegFlags*/GIMT_Encode2(RegState::Define),
        GIR_Copy, /*NewInsnID*/2, /*OldInsnID*/0, /*OpIdx*/2, // src0
        GIR_Copy, /*NewInsnID*/2, /*OldInsnID*/0, /*OpIdx*/3, // src1
        GIR_ConstrainSelectedInstOperands, /*InsnID*/2,
        GIR_BuildMI, /*InsnID*/1, /*Opcode*/GIMT_Encode2(AMDGPU::V_MUL_I32_I24_e64),
        GIR_AddTempRegister, /*InsnID*/1, /*TempRegID*/0, /*TempRegFlags*/GIMT_Encode2(RegState::Define),
        GIR_Copy, /*NewInsnID*/1, /*OldInsnID*/0, /*OpIdx*/2, // src0
        GIR_Copy, /*NewInsnID*/1, /*OldInsnID*/0, /*OpIdx*/3, // src1
        GIR_AddImm8, /*InsnID*/1, /*Imm*/0,
        GIR_ConstrainSelectedInstOperands, /*InsnID*/1,
        GIR_BuildMI, /*InsnID*/0, /*Opcode*/GIMT_Encode2(TargetOpcode::REG_SEQUENCE),
        GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/0, // DstI[dst]
        GIR_AddSimpleTempRegister, /*InsnID*/0, /*TempRegID*/0,
        GIR_AddImm8, /*InsnID*/0, /*SubRegIndex*/3,
        GIR_AddSimpleTempRegister, /*InsnID*/0, /*TempRegID*/1,
        GIR_AddImm8, /*InsnID*/0, /*SubRegIndex*/11,
        GIR_ConstrainOperandRC, /*InsnID*/0, /*Op*/0, GIMT_Encode2(AMDGPU::VReg_64RegClassID),
        GIR_ConstrainOperandRC, /*InsnID*/0, /*Op*/1, GIMT_Encode2(AMDGPU::VGPR_32RegClassID),
        GIR_ConstrainOperandRC, /*InsnID*/0, /*Op*/3, GIMT_Encode2(AMDGPU::VGPR_32RegClassID),
        GIR_EraseFromParent, /*InsnID*/0,
        // GIR_Coverage, 2107,
        GIR_Done,
      // Label 3132: @200784
      GIM_Try, /*On fail goto*//*Label 3133*/ GIMT_Encode4(200896), // Rule ID 2109 //
        GIM_CheckIntrinsicID, /*MI*/0, /*Op*/1, GIMT_Encode2(Intrinsic::amdgcn_mul_u24),
        GIM_CheckType, /*MI*/0, /*Op*/0, /*Type*/GILLT_s64,
        GIM_CheckType, /*MI*/0, /*Op*/2, /*Type*/GILLT_s32,
        GIM_CheckType, /*MI*/0, /*Op*/3, /*Type*/GILLT_s32,
        GIM_CheckRegBankForClass, /*MI*/0, /*Op*/0, /*RC*/GIMT_Encode2(AMDGPU::VReg_64RegClassID),
        // (intrinsic_wo_chain:{ *:[i64] } 2585:{ *:[iPTR] }, i32:{ *:[i32] }:$src0, i32:{ *:[i32] }:$src1)  =>  (REG_SEQUENCE:{ *:[i64] } VReg_64:{ *:[i32] }, (V_MUL_U32_U24_e64:{ *:[i16] } ?:{ *:[i32] }:$src0, ?:{ *:[i32] }:$src1), sub0:{ *:[i32] }, (V_MUL_HI_U32_U24_e64:{ *:[i16] } ?:{ *:[i32] }:$src0, ?:{ *:[i32] }:$src1), sub1:{ *:[i32] })
        GIR_MakeTempReg, /*TempRegID*/0, /*TypeID*/GILLT_s16,
        GIR_MakeTempReg, /*TempRegID*/1, /*TypeID*/GILLT_s16,
        GIR_BuildMI, /*InsnID*/2, /*Opcode*/GIMT_Encode2(AMDGPU::V_MUL_HI_U32_U24_e64),
        GIR_AddTempRegister, /*InsnID*/2, /*TempRegID*/1, /*TempRegFlags*/GIMT_Encode2(RegState::Define),
        GIR_Copy, /*NewInsnID*/2, /*OldInsnID*/0, /*OpIdx*/2, // src0
        GIR_Copy, /*NewInsnID*/2, /*OldInsnID*/0, /*OpIdx*/3, // src1
        GIR_ConstrainSelectedInstOperands, /*InsnID*/2,
        GIR_BuildMI, /*InsnID*/1, /*Opcode*/GIMT_Encode2(AMDGPU::V_MUL_U32_U24_e64),
        GIR_AddTempRegister, /*InsnID*/1, /*TempRegID*/0, /*TempRegFlags*/GIMT_Encode2(RegState::Define),
        GIR_Copy, /*NewInsnID*/1, /*OldInsnID*/0, /*OpIdx*/2, // src0
        GIR_Copy, /*NewInsnID*/1, /*OldInsnID*/0, /*OpIdx*/3, // src1
        GIR_AddImm8, /*InsnID*/1, /*Imm*/0,
        GIR_ConstrainSelectedInstOperands, /*InsnID*/1,
        GIR_BuildMI, /*InsnID*/0, /*Opcode*/GIMT_Encode2(TargetOpcode::REG_SEQUENCE),
        GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/0, // DstI[dst]
        GIR_AddSimpleTempRegister, /*InsnID*/0, /*TempRegID*/0,
        GIR_AddImm8, /*InsnID*/0, /*SubRegIndex*/3,
        GIR_AddSimpleTempRegister, /*InsnID*/0, /*TempRegID*/1,
        GIR_AddImm8, /*InsnID*/0, /*SubRegIndex*/11,
        GIR_ConstrainOperandRC, /*InsnID*/0, /*Op*/0, GIMT_Encode2(AMDGPU::VReg_64RegClassID),
        GIR_ConstrainOperandRC, /*InsnID*/0, /*Op*/1, GIMT_Encode2(AMDGPU::VGPR_32RegClassID),
        GIR_ConstrainOperandRC, /*InsnID*/0, /*Op*/3, GIMT_Encode2(AMDGPU::VGPR_32RegClassID),
        GIR_EraseFromParent, /*InsnID*/0,
        // GIR_Coverage, 2109,
        GIR_Done,
      // Label 3133: @200896
      GIM_Try, /*On fail goto*//*Label 3134*/ GIMT_Encode4(200980), // Rule ID 727 //
        GIM_CheckIntrinsicID, /*MI*/0, /*Op*/1, GIMT_Encode2(Intrinsic::amdgcn_fmul_legacy),
        GIM_CheckType, /*MI*/0, /*Op*/0, /*Type*/GILLT_s32,
        GIM_CheckType, /*MI*/0, /*Op*/2, /*Type*/GILLT_s32,
        GIM_CheckType, /*MI*/0, /*Op*/3, /*Type*/GILLT_s32,
        GIM_CheckRegBankForClass, /*MI*/0, /*Op*/0, /*RC*/GIMT_Encode2(AMDGPU::VGPR_32RegClassID),
        GIM_CheckComplexPattern, /*MI*/0, /*Op*/2, /*Renderer*/GIMT_Encode2(0), GIMT_Encode2(GICP_gi_vop3mods0),
        GIM_CheckComplexPattern, /*MI*/0, /*Op*/3, /*Renderer*/GIMT_Encode2(1), GIMT_Encode2(GICP_gi_vop3mods),
        // (intrinsic_wo_chain:{ *:[f32] } 1973:{ *:[iPTR] }, (VOP3Mods0:{ *:[f32] } f32:{ *:[f32] }:$src0, i32:{ *:[i32] }:$src0_modifiers, i1:{ *:[i1] }:$clamp, i32:{ *:[i32] }:$omod), (VOP3Mods:{ *:[f32] } f32:{ *:[f32] }:$src1, i32:{ *:[i32] }:$src1_modifiers))  =>  (V_MUL_LEGACY_F32_e64:{ *:[f32] } i32:{ *:[i32] }:$src0_modifiers, f32:{ *:[f32] }:$src0, i32:{ *:[i32] }:$src1_modifiers, f32:{ *:[f32] }:$src1, i1:{ *:[i1] }:$clamp, i32:{ *:[i32] }:$omod)
        GIR_BuildMI, /*InsnID*/0, /*Opcode*/GIMT_Encode2(AMDGPU::V_MUL_LEGACY_F32_e64),
        GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/0, // DstI[vdst]
        GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/1, // src0_modifiers
        GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/0, // src0
        GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(1), /*SubOperand*/1, // src1_modifiers
        GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(1), /*SubOperand*/0, // src1
        GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/2, // clamp
        GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/3, // omod
        GIR_ConstrainSelectedInstOperands, /*InsnID*/0,
        GIR_EraseFromParent, /*InsnID*/0,
        // GIR_Coverage, 727,
        GIR_Done,
      // Label 3134: @200980
      GIM_Try, /*On fail goto*//*Label 3135*/ GIMT_Encode4(201059), // Rule ID 763 //
        GIM_CheckIntrinsicID, /*MI*/0, /*Op*/1, GIMT_Encode2(Intrinsic::amdgcn_cvt_pknorm_i16),
        GIM_CheckType, /*MI*/0, /*Op*/0, /*Type*/GILLT_v2s16,
        GIM_CheckType, /*MI*/0, /*Op*/2, /*Type*/GILLT_s32,
        GIM_CheckType, /*MI*/0, /*Op*/3, /*Type*/GILLT_s32,
        GIM_CheckRegBankForClass, /*MI*/0, /*Op*/0, /*RC*/GIMT_Encode2(AMDGPU::VGPR_32RegClassID),
        GIM_CheckComplexPattern, /*MI*/0, /*Op*/2, /*Renderer*/GIMT_Encode2(0), GIMT_Encode2(GICP_gi_vop3mods0),
        GIM_CheckComplexPattern, /*MI*/0, /*Op*/3, /*Renderer*/GIMT_Encode2(1), GIMT_Encode2(GICP_gi_vop3mods),
        // (intrinsic_wo_chain:{ *:[v2i16] } 1917:{ *:[iPTR] }, (VOP3Mods0:{ *:[f32] } f32:{ *:[f32] }:$src0, i32:{ *:[i32] }:$src0_modifiers, i1:{ *:[i1] }:$clamp), (VOP3Mods:{ *:[f32] } f32:{ *:[f32] }:$src1, i32:{ *:[i32] }:$src1_modifiers))  =>  (V_CVT_PKNORM_I16_F32_e64:{ *:[v2i16] } i32:{ *:[i32] }:$src0_modifiers, f32:{ *:[f32] }:$src0, i32:{ *:[i32] }:$src1_modifiers, f32:{ *:[f32] }:$src1, i1:{ *:[i1] }:$clamp)
        GIR_BuildMI, /*InsnID*/0, /*Opcode*/GIMT_Encode2(AMDGPU::V_CVT_PKNORM_I16_F32_e64),
        GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/0, // DstI[vdst]
        GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/1, // src0_modifiers
        GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/0, // src0
        GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(1), /*SubOperand*/1, // src1_modifiers
        GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(1), /*SubOperand*/0, // src1
        GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/2, // clamp
        GIR_ConstrainSelectedInstOperands, /*InsnID*/0,
        GIR_EraseFromParent, /*InsnID*/0,
        // GIR_Coverage, 763,
        GIR_Done,
      // Label 3135: @201059
      GIM_Try, /*On fail goto*//*Label 3136*/ GIMT_Encode4(201138), // Rule ID 765 //
        GIM_CheckIntrinsicID, /*MI*/0, /*Op*/1, GIMT_Encode2(Intrinsic::amdgcn_cvt_pknorm_u16),
        GIM_CheckType, /*MI*/0, /*Op*/0, /*Type*/GILLT_v2s16,
        GIM_CheckType, /*MI*/0, /*Op*/2, /*Type*/GILLT_s32,
        GIM_CheckType, /*MI*/0, /*Op*/3, /*Type*/GILLT_s32,
        GIM_CheckRegBankForClass, /*MI*/0, /*Op*/0, /*RC*/GIMT_Encode2(AMDGPU::VGPR_32RegClassID),
        GIM_CheckComplexPattern, /*MI*/0, /*Op*/2, /*Renderer*/GIMT_Encode2(0), GIMT_Encode2(GICP_gi_vop3mods0),
        GIM_CheckComplexPattern, /*MI*/0, /*Op*/3, /*Renderer*/GIMT_Encode2(1), GIMT_Encode2(GICP_gi_vop3mods),
        // (intrinsic_wo_chain:{ *:[v2i16] } 1918:{ *:[iPTR] }, (VOP3Mods0:{ *:[f32] } f32:{ *:[f32] }:$src0, i32:{ *:[i32] }:$src0_modifiers, i1:{ *:[i1] }:$clamp), (VOP3Mods:{ *:[f32] } f32:{ *:[f32] }:$src1, i32:{ *:[i32] }:$src1_modifiers))  =>  (V_CVT_PKNORM_U16_F32_e64:{ *:[v2i16] } i32:{ *:[i32] }:$src0_modifiers, f32:{ *:[f32] }:$src0, i32:{ *:[i32] }:$src1_modifiers, f32:{ *:[f32] }:$src1, i1:{ *:[i1] }:$clamp)
        GIR_BuildMI, /*InsnID*/0, /*Opcode*/GIMT_Encode2(AMDGPU::V_CVT_PKNORM_U16_F32_e64),
        GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/0, // DstI[vdst]
        GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/1, // src0_modifiers
        GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/0, // src0
        GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(1), /*SubOperand*/1, // src1_modifiers
        GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(1), /*SubOperand*/0, // src1
        GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/2, // clamp
        GIR_ConstrainSelectedInstOperands, /*InsnID*/0,
        GIR_EraseFromParent, /*InsnID*/0,
        // GIR_Coverage, 765,
        GIR_Done,
      // Label 3136: @201138
      GIM_Try, /*On fail goto*//*Label 3137*/ GIMT_Encode4(201222), // Rule ID 767 //
        GIM_CheckIntrinsicID, /*MI*/0, /*Op*/1, GIMT_Encode2(Intrinsic::amdgcn_cvt_pkrtz),
        GIM_CheckType, /*MI*/0, /*Op*/0, /*Type*/GILLT_v2s16,
        GIM_CheckType, /*MI*/0, /*Op*/2, /*Type*/GILLT_s32,
        GIM_CheckType, /*MI*/0, /*Op*/3, /*Type*/GILLT_s32,
        GIM_CheckRegBankForClass, /*MI*/0, /*Op*/0, /*RC*/GIMT_Encode2(AMDGPU::VGPR_32RegClassID),
        GIM_CheckComplexPattern, /*MI*/0, /*Op*/2, /*Renderer*/GIMT_Encode2(0), GIMT_Encode2(GICP_gi_vop3mods0),
        GIM_CheckComplexPattern, /*MI*/0, /*Op*/3, /*Renderer*/GIMT_Encode2(1), GIMT_Encode2(GICP_gi_vop3mods),
        // (intrinsic_wo_chain:{ *:[v2f16] } 1919:{ *:[iPTR] }, (VOP3Mods0:{ *:[f32] } f32:{ *:[f32] }:$src0, i32:{ *:[i32] }:$src0_modifiers, i1:{ *:[i1] }:$clamp, i32:{ *:[i32] }:$omod), (VOP3Mods:{ *:[f32] } f32:{ *:[f32] }:$src1, i32:{ *:[i32] }:$src1_modifiers))  =>  (V_CVT_PKRTZ_F16_F32_e64:{ *:[v2f16] } i32:{ *:[i32] }:$src0_modifiers, f32:{ *:[f32] }:$src0, i32:{ *:[i32] }:$src1_modifiers, f32:{ *:[f32] }:$src1, i1:{ *:[i1] }:$clamp, i32:{ *:[i32] }:$omod)
        GIR_BuildMI, /*InsnID*/0, /*Opcode*/GIMT_Encode2(AMDGPU::V_CVT_PKRTZ_F16_F32_e64),
        GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/0, // DstI[vdst]
        GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/1, // src0_modifiers
        GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/0, // src0
        GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(1), /*SubOperand*/1, // src1_modifiers
        GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(1), /*SubOperand*/0, // src1
        GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/2, // clamp
        GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/3, // omod
        GIR_ConstrainSelectedInstOperands, /*InsnID*/0,
        GIR_EraseFromParent, /*InsnID*/0,
        // GIR_Coverage, 767,
        GIR_Done,
      // Label 3137: @201222
      GIM_Try, /*On fail goto*//*Label 3138*/ GIMT_Encode4(201306), // Rule ID 904 //
        GIM_CheckIntrinsicID, /*MI*/0, /*Op*/1, GIMT_Encode2(Intrinsic::amdgcn_trig_preop),
        GIM_CheckType, /*MI*/0, /*Op*/0, /*Type*/GILLT_s64,
        GIM_CheckType, /*MI*/0, /*Op*/2, /*Type*/GILLT_s64,
        GIM_CheckType, /*MI*/0, /*Op*/3, /*Type*/GILLT_s32,
        GIM_CheckRegBankForClass, /*MI*/0, /*Op*/0, /*RC*/GIMT_Encode2(AMDGPU::VReg_64RegClassID),
        GIM_CheckComplexPattern, /*MI*/0, /*Op*/2, /*Renderer*/GIMT_Encode2(0), GIMT_Encode2(GICP_gi_vop3mods0),
        GIM_CheckComplexPattern, /*MI*/0, /*Op*/3, /*Renderer*/GIMT_Encode2(1), GIMT_Encode2(GICP_gi_vop3mods),
        // (intrinsic_wo_chain:{ *:[f64] } 2797:{ *:[iPTR] }, (VOP3Mods0:{ *:[f64] } f64:{ *:[f64] }:$src0, i32:{ *:[i32] }:$src0_modifiers, i1:{ *:[i1] }:$clamp, i32:{ *:[i32] }:$omod), (VOP3Mods:{ *:[i32] } i32:{ *:[i32] }:$src1, i32:{ *:[i32] }:$src1_modifiers))  =>  (V_TRIG_PREOP_F64_e64:{ *:[f64] } i32:{ *:[i32] }:$src0_modifiers, f64:{ *:[f64] }:$src0, i32:{ *:[i32] }:$src1_modifiers, i32:{ *:[i32] }:$src1, i1:{ *:[i1] }:$clamp, i32:{ *:[i32] }:$omod)
        GIR_BuildMI, /*InsnID*/0, /*Opcode*/GIMT_Encode2(AMDGPU::V_TRIG_PREOP_F64_e64),
        GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/0, // DstI[vdst]
        GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/1, // src0_modifiers
        GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/0, // src0
        GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(1), /*SubOperand*/1, // src1_modifiers
        GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(1), /*SubOperand*/0, // src1
        GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/2, // clamp
        GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/3, // omod
        GIR_ConstrainSelectedInstOperands, /*InsnID*/0,
        GIR_EraseFromParent, /*InsnID*/0,
        // GIR_Coverage, 904,
        GIR_Done,
      // Label 3138: @201306
      GIM_Try, /*On fail goto*//*Label 3139*/ GIMT_Encode4(201390), // Rule ID 7127 //
        GIM_CheckIntrinsicID, /*MI*/0, /*Op*/1, GIMT_Encode2(Intrinsic::amdgcn_fmul_legacy),
        GIM_CheckType, /*MI*/0, /*Op*/0, /*Type*/GILLT_s32,
        GIM_CheckType, /*MI*/0, /*Op*/2, /*Type*/GILLT_s32,
        GIM_CheckType, /*MI*/0, /*Op*/3, /*Type*/GILLT_s32,
        GIM_CheckRegBankForClass, /*MI*/0, /*Op*/0, /*RC*/GIMT_Encode2(AMDGPU::VGPR_32RegClassID),
        GIM_CheckComplexPattern, /*MI*/0, /*Op*/2, /*Renderer*/GIMT_Encode2(0), GIMT_Encode2(GICP_gi_vop3mods),
        GIM_CheckComplexPattern, /*MI*/0, /*Op*/3, /*Renderer*/GIMT_Encode2(1), GIMT_Encode2(GICP_gi_vop3mods0),
        // (intrinsic_wo_chain:{ *:[f32] } 1973:{ *:[iPTR] }, (VOP3Mods:{ *:[f32] } f32:{ *:[f32] }:$src1, i32:{ *:[i32] }:$src1_modifiers), (VOP3Mods0:{ *:[f32] } f32:{ *:[f32] }:$src0, i32:{ *:[i32] }:$src0_modifiers, i1:{ *:[i1] }:$clamp, i32:{ *:[i32] }:$omod))  =>  (V_MUL_LEGACY_F32_e64:{ *:[f32] } i32:{ *:[i32] }:$src0_modifiers, f32:{ *:[f32] }:$src0, i32:{ *:[i32] }:$src1_modifiers, f32:{ *:[f32] }:$src1, i1:{ *:[i1] }:$clamp, i32:{ *:[i32] }:$omod)
        GIR_BuildMI, /*InsnID*/0, /*Opcode*/GIMT_Encode2(AMDGPU::V_MUL_LEGACY_F32_e64),
        GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/0, // DstI[vdst]
        GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(1), /*SubOperand*/1, // src0_modifiers
        GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(1), /*SubOperand*/0, // src0
        GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/1, // src1_modifiers
        GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/0, // src1
        GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(1), /*SubOperand*/2, // clamp
        GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(1), /*SubOperand*/3, // omod
        GIR_ConstrainSelectedInstOperands, /*InsnID*/0,
        GIR_EraseFromParent, /*InsnID*/0,
        // GIR_Coverage, 7127,
        GIR_Done,
      // Label 3139: @201390
      GIM_Try, /*On fail goto*//*Label 3140*/ GIMT_Encode4(201451), // Rule ID 557 //
        GIM_CheckIntrinsicID, /*MI*/0, /*Op*/1, GIMT_Encode2(Intrinsic::amdgcn_class),
        GIM_CheckType, /*MI*/0, /*Op*/0, /*Type*/GILLT_s1,
        GIM_CheckType, /*MI*/0, /*Op*/2, /*Type*/GILLT_s32,
        GIM_CheckType, /*MI*/0, /*Op*/3, /*Type*/GILLT_s32,
        GIM_CheckRegBankForClass, /*MI*/0, /*Op*/0, /*RC*/GIMT_Encode2(AMDGPU::SReg_1RegClassID),
        GIM_CheckComplexPattern, /*MI*/0, /*Op*/2, /*Renderer*/GIMT_Encode2(0), GIMT_Encode2(GICP_gi_vop3modsnoncanonicalizing),
        // (intrinsic_wo_chain:{ *:[i1] } 1901:{ *:[iPTR] }, (VOP3ModsNonCanonicalizing:{ *:[f32] } f32:{ *:[f32] }:$src0, i32:{ *:[i32] }:$src0_modifiers), i32:{ *:[i32] }:$src1)  =>  (V_CMP_CLASS_F32_e64:{ *:[i1] } i32:{ *:[i32] }:$src0_modifiers, f32:{ *:[f32] }:$src0, i32:{ *:[i32] }:$src1)
        GIR_BuildMI, /*InsnID*/0, /*Opcode*/GIMT_Encode2(AMDGPU::V_CMP_CLASS_F32_e64),
        GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/0, // DstI[sdst]
        GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/1, // src0_modifiers
        GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/0, // src0
        GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/3, // src1
        GIR_ConstrainSelectedInstOperands, /*InsnID*/0,
        GIR_EraseFromParent, /*InsnID*/0,
        // GIR_Coverage, 557,
        GIR_Done,
      // Label 3140: @201451
      GIM_Try, /*On fail goto*//*Label 3141*/ GIMT_Encode4(201512), // Rule ID 559 //
        GIM_CheckIntrinsicID, /*MI*/0, /*Op*/1, GIMT_Encode2(Intrinsic::amdgcn_class),
        GIM_CheckType, /*MI*/0, /*Op*/0, /*Type*/GILLT_s1,
        GIM_CheckType, /*MI*/0, /*Op*/2, /*Type*/GILLT_s32,
        GIM_CheckType, /*MI*/0, /*Op*/3, /*Type*/GILLT_s32,
        GIM_CheckRegBankForClass, /*MI*/0, /*Op*/0, /*RC*/GIMT_Encode2(AMDGPU::SReg_1RegClassID),
        GIM_CheckComplexPattern, /*MI*/0, /*Op*/2, /*Renderer*/GIMT_Encode2(0), GIMT_Encode2(GICP_gi_vop3modsnoncanonicalizing),
        // (intrinsic_wo_chain:{ *:[i1] } 1901:{ *:[iPTR] }, (VOP3ModsNonCanonicalizing:{ *:[f32] } f32:{ *:[f32] }:$src0, i32:{ *:[i32] }:$src0_modifiers), i32:{ *:[i32] }:$src1)  =>  (V_CMPX_CLASS_F32_e64:{ *:[i1] } i32:{ *:[i32] }:$src0_modifiers, f32:{ *:[f32] }:$src0, i32:{ *:[i32] }:$src1)
        GIR_BuildMI, /*InsnID*/0, /*Opcode*/GIMT_Encode2(AMDGPU::V_CMPX_CLASS_F32_e64),
        GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/0, // DstI[sdst]
        GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/1, // src0_modifiers
        GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/0, // src0
        GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/3, // src1
        GIR_ConstrainSelectedInstOperands, /*InsnID*/0,
        GIR_EraseFromParent, /*InsnID*/0,
        // GIR_Coverage, 559,
        GIR_Done,
      // Label 3141: @201512
      GIM_Try, /*On fail goto*//*Label 3142*/ GIMT_Encode4(201573), // Rule ID 561 //
        GIM_CheckIntrinsicID, /*MI*/0, /*Op*/1, GIMT_Encode2(Intrinsic::amdgcn_class),
        GIM_CheckType, /*MI*/0, /*Op*/0, /*Type*/GILLT_s1,
        GIM_CheckType, /*MI*/0, /*Op*/2, /*Type*/GILLT_s64,
        GIM_CheckType, /*MI*/0, /*Op*/3, /*Type*/GILLT_s32,
        GIM_CheckRegBankForClass, /*MI*/0, /*Op*/0, /*RC*/GIMT_Encode2(AMDGPU::SReg_1RegClassID),
        GIM_CheckComplexPattern, /*MI*/0, /*Op*/2, /*Renderer*/GIMT_Encode2(0), GIMT_Encode2(GICP_gi_vop3modsnoncanonicalizing),
        // (intrinsic_wo_chain:{ *:[i1] } 1901:{ *:[iPTR] }, (VOP3ModsNonCanonicalizing:{ *:[f64] } f64:{ *:[f64] }:$src0, i32:{ *:[i32] }:$src0_modifiers), i32:{ *:[i32] }:$src1)  =>  (V_CMP_CLASS_F64_e64:{ *:[i1] } i32:{ *:[i32] }:$src0_modifiers, f64:{ *:[f64] }:$src0, i32:{ *:[i32] }:$src1)
        GIR_BuildMI, /*InsnID*/0, /*Opcode*/GIMT_Encode2(AMDGPU::V_CMP_CLASS_F64_e64),
        GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/0, // DstI[sdst]
        GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/1, // src0_modifiers
        GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/0, // src0
        GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/3, // src1
        GIR_ConstrainSelectedInstOperands, /*InsnID*/0,
        GIR_EraseFromParent, /*InsnID*/0,
        // GIR_Coverage, 561,
        GIR_Done,
      // Label 3142: @201573
      GIM_Try, /*On fail goto*//*Label 3143*/ GIMT_Encode4(201634), // Rule ID 563 //
        GIM_CheckIntrinsicID, /*MI*/0, /*Op*/1, GIMT_Encode2(Intrinsic::amdgcn_class),
        GIM_CheckType, /*MI*/0, /*Op*/0, /*Type*/GILLT_s1,
        GIM_CheckType, /*MI*/0, /*Op*/2, /*Type*/GILLT_s64,
        GIM_CheckType, /*MI*/0, /*Op*/3, /*Type*/GILLT_s32,
        GIM_CheckRegBankForClass, /*MI*/0, /*Op*/0, /*RC*/GIMT_Encode2(AMDGPU::SReg_1RegClassID),
        GIM_CheckComplexPattern, /*MI*/0, /*Op*/2, /*Renderer*/GIMT_Encode2(0), GIMT_Encode2(GICP_gi_vop3modsnoncanonicalizing),
        // (intrinsic_wo_chain:{ *:[i1] } 1901:{ *:[iPTR] }, (VOP3ModsNonCanonicalizing:{ *:[f64] } f64:{ *:[f64] }:$src0, i32:{ *:[i32] }:$src0_modifiers), i32:{ *:[i32] }:$src1)  =>  (V_CMPX_CLASS_F64_e64:{ *:[i1] } i32:{ *:[i32] }:$src0_modifiers, f64:{ *:[f64] }:$src0, i32:{ *:[i32] }:$src1)
        GIR_BuildMI, /*InsnID*/0, /*Opcode*/GIMT_Encode2(AMDGPU::V_CMPX_CLASS_F64_e64),
        GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/0, // DstI[sdst]
        GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/1, // src0_modifiers
        GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/0, // src0
        GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/3, // src1
        GIR_ConstrainSelectedInstOperands, /*InsnID*/0,
        GIR_EraseFromParent, /*InsnID*/0,
        // GIR_Coverage, 563,
        GIR_Done,
      // Label 3143: @201634
      GIM_Try, /*On fail goto*//*Label 3144*/ GIMT_Encode4(201698), // Rule ID 565 //
        GIM_CheckFeatures, GIMT_Encode2(GIFBS_Has16BitInsts_NotHasTrue16BitInsts),
        GIM_CheckIntrinsicID, /*MI*/0, /*Op*/1, GIMT_Encode2(Intrinsic::amdgcn_class),
        GIM_CheckType, /*MI*/0, /*Op*/0, /*Type*/GILLT_s1,
        GIM_CheckType, /*MI*/0, /*Op*/2, /*Type*/GILLT_s16,
        GIM_CheckType, /*MI*/0, /*Op*/3, /*Type*/GILLT_s32,
        GIM_CheckRegBankForClass, /*MI*/0, /*Op*/0, /*RC*/GIMT_Encode2(AMDGPU::SReg_1RegClassID),
        GIM_CheckComplexPattern, /*MI*/0, /*Op*/2, /*Renderer*/GIMT_Encode2(0), GIMT_Encode2(GICP_gi_vop3modsnoncanonicalizing),
        // (intrinsic_wo_chain:{ *:[i1] } 1901:{ *:[iPTR] }, (VOP3ModsNonCanonicalizing:{ *:[f16] } f16:{ *:[f16] }:$src0, i32:{ *:[i32] }:$src0_modifiers), i32:{ *:[i32] }:$src1)  =>  (V_CMP_CLASS_F16_e64:{ *:[i1] } i32:{ *:[i32] }:$src0_modifiers, f16:{ *:[f16] }:$src0, i32:{ *:[i32] }:$src1)
        GIR_BuildMI, /*InsnID*/0, /*Opcode*/GIMT_Encode2(AMDGPU::V_CMP_CLASS_F16_e64),
        GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/0, // DstI[sdst]
        GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/1, // src0_modifiers
        GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/0, // src0
        GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/3, // src1
        GIR_ConstrainSelectedInstOperands, /*InsnID*/0,
        GIR_EraseFromParent, /*InsnID*/0,
        // GIR_Coverage, 565,
        GIR_Done,
      // Label 3144: @201698
      GIM_Try, /*On fail goto*//*Label 3145*/ GIMT_Encode4(201762), // Rule ID 567 //
        GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasTrue16BitInsts),
        GIM_CheckIntrinsicID, /*MI*/0, /*Op*/1, GIMT_Encode2(Intrinsic::amdgcn_class),
        GIM_CheckType, /*MI*/0, /*Op*/0, /*Type*/GILLT_s1,
        GIM_CheckType, /*MI*/0, /*Op*/2, /*Type*/GILLT_s16,
        GIM_CheckType, /*MI*/0, /*Op*/3, /*Type*/GILLT_s32,
        GIM_CheckRegBankForClass, /*MI*/0, /*Op*/0, /*RC*/GIMT_Encode2(AMDGPU::SReg_1RegClassID),
        GIM_CheckComplexPattern, /*MI*/0, /*Op*/2, /*Renderer*/GIMT_Encode2(0), GIMT_Encode2(GICP_gi_vop3modsnoncanonicalizing),
        // (intrinsic_wo_chain:{ *:[i1] } 1901:{ *:[iPTR] }, (VOP3ModsNonCanonicalizing:{ *:[f16] } f16:{ *:[f16] }:$src0, i32:{ *:[i32] }:$src0_modifiers), i32:{ *:[i32] }:$src1)  =>  (V_CMP_CLASS_F16_t16_e64:{ *:[i1] } i32:{ *:[i32] }:$src0_modifiers, f16:{ *:[f16] }:$src0, i32:{ *:[i32] }:$src1)
        GIR_BuildMI, /*InsnID*/0, /*Opcode*/GIMT_Encode2(AMDGPU::V_CMP_CLASS_F16_t16_e64),
        GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/0, // DstI[sdst]
        GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/1, // src0_modifiers
        GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/0, // src0
        GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/3, // src1
        GIR_ConstrainSelectedInstOperands, /*InsnID*/0,
        GIR_EraseFromParent, /*InsnID*/0,
        // GIR_Coverage, 567,
        GIR_Done,
      // Label 3145: @201762
      GIM_Try, /*On fail goto*//*Label 3146*/ GIMT_Encode4(201826), // Rule ID 569 //
        GIM_CheckFeatures, GIMT_Encode2(GIFBS_Has16BitInsts_NotHasTrue16BitInsts),
        GIM_CheckIntrinsicID, /*MI*/0, /*Op*/1, GIMT_Encode2(Intrinsic::amdgcn_class),
        GIM_CheckType, /*MI*/0, /*Op*/0, /*Type*/GILLT_s1,
        GIM_CheckType, /*MI*/0, /*Op*/2, /*Type*/GILLT_s16,
        GIM_CheckType, /*MI*/0, /*Op*/3, /*Type*/GILLT_s32,
        GIM_CheckRegBankForClass, /*MI*/0, /*Op*/0, /*RC*/GIMT_Encode2(AMDGPU::SReg_1RegClassID),
        GIM_CheckComplexPattern, /*MI*/0, /*Op*/2, /*Renderer*/GIMT_Encode2(0), GIMT_Encode2(GICP_gi_vop3modsnoncanonicalizing),
        // (intrinsic_wo_chain:{ *:[i1] } 1901:{ *:[iPTR] }, (VOP3ModsNonCanonicalizing:{ *:[f16] } f16:{ *:[f16] }:$src0, i32:{ *:[i32] }:$src0_modifiers), i32:{ *:[i32] }:$src1)  =>  (V_CMPX_CLASS_F16_e64:{ *:[i1] } i32:{ *:[i32] }:$src0_modifiers, f16:{ *:[f16] }:$src0, i32:{ *:[i32] }:$src1)
        GIR_BuildMI, /*InsnID*/0, /*Opcode*/GIMT_Encode2(AMDGPU::V_CMPX_CLASS_F16_e64),
        GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/0, // DstI[sdst]
        GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/1, // src0_modifiers
        GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/0, // src0
        GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/3, // src1
        GIR_ConstrainSelectedInstOperands, /*InsnID*/0,
        GIR_EraseFromParent, /*InsnID*/0,
        // GIR_Coverage, 569,
        GIR_Done,
      // Label 3146: @201826
      GIM_Try, /*On fail goto*//*Label 3147*/ GIMT_Encode4(201890), // Rule ID 571 //
        GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasTrue16BitInsts),
        GIM_CheckIntrinsicID, /*MI*/0, /*Op*/1, GIMT_Encode2(Intrinsic::amdgcn_class),
        GIM_CheckType, /*MI*/0, /*Op*/0, /*Type*/GILLT_s1,
        GIM_CheckType, /*MI*/0, /*Op*/2, /*Type*/GILLT_s16,
        GIM_CheckType, /*MI*/0, /*Op*/3, /*Type*/GILLT_s32,
        GIM_CheckRegBankForClass, /*MI*/0, /*Op*/0, /*RC*/GIMT_Encode2(AMDGPU::SReg_1RegClassID),
        GIM_CheckComplexPattern, /*MI*/0, /*Op*/2, /*Renderer*/GIMT_Encode2(0), GIMT_Encode2(GICP_gi_vop3modsnoncanonicalizing),
        // (intrinsic_wo_chain:{ *:[i1] } 1901:{ *:[iPTR] }, (VOP3ModsNonCanonicalizing:{ *:[f16] } f16:{ *:[f16] }:$src0, i32:{ *:[i32] }:$src0_modifiers), i32:{ *:[i32] }:$src1)  =>  (V_CMPX_CLASS_F16_t16_e64:{ *:[i1] } i32:{ *:[i32] }:$src0_modifiers, f16:{ *:[f16] }:$src0, i32:{ *:[i32] }:$src1)
        GIR_BuildMI, /*InsnID*/0, /*Opcode*/GIMT_Encode2(AMDGPU::V_CMPX_CLASS_F16_t16_e64),
        GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/0, // DstI[sdst]
        GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/1, // src0_modifiers
        GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/0, // src0
        GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/3, // src1
        GIR_ConstrainSelectedInstOperands, /*InsnID*/0,
        GIR_EraseFromParent, /*InsnID*/0,
        // GIR_Coverage, 571,
        GIR_Done,
      // Label 3147: @201890
      GIM_Try, /*On fail goto*//*Label 3148*/ GIMT_Encode4(201941), // Rule ID 731 //
        GIM_CheckIntrinsicID, /*MI*/0, /*Op*/1, GIMT_Encode2(Intrinsic::amdgcn_mul_i24),
        GIM_CheckType, /*MI*/0, /*Op*/0, /*Type*/GILLT_s32,
        GIM_CheckType, /*MI*/0, /*Op*/2, /*Type*/GILLT_s32,
        GIM_CheckType, /*MI*/0, /*Op*/3, /*Type*/GILLT_s32,
        GIM_CheckRegBankForClass, /*MI*/0, /*Op*/0, /*RC*/GIMT_Encode2(AMDGPU::VGPR_32RegClassID),
        // (intrinsic_wo_chain:{ *:[i32] } 2584:{ *:[iPTR] }, i32:{ *:[i32] }:$src0, i32:{ *:[i32] }:$src1)  =>  (V_MUL_I32_I24_e64:{ *:[i32] } i32:{ *:[i32] }:$src0, i32:{ *:[i32] }:$src1)
        GIR_BuildMI, /*InsnID*/0, /*Opcode*/GIMT_Encode2(AMDGPU::V_MUL_I32_I24_e64),
        GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/0, // DstI[vdst]
        GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/2, // src0
        GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/3, // src1
        GIR_AddImm8, /*InsnID*/0, /*Imm*/0,
        GIR_ConstrainSelectedInstOperands, /*InsnID*/0,
        GIR_EraseFromParent, /*InsnID*/0,
        // GIR_Coverage, 731,
        GIR_Done,
      // Label 3148: @201941
      GIM_Try, /*On fail goto*//*Label 3149*/ GIMT_Encode4(201989), // Rule ID 733 //
        GIM_CheckIntrinsicID, /*MI*/0, /*Op*/1, GIMT_Encode2(Intrinsic::amdgcn_mulhi_i24),
        GIM_CheckType, /*MI*/0, /*Op*/0, /*Type*/GILLT_s32,
        GIM_CheckType, /*MI*/0, /*Op*/2, /*Type*/GILLT_s32,
        GIM_CheckType, /*MI*/0, /*Op*/3, /*Type*/GILLT_s32,
        GIM_CheckRegBankForClass, /*MI*/0, /*Op*/0, /*RC*/GIMT_Encode2(AMDGPU::VGPR_32RegClassID),
        // (intrinsic_wo_chain:{ *:[i32] } 2586:{ *:[iPTR] }, i32:{ *:[i32] }:$src0, i32:{ *:[i32] }:$src1)  =>  (V_MUL_HI_I32_I24_e64:{ *:[i32] } i32:{ *:[i32] }:$src0, i32:{ *:[i32] }:$src1)
        GIR_BuildMI, /*InsnID*/0, /*Opcode*/GIMT_Encode2(AMDGPU::V_MUL_HI_I32_I24_e64),
        GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/0, // DstI[vdst]
        GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/2, // src0
        GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/3, // src1
        GIR_ConstrainSelectedInstOperands, /*InsnID*/0,
        GIR_EraseFromParent, /*InsnID*/0,
        // GIR_Coverage, 733,
        GIR_Done,
      // Label 3149: @201989
      GIM_Try, /*On fail goto*//*Label 3150*/ GIMT_Encode4(202040), // Rule ID 735 //
        GIM_CheckIntrinsicID, /*MI*/0, /*Op*/1, GIMT_Encode2(Intrinsic::amdgcn_mul_u24),
        GIM_CheckType, /*MI*/0, /*Op*/0, /*Type*/GILLT_s32,
        GIM_CheckType, /*MI*/0, /*Op*/2, /*Type*/GILLT_s32,
        GIM_CheckType, /*MI*/0, /*Op*/3, /*Type*/GILLT_s32,
        GIM_CheckRegBankForClass, /*MI*/0, /*Op*/0, /*RC*/GIMT_Encode2(AMDGPU::VGPR_32RegClassID),
        // (intrinsic_wo_chain:{ *:[i32] } 2585:{ *:[iPTR] }, i32:{ *:[i32] }:$src0, i32:{ *:[i32] }:$src1)  =>  (V_MUL_U32_U24_e64:{ *:[i32] } i32:{ *:[i32] }:$src0, i32:{ *:[i32] }:$src1)
        GIR_BuildMI, /*InsnID*/0, /*Opcode*/GIMT_Encode2(AMDGPU::V_MUL_U32_U24_e64),
        GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/0, // DstI[vdst]
        GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/2, // src0
        GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/3, // src1
        GIR_AddImm8, /*InsnID*/0, /*Imm*/0,
        GIR_ConstrainSelectedInstOperands, /*InsnID*/0,
        GIR_EraseFromParent, /*InsnID*/0,
        // GIR_Coverage, 735,
        GIR_Done,
      // Label 3150: @202040
      GIM_Try, /*On fail goto*//*Label 3151*/ GIMT_Encode4(202088), // Rule ID 737 //
        GIM_CheckIntrinsicID, /*MI*/0, /*Op*/1, GIMT_Encode2(Intrinsic::amdgcn_mulhi_u24),
        GIM_CheckType, /*MI*/0, /*Op*/0, /*Type*/GILLT_s32,
        GIM_CheckType, /*MI*/0, /*Op*/2, /*Type*/GILLT_s32,
        GIM_CheckType, /*MI*/0, /*Op*/3, /*Type*/GILLT_s32,
        GIM_CheckRegBankForClass, /*MI*/0, /*Op*/0, /*RC*/GIMT_Encode2(AMDGPU::VGPR_32RegClassID),
        // (intrinsic_wo_chain:{ *:[i32] } 2587:{ *:[iPTR] }, i32:{ *:[i32] }:$src0, i32:{ *:[i32] }:$src1)  =>  (V_MUL_HI_U32_U24_e64:{ *:[i32] } i32:{ *:[i32] }:$src0, i32:{ *:[i32] }:$src1)
        GIR_BuildMI, /*InsnID*/0, /*Opcode*/GIMT_Encode2(AMDGPU::V_MUL_HI_U32_U24_e64),
        GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/0, // DstI[vdst]
        GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/2, // src0
        GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/3, // src1
        GIR_ConstrainSelectedInstOperands, /*InsnID*/0,
        GIR_EraseFromParent, /*InsnID*/0,
        // GIR_Coverage, 737,
        GIR_Done,
      // Label 3151: @202088
      GIM_Try, /*On fail goto*//*Label 3152*/ GIMT_Encode4(202136), // Rule ID 759 //
        GIM_CheckIntrinsicID, /*MI*/0, /*Op*/1, GIMT_Encode2(Intrinsic::amdgcn_mbcnt_lo),
        GIM_CheckType, /*MI*/0, /*Op*/0, /*Type*/GILLT_s32,
        GIM_CheckType, /*MI*/0, /*Op*/2, /*Type*/GILLT_s32,
        GIM_CheckType, /*MI*/0, /*Op*/3, /*Type*/GILLT_s32,
        GIM_CheckRegBankForClass, /*MI*/0, /*Op*/0, /*RC*/GIMT_Encode2(AMDGPU::VGPR_32RegClassID),
        // (intrinsic_wo_chain:{ *:[i32] } 2539:{ *:[iPTR] }, i32:{ *:[i32] }:$src0, i32:{ *:[i32] }:$src1)  =>  (V_MBCNT_LO_U32_B32_e64:{ *:[i32] } i32:{ *:[i32] }:$src0, i32:{ *:[i32] }:$src1)
        GIR_BuildMI, /*InsnID*/0, /*Opcode*/GIMT_Encode2(AMDGPU::V_MBCNT_LO_U32_B32_e64),
        GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/0, // DstI[vdst]
        GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/2, // src0
        GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/3, // src1
        GIR_ConstrainSelectedInstOperands, /*InsnID*/0,
        GIR_EraseFromParent, /*InsnID*/0,
        // GIR_Coverage, 759,
        GIR_Done,
      // Label 3152: @202136
      GIM_Try, /*On fail goto*//*Label 3153*/ GIMT_Encode4(202184), // Rule ID 760 //
        GIM_CheckIntrinsicID, /*MI*/0, /*Op*/1, GIMT_Encode2(Intrinsic::amdgcn_mbcnt_hi),
        GIM_CheckType, /*MI*/0, /*Op*/0, /*Type*/GILLT_s32,
        GIM_CheckType, /*MI*/0, /*Op*/2, /*Type*/GILLT_s32,
        GIM_CheckType, /*MI*/0, /*Op*/3, /*Type*/GILLT_s32,
        GIM_CheckRegBankForClass, /*MI*/0, /*Op*/0, /*RC*/GIMT_Encode2(AMDGPU::VGPR_32RegClassID),
        // (intrinsic_wo_chain:{ *:[i32] } 2538:{ *:[iPTR] }, i32:{ *:[i32] }:$src0, i32:{ *:[i32] }:$src1)  =>  (V_MBCNT_HI_U32_B32_e64:{ *:[i32] } i32:{ *:[i32] }:$src0, i32:{ *:[i32] }:$src1)
        GIR_BuildMI, /*InsnID*/0, /*Opcode*/GIMT_Encode2(AMDGPU::V_MBCNT_HI_U32_B32_e64),
        GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/0, // DstI[vdst]
        GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/2, // src0
        GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/3, // src1
        GIR_ConstrainSelectedInstOperands, /*InsnID*/0,
        GIR_EraseFromParent, /*InsnID*/0,
        // GIR_Coverage, 760,
        GIR_Done,
      // Label 3153: @202184
      GIM_Try, /*On fail goto*//*Label 3154*/ GIMT_Encode4(202232), // Rule ID 769 //
        GIM_CheckIntrinsicID, /*MI*/0, /*Op*/1, GIMT_Encode2(Intrinsic::amdgcn_cvt_pk_u16),
        GIM_CheckType, /*MI*/0, /*Op*/0, /*Type*/GILLT_v2s16,
        GIM_CheckType, /*MI*/0, /*Op*/2, /*Type*/GILLT_s32,
        GIM_CheckType, /*MI*/0, /*Op*/3, /*Type*/GILLT_s32,
        GIM_CheckRegBankForClass, /*MI*/0, /*Op*/0, /*RC*/GIMT_Encode2(AMDGPU::VGPR_32RegClassID),
        // (intrinsic_wo_chain:{ *:[v2i16] } 1915:{ *:[iPTR] }, i32:{ *:[i32] }:$src0, i32:{ *:[i32] }:$src1)  =>  (V_CVT_PK_U16_U32_e64:{ *:[v2i16] } i32:{ *:[i32] }:$src0, i32:{ *:[i32] }:$src1)
        GIR_BuildMI, /*InsnID*/0, /*Opcode*/GIMT_Encode2(AMDGPU::V_CVT_PK_U16_U32_e64),
        GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/0, // DstI[vdst]
        GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/2, // src0
        GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/3, // src1
        GIR_ConstrainSelectedInstOperands, /*InsnID*/0,
        GIR_EraseFromParent, /*InsnID*/0,
        // GIR_Coverage, 769,
        GIR_Done,
      // Label 3154: @202232
      GIM_Try, /*On fail goto*//*Label 3155*/ GIMT_Encode4(202280), // Rule ID 771 //
        GIM_CheckIntrinsicID, /*MI*/0, /*Op*/1, GIMT_Encode2(Intrinsic::amdgcn_cvt_pk_i16),
        GIM_CheckType, /*MI*/0, /*Op*/0, /*Type*/GILLT_v2s16,
        GIM_CheckType, /*MI*/0, /*Op*/2, /*Type*/GILLT_s32,
        GIM_CheckType, /*MI*/0, /*Op*/3, /*Type*/GILLT_s32,
        GIM_CheckRegBankForClass, /*MI*/0, /*Op*/0, /*RC*/GIMT_Encode2(AMDGPU::VGPR_32RegClassID),
        // (intrinsic_wo_chain:{ *:[v2i16] } 1914:{ *:[iPTR] }, i32:{ *:[i32] }:$src0, i32:{ *:[i32] }:$src1)  =>  (V_CVT_PK_I16_I32_e64:{ *:[v2i16] } i32:{ *:[i32] }:$src0, i32:{ *:[i32] }:$src1)
        GIR_BuildMI, /*InsnID*/0, /*Opcode*/GIMT_Encode2(AMDGPU::V_CVT_PK_I16_I32_e64),
        GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/0, // DstI[vdst]
        GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/2, // src0
        GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/3, // src1
        GIR_ConstrainSelectedInstOperands, /*InsnID*/0,
        GIR_EraseFromParent, /*InsnID*/0,
        // GIR_Coverage, 771,
        GIR_Done,
      // Label 3155: @202280
      GIM_Reject,
    // Label 3104: @202281
    GIM_Try, /*On fail goto*//*Label 3156*/ GIMT_Encode4(205786),
      GIM_CheckNumOperands, /*MI*/0, /*Expected*/5,
      GIM_Try, /*On fail goto*//*Label 3157*/ GIMT_Encode4(202390), // Rule ID 5835 //
        GIM_CheckIntrinsicID, /*MI*/0, /*Op*/1, GIMT_Encode2(Intrinsic::amdgcn_interp_inreg_p10),
        GIM_CheckType, /*MI*/0, /*Op*/0, /*Type*/GILLT_s32,
        GIM_CheckType, /*MI*/0, /*Op*/2, /*Type*/GILLT_s32,
        GIM_CheckType, /*MI*/0, /*Op*/3, /*Type*/GILLT_s32,
        GIM_CheckType, /*MI*/0, /*Op*/4, /*Type*/GILLT_s32,
        GIM_CheckRegBankForClass, /*MI*/0, /*Op*/0, /*RC*/GIMT_Encode2(AMDGPU::VGPR_32RegClassID),
        GIM_CheckComplexPattern, /*MI*/0, /*Op*/2, /*Renderer*/GIMT_Encode2(0), GIMT_Encode2(GICP_gi_vinterpmods),
        GIM_CheckComplexPattern, /*MI*/0, /*Op*/3, /*Renderer*/GIMT_Encode2(1), GIMT_Encode2(GICP_gi_vinterpmods),
        GIM_CheckComplexPattern, /*MI*/0, /*Op*/4, /*Renderer*/GIMT_Encode2(2), GIMT_Encode2(GICP_gi_vinterpmods),
        // (intrinsic_wo_chain:{ *:[f32] } 2515:{ *:[iPTR] }, (VINTERPMods:{ *:[f32] } f32:{ *:[f32] }:$src0, i32:{ *:[i32] }:$src0_modifiers), (VINTERPMods:{ *:[f32] } f32:{ *:[f32] }:$src1, i32:{ *:[i32] }:$src1_modifiers), (VINTERPMods:{ *:[f32] } f32:{ *:[f32] }:$src2, i32:{ *:[i32] }:$src2_modifiers))  =>  (V_INTERP_P10_F32_inreg:{ *:[f32] } ?:{ *:[i32] }:$src0_modifiers, ?:{ *:[f32] }:$src0, ?:{ *:[i32] }:$src1_modifiers, ?:{ *:[f32] }:$src1, ?:{ *:[i32] }:$src2_modifiers, ?:{ *:[f32] }:$src2, 0:{ *:[i1] }, 7:{ *:[i8] })
        GIR_BuildMI, /*InsnID*/0, /*Opcode*/GIMT_Encode2(AMDGPU::V_INTERP_P10_F32_inreg),
        GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/0, // DstI[vdst]
        GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/1, // src0_modifiers
        GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/0, // src0
        GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(1), /*SubOperand*/1, // src1_modifiers
        GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(1), /*SubOperand*/0, // src1
        GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(2), /*SubOperand*/1, // src2_modifiers
        GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(2), /*SubOperand*/0, // src2
        GIR_AddImm8, /*InsnID*/0, /*Imm*/0,
        GIR_AddImm8, /*InsnID*/0, /*Imm*/7,
        GIR_ConstrainSelectedInstOperands, /*InsnID*/0,
        GIR_EraseFromParent, /*InsnID*/0,
        // GIR_Coverage, 5835,
        GIR_Done,
      // Label 3157: @202390
      GIM_Try, /*On fail goto*//*Label 3158*/ GIMT_Encode4(202491), // Rule ID 5836 //
        GIM_CheckIntrinsicID, /*MI*/0, /*Op*/1, GIMT_Encode2(Intrinsic::amdgcn_interp_inreg_p2),
        GIM_CheckType, /*MI*/0, /*Op*/0, /*Type*/GILLT_s32,
        GIM_CheckType, /*MI*/0, /*Op*/2, /*Type*/GILLT_s32,
        GIM_CheckType, /*MI*/0, /*Op*/3, /*Type*/GILLT_s32,
        GIM_CheckType, /*MI*/0, /*Op*/4, /*Type*/GILLT_s32,
        GIM_CheckRegBankForClass, /*MI*/0, /*Op*/0, /*RC*/GIMT_Encode2(AMDGPU::VGPR_32RegClassID),
        GIM_CheckComplexPattern, /*MI*/0, /*Op*/2, /*Renderer*/GIMT_Encode2(0), GIMT_Encode2(GICP_gi_vinterpmods),
        GIM_CheckComplexPattern, /*MI*/0, /*Op*/3, /*Renderer*/GIMT_Encode2(1), GIMT_Encode2(GICP_gi_vinterpmods),
        GIM_CheckComplexPattern, /*MI*/0, /*Op*/4, /*Renderer*/GIMT_Encode2(2), GIMT_Encode2(GICP_gi_vinterpmods),
        // (intrinsic_wo_chain:{ *:[f32] } 2517:{ *:[iPTR] }, (VINTERPMods:{ *:[f32] } f32:{ *:[f32] }:$src0, i32:{ *:[i32] }:$src0_modifiers), (VINTERPMods:{ *:[f32] } f32:{ *:[f32] }:$src1, i32:{ *:[i32] }:$src1_modifiers), (VINTERPMods:{ *:[f32] } f32:{ *:[f32] }:$src2, i32:{ *:[i32] }:$src2_modifiers))  =>  (V_INTERP_P2_F32_inreg:{ *:[f32] } ?:{ *:[i32] }:$src0_modifiers, ?:{ *:[f32] }:$src0, ?:{ *:[i32] }:$src1_modifiers, ?:{ *:[f32] }:$src1, ?:{ *:[i32] }:$src2_modifiers, ?:{ *:[f32] }:$src2, 0:{ *:[i1] }, 7:{ *:[i8] })
        GIR_BuildMI, /*InsnID*/0, /*Opcode*/GIMT_Encode2(AMDGPU::V_INTERP_P2_F32_inreg),
        GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/0, // DstI[vdst]
        GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/1, // src0_modifiers
        GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/0, // src0
        GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(1), /*SubOperand*/1, // src1_modifiers
        GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(1), /*SubOperand*/0, // src1
        GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(2), /*SubOperand*/1, // src2_modifiers
        GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(2), /*SubOperand*/0, // src2
        GIR_AddImm8, /*InsnID*/0, /*Imm*/0,
        GIR_AddImm8, /*InsnID*/0, /*Imm*/7,
        GIR_ConstrainSelectedInstOperands, /*InsnID*/0,
        GIR_EraseFromParent, /*InsnID*/0,
        // GIR_Coverage, 5836,
        GIR_Done,
      // Label 3158: @202491
      GIM_Try, /*On fail goto*//*Label 3159*/ GIMT_Encode4(202589), // Rule ID 5887 //
        GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasMadMacF32Insts),
        GIM_CheckIntrinsicID, /*MI*/0, /*Op*/1, GIMT_Encode2(Intrinsic::amdgcn_fmad_ftz),
        GIM_CheckType, /*MI*/0, /*Op*/0, /*Type*/GILLT_s32,
        GIM_CheckType, /*MI*/0, /*Op*/2, /*Type*/GILLT_s32,
        GIM_CheckType, /*MI*/0, /*Op*/3, /*Type*/GILLT_s32,
        GIM_CheckType, /*MI*/0, /*Op*/4, /*Type*/GILLT_s32,
        GIM_CheckRegBankForClass, /*MI*/0, /*Op*/0, /*RC*/GIMT_Encode2(AMDGPU::VGPR_32RegClassID),
        GIM_CheckComplexPattern, /*MI*/0, /*Op*/2, /*Renderer*/GIMT_Encode2(0), GIMT_Encode2(GICP_gi_vop3_no_mods),
        GIM_CheckComplexPattern, /*MI*/0, /*Op*/3, /*Renderer*/GIMT_Encode2(1), GIMT_Encode2(GICP_gi_vop3_no_mods),
        GIM_CheckComplexPattern, /*MI*/0, /*Op*/4, /*Renderer*/GIMT_Encode2(2), GIMT_Encode2(GICP_gi_vop3_no_mods),
        // (intrinsic_wo_chain:{ *:[f32] } 1971:{ *:[iPTR] }, (VOP3NoMods:{ *:[f32] } f32:{ *:[f32] }:$src0), (VOP3NoMods:{ *:[f32] } f32:{ *:[f32] }:$src1), (VOP3NoMods:{ *:[f32] } f32:{ *:[f32] }:$src2))  =>  (V_MAC_F32_e64:{ *:[f32] } 0:{ *:[i32] }, ?:{ *:[f32] }:$src0, 0:{ *:[i32] }, ?:{ *:[f32] }:$src1, 0:{ *:[i32] }, ?:{ *:[f32] }:$src2, 0:{ *:[i1] }, 0:{ *:[i32] })
        GIR_BuildMI, /*InsnID*/0, /*Opcode*/GIMT_Encode2(AMDGPU::V_MAC_F32_e64),
        GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/0, // DstI[vdst]
        GIR_AddImm8, /*InsnID*/0, /*Imm*/0,
        GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/0, // src0
        GIR_AddImm8, /*InsnID*/0, /*Imm*/0,
        GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(1), /*SubOperand*/0, // src1
        GIR_AddImm8, /*InsnID*/0, /*Imm*/0,
        GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(2), /*SubOperand*/0, // src2
        GIR_AddImm8, /*InsnID*/0, /*Imm*/0,
        GIR_AddImm8, /*InsnID*/0, /*Imm*/0,
        GIR_ConstrainSelectedInstOperands, /*InsnID*/0,
        GIR_EraseFromParent, /*InsnID*/0,
        // GIR_Coverage, 5887,
        GIR_Done,
      // Label 3159: @202589
      GIM_Try, /*On fail goto*//*Label 3160*/ GIMT_Encode4(202687), // Rule ID 5891 //
        GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasFmaLegacy32),
        GIM_CheckIntrinsicID, /*MI*/0, /*Op*/1, GIMT_Encode2(Intrinsic::amdgcn_fma_legacy),
        GIM_CheckType, /*MI*/0, /*Op*/0, /*Type*/GILLT_s32,
        GIM_CheckType, /*MI*/0, /*Op*/2, /*Type*/GILLT_s32,
        GIM_CheckType, /*MI*/0, /*Op*/3, /*Type*/GILLT_s32,
        GIM_CheckType, /*MI*/0, /*Op*/4, /*Type*/GILLT_s32,
        GIM_CheckRegBankForClass, /*MI*/0, /*Op*/0, /*RC*/GIMT_Encode2(AMDGPU::VGPR_32RegClassID),
        GIM_CheckComplexPattern, /*MI*/0, /*Op*/2, /*Renderer*/GIMT_Encode2(0), GIMT_Encode2(GICP_gi_vop3_no_mods),
        GIM_CheckComplexPattern, /*MI*/0, /*Op*/3, /*Renderer*/GIMT_Encode2(1), GIMT_Encode2(GICP_gi_vop3_no_mods),
        GIM_CheckComplexPattern, /*MI*/0, /*Op*/4, /*Renderer*/GIMT_Encode2(2), GIMT_Encode2(GICP_gi_vop3_no_mods),
        // (intrinsic_wo_chain:{ *:[f32] } 1970:{ *:[iPTR] }, (VOP3NoMods:{ *:[f32] } f32:{ *:[f32] }:$src0), (VOP3NoMods:{ *:[f32] } f32:{ *:[f32] }:$src1), (VOP3NoMods:{ *:[f32] } f32:{ *:[f32] }:$src2))  =>  (V_FMAC_LEGACY_F32_e64:{ *:[f32] } 0:{ *:[i32] }, ?:{ *:[f32] }:$src0, 0:{ *:[i32] }, ?:{ *:[f32] }:$src1, 0:{ *:[i32] }, ?:{ *:[f32] }:$src2, 0:{ *:[i1] }, 0:{ *:[i32] })
        GIR_BuildMI, /*InsnID*/0, /*Opcode*/GIMT_Encode2(AMDGPU::V_FMAC_LEGACY_F32_e64),
        GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/0, // DstI[vdst]
        GIR_AddImm8, /*InsnID*/0, /*Imm*/0,
        GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/0, // src0
        GIR_AddImm8, /*InsnID*/0, /*Imm*/0,
        GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(1), /*SubOperand*/0, // src1
        GIR_AddImm8, /*InsnID*/0, /*Imm*/0,
        GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(2), /*SubOperand*/0, // src2
        GIR_AddImm8, /*InsnID*/0, /*Imm*/0,
        GIR_AddImm8, /*InsnID*/0, /*Imm*/0,
        GIR_ConstrainSelectedInstOperands, /*InsnID*/0,
        GIR_EraseFromParent, /*InsnID*/0,
        // GIR_Coverage, 5891,
        GIR_Done,
      // Label 3160: @202687
      GIM_Try, /*On fail goto*//*Label 3161*/ GIMT_Encode4(202785), // Rule ID 5893 //
        GIM_CheckFeatures, GIMT_Encode2(GIFBS_Has16BitInsts),
        GIM_CheckIntrinsicID, /*MI*/0, /*Op*/1, GIMT_Encode2(Intrinsic::amdgcn_fmad_ftz),
        GIM_CheckType, /*MI*/0, /*Op*/0, /*Type*/GILLT_s16,
        GIM_CheckType, /*MI*/0, /*Op*/2, /*Type*/GILLT_s16,
        GIM_CheckType, /*MI*/0, /*Op*/3, /*Type*/GILLT_s16,
        GIM_CheckType, /*MI*/0, /*Op*/4, /*Type*/GILLT_s16,
        GIM_CheckRegBankForClass, /*MI*/0, /*Op*/0, /*RC*/GIMT_Encode2(AMDGPU::VGPR_32RegClassID),
        GIM_CheckComplexPattern, /*MI*/0, /*Op*/2, /*Renderer*/GIMT_Encode2(0), GIMT_Encode2(GICP_gi_vop3_no_mods),
        GIM_CheckComplexPattern, /*MI*/0, /*Op*/3, /*Renderer*/GIMT_Encode2(1), GIMT_Encode2(GICP_gi_vop3_no_mods),
        GIM_CheckComplexPattern, /*MI*/0, /*Op*/4, /*Renderer*/GIMT_Encode2(2), GIMT_Encode2(GICP_gi_vop3_no_mods),
        // (intrinsic_wo_chain:{ *:[f16] } 1971:{ *:[iPTR] }, (VOP3NoMods:{ *:[f16] } f16:{ *:[f16] }:$src0), (VOP3NoMods:{ *:[f16] } f16:{ *:[f16] }:$src1), (VOP3NoMods:{ *:[f16] } f16:{ *:[f16] }:$src2))  =>  (V_MAC_F16_e64:{ *:[f16] } 0:{ *:[i32] }, ?:{ *:[f16] }:$src0, 0:{ *:[i32] }, ?:{ *:[f16] }:$src1, 0:{ *:[i32] }, ?:{ *:[f16] }:$src2, 0:{ *:[i1] }, 0:{ *:[i32] })
        GIR_BuildMI, /*InsnID*/0, /*Opcode*/GIMT_Encode2(AMDGPU::V_MAC_F16_e64),
        GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/0, // DstI[vdst]
        GIR_AddImm8, /*InsnID*/0, /*Imm*/0,
        GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/0, // src0
        GIR_AddImm8, /*InsnID*/0, /*Imm*/0,
        GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(1), /*SubOperand*/0, // src1
        GIR_AddImm8, /*InsnID*/0, /*Imm*/0,
        GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(2), /*SubOperand*/0, // src2
        GIR_AddImm8, /*InsnID*/0, /*Imm*/0,
        GIR_AddImm8, /*InsnID*/0, /*Imm*/0,
        GIR_ConstrainSelectedInstOperands, /*InsnID*/0,
        GIR_EraseFromParent, /*InsnID*/0,
        // GIR_Coverage, 5893,
        GIR_Done,
      // Label 3161: @202785
      GIM_Try, /*On fail goto*//*Label 3162*/ GIMT_Encode4(202863), // Rule ID 2271 //
        GIM_CheckFeatures, GIMT_Encode2(GIFBS_isGFX12Plus),
        GIM_CheckIntrinsicID, /*MI*/0, /*Op*/1, GIMT_Encode2(Intrinsic::amdgcn_dot4_f32_fp8_bf8),
        GIM_CheckType, /*MI*/0, /*Op*/0, /*Type*/GILLT_s32,
        GIM_CheckType, /*MI*/0, /*Op*/2, /*Type*/GILLT_s32,
        GIM_CheckType, /*MI*/0, /*Op*/3, /*Type*/GILLT_s32,
        GIM_CheckType, /*MI*/0, /*Op*/4, /*Type*/GILLT_s32,
        GIM_CheckRegBankForClass, /*MI*/0, /*Op*/0, /*RC*/GIMT_Encode2(AMDGPU::VGPR_32RegClassID),
        GIM_CheckComplexPattern, /*MI*/0, /*Op*/4, /*Renderer*/GIMT_Encode2(0), GIMT_Encode2(GICP_gi_vop3mods),
        // (intrinsic_wo_chain:{ *:[f32] } 1929:{ *:[iPTR] }, i32:{ *:[i32] }:$src0, i32:{ *:[i32] }:$src1, (VOP3Mods:{ *:[f32] } f32:{ *:[f32] }:$src2, i32:{ *:[i32] }:$src2_modifiers))  =>  (V_DOT4_F32_FP8_BF8:{ *:[f32] } i32:{ *:[i32] }:$src0, i32:{ *:[i32] }:$src1, i32:{ *:[i32] }:$src2_modifiers, f32:{ *:[f32] }:$src2)
        GIR_BuildMI, /*InsnID*/0, /*Opcode*/GIMT_Encode2(AMDGPU::V_DOT4_F32_FP8_BF8),
        GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/0, // DstI[vdst]
        GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/2, // src0
        GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/3, // src1
        GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/1, // src2_modifiers
        GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/0, // src2
        GIR_AddImm8, /*InsnID*/0, /*Imm*/0,
        GIR_AddImm8, /*InsnID*/0, /*Imm*/0,
        GIR_ConstrainSelectedInstOperands, /*InsnID*/0,
        GIR_EraseFromParent, /*InsnID*/0,
        // GIR_Coverage, 2271,
        GIR_Done,
      // Label 3162: @202863
      GIM_Try, /*On fail goto*//*Label 3163*/ GIMT_Encode4(202941), // Rule ID 2272 //
        GIM_CheckFeatures, GIMT_Encode2(GIFBS_isGFX12Plus),
        GIM_CheckIntrinsicID, /*MI*/0, /*Op*/1, GIMT_Encode2(Intrinsic::amdgcn_dot4_f32_bf8_fp8),
        GIM_CheckType, /*MI*/0, /*Op*/0, /*Type*/GILLT_s32,
        GIM_CheckType, /*MI*/0, /*Op*/2, /*Type*/GILLT_s32,
        GIM_CheckType, /*MI*/0, /*Op*/3, /*Type*/GILLT_s32,
        GIM_CheckType, /*MI*/0, /*Op*/4, /*Type*/GILLT_s32,
        GIM_CheckRegBankForClass, /*MI*/0, /*Op*/0, /*RC*/GIMT_Encode2(AMDGPU::VGPR_32RegClassID),
        GIM_CheckComplexPattern, /*MI*/0, /*Op*/4, /*Renderer*/GIMT_Encode2(0), GIMT_Encode2(GICP_gi_vop3mods),
        // (intrinsic_wo_chain:{ *:[f32] } 1928:{ *:[iPTR] }, i32:{ *:[i32] }:$src0, i32:{ *:[i32] }:$src1, (VOP3Mods:{ *:[f32] } f32:{ *:[f32] }:$src2, i32:{ *:[i32] }:$src2_modifiers))  =>  (V_DOT4_F32_BF8_FP8:{ *:[f32] } i32:{ *:[i32] }:$src0, i32:{ *:[i32] }:$src1, i32:{ *:[i32] }:$src2_modifiers, f32:{ *:[f32] }:$src2)
        GIR_BuildMI, /*InsnID*/0, /*Opcode*/GIMT_Encode2(AMDGPU::V_DOT4_F32_BF8_FP8),
        GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/0, // DstI[vdst]
        GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/2, // src0
        GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/3, // src1
        GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/1, // src2_modifiers
        GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/0, // src2
        GIR_AddImm8, /*InsnID*/0, /*Imm*/0,
        GIR_AddImm8, /*InsnID*/0, /*Imm*/0,
        GIR_ConstrainSelectedInstOperands, /*InsnID*/0,
        GIR_EraseFromParent, /*InsnID*/0,
        // GIR_Coverage, 2272,
        GIR_Done,
      // Label 3163: @202941
      GIM_Try, /*On fail goto*//*Label 3164*/ GIMT_Encode4(203019), // Rule ID 2273 //
        GIM_CheckFeatures, GIMT_Encode2(GIFBS_isGFX12Plus),
        GIM_CheckIntrinsicID, /*MI*/0, /*Op*/1, GIMT_Encode2(Intrinsic::amdgcn_dot4_f32_fp8_fp8),
        GIM_CheckType, /*MI*/0, /*Op*/0, /*Type*/GILLT_s32,
        GIM_CheckType, /*MI*/0, /*Op*/2, /*Type*/GILLT_s32,
        GIM_CheckType, /*MI*/0, /*Op*/3, /*Type*/GILLT_s32,
        GIM_CheckType, /*MI*/0, /*Op*/4, /*Type*/GILLT_s32,
        GIM_CheckRegBankForClass, /*MI*/0, /*Op*/0, /*RC*/GIMT_Encode2(AMDGPU::VGPR_32RegClassID),
        GIM_CheckComplexPattern, /*MI*/0, /*Op*/4, /*Renderer*/GIMT_Encode2(0), GIMT_Encode2(GICP_gi_vop3mods),
        // (intrinsic_wo_chain:{ *:[f32] } 1930:{ *:[iPTR] }, i32:{ *:[i32] }:$src0, i32:{ *:[i32] }:$src1, (VOP3Mods:{ *:[f32] } f32:{ *:[f32] }:$src2, i32:{ *:[i32] }:$src2_modifiers))  =>  (V_DOT4_F32_FP8_FP8:{ *:[f32] } i32:{ *:[i32] }:$src0, i32:{ *:[i32] }:$src1, i32:{ *:[i32] }:$src2_modifiers, f32:{ *:[f32] }:$src2)
        GIR_BuildMI, /*InsnID*/0, /*Opcode*/GIMT_Encode2(AMDGPU::V_DOT4_F32_FP8_FP8),
        GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/0, // DstI[vdst]
        GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/2, // src0
        GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/3, // src1
        GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/1, // src2_modifiers
        GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/0, // src2
        GIR_AddImm8, /*InsnID*/0, /*Imm*/0,
        GIR_AddImm8, /*InsnID*/0, /*Imm*/0,
        GIR_ConstrainSelectedInstOperands, /*InsnID*/0,
        GIR_EraseFromParent, /*InsnID*/0,
        // GIR_Coverage, 2273,
        GIR_Done,
      // Label 3164: @203019
      GIM_Try, /*On fail goto*//*Label 3165*/ GIMT_Encode4(203097), // Rule ID 2274 //
        GIM_CheckFeatures, GIMT_Encode2(GIFBS_isGFX12Plus),
        GIM_CheckIntrinsicID, /*MI*/0, /*Op*/1, GIMT_Encode2(Intrinsic::amdgcn_dot4_f32_bf8_bf8),
        GIM_CheckType, /*MI*/0, /*Op*/0, /*Type*/GILLT_s32,
        GIM_CheckType, /*MI*/0, /*Op*/2, /*Type*/GILLT_s32,
        GIM_CheckType, /*MI*/0, /*Op*/3, /*Type*/GILLT_s32,
        GIM_CheckType, /*MI*/0, /*Op*/4, /*Type*/GILLT_s32,
        GIM_CheckRegBankForClass, /*MI*/0, /*Op*/0, /*RC*/GIMT_Encode2(AMDGPU::VGPR_32RegClassID),
        GIM_CheckComplexPattern, /*MI*/0, /*Op*/4, /*Renderer*/GIMT_Encode2(0), GIMT_Encode2(GICP_gi_vop3mods),
        // (intrinsic_wo_chain:{ *:[f32] } 1927:{ *:[iPTR] }, i32:{ *:[i32] }:$src0, i32:{ *:[i32] }:$src1, (VOP3Mods:{ *:[f32] } f32:{ *:[f32] }:$src2, i32:{ *:[i32] }:$src2_modifiers))  =>  (V_DOT4_F32_BF8_BF8:{ *:[f32] } i32:{ *:[i32] }:$src0, i32:{ *:[i32] }:$src1, i32:{ *:[i32] }:$src2_modifiers, f32:{ *:[f32] }:$src2)
        GIR_BuildMI, /*InsnID*/0, /*Opcode*/GIMT_Encode2(AMDGPU::V_DOT4_F32_BF8_BF8),
        GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/0, // DstI[vdst]
        GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/2, // src0
        GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/3, // src1
        GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/1, // src2_modifiers
        GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/0, // src2
        GIR_AddImm8, /*InsnID*/0, /*Imm*/0,
        GIR_AddImm8, /*InsnID*/0, /*Imm*/0,
        GIR_ConstrainSelectedInstOperands, /*InsnID*/0,
        GIR_EraseFromParent, /*InsnID*/0,
        // GIR_Coverage, 2274,
        GIR_Done,
      // Label 3165: @203097
      GIM_Try, /*On fail goto*//*Label 3166*/ GIMT_Encode4(203176), // Rule ID 5830 //
        GIM_CheckFeatures, GIMT_Encode2(GIFBS_isGFX11Only),
        GIM_CheckIntrinsicID, /*MI*/0, /*Op*/1, GIMT_Encode2(Intrinsic::amdgcn_lds_param_load),
        GIM_CheckType, /*MI*/0, /*Op*/0, /*Type*/GILLT_s32,
        GIM_CheckType, /*MI*/0, /*Op*/4, /*Type*/GILLT_s32,
        GIM_CheckRegBankForClass, /*MI*/0, /*Op*/0, /*RC*/GIMT_Encode2(AMDGPU::VGPR_32RegClassID),
        // MIs[0] attrchan
        GIM_CheckIsImm, /*MI*/0, /*Op*/2,
        // MIs[0] attr
        GIM_CheckIsImm, /*MI*/0, /*Op*/3,
        GIM_CheckRegBankForClass, /*MI*/0, /*Op*/4, /*RC*/GIMT_Encode2(AMDGPU::M0_CLASSRegClassID),
        // (intrinsic_wo_chain:{ *:[f32] } 2531:{ *:[iPTR] }, (timm:{ *:[i32] }):$attrchan, (timm:{ *:[i32] }):$attr, M0:{ *:[i32] })  =>  (LDS_PARAM_LOAD:{ *:[f32] } (timm:{ *:[i32] }):$attr, (timm:{ *:[i32] }):$attrchan, 0:{ *:[i8] })
        GIR_BuildMI, /*InsnID*/1, /*Opcode*/GIMT_Encode2(TargetOpcode::COPY),
        GIR_AddRegister, /*InsnID*/1, GIMT_Encode2(AMDGPU::M0), /*AddRegisterRegFlags*/GIMT_Encode2(RegState::Define),
        GIR_Copy, /*NewInsnID*/1, /*OldInsnID*/0, /*OpIdx*/4, // M0
        GIR_BuildMI, /*InsnID*/0, /*Opcode*/GIMT_Encode2(AMDGPU::LDS_PARAM_LOAD),
        GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/0, // DstI[vdst]
        GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/3, // attr
        GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/2, // attrchan
        GIR_AddImm8, /*InsnID*/0, /*Imm*/0,
        GIR_MergeMemOperands, /*InsnID*/0, /*NumInsns*/1, /*MergeInsnID's*/0,
        GIR_ConstrainSelectedInstOperands, /*InsnID*/0,
        GIR_EraseFromParent, /*InsnID*/0,
        // GIR_Coverage, 5830,
        GIR_Done,
      // Label 3166: @203176
      GIM_Try, /*On fail goto*//*Label 3167*/ GIMT_Encode4(203258), // Rule ID 5832 //
        GIM_CheckFeatures, GIMT_Encode2(GIFBS_isGFX12Plus),
        GIM_CheckIntrinsicID, /*MI*/0, /*Op*/1, GIMT_Encode2(Intrinsic::amdgcn_lds_param_load),
        GIM_CheckType, /*MI*/0, /*Op*/0, /*Type*/GILLT_s32,
        GIM_CheckType, /*MI*/0, /*Op*/4, /*Type*/GILLT_s32,
        GIM_CheckRegBankForClass, /*MI*/0, /*Op*/0, /*RC*/GIMT_Encode2(AMDGPU::VGPR_32RegClassID),
        // MIs[0] attrchan
        GIM_CheckIsImm, /*MI*/0, /*Op*/2,
        // MIs[0] attr
        GIM_CheckIsImm, /*MI*/0, /*Op*/3,
        GIM_CheckRegBankForClass, /*MI*/0, /*Op*/4, /*RC*/GIMT_Encode2(AMDGPU::M0_CLASSRegClassID),
        // (intrinsic_wo_chain:{ *:[f32] } 2531:{ *:[iPTR] }, (timm:{ *:[i32] }):$attrchan, (timm:{ *:[i32] }):$attr, M0:{ *:[i32] })  =>  (DS_PARAM_LOAD:{ *:[f32] } (timm:{ *:[i32] }):$attr, (timm:{ *:[i32] }):$attrchan, 0:{ *:[i8] }, 1:{ *:[i8] })
        GIR_BuildMI, /*InsnID*/1, /*Opcode*/GIMT_Encode2(TargetOpcode::COPY),
        GIR_AddRegister, /*InsnID*/1, GIMT_Encode2(AMDGPU::M0), /*AddRegisterRegFlags*/GIMT_Encode2(RegState::Define),
        GIR_Copy, /*NewInsnID*/1, /*OldInsnID*/0, /*OpIdx*/4, // M0
        GIR_BuildMI, /*InsnID*/0, /*Opcode*/GIMT_Encode2(AMDGPU::DS_PARAM_LOAD),
        GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/0, // DstI[vdst]
        GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/3, // attr
        GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/2, // attrchan
        GIR_AddImm8, /*InsnID*/0, /*Imm*/0,
        GIR_AddImm8, /*InsnID*/0, /*Imm*/1,
        GIR_MergeMemOperands, /*InsnID*/0, /*NumInsns*/1, /*MergeInsnID's*/0,
        GIR_ConstrainSelectedInstOperands, /*InsnID*/0,
        GIR_EraseFromParent, /*InsnID*/0,
        // GIR_Coverage, 5832,
        GIR_Done,
      // Label 3167: @203258
      GIM_Try, /*On fail goto*//*Label 3168*/ GIMT_Encode4(203317), // Rule ID 2238 //
        GIM_CheckIntrinsicID, /*MI*/0, /*Op*/1, GIMT_Encode2(Intrinsic::amdgcn_sad_u8),
        GIM_CheckType, /*MI*/0, /*Op*/0, /*Type*/GILLT_s32,
        GIM_CheckType, /*MI*/0, /*Op*/2, /*Type*/GILLT_s32,
        GIM_CheckType, /*MI*/0, /*Op*/3, /*Type*/GILLT_s32,
        GIM_CheckType, /*MI*/0, /*Op*/4, /*Type*/GILLT_s32,
        GIM_CheckRegBankForClass, /*MI*/0, /*Op*/0, /*RC*/GIMT_Encode2(AMDGPU::VGPR_32RegClassID),
        // (intrinsic_wo_chain:{ *:[i32] } 2703:{ *:[iPTR] }, i32:{ *:[i32] }:$src0, i32:{ *:[i32] }:$src1, i32:{ *:[i32] }:$src2)  =>  (V_SAD_U8_e64:{ *:[i32] } i32:{ *:[i32] }:$src0, i32:{ *:[i32] }:$src1, i32:{ *:[i32] }:$src2, 0:{ *:[i1] })
        GIR_BuildMI, /*InsnID*/0, /*Opcode*/GIMT_Encode2(AMDGPU::V_SAD_U8_e64),
        GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/0, // DstI[vdst]
        GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/2, // src0
        GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/3, // src1
        GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/4, // src2
        GIR_AddImm8, /*InsnID*/0, /*Imm*/0,
        GIR_ConstrainSelectedInstOperands, /*InsnID*/0,
        GIR_EraseFromParent, /*InsnID*/0,
        // GIR_Coverage, 2238,
        GIR_Done,
      // Label 3168: @203317
      GIM_Try, /*On fail goto*//*Label 3169*/ GIMT_Encode4(203376), // Rule ID 2239 //
        GIM_CheckIntrinsicID, /*MI*/0, /*Op*/1, GIMT_Encode2(Intrinsic::amdgcn_sad_hi_u8),
        GIM_CheckType, /*MI*/0, /*Op*/0, /*Type*/GILLT_s32,
        GIM_CheckType, /*MI*/0, /*Op*/2, /*Type*/GILLT_s32,
        GIM_CheckType, /*MI*/0, /*Op*/3, /*Type*/GILLT_s32,
        GIM_CheckType, /*MI*/0, /*Op*/4, /*Type*/GILLT_s32,
        GIM_CheckRegBankForClass, /*MI*/0, /*Op*/0, /*RC*/GIMT_Encode2(AMDGPU::VGPR_32RegClassID),
        // (intrinsic_wo_chain:{ *:[i32] } 2701:{ *:[iPTR] }, i32:{ *:[i32] }:$src0, i32:{ *:[i32] }:$src1, i32:{ *:[i32] }:$src2)  =>  (V_SAD_HI_U8_e64:{ *:[i32] } i32:{ *:[i32] }:$src0, i32:{ *:[i32] }:$src1, i32:{ *:[i32] }:$src2, 0:{ *:[i1] })
        GIR_BuildMI, /*InsnID*/0, /*Opcode*/GIMT_Encode2(AMDGPU::V_SAD_HI_U8_e64),
        GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/0, // DstI[vdst]
        GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/2, // src0
        GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/3, // src1
        GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/4, // src2
        GIR_AddImm8, /*InsnID*/0, /*Imm*/0,
        GIR_ConstrainSelectedInstOperands, /*InsnID*/0,
        GIR_EraseFromParent, /*InsnID*/0,
        // GIR_Coverage, 2239,
        GIR_Done,
      // Label 3169: @203376
      GIM_Try, /*On fail goto*//*Label 3170*/ GIMT_Encode4(203435), // Rule ID 2240 //
        GIM_CheckIntrinsicID, /*MI*/0, /*Op*/1, GIMT_Encode2(Intrinsic::amdgcn_sad_u16),
        GIM_CheckType, /*MI*/0, /*Op*/0, /*Type*/GILLT_s32,
        GIM_CheckType, /*MI*/0, /*Op*/2, /*Type*/GILLT_s32,
        GIM_CheckType, /*MI*/0, /*Op*/3, /*Type*/GILLT_s32,
        GIM_CheckType, /*MI*/0, /*Op*/4, /*Type*/GILLT_s32,
        GIM_CheckRegBankForClass, /*MI*/0, /*Op*/0, /*RC*/GIMT_Encode2(AMDGPU::VGPR_32RegClassID),
        // (intrinsic_wo_chain:{ *:[i32] } 2702:{ *:[iPTR] }, i32:{ *:[i32] }:$src0, i32:{ *:[i32] }:$src1, i32:{ *:[i32] }:$src2)  =>  (V_SAD_U16_e64:{ *:[i32] } i32:{ *:[i32] }:$src0, i32:{ *:[i32] }:$src1, i32:{ *:[i32] }:$src2, 0:{ *:[i1] })
        GIR_BuildMI, /*InsnID*/0, /*Opcode*/GIMT_Encode2(AMDGPU::V_SAD_U16_e64),
        GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/0, // DstI[vdst]
        GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/2, // src0
        GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/3, // src1
        GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/4, // src2
        GIR_AddImm8, /*InsnID*/0, /*Imm*/0,
        GIR_ConstrainSelectedInstOperands, /*InsnID*/0,
        GIR_EraseFromParent, /*InsnID*/0,
        // GIR_Coverage, 2240,
        GIR_Done,
      // Label 3170: @203435
      GIM_Try, /*On fail goto*//*Label 3171*/ GIMT_Encode4(203494), // Rule ID 2241 //
        GIM_CheckIntrinsicID, /*MI*/0, /*Op*/1, GIMT_Encode2(Intrinsic::amdgcn_msad_u8),
        GIM_CheckType, /*MI*/0, /*Op*/0, /*Type*/GILLT_s32,
        GIM_CheckType, /*MI*/0, /*Op*/2, /*Type*/GILLT_s32,
        GIM_CheckType, /*MI*/0, /*Op*/3, /*Type*/GILLT_s32,
        GIM_CheckType, /*MI*/0, /*Op*/4, /*Type*/GILLT_s32,
        GIM_CheckRegBankForClass, /*MI*/0, /*Op*/0, /*RC*/GIMT_Encode2(AMDGPU::VGPR_32RegClassID),
        // (intrinsic_wo_chain:{ *:[i32] } 2583:{ *:[iPTR] }, i32:{ *:[i32] }:$src0, i32:{ *:[i32] }:$src1, i32:{ *:[i32] }:$src2)  =>  (V_MSAD_U8_e64:{ *:[i32] } i32:{ *:[i32] }:$src0, i32:{ *:[i32] }:$src1, i32:{ *:[i32] }:$src2, 0:{ *:[i1] })
        GIR_BuildMI, /*InsnID*/0, /*Opcode*/GIMT_Encode2(AMDGPU::V_MSAD_U8_e64),
        GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/0, // DstI[vdst]
        GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/2, // src0
        GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/3, // src1
        GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/4, // src2
        GIR_AddImm8, /*InsnID*/0, /*Imm*/0,
        GIR_ConstrainSelectedInstOperands, /*InsnID*/0,
        GIR_EraseFromParent, /*InsnID*/0,
        // GIR_Coverage, 2241,
        GIR_Done,
      // Label 3171: @203494
      GIM_Try, /*On fail goto*//*Label 3172*/ GIMT_Encode4(203553), // Rule ID 2242 //
        GIM_CheckIntrinsicID, /*MI*/0, /*Op*/1, GIMT_Encode2(Intrinsic::amdgcn_mqsad_pk_u16_u8),
        GIM_CheckType, /*MI*/0, /*Op*/0, /*Type*/GILLT_s64,
        GIM_CheckType, /*MI*/0, /*Op*/2, /*Type*/GILLT_s64,
        GIM_CheckType, /*MI*/0, /*Op*/3, /*Type*/GILLT_s32,
        GIM_CheckType, /*MI*/0, /*Op*/4, /*Type*/GILLT_s64,
        GIM_CheckRegBankForClass, /*MI*/0, /*Op*/0, /*RC*/GIMT_Encode2(AMDGPU::VReg_64RegClassID),
        // (intrinsic_wo_chain:{ *:[i64] } 2581:{ *:[iPTR] }, i64:{ *:[i64] }:$src0, i32:{ *:[i32] }:$src1, i64:{ *:[i64] }:$src2)  =>  (V_MQSAD_PK_U16_U8_e64:{ *:[i64] } i64:{ *:[i64] }:$src0, i32:{ *:[i32] }:$src1, i64:{ *:[i64] }:$src2, 0:{ *:[i1] })
        GIR_BuildMI, /*InsnID*/0, /*Opcode*/GIMT_Encode2(AMDGPU::V_MQSAD_PK_U16_U8_e64),
        GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/0, // DstI[vdst]
        GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/2, // src0
        GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/3, // src1
        GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/4, // src2
        GIR_AddImm8, /*InsnID*/0, /*Imm*/0,
        GIR_ConstrainSelectedInstOperands, /*InsnID*/0,
        GIR_EraseFromParent, /*InsnID*/0,
        // GIR_Coverage, 2242,
        GIR_Done,
      // Label 3172: @203553
      GIM_Try, /*On fail goto*//*Label 3173*/ GIMT_Encode4(203612), // Rule ID 2243 //
        GIM_CheckIntrinsicID, /*MI*/0, /*Op*/1, GIMT_Encode2(Intrinsic::amdgcn_qsad_pk_u16_u8),
        GIM_CheckType, /*MI*/0, /*Op*/0, /*Type*/GILLT_s64,
        GIM_CheckType, /*MI*/0, /*Op*/2, /*Type*/GILLT_s64,
        GIM_CheckType, /*MI*/0, /*Op*/3, /*Type*/GILLT_s32,
        GIM_CheckType, /*MI*/0, /*Op*/4, /*Type*/GILLT_s64,
        GIM_CheckRegBankForClass, /*MI*/0, /*Op*/0, /*RC*/GIMT_Encode2(AMDGPU::VReg_64RegClassID),
        // (intrinsic_wo_chain:{ *:[i64] } 2595:{ *:[iPTR] }, i64:{ *:[i64] }:$src0, i32:{ *:[i32] }:$src1, i64:{ *:[i64] }:$src2)  =>  (V_QSAD_PK_U16_U8_e64:{ *:[i64] } i64:{ *:[i64] }:$src0, i32:{ *:[i32] }:$src1, i64:{ *:[i64] }:$src2, 0:{ *:[i1] })
        GIR_BuildMI, /*InsnID*/0, /*Opcode*/GIMT_Encode2(AMDGPU::V_QSAD_PK_U16_U8_e64),
        GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/0, // DstI[vdst]
        GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/2, // src0
        GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/3, // src1
        GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/4, // src2
        GIR_AddImm8, /*InsnID*/0, /*Imm*/0,
        GIR_ConstrainSelectedInstOperands, /*InsnID*/0,
        GIR_EraseFromParent, /*InsnID*/0,
        // GIR_Coverage, 2243,
        GIR_Done,
      // Label 3173: @203612
      GIM_Try, /*On fail goto*//*Label 3174*/ GIMT_Encode4(203671), // Rule ID 2244 //
        GIM_CheckIntrinsicID, /*MI*/0, /*Op*/1, GIMT_Encode2(Intrinsic::amdgcn_mqsad_u32_u8),
        GIM_CheckType, /*MI*/0, /*Op*/0, /*Type*/GILLT_v4s32,
        GIM_CheckType, /*MI*/0, /*Op*/2, /*Type*/GILLT_s64,
        GIM_CheckType, /*MI*/0, /*Op*/3, /*Type*/GILLT_s32,
        GIM_CheckType, /*MI*/0, /*Op*/4, /*Type*/GILLT_v4s32,
        GIM_CheckRegBankForClass, /*MI*/0, /*Op*/0, /*RC*/GIMT_Encode2(AMDGPU::VReg_128RegClassID),
        // (intrinsic_wo_chain:{ *:[v4i32] } 2582:{ *:[iPTR] }, i64:{ *:[i64] }:$src0, i32:{ *:[i32] }:$src1, v4i32:{ *:[v4i32] }:$src2)  =>  (V_MQSAD_U32_U8_e64:{ *:[v4i32] } i64:{ *:[i64] }:$src0, i32:{ *:[i32] }:$src1, v4i32:{ *:[v4i32] }:$src2, 0:{ *:[i1] })
        GIR_BuildMI, /*InsnID*/0, /*Opcode*/GIMT_Encode2(AMDGPU::V_MQSAD_U32_U8_e64),
        GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/0, // DstI[vdst]
        GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/2, // src0
        GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/3, // src1
        GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/4, // src2
        GIR_AddImm8, /*InsnID*/0, /*Imm*/0,
        GIR_ConstrainSelectedInstOperands, /*InsnID*/0,
        GIR_EraseFromParent, /*InsnID*/0,
        // GIR_Coverage, 2244,
        GIR_Done,
      // Label 3174: @203671
      GIM_Try, /*On fail goto*//*Label 3175*/ GIMT_Encode4(203779), // Rule ID 849 //
        GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasMadMacF32Insts),
        GIM_CheckIntrinsicID, /*MI*/0, /*Op*/1, GIMT_Encode2(Intrinsic::amdgcn_fmad_ftz),
        GIM_CheckType, /*MI*/0, /*Op*/0, /*Type*/GILLT_s32,
        GIM_CheckType, /*MI*/0, /*Op*/2, /*Type*/GILLT_s32,
        GIM_CheckType, /*MI*/0, /*Op*/3, /*Type*/GILLT_s32,
        GIM_CheckType, /*MI*/0, /*Op*/4, /*Type*/GILLT_s32,
        GIM_CheckRegBankForClass, /*MI*/0, /*Op*/0, /*RC*/GIMT_Encode2(AMDGPU::VGPR_32RegClassID),
        GIM_CheckComplexPattern, /*MI*/0, /*Op*/2, /*Renderer*/GIMT_Encode2(0), GIMT_Encode2(GICP_gi_vop3mods0),
        GIM_CheckComplexPattern, /*MI*/0, /*Op*/3, /*Renderer*/GIMT_Encode2(1), GIMT_Encode2(GICP_gi_vop3mods),
        GIM_CheckComplexPattern, /*MI*/0, /*Op*/4, /*Renderer*/GIMT_Encode2(2), GIMT_Encode2(GICP_gi_vop3mods),
        // (intrinsic_wo_chain:{ *:[f32] } 1971:{ *:[iPTR] }, (VOP3Mods0:{ *:[f32] } f32:{ *:[f32] }:$src0, i32:{ *:[i32] }:$src0_modifiers, i1:{ *:[i1] }:$clamp, i32:{ *:[i32] }:$omod), (VOP3Mods:{ *:[f32] } f32:{ *:[f32] }:$src1, i32:{ *:[i32] }:$src1_modifiers), (VOP3Mods:{ *:[f32] } f32:{ *:[f32] }:$src2, i32:{ *:[i32] }:$src2_modifiers))  =>  (V_MAD_F32_e64:{ *:[f32] } i32:{ *:[i32] }:$src0_modifiers, f32:{ *:[f32] }:$src0, i32:{ *:[i32] }:$src1_modifiers, f32:{ *:[f32] }:$src1, i32:{ *:[i32] }:$src2_modifiers, f32:{ *:[f32] }:$src2, i1:{ *:[i1] }:$clamp, i32:{ *:[i32] }:$omod)
        GIR_BuildMI, /*InsnID*/0, /*Opcode*/GIMT_Encode2(AMDGPU::V_MAD_F32_e64),
        GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/0, // DstI[vdst]
        GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/1, // src0_modifiers
        GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/0, // src0
        GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(1), /*SubOperand*/1, // src1_modifiers
        GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(1), /*SubOperand*/0, // src1
        GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(2), /*SubOperand*/1, // src2_modifiers
        GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(2), /*SubOperand*/0, // src2
        GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/2, // clamp
        GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/3, // omod
        GIR_ConstrainSelectedInstOperands, /*InsnID*/0,
        GIR_EraseFromParent, /*InsnID*/0,
        // GIR_Coverage, 849,
        GIR_Done,
      // Label 3175: @203779
      GIM_Try, /*On fail goto*//*Label 3176*/ GIMT_Encode4(203887), // Rule ID 851 //
        GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasFmaLegacy32),
        GIM_CheckIntrinsicID, /*MI*/0, /*Op*/1, GIMT_Encode2(Intrinsic::amdgcn_fma_legacy),
        GIM_CheckType, /*MI*/0, /*Op*/0, /*Type*/GILLT_s32,
        GIM_CheckType, /*MI*/0, /*Op*/2, /*Type*/GILLT_s32,
        GIM_CheckType, /*MI*/0, /*Op*/3, /*Type*/GILLT_s32,
        GIM_CheckType, /*MI*/0, /*Op*/4, /*Type*/GILLT_s32,
        GIM_CheckRegBankForClass, /*MI*/0, /*Op*/0, /*RC*/GIMT_Encode2(AMDGPU::VGPR_32RegClassID),
        GIM_CheckComplexPattern, /*MI*/0, /*Op*/2, /*Renderer*/GIMT_Encode2(0), GIMT_Encode2(GICP_gi_vop3mods0),
        GIM_CheckComplexPattern, /*MI*/0, /*Op*/3, /*Renderer*/GIMT_Encode2(1), GIMT_Encode2(GICP_gi_vop3mods),
        GIM_CheckComplexPattern, /*MI*/0, /*Op*/4, /*Renderer*/GIMT_Encode2(2), GIMT_Encode2(GICP_gi_vop3mods),
        // (intrinsic_wo_chain:{ *:[f32] } 1970:{ *:[iPTR] }, (VOP3Mods0:{ *:[f32] } f32:{ *:[f32] }:$src0, i32:{ *:[i32] }:$src0_modifiers, i1:{ *:[i1] }:$clamp, i32:{ *:[i32] }:$omod), (VOP3Mods:{ *:[f32] } f32:{ *:[f32] }:$src1, i32:{ *:[i32] }:$src1_modifiers), (VOP3Mods:{ *:[f32] } f32:{ *:[f32] }:$src2, i32:{ *:[i32] }:$src2_modifiers))  =>  (V_FMA_LEGACY_F32_e64:{ *:[f32] } i32:{ *:[i32] }:$src0_modifiers, f32:{ *:[f32] }:$src0, i32:{ *:[i32] }:$src1_modifiers, f32:{ *:[f32] }:$src1, i32:{ *:[i32] }:$src2_modifiers, f32:{ *:[f32] }:$src2, i1:{ *:[i1] }:$clamp, i32:{ *:[i32] }:$omod)
        GIR_BuildMI, /*InsnID*/0, /*Opcode*/GIMT_Encode2(AMDGPU::V_FMA_LEGACY_F32_e64),
        GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/0, // DstI[vdst]
        GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/1, // src0_modifiers
        GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/0, // src0
        GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(1), /*SubOperand*/1, // src1_modifiers
        GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(1), /*SubOperand*/0, // src1
        GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(2), /*SubOperand*/1, // src2_modifiers
        GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(2), /*SubOperand*/0, // src2
        GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/2, // clamp
        GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/3, // omod
        GIR_ConstrainSelectedInstOperands, /*InsnID*/0,
        GIR_EraseFromParent, /*InsnID*/0,
        // GIR_Coverage, 851,
        GIR_Done,
      // Label 3176: @203887
      GIM_Try, /*On fail goto*//*Label 3177*/ GIMT_Encode4(203992), // Rule ID 874 //
        GIM_CheckIntrinsicID, /*MI*/0, /*Op*/1, GIMT_Encode2(Intrinsic::amdgcn_cubeid),
        GIM_CheckType, /*MI*/0, /*Op*/0, /*Type*/GILLT_s32,
        GIM_CheckType, /*MI*/0, /*Op*/2, /*Type*/GILLT_s32,
        GIM_CheckType, /*MI*/0, /*Op*/3, /*Type*/GILLT_s32,
        GIM_CheckType, /*MI*/0, /*Op*/4, /*Type*/GILLT_s32,
        GIM_CheckRegBankForClass, /*MI*/0, /*Op*/0, /*RC*/GIMT_Encode2(AMDGPU::VGPR_32RegClassID),
        GIM_CheckComplexPattern, /*MI*/0, /*Op*/2, /*Renderer*/GIMT_Encode2(0), GIMT_Encode2(GICP_gi_vop3mods0),
        GIM_CheckComplexPattern, /*MI*/0, /*Op*/3, /*Renderer*/GIMT_Encode2(1), GIMT_Encode2(GICP_gi_vop3mods),
        GIM_CheckComplexPattern, /*MI*/0, /*Op*/4, /*Renderer*/GIMT_Encode2(2), GIMT_Encode2(GICP_gi_vop3mods),
        // (intrinsic_wo_chain:{ *:[f32] } 1904:{ *:[iPTR] }, (VOP3Mods0:{ *:[f32] } f32:{ *:[f32] }:$src0, i32:{ *:[i32] }:$src0_modifiers, i1:{ *:[i1] }:$clamp, i32:{ *:[i32] }:$omod), (VOP3Mods:{ *:[f32] } f32:{ *:[f32] }:$src1, i32:{ *:[i32] }:$src1_modifiers), (VOP3Mods:{ *:[f32] } f32:{ *:[f32] }:$src2, i32:{ *:[i32] }:$src2_modifiers))  =>  (V_CUBEID_F32_e64:{ *:[f32] } i32:{ *:[i32] }:$src0_modifiers, f32:{ *:[f32] }:$src0, i32:{ *:[i32] }:$src1_modifiers, f32:{ *:[f32] }:$src1, i32:{ *:[i32] }:$src2_modifiers, f32:{ *:[f32] }:$src2, i1:{ *:[i1] }:$clamp, i32:{ *:[i32] }:$omod)
        GIR_BuildMI, /*InsnID*/0, /*Opcode*/GIMT_Encode2(AMDGPU::V_CUBEID_F32_e64),
        GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/0, // DstI[vdst]
        GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/1, // src0_modifiers
        GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/0, // src0
        GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(1), /*SubOperand*/1, // src1_modifiers
        GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(1), /*SubOperand*/0, // src1
        GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(2), /*SubOperand*/1, // src2_modifiers
        GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(2), /*SubOperand*/0, // src2
        GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/2, // clamp
        GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/3, // omod
        GIR_ConstrainSelectedInstOperands, /*InsnID*/0,
        GIR_EraseFromParent, /*InsnID*/0,
        // GIR_Coverage, 874,
        GIR_Done,
      // Label 3177: @203992
      GIM_Try, /*On fail goto*//*Label 3178*/ GIMT_Encode4(204097), // Rule ID 875 //
        GIM_CheckIntrinsicID, /*MI*/0, /*Op*/1, GIMT_Encode2(Intrinsic::amdgcn_cubesc),
        GIM_CheckType, /*MI*/0, /*Op*/0, /*Type*/GILLT_s32,
        GIM_CheckType, /*MI*/0, /*Op*/2, /*Type*/GILLT_s32,
        GIM_CheckType, /*MI*/0, /*Op*/3, /*Type*/GILLT_s32,
        GIM_CheckType, /*MI*/0, /*Op*/4, /*Type*/GILLT_s32,
        GIM_CheckRegBankForClass, /*MI*/0, /*Op*/0, /*RC*/GIMT_Encode2(AMDGPU::VGPR_32RegClassID),
        GIM_CheckComplexPattern, /*MI*/0, /*Op*/2, /*Renderer*/GIMT_Encode2(0), GIMT_Encode2(GICP_gi_vop3mods0),
        GIM_CheckComplexPattern, /*MI*/0, /*Op*/3, /*Renderer*/GIMT_Encode2(1), GIMT_Encode2(GICP_gi_vop3mods),
        GIM_CheckComplexPattern, /*MI*/0, /*Op*/4, /*Renderer*/GIMT_Encode2(2), GIMT_Encode2(GICP_gi_vop3mods),
        // (intrinsic_wo_chain:{ *:[f32] } 1906:{ *:[iPTR] }, (VOP3Mods0:{ *:[f32] } f32:{ *:[f32] }:$src0, i32:{ *:[i32] }:$src0_modifiers, i1:{ *:[i1] }:$clamp, i32:{ *:[i32] }:$omod), (VOP3Mods:{ *:[f32] } f32:{ *:[f32] }:$src1, i32:{ *:[i32] }:$src1_modifiers), (VOP3Mods:{ *:[f32] } f32:{ *:[f32] }:$src2, i32:{ *:[i32] }:$src2_modifiers))  =>  (V_CUBESC_F32_e64:{ *:[f32] } i32:{ *:[i32] }:$src0_modifiers, f32:{ *:[f32] }:$src0, i32:{ *:[i32] }:$src1_modifiers, f32:{ *:[f32] }:$src1, i32:{ *:[i32] }:$src2_modifiers, f32:{ *:[f32] }:$src2, i1:{ *:[i1] }:$clamp, i32:{ *:[i32] }:$omod)
        GIR_BuildMI, /*InsnID*/0, /*Opcode*/GIMT_Encode2(AMDGPU::V_CUBESC_F32_e64),
        GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/0, // DstI[vdst]
        GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/1, // src0_modifiers
        GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/0, // src0
        GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(1), /*SubOperand*/1, // src1_modifiers
        GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(1), /*SubOperand*/0, // src1
        GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(2), /*SubOperand*/1, // src2_modifiers
        GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(2), /*SubOperand*/0, // src2
        GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/2, // clamp
        GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/3, // omod
        GIR_ConstrainSelectedInstOperands, /*InsnID*/0,
        GIR_EraseFromParent, /*InsnID*/0,
        // GIR_Coverage, 875,
        GIR_Done,
      // Label 3178: @204097
      GIM_Try, /*On fail goto*//*Label 3179*/ GIMT_Encode4(204202), // Rule ID 876 //
        GIM_CheckIntrinsicID, /*MI*/0, /*Op*/1, GIMT_Encode2(Intrinsic::amdgcn_cubetc),
        GIM_CheckType, /*MI*/0, /*Op*/0, /*Type*/GILLT_s32,
        GIM_CheckType, /*MI*/0, /*Op*/2, /*Type*/GILLT_s32,
        GIM_CheckType, /*MI*/0, /*Op*/3, /*Type*/GILLT_s32,
        GIM_CheckType, /*MI*/0, /*Op*/4, /*Type*/GILLT_s32,
        GIM_CheckRegBankForClass, /*MI*/0, /*Op*/0, /*RC*/GIMT_Encode2(AMDGPU::VGPR_32RegClassID),
        GIM_CheckComplexPattern, /*MI*/0, /*Op*/2, /*Renderer*/GIMT_Encode2(0), GIMT_Encode2(GICP_gi_vop3mods0),
        GIM_CheckComplexPattern, /*MI*/0, /*Op*/3, /*Renderer*/GIMT_Encode2(1), GIMT_Encode2(GICP_gi_vop3mods),
        GIM_CheckComplexPattern, /*MI*/0, /*Op*/4, /*Renderer*/GIMT_Encode2(2), GIMT_Encode2(GICP_gi_vop3mods),
        // (intrinsic_wo_chain:{ *:[f32] } 1907:{ *:[iPTR] }, (VOP3Mods0:{ *:[f32] } f32:{ *:[f32] }:$src0, i32:{ *:[i32] }:$src0_modifiers, i1:{ *:[i1] }:$clamp, i32:{ *:[i32] }:$omod), (VOP3Mods:{ *:[f32] } f32:{ *:[f32] }:$src1, i32:{ *:[i32] }:$src1_modifiers), (VOP3Mods:{ *:[f32] } f32:{ *:[f32] }:$src2, i32:{ *:[i32] }:$src2_modifiers))  =>  (V_CUBETC_F32_e64:{ *:[f32] } i32:{ *:[i32] }:$src0_modifiers, f32:{ *:[f32] }:$src0, i32:{ *:[i32] }:$src1_modifiers, f32:{ *:[f32] }:$src1, i32:{ *:[i32] }:$src2_modifiers, f32:{ *:[f32] }:$src2, i1:{ *:[i1] }:$clamp, i32:{ *:[i32] }:$omod)
        GIR_BuildMI, /*InsnID*/0, /*Opcode*/GIMT_Encode2(AMDGPU::V_CUBETC_F32_e64),
        GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/0, // DstI[vdst]
        GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/1, // src0_modifiers
        GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/0, // src0
        GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(1), /*SubOperand*/1, // src1_modifiers
        GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(1), /*SubOperand*/0, // src1
        GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(2), /*SubOperand*/1, // src2_modifiers
        GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(2), /*SubOperand*/0, // src2
        GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/2, // clamp
        GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/3, // omod
        GIR_ConstrainSelectedInstOperands, /*InsnID*/0,
        GIR_EraseFromParent, /*InsnID*/0,
        // GIR_Coverage, 876,
        GIR_Done,
      // Label 3179: @204202
      GIM_Try, /*On fail goto*//*Label 3180*/ GIMT_Encode4(204307), // Rule ID 877 //
        GIM_CheckIntrinsicID, /*MI*/0, /*Op*/1, GIMT_Encode2(Intrinsic::amdgcn_cubema),
        GIM_CheckType, /*MI*/0, /*Op*/0, /*Type*/GILLT_s32,
        GIM_CheckType, /*MI*/0, /*Op*/2, /*Type*/GILLT_s32,
        GIM_CheckType, /*MI*/0, /*Op*/3, /*Type*/GILLT_s32,
        GIM_CheckType, /*MI*/0, /*Op*/4, /*Type*/GILLT_s32,
        GIM_CheckRegBankForClass, /*MI*/0, /*Op*/0, /*RC*/GIMT_Encode2(AMDGPU::VGPR_32RegClassID),
        GIM_CheckComplexPattern, /*MI*/0, /*Op*/2, /*Renderer*/GIMT_Encode2(0), GIMT_Encode2(GICP_gi_vop3mods0),
        GIM_CheckComplexPattern, /*MI*/0, /*Op*/3, /*Renderer*/GIMT_Encode2(1), GIMT_Encode2(GICP_gi_vop3mods),
        GIM_CheckComplexPattern, /*MI*/0, /*Op*/4, /*Renderer*/GIMT_Encode2(2), GIMT_Encode2(GICP_gi_vop3mods),
        // (intrinsic_wo_chain:{ *:[f32] } 1905:{ *:[iPTR] }, (VOP3Mods0:{ *:[f32] } f32:{ *:[f32] }:$src0, i32:{ *:[i32] }:$src0_modifiers, i1:{ *:[i1] }:$clamp, i32:{ *:[i32] }:$omod), (VOP3Mods:{ *:[f32] } f32:{ *:[f32] }:$src1, i32:{ *:[i32] }:$src1_modifiers), (VOP3Mods:{ *:[f32] } f32:{ *:[f32] }:$src2, i32:{ *:[i32] }:$src2_modifiers))  =>  (V_CUBEMA_F32_e64:{ *:[f32] } i32:{ *:[i32] }:$src0_modifiers, f32:{ *:[f32] }:$src0, i32:{ *:[i32] }:$src1_modifiers, f32:{ *:[f32] }:$src1, i32:{ *:[i32] }:$src2_modifiers, f32:{ *:[f32] }:$src2, i1:{ *:[i1] }:$clamp, i32:{ *:[i32] }:$omod)
        GIR_BuildMI, /*InsnID*/0, /*Opcode*/GIMT_Encode2(AMDGPU::V_CUBEMA_F32_e64),
        GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/0, // DstI[vdst]
        GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/1, // src0_modifiers
        GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/0, // src0
        GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(1), /*SubOperand*/1, // src1_modifiers
        GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(1), /*SubOperand*/0, // src1
        GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(2), /*SubOperand*/1, // src2_modifiers
        GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(2), /*SubOperand*/0, // src2
        GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/2, // clamp
        GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/3, // omod
        GIR_ConstrainSelectedInstOperands, /*InsnID*/0,
        GIR_EraseFromParent, /*InsnID*/0,
        // GIR_Coverage, 877,
        GIR_Done,
      // Label 3180: @204307
      GIM_Try, /*On fail goto*//*Label 3181*/ GIMT_Encode4(204412), // Rule ID 893 //
        GIM_CheckIntrinsicID, /*MI*/0, /*Op*/1, GIMT_Encode2(Intrinsic::amdgcn_fmed3),
        GIM_CheckType, /*MI*/0, /*Op*/0, /*Type*/GILLT_s32,
        GIM_CheckType, /*MI*/0, /*Op*/2, /*Type*/GILLT_s32,
        GIM_CheckType, /*MI*/0, /*Op*/3, /*Type*/GILLT_s32,
        GIM_CheckType, /*MI*/0, /*Op*/4, /*Type*/GILLT_s32,
        GIM_CheckRegBankForClass, /*MI*/0, /*Op*/0, /*RC*/GIMT_Encode2(AMDGPU::VGPR_32RegClassID),
        GIM_CheckComplexPattern, /*MI*/0, /*Op*/2, /*Renderer*/GIMT_Encode2(0), GIMT_Encode2(GICP_gi_vop3mods0),
        GIM_CheckComplexPattern, /*MI*/0, /*Op*/3, /*Renderer*/GIMT_Encode2(1), GIMT_Encode2(GICP_gi_vop3mods),
        GIM_CheckComplexPattern, /*MI*/0, /*Op*/4, /*Renderer*/GIMT_Encode2(2), GIMT_Encode2(GICP_gi_vop3mods),
        // (intrinsic_wo_chain:{ *:[f32] } 1972:{ *:[iPTR] }, (VOP3Mods0:{ *:[f32] } f32:{ *:[f32] }:$src0, i32:{ *:[i32] }:$src0_modifiers, i1:{ *:[i1] }:$clamp, i32:{ *:[i32] }:$omod), (VOP3Mods:{ *:[f32] } f32:{ *:[f32] }:$src1, i32:{ *:[i32] }:$src1_modifiers), (VOP3Mods:{ *:[f32] } f32:{ *:[f32] }:$src2, i32:{ *:[i32] }:$src2_modifiers))  =>  (V_MED3_F32_e64:{ *:[f32] } i32:{ *:[i32] }:$src0_modifiers, f32:{ *:[f32] }:$src0, i32:{ *:[i32] }:$src1_modifiers, f32:{ *:[f32] }:$src1, i32:{ *:[i32] }:$src2_modifiers, f32:{ *:[f32] }:$src2, i1:{ *:[i1] }:$clamp, i32:{ *:[i32] }:$omod)
        GIR_BuildMI, /*InsnID*/0, /*Opcode*/GIMT_Encode2(AMDGPU::V_MED3_F32_e64),
        GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/0, // DstI[vdst]
        GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/1, // src0_modifiers
        GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/0, // src0
        GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(1), /*SubOperand*/1, // src1_modifiers
        GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(1), /*SubOperand*/0, // src1
        GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(2), /*SubOperand*/1, // src2_modifiers
        GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(2), /*SubOperand*/0, // src2
        GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/2, // clamp
        GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/3, // omod
        GIR_ConstrainSelectedInstOperands, /*InsnID*/0,
        GIR_EraseFromParent, /*InsnID*/0,
        // GIR_Coverage, 893,
        GIR_Done,
      // Label 3181: @204412
      GIM_Try, /*On fail goto*//*Label 3182*/ GIMT_Encode4(204512), // Rule ID 897 //
        GIM_CheckIntrinsicID, /*MI*/0, /*Op*/1, GIMT_Encode2(Intrinsic::amdgcn_cvt_pk_u8_f32),
        GIM_CheckType, /*MI*/0, /*Op*/0, /*Type*/GILLT_s32,
        GIM_CheckType, /*MI*/0, /*Op*/2, /*Type*/GILLT_s32,
        GIM_CheckType, /*MI*/0, /*Op*/3, /*Type*/GILLT_s32,
        GIM_CheckType, /*MI*/0, /*Op*/4, /*Type*/GILLT_s32,
        GIM_CheckRegBankForClass, /*MI*/0, /*Op*/0, /*RC*/GIMT_Encode2(AMDGPU::VGPR_32RegClassID),
        GIM_CheckComplexPattern, /*MI*/0, /*Op*/2, /*Renderer*/GIMT_Encode2(0), GIMT_Encode2(GICP_gi_vop3mods0),
        GIM_CheckComplexPattern, /*MI*/0, /*Op*/3, /*Renderer*/GIMT_Encode2(1), GIMT_Encode2(GICP_gi_vop3mods),
        GIM_CheckComplexPattern, /*MI*/0, /*Op*/4, /*Renderer*/GIMT_Encode2(2), GIMT_Encode2(GICP_gi_vop3mods),
        // (intrinsic_wo_chain:{ *:[i32] } 1916:{ *:[iPTR] }, (VOP3Mods0:{ *:[f32] } f32:{ *:[f32] }:$src0, i32:{ *:[i32] }:$src0_modifiers, i1:{ *:[i1] }:$clamp), (VOP3Mods:{ *:[i32] } i32:{ *:[i32] }:$src1, i32:{ *:[i32] }:$src1_modifiers), (VOP3Mods:{ *:[i32] } i32:{ *:[i32] }:$src2, i32:{ *:[i32] }:$src2_modifiers))  =>  (V_CVT_PK_U8_F32_e64:{ *:[i32] } i32:{ *:[i32] }:$src0_modifiers, f32:{ *:[f32] }:$src0, i32:{ *:[i32] }:$src1_modifiers, i32:{ *:[i32] }:$src1, i32:{ *:[i32] }:$src2_modifiers, i32:{ *:[i32] }:$src2, i1:{ *:[i1] }:$clamp)
        GIR_BuildMI, /*InsnID*/0, /*Opcode*/GIMT_Encode2(AMDGPU::V_CVT_PK_U8_F32_e64),
        GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/0, // DstI[vdst]
        GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/1, // src0_modifiers
        GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/0, // src0
        GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(1), /*SubOperand*/1, // src1_modifiers
        GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(1), /*SubOperand*/0, // src1
        GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(2), /*SubOperand*/1, // src2_modifiers
        GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(2), /*SubOperand*/0, // src2
        GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/2, // clamp
        GIR_ConstrainSelectedInstOperands, /*InsnID*/0,
        GIR_EraseFromParent, /*InsnID*/0,
        // GIR_Coverage, 897,
        GIR_Done,
      // Label 3182: @204512
      GIM_Try, /*On fail goto*//*Label 3183*/ GIMT_Encode4(204617), // Rule ID 898 //
        GIM_CheckIntrinsicID, /*MI*/0, /*Op*/1, GIMT_Encode2(Intrinsic::amdgcn_div_fixup),
        GIM_CheckType, /*MI*/0, /*Op*/0, /*Type*/GILLT_s32,
        GIM_CheckType, /*MI*/0, /*Op*/2, /*Type*/GILLT_s32,
        GIM_CheckType, /*MI*/0, /*Op*/3, /*Type*/GILLT_s32,
        GIM_CheckType, /*MI*/0, /*Op*/4, /*Type*/GILLT_s32,
        GIM_CheckRegBankForClass, /*MI*/0, /*Op*/0, /*RC*/GIMT_Encode2(AMDGPU::VGPR_32RegClassID),
        GIM_CheckComplexPattern, /*MI*/0, /*Op*/2, /*Renderer*/GIMT_Encode2(0), GIMT_Encode2(GICP_gi_vop3mods0),
        GIM_CheckComplexPattern, /*MI*/0, /*Op*/3, /*Renderer*/GIMT_Encode2(1), GIMT_Encode2(GICP_gi_vop3mods),
        GIM_CheckComplexPattern, /*MI*/0, /*Op*/4, /*Renderer*/GIMT_Encode2(2), GIMT_Encode2(GICP_gi_vop3mods),
        // (intrinsic_wo_chain:{ *:[f32] } 1924:{ *:[iPTR] }, (VOP3Mods0:{ *:[f32] } f32:{ *:[f32] }:$src0, i32:{ *:[i32] }:$src0_modifiers, i1:{ *:[i1] }:$clamp, i32:{ *:[i32] }:$omod), (VOP3Mods:{ *:[f32] } f32:{ *:[f32] }:$src1, i32:{ *:[i32] }:$src1_modifiers), (VOP3Mods:{ *:[f32] } f32:{ *:[f32] }:$src2, i32:{ *:[i32] }:$src2_modifiers))  =>  (V_DIV_FIXUP_F32_e64:{ *:[f32] } i32:{ *:[i32] }:$src0_modifiers, f32:{ *:[f32] }:$src0, i32:{ *:[i32] }:$src1_modifiers, f32:{ *:[f32] }:$src1, i32:{ *:[i32] }:$src2_modifiers, f32:{ *:[f32] }:$src2, i1:{ *:[i1] }:$clamp, i32:{ *:[i32] }:$omod)
        GIR_BuildMI, /*InsnID*/0, /*Opcode*/GIMT_Encode2(AMDGPU::V_DIV_FIXUP_F32_e64),
        GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/0, // DstI[vdst]
        GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/1, // src0_modifiers
        GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/0, // src0
        GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(1), /*SubOperand*/1, // src1_modifiers
        GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(1), /*SubOperand*/0, // src1
        GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(2), /*SubOperand*/1, // src2_modifiers
        GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(2), /*SubOperand*/0, // src2
        GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/2, // clamp
        GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/3, // omod
        GIR_ConstrainSelectedInstOperands, /*InsnID*/0,
        GIR_EraseFromParent, /*InsnID*/0,
        // GIR_Coverage, 898,
        GIR_Done,
      // Label 3183: @204617
      GIM_Try, /*On fail goto*//*Label 3184*/ GIMT_Encode4(204722), // Rule ID 900 //
        GIM_CheckIntrinsicID, /*MI*/0, /*Op*/1, GIMT_Encode2(Intrinsic::amdgcn_div_fixup),
        GIM_CheckType, /*MI*/0, /*Op*/0, /*Type*/GILLT_s64,
        GIM_CheckType, /*MI*/0, /*Op*/2, /*Type*/GILLT_s64,
        GIM_CheckType, /*MI*/0, /*Op*/3, /*Type*/GILLT_s64,
        GIM_CheckType, /*MI*/0, /*Op*/4, /*Type*/GILLT_s64,
        GIM_CheckRegBankForClass, /*MI*/0, /*Op*/0, /*RC*/GIMT_Encode2(AMDGPU::VReg_64RegClassID),
        GIM_CheckComplexPattern, /*MI*/0, /*Op*/2, /*Renderer*/GIMT_Encode2(0), GIMT_Encode2(GICP_gi_vop3mods0),
        GIM_CheckComplexPattern, /*MI*/0, /*Op*/3, /*Renderer*/GIMT_Encode2(1), GIMT_Encode2(GICP_gi_vop3mods),
        GIM_CheckComplexPattern, /*MI*/0, /*Op*/4, /*Renderer*/GIMT_Encode2(2), GIMT_Encode2(GICP_gi_vop3mods),
        // (intrinsic_wo_chain:{ *:[f64] } 1924:{ *:[iPTR] }, (VOP3Mods0:{ *:[f64] } f64:{ *:[f64] }:$src0, i32:{ *:[i32] }:$src0_modifiers, i1:{ *:[i1] }:$clamp, i32:{ *:[i32] }:$omod), (VOP3Mods:{ *:[f64] } f64:{ *:[f64] }:$src1, i32:{ *:[i32] }:$src1_modifiers), (VOP3Mods:{ *:[f64] } f64:{ *:[f64] }:$src2, i32:{ *:[i32] }:$src2_modifiers))  =>  (V_DIV_FIXUP_F64_e64:{ *:[f64] } i32:{ *:[i32] }:$src0_modifiers, f64:{ *:[f64] }:$src0, i32:{ *:[i32] }:$src1_modifiers, f64:{ *:[f64] }:$src1, i32:{ *:[i32] }:$src2_modifiers, f64:{ *:[f64] }:$src2, i1:{ *:[i1] }:$clamp, i32:{ *:[i32] }:$omod)
        GIR_BuildMI, /*InsnID*/0, /*Opcode*/GIMT_Encode2(AMDGPU::V_DIV_FIXUP_F64_e64),
        GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/0, // DstI[vdst]
        GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/1, // src0_modifiers
        GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/0, // src0
        GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(1), /*SubOperand*/1, // src1_modifiers
        GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(1), /*SubOperand*/0, // src1
        GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(2), /*SubOperand*/1, // src2_modifiers
        GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(2), /*SubOperand*/0, // src2
        GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/2, // clamp
        GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/3, // omod
        GIR_ConstrainSelectedInstOperands, /*InsnID*/0,
        GIR_EraseFromParent, /*InsnID*/0,
        // GIR_Coverage, 900,
        GIR_Done,
      // Label 3184: @204722
      GIM_Try, /*On fail goto*//*Label 3185*/ GIMT_Encode4(204830), // Rule ID 919 //
        GIM_CheckFeatures, GIMT_Encode2(GIFBS_Has16BitInsts_isGFX8Only),
        GIM_CheckIntrinsicID, /*MI*/0, /*Op*/1, GIMT_Encode2(Intrinsic::amdgcn_div_fixup),
        GIM_CheckType, /*MI*/0, /*Op*/0, /*Type*/GILLT_s16,
        GIM_CheckType, /*MI*/0, /*Op*/2, /*Type*/GILLT_s16,
        GIM_CheckType, /*MI*/0, /*Op*/3, /*Type*/GILLT_s16,
        GIM_CheckType, /*MI*/0, /*Op*/4, /*Type*/GILLT_s16,
        GIM_CheckRegBankForClass, /*MI*/0, /*Op*/0, /*RC*/GIMT_Encode2(AMDGPU::VGPR_32RegClassID),
        GIM_CheckComplexPattern, /*MI*/0, /*Op*/2, /*Renderer*/GIMT_Encode2(0), GIMT_Encode2(GICP_gi_vop3mods0),
        GIM_CheckComplexPattern, /*MI*/0, /*Op*/3, /*Renderer*/GIMT_Encode2(1), GIMT_Encode2(GICP_gi_vop3mods),
        GIM_CheckComplexPattern, /*MI*/0, /*Op*/4, /*Renderer*/GIMT_Encode2(2), GIMT_Encode2(GICP_gi_vop3mods),
        // (intrinsic_wo_chain:{ *:[f16] } 1924:{ *:[iPTR] }, (VOP3Mods0:{ *:[f16] } f16:{ *:[f16] }:$src0, i32:{ *:[i32] }:$src0_modifiers, i1:{ *:[i1] }:$clamp, i32:{ *:[i32] }:$omod), (VOP3Mods:{ *:[f16] } f16:{ *:[f16] }:$src1, i32:{ *:[i32] }:$src1_modifiers), (VOP3Mods:{ *:[f16] } f16:{ *:[f16] }:$src2, i32:{ *:[i32] }:$src2_modifiers))  =>  (V_DIV_FIXUP_F16_e64:{ *:[f16] } i32:{ *:[i32] }:$src0_modifiers, f16:{ *:[f16] }:$src0, i32:{ *:[i32] }:$src1_modifiers, f16:{ *:[f16] }:$src1, i32:{ *:[i32] }:$src2_modifiers, f16:{ *:[f16] }:$src2, i1:{ *:[i1] }:$clamp, i32:{ *:[i32] }:$omod)
        GIR_BuildMI, /*InsnID*/0, /*Opcode*/GIMT_Encode2(AMDGPU::V_DIV_FIXUP_F16_e64),
        GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/0, // DstI[vdst]
        GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/1, // src0_modifiers
        GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/0, // src0
        GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(1), /*SubOperand*/1, // src1_modifiers
        GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(1), /*SubOperand*/0, // src1
        GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(2), /*SubOperand*/1, // src2_modifiers
        GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(2), /*SubOperand*/0, // src2
        GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/2, // clamp
        GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/3, // omod
        GIR_ConstrainSelectedInstOperands, /*InsnID*/0,
        GIR_EraseFromParent, /*InsnID*/0,
        // GIR_Coverage, 919,
        GIR_Done,
      // Label 3185: @204830
      GIM_Try, /*On fail goto*//*Label 3186*/ GIMT_Encode4(204938), // Rule ID 928 //
        GIM_CheckFeatures, GIMT_Encode2(GIFBS_Has16BitInsts),
        GIM_CheckIntrinsicID, /*MI*/0, /*Op*/1, GIMT_Encode2(Intrinsic::amdgcn_fmad_ftz),
        GIM_CheckType, /*MI*/0, /*Op*/0, /*Type*/GILLT_s16,
        GIM_CheckType, /*MI*/0, /*Op*/2, /*Type*/GILLT_s16,
        GIM_CheckType, /*MI*/0, /*Op*/3, /*Type*/GILLT_s16,
        GIM_CheckType, /*MI*/0, /*Op*/4, /*Type*/GILLT_s16,
        GIM_CheckRegBankForClass, /*MI*/0, /*Op*/0, /*RC*/GIMT_Encode2(AMDGPU::VGPR_32RegClassID),
        GIM_CheckComplexPattern, /*MI*/0, /*Op*/2, /*Renderer*/GIMT_Encode2(0), GIMT_Encode2(GICP_gi_vop3mods0),
        GIM_CheckComplexPattern, /*MI*/0, /*Op*/3, /*Renderer*/GIMT_Encode2(1), GIMT_Encode2(GICP_gi_vop3mods),
        GIM_CheckComplexPattern, /*MI*/0, /*Op*/4, /*Renderer*/GIMT_Encode2(2), GIMT_Encode2(GICP_gi_vop3mods),
        // (intrinsic_wo_chain:{ *:[f16] } 1971:{ *:[iPTR] }, (VOP3Mods0:{ *:[f16] } f16:{ *:[f16] }:$src0, i32:{ *:[i32] }:$src0_modifiers, i1:{ *:[i1] }:$clamp, i32:{ *:[i32] }:$omod), (VOP3Mods:{ *:[f16] } f16:{ *:[f16] }:$src1, i32:{ *:[i32] }:$src1_modifiers), (VOP3Mods:{ *:[f16] } f16:{ *:[f16] }:$src2, i32:{ *:[i32] }:$src2_modifiers))  =>  (V_MAD_F16_e64:{ *:[f16] } i32:{ *:[i32] }:$src0_modifiers, f16:{ *:[f16] }:$src0, i32:{ *:[i32] }:$src1_modifiers, f16:{ *:[f16] }:$src1, i32:{ *:[i32] }:$src2_modifiers, f16:{ *:[f16] }:$src2, i1:{ *:[i1] }:$clamp, i32:{ *:[i32] }:$omod)
        GIR_BuildMI, /*InsnID*/0, /*Opcode*/GIMT_Encode2(AMDGPU::V_MAD_F16_e64),
        GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/0, // DstI[vdst]
        GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/1, // src0_modifiers
        GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/0, // src0
        GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(1), /*SubOperand*/1, // src1_modifiers
        GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(1), /*SubOperand*/0, // src1
        GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(2), /*SubOperand*/1, // src2_modifiers
        GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(2), /*SubOperand*/0, // src2
        GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/2, // clamp
        GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/3, // omod
        GIR_ConstrainSelectedInstOperands, /*InsnID*/0,
        GIR_EraseFromParent, /*InsnID*/0,
        // GIR_Coverage, 928,
        GIR_Done,
      // Label 3186: @204938
      GIM_Try, /*On fail goto*//*Label 3187*/ GIMT_Encode4(205046), // Rule ID 7170 //
        GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasFmaLegacy32),
        GIM_CheckIntrinsicID, /*MI*/0, /*Op*/1, GIMT_Encode2(Intrinsic::amdgcn_fma_legacy),
        GIM_CheckType, /*MI*/0, /*Op*/0, /*Type*/GILLT_s32,
        GIM_CheckType, /*MI*/0, /*Op*/2, /*Type*/GILLT_s32,
        GIM_CheckType, /*MI*/0, /*Op*/3, /*Type*/GILLT_s32,
        GIM_CheckType, /*MI*/0, /*Op*/4, /*Type*/GILLT_s32,
        GIM_CheckRegBankForClass, /*MI*/0, /*Op*/0, /*RC*/GIMT_Encode2(AMDGPU::VGPR_32RegClassID),
        GIM_CheckComplexPattern, /*MI*/0, /*Op*/2, /*Renderer*/GIMT_Encode2(0), GIMT_Encode2(GICP_gi_vop3mods),
        GIM_CheckComplexPattern, /*MI*/0, /*Op*/3, /*Renderer*/GIMT_Encode2(1), GIMT_Encode2(GICP_gi_vop3mods0),
        GIM_CheckComplexPattern, /*MI*/0, /*Op*/4, /*Renderer*/GIMT_Encode2(2), GIMT_Encode2(GICP_gi_vop3mods),
        // (intrinsic_wo_chain:{ *:[f32] } 1970:{ *:[iPTR] }, (VOP3Mods:{ *:[f32] } f32:{ *:[f32] }:$src1, i32:{ *:[i32] }:$src1_modifiers), (VOP3Mods0:{ *:[f32] } f32:{ *:[f32] }:$src0, i32:{ *:[i32] }:$src0_modifiers, i1:{ *:[i1] }:$clamp, i32:{ *:[i32] }:$omod), (VOP3Mods:{ *:[f32] } f32:{ *:[f32] }:$src2, i32:{ *:[i32] }:$src2_modifiers))  =>  (V_FMA_LEGACY_F32_e64:{ *:[f32] } i32:{ *:[i32] }:$src0_modifiers, f32:{ *:[f32] }:$src0, i32:{ *:[i32] }:$src1_modifiers, f32:{ *:[f32] }:$src1, i32:{ *:[i32] }:$src2_modifiers, f32:{ *:[f32] }:$src2, i1:{ *:[i1] }:$clamp, i32:{ *:[i32] }:$omod)
        GIR_BuildMI, /*InsnID*/0, /*Opcode*/GIMT_Encode2(AMDGPU::V_FMA_LEGACY_F32_e64),
        GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/0, // DstI[vdst]
        GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(1), /*SubOperand*/1, // src0_modifiers
        GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(1), /*SubOperand*/0, // src0
        GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/1, // src1_modifiers
        GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/0, // src1
        GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(2), /*SubOperand*/1, // src2_modifiers
        GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(2), /*SubOperand*/0, // src2
        GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(1), /*SubOperand*/2, // clamp
        GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(1), /*SubOperand*/3, // omod
        GIR_ConstrainSelectedInstOperands, /*InsnID*/0,
        GIR_EraseFromParent, /*InsnID*/0,
        // GIR_Coverage, 7170,
        GIR_Done,
      // Label 3187: @205046
      GIM_Try, /*On fail goto*//*Label 3188*/ GIMT_Encode4(205153), // Rule ID 923 //
        GIM_CheckFeatures, GIMT_Encode2(GIFBS_isGFX9Plus),
        GIM_CheckIntrinsicID, /*MI*/0, /*Op*/1, GIMT_Encode2(Intrinsic::amdgcn_div_fixup),
        GIM_CheckType, /*MI*/0, /*Op*/0, /*Type*/GILLT_s16,
        GIM_CheckType, /*MI*/0, /*Op*/2, /*Type*/GILLT_s16,
        GIM_CheckType, /*MI*/0, /*Op*/3, /*Type*/GILLT_s16,
        GIM_CheckType, /*MI*/0, /*Op*/4, /*Type*/GILLT_s16,
        GIM_CheckRegBankForClass, /*MI*/0, /*Op*/0, /*RC*/GIMT_Encode2(AMDGPU::VGPR_32RegClassID),
        GIM_CheckComplexPattern, /*MI*/0, /*Op*/2, /*Renderer*/GIMT_Encode2(0), GIMT_Encode2(GICP_gi_vop3opselmods),
        GIM_CheckComplexPattern, /*MI*/0, /*Op*/3, /*Renderer*/GIMT_Encode2(1), GIMT_Encode2(GICP_gi_vop3opselmods),
        GIM_CheckComplexPattern, /*MI*/0, /*Op*/4, /*Renderer*/GIMT_Encode2(2), GIMT_Encode2(GICP_gi_vop3opselmods),
        // (intrinsic_wo_chain:{ *:[f16] } 1924:{ *:[iPTR] }, (VOP3OpSelMods:{ *:[f16] } f16:{ *:[f16] }:$src0, i32:{ *:[i32] }:$src0_modifiers), (VOP3OpSelMods:{ *:[f16] } f16:{ *:[f16] }:$src1, i32:{ *:[i32] }:$src1_modifiers), (VOP3OpSelMods:{ *:[f16] } f16:{ *:[f16] }:$src2, i32:{ *:[i32] }:$src2_modifiers))  =>  (V_DIV_FIXUP_F16_gfx9_e64:{ *:[f16] } i32:{ *:[i32] }:$src0_modifiers, f16:{ *:[f16] }:$src0, i32:{ *:[i32] }:$src1_modifiers, f16:{ *:[f16] }:$src1, i32:{ *:[i32] }:$src2_modifiers, f16:{ *:[f16] }:$src2)
        GIR_BuildMI, /*InsnID*/0, /*Opcode*/GIMT_Encode2(AMDGPU::V_DIV_FIXUP_F16_gfx9_e64),
        GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/0, // DstI[vdst]
        GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/1, // src0_modifiers
        GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/0, // src0
        GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(1), /*SubOperand*/1, // src1_modifiers
        GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(1), /*SubOperand*/0, // src1
        GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(2), /*SubOperand*/1, // src2_modifiers
        GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(2), /*SubOperand*/0, // src2
        GIR_AddImm8, /*InsnID*/0, /*Imm*/0,
        GIR_AddImm8, /*InsnID*/0, /*Imm*/0,
        GIR_AddImm8, /*InsnID*/0, /*Imm*/0,
        GIR_ConstrainSelectedInstOperands, /*InsnID*/0,
        GIR_EraseFromParent, /*InsnID*/0,
        // GIR_Coverage, 923,
        GIR_Done,
      // Label 3188: @205153
      GIM_Try, /*On fail goto*//*Label 3189*/ GIMT_Encode4(205260), // Rule ID 932 //
        GIM_CheckFeatures, GIMT_Encode2(GIFBS_isGFX9Plus),
        GIM_CheckIntrinsicID, /*MI*/0, /*Op*/1, GIMT_Encode2(Intrinsic::amdgcn_fmed3),
        GIM_CheckType, /*MI*/0, /*Op*/0, /*Type*/GILLT_s16,
        GIM_CheckType, /*MI*/0, /*Op*/2, /*Type*/GILLT_s16,
        GIM_CheckType, /*MI*/0, /*Op*/3, /*Type*/GILLT_s16,
        GIM_CheckType, /*MI*/0, /*Op*/4, /*Type*/GILLT_s16,
        GIM_CheckRegBankForClass, /*MI*/0, /*Op*/0, /*RC*/GIMT_Encode2(AMDGPU::VGPR_32RegClassID),
        GIM_CheckComplexPattern, /*MI*/0, /*Op*/2, /*Renderer*/GIMT_Encode2(0), GIMT_Encode2(GICP_gi_vop3opselmods),
        GIM_CheckComplexPattern, /*MI*/0, /*Op*/3, /*Renderer*/GIMT_Encode2(1), GIMT_Encode2(GICP_gi_vop3opselmods),
        GIM_CheckComplexPattern, /*MI*/0, /*Op*/4, /*Renderer*/GIMT_Encode2(2), GIMT_Encode2(GICP_gi_vop3opselmods),
        // (intrinsic_wo_chain:{ *:[f16] } 1972:{ *:[iPTR] }, (VOP3OpSelMods:{ *:[f16] } f16:{ *:[f16] }:$src0, i32:{ *:[i32] }:$src0_modifiers), (VOP3OpSelMods:{ *:[f16] } f16:{ *:[f16] }:$src1, i32:{ *:[i32] }:$src1_modifiers), (VOP3OpSelMods:{ *:[f16] } f16:{ *:[f16] }:$src2, i32:{ *:[i32] }:$src2_modifiers))  =>  (V_MED3_F16_e64:{ *:[f16] } i32:{ *:[i32] }:$src0_modifiers, f16:{ *:[f16] }:$src0, i32:{ *:[i32] }:$src1_modifiers, f16:{ *:[f16] }:$src1, i32:{ *:[i32] }:$src2_modifiers, f16:{ *:[f16] }:$src2)
        GIR_BuildMI, /*InsnID*/0, /*Opcode*/GIMT_Encode2(AMDGPU::V_MED3_F16_e64),
        GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/0, // DstI[vdst]
        GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/1, // src0_modifiers
        GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/0, // src0
        GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(1), /*SubOperand*/1, // src1_modifiers
        GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(1), /*SubOperand*/0, // src1
        GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(2), /*SubOperand*/1, // src2_modifiers
        GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(2), /*SubOperand*/0, // src2
        GIR_AddImm8, /*InsnID*/0, /*Imm*/0,
        GIR_AddImm8, /*InsnID*/0, /*Imm*/0,
        GIR_AddImm8, /*InsnID*/0, /*Imm*/0,
        GIR_ConstrainSelectedInstOperands, /*InsnID*/0,
        GIR_EraseFromParent, /*InsnID*/0,
        // GIR_Coverage, 932,
        GIR_Done,
      // Label 3189: @205260
      GIM_Try, /*On fail goto*//*Label 3190*/ GIMT_Encode4(205361), // Rule ID 946 //
        GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasDot9Insts),
        GIM_CheckIntrinsicID, /*MI*/0, /*Op*/1, GIMT_Encode2(Intrinsic::amdgcn_fdot2_f16_f16),
        GIM_CheckType, /*MI*/0, /*Op*/0, /*Type*/GILLT_s16,
        GIM_CheckType, /*MI*/0, /*Op*/2, /*Type*/GILLT_v2s16,
        GIM_CheckType, /*MI*/0, /*Op*/3, /*Type*/GILLT_v2s16,
        GIM_CheckType, /*MI*/0, /*Op*/4, /*Type*/GILLT_s16,
        GIM_CheckRegBankForClass, /*MI*/0, /*Op*/0, /*RC*/GIMT_Encode2(AMDGPU::VGPR_32RegClassID),
        GIM_CheckComplexPattern, /*MI*/0, /*Op*/2, /*Renderer*/GIMT_Encode2(0), GIMT_Encode2(GICP_gi_vop3opselmods),
        GIM_CheckComplexPattern, /*MI*/0, /*Op*/3, /*Renderer*/GIMT_Encode2(1), GIMT_Encode2(GICP_gi_vop3opselmods),
        GIM_CheckComplexPattern, /*MI*/0, /*Op*/4, /*Renderer*/GIMT_Encode2(2), GIMT_Encode2(GICP_gi_vop3opselmods),
        // (intrinsic_wo_chain:{ *:[f16] } 1962:{ *:[iPTR] }, (VOP3OpSelMods:{ *:[v2f16] } v2f16:{ *:[v2f16] }:$src0, i32:{ *:[i32] }:$src0_modifiers), (VOP3OpSelMods:{ *:[v2f16] } v2f16:{ *:[v2f16] }:$src1, i32:{ *:[i32] }:$src1_modifiers), (VOP3OpSelMods:{ *:[f16] } f16:{ *:[f16] }:$src2, i32:{ *:[i32] }:$src2_modifiers))  =>  (V_DOT2_F16_F16_e64:{ *:[f16] } i32:{ *:[i32] }:$src0_modifiers, v2f16:{ *:[v2f16] }:$src0, i32:{ *:[i32] }:$src1_modifiers, v2f16:{ *:[v2f16] }:$src1, i32:{ *:[i32] }:$src2_modifiers, f16:{ *:[f16] }:$src2)
        GIR_BuildMI, /*InsnID*/0, /*Opcode*/GIMT_Encode2(AMDGPU::V_DOT2_F16_F16_e64),
        GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/0, // DstI[vdst]
        GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/1, // src0_modifiers
        GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/0, // src0
        GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(1), /*SubOperand*/1, // src1_modifiers
        GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(1), /*SubOperand*/0, // src1
        GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(2), /*SubOperand*/1, // src2_modifiers
        GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(2), /*SubOperand*/0, // src2
        GIR_AddImm8, /*InsnID*/0, /*Imm*/0,
        GIR_ConstrainSelectedInstOperands, /*InsnID*/0,
        GIR_EraseFromParent, /*InsnID*/0,
        // GIR_Coverage, 946,
        GIR_Done,
      // Label 3190: @205361
      GIM_Try, /*On fail goto*//*Label 3191*/ GIMT_Encode4(205462), // Rule ID 947 //
        GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasDot9Insts),
        GIM_CheckIntrinsicID, /*MI*/0, /*Op*/1, GIMT_Encode2(Intrinsic::amdgcn_fdot2_bf16_bf16),
        GIM_CheckType, /*MI*/0, /*Op*/0, /*Type*/GILLT_s16,
        GIM_CheckType, /*MI*/0, /*Op*/2, /*Type*/GILLT_v2s16,
        GIM_CheckType, /*MI*/0, /*Op*/3, /*Type*/GILLT_v2s16,
        GIM_CheckType, /*MI*/0, /*Op*/4, /*Type*/GILLT_s16,
        GIM_CheckRegBankForClass, /*MI*/0, /*Op*/0, /*RC*/GIMT_Encode2(AMDGPU::VGPR_32RegClassID),
        GIM_CheckComplexPattern, /*MI*/0, /*Op*/2, /*Renderer*/GIMT_Encode2(0), GIMT_Encode2(GICP_gi_vop3opselmods),
        GIM_CheckComplexPattern, /*MI*/0, /*Op*/3, /*Renderer*/GIMT_Encode2(1), GIMT_Encode2(GICP_gi_vop3opselmods),
        GIM_CheckComplexPattern, /*MI*/0, /*Op*/4, /*Renderer*/GIMT_Encode2(2), GIMT_Encode2(GICP_gi_vop3opselmods),
        // (intrinsic_wo_chain:{ *:[i16] } 1961:{ *:[iPTR] }, (VOP3OpSelMods:{ *:[v2i16] } v2i16:{ *:[v2i16] }:$src0, i32:{ *:[i32] }:$src0_modifiers), (VOP3OpSelMods:{ *:[v2i16] } v2i16:{ *:[v2i16] }:$src1, i32:{ *:[i32] }:$src1_modifiers), (VOP3OpSelMods:{ *:[i16] } i16:{ *:[i16] }:$src2, i32:{ *:[i32] }:$src2_modifiers))  =>  (V_DOT2_BF16_BF16_e64:{ *:[i16] } i32:{ *:[i32] }:$src0_modifiers, v2i16:{ *:[v2i16] }:$src0, i32:{ *:[i32] }:$src1_modifiers, v2i16:{ *:[v2i16] }:$src1, i32:{ *:[i32] }:$src2_modifiers, i16:{ *:[i16] }:$src2)
        GIR_BuildMI, /*InsnID*/0, /*Opcode*/GIMT_Encode2(AMDGPU::V_DOT2_BF16_BF16_e64),
        GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/0, // DstI[vdst]
        GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/1, // src0_modifiers
        GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/0, // src0
        GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(1), /*SubOperand*/1, // src1_modifiers
        GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(1), /*SubOperand*/0, // src1
        GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(2), /*SubOperand*/1, // src2_modifiers
        GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(2), /*SubOperand*/0, // src2
        GIR_AddImm8, /*InsnID*/0, /*Imm*/0,
        GIR_ConstrainSelectedInstOperands, /*InsnID*/0,
        GIR_EraseFromParent, /*InsnID*/0,
        // GIR_Coverage, 947,
        GIR_Done,
      // Label 3191: @205462
      GIM_Try, /*On fail goto*//*Label 3192*/ GIMT_Encode4(205526), // Rule ID 854 //
        GIM_CheckIntrinsicID, /*MI*/0, /*Op*/1, GIMT_Encode2(Intrinsic::amdgcn_lerp),
        GIM_CheckType, /*MI*/0, /*Op*/0, /*Type*/GILLT_s32,
        GIM_CheckType, /*MI*/0, /*Op*/2, /*Type*/GILLT_s32,
        GIM_CheckType, /*MI*/0, /*Op*/3, /*Type*/GILLT_s32,
        GIM_CheckType, /*MI*/0, /*Op*/4, /*Type*/GILLT_s32,
        GIM_CheckRegBankForClass, /*MI*/0, /*Op*/0, /*RC*/GIMT_Encode2(AMDGPU::VGPR_32RegClassID),
        GIM_CheckComplexPattern, /*MI*/0, /*Op*/2, /*Renderer*/GIMT_Encode2(0), GIMT_Encode2(GICP_gi_vop3mods0),
        // (intrinsic_wo_chain:{ *:[i32] } 2532:{ *:[iPTR] }, (VOP3Mods0:{ *:[i32] } i32:{ *:[i32] }:$src0), i32:{ *:[i32] }:$src1, i32:{ *:[i32] }:$src2)  =>  (V_LERP_U8_e64:{ *:[i32] } i32:{ *:[i32] }:$src0, i32:{ *:[i32] }:$src1, i32:{ *:[i32] }:$src2)
        GIR_BuildMI, /*InsnID*/0, /*Opcode*/GIMT_Encode2(AMDGPU::V_LERP_U8_e64),
        GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/0, // DstI[vdst]
        GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/0, // src0
        GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/3, // src1
        GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/4, // src2
        GIR_ConstrainSelectedInstOperands, /*InsnID*/0,
        GIR_EraseFromParent, /*InsnID*/0,
        // GIR_Coverage, 854,
        GIR_Done,
      // Label 3192: @205526
      GIM_Try, /*On fail goto*//*Label 3193*/ GIMT_Encode4(205590), // Rule ID 878 //
        GIM_CheckIntrinsicID, /*MI*/0, /*Op*/1, GIMT_Encode2(Intrinsic::amdgcn_ubfe),
        GIM_CheckType, /*MI*/0, /*Op*/0, /*Type*/GILLT_s32,
        GIM_CheckType, /*MI*/0, /*Op*/2, /*Type*/GILLT_s32,
        GIM_CheckType, /*MI*/0, /*Op*/3, /*Type*/GILLT_s32,
        GIM_CheckType, /*MI*/0, /*Op*/4, /*Type*/GILLT_s32,
        GIM_CheckRegBankForClass, /*MI*/0, /*Op*/0, /*RC*/GIMT_Encode2(AMDGPU::VGPR_32RegClassID),
        GIM_CheckComplexPattern, /*MI*/0, /*Op*/2, /*Renderer*/GIMT_Encode2(0), GIMT_Encode2(GICP_gi_vop3mods0),
        // (intrinsic_wo_chain:{ *:[i32] } 2798:{ *:[iPTR] }, (VOP3Mods0:{ *:[i32] } i32:{ *:[i32] }:$src0), i32:{ *:[i32] }:$src1, i32:{ *:[i32] }:$src2)  =>  (V_BFE_U32_e64:{ *:[i32] } i32:{ *:[i32] }:$src0, i32:{ *:[i32] }:$src1, i32:{ *:[i32] }:$src2)
        GIR_BuildMI, /*InsnID*/0, /*Opcode*/GIMT_Encode2(AMDGPU::V_BFE_U32_e64),
        GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/0, // DstI[vdst]
        GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/0, // src0
        GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/3, // src1
        GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/4, // src2
        GIR_ConstrainSelectedInstOperands, /*InsnID*/0,
        GIR_EraseFromParent, /*InsnID*/0,
        // GIR_Coverage, 878,
        GIR_Done,
      // Label 3193: @205590
      GIM_Try, /*On fail goto*//*Label 3194*/ GIMT_Encode4(205654), // Rule ID 880 //
        GIM_CheckIntrinsicID, /*MI*/0, /*Op*/1, GIMT_Encode2(Intrinsic::amdgcn_sbfe),
        GIM_CheckType, /*MI*/0, /*Op*/0, /*Type*/GILLT_s32,
        GIM_CheckType, /*MI*/0, /*Op*/2, /*Type*/GILLT_s32,
        GIM_CheckType, /*MI*/0, /*Op*/3, /*Type*/GILLT_s32,
        GIM_CheckType, /*MI*/0, /*Op*/4, /*Type*/GILLT_s32,
        GIM_CheckRegBankForClass, /*MI*/0, /*Op*/0, /*RC*/GIMT_Encode2(AMDGPU::VGPR_32RegClassID),
        GIM_CheckComplexPattern, /*MI*/0, /*Op*/2, /*Renderer*/GIMT_Encode2(0), GIMT_Encode2(GICP_gi_vop3mods0),
        // (intrinsic_wo_chain:{ *:[i32] } 2704:{ *:[iPTR] }, (VOP3Mods0:{ *:[i32] } i32:{ *:[i32] }:$src0), i32:{ *:[i32] }:$src1, i32:{ *:[i32] }:$src2)  =>  (V_BFE_I32_e64:{ *:[i32] } i32:{ *:[i32] }:$src0, i32:{ *:[i32] }:$src1, i32:{ *:[i32] }:$src2)
        GIR_BuildMI, /*InsnID*/0, /*Opcode*/GIMT_Encode2(AMDGPU::V_BFE_I32_e64),
        GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/0, // DstI[vdst]
        GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/0, // src0
        GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/3, // src1
        GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/4, // src2
        GIR_ConstrainSelectedInstOperands, /*InsnID*/0,
        GIR_EraseFromParent, /*InsnID*/0,
        // GIR_Coverage, 880,
        GIR_Done,
      // Label 3194: @205654
      GIM_Try, /*On fail goto*//*Label 3195*/ GIMT_Encode4(205718), // Rule ID 884 //
        GIM_CheckIntrinsicID, /*MI*/0, /*Op*/1, GIMT_Encode2(Intrinsic::amdgcn_alignbyte),
        GIM_CheckType, /*MI*/0, /*Op*/0, /*Type*/GILLT_s32,
        GIM_CheckType, /*MI*/0, /*Op*/2, /*Type*/GILLT_s32,
        GIM_CheckType, /*MI*/0, /*Op*/3, /*Type*/GILLT_s32,
        GIM_CheckType, /*MI*/0, /*Op*/4, /*Type*/GILLT_s32,
        GIM_CheckRegBankForClass, /*MI*/0, /*Op*/0, /*RC*/GIMT_Encode2(AMDGPU::VGPR_32RegClassID),
        GIM_CheckComplexPattern, /*MI*/0, /*Op*/2, /*Renderer*/GIMT_Encode2(0), GIMT_Encode2(GICP_gi_vop3mods0),
        // (intrinsic_wo_chain:{ *:[i32] } 1878:{ *:[iPTR] }, (VOP3Mods0:{ *:[i32] } i32:{ *:[i32] }:$src0), i32:{ *:[i32] }:$src1, i32:{ *:[i32] }:$src2)  =>  (V_ALIGNBYTE_B32_e64:{ *:[i32] } i32:{ *:[i32] }:$src0, i32:{ *:[i32] }:$src1, i32:{ *:[i32] }:$src2)
        GIR_BuildMI, /*InsnID*/0, /*Opcode*/GIMT_Encode2(AMDGPU::V_ALIGNBYTE_B32_e64),
        GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/0, // DstI[vdst]
        GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/0, // src0
        GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/3, // src1
        GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/4, // src2
        GIR_ConstrainSelectedInstOperands, /*InsnID*/0,
        GIR_EraseFromParent, /*InsnID*/0,
        // GIR_Coverage, 884,
        GIR_Done,
      // Label 3195: @205718
      GIM_Try, /*On fail goto*//*Label 3196*/ GIMT_Encode4(205785), // Rule ID 917 //
        GIM_CheckFeatures, GIMT_Encode2(GIFBS_isGFX8Plus),
        GIM_CheckIntrinsicID, /*MI*/0, /*Op*/1, GIMT_Encode2(Intrinsic::amdgcn_perm),
        GIM_CheckType, /*MI*/0, /*Op*/0, /*Type*/GILLT_s32,
        GIM_CheckType, /*MI*/0, /*Op*/2, /*Type*/GILLT_s32,
        GIM_CheckType, /*MI*/0, /*Op*/3, /*Type*/GILLT_s32,
        GIM_CheckType, /*MI*/0, /*Op*/4, /*Type*/GILLT_s32,
        GIM_CheckRegBankForClass, /*MI*/0, /*Op*/0, /*RC*/GIMT_Encode2(AMDGPU::VGPR_32RegClassID),
        GIM_CheckComplexPattern, /*MI*/0, /*Op*/2, /*Renderer*/GIMT_Encode2(0), GIMT_Encode2(GICP_gi_vop3mods0),
        // (intrinsic_wo_chain:{ *:[i32] } 2588:{ *:[iPTR] }, (VOP3Mods0:{ *:[i32] } i32:{ *:[i32] }:$src0), i32:{ *:[i32] }:$src1, i32:{ *:[i32] }:$src2)  =>  (V_PERM_B32_e64:{ *:[i32] } i32:{ *:[i32] }:$src0, i32:{ *:[i32] }:$src1, i32:{ *:[i32] }:$src2)
        GIR_BuildMI, /*InsnID*/0, /*Opcode*/GIMT_Encode2(AMDGPU::V_PERM_B32_e64),
        GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/0, // DstI[vdst]
        GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/0, // src0
        GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/3, // src1
        GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/4, // src2
        GIR_ConstrainSelectedInstOperands, /*InsnID*/0,
        GIR_EraseFromParent, /*InsnID*/0,
        // GIR_Coverage, 917,
        GIR_Done,
      // Label 3196: @205785
      GIM_Reject,
    // Label 3156: @205786
    GIM_Try, /*On fail goto*//*Label 3197*/ GIMT_Encode4(209364),
      GIM_CheckNumOperands, /*MI*/0, /*Expected*/6,
      GIM_Try, /*On fail goto*//*Label 3198*/ GIMT_Encode4(205864), // Rule ID 2119 //
        GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasDot5Insts),
        GIM_CheckIntrinsicID, /*MI*/0, /*Op*/1, GIMT_Encode2(Intrinsic::amdgcn_fdot2),
        GIM_CheckType, /*MI*/0, /*Op*/0, /*Type*/GILLT_s32,
        GIM_CheckType, /*MI*/0, /*Op*/2, /*Type*/GILLT_v2s16,
        GIM_CheckType, /*MI*/0, /*Op*/3, /*Type*/GILLT_v2s16,
        GIM_CheckType, /*MI*/0, /*Op*/4, /*Type*/GILLT_s32,
        GIM_CheckRegBankForClass, /*MI*/0, /*Op*/0, /*RC*/GIMT_Encode2(AMDGPU::VGPR_32RegClassID),
        // MIs[0] Operand 5
        GIM_CheckLiteralInt, /*MI*/0, /*Op*/5, GIMT_Encode8(0),
        // (intrinsic_wo_chain:{ *:[f32] } 1960:{ *:[iPTR] }, v2f16:{ *:[v2f16] }:$src0, v2f16:{ *:[v2f16] }:$src1, f32:{ *:[f32] }:$src2, 0:{ *:[i1] })  =>  (V_DOT2C_F32_F16_e32:{ *:[f32] } ?:{ *:[v2f16] }:$src0, ?:{ *:[v2f16] }:$src1, ?:{ *:[f32] }:$src2)
        GIR_BuildMI, /*InsnID*/0, /*Opcode*/GIMT_Encode2(AMDGPU::V_DOT2C_F32_F16_e32),
        GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/0, // DstI[vdst]
        GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/2, // src0
        GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/3, // src1
        GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/4, // src2
        GIR_ConstrainSelectedInstOperands, /*InsnID*/0,
        GIR_EraseFromParent, /*InsnID*/0,
        // GIR_Coverage, 2119,
        GIR_Done,
      // Label 3198: @205864
      GIM_Try, /*On fail goto*//*Label 3199*/ GIMT_Encode4(205934), // Rule ID 2121 //
        GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasDot6Insts),
        GIM_CheckIntrinsicID, /*MI*/0, /*Op*/1, GIMT_Encode2(Intrinsic::amdgcn_sdot4),
        GIM_CheckType, /*MI*/0, /*Op*/0, /*Type*/GILLT_s32,
        GIM_CheckType, /*MI*/0, /*Op*/2, /*Type*/GILLT_s32,
        GIM_CheckType, /*MI*/0, /*Op*/3, /*Type*/GILLT_s32,
        GIM_CheckType, /*MI*/0, /*Op*/4, /*Type*/GILLT_s32,
        GIM_CheckRegBankForClass, /*MI*/0, /*Op*/0, /*RC*/GIMT_Encode2(AMDGPU::VGPR_32RegClassID),
        // MIs[0] Operand 5
        GIM_CheckLiteralInt, /*MI*/0, /*Op*/5, GIMT_Encode8(0),
        // (intrinsic_wo_chain:{ *:[i32] } 2708:{ *:[iPTR] }, i32:{ *:[i32] }:$src0, i32:{ *:[i32] }:$src1, i32:{ *:[i32] }:$src2, 0:{ *:[i1] })  =>  (V_DOT4C_I32_I8_e32:{ *:[i32] } ?:{ *:[i32] }:$src0, ?:{ *:[i32] }:$src1, ?:{ *:[i32] }:$src2)
        GIR_BuildMI, /*InsnID*/0, /*Opcode*/GIMT_Encode2(AMDGPU::V_DOT4C_I32_I8_e32),
        GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/0, // DstI[vdst]
        GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/2, // src0
        GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/3, // src1
        GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/4, // src2
        GIR_ConstrainSelectedInstOperands, /*InsnID*/0,
        GIR_EraseFromParent, /*InsnID*/0,
        // GIR_Coverage, 2121,
        GIR_Done,
      // Label 3199: @205934
      GIM_Try, /*On fail goto*//*Label 3200*/ GIMT_Encode4(206004), // Rule ID 2122 //
        GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasDot4Insts),
        GIM_CheckIntrinsicID, /*MI*/0, /*Op*/1, GIMT_Encode2(Intrinsic::amdgcn_sdot2),
        GIM_CheckType, /*MI*/0, /*Op*/0, /*Type*/GILLT_s32,
        GIM_CheckType, /*MI*/0, /*Op*/2, /*Type*/GILLT_v2s16,
        GIM_CheckType, /*MI*/0, /*Op*/3, /*Type*/GILLT_v2s16,
        GIM_CheckType, /*MI*/0, /*Op*/4, /*Type*/GILLT_s32,
        GIM_CheckRegBankForClass, /*MI*/0, /*Op*/0, /*RC*/GIMT_Encode2(AMDGPU::VGPR_32RegClassID),
        // MIs[0] Operand 5
        GIM_CheckLiteralInt, /*MI*/0, /*Op*/5, GIMT_Encode8(0),
        // (intrinsic_wo_chain:{ *:[i32] } 2707:{ *:[iPTR] }, v2i16:{ *:[v2i16] }:$src0, v2i16:{ *:[v2i16] }:$src1, i32:{ *:[i32] }:$src2, 0:{ *:[i1] })  =>  (V_DOT2C_I32_I16_e32:{ *:[i32] } ?:{ *:[v2i16] }:$src0, ?:{ *:[v2i16] }:$src1, ?:{ *:[i32] }:$src2)
        GIR_BuildMI, /*InsnID*/0, /*Opcode*/GIMT_Encode2(AMDGPU::V_DOT2C_I32_I16_e32),
        GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/0, // DstI[vdst]
        GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/2, // src0
        GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/3, // src1
        GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/4, // src2
        GIR_ConstrainSelectedInstOperands, /*InsnID*/0,
        GIR_EraseFromParent, /*InsnID*/0,
        // GIR_Coverage, 2122,
        GIR_Done,
      // Label 3200: @206004
      GIM_Try, /*On fail goto*//*Label 3201*/ GIMT_Encode4(206074), // Rule ID 2123 //
        GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasDot3Insts),
        GIM_CheckIntrinsicID, /*MI*/0, /*Op*/1, GIMT_Encode2(Intrinsic::amdgcn_sdot8),
        GIM_CheckType, /*MI*/0, /*Op*/0, /*Type*/GILLT_s32,
        GIM_CheckType, /*MI*/0, /*Op*/2, /*Type*/GILLT_s32,
        GIM_CheckType, /*MI*/0, /*Op*/3, /*Type*/GILLT_s32,
        GIM_CheckType, /*MI*/0, /*Op*/4, /*Type*/GILLT_s32,
        GIM_CheckRegBankForClass, /*MI*/0, /*Op*/0, /*RC*/GIMT_Encode2(AMDGPU::VGPR_32RegClassID),
        // MIs[0] Operand 5
        GIM_CheckLiteralInt, /*MI*/0, /*Op*/5, GIMT_Encode8(0),
        // (intrinsic_wo_chain:{ *:[i32] } 2709:{ *:[iPTR] }, i32:{ *:[i32] }:$src0, i32:{ *:[i32] }:$src1, i32:{ *:[i32] }:$src2, 0:{ *:[i1] })  =>  (V_DOT8C_I32_I4_e32:{ *:[i32] } ?:{ *:[i32] }:$src0, ?:{ *:[i32] }:$src1, ?:{ *:[i32] }:$src2)
        GIR_BuildMI, /*InsnID*/0, /*Opcode*/GIMT_Encode2(AMDGPU::V_DOT8C_I32_I4_e32),
        GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/0, // DstI[vdst]
        GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/2, // src0
        GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/3, // src1
        GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/4, // src2
        GIR_ConstrainSelectedInstOperands, /*InsnID*/0,
        GIR_EraseFromParent, /*InsnID*/0,
        // GIR_Coverage, 2123,
        GIR_Done,
      // Label 3201: @206074
      GIM_Try, /*On fail goto*//*Label 3202*/ GIMT_Encode4(206189), // Rule ID 5833 //
        GIM_CheckIntrinsicID, /*MI*/0, /*Op*/1, GIMT_Encode2(Intrinsic::amdgcn_interp_inreg_p10_f16),
        GIM_CheckType, /*MI*/0, /*Op*/0, /*Type*/GILLT_s32,
        GIM_CheckType, /*MI*/0, /*Op*/2, /*Type*/GILLT_s32,
        GIM_CheckType, /*MI*/0, /*Op*/3, /*Type*/GILLT_s32,
        GIM_CheckType, /*MI*/0, /*Op*/4, /*Type*/GILLT_s32,
        GIM_CheckRegBankForClass, /*MI*/0, /*Op*/0, /*RC*/GIMT_Encode2(AMDGPU::VGPR_32RegClassID),
        // MIs[0] Operand 5
        GIM_CheckLiteralInt, /*MI*/0, /*Op*/5, GIMT_Encode8(0),
        GIM_CheckComplexPattern, /*MI*/0, /*Op*/2, /*Renderer*/GIMT_Encode2(0), GIMT_Encode2(GICP_gi_vinterpmods),
        GIM_CheckComplexPattern, /*MI*/0, /*Op*/3, /*Renderer*/GIMT_Encode2(1), GIMT_Encode2(GICP_gi_vinterpmods),
        GIM_CheckComplexPattern, /*MI*/0, /*Op*/4, /*Renderer*/GIMT_Encode2(2), GIMT_Encode2(GICP_gi_vinterpmods),
        // (intrinsic_wo_chain:{ *:[f32] } 2516:{ *:[iPTR] }, (VINTERPMods:{ *:[f32] } f32:{ *:[f32] }:$src0, i32:{ *:[i32] }:$src0_modifiers), (VINTERPMods:{ *:[f32] } f32:{ *:[f32] }:$src1, i32:{ *:[i32] }:$src1_modifiers), (VINTERPMods:{ *:[f32] } f32:{ *:[f32] }:$src2, i32:{ *:[i32] }:$src2_modifiers), 0:{ *:[i1] })  =>  (V_INTERP_P10_F16_F32_inreg:{ *:[f32] } ?:{ *:[i32] }:$src0_modifiers, ?:{ *:[f32] }:$src0, ?:{ *:[i32] }:$src1_modifiers, ?:{ *:[f32] }:$src1, ?:{ *:[i32] }:$src2_modifiers, ?:{ *:[f32] }:$src2, 0:{ *:[i1] }, 7:{ *:[i8] })
        GIR_BuildMI, /*InsnID*/0, /*Opcode*/GIMT_Encode2(AMDGPU::V_INTERP_P10_F16_F32_inreg),
        GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/0, // DstI[vdst]
        GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/1, // src0_modifiers
        GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/0, // src0
        GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(1), /*SubOperand*/1, // src1_modifiers
        GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(1), /*SubOperand*/0, // src1
        GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(2), /*SubOperand*/1, // src2_modifiers
        GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(2), /*SubOperand*/0, // src2
        GIR_AddImm8, /*InsnID*/0, /*Imm*/0,
        GIR_AddImm8, /*InsnID*/0, /*Imm*/0,
        GIR_AddImm8, /*InsnID*/0, /*Imm*/7,
        GIR_ConstrainSelectedInstOperands, /*InsnID*/0,
        GIR_EraseFromParent, /*InsnID*/0,
        // GIR_Coverage, 5833,
        GIR_Done,
      // Label 3202: @206189
      GIM_Try, /*On fail goto*//*Label 3203*/ GIMT_Encode4(206304), // Rule ID 5834 //
        GIM_CheckIntrinsicID, /*MI*/0, /*Op*/1, GIMT_Encode2(Intrinsic::amdgcn_interp_inreg_p10_f16),
        GIM_CheckType, /*MI*/0, /*Op*/0, /*Type*/GILLT_s32,
        GIM_CheckType, /*MI*/0, /*Op*/2, /*Type*/GILLT_s32,
        GIM_CheckType, /*MI*/0, /*Op*/3, /*Type*/GILLT_s32,
        GIM_CheckType, /*MI*/0, /*Op*/4, /*Type*/GILLT_s32,
        GIM_CheckRegBankForClass, /*MI*/0, /*Op*/0, /*RC*/GIMT_Encode2(AMDGPU::VGPR_32RegClassID),
        // MIs[0] Operand 5
        GIM_CheckLiteralInt, /*MI*/0, /*Op*/5, GIMT_Encode8(-1),
        GIM_CheckComplexPattern, /*MI*/0, /*Op*/2, /*Renderer*/GIMT_Encode2(0), GIMT_Encode2(GICP_gi_vinterpmods_hi),
        GIM_CheckComplexPattern, /*MI*/0, /*Op*/3, /*Renderer*/GIMT_Encode2(1), GIMT_Encode2(GICP_gi_vinterpmods),
        GIM_CheckComplexPattern, /*MI*/0, /*Op*/4, /*Renderer*/GIMT_Encode2(2), GIMT_Encode2(GICP_gi_vinterpmods_hi),
        // (intrinsic_wo_chain:{ *:[f32] } 2516:{ *:[iPTR] }, (VINTERPModsHi:{ *:[f32] } f32:{ *:[f32] }:$src0, i32:{ *:[i32] }:$src0_modifiers), (VINTERPMods:{ *:[f32] } f32:{ *:[f32] }:$src1, i32:{ *:[i32] }:$src1_modifiers), (VINTERPModsHi:{ *:[f32] } f32:{ *:[f32] }:$src2, i32:{ *:[i32] }:$src2_modifiers), -1:{ *:[i1] })  =>  (V_INTERP_P10_F16_F32_inreg:{ *:[f32] } ?:{ *:[i32] }:$src0_modifiers, ?:{ *:[f32] }:$src0, ?:{ *:[i32] }:$src1_modifiers, ?:{ *:[f32] }:$src1, ?:{ *:[i32] }:$src2_modifiers, ?:{ *:[f32] }:$src2, 0:{ *:[i1] }, 7:{ *:[i8] })
        GIR_BuildMI, /*InsnID*/0, /*Opcode*/GIMT_Encode2(AMDGPU::V_INTERP_P10_F16_F32_inreg),
        GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/0, // DstI[vdst]
        GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/1, // src0_modifiers
        GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/0, // src0
        GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(1), /*SubOperand*/1, // src1_modifiers
        GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(1), /*SubOperand*/0, // src1
        GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(2), /*SubOperand*/1, // src2_modifiers
        GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(2), /*SubOperand*/0, // src2
        GIR_AddImm8, /*InsnID*/0, /*Imm*/0,
        GIR_AddImm8, /*InsnID*/0, /*Imm*/0,
        GIR_AddImm8, /*InsnID*/0, /*Imm*/7,
        GIR_ConstrainSelectedInstOperands, /*InsnID*/0,
        GIR_EraseFromParent, /*InsnID*/0,
        // GIR_Coverage, 5834,
        GIR_Done,
      // Label 3203: @206304
      GIM_Try, /*On fail goto*//*Label 3204*/ GIMT_Encode4(206419), // Rule ID 5837 //
        GIM_CheckIntrinsicID, /*MI*/0, /*Op*/1, GIMT_Encode2(Intrinsic::amdgcn_interp_inreg_p2_f16),
        GIM_CheckType, /*MI*/0, /*Op*/0, /*Type*/GILLT_s16,
        GIM_CheckType, /*MI*/0, /*Op*/2, /*Type*/GILLT_s32,
        GIM_CheckType, /*MI*/0, /*Op*/3, /*Type*/GILLT_s32,
        GIM_CheckType, /*MI*/0, /*Op*/4, /*Type*/GILLT_s32,
        GIM_CheckRegBankForClass, /*MI*/0, /*Op*/0, /*RC*/GIMT_Encode2(AMDGPU::VGPR_32RegClassID),
        // MIs[0] Operand 5
        GIM_CheckLiteralInt, /*MI*/0, /*Op*/5, GIMT_Encode8(0),
        GIM_CheckComplexPattern, /*MI*/0, /*Op*/2, /*Renderer*/GIMT_Encode2(0), GIMT_Encode2(GICP_gi_vinterpmods),
        GIM_CheckComplexPattern, /*MI*/0, /*Op*/3, /*Renderer*/GIMT_Encode2(1), GIMT_Encode2(GICP_gi_vinterpmods),
        GIM_CheckComplexPattern, /*MI*/0, /*Op*/4, /*Renderer*/GIMT_Encode2(2), GIMT_Encode2(GICP_gi_vinterpmods),
        // (intrinsic_wo_chain:{ *:[f16] } 2518:{ *:[iPTR] }, (VINTERPMods:{ *:[f32] } f32:{ *:[f32] }:$src0, i32:{ *:[i32] }:$src0_modifiers), (VINTERPMods:{ *:[f32] } f32:{ *:[f32] }:$src1, i32:{ *:[i32] }:$src1_modifiers), (VINTERPMods:{ *:[f32] } f32:{ *:[f32] }:$src2, i32:{ *:[i32] }:$src2_modifiers), 0:{ *:[i1] })  =>  (V_INTERP_P2_F16_F32_inreg:{ *:[f16] } ?:{ *:[i32] }:$src0_modifiers, ?:{ *:[f32] }:$src0, ?:{ *:[i32] }:$src1_modifiers, ?:{ *:[f32] }:$src1, ?:{ *:[i32] }:$src2_modifiers, ?:{ *:[f32] }:$src2, 0:{ *:[i1] }, 7:{ *:[i8] })
        GIR_BuildMI, /*InsnID*/0, /*Opcode*/GIMT_Encode2(AMDGPU::V_INTERP_P2_F16_F32_inreg),
        GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/0, // DstI[vdst]
        GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/1, // src0_modifiers
        GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/0, // src0
        GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(1), /*SubOperand*/1, // src1_modifiers
        GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(1), /*SubOperand*/0, // src1
        GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(2), /*SubOperand*/1, // src2_modifiers
        GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(2), /*SubOperand*/0, // src2
        GIR_AddImm8, /*InsnID*/0, /*Imm*/0,
        GIR_AddImm8, /*InsnID*/0, /*Imm*/0,
        GIR_AddImm8, /*InsnID*/0, /*Imm*/7,
        GIR_ConstrainSelectedInstOperands, /*InsnID*/0,
        GIR_EraseFromParent, /*InsnID*/0,
        // GIR_Coverage, 5837,
        GIR_Done,
      // Label 3204: @206419
      GIM_Try, /*On fail goto*//*Label 3205*/ GIMT_Encode4(206534), // Rule ID 5838 //
        GIM_CheckIntrinsicID, /*MI*/0, /*Op*/1, GIMT_Encode2(Intrinsic::amdgcn_interp_inreg_p2_f16),
        GIM_CheckType, /*MI*/0, /*Op*/0, /*Type*/GILLT_s16,
        GIM_CheckType, /*MI*/0, /*Op*/2, /*Type*/GILLT_s32,
        GIM_CheckType, /*MI*/0, /*Op*/3, /*Type*/GILLT_s32,
        GIM_CheckType, /*MI*/0, /*Op*/4, /*Type*/GILLT_s32,
        GIM_CheckRegBankForClass, /*MI*/0, /*Op*/0, /*RC*/GIMT_Encode2(AMDGPU::VGPR_32RegClassID),
        // MIs[0] Operand 5
        GIM_CheckLiteralInt, /*MI*/0, /*Op*/5, GIMT_Encode8(-1),
        GIM_CheckComplexPattern, /*MI*/0, /*Op*/2, /*Renderer*/GIMT_Encode2(0), GIMT_Encode2(GICP_gi_vinterpmods_hi),
        GIM_CheckComplexPattern, /*MI*/0, /*Op*/3, /*Renderer*/GIMT_Encode2(1), GIMT_Encode2(GICP_gi_vinterpmods),
        GIM_CheckComplexPattern, /*MI*/0, /*Op*/4, /*Renderer*/GIMT_Encode2(2), GIMT_Encode2(GICP_gi_vinterpmods),
        // (intrinsic_wo_chain:{ *:[f16] } 2518:{ *:[iPTR] }, (VINTERPModsHi:{ *:[f32] } f32:{ *:[f32] }:$src0, i32:{ *:[i32] }:$src0_modifiers), (VINTERPMods:{ *:[f32] } f32:{ *:[f32] }:$src1, i32:{ *:[i32] }:$src1_modifiers), (VINTERPMods:{ *:[f32] } f32:{ *:[f32] }:$src2, i32:{ *:[i32] }:$src2_modifiers), -1:{ *:[i1] })  =>  (V_INTERP_P2_F16_F32_inreg:{ *:[f16] } ?:{ *:[i32] }:$src0_modifiers, ?:{ *:[f32] }:$src0, ?:{ *:[i32] }:$src1_modifiers, ?:{ *:[f32] }:$src1, ?:{ *:[i32] }:$src2_modifiers, ?:{ *:[f32] }:$src2, 0:{ *:[i1] }, 7:{ *:[i8] })
        GIR_BuildMI, /*InsnID*/0, /*Opcode*/GIMT_Encode2(AMDGPU::V_INTERP_P2_F16_F32_inreg),
        GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/0, // DstI[vdst]
        GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/1, // src0_modifiers
        GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/0, // src0
        GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(1), /*SubOperand*/1, // src1_modifiers
        GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(1), /*SubOperand*/0, // src1
        GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(2), /*SubOperand*/1, // src2_modifiers
        GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(2), /*SubOperand*/0, // src2
        GIR_AddImm8, /*InsnID*/0, /*Imm*/0,
        GIR_AddImm8, /*InsnID*/0, /*Imm*/0,
        GIR_AddImm8, /*InsnID*/0, /*Imm*/7,
        GIR_ConstrainSelectedInstOperands, /*InsnID*/0,
        GIR_EraseFromParent, /*InsnID*/0,
        // GIR_Coverage, 5838,
        GIR_Done,
      // Label 3205: @206534
      GIM_Try, /*On fail goto*//*Label 3206*/ GIMT_Encode4(206661), // Rule ID 2218 //
        GIM_CheckFeatures, GIMT_Encode2(GIFBS_isWave64),
        GIM_CheckIntrinsicID, /*MI*/0, /*Op*/1, GIMT_Encode2(Intrinsic::amdgcn_div_fmas),
        GIM_CheckType, /*MI*/0, /*Op*/0, /*Type*/GILLT_s32,
        GIM_CheckType, /*MI*/0, /*Op*/2, /*Type*/GILLT_s32,
        GIM_CheckType, /*MI*/0, /*Op*/3, /*Type*/GILLT_s32,
        GIM_CheckType, /*MI*/0, /*Op*/4, /*Type*/GILLT_s32,
        GIM_CheckType, /*MI*/0, /*Op*/5, /*Type*/GILLT_s1,
        GIM_CheckRegBankForClass, /*MI*/0, /*Op*/0, /*RC*/GIMT_Encode2(AMDGPU::VGPR_32RegClassID),
        GIM_CheckRegBankForClass, /*MI*/0, /*Op*/5, /*RC*/GIMT_Encode2(AMDGPU::SReg_64_XEXECRegClassID),
        GIM_CheckComplexPattern, /*MI*/0, /*Op*/2, /*Renderer*/GIMT_Encode2(0), GIMT_Encode2(GICP_gi_vop3mods),
        GIM_CheckComplexPattern, /*MI*/0, /*Op*/3, /*Renderer*/GIMT_Encode2(1), GIMT_Encode2(GICP_gi_vop3mods),
        GIM_CheckComplexPattern, /*MI*/0, /*Op*/4, /*Renderer*/GIMT_Encode2(2), GIMT_Encode2(GICP_gi_vop3mods),
        // (intrinsic_wo_chain:{ *:[f32] } 1925:{ *:[iPTR] }, (VOP3Mods:{ *:[f32] } f32:{ *:[f32] }:$src0, i32:{ *:[i32] }:$src0_modifiers), (VOP3Mods:{ *:[f32] } f32:{ *:[f32] }:$src1, i32:{ *:[i32] }:$src1_modifiers), (VOP3Mods:{ *:[f32] } f32:{ *:[f32] }:$src2, i32:{ *:[i32] }:$src2_modifiers), VCC:{ *:[i1] })  =>  (V_DIV_FMAS_F32_e64:{ *:[f32] } ?:{ *:[i32] }:$src0_modifiers, ?:{ *:[f32] }:$src0, ?:{ *:[i32] }:$src1_modifiers, ?:{ *:[f32] }:$src1, ?:{ *:[i32] }:$src2_modifiers, ?:{ *:[f32] }:$src2)
        GIR_BuildMI, /*InsnID*/1, /*Opcode*/GIMT_Encode2(TargetOpcode::COPY),
        GIR_AddRegister, /*InsnID*/1, GIMT_Encode2(AMDGPU::VCC), /*AddRegisterRegFlags*/GIMT_Encode2(RegState::Define),
        GIR_Copy, /*NewInsnID*/1, /*OldInsnID*/0, /*OpIdx*/5, // VCC
        GIR_BuildMI, /*InsnID*/0, /*Opcode*/GIMT_Encode2(AMDGPU::V_DIV_FMAS_F32_e64),
        GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/0, // DstI[vdst]
        GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/1, // src0_modifiers
        GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/0, // src0
        GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(1), /*SubOperand*/1, // src1_modifiers
        GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(1), /*SubOperand*/0, // src1
        GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(2), /*SubOperand*/1, // src2_modifiers
        GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(2), /*SubOperand*/0, // src2
        GIR_AddImm8, /*InsnID*/0, /*Imm*/0,
        GIR_AddImm8, /*InsnID*/0, /*Imm*/0,
        GIR_ConstrainSelectedInstOperands, /*InsnID*/0,
        GIR_EraseFromParent, /*InsnID*/0,
        // GIR_Coverage, 2218,
        GIR_Done,
      // Label 3206: @206661
      GIM_Try, /*On fail goto*//*Label 3207*/ GIMT_Encode4(206788), // Rule ID 2220 //
        GIM_CheckFeatures, GIMT_Encode2(GIFBS_isWave64),
        GIM_CheckIntrinsicID, /*MI*/0, /*Op*/1, GIMT_Encode2(Intrinsic::amdgcn_div_fmas),
        GIM_CheckType, /*MI*/0, /*Op*/0, /*Type*/GILLT_s64,
        GIM_CheckType, /*MI*/0, /*Op*/2, /*Type*/GILLT_s64,
        GIM_CheckType, /*MI*/0, /*Op*/3, /*Type*/GILLT_s64,
        GIM_CheckType, /*MI*/0, /*Op*/4, /*Type*/GILLT_s64,
        GIM_CheckType, /*MI*/0, /*Op*/5, /*Type*/GILLT_s1,
        GIM_CheckRegBankForClass, /*MI*/0, /*Op*/0, /*RC*/GIMT_Encode2(AMDGPU::VReg_64RegClassID),
        GIM_CheckRegBankForClass, /*MI*/0, /*Op*/5, /*RC*/GIMT_Encode2(AMDGPU::SReg_64_XEXECRegClassID),
        GIM_CheckComplexPattern, /*MI*/0, /*Op*/2, /*Renderer*/GIMT_Encode2(0), GIMT_Encode2(GICP_gi_vop3mods),
        GIM_CheckComplexPattern, /*MI*/0, /*Op*/3, /*Renderer*/GIMT_Encode2(1), GIMT_Encode2(GICP_gi_vop3mods),
        GIM_CheckComplexPattern, /*MI*/0, /*Op*/4, /*Renderer*/GIMT_Encode2(2), GIMT_Encode2(GICP_gi_vop3mods),
        // (intrinsic_wo_chain:{ *:[f64] } 1925:{ *:[iPTR] }, (VOP3Mods:{ *:[f64] } f64:{ *:[f64] }:$src0, i32:{ *:[i32] }:$src0_modifiers), (VOP3Mods:{ *:[f64] } f64:{ *:[f64] }:$src1, i32:{ *:[i32] }:$src1_modifiers), (VOP3Mods:{ *:[f64] } f64:{ *:[f64] }:$src2, i32:{ *:[i32] }:$src2_modifiers), VCC:{ *:[i1] })  =>  (V_DIV_FMAS_F64_e64:{ *:[f64] } ?:{ *:[i32] }:$src0_modifiers, ?:{ *:[f64] }:$src0, ?:{ *:[i32] }:$src1_modifiers, ?:{ *:[f64] }:$src1, ?:{ *:[i32] }:$src2_modifiers, ?:{ *:[f64] }:$src2)
        GIR_BuildMI, /*InsnID*/1, /*Opcode*/GIMT_Encode2(TargetOpcode::COPY),
        GIR_AddRegister, /*InsnID*/1, GIMT_Encode2(AMDGPU::VCC), /*AddRegisterRegFlags*/GIMT_Encode2(RegState::Define),
        GIR_Copy, /*NewInsnID*/1, /*OldInsnID*/0, /*OpIdx*/5, // VCC
        GIR_BuildMI, /*InsnID*/0, /*Opcode*/GIMT_Encode2(AMDGPU::V_DIV_FMAS_F64_e64),
        GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/0, // DstI[vdst]
        GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/1, // src0_modifiers
        GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/0, // src0
        GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(1), /*SubOperand*/1, // src1_modifiers
        GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(1), /*SubOperand*/0, // src1
        GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(2), /*SubOperand*/1, // src2_modifiers
        GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(2), /*SubOperand*/0, // src2
        GIR_AddImm8, /*InsnID*/0, /*Imm*/0,
        GIR_AddImm8, /*InsnID*/0, /*Imm*/0,
        GIR_ConstrainSelectedInstOperands, /*InsnID*/0,
        GIR_EraseFromParent, /*InsnID*/0,
        // GIR_Coverage, 2220,
        GIR_Done,
      // Label 3207: @206788
      GIM_Try, /*On fail goto*//*Label 3208*/ GIMT_Encode4(206915), // Rule ID 2222 //
        GIM_CheckFeatures, GIMT_Encode2(GIFBS_isWave32),
        GIM_CheckIntrinsicID, /*MI*/0, /*Op*/1, GIMT_Encode2(Intrinsic::amdgcn_div_fmas),
        GIM_CheckType, /*MI*/0, /*Op*/0, /*Type*/GILLT_s32,
        GIM_CheckType, /*MI*/0, /*Op*/2, /*Type*/GILLT_s32,
        GIM_CheckType, /*MI*/0, /*Op*/3, /*Type*/GILLT_s32,
        GIM_CheckType, /*MI*/0, /*Op*/4, /*Type*/GILLT_s32,
        GIM_CheckType, /*MI*/0, /*Op*/5, /*Type*/GILLT_s1,
        GIM_CheckRegBankForClass, /*MI*/0, /*Op*/0, /*RC*/GIMT_Encode2(AMDGPU::VGPR_32RegClassID),
        GIM_CheckRegBankForClass, /*MI*/0, /*Op*/5, /*RC*/GIMT_Encode2(AMDGPU::SReg_32_XM0_XEXECRegClassID),
        GIM_CheckComplexPattern, /*MI*/0, /*Op*/2, /*Renderer*/GIMT_Encode2(0), GIMT_Encode2(GICP_gi_vop3mods),
        GIM_CheckComplexPattern, /*MI*/0, /*Op*/3, /*Renderer*/GIMT_Encode2(1), GIMT_Encode2(GICP_gi_vop3mods),
        GIM_CheckComplexPattern, /*MI*/0, /*Op*/4, /*Renderer*/GIMT_Encode2(2), GIMT_Encode2(GICP_gi_vop3mods),
        // (intrinsic_wo_chain:{ *:[f32] } 1925:{ *:[iPTR] }, (VOP3Mods:{ *:[f32] } f32:{ *:[f32] }:$src0, i32:{ *:[i32] }:$src0_modifiers), (VOP3Mods:{ *:[f32] } f32:{ *:[f32] }:$src1, i32:{ *:[i32] }:$src1_modifiers), (VOP3Mods:{ *:[f32] } f32:{ *:[f32] }:$src2, i32:{ *:[i32] }:$src2_modifiers), VCC_LO:{ *:[i1] })  =>  (V_DIV_FMAS_F32_e64:{ *:[f32] } ?:{ *:[i32] }:$src0_modifiers, ?:{ *:[f32] }:$src0, ?:{ *:[i32] }:$src1_modifiers, ?:{ *:[f32] }:$src1, ?:{ *:[i32] }:$src2_modifiers, ?:{ *:[f32] }:$src2)
        GIR_BuildMI, /*InsnID*/1, /*Opcode*/GIMT_Encode2(TargetOpcode::COPY),
        GIR_AddRegister, /*InsnID*/1, GIMT_Encode2(AMDGPU::VCC_LO), /*AddRegisterRegFlags*/GIMT_Encode2(RegState::Define),
        GIR_Copy, /*NewInsnID*/1, /*OldInsnID*/0, /*OpIdx*/5, // VCC_LO
        GIR_BuildMI, /*InsnID*/0, /*Opcode*/GIMT_Encode2(AMDGPU::V_DIV_FMAS_F32_e64),
        GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/0, // DstI[vdst]
        GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/1, // src0_modifiers
        GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/0, // src0
        GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(1), /*SubOperand*/1, // src1_modifiers
        GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(1), /*SubOperand*/0, // src1
        GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(2), /*SubOperand*/1, // src2_modifiers
        GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(2), /*SubOperand*/0, // src2
        GIR_AddImm8, /*InsnID*/0, /*Imm*/0,
        GIR_AddImm8, /*InsnID*/0, /*Imm*/0,
        GIR_ConstrainSelectedInstOperands, /*InsnID*/0,
        GIR_EraseFromParent, /*InsnID*/0,
        // GIR_Coverage, 2222,
        GIR_Done,
      // Label 3208: @206915
      GIM_Try, /*On fail goto*//*Label 3209*/ GIMT_Encode4(207042), // Rule ID 2224 //
        GIM_CheckFeatures, GIMT_Encode2(GIFBS_isWave32),
        GIM_CheckIntrinsicID, /*MI*/0, /*Op*/1, GIMT_Encode2(Intrinsic::amdgcn_div_fmas),
        GIM_CheckType, /*MI*/0, /*Op*/0, /*Type*/GILLT_s64,
        GIM_CheckType, /*MI*/0, /*Op*/2, /*Type*/GILLT_s64,
        GIM_CheckType, /*MI*/0, /*Op*/3, /*Type*/GILLT_s64,
        GIM_CheckType, /*MI*/0, /*Op*/4, /*Type*/GILLT_s64,
        GIM_CheckType, /*MI*/0, /*Op*/5, /*Type*/GILLT_s1,
        GIM_CheckRegBankForClass, /*MI*/0, /*Op*/0, /*RC*/GIMT_Encode2(AMDGPU::VReg_64RegClassID),
        GIM_CheckRegBankForClass, /*MI*/0, /*Op*/5, /*RC*/GIMT_Encode2(AMDGPU::SReg_32_XM0_XEXECRegClassID),
        GIM_CheckComplexPattern, /*MI*/0, /*Op*/2, /*Renderer*/GIMT_Encode2(0), GIMT_Encode2(GICP_gi_vop3mods),
        GIM_CheckComplexPattern, /*MI*/0, /*Op*/3, /*Renderer*/GIMT_Encode2(1), GIMT_Encode2(GICP_gi_vop3mods),
        GIM_CheckComplexPattern, /*MI*/0, /*Op*/4, /*Renderer*/GIMT_Encode2(2), GIMT_Encode2(GICP_gi_vop3mods),
        // (intrinsic_wo_chain:{ *:[f64] } 1925:{ *:[iPTR] }, (VOP3Mods:{ *:[f64] } f64:{ *:[f64] }:$src0, i32:{ *:[i32] }:$src0_modifiers), (VOP3Mods:{ *:[f64] } f64:{ *:[f64] }:$src1, i32:{ *:[i32] }:$src1_modifiers), (VOP3Mods:{ *:[f64] } f64:{ *:[f64] }:$src2, i32:{ *:[i32] }:$src2_modifiers), VCC_LO:{ *:[i1] })  =>  (V_DIV_FMAS_F64_e64:{ *:[f64] } ?:{ *:[i32] }:$src0_modifiers, ?:{ *:[f64] }:$src0, ?:{ *:[i32] }:$src1_modifiers, ?:{ *:[f64] }:$src1, ?:{ *:[i32] }:$src2_modifiers, ?:{ *:[f64] }:$src2)
        GIR_BuildMI, /*InsnID*/1, /*Opcode*/GIMT_Encode2(TargetOpcode::COPY),
        GIR_AddRegister, /*InsnID*/1, GIMT_Encode2(AMDGPU::VCC_LO), /*AddRegisterRegFlags*/GIMT_Encode2(RegState::Define),
        GIR_Copy, /*NewInsnID*/1, /*OldInsnID*/0, /*OpIdx*/5, // VCC_LO
        GIR_BuildMI, /*InsnID*/0, /*Opcode*/GIMT_Encode2(AMDGPU::V_DIV_FMAS_F64_e64),
        GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/0, // DstI[vdst]
        GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/1, // src0_modifiers
        GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/0, // src0
        GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(1), /*SubOperand*/1, // src1_modifiers
        GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(1), /*SubOperand*/0, // src1
        GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(2), /*SubOperand*/1, // src2_modifiers
        GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(2), /*SubOperand*/0, // src2
        GIR_AddImm8, /*InsnID*/0, /*Imm*/0,
        GIR_AddImm8, /*InsnID*/0, /*Imm*/0,
        GIR_ConstrainSelectedInstOperands, /*InsnID*/0,
        GIR_EraseFromParent, /*InsnID*/0,
        // GIR_Coverage, 2224,
        GIR_Done,
      // Label 3209: @207042
      GIM_Try, /*On fail goto*//*Label 3210*/ GIMT_Encode4(207121), // Rule ID 1107 //
        GIM_CheckFeatures, GIMT_Encode2(GIFBS_isNotGFX90APlus),
        GIM_CheckIntrinsicID, /*MI*/0, /*Op*/1, GIMT_Encode2(Intrinsic::amdgcn_interp_mov),
        GIM_CheckType, /*MI*/0, /*Op*/0, /*Type*/GILLT_s32,
        GIM_CheckType, /*MI*/0, /*Op*/5, /*Type*/GILLT_s32,
        GIM_CheckRegBankForClass, /*MI*/0, /*Op*/0, /*RC*/GIMT_Encode2(AMDGPU::VGPR_32RegClassID),
        // MIs[0] vsrc
        GIM_CheckIsImm, /*MI*/0, /*Op*/2,
        // MIs[0] attrchan
        GIM_CheckIsImm, /*MI*/0, /*Op*/3,
        // MIs[0] attr
        GIM_CheckIsImm, /*MI*/0, /*Op*/4,
        GIM_CheckRegBankForClass, /*MI*/0, /*Op*/5, /*RC*/GIMT_Encode2(AMDGPU::M0_CLASSRegClassID),
        // (intrinsic_wo_chain:{ *:[f32] } 2519:{ *:[iPTR] }, (timm:{ *:[i32] }):$vsrc, (timm:{ *:[i32] }):$attrchan, (timm:{ *:[i32] }):$attr, M0:{ *:[i32] })  =>  (V_INTERP_MOV_F32:{ *:[f32] } (timm:{ *:[i32] }):$vsrc, (timm:{ *:[i32] }):$attr, (timm:{ *:[i32] }):$attrchan)
        GIR_BuildMI, /*InsnID*/1, /*Opcode*/GIMT_Encode2(TargetOpcode::COPY),
        GIR_AddRegister, /*InsnID*/1, GIMT_Encode2(AMDGPU::M0), /*AddRegisterRegFlags*/GIMT_Encode2(RegState::Define),
        GIR_Copy, /*NewInsnID*/1, /*OldInsnID*/0, /*OpIdx*/5, // M0
        GIR_BuildMI, /*InsnID*/0, /*Opcode*/GIMT_Encode2(AMDGPU::V_INTERP_MOV_F32),
        GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/0, // DstI[vdst]
        GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/2, // vsrc
        GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/4, // attr
        GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/3, // attrchan
        GIR_ConstrainSelectedInstOperands, /*InsnID*/0,
        GIR_EraseFromParent, /*InsnID*/0,
        // GIR_Coverage, 1107,
        GIR_Done,
      // Label 3210: @207121
      GIM_Try, /*On fail goto*//*Label 3211*/ GIMT_Encode4(207201), // Rule ID 1104 //
        GIM_CheckFeatures, GIMT_Encode2(GIFBS_has32BankLDS_isNotGFX90APlus),
        GIM_CheckIntrinsicID, /*MI*/0, /*Op*/1, GIMT_Encode2(Intrinsic::amdgcn_interp_p1),
        GIM_CheckType, /*MI*/0, /*Op*/0, /*Type*/GILLT_s32,
        GIM_CheckType, /*MI*/0, /*Op*/2, /*Type*/GILLT_s32,
        GIM_CheckType, /*MI*/0, /*Op*/5, /*Type*/GILLT_s32,
        GIM_CheckRegBankForClass, /*MI*/0, /*Op*/0, /*RC*/GIMT_Encode2(AMDGPU::VGPR_32RegClassID),
        // MIs[0] attrchan
        GIM_CheckIsImm, /*MI*/0, /*Op*/3,
        // MIs[0] attr
        GIM_CheckIsImm, /*MI*/0, /*Op*/4,
        GIM_CheckRegBankForClass, /*MI*/0, /*Op*/5, /*RC*/GIMT_Encode2(AMDGPU::M0_CLASSRegClassID),
        // (intrinsic_wo_chain:{ *:[f32] } 2520:{ *:[iPTR] }, f32:{ *:[f32] }:$vsrc, (timm:{ *:[i32] }):$attrchan, (timm:{ *:[i32] }):$attr, M0:{ *:[i32] })  =>  (V_INTERP_P1_F32:{ *:[f32] } f32:{ *:[f32] }:$vsrc, (timm:{ *:[i32] }):$attr, (timm:{ *:[i32] }):$attrchan)
        GIR_BuildMI, /*InsnID*/1, /*Opcode*/GIMT_Encode2(TargetOpcode::COPY),
        GIR_AddRegister, /*InsnID*/1, GIMT_Encode2(AMDGPU::M0), /*AddRegisterRegFlags*/GIMT_Encode2(RegState::Define),
        GIR_Copy, /*NewInsnID*/1, /*OldInsnID*/0, /*OpIdx*/5, // M0
        GIR_BuildMI, /*InsnID*/0, /*Opcode*/GIMT_Encode2(AMDGPU::V_INTERP_P1_F32),
        GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/0, // DstI[vdst]
        GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/2, // vsrc
        GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/4, // attr
        GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/3, // attrchan
        GIR_ConstrainSelectedInstOperands, /*InsnID*/0,
        GIR_EraseFromParent, /*InsnID*/0,
        // GIR_Coverage, 1104,
        GIR_Done,
      // Label 3211: @207201
      GIM_Try, /*On fail goto*//*Label 3212*/ GIMT_Encode4(207281), // Rule ID 1105 //
        GIM_CheckFeatures, GIMT_Encode2(GIFBS_has16BankLDS_isNotGFX90APlus),
        GIM_CheckIntrinsicID, /*MI*/0, /*Op*/1, GIMT_Encode2(Intrinsic::amdgcn_interp_p1),
        GIM_CheckType, /*MI*/0, /*Op*/0, /*Type*/GILLT_s32,
        GIM_CheckType, /*MI*/0, /*Op*/2, /*Type*/GILLT_s32,
        GIM_CheckType, /*MI*/0, /*Op*/5, /*Type*/GILLT_s32,
        GIM_CheckRegBankForClass, /*MI*/0, /*Op*/0, /*RC*/GIMT_Encode2(AMDGPU::VGPR_32RegClassID),
        // MIs[0] attrchan
        GIM_CheckIsImm, /*MI*/0, /*Op*/3,
        // MIs[0] attr
        GIM_CheckIsImm, /*MI*/0, /*Op*/4,
        GIM_CheckRegBankForClass, /*MI*/0, /*Op*/5, /*RC*/GIMT_Encode2(AMDGPU::M0_CLASSRegClassID),
        // (intrinsic_wo_chain:{ *:[f32] } 2520:{ *:[iPTR] }, f32:{ *:[f32] }:$vsrc, (timm:{ *:[i32] }):$attrchan, (timm:{ *:[i32] }):$attr, M0:{ *:[i32] })  =>  (V_INTERP_P1_F32_16bank:{ *:[f32] } f32:{ *:[f32] }:$vsrc, (timm:{ *:[i32] }):$attr, (timm:{ *:[i32] }):$attrchan)
        GIR_BuildMI, /*InsnID*/1, /*Opcode*/GIMT_Encode2(TargetOpcode::COPY),
        GIR_AddRegister, /*InsnID*/1, GIMT_Encode2(AMDGPU::M0), /*AddRegisterRegFlags*/GIMT_Encode2(RegState::Define),
        GIR_Copy, /*NewInsnID*/1, /*OldInsnID*/0, /*OpIdx*/5, // M0
        GIR_BuildMI, /*InsnID*/0, /*Opcode*/GIMT_Encode2(AMDGPU::V_INTERP_P1_F32_16bank),
        GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/0, // DstI[vdst]
        GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/2, // vsrc
        GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/4, // attr
        GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/3, // attrchan
        GIR_ConstrainSelectedInstOperands, /*InsnID*/0,
        GIR_EraseFromParent, /*InsnID*/0,
        // GIR_Coverage, 1105,
        GIR_Done,
      // Label 3212: @207281
      GIM_Try, /*On fail goto*//*Label 3213*/ GIMT_Encode4(207360), // Rule ID 2172 //
        GIM_CheckFeatures, GIMT_Encode2(GIFBS_isGFX9Plus),
        GIM_CheckIntrinsicID, /*MI*/0, /*Op*/1, GIMT_Encode2(Intrinsic::amdgcn_cvt_pk_fp8_f32),
        GIM_CheckType, /*MI*/0, /*Op*/0, /*Type*/GILLT_s32,
        GIM_CheckType, /*MI*/0, /*Op*/2, /*Type*/GILLT_s32,
        GIM_CheckType, /*MI*/0, /*Op*/3, /*Type*/GILLT_s32,
        GIM_CheckType, /*MI*/0, /*Op*/4, /*Type*/GILLT_s32,
        GIM_CheckRegBankForClass, /*MI*/0, /*Op*/0, /*RC*/GIMT_Encode2(AMDGPU::VGPR_32RegClassID),
        // MIs[0] Operand 5
        GIM_CheckLiteralInt, /*MI*/0, /*Op*/5, GIMT_Encode8(0),
        // (intrinsic_wo_chain:{ *:[i32] } 1913:{ *:[iPTR] }, f32:{ *:[f32] }:$src0, f32:{ *:[f32] }:$src1, i32:{ *:[i32] }:$old, 0:{ *:[i1] })  =>  (V_CVT_PK_FP8_F32_e64:{ *:[i32] } 0:{ *:[i32] }, ?:{ *:[f32] }:$src0, 0:{ *:[i32] }, ?:{ *:[f32] }:$src1, ?:{ *:[i32] }:$old, 0:{ *:[i32] })
        GIR_BuildMI, /*InsnID*/0, /*Opcode*/GIMT_Encode2(AMDGPU::V_CVT_PK_FP8_F32_e64),
        GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/0, // DstI[vdst]
        GIR_AddImm8, /*InsnID*/0, /*Imm*/0,
        GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/2, // src0
        GIR_AddImm8, /*InsnID*/0, /*Imm*/0,
        GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/3, // src1
        GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/4, // old
        GIR_AddImm8, /*InsnID*/0, /*Imm*/0,
        GIR_ConstrainSelectedInstOperands, /*InsnID*/0,
        GIR_EraseFromParent, /*InsnID*/0,
        // GIR_Coverage, 2172,
        GIR_Done,
      // Label 3213: @207360
      GIM_Try, /*On fail goto*//*Label 3214*/ GIMT_Encode4(207439), // Rule ID 2173 //
        GIM_CheckFeatures, GIMT_Encode2(GIFBS_isGFX9Plus),
        GIM_CheckIntrinsicID, /*MI*/0, /*Op*/1, GIMT_Encode2(Intrinsic::amdgcn_cvt_pk_bf8_f32),
        GIM_CheckType, /*MI*/0, /*Op*/0, /*Type*/GILLT_s32,
        GIM_CheckType, /*MI*/0, /*Op*/2, /*Type*/GILLT_s32,
        GIM_CheckType, /*MI*/0, /*Op*/3, /*Type*/GILLT_s32,
        GIM_CheckType, /*MI*/0, /*Op*/4, /*Type*/GILLT_s32,
        GIM_CheckRegBankForClass, /*MI*/0, /*Op*/0, /*RC*/GIMT_Encode2(AMDGPU::VGPR_32RegClassID),
        // MIs[0] Operand 5
        GIM_CheckLiteralInt, /*MI*/0, /*Op*/5, GIMT_Encode8(0),
        // (intrinsic_wo_chain:{ *:[i32] } 1910:{ *:[iPTR] }, f32:{ *:[f32] }:$src0, f32:{ *:[f32] }:$src1, i32:{ *:[i32] }:$old, 0:{ *:[i1] })  =>  (V_CVT_PK_BF8_F32_e64:{ *:[i32] } 0:{ *:[i32] }, ?:{ *:[f32] }:$src0, 0:{ *:[i32] }, ?:{ *:[f32] }:$src1, ?:{ *:[i32] }:$old, 0:{ *:[i32] })
        GIR_BuildMI, /*InsnID*/0, /*Opcode*/GIMT_Encode2(AMDGPU::V_CVT_PK_BF8_F32_e64),
        GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/0, // DstI[vdst]
        GIR_AddImm8, /*InsnID*/0, /*Imm*/0,
        GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/2, // src0
        GIR_AddImm8, /*InsnID*/0, /*Imm*/0,
        GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/3, // src1
        GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/4, // old
        GIR_AddImm8, /*InsnID*/0, /*Imm*/0,
        GIR_ConstrainSelectedInstOperands, /*InsnID*/0,
        GIR_EraseFromParent, /*InsnID*/0,
        // GIR_Coverage, 2173,
        GIR_Done,
      // Label 3214: @207439
      GIM_Try, /*On fail goto*//*Label 3215*/ GIMT_Encode4(207518), // Rule ID 2174 //
        GIM_CheckFeatures, GIMT_Encode2(GIFBS_isGFX9Plus),
        GIM_CheckIntrinsicID, /*MI*/0, /*Op*/1, GIMT_Encode2(Intrinsic::amdgcn_cvt_pk_fp8_f32),
        GIM_CheckType, /*MI*/0, /*Op*/0, /*Type*/GILLT_s32,
        GIM_CheckType, /*MI*/0, /*Op*/2, /*Type*/GILLT_s32,
        GIM_CheckType, /*MI*/0, /*Op*/3, /*Type*/GILLT_s32,
        GIM_CheckType, /*MI*/0, /*Op*/4, /*Type*/GILLT_s32,
        GIM_CheckRegBankForClass, /*MI*/0, /*Op*/0, /*RC*/GIMT_Encode2(AMDGPU::VGPR_32RegClassID),
        // MIs[0] Operand 5
        GIM_CheckLiteralInt, /*MI*/0, /*Op*/5, GIMT_Encode8(-1),
        // (intrinsic_wo_chain:{ *:[i32] } 1913:{ *:[iPTR] }, f32:{ *:[f32] }:$src0, f32:{ *:[f32] }:$src1, i32:{ *:[i32] }:$old, -1:{ *:[i1] })  =>  (V_CVT_PK_FP8_F32_e64:{ *:[i32] } 8:{ *:[i32] }, ?:{ *:[f32] }:$src0, 0:{ *:[i32] }, ?:{ *:[f32] }:$src1, ?:{ *:[i32] }:$old, 0:{ *:[i32] })
        GIR_BuildMI, /*InsnID*/0, /*Opcode*/GIMT_Encode2(AMDGPU::V_CVT_PK_FP8_F32_e64),
        GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/0, // DstI[vdst]
        GIR_AddImm8, /*InsnID*/0, /*Imm*/8,
        GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/2, // src0
        GIR_AddImm8, /*InsnID*/0, /*Imm*/0,
        GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/3, // src1
        GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/4, // old
        GIR_AddImm8, /*InsnID*/0, /*Imm*/0,
        GIR_ConstrainSelectedInstOperands, /*InsnID*/0,
        GIR_EraseFromParent, /*InsnID*/0,
        // GIR_Coverage, 2174,
        GIR_Done,
      // Label 3215: @207518
      GIM_Try, /*On fail goto*//*Label 3216*/ GIMT_Encode4(207597), // Rule ID 2175 //
        GIM_CheckFeatures, GIMT_Encode2(GIFBS_isGFX9Plus),
        GIM_CheckIntrinsicID, /*MI*/0, /*Op*/1, GIMT_Encode2(Intrinsic::amdgcn_cvt_pk_bf8_f32),
        GIM_CheckType, /*MI*/0, /*Op*/0, /*Type*/GILLT_s32,
        GIM_CheckType, /*MI*/0, /*Op*/2, /*Type*/GILLT_s32,
        GIM_CheckType, /*MI*/0, /*Op*/3, /*Type*/GILLT_s32,
        GIM_CheckType, /*MI*/0, /*Op*/4, /*Type*/GILLT_s32,
        GIM_CheckRegBankForClass, /*MI*/0, /*Op*/0, /*RC*/GIMT_Encode2(AMDGPU::VGPR_32RegClassID),
        // MIs[0] Operand 5
        GIM_CheckLiteralInt, /*MI*/0, /*Op*/5, GIMT_Encode8(-1),
        // (intrinsic_wo_chain:{ *:[i32] } 1910:{ *:[iPTR] }, f32:{ *:[f32] }:$src0, f32:{ *:[f32] }:$src1, i32:{ *:[i32] }:$old, -1:{ *:[i1] })  =>  (V_CVT_PK_BF8_F32_e64:{ *:[i32] } 8:{ *:[i32] }, ?:{ *:[f32] }:$src0, 0:{ *:[i32] }, ?:{ *:[f32] }:$src1, ?:{ *:[i32] }:$old, 0:{ *:[i32] })
        GIR_BuildMI, /*InsnID*/0, /*Opcode*/GIMT_Encode2(AMDGPU::V_CVT_PK_BF8_F32_e64),
        GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/0, // DstI[vdst]
        GIR_AddImm8, /*InsnID*/0, /*Imm*/8,
        GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/2, // src0
        GIR_AddImm8, /*InsnID*/0, /*Imm*/0,
        GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/3, // src1
        GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/4, // old
        GIR_AddImm8, /*InsnID*/0, /*Imm*/0,
        GIR_ConstrainSelectedInstOperands, /*InsnID*/0,
        GIR_EraseFromParent, /*InsnID*/0,
        // GIR_Coverage, 2175,
        GIR_Done,
      // Label 3216: @207597
      GIM_Try, /*On fail goto*//*Label 3217*/ GIMT_Encode4(207679), // Rule ID 2176 //
        GIM_CheckFeatures, GIMT_Encode2(GIFBS_isGFX9Plus),
        GIM_CheckIntrinsicID, /*MI*/0, /*Op*/1, GIMT_Encode2(Intrinsic::amdgcn_cvt_sr_fp8_f32),
        GIM_CheckType, /*MI*/0, /*Op*/0, /*Type*/GILLT_s32,
        GIM_CheckType, /*MI*/0, /*Op*/2, /*Type*/GILLT_s32,
        GIM_CheckType, /*MI*/0, /*Op*/3, /*Type*/GILLT_s32,
        GIM_CheckType, /*MI*/0, /*Op*/4, /*Type*/GILLT_s32,
        GIM_CheckRegBankForClass, /*MI*/0, /*Op*/0, /*RC*/GIMT_Encode2(AMDGPU::VGPR_32RegClassID),
        // MIs[0] Operand 5
        GIM_CheckLiteralInt, /*MI*/0, /*Op*/5, GIMT_Encode8(0),
        // (intrinsic_wo_chain:{ *:[i32] } 1921:{ *:[iPTR] }, f32:{ *:[f32] }:$src0, i32:{ *:[i32] }:$src1, i32:{ *:[i32] }:$old, 0:{ *:[i32] })  =>  (V_CVT_SR_FP8_F32_e64:{ *:[i32] } 0:{ *:[i32] }, ?:{ *:[f32] }:$src0, 0:{ *:[i32] }, ?:{ *:[i32] }:$src1, 0:{ *:[i32] }, ?:{ *:[i32] }:$old, 0:{ *:[i32] })
        GIR_BuildMI, /*InsnID*/0, /*Opcode*/GIMT_Encode2(AMDGPU::V_CVT_SR_FP8_F32_e64),
        GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/0, // DstI[vdst]
        GIR_AddImm8, /*InsnID*/0, /*Imm*/0,
        GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/2, // src0
        GIR_AddImm8, /*InsnID*/0, /*Imm*/0,
        GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/3, // src1
        GIR_AddImm8, /*InsnID*/0, /*Imm*/0,
        GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/4, // old
        GIR_AddImm8, /*InsnID*/0, /*Imm*/0,
        GIR_ConstrainSelectedInstOperands, /*InsnID*/0,
        GIR_EraseFromParent, /*InsnID*/0,
        // GIR_Coverage, 2176,
        GIR_Done,
      // Label 3217: @207679
      GIM_Try, /*On fail goto*//*Label 3218*/ GIMT_Encode4(207761), // Rule ID 2177 //
        GIM_CheckFeatures, GIMT_Encode2(GIFBS_isGFX9Plus),
        GIM_CheckIntrinsicID, /*MI*/0, /*Op*/1, GIMT_Encode2(Intrinsic::amdgcn_cvt_sr_bf8_f32),
        GIM_CheckType, /*MI*/0, /*Op*/0, /*Type*/GILLT_s32,
        GIM_CheckType, /*MI*/0, /*Op*/2, /*Type*/GILLT_s32,
        GIM_CheckType, /*MI*/0, /*Op*/3, /*Type*/GILLT_s32,
        GIM_CheckType, /*MI*/0, /*Op*/4, /*Type*/GILLT_s32,
        GIM_CheckRegBankForClass, /*MI*/0, /*Op*/0, /*RC*/GIMT_Encode2(AMDGPU::VGPR_32RegClassID),
        // MIs[0] Operand 5
        GIM_CheckLiteralInt, /*MI*/0, /*Op*/5, GIMT_Encode8(0),
        // (intrinsic_wo_chain:{ *:[i32] } 1920:{ *:[iPTR] }, f32:{ *:[f32] }:$src0, i32:{ *:[i32] }:$src1, i32:{ *:[i32] }:$old, 0:{ *:[i32] })  =>  (V_CVT_SR_BF8_F32_e64:{ *:[i32] } 0:{ *:[i32] }, ?:{ *:[f32] }:$src0, 0:{ *:[i32] }, ?:{ *:[i32] }:$src1, 0:{ *:[i32] }, ?:{ *:[i32] }:$old, 0:{ *:[i32] })
        GIR_BuildMI, /*InsnID*/0, /*Opcode*/GIMT_Encode2(AMDGPU::V_CVT_SR_BF8_F32_e64),
        GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/0, // DstI[vdst]
        GIR_AddImm8, /*InsnID*/0, /*Imm*/0,
        GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/2, // src0
        GIR_AddImm8, /*InsnID*/0, /*Imm*/0,
        GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/3, // src1
        GIR_AddImm8, /*InsnID*/0, /*Imm*/0,
        GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/4, // old
        GIR_AddImm8, /*InsnID*/0, /*Imm*/0,
        GIR_ConstrainSelectedInstOperands, /*InsnID*/0,
        GIR_EraseFromParent, /*InsnID*/0,
        // GIR_Coverage, 2177,
        GIR_Done,
      // Label 3218: @207761
      GIM_Try, /*On fail goto*//*Label 3219*/ GIMT_Encode4(207843), // Rule ID 2178 //
        GIM_CheckFeatures, GIMT_Encode2(GIFBS_isGFX9Plus),
        GIM_CheckIntrinsicID, /*MI*/0, /*Op*/1, GIMT_Encode2(Intrinsic::amdgcn_cvt_sr_fp8_f32),
        GIM_CheckType, /*MI*/0, /*Op*/0, /*Type*/GILLT_s32,
        GIM_CheckType, /*MI*/0, /*Op*/2, /*Type*/GILLT_s32,
        GIM_CheckType, /*MI*/0, /*Op*/3, /*Type*/GILLT_s32,
        GIM_CheckType, /*MI*/0, /*Op*/4, /*Type*/GILLT_s32,
        GIM_CheckRegBankForClass, /*MI*/0, /*Op*/0, /*RC*/GIMT_Encode2(AMDGPU::VGPR_32RegClassID),
        // MIs[0] Operand 5
        GIM_CheckLiteralInt, /*MI*/0, /*Op*/5, GIMT_Encode8(1),
        // (intrinsic_wo_chain:{ *:[i32] } 1921:{ *:[iPTR] }, f32:{ *:[f32] }:$src0, i32:{ *:[i32] }:$src1, i32:{ *:[i32] }:$old, 1:{ *:[i32] })  =>  (V_CVT_SR_FP8_F32_e64:{ *:[i32] } 0:{ *:[i32] }, ?:{ *:[f32] }:$src0, 0:{ *:[i32] }, ?:{ *:[i32] }:$src1, 4:{ *:[i32] }, ?:{ *:[i32] }:$old, 0:{ *:[i32] })
        GIR_BuildMI, /*InsnID*/0, /*Opcode*/GIMT_Encode2(AMDGPU::V_CVT_SR_FP8_F32_e64),
        GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/0, // DstI[vdst]
        GIR_AddImm8, /*InsnID*/0, /*Imm*/0,
        GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/2, // src0
        GIR_AddImm8, /*InsnID*/0, /*Imm*/0,
        GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/3, // src1
        GIR_AddImm8, /*InsnID*/0, /*Imm*/4,
        GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/4, // old
        GIR_AddImm8, /*InsnID*/0, /*Imm*/0,
        GIR_ConstrainSelectedInstOperands, /*InsnID*/0,
        GIR_EraseFromParent, /*InsnID*/0,
        // GIR_Coverage, 2178,
        GIR_Done,
      // Label 3219: @207843
      GIM_Try, /*On fail goto*//*Label 3220*/ GIMT_Encode4(207925), // Rule ID 2179 //
        GIM_CheckFeatures, GIMT_Encode2(GIFBS_isGFX9Plus),
        GIM_CheckIntrinsicID, /*MI*/0, /*Op*/1, GIMT_Encode2(Intrinsic::amdgcn_cvt_sr_bf8_f32),
        GIM_CheckType, /*MI*/0, /*Op*/0, /*Type*/GILLT_s32,
        GIM_CheckType, /*MI*/0, /*Op*/2, /*Type*/GILLT_s32,
        GIM_CheckType, /*MI*/0, /*Op*/3, /*Type*/GILLT_s32,
        GIM_CheckType, /*MI*/0, /*Op*/4, /*Type*/GILLT_s32,
        GIM_CheckRegBankForClass, /*MI*/0, /*Op*/0, /*RC*/GIMT_Encode2(AMDGPU::VGPR_32RegClassID),
        // MIs[0] Operand 5
        GIM_CheckLiteralInt, /*MI*/0, /*Op*/5, GIMT_Encode8(1),
        // (intrinsic_wo_chain:{ *:[i32] } 1920:{ *:[iPTR] }, f32:{ *:[f32] }:$src0, i32:{ *:[i32] }:$src1, i32:{ *:[i32] }:$old, 1:{ *:[i32] })  =>  (V_CVT_SR_BF8_F32_e64:{ *:[i32] } 0:{ *:[i32] }, ?:{ *:[f32] }:$src0, 0:{ *:[i32] }, ?:{ *:[i32] }:$src1, 4:{ *:[i32] }, ?:{ *:[i32] }:$old, 0:{ *:[i32] })
        GIR_BuildMI, /*InsnID*/0, /*Opcode*/GIMT_Encode2(AMDGPU::V_CVT_SR_BF8_F32_e64),
        GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/0, // DstI[vdst]
        GIR_AddImm8, /*InsnID*/0, /*Imm*/0,
        GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/2, // src0
        GIR_AddImm8, /*InsnID*/0, /*Imm*/0,
        GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/3, // src1
        GIR_AddImm8, /*InsnID*/0, /*Imm*/4,
        GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/4, // old
        GIR_AddImm8, /*InsnID*/0, /*Imm*/0,
        GIR_ConstrainSelectedInstOperands, /*InsnID*/0,
        GIR_EraseFromParent, /*InsnID*/0,
        // GIR_Coverage, 2179,
        GIR_Done,
      // Label 3220: @207925
      GIM_Try, /*On fail goto*//*Label 3221*/ GIMT_Encode4(208007), // Rule ID 2180 //
        GIM_CheckFeatures, GIMT_Encode2(GIFBS_isGFX9Plus),
        GIM_CheckIntrinsicID, /*MI*/0, /*Op*/1, GIMT_Encode2(Intrinsic::amdgcn_cvt_sr_fp8_f32),
        GIM_CheckType, /*MI*/0, /*Op*/0, /*Type*/GILLT_s32,
        GIM_CheckType, /*MI*/0, /*Op*/2, /*Type*/GILLT_s32,
        GIM_CheckType, /*MI*/0, /*Op*/3, /*Type*/GILLT_s32,
        GIM_CheckType, /*MI*/0, /*Op*/4, /*Type*/GILLT_s32,
        GIM_CheckRegBankForClass, /*MI*/0, /*Op*/0, /*RC*/GIMT_Encode2(AMDGPU::VGPR_32RegClassID),
        // MIs[0] Operand 5
        GIM_CheckLiteralInt, /*MI*/0, /*Op*/5, GIMT_Encode8(2),
        // (intrinsic_wo_chain:{ *:[i32] } 1921:{ *:[iPTR] }, f32:{ *:[f32] }:$src0, i32:{ *:[i32] }:$src1, i32:{ *:[i32] }:$old, 2:{ *:[i32] })  =>  (V_CVT_SR_FP8_F32_e64:{ *:[i32] } 8:{ *:[i32] }, ?:{ *:[f32] }:$src0, 0:{ *:[i32] }, ?:{ *:[i32] }:$src1, 0:{ *:[i32] }, ?:{ *:[i32] }:$old, 0:{ *:[i32] })
        GIR_BuildMI, /*InsnID*/0, /*Opcode*/GIMT_Encode2(AMDGPU::V_CVT_SR_FP8_F32_e64),
        GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/0, // DstI[vdst]
        GIR_AddImm8, /*InsnID*/0, /*Imm*/8,
        GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/2, // src0
        GIR_AddImm8, /*InsnID*/0, /*Imm*/0,
        GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/3, // src1
        GIR_AddImm8, /*InsnID*/0, /*Imm*/0,
        GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/4, // old
        GIR_AddImm8, /*InsnID*/0, /*Imm*/0,
        GIR_ConstrainSelectedInstOperands, /*InsnID*/0,
        GIR_EraseFromParent, /*InsnID*/0,
        // GIR_Coverage, 2180,
        GIR_Done,
      // Label 3221: @208007
      GIM_Try, /*On fail goto*//*Label 3222*/ GIMT_Encode4(208089), // Rule ID 2181 //
        GIM_CheckFeatures, GIMT_Encode2(GIFBS_isGFX9Plus),
        GIM_CheckIntrinsicID, /*MI*/0, /*Op*/1, GIMT_Encode2(Intrinsic::amdgcn_cvt_sr_bf8_f32),
        GIM_CheckType, /*MI*/0, /*Op*/0, /*Type*/GILLT_s32,
        GIM_CheckType, /*MI*/0, /*Op*/2, /*Type*/GILLT_s32,
        GIM_CheckType, /*MI*/0, /*Op*/3, /*Type*/GILLT_s32,
        GIM_CheckType, /*MI*/0, /*Op*/4, /*Type*/GILLT_s32,
        GIM_CheckRegBankForClass, /*MI*/0, /*Op*/0, /*RC*/GIMT_Encode2(AMDGPU::VGPR_32RegClassID),
        // MIs[0] Operand 5
        GIM_CheckLiteralInt, /*MI*/0, /*Op*/5, GIMT_Encode8(2),
        // (intrinsic_wo_chain:{ *:[i32] } 1920:{ *:[iPTR] }, f32:{ *:[f32] }:$src0, i32:{ *:[i32] }:$src1, i32:{ *:[i32] }:$old, 2:{ *:[i32] })  =>  (V_CVT_SR_BF8_F32_e64:{ *:[i32] } 8:{ *:[i32] }, ?:{ *:[f32] }:$src0, 0:{ *:[i32] }, ?:{ *:[i32] }:$src1, 0:{ *:[i32] }, ?:{ *:[i32] }:$old, 0:{ *:[i32] })
        GIR_BuildMI, /*InsnID*/0, /*Opcode*/GIMT_Encode2(AMDGPU::V_CVT_SR_BF8_F32_e64),
        GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/0, // DstI[vdst]
        GIR_AddImm8, /*InsnID*/0, /*Imm*/8,
        GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/2, // src0
        GIR_AddImm8, /*InsnID*/0, /*Imm*/0,
        GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/3, // src1
        GIR_AddImm8, /*InsnID*/0, /*Imm*/0,
        GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/4, // old
        GIR_AddImm8, /*InsnID*/0, /*Imm*/0,
        GIR_ConstrainSelectedInstOperands, /*InsnID*/0,
        GIR_EraseFromParent, /*InsnID*/0,
        // GIR_Coverage, 2181,
        GIR_Done,
      // Label 3222: @208089
      GIM_Try, /*On fail goto*//*Label 3223*/ GIMT_Encode4(208171), // Rule ID 2182 //
        GIM_CheckFeatures, GIMT_Encode2(GIFBS_isGFX9Plus),
        GIM_CheckIntrinsicID, /*MI*/0, /*Op*/1, GIMT_Encode2(Intrinsic::amdgcn_cvt_sr_fp8_f32),
        GIM_CheckType, /*MI*/0, /*Op*/0, /*Type*/GILLT_s32,
        GIM_CheckType, /*MI*/0, /*Op*/2, /*Type*/GILLT_s32,
        GIM_CheckType, /*MI*/0, /*Op*/3, /*Type*/GILLT_s32,
        GIM_CheckType, /*MI*/0, /*Op*/4, /*Type*/GILLT_s32,
        GIM_CheckRegBankForClass, /*MI*/0, /*Op*/0, /*RC*/GIMT_Encode2(AMDGPU::VGPR_32RegClassID),
        // MIs[0] Operand 5
        GIM_CheckLiteralInt, /*MI*/0, /*Op*/5, GIMT_Encode8(3),
        // (intrinsic_wo_chain:{ *:[i32] } 1921:{ *:[iPTR] }, f32:{ *:[f32] }:$src0, i32:{ *:[i32] }:$src1, i32:{ *:[i32] }:$old, 3:{ *:[i32] })  =>  (V_CVT_SR_FP8_F32_e64:{ *:[i32] } 8:{ *:[i32] }, ?:{ *:[f32] }:$src0, 0:{ *:[i32] }, ?:{ *:[i32] }:$src1, 4:{ *:[i32] }, ?:{ *:[i32] }:$old, 0:{ *:[i32] })
        GIR_BuildMI, /*InsnID*/0, /*Opcode*/GIMT_Encode2(AMDGPU::V_CVT_SR_FP8_F32_e64),
        GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/0, // DstI[vdst]
        GIR_AddImm8, /*InsnID*/0, /*Imm*/8,
        GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/2, // src0
        GIR_AddImm8, /*InsnID*/0, /*Imm*/0,
        GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/3, // src1
        GIR_AddImm8, /*InsnID*/0, /*Imm*/4,
        GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/4, // old
        GIR_AddImm8, /*InsnID*/0, /*Imm*/0,
        GIR_ConstrainSelectedInstOperands, /*InsnID*/0,
        GIR_EraseFromParent, /*InsnID*/0,
        // GIR_Coverage, 2182,
        GIR_Done,
      // Label 3223: @208171
      GIM_Try, /*On fail goto*//*Label 3224*/ GIMT_Encode4(208253), // Rule ID 2183 //
        GIM_CheckFeatures, GIMT_Encode2(GIFBS_isGFX9Plus),
        GIM_CheckIntrinsicID, /*MI*/0, /*Op*/1, GIMT_Encode2(Intrinsic::amdgcn_cvt_sr_bf8_f32),
        GIM_CheckType, /*MI*/0, /*Op*/0, /*Type*/GILLT_s32,
        GIM_CheckType, /*MI*/0, /*Op*/2, /*Type*/GILLT_s32,
        GIM_CheckType, /*MI*/0, /*Op*/3, /*Type*/GILLT_s32,
        GIM_CheckType, /*MI*/0, /*Op*/4, /*Type*/GILLT_s32,
        GIM_CheckRegBankForClass, /*MI*/0, /*Op*/0, /*RC*/GIMT_Encode2(AMDGPU::VGPR_32RegClassID),
        // MIs[0] Operand 5
        GIM_CheckLiteralInt, /*MI*/0, /*Op*/5, GIMT_Encode8(3),
        // (intrinsic_wo_chain:{ *:[i32] } 1920:{ *:[iPTR] }, f32:{ *:[f32] }:$src0, i32:{ *:[i32] }:$src1, i32:{ *:[i32] }:$old, 3:{ *:[i32] })  =>  (V_CVT_SR_BF8_F32_e64:{ *:[i32] } 8:{ *:[i32] }, ?:{ *:[f32] }:$src0, 0:{ *:[i32] }, ?:{ *:[i32] }:$src1, 4:{ *:[i32] }, ?:{ *:[i32] }:$old, 0:{ *:[i32] })
        GIR_BuildMI, /*InsnID*/0, /*Opcode*/GIMT_Encode2(AMDGPU::V_CVT_SR_BF8_F32_e64),
        GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/0, // DstI[vdst]
        GIR_AddImm8, /*InsnID*/0, /*Imm*/8,
        GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/2, // src0
        GIR_AddImm8, /*InsnID*/0, /*Imm*/0,
        GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/3, // src1
        GIR_AddImm8, /*InsnID*/0, /*Imm*/4,
        GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/4, // old
        GIR_AddImm8, /*InsnID*/0, /*Imm*/0,
        GIR_ConstrainSelectedInstOperands, /*InsnID*/0,
        GIR_EraseFromParent, /*InsnID*/0,
        // GIR_Coverage, 2183,
        GIR_Done,
      // Label 3224: @208253
      GIM_Try, /*On fail goto*//*Label 3225*/ GIMT_Encode4(208340), // Rule ID 2269 //
        GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasDot8Insts),
        GIM_CheckIntrinsicID, /*MI*/0, /*Op*/1, GIMT_Encode2(Intrinsic::amdgcn_sdot8),
        GIM_CheckType, /*MI*/0, /*Op*/0, /*Type*/GILLT_s32,
        GIM_CheckType, /*MI*/0, /*Op*/2, /*Type*/GILLT_s32,
        GIM_CheckType, /*MI*/0, /*Op*/3, /*Type*/GILLT_s32,
        GIM_CheckType, /*MI*/0, /*Op*/4, /*Type*/GILLT_s32,
        GIM_CheckRegBankForClass, /*MI*/0, /*Op*/0, /*RC*/GIMT_Encode2(AMDGPU::VGPR_32RegClassID),
        // MIs[0] clamp
        GIM_CheckIsImm, /*MI*/0, /*Op*/5,
        // (intrinsic_wo_chain:{ *:[i32] } 2709:{ *:[iPTR] }, i32:{ *:[i32] }:$src0, i32:{ *:[i32] }:$src1, i32:{ *:[i32] }:$src2, (timm:{ *:[i1] }):$clamp)  =>  (V_DOT8_I32_IU4:{ *:[i32] } 9:{ *:[i32] }, i32:{ *:[i32] }:$src0, 9:{ *:[i32] }, i32:{ *:[i32] }:$src1, 8:{ *:[i32] }, i32:{ *:[i32] }:$src2, i1:{ *:[i1] }:$clamp)
        GIR_BuildMI, /*InsnID*/0, /*Opcode*/GIMT_Encode2(AMDGPU::V_DOT8_I32_IU4),
        GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/0, // DstI[vdst]
        GIR_AddImm8, /*InsnID*/0, /*Imm*/9,
        GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/2, // src0
        GIR_AddImm8, /*InsnID*/0, /*Imm*/9,
        GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/3, // src1
        GIR_AddImm8, /*InsnID*/0, /*Imm*/8,
        GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/4, // src2
        GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/5, // clamp
        GIR_AddImm8, /*InsnID*/0, /*Imm*/0,
        GIR_AddImm8, /*InsnID*/0, /*Imm*/0,
        GIR_AddImm8, /*InsnID*/0, /*Imm*/0,
        GIR_AddImm8, /*InsnID*/0, /*Imm*/0,
        GIR_ConstrainSelectedInstOperands, /*InsnID*/0,
        GIR_EraseFromParent, /*InsnID*/0,
        // GIR_Coverage, 2269,
        GIR_Done,
      // Label 3225: @208340
      GIM_Try, /*On fail goto*//*Label 3226*/ GIMT_Encode4(208427), // Rule ID 2270 //
        GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasDot8Insts),
        GIM_CheckIntrinsicID, /*MI*/0, /*Op*/1, GIMT_Encode2(Intrinsic::amdgcn_sdot4),
        GIM_CheckType, /*MI*/0, /*Op*/0, /*Type*/GILLT_s32,
        GIM_CheckType, /*MI*/0, /*Op*/2, /*Type*/GILLT_s32,
        GIM_CheckType, /*MI*/0, /*Op*/3, /*Type*/GILLT_s32,
        GIM_CheckType, /*MI*/0, /*Op*/4, /*Type*/GILLT_s32,
        GIM_CheckRegBankForClass, /*MI*/0, /*Op*/0, /*RC*/GIMT_Encode2(AMDGPU::VGPR_32RegClassID),
        // MIs[0] clamp
        GIM_CheckIsImm, /*MI*/0, /*Op*/5,
        // (intrinsic_wo_chain:{ *:[i32] } 2708:{ *:[iPTR] }, i32:{ *:[i32] }:$src0, i32:{ *:[i32] }:$src1, i32:{ *:[i32] }:$src2, (timm:{ *:[i1] }):$clamp)  =>  (V_DOT4_I32_IU8:{ *:[i32] } 9:{ *:[i32] }, i32:{ *:[i32] }:$src0, 9:{ *:[i32] }, i32:{ *:[i32] }:$src1, 8:{ *:[i32] }, i32:{ *:[i32] }:$src2, i1:{ *:[i1] }:$clamp)
        GIR_BuildMI, /*InsnID*/0, /*Opcode*/GIMT_Encode2(AMDGPU::V_DOT4_I32_IU8),
        GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/0, // DstI[vdst]
        GIR_AddImm8, /*InsnID*/0, /*Imm*/9,
        GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/2, // src0
        GIR_AddImm8, /*InsnID*/0, /*Imm*/9,
        GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/3, // src1
        GIR_AddImm8, /*InsnID*/0, /*Imm*/8,
        GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/4, // src2
        GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/5, // clamp
        GIR_AddImm8, /*InsnID*/0, /*Imm*/0,
        GIR_AddImm8, /*InsnID*/0, /*Imm*/0,
        GIR_AddImm8, /*InsnID*/0, /*Imm*/0,
        GIR_AddImm8, /*InsnID*/0, /*Imm*/0,
        GIR_ConstrainSelectedInstOperands, /*InsnID*/0,
        GIR_EraseFromParent, /*InsnID*/0,
        // GIR_Coverage, 2270,
        GIR_Done,
      // Label 3226: @208427
      GIM_Try, /*On fail goto*//*Label 3227*/ GIMT_Encode4(208544), // Rule ID 983 //
        GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasDot2Insts),
        GIM_CheckIntrinsicID, /*MI*/0, /*Op*/1, GIMT_Encode2(Intrinsic::amdgcn_sdot2),
        GIM_CheckType, /*MI*/0, /*Op*/0, /*Type*/GILLT_s32,
        GIM_CheckType, /*MI*/0, /*Op*/2, /*Type*/GILLT_v2s16,
        GIM_CheckType, /*MI*/0, /*Op*/3, /*Type*/GILLT_v2s16,
        GIM_CheckType, /*MI*/0, /*Op*/4, /*Type*/GILLT_s32,
        GIM_CheckRegBankForClass, /*MI*/0, /*Op*/0, /*RC*/GIMT_Encode2(AMDGPU::VGPR_32RegClassID),
        // MIs[0] clamp
        GIM_CheckIsImm, /*MI*/0, /*Op*/5,
        GIM_CheckComplexPattern, /*MI*/0, /*Op*/2, /*Renderer*/GIMT_Encode2(0), GIMT_Encode2(GICP_gi_vop3pmodsdot),
        GIM_CheckComplexPattern, /*MI*/0, /*Op*/3, /*Renderer*/GIMT_Encode2(1), GIMT_Encode2(GICP_gi_vop3pmodsdot),
        GIM_CheckComplexPattern, /*MI*/0, /*Op*/4, /*Renderer*/GIMT_Encode2(2), GIMT_Encode2(GICP_gi_vop3pmodsdot),
        // (intrinsic_wo_chain:{ *:[i32] } 2707:{ *:[iPTR] }, (VOP3PModsDOT:{ *:[v2i16] } v2i16:{ *:[v2i16] }:$src0, i32:{ *:[i32] }:$src0_modifiers), (VOP3PModsDOT:{ *:[v2i16] } v2i16:{ *:[v2i16] }:$src1, i32:{ *:[i32] }:$src1_modifiers), (VOP3PModsDOT:{ *:[i32] } i32:{ *:[i32] }:$src2, i32:{ *:[i32] }:$src2_modifiers), (timm:{ *:[i1] }):$clamp)  =>  (V_DOT2_I32_I16:{ *:[i32] } i32:{ *:[i32] }:$src0_modifiers, v2i16:{ *:[v2i16] }:$src0, i32:{ *:[i32] }:$src1_modifiers, v2i16:{ *:[v2i16] }:$src1, i32:{ *:[i32] }:$src2_modifiers, i32:{ *:[i32] }:$src2, (timm:{ *:[i1] }):$clamp)
        GIR_BuildMI, /*InsnID*/0, /*Opcode*/GIMT_Encode2(AMDGPU::V_DOT2_I32_I16),
        GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/0, // DstI[vdst]
        GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/1, // src0_modifiers
        GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/0, // src0
        GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(1), /*SubOperand*/1, // src1_modifiers
        GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(1), /*SubOperand*/0, // src1
        GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(2), /*SubOperand*/1, // src2_modifiers
        GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(2), /*SubOperand*/0, // src2
        GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/5, // clamp
        GIR_AddImm8, /*InsnID*/0, /*Imm*/0,
        GIR_AddImm8, /*InsnID*/0, /*Imm*/0,
        GIR_AddImm8, /*InsnID*/0, /*Imm*/0,
        GIR_AddImm8, /*InsnID*/0, /*Imm*/0,
        GIR_ConstrainSelectedInstOperands, /*InsnID*/0,
        GIR_EraseFromParent, /*InsnID*/0,
        // GIR_Coverage, 983,
        GIR_Done,
      // Label 3227: @208544
      GIM_Try, /*On fail goto*//*Label 3228*/ GIMT_Encode4(208661), // Rule ID 984 //
        GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasDot2Insts),
        GIM_CheckIntrinsicID, /*MI*/0, /*Op*/1, GIMT_Encode2(Intrinsic::amdgcn_udot2),
        GIM_CheckType, /*MI*/0, /*Op*/0, /*Type*/GILLT_s32,
        GIM_CheckType, /*MI*/0, /*Op*/2, /*Type*/GILLT_v2s16,
        GIM_CheckType, /*MI*/0, /*Op*/3, /*Type*/GILLT_v2s16,
        GIM_CheckType, /*MI*/0, /*Op*/4, /*Type*/GILLT_s32,
        GIM_CheckRegBankForClass, /*MI*/0, /*Op*/0, /*RC*/GIMT_Encode2(AMDGPU::VGPR_32RegClassID),
        // MIs[0] clamp
        GIM_CheckIsImm, /*MI*/0, /*Op*/5,
        GIM_CheckComplexPattern, /*MI*/0, /*Op*/2, /*Renderer*/GIMT_Encode2(0), GIMT_Encode2(GICP_gi_vop3pmodsdot),
        GIM_CheckComplexPattern, /*MI*/0, /*Op*/3, /*Renderer*/GIMT_Encode2(1), GIMT_Encode2(GICP_gi_vop3pmodsdot),
        GIM_CheckComplexPattern, /*MI*/0, /*Op*/4, /*Renderer*/GIMT_Encode2(2), GIMT_Encode2(GICP_gi_vop3pmodsdot),
        // (intrinsic_wo_chain:{ *:[i32] } 2799:{ *:[iPTR] }, (VOP3PModsDOT:{ *:[v2i16] } v2i16:{ *:[v2i16] }:$src0, i32:{ *:[i32] }:$src0_modifiers), (VOP3PModsDOT:{ *:[v2i16] } v2i16:{ *:[v2i16] }:$src1, i32:{ *:[i32] }:$src1_modifiers), (VOP3PModsDOT:{ *:[i32] } i32:{ *:[i32] }:$src2, i32:{ *:[i32] }:$src2_modifiers), (timm:{ *:[i1] }):$clamp)  =>  (V_DOT2_U32_U16:{ *:[i32] } i32:{ *:[i32] }:$src0_modifiers, v2i16:{ *:[v2i16] }:$src0, i32:{ *:[i32] }:$src1_modifiers, v2i16:{ *:[v2i16] }:$src1, i32:{ *:[i32] }:$src2_modifiers, i32:{ *:[i32] }:$src2, (timm:{ *:[i1] }):$clamp)
        GIR_BuildMI, /*InsnID*/0, /*Opcode*/GIMT_Encode2(AMDGPU::V_DOT2_U32_U16),
        GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/0, // DstI[vdst]
        GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/1, // src0_modifiers
        GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/0, // src0
        GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(1), /*SubOperand*/1, // src1_modifiers
        GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(1), /*SubOperand*/0, // src1
        GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(2), /*SubOperand*/1, // src2_modifiers
        GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(2), /*SubOperand*/0, // src2
        GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/5, // clamp
        GIR_AddImm8, /*InsnID*/0, /*Imm*/0,
        GIR_AddImm8, /*InsnID*/0, /*Imm*/0,
        GIR_AddImm8, /*InsnID*/0, /*Imm*/0,
        GIR_AddImm8, /*InsnID*/0, /*Imm*/0,
        GIR_ConstrainSelectedInstOperands, /*InsnID*/0,
        GIR_EraseFromParent, /*InsnID*/0,
        // GIR_Coverage, 984,
        GIR_Done,
      // Label 3228: @208661
      GIM_Try, /*On fail goto*//*Label 3229*/ GIMT_Encode4(208778), // Rule ID 985 //
        GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasDot10Insts),
        GIM_CheckIntrinsicID, /*MI*/0, /*Op*/1, GIMT_Encode2(Intrinsic::amdgcn_fdot2),
        GIM_CheckType, /*MI*/0, /*Op*/0, /*Type*/GILLT_s32,
        GIM_CheckType, /*MI*/0, /*Op*/2, /*Type*/GILLT_v2s16,
        GIM_CheckType, /*MI*/0, /*Op*/3, /*Type*/GILLT_v2s16,
        GIM_CheckType, /*MI*/0, /*Op*/4, /*Type*/GILLT_s32,
        GIM_CheckRegBankForClass, /*MI*/0, /*Op*/0, /*RC*/GIMT_Encode2(AMDGPU::VGPR_32RegClassID),
        // MIs[0] clamp
        GIM_CheckIsImm, /*MI*/0, /*Op*/5,
        GIM_CheckComplexPattern, /*MI*/0, /*Op*/2, /*Renderer*/GIMT_Encode2(0), GIMT_Encode2(GICP_gi_vop3pmodsdot),
        GIM_CheckComplexPattern, /*MI*/0, /*Op*/3, /*Renderer*/GIMT_Encode2(1), GIMT_Encode2(GICP_gi_vop3pmodsdot),
        GIM_CheckComplexPattern, /*MI*/0, /*Op*/4, /*Renderer*/GIMT_Encode2(2), GIMT_Encode2(GICP_gi_vop3pmodsdot),
        // (intrinsic_wo_chain:{ *:[f32] } 1960:{ *:[iPTR] }, (VOP3PModsDOT:{ *:[v2f16] } v2f16:{ *:[v2f16] }:$src0, i32:{ *:[i32] }:$src0_modifiers), (VOP3PModsDOT:{ *:[v2f16] } v2f16:{ *:[v2f16] }:$src1, i32:{ *:[i32] }:$src1_modifiers), (VOP3PModsDOT:{ *:[f32] } f32:{ *:[f32] }:$src2, i32:{ *:[i32] }:$src2_modifiers), (timm:{ *:[i1] }):$clamp)  =>  (V_DOT2_F32_F16:{ *:[f32] } i32:{ *:[i32] }:$src0_modifiers, v2f16:{ *:[v2f16] }:$src0, i32:{ *:[i32] }:$src1_modifiers, v2f16:{ *:[v2f16] }:$src1, i32:{ *:[i32] }:$src2_modifiers, f32:{ *:[f32] }:$src2, (timm:{ *:[i1] }):$clamp)
        GIR_BuildMI, /*InsnID*/0, /*Opcode*/GIMT_Encode2(AMDGPU::V_DOT2_F32_F16),
        GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/0, // DstI[vdst]
        GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/1, // src0_modifiers
        GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/0, // src0
        GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(1), /*SubOperand*/1, // src1_modifiers
        GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(1), /*SubOperand*/0, // src1
        GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(2), /*SubOperand*/1, // src2_modifiers
        GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(2), /*SubOperand*/0, // src2
        GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/5, // clamp
        GIR_AddImm8, /*InsnID*/0, /*Imm*/0,
        GIR_AddImm8, /*InsnID*/0, /*Imm*/0,
        GIR_AddImm8, /*InsnID*/0, /*Imm*/0,
        GIR_AddImm8, /*InsnID*/0, /*Imm*/0,
        GIR_ConstrainSelectedInstOperands, /*InsnID*/0,
        GIR_EraseFromParent, /*InsnID*/0,
        // GIR_Coverage, 985,
        GIR_Done,
      // Label 3229: @208778
      GIM_Try, /*On fail goto*//*Label 3230*/ GIMT_Encode4(208895), // Rule ID 987 //
        GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasDot7Insts),
        GIM_CheckIntrinsicID, /*MI*/0, /*Op*/1, GIMT_Encode2(Intrinsic::amdgcn_udot4),
        GIM_CheckType, /*MI*/0, /*Op*/0, /*Type*/GILLT_s32,
        GIM_CheckType, /*MI*/0, /*Op*/2, /*Type*/GILLT_s32,
        GIM_CheckType, /*MI*/0, /*Op*/3, /*Type*/GILLT_s32,
        GIM_CheckType, /*MI*/0, /*Op*/4, /*Type*/GILLT_s32,
        GIM_CheckRegBankForClass, /*MI*/0, /*Op*/0, /*RC*/GIMT_Encode2(AMDGPU::VGPR_32RegClassID),
        // MIs[0] clamp
        GIM_CheckIsImm, /*MI*/0, /*Op*/5,
        GIM_CheckComplexPattern, /*MI*/0, /*Op*/2, /*Renderer*/GIMT_Encode2(0), GIMT_Encode2(GICP_gi_vop3pmodsdot),
        GIM_CheckComplexPattern, /*MI*/0, /*Op*/3, /*Renderer*/GIMT_Encode2(1), GIMT_Encode2(GICP_gi_vop3pmodsdot),
        GIM_CheckComplexPattern, /*MI*/0, /*Op*/4, /*Renderer*/GIMT_Encode2(2), GIMT_Encode2(GICP_gi_vop3pmodsdot),
        // (intrinsic_wo_chain:{ *:[i32] } 2800:{ *:[iPTR] }, (VOP3PModsDOT:{ *:[i32] } i32:{ *:[i32] }:$src0, i32:{ *:[i32] }:$src0_modifiers), (VOP3PModsDOT:{ *:[i32] } i32:{ *:[i32] }:$src1, i32:{ *:[i32] }:$src1_modifiers), (VOP3PModsDOT:{ *:[i32] } i32:{ *:[i32] }:$src2, i32:{ *:[i32] }:$src2_modifiers), (timm:{ *:[i1] }):$clamp)  =>  (V_DOT4_U32_U8:{ *:[i32] } i32:{ *:[i32] }:$src0_modifiers, i32:{ *:[i32] }:$src0, i32:{ *:[i32] }:$src1_modifiers, i32:{ *:[i32] }:$src1, i32:{ *:[i32] }:$src2_modifiers, i32:{ *:[i32] }:$src2, (timm:{ *:[i1] }):$clamp)
        GIR_BuildMI, /*InsnID*/0, /*Opcode*/GIMT_Encode2(AMDGPU::V_DOT4_U32_U8),
        GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/0, // DstI[vdst]
        GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/1, // src0_modifiers
        GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/0, // src0
        GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(1), /*SubOperand*/1, // src1_modifiers
        GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(1), /*SubOperand*/0, // src1
        GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(2), /*SubOperand*/1, // src2_modifiers
        GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(2), /*SubOperand*/0, // src2
        GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/5, // clamp
        GIR_AddImm8, /*InsnID*/0, /*Imm*/0,
        GIR_AddImm8, /*InsnID*/0, /*Imm*/0,
        GIR_AddImm8, /*InsnID*/0, /*Imm*/0,
        GIR_AddImm8, /*InsnID*/0, /*Imm*/0,
        GIR_ConstrainSelectedInstOperands, /*InsnID*/0,
        GIR_EraseFromParent, /*InsnID*/0,
        // GIR_Coverage, 987,
        GIR_Done,
      // Label 3230: @208895
      GIM_Try, /*On fail goto*//*Label 3231*/ GIMT_Encode4(209012), // Rule ID 988 //
        GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasDot7Insts),
        GIM_CheckIntrinsicID, /*MI*/0, /*Op*/1, GIMT_Encode2(Intrinsic::amdgcn_udot8),
        GIM_CheckType, /*MI*/0, /*Op*/0, /*Type*/GILLT_s32,
        GIM_CheckType, /*MI*/0, /*Op*/2, /*Type*/GILLT_s32,
        GIM_CheckType, /*MI*/0, /*Op*/3, /*Type*/GILLT_s32,
        GIM_CheckType, /*MI*/0, /*Op*/4, /*Type*/GILLT_s32,
        GIM_CheckRegBankForClass, /*MI*/0, /*Op*/0, /*RC*/GIMT_Encode2(AMDGPU::VGPR_32RegClassID),
        // MIs[0] clamp
        GIM_CheckIsImm, /*MI*/0, /*Op*/5,
        GIM_CheckComplexPattern, /*MI*/0, /*Op*/2, /*Renderer*/GIMT_Encode2(0), GIMT_Encode2(GICP_gi_vop3pmodsdot),
        GIM_CheckComplexPattern, /*MI*/0, /*Op*/3, /*Renderer*/GIMT_Encode2(1), GIMT_Encode2(GICP_gi_vop3pmodsdot),
        GIM_CheckComplexPattern, /*MI*/0, /*Op*/4, /*Renderer*/GIMT_Encode2(2), GIMT_Encode2(GICP_gi_vop3pmodsdot),
        // (intrinsic_wo_chain:{ *:[i32] } 2801:{ *:[iPTR] }, (VOP3PModsDOT:{ *:[i32] } i32:{ *:[i32] }:$src0, i32:{ *:[i32] }:$src0_modifiers), (VOP3PModsDOT:{ *:[i32] } i32:{ *:[i32] }:$src1, i32:{ *:[i32] }:$src1_modifiers), (VOP3PModsDOT:{ *:[i32] } i32:{ *:[i32] }:$src2, i32:{ *:[i32] }:$src2_modifiers), (timm:{ *:[i1] }):$clamp)  =>  (V_DOT8_U32_U4:{ *:[i32] } i32:{ *:[i32] }:$src0_modifiers, i32:{ *:[i32] }:$src0, i32:{ *:[i32] }:$src1_modifiers, i32:{ *:[i32] }:$src1, i32:{ *:[i32] }:$src2_modifiers, i32:{ *:[i32] }:$src2, (timm:{ *:[i1] }):$clamp)
        GIR_BuildMI, /*InsnID*/0, /*Opcode*/GIMT_Encode2(AMDGPU::V_DOT8_U32_U4),
        GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/0, // DstI[vdst]
        GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/1, // src0_modifiers
        GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/0, // src0
        GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(1), /*SubOperand*/1, // src1_modifiers
        GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(1), /*SubOperand*/0, // src1
        GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(2), /*SubOperand*/1, // src2_modifiers
        GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(2), /*SubOperand*/0, // src2
        GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/5, // clamp
        GIR_AddImm8, /*InsnID*/0, /*Imm*/0,
        GIR_AddImm8, /*InsnID*/0, /*Imm*/0,
        GIR_AddImm8, /*InsnID*/0, /*Imm*/0,
        GIR_AddImm8, /*InsnID*/0, /*Imm*/0,
        GIR_ConstrainSelectedInstOperands, /*InsnID*/0,
        GIR_EraseFromParent, /*InsnID*/0,
        // GIR_Coverage, 988,
        GIR_Done,
      // Label 3231: @209012
      GIM_Try, /*On fail goto*//*Label 3232*/ GIMT_Encode4(209129), // Rule ID 989 //
        GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasDot1Insts),
        GIM_CheckIntrinsicID, /*MI*/0, /*Op*/1, GIMT_Encode2(Intrinsic::amdgcn_sdot4),
        GIM_CheckType, /*MI*/0, /*Op*/0, /*Type*/GILLT_s32,
        GIM_CheckType, /*MI*/0, /*Op*/2, /*Type*/GILLT_s32,
        GIM_CheckType, /*MI*/0, /*Op*/3, /*Type*/GILLT_s32,
        GIM_CheckType, /*MI*/0, /*Op*/4, /*Type*/GILLT_s32,
        GIM_CheckRegBankForClass, /*MI*/0, /*Op*/0, /*RC*/GIMT_Encode2(AMDGPU::VGPR_32RegClassID),
        // MIs[0] clamp
        GIM_CheckIsImm, /*MI*/0, /*Op*/5,
        GIM_CheckComplexPattern, /*MI*/0, /*Op*/2, /*Renderer*/GIMT_Encode2(0), GIMT_Encode2(GICP_gi_vop3pmodsdot),
        GIM_CheckComplexPattern, /*MI*/0, /*Op*/3, /*Renderer*/GIMT_Encode2(1), GIMT_Encode2(GICP_gi_vop3pmodsdot),
        GIM_CheckComplexPattern, /*MI*/0, /*Op*/4, /*Renderer*/GIMT_Encode2(2), GIMT_Encode2(GICP_gi_vop3pmodsdot),
        // (intrinsic_wo_chain:{ *:[i32] } 2708:{ *:[iPTR] }, (VOP3PModsDOT:{ *:[i32] } i32:{ *:[i32] }:$src0, i32:{ *:[i32] }:$src0_modifiers), (VOP3PModsDOT:{ *:[i32] } i32:{ *:[i32] }:$src1, i32:{ *:[i32] }:$src1_modifiers), (VOP3PModsDOT:{ *:[i32] } i32:{ *:[i32] }:$src2, i32:{ *:[i32] }:$src2_modifiers), (timm:{ *:[i1] }):$clamp)  =>  (V_DOT4_I32_I8:{ *:[i32] } i32:{ *:[i32] }:$src0_modifiers, i32:{ *:[i32] }:$src0, i32:{ *:[i32] }:$src1_modifiers, i32:{ *:[i32] }:$src1, i32:{ *:[i32] }:$src2_modifiers, i32:{ *:[i32] }:$src2, (timm:{ *:[i1] }):$clamp)
        GIR_BuildMI, /*InsnID*/0, /*Opcode*/GIMT_Encode2(AMDGPU::V_DOT4_I32_I8),
        GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/0, // DstI[vdst]
        GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/1, // src0_modifiers
        GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/0, // src0
        GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(1), /*SubOperand*/1, // src1_modifiers
        GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(1), /*SubOperand*/0, // src1
        GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(2), /*SubOperand*/1, // src2_modifiers
        GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(2), /*SubOperand*/0, // src2
        GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/5, // clamp
        GIR_AddImm8, /*InsnID*/0, /*Imm*/0,
        GIR_AddImm8, /*InsnID*/0, /*Imm*/0,
        GIR_AddImm8, /*InsnID*/0, /*Imm*/0,
        GIR_AddImm8, /*InsnID*/0, /*Imm*/0,
        GIR_ConstrainSelectedInstOperands, /*InsnID*/0,
        GIR_EraseFromParent, /*InsnID*/0,
        // GIR_Coverage, 989,
        GIR_Done,
      // Label 3232: @209129
      GIM_Try, /*On fail goto*//*Label 3233*/ GIMT_Encode4(209246), // Rule ID 990 //
        GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasDot1Insts),
        GIM_CheckIntrinsicID, /*MI*/0, /*Op*/1, GIMT_Encode2(Intrinsic::amdgcn_sdot8),
        GIM_CheckType, /*MI*/0, /*Op*/0, /*Type*/GILLT_s32,
        GIM_CheckType, /*MI*/0, /*Op*/2, /*Type*/GILLT_s32,
        GIM_CheckType, /*MI*/0, /*Op*/3, /*Type*/GILLT_s32,
        GIM_CheckType, /*MI*/0, /*Op*/4, /*Type*/GILLT_s32,
        GIM_CheckRegBankForClass, /*MI*/0, /*Op*/0, /*RC*/GIMT_Encode2(AMDGPU::VGPR_32RegClassID),
        // MIs[0] clamp
        GIM_CheckIsImm, /*MI*/0, /*Op*/5,
        GIM_CheckComplexPattern, /*MI*/0, /*Op*/2, /*Renderer*/GIMT_Encode2(0), GIMT_Encode2(GICP_gi_vop3pmodsdot),
        GIM_CheckComplexPattern, /*MI*/0, /*Op*/3, /*Renderer*/GIMT_Encode2(1), GIMT_Encode2(GICP_gi_vop3pmodsdot),
        GIM_CheckComplexPattern, /*MI*/0, /*Op*/4, /*Renderer*/GIMT_Encode2(2), GIMT_Encode2(GICP_gi_vop3pmodsdot),
        // (intrinsic_wo_chain:{ *:[i32] } 2709:{ *:[iPTR] }, (VOP3PModsDOT:{ *:[i32] } i32:{ *:[i32] }:$src0, i32:{ *:[i32] }:$src0_modifiers), (VOP3PModsDOT:{ *:[i32] } i32:{ *:[i32] }:$src1, i32:{ *:[i32] }:$src1_modifiers), (VOP3PModsDOT:{ *:[i32] } i32:{ *:[i32] }:$src2, i32:{ *:[i32] }:$src2_modifiers), (timm:{ *:[i1] }):$clamp)  =>  (V_DOT8_I32_I4:{ *:[i32] } i32:{ *:[i32] }:$src0_modifiers, i32:{ *:[i32] }:$src0, i32:{ *:[i32] }:$src1_modifiers, i32:{ *:[i32] }:$src1, i32:{ *:[i32] }:$src2_modifiers, i32:{ *:[i32] }:$src2, (timm:{ *:[i1] }):$clamp)
        GIR_BuildMI, /*InsnID*/0, /*Opcode*/GIMT_Encode2(AMDGPU::V_DOT8_I32_I4),
        GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/0, // DstI[vdst]
        GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/1, // src0_modifiers
        GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/0, // src0
        GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(1), /*SubOperand*/1, // src1_modifiers
        GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(1), /*SubOperand*/0, // src1
        GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(2), /*SubOperand*/1, // src2_modifiers
        GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(2), /*SubOperand*/0, // src2
        GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/5, // clamp
        GIR_AddImm8, /*InsnID*/0, /*Imm*/0,
        GIR_AddImm8, /*InsnID*/0, /*Imm*/0,
        GIR_AddImm8, /*InsnID*/0, /*Imm*/0,
        GIR_AddImm8, /*InsnID*/0, /*Imm*/0,
        GIR_ConstrainSelectedInstOperands, /*InsnID*/0,
        GIR_EraseFromParent, /*InsnID*/0,
        // GIR_Coverage, 990,
        GIR_Done,
      // Label 3233: @209246
      GIM_Try, /*On fail goto*//*Label 3234*/ GIMT_Encode4(209363), // Rule ID 991 //
        GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasDot9Insts),
        GIM_CheckIntrinsicID, /*MI*/0, /*Op*/1, GIMT_Encode2(Intrinsic::amdgcn_fdot2_f32_bf16),
        GIM_CheckType, /*MI*/0, /*Op*/0, /*Type*/GILLT_s32,
        GIM_CheckType, /*MI*/0, /*Op*/2, /*Type*/GILLT_v2s16,
        GIM_CheckType, /*MI*/0, /*Op*/3, /*Type*/GILLT_v2s16,
        GIM_CheckType, /*MI*/0, /*Op*/4, /*Type*/GILLT_s32,
        GIM_CheckRegBankForClass, /*MI*/0, /*Op*/0, /*RC*/GIMT_Encode2(AMDGPU::VGPR_32RegClassID),
        // MIs[0] clamp
        GIM_CheckIsImm, /*MI*/0, /*Op*/5,
        GIM_CheckComplexPattern, /*MI*/0, /*Op*/2, /*Renderer*/GIMT_Encode2(0), GIMT_Encode2(GICP_gi_vop3pmodsdot),
        GIM_CheckComplexPattern, /*MI*/0, /*Op*/3, /*Renderer*/GIMT_Encode2(1), GIMT_Encode2(GICP_gi_vop3pmodsdot),
        GIM_CheckComplexPattern, /*MI*/0, /*Op*/4, /*Renderer*/GIMT_Encode2(2), GIMT_Encode2(GICP_gi_vop3pmodsdot),
        // (intrinsic_wo_chain:{ *:[f32] } 1963:{ *:[iPTR] }, (VOP3PModsDOT:{ *:[v2i16] } v2i16:{ *:[v2i16] }:$src0, i32:{ *:[i32] }:$src0_modifiers), (VOP3PModsDOT:{ *:[v2i16] } v2i16:{ *:[v2i16] }:$src1, i32:{ *:[i32] }:$src1_modifiers), (VOP3PModsDOT:{ *:[f32] } f32:{ *:[f32] }:$src2, i32:{ *:[i32] }:$src2_modifiers), (timm:{ *:[i1] }):$clamp)  =>  (V_DOT2_F32_BF16:{ *:[f32] } i32:{ *:[i32] }:$src0_modifiers, v2i16:{ *:[v2i16] }:$src0, i32:{ *:[i32] }:$src1_modifiers, v2i16:{ *:[v2i16] }:$src1, i32:{ *:[i32] }:$src2_modifiers, f32:{ *:[f32] }:$src2, (timm:{ *:[i1] }):$clamp)
        GIR_BuildMI, /*InsnID*/0, /*Opcode*/GIMT_Encode2(AMDGPU::V_DOT2_F32_BF16),
        GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/0, // DstI[vdst]
        GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/1, // src0_modifiers
        GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/0, // src0
        GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(1), /*SubOperand*/1, // src1_modifiers
        GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(1), /*SubOperand*/0, // src1
        GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(2), /*SubOperand*/1, // src2_modifiers
        GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(2), /*SubOperand*/0, // src2
        GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/5, // clamp
        GIR_AddImm8, /*InsnID*/0, /*Imm*/0,
        GIR_AddImm8, /*InsnID*/0, /*Imm*/0,
        GIR_AddImm8, /*InsnID*/0, /*Imm*/0,
        GIR_AddImm8, /*InsnID*/0, /*Imm*/0,
        GIR_ConstrainSelectedInstOperands, /*InsnID*/0,
        GIR_EraseFromParent, /*InsnID*/0,
        // GIR_Coverage, 991,
        GIR_Done,
      // Label 3234: @209363
      GIM_Reject,
    // Label 3197: @209364
    GIM_Try, /*On fail goto*//*Label 3235*/ GIMT_Encode4(209567),
      GIM_CheckNumOperands, /*MI*/0, /*Expected*/7,
      GIM_Try, /*On fail goto*//*Label 3236*/ GIMT_Encode4(209460), // Rule ID 1106 //
        GIM_CheckFeatures, GIMT_Encode2(GIFBS_isNotGFX90APlus),
        GIM_CheckIntrinsicID, /*MI*/0, /*Op*/1, GIMT_Encode2(Intrinsic::amdgcn_interp_p2),
        GIM_CheckType, /*MI*/0, /*Op*/0, /*Type*/GILLT_s32,
        GIM_CheckType, /*MI*/0, /*Op*/2, /*Type*/GILLT_s32,
        GIM_CheckType, /*MI*/0, /*Op*/3, /*Type*/GILLT_s32,
        GIM_CheckType, /*MI*/0, /*Op*/6, /*Type*/GILLT_s32,
        GIM_CheckRegBankForClass, /*MI*/0, /*Op*/0, /*RC*/GIMT_Encode2(AMDGPU::VGPR_32RegClassID),
        // MIs[0] attrchan
        GIM_CheckIsImm, /*MI*/0, /*Op*/4,
        // MIs[0] attr
        GIM_CheckIsImm, /*MI*/0, /*Op*/5,
        GIM_CheckRegBankForClass, /*MI*/0, /*Op*/6, /*RC*/GIMT_Encode2(AMDGPU::M0_CLASSRegClassID),
        // (intrinsic_wo_chain:{ *:[f32] } 2522:{ *:[iPTR] }, f32:{ *:[f32] }:$src0, f32:{ *:[f32] }:$vsrc, (timm:{ *:[i32] }):$attrchan, (timm:{ *:[i32] }):$attr, M0:{ *:[i32] })  =>  (V_INTERP_P2_F32:{ *:[f32] } f32:{ *:[f32] }:$src0, f32:{ *:[f32] }:$vsrc, (timm:{ *:[i32] }):$attr, (timm:{ *:[i32] }):$attrchan)
        GIR_BuildMI, /*InsnID*/1, /*Opcode*/GIMT_Encode2(TargetOpcode::COPY),
        GIR_AddRegister, /*InsnID*/1, GIMT_Encode2(AMDGPU::M0), /*AddRegisterRegFlags*/GIMT_Encode2(RegState::Define),
        GIR_Copy, /*NewInsnID*/1, /*OldInsnID*/0, /*OpIdx*/6, // M0
        GIR_BuildMI, /*InsnID*/0, /*Opcode*/GIMT_Encode2(AMDGPU::V_INTERP_P2_F32),
        GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/0, // DstI[vdst]
        GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/2, // src0
        GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/3, // vsrc
        GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/5, // attr
        GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/4, // attrchan
        GIR_ConstrainSelectedInstOperands, /*InsnID*/0,
        GIR_EraseFromParent, /*InsnID*/0,
        // GIR_Coverage, 1106,
        GIR_Done,
      // Label 3236: @209460
      GIM_Try, /*On fail goto*//*Label 3237*/ GIMT_Encode4(209566), // Rule ID 931 //
        GIM_CheckFeatures, GIMT_Encode2(GIFBS_Has16BitInsts_has32BankLDS_isNotGFX90APlus),
        GIM_CheckIntrinsicID, /*MI*/0, /*Op*/1, GIMT_Encode2(Intrinsic::amdgcn_interp_p1_f16),
        GIM_CheckType, /*MI*/0, /*Op*/0, /*Type*/GILLT_s32,
        GIM_CheckType, /*MI*/0, /*Op*/2, /*Type*/GILLT_s32,
        GIM_CheckType, /*MI*/0, /*Op*/6, /*Type*/GILLT_s32,
        GIM_CheckRegBankForClass, /*MI*/0, /*Op*/0, /*RC*/GIMT_Encode2(AMDGPU::VGPR_32RegClassID),
        // MIs[0] attrchan
        GIM_CheckIsImm, /*MI*/0, /*Op*/3,
        // MIs[0] attr
        GIM_CheckIsImm, /*MI*/0, /*Op*/4,
        // MIs[0] high
        GIM_CheckIsImm, /*MI*/0, /*Op*/5,
        GIM_CheckRegBankForClass, /*MI*/0, /*Op*/6, /*RC*/GIMT_Encode2(AMDGPU::M0_CLASSRegClassID),
        GIM_CheckComplexPattern, /*MI*/0, /*Op*/2, /*Renderer*/GIMT_Encode2(0), GIMT_Encode2(GICP_gi_vop3mods),
        // (intrinsic_wo_chain:{ *:[f32] } 2521:{ *:[iPTR] }, (VOP3Mods:{ *:[f32] } f32:{ *:[f32] }:$src0, i32:{ *:[i32] }:$src0_modifiers), (timm:{ *:[i32] }):$attrchan, (timm:{ *:[i32] }):$attr, (timm:{ *:[i1] }):$high, M0:{ *:[i32] })  =>  (V_INTERP_P1LL_F16:{ *:[f32] } i32:{ *:[i32] }:$src0_modifiers, f32:{ *:[f32] }:$src0, (timm:{ *:[i32] }):$attr, (timm:{ *:[i32] }):$attrchan, (timm:{ *:[i1] }):$high)
        GIR_BuildMI, /*InsnID*/1, /*Opcode*/GIMT_Encode2(TargetOpcode::COPY),
        GIR_AddRegister, /*InsnID*/1, GIMT_Encode2(AMDGPU::M0), /*AddRegisterRegFlags*/GIMT_Encode2(RegState::Define),
        GIR_Copy, /*NewInsnID*/1, /*OldInsnID*/0, /*OpIdx*/6, // M0
        GIR_BuildMI, /*InsnID*/0, /*Opcode*/GIMT_Encode2(AMDGPU::V_INTERP_P1LL_F16),
        GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/0, // DstI[vdst]
        GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/1, // src0_modifiers
        GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/0, // src0
        GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/4, // attr
        GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/3, // attrchan
        GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/5, // high
        GIR_AddImm8, /*InsnID*/0, /*Imm*/0,
        GIR_AddImm8, /*InsnID*/0, /*Imm*/0,
        GIR_ConstrainSelectedInstOperands, /*InsnID*/0,
        GIR_EraseFromParent, /*InsnID*/0,
        // GIR_Coverage, 931,
        GIR_Done,
      // Label 3237: @209566
      GIM_Reject,
    // Label 3235: @209567
    GIM_Try, /*On fail goto*//*Label 3238*/ GIMT_Encode4(209910),
      GIM_CheckNumOperands, /*MI*/0, /*Expected*/8,
      GIM_Try, /*On fail goto*//*Label 3239*/ GIMT_Encode4(209680), // Rule ID 2267 //
        GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasDot8Insts),
        GIM_CheckIntrinsicID, /*MI*/0, /*Op*/1, GIMT_Encode2(Intrinsic::amdgcn_sudot4),
        GIM_CheckType, /*MI*/0, /*Op*/0, /*Type*/GILLT_s32,
        GIM_CheckType, /*MI*/0, /*Op*/3, /*Type*/GILLT_s32,
        GIM_CheckType, /*MI*/0, /*Op*/5, /*Type*/GILLT_s32,
        GIM_CheckType, /*MI*/0, /*Op*/6, /*Type*/GILLT_s32,
        GIM_CheckRegBankForClass, /*MI*/0, /*Op*/0, /*RC*/GIMT_Encode2(AMDGPU::VGPR_32RegClassID),
        // MIs[0] clamp
        GIM_CheckIsImm, /*MI*/0, /*Op*/7,
        GIM_CheckComplexPattern, /*MI*/0, /*Op*/2, /*Renderer*/GIMT_Encode2(0), GIMT_Encode2(GICP_gi_vop3pmodsneg),
        GIM_CheckComplexPattern, /*MI*/0, /*Op*/4, /*Renderer*/GIMT_Encode2(1), GIMT_Encode2(GICP_gi_vop3pmodsneg),
        // (intrinsic_wo_chain:{ *:[i32] } 2782:{ *:[iPTR] }, (VOP3PModsNeg:{ *:[i1] } i32:{ *:[i32] }:$src0_mods), i32:{ *:[i32] }:$src0, (VOP3PModsNeg:{ *:[i1] } i32:{ *:[i32] }:$src1_mods), i32:{ *:[i32] }:$src1, i32:{ *:[i32] }:$src2, (timm:{ *:[i1] }):$clamp)  =>  (V_DOT4_I32_IU8:{ *:[i32] } ?:{ *:[i32] }:$src0_mods, i32:{ *:[i32] }:$src0, ?:{ *:[i32] }:$src1_mods, i32:{ *:[i32] }:$src1, 8:{ *:[i32] }, i32:{ *:[i32] }:$src2, i1:{ *:[i1] }:$clamp)
        GIR_BuildMI, /*InsnID*/0, /*Opcode*/GIMT_Encode2(AMDGPU::V_DOT4_I32_IU8),
        GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/0, // DstI[vdst]
        GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/0, // src0_mods
        GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/3, // src0
        GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(1), /*SubOperand*/0, // src1_mods
        GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/5, // src1
        GIR_AddImm8, /*InsnID*/0, /*Imm*/8,
        GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/6, // src2
        GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/7, // clamp
        GIR_AddImm8, /*InsnID*/0, /*Imm*/0,
        GIR_AddImm8, /*InsnID*/0, /*Imm*/0,
        GIR_AddImm8, /*InsnID*/0, /*Imm*/0,
        GIR_AddImm8, /*InsnID*/0, /*Imm*/0,
        GIR_ConstrainSelectedInstOperands, /*InsnID*/0,
        GIR_EraseFromParent, /*InsnID*/0,
        // GIR_Coverage, 2267,
        GIR_Done,
      // Label 3239: @209680
      GIM_Try, /*On fail goto*//*Label 3240*/ GIMT_Encode4(209785), // Rule ID 2268 //
        GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasDot8Insts),
        GIM_CheckIntrinsicID, /*MI*/0, /*Op*/1, GIMT_Encode2(Intrinsic::amdgcn_sudot8),
        GIM_CheckType, /*MI*/0, /*Op*/0, /*Type*/GILLT_s32,
        GIM_CheckType, /*MI*/0, /*Op*/3, /*Type*/GILLT_s32,
        GIM_CheckType, /*MI*/0, /*Op*/5, /*Type*/GILLT_s32,
        GIM_CheckType, /*MI*/0, /*Op*/6, /*Type*/GILLT_s32,
        GIM_CheckRegBankForClass, /*MI*/0, /*Op*/0, /*RC*/GIMT_Encode2(AMDGPU::VGPR_32RegClassID),
        // MIs[0] clamp
        GIM_CheckIsImm, /*MI*/0, /*Op*/7,
        GIM_CheckComplexPattern, /*MI*/0, /*Op*/2, /*Renderer*/GIMT_Encode2(0), GIMT_Encode2(GICP_gi_vop3pmodsneg),
        GIM_CheckComplexPattern, /*MI*/0, /*Op*/4, /*Renderer*/GIMT_Encode2(1), GIMT_Encode2(GICP_gi_vop3pmodsneg),
        // (intrinsic_wo_chain:{ *:[i32] } 2783:{ *:[iPTR] }, (VOP3PModsNeg:{ *:[i1] } i32:{ *:[i32] }:$src0_mods), i32:{ *:[i32] }:$src0, (VOP3PModsNeg:{ *:[i1] } i32:{ *:[i32] }:$src1_mods), i32:{ *:[i32] }:$src1, i32:{ *:[i32] }:$src2, (timm:{ *:[i1] }):$clamp)  =>  (V_DOT8_I32_IU4:{ *:[i32] } ?:{ *:[i32] }:$src0_mods, i32:{ *:[i32] }:$src0, ?:{ *:[i32] }:$src1_mods, i32:{ *:[i32] }:$src1, 8:{ *:[i32] }, i32:{ *:[i32] }:$src2, i1:{ *:[i1] }:$clamp)
        GIR_BuildMI, /*InsnID*/0, /*Opcode*/GIMT_Encode2(AMDGPU::V_DOT8_I32_IU4),
        GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/0, // DstI[vdst]
        GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/0, // src0_mods
        GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/3, // src0
        GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(1), /*SubOperand*/0, // src1_mods
        GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/5, // src1
        GIR_AddImm8, /*InsnID*/0, /*Imm*/8,
        GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/6, // src2
        GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/7, // clamp
        GIR_AddImm8, /*InsnID*/0, /*Imm*/0,
        GIR_AddImm8, /*InsnID*/0, /*Imm*/0,
        GIR_AddImm8, /*InsnID*/0, /*Imm*/0,
        GIR_AddImm8, /*InsnID*/0, /*Imm*/0,
        GIR_ConstrainSelectedInstOperands, /*InsnID*/0,
        GIR_EraseFromParent, /*InsnID*/0,
        // GIR_Coverage, 2268,
        GIR_Done,
      // Label 3240: @209785
      GIM_Try, /*On fail goto*//*Label 3241*/ GIMT_Encode4(209909), // Rule ID 930 //
        GIM_CheckFeatures, GIMT_Encode2(GIFBS_Has16BitInsts_isNotGFX90APlus),
        GIM_CheckIntrinsicID, /*MI*/0, /*Op*/1, GIMT_Encode2(Intrinsic::amdgcn_interp_p2_f16),
        GIM_CheckType, /*MI*/0, /*Op*/0, /*Type*/GILLT_s16,
        GIM_CheckType, /*MI*/0, /*Op*/2, /*Type*/GILLT_s32,
        GIM_CheckType, /*MI*/0, /*Op*/3, /*Type*/GILLT_s32,
        GIM_CheckType, /*MI*/0, /*Op*/7, /*Type*/GILLT_s32,
        GIM_CheckRegBankForClass, /*MI*/0, /*Op*/0, /*RC*/GIMT_Encode2(AMDGPU::VGPR_32RegClassID),
        // MIs[0] attrchan
        GIM_CheckIsImm, /*MI*/0, /*Op*/4,
        // MIs[0] attr
        GIM_CheckIsImm, /*MI*/0, /*Op*/5,
        // MIs[0] high
        GIM_CheckIsImm, /*MI*/0, /*Op*/6,
        GIM_CheckRegBankForClass, /*MI*/0, /*Op*/7, /*RC*/GIMT_Encode2(AMDGPU::M0_CLASSRegClassID),
        GIM_CheckComplexPattern, /*MI*/0, /*Op*/2, /*Renderer*/GIMT_Encode2(0), GIMT_Encode2(GICP_gi_vop3mods),
        GIM_CheckComplexPattern, /*MI*/0, /*Op*/3, /*Renderer*/GIMT_Encode2(1), GIMT_Encode2(GICP_gi_vop3mods),
        // (intrinsic_wo_chain:{ *:[f16] } 2523:{ *:[iPTR] }, (VOP3Mods:{ *:[f32] } f32:{ *:[f32] }:$src2, i32:{ *:[i32] }:$src2_modifiers), (VOP3Mods:{ *:[f32] } f32:{ *:[f32] }:$src0, i32:{ *:[i32] }:$src0_modifiers), (timm:{ *:[i32] }):$attrchan, (timm:{ *:[i32] }):$attr, (timm:{ *:[i1] }):$high, M0:{ *:[i32] })  =>  (V_INTERP_P2_F16:{ *:[f16] } i32:{ *:[i32] }:$src0_modifiers, f32:{ *:[f32] }:$src0, (timm:{ *:[i32] }):$attr, (timm:{ *:[i32] }):$attrchan, i32:{ *:[i32] }:$src2_modifiers, f32:{ *:[f32] }:$src2, (timm:{ *:[i1] }):$high)
        GIR_BuildMI, /*InsnID*/1, /*Opcode*/GIMT_Encode2(TargetOpcode::COPY),
        GIR_AddRegister, /*InsnID*/1, GIMT_Encode2(AMDGPU::M0), /*AddRegisterRegFlags*/GIMT_Encode2(RegState::Define),
        GIR_Copy, /*NewInsnID*/1, /*OldInsnID*/0, /*OpIdx*/7, // M0
        GIR_BuildMI, /*InsnID*/0, /*Opcode*/GIMT_Encode2(AMDGPU::V_INTERP_P2_F16),
        GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/0, // DstI[vdst]
        GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(1), /*SubOperand*/1, // src0_modifiers
        GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(1), /*SubOperand*/0, // src0
        GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/5, // attr
        GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/4, // attrchan
        GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/1, // src2_modifiers
        GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/0, // src2
        GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/6, // high
        GIR_AddImm8, /*InsnID*/0, /*Imm*/0,
        GIR_ConstrainSelectedInstOperands, /*InsnID*/0,
        GIR_EraseFromParent, /*InsnID*/0,
        // GIR_Coverage, 930,
        GIR_Done,
      // Label 3241: @209909
      GIM_Reject,
    // Label 3238: @209910
    GIM_Reject,
    // Label 33: @209911
    GIM_Try, /*On fail goto*//*Label 3242*/ GIMT_Encode4(210121),
      GIM_CheckNumOperands, /*MI*/0, /*Expected*/1,
      GIM_Try, /*On fail goto*//*Label 3243*/ GIMT_Encode4(209938), // Rule ID 1091 //
        GIM_CheckIntrinsicID, /*MI*/0, /*Op*/0, GIMT_Encode2(Intrinsic::amdgcn_s_dcache_inv),
        // (intrinsic_void 2666:{ *:[iPTR] })  =>  (S_DCACHE_INV)
        GIR_BuildMI, /*InsnID*/0, /*Opcode*/GIMT_Encode2(AMDGPU::S_DCACHE_INV),
        GIR_ConstrainSelectedInstOperands, /*InsnID*/0,
        GIR_EraseFromParent, /*InsnID*/0,
        // GIR_Coverage, 1091,
        GIR_Done,
      // Label 3243: @209938
      GIM_Try, /*On fail goto*//*Label 3244*/ GIMT_Encode4(209960), // Rule ID 1092 //
        GIM_CheckFeatures, GIMT_Encode2(GIFBS_isGFX7GFX8GFX9),
        GIM_CheckIntrinsicID, /*MI*/0, /*Op*/0, GIMT_Encode2(Intrinsic::amdgcn_s_dcache_inv_vol),
        // (intrinsic_void 2667:{ *:[iPTR] })  =>  (S_DCACHE_INV_VOL)
        GIR_BuildMI, /*InsnID*/0, /*Opcode*/GIMT_Encode2(AMDGPU::S_DCACHE_INV_VOL),
        GIR_ConstrainSelectedInstOperands, /*InsnID*/0,
        GIR_EraseFromParent, /*InsnID*/0,
        // GIR_Coverage, 1092,
        GIR_Done,
      // Label 3244: @209960
      GIM_Try, /*On fail goto*//*Label 3245*/ GIMT_Encode4(209982), // Rule ID 1093 //
        GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasScalarStores_isGFX8Plus),
        GIM_CheckIntrinsicID, /*MI*/0, /*Op*/0, GIMT_Encode2(Intrinsic::amdgcn_s_dcache_wb),
        // (intrinsic_void 2668:{ *:[iPTR] })  =>  (S_DCACHE_WB)
        GIR_BuildMI, /*InsnID*/0, /*Opcode*/GIMT_Encode2(AMDGPU::S_DCACHE_WB),
        GIR_ConstrainSelectedInstOperands, /*InsnID*/0,
        GIR_EraseFromParent, /*InsnID*/0,
        // GIR_Coverage, 1093,
        GIR_Done,
      // Label 3245: @209982
      GIM_Try, /*On fail goto*//*Label 3246*/ GIMT_Encode4(210004), // Rule ID 1094 //
        GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasScalarStores_isGFX8Plus),
        GIM_CheckIntrinsicID, /*MI*/0, /*Op*/0, GIMT_Encode2(Intrinsic::amdgcn_s_dcache_wb_vol),
        // (intrinsic_void 2669:{ *:[iPTR] })  =>  (S_DCACHE_WB_VOL)
        GIR_BuildMI, /*InsnID*/0, /*Opcode*/GIMT_Encode2(AMDGPU::S_DCACHE_WB_VOL),
        GIR_ConstrainSelectedInstOperands, /*InsnID*/0,
        GIR_EraseFromParent, /*InsnID*/0,
        // GIR_Coverage, 1094,
        GIR_Done,
      // Label 3246: @210004
      GIM_Try, /*On fail goto*//*Label 3247*/ GIMT_Encode4(210026), // Rule ID 1101 //
        GIM_CheckFeatures, GIMT_Encode2(GIFBS_isGFX6),
        GIM_CheckIntrinsicID, /*MI*/0, /*Op*/0, GIMT_Encode2(Intrinsic::amdgcn_buffer_wbinvl1_sc),
        // (intrinsic_void 1899:{ *:[iPTR] })  =>  (BUFFER_WBINVL1_SC)
        GIR_BuildMI, /*InsnID*/0, /*Opcode*/GIMT_Encode2(AMDGPU::BUFFER_WBINVL1_SC),
        GIR_ConstrainSelectedInstOperands, /*InsnID*/0,
        GIR_EraseFromParent, /*InsnID*/0,
        // GIR_Coverage, 1101,
        GIR_Done,
      // Label 3247: @210026
      GIM_Try, /*On fail goto*//*Label 3248*/ GIMT_Encode4(210048), // Rule ID 1102 //
        GIM_CheckFeatures, GIMT_Encode2(GIFBS_isNotGFX12Plus),
        GIM_CheckIntrinsicID, /*MI*/0, /*Op*/0, GIMT_Encode2(Intrinsic::amdgcn_buffer_wbinvl1),
        // (intrinsic_void 1898:{ *:[iPTR] })  =>  (BUFFER_WBINVL1)
        GIR_BuildMI, /*InsnID*/0, /*Opcode*/GIMT_Encode2(AMDGPU::BUFFER_WBINVL1),
        GIR_ConstrainSelectedInstOperands, /*InsnID*/0,
        GIR_EraseFromParent, /*InsnID*/0,
        // GIR_Coverage, 1102,
        GIR_Done,
      // Label 3248: @210048
      GIM_Try, /*On fail goto*//*Label 3249*/ GIMT_Encode4(210070), // Rule ID 1103 //
        GIM_CheckFeatures, GIMT_Encode2(GIFBS_isGFX7Plus),
        GIM_CheckIntrinsicID, /*MI*/0, /*Op*/0, GIMT_Encode2(Intrinsic::amdgcn_buffer_wbinvl1_vol),
        // (intrinsic_void 1900:{ *:[iPTR] })  =>  (BUFFER_WBINVL1_VOL)
        GIR_BuildMI, /*InsnID*/0, /*Opcode*/GIMT_Encode2(AMDGPU::BUFFER_WBINVL1_VOL),
        GIR_ConstrainSelectedInstOperands, /*InsnID*/0,
        GIR_EraseFromParent, /*InsnID*/0,
        // GIR_Coverage, 1103,
        GIR_Done,
      // Label 3249: @210070
      GIM_Try, /*On fail goto*//*Label 3250*/ GIMT_Encode4(210095), // Rule ID 1648 //
        GIM_CheckFeatures, GIMT_Encode2(GIFBS_isNotGFX12Plus),
        GIM_CheckIntrinsicID, /*MI*/0, /*Op*/0, GIMT_Encode2(Intrinsic::amdgcn_s_wait_event_export_ready),
        // (intrinsic_void 2692:{ *:[iPTR] })  =>  (S_WAIT_EVENT 0:{ *:[i16] })
        GIR_BuildMI, /*InsnID*/0, /*Opcode*/GIMT_Encode2(AMDGPU::S_WAIT_EVENT),
        GIR_AddImm8, /*InsnID*/0, /*Imm*/0,
        GIR_ConstrainSelectedInstOperands, /*InsnID*/0,
        GIR_EraseFromParent, /*InsnID*/0,
        // GIR_Coverage, 1648,
        GIR_Done,
      // Label 3250: @210095
      GIM_Try, /*On fail goto*//*Label 3251*/ GIMT_Encode4(210120), // Rule ID 1649 //
        GIM_CheckFeatures, GIMT_Encode2(GIFBS_isGFX12Plus),
        GIM_CheckIntrinsicID, /*MI*/0, /*Op*/0, GIMT_Encode2(Intrinsic::amdgcn_s_wait_event_export_ready),
        // (intrinsic_void 2692:{ *:[iPTR] })  =>  (S_WAIT_EVENT 2:{ *:[i16] })
        GIR_BuildMI, /*InsnID*/0, /*Opcode*/GIMT_Encode2(AMDGPU::S_WAIT_EVENT),
        GIR_AddImm8, /*InsnID*/0, /*Imm*/2,
        GIR_ConstrainSelectedInstOperands, /*InsnID*/0,
        GIR_EraseFromParent, /*InsnID*/0,
        // GIR_Coverage, 1649,
        GIR_Done,
      // Label 3251: @210120
      GIM_Reject,
    // Label 3242: @210121
    GIM_Try, /*On fail goto*//*Label 3252*/ GIMT_Encode4(210953),
      GIM_CheckNumOperands, /*MI*/0, /*Expected*/2,
      GIM_Try, /*On fail goto*//*Label 3253*/ GIMT_Encode4(210189), // Rule ID 5852 //
        GIM_CheckIntrinsicID, /*MI*/0, /*Op*/0, GIMT_Encode2(Intrinsic::amdgcn_kill),
        GIM_CheckType, /*MI*/0, /*Op*/1, /*Type*/GILLT_s1,
        GIM_RecordInsn, /*DefineMI*/1, /*MI*/0, /*OpIdx*/1, // MIs[1]
        GIM_CheckOpcode, /*MI*/1, GIMT_Encode2(TargetOpcode::G_XOR),
        GIM_CheckType, /*MI*/1, /*Op*/1, /*Type*/GILLT_s1,
        GIM_CheckType, /*MI*/1, /*Op*/2, /*Type*/GILLT_s1,
        GIM_CheckConstantInt8, /*MI*/1, /*Op*/2, uint8_t(-1),
        GIM_CheckIsSafeToFold, /*InsnID*/1,
        // (intrinsic_void 2528:{ *:[iPTR] }, (xor:{ *:[i1] } i1:{ *:[i1] }:$src, -1:{ *:[i1] }))  =>  (SI_KILL_I1_PSEUDO SCSrc_i1:{ *:[i1] }:$src, -1:{ *:[i1] })
        GIR_BuildMI, /*InsnID*/0, /*Opcode*/GIMT_Encode2(AMDGPU::SI_KILL_I1_PSEUDO),
        GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/1, /*OpIdx*/1, // src
        GIR_AddImm8, /*InsnID*/0, /*Imm*/uint8_t(-1),
        GIR_SetImplicitDefDead, /*InsnID*/0, /*OpIdx for AMDGPU::SCC*/1,
        GIR_MergeMemOperands, /*InsnID*/0, /*NumInsns*/2, /*MergeInsnID's*/0, 1,
        GIR_ConstrainSelectedInstOperands, /*InsnID*/0,
        GIR_EraseFromParent, /*InsnID*/0,
        // GIR_Coverage, 5852,
        GIR_Done,
      // Label 3253: @210189
      GIM_Try, /*On fail goto*//*Label 3254*/ GIMT_Encode4(210249), // Rule ID 5855 //
        GIM_CheckIntrinsicID, /*MI*/0, /*Op*/0, GIMT_Encode2(Intrinsic::amdgcn_wqm_demote),
        GIM_CheckType, /*MI*/0, /*Op*/1, /*Type*/GILLT_s1,
        GIM_RecordInsn, /*DefineMI*/1, /*MI*/0, /*OpIdx*/1, // MIs[1]
        GIM_CheckOpcode, /*MI*/1, GIMT_Encode2(TargetOpcode::G_XOR),
        GIM_CheckType, /*MI*/1, /*Op*/1, /*Type*/GILLT_s1,
        GIM_CheckType, /*MI*/1, /*Op*/2, /*Type*/GILLT_s1,
        GIM_CheckConstantInt8, /*MI*/1, /*Op*/2, uint8_t(-1),
        GIM_CheckIsSafeToFold, /*InsnID*/1,
        // (intrinsic_void 2829:{ *:[iPTR] }, (xor:{ *:[i1] } i1:{ *:[i1] }:$src, -1:{ *:[i1] }))  =>  (SI_DEMOTE_I1 SCSrc_i1:{ *:[i1] }:$src, -1:{ *:[i1] })
        GIR_BuildMI, /*InsnID*/0, /*Opcode*/GIMT_Encode2(AMDGPU::SI_DEMOTE_I1),
        GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/1, /*OpIdx*/1, // src
        GIR_AddImm8, /*InsnID*/0, /*Imm*/uint8_t(-1),
        GIR_SetImplicitDefDead, /*InsnID*/0, /*OpIdx for AMDGPU::SCC*/1,
        GIR_MergeMemOperands, /*InsnID*/0, /*NumInsns*/2, /*MergeInsnID's*/0, 1,
        GIR_ConstrainSelectedInstOperands, /*InsnID*/0,
        GIR_EraseFromParent, /*InsnID*/0,
        // GIR_Coverage, 5855,
        GIR_Done,
      // Label 3254: @210249
      GIM_Try, /*On fail goto*//*Label 3255*/ GIMT_Encode4(210275), // Rule ID 180 //
        GIM_CheckIntrinsicID, /*MI*/0, /*Op*/0, GIMT_Encode2(Intrinsic::amdgcn_s_nop),
        // MIs[0] simm16
        GIM_CheckIsImm, /*MI*/0, /*Op*/1,
        // (intrinsic_void 2678:{ *:[iPTR] }, (timm:{ *:[i16] }):$simm16)  =>  (S_NOP (timm:{ *:[i16] }):$simm16)
        GIR_BuildMI, /*InsnID*/0, /*Opcode*/GIMT_Encode2(AMDGPU::S_NOP),
        GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/1, // simm16
        GIR_ConstrainSelectedInstOperands, /*InsnID*/0,
        GIR_EraseFromParent, /*InsnID*/0,
        // GIR_Coverage, 180,
        GIR_Done,
      // Label 3255: @210275
      GIM_Try, /*On fail goto*//*Label 3256*/ GIMT_Encode4(210301), // Rule ID 186 //
        GIM_CheckIntrinsicID, /*MI*/0, /*Op*/0, GIMT_Encode2(Intrinsic::amdgcn_s_waitcnt),
        // MIs[0] simm16
        GIM_CheckIsImm, /*MI*/0, /*Op*/1,
        // (intrinsic_void 2698:{ *:[iPTR] }, (timm:{ *:[i32] }):$simm16)  =>  (S_WAITCNT (timm:{ *:[i32] }):$simm16)
        GIR_BuildMI, /*InsnID*/0, /*Opcode*/GIMT_Encode2(AMDGPU::S_WAITCNT),
        GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/1, // simm16
        GIR_ConstrainSelectedInstOperands, /*InsnID*/0,
        GIR_EraseFromParent, /*InsnID*/0,
        // GIR_Coverage, 186,
        GIR_Done,
      // Label 3256: @210301
      GIM_Try, /*On fail goto*//*Label 3257*/ GIMT_Encode4(210327), // Rule ID 187 //
        GIM_CheckIntrinsicID, /*MI*/0, /*Op*/0, GIMT_Encode2(Intrinsic::amdgcn_s_sethalt),
        // MIs[0] simm16
        GIM_CheckIsImm, /*MI*/0, /*Op*/1,
        // (intrinsic_void 2683:{ *:[iPTR] }, (timm:{ *:[i32] }):$simm16)  =>  (S_SETHALT (timm:{ *:[i32] }):$simm16)
        GIR_BuildMI, /*InsnID*/0, /*Opcode*/GIMT_Encode2(AMDGPU::S_SETHALT),
        GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/1, // simm16
        GIR_ConstrainSelectedInstOperands, /*InsnID*/0,
        GIR_EraseFromParent, /*InsnID*/0,
        // GIR_Coverage, 187,
        GIR_Done,
      // Label 3257: @210327
      GIM_Try, /*On fail goto*//*Label 3258*/ GIMT_Encode4(210353), // Rule ID 188 //
        GIM_CheckIntrinsicID, /*MI*/0, /*Op*/0, GIMT_Encode2(Intrinsic::amdgcn_s_sleep),
        // MIs[0] simm16
        GIM_CheckIsImm, /*MI*/0, /*Op*/1,
        // (intrinsic_void 2686:{ *:[iPTR] }, (timm:{ *:[i32] }):$simm16)  =>  (S_SLEEP (timm:{ *:[i32] }):$simm16)
        GIR_BuildMI, /*InsnID*/0, /*Opcode*/GIMT_Encode2(AMDGPU::S_SLEEP),
        GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/1, // simm16
        GIR_ConstrainSelectedInstOperands, /*InsnID*/0,
        GIR_EraseFromParent, /*InsnID*/0,
        // GIR_Coverage, 188,
        GIR_Done,
      // Label 3258: @210353
      GIM_Try, /*On fail goto*//*Label 3259*/ GIMT_Encode4(210379), // Rule ID 190 //
        GIM_CheckIntrinsicID, /*MI*/0, /*Op*/0, GIMT_Encode2(Intrinsic::amdgcn_s_setprio),
        // MIs[0] simm16
        GIM_CheckIsImm, /*MI*/0, /*Op*/1,
        // (intrinsic_void 2684:{ *:[iPTR] }, (timm:{ *:[i16] }):$simm16)  =>  (S_SETPRIO (timm:{ *:[i16] }):$simm16)
        GIR_BuildMI, /*InsnID*/0, /*Opcode*/GIMT_Encode2(AMDGPU::S_SETPRIO),
        GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/1, // simm16
        GIR_ConstrainSelectedInstOperands, /*InsnID*/0,
        GIR_EraseFromParent, /*InsnID*/0,
        // GIR_Coverage, 190,
        GIR_Done,
      // Label 3259: @210379
      GIM_Try, /*On fail goto*//*Label 3260*/ GIMT_Encode4(210405), // Rule ID 193 //
        GIM_CheckIntrinsicID, /*MI*/0, /*Op*/0, GIMT_Encode2(Intrinsic::amdgcn_s_incperflevel),
        // MIs[0] simm16
        GIM_CheckIsImm, /*MI*/0, /*Op*/1,
        // (intrinsic_void 2675:{ *:[iPTR] }, (timm:{ *:[i32] }):$simm16)  =>  (S_INCPERFLEVEL (timm:{ *:[i32] }):$simm16)
        GIR_BuildMI, /*InsnID*/0, /*Opcode*/GIMT_Encode2(AMDGPU::S_INCPERFLEVEL),
        GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/1, // simm16
        GIR_ConstrainSelectedInstOperands, /*InsnID*/0,
        GIR_EraseFromParent, /*InsnID*/0,
        // GIR_Coverage, 193,
        GIR_Done,
      // Label 3260: @210405
      GIM_Try, /*On fail goto*//*Label 3261*/ GIMT_Encode4(210431), // Rule ID 194 //
        GIM_CheckIntrinsicID, /*MI*/0, /*Op*/0, GIMT_Encode2(Intrinsic::amdgcn_s_decperflevel),
        // MIs[0] simm16
        GIM_CheckIsImm, /*MI*/0, /*Op*/1,
        // (intrinsic_void 2670:{ *:[iPTR] }, (timm:{ *:[i32] }):$simm16)  =>  (S_DECPERFLEVEL (timm:{ *:[i32] }):$simm16)
        GIR_BuildMI, /*InsnID*/0, /*Opcode*/GIMT_Encode2(AMDGPU::S_DECPERFLEVEL),
        GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/1, // simm16
        GIR_ConstrainSelectedInstOperands, /*InsnID*/0,
        GIR_EraseFromParent, /*InsnID*/0,
        // GIR_Coverage, 194,
        GIR_Done,
      // Label 3261: @210431
      GIM_Try, /*On fail goto*//*Label 3262*/ GIMT_Encode4(210460), // Rule ID 197 //
        GIM_CheckFeatures, GIMT_Encode2(GIFBS_isGFX10Plus),
        GIM_CheckIntrinsicID, /*MI*/0, /*Op*/0, GIMT_Encode2(Intrinsic::amdgcn_s_ttracedata_imm),
        // MIs[0] simm16
        GIM_CheckIsImm, /*MI*/0, /*Op*/1,
        // (intrinsic_void 2689:{ *:[iPTR] }, (timm:{ *:[i16] }):$simm16)  =>  (S_TTRACEDATA_IMM (timm:{ *:[i16] }):$simm16)
        GIR_BuildMI, /*InsnID*/0, /*Opcode*/GIMT_Encode2(AMDGPU::S_TTRACEDATA_IMM),
        GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/1, // simm16
        GIR_ConstrainSelectedInstOperands, /*InsnID*/0,
        GIR_EraseFromParent, /*InsnID*/0,
        // GIR_Coverage, 197,
        GIR_Done,
      // Label 3262: @210460
      GIM_Try, /*On fail goto*//*Label 3263*/ GIMT_Encode4(210489), // Rule ID 198 //
        GIM_CheckFeatures, GIMT_Encode2(GIFBS_isGFX12Plus),
        GIM_CheckIntrinsicID, /*MI*/0, /*Op*/0, GIMT_Encode2(Intrinsic::amdgcn_s_wait_loadcnt),
        // MIs[0] simm16
        GIM_CheckIsImm, /*MI*/0, /*Op*/1,
        // (intrinsic_void 2695:{ *:[iPTR] }, (timm:{ *:[i16] }):$simm16)  =>  (S_WAIT_LOADCNT (timm:{ *:[i16] }):$simm16)
        GIR_BuildMI, /*InsnID*/0, /*Opcode*/GIMT_Encode2(AMDGPU::S_WAIT_LOADCNT),
        GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/1, // simm16
        GIR_ConstrainSelectedInstOperands, /*InsnID*/0,
        GIR_EraseFromParent, /*InsnID*/0,
        // GIR_Coverage, 198,
        GIR_Done,
      // Label 3263: @210489
      GIM_Try, /*On fail goto*//*Label 3264*/ GIMT_Encode4(210518), // Rule ID 199 //
        GIM_CheckFeatures, GIMT_Encode2(GIFBS_isGFX12Plus),
        GIM_CheckIntrinsicID, /*MI*/0, /*Op*/0, GIMT_Encode2(Intrinsic::amdgcn_s_wait_storecnt),
        // MIs[0] simm16
        GIM_CheckIsImm, /*MI*/0, /*Op*/1,
        // (intrinsic_void 2697:{ *:[iPTR] }, (timm:{ *:[i16] }):$simm16)  =>  (S_WAIT_STORECNT (timm:{ *:[i16] }):$simm16)
        GIR_BuildMI, /*InsnID*/0, /*Opcode*/GIMT_Encode2(AMDGPU::S_WAIT_STORECNT),
        GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/1, // simm16
        GIR_ConstrainSelectedInstOperands, /*InsnID*/0,
        GIR_EraseFromParent, /*InsnID*/0,
        // GIR_Coverage, 199,
        GIR_Done,
      // Label 3264: @210518
      GIM_Try, /*On fail goto*//*Label 3265*/ GIMT_Encode4(210547), // Rule ID 200 //
        GIM_CheckFeatures, GIMT_Encode2(GIFBS_isGFX12Plus),
        GIM_CheckIntrinsicID, /*MI*/0, /*Op*/0, GIMT_Encode2(Intrinsic::amdgcn_s_wait_samplecnt),
        // MIs[0] simm16
        GIM_CheckIsImm, /*MI*/0, /*Op*/1,
        // (intrinsic_void 2696:{ *:[iPTR] }, (timm:{ *:[i16] }):$simm16)  =>  (S_WAIT_SAMPLECNT (timm:{ *:[i16] }):$simm16)
        GIR_BuildMI, /*InsnID*/0, /*Opcode*/GIMT_Encode2(AMDGPU::S_WAIT_SAMPLECNT),
        GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/1, // simm16
        GIR_ConstrainSelectedInstOperands, /*InsnID*/0,
        GIR_EraseFromParent, /*InsnID*/0,
        // GIR_Coverage, 200,
        GIR_Done,
      // Label 3265: @210547
      GIM_Try, /*On fail goto*//*Label 3266*/ GIMT_Encode4(210576), // Rule ID 201 //
        GIM_CheckFeatures, GIMT_Encode2(GIFBS_isGFX12Plus),
        GIM_CheckIntrinsicID, /*MI*/0, /*Op*/0, GIMT_Encode2(Intrinsic::amdgcn_s_wait_bvhcnt),
        // MIs[0] simm16
        GIM_CheckIsImm, /*MI*/0, /*Op*/1,
        // (intrinsic_void 2690:{ *:[iPTR] }, (timm:{ *:[i16] }):$simm16)  =>  (S_WAIT_BVHCNT (timm:{ *:[i16] }):$simm16)
        GIR_BuildMI, /*InsnID*/0, /*Opcode*/GIMT_Encode2(AMDGPU::S_WAIT_BVHCNT),
        GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/1, // simm16
        GIR_ConstrainSelectedInstOperands, /*InsnID*/0,
        GIR_EraseFromParent, /*InsnID*/0,
        // GIR_Coverage, 201,
        GIR_Done,
      // Label 3266: @210576
      GIM_Try, /*On fail goto*//*Label 3267*/ GIMT_Encode4(210605), // Rule ID 202 //
        GIM_CheckFeatures, GIMT_Encode2(GIFBS_isGFX12Plus),
        GIM_CheckIntrinsicID, /*MI*/0, /*Op*/0, GIMT_Encode2(Intrinsic::amdgcn_s_wait_expcnt),
        // MIs[0] simm16
        GIM_CheckIsImm, /*MI*/0, /*Op*/1,
        // (intrinsic_void 2693:{ *:[iPTR] }, (timm:{ *:[i16] }):$simm16)  =>  (S_WAIT_EXPCNT (timm:{ *:[i16] }):$simm16)
        GIR_BuildMI, /*InsnID*/0, /*Opcode*/GIMT_Encode2(AMDGPU::S_WAIT_EXPCNT),
        GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/1, // simm16
        GIR_ConstrainSelectedInstOperands, /*InsnID*/0,
        GIR_EraseFromParent, /*InsnID*/0,
        // GIR_Coverage, 202,
        GIR_Done,
      // Label 3267: @210605
      GIM_Try, /*On fail goto*//*Label 3268*/ GIMT_Encode4(210634), // Rule ID 203 //
        GIM_CheckFeatures, GIMT_Encode2(GIFBS_isGFX12Plus),
        GIM_CheckIntrinsicID, /*MI*/0, /*Op*/0, GIMT_Encode2(Intrinsic::amdgcn_s_wait_dscnt),
        // MIs[0] simm16
        GIM_CheckIsImm, /*MI*/0, /*Op*/1,
        // (intrinsic_void 2691:{ *:[iPTR] }, (timm:{ *:[i16] }):$simm16)  =>  (S_WAIT_DSCNT (timm:{ *:[i16] }):$simm16)
        GIR_BuildMI, /*InsnID*/0, /*Opcode*/GIMT_Encode2(AMDGPU::S_WAIT_DSCNT),
        GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/1, // simm16
        GIR_ConstrainSelectedInstOperands, /*InsnID*/0,
        GIR_EraseFromParent, /*InsnID*/0,
        // GIR_Coverage, 203,
        GIR_Done,
      // Label 3268: @210634
      GIM_Try, /*On fail goto*//*Label 3269*/ GIMT_Encode4(210663), // Rule ID 204 //
        GIM_CheckFeatures, GIMT_Encode2(GIFBS_isGFX12Plus),
        GIM_CheckIntrinsicID, /*MI*/0, /*Op*/0, GIMT_Encode2(Intrinsic::amdgcn_s_wait_kmcnt),
        // MIs[0] simm16
        GIM_CheckIsImm, /*MI*/0, /*Op*/1,
        // (intrinsic_void 2694:{ *:[iPTR] }, (timm:{ *:[i16] }):$simm16)  =>  (S_WAIT_KMCNT (timm:{ *:[i16] }):$simm16)
        GIR_BuildMI, /*InsnID*/0, /*Opcode*/GIMT_Encode2(AMDGPU::S_WAIT_KMCNT),
        GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/1, // simm16
        GIR_ConstrainSelectedInstOperands, /*InsnID*/0,
        GIR_EraseFromParent, /*InsnID*/0,
        // GIR_Coverage, 204,
        GIR_Done,
      // Label 3269: @210663
      GIM_Try, /*On fail goto*//*Label 3270*/ GIMT_Encode4(210698), // Rule ID 1090 //
        GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasSMemTimeInst),
        GIM_CheckIntrinsicID, /*MI*/0, /*Op*/1, GIMT_Encode2(Intrinsic::amdgcn_s_memtime),
        GIM_CheckType, /*MI*/0, /*Op*/0, /*Type*/GILLT_s64,
        GIM_CheckRegBankForClass, /*MI*/0, /*Op*/0, /*RC*/GIMT_Encode2(AMDGPU::SReg_64_XEXECRegClassID),
        // (intrinsic_w_chain:{ *:[i64] } 2677:{ *:[iPTR] })  =>  (S_MEMTIME:{ *:[i64] })
        GIR_BuildMI, /*InsnID*/0, /*Opcode*/GIMT_Encode2(AMDGPU::S_MEMTIME),
        GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/0, // DstI[sdst]
        GIR_ConstrainSelectedInstOperands, /*InsnID*/0,
        GIR_EraseFromParent, /*InsnID*/0,
        // GIR_Coverage, 1090,
        GIR_Done,
      // Label 3270: @210698
      GIM_Try, /*On fail goto*//*Label 3271*/ GIMT_Encode4(210733), // Rule ID 1095 //
        GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasSMemRealTime),
        GIM_CheckIntrinsicID, /*MI*/0, /*Op*/1, GIMT_Encode2(Intrinsic::amdgcn_s_memrealtime),
        GIM_CheckType, /*MI*/0, /*Op*/0, /*Type*/GILLT_s64,
        GIM_CheckRegBankForClass, /*MI*/0, /*Op*/0, /*RC*/GIMT_Encode2(AMDGPU::SReg_64_XEXECRegClassID),
        // (intrinsic_w_chain:{ *:[i64] } 2676:{ *:[iPTR] })  =>  (S_MEMREALTIME:{ *:[i64] })
        GIR_BuildMI, /*InsnID*/0, /*Opcode*/GIMT_Encode2(AMDGPU::S_MEMREALTIME),
        GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/0, // DstI[sdst]
        GIR_ConstrainSelectedInstOperands, /*InsnID*/0,
        GIR_EraseFromParent, /*InsnID*/0,
        // GIR_Coverage, 1095,
        GIR_Done,
      // Label 3271: @210733
      GIM_Try, /*On fail goto*//*Label 3272*/ GIMT_Encode4(210768), // Rule ID 1096 //
        GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasGetWaveIdInst),
        GIM_CheckIntrinsicID, /*MI*/0, /*Op*/1, GIMT_Encode2(Intrinsic::amdgcn_s_get_waveid_in_workgroup),
        GIM_CheckType, /*MI*/0, /*Op*/0, /*Type*/GILLT_s32,
        GIM_CheckRegBankForClass, /*MI*/0, /*Op*/0, /*RC*/GIMT_Encode2(AMDGPU::SReg_32_XM0_XEXECRegClassID),
        // (intrinsic_w_chain:{ *:[i32] } 2672:{ *:[iPTR] })  =>  (S_GET_WAVEID_IN_WORKGROUP:{ *:[i32] })
        GIR_BuildMI, /*InsnID*/0, /*Opcode*/GIMT_Encode2(AMDGPU::S_GET_WAVEID_IN_WORKGROUP),
        GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/0, // DstI[sdst]
        GIR_ConstrainSelectedInstOperands, /*InsnID*/0,
        GIR_EraseFromParent, /*InsnID*/0,
        // GIR_Coverage, 1096,
        GIR_Done,
      // Label 3272: @210768
      GIM_Try, /*On fail goto*//*Label 3273*/ GIMT_Encode4(210804), // Rule ID 1130 //
        GIM_CheckIntrinsicID, /*MI*/0, /*Op*/1, GIMT_Encode2(Intrinsic::amdgcn_live_mask),
        GIM_CheckType, /*MI*/0, /*Op*/0, /*Type*/GILLT_s1,
        GIM_CheckRegBankForClass, /*MI*/0, /*Op*/0, /*RC*/GIMT_Encode2(AMDGPU::SReg_1RegClassID),
        // (intrinsic_w_chain:{ *:[i1] } 2533:{ *:[iPTR] })  =>  (SI_LIVE_MASK:{ *:[i1] })
        GIR_BuildMI, /*InsnID*/0, /*Opcode*/GIMT_Encode2(AMDGPU::SI_LIVE_MASK),
        GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/0, // DstI[dst]
        GIR_MergeMemOperands, /*InsnID*/0, /*NumInsns*/1, /*MergeInsnID's*/0,
        GIR_ConstrainSelectedInstOperands, /*InsnID*/0,
        GIR_EraseFromParent, /*InsnID*/0,
        // GIR_Coverage, 1130,
        GIR_Done,
      // Label 3273: @210804
      GIM_Try, /*On fail goto*//*Label 3274*/ GIMT_Encode4(210836), // Rule ID 189 //
        GIM_CheckIntrinsicID, /*MI*/0, /*Op*/0, GIMT_Encode2(Intrinsic::amdgcn_s_sleep_var),
        GIM_CheckType, /*MI*/0, /*Op*/1, /*Type*/GILLT_s32,
        GIM_CheckRegBankForClass, /*MI*/0, /*Op*/1, /*RC*/GIMT_Encode2(AMDGPU::SReg_32RegClassID),
        // (intrinsic_void 2687:{ *:[iPTR] }, SSrc_b32:{ *:[i32] }:$src0)  =>  (S_SLEEP_VAR SSrc_b32:{ *:[i32] }:$src0)
        GIR_BuildMI, /*InsnID*/0, /*Opcode*/GIMT_Encode2(AMDGPU::S_SLEEP_VAR),
        GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/1, // src0
        GIR_ConstrainSelectedInstOperands, /*InsnID*/0,
        GIR_EraseFromParent, /*InsnID*/0,
        // GIR_Coverage, 189,
        GIR_Done,
      // Label 3274: @210836
      GIM_Try, /*On fail goto*//*Label 3275*/ GIMT_Encode4(210878), // Rule ID 195 //
        GIM_CheckIntrinsicID, /*MI*/0, /*Op*/0, GIMT_Encode2(Intrinsic::amdgcn_s_ttracedata),
        GIM_CheckType, /*MI*/0, /*Op*/1, /*Type*/GILLT_s32,
        GIM_CheckRegBankForClass, /*MI*/0, /*Op*/1, /*RC*/GIMT_Encode2(AMDGPU::M0_CLASSRegClassID),
        // (intrinsic_void 2688:{ *:[iPTR] }, M0:{ *:[i32] })  =>  (S_TTRACEDATA)
        GIR_BuildMI, /*InsnID*/1, /*Opcode*/GIMT_Encode2(TargetOpcode::COPY),
        GIR_AddRegister, /*InsnID*/1, GIMT_Encode2(AMDGPU::M0), /*AddRegisterRegFlags*/GIMT_Encode2(RegState::Define),
        GIR_Copy, /*NewInsnID*/1, /*OldInsnID*/0, /*OpIdx*/1, // M0
        GIR_BuildMI, /*InsnID*/0, /*Opcode*/GIMT_Encode2(AMDGPU::S_TTRACEDATA),
        GIR_ConstrainSelectedInstOperands, /*InsnID*/0,
        GIR_EraseFromParent, /*InsnID*/0,
        // GIR_Coverage, 195,
        GIR_Done,
      // Label 3275: @210878
      GIM_Try, /*On fail goto*//*Label 3276*/ GIMT_Encode4(210915), // Rule ID 5851 //
        GIM_CheckIntrinsicID, /*MI*/0, /*Op*/0, GIMT_Encode2(Intrinsic::amdgcn_kill),
        GIM_CheckType, /*MI*/0, /*Op*/1, /*Type*/GILLT_s1,
        // (intrinsic_void 2528:{ *:[iPTR] }, i1:{ *:[i1] }:$src)  =>  (SI_KILL_I1_PSEUDO SCSrc_i1:{ *:[i1] }:$src, 0:{ *:[i1] })
        GIR_BuildMI, /*InsnID*/0, /*Opcode*/GIMT_Encode2(AMDGPU::SI_KILL_I1_PSEUDO),
        GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/1, // src
        GIR_AddImm8, /*InsnID*/0, /*Imm*/0,
        GIR_SetImplicitDefDead, /*InsnID*/0, /*OpIdx for AMDGPU::SCC*/1,
        GIR_MergeMemOperands, /*InsnID*/0, /*NumInsns*/1, /*MergeInsnID's*/0,
        GIR_ConstrainSelectedInstOperands, /*InsnID*/0,
        GIR_EraseFromParent, /*InsnID*/0,
        // GIR_Coverage, 5851,
        GIR_Done,
      // Label 3276: @210915
      GIM_Try, /*On fail goto*//*Label 3277*/ GIMT_Encode4(210952), // Rule ID 5854 //
        GIM_CheckIntrinsicID, /*MI*/0, /*Op*/0, GIMT_Encode2(Intrinsic::amdgcn_wqm_demote),
        GIM_CheckType, /*MI*/0, /*Op*/1, /*Type*/GILLT_s1,
        // (intrinsic_void 2829:{ *:[iPTR] }, i1:{ *:[i1] }:$src)  =>  (SI_DEMOTE_I1 SCSrc_i1:{ *:[i1] }:$src, 0:{ *:[i1] })
        GIR_BuildMI, /*InsnID*/0, /*Opcode*/GIMT_Encode2(AMDGPU::SI_DEMOTE_I1),
        GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/1, // src
        GIR_AddImm8, /*InsnID*/0, /*Imm*/0,
        GIR_SetImplicitDefDead, /*InsnID*/0, /*OpIdx for AMDGPU::SCC*/1,
        GIR_MergeMemOperands, /*InsnID*/0, /*NumInsns*/1, /*MergeInsnID's*/0,
        GIR_ConstrainSelectedInstOperands, /*InsnID*/0,
        GIR_EraseFromParent, /*InsnID*/0,
        // GIR_Coverage, 5854,
        GIR_Done,
      // Label 3277: @210952
      GIM_Reject,
    // Label 3252: @210953
    GIM_Try, /*On fail goto*//*Label 3278*/ GIMT_Encode4(211357),
      GIM_CheckNumOperands, /*MI*/0, /*Expected*/3,
      GIM_Try, /*On fail goto*//*Label 3279*/ GIMT_Encode4(211002), // Rule ID 121 //
        GIM_CheckIntrinsicID, /*MI*/0, /*Op*/0, GIMT_Encode2(Intrinsic::amdgcn_s_setreg),
        GIM_CheckType, /*MI*/0, /*Op*/2, /*Type*/GILLT_s32,
        // MIs[0] simm16
        GIM_CheckIsImm, /*MI*/0, /*Op*/1,
        GIM_CheckImmOperandPredicate, /*MI*/0, /*MO*/1, /*Predicate*/GIMT_Encode2(GICXXPred_I64_Predicate_SIMM16bit),
        // (intrinsic_void 2685:{ *:[iPTR] }, (timm:{ *:[i32] })<<P:Predicate_SIMM16bit>><<X:as_i16timm>>:$simm16, i32:{ *:[i32] }:$sdst)  =>  (S_SETREG_B32 i32:{ *:[i32] }:$sdst, (as_i16timm:{ *:[i32] } (timm:{ *:[i32] }):$simm16))
        GIR_BuildMI, /*InsnID*/0, /*Opcode*/GIMT_Encode2(AMDGPU::S_SETREG_B32),
        GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/2, // sdst
        GIR_CustomOperandRenderer, /*InsnID*/0, /*OldInsnID*/0, /*OpIdx*/1, /*OperandRenderer*/GIMT_Encode2(GICR_renderTruncTImm), // simm16
        GIR_ConstrainSelectedInstOperands, /*InsnID*/0,
        GIR_EraseFromParent, /*InsnID*/0,
        // GIR_Coverage, 121,
        GIR_Done,
      // Label 3279: @211002
      GIM_Try, /*On fail goto*//*Label 3280*/ GIMT_Encode4(211044), // Rule ID 25 //
        GIM_CheckFeatures, GIMT_Encode2(GIFBS_isGFX11Plus),
        GIM_CheckIntrinsicID, /*MI*/0, /*Op*/1, GIMT_Encode2(Intrinsic::amdgcn_s_sendmsg_rtn),
        GIM_CheckType, /*MI*/0, /*Op*/0, /*Type*/GILLT_s32,
        GIM_CheckRegBankForClass, /*MI*/0, /*Op*/0, /*RC*/GIMT_Encode2(AMDGPU::SReg_32RegClassID),
        // MIs[0] src0
        GIM_CheckIsImm, /*MI*/0, /*Op*/2,
        // (intrinsic_w_chain:{ *:[i32] } 2681:{ *:[iPTR] }, (timm:{ *:[i32] }):$src0)  =>  (S_SENDMSG_RTN_B32:{ *:[i32] } (timm:{ *:[i32] }):$src0)
        GIR_BuildMI, /*InsnID*/0, /*Opcode*/GIMT_Encode2(AMDGPU::S_SENDMSG_RTN_B32),
        GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/0, // DstI[sdst]
        GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/2, // src0
        GIR_ConstrainSelectedInstOperands, /*InsnID*/0,
        GIR_EraseFromParent, /*InsnID*/0,
        // GIR_Coverage, 25,
        GIR_Done,
      // Label 3280: @211044
      GIM_Try, /*On fail goto*//*Label 3281*/ GIMT_Encode4(211086), // Rule ID 26 //
        GIM_CheckFeatures, GIMT_Encode2(GIFBS_isGFX11Plus),
        GIM_CheckIntrinsicID, /*MI*/0, /*Op*/1, GIMT_Encode2(Intrinsic::amdgcn_s_sendmsg_rtn),
        GIM_CheckType, /*MI*/0, /*Op*/0, /*Type*/GILLT_s64,
        GIM_CheckRegBankForClass, /*MI*/0, /*Op*/0, /*RC*/GIMT_Encode2(AMDGPU::SReg_64RegClassID),
        // MIs[0] src0
        GIM_CheckIsImm, /*MI*/0, /*Op*/2,
        // (intrinsic_w_chain:{ *:[i64] } 2681:{ *:[iPTR] }, (timm:{ *:[i32] }):$src0)  =>  (S_SENDMSG_RTN_B64:{ *:[i64] } (timm:{ *:[i32] }):$src0)
        GIR_BuildMI, /*InsnID*/0, /*Opcode*/GIMT_Encode2(AMDGPU::S_SENDMSG_RTN_B64),
        GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/0, // DstI[sdst]
        GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/2, // src0
        GIR_ConstrainSelectedInstOperands, /*InsnID*/0,
        GIR_EraseFromParent, /*InsnID*/0,
        // GIR_Coverage, 26,
        GIR_Done,
      // Label 3281: @211086
      GIM_Try, /*On fail goto*//*Label 3282*/ GIMT_Encode4(211125), // Rule ID 120 //
        GIM_CheckIntrinsicID, /*MI*/0, /*Op*/1, GIMT_Encode2(Intrinsic::amdgcn_s_getreg),
        GIM_CheckType, /*MI*/0, /*Op*/0, /*Type*/GILLT_s32,
        GIM_CheckRegBankForClass, /*MI*/0, /*Op*/0, /*RC*/GIMT_Encode2(AMDGPU::SReg_32RegClassID),
        // MIs[0] simm16
        GIM_CheckIsImm, /*MI*/0, /*Op*/2,
        // (intrinsic_w_chain:{ *:[i32] } 2674:{ *:[iPTR] }, (timm:{ *:[i32] }):$simm16)  =>  (S_GETREG_B32:{ *:[i32] } (timm:{ *:[i32] }):$simm16)
        GIR_BuildMI, /*InsnID*/0, /*Opcode*/GIMT_Encode2(AMDGPU::S_GETREG_B32),
        GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/0, // DstI[sdst]
        GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/2, // simm16
        GIR_ConstrainSelectedInstOperands, /*InsnID*/0,
        GIR_EraseFromParent, /*InsnID*/0,
        // GIR_Coverage, 120,
        GIR_Done,
      // Label 3282: @211125
      GIM_Try, /*On fail goto*//*Label 3283*/ GIMT_Encode4(211174), // Rule ID 191 //
        GIM_CheckIntrinsicID, /*MI*/0, /*Op*/0, GIMT_Encode2(Intrinsic::amdgcn_s_sendmsg),
        GIM_CheckType, /*MI*/0, /*Op*/2, /*Type*/GILLT_s32,
        // MIs[0] simm16
        GIM_CheckIsImm, /*MI*/0, /*Op*/1,
        GIM_CheckRegBankForClass, /*MI*/0, /*Op*/2, /*RC*/GIMT_Encode2(AMDGPU::M0_CLASSRegClassID),
        // (intrinsic_void 2680:{ *:[iPTR] }, (timm:{ *:[i32] }):$simm16, M0:{ *:[i32] })  =>  (S_SENDMSG (timm:{ *:[i32] }):$simm16)
        GIR_BuildMI, /*InsnID*/1, /*Opcode*/GIMT_Encode2(TargetOpcode::COPY),
        GIR_AddRegister, /*InsnID*/1, GIMT_Encode2(AMDGPU::M0), /*AddRegisterRegFlags*/GIMT_Encode2(RegState::Define),
        GIR_Copy, /*NewInsnID*/1, /*OldInsnID*/0, /*OpIdx*/2, // M0
        GIR_BuildMI, /*InsnID*/0, /*Opcode*/GIMT_Encode2(AMDGPU::S_SENDMSG),
        GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/1, // simm16
        GIR_ConstrainSelectedInstOperands, /*InsnID*/0,
        GIR_EraseFromParent, /*InsnID*/0,
        // GIR_Coverage, 191,
        GIR_Done,
      // Label 3283: @211174
      GIM_Try, /*On fail goto*//*Label 3284*/ GIMT_Encode4(211223), // Rule ID 192 //
        GIM_CheckIntrinsicID, /*MI*/0, /*Op*/0, GIMT_Encode2(Intrinsic::amdgcn_s_sendmsghalt),
        GIM_CheckType, /*MI*/0, /*Op*/2, /*Type*/GILLT_s32,
        // MIs[0] simm16
        GIM_CheckIsImm, /*MI*/0, /*Op*/1,
        GIM_CheckRegBankForClass, /*MI*/0, /*Op*/2, /*RC*/GIMT_Encode2(AMDGPU::M0_CLASSRegClassID),
        // (intrinsic_void 2682:{ *:[iPTR] }, (timm:{ *:[i32] }):$simm16, M0:{ *:[i32] })  =>  (S_SENDMSGHALT (timm:{ *:[i32] }):$simm16)
        GIR_BuildMI, /*InsnID*/1, /*Opcode*/GIMT_Encode2(TargetOpcode::COPY),
        GIR_AddRegister, /*InsnID*/1, GIMT_Encode2(AMDGPU::M0), /*AddRegisterRegFlags*/GIMT_Encode2(RegState::Define),
        GIR_Copy, /*NewInsnID*/1, /*OldInsnID*/0, /*OpIdx*/2, // M0
        GIR_BuildMI, /*InsnID*/0, /*Opcode*/GIMT_Encode2(AMDGPU::S_SENDMSGHALT),
        GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/1, // simm16
        GIR_ConstrainSelectedInstOperands, /*InsnID*/0,
        GIR_EraseFromParent, /*InsnID*/0,
        // GIR_Coverage, 192,
        GIR_Done,
      // Label 3284: @211223
      GIM_Try, /*On fail goto*//*Label 3285*/ GIMT_Encode4(211288), // Rule ID 5829 //
        GIM_CheckFeatures, GIMT_Encode2(GIFBS_isGFX11Only),
        GIM_CheckIntrinsicID, /*MI*/0, /*Op*/1, GIMT_Encode2(Intrinsic::amdgcn_lds_direct_load),
        GIM_CheckType, /*MI*/0, /*Op*/0, /*Type*/GILLT_s32,
        GIM_CheckType, /*MI*/0, /*Op*/2, /*Type*/GILLT_s32,
        GIM_CheckRegBankForClass, /*MI*/0, /*Op*/0, /*RC*/GIMT_Encode2(AMDGPU::VGPR_32RegClassID),
        GIM_CheckRegBankForClass, /*MI*/0, /*Op*/2, /*RC*/GIMT_Encode2(AMDGPU::M0_CLASSRegClassID),
        // (intrinsic_w_chain:{ *:[f32] } 2529:{ *:[iPTR] }, M0:{ *:[i32] })  =>  (LDS_DIRECT_LOAD:{ *:[f32] } 0:{ *:[i8] })
        GIR_BuildMI, /*InsnID*/1, /*Opcode*/GIMT_Encode2(TargetOpcode::COPY),
        GIR_AddRegister, /*InsnID*/1, GIMT_Encode2(AMDGPU::M0), /*AddRegisterRegFlags*/GIMT_Encode2(RegState::Define),
        GIR_Copy, /*NewInsnID*/1, /*OldInsnID*/0, /*OpIdx*/2, // M0
        GIR_BuildMI, /*InsnID*/0, /*Opcode*/GIMT_Encode2(AMDGPU::LDS_DIRECT_LOAD),
        GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/0, // DstI[vdst]
        GIR_AddImm8, /*InsnID*/0, /*Imm*/0,
        GIR_MergeMemOperands, /*InsnID*/0, /*NumInsns*/1, /*MergeInsnID's*/0,
        GIR_ConstrainSelectedInstOperands, /*InsnID*/0,
        GIR_EraseFromParent, /*InsnID*/0,
        // GIR_Coverage, 5829,
        GIR_Done,
      // Label 3285: @211288
      GIM_Try, /*On fail goto*//*Label 3286*/ GIMT_Encode4(211356), // Rule ID 5831 //
        GIM_CheckFeatures, GIMT_Encode2(GIFBS_isGFX12Plus),
        GIM_CheckIntrinsicID, /*MI*/0, /*Op*/1, GIMT_Encode2(Intrinsic::amdgcn_lds_direct_load),
        GIM_CheckType, /*MI*/0, /*Op*/0, /*Type*/GILLT_s32,
        GIM_CheckType, /*MI*/0, /*Op*/2, /*Type*/GILLT_s32,
        GIM_CheckRegBankForClass, /*MI*/0, /*Op*/0, /*RC*/GIMT_Encode2(AMDGPU::VGPR_32RegClassID),
        GIM_CheckRegBankForClass, /*MI*/0, /*Op*/2, /*RC*/GIMT_Encode2(AMDGPU::M0_CLASSRegClassID),
        // (intrinsic_w_chain:{ *:[f32] } 2529:{ *:[iPTR] }, M0:{ *:[i32] })  =>  (DS_DIRECT_LOAD:{ *:[f32] } 0:{ *:[i8] }, 1:{ *:[i8] })
        GIR_BuildMI, /*InsnID*/1, /*Opcode*/GIMT_Encode2(TargetOpcode::COPY),
        GIR_AddRegister, /*InsnID*/1, GIMT_Encode2(AMDGPU::M0), /*AddRegisterRegFlags*/GIMT_Encode2(RegState::Define),
        GIR_Copy, /*NewInsnID*/1, /*OldInsnID*/0, /*OpIdx*/2, // M0
        GIR_BuildMI, /*InsnID*/0, /*Opcode*/GIMT_Encode2(AMDGPU::DS_DIRECT_LOAD),
        GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/0, // DstI[vdst]
        GIR_AddImm8, /*InsnID*/0, /*Imm*/0,
        GIR_AddImm8, /*InsnID*/0, /*Imm*/1,
        GIR_MergeMemOperands, /*InsnID*/0, /*NumInsns*/1, /*MergeInsnID's*/0,
        GIR_ConstrainSelectedInstOperands, /*InsnID*/0,
        GIR_EraseFromParent, /*InsnID*/0,
        // GIR_Coverage, 5831,
        GIR_Done,
      // Label 3286: @211356
      GIM_Reject,
    // Label 3278: @211357
    GIM_Try, /*On fail goto*//*Label 3287*/ GIMT_Encode4(219311),
      GIM_CheckNumOperands, /*MI*/0, /*Expected*/4,
      GIM_Try, /*On fail goto*//*Label 3288*/ GIMT_Encode4(211446), // Rule ID 1098 //
        GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasGFX10_BEncoding),
        GIM_CheckIntrinsicID, /*MI*/0, /*Op*/1, GIMT_Encode2(Intrinsic::amdgcn_global_atomic_csub),
        GIM_CheckType, /*MI*/0, /*Op*/0, /*Type*/GILLT_s32,
        GIM_CheckType, /*MI*/0, /*Op*/3, /*Type*/GILLT_s32,
        GIM_CheckRegBankForClass, /*MI*/0, /*Op*/0, /*RC*/GIMT_Encode2(AMDGPU::AV_32RegClassID),
        GIM_CheckPointerToAny, /*MI*/0, /*Op*/2, /*SizeInBits*/0,
        GIM_CheckComplexPattern, /*MI*/0, /*Op*/2, /*Renderer*/GIMT_Encode2(0), GIMT_Encode2(GICP_gi_mubuf_addr64),
        // (intrinsic_w_chain:{ *:[i32] } 1977:{ *:[iPTR] }, (MUBUFAddr64:{ *:[iPTR] } v4i32:{ *:[v4i32] }:$srsrc, i64:{ *:[i64] }:$vaddr, i32:{ *:[i32] }:$soffset, i32:{ *:[i32] }:$offset), i32:{ *:[i32] }:$vdata_in)  =>  (BUFFER_ATOMIC_CSUB_ADDR64_RTN:{ *:[i32] } i32:{ *:[i32] }:$vdata_in, i64:{ *:[i64] }:$vaddr, v4i32:{ *:[v4i32] }:$srsrc, i32:{ *:[i32] }:$soffset, i32:{ *:[i32] }:$offset)
        GIR_BuildMI, /*InsnID*/0, /*Opcode*/GIMT_Encode2(AMDGPU::BUFFER_ATOMIC_CSUB_ADDR64_RTN),
        GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/0, // DstI[vdata]
        GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/3, // vdata_in
        GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/1, // vaddr
        GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/0, // srsrc
        GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/2, // soffset
        GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/3, // offset
        GIR_AddImm8, /*InsnID*/0, /*Imm*/1,
        GIR_MergeMemOperands, /*InsnID*/0, /*NumInsns*/1, /*MergeInsnID's*/0,
        GIR_ConstrainSelectedInstOperands, /*InsnID*/0,
        GIR_EraseFromParent, /*InsnID*/0,
        // GIR_Coverage, 1098,
        GIR_Done,
      // Label 3288: @211446
      GIM_Try, /*On fail goto*//*Label 3289*/ GIMT_Encode4(211527), // Rule ID 1100 //
        GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasGFX10_BEncoding),
        GIM_CheckIntrinsicID, /*MI*/0, /*Op*/1, GIMT_Encode2(Intrinsic::amdgcn_global_atomic_csub),
        GIM_CheckType, /*MI*/0, /*Op*/0, /*Type*/GILLT_s32,
        GIM_CheckType, /*MI*/0, /*Op*/3, /*Type*/GILLT_s32,
        GIM_CheckRegBankForClass, /*MI*/0, /*Op*/0, /*RC*/GIMT_Encode2(AMDGPU::AV_32RegClassID),
        GIM_CheckPointerToAny, /*MI*/0, /*Op*/2, /*SizeInBits*/0,
        GIM_CheckComplexPattern, /*MI*/0, /*Op*/2, /*Renderer*/GIMT_Encode2(0), GIMT_Encode2(GICP_gi_mubuf_addr64),
        // (intrinsic_w_chain:{ *:[i32] } 1977:{ *:[iPTR] }, (MUBUFAddr64:{ *:[iPTR] } v4i32:{ *:[v4i32] }:$srsrc, i64:{ *:[i64] }:$vaddr, i32:{ *:[i32] }:$soffset, i32:{ *:[i32] }:$offset), i32:{ *:[i32] }:$vdata_in)  =>  (BUFFER_ATOMIC_CSUB_VBUFFER_ADDR64_RTN:{ *:[i32] } i32:{ *:[i32] }:$vdata_in, i64:{ *:[i64] }:$vaddr, v4i32:{ *:[v4i32] }:$srsrc, i32:{ *:[i32] }:$soffset, i32:{ *:[i32] }:$offset)
        GIR_BuildMI, /*InsnID*/0, /*Opcode*/GIMT_Encode2(AMDGPU::BUFFER_ATOMIC_CSUB_VBUFFER_ADDR64_RTN),
        GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/0, // DstI[vdata]
        GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/3, // vdata_in
        GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/1, // vaddr
        GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/0, // srsrc
        GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/2, // soffset
        GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/3, // offset
        GIR_AddImm8, /*InsnID*/0, /*Imm*/1,
        GIR_MergeMemOperands, /*InsnID*/0, /*NumInsns*/1, /*MergeInsnID's*/0,
        GIR_ConstrainSelectedInstOperands, /*InsnID*/0,
        GIR_EraseFromParent, /*InsnID*/0,
        // GIR_Coverage, 1100,
        GIR_Done,
      // Label 3289: @211527
      GIM_Try, /*On fail goto*//*Label 3290*/ GIMT_Encode4(211603), // Rule ID 1097 //
        GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasGFX10_BEncoding),
        GIM_CheckIntrinsicID, /*MI*/0, /*Op*/1, GIMT_Encode2(Intrinsic::amdgcn_global_atomic_csub),
        GIM_CheckType, /*MI*/0, /*Op*/0, /*Type*/GILLT_s32,
        GIM_CheckType, /*MI*/0, /*Op*/3, /*Type*/GILLT_s32,
        GIM_CheckRegBankForClass, /*MI*/0, /*Op*/0, /*RC*/GIMT_Encode2(AMDGPU::AV_32RegClassID),
        GIM_CheckPointerToAny, /*MI*/0, /*Op*/2, /*SizeInBits*/0,
        GIM_CheckComplexPattern, /*MI*/0, /*Op*/2, /*Renderer*/GIMT_Encode2(0), GIMT_Encode2(GICP_gi_mubuf_offset),
        // (intrinsic_w_chain:{ *:[i32] } 1977:{ *:[iPTR] }, (MUBUFOffset:{ *:[iPTR] } v4i32:{ *:[v4i32] }:$srsrc, i32:{ *:[i32] }:$soffset, i32:{ *:[i32] }:$offset), i32:{ *:[i32] }:$vdata_in)  =>  (BUFFER_ATOMIC_CSUB_OFFSET_RTN:{ *:[i32] } i32:{ *:[i32] }:$vdata_in, v4i32:{ *:[v4i32] }:$srsrc, i32:{ *:[i32] }:$soffset, i32:{ *:[i32] }:$offset)
        GIR_BuildMI, /*InsnID*/0, /*Opcode*/GIMT_Encode2(AMDGPU::BUFFER_ATOMIC_CSUB_OFFSET_RTN),
        GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/0, // DstI[vdata]
        GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/3, // vdata_in
        GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/0, // srsrc
        GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/1, // soffset
        GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/2, // offset
        GIR_AddImm8, /*InsnID*/0, /*Imm*/1,
        GIR_MergeMemOperands, /*InsnID*/0, /*NumInsns*/1, /*MergeInsnID's*/0,
        GIR_ConstrainSelectedInstOperands, /*InsnID*/0,
        GIR_EraseFromParent, /*InsnID*/0,
        // GIR_Coverage, 1097,
        GIR_Done,
      // Label 3290: @211603
      GIM_Try, /*On fail goto*//*Label 3291*/ GIMT_Encode4(211679), // Rule ID 1099 //
        GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasGFX10_BEncoding),
        GIM_CheckIntrinsicID, /*MI*/0, /*Op*/1, GIMT_Encode2(Intrinsic::amdgcn_global_atomic_csub),
        GIM_CheckType, /*MI*/0, /*Op*/0, /*Type*/GILLT_s32,
        GIM_CheckType, /*MI*/0, /*Op*/3, /*Type*/GILLT_s32,
        GIM_CheckRegBankForClass, /*MI*/0, /*Op*/0, /*RC*/GIMT_Encode2(AMDGPU::AV_32RegClassID),
        GIM_CheckPointerToAny, /*MI*/0, /*Op*/2, /*SizeInBits*/0,
        GIM_CheckComplexPattern, /*MI*/0, /*Op*/2, /*Renderer*/GIMT_Encode2(0), GIMT_Encode2(GICP_gi_mubuf_offset),
        // (intrinsic_w_chain:{ *:[i32] } 1977:{ *:[iPTR] }, (MUBUFOffset:{ *:[iPTR] } v4i32:{ *:[v4i32] }:$srsrc, i32:{ *:[i32] }:$soffset, i32:{ *:[i32] }:$offset), i32:{ *:[i32] }:$vdata_in)  =>  (BUFFER_ATOMIC_CSUB_VBUFFER_OFFSET_RTN:{ *:[i32] } i32:{ *:[i32] }:$vdata_in, v4i32:{ *:[v4i32] }:$srsrc, i32:{ *:[i32] }:$soffset, i32:{ *:[i32] }:$offset)
        GIR_BuildMI, /*InsnID*/0, /*Opcode*/GIMT_Encode2(AMDGPU::BUFFER_ATOMIC_CSUB_VBUFFER_OFFSET_RTN),
        GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/0, // DstI[vdata]
        GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/3, // vdata_in
        GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/0, // srsrc
        GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/1, // soffset
        GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/2, // offset
        GIR_AddImm8, /*InsnID*/0, /*Imm*/1,
        GIR_MergeMemOperands, /*InsnID*/0, /*NumInsns*/1, /*MergeInsnID's*/0,
        GIR_ConstrainSelectedInstOperands, /*InsnID*/0,
        GIR_EraseFromParent, /*InsnID*/0,
        // GIR_Coverage, 1099,
        GIR_Done,
      // Label 3291: @211679
      GIM_Try, /*On fail goto*//*Label 3292*/ GIMT_Encode4(211748), // Rule ID 6565 //
        GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasAtomicCSubNoRtnInsts_isGFX12Plus),
        GIM_CheckIntrinsicID, /*MI*/0, /*Op*/1, GIMT_Encode2(Intrinsic::amdgcn_atomic_cond_sub_u32),
        GIM_CheckType, /*MI*/0, /*Op*/0, /*Type*/GILLT_s32,
        GIM_CheckType, /*MI*/0, /*Op*/3, /*Type*/GILLT_s32,
        GIM_CheckMemoryAddressSpace, /*MI*/0, /*MMO*/0, /*NumAddrSpace*/1, /*AddrSpace*/3,
        GIM_CheckHasNoUse, /*MI*/0,
        GIM_CheckPointerToAny, /*MI*/0, /*Op*/2, /*SizeInBits*/0,
        GIM_CheckComplexPattern, /*MI*/0, /*Op*/2, /*Renderer*/GIMT_Encode2(0), GIMT_Encode2(GICP_gi_ds_1addr_1offset),
        // (intrinsic_w_chain:{ *:[i32] } 1879:{ *:[iPTR] }, (DS1Addr1Offset:{ *:[iPTR] } i32:{ *:[i32] }:$ptr, i32:{ *:[i32] }:$offset), i32:{ *:[i32] }:$value)<<P:Predicate_int_amdgcn_atomic_cond_sub_u32_noret_local_addrspace>>  =>  (DS_COND_SUB_U32 ?:{ *:[i32] }:$ptr, anonymous_15037:{ *:[i32] }:$value, offset:{ *:[i32] }:$offset, 0:{ *:[i1] })
        GIR_BuildMI, /*InsnID*/0, /*Opcode*/GIMT_Encode2(AMDGPU::DS_COND_SUB_U32),
        GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/0, // ptr
        GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/3, // value
        GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/1, // offset
        GIR_AddImm8, /*InsnID*/0, /*Imm*/0,
        GIR_MergeMemOperands, /*InsnID*/0, /*NumInsns*/1, /*MergeInsnID's*/0,
        GIR_ConstrainSelectedInstOperands, /*InsnID*/0,
        GIR_EraseFromParent, /*InsnID*/0,
        // GIR_Coverage, 6565,
        GIR_Done,
      // Label 3292: @211748
      GIM_Try, /*On fail goto*//*Label 3293*/ GIMT_Encode4(211817), // Rule ID 7082 //
        GIM_CheckFeatures, GIMT_Encode2(GIFBS_isGFX90APlus),
        GIM_CheckIntrinsicID, /*MI*/0, /*Op*/1, GIMT_Encode2(Intrinsic::amdgcn_flat_atomic_fadd),
        GIM_CheckType, /*MI*/0, /*Op*/0, /*Type*/GILLT_s64,
        GIM_CheckType, /*MI*/0, /*Op*/3, /*Type*/GILLT_s64,
        GIM_CheckMemoryAddressSpace, /*MI*/0, /*MMO*/0, /*NumAddrSpace*/1, /*AddrSpace*/3,
        GIM_CheckHasNoUse, /*MI*/0,
        GIM_CheckPointerToAny, /*MI*/0, /*Op*/2, /*SizeInBits*/0,
        GIM_CheckComplexPattern, /*MI*/0, /*Op*/2, /*Renderer*/GIMT_Encode2(0), GIMT_Encode2(GICP_gi_ds_1addr_1offset),
        // (intrinsic_w_chain:{ *:[f64] } 1964:{ *:[iPTR] }, (DS1Addr1Offset:{ *:[iPTR] } i32:{ *:[i32] }:$ptr, i32:{ *:[i32] }:$offset), f64:{ *:[f64] }:$value)<<P:Predicate_int_amdgcn_flat_atomic_fadd_noret_local_addrspace>>  =>  (DS_ADD_F64 ?:{ *:[i32] }:$ptr, anonymous_15036:{ *:[f64] }:$value, offset:{ *:[i32] }:$offset, 0:{ *:[i1] })
        GIR_BuildMI, /*InsnID*/0, /*Opcode*/GIMT_Encode2(AMDGPU::DS_ADD_F64),
        GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/0, // ptr
        GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/3, // value
        GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/1, // offset
        GIR_AddImm8, /*InsnID*/0, /*Imm*/0,
        GIR_MergeMemOperands, /*InsnID*/0, /*NumInsns*/1, /*MergeInsnID's*/0,
        GIR_ConstrainSelectedInstOperands, /*InsnID*/0,
        GIR_EraseFromParent, /*InsnID*/0,
        // GIR_Coverage, 7082,
        GIR_Done,
      // Label 3293: @211817
      GIM_Try, /*On fail goto*//*Label 3294*/ GIMT_Encode4(211893), // Rule ID 6564 //
        GIM_CheckFeatures, GIMT_Encode2(GIFBS_isGFX12Plus),
        GIM_CheckIntrinsicID, /*MI*/0, /*Op*/1, GIMT_Encode2(Intrinsic::amdgcn_atomic_cond_sub_u32),
        GIM_CheckType, /*MI*/0, /*Op*/0, /*Type*/GILLT_s32,
        GIM_CheckType, /*MI*/0, /*Op*/3, /*Type*/GILLT_s32,
        GIM_CheckMemoryAddressSpace, /*MI*/0, /*MMO*/0, /*NumAddrSpace*/1, /*AddrSpace*/3,
        GIM_CheckRegBankForClass, /*MI*/0, /*Op*/0, /*RC*/GIMT_Encode2(AMDGPU::AV_32RegClassID),
        GIM_CheckPointerToAny, /*MI*/0, /*Op*/2, /*SizeInBits*/0,
        GIM_CheckComplexPattern, /*MI*/0, /*Op*/2, /*Renderer*/GIMT_Encode2(0), GIMT_Encode2(GICP_gi_ds_1addr_1offset),
        // (intrinsic_w_chain:{ *:[i32] } 1879:{ *:[iPTR] }, (DS1Addr1Offset:{ *:[iPTR] } i32:{ *:[i32] }:$ptr, i32:{ *:[i32] }:$offset), i32:{ *:[i32] }:$value)<<P:Predicate_int_amdgcn_atomic_cond_sub_u32_local_addrspace>>  =>  (DS_COND_SUB_RTN_U32:{ *:[i32] } ?:{ *:[i32] }:$ptr, anonymous_15037:{ *:[i32] }:$value, offset:{ *:[i32] }:$offset, 0:{ *:[i1] })
        GIR_BuildMI, /*InsnID*/0, /*Opcode*/GIMT_Encode2(AMDGPU::DS_COND_SUB_RTN_U32),
        GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/0, // DstI[vdst]
        GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/0, // ptr
        GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/3, // value
        GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/1, // offset
        GIR_AddImm8, /*InsnID*/0, /*Imm*/0,
        GIR_MergeMemOperands, /*InsnID*/0, /*NumInsns*/1, /*MergeInsnID's*/0,
        GIR_ConstrainSelectedInstOperands, /*InsnID*/0,
        GIR_EraseFromParent, /*InsnID*/0,
        // GIR_Coverage, 6564,
        GIR_Done,
      // Label 3294: @211893
      GIM_Try, /*On fail goto*//*Label 3295*/ GIMT_Encode4(211969), // Rule ID 7081 //
        GIM_CheckFeatures, GIMT_Encode2(GIFBS_isGFX90APlus),
        GIM_CheckIntrinsicID, /*MI*/0, /*Op*/1, GIMT_Encode2(Intrinsic::amdgcn_flat_atomic_fadd),
        GIM_CheckType, /*MI*/0, /*Op*/0, /*Type*/GILLT_s64,
        GIM_CheckType, /*MI*/0, /*Op*/3, /*Type*/GILLT_s64,
        GIM_CheckMemoryAddressSpace, /*MI*/0, /*MMO*/0, /*NumAddrSpace*/1, /*AddrSpace*/3,
        GIM_CheckRegBankForClass, /*MI*/0, /*Op*/0, /*RC*/GIMT_Encode2(AMDGPU::AV_64RegClassID),
        GIM_CheckPointerToAny, /*MI*/0, /*Op*/2, /*SizeInBits*/0,
        GIM_CheckComplexPattern, /*MI*/0, /*Op*/2, /*Renderer*/GIMT_Encode2(0), GIMT_Encode2(GICP_gi_ds_1addr_1offset),
        // (intrinsic_w_chain:{ *:[f64] } 1964:{ *:[iPTR] }, (DS1Addr1Offset:{ *:[iPTR] } i32:{ *:[i32] }:$ptr, i32:{ *:[i32] }:$offset), f64:{ *:[f64] }:$value)<<P:Predicate_int_amdgcn_flat_atomic_fadd_local_addrspace>>  =>  (DS_ADD_RTN_F64:{ *:[f64] } ?:{ *:[i32] }:$ptr, anonymous_15036:{ *:[f64] }:$value, offset:{ *:[i32] }:$offset, 0:{ *:[i1] })
        GIR_BuildMI, /*InsnID*/0, /*Opcode*/GIMT_Encode2(AMDGPU::DS_ADD_RTN_F64),
        GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/0, // DstI[vdst]
        GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/0, // ptr
        GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/3, // value
        GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/1, // offset
        GIR_AddImm8, /*InsnID*/0, /*Imm*/0,
        GIR_MergeMemOperands, /*InsnID*/0, /*NumInsns*/1, /*MergeInsnID's*/0,
        GIR_ConstrainSelectedInstOperands, /*InsnID*/0,
        GIR_EraseFromParent, /*InsnID*/0,
        // GIR_Coverage, 7081,
        GIR_Done,
      // Label 3295: @211969
      GIM_Try, /*On fail goto*//*Label 3296*/ GIMT_Encode4(212045), // Rule ID 3257 //
        GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasAtomicCSubNoRtnInsts_isGFX12Plus),
        GIM_CheckIntrinsicID, /*MI*/0, /*Op*/1, GIMT_Encode2(Intrinsic::amdgcn_atomic_cond_sub_u32),
        GIM_CheckType, /*MI*/0, /*Op*/0, /*Type*/GILLT_s32,
        GIM_CheckType, /*MI*/0, /*Op*/3, /*Type*/GILLT_s32,
        GIM_CheckMemoryAddressSpace, /*MI*/0, /*MMO*/0, /*NumAddrSpace*/3, /*AddrSpace*/1, /*AddrSpace*/4, /*AddrSpace*/6,
        GIM_CheckHasNoUse, /*MI*/0,
        GIM_CheckPointerToAny, /*MI*/0, /*Op*/2, /*SizeInBits*/0,
        GIM_CheckComplexPattern, /*MI*/0, /*Op*/2, /*Renderer*/GIMT_Encode2(0), GIMT_Encode2(GICP_gi_global_saddr),
        // (intrinsic_w_chain:{ *:[i32] } 1879:{ *:[iPTR] }, (GlobalSAddr:{ *:[iPTR] } SReg_64:{ *:[i64] }:$saddr, VGPR_32:{ *:[i32] }:$voffset, i32:{ *:[i32] }:$offset), i32:{ *:[i32] }:$data)<<P:Predicate_int_amdgcn_atomic_cond_sub_u32_noret_global_addrspace>>  =>  (GLOBAL_ATOMIC_COND_SUB_U32_SADDR ?:{ *:[i32] }:$voffset, anonymous_15037:{ *:[i32] }:$data, ?:{ *:[i64] }:$saddr, ?:{ *:[i32] }:$offset)
        GIR_BuildMI, /*InsnID*/0, /*Opcode*/GIMT_Encode2(AMDGPU::GLOBAL_ATOMIC_COND_SUB_U32_SADDR),
        GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/1, // voffset
        GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/3, // data
        GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/0, // saddr
        GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/2, // offset
        GIR_AddImm8, /*InsnID*/0, /*Imm*/0,
        GIR_MergeMemOperands, /*InsnID*/0, /*NumInsns*/1, /*MergeInsnID's*/0,
        GIR_ConstrainSelectedInstOperands, /*InsnID*/0,
        GIR_EraseFromParent, /*InsnID*/0,
        // GIR_Coverage, 3257,
        GIR_Done,
      // Label 3296: @212045
      GIM_Try, /*On fail goto*//*Label 3297*/ GIMT_Encode4(212121), // Rule ID 3337 //
        GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasAtomicFaddNoRtnInsts),
        GIM_CheckIntrinsicID, /*MI*/0, /*Op*/1, GIMT_Encode2(Intrinsic::amdgcn_flat_atomic_fadd),
        GIM_CheckType, /*MI*/0, /*Op*/0, /*Type*/GILLT_s32,
        GIM_CheckType, /*MI*/0, /*Op*/3, /*Type*/GILLT_s32,
        GIM_CheckMemoryAddressSpace, /*MI*/0, /*MMO*/0, /*NumAddrSpace*/3, /*AddrSpace*/1, /*AddrSpace*/4, /*AddrSpace*/6,
        GIM_CheckHasNoUse, /*MI*/0,
        GIM_CheckPointerToAny, /*MI*/0, /*Op*/2, /*SizeInBits*/0,
        GIM_CheckComplexPattern, /*MI*/0, /*Op*/2, /*Renderer*/GIMT_Encode2(0), GIMT_Encode2(GICP_gi_global_saddr),
        // (intrinsic_w_chain:{ *:[f32] } 1964:{ *:[iPTR] }, (GlobalSAddr:{ *:[iPTR] } SReg_64:{ *:[i64] }:$saddr, VGPR_32:{ *:[i32] }:$voffset, i32:{ *:[i32] }:$offset), f32:{ *:[f32] }:$data)<<P:Predicate_int_amdgcn_flat_atomic_fadd_noret_global_addrspace>>  =>  (GLOBAL_ATOMIC_ADD_F32_SADDR ?:{ *:[i32] }:$voffset, anonymous_15037:{ *:[f32] }:$data, ?:{ *:[i64] }:$saddr, ?:{ *:[i32] }:$offset)
        GIR_BuildMI, /*InsnID*/0, /*Opcode*/GIMT_Encode2(AMDGPU::GLOBAL_ATOMIC_ADD_F32_SADDR),
        GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/1, // voffset
        GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/3, // data
        GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/0, // saddr
        GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/2, // offset
        GIR_AddImm8, /*InsnID*/0, /*Imm*/0,
        GIR_MergeMemOperands, /*InsnID*/0, /*NumInsns*/1, /*MergeInsnID's*/0,
        GIR_ConstrainSelectedInstOperands, /*InsnID*/0,
        GIR_EraseFromParent, /*InsnID*/0,
        // GIR_Coverage, 3337,
        GIR_Done,
      // Label 3297: @212121
      GIM_Try, /*On fail goto*//*Label 3298*/ GIMT_Encode4(212197), // Rule ID 3339 //
        GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasAtomicFaddNoRtnInsts),
        GIM_CheckIntrinsicID, /*MI*/0, /*Op*/1, GIMT_Encode2(Intrinsic::amdgcn_global_atomic_fadd),
        GIM_CheckType, /*MI*/0, /*Op*/0, /*Type*/GILLT_s32,
        GIM_CheckType, /*MI*/0, /*Op*/3, /*Type*/GILLT_s32,
        GIM_CheckMemoryAddressSpace, /*MI*/0, /*MMO*/0, /*NumAddrSpace*/3, /*AddrSpace*/1, /*AddrSpace*/4, /*AddrSpace*/6,
        GIM_CheckHasNoUse, /*MI*/0,
        GIM_CheckPointerToAny, /*MI*/0, /*Op*/2, /*SizeInBits*/0,
        GIM_CheckComplexPattern, /*MI*/0, /*Op*/2, /*Renderer*/GIMT_Encode2(0), GIMT_Encode2(GICP_gi_global_saddr),
        // (intrinsic_w_chain:{ *:[f32] } 1978:{ *:[iPTR] }, (GlobalSAddr:{ *:[iPTR] } SReg_64:{ *:[i64] }:$saddr, VGPR_32:{ *:[i32] }:$voffset, i32:{ *:[i32] }:$offset), f32:{ *:[f32] }:$data)<<P:Predicate_int_amdgcn_global_atomic_fadd_noret_global_addrspace>>  =>  (GLOBAL_ATOMIC_ADD_F32_SADDR ?:{ *:[i32] }:$voffset, anonymous_15037:{ *:[f32] }:$data, ?:{ *:[i64] }:$saddr, ?:{ *:[i32] }:$offset)
        GIR_BuildMI, /*InsnID*/0, /*Opcode*/GIMT_Encode2(AMDGPU::GLOBAL_ATOMIC_ADD_F32_SADDR),
        GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/1, // voffset
        GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/3, // data
        GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/0, // saddr
        GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/2, // offset
        GIR_AddImm8, /*InsnID*/0, /*Imm*/0,
        GIR_MergeMemOperands, /*InsnID*/0, /*NumInsns*/1, /*MergeInsnID's*/0,
        GIR_ConstrainSelectedInstOperands, /*InsnID*/0,
        GIR_EraseFromParent, /*InsnID*/0,
        // GIR_Coverage, 3339,
        GIR_Done,
      // Label 3298: @212197
      GIM_Try, /*On fail goto*//*Label 3299*/ GIMT_Encode4(212273), // Rule ID 3341 //
        GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasAtomicBufferGlobalPkAddF16NoRtnInsts),
        GIM_CheckIntrinsicID, /*MI*/0, /*Op*/1, GIMT_Encode2(Intrinsic::amdgcn_flat_atomic_fadd),
        GIM_CheckType, /*MI*/0, /*Op*/0, /*Type*/GILLT_v2s16,
        GIM_CheckType, /*MI*/0, /*Op*/3, /*Type*/GILLT_v2s16,
        GIM_CheckMemoryAddressSpace, /*MI*/0, /*MMO*/0, /*NumAddrSpace*/3, /*AddrSpace*/1, /*AddrSpace*/4, /*AddrSpace*/6,
        GIM_CheckHasNoUse, /*MI*/0,
        GIM_CheckPointerToAny, /*MI*/0, /*Op*/2, /*SizeInBits*/0,
        GIM_CheckComplexPattern, /*MI*/0, /*Op*/2, /*Renderer*/GIMT_Encode2(0), GIMT_Encode2(GICP_gi_global_saddr),
        // (intrinsic_w_chain:{ *:[v2f16] } 1964:{ *:[iPTR] }, (GlobalSAddr:{ *:[iPTR] } SReg_64:{ *:[i64] }:$saddr, VGPR_32:{ *:[i32] }:$voffset, i32:{ *:[i32] }:$offset), v2f16:{ *:[v2f16] }:$data)<<P:Predicate_int_amdgcn_flat_atomic_fadd_noret_global_addrspace>>  =>  (GLOBAL_ATOMIC_PK_ADD_F16_SADDR ?:{ *:[i32] }:$voffset, anonymous_15037:{ *:[v2f16] }:$data, ?:{ *:[i64] }:$saddr, ?:{ *:[i32] }:$offset)
        GIR_BuildMI, /*InsnID*/0, /*Opcode*/GIMT_Encode2(AMDGPU::GLOBAL_ATOMIC_PK_ADD_F16_SADDR),
        GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/1, // voffset
        GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/3, // data
        GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/0, // saddr
        GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/2, // offset
        GIR_AddImm8, /*InsnID*/0, /*Imm*/0,
        GIR_MergeMemOperands, /*InsnID*/0, /*NumInsns*/1, /*MergeInsnID's*/0,
        GIR_ConstrainSelectedInstOperands, /*InsnID*/0,
        GIR_EraseFromParent, /*InsnID*/0,
        // GIR_Coverage, 3341,
        GIR_Done,
      // Label 3299: @212273
      GIM_Try, /*On fail goto*//*Label 3300*/ GIMT_Encode4(212349), // Rule ID 3343 //
        GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasAtomicBufferGlobalPkAddF16NoRtnInsts),
        GIM_CheckIntrinsicID, /*MI*/0, /*Op*/1, GIMT_Encode2(Intrinsic::amdgcn_global_atomic_fadd),
        GIM_CheckType, /*MI*/0, /*Op*/0, /*Type*/GILLT_v2s16,
        GIM_CheckType, /*MI*/0, /*Op*/3, /*Type*/GILLT_v2s16,
        GIM_CheckMemoryAddressSpace, /*MI*/0, /*MMO*/0, /*NumAddrSpace*/3, /*AddrSpace*/1, /*AddrSpace*/4, /*AddrSpace*/6,
        GIM_CheckHasNoUse, /*MI*/0,
        GIM_CheckPointerToAny, /*MI*/0, /*Op*/2, /*SizeInBits*/0,
        GIM_CheckComplexPattern, /*MI*/0, /*Op*/2, /*Renderer*/GIMT_Encode2(0), GIMT_Encode2(GICP_gi_global_saddr),
        // (intrinsic_w_chain:{ *:[v2f16] } 1978:{ *:[iPTR] }, (GlobalSAddr:{ *:[iPTR] } SReg_64:{ *:[i64] }:$saddr, VGPR_32:{ *:[i32] }:$voffset, i32:{ *:[i32] }:$offset), v2f16:{ *:[v2f16] }:$data)<<P:Predicate_int_amdgcn_global_atomic_fadd_noret_global_addrspace>>  =>  (GLOBAL_ATOMIC_PK_ADD_F16_SADDR ?:{ *:[i32] }:$voffset, anonymous_15037:{ *:[v2f16] }:$data, ?:{ *:[i64] }:$saddr, ?:{ *:[i32] }:$offset)
        GIR_BuildMI, /*InsnID*/0, /*Opcode*/GIMT_Encode2(AMDGPU::GLOBAL_ATOMIC_PK_ADD_F16_SADDR),
        GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/1, // voffset
        GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/3, // data
        GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/0, // saddr
        GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/2, // offset
        GIR_AddImm8, /*InsnID*/0, /*Imm*/0,
        GIR_MergeMemOperands, /*InsnID*/0, /*NumInsns*/1, /*MergeInsnID's*/0,
        GIR_ConstrainSelectedInstOperands, /*InsnID*/0,
        GIR_EraseFromParent, /*InsnID*/0,
        // GIR_Coverage, 3343,
        GIR_Done,
      // Label 3300: @212349
      GIM_Try, /*On fail goto*//*Label 3301*/ GIMT_Encode4(212425), // Rule ID 3367 //
        GIM_CheckFeatures, GIMT_Encode2(GIFBS_isGFX90APlus),
        GIM_CheckIntrinsicID, /*MI*/0, /*Op*/1, GIMT_Encode2(Intrinsic::amdgcn_flat_atomic_fadd),
        GIM_CheckType, /*MI*/0, /*Op*/0, /*Type*/GILLT_s64,
        GIM_CheckType, /*MI*/0, /*Op*/3, /*Type*/GILLT_s64,
        GIM_CheckMemoryAddressSpace, /*MI*/0, /*MMO*/0, /*NumAddrSpace*/3, /*AddrSpace*/1, /*AddrSpace*/4, /*AddrSpace*/6,
        GIM_CheckHasNoUse, /*MI*/0,
        GIM_CheckPointerToAny, /*MI*/0, /*Op*/2, /*SizeInBits*/0,
        GIM_CheckComplexPattern, /*MI*/0, /*Op*/2, /*Renderer*/GIMT_Encode2(0), GIMT_Encode2(GICP_gi_global_saddr),
        // (intrinsic_w_chain:{ *:[f64] } 1964:{ *:[iPTR] }, (GlobalSAddr:{ *:[iPTR] } SReg_64:{ *:[i64] }:$saddr, VGPR_32:{ *:[i32] }:$voffset, i32:{ *:[i32] }:$offset), f64:{ *:[f64] }:$data)<<P:Predicate_int_amdgcn_flat_atomic_fadd_noret_global_addrspace>>  =>  (GLOBAL_ATOMIC_ADD_F64_SADDR ?:{ *:[i32] }:$voffset, anonymous_15036:{ *:[f64] }:$data, ?:{ *:[i64] }:$saddr, ?:{ *:[i32] }:$offset)
        GIR_BuildMI, /*InsnID*/0, /*Opcode*/GIMT_Encode2(AMDGPU::GLOBAL_ATOMIC_ADD_F64_SADDR),
        GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/1, // voffset
        GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/3, // data
        GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/0, // saddr
        GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/2, // offset
        GIR_AddImm8, /*InsnID*/0, /*Imm*/0,
        GIR_MergeMemOperands, /*InsnID*/0, /*NumInsns*/1, /*MergeInsnID's*/0,
        GIR_ConstrainSelectedInstOperands, /*InsnID*/0,
        GIR_EraseFromParent, /*InsnID*/0,
        // GIR_Coverage, 3367,
        GIR_Done,
      // Label 3301: @212425
      GIM_Try, /*On fail goto*//*Label 3302*/ GIMT_Encode4(212501), // Rule ID 3371 //
        GIM_CheckFeatures, GIMT_Encode2(GIFBS_isGFX90APlus),
        GIM_CheckIntrinsicID, /*MI*/0, /*Op*/1, GIMT_Encode2(Intrinsic::amdgcn_global_atomic_fadd),
        GIM_CheckType, /*MI*/0, /*Op*/0, /*Type*/GILLT_s64,
        GIM_CheckType, /*MI*/0, /*Op*/3, /*Type*/GILLT_s64,
        GIM_CheckMemoryAddressSpace, /*MI*/0, /*MMO*/0, /*NumAddrSpace*/3, /*AddrSpace*/1, /*AddrSpace*/4, /*AddrSpace*/6,
        GIM_CheckHasNoUse, /*MI*/0,
        GIM_CheckPointerToAny, /*MI*/0, /*Op*/2, /*SizeInBits*/0,
        GIM_CheckComplexPattern, /*MI*/0, /*Op*/2, /*Renderer*/GIMT_Encode2(0), GIMT_Encode2(GICP_gi_global_saddr),
        // (intrinsic_w_chain:{ *:[f64] } 1978:{ *:[iPTR] }, (GlobalSAddr:{ *:[iPTR] } SReg_64:{ *:[i64] }:$saddr, VGPR_32:{ *:[i32] }:$voffset, i32:{ *:[i32] }:$offset), f64:{ *:[f64] }:$data)<<P:Predicate_int_amdgcn_global_atomic_fadd_noret_global_addrspace>>  =>  (GLOBAL_ATOMIC_ADD_F64_SADDR ?:{ *:[i32] }:$voffset, anonymous_15036:{ *:[f64] }:$data, ?:{ *:[i64] }:$saddr, ?:{ *:[i32] }:$offset)
        GIR_BuildMI, /*InsnID*/0, /*Opcode*/GIMT_Encode2(AMDGPU::GLOBAL_ATOMIC_ADD_F64_SADDR),
        GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/1, // voffset
        GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/3, // data
        GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/0, // saddr
        GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/2, // offset
        GIR_AddImm8, /*InsnID*/0, /*Imm*/0,
        GIR_MergeMemOperands, /*InsnID*/0, /*NumInsns*/1, /*MergeInsnID's*/0,
        GIR_ConstrainSelectedInstOperands, /*InsnID*/0,
        GIR_EraseFromParent, /*InsnID*/0,
        // GIR_Coverage, 3371,
        GIR_Done,
      // Label 3302: @212501
      GIM_Try, /*On fail goto*//*Label 3303*/ GIMT_Encode4(212570), // Rule ID 3201 //
        GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasAtomicCSubNoRtnInsts),
        GIM_CheckIntrinsicID, /*MI*/0, /*Op*/1, GIMT_Encode2(Intrinsic::amdgcn_global_atomic_csub),
        GIM_CheckType, /*MI*/0, /*Op*/0, /*Type*/GILLT_s32,
        GIM_CheckType, /*MI*/0, /*Op*/3, /*Type*/GILLT_s32,
        GIM_CheckHasNoUse, /*MI*/0,
        GIM_CheckPointerToAny, /*MI*/0, /*Op*/2, /*SizeInBits*/0,
        GIM_CheckComplexPattern, /*MI*/0, /*Op*/2, /*Renderer*/GIMT_Encode2(0), GIMT_Encode2(GICP_gi_global_saddr),
        // (intrinsic_w_chain:{ *:[i32] } 1977:{ *:[iPTR] }, (GlobalSAddr:{ *:[iPTR] } SReg_64:{ *:[i64] }:$saddr, VGPR_32:{ *:[i32] }:$voffset, i32:{ *:[i32] }:$offset), i32:{ *:[i32] }:$data)<<P:Predicate_int_amdgcn_global_atomic_csub_noret>>  =>  (GLOBAL_ATOMIC_CSUB_SADDR ?:{ *:[i32] }:$voffset, anonymous_15037:{ *:[i32] }:$data, ?:{ *:[i64] }:$saddr, ?:{ *:[i32] }:$offset)
        GIR_BuildMI, /*InsnID*/0, /*Opcode*/GIMT_Encode2(AMDGPU::GLOBAL_ATOMIC_CSUB_SADDR),
        GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/1, // voffset
        GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/3, // data
        GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/0, // saddr
        GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/2, // offset
        GIR_AddImm8, /*InsnID*/0, /*Imm*/0,
        GIR_MergeMemOperands, /*InsnID*/0, /*NumInsns*/1, /*MergeInsnID's*/0,
        GIR_ConstrainSelectedInstOperands, /*InsnID*/0,
        GIR_EraseFromParent, /*InsnID*/0,
        // GIR_Coverage, 3201,
        GIR_Done,
      // Label 3303: @212570
      GIM_Try, /*On fail goto*//*Label 3304*/ GIMT_Encode4(212639), // Rule ID 3287 //
        GIM_CheckFeatures, GIMT_Encode2(GIFBS_isGFX10GFX11),
        GIM_CheckIntrinsicID, /*MI*/0, /*Op*/1, GIMT_Encode2(Intrinsic::amdgcn_global_atomic_fmin),
        GIM_CheckType, /*MI*/0, /*Op*/0, /*Type*/GILLT_s32,
        GIM_CheckType, /*MI*/0, /*Op*/3, /*Type*/GILLT_s32,
        GIM_CheckHasNoUse, /*MI*/0,
        GIM_CheckPointerToAny, /*MI*/0, /*Op*/2, /*SizeInBits*/0,
        GIM_CheckComplexPattern, /*MI*/0, /*Op*/2, /*Renderer*/GIMT_Encode2(0), GIMT_Encode2(GICP_gi_global_saddr),
        // (intrinsic_w_chain:{ *:[f32] } 1982:{ *:[iPTR] }, (GlobalSAddr:{ *:[iPTR] } SReg_64:{ *:[i64] }:$saddr, VGPR_32:{ *:[i32] }:$voffset, i32:{ *:[i32] }:$offset), f32:{ *:[f32] }:$data)<<P:Predicate_int_amdgcn_global_atomic_fmin_noret>>  =>  (GLOBAL_ATOMIC_FMIN_SADDR ?:{ *:[i32] }:$voffset, anonymous_15037:{ *:[f32] }:$data, ?:{ *:[i64] }:$saddr, ?:{ *:[i32] }:$offset)
        GIR_BuildMI, /*InsnID*/0, /*Opcode*/GIMT_Encode2(AMDGPU::GLOBAL_ATOMIC_FMIN_SADDR),
        GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/1, // voffset
        GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/3, // data
        GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/0, // saddr
        GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/2, // offset
        GIR_AddImm8, /*InsnID*/0, /*Imm*/0,
        GIR_MergeMemOperands, /*InsnID*/0, /*NumInsns*/1, /*MergeInsnID's*/0,
        GIR_ConstrainSelectedInstOperands, /*InsnID*/0,
        GIR_EraseFromParent, /*InsnID*/0,
        // GIR_Coverage, 3287,
        GIR_Done,
      // Label 3304: @212639
      GIM_Try, /*On fail goto*//*Label 3305*/ GIMT_Encode4(212708), // Rule ID 3291 //
        GIM_CheckFeatures, GIMT_Encode2(GIFBS_isGFX10GFX11),
        GIM_CheckIntrinsicID, /*MI*/0, /*Op*/1, GIMT_Encode2(Intrinsic::amdgcn_global_atomic_fmax),
        GIM_CheckType, /*MI*/0, /*Op*/0, /*Type*/GILLT_s32,
        GIM_CheckType, /*MI*/0, /*Op*/3, /*Type*/GILLT_s32,
        GIM_CheckHasNoUse, /*MI*/0,
        GIM_CheckPointerToAny, /*MI*/0, /*Op*/2, /*SizeInBits*/0,
        GIM_CheckComplexPattern, /*MI*/0, /*Op*/2, /*Renderer*/GIMT_Encode2(0), GIMT_Encode2(GICP_gi_global_saddr),
        // (intrinsic_w_chain:{ *:[f32] } 1980:{ *:[iPTR] }, (GlobalSAddr:{ *:[iPTR] } SReg_64:{ *:[i64] }:$saddr, VGPR_32:{ *:[i32] }:$voffset, i32:{ *:[i32] }:$offset), f32:{ *:[f32] }:$data)<<P:Predicate_int_amdgcn_global_atomic_fmax_noret>>  =>  (GLOBAL_ATOMIC_FMAX_SADDR ?:{ *:[i32] }:$voffset, anonymous_15037:{ *:[f32] }:$data, ?:{ *:[i64] }:$saddr, ?:{ *:[i32] }:$offset)
        GIR_BuildMI, /*InsnID*/0, /*Opcode*/GIMT_Encode2(AMDGPU::GLOBAL_ATOMIC_FMAX_SADDR),
        GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/1, // voffset
        GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/3, // data
        GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/0, // saddr
        GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/2, // offset
        GIR_AddImm8, /*InsnID*/0, /*Imm*/0,
        GIR_MergeMemOperands, /*InsnID*/0, /*NumInsns*/1, /*MergeInsnID's*/0,
        GIR_ConstrainSelectedInstOperands, /*InsnID*/0,
        GIR_EraseFromParent, /*InsnID*/0,
        // GIR_Coverage, 3291,
        GIR_Done,
      // Label 3305: @212708
      GIM_Try, /*On fail goto*//*Label 3306*/ GIMT_Encode4(212777), // Rule ID 3307 //
        GIM_CheckFeatures, GIMT_Encode2(GIFBS_isGFX10Only),
        GIM_CheckIntrinsicID, /*MI*/0, /*Op*/1, GIMT_Encode2(Intrinsic::amdgcn_global_atomic_fmin),
        GIM_CheckType, /*MI*/0, /*Op*/0, /*Type*/GILLT_s64,
        GIM_CheckType, /*MI*/0, /*Op*/3, /*Type*/GILLT_s64,
        GIM_CheckHasNoUse, /*MI*/0,
        GIM_CheckPointerToAny, /*MI*/0, /*Op*/2, /*SizeInBits*/0,
        GIM_CheckComplexPattern, /*MI*/0, /*Op*/2, /*Renderer*/GIMT_Encode2(0), GIMT_Encode2(GICP_gi_global_saddr),
        // (intrinsic_w_chain:{ *:[f64] } 1982:{ *:[iPTR] }, (GlobalSAddr:{ *:[iPTR] } SReg_64:{ *:[i64] }:$saddr, VGPR_32:{ *:[i32] }:$voffset, i32:{ *:[i32] }:$offset), f64:{ *:[f64] }:$data)<<P:Predicate_int_amdgcn_global_atomic_fmin_noret>>  =>  (GLOBAL_ATOMIC_FMIN_X2_SADDR ?:{ *:[i32] }:$voffset, anonymous_15036:{ *:[f64] }:$data, ?:{ *:[i64] }:$saddr, ?:{ *:[i32] }:$offset)
        GIR_BuildMI, /*InsnID*/0, /*Opcode*/GIMT_Encode2(AMDGPU::GLOBAL_ATOMIC_FMIN_X2_SADDR),
        GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/1, // voffset
        GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/3, // data
        GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/0, // saddr
        GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/2, // offset
        GIR_AddImm8, /*InsnID*/0, /*Imm*/0,
        GIR_MergeMemOperands, /*InsnID*/0, /*NumInsns*/1, /*MergeInsnID's*/0,
        GIR_ConstrainSelectedInstOperands, /*InsnID*/0,
        GIR_EraseFromParent, /*InsnID*/0,
        // GIR_Coverage, 3307,
        GIR_Done,
      // Label 3306: @212777
      GIM_Try, /*On fail goto*//*Label 3307*/ GIMT_Encode4(212846), // Rule ID 3311 //
        GIM_CheckFeatures, GIMT_Encode2(GIFBS_isGFX10Only),
        GIM_CheckIntrinsicID, /*MI*/0, /*Op*/1, GIMT_Encode2(Intrinsic::amdgcn_global_atomic_fmax),
        GIM_CheckType, /*MI*/0, /*Op*/0, /*Type*/GILLT_s64,
        GIM_CheckType, /*MI*/0, /*Op*/3, /*Type*/GILLT_s64,
        GIM_CheckHasNoUse, /*MI*/0,
        GIM_CheckPointerToAny, /*MI*/0, /*Op*/2, /*SizeInBits*/0,
        GIM_CheckComplexPattern, /*MI*/0, /*Op*/2, /*Renderer*/GIMT_Encode2(0), GIMT_Encode2(GICP_gi_global_saddr),
        // (intrinsic_w_chain:{ *:[f64] } 1980:{ *:[iPTR] }, (GlobalSAddr:{ *:[iPTR] } SReg_64:{ *:[i64] }:$saddr, VGPR_32:{ *:[i32] }:$voffset, i32:{ *:[i32] }:$offset), f64:{ *:[f64] }:$data)<<P:Predicate_int_amdgcn_global_atomic_fmax_noret>>  =>  (GLOBAL_ATOMIC_FMAX_X2_SADDR ?:{ *:[i32] }:$voffset, anonymous_15036:{ *:[f64] }:$data, ?:{ *:[i64] }:$saddr, ?:{ *:[i32] }:$offset)
        GIR_BuildMI, /*InsnID*/0, /*Opcode*/GIMT_Encode2(AMDGPU::GLOBAL_ATOMIC_FMAX_X2_SADDR),
        GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/1, // voffset
        GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/3, // data
        GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/0, // saddr
        GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/2, // offset
        GIR_AddImm8, /*InsnID*/0, /*Imm*/0,
        GIR_MergeMemOperands, /*InsnID*/0, /*NumInsns*/1, /*MergeInsnID's*/0,
        GIR_ConstrainSelectedInstOperands, /*InsnID*/0,
        GIR_EraseFromParent, /*InsnID*/0,
        // GIR_Coverage, 3311,
        GIR_Done,
      // Label 3307: @212846
      GIM_Try, /*On fail goto*//*Label 3308*/ GIMT_Encode4(212915), // Rule ID 3323 //
        GIM_CheckFeatures, GIMT_Encode2(GIFBS_isGFX12Only),
        GIM_CheckIntrinsicID, /*MI*/0, /*Op*/1, GIMT_Encode2(Intrinsic::amdgcn_global_atomic_fmin_num),
        GIM_CheckType, /*MI*/0, /*Op*/0, /*Type*/GILLT_s32,
        GIM_CheckType, /*MI*/0, /*Op*/3, /*Type*/GILLT_s32,
        GIM_CheckHasNoUse, /*MI*/0,
        GIM_CheckPointerToAny, /*MI*/0, /*Op*/2, /*SizeInBits*/0,
        GIM_CheckComplexPattern, /*MI*/0, /*Op*/2, /*Renderer*/GIMT_Encode2(0), GIMT_Encode2(GICP_gi_global_saddr),
        // (intrinsic_w_chain:{ *:[f32] } 1983:{ *:[iPTR] }, (GlobalSAddr:{ *:[iPTR] } SReg_64:{ *:[i64] }:$saddr, VGPR_32:{ *:[i32] }:$voffset, i32:{ *:[i32] }:$offset), f32:{ *:[f32] }:$data)<<P:Predicate_int_amdgcn_global_atomic_fmin_num_noret>>  =>  (GLOBAL_ATOMIC_FMIN_SADDR ?:{ *:[i32] }:$voffset, anonymous_15037:{ *:[f32] }:$data, ?:{ *:[i64] }:$saddr, ?:{ *:[i32] }:$offset)
        GIR_BuildMI, /*InsnID*/0, /*Opcode*/GIMT_Encode2(AMDGPU::GLOBAL_ATOMIC_FMIN_SADDR),
        GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/1, // voffset
        GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/3, // data
        GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/0, // saddr
        GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/2, // offset
        GIR_AddImm8, /*InsnID*/0, /*Imm*/0,
        GIR_MergeMemOperands, /*InsnID*/0, /*NumInsns*/1, /*MergeInsnID's*/0,
        GIR_ConstrainSelectedInstOperands, /*InsnID*/0,
        GIR_EraseFromParent, /*InsnID*/0,
        // GIR_Coverage, 3323,
        GIR_Done,
      // Label 3308: @212915
      GIM_Try, /*On fail goto*//*Label 3309*/ GIMT_Encode4(212984), // Rule ID 3327 //
        GIM_CheckFeatures, GIMT_Encode2(GIFBS_isGFX12Only),
        GIM_CheckIntrinsicID, /*MI*/0, /*Op*/1, GIMT_Encode2(Intrinsic::amdgcn_global_atomic_fmax_num),
        GIM_CheckType, /*MI*/0, /*Op*/0, /*Type*/GILLT_s32,
        GIM_CheckType, /*MI*/0, /*Op*/3, /*Type*/GILLT_s32,
        GIM_CheckHasNoUse, /*MI*/0,
        GIM_CheckPointerToAny, /*MI*/0, /*Op*/2, /*SizeInBits*/0,
        GIM_CheckComplexPattern, /*MI*/0, /*Op*/2, /*Renderer*/GIMT_Encode2(0), GIMT_Encode2(GICP_gi_global_saddr),
        // (intrinsic_w_chain:{ *:[f32] } 1981:{ *:[iPTR] }, (GlobalSAddr:{ *:[iPTR] } SReg_64:{ *:[i64] }:$saddr, VGPR_32:{ *:[i32] }:$voffset, i32:{ *:[i32] }:$offset), f32:{ *:[f32] }:$data)<<P:Predicate_int_amdgcn_global_atomic_fmax_num_noret>>  =>  (GLOBAL_ATOMIC_FMAX_SADDR ?:{ *:[i32] }:$voffset, anonymous_15037:{ *:[f32] }:$data, ?:{ *:[i64] }:$saddr, ?:{ *:[i32] }:$offset)
        GIR_BuildMI, /*InsnID*/0, /*Opcode*/GIMT_Encode2(AMDGPU::GLOBAL_ATOMIC_FMAX_SADDR),
        GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/1, // voffset
        GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/3, // data
        GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/0, // saddr
        GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/2, // offset
        GIR_AddImm8, /*InsnID*/0, /*Imm*/0,
        GIR_MergeMemOperands, /*InsnID*/0, /*NumInsns*/1, /*MergeInsnID's*/0,
        GIR_ConstrainSelectedInstOperands, /*InsnID*/0,
        GIR_EraseFromParent, /*InsnID*/0,
        // GIR_Coverage, 3327,
        GIR_Done,
      // Label 3309: @212984
      GIM_Try, /*On fail goto*//*Label 3310*/ GIMT_Encode4(213053), // Rule ID 3375 //
        GIM_CheckFeatures, GIMT_Encode2(GIFBS_isGFX90APlus),
        GIM_CheckIntrinsicID, /*MI*/0, /*Op*/1, GIMT_Encode2(Intrinsic::amdgcn_global_atomic_fmin),
        GIM_CheckType, /*MI*/0, /*Op*/0, /*Type*/GILLT_s64,
        GIM_CheckType, /*MI*/0, /*Op*/3, /*Type*/GILLT_s64,
        GIM_CheckHasNoUse, /*MI*/0,
        GIM_CheckPointerToAny, /*MI*/0, /*Op*/2, /*SizeInBits*/0,
        GIM_CheckComplexPattern, /*MI*/0, /*Op*/2, /*Renderer*/GIMT_Encode2(0), GIMT_Encode2(GICP_gi_global_saddr),
        // (intrinsic_w_chain:{ *:[f64] } 1982:{ *:[iPTR] }, (GlobalSAddr:{ *:[iPTR] } SReg_64:{ *:[i64] }:$saddr, VGPR_32:{ *:[i32] }:$voffset, i32:{ *:[i32] }:$offset), f64:{ *:[f64] }:$data)<<P:Predicate_int_amdgcn_global_atomic_fmin_noret>>  =>  (GLOBAL_ATOMIC_MIN_F64_SADDR ?:{ *:[i32] }:$voffset, anonymous_15036:{ *:[f64] }:$data, ?:{ *:[i64] }:$saddr, ?:{ *:[i32] }:$offset)
        GIR_BuildMI, /*InsnID*/0, /*Opcode*/GIMT_Encode2(AMDGPU::GLOBAL_ATOMIC_MIN_F64_SADDR),
        GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/1, // voffset
        GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/3, // data
        GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/0, // saddr
        GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/2, // offset
        GIR_AddImm8, /*InsnID*/0, /*Imm*/0,
        GIR_MergeMemOperands, /*InsnID*/0, /*NumInsns*/1, /*MergeInsnID's*/0,
        GIR_ConstrainSelectedInstOperands, /*InsnID*/0,
        GIR_EraseFromParent, /*InsnID*/0,
        // GIR_Coverage, 3375,
        GIR_Done,
      // Label 3310: @213053
      GIM_Try, /*On fail goto*//*Label 3311*/ GIMT_Encode4(213122), // Rule ID 3379 //
        GIM_CheckFeatures, GIMT_Encode2(GIFBS_isGFX90APlus),
        GIM_CheckIntrinsicID, /*MI*/0, /*Op*/1, GIMT_Encode2(Intrinsic::amdgcn_global_atomic_fmax),
        GIM_CheckType, /*MI*/0, /*Op*/0, /*Type*/GILLT_s64,
        GIM_CheckType, /*MI*/0, /*Op*/3, /*Type*/GILLT_s64,
        GIM_CheckHasNoUse, /*MI*/0,
        GIM_CheckPointerToAny, /*MI*/0, /*Op*/2, /*SizeInBits*/0,
        GIM_CheckComplexPattern, /*MI*/0, /*Op*/2, /*Renderer*/GIMT_Encode2(0), GIMT_Encode2(GICP_gi_global_saddr),
        // (intrinsic_w_chain:{ *:[f64] } 1980:{ *:[iPTR] }, (GlobalSAddr:{ *:[iPTR] } SReg_64:{ *:[i64] }:$saddr, VGPR_32:{ *:[i32] }:$voffset, i32:{ *:[i32] }:$offset), f64:{ *:[f64] }:$data)<<P:Predicate_int_amdgcn_global_atomic_fmax_noret>>  =>  (GLOBAL_ATOMIC_MAX_F64_SADDR ?:{ *:[i32] }:$voffset, anonymous_15036:{ *:[f64] }:$data, ?:{ *:[i64] }:$saddr, ?:{ *:[i32] }:$offset)
        GIR_BuildMI, /*InsnID*/0, /*Opcode*/GIMT_Encode2(AMDGPU::GLOBAL_ATOMIC_MAX_F64_SADDR),
        GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/1, // voffset
        GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/3, // data
        GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/0, // saddr
        GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/2, // offset
        GIR_AddImm8, /*InsnID*/0, /*Imm*/0,
        GIR_MergeMemOperands, /*InsnID*/0, /*NumInsns*/1, /*MergeInsnID's*/0,
        GIR_ConstrainSelectedInstOperands, /*InsnID*/0,
        GIR_EraseFromParent, /*InsnID*/0,
        // GIR_Coverage, 3379,
        GIR_Done,
      // Label 3311: @213122
      GIM_Try, /*On fail goto*//*Label 3312*/ GIMT_Encode4(213191), // Rule ID 3401 //
        GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasAtomicGlobalPkAddBF16Inst),
        GIM_CheckIntrinsicID, /*MI*/0, /*Op*/1, GIMT_Encode2(Intrinsic::amdgcn_global_atomic_fadd_v2bf16),
        GIM_CheckType, /*MI*/0, /*Op*/0, /*Type*/GILLT_v2s16,
        GIM_CheckType, /*MI*/0, /*Op*/3, /*Type*/GILLT_v2s16,
        GIM_CheckHasNoUse, /*MI*/0,
        GIM_CheckPointerToAny, /*MI*/0, /*Op*/2, /*SizeInBits*/0,
        GIM_CheckComplexPattern, /*MI*/0, /*Op*/2, /*Renderer*/GIMT_Encode2(0), GIMT_Encode2(GICP_gi_global_saddr),
        // (intrinsic_w_chain:{ *:[v2i16] } 1979:{ *:[iPTR] }, (GlobalSAddr:{ *:[iPTR] } SReg_64:{ *:[i64] }:$saddr, VGPR_32:{ *:[i32] }:$voffset, i32:{ *:[i32] }:$offset), v2i16:{ *:[v2i16] }:$data)<<P:Predicate_int_amdgcn_global_atomic_fadd_v2bf16_noret>>  =>  (GLOBAL_ATOMIC_PK_ADD_BF16_SADDR ?:{ *:[i32] }:$voffset, anonymous_15037:{ *:[v2i16] }:$data, ?:{ *:[i64] }:$saddr, ?:{ *:[i32] }:$offset)
        GIR_BuildMI, /*InsnID*/0, /*Opcode*/GIMT_Encode2(AMDGPU::GLOBAL_ATOMIC_PK_ADD_BF16_SADDR),
        GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/1, // voffset
        GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/3, // data
        GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/0, // saddr
        GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/2, // offset
        GIR_AddImm8, /*InsnID*/0, /*Imm*/0,
        GIR_MergeMemOperands, /*InsnID*/0, /*NumInsns*/1, /*MergeInsnID's*/0,
        GIR_ConstrainSelectedInstOperands, /*InsnID*/0,
        GIR_EraseFromParent, /*InsnID*/0,
        // GIR_Coverage, 3401,
        GIR_Done,
      // Label 3312: @213191
      GIM_Try, /*On fail goto*//*Label 3313*/ GIMT_Encode4(213274), // Rule ID 3255 //
        GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasFlatGlobalInsts_isGFX12Plus),
        GIM_CheckIntrinsicID, /*MI*/0, /*Op*/1, GIMT_Encode2(Intrinsic::amdgcn_atomic_cond_sub_u32),
        GIM_CheckType, /*MI*/0, /*Op*/0, /*Type*/GILLT_s32,
        GIM_CheckType, /*MI*/0, /*Op*/3, /*Type*/GILLT_s32,
        GIM_CheckMemoryAddressSpace, /*MI*/0, /*MMO*/0, /*NumAddrSpace*/3, /*AddrSpace*/1, /*AddrSpace*/4, /*AddrSpace*/6,
        GIM_CheckRegBankForClass, /*MI*/0, /*Op*/0, /*RC*/GIMT_Encode2(AMDGPU::AV_32RegClassID),
        GIM_CheckPointerToAny, /*MI*/0, /*Op*/2, /*SizeInBits*/0,
        GIM_CheckComplexPattern, /*MI*/0, /*Op*/2, /*Renderer*/GIMT_Encode2(0), GIMT_Encode2(GICP_gi_global_saddr),
        // (intrinsic_w_chain:{ *:[i32] } 1879:{ *:[iPTR] }, (GlobalSAddr:{ *:[iPTR] } SReg_64:{ *:[i64] }:$saddr, VGPR_32:{ *:[i32] }:$voffset, i32:{ *:[i32] }:$offset), i32:{ *:[i32] }:$data)<<P:Predicate_int_amdgcn_atomic_cond_sub_u32_global_addrspace>>  =>  (GLOBAL_ATOMIC_COND_SUB_U32_SADDR_RTN:{ *:[i32] } ?:{ *:[i32] }:$voffset, anonymous_15037:{ *:[i32] }:$data, ?:{ *:[i64] }:$saddr, ?:{ *:[i32] }:$offset)
        GIR_BuildMI, /*InsnID*/0, /*Opcode*/GIMT_Encode2(AMDGPU::GLOBAL_ATOMIC_COND_SUB_U32_SADDR_RTN),
        GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/0, // DstI[vdst]
        GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/1, // voffset
        GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/3, // data
        GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/0, // saddr
        GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/2, // offset
        GIR_AddImm8, /*InsnID*/0, /*Imm*/1,
        GIR_MergeMemOperands, /*InsnID*/0, /*NumInsns*/1, /*MergeInsnID's*/0,
        GIR_ConstrainSelectedInstOperands, /*InsnID*/0,
        GIR_EraseFromParent, /*InsnID*/0,
        // GIR_Coverage, 3255,
        GIR_Done,
      // Label 3313: @213274
      GIM_Try, /*On fail goto*//*Label 3314*/ GIMT_Encode4(213357), // Rule ID 3347 //
        GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasAtomicFaddRtnInsts),
        GIM_CheckIntrinsicID, /*MI*/0, /*Op*/1, GIMT_Encode2(Intrinsic::amdgcn_flat_atomic_fadd),
        GIM_CheckType, /*MI*/0, /*Op*/0, /*Type*/GILLT_s32,
        GIM_CheckType, /*MI*/0, /*Op*/3, /*Type*/GILLT_s32,
        GIM_CheckMemoryAddressSpace, /*MI*/0, /*MMO*/0, /*NumAddrSpace*/3, /*AddrSpace*/1, /*AddrSpace*/4, /*AddrSpace*/6,
        GIM_CheckRegBankForClass, /*MI*/0, /*Op*/0, /*RC*/GIMT_Encode2(AMDGPU::AV_32RegClassID),
        GIM_CheckPointerToAny, /*MI*/0, /*Op*/2, /*SizeInBits*/0,
        GIM_CheckComplexPattern, /*MI*/0, /*Op*/2, /*Renderer*/GIMT_Encode2(0), GIMT_Encode2(GICP_gi_global_saddr),
        // (intrinsic_w_chain:{ *:[f32] } 1964:{ *:[iPTR] }, (GlobalSAddr:{ *:[iPTR] } SReg_64:{ *:[i64] }:$saddr, VGPR_32:{ *:[i32] }:$voffset, i32:{ *:[i32] }:$offset), f32:{ *:[f32] }:$data)<<P:Predicate_int_amdgcn_flat_atomic_fadd_global_addrspace>>  =>  (GLOBAL_ATOMIC_ADD_F32_SADDR_RTN:{ *:[f32] } ?:{ *:[i32] }:$voffset, anonymous_15037:{ *:[f32] }:$data, ?:{ *:[i64] }:$saddr, ?:{ *:[i32] }:$offset)
        GIR_BuildMI, /*InsnID*/0, /*Opcode*/GIMT_Encode2(AMDGPU::GLOBAL_ATOMIC_ADD_F32_SADDR_RTN),
        GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/0, // DstI[vdst]
        GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/1, // voffset
        GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/3, // data
        GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/0, // saddr
        GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/2, // offset
        GIR_AddImm8, /*InsnID*/0, /*Imm*/1,
        GIR_MergeMemOperands, /*InsnID*/0, /*NumInsns*/1, /*MergeInsnID's*/0,
        GIR_ConstrainSelectedInstOperands, /*InsnID*/0,
        GIR_EraseFromParent, /*InsnID*/0,
        // GIR_Coverage, 3347,
        GIR_Done,
      // Label 3314: @213357
      GIM_Try, /*On fail goto*//*Label 3315*/ GIMT_Encode4(213440), // Rule ID 3349 //
        GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasAtomicFaddRtnInsts),
        GIM_CheckIntrinsicID, /*MI*/0, /*Op*/1, GIMT_Encode2(Intrinsic::amdgcn_global_atomic_fadd),
        GIM_CheckType, /*MI*/0, /*Op*/0, /*Type*/GILLT_s32,
        GIM_CheckType, /*MI*/0, /*Op*/3, /*Type*/GILLT_s32,
        GIM_CheckMemoryAddressSpace, /*MI*/0, /*MMO*/0, /*NumAddrSpace*/3, /*AddrSpace*/1, /*AddrSpace*/4, /*AddrSpace*/6,
        GIM_CheckRegBankForClass, /*MI*/0, /*Op*/0, /*RC*/GIMT_Encode2(AMDGPU::AV_32RegClassID),
        GIM_CheckPointerToAny, /*MI*/0, /*Op*/2, /*SizeInBits*/0,
        GIM_CheckComplexPattern, /*MI*/0, /*Op*/2, /*Renderer*/GIMT_Encode2(0), GIMT_Encode2(GICP_gi_global_saddr),
        // (intrinsic_w_chain:{ *:[f32] } 1978:{ *:[iPTR] }, (GlobalSAddr:{ *:[iPTR] } SReg_64:{ *:[i64] }:$saddr, VGPR_32:{ *:[i32] }:$voffset, i32:{ *:[i32] }:$offset), f32:{ *:[f32] }:$data)<<P:Predicate_int_amdgcn_global_atomic_fadd_global_addrspace>>  =>  (GLOBAL_ATOMIC_ADD_F32_SADDR_RTN:{ *:[f32] } ?:{ *:[i32] }:$voffset, anonymous_15037:{ *:[f32] }:$data, ?:{ *:[i64] }:$saddr, ?:{ *:[i32] }:$offset)
        GIR_BuildMI, /*InsnID*/0, /*Opcode*/GIMT_Encode2(AMDGPU::GLOBAL_ATOMIC_ADD_F32_SADDR_RTN),
        GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/0, // DstI[vdst]
        GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/1, // voffset
        GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/3, // data
        GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/0, // saddr
        GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/2, // offset
        GIR_AddImm8, /*InsnID*/0, /*Imm*/1,
        GIR_MergeMemOperands, /*InsnID*/0, /*NumInsns*/1, /*MergeInsnID's*/0,
        GIR_ConstrainSelectedInstOperands, /*InsnID*/0,
        GIR_EraseFromParent, /*InsnID*/0,
        // GIR_Coverage, 3349,
        GIR_Done,
      // Label 3315: @213440
      GIM_Try, /*On fail goto*//*Label 3316*/ GIMT_Encode4(213523), // Rule ID 3351 //
        GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasAtomicBufferGlobalPkAddF16Insts),
        GIM_CheckIntrinsicID, /*MI*/0, /*Op*/1, GIMT_Encode2(Intrinsic::amdgcn_flat_atomic_fadd),
        GIM_CheckType, /*MI*/0, /*Op*/0, /*Type*/GILLT_v2s16,
        GIM_CheckType, /*MI*/0, /*Op*/3, /*Type*/GILLT_v2s16,
        GIM_CheckMemoryAddressSpace, /*MI*/0, /*MMO*/0, /*NumAddrSpace*/3, /*AddrSpace*/1, /*AddrSpace*/4, /*AddrSpace*/6,
        GIM_CheckRegBankForClass, /*MI*/0, /*Op*/0, /*RC*/GIMT_Encode2(AMDGPU::AV_32RegClassID),
        GIM_CheckPointerToAny, /*MI*/0, /*Op*/2, /*SizeInBits*/0,
        GIM_CheckComplexPattern, /*MI*/0, /*Op*/2, /*Renderer*/GIMT_Encode2(0), GIMT_Encode2(GICP_gi_global_saddr),
        // (intrinsic_w_chain:{ *:[v2f16] } 1964:{ *:[iPTR] }, (GlobalSAddr:{ *:[iPTR] } SReg_64:{ *:[i64] }:$saddr, VGPR_32:{ *:[i32] }:$voffset, i32:{ *:[i32] }:$offset), v2f16:{ *:[v2f16] }:$data)<<P:Predicate_int_amdgcn_flat_atomic_fadd_global_addrspace>>  =>  (GLOBAL_ATOMIC_PK_ADD_F16_SADDR_RTN:{ *:[v2f16] } ?:{ *:[i32] }:$voffset, anonymous_15037:{ *:[v2f16] }:$data, ?:{ *:[i64] }:$saddr, ?:{ *:[i32] }:$offset)
        GIR_BuildMI, /*InsnID*/0, /*Opcode*/GIMT_Encode2(AMDGPU::GLOBAL_ATOMIC_PK_ADD_F16_SADDR_RTN),
        GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/0, // DstI[vdst]
        GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/1, // voffset
        GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/3, // data
        GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/0, // saddr
        GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/2, // offset
        GIR_AddImm8, /*InsnID*/0, /*Imm*/1,
        GIR_MergeMemOperands, /*InsnID*/0, /*NumInsns*/1, /*MergeInsnID's*/0,
        GIR_ConstrainSelectedInstOperands, /*InsnID*/0,
        GIR_EraseFromParent, /*InsnID*/0,
        // GIR_Coverage, 3351,
        GIR_Done,
      // Label 3316: @213523
      GIM_Try, /*On fail goto*//*Label 3317*/ GIMT_Encode4(213606), // Rule ID 3353 //
        GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasAtomicBufferGlobalPkAddF16Insts),
        GIM_CheckIntrinsicID, /*MI*/0, /*Op*/1, GIMT_Encode2(Intrinsic::amdgcn_global_atomic_fadd),
        GIM_CheckType, /*MI*/0, /*Op*/0, /*Type*/GILLT_v2s16,
        GIM_CheckType, /*MI*/0, /*Op*/3, /*Type*/GILLT_v2s16,
        GIM_CheckMemoryAddressSpace, /*MI*/0, /*MMO*/0, /*NumAddrSpace*/3, /*AddrSpace*/1, /*AddrSpace*/4, /*AddrSpace*/6,
        GIM_CheckRegBankForClass, /*MI*/0, /*Op*/0, /*RC*/GIMT_Encode2(AMDGPU::AV_32RegClassID),
        GIM_CheckPointerToAny, /*MI*/0, /*Op*/2, /*SizeInBits*/0,
        GIM_CheckComplexPattern, /*MI*/0, /*Op*/2, /*Renderer*/GIMT_Encode2(0), GIMT_Encode2(GICP_gi_global_saddr),
        // (intrinsic_w_chain:{ *:[v2f16] } 1978:{ *:[iPTR] }, (GlobalSAddr:{ *:[iPTR] } SReg_64:{ *:[i64] }:$saddr, VGPR_32:{ *:[i32] }:$voffset, i32:{ *:[i32] }:$offset), v2f16:{ *:[v2f16] }:$data)<<P:Predicate_int_amdgcn_global_atomic_fadd_global_addrspace>>  =>  (GLOBAL_ATOMIC_PK_ADD_F16_SADDR_RTN:{ *:[v2f16] } ?:{ *:[i32] }:$voffset, anonymous_15037:{ *:[v2f16] }:$data, ?:{ *:[i64] }:$saddr, ?:{ *:[i32] }:$offset)
        GIR_BuildMI, /*InsnID*/0, /*Opcode*/GIMT_Encode2(AMDGPU::GLOBAL_ATOMIC_PK_ADD_F16_SADDR_RTN),
        GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/0, // DstI[vdst]
        GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/1, // voffset
        GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/3, // data
        GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/0, // saddr
        GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/2, // offset
        GIR_AddImm8, /*InsnID*/0, /*Imm*/1,
        GIR_MergeMemOperands, /*InsnID*/0, /*NumInsns*/1, /*MergeInsnID's*/0,
        GIR_ConstrainSelectedInstOperands, /*InsnID*/0,
        GIR_EraseFromParent, /*InsnID*/0,
        // GIR_Coverage, 3353,
        GIR_Done,
      // Label 3317: @213606
      GIM_Try, /*On fail goto*//*Label 3318*/ GIMT_Encode4(213689), // Rule ID 3369 //
        GIM_CheckFeatures, GIMT_Encode2(GIFBS_isGFX90APlus),
        GIM_CheckIntrinsicID, /*MI*/0, /*Op*/1, GIMT_Encode2(Intrinsic::amdgcn_flat_atomic_fadd),
        GIM_CheckType, /*MI*/0, /*Op*/0, /*Type*/GILLT_s64,
        GIM_CheckType, /*MI*/0, /*Op*/3, /*Type*/GILLT_s64,
        GIM_CheckMemoryAddressSpace, /*MI*/0, /*MMO*/0, /*NumAddrSpace*/3, /*AddrSpace*/1, /*AddrSpace*/4, /*AddrSpace*/6,
        GIM_CheckRegBankForClass, /*MI*/0, /*Op*/0, /*RC*/GIMT_Encode2(AMDGPU::AV_64RegClassID),
        GIM_CheckPointerToAny, /*MI*/0, /*Op*/2, /*SizeInBits*/0,
        GIM_CheckComplexPattern, /*MI*/0, /*Op*/2, /*Renderer*/GIMT_Encode2(0), GIMT_Encode2(GICP_gi_global_saddr),
        // (intrinsic_w_chain:{ *:[f64] } 1964:{ *:[iPTR] }, (GlobalSAddr:{ *:[iPTR] } SReg_64:{ *:[i64] }:$saddr, VGPR_32:{ *:[i32] }:$voffset, i32:{ *:[i32] }:$offset), f64:{ *:[f64] }:$data)<<P:Predicate_int_amdgcn_flat_atomic_fadd_global_addrspace>>  =>  (GLOBAL_ATOMIC_ADD_F64_SADDR_RTN:{ *:[f64] } ?:{ *:[i32] }:$voffset, anonymous_15036:{ *:[f64] }:$data, ?:{ *:[i64] }:$saddr, ?:{ *:[i32] }:$offset)
        GIR_BuildMI, /*InsnID*/0, /*Opcode*/GIMT_Encode2(AMDGPU::GLOBAL_ATOMIC_ADD_F64_SADDR_RTN),
        GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/0, // DstI[vdst]
        GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/1, // voffset
        GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/3, // data
        GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/0, // saddr
        GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/2, // offset
        GIR_AddImm8, /*InsnID*/0, /*Imm*/1,
        GIR_MergeMemOperands, /*InsnID*/0, /*NumInsns*/1, /*MergeInsnID's*/0,
        GIR_ConstrainSelectedInstOperands, /*InsnID*/0,
        GIR_EraseFromParent, /*InsnID*/0,
        // GIR_Coverage, 3369,
        GIR_Done,
      // Label 3318: @213689
      GIM_Try, /*On fail goto*//*Label 3319*/ GIMT_Encode4(213772), // Rule ID 3373 //
        GIM_CheckFeatures, GIMT_Encode2(GIFBS_isGFX90APlus),
        GIM_CheckIntrinsicID, /*MI*/0, /*Op*/1, GIMT_Encode2(Intrinsic::amdgcn_global_atomic_fadd),
        GIM_CheckType, /*MI*/0, /*Op*/0, /*Type*/GILLT_s64,
        GIM_CheckType, /*MI*/0, /*Op*/3, /*Type*/GILLT_s64,
        GIM_CheckMemoryAddressSpace, /*MI*/0, /*MMO*/0, /*NumAddrSpace*/3, /*AddrSpace*/1, /*AddrSpace*/4, /*AddrSpace*/6,
        GIM_CheckRegBankForClass, /*MI*/0, /*Op*/0, /*RC*/GIMT_Encode2(AMDGPU::AV_64RegClassID),
        GIM_CheckPointerToAny, /*MI*/0, /*Op*/2, /*SizeInBits*/0,
        GIM_CheckComplexPattern, /*MI*/0, /*Op*/2, /*Renderer*/GIMT_Encode2(0), GIMT_Encode2(GICP_gi_global_saddr),
        // (intrinsic_w_chain:{ *:[f64] } 1978:{ *:[iPTR] }, (GlobalSAddr:{ *:[iPTR] } SReg_64:{ *:[i64] }:$saddr, VGPR_32:{ *:[i32] }:$voffset, i32:{ *:[i32] }:$offset), f64:{ *:[f64] }:$data)<<P:Predicate_int_amdgcn_global_atomic_fadd_global_addrspace>>  =>  (GLOBAL_ATOMIC_ADD_F64_SADDR_RTN:{ *:[f64] } ?:{ *:[i32] }:$voffset, anonymous_15036:{ *:[f64] }:$data, ?:{ *:[i64] }:$saddr, ?:{ *:[i32] }:$offset)
        GIR_BuildMI, /*InsnID*/0, /*Opcode*/GIMT_Encode2(AMDGPU::GLOBAL_ATOMIC_ADD_F64_SADDR_RTN),
        GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/0, // DstI[vdst]
        GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/1, // voffset
        GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/3, // data
        GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/0, // saddr
        GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/2, // offset
        GIR_AddImm8, /*InsnID*/0, /*Imm*/1,
        GIR_MergeMemOperands, /*InsnID*/0, /*NumInsns*/1, /*MergeInsnID's*/0,
        GIR_ConstrainSelectedInstOperands, /*InsnID*/0,
        GIR_EraseFromParent, /*InsnID*/0,
        // GIR_Coverage, 3373,
        GIR_Done,
      // Label 3319: @213772
      GIM_Try, /*On fail goto*//*Label 3320*/ GIMT_Encode4(213848), // Rule ID 3199 //
        GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasFlatGlobalInsts),
        GIM_CheckIntrinsicID, /*MI*/0, /*Op*/1, GIMT_Encode2(Intrinsic::amdgcn_global_atomic_csub),
        GIM_CheckType, /*MI*/0, /*Op*/0, /*Type*/GILLT_s32,
        GIM_CheckType, /*MI*/0, /*Op*/3, /*Type*/GILLT_s32,
        GIM_CheckRegBankForClass, /*MI*/0, /*Op*/0, /*RC*/GIMT_Encode2(AMDGPU::AV_32RegClassID),
        GIM_CheckPointerToAny, /*MI*/0, /*Op*/2, /*SizeInBits*/0,
        GIM_CheckComplexPattern, /*MI*/0, /*Op*/2, /*Renderer*/GIMT_Encode2(0), GIMT_Encode2(GICP_gi_global_saddr),
        // (intrinsic_w_chain:{ *:[i32] } 1977:{ *:[iPTR] }, (GlobalSAddr:{ *:[iPTR] } SReg_64:{ *:[i64] }:$saddr, VGPR_32:{ *:[i32] }:$voffset, i32:{ *:[i32] }:$offset), i32:{ *:[i32] }:$data)  =>  (GLOBAL_ATOMIC_CSUB_SADDR_RTN:{ *:[i32] } ?:{ *:[i32] }:$voffset, anonymous_15037:{ *:[i32] }:$data, ?:{ *:[i64] }:$saddr, ?:{ *:[i32] }:$offset)
        GIR_BuildMI, /*InsnID*/0, /*Opcode*/GIMT_Encode2(AMDGPU::GLOBAL_ATOMIC_CSUB_SADDR_RTN),
        GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/0, // DstI[vdst]
        GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/1, // voffset
        GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/3, // data
        GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/0, // saddr
        GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/2, // offset
        GIR_AddImm8, /*InsnID*/0, /*Imm*/1,
        GIR_MergeMemOperands, /*InsnID*/0, /*NumInsns*/1, /*MergeInsnID's*/0,
        GIR_ConstrainSelectedInstOperands, /*InsnID*/0,
        GIR_EraseFromParent, /*InsnID*/0,
        // GIR_Coverage, 3199,
        GIR_Done,
      // Label 3320: @213848
      GIM_Try, /*On fail goto*//*Label 3321*/ GIMT_Encode4(213924), // Rule ID 3259 //
        GIM_CheckFeatures, GIMT_Encode2(GIFBS_isGFX12Plus),
        GIM_CheckIntrinsicID, /*MI*/0, /*Op*/1, GIMT_Encode2(Intrinsic::amdgcn_global_atomic_ordered_add_b64),
        GIM_CheckType, /*MI*/0, /*Op*/0, /*Type*/GILLT_s64,
        GIM_CheckType, /*MI*/0, /*Op*/3, /*Type*/GILLT_s64,
        GIM_CheckRegBankForClass, /*MI*/0, /*Op*/0, /*RC*/GIMT_Encode2(AMDGPU::AV_64RegClassID),
        GIM_CheckPointerToAny, /*MI*/0, /*Op*/2, /*SizeInBits*/0,
        GIM_CheckComplexPattern, /*MI*/0, /*Op*/2, /*Renderer*/GIMT_Encode2(0), GIMT_Encode2(GICP_gi_global_saddr),
        // (intrinsic_w_chain:{ *:[i64] } 1984:{ *:[iPTR] }, (GlobalSAddr:{ *:[iPTR] } SReg_64:{ *:[i64] }:$saddr, VGPR_32:{ *:[i32] }:$voffset, i32:{ *:[i32] }:$offset), i64:{ *:[i64] }:$data)  =>  (GLOBAL_ATOMIC_ORDERED_ADD_B64_SADDR_RTN:{ *:[i64] } ?:{ *:[i32] }:$voffset, anonymous_15036:{ *:[i64] }:$data, ?:{ *:[i64] }:$saddr, ?:{ *:[i32] }:$offset)
        GIR_BuildMI, /*InsnID*/0, /*Opcode*/GIMT_Encode2(AMDGPU::GLOBAL_ATOMIC_ORDERED_ADD_B64_SADDR_RTN),
        GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/0, // DstI[vdst]
        GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/1, // voffset
        GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/3, // data
        GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/0, // saddr
        GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/2, // offset
        GIR_AddImm8, /*InsnID*/0, /*Imm*/1,
        GIR_MergeMemOperands, /*InsnID*/0, /*NumInsns*/1, /*MergeInsnID's*/0,
        GIR_ConstrainSelectedInstOperands, /*InsnID*/0,
        GIR_EraseFromParent, /*InsnID*/0,
        // GIR_Coverage, 3259,
        GIR_Done,
      // Label 3321: @213924
      GIM_Try, /*On fail goto*//*Label 3322*/ GIMT_Encode4(214000), // Rule ID 3289 //
        GIM_CheckFeatures, GIMT_Encode2(GIFBS_isGFX10GFX11),
        GIM_CheckIntrinsicID, /*MI*/0, /*Op*/1, GIMT_Encode2(Intrinsic::amdgcn_global_atomic_fmin),
        GIM_CheckType, /*MI*/0, /*Op*/0, /*Type*/GILLT_s32,
        GIM_CheckType, /*MI*/0, /*Op*/3, /*Type*/GILLT_s32,
        GIM_CheckRegBankForClass, /*MI*/0, /*Op*/0, /*RC*/GIMT_Encode2(AMDGPU::AV_32RegClassID),
        GIM_CheckPointerToAny, /*MI*/0, /*Op*/2, /*SizeInBits*/0,
        GIM_CheckComplexPattern, /*MI*/0, /*Op*/2, /*Renderer*/GIMT_Encode2(0), GIMT_Encode2(GICP_gi_global_saddr),
        // (intrinsic_w_chain:{ *:[f32] } 1982:{ *:[iPTR] }, (GlobalSAddr:{ *:[iPTR] } SReg_64:{ *:[i64] }:$saddr, VGPR_32:{ *:[i32] }:$voffset, i32:{ *:[i32] }:$offset), f32:{ *:[f32] }:$data)  =>  (GLOBAL_ATOMIC_FMIN_SADDR_RTN:{ *:[f32] } ?:{ *:[i32] }:$voffset, anonymous_15037:{ *:[f32] }:$data, ?:{ *:[i64] }:$saddr, ?:{ *:[i32] }:$offset)
        GIR_BuildMI, /*InsnID*/0, /*Opcode*/GIMT_Encode2(AMDGPU::GLOBAL_ATOMIC_FMIN_SADDR_RTN),
        GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/0, // DstI[vdst]
        GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/1, // voffset
        GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/3, // data
        GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/0, // saddr
        GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/2, // offset
        GIR_AddImm8, /*InsnID*/0, /*Imm*/1,
        GIR_MergeMemOperands, /*InsnID*/0, /*NumInsns*/1, /*MergeInsnID's*/0,
        GIR_ConstrainSelectedInstOperands, /*InsnID*/0,
        GIR_EraseFromParent, /*InsnID*/0,
        // GIR_Coverage, 3289,
        GIR_Done,
      // Label 3322: @214000
      GIM_Try, /*On fail goto*//*Label 3323*/ GIMT_Encode4(214076), // Rule ID 3293 //
        GIM_CheckFeatures, GIMT_Encode2(GIFBS_isGFX10GFX11),
        GIM_CheckIntrinsicID, /*MI*/0, /*Op*/1, GIMT_Encode2(Intrinsic::amdgcn_global_atomic_fmax),
        GIM_CheckType, /*MI*/0, /*Op*/0, /*Type*/GILLT_s32,
        GIM_CheckType, /*MI*/0, /*Op*/3, /*Type*/GILLT_s32,
        GIM_CheckRegBankForClass, /*MI*/0, /*Op*/0, /*RC*/GIMT_Encode2(AMDGPU::AV_32RegClassID),
        GIM_CheckPointerToAny, /*MI*/0, /*Op*/2, /*SizeInBits*/0,
        GIM_CheckComplexPattern, /*MI*/0, /*Op*/2, /*Renderer*/GIMT_Encode2(0), GIMT_Encode2(GICP_gi_global_saddr),
        // (intrinsic_w_chain:{ *:[f32] } 1980:{ *:[iPTR] }, (GlobalSAddr:{ *:[iPTR] } SReg_64:{ *:[i64] }:$saddr, VGPR_32:{ *:[i32] }:$voffset, i32:{ *:[i32] }:$offset), f32:{ *:[f32] }:$data)  =>  (GLOBAL_ATOMIC_FMAX_SADDR_RTN:{ *:[f32] } ?:{ *:[i32] }:$voffset, anonymous_15037:{ *:[f32] }:$data, ?:{ *:[i64] }:$saddr, ?:{ *:[i32] }:$offset)
        GIR_BuildMI, /*InsnID*/0, /*Opcode*/GIMT_Encode2(AMDGPU::GLOBAL_ATOMIC_FMAX_SADDR_RTN),
        GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/0, // DstI[vdst]
        GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/1, // voffset
        GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/3, // data
        GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/0, // saddr
        GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/2, // offset
        GIR_AddImm8, /*InsnID*/0, /*Imm*/1,
        GIR_MergeMemOperands, /*InsnID*/0, /*NumInsns*/1, /*MergeInsnID's*/0,
        GIR_ConstrainSelectedInstOperands, /*InsnID*/0,
        GIR_EraseFromParent, /*InsnID*/0,
        // GIR_Coverage, 3293,
        GIR_Done,
      // Label 3323: @214076
      GIM_Try, /*On fail goto*//*Label 3324*/ GIMT_Encode4(214152), // Rule ID 3309 //
        GIM_CheckFeatures, GIMT_Encode2(GIFBS_isGFX10Only),
        GIM_CheckIntrinsicID, /*MI*/0, /*Op*/1, GIMT_Encode2(Intrinsic::amdgcn_global_atomic_fmin),
        GIM_CheckType, /*MI*/0, /*Op*/0, /*Type*/GILLT_s64,
        GIM_CheckType, /*MI*/0, /*Op*/3, /*Type*/GILLT_s64,
        GIM_CheckRegBankForClass, /*MI*/0, /*Op*/0, /*RC*/GIMT_Encode2(AMDGPU::AV_64RegClassID),
        GIM_CheckPointerToAny, /*MI*/0, /*Op*/2, /*SizeInBits*/0,
        GIM_CheckComplexPattern, /*MI*/0, /*Op*/2, /*Renderer*/GIMT_Encode2(0), GIMT_Encode2(GICP_gi_global_saddr),
        // (intrinsic_w_chain:{ *:[f64] } 1982:{ *:[iPTR] }, (GlobalSAddr:{ *:[iPTR] } SReg_64:{ *:[i64] }:$saddr, VGPR_32:{ *:[i32] }:$voffset, i32:{ *:[i32] }:$offset), f64:{ *:[f64] }:$data)  =>  (GLOBAL_ATOMIC_FMIN_X2_SADDR_RTN:{ *:[f64] } ?:{ *:[i32] }:$voffset, anonymous_15036:{ *:[f64] }:$data, ?:{ *:[i64] }:$saddr, ?:{ *:[i32] }:$offset)
        GIR_BuildMI, /*InsnID*/0, /*Opcode*/GIMT_Encode2(AMDGPU::GLOBAL_ATOMIC_FMIN_X2_SADDR_RTN),
        GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/0, // DstI[vdst]
        GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/1, // voffset
        GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/3, // data
        GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/0, // saddr
        GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/2, // offset
        GIR_AddImm8, /*InsnID*/0, /*Imm*/1,
        GIR_MergeMemOperands, /*InsnID*/0, /*NumInsns*/1, /*MergeInsnID's*/0,
        GIR_ConstrainSelectedInstOperands, /*InsnID*/0,
        GIR_EraseFromParent, /*InsnID*/0,
        // GIR_Coverage, 3309,
        GIR_Done,
      // Label 3324: @214152
      GIM_Try, /*On fail goto*//*Label 3325*/ GIMT_Encode4(214228), // Rule ID 3313 //
        GIM_CheckFeatures, GIMT_Encode2(GIFBS_isGFX10Only),
        GIM_CheckIntrinsicID, /*MI*/0, /*Op*/1, GIMT_Encode2(Intrinsic::amdgcn_global_atomic_fmax),
        GIM_CheckType, /*MI*/0, /*Op*/0, /*Type*/GILLT_s64,
        GIM_CheckType, /*MI*/0, /*Op*/3, /*Type*/GILLT_s64,
        GIM_CheckRegBankForClass, /*MI*/0, /*Op*/0, /*RC*/GIMT_Encode2(AMDGPU::AV_64RegClassID),
        GIM_CheckPointerToAny, /*MI*/0, /*Op*/2, /*SizeInBits*/0,
        GIM_CheckComplexPattern, /*MI*/0, /*Op*/2, /*Renderer*/GIMT_Encode2(0), GIMT_Encode2(GICP_gi_global_saddr),
        // (intrinsic_w_chain:{ *:[f64] } 1980:{ *:[iPTR] }, (GlobalSAddr:{ *:[iPTR] } SReg_64:{ *:[i64] }:$saddr, VGPR_32:{ *:[i32] }:$voffset, i32:{ *:[i32] }:$offset), f64:{ *:[f64] }:$data)  =>  (GLOBAL_ATOMIC_FMAX_X2_SADDR_RTN:{ *:[f64] } ?:{ *:[i32] }:$voffset, anonymous_15036:{ *:[f64] }:$data, ?:{ *:[i64] }:$saddr, ?:{ *:[i32] }:$offset)
        GIR_BuildMI, /*InsnID*/0, /*Opcode*/GIMT_Encode2(AMDGPU::GLOBAL_ATOMIC_FMAX_X2_SADDR_RTN),
        GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/0, // DstI[vdst]
        GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/1, // voffset
        GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/3, // data
        GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/0, // saddr
        GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/2, // offset
        GIR_AddImm8, /*InsnID*/0, /*Imm*/1,
        GIR_MergeMemOperands, /*InsnID*/0, /*NumInsns*/1, /*MergeInsnID's*/0,
        GIR_ConstrainSelectedInstOperands, /*InsnID*/0,
        GIR_EraseFromParent, /*InsnID*/0,
        // GIR_Coverage, 3313,
        GIR_Done,
      // Label 3325: @214228
      GIM_Try, /*On fail goto*//*Label 3326*/ GIMT_Encode4(214304), // Rule ID 3325 //
        GIM_CheckFeatures, GIMT_Encode2(GIFBS_isGFX12Only),
        GIM_CheckIntrinsicID, /*MI*/0, /*Op*/1, GIMT_Encode2(Intrinsic::amdgcn_global_atomic_fmin_num),
        GIM_CheckType, /*MI*/0, /*Op*/0, /*Type*/GILLT_s32,
        GIM_CheckType, /*MI*/0, /*Op*/3, /*Type*/GILLT_s32,
        GIM_CheckRegBankForClass, /*MI*/0, /*Op*/0, /*RC*/GIMT_Encode2(AMDGPU::AV_32RegClassID),
        GIM_CheckPointerToAny, /*MI*/0, /*Op*/2, /*SizeInBits*/0,
        GIM_CheckComplexPattern, /*MI*/0, /*Op*/2, /*Renderer*/GIMT_Encode2(0), GIMT_Encode2(GICP_gi_global_saddr),
        // (intrinsic_w_chain:{ *:[f32] } 1983:{ *:[iPTR] }, (GlobalSAddr:{ *:[iPTR] } SReg_64:{ *:[i64] }:$saddr, VGPR_32:{ *:[i32] }:$voffset, i32:{ *:[i32] }:$offset), f32:{ *:[f32] }:$data)  =>  (GLOBAL_ATOMIC_FMIN_SADDR_RTN:{ *:[f32] } ?:{ *:[i32] }:$voffset, anonymous_15037:{ *:[f32] }:$data, ?:{ *:[i64] }:$saddr, ?:{ *:[i32] }:$offset)
        GIR_BuildMI, /*InsnID*/0, /*Opcode*/GIMT_Encode2(AMDGPU::GLOBAL_ATOMIC_FMIN_SADDR_RTN),
        GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/0, // DstI[vdst]
        GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/1, // voffset
        GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/3, // data
        GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/0, // saddr
        GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/2, // offset
        GIR_AddImm8, /*InsnID*/0, /*Imm*/1,
        GIR_MergeMemOperands, /*InsnID*/0, /*NumInsns*/1, /*MergeInsnID's*/0,
        GIR_ConstrainSelectedInstOperands, /*InsnID*/0,
        GIR_EraseFromParent, /*InsnID*/0,
        // GIR_Coverage, 3325,
        GIR_Done,
      // Label 3326: @214304
      GIM_Try, /*On fail goto*//*Label 3327*/ GIMT_Encode4(214380), // Rule ID 3329 //
        GIM_CheckFeatures, GIMT_Encode2(GIFBS_isGFX12Only),
        GIM_CheckIntrinsicID, /*MI*/0, /*Op*/1, GIMT_Encode2(Intrinsic::amdgcn_global_atomic_fmax_num),
        GIM_CheckType, /*MI*/0, /*Op*/0, /*Type*/GILLT_s32,
        GIM_CheckType, /*MI*/0, /*Op*/3, /*Type*/GILLT_s32,
        GIM_CheckRegBankForClass, /*MI*/0, /*Op*/0, /*RC*/GIMT_Encode2(AMDGPU::AV_32RegClassID),
        GIM_CheckPointerToAny, /*MI*/0, /*Op*/2, /*SizeInBits*/0,
        GIM_CheckComplexPattern, /*MI*/0, /*Op*/2, /*Renderer*/GIMT_Encode2(0), GIMT_Encode2(GICP_gi_global_saddr),
        // (intrinsic_w_chain:{ *:[f32] } 1981:{ *:[iPTR] }, (GlobalSAddr:{ *:[iPTR] } SReg_64:{ *:[i64] }:$saddr, VGPR_32:{ *:[i32] }:$voffset, i32:{ *:[i32] }:$offset), f32:{ *:[f32] }:$data)  =>  (GLOBAL_ATOMIC_FMAX_SADDR_RTN:{ *:[f32] } ?:{ *:[i32] }:$voffset, anonymous_15037:{ *:[f32] }:$data, ?:{ *:[i64] }:$saddr, ?:{ *:[i32] }:$offset)
        GIR_BuildMI, /*InsnID*/0, /*Opcode*/GIMT_Encode2(AMDGPU::GLOBAL_ATOMIC_FMAX_SADDR_RTN),
        GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/0, // DstI[vdst]
        GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/1, // voffset
        GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/3, // data
        GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/0, // saddr
        GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/2, // offset
        GIR_AddImm8, /*InsnID*/0, /*Imm*/1,
        GIR_MergeMemOperands, /*InsnID*/0, /*NumInsns*/1, /*MergeInsnID's*/0,
        GIR_ConstrainSelectedInstOperands, /*InsnID*/0,
        GIR_EraseFromParent, /*InsnID*/0,
        // GIR_Coverage, 3329,
        GIR_Done,
      // Label 3327: @214380
      GIM_Try, /*On fail goto*//*Label 3328*/ GIMT_Encode4(214456), // Rule ID 3377 //
        GIM_CheckFeatures, GIMT_Encode2(GIFBS_isGFX90APlus),
        GIM_CheckIntrinsicID, /*MI*/0, /*Op*/1, GIMT_Encode2(Intrinsic::amdgcn_global_atomic_fmin),
        GIM_CheckType, /*MI*/0, /*Op*/0, /*Type*/GILLT_s64,
        GIM_CheckType, /*MI*/0, /*Op*/3, /*Type*/GILLT_s64,
        GIM_CheckRegBankForClass, /*MI*/0, /*Op*/0, /*RC*/GIMT_Encode2(AMDGPU::AV_64RegClassID),
        GIM_CheckPointerToAny, /*MI*/0, /*Op*/2, /*SizeInBits*/0,
        GIM_CheckComplexPattern, /*MI*/0, /*Op*/2, /*Renderer*/GIMT_Encode2(0), GIMT_Encode2(GICP_gi_global_saddr),
        // (intrinsic_w_chain:{ *:[f64] } 1982:{ *:[iPTR] }, (GlobalSAddr:{ *:[iPTR] } SReg_64:{ *:[i64] }:$saddr, VGPR_32:{ *:[i32] }:$voffset, i32:{ *:[i32] }:$offset), f64:{ *:[f64] }:$data)  =>  (GLOBAL_ATOMIC_MIN_F64_SADDR_RTN:{ *:[f64] } ?:{ *:[i32] }:$voffset, anonymous_15036:{ *:[f64] }:$data, ?:{ *:[i64] }:$saddr, ?:{ *:[i32] }:$offset)
        GIR_BuildMI, /*InsnID*/0, /*Opcode*/GIMT_Encode2(AMDGPU::GLOBAL_ATOMIC_MIN_F64_SADDR_RTN),
        GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/0, // DstI[vdst]
        GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/1, // voffset
        GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/3, // data
        GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/0, // saddr
        GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/2, // offset
        GIR_AddImm8, /*InsnID*/0, /*Imm*/1,
        GIR_MergeMemOperands, /*InsnID*/0, /*NumInsns*/1, /*MergeInsnID's*/0,
        GIR_ConstrainSelectedInstOperands, /*InsnID*/0,
        GIR_EraseFromParent, /*InsnID*/0,
        // GIR_Coverage, 3377,
        GIR_Done,
      // Label 3328: @214456
      GIM_Try, /*On fail goto*//*Label 3329*/ GIMT_Encode4(214532), // Rule ID 3381 //
        GIM_CheckFeatures, GIMT_Encode2(GIFBS_isGFX90APlus),
        GIM_CheckIntrinsicID, /*MI*/0, /*Op*/1, GIMT_Encode2(Intrinsic::amdgcn_global_atomic_fmax),
        GIM_CheckType, /*MI*/0, /*Op*/0, /*Type*/GILLT_s64,
        GIM_CheckType, /*MI*/0, /*Op*/3, /*Type*/GILLT_s64,
        GIM_CheckRegBankForClass, /*MI*/0, /*Op*/0, /*RC*/GIMT_Encode2(AMDGPU::AV_64RegClassID),
        GIM_CheckPointerToAny, /*MI*/0, /*Op*/2, /*SizeInBits*/0,
        GIM_CheckComplexPattern, /*MI*/0, /*Op*/2, /*Renderer*/GIMT_Encode2(0), GIMT_Encode2(GICP_gi_global_saddr),
        // (intrinsic_w_chain:{ *:[f64] } 1980:{ *:[iPTR] }, (GlobalSAddr:{ *:[iPTR] } SReg_64:{ *:[i64] }:$saddr, VGPR_32:{ *:[i32] }:$voffset, i32:{ *:[i32] }:$offset), f64:{ *:[f64] }:$data)  =>  (GLOBAL_ATOMIC_MAX_F64_SADDR_RTN:{ *:[f64] } ?:{ *:[i32] }:$voffset, anonymous_15036:{ *:[f64] }:$data, ?:{ *:[i64] }:$saddr, ?:{ *:[i32] }:$offset)
        GIR_BuildMI, /*InsnID*/0, /*Opcode*/GIMT_Encode2(AMDGPU::GLOBAL_ATOMIC_MAX_F64_SADDR_RTN),
        GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/0, // DstI[vdst]
        GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/1, // voffset
        GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/3, // data
        GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/0, // saddr
        GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/2, // offset
        GIR_AddImm8, /*InsnID*/0, /*Imm*/1,
        GIR_MergeMemOperands, /*InsnID*/0, /*NumInsns*/1, /*MergeInsnID's*/0,
        GIR_ConstrainSelectedInstOperands, /*InsnID*/0,
        GIR_EraseFromParent, /*InsnID*/0,
        // GIR_Coverage, 3381,
        GIR_Done,
      // Label 3329: @214532
      GIM_Try, /*On fail goto*//*Label 3330*/ GIMT_Encode4(214608), // Rule ID 3403 //
        GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasAtomicGlobalPkAddBF16Inst),
        GIM_CheckIntrinsicID, /*MI*/0, /*Op*/1, GIMT_Encode2(Intrinsic::amdgcn_global_atomic_fadd_v2bf16),
        GIM_CheckType, /*MI*/0, /*Op*/0, /*Type*/GILLT_v2s16,
        GIM_CheckType, /*MI*/0, /*Op*/3, /*Type*/GILLT_v2s16,
        GIM_CheckRegBankForClass, /*MI*/0, /*Op*/0, /*RC*/GIMT_Encode2(AMDGPU::AV_32RegClassID),
        GIM_CheckPointerToAny, /*MI*/0, /*Op*/2, /*SizeInBits*/0,
        GIM_CheckComplexPattern, /*MI*/0, /*Op*/2, /*Renderer*/GIMT_Encode2(0), GIMT_Encode2(GICP_gi_global_saddr),
        // (intrinsic_w_chain:{ *:[v2i16] } 1979:{ *:[iPTR] }, (GlobalSAddr:{ *:[iPTR] } SReg_64:{ *:[i64] }:$saddr, VGPR_32:{ *:[i32] }:$voffset, i32:{ *:[i32] }:$offset), v2i16:{ *:[v2i16] }:$data)  =>  (GLOBAL_ATOMIC_PK_ADD_BF16_SADDR_RTN:{ *:[v2i16] } ?:{ *:[i32] }:$voffset, anonymous_15037:{ *:[v2i16] }:$data, ?:{ *:[i64] }:$saddr, ?:{ *:[i32] }:$offset)
        GIR_BuildMI, /*InsnID*/0, /*Opcode*/GIMT_Encode2(AMDGPU::GLOBAL_ATOMIC_PK_ADD_BF16_SADDR_RTN),
        GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/0, // DstI[vdst]
        GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/1, // voffset
        GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/3, // data
        GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/0, // saddr
        GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/2, // offset
        GIR_AddImm8, /*InsnID*/0, /*Imm*/1,
        GIR_MergeMemOperands, /*InsnID*/0, /*NumInsns*/1, /*MergeInsnID's*/0,
        GIR_ConstrainSelectedInstOperands, /*InsnID*/0,
        GIR_EraseFromParent, /*InsnID*/0,
        // GIR_Coverage, 3403,
        GIR_Done,
      // Label 3330: @214608
      GIM_Try, /*On fail goto*//*Label 3331*/ GIMT_Encode4(214679), // Rule ID 3256 //
        GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasAtomicCSubNoRtnInsts_isGFX12Plus),
        GIM_CheckIntrinsicID, /*MI*/0, /*Op*/1, GIMT_Encode2(Intrinsic::amdgcn_atomic_cond_sub_u32),
        GIM_CheckType, /*MI*/0, /*Op*/0, /*Type*/GILLT_s32,
        GIM_CheckType, /*MI*/0, /*Op*/3, /*Type*/GILLT_s32,
        GIM_CheckMemoryAddressSpace, /*MI*/0, /*MMO*/0, /*NumAddrSpace*/3, /*AddrSpace*/1, /*AddrSpace*/4, /*AddrSpace*/6,
        GIM_CheckHasNoUse, /*MI*/0,
        GIM_CheckPointerToAny, /*MI*/0, /*Op*/2, /*SizeInBits*/0,
        GIM_CheckComplexPattern, /*MI*/0, /*Op*/2, /*Renderer*/GIMT_Encode2(0), GIMT_Encode2(GICP_gi_global_offset),
        // (intrinsic_w_chain:{ *:[i32] } 1879:{ *:[iPTR] }, (GlobalOffset:{ *:[iPTR] } i64:{ *:[i64] }:$vaddr, i32:{ *:[i32] }:$offset), i32:{ *:[i32] }:$data)<<P:Predicate_int_amdgcn_atomic_cond_sub_u32_noret_global_addrspace>>  =>  (GLOBAL_ATOMIC_COND_SUB_U32 VReg_64:{ *:[i64] }:$vaddr, anonymous_15037:{ *:[i32] }:$data, ?:{ *:[i32] }:$offset)
        GIR_BuildMI, /*InsnID*/0, /*Opcode*/GIMT_Encode2(AMDGPU::GLOBAL_ATOMIC_COND_SUB_U32),
        GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/0, // vaddr
        GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/3, // data
        GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/1, // offset
        GIR_AddImm8, /*InsnID*/0, /*Imm*/0,
        GIR_MergeMemOperands, /*InsnID*/0, /*NumInsns*/1, /*MergeInsnID's*/0,
        GIR_ConstrainSelectedInstOperands, /*InsnID*/0,
        GIR_EraseFromParent, /*InsnID*/0,
        // GIR_Coverage, 3256,
        GIR_Done,
      // Label 3331: @214679
      GIM_Try, /*On fail goto*//*Label 3332*/ GIMT_Encode4(214750), // Rule ID 3336 //
        GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasAtomicFaddNoRtnInsts),
        GIM_CheckIntrinsicID, /*MI*/0, /*Op*/1, GIMT_Encode2(Intrinsic::amdgcn_flat_atomic_fadd),
        GIM_CheckType, /*MI*/0, /*Op*/0, /*Type*/GILLT_s32,
        GIM_CheckType, /*MI*/0, /*Op*/3, /*Type*/GILLT_s32,
        GIM_CheckMemoryAddressSpace, /*MI*/0, /*MMO*/0, /*NumAddrSpace*/3, /*AddrSpace*/1, /*AddrSpace*/4, /*AddrSpace*/6,
        GIM_CheckHasNoUse, /*MI*/0,
        GIM_CheckPointerToAny, /*MI*/0, /*Op*/2, /*SizeInBits*/0,
        GIM_CheckComplexPattern, /*MI*/0, /*Op*/2, /*Renderer*/GIMT_Encode2(0), GIMT_Encode2(GICP_gi_global_offset),
        // (intrinsic_w_chain:{ *:[f32] } 1964:{ *:[iPTR] }, (GlobalOffset:{ *:[iPTR] } i64:{ *:[i64] }:$vaddr, i32:{ *:[i32] }:$offset), f32:{ *:[f32] }:$data)<<P:Predicate_int_amdgcn_flat_atomic_fadd_noret_global_addrspace>>  =>  (GLOBAL_ATOMIC_ADD_F32 VReg_64:{ *:[i64] }:$vaddr, anonymous_15037:{ *:[f32] }:$data, ?:{ *:[i32] }:$offset)
        GIR_BuildMI, /*InsnID*/0, /*Opcode*/GIMT_Encode2(AMDGPU::GLOBAL_ATOMIC_ADD_F32),
        GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/0, // vaddr
        GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/3, // data
        GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/1, // offset
        GIR_AddImm8, /*InsnID*/0, /*Imm*/0,
        GIR_MergeMemOperands, /*InsnID*/0, /*NumInsns*/1, /*MergeInsnID's*/0,
        GIR_ConstrainSelectedInstOperands, /*InsnID*/0,
        GIR_EraseFromParent, /*InsnID*/0,
        // GIR_Coverage, 3336,
        GIR_Done,
      // Label 3332: @214750
      GIM_Try, /*On fail goto*//*Label 3333*/ GIMT_Encode4(214821), // Rule ID 3338 //
        GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasAtomicFaddNoRtnInsts),
        GIM_CheckIntrinsicID, /*MI*/0, /*Op*/1, GIMT_Encode2(Intrinsic::amdgcn_global_atomic_fadd),
        GIM_CheckType, /*MI*/0, /*Op*/0, /*Type*/GILLT_s32,
        GIM_CheckType, /*MI*/0, /*Op*/3, /*Type*/GILLT_s32,
        GIM_CheckMemoryAddressSpace, /*MI*/0, /*MMO*/0, /*NumAddrSpace*/3, /*AddrSpace*/1, /*AddrSpace*/4, /*AddrSpace*/6,
        GIM_CheckHasNoUse, /*MI*/0,
        GIM_CheckPointerToAny, /*MI*/0, /*Op*/2, /*SizeInBits*/0,
        GIM_CheckComplexPattern, /*MI*/0, /*Op*/2, /*Renderer*/GIMT_Encode2(0), GIMT_Encode2(GICP_gi_global_offset),
        // (intrinsic_w_chain:{ *:[f32] } 1978:{ *:[iPTR] }, (GlobalOffset:{ *:[iPTR] } i64:{ *:[i64] }:$vaddr, i32:{ *:[i32] }:$offset), f32:{ *:[f32] }:$data)<<P:Predicate_int_amdgcn_global_atomic_fadd_noret_global_addrspace>>  =>  (GLOBAL_ATOMIC_ADD_F32 VReg_64:{ *:[i64] }:$vaddr, anonymous_15037:{ *:[f32] }:$data, ?:{ *:[i32] }:$offset)
        GIR_BuildMI, /*InsnID*/0, /*Opcode*/GIMT_Encode2(AMDGPU::GLOBAL_ATOMIC_ADD_F32),
        GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/0, // vaddr
        GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/3, // data
        GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/1, // offset
        GIR_AddImm8, /*InsnID*/0, /*Imm*/0,
        GIR_MergeMemOperands, /*InsnID*/0, /*NumInsns*/1, /*MergeInsnID's*/0,
        GIR_ConstrainSelectedInstOperands, /*InsnID*/0,
        GIR_EraseFromParent, /*InsnID*/0,
        // GIR_Coverage, 3338,
        GIR_Done,
      // Label 3333: @214821
      GIM_Try, /*On fail goto*//*Label 3334*/ GIMT_Encode4(214892), // Rule ID 3340 //
        GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasAtomicBufferGlobalPkAddF16NoRtnInsts),
        GIM_CheckIntrinsicID, /*MI*/0, /*Op*/1, GIMT_Encode2(Intrinsic::amdgcn_flat_atomic_fadd),
        GIM_CheckType, /*MI*/0, /*Op*/0, /*Type*/GILLT_v2s16,
        GIM_CheckType, /*MI*/0, /*Op*/3, /*Type*/GILLT_v2s16,
        GIM_CheckMemoryAddressSpace, /*MI*/0, /*MMO*/0, /*NumAddrSpace*/3, /*AddrSpace*/1, /*AddrSpace*/4, /*AddrSpace*/6,
        GIM_CheckHasNoUse, /*MI*/0,
        GIM_CheckPointerToAny, /*MI*/0, /*Op*/2, /*SizeInBits*/0,
        GIM_CheckComplexPattern, /*MI*/0, /*Op*/2, /*Renderer*/GIMT_Encode2(0), GIMT_Encode2(GICP_gi_global_offset),
        // (intrinsic_w_chain:{ *:[v2f16] } 1964:{ *:[iPTR] }, (GlobalOffset:{ *:[iPTR] } i64:{ *:[i64] }:$vaddr, i32:{ *:[i32] }:$offset), v2f16:{ *:[v2f16] }:$data)<<P:Predicate_int_amdgcn_flat_atomic_fadd_noret_global_addrspace>>  =>  (GLOBAL_ATOMIC_PK_ADD_F16 VReg_64:{ *:[i64] }:$vaddr, anonymous_15037:{ *:[v2f16] }:$data, ?:{ *:[i32] }:$offset)
        GIR_BuildMI, /*InsnID*/0, /*Opcode*/GIMT_Encode2(AMDGPU::GLOBAL_ATOMIC_PK_ADD_F16),
        GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/0, // vaddr
        GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/3, // data
        GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/1, // offset
        GIR_AddImm8, /*InsnID*/0, /*Imm*/0,
        GIR_MergeMemOperands, /*InsnID*/0, /*NumInsns*/1, /*MergeInsnID's*/0,
        GIR_ConstrainSelectedInstOperands, /*InsnID*/0,
        GIR_EraseFromParent, /*InsnID*/0,
        // GIR_Coverage, 3340,
        GIR_Done,
      // Label 3334: @214892
      GIM_Try, /*On fail goto*//*Label 3335*/ GIMT_Encode4(214963), // Rule ID 3342 //
        GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasAtomicBufferGlobalPkAddF16NoRtnInsts),
        GIM_CheckIntrinsicID, /*MI*/0, /*Op*/1, GIMT_Encode2(Intrinsic::amdgcn_global_atomic_fadd),
        GIM_CheckType, /*MI*/0, /*Op*/0, /*Type*/GILLT_v2s16,
        GIM_CheckType, /*MI*/0, /*Op*/3, /*Type*/GILLT_v2s16,
        GIM_CheckMemoryAddressSpace, /*MI*/0, /*MMO*/0, /*NumAddrSpace*/3, /*AddrSpace*/1, /*AddrSpace*/4, /*AddrSpace*/6,
        GIM_CheckHasNoUse, /*MI*/0,
        GIM_CheckPointerToAny, /*MI*/0, /*Op*/2, /*SizeInBits*/0,
        GIM_CheckComplexPattern, /*MI*/0, /*Op*/2, /*Renderer*/GIMT_Encode2(0), GIMT_Encode2(GICP_gi_global_offset),
        // (intrinsic_w_chain:{ *:[v2f16] } 1978:{ *:[iPTR] }, (GlobalOffset:{ *:[iPTR] } i64:{ *:[i64] }:$vaddr, i32:{ *:[i32] }:$offset), v2f16:{ *:[v2f16] }:$data)<<P:Predicate_int_amdgcn_global_atomic_fadd_noret_global_addrspace>>  =>  (GLOBAL_ATOMIC_PK_ADD_F16 VReg_64:{ *:[i64] }:$vaddr, anonymous_15037:{ *:[v2f16] }:$data, ?:{ *:[i32] }:$offset)
        GIR_BuildMI, /*InsnID*/0, /*Opcode*/GIMT_Encode2(AMDGPU::GLOBAL_ATOMIC_PK_ADD_F16),
        GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/0, // vaddr
        GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/3, // data
        GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/1, // offset
        GIR_AddImm8, /*InsnID*/0, /*Imm*/0,
        GIR_MergeMemOperands, /*InsnID*/0, /*NumInsns*/1, /*MergeInsnID's*/0,
        GIR_ConstrainSelectedInstOperands, /*InsnID*/0,
        GIR_EraseFromParent, /*InsnID*/0,
        // GIR_Coverage, 3342,
        GIR_Done,
      // Label 3335: @214963
      GIM_Try, /*On fail goto*//*Label 3336*/ GIMT_Encode4(215034), // Rule ID 3366 //
        GIM_CheckFeatures, GIMT_Encode2(GIFBS_isGFX90APlus),
        GIM_CheckIntrinsicID, /*MI*/0, /*Op*/1, GIMT_Encode2(Intrinsic::amdgcn_flat_atomic_fadd),
        GIM_CheckType, /*MI*/0, /*Op*/0, /*Type*/GILLT_s64,
        GIM_CheckType, /*MI*/0, /*Op*/3, /*Type*/GILLT_s64,
        GIM_CheckMemoryAddressSpace, /*MI*/0, /*MMO*/0, /*NumAddrSpace*/3, /*AddrSpace*/1, /*AddrSpace*/4, /*AddrSpace*/6,
        GIM_CheckHasNoUse, /*MI*/0,
        GIM_CheckPointerToAny, /*MI*/0, /*Op*/2, /*SizeInBits*/0,
        GIM_CheckComplexPattern, /*MI*/0, /*Op*/2, /*Renderer*/GIMT_Encode2(0), GIMT_Encode2(GICP_gi_global_offset),
        // (intrinsic_w_chain:{ *:[f64] } 1964:{ *:[iPTR] }, (GlobalOffset:{ *:[iPTR] } i64:{ *:[i64] }:$vaddr, i32:{ *:[i32] }:$offset), f64:{ *:[f64] }:$data)<<P:Predicate_int_amdgcn_flat_atomic_fadd_noret_global_addrspace>>  =>  (GLOBAL_ATOMIC_ADD_F64 VReg_64:{ *:[i64] }:$vaddr, anonymous_15036:{ *:[f64] }:$data, ?:{ *:[i32] }:$offset)
        GIR_BuildMI, /*InsnID*/0, /*Opcode*/GIMT_Encode2(AMDGPU::GLOBAL_ATOMIC_ADD_F64),
        GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/0, // vaddr
        GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/3, // data
        GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/1, // offset
        GIR_AddImm8, /*InsnID*/0, /*Imm*/0,
        GIR_MergeMemOperands, /*InsnID*/0, /*NumInsns*/1, /*MergeInsnID's*/0,
        GIR_ConstrainSelectedInstOperands, /*InsnID*/0,
        GIR_EraseFromParent, /*InsnID*/0,
        // GIR_Coverage, 3366,
        GIR_Done,
      // Label 3336: @215034
      GIM_Try, /*On fail goto*//*Label 3337*/ GIMT_Encode4(215105), // Rule ID 3370 //
        GIM_CheckFeatures, GIMT_Encode2(GIFBS_isGFX90APlus),
        GIM_CheckIntrinsicID, /*MI*/0, /*Op*/1, GIMT_Encode2(Intrinsic::amdgcn_global_atomic_fadd),
        GIM_CheckType, /*MI*/0, /*Op*/0, /*Type*/GILLT_s64,
        GIM_CheckType, /*MI*/0, /*Op*/3, /*Type*/GILLT_s64,
        GIM_CheckMemoryAddressSpace, /*MI*/0, /*MMO*/0, /*NumAddrSpace*/3, /*AddrSpace*/1, /*AddrSpace*/4, /*AddrSpace*/6,
        GIM_CheckHasNoUse, /*MI*/0,
        GIM_CheckPointerToAny, /*MI*/0, /*Op*/2, /*SizeInBits*/0,
        GIM_CheckComplexPattern, /*MI*/0, /*Op*/2, /*Renderer*/GIMT_Encode2(0), GIMT_Encode2(GICP_gi_global_offset),
        // (intrinsic_w_chain:{ *:[f64] } 1978:{ *:[iPTR] }, (GlobalOffset:{ *:[iPTR] } i64:{ *:[i64] }:$vaddr, i32:{ *:[i32] }:$offset), f64:{ *:[f64] }:$data)<<P:Predicate_int_amdgcn_global_atomic_fadd_noret_global_addrspace>>  =>  (GLOBAL_ATOMIC_ADD_F64 VReg_64:{ *:[i64] }:$vaddr, anonymous_15036:{ *:[f64] }:$data, ?:{ *:[i32] }:$offset)
        GIR_BuildMI, /*InsnID*/0, /*Opcode*/GIMT_Encode2(AMDGPU::GLOBAL_ATOMIC_ADD_F64),
        GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/0, // vaddr
        GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/3, // data
        GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/1, // offset
        GIR_AddImm8, /*InsnID*/0, /*Imm*/0,
        GIR_MergeMemOperands, /*InsnID*/0, /*NumInsns*/1, /*MergeInsnID's*/0,
        GIR_ConstrainSelectedInstOperands, /*InsnID*/0,
        GIR_EraseFromParent, /*InsnID*/0,
        // GIR_Coverage, 3370,
        GIR_Done,
      // Label 3337: @215105
      GIM_Try, /*On fail goto*//*Label 3338*/ GIMT_Encode4(215169), // Rule ID 3200 //
        GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasAtomicCSubNoRtnInsts),
        GIM_CheckIntrinsicID, /*MI*/0, /*Op*/1, GIMT_Encode2(Intrinsic::amdgcn_global_atomic_csub),
        GIM_CheckType, /*MI*/0, /*Op*/0, /*Type*/GILLT_s32,
        GIM_CheckType, /*MI*/0, /*Op*/3, /*Type*/GILLT_s32,
        GIM_CheckHasNoUse, /*MI*/0,
        GIM_CheckPointerToAny, /*MI*/0, /*Op*/2, /*SizeInBits*/0,
        GIM_CheckComplexPattern, /*MI*/0, /*Op*/2, /*Renderer*/GIMT_Encode2(0), GIMT_Encode2(GICP_gi_global_offset),
        // (intrinsic_w_chain:{ *:[i32] } 1977:{ *:[iPTR] }, (GlobalOffset:{ *:[iPTR] } i64:{ *:[i64] }:$vaddr, i32:{ *:[i32] }:$offset), i32:{ *:[i32] }:$data)<<P:Predicate_int_amdgcn_global_atomic_csub_noret>>  =>  (GLOBAL_ATOMIC_CSUB VReg_64:{ *:[i64] }:$vaddr, anonymous_15037:{ *:[i32] }:$data, ?:{ *:[i32] }:$offset)
        GIR_BuildMI, /*InsnID*/0, /*Opcode*/GIMT_Encode2(AMDGPU::GLOBAL_ATOMIC_CSUB),
        GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/0, // vaddr
        GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/3, // data
        GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/1, // offset
        GIR_AddImm8, /*InsnID*/0, /*Imm*/0,
        GIR_MergeMemOperands, /*InsnID*/0, /*NumInsns*/1, /*MergeInsnID's*/0,
        GIR_ConstrainSelectedInstOperands, /*InsnID*/0,
        GIR_EraseFromParent, /*InsnID*/0,
        // GIR_Coverage, 3200,
        GIR_Done,
      // Label 3338: @215169
      GIM_Try, /*On fail goto*//*Label 3339*/ GIMT_Encode4(215233), // Rule ID 3286 //
        GIM_CheckFeatures, GIMT_Encode2(GIFBS_isGFX10GFX11),
        GIM_CheckIntrinsicID, /*MI*/0, /*Op*/1, GIMT_Encode2(Intrinsic::amdgcn_global_atomic_fmin),
        GIM_CheckType, /*MI*/0, /*Op*/0, /*Type*/GILLT_s32,
        GIM_CheckType, /*MI*/0, /*Op*/3, /*Type*/GILLT_s32,
        GIM_CheckHasNoUse, /*MI*/0,
        GIM_CheckPointerToAny, /*MI*/0, /*Op*/2, /*SizeInBits*/0,
        GIM_CheckComplexPattern, /*MI*/0, /*Op*/2, /*Renderer*/GIMT_Encode2(0), GIMT_Encode2(GICP_gi_global_offset),
        // (intrinsic_w_chain:{ *:[f32] } 1982:{ *:[iPTR] }, (GlobalOffset:{ *:[iPTR] } i64:{ *:[i64] }:$vaddr, i32:{ *:[i32] }:$offset), f32:{ *:[f32] }:$data)<<P:Predicate_int_amdgcn_global_atomic_fmin_noret>>  =>  (GLOBAL_ATOMIC_FMIN VReg_64:{ *:[i64] }:$vaddr, anonymous_15037:{ *:[f32] }:$data, ?:{ *:[i32] }:$offset)
        GIR_BuildMI, /*InsnID*/0, /*Opcode*/GIMT_Encode2(AMDGPU::GLOBAL_ATOMIC_FMIN),
        GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/0, // vaddr
        GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/3, // data
        GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/1, // offset
        GIR_AddImm8, /*InsnID*/0, /*Imm*/0,
        GIR_MergeMemOperands, /*InsnID*/0, /*NumInsns*/1, /*MergeInsnID's*/0,
        GIR_ConstrainSelectedInstOperands, /*InsnID*/0,
        GIR_EraseFromParent, /*InsnID*/0,
        // GIR_Coverage, 3286,
        GIR_Done,
      // Label 3339: @215233
      GIM_Try, /*On fail goto*//*Label 3340*/ GIMT_Encode4(215297), // Rule ID 3290 //
        GIM_CheckFeatures, GIMT_Encode2(GIFBS_isGFX10GFX11),
        GIM_CheckIntrinsicID, /*MI*/0, /*Op*/1, GIMT_Encode2(Intrinsic::amdgcn_global_atomic_fmax),
        GIM_CheckType, /*MI*/0, /*Op*/0, /*Type*/GILLT_s32,
        GIM_CheckType, /*MI*/0, /*Op*/3, /*Type*/GILLT_s32,
        GIM_CheckHasNoUse, /*MI*/0,
        GIM_CheckPointerToAny, /*MI*/0, /*Op*/2, /*SizeInBits*/0,
        GIM_CheckComplexPattern, /*MI*/0, /*Op*/2, /*Renderer*/GIMT_Encode2(0), GIMT_Encode2(GICP_gi_global_offset),
        // (intrinsic_w_chain:{ *:[f32] } 1980:{ *:[iPTR] }, (GlobalOffset:{ *:[iPTR] } i64:{ *:[i64] }:$vaddr, i32:{ *:[i32] }:$offset), f32:{ *:[f32] }:$data)<<P:Predicate_int_amdgcn_global_atomic_fmax_noret>>  =>  (GLOBAL_ATOMIC_FMAX VReg_64:{ *:[i64] }:$vaddr, anonymous_15037:{ *:[f32] }:$data, ?:{ *:[i32] }:$offset)
        GIR_BuildMI, /*InsnID*/0, /*Opcode*/GIMT_Encode2(AMDGPU::GLOBAL_ATOMIC_FMAX),
        GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/0, // vaddr
        GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/3, // data
        GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/1, // offset
        GIR_AddImm8, /*InsnID*/0, /*Imm*/0,
        GIR_MergeMemOperands, /*InsnID*/0, /*NumInsns*/1, /*MergeInsnID's*/0,
        GIR_ConstrainSelectedInstOperands, /*InsnID*/0,
        GIR_EraseFromParent, /*InsnID*/0,
        // GIR_Coverage, 3290,
        GIR_Done,
      // Label 3340: @215297
      GIM_Try, /*On fail goto*//*Label 3341*/ GIMT_Encode4(215361), // Rule ID 3306 //
        GIM_CheckFeatures, GIMT_Encode2(GIFBS_isGFX10Only),
        GIM_CheckIntrinsicID, /*MI*/0, /*Op*/1, GIMT_Encode2(Intrinsic::amdgcn_global_atomic_fmin),
        GIM_CheckType, /*MI*/0, /*Op*/0, /*Type*/GILLT_s64,
        GIM_CheckType, /*MI*/0, /*Op*/3, /*Type*/GILLT_s64,
        GIM_CheckHasNoUse, /*MI*/0,
        GIM_CheckPointerToAny, /*MI*/0, /*Op*/2, /*SizeInBits*/0,
        GIM_CheckComplexPattern, /*MI*/0, /*Op*/2, /*Renderer*/GIMT_Encode2(0), GIMT_Encode2(GICP_gi_global_offset),
        // (intrinsic_w_chain:{ *:[f64] } 1982:{ *:[iPTR] }, (GlobalOffset:{ *:[iPTR] } i64:{ *:[i64] }:$vaddr, i32:{ *:[i32] }:$offset), f64:{ *:[f64] }:$data)<<P:Predicate_int_amdgcn_global_atomic_fmin_noret>>  =>  (GLOBAL_ATOMIC_FMIN_X2 VReg_64:{ *:[i64] }:$vaddr, anonymous_15036:{ *:[f64] }:$data, ?:{ *:[i32] }:$offset)
        GIR_BuildMI, /*InsnID*/0, /*Opcode*/GIMT_Encode2(AMDGPU::GLOBAL_ATOMIC_FMIN_X2),
        GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/0, // vaddr
        GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/3, // data
        GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/1, // offset
        GIR_AddImm8, /*InsnID*/0, /*Imm*/0,
        GIR_MergeMemOperands, /*InsnID*/0, /*NumInsns*/1, /*MergeInsnID's*/0,
        GIR_ConstrainSelectedInstOperands, /*InsnID*/0,
        GIR_EraseFromParent, /*InsnID*/0,
        // GIR_Coverage, 3306,
        GIR_Done,
      // Label 3341: @215361
      GIM_Try, /*On fail goto*//*Label 3342*/ GIMT_Encode4(215425), // Rule ID 3310 //
        GIM_CheckFeatures, GIMT_Encode2(GIFBS_isGFX10Only),
        GIM_CheckIntrinsicID, /*MI*/0, /*Op*/1, GIMT_Encode2(Intrinsic::amdgcn_global_atomic_fmax),
        GIM_CheckType, /*MI*/0, /*Op*/0, /*Type*/GILLT_s64,
        GIM_CheckType, /*MI*/0, /*Op*/3, /*Type*/GILLT_s64,
        GIM_CheckHasNoUse, /*MI*/0,
        GIM_CheckPointerToAny, /*MI*/0, /*Op*/2, /*SizeInBits*/0,
        GIM_CheckComplexPattern, /*MI*/0, /*Op*/2, /*Renderer*/GIMT_Encode2(0), GIMT_Encode2(GICP_gi_global_offset),
        // (intrinsic_w_chain:{ *:[f64] } 1980:{ *:[iPTR] }, (GlobalOffset:{ *:[iPTR] } i64:{ *:[i64] }:$vaddr, i32:{ *:[i32] }:$offset), f64:{ *:[f64] }:$data)<<P:Predicate_int_amdgcn_global_atomic_fmax_noret>>  =>  (GLOBAL_ATOMIC_FMAX_X2 VReg_64:{ *:[i64] }:$vaddr, anonymous_15036:{ *:[f64] }:$data, ?:{ *:[i32] }:$offset)
        GIR_BuildMI, /*InsnID*/0, /*Opcode*/GIMT_Encode2(AMDGPU::GLOBAL_ATOMIC_FMAX_X2),
        GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/0, // vaddr
        GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/3, // data
        GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/1, // offset
        GIR_AddImm8, /*InsnID*/0, /*Imm*/0,
        GIR_MergeMemOperands, /*InsnID*/0, /*NumInsns*/1, /*MergeInsnID's*/0,
        GIR_ConstrainSelectedInstOperands, /*InsnID*/0,
        GIR_EraseFromParent, /*InsnID*/0,
        // GIR_Coverage, 3310,
        GIR_Done,
      // Label 3342: @215425
      GIM_Try, /*On fail goto*//*Label 3343*/ GIMT_Encode4(215489), // Rule ID 3322 //
        GIM_CheckFeatures, GIMT_Encode2(GIFBS_isGFX12Only),
        GIM_CheckIntrinsicID, /*MI*/0, /*Op*/1, GIMT_Encode2(Intrinsic::amdgcn_global_atomic_fmin_num),
        GIM_CheckType, /*MI*/0, /*Op*/0, /*Type*/GILLT_s32,
        GIM_CheckType, /*MI*/0, /*Op*/3, /*Type*/GILLT_s32,
        GIM_CheckHasNoUse, /*MI*/0,
        GIM_CheckPointerToAny, /*MI*/0, /*Op*/2, /*SizeInBits*/0,
        GIM_CheckComplexPattern, /*MI*/0, /*Op*/2, /*Renderer*/GIMT_Encode2(0), GIMT_Encode2(GICP_gi_global_offset),
        // (intrinsic_w_chain:{ *:[f32] } 1983:{ *:[iPTR] }, (GlobalOffset:{ *:[iPTR] } i64:{ *:[i64] }:$vaddr, i32:{ *:[i32] }:$offset), f32:{ *:[f32] }:$data)<<P:Predicate_int_amdgcn_global_atomic_fmin_num_noret>>  =>  (GLOBAL_ATOMIC_FMIN VReg_64:{ *:[i64] }:$vaddr, anonymous_15037:{ *:[f32] }:$data, ?:{ *:[i32] }:$offset)
        GIR_BuildMI, /*InsnID*/0, /*Opcode*/GIMT_Encode2(AMDGPU::GLOBAL_ATOMIC_FMIN),
        GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/0, // vaddr
        GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/3, // data
        GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/1, // offset
        GIR_AddImm8, /*InsnID*/0, /*Imm*/0,
        GIR_MergeMemOperands, /*InsnID*/0, /*NumInsns*/1, /*MergeInsnID's*/0,
        GIR_ConstrainSelectedInstOperands, /*InsnID*/0,
        GIR_EraseFromParent, /*InsnID*/0,
        // GIR_Coverage, 3322,
        GIR_Done,
      // Label 3343: @215489
      GIM_Try, /*On fail goto*//*Label 3344*/ GIMT_Encode4(215553), // Rule ID 3326 //
        GIM_CheckFeatures, GIMT_Encode2(GIFBS_isGFX12Only),
        GIM_CheckIntrinsicID, /*MI*/0, /*Op*/1, GIMT_Encode2(Intrinsic::amdgcn_global_atomic_fmax_num),
        GIM_CheckType, /*MI*/0, /*Op*/0, /*Type*/GILLT_s32,
        GIM_CheckType, /*MI*/0, /*Op*/3, /*Type*/GILLT_s32,
        GIM_CheckHasNoUse, /*MI*/0,
        GIM_CheckPointerToAny, /*MI*/0, /*Op*/2, /*SizeInBits*/0,
        GIM_CheckComplexPattern, /*MI*/0, /*Op*/2, /*Renderer*/GIMT_Encode2(0), GIMT_Encode2(GICP_gi_global_offset),
        // (intrinsic_w_chain:{ *:[f32] } 1981:{ *:[iPTR] }, (GlobalOffset:{ *:[iPTR] } i64:{ *:[i64] }:$vaddr, i32:{ *:[i32] }:$offset), f32:{ *:[f32] }:$data)<<P:Predicate_int_amdgcn_global_atomic_fmax_num_noret>>  =>  (GLOBAL_ATOMIC_FMAX VReg_64:{ *:[i64] }:$vaddr, anonymous_15037:{ *:[f32] }:$data, ?:{ *:[i32] }:$offset)
        GIR_BuildMI, /*InsnID*/0, /*Opcode*/GIMT_Encode2(AMDGPU::GLOBAL_ATOMIC_FMAX),
        GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/0, // vaddr
        GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/3, // data
        GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/1, // offset
        GIR_AddImm8, /*InsnID*/0, /*Imm*/0,
        GIR_MergeMemOperands, /*InsnID*/0, /*NumInsns*/1, /*MergeInsnID's*/0,
        GIR_ConstrainSelectedInstOperands, /*InsnID*/0,
        GIR_EraseFromParent, /*InsnID*/0,
        // GIR_Coverage, 3326,
        GIR_Done,
      // Label 3344: @215553
      GIM_Try, /*On fail goto*//*Label 3345*/ GIMT_Encode4(215617), // Rule ID 3374 //
        GIM_CheckFeatures, GIMT_Encode2(GIFBS_isGFX90APlus),
        GIM_CheckIntrinsicID, /*MI*/0, /*Op*/1, GIMT_Encode2(Intrinsic::amdgcn_global_atomic_fmin),
        GIM_CheckType, /*MI*/0, /*Op*/0, /*Type*/GILLT_s64,
        GIM_CheckType, /*MI*/0, /*Op*/3, /*Type*/GILLT_s64,
        GIM_CheckHasNoUse, /*MI*/0,
        GIM_CheckPointerToAny, /*MI*/0, /*Op*/2, /*SizeInBits*/0,
        GIM_CheckComplexPattern, /*MI*/0, /*Op*/2, /*Renderer*/GIMT_Encode2(0), GIMT_Encode2(GICP_gi_global_offset),
        // (intrinsic_w_chain:{ *:[f64] } 1982:{ *:[iPTR] }, (GlobalOffset:{ *:[iPTR] } i64:{ *:[i64] }:$vaddr, i32:{ *:[i32] }:$offset), f64:{ *:[f64] }:$data)<<P:Predicate_int_amdgcn_global_atomic_fmin_noret>>  =>  (GLOBAL_ATOMIC_MIN_F64 VReg_64:{ *:[i64] }:$vaddr, anonymous_15036:{ *:[f64] }:$data, ?:{ *:[i32] }:$offset)
        GIR_BuildMI, /*InsnID*/0, /*Opcode*/GIMT_Encode2(AMDGPU::GLOBAL_ATOMIC_MIN_F64),
        GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/0, // vaddr
        GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/3, // data
        GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/1, // offset
        GIR_AddImm8, /*InsnID*/0, /*Imm*/0,
        GIR_MergeMemOperands, /*InsnID*/0, /*NumInsns*/1, /*MergeInsnID's*/0,
        GIR_ConstrainSelectedInstOperands, /*InsnID*/0,
        GIR_EraseFromParent, /*InsnID*/0,
        // GIR_Coverage, 3374,
        GIR_Done,
      // Label 3345: @215617
      GIM_Try, /*On fail goto*//*Label 3346*/ GIMT_Encode4(215681), // Rule ID 3378 //
        GIM_CheckFeatures, GIMT_Encode2(GIFBS_isGFX90APlus),
        GIM_CheckIntrinsicID, /*MI*/0, /*Op*/1, GIMT_Encode2(Intrinsic::amdgcn_global_atomic_fmax),
        GIM_CheckType, /*MI*/0, /*Op*/0, /*Type*/GILLT_s64,
        GIM_CheckType, /*MI*/0, /*Op*/3, /*Type*/GILLT_s64,
        GIM_CheckHasNoUse, /*MI*/0,
        GIM_CheckPointerToAny, /*MI*/0, /*Op*/2, /*SizeInBits*/0,
        GIM_CheckComplexPattern, /*MI*/0, /*Op*/2, /*Renderer*/GIMT_Encode2(0), GIMT_Encode2(GICP_gi_global_offset),
        // (intrinsic_w_chain:{ *:[f64] } 1980:{ *:[iPTR] }, (GlobalOffset:{ *:[iPTR] } i64:{ *:[i64] }:$vaddr, i32:{ *:[i32] }:$offset), f64:{ *:[f64] }:$data)<<P:Predicate_int_amdgcn_global_atomic_fmax_noret>>  =>  (GLOBAL_ATOMIC_MAX_F64 VReg_64:{ *:[i64] }:$vaddr, anonymous_15036:{ *:[f64] }:$data, ?:{ *:[i32] }:$offset)
        GIR_BuildMI, /*InsnID*/0, /*Opcode*/GIMT_Encode2(AMDGPU::GLOBAL_ATOMIC_MAX_F64),
        GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/0, // vaddr
        GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/3, // data
        GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/1, // offset
        GIR_AddImm8, /*InsnID*/0, /*Imm*/0,
        GIR_MergeMemOperands, /*InsnID*/0, /*NumInsns*/1, /*MergeInsnID's*/0,
        GIR_ConstrainSelectedInstOperands, /*InsnID*/0,
        GIR_EraseFromParent, /*InsnID*/0,
        // GIR_Coverage, 3378,
        GIR_Done,
      // Label 3346: @215681
      GIM_Try, /*On fail goto*//*Label 3347*/ GIMT_Encode4(215745), // Rule ID 3400 //
        GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasAtomicGlobalPkAddBF16Inst),
        GIM_CheckIntrinsicID, /*MI*/0, /*Op*/1, GIMT_Encode2(Intrinsic::amdgcn_global_atomic_fadd_v2bf16),
        GIM_CheckType, /*MI*/0, /*Op*/0, /*Type*/GILLT_v2s16,
        GIM_CheckType, /*MI*/0, /*Op*/3, /*Type*/GILLT_v2s16,
        GIM_CheckHasNoUse, /*MI*/0,
        GIM_CheckPointerToAny, /*MI*/0, /*Op*/2, /*SizeInBits*/0,
        GIM_CheckComplexPattern, /*MI*/0, /*Op*/2, /*Renderer*/GIMT_Encode2(0), GIMT_Encode2(GICP_gi_global_offset),
        // (intrinsic_w_chain:{ *:[v2i16] } 1979:{ *:[iPTR] }, (GlobalOffset:{ *:[iPTR] } i64:{ *:[i64] }:$vaddr, i32:{ *:[i32] }:$offset), v2i16:{ *:[v2i16] }:$data)<<P:Predicate_int_amdgcn_global_atomic_fadd_v2bf16_noret>>  =>  (GLOBAL_ATOMIC_PK_ADD_BF16 VReg_64:{ *:[i64] }:$vaddr, anonymous_15037:{ *:[v2i16] }:$data, ?:{ *:[i32] }:$offset)
        GIR_BuildMI, /*InsnID*/0, /*Opcode*/GIMT_Encode2(AMDGPU::GLOBAL_ATOMIC_PK_ADD_BF16),
        GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/0, // vaddr
        GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/3, // data
        GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/1, // offset
        GIR_AddImm8, /*InsnID*/0, /*Imm*/0,
        GIR_MergeMemOperands, /*InsnID*/0, /*NumInsns*/1, /*MergeInsnID's*/0,
        GIR_ConstrainSelectedInstOperands, /*InsnID*/0,
        GIR_EraseFromParent, /*InsnID*/0,
        // GIR_Coverage, 3400,
        GIR_Done,
      // Label 3347: @215745
      GIM_Try, /*On fail goto*//*Label 3348*/ GIMT_Encode4(215823), // Rule ID 3254 //
        GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasFlatGlobalInsts_isGFX12Plus),
        GIM_CheckIntrinsicID, /*MI*/0, /*Op*/1, GIMT_Encode2(Intrinsic::amdgcn_atomic_cond_sub_u32),
        GIM_CheckType, /*MI*/0, /*Op*/0, /*Type*/GILLT_s32,
        GIM_CheckType, /*MI*/0, /*Op*/3, /*Type*/GILLT_s32,
        GIM_CheckMemoryAddressSpace, /*MI*/0, /*MMO*/0, /*NumAddrSpace*/3, /*AddrSpace*/1, /*AddrSpace*/4, /*AddrSpace*/6,
        GIM_CheckRegBankForClass, /*MI*/0, /*Op*/0, /*RC*/GIMT_Encode2(AMDGPU::AV_32RegClassID),
        GIM_CheckPointerToAny, /*MI*/0, /*Op*/2, /*SizeInBits*/0,
        GIM_CheckComplexPattern, /*MI*/0, /*Op*/2, /*Renderer*/GIMT_Encode2(0), GIMT_Encode2(GICP_gi_global_offset),
        // (intrinsic_w_chain:{ *:[i32] } 1879:{ *:[iPTR] }, (GlobalOffset:{ *:[iPTR] } i64:{ *:[i64] }:$vaddr, i32:{ *:[i32] }:$offset), i32:{ *:[i32] }:$data)<<P:Predicate_int_amdgcn_atomic_cond_sub_u32_global_addrspace>>  =>  (GLOBAL_ATOMIC_COND_SUB_U32_RTN:{ *:[i32] } VReg_64:{ *:[i64] }:$vaddr, anonymous_15037:{ *:[i32] }:$data, ?:{ *:[i32] }:$offset)
        GIR_BuildMI, /*InsnID*/0, /*Opcode*/GIMT_Encode2(AMDGPU::GLOBAL_ATOMIC_COND_SUB_U32_RTN),
        GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/0, // DstI[vdst]
        GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/0, // vaddr
        GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/3, // data
        GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/1, // offset
        GIR_AddImm8, /*InsnID*/0, /*Imm*/1,
        GIR_MergeMemOperands, /*InsnID*/0, /*NumInsns*/1, /*MergeInsnID's*/0,
        GIR_ConstrainSelectedInstOperands, /*InsnID*/0,
        GIR_EraseFromParent, /*InsnID*/0,
        // GIR_Coverage, 3254,
        GIR_Done,
      // Label 3348: @215823
      GIM_Try, /*On fail goto*//*Label 3349*/ GIMT_Encode4(215901), // Rule ID 3346 //
        GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasAtomicFaddRtnInsts),
        GIM_CheckIntrinsicID, /*MI*/0, /*Op*/1, GIMT_Encode2(Intrinsic::amdgcn_flat_atomic_fadd),
        GIM_CheckType, /*MI*/0, /*Op*/0, /*Type*/GILLT_s32,
        GIM_CheckType, /*MI*/0, /*Op*/3, /*Type*/GILLT_s32,
        GIM_CheckMemoryAddressSpace, /*MI*/0, /*MMO*/0, /*NumAddrSpace*/3, /*AddrSpace*/1, /*AddrSpace*/4, /*AddrSpace*/6,
        GIM_CheckRegBankForClass, /*MI*/0, /*Op*/0, /*RC*/GIMT_Encode2(AMDGPU::AV_32RegClassID),
        GIM_CheckPointerToAny, /*MI*/0, /*Op*/2, /*SizeInBits*/0,
        GIM_CheckComplexPattern, /*MI*/0, /*Op*/2, /*Renderer*/GIMT_Encode2(0), GIMT_Encode2(GICP_gi_global_offset),
        // (intrinsic_w_chain:{ *:[f32] } 1964:{ *:[iPTR] }, (GlobalOffset:{ *:[iPTR] } i64:{ *:[i64] }:$vaddr, i32:{ *:[i32] }:$offset), f32:{ *:[f32] }:$data)<<P:Predicate_int_amdgcn_flat_atomic_fadd_global_addrspace>>  =>  (GLOBAL_ATOMIC_ADD_F32_RTN:{ *:[f32] } VReg_64:{ *:[i64] }:$vaddr, anonymous_15037:{ *:[f32] }:$data, ?:{ *:[i32] }:$offset)
        GIR_BuildMI, /*InsnID*/0, /*Opcode*/GIMT_Encode2(AMDGPU::GLOBAL_ATOMIC_ADD_F32_RTN),
        GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/0, // DstI[vdst]
        GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/0, // vaddr
        GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/3, // data
        GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/1, // offset
        GIR_AddImm8, /*InsnID*/0, /*Imm*/1,
        GIR_MergeMemOperands, /*InsnID*/0, /*NumInsns*/1, /*MergeInsnID's*/0,
        GIR_ConstrainSelectedInstOperands, /*InsnID*/0,
        GIR_EraseFromParent, /*InsnID*/0,
        // GIR_Coverage, 3346,
        GIR_Done,
      // Label 3349: @215901
      GIM_Try, /*On fail goto*//*Label 3350*/ GIMT_Encode4(215979), // Rule ID 3348 //
        GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasAtomicFaddRtnInsts),
        GIM_CheckIntrinsicID, /*MI*/0, /*Op*/1, GIMT_Encode2(Intrinsic::amdgcn_global_atomic_fadd),
        GIM_CheckType, /*MI*/0, /*Op*/0, /*Type*/GILLT_s32,
        GIM_CheckType, /*MI*/0, /*Op*/3, /*Type*/GILLT_s32,
        GIM_CheckMemoryAddressSpace, /*MI*/0, /*MMO*/0, /*NumAddrSpace*/3, /*AddrSpace*/1, /*AddrSpace*/4, /*AddrSpace*/6,
        GIM_CheckRegBankForClass, /*MI*/0, /*Op*/0, /*RC*/GIMT_Encode2(AMDGPU::AV_32RegClassID),
        GIM_CheckPointerToAny, /*MI*/0, /*Op*/2, /*SizeInBits*/0,
        GIM_CheckComplexPattern, /*MI*/0, /*Op*/2, /*Renderer*/GIMT_Encode2(0), GIMT_Encode2(GICP_gi_global_offset),
        // (intrinsic_w_chain:{ *:[f32] } 1978:{ *:[iPTR] }, (GlobalOffset:{ *:[iPTR] } i64:{ *:[i64] }:$vaddr, i32:{ *:[i32] }:$offset), f32:{ *:[f32] }:$data)<<P:Predicate_int_amdgcn_global_atomic_fadd_global_addrspace>>  =>  (GLOBAL_ATOMIC_ADD_F32_RTN:{ *:[f32] } VReg_64:{ *:[i64] }:$vaddr, anonymous_15037:{ *:[f32] }:$data, ?:{ *:[i32] }:$offset)
        GIR_BuildMI, /*InsnID*/0, /*Opcode*/GIMT_Encode2(AMDGPU::GLOBAL_ATOMIC_ADD_F32_RTN),
        GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/0, // DstI[vdst]
        GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/0, // vaddr
        GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/3, // data
        GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/1, // offset
        GIR_AddImm8, /*InsnID*/0, /*Imm*/1,
        GIR_MergeMemOperands, /*InsnID*/0, /*NumInsns*/1, /*MergeInsnID's*/0,
        GIR_ConstrainSelectedInstOperands, /*InsnID*/0,
        GIR_EraseFromParent, /*InsnID*/0,
        // GIR_Coverage, 3348,
        GIR_Done,
      // Label 3350: @215979
      GIM_Try, /*On fail goto*//*Label 3351*/ GIMT_Encode4(216057), // Rule ID 3350 //
        GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasAtomicBufferGlobalPkAddF16Insts),
        GIM_CheckIntrinsicID, /*MI*/0, /*Op*/1, GIMT_Encode2(Intrinsic::amdgcn_flat_atomic_fadd),
        GIM_CheckType, /*MI*/0, /*Op*/0, /*Type*/GILLT_v2s16,
        GIM_CheckType, /*MI*/0, /*Op*/3, /*Type*/GILLT_v2s16,
        GIM_CheckMemoryAddressSpace, /*MI*/0, /*MMO*/0, /*NumAddrSpace*/3, /*AddrSpace*/1, /*AddrSpace*/4, /*AddrSpace*/6,
        GIM_CheckRegBankForClass, /*MI*/0, /*Op*/0, /*RC*/GIMT_Encode2(AMDGPU::AV_32RegClassID),
        GIM_CheckPointerToAny, /*MI*/0, /*Op*/2, /*SizeInBits*/0,
        GIM_CheckComplexPattern, /*MI*/0, /*Op*/2, /*Renderer*/GIMT_Encode2(0), GIMT_Encode2(GICP_gi_global_offset),
        // (intrinsic_w_chain:{ *:[v2f16] } 1964:{ *:[iPTR] }, (GlobalOffset:{ *:[iPTR] } i64:{ *:[i64] }:$vaddr, i32:{ *:[i32] }:$offset), v2f16:{ *:[v2f16] }:$data)<<P:Predicate_int_amdgcn_flat_atomic_fadd_global_addrspace>>  =>  (GLOBAL_ATOMIC_PK_ADD_F16_RTN:{ *:[v2f16] } VReg_64:{ *:[i64] }:$vaddr, anonymous_15037:{ *:[v2f16] }:$data, ?:{ *:[i32] }:$offset)
        GIR_BuildMI, /*InsnID*/0, /*Opcode*/GIMT_Encode2(AMDGPU::GLOBAL_ATOMIC_PK_ADD_F16_RTN),
        GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/0, // DstI[vdst]
        GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/0, // vaddr
        GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/3, // data
        GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/1, // offset
        GIR_AddImm8, /*InsnID*/0, /*Imm*/1,
        GIR_MergeMemOperands, /*InsnID*/0, /*NumInsns*/1, /*MergeInsnID's*/0,
        GIR_ConstrainSelectedInstOperands, /*InsnID*/0,
        GIR_EraseFromParent, /*InsnID*/0,
        // GIR_Coverage, 3350,
        GIR_Done,
      // Label 3351: @216057
      GIM_Try, /*On fail goto*//*Label 3352*/ GIMT_Encode4(216135), // Rule ID 3352 //
        GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasAtomicBufferGlobalPkAddF16Insts),
        GIM_CheckIntrinsicID, /*MI*/0, /*Op*/1, GIMT_Encode2(Intrinsic::amdgcn_global_atomic_fadd),
        GIM_CheckType, /*MI*/0, /*Op*/0, /*Type*/GILLT_v2s16,
        GIM_CheckType, /*MI*/0, /*Op*/3, /*Type*/GILLT_v2s16,
        GIM_CheckMemoryAddressSpace, /*MI*/0, /*MMO*/0, /*NumAddrSpace*/3, /*AddrSpace*/1, /*AddrSpace*/4, /*AddrSpace*/6,
        GIM_CheckRegBankForClass, /*MI*/0, /*Op*/0, /*RC*/GIMT_Encode2(AMDGPU::AV_32RegClassID),
        GIM_CheckPointerToAny, /*MI*/0, /*Op*/2, /*SizeInBits*/0,
        GIM_CheckComplexPattern, /*MI*/0, /*Op*/2, /*Renderer*/GIMT_Encode2(0), GIMT_Encode2(GICP_gi_global_offset),
        // (intrinsic_w_chain:{ *:[v2f16] } 1978:{ *:[iPTR] }, (GlobalOffset:{ *:[iPTR] } i64:{ *:[i64] }:$vaddr, i32:{ *:[i32] }:$offset), v2f16:{ *:[v2f16] }:$data)<<P:Predicate_int_amdgcn_global_atomic_fadd_global_addrspace>>  =>  (GLOBAL_ATOMIC_PK_ADD_F16_RTN:{ *:[v2f16] } VReg_64:{ *:[i64] }:$vaddr, anonymous_15037:{ *:[v2f16] }:$data, ?:{ *:[i32] }:$offset)
        GIR_BuildMI, /*InsnID*/0, /*Opcode*/GIMT_Encode2(AMDGPU::GLOBAL_ATOMIC_PK_ADD_F16_RTN),
        GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/0, // DstI[vdst]
        GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/0, // vaddr
        GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/3, // data
        GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/1, // offset
        GIR_AddImm8, /*InsnID*/0, /*Imm*/1,
        GIR_MergeMemOperands, /*InsnID*/0, /*NumInsns*/1, /*MergeInsnID's*/0,
        GIR_ConstrainSelectedInstOperands, /*InsnID*/0,
        GIR_EraseFromParent, /*InsnID*/0,
        // GIR_Coverage, 3352,
        GIR_Done,
      // Label 3352: @216135
      GIM_Try, /*On fail goto*//*Label 3353*/ GIMT_Encode4(216213), // Rule ID 3368 //
        GIM_CheckFeatures, GIMT_Encode2(GIFBS_isGFX90APlus),
        GIM_CheckIntrinsicID, /*MI*/0, /*Op*/1, GIMT_Encode2(Intrinsic::amdgcn_flat_atomic_fadd),
        GIM_CheckType, /*MI*/0, /*Op*/0, /*Type*/GILLT_s64,
        GIM_CheckType, /*MI*/0, /*Op*/3, /*Type*/GILLT_s64,
        GIM_CheckMemoryAddressSpace, /*MI*/0, /*MMO*/0, /*NumAddrSpace*/3, /*AddrSpace*/1, /*AddrSpace*/4, /*AddrSpace*/6,
        GIM_CheckRegBankForClass, /*MI*/0, /*Op*/0, /*RC*/GIMT_Encode2(AMDGPU::AV_64RegClassID),
        GIM_CheckPointerToAny, /*MI*/0, /*Op*/2, /*SizeInBits*/0,
        GIM_CheckComplexPattern, /*MI*/0, /*Op*/2, /*Renderer*/GIMT_Encode2(0), GIMT_Encode2(GICP_gi_global_offset),
        // (intrinsic_w_chain:{ *:[f64] } 1964:{ *:[iPTR] }, (GlobalOffset:{ *:[iPTR] } i64:{ *:[i64] }:$vaddr, i32:{ *:[i32] }:$offset), f64:{ *:[f64] }:$data)<<P:Predicate_int_amdgcn_flat_atomic_fadd_global_addrspace>>  =>  (GLOBAL_ATOMIC_ADD_F64_RTN:{ *:[f64] } VReg_64:{ *:[i64] }:$vaddr, anonymous_15036:{ *:[f64] }:$data, ?:{ *:[i32] }:$offset)
        GIR_BuildMI, /*InsnID*/0, /*Opcode*/GIMT_Encode2(AMDGPU::GLOBAL_ATOMIC_ADD_F64_RTN),
        GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/0, // DstI[vdst]
        GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/0, // vaddr
        GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/3, // data
        GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/1, // offset
        GIR_AddImm8, /*InsnID*/0, /*Imm*/1,
        GIR_MergeMemOperands, /*InsnID*/0, /*NumInsns*/1, /*MergeInsnID's*/0,
        GIR_ConstrainSelectedInstOperands, /*InsnID*/0,
        GIR_EraseFromParent, /*InsnID*/0,
        // GIR_Coverage, 3368,
        GIR_Done,
      // Label 3353: @216213
      GIM_Try, /*On fail goto*//*Label 3354*/ GIMT_Encode4(216291), // Rule ID 3372 //
        GIM_CheckFeatures, GIMT_Encode2(GIFBS_isGFX90APlus),
        GIM_CheckIntrinsicID, /*MI*/0, /*Op*/1, GIMT_Encode2(Intrinsic::amdgcn_global_atomic_fadd),
        GIM_CheckType, /*MI*/0, /*Op*/0, /*Type*/GILLT_s64,
        GIM_CheckType, /*MI*/0, /*Op*/3, /*Type*/GILLT_s64,
        GIM_CheckMemoryAddressSpace, /*MI*/0, /*MMO*/0, /*NumAddrSpace*/3, /*AddrSpace*/1, /*AddrSpace*/4, /*AddrSpace*/6,
        GIM_CheckRegBankForClass, /*MI*/0, /*Op*/0, /*RC*/GIMT_Encode2(AMDGPU::AV_64RegClassID),
        GIM_CheckPointerToAny, /*MI*/0, /*Op*/2, /*SizeInBits*/0,
        GIM_CheckComplexPattern, /*MI*/0, /*Op*/2, /*Renderer*/GIMT_Encode2(0), GIMT_Encode2(GICP_gi_global_offset),
        // (intrinsic_w_chain:{ *:[f64] } 1978:{ *:[iPTR] }, (GlobalOffset:{ *:[iPTR] } i64:{ *:[i64] }:$vaddr, i32:{ *:[i32] }:$offset), f64:{ *:[f64] }:$data)<<P:Predicate_int_amdgcn_global_atomic_fadd_global_addrspace>>  =>  (GLOBAL_ATOMIC_ADD_F64_RTN:{ *:[f64] } VReg_64:{ *:[i64] }:$vaddr, anonymous_15036:{ *:[f64] }:$data, ?:{ *:[i32] }:$offset)
        GIR_BuildMI, /*InsnID*/0, /*Opcode*/GIMT_Encode2(AMDGPU::GLOBAL_ATOMIC_ADD_F64_RTN),
        GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/0, // DstI[vdst]
        GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/0, // vaddr
        GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/3, // data
        GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/1, // offset
        GIR_AddImm8, /*InsnID*/0, /*Imm*/1,
        GIR_MergeMemOperands, /*InsnID*/0, /*NumInsns*/1, /*MergeInsnID's*/0,
        GIR_ConstrainSelectedInstOperands, /*InsnID*/0,
        GIR_EraseFromParent, /*InsnID*/0,
        // GIR_Coverage, 3372,
        GIR_Done,
      // Label 3354: @216291
      GIM_Try, /*On fail goto*//*Label 3355*/ GIMT_Encode4(216362), // Rule ID 3198 //
        GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasFlatGlobalInsts),
        GIM_CheckIntrinsicID, /*MI*/0, /*Op*/1, GIMT_Encode2(Intrinsic::amdgcn_global_atomic_csub),
        GIM_CheckType, /*MI*/0, /*Op*/0, /*Type*/GILLT_s32,
        GIM_CheckType, /*MI*/0, /*Op*/3, /*Type*/GILLT_s32,
        GIM_CheckRegBankForClass, /*MI*/0, /*Op*/0, /*RC*/GIMT_Encode2(AMDGPU::AV_32RegClassID),
        GIM_CheckPointerToAny, /*MI*/0, /*Op*/2, /*SizeInBits*/0,
        GIM_CheckComplexPattern, /*MI*/0, /*Op*/2, /*Renderer*/GIMT_Encode2(0), GIMT_Encode2(GICP_gi_global_offset),
        // (intrinsic_w_chain:{ *:[i32] } 1977:{ *:[iPTR] }, (GlobalOffset:{ *:[iPTR] } i64:{ *:[i64] }:$vaddr, i32:{ *:[i32] }:$offset), i32:{ *:[i32] }:$data)  =>  (GLOBAL_ATOMIC_CSUB_RTN:{ *:[i32] } VReg_64:{ *:[i64] }:$vaddr, anonymous_15037:{ *:[i32] }:$data, ?:{ *:[i32] }:$offset)
        GIR_BuildMI, /*InsnID*/0, /*Opcode*/GIMT_Encode2(AMDGPU::GLOBAL_ATOMIC_CSUB_RTN),
        GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/0, // DstI[vdst]
        GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/0, // vaddr
        GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/3, // data
        GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/1, // offset
        GIR_AddImm8, /*InsnID*/0, /*Imm*/1,
        GIR_MergeMemOperands, /*InsnID*/0, /*NumInsns*/1, /*MergeInsnID's*/0,
        GIR_ConstrainSelectedInstOperands, /*InsnID*/0,
        GIR_EraseFromParent, /*InsnID*/0,
        // GIR_Coverage, 3198,
        GIR_Done,
      // Label 3355: @216362
      GIM_Try, /*On fail goto*//*Label 3356*/ GIMT_Encode4(216433), // Rule ID 3258 //
        GIM_CheckFeatures, GIMT_Encode2(GIFBS_isGFX12Plus),
        GIM_CheckIntrinsicID, /*MI*/0, /*Op*/1, GIMT_Encode2(Intrinsic::amdgcn_global_atomic_ordered_add_b64),
        GIM_CheckType, /*MI*/0, /*Op*/0, /*Type*/GILLT_s64,
        GIM_CheckType, /*MI*/0, /*Op*/3, /*Type*/GILLT_s64,
        GIM_CheckRegBankForClass, /*MI*/0, /*Op*/0, /*RC*/GIMT_Encode2(AMDGPU::AV_64RegClassID),
        GIM_CheckPointerToAny, /*MI*/0, /*Op*/2, /*SizeInBits*/0,
        GIM_CheckComplexPattern, /*MI*/0, /*Op*/2, /*Renderer*/GIMT_Encode2(0), GIMT_Encode2(GICP_gi_global_offset),
        // (intrinsic_w_chain:{ *:[i64] } 1984:{ *:[iPTR] }, (GlobalOffset:{ *:[iPTR] } i64:{ *:[i64] }:$vaddr, i32:{ *:[i32] }:$offset), i64:{ *:[i64] }:$data)  =>  (GLOBAL_ATOMIC_ORDERED_ADD_B64_RTN:{ *:[i64] } VReg_64:{ *:[i64] }:$vaddr, anonymous_15036:{ *:[i64] }:$data, ?:{ *:[i32] }:$offset)
        GIR_BuildMI, /*InsnID*/0, /*Opcode*/GIMT_Encode2(AMDGPU::GLOBAL_ATOMIC_ORDERED_ADD_B64_RTN),
        GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/0, // DstI[vdst]
        GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/0, // vaddr
        GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/3, // data
        GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/1, // offset
        GIR_AddImm8, /*InsnID*/0, /*Imm*/1,
        GIR_MergeMemOperands, /*InsnID*/0, /*NumInsns*/1, /*MergeInsnID's*/0,
        GIR_ConstrainSelectedInstOperands, /*InsnID*/0,
        GIR_EraseFromParent, /*InsnID*/0,
        // GIR_Coverage, 3258,
        GIR_Done,
      // Label 3356: @216433
      GIM_Try, /*On fail goto*//*Label 3357*/ GIMT_Encode4(216504), // Rule ID 3288 //
        GIM_CheckFeatures, GIMT_Encode2(GIFBS_isGFX10GFX11),
        GIM_CheckIntrinsicID, /*MI*/0, /*Op*/1, GIMT_Encode2(Intrinsic::amdgcn_global_atomic_fmin),
        GIM_CheckType, /*MI*/0, /*Op*/0, /*Type*/GILLT_s32,
        GIM_CheckType, /*MI*/0, /*Op*/3, /*Type*/GILLT_s32,
        GIM_CheckRegBankForClass, /*MI*/0, /*Op*/0, /*RC*/GIMT_Encode2(AMDGPU::AV_32RegClassID),
        GIM_CheckPointerToAny, /*MI*/0, /*Op*/2, /*SizeInBits*/0,
        GIM_CheckComplexPattern, /*MI*/0, /*Op*/2, /*Renderer*/GIMT_Encode2(0), GIMT_Encode2(GICP_gi_global_offset),
        // (intrinsic_w_chain:{ *:[f32] } 1982:{ *:[iPTR] }, (GlobalOffset:{ *:[iPTR] } i64:{ *:[i64] }:$vaddr, i32:{ *:[i32] }:$offset), f32:{ *:[f32] }:$data)  =>  (GLOBAL_ATOMIC_FMIN_RTN:{ *:[f32] } VReg_64:{ *:[i64] }:$vaddr, anonymous_15037:{ *:[f32] }:$data, ?:{ *:[i32] }:$offset)
        GIR_BuildMI, /*InsnID*/0, /*Opcode*/GIMT_Encode2(AMDGPU::GLOBAL_ATOMIC_FMIN_RTN),
        GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/0, // DstI[vdst]
        GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/0, // vaddr
        GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/3, // data
        GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/1, // offset
        GIR_AddImm8, /*InsnID*/0, /*Imm*/1,
        GIR_MergeMemOperands, /*InsnID*/0, /*NumInsns*/1, /*MergeInsnID's*/0,
        GIR_ConstrainSelectedInstOperands, /*InsnID*/0,
        GIR_EraseFromParent, /*InsnID*/0,
        // GIR_Coverage, 3288,
        GIR_Done,
      // Label 3357: @216504
      GIM_Try, /*On fail goto*//*Label 3358*/ GIMT_Encode4(216575), // Rule ID 3292 //
        GIM_CheckFeatures, GIMT_Encode2(GIFBS_isGFX10GFX11),
        GIM_CheckIntrinsicID, /*MI*/0, /*Op*/1, GIMT_Encode2(Intrinsic::amdgcn_global_atomic_fmax),
        GIM_CheckType, /*MI*/0, /*Op*/0, /*Type*/GILLT_s32,
        GIM_CheckType, /*MI*/0, /*Op*/3, /*Type*/GILLT_s32,
        GIM_CheckRegBankForClass, /*MI*/0, /*Op*/0, /*RC*/GIMT_Encode2(AMDGPU::AV_32RegClassID),
        GIM_CheckPointerToAny, /*MI*/0, /*Op*/2, /*SizeInBits*/0,
        GIM_CheckComplexPattern, /*MI*/0, /*Op*/2, /*Renderer*/GIMT_Encode2(0), GIMT_Encode2(GICP_gi_global_offset),
        // (intrinsic_w_chain:{ *:[f32] } 1980:{ *:[iPTR] }, (GlobalOffset:{ *:[iPTR] } i64:{ *:[i64] }:$vaddr, i32:{ *:[i32] }:$offset), f32:{ *:[f32] }:$data)  =>  (GLOBAL_ATOMIC_FMAX_RTN:{ *:[f32] } VReg_64:{ *:[i64] }:$vaddr, anonymous_15037:{ *:[f32] }:$data, ?:{ *:[i32] }:$offset)
        GIR_BuildMI, /*InsnID*/0, /*Opcode*/GIMT_Encode2(AMDGPU::GLOBAL_ATOMIC_FMAX_RTN),
        GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/0, // DstI[vdst]
        GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/0, // vaddr
        GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/3, // data
        GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/1, // offset
        GIR_AddImm8, /*InsnID*/0, /*Imm*/1,
        GIR_MergeMemOperands, /*InsnID*/0, /*NumInsns*/1, /*MergeInsnID's*/0,
        GIR_ConstrainSelectedInstOperands, /*InsnID*/0,
        GIR_EraseFromParent, /*InsnID*/0,
        // GIR_Coverage, 3292,
        GIR_Done,
      // Label 3358: @216575
      GIM_Try, /*On fail goto*//*Label 3359*/ GIMT_Encode4(216646), // Rule ID 3308 //
        GIM_CheckFeatures, GIMT_Encode2(GIFBS_isGFX10Only),
        GIM_CheckIntrinsicID, /*MI*/0, /*Op*/1, GIMT_Encode2(Intrinsic::amdgcn_global_atomic_fmin),
        GIM_CheckType, /*MI*/0, /*Op*/0, /*Type*/GILLT_s64,
        GIM_CheckType, /*MI*/0, /*Op*/3, /*Type*/GILLT_s64,
        GIM_CheckRegBankForClass, /*MI*/0, /*Op*/0, /*RC*/GIMT_Encode2(AMDGPU::AV_64RegClassID),
        GIM_CheckPointerToAny, /*MI*/0, /*Op*/2, /*SizeInBits*/0,
        GIM_CheckComplexPattern, /*MI*/0, /*Op*/2, /*Renderer*/GIMT_Encode2(0), GIMT_Encode2(GICP_gi_global_offset),
        // (intrinsic_w_chain:{ *:[f64] } 1982:{ *:[iPTR] }, (GlobalOffset:{ *:[iPTR] } i64:{ *:[i64] }:$vaddr, i32:{ *:[i32] }:$offset), f64:{ *:[f64] }:$data)  =>  (GLOBAL_ATOMIC_FMIN_X2_RTN:{ *:[f64] } VReg_64:{ *:[i64] }:$vaddr, anonymous_15036:{ *:[f64] }:$data, ?:{ *:[i32] }:$offset)
        GIR_BuildMI, /*InsnID*/0, /*Opcode*/GIMT_Encode2(AMDGPU::GLOBAL_ATOMIC_FMIN_X2_RTN),
        GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/0, // DstI[vdst]
        GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/0, // vaddr
        GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/3, // data
        GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/1, // offset
        GIR_AddImm8, /*InsnID*/0, /*Imm*/1,
        GIR_MergeMemOperands, /*InsnID*/0, /*NumInsns*/1, /*MergeInsnID's*/0,
        GIR_ConstrainSelectedInstOperands, /*InsnID*/0,
        GIR_EraseFromParent, /*InsnID*/0,
        // GIR_Coverage, 3308,
        GIR_Done,
      // Label 3359: @216646
      GIM_Try, /*On fail goto*//*Label 3360*/ GIMT_Encode4(216717), // Rule ID 3312 //
        GIM_CheckFeatures, GIMT_Encode2(GIFBS_isGFX10Only),
        GIM_CheckIntrinsicID, /*MI*/0, /*Op*/1, GIMT_Encode2(Intrinsic::amdgcn_global_atomic_fmax),
        GIM_CheckType, /*MI*/0, /*Op*/0, /*Type*/GILLT_s64,
        GIM_CheckType, /*MI*/0, /*Op*/3, /*Type*/GILLT_s64,
        GIM_CheckRegBankForClass, /*MI*/0, /*Op*/0, /*RC*/GIMT_Encode2(AMDGPU::AV_64RegClassID),
        GIM_CheckPointerToAny, /*MI*/0, /*Op*/2, /*SizeInBits*/0,
        GIM_CheckComplexPattern, /*MI*/0, /*Op*/2, /*Renderer*/GIMT_Encode2(0), GIMT_Encode2(GICP_gi_global_offset),
        // (intrinsic_w_chain:{ *:[f64] } 1980:{ *:[iPTR] }, (GlobalOffset:{ *:[iPTR] } i64:{ *:[i64] }:$vaddr, i32:{ *:[i32] }:$offset), f64:{ *:[f64] }:$data)  =>  (GLOBAL_ATOMIC_FMAX_X2_RTN:{ *:[f64] } VReg_64:{ *:[i64] }:$vaddr, anonymous_15036:{ *:[f64] }:$data, ?:{ *:[i32] }:$offset)
        GIR_BuildMI, /*InsnID*/0, /*Opcode*/GIMT_Encode2(AMDGPU::GLOBAL_ATOMIC_FMAX_X2_RTN),
        GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/0, // DstI[vdst]
        GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/0, // vaddr
        GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/3, // data
        GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/1, // offset
        GIR_AddImm8, /*InsnID*/0, /*Imm*/1,
        GIR_MergeMemOperands, /*InsnID*/0, /*NumInsns*/1, /*MergeInsnID's*/0,
        GIR_ConstrainSelectedInstOperands, /*InsnID*/0,
        GIR_EraseFromParent, /*InsnID*/0,
        // GIR_Coverage, 3312,
        GIR_Done,
      // Label 3360: @216717
      GIM_Try, /*On fail goto*//*Label 3361*/ GIMT_Encode4(216788), // Rule ID 3324 //
        GIM_CheckFeatures, GIMT_Encode2(GIFBS_isGFX12Only),
        GIM_CheckIntrinsicID, /*MI*/0, /*Op*/1, GIMT_Encode2(Intrinsic::amdgcn_global_atomic_fmin_num),
        GIM_CheckType, /*MI*/0, /*Op*/0, /*Type*/GILLT_s32,
        GIM_CheckType, /*MI*/0, /*Op*/3, /*Type*/GILLT_s32,
        GIM_CheckRegBankForClass, /*MI*/0, /*Op*/0, /*RC*/GIMT_Encode2(AMDGPU::AV_32RegClassID),
        GIM_CheckPointerToAny, /*MI*/0, /*Op*/2, /*SizeInBits*/0,
        GIM_CheckComplexPattern, /*MI*/0, /*Op*/2, /*Renderer*/GIMT_Encode2(0), GIMT_Encode2(GICP_gi_global_offset),
        // (intrinsic_w_chain:{ *:[f32] } 1983:{ *:[iPTR] }, (GlobalOffset:{ *:[iPTR] } i64:{ *:[i64] }:$vaddr, i32:{ *:[i32] }:$offset), f32:{ *:[f32] }:$data)  =>  (GLOBAL_ATOMIC_FMIN_RTN:{ *:[f32] } VReg_64:{ *:[i64] }:$vaddr, anonymous_15037:{ *:[f32] }:$data, ?:{ *:[i32] }:$offset)
        GIR_BuildMI, /*InsnID*/0, /*Opcode*/GIMT_Encode2(AMDGPU::GLOBAL_ATOMIC_FMIN_RTN),
        GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/0, // DstI[vdst]
        GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/0, // vaddr
        GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/3, // data
        GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/1, // offset
        GIR_AddImm8, /*InsnID*/0, /*Imm*/1,
        GIR_MergeMemOperands, /*InsnID*/0, /*NumInsns*/1, /*MergeInsnID's*/0,
        GIR_ConstrainSelectedInstOperands, /*InsnID*/0,
        GIR_EraseFromParent, /*InsnID*/0,
        // GIR_Coverage, 3324,
        GIR_Done,
      // Label 3361: @216788
      GIM_Try, /*On fail goto*//*Label 3362*/ GIMT_Encode4(216859), // Rule ID 3328 //
        GIM_CheckFeatures, GIMT_Encode2(GIFBS_isGFX12Only),
        GIM_CheckIntrinsicID, /*MI*/0, /*Op*/1, GIMT_Encode2(Intrinsic::amdgcn_global_atomic_fmax_num),
        GIM_CheckType, /*MI*/0, /*Op*/0, /*Type*/GILLT_s32,
        GIM_CheckType, /*MI*/0, /*Op*/3, /*Type*/GILLT_s32,
        GIM_CheckRegBankForClass, /*MI*/0, /*Op*/0, /*RC*/GIMT_Encode2(AMDGPU::AV_32RegClassID),
        GIM_CheckPointerToAny, /*MI*/0, /*Op*/2, /*SizeInBits*/0,
        GIM_CheckComplexPattern, /*MI*/0, /*Op*/2, /*Renderer*/GIMT_Encode2(0), GIMT_Encode2(GICP_gi_global_offset),
        // (intrinsic_w_chain:{ *:[f32] } 1981:{ *:[iPTR] }, (GlobalOffset:{ *:[iPTR] } i64:{ *:[i64] }:$vaddr, i32:{ *:[i32] }:$offset), f32:{ *:[f32] }:$data)  =>  (GLOBAL_ATOMIC_FMAX_RTN:{ *:[f32] } VReg_64:{ *:[i64] }:$vaddr, anonymous_15037:{ *:[f32] }:$data, ?:{ *:[i32] }:$offset)
        GIR_BuildMI, /*InsnID*/0, /*Opcode*/GIMT_Encode2(AMDGPU::GLOBAL_ATOMIC_FMAX_RTN),
        GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/0, // DstI[vdst]
        GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/0, // vaddr
        GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/3, // data
        GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/1, // offset
        GIR_AddImm8, /*InsnID*/0, /*Imm*/1,
        GIR_MergeMemOperands, /*InsnID*/0, /*NumInsns*/1, /*MergeInsnID's*/0,
        GIR_ConstrainSelectedInstOperands, /*InsnID*/0,
        GIR_EraseFromParent, /*InsnID*/0,
        // GIR_Coverage, 3328,
        GIR_Done,
      // Label 3362: @216859
      GIM_Try, /*On fail goto*//*Label 3363*/ GIMT_Encode4(216930), // Rule ID 3376 //
        GIM_CheckFeatures, GIMT_Encode2(GIFBS_isGFX90APlus),
        GIM_CheckIntrinsicID, /*MI*/0, /*Op*/1, GIMT_Encode2(Intrinsic::amdgcn_global_atomic_fmin),
        GIM_CheckType, /*MI*/0, /*Op*/0, /*Type*/GILLT_s64,
        GIM_CheckType, /*MI*/0, /*Op*/3, /*Type*/GILLT_s64,
        GIM_CheckRegBankForClass, /*MI*/0, /*Op*/0, /*RC*/GIMT_Encode2(AMDGPU::AV_64RegClassID),
        GIM_CheckPointerToAny, /*MI*/0, /*Op*/2, /*SizeInBits*/0,
        GIM_CheckComplexPattern, /*MI*/0, /*Op*/2, /*Renderer*/GIMT_Encode2(0), GIMT_Encode2(GICP_gi_global_offset),
        // (intrinsic_w_chain:{ *:[f64] } 1982:{ *:[iPTR] }, (GlobalOffset:{ *:[iPTR] } i64:{ *:[i64] }:$vaddr, i32:{ *:[i32] }:$offset), f64:{ *:[f64] }:$data)  =>  (GLOBAL_ATOMIC_MIN_F64_RTN:{ *:[f64] } VReg_64:{ *:[i64] }:$vaddr, anonymous_15036:{ *:[f64] }:$data, ?:{ *:[i32] }:$offset)
        GIR_BuildMI, /*InsnID*/0, /*Opcode*/GIMT_Encode2(AMDGPU::GLOBAL_ATOMIC_MIN_F64_RTN),
        GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/0, // DstI[vdst]
        GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/0, // vaddr
        GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/3, // data
        GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/1, // offset
        GIR_AddImm8, /*InsnID*/0, /*Imm*/1,
        GIR_MergeMemOperands, /*InsnID*/0, /*NumInsns*/1, /*MergeInsnID's*/0,
        GIR_ConstrainSelectedInstOperands, /*InsnID*/0,
        GIR_EraseFromParent, /*InsnID*/0,
        // GIR_Coverage, 3376,
        GIR_Done,
      // Label 3363: @216930
      GIM_Try, /*On fail goto*//*Label 3364*/ GIMT_Encode4(217001), // Rule ID 3380 //
        GIM_CheckFeatures, GIMT_Encode2(GIFBS_isGFX90APlus),
        GIM_CheckIntrinsicID, /*MI*/0, /*Op*/1, GIMT_Encode2(Intrinsic::amdgcn_global_atomic_fmax),
        GIM_CheckType, /*MI*/0, /*Op*/0, /*Type*/GILLT_s64,
        GIM_CheckType, /*MI*/0, /*Op*/3, /*Type*/GILLT_s64,
        GIM_CheckRegBankForClass, /*MI*/0, /*Op*/0, /*RC*/GIMT_Encode2(AMDGPU::AV_64RegClassID),
        GIM_CheckPointerToAny, /*MI*/0, /*Op*/2, /*SizeInBits*/0,
        GIM_CheckComplexPattern, /*MI*/0, /*Op*/2, /*Renderer*/GIMT_Encode2(0), GIMT_Encode2(GICP_gi_global_offset),
        // (intrinsic_w_chain:{ *:[f64] } 1980:{ *:[iPTR] }, (GlobalOffset:{ *:[iPTR] } i64:{ *:[i64] }:$vaddr, i32:{ *:[i32] }:$offset), f64:{ *:[f64] }:$data)  =>  (GLOBAL_ATOMIC_MAX_F64_RTN:{ *:[f64] } VReg_64:{ *:[i64] }:$vaddr, anonymous_15036:{ *:[f64] }:$data, ?:{ *:[i32] }:$offset)
        GIR_BuildMI, /*InsnID*/0, /*Opcode*/GIMT_Encode2(AMDGPU::GLOBAL_ATOMIC_MAX_F64_RTN),
        GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/0, // DstI[vdst]
        GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/0, // vaddr
        GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/3, // data
        GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/1, // offset
        GIR_AddImm8, /*InsnID*/0, /*Imm*/1,
        GIR_MergeMemOperands, /*InsnID*/0, /*NumInsns*/1, /*MergeInsnID's*/0,
        GIR_ConstrainSelectedInstOperands, /*InsnID*/0,
        GIR_EraseFromParent, /*InsnID*/0,
        // GIR_Coverage, 3380,
        GIR_Done,
      // Label 3364: @217001
      GIM_Try, /*On fail goto*//*Label 3365*/ GIMT_Encode4(217072), // Rule ID 3402 //
        GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasAtomicGlobalPkAddBF16Inst),
        GIM_CheckIntrinsicID, /*MI*/0, /*Op*/1, GIMT_Encode2(Intrinsic::amdgcn_global_atomic_fadd_v2bf16),
        GIM_CheckType, /*MI*/0, /*Op*/0, /*Type*/GILLT_v2s16,
        GIM_CheckType, /*MI*/0, /*Op*/3, /*Type*/GILLT_v2s16,
        GIM_CheckRegBankForClass, /*MI*/0, /*Op*/0, /*RC*/GIMT_Encode2(AMDGPU::AV_32RegClassID),
        GIM_CheckPointerToAny, /*MI*/0, /*Op*/2, /*SizeInBits*/0,
        GIM_CheckComplexPattern, /*MI*/0, /*Op*/2, /*Renderer*/GIMT_Encode2(0), GIMT_Encode2(GICP_gi_global_offset),
        // (intrinsic_w_chain:{ *:[v2i16] } 1979:{ *:[iPTR] }, (GlobalOffset:{ *:[iPTR] } i64:{ *:[i64] }:$vaddr, i32:{ *:[i32] }:$offset), v2i16:{ *:[v2i16] }:$data)  =>  (GLOBAL_ATOMIC_PK_ADD_BF16_RTN:{ *:[v2i16] } VReg_64:{ *:[i64] }:$vaddr, anonymous_15037:{ *:[v2i16] }:$data, ?:{ *:[i32] }:$offset)
        GIR_BuildMI, /*InsnID*/0, /*Opcode*/GIMT_Encode2(AMDGPU::GLOBAL_ATOMIC_PK_ADD_BF16_RTN),
        GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/0, // DstI[vdst]
        GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/0, // vaddr
        GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/3, // data
        GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/1, // offset
        GIR_AddImm8, /*InsnID*/0, /*Imm*/1,
        GIR_MergeMemOperands, /*InsnID*/0, /*NumInsns*/1, /*MergeInsnID's*/0,
        GIR_ConstrainSelectedInstOperands, /*InsnID*/0,
        GIR_EraseFromParent, /*InsnID*/0,
        // GIR_Coverage, 3402,
        GIR_Done,
      // Label 3365: @217072
      GIM_Try, /*On fail goto*//*Label 3366*/ GIMT_Encode4(217125), // Rule ID 7088 //
        GIM_CheckIntrinsicID, /*MI*/0, /*Op*/1, GIMT_Encode2(Intrinsic::amdgcn_ds_add_gs_reg_rtn),
        GIM_CheckType, /*MI*/0, /*Op*/0, /*Type*/GILLT_s64,
        GIM_CheckType, /*MI*/0, /*Op*/2, /*Type*/GILLT_s32,
        GIM_CheckRegBankForClass, /*MI*/0, /*Op*/0, /*RC*/GIMT_Encode2(AMDGPU::AV_64RegClassID),
        // MIs[0] offset32
        GIM_CheckIsImm, /*MI*/0, /*Op*/3,
        // (intrinsic_w_chain:{ *:[i64] } 1931:{ *:[iPTR] }, i32:{ *:[i32] }:$src, (timm:{ *:[i32] }):$offset32)  =>  (DS_ADD_GS_REG_RTN:{ *:[i64] } VGPR_32:{ *:[i32] }:$src, (as_i32timm:{ *:[i32] } ?:{ *:[i32] }:$offset32))
        GIR_BuildMI, /*InsnID*/0, /*Opcode*/GIMT_Encode2(AMDGPU::DS_ADD_GS_REG_RTN),
        GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/0, // DstI[vdst]
        GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/2, // src
        GIR_CustomOperandRenderer, /*InsnID*/0, /*OldInsnID*/0, /*OpIdx*/3, /*OperandRenderer*/GIMT_Encode2(GICR_renderTruncTImm), // offset32
        GIR_MergeMemOperands, /*InsnID*/0, /*NumInsns*/1, /*MergeInsnID's*/0,
        GIR_ConstrainSelectedInstOperands, /*InsnID*/0,
        GIR_EraseFromParent, /*InsnID*/0,
        // GIR_Coverage, 7088,
        GIR_Done,
      // Label 3366: @217125
      GIM_Try, /*On fail goto*//*Label 3367*/ GIMT_Encode4(217224), // Rule ID 7089 //
        GIM_CheckIntrinsicID, /*MI*/0, /*Op*/1, GIMT_Encode2(Intrinsic::amdgcn_ds_add_gs_reg_rtn),
        GIM_CheckType, /*MI*/0, /*Op*/0, /*Type*/GILLT_s32,
        GIM_CheckType, /*MI*/0, /*Op*/2, /*Type*/GILLT_s32,
        GIM_CheckRegBankForClass, /*MI*/0, /*Op*/0, /*RC*/GIMT_Encode2(AMDGPU::VReg_64RegClassID),
        // MIs[0] offset32
        GIM_CheckIsImm, /*MI*/0, /*Op*/3,
        // (intrinsic_w_chain:{ *:[i32] } 1931:{ *:[iPTR] }, i32:{ *:[i32] }:$src, (timm:{ *:[i32] }):$offset32)  =>  (EXTRACT_SUBREG:{ *:[i32] } (COPY_TO_REGCLASS:{ *:[i64] } (DS_ADD_GS_REG_RTN:{ *:[i64] } VGPR_32:{ *:[i32] }:$src, (as_i32timm:{ *:[i32] } ?:{ *:[i32] }:$offset32)), VReg_64:{ *:[i32] }), sub0:{ *:[i32] })
        GIR_MakeTempReg, /*TempRegID*/0, /*TypeID*/GILLT_s64,
        GIR_MakeTempReg, /*TempRegID*/1, /*TypeID*/GILLT_s64,
        GIR_BuildMI, /*InsnID*/2, /*Opcode*/GIMT_Encode2(AMDGPU::DS_ADD_GS_REG_RTN),
        GIR_AddTempRegister, /*InsnID*/2, /*TempRegID*/1, /*TempRegFlags*/GIMT_Encode2(RegState::Define),
        GIR_Copy, /*NewInsnID*/2, /*OldInsnID*/0, /*OpIdx*/2, // src
        GIR_CustomOperandRenderer, /*InsnID*/2, /*OldInsnID*/0, /*OpIdx*/3, /*OperandRenderer*/GIMT_Encode2(GICR_renderTruncTImm), // offset32
        GIR_MergeMemOperands, /*InsnID*/2, /*NumInsns*/1, /*MergeInsnID's*/0,
        GIR_ConstrainSelectedInstOperands, /*InsnID*/2,
        GIR_BuildMI, /*InsnID*/1, /*Opcode*/GIMT_Encode2(TargetOpcode::COPY),
        GIR_AddTempRegister, /*InsnID*/1, /*TempRegID*/0, /*TempRegFlags*/GIMT_Encode2(RegState::Define),
        GIR_AddSimpleTempRegister, /*InsnID*/1, /*TempRegID*/1,
        GIR_ConstrainSelectedInstOperands, /*InsnID*/1,
        GIR_BuildMI, /*InsnID*/0, /*Opcode*/GIMT_Encode2(TargetOpcode::COPY),
        GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/0, // DstI[dst]
        GIR_AddTempSubRegister, /*InsnID*/0, /*TempRegID*/0, /*TempRegFlags*/GIMT_Encode2(0), GIMT_Encode2(AMDGPU::sub0),
        GIR_ConstrainOperandRC, /*InsnID*/0, /*Op*/0, GIMT_Encode2(AMDGPU::VGPR_32RegClassID),
        GIR_ConstrainOperandRC, /*InsnID*/0, /*Op*/1, GIMT_Encode2(AMDGPU::VReg_64RegClassID),
        GIR_EraseFromParent, /*InsnID*/0,
        // GIR_Coverage, 7089,
        GIR_Done,
      // Label 3367: @217224
      GIM_Try, /*On fail goto*//*Label 3368*/ GIMT_Encode4(217277), // Rule ID 7090 //
        GIM_CheckIntrinsicID, /*MI*/0, /*Op*/1, GIMT_Encode2(Intrinsic::amdgcn_ds_sub_gs_reg_rtn),
        GIM_CheckType, /*MI*/0, /*Op*/0, /*Type*/GILLT_s64,
        GIM_CheckType, /*MI*/0, /*Op*/2, /*Type*/GILLT_s32,
        GIM_CheckRegBankForClass, /*MI*/0, /*Op*/0, /*RC*/GIMT_Encode2(AMDGPU::AV_64RegClassID),
        // MIs[0] offset32
        GIM_CheckIsImm, /*MI*/0, /*Op*/3,
        // (intrinsic_w_chain:{ *:[i64] } 1949:{ *:[iPTR] }, i32:{ *:[i32] }:$src, (timm:{ *:[i32] }):$offset32)  =>  (DS_SUB_GS_REG_RTN:{ *:[i64] } VGPR_32:{ *:[i32] }:$src, (as_i32timm:{ *:[i32] } ?:{ *:[i32] }:$offset32))
        GIR_BuildMI, /*InsnID*/0, /*Opcode*/GIMT_Encode2(AMDGPU::DS_SUB_GS_REG_RTN),
        GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/0, // DstI[vdst]
        GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/2, // src
        GIR_CustomOperandRenderer, /*InsnID*/0, /*OldInsnID*/0, /*OpIdx*/3, /*OperandRenderer*/GIMT_Encode2(GICR_renderTruncTImm), // offset32
        GIR_MergeMemOperands, /*InsnID*/0, /*NumInsns*/1, /*MergeInsnID's*/0,
        GIR_ConstrainSelectedInstOperands, /*InsnID*/0,
        GIR_EraseFromParent, /*InsnID*/0,
        // GIR_Coverage, 7090,
        GIR_Done,
      // Label 3368: @217277
      GIM_Try, /*On fail goto*//*Label 3369*/ GIMT_Encode4(217376), // Rule ID 7091 //
        GIM_CheckIntrinsicID, /*MI*/0, /*Op*/1, GIMT_Encode2(Intrinsic::amdgcn_ds_sub_gs_reg_rtn),
        GIM_CheckType, /*MI*/0, /*Op*/0, /*Type*/GILLT_s32,
        GIM_CheckType, /*MI*/0, /*Op*/2, /*Type*/GILLT_s32,
        GIM_CheckRegBankForClass, /*MI*/0, /*Op*/0, /*RC*/GIMT_Encode2(AMDGPU::VReg_64RegClassID),
        // MIs[0] offset32
        GIM_CheckIsImm, /*MI*/0, /*Op*/3,
        // (intrinsic_w_chain:{ *:[i32] } 1949:{ *:[iPTR] }, i32:{ *:[i32] }:$src, (timm:{ *:[i32] }):$offset32)  =>  (EXTRACT_SUBREG:{ *:[i32] } (COPY_TO_REGCLASS:{ *:[i64] } (DS_SUB_GS_REG_RTN:{ *:[i64] } VGPR_32:{ *:[i32] }:$src, (as_i32timm:{ *:[i32] } ?:{ *:[i32] }:$offset32)), VReg_64:{ *:[i32] }), sub0:{ *:[i32] })
        GIR_MakeTempReg, /*TempRegID*/0, /*TypeID*/GILLT_s64,
        GIR_MakeTempReg, /*TempRegID*/1, /*TypeID*/GILLT_s64,
        GIR_BuildMI, /*InsnID*/2, /*Opcode*/GIMT_Encode2(AMDGPU::DS_SUB_GS_REG_RTN),
        GIR_AddTempRegister, /*InsnID*/2, /*TempRegID*/1, /*TempRegFlags*/GIMT_Encode2(RegState::Define),
        GIR_Copy, /*NewInsnID*/2, /*OldInsnID*/0, /*OpIdx*/2, // src
        GIR_CustomOperandRenderer, /*InsnID*/2, /*OldInsnID*/0, /*OpIdx*/3, /*OperandRenderer*/GIMT_Encode2(GICR_renderTruncTImm), // offset32
        GIR_MergeMemOperands, /*InsnID*/2, /*NumInsns*/1, /*MergeInsnID's*/0,
        GIR_ConstrainSelectedInstOperands, /*InsnID*/2,
        GIR_BuildMI, /*InsnID*/1, /*Opcode*/GIMT_Encode2(TargetOpcode::COPY),
        GIR_AddTempRegister, /*InsnID*/1, /*TempRegID*/0, /*TempRegFlags*/GIMT_Encode2(RegState::Define),
        GIR_AddSimpleTempRegister, /*InsnID*/1, /*TempRegID*/1,
        GIR_ConstrainSelectedInstOperands, /*InsnID*/1,
        GIR_BuildMI, /*InsnID*/0, /*Opcode*/GIMT_Encode2(TargetOpcode::COPY),
        GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/0, // DstI[dst]
        GIR_AddTempSubRegister, /*InsnID*/0, /*TempRegID*/0, /*TempRegFlags*/GIMT_Encode2(0), GIMT_Encode2(AMDGPU::sub0),
        GIR_ConstrainOperandRC, /*InsnID*/0, /*Op*/0, GIMT_Encode2(AMDGPU::VGPR_32RegClassID),
        GIR_ConstrainOperandRC, /*InsnID*/0, /*Op*/1, GIMT_Encode2(AMDGPU::VReg_64RegClassID),
        GIR_EraseFromParent, /*InsnID*/0,
        // GIR_Coverage, 7091,
        GIR_Done,
      // Label 3369: @217376
      GIM_Try, /*On fail goto*//*Label 3370*/ GIMT_Encode4(217430), // Rule ID 7086 //
        GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasAtomicDsPkAdd16Insts),
        GIM_CheckIntrinsicID, /*MI*/0, /*Op*/1, GIMT_Encode2(Intrinsic::amdgcn_ds_fadd_v2bf16),
        GIM_CheckType, /*MI*/0, /*Op*/0, /*Type*/GILLT_v2s16,
        GIM_CheckType, /*MI*/0, /*Op*/3, /*Type*/GILLT_v2s16,
        GIM_CheckHasNoUse, /*MI*/0,
        // MIs[0] ptr
        GIM_CheckPointerToAny, /*MI*/0, /*Op*/2, /*SizeInBits*/32,
        // (intrinsic_w_chain:{ *:[v2i16] } 1937:{ *:[iPTR] }, i32:{ *:[i32] }:$ptr, v2i16:{ *:[v2i16] }:$src)<<P:Predicate_int_amdgcn_ds_fadd_v2bf16_noret>>  =>  (DS_PK_ADD_BF16 VGPR_32:{ *:[i32] }:$ptr, VGPR_32:{ *:[v2i16] }:$src, 0:{ *:[i32] }, 0:{ *:[i1] })
        GIR_BuildMI, /*InsnID*/0, /*Opcode*/GIMT_Encode2(AMDGPU::DS_PK_ADD_BF16),
        GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/2, // ptr
        GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/3, // src
        GIR_AddImm8, /*InsnID*/0, /*Imm*/0,
        GIR_AddImm8, /*InsnID*/0, /*Imm*/0,
        GIR_MergeMemOperands, /*InsnID*/0, /*NumInsns*/1, /*MergeInsnID's*/0,
        GIR_ConstrainSelectedInstOperands, /*InsnID*/0,
        GIR_EraseFromParent, /*InsnID*/0,
        // GIR_Coverage, 7086,
        GIR_Done,
      // Label 3370: @217430
      GIM_Try, /*On fail goto*//*Label 3371*/ GIMT_Encode4(217491), // Rule ID 7085 //
        GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasAtomicDsPkAdd16Insts),
        GIM_CheckIntrinsicID, /*MI*/0, /*Op*/1, GIMT_Encode2(Intrinsic::amdgcn_ds_fadd_v2bf16),
        GIM_CheckType, /*MI*/0, /*Op*/0, /*Type*/GILLT_v2s16,
        GIM_CheckType, /*MI*/0, /*Op*/3, /*Type*/GILLT_v2s16,
        GIM_CheckRegBankForClass, /*MI*/0, /*Op*/0, /*RC*/GIMT_Encode2(AMDGPU::AV_32RegClassID),
        // MIs[0] ptr
        GIM_CheckPointerToAny, /*MI*/0, /*Op*/2, /*SizeInBits*/32,
        // (intrinsic_w_chain:{ *:[v2i16] } 1937:{ *:[iPTR] }, i32:{ *:[i32] }:$ptr, v2i16:{ *:[v2i16] }:$src)  =>  (DS_PK_ADD_RTN_BF16:{ *:[v2i16] } VGPR_32:{ *:[i32] }:$ptr, VGPR_32:{ *:[v2i16] }:$src, 0:{ *:[i32] }, 0:{ *:[i1] })
        GIR_BuildMI, /*InsnID*/0, /*Opcode*/GIMT_Encode2(AMDGPU::DS_PK_ADD_RTN_BF16),
        GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/0, // DstI[vdst]
        GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/2, // ptr
        GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/3, // src
        GIR_AddImm8, /*InsnID*/0, /*Imm*/0,
        GIR_AddImm8, /*InsnID*/0, /*Imm*/0,
        GIR_MergeMemOperands, /*InsnID*/0, /*NumInsns*/1, /*MergeInsnID's*/0,
        GIR_ConstrainSelectedInstOperands, /*InsnID*/0,
        GIR_EraseFromParent, /*InsnID*/0,
        // GIR_Coverage, 7085,
        GIR_Done,
      // Label 3371: @217491
      GIM_Try, /*On fail goto*//*Label 3372*/ GIMT_Encode4(217563), // Rule ID 2749 //
        GIM_CheckFeatures, GIMT_Encode2(GIFBS_isGFX90APlus),
        GIM_CheckIntrinsicID, /*MI*/0, /*Op*/1, GIMT_Encode2(Intrinsic::amdgcn_flat_atomic_fadd),
        GIM_CheckType, /*MI*/0, /*Op*/0, /*Type*/GILLT_s64,
        GIM_CheckType, /*MI*/0, /*Op*/3, /*Type*/GILLT_s64,
        GIM_CheckMemoryAddressSpace, /*MI*/0, /*MMO*/0, /*NumAddrSpace*/4, /*AddrSpace*/0, /*AddrSpace*/1, /*AddrSpace*/4, /*AddrSpace*/6,
        GIM_CheckHasNoUse, /*MI*/0,
        GIM_CheckPointerToAny, /*MI*/0, /*Op*/2, /*SizeInBits*/0,
        GIM_CheckComplexPattern, /*MI*/0, /*Op*/2, /*Renderer*/GIMT_Encode2(0), GIMT_Encode2(GICP_gi_global_offset),
        // (intrinsic_w_chain:{ *:[f64] } 1964:{ *:[iPTR] }, (GlobalOffset:{ *:[iPTR] } i64:{ *:[i64] }:$vaddr, i32:{ *:[i32] }:$offset), f64:{ *:[f64] }:$data)<<P:Predicate_int_amdgcn_flat_atomic_fadd_noret_flat_addrspace>>  =>  (FLAT_ATOMIC_ADD_F64 VReg_64:{ *:[i64] }:$vaddr, anonymous_15036:{ *:[f64] }:$data, ?:{ *:[i32] }:$offset)
        GIR_BuildMI, /*InsnID*/0, /*Opcode*/GIMT_Encode2(AMDGPU::FLAT_ATOMIC_ADD_F64),
        GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/0, // vaddr
        GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/3, // data
        GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/1, // offset
        GIR_AddImm8, /*InsnID*/0, /*Imm*/0,
        GIR_MergeMemOperands, /*InsnID*/0, /*NumInsns*/1, /*MergeInsnID's*/0,
        GIR_ConstrainSelectedInstOperands, /*InsnID*/0,
        GIR_EraseFromParent, /*InsnID*/0,
        // GIR_Coverage, 2749,
        GIR_Done,
      // Label 3372: @217563
      GIM_Try, /*On fail goto*//*Label 3373*/ GIMT_Encode4(217635), // Rule ID 2932 //
        GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasAtomicCSubNoRtnInsts_isGFX12Plus),
        GIM_CheckIntrinsicID, /*MI*/0, /*Op*/1, GIMT_Encode2(Intrinsic::amdgcn_atomic_cond_sub_u32),
        GIM_CheckType, /*MI*/0, /*Op*/0, /*Type*/GILLT_s32,
        GIM_CheckType, /*MI*/0, /*Op*/3, /*Type*/GILLT_s32,
        GIM_CheckMemoryAddressSpace, /*MI*/0, /*MMO*/0, /*NumAddrSpace*/4, /*AddrSpace*/0, /*AddrSpace*/1, /*AddrSpace*/4, /*AddrSpace*/6,
        GIM_CheckHasNoUse, /*MI*/0,
        GIM_CheckPointerToAny, /*MI*/0, /*Op*/2, /*SizeInBits*/0,
        GIM_CheckComplexPattern, /*MI*/0, /*Op*/2, /*Renderer*/GIMT_Encode2(0), GIMT_Encode2(GICP_gi_flat_offset),
        // (intrinsic_w_chain:{ *:[i32] } 1879:{ *:[iPTR] }, (FlatOffset:{ *:[iPTR] } i64:{ *:[i64] }:$vaddr, i32:{ *:[i32] }:$offset), i32:{ *:[i32] }:$data)<<P:Predicate_int_amdgcn_atomic_cond_sub_u32_noret_flat_addrspace>>  =>  (FLAT_ATOMIC_COND_SUB_U32 VReg_64:{ *:[i64] }:$vaddr, anonymous_15037:{ *:[i32] }:$data, ?:{ *:[i32] }:$offset)
        GIR_BuildMI, /*InsnID*/0, /*Opcode*/GIMT_Encode2(AMDGPU::FLAT_ATOMIC_COND_SUB_U32),
        GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/0, // vaddr
        GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/3, // data
        GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/1, // offset
        GIR_AddImm8, /*InsnID*/0, /*Imm*/0,
        GIR_MergeMemOperands, /*InsnID*/0, /*NumInsns*/1, /*MergeInsnID's*/0,
        GIR_ConstrainSelectedInstOperands, /*InsnID*/0,
        GIR_EraseFromParent, /*InsnID*/0,
        // GIR_Coverage, 2932,
        GIR_Done,
      // Label 3373: @217635
      GIM_Try, /*On fail goto*//*Label 3374*/ GIMT_Encode4(217707), // Rule ID 3394 //
        GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasFlatAtomicFaddF32Inst),
        GIM_CheckIntrinsicID, /*MI*/0, /*Op*/1, GIMT_Encode2(Intrinsic::amdgcn_flat_atomic_fadd),
        GIM_CheckType, /*MI*/0, /*Op*/0, /*Type*/GILLT_s32,
        GIM_CheckType, /*MI*/0, /*Op*/3, /*Type*/GILLT_s32,
        GIM_CheckMemoryAddressSpace, /*MI*/0, /*MMO*/0, /*NumAddrSpace*/4, /*AddrSpace*/0, /*AddrSpace*/1, /*AddrSpace*/4, /*AddrSpace*/6,
        GIM_CheckHasNoUse, /*MI*/0,
        GIM_CheckPointerToAny, /*MI*/0, /*Op*/2, /*SizeInBits*/0,
        GIM_CheckComplexPattern, /*MI*/0, /*Op*/2, /*Renderer*/GIMT_Encode2(0), GIMT_Encode2(GICP_gi_global_offset),
        // (intrinsic_w_chain:{ *:[f32] } 1964:{ *:[iPTR] }, (GlobalOffset:{ *:[iPTR] } i64:{ *:[i64] }:$vaddr, i32:{ *:[i32] }:$offset), f32:{ *:[f32] }:$data)<<P:Predicate_int_amdgcn_flat_atomic_fadd_noret_flat_addrspace>>  =>  (FLAT_ATOMIC_ADD_F32 VReg_64:{ *:[i64] }:$vaddr, anonymous_15037:{ *:[f32] }:$data, ?:{ *:[i32] }:$offset)
        GIR_BuildMI, /*InsnID*/0, /*Opcode*/GIMT_Encode2(AMDGPU::FLAT_ATOMIC_ADD_F32),
        GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/0, // vaddr
        GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/3, // data
        GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/1, // offset
        GIR_AddImm8, /*InsnID*/0, /*Imm*/0,
        GIR_MergeMemOperands, /*InsnID*/0, /*NumInsns*/1, /*MergeInsnID's*/0,
        GIR_ConstrainSelectedInstOperands, /*InsnID*/0,
        GIR_EraseFromParent, /*InsnID*/0,
        // GIR_Coverage, 3394,
        GIR_Done,
      // Label 3374: @217707
      GIM_Try, /*On fail goto*//*Label 3375*/ GIMT_Encode4(217779), // Rule ID 3396 //
        GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasAtomicFlatPkAdd16Insts),
        GIM_CheckIntrinsicID, /*MI*/0, /*Op*/1, GIMT_Encode2(Intrinsic::amdgcn_flat_atomic_fadd),
        GIM_CheckType, /*MI*/0, /*Op*/0, /*Type*/GILLT_v2s16,
        GIM_CheckType, /*MI*/0, /*Op*/3, /*Type*/GILLT_v2s16,
        GIM_CheckMemoryAddressSpace, /*MI*/0, /*MMO*/0, /*NumAddrSpace*/4, /*AddrSpace*/0, /*AddrSpace*/1, /*AddrSpace*/4, /*AddrSpace*/6,
        GIM_CheckHasNoUse, /*MI*/0,
        GIM_CheckPointerToAny, /*MI*/0, /*Op*/2, /*SizeInBits*/0,
        GIM_CheckComplexPattern, /*MI*/0, /*Op*/2, /*Renderer*/GIMT_Encode2(0), GIMT_Encode2(GICP_gi_global_offset),
        // (intrinsic_w_chain:{ *:[v2f16] } 1964:{ *:[iPTR] }, (GlobalOffset:{ *:[iPTR] } i64:{ *:[i64] }:$vaddr, i32:{ *:[i32] }:$offset), v2f16:{ *:[v2f16] }:$data)<<P:Predicate_int_amdgcn_flat_atomic_fadd_noret_flat_addrspace>>  =>  (FLAT_ATOMIC_PK_ADD_F16 VReg_64:{ *:[i64] }:$vaddr, anonymous_15037:{ *:[v2f16] }:$data, ?:{ *:[i32] }:$offset)
        GIR_BuildMI, /*InsnID*/0, /*Opcode*/GIMT_Encode2(AMDGPU::FLAT_ATOMIC_PK_ADD_F16),
        GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/0, // vaddr
        GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/3, // data
        GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/1, // offset
        GIR_AddImm8, /*InsnID*/0, /*Imm*/0,
        GIR_MergeMemOperands, /*InsnID*/0, /*NumInsns*/1, /*MergeInsnID's*/0,
        GIR_ConstrainSelectedInstOperands, /*InsnID*/0,
        GIR_EraseFromParent, /*InsnID*/0,
        // GIR_Coverage, 3396,
        GIR_Done,
      // Label 3375: @217779
      GIM_Try, /*On fail goto*//*Label 3376*/ GIMT_Encode4(217843), // Rule ID 3295 //
        GIM_CheckFeatures, GIMT_Encode2(GIFBS_isGFX10GFX11),
        GIM_CheckIntrinsicID, /*MI*/0, /*Op*/1, GIMT_Encode2(Intrinsic::amdgcn_flat_atomic_fmin),
        GIM_CheckType, /*MI*/0, /*Op*/0, /*Type*/GILLT_s32,
        GIM_CheckType, /*MI*/0, /*Op*/3, /*Type*/GILLT_s32,
        GIM_CheckHasNoUse, /*MI*/0,
        GIM_CheckPointerToAny, /*MI*/0, /*Op*/2, /*SizeInBits*/0,
        GIM_CheckComplexPattern, /*MI*/0, /*Op*/2, /*Renderer*/GIMT_Encode2(0), GIMT_Encode2(GICP_gi_global_offset),
        // (intrinsic_w_chain:{ *:[f32] } 1968:{ *:[iPTR] }, (GlobalOffset:{ *:[iPTR] } i64:{ *:[i64] }:$vaddr, i32:{ *:[i32] }:$offset), f32:{ *:[f32] }:$data)<<P:Predicate_int_amdgcn_flat_atomic_fmin_noret>>  =>  (FLAT_ATOMIC_FMIN VReg_64:{ *:[i64] }:$vaddr, anonymous_15037:{ *:[f32] }:$data, ?:{ *:[i32] }:$offset)
        GIR_BuildMI, /*InsnID*/0, /*Opcode*/GIMT_Encode2(AMDGPU::FLAT_ATOMIC_FMIN),
        GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/0, // vaddr
        GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/3, // data
        GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/1, // offset
        GIR_AddImm8, /*InsnID*/0, /*Imm*/0,
        GIR_MergeMemOperands, /*InsnID*/0, /*NumInsns*/1, /*MergeInsnID's*/0,
        GIR_ConstrainSelectedInstOperands, /*InsnID*/0,
        GIR_EraseFromParent, /*InsnID*/0,
        // GIR_Coverage, 3295,
        GIR_Done,
      // Label 3376: @217843
      GIM_Try, /*On fail goto*//*Label 3377*/ GIMT_Encode4(217907), // Rule ID 3297 //
        GIM_CheckFeatures, GIMT_Encode2(GIFBS_isGFX10GFX11),
        GIM_CheckIntrinsicID, /*MI*/0, /*Op*/1, GIMT_Encode2(Intrinsic::amdgcn_flat_atomic_fmax),
        GIM_CheckType, /*MI*/0, /*Op*/0, /*Type*/GILLT_s32,
        GIM_CheckType, /*MI*/0, /*Op*/3, /*Type*/GILLT_s32,
        GIM_CheckHasNoUse, /*MI*/0,
        GIM_CheckPointerToAny, /*MI*/0, /*Op*/2, /*SizeInBits*/0,
        GIM_CheckComplexPattern, /*MI*/0, /*Op*/2, /*Renderer*/GIMT_Encode2(0), GIMT_Encode2(GICP_gi_global_offset),
        // (intrinsic_w_chain:{ *:[f32] } 1966:{ *:[iPTR] }, (GlobalOffset:{ *:[iPTR] } i64:{ *:[i64] }:$vaddr, i32:{ *:[i32] }:$offset), f32:{ *:[f32] }:$data)<<P:Predicate_int_amdgcn_flat_atomic_fmax_noret>>  =>  (FLAT_ATOMIC_FMAX VReg_64:{ *:[i64] }:$vaddr, anonymous_15037:{ *:[f32] }:$data, ?:{ *:[i32] }:$offset)
        GIR_BuildMI, /*InsnID*/0, /*Opcode*/GIMT_Encode2(AMDGPU::FLAT_ATOMIC_FMAX),
        GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/0, // vaddr
        GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/3, // data
        GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/1, // offset
        GIR_AddImm8, /*InsnID*/0, /*Imm*/0,
        GIR_MergeMemOperands, /*InsnID*/0, /*NumInsns*/1, /*MergeInsnID's*/0,
        GIR_ConstrainSelectedInstOperands, /*InsnID*/0,
        GIR_EraseFromParent, /*InsnID*/0,
        // GIR_Coverage, 3297,
        GIR_Done,
      // Label 3377: @217907
      GIM_Try, /*On fail goto*//*Label 3378*/ GIMT_Encode4(217971), // Rule ID 3319 //
        GIM_CheckFeatures, GIMT_Encode2(GIFBS_isGFX10Only),
        GIM_CheckIntrinsicID, /*MI*/0, /*Op*/1, GIMT_Encode2(Intrinsic::amdgcn_flat_atomic_fmin),
        GIM_CheckType, /*MI*/0, /*Op*/0, /*Type*/GILLT_s64,
        GIM_CheckType, /*MI*/0, /*Op*/3, /*Type*/GILLT_s64,
        GIM_CheckHasNoUse, /*MI*/0,
        GIM_CheckPointerToAny, /*MI*/0, /*Op*/2, /*SizeInBits*/0,
        GIM_CheckComplexPattern, /*MI*/0, /*Op*/2, /*Renderer*/GIMT_Encode2(0), GIMT_Encode2(GICP_gi_global_offset),
        // (intrinsic_w_chain:{ *:[f64] } 1968:{ *:[iPTR] }, (GlobalOffset:{ *:[iPTR] } i64:{ *:[i64] }:$vaddr, i32:{ *:[i32] }:$offset), f64:{ *:[f64] }:$data)<<P:Predicate_int_amdgcn_flat_atomic_fmin_noret>>  =>  (FLAT_ATOMIC_FMIN_X2 VReg_64:{ *:[i64] }:$vaddr, anonymous_15036:{ *:[f64] }:$data, ?:{ *:[i32] }:$offset)
        GIR_BuildMI, /*InsnID*/0, /*Opcode*/GIMT_Encode2(AMDGPU::FLAT_ATOMIC_FMIN_X2),
        GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/0, // vaddr
        GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/3, // data
        GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/1, // offset
        GIR_AddImm8, /*InsnID*/0, /*Imm*/0,
        GIR_MergeMemOperands, /*InsnID*/0, /*NumInsns*/1, /*MergeInsnID's*/0,
        GIR_ConstrainSelectedInstOperands, /*InsnID*/0,
        GIR_EraseFromParent, /*InsnID*/0,
        // GIR_Coverage, 3319,
        GIR_Done,
      // Label 3378: @217971
      GIM_Try, /*On fail goto*//*Label 3379*/ GIMT_Encode4(218035), // Rule ID 3321 //
        GIM_CheckFeatures, GIMT_Encode2(GIFBS_isGFX10Only),
        GIM_CheckIntrinsicID, /*MI*/0, /*Op*/1, GIMT_Encode2(Intrinsic::amdgcn_flat_atomic_fmax),
        GIM_CheckType, /*MI*/0, /*Op*/0, /*Type*/GILLT_s64,
        GIM_CheckType, /*MI*/0, /*Op*/3, /*Type*/GILLT_s64,
        GIM_CheckHasNoUse, /*MI*/0,
        GIM_CheckPointerToAny, /*MI*/0, /*Op*/2, /*SizeInBits*/0,
        GIM_CheckComplexPattern, /*MI*/0, /*Op*/2, /*Renderer*/GIMT_Encode2(0), GIMT_Encode2(GICP_gi_global_offset),
        // (intrinsic_w_chain:{ *:[f64] } 1966:{ *:[iPTR] }, (GlobalOffset:{ *:[iPTR] } i64:{ *:[i64] }:$vaddr, i32:{ *:[i32] }:$offset), f64:{ *:[f64] }:$data)<<P:Predicate_int_amdgcn_flat_atomic_fmax_noret>>  =>  (FLAT_ATOMIC_FMAX_X2 VReg_64:{ *:[i64] }:$vaddr, anonymous_15036:{ *:[f64] }:$data, ?:{ *:[i32] }:$offset)
        GIR_BuildMI, /*InsnID*/0, /*Opcode*/GIMT_Encode2(AMDGPU::FLAT_ATOMIC_FMAX_X2),
        GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/0, // vaddr
        GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/3, // data
        GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/1, // offset
        GIR_AddImm8, /*InsnID*/0, /*Imm*/0,
        GIR_MergeMemOperands, /*InsnID*/0, /*NumInsns*/1, /*MergeInsnID's*/0,
        GIR_ConstrainSelectedInstOperands, /*InsnID*/0,
        GIR_EraseFromParent, /*InsnID*/0,
        // GIR_Coverage, 3321,
        GIR_Done,
      // Label 3379: @218035
      GIM_Try, /*On fail goto*//*Label 3380*/ GIMT_Encode4(218099), // Rule ID 3331 //
        GIM_CheckFeatures, GIMT_Encode2(GIFBS_isGFX12Only),
        GIM_CheckIntrinsicID, /*MI*/0, /*Op*/1, GIMT_Encode2(Intrinsic::amdgcn_flat_atomic_fmin_num),
        GIM_CheckType, /*MI*/0, /*Op*/0, /*Type*/GILLT_s32,
        GIM_CheckType, /*MI*/0, /*Op*/3, /*Type*/GILLT_s32,
        GIM_CheckHasNoUse, /*MI*/0,
        GIM_CheckPointerToAny, /*MI*/0, /*Op*/2, /*SizeInBits*/0,
        GIM_CheckComplexPattern, /*MI*/0, /*Op*/2, /*Renderer*/GIMT_Encode2(0), GIMT_Encode2(GICP_gi_global_offset),
        // (intrinsic_w_chain:{ *:[f32] } 1969:{ *:[iPTR] }, (GlobalOffset:{ *:[iPTR] } i64:{ *:[i64] }:$vaddr, i32:{ *:[i32] }:$offset), f32:{ *:[f32] }:$data)<<P:Predicate_int_amdgcn_flat_atomic_fmin_num_noret>>  =>  (FLAT_ATOMIC_FMIN VReg_64:{ *:[i64] }:$vaddr, anonymous_15037:{ *:[f32] }:$data, ?:{ *:[i32] }:$offset)
        GIR_BuildMI, /*InsnID*/0, /*Opcode*/GIMT_Encode2(AMDGPU::FLAT_ATOMIC_FMIN),
        GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/0, // vaddr
        GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/3, // data
        GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/1, // offset
        GIR_AddImm8, /*InsnID*/0, /*Imm*/0,
        GIR_MergeMemOperands, /*InsnID*/0, /*NumInsns*/1, /*MergeInsnID's*/0,
        GIR_ConstrainSelectedInstOperands, /*InsnID*/0,
        GIR_EraseFromParent, /*InsnID*/0,
        // GIR_Coverage, 3331,
        GIR_Done,
      // Label 3380: @218099
      GIM_Try, /*On fail goto*//*Label 3381*/ GIMT_Encode4(218163), // Rule ID 3333 //
        GIM_CheckFeatures, GIMT_Encode2(GIFBS_isGFX12Only),
        GIM_CheckIntrinsicID, /*MI*/0, /*Op*/1, GIMT_Encode2(Intrinsic::amdgcn_flat_atomic_fmax_num),
        GIM_CheckType, /*MI*/0, /*Op*/0, /*Type*/GILLT_s32,
        GIM_CheckType, /*MI*/0, /*Op*/3, /*Type*/GILLT_s32,
        GIM_CheckHasNoUse, /*MI*/0,
        GIM_CheckPointerToAny, /*MI*/0, /*Op*/2, /*SizeInBits*/0,
        GIM_CheckComplexPattern, /*MI*/0, /*Op*/2, /*Renderer*/GIMT_Encode2(0), GIMT_Encode2(GICP_gi_global_offset),
        // (intrinsic_w_chain:{ *:[f32] } 1967:{ *:[iPTR] }, (GlobalOffset:{ *:[iPTR] } i64:{ *:[i64] }:$vaddr, i32:{ *:[i32] }:$offset), f32:{ *:[f32] }:$data)<<P:Predicate_int_amdgcn_flat_atomic_fmax_num_noret>>  =>  (FLAT_ATOMIC_FMAX VReg_64:{ *:[i64] }:$vaddr, anonymous_15037:{ *:[f32] }:$data, ?:{ *:[i32] }:$offset)
        GIR_BuildMI, /*InsnID*/0, /*Opcode*/GIMT_Encode2(AMDGPU::FLAT_ATOMIC_FMAX),
        GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/0, // vaddr
        GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/3, // data
        GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/1, // offset
        GIR_AddImm8, /*InsnID*/0, /*Imm*/0,
        GIR_MergeMemOperands, /*InsnID*/0, /*NumInsns*/1, /*MergeInsnID's*/0,
        GIR_ConstrainSelectedInstOperands, /*InsnID*/0,
        GIR_EraseFromParent, /*InsnID*/0,
        // GIR_Coverage, 3333,
        GIR_Done,
      // Label 3381: @218163
      GIM_Try, /*On fail goto*//*Label 3382*/ GIMT_Encode4(218227), // Rule ID 3389 //
        GIM_CheckFeatures, GIMT_Encode2(GIFBS_isGFX90APlus),
        GIM_CheckIntrinsicID, /*MI*/0, /*Op*/1, GIMT_Encode2(Intrinsic::amdgcn_flat_atomic_fmin),
        GIM_CheckType, /*MI*/0, /*Op*/0, /*Type*/GILLT_s64,
        GIM_CheckType, /*MI*/0, /*Op*/3, /*Type*/GILLT_s64,
        GIM_CheckHasNoUse, /*MI*/0,
        GIM_CheckPointerToAny, /*MI*/0, /*Op*/2, /*SizeInBits*/0,
        GIM_CheckComplexPattern, /*MI*/0, /*Op*/2, /*Renderer*/GIMT_Encode2(0), GIMT_Encode2(GICP_gi_global_offset),
        // (intrinsic_w_chain:{ *:[f64] } 1968:{ *:[iPTR] }, (GlobalOffset:{ *:[iPTR] } i64:{ *:[i64] }:$vaddr, i32:{ *:[i32] }:$offset), f64:{ *:[f64] }:$data)<<P:Predicate_int_amdgcn_flat_atomic_fmin_noret>>  =>  (FLAT_ATOMIC_MIN_F64 VReg_64:{ *:[i64] }:$vaddr, anonymous_15036:{ *:[f64] }:$data, ?:{ *:[i32] }:$offset)
        GIR_BuildMI, /*InsnID*/0, /*Opcode*/GIMT_Encode2(AMDGPU::FLAT_ATOMIC_MIN_F64),
        GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/0, // vaddr
        GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/3, // data
        GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/1, // offset
        GIR_AddImm8, /*InsnID*/0, /*Imm*/0,
        GIR_MergeMemOperands, /*InsnID*/0, /*NumInsns*/1, /*MergeInsnID's*/0,
        GIR_ConstrainSelectedInstOperands, /*InsnID*/0,
        GIR_EraseFromParent, /*InsnID*/0,
        // GIR_Coverage, 3389,
        GIR_Done,
      // Label 3382: @218227
      GIM_Try, /*On fail goto*//*Label 3383*/ GIMT_Encode4(218291), // Rule ID 3391 //
        GIM_CheckFeatures, GIMT_Encode2(GIFBS_isGFX90APlus),
        GIM_CheckIntrinsicID, /*MI*/0, /*Op*/1, GIMT_Encode2(Intrinsic::amdgcn_flat_atomic_fmax),
        GIM_CheckType, /*MI*/0, /*Op*/0, /*Type*/GILLT_s64,
        GIM_CheckType, /*MI*/0, /*Op*/3, /*Type*/GILLT_s64,
        GIM_CheckHasNoUse, /*MI*/0,
        GIM_CheckPointerToAny, /*MI*/0, /*Op*/2, /*SizeInBits*/0,
        GIM_CheckComplexPattern, /*MI*/0, /*Op*/2, /*Renderer*/GIMT_Encode2(0), GIMT_Encode2(GICP_gi_global_offset),
        // (intrinsic_w_chain:{ *:[f64] } 1966:{ *:[iPTR] }, (GlobalOffset:{ *:[iPTR] } i64:{ *:[i64] }:$vaddr, i32:{ *:[i32] }:$offset), f64:{ *:[f64] }:$data)<<P:Predicate_int_amdgcn_flat_atomic_fmax_noret>>  =>  (FLAT_ATOMIC_MAX_F64 VReg_64:{ *:[i64] }:$vaddr, anonymous_15036:{ *:[f64] }:$data, ?:{ *:[i32] }:$offset)
        GIR_BuildMI, /*InsnID*/0, /*Opcode*/GIMT_Encode2(AMDGPU::FLAT_ATOMIC_MAX_F64),
        GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/0, // vaddr
        GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/3, // data
        GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/1, // offset
        GIR_AddImm8, /*InsnID*/0, /*Imm*/0,
        GIR_MergeMemOperands, /*InsnID*/0, /*NumInsns*/1, /*MergeInsnID's*/0,
        GIR_ConstrainSelectedInstOperands, /*InsnID*/0,
        GIR_EraseFromParent, /*InsnID*/0,
        // GIR_Coverage, 3391,
        GIR_Done,
      // Label 3383: @218291
      GIM_Try, /*On fail goto*//*Label 3384*/ GIMT_Encode4(218355), // Rule ID 3399 //
        GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasAtomicFlatPkAdd16Insts),
        GIM_CheckIntrinsicID, /*MI*/0, /*Op*/1, GIMT_Encode2(Intrinsic::amdgcn_flat_atomic_fadd_v2bf16),
        GIM_CheckType, /*MI*/0, /*Op*/0, /*Type*/GILLT_v2s16,
        GIM_CheckType, /*MI*/0, /*Op*/3, /*Type*/GILLT_v2s16,
        GIM_CheckHasNoUse, /*MI*/0,
        GIM_CheckPointerToAny, /*MI*/0, /*Op*/2, /*SizeInBits*/0,
        GIM_CheckComplexPattern, /*MI*/0, /*Op*/2, /*Renderer*/GIMT_Encode2(0), GIMT_Encode2(GICP_gi_global_offset),
        // (intrinsic_w_chain:{ *:[v2i16] } 1965:{ *:[iPTR] }, (GlobalOffset:{ *:[iPTR] } i64:{ *:[i64] }:$vaddr, i32:{ *:[i32] }:$offset), v2i16:{ *:[v2i16] }:$data)<<P:Predicate_int_amdgcn_flat_atomic_fadd_v2bf16_noret>>  =>  (FLAT_ATOMIC_PK_ADD_BF16 VReg_64:{ *:[i64] }:$vaddr, anonymous_15037:{ *:[v2i16] }:$data, ?:{ *:[i32] }:$offset)
        GIR_BuildMI, /*InsnID*/0, /*Opcode*/GIMT_Encode2(AMDGPU::FLAT_ATOMIC_PK_ADD_BF16),
        GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/0, // vaddr
        GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/3, // data
        GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/1, // offset
        GIR_AddImm8, /*InsnID*/0, /*Imm*/0,
        GIR_MergeMemOperands, /*InsnID*/0, /*NumInsns*/1, /*MergeInsnID's*/0,
        GIR_ConstrainSelectedInstOperands, /*InsnID*/0,
        GIR_EraseFromParent, /*InsnID*/0,
        // GIR_Coverage, 3399,
        GIR_Done,
      // Label 3384: @218355
      GIM_Try, /*On fail goto*//*Label 3385*/ GIMT_Encode4(218434), // Rule ID 2750 //
        GIM_CheckFeatures, GIMT_Encode2(GIFBS_isGFX90APlus),
        GIM_CheckIntrinsicID, /*MI*/0, /*Op*/1, GIMT_Encode2(Intrinsic::amdgcn_flat_atomic_fadd),
        GIM_CheckType, /*MI*/0, /*Op*/0, /*Type*/GILLT_s64,
        GIM_CheckType, /*MI*/0, /*Op*/3, /*Type*/GILLT_s64,
        GIM_CheckMemoryAddressSpace, /*MI*/0, /*MMO*/0, /*NumAddrSpace*/4, /*AddrSpace*/0, /*AddrSpace*/1, /*AddrSpace*/4, /*AddrSpace*/6,
        GIM_CheckRegBankForClass, /*MI*/0, /*Op*/0, /*RC*/GIMT_Encode2(AMDGPU::AV_64RegClassID),
        GIM_CheckPointerToAny, /*MI*/0, /*Op*/2, /*SizeInBits*/0,
        GIM_CheckComplexPattern, /*MI*/0, /*Op*/2, /*Renderer*/GIMT_Encode2(0), GIMT_Encode2(GICP_gi_global_offset),
        // (intrinsic_w_chain:{ *:[f64] } 1964:{ *:[iPTR] }, (GlobalOffset:{ *:[iPTR] } i64:{ *:[i64] }:$vaddr, i32:{ *:[i32] }:$offset), f64:{ *:[f64] }:$data)<<P:Predicate_int_amdgcn_flat_atomic_fadd_flat_addrspace>>  =>  (FLAT_ATOMIC_ADD_F64_RTN:{ *:[f64] } VReg_64:{ *:[i64] }:$vaddr, anonymous_15036:{ *:[f64] }:$data, ?:{ *:[i32] }:$offset)
        GIR_BuildMI, /*InsnID*/0, /*Opcode*/GIMT_Encode2(AMDGPU::FLAT_ATOMIC_ADD_F64_RTN),
        GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/0, // DstI[vdst]
        GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/0, // vaddr
        GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/3, // data
        GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/1, // offset
        GIR_AddImm8, /*InsnID*/0, /*Imm*/1,
        GIR_MergeMemOperands, /*InsnID*/0, /*NumInsns*/1, /*MergeInsnID's*/0,
        GIR_ConstrainSelectedInstOperands, /*InsnID*/0,
        GIR_EraseFromParent, /*InsnID*/0,
        // GIR_Coverage, 2750,
        GIR_Done,
      // Label 3385: @218434
      GIM_Try, /*On fail goto*//*Label 3386*/ GIMT_Encode4(218513), // Rule ID 2931 //
        GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasFlatAddressSpace_isGFX12Plus),
        GIM_CheckIntrinsicID, /*MI*/0, /*Op*/1, GIMT_Encode2(Intrinsic::amdgcn_atomic_cond_sub_u32),
        GIM_CheckType, /*MI*/0, /*Op*/0, /*Type*/GILLT_s32,
        GIM_CheckType, /*MI*/0, /*Op*/3, /*Type*/GILLT_s32,
        GIM_CheckMemoryAddressSpace, /*MI*/0, /*MMO*/0, /*NumAddrSpace*/4, /*AddrSpace*/0, /*AddrSpace*/1, /*AddrSpace*/4, /*AddrSpace*/6,
        GIM_CheckRegBankForClass, /*MI*/0, /*Op*/0, /*RC*/GIMT_Encode2(AMDGPU::AV_32RegClassID),
        GIM_CheckPointerToAny, /*MI*/0, /*Op*/2, /*SizeInBits*/0,
        GIM_CheckComplexPattern, /*MI*/0, /*Op*/2, /*Renderer*/GIMT_Encode2(0), GIMT_Encode2(GICP_gi_flat_offset),
        // (intrinsic_w_chain:{ *:[i32] } 1879:{ *:[iPTR] }, (FlatOffset:{ *:[iPTR] } i64:{ *:[i64] }:$vaddr, i32:{ *:[i32] }:$offset), i32:{ *:[i32] }:$data)<<P:Predicate_int_amdgcn_atomic_cond_sub_u32_flat_addrspace>>  =>  (FLAT_ATOMIC_COND_SUB_U32_RTN:{ *:[i32] } VReg_64:{ *:[i64] }:$vaddr, anonymous_15037:{ *:[i32] }:$data, ?:{ *:[i32] }:$offset)
        GIR_BuildMI, /*InsnID*/0, /*Opcode*/GIMT_Encode2(AMDGPU::FLAT_ATOMIC_COND_SUB_U32_RTN),
        GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/0, // DstI[vdst]
        GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/0, // vaddr
        GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/3, // data
        GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/1, // offset
        GIR_AddImm8, /*InsnID*/0, /*Imm*/1,
        GIR_MergeMemOperands, /*InsnID*/0, /*NumInsns*/1, /*MergeInsnID's*/0,
        GIR_ConstrainSelectedInstOperands, /*InsnID*/0,
        GIR_EraseFromParent, /*InsnID*/0,
        // GIR_Coverage, 2931,
        GIR_Done,
      // Label 3386: @218513
      GIM_Try, /*On fail goto*//*Label 3387*/ GIMT_Encode4(218592), // Rule ID 3395 //
        GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasFlatAtomicFaddF32Inst),
        GIM_CheckIntrinsicID, /*MI*/0, /*Op*/1, GIMT_Encode2(Intrinsic::amdgcn_flat_atomic_fadd),
        GIM_CheckType, /*MI*/0, /*Op*/0, /*Type*/GILLT_s32,
        GIM_CheckType, /*MI*/0, /*Op*/3, /*Type*/GILLT_s32,
        GIM_CheckMemoryAddressSpace, /*MI*/0, /*MMO*/0, /*NumAddrSpace*/4, /*AddrSpace*/0, /*AddrSpace*/1, /*AddrSpace*/4, /*AddrSpace*/6,
        GIM_CheckRegBankForClass, /*MI*/0, /*Op*/0, /*RC*/GIMT_Encode2(AMDGPU::AV_32RegClassID),
        GIM_CheckPointerToAny, /*MI*/0, /*Op*/2, /*SizeInBits*/0,
        GIM_CheckComplexPattern, /*MI*/0, /*Op*/2, /*Renderer*/GIMT_Encode2(0), GIMT_Encode2(GICP_gi_global_offset),
        // (intrinsic_w_chain:{ *:[f32] } 1964:{ *:[iPTR] }, (GlobalOffset:{ *:[iPTR] } i64:{ *:[i64] }:$vaddr, i32:{ *:[i32] }:$offset), f32:{ *:[f32] }:$data)<<P:Predicate_int_amdgcn_flat_atomic_fadd_flat_addrspace>>  =>  (FLAT_ATOMIC_ADD_F32_RTN:{ *:[f32] } VReg_64:{ *:[i64] }:$vaddr, anonymous_15037:{ *:[f32] }:$data, ?:{ *:[i32] }:$offset)
        GIR_BuildMI, /*InsnID*/0, /*Opcode*/GIMT_Encode2(AMDGPU::FLAT_ATOMIC_ADD_F32_RTN),
        GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/0, // DstI[vdst]
        GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/0, // vaddr
        GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/3, // data
        GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/1, // offset
        GIR_AddImm8, /*InsnID*/0, /*Imm*/1,
        GIR_MergeMemOperands, /*InsnID*/0, /*NumInsns*/1, /*MergeInsnID's*/0,
        GIR_ConstrainSelectedInstOperands, /*InsnID*/0,
        GIR_EraseFromParent, /*InsnID*/0,
        // GIR_Coverage, 3395,
        GIR_Done,
      // Label 3387: @218592
      GIM_Try, /*On fail goto*//*Label 3388*/ GIMT_Encode4(218671), // Rule ID 3397 //
        GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasAtomicFlatPkAdd16Insts),
        GIM_CheckIntrinsicID, /*MI*/0, /*Op*/1, GIMT_Encode2(Intrinsic::amdgcn_flat_atomic_fadd),
        GIM_CheckType, /*MI*/0, /*Op*/0, /*Type*/GILLT_v2s16,
        GIM_CheckType, /*MI*/0, /*Op*/3, /*Type*/GILLT_v2s16,
        GIM_CheckMemoryAddressSpace, /*MI*/0, /*MMO*/0, /*NumAddrSpace*/4, /*AddrSpace*/0, /*AddrSpace*/1, /*AddrSpace*/4, /*AddrSpace*/6,
        GIM_CheckRegBankForClass, /*MI*/0, /*Op*/0, /*RC*/GIMT_Encode2(AMDGPU::AV_32RegClassID),
        GIM_CheckPointerToAny, /*MI*/0, /*Op*/2, /*SizeInBits*/0,
        GIM_CheckComplexPattern, /*MI*/0, /*Op*/2, /*Renderer*/GIMT_Encode2(0), GIMT_Encode2(GICP_gi_global_offset),
        // (intrinsic_w_chain:{ *:[v2f16] } 1964:{ *:[iPTR] }, (GlobalOffset:{ *:[iPTR] } i64:{ *:[i64] }:$vaddr, i32:{ *:[i32] }:$offset), v2f16:{ *:[v2f16] }:$data)<<P:Predicate_int_amdgcn_flat_atomic_fadd_flat_addrspace>>  =>  (FLAT_ATOMIC_PK_ADD_F16_RTN:{ *:[v2f16] } VReg_64:{ *:[i64] }:$vaddr, anonymous_15037:{ *:[v2f16] }:$data, ?:{ *:[i32] }:$offset)
        GIR_BuildMI, /*InsnID*/0, /*Opcode*/GIMT_Encode2(AMDGPU::FLAT_ATOMIC_PK_ADD_F16_RTN),
        GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/0, // DstI[vdst]
        GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/0, // vaddr
        GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/3, // data
        GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/1, // offset
        GIR_AddImm8, /*InsnID*/0, /*Imm*/1,
        GIR_MergeMemOperands, /*InsnID*/0, /*NumInsns*/1, /*MergeInsnID's*/0,
        GIR_ConstrainSelectedInstOperands, /*InsnID*/0,
        GIR_EraseFromParent, /*InsnID*/0,
        // GIR_Coverage, 3397,
        GIR_Done,
      // Label 3388: @218671
      GIM_Try, /*On fail goto*//*Label 3389*/ GIMT_Encode4(218742), // Rule ID 3294 //
        GIM_CheckFeatures, GIMT_Encode2(GIFBS_isGFX10GFX11),
        GIM_CheckIntrinsicID, /*MI*/0, /*Op*/1, GIMT_Encode2(Intrinsic::amdgcn_flat_atomic_fmin),
        GIM_CheckType, /*MI*/0, /*Op*/0, /*Type*/GILLT_s32,
        GIM_CheckType, /*MI*/0, /*Op*/3, /*Type*/GILLT_s32,
        GIM_CheckRegBankForClass, /*MI*/0, /*Op*/0, /*RC*/GIMT_Encode2(AMDGPU::AV_32RegClassID),
        GIM_CheckPointerToAny, /*MI*/0, /*Op*/2, /*SizeInBits*/0,
        GIM_CheckComplexPattern, /*MI*/0, /*Op*/2, /*Renderer*/GIMT_Encode2(0), GIMT_Encode2(GICP_gi_global_offset),
        // (intrinsic_w_chain:{ *:[f32] } 1968:{ *:[iPTR] }, (GlobalOffset:{ *:[iPTR] } i64:{ *:[i64] }:$vaddr, i32:{ *:[i32] }:$offset), f32:{ *:[f32] }:$data)  =>  (FLAT_ATOMIC_FMIN_RTN:{ *:[f32] } VReg_64:{ *:[i64] }:$vaddr, anonymous_15037:{ *:[f32] }:$data, ?:{ *:[i32] }:$offset)
        GIR_BuildMI, /*InsnID*/0, /*Opcode*/GIMT_Encode2(AMDGPU::FLAT_ATOMIC_FMIN_RTN),
        GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/0, // DstI[vdst]
        GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/0, // vaddr
        GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/3, // data
        GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/1, // offset
        GIR_AddImm8, /*InsnID*/0, /*Imm*/1,
        GIR_MergeMemOperands, /*InsnID*/0, /*NumInsns*/1, /*MergeInsnID's*/0,
        GIR_ConstrainSelectedInstOperands, /*InsnID*/0,
        GIR_EraseFromParent, /*InsnID*/0,
        // GIR_Coverage, 3294,
        GIR_Done,
      // Label 3389: @218742
      GIM_Try, /*On fail goto*//*Label 3390*/ GIMT_Encode4(218813), // Rule ID 3296 //
        GIM_CheckFeatures, GIMT_Encode2(GIFBS_isGFX10GFX11),
        GIM_CheckIntrinsicID, /*MI*/0, /*Op*/1, GIMT_Encode2(Intrinsic::amdgcn_flat_atomic_fmax),
        GIM_CheckType, /*MI*/0, /*Op*/0, /*Type*/GILLT_s32,
        GIM_CheckType, /*MI*/0, /*Op*/3, /*Type*/GILLT_s32,
        GIM_CheckRegBankForClass, /*MI*/0, /*Op*/0, /*RC*/GIMT_Encode2(AMDGPU::AV_32RegClassID),
        GIM_CheckPointerToAny, /*MI*/0, /*Op*/2, /*SizeInBits*/0,
        GIM_CheckComplexPattern, /*MI*/0, /*Op*/2, /*Renderer*/GIMT_Encode2(0), GIMT_Encode2(GICP_gi_global_offset),
        // (intrinsic_w_chain:{ *:[f32] } 1966:{ *:[iPTR] }, (GlobalOffset:{ *:[iPTR] } i64:{ *:[i64] }:$vaddr, i32:{ *:[i32] }:$offset), f32:{ *:[f32] }:$data)  =>  (FLAT_ATOMIC_FMAX_RTN:{ *:[f32] } VReg_64:{ *:[i64] }:$vaddr, anonymous_15037:{ *:[f32] }:$data, ?:{ *:[i32] }:$offset)
        GIR_BuildMI, /*InsnID*/0, /*Opcode*/GIMT_Encode2(AMDGPU::FLAT_ATOMIC_FMAX_RTN),
        GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/0, // DstI[vdst]
        GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/0, // vaddr
        GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/3, // data
        GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/1, // offset
        GIR_AddImm8, /*InsnID*/0, /*Imm*/1,
        GIR_MergeMemOperands, /*InsnID*/0, /*NumInsns*/1, /*MergeInsnID's*/0,
        GIR_ConstrainSelectedInstOperands, /*InsnID*/0,
        GIR_EraseFromParent, /*InsnID*/0,
        // GIR_Coverage, 3296,
        GIR_Done,
      // Label 3390: @218813
      GIM_Try, /*On fail goto*//*Label 3391*/ GIMT_Encode4(218884), // Rule ID 3318 //
        GIM_CheckFeatures, GIMT_Encode2(GIFBS_isGFX10Only),
        GIM_CheckIntrinsicID, /*MI*/0, /*Op*/1, GIMT_Encode2(Intrinsic::amdgcn_flat_atomic_fmin),
        GIM_CheckType, /*MI*/0, /*Op*/0, /*Type*/GILLT_s64,
        GIM_CheckType, /*MI*/0, /*Op*/3, /*Type*/GILLT_s64,
        GIM_CheckRegBankForClass, /*MI*/0, /*Op*/0, /*RC*/GIMT_Encode2(AMDGPU::AV_64RegClassID),
        GIM_CheckPointerToAny, /*MI*/0, /*Op*/2, /*SizeInBits*/0,
        GIM_CheckComplexPattern, /*MI*/0, /*Op*/2, /*Renderer*/GIMT_Encode2(0), GIMT_Encode2(GICP_gi_global_offset),
        // (intrinsic_w_chain:{ *:[f64] } 1968:{ *:[iPTR] }, (GlobalOffset:{ *:[iPTR] } i64:{ *:[i64] }:$vaddr, i32:{ *:[i32] }:$offset), f64:{ *:[f64] }:$data)  =>  (FLAT_ATOMIC_FMIN_X2_RTN:{ *:[f64] } VReg_64:{ *:[i64] }:$vaddr, anonymous_15036:{ *:[f64] }:$data, ?:{ *:[i32] }:$offset)
        GIR_BuildMI, /*InsnID*/0, /*Opcode*/GIMT_Encode2(AMDGPU::FLAT_ATOMIC_FMIN_X2_RTN),
        GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/0, // DstI[vdst]
        GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/0, // vaddr
        GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/3, // data
        GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/1, // offset
        GIR_AddImm8, /*InsnID*/0, /*Imm*/1,
        GIR_MergeMemOperands, /*InsnID*/0, /*NumInsns*/1, /*MergeInsnID's*/0,
        GIR_ConstrainSelectedInstOperands, /*InsnID*/0,
        GIR_EraseFromParent, /*InsnID*/0,
        // GIR_Coverage, 3318,
        GIR_Done,
      // Label 3391: @218884
      GIM_Try, /*On fail goto*//*Label 3392*/ GIMT_Encode4(218955), // Rule ID 3320 //
        GIM_CheckFeatures, GIMT_Encode2(GIFBS_isGFX10Only),
        GIM_CheckIntrinsicID, /*MI*/0, /*Op*/1, GIMT_Encode2(Intrinsic::amdgcn_flat_atomic_fmax),
        GIM_CheckType, /*MI*/0, /*Op*/0, /*Type*/GILLT_s64,
        GIM_CheckType, /*MI*/0, /*Op*/3, /*Type*/GILLT_s64,
        GIM_CheckRegBankForClass, /*MI*/0, /*Op*/0, /*RC*/GIMT_Encode2(AMDGPU::AV_64RegClassID),
        GIM_CheckPointerToAny, /*MI*/0, /*Op*/2, /*SizeInBits*/0,
        GIM_CheckComplexPattern, /*MI*/0, /*Op*/2, /*Renderer*/GIMT_Encode2(0), GIMT_Encode2(GICP_gi_global_offset),
        // (intrinsic_w_chain:{ *:[f64] } 1966:{ *:[iPTR] }, (GlobalOffset:{ *:[iPTR] } i64:{ *:[i64] }:$vaddr, i32:{ *:[i32] }:$offset), f64:{ *:[f64] }:$data)  =>  (FLAT_ATOMIC_FMAX_X2_RTN:{ *:[f64] } VReg_64:{ *:[i64] }:$vaddr, anonymous_15036:{ *:[f64] }:$data, ?:{ *:[i32] }:$offset)
        GIR_BuildMI, /*InsnID*/0, /*Opcode*/GIMT_Encode2(AMDGPU::FLAT_ATOMIC_FMAX_X2_RTN),
        GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/0, // DstI[vdst]
        GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/0, // vaddr
        GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/3, // data
        GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/1, // offset
        GIR_AddImm8, /*InsnID*/0, /*Imm*/1,
        GIR_MergeMemOperands, /*InsnID*/0, /*NumInsns*/1, /*MergeInsnID's*/0,
        GIR_ConstrainSelectedInstOperands, /*InsnID*/0,
        GIR_EraseFromParent, /*InsnID*/0,
        // GIR_Coverage, 3320,
        GIR_Done,
      // Label 3392: @218955
      GIM_Try, /*On fail goto*//*Label 3393*/ GIMT_Encode4(219026), // Rule ID 3330 //
        GIM_CheckFeatures, GIMT_Encode2(GIFBS_isGFX12Only),
        GIM_CheckIntrinsicID, /*MI*/0, /*Op*/1, GIMT_Encode2(Intrinsic::amdgcn_flat_atomic_fmin_num),
        GIM_CheckType, /*MI*/0, /*Op*/0, /*Type*/GILLT_s32,
        GIM_CheckType, /*MI*/0, /*Op*/3, /*Type*/GILLT_s32,
        GIM_CheckRegBankForClass, /*MI*/0, /*Op*/0, /*RC*/GIMT_Encode2(AMDGPU::AV_32RegClassID),
        GIM_CheckPointerToAny, /*MI*/0, /*Op*/2, /*SizeInBits*/0,
        GIM_CheckComplexPattern, /*MI*/0, /*Op*/2, /*Renderer*/GIMT_Encode2(0), GIMT_Encode2(GICP_gi_global_offset),
        // (intrinsic_w_chain:{ *:[f32] } 1969:{ *:[iPTR] }, (GlobalOffset:{ *:[iPTR] } i64:{ *:[i64] }:$vaddr, i32:{ *:[i32] }:$offset), f32:{ *:[f32] }:$data)  =>  (FLAT_ATOMIC_FMIN_RTN:{ *:[f32] } VReg_64:{ *:[i64] }:$vaddr, anonymous_15037:{ *:[f32] }:$data, ?:{ *:[i32] }:$offset)
        GIR_BuildMI, /*InsnID*/0, /*Opcode*/GIMT_Encode2(AMDGPU::FLAT_ATOMIC_FMIN_RTN),
        GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/0, // DstI[vdst]
        GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/0, // vaddr
        GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/3, // data
        GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/1, // offset
        GIR_AddImm8, /*InsnID*/0, /*Imm*/1,
        GIR_MergeMemOperands, /*InsnID*/0, /*NumInsns*/1, /*MergeInsnID's*/0,
        GIR_ConstrainSelectedInstOperands, /*InsnID*/0,
        GIR_EraseFromParent, /*InsnID*/0,
        // GIR_Coverage, 3330,
        GIR_Done,
      // Label 3393: @219026
      GIM_Try, /*On fail goto*//*Label 3394*/ GIMT_Encode4(219097), // Rule ID 3332 //
        GIM_CheckFeatures, GIMT_Encode2(GIFBS_isGFX12Only),
        GIM_CheckIntrinsicID, /*MI*/0, /*Op*/1, GIMT_Encode2(Intrinsic::amdgcn_flat_atomic_fmax_num),
        GIM_CheckType, /*MI*/0, /*Op*/0, /*Type*/GILLT_s32,
        GIM_CheckType, /*MI*/0, /*Op*/3, /*Type*/GILLT_s32,
        GIM_CheckRegBankForClass, /*MI*/0, /*Op*/0, /*RC*/GIMT_Encode2(AMDGPU::AV_32RegClassID),
        GIM_CheckPointerToAny, /*MI*/0, /*Op*/2, /*SizeInBits*/0,
        GIM_CheckComplexPattern, /*MI*/0, /*Op*/2, /*Renderer*/GIMT_Encode2(0), GIMT_Encode2(GICP_gi_global_offset),
        // (intrinsic_w_chain:{ *:[f32] } 1967:{ *:[iPTR] }, (GlobalOffset:{ *:[iPTR] } i64:{ *:[i64] }:$vaddr, i32:{ *:[i32] }:$offset), f32:{ *:[f32] }:$data)  =>  (FLAT_ATOMIC_FMAX_RTN:{ *:[f32] } VReg_64:{ *:[i64] }:$vaddr, anonymous_15037:{ *:[f32] }:$data, ?:{ *:[i32] }:$offset)
        GIR_BuildMI, /*InsnID*/0, /*Opcode*/GIMT_Encode2(AMDGPU::FLAT_ATOMIC_FMAX_RTN),
        GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/0, // DstI[vdst]
        GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/0, // vaddr
        GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/3, // data
        GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/1, // offset
        GIR_AddImm8, /*InsnID*/0, /*Imm*/1,
        GIR_MergeMemOperands, /*InsnID*/0, /*NumInsns*/1, /*MergeInsnID's*/0,
        GIR_ConstrainSelectedInstOperands, /*InsnID*/0,
        GIR_EraseFromParent, /*InsnID*/0,
        // GIR_Coverage, 3332,
        GIR_Done,
      // Label 3394: @219097
      GIM_Try, /*On fail goto*//*Label 3395*/ GIMT_Encode4(219168), // Rule ID 3388 //
        GIM_CheckFeatures, GIMT_Encode2(GIFBS_isGFX90APlus),
        GIM_CheckIntrinsicID, /*MI*/0, /*Op*/1, GIMT_Encode2(Intrinsic::amdgcn_flat_atomic_fmin),
        GIM_CheckType, /*MI*/0, /*Op*/0, /*Type*/GILLT_s64,
        GIM_CheckType, /*MI*/0, /*Op*/3, /*Type*/GILLT_s64,
        GIM_CheckRegBankForClass, /*MI*/0, /*Op*/0, /*RC*/GIMT_Encode2(AMDGPU::AV_64RegClassID),
        GIM_CheckPointerToAny, /*MI*/0, /*Op*/2, /*SizeInBits*/0,
        GIM_CheckComplexPattern, /*MI*/0, /*Op*/2, /*Renderer*/GIMT_Encode2(0), GIMT_Encode2(GICP_gi_global_offset),
        // (intrinsic_w_chain:{ *:[f64] } 1968:{ *:[iPTR] }, (GlobalOffset:{ *:[iPTR] } i64:{ *:[i64] }:$vaddr, i32:{ *:[i32] }:$offset), f64:{ *:[f64] }:$data)  =>  (FLAT_ATOMIC_MIN_F64_RTN:{ *:[f64] } VReg_64:{ *:[i64] }:$vaddr, anonymous_15036:{ *:[f64] }:$data, ?:{ *:[i32] }:$offset)
        GIR_BuildMI, /*InsnID*/0, /*Opcode*/GIMT_Encode2(AMDGPU::FLAT_ATOMIC_MIN_F64_RTN),
        GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/0, // DstI[vdst]
        GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/0, // vaddr
        GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/3, // data
        GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/1, // offset
        GIR_AddImm8, /*InsnID*/0, /*Imm*/1,
        GIR_MergeMemOperands, /*InsnID*/0, /*NumInsns*/1, /*MergeInsnID's*/0,
        GIR_ConstrainSelectedInstOperands, /*InsnID*/0,
        GIR_EraseFromParent, /*InsnID*/0,
        // GIR_Coverage, 3388,
        GIR_Done,
      // Label 3395: @219168
      GIM_Try, /*On fail goto*//*Label 3396*/ GIMT_Encode4(219239), // Rule ID 3390 //
        GIM_CheckFeatures, GIMT_Encode2(GIFBS_isGFX90APlus),
        GIM_CheckIntrinsicID, /*MI*/0, /*Op*/1, GIMT_Encode2(Intrinsic::amdgcn_flat_atomic_fmax),
        GIM_CheckType, /*MI*/0, /*Op*/0, /*Type*/GILLT_s64,
        GIM_CheckType, /*MI*/0, /*Op*/3, /*Type*/GILLT_s64,
        GIM_CheckRegBankForClass, /*MI*/0, /*Op*/0, /*RC*/GIMT_Encode2(AMDGPU::AV_64RegClassID),
        GIM_CheckPointerToAny, /*MI*/0, /*Op*/2, /*SizeInBits*/0,
        GIM_CheckComplexPattern, /*MI*/0, /*Op*/2, /*Renderer*/GIMT_Encode2(0), GIMT_Encode2(GICP_gi_global_offset),
        // (intrinsic_w_chain:{ *:[f64] } 1966:{ *:[iPTR] }, (GlobalOffset:{ *:[iPTR] } i64:{ *:[i64] }:$vaddr, i32:{ *:[i32] }:$offset), f64:{ *:[f64] }:$data)  =>  (FLAT_ATOMIC_MAX_F64_RTN:{ *:[f64] } VReg_64:{ *:[i64] }:$vaddr, anonymous_15036:{ *:[f64] }:$data, ?:{ *:[i32] }:$offset)
        GIR_BuildMI, /*InsnID*/0, /*Opcode*/GIMT_Encode2(AMDGPU::FLAT_ATOMIC_MAX_F64_RTN),
        GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/0, // DstI[vdst]
        GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/0, // vaddr
        GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/3, // data
        GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/1, // offset
        GIR_AddImm8, /*InsnID*/0, /*Imm*/1,
        GIR_MergeMemOperands, /*InsnID*/0, /*NumInsns*/1, /*MergeInsnID's*/0,
        GIR_ConstrainSelectedInstOperands, /*InsnID*/0,
        GIR_EraseFromParent, /*InsnID*/0,
        // GIR_Coverage, 3390,
        GIR_Done,
      // Label 3396: @219239
      GIM_Try, /*On fail goto*//*Label 3397*/ GIMT_Encode4(219310), // Rule ID 3398 //
        GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasAtomicFlatPkAdd16Insts),
        GIM_CheckIntrinsicID, /*MI*/0, /*Op*/1, GIMT_Encode2(Intrinsic::amdgcn_flat_atomic_fadd_v2bf16),
        GIM_CheckType, /*MI*/0, /*Op*/0, /*Type*/GILLT_v2s16,
        GIM_CheckType, /*MI*/0, /*Op*/3, /*Type*/GILLT_v2s16,
        GIM_CheckRegBankForClass, /*MI*/0, /*Op*/0, /*RC*/GIMT_Encode2(AMDGPU::AV_32RegClassID),
        GIM_CheckPointerToAny, /*MI*/0, /*Op*/2, /*SizeInBits*/0,
        GIM_CheckComplexPattern, /*MI*/0, /*Op*/2, /*Renderer*/GIMT_Encode2(0), GIMT_Encode2(GICP_gi_global_offset),
        // (intrinsic_w_chain:{ *:[v2i16] } 1965:{ *:[iPTR] }, (GlobalOffset:{ *:[iPTR] } i64:{ *:[i64] }:$vaddr, i32:{ *:[i32] }:$offset), v2i16:{ *:[v2i16] }:$data)  =>  (FLAT_ATOMIC_PK_ADD_BF16_RTN:{ *:[v2i16] } VReg_64:{ *:[i64] }:$vaddr, anonymous_15037:{ *:[v2i16] }:$data, ?:{ *:[i32] }:$offset)
        GIR_BuildMI, /*InsnID*/0, /*Opcode*/GIMT_Encode2(AMDGPU::FLAT_ATOMIC_PK_ADD_BF16_RTN),
        GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/0, // DstI[vdst]
        GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/0, // vaddr
        GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/3, // data
        GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/1, // offset
        GIR_AddImm8, /*InsnID*/0, /*Imm*/1,
        GIR_MergeMemOperands, /*InsnID*/0, /*NumInsns*/1, /*MergeInsnID's*/0,
        GIR_ConstrainSelectedInstOperands, /*InsnID*/0,
        GIR_EraseFromParent, /*InsnID*/0,
        // GIR_Coverage, 3398,
        GIR_Done,
      // Label 3397: @219310
      GIM_Reject,
    // Label 3287: @219311
    GIM_Try, /*On fail goto*//*Label 3398*/ GIMT_Encode4(219705),
      GIM_CheckNumOperands, /*MI*/0, /*Expected*/7,
      GIM_CheckIntrinsicID, /*MI*/0, /*Op*/0, GIMT_Encode2(Intrinsic::amdgcn_exp_compr),
      GIM_CheckType, /*MI*/0, /*Op*/3, /*Type*/GILLT_v2s16,
      GIM_CheckType, /*MI*/0, /*Op*/4, /*Type*/GILLT_v2s16,
      GIM_CheckIsImm, /*MI*/0, /*Op*/1,
      GIM_CheckIsImm, /*MI*/0, /*Op*/2,
      GIM_CheckRegBankForClass, /*MI*/0, /*Op*/3, /*RC*/GIMT_Encode2(AMDGPU::VGPR_32RegClassID),
      GIM_CheckRegBankForClass, /*MI*/0, /*Op*/4, /*RC*/GIMT_Encode2(AMDGPU::VGPR_32RegClassID),
      GIM_Try, /*On fail goto*//*Label 3399*/ GIMT_Encode4(219437), // Rule ID 5825 //
        // MIs[0] Operand 5
        GIM_CheckLiteralInt, /*MI*/0, /*Op*/5, GIMT_Encode8(0),
        // MIs[0] vm
        GIM_CheckIsImm, /*MI*/0, /*Op*/6,
        // (intrinsic_void 1955:{ *:[iPTR] }, (timm:{ *:[i32] }):$tgt, (timm:{ *:[i32] }):$en, ExpSrc0:{ *:[v2i16] }:$src0, ExpSrc1:{ *:[v2i16] }:$src1, 0:{ *:[i1] }, (timm:{ *:[i1] }):$vm)  =>  (EXP (timm:{ *:[i32] }):$tgt, ExpSrc0:{ *:[v2i16] }:$src0, ExpSrc1:{ *:[v2i16] }:$src1, (IMPLICIT_DEF:{ *:[i16] }), (IMPLICIT_DEF:{ *:[i16] }), (timm:{ *:[i1] }):$vm, 1:{ *:[i1] }, (timm:{ *:[i32] }):$en)
        GIR_MakeTempReg, /*TempRegID*/0, /*TypeID*/GILLT_s16,
        GIR_MakeTempReg, /*TempRegID*/1, /*TypeID*/GILLT_s16,
        GIR_BuildMI, /*InsnID*/2, /*Opcode*/GIMT_Encode2(TargetOpcode::IMPLICIT_DEF),
        GIR_AddTempRegister, /*InsnID*/2, /*TempRegID*/1, /*TempRegFlags*/GIMT_Encode2(RegState::Define),
        GIR_ConstrainSelectedInstOperands, /*InsnID*/2,
        GIR_BuildMI, /*InsnID*/1, /*Opcode*/GIMT_Encode2(TargetOpcode::IMPLICIT_DEF),
        GIR_AddTempRegister, /*InsnID*/1, /*TempRegID*/0, /*TempRegFlags*/GIMT_Encode2(RegState::Define),
        GIR_ConstrainSelectedInstOperands, /*InsnID*/1,
        GIR_BuildMI, /*InsnID*/0, /*Opcode*/GIMT_Encode2(AMDGPU::EXP),
        GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/1, // tgt
        GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/3, // src0
        GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/4, // src1
        GIR_AddSimpleTempRegister, /*InsnID*/0, /*TempRegID*/0,
        GIR_AddSimpleTempRegister, /*InsnID*/0, /*TempRegID*/1,
        GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/6, // vm
        GIR_AddImm8, /*InsnID*/0, /*Imm*/1,
        GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/2, // en
        GIR_MergeMemOperands, /*InsnID*/0, /*NumInsns*/1, /*MergeInsnID's*/0,
        GIR_ConstrainSelectedInstOperands, /*InsnID*/0,
        GIR_EraseFromParent, /*InsnID*/0,
        // GIR_Coverage, 5825,
        GIR_Done,
      // Label 3399: @219437
      GIM_Try, /*On fail goto*//*Label 3400*/ GIMT_Encode4(219526), // Rule ID 5826 //
        // MIs[0] Operand 5
        GIM_CheckLiteralInt, /*MI*/0, /*Op*/5, GIMT_Encode8(-1),
        // MIs[0] vm
        GIM_CheckIsImm, /*MI*/0, /*Op*/6,
        // (intrinsic_void 1955:{ *:[iPTR] }, (timm:{ *:[i32] }):$tgt, (timm:{ *:[i32] }):$en, ExpSrc0:{ *:[v2i16] }:$src0, ExpSrc1:{ *:[v2i16] }:$src1, -1:{ *:[i1] }, (timm:{ *:[i1] }):$vm)  =>  (EXP_DONE (timm:{ *:[i32] }):$tgt, ExpSrc0:{ *:[v2i16] }:$src0, ExpSrc1:{ *:[v2i16] }:$src1, (IMPLICIT_DEF:{ *:[i16] }), (IMPLICIT_DEF:{ *:[i16] }), (timm:{ *:[i1] }):$vm, 1:{ *:[i1] }, (timm:{ *:[i32] }):$en)
        GIR_MakeTempReg, /*TempRegID*/0, /*TypeID*/GILLT_s16,
        GIR_MakeTempReg, /*TempRegID*/1, /*TypeID*/GILLT_s16,
        GIR_BuildMI, /*InsnID*/2, /*Opcode*/GIMT_Encode2(TargetOpcode::IMPLICIT_DEF),
        GIR_AddTempRegister, /*InsnID*/2, /*TempRegID*/1, /*TempRegFlags*/GIMT_Encode2(RegState::Define),
        GIR_ConstrainSelectedInstOperands, /*InsnID*/2,
        GIR_BuildMI, /*InsnID*/1, /*Opcode*/GIMT_Encode2(TargetOpcode::IMPLICIT_DEF),
        GIR_AddTempRegister, /*InsnID*/1, /*TempRegID*/0, /*TempRegFlags*/GIMT_Encode2(RegState::Define),
        GIR_ConstrainSelectedInstOperands, /*InsnID*/1,
        GIR_BuildMI, /*InsnID*/0, /*Opcode*/GIMT_Encode2(AMDGPU::EXP_DONE),
        GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/1, // tgt
        GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/3, // src0
        GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/4, // src1
        GIR_AddSimpleTempRegister, /*InsnID*/0, /*TempRegID*/0,
        GIR_AddSimpleTempRegister, /*InsnID*/0, /*TempRegID*/1,
        GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/6, // vm
        GIR_AddImm8, /*InsnID*/0, /*Imm*/1,
        GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/2, // en
        GIR_MergeMemOperands, /*InsnID*/0, /*NumInsns*/1, /*MergeInsnID's*/0,
        GIR_ConstrainSelectedInstOperands, /*InsnID*/0,
        GIR_EraseFromParent, /*InsnID*/0,
        // GIR_Coverage, 5826,
        GIR_Done,
      // Label 3400: @219526
      GIM_Try, /*On fail goto*//*Label 3401*/ GIMT_Encode4(219615), // Rule ID 5827 //
        // MIs[0] Operand 5
        GIM_CheckLiteralInt, /*MI*/0, /*Op*/5, GIMT_Encode8(0),
        // MIs[0] vm
        GIM_CheckIsImm, /*MI*/0, /*Op*/6,
        // (intrinsic_void 1955:{ *:[iPTR] }, (timm:{ *:[i32] }):$tgt, (timm:{ *:[i32] }):$en, ExpSrc0:{ *:[v2f16] }:$src0, ExpSrc1:{ *:[v2f16] }:$src1, 0:{ *:[i1] }, (timm:{ *:[i1] }):$vm)  =>  (EXP (timm:{ *:[i32] }):$tgt, ExpSrc0:{ *:[v2f16] }:$src0, ExpSrc1:{ *:[v2f16] }:$src1, (IMPLICIT_DEF:{ *:[i16] }), (IMPLICIT_DEF:{ *:[i16] }), (timm:{ *:[i1] }):$vm, 1:{ *:[i1] }, (timm:{ *:[i32] }):$en)
        GIR_MakeTempReg, /*TempRegID*/0, /*TypeID*/GILLT_s16,
        GIR_MakeTempReg, /*TempRegID*/1, /*TypeID*/GILLT_s16,
        GIR_BuildMI, /*InsnID*/2, /*Opcode*/GIMT_Encode2(TargetOpcode::IMPLICIT_DEF),
        GIR_AddTempRegister, /*InsnID*/2, /*TempRegID*/1, /*TempRegFlags*/GIMT_Encode2(RegState::Define),
        GIR_ConstrainSelectedInstOperands, /*InsnID*/2,
        GIR_BuildMI, /*InsnID*/1, /*Opcode*/GIMT_Encode2(TargetOpcode::IMPLICIT_DEF),
        GIR_AddTempRegister, /*InsnID*/1, /*TempRegID*/0, /*TempRegFlags*/GIMT_Encode2(RegState::Define),
        GIR_ConstrainSelectedInstOperands, /*InsnID*/1,
        GIR_BuildMI, /*InsnID*/0, /*Opcode*/GIMT_Encode2(AMDGPU::EXP),
        GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/1, // tgt
        GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/3, // src0
        GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/4, // src1
        GIR_AddSimpleTempRegister, /*InsnID*/0, /*TempRegID*/0,
        GIR_AddSimpleTempRegister, /*InsnID*/0, /*TempRegID*/1,
        GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/6, // vm
        GIR_AddImm8, /*InsnID*/0, /*Imm*/1,
        GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/2, // en
        GIR_MergeMemOperands, /*InsnID*/0, /*NumInsns*/1, /*MergeInsnID's*/0,
        GIR_ConstrainSelectedInstOperands, /*InsnID*/0,
        GIR_EraseFromParent, /*InsnID*/0,
        // GIR_Coverage, 5827,
        GIR_Done,
      // Label 3401: @219615
      GIM_Try, /*On fail goto*//*Label 3402*/ GIMT_Encode4(219704), // Rule ID 5828 //
        // MIs[0] Operand 5
        GIM_CheckLiteralInt, /*MI*/0, /*Op*/5, GIMT_Encode8(-1),
        // MIs[0] vm
        GIM_CheckIsImm, /*MI*/0, /*Op*/6,
        // (intrinsic_void 1955:{ *:[iPTR] }, (timm:{ *:[i32] }):$tgt, (timm:{ *:[i32] }):$en, ExpSrc0:{ *:[v2f16] }:$src0, ExpSrc1:{ *:[v2f16] }:$src1, -1:{ *:[i1] }, (timm:{ *:[i1] }):$vm)  =>  (EXP_DONE (timm:{ *:[i32] }):$tgt, ExpSrc0:{ *:[v2f16] }:$src0, ExpSrc1:{ *:[v2f16] }:$src1, (IMPLICIT_DEF:{ *:[i16] }), (IMPLICIT_DEF:{ *:[i16] }), (timm:{ *:[i1] }):$vm, 1:{ *:[i1] }, (timm:{ *:[i32] }):$en)
        GIR_MakeTempReg, /*TempRegID*/0, /*TypeID*/GILLT_s16,
        GIR_MakeTempReg, /*TempRegID*/1, /*TypeID*/GILLT_s16,
        GIR_BuildMI, /*InsnID*/2, /*Opcode*/GIMT_Encode2(TargetOpcode::IMPLICIT_DEF),
        GIR_AddTempRegister, /*InsnID*/2, /*TempRegID*/1, /*TempRegFlags*/GIMT_Encode2(RegState::Define),
        GIR_ConstrainSelectedInstOperands, /*InsnID*/2,
        GIR_BuildMI, /*InsnID*/1, /*Opcode*/GIMT_Encode2(TargetOpcode::IMPLICIT_DEF),
        GIR_AddTempRegister, /*InsnID*/1, /*TempRegID*/0, /*TempRegFlags*/GIMT_Encode2(RegState::Define),
        GIR_ConstrainSelectedInstOperands, /*InsnID*/1,
        GIR_BuildMI, /*InsnID*/0, /*Opcode*/GIMT_Encode2(AMDGPU::EXP_DONE),
        GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/1, // tgt
        GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/3, // src0
        GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/4, // src1
        GIR_AddSimpleTempRegister, /*InsnID*/0, /*TempRegID*/0,
        GIR_AddSimpleTempRegister, /*InsnID*/0, /*TempRegID*/1,
        GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/6, // vm
        GIR_AddImm8, /*InsnID*/0, /*Imm*/1,
        GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/2, // en
        GIR_MergeMemOperands, /*InsnID*/0, /*NumInsns*/1, /*MergeInsnID's*/0,
        GIR_ConstrainSelectedInstOperands, /*InsnID*/0,
        GIR_EraseFromParent, /*InsnID*/0,
        // GIR_Coverage, 5828,
        GIR_Done,
      // Label 3402: @219704
      GIM_Reject,
    // Label 3398: @219705
    GIM_Try, /*On fail goto*//*Label 3403*/ GIMT_Encode4(220670),
      GIM_CheckNumOperands, /*MI*/0, /*Expected*/9,
      GIM_Try, /*On fail goto*//*Label 3404*/ GIMT_Encode4(219823), // Rule ID 5817 //
        GIM_CheckIntrinsicID, /*MI*/0, /*Op*/0, GIMT_Encode2(Intrinsic::amdgcn_exp),
        GIM_CheckType, /*MI*/0, /*Op*/3, /*Type*/GILLT_s32,
        GIM_CheckType, /*MI*/0, /*Op*/4, /*Type*/GILLT_s32,
        GIM_CheckType, /*MI*/0, /*Op*/5, /*Type*/GILLT_s32,
        GIM_CheckType, /*MI*/0, /*Op*/6, /*Type*/GILLT_s32,
        // MIs[0] tgt
        GIM_CheckIsImm, /*MI*/0, /*Op*/1,
        // MIs[0] en
        GIM_CheckIsImm, /*MI*/0, /*Op*/2,
        GIM_CheckRegBankForClass, /*MI*/0, /*Op*/3, /*RC*/GIMT_Encode2(AMDGPU::VGPR_32RegClassID),
        GIM_CheckRegBankForClass, /*MI*/0, /*Op*/4, /*RC*/GIMT_Encode2(AMDGPU::VGPR_32RegClassID),
        GIM_CheckRegBankForClass, /*MI*/0, /*Op*/5, /*RC*/GIMT_Encode2(AMDGPU::VGPR_32RegClassID),
        GIM_CheckRegBankForClass, /*MI*/0, /*Op*/6, /*RC*/GIMT_Encode2(AMDGPU::VGPR_32RegClassID),
        // MIs[0] Operand 7
        GIM_CheckLiteralInt, /*MI*/0, /*Op*/7, GIMT_Encode8(0),
        // MIs[0] vm
        GIM_CheckIsImm, /*MI*/0, /*Op*/8,
        // (intrinsic_void 1954:{ *:[iPTR] }, (timm:{ *:[i32] }):$tgt, (timm:{ *:[i32] }):$en, ExpSrc0:{ *:[i32] }:$src0, ExpSrc1:{ *:[i32] }:$src1, ExpSrc2:{ *:[i32] }:$src2, ExpSrc3:{ *:[i32] }:$src3, 0:{ *:[i1] }, (timm:{ *:[i1] }):$vm)  =>  (EXP (timm:{ *:[i32] }):$tgt, ExpSrc0:{ *:[i32] }:$src0, ExpSrc1:{ *:[i32] }:$src1, ExpSrc2:{ *:[i32] }:$src2, ExpSrc3:{ *:[i32] }:$src3, (timm:{ *:[i1] }):$vm, 0:{ *:[i1] }, (timm:{ *:[i32] }):$en)
        GIR_BuildMI, /*InsnID*/0, /*Opcode*/GIMT_Encode2(AMDGPU::EXP),
        GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/1, // tgt
        GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/3, // src0
        GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/4, // src1
        GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/5, // src2
        GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/6, // src3
        GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/8, // vm
        GIR_AddImm8, /*InsnID*/0, /*Imm*/0,
        GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/2, // en
        GIR_MergeMemOperands, /*InsnID*/0, /*NumInsns*/1, /*MergeInsnID's*/0,
        GIR_ConstrainSelectedInstOperands, /*InsnID*/0,
        GIR_EraseFromParent, /*InsnID*/0,
        // GIR_Coverage, 5817,
        GIR_Done,
      // Label 3404: @219823
      GIM_Try, /*On fail goto*//*Label 3405*/ GIMT_Encode4(219933), // Rule ID 5818 //
        GIM_CheckIntrinsicID, /*MI*/0, /*Op*/0, GIMT_Encode2(Intrinsic::amdgcn_exp),
        GIM_CheckType, /*MI*/0, /*Op*/3, /*Type*/GILLT_s32,
        GIM_CheckType, /*MI*/0, /*Op*/4, /*Type*/GILLT_s32,
        GIM_CheckType, /*MI*/0, /*Op*/5, /*Type*/GILLT_s32,
        GIM_CheckType, /*MI*/0, /*Op*/6, /*Type*/GILLT_s32,
        // MIs[0] tgt
        GIM_CheckIsImm, /*MI*/0, /*Op*/1,
        // MIs[0] en
        GIM_CheckIsImm, /*MI*/0, /*Op*/2,
        GIM_CheckRegBankForClass, /*MI*/0, /*Op*/3, /*RC*/GIMT_Encode2(AMDGPU::VGPR_32RegClassID),
        GIM_CheckRegBankForClass, /*MI*/0, /*Op*/4, /*RC*/GIMT_Encode2(AMDGPU::VGPR_32RegClassID),
        GIM_CheckRegBankForClass, /*MI*/0, /*Op*/5, /*RC*/GIMT_Encode2(AMDGPU::VGPR_32RegClassID),
        GIM_CheckRegBankForClass, /*MI*/0, /*Op*/6, /*RC*/GIMT_Encode2(AMDGPU::VGPR_32RegClassID),
        // MIs[0] Operand 7
        GIM_CheckLiteralInt, /*MI*/0, /*Op*/7, GIMT_Encode8(-1),
        // MIs[0] vm
        GIM_CheckIsImm, /*MI*/0, /*Op*/8,
        // (intrinsic_void 1954:{ *:[iPTR] }, (timm:{ *:[i32] }):$tgt, (timm:{ *:[i32] }):$en, ExpSrc0:{ *:[i32] }:$src0, ExpSrc1:{ *:[i32] }:$src1, ExpSrc2:{ *:[i32] }:$src2, ExpSrc3:{ *:[i32] }:$src3, -1:{ *:[i1] }, (timm:{ *:[i1] }):$vm)  =>  (EXP_DONE (timm:{ *:[i32] }):$tgt, ExpSrc0:{ *:[i32] }:$src0, ExpSrc1:{ *:[i32] }:$src1, ExpSrc2:{ *:[i32] }:$src2, ExpSrc3:{ *:[i32] }:$src3, (timm:{ *:[i1] }):$vm, 0:{ *:[i1] }, (timm:{ *:[i32] }):$en)
        GIR_BuildMI, /*InsnID*/0, /*Opcode*/GIMT_Encode2(AMDGPU::EXP_DONE),
        GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/1, // tgt
        GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/3, // src0
        GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/4, // src1
        GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/5, // src2
        GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/6, // src3
        GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/8, // vm
        GIR_AddImm8, /*InsnID*/0, /*Imm*/0,
        GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/2, // en
        GIR_MergeMemOperands, /*InsnID*/0, /*NumInsns*/1, /*MergeInsnID's*/0,
        GIR_ConstrainSelectedInstOperands, /*InsnID*/0,
        GIR_EraseFromParent, /*InsnID*/0,
        // GIR_Coverage, 5818,
        GIR_Done,
      // Label 3405: @219933
      GIM_Try, /*On fail goto*//*Label 3406*/ GIMT_Encode4(220043), // Rule ID 5819 //
        GIM_CheckIntrinsicID, /*MI*/0, /*Op*/0, GIMT_Encode2(Intrinsic::amdgcn_exp),
        GIM_CheckType, /*MI*/0, /*Op*/3, /*Type*/GILLT_s32,
        GIM_CheckType, /*MI*/0, /*Op*/4, /*Type*/GILLT_s32,
        GIM_CheckType, /*MI*/0, /*Op*/5, /*Type*/GILLT_s32,
        GIM_CheckType, /*MI*/0, /*Op*/6, /*Type*/GILLT_s32,
        // MIs[0] tgt
        GIM_CheckIsImm, /*MI*/0, /*Op*/1,
        // MIs[0] en
        GIM_CheckIsImm, /*MI*/0, /*Op*/2,
        GIM_CheckRegBankForClass, /*MI*/0, /*Op*/3, /*RC*/GIMT_Encode2(AMDGPU::VGPR_32RegClassID),
        GIM_CheckRegBankForClass, /*MI*/0, /*Op*/4, /*RC*/GIMT_Encode2(AMDGPU::VGPR_32RegClassID),
        GIM_CheckRegBankForClass, /*MI*/0, /*Op*/5, /*RC*/GIMT_Encode2(AMDGPU::VGPR_32RegClassID),
        GIM_CheckRegBankForClass, /*MI*/0, /*Op*/6, /*RC*/GIMT_Encode2(AMDGPU::VGPR_32RegClassID),
        // MIs[0] Operand 7
        GIM_CheckLiteralInt, /*MI*/0, /*Op*/7, GIMT_Encode8(0),
        // MIs[0] vm
        GIM_CheckIsImm, /*MI*/0, /*Op*/8,
        // (intrinsic_void 1954:{ *:[iPTR] }, (timm:{ *:[i32] }):$tgt, (timm:{ *:[i32] }):$en, ExpSrc0:{ *:[f32] }:$src0, ExpSrc1:{ *:[f32] }:$src1, ExpSrc2:{ *:[f32] }:$src2, ExpSrc3:{ *:[f32] }:$src3, 0:{ *:[i1] }, (timm:{ *:[i1] }):$vm)  =>  (EXP (timm:{ *:[i32] }):$tgt, ExpSrc0:{ *:[f32] }:$src0, ExpSrc1:{ *:[f32] }:$src1, ExpSrc2:{ *:[f32] }:$src2, ExpSrc3:{ *:[f32] }:$src3, (timm:{ *:[i1] }):$vm, 0:{ *:[i1] }, (timm:{ *:[i32] }):$en)
        GIR_BuildMI, /*InsnID*/0, /*Opcode*/GIMT_Encode2(AMDGPU::EXP),
        GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/1, // tgt
        GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/3, // src0
        GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/4, // src1
        GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/5, // src2
        GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/6, // src3
        GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/8, // vm
        GIR_AddImm8, /*InsnID*/0, /*Imm*/0,
        GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/2, // en
        GIR_MergeMemOperands, /*InsnID*/0, /*NumInsns*/1, /*MergeInsnID's*/0,
        GIR_ConstrainSelectedInstOperands, /*InsnID*/0,
        GIR_EraseFromParent, /*InsnID*/0,
        // GIR_Coverage, 5819,
        GIR_Done,
      // Label 3406: @220043
      GIM_Try, /*On fail goto*//*Label 3407*/ GIMT_Encode4(220153), // Rule ID 5820 //
        GIM_CheckIntrinsicID, /*MI*/0, /*Op*/0, GIMT_Encode2(Intrinsic::amdgcn_exp),
        GIM_CheckType, /*MI*/0, /*Op*/3, /*Type*/GILLT_s32,
        GIM_CheckType, /*MI*/0, /*Op*/4, /*Type*/GILLT_s32,
        GIM_CheckType, /*MI*/0, /*Op*/5, /*Type*/GILLT_s32,
        GIM_CheckType, /*MI*/0, /*Op*/6, /*Type*/GILLT_s32,
        // MIs[0] tgt
        GIM_CheckIsImm, /*MI*/0, /*Op*/1,
        // MIs[0] en
        GIM_CheckIsImm, /*MI*/0, /*Op*/2,
        GIM_CheckRegBankForClass, /*MI*/0, /*Op*/3, /*RC*/GIMT_Encode2(AMDGPU::VGPR_32RegClassID),
        GIM_CheckRegBankForClass, /*MI*/0, /*Op*/4, /*RC*/GIMT_Encode2(AMDGPU::VGPR_32RegClassID),
        GIM_CheckRegBankForClass, /*MI*/0, /*Op*/5, /*RC*/GIMT_Encode2(AMDGPU::VGPR_32RegClassID),
        GIM_CheckRegBankForClass, /*MI*/0, /*Op*/6, /*RC*/GIMT_Encode2(AMDGPU::VGPR_32RegClassID),
        // MIs[0] Operand 7
        GIM_CheckLiteralInt, /*MI*/0, /*Op*/7, GIMT_Encode8(-1),
        // MIs[0] vm
        GIM_CheckIsImm, /*MI*/0, /*Op*/8,
        // (intrinsic_void 1954:{ *:[iPTR] }, (timm:{ *:[i32] }):$tgt, (timm:{ *:[i32] }):$en, ExpSrc0:{ *:[f32] }:$src0, ExpSrc1:{ *:[f32] }:$src1, ExpSrc2:{ *:[f32] }:$src2, ExpSrc3:{ *:[f32] }:$src3, -1:{ *:[i1] }, (timm:{ *:[i1] }):$vm)  =>  (EXP_DONE (timm:{ *:[i32] }):$tgt, ExpSrc0:{ *:[f32] }:$src0, ExpSrc1:{ *:[f32] }:$src1, ExpSrc2:{ *:[f32] }:$src2, ExpSrc3:{ *:[f32] }:$src3, (timm:{ *:[i1] }):$vm, 0:{ *:[i1] }, (timm:{ *:[i32] }):$en)
        GIR_BuildMI, /*InsnID*/0, /*Opcode*/GIMT_Encode2(AMDGPU::EXP_DONE),
        GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/1, // tgt
        GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/3, // src0
        GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/4, // src1
        GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/5, // src2
        GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/6, // src3
        GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/8, // vm
        GIR_AddImm8, /*InsnID*/0, /*Imm*/0,
        GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/2, // en
        GIR_MergeMemOperands, /*InsnID*/0, /*NumInsns*/1, /*MergeInsnID's*/0,
        GIR_ConstrainSelectedInstOperands, /*InsnID*/0,
        GIR_EraseFromParent, /*InsnID*/0,
        // GIR_Coverage, 5820,
        GIR_Done,
      // Label 3407: @220153
      GIM_Try, /*On fail goto*//*Label 3408*/ GIMT_Encode4(220282), // Rule ID 5821 //
        GIM_CheckIntrinsicID, /*MI*/0, /*Op*/0, GIMT_Encode2(Intrinsic::amdgcn_exp_row),
        GIM_CheckType, /*MI*/0, /*Op*/3, /*Type*/GILLT_s32,
        GIM_CheckType, /*MI*/0, /*Op*/4, /*Type*/GILLT_s32,
        GIM_CheckType, /*MI*/0, /*Op*/5, /*Type*/GILLT_s32,
        GIM_CheckType, /*MI*/0, /*Op*/6, /*Type*/GILLT_s32,
        GIM_CheckType, /*MI*/0, /*Op*/8, /*Type*/GILLT_s32,
        // MIs[0] tgt
        GIM_CheckIsImm, /*MI*/0, /*Op*/1,
        // MIs[0] en
        GIM_CheckIsImm, /*MI*/0, /*Op*/2,
        GIM_CheckRegBankForClass, /*MI*/0, /*Op*/3, /*RC*/GIMT_Encode2(AMDGPU::VGPR_32RegClassID),
        GIM_CheckRegBankForClass, /*MI*/0, /*Op*/4, /*RC*/GIMT_Encode2(AMDGPU::VGPR_32RegClassID),
        GIM_CheckRegBankForClass, /*MI*/0, /*Op*/5, /*RC*/GIMT_Encode2(AMDGPU::VGPR_32RegClassID),
        GIM_CheckRegBankForClass, /*MI*/0, /*Op*/6, /*RC*/GIMT_Encode2(AMDGPU::VGPR_32RegClassID),
        // MIs[0] Operand 7
        GIM_CheckLiteralInt, /*MI*/0, /*Op*/7, GIMT_Encode8(0),
        GIM_CheckRegBankForClass, /*MI*/0, /*Op*/8, /*RC*/GIMT_Encode2(AMDGPU::M0_CLASSRegClassID),
        // (intrinsic_void 1956:{ *:[iPTR] }, (timm:{ *:[i32] }):$tgt, (timm:{ *:[i32] }):$en, ExpSrc0:{ *:[i32] }:$src0, ExpSrc1:{ *:[i32] }:$src1, ExpSrc2:{ *:[i32] }:$src2, ExpSrc3:{ *:[i32] }:$src3, 0:{ *:[i1] }, M0:{ *:[i32] })  =>  (EXP_ROW (timm:{ *:[i32] }):$tgt, ExpSrc0:{ *:[i32] }:$src0, ExpSrc1:{ *:[i32] }:$src1, ExpSrc2:{ *:[i32] }:$src2, ExpSrc3:{ *:[i32] }:$src3, 0:{ *:[i1] }, 0:{ *:[i1] }, (timm:{ *:[i32] }):$en)
        GIR_BuildMI, /*InsnID*/1, /*Opcode*/GIMT_Encode2(TargetOpcode::COPY),
        GIR_AddRegister, /*InsnID*/1, GIMT_Encode2(AMDGPU::M0), /*AddRegisterRegFlags*/GIMT_Encode2(RegState::Define),
        GIR_Copy, /*NewInsnID*/1, /*OldInsnID*/0, /*OpIdx*/8, // M0
        GIR_BuildMI, /*InsnID*/0, /*Opcode*/GIMT_Encode2(AMDGPU::EXP_ROW),
        GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/1, // tgt
        GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/3, // src0
        GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/4, // src1
        GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/5, // src2
        GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/6, // src3
        GIR_AddImm8, /*InsnID*/0, /*Imm*/0,
        GIR_AddImm8, /*InsnID*/0, /*Imm*/0,
        GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/2, // en
        GIR_MergeMemOperands, /*InsnID*/0, /*NumInsns*/1, /*MergeInsnID's*/0,
        GIR_ConstrainSelectedInstOperands, /*InsnID*/0,
        GIR_EraseFromParent, /*InsnID*/0,
        // GIR_Coverage, 5821,
        GIR_Done,
      // Label 3408: @220282
      GIM_Try, /*On fail goto*//*Label 3409*/ GIMT_Encode4(220411), // Rule ID 5822 //
        GIM_CheckIntrinsicID, /*MI*/0, /*Op*/0, GIMT_Encode2(Intrinsic::amdgcn_exp_row),
        GIM_CheckType, /*MI*/0, /*Op*/3, /*Type*/GILLT_s32,
        GIM_CheckType, /*MI*/0, /*Op*/4, /*Type*/GILLT_s32,
        GIM_CheckType, /*MI*/0, /*Op*/5, /*Type*/GILLT_s32,
        GIM_CheckType, /*MI*/0, /*Op*/6, /*Type*/GILLT_s32,
        GIM_CheckType, /*MI*/0, /*Op*/8, /*Type*/GILLT_s32,
        // MIs[0] tgt
        GIM_CheckIsImm, /*MI*/0, /*Op*/1,
        // MIs[0] en
        GIM_CheckIsImm, /*MI*/0, /*Op*/2,
        GIM_CheckRegBankForClass, /*MI*/0, /*Op*/3, /*RC*/GIMT_Encode2(AMDGPU::VGPR_32RegClassID),
        GIM_CheckRegBankForClass, /*MI*/0, /*Op*/4, /*RC*/GIMT_Encode2(AMDGPU::VGPR_32RegClassID),
        GIM_CheckRegBankForClass, /*MI*/0, /*Op*/5, /*RC*/GIMT_Encode2(AMDGPU::VGPR_32RegClassID),
        GIM_CheckRegBankForClass, /*MI*/0, /*Op*/6, /*RC*/GIMT_Encode2(AMDGPU::VGPR_32RegClassID),
        // MIs[0] Operand 7
        GIM_CheckLiteralInt, /*MI*/0, /*Op*/7, GIMT_Encode8(-1),
        GIM_CheckRegBankForClass, /*MI*/0, /*Op*/8, /*RC*/GIMT_Encode2(AMDGPU::M0_CLASSRegClassID),
        // (intrinsic_void 1956:{ *:[iPTR] }, (timm:{ *:[i32] }):$tgt, (timm:{ *:[i32] }):$en, ExpSrc0:{ *:[i32] }:$src0, ExpSrc1:{ *:[i32] }:$src1, ExpSrc2:{ *:[i32] }:$src2, ExpSrc3:{ *:[i32] }:$src3, -1:{ *:[i1] }, M0:{ *:[i32] })  =>  (EXP_ROW_DONE (timm:{ *:[i32] }):$tgt, ExpSrc0:{ *:[i32] }:$src0, ExpSrc1:{ *:[i32] }:$src1, ExpSrc2:{ *:[i32] }:$src2, ExpSrc3:{ *:[i32] }:$src3, 0:{ *:[i1] }, 0:{ *:[i1] }, (timm:{ *:[i32] }):$en)
        GIR_BuildMI, /*InsnID*/1, /*Opcode*/GIMT_Encode2(TargetOpcode::COPY),
        GIR_AddRegister, /*InsnID*/1, GIMT_Encode2(AMDGPU::M0), /*AddRegisterRegFlags*/GIMT_Encode2(RegState::Define),
        GIR_Copy, /*NewInsnID*/1, /*OldInsnID*/0, /*OpIdx*/8, // M0
        GIR_BuildMI, /*InsnID*/0, /*Opcode*/GIMT_Encode2(AMDGPU::EXP_ROW_DONE),
        GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/1, // tgt
        GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/3, // src0
        GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/4, // src1
        GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/5, // src2
        GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/6, // src3
        GIR_AddImm8, /*InsnID*/0, /*Imm*/0,
        GIR_AddImm8, /*InsnID*/0, /*Imm*/0,
        GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/2, // en
        GIR_MergeMemOperands, /*InsnID*/0, /*NumInsns*/1, /*MergeInsnID's*/0,
        GIR_ConstrainSelectedInstOperands, /*InsnID*/0,
        GIR_EraseFromParent, /*InsnID*/0,
        // GIR_Coverage, 5822,
        GIR_Done,
      // Label 3409: @220411
      GIM_Try, /*On fail goto*//*Label 3410*/ GIMT_Encode4(220540), // Rule ID 5823 //
        GIM_CheckIntrinsicID, /*MI*/0, /*Op*/0, GIMT_Encode2(Intrinsic::amdgcn_exp_row),
        GIM_CheckType, /*MI*/0, /*Op*/3, /*Type*/GILLT_s32,
        GIM_CheckType, /*MI*/0, /*Op*/4, /*Type*/GILLT_s32,
        GIM_CheckType, /*MI*/0, /*Op*/5, /*Type*/GILLT_s32,
        GIM_CheckType, /*MI*/0, /*Op*/6, /*Type*/GILLT_s32,
        GIM_CheckType, /*MI*/0, /*Op*/8, /*Type*/GILLT_s32,
        // MIs[0] tgt
        GIM_CheckIsImm, /*MI*/0, /*Op*/1,
        // MIs[0] en
        GIM_CheckIsImm, /*MI*/0, /*Op*/2,
        GIM_CheckRegBankForClass, /*MI*/0, /*Op*/3, /*RC*/GIMT_Encode2(AMDGPU::VGPR_32RegClassID),
        GIM_CheckRegBankForClass, /*MI*/0, /*Op*/4, /*RC*/GIMT_Encode2(AMDGPU::VGPR_32RegClassID),
        GIM_CheckRegBankForClass, /*MI*/0, /*Op*/5, /*RC*/GIMT_Encode2(AMDGPU::VGPR_32RegClassID),
        GIM_CheckRegBankForClass, /*MI*/0, /*Op*/6, /*RC*/GIMT_Encode2(AMDGPU::VGPR_32RegClassID),
        // MIs[0] Operand 7
        GIM_CheckLiteralInt, /*MI*/0, /*Op*/7, GIMT_Encode8(0),
        GIM_CheckRegBankForClass, /*MI*/0, /*Op*/8, /*RC*/GIMT_Encode2(AMDGPU::M0_CLASSRegClassID),
        // (intrinsic_void 1956:{ *:[iPTR] }, (timm:{ *:[i32] }):$tgt, (timm:{ *:[i32] }):$en, ExpSrc0:{ *:[f32] }:$src0, ExpSrc1:{ *:[f32] }:$src1, ExpSrc2:{ *:[f32] }:$src2, ExpSrc3:{ *:[f32] }:$src3, 0:{ *:[i1] }, M0:{ *:[i32] })  =>  (EXP_ROW (timm:{ *:[i32] }):$tgt, ExpSrc0:{ *:[f32] }:$src0, ExpSrc1:{ *:[f32] }:$src1, ExpSrc2:{ *:[f32] }:$src2, ExpSrc3:{ *:[f32] }:$src3, 0:{ *:[i1] }, 0:{ *:[i1] }, (timm:{ *:[i32] }):$en)
        GIR_BuildMI, /*InsnID*/1, /*Opcode*/GIMT_Encode2(TargetOpcode::COPY),
        GIR_AddRegister, /*InsnID*/1, GIMT_Encode2(AMDGPU::M0), /*AddRegisterRegFlags*/GIMT_Encode2(RegState::Define),
        GIR_Copy, /*NewInsnID*/1, /*OldInsnID*/0, /*OpIdx*/8, // M0
        GIR_BuildMI, /*InsnID*/0, /*Opcode*/GIMT_Encode2(AMDGPU::EXP_ROW),
        GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/1, // tgt
        GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/3, // src0
        GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/4, // src1
        GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/5, // src2
        GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/6, // src3
        GIR_AddImm8, /*InsnID*/0, /*Imm*/0,
        GIR_AddImm8, /*InsnID*/0, /*Imm*/0,
        GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/2, // en
        GIR_MergeMemOperands, /*InsnID*/0, /*NumInsns*/1, /*MergeInsnID's*/0,
        GIR_ConstrainSelectedInstOperands, /*InsnID*/0,
        GIR_EraseFromParent, /*InsnID*/0,
        // GIR_Coverage, 5823,
        GIR_Done,
      // Label 3410: @220540
      GIM_Try, /*On fail goto*//*Label 3411*/ GIMT_Encode4(220669), // Rule ID 5824 //
        GIM_CheckIntrinsicID, /*MI*/0, /*Op*/0, GIMT_Encode2(Intrinsic::amdgcn_exp_row),
        GIM_CheckType, /*MI*/0, /*Op*/3, /*Type*/GILLT_s32,
        GIM_CheckType, /*MI*/0, /*Op*/4, /*Type*/GILLT_s32,
        GIM_CheckType, /*MI*/0, /*Op*/5, /*Type*/GILLT_s32,
        GIM_CheckType, /*MI*/0, /*Op*/6, /*Type*/GILLT_s32,
        GIM_CheckType, /*MI*/0, /*Op*/8, /*Type*/GILLT_s32,
        // MIs[0] tgt
        GIM_CheckIsImm, /*MI*/0, /*Op*/1,
        // MIs[0] en
        GIM_CheckIsImm, /*MI*/0, /*Op*/2,
        GIM_CheckRegBankForClass, /*MI*/0, /*Op*/3, /*RC*/GIMT_Encode2(AMDGPU::VGPR_32RegClassID),
        GIM_CheckRegBankForClass, /*MI*/0, /*Op*/4, /*RC*/GIMT_Encode2(AMDGPU::VGPR_32RegClassID),
        GIM_CheckRegBankForClass, /*MI*/0, /*Op*/5, /*RC*/GIMT_Encode2(AMDGPU::VGPR_32RegClassID),
        GIM_CheckRegBankForClass, /*MI*/0, /*Op*/6, /*RC*/GIMT_Encode2(AMDGPU::VGPR_32RegClassID),
        // MIs[0] Operand 7
        GIM_CheckLiteralInt, /*MI*/0, /*Op*/7, GIMT_Encode8(-1),
        GIM_CheckRegBankForClass, /*MI*/0, /*Op*/8, /*RC*/GIMT_Encode2(AMDGPU::M0_CLASSRegClassID),
        // (intrinsic_void 1956:{ *:[iPTR] }, (timm:{ *:[i32] }):$tgt, (timm:{ *:[i32] }):$en, ExpSrc0:{ *:[f32] }:$src0, ExpSrc1:{ *:[f32] }:$src1, ExpSrc2:{ *:[f32] }:$src2, ExpSrc3:{ *:[f32] }:$src3, -1:{ *:[i1] }, M0:{ *:[i32] })  =>  (EXP_ROW_DONE (timm:{ *:[i32] }):$tgt, ExpSrc0:{ *:[f32] }:$src0, ExpSrc1:{ *:[f32] }:$src1, ExpSrc2:{ *:[f32] }:$src2, ExpSrc3:{ *:[f32] }:$src3, 0:{ *:[i1] }, 0:{ *:[i1] }, (timm:{ *:[i32] }):$en)
        GIR_BuildMI, /*InsnID*/1, /*Opcode*/GIMT_Encode2(TargetOpcode::COPY),
        GIR_AddRegister, /*InsnID*/1, GIMT_Encode2(AMDGPU::M0), /*AddRegisterRegFlags*/GIMT_Encode2(RegState::Define),
        GIR_Copy, /*NewInsnID*/1, /*OldInsnID*/0, /*OpIdx*/8, // M0
        GIR_BuildMI, /*InsnID*/0, /*Opcode*/GIMT_Encode2(AMDGPU::EXP_ROW_DONE),
        GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/1, // tgt
        GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/3, // src0
        GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/4, // src1
        GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/5, // src2
        GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/6, // src3
        GIR_AddImm8, /*InsnID*/0, /*Imm*/0,
        GIR_AddImm8, /*InsnID*/0, /*Imm*/0,
        GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/2, // en
        GIR_MergeMemOperands, /*InsnID*/0, /*NumInsns*/1, /*MergeInsnID's*/0,
        GIR_ConstrainSelectedInstOperands, /*InsnID*/0,
        GIR_EraseFromParent, /*InsnID*/0,
        // GIR_Coverage, 5824,
        GIR_Done,
      // Label 3411: @220669
      GIM_Reject,
    // Label 3403: @220670
    GIM_Reject,
    // Label 34: @220671
    GIM_Try, /*On fail goto*//*Label 3412*/ GIMT_Encode4(221119),
      GIM_CheckNumOperands, /*MI*/0, /*Expected*/3,
      GIM_Try, /*On fail goto*//*Label 3413*/ GIMT_Encode4(220729), // Rule ID 6465 //
        GIM_CheckIntrinsicID, /*MI*/0, /*Op*/1, GIMT_Encode2(Intrinsic::amdgcn_readfirstlane),
        GIM_CheckType, /*MI*/0, /*Op*/0, /*Type*/GILLT_s32,
        GIM_CheckType, /*MI*/0, /*Op*/2, /*Type*/GILLT_s32,
        GIM_CheckRegBankForClass, /*MI*/0, /*Op*/0, /*RC*/GIMT_Encode2(AMDGPU::SReg_32RegClassID),
        GIM_RecordInsn, /*DefineMI*/1, /*MI*/0, /*OpIdx*/2, // MIs[1]
        GIM_CheckOpcode, /*MI*/1, GIMT_Encode2(TargetOpcode::G_CONSTANT),
        // MIs[1] Operand 1
        // No operand predicates
        GIM_CheckIsSafeToFold, /*InsnID*/1,
        // (intrinsic_wo_chain:{ *:[i32] } 2649:{ *:[iPTR] }, (imm:{ *:[i32] }):$src)  =>  (S_MOV_B32:{ *:[i32] } SReg_32:{ *:[i32] }:$src)
        GIR_BuildMI, /*InsnID*/0, /*Opcode*/GIMT_Encode2(AMDGPU::S_MOV_B32),
        GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/0, // DstI[sdst]
        GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/2, // src
        GIR_ConstrainSelectedInstOperands, /*InsnID*/0,
        GIR_EraseFromParent, /*InsnID*/0,
        // GIR_Coverage, 6465,
        GIR_Done,
      // Label 3413: @220729
      GIM_Try, /*On fail goto*//*Label 3414*/ GIMT_Encode4(220774), // Rule ID 573 //
        GIM_CheckIntrinsicID, /*MI*/0, /*Op*/1, GIMT_Encode2(Intrinsic::amdgcn_readfirstlane),
        GIM_CheckType, /*MI*/0, /*Op*/0, /*Type*/GILLT_s32,
        GIM_CheckType, /*MI*/0, /*Op*/2, /*Type*/GILLT_s32,
        GIM_CheckRegBankForClass, /*MI*/0, /*Op*/0, /*RC*/GIMT_Encode2(AMDGPU::SReg_32RegClassID),
        GIM_CheckRegBankForClass, /*MI*/0, /*Op*/2, /*RC*/GIMT_Encode2(AMDGPU::VRegOrLds_32RegClassID),
        // (intrinsic_wo_chain:{ *:[i32] } 2649:{ *:[iPTR] }, VRegOrLdsSrc_32:{ *:[i32] }:$src0)  =>  (V_READFIRSTLANE_B32:{ *:[i32] } VRegOrLdsSrc_32:{ *:[i32] }:$src0)
        GIR_BuildMI, /*InsnID*/0, /*Opcode*/GIMT_Encode2(AMDGPU::V_READFIRSTLANE_B32),
        GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/0, // DstI[vdst]
        GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/2, // src0
        GIR_ConstrainSelectedInstOperands, /*InsnID*/0,
        GIR_EraseFromParent, /*InsnID*/0,
        // GIR_Coverage, 573,
        GIR_Done,
      // Label 3414: @220774
      GIM_Try, /*On fail goto*//*Label 3415*/ GIMT_Encode4(220817), // Rule ID 2 //
        GIM_CheckIntrinsicID, /*MI*/0, /*Op*/1, GIMT_Encode2(Intrinsic::amdgcn_s_wqm),
        GIM_CheckType, /*MI*/0, /*Op*/0, /*Type*/GILLT_s32,
        GIM_CheckType, /*MI*/0, /*Op*/2, /*Type*/GILLT_s32,
        GIM_CheckRegBankForClass, /*MI*/0, /*Op*/0, /*RC*/GIMT_Encode2(AMDGPU::SReg_32RegClassID),
        // (intrinsic_wo_chain:{ *:[i32] } 2700:{ *:[iPTR] }, i32:{ *:[i32] }:$src0)  =>  (S_WQM_B32:{ *:[i32] }:{ *:[i1] } i32:{ *:[i32] }:$src0)
        GIR_BuildMI, /*InsnID*/0, /*Opcode*/GIMT_Encode2(AMDGPU::S_WQM_B32),
        GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/0, // DstI[sdst]
        GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/2, // src0
        GIR_SetImplicitDefDead, /*InsnID*/0, /*OpIdx for AMDGPU::SCC*/0,
        GIR_ConstrainSelectedInstOperands, /*InsnID*/0,
        GIR_EraseFromParent, /*InsnID*/0,
        // GIR_Coverage, 2,
        GIR_Done,
      // Label 3415: @220817
      GIM_Try, /*On fail goto*//*Label 3416*/ GIMT_Encode4(220860), // Rule ID 3 //
        GIM_CheckIntrinsicID, /*MI*/0, /*Op*/1, GIMT_Encode2(Intrinsic::amdgcn_s_wqm),
        GIM_CheckType, /*MI*/0, /*Op*/0, /*Type*/GILLT_s64,
        GIM_CheckType, /*MI*/0, /*Op*/2, /*Type*/GILLT_s64,
        GIM_CheckRegBankForClass, /*MI*/0, /*Op*/0, /*RC*/GIMT_Encode2(AMDGPU::SReg_64RegClassID),
        // (intrinsic_wo_chain:{ *:[i64] } 2700:{ *:[iPTR] }, i64:{ *:[i64] }:$src0)  =>  (S_WQM_B64:{ *:[i64] }:{ *:[i1] } i64:{ *:[i64] }:$src0)
        GIR_BuildMI, /*InsnID*/0, /*Opcode*/GIMT_Encode2(AMDGPU::S_WQM_B64),
        GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/0, // DstI[sdst]
        GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/2, // src0
        GIR_SetImplicitDefDead, /*InsnID*/0, /*OpIdx for AMDGPU::SCC*/0,
        GIR_ConstrainSelectedInstOperands, /*InsnID*/0,
        GIR_EraseFromParent, /*InsnID*/0,
        // GIR_Coverage, 3,
        GIR_Done,
      // Label 3416: @220860
      GIM_Try, /*On fail goto*//*Label 3417*/ GIMT_Encode4(220900), // Rule ID 21 //
        GIM_CheckIntrinsicID, /*MI*/0, /*Op*/1, GIMT_Encode2(Intrinsic::amdgcn_s_quadmask),
        GIM_CheckType, /*MI*/0, /*Op*/0, /*Type*/GILLT_s32,
        GIM_CheckType, /*MI*/0, /*Op*/2, /*Type*/GILLT_s32,
        GIM_CheckRegBankForClass, /*MI*/0, /*Op*/0, /*RC*/GIMT_Encode2(AMDGPU::SReg_32RegClassID),
        // (intrinsic_wo_chain:{ *:[i32] } 2679:{ *:[iPTR] }, i32:{ *:[i32] }:$src0)  =>  (S_QUADMASK_B32:{ *:[i32] } i32:{ *:[i32] }:$src0)
        GIR_BuildMI, /*InsnID*/0, /*Opcode*/GIMT_Encode2(AMDGPU::S_QUADMASK_B32),
        GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/0, // DstI[sdst]
        GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/2, // src0
        GIR_ConstrainSelectedInstOperands, /*InsnID*/0,
        GIR_EraseFromParent, /*InsnID*/0,
        // GIR_Coverage, 21,
        GIR_Done,
      // Label 3417: @220900
      GIM_Try, /*On fail goto*//*Label 3418*/ GIMT_Encode4(220940), // Rule ID 22 //
        GIM_CheckIntrinsicID, /*MI*/0, /*Op*/1, GIMT_Encode2(Intrinsic::amdgcn_s_quadmask),
        GIM_CheckType, /*MI*/0, /*Op*/0, /*Type*/GILLT_s64,
        GIM_CheckType, /*MI*/0, /*Op*/2, /*Type*/GILLT_s64,
        GIM_CheckRegBankForClass, /*MI*/0, /*Op*/0, /*RC*/GIMT_Encode2(AMDGPU::SReg_64RegClassID),
        // (intrinsic_wo_chain:{ *:[i64] } 2679:{ *:[iPTR] }, i64:{ *:[i64] }:$src0)  =>  (S_QUADMASK_B64:{ *:[i64] } i64:{ *:[i64] }:$src0)
        GIR_BuildMI, /*InsnID*/0, /*Opcode*/GIMT_Encode2(AMDGPU::S_QUADMASK_B64),
        GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/0, // DstI[sdst]
        GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/2, // src0
        GIR_ConstrainSelectedInstOperands, /*InsnID*/0,
        GIR_EraseFromParent, /*InsnID*/0,
        // GIR_Coverage, 22,
        GIR_Done,
      // Label 3418: @220940
      GIM_Try, /*On fail goto*//*Label 3419*/ GIMT_Encode4(220983), // Rule ID 24 //
        GIM_CheckFeatures, GIMT_Encode2(GIFBS_isGFX9Plus),
        GIM_CheckIntrinsicID, /*MI*/0, /*Op*/1, GIMT_Encode2(Intrinsic::amdgcn_s_bitreplicate),
        GIM_CheckType, /*MI*/0, /*Op*/0, /*Type*/GILLT_s64,
        GIM_CheckType, /*MI*/0, /*Op*/2, /*Type*/GILLT_s32,
        GIM_CheckRegBankForClass, /*MI*/0, /*Op*/0, /*RC*/GIMT_Encode2(AMDGPU::SReg_64RegClassID),
        // (intrinsic_wo_chain:{ *:[i64] } 2664:{ *:[iPTR] }, i32:{ *:[i32] }:$src0)  =>  (S_BITREPLICATE_B64_B32:{ *:[i64] } i32:{ *:[i32] }:$src0)
        GIR_BuildMI, /*InsnID*/0, /*Opcode*/GIMT_Encode2(AMDGPU::S_BITREPLICATE_B64_B32),
        GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/0, // DstI[sdst]
        GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/2, // src0
        GIR_ConstrainSelectedInstOperands, /*InsnID*/0,
        GIR_EraseFromParent, /*InsnID*/0,
        // GIR_Coverage, 24,
        GIR_Done,
      // Label 3419: @220983
      GIM_Try, /*On fail goto*//*Label 3420*/ GIMT_Encode4(221026), // Rule ID 722 //
        GIM_CheckFeatures, GIMT_Encode2(GIFBS_isGFX11Plus),
        GIM_CheckIntrinsicID, /*MI*/0, /*Op*/1, GIMT_Encode2(Intrinsic::amdgcn_permlane64),
        GIM_CheckType, /*MI*/0, /*Op*/0, /*Type*/GILLT_s32,
        GIM_CheckType, /*MI*/0, /*Op*/2, /*Type*/GILLT_s32,
        GIM_CheckRegBankForClass, /*MI*/0, /*Op*/0, /*RC*/GIMT_Encode2(AMDGPU::VGPR_32RegClassID),
        // (intrinsic_wo_chain:{ *:[i32] } 2591:{ *:[iPTR] }, i32:{ *:[i32] }:$src0)  =>  (V_PERMLANE64_B32:{ *:[i32] } i32:{ *:[i32] }:$src0)
        GIR_BuildMI, /*InsnID*/0, /*Opcode*/GIMT_Encode2(AMDGPU::V_PERMLANE64_B32),
        GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/0, // DstI[vdst]
        GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/2, // src0
        GIR_ConstrainSelectedInstOperands, /*InsnID*/0,
        GIR_EraseFromParent, /*InsnID*/0,
        // GIR_Coverage, 722,
        GIR_Done,
      // Label 3420: @221026
      GIM_Try, /*On fail goto*//*Label 3421*/ GIMT_Encode4(221072), // Rule ID 1640 //
        GIM_CheckFeatures, GIMT_Encode2(GIFBS_isWave32),
        GIM_CheckIntrinsicID, /*MI*/0, /*Op*/1, GIMT_Encode2(Intrinsic::amdgcn_wqm_vote),
        GIM_CheckType, /*MI*/0, /*Op*/0, /*Type*/GILLT_s1,
        GIM_CheckType, /*MI*/0, /*Op*/2, /*Type*/GILLT_s1,
        GIM_CheckRegBankForClass, /*MI*/0, /*Op*/0, /*RC*/GIMT_Encode2(AMDGPU::SReg_32RegClassID),
        // (intrinsic_wo_chain:{ *:[i1] } 2830:{ *:[iPTR] }, i1:{ *:[i1] }:$src0)  =>  (S_WQM_B32:{ *:[i1] }:{ *:[i1] } SSrc_b32:{ *:[i1] }:$src0)
        GIR_BuildMI, /*InsnID*/0, /*Opcode*/GIMT_Encode2(AMDGPU::S_WQM_B32),
        GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/0, // DstI[sdst]
        GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/2, // src0
        GIR_SetImplicitDefDead, /*InsnID*/0, /*OpIdx for AMDGPU::SCC*/0,
        GIR_ConstrainSelectedInstOperands, /*InsnID*/0,
        GIR_EraseFromParent, /*InsnID*/0,
        // GIR_Coverage, 1640,
        GIR_Done,
      // Label 3421: @221072
      GIM_Try, /*On fail goto*//*Label 3422*/ GIMT_Encode4(221118), // Rule ID 1641 //
        GIM_CheckFeatures, GIMT_Encode2(GIFBS_isWave64),
        GIM_CheckIntrinsicID, /*MI*/0, /*Op*/1, GIMT_Encode2(Intrinsic::amdgcn_wqm_vote),
        GIM_CheckType, /*MI*/0, /*Op*/0, /*Type*/GILLT_s1,
        GIM_CheckType, /*MI*/0, /*Op*/2, /*Type*/GILLT_s1,
        GIM_CheckRegBankForClass, /*MI*/0, /*Op*/0, /*RC*/GIMT_Encode2(AMDGPU::SReg_64RegClassID),
        // (intrinsic_wo_chain:{ *:[i1] } 2830:{ *:[iPTR] }, i1:{ *:[i1] }:$src0)  =>  (S_WQM_B64:{ *:[i1] }:{ *:[i1] } SSrc_b64:{ *:[i1] }:$src0)
        GIR_BuildMI, /*InsnID*/0, /*Opcode*/GIMT_Encode2(AMDGPU::S_WQM_B64),
        GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/0, // DstI[sdst]
        GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/2, // src0
        GIR_SetImplicitDefDead, /*InsnID*/0, /*OpIdx for AMDGPU::SCC*/0,
        GIR_ConstrainSelectedInstOperands, /*InsnID*/0,
        GIR_EraseFromParent, /*InsnID*/0,
        // GIR_Coverage, 1641,
        GIR_Done,
      // Label 3422: @221118
      GIM_Reject,
    // Label 3412: @221119
    GIM_Try, /*On fail goto*//*Label 3423*/ GIMT_Encode4(221846),
      GIM_CheckNumOperands, /*MI*/0, /*Expected*/4,
      GIM_Try, /*On fail goto*//*Label 3424*/ GIMT_Encode4(221191), // Rule ID 1142 //
        GIM_CheckFeatures, GIMT_Encode2(GIFBS_isGFX8Plus),
        GIM_CheckIntrinsicID, /*MI*/0, /*Op*/1, GIMT_Encode2(Intrinsic::amdgcn_ds_permute),
        GIM_CheckType, /*MI*/0, /*Op*/0, /*Type*/GILLT_s32,
        GIM_CheckType, /*MI*/0, /*Op*/2, /*Type*/GILLT_s32,
        GIM_CheckType, /*MI*/0, /*Op*/3, /*Type*/GILLT_s32,
        GIM_CheckRegBankForClass, /*MI*/0, /*Op*/0, /*RC*/GIMT_Encode2(AMDGPU::AV_32RegClassID),
        GIM_CheckComplexPattern, /*MI*/0, /*Op*/2, /*Renderer*/GIMT_Encode2(0), GIMT_Encode2(GICP_gi_ds_1addr_1offset),
        // (intrinsic_wo_chain:{ *:[i32] } 1948:{ *:[iPTR] }, (DS1Addr1Offset:{ *:[i32] } i32:{ *:[i32] }:$addr, i32:{ *:[i32] }:$offset), i32:{ *:[i32] }:$data0)  =>  (DS_PERMUTE_B32:{ *:[i32] } i32:{ *:[i32] }:$addr, i32:{ *:[i32] }:$data0, i32:{ *:[i32] }:$offset)
        GIR_BuildMI, /*InsnID*/0, /*Opcode*/GIMT_Encode2(AMDGPU::DS_PERMUTE_B32),
        GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/0, // DstI[vdst]
        GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/0, // addr
        GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/3, // data0
        GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/1, // offset
        GIR_ConstrainSelectedInstOperands, /*InsnID*/0,
        GIR_EraseFromParent, /*InsnID*/0,
        // GIR_Coverage, 1142,
        GIR_Done,
      // Label 3424: @221191
      GIM_Try, /*On fail goto*//*Label 3425*/ GIMT_Encode4(221255), // Rule ID 1143 //
        GIM_CheckFeatures, GIMT_Encode2(GIFBS_isGFX8Plus),
        GIM_CheckIntrinsicID, /*MI*/0, /*Op*/1, GIMT_Encode2(Intrinsic::amdgcn_ds_bpermute),
        GIM_CheckType, /*MI*/0, /*Op*/0, /*Type*/GILLT_s32,
        GIM_CheckType, /*MI*/0, /*Op*/2, /*Type*/GILLT_s32,
        GIM_CheckType, /*MI*/0, /*Op*/3, /*Type*/GILLT_s32,
        GIM_CheckRegBankForClass, /*MI*/0, /*Op*/0, /*RC*/GIMT_Encode2(AMDGPU::AV_32RegClassID),
        GIM_CheckComplexPattern, /*MI*/0, /*Op*/2, /*Renderer*/GIMT_Encode2(0), GIMT_Encode2(GICP_gi_ds_1addr_1offset),
        // (intrinsic_wo_chain:{ *:[i32] } 1933:{ *:[iPTR] }, (DS1Addr1Offset:{ *:[i32] } i32:{ *:[i32] }:$addr, i32:{ *:[i32] }:$offset), i32:{ *:[i32] }:$data0)  =>  (DS_BPERMUTE_B32:{ *:[i32] } i32:{ *:[i32] }:$addr, i32:{ *:[i32] }:$data0, i32:{ *:[i32] }:$offset)
        GIR_BuildMI, /*InsnID*/0, /*Opcode*/GIMT_Encode2(AMDGPU::DS_BPERMUTE_B32),
        GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/0, // DstI[vdst]
        GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/0, // addr
        GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/3, // data0
        GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/1, // offset
        GIR_ConstrainSelectedInstOperands, /*InsnID*/0,
        GIR_EraseFromParent, /*InsnID*/0,
        // GIR_Coverage, 1143,
        GIR_Done,
      // Label 3425: @221255
      GIM_Try, /*On fail goto*//*Label 3426*/ GIMT_Encode4(221321), // Rule ID 2089 //
        GIM_CheckFeatures, GIMT_Encode2(GIFBS_isGFX10Only),
        GIM_CheckIntrinsicID, /*MI*/0, /*Op*/1, GIMT_Encode2(Intrinsic::amdgcn_mov_dpp8),
        GIM_CheckType, /*MI*/0, /*Op*/0, /*Type*/GILLT_s32,
        GIM_CheckType, /*MI*/0, /*Op*/2, /*Type*/GILLT_s32,
        GIM_CheckRegBankForClass, /*MI*/0, /*Op*/0, /*RC*/GIMT_Encode2(AMDGPU::VGPR_32RegClassID),
        // MIs[0] dpp8
        GIM_CheckIsImm, /*MI*/0, /*Op*/3,
        // (intrinsic_wo_chain:{ *:[i32] } 2580:{ *:[iPTR] }, i32:{ *:[i32] }:$src, (timm:{ *:[i32] }):$dpp8)  =>  (V_MOV_B32_dpp8_gfx10:{ *:[i32] } VGPR_32:{ *:[i32] }:$src, VGPR_32:{ *:[i32] }:$src, (as_i32timm:{ *:[i32] } ?:{ *:[i32] }:$dpp8), 233:{ *:[i32] })
        GIR_BuildMI, /*InsnID*/0, /*Opcode*/GIMT_Encode2(AMDGPU::V_MOV_B32_dpp8_gfx10),
        GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/0, // DstI[vdst]
        GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/2, // src
        GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/2, // src
        GIR_CustomOperandRenderer, /*InsnID*/0, /*OldInsnID*/0, /*OpIdx*/3, /*OperandRenderer*/GIMT_Encode2(GICR_renderTruncTImm), // dpp8
        GIR_AddImm, /*InsnID*/0, /*Imm*/GIMT_Encode8(233),
        GIR_ConstrainSelectedInstOperands, /*InsnID*/0,
        GIR_EraseFromParent, /*InsnID*/0,
        // GIR_Coverage, 2089,
        GIR_Done,
      // Label 3426: @221321
      GIM_Try, /*On fail goto*//*Label 3427*/ GIMT_Encode4(221387), // Rule ID 2090 //
        GIM_CheckFeatures, GIMT_Encode2(GIFBS_isGFX11Only),
        GIM_CheckIntrinsicID, /*MI*/0, /*Op*/1, GIMT_Encode2(Intrinsic::amdgcn_mov_dpp8),
        GIM_CheckType, /*MI*/0, /*Op*/0, /*Type*/GILLT_s32,
        GIM_CheckType, /*MI*/0, /*Op*/2, /*Type*/GILLT_s32,
        GIM_CheckRegBankForClass, /*MI*/0, /*Op*/0, /*RC*/GIMT_Encode2(AMDGPU::VGPR_32RegClassID),
        // MIs[0] dpp8
        GIM_CheckIsImm, /*MI*/0, /*Op*/3,
        // (intrinsic_wo_chain:{ *:[i32] } 2580:{ *:[iPTR] }, i32:{ *:[i32] }:$src, (timm:{ *:[i32] }):$dpp8)  =>  (V_MOV_B32_dpp8_gfx11:{ *:[i32] } VGPR_32:{ *:[i32] }:$src, VGPR_32:{ *:[i32] }:$src, (as_i32timm:{ *:[i32] } ?:{ *:[i32] }:$dpp8), 233:{ *:[i32] })
        GIR_BuildMI, /*InsnID*/0, /*Opcode*/GIMT_Encode2(AMDGPU::V_MOV_B32_dpp8_gfx11),
        GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/0, // DstI[vdst]
        GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/2, // src
        GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/2, // src
        GIR_CustomOperandRenderer, /*InsnID*/0, /*OldInsnID*/0, /*OpIdx*/3, /*OperandRenderer*/GIMT_Encode2(GICR_renderTruncTImm), // dpp8
        GIR_AddImm, /*InsnID*/0, /*Imm*/GIMT_Encode8(233),
        GIR_ConstrainSelectedInstOperands, /*InsnID*/0,
        GIR_EraseFromParent, /*InsnID*/0,
        // GIR_Coverage, 2090,
        GIR_Done,
      // Label 3427: @221387
      GIM_Try, /*On fail goto*//*Label 3428*/ GIMT_Encode4(221453), // Rule ID 2091 //
        GIM_CheckFeatures, GIMT_Encode2(GIFBS_isGFX12Only),
        GIM_CheckIntrinsicID, /*MI*/0, /*Op*/1, GIMT_Encode2(Intrinsic::amdgcn_mov_dpp8),
        GIM_CheckType, /*MI*/0, /*Op*/0, /*Type*/GILLT_s32,
        GIM_CheckType, /*MI*/0, /*Op*/2, /*Type*/GILLT_s32,
        GIM_CheckRegBankForClass, /*MI*/0, /*Op*/0, /*RC*/GIMT_Encode2(AMDGPU::VGPR_32RegClassID),
        // MIs[0] dpp8
        GIM_CheckIsImm, /*MI*/0, /*Op*/3,
        // (intrinsic_wo_chain:{ *:[i32] } 2580:{ *:[iPTR] }, i32:{ *:[i32] }:$src, (timm:{ *:[i32] }):$dpp8)  =>  (V_MOV_B32_dpp8_gfx12:{ *:[i32] } VGPR_32:{ *:[i32] }:$src, VGPR_32:{ *:[i32] }:$src, (as_i32timm:{ *:[i32] } ?:{ *:[i32] }:$dpp8), 233:{ *:[i32] })
        GIR_BuildMI, /*InsnID*/0, /*Opcode*/GIMT_Encode2(AMDGPU::V_MOV_B32_dpp8_gfx12),
        GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/0, // DstI[vdst]
        GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/2, // src
        GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/2, // src
        GIR_CustomOperandRenderer, /*InsnID*/0, /*OldInsnID*/0, /*OpIdx*/3, /*OperandRenderer*/GIMT_Encode2(GICR_renderTruncTImm), // dpp8
        GIR_AddImm, /*InsnID*/0, /*Imm*/GIMT_Encode8(233),
        GIR_ConstrainSelectedInstOperands, /*InsnID*/0,
        GIR_EraseFromParent, /*InsnID*/0,
        // GIR_Coverage, 2091,
        GIR_Done,
      // Label 3428: @221453
      GIM_Try, /*On fail goto*//*Label 3429*/ GIMT_Encode4(221505), // Rule ID 6566 //
        GIM_CheckIntrinsicID, /*MI*/0, /*Op*/1, GIMT_Encode2(Intrinsic::amdgcn_ds_swizzle),
        GIM_CheckType, /*MI*/0, /*Op*/0, /*Type*/GILLT_s32,
        GIM_CheckType, /*MI*/0, /*Op*/2, /*Type*/GILLT_s32,
        GIM_CheckRegBankForClass, /*MI*/0, /*Op*/0, /*RC*/GIMT_Encode2(AMDGPU::AV_32RegClassID),
        // MIs[0] offset16
        GIM_CheckIsImm, /*MI*/0, /*Op*/3,
        // (intrinsic_wo_chain:{ *:[i32] } 1950:{ *:[iPTR] }, i32:{ *:[i32] }:$src, (timm:{ *:[i32] }):$offset16)  =>  (DS_SWIZZLE_B32:{ *:[i32] } VGPR_32:{ *:[i32] }:$src, (as_i16timm:{ *:[i16] } ?:{ *:[i32] }:$offset16), 0:{ *:[i1] })
        GIR_BuildMI, /*InsnID*/0, /*Opcode*/GIMT_Encode2(AMDGPU::DS_SWIZZLE_B32),
        GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/0, // DstI[vdst]
        GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/2, // src
        GIR_CustomOperandRenderer, /*InsnID*/0, /*OldInsnID*/0, /*OpIdx*/3, /*OperandRenderer*/GIMT_Encode2(GICR_renderTruncTImm), // offset16
        GIR_AddImm8, /*InsnID*/0, /*Imm*/0,
        GIR_ConstrainSelectedInstOperands, /*InsnID*/0,
        GIR_EraseFromParent, /*InsnID*/0,
        // GIR_Coverage, 6566,
        GIR_Done,
      // Label 3429: @221505
      GIM_Try, /*On fail goto*//*Label 3430*/ GIMT_Encode4(221553), // Rule ID 756 //
        GIM_CheckIntrinsicID, /*MI*/0, /*Op*/1, GIMT_Encode2(Intrinsic::amdgcn_readlane),
        GIM_CheckType, /*MI*/0, /*Op*/0, /*Type*/GILLT_s32,
        GIM_CheckType, /*MI*/0, /*Op*/2, /*Type*/GILLT_s32,
        GIM_CheckType, /*MI*/0, /*Op*/3, /*Type*/GILLT_s32,
        GIM_CheckRegBankForClass, /*MI*/0, /*Op*/0, /*RC*/GIMT_Encode2(AMDGPU::SReg_32RegClassID),
        // (intrinsic_wo_chain:{ *:[i32] } 2650:{ *:[iPTR] }, i32:{ *:[i32] }:$src0, i32:{ *:[i32] }:$src1)  =>  (V_READLANE_B32:{ *:[i32] } i32:{ *:[i32] }:$src0, i32:{ *:[i32] }:$src1)
        GIR_BuildMI, /*InsnID*/0, /*Opcode*/GIMT_Encode2(AMDGPU::V_READLANE_B32),
        GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/0, // DstI[vdst]
        GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/2, // src0
        GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/3, // src1
        GIR_ConstrainSelectedInstOperands, /*InsnID*/0,
        GIR_EraseFromParent, /*InsnID*/0,
        // GIR_Coverage, 756,
        GIR_Done,
      // Label 3430: @221553
      GIM_Try, /*On fail goto*//*Label 3431*/ GIMT_Encode4(221604), // Rule ID 1112 //
        GIM_CheckIntrinsicID, /*MI*/0, /*Op*/1, GIMT_Encode2(Intrinsic::amdgcn_set_inactive),
        GIM_CheckType, /*MI*/0, /*Op*/0, /*Type*/GILLT_s32,
        GIM_CheckType, /*MI*/0, /*Op*/2, /*Type*/GILLT_s32,
        GIM_CheckType, /*MI*/0, /*Op*/3, /*Type*/GILLT_s32,
        GIM_CheckRegBankForClass, /*MI*/0, /*Op*/0, /*RC*/GIMT_Encode2(AMDGPU::VGPR_32RegClassID),
        // (intrinsic_wo_chain:{ *:[i32] } 2710:{ *:[iPTR] }, i32:{ *:[i32] }:$src, i32:{ *:[i32] }:$inactive)  =>  (V_SET_INACTIVE_B32:{ *:[i32] }:{ *:[i1] } i32:{ *:[i32] }:$src, i32:{ *:[i32] }:$inactive)
        GIR_BuildMI, /*InsnID*/0, /*Opcode*/GIMT_Encode2(AMDGPU::V_SET_INACTIVE_B32),
        GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/0, // DstI[vdst]
        GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/2, // src
        GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/3, // inactive
        GIR_SetImplicitDefDead, /*InsnID*/0, /*OpIdx for AMDGPU::SCC*/0,
        GIR_ConstrainSelectedInstOperands, /*InsnID*/0,
        GIR_EraseFromParent, /*InsnID*/0,
        // GIR_Coverage, 1112,
        GIR_Done,
      // Label 3431: @221604
      GIM_Try, /*On fail goto*//*Label 3432*/ GIMT_Encode4(221655), // Rule ID 1113 //
        GIM_CheckIntrinsicID, /*MI*/0, /*Op*/1, GIMT_Encode2(Intrinsic::amdgcn_set_inactive),
        GIM_CheckType, /*MI*/0, /*Op*/0, /*Type*/GILLT_s64,
        GIM_CheckType, /*MI*/0, /*Op*/2, /*Type*/GILLT_s64,
        GIM_CheckType, /*MI*/0, /*Op*/3, /*Type*/GILLT_s64,
        GIM_CheckRegBankForClass, /*MI*/0, /*Op*/0, /*RC*/GIMT_Encode2(AMDGPU::VReg_64RegClassID),
        // (intrinsic_wo_chain:{ *:[i64] } 2710:{ *:[iPTR] }, i64:{ *:[i64] }:$src, i64:{ *:[i64] }:$inactive)  =>  (V_SET_INACTIVE_B64:{ *:[i64] }:{ *:[i1] } i64:{ *:[i64] }:$src, i64:{ *:[i64] }:$inactive)
        GIR_BuildMI, /*InsnID*/0, /*Opcode*/GIMT_Encode2(AMDGPU::V_SET_INACTIVE_B64),
        GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/0, // DstI[vdst]
        GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/2, // src
        GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/3, // inactive
        GIR_SetImplicitDefDead, /*InsnID*/0, /*OpIdx for AMDGPU::SCC*/0,
        GIR_ConstrainSelectedInstOperands, /*InsnID*/0,
        GIR_EraseFromParent, /*InsnID*/0,
        // GIR_Coverage, 1113,
        GIR_Done,
      // Label 3432: @221655
      GIM_Try, /*On fail goto*//*Label 3433*/ GIMT_Encode4(221706), // Rule ID 5839 //
        GIM_CheckIntrinsicID, /*MI*/0, /*Op*/1, GIMT_Encode2(Intrinsic::amdgcn_set_inactive_chain_arg),
        GIM_CheckType, /*MI*/0, /*Op*/0, /*Type*/GILLT_s32,
        GIM_CheckType, /*MI*/0, /*Op*/2, /*Type*/GILLT_s32,
        GIM_CheckType, /*MI*/0, /*Op*/3, /*Type*/GILLT_s32,
        GIM_CheckRegBankForClass, /*MI*/0, /*Op*/0, /*RC*/GIMT_Encode2(AMDGPU::VGPR_32RegClassID),
        // (intrinsic_wo_chain:{ *:[i32] } 2711:{ *:[iPTR] }, i32:{ *:[i32] }:$src, i32:{ *:[i32] }:$inactive)  =>  (V_SET_INACTIVE_B32:{ *:[i32] }:{ *:[i1] } VGPR_32:{ *:[i32] }:$src, VGPR_32:{ *:[i32] }:$inactive)
        GIR_BuildMI, /*InsnID*/0, /*Opcode*/GIMT_Encode2(AMDGPU::V_SET_INACTIVE_B32),
        GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/0, // DstI[vdst]
        GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/2, // src
        GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/3, // inactive
        GIR_SetImplicitDefDead, /*InsnID*/0, /*OpIdx for AMDGPU::SCC*/0,
        GIR_ConstrainSelectedInstOperands, /*InsnID*/0,
        GIR_EraseFromParent, /*InsnID*/0,
        // GIR_Coverage, 5839,
        GIR_Done,
      // Label 3433: @221706
      GIM_Try, /*On fail goto*//*Label 3434*/ GIMT_Encode4(221757), // Rule ID 5840 //
        GIM_CheckIntrinsicID, /*MI*/0, /*Op*/1, GIMT_Encode2(Intrinsic::amdgcn_set_inactive_chain_arg),
        GIM_CheckType, /*MI*/0, /*Op*/0, /*Type*/GILLT_s64,
        GIM_CheckType, /*MI*/0, /*Op*/2, /*Type*/GILLT_s64,
        GIM_CheckType, /*MI*/0, /*Op*/3, /*Type*/GILLT_s64,
        GIM_CheckRegBankForClass, /*MI*/0, /*Op*/0, /*RC*/GIMT_Encode2(AMDGPU::VReg_64RegClassID),
        // (intrinsic_wo_chain:{ *:[i64] } 2711:{ *:[iPTR] }, i64:{ *:[i64] }:$src, i64:{ *:[i64] }:$inactive)  =>  (V_SET_INACTIVE_B64:{ *:[i64] }:{ *:[i1] } VReg_64:{ *:[i64] }:$src, VReg_64:{ *:[i64] }:$inactive)
        GIR_BuildMI, /*InsnID*/0, /*Opcode*/GIMT_Encode2(AMDGPU::V_SET_INACTIVE_B64),
        GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/0, // DstI[vdst]
        GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/2, // src
        GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/3, // inactive
        GIR_SetImplicitDefDead, /*InsnID*/0, /*OpIdx for AMDGPU::SCC*/0,
        GIR_ConstrainSelectedInstOperands, /*InsnID*/0,
        GIR_EraseFromParent, /*InsnID*/0,
        // GIR_Coverage, 5840,
        GIR_Done,
      // Label 3434: @221757
      GIM_Try, /*On fail goto*//*Label 3435*/ GIMT_Encode4(221801), // Rule ID 1114 //
        GIM_CheckIntrinsicID, /*MI*/0, /*Op*/1, GIMT_Encode2(Intrinsic::amdgcn_wave_reduce_umin),
        GIM_CheckType, /*MI*/0, /*Op*/0, /*Type*/GILLT_s32,
        GIM_CheckType, /*MI*/0, /*Op*/2, /*Type*/GILLT_s32,
        GIM_CheckRegBankForClass, /*MI*/0, /*Op*/0, /*RC*/GIMT_Encode2(AMDGPU::SGPR_32RegClassID),
        // MIs[0] strategy
        // No operand predicates
        // (intrinsic_wo_chain:{ *:[i32] } 2807:{ *:[iPTR] }, i32:{ *:[i32] }:$src, i32:{ *:[i32] }:$strategy)  =>  (WAVE_REDUCE_UMIN_PSEUDO_U32:{ *:[i32] } i32:{ *:[i32] }:$src, i32:{ *:[i32] }:$strategy)
        GIR_BuildMI, /*InsnID*/0, /*Opcode*/GIMT_Encode2(AMDGPU::WAVE_REDUCE_UMIN_PSEUDO_U32),
        GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/0, // DstI[sdst]
        GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/2, // src
        GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/3, // strategy
        GIR_ConstrainSelectedInstOperands, /*InsnID*/0,
        GIR_EraseFromParent, /*InsnID*/0,
        // GIR_Coverage, 1114,
        GIR_Done,
      // Label 3435: @221801
      GIM_Try, /*On fail goto*//*Label 3436*/ GIMT_Encode4(221845), // Rule ID 1115 //
        GIM_CheckIntrinsicID, /*MI*/0, /*Op*/1, GIMT_Encode2(Intrinsic::amdgcn_wave_reduce_umax),
        GIM_CheckType, /*MI*/0, /*Op*/0, /*Type*/GILLT_s32,
        GIM_CheckType, /*MI*/0, /*Op*/2, /*Type*/GILLT_s32,
        GIM_CheckRegBankForClass, /*MI*/0, /*Op*/0, /*RC*/GIMT_Encode2(AMDGPU::SGPR_32RegClassID),
        // MIs[0] strategy
        // No operand predicates
        // (intrinsic_wo_chain:{ *:[i32] } 2806:{ *:[iPTR] }, i32:{ *:[i32] }:$src, i32:{ *:[i32] }:$strategy)  =>  (WAVE_REDUCE_UMAX_PSEUDO_U32:{ *:[i32] } i32:{ *:[i32] }:$src, i32:{ *:[i32] }:$strategy)
        GIR_BuildMI, /*InsnID*/0, /*Opcode*/GIMT_Encode2(AMDGPU::WAVE_REDUCE_UMAX_PSEUDO_U32),
        GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/0, // DstI[sdst]
        GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/2, // src
        GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/3, // strategy
        GIR_ConstrainSelectedInstOperands, /*InsnID*/0,
        GIR_EraseFromParent, /*InsnID*/0,
        // GIR_Coverage, 1115,
        GIR_Done,
      // Label 3436: @221845
      GIM_Reject,
    // Label 3423: @221846
    GIM_Try, /*On fail goto*//*Label 3437*/ GIMT_Encode4(224303),
      GIM_CheckNumOperands, /*MI*/0, /*Expected*/5,
      GIM_Try, /*On fail goto*//*Label 3438*/ GIMT_Encode4(221956), // Rule ID 2336 //
        GIM_CheckFeatures, GIMT_Encode2(GIFBS_isGFX12Plus_isWave32),
        GIM_CheckIntrinsicID, /*MI*/0, /*Op*/1, GIMT_Encode2(Intrinsic::amdgcn_wmma_f32_16x16x16_f16),
        GIM_CheckType, /*MI*/0, /*Op*/0, /*Type*/GILLT_v8s32,
        GIM_CheckType, /*MI*/0, /*Op*/2, /*Type*/GILLT_v8s16,
        GIM_CheckType, /*MI*/0, /*Op*/3, /*Type*/GILLT_v8s16,
        GIM_CheckType, /*MI*/0, /*Op*/4, /*Type*/GILLT_v8s32,
        GIM_CheckRegBankForClass, /*MI*/0, /*Op*/0, /*RC*/GIMT_Encode2(AMDGPU::VReg_256RegClassID),
        GIM_CheckComplexPattern, /*MI*/0, /*Op*/2, /*Renderer*/GIMT_Encode2(0), GIMT_Encode2(GICP_gi_wmmamodsf16Neg),
        GIM_CheckComplexPattern, /*MI*/0, /*Op*/3, /*Renderer*/GIMT_Encode2(1), GIMT_Encode2(GICP_gi_wmmamodsf16Neg),
        GIM_CheckComplexPattern, /*MI*/0, /*Op*/4, /*Renderer*/GIMT_Encode2(2), GIMT_Encode2(GICP_gi_wmmavisrc),
        // (intrinsic_wo_chain:{ *:[v8f32] } 2816:{ *:[iPTR] }, (WMMAModsF16Neg:{ *:[v8f16] } v8f16:{ *:[v8f16] }:$src0, i32:{ *:[i32] }:$src0_modifiers), (WMMAModsF16Neg:{ *:[v8f16] } v8f16:{ *:[v8f16] }:$src1, i32:{ *:[i32] }:$src1_modifiers), (WMMAVISrc:{ *:[v8f32] } v8f32:{ *:[v8f32] }:$src2))  =>  (V_WMMA_F32_16X16X16_F16_w32_threeaddr:{ *:[v8f32] } i32:{ *:[i32] }:$src0_modifiers, v8f16:{ *:[v8f16] }:$src0, i32:{ *:[i32] }:$src1_modifiers, v8f16:{ *:[v8f16] }:$src1, 8:{ *:[i32] }, v8f32:{ *:[v8f32] }:$src2)
        GIR_BuildMI, /*InsnID*/0, /*Opcode*/GIMT_Encode2(AMDGPU::V_WMMA_F32_16X16X16_F16_w32_threeaddr),
        GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/0, // DstI[vdst]
        GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/1, // src0_modifiers
        GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/0, // src0
        GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(1), /*SubOperand*/1, // src1_modifiers
        GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(1), /*SubOperand*/0, // src1
        GIR_AddImm8, /*InsnID*/0, /*Imm*/8,
        GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(2), /*SubOperand*/0, // src2
        GIR_AddImm8, /*InsnID*/0, /*Imm*/0,
        GIR_AddImm8, /*InsnID*/0, /*Imm*/0,
        GIR_ConstrainSelectedInstOperands, /*InsnID*/0,
        GIR_EraseFromParent, /*InsnID*/0,
        // GIR_Coverage, 2336,
        GIR_Done,
      // Label 3438: @221956
      GIM_Try, /*On fail goto*//*Label 3439*/ GIMT_Encode4(222058), // Rule ID 2369 //
        GIM_CheckFeatures, GIMT_Encode2(GIFBS_isGFX12Plus_isWave64),
        GIM_CheckIntrinsicID, /*MI*/0, /*Op*/1, GIMT_Encode2(Intrinsic::amdgcn_wmma_f32_16x16x16_f16),
        GIM_CheckType, /*MI*/0, /*Op*/0, /*Type*/GILLT_v4s32,
        GIM_CheckType, /*MI*/0, /*Op*/2, /*Type*/GILLT_v4s16,
        GIM_CheckType, /*MI*/0, /*Op*/3, /*Type*/GILLT_v4s16,
        GIM_CheckType, /*MI*/0, /*Op*/4, /*Type*/GILLT_v4s32,
        GIM_CheckRegBankForClass, /*MI*/0, /*Op*/0, /*RC*/GIMT_Encode2(AMDGPU::VReg_128RegClassID),
        GIM_CheckComplexPattern, /*MI*/0, /*Op*/2, /*Renderer*/GIMT_Encode2(0), GIMT_Encode2(GICP_gi_wmmamodsf16Neg),
        GIM_CheckComplexPattern, /*MI*/0, /*Op*/3, /*Renderer*/GIMT_Encode2(1), GIMT_Encode2(GICP_gi_wmmamodsf16Neg),
        GIM_CheckComplexPattern, /*MI*/0, /*Op*/4, /*Renderer*/GIMT_Encode2(2), GIMT_Encode2(GICP_gi_wmmavisrc),
        // (intrinsic_wo_chain:{ *:[v4f32] } 2816:{ *:[iPTR] }, (WMMAModsF16Neg:{ *:[v4f16] } v4f16:{ *:[v4f16] }:$src0, i32:{ *:[i32] }:$src0_modifiers), (WMMAModsF16Neg:{ *:[v4f16] } v4f16:{ *:[v4f16] }:$src1, i32:{ *:[i32] }:$src1_modifiers), (WMMAVISrc:{ *:[v4f32] } v4f32:{ *:[v4f32] }:$src2))  =>  (V_WMMA_F32_16X16X16_F16_w64_threeaddr:{ *:[v4f32] } i32:{ *:[i32] }:$src0_modifiers, v4f16:{ *:[v4f16] }:$src0, i32:{ *:[i32] }:$src1_modifiers, v4f16:{ *:[v4f16] }:$src1, 8:{ *:[i32] }, v4f32:{ *:[v4f32] }:$src2)
        GIR_BuildMI, /*InsnID*/0, /*Opcode*/GIMT_Encode2(AMDGPU::V_WMMA_F32_16X16X16_F16_w64_threeaddr),
        GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/0, // DstI[vdst]
        GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/1, // src0_modifiers
        GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/0, // src0
        GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(1), /*SubOperand*/1, // src1_modifiers
        GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(1), /*SubOperand*/0, // src1
        GIR_AddImm8, /*InsnID*/0, /*Imm*/8,
        GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(2), /*SubOperand*/0, // src2
        GIR_AddImm8, /*InsnID*/0, /*Imm*/0,
        GIR_AddImm8, /*InsnID*/0, /*Imm*/0,
        GIR_ConstrainSelectedInstOperands, /*InsnID*/0,
        GIR_EraseFromParent, /*InsnID*/0,
        // GIR_Coverage, 2369,
        GIR_Done,
      // Label 3439: @222058
      GIM_Try, /*On fail goto*//*Label 3440*/ GIMT_Encode4(222162), // Rule ID 2321 //
        GIM_CheckFeatures, GIMT_Encode2(GIFBS_isGFX11Only_isWave32),
        GIM_CheckIntrinsicID, /*MI*/0, /*Op*/1, GIMT_Encode2(Intrinsic::amdgcn_wmma_f32_16x16x16_f16),
        GIM_CheckType, /*MI*/0, /*Op*/0, /*Type*/GILLT_v8s32,
        GIM_CheckType, /*MI*/0, /*Op*/2, /*Type*/GILLT_v16s16,
        GIM_CheckType, /*MI*/0, /*Op*/3, /*Type*/GILLT_v16s16,
        GIM_CheckType, /*MI*/0, /*Op*/4, /*Type*/GILLT_v8s32,
        GIM_CheckRegBankForClass, /*MI*/0, /*Op*/0, /*RC*/GIMT_Encode2(AMDGPU::VReg_256RegClassID),
        GIM_CheckComplexPattern, /*MI*/0, /*Op*/2, /*Renderer*/GIMT_Encode2(0), GIMT_Encode2(GICP_gi_vop3pmods),
        GIM_CheckComplexPattern, /*MI*/0, /*Op*/3, /*Renderer*/GIMT_Encode2(1), GIMT_Encode2(GICP_gi_vop3pmods),
        GIM_CheckComplexPattern, /*MI*/0, /*Op*/4, /*Renderer*/GIMT_Encode2(2), GIMT_Encode2(GICP_gi_vop3pmods),
        // (intrinsic_wo_chain:{ *:[v8f32] } 2816:{ *:[iPTR] }, (VOP3PMods:{ *:[v16f16] } v16f16:{ *:[v16f16] }:$src0, i32:{ *:[i32] }:$src0_modifiers), (VOP3PMods:{ *:[v16f16] } v16f16:{ *:[v16f16] }:$src1, i32:{ *:[i32] }:$src1_modifiers), (VOP3PMods:{ *:[v8f32] } v8f32:{ *:[v8f32] }:$src2, i32:{ *:[i32] }:$src2_modifiers))  =>  (V_WMMA_F32_16X16X16_F16_twoaddr_w32:{ *:[v8f32] } i32:{ *:[i32] }:$src0_modifiers, v16f16:{ *:[v16f16] }:$src0, i32:{ *:[i32] }:$src1_modifiers, v16f16:{ *:[v16f16] }:$src1, ?:{ *:[i32] }:$src2_modifiers, v8f32:{ *:[v8f32] }:$src2)
        GIR_BuildMI, /*InsnID*/0, /*Opcode*/GIMT_Encode2(AMDGPU::V_WMMA_F32_16X16X16_F16_twoaddr_w32),
        GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/0, // DstI[vdst]
        GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/1, // src0_modifiers
        GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/0, // src0
        GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(1), /*SubOperand*/1, // src1_modifiers
        GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(1), /*SubOperand*/0, // src1
        GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(2), /*SubOperand*/1, // src2_modifiers
        GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(2), /*SubOperand*/0, // src2
        GIR_AddImm8, /*InsnID*/0, /*Imm*/0,
        GIR_AddImm8, /*InsnID*/0, /*Imm*/0,
        GIR_ConstrainSelectedInstOperands, /*InsnID*/0,
        GIR_EraseFromParent, /*InsnID*/0,
        // GIR_Coverage, 2321,
        GIR_Done,
      // Label 3440: @222162
      GIM_Try, /*On fail goto*//*Label 3441*/ GIMT_Encode4(222266), // Rule ID 2322 //
        GIM_CheckFeatures, GIMT_Encode2(GIFBS_isGFX11Only_isWave32),
        GIM_CheckIntrinsicID, /*MI*/0, /*Op*/1, GIMT_Encode2(Intrinsic::amdgcn_wmma_f32_16x16x16_bf16),
        GIM_CheckType, /*MI*/0, /*Op*/0, /*Type*/GILLT_v8s32,
        GIM_CheckType, /*MI*/0, /*Op*/2, /*Type*/GILLT_v16s16,
        GIM_CheckType, /*MI*/0, /*Op*/3, /*Type*/GILLT_v16s16,
        GIM_CheckType, /*MI*/0, /*Op*/4, /*Type*/GILLT_v8s32,
        GIM_CheckRegBankForClass, /*MI*/0, /*Op*/0, /*RC*/GIMT_Encode2(AMDGPU::VReg_256RegClassID),
        GIM_CheckComplexPattern, /*MI*/0, /*Op*/2, /*Renderer*/GIMT_Encode2(0), GIMT_Encode2(GICP_gi_vop3pmods),
        GIM_CheckComplexPattern, /*MI*/0, /*Op*/3, /*Renderer*/GIMT_Encode2(1), GIMT_Encode2(GICP_gi_vop3pmods),
        GIM_CheckComplexPattern, /*MI*/0, /*Op*/4, /*Renderer*/GIMT_Encode2(2), GIMT_Encode2(GICP_gi_vop3pmods),
        // (intrinsic_wo_chain:{ *:[v8f32] } 2813:{ *:[iPTR] }, (VOP3PMods:{ *:[v16i16] } v16i16:{ *:[v16i16] }:$src0, i32:{ *:[i32] }:$src0_modifiers), (VOP3PMods:{ *:[v16i16] } v16i16:{ *:[v16i16] }:$src1, i32:{ *:[i32] }:$src1_modifiers), (VOP3PMods:{ *:[v8f32] } v8f32:{ *:[v8f32] }:$src2, i32:{ *:[i32] }:$src2_modifiers))  =>  (V_WMMA_F32_16X16X16_BF16_twoaddr_w32:{ *:[v8f32] } i32:{ *:[i32] }:$src0_modifiers, v16i16:{ *:[v16i16] }:$src0, i32:{ *:[i32] }:$src1_modifiers, v16i16:{ *:[v16i16] }:$src1, ?:{ *:[i32] }:$src2_modifiers, v8f32:{ *:[v8f32] }:$src2)
        GIR_BuildMI, /*InsnID*/0, /*Opcode*/GIMT_Encode2(AMDGPU::V_WMMA_F32_16X16X16_BF16_twoaddr_w32),
        GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/0, // DstI[vdst]
        GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/1, // src0_modifiers
        GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/0, // src0
        GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(1), /*SubOperand*/1, // src1_modifiers
        GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(1), /*SubOperand*/0, // src1
        GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(2), /*SubOperand*/1, // src2_modifiers
        GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(2), /*SubOperand*/0, // src2
        GIR_AddImm8, /*InsnID*/0, /*Imm*/0,
        GIR_AddImm8, /*InsnID*/0, /*Imm*/0,
        GIR_ConstrainSelectedInstOperands, /*InsnID*/0,
        GIR_EraseFromParent, /*InsnID*/0,
        // GIR_Coverage, 2322,
        GIR_Done,
      // Label 3441: @222266
      GIM_Try, /*On fail goto*//*Label 3442*/ GIMT_Encode4(222370), // Rule ID 2327 //
        GIM_CheckFeatures, GIMT_Encode2(GIFBS_isGFX11Only_isWave64),
        GIM_CheckIntrinsicID, /*MI*/0, /*Op*/1, GIMT_Encode2(Intrinsic::amdgcn_wmma_f32_16x16x16_f16),
        GIM_CheckType, /*MI*/0, /*Op*/0, /*Type*/GILLT_v4s32,
        GIM_CheckType, /*MI*/0, /*Op*/2, /*Type*/GILLT_v16s16,
        GIM_CheckType, /*MI*/0, /*Op*/3, /*Type*/GILLT_v16s16,
        GIM_CheckType, /*MI*/0, /*Op*/4, /*Type*/GILLT_v4s32,
        GIM_CheckRegBankForClass, /*MI*/0, /*Op*/0, /*RC*/GIMT_Encode2(AMDGPU::VReg_128RegClassID),
        GIM_CheckComplexPattern, /*MI*/0, /*Op*/2, /*Renderer*/GIMT_Encode2(0), GIMT_Encode2(GICP_gi_vop3pmods),
        GIM_CheckComplexPattern, /*MI*/0, /*Op*/3, /*Renderer*/GIMT_Encode2(1), GIMT_Encode2(GICP_gi_vop3pmods),
        GIM_CheckComplexPattern, /*MI*/0, /*Op*/4, /*Renderer*/GIMT_Encode2(2), GIMT_Encode2(GICP_gi_vop3pmods),
        // (intrinsic_wo_chain:{ *:[v4f32] } 2816:{ *:[iPTR] }, (VOP3PMods:{ *:[v16f16] } v16f16:{ *:[v16f16] }:$src0, i32:{ *:[i32] }:$src0_modifiers), (VOP3PMods:{ *:[v16f16] } v16f16:{ *:[v16f16] }:$src1, i32:{ *:[i32] }:$src1_modifiers), (VOP3PMods:{ *:[v4f32] } v4f32:{ *:[v4f32] }:$src2, i32:{ *:[i32] }:$src2_modifiers))  =>  (V_WMMA_F32_16X16X16_F16_twoaddr_w64:{ *:[v4f32] } i32:{ *:[i32] }:$src0_modifiers, v16f16:{ *:[v16f16] }:$src0, i32:{ *:[i32] }:$src1_modifiers, v16f16:{ *:[v16f16] }:$src1, ?:{ *:[i32] }:$src2_modifiers, v4f32:{ *:[v4f32] }:$src2)
        GIR_BuildMI, /*InsnID*/0, /*Opcode*/GIMT_Encode2(AMDGPU::V_WMMA_F32_16X16X16_F16_twoaddr_w64),
        GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/0, // DstI[vdst]
        GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/1, // src0_modifiers
        GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/0, // src0
        GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(1), /*SubOperand*/1, // src1_modifiers
        GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(1), /*SubOperand*/0, // src1
        GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(2), /*SubOperand*/1, // src2_modifiers
        GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(2), /*SubOperand*/0, // src2
        GIR_AddImm8, /*InsnID*/0, /*Imm*/0,
        GIR_AddImm8, /*InsnID*/0, /*Imm*/0,
        GIR_ConstrainSelectedInstOperands, /*InsnID*/0,
        GIR_EraseFromParent, /*InsnID*/0,
        // GIR_Coverage, 2327,
        GIR_Done,
      // Label 3442: @222370
      GIM_Try, /*On fail goto*//*Label 3443*/ GIMT_Encode4(222474), // Rule ID 2328 //
        GIM_CheckFeatures, GIMT_Encode2(GIFBS_isGFX11Only_isWave64),
        GIM_CheckIntrinsicID, /*MI*/0, /*Op*/1, GIMT_Encode2(Intrinsic::amdgcn_wmma_f32_16x16x16_bf16),
        GIM_CheckType, /*MI*/0, /*Op*/0, /*Type*/GILLT_v4s32,
        GIM_CheckType, /*MI*/0, /*Op*/2, /*Type*/GILLT_v16s16,
        GIM_CheckType, /*MI*/0, /*Op*/3, /*Type*/GILLT_v16s16,
        GIM_CheckType, /*MI*/0, /*Op*/4, /*Type*/GILLT_v4s32,
        GIM_CheckRegBankForClass, /*MI*/0, /*Op*/0, /*RC*/GIMT_Encode2(AMDGPU::VReg_128RegClassID),
        GIM_CheckComplexPattern, /*MI*/0, /*Op*/2, /*Renderer*/GIMT_Encode2(0), GIMT_Encode2(GICP_gi_vop3pmods),
        GIM_CheckComplexPattern, /*MI*/0, /*Op*/3, /*Renderer*/GIMT_Encode2(1), GIMT_Encode2(GICP_gi_vop3pmods),
        GIM_CheckComplexPattern, /*MI*/0, /*Op*/4, /*Renderer*/GIMT_Encode2(2), GIMT_Encode2(GICP_gi_vop3pmods),
        // (intrinsic_wo_chain:{ *:[v4f32] } 2813:{ *:[iPTR] }, (VOP3PMods:{ *:[v16i16] } v16i16:{ *:[v16i16] }:$src0, i32:{ *:[i32] }:$src0_modifiers), (VOP3PMods:{ *:[v16i16] } v16i16:{ *:[v16i16] }:$src1, i32:{ *:[i32] }:$src1_modifiers), (VOP3PMods:{ *:[v4f32] } v4f32:{ *:[v4f32] }:$src2, i32:{ *:[i32] }:$src2_modifiers))  =>  (V_WMMA_F32_16X16X16_BF16_twoaddr_w64:{ *:[v4f32] } i32:{ *:[i32] }:$src0_modifiers, v16i16:{ *:[v16i16] }:$src0, i32:{ *:[i32] }:$src1_modifiers, v16i16:{ *:[v16i16] }:$src1, ?:{ *:[i32] }:$src2_modifiers, v4f32:{ *:[v4f32] }:$src2)
        GIR_BuildMI, /*InsnID*/0, /*Opcode*/GIMT_Encode2(AMDGPU::V_WMMA_F32_16X16X16_BF16_twoaddr_w64),
        GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/0, // DstI[vdst]
        GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/1, // src0_modifiers
        GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/0, // src0
        GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(1), /*SubOperand*/1, // src1_modifiers
        GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(1), /*SubOperand*/0, // src1
        GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(2), /*SubOperand*/1, // src2_modifiers
        GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(2), /*SubOperand*/0, // src2
        GIR_AddImm8, /*InsnID*/0, /*Imm*/0,
        GIR_AddImm8, /*InsnID*/0, /*Imm*/0,
        GIR_ConstrainSelectedInstOperands, /*InsnID*/0,
        GIR_EraseFromParent, /*InsnID*/0,
        // GIR_Coverage, 2328,
        GIR_Done,
      // Label 3443: @222474
      GIM_Try, /*On fail goto*//*Label 3444*/ GIMT_Encode4(222578), // Rule ID 2335 //
        GIM_CheckFeatures, GIMT_Encode2(GIFBS_isGFX12Plus_isWave32),
        GIM_CheckIntrinsicID, /*MI*/0, /*Op*/1, GIMT_Encode2(Intrinsic::amdgcn_wmma_f32_16x16x16_f16),
        GIM_CheckType, /*MI*/0, /*Op*/0, /*Type*/GILLT_v8s32,
        GIM_CheckType, /*MI*/0, /*Op*/2, /*Type*/GILLT_v8s16,
        GIM_CheckType, /*MI*/0, /*Op*/3, /*Type*/GILLT_v8s16,
        GIM_CheckType, /*MI*/0, /*Op*/4, /*Type*/GILLT_v8s32,
        GIM_CheckRegBankForClass, /*MI*/0, /*Op*/0, /*RC*/GIMT_Encode2(AMDGPU::VReg_256RegClassID),
        GIM_CheckComplexPattern, /*MI*/0, /*Op*/2, /*Renderer*/GIMT_Encode2(0), GIMT_Encode2(GICP_gi_wmmamodsf16Neg),
        GIM_CheckComplexPattern, /*MI*/0, /*Op*/3, /*Renderer*/GIMT_Encode2(1), GIMT_Encode2(GICP_gi_wmmamodsf16Neg),
        GIM_CheckComplexPattern, /*MI*/0, /*Op*/4, /*Renderer*/GIMT_Encode2(2), GIMT_Encode2(GICP_gi_wmmamods),
        // (intrinsic_wo_chain:{ *:[v8f32] } 2816:{ *:[iPTR] }, (WMMAModsF16Neg:{ *:[v8f16] } v8f16:{ *:[v8f16] }:$src0, i32:{ *:[i32] }:$src0_modifiers), (WMMAModsF16Neg:{ *:[v8f16] } v8f16:{ *:[v8f16] }:$src1, i32:{ *:[i32] }:$src1_modifiers), (WMMAModsF32NegAbs:{ *:[v8f32] } v8f32:{ *:[v8f32] }:$src2, i32:{ *:[i32] }:$src2_modifiers))  =>  (V_WMMA_F32_16X16X16_F16_w32_twoaddr:{ *:[v8f32] } i32:{ *:[i32] }:$src0_modifiers, v8f16:{ *:[v8f16] }:$src0, i32:{ *:[i32] }:$src1_modifiers, v8f16:{ *:[v8f16] }:$src1, i32:{ *:[i32] }:$src2_modifiers, v8f32:{ *:[v8f32] }:$src2)
        GIR_BuildMI, /*InsnID*/0, /*Opcode*/GIMT_Encode2(AMDGPU::V_WMMA_F32_16X16X16_F16_w32_twoaddr),
        GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/0, // DstI[vdst]
        GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/1, // src0_modifiers
        GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/0, // src0
        GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(1), /*SubOperand*/1, // src1_modifiers
        GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(1), /*SubOperand*/0, // src1
        GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(2), /*SubOperand*/1, // src2_modifiers
        GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(2), /*SubOperand*/0, // src2
        GIR_AddImm8, /*InsnID*/0, /*Imm*/0,
        GIR_AddImm8, /*InsnID*/0, /*Imm*/0,
        GIR_ConstrainSelectedInstOperands, /*InsnID*/0,
        GIR_EraseFromParent, /*InsnID*/0,
        // GIR_Coverage, 2335,
        GIR_Done,
      // Label 3444: @222578
      GIM_Try, /*On fail goto*//*Label 3445*/ GIMT_Encode4(222682), // Rule ID 2368 //
        GIM_CheckFeatures, GIMT_Encode2(GIFBS_isGFX12Plus_isWave64),
        GIM_CheckIntrinsicID, /*MI*/0, /*Op*/1, GIMT_Encode2(Intrinsic::amdgcn_wmma_f32_16x16x16_f16),
        GIM_CheckType, /*MI*/0, /*Op*/0, /*Type*/GILLT_v4s32,
        GIM_CheckType, /*MI*/0, /*Op*/2, /*Type*/GILLT_v4s16,
        GIM_CheckType, /*MI*/0, /*Op*/3, /*Type*/GILLT_v4s16,
        GIM_CheckType, /*MI*/0, /*Op*/4, /*Type*/GILLT_v4s32,
        GIM_CheckRegBankForClass, /*MI*/0, /*Op*/0, /*RC*/GIMT_Encode2(AMDGPU::VReg_128RegClassID),
        GIM_CheckComplexPattern, /*MI*/0, /*Op*/2, /*Renderer*/GIMT_Encode2(0), GIMT_Encode2(GICP_gi_wmmamodsf16Neg),
        GIM_CheckComplexPattern, /*MI*/0, /*Op*/3, /*Renderer*/GIMT_Encode2(1), GIMT_Encode2(GICP_gi_wmmamodsf16Neg),
        GIM_CheckComplexPattern, /*MI*/0, /*Op*/4, /*Renderer*/GIMT_Encode2(2), GIMT_Encode2(GICP_gi_wmmamods),
        // (intrinsic_wo_chain:{ *:[v4f32] } 2816:{ *:[iPTR] }, (WMMAModsF16Neg:{ *:[v4f16] } v4f16:{ *:[v4f16] }:$src0, i32:{ *:[i32] }:$src0_modifiers), (WMMAModsF16Neg:{ *:[v4f16] } v4f16:{ *:[v4f16] }:$src1, i32:{ *:[i32] }:$src1_modifiers), (WMMAModsF32NegAbs:{ *:[v4f32] } v4f32:{ *:[v4f32] }:$src2, i32:{ *:[i32] }:$src2_modifiers))  =>  (V_WMMA_F32_16X16X16_F16_w64_twoaddr:{ *:[v4f32] } i32:{ *:[i32] }:$src0_modifiers, v4f16:{ *:[v4f16] }:$src0, i32:{ *:[i32] }:$src1_modifiers, v4f16:{ *:[v4f16] }:$src1, i32:{ *:[i32] }:$src2_modifiers, v4f32:{ *:[v4f32] }:$src2)
        GIR_BuildMI, /*InsnID*/0, /*Opcode*/GIMT_Encode2(AMDGPU::V_WMMA_F32_16X16X16_F16_w64_twoaddr),
        GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/0, // DstI[vdst]
        GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/1, // src0_modifiers
        GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/0, // src0
        GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(1), /*SubOperand*/1, // src1_modifiers
        GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(1), /*SubOperand*/0, // src1
        GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(2), /*SubOperand*/1, // src2_modifiers
        GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(2), /*SubOperand*/0, // src2
        GIR_AddImm8, /*InsnID*/0, /*Imm*/0,
        GIR_AddImm8, /*InsnID*/0, /*Imm*/0,
        GIR_ConstrainSelectedInstOperands, /*InsnID*/0,
        GIR_EraseFromParent, /*InsnID*/0,
        // GIR_Coverage, 2368,
        GIR_Done,
      // Label 3445: @222682
      GIM_Try, /*On fail goto*//*Label 3446*/ GIMT_Encode4(222764), // Rule ID 2338 //
        GIM_CheckFeatures, GIMT_Encode2(GIFBS_isGFX12Plus_isWave32),
        GIM_CheckIntrinsicID, /*MI*/0, /*Op*/1, GIMT_Encode2(Intrinsic::amdgcn_wmma_f32_16x16x16_bf16),
        GIM_CheckType, /*MI*/0, /*Op*/0, /*Type*/GILLT_v8s32,
        GIM_CheckType, /*MI*/0, /*Op*/2, /*Type*/GILLT_v8s16,
        GIM_CheckType, /*MI*/0, /*Op*/3, /*Type*/GILLT_v8s16,
        GIM_CheckType, /*MI*/0, /*Op*/4, /*Type*/GILLT_v8s32,
        GIM_CheckRegBankForClass, /*MI*/0, /*Op*/0, /*RC*/GIMT_Encode2(AMDGPU::VReg_256RegClassID),
        GIM_CheckComplexPattern, /*MI*/0, /*Op*/4, /*Renderer*/GIMT_Encode2(0), GIMT_Encode2(GICP_gi_wmmavisrc),
        // (intrinsic_wo_chain:{ *:[v8f32] } 2813:{ *:[iPTR] }, v8i16:{ *:[v8i16] }:$src0, v8i16:{ *:[v8i16] }:$src1, (WMMAVISrc:{ *:[v8f32] } v8f32:{ *:[v8f32] }:$src2))  =>  (V_WMMA_F32_16X16X16_BF16_w32_threeaddr:{ *:[v8f32] } 8:{ *:[i32] }, v8i16:{ *:[v8i16] }:$src0, 8:{ *:[i32] }, v8i16:{ *:[v8i16] }:$src1, 8:{ *:[i32] }, v8f32:{ *:[v8f32] }:$src2)
        GIR_BuildMI, /*InsnID*/0, /*Opcode*/GIMT_Encode2(AMDGPU::V_WMMA_F32_16X16X16_BF16_w32_threeaddr),
        GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/0, // DstI[vdst]
        GIR_AddImm8, /*InsnID*/0, /*Imm*/8,
        GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/2, // src0
        GIR_AddImm8, /*InsnID*/0, /*Imm*/8,
        GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/3, // src1
        GIR_AddImm8, /*InsnID*/0, /*Imm*/8,
        GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/0, // src2
        GIR_AddImm8, /*InsnID*/0, /*Imm*/0,
        GIR_AddImm8, /*InsnID*/0, /*Imm*/0,
        GIR_ConstrainSelectedInstOperands, /*InsnID*/0,
        GIR_EraseFromParent, /*InsnID*/0,
        // GIR_Coverage, 2338,
        GIR_Done,
      // Label 3446: @222764
      GIM_Try, /*On fail goto*//*Label 3447*/ GIMT_Encode4(222840), // Rule ID 2348 //
        GIM_CheckFeatures, GIMT_Encode2(GIFBS_isGFX12Plus_isWave32),
        GIM_CheckIntrinsicID, /*MI*/0, /*Op*/1, GIMT_Encode2(Intrinsic::amdgcn_wmma_f32_16x16x16_fp8_fp8),
        GIM_CheckType, /*MI*/0, /*Op*/0, /*Type*/GILLT_v8s32,
        GIM_CheckType, /*MI*/0, /*Op*/2, /*Type*/GILLT_v2s32,
        GIM_CheckType, /*MI*/0, /*Op*/3, /*Type*/GILLT_v2s32,
        GIM_CheckType, /*MI*/0, /*Op*/4, /*Type*/GILLT_v8s32,
        GIM_CheckRegBankForClass, /*MI*/0, /*Op*/0, /*RC*/GIMT_Encode2(AMDGPU::VReg_256RegClassID),
        GIM_CheckComplexPattern, /*MI*/0, /*Op*/4, /*Renderer*/GIMT_Encode2(0), GIMT_Encode2(GICP_gi_wmmavisrc),
        // (intrinsic_wo_chain:{ *:[v8f32] } 2818:{ *:[iPTR] }, v2i32:{ *:[v2i32] }:$src0, v2i32:{ *:[v2i32] }:$src1, (WMMAVISrc:{ *:[v8f32] } v8f32:{ *:[v8f32] }:$src2))  =>  (V_WMMA_F32_16X16X16_FP8_FP8_w32_threeaddr:{ *:[v8f32] } v2i32:{ *:[v2i32] }:$src0, v2i32:{ *:[v2i32] }:$src1, 8:{ *:[i32] }, v8f32:{ *:[v8f32] }:$src2)
        GIR_BuildMI, /*InsnID*/0, /*Opcode*/GIMT_Encode2(AMDGPU::V_WMMA_F32_16X16X16_FP8_FP8_w32_threeaddr),
        GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/0, // DstI[vdst]
        GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/2, // src0
        GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/3, // src1
        GIR_AddImm8, /*InsnID*/0, /*Imm*/8,
        GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/0, // src2
        GIR_AddImm8, /*InsnID*/0, /*Imm*/0,
        GIR_AddImm8, /*InsnID*/0, /*Imm*/0,
        GIR_ConstrainSelectedInstOperands, /*InsnID*/0,
        GIR_EraseFromParent, /*InsnID*/0,
        // GIR_Coverage, 2348,
        GIR_Done,
      // Label 3447: @222840
      GIM_Try, /*On fail goto*//*Label 3448*/ GIMT_Encode4(222916), // Rule ID 2350 //
        GIM_CheckFeatures, GIMT_Encode2(GIFBS_isGFX12Plus_isWave32),
        GIM_CheckIntrinsicID, /*MI*/0, /*Op*/1, GIMT_Encode2(Intrinsic::amdgcn_wmma_f32_16x16x16_fp8_bf8),
        GIM_CheckType, /*MI*/0, /*Op*/0, /*Type*/GILLT_v8s32,
        GIM_CheckType, /*MI*/0, /*Op*/2, /*Type*/GILLT_v2s32,
        GIM_CheckType, /*MI*/0, /*Op*/3, /*Type*/GILLT_v2s32,
        GIM_CheckType, /*MI*/0, /*Op*/4, /*Type*/GILLT_v8s32,
        GIM_CheckRegBankForClass, /*MI*/0, /*Op*/0, /*RC*/GIMT_Encode2(AMDGPU::VReg_256RegClassID),
        GIM_CheckComplexPattern, /*MI*/0, /*Op*/4, /*Renderer*/GIMT_Encode2(0), GIMT_Encode2(GICP_gi_wmmavisrc),
        // (intrinsic_wo_chain:{ *:[v8f32] } 2817:{ *:[iPTR] }, v2i32:{ *:[v2i32] }:$src0, v2i32:{ *:[v2i32] }:$src1, (WMMAVISrc:{ *:[v8f32] } v8f32:{ *:[v8f32] }:$src2))  =>  (V_WMMA_F32_16X16X16_FP8_BF8_w32_threeaddr:{ *:[v8f32] } v2i32:{ *:[v2i32] }:$src0, v2i32:{ *:[v2i32] }:$src1, 8:{ *:[i32] }, v8f32:{ *:[v8f32] }:$src2)
        GIR_BuildMI, /*InsnID*/0, /*Opcode*/GIMT_Encode2(AMDGPU::V_WMMA_F32_16X16X16_FP8_BF8_w32_threeaddr),
        GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/0, // DstI[vdst]
        GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/2, // src0
        GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/3, // src1
        GIR_AddImm8, /*InsnID*/0, /*Imm*/8,
        GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/0, // src2
        GIR_AddImm8, /*InsnID*/0, /*Imm*/0,
        GIR_AddImm8, /*InsnID*/0, /*Imm*/0,
        GIR_ConstrainSelectedInstOperands, /*InsnID*/0,
        GIR_EraseFromParent, /*InsnID*/0,
        // GIR_Coverage, 2350,
        GIR_Done,
      // Label 3448: @222916
      GIM_Try, /*On fail goto*//*Label 3449*/ GIMT_Encode4(222992), // Rule ID 2352 //
        GIM_CheckFeatures, GIMT_Encode2(GIFBS_isGFX12Plus_isWave32),
        GIM_CheckIntrinsicID, /*MI*/0, /*Op*/1, GIMT_Encode2(Intrinsic::amdgcn_wmma_f32_16x16x16_bf8_fp8),
        GIM_CheckType, /*MI*/0, /*Op*/0, /*Type*/GILLT_v8s32,
        GIM_CheckType, /*MI*/0, /*Op*/2, /*Type*/GILLT_v2s32,
        GIM_CheckType, /*MI*/0, /*Op*/3, /*Type*/GILLT_v2s32,
        GIM_CheckType, /*MI*/0, /*Op*/4, /*Type*/GILLT_v8s32,
        GIM_CheckRegBankForClass, /*MI*/0, /*Op*/0, /*RC*/GIMT_Encode2(AMDGPU::VReg_256RegClassID),
        GIM_CheckComplexPattern, /*MI*/0, /*Op*/4, /*Renderer*/GIMT_Encode2(0), GIMT_Encode2(GICP_gi_wmmavisrc),
        // (intrinsic_wo_chain:{ *:[v8f32] } 2815:{ *:[iPTR] }, v2i32:{ *:[v2i32] }:$src0, v2i32:{ *:[v2i32] }:$src1, (WMMAVISrc:{ *:[v8f32] } v8f32:{ *:[v8f32] }:$src2))  =>  (V_WMMA_F32_16X16X16_BF8_FP8_w32_threeaddr:{ *:[v8f32] } v2i32:{ *:[v2i32] }:$src0, v2i32:{ *:[v2i32] }:$src1, 8:{ *:[i32] }, v8f32:{ *:[v8f32] }:$src2)
        GIR_BuildMI, /*InsnID*/0, /*Opcode*/GIMT_Encode2(AMDGPU::V_WMMA_F32_16X16X16_BF8_FP8_w32_threeaddr),
        GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/0, // DstI[vdst]
        GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/2, // src0
        GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/3, // src1
        GIR_AddImm8, /*InsnID*/0, /*Imm*/8,
        GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/0, // src2
        GIR_AddImm8, /*InsnID*/0, /*Imm*/0,
        GIR_AddImm8, /*InsnID*/0, /*Imm*/0,
        GIR_ConstrainSelectedInstOperands, /*InsnID*/0,
        GIR_EraseFromParent, /*InsnID*/0,
        // GIR_Coverage, 2352,
        GIR_Done,
      // Label 3449: @222992
      GIM_Try, /*On fail goto*//*Label 3450*/ GIMT_Encode4(223068), // Rule ID 2354 //
        GIM_CheckFeatures, GIMT_Encode2(GIFBS_isGFX12Plus_isWave32),
        GIM_CheckIntrinsicID, /*MI*/0, /*Op*/1, GIMT_Encode2(Intrinsic::amdgcn_wmma_f32_16x16x16_bf8_bf8),
        GIM_CheckType, /*MI*/0, /*Op*/0, /*Type*/GILLT_v8s32,
        GIM_CheckType, /*MI*/0, /*Op*/2, /*Type*/GILLT_v2s32,
        GIM_CheckType, /*MI*/0, /*Op*/3, /*Type*/GILLT_v2s32,
        GIM_CheckType, /*MI*/0, /*Op*/4, /*Type*/GILLT_v8s32,
        GIM_CheckRegBankForClass, /*MI*/0, /*Op*/0, /*RC*/GIMT_Encode2(AMDGPU::VReg_256RegClassID),
        GIM_CheckComplexPattern, /*MI*/0, /*Op*/4, /*Renderer*/GIMT_Encode2(0), GIMT_Encode2(GICP_gi_wmmavisrc),
        // (intrinsic_wo_chain:{ *:[v8f32] } 2814:{ *:[iPTR] }, v2i32:{ *:[v2i32] }:$src0, v2i32:{ *:[v2i32] }:$src1, (WMMAVISrc:{ *:[v8f32] } v8f32:{ *:[v8f32] }:$src2))  =>  (V_WMMA_F32_16X16X16_BF8_BF8_w32_threeaddr:{ *:[v8f32] } v2i32:{ *:[v2i32] }:$src0, v2i32:{ *:[v2i32] }:$src1, 8:{ *:[i32] }, v8f32:{ *:[v8f32] }:$src2)
        GIR_BuildMI, /*InsnID*/0, /*Opcode*/GIMT_Encode2(AMDGPU::V_WMMA_F32_16X16X16_BF8_BF8_w32_threeaddr),
        GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/0, // DstI[vdst]
        GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/2, // src0
        GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/3, // src1
        GIR_AddImm8, /*InsnID*/0, /*Imm*/8,
        GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/0, // src2
        GIR_AddImm8, /*InsnID*/0, /*Imm*/0,
        GIR_AddImm8, /*InsnID*/0, /*Imm*/0,
        GIR_ConstrainSelectedInstOperands, /*InsnID*/0,
        GIR_EraseFromParent, /*InsnID*/0,
        // GIR_Coverage, 2354,
        GIR_Done,
      // Label 3450: @223068
      GIM_Try, /*On fail goto*//*Label 3451*/ GIMT_Encode4(223150), // Rule ID 2371 //
        GIM_CheckFeatures, GIMT_Encode2(GIFBS_isGFX12Plus_isWave64),
        GIM_CheckIntrinsicID, /*MI*/0, /*Op*/1, GIMT_Encode2(Intrinsic::amdgcn_wmma_f32_16x16x16_bf16),
        GIM_CheckType, /*MI*/0, /*Op*/0, /*Type*/GILLT_v4s32,
        GIM_CheckType, /*MI*/0, /*Op*/2, /*Type*/GILLT_v4s16,
        GIM_CheckType, /*MI*/0, /*Op*/3, /*Type*/GILLT_v4s16,
        GIM_CheckType, /*MI*/0, /*Op*/4, /*Type*/GILLT_v4s32,
        GIM_CheckRegBankForClass, /*MI*/0, /*Op*/0, /*RC*/GIMT_Encode2(AMDGPU::VReg_128RegClassID),
        GIM_CheckComplexPattern, /*MI*/0, /*Op*/4, /*Renderer*/GIMT_Encode2(0), GIMT_Encode2(GICP_gi_wmmavisrc),
        // (intrinsic_wo_chain:{ *:[v4f32] } 2813:{ *:[iPTR] }, v4i16:{ *:[v4i16] }:$src0, v4i16:{ *:[v4i16] }:$src1, (WMMAVISrc:{ *:[v4f32] } v4f32:{ *:[v4f32] }:$src2))  =>  (V_WMMA_F32_16X16X16_BF16_w64_threeaddr:{ *:[v4f32] } 8:{ *:[i32] }, v4i16:{ *:[v4i16] }:$src0, 8:{ *:[i32] }, v4i16:{ *:[v4i16] }:$src1, 8:{ *:[i32] }, v4f32:{ *:[v4f32] }:$src2)
        GIR_BuildMI, /*InsnID*/0, /*Opcode*/GIMT_Encode2(AMDGPU::V_WMMA_F32_16X16X16_BF16_w64_threeaddr),
        GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/0, // DstI[vdst]
        GIR_AddImm8, /*InsnID*/0, /*Imm*/8,
        GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/2, // src0
        GIR_AddImm8, /*InsnID*/0, /*Imm*/8,
        GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/3, // src1
        GIR_AddImm8, /*InsnID*/0, /*Imm*/8,
        GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/0, // src2
        GIR_AddImm8, /*InsnID*/0, /*Imm*/0,
        GIR_AddImm8, /*InsnID*/0, /*Imm*/0,
        GIR_ConstrainSelectedInstOperands, /*InsnID*/0,
        GIR_EraseFromParent, /*InsnID*/0,
        // GIR_Coverage, 2371,
        GIR_Done,
      // Label 3451: @223150
      GIM_Try, /*On fail goto*//*Label 3452*/ GIMT_Encode4(223226), // Rule ID 2381 //
        GIM_CheckFeatures, GIMT_Encode2(GIFBS_isGFX12Plus_isWave64),
        GIM_CheckIntrinsicID, /*MI*/0, /*Op*/1, GIMT_Encode2(Intrinsic::amdgcn_wmma_f32_16x16x16_fp8_fp8),
        GIM_CheckType, /*MI*/0, /*Op*/0, /*Type*/GILLT_v4s32,
        GIM_CheckType, /*MI*/0, /*Op*/2, /*Type*/GILLT_s32,
        GIM_CheckType, /*MI*/0, /*Op*/3, /*Type*/GILLT_s32,
        GIM_CheckType, /*MI*/0, /*Op*/4, /*Type*/GILLT_v4s32,
        GIM_CheckRegBankForClass, /*MI*/0, /*Op*/0, /*RC*/GIMT_Encode2(AMDGPU::VReg_128RegClassID),
        GIM_CheckComplexPattern, /*MI*/0, /*Op*/4, /*Renderer*/GIMT_Encode2(0), GIMT_Encode2(GICP_gi_wmmavisrc),
        // (intrinsic_wo_chain:{ *:[v4f32] } 2818:{ *:[iPTR] }, i32:{ *:[i32] }:$src0, i32:{ *:[i32] }:$src1, (WMMAVISrc:{ *:[v4f32] } v4f32:{ *:[v4f32] }:$src2))  =>  (V_WMMA_F32_16X16X16_FP8_FP8_w64_threeaddr:{ *:[v4f32] } i32:{ *:[i32] }:$src0, i32:{ *:[i32] }:$src1, 8:{ *:[i32] }, v4f32:{ *:[v4f32] }:$src2)
        GIR_BuildMI, /*InsnID*/0, /*Opcode*/GIMT_Encode2(AMDGPU::V_WMMA_F32_16X16X16_FP8_FP8_w64_threeaddr),
        GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/0, // DstI[vdst]
        GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/2, // src0
        GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/3, // src1
        GIR_AddImm8, /*InsnID*/0, /*Imm*/8,
        GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/0, // src2
        GIR_AddImm8, /*InsnID*/0, /*Imm*/0,
        GIR_AddImm8, /*InsnID*/0, /*Imm*/0,
        GIR_ConstrainSelectedInstOperands, /*InsnID*/0,
        GIR_EraseFromParent, /*InsnID*/0,
        // GIR_Coverage, 2381,
        GIR_Done,
      // Label 3452: @223226
      GIM_Try, /*On fail goto*//*Label 3453*/ GIMT_Encode4(223302), // Rule ID 2383 //
        GIM_CheckFeatures, GIMT_Encode2(GIFBS_isGFX12Plus_isWave64),
        GIM_CheckIntrinsicID, /*MI*/0, /*Op*/1, GIMT_Encode2(Intrinsic::amdgcn_wmma_f32_16x16x16_fp8_bf8),
        GIM_CheckType, /*MI*/0, /*Op*/0, /*Type*/GILLT_v4s32,
        GIM_CheckType, /*MI*/0, /*Op*/2, /*Type*/GILLT_s32,
        GIM_CheckType, /*MI*/0, /*Op*/3, /*Type*/GILLT_s32,
        GIM_CheckType, /*MI*/0, /*Op*/4, /*Type*/GILLT_v4s32,
        GIM_CheckRegBankForClass, /*MI*/0, /*Op*/0, /*RC*/GIMT_Encode2(AMDGPU::VReg_128RegClassID),
        GIM_CheckComplexPattern, /*MI*/0, /*Op*/4, /*Renderer*/GIMT_Encode2(0), GIMT_Encode2(GICP_gi_wmmavisrc),
        // (intrinsic_wo_chain:{ *:[v4f32] } 2817:{ *:[iPTR] }, i32:{ *:[i32] }:$src0, i32:{ *:[i32] }:$src1, (WMMAVISrc:{ *:[v4f32] } v4f32:{ *:[v4f32] }:$src2))  =>  (V_WMMA_F32_16X16X16_FP8_BF8_w64_threeaddr:{ *:[v4f32] } i32:{ *:[i32] }:$src0, i32:{ *:[i32] }:$src1, 8:{ *:[i32] }, v4f32:{ *:[v4f32] }:$src2)
        GIR_BuildMI, /*InsnID*/0, /*Opcode*/GIMT_Encode2(AMDGPU::V_WMMA_F32_16X16X16_FP8_BF8_w64_threeaddr),
        GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/0, // DstI[vdst]
        GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/2, // src0
        GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/3, // src1
        GIR_AddImm8, /*InsnID*/0, /*Imm*/8,
        GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/0, // src2
        GIR_AddImm8, /*InsnID*/0, /*Imm*/0,
        GIR_AddImm8, /*InsnID*/0, /*Imm*/0,
        GIR_ConstrainSelectedInstOperands, /*InsnID*/0,
        GIR_EraseFromParent, /*InsnID*/0,
        // GIR_Coverage, 2383,
        GIR_Done,
      // Label 3453: @223302
      GIM_Try, /*On fail goto*//*Label 3454*/ GIMT_Encode4(223378), // Rule ID 2385 //
        GIM_CheckFeatures, GIMT_Encode2(GIFBS_isGFX12Plus_isWave64),
        GIM_CheckIntrinsicID, /*MI*/0, /*Op*/1, GIMT_Encode2(Intrinsic::amdgcn_wmma_f32_16x16x16_bf8_fp8),
        GIM_CheckType, /*MI*/0, /*Op*/0, /*Type*/GILLT_v4s32,
        GIM_CheckType, /*MI*/0, /*Op*/2, /*Type*/GILLT_s32,
        GIM_CheckType, /*MI*/0, /*Op*/3, /*Type*/GILLT_s32,
        GIM_CheckType, /*MI*/0, /*Op*/4, /*Type*/GILLT_v4s32,
        GIM_CheckRegBankForClass, /*MI*/0, /*Op*/0, /*RC*/GIMT_Encode2(AMDGPU::VReg_128RegClassID),
        GIM_CheckComplexPattern, /*MI*/0, /*Op*/4, /*Renderer*/GIMT_Encode2(0), GIMT_Encode2(GICP_gi_wmmavisrc),
        // (intrinsic_wo_chain:{ *:[v4f32] } 2815:{ *:[iPTR] }, i32:{ *:[i32] }:$src0, i32:{ *:[i32] }:$src1, (WMMAVISrc:{ *:[v4f32] } v4f32:{ *:[v4f32] }:$src2))  =>  (V_WMMA_F32_16X16X16_BF8_FP8_w64_threeaddr:{ *:[v4f32] } i32:{ *:[i32] }:$src0, i32:{ *:[i32] }:$src1, 8:{ *:[i32] }, v4f32:{ *:[v4f32] }:$src2)
        GIR_BuildMI, /*InsnID*/0, /*Opcode*/GIMT_Encode2(AMDGPU::V_WMMA_F32_16X16X16_BF8_FP8_w64_threeaddr),
        GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/0, // DstI[vdst]
        GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/2, // src0
        GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/3, // src1
        GIR_AddImm8, /*InsnID*/0, /*Imm*/8,
        GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/0, // src2
        GIR_AddImm8, /*InsnID*/0, /*Imm*/0,
        GIR_AddImm8, /*InsnID*/0, /*Imm*/0,
        GIR_ConstrainSelectedInstOperands, /*InsnID*/0,
        GIR_EraseFromParent, /*InsnID*/0,
        // GIR_Coverage, 2385,
        GIR_Done,
      // Label 3454: @223378
      GIM_Try, /*On fail goto*//*Label 3455*/ GIMT_Encode4(223454), // Rule ID 2387 //
        GIM_CheckFeatures, GIMT_Encode2(GIFBS_isGFX12Plus_isWave64),
        GIM_CheckIntrinsicID, /*MI*/0, /*Op*/1, GIMT_Encode2(Intrinsic::amdgcn_wmma_f32_16x16x16_bf8_bf8),
        GIM_CheckType, /*MI*/0, /*Op*/0, /*Type*/GILLT_v4s32,
        GIM_CheckType, /*MI*/0, /*Op*/2, /*Type*/GILLT_s32,
        GIM_CheckType, /*MI*/0, /*Op*/3, /*Type*/GILLT_s32,
        GIM_CheckType, /*MI*/0, /*Op*/4, /*Type*/GILLT_v4s32,
        GIM_CheckRegBankForClass, /*MI*/0, /*Op*/0, /*RC*/GIMT_Encode2(AMDGPU::VReg_128RegClassID),
        GIM_CheckComplexPattern, /*MI*/0, /*Op*/4, /*Renderer*/GIMT_Encode2(0), GIMT_Encode2(GICP_gi_wmmavisrc),
        // (intrinsic_wo_chain:{ *:[v4f32] } 2814:{ *:[iPTR] }, i32:{ *:[i32] }:$src0, i32:{ *:[i32] }:$src1, (WMMAVISrc:{ *:[v4f32] } v4f32:{ *:[v4f32] }:$src2))  =>  (V_WMMA_F32_16X16X16_BF8_BF8_w64_threeaddr:{ *:[v4f32] } i32:{ *:[i32] }:$src0, i32:{ *:[i32] }:$src1, 8:{ *:[i32] }, v4f32:{ *:[v4f32] }:$src2)
        GIR_BuildMI, /*InsnID*/0, /*Opcode*/GIMT_Encode2(AMDGPU::V_WMMA_F32_16X16X16_BF8_BF8_w64_threeaddr),
        GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/0, // DstI[vdst]
        GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/2, // src0
        GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/3, // src1
        GIR_AddImm8, /*InsnID*/0, /*Imm*/8,
        GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/0, // src2
        GIR_AddImm8, /*InsnID*/0, /*Imm*/0,
        GIR_AddImm8, /*InsnID*/0, /*Imm*/0,
        GIR_ConstrainSelectedInstOperands, /*InsnID*/0,
        GIR_EraseFromParent, /*InsnID*/0,
        // GIR_Coverage, 2387,
        GIR_Done,
      // Label 3455: @223454
      GIM_Try, /*On fail goto*//*Label 3456*/ GIMT_Encode4(223538), // Rule ID 2337 //
        GIM_CheckFeatures, GIMT_Encode2(GIFBS_isGFX12Plus_isWave32),
        GIM_CheckIntrinsicID, /*MI*/0, /*Op*/1, GIMT_Encode2(Intrinsic::amdgcn_wmma_f32_16x16x16_bf16),
        GIM_CheckType, /*MI*/0, /*Op*/0, /*Type*/GILLT_v8s32,
        GIM_CheckType, /*MI*/0, /*Op*/2, /*Type*/GILLT_v8s16,
        GIM_CheckType, /*MI*/0, /*Op*/3, /*Type*/GILLT_v8s16,
        GIM_CheckType, /*MI*/0, /*Op*/4, /*Type*/GILLT_v8s32,
        GIM_CheckRegBankForClass, /*MI*/0, /*Op*/0, /*RC*/GIMT_Encode2(AMDGPU::VReg_256RegClassID),
        GIM_CheckComplexPattern, /*MI*/0, /*Op*/4, /*Renderer*/GIMT_Encode2(0), GIMT_Encode2(GICP_gi_wmmamods),
        // (intrinsic_wo_chain:{ *:[v8f32] } 2813:{ *:[iPTR] }, v8i16:{ *:[v8i16] }:$src0, v8i16:{ *:[v8i16] }:$src1, (WMMAModsF32NegAbs:{ *:[v8f32] } v8f32:{ *:[v8f32] }:$src2, i32:{ *:[i32] }:$src2_modifiers))  =>  (V_WMMA_F32_16X16X16_BF16_w32_twoaddr:{ *:[v8f32] } 8:{ *:[i32] }, v8i16:{ *:[v8i16] }:$src0, 8:{ *:[i32] }, v8i16:{ *:[v8i16] }:$src1, i32:{ *:[i32] }:$src2_modifiers, v8f32:{ *:[v8f32] }:$src2)
        GIR_BuildMI, /*InsnID*/0, /*Opcode*/GIMT_Encode2(AMDGPU::V_WMMA_F32_16X16X16_BF16_w32_twoaddr),
        GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/0, // DstI[vdst]
        GIR_AddImm8, /*InsnID*/0, /*Imm*/8,
        GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/2, // src0
        GIR_AddImm8, /*InsnID*/0, /*Imm*/8,
        GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/3, // src1
        GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/1, // src2_modifiers
        GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/0, // src2
        GIR_AddImm8, /*InsnID*/0, /*Imm*/0,
        GIR_AddImm8, /*InsnID*/0, /*Imm*/0,
        GIR_ConstrainSelectedInstOperands, /*InsnID*/0,
        GIR_EraseFromParent, /*InsnID*/0,
        // GIR_Coverage, 2337,
        GIR_Done,
      // Label 3456: @223538
      GIM_Try, /*On fail goto*//*Label 3457*/ GIMT_Encode4(223616), // Rule ID 2347 //
        GIM_CheckFeatures, GIMT_Encode2(GIFBS_isGFX12Plus_isWave32),
        GIM_CheckIntrinsicID, /*MI*/0, /*Op*/1, GIMT_Encode2(Intrinsic::amdgcn_wmma_f32_16x16x16_fp8_fp8),
        GIM_CheckType, /*MI*/0, /*Op*/0, /*Type*/GILLT_v8s32,
        GIM_CheckType, /*MI*/0, /*Op*/2, /*Type*/GILLT_v2s32,
        GIM_CheckType, /*MI*/0, /*Op*/3, /*Type*/GILLT_v2s32,
        GIM_CheckType, /*MI*/0, /*Op*/4, /*Type*/GILLT_v8s32,
        GIM_CheckRegBankForClass, /*MI*/0, /*Op*/0, /*RC*/GIMT_Encode2(AMDGPU::VReg_256RegClassID),
        GIM_CheckComplexPattern, /*MI*/0, /*Op*/4, /*Renderer*/GIMT_Encode2(0), GIMT_Encode2(GICP_gi_wmmamods),
        // (intrinsic_wo_chain:{ *:[v8f32] } 2818:{ *:[iPTR] }, v2i32:{ *:[v2i32] }:$src0, v2i32:{ *:[v2i32] }:$src1, (WMMAModsF32NegAbs:{ *:[v8f32] } v8f32:{ *:[v8f32] }:$src2, i32:{ *:[i32] }:$src2_modifiers))  =>  (V_WMMA_F32_16X16X16_FP8_FP8_w32_twoaddr:{ *:[v8f32] } v2i32:{ *:[v2i32] }:$src0, v2i32:{ *:[v2i32] }:$src1, i32:{ *:[i32] }:$src2_modifiers, v8f32:{ *:[v8f32] }:$src2)
        GIR_BuildMI, /*InsnID*/0, /*Opcode*/GIMT_Encode2(AMDGPU::V_WMMA_F32_16X16X16_FP8_FP8_w32_twoaddr),
        GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/0, // DstI[vdst]
        GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/2, // src0
        GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/3, // src1
        GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/1, // src2_modifiers
        GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/0, // src2
        GIR_AddImm8, /*InsnID*/0, /*Imm*/0,
        GIR_AddImm8, /*InsnID*/0, /*Imm*/0,
        GIR_ConstrainSelectedInstOperands, /*InsnID*/0,
        GIR_EraseFromParent, /*InsnID*/0,
        // GIR_Coverage, 2347,
        GIR_Done,
      // Label 3457: @223616
      GIM_Try, /*On fail goto*//*Label 3458*/ GIMT_Encode4(223694), // Rule ID 2349 //
        GIM_CheckFeatures, GIMT_Encode2(GIFBS_isGFX12Plus_isWave32),
        GIM_CheckIntrinsicID, /*MI*/0, /*Op*/1, GIMT_Encode2(Intrinsic::amdgcn_wmma_f32_16x16x16_fp8_bf8),
        GIM_CheckType, /*MI*/0, /*Op*/0, /*Type*/GILLT_v8s32,
        GIM_CheckType, /*MI*/0, /*Op*/2, /*Type*/GILLT_v2s32,
        GIM_CheckType, /*MI*/0, /*Op*/3, /*Type*/GILLT_v2s32,
        GIM_CheckType, /*MI*/0, /*Op*/4, /*Type*/GILLT_v8s32,
        GIM_CheckRegBankForClass, /*MI*/0, /*Op*/0, /*RC*/GIMT_Encode2(AMDGPU::VReg_256RegClassID),
        GIM_CheckComplexPattern, /*MI*/0, /*Op*/4, /*Renderer*/GIMT_Encode2(0), GIMT_Encode2(GICP_gi_wmmamods),
        // (intrinsic_wo_chain:{ *:[v8f32] } 2817:{ *:[iPTR] }, v2i32:{ *:[v2i32] }:$src0, v2i32:{ *:[v2i32] }:$src1, (WMMAModsF32NegAbs:{ *:[v8f32] } v8f32:{ *:[v8f32] }:$src2, i32:{ *:[i32] }:$src2_modifiers))  =>  (V_WMMA_F32_16X16X16_FP8_BF8_w32_twoaddr:{ *:[v8f32] } v2i32:{ *:[v2i32] }:$src0, v2i32:{ *:[v2i32] }:$src1, i32:{ *:[i32] }:$src2_modifiers, v8f32:{ *:[v8f32] }:$src2)
        GIR_BuildMI, /*InsnID*/0, /*Opcode*/GIMT_Encode2(AMDGPU::V_WMMA_F32_16X16X16_FP8_BF8_w32_twoaddr),
        GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/0, // DstI[vdst]
        GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/2, // src0
        GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/3, // src1
        GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/1, // src2_modifiers
        GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/0, // src2
        GIR_AddImm8, /*InsnID*/0, /*Imm*/0,
        GIR_AddImm8, /*InsnID*/0, /*Imm*/0,
        GIR_ConstrainSelectedInstOperands, /*InsnID*/0,
        GIR_EraseFromParent, /*InsnID*/0,
        // GIR_Coverage, 2349,
        GIR_Done,
      // Label 3458: @223694
      GIM_Try, /*On fail goto*//*Label 3459*/ GIMT_Encode4(223772), // Rule ID 2351 //
        GIM_CheckFeatures, GIMT_Encode2(GIFBS_isGFX12Plus_isWave32),
        GIM_CheckIntrinsicID, /*MI*/0, /*Op*/1, GIMT_Encode2(Intrinsic::amdgcn_wmma_f32_16x16x16_bf8_fp8),
        GIM_CheckType, /*MI*/0, /*Op*/0, /*Type*/GILLT_v8s32,
        GIM_CheckType, /*MI*/0, /*Op*/2, /*Type*/GILLT_v2s32,
        GIM_CheckType, /*MI*/0, /*Op*/3, /*Type*/GILLT_v2s32,
        GIM_CheckType, /*MI*/0, /*Op*/4, /*Type*/GILLT_v8s32,
        GIM_CheckRegBankForClass, /*MI*/0, /*Op*/0, /*RC*/GIMT_Encode2(AMDGPU::VReg_256RegClassID),
        GIM_CheckComplexPattern, /*MI*/0, /*Op*/4, /*Renderer*/GIMT_Encode2(0), GIMT_Encode2(GICP_gi_wmmamods),
        // (intrinsic_wo_chain:{ *:[v8f32] } 2815:{ *:[iPTR] }, v2i32:{ *:[v2i32] }:$src0, v2i32:{ *:[v2i32] }:$src1, (WMMAModsF32NegAbs:{ *:[v8f32] } v8f32:{ *:[v8f32] }:$src2, i32:{ *:[i32] }:$src2_modifiers))  =>  (V_WMMA_F32_16X16X16_BF8_FP8_w32_twoaddr:{ *:[v8f32] } v2i32:{ *:[v2i32] }:$src0, v2i32:{ *:[v2i32] }:$src1, i32:{ *:[i32] }:$src2_modifiers, v8f32:{ *:[v8f32] }:$src2)
        GIR_BuildMI, /*InsnID*/0, /*Opcode*/GIMT_Encode2(AMDGPU::V_WMMA_F32_16X16X16_BF8_FP8_w32_twoaddr),
        GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/0, // DstI[vdst]
        GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/2, // src0
        GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/3, // src1
        GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/1, // src2_modifiers
        GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/0, // src2
        GIR_AddImm8, /*InsnID*/0, /*Imm*/0,
        GIR_AddImm8, /*InsnID*/0, /*Imm*/0,
        GIR_ConstrainSelectedInstOperands, /*InsnID*/0,
        GIR_EraseFromParent, /*InsnID*/0,
        // GIR_Coverage, 2351,
        GIR_Done,
      // Label 3459: @223772
      GIM_Try, /*On fail goto*//*Label 3460*/ GIMT_Encode4(223850), // Rule ID 2353 //
        GIM_CheckFeatures, GIMT_Encode2(GIFBS_isGFX12Plus_isWave32),
        GIM_CheckIntrinsicID, /*MI*/0, /*Op*/1, GIMT_Encode2(Intrinsic::amdgcn_wmma_f32_16x16x16_bf8_bf8),
        GIM_CheckType, /*MI*/0, /*Op*/0, /*Type*/GILLT_v8s32,
        GIM_CheckType, /*MI*/0, /*Op*/2, /*Type*/GILLT_v2s32,
        GIM_CheckType, /*MI*/0, /*Op*/3, /*Type*/GILLT_v2s32,
        GIM_CheckType, /*MI*/0, /*Op*/4, /*Type*/GILLT_v8s32,
        GIM_CheckRegBankForClass, /*MI*/0, /*Op*/0, /*RC*/GIMT_Encode2(AMDGPU::VReg_256RegClassID),
        GIM_CheckComplexPattern, /*MI*/0, /*Op*/4, /*Renderer*/GIMT_Encode2(0), GIMT_Encode2(GICP_gi_wmmamods),
        // (intrinsic_wo_chain:{ *:[v8f32] } 2814:{ *:[iPTR] }, v2i32:{ *:[v2i32] }:$src0, v2i32:{ *:[v2i32] }:$src1, (WMMAModsF32NegAbs:{ *:[v8f32] } v8f32:{ *:[v8f32] }:$src2, i32:{ *:[i32] }:$src2_modifiers))  =>  (V_WMMA_F32_16X16X16_BF8_BF8_w32_twoaddr:{ *:[v8f32] } v2i32:{ *:[v2i32] }:$src0, v2i32:{ *:[v2i32] }:$src1, i32:{ *:[i32] }:$src2_modifiers, v8f32:{ *:[v8f32] }:$src2)
        GIR_BuildMI, /*InsnID*/0, /*Opcode*/GIMT_Encode2(AMDGPU::V_WMMA_F32_16X16X16_BF8_BF8_w32_twoaddr),
        GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/0, // DstI[vdst]
        GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/2, // src0
        GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/3, // src1
        GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/1, // src2_modifiers
        GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/0, // src2
        GIR_AddImm8, /*InsnID*/0, /*Imm*/0,
        GIR_AddImm8, /*InsnID*/0, /*Imm*/0,
        GIR_ConstrainSelectedInstOperands, /*InsnID*/0,
        GIR_EraseFromParent, /*InsnID*/0,
        // GIR_Coverage, 2353,
        GIR_Done,
      // Label 3460: @223850
      GIM_Try, /*On fail goto*//*Label 3461*/ GIMT_Encode4(223934), // Rule ID 2370 //
        GIM_CheckFeatures, GIMT_Encode2(GIFBS_isGFX12Plus_isWave64),
        GIM_CheckIntrinsicID, /*MI*/0, /*Op*/1, GIMT_Encode2(Intrinsic::amdgcn_wmma_f32_16x16x16_bf16),
        GIM_CheckType, /*MI*/0, /*Op*/0, /*Type*/GILLT_v4s32,
        GIM_CheckType, /*MI*/0, /*Op*/2, /*Type*/GILLT_v4s16,
        GIM_CheckType, /*MI*/0, /*Op*/3, /*Type*/GILLT_v4s16,
        GIM_CheckType, /*MI*/0, /*Op*/4, /*Type*/GILLT_v4s32,
        GIM_CheckRegBankForClass, /*MI*/0, /*Op*/0, /*RC*/GIMT_Encode2(AMDGPU::VReg_128RegClassID),
        GIM_CheckComplexPattern, /*MI*/0, /*Op*/4, /*Renderer*/GIMT_Encode2(0), GIMT_Encode2(GICP_gi_wmmamods),
        // (intrinsic_wo_chain:{ *:[v4f32] } 2813:{ *:[iPTR] }, v4i16:{ *:[v4i16] }:$src0, v4i16:{ *:[v4i16] }:$src1, (WMMAModsF32NegAbs:{ *:[v4f32] } v4f32:{ *:[v4f32] }:$src2, i32:{ *:[i32] }:$src2_modifiers))  =>  (V_WMMA_F32_16X16X16_BF16_w64_twoaddr:{ *:[v4f32] } 8:{ *:[i32] }, v4i16:{ *:[v4i16] }:$src0, 8:{ *:[i32] }, v4i16:{ *:[v4i16] }:$src1, i32:{ *:[i32] }:$src2_modifiers, v4f32:{ *:[v4f32] }:$src2)
        GIR_BuildMI, /*InsnID*/0, /*Opcode*/GIMT_Encode2(AMDGPU::V_WMMA_F32_16X16X16_BF16_w64_twoaddr),
        GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/0, // DstI[vdst]
        GIR_AddImm8, /*InsnID*/0, /*Imm*/8,
        GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/2, // src0
        GIR_AddImm8, /*InsnID*/0, /*Imm*/8,
        GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/3, // src1
        GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/1, // src2_modifiers
        GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/0, // src2
        GIR_AddImm8, /*InsnID*/0, /*Imm*/0,
        GIR_AddImm8, /*InsnID*/0, /*Imm*/0,
        GIR_ConstrainSelectedInstOperands, /*InsnID*/0,
        GIR_EraseFromParent, /*InsnID*/0,
        // GIR_Coverage, 2370,
        GIR_Done,
      // Label 3461: @223934
      GIM_Try, /*On fail goto*//*Label 3462*/ GIMT_Encode4(224012), // Rule ID 2380 //
        GIM_CheckFeatures, GIMT_Encode2(GIFBS_isGFX12Plus_isWave64),
        GIM_CheckIntrinsicID, /*MI*/0, /*Op*/1, GIMT_Encode2(Intrinsic::amdgcn_wmma_f32_16x16x16_fp8_fp8),
        GIM_CheckType, /*MI*/0, /*Op*/0, /*Type*/GILLT_v4s32,
        GIM_CheckType, /*MI*/0, /*Op*/2, /*Type*/GILLT_s32,
        GIM_CheckType, /*MI*/0, /*Op*/3, /*Type*/GILLT_s32,
        GIM_CheckType, /*MI*/0, /*Op*/4, /*Type*/GILLT_v4s32,
        GIM_CheckRegBankForClass, /*MI*/0, /*Op*/0, /*RC*/GIMT_Encode2(AMDGPU::VReg_128RegClassID),
        GIM_CheckComplexPattern, /*MI*/0, /*Op*/4, /*Renderer*/GIMT_Encode2(0), GIMT_Encode2(GICP_gi_wmmamods),
        // (intrinsic_wo_chain:{ *:[v4f32] } 2818:{ *:[iPTR] }, i32:{ *:[i32] }:$src0, i32:{ *:[i32] }:$src1, (WMMAModsF32NegAbs:{ *:[v4f32] } v4f32:{ *:[v4f32] }:$src2, i32:{ *:[i32] }:$src2_modifiers))  =>  (V_WMMA_F32_16X16X16_FP8_FP8_w64_twoaddr:{ *:[v4f32] } i32:{ *:[i32] }:$src0, i32:{ *:[i32] }:$src1, i32:{ *:[i32] }:$src2_modifiers, v4f32:{ *:[v4f32] }:$src2)
        GIR_BuildMI, /*InsnID*/0, /*Opcode*/GIMT_Encode2(AMDGPU::V_WMMA_F32_16X16X16_FP8_FP8_w64_twoaddr),
        GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/0, // DstI[vdst]
        GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/2, // src0
        GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/3, // src1
        GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/1, // src2_modifiers
        GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/0, // src2
        GIR_AddImm8, /*InsnID*/0, /*Imm*/0,
        GIR_AddImm8, /*InsnID*/0, /*Imm*/0,
        GIR_ConstrainSelectedInstOperands, /*InsnID*/0,
        GIR_EraseFromParent, /*InsnID*/0,
        // GIR_Coverage, 2380,
        GIR_Done,
      // Label 3462: @224012
      GIM_Try, /*On fail goto*//*Label 3463*/ GIMT_Encode4(224090), // Rule ID 2382 //
        GIM_CheckFeatures, GIMT_Encode2(GIFBS_isGFX12Plus_isWave64),
        GIM_CheckIntrinsicID, /*MI*/0, /*Op*/1, GIMT_Encode2(Intrinsic::amdgcn_wmma_f32_16x16x16_fp8_bf8),
        GIM_CheckType, /*MI*/0, /*Op*/0, /*Type*/GILLT_v4s32,
        GIM_CheckType, /*MI*/0, /*Op*/2, /*Type*/GILLT_s32,
        GIM_CheckType, /*MI*/0, /*Op*/3, /*Type*/GILLT_s32,
        GIM_CheckType, /*MI*/0, /*Op*/4, /*Type*/GILLT_v4s32,
        GIM_CheckRegBankForClass, /*MI*/0, /*Op*/0, /*RC*/GIMT_Encode2(AMDGPU::VReg_128RegClassID),
        GIM_CheckComplexPattern, /*MI*/0, /*Op*/4, /*Renderer*/GIMT_Encode2(0), GIMT_Encode2(GICP_gi_wmmamods),
        // (intrinsic_wo_chain:{ *:[v4f32] } 2817:{ *:[iPTR] }, i32:{ *:[i32] }:$src0, i32:{ *:[i32] }:$src1, (WMMAModsF32NegAbs:{ *:[v4f32] } v4f32:{ *:[v4f32] }:$src2, i32:{ *:[i32] }:$src2_modifiers))  =>  (V_WMMA_F32_16X16X16_FP8_BF8_w64_twoaddr:{ *:[v4f32] } i32:{ *:[i32] }:$src0, i32:{ *:[i32] }:$src1, i32:{ *:[i32] }:$src2_modifiers, v4f32:{ *:[v4f32] }:$src2)
        GIR_BuildMI, /*InsnID*/0, /*Opcode*/GIMT_Encode2(AMDGPU::V_WMMA_F32_16X16X16_FP8_BF8_w64_twoaddr),
        GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/0, // DstI[vdst]
        GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/2, // src0
        GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/3, // src1
        GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/1, // src2_modifiers
        GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/0, // src2
        GIR_AddImm8, /*InsnID*/0, /*Imm*/0,
        GIR_AddImm8, /*InsnID*/0, /*Imm*/0,
        GIR_ConstrainSelectedInstOperands, /*InsnID*/0,
        GIR_EraseFromParent, /*InsnID*/0,
        // GIR_Coverage, 2382,
        GIR_Done,
      // Label 3463: @224090
      GIM_Try, /*On fail goto*//*Label 3464*/ GIMT_Encode4(224168), // Rule ID 2384 //
        GIM_CheckFeatures, GIMT_Encode2(GIFBS_isGFX12Plus_isWave64),
        GIM_CheckIntrinsicID, /*MI*/0, /*Op*/1, GIMT_Encode2(Intrinsic::amdgcn_wmma_f32_16x16x16_bf8_fp8),
        GIM_CheckType, /*MI*/0, /*Op*/0, /*Type*/GILLT_v4s32,
        GIM_CheckType, /*MI*/0, /*Op*/2, /*Type*/GILLT_s32,
        GIM_CheckType, /*MI*/0, /*Op*/3, /*Type*/GILLT_s32,
        GIM_CheckType, /*MI*/0, /*Op*/4, /*Type*/GILLT_v4s32,
        GIM_CheckRegBankForClass, /*MI*/0, /*Op*/0, /*RC*/GIMT_Encode2(AMDGPU::VReg_128RegClassID),
        GIM_CheckComplexPattern, /*MI*/0, /*Op*/4, /*Renderer*/GIMT_Encode2(0), GIMT_Encode2(GICP_gi_wmmamods),
        // (intrinsic_wo_chain:{ *:[v4f32] } 2815:{ *:[iPTR] }, i32:{ *:[i32] }:$src0, i32:{ *:[i32] }:$src1, (WMMAModsF32NegAbs:{ *:[v4f32] } v4f32:{ *:[v4f32] }:$src2, i32:{ *:[i32] }:$src2_modifiers))  =>  (V_WMMA_F32_16X16X16_BF8_FP8_w64_twoaddr:{ *:[v4f32] } i32:{ *:[i32] }:$src0, i32:{ *:[i32] }:$src1, i32:{ *:[i32] }:$src2_modifiers, v4f32:{ *:[v4f32] }:$src2)
        GIR_BuildMI, /*InsnID*/0, /*Opcode*/GIMT_Encode2(AMDGPU::V_WMMA_F32_16X16X16_BF8_FP8_w64_twoaddr),
        GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/0, // DstI[vdst]
        GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/2, // src0
        GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/3, // src1
        GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/1, // src2_modifiers
        GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/0, // src2
        GIR_AddImm8, /*InsnID*/0, /*Imm*/0,
        GIR_AddImm8, /*InsnID*/0, /*Imm*/0,
        GIR_ConstrainSelectedInstOperands, /*InsnID*/0,
        GIR_EraseFromParent, /*InsnID*/0,
        // GIR_Coverage, 2384,
        GIR_Done,
      // Label 3464: @224168
      GIM_Try, /*On fail goto*//*Label 3465*/ GIMT_Encode4(224246), // Rule ID 2386 //
        GIM_CheckFeatures, GIMT_Encode2(GIFBS_isGFX12Plus_isWave64),
        GIM_CheckIntrinsicID, /*MI*/0, /*Op*/1, GIMT_Encode2(Intrinsic::amdgcn_wmma_f32_16x16x16_bf8_bf8),
        GIM_CheckType, /*MI*/0, /*Op*/0, /*Type*/GILLT_v4s32,
        GIM_CheckType, /*MI*/0, /*Op*/2, /*Type*/GILLT_s32,
        GIM_CheckType, /*MI*/0, /*Op*/3, /*Type*/GILLT_s32,
        GIM_CheckType, /*MI*/0, /*Op*/4, /*Type*/GILLT_v4s32,
        GIM_CheckRegBankForClass, /*MI*/0, /*Op*/0, /*RC*/GIMT_Encode2(AMDGPU::VReg_128RegClassID),
        GIM_CheckComplexPattern, /*MI*/0, /*Op*/4, /*Renderer*/GIMT_Encode2(0), GIMT_Encode2(GICP_gi_wmmamods),
        // (intrinsic_wo_chain:{ *:[v4f32] } 2814:{ *:[iPTR] }, i32:{ *:[i32] }:$src0, i32:{ *:[i32] }:$src1, (WMMAModsF32NegAbs:{ *:[v4f32] } v4f32:{ *:[v4f32] }:$src2, i32:{ *:[i32] }:$src2_modifiers))  =>  (V_WMMA_F32_16X16X16_BF8_BF8_w64_twoaddr:{ *:[v4f32] } i32:{ *:[i32] }:$src0, i32:{ *:[i32] }:$src1, i32:{ *:[i32] }:$src2_modifiers, v4f32:{ *:[v4f32] }:$src2)
        GIR_BuildMI, /*InsnID*/0, /*Opcode*/GIMT_Encode2(AMDGPU::V_WMMA_F32_16X16X16_BF8_BF8_w64_twoaddr),
        GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/0, // DstI[vdst]
        GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/2, // src0
        GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/3, // src1
        GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/1, // src2_modifiers
        GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/0, // src2
        GIR_AddImm8, /*InsnID*/0, /*Imm*/0,
        GIR_AddImm8, /*InsnID*/0, /*Imm*/0,
        GIR_ConstrainSelectedInstOperands, /*InsnID*/0,
        GIR_EraseFromParent, /*InsnID*/0,
        // GIR_Coverage, 2386,
        GIR_Done,
      // Label 3465: @224246
      GIM_Try, /*On fail goto*//*Label 3466*/ GIMT_Encode4(224302), // Rule ID 757 //
        GIM_CheckIntrinsicID, /*MI*/0, /*Op*/1, GIMT_Encode2(Intrinsic::amdgcn_writelane),
        GIM_CheckType, /*MI*/0, /*Op*/0, /*Type*/GILLT_s32,
        GIM_CheckType, /*MI*/0, /*Op*/2, /*Type*/GILLT_s32,
        GIM_CheckType, /*MI*/0, /*Op*/3, /*Type*/GILLT_s32,
        GIM_CheckType, /*MI*/0, /*Op*/4, /*Type*/GILLT_s32,
        GIM_CheckRegBankForClass, /*MI*/0, /*Op*/0, /*RC*/GIMT_Encode2(AMDGPU::VGPR_32RegClassID),
        // (intrinsic_wo_chain:{ *:[i32] } 2831:{ *:[iPTR] }, i32:{ *:[i32] }:$src0, i32:{ *:[i32] }:$src1, i32:{ *:[i32] }:$vdst_in)  =>  (V_WRITELANE_B32:{ *:[i32] } i32:{ *:[i32] }:$src0, i32:{ *:[i32] }:$src1, i32:{ *:[i32] }:$vdst_in)
        GIR_BuildMI, /*InsnID*/0, /*Opcode*/GIMT_Encode2(AMDGPU::V_WRITELANE_B32),
        GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/0, // DstI[vdst]
        GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/2, // src0
        GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/3, // src1
        GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/4, // vdst_in
        GIR_ConstrainSelectedInstOperands, /*InsnID*/0,
        GIR_EraseFromParent, /*InsnID*/0,
        // GIR_Coverage, 757,
        GIR_Done,
      // Label 3466: @224302
      GIM_Reject,
    // Label 3437: @224303
    GIM_Try, /*On fail goto*//*Label 3467*/ GIMT_Encode4(227292),
      GIM_CheckNumOperands, /*MI*/0, /*Expected*/6,
      GIM_Try, /*On fail goto*//*Label 3468*/ GIMT_Encode4(224424), // Rule ID 2340 //
        GIM_CheckFeatures, GIMT_Encode2(GIFBS_isGFX12Plus_isWave32),
        GIM_CheckIntrinsicID, /*MI*/0, /*Op*/1, GIMT_Encode2(Intrinsic::amdgcn_wmma_f16_16x16x16_f16),
        GIM_CheckType, /*MI*/0, /*Op*/0, /*Type*/GILLT_v8s16,
        GIM_CheckType, /*MI*/0, /*Op*/2, /*Type*/GILLT_v8s16,
        GIM_CheckType, /*MI*/0, /*Op*/3, /*Type*/GILLT_v8s16,
        GIM_CheckType, /*MI*/0, /*Op*/4, /*Type*/GILLT_v8s16,
        GIM_CheckRegBankForClass, /*MI*/0, /*Op*/0, /*RC*/GIMT_Encode2(AMDGPU::VReg_128RegClassID),
        // MIs[0] Operand 5
        GIM_CheckLiteralInt, /*MI*/0, /*Op*/5, GIMT_Encode8(0),
        GIM_CheckComplexPattern, /*MI*/0, /*Op*/2, /*Renderer*/GIMT_Encode2(0), GIMT_Encode2(GICP_gi_wmmamodsf16Neg),
        GIM_CheckComplexPattern, /*MI*/0, /*Op*/3, /*Renderer*/GIMT_Encode2(1), GIMT_Encode2(GICP_gi_wmmamodsf16Neg),
        GIM_CheckComplexPattern, /*MI*/0, /*Op*/4, /*Renderer*/GIMT_Encode2(2), GIMT_Encode2(GICP_gi_wmmavisrc),
        // (intrinsic_wo_chain:{ *:[v8f16] } 2811:{ *:[iPTR] }, (WMMAModsF16Neg:{ *:[v8f16] } v8f16:{ *:[v8f16] }:$src0, i32:{ *:[i32] }:$src0_modifiers), (WMMAModsF16Neg:{ *:[v8f16] } v8f16:{ *:[v8f16] }:$src1, i32:{ *:[i32] }:$src1_modifiers), (WMMAVISrc:{ *:[v8f16] } v8f16:{ *:[v8f16] }:$src2), 0:{ *:[i1] })  =>  (V_WMMA_F16_16X16X16_F16_w32_threeaddr:{ *:[v8f16] } i32:{ *:[i32] }:$src0_modifiers, v8f16:{ *:[v8f16] }:$src0, i32:{ *:[i32] }:$src1_modifiers, v8f16:{ *:[v8f16] }:$src1, 8:{ *:[i32] }, v8f16:{ *:[v8f16] }:$src2)
        GIR_BuildMI, /*InsnID*/0, /*Opcode*/GIMT_Encode2(AMDGPU::V_WMMA_F16_16X16X16_F16_w32_threeaddr),
        GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/0, // DstI[vdst]
        GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/1, // src0_modifiers
        GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/0, // src0
        GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(1), /*SubOperand*/1, // src1_modifiers
        GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(1), /*SubOperand*/0, // src1
        GIR_AddImm8, /*InsnID*/0, /*Imm*/8,
        GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(2), /*SubOperand*/0, // src2
        GIR_AddImm8, /*InsnID*/0, /*Imm*/0,
        GIR_AddImm8, /*InsnID*/0, /*Imm*/0,
        GIR_ConstrainSelectedInstOperands, /*InsnID*/0,
        GIR_EraseFromParent, /*InsnID*/0,
        // GIR_Coverage, 2340,
        GIR_Done,
      // Label 3468: @224424
      GIM_Try, /*On fail goto*//*Label 3469*/ GIMT_Encode4(224537), // Rule ID 2373 //
        GIM_CheckFeatures, GIMT_Encode2(GIFBS_isGFX12Plus_isWave64),
        GIM_CheckIntrinsicID, /*MI*/0, /*Op*/1, GIMT_Encode2(Intrinsic::amdgcn_wmma_f16_16x16x16_f16),
        GIM_CheckType, /*MI*/0, /*Op*/0, /*Type*/GILLT_v4s16,
        GIM_CheckType, /*MI*/0, /*Op*/2, /*Type*/GILLT_v4s16,
        GIM_CheckType, /*MI*/0, /*Op*/3, /*Type*/GILLT_v4s16,
        GIM_CheckType, /*MI*/0, /*Op*/4, /*Type*/GILLT_v4s16,
        GIM_CheckRegBankForClass, /*MI*/0, /*Op*/0, /*RC*/GIMT_Encode2(AMDGPU::VReg_64RegClassID),
        // MIs[0] Operand 5
        GIM_CheckLiteralInt, /*MI*/0, /*Op*/5, GIMT_Encode8(0),
        GIM_CheckComplexPattern, /*MI*/0, /*Op*/2, /*Renderer*/GIMT_Encode2(0), GIMT_Encode2(GICP_gi_wmmamodsf16Neg),
        GIM_CheckComplexPattern, /*MI*/0, /*Op*/3, /*Renderer*/GIMT_Encode2(1), GIMT_Encode2(GICP_gi_wmmamodsf16Neg),
        GIM_CheckComplexPattern, /*MI*/0, /*Op*/4, /*Renderer*/GIMT_Encode2(2), GIMT_Encode2(GICP_gi_wmmavisrc),
        // (intrinsic_wo_chain:{ *:[v4f16] } 2811:{ *:[iPTR] }, (WMMAModsF16Neg:{ *:[v4f16] } v4f16:{ *:[v4f16] }:$src0, i32:{ *:[i32] }:$src0_modifiers), (WMMAModsF16Neg:{ *:[v4f16] } v4f16:{ *:[v4f16] }:$src1, i32:{ *:[i32] }:$src1_modifiers), (WMMAVISrc:{ *:[v4f16] } v4f16:{ *:[v4f16] }:$src2), 0:{ *:[i1] })  =>  (V_WMMA_F16_16X16X16_F16_w64_threeaddr:{ *:[v4f16] } i32:{ *:[i32] }:$src0_modifiers, v4f16:{ *:[v4f16] }:$src0, i32:{ *:[i32] }:$src1_modifiers, v4f16:{ *:[v4f16] }:$src1, 8:{ *:[i32] }, v4f16:{ *:[v4f16] }:$src2)
        GIR_BuildMI, /*InsnID*/0, /*Opcode*/GIMT_Encode2(AMDGPU::V_WMMA_F16_16X16X16_F16_w64_threeaddr),
        GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/0, // DstI[vdst]
        GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/1, // src0_modifiers
        GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/0, // src0
        GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(1), /*SubOperand*/1, // src1_modifiers
        GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(1), /*SubOperand*/0, // src1
        GIR_AddImm8, /*InsnID*/0, /*Imm*/8,
        GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(2), /*SubOperand*/0, // src2
        GIR_AddImm8, /*InsnID*/0, /*Imm*/0,
        GIR_AddImm8, /*InsnID*/0, /*Imm*/0,
        GIR_ConstrainSelectedInstOperands, /*InsnID*/0,
        GIR_EraseFromParent, /*InsnID*/0,
        // GIR_Coverage, 2373,
        GIR_Done,
      // Label 3469: @224537
      GIM_Try, /*On fail goto*//*Label 3470*/ GIMT_Encode4(224652), // Rule ID 2339 //
        GIM_CheckFeatures, GIMT_Encode2(GIFBS_isGFX12Plus_isWave32),
        GIM_CheckIntrinsicID, /*MI*/0, /*Op*/1, GIMT_Encode2(Intrinsic::amdgcn_wmma_f16_16x16x16_f16),
        GIM_CheckType, /*MI*/0, /*Op*/0, /*Type*/GILLT_v8s16,
        GIM_CheckType, /*MI*/0, /*Op*/2, /*Type*/GILLT_v8s16,
        GIM_CheckType, /*MI*/0, /*Op*/3, /*Type*/GILLT_v8s16,
        GIM_CheckType, /*MI*/0, /*Op*/4, /*Type*/GILLT_v8s16,
        GIM_CheckRegBankForClass, /*MI*/0, /*Op*/0, /*RC*/GIMT_Encode2(AMDGPU::VReg_128RegClassID),
        // MIs[0] Operand 5
        GIM_CheckLiteralInt, /*MI*/0, /*Op*/5, GIMT_Encode8(0),
        GIM_CheckComplexPattern, /*MI*/0, /*Op*/2, /*Renderer*/GIMT_Encode2(0), GIMT_Encode2(GICP_gi_wmmamodsf16Neg),
        GIM_CheckComplexPattern, /*MI*/0, /*Op*/3, /*Renderer*/GIMT_Encode2(1), GIMT_Encode2(GICP_gi_wmmamodsf16Neg),
        GIM_CheckComplexPattern, /*MI*/0, /*Op*/4, /*Renderer*/GIMT_Encode2(2), GIMT_Encode2(GICP_gi_wmmamodsf16NegAbs),
        // (intrinsic_wo_chain:{ *:[v8f16] } 2811:{ *:[iPTR] }, (WMMAModsF16Neg:{ *:[v8f16] } v8f16:{ *:[v8f16] }:$src0, i32:{ *:[i32] }:$src0_modifiers), (WMMAModsF16Neg:{ *:[v8f16] } v8f16:{ *:[v8f16] }:$src1, i32:{ *:[i32] }:$src1_modifiers), (WMMAModsF16NegAbs:{ *:[v8f16] } v8f16:{ *:[v8f16] }:$src2, i32:{ *:[i32] }:$src2_modifiers), 0:{ *:[i1] })  =>  (V_WMMA_F16_16X16X16_F16_w32_twoaddr:{ *:[v8f16] } i32:{ *:[i32] }:$src0_modifiers, v8f16:{ *:[v8f16] }:$src0, i32:{ *:[i32] }:$src1_modifiers, v8f16:{ *:[v8f16] }:$src1, i32:{ *:[i32] }:$src2_modifiers, v8f16:{ *:[v8f16] }:$src2)
        GIR_BuildMI, /*InsnID*/0, /*Opcode*/GIMT_Encode2(AMDGPU::V_WMMA_F16_16X16X16_F16_w32_twoaddr),
        GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/0, // DstI[vdst]
        GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/1, // src0_modifiers
        GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/0, // src0
        GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(1), /*SubOperand*/1, // src1_modifiers
        GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(1), /*SubOperand*/0, // src1
        GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(2), /*SubOperand*/1, // src2_modifiers
        GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(2), /*SubOperand*/0, // src2
        GIR_AddImm8, /*InsnID*/0, /*Imm*/0,
        GIR_AddImm8, /*InsnID*/0, /*Imm*/0,
        GIR_ConstrainSelectedInstOperands, /*InsnID*/0,
        GIR_EraseFromParent, /*InsnID*/0,
        // GIR_Coverage, 2339,
        GIR_Done,
      // Label 3470: @224652
      GIM_Try, /*On fail goto*//*Label 3471*/ GIMT_Encode4(224767), // Rule ID 2372 //
        GIM_CheckFeatures, GIMT_Encode2(GIFBS_isGFX12Plus_isWave64),
        GIM_CheckIntrinsicID, /*MI*/0, /*Op*/1, GIMT_Encode2(Intrinsic::amdgcn_wmma_f16_16x16x16_f16),
        GIM_CheckType, /*MI*/0, /*Op*/0, /*Type*/GILLT_v4s16,
        GIM_CheckType, /*MI*/0, /*Op*/2, /*Type*/GILLT_v4s16,
        GIM_CheckType, /*MI*/0, /*Op*/3, /*Type*/GILLT_v4s16,
        GIM_CheckType, /*MI*/0, /*Op*/4, /*Type*/GILLT_v4s16,
        GIM_CheckRegBankForClass, /*MI*/0, /*Op*/0, /*RC*/GIMT_Encode2(AMDGPU::VReg_64RegClassID),
        // MIs[0] Operand 5
        GIM_CheckLiteralInt, /*MI*/0, /*Op*/5, GIMT_Encode8(0),
        GIM_CheckComplexPattern, /*MI*/0, /*Op*/2, /*Renderer*/GIMT_Encode2(0), GIMT_Encode2(GICP_gi_wmmamodsf16Neg),
        GIM_CheckComplexPattern, /*MI*/0, /*Op*/3, /*Renderer*/GIMT_Encode2(1), GIMT_Encode2(GICP_gi_wmmamodsf16Neg),
        GIM_CheckComplexPattern, /*MI*/0, /*Op*/4, /*Renderer*/GIMT_Encode2(2), GIMT_Encode2(GICP_gi_wmmamodsf16NegAbs),
        // (intrinsic_wo_chain:{ *:[v4f16] } 2811:{ *:[iPTR] }, (WMMAModsF16Neg:{ *:[v4f16] } v4f16:{ *:[v4f16] }:$src0, i32:{ *:[i32] }:$src0_modifiers), (WMMAModsF16Neg:{ *:[v4f16] } v4f16:{ *:[v4f16] }:$src1, i32:{ *:[i32] }:$src1_modifiers), (WMMAModsF16NegAbs:{ *:[v4f16] } v4f16:{ *:[v4f16] }:$src2, i32:{ *:[i32] }:$src2_modifiers), 0:{ *:[i1] })  =>  (V_WMMA_F16_16X16X16_F16_w64_twoaddr:{ *:[v4f16] } i32:{ *:[i32] }:$src0_modifiers, v4f16:{ *:[v4f16] }:$src0, i32:{ *:[i32] }:$src1_modifiers, v4f16:{ *:[v4f16] }:$src1, i32:{ *:[i32] }:$src2_modifiers, v4f16:{ *:[v4f16] }:$src2)
        GIR_BuildMI, /*InsnID*/0, /*Opcode*/GIMT_Encode2(AMDGPU::V_WMMA_F16_16X16X16_F16_w64_twoaddr),
        GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/0, // DstI[vdst]
        GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/1, // src0_modifiers
        GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/0, // src0
        GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(1), /*SubOperand*/1, // src1_modifiers
        GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(1), /*SubOperand*/0, // src1
        GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(2), /*SubOperand*/1, // src2_modifiers
        GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(2), /*SubOperand*/0, // src2
        GIR_AddImm8, /*InsnID*/0, /*Imm*/0,
        GIR_AddImm8, /*InsnID*/0, /*Imm*/0,
        GIR_ConstrainSelectedInstOperands, /*InsnID*/0,
        GIR_EraseFromParent, /*InsnID*/0,
        // GIR_Coverage, 2372,
        GIR_Done,
      // Label 3471: @224767
      GIM_Try, /*On fail goto*//*Label 3472*/ GIMT_Encode4(224879), // Rule ID 2357 //
        GIM_CheckFeatures, GIMT_Encode2(GIFBS_isGFX12Plus_isWave32),
        GIM_CheckIntrinsicID, /*MI*/0, /*Op*/1, GIMT_Encode2(Intrinsic::amdgcn_swmmac_f32_16x16x32_f16),
        GIM_CheckType, /*MI*/0, /*Op*/0, /*Type*/GILLT_v8s32,
        GIM_CheckType, /*MI*/0, /*Op*/2, /*Type*/GILLT_v8s16,
        GIM_CheckType, /*MI*/0, /*Op*/3, /*Type*/GILLT_v16s16,
        GIM_CheckType, /*MI*/0, /*Op*/4, /*Type*/GILLT_v8s32,
        GIM_CheckType, /*MI*/0, /*Op*/5, /*Type*/GILLT_s32,
        GIM_CheckRegBankForClass, /*MI*/0, /*Op*/0, /*RC*/GIMT_Encode2(AMDGPU::VReg_256RegClassID),
        GIM_CheckComplexPattern, /*MI*/0, /*Op*/2, /*Renderer*/GIMT_Encode2(0), GIMT_Encode2(GICP_gi_wmmamodsf16Neg),
        GIM_CheckComplexPattern, /*MI*/0, /*Op*/3, /*Renderer*/GIMT_Encode2(1), GIMT_Encode2(GICP_gi_wmmamodsf16Neg),
        GIM_CheckComplexPattern, /*MI*/0, /*Op*/5, /*Renderer*/GIMT_Encode2(2), GIMT_Encode2(GICP_gi_swmmacindex16),
        // (intrinsic_wo_chain:{ *:[v8f32] } 2789:{ *:[iPTR] }, (WMMAModsF16Neg:{ *:[v8f16] } v8f16:{ *:[v8f16] }:$src0, i32:{ *:[i32] }:$src0_modifiers), (WMMAModsF16Neg:{ *:[v16f16] } v16f16:{ *:[v16f16] }:$src1, i32:{ *:[i32] }:$src1_modifiers), v8f32:{ *:[v8f32] }:$srcTiedDef, (SWMMACIndex16:{ *:[i32] } i32:{ *:[i32] }:$src2, i32:{ *:[i32] }:$index_key_16bit))  =>  (V_SWMMAC_F32_16X16X32_F16_w32_twoaddr:{ *:[v8f32] } i32:{ *:[i32] }:$src0_modifiers, v8f16:{ *:[v8f16] }:$src0, i32:{ *:[i32] }:$src1_modifiers, v16f16:{ *:[v16f16] }:$src1, v8f32:{ *:[v8f32] }:$srcTiedDef, i32:{ *:[i32] }:$src2, i32:{ *:[i32] }:$index_key_16bit)
        GIR_BuildMI, /*InsnID*/0, /*Opcode*/GIMT_Encode2(AMDGPU::V_SWMMAC_F32_16X16X32_F16_w32_twoaddr),
        GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/0, // DstI[vdst]
        GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/1, // src0_modifiers
        GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/0, // src0
        GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(1), /*SubOperand*/1, // src1_modifiers
        GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(1), /*SubOperand*/0, // src1
        GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/4, // srcTiedDef
        GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(2), /*SubOperand*/0, // src2
        GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(2), /*SubOperand*/1, // index_key_16bit
        GIR_AddImm8, /*InsnID*/0, /*Imm*/0,
        GIR_AddImm8, /*InsnID*/0, /*Imm*/0,
        GIR_ConstrainSelectedInstOperands, /*InsnID*/0,
        GIR_EraseFromParent, /*InsnID*/0,
        // GIR_Coverage, 2357,
        GIR_Done,
      // Label 3472: @224879
      GIM_Try, /*On fail goto*//*Label 3473*/ GIMT_Encode4(224991), // Rule ID 2359 //
        GIM_CheckFeatures, GIMT_Encode2(GIFBS_isGFX12Plus_isWave32),
        GIM_CheckIntrinsicID, /*MI*/0, /*Op*/1, GIMT_Encode2(Intrinsic::amdgcn_swmmac_f16_16x16x32_f16),
        GIM_CheckType, /*MI*/0, /*Op*/0, /*Type*/GILLT_v8s16,
        GIM_CheckType, /*MI*/0, /*Op*/2, /*Type*/GILLT_v8s16,
        GIM_CheckType, /*MI*/0, /*Op*/3, /*Type*/GILLT_v16s16,
        GIM_CheckType, /*MI*/0, /*Op*/4, /*Type*/GILLT_v8s16,
        GIM_CheckType, /*MI*/0, /*Op*/5, /*Type*/GILLT_s32,
        GIM_CheckRegBankForClass, /*MI*/0, /*Op*/0, /*RC*/GIMT_Encode2(AMDGPU::VReg_128RegClassID),
        GIM_CheckComplexPattern, /*MI*/0, /*Op*/2, /*Renderer*/GIMT_Encode2(0), GIMT_Encode2(GICP_gi_wmmamodsf16Neg),
        GIM_CheckComplexPattern, /*MI*/0, /*Op*/3, /*Renderer*/GIMT_Encode2(1), GIMT_Encode2(GICP_gi_wmmamodsf16Neg),
        GIM_CheckComplexPattern, /*MI*/0, /*Op*/5, /*Renderer*/GIMT_Encode2(2), GIMT_Encode2(GICP_gi_swmmacindex16),
        // (intrinsic_wo_chain:{ *:[v8f16] } 2785:{ *:[iPTR] }, (WMMAModsF16Neg:{ *:[v8f16] } v8f16:{ *:[v8f16] }:$src0, i32:{ *:[i32] }:$src0_modifiers), (WMMAModsF16Neg:{ *:[v16f16] } v16f16:{ *:[v16f16] }:$src1, i32:{ *:[i32] }:$src1_modifiers), v8f16:{ *:[v8f16] }:$srcTiedDef, (SWMMACIndex16:{ *:[i32] } i32:{ *:[i32] }:$src2, i32:{ *:[i32] }:$index_key_16bit))  =>  (V_SWMMAC_F16_16X16X32_F16_w32_twoaddr:{ *:[v8f16] } i32:{ *:[i32] }:$src0_modifiers, v8f16:{ *:[v8f16] }:$src0, i32:{ *:[i32] }:$src1_modifiers, v16f16:{ *:[v16f16] }:$src1, v8f16:{ *:[v8f16] }:$srcTiedDef, i32:{ *:[i32] }:$src2, i32:{ *:[i32] }:$index_key_16bit)
        GIR_BuildMI, /*InsnID*/0, /*Opcode*/GIMT_Encode2(AMDGPU::V_SWMMAC_F16_16X16X32_F16_w32_twoaddr),
        GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/0, // DstI[vdst]
        GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/1, // src0_modifiers
        GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/0, // src0
        GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(1), /*SubOperand*/1, // src1_modifiers
        GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(1), /*SubOperand*/0, // src1
        GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/4, // srcTiedDef
        GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(2), /*SubOperand*/0, // src2
        GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(2), /*SubOperand*/1, // index_key_16bit
        GIR_AddImm8, /*InsnID*/0, /*Imm*/0,
        GIR_AddImm8, /*InsnID*/0, /*Imm*/0,
        GIR_ConstrainSelectedInstOperands, /*InsnID*/0,
        GIR_EraseFromParent, /*InsnID*/0,
        // GIR_Coverage, 2359,
        GIR_Done,
      // Label 3473: @224991
      GIM_Try, /*On fail goto*//*Label 3474*/ GIMT_Encode4(225103), // Rule ID 2390 //
        GIM_CheckFeatures, GIMT_Encode2(GIFBS_isGFX12Plus_isWave64),
        GIM_CheckIntrinsicID, /*MI*/0, /*Op*/1, GIMT_Encode2(Intrinsic::amdgcn_swmmac_f32_16x16x32_f16),
        GIM_CheckType, /*MI*/0, /*Op*/0, /*Type*/GILLT_v4s32,
        GIM_CheckType, /*MI*/0, /*Op*/2, /*Type*/GILLT_v4s16,
        GIM_CheckType, /*MI*/0, /*Op*/3, /*Type*/GILLT_v8s16,
        GIM_CheckType, /*MI*/0, /*Op*/4, /*Type*/GILLT_v4s32,
        GIM_CheckType, /*MI*/0, /*Op*/5, /*Type*/GILLT_s32,
        GIM_CheckRegBankForClass, /*MI*/0, /*Op*/0, /*RC*/GIMT_Encode2(AMDGPU::VReg_128RegClassID),
        GIM_CheckComplexPattern, /*MI*/0, /*Op*/2, /*Renderer*/GIMT_Encode2(0), GIMT_Encode2(GICP_gi_wmmamodsf16Neg),
        GIM_CheckComplexPattern, /*MI*/0, /*Op*/3, /*Renderer*/GIMT_Encode2(1), GIMT_Encode2(GICP_gi_wmmamodsf16Neg),
        GIM_CheckComplexPattern, /*MI*/0, /*Op*/5, /*Renderer*/GIMT_Encode2(2), GIMT_Encode2(GICP_gi_swmmacindex8),
        // (intrinsic_wo_chain:{ *:[v4f32] } 2789:{ *:[iPTR] }, (WMMAModsF16Neg:{ *:[v4f16] } v4f16:{ *:[v4f16] }:$src0, i32:{ *:[i32] }:$src0_modifiers), (WMMAModsF16Neg:{ *:[v8f16] } v8f16:{ *:[v8f16] }:$src1, i32:{ *:[i32] }:$src1_modifiers), v4f32:{ *:[v4f32] }:$srcTiedDef, (SWMMACIndex8:{ *:[i32] } i32:{ *:[i32] }:$src2, i32:{ *:[i32] }:$index_key_8bit))  =>  (V_SWMMAC_F32_16X16X32_F16_w64_twoaddr:{ *:[v4f32] } i32:{ *:[i32] }:$src0_modifiers, v4f16:{ *:[v4f16] }:$src0, i32:{ *:[i32] }:$src1_modifiers, v8f16:{ *:[v8f16] }:$src1, v4f32:{ *:[v4f32] }:$srcTiedDef, i32:{ *:[i32] }:$src2, i32:{ *:[i32] }:$index_key_8bit)
        GIR_BuildMI, /*InsnID*/0, /*Opcode*/GIMT_Encode2(AMDGPU::V_SWMMAC_F32_16X16X32_F16_w64_twoaddr),
        GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/0, // DstI[vdst]
        GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/1, // src0_modifiers
        GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/0, // src0
        GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(1), /*SubOperand*/1, // src1_modifiers
        GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(1), /*SubOperand*/0, // src1
        GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/4, // srcTiedDef
        GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(2), /*SubOperand*/0, // src2
        GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(2), /*SubOperand*/1, // index_key_8bit
        GIR_AddImm8, /*InsnID*/0, /*Imm*/0,
        GIR_AddImm8, /*InsnID*/0, /*Imm*/0,
        GIR_ConstrainSelectedInstOperands, /*InsnID*/0,
        GIR_EraseFromParent, /*InsnID*/0,
        // GIR_Coverage, 2390,
        GIR_Done,
      // Label 3474: @225103
      GIM_Try, /*On fail goto*//*Label 3475*/ GIMT_Encode4(225215), // Rule ID 2392 //
        GIM_CheckFeatures, GIMT_Encode2(GIFBS_isGFX12Plus_isWave64),
        GIM_CheckIntrinsicID, /*MI*/0, /*Op*/1, GIMT_Encode2(Intrinsic::amdgcn_swmmac_f16_16x16x32_f16),
        GIM_CheckType, /*MI*/0, /*Op*/0, /*Type*/GILLT_v4s16,
        GIM_CheckType, /*MI*/0, /*Op*/2, /*Type*/GILLT_v4s16,
        GIM_CheckType, /*MI*/0, /*Op*/3, /*Type*/GILLT_v8s16,
        GIM_CheckType, /*MI*/0, /*Op*/4, /*Type*/GILLT_v4s16,
        GIM_CheckType, /*MI*/0, /*Op*/5, /*Type*/GILLT_s32,
        GIM_CheckRegBankForClass, /*MI*/0, /*Op*/0, /*RC*/GIMT_Encode2(AMDGPU::VReg_64RegClassID),
        GIM_CheckComplexPattern, /*MI*/0, /*Op*/2, /*Renderer*/GIMT_Encode2(0), GIMT_Encode2(GICP_gi_wmmamodsf16Neg),
        GIM_CheckComplexPattern, /*MI*/0, /*Op*/3, /*Renderer*/GIMT_Encode2(1), GIMT_Encode2(GICP_gi_wmmamodsf16Neg),
        GIM_CheckComplexPattern, /*MI*/0, /*Op*/5, /*Renderer*/GIMT_Encode2(2), GIMT_Encode2(GICP_gi_swmmacindex8),
        // (intrinsic_wo_chain:{ *:[v4f16] } 2785:{ *:[iPTR] }, (WMMAModsF16Neg:{ *:[v4f16] } v4f16:{ *:[v4f16] }:$src0, i32:{ *:[i32] }:$src0_modifiers), (WMMAModsF16Neg:{ *:[v8f16] } v8f16:{ *:[v8f16] }:$src1, i32:{ *:[i32] }:$src1_modifiers), v4f16:{ *:[v4f16] }:$srcTiedDef, (SWMMACIndex8:{ *:[i32] } i32:{ *:[i32] }:$src2, i32:{ *:[i32] }:$index_key_8bit))  =>  (V_SWMMAC_F16_16X16X32_F16_w64_twoaddr:{ *:[v4f16] } i32:{ *:[i32] }:$src0_modifiers, v4f16:{ *:[v4f16] }:$src0, i32:{ *:[i32] }:$src1_modifiers, v8f16:{ *:[v8f16] }:$src1, v4f16:{ *:[v4f16] }:$srcTiedDef, i32:{ *:[i32] }:$src2, i32:{ *:[i32] }:$index_key_8bit)
        GIR_BuildMI, /*InsnID*/0, /*Opcode*/GIMT_Encode2(AMDGPU::V_SWMMAC_F16_16X16X32_F16_w64_twoaddr),
        GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/0, // DstI[vdst]
        GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/1, // src0_modifiers
        GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/0, // src0
        GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(1), /*SubOperand*/1, // src1_modifiers
        GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(1), /*SubOperand*/0, // src1
        GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/4, // srcTiedDef
        GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(2), /*SubOperand*/0, // src2
        GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(2), /*SubOperand*/1, // index_key_8bit
        GIR_AddImm8, /*InsnID*/0, /*Imm*/0,
        GIR_AddImm8, /*InsnID*/0, /*Imm*/0,
        GIR_ConstrainSelectedInstOperands, /*InsnID*/0,
        GIR_EraseFromParent, /*InsnID*/0,
        // GIR_Coverage, 2392,
        GIR_Done,
      // Label 3475: @225215
      GIM_Try, /*On fail goto*//*Label 3476*/ GIMT_Encode4(225308), // Rule ID 2342 //
        GIM_CheckFeatures, GIMT_Encode2(GIFBS_isGFX12Plus_isWave32),
        GIM_CheckIntrinsicID, /*MI*/0, /*Op*/1, GIMT_Encode2(Intrinsic::amdgcn_wmma_bf16_16x16x16_bf16),
        GIM_CheckType, /*MI*/0, /*Op*/0, /*Type*/GILLT_v8s16,
        GIM_CheckType, /*MI*/0, /*Op*/2, /*Type*/GILLT_v8s16,
        GIM_CheckType, /*MI*/0, /*Op*/3, /*Type*/GILLT_v8s16,
        GIM_CheckType, /*MI*/0, /*Op*/4, /*Type*/GILLT_v8s16,
        GIM_CheckRegBankForClass, /*MI*/0, /*Op*/0, /*RC*/GIMT_Encode2(AMDGPU::VReg_128RegClassID),
        // MIs[0] Operand 5
        GIM_CheckLiteralInt, /*MI*/0, /*Op*/5, GIMT_Encode8(0),
        GIM_CheckComplexPattern, /*MI*/0, /*Op*/4, /*Renderer*/GIMT_Encode2(0), GIMT_Encode2(GICP_gi_wmmavisrc),
        // (intrinsic_wo_chain:{ *:[v8i16] } 2809:{ *:[iPTR] }, v8i16:{ *:[v8i16] }:$src0, v8i16:{ *:[v8i16] }:$src1, (WMMAVISrc:{ *:[v8i16] } v8i16:{ *:[v8i16] }:$src2), 0:{ *:[i1] })  =>  (V_WMMA_BF16_16X16X16_BF16_w32_threeaddr:{ *:[v8i16] } 8:{ *:[i32] }, v8i16:{ *:[v8i16] }:$src0, 8:{ *:[i32] }, v8i16:{ *:[v8i16] }:$src1, 8:{ *:[i32] }, v8i16:{ *:[v8i16] }:$src2)
        GIR_BuildMI, /*InsnID*/0, /*Opcode*/GIMT_Encode2(AMDGPU::V_WMMA_BF16_16X16X16_BF16_w32_threeaddr),
        GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/0, // DstI[vdst]
        GIR_AddImm8, /*InsnID*/0, /*Imm*/8,
        GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/2, // src0
        GIR_AddImm8, /*InsnID*/0, /*Imm*/8,
        GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/3, // src1
        GIR_AddImm8, /*InsnID*/0, /*Imm*/8,
        GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/0, // src2
        GIR_AddImm8, /*InsnID*/0, /*Imm*/0,
        GIR_AddImm8, /*InsnID*/0, /*Imm*/0,
        GIR_ConstrainSelectedInstOperands, /*InsnID*/0,
        GIR_EraseFromParent, /*InsnID*/0,
        // GIR_Coverage, 2342,
        GIR_Done,
      // Label 3476: @225308
      GIM_Try, /*On fail goto*//*Label 3477*/ GIMT_Encode4(225401), // Rule ID 2375 //
        GIM_CheckFeatures, GIMT_Encode2(GIFBS_isGFX12Plus_isWave64),
        GIM_CheckIntrinsicID, /*MI*/0, /*Op*/1, GIMT_Encode2(Intrinsic::amdgcn_wmma_bf16_16x16x16_bf16),
        GIM_CheckType, /*MI*/0, /*Op*/0, /*Type*/GILLT_v4s16,
        GIM_CheckType, /*MI*/0, /*Op*/2, /*Type*/GILLT_v4s16,
        GIM_CheckType, /*MI*/0, /*Op*/3, /*Type*/GILLT_v4s16,
        GIM_CheckType, /*MI*/0, /*Op*/4, /*Type*/GILLT_v4s16,
        GIM_CheckRegBankForClass, /*MI*/0, /*Op*/0, /*RC*/GIMT_Encode2(AMDGPU::VReg_64RegClassID),
        // MIs[0] Operand 5
        GIM_CheckLiteralInt, /*MI*/0, /*Op*/5, GIMT_Encode8(0),
        GIM_CheckComplexPattern, /*MI*/0, /*Op*/4, /*Renderer*/GIMT_Encode2(0), GIMT_Encode2(GICP_gi_wmmavisrc),
        // (intrinsic_wo_chain:{ *:[v4i16] } 2809:{ *:[iPTR] }, v4i16:{ *:[v4i16] }:$src0, v4i16:{ *:[v4i16] }:$src1, (WMMAVISrc:{ *:[v4i16] } v4i16:{ *:[v4i16] }:$src2), 0:{ *:[i1] })  =>  (V_WMMA_BF16_16X16X16_BF16_w64_threeaddr:{ *:[v4i16] } 8:{ *:[i32] }, v4i16:{ *:[v4i16] }:$src0, 8:{ *:[i32] }, v4i16:{ *:[v4i16] }:$src1, 8:{ *:[i32] }, v4i16:{ *:[v4i16] }:$src2)
        GIR_BuildMI, /*InsnID*/0, /*Opcode*/GIMT_Encode2(AMDGPU::V_WMMA_BF16_16X16X16_BF16_w64_threeaddr),
        GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/0, // DstI[vdst]
        GIR_AddImm8, /*InsnID*/0, /*Imm*/8,
        GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/2, // src0
        GIR_AddImm8, /*InsnID*/0, /*Imm*/8,
        GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/3, // src1
        GIR_AddImm8, /*InsnID*/0, /*Imm*/8,
        GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/0, // src2
        GIR_AddImm8, /*InsnID*/0, /*Imm*/0,
        GIR_AddImm8, /*InsnID*/0, /*Imm*/0,
        GIR_ConstrainSelectedInstOperands, /*InsnID*/0,
        GIR_EraseFromParent, /*InsnID*/0,
        // GIR_Coverage, 2375,
        GIR_Done,
      // Label 3477: @225401
      GIM_Try, /*On fail goto*//*Label 3478*/ GIMT_Encode4(225493), // Rule ID 2358 //
        GIM_CheckFeatures, GIMT_Encode2(GIFBS_isGFX12Plus_isWave32),
        GIM_CheckIntrinsicID, /*MI*/0, /*Op*/1, GIMT_Encode2(Intrinsic::amdgcn_swmmac_f32_16x16x32_bf16),
        GIM_CheckType, /*MI*/0, /*Op*/0, /*Type*/GILLT_v8s32,
        GIM_CheckType, /*MI*/0, /*Op*/2, /*Type*/GILLT_v8s16,
        GIM_CheckType, /*MI*/0, /*Op*/3, /*Type*/GILLT_v16s16,
        GIM_CheckType, /*MI*/0, /*Op*/4, /*Type*/GILLT_v8s32,
        GIM_CheckType, /*MI*/0, /*Op*/5, /*Type*/GILLT_s32,
        GIM_CheckRegBankForClass, /*MI*/0, /*Op*/0, /*RC*/GIMT_Encode2(AMDGPU::VReg_256RegClassID),
        GIM_CheckComplexPattern, /*MI*/0, /*Op*/5, /*Renderer*/GIMT_Encode2(0), GIMT_Encode2(GICP_gi_swmmacindex16),
        // (intrinsic_wo_chain:{ *:[v8f32] } 2786:{ *:[iPTR] }, v8i16:{ *:[v8i16] }:$src0, v16i16:{ *:[v16i16] }:$src1, v8f32:{ *:[v8f32] }:$srcTiedDef, (SWMMACIndex16:{ *:[i32] } i32:{ *:[i32] }:$src2, i32:{ *:[i32] }:$index_key_16bit))  =>  (V_SWMMAC_F32_16X16X32_BF16_w32_twoaddr:{ *:[v8f32] } 8:{ *:[i32] }, v8i16:{ *:[v8i16] }:$src0, 8:{ *:[i32] }, v16i16:{ *:[v16i16] }:$src1, v8f32:{ *:[v8f32] }:$srcTiedDef, i32:{ *:[i32] }:$src2, i32:{ *:[i32] }:$index_key_16bit)
        GIR_BuildMI, /*InsnID*/0, /*Opcode*/GIMT_Encode2(AMDGPU::V_SWMMAC_F32_16X16X32_BF16_w32_twoaddr),
        GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/0, // DstI[vdst]
        GIR_AddImm8, /*InsnID*/0, /*Imm*/8,
        GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/2, // src0
        GIR_AddImm8, /*InsnID*/0, /*Imm*/8,
        GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/3, // src1
        GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/4, // srcTiedDef
        GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/0, // src2
        GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/1, // index_key_16bit
        GIR_AddImm8, /*InsnID*/0, /*Imm*/0,
        GIR_AddImm8, /*InsnID*/0, /*Imm*/0,
        GIR_ConstrainSelectedInstOperands, /*InsnID*/0,
        GIR_EraseFromParent, /*InsnID*/0,
        // GIR_Coverage, 2358,
        GIR_Done,
      // Label 3478: @225493
      GIM_Try, /*On fail goto*//*Label 3479*/ GIMT_Encode4(225585), // Rule ID 2360 //
        GIM_CheckFeatures, GIMT_Encode2(GIFBS_isGFX12Plus_isWave32),
        GIM_CheckIntrinsicID, /*MI*/0, /*Op*/1, GIMT_Encode2(Intrinsic::amdgcn_swmmac_bf16_16x16x32_bf16),
        GIM_CheckType, /*MI*/0, /*Op*/0, /*Type*/GILLT_v8s16,
        GIM_CheckType, /*MI*/0, /*Op*/2, /*Type*/GILLT_v8s16,
        GIM_CheckType, /*MI*/0, /*Op*/3, /*Type*/GILLT_v16s16,
        GIM_CheckType, /*MI*/0, /*Op*/4, /*Type*/GILLT_v8s16,
        GIM_CheckType, /*MI*/0, /*Op*/5, /*Type*/GILLT_s32,
        GIM_CheckRegBankForClass, /*MI*/0, /*Op*/0, /*RC*/GIMT_Encode2(AMDGPU::VReg_128RegClassID),
        GIM_CheckComplexPattern, /*MI*/0, /*Op*/5, /*Renderer*/GIMT_Encode2(0), GIMT_Encode2(GICP_gi_swmmacindex16),
        // (intrinsic_wo_chain:{ *:[v8i16] } 2784:{ *:[iPTR] }, v8i16:{ *:[v8i16] }:$src0, v16i16:{ *:[v16i16] }:$src1, v8i16:{ *:[v8i16] }:$srcTiedDef, (SWMMACIndex16:{ *:[i32] } i32:{ *:[i32] }:$src2, i32:{ *:[i32] }:$index_key_16bit))  =>  (V_SWMMAC_BF16_16X16X32_BF16_w32_twoaddr:{ *:[v8i16] } 8:{ *:[i32] }, v8i16:{ *:[v8i16] }:$src0, 8:{ *:[i32] }, v16i16:{ *:[v16i16] }:$src1, v8i16:{ *:[v8i16] }:$srcTiedDef, i32:{ *:[i32] }:$src2, i32:{ *:[i32] }:$index_key_16bit)
        GIR_BuildMI, /*InsnID*/0, /*Opcode*/GIMT_Encode2(AMDGPU::V_SWMMAC_BF16_16X16X32_BF16_w32_twoaddr),
        GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/0, // DstI[vdst]
        GIR_AddImm8, /*InsnID*/0, /*Imm*/8,
        GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/2, // src0
        GIR_AddImm8, /*InsnID*/0, /*Imm*/8,
        GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/3, // src1
        GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/4, // srcTiedDef
        GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/0, // src2
        GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/1, // index_key_16bit
        GIR_AddImm8, /*InsnID*/0, /*Imm*/0,
        GIR_AddImm8, /*InsnID*/0, /*Imm*/0,
        GIR_ConstrainSelectedInstOperands, /*InsnID*/0,
        GIR_EraseFromParent, /*InsnID*/0,
        // GIR_Coverage, 2360,
        GIR_Done,
      // Label 3479: @225585
      GIM_Try, /*On fail goto*//*Label 3480*/ GIMT_Encode4(225665), // Rule ID 2364 //
        GIM_CheckFeatures, GIMT_Encode2(GIFBS_isGFX12Plus_isWave32),
        GIM_CheckIntrinsicID, /*MI*/0, /*Op*/1, GIMT_Encode2(Intrinsic::amdgcn_swmmac_f32_16x16x32_fp8_fp8),
        GIM_CheckType, /*MI*/0, /*Op*/0, /*Type*/GILLT_v8s32,
        GIM_CheckType, /*MI*/0, /*Op*/2, /*Type*/GILLT_v2s32,
        GIM_CheckType, /*MI*/0, /*Op*/3, /*Type*/GILLT_v4s32,
        GIM_CheckType, /*MI*/0, /*Op*/4, /*Type*/GILLT_v8s32,
        GIM_CheckType, /*MI*/0, /*Op*/5, /*Type*/GILLT_s32,
        GIM_CheckRegBankForClass, /*MI*/0, /*Op*/0, /*RC*/GIMT_Encode2(AMDGPU::VReg_256RegClassID),
        GIM_CheckComplexPattern, /*MI*/0, /*Op*/5, /*Renderer*/GIMT_Encode2(0), GIMT_Encode2(GICP_gi_swmmacindex16),
        // (intrinsic_wo_chain:{ *:[v8f32] } 2791:{ *:[iPTR] }, v2i32:{ *:[v2i32] }:$src0, v4i32:{ *:[v4i32] }:$src1, v8f32:{ *:[v8f32] }:$srcTiedDef, (SWMMACIndex16:{ *:[i32] } i32:{ *:[i32] }:$src2, i32:{ *:[i32] }:$index_key_16bit))  =>  (V_SWMMAC_F32_16X16X32_FP8_FP8_w32_twoaddr:{ *:[v8f32] } v2i32:{ *:[v2i32] }:$src0, v4i32:{ *:[v4i32] }:$src1, v8f32:{ *:[v8f32] }:$srcTiedDef, i32:{ *:[i32] }:$src2, i32:{ *:[i32] }:$index_key_16bit)
        GIR_BuildMI, /*InsnID*/0, /*Opcode*/GIMT_Encode2(AMDGPU::V_SWMMAC_F32_16X16X32_FP8_FP8_w32_twoaddr),
        GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/0, // DstI[vdst]
        GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/2, // src0
        GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/3, // src1
        GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/4, // srcTiedDef
        GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/0, // src2
        GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/1, // index_key_16bit
        GIR_ConstrainSelectedInstOperands, /*InsnID*/0,
        GIR_EraseFromParent, /*InsnID*/0,
        // GIR_Coverage, 2364,
        GIR_Done,
      // Label 3480: @225665
      GIM_Try, /*On fail goto*//*Label 3481*/ GIMT_Encode4(225745), // Rule ID 2365 //
        GIM_CheckFeatures, GIMT_Encode2(GIFBS_isGFX12Plus_isWave32),
        GIM_CheckIntrinsicID, /*MI*/0, /*Op*/1, GIMT_Encode2(Intrinsic::amdgcn_swmmac_f32_16x16x32_fp8_bf8),
        GIM_CheckType, /*MI*/0, /*Op*/0, /*Type*/GILLT_v8s32,
        GIM_CheckType, /*MI*/0, /*Op*/2, /*Type*/GILLT_v2s32,
        GIM_CheckType, /*MI*/0, /*Op*/3, /*Type*/GILLT_v4s32,
        GIM_CheckType, /*MI*/0, /*Op*/4, /*Type*/GILLT_v8s32,
        GIM_CheckType, /*MI*/0, /*Op*/5, /*Type*/GILLT_s32,
        GIM_CheckRegBankForClass, /*MI*/0, /*Op*/0, /*RC*/GIMT_Encode2(AMDGPU::VReg_256RegClassID),
        GIM_CheckComplexPattern, /*MI*/0, /*Op*/5, /*Renderer*/GIMT_Encode2(0), GIMT_Encode2(GICP_gi_swmmacindex16),
        // (intrinsic_wo_chain:{ *:[v8f32] } 2790:{ *:[iPTR] }, v2i32:{ *:[v2i32] }:$src0, v4i32:{ *:[v4i32] }:$src1, v8f32:{ *:[v8f32] }:$srcTiedDef, (SWMMACIndex16:{ *:[i32] } i32:{ *:[i32] }:$src2, i32:{ *:[i32] }:$index_key_16bit))  =>  (V_SWMMAC_F32_16X16X32_FP8_BF8_w32_twoaddr:{ *:[v8f32] } v2i32:{ *:[v2i32] }:$src0, v4i32:{ *:[v4i32] }:$src1, v8f32:{ *:[v8f32] }:$srcTiedDef, i32:{ *:[i32] }:$src2, i32:{ *:[i32] }:$index_key_16bit)
        GIR_BuildMI, /*InsnID*/0, /*Opcode*/GIMT_Encode2(AMDGPU::V_SWMMAC_F32_16X16X32_FP8_BF8_w32_twoaddr),
        GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/0, // DstI[vdst]
        GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/2, // src0
        GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/3, // src1
        GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/4, // srcTiedDef
        GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/0, // src2
        GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/1, // index_key_16bit
        GIR_ConstrainSelectedInstOperands, /*InsnID*/0,
        GIR_EraseFromParent, /*InsnID*/0,
        // GIR_Coverage, 2365,
        GIR_Done,
      // Label 3481: @225745
      GIM_Try, /*On fail goto*//*Label 3482*/ GIMT_Encode4(225825), // Rule ID 2366 //
        GIM_CheckFeatures, GIMT_Encode2(GIFBS_isGFX12Plus_isWave32),
        GIM_CheckIntrinsicID, /*MI*/0, /*Op*/1, GIMT_Encode2(Intrinsic::amdgcn_swmmac_f32_16x16x32_bf8_fp8),
        GIM_CheckType, /*MI*/0, /*Op*/0, /*Type*/GILLT_v8s32,
        GIM_CheckType, /*MI*/0, /*Op*/2, /*Type*/GILLT_v2s32,
        GIM_CheckType, /*MI*/0, /*Op*/3, /*Type*/GILLT_v4s32,
        GIM_CheckType, /*MI*/0, /*Op*/4, /*Type*/GILLT_v8s32,
        GIM_CheckType, /*MI*/0, /*Op*/5, /*Type*/GILLT_s32,
        GIM_CheckRegBankForClass, /*MI*/0, /*Op*/0, /*RC*/GIMT_Encode2(AMDGPU::VReg_256RegClassID),
        GIM_CheckComplexPattern, /*MI*/0, /*Op*/5, /*Renderer*/GIMT_Encode2(0), GIMT_Encode2(GICP_gi_swmmacindex16),
        // (intrinsic_wo_chain:{ *:[v8f32] } 2788:{ *:[iPTR] }, v2i32:{ *:[v2i32] }:$src0, v4i32:{ *:[v4i32] }:$src1, v8f32:{ *:[v8f32] }:$srcTiedDef, (SWMMACIndex16:{ *:[i32] } i32:{ *:[i32] }:$src2, i32:{ *:[i32] }:$index_key_16bit))  =>  (V_SWMMAC_F32_16X16X32_BF8_FP8_w32_twoaddr:{ *:[v8f32] } v2i32:{ *:[v2i32] }:$src0, v4i32:{ *:[v4i32] }:$src1, v8f32:{ *:[v8f32] }:$srcTiedDef, i32:{ *:[i32] }:$src2, i32:{ *:[i32] }:$index_key_16bit)
        GIR_BuildMI, /*InsnID*/0, /*Opcode*/GIMT_Encode2(AMDGPU::V_SWMMAC_F32_16X16X32_BF8_FP8_w32_twoaddr),
        GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/0, // DstI[vdst]
        GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/2, // src0
        GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/3, // src1
        GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/4, // srcTiedDef
        GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/0, // src2
        GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/1, // index_key_16bit
        GIR_ConstrainSelectedInstOperands, /*InsnID*/0,
        GIR_EraseFromParent, /*InsnID*/0,
        // GIR_Coverage, 2366,
        GIR_Done,
      // Label 3482: @225825
      GIM_Try, /*On fail goto*//*Label 3483*/ GIMT_Encode4(225905), // Rule ID 2367 //
        GIM_CheckFeatures, GIMT_Encode2(GIFBS_isGFX12Plus_isWave32),
        GIM_CheckIntrinsicID, /*MI*/0, /*Op*/1, GIMT_Encode2(Intrinsic::amdgcn_swmmac_f32_16x16x32_bf8_bf8),
        GIM_CheckType, /*MI*/0, /*Op*/0, /*Type*/GILLT_v8s32,
        GIM_CheckType, /*MI*/0, /*Op*/2, /*Type*/GILLT_v2s32,
        GIM_CheckType, /*MI*/0, /*Op*/3, /*Type*/GILLT_v4s32,
        GIM_CheckType, /*MI*/0, /*Op*/4, /*Type*/GILLT_v8s32,
        GIM_CheckType, /*MI*/0, /*Op*/5, /*Type*/GILLT_s32,
        GIM_CheckRegBankForClass, /*MI*/0, /*Op*/0, /*RC*/GIMT_Encode2(AMDGPU::VReg_256RegClassID),
        GIM_CheckComplexPattern, /*MI*/0, /*Op*/5, /*Renderer*/GIMT_Encode2(0), GIMT_Encode2(GICP_gi_swmmacindex16),
        // (intrinsic_wo_chain:{ *:[v8f32] } 2787:{ *:[iPTR] }, v2i32:{ *:[v2i32] }:$src0, v4i32:{ *:[v4i32] }:$src1, v8f32:{ *:[v8f32] }:$srcTiedDef, (SWMMACIndex16:{ *:[i32] } i32:{ *:[i32] }:$src2, i32:{ *:[i32] }:$index_key_16bit))  =>  (V_SWMMAC_F32_16X16X32_BF8_BF8_w32_twoaddr:{ *:[v8f32] } v2i32:{ *:[v2i32] }:$src0, v4i32:{ *:[v4i32] }:$src1, v8f32:{ *:[v8f32] }:$srcTiedDef, i32:{ *:[i32] }:$src2, i32:{ *:[i32] }:$index_key_16bit)
        GIR_BuildMI, /*InsnID*/0, /*Opcode*/GIMT_Encode2(AMDGPU::V_SWMMAC_F32_16X16X32_BF8_BF8_w32_twoaddr),
        GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/0, // DstI[vdst]
        GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/2, // src0
        GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/3, // src1
        GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/4, // srcTiedDef
        GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/0, // src2
        GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/1, // index_key_16bit
        GIR_ConstrainSelectedInstOperands, /*InsnID*/0,
        GIR_EraseFromParent, /*InsnID*/0,
        // GIR_Coverage, 2367,
        GIR_Done,
      // Label 3483: @225905
      GIM_Try, /*On fail goto*//*Label 3484*/ GIMT_Encode4(225997), // Rule ID 2391 //
        GIM_CheckFeatures, GIMT_Encode2(GIFBS_isGFX12Plus_isWave64),
        GIM_CheckIntrinsicID, /*MI*/0, /*Op*/1, GIMT_Encode2(Intrinsic::amdgcn_swmmac_f32_16x16x32_bf16),
        GIM_CheckType, /*MI*/0, /*Op*/0, /*Type*/GILLT_v4s32,
        GIM_CheckType, /*MI*/0, /*Op*/2, /*Type*/GILLT_v4s16,
        GIM_CheckType, /*MI*/0, /*Op*/3, /*Type*/GILLT_v8s16,
        GIM_CheckType, /*MI*/0, /*Op*/4, /*Type*/GILLT_v4s32,
        GIM_CheckType, /*MI*/0, /*Op*/5, /*Type*/GILLT_s32,
        GIM_CheckRegBankForClass, /*MI*/0, /*Op*/0, /*RC*/GIMT_Encode2(AMDGPU::VReg_128RegClassID),
        GIM_CheckComplexPattern, /*MI*/0, /*Op*/5, /*Renderer*/GIMT_Encode2(0), GIMT_Encode2(GICP_gi_swmmacindex8),
        // (intrinsic_wo_chain:{ *:[v4f32] } 2786:{ *:[iPTR] }, v4i16:{ *:[v4i16] }:$src0, v8i16:{ *:[v8i16] }:$src1, v4f32:{ *:[v4f32] }:$srcTiedDef, (SWMMACIndex8:{ *:[i32] } i32:{ *:[i32] }:$src2, i32:{ *:[i32] }:$index_key_8bit))  =>  (V_SWMMAC_F32_16X16X32_BF16_w64_twoaddr:{ *:[v4f32] } 8:{ *:[i32] }, v4i16:{ *:[v4i16] }:$src0, 8:{ *:[i32] }, v8i16:{ *:[v8i16] }:$src1, v4f32:{ *:[v4f32] }:$srcTiedDef, i32:{ *:[i32] }:$src2, i32:{ *:[i32] }:$index_key_8bit)
        GIR_BuildMI, /*InsnID*/0, /*Opcode*/GIMT_Encode2(AMDGPU::V_SWMMAC_F32_16X16X32_BF16_w64_twoaddr),
        GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/0, // DstI[vdst]
        GIR_AddImm8, /*InsnID*/0, /*Imm*/8,
        GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/2, // src0
        GIR_AddImm8, /*InsnID*/0, /*Imm*/8,
        GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/3, // src1
        GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/4, // srcTiedDef
        GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/0, // src2
        GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/1, // index_key_8bit
        GIR_AddImm8, /*InsnID*/0, /*Imm*/0,
        GIR_AddImm8, /*InsnID*/0, /*Imm*/0,
        GIR_ConstrainSelectedInstOperands, /*InsnID*/0,
        GIR_EraseFromParent, /*InsnID*/0,
        // GIR_Coverage, 2391,
        GIR_Done,
      // Label 3484: @225997
      GIM_Try, /*On fail goto*//*Label 3485*/ GIMT_Encode4(226089), // Rule ID 2393 //
        GIM_CheckFeatures, GIMT_Encode2(GIFBS_isGFX12Plus_isWave64),
        GIM_CheckIntrinsicID, /*MI*/0, /*Op*/1, GIMT_Encode2(Intrinsic::amdgcn_swmmac_bf16_16x16x32_bf16),
        GIM_CheckType, /*MI*/0, /*Op*/0, /*Type*/GILLT_v4s16,
        GIM_CheckType, /*MI*/0, /*Op*/2, /*Type*/GILLT_v4s16,
        GIM_CheckType, /*MI*/0, /*Op*/3, /*Type*/GILLT_v8s16,
        GIM_CheckType, /*MI*/0, /*Op*/4, /*Type*/GILLT_v4s16,
        GIM_CheckType, /*MI*/0, /*Op*/5, /*Type*/GILLT_s32,
        GIM_CheckRegBankForClass, /*MI*/0, /*Op*/0, /*RC*/GIMT_Encode2(AMDGPU::VReg_64RegClassID),
        GIM_CheckComplexPattern, /*MI*/0, /*Op*/5, /*Renderer*/GIMT_Encode2(0), GIMT_Encode2(GICP_gi_swmmacindex8),
        // (intrinsic_wo_chain:{ *:[v4i16] } 2784:{ *:[iPTR] }, v4i16:{ *:[v4i16] }:$src0, v8i16:{ *:[v8i16] }:$src1, v4i16:{ *:[v4i16] }:$srcTiedDef, (SWMMACIndex8:{ *:[i32] } i32:{ *:[i32] }:$src2, i32:{ *:[i32] }:$index_key_8bit))  =>  (V_SWMMAC_BF16_16X16X32_BF16_w64_twoaddr:{ *:[v4i16] } 8:{ *:[i32] }, v4i16:{ *:[v4i16] }:$src0, 8:{ *:[i32] }, v8i16:{ *:[v8i16] }:$src1, v4i16:{ *:[v4i16] }:$srcTiedDef, i32:{ *:[i32] }:$src2, i32:{ *:[i32] }:$index_key_8bit)
        GIR_BuildMI, /*InsnID*/0, /*Opcode*/GIMT_Encode2(AMDGPU::V_SWMMAC_BF16_16X16X32_BF16_w64_twoaddr),
        GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/0, // DstI[vdst]
        GIR_AddImm8, /*InsnID*/0, /*Imm*/8,
        GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/2, // src0
        GIR_AddImm8, /*InsnID*/0, /*Imm*/8,
        GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/3, // src1
        GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/4, // srcTiedDef
        GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/0, // src2
        GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/1, // index_key_8bit
        GIR_AddImm8, /*InsnID*/0, /*Imm*/0,
        GIR_AddImm8, /*InsnID*/0, /*Imm*/0,
        GIR_ConstrainSelectedInstOperands, /*InsnID*/0,
        GIR_EraseFromParent, /*InsnID*/0,
        // GIR_Coverage, 2393,
        GIR_Done,
      // Label 3485: @226089
      GIM_Try, /*On fail goto*//*Label 3486*/ GIMT_Encode4(226169), // Rule ID 2397 //
        GIM_CheckFeatures, GIMT_Encode2(GIFBS_isGFX12Plus_isWave64),
        GIM_CheckIntrinsicID, /*MI*/0, /*Op*/1, GIMT_Encode2(Intrinsic::amdgcn_swmmac_f32_16x16x32_fp8_fp8),
        GIM_CheckType, /*MI*/0, /*Op*/0, /*Type*/GILLT_v4s32,
        GIM_CheckType, /*MI*/0, /*Op*/2, /*Type*/GILLT_s32,
        GIM_CheckType, /*MI*/0, /*Op*/3, /*Type*/GILLT_v2s32,
        GIM_CheckType, /*MI*/0, /*Op*/4, /*Type*/GILLT_v4s32,
        GIM_CheckType, /*MI*/0, /*Op*/5, /*Type*/GILLT_s32,
        GIM_CheckRegBankForClass, /*MI*/0, /*Op*/0, /*RC*/GIMT_Encode2(AMDGPU::VReg_128RegClassID),
        GIM_CheckComplexPattern, /*MI*/0, /*Op*/5, /*Renderer*/GIMT_Encode2(0), GIMT_Encode2(GICP_gi_swmmacindex8),
        // (intrinsic_wo_chain:{ *:[v4f32] } 2791:{ *:[iPTR] }, i32:{ *:[i32] }:$src0, v2i32:{ *:[v2i32] }:$src1, v4f32:{ *:[v4f32] }:$srcTiedDef, (SWMMACIndex8:{ *:[i32] } i32:{ *:[i32] }:$src2, i32:{ *:[i32] }:$index_key_8bit))  =>  (V_SWMMAC_F32_16X16X32_FP8_FP8_w64_twoaddr:{ *:[v4f32] } i32:{ *:[i32] }:$src0, v2i32:{ *:[v2i32] }:$src1, v4f32:{ *:[v4f32] }:$srcTiedDef, i32:{ *:[i32] }:$src2, i32:{ *:[i32] }:$index_key_8bit)
        GIR_BuildMI, /*InsnID*/0, /*Opcode*/GIMT_Encode2(AMDGPU::V_SWMMAC_F32_16X16X32_FP8_FP8_w64_twoaddr),
        GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/0, // DstI[vdst]
        GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/2, // src0
        GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/3, // src1
        GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/4, // srcTiedDef
        GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/0, // src2
        GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/1, // index_key_8bit
        GIR_ConstrainSelectedInstOperands, /*InsnID*/0,
        GIR_EraseFromParent, /*InsnID*/0,
        // GIR_Coverage, 2397,
        GIR_Done,
      // Label 3486: @226169
      GIM_Try, /*On fail goto*//*Label 3487*/ GIMT_Encode4(226249), // Rule ID 2398 //
        GIM_CheckFeatures, GIMT_Encode2(GIFBS_isGFX12Plus_isWave64),
        GIM_CheckIntrinsicID, /*MI*/0, /*Op*/1, GIMT_Encode2(Intrinsic::amdgcn_swmmac_f32_16x16x32_fp8_bf8),
        GIM_CheckType, /*MI*/0, /*Op*/0, /*Type*/GILLT_v4s32,
        GIM_CheckType, /*MI*/0, /*Op*/2, /*Type*/GILLT_s32,
        GIM_CheckType, /*MI*/0, /*Op*/3, /*Type*/GILLT_v2s32,
        GIM_CheckType, /*MI*/0, /*Op*/4, /*Type*/GILLT_v4s32,
        GIM_CheckType, /*MI*/0, /*Op*/5, /*Type*/GILLT_s32,
        GIM_CheckRegBankForClass, /*MI*/0, /*Op*/0, /*RC*/GIMT_Encode2(AMDGPU::VReg_128RegClassID),
        GIM_CheckComplexPattern, /*MI*/0, /*Op*/5, /*Renderer*/GIMT_Encode2(0), GIMT_Encode2(GICP_gi_swmmacindex8),
        // (intrinsic_wo_chain:{ *:[v4f32] } 2790:{ *:[iPTR] }, i32:{ *:[i32] }:$src0, v2i32:{ *:[v2i32] }:$src1, v4f32:{ *:[v4f32] }:$srcTiedDef, (SWMMACIndex8:{ *:[i32] } i32:{ *:[i32] }:$src2, i32:{ *:[i32] }:$index_key_8bit))  =>  (V_SWMMAC_F32_16X16X32_FP8_BF8_w64_twoaddr:{ *:[v4f32] } i32:{ *:[i32] }:$src0, v2i32:{ *:[v2i32] }:$src1, v4f32:{ *:[v4f32] }:$srcTiedDef, i32:{ *:[i32] }:$src2, i32:{ *:[i32] }:$index_key_8bit)
        GIR_BuildMI, /*InsnID*/0, /*Opcode*/GIMT_Encode2(AMDGPU::V_SWMMAC_F32_16X16X32_FP8_BF8_w64_twoaddr),
        GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/0, // DstI[vdst]
        GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/2, // src0
        GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/3, // src1
        GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/4, // srcTiedDef
        GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/0, // src2
        GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/1, // index_key_8bit
        GIR_ConstrainSelectedInstOperands, /*InsnID*/0,
        GIR_EraseFromParent, /*InsnID*/0,
        // GIR_Coverage, 2398,
        GIR_Done,
      // Label 3487: @226249
      GIM_Try, /*On fail goto*//*Label 3488*/ GIMT_Encode4(226329), // Rule ID 2399 //
        GIM_CheckFeatures, GIMT_Encode2(GIFBS_isGFX12Plus_isWave64),
        GIM_CheckIntrinsicID, /*MI*/0, /*Op*/1, GIMT_Encode2(Intrinsic::amdgcn_swmmac_f32_16x16x32_bf8_fp8),
        GIM_CheckType, /*MI*/0, /*Op*/0, /*Type*/GILLT_v4s32,
        GIM_CheckType, /*MI*/0, /*Op*/2, /*Type*/GILLT_s32,
        GIM_CheckType, /*MI*/0, /*Op*/3, /*Type*/GILLT_v2s32,
        GIM_CheckType, /*MI*/0, /*Op*/4, /*Type*/GILLT_v4s32,
        GIM_CheckType, /*MI*/0, /*Op*/5, /*Type*/GILLT_s32,
        GIM_CheckRegBankForClass, /*MI*/0, /*Op*/0, /*RC*/GIMT_Encode2(AMDGPU::VReg_128RegClassID),
        GIM_CheckComplexPattern, /*MI*/0, /*Op*/5, /*Renderer*/GIMT_Encode2(0), GIMT_Encode2(GICP_gi_swmmacindex8),
        // (intrinsic_wo_chain:{ *:[v4f32] } 2788:{ *:[iPTR] }, i32:{ *:[i32] }:$src0, v2i32:{ *:[v2i32] }:$src1, v4f32:{ *:[v4f32] }:$srcTiedDef, (SWMMACIndex8:{ *:[i32] } i32:{ *:[i32] }:$src2, i32:{ *:[i32] }:$index_key_8bit))  =>  (V_SWMMAC_F32_16X16X32_BF8_FP8_w64_twoaddr:{ *:[v4f32] } i32:{ *:[i32] }:$src0, v2i32:{ *:[v2i32] }:$src1, v4f32:{ *:[v4f32] }:$srcTiedDef, i32:{ *:[i32] }:$src2, i32:{ *:[i32] }:$index_key_8bit)
        GIR_BuildMI, /*InsnID*/0, /*Opcode*/GIMT_Encode2(AMDGPU::V_SWMMAC_F32_16X16X32_BF8_FP8_w64_twoaddr),
        GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/0, // DstI[vdst]
        GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/2, // src0
        GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/3, // src1
        GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/4, // srcTiedDef
        GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/0, // src2
        GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/1, // index_key_8bit
        GIR_ConstrainSelectedInstOperands, /*InsnID*/0,
        GIR_EraseFromParent, /*InsnID*/0,
        // GIR_Coverage, 2399,
        GIR_Done,
      // Label 3488: @226329
      GIM_Try, /*On fail goto*//*Label 3489*/ GIMT_Encode4(226409), // Rule ID 2400 //
        GIM_CheckFeatures, GIMT_Encode2(GIFBS_isGFX12Plus_isWave64),
        GIM_CheckIntrinsicID, /*MI*/0, /*Op*/1, GIMT_Encode2(Intrinsic::amdgcn_swmmac_f32_16x16x32_bf8_bf8),
        GIM_CheckType, /*MI*/0, /*Op*/0, /*Type*/GILLT_v4s32,
        GIM_CheckType, /*MI*/0, /*Op*/2, /*Type*/GILLT_s32,
        GIM_CheckType, /*MI*/0, /*Op*/3, /*Type*/GILLT_v2s32,
        GIM_CheckType, /*MI*/0, /*Op*/4, /*Type*/GILLT_v4s32,
        GIM_CheckType, /*MI*/0, /*Op*/5, /*Type*/GILLT_s32,
        GIM_CheckRegBankForClass, /*MI*/0, /*Op*/0, /*RC*/GIMT_Encode2(AMDGPU::VReg_128RegClassID),
        GIM_CheckComplexPattern, /*MI*/0, /*Op*/5, /*Renderer*/GIMT_Encode2(0), GIMT_Encode2(GICP_gi_swmmacindex8),
        // (intrinsic_wo_chain:{ *:[v4f32] } 2787:{ *:[iPTR] }, i32:{ *:[i32] }:$src0, v2i32:{ *:[v2i32] }:$src1, v4f32:{ *:[v4f32] }:$srcTiedDef, (SWMMACIndex8:{ *:[i32] } i32:{ *:[i32] }:$src2, i32:{ *:[i32] }:$index_key_8bit))  =>  (V_SWMMAC_F32_16X16X32_BF8_BF8_w64_twoaddr:{ *:[v4f32] } i32:{ *:[i32] }:$src0, v2i32:{ *:[v2i32] }:$src1, v4f32:{ *:[v4f32] }:$srcTiedDef, i32:{ *:[i32] }:$src2, i32:{ *:[i32] }:$index_key_8bit)
        GIR_BuildMI, /*InsnID*/0, /*Opcode*/GIMT_Encode2(AMDGPU::V_SWMMAC_F32_16X16X32_BF8_BF8_w64_twoaddr),
        GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/0, // DstI[vdst]
        GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/2, // src0
        GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/3, // src1
        GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/4, // srcTiedDef
        GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/0, // src2
        GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/1, // index_key_8bit
        GIR_ConstrainSelectedInstOperands, /*InsnID*/0,
        GIR_EraseFromParent, /*InsnID*/0,
        // GIR_Coverage, 2400,
        GIR_Done,
      // Label 3489: @226409
      GIM_Try, /*On fail goto*//*Label 3490*/ GIMT_Encode4(226498), // Rule ID 2319 //
        GIM_CheckFeatures, GIMT_Encode2(GIFBS_isGFX11Only_isWave32),
        GIM_CheckIntrinsicID, /*MI*/0, /*Op*/1, GIMT_Encode2(Intrinsic::amdgcn_wmma_f16_16x16x16_f16),
        GIM_CheckType, /*MI*/0, /*Op*/0, /*Type*/GILLT_v16s16,
        GIM_CheckType, /*MI*/0, /*Op*/2, /*Type*/GILLT_v16s16,
        GIM_CheckType, /*MI*/0, /*Op*/3, /*Type*/GILLT_v16s16,
        GIM_CheckType, /*MI*/0, /*Op*/4, /*Type*/GILLT_v16s16,
        GIM_CheckRegBankForClass, /*MI*/0, /*Op*/0, /*RC*/GIMT_Encode2(AMDGPU::VReg_256RegClassID),
        GIM_CheckComplexPattern, /*MI*/0, /*Op*/5, /*Renderer*/GIMT_Encode2(0), GIMT_Encode2(GICP_gi_wmmaopselvop3pmods),
        // (intrinsic_wo_chain:{ *:[v16f16] } 2811:{ *:[iPTR] }, v16f16:{ *:[v16f16] }:$src0, v16f16:{ *:[v16f16] }:$src1, v16f16:{ *:[v16f16] }:$src2, (WMMAOpSelVOP3PMods:{ *:[i1] } i32:{ *:[i32] }:$src2_modifiers))  =>  (V_WMMA_F16_16X16X16_F16_twoaddr_w32:{ *:[v16f16] } 8:{ *:[i32] }, v16f16:{ *:[v16f16] }:$src0, 8:{ *:[i32] }, v16f16:{ *:[v16f16] }:$src1, i32:{ *:[i32] }:$src2_modifiers, v16f16:{ *:[v16f16] }:$src2)
        GIR_BuildMI, /*InsnID*/0, /*Opcode*/GIMT_Encode2(AMDGPU::V_WMMA_F16_16X16X16_F16_twoaddr_w32),
        GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/0, // DstI[vdst]
        GIR_AddImm8, /*InsnID*/0, /*Imm*/8,
        GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/2, // src0
        GIR_AddImm8, /*InsnID*/0, /*Imm*/8,
        GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/3, // src1
        GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/0, // src2_modifiers
        GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/4, // src2
        GIR_AddImm8, /*InsnID*/0, /*Imm*/0,
        GIR_AddImm8, /*InsnID*/0, /*Imm*/0,
        GIR_AddImm8, /*InsnID*/0, /*Imm*/0,
        GIR_AddImm8, /*InsnID*/0, /*Imm*/0,
        GIR_ConstrainSelectedInstOperands, /*InsnID*/0,
        GIR_EraseFromParent, /*InsnID*/0,
        // GIR_Coverage, 2319,
        GIR_Done,
      // Label 3490: @226498
      GIM_Try, /*On fail goto*//*Label 3491*/ GIMT_Encode4(226587), // Rule ID 2323 //
        GIM_CheckFeatures, GIMT_Encode2(GIFBS_isGFX11Only_isWave32),
        GIM_CheckIntrinsicID, /*MI*/0, /*Op*/1, GIMT_Encode2(Intrinsic::amdgcn_wmma_bf16_16x16x16_bf16),
        GIM_CheckType, /*MI*/0, /*Op*/0, /*Type*/GILLT_v16s16,
        GIM_CheckType, /*MI*/0, /*Op*/2, /*Type*/GILLT_v16s16,
        GIM_CheckType, /*MI*/0, /*Op*/3, /*Type*/GILLT_v16s16,
        GIM_CheckType, /*MI*/0, /*Op*/4, /*Type*/GILLT_v16s16,
        GIM_CheckRegBankForClass, /*MI*/0, /*Op*/0, /*RC*/GIMT_Encode2(AMDGPU::VReg_256RegClassID),
        GIM_CheckComplexPattern, /*MI*/0, /*Op*/5, /*Renderer*/GIMT_Encode2(0), GIMT_Encode2(GICP_gi_wmmaopselvop3pmods),
        // (intrinsic_wo_chain:{ *:[v16i16] } 2809:{ *:[iPTR] }, v16i16:{ *:[v16i16] }:$src0, v16i16:{ *:[v16i16] }:$src1, v16i16:{ *:[v16i16] }:$src2, (WMMAOpSelVOP3PMods:{ *:[i1] } i32:{ *:[i32] }:$src2_modifiers))  =>  (V_WMMA_BF16_16X16X16_BF16_twoaddr_w32:{ *:[v16i16] } 8:{ *:[i32] }, v16i16:{ *:[v16i16] }:$src0, 8:{ *:[i32] }, v16i16:{ *:[v16i16] }:$src1, i32:{ *:[i32] }:$src2_modifiers, v16i16:{ *:[v16i16] }:$src2)
        GIR_BuildMI, /*InsnID*/0, /*Opcode*/GIMT_Encode2(AMDGPU::V_WMMA_BF16_16X16X16_BF16_twoaddr_w32),
        GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/0, // DstI[vdst]
        GIR_AddImm8, /*InsnID*/0, /*Imm*/8,
        GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/2, // src0
        GIR_AddImm8, /*InsnID*/0, /*Imm*/8,
        GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/3, // src1
        GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/0, // src2_modifiers
        GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/4, // src2
        GIR_AddImm8, /*InsnID*/0, /*Imm*/0,
        GIR_AddImm8, /*InsnID*/0, /*Imm*/0,
        GIR_AddImm8, /*InsnID*/0, /*Imm*/0,
        GIR_AddImm8, /*InsnID*/0, /*Imm*/0,
        GIR_ConstrainSelectedInstOperands, /*InsnID*/0,
        GIR_EraseFromParent, /*InsnID*/0,
        // GIR_Coverage, 2323,
        GIR_Done,
      // Label 3491: @226587
      GIM_Try, /*On fail goto*//*Label 3492*/ GIMT_Encode4(226676), // Rule ID 2324 //
        GIM_CheckFeatures, GIMT_Encode2(GIFBS_isGFX11Only_isWave32),
        GIM_CheckIntrinsicID, /*MI*/0, /*Op*/1, GIMT_Encode2(Intrinsic::amdgcn_wmma_f16_16x16x16_f16_tied),
        GIM_CheckType, /*MI*/0, /*Op*/0, /*Type*/GILLT_v16s16,
        GIM_CheckType, /*MI*/0, /*Op*/2, /*Type*/GILLT_v16s16,
        GIM_CheckType, /*MI*/0, /*Op*/3, /*Type*/GILLT_v16s16,
        GIM_CheckType, /*MI*/0, /*Op*/4, /*Type*/GILLT_v16s16,
        GIM_CheckRegBankForClass, /*MI*/0, /*Op*/0, /*RC*/GIMT_Encode2(AMDGPU::VReg_256RegClassID),
        GIM_CheckComplexPattern, /*MI*/0, /*Op*/5, /*Renderer*/GIMT_Encode2(0), GIMT_Encode2(GICP_gi_wmmaopselvop3pmods),
        // (intrinsic_wo_chain:{ *:[v16f16] } 2812:{ *:[iPTR] }, v16f16:{ *:[v16f16] }:$src0, v16f16:{ *:[v16f16] }:$src1, v16f16:{ *:[v16f16] }:$src2, (WMMAOpSelVOP3PMods:{ *:[i1] } i32:{ *:[i32] }:$src2_modifiers))  =>  (V_WMMA_F16_16X16X16_F16_TIED_twoaddr_w32:{ *:[v16f16] } 8:{ *:[i32] }, v16f16:{ *:[v16f16] }:$src0, 8:{ *:[i32] }, v16f16:{ *:[v16f16] }:$src1, i32:{ *:[i32] }:$src2_modifiers, v16f16:{ *:[v16f16] }:$src2)
        GIR_BuildMI, /*InsnID*/0, /*Opcode*/GIMT_Encode2(AMDGPU::V_WMMA_F16_16X16X16_F16_TIED_twoaddr_w32),
        GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/0, // DstI[vdst]
        GIR_AddImm8, /*InsnID*/0, /*Imm*/8,
        GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/2, // src0
        GIR_AddImm8, /*InsnID*/0, /*Imm*/8,
        GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/3, // src1
        GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/0, // src2_modifiers
        GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/4, // src2
        GIR_AddImm8, /*InsnID*/0, /*Imm*/0,
        GIR_AddImm8, /*InsnID*/0, /*Imm*/0,
        GIR_AddImm8, /*InsnID*/0, /*Imm*/0,
        GIR_AddImm8, /*InsnID*/0, /*Imm*/0,
        GIR_ConstrainSelectedInstOperands, /*InsnID*/0,
        GIR_EraseFromParent, /*InsnID*/0,
        // GIR_Coverage, 2324,
        GIR_Done,
      // Label 3492: @226676
      GIM_Try, /*On fail goto*//*Label 3493*/ GIMT_Encode4(226765), // Rule ID 2325 //
        GIM_CheckFeatures, GIMT_Encode2(GIFBS_isGFX11Only_isWave32),
        GIM_CheckIntrinsicID, /*MI*/0, /*Op*/1, GIMT_Encode2(Intrinsic::amdgcn_wmma_bf16_16x16x16_bf16_tied),
        GIM_CheckType, /*MI*/0, /*Op*/0, /*Type*/GILLT_v16s16,
        GIM_CheckType, /*MI*/0, /*Op*/2, /*Type*/GILLT_v16s16,
        GIM_CheckType, /*MI*/0, /*Op*/3, /*Type*/GILLT_v16s16,
        GIM_CheckType, /*MI*/0, /*Op*/4, /*Type*/GILLT_v16s16,
        GIM_CheckRegBankForClass, /*MI*/0, /*Op*/0, /*RC*/GIMT_Encode2(AMDGPU::VReg_256RegClassID),
        GIM_CheckComplexPattern, /*MI*/0, /*Op*/5, /*Renderer*/GIMT_Encode2(0), GIMT_Encode2(GICP_gi_wmmaopselvop3pmods),
        // (intrinsic_wo_chain:{ *:[v16i16] } 2810:{ *:[iPTR] }, v16i16:{ *:[v16i16] }:$src0, v16i16:{ *:[v16i16] }:$src1, v16i16:{ *:[v16i16] }:$src2, (WMMAOpSelVOP3PMods:{ *:[i1] } i32:{ *:[i32] }:$src2_modifiers))  =>  (V_WMMA_BF16_16X16X16_BF16_TIED_twoaddr_w32:{ *:[v16i16] } 8:{ *:[i32] }, v16i16:{ *:[v16i16] }:$src0, 8:{ *:[i32] }, v16i16:{ *:[v16i16] }:$src1, i32:{ *:[i32] }:$src2_modifiers, v16i16:{ *:[v16i16] }:$src2)
        GIR_BuildMI, /*InsnID*/0, /*Opcode*/GIMT_Encode2(AMDGPU::V_WMMA_BF16_16X16X16_BF16_TIED_twoaddr_w32),
        GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/0, // DstI[vdst]
        GIR_AddImm8, /*InsnID*/0, /*Imm*/8,
        GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/2, // src0
        GIR_AddImm8, /*InsnID*/0, /*Imm*/8,
        GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/3, // src1
        GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/0, // src2_modifiers
        GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/4, // src2
        GIR_AddImm8, /*InsnID*/0, /*Imm*/0,
        GIR_AddImm8, /*InsnID*/0, /*Imm*/0,
        GIR_AddImm8, /*InsnID*/0, /*Imm*/0,
        GIR_AddImm8, /*InsnID*/0, /*Imm*/0,
        GIR_ConstrainSelectedInstOperands, /*InsnID*/0,
        GIR_EraseFromParent, /*InsnID*/0,
        // GIR_Coverage, 2325,
        GIR_Done,
      // Label 3493: @226765
      GIM_Try, /*On fail goto*//*Label 3494*/ GIMT_Encode4(226854), // Rule ID 2329 //
        GIM_CheckFeatures, GIMT_Encode2(GIFBS_isGFX11Only_isWave64),
        GIM_CheckIntrinsicID, /*MI*/0, /*Op*/1, GIMT_Encode2(Intrinsic::amdgcn_wmma_f16_16x16x16_f16),
        GIM_CheckType, /*MI*/0, /*Op*/0, /*Type*/GILLT_v8s16,
        GIM_CheckType, /*MI*/0, /*Op*/2, /*Type*/GILLT_v16s16,
        GIM_CheckType, /*MI*/0, /*Op*/3, /*Type*/GILLT_v16s16,
        GIM_CheckType, /*MI*/0, /*Op*/4, /*Type*/GILLT_v8s16,
        GIM_CheckRegBankForClass, /*MI*/0, /*Op*/0, /*RC*/GIMT_Encode2(AMDGPU::VReg_128RegClassID),
        GIM_CheckComplexPattern, /*MI*/0, /*Op*/5, /*Renderer*/GIMT_Encode2(0), GIMT_Encode2(GICP_gi_wmmaopselvop3pmods),
        // (intrinsic_wo_chain:{ *:[v8f16] } 2811:{ *:[iPTR] }, v16f16:{ *:[v16f16] }:$src0, v16f16:{ *:[v16f16] }:$src1, v8f16:{ *:[v8f16] }:$src2, (WMMAOpSelVOP3PMods:{ *:[i1] } i32:{ *:[i32] }:$src2_modifiers))  =>  (V_WMMA_F16_16X16X16_F16_twoaddr_w64:{ *:[v8f16] } 8:{ *:[i32] }, v16f16:{ *:[v16f16] }:$src0, 8:{ *:[i32] }, v16f16:{ *:[v16f16] }:$src1, i32:{ *:[i32] }:$src2_modifiers, v8f16:{ *:[v8f16] }:$src2)
        GIR_BuildMI, /*InsnID*/0, /*Opcode*/GIMT_Encode2(AMDGPU::V_WMMA_F16_16X16X16_F16_twoaddr_w64),
        GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/0, // DstI[vdst]
        GIR_AddImm8, /*InsnID*/0, /*Imm*/8,
        GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/2, // src0
        GIR_AddImm8, /*InsnID*/0, /*Imm*/8,
        GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/3, // src1
        GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/0, // src2_modifiers
        GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/4, // src2
        GIR_AddImm8, /*InsnID*/0, /*Imm*/0,
        GIR_AddImm8, /*InsnID*/0, /*Imm*/0,
        GIR_AddImm8, /*InsnID*/0, /*Imm*/0,
        GIR_AddImm8, /*InsnID*/0, /*Imm*/0,
        GIR_ConstrainSelectedInstOperands, /*InsnID*/0,
        GIR_EraseFromParent, /*InsnID*/0,
        // GIR_Coverage, 2329,
        GIR_Done,
      // Label 3494: @226854
      GIM_Try, /*On fail goto*//*Label 3495*/ GIMT_Encode4(226943), // Rule ID 2330 //
        GIM_CheckFeatures, GIMT_Encode2(GIFBS_isGFX11Only_isWave64),
        GIM_CheckIntrinsicID, /*MI*/0, /*Op*/1, GIMT_Encode2(Intrinsic::amdgcn_wmma_bf16_16x16x16_bf16),
        GIM_CheckType, /*MI*/0, /*Op*/0, /*Type*/GILLT_v8s16,
        GIM_CheckType, /*MI*/0, /*Op*/2, /*Type*/GILLT_v16s16,
        GIM_CheckType, /*MI*/0, /*Op*/3, /*Type*/GILLT_v16s16,
        GIM_CheckType, /*MI*/0, /*Op*/4, /*Type*/GILLT_v8s16,
        GIM_CheckRegBankForClass, /*MI*/0, /*Op*/0, /*RC*/GIMT_Encode2(AMDGPU::VReg_128RegClassID),
        GIM_CheckComplexPattern, /*MI*/0, /*Op*/5, /*Renderer*/GIMT_Encode2(0), GIMT_Encode2(GICP_gi_wmmaopselvop3pmods),
        // (intrinsic_wo_chain:{ *:[v8i16] } 2809:{ *:[iPTR] }, v16i16:{ *:[v16i16] }:$src0, v16i16:{ *:[v16i16] }:$src1, v8i16:{ *:[v8i16] }:$src2, (WMMAOpSelVOP3PMods:{ *:[i1] } i32:{ *:[i32] }:$src2_modifiers))  =>  (V_WMMA_BF16_16X16X16_BF16_twoaddr_w64:{ *:[v8i16] } 8:{ *:[i32] }, v16i16:{ *:[v16i16] }:$src0, 8:{ *:[i32] }, v16i16:{ *:[v16i16] }:$src1, i32:{ *:[i32] }:$src2_modifiers, v8i16:{ *:[v8i16] }:$src2)
        GIR_BuildMI, /*InsnID*/0, /*Opcode*/GIMT_Encode2(AMDGPU::V_WMMA_BF16_16X16X16_BF16_twoaddr_w64),
        GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/0, // DstI[vdst]
        GIR_AddImm8, /*InsnID*/0, /*Imm*/8,
        GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/2, // src0
        GIR_AddImm8, /*InsnID*/0, /*Imm*/8,
        GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/3, // src1
        GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/0, // src2_modifiers
        GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/4, // src2
        GIR_AddImm8, /*InsnID*/0, /*Imm*/0,
        GIR_AddImm8, /*InsnID*/0, /*Imm*/0,
        GIR_AddImm8, /*InsnID*/0, /*Imm*/0,
        GIR_AddImm8, /*InsnID*/0, /*Imm*/0,
        GIR_ConstrainSelectedInstOperands, /*InsnID*/0,
        GIR_EraseFromParent, /*InsnID*/0,
        // GIR_Coverage, 2330,
        GIR_Done,
      // Label 3495: @226943
      GIM_Try, /*On fail goto*//*Label 3496*/ GIMT_Encode4(227032), // Rule ID 2331 //
        GIM_CheckFeatures, GIMT_Encode2(GIFBS_isGFX11Only_isWave64),
        GIM_CheckIntrinsicID, /*MI*/0, /*Op*/1, GIMT_Encode2(Intrinsic::amdgcn_wmma_f16_16x16x16_f16_tied),
        GIM_CheckType, /*MI*/0, /*Op*/0, /*Type*/GILLT_v8s16,
        GIM_CheckType, /*MI*/0, /*Op*/2, /*Type*/GILLT_v16s16,
        GIM_CheckType, /*MI*/0, /*Op*/3, /*Type*/GILLT_v16s16,
        GIM_CheckType, /*MI*/0, /*Op*/4, /*Type*/GILLT_v8s16,
        GIM_CheckRegBankForClass, /*MI*/0, /*Op*/0, /*RC*/GIMT_Encode2(AMDGPU::VReg_128RegClassID),
        GIM_CheckComplexPattern, /*MI*/0, /*Op*/5, /*Renderer*/GIMT_Encode2(0), GIMT_Encode2(GICP_gi_wmmaopselvop3pmods),
        // (intrinsic_wo_chain:{ *:[v8f16] } 2812:{ *:[iPTR] }, v16f16:{ *:[v16f16] }:$src0, v16f16:{ *:[v16f16] }:$src1, v8f16:{ *:[v8f16] }:$src2, (WMMAOpSelVOP3PMods:{ *:[i1] } i32:{ *:[i32] }:$src2_modifiers))  =>  (V_WMMA_F16_16X16X16_F16_TIED_twoaddr_w64:{ *:[v8f16] } 8:{ *:[i32] }, v16f16:{ *:[v16f16] }:$src0, 8:{ *:[i32] }, v16f16:{ *:[v16f16] }:$src1, i32:{ *:[i32] }:$src2_modifiers, v8f16:{ *:[v8f16] }:$src2)
        GIR_BuildMI, /*InsnID*/0, /*Opcode*/GIMT_Encode2(AMDGPU::V_WMMA_F16_16X16X16_F16_TIED_twoaddr_w64),
        GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/0, // DstI[vdst]
        GIR_AddImm8, /*InsnID*/0, /*Imm*/8,
        GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/2, // src0
        GIR_AddImm8, /*InsnID*/0, /*Imm*/8,
        GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/3, // src1
        GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/0, // src2_modifiers
        GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/4, // src2
        GIR_AddImm8, /*InsnID*/0, /*Imm*/0,
        GIR_AddImm8, /*InsnID*/0, /*Imm*/0,
        GIR_AddImm8, /*InsnID*/0, /*Imm*/0,
        GIR_AddImm8, /*InsnID*/0, /*Imm*/0,
        GIR_ConstrainSelectedInstOperands, /*InsnID*/0,
        GIR_EraseFromParent, /*InsnID*/0,
        // GIR_Coverage, 2331,
        GIR_Done,
      // Label 3496: @227032
      GIM_Try, /*On fail goto*//*Label 3497*/ GIMT_Encode4(227121), // Rule ID 2332 //
        GIM_CheckFeatures, GIMT_Encode2(GIFBS_isGFX11Only_isWave64),
        GIM_CheckIntrinsicID, /*MI*/0, /*Op*/1, GIMT_Encode2(Intrinsic::amdgcn_wmma_bf16_16x16x16_bf16_tied),
        GIM_CheckType, /*MI*/0, /*Op*/0, /*Type*/GILLT_v8s16,
        GIM_CheckType, /*MI*/0, /*Op*/2, /*Type*/GILLT_v16s16,
        GIM_CheckType, /*MI*/0, /*Op*/3, /*Type*/GILLT_v16s16,
        GIM_CheckType, /*MI*/0, /*Op*/4, /*Type*/GILLT_v8s16,
        GIM_CheckRegBankForClass, /*MI*/0, /*Op*/0, /*RC*/GIMT_Encode2(AMDGPU::VReg_128RegClassID),
        GIM_CheckComplexPattern, /*MI*/0, /*Op*/5, /*Renderer*/GIMT_Encode2(0), GIMT_Encode2(GICP_gi_wmmaopselvop3pmods),
        // (intrinsic_wo_chain:{ *:[v8i16] } 2810:{ *:[iPTR] }, v16i16:{ *:[v16i16] }:$src0, v16i16:{ *:[v16i16] }:$src1, v8i16:{ *:[v8i16] }:$src2, (WMMAOpSelVOP3PMods:{ *:[i1] } i32:{ *:[i32] }:$src2_modifiers))  =>  (V_WMMA_BF16_16X16X16_BF16_TIED_twoaddr_w64:{ *:[v8i16] } 8:{ *:[i32] }, v16i16:{ *:[v16i16] }:$src0, 8:{ *:[i32] }, v16i16:{ *:[v16i16] }:$src1, i32:{ *:[i32] }:$src2_modifiers, v8i16:{ *:[v8i16] }:$src2)
        GIR_BuildMI, /*InsnID*/0, /*Opcode*/GIMT_Encode2(AMDGPU::V_WMMA_BF16_16X16X16_BF16_TIED_twoaddr_w64),
        GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/0, // DstI[vdst]
        GIR_AddImm8, /*InsnID*/0, /*Imm*/8,
        GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/2, // src0
        GIR_AddImm8, /*InsnID*/0, /*Imm*/8,
        GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/3, // src1
        GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/0, // src2_modifiers
        GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/4, // src2
        GIR_AddImm8, /*InsnID*/0, /*Imm*/0,
        GIR_AddImm8, /*InsnID*/0, /*Imm*/0,
        GIR_AddImm8, /*InsnID*/0, /*Imm*/0,
        GIR_AddImm8, /*InsnID*/0, /*Imm*/0,
        GIR_ConstrainSelectedInstOperands, /*InsnID*/0,
        GIR_EraseFromParent, /*InsnID*/0,
        // GIR_Coverage, 2332,
        GIR_Done,
      // Label 3497: @227121
      GIM_Try, /*On fail goto*//*Label 3498*/ GIMT_Encode4(227206), // Rule ID 2341 //
        GIM_CheckFeatures, GIMT_Encode2(GIFBS_isGFX12Plus_isWave32),
        GIM_CheckIntrinsicID, /*MI*/0, /*Op*/1, GIMT_Encode2(Intrinsic::amdgcn_wmma_bf16_16x16x16_bf16),
        GIM_CheckType, /*MI*/0, /*Op*/0, /*Type*/GILLT_v8s16,
        GIM_CheckType, /*MI*/0, /*Op*/2, /*Type*/GILLT_v8s16,
        GIM_CheckType, /*MI*/0, /*Op*/3, /*Type*/GILLT_v8s16,
        GIM_CheckType, /*MI*/0, /*Op*/4, /*Type*/GILLT_v8s16,
        GIM_CheckRegBankForClass, /*MI*/0, /*Op*/0, /*RC*/GIMT_Encode2(AMDGPU::VReg_128RegClassID),
        // MIs[0] Operand 5
        GIM_CheckLiteralInt, /*MI*/0, /*Op*/5, GIMT_Encode8(0),
        // (intrinsic_wo_chain:{ *:[v8i16] } 2809:{ *:[iPTR] }, v8i16:{ *:[v8i16] }:$src0, v8i16:{ *:[v8i16] }:$src1, v8i16:{ *:[v8i16] }:$src2, 0:{ *:[i1] })  =>  (V_WMMA_BF16_16X16X16_BF16_w32_twoaddr:{ *:[v8i16] } 8:{ *:[i32] }, v8i16:{ *:[v8i16] }:$src0, 8:{ *:[i32] }, v8i16:{ *:[v8i16] }:$src1, 8:{ *:[i32] }, v8i16:{ *:[v8i16] }:$src2)
        GIR_BuildMI, /*InsnID*/0, /*Opcode*/GIMT_Encode2(AMDGPU::V_WMMA_BF16_16X16X16_BF16_w32_twoaddr),
        GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/0, // DstI[vdst]
        GIR_AddImm8, /*InsnID*/0, /*Imm*/8,
        GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/2, // src0
        GIR_AddImm8, /*InsnID*/0, /*Imm*/8,
        GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/3, // src1
        GIR_AddImm8, /*InsnID*/0, /*Imm*/8,
        GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/4, // src2
        GIR_AddImm8, /*InsnID*/0, /*Imm*/0,
        GIR_AddImm8, /*InsnID*/0, /*Imm*/0,
        GIR_ConstrainSelectedInstOperands, /*InsnID*/0,
        GIR_EraseFromParent, /*InsnID*/0,
        // GIR_Coverage, 2341,
        GIR_Done,
      // Label 3498: @227206
      GIM_Try, /*On fail goto*//*Label 3499*/ GIMT_Encode4(227291), // Rule ID 2374 //
        GIM_CheckFeatures, GIMT_Encode2(GIFBS_isGFX12Plus_isWave64),
        GIM_CheckIntrinsicID, /*MI*/0, /*Op*/1, GIMT_Encode2(Intrinsic::amdgcn_wmma_bf16_16x16x16_bf16),
        GIM_CheckType, /*MI*/0, /*Op*/0, /*Type*/GILLT_v4s16,
        GIM_CheckType, /*MI*/0, /*Op*/2, /*Type*/GILLT_v4s16,
        GIM_CheckType, /*MI*/0, /*Op*/3, /*Type*/GILLT_v4s16,
        GIM_CheckType, /*MI*/0, /*Op*/4, /*Type*/GILLT_v4s16,
        GIM_CheckRegBankForClass, /*MI*/0, /*Op*/0, /*RC*/GIMT_Encode2(AMDGPU::VReg_64RegClassID),
        // MIs[0] Operand 5
        GIM_CheckLiteralInt, /*MI*/0, /*Op*/5, GIMT_Encode8(0),
        // (intrinsic_wo_chain:{ *:[v4i16] } 2809:{ *:[iPTR] }, v4i16:{ *:[v4i16] }:$src0, v4i16:{ *:[v4i16] }:$src1, v4i16:{ *:[v4i16] }:$src2, 0:{ *:[i1] })  =>  (V_WMMA_BF16_16X16X16_BF16_w64_twoaddr:{ *:[v4i16] } 8:{ *:[i32] }, v4i16:{ *:[v4i16] }:$src0, 8:{ *:[i32] }, v4i16:{ *:[v4i16] }:$src1, 8:{ *:[i32] }, v4i16:{ *:[v4i16] }:$src2)
        GIR_BuildMI, /*InsnID*/0, /*Opcode*/GIMT_Encode2(AMDGPU::V_WMMA_BF16_16X16X16_BF16_w64_twoaddr),
        GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/0, // DstI[vdst]
        GIR_AddImm8, /*InsnID*/0, /*Imm*/8,
        GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/2, // src0
        GIR_AddImm8, /*InsnID*/0, /*Imm*/8,
        GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/3, // src1
        GIR_AddImm8, /*InsnID*/0, /*Imm*/8,
        GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/4, // src2
        GIR_AddImm8, /*InsnID*/0, /*Imm*/0,
        GIR_AddImm8, /*InsnID*/0, /*Imm*/0,
        GIR_ConstrainSelectedInstOperands, /*InsnID*/0,
        GIR_EraseFromParent, /*InsnID*/0,
        // GIR_Coverage, 2374,
        GIR_Done,
      // Label 3499: @227291
      GIM_Reject,
    // Label 3467: @227292
    GIM_Try, /*On fail goto*//*Label 3500*/ GIMT_Encode4(227624),
      GIM_CheckNumOperands, /*MI*/0, /*Expected*/7,
      GIM_Try, /*On fail goto*//*Label 3501*/ GIMT_Encode4(227383), // Rule ID 2080 //
        GIM_CheckFeatures, GIMT_Encode2(GIFBS_isGFX8Plus),
        GIM_CheckIntrinsicID, /*MI*/0, /*Op*/1, GIMT_Encode2(Intrinsic::amdgcn_mov_dpp),
        GIM_CheckType, /*MI*/0, /*Op*/0, /*Type*/GILLT_s32,
        GIM_CheckType, /*MI*/0, /*Op*/2, /*Type*/GILLT_s32,
        GIM_CheckRegBankForClass, /*MI*/0, /*Op*/0, /*RC*/GIMT_Encode2(AMDGPU::VGPR_32RegClassID),
        // MIs[0] dpp_ctrl
        GIM_CheckIsImm, /*MI*/0, /*Op*/3,
        // MIs[0] row_mask
        GIM_CheckIsImm, /*MI*/0, /*Op*/4,
        // MIs[0] bank_mask
        GIM_CheckIsImm, /*MI*/0, /*Op*/5,
        // MIs[0] bound_ctrl
        GIM_CheckIsImm, /*MI*/0, /*Op*/6,
        // (intrinsic_wo_chain:{ *:[i32] } 2579:{ *:[iPTR] }, i32:{ *:[i32] }:$src, (timm:{ *:[i32] }):$dpp_ctrl, (timm:{ *:[i32] }):$row_mask, (timm:{ *:[i32] }):$bank_mask, (timm:{ *:[i1] }):$bound_ctrl)  =>  (V_MOV_B32_dpp:{ *:[i32] } VGPR_32:{ *:[i32] }:$src, VGPR_32:{ *:[i32] }:$src, (as_i32timm:{ *:[i32] } ?:{ *:[i32] }:$dpp_ctrl), (as_i32timm:{ *:[i32] } ?:{ *:[i32] }:$row_mask), (as_i32timm:{ *:[i32] } ?:{ *:[i32] }:$bank_mask), (as_i1timm:{ *:[i1] } ?:{ *:[i1] }:$bound_ctrl))
        GIR_BuildMI, /*InsnID*/0, /*Opcode*/GIMT_Encode2(AMDGPU::V_MOV_B32_dpp),
        GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/0, // DstI[vdst]
        GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/2, // src
        GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/2, // src
        GIR_CustomOperandRenderer, /*InsnID*/0, /*OldInsnID*/0, /*OpIdx*/3, /*OperandRenderer*/GIMT_Encode2(GICR_renderTruncTImm), // dpp_ctrl
        GIR_CustomOperandRenderer, /*InsnID*/0, /*OldInsnID*/0, /*OpIdx*/4, /*OperandRenderer*/GIMT_Encode2(GICR_renderTruncTImm), // row_mask
        GIR_CustomOperandRenderer, /*InsnID*/0, /*OldInsnID*/0, /*OpIdx*/5, /*OperandRenderer*/GIMT_Encode2(GICR_renderTruncTImm), // bank_mask
        GIR_CustomOperandRenderer, /*InsnID*/0, /*OldInsnID*/0, /*OpIdx*/6, /*OperandRenderer*/GIMT_Encode2(GICR_renderTruncTImm), // bound_ctrl
        GIR_ConstrainSelectedInstOperands, /*InsnID*/0,
        GIR_EraseFromParent, /*InsnID*/0,
        // GIR_Coverage, 2080,
        GIR_Done,
      // Label 3501: @227383
      GIM_Try, /*On fail goto*//*Label 3502*/ GIMT_Encode4(227463), // Rule ID 6459 //
        GIM_CheckIntrinsicID, /*MI*/0, /*Op*/1, GIMT_Encode2(Intrinsic::amdgcn_mov_dpp),
        GIM_CheckType, /*MI*/0, /*Op*/0, /*Type*/GILLT_s64,
        GIM_CheckType, /*MI*/0, /*Op*/2, /*Type*/GILLT_s64,
        GIM_CheckRegBankForClass, /*MI*/0, /*Op*/0, /*RC*/GIMT_Encode2(AMDGPU::VReg_64RegClassID),
        // MIs[0] dpp_ctrl
        GIM_CheckIsImm, /*MI*/0, /*Op*/3,
        // MIs[0] row_mask
        GIM_CheckIsImm, /*MI*/0, /*Op*/4,
        // MIs[0] bank_mask
        GIM_CheckIsImm, /*MI*/0, /*Op*/5,
        // MIs[0] bound_ctrl
        GIM_CheckIsImm, /*MI*/0, /*Op*/6,
        // (intrinsic_wo_chain:{ *:[i64] } 2579:{ *:[iPTR] }, i64:{ *:[i64] }:$src, (timm:{ *:[i32] }):$dpp_ctrl, (timm:{ *:[i32] }):$row_mask, (timm:{ *:[i32] }):$bank_mask, (timm:{ *:[i1] }):$bound_ctrl)  =>  (V_MOV_B64_DPP_PSEUDO:{ *:[i64] } VReg_64_Align2:{ *:[i64] }:$src, VReg_64_Align2:{ *:[i64] }:$src, (as_i32timm:{ *:[i32] } ?:{ *:[i32] }:$dpp_ctrl), (as_i32timm:{ *:[i32] } ?:{ *:[i32] }:$row_mask), (as_i32timm:{ *:[i32] } ?:{ *:[i32] }:$bank_mask), (as_i1timm:{ *:[i1] } ?:{ *:[i1] }:$bound_ctrl))
        GIR_BuildMI, /*InsnID*/0, /*Opcode*/GIMT_Encode2(AMDGPU::V_MOV_B64_DPP_PSEUDO),
        GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/0, // DstI[vdst]
        GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/2, // src
        GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/2, // src
        GIR_CustomOperandRenderer, /*InsnID*/0, /*OldInsnID*/0, /*OpIdx*/3, /*OperandRenderer*/GIMT_Encode2(GICR_renderTruncTImm), // dpp_ctrl
        GIR_CustomOperandRenderer, /*InsnID*/0, /*OldInsnID*/0, /*OpIdx*/4, /*OperandRenderer*/GIMT_Encode2(GICR_renderTruncTImm), // row_mask
        GIR_CustomOperandRenderer, /*InsnID*/0, /*OldInsnID*/0, /*OpIdx*/5, /*OperandRenderer*/GIMT_Encode2(GICR_renderTruncTImm), // bank_mask
        GIR_CustomOperandRenderer, /*InsnID*/0, /*OldInsnID*/0, /*OpIdx*/6, /*OperandRenderer*/GIMT_Encode2(GICR_renderTruncTImm), // bound_ctrl
        GIR_ConstrainSelectedInstOperands, /*InsnID*/0,
        GIR_EraseFromParent, /*InsnID*/0,
        // GIR_Coverage, 6459,
        GIR_Done,
      // Label 3502: @227463
      GIM_Try, /*On fail goto*//*Label 3503*/ GIMT_Encode4(227543), // Rule ID 2216 //
        GIM_CheckFeatures, GIMT_Encode2(GIFBS_isGFX12Plus),
        GIM_CheckIntrinsicID, /*MI*/0, /*Op*/1, GIMT_Encode2(Intrinsic::amdgcn_permlane16_var),
        GIM_CheckType, /*MI*/0, /*Op*/0, /*Type*/GILLT_s32,
        GIM_CheckType, /*MI*/0, /*Op*/2, /*Type*/GILLT_s32,
        GIM_CheckType, /*MI*/0, /*Op*/3, /*Type*/GILLT_s32,
        GIM_CheckType, /*MI*/0, /*Op*/4, /*Type*/GILLT_s32,
        GIM_CheckRegBankForClass, /*MI*/0, /*Op*/0, /*RC*/GIMT_Encode2(AMDGPU::VGPR_32RegClassID),
        // MIs[0] fi
        GIM_CheckIsImm, /*MI*/0, /*Op*/5,
        // MIs[0] bc
        GIM_CheckIsImm, /*MI*/0, /*Op*/6,
        // (intrinsic_wo_chain:{ *:[i32] } 2590:{ *:[iPTR] }, i32:{ *:[i32] }:$vdst_in, i32:{ *:[i32] }:$src0, i32:{ *:[i32] }:$src1, (timm:{ *:[i1] }):$fi, (timm:{ *:[i1] }):$bc)  =>  (V_PERMLANE16_VAR_B32_e64:{ *:[i32] } (opsel_i1timm:{ *:[i32] } ?:{ *:[i1] }:$fi), VGPR_32:{ *:[i32] }:$src0, (opsel_i1timm:{ *:[i32] } ?:{ *:[i1] }:$bc), VGPR_32:{ *:[i32] }:$src1, VGPR_32:{ *:[i32] }:$vdst_in)
        GIR_BuildMI, /*InsnID*/0, /*Opcode*/GIMT_Encode2(AMDGPU::V_PERMLANE16_VAR_B32_e64),
        GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/0, // DstI[vdst]
        GIR_CustomOperandRenderer, /*InsnID*/0, /*OldInsnID*/0, /*OpIdx*/5, /*OperandRenderer*/GIMT_Encode2(GICR_renderOpSelTImm), // fi
        GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/3, // src0
        GIR_CustomOperandRenderer, /*InsnID*/0, /*OldInsnID*/0, /*OpIdx*/6, /*OperandRenderer*/GIMT_Encode2(GICR_renderOpSelTImm), // bc
        GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/4, // src1
        GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/2, // vdst_in
        GIR_AddImm8, /*InsnID*/0, /*Imm*/0,
        GIR_ConstrainSelectedInstOperands, /*InsnID*/0,
        GIR_EraseFromParent, /*InsnID*/0,
        // GIR_Coverage, 2216,
        GIR_Done,
      // Label 3503: @227543
      GIM_Try, /*On fail goto*//*Label 3504*/ GIMT_Encode4(227623), // Rule ID 2217 //
        GIM_CheckFeatures, GIMT_Encode2(GIFBS_isGFX12Plus),
        GIM_CheckIntrinsicID, /*MI*/0, /*Op*/1, GIMT_Encode2(Intrinsic::amdgcn_permlanex16_var),
        GIM_CheckType, /*MI*/0, /*Op*/0, /*Type*/GILLT_s32,
        GIM_CheckType, /*MI*/0, /*Op*/2, /*Type*/GILLT_s32,
        GIM_CheckType, /*MI*/0, /*Op*/3, /*Type*/GILLT_s32,
        GIM_CheckType, /*MI*/0, /*Op*/4, /*Type*/GILLT_s32,
        GIM_CheckRegBankForClass, /*MI*/0, /*Op*/0, /*RC*/GIMT_Encode2(AMDGPU::VGPR_32RegClassID),
        // MIs[0] fi
        GIM_CheckIsImm, /*MI*/0, /*Op*/5,
        // MIs[0] bc
        GIM_CheckIsImm, /*MI*/0, /*Op*/6,
        // (intrinsic_wo_chain:{ *:[i32] } 2593:{ *:[iPTR] }, i32:{ *:[i32] }:$vdst_in, i32:{ *:[i32] }:$src0, i32:{ *:[i32] }:$src1, (timm:{ *:[i1] }):$fi, (timm:{ *:[i1] }):$bc)  =>  (V_PERMLANEX16_VAR_B32_e64:{ *:[i32] } (opsel_i1timm:{ *:[i32] } ?:{ *:[i1] }:$fi), VGPR_32:{ *:[i32] }:$src0, (opsel_i1timm:{ *:[i32] } ?:{ *:[i1] }:$bc), VGPR_32:{ *:[i32] }:$src1, VGPR_32:{ *:[i32] }:$vdst_in)
        GIR_BuildMI, /*InsnID*/0, /*Opcode*/GIMT_Encode2(AMDGPU::V_PERMLANEX16_VAR_B32_e64),
        GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/0, // DstI[vdst]
        GIR_CustomOperandRenderer, /*InsnID*/0, /*OldInsnID*/0, /*OpIdx*/5, /*OperandRenderer*/GIMT_Encode2(GICR_renderOpSelTImm), // fi
        GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/3, // src0
        GIR_CustomOperandRenderer, /*InsnID*/0, /*OldInsnID*/0, /*OpIdx*/6, /*OperandRenderer*/GIMT_Encode2(GICR_renderOpSelTImm), // bc
        GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/4, // src1
        GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/2, // vdst_in
        GIR_AddImm8, /*InsnID*/0, /*Imm*/0,
        GIR_ConstrainSelectedInstOperands, /*InsnID*/0,
        GIR_EraseFromParent, /*InsnID*/0,
        // GIR_Coverage, 2217,
        GIR_Done,
      // Label 3504: @227623
      GIM_Reject,
    // Label 3500: @227624
    GIM_Try, /*On fail goto*//*Label 3505*/ GIMT_Encode4(237457),
      GIM_CheckNumOperands, /*MI*/0, /*Expected*/8,
      GIM_Try, /*On fail goto*//*Label 3506*/ GIMT_Encode4(227730), // Rule ID 2344 //
        GIM_CheckFeatures, GIMT_Encode2(GIFBS_isGFX12Plus_isWave32),
        GIM_CheckIntrinsicID, /*MI*/0, /*Op*/1, GIMT_Encode2(Intrinsic::amdgcn_wmma_i32_16x16x16_iu8),
        GIM_CheckType, /*MI*/0, /*Op*/0, /*Type*/GILLT_v8s32,
        GIM_CheckType, /*MI*/0, /*Op*/3, /*Type*/GILLT_v2s32,
        GIM_CheckType, /*MI*/0, /*Op*/5, /*Type*/GILLT_v2s32,
        GIM_CheckType, /*MI*/0, /*Op*/6, /*Type*/GILLT_v8s32,
        GIM_CheckRegBankForClass, /*MI*/0, /*Op*/0, /*RC*/GIMT_Encode2(AMDGPU::VReg_256RegClassID),
        // MIs[0] clamp
        // No operand predicates
        GIM_CheckComplexPattern, /*MI*/0, /*Op*/2, /*Renderer*/GIMT_Encode2(0), GIMT_Encode2(GICP_gi_vop3pmodsneg),
        GIM_CheckComplexPattern, /*MI*/0, /*Op*/4, /*Renderer*/GIMT_Encode2(1), GIMT_Encode2(GICP_gi_vop3pmodsneg),
        GIM_CheckComplexPattern, /*MI*/0, /*Op*/6, /*Renderer*/GIMT_Encode2(2), GIMT_Encode2(GICP_gi_wmmavisrc),
        // (intrinsic_wo_chain:{ *:[v8i32] } 2820:{ *:[iPTR] }, (VOP3PModsNeg:{ *:[i1] } i32:{ *:[i32] }:$src0_modifiers), v2i32:{ *:[v2i32] }:$src0, (VOP3PModsNeg:{ *:[i1] } i32:{ *:[i32] }:$src1_modifiers), v2i32:{ *:[v2i32] }:$src1, (WMMAVISrc:{ *:[v8i32] } v8i32:{ *:[v8i32] }:$src2), i1:{ *:[i1] }:$clamp)  =>  (V_WMMA_I32_16X16X16_IU8_w32_threeaddr:{ *:[v8i32] } i32:{ *:[i32] }:$src0_modifiers, v2i32:{ *:[v2i32] }:$src0, i32:{ *:[i32] }:$src1_modifiers, v2i32:{ *:[v2i32] }:$src1, v8i32:{ *:[v8i32] }:$src2, i1:{ *:[i1] }:$clamp)
        GIR_BuildMI, /*InsnID*/0, /*Opcode*/GIMT_Encode2(AMDGPU::V_WMMA_I32_16X16X16_IU8_w32_threeaddr),
        GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/0, // DstI[vdst]
        GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/0, // src0_modifiers
        GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/3, // src0
        GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(1), /*SubOperand*/0, // src1_modifiers
        GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/5, // src1
        GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(2), /*SubOperand*/0, // src2
        GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/7, // clamp
        GIR_AddImm8, /*InsnID*/0, /*Imm*/0,
        GIR_ConstrainSelectedInstOperands, /*InsnID*/0,
        GIR_EraseFromParent, /*InsnID*/0,
        // GIR_Coverage, 2344,
        GIR_Done,
      // Label 3506: @227730
      GIM_Try, /*On fail goto*//*Label 3507*/ GIMT_Encode4(227828), // Rule ID 2346 //
        GIM_CheckFeatures, GIMT_Encode2(GIFBS_isGFX12Plus_isWave32),
        GIM_CheckIntrinsicID, /*MI*/0, /*Op*/1, GIMT_Encode2(Intrinsic::amdgcn_wmma_i32_16x16x16_iu4),
        GIM_CheckType, /*MI*/0, /*Op*/0, /*Type*/GILLT_v8s32,
        GIM_CheckType, /*MI*/0, /*Op*/3, /*Type*/GILLT_s32,
        GIM_CheckType, /*MI*/0, /*Op*/5, /*Type*/GILLT_s32,
        GIM_CheckType, /*MI*/0, /*Op*/6, /*Type*/GILLT_v8s32,
        GIM_CheckRegBankForClass, /*MI*/0, /*Op*/0, /*RC*/GIMT_Encode2(AMDGPU::VReg_256RegClassID),
        // MIs[0] clamp
        // No operand predicates
        GIM_CheckComplexPattern, /*MI*/0, /*Op*/2, /*Renderer*/GIMT_Encode2(0), GIMT_Encode2(GICP_gi_vop3pmodsneg),
        GIM_CheckComplexPattern, /*MI*/0, /*Op*/4, /*Renderer*/GIMT_Encode2(1), GIMT_Encode2(GICP_gi_vop3pmodsneg),
        GIM_CheckComplexPattern, /*MI*/0, /*Op*/6, /*Renderer*/GIMT_Encode2(2), GIMT_Encode2(GICP_gi_wmmavisrc),
        // (intrinsic_wo_chain:{ *:[v8i32] } 2819:{ *:[iPTR] }, (VOP3PModsNeg:{ *:[i1] } i32:{ *:[i32] }:$src0_modifiers), i32:{ *:[i32] }:$src0, (VOP3PModsNeg:{ *:[i1] } i32:{ *:[i32] }:$src1_modifiers), i32:{ *:[i32] }:$src1, (WMMAVISrc:{ *:[v8i32] } v8i32:{ *:[v8i32] }:$src2), i1:{ *:[i1] }:$clamp)  =>  (V_WMMA_I32_16X16X16_IU4_w32_threeaddr:{ *:[v8i32] } i32:{ *:[i32] }:$src0_modifiers, i32:{ *:[i32] }:$src0, i32:{ *:[i32] }:$src1_modifiers, i32:{ *:[i32] }:$src1, v8i32:{ *:[v8i32] }:$src2, i1:{ *:[i1] }:$clamp)
        GIR_BuildMI, /*InsnID*/0, /*Opcode*/GIMT_Encode2(AMDGPU::V_WMMA_I32_16X16X16_IU4_w32_threeaddr),
        GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/0, // DstI[vdst]
        GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/0, // src0_modifiers
        GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/3, // src0
        GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(1), /*SubOperand*/0, // src1_modifiers
        GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/5, // src1
        GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(2), /*SubOperand*/0, // src2
        GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/7, // clamp
        GIR_AddImm8, /*InsnID*/0, /*Imm*/0,
        GIR_ConstrainSelectedInstOperands, /*InsnID*/0,
        GIR_EraseFromParent, /*InsnID*/0,
        // GIR_Coverage, 2346,
        GIR_Done,
      // Label 3507: @227828
      GIM_Try, /*On fail goto*//*Label 3508*/ GIMT_Encode4(227926), // Rule ID 2356 //
        GIM_CheckFeatures, GIMT_Encode2(GIFBS_isGFX12Plus_isWave32),
        GIM_CheckIntrinsicID, /*MI*/0, /*Op*/1, GIMT_Encode2(Intrinsic::amdgcn_wmma_i32_16x16x32_iu4),
        GIM_CheckType, /*MI*/0, /*Op*/0, /*Type*/GILLT_v8s32,
        GIM_CheckType, /*MI*/0, /*Op*/3, /*Type*/GILLT_v2s32,
        GIM_CheckType, /*MI*/0, /*Op*/5, /*Type*/GILLT_v2s32,
        GIM_CheckType, /*MI*/0, /*Op*/6, /*Type*/GILLT_v8s32,
        GIM_CheckRegBankForClass, /*MI*/0, /*Op*/0, /*RC*/GIMT_Encode2(AMDGPU::VReg_256RegClassID),
        // MIs[0] clamp
        // No operand predicates
        GIM_CheckComplexPattern, /*MI*/0, /*Op*/2, /*Renderer*/GIMT_Encode2(0), GIMT_Encode2(GICP_gi_vop3pmodsneg),
        GIM_CheckComplexPattern, /*MI*/0, /*Op*/4, /*Renderer*/GIMT_Encode2(1), GIMT_Encode2(GICP_gi_vop3pmodsneg),
        GIM_CheckComplexPattern, /*MI*/0, /*Op*/6, /*Renderer*/GIMT_Encode2(2), GIMT_Encode2(GICP_gi_wmmavisrc),
        // (intrinsic_wo_chain:{ *:[v8i32] } 2821:{ *:[iPTR] }, (VOP3PModsNeg:{ *:[i1] } i32:{ *:[i32] }:$src0_modifiers), v2i32:{ *:[v2i32] }:$src0, (VOP3PModsNeg:{ *:[i1] } i32:{ *:[i32] }:$src1_modifiers), v2i32:{ *:[v2i32] }:$src1, (WMMAVISrc:{ *:[v8i32] } v8i32:{ *:[v8i32] }:$src2), i1:{ *:[i1] }:$clamp)  =>  (V_WMMA_I32_16X16X32_IU4_w32_threeaddr:{ *:[v8i32] } i32:{ *:[i32] }:$src0_modifiers, v2i32:{ *:[v2i32] }:$src0, i32:{ *:[i32] }:$src1_modifiers, v2i32:{ *:[v2i32] }:$src1, v8i32:{ *:[v8i32] }:$src2, i1:{ *:[i1] }:$clamp)
        GIR_BuildMI, /*InsnID*/0, /*Opcode*/GIMT_Encode2(AMDGPU::V_WMMA_I32_16X16X32_IU4_w32_threeaddr),
        GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/0, // DstI[vdst]
        GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/0, // src0_modifiers
        GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/3, // src0
        GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(1), /*SubOperand*/0, // src1_modifiers
        GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/5, // src1
        GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(2), /*SubOperand*/0, // src2
        GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/7, // clamp
        GIR_AddImm8, /*InsnID*/0, /*Imm*/0,
        GIR_ConstrainSelectedInstOperands, /*InsnID*/0,
        GIR_EraseFromParent, /*InsnID*/0,
        // GIR_Coverage, 2356,
        GIR_Done,
      // Label 3508: @227926
      GIM_Try, /*On fail goto*//*Label 3509*/ GIMT_Encode4(228024), // Rule ID 2377 //
        GIM_CheckFeatures, GIMT_Encode2(GIFBS_isGFX12Plus_isWave64),
        GIM_CheckIntrinsicID, /*MI*/0, /*Op*/1, GIMT_Encode2(Intrinsic::amdgcn_wmma_i32_16x16x16_iu8),
        GIM_CheckType, /*MI*/0, /*Op*/0, /*Type*/GILLT_v4s32,
        GIM_CheckType, /*MI*/0, /*Op*/3, /*Type*/GILLT_s32,
        GIM_CheckType, /*MI*/0, /*Op*/5, /*Type*/GILLT_s32,
        GIM_CheckType, /*MI*/0, /*Op*/6, /*Type*/GILLT_v4s32,
        GIM_CheckRegBankForClass, /*MI*/0, /*Op*/0, /*RC*/GIMT_Encode2(AMDGPU::VReg_128RegClassID),
        // MIs[0] clamp
        // No operand predicates
        GIM_CheckComplexPattern, /*MI*/0, /*Op*/2, /*Renderer*/GIMT_Encode2(0), GIMT_Encode2(GICP_gi_vop3pmodsneg),
        GIM_CheckComplexPattern, /*MI*/0, /*Op*/4, /*Renderer*/GIMT_Encode2(1), GIMT_Encode2(GICP_gi_vop3pmodsneg),
        GIM_CheckComplexPattern, /*MI*/0, /*Op*/6, /*Renderer*/GIMT_Encode2(2), GIMT_Encode2(GICP_gi_wmmavisrc),
        // (intrinsic_wo_chain:{ *:[v4i32] } 2820:{ *:[iPTR] }, (VOP3PModsNeg:{ *:[i1] } i32:{ *:[i32] }:$src0_modifiers), i32:{ *:[i32] }:$src0, (VOP3PModsNeg:{ *:[i1] } i32:{ *:[i32] }:$src1_modifiers), i32:{ *:[i32] }:$src1, (WMMAVISrc:{ *:[v4i32] } v4i32:{ *:[v4i32] }:$src2), i1:{ *:[i1] }:$clamp)  =>  (V_WMMA_I32_16X16X16_IU8_w64_threeaddr:{ *:[v4i32] } i32:{ *:[i32] }:$src0_modifiers, i32:{ *:[i32] }:$src0, i32:{ *:[i32] }:$src1_modifiers, i32:{ *:[i32] }:$src1, v4i32:{ *:[v4i32] }:$src2, i1:{ *:[i1] }:$clamp)
        GIR_BuildMI, /*InsnID*/0, /*Opcode*/GIMT_Encode2(AMDGPU::V_WMMA_I32_16X16X16_IU8_w64_threeaddr),
        GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/0, // DstI[vdst]
        GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/0, // src0_modifiers
        GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/3, // src0
        GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(1), /*SubOperand*/0, // src1_modifiers
        GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/5, // src1
        GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(2), /*SubOperand*/0, // src2
        GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/7, // clamp
        GIR_AddImm8, /*InsnID*/0, /*Imm*/0,
        GIR_ConstrainSelectedInstOperands, /*InsnID*/0,
        GIR_EraseFromParent, /*InsnID*/0,
        // GIR_Coverage, 2377,
        GIR_Done,
      // Label 3509: @228024
      GIM_Try, /*On fail goto*//*Label 3510*/ GIMT_Encode4(228122), // Rule ID 2379 //
        GIM_CheckFeatures, GIMT_Encode2(GIFBS_isGFX12Plus_isWave64),
        GIM_CheckIntrinsicID, /*MI*/0, /*Op*/1, GIMT_Encode2(Intrinsic::amdgcn_wmma_i32_16x16x16_iu4),
        GIM_CheckType, /*MI*/0, /*Op*/0, /*Type*/GILLT_v4s32,
        GIM_CheckType, /*MI*/0, /*Op*/3, /*Type*/GILLT_s32,
        GIM_CheckType, /*MI*/0, /*Op*/5, /*Type*/GILLT_s32,
        GIM_CheckType, /*MI*/0, /*Op*/6, /*Type*/GILLT_v4s32,
        GIM_CheckRegBankForClass, /*MI*/0, /*Op*/0, /*RC*/GIMT_Encode2(AMDGPU::VReg_128RegClassID),
        // MIs[0] clamp
        // No operand predicates
        GIM_CheckComplexPattern, /*MI*/0, /*Op*/2, /*Renderer*/GIMT_Encode2(0), GIMT_Encode2(GICP_gi_vop3pmodsneg),
        GIM_CheckComplexPattern, /*MI*/0, /*Op*/4, /*Renderer*/GIMT_Encode2(1), GIMT_Encode2(GICP_gi_vop3pmodsneg),
        GIM_CheckComplexPattern, /*MI*/0, /*Op*/6, /*Renderer*/GIMT_Encode2(2), GIMT_Encode2(GICP_gi_wmmavisrc),
        // (intrinsic_wo_chain:{ *:[v4i32] } 2819:{ *:[iPTR] }, (VOP3PModsNeg:{ *:[i1] } i32:{ *:[i32] }:$src0_modifiers), i32:{ *:[i32] }:$src0, (VOP3PModsNeg:{ *:[i1] } i32:{ *:[i32] }:$src1_modifiers), i32:{ *:[i32] }:$src1, (WMMAVISrc:{ *:[v4i32] } v4i32:{ *:[v4i32] }:$src2), i1:{ *:[i1] }:$clamp)  =>  (V_WMMA_I32_16X16X16_IU4_w64_threeaddr:{ *:[v4i32] } i32:{ *:[i32] }:$src0_modifiers, i32:{ *:[i32] }:$src0, i32:{ *:[i32] }:$src1_modifiers, i32:{ *:[i32] }:$src1, v4i32:{ *:[v4i32] }:$src2, i1:{ *:[i1] }:$clamp)
        GIR_BuildMI, /*InsnID*/0, /*Opcode*/GIMT_Encode2(AMDGPU::V_WMMA_I32_16X16X16_IU4_w64_threeaddr),
        GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/0, // DstI[vdst]
        GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/0, // src0_modifiers
        GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/3, // src0
        GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(1), /*SubOperand*/0, // src1_modifiers
        GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/5, // src1
        GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(2), /*SubOperand*/0, // src2
        GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/7, // clamp
        GIR_AddImm8, /*InsnID*/0, /*Imm*/0,
        GIR_ConstrainSelectedInstOperands, /*InsnID*/0,
        GIR_EraseFromParent, /*InsnID*/0,
        // GIR_Coverage, 2379,
        GIR_Done,
      // Label 3510: @228122
      GIM_Try, /*On fail goto*//*Label 3511*/ GIMT_Encode4(228220), // Rule ID 2389 //
        GIM_CheckFeatures, GIMT_Encode2(GIFBS_isGFX12Plus_isWave64),
        GIM_CheckIntrinsicID, /*MI*/0, /*Op*/1, GIMT_Encode2(Intrinsic::amdgcn_wmma_i32_16x16x32_iu4),
        GIM_CheckType, /*MI*/0, /*Op*/0, /*Type*/GILLT_v4s32,
        GIM_CheckType, /*MI*/0, /*Op*/3, /*Type*/GILLT_s32,
        GIM_CheckType, /*MI*/0, /*Op*/5, /*Type*/GILLT_s32,
        GIM_CheckType, /*MI*/0, /*Op*/6, /*Type*/GILLT_v4s32,
        GIM_CheckRegBankForClass, /*MI*/0, /*Op*/0, /*RC*/GIMT_Encode2(AMDGPU::VReg_128RegClassID),
        // MIs[0] clamp
        // No operand predicates
        GIM_CheckComplexPattern, /*MI*/0, /*Op*/2, /*Renderer*/GIMT_Encode2(0), GIMT_Encode2(GICP_gi_vop3pmodsneg),
        GIM_CheckComplexPattern, /*MI*/0, /*Op*/4, /*Renderer*/GIMT_Encode2(1), GIMT_Encode2(GICP_gi_vop3pmodsneg),
        GIM_CheckComplexPattern, /*MI*/0, /*Op*/6, /*Renderer*/GIMT_Encode2(2), GIMT_Encode2(GICP_gi_wmmavisrc),
        // (intrinsic_wo_chain:{ *:[v4i32] } 2821:{ *:[iPTR] }, (VOP3PModsNeg:{ *:[i1] } i32:{ *:[i32] }:$src0_modifiers), i32:{ *:[i32] }:$src0, (VOP3PModsNeg:{ *:[i1] } i32:{ *:[i32] }:$src1_modifiers), i32:{ *:[i32] }:$src1, (WMMAVISrc:{ *:[v4i32] } v4i32:{ *:[v4i32] }:$src2), i1:{ *:[i1] }:$clamp)  =>  (V_WMMA_I32_16X16X32_IU4_w64_threeaddr:{ *:[v4i32] } i32:{ *:[i32] }:$src0_modifiers, i32:{ *:[i32] }:$src0, i32:{ *:[i32] }:$src1_modifiers, i32:{ *:[i32] }:$src1, v4i32:{ *:[v4i32] }:$src2, i1:{ *:[i1] }:$clamp)
        GIR_BuildMI, /*InsnID*/0, /*Opcode*/GIMT_Encode2(AMDGPU::V_WMMA_I32_16X16X32_IU4_w64_threeaddr),
        GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/0, // DstI[vdst]
        GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/0, // src0_modifiers
        GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/3, // src0
        GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(1), /*SubOperand*/0, // src1_modifiers
        GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/5, // src1
        GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(2), /*SubOperand*/0, // src2
        GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/7, // clamp
        GIR_AddImm8, /*InsnID*/0, /*Imm*/0,
        GIR_ConstrainSelectedInstOperands, /*InsnID*/0,
        GIR_EraseFromParent, /*InsnID*/0,
        // GIR_Coverage, 2389,
        GIR_Done,
      // Label 3511: @228220
      GIM_Try, /*On fail goto*//*Label 3512*/ GIMT_Encode4(228319), // Rule ID 2320 //
        GIM_CheckFeatures, GIMT_Encode2(GIFBS_isGFX11Only_isWave32),
        GIM_CheckIntrinsicID, /*MI*/0, /*Op*/1, GIMT_Encode2(Intrinsic::amdgcn_wmma_i32_16x16x16_iu8),
        GIM_CheckType, /*MI*/0, /*Op*/0, /*Type*/GILLT_v8s32,
        GIM_CheckType, /*MI*/0, /*Op*/3, /*Type*/GILLT_v4s32,
        GIM_CheckType, /*MI*/0, /*Op*/5, /*Type*/GILLT_v4s32,
        GIM_CheckType, /*MI*/0, /*Op*/6, /*Type*/GILLT_v8s32,
        GIM_CheckRegBankForClass, /*MI*/0, /*Op*/0, /*RC*/GIMT_Encode2(AMDGPU::VReg_256RegClassID),
        // MIs[0] clamp
        GIM_CheckIsImm, /*MI*/0, /*Op*/7,
        GIM_CheckComplexPattern, /*MI*/0, /*Op*/2, /*Renderer*/GIMT_Encode2(0), GIMT_Encode2(GICP_gi_vop3pmodsneg),
        GIM_CheckComplexPattern, /*MI*/0, /*Op*/4, /*Renderer*/GIMT_Encode2(1), GIMT_Encode2(GICP_gi_vop3pmodsneg),
        // (intrinsic_wo_chain:{ *:[v8i32] } 2820:{ *:[iPTR] }, (VOP3PModsNeg:{ *:[i1] } i32:{ *:[i32] }:$src0_modifiers), v4i32:{ *:[v4i32] }:$src0, (VOP3PModsNeg:{ *:[i1] } i32:{ *:[i32] }:$src1_modifiers), v4i32:{ *:[v4i32] }:$src1, v8i32:{ *:[v8i32] }:$src2, (timm:{ *:[i1] }):$clamp)  =>  (V_WMMA_I32_16X16X16_IU8_twoaddr_w32:{ *:[v8i32] } i32:{ *:[i32] }:$src0_modifiers, v4i32:{ *:[v4i32] }:$src0, i32:{ *:[i32] }:$src1_modifiers, v4i32:{ *:[v4i32] }:$src1, 8:{ *:[i32] }, v8i32:{ *:[v8i32] }:$src2, i1:{ *:[i1] }:$clamp)
        GIR_BuildMI, /*InsnID*/0, /*Opcode*/GIMT_Encode2(AMDGPU::V_WMMA_I32_16X16X16_IU8_twoaddr_w32),
        GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/0, // DstI[vdst]
        GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/0, // src0_modifiers
        GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/3, // src0
        GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(1), /*SubOperand*/0, // src1_modifiers
        GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/5, // src1
        GIR_AddImm8, /*InsnID*/0, /*Imm*/8,
        GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/6, // src2
        GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/7, // clamp
        GIR_AddImm8, /*InsnID*/0, /*Imm*/0,
        GIR_AddImm8, /*InsnID*/0, /*Imm*/0,
        GIR_ConstrainSelectedInstOperands, /*InsnID*/0,
        GIR_EraseFromParent, /*InsnID*/0,
        // GIR_Coverage, 2320,
        GIR_Done,
      // Label 3512: @228319
      GIM_Try, /*On fail goto*//*Label 3513*/ GIMT_Encode4(228418), // Rule ID 2326 //
        GIM_CheckFeatures, GIMT_Encode2(GIFBS_isGFX11Only_isWave32),
        GIM_CheckIntrinsicID, /*MI*/0, /*Op*/1, GIMT_Encode2(Intrinsic::amdgcn_wmma_i32_16x16x16_iu4),
        GIM_CheckType, /*MI*/0, /*Op*/0, /*Type*/GILLT_v8s32,
        GIM_CheckType, /*MI*/0, /*Op*/3, /*Type*/GILLT_v2s32,
        GIM_CheckType, /*MI*/0, /*Op*/5, /*Type*/GILLT_v2s32,
        GIM_CheckType, /*MI*/0, /*Op*/6, /*Type*/GILLT_v8s32,
        GIM_CheckRegBankForClass, /*MI*/0, /*Op*/0, /*RC*/GIMT_Encode2(AMDGPU::VReg_256RegClassID),
        // MIs[0] clamp
        GIM_CheckIsImm, /*MI*/0, /*Op*/7,
        GIM_CheckComplexPattern, /*MI*/0, /*Op*/2, /*Renderer*/GIMT_Encode2(0), GIMT_Encode2(GICP_gi_vop3pmodsneg),
        GIM_CheckComplexPattern, /*MI*/0, /*Op*/4, /*Renderer*/GIMT_Encode2(1), GIMT_Encode2(GICP_gi_vop3pmodsneg),
        // (intrinsic_wo_chain:{ *:[v8i32] } 2819:{ *:[iPTR] }, (VOP3PModsNeg:{ *:[i1] } i32:{ *:[i32] }:$src0_modifiers), v2i32:{ *:[v2i32] }:$src0, (VOP3PModsNeg:{ *:[i1] } i32:{ *:[i32] }:$src1_modifiers), v2i32:{ *:[v2i32] }:$src1, v8i32:{ *:[v8i32] }:$src2, (timm:{ *:[i1] }):$clamp)  =>  (V_WMMA_I32_16X16X16_IU4_twoaddr_w32:{ *:[v8i32] } i32:{ *:[i32] }:$src0_modifiers, v2i32:{ *:[v2i32] }:$src0, i32:{ *:[i32] }:$src1_modifiers, v2i32:{ *:[v2i32] }:$src1, 8:{ *:[i32] }, v8i32:{ *:[v8i32] }:$src2, i1:{ *:[i1] }:$clamp)
        GIR_BuildMI, /*InsnID*/0, /*Opcode*/GIMT_Encode2(AMDGPU::V_WMMA_I32_16X16X16_IU4_twoaddr_w32),
        GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/0, // DstI[vdst]
        GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/0, // src0_modifiers
        GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/3, // src0
        GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(1), /*SubOperand*/0, // src1_modifiers
        GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/5, // src1
        GIR_AddImm8, /*InsnID*/0, /*Imm*/8,
        GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/6, // src2
        GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/7, // clamp
        GIR_AddImm8, /*InsnID*/0, /*Imm*/0,
        GIR_AddImm8, /*InsnID*/0, /*Imm*/0,
        GIR_ConstrainSelectedInstOperands, /*InsnID*/0,
        GIR_EraseFromParent, /*InsnID*/0,
        // GIR_Coverage, 2326,
        GIR_Done,
      // Label 3513: @228418
      GIM_Try, /*On fail goto*//*Label 3514*/ GIMT_Encode4(228517), // Rule ID 2333 //
        GIM_CheckFeatures, GIMT_Encode2(GIFBS_isGFX11Only_isWave64),
        GIM_CheckIntrinsicID, /*MI*/0, /*Op*/1, GIMT_Encode2(Intrinsic::amdgcn_wmma_i32_16x16x16_iu8),
        GIM_CheckType, /*MI*/0, /*Op*/0, /*Type*/GILLT_v4s32,
        GIM_CheckType, /*MI*/0, /*Op*/3, /*Type*/GILLT_v4s32,
        GIM_CheckType, /*MI*/0, /*Op*/5, /*Type*/GILLT_v4s32,
        GIM_CheckType, /*MI*/0, /*Op*/6, /*Type*/GILLT_v4s32,
        GIM_CheckRegBankForClass, /*MI*/0, /*Op*/0, /*RC*/GIMT_Encode2(AMDGPU::VReg_128RegClassID),
        // MIs[0] clamp
        GIM_CheckIsImm, /*MI*/0, /*Op*/7,
        GIM_CheckComplexPattern, /*MI*/0, /*Op*/2, /*Renderer*/GIMT_Encode2(0), GIMT_Encode2(GICP_gi_vop3pmodsneg),
        GIM_CheckComplexPattern, /*MI*/0, /*Op*/4, /*Renderer*/GIMT_Encode2(1), GIMT_Encode2(GICP_gi_vop3pmodsneg),
        // (intrinsic_wo_chain:{ *:[v4i32] } 2820:{ *:[iPTR] }, (VOP3PModsNeg:{ *:[i1] } i32:{ *:[i32] }:$src0_modifiers), v4i32:{ *:[v4i32] }:$src0, (VOP3PModsNeg:{ *:[i1] } i32:{ *:[i32] }:$src1_modifiers), v4i32:{ *:[v4i32] }:$src1, v4i32:{ *:[v4i32] }:$src2, (timm:{ *:[i1] }):$clamp)  =>  (V_WMMA_I32_16X16X16_IU8_twoaddr_w64:{ *:[v4i32] } i32:{ *:[i32] }:$src0_modifiers, v4i32:{ *:[v4i32] }:$src0, i32:{ *:[i32] }:$src1_modifiers, v4i32:{ *:[v4i32] }:$src1, 8:{ *:[i32] }, v4i32:{ *:[v4i32] }:$src2, i1:{ *:[i1] }:$clamp)
        GIR_BuildMI, /*InsnID*/0, /*Opcode*/GIMT_Encode2(AMDGPU::V_WMMA_I32_16X16X16_IU8_twoaddr_w64),
        GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/0, // DstI[vdst]
        GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/0, // src0_modifiers
        GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/3, // src0
        GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(1), /*SubOperand*/0, // src1_modifiers
        GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/5, // src1
        GIR_AddImm8, /*InsnID*/0, /*Imm*/8,
        GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/6, // src2
        GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/7, // clamp
        GIR_AddImm8, /*InsnID*/0, /*Imm*/0,
        GIR_AddImm8, /*InsnID*/0, /*Imm*/0,
        GIR_ConstrainSelectedInstOperands, /*InsnID*/0,
        GIR_EraseFromParent, /*InsnID*/0,
        // GIR_Coverage, 2333,
        GIR_Done,
      // Label 3514: @228517
      GIM_Try, /*On fail goto*//*Label 3515*/ GIMT_Encode4(228616), // Rule ID 2334 //
        GIM_CheckFeatures, GIMT_Encode2(GIFBS_isGFX11Only_isWave64),
        GIM_CheckIntrinsicID, /*MI*/0, /*Op*/1, GIMT_Encode2(Intrinsic::amdgcn_wmma_i32_16x16x16_iu4),
        GIM_CheckType, /*MI*/0, /*Op*/0, /*Type*/GILLT_v4s32,
        GIM_CheckType, /*MI*/0, /*Op*/3, /*Type*/GILLT_v2s32,
        GIM_CheckType, /*MI*/0, /*Op*/5, /*Type*/GILLT_v2s32,
        GIM_CheckType, /*MI*/0, /*Op*/6, /*Type*/GILLT_v4s32,
        GIM_CheckRegBankForClass, /*MI*/0, /*Op*/0, /*RC*/GIMT_Encode2(AMDGPU::VReg_128RegClassID),
        // MIs[0] clamp
        GIM_CheckIsImm, /*MI*/0, /*Op*/7,
        GIM_CheckComplexPattern, /*MI*/0, /*Op*/2, /*Renderer*/GIMT_Encode2(0), GIMT_Encode2(GICP_gi_vop3pmodsneg),
        GIM_CheckComplexPattern, /*MI*/0, /*Op*/4, /*Renderer*/GIMT_Encode2(1), GIMT_Encode2(GICP_gi_vop3pmodsneg),
        // (intrinsic_wo_chain:{ *:[v4i32] } 2819:{ *:[iPTR] }, (VOP3PModsNeg:{ *:[i1] } i32:{ *:[i32] }:$src0_modifiers), v2i32:{ *:[v2i32] }:$src0, (VOP3PModsNeg:{ *:[i1] } i32:{ *:[i32] }:$src1_modifiers), v2i32:{ *:[v2i32] }:$src1, v4i32:{ *:[v4i32] }:$src2, (timm:{ *:[i1] }):$clamp)  =>  (V_WMMA_I32_16X16X16_IU4_twoaddr_w64:{ *:[v4i32] } i32:{ *:[i32] }:$src0_modifiers, v2i32:{ *:[v2i32] }:$src0, i32:{ *:[i32] }:$src1_modifiers, v2i32:{ *:[v2i32] }:$src1, 8:{ *:[i32] }, v4i32:{ *:[v4i32] }:$src2, i1:{ *:[i1] }:$clamp)
        GIR_BuildMI, /*InsnID*/0, /*Opcode*/GIMT_Encode2(AMDGPU::V_WMMA_I32_16X16X16_IU4_twoaddr_w64),
        GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/0, // DstI[vdst]
        GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/0, // src0_modifiers
        GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/3, // src0
        GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(1), /*SubOperand*/0, // src1_modifiers
        GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/5, // src1
        GIR_AddImm8, /*InsnID*/0, /*Imm*/8,
        GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/6, // src2
        GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/7, // clamp
        GIR_AddImm8, /*InsnID*/0, /*Imm*/0,
        GIR_AddImm8, /*InsnID*/0, /*Imm*/0,
        GIR_ConstrainSelectedInstOperands, /*InsnID*/0,
        GIR_EraseFromParent, /*InsnID*/0,
        // GIR_Coverage, 2334,
        GIR_Done,
      // Label 3515: @228616
      GIM_Try, /*On fail goto*//*Label 3516*/ GIMT_Encode4(228706), // Rule ID 2343 //
        GIM_CheckFeatures, GIMT_Encode2(GIFBS_isGFX12Plus_isWave32),
        GIM_CheckIntrinsicID, /*MI*/0, /*Op*/1, GIMT_Encode2(Intrinsic::amdgcn_wmma_i32_16x16x16_iu8),
        GIM_CheckType, /*MI*/0, /*Op*/0, /*Type*/GILLT_v8s32,
        GIM_CheckType, /*MI*/0, /*Op*/3, /*Type*/GILLT_v2s32,
        GIM_CheckType, /*MI*/0, /*Op*/5, /*Type*/GILLT_v2s32,
        GIM_CheckType, /*MI*/0, /*Op*/6, /*Type*/GILLT_v8s32,
        GIM_CheckRegBankForClass, /*MI*/0, /*Op*/0, /*RC*/GIMT_Encode2(AMDGPU::VReg_256RegClassID),
        // MIs[0] clamp
        // No operand predicates
        GIM_CheckComplexPattern, /*MI*/0, /*Op*/2, /*Renderer*/GIMT_Encode2(0), GIMT_Encode2(GICP_gi_vop3pmodsneg),
        GIM_CheckComplexPattern, /*MI*/0, /*Op*/4, /*Renderer*/GIMT_Encode2(1), GIMT_Encode2(GICP_gi_vop3pmodsneg),
        // (intrinsic_wo_chain:{ *:[v8i32] } 2820:{ *:[iPTR] }, (VOP3PModsNeg:{ *:[i1] } i32:{ *:[i32] }:$src0_modifiers), v2i32:{ *:[v2i32] }:$src0, (VOP3PModsNeg:{ *:[i1] } i32:{ *:[i32] }:$src1_modifiers), v2i32:{ *:[v2i32] }:$src1, v8i32:{ *:[v8i32] }:$src2, i1:{ *:[i1] }:$clamp)  =>  (V_WMMA_I32_16X16X16_IU8_w32_twoaddr:{ *:[v8i32] } i32:{ *:[i32] }:$src0_modifiers, v2i32:{ *:[v2i32] }:$src0, i32:{ *:[i32] }:$src1_modifiers, v2i32:{ *:[v2i32] }:$src1, v8i32:{ *:[v8i32] }:$src2, i1:{ *:[i1] }:$clamp)
        GIR_BuildMI, /*InsnID*/0, /*Opcode*/GIMT_Encode2(AMDGPU::V_WMMA_I32_16X16X16_IU8_w32_twoaddr),
        GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/0, // DstI[vdst]
        GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/0, // src0_modifiers
        GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/3, // src0
        GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(1), /*SubOperand*/0, // src1_modifiers
        GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/5, // src1
        GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/6, // src2
        GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/7, // clamp
        GIR_AddImm8, /*InsnID*/0, /*Imm*/0,
        GIR_ConstrainSelectedInstOperands, /*InsnID*/0,
        GIR_EraseFromParent, /*InsnID*/0,
        // GIR_Coverage, 2343,
        GIR_Done,
      // Label 3516: @228706
      GIM_Try, /*On fail goto*//*Label 3517*/ GIMT_Encode4(228796), // Rule ID 2345 //
        GIM_CheckFeatures, GIMT_Encode2(GIFBS_isGFX12Plus_isWave32),
        GIM_CheckIntrinsicID, /*MI*/0, /*Op*/1, GIMT_Encode2(Intrinsic::amdgcn_wmma_i32_16x16x16_iu4),
        GIM_CheckType, /*MI*/0, /*Op*/0, /*Type*/GILLT_v8s32,
        GIM_CheckType, /*MI*/0, /*Op*/3, /*Type*/GILLT_s32,
        GIM_CheckType, /*MI*/0, /*Op*/5, /*Type*/GILLT_s32,
        GIM_CheckType, /*MI*/0, /*Op*/6, /*Type*/GILLT_v8s32,
        GIM_CheckRegBankForClass, /*MI*/0, /*Op*/0, /*RC*/GIMT_Encode2(AMDGPU::VReg_256RegClassID),
        // MIs[0] clamp
        // No operand predicates
        GIM_CheckComplexPattern, /*MI*/0, /*Op*/2, /*Renderer*/GIMT_Encode2(0), GIMT_Encode2(GICP_gi_vop3pmodsneg),
        GIM_CheckComplexPattern, /*MI*/0, /*Op*/4, /*Renderer*/GIMT_Encode2(1), GIMT_Encode2(GICP_gi_vop3pmodsneg),
        // (intrinsic_wo_chain:{ *:[v8i32] } 2819:{ *:[iPTR] }, (VOP3PModsNeg:{ *:[i1] } i32:{ *:[i32] }:$src0_modifiers), i32:{ *:[i32] }:$src0, (VOP3PModsNeg:{ *:[i1] } i32:{ *:[i32] }:$src1_modifiers), i32:{ *:[i32] }:$src1, v8i32:{ *:[v8i32] }:$src2, i1:{ *:[i1] }:$clamp)  =>  (V_WMMA_I32_16X16X16_IU4_w32_twoaddr:{ *:[v8i32] } i32:{ *:[i32] }:$src0_modifiers, i32:{ *:[i32] }:$src0, i32:{ *:[i32] }:$src1_modifiers, i32:{ *:[i32] }:$src1, v8i32:{ *:[v8i32] }:$src2, i1:{ *:[i1] }:$clamp)
        GIR_BuildMI, /*InsnID*/0, /*Opcode*/GIMT_Encode2(AMDGPU::V_WMMA_I32_16X16X16_IU4_w32_twoaddr),
        GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/0, // DstI[vdst]
        GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/0, // src0_modifiers
        GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/3, // src0
        GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(1), /*SubOperand*/0, // src1_modifiers
        GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/5, // src1
        GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/6, // src2
        GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/7, // clamp
        GIR_AddImm8, /*InsnID*/0, /*Imm*/0,
        GIR_ConstrainSelectedInstOperands, /*InsnID*/0,
        GIR_EraseFromParent, /*InsnID*/0,
        // GIR_Coverage, 2345,
        GIR_Done,
      // Label 3517: @228796
      GIM_Try, /*On fail goto*//*Label 3518*/ GIMT_Encode4(228886), // Rule ID 2355 //
        GIM_CheckFeatures, GIMT_Encode2(GIFBS_isGFX12Plus_isWave32),
        GIM_CheckIntrinsicID, /*MI*/0, /*Op*/1, GIMT_Encode2(Intrinsic::amdgcn_wmma_i32_16x16x32_iu4),
        GIM_CheckType, /*MI*/0, /*Op*/0, /*Type*/GILLT_v8s32,
        GIM_CheckType, /*MI*/0, /*Op*/3, /*Type*/GILLT_v2s32,
        GIM_CheckType, /*MI*/0, /*Op*/5, /*Type*/GILLT_v2s32,
        GIM_CheckType, /*MI*/0, /*Op*/6, /*Type*/GILLT_v8s32,
        GIM_CheckRegBankForClass, /*MI*/0, /*Op*/0, /*RC*/GIMT_Encode2(AMDGPU::VReg_256RegClassID),
        // MIs[0] clamp
        // No operand predicates
        GIM_CheckComplexPattern, /*MI*/0, /*Op*/2, /*Renderer*/GIMT_Encode2(0), GIMT_Encode2(GICP_gi_vop3pmodsneg),
        GIM_CheckComplexPattern, /*MI*/0, /*Op*/4, /*Renderer*/GIMT_Encode2(1), GIMT_Encode2(GICP_gi_vop3pmodsneg),
        // (intrinsic_wo_chain:{ *:[v8i32] } 2821:{ *:[iPTR] }, (VOP3PModsNeg:{ *:[i1] } i32:{ *:[i32] }:$src0_modifiers), v2i32:{ *:[v2i32] }:$src0, (VOP3PModsNeg:{ *:[i1] } i32:{ *:[i32] }:$src1_modifiers), v2i32:{ *:[v2i32] }:$src1, v8i32:{ *:[v8i32] }:$src2, i1:{ *:[i1] }:$clamp)  =>  (V_WMMA_I32_16X16X32_IU4_w32_twoaddr:{ *:[v8i32] } i32:{ *:[i32] }:$src0_modifiers, v2i32:{ *:[v2i32] }:$src0, i32:{ *:[i32] }:$src1_modifiers, v2i32:{ *:[v2i32] }:$src1, v8i32:{ *:[v8i32] }:$src2, i1:{ *:[i1] }:$clamp)
        GIR_BuildMI, /*InsnID*/0, /*Opcode*/GIMT_Encode2(AMDGPU::V_WMMA_I32_16X16X32_IU4_w32_twoaddr),
        GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/0, // DstI[vdst]
        GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/0, // src0_modifiers
        GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/3, // src0
        GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(1), /*SubOperand*/0, // src1_modifiers
        GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/5, // src1
        GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/6, // src2
        GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/7, // clamp
        GIR_AddImm8, /*InsnID*/0, /*Imm*/0,
        GIR_ConstrainSelectedInstOperands, /*InsnID*/0,
        GIR_EraseFromParent, /*InsnID*/0,
        // GIR_Coverage, 2355,
        GIR_Done,
      // Label 3518: @228886
      GIM_Try, /*On fail goto*//*Label 3519*/ GIMT_Encode4(228976), // Rule ID 2376 //
        GIM_CheckFeatures, GIMT_Encode2(GIFBS_isGFX12Plus_isWave64),
        GIM_CheckIntrinsicID, /*MI*/0, /*Op*/1, GIMT_Encode2(Intrinsic::amdgcn_wmma_i32_16x16x16_iu8),
        GIM_CheckType, /*MI*/0, /*Op*/0, /*Type*/GILLT_v4s32,
        GIM_CheckType, /*MI*/0, /*Op*/3, /*Type*/GILLT_s32,
        GIM_CheckType, /*MI*/0, /*Op*/5, /*Type*/GILLT_s32,
        GIM_CheckType, /*MI*/0, /*Op*/6, /*Type*/GILLT_v4s32,
        GIM_CheckRegBankForClass, /*MI*/0, /*Op*/0, /*RC*/GIMT_Encode2(AMDGPU::VReg_128RegClassID),
        // MIs[0] clamp
        // No operand predicates
        GIM_CheckComplexPattern, /*MI*/0, /*Op*/2, /*Renderer*/GIMT_Encode2(0), GIMT_Encode2(GICP_gi_vop3pmodsneg),
        GIM_CheckComplexPattern, /*MI*/0, /*Op*/4, /*Renderer*/GIMT_Encode2(1), GIMT_Encode2(GICP_gi_vop3pmodsneg),
        // (intrinsic_wo_chain:{ *:[v4i32] } 2820:{ *:[iPTR] }, (VOP3PModsNeg:{ *:[i1] } i32:{ *:[i32] }:$src0_modifiers), i32:{ *:[i32] }:$src0, (VOP3PModsNeg:{ *:[i1] } i32:{ *:[i32] }:$src1_modifiers), i32:{ *:[i32] }:$src1, v4i32:{ *:[v4i32] }:$src2, i1:{ *:[i1] }:$clamp)  =>  (V_WMMA_I32_16X16X16_IU8_w64_twoaddr:{ *:[v4i32] } i32:{ *:[i32] }:$src0_modifiers, i32:{ *:[i32] }:$src0, i32:{ *:[i32] }:$src1_modifiers, i32:{ *:[i32] }:$src1, v4i32:{ *:[v4i32] }:$src2, i1:{ *:[i1] }:$clamp)
        GIR_BuildMI, /*InsnID*/0, /*Opcode*/GIMT_Encode2(AMDGPU::V_WMMA_I32_16X16X16_IU8_w64_twoaddr),
        GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/0, // DstI[vdst]
        GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/0, // src0_modifiers
        GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/3, // src0
        GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(1), /*SubOperand*/0, // src1_modifiers
        GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/5, // src1
        GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/6, // src2
        GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/7, // clamp
        GIR_AddImm8, /*InsnID*/0, /*Imm*/0,
        GIR_ConstrainSelectedInstOperands, /*InsnID*/0,
        GIR_EraseFromParent, /*InsnID*/0,
        // GIR_Coverage, 2376,
        GIR_Done,
      // Label 3519: @228976
      GIM_Try, /*On fail goto*//*Label 3520*/ GIMT_Encode4(229066), // Rule ID 2378 //
        GIM_CheckFeatures, GIMT_Encode2(GIFBS_isGFX12Plus_isWave64),
        GIM_CheckIntrinsicID, /*MI*/0, /*Op*/1, GIMT_Encode2(Intrinsic::amdgcn_wmma_i32_16x16x16_iu4),
        GIM_CheckType, /*MI*/0, /*Op*/0, /*Type*/GILLT_v4s32,
        GIM_CheckType, /*MI*/0, /*Op*/3, /*Type*/GILLT_s32,
        GIM_CheckType, /*MI*/0, /*Op*/5, /*Type*/GILLT_s32,
        GIM_CheckType, /*MI*/0, /*Op*/6, /*Type*/GILLT_v4s32,
        GIM_CheckRegBankForClass, /*MI*/0, /*Op*/0, /*RC*/GIMT_Encode2(AMDGPU::VReg_128RegClassID),
        // MIs[0] clamp
        // No operand predicates
        GIM_CheckComplexPattern, /*MI*/0, /*Op*/2, /*Renderer*/GIMT_Encode2(0), GIMT_Encode2(GICP_gi_vop3pmodsneg),
        GIM_CheckComplexPattern, /*MI*/0, /*Op*/4, /*Renderer*/GIMT_Encode2(1), GIMT_Encode2(GICP_gi_vop3pmodsneg),
        // (intrinsic_wo_chain:{ *:[v4i32] } 2819:{ *:[iPTR] }, (VOP3PModsNeg:{ *:[i1] } i32:{ *:[i32] }:$src0_modifiers), i32:{ *:[i32] }:$src0, (VOP3PModsNeg:{ *:[i1] } i32:{ *:[i32] }:$src1_modifiers), i32:{ *:[i32] }:$src1, v4i32:{ *:[v4i32] }:$src2, i1:{ *:[i1] }:$clamp)  =>  (V_WMMA_I32_16X16X16_IU4_w64_twoaddr:{ *:[v4i32] } i32:{ *:[i32] }:$src0_modifiers, i32:{ *:[i32] }:$src0, i32:{ *:[i32] }:$src1_modifiers, i32:{ *:[i32] }:$src1, v4i32:{ *:[v4i32] }:$src2, i1:{ *:[i1] }:$clamp)
        GIR_BuildMI, /*InsnID*/0, /*Opcode*/GIMT_Encode2(AMDGPU::V_WMMA_I32_16X16X16_IU4_w64_twoaddr),
        GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/0, // DstI[vdst]
        GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/0, // src0_modifiers
        GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/3, // src0
        GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(1), /*SubOperand*/0, // src1_modifiers
        GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/5, // src1
        GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/6, // src2
        GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/7, // clamp
        GIR_AddImm8, /*InsnID*/0, /*Imm*/0,
        GIR_ConstrainSelectedInstOperands, /*InsnID*/0,
        GIR_EraseFromParent, /*InsnID*/0,
        // GIR_Coverage, 2378,
        GIR_Done,
      // Label 3520: @229066
      GIM_Try, /*On fail goto*//*Label 3521*/ GIMT_Encode4(229156), // Rule ID 2388 //
        GIM_CheckFeatures, GIMT_Encode2(GIFBS_isGFX12Plus_isWave64),
        GIM_CheckIntrinsicID, /*MI*/0, /*Op*/1, GIMT_Encode2(Intrinsic::amdgcn_wmma_i32_16x16x32_iu4),
        GIM_CheckType, /*MI*/0, /*Op*/0, /*Type*/GILLT_v4s32,
        GIM_CheckType, /*MI*/0, /*Op*/3, /*Type*/GILLT_s32,
        GIM_CheckType, /*MI*/0, /*Op*/5, /*Type*/GILLT_s32,
        GIM_CheckType, /*MI*/0, /*Op*/6, /*Type*/GILLT_v4s32,
        GIM_CheckRegBankForClass, /*MI*/0, /*Op*/0, /*RC*/GIMT_Encode2(AMDGPU::VReg_128RegClassID),
        // MIs[0] clamp
        // No operand predicates
        GIM_CheckComplexPattern, /*MI*/0, /*Op*/2, /*Renderer*/GIMT_Encode2(0), GIMT_Encode2(GICP_gi_vop3pmodsneg),
        GIM_CheckComplexPattern, /*MI*/0, /*Op*/4, /*Renderer*/GIMT_Encode2(1), GIMT_Encode2(GICP_gi_vop3pmodsneg),
        // (intrinsic_wo_chain:{ *:[v4i32] } 2821:{ *:[iPTR] }, (VOP3PModsNeg:{ *:[i1] } i32:{ *:[i32] }:$src0_modifiers), i32:{ *:[i32] }:$src0, (VOP3PModsNeg:{ *:[i1] } i32:{ *:[i32] }:$src1_modifiers), i32:{ *:[i32] }:$src1, v4i32:{ *:[v4i32] }:$src2, i1:{ *:[i1] }:$clamp)  =>  (V_WMMA_I32_16X16X32_IU4_w64_twoaddr:{ *:[v4i32] } i32:{ *:[i32] }:$src0_modifiers, i32:{ *:[i32] }:$src0, i32:{ *:[i32] }:$src1_modifiers, i32:{ *:[i32] }:$src1, v4i32:{ *:[v4i32] }:$src2, i1:{ *:[i1] }:$clamp)
        GIR_BuildMI, /*InsnID*/0, /*Opcode*/GIMT_Encode2(AMDGPU::V_WMMA_I32_16X16X32_IU4_w64_twoaddr),
        GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/0, // DstI[vdst]
        GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/0, // src0_modifiers
        GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/3, // src0
        GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(1), /*SubOperand*/0, // src1_modifiers
        GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/5, // src1
        GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/6, // src2
        GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/7, // clamp
        GIR_AddImm8, /*InsnID*/0, /*Imm*/0,
        GIR_ConstrainSelectedInstOperands, /*InsnID*/0,
        GIR_EraseFromParent, /*InsnID*/0,
        // GIR_Coverage, 2388,
        GIR_Done,
      // Label 3521: @229156
      GIM_Try, /*On fail goto*//*Label 3522*/ GIMT_Encode4(229243), // Rule ID 2081 //
        GIM_CheckFeatures, GIMT_Encode2(GIFBS_isGFX8Plus),
        GIM_CheckIntrinsicID, /*MI*/0, /*Op*/1, GIMT_Encode2(Intrinsic::amdgcn_update_dpp),
        GIM_CheckType, /*MI*/0, /*Op*/0, /*Type*/GILLT_s32,
        GIM_CheckType, /*MI*/0, /*Op*/2, /*Type*/GILLT_s32,
        GIM_CheckType, /*MI*/0, /*Op*/3, /*Type*/GILLT_s32,
        GIM_CheckRegBankForClass, /*MI*/0, /*Op*/0, /*RC*/GIMT_Encode2(AMDGPU::VGPR_32RegClassID),
        // MIs[0] dpp_ctrl
        GIM_CheckIsImm, /*MI*/0, /*Op*/4,
        // MIs[0] row_mask
        GIM_CheckIsImm, /*MI*/0, /*Op*/5,
        // MIs[0] bank_mask
        GIM_CheckIsImm, /*MI*/0, /*Op*/6,
        // MIs[0] bound_ctrl
        GIM_CheckIsImm, /*MI*/0, /*Op*/7,
        // (intrinsic_wo_chain:{ *:[i32] } 2803:{ *:[iPTR] }, i32:{ *:[i32] }:$old, i32:{ *:[i32] }:$src, (timm:{ *:[i32] }):$dpp_ctrl, (timm:{ *:[i32] }):$row_mask, (timm:{ *:[i32] }):$bank_mask, (timm:{ *:[i1] }):$bound_ctrl)  =>  (V_MOV_B32_dpp:{ *:[i32] } VGPR_32:{ *:[i32] }:$old, VGPR_32:{ *:[i32] }:$src, (as_i32timm:{ *:[i32] } ?:{ *:[i32] }:$dpp_ctrl), (as_i32timm:{ *:[i32] } ?:{ *:[i32] }:$row_mask), (as_i32timm:{ *:[i32] } ?:{ *:[i32] }:$bank_mask), (as_i1timm:{ *:[i1] } ?:{ *:[i1] }:$bound_ctrl))
        GIR_BuildMI, /*InsnID*/0, /*Opcode*/GIMT_Encode2(AMDGPU::V_MOV_B32_dpp),
        GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/0, // DstI[vdst]
        GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/2, // old
        GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/3, // src
        GIR_CustomOperandRenderer, /*InsnID*/0, /*OldInsnID*/0, /*OpIdx*/4, /*OperandRenderer*/GIMT_Encode2(GICR_renderTruncTImm), // dpp_ctrl
        GIR_CustomOperandRenderer, /*InsnID*/0, /*OldInsnID*/0, /*OpIdx*/5, /*OperandRenderer*/GIMT_Encode2(GICR_renderTruncTImm), // row_mask
        GIR_CustomOperandRenderer, /*InsnID*/0, /*OldInsnID*/0, /*OpIdx*/6, /*OperandRenderer*/GIMT_Encode2(GICR_renderTruncTImm), // bank_mask
        GIR_CustomOperandRenderer, /*InsnID*/0, /*OldInsnID*/0, /*OpIdx*/7, /*OperandRenderer*/GIMT_Encode2(GICR_renderTruncTImm), // bound_ctrl
        GIR_ConstrainSelectedInstOperands, /*InsnID*/0,
        GIR_EraseFromParent, /*InsnID*/0,
        // GIR_Coverage, 2081,
        GIR_Done,
      // Label 3522: @229243
      GIM_Try, /*On fail goto*//*Label 3523*/ GIMT_Encode4(229330), // Rule ID 2082 //
        GIM_CheckFeatures, GIMT_Encode2(GIFBS_isGFX8Plus),
        GIM_CheckIntrinsicID, /*MI*/0, /*Op*/1, GIMT_Encode2(Intrinsic::amdgcn_update_dpp),
        GIM_CheckType, /*MI*/0, /*Op*/0, /*Type*/GILLT_s32,
        GIM_CheckType, /*MI*/0, /*Op*/2, /*Type*/GILLT_s32,
        GIM_CheckType, /*MI*/0, /*Op*/3, /*Type*/GILLT_s32,
        GIM_CheckRegBankForClass, /*MI*/0, /*Op*/0, /*RC*/GIMT_Encode2(AMDGPU::VGPR_32RegClassID),
        // MIs[0] dpp_ctrl
        GIM_CheckIsImm, /*MI*/0, /*Op*/4,
        // MIs[0] row_mask
        GIM_CheckIsImm, /*MI*/0, /*Op*/5,
        // MIs[0] bank_mask
        GIM_CheckIsImm, /*MI*/0, /*Op*/6,
        // MIs[0] bound_ctrl
        GIM_CheckIsImm, /*MI*/0, /*Op*/7,
        // (intrinsic_wo_chain:{ *:[f32] } 2803:{ *:[iPTR] }, f32:{ *:[f32] }:$old, f32:{ *:[f32] }:$src, (timm:{ *:[i32] }):$dpp_ctrl, (timm:{ *:[i32] }):$row_mask, (timm:{ *:[i32] }):$bank_mask, (timm:{ *:[i1] }):$bound_ctrl)  =>  (V_MOV_B32_dpp:{ *:[f32] } VGPR_32:{ *:[f32] }:$old, VGPR_32:{ *:[f32] }:$src, (as_i32timm:{ *:[i32] } ?:{ *:[i32] }:$dpp_ctrl), (as_i32timm:{ *:[i32] } ?:{ *:[i32] }:$row_mask), (as_i32timm:{ *:[i32] } ?:{ *:[i32] }:$bank_mask), (as_i1timm:{ *:[i1] } ?:{ *:[i1] }:$bound_ctrl))
        GIR_BuildMI, /*InsnID*/0, /*Opcode*/GIMT_Encode2(AMDGPU::V_MOV_B32_dpp),
        GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/0, // DstI[vdst]
        GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/2, // old
        GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/3, // src
        GIR_CustomOperandRenderer, /*InsnID*/0, /*OldInsnID*/0, /*OpIdx*/4, /*OperandRenderer*/GIMT_Encode2(GICR_renderTruncTImm), // dpp_ctrl
        GIR_CustomOperandRenderer, /*InsnID*/0, /*OldInsnID*/0, /*OpIdx*/5, /*OperandRenderer*/GIMT_Encode2(GICR_renderTruncTImm), // row_mask
        GIR_CustomOperandRenderer, /*InsnID*/0, /*OldInsnID*/0, /*OpIdx*/6, /*OperandRenderer*/GIMT_Encode2(GICR_renderTruncTImm), // bank_mask
        GIR_CustomOperandRenderer, /*InsnID*/0, /*OldInsnID*/0, /*OpIdx*/7, /*OperandRenderer*/GIMT_Encode2(GICR_renderTruncTImm), // bound_ctrl
        GIR_ConstrainSelectedInstOperands, /*InsnID*/0,
        GIR_EraseFromParent, /*InsnID*/0,
        // GIR_Coverage, 2082,
        GIR_Done,
      // Label 3523: @229330
      GIM_Try, /*On fail goto*//*Label 3524*/ GIMT_Encode4(229417), // Rule ID 2083 //
        GIM_CheckFeatures, GIMT_Encode2(GIFBS_isGFX8Plus),
        GIM_CheckIntrinsicID, /*MI*/0, /*Op*/1, GIMT_Encode2(Intrinsic::amdgcn_update_dpp),
        GIM_CheckType, /*MI*/0, /*Op*/0, /*Type*/GILLT_v2s16,
        GIM_CheckType, /*MI*/0, /*Op*/2, /*Type*/GILLT_v2s16,
        GIM_CheckType, /*MI*/0, /*Op*/3, /*Type*/GILLT_v2s16,
        GIM_CheckRegBankForClass, /*MI*/0, /*Op*/0, /*RC*/GIMT_Encode2(AMDGPU::VGPR_32RegClassID),
        // MIs[0] dpp_ctrl
        GIM_CheckIsImm, /*MI*/0, /*Op*/4,
        // MIs[0] row_mask
        GIM_CheckIsImm, /*MI*/0, /*Op*/5,
        // MIs[0] bank_mask
        GIM_CheckIsImm, /*MI*/0, /*Op*/6,
        // MIs[0] bound_ctrl
        GIM_CheckIsImm, /*MI*/0, /*Op*/7,
        // (intrinsic_wo_chain:{ *:[v2i16] } 2803:{ *:[iPTR] }, v2i16:{ *:[v2i16] }:$old, v2i16:{ *:[v2i16] }:$src, (timm:{ *:[i32] }):$dpp_ctrl, (timm:{ *:[i32] }):$row_mask, (timm:{ *:[i32] }):$bank_mask, (timm:{ *:[i1] }):$bound_ctrl)  =>  (V_MOV_B32_dpp:{ *:[v2i16] } VGPR_32:{ *:[v2i16] }:$old, VGPR_32:{ *:[v2i16] }:$src, (as_i32timm:{ *:[i32] } ?:{ *:[i32] }:$dpp_ctrl), (as_i32timm:{ *:[i32] } ?:{ *:[i32] }:$row_mask), (as_i32timm:{ *:[i32] } ?:{ *:[i32] }:$bank_mask), (as_i1timm:{ *:[i1] } ?:{ *:[i1] }:$bound_ctrl))
        GIR_BuildMI, /*InsnID*/0, /*Opcode*/GIMT_Encode2(AMDGPU::V_MOV_B32_dpp),
        GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/0, // DstI[vdst]
        GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/2, // old
        GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/3, // src
        GIR_CustomOperandRenderer, /*InsnID*/0, /*OldInsnID*/0, /*OpIdx*/4, /*OperandRenderer*/GIMT_Encode2(GICR_renderTruncTImm), // dpp_ctrl
        GIR_CustomOperandRenderer, /*InsnID*/0, /*OldInsnID*/0, /*OpIdx*/5, /*OperandRenderer*/GIMT_Encode2(GICR_renderTruncTImm), // row_mask
        GIR_CustomOperandRenderer, /*InsnID*/0, /*OldInsnID*/0, /*OpIdx*/6, /*OperandRenderer*/GIMT_Encode2(GICR_renderTruncTImm), // bank_mask
        GIR_CustomOperandRenderer, /*InsnID*/0, /*OldInsnID*/0, /*OpIdx*/7, /*OperandRenderer*/GIMT_Encode2(GICR_renderTruncTImm), // bound_ctrl
        GIR_ConstrainSelectedInstOperands, /*InsnID*/0,
        GIR_EraseFromParent, /*InsnID*/0,
        // GIR_Coverage, 2083,
        GIR_Done,
      // Label 3524: @229417
      GIM_Try, /*On fail goto*//*Label 3525*/ GIMT_Encode4(229504), // Rule ID 2084 //
        GIM_CheckFeatures, GIMT_Encode2(GIFBS_isGFX8Plus),
        GIM_CheckIntrinsicID, /*MI*/0, /*Op*/1, GIMT_Encode2(Intrinsic::amdgcn_update_dpp),
        GIM_CheckType, /*MI*/0, /*Op*/0, /*Type*/GILLT_v2s16,
        GIM_CheckType, /*MI*/0, /*Op*/2, /*Type*/GILLT_v2s16,
        GIM_CheckType, /*MI*/0, /*Op*/3, /*Type*/GILLT_v2s16,
        GIM_CheckRegBankForClass, /*MI*/0, /*Op*/0, /*RC*/GIMT_Encode2(AMDGPU::VGPR_32RegClassID),
        // MIs[0] dpp_ctrl
        GIM_CheckIsImm, /*MI*/0, /*Op*/4,
        // MIs[0] row_mask
        GIM_CheckIsImm, /*MI*/0, /*Op*/5,
        // MIs[0] bank_mask
        GIM_CheckIsImm, /*MI*/0, /*Op*/6,
        // MIs[0] bound_ctrl
        GIM_CheckIsImm, /*MI*/0, /*Op*/7,
        // (intrinsic_wo_chain:{ *:[v2f16] } 2803:{ *:[iPTR] }, v2f16:{ *:[v2f16] }:$old, v2f16:{ *:[v2f16] }:$src, (timm:{ *:[i32] }):$dpp_ctrl, (timm:{ *:[i32] }):$row_mask, (timm:{ *:[i32] }):$bank_mask, (timm:{ *:[i1] }):$bound_ctrl)  =>  (V_MOV_B32_dpp:{ *:[v2f16] } VGPR_32:{ *:[v2f16] }:$old, VGPR_32:{ *:[v2f16] }:$src, (as_i32timm:{ *:[i32] } ?:{ *:[i32] }:$dpp_ctrl), (as_i32timm:{ *:[i32] } ?:{ *:[i32] }:$row_mask), (as_i32timm:{ *:[i32] } ?:{ *:[i32] }:$bank_mask), (as_i1timm:{ *:[i1] } ?:{ *:[i1] }:$bound_ctrl))
        GIR_BuildMI, /*InsnID*/0, /*Opcode*/GIMT_Encode2(AMDGPU::V_MOV_B32_dpp),
        GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/0, // DstI[vdst]
        GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/2, // old
        GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/3, // src
        GIR_CustomOperandRenderer, /*InsnID*/0, /*OldInsnID*/0, /*OpIdx*/4, /*OperandRenderer*/GIMT_Encode2(GICR_renderTruncTImm), // dpp_ctrl
        GIR_CustomOperandRenderer, /*InsnID*/0, /*OldInsnID*/0, /*OpIdx*/5, /*OperandRenderer*/GIMT_Encode2(GICR_renderTruncTImm), // row_mask
        GIR_CustomOperandRenderer, /*InsnID*/0, /*OldInsnID*/0, /*OpIdx*/6, /*OperandRenderer*/GIMT_Encode2(GICR_renderTruncTImm), // bank_mask
        GIR_CustomOperandRenderer, /*InsnID*/0, /*OldInsnID*/0, /*OpIdx*/7, /*OperandRenderer*/GIMT_Encode2(GICR_renderTruncTImm), // bound_ctrl
        GIR_ConstrainSelectedInstOperands, /*InsnID*/0,
        GIR_EraseFromParent, /*InsnID*/0,
        // GIR_Coverage, 2084,
        GIR_Done,
      // Label 3525: @229504
      GIM_Try, /*On fail goto*//*Label 3526*/ GIMT_Encode4(229588), // Rule ID 6460 //
        GIM_CheckIntrinsicID, /*MI*/0, /*Op*/1, GIMT_Encode2(Intrinsic::amdgcn_update_dpp),
        GIM_CheckType, /*MI*/0, /*Op*/0, /*Type*/GILLT_s64,
        GIM_CheckType, /*MI*/0, /*Op*/2, /*Type*/GILLT_s64,
        GIM_CheckType, /*MI*/0, /*Op*/3, /*Type*/GILLT_s64,
        GIM_CheckRegBankForClass, /*MI*/0, /*Op*/0, /*RC*/GIMT_Encode2(AMDGPU::VReg_64RegClassID),
        // MIs[0] dpp_ctrl
        GIM_CheckIsImm, /*MI*/0, /*Op*/4,
        // MIs[0] row_mask
        GIM_CheckIsImm, /*MI*/0, /*Op*/5,
        // MIs[0] bank_mask
        GIM_CheckIsImm, /*MI*/0, /*Op*/6,
        // MIs[0] bound_ctrl
        GIM_CheckIsImm, /*MI*/0, /*Op*/7,
        // (intrinsic_wo_chain:{ *:[i64] } 2803:{ *:[iPTR] }, i64:{ *:[i64] }:$old, i64:{ *:[i64] }:$src, (timm:{ *:[i32] }):$dpp_ctrl, (timm:{ *:[i32] }):$row_mask, (timm:{ *:[i32] }):$bank_mask, (timm:{ *:[i1] }):$bound_ctrl)  =>  (V_MOV_B64_DPP_PSEUDO:{ *:[i64] } VReg_64_Align2:{ *:[i64] }:$old, VReg_64_Align2:{ *:[i64] }:$src, (as_i32timm:{ *:[i32] } ?:{ *:[i32] }:$dpp_ctrl), (as_i32timm:{ *:[i32] } ?:{ *:[i32] }:$row_mask), (as_i32timm:{ *:[i32] } ?:{ *:[i32] }:$bank_mask), (as_i1timm:{ *:[i1] } ?:{ *:[i1] }:$bound_ctrl))
        GIR_BuildMI, /*InsnID*/0, /*Opcode*/GIMT_Encode2(AMDGPU::V_MOV_B64_DPP_PSEUDO),
        GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/0, // DstI[vdst]
        GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/2, // old
        GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/3, // src
        GIR_CustomOperandRenderer, /*InsnID*/0, /*OldInsnID*/0, /*OpIdx*/4, /*OperandRenderer*/GIMT_Encode2(GICR_renderTruncTImm), // dpp_ctrl
        GIR_CustomOperandRenderer, /*InsnID*/0, /*OldInsnID*/0, /*OpIdx*/5, /*OperandRenderer*/GIMT_Encode2(GICR_renderTruncTImm), // row_mask
        GIR_CustomOperandRenderer, /*InsnID*/0, /*OldInsnID*/0, /*OpIdx*/6, /*OperandRenderer*/GIMT_Encode2(GICR_renderTruncTImm), // bank_mask
        GIR_CustomOperandRenderer, /*InsnID*/0, /*OldInsnID*/0, /*OpIdx*/7, /*OperandRenderer*/GIMT_Encode2(GICR_renderTruncTImm), // bound_ctrl
        GIR_ConstrainSelectedInstOperands, /*InsnID*/0,
        GIR_EraseFromParent, /*InsnID*/0,
        // GIR_Coverage, 6460,
        GIR_Done,
      // Label 3526: @229588
      GIM_Try, /*On fail goto*//*Label 3527*/ GIMT_Encode4(229679), // Rule ID 2211 //
        GIM_CheckFeatures, GIMT_Encode2(GIFBS_isGFX10Plus),
        GIM_CheckIntrinsicID, /*MI*/0, /*Op*/1, GIMT_Encode2(Intrinsic::amdgcn_permlane16),
        GIM_CheckType, /*MI*/0, /*Op*/0, /*Type*/GILLT_s32,
        GIM_CheckType, /*MI*/0, /*Op*/2, /*Type*/GILLT_s32,
        GIM_CheckType, /*MI*/0, /*Op*/3, /*Type*/GILLT_s32,
        GIM_CheckType, /*MI*/0, /*Op*/4, /*Type*/GILLT_s32,
        GIM_CheckType, /*MI*/0, /*Op*/5, /*Type*/GILLT_s32,
        GIM_CheckRegBankForClass, /*MI*/0, /*Op*/0, /*RC*/GIMT_Encode2(AMDGPU::VGPR_32RegClassID),
        // MIs[0] fi
        GIM_CheckIsImm, /*MI*/0, /*Op*/6,
        // MIs[0] bc
        GIM_CheckIsImm, /*MI*/0, /*Op*/7,
        // (intrinsic_wo_chain:{ *:[i32] } 2589:{ *:[iPTR] }, i32:{ *:[i32] }:$vdst_in, i32:{ *:[i32] }:$src0, i32:{ *:[i32] }:$src1, i32:{ *:[i32] }:$src2, (timm:{ *:[i1] }):$fi, (timm:{ *:[i1] }):$bc)  =>  (V_PERMLANE16_B32_e64:{ *:[i32] } (opsel_i1timm:{ *:[i32] } ?:{ *:[i1] }:$fi), VGPR_32:{ *:[i32] }:$src0, (opsel_i1timm:{ *:[i32] } ?:{ *:[i1] }:$bc), SCSrc_b32:{ *:[i32] }:$src1, 0:{ *:[i32] }, SCSrc_b32:{ *:[i32] }:$src2, VGPR_32:{ *:[i32] }:$vdst_in)
        GIR_BuildMI, /*InsnID*/0, /*Opcode*/GIMT_Encode2(AMDGPU::V_PERMLANE16_B32_e64),
        GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/0, // DstI[vdst]
        GIR_CustomOperandRenderer, /*InsnID*/0, /*OldInsnID*/0, /*OpIdx*/6, /*OperandRenderer*/GIMT_Encode2(GICR_renderOpSelTImm), // fi
        GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/3, // src0
        GIR_CustomOperandRenderer, /*InsnID*/0, /*OldInsnID*/0, /*OpIdx*/7, /*OperandRenderer*/GIMT_Encode2(GICR_renderOpSelTImm), // bc
        GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/4, // src1
        GIR_AddImm8, /*InsnID*/0, /*Imm*/0,
        GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/5, // src2
        GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/2, // vdst_in
        GIR_AddImm8, /*InsnID*/0, /*Imm*/0,
        GIR_ConstrainSelectedInstOperands, /*InsnID*/0,
        GIR_EraseFromParent, /*InsnID*/0,
        // GIR_Coverage, 2211,
        GIR_Done,
      // Label 3527: @229679
      GIM_Try, /*On fail goto*//*Label 3528*/ GIMT_Encode4(229770), // Rule ID 2212 //
        GIM_CheckFeatures, GIMT_Encode2(GIFBS_isGFX10Plus),
        GIM_CheckIntrinsicID, /*MI*/0, /*Op*/1, GIMT_Encode2(Intrinsic::amdgcn_permlanex16),
        GIM_CheckType, /*MI*/0, /*Op*/0, /*Type*/GILLT_s32,
        GIM_CheckType, /*MI*/0, /*Op*/2, /*Type*/GILLT_s32,
        GIM_CheckType, /*MI*/0, /*Op*/3, /*Type*/GILLT_s32,
        GIM_CheckType, /*MI*/0, /*Op*/4, /*Type*/GILLT_s32,
        GIM_CheckType, /*MI*/0, /*Op*/5, /*Type*/GILLT_s32,
        GIM_CheckRegBankForClass, /*MI*/0, /*Op*/0, /*RC*/GIMT_Encode2(AMDGPU::VGPR_32RegClassID),
        // MIs[0] fi
        GIM_CheckIsImm, /*MI*/0, /*Op*/6,
        // MIs[0] bc
        GIM_CheckIsImm, /*MI*/0, /*Op*/7,
        // (intrinsic_wo_chain:{ *:[i32] } 2592:{ *:[iPTR] }, i32:{ *:[i32] }:$vdst_in, i32:{ *:[i32] }:$src0, i32:{ *:[i32] }:$src1, i32:{ *:[i32] }:$src2, (timm:{ *:[i1] }):$fi, (timm:{ *:[i1] }):$bc)  =>  (V_PERMLANEX16_B32_e64:{ *:[i32] } (opsel_i1timm:{ *:[i32] } ?:{ *:[i1] }:$fi), VGPR_32:{ *:[i32] }:$src0, (opsel_i1timm:{ *:[i32] } ?:{ *:[i1] }:$bc), SCSrc_b32:{ *:[i32] }:$src1, 0:{ *:[i32] }, SCSrc_b32:{ *:[i32] }:$src2, VGPR_32:{ *:[i32] }:$vdst_in)
        GIR_BuildMI, /*InsnID*/0, /*Opcode*/GIMT_Encode2(AMDGPU::V_PERMLANEX16_B32_e64),
        GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/0, // DstI[vdst]
        GIR_CustomOperandRenderer, /*InsnID*/0, /*OldInsnID*/0, /*OpIdx*/6, /*OperandRenderer*/GIMT_Encode2(GICR_renderOpSelTImm), // fi
        GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/3, // src0
        GIR_CustomOperandRenderer, /*InsnID*/0, /*OldInsnID*/0, /*OpIdx*/7, /*OperandRenderer*/GIMT_Encode2(GICR_renderOpSelTImm), // bc
        GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/4, // src1
        GIR_AddImm8, /*InsnID*/0, /*Imm*/0,
        GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/5, // src2
        GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/2, // vdst_in
        GIR_AddImm8, /*InsnID*/0, /*Imm*/0,
        GIR_ConstrainSelectedInstOperands, /*InsnID*/0,
        GIR_EraseFromParent, /*InsnID*/0,
        // GIR_Coverage, 2212,
        GIR_Done,
      // Label 3528: @229770
      GIM_Try, /*On fail goto*//*Label 3529*/ GIMT_Encode4(229854), // Rule ID 992 //
        GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasMAIInsts),
        GIM_CheckIntrinsicID, /*MI*/0, /*Op*/1, GIMT_Encode2(Intrinsic::amdgcn_mfma_f32_4x4x1f32),
        GIM_CheckType, /*MI*/0, /*Op*/0, /*Type*/GILLT_v4s32,
        GIM_CheckType, /*MI*/0, /*Op*/2, /*Type*/GILLT_s32,
        GIM_CheckType, /*MI*/0, /*Op*/3, /*Type*/GILLT_s32,
        GIM_CheckType, /*MI*/0, /*Op*/4, /*Type*/GILLT_v4s32,
        GIM_CheckRegBankForClass, /*MI*/0, /*Op*/0, /*RC*/GIMT_Encode2(AMDGPU::AReg_128RegClassID),
        // MIs[0] cbsz
        GIM_CheckIsImm, /*MI*/0, /*Op*/5,
        // MIs[0] abid
        GIM_CheckIsImm, /*MI*/0, /*Op*/6,
        // MIs[0] blgp
        GIM_CheckIsImm, /*MI*/0, /*Op*/7,
        GIM_CheckCxxInsnPredicate, /*MI*/0, /*FnId*/GIMT_Encode2(GICXXPred_MI_Predicate_anonymous_24726),
        // (intrinsic_wo_chain:{ *:[v4f32] } 2566:{ *:[iPTR] }, f32:{ *:[f32] }:$src0, f32:{ *:[f32] }:$src1, v4f32:{ *:[v4f32] }:$src2, (timm:{ *:[i32] }):$cbsz, (timm:{ *:[i32] }):$abid, (timm:{ *:[i32] }):$blgp)<<P:Predicate_anonymous_24726>>  =>  (V_MFMA_F32_4X4X1F32_e64:{ *:[v4f32] } f32:{ *:[f32] }:$src0, f32:{ *:[f32] }:$src1, v4f32:{ *:[v4f32] }:$src2, (timm:{ *:[i32] }):$cbsz, (timm:{ *:[i32] }):$abid, (timm:{ *:[i32] }):$blgp)
        GIR_BuildMI, /*InsnID*/0, /*Opcode*/GIMT_Encode2(AMDGPU::V_MFMA_F32_4X4X1F32_e64),
        GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/0, // DstI[vdst]
        GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/2, // src0
        GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/3, // src1
        GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/4, // src2
        GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/5, // cbsz
        GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/6, // abid
        GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/7, // blgp
        GIR_ConstrainSelectedInstOperands, /*InsnID*/0,
        GIR_EraseFromParent, /*InsnID*/0,
        // GIR_Coverage, 992,
        GIR_Done,
      // Label 3529: @229854
      GIM_Try, /*On fail goto*//*Label 3530*/ GIMT_Encode4(229938), // Rule ID 993 //
        GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasMAIInsts),
        GIM_CheckIntrinsicID, /*MI*/0, /*Op*/1, GIMT_Encode2(Intrinsic::amdgcn_mfma_f32_4x4x1f32),
        GIM_CheckType, /*MI*/0, /*Op*/0, /*Type*/GILLT_v4s32,
        GIM_CheckType, /*MI*/0, /*Op*/2, /*Type*/GILLT_s32,
        GIM_CheckType, /*MI*/0, /*Op*/3, /*Type*/GILLT_s32,
        GIM_CheckType, /*MI*/0, /*Op*/4, /*Type*/GILLT_v4s32,
        GIM_CheckRegBankForClass, /*MI*/0, /*Op*/0, /*RC*/GIMT_Encode2(AMDGPU::VReg_128RegClassID),
        // MIs[0] cbsz
        GIM_CheckIsImm, /*MI*/0, /*Op*/5,
        // MIs[0] abid
        GIM_CheckIsImm, /*MI*/0, /*Op*/6,
        // MIs[0] blgp
        GIM_CheckIsImm, /*MI*/0, /*Op*/7,
        GIM_CheckCxxInsnPredicate, /*MI*/0, /*FnId*/GIMT_Encode2(GICXXPred_MI_Predicate_anonymous_24728),
        // (intrinsic_wo_chain:{ *:[v4f32] } 2566:{ *:[iPTR] }, f32:{ *:[f32] }:$src0, f32:{ *:[f32] }:$src1, v4f32:{ *:[v4f32] }:$src2, (timm:{ *:[i32] }):$cbsz, (timm:{ *:[i32] }):$abid, (timm:{ *:[i32] }):$blgp)<<P:Predicate_anonymous_24728>>  =>  (V_MFMA_F32_4X4X1F32_vgprcd_e64:{ *:[v4f32] } f32:{ *:[f32] }:$src0, f32:{ *:[f32] }:$src1, v4f32:{ *:[v4f32] }:$src2, (timm:{ *:[i32] }):$cbsz, (timm:{ *:[i32] }):$abid, (timm:{ *:[i32] }):$blgp)
        GIR_BuildMI, /*InsnID*/0, /*Opcode*/GIMT_Encode2(AMDGPU::V_MFMA_F32_4X4X1F32_vgprcd_e64),
        GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/0, // DstI[vdst]
        GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/2, // src0
        GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/3, // src1
        GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/4, // src2
        GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/5, // cbsz
        GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/6, // abid
        GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/7, // blgp
        GIR_ConstrainSelectedInstOperands, /*InsnID*/0,
        GIR_EraseFromParent, /*InsnID*/0,
        // GIR_Coverage, 993,
        GIR_Done,
      // Label 3530: @229938
      GIM_Try, /*On fail goto*//*Label 3531*/ GIMT_Encode4(230022), // Rule ID 994 //
        GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasMAIInsts),
        GIM_CheckIntrinsicID, /*MI*/0, /*Op*/1, GIMT_Encode2(Intrinsic::amdgcn_mfma_f32_16x16x1f32),
        GIM_CheckType, /*MI*/0, /*Op*/0, /*Type*/GILLT_v16s32,
        GIM_CheckType, /*MI*/0, /*Op*/2, /*Type*/GILLT_s32,
        GIM_CheckType, /*MI*/0, /*Op*/3, /*Type*/GILLT_s32,
        GIM_CheckType, /*MI*/0, /*Op*/4, /*Type*/GILLT_v16s32,
        GIM_CheckRegBankForClass, /*MI*/0, /*Op*/0, /*RC*/GIMT_Encode2(AMDGPU::AReg_512RegClassID),
        // MIs[0] cbsz
        GIM_CheckIsImm, /*MI*/0, /*Op*/5,
        // MIs[0] abid
        GIM_CheckIsImm, /*MI*/0, /*Op*/6,
        // MIs[0] blgp
        GIM_CheckIsImm, /*MI*/0, /*Op*/7,
        GIM_CheckCxxInsnPredicate, /*MI*/0, /*FnId*/GIMT_Encode2(GICXXPred_MI_Predicate_anonymous_24732),
        // (intrinsic_wo_chain:{ *:[v16f32] } 2542:{ *:[iPTR] }, f32:{ *:[f32] }:$src0, f32:{ *:[f32] }:$src1, v16f32:{ *:[v16f32] }:$src2, (timm:{ *:[i32] }):$cbsz, (timm:{ *:[i32] }):$abid, (timm:{ *:[i32] }):$blgp)<<P:Predicate_anonymous_24732>>  =>  (V_MFMA_F32_16X16X1F32_mac_e64:{ *:[v16f32] } f32:{ *:[f32] }:$src0, f32:{ *:[f32] }:$src1, v16f32:{ *:[v16f32] }:$src2, (timm:{ *:[i32] }):$cbsz, (timm:{ *:[i32] }):$abid, (timm:{ *:[i32] }):$blgp)
        GIR_BuildMI, /*InsnID*/0, /*Opcode*/GIMT_Encode2(AMDGPU::V_MFMA_F32_16X16X1F32_mac_e64),
        GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/0, // DstI[vdst]
        GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/2, // src0
        GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/3, // src1
        GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/4, // src2
        GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/5, // cbsz
        GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/6, // abid
        GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/7, // blgp
        GIR_ConstrainSelectedInstOperands, /*InsnID*/0,
        GIR_EraseFromParent, /*InsnID*/0,
        // GIR_Coverage, 994,
        GIR_Done,
      // Label 3531: @230022
      GIM_Try, /*On fail goto*//*Label 3532*/ GIMT_Encode4(230106), // Rule ID 995 //
        GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasMAIInsts),
        GIM_CheckIntrinsicID, /*MI*/0, /*Op*/1, GIMT_Encode2(Intrinsic::amdgcn_mfma_f32_16x16x1f32),
        GIM_CheckType, /*MI*/0, /*Op*/0, /*Type*/GILLT_v16s32,
        GIM_CheckType, /*MI*/0, /*Op*/2, /*Type*/GILLT_s32,
        GIM_CheckType, /*MI*/0, /*Op*/3, /*Type*/GILLT_s32,
        GIM_CheckType, /*MI*/0, /*Op*/4, /*Type*/GILLT_v16s32,
        GIM_CheckRegBankForClass, /*MI*/0, /*Op*/0, /*RC*/GIMT_Encode2(AMDGPU::VReg_512RegClassID),
        // MIs[0] cbsz
        GIM_CheckIsImm, /*MI*/0, /*Op*/5,
        // MIs[0] abid
        GIM_CheckIsImm, /*MI*/0, /*Op*/6,
        // MIs[0] blgp
        GIM_CheckIsImm, /*MI*/0, /*Op*/7,
        GIM_CheckCxxInsnPredicate, /*MI*/0, /*FnId*/GIMT_Encode2(GICXXPred_MI_Predicate_anonymous_24734),
        // (intrinsic_wo_chain:{ *:[v16f32] } 2542:{ *:[iPTR] }, f32:{ *:[f32] }:$src0, f32:{ *:[f32] }:$src1, v16f32:{ *:[v16f32] }:$src2, (timm:{ *:[i32] }):$cbsz, (timm:{ *:[i32] }):$abid, (timm:{ *:[i32] }):$blgp)<<P:Predicate_anonymous_24734>>  =>  (V_MFMA_F32_16X16X1F32_mac_vgprcd_e64:{ *:[v16f32] } f32:{ *:[f32] }:$src0, f32:{ *:[f32] }:$src1, v16f32:{ *:[v16f32] }:$src2, (timm:{ *:[i32] }):$cbsz, (timm:{ *:[i32] }):$abid, (timm:{ *:[i32] }):$blgp)
        GIR_BuildMI, /*InsnID*/0, /*Opcode*/GIMT_Encode2(AMDGPU::V_MFMA_F32_16X16X1F32_mac_vgprcd_e64),
        GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/0, // DstI[vdst]
        GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/2, // src0
        GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/3, // src1
        GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/4, // src2
        GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/5, // cbsz
        GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/6, // abid
        GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/7, // blgp
        GIR_ConstrainSelectedInstOperands, /*InsnID*/0,
        GIR_EraseFromParent, /*InsnID*/0,
        // GIR_Coverage, 995,
        GIR_Done,
      // Label 3532: @230106
      GIM_Try, /*On fail goto*//*Label 3533*/ GIMT_Encode4(230190), // Rule ID 996 //
        GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasMAIInsts),
        GIM_CheckIntrinsicID, /*MI*/0, /*Op*/1, GIMT_Encode2(Intrinsic::amdgcn_mfma_f32_16x16x4f32),
        GIM_CheckType, /*MI*/0, /*Op*/0, /*Type*/GILLT_v4s32,
        GIM_CheckType, /*MI*/0, /*Op*/2, /*Type*/GILLT_s32,
        GIM_CheckType, /*MI*/0, /*Op*/3, /*Type*/GILLT_s32,
        GIM_CheckType, /*MI*/0, /*Op*/4, /*Type*/GILLT_v4s32,
        GIM_CheckRegBankForClass, /*MI*/0, /*Op*/0, /*RC*/GIMT_Encode2(AMDGPU::AReg_128RegClassID),
        // MIs[0] cbsz
        GIM_CheckIsImm, /*MI*/0, /*Op*/5,
        // MIs[0] abid
        GIM_CheckIsImm, /*MI*/0, /*Op*/6,
        // MIs[0] blgp
        GIM_CheckIsImm, /*MI*/0, /*Op*/7,
        GIM_CheckCxxInsnPredicate, /*MI*/0, /*FnId*/GIMT_Encode2(GICXXPred_MI_Predicate_anonymous_24736),
        // (intrinsic_wo_chain:{ *:[v4f32] } 2550:{ *:[iPTR] }, f32:{ *:[f32] }:$src0, f32:{ *:[f32] }:$src1, v4f32:{ *:[v4f32] }:$src2, (timm:{ *:[i32] }):$cbsz, (timm:{ *:[i32] }):$abid, (timm:{ *:[i32] }):$blgp)<<P:Predicate_anonymous_24736>>  =>  (V_MFMA_F32_16X16X4F32_e64:{ *:[v4f32] } f32:{ *:[f32] }:$src0, f32:{ *:[f32] }:$src1, v4f32:{ *:[v4f32] }:$src2, (timm:{ *:[i32] }):$cbsz, (timm:{ *:[i32] }):$abid, (timm:{ *:[i32] }):$blgp)
        GIR_BuildMI, /*InsnID*/0, /*Opcode*/GIMT_Encode2(AMDGPU::V_MFMA_F32_16X16X4F32_e64),
        GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/0, // DstI[vdst]
        GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/2, // src0
        GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/3, // src1
        GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/4, // src2
        GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/5, // cbsz
        GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/6, // abid
        GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/7, // blgp
        GIR_ConstrainSelectedInstOperands, /*InsnID*/0,
        GIR_EraseFromParent, /*InsnID*/0,
        // GIR_Coverage, 996,
        GIR_Done,
      // Label 3533: @230190
      GIM_Try, /*On fail goto*//*Label 3534*/ GIMT_Encode4(230274), // Rule ID 997 //
        GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasMAIInsts),
        GIM_CheckIntrinsicID, /*MI*/0, /*Op*/1, GIMT_Encode2(Intrinsic::amdgcn_mfma_f32_16x16x4f32),
        GIM_CheckType, /*MI*/0, /*Op*/0, /*Type*/GILLT_v4s32,
        GIM_CheckType, /*MI*/0, /*Op*/2, /*Type*/GILLT_s32,
        GIM_CheckType, /*MI*/0, /*Op*/3, /*Type*/GILLT_s32,
        GIM_CheckType, /*MI*/0, /*Op*/4, /*Type*/GILLT_v4s32,
        GIM_CheckRegBankForClass, /*MI*/0, /*Op*/0, /*RC*/GIMT_Encode2(AMDGPU::VReg_128RegClassID),
        // MIs[0] cbsz
        GIM_CheckIsImm, /*MI*/0, /*Op*/5,
        // MIs[0] abid
        GIM_CheckIsImm, /*MI*/0, /*Op*/6,
        // MIs[0] blgp
        GIM_CheckIsImm, /*MI*/0, /*Op*/7,
        GIM_CheckCxxInsnPredicate, /*MI*/0, /*FnId*/GIMT_Encode2(GICXXPred_MI_Predicate_anonymous_24738),
        // (intrinsic_wo_chain:{ *:[v4f32] } 2550:{ *:[iPTR] }, f32:{ *:[f32] }:$src0, f32:{ *:[f32] }:$src1, v4f32:{ *:[v4f32] }:$src2, (timm:{ *:[i32] }):$cbsz, (timm:{ *:[i32] }):$abid, (timm:{ *:[i32] }):$blgp)<<P:Predicate_anonymous_24738>>  =>  (V_MFMA_F32_16X16X4F32_vgprcd_e64:{ *:[v4f32] } f32:{ *:[f32] }:$src0, f32:{ *:[f32] }:$src1, v4f32:{ *:[v4f32] }:$src2, (timm:{ *:[i32] }):$cbsz, (timm:{ *:[i32] }):$abid, (timm:{ *:[i32] }):$blgp)
        GIR_BuildMI, /*InsnID*/0, /*Opcode*/GIMT_Encode2(AMDGPU::V_MFMA_F32_16X16X4F32_vgprcd_e64),
        GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/0, // DstI[vdst]
        GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/2, // src0
        GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/3, // src1
        GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/4, // src2
        GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/5, // cbsz
        GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/6, // abid
        GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/7, // blgp
        GIR_ConstrainSelectedInstOperands, /*InsnID*/0,
        GIR_EraseFromParent, /*InsnID*/0,
        // GIR_Coverage, 997,
        GIR_Done,
      // Label 3534: @230274
      GIM_Try, /*On fail goto*//*Label 3535*/ GIMT_Encode4(230358), // Rule ID 998 //
        GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasMAIInsts),
        GIM_CheckIntrinsicID, /*MI*/0, /*Op*/1, GIMT_Encode2(Intrinsic::amdgcn_mfma_f32_32x32x1f32),
        GIM_CheckType, /*MI*/0, /*Op*/0, /*Type*/GILLT_v32s32,
        GIM_CheckType, /*MI*/0, /*Op*/2, /*Type*/GILLT_s32,
        GIM_CheckType, /*MI*/0, /*Op*/3, /*Type*/GILLT_s32,
        GIM_CheckType, /*MI*/0, /*Op*/4, /*Type*/GILLT_v32s32,
        GIM_CheckRegBankForClass, /*MI*/0, /*Op*/0, /*RC*/GIMT_Encode2(AMDGPU::AReg_1024RegClassID),
        // MIs[0] cbsz
        GIM_CheckIsImm, /*MI*/0, /*Op*/5,
        // MIs[0] abid
        GIM_CheckIsImm, /*MI*/0, /*Op*/6,
        // MIs[0] blgp
        GIM_CheckIsImm, /*MI*/0, /*Op*/7,
        GIM_CheckCxxInsnPredicate, /*MI*/0, /*FnId*/GIMT_Encode2(GICXXPred_MI_Predicate_anonymous_24742),
        // (intrinsic_wo_chain:{ *:[v32f32] } 2557:{ *:[iPTR] }, f32:{ *:[f32] }:$src0, f32:{ *:[f32] }:$src1, v32f32:{ *:[v32f32] }:$src2, (timm:{ *:[i32] }):$cbsz, (timm:{ *:[i32] }):$abid, (timm:{ *:[i32] }):$blgp)<<P:Predicate_anonymous_24742>>  =>  (V_MFMA_F32_32X32X1F32_mac_e64:{ *:[v32f32] } f32:{ *:[f32] }:$src0, f32:{ *:[f32] }:$src1, v32f32:{ *:[v32f32] }:$src2, (timm:{ *:[i32] }):$cbsz, (timm:{ *:[i32] }):$abid, (timm:{ *:[i32] }):$blgp)
        GIR_BuildMI, /*InsnID*/0, /*Opcode*/GIMT_Encode2(AMDGPU::V_MFMA_F32_32X32X1F32_mac_e64),
        GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/0, // DstI[vdst]
        GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/2, // src0
        GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/3, // src1
        GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/4, // src2
        GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/5, // cbsz
        GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/6, // abid
        GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/7, // blgp
        GIR_ConstrainSelectedInstOperands, /*InsnID*/0,
        GIR_EraseFromParent, /*InsnID*/0,
        // GIR_Coverage, 998,
        GIR_Done,
      // Label 3535: @230358
      GIM_Try, /*On fail goto*//*Label 3536*/ GIMT_Encode4(230442), // Rule ID 999 //
        GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasMAIInsts),
        GIM_CheckIntrinsicID, /*MI*/0, /*Op*/1, GIMT_Encode2(Intrinsic::amdgcn_mfma_f32_32x32x1f32),
        GIM_CheckType, /*MI*/0, /*Op*/0, /*Type*/GILLT_v32s32,
        GIM_CheckType, /*MI*/0, /*Op*/2, /*Type*/GILLT_s32,
        GIM_CheckType, /*MI*/0, /*Op*/3, /*Type*/GILLT_s32,
        GIM_CheckType, /*MI*/0, /*Op*/4, /*Type*/GILLT_v32s32,
        GIM_CheckRegBankForClass, /*MI*/0, /*Op*/0, /*RC*/GIMT_Encode2(AMDGPU::VReg_1024RegClassID),
        // MIs[0] cbsz
        GIM_CheckIsImm, /*MI*/0, /*Op*/5,
        // MIs[0] abid
        GIM_CheckIsImm, /*MI*/0, /*Op*/6,
        // MIs[0] blgp
        GIM_CheckIsImm, /*MI*/0, /*Op*/7,
        GIM_CheckCxxInsnPredicate, /*MI*/0, /*FnId*/GIMT_Encode2(GICXXPred_MI_Predicate_anonymous_24744),
        // (intrinsic_wo_chain:{ *:[v32f32] } 2557:{ *:[iPTR] }, f32:{ *:[f32] }:$src0, f32:{ *:[f32] }:$src1, v32f32:{ *:[v32f32] }:$src2, (timm:{ *:[i32] }):$cbsz, (timm:{ *:[i32] }):$abid, (timm:{ *:[i32] }):$blgp)<<P:Predicate_anonymous_24744>>  =>  (V_MFMA_F32_32X32X1F32_mac_vgprcd_e64:{ *:[v32f32] } f32:{ *:[f32] }:$src0, f32:{ *:[f32] }:$src1, v32f32:{ *:[v32f32] }:$src2, (timm:{ *:[i32] }):$cbsz, (timm:{ *:[i32] }):$abid, (timm:{ *:[i32] }):$blgp)
        GIR_BuildMI, /*InsnID*/0, /*Opcode*/GIMT_Encode2(AMDGPU::V_MFMA_F32_32X32X1F32_mac_vgprcd_e64),
        GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/0, // DstI[vdst]
        GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/2, // src0
        GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/3, // src1
        GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/4, // src2
        GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/5, // cbsz
        GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/6, // abid
        GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/7, // blgp
        GIR_ConstrainSelectedInstOperands, /*InsnID*/0,
        GIR_EraseFromParent, /*InsnID*/0,
        // GIR_Coverage, 999,
        GIR_Done,
      // Label 3536: @230442
      GIM_Try, /*On fail goto*//*Label 3537*/ GIMT_Encode4(230526), // Rule ID 1000 //
        GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasMAIInsts),
        GIM_CheckIntrinsicID, /*MI*/0, /*Op*/1, GIMT_Encode2(Intrinsic::amdgcn_mfma_f32_32x32x2f32),
        GIM_CheckType, /*MI*/0, /*Op*/0, /*Type*/GILLT_v16s32,
        GIM_CheckType, /*MI*/0, /*Op*/2, /*Type*/GILLT_s32,
        GIM_CheckType, /*MI*/0, /*Op*/3, /*Type*/GILLT_s32,
        GIM_CheckType, /*MI*/0, /*Op*/4, /*Type*/GILLT_v16s32,
        GIM_CheckRegBankForClass, /*MI*/0, /*Op*/0, /*RC*/GIMT_Encode2(AMDGPU::AReg_512RegClassID),
        // MIs[0] cbsz
        GIM_CheckIsImm, /*MI*/0, /*Op*/5,
        // MIs[0] abid
        GIM_CheckIsImm, /*MI*/0, /*Op*/6,
        // MIs[0] blgp
        GIM_CheckIsImm, /*MI*/0, /*Op*/7,
        GIM_CheckCxxInsnPredicate, /*MI*/0, /*FnId*/GIMT_Encode2(GICXXPred_MI_Predicate_anonymous_24746),
        // (intrinsic_wo_chain:{ *:[v16f32] } 2559:{ *:[iPTR] }, f32:{ *:[f32] }:$src0, f32:{ *:[f32] }:$src1, v16f32:{ *:[v16f32] }:$src2, (timm:{ *:[i32] }):$cbsz, (timm:{ *:[i32] }):$abid, (timm:{ *:[i32] }):$blgp)<<P:Predicate_anonymous_24746>>  =>  (V_MFMA_F32_32X32X2F32_mac_e64:{ *:[v16f32] } f32:{ *:[f32] }:$src0, f32:{ *:[f32] }:$src1, v16f32:{ *:[v16f32] }:$src2, (timm:{ *:[i32] }):$cbsz, (timm:{ *:[i32] }):$abid, (timm:{ *:[i32] }):$blgp)
        GIR_BuildMI, /*InsnID*/0, /*Opcode*/GIMT_Encode2(AMDGPU::V_MFMA_F32_32X32X2F32_mac_e64),
        GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/0, // DstI[vdst]
        GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/2, // src0
        GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/3, // src1
        GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/4, // src2
        GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/5, // cbsz
        GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/6, // abid
        GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/7, // blgp
        GIR_ConstrainSelectedInstOperands, /*InsnID*/0,
        GIR_EraseFromParent, /*InsnID*/0,
        // GIR_Coverage, 1000,
        GIR_Done,
      // Label 3537: @230526
      GIM_Try, /*On fail goto*//*Label 3538*/ GIMT_Encode4(230610), // Rule ID 1001 //
        GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasMAIInsts),
        GIM_CheckIntrinsicID, /*MI*/0, /*Op*/1, GIMT_Encode2(Intrinsic::amdgcn_mfma_f32_32x32x2f32),
        GIM_CheckType, /*MI*/0, /*Op*/0, /*Type*/GILLT_v16s32,
        GIM_CheckType, /*MI*/0, /*Op*/2, /*Type*/GILLT_s32,
        GIM_CheckType, /*MI*/0, /*Op*/3, /*Type*/GILLT_s32,
        GIM_CheckType, /*MI*/0, /*Op*/4, /*Type*/GILLT_v16s32,
        GIM_CheckRegBankForClass, /*MI*/0, /*Op*/0, /*RC*/GIMT_Encode2(AMDGPU::VReg_512RegClassID),
        // MIs[0] cbsz
        GIM_CheckIsImm, /*MI*/0, /*Op*/5,
        // MIs[0] abid
        GIM_CheckIsImm, /*MI*/0, /*Op*/6,
        // MIs[0] blgp
        GIM_CheckIsImm, /*MI*/0, /*Op*/7,
        GIM_CheckCxxInsnPredicate, /*MI*/0, /*FnId*/GIMT_Encode2(GICXXPred_MI_Predicate_anonymous_24748),
        // (intrinsic_wo_chain:{ *:[v16f32] } 2559:{ *:[iPTR] }, f32:{ *:[f32] }:$src0, f32:{ *:[f32] }:$src1, v16f32:{ *:[v16f32] }:$src2, (timm:{ *:[i32] }):$cbsz, (timm:{ *:[i32] }):$abid, (timm:{ *:[i32] }):$blgp)<<P:Predicate_anonymous_24748>>  =>  (V_MFMA_F32_32X32X2F32_mac_vgprcd_e64:{ *:[v16f32] } f32:{ *:[f32] }:$src0, f32:{ *:[f32] }:$src1, v16f32:{ *:[v16f32] }:$src2, (timm:{ *:[i32] }):$cbsz, (timm:{ *:[i32] }):$abid, (timm:{ *:[i32] }):$blgp)
        GIR_BuildMI, /*InsnID*/0, /*Opcode*/GIMT_Encode2(AMDGPU::V_MFMA_F32_32X32X2F32_mac_vgprcd_e64),
        GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/0, // DstI[vdst]
        GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/2, // src0
        GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/3, // src1
        GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/4, // src2
        GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/5, // cbsz
        GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/6, // abid
        GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/7, // blgp
        GIR_ConstrainSelectedInstOperands, /*InsnID*/0,
        GIR_EraseFromParent, /*InsnID*/0,
        // GIR_Coverage, 1001,
        GIR_Done,
      // Label 3538: @230610
      GIM_Try, /*On fail goto*//*Label 3539*/ GIMT_Encode4(230694), // Rule ID 1002 //
        GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasMAIInsts),
        GIM_CheckIntrinsicID, /*MI*/0, /*Op*/1, GIMT_Encode2(Intrinsic::amdgcn_mfma_f32_4x4x4f16),
        GIM_CheckType, /*MI*/0, /*Op*/0, /*Type*/GILLT_v4s32,
        GIM_CheckType, /*MI*/0, /*Op*/2, /*Type*/GILLT_v4s16,
        GIM_CheckType, /*MI*/0, /*Op*/3, /*Type*/GILLT_v4s16,
        GIM_CheckType, /*MI*/0, /*Op*/4, /*Type*/GILLT_v4s32,
        GIM_CheckRegBankForClass, /*MI*/0, /*Op*/0, /*RC*/GIMT_Encode2(AMDGPU::AReg_128RegClassID),
        // MIs[0] cbsz
        GIM_CheckIsImm, /*MI*/0, /*Op*/5,
        // MIs[0] abid
        GIM_CheckIsImm, /*MI*/0, /*Op*/6,
        // MIs[0] blgp
        GIM_CheckIsImm, /*MI*/0, /*Op*/7,
        GIM_CheckCxxInsnPredicate, /*MI*/0, /*FnId*/GIMT_Encode2(GICXXPred_MI_Predicate_anonymous_24750),
        // (intrinsic_wo_chain:{ *:[v4f32] } 2569:{ *:[iPTR] }, v4f16:{ *:[v4f16] }:$src0, v4f16:{ *:[v4f16] }:$src1, v4f32:{ *:[v4f32] }:$src2, (timm:{ *:[i32] }):$cbsz, (timm:{ *:[i32] }):$abid, (timm:{ *:[i32] }):$blgp)<<P:Predicate_anonymous_24750>>  =>  (V_MFMA_F32_4X4X4F16_e64:{ *:[v4f32] } v4f16:{ *:[v4f16] }:$src0, v4f16:{ *:[v4f16] }:$src1, v4f32:{ *:[v4f32] }:$src2, (timm:{ *:[i32] }):$cbsz, (timm:{ *:[i32] }):$abid, (timm:{ *:[i32] }):$blgp)
        GIR_BuildMI, /*InsnID*/0, /*Opcode*/GIMT_Encode2(AMDGPU::V_MFMA_F32_4X4X4F16_e64),
        GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/0, // DstI[vdst]
        GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/2, // src0
        GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/3, // src1
        GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/4, // src2
        GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/5, // cbsz
        GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/6, // abid
        GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/7, // blgp
        GIR_ConstrainSelectedInstOperands, /*InsnID*/0,
        GIR_EraseFromParent, /*InsnID*/0,
        // GIR_Coverage, 1002,
        GIR_Done,
      // Label 3539: @230694
      GIM_Try, /*On fail goto*//*Label 3540*/ GIMT_Encode4(230778), // Rule ID 1003 //
        GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasMAIInsts),
        GIM_CheckIntrinsicID, /*MI*/0, /*Op*/1, GIMT_Encode2(Intrinsic::amdgcn_mfma_f32_4x4x4f16),
        GIM_CheckType, /*MI*/0, /*Op*/0, /*Type*/GILLT_v4s32,
        GIM_CheckType, /*MI*/0, /*Op*/2, /*Type*/GILLT_v4s16,
        GIM_CheckType, /*MI*/0, /*Op*/3, /*Type*/GILLT_v4s16,
        GIM_CheckType, /*MI*/0, /*Op*/4, /*Type*/GILLT_v4s32,
        GIM_CheckRegBankForClass, /*MI*/0, /*Op*/0, /*RC*/GIMT_Encode2(AMDGPU::VReg_128RegClassID),
        // MIs[0] cbsz
        GIM_CheckIsImm, /*MI*/0, /*Op*/5,
        // MIs[0] abid
        GIM_CheckIsImm, /*MI*/0, /*Op*/6,
        // MIs[0] blgp
        GIM_CheckIsImm, /*MI*/0, /*Op*/7,
        GIM_CheckCxxInsnPredicate, /*MI*/0, /*FnId*/GIMT_Encode2(GICXXPred_MI_Predicate_anonymous_24752),
        // (intrinsic_wo_chain:{ *:[v4f32] } 2569:{ *:[iPTR] }, v4f16:{ *:[v4f16] }:$src0, v4f16:{ *:[v4f16] }:$src1, v4f32:{ *:[v4f32] }:$src2, (timm:{ *:[i32] }):$cbsz, (timm:{ *:[i32] }):$abid, (timm:{ *:[i32] }):$blgp)<<P:Predicate_anonymous_24752>>  =>  (V_MFMA_F32_4X4X4F16_vgprcd_e64:{ *:[v4f32] } v4f16:{ *:[v4f16] }:$src0, v4f16:{ *:[v4f16] }:$src1, v4f32:{ *:[v4f32] }:$src2, (timm:{ *:[i32] }):$cbsz, (timm:{ *:[i32] }):$abid, (timm:{ *:[i32] }):$blgp)
        GIR_BuildMI, /*InsnID*/0, /*Opcode*/GIMT_Encode2(AMDGPU::V_MFMA_F32_4X4X4F16_vgprcd_e64),
        GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/0, // DstI[vdst]
        GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/2, // src0
        GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/3, // src1
        GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/4, // src2
        GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/5, // cbsz
        GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/6, // abid
        GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/7, // blgp
        GIR_ConstrainSelectedInstOperands, /*InsnID*/0,
        GIR_EraseFromParent, /*InsnID*/0,
        // GIR_Coverage, 1003,
        GIR_Done,
      // Label 3540: @230778
      GIM_Try, /*On fail goto*//*Label 3541*/ GIMT_Encode4(230862), // Rule ID 1004 //
        GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasMAIInsts),
        GIM_CheckIntrinsicID, /*MI*/0, /*Op*/1, GIMT_Encode2(Intrinsic::amdgcn_mfma_i32_4x4x4i8),
        GIM_CheckType, /*MI*/0, /*Op*/0, /*Type*/GILLT_v4s32,
        GIM_CheckType, /*MI*/0, /*Op*/2, /*Type*/GILLT_s32,
        GIM_CheckType, /*MI*/0, /*Op*/3, /*Type*/GILLT_s32,
        GIM_CheckType, /*MI*/0, /*Op*/4, /*Type*/GILLT_v4s32,
        GIM_CheckRegBankForClass, /*MI*/0, /*Op*/0, /*RC*/GIMT_Encode2(AMDGPU::AReg_128RegClassID),
        // MIs[0] cbsz
        GIM_CheckIsImm, /*MI*/0, /*Op*/5,
        // MIs[0] abid
        GIM_CheckIsImm, /*MI*/0, /*Op*/6,
        // MIs[0] blgp
        GIM_CheckIsImm, /*MI*/0, /*Op*/7,
        GIM_CheckCxxInsnPredicate, /*MI*/0, /*FnId*/GIMT_Encode2(GICXXPred_MI_Predicate_anonymous_24754),
        // (intrinsic_wo_chain:{ *:[v4i32] } 2578:{ *:[iPTR] }, i32:{ *:[i32] }:$src0, i32:{ *:[i32] }:$src1, v4i32:{ *:[v4i32] }:$src2, (timm:{ *:[i32] }):$cbsz, (timm:{ *:[i32] }):$abid, (timm:{ *:[i32] }):$blgp)<<P:Predicate_anonymous_24754>>  =>  (V_MFMA_I32_4X4X4I8_e64:{ *:[v4i32] } i32:{ *:[i32] }:$src0, i32:{ *:[i32] }:$src1, v4i32:{ *:[v4i32] }:$src2, (timm:{ *:[i32] }):$cbsz, (timm:{ *:[i32] }):$abid, (timm:{ *:[i32] }):$blgp)
        GIR_BuildMI, /*InsnID*/0, /*Opcode*/GIMT_Encode2(AMDGPU::V_MFMA_I32_4X4X4I8_e64),
        GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/0, // DstI[vdst]
        GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/2, // src0
        GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/3, // src1
        GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/4, // src2
        GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/5, // cbsz
        GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/6, // abid
        GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/7, // blgp
        GIR_ConstrainSelectedInstOperands, /*InsnID*/0,
        GIR_EraseFromParent, /*InsnID*/0,
        // GIR_Coverage, 1004,
        GIR_Done,
      // Label 3541: @230862
      GIM_Try, /*On fail goto*//*Label 3542*/ GIMT_Encode4(230946), // Rule ID 1005 //
        GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasMAIInsts),
        GIM_CheckIntrinsicID, /*MI*/0, /*Op*/1, GIMT_Encode2(Intrinsic::amdgcn_mfma_i32_4x4x4i8),
        GIM_CheckType, /*MI*/0, /*Op*/0, /*Type*/GILLT_v4s32,
        GIM_CheckType, /*MI*/0, /*Op*/2, /*Type*/GILLT_s32,
        GIM_CheckType, /*MI*/0, /*Op*/3, /*Type*/GILLT_s32,
        GIM_CheckType, /*MI*/0, /*Op*/4, /*Type*/GILLT_v4s32,
        GIM_CheckRegBankForClass, /*MI*/0, /*Op*/0, /*RC*/GIMT_Encode2(AMDGPU::VReg_128RegClassID),
        // MIs[0] cbsz
        GIM_CheckIsImm, /*MI*/0, /*Op*/5,
        // MIs[0] abid
        GIM_CheckIsImm, /*MI*/0, /*Op*/6,
        // MIs[0] blgp
        GIM_CheckIsImm, /*MI*/0, /*Op*/7,
        GIM_CheckCxxInsnPredicate, /*MI*/0, /*FnId*/GIMT_Encode2(GICXXPred_MI_Predicate_anonymous_24756),
        // (intrinsic_wo_chain:{ *:[v4i32] } 2578:{ *:[iPTR] }, i32:{ *:[i32] }:$src0, i32:{ *:[i32] }:$src1, v4i32:{ *:[v4i32] }:$src2, (timm:{ *:[i32] }):$cbsz, (timm:{ *:[i32] }):$abid, (timm:{ *:[i32] }):$blgp)<<P:Predicate_anonymous_24756>>  =>  (V_MFMA_I32_4X4X4I8_vgprcd_e64:{ *:[v4i32] } i32:{ *:[i32] }:$src0, i32:{ *:[i32] }:$src1, v4i32:{ *:[v4i32] }:$src2, (timm:{ *:[i32] }):$cbsz, (timm:{ *:[i32] }):$abid, (timm:{ *:[i32] }):$blgp)
        GIR_BuildMI, /*InsnID*/0, /*Opcode*/GIMT_Encode2(AMDGPU::V_MFMA_I32_4X4X4I8_vgprcd_e64),
        GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/0, // DstI[vdst]
        GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/2, // src0
        GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/3, // src1
        GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/4, // src2
        GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/5, // cbsz
        GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/6, // abid
        GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/7, // blgp
        GIR_ConstrainSelectedInstOperands, /*InsnID*/0,
        GIR_EraseFromParent, /*InsnID*/0,
        // GIR_Coverage, 1005,
        GIR_Done,
      // Label 3542: @230946
      GIM_Try, /*On fail goto*//*Label 3543*/ GIMT_Encode4(231030), // Rule ID 1006 //
        GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasMAIInsts),
        GIM_CheckIntrinsicID, /*MI*/0, /*Op*/1, GIMT_Encode2(Intrinsic::amdgcn_mfma_f32_16x16x4f16),
        GIM_CheckType, /*MI*/0, /*Op*/0, /*Type*/GILLT_v16s32,
        GIM_CheckType, /*MI*/0, /*Op*/2, /*Type*/GILLT_v4s16,
        GIM_CheckType, /*MI*/0, /*Op*/3, /*Type*/GILLT_v4s16,
        GIM_CheckType, /*MI*/0, /*Op*/4, /*Type*/GILLT_v16s32,
        GIM_CheckRegBankForClass, /*MI*/0, /*Op*/0, /*RC*/GIMT_Encode2(AMDGPU::AReg_512RegClassID),
        // MIs[0] cbsz
        GIM_CheckIsImm, /*MI*/0, /*Op*/5,
        // MIs[0] abid
        GIM_CheckIsImm, /*MI*/0, /*Op*/6,
        // MIs[0] blgp
        GIM_CheckIsImm, /*MI*/0, /*Op*/7,
        GIM_CheckCxxInsnPredicate, /*MI*/0, /*FnId*/GIMT_Encode2(GICXXPred_MI_Predicate_anonymous_24760),
        // (intrinsic_wo_chain:{ *:[v16f32] } 2549:{ *:[iPTR] }, v4f16:{ *:[v4f16] }:$src0, v4f16:{ *:[v4f16] }:$src1, v16f32:{ *:[v16f32] }:$src2, (timm:{ *:[i32] }):$cbsz, (timm:{ *:[i32] }):$abid, (timm:{ *:[i32] }):$blgp)<<P:Predicate_anonymous_24760>>  =>  (V_MFMA_F32_16X16X4F16_mac_e64:{ *:[v16f32] } v4f16:{ *:[v4f16] }:$src0, v4f16:{ *:[v4f16] }:$src1, v16f32:{ *:[v16f32] }:$src2, (timm:{ *:[i32] }):$cbsz, (timm:{ *:[i32] }):$abid, (timm:{ *:[i32] }):$blgp)
        GIR_BuildMI, /*InsnID*/0, /*Opcode*/GIMT_Encode2(AMDGPU::V_MFMA_F32_16X16X4F16_mac_e64),
        GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/0, // DstI[vdst]
        GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/2, // src0
        GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/3, // src1
        GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/4, // src2
        GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/5, // cbsz
        GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/6, // abid
        GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/7, // blgp
        GIR_ConstrainSelectedInstOperands, /*InsnID*/0,
        GIR_EraseFromParent, /*InsnID*/0,
        // GIR_Coverage, 1006,
        GIR_Done,
      // Label 3543: @231030
      GIM_Try, /*On fail goto*//*Label 3544*/ GIMT_Encode4(231114), // Rule ID 1007 //
        GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasMAIInsts),
        GIM_CheckIntrinsicID, /*MI*/0, /*Op*/1, GIMT_Encode2(Intrinsic::amdgcn_mfma_f32_16x16x4f16),
        GIM_CheckType, /*MI*/0, /*Op*/0, /*Type*/GILLT_v16s32,
        GIM_CheckType, /*MI*/0, /*Op*/2, /*Type*/GILLT_v4s16,
        GIM_CheckType, /*MI*/0, /*Op*/3, /*Type*/GILLT_v4s16,
        GIM_CheckType, /*MI*/0, /*Op*/4, /*Type*/GILLT_v16s32,
        GIM_CheckRegBankForClass, /*MI*/0, /*Op*/0, /*RC*/GIMT_Encode2(AMDGPU::VReg_512RegClassID),
        // MIs[0] cbsz
        GIM_CheckIsImm, /*MI*/0, /*Op*/5,
        // MIs[0] abid
        GIM_CheckIsImm, /*MI*/0, /*Op*/6,
        // MIs[0] blgp
        GIM_CheckIsImm, /*MI*/0, /*Op*/7,
        GIM_CheckCxxInsnPredicate, /*MI*/0, /*FnId*/GIMT_Encode2(GICXXPred_MI_Predicate_anonymous_24762),
        // (intrinsic_wo_chain:{ *:[v16f32] } 2549:{ *:[iPTR] }, v4f16:{ *:[v4f16] }:$src0, v4f16:{ *:[v4f16] }:$src1, v16f32:{ *:[v16f32] }:$src2, (timm:{ *:[i32] }):$cbsz, (timm:{ *:[i32] }):$abid, (timm:{ *:[i32] }):$blgp)<<P:Predicate_anonymous_24762>>  =>  (V_MFMA_F32_16X16X4F16_mac_vgprcd_e64:{ *:[v16f32] } v4f16:{ *:[v4f16] }:$src0, v4f16:{ *:[v4f16] }:$src1, v16f32:{ *:[v16f32] }:$src2, (timm:{ *:[i32] }):$cbsz, (timm:{ *:[i32] }):$abid, (timm:{ *:[i32] }):$blgp)
        GIR_BuildMI, /*InsnID*/0, /*Opcode*/GIMT_Encode2(AMDGPU::V_MFMA_F32_16X16X4F16_mac_vgprcd_e64),
        GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/0, // DstI[vdst]
        GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/2, // src0
        GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/3, // src1
        GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/4, // src2
        GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/5, // cbsz
        GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/6, // abid
        GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/7, // blgp
        GIR_ConstrainSelectedInstOperands, /*InsnID*/0,
        GIR_EraseFromParent, /*InsnID*/0,
        // GIR_Coverage, 1007,
        GIR_Done,
      // Label 3544: @231114
      GIM_Try, /*On fail goto*//*Label 3545*/ GIMT_Encode4(231198), // Rule ID 1008 //
        GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasMAIInsts),
        GIM_CheckIntrinsicID, /*MI*/0, /*Op*/1, GIMT_Encode2(Intrinsic::amdgcn_mfma_f32_16x16x16f16),
        GIM_CheckType, /*MI*/0, /*Op*/0, /*Type*/GILLT_v4s32,
        GIM_CheckType, /*MI*/0, /*Op*/2, /*Type*/GILLT_v4s16,
        GIM_CheckType, /*MI*/0, /*Op*/3, /*Type*/GILLT_v4s16,
        GIM_CheckType, /*MI*/0, /*Op*/4, /*Type*/GILLT_v4s32,
        GIM_CheckRegBankForClass, /*MI*/0, /*Op*/0, /*RC*/GIMT_Encode2(AMDGPU::AReg_128RegClassID),
        // MIs[0] cbsz
        GIM_CheckIsImm, /*MI*/0, /*Op*/5,
        // MIs[0] abid
        GIM_CheckIsImm, /*MI*/0, /*Op*/6,
        // MIs[0] blgp
        GIM_CheckIsImm, /*MI*/0, /*Op*/7,
        GIM_CheckCxxInsnPredicate, /*MI*/0, /*FnId*/GIMT_Encode2(GICXXPred_MI_Predicate_anonymous_24764),
        // (intrinsic_wo_chain:{ *:[v4f32] } 2541:{ *:[iPTR] }, v4f16:{ *:[v4f16] }:$src0, v4f16:{ *:[v4f16] }:$src1, v4f32:{ *:[v4f32] }:$src2, (timm:{ *:[i32] }):$cbsz, (timm:{ *:[i32] }):$abid, (timm:{ *:[i32] }):$blgp)<<P:Predicate_anonymous_24764>>  =>  (V_MFMA_F32_16X16X16F16_e64:{ *:[v4f32] } v4f16:{ *:[v4f16] }:$src0, v4f16:{ *:[v4f16] }:$src1, v4f32:{ *:[v4f32] }:$src2, (timm:{ *:[i32] }):$cbsz, (timm:{ *:[i32] }):$abid, (timm:{ *:[i32] }):$blgp)
        GIR_BuildMI, /*InsnID*/0, /*Opcode*/GIMT_Encode2(AMDGPU::V_MFMA_F32_16X16X16F16_e64),
        GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/0, // DstI[vdst]
        GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/2, // src0
        GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/3, // src1
        GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/4, // src2
        GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/5, // cbsz
        GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/6, // abid
        GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/7, // blgp
        GIR_ConstrainSelectedInstOperands, /*InsnID*/0,
        GIR_EraseFromParent, /*InsnID*/0,
        // GIR_Coverage, 1008,
        GIR_Done,
      // Label 3545: @231198
      GIM_Try, /*On fail goto*//*Label 3546*/ GIMT_Encode4(231282), // Rule ID 1009 //
        GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasMAIInsts),
        GIM_CheckIntrinsicID, /*MI*/0, /*Op*/1, GIMT_Encode2(Intrinsic::amdgcn_mfma_f32_16x16x16f16),
        GIM_CheckType, /*MI*/0, /*Op*/0, /*Type*/GILLT_v4s32,
        GIM_CheckType, /*MI*/0, /*Op*/2, /*Type*/GILLT_v4s16,
        GIM_CheckType, /*MI*/0, /*Op*/3, /*Type*/GILLT_v4s16,
        GIM_CheckType, /*MI*/0, /*Op*/4, /*Type*/GILLT_v4s32,
        GIM_CheckRegBankForClass, /*MI*/0, /*Op*/0, /*RC*/GIMT_Encode2(AMDGPU::VReg_128RegClassID),
        // MIs[0] cbsz
        GIM_CheckIsImm, /*MI*/0, /*Op*/5,
        // MIs[0] abid
        GIM_CheckIsImm, /*MI*/0, /*Op*/6,
        // MIs[0] blgp
        GIM_CheckIsImm, /*MI*/0, /*Op*/7,
        GIM_CheckCxxInsnPredicate, /*MI*/0, /*FnId*/GIMT_Encode2(GICXXPred_MI_Predicate_anonymous_24766),
        // (intrinsic_wo_chain:{ *:[v4f32] } 2541:{ *:[iPTR] }, v4f16:{ *:[v4f16] }:$src0, v4f16:{ *:[v4f16] }:$src1, v4f32:{ *:[v4f32] }:$src2, (timm:{ *:[i32] }):$cbsz, (timm:{ *:[i32] }):$abid, (timm:{ *:[i32] }):$blgp)<<P:Predicate_anonymous_24766>>  =>  (V_MFMA_F32_16X16X16F16_vgprcd_e64:{ *:[v4f32] } v4f16:{ *:[v4f16] }:$src0, v4f16:{ *:[v4f16] }:$src1, v4f32:{ *:[v4f32] }:$src2, (timm:{ *:[i32] }):$cbsz, (timm:{ *:[i32] }):$abid, (timm:{ *:[i32] }):$blgp)
        GIR_BuildMI, /*InsnID*/0, /*Opcode*/GIMT_Encode2(AMDGPU::V_MFMA_F32_16X16X16F16_vgprcd_e64),
        GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/0, // DstI[vdst]
        GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/2, // src0
        GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/3, // src1
        GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/4, // src2
        GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/5, // cbsz
        GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/6, // abid
        GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/7, // blgp
        GIR_ConstrainSelectedInstOperands, /*InsnID*/0,
        GIR_EraseFromParent, /*InsnID*/0,
        // GIR_Coverage, 1009,
        GIR_Done,
      // Label 3546: @231282
      GIM_Try, /*On fail goto*//*Label 3547*/ GIMT_Encode4(231366), // Rule ID 1010 //
        GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasMAIInsts),
        GIM_CheckIntrinsicID, /*MI*/0, /*Op*/1, GIMT_Encode2(Intrinsic::amdgcn_mfma_i32_16x16x4i8),
        GIM_CheckType, /*MI*/0, /*Op*/0, /*Type*/GILLT_v16s32,
        GIM_CheckType, /*MI*/0, /*Op*/2, /*Type*/GILLT_s32,
        GIM_CheckType, /*MI*/0, /*Op*/3, /*Type*/GILLT_s32,
        GIM_CheckType, /*MI*/0, /*Op*/4, /*Type*/GILLT_v16s32,
        GIM_CheckRegBankForClass, /*MI*/0, /*Op*/0, /*RC*/GIMT_Encode2(AMDGPU::AReg_512RegClassID),
        // MIs[0] cbsz
        GIM_CheckIsImm, /*MI*/0, /*Op*/5,
        // MIs[0] abid
        GIM_CheckIsImm, /*MI*/0, /*Op*/6,
        // MIs[0] blgp
        GIM_CheckIsImm, /*MI*/0, /*Op*/7,
        GIM_CheckCxxInsnPredicate, /*MI*/0, /*FnId*/GIMT_Encode2(GICXXPred_MI_Predicate_anonymous_24770),
        // (intrinsic_wo_chain:{ *:[v16i32] } 2574:{ *:[iPTR] }, i32:{ *:[i32] }:$src0, i32:{ *:[i32] }:$src1, v16i32:{ *:[v16i32] }:$src2, (timm:{ *:[i32] }):$cbsz, (timm:{ *:[i32] }):$abid, (timm:{ *:[i32] }):$blgp)<<P:Predicate_anonymous_24770>>  =>  (V_MFMA_I32_16X16X4I8_mac_e64:{ *:[v16i32] } i32:{ *:[i32] }:$src0, i32:{ *:[i32] }:$src1, v16i32:{ *:[v16i32] }:$src2, (timm:{ *:[i32] }):$cbsz, (timm:{ *:[i32] }):$abid, (timm:{ *:[i32] }):$blgp)
        GIR_BuildMI, /*InsnID*/0, /*Opcode*/GIMT_Encode2(AMDGPU::V_MFMA_I32_16X16X4I8_mac_e64),
        GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/0, // DstI[vdst]
        GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/2, // src0
        GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/3, // src1
        GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/4, // src2
        GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/5, // cbsz
        GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/6, // abid
        GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/7, // blgp
        GIR_ConstrainSelectedInstOperands, /*InsnID*/0,
        GIR_EraseFromParent, /*InsnID*/0,
        // GIR_Coverage, 1010,
        GIR_Done,
      // Label 3547: @231366
      GIM_Try, /*On fail goto*//*Label 3548*/ GIMT_Encode4(231450), // Rule ID 1011 //
        GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasMAIInsts),
        GIM_CheckIntrinsicID, /*MI*/0, /*Op*/1, GIMT_Encode2(Intrinsic::amdgcn_mfma_i32_16x16x4i8),
        GIM_CheckType, /*MI*/0, /*Op*/0, /*Type*/GILLT_v16s32,
        GIM_CheckType, /*MI*/0, /*Op*/2, /*Type*/GILLT_s32,
        GIM_CheckType, /*MI*/0, /*Op*/3, /*Type*/GILLT_s32,
        GIM_CheckType, /*MI*/0, /*Op*/4, /*Type*/GILLT_v16s32,
        GIM_CheckRegBankForClass, /*MI*/0, /*Op*/0, /*RC*/GIMT_Encode2(AMDGPU::VReg_512RegClassID),
        // MIs[0] cbsz
        GIM_CheckIsImm, /*MI*/0, /*Op*/5,
        // MIs[0] abid
        GIM_CheckIsImm, /*MI*/0, /*Op*/6,
        // MIs[0] blgp
        GIM_CheckIsImm, /*MI*/0, /*Op*/7,
        GIM_CheckCxxInsnPredicate, /*MI*/0, /*FnId*/GIMT_Encode2(GICXXPred_MI_Predicate_anonymous_24772),
        // (intrinsic_wo_chain:{ *:[v16i32] } 2574:{ *:[iPTR] }, i32:{ *:[i32] }:$src0, i32:{ *:[i32] }:$src1, v16i32:{ *:[v16i32] }:$src2, (timm:{ *:[i32] }):$cbsz, (timm:{ *:[i32] }):$abid, (timm:{ *:[i32] }):$blgp)<<P:Predicate_anonymous_24772>>  =>  (V_MFMA_I32_16X16X4I8_mac_vgprcd_e64:{ *:[v16i32] } i32:{ *:[i32] }:$src0, i32:{ *:[i32] }:$src1, v16i32:{ *:[v16i32] }:$src2, (timm:{ *:[i32] }):$cbsz, (timm:{ *:[i32] }):$abid, (timm:{ *:[i32] }):$blgp)
        GIR_BuildMI, /*InsnID*/0, /*Opcode*/GIMT_Encode2(AMDGPU::V_MFMA_I32_16X16X4I8_mac_vgprcd_e64),
        GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/0, // DstI[vdst]
        GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/2, // src0
        GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/3, // src1
        GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/4, // src2
        GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/5, // cbsz
        GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/6, // abid
        GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/7, // blgp
        GIR_ConstrainSelectedInstOperands, /*InsnID*/0,
        GIR_EraseFromParent, /*InsnID*/0,
        // GIR_Coverage, 1011,
        GIR_Done,
      // Label 3548: @231450
      GIM_Try, /*On fail goto*//*Label 3549*/ GIMT_Encode4(231534), // Rule ID 1012 //
        GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasMAIInsts),
        GIM_CheckIntrinsicID, /*MI*/0, /*Op*/1, GIMT_Encode2(Intrinsic::amdgcn_mfma_f32_32x32x4f16),
        GIM_CheckType, /*MI*/0, /*Op*/0, /*Type*/GILLT_v32s32,
        GIM_CheckType, /*MI*/0, /*Op*/2, /*Type*/GILLT_v4s16,
        GIM_CheckType, /*MI*/0, /*Op*/3, /*Type*/GILLT_v4s16,
        GIM_CheckType, /*MI*/0, /*Op*/4, /*Type*/GILLT_v32s32,
        GIM_CheckRegBankForClass, /*MI*/0, /*Op*/0, /*RC*/GIMT_Encode2(AMDGPU::AReg_1024RegClassID),
        // MIs[0] cbsz
        GIM_CheckIsImm, /*MI*/0, /*Op*/5,
        // MIs[0] abid
        GIM_CheckIsImm, /*MI*/0, /*Op*/6,
        // MIs[0] blgp
        GIM_CheckIsImm, /*MI*/0, /*Op*/7,
        GIM_CheckCxxInsnPredicate, /*MI*/0, /*FnId*/GIMT_Encode2(GICXXPred_MI_Predicate_anonymous_24776),
        // (intrinsic_wo_chain:{ *:[v32f32] } 2563:{ *:[iPTR] }, v4f16:{ *:[v4f16] }:$src0, v4f16:{ *:[v4f16] }:$src1, v32f32:{ *:[v32f32] }:$src2, (timm:{ *:[i32] }):$cbsz, (timm:{ *:[i32] }):$abid, (timm:{ *:[i32] }):$blgp)<<P:Predicate_anonymous_24776>>  =>  (V_MFMA_F32_32X32X4F16_mac_e64:{ *:[v32f32] } v4f16:{ *:[v4f16] }:$src0, v4f16:{ *:[v4f16] }:$src1, v32f32:{ *:[v32f32] }:$src2, (timm:{ *:[i32] }):$cbsz, (timm:{ *:[i32] }):$abid, (timm:{ *:[i32] }):$blgp)
        GIR_BuildMI, /*InsnID*/0, /*Opcode*/GIMT_Encode2(AMDGPU::V_MFMA_F32_32X32X4F16_mac_e64),
        GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/0, // DstI[vdst]
        GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/2, // src0
        GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/3, // src1
        GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/4, // src2
        GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/5, // cbsz
        GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/6, // abid
        GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/7, // blgp
        GIR_ConstrainSelectedInstOperands, /*InsnID*/0,
        GIR_EraseFromParent, /*InsnID*/0,
        // GIR_Coverage, 1012,
        GIR_Done,
      // Label 3549: @231534
      GIM_Try, /*On fail goto*//*Label 3550*/ GIMT_Encode4(231618), // Rule ID 1013 //
        GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasMAIInsts),
        GIM_CheckIntrinsicID, /*MI*/0, /*Op*/1, GIMT_Encode2(Intrinsic::amdgcn_mfma_f32_32x32x4f16),
        GIM_CheckType, /*MI*/0, /*Op*/0, /*Type*/GILLT_v32s32,
        GIM_CheckType, /*MI*/0, /*Op*/2, /*Type*/GILLT_v4s16,
        GIM_CheckType, /*MI*/0, /*Op*/3, /*Type*/GILLT_v4s16,
        GIM_CheckType, /*MI*/0, /*Op*/4, /*Type*/GILLT_v32s32,
        GIM_CheckRegBankForClass, /*MI*/0, /*Op*/0, /*RC*/GIMT_Encode2(AMDGPU::VReg_1024RegClassID),
        // MIs[0] cbsz
        GIM_CheckIsImm, /*MI*/0, /*Op*/5,
        // MIs[0] abid
        GIM_CheckIsImm, /*MI*/0, /*Op*/6,
        // MIs[0] blgp
        GIM_CheckIsImm, /*MI*/0, /*Op*/7,
        GIM_CheckCxxInsnPredicate, /*MI*/0, /*FnId*/GIMT_Encode2(GICXXPred_MI_Predicate_anonymous_24778),
        // (intrinsic_wo_chain:{ *:[v32f32] } 2563:{ *:[iPTR] }, v4f16:{ *:[v4f16] }:$src0, v4f16:{ *:[v4f16] }:$src1, v32f32:{ *:[v32f32] }:$src2, (timm:{ *:[i32] }):$cbsz, (timm:{ *:[i32] }):$abid, (timm:{ *:[i32] }):$blgp)<<P:Predicate_anonymous_24778>>  =>  (V_MFMA_F32_32X32X4F16_mac_vgprcd_e64:{ *:[v32f32] } v4f16:{ *:[v4f16] }:$src0, v4f16:{ *:[v4f16] }:$src1, v32f32:{ *:[v32f32] }:$src2, (timm:{ *:[i32] }):$cbsz, (timm:{ *:[i32] }):$abid, (timm:{ *:[i32] }):$blgp)
        GIR_BuildMI, /*InsnID*/0, /*Opcode*/GIMT_Encode2(AMDGPU::V_MFMA_F32_32X32X4F16_mac_vgprcd_e64),
        GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/0, // DstI[vdst]
        GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/2, // src0
        GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/3, // src1
        GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/4, // src2
        GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/5, // cbsz
        GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/6, // abid
        GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/7, // blgp
        GIR_ConstrainSelectedInstOperands, /*InsnID*/0,
        GIR_EraseFromParent, /*InsnID*/0,
        // GIR_Coverage, 1013,
        GIR_Done,
      // Label 3550: @231618
      GIM_Try, /*On fail goto*//*Label 3551*/ GIMT_Encode4(231702), // Rule ID 1014 //
        GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasMAIInsts),
        GIM_CheckIntrinsicID, /*MI*/0, /*Op*/1, GIMT_Encode2(Intrinsic::amdgcn_mfma_f32_32x32x8f16),
        GIM_CheckType, /*MI*/0, /*Op*/0, /*Type*/GILLT_v16s32,
        GIM_CheckType, /*MI*/0, /*Op*/2, /*Type*/GILLT_v4s16,
        GIM_CheckType, /*MI*/0, /*Op*/3, /*Type*/GILLT_v4s16,
        GIM_CheckType, /*MI*/0, /*Op*/4, /*Type*/GILLT_v16s32,
        GIM_CheckRegBankForClass, /*MI*/0, /*Op*/0, /*RC*/GIMT_Encode2(AMDGPU::AReg_512RegClassID),
        // MIs[0] cbsz
        GIM_CheckIsImm, /*MI*/0, /*Op*/5,
        // MIs[0] abid
        GIM_CheckIsImm, /*MI*/0, /*Op*/6,
        // MIs[0] blgp
        GIM_CheckIsImm, /*MI*/0, /*Op*/7,
        GIM_CheckCxxInsnPredicate, /*MI*/0, /*FnId*/GIMT_Encode2(GICXXPred_MI_Predicate_anonymous_24780),
        // (intrinsic_wo_chain:{ *:[v16f32] } 2565:{ *:[iPTR] }, v4f16:{ *:[v4f16] }:$src0, v4f16:{ *:[v4f16] }:$src1, v16f32:{ *:[v16f32] }:$src2, (timm:{ *:[i32] }):$cbsz, (timm:{ *:[i32] }):$abid, (timm:{ *:[i32] }):$blgp)<<P:Predicate_anonymous_24780>>  =>  (V_MFMA_F32_32X32X8F16_mac_e64:{ *:[v16f32] } v4f16:{ *:[v4f16] }:$src0, v4f16:{ *:[v4f16] }:$src1, v16f32:{ *:[v16f32] }:$src2, (timm:{ *:[i32] }):$cbsz, (timm:{ *:[i32] }):$abid, (timm:{ *:[i32] }):$blgp)
        GIR_BuildMI, /*InsnID*/0, /*Opcode*/GIMT_Encode2(AMDGPU::V_MFMA_F32_32X32X8F16_mac_e64),
        GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/0, // DstI[vdst]
        GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/2, // src0
        GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/3, // src1
        GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/4, // src2
        GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/5, // cbsz
        GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/6, // abid
        GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/7, // blgp
        GIR_ConstrainSelectedInstOperands, /*InsnID*/0,
        GIR_EraseFromParent, /*InsnID*/0,
        // GIR_Coverage, 1014,
        GIR_Done,
      // Label 3551: @231702
      GIM_Try, /*On fail goto*//*Label 3552*/ GIMT_Encode4(231786), // Rule ID 1015 //
        GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasMAIInsts),
        GIM_CheckIntrinsicID, /*MI*/0, /*Op*/1, GIMT_Encode2(Intrinsic::amdgcn_mfma_f32_32x32x8f16),
        GIM_CheckType, /*MI*/0, /*Op*/0, /*Type*/GILLT_v16s32,
        GIM_CheckType, /*MI*/0, /*Op*/2, /*Type*/GILLT_v4s16,
        GIM_CheckType, /*MI*/0, /*Op*/3, /*Type*/GILLT_v4s16,
        GIM_CheckType, /*MI*/0, /*Op*/4, /*Type*/GILLT_v16s32,
        GIM_CheckRegBankForClass, /*MI*/0, /*Op*/0, /*RC*/GIMT_Encode2(AMDGPU::VReg_512RegClassID),
        // MIs[0] cbsz
        GIM_CheckIsImm, /*MI*/0, /*Op*/5,
        // MIs[0] abid
        GIM_CheckIsImm, /*MI*/0, /*Op*/6,
        // MIs[0] blgp
        GIM_CheckIsImm, /*MI*/0, /*Op*/7,
        GIM_CheckCxxInsnPredicate, /*MI*/0, /*FnId*/GIMT_Encode2(GICXXPred_MI_Predicate_anonymous_24782),
        // (intrinsic_wo_chain:{ *:[v16f32] } 2565:{ *:[iPTR] }, v4f16:{ *:[v4f16] }:$src0, v4f16:{ *:[v4f16] }:$src1, v16f32:{ *:[v16f32] }:$src2, (timm:{ *:[i32] }):$cbsz, (timm:{ *:[i32] }):$abid, (timm:{ *:[i32] }):$blgp)<<P:Predicate_anonymous_24782>>  =>  (V_MFMA_F32_32X32X8F16_mac_vgprcd_e64:{ *:[v16f32] } v4f16:{ *:[v4f16] }:$src0, v4f16:{ *:[v4f16] }:$src1, v16f32:{ *:[v16f32] }:$src2, (timm:{ *:[i32] }):$cbsz, (timm:{ *:[i32] }):$abid, (timm:{ *:[i32] }):$blgp)
        GIR_BuildMI, /*InsnID*/0, /*Opcode*/GIMT_Encode2(AMDGPU::V_MFMA_F32_32X32X8F16_mac_vgprcd_e64),
        GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/0, // DstI[vdst]
        GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/2, // src0
        GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/3, // src1
        GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/4, // src2
        GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/5, // cbsz
        GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/6, // abid
        GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/7, // blgp
        GIR_ConstrainSelectedInstOperands, /*InsnID*/0,
        GIR_EraseFromParent, /*InsnID*/0,
        // GIR_Coverage, 1015,
        GIR_Done,
      // Label 3552: @231786
      GIM_Try, /*On fail goto*//*Label 3553*/ GIMT_Encode4(231870), // Rule ID 1016 //
        GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasMAIInsts),
        GIM_CheckIntrinsicID, /*MI*/0, /*Op*/1, GIMT_Encode2(Intrinsic::amdgcn_mfma_i32_32x32x4i8),
        GIM_CheckType, /*MI*/0, /*Op*/0, /*Type*/GILLT_v32s32,
        GIM_CheckType, /*MI*/0, /*Op*/2, /*Type*/GILLT_s32,
        GIM_CheckType, /*MI*/0, /*Op*/3, /*Type*/GILLT_s32,
        GIM_CheckType, /*MI*/0, /*Op*/4, /*Type*/GILLT_v32s32,
        GIM_CheckRegBankForClass, /*MI*/0, /*Op*/0, /*RC*/GIMT_Encode2(AMDGPU::AReg_1024RegClassID),
        // MIs[0] cbsz
        GIM_CheckIsImm, /*MI*/0, /*Op*/5,
        // MIs[0] abid
        GIM_CheckIsImm, /*MI*/0, /*Op*/6,
        // MIs[0] blgp
        GIM_CheckIsImm, /*MI*/0, /*Op*/7,
        GIM_CheckCxxInsnPredicate, /*MI*/0, /*FnId*/GIMT_Encode2(GICXXPred_MI_Predicate_anonymous_24786),
        // (intrinsic_wo_chain:{ *:[v32i32] } 2576:{ *:[iPTR] }, i32:{ *:[i32] }:$src0, i32:{ *:[i32] }:$src1, v32i32:{ *:[v32i32] }:$src2, (timm:{ *:[i32] }):$cbsz, (timm:{ *:[i32] }):$abid, (timm:{ *:[i32] }):$blgp)<<P:Predicate_anonymous_24786>>  =>  (V_MFMA_I32_32X32X4I8_mac_e64:{ *:[v32i32] } i32:{ *:[i32] }:$src0, i32:{ *:[i32] }:$src1, v32i32:{ *:[v32i32] }:$src2, (timm:{ *:[i32] }):$cbsz, (timm:{ *:[i32] }):$abid, (timm:{ *:[i32] }):$blgp)
        GIR_BuildMI, /*InsnID*/0, /*Opcode*/GIMT_Encode2(AMDGPU::V_MFMA_I32_32X32X4I8_mac_e64),
        GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/0, // DstI[vdst]
        GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/2, // src0
        GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/3, // src1
        GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/4, // src2
        GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/5, // cbsz
        GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/6, // abid
        GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/7, // blgp
        GIR_ConstrainSelectedInstOperands, /*InsnID*/0,
        GIR_EraseFromParent, /*InsnID*/0,
        // GIR_Coverage, 1016,
        GIR_Done,
      // Label 3553: @231870
      GIM_Try, /*On fail goto*//*Label 3554*/ GIMT_Encode4(231954), // Rule ID 1017 //
        GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasMAIInsts),
        GIM_CheckIntrinsicID, /*MI*/0, /*Op*/1, GIMT_Encode2(Intrinsic::amdgcn_mfma_i32_32x32x4i8),
        GIM_CheckType, /*MI*/0, /*Op*/0, /*Type*/GILLT_v32s32,
        GIM_CheckType, /*MI*/0, /*Op*/2, /*Type*/GILLT_s32,
        GIM_CheckType, /*MI*/0, /*Op*/3, /*Type*/GILLT_s32,
        GIM_CheckType, /*MI*/0, /*Op*/4, /*Type*/GILLT_v32s32,
        GIM_CheckRegBankForClass, /*MI*/0, /*Op*/0, /*RC*/GIMT_Encode2(AMDGPU::VReg_1024RegClassID),
        // MIs[0] cbsz
        GIM_CheckIsImm, /*MI*/0, /*Op*/5,
        // MIs[0] abid
        GIM_CheckIsImm, /*MI*/0, /*Op*/6,
        // MIs[0] blgp
        GIM_CheckIsImm, /*MI*/0, /*Op*/7,
        GIM_CheckCxxInsnPredicate, /*MI*/0, /*FnId*/GIMT_Encode2(GICXXPred_MI_Predicate_anonymous_24788),
        // (intrinsic_wo_chain:{ *:[v32i32] } 2576:{ *:[iPTR] }, i32:{ *:[i32] }:$src0, i32:{ *:[i32] }:$src1, v32i32:{ *:[v32i32] }:$src2, (timm:{ *:[i32] }):$cbsz, (timm:{ *:[i32] }):$abid, (timm:{ *:[i32] }):$blgp)<<P:Predicate_anonymous_24788>>  =>  (V_MFMA_I32_32X32X4I8_mac_vgprcd_e64:{ *:[v32i32] } i32:{ *:[i32] }:$src0, i32:{ *:[i32] }:$src1, v32i32:{ *:[v32i32] }:$src2, (timm:{ *:[i32] }):$cbsz, (timm:{ *:[i32] }):$abid, (timm:{ *:[i32] }):$blgp)
        GIR_BuildMI, /*InsnID*/0, /*Opcode*/GIMT_Encode2(AMDGPU::V_MFMA_I32_32X32X4I8_mac_vgprcd_e64),
        GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/0, // DstI[vdst]
        GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/2, // src0
        GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/3, // src1
        GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/4, // src2
        GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/5, // cbsz
        GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/6, // abid
        GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/7, // blgp
        GIR_ConstrainSelectedInstOperands, /*InsnID*/0,
        GIR_EraseFromParent, /*InsnID*/0,
        // GIR_Coverage, 1017,
        GIR_Done,
      // Label 3554: @231954
      GIM_Try, /*On fail goto*//*Label 3555*/ GIMT_Encode4(232038), // Rule ID 1018 //
        GIM_CheckFeatures, GIMT_Encode2(GIFBS_isGFX908orGFX90A),
        GIM_CheckIntrinsicID, /*MI*/0, /*Op*/1, GIMT_Encode2(Intrinsic::amdgcn_mfma_i32_16x16x16i8),
        GIM_CheckType, /*MI*/0, /*Op*/0, /*Type*/GILLT_v4s32,
        GIM_CheckType, /*MI*/0, /*Op*/2, /*Type*/GILLT_s32,
        GIM_CheckType, /*MI*/0, /*Op*/3, /*Type*/GILLT_s32,
        GIM_CheckType, /*MI*/0, /*Op*/4, /*Type*/GILLT_v4s32,
        GIM_CheckRegBankForClass, /*MI*/0, /*Op*/0, /*RC*/GIMT_Encode2(AMDGPU::AReg_128RegClassID),
        // MIs[0] cbsz
        GIM_CheckIsImm, /*MI*/0, /*Op*/5,
        // MIs[0] abid
        GIM_CheckIsImm, /*MI*/0, /*Op*/6,
        // MIs[0] blgp
        GIM_CheckIsImm, /*MI*/0, /*Op*/7,
        GIM_CheckCxxInsnPredicate, /*MI*/0, /*FnId*/GIMT_Encode2(GICXXPred_MI_Predicate_anonymous_24790),
        // (intrinsic_wo_chain:{ *:[v4i32] } 2572:{ *:[iPTR] }, i32:{ *:[i32] }:$src0, i32:{ *:[i32] }:$src1, v4i32:{ *:[v4i32] }:$src2, (timm:{ *:[i32] }):$cbsz, (timm:{ *:[i32] }):$abid, (timm:{ *:[i32] }):$blgp)<<P:Predicate_anonymous_24790>>  =>  (V_MFMA_I32_16X16X16I8_e64:{ *:[v4i32] } i32:{ *:[i32] }:$src0, i32:{ *:[i32] }:$src1, v4i32:{ *:[v4i32] }:$src2, (timm:{ *:[i32] }):$cbsz, (timm:{ *:[i32] }):$abid, (timm:{ *:[i32] }):$blgp)
        GIR_BuildMI, /*InsnID*/0, /*Opcode*/GIMT_Encode2(AMDGPU::V_MFMA_I32_16X16X16I8_e64),
        GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/0, // DstI[vdst]
        GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/2, // src0
        GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/3, // src1
        GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/4, // src2
        GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/5, // cbsz
        GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/6, // abid
        GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/7, // blgp
        GIR_ConstrainSelectedInstOperands, /*InsnID*/0,
        GIR_EraseFromParent, /*InsnID*/0,
        // GIR_Coverage, 1018,
        GIR_Done,
      // Label 3555: @232038
      GIM_Try, /*On fail goto*//*Label 3556*/ GIMT_Encode4(232122), // Rule ID 1019 //
        GIM_CheckFeatures, GIMT_Encode2(GIFBS_isGFX908orGFX90A),
        GIM_CheckIntrinsicID, /*MI*/0, /*Op*/1, GIMT_Encode2(Intrinsic::amdgcn_mfma_i32_16x16x16i8),
        GIM_CheckType, /*MI*/0, /*Op*/0, /*Type*/GILLT_v4s32,
        GIM_CheckType, /*MI*/0, /*Op*/2, /*Type*/GILLT_s32,
        GIM_CheckType, /*MI*/0, /*Op*/3, /*Type*/GILLT_s32,
        GIM_CheckType, /*MI*/0, /*Op*/4, /*Type*/GILLT_v4s32,
        GIM_CheckRegBankForClass, /*MI*/0, /*Op*/0, /*RC*/GIMT_Encode2(AMDGPU::VReg_128RegClassID),
        // MIs[0] cbsz
        GIM_CheckIsImm, /*MI*/0, /*Op*/5,
        // MIs[0] abid
        GIM_CheckIsImm, /*MI*/0, /*Op*/6,
        // MIs[0] blgp
        GIM_CheckIsImm, /*MI*/0, /*Op*/7,
        GIM_CheckCxxInsnPredicate, /*MI*/0, /*FnId*/GIMT_Encode2(GICXXPred_MI_Predicate_anonymous_24792),
        // (intrinsic_wo_chain:{ *:[v4i32] } 2572:{ *:[iPTR] }, i32:{ *:[i32] }:$src0, i32:{ *:[i32] }:$src1, v4i32:{ *:[v4i32] }:$src2, (timm:{ *:[i32] }):$cbsz, (timm:{ *:[i32] }):$abid, (timm:{ *:[i32] }):$blgp)<<P:Predicate_anonymous_24792>>  =>  (V_MFMA_I32_16X16X16I8_vgprcd_e64:{ *:[v4i32] } i32:{ *:[i32] }:$src0, i32:{ *:[i32] }:$src1, v4i32:{ *:[v4i32] }:$src2, (timm:{ *:[i32] }):$cbsz, (timm:{ *:[i32] }):$abid, (timm:{ *:[i32] }):$blgp)
        GIR_BuildMI, /*InsnID*/0, /*Opcode*/GIMT_Encode2(AMDGPU::V_MFMA_I32_16X16X16I8_vgprcd_e64),
        GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/0, // DstI[vdst]
        GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/2, // src0
        GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/3, // src1
        GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/4, // src2
        GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/5, // cbsz
        GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/6, // abid
        GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/7, // blgp
        GIR_ConstrainSelectedInstOperands, /*InsnID*/0,
        GIR_EraseFromParent, /*InsnID*/0,
        // GIR_Coverage, 1019,
        GIR_Done,
      // Label 3556: @232122
      GIM_Try, /*On fail goto*//*Label 3557*/ GIMT_Encode4(232206), // Rule ID 1020 //
        GIM_CheckFeatures, GIMT_Encode2(GIFBS_isGFX908orGFX90A),
        GIM_CheckIntrinsicID, /*MI*/0, /*Op*/1, GIMT_Encode2(Intrinsic::amdgcn_mfma_i32_32x32x8i8),
        GIM_CheckType, /*MI*/0, /*Op*/0, /*Type*/GILLT_v16s32,
        GIM_CheckType, /*MI*/0, /*Op*/2, /*Type*/GILLT_s32,
        GIM_CheckType, /*MI*/0, /*Op*/3, /*Type*/GILLT_s32,
        GIM_CheckType, /*MI*/0, /*Op*/4, /*Type*/GILLT_v16s32,
        GIM_CheckRegBankForClass, /*MI*/0, /*Op*/0, /*RC*/GIMT_Encode2(AMDGPU::AReg_512RegClassID),
        // MIs[0] cbsz
        GIM_CheckIsImm, /*MI*/0, /*Op*/5,
        // MIs[0] abid
        GIM_CheckIsImm, /*MI*/0, /*Op*/6,
        // MIs[0] blgp
        GIM_CheckIsImm, /*MI*/0, /*Op*/7,
        GIM_CheckCxxInsnPredicate, /*MI*/0, /*FnId*/GIMT_Encode2(GICXXPred_MI_Predicate_anonymous_24794),
        // (intrinsic_wo_chain:{ *:[v16i32] } 2577:{ *:[iPTR] }, i32:{ *:[i32] }:$src0, i32:{ *:[i32] }:$src1, v16i32:{ *:[v16i32] }:$src2, (timm:{ *:[i32] }):$cbsz, (timm:{ *:[i32] }):$abid, (timm:{ *:[i32] }):$blgp)<<P:Predicate_anonymous_24794>>  =>  (V_MFMA_I32_32X32X8I8_mac_e64:{ *:[v16i32] } i32:{ *:[i32] }:$src0, i32:{ *:[i32] }:$src1, v16i32:{ *:[v16i32] }:$src2, (timm:{ *:[i32] }):$cbsz, (timm:{ *:[i32] }):$abid, (timm:{ *:[i32] }):$blgp)
        GIR_BuildMI, /*InsnID*/0, /*Opcode*/GIMT_Encode2(AMDGPU::V_MFMA_I32_32X32X8I8_mac_e64),
        GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/0, // DstI[vdst]
        GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/2, // src0
        GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/3, // src1
        GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/4, // src2
        GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/5, // cbsz
        GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/6, // abid
        GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/7, // blgp
        GIR_ConstrainSelectedInstOperands, /*InsnID*/0,
        GIR_EraseFromParent, /*InsnID*/0,
        // GIR_Coverage, 1020,
        GIR_Done,
      // Label 3557: @232206
      GIM_Try, /*On fail goto*//*Label 3558*/ GIMT_Encode4(232290), // Rule ID 1021 //
        GIM_CheckFeatures, GIMT_Encode2(GIFBS_isGFX908orGFX90A),
        GIM_CheckIntrinsicID, /*MI*/0, /*Op*/1, GIMT_Encode2(Intrinsic::amdgcn_mfma_i32_32x32x8i8),
        GIM_CheckType, /*MI*/0, /*Op*/0, /*Type*/GILLT_v16s32,
        GIM_CheckType, /*MI*/0, /*Op*/2, /*Type*/GILLT_s32,
        GIM_CheckType, /*MI*/0, /*Op*/3, /*Type*/GILLT_s32,
        GIM_CheckType, /*MI*/0, /*Op*/4, /*Type*/GILLT_v16s32,
        GIM_CheckRegBankForClass, /*MI*/0, /*Op*/0, /*RC*/GIMT_Encode2(AMDGPU::VReg_512RegClassID),
        // MIs[0] cbsz
        GIM_CheckIsImm, /*MI*/0, /*Op*/5,
        // MIs[0] abid
        GIM_CheckIsImm, /*MI*/0, /*Op*/6,
        // MIs[0] blgp
        GIM_CheckIsImm, /*MI*/0, /*Op*/7,
        GIM_CheckCxxInsnPredicate, /*MI*/0, /*FnId*/GIMT_Encode2(GICXXPred_MI_Predicate_anonymous_24796),
        // (intrinsic_wo_chain:{ *:[v16i32] } 2577:{ *:[iPTR] }, i32:{ *:[i32] }:$src0, i32:{ *:[i32] }:$src1, v16i32:{ *:[v16i32] }:$src2, (timm:{ *:[i32] }):$cbsz, (timm:{ *:[i32] }):$abid, (timm:{ *:[i32] }):$blgp)<<P:Predicate_anonymous_24796>>  =>  (V_MFMA_I32_32X32X8I8_mac_vgprcd_e64:{ *:[v16i32] } i32:{ *:[i32] }:$src0, i32:{ *:[i32] }:$src1, v16i32:{ *:[v16i32] }:$src2, (timm:{ *:[i32] }):$cbsz, (timm:{ *:[i32] }):$abid, (timm:{ *:[i32] }):$blgp)
        GIR_BuildMI, /*InsnID*/0, /*Opcode*/GIMT_Encode2(AMDGPU::V_MFMA_I32_32X32X8I8_mac_vgprcd_e64),
        GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/0, // DstI[vdst]
        GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/2, // src0
        GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/3, // src1
        GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/4, // src2
        GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/5, // cbsz
        GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/6, // abid
        GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/7, // blgp
        GIR_ConstrainSelectedInstOperands, /*InsnID*/0,
        GIR_EraseFromParent, /*InsnID*/0,
        // GIR_Coverage, 1021,
        GIR_Done,
      // Label 3558: @232290
      GIM_Try, /*On fail goto*//*Label 3559*/ GIMT_Encode4(232374), // Rule ID 1022 //
        GIM_CheckFeatures, GIMT_Encode2(GIFBS_isGFX908orGFX90A),
        GIM_CheckIntrinsicID, /*MI*/0, /*Op*/1, GIMT_Encode2(Intrinsic::amdgcn_mfma_f32_4x4x2bf16),
        GIM_CheckType, /*MI*/0, /*Op*/0, /*Type*/GILLT_v4s32,
        GIM_CheckType, /*MI*/0, /*Op*/2, /*Type*/GILLT_v2s16,
        GIM_CheckType, /*MI*/0, /*Op*/3, /*Type*/GILLT_v2s16,
        GIM_CheckType, /*MI*/0, /*Op*/4, /*Type*/GILLT_v4s32,
        GIM_CheckRegBankForClass, /*MI*/0, /*Op*/0, /*RC*/GIMT_Encode2(AMDGPU::AReg_128RegClassID),
        // MIs[0] cbsz
        GIM_CheckIsImm, /*MI*/0, /*Op*/5,
        // MIs[0] abid
        GIM_CheckIsImm, /*MI*/0, /*Op*/6,
        // MIs[0] blgp
        GIM_CheckIsImm, /*MI*/0, /*Op*/7,
        GIM_CheckCxxInsnPredicate, /*MI*/0, /*FnId*/GIMT_Encode2(GICXXPred_MI_Predicate_anonymous_24798),
        // (intrinsic_wo_chain:{ *:[v4f32] } 2567:{ *:[iPTR] }, v2i16:{ *:[v2i16] }:$src0, v2i16:{ *:[v2i16] }:$src1, v4f32:{ *:[v4f32] }:$src2, (timm:{ *:[i32] }):$cbsz, (timm:{ *:[i32] }):$abid, (timm:{ *:[i32] }):$blgp)<<P:Predicate_anonymous_24798>>  =>  (V_MFMA_F32_4X4X2BF16_e64:{ *:[v4f32] } v2i16:{ *:[v2i16] }:$src0, v2i16:{ *:[v2i16] }:$src1, v4f32:{ *:[v4f32] }:$src2, (timm:{ *:[i32] }):$cbsz, (timm:{ *:[i32] }):$abid, (timm:{ *:[i32] }):$blgp)
        GIR_BuildMI, /*InsnID*/0, /*Opcode*/GIMT_Encode2(AMDGPU::V_MFMA_F32_4X4X2BF16_e64),
        GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/0, // DstI[vdst]
        GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/2, // src0
        GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/3, // src1
        GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/4, // src2
        GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/5, // cbsz
        GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/6, // abid
        GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/7, // blgp
        GIR_ConstrainSelectedInstOperands, /*InsnID*/0,
        GIR_EraseFromParent, /*InsnID*/0,
        // GIR_Coverage, 1022,
        GIR_Done,
      // Label 3559: @232374
      GIM_Try, /*On fail goto*//*Label 3560*/ GIMT_Encode4(232458), // Rule ID 1023 //
        GIM_CheckFeatures, GIMT_Encode2(GIFBS_isGFX908orGFX90A),
        GIM_CheckIntrinsicID, /*MI*/0, /*Op*/1, GIMT_Encode2(Intrinsic::amdgcn_mfma_f32_4x4x2bf16),
        GIM_CheckType, /*MI*/0, /*Op*/0, /*Type*/GILLT_v4s32,
        GIM_CheckType, /*MI*/0, /*Op*/2, /*Type*/GILLT_v2s16,
        GIM_CheckType, /*MI*/0, /*Op*/3, /*Type*/GILLT_v2s16,
        GIM_CheckType, /*MI*/0, /*Op*/4, /*Type*/GILLT_v4s32,
        GIM_CheckRegBankForClass, /*MI*/0, /*Op*/0, /*RC*/GIMT_Encode2(AMDGPU::VReg_128RegClassID),
        // MIs[0] cbsz
        GIM_CheckIsImm, /*MI*/0, /*Op*/5,
        // MIs[0] abid
        GIM_CheckIsImm, /*MI*/0, /*Op*/6,
        // MIs[0] blgp
        GIM_CheckIsImm, /*MI*/0, /*Op*/7,
        GIM_CheckCxxInsnPredicate, /*MI*/0, /*FnId*/GIMT_Encode2(GICXXPred_MI_Predicate_anonymous_24800),
        // (intrinsic_wo_chain:{ *:[v4f32] } 2567:{ *:[iPTR] }, v2i16:{ *:[v2i16] }:$src0, v2i16:{ *:[v2i16] }:$src1, v4f32:{ *:[v4f32] }:$src2, (timm:{ *:[i32] }):$cbsz, (timm:{ *:[i32] }):$abid, (timm:{ *:[i32] }):$blgp)<<P:Predicate_anonymous_24800>>  =>  (V_MFMA_F32_4X4X2BF16_vgprcd_e64:{ *:[v4f32] } v2i16:{ *:[v2i16] }:$src0, v2i16:{ *:[v2i16] }:$src1, v4f32:{ *:[v4f32] }:$src2, (timm:{ *:[i32] }):$cbsz, (timm:{ *:[i32] }):$abid, (timm:{ *:[i32] }):$blgp)
        GIR_BuildMI, /*InsnID*/0, /*Opcode*/GIMT_Encode2(AMDGPU::V_MFMA_F32_4X4X2BF16_vgprcd_e64),
        GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/0, // DstI[vdst]
        GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/2, // src0
        GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/3, // src1
        GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/4, // src2
        GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/5, // cbsz
        GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/6, // abid
        GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/7, // blgp
        GIR_ConstrainSelectedInstOperands, /*InsnID*/0,
        GIR_EraseFromParent, /*InsnID*/0,
        // GIR_Coverage, 1023,
        GIR_Done,
      // Label 3560: @232458
      GIM_Try, /*On fail goto*//*Label 3561*/ GIMT_Encode4(232542), // Rule ID 1024 //
        GIM_CheckFeatures, GIMT_Encode2(GIFBS_isGFX908orGFX90A),
        GIM_CheckIntrinsicID, /*MI*/0, /*Op*/1, GIMT_Encode2(Intrinsic::amdgcn_mfma_f32_16x16x2bf16),
        GIM_CheckType, /*MI*/0, /*Op*/0, /*Type*/GILLT_v16s32,
        GIM_CheckType, /*MI*/0, /*Op*/2, /*Type*/GILLT_v2s16,
        GIM_CheckType, /*MI*/0, /*Op*/3, /*Type*/GILLT_v2s16,
        GIM_CheckType, /*MI*/0, /*Op*/4, /*Type*/GILLT_v16s32,
        GIM_CheckRegBankForClass, /*MI*/0, /*Op*/0, /*RC*/GIMT_Encode2(AMDGPU::AReg_512RegClassID),
        // MIs[0] cbsz
        GIM_CheckIsImm, /*MI*/0, /*Op*/5,
        // MIs[0] abid
        GIM_CheckIsImm, /*MI*/0, /*Op*/6,
        // MIs[0] blgp
        GIM_CheckIsImm, /*MI*/0, /*Op*/7,
        GIM_CheckCxxInsnPredicate, /*MI*/0, /*FnId*/GIMT_Encode2(GICXXPred_MI_Predicate_anonymous_24804),
        // (intrinsic_wo_chain:{ *:[v16f32] } 2543:{ *:[iPTR] }, v2i16:{ *:[v2i16] }:$src0, v2i16:{ *:[v2i16] }:$src1, v16f32:{ *:[v16f32] }:$src2, (timm:{ *:[i32] }):$cbsz, (timm:{ *:[i32] }):$abid, (timm:{ *:[i32] }):$blgp)<<P:Predicate_anonymous_24804>>  =>  (V_MFMA_F32_16X16X2BF16_mac_e64:{ *:[v16f32] } v2i16:{ *:[v2i16] }:$src0, v2i16:{ *:[v2i16] }:$src1, v16f32:{ *:[v16f32] }:$src2, (timm:{ *:[i32] }):$cbsz, (timm:{ *:[i32] }):$abid, (timm:{ *:[i32] }):$blgp)
        GIR_BuildMI, /*InsnID*/0, /*Opcode*/GIMT_Encode2(AMDGPU::V_MFMA_F32_16X16X2BF16_mac_e64),
        GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/0, // DstI[vdst]
        GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/2, // src0
        GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/3, // src1
        GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/4, // src2
        GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/5, // cbsz
        GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/6, // abid
        GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/7, // blgp
        GIR_ConstrainSelectedInstOperands, /*InsnID*/0,
        GIR_EraseFromParent, /*InsnID*/0,
        // GIR_Coverage, 1024,
        GIR_Done,
      // Label 3561: @232542
      GIM_Try, /*On fail goto*//*Label 3562*/ GIMT_Encode4(232626), // Rule ID 1025 //
        GIM_CheckFeatures, GIMT_Encode2(GIFBS_isGFX908orGFX90A),
        GIM_CheckIntrinsicID, /*MI*/0, /*Op*/1, GIMT_Encode2(Intrinsic::amdgcn_mfma_f32_16x16x2bf16),
        GIM_CheckType, /*MI*/0, /*Op*/0, /*Type*/GILLT_v16s32,
        GIM_CheckType, /*MI*/0, /*Op*/2, /*Type*/GILLT_v2s16,
        GIM_CheckType, /*MI*/0, /*Op*/3, /*Type*/GILLT_v2s16,
        GIM_CheckType, /*MI*/0, /*Op*/4, /*Type*/GILLT_v16s32,
        GIM_CheckRegBankForClass, /*MI*/0, /*Op*/0, /*RC*/GIMT_Encode2(AMDGPU::VReg_512RegClassID),
        // MIs[0] cbsz
        GIM_CheckIsImm, /*MI*/0, /*Op*/5,
        // MIs[0] abid
        GIM_CheckIsImm, /*MI*/0, /*Op*/6,
        // MIs[0] blgp
        GIM_CheckIsImm, /*MI*/0, /*Op*/7,
        GIM_CheckCxxInsnPredicate, /*MI*/0, /*FnId*/GIMT_Encode2(GICXXPred_MI_Predicate_anonymous_24806),
        // (intrinsic_wo_chain:{ *:[v16f32] } 2543:{ *:[iPTR] }, v2i16:{ *:[v2i16] }:$src0, v2i16:{ *:[v2i16] }:$src1, v16f32:{ *:[v16f32] }:$src2, (timm:{ *:[i32] }):$cbsz, (timm:{ *:[i32] }):$abid, (timm:{ *:[i32] }):$blgp)<<P:Predicate_anonymous_24806>>  =>  (V_MFMA_F32_16X16X2BF16_mac_vgprcd_e64:{ *:[v16f32] } v2i16:{ *:[v2i16] }:$src0, v2i16:{ *:[v2i16] }:$src1, v16f32:{ *:[v16f32] }:$src2, (timm:{ *:[i32] }):$cbsz, (timm:{ *:[i32] }):$abid, (timm:{ *:[i32] }):$blgp)
        GIR_BuildMI, /*InsnID*/0, /*Opcode*/GIMT_Encode2(AMDGPU::V_MFMA_F32_16X16X2BF16_mac_vgprcd_e64),
        GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/0, // DstI[vdst]
        GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/2, // src0
        GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/3, // src1
        GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/4, // src2
        GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/5, // cbsz
        GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/6, // abid
        GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/7, // blgp
        GIR_ConstrainSelectedInstOperands, /*InsnID*/0,
        GIR_EraseFromParent, /*InsnID*/0,
        // GIR_Coverage, 1025,
        GIR_Done,
      // Label 3562: @232626
      GIM_Try, /*On fail goto*//*Label 3563*/ GIMT_Encode4(232710), // Rule ID 1026 //
        GIM_CheckFeatures, GIMT_Encode2(GIFBS_isGFX908orGFX90A),
        GIM_CheckIntrinsicID, /*MI*/0, /*Op*/1, GIMT_Encode2(Intrinsic::amdgcn_mfma_f32_16x16x8bf16),
        GIM_CheckType, /*MI*/0, /*Op*/0, /*Type*/GILLT_v4s32,
        GIM_CheckType, /*MI*/0, /*Op*/2, /*Type*/GILLT_v2s16,
        GIM_CheckType, /*MI*/0, /*Op*/3, /*Type*/GILLT_v2s16,
        GIM_CheckType, /*MI*/0, /*Op*/4, /*Type*/GILLT_v4s32,
        GIM_CheckRegBankForClass, /*MI*/0, /*Op*/0, /*RC*/GIMT_Encode2(AMDGPU::AReg_128RegClassID),
        // MIs[0] cbsz
        GIM_CheckIsImm, /*MI*/0, /*Op*/5,
        // MIs[0] abid
        GIM_CheckIsImm, /*MI*/0, /*Op*/6,
        // MIs[0] blgp
        GIM_CheckIsImm, /*MI*/0, /*Op*/7,
        GIM_CheckCxxInsnPredicate, /*MI*/0, /*FnId*/GIMT_Encode2(GICXXPred_MI_Predicate_anonymous_24808),
        // (intrinsic_wo_chain:{ *:[v4f32] } 2552:{ *:[iPTR] }, v2i16:{ *:[v2i16] }:$src0, v2i16:{ *:[v2i16] }:$src1, v4f32:{ *:[v4f32] }:$src2, (timm:{ *:[i32] }):$cbsz, (timm:{ *:[i32] }):$abid, (timm:{ *:[i32] }):$blgp)<<P:Predicate_anonymous_24808>>  =>  (V_MFMA_F32_16X16X8BF16_e64:{ *:[v4f32] } v2i16:{ *:[v2i16] }:$src0, v2i16:{ *:[v2i16] }:$src1, v4f32:{ *:[v4f32] }:$src2, (timm:{ *:[i32] }):$cbsz, (timm:{ *:[i32] }):$abid, (timm:{ *:[i32] }):$blgp)
        GIR_BuildMI, /*InsnID*/0, /*Opcode*/GIMT_Encode2(AMDGPU::V_MFMA_F32_16X16X8BF16_e64),
        GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/0, // DstI[vdst]
        GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/2, // src0
        GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/3, // src1
        GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/4, // src2
        GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/5, // cbsz
        GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/6, // abid
        GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/7, // blgp
        GIR_ConstrainSelectedInstOperands, /*InsnID*/0,
        GIR_EraseFromParent, /*InsnID*/0,
        // GIR_Coverage, 1026,
        GIR_Done,
      // Label 3563: @232710
      GIM_Try, /*On fail goto*//*Label 3564*/ GIMT_Encode4(232794), // Rule ID 1027 //
        GIM_CheckFeatures, GIMT_Encode2(GIFBS_isGFX908orGFX90A),
        GIM_CheckIntrinsicID, /*MI*/0, /*Op*/1, GIMT_Encode2(Intrinsic::amdgcn_mfma_f32_16x16x8bf16),
        GIM_CheckType, /*MI*/0, /*Op*/0, /*Type*/GILLT_v4s32,
        GIM_CheckType, /*MI*/0, /*Op*/2, /*Type*/GILLT_v2s16,
        GIM_CheckType, /*MI*/0, /*Op*/3, /*Type*/GILLT_v2s16,
        GIM_CheckType, /*MI*/0, /*Op*/4, /*Type*/GILLT_v4s32,
        GIM_CheckRegBankForClass, /*MI*/0, /*Op*/0, /*RC*/GIMT_Encode2(AMDGPU::VReg_128RegClassID),
        // MIs[0] cbsz
        GIM_CheckIsImm, /*MI*/0, /*Op*/5,
        // MIs[0] abid
        GIM_CheckIsImm, /*MI*/0, /*Op*/6,
        // MIs[0] blgp
        GIM_CheckIsImm, /*MI*/0, /*Op*/7,
        GIM_CheckCxxInsnPredicate, /*MI*/0, /*FnId*/GIMT_Encode2(GICXXPred_MI_Predicate_anonymous_24810),
        // (intrinsic_wo_chain:{ *:[v4f32] } 2552:{ *:[iPTR] }, v2i16:{ *:[v2i16] }:$src0, v2i16:{ *:[v2i16] }:$src1, v4f32:{ *:[v4f32] }:$src2, (timm:{ *:[i32] }):$cbsz, (timm:{ *:[i32] }):$abid, (timm:{ *:[i32] }):$blgp)<<P:Predicate_anonymous_24810>>  =>  (V_MFMA_F32_16X16X8BF16_vgprcd_e64:{ *:[v4f32] } v2i16:{ *:[v2i16] }:$src0, v2i16:{ *:[v2i16] }:$src1, v4f32:{ *:[v4f32] }:$src2, (timm:{ *:[i32] }):$cbsz, (timm:{ *:[i32] }):$abid, (timm:{ *:[i32] }):$blgp)
        GIR_BuildMI, /*InsnID*/0, /*Opcode*/GIMT_Encode2(AMDGPU::V_MFMA_F32_16X16X8BF16_vgprcd_e64),
        GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/0, // DstI[vdst]
        GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/2, // src0
        GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/3, // src1
        GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/4, // src2
        GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/5, // cbsz
        GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/6, // abid
        GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/7, // blgp
        GIR_ConstrainSelectedInstOperands, /*InsnID*/0,
        GIR_EraseFromParent, /*InsnID*/0,
        // GIR_Coverage, 1027,
        GIR_Done,
      // Label 3564: @232794
      GIM_Try, /*On fail goto*//*Label 3565*/ GIMT_Encode4(232878), // Rule ID 1028 //
        GIM_CheckFeatures, GIMT_Encode2(GIFBS_isGFX908orGFX90A),
        GIM_CheckIntrinsicID, /*MI*/0, /*Op*/1, GIMT_Encode2(Intrinsic::amdgcn_mfma_f32_32x32x2bf16),
        GIM_CheckType, /*MI*/0, /*Op*/0, /*Type*/GILLT_v32s32,
        GIM_CheckType, /*MI*/0, /*Op*/2, /*Type*/GILLT_v2s16,
        GIM_CheckType, /*MI*/0, /*Op*/3, /*Type*/GILLT_v2s16,
        GIM_CheckType, /*MI*/0, /*Op*/4, /*Type*/GILLT_v32s32,
        GIM_CheckRegBankForClass, /*MI*/0, /*Op*/0, /*RC*/GIMT_Encode2(AMDGPU::AReg_1024RegClassID),
        // MIs[0] cbsz
        GIM_CheckIsImm, /*MI*/0, /*Op*/5,
        // MIs[0] abid
        GIM_CheckIsImm, /*MI*/0, /*Op*/6,
        // MIs[0] blgp
        GIM_CheckIsImm, /*MI*/0, /*Op*/7,
        GIM_CheckCxxInsnPredicate, /*MI*/0, /*FnId*/GIMT_Encode2(GICXXPred_MI_Predicate_anonymous_24814),
        // (intrinsic_wo_chain:{ *:[v32f32] } 2558:{ *:[iPTR] }, v2i16:{ *:[v2i16] }:$src0, v2i16:{ *:[v2i16] }:$src1, v32f32:{ *:[v32f32] }:$src2, (timm:{ *:[i32] }):$cbsz, (timm:{ *:[i32] }):$abid, (timm:{ *:[i32] }):$blgp)<<P:Predicate_anonymous_24814>>  =>  (V_MFMA_F32_32X32X2BF16_mac_e64:{ *:[v32f32] } v2i16:{ *:[v2i16] }:$src0, v2i16:{ *:[v2i16] }:$src1, v32f32:{ *:[v32f32] }:$src2, (timm:{ *:[i32] }):$cbsz, (timm:{ *:[i32] }):$abid, (timm:{ *:[i32] }):$blgp)
        GIR_BuildMI, /*InsnID*/0, /*Opcode*/GIMT_Encode2(AMDGPU::V_MFMA_F32_32X32X2BF16_mac_e64),
        GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/0, // DstI[vdst]
        GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/2, // src0
        GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/3, // src1
        GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/4, // src2
        GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/5, // cbsz
        GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/6, // abid
        GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/7, // blgp
        GIR_ConstrainSelectedInstOperands, /*InsnID*/0,
        GIR_EraseFromParent, /*InsnID*/0,
        // GIR_Coverage, 1028,
        GIR_Done,
      // Label 3565: @232878
      GIM_Try, /*On fail goto*//*Label 3566*/ GIMT_Encode4(232962), // Rule ID 1029 //
        GIM_CheckFeatures, GIMT_Encode2(GIFBS_isGFX908orGFX90A),
        GIM_CheckIntrinsicID, /*MI*/0, /*Op*/1, GIMT_Encode2(Intrinsic::amdgcn_mfma_f32_32x32x2bf16),
        GIM_CheckType, /*MI*/0, /*Op*/0, /*Type*/GILLT_v32s32,
        GIM_CheckType, /*MI*/0, /*Op*/2, /*Type*/GILLT_v2s16,
        GIM_CheckType, /*MI*/0, /*Op*/3, /*Type*/GILLT_v2s16,
        GIM_CheckType, /*MI*/0, /*Op*/4, /*Type*/GILLT_v32s32,
        GIM_CheckRegBankForClass, /*MI*/0, /*Op*/0, /*RC*/GIMT_Encode2(AMDGPU::VReg_1024RegClassID),
        // MIs[0] cbsz
        GIM_CheckIsImm, /*MI*/0, /*Op*/5,
        // MIs[0] abid
        GIM_CheckIsImm, /*MI*/0, /*Op*/6,
        // MIs[0] blgp
        GIM_CheckIsImm, /*MI*/0, /*Op*/7,
        GIM_CheckCxxInsnPredicate, /*MI*/0, /*FnId*/GIMT_Encode2(GICXXPred_MI_Predicate_anonymous_24816),
        // (intrinsic_wo_chain:{ *:[v32f32] } 2558:{ *:[iPTR] }, v2i16:{ *:[v2i16] }:$src0, v2i16:{ *:[v2i16] }:$src1, v32f32:{ *:[v32f32] }:$src2, (timm:{ *:[i32] }):$cbsz, (timm:{ *:[i32] }):$abid, (timm:{ *:[i32] }):$blgp)<<P:Predicate_anonymous_24816>>  =>  (V_MFMA_F32_32X32X2BF16_mac_vgprcd_e64:{ *:[v32f32] } v2i16:{ *:[v2i16] }:$src0, v2i16:{ *:[v2i16] }:$src1, v32f32:{ *:[v32f32] }:$src2, (timm:{ *:[i32] }):$cbsz, (timm:{ *:[i32] }):$abid, (timm:{ *:[i32] }):$blgp)
        GIR_BuildMI, /*InsnID*/0, /*Opcode*/GIMT_Encode2(AMDGPU::V_MFMA_F32_32X32X2BF16_mac_vgprcd_e64),
        GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/0, // DstI[vdst]
        GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/2, // src0
        GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/3, // src1
        GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/4, // src2
        GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/5, // cbsz
        GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/6, // abid
        GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/7, // blgp
        GIR_ConstrainSelectedInstOperands, /*InsnID*/0,
        GIR_EraseFromParent, /*InsnID*/0,
        // GIR_Coverage, 1029,
        GIR_Done,
      // Label 3566: @232962
      GIM_Try, /*On fail goto*//*Label 3567*/ GIMT_Encode4(233046), // Rule ID 1030 //
        GIM_CheckFeatures, GIMT_Encode2(GIFBS_isGFX908orGFX90A),
        GIM_CheckIntrinsicID, /*MI*/0, /*Op*/1, GIMT_Encode2(Intrinsic::amdgcn_mfma_f32_32x32x4bf16),
        GIM_CheckType, /*MI*/0, /*Op*/0, /*Type*/GILLT_v16s32,
        GIM_CheckType, /*MI*/0, /*Op*/2, /*Type*/GILLT_v2s16,
        GIM_CheckType, /*MI*/0, /*Op*/3, /*Type*/GILLT_v2s16,
        GIM_CheckType, /*MI*/0, /*Op*/4, /*Type*/GILLT_v16s32,
        GIM_CheckRegBankForClass, /*MI*/0, /*Op*/0, /*RC*/GIMT_Encode2(AMDGPU::AReg_512RegClassID),
        // MIs[0] cbsz
        GIM_CheckIsImm, /*MI*/0, /*Op*/5,
        // MIs[0] abid
        GIM_CheckIsImm, /*MI*/0, /*Op*/6,
        // MIs[0] blgp
        GIM_CheckIsImm, /*MI*/0, /*Op*/7,
        GIM_CheckCxxInsnPredicate, /*MI*/0, /*FnId*/GIMT_Encode2(GICXXPred_MI_Predicate_anonymous_24818),
        // (intrinsic_wo_chain:{ *:[v16f32] } 2561:{ *:[iPTR] }, v2i16:{ *:[v2i16] }:$src0, v2i16:{ *:[v2i16] }:$src1, v16f32:{ *:[v16f32] }:$src2, (timm:{ *:[i32] }):$cbsz, (timm:{ *:[i32] }):$abid, (timm:{ *:[i32] }):$blgp)<<P:Predicate_anonymous_24818>>  =>  (V_MFMA_F32_32X32X4BF16_mac_e64:{ *:[v16f32] } v2i16:{ *:[v2i16] }:$src0, v2i16:{ *:[v2i16] }:$src1, v16f32:{ *:[v16f32] }:$src2, (timm:{ *:[i32] }):$cbsz, (timm:{ *:[i32] }):$abid, (timm:{ *:[i32] }):$blgp)
        GIR_BuildMI, /*InsnID*/0, /*Opcode*/GIMT_Encode2(AMDGPU::V_MFMA_F32_32X32X4BF16_mac_e64),
        GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/0, // DstI[vdst]
        GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/2, // src0
        GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/3, // src1
        GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/4, // src2
        GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/5, // cbsz
        GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/6, // abid
        GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/7, // blgp
        GIR_ConstrainSelectedInstOperands, /*InsnID*/0,
        GIR_EraseFromParent, /*InsnID*/0,
        // GIR_Coverage, 1030,
        GIR_Done,
      // Label 3567: @233046
      GIM_Try, /*On fail goto*//*Label 3568*/ GIMT_Encode4(233130), // Rule ID 1031 //
        GIM_CheckFeatures, GIMT_Encode2(GIFBS_isGFX908orGFX90A),
        GIM_CheckIntrinsicID, /*MI*/0, /*Op*/1, GIMT_Encode2(Intrinsic::amdgcn_mfma_f32_32x32x4bf16),
        GIM_CheckType, /*MI*/0, /*Op*/0, /*Type*/GILLT_v16s32,
        GIM_CheckType, /*MI*/0, /*Op*/2, /*Type*/GILLT_v2s16,
        GIM_CheckType, /*MI*/0, /*Op*/3, /*Type*/GILLT_v2s16,
        GIM_CheckType, /*MI*/0, /*Op*/4, /*Type*/GILLT_v16s32,
        GIM_CheckRegBankForClass, /*MI*/0, /*Op*/0, /*RC*/GIMT_Encode2(AMDGPU::VReg_512RegClassID),
        // MIs[0] cbsz
        GIM_CheckIsImm, /*MI*/0, /*Op*/5,
        // MIs[0] abid
        GIM_CheckIsImm, /*MI*/0, /*Op*/6,
        // MIs[0] blgp
        GIM_CheckIsImm, /*MI*/0, /*Op*/7,
        GIM_CheckCxxInsnPredicate, /*MI*/0, /*FnId*/GIMT_Encode2(GICXXPred_MI_Predicate_anonymous_24820),
        // (intrinsic_wo_chain:{ *:[v16f32] } 2561:{ *:[iPTR] }, v2i16:{ *:[v2i16] }:$src0, v2i16:{ *:[v2i16] }:$src1, v16f32:{ *:[v16f32] }:$src2, (timm:{ *:[i32] }):$cbsz, (timm:{ *:[i32] }):$abid, (timm:{ *:[i32] }):$blgp)<<P:Predicate_anonymous_24820>>  =>  (V_MFMA_F32_32X32X4BF16_mac_vgprcd_e64:{ *:[v16f32] } v2i16:{ *:[v2i16] }:$src0, v2i16:{ *:[v2i16] }:$src1, v16f32:{ *:[v16f32] }:$src2, (timm:{ *:[i32] }):$cbsz, (timm:{ *:[i32] }):$abid, (timm:{ *:[i32] }):$blgp)
        GIR_BuildMI, /*InsnID*/0, /*Opcode*/GIMT_Encode2(AMDGPU::V_MFMA_F32_32X32X4BF16_mac_vgprcd_e64),
        GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/0, // DstI[vdst]
        GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/2, // src0
        GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/3, // src1
        GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/4, // src2
        GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/5, // cbsz
        GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/6, // abid
        GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/7, // blgp
        GIR_ConstrainSelectedInstOperands, /*InsnID*/0,
        GIR_EraseFromParent, /*InsnID*/0,
        // GIR_Coverage, 1031,
        GIR_Done,
      // Label 3568: @233130
      GIM_Try, /*On fail goto*//*Label 3569*/ GIMT_Encode4(233214), // Rule ID 1032 //
        GIM_CheckFeatures, GIMT_Encode2(GIFBS_isGFX90APlus),
        GIM_CheckIntrinsicID, /*MI*/0, /*Op*/1, GIMT_Encode2(Intrinsic::amdgcn_mfma_f32_32x32x4bf16_1k),
        GIM_CheckType, /*MI*/0, /*Op*/0, /*Type*/GILLT_v32s32,
        GIM_CheckType, /*MI*/0, /*Op*/2, /*Type*/GILLT_v4s16,
        GIM_CheckType, /*MI*/0, /*Op*/3, /*Type*/GILLT_v4s16,
        GIM_CheckType, /*MI*/0, /*Op*/4, /*Type*/GILLT_v32s32,
        GIM_CheckRegBankForClass, /*MI*/0, /*Op*/0, /*RC*/GIMT_Encode2(AMDGPU::AReg_1024RegClassID),
        // MIs[0] cbsz
        GIM_CheckIsImm, /*MI*/0, /*Op*/5,
        // MIs[0] abid
        GIM_CheckIsImm, /*MI*/0, /*Op*/6,
        // MIs[0] blgp
        GIM_CheckIsImm, /*MI*/0, /*Op*/7,
        GIM_CheckCxxInsnPredicate, /*MI*/0, /*FnId*/GIMT_Encode2(GICXXPred_MI_Predicate_anonymous_24824),
        // (intrinsic_wo_chain:{ *:[v32f32] } 2562:{ *:[iPTR] }, v4i16:{ *:[v4i16] }:$src0, v4i16:{ *:[v4i16] }:$src1, v32f32:{ *:[v32f32] }:$src2, (timm:{ *:[i32] }):$cbsz, (timm:{ *:[i32] }):$abid, (timm:{ *:[i32] }):$blgp)<<P:Predicate_anonymous_24824>>  =>  (V_MFMA_F32_32X32X4BF16_1K_mac_e64:{ *:[v32f32] } v4i16:{ *:[v4i16] }:$src0, v4i16:{ *:[v4i16] }:$src1, v32f32:{ *:[v32f32] }:$src2, (timm:{ *:[i32] }):$cbsz, (timm:{ *:[i32] }):$abid, (timm:{ *:[i32] }):$blgp)
        GIR_BuildMI, /*InsnID*/0, /*Opcode*/GIMT_Encode2(AMDGPU::V_MFMA_F32_32X32X4BF16_1K_mac_e64),
        GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/0, // DstI[vdst]
        GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/2, // src0
        GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/3, // src1
        GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/4, // src2
        GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/5, // cbsz
        GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/6, // abid
        GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/7, // blgp
        GIR_ConstrainSelectedInstOperands, /*InsnID*/0,
        GIR_EraseFromParent, /*InsnID*/0,
        // GIR_Coverage, 1032,
        GIR_Done,
      // Label 3569: @233214
      GIM_Try, /*On fail goto*//*Label 3570*/ GIMT_Encode4(233298), // Rule ID 1033 //
        GIM_CheckFeatures, GIMT_Encode2(GIFBS_isGFX90APlus),
        GIM_CheckIntrinsicID, /*MI*/0, /*Op*/1, GIMT_Encode2(Intrinsic::amdgcn_mfma_f32_32x32x4bf16_1k),
        GIM_CheckType, /*MI*/0, /*Op*/0, /*Type*/GILLT_v32s32,
        GIM_CheckType, /*MI*/0, /*Op*/2, /*Type*/GILLT_v4s16,
        GIM_CheckType, /*MI*/0, /*Op*/3, /*Type*/GILLT_v4s16,
        GIM_CheckType, /*MI*/0, /*Op*/4, /*Type*/GILLT_v32s32,
        GIM_CheckRegBankForClass, /*MI*/0, /*Op*/0, /*RC*/GIMT_Encode2(AMDGPU::VReg_1024RegClassID),
        // MIs[0] cbsz
        GIM_CheckIsImm, /*MI*/0, /*Op*/5,
        // MIs[0] abid
        GIM_CheckIsImm, /*MI*/0, /*Op*/6,
        // MIs[0] blgp
        GIM_CheckIsImm, /*MI*/0, /*Op*/7,
        GIM_CheckCxxInsnPredicate, /*MI*/0, /*FnId*/GIMT_Encode2(GICXXPred_MI_Predicate_anonymous_24826),
        // (intrinsic_wo_chain:{ *:[v32f32] } 2562:{ *:[iPTR] }, v4i16:{ *:[v4i16] }:$src0, v4i16:{ *:[v4i16] }:$src1, v32f32:{ *:[v32f32] }:$src2, (timm:{ *:[i32] }):$cbsz, (timm:{ *:[i32] }):$abid, (timm:{ *:[i32] }):$blgp)<<P:Predicate_anonymous_24826>>  =>  (V_MFMA_F32_32X32X4BF16_1K_mac_vgprcd_e64:{ *:[v32f32] } v4i16:{ *:[v4i16] }:$src0, v4i16:{ *:[v4i16] }:$src1, v32f32:{ *:[v32f32] }:$src2, (timm:{ *:[i32] }):$cbsz, (timm:{ *:[i32] }):$abid, (timm:{ *:[i32] }):$blgp)
        GIR_BuildMI, /*InsnID*/0, /*Opcode*/GIMT_Encode2(AMDGPU::V_MFMA_F32_32X32X4BF16_1K_mac_vgprcd_e64),
        GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/0, // DstI[vdst]
        GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/2, // src0
        GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/3, // src1
        GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/4, // src2
        GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/5, // cbsz
        GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/6, // abid
        GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/7, // blgp
        GIR_ConstrainSelectedInstOperands, /*InsnID*/0,
        GIR_EraseFromParent, /*InsnID*/0,
        // GIR_Coverage, 1033,
        GIR_Done,
      // Label 3570: @233298
      GIM_Try, /*On fail goto*//*Label 3571*/ GIMT_Encode4(233382), // Rule ID 1034 //
        GIM_CheckFeatures, GIMT_Encode2(GIFBS_isGFX90APlus),
        GIM_CheckIntrinsicID, /*MI*/0, /*Op*/1, GIMT_Encode2(Intrinsic::amdgcn_mfma_f32_16x16x4bf16_1k),
        GIM_CheckType, /*MI*/0, /*Op*/0, /*Type*/GILLT_v16s32,
        GIM_CheckType, /*MI*/0, /*Op*/2, /*Type*/GILLT_v4s16,
        GIM_CheckType, /*MI*/0, /*Op*/3, /*Type*/GILLT_v4s16,
        GIM_CheckType, /*MI*/0, /*Op*/4, /*Type*/GILLT_v16s32,
        GIM_CheckRegBankForClass, /*MI*/0, /*Op*/0, /*RC*/GIMT_Encode2(AMDGPU::AReg_512RegClassID),
        // MIs[0] cbsz
        GIM_CheckIsImm, /*MI*/0, /*Op*/5,
        // MIs[0] abid
        GIM_CheckIsImm, /*MI*/0, /*Op*/6,
        // MIs[0] blgp
        GIM_CheckIsImm, /*MI*/0, /*Op*/7,
        GIM_CheckCxxInsnPredicate, /*MI*/0, /*FnId*/GIMT_Encode2(GICXXPred_MI_Predicate_anonymous_24830),
        // (intrinsic_wo_chain:{ *:[v16f32] } 2548:{ *:[iPTR] }, v4i16:{ *:[v4i16] }:$src0, v4i16:{ *:[v4i16] }:$src1, v16f32:{ *:[v16f32] }:$src2, (timm:{ *:[i32] }):$cbsz, (timm:{ *:[i32] }):$abid, (timm:{ *:[i32] }):$blgp)<<P:Predicate_anonymous_24830>>  =>  (V_MFMA_F32_16X16X4BF16_1K_mac_e64:{ *:[v16f32] } v4i16:{ *:[v4i16] }:$src0, v4i16:{ *:[v4i16] }:$src1, v16f32:{ *:[v16f32] }:$src2, (timm:{ *:[i32] }):$cbsz, (timm:{ *:[i32] }):$abid, (timm:{ *:[i32] }):$blgp)
        GIR_BuildMI, /*InsnID*/0, /*Opcode*/GIMT_Encode2(AMDGPU::V_MFMA_F32_16X16X4BF16_1K_mac_e64),
        GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/0, // DstI[vdst]
        GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/2, // src0
        GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/3, // src1
        GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/4, // src2
        GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/5, // cbsz
        GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/6, // abid
        GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/7, // blgp
        GIR_ConstrainSelectedInstOperands, /*InsnID*/0,
        GIR_EraseFromParent, /*InsnID*/0,
        // GIR_Coverage, 1034,
        GIR_Done,
      // Label 3571: @233382
      GIM_Try, /*On fail goto*//*Label 3572*/ GIMT_Encode4(233466), // Rule ID 1035 //
        GIM_CheckFeatures, GIMT_Encode2(GIFBS_isGFX90APlus),
        GIM_CheckIntrinsicID, /*MI*/0, /*Op*/1, GIMT_Encode2(Intrinsic::amdgcn_mfma_f32_16x16x4bf16_1k),
        GIM_CheckType, /*MI*/0, /*Op*/0, /*Type*/GILLT_v16s32,
        GIM_CheckType, /*MI*/0, /*Op*/2, /*Type*/GILLT_v4s16,
        GIM_CheckType, /*MI*/0, /*Op*/3, /*Type*/GILLT_v4s16,
        GIM_CheckType, /*MI*/0, /*Op*/4, /*Type*/GILLT_v16s32,
        GIM_CheckRegBankForClass, /*MI*/0, /*Op*/0, /*RC*/GIMT_Encode2(AMDGPU::VReg_512RegClassID),
        // MIs[0] cbsz
        GIM_CheckIsImm, /*MI*/0, /*Op*/5,
        // MIs[0] abid
        GIM_CheckIsImm, /*MI*/0, /*Op*/6,
        // MIs[0] blgp
        GIM_CheckIsImm, /*MI*/0, /*Op*/7,
        GIM_CheckCxxInsnPredicate, /*MI*/0, /*FnId*/GIMT_Encode2(GICXXPred_MI_Predicate_anonymous_24832),
        // (intrinsic_wo_chain:{ *:[v16f32] } 2548:{ *:[iPTR] }, v4i16:{ *:[v4i16] }:$src0, v4i16:{ *:[v4i16] }:$src1, v16f32:{ *:[v16f32] }:$src2, (timm:{ *:[i32] }):$cbsz, (timm:{ *:[i32] }):$abid, (timm:{ *:[i32] }):$blgp)<<P:Predicate_anonymous_24832>>  =>  (V_MFMA_F32_16X16X4BF16_1K_mac_vgprcd_e64:{ *:[v16f32] } v4i16:{ *:[v4i16] }:$src0, v4i16:{ *:[v4i16] }:$src1, v16f32:{ *:[v16f32] }:$src2, (timm:{ *:[i32] }):$cbsz, (timm:{ *:[i32] }):$abid, (timm:{ *:[i32] }):$blgp)
        GIR_BuildMI, /*InsnID*/0, /*Opcode*/GIMT_Encode2(AMDGPU::V_MFMA_F32_16X16X4BF16_1K_mac_vgprcd_e64),
        GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/0, // DstI[vdst]
        GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/2, // src0
        GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/3, // src1
        GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/4, // src2
        GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/5, // cbsz
        GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/6, // abid
        GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/7, // blgp
        GIR_ConstrainSelectedInstOperands, /*InsnID*/0,
        GIR_EraseFromParent, /*InsnID*/0,
        // GIR_Coverage, 1035,
        GIR_Done,
      // Label 3572: @233466
      GIM_Try, /*On fail goto*//*Label 3573*/ GIMT_Encode4(233550), // Rule ID 1036 //
        GIM_CheckFeatures, GIMT_Encode2(GIFBS_isGFX90APlus),
        GIM_CheckIntrinsicID, /*MI*/0, /*Op*/1, GIMT_Encode2(Intrinsic::amdgcn_mfma_f32_4x4x4bf16_1k),
        GIM_CheckType, /*MI*/0, /*Op*/0, /*Type*/GILLT_v4s32,
        GIM_CheckType, /*MI*/0, /*Op*/2, /*Type*/GILLT_v4s16,
        GIM_CheckType, /*MI*/0, /*Op*/3, /*Type*/GILLT_v4s16,
        GIM_CheckType, /*MI*/0, /*Op*/4, /*Type*/GILLT_v4s32,
        GIM_CheckRegBankForClass, /*MI*/0, /*Op*/0, /*RC*/GIMT_Encode2(AMDGPU::AReg_128RegClassID),
        // MIs[0] cbsz
        GIM_CheckIsImm, /*MI*/0, /*Op*/5,
        // MIs[0] abid
        GIM_CheckIsImm, /*MI*/0, /*Op*/6,
        // MIs[0] blgp
        GIM_CheckIsImm, /*MI*/0, /*Op*/7,
        GIM_CheckCxxInsnPredicate, /*MI*/0, /*FnId*/GIMT_Encode2(GICXXPred_MI_Predicate_anonymous_24834),
        // (intrinsic_wo_chain:{ *:[v4f32] } 2568:{ *:[iPTR] }, v4i16:{ *:[v4i16] }:$src0, v4i16:{ *:[v4i16] }:$src1, v4f32:{ *:[v4f32] }:$src2, (timm:{ *:[i32] }):$cbsz, (timm:{ *:[i32] }):$abid, (timm:{ *:[i32] }):$blgp)<<P:Predicate_anonymous_24834>>  =>  (V_MFMA_F32_4X4X4BF16_1K_e64:{ *:[v4f32] } v4i16:{ *:[v4i16] }:$src0, v4i16:{ *:[v4i16] }:$src1, v4f32:{ *:[v4f32] }:$src2, (timm:{ *:[i32] }):$cbsz, (timm:{ *:[i32] }):$abid, (timm:{ *:[i32] }):$blgp)
        GIR_BuildMI, /*InsnID*/0, /*Opcode*/GIMT_Encode2(AMDGPU::V_MFMA_F32_4X4X4BF16_1K_e64),
        GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/0, // DstI[vdst]
        GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/2, // src0
        GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/3, // src1
        GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/4, // src2
        GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/5, // cbsz
        GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/6, // abid
        GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/7, // blgp
        GIR_ConstrainSelectedInstOperands, /*InsnID*/0,
        GIR_EraseFromParent, /*InsnID*/0,
        // GIR_Coverage, 1036,
        GIR_Done,
      // Label 3573: @233550
      GIM_Try, /*On fail goto*//*Label 3574*/ GIMT_Encode4(233634), // Rule ID 1037 //
        GIM_CheckFeatures, GIMT_Encode2(GIFBS_isGFX90APlus),
        GIM_CheckIntrinsicID, /*MI*/0, /*Op*/1, GIMT_Encode2(Intrinsic::amdgcn_mfma_f32_4x4x4bf16_1k),
        GIM_CheckType, /*MI*/0, /*Op*/0, /*Type*/GILLT_v4s32,
        GIM_CheckType, /*MI*/0, /*Op*/2, /*Type*/GILLT_v4s16,
        GIM_CheckType, /*MI*/0, /*Op*/3, /*Type*/GILLT_v4s16,
        GIM_CheckType, /*MI*/0, /*Op*/4, /*Type*/GILLT_v4s32,
        GIM_CheckRegBankForClass, /*MI*/0, /*Op*/0, /*RC*/GIMT_Encode2(AMDGPU::VReg_128RegClassID),
        // MIs[0] cbsz
        GIM_CheckIsImm, /*MI*/0, /*Op*/5,
        // MIs[0] abid
        GIM_CheckIsImm, /*MI*/0, /*Op*/6,
        // MIs[0] blgp
        GIM_CheckIsImm, /*MI*/0, /*Op*/7,
        GIM_CheckCxxInsnPredicate, /*MI*/0, /*FnId*/GIMT_Encode2(GICXXPred_MI_Predicate_anonymous_24836),
        // (intrinsic_wo_chain:{ *:[v4f32] } 2568:{ *:[iPTR] }, v4i16:{ *:[v4i16] }:$src0, v4i16:{ *:[v4i16] }:$src1, v4f32:{ *:[v4f32] }:$src2, (timm:{ *:[i32] }):$cbsz, (timm:{ *:[i32] }):$abid, (timm:{ *:[i32] }):$blgp)<<P:Predicate_anonymous_24836>>  =>  (V_MFMA_F32_4X4X4BF16_1K_vgprcd_e64:{ *:[v4f32] } v4i16:{ *:[v4i16] }:$src0, v4i16:{ *:[v4i16] }:$src1, v4f32:{ *:[v4f32] }:$src2, (timm:{ *:[i32] }):$cbsz, (timm:{ *:[i32] }):$abid, (timm:{ *:[i32] }):$blgp)
        GIR_BuildMI, /*InsnID*/0, /*Opcode*/GIMT_Encode2(AMDGPU::V_MFMA_F32_4X4X4BF16_1K_vgprcd_e64),
        GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/0, // DstI[vdst]
        GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/2, // src0
        GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/3, // src1
        GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/4, // src2
        GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/5, // cbsz
        GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/6, // abid
        GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/7, // blgp
        GIR_ConstrainSelectedInstOperands, /*InsnID*/0,
        GIR_EraseFromParent, /*InsnID*/0,
        // GIR_Coverage, 1037,
        GIR_Done,
      // Label 3574: @233634
      GIM_Try, /*On fail goto*//*Label 3575*/ GIMT_Encode4(233718), // Rule ID 1038 //
        GIM_CheckFeatures, GIMT_Encode2(GIFBS_isGFX90APlus),
        GIM_CheckIntrinsicID, /*MI*/0, /*Op*/1, GIMT_Encode2(Intrinsic::amdgcn_mfma_f32_32x32x8bf16_1k),
        GIM_CheckType, /*MI*/0, /*Op*/0, /*Type*/GILLT_v16s32,
        GIM_CheckType, /*MI*/0, /*Op*/2, /*Type*/GILLT_v4s16,
        GIM_CheckType, /*MI*/0, /*Op*/3, /*Type*/GILLT_v4s16,
        GIM_CheckType, /*MI*/0, /*Op*/4, /*Type*/GILLT_v16s32,
        GIM_CheckRegBankForClass, /*MI*/0, /*Op*/0, /*RC*/GIMT_Encode2(AMDGPU::AReg_512RegClassID),
        // MIs[0] cbsz
        GIM_CheckIsImm, /*MI*/0, /*Op*/5,
        // MIs[0] abid
        GIM_CheckIsImm, /*MI*/0, /*Op*/6,
        // MIs[0] blgp
        GIM_CheckIsImm, /*MI*/0, /*Op*/7,
        GIM_CheckCxxInsnPredicate, /*MI*/0, /*FnId*/GIMT_Encode2(GICXXPred_MI_Predicate_anonymous_24838),
        // (intrinsic_wo_chain:{ *:[v16f32] } 2564:{ *:[iPTR] }, v4i16:{ *:[v4i16] }:$src0, v4i16:{ *:[v4i16] }:$src1, v16f32:{ *:[v16f32] }:$src2, (timm:{ *:[i32] }):$cbsz, (timm:{ *:[i32] }):$abid, (timm:{ *:[i32] }):$blgp)<<P:Predicate_anonymous_24838>>  =>  (V_MFMA_F32_32X32X8BF16_1K_mac_e64:{ *:[v16f32] } v4i16:{ *:[v4i16] }:$src0, v4i16:{ *:[v4i16] }:$src1, v16f32:{ *:[v16f32] }:$src2, (timm:{ *:[i32] }):$cbsz, (timm:{ *:[i32] }):$abid, (timm:{ *:[i32] }):$blgp)
        GIR_BuildMI, /*InsnID*/0, /*Opcode*/GIMT_Encode2(AMDGPU::V_MFMA_F32_32X32X8BF16_1K_mac_e64),
        GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/0, // DstI[vdst]
        GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/2, // src0
        GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/3, // src1
        GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/4, // src2
        GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/5, // cbsz
        GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/6, // abid
        GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/7, // blgp
        GIR_ConstrainSelectedInstOperands, /*InsnID*/0,
        GIR_EraseFromParent, /*InsnID*/0,
        // GIR_Coverage, 1038,
        GIR_Done,
      // Label 3575: @233718
      GIM_Try, /*On fail goto*//*Label 3576*/ GIMT_Encode4(233802), // Rule ID 1039 //
        GIM_CheckFeatures, GIMT_Encode2(GIFBS_isGFX90APlus),
        GIM_CheckIntrinsicID, /*MI*/0, /*Op*/1, GIMT_Encode2(Intrinsic::amdgcn_mfma_f32_32x32x8bf16_1k),
        GIM_CheckType, /*MI*/0, /*Op*/0, /*Type*/GILLT_v16s32,
        GIM_CheckType, /*MI*/0, /*Op*/2, /*Type*/GILLT_v4s16,
        GIM_CheckType, /*MI*/0, /*Op*/3, /*Type*/GILLT_v4s16,
        GIM_CheckType, /*MI*/0, /*Op*/4, /*Type*/GILLT_v16s32,
        GIM_CheckRegBankForClass, /*MI*/0, /*Op*/0, /*RC*/GIMT_Encode2(AMDGPU::VReg_512RegClassID),
        // MIs[0] cbsz
        GIM_CheckIsImm, /*MI*/0, /*Op*/5,
        // MIs[0] abid
        GIM_CheckIsImm, /*MI*/0, /*Op*/6,
        // MIs[0] blgp
        GIM_CheckIsImm, /*MI*/0, /*Op*/7,
        GIM_CheckCxxInsnPredicate, /*MI*/0, /*FnId*/GIMT_Encode2(GICXXPred_MI_Predicate_anonymous_24840),
        // (intrinsic_wo_chain:{ *:[v16f32] } 2564:{ *:[iPTR] }, v4i16:{ *:[v4i16] }:$src0, v4i16:{ *:[v4i16] }:$src1, v16f32:{ *:[v16f32] }:$src2, (timm:{ *:[i32] }):$cbsz, (timm:{ *:[i32] }):$abid, (timm:{ *:[i32] }):$blgp)<<P:Predicate_anonymous_24840>>  =>  (V_MFMA_F32_32X32X8BF16_1K_mac_vgprcd_e64:{ *:[v16f32] } v4i16:{ *:[v4i16] }:$src0, v4i16:{ *:[v4i16] }:$src1, v16f32:{ *:[v16f32] }:$src2, (timm:{ *:[i32] }):$cbsz, (timm:{ *:[i32] }):$abid, (timm:{ *:[i32] }):$blgp)
        GIR_BuildMI, /*InsnID*/0, /*Opcode*/GIMT_Encode2(AMDGPU::V_MFMA_F32_32X32X8BF16_1K_mac_vgprcd_e64),
        GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/0, // DstI[vdst]
        GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/2, // src0
        GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/3, // src1
        GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/4, // src2
        GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/5, // cbsz
        GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/6, // abid
        GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/7, // blgp
        GIR_ConstrainSelectedInstOperands, /*InsnID*/0,
        GIR_EraseFromParent, /*InsnID*/0,
        // GIR_Coverage, 1039,
        GIR_Done,
      // Label 3576: @233802
      GIM_Try, /*On fail goto*//*Label 3577*/ GIMT_Encode4(233886), // Rule ID 1040 //
        GIM_CheckFeatures, GIMT_Encode2(GIFBS_isGFX90APlus),
        GIM_CheckIntrinsicID, /*MI*/0, /*Op*/1, GIMT_Encode2(Intrinsic::amdgcn_mfma_f32_16x16x16bf16_1k),
        GIM_CheckType, /*MI*/0, /*Op*/0, /*Type*/GILLT_v4s32,
        GIM_CheckType, /*MI*/0, /*Op*/2, /*Type*/GILLT_v4s16,
        GIM_CheckType, /*MI*/0, /*Op*/3, /*Type*/GILLT_v4s16,
        GIM_CheckType, /*MI*/0, /*Op*/4, /*Type*/GILLT_v4s32,
        GIM_CheckRegBankForClass, /*MI*/0, /*Op*/0, /*RC*/GIMT_Encode2(AMDGPU::AReg_128RegClassID),
        // MIs[0] cbsz
        GIM_CheckIsImm, /*MI*/0, /*Op*/5,
        // MIs[0] abid
        GIM_CheckIsImm, /*MI*/0, /*Op*/6,
        // MIs[0] blgp
        GIM_CheckIsImm, /*MI*/0, /*Op*/7,
        GIM_CheckCxxInsnPredicate, /*MI*/0, /*FnId*/GIMT_Encode2(GICXXPred_MI_Predicate_anonymous_24842),
        // (intrinsic_wo_chain:{ *:[v4f32] } 2540:{ *:[iPTR] }, v4i16:{ *:[v4i16] }:$src0, v4i16:{ *:[v4i16] }:$src1, v4f32:{ *:[v4f32] }:$src2, (timm:{ *:[i32] }):$cbsz, (timm:{ *:[i32] }):$abid, (timm:{ *:[i32] }):$blgp)<<P:Predicate_anonymous_24842>>  =>  (V_MFMA_F32_16X16X16BF16_1K_e64:{ *:[v4f32] } v4i16:{ *:[v4i16] }:$src0, v4i16:{ *:[v4i16] }:$src1, v4f32:{ *:[v4f32] }:$src2, (timm:{ *:[i32] }):$cbsz, (timm:{ *:[i32] }):$abid, (timm:{ *:[i32] }):$blgp)
        GIR_BuildMI, /*InsnID*/0, /*Opcode*/GIMT_Encode2(AMDGPU::V_MFMA_F32_16X16X16BF16_1K_e64),
        GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/0, // DstI[vdst]
        GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/2, // src0
        GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/3, // src1
        GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/4, // src2
        GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/5, // cbsz
        GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/6, // abid
        GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/7, // blgp
        GIR_ConstrainSelectedInstOperands, /*InsnID*/0,
        GIR_EraseFromParent, /*InsnID*/0,
        // GIR_Coverage, 1040,
        GIR_Done,
      // Label 3577: @233886
      GIM_Try, /*On fail goto*//*Label 3578*/ GIMT_Encode4(233970), // Rule ID 1041 //
        GIM_CheckFeatures, GIMT_Encode2(GIFBS_isGFX90APlus),
        GIM_CheckIntrinsicID, /*MI*/0, /*Op*/1, GIMT_Encode2(Intrinsic::amdgcn_mfma_f32_16x16x16bf16_1k),
        GIM_CheckType, /*MI*/0, /*Op*/0, /*Type*/GILLT_v4s32,
        GIM_CheckType, /*MI*/0, /*Op*/2, /*Type*/GILLT_v4s16,
        GIM_CheckType, /*MI*/0, /*Op*/3, /*Type*/GILLT_v4s16,
        GIM_CheckType, /*MI*/0, /*Op*/4, /*Type*/GILLT_v4s32,
        GIM_CheckRegBankForClass, /*MI*/0, /*Op*/0, /*RC*/GIMT_Encode2(AMDGPU::VReg_128RegClassID),
        // MIs[0] cbsz
        GIM_CheckIsImm, /*MI*/0, /*Op*/5,
        // MIs[0] abid
        GIM_CheckIsImm, /*MI*/0, /*Op*/6,
        // MIs[0] blgp
        GIM_CheckIsImm, /*MI*/0, /*Op*/7,
        GIM_CheckCxxInsnPredicate, /*MI*/0, /*FnId*/GIMT_Encode2(GICXXPred_MI_Predicate_anonymous_24844),
        // (intrinsic_wo_chain:{ *:[v4f32] } 2540:{ *:[iPTR] }, v4i16:{ *:[v4i16] }:$src0, v4i16:{ *:[v4i16] }:$src1, v4f32:{ *:[v4f32] }:$src2, (timm:{ *:[i32] }):$cbsz, (timm:{ *:[i32] }):$abid, (timm:{ *:[i32] }):$blgp)<<P:Predicate_anonymous_24844>>  =>  (V_MFMA_F32_16X16X16BF16_1K_vgprcd_e64:{ *:[v4f32] } v4i16:{ *:[v4i16] }:$src0, v4i16:{ *:[v4i16] }:$src1, v4f32:{ *:[v4f32] }:$src2, (timm:{ *:[i32] }):$cbsz, (timm:{ *:[i32] }):$abid, (timm:{ *:[i32] }):$blgp)
        GIR_BuildMI, /*InsnID*/0, /*Opcode*/GIMT_Encode2(AMDGPU::V_MFMA_F32_16X16X16BF16_1K_vgprcd_e64),
        GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/0, // DstI[vdst]
        GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/2, // src0
        GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/3, // src1
        GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/4, // src2
        GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/5, // cbsz
        GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/6, // abid
        GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/7, // blgp
        GIR_ConstrainSelectedInstOperands, /*InsnID*/0,
        GIR_EraseFromParent, /*InsnID*/0,
        // GIR_Coverage, 1041,
        GIR_Done,
      // Label 3578: @233970
      GIM_Try, /*On fail goto*//*Label 3579*/ GIMT_Encode4(234054), // Rule ID 1042 //
        GIM_CheckFeatures, GIMT_Encode2(GIFBS_isGFX90APlus),
        GIM_CheckIntrinsicID, /*MI*/0, /*Op*/1, GIMT_Encode2(Intrinsic::amdgcn_mfma_f64_16x16x4f64),
        GIM_CheckType, /*MI*/0, /*Op*/0, /*Type*/GILLT_v4s64,
        GIM_CheckType, /*MI*/0, /*Op*/2, /*Type*/GILLT_s64,
        GIM_CheckType, /*MI*/0, /*Op*/3, /*Type*/GILLT_s64,
        GIM_CheckType, /*MI*/0, /*Op*/4, /*Type*/GILLT_v4s64,
        GIM_CheckRegBankForClass, /*MI*/0, /*Op*/0, /*RC*/GIMT_Encode2(AMDGPU::AReg_256RegClassID),
        // MIs[0] cbsz
        GIM_CheckIsImm, /*MI*/0, /*Op*/5,
        // MIs[0] abid
        GIM_CheckIsImm, /*MI*/0, /*Op*/6,
        // MIs[0] blgp
        GIM_CheckIsImm, /*MI*/0, /*Op*/7,
        GIM_CheckCxxInsnPredicate, /*MI*/0, /*FnId*/GIMT_Encode2(GICXXPred_MI_Predicate_anonymous_24848),
        // (intrinsic_wo_chain:{ *:[v4f64] } 2570:{ *:[iPTR] }, f64:{ *:[f64] }:$src0, f64:{ *:[f64] }:$src1, v4f64:{ *:[v4f64] }:$src2, (timm:{ *:[i32] }):$cbsz, (timm:{ *:[i32] }):$abid, (timm:{ *:[i32] }):$blgp)<<P:Predicate_anonymous_24848>>  =>  (V_MFMA_F64_16X16X4F64_mac_e64:{ *:[v4f64] } f64:{ *:[f64] }:$src0, f64:{ *:[f64] }:$src1, v4f64:{ *:[v4f64] }:$src2, (timm:{ *:[i32] }):$cbsz, (timm:{ *:[i32] }):$abid, (timm:{ *:[i32] }):$blgp)
        GIR_BuildMI, /*InsnID*/0, /*Opcode*/GIMT_Encode2(AMDGPU::V_MFMA_F64_16X16X4F64_mac_e64),
        GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/0, // DstI[vdst]
        GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/2, // src0
        GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/3, // src1
        GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/4, // src2
        GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/5, // cbsz
        GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/6, // abid
        GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/7, // blgp
        GIR_ConstrainSelectedInstOperands, /*InsnID*/0,
        GIR_EraseFromParent, /*InsnID*/0,
        // GIR_Coverage, 1042,
        GIR_Done,
      // Label 3579: @234054
      GIM_Try, /*On fail goto*//*Label 3580*/ GIMT_Encode4(234138), // Rule ID 1043 //
        GIM_CheckFeatures, GIMT_Encode2(GIFBS_isGFX90APlus),
        GIM_CheckIntrinsicID, /*MI*/0, /*Op*/1, GIMT_Encode2(Intrinsic::amdgcn_mfma_f64_16x16x4f64),
        GIM_CheckType, /*MI*/0, /*Op*/0, /*Type*/GILLT_v4s64,
        GIM_CheckType, /*MI*/0, /*Op*/2, /*Type*/GILLT_s64,
        GIM_CheckType, /*MI*/0, /*Op*/3, /*Type*/GILLT_s64,
        GIM_CheckType, /*MI*/0, /*Op*/4, /*Type*/GILLT_v4s64,
        GIM_CheckRegBankForClass, /*MI*/0, /*Op*/0, /*RC*/GIMT_Encode2(AMDGPU::VReg_256RegClassID),
        // MIs[0] cbsz
        GIM_CheckIsImm, /*MI*/0, /*Op*/5,
        // MIs[0] abid
        GIM_CheckIsImm, /*MI*/0, /*Op*/6,
        // MIs[0] blgp
        GIM_CheckIsImm, /*MI*/0, /*Op*/7,
        GIM_CheckCxxInsnPredicate, /*MI*/0, /*FnId*/GIMT_Encode2(GICXXPred_MI_Predicate_anonymous_24850),
        // (intrinsic_wo_chain:{ *:[v4f64] } 2570:{ *:[iPTR] }, f64:{ *:[f64] }:$src0, f64:{ *:[f64] }:$src1, v4f64:{ *:[v4f64] }:$src2, (timm:{ *:[i32] }):$cbsz, (timm:{ *:[i32] }):$abid, (timm:{ *:[i32] }):$blgp)<<P:Predicate_anonymous_24850>>  =>  (V_MFMA_F64_16X16X4F64_mac_vgprcd_e64:{ *:[v4f64] } f64:{ *:[f64] }:$src0, f64:{ *:[f64] }:$src1, v4f64:{ *:[v4f64] }:$src2, (timm:{ *:[i32] }):$cbsz, (timm:{ *:[i32] }):$abid, (timm:{ *:[i32] }):$blgp)
        GIR_BuildMI, /*InsnID*/0, /*Opcode*/GIMT_Encode2(AMDGPU::V_MFMA_F64_16X16X4F64_mac_vgprcd_e64),
        GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/0, // DstI[vdst]
        GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/2, // src0
        GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/3, // src1
        GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/4, // src2
        GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/5, // cbsz
        GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/6, // abid
        GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/7, // blgp
        GIR_ConstrainSelectedInstOperands, /*InsnID*/0,
        GIR_EraseFromParent, /*InsnID*/0,
        // GIR_Coverage, 1043,
        GIR_Done,
      // Label 3580: @234138
      GIM_Try, /*On fail goto*//*Label 3581*/ GIMT_Encode4(234222), // Rule ID 1044 //
        GIM_CheckFeatures, GIMT_Encode2(GIFBS_isGFX90APlus),
        GIM_CheckIntrinsicID, /*MI*/0, /*Op*/1, GIMT_Encode2(Intrinsic::amdgcn_mfma_f64_4x4x4f64),
        GIM_CheckType, /*MI*/0, /*Op*/0, /*Type*/GILLT_s64,
        GIM_CheckType, /*MI*/0, /*Op*/2, /*Type*/GILLT_s64,
        GIM_CheckType, /*MI*/0, /*Op*/3, /*Type*/GILLT_s64,
        GIM_CheckType, /*MI*/0, /*Op*/4, /*Type*/GILLT_s64,
        GIM_CheckRegBankForClass, /*MI*/0, /*Op*/0, /*RC*/GIMT_Encode2(AMDGPU::AReg_64RegClassID),
        // MIs[0] cbsz
        GIM_CheckIsImm, /*MI*/0, /*Op*/5,
        // MIs[0] abid
        GIM_CheckIsImm, /*MI*/0, /*Op*/6,
        // MIs[0] blgp
        GIM_CheckIsImm, /*MI*/0, /*Op*/7,
        GIM_CheckCxxInsnPredicate, /*MI*/0, /*FnId*/GIMT_Encode2(GICXXPred_MI_Predicate_anonymous_24852),
        // (intrinsic_wo_chain:{ *:[f64] } 2571:{ *:[iPTR] }, f64:{ *:[f64] }:$src0, f64:{ *:[f64] }:$src1, f64:{ *:[f64] }:$src2, (timm:{ *:[i32] }):$cbsz, (timm:{ *:[i32] }):$abid, (timm:{ *:[i32] }):$blgp)<<P:Predicate_anonymous_24852>>  =>  (V_MFMA_F64_4X4X4F64_e64:{ *:[f64] } f64:{ *:[f64] }:$src0, f64:{ *:[f64] }:$src1, f64:{ *:[f64] }:$src2, (timm:{ *:[i32] }):$cbsz, (timm:{ *:[i32] }):$abid, (timm:{ *:[i32] }):$blgp)
        GIR_BuildMI, /*InsnID*/0, /*Opcode*/GIMT_Encode2(AMDGPU::V_MFMA_F64_4X4X4F64_e64),
        GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/0, // DstI[vdst]
        GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/2, // src0
        GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/3, // src1
        GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/4, // src2
        GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/5, // cbsz
        GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/6, // abid
        GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/7, // blgp
        GIR_ConstrainSelectedInstOperands, /*InsnID*/0,
        GIR_EraseFromParent, /*InsnID*/0,
        // GIR_Coverage, 1044,
        GIR_Done,
      // Label 3581: @234222
      GIM_Try, /*On fail goto*//*Label 3582*/ GIMT_Encode4(234306), // Rule ID 1045 //
        GIM_CheckFeatures, GIMT_Encode2(GIFBS_isGFX90APlus),
        GIM_CheckIntrinsicID, /*MI*/0, /*Op*/1, GIMT_Encode2(Intrinsic::amdgcn_mfma_f64_4x4x4f64),
        GIM_CheckType, /*MI*/0, /*Op*/0, /*Type*/GILLT_s64,
        GIM_CheckType, /*MI*/0, /*Op*/2, /*Type*/GILLT_s64,
        GIM_CheckType, /*MI*/0, /*Op*/3, /*Type*/GILLT_s64,
        GIM_CheckType, /*MI*/0, /*Op*/4, /*Type*/GILLT_s64,
        GIM_CheckRegBankForClass, /*MI*/0, /*Op*/0, /*RC*/GIMT_Encode2(AMDGPU::VReg_64RegClassID),
        // MIs[0] cbsz
        GIM_CheckIsImm, /*MI*/0, /*Op*/5,
        // MIs[0] abid
        GIM_CheckIsImm, /*MI*/0, /*Op*/6,
        // MIs[0] blgp
        GIM_CheckIsImm, /*MI*/0, /*Op*/7,
        GIM_CheckCxxInsnPredicate, /*MI*/0, /*FnId*/GIMT_Encode2(GICXXPred_MI_Predicate_anonymous_24854),
        // (intrinsic_wo_chain:{ *:[f64] } 2571:{ *:[iPTR] }, f64:{ *:[f64] }:$src0, f64:{ *:[f64] }:$src1, f64:{ *:[f64] }:$src2, (timm:{ *:[i32] }):$cbsz, (timm:{ *:[i32] }):$abid, (timm:{ *:[i32] }):$blgp)<<P:Predicate_anonymous_24854>>  =>  (V_MFMA_F64_4X4X4F64_vgprcd_e64:{ *:[f64] } f64:{ *:[f64] }:$src0, f64:{ *:[f64] }:$src1, f64:{ *:[f64] }:$src2, (timm:{ *:[i32] }):$cbsz, (timm:{ *:[i32] }):$abid, (timm:{ *:[i32] }):$blgp)
        GIR_BuildMI, /*InsnID*/0, /*Opcode*/GIMT_Encode2(AMDGPU::V_MFMA_F64_4X4X4F64_vgprcd_e64),
        GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/0, // DstI[vdst]
        GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/2, // src0
        GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/3, // src1
        GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/4, // src2
        GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/5, // cbsz
        GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/6, // abid
        GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/7, // blgp
        GIR_ConstrainSelectedInstOperands, /*InsnID*/0,
        GIR_EraseFromParent, /*InsnID*/0,
        // GIR_Coverage, 1045,
        GIR_Done,
      // Label 3582: @234306
      GIM_Try, /*On fail goto*//*Label 3583*/ GIMT_Encode4(234390), // Rule ID 1046 //
        GIM_CheckFeatures, GIMT_Encode2(GIFBS_isGFX940Plus),
        GIM_CheckIntrinsicID, /*MI*/0, /*Op*/1, GIMT_Encode2(Intrinsic::amdgcn_mfma_i32_32x32x16_i8),
        GIM_CheckType, /*MI*/0, /*Op*/0, /*Type*/GILLT_v16s32,
        GIM_CheckType, /*MI*/0, /*Op*/2, /*Type*/GILLT_s64,
        GIM_CheckType, /*MI*/0, /*Op*/3, /*Type*/GILLT_s64,
        GIM_CheckType, /*MI*/0, /*Op*/4, /*Type*/GILLT_v16s32,
        GIM_CheckRegBankForClass, /*MI*/0, /*Op*/0, /*RC*/GIMT_Encode2(AMDGPU::AReg_512RegClassID),
        // MIs[0] cbsz
        GIM_CheckIsImm, /*MI*/0, /*Op*/5,
        // MIs[0] abid
        GIM_CheckIsImm, /*MI*/0, /*Op*/6,
        // MIs[0] blgp
        GIM_CheckIsImm, /*MI*/0, /*Op*/7,
        GIM_CheckCxxInsnPredicate, /*MI*/0, /*FnId*/GIMT_Encode2(GICXXPred_MI_Predicate_anonymous_24858),
        // (intrinsic_wo_chain:{ *:[v16i32] } 2575:{ *:[iPTR] }, i64:{ *:[i64] }:$src0, i64:{ *:[i64] }:$src1, v16i32:{ *:[v16i32] }:$src2, (timm:{ *:[i32] }):$cbsz, (timm:{ *:[i32] }):$abid, (timm:{ *:[i32] }):$blgp)<<P:Predicate_anonymous_24858>>  =>  (V_MFMA_I32_32X32X16I8_mac_e64:{ *:[v16i32] } i64:{ *:[i64] }:$src0, i64:{ *:[i64] }:$src1, v16i32:{ *:[v16i32] }:$src2, (timm:{ *:[i32] }):$cbsz, (timm:{ *:[i32] }):$abid, (timm:{ *:[i32] }):$blgp)
        GIR_BuildMI, /*InsnID*/0, /*Opcode*/GIMT_Encode2(AMDGPU::V_MFMA_I32_32X32X16I8_mac_e64),
        GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/0, // DstI[vdst]
        GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/2, // src0
        GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/3, // src1
        GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/4, // src2
        GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/5, // cbsz
        GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/6, // abid
        GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/7, // blgp
        GIR_ConstrainSelectedInstOperands, /*InsnID*/0,
        GIR_EraseFromParent, /*InsnID*/0,
        // GIR_Coverage, 1046,
        GIR_Done,
      // Label 3583: @234390
      GIM_Try, /*On fail goto*//*Label 3584*/ GIMT_Encode4(234474), // Rule ID 1047 //
        GIM_CheckFeatures, GIMT_Encode2(GIFBS_isGFX940Plus),
        GIM_CheckIntrinsicID, /*MI*/0, /*Op*/1, GIMT_Encode2(Intrinsic::amdgcn_mfma_i32_32x32x16_i8),
        GIM_CheckType, /*MI*/0, /*Op*/0, /*Type*/GILLT_v16s32,
        GIM_CheckType, /*MI*/0, /*Op*/2, /*Type*/GILLT_s64,
        GIM_CheckType, /*MI*/0, /*Op*/3, /*Type*/GILLT_s64,
        GIM_CheckType, /*MI*/0, /*Op*/4, /*Type*/GILLT_v16s32,
        GIM_CheckRegBankForClass, /*MI*/0, /*Op*/0, /*RC*/GIMT_Encode2(AMDGPU::VReg_512RegClassID),
        // MIs[0] cbsz
        GIM_CheckIsImm, /*MI*/0, /*Op*/5,
        // MIs[0] abid
        GIM_CheckIsImm, /*MI*/0, /*Op*/6,
        // MIs[0] blgp
        GIM_CheckIsImm, /*MI*/0, /*Op*/7,
        GIM_CheckCxxInsnPredicate, /*MI*/0, /*FnId*/GIMT_Encode2(GICXXPred_MI_Predicate_anonymous_24860),
        // (intrinsic_wo_chain:{ *:[v16i32] } 2575:{ *:[iPTR] }, i64:{ *:[i64] }:$src0, i64:{ *:[i64] }:$src1, v16i32:{ *:[v16i32] }:$src2, (timm:{ *:[i32] }):$cbsz, (timm:{ *:[i32] }):$abid, (timm:{ *:[i32] }):$blgp)<<P:Predicate_anonymous_24860>>  =>  (V_MFMA_I32_32X32X16I8_mac_vgprcd_e64:{ *:[v16i32] } i64:{ *:[i64] }:$src0, i64:{ *:[i64] }:$src1, v16i32:{ *:[v16i32] }:$src2, (timm:{ *:[i32] }):$cbsz, (timm:{ *:[i32] }):$abid, (timm:{ *:[i32] }):$blgp)
        GIR_BuildMI, /*InsnID*/0, /*Opcode*/GIMT_Encode2(AMDGPU::V_MFMA_I32_32X32X16I8_mac_vgprcd_e64),
        GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/0, // DstI[vdst]
        GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/2, // src0
        GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/3, // src1
        GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/4, // src2
        GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/5, // cbsz
        GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/6, // abid
        GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/7, // blgp
        GIR_ConstrainSelectedInstOperands, /*InsnID*/0,
        GIR_EraseFromParent, /*InsnID*/0,
        // GIR_Coverage, 1047,
        GIR_Done,
      // Label 3584: @234474
      GIM_Try, /*On fail goto*//*Label 3585*/ GIMT_Encode4(234558), // Rule ID 1048 //
        GIM_CheckFeatures, GIMT_Encode2(GIFBS_isGFX940Plus),
        GIM_CheckIntrinsicID, /*MI*/0, /*Op*/1, GIMT_Encode2(Intrinsic::amdgcn_mfma_i32_16x16x32_i8),
        GIM_CheckType, /*MI*/0, /*Op*/0, /*Type*/GILLT_v4s32,
        GIM_CheckType, /*MI*/0, /*Op*/2, /*Type*/GILLT_s64,
        GIM_CheckType, /*MI*/0, /*Op*/3, /*Type*/GILLT_s64,
        GIM_CheckType, /*MI*/0, /*Op*/4, /*Type*/GILLT_v4s32,
        GIM_CheckRegBankForClass, /*MI*/0, /*Op*/0, /*RC*/GIMT_Encode2(AMDGPU::AReg_128RegClassID),
        // MIs[0] cbsz
        GIM_CheckIsImm, /*MI*/0, /*Op*/5,
        // MIs[0] abid
        GIM_CheckIsImm, /*MI*/0, /*Op*/6,
        // MIs[0] blgp
        GIM_CheckIsImm, /*MI*/0, /*Op*/7,
        GIM_CheckCxxInsnPredicate, /*MI*/0, /*FnId*/GIMT_Encode2(GICXXPred_MI_Predicate_anonymous_24862),
        // (intrinsic_wo_chain:{ *:[v4i32] } 2573:{ *:[iPTR] }, i64:{ *:[i64] }:$src0, i64:{ *:[i64] }:$src1, v4i32:{ *:[v4i32] }:$src2, (timm:{ *:[i32] }):$cbsz, (timm:{ *:[i32] }):$abid, (timm:{ *:[i32] }):$blgp)<<P:Predicate_anonymous_24862>>  =>  (V_MFMA_I32_16X16X32I8_e64:{ *:[v4i32] } i64:{ *:[i64] }:$src0, i64:{ *:[i64] }:$src1, v4i32:{ *:[v4i32] }:$src2, (timm:{ *:[i32] }):$cbsz, (timm:{ *:[i32] }):$abid, (timm:{ *:[i32] }):$blgp)
        GIR_BuildMI, /*InsnID*/0, /*Opcode*/GIMT_Encode2(AMDGPU::V_MFMA_I32_16X16X32I8_e64),
        GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/0, // DstI[vdst]
        GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/2, // src0
        GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/3, // src1
        GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/4, // src2
        GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/5, // cbsz
        GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/6, // abid
        GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/7, // blgp
        GIR_ConstrainSelectedInstOperands, /*InsnID*/0,
        GIR_EraseFromParent, /*InsnID*/0,
        // GIR_Coverage, 1048,
        GIR_Done,
      // Label 3585: @234558
      GIM_Try, /*On fail goto*//*Label 3586*/ GIMT_Encode4(234642), // Rule ID 1049 //
        GIM_CheckFeatures, GIMT_Encode2(GIFBS_isGFX940Plus),
        GIM_CheckIntrinsicID, /*MI*/0, /*Op*/1, GIMT_Encode2(Intrinsic::amdgcn_mfma_i32_16x16x32_i8),
        GIM_CheckType, /*MI*/0, /*Op*/0, /*Type*/GILLT_v4s32,
        GIM_CheckType, /*MI*/0, /*Op*/2, /*Type*/GILLT_s64,
        GIM_CheckType, /*MI*/0, /*Op*/3, /*Type*/GILLT_s64,
        GIM_CheckType, /*MI*/0, /*Op*/4, /*Type*/GILLT_v4s32,
        GIM_CheckRegBankForClass, /*MI*/0, /*Op*/0, /*RC*/GIMT_Encode2(AMDGPU::VReg_128RegClassID),
        // MIs[0] cbsz
        GIM_CheckIsImm, /*MI*/0, /*Op*/5,
        // MIs[0] abid
        GIM_CheckIsImm, /*MI*/0, /*Op*/6,
        // MIs[0] blgp
        GIM_CheckIsImm, /*MI*/0, /*Op*/7,
        GIM_CheckCxxInsnPredicate, /*MI*/0, /*FnId*/GIMT_Encode2(GICXXPred_MI_Predicate_anonymous_24864),
        // (intrinsic_wo_chain:{ *:[v4i32] } 2573:{ *:[iPTR] }, i64:{ *:[i64] }:$src0, i64:{ *:[i64] }:$src1, v4i32:{ *:[v4i32] }:$src2, (timm:{ *:[i32] }):$cbsz, (timm:{ *:[i32] }):$abid, (timm:{ *:[i32] }):$blgp)<<P:Predicate_anonymous_24864>>  =>  (V_MFMA_I32_16X16X32I8_vgprcd_e64:{ *:[v4i32] } i64:{ *:[i64] }:$src0, i64:{ *:[i64] }:$src1, v4i32:{ *:[v4i32] }:$src2, (timm:{ *:[i32] }):$cbsz, (timm:{ *:[i32] }):$abid, (timm:{ *:[i32] }):$blgp)
        GIR_BuildMI, /*InsnID*/0, /*Opcode*/GIMT_Encode2(AMDGPU::V_MFMA_I32_16X16X32I8_vgprcd_e64),
        GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/0, // DstI[vdst]
        GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/2, // src0
        GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/3, // src1
        GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/4, // src2
        GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/5, // cbsz
        GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/6, // abid
        GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/7, // blgp
        GIR_ConstrainSelectedInstOperands, /*InsnID*/0,
        GIR_EraseFromParent, /*InsnID*/0,
        // GIR_Coverage, 1049,
        GIR_Done,
      // Label 3586: @234642
      GIM_Try, /*On fail goto*//*Label 3587*/ GIMT_Encode4(234726), // Rule ID 1050 //
        GIM_CheckFeatures, GIMT_Encode2(GIFBS_isGFX940Plus),
        GIM_CheckIntrinsicID, /*MI*/0, /*Op*/1, GIMT_Encode2(Intrinsic::amdgcn_mfma_f32_16x16x8_xf32),
        GIM_CheckType, /*MI*/0, /*Op*/0, /*Type*/GILLT_v4s32,
        GIM_CheckType, /*MI*/0, /*Op*/2, /*Type*/GILLT_v2s32,
        GIM_CheckType, /*MI*/0, /*Op*/3, /*Type*/GILLT_v2s32,
        GIM_CheckType, /*MI*/0, /*Op*/4, /*Type*/GILLT_v4s32,
        GIM_CheckRegBankForClass, /*MI*/0, /*Op*/0, /*RC*/GIMT_Encode2(AMDGPU::AReg_128RegClassID),
        // MIs[0] cbsz
        GIM_CheckIsImm, /*MI*/0, /*Op*/5,
        // MIs[0] abid
        GIM_CheckIsImm, /*MI*/0, /*Op*/6,
        // MIs[0] blgp
        GIM_CheckIsImm, /*MI*/0, /*Op*/7,
        GIM_CheckCxxInsnPredicate, /*MI*/0, /*FnId*/GIMT_Encode2(GICXXPred_MI_Predicate_anonymous_24866),
        // (intrinsic_wo_chain:{ *:[v4f32] } 2551:{ *:[iPTR] }, v2f32:{ *:[v2f32] }:$src0, v2f32:{ *:[v2f32] }:$src1, v4f32:{ *:[v4f32] }:$src2, (timm:{ *:[i32] }):$cbsz, (timm:{ *:[i32] }):$abid, (timm:{ *:[i32] }):$blgp)<<P:Predicate_anonymous_24866>>  =>  (V_MFMA_F32_16X16X8XF32_e64:{ *:[v4f32] } v2f32:{ *:[v2f32] }:$src0, v2f32:{ *:[v2f32] }:$src1, v4f32:{ *:[v4f32] }:$src2, (timm:{ *:[i32] }):$cbsz, (timm:{ *:[i32] }):$abid, (timm:{ *:[i32] }):$blgp)
        GIR_BuildMI, /*InsnID*/0, /*Opcode*/GIMT_Encode2(AMDGPU::V_MFMA_F32_16X16X8XF32_e64),
        GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/0, // DstI[vdst]
        GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/2, // src0
        GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/3, // src1
        GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/4, // src2
        GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/5, // cbsz
        GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/6, // abid
        GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/7, // blgp
        GIR_ConstrainSelectedInstOperands, /*InsnID*/0,
        GIR_EraseFromParent, /*InsnID*/0,
        // GIR_Coverage, 1050,
        GIR_Done,
      // Label 3587: @234726
      GIM_Try, /*On fail goto*//*Label 3588*/ GIMT_Encode4(234810), // Rule ID 1051 //
        GIM_CheckFeatures, GIMT_Encode2(GIFBS_isGFX940Plus),
        GIM_CheckIntrinsicID, /*MI*/0, /*Op*/1, GIMT_Encode2(Intrinsic::amdgcn_mfma_f32_16x16x8_xf32),
        GIM_CheckType, /*MI*/0, /*Op*/0, /*Type*/GILLT_v4s32,
        GIM_CheckType, /*MI*/0, /*Op*/2, /*Type*/GILLT_v2s32,
        GIM_CheckType, /*MI*/0, /*Op*/3, /*Type*/GILLT_v2s32,
        GIM_CheckType, /*MI*/0, /*Op*/4, /*Type*/GILLT_v4s32,
        GIM_CheckRegBankForClass, /*MI*/0, /*Op*/0, /*RC*/GIMT_Encode2(AMDGPU::VReg_128RegClassID),
        // MIs[0] cbsz
        GIM_CheckIsImm, /*MI*/0, /*Op*/5,
        // MIs[0] abid
        GIM_CheckIsImm, /*MI*/0, /*Op*/6,
        // MIs[0] blgp
        GIM_CheckIsImm, /*MI*/0, /*Op*/7,
        GIM_CheckCxxInsnPredicate, /*MI*/0, /*FnId*/GIMT_Encode2(GICXXPred_MI_Predicate_anonymous_24868),
        // (intrinsic_wo_chain:{ *:[v4f32] } 2551:{ *:[iPTR] }, v2f32:{ *:[v2f32] }:$src0, v2f32:{ *:[v2f32] }:$src1, v4f32:{ *:[v4f32] }:$src2, (timm:{ *:[i32] }):$cbsz, (timm:{ *:[i32] }):$abid, (timm:{ *:[i32] }):$blgp)<<P:Predicate_anonymous_24868>>  =>  (V_MFMA_F32_16X16X8XF32_vgprcd_e64:{ *:[v4f32] } v2f32:{ *:[v2f32] }:$src0, v2f32:{ *:[v2f32] }:$src1, v4f32:{ *:[v4f32] }:$src2, (timm:{ *:[i32] }):$cbsz, (timm:{ *:[i32] }):$abid, (timm:{ *:[i32] }):$blgp)
        GIR_BuildMI, /*InsnID*/0, /*Opcode*/GIMT_Encode2(AMDGPU::V_MFMA_F32_16X16X8XF32_vgprcd_e64),
        GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/0, // DstI[vdst]
        GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/2, // src0
        GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/3, // src1
        GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/4, // src2
        GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/5, // cbsz
        GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/6, // abid
        GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/7, // blgp
        GIR_ConstrainSelectedInstOperands, /*InsnID*/0,
        GIR_EraseFromParent, /*InsnID*/0,
        // GIR_Coverage, 1051,
        GIR_Done,
      // Label 3588: @234810
      GIM_Try, /*On fail goto*//*Label 3589*/ GIMT_Encode4(234894), // Rule ID 1052 //
        GIM_CheckFeatures, GIMT_Encode2(GIFBS_isGFX940Plus),
        GIM_CheckIntrinsicID, /*MI*/0, /*Op*/1, GIMT_Encode2(Intrinsic::amdgcn_mfma_f32_32x32x4_xf32),
        GIM_CheckType, /*MI*/0, /*Op*/0, /*Type*/GILLT_v16s32,
        GIM_CheckType, /*MI*/0, /*Op*/2, /*Type*/GILLT_v2s32,
        GIM_CheckType, /*MI*/0, /*Op*/3, /*Type*/GILLT_v2s32,
        GIM_CheckType, /*MI*/0, /*Op*/4, /*Type*/GILLT_v16s32,
        GIM_CheckRegBankForClass, /*MI*/0, /*Op*/0, /*RC*/GIMT_Encode2(AMDGPU::AReg_512RegClassID),
        // MIs[0] cbsz
        GIM_CheckIsImm, /*MI*/0, /*Op*/5,
        // MIs[0] abid
        GIM_CheckIsImm, /*MI*/0, /*Op*/6,
        // MIs[0] blgp
        GIM_CheckIsImm, /*MI*/0, /*Op*/7,
        GIM_CheckCxxInsnPredicate, /*MI*/0, /*FnId*/GIMT_Encode2(GICXXPred_MI_Predicate_anonymous_24872),
        // (intrinsic_wo_chain:{ *:[v16f32] } 2560:{ *:[iPTR] }, v2f32:{ *:[v2f32] }:$src0, v2f32:{ *:[v2f32] }:$src1, v16f32:{ *:[v16f32] }:$src2, (timm:{ *:[i32] }):$cbsz, (timm:{ *:[i32] }):$abid, (timm:{ *:[i32] }):$blgp)<<P:Predicate_anonymous_24872>>  =>  (V_MFMA_F32_32X32X4XF32_mac_e64:{ *:[v16f32] } v2f32:{ *:[v2f32] }:$src0, v2f32:{ *:[v2f32] }:$src1, v16f32:{ *:[v16f32] }:$src2, (timm:{ *:[i32] }):$cbsz, (timm:{ *:[i32] }):$abid, (timm:{ *:[i32] }):$blgp)
        GIR_BuildMI, /*InsnID*/0, /*Opcode*/GIMT_Encode2(AMDGPU::V_MFMA_F32_32X32X4XF32_mac_e64),
        GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/0, // DstI[vdst]
        GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/2, // src0
        GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/3, // src1
        GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/4, // src2
        GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/5, // cbsz
        GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/6, // abid
        GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/7, // blgp
        GIR_ConstrainSelectedInstOperands, /*InsnID*/0,
        GIR_EraseFromParent, /*InsnID*/0,
        // GIR_Coverage, 1052,
        GIR_Done,
      // Label 3589: @234894
      GIM_Try, /*On fail goto*//*Label 3590*/ GIMT_Encode4(234978), // Rule ID 1053 //
        GIM_CheckFeatures, GIMT_Encode2(GIFBS_isGFX940Plus),
        GIM_CheckIntrinsicID, /*MI*/0, /*Op*/1, GIMT_Encode2(Intrinsic::amdgcn_mfma_f32_32x32x4_xf32),
        GIM_CheckType, /*MI*/0, /*Op*/0, /*Type*/GILLT_v16s32,
        GIM_CheckType, /*MI*/0, /*Op*/2, /*Type*/GILLT_v2s32,
        GIM_CheckType, /*MI*/0, /*Op*/3, /*Type*/GILLT_v2s32,
        GIM_CheckType, /*MI*/0, /*Op*/4, /*Type*/GILLT_v16s32,
        GIM_CheckRegBankForClass, /*MI*/0, /*Op*/0, /*RC*/GIMT_Encode2(AMDGPU::VReg_512RegClassID),
        // MIs[0] cbsz
        GIM_CheckIsImm, /*MI*/0, /*Op*/5,
        // MIs[0] abid
        GIM_CheckIsImm, /*MI*/0, /*Op*/6,
        // MIs[0] blgp
        GIM_CheckIsImm, /*MI*/0, /*Op*/7,
        GIM_CheckCxxInsnPredicate, /*MI*/0, /*FnId*/GIMT_Encode2(GICXXPred_MI_Predicate_anonymous_24874),
        // (intrinsic_wo_chain:{ *:[v16f32] } 2560:{ *:[iPTR] }, v2f32:{ *:[v2f32] }:$src0, v2f32:{ *:[v2f32] }:$src1, v16f32:{ *:[v16f32] }:$src2, (timm:{ *:[i32] }):$cbsz, (timm:{ *:[i32] }):$abid, (timm:{ *:[i32] }):$blgp)<<P:Predicate_anonymous_24874>>  =>  (V_MFMA_F32_32X32X4XF32_mac_vgprcd_e64:{ *:[v16f32] } v2f32:{ *:[v2f32] }:$src0, v2f32:{ *:[v2f32] }:$src1, v16f32:{ *:[v16f32] }:$src2, (timm:{ *:[i32] }):$cbsz, (timm:{ *:[i32] }):$abid, (timm:{ *:[i32] }):$blgp)
        GIR_BuildMI, /*InsnID*/0, /*Opcode*/GIMT_Encode2(AMDGPU::V_MFMA_F32_32X32X4XF32_mac_vgprcd_e64),
        GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/0, // DstI[vdst]
        GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/2, // src0
        GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/3, // src1
        GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/4, // src2
        GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/5, // cbsz
        GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/6, // abid
        GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/7, // blgp
        GIR_ConstrainSelectedInstOperands, /*InsnID*/0,
        GIR_EraseFromParent, /*InsnID*/0,
        // GIR_Coverage, 1053,
        GIR_Done,
      // Label 3590: @234978
      GIM_Try, /*On fail goto*//*Label 3591*/ GIMT_Encode4(235062), // Rule ID 1054 //
        GIM_CheckFeatures, GIMT_Encode2(GIFBS_isGFX940Plus),
        GIM_CheckIntrinsicID, /*MI*/0, /*Op*/1, GIMT_Encode2(Intrinsic::amdgcn_mfma_f32_16x16x32_bf8_bf8),
        GIM_CheckType, /*MI*/0, /*Op*/0, /*Type*/GILLT_v4s32,
        GIM_CheckType, /*MI*/0, /*Op*/2, /*Type*/GILLT_s64,
        GIM_CheckType, /*MI*/0, /*Op*/3, /*Type*/GILLT_s64,
        GIM_CheckType, /*MI*/0, /*Op*/4, /*Type*/GILLT_v4s32,
        GIM_CheckRegBankForClass, /*MI*/0, /*Op*/0, /*RC*/GIMT_Encode2(AMDGPU::AReg_128RegClassID),
        // MIs[0] cbsz
        GIM_CheckIsImm, /*MI*/0, /*Op*/5,
        // MIs[0] abid
        GIM_CheckIsImm, /*MI*/0, /*Op*/6,
        // MIs[0] blgp
        GIM_CheckIsImm, /*MI*/0, /*Op*/7,
        GIM_CheckCxxInsnPredicate, /*MI*/0, /*FnId*/GIMT_Encode2(GICXXPred_MI_Predicate_anonymous_24876),
        // (intrinsic_wo_chain:{ *:[v4f32] } 2544:{ *:[iPTR] }, i64:{ *:[i64] }:$src0, i64:{ *:[i64] }:$src1, v4f32:{ *:[v4f32] }:$src2, (timm:{ *:[i32] }):$cbsz, (timm:{ *:[i32] }):$abid, (timm:{ *:[i32] }):$blgp)<<P:Predicate_anonymous_24876>>  =>  (V_MFMA_F32_16X16X32_BF8_BF8_e64:{ *:[v4f32] } i64:{ *:[i64] }:$src0, i64:{ *:[i64] }:$src1, v4f32:{ *:[v4f32] }:$src2, (timm:{ *:[i32] }):$cbsz, (timm:{ *:[i32] }):$abid, (timm:{ *:[i32] }):$blgp)
        GIR_BuildMI, /*InsnID*/0, /*Opcode*/GIMT_Encode2(AMDGPU::V_MFMA_F32_16X16X32_BF8_BF8_e64),
        GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/0, // DstI[vdst]
        GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/2, // src0
        GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/3, // src1
        GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/4, // src2
        GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/5, // cbsz
        GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/6, // abid
        GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/7, // blgp
        GIR_ConstrainSelectedInstOperands, /*InsnID*/0,
        GIR_EraseFromParent, /*InsnID*/0,
        // GIR_Coverage, 1054,
        GIR_Done,
      // Label 3591: @235062
      GIM_Try, /*On fail goto*//*Label 3592*/ GIMT_Encode4(235146), // Rule ID 1055 //
        GIM_CheckFeatures, GIMT_Encode2(GIFBS_isGFX940Plus),
        GIM_CheckIntrinsicID, /*MI*/0, /*Op*/1, GIMT_Encode2(Intrinsic::amdgcn_mfma_f32_16x16x32_bf8_bf8),
        GIM_CheckType, /*MI*/0, /*Op*/0, /*Type*/GILLT_v4s32,
        GIM_CheckType, /*MI*/0, /*Op*/2, /*Type*/GILLT_s64,
        GIM_CheckType, /*MI*/0, /*Op*/3, /*Type*/GILLT_s64,
        GIM_CheckType, /*MI*/0, /*Op*/4, /*Type*/GILLT_v4s32,
        GIM_CheckRegBankForClass, /*MI*/0, /*Op*/0, /*RC*/GIMT_Encode2(AMDGPU::VReg_128RegClassID),
        // MIs[0] cbsz
        GIM_CheckIsImm, /*MI*/0, /*Op*/5,
        // MIs[0] abid
        GIM_CheckIsImm, /*MI*/0, /*Op*/6,
        // MIs[0] blgp
        GIM_CheckIsImm, /*MI*/0, /*Op*/7,
        GIM_CheckCxxInsnPredicate, /*MI*/0, /*FnId*/GIMT_Encode2(GICXXPred_MI_Predicate_anonymous_24878),
        // (intrinsic_wo_chain:{ *:[v4f32] } 2544:{ *:[iPTR] }, i64:{ *:[i64] }:$src0, i64:{ *:[i64] }:$src1, v4f32:{ *:[v4f32] }:$src2, (timm:{ *:[i32] }):$cbsz, (timm:{ *:[i32] }):$abid, (timm:{ *:[i32] }):$blgp)<<P:Predicate_anonymous_24878>>  =>  (V_MFMA_F32_16X16X32_BF8_BF8_vgprcd_e64:{ *:[v4f32] } i64:{ *:[i64] }:$src0, i64:{ *:[i64] }:$src1, v4f32:{ *:[v4f32] }:$src2, (timm:{ *:[i32] }):$cbsz, (timm:{ *:[i32] }):$abid, (timm:{ *:[i32] }):$blgp)
        GIR_BuildMI, /*InsnID*/0, /*Opcode*/GIMT_Encode2(AMDGPU::V_MFMA_F32_16X16X32_BF8_BF8_vgprcd_e64),
        GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/0, // DstI[vdst]
        GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/2, // src0
        GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/3, // src1
        GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/4, // src2
        GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/5, // cbsz
        GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/6, // abid
        GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/7, // blgp
        GIR_ConstrainSelectedInstOperands, /*InsnID*/0,
        GIR_EraseFromParent, /*InsnID*/0,
        // GIR_Coverage, 1055,
        GIR_Done,
      // Label 3592: @235146
      GIM_Try, /*On fail goto*//*Label 3593*/ GIMT_Encode4(235230), // Rule ID 1056 //
        GIM_CheckFeatures, GIMT_Encode2(GIFBS_isGFX940Plus),
        GIM_CheckIntrinsicID, /*MI*/0, /*Op*/1, GIMT_Encode2(Intrinsic::amdgcn_mfma_f32_16x16x32_bf8_fp8),
        GIM_CheckType, /*MI*/0, /*Op*/0, /*Type*/GILLT_v4s32,
        GIM_CheckType, /*MI*/0, /*Op*/2, /*Type*/GILLT_s64,
        GIM_CheckType, /*MI*/0, /*Op*/3, /*Type*/GILLT_s64,
        GIM_CheckType, /*MI*/0, /*Op*/4, /*Type*/GILLT_v4s32,
        GIM_CheckRegBankForClass, /*MI*/0, /*Op*/0, /*RC*/GIMT_Encode2(AMDGPU::AReg_128RegClassID),
        // MIs[0] cbsz
        GIM_CheckIsImm, /*MI*/0, /*Op*/5,
        // MIs[0] abid
        GIM_CheckIsImm, /*MI*/0, /*Op*/6,
        // MIs[0] blgp
        GIM_CheckIsImm, /*MI*/0, /*Op*/7,
        GIM_CheckCxxInsnPredicate, /*MI*/0, /*FnId*/GIMT_Encode2(GICXXPred_MI_Predicate_anonymous_24880),
        // (intrinsic_wo_chain:{ *:[v4f32] } 2545:{ *:[iPTR] }, i64:{ *:[i64] }:$src0, i64:{ *:[i64] }:$src1, v4f32:{ *:[v4f32] }:$src2, (timm:{ *:[i32] }):$cbsz, (timm:{ *:[i32] }):$abid, (timm:{ *:[i32] }):$blgp)<<P:Predicate_anonymous_24880>>  =>  (V_MFMA_F32_16X16X32_BF8_FP8_e64:{ *:[v4f32] } i64:{ *:[i64] }:$src0, i64:{ *:[i64] }:$src1, v4f32:{ *:[v4f32] }:$src2, (timm:{ *:[i32] }):$cbsz, (timm:{ *:[i32] }):$abid, (timm:{ *:[i32] }):$blgp)
        GIR_BuildMI, /*InsnID*/0, /*Opcode*/GIMT_Encode2(AMDGPU::V_MFMA_F32_16X16X32_BF8_FP8_e64),
        GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/0, // DstI[vdst]
        GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/2, // src0
        GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/3, // src1
        GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/4, // src2
        GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/5, // cbsz
        GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/6, // abid
        GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/7, // blgp
        GIR_ConstrainSelectedInstOperands, /*InsnID*/0,
        GIR_EraseFromParent, /*InsnID*/0,
        // GIR_Coverage, 1056,
        GIR_Done,
      // Label 3593: @235230
      GIM_Try, /*On fail goto*//*Label 3594*/ GIMT_Encode4(235314), // Rule ID 1057 //
        GIM_CheckFeatures, GIMT_Encode2(GIFBS_isGFX940Plus),
        GIM_CheckIntrinsicID, /*MI*/0, /*Op*/1, GIMT_Encode2(Intrinsic::amdgcn_mfma_f32_16x16x32_bf8_fp8),
        GIM_CheckType, /*MI*/0, /*Op*/0, /*Type*/GILLT_v4s32,
        GIM_CheckType, /*MI*/0, /*Op*/2, /*Type*/GILLT_s64,
        GIM_CheckType, /*MI*/0, /*Op*/3, /*Type*/GILLT_s64,
        GIM_CheckType, /*MI*/0, /*Op*/4, /*Type*/GILLT_v4s32,
        GIM_CheckRegBankForClass, /*MI*/0, /*Op*/0, /*RC*/GIMT_Encode2(AMDGPU::VReg_128RegClassID),
        // MIs[0] cbsz
        GIM_CheckIsImm, /*MI*/0, /*Op*/5,
        // MIs[0] abid
        GIM_CheckIsImm, /*MI*/0, /*Op*/6,
        // MIs[0] blgp
        GIM_CheckIsImm, /*MI*/0, /*Op*/7,
        GIM_CheckCxxInsnPredicate, /*MI*/0, /*FnId*/GIMT_Encode2(GICXXPred_MI_Predicate_anonymous_24882),
        // (intrinsic_wo_chain:{ *:[v4f32] } 2545:{ *:[iPTR] }, i64:{ *:[i64] }:$src0, i64:{ *:[i64] }:$src1, v4f32:{ *:[v4f32] }:$src2, (timm:{ *:[i32] }):$cbsz, (timm:{ *:[i32] }):$abid, (timm:{ *:[i32] }):$blgp)<<P:Predicate_anonymous_24882>>  =>  (V_MFMA_F32_16X16X32_BF8_FP8_vgprcd_e64:{ *:[v4f32] } i64:{ *:[i64] }:$src0, i64:{ *:[i64] }:$src1, v4f32:{ *:[v4f32] }:$src2, (timm:{ *:[i32] }):$cbsz, (timm:{ *:[i32] }):$abid, (timm:{ *:[i32] }):$blgp)
        GIR_BuildMI, /*InsnID*/0, /*Opcode*/GIMT_Encode2(AMDGPU::V_MFMA_F32_16X16X32_BF8_FP8_vgprcd_e64),
        GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/0, // DstI[vdst]
        GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/2, // src0
        GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/3, // src1
        GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/4, // src2
        GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/5, // cbsz
        GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/6, // abid
        GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/7, // blgp
        GIR_ConstrainSelectedInstOperands, /*InsnID*/0,
        GIR_EraseFromParent, /*InsnID*/0,
        // GIR_Coverage, 1057,
        GIR_Done,
      // Label 3594: @235314
      GIM_Try, /*On fail goto*//*Label 3595*/ GIMT_Encode4(235398), // Rule ID 1058 //
        GIM_CheckFeatures, GIMT_Encode2(GIFBS_isGFX940Plus),
        GIM_CheckIntrinsicID, /*MI*/0, /*Op*/1, GIMT_Encode2(Intrinsic::amdgcn_mfma_f32_16x16x32_fp8_bf8),
        GIM_CheckType, /*MI*/0, /*Op*/0, /*Type*/GILLT_v4s32,
        GIM_CheckType, /*MI*/0, /*Op*/2, /*Type*/GILLT_s64,
        GIM_CheckType, /*MI*/0, /*Op*/3, /*Type*/GILLT_s64,
        GIM_CheckType, /*MI*/0, /*Op*/4, /*Type*/GILLT_v4s32,
        GIM_CheckRegBankForClass, /*MI*/0, /*Op*/0, /*RC*/GIMT_Encode2(AMDGPU::AReg_128RegClassID),
        // MIs[0] cbsz
        GIM_CheckIsImm, /*MI*/0, /*Op*/5,
        // MIs[0] abid
        GIM_CheckIsImm, /*MI*/0, /*Op*/6,
        // MIs[0] blgp
        GIM_CheckIsImm, /*MI*/0, /*Op*/7,
        GIM_CheckCxxInsnPredicate, /*MI*/0, /*FnId*/GIMT_Encode2(GICXXPred_MI_Predicate_anonymous_24884),
        // (intrinsic_wo_chain:{ *:[v4f32] } 2546:{ *:[iPTR] }, i64:{ *:[i64] }:$src0, i64:{ *:[i64] }:$src1, v4f32:{ *:[v4f32] }:$src2, (timm:{ *:[i32] }):$cbsz, (timm:{ *:[i32] }):$abid, (timm:{ *:[i32] }):$blgp)<<P:Predicate_anonymous_24884>>  =>  (V_MFMA_F32_16X16X32_FP8_BF8_e64:{ *:[v4f32] } i64:{ *:[i64] }:$src0, i64:{ *:[i64] }:$src1, v4f32:{ *:[v4f32] }:$src2, (timm:{ *:[i32] }):$cbsz, (timm:{ *:[i32] }):$abid, (timm:{ *:[i32] }):$blgp)
        GIR_BuildMI, /*InsnID*/0, /*Opcode*/GIMT_Encode2(AMDGPU::V_MFMA_F32_16X16X32_FP8_BF8_e64),
        GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/0, // DstI[vdst]
        GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/2, // src0
        GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/3, // src1
        GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/4, // src2
        GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/5, // cbsz
        GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/6, // abid
        GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/7, // blgp
        GIR_ConstrainSelectedInstOperands, /*InsnID*/0,
        GIR_EraseFromParent, /*InsnID*/0,
        // GIR_Coverage, 1058,
        GIR_Done,
      // Label 3595: @235398
      GIM_Try, /*On fail goto*//*Label 3596*/ GIMT_Encode4(235482), // Rule ID 1059 //
        GIM_CheckFeatures, GIMT_Encode2(GIFBS_isGFX940Plus),
        GIM_CheckIntrinsicID, /*MI*/0, /*Op*/1, GIMT_Encode2(Intrinsic::amdgcn_mfma_f32_16x16x32_fp8_bf8),
        GIM_CheckType, /*MI*/0, /*Op*/0, /*Type*/GILLT_v4s32,
        GIM_CheckType, /*MI*/0, /*Op*/2, /*Type*/GILLT_s64,
        GIM_CheckType, /*MI*/0, /*Op*/3, /*Type*/GILLT_s64,
        GIM_CheckType, /*MI*/0, /*Op*/4, /*Type*/GILLT_v4s32,
        GIM_CheckRegBankForClass, /*MI*/0, /*Op*/0, /*RC*/GIMT_Encode2(AMDGPU::VReg_128RegClassID),
        // MIs[0] cbsz
        GIM_CheckIsImm, /*MI*/0, /*Op*/5,
        // MIs[0] abid
        GIM_CheckIsImm, /*MI*/0, /*Op*/6,
        // MIs[0] blgp
        GIM_CheckIsImm, /*MI*/0, /*Op*/7,
        GIM_CheckCxxInsnPredicate, /*MI*/0, /*FnId*/GIMT_Encode2(GICXXPred_MI_Predicate_anonymous_24886),
        // (intrinsic_wo_chain:{ *:[v4f32] } 2546:{ *:[iPTR] }, i64:{ *:[i64] }:$src0, i64:{ *:[i64] }:$src1, v4f32:{ *:[v4f32] }:$src2, (timm:{ *:[i32] }):$cbsz, (timm:{ *:[i32] }):$abid, (timm:{ *:[i32] }):$blgp)<<P:Predicate_anonymous_24886>>  =>  (V_MFMA_F32_16X16X32_FP8_BF8_vgprcd_e64:{ *:[v4f32] } i64:{ *:[i64] }:$src0, i64:{ *:[i64] }:$src1, v4f32:{ *:[v4f32] }:$src2, (timm:{ *:[i32] }):$cbsz, (timm:{ *:[i32] }):$abid, (timm:{ *:[i32] }):$blgp)
        GIR_BuildMI, /*InsnID*/0, /*Opcode*/GIMT_Encode2(AMDGPU::V_MFMA_F32_16X16X32_FP8_BF8_vgprcd_e64),
        GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/0, // DstI[vdst]
        GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/2, // src0
        GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/3, // src1
        GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/4, // src2
        GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/5, // cbsz
        GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/6, // abid
        GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/7, // blgp
        GIR_ConstrainSelectedInstOperands, /*InsnID*/0,
        GIR_EraseFromParent, /*InsnID*/0,
        // GIR_Coverage, 1059,
        GIR_Done,
      // Label 3596: @235482
      GIM_Try, /*On fail goto*//*Label 3597*/ GIMT_Encode4(235566), // Rule ID 1060 //
        GIM_CheckFeatures, GIMT_Encode2(GIFBS_isGFX940Plus),
        GIM_CheckIntrinsicID, /*MI*/0, /*Op*/1, GIMT_Encode2(Intrinsic::amdgcn_mfma_f32_16x16x32_fp8_fp8),
        GIM_CheckType, /*MI*/0, /*Op*/0, /*Type*/GILLT_v4s32,
        GIM_CheckType, /*MI*/0, /*Op*/2, /*Type*/GILLT_s64,
        GIM_CheckType, /*MI*/0, /*Op*/3, /*Type*/GILLT_s64,
        GIM_CheckType, /*MI*/0, /*Op*/4, /*Type*/GILLT_v4s32,
        GIM_CheckRegBankForClass, /*MI*/0, /*Op*/0, /*RC*/GIMT_Encode2(AMDGPU::AReg_128RegClassID),
        // MIs[0] cbsz
        GIM_CheckIsImm, /*MI*/0, /*Op*/5,
        // MIs[0] abid
        GIM_CheckIsImm, /*MI*/0, /*Op*/6,
        // MIs[0] blgp
        GIM_CheckIsImm, /*MI*/0, /*Op*/7,
        GIM_CheckCxxInsnPredicate, /*MI*/0, /*FnId*/GIMT_Encode2(GICXXPred_MI_Predicate_anonymous_24888),
        // (intrinsic_wo_chain:{ *:[v4f32] } 2547:{ *:[iPTR] }, i64:{ *:[i64] }:$src0, i64:{ *:[i64] }:$src1, v4f32:{ *:[v4f32] }:$src2, (timm:{ *:[i32] }):$cbsz, (timm:{ *:[i32] }):$abid, (timm:{ *:[i32] }):$blgp)<<P:Predicate_anonymous_24888>>  =>  (V_MFMA_F32_16X16X32_FP8_FP8_e64:{ *:[v4f32] } i64:{ *:[i64] }:$src0, i64:{ *:[i64] }:$src1, v4f32:{ *:[v4f32] }:$src2, (timm:{ *:[i32] }):$cbsz, (timm:{ *:[i32] }):$abid, (timm:{ *:[i32] }):$blgp)
        GIR_BuildMI, /*InsnID*/0, /*Opcode*/GIMT_Encode2(AMDGPU::V_MFMA_F32_16X16X32_FP8_FP8_e64),
        GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/0, // DstI[vdst]
        GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/2, // src0
        GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/3, // src1
        GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/4, // src2
        GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/5, // cbsz
        GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/6, // abid
        GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/7, // blgp
        GIR_ConstrainSelectedInstOperands, /*InsnID*/0,
        GIR_EraseFromParent, /*InsnID*/0,
        // GIR_Coverage, 1060,
        GIR_Done,
      // Label 3597: @235566
      GIM_Try, /*On fail goto*//*Label 3598*/ GIMT_Encode4(235650), // Rule ID 1061 //
        GIM_CheckFeatures, GIMT_Encode2(GIFBS_isGFX940Plus),
        GIM_CheckIntrinsicID, /*MI*/0, /*Op*/1, GIMT_Encode2(Intrinsic::amdgcn_mfma_f32_16x16x32_fp8_fp8),
        GIM_CheckType, /*MI*/0, /*Op*/0, /*Type*/GILLT_v4s32,
        GIM_CheckType, /*MI*/0, /*Op*/2, /*Type*/GILLT_s64,
        GIM_CheckType, /*MI*/0, /*Op*/3, /*Type*/GILLT_s64,
        GIM_CheckType, /*MI*/0, /*Op*/4, /*Type*/GILLT_v4s32,
        GIM_CheckRegBankForClass, /*MI*/0, /*Op*/0, /*RC*/GIMT_Encode2(AMDGPU::VReg_128RegClassID),
        // MIs[0] cbsz
        GIM_CheckIsImm, /*MI*/0, /*Op*/5,
        // MIs[0] abid
        GIM_CheckIsImm, /*MI*/0, /*Op*/6,
        // MIs[0] blgp
        GIM_CheckIsImm, /*MI*/0, /*Op*/7,
        GIM_CheckCxxInsnPredicate, /*MI*/0, /*FnId*/GIMT_Encode2(GICXXPred_MI_Predicate_anonymous_24890),
        // (intrinsic_wo_chain:{ *:[v4f32] } 2547:{ *:[iPTR] }, i64:{ *:[i64] }:$src0, i64:{ *:[i64] }:$src1, v4f32:{ *:[v4f32] }:$src2, (timm:{ *:[i32] }):$cbsz, (timm:{ *:[i32] }):$abid, (timm:{ *:[i32] }):$blgp)<<P:Predicate_anonymous_24890>>  =>  (V_MFMA_F32_16X16X32_FP8_FP8_vgprcd_e64:{ *:[v4f32] } i64:{ *:[i64] }:$src0, i64:{ *:[i64] }:$src1, v4f32:{ *:[v4f32] }:$src2, (timm:{ *:[i32] }):$cbsz, (timm:{ *:[i32] }):$abid, (timm:{ *:[i32] }):$blgp)
        GIR_BuildMI, /*InsnID*/0, /*Opcode*/GIMT_Encode2(AMDGPU::V_MFMA_F32_16X16X32_FP8_FP8_vgprcd_e64),
        GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/0, // DstI[vdst]
        GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/2, // src0
        GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/3, // src1
        GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/4, // src2
        GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/5, // cbsz
        GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/6, // abid
        GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/7, // blgp
        GIR_ConstrainSelectedInstOperands, /*InsnID*/0,
        GIR_EraseFromParent, /*InsnID*/0,
        // GIR_Coverage, 1061,
        GIR_Done,
      // Label 3598: @235650
      GIM_Try, /*On fail goto*//*Label 3599*/ GIMT_Encode4(235734), // Rule ID 1062 //
        GIM_CheckFeatures, GIMT_Encode2(GIFBS_isGFX940Plus),
        GIM_CheckIntrinsicID, /*MI*/0, /*Op*/1, GIMT_Encode2(Intrinsic::amdgcn_mfma_f32_32x32x16_bf8_bf8),
        GIM_CheckType, /*MI*/0, /*Op*/0, /*Type*/GILLT_v16s32,
        GIM_CheckType, /*MI*/0, /*Op*/2, /*Type*/GILLT_s64,
        GIM_CheckType, /*MI*/0, /*Op*/3, /*Type*/GILLT_s64,
        GIM_CheckType, /*MI*/0, /*Op*/4, /*Type*/GILLT_v16s32,
        GIM_CheckRegBankForClass, /*MI*/0, /*Op*/0, /*RC*/GIMT_Encode2(AMDGPU::AReg_512RegClassID),
        // MIs[0] cbsz
        GIM_CheckIsImm, /*MI*/0, /*Op*/5,
        // MIs[0] abid
        GIM_CheckIsImm, /*MI*/0, /*Op*/6,
        // MIs[0] blgp
        GIM_CheckIsImm, /*MI*/0, /*Op*/7,
        GIM_CheckCxxInsnPredicate, /*MI*/0, /*FnId*/GIMT_Encode2(GICXXPred_MI_Predicate_anonymous_24894),
        // (intrinsic_wo_chain:{ *:[v16f32] } 2553:{ *:[iPTR] }, i64:{ *:[i64] }:$src0, i64:{ *:[i64] }:$src1, v16f32:{ *:[v16f32] }:$src2, (timm:{ *:[i32] }):$cbsz, (timm:{ *:[i32] }):$abid, (timm:{ *:[i32] }):$blgp)<<P:Predicate_anonymous_24894>>  =>  (V_MFMA_F32_32X32X16_BF8_BF8_mac_e64:{ *:[v16f32] } i64:{ *:[i64] }:$src0, i64:{ *:[i64] }:$src1, v16f32:{ *:[v16f32] }:$src2, (timm:{ *:[i32] }):$cbsz, (timm:{ *:[i32] }):$abid, (timm:{ *:[i32] }):$blgp)
        GIR_BuildMI, /*InsnID*/0, /*Opcode*/GIMT_Encode2(AMDGPU::V_MFMA_F32_32X32X16_BF8_BF8_mac_e64),
        GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/0, // DstI[vdst]
        GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/2, // src0
        GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/3, // src1
        GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/4, // src2
        GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/5, // cbsz
        GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/6, // abid
        GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/7, // blgp
        GIR_ConstrainSelectedInstOperands, /*InsnID*/0,
        GIR_EraseFromParent, /*InsnID*/0,
        // GIR_Coverage, 1062,
        GIR_Done,
      // Label 3599: @235734
      GIM_Try, /*On fail goto*//*Label 3600*/ GIMT_Encode4(235818), // Rule ID 1063 //
        GIM_CheckFeatures, GIMT_Encode2(GIFBS_isGFX940Plus),
        GIM_CheckIntrinsicID, /*MI*/0, /*Op*/1, GIMT_Encode2(Intrinsic::amdgcn_mfma_f32_32x32x16_bf8_bf8),
        GIM_CheckType, /*MI*/0, /*Op*/0, /*Type*/GILLT_v16s32,
        GIM_CheckType, /*MI*/0, /*Op*/2, /*Type*/GILLT_s64,
        GIM_CheckType, /*MI*/0, /*Op*/3, /*Type*/GILLT_s64,
        GIM_CheckType, /*MI*/0, /*Op*/4, /*Type*/GILLT_v16s32,
        GIM_CheckRegBankForClass, /*MI*/0, /*Op*/0, /*RC*/GIMT_Encode2(AMDGPU::VReg_512RegClassID),
        // MIs[0] cbsz
        GIM_CheckIsImm, /*MI*/0, /*Op*/5,
        // MIs[0] abid
        GIM_CheckIsImm, /*MI*/0, /*Op*/6,
        // MIs[0] blgp
        GIM_CheckIsImm, /*MI*/0, /*Op*/7,
        GIM_CheckCxxInsnPredicate, /*MI*/0, /*FnId*/GIMT_Encode2(GICXXPred_MI_Predicate_anonymous_24896),
        // (intrinsic_wo_chain:{ *:[v16f32] } 2553:{ *:[iPTR] }, i64:{ *:[i64] }:$src0, i64:{ *:[i64] }:$src1, v16f32:{ *:[v16f32] }:$src2, (timm:{ *:[i32] }):$cbsz, (timm:{ *:[i32] }):$abid, (timm:{ *:[i32] }):$blgp)<<P:Predicate_anonymous_24896>>  =>  (V_MFMA_F32_32X32X16_BF8_BF8_mac_vgprcd_e64:{ *:[v16f32] } i64:{ *:[i64] }:$src0, i64:{ *:[i64] }:$src1, v16f32:{ *:[v16f32] }:$src2, (timm:{ *:[i32] }):$cbsz, (timm:{ *:[i32] }):$abid, (timm:{ *:[i32] }):$blgp)
        GIR_BuildMI, /*InsnID*/0, /*Opcode*/GIMT_Encode2(AMDGPU::V_MFMA_F32_32X32X16_BF8_BF8_mac_vgprcd_e64),
        GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/0, // DstI[vdst]
        GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/2, // src0
        GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/3, // src1
        GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/4, // src2
        GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/5, // cbsz
        GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/6, // abid
        GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/7, // blgp
        GIR_ConstrainSelectedInstOperands, /*InsnID*/0,
        GIR_EraseFromParent, /*InsnID*/0,
        // GIR_Coverage, 1063,
        GIR_Done,
      // Label 3600: @235818
      GIM_Try, /*On fail goto*//*Label 3601*/ GIMT_Encode4(235902), // Rule ID 1064 //
        GIM_CheckFeatures, GIMT_Encode2(GIFBS_isGFX940Plus),
        GIM_CheckIntrinsicID, /*MI*/0, /*Op*/1, GIMT_Encode2(Intrinsic::amdgcn_mfma_f32_32x32x16_bf8_fp8),
        GIM_CheckType, /*MI*/0, /*Op*/0, /*Type*/GILLT_v16s32,
        GIM_CheckType, /*MI*/0, /*Op*/2, /*Type*/GILLT_s64,
        GIM_CheckType, /*MI*/0, /*Op*/3, /*Type*/GILLT_s64,
        GIM_CheckType, /*MI*/0, /*Op*/4, /*Type*/GILLT_v16s32,
        GIM_CheckRegBankForClass, /*MI*/0, /*Op*/0, /*RC*/GIMT_Encode2(AMDGPU::AReg_512RegClassID),
        // MIs[0] cbsz
        GIM_CheckIsImm, /*MI*/0, /*Op*/5,
        // MIs[0] abid
        GIM_CheckIsImm, /*MI*/0, /*Op*/6,
        // MIs[0] blgp
        GIM_CheckIsImm, /*MI*/0, /*Op*/7,
        GIM_CheckCxxInsnPredicate, /*MI*/0, /*FnId*/GIMT_Encode2(GICXXPred_MI_Predicate_anonymous_24898),
        // (intrinsic_wo_chain:{ *:[v16f32] } 2554:{ *:[iPTR] }, i64:{ *:[i64] }:$src0, i64:{ *:[i64] }:$src1, v16f32:{ *:[v16f32] }:$src2, (timm:{ *:[i32] }):$cbsz, (timm:{ *:[i32] }):$abid, (timm:{ *:[i32] }):$blgp)<<P:Predicate_anonymous_24898>>  =>  (V_MFMA_F32_32X32X16_BF8_FP8_mac_e64:{ *:[v16f32] } i64:{ *:[i64] }:$src0, i64:{ *:[i64] }:$src1, v16f32:{ *:[v16f32] }:$src2, (timm:{ *:[i32] }):$cbsz, (timm:{ *:[i32] }):$abid, (timm:{ *:[i32] }):$blgp)
        GIR_BuildMI, /*InsnID*/0, /*Opcode*/GIMT_Encode2(AMDGPU::V_MFMA_F32_32X32X16_BF8_FP8_mac_e64),
        GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/0, // DstI[vdst]
        GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/2, // src0
        GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/3, // src1
        GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/4, // src2
        GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/5, // cbsz
        GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/6, // abid
        GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/7, // blgp
        GIR_ConstrainSelectedInstOperands, /*InsnID*/0,
        GIR_EraseFromParent, /*InsnID*/0,
        // GIR_Coverage, 1064,
        GIR_Done,
      // Label 3601: @235902
      GIM_Try, /*On fail goto*//*Label 3602*/ GIMT_Encode4(235986), // Rule ID 1065 //
        GIM_CheckFeatures, GIMT_Encode2(GIFBS_isGFX940Plus),
        GIM_CheckIntrinsicID, /*MI*/0, /*Op*/1, GIMT_Encode2(Intrinsic::amdgcn_mfma_f32_32x32x16_bf8_fp8),
        GIM_CheckType, /*MI*/0, /*Op*/0, /*Type*/GILLT_v16s32,
        GIM_CheckType, /*MI*/0, /*Op*/2, /*Type*/GILLT_s64,
        GIM_CheckType, /*MI*/0, /*Op*/3, /*Type*/GILLT_s64,
        GIM_CheckType, /*MI*/0, /*Op*/4, /*Type*/GILLT_v16s32,
        GIM_CheckRegBankForClass, /*MI*/0, /*Op*/0, /*RC*/GIMT_Encode2(AMDGPU::VReg_512RegClassID),
        // MIs[0] cbsz
        GIM_CheckIsImm, /*MI*/0, /*Op*/5,
        // MIs[0] abid
        GIM_CheckIsImm, /*MI*/0, /*Op*/6,
        // MIs[0] blgp
        GIM_CheckIsImm, /*MI*/0, /*Op*/7,
        GIM_CheckCxxInsnPredicate, /*MI*/0, /*FnId*/GIMT_Encode2(GICXXPred_MI_Predicate_anonymous_24900),
        // (intrinsic_wo_chain:{ *:[v16f32] } 2554:{ *:[iPTR] }, i64:{ *:[i64] }:$src0, i64:{ *:[i64] }:$src1, v16f32:{ *:[v16f32] }:$src2, (timm:{ *:[i32] }):$cbsz, (timm:{ *:[i32] }):$abid, (timm:{ *:[i32] }):$blgp)<<P:Predicate_anonymous_24900>>  =>  (V_MFMA_F32_32X32X16_BF8_FP8_mac_vgprcd_e64:{ *:[v16f32] } i64:{ *:[i64] }:$src0, i64:{ *:[i64] }:$src1, v16f32:{ *:[v16f32] }:$src2, (timm:{ *:[i32] }):$cbsz, (timm:{ *:[i32] }):$abid, (timm:{ *:[i32] }):$blgp)
        GIR_BuildMI, /*InsnID*/0, /*Opcode*/GIMT_Encode2(AMDGPU::V_MFMA_F32_32X32X16_BF8_FP8_mac_vgprcd_e64),
        GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/0, // DstI[vdst]
        GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/2, // src0
        GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/3, // src1
        GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/4, // src2
        GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/5, // cbsz
        GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/6, // abid
        GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/7, // blgp
        GIR_ConstrainSelectedInstOperands, /*InsnID*/0,
        GIR_EraseFromParent, /*InsnID*/0,
        // GIR_Coverage, 1065,
        GIR_Done,
      // Label 3602: @235986
      GIM_Try, /*On fail goto*//*Label 3603*/ GIMT_Encode4(236070), // Rule ID 1066 //
        GIM_CheckFeatures, GIMT_Encode2(GIFBS_isGFX940Plus),
        GIM_CheckIntrinsicID, /*MI*/0, /*Op*/1, GIMT_Encode2(Intrinsic::amdgcn_mfma_f32_32x32x16_fp8_bf8),
        GIM_CheckType, /*MI*/0, /*Op*/0, /*Type*/GILLT_v16s32,
        GIM_CheckType, /*MI*/0, /*Op*/2, /*Type*/GILLT_s64,
        GIM_CheckType, /*MI*/0, /*Op*/3, /*Type*/GILLT_s64,
        GIM_CheckType, /*MI*/0, /*Op*/4, /*Type*/GILLT_v16s32,
        GIM_CheckRegBankForClass, /*MI*/0, /*Op*/0, /*RC*/GIMT_Encode2(AMDGPU::AReg_512RegClassID),
        // MIs[0] cbsz
        GIM_CheckIsImm, /*MI*/0, /*Op*/5,
        // MIs[0] abid
        GIM_CheckIsImm, /*MI*/0, /*Op*/6,
        // MIs[0] blgp
        GIM_CheckIsImm, /*MI*/0, /*Op*/7,
        GIM_CheckCxxInsnPredicate, /*MI*/0, /*FnId*/GIMT_Encode2(GICXXPred_MI_Predicate_anonymous_24902),
        // (intrinsic_wo_chain:{ *:[v16f32] } 2555:{ *:[iPTR] }, i64:{ *:[i64] }:$src0, i64:{ *:[i64] }:$src1, v16f32:{ *:[v16f32] }:$src2, (timm:{ *:[i32] }):$cbsz, (timm:{ *:[i32] }):$abid, (timm:{ *:[i32] }):$blgp)<<P:Predicate_anonymous_24902>>  =>  (V_MFMA_F32_32X32X16_FP8_BF8_mac_e64:{ *:[v16f32] } i64:{ *:[i64] }:$src0, i64:{ *:[i64] }:$src1, v16f32:{ *:[v16f32] }:$src2, (timm:{ *:[i32] }):$cbsz, (timm:{ *:[i32] }):$abid, (timm:{ *:[i32] }):$blgp)
        GIR_BuildMI, /*InsnID*/0, /*Opcode*/GIMT_Encode2(AMDGPU::V_MFMA_F32_32X32X16_FP8_BF8_mac_e64),
        GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/0, // DstI[vdst]
        GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/2, // src0
        GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/3, // src1
        GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/4, // src2
        GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/5, // cbsz
        GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/6, // abid
        GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/7, // blgp
        GIR_ConstrainSelectedInstOperands, /*InsnID*/0,
        GIR_EraseFromParent, /*InsnID*/0,
        // GIR_Coverage, 1066,
        GIR_Done,
      // Label 3603: @236070
      GIM_Try, /*On fail goto*//*Label 3604*/ GIMT_Encode4(236154), // Rule ID 1067 //
        GIM_CheckFeatures, GIMT_Encode2(GIFBS_isGFX940Plus),
        GIM_CheckIntrinsicID, /*MI*/0, /*Op*/1, GIMT_Encode2(Intrinsic::amdgcn_mfma_f32_32x32x16_fp8_bf8),
        GIM_CheckType, /*MI*/0, /*Op*/0, /*Type*/GILLT_v16s32,
        GIM_CheckType, /*MI*/0, /*Op*/2, /*Type*/GILLT_s64,
        GIM_CheckType, /*MI*/0, /*Op*/3, /*Type*/GILLT_s64,
        GIM_CheckType, /*MI*/0, /*Op*/4, /*Type*/GILLT_v16s32,
        GIM_CheckRegBankForClass, /*MI*/0, /*Op*/0, /*RC*/GIMT_Encode2(AMDGPU::VReg_512RegClassID),
        // MIs[0] cbsz
        GIM_CheckIsImm, /*MI*/0, /*Op*/5,
        // MIs[0] abid
        GIM_CheckIsImm, /*MI*/0, /*Op*/6,
        // MIs[0] blgp
        GIM_CheckIsImm, /*MI*/0, /*Op*/7,
        GIM_CheckCxxInsnPredicate, /*MI*/0, /*FnId*/GIMT_Encode2(GICXXPred_MI_Predicate_anonymous_24904),
        // (intrinsic_wo_chain:{ *:[v16f32] } 2555:{ *:[iPTR] }, i64:{ *:[i64] }:$src0, i64:{ *:[i64] }:$src1, v16f32:{ *:[v16f32] }:$src2, (timm:{ *:[i32] }):$cbsz, (timm:{ *:[i32] }):$abid, (timm:{ *:[i32] }):$blgp)<<P:Predicate_anonymous_24904>>  =>  (V_MFMA_F32_32X32X16_FP8_BF8_mac_vgprcd_e64:{ *:[v16f32] } i64:{ *:[i64] }:$src0, i64:{ *:[i64] }:$src1, v16f32:{ *:[v16f32] }:$src2, (timm:{ *:[i32] }):$cbsz, (timm:{ *:[i32] }):$abid, (timm:{ *:[i32] }):$blgp)
        GIR_BuildMI, /*InsnID*/0, /*Opcode*/GIMT_Encode2(AMDGPU::V_MFMA_F32_32X32X16_FP8_BF8_mac_vgprcd_e64),
        GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/0, // DstI[vdst]
        GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/2, // src0
        GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/3, // src1
        GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/4, // src2
        GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/5, // cbsz
        GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/6, // abid
        GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/7, // blgp
        GIR_ConstrainSelectedInstOperands, /*InsnID*/0,
        GIR_EraseFromParent, /*InsnID*/0,
        // GIR_Coverage, 1067,
        GIR_Done,
      // Label 3604: @236154
      GIM_Try, /*On fail goto*//*Label 3605*/ GIMT_Encode4(236238), // Rule ID 1068 //
        GIM_CheckFeatures, GIMT_Encode2(GIFBS_isGFX940Plus),
        GIM_CheckIntrinsicID, /*MI*/0, /*Op*/1, GIMT_Encode2(Intrinsic::amdgcn_mfma_f32_32x32x16_fp8_fp8),
        GIM_CheckType, /*MI*/0, /*Op*/0, /*Type*/GILLT_v16s32,
        GIM_CheckType, /*MI*/0, /*Op*/2, /*Type*/GILLT_s64,
        GIM_CheckType, /*MI*/0, /*Op*/3, /*Type*/GILLT_s64,
        GIM_CheckType, /*MI*/0, /*Op*/4, /*Type*/GILLT_v16s32,
        GIM_CheckRegBankForClass, /*MI*/0, /*Op*/0, /*RC*/GIMT_Encode2(AMDGPU::AReg_512RegClassID),
        // MIs[0] cbsz
        GIM_CheckIsImm, /*MI*/0, /*Op*/5,
        // MIs[0] abid
        GIM_CheckIsImm, /*MI*/0, /*Op*/6,
        // MIs[0] blgp
        GIM_CheckIsImm, /*MI*/0, /*Op*/7,
        GIM_CheckCxxInsnPredicate, /*MI*/0, /*FnId*/GIMT_Encode2(GICXXPred_MI_Predicate_anonymous_24906),
        // (intrinsic_wo_chain:{ *:[v16f32] } 2556:{ *:[iPTR] }, i64:{ *:[i64] }:$src0, i64:{ *:[i64] }:$src1, v16f32:{ *:[v16f32] }:$src2, (timm:{ *:[i32] }):$cbsz, (timm:{ *:[i32] }):$abid, (timm:{ *:[i32] }):$blgp)<<P:Predicate_anonymous_24906>>  =>  (V_MFMA_F32_32X32X16_FP8_FP8_mac_e64:{ *:[v16f32] } i64:{ *:[i64] }:$src0, i64:{ *:[i64] }:$src1, v16f32:{ *:[v16f32] }:$src2, (timm:{ *:[i32] }):$cbsz, (timm:{ *:[i32] }):$abid, (timm:{ *:[i32] }):$blgp)
        GIR_BuildMI, /*InsnID*/0, /*Opcode*/GIMT_Encode2(AMDGPU::V_MFMA_F32_32X32X16_FP8_FP8_mac_e64),
        GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/0, // DstI[vdst]
        GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/2, // src0
        GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/3, // src1
        GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/4, // src2
        GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/5, // cbsz
        GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/6, // abid
        GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/7, // blgp
        GIR_ConstrainSelectedInstOperands, /*InsnID*/0,
        GIR_EraseFromParent, /*InsnID*/0,
        // GIR_Coverage, 1068,
        GIR_Done,
      // Label 3605: @236238
      GIM_Try, /*On fail goto*//*Label 3606*/ GIMT_Encode4(236322), // Rule ID 1069 //
        GIM_CheckFeatures, GIMT_Encode2(GIFBS_isGFX940Plus),
        GIM_CheckIntrinsicID, /*MI*/0, /*Op*/1, GIMT_Encode2(Intrinsic::amdgcn_mfma_f32_32x32x16_fp8_fp8),
        GIM_CheckType, /*MI*/0, /*Op*/0, /*Type*/GILLT_v16s32,
        GIM_CheckType, /*MI*/0, /*Op*/2, /*Type*/GILLT_s64,
        GIM_CheckType, /*MI*/0, /*Op*/3, /*Type*/GILLT_s64,
        GIM_CheckType, /*MI*/0, /*Op*/4, /*Type*/GILLT_v16s32,
        GIM_CheckRegBankForClass, /*MI*/0, /*Op*/0, /*RC*/GIMT_Encode2(AMDGPU::VReg_512RegClassID),
        // MIs[0] cbsz
        GIM_CheckIsImm, /*MI*/0, /*Op*/5,
        // MIs[0] abid
        GIM_CheckIsImm, /*MI*/0, /*Op*/6,
        // MIs[0] blgp
        GIM_CheckIsImm, /*MI*/0, /*Op*/7,
        GIM_CheckCxxInsnPredicate, /*MI*/0, /*FnId*/GIMT_Encode2(GICXXPred_MI_Predicate_anonymous_24908),
        // (intrinsic_wo_chain:{ *:[v16f32] } 2556:{ *:[iPTR] }, i64:{ *:[i64] }:$src0, i64:{ *:[i64] }:$src1, v16f32:{ *:[v16f32] }:$src2, (timm:{ *:[i32] }):$cbsz, (timm:{ *:[i32] }):$abid, (timm:{ *:[i32] }):$blgp)<<P:Predicate_anonymous_24908>>  =>  (V_MFMA_F32_32X32X16_FP8_FP8_mac_vgprcd_e64:{ *:[v16f32] } i64:{ *:[i64] }:$src0, i64:{ *:[i64] }:$src1, v16f32:{ *:[v16f32] }:$src2, (timm:{ *:[i32] }):$cbsz, (timm:{ *:[i32] }):$abid, (timm:{ *:[i32] }):$blgp)
        GIR_BuildMI, /*InsnID*/0, /*Opcode*/GIMT_Encode2(AMDGPU::V_MFMA_F32_32X32X16_FP8_FP8_mac_vgprcd_e64),
        GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/0, // DstI[vdst]
        GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/2, // src0
        GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/3, // src1
        GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/4, // src2
        GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/5, // cbsz
        GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/6, // abid
        GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/7, // blgp
        GIR_ConstrainSelectedInstOperands, /*InsnID*/0,
        GIR_EraseFromParent, /*InsnID*/0,
        // GIR_Coverage, 1069,
        GIR_Done,
      // Label 3606: @236322
      GIM_Try, /*On fail goto*//*Label 3607*/ GIMT_Encode4(236403), // Rule ID 1070 //
        GIM_CheckFeatures, GIMT_Encode2(GIFBS_isGFX940Plus),
        GIM_CheckIntrinsicID, /*MI*/0, /*Op*/1, GIMT_Encode2(Intrinsic::amdgcn_smfmac_f32_16x16x32_f16),
        GIM_CheckType, /*MI*/0, /*Op*/0, /*Type*/GILLT_v4s32,
        GIM_CheckType, /*MI*/0, /*Op*/2, /*Type*/GILLT_v4s16,
        GIM_CheckType, /*MI*/0, /*Op*/3, /*Type*/GILLT_v8s16,
        GIM_CheckType, /*MI*/0, /*Op*/4, /*Type*/GILLT_v4s32,
        GIM_CheckType, /*MI*/0, /*Op*/5, /*Type*/GILLT_s32,
        GIM_CheckRegBankForClass, /*MI*/0, /*Op*/0, /*RC*/GIMT_Encode2(AMDGPU::AV_128RegClassID),
        // MIs[0] cbsz
        GIM_CheckIsImm, /*MI*/0, /*Op*/6,
        // MIs[0] abid
        GIM_CheckIsImm, /*MI*/0, /*Op*/7,
        // (intrinsic_wo_chain:{ *:[v4f32] } 2715:{ *:[iPTR] }, v4f16:{ *:[v4f16] }:$src0, v8f16:{ *:[v8f16] }:$src1, v4f32:{ *:[v4f32] }:$src2, i32:{ *:[i32] }:$idx, (timm:{ *:[i32] }):$cbsz, (timm:{ *:[i32] }):$abid)  =>  (V_SMFMAC_F32_16X16X32_F16_e64:{ *:[v4f32] } v4f16:{ *:[v4f16] }:$src0, v8f16:{ *:[v8f16] }:$src1, i32:{ *:[i32] }:$idx, (timm:{ *:[i32] }):$cbsz, (timm:{ *:[i32] }):$abid, v4f32:{ *:[v4f32] }:$src2)
        GIR_BuildMI, /*InsnID*/0, /*Opcode*/GIMT_Encode2(AMDGPU::V_SMFMAC_F32_16X16X32_F16_e64),
        GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/0, // DstI[vdst]
        GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/2, // src0
        GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/3, // src1
        GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/5, // idx
        GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/6, // cbsz
        GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/7, // abid
        GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/4, // src2
        GIR_ConstrainSelectedInstOperands, /*InsnID*/0,
        GIR_EraseFromParent, /*InsnID*/0,
        // GIR_Coverage, 1070,
        GIR_Done,
      // Label 3607: @236403
      GIM_Try, /*On fail goto*//*Label 3608*/ GIMT_Encode4(236484), // Rule ID 1071 //
        GIM_CheckFeatures, GIMT_Encode2(GIFBS_isGFX940Plus),
        GIM_CheckIntrinsicID, /*MI*/0, /*Op*/1, GIMT_Encode2(Intrinsic::amdgcn_smfmac_f32_32x32x16_f16),
        GIM_CheckType, /*MI*/0, /*Op*/0, /*Type*/GILLT_v16s32,
        GIM_CheckType, /*MI*/0, /*Op*/2, /*Type*/GILLT_v4s16,
        GIM_CheckType, /*MI*/0, /*Op*/3, /*Type*/GILLT_v8s16,
        GIM_CheckType, /*MI*/0, /*Op*/4, /*Type*/GILLT_v16s32,
        GIM_CheckType, /*MI*/0, /*Op*/5, /*Type*/GILLT_s32,
        GIM_CheckRegBankForClass, /*MI*/0, /*Op*/0, /*RC*/GIMT_Encode2(AMDGPU::AV_512RegClassID),
        // MIs[0] cbsz
        GIM_CheckIsImm, /*MI*/0, /*Op*/6,
        // MIs[0] abid
        GIM_CheckIsImm, /*MI*/0, /*Op*/7,
        // (intrinsic_wo_chain:{ *:[v16f32] } 2721:{ *:[iPTR] }, v4f16:{ *:[v4f16] }:$src0, v8f16:{ *:[v8f16] }:$src1, v16f32:{ *:[v16f32] }:$src2, i32:{ *:[i32] }:$idx, (timm:{ *:[i32] }):$cbsz, (timm:{ *:[i32] }):$abid)  =>  (V_SMFMAC_F32_32X32X16_F16_e64:{ *:[v16f32] } v4f16:{ *:[v4f16] }:$src0, v8f16:{ *:[v8f16] }:$src1, i32:{ *:[i32] }:$idx, (timm:{ *:[i32] }):$cbsz, (timm:{ *:[i32] }):$abid, v16f32:{ *:[v16f32] }:$src2)
        GIR_BuildMI, /*InsnID*/0, /*Opcode*/GIMT_Encode2(AMDGPU::V_SMFMAC_F32_32X32X16_F16_e64),
        GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/0, // DstI[vdst]
        GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/2, // src0
        GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/3, // src1
        GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/5, // idx
        GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/6, // cbsz
        GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/7, // abid
        GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/4, // src2
        GIR_ConstrainSelectedInstOperands, /*InsnID*/0,
        GIR_EraseFromParent, /*InsnID*/0,
        // GIR_Coverage, 1071,
        GIR_Done,
      // Label 3608: @236484
      GIM_Try, /*On fail goto*//*Label 3609*/ GIMT_Encode4(236565), // Rule ID 1072 //
        GIM_CheckFeatures, GIMT_Encode2(GIFBS_isGFX940Plus),
        GIM_CheckIntrinsicID, /*MI*/0, /*Op*/1, GIMT_Encode2(Intrinsic::amdgcn_smfmac_f32_16x16x32_bf16),
        GIM_CheckType, /*MI*/0, /*Op*/0, /*Type*/GILLT_v4s32,
        GIM_CheckType, /*MI*/0, /*Op*/2, /*Type*/GILLT_v4s16,
        GIM_CheckType, /*MI*/0, /*Op*/3, /*Type*/GILLT_v8s16,
        GIM_CheckType, /*MI*/0, /*Op*/4, /*Type*/GILLT_v4s32,
        GIM_CheckType, /*MI*/0, /*Op*/5, /*Type*/GILLT_s32,
        GIM_CheckRegBankForClass, /*MI*/0, /*Op*/0, /*RC*/GIMT_Encode2(AMDGPU::AV_128RegClassID),
        // MIs[0] cbsz
        GIM_CheckIsImm, /*MI*/0, /*Op*/6,
        // MIs[0] abid
        GIM_CheckIsImm, /*MI*/0, /*Op*/7,
        // (intrinsic_wo_chain:{ *:[v4f32] } 2714:{ *:[iPTR] }, v4i16:{ *:[v4i16] }:$src0, v8i16:{ *:[v8i16] }:$src1, v4f32:{ *:[v4f32] }:$src2, i32:{ *:[i32] }:$idx, (timm:{ *:[i32] }):$cbsz, (timm:{ *:[i32] }):$abid)  =>  (V_SMFMAC_F32_16X16X32_BF16_e64:{ *:[v4f32] } v4i16:{ *:[v4i16] }:$src0, v8i16:{ *:[v8i16] }:$src1, i32:{ *:[i32] }:$idx, (timm:{ *:[i32] }):$cbsz, (timm:{ *:[i32] }):$abid, v4f32:{ *:[v4f32] }:$src2)
        GIR_BuildMI, /*InsnID*/0, /*Opcode*/GIMT_Encode2(AMDGPU::V_SMFMAC_F32_16X16X32_BF16_e64),
        GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/0, // DstI[vdst]
        GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/2, // src0
        GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/3, // src1
        GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/5, // idx
        GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/6, // cbsz
        GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/7, // abid
        GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/4, // src2
        GIR_ConstrainSelectedInstOperands, /*InsnID*/0,
        GIR_EraseFromParent, /*InsnID*/0,
        // GIR_Coverage, 1072,
        GIR_Done,
      // Label 3609: @236565
      GIM_Try, /*On fail goto*//*Label 3610*/ GIMT_Encode4(236646), // Rule ID 1073 //
        GIM_CheckFeatures, GIMT_Encode2(GIFBS_isGFX940Plus),
        GIM_CheckIntrinsicID, /*MI*/0, /*Op*/1, GIMT_Encode2(Intrinsic::amdgcn_smfmac_f32_32x32x16_bf16),
        GIM_CheckType, /*MI*/0, /*Op*/0, /*Type*/GILLT_v16s32,
        GIM_CheckType, /*MI*/0, /*Op*/2, /*Type*/GILLT_v4s16,
        GIM_CheckType, /*MI*/0, /*Op*/3, /*Type*/GILLT_v8s16,
        GIM_CheckType, /*MI*/0, /*Op*/4, /*Type*/GILLT_v16s32,
        GIM_CheckType, /*MI*/0, /*Op*/5, /*Type*/GILLT_s32,
        GIM_CheckRegBankForClass, /*MI*/0, /*Op*/0, /*RC*/GIMT_Encode2(AMDGPU::AV_512RegClassID),
        // MIs[0] cbsz
        GIM_CheckIsImm, /*MI*/0, /*Op*/6,
        // MIs[0] abid
        GIM_CheckIsImm, /*MI*/0, /*Op*/7,
        // (intrinsic_wo_chain:{ *:[v16f32] } 2720:{ *:[iPTR] }, v4i16:{ *:[v4i16] }:$src0, v8i16:{ *:[v8i16] }:$src1, v16f32:{ *:[v16f32] }:$src2, i32:{ *:[i32] }:$idx, (timm:{ *:[i32] }):$cbsz, (timm:{ *:[i32] }):$abid)  =>  (V_SMFMAC_F32_32X32X16_BF16_e64:{ *:[v16f32] } v4i16:{ *:[v4i16] }:$src0, v8i16:{ *:[v8i16] }:$src1, i32:{ *:[i32] }:$idx, (timm:{ *:[i32] }):$cbsz, (timm:{ *:[i32] }):$abid, v16f32:{ *:[v16f32] }:$src2)
        GIR_BuildMI, /*InsnID*/0, /*Opcode*/GIMT_Encode2(AMDGPU::V_SMFMAC_F32_32X32X16_BF16_e64),
        GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/0, // DstI[vdst]
        GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/2, // src0
        GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/3, // src1
        GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/5, // idx
        GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/6, // cbsz
        GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/7, // abid
        GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/4, // src2
        GIR_ConstrainSelectedInstOperands, /*InsnID*/0,
        GIR_EraseFromParent, /*InsnID*/0,
        // GIR_Coverage, 1073,
        GIR_Done,
      // Label 3610: @236646
      GIM_Try, /*On fail goto*//*Label 3611*/ GIMT_Encode4(236727), // Rule ID 1074 //
        GIM_CheckFeatures, GIMT_Encode2(GIFBS_isGFX940Plus),
        GIM_CheckIntrinsicID, /*MI*/0, /*Op*/1, GIMT_Encode2(Intrinsic::amdgcn_smfmac_i32_16x16x64_i8),
        GIM_CheckType, /*MI*/0, /*Op*/0, /*Type*/GILLT_v4s32,
        GIM_CheckType, /*MI*/0, /*Op*/2, /*Type*/GILLT_v2s32,
        GIM_CheckType, /*MI*/0, /*Op*/3, /*Type*/GILLT_v4s32,
        GIM_CheckType, /*MI*/0, /*Op*/4, /*Type*/GILLT_v4s32,
        GIM_CheckType, /*MI*/0, /*Op*/5, /*Type*/GILLT_s32,
        GIM_CheckRegBankForClass, /*MI*/0, /*Op*/0, /*RC*/GIMT_Encode2(AMDGPU::AV_128RegClassID),
        // MIs[0] cbsz
        GIM_CheckIsImm, /*MI*/0, /*Op*/6,
        // MIs[0] abid
        GIM_CheckIsImm, /*MI*/0, /*Op*/7,
        // (intrinsic_wo_chain:{ *:[v4i32] } 2726:{ *:[iPTR] }, v2i32:{ *:[v2i32] }:$src0, v4i32:{ *:[v4i32] }:$src1, v4i32:{ *:[v4i32] }:$src2, i32:{ *:[i32] }:$idx, (timm:{ *:[i32] }):$cbsz, (timm:{ *:[i32] }):$abid)  =>  (V_SMFMAC_I32_16X16X64_I8_e64:{ *:[v4i32] } v2i32:{ *:[v2i32] }:$src0, v4i32:{ *:[v4i32] }:$src1, i32:{ *:[i32] }:$idx, (timm:{ *:[i32] }):$cbsz, (timm:{ *:[i32] }):$abid, v4i32:{ *:[v4i32] }:$src2)
        GIR_BuildMI, /*InsnID*/0, /*Opcode*/GIMT_Encode2(AMDGPU::V_SMFMAC_I32_16X16X64_I8_e64),
        GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/0, // DstI[vdst]
        GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/2, // src0
        GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/3, // src1
        GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/5, // idx
        GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/6, // cbsz
        GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/7, // abid
        GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/4, // src2
        GIR_ConstrainSelectedInstOperands, /*InsnID*/0,
        GIR_EraseFromParent, /*InsnID*/0,
        // GIR_Coverage, 1074,
        GIR_Done,
      // Label 3611: @236727
      GIM_Try, /*On fail goto*//*Label 3612*/ GIMT_Encode4(236808), // Rule ID 1075 //
        GIM_CheckFeatures, GIMT_Encode2(GIFBS_isGFX940Plus),
        GIM_CheckIntrinsicID, /*MI*/0, /*Op*/1, GIMT_Encode2(Intrinsic::amdgcn_smfmac_i32_32x32x32_i8),
        GIM_CheckType, /*MI*/0, /*Op*/0, /*Type*/GILLT_v16s32,
        GIM_CheckType, /*MI*/0, /*Op*/2, /*Type*/GILLT_v2s32,
        GIM_CheckType, /*MI*/0, /*Op*/3, /*Type*/GILLT_v4s32,
        GIM_CheckType, /*MI*/0, /*Op*/4, /*Type*/GILLT_v16s32,
        GIM_CheckType, /*MI*/0, /*Op*/5, /*Type*/GILLT_s32,
        GIM_CheckRegBankForClass, /*MI*/0, /*Op*/0, /*RC*/GIMT_Encode2(AMDGPU::AV_512RegClassID),
        // MIs[0] cbsz
        GIM_CheckIsImm, /*MI*/0, /*Op*/6,
        // MIs[0] abid
        GIM_CheckIsImm, /*MI*/0, /*Op*/7,
        // (intrinsic_wo_chain:{ *:[v16i32] } 2727:{ *:[iPTR] }, v2i32:{ *:[v2i32] }:$src0, v4i32:{ *:[v4i32] }:$src1, v16i32:{ *:[v16i32] }:$src2, i32:{ *:[i32] }:$idx, (timm:{ *:[i32] }):$cbsz, (timm:{ *:[i32] }):$abid)  =>  (V_SMFMAC_I32_32X32X32_I8_e64:{ *:[v16i32] } v2i32:{ *:[v2i32] }:$src0, v4i32:{ *:[v4i32] }:$src1, i32:{ *:[i32] }:$idx, (timm:{ *:[i32] }):$cbsz, (timm:{ *:[i32] }):$abid, v16i32:{ *:[v16i32] }:$src2)
        GIR_BuildMI, /*InsnID*/0, /*Opcode*/GIMT_Encode2(AMDGPU::V_SMFMAC_I32_32X32X32_I8_e64),
        GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/0, // DstI[vdst]
        GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/2, // src0
        GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/3, // src1
        GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/5, // idx
        GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/6, // cbsz
        GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/7, // abid
        GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/4, // src2
        GIR_ConstrainSelectedInstOperands, /*InsnID*/0,
        GIR_EraseFromParent, /*InsnID*/0,
        // GIR_Coverage, 1075,
        GIR_Done,
      // Label 3612: @236808
      GIM_Try, /*On fail goto*//*Label 3613*/ GIMT_Encode4(236889), // Rule ID 1076 //
        GIM_CheckFeatures, GIMT_Encode2(GIFBS_isGFX940Plus),
        GIM_CheckIntrinsicID, /*MI*/0, /*Op*/1, GIMT_Encode2(Intrinsic::amdgcn_smfmac_f32_16x16x64_bf8_bf8),
        GIM_CheckType, /*MI*/0, /*Op*/0, /*Type*/GILLT_v4s32,
        GIM_CheckType, /*MI*/0, /*Op*/2, /*Type*/GILLT_v2s32,
        GIM_CheckType, /*MI*/0, /*Op*/3, /*Type*/GILLT_v4s32,
        GIM_CheckType, /*MI*/0, /*Op*/4, /*Type*/GILLT_v4s32,
        GIM_CheckType, /*MI*/0, /*Op*/5, /*Type*/GILLT_s32,
        GIM_CheckRegBankForClass, /*MI*/0, /*Op*/0, /*RC*/GIMT_Encode2(AMDGPU::AV_128RegClassID),
        // MIs[0] cbsz
        GIM_CheckIsImm, /*MI*/0, /*Op*/6,
        // MIs[0] abid
        GIM_CheckIsImm, /*MI*/0, /*Op*/7,
        // (intrinsic_wo_chain:{ *:[v4f32] } 2716:{ *:[iPTR] }, v2i32:{ *:[v2i32] }:$src0, v4i32:{ *:[v4i32] }:$src1, v4f32:{ *:[v4f32] }:$src2, i32:{ *:[i32] }:$idx, (timm:{ *:[i32] }):$cbsz, (timm:{ *:[i32] }):$abid)  =>  (V_SMFMAC_F32_16X16X64_BF8_BF8_e64:{ *:[v4f32] } v2i32:{ *:[v2i32] }:$src0, v4i32:{ *:[v4i32] }:$src1, i32:{ *:[i32] }:$idx, (timm:{ *:[i32] }):$cbsz, (timm:{ *:[i32] }):$abid, v4f32:{ *:[v4f32] }:$src2)
        GIR_BuildMI, /*InsnID*/0, /*Opcode*/GIMT_Encode2(AMDGPU::V_SMFMAC_F32_16X16X64_BF8_BF8_e64),
        GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/0, // DstI[vdst]
        GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/2, // src0
        GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/3, // src1
        GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/5, // idx
        GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/6, // cbsz
        GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/7, // abid
        GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/4, // src2
        GIR_ConstrainSelectedInstOperands, /*InsnID*/0,
        GIR_EraseFromParent, /*InsnID*/0,
        // GIR_Coverage, 1076,
        GIR_Done,
      // Label 3613: @236889
      GIM_Try, /*On fail goto*//*Label 3614*/ GIMT_Encode4(236970), // Rule ID 1077 //
        GIM_CheckFeatures, GIMT_Encode2(GIFBS_isGFX940Plus),
        GIM_CheckIntrinsicID, /*MI*/0, /*Op*/1, GIMT_Encode2(Intrinsic::amdgcn_smfmac_f32_16x16x64_bf8_fp8),
        GIM_CheckType, /*MI*/0, /*Op*/0, /*Type*/GILLT_v4s32,
        GIM_CheckType, /*MI*/0, /*Op*/2, /*Type*/GILLT_v2s32,
        GIM_CheckType, /*MI*/0, /*Op*/3, /*Type*/GILLT_v4s32,
        GIM_CheckType, /*MI*/0, /*Op*/4, /*Type*/GILLT_v4s32,
        GIM_CheckType, /*MI*/0, /*Op*/5, /*Type*/GILLT_s32,
        GIM_CheckRegBankForClass, /*MI*/0, /*Op*/0, /*RC*/GIMT_Encode2(AMDGPU::AV_128RegClassID),
        // MIs[0] cbsz
        GIM_CheckIsImm, /*MI*/0, /*Op*/6,
        // MIs[0] abid
        GIM_CheckIsImm, /*MI*/0, /*Op*/7,
        // (intrinsic_wo_chain:{ *:[v4f32] } 2717:{ *:[iPTR] }, v2i32:{ *:[v2i32] }:$src0, v4i32:{ *:[v4i32] }:$src1, v4f32:{ *:[v4f32] }:$src2, i32:{ *:[i32] }:$idx, (timm:{ *:[i32] }):$cbsz, (timm:{ *:[i32] }):$abid)  =>  (V_SMFMAC_F32_16X16X64_BF8_FP8_e64:{ *:[v4f32] } v2i32:{ *:[v2i32] }:$src0, v4i32:{ *:[v4i32] }:$src1, i32:{ *:[i32] }:$idx, (timm:{ *:[i32] }):$cbsz, (timm:{ *:[i32] }):$abid, v4f32:{ *:[v4f32] }:$src2)
        GIR_BuildMI, /*InsnID*/0, /*Opcode*/GIMT_Encode2(AMDGPU::V_SMFMAC_F32_16X16X64_BF8_FP8_e64),
        GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/0, // DstI[vdst]
        GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/2, // src0
        GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/3, // src1
        GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/5, // idx
        GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/6, // cbsz
        GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/7, // abid
        GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/4, // src2
        GIR_ConstrainSelectedInstOperands, /*InsnID*/0,
        GIR_EraseFromParent, /*InsnID*/0,
        // GIR_Coverage, 1077,
        GIR_Done,
      // Label 3614: @236970
      GIM_Try, /*On fail goto*//*Label 3615*/ GIMT_Encode4(237051), // Rule ID 1078 //
        GIM_CheckFeatures, GIMT_Encode2(GIFBS_isGFX940Plus),
        GIM_CheckIntrinsicID, /*MI*/0, /*Op*/1, GIMT_Encode2(Intrinsic::amdgcn_smfmac_f32_16x16x64_fp8_bf8),
        GIM_CheckType, /*MI*/0, /*Op*/0, /*Type*/GILLT_v4s32,
        GIM_CheckType, /*MI*/0, /*Op*/2, /*Type*/GILLT_v2s32,
        GIM_CheckType, /*MI*/0, /*Op*/3, /*Type*/GILLT_v4s32,
        GIM_CheckType, /*MI*/0, /*Op*/4, /*Type*/GILLT_v4s32,
        GIM_CheckType, /*MI*/0, /*Op*/5, /*Type*/GILLT_s32,
        GIM_CheckRegBankForClass, /*MI*/0, /*Op*/0, /*RC*/GIMT_Encode2(AMDGPU::AV_128RegClassID),
        // MIs[0] cbsz
        GIM_CheckIsImm, /*MI*/0, /*Op*/6,
        // MIs[0] abid
        GIM_CheckIsImm, /*MI*/0, /*Op*/7,
        // (intrinsic_wo_chain:{ *:[v4f32] } 2718:{ *:[iPTR] }, v2i32:{ *:[v2i32] }:$src0, v4i32:{ *:[v4i32] }:$src1, v4f32:{ *:[v4f32] }:$src2, i32:{ *:[i32] }:$idx, (timm:{ *:[i32] }):$cbsz, (timm:{ *:[i32] }):$abid)  =>  (V_SMFMAC_F32_16X16X64_FP8_BF8_e64:{ *:[v4f32] } v2i32:{ *:[v2i32] }:$src0, v4i32:{ *:[v4i32] }:$src1, i32:{ *:[i32] }:$idx, (timm:{ *:[i32] }):$cbsz, (timm:{ *:[i32] }):$abid, v4f32:{ *:[v4f32] }:$src2)
        GIR_BuildMI, /*InsnID*/0, /*Opcode*/GIMT_Encode2(AMDGPU::V_SMFMAC_F32_16X16X64_FP8_BF8_e64),
        GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/0, // DstI[vdst]
        GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/2, // src0
        GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/3, // src1
        GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/5, // idx
        GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/6, // cbsz
        GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/7, // abid
        GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/4, // src2
        GIR_ConstrainSelectedInstOperands, /*InsnID*/0,
        GIR_EraseFromParent, /*InsnID*/0,
        // GIR_Coverage, 1078,
        GIR_Done,
      // Label 3615: @237051
      GIM_Try, /*On fail goto*//*Label 3616*/ GIMT_Encode4(237132), // Rule ID 1079 //
        GIM_CheckFeatures, GIMT_Encode2(GIFBS_isGFX940Plus),
        GIM_CheckIntrinsicID, /*MI*/0, /*Op*/1, GIMT_Encode2(Intrinsic::amdgcn_smfmac_f32_16x16x64_fp8_fp8),
        GIM_CheckType, /*MI*/0, /*Op*/0, /*Type*/GILLT_v4s32,
        GIM_CheckType, /*MI*/0, /*Op*/2, /*Type*/GILLT_v2s32,
        GIM_CheckType, /*MI*/0, /*Op*/3, /*Type*/GILLT_v4s32,
        GIM_CheckType, /*MI*/0, /*Op*/4, /*Type*/GILLT_v4s32,
        GIM_CheckType, /*MI*/0, /*Op*/5, /*Type*/GILLT_s32,
        GIM_CheckRegBankForClass, /*MI*/0, /*Op*/0, /*RC*/GIMT_Encode2(AMDGPU::AV_128RegClassID),
        // MIs[0] cbsz
        GIM_CheckIsImm, /*MI*/0, /*Op*/6,
        // MIs[0] abid
        GIM_CheckIsImm, /*MI*/0, /*Op*/7,
        // (intrinsic_wo_chain:{ *:[v4f32] } 2719:{ *:[iPTR] }, v2i32:{ *:[v2i32] }:$src0, v4i32:{ *:[v4i32] }:$src1, v4f32:{ *:[v4f32] }:$src2, i32:{ *:[i32] }:$idx, (timm:{ *:[i32] }):$cbsz, (timm:{ *:[i32] }):$abid)  =>  (V_SMFMAC_F32_16X16X64_FP8_FP8_e64:{ *:[v4f32] } v2i32:{ *:[v2i32] }:$src0, v4i32:{ *:[v4i32] }:$src1, i32:{ *:[i32] }:$idx, (timm:{ *:[i32] }):$cbsz, (timm:{ *:[i32] }):$abid, v4f32:{ *:[v4f32] }:$src2)
        GIR_BuildMI, /*InsnID*/0, /*Opcode*/GIMT_Encode2(AMDGPU::V_SMFMAC_F32_16X16X64_FP8_FP8_e64),
        GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/0, // DstI[vdst]
        GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/2, // src0
        GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/3, // src1
        GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/5, // idx
        GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/6, // cbsz
        GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/7, // abid
        GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/4, // src2
        GIR_ConstrainSelectedInstOperands, /*InsnID*/0,
        GIR_EraseFromParent, /*InsnID*/0,
        // GIR_Coverage, 1079,
        GIR_Done,
      // Label 3616: @237132
      GIM_Try, /*On fail goto*//*Label 3617*/ GIMT_Encode4(237213), // Rule ID 1080 //
        GIM_CheckFeatures, GIMT_Encode2(GIFBS_isGFX940Plus),
        GIM_CheckIntrinsicID, /*MI*/0, /*Op*/1, GIMT_Encode2(Intrinsic::amdgcn_smfmac_f32_32x32x32_bf8_bf8),
        GIM_CheckType, /*MI*/0, /*Op*/0, /*Type*/GILLT_v16s32,
        GIM_CheckType, /*MI*/0, /*Op*/2, /*Type*/GILLT_v2s32,
        GIM_CheckType, /*MI*/0, /*Op*/3, /*Type*/GILLT_v4s32,
        GIM_CheckType, /*MI*/0, /*Op*/4, /*Type*/GILLT_v16s32,
        GIM_CheckType, /*MI*/0, /*Op*/5, /*Type*/GILLT_s32,
        GIM_CheckRegBankForClass, /*MI*/0, /*Op*/0, /*RC*/GIMT_Encode2(AMDGPU::AV_512RegClassID),
        // MIs[0] cbsz
        GIM_CheckIsImm, /*MI*/0, /*Op*/6,
        // MIs[0] abid
        GIM_CheckIsImm, /*MI*/0, /*Op*/7,
        // (intrinsic_wo_chain:{ *:[v16f32] } 2722:{ *:[iPTR] }, v2i32:{ *:[v2i32] }:$src0, v4i32:{ *:[v4i32] }:$src1, v16f32:{ *:[v16f32] }:$src2, i32:{ *:[i32] }:$idx, (timm:{ *:[i32] }):$cbsz, (timm:{ *:[i32] }):$abid)  =>  (V_SMFMAC_F32_32X32X32_BF8_BF8_e64:{ *:[v16f32] } v2i32:{ *:[v2i32] }:$src0, v4i32:{ *:[v4i32] }:$src1, i32:{ *:[i32] }:$idx, (timm:{ *:[i32] }):$cbsz, (timm:{ *:[i32] }):$abid, v16f32:{ *:[v16f32] }:$src2)
        GIR_BuildMI, /*InsnID*/0, /*Opcode*/GIMT_Encode2(AMDGPU::V_SMFMAC_F32_32X32X32_BF8_BF8_e64),
        GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/0, // DstI[vdst]
        GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/2, // src0
        GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/3, // src1
        GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/5, // idx
        GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/6, // cbsz
        GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/7, // abid
        GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/4, // src2
        GIR_ConstrainSelectedInstOperands, /*InsnID*/0,
        GIR_EraseFromParent, /*InsnID*/0,
        // GIR_Coverage, 1080,
        GIR_Done,
      // Label 3617: @237213
      GIM_Try, /*On fail goto*//*Label 3618*/ GIMT_Encode4(237294), // Rule ID 1081 //
        GIM_CheckFeatures, GIMT_Encode2(GIFBS_isGFX940Plus),
        GIM_CheckIntrinsicID, /*MI*/0, /*Op*/1, GIMT_Encode2(Intrinsic::amdgcn_smfmac_f32_32x32x32_bf8_fp8),
        GIM_CheckType, /*MI*/0, /*Op*/0, /*Type*/GILLT_v16s32,
        GIM_CheckType, /*MI*/0, /*Op*/2, /*Type*/GILLT_v2s32,
        GIM_CheckType, /*MI*/0, /*Op*/3, /*Type*/GILLT_v4s32,
        GIM_CheckType, /*MI*/0, /*Op*/4, /*Type*/GILLT_v16s32,
        GIM_CheckType, /*MI*/0, /*Op*/5, /*Type*/GILLT_s32,
        GIM_CheckRegBankForClass, /*MI*/0, /*Op*/0, /*RC*/GIMT_Encode2(AMDGPU::AV_512RegClassID),
        // MIs[0] cbsz
        GIM_CheckIsImm, /*MI*/0, /*Op*/6,
        // MIs[0] abid
        GIM_CheckIsImm, /*MI*/0, /*Op*/7,
        // (intrinsic_wo_chain:{ *:[v16f32] } 2723:{ *:[iPTR] }, v2i32:{ *:[v2i32] }:$src0, v4i32:{ *:[v4i32] }:$src1, v16f32:{ *:[v16f32] }:$src2, i32:{ *:[i32] }:$idx, (timm:{ *:[i32] }):$cbsz, (timm:{ *:[i32] }):$abid)  =>  (V_SMFMAC_F32_32X32X32_BF8_FP8_e64:{ *:[v16f32] } v2i32:{ *:[v2i32] }:$src0, v4i32:{ *:[v4i32] }:$src1, i32:{ *:[i32] }:$idx, (timm:{ *:[i32] }):$cbsz, (timm:{ *:[i32] }):$abid, v16f32:{ *:[v16f32] }:$src2)
        GIR_BuildMI, /*InsnID*/0, /*Opcode*/GIMT_Encode2(AMDGPU::V_SMFMAC_F32_32X32X32_BF8_FP8_e64),
        GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/0, // DstI[vdst]
        GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/2, // src0
        GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/3, // src1
        GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/5, // idx
        GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/6, // cbsz
        GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/7, // abid
        GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/4, // src2
        GIR_ConstrainSelectedInstOperands, /*InsnID*/0,
        GIR_EraseFromParent, /*InsnID*/0,
        // GIR_Coverage, 1081,
        GIR_Done,
      // Label 3618: @237294
      GIM_Try, /*On fail goto*//*Label 3619*/ GIMT_Encode4(237375), // Rule ID 1082 //
        GIM_CheckFeatures, GIMT_Encode2(GIFBS_isGFX940Plus),
        GIM_CheckIntrinsicID, /*MI*/0, /*Op*/1, GIMT_Encode2(Intrinsic::amdgcn_smfmac_f32_32x32x32_fp8_bf8),
        GIM_CheckType, /*MI*/0, /*Op*/0, /*Type*/GILLT_v16s32,
        GIM_CheckType, /*MI*/0, /*Op*/2, /*Type*/GILLT_v2s32,
        GIM_CheckType, /*MI*/0, /*Op*/3, /*Type*/GILLT_v4s32,
        GIM_CheckType, /*MI*/0, /*Op*/4, /*Type*/GILLT_v16s32,
        GIM_CheckType, /*MI*/0, /*Op*/5, /*Type*/GILLT_s32,
        GIM_CheckRegBankForClass, /*MI*/0, /*Op*/0, /*RC*/GIMT_Encode2(AMDGPU::AV_512RegClassID),
        // MIs[0] cbsz
        GIM_CheckIsImm, /*MI*/0, /*Op*/6,
        // MIs[0] abid
        GIM_CheckIsImm, /*MI*/0, /*Op*/7,
        // (intrinsic_wo_chain:{ *:[v16f32] } 2724:{ *:[iPTR] }, v2i32:{ *:[v2i32] }:$src0, v4i32:{ *:[v4i32] }:$src1, v16f32:{ *:[v16f32] }:$src2, i32:{ *:[i32] }:$idx, (timm:{ *:[i32] }):$cbsz, (timm:{ *:[i32] }):$abid)  =>  (V_SMFMAC_F32_32X32X32_FP8_BF8_e64:{ *:[v16f32] } v2i32:{ *:[v2i32] }:$src0, v4i32:{ *:[v4i32] }:$src1, i32:{ *:[i32] }:$idx, (timm:{ *:[i32] }):$cbsz, (timm:{ *:[i32] }):$abid, v16f32:{ *:[v16f32] }:$src2)
        GIR_BuildMI, /*InsnID*/0, /*Opcode*/GIMT_Encode2(AMDGPU::V_SMFMAC_F32_32X32X32_FP8_BF8_e64),
        GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/0, // DstI[vdst]
        GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/2, // src0
        GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/3, // src1
        GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/5, // idx
        GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/6, // cbsz
        GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/7, // abid
        GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/4, // src2
        GIR_ConstrainSelectedInstOperands, /*InsnID*/0,
        GIR_EraseFromParent, /*InsnID*/0,
        // GIR_Coverage, 1082,
        GIR_Done,
      // Label 3619: @237375
      GIM_Try, /*On fail goto*//*Label 3620*/ GIMT_Encode4(237456), // Rule ID 1083 //
        GIM_CheckFeatures, GIMT_Encode2(GIFBS_isGFX940Plus),
        GIM_CheckIntrinsicID, /*MI*/0, /*Op*/1, GIMT_Encode2(Intrinsic::amdgcn_smfmac_f32_32x32x32_fp8_fp8),
        GIM_CheckType, /*MI*/0, /*Op*/0, /*Type*/GILLT_v16s32,
        GIM_CheckType, /*MI*/0, /*Op*/2, /*Type*/GILLT_v2s32,
        GIM_CheckType, /*MI*/0, /*Op*/3, /*Type*/GILLT_v4s32,
        GIM_CheckType, /*MI*/0, /*Op*/4, /*Type*/GILLT_v16s32,
        GIM_CheckType, /*MI*/0, /*Op*/5, /*Type*/GILLT_s32,
        GIM_CheckRegBankForClass, /*MI*/0, /*Op*/0, /*RC*/GIMT_Encode2(AMDGPU::AV_512RegClassID),
        // MIs[0] cbsz
        GIM_CheckIsImm, /*MI*/0, /*Op*/6,
        // MIs[0] abid
        GIM_CheckIsImm, /*MI*/0, /*Op*/7,
        // (intrinsic_wo_chain:{ *:[v16f32] } 2725:{ *:[iPTR] }, v2i32:{ *:[v2i32] }:$src0, v4i32:{ *:[v4i32] }:$src1, v16f32:{ *:[v16f32] }:$src2, i32:{ *:[i32] }:$idx, (timm:{ *:[i32] }):$cbsz, (timm:{ *:[i32] }):$abid)  =>  (V_SMFMAC_F32_32X32X32_FP8_FP8_e64:{ *:[v16f32] } v2i32:{ *:[v2i32] }:$src0, v4i32:{ *:[v4i32] }:$src1, i32:{ *:[i32] }:$idx, (timm:{ *:[i32] }):$cbsz, (timm:{ *:[i32] }):$abid, v16f32:{ *:[v16f32] }:$src2)
        GIR_BuildMI, /*InsnID*/0, /*Opcode*/GIMT_Encode2(AMDGPU::V_SMFMAC_F32_32X32X32_FP8_FP8_e64),
        GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/0, // DstI[vdst]
        GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/2, // src0
        GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/3, // src1
        GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/5, // idx
        GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/6, // cbsz
        GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/7, // abid
        GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/4, // src2
        GIR_ConstrainSelectedInstOperands, /*InsnID*/0,
        GIR_EraseFromParent, /*InsnID*/0,
        // GIR_Coverage, 1083,
        GIR_Done,
      // Label 3620: @237456
      GIM_Reject,
    // Label 3505: @237457
    GIM_Try, /*On fail goto*//*Label 3621*/ GIMT_Encode4(238119),
      GIM_CheckNumOperands, /*MI*/0, /*Expected*/9,
      GIM_Try, /*On fail goto*//*Label 3622*/ GIMT_Encode4(237576), // Rule ID 2361 //
        GIM_CheckFeatures, GIMT_Encode2(GIFBS_isGFX12Plus_isWave32),
        GIM_CheckIntrinsicID, /*MI*/0, /*Op*/1, GIMT_Encode2(Intrinsic::amdgcn_swmmac_i32_16x16x32_iu8),
        GIM_CheckType, /*MI*/0, /*Op*/0, /*Type*/GILLT_v8s32,
        GIM_CheckType, /*MI*/0, /*Op*/3, /*Type*/GILLT_v2s32,
        GIM_CheckType, /*MI*/0, /*Op*/5, /*Type*/GILLT_v4s32,
        GIM_CheckType, /*MI*/0, /*Op*/6, /*Type*/GILLT_v8s32,
        GIM_CheckType, /*MI*/0, /*Op*/7, /*Type*/GILLT_s32,
        GIM_CheckRegBankForClass, /*MI*/0, /*Op*/0, /*RC*/GIMT_Encode2(AMDGPU::VReg_256RegClassID),
        // MIs[0] clamp
        // No operand predicates
        GIM_CheckComplexPattern, /*MI*/0, /*Op*/2, /*Renderer*/GIMT_Encode2(0), GIMT_Encode2(GICP_gi_vop3pmodsneg),
        GIM_CheckComplexPattern, /*MI*/0, /*Op*/4, /*Renderer*/GIMT_Encode2(1), GIMT_Encode2(GICP_gi_vop3pmodsneg),
        GIM_CheckComplexPattern, /*MI*/0, /*Op*/7, /*Renderer*/GIMT_Encode2(2), GIMT_Encode2(GICP_gi_swmmacindex16),
        // (intrinsic_wo_chain:{ *:[v8i32] } 2793:{ *:[iPTR] }, (VOP3PModsNeg:{ *:[i1] } i32:{ *:[i32] }:$src0_modifiers), v2i32:{ *:[v2i32] }:$src0, (VOP3PModsNeg:{ *:[i1] } i32:{ *:[i32] }:$src1_modifiers), v4i32:{ *:[v4i32] }:$src1, v8i32:{ *:[v8i32] }:$srcTiedDef, (SWMMACIndex16:{ *:[i32] } i32:{ *:[i32] }:$src2, i32:{ *:[i32] }:$index_key_16bit), i1:{ *:[i1] }:$clamp)  =>  (V_SWMMAC_I32_16X16X32_IU8_w32_twoaddr:{ *:[v8i32] } i32:{ *:[i32] }:$src0_modifiers, v2i32:{ *:[v2i32] }:$src0, i32:{ *:[i32] }:$src1_modifiers, v4i32:{ *:[v4i32] }:$src1, v8i32:{ *:[v8i32] }:$srcTiedDef, i32:{ *:[i32] }:$src2, i32:{ *:[i32] }:$index_key_16bit, i1:{ *:[i1] }:$clamp)
        GIR_BuildMI, /*InsnID*/0, /*Opcode*/GIMT_Encode2(AMDGPU::V_SWMMAC_I32_16X16X32_IU8_w32_twoaddr),
        GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/0, // DstI[vdst]
        GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/0, // src0_modifiers
        GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/3, // src0
        GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(1), /*SubOperand*/0, // src1_modifiers
        GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/5, // src1
        GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/6, // srcTiedDef
        GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(2), /*SubOperand*/0, // src2
        GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(2), /*SubOperand*/1, // index_key_16bit
        GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/8, // clamp
        GIR_AddImm8, /*InsnID*/0, /*Imm*/0,
        GIR_ConstrainSelectedInstOperands, /*InsnID*/0,
        GIR_EraseFromParent, /*InsnID*/0,
        // GIR_Coverage, 2361,
        GIR_Done,
      // Label 3622: @237576
      GIM_Try, /*On fail goto*//*Label 3623*/ GIMT_Encode4(237687), // Rule ID 2362 //
        GIM_CheckFeatures, GIMT_Encode2(GIFBS_isGFX12Plus_isWave32),
        GIM_CheckIntrinsicID, /*MI*/0, /*Op*/1, GIMT_Encode2(Intrinsic::amdgcn_swmmac_i32_16x16x32_iu4),
        GIM_CheckType, /*MI*/0, /*Op*/0, /*Type*/GILLT_v8s32,
        GIM_CheckType, /*MI*/0, /*Op*/3, /*Type*/GILLT_s32,
        GIM_CheckType, /*MI*/0, /*Op*/5, /*Type*/GILLT_v2s32,
        GIM_CheckType, /*MI*/0, /*Op*/6, /*Type*/GILLT_v8s32,
        GIM_CheckType, /*MI*/0, /*Op*/7, /*Type*/GILLT_s32,
        GIM_CheckRegBankForClass, /*MI*/0, /*Op*/0, /*RC*/GIMT_Encode2(AMDGPU::VReg_256RegClassID),
        // MIs[0] clamp
        // No operand predicates
        GIM_CheckComplexPattern, /*MI*/0, /*Op*/2, /*Renderer*/GIMT_Encode2(0), GIMT_Encode2(GICP_gi_vop3pmodsneg),
        GIM_CheckComplexPattern, /*MI*/0, /*Op*/4, /*Renderer*/GIMT_Encode2(1), GIMT_Encode2(GICP_gi_vop3pmodsneg),
        GIM_CheckComplexPattern, /*MI*/0, /*Op*/7, /*Renderer*/GIMT_Encode2(2), GIMT_Encode2(GICP_gi_swmmacindex16),
        // (intrinsic_wo_chain:{ *:[v8i32] } 2792:{ *:[iPTR] }, (VOP3PModsNeg:{ *:[i1] } i32:{ *:[i32] }:$src0_modifiers), i32:{ *:[i32] }:$src0, (VOP3PModsNeg:{ *:[i1] } i32:{ *:[i32] }:$src1_modifiers), v2i32:{ *:[v2i32] }:$src1, v8i32:{ *:[v8i32] }:$srcTiedDef, (SWMMACIndex16:{ *:[i32] } i32:{ *:[i32] }:$src2, i32:{ *:[i32] }:$index_key_16bit), i1:{ *:[i1] }:$clamp)  =>  (V_SWMMAC_I32_16X16X32_IU4_w32_twoaddr:{ *:[v8i32] } i32:{ *:[i32] }:$src0_modifiers, i32:{ *:[i32] }:$src0, i32:{ *:[i32] }:$src1_modifiers, v2i32:{ *:[v2i32] }:$src1, v8i32:{ *:[v8i32] }:$srcTiedDef, i32:{ *:[i32] }:$src2, i32:{ *:[i32] }:$index_key_16bit, i1:{ *:[i1] }:$clamp)
        GIR_BuildMI, /*InsnID*/0, /*Opcode*/GIMT_Encode2(AMDGPU::V_SWMMAC_I32_16X16X32_IU4_w32_twoaddr),
        GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/0, // DstI[vdst]
        GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/0, // src0_modifiers
        GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/3, // src0
        GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(1), /*SubOperand*/0, // src1_modifiers
        GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/5, // src1
        GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/6, // srcTiedDef
        GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(2), /*SubOperand*/0, // src2
        GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(2), /*SubOperand*/1, // index_key_16bit
        GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/8, // clamp
        GIR_AddImm8, /*InsnID*/0, /*Imm*/0,
        GIR_ConstrainSelectedInstOperands, /*InsnID*/0,
        GIR_EraseFromParent, /*InsnID*/0,
        // GIR_Coverage, 2362,
        GIR_Done,
      // Label 3623: @237687
      GIM_Try, /*On fail goto*//*Label 3624*/ GIMT_Encode4(237798), // Rule ID 2394 //
        GIM_CheckFeatures, GIMT_Encode2(GIFBS_isGFX12Plus_isWave64),
        GIM_CheckIntrinsicID, /*MI*/0, /*Op*/1, GIMT_Encode2(Intrinsic::amdgcn_swmmac_i32_16x16x32_iu8),
        GIM_CheckType, /*MI*/0, /*Op*/0, /*Type*/GILLT_v4s32,
        GIM_CheckType, /*MI*/0, /*Op*/3, /*Type*/GILLT_s32,
        GIM_CheckType, /*MI*/0, /*Op*/5, /*Type*/GILLT_v2s32,
        GIM_CheckType, /*MI*/0, /*Op*/6, /*Type*/GILLT_v4s32,
        GIM_CheckType, /*MI*/0, /*Op*/7, /*Type*/GILLT_s32,
        GIM_CheckRegBankForClass, /*MI*/0, /*Op*/0, /*RC*/GIMT_Encode2(AMDGPU::VReg_128RegClassID),
        // MIs[0] clamp
        // No operand predicates
        GIM_CheckComplexPattern, /*MI*/0, /*Op*/2, /*Renderer*/GIMT_Encode2(0), GIMT_Encode2(GICP_gi_vop3pmodsneg),
        GIM_CheckComplexPattern, /*MI*/0, /*Op*/4, /*Renderer*/GIMT_Encode2(1), GIMT_Encode2(GICP_gi_vop3pmodsneg),
        GIM_CheckComplexPattern, /*MI*/0, /*Op*/7, /*Renderer*/GIMT_Encode2(2), GIMT_Encode2(GICP_gi_swmmacindex8),
        // (intrinsic_wo_chain:{ *:[v4i32] } 2793:{ *:[iPTR] }, (VOP3PModsNeg:{ *:[i1] } i32:{ *:[i32] }:$src0_modifiers), i32:{ *:[i32] }:$src0, (VOP3PModsNeg:{ *:[i1] } i32:{ *:[i32] }:$src1_modifiers), v2i32:{ *:[v2i32] }:$src1, v4i32:{ *:[v4i32] }:$srcTiedDef, (SWMMACIndex8:{ *:[i32] } i32:{ *:[i32] }:$src2, i32:{ *:[i32] }:$index_key_8bit), i1:{ *:[i1] }:$clamp)  =>  (V_SWMMAC_I32_16X16X32_IU8_w64_twoaddr:{ *:[v4i32] } i32:{ *:[i32] }:$src0_modifiers, i32:{ *:[i32] }:$src0, i32:{ *:[i32] }:$src1_modifiers, v2i32:{ *:[v2i32] }:$src1, v4i32:{ *:[v4i32] }:$srcTiedDef, i32:{ *:[i32] }:$src2, i32:{ *:[i32] }:$index_key_8bit, i1:{ *:[i1] }:$clamp)
        GIR_BuildMI, /*InsnID*/0, /*Opcode*/GIMT_Encode2(AMDGPU::V_SWMMAC_I32_16X16X32_IU8_w64_twoaddr),
        GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/0, // DstI[vdst]
        GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/0, // src0_modifiers
        GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/3, // src0
        GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(1), /*SubOperand*/0, // src1_modifiers
        GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/5, // src1
        GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/6, // srcTiedDef
        GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(2), /*SubOperand*/0, // src2
        GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(2), /*SubOperand*/1, // index_key_8bit
        GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/8, // clamp
        GIR_AddImm8, /*InsnID*/0, /*Imm*/0,
        GIR_ConstrainSelectedInstOperands, /*InsnID*/0,
        GIR_EraseFromParent, /*InsnID*/0,
        // GIR_Coverage, 2394,
        GIR_Done,
      // Label 3624: @237798
      GIM_Try, /*On fail goto*//*Label 3625*/ GIMT_Encode4(237909), // Rule ID 2395 //
        GIM_CheckFeatures, GIMT_Encode2(GIFBS_isGFX12Plus_isWave64),
        GIM_CheckIntrinsicID, /*MI*/0, /*Op*/1, GIMT_Encode2(Intrinsic::amdgcn_swmmac_i32_16x16x32_iu4),
        GIM_CheckType, /*MI*/0, /*Op*/0, /*Type*/GILLT_v4s32,
        GIM_CheckType, /*MI*/0, /*Op*/3, /*Type*/GILLT_s32,
        GIM_CheckType, /*MI*/0, /*Op*/5, /*Type*/GILLT_s32,
        GIM_CheckType, /*MI*/0, /*Op*/6, /*Type*/GILLT_v4s32,
        GIM_CheckType, /*MI*/0, /*Op*/7, /*Type*/GILLT_s32,
        GIM_CheckRegBankForClass, /*MI*/0, /*Op*/0, /*RC*/GIMT_Encode2(AMDGPU::VReg_128RegClassID),
        // MIs[0] clamp
        // No operand predicates
        GIM_CheckComplexPattern, /*MI*/0, /*Op*/2, /*Renderer*/GIMT_Encode2(0), GIMT_Encode2(GICP_gi_vop3pmodsneg),
        GIM_CheckComplexPattern, /*MI*/0, /*Op*/4, /*Renderer*/GIMT_Encode2(1), GIMT_Encode2(GICP_gi_vop3pmodsneg),
        GIM_CheckComplexPattern, /*MI*/0, /*Op*/7, /*Renderer*/GIMT_Encode2(2), GIMT_Encode2(GICP_gi_swmmacindex16),
        // (intrinsic_wo_chain:{ *:[v4i32] } 2792:{ *:[iPTR] }, (VOP3PModsNeg:{ *:[i1] } i32:{ *:[i32] }:$src0_modifiers), i32:{ *:[i32] }:$src0, (VOP3PModsNeg:{ *:[i1] } i32:{ *:[i32] }:$src1_modifiers), i32:{ *:[i32] }:$src1, v4i32:{ *:[v4i32] }:$srcTiedDef, (SWMMACIndex16:{ *:[i32] } i32:{ *:[i32] }:$src2, i32:{ *:[i32] }:$index_key_16bit), i1:{ *:[i1] }:$clamp)  =>  (V_SWMMAC_I32_16X16X32_IU4_w64_twoaddr:{ *:[v4i32] } i32:{ *:[i32] }:$src0_modifiers, i32:{ *:[i32] }:$src0, i32:{ *:[i32] }:$src1_modifiers, i32:{ *:[i32] }:$src1, v4i32:{ *:[v4i32] }:$srcTiedDef, i32:{ *:[i32] }:$src2, i32:{ *:[i32] }:$index_key_16bit, i1:{ *:[i1] }:$clamp)
        GIR_BuildMI, /*InsnID*/0, /*Opcode*/GIMT_Encode2(AMDGPU::V_SWMMAC_I32_16X16X32_IU4_w64_twoaddr),
        GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/0, // DstI[vdst]
        GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/0, // src0_modifiers
        GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/3, // src0
        GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(1), /*SubOperand*/0, // src1_modifiers
        GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/5, // src1
        GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/6, // srcTiedDef
        GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(2), /*SubOperand*/0, // src2
        GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(2), /*SubOperand*/1, // index_key_16bit
        GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/8, // clamp
        GIR_AddImm8, /*InsnID*/0, /*Imm*/0,
        GIR_ConstrainSelectedInstOperands, /*InsnID*/0,
        GIR_EraseFromParent, /*InsnID*/0,
        // GIR_Coverage, 2395,
        GIR_Done,
      // Label 3625: @237909
      GIM_Try, /*On fail goto*//*Label 3626*/ GIMT_Encode4(238020), // Rule ID 2396 //
        GIM_CheckFeatures, GIMT_Encode2(GIFBS_isGFX12Plus_isWave64),
        GIM_CheckIntrinsicID, /*MI*/0, /*Op*/1, GIMT_Encode2(Intrinsic::amdgcn_swmmac_i32_16x16x64_iu4),
        GIM_CheckType, /*MI*/0, /*Op*/0, /*Type*/GILLT_v4s32,
        GIM_CheckType, /*MI*/0, /*Op*/3, /*Type*/GILLT_s32,
        GIM_CheckType, /*MI*/0, /*Op*/5, /*Type*/GILLT_v2s32,
        GIM_CheckType, /*MI*/0, /*Op*/6, /*Type*/GILLT_v4s32,
        GIM_CheckType, /*MI*/0, /*Op*/7, /*Type*/GILLT_s32,
        GIM_CheckRegBankForClass, /*MI*/0, /*Op*/0, /*RC*/GIMT_Encode2(AMDGPU::VReg_128RegClassID),
        // MIs[0] clamp
        // No operand predicates
        GIM_CheckComplexPattern, /*MI*/0, /*Op*/2, /*Renderer*/GIMT_Encode2(0), GIMT_Encode2(GICP_gi_vop3pmodsneg),
        GIM_CheckComplexPattern, /*MI*/0, /*Op*/4, /*Renderer*/GIMT_Encode2(1), GIMT_Encode2(GICP_gi_vop3pmodsneg),
        GIM_CheckComplexPattern, /*MI*/0, /*Op*/7, /*Renderer*/GIMT_Encode2(2), GIMT_Encode2(GICP_gi_swmmacindex16),
        // (intrinsic_wo_chain:{ *:[v4i32] } 2794:{ *:[iPTR] }, (VOP3PModsNeg:{ *:[i1] } i32:{ *:[i32] }:$src0_modifiers), i32:{ *:[i32] }:$src0, (VOP3PModsNeg:{ *:[i1] } i32:{ *:[i32] }:$src1_modifiers), v2i32:{ *:[v2i32] }:$src1, v4i32:{ *:[v4i32] }:$srcTiedDef, (SWMMACIndex16:{ *:[i32] } i32:{ *:[i32] }:$src2, i32:{ *:[i32] }:$index_key_16bit), i1:{ *:[i1] }:$clamp)  =>  (V_SWMMAC_I32_16X16X64_IU4_w64_twoaddr:{ *:[v4i32] } i32:{ *:[i32] }:$src0_modifiers, i32:{ *:[i32] }:$src0, i32:{ *:[i32] }:$src1_modifiers, v2i32:{ *:[v2i32] }:$src1, v4i32:{ *:[v4i32] }:$srcTiedDef, i32:{ *:[i32] }:$src2, i32:{ *:[i32] }:$index_key_16bit, i1:{ *:[i1] }:$clamp)
        GIR_BuildMI, /*InsnID*/0, /*Opcode*/GIMT_Encode2(AMDGPU::V_SWMMAC_I32_16X16X64_IU4_w64_twoaddr),
        GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/0, // DstI[vdst]
        GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/0, // src0_modifiers
        GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/3, // src0
        GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(1), /*SubOperand*/0, // src1_modifiers
        GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/5, // src1
        GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/6, // srcTiedDef
        GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(2), /*SubOperand*/0, // src2
        GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(2), /*SubOperand*/1, // index_key_16bit
        GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/8, // clamp
        GIR_AddImm8, /*InsnID*/0, /*Imm*/0,
        GIR_ConstrainSelectedInstOperands, /*InsnID*/0,
        GIR_EraseFromParent, /*InsnID*/0,
        // GIR_Coverage, 2396,
        GIR_Done,
      // Label 3626: @238020
      GIM_Try, /*On fail goto*//*Label 3627*/ GIMT_Encode4(238118), // Rule ID 2363 //
        GIM_CheckFeatures, GIMT_Encode2(GIFBS_isGFX12Plus_isWave32),
        GIM_CheckIntrinsicID, /*MI*/0, /*Op*/1, GIMT_Encode2(Intrinsic::amdgcn_swmmac_i32_16x16x64_iu4),
        GIM_CheckType, /*MI*/0, /*Op*/0, /*Type*/GILLT_v8s32,
        GIM_CheckType, /*MI*/0, /*Op*/3, /*Type*/GILLT_v2s32,
        GIM_CheckType, /*MI*/0, /*Op*/5, /*Type*/GILLT_v4s32,
        GIM_CheckType, /*MI*/0, /*Op*/6, /*Type*/GILLT_v8s32,
        GIM_CheckType, /*MI*/0, /*Op*/7, /*Type*/GILLT_s32,
        GIM_CheckRegBankForClass, /*MI*/0, /*Op*/0, /*RC*/GIMT_Encode2(AMDGPU::VReg_256RegClassID),
        // MIs[0] clamp
        // No operand predicates
        GIM_CheckComplexPattern, /*MI*/0, /*Op*/2, /*Renderer*/GIMT_Encode2(0), GIMT_Encode2(GICP_gi_vop3pmodsneg),
        GIM_CheckComplexPattern, /*MI*/0, /*Op*/4, /*Renderer*/GIMT_Encode2(1), GIMT_Encode2(GICP_gi_vop3pmodsneg),
        // (intrinsic_wo_chain:{ *:[v8i32] } 2794:{ *:[iPTR] }, (VOP3PModsNeg:{ *:[i1] } i32:{ *:[i32] }:$src0_modifiers), v2i32:{ *:[v2i32] }:$src0, (VOP3PModsNeg:{ *:[i1] } i32:{ *:[i32] }:$src1_modifiers), v4i32:{ *:[v4i32] }:$src1, v8i32:{ *:[v8i32] }:$srcTiedDef, i32:{ *:[i32] }:$src2, i1:{ *:[i1] }:$clamp)  =>  (V_SWMMAC_I32_16X16X64_IU4_w32_twoaddr:{ *:[v8i32] } i32:{ *:[i32] }:$src0_modifiers, v2i32:{ *:[v2i32] }:$src0, i32:{ *:[i32] }:$src1_modifiers, v4i32:{ *:[v4i32] }:$src1, v8i32:{ *:[v8i32] }:$srcTiedDef, i32:{ *:[i32] }:$src2, i1:{ *:[i1] }:$clamp)
        GIR_BuildMI, /*InsnID*/0, /*Opcode*/GIMT_Encode2(AMDGPU::V_SWMMAC_I32_16X16X64_IU4_w32_twoaddr),
        GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/0, // DstI[vdst]
        GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/0, // src0_modifiers
        GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/3, // src0
        GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(1), /*SubOperand*/0, // src1_modifiers
        GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/5, // src1
        GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/6, // srcTiedDef
        GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/7, // src2
        GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/8, // clamp
        GIR_AddImm8, /*InsnID*/0, /*Imm*/0,
        GIR_ConstrainSelectedInstOperands, /*InsnID*/0,
        GIR_EraseFromParent, /*InsnID*/0,
        // GIR_Coverage, 2363,
        GIR_Done,
      // Label 3627: @238118
      GIM_Reject,
    // Label 3621: @238119
    GIM_Reject,
    // Label 35: @238120
    GIM_Try, /*On fail goto*//*Label 3628*/ GIMT_Encode4(238212),
      GIM_CheckNumOperands, /*MI*/0, /*Expected*/1,
      GIM_Try, /*On fail goto*//*Label 3629*/ GIMT_Encode4(238147), // Rule ID 183 //
        GIM_CheckIntrinsicID, /*MI*/0, /*Op*/0, GIMT_Encode2(Intrinsic::amdgcn_s_barrier),
        // (intrinsic_void 2655:{ *:[iPTR] })  =>  (S_BARRIER)
        GIR_BuildMI, /*InsnID*/0, /*Opcode*/GIMT_Encode2(AMDGPU::S_BARRIER),
        GIR_ConstrainSelectedInstOperands, /*InsnID*/0,
        GIR_EraseFromParent, /*InsnID*/0,
        // GIR_Coverage, 183,
        GIR_Done,
      // Label 3629: @238147
      GIM_Try, /*On fail goto*//*Label 3630*/ GIMT_Encode4(238166), // Rule ID 1122 //
        GIM_CheckIntrinsicID, /*MI*/0, /*Op*/0, GIMT_Encode2(Intrinsic::amdgcn_wave_barrier),
        // (intrinsic_void 2804:{ *:[iPTR] })  =>  (WAVE_BARRIER)
        GIR_BuildMI, /*InsnID*/0, /*Opcode*/GIMT_Encode2(AMDGPU::WAVE_BARRIER),
        GIR_ConstrainSelectedInstOperands, /*InsnID*/0,
        GIR_EraseFromParent, /*InsnID*/0,
        // GIR_Coverage, 1122,
        GIR_Done,
      // Label 3630: @238166
      GIM_Try, /*On fail goto*//*Label 3631*/ GIMT_Encode4(238189), // Rule ID 1131 //
        GIM_CheckIntrinsicID, /*MI*/0, /*Op*/0, GIMT_Encode2(Intrinsic::amdgcn_unreachable),
        // (intrinsic_void 2802:{ *:[iPTR] })  =>  (SI_MASKED_UNREACHABLE)
        GIR_BuildMI, /*InsnID*/0, /*Opcode*/GIMT_Encode2(AMDGPU::SI_MASKED_UNREACHABLE),
        GIR_MergeMemOperands, /*InsnID*/0, /*NumInsns*/1, /*MergeInsnID's*/0,
        GIR_ConstrainSelectedInstOperands, /*InsnID*/0,
        GIR_EraseFromParent, /*InsnID*/0,
        // GIR_Coverage, 1131,
        GIR_Done,
      // Label 3631: @238189
      GIM_Try, /*On fail goto*//*Label 3632*/ GIMT_Encode4(238211), // Rule ID 1643 //
        GIM_CheckIntrinsicID, /*MI*/0, /*Op*/0, GIMT_Encode2(Intrinsic::amdgcn_endpgm),
        // (intrinsic_void 1953:{ *:[iPTR] })  =>  (S_ENDPGM 0:{ *:[i16] })
        GIR_BuildMI, /*InsnID*/0, /*Opcode*/GIMT_Encode2(AMDGPU::S_ENDPGM),
        GIR_AddImm8, /*InsnID*/0, /*Imm*/0,
        GIR_ConstrainSelectedInstOperands, /*InsnID*/0,
        GIR_EraseFromParent, /*InsnID*/0,
        // GIR_Coverage, 1643,
        GIR_Done,
      // Label 3632: @238211
      GIM_Reject,
    // Label 3628: @238212
    GIM_Try, /*On fail goto*//*Label 3633*/ GIMT_Encode4(238396),
      GIM_CheckNumOperands, /*MI*/0, /*Expected*/2,
      GIM_Try, /*On fail goto*//*Label 3634*/ GIMT_Encode4(238246), // Rule ID 43 //
        GIM_CheckIntrinsicID, /*MI*/0, /*Op*/0, GIMT_Encode2(Intrinsic::amdgcn_s_barrier_signal),
        // MIs[0] src0
        GIM_CheckIsImm, /*MI*/0, /*Op*/1,
        // (intrinsic_void 2659:{ *:[iPTR] }, (timm:{ *:[i32] }):$src0)  =>  (S_BARRIER_SIGNAL_IMM (timm:{ *:[i32] }):$src0)
        GIR_BuildMI, /*InsnID*/0, /*Opcode*/GIMT_Encode2(AMDGPU::S_BARRIER_SIGNAL_IMM),
        GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/1, // src0
        GIR_ConstrainSelectedInstOperands, /*InsnID*/0,
        GIR_EraseFromParent, /*InsnID*/0,
        // GIR_Coverage, 43,
        GIR_Done,
      // Label 3634: @238246
      GIM_Try, /*On fail goto*//*Label 3635*/ GIMT_Encode4(238272), // Rule ID 184 //
        GIM_CheckIntrinsicID, /*MI*/0, /*Op*/0, GIMT_Encode2(Intrinsic::amdgcn_s_barrier_wait),
        // MIs[0] simm16
        GIM_CheckIsImm, /*MI*/0, /*Op*/1,
        // (intrinsic_void 2663:{ *:[iPTR] }, (timm:{ *:[i16] }):$simm16)  =>  (S_BARRIER_WAIT (timm:{ *:[i16] }):$simm16)
        GIR_BuildMI, /*InsnID*/0, /*Opcode*/GIMT_Encode2(AMDGPU::S_BARRIER_WAIT),
        GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/1, // simm16
        GIR_ConstrainSelectedInstOperands, /*InsnID*/0,
        GIR_EraseFromParent, /*InsnID*/0,
        // GIR_Coverage, 184,
        GIR_Done,
      // Label 3635: @238272
      GIM_Try, /*On fail goto*//*Label 3636*/ GIMT_Encode4(238298), // Rule ID 1123 //
        GIM_CheckIntrinsicID, /*MI*/0, /*Op*/0, GIMT_Encode2(Intrinsic::amdgcn_sched_barrier),
        // MIs[0] mask
        GIM_CheckIsImm, /*MI*/0, /*Op*/1,
        // (intrinsic_void 2705:{ *:[iPTR] }, (timm:{ *:[i32] }):$mask)  =>  (SCHED_BARRIER (timm:{ *:[i32] }):$mask)
        GIR_BuildMI, /*InsnID*/0, /*Opcode*/GIMT_Encode2(AMDGPU::SCHED_BARRIER),
        GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/1, // mask
        GIR_ConstrainSelectedInstOperands, /*InsnID*/0,
        GIR_EraseFromParent, /*InsnID*/0,
        // GIR_Coverage, 1123,
        GIR_Done,
      // Label 3636: @238298
      GIM_Try, /*On fail goto*//*Label 3637*/ GIMT_Encode4(238324), // Rule ID 1125 //
        GIM_CheckIntrinsicID, /*MI*/0, /*Op*/0, GIMT_Encode2(Intrinsic::amdgcn_iglp_opt),
        // MIs[0] mask
        GIM_CheckIsImm, /*MI*/0, /*Op*/1,
        // (intrinsic_void 1991:{ *:[iPTR] }, (timm:{ *:[i32] }):$mask)  =>  (IGLP_OPT (timm:{ *:[i32] }):$mask)
        GIR_BuildMI, /*InsnID*/0, /*Opcode*/GIMT_Encode2(AMDGPU::IGLP_OPT),
        GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/1, // mask
        GIR_ConstrainSelectedInstOperands, /*InsnID*/0,
        GIR_EraseFromParent, /*InsnID*/0,
        // GIR_Coverage, 1125,
        GIR_Done,
      // Label 3637: @238324
      GIM_Try, /*On fail goto*//*Label 3638*/ GIMT_Encode4(238353), // Rule ID 1132 //
        GIM_CheckIntrinsicID, /*MI*/0, /*Op*/0, GIMT_Encode2(Intrinsic::amdgcn_init_exec),
        // MIs[0] src
        GIM_CheckIsImm, /*MI*/0, /*Op*/1,
        // (intrinsic_void 2513:{ *:[iPTR] }, (timm:{ *:[i64] }):$src)  =>  (SI_INIT_EXEC (timm:{ *:[i64] }):$src)
        GIR_BuildMI, /*InsnID*/0, /*Opcode*/GIMT_Encode2(AMDGPU::SI_INIT_EXEC),
        GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/1, // src
        GIR_SetImplicitDefDead, /*InsnID*/0, /*OpIdx for AMDGPU::EXEC*/0,
        GIR_ConstrainSelectedInstOperands, /*InsnID*/0,
        GIR_EraseFromParent, /*InsnID*/0,
        // GIR_Coverage, 1132,
        GIR_Done,
      // Label 3638: @238353
      GIM_Try, /*On fail goto*//*Label 3639*/ GIMT_Encode4(238395), // Rule ID 41 //
        GIM_CheckIntrinsicID, /*MI*/0, /*Op*/0, GIMT_Encode2(Intrinsic::amdgcn_s_barrier_signal_var),
        GIM_CheckType, /*MI*/0, /*Op*/1, /*Type*/GILLT_s32,
        GIM_CheckRegBankForClass, /*MI*/0, /*Op*/1, /*RC*/GIMT_Encode2(AMDGPU::M0_CLASSRegClassID),
        // (intrinsic_void 2662:{ *:[iPTR] }, M0:{ *:[i32] })  =>  (S_BARRIER_SIGNAL_M0)
        GIR_BuildMI, /*InsnID*/1, /*Opcode*/GIMT_Encode2(TargetOpcode::COPY),
        GIR_AddRegister, /*InsnID*/1, GIMT_Encode2(AMDGPU::M0), /*AddRegisterRegFlags*/GIMT_Encode2(RegState::Define),
        GIR_Copy, /*NewInsnID*/1, /*OldInsnID*/0, /*OpIdx*/1, // M0
        GIR_BuildMI, /*InsnID*/0, /*Opcode*/GIMT_Encode2(AMDGPU::S_BARRIER_SIGNAL_M0),
        GIR_ConstrainSelectedInstOperands, /*InsnID*/0,
        GIR_EraseFromParent, /*InsnID*/0,
        // GIR_Coverage, 41,
        GIR_Done,
      // Label 3639: @238395
      GIM_Reject,
    // Label 3633: @238396
    GIM_Try, /*On fail goto*//*Label 3640*/ GIMT_Encode4(239490),
      GIM_CheckNumOperands, /*MI*/0, /*Expected*/3,
      GIM_Try, /*On fail goto*//*Label 3641*/ GIMT_Encode4(238472), // Rule ID 3261 //
        GIM_CheckFeatures, GIMT_Encode2(GIFBS_isGFX12Plus_isWave32),
        GIM_CheckIntrinsicID, /*MI*/0, /*Op*/1, GIMT_Encode2(Intrinsic::amdgcn_global_load_tr),
        GIM_CheckType, /*MI*/0, /*Op*/0, /*Type*/GILLT_v2s32,
        GIM_CheckRegBankForClass, /*MI*/0, /*Op*/0, /*RC*/GIMT_Encode2(AMDGPU::AV_64RegClassID),
        GIM_CheckPointerToAny, /*MI*/0, /*Op*/2, /*SizeInBits*/0,
        GIM_CheckComplexPattern, /*MI*/0, /*Op*/2, /*Renderer*/GIMT_Encode2(0), GIMT_Encode2(GICP_gi_global_saddr),
        // (intrinsic_w_chain:{ *:[v2i32] } 1986:{ *:[iPTR] }, (GlobalSAddr:{ *:[iPTR] } SReg_64:{ *:[i64] }:$saddr, VGPR_32:{ *:[i32] }:$voffset, i32:{ *:[i32] }:$offset))  =>  (GLOBAL_LOAD_TR_B64_w32_SADDR:{ *:[v2i32] } ?:{ *:[i64] }:$saddr, ?:{ *:[i32] }:$voffset, ?:{ *:[i32] }:$offset, 0:{ *:[i32] })
        GIR_BuildMI, /*InsnID*/0, /*Opcode*/GIMT_Encode2(AMDGPU::GLOBAL_LOAD_TR_B64_w32_SADDR),
        GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/0, // DstI[vdst]
        GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/0, // saddr
        GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/1, // voffset
        GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/2, // offset
        GIR_AddImm8, /*InsnID*/0, /*Imm*/0,
        GIR_MergeMemOperands, /*InsnID*/0, /*NumInsns*/1, /*MergeInsnID's*/0,
        GIR_ConstrainSelectedInstOperands, /*InsnID*/0,
        GIR_EraseFromParent, /*InsnID*/0,
        // GIR_Coverage, 3261,
        GIR_Done,
      // Label 3641: @238472
      GIM_Try, /*On fail goto*//*Label 3642*/ GIMT_Encode4(238540), // Rule ID 3263 //
        GIM_CheckFeatures, GIMT_Encode2(GIFBS_isGFX12Plus_isWave32),
        GIM_CheckIntrinsicID, /*MI*/0, /*Op*/1, GIMT_Encode2(Intrinsic::amdgcn_global_load_tr),
        GIM_CheckType, /*MI*/0, /*Op*/0, /*Type*/GILLT_v8s16,
        GIM_CheckRegBankForClass, /*MI*/0, /*Op*/0, /*RC*/GIMT_Encode2(AMDGPU::AV_128RegClassID),
        GIM_CheckPointerToAny, /*MI*/0, /*Op*/2, /*SizeInBits*/0,
        GIM_CheckComplexPattern, /*MI*/0, /*Op*/2, /*Renderer*/GIMT_Encode2(0), GIMT_Encode2(GICP_gi_global_saddr),
        // (intrinsic_w_chain:{ *:[v8i16] } 1986:{ *:[iPTR] }, (GlobalSAddr:{ *:[iPTR] } SReg_64:{ *:[i64] }:$saddr, VGPR_32:{ *:[i32] }:$voffset, i32:{ *:[i32] }:$offset))  =>  (GLOBAL_LOAD_TR_B128_w32_SADDR:{ *:[v8i16] } ?:{ *:[i64] }:$saddr, ?:{ *:[i32] }:$voffset, ?:{ *:[i32] }:$offset, 0:{ *:[i32] })
        GIR_BuildMI, /*InsnID*/0, /*Opcode*/GIMT_Encode2(AMDGPU::GLOBAL_LOAD_TR_B128_w32_SADDR),
        GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/0, // DstI[vdst]
        GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/0, // saddr
        GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/1, // voffset
        GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/2, // offset
        GIR_AddImm8, /*InsnID*/0, /*Imm*/0,
        GIR_MergeMemOperands, /*InsnID*/0, /*NumInsns*/1, /*MergeInsnID's*/0,
        GIR_ConstrainSelectedInstOperands, /*InsnID*/0,
        GIR_EraseFromParent, /*InsnID*/0,
        // GIR_Coverage, 3263,
        GIR_Done,
      // Label 3642: @238540
      GIM_Try, /*On fail goto*//*Label 3643*/ GIMT_Encode4(238608), // Rule ID 3265 //
        GIM_CheckFeatures, GIMT_Encode2(GIFBS_isGFX12Plus_isWave32),
        GIM_CheckIntrinsicID, /*MI*/0, /*Op*/1, GIMT_Encode2(Intrinsic::amdgcn_global_load_tr),
        GIM_CheckType, /*MI*/0, /*Op*/0, /*Type*/GILLT_v8s16,
        GIM_CheckRegBankForClass, /*MI*/0, /*Op*/0, /*RC*/GIMT_Encode2(AMDGPU::AV_128RegClassID),
        GIM_CheckPointerToAny, /*MI*/0, /*Op*/2, /*SizeInBits*/0,
        GIM_CheckComplexPattern, /*MI*/0, /*Op*/2, /*Renderer*/GIMT_Encode2(0), GIMT_Encode2(GICP_gi_global_saddr),
        // (intrinsic_w_chain:{ *:[v8f16] } 1986:{ *:[iPTR] }, (GlobalSAddr:{ *:[iPTR] } SReg_64:{ *:[i64] }:$saddr, VGPR_32:{ *:[i32] }:$voffset, i32:{ *:[i32] }:$offset))  =>  (GLOBAL_LOAD_TR_B128_w32_SADDR:{ *:[v8f16] } ?:{ *:[i64] }:$saddr, ?:{ *:[i32] }:$voffset, ?:{ *:[i32] }:$offset, 0:{ *:[i32] })
        GIR_BuildMI, /*InsnID*/0, /*Opcode*/GIMT_Encode2(AMDGPU::GLOBAL_LOAD_TR_B128_w32_SADDR),
        GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/0, // DstI[vdst]
        GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/0, // saddr
        GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/1, // voffset
        GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/2, // offset
        GIR_AddImm8, /*InsnID*/0, /*Imm*/0,
        GIR_MergeMemOperands, /*InsnID*/0, /*NumInsns*/1, /*MergeInsnID's*/0,
        GIR_ConstrainSelectedInstOperands, /*InsnID*/0,
        GIR_EraseFromParent, /*InsnID*/0,
        // GIR_Coverage, 3265,
        GIR_Done,
      // Label 3643: @238608
      GIM_Try, /*On fail goto*//*Label 3644*/ GIMT_Encode4(238676), // Rule ID 3267 //
        GIM_CheckFeatures, GIMT_Encode2(GIFBS_isGFX12Plus_isWave32),
        GIM_CheckIntrinsicID, /*MI*/0, /*Op*/1, GIMT_Encode2(Intrinsic::amdgcn_global_load_tr),
        GIM_CheckType, /*MI*/0, /*Op*/0, /*Type*/GILLT_v8s16,
        GIM_CheckRegBankForClass, /*MI*/0, /*Op*/0, /*RC*/GIMT_Encode2(AMDGPU::AV_128RegClassID),
        GIM_CheckPointerToAny, /*MI*/0, /*Op*/2, /*SizeInBits*/0,
        GIM_CheckComplexPattern, /*MI*/0, /*Op*/2, /*Renderer*/GIMT_Encode2(0), GIMT_Encode2(GICP_gi_global_saddr),
        // (intrinsic_w_chain:{ *:[v8bf16] } 1986:{ *:[iPTR] }, (GlobalSAddr:{ *:[iPTR] } SReg_64:{ *:[i64] }:$saddr, VGPR_32:{ *:[i32] }:$voffset, i32:{ *:[i32] }:$offset))  =>  (GLOBAL_LOAD_TR_B128_w32_SADDR:{ *:[v8bf16] } ?:{ *:[i64] }:$saddr, ?:{ *:[i32] }:$voffset, ?:{ *:[i32] }:$offset, 0:{ *:[i32] })
        GIR_BuildMI, /*InsnID*/0, /*Opcode*/GIMT_Encode2(AMDGPU::GLOBAL_LOAD_TR_B128_w32_SADDR),
        GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/0, // DstI[vdst]
        GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/0, // saddr
        GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/1, // voffset
        GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/2, // offset
        GIR_AddImm8, /*InsnID*/0, /*Imm*/0,
        GIR_MergeMemOperands, /*InsnID*/0, /*NumInsns*/1, /*MergeInsnID's*/0,
        GIR_ConstrainSelectedInstOperands, /*InsnID*/0,
        GIR_EraseFromParent, /*InsnID*/0,
        // GIR_Coverage, 3267,
        GIR_Done,
      // Label 3644: @238676
      GIM_Try, /*On fail goto*//*Label 3645*/ GIMT_Encode4(238744), // Rule ID 3269 //
        GIM_CheckFeatures, GIMT_Encode2(GIFBS_isGFX12Plus_isWave64),
        GIM_CheckIntrinsicID, /*MI*/0, /*Op*/1, GIMT_Encode2(Intrinsic::amdgcn_global_load_tr),
        GIM_CheckType, /*MI*/0, /*Op*/0, /*Type*/GILLT_s32,
        GIM_CheckRegBankForClass, /*MI*/0, /*Op*/0, /*RC*/GIMT_Encode2(AMDGPU::AV_32RegClassID),
        GIM_CheckPointerToAny, /*MI*/0, /*Op*/2, /*SizeInBits*/0,
        GIM_CheckComplexPattern, /*MI*/0, /*Op*/2, /*Renderer*/GIMT_Encode2(0), GIMT_Encode2(GICP_gi_global_saddr),
        // (intrinsic_w_chain:{ *:[i32] } 1986:{ *:[iPTR] }, (GlobalSAddr:{ *:[iPTR] } SReg_64:{ *:[i64] }:$saddr, VGPR_32:{ *:[i32] }:$voffset, i32:{ *:[i32] }:$offset))  =>  (GLOBAL_LOAD_TR_B64_w64_SADDR:{ *:[i32] } ?:{ *:[i64] }:$saddr, ?:{ *:[i32] }:$voffset, ?:{ *:[i32] }:$offset, 0:{ *:[i32] })
        GIR_BuildMI, /*InsnID*/0, /*Opcode*/GIMT_Encode2(AMDGPU::GLOBAL_LOAD_TR_B64_w64_SADDR),
        GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/0, // DstI[vdst]
        GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/0, // saddr
        GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/1, // voffset
        GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/2, // offset
        GIR_AddImm8, /*InsnID*/0, /*Imm*/0,
        GIR_MergeMemOperands, /*InsnID*/0, /*NumInsns*/1, /*MergeInsnID's*/0,
        GIR_ConstrainSelectedInstOperands, /*InsnID*/0,
        GIR_EraseFromParent, /*InsnID*/0,
        // GIR_Coverage, 3269,
        GIR_Done,
      // Label 3645: @238744
      GIM_Try, /*On fail goto*//*Label 3646*/ GIMT_Encode4(238812), // Rule ID 3271 //
        GIM_CheckFeatures, GIMT_Encode2(GIFBS_isGFX12Plus_isWave64),
        GIM_CheckIntrinsicID, /*MI*/0, /*Op*/1, GIMT_Encode2(Intrinsic::amdgcn_global_load_tr),
        GIM_CheckType, /*MI*/0, /*Op*/0, /*Type*/GILLT_v4s16,
        GIM_CheckRegBankForClass, /*MI*/0, /*Op*/0, /*RC*/GIMT_Encode2(AMDGPU::AV_64RegClassID),
        GIM_CheckPointerToAny, /*MI*/0, /*Op*/2, /*SizeInBits*/0,
        GIM_CheckComplexPattern, /*MI*/0, /*Op*/2, /*Renderer*/GIMT_Encode2(0), GIMT_Encode2(GICP_gi_global_saddr),
        // (intrinsic_w_chain:{ *:[v4i16] } 1986:{ *:[iPTR] }, (GlobalSAddr:{ *:[iPTR] } SReg_64:{ *:[i64] }:$saddr, VGPR_32:{ *:[i32] }:$voffset, i32:{ *:[i32] }:$offset))  =>  (GLOBAL_LOAD_TR_B128_w64_SADDR:{ *:[v4i16] } ?:{ *:[i64] }:$saddr, ?:{ *:[i32] }:$voffset, ?:{ *:[i32] }:$offset, 0:{ *:[i32] })
        GIR_BuildMI, /*InsnID*/0, /*Opcode*/GIMT_Encode2(AMDGPU::GLOBAL_LOAD_TR_B128_w64_SADDR),
        GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/0, // DstI[vdst]
        GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/0, // saddr
        GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/1, // voffset
        GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/2, // offset
        GIR_AddImm8, /*InsnID*/0, /*Imm*/0,
        GIR_MergeMemOperands, /*InsnID*/0, /*NumInsns*/1, /*MergeInsnID's*/0,
        GIR_ConstrainSelectedInstOperands, /*InsnID*/0,
        GIR_EraseFromParent, /*InsnID*/0,
        // GIR_Coverage, 3271,
        GIR_Done,
      // Label 3646: @238812
      GIM_Try, /*On fail goto*//*Label 3647*/ GIMT_Encode4(238880), // Rule ID 3273 //
        GIM_CheckFeatures, GIMT_Encode2(GIFBS_isGFX12Plus_isWave64),
        GIM_CheckIntrinsicID, /*MI*/0, /*Op*/1, GIMT_Encode2(Intrinsic::amdgcn_global_load_tr),
        GIM_CheckType, /*MI*/0, /*Op*/0, /*Type*/GILLT_v4s16,
        GIM_CheckRegBankForClass, /*MI*/0, /*Op*/0, /*RC*/GIMT_Encode2(AMDGPU::AV_64RegClassID),
        GIM_CheckPointerToAny, /*MI*/0, /*Op*/2, /*SizeInBits*/0,
        GIM_CheckComplexPattern, /*MI*/0, /*Op*/2, /*Renderer*/GIMT_Encode2(0), GIMT_Encode2(GICP_gi_global_saddr),
        // (intrinsic_w_chain:{ *:[v4f16] } 1986:{ *:[iPTR] }, (GlobalSAddr:{ *:[iPTR] } SReg_64:{ *:[i64] }:$saddr, VGPR_32:{ *:[i32] }:$voffset, i32:{ *:[i32] }:$offset))  =>  (GLOBAL_LOAD_TR_B128_w64_SADDR:{ *:[v4f16] } ?:{ *:[i64] }:$saddr, ?:{ *:[i32] }:$voffset, ?:{ *:[i32] }:$offset, 0:{ *:[i32] })
        GIR_BuildMI, /*InsnID*/0, /*Opcode*/GIMT_Encode2(AMDGPU::GLOBAL_LOAD_TR_B128_w64_SADDR),
        GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/0, // DstI[vdst]
        GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/0, // saddr
        GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/1, // voffset
        GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/2, // offset
        GIR_AddImm8, /*InsnID*/0, /*Imm*/0,
        GIR_MergeMemOperands, /*InsnID*/0, /*NumInsns*/1, /*MergeInsnID's*/0,
        GIR_ConstrainSelectedInstOperands, /*InsnID*/0,
        GIR_EraseFromParent, /*InsnID*/0,
        // GIR_Coverage, 3273,
        GIR_Done,
      // Label 3647: @238880
      GIM_Try, /*On fail goto*//*Label 3648*/ GIMT_Encode4(238948), // Rule ID 3275 //
        GIM_CheckFeatures, GIMT_Encode2(GIFBS_isGFX12Plus_isWave64),
        GIM_CheckIntrinsicID, /*MI*/0, /*Op*/1, GIMT_Encode2(Intrinsic::amdgcn_global_load_tr),
        GIM_CheckType, /*MI*/0, /*Op*/0, /*Type*/GILLT_v4s16,
        GIM_CheckRegBankForClass, /*MI*/0, /*Op*/0, /*RC*/GIMT_Encode2(AMDGPU::AV_64RegClassID),
        GIM_CheckPointerToAny, /*MI*/0, /*Op*/2, /*SizeInBits*/0,
        GIM_CheckComplexPattern, /*MI*/0, /*Op*/2, /*Renderer*/GIMT_Encode2(0), GIMT_Encode2(GICP_gi_global_saddr),
        // (intrinsic_w_chain:{ *:[v4bf16] } 1986:{ *:[iPTR] }, (GlobalSAddr:{ *:[iPTR] } SReg_64:{ *:[i64] }:$saddr, VGPR_32:{ *:[i32] }:$voffset, i32:{ *:[i32] }:$offset))  =>  (GLOBAL_LOAD_TR_B128_w64_SADDR:{ *:[v4bf16] } ?:{ *:[i64] }:$saddr, ?:{ *:[i32] }:$voffset, ?:{ *:[i32] }:$offset, 0:{ *:[i32] })
        GIR_BuildMI, /*InsnID*/0, /*Opcode*/GIMT_Encode2(AMDGPU::GLOBAL_LOAD_TR_B128_w64_SADDR),
        GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/0, // DstI[vdst]
        GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/0, // saddr
        GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/1, // voffset
        GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/2, // offset
        GIR_AddImm8, /*InsnID*/0, /*Imm*/0,
        GIR_MergeMemOperands, /*InsnID*/0, /*NumInsns*/1, /*MergeInsnID's*/0,
        GIR_ConstrainSelectedInstOperands, /*InsnID*/0,
        GIR_EraseFromParent, /*InsnID*/0,
        // GIR_Coverage, 3275,
        GIR_Done,
      // Label 3648: @238948
      GIM_Try, /*On fail goto*//*Label 3649*/ GIMT_Encode4(239011), // Rule ID 3260 //
        GIM_CheckFeatures, GIMT_Encode2(GIFBS_isGFX12Plus_isWave32),
        GIM_CheckIntrinsicID, /*MI*/0, /*Op*/1, GIMT_Encode2(Intrinsic::amdgcn_global_load_tr),
        GIM_CheckType, /*MI*/0, /*Op*/0, /*Type*/GILLT_v2s32,
        GIM_CheckRegBankForClass, /*MI*/0, /*Op*/0, /*RC*/GIMT_Encode2(AMDGPU::AV_64RegClassID),
        GIM_CheckPointerToAny, /*MI*/0, /*Op*/2, /*SizeInBits*/0,
        GIM_CheckComplexPattern, /*MI*/0, /*Op*/2, /*Renderer*/GIMT_Encode2(0), GIMT_Encode2(GICP_gi_global_offset),
        // (intrinsic_w_chain:{ *:[v2i32] } 1986:{ *:[iPTR] }, (GlobalOffset:{ *:[iPTR] } VReg_64:{ *:[i64] }:$vaddr, i32:{ *:[i32] }:$offset))  =>  (GLOBAL_LOAD_TR_B64_w32:{ *:[v2i32] } ?:{ *:[i64] }:$vaddr, ?:{ *:[i32] }:$offset)
        GIR_BuildMI, /*InsnID*/0, /*Opcode*/GIMT_Encode2(AMDGPU::GLOBAL_LOAD_TR_B64_w32),
        GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/0, // DstI[vdst]
        GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/0, // vaddr
        GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/1, // offset
        GIR_AddImm8, /*InsnID*/0, /*Imm*/0,
        GIR_MergeMemOperands, /*InsnID*/0, /*NumInsns*/1, /*MergeInsnID's*/0,
        GIR_ConstrainSelectedInstOperands, /*InsnID*/0,
        GIR_EraseFromParent, /*InsnID*/0,
        // GIR_Coverage, 3260,
        GIR_Done,
      // Label 3649: @239011
      GIM_Try, /*On fail goto*//*Label 3650*/ GIMT_Encode4(239074), // Rule ID 3262 //
        GIM_CheckFeatures, GIMT_Encode2(GIFBS_isGFX12Plus_isWave32),
        GIM_CheckIntrinsicID, /*MI*/0, /*Op*/1, GIMT_Encode2(Intrinsic::amdgcn_global_load_tr),
        GIM_CheckType, /*MI*/0, /*Op*/0, /*Type*/GILLT_v8s16,
        GIM_CheckRegBankForClass, /*MI*/0, /*Op*/0, /*RC*/GIMT_Encode2(AMDGPU::AV_128RegClassID),
        GIM_CheckPointerToAny, /*MI*/0, /*Op*/2, /*SizeInBits*/0,
        GIM_CheckComplexPattern, /*MI*/0, /*Op*/2, /*Renderer*/GIMT_Encode2(0), GIMT_Encode2(GICP_gi_global_offset),
        // (intrinsic_w_chain:{ *:[v8i16] } 1986:{ *:[iPTR] }, (GlobalOffset:{ *:[iPTR] } VReg_64:{ *:[i64] }:$vaddr, i32:{ *:[i32] }:$offset))  =>  (GLOBAL_LOAD_TR_B128_w32:{ *:[v8i16] } ?:{ *:[i64] }:$vaddr, ?:{ *:[i32] }:$offset)
        GIR_BuildMI, /*InsnID*/0, /*Opcode*/GIMT_Encode2(AMDGPU::GLOBAL_LOAD_TR_B128_w32),
        GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/0, // DstI[vdst]
        GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/0, // vaddr
        GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/1, // offset
        GIR_AddImm8, /*InsnID*/0, /*Imm*/0,
        GIR_MergeMemOperands, /*InsnID*/0, /*NumInsns*/1, /*MergeInsnID's*/0,
        GIR_ConstrainSelectedInstOperands, /*InsnID*/0,
        GIR_EraseFromParent, /*InsnID*/0,
        // GIR_Coverage, 3262,
        GIR_Done,
      // Label 3650: @239074
      GIM_Try, /*On fail goto*//*Label 3651*/ GIMT_Encode4(239137), // Rule ID 3264 //
        GIM_CheckFeatures, GIMT_Encode2(GIFBS_isGFX12Plus_isWave32),
        GIM_CheckIntrinsicID, /*MI*/0, /*Op*/1, GIMT_Encode2(Intrinsic::amdgcn_global_load_tr),
        GIM_CheckType, /*MI*/0, /*Op*/0, /*Type*/GILLT_v8s16,
        GIM_CheckRegBankForClass, /*MI*/0, /*Op*/0, /*RC*/GIMT_Encode2(AMDGPU::AV_128RegClassID),
        GIM_CheckPointerToAny, /*MI*/0, /*Op*/2, /*SizeInBits*/0,
        GIM_CheckComplexPattern, /*MI*/0, /*Op*/2, /*Renderer*/GIMT_Encode2(0), GIMT_Encode2(GICP_gi_global_offset),
        // (intrinsic_w_chain:{ *:[v8f16] } 1986:{ *:[iPTR] }, (GlobalOffset:{ *:[iPTR] } VReg_64:{ *:[i64] }:$vaddr, i32:{ *:[i32] }:$offset))  =>  (GLOBAL_LOAD_TR_B128_w32:{ *:[v8f16] } ?:{ *:[i64] }:$vaddr, ?:{ *:[i32] }:$offset)
        GIR_BuildMI, /*InsnID*/0, /*Opcode*/GIMT_Encode2(AMDGPU::GLOBAL_LOAD_TR_B128_w32),
        GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/0, // DstI[vdst]
        GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/0, // vaddr
        GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/1, // offset
        GIR_AddImm8, /*InsnID*/0, /*Imm*/0,
        GIR_MergeMemOperands, /*InsnID*/0, /*NumInsns*/1, /*MergeInsnID's*/0,
        GIR_ConstrainSelectedInstOperands, /*InsnID*/0,
        GIR_EraseFromParent, /*InsnID*/0,
        // GIR_Coverage, 3264,
        GIR_Done,
      // Label 3651: @239137
      GIM_Try, /*On fail goto*//*Label 3652*/ GIMT_Encode4(239200), // Rule ID 3266 //
        GIM_CheckFeatures, GIMT_Encode2(GIFBS_isGFX12Plus_isWave32),
        GIM_CheckIntrinsicID, /*MI*/0, /*Op*/1, GIMT_Encode2(Intrinsic::amdgcn_global_load_tr),
        GIM_CheckType, /*MI*/0, /*Op*/0, /*Type*/GILLT_v8s16,
        GIM_CheckRegBankForClass, /*MI*/0, /*Op*/0, /*RC*/GIMT_Encode2(AMDGPU::AV_128RegClassID),
        GIM_CheckPointerToAny, /*MI*/0, /*Op*/2, /*SizeInBits*/0,
        GIM_CheckComplexPattern, /*MI*/0, /*Op*/2, /*Renderer*/GIMT_Encode2(0), GIMT_Encode2(GICP_gi_global_offset),
        // (intrinsic_w_chain:{ *:[v8bf16] } 1986:{ *:[iPTR] }, (GlobalOffset:{ *:[iPTR] } VReg_64:{ *:[i64] }:$vaddr, i32:{ *:[i32] }:$offset))  =>  (GLOBAL_LOAD_TR_B128_w32:{ *:[v8bf16] } ?:{ *:[i64] }:$vaddr, ?:{ *:[i32] }:$offset)
        GIR_BuildMI, /*InsnID*/0, /*Opcode*/GIMT_Encode2(AMDGPU::GLOBAL_LOAD_TR_B128_w32),
        GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/0, // DstI[vdst]
        GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/0, // vaddr
        GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/1, // offset
        GIR_AddImm8, /*InsnID*/0, /*Imm*/0,
        GIR_MergeMemOperands, /*InsnID*/0, /*NumInsns*/1, /*MergeInsnID's*/0,
        GIR_ConstrainSelectedInstOperands, /*InsnID*/0,
        GIR_EraseFromParent, /*InsnID*/0,
        // GIR_Coverage, 3266,
        GIR_Done,
      // Label 3652: @239200
      GIM_Try, /*On fail goto*//*Label 3653*/ GIMT_Encode4(239263), // Rule ID 3268 //
        GIM_CheckFeatures, GIMT_Encode2(GIFBS_isGFX12Plus_isWave64),
        GIM_CheckIntrinsicID, /*MI*/0, /*Op*/1, GIMT_Encode2(Intrinsic::amdgcn_global_load_tr),
        GIM_CheckType, /*MI*/0, /*Op*/0, /*Type*/GILLT_s32,
        GIM_CheckRegBankForClass, /*MI*/0, /*Op*/0, /*RC*/GIMT_Encode2(AMDGPU::AV_32RegClassID),
        GIM_CheckPointerToAny, /*MI*/0, /*Op*/2, /*SizeInBits*/0,
        GIM_CheckComplexPattern, /*MI*/0, /*Op*/2, /*Renderer*/GIMT_Encode2(0), GIMT_Encode2(GICP_gi_global_offset),
        // (intrinsic_w_chain:{ *:[i32] } 1986:{ *:[iPTR] }, (GlobalOffset:{ *:[iPTR] } VReg_64:{ *:[i64] }:$vaddr, i32:{ *:[i32] }:$offset))  =>  (GLOBAL_LOAD_TR_B64_w64:{ *:[i32] } ?:{ *:[i64] }:$vaddr, ?:{ *:[i32] }:$offset)
        GIR_BuildMI, /*InsnID*/0, /*Opcode*/GIMT_Encode2(AMDGPU::GLOBAL_LOAD_TR_B64_w64),
        GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/0, // DstI[vdst]
        GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/0, // vaddr
        GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/1, // offset
        GIR_AddImm8, /*InsnID*/0, /*Imm*/0,
        GIR_MergeMemOperands, /*InsnID*/0, /*NumInsns*/1, /*MergeInsnID's*/0,
        GIR_ConstrainSelectedInstOperands, /*InsnID*/0,
        GIR_EraseFromParent, /*InsnID*/0,
        // GIR_Coverage, 3268,
        GIR_Done,
      // Label 3653: @239263
      GIM_Try, /*On fail goto*//*Label 3654*/ GIMT_Encode4(239326), // Rule ID 3270 //
        GIM_CheckFeatures, GIMT_Encode2(GIFBS_isGFX12Plus_isWave64),
        GIM_CheckIntrinsicID, /*MI*/0, /*Op*/1, GIMT_Encode2(Intrinsic::amdgcn_global_load_tr),
        GIM_CheckType, /*MI*/0, /*Op*/0, /*Type*/GILLT_v4s16,
        GIM_CheckRegBankForClass, /*MI*/0, /*Op*/0, /*RC*/GIMT_Encode2(AMDGPU::AV_64RegClassID),
        GIM_CheckPointerToAny, /*MI*/0, /*Op*/2, /*SizeInBits*/0,
        GIM_CheckComplexPattern, /*MI*/0, /*Op*/2, /*Renderer*/GIMT_Encode2(0), GIMT_Encode2(GICP_gi_global_offset),
        // (intrinsic_w_chain:{ *:[v4i16] } 1986:{ *:[iPTR] }, (GlobalOffset:{ *:[iPTR] } VReg_64:{ *:[i64] }:$vaddr, i32:{ *:[i32] }:$offset))  =>  (GLOBAL_LOAD_TR_B128_w64:{ *:[v4i16] } ?:{ *:[i64] }:$vaddr, ?:{ *:[i32] }:$offset)
        GIR_BuildMI, /*InsnID*/0, /*Opcode*/GIMT_Encode2(AMDGPU::GLOBAL_LOAD_TR_B128_w64),
        GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/0, // DstI[vdst]
        GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/0, // vaddr
        GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/1, // offset
        GIR_AddImm8, /*InsnID*/0, /*Imm*/0,
        GIR_MergeMemOperands, /*InsnID*/0, /*NumInsns*/1, /*MergeInsnID's*/0,
        GIR_ConstrainSelectedInstOperands, /*InsnID*/0,
        GIR_EraseFromParent, /*InsnID*/0,
        // GIR_Coverage, 3270,
        GIR_Done,
      // Label 3654: @239326
      GIM_Try, /*On fail goto*//*Label 3655*/ GIMT_Encode4(239389), // Rule ID 3272 //
        GIM_CheckFeatures, GIMT_Encode2(GIFBS_isGFX12Plus_isWave64),
        GIM_CheckIntrinsicID, /*MI*/0, /*Op*/1, GIMT_Encode2(Intrinsic::amdgcn_global_load_tr),
        GIM_CheckType, /*MI*/0, /*Op*/0, /*Type*/GILLT_v4s16,
        GIM_CheckRegBankForClass, /*MI*/0, /*Op*/0, /*RC*/GIMT_Encode2(AMDGPU::AV_64RegClassID),
        GIM_CheckPointerToAny, /*MI*/0, /*Op*/2, /*SizeInBits*/0,
        GIM_CheckComplexPattern, /*MI*/0, /*Op*/2, /*Renderer*/GIMT_Encode2(0), GIMT_Encode2(GICP_gi_global_offset),
        // (intrinsic_w_chain:{ *:[v4f16] } 1986:{ *:[iPTR] }, (GlobalOffset:{ *:[iPTR] } VReg_64:{ *:[i64] }:$vaddr, i32:{ *:[i32] }:$offset))  =>  (GLOBAL_LOAD_TR_B128_w64:{ *:[v4f16] } ?:{ *:[i64] }:$vaddr, ?:{ *:[i32] }:$offset)
        GIR_BuildMI, /*InsnID*/0, /*Opcode*/GIMT_Encode2(AMDGPU::GLOBAL_LOAD_TR_B128_w64),
        GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/0, // DstI[vdst]
        GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/0, // vaddr
        GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/1, // offset
        GIR_AddImm8, /*InsnID*/0, /*Imm*/0,
        GIR_MergeMemOperands, /*InsnID*/0, /*NumInsns*/1, /*MergeInsnID's*/0,
        GIR_ConstrainSelectedInstOperands, /*InsnID*/0,
        GIR_EraseFromParent, /*InsnID*/0,
        // GIR_Coverage, 3272,
        GIR_Done,
      // Label 3655: @239389
      GIM_Try, /*On fail goto*//*Label 3656*/ GIMT_Encode4(239452), // Rule ID 3274 //
        GIM_CheckFeatures, GIMT_Encode2(GIFBS_isGFX12Plus_isWave64),
        GIM_CheckIntrinsicID, /*MI*/0, /*Op*/1, GIMT_Encode2(Intrinsic::amdgcn_global_load_tr),
        GIM_CheckType, /*MI*/0, /*Op*/0, /*Type*/GILLT_v4s16,
        GIM_CheckRegBankForClass, /*MI*/0, /*Op*/0, /*RC*/GIMT_Encode2(AMDGPU::AV_64RegClassID),
        GIM_CheckPointerToAny, /*MI*/0, /*Op*/2, /*SizeInBits*/0,
        GIM_CheckComplexPattern, /*MI*/0, /*Op*/2, /*Renderer*/GIMT_Encode2(0), GIMT_Encode2(GICP_gi_global_offset),
        // (intrinsic_w_chain:{ *:[v4bf16] } 1986:{ *:[iPTR] }, (GlobalOffset:{ *:[iPTR] } VReg_64:{ *:[i64] }:$vaddr, i32:{ *:[i32] }:$offset))  =>  (GLOBAL_LOAD_TR_B128_w64:{ *:[v4bf16] } ?:{ *:[i64] }:$vaddr, ?:{ *:[i32] }:$offset)
        GIR_BuildMI, /*InsnID*/0, /*Opcode*/GIMT_Encode2(AMDGPU::GLOBAL_LOAD_TR_B128_w64),
        GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/0, // DstI[vdst]
        GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/0, // vaddr
        GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/1, // offset
        GIR_AddImm8, /*InsnID*/0, /*Imm*/0,
        GIR_MergeMemOperands, /*InsnID*/0, /*NumInsns*/1, /*MergeInsnID's*/0,
        GIR_ConstrainSelectedInstOperands, /*InsnID*/0,
        GIR_EraseFromParent, /*InsnID*/0,
        // GIR_Coverage, 3274,
        GIR_Done,
      // Label 3656: @239452
      GIM_Try, /*On fail goto*//*Label 3657*/ GIMT_Encode4(239489), // Rule ID 1133 //
        GIM_CheckIntrinsicID, /*MI*/0, /*Op*/0, GIMT_Encode2(Intrinsic::amdgcn_init_exec_from_input),
        GIM_CheckType, /*MI*/0, /*Op*/1, /*Type*/GILLT_s32,
        // MIs[0] shift
        GIM_CheckIsImm, /*MI*/0, /*Op*/2,
        // (intrinsic_void 2514:{ *:[iPTR] }, i32:{ *:[i32] }:$input, (timm:{ *:[i32] }):$shift)  =>  (SI_INIT_EXEC_FROM_INPUT i32:{ *:[i32] }:$input, (timm:{ *:[i32] }):$shift)
        GIR_BuildMI, /*InsnID*/0, /*Opcode*/GIMT_Encode2(AMDGPU::SI_INIT_EXEC_FROM_INPUT),
        GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/1, // input
        GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/2, // shift
        GIR_SetImplicitDefDead, /*InsnID*/0, /*OpIdx for AMDGPU::EXEC*/0,
        GIR_ConstrainSelectedInstOperands, /*InsnID*/0,
        GIR_EraseFromParent, /*InsnID*/0,
        // GIR_Coverage, 1133,
        GIR_Done,
      // Label 3657: @239489
      GIM_Reject,
    // Label 3640: @239490
    GIM_Try, /*On fail goto*//*Label 3658*/ GIMT_Encode4(239533), // Rule ID 1124 //
      GIM_CheckNumOperands, /*MI*/0, /*Expected*/4,
      GIM_CheckIntrinsicID, /*MI*/0, /*Op*/0, GIMT_Encode2(Intrinsic::amdgcn_sched_group_barrier),
      // MIs[0] mask
      GIM_CheckIsImm, /*MI*/0, /*Op*/1,
      // MIs[0] size
      GIM_CheckIsImm, /*MI*/0, /*Op*/2,
      // MIs[0] syncid
      GIM_CheckIsImm, /*MI*/0, /*Op*/3,
      // (intrinsic_void 2706:{ *:[iPTR] }, (timm:{ *:[i32] }):$mask, (timm:{ *:[i32] }):$size, (timm:{ *:[i32] }):$syncid)  =>  (SCHED_GROUP_BARRIER (timm:{ *:[i32] }):$mask, (timm:{ *:[i32] }):$size, (timm:{ *:[i32] }):$syncid)
      GIR_BuildMI, /*InsnID*/0, /*Opcode*/GIMT_Encode2(AMDGPU::SCHED_GROUP_BARRIER),
      GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/1, // mask
      GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/2, // size
      GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/3, // syncid
      GIR_ConstrainSelectedInstOperands, /*InsnID*/0,
      GIR_EraseFromParent, /*InsnID*/0,
      // GIR_Coverage, 1124,
      GIR_Done,
    // Label 3658: @239533
    GIM_Reject,
    // Label 36: @239534
    GIM_SwitchType, /*MI*/0, /*Op*/0, /*[*/GIMT_Encode2(8), GIMT_Encode2(11), /*)*//*default:*//*Label 3662*/ GIMT_Encode4(239905),
    /*GILLT_s16*//*Label 3659*/ GIMT_Encode4(239557),
    /*GILLT_s32*//*Label 3660*/ GIMT_Encode4(239604),
    /*GILLT_s64*//*Label 3661*/ GIMT_Encode4(239648),
    // Label 3659: @239557
    GIM_Try, /*On fail goto*//*Label 3663*/ GIMT_Encode4(239603), // Rule ID 2159 //
      GIM_CheckFeatures, GIMT_Encode2(GIFBS_Has16BitInsts),
      GIM_CheckType, /*MI*/0, /*Op*/1, /*Type*/GILLT_s1,
      GIM_CheckRegBankForClass, /*MI*/0, /*Op*/0, /*RC*/GIMT_Encode2(AMDGPU::VGPR_32RegClassID),
      // (anyext:{ *:[i16] } i1:{ *:[i1] }:$src)  =>  (V_CNDMASK_B32_e64:{ *:[i16] } 0:{ *:[i32] }, 0:{ *:[i32] }, 0:{ *:[i32] }, 1:{ *:[i32] }, ?:{ *:[i1] }:$src)
      GIR_BuildMI, /*InsnID*/0, /*Opcode*/GIMT_Encode2(AMDGPU::V_CNDMASK_B32_e64),
      GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/0, // DstI[vdst]
      GIR_AddImm8, /*InsnID*/0, /*Imm*/0,
      GIR_AddImm8, /*InsnID*/0, /*Imm*/0,
      GIR_AddImm8, /*InsnID*/0, /*Imm*/0,
      GIR_AddImm8, /*InsnID*/0, /*Imm*/1,
      GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/1, // src
      GIR_ConstrainSelectedInstOperands, /*InsnID*/0,
      GIR_EraseFromParent, /*InsnID*/0,
      // GIR_Coverage, 2159,
      GIR_Done,
    // Label 3663: @239603
    GIM_Reject,
    // Label 3660: @239604
    GIM_Try, /*On fail goto*//*Label 3664*/ GIMT_Encode4(239647), // Rule ID 6267 //
      GIM_CheckType, /*MI*/0, /*Op*/1, /*Type*/GILLT_s1,
      GIM_CheckRegBankForClass, /*MI*/0, /*Op*/0, /*RC*/GIMT_Encode2(AMDGPU::VGPR_32RegClassID),
      // (anyext:{ *:[i32] } i1:{ *:[i1] }:$src0)  =>  (V_CNDMASK_B32_e64:{ *:[i32] } 0:{ *:[i32] }, 0:{ *:[i32] }, 0:{ *:[i32] }, 1:{ *:[i32] }, i1:{ *:[i1] }:$src0)
      GIR_BuildMI, /*InsnID*/0, /*Opcode*/GIMT_Encode2(AMDGPU::V_CNDMASK_B32_e64),
      GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/0, // DstI[vdst]
      GIR_AddImm8, /*InsnID*/0, /*Imm*/0,
      GIR_AddImm8, /*InsnID*/0, /*Imm*/0,
      GIR_AddImm8, /*InsnID*/0, /*Imm*/0,
      GIR_AddImm8, /*InsnID*/0, /*Imm*/1,
      GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/1, // src0
      GIR_ConstrainSelectedInstOperands, /*InsnID*/0,
      GIR_EraseFromParent, /*InsnID*/0,
      // GIR_Coverage, 6267,
      GIR_Done,
    // Label 3664: @239647
    GIM_Reject,
    // Label 3661: @239648
    GIM_Try, /*On fail goto*//*Label 3665*/ GIMT_Encode4(239738), // Rule ID 2086 //
      GIM_CheckFeatures, GIMT_Encode2(GIFBS_isGFX8Plus),
      GIM_CheckType, /*MI*/0, /*Op*/1, /*Type*/GILLT_s16,
      GIM_CheckRegBankForClass, /*MI*/0, /*Op*/0, /*RC*/GIMT_Encode2(AMDGPU::VReg_64RegClassID),
      // (anyext:{ *:[i64] } i16:{ *:[i16] }:$src)  =>  (REG_SEQUENCE:{ *:[i64] } VReg_64:{ *:[i32] }, (COPY:{ *:[i32] } ?:{ *:[i16] }:$src), sub0:{ *:[i32] }, (V_MOV_B32_e32:{ *:[i16] } 0:{ *:[i32] }), sub1:{ *:[i32] })
      GIR_MakeTempReg, /*TempRegID*/0, /*TypeID*/GILLT_s32,
      GIR_MakeTempReg, /*TempRegID*/1, /*TypeID*/GILLT_s16,
      GIR_BuildMI, /*InsnID*/2, /*Opcode*/GIMT_Encode2(AMDGPU::V_MOV_B32_e32),
      GIR_AddTempRegister, /*InsnID*/2, /*TempRegID*/1, /*TempRegFlags*/GIMT_Encode2(RegState::Define),
      GIR_AddImm8, /*InsnID*/2, /*Imm*/0,
      GIR_ConstrainSelectedInstOperands, /*InsnID*/2,
      GIR_BuildMI, /*InsnID*/1, /*Opcode*/GIMT_Encode2(TargetOpcode::COPY),
      GIR_AddTempRegister, /*InsnID*/1, /*TempRegID*/0, /*TempRegFlags*/GIMT_Encode2(RegState::Define),
      GIR_Copy, /*NewInsnID*/1, /*OldInsnID*/0, /*OpIdx*/1, // src
      GIR_ConstrainSelectedInstOperands, /*InsnID*/1,
      GIR_BuildMI, /*InsnID*/0, /*Opcode*/GIMT_Encode2(TargetOpcode::REG_SEQUENCE),
      GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/0, // DstI[dst]
      GIR_AddSimpleTempRegister, /*InsnID*/0, /*TempRegID*/0,
      GIR_AddImm8, /*InsnID*/0, /*SubRegIndex*/3,
      GIR_AddSimpleTempRegister, /*InsnID*/0, /*TempRegID*/1,
      GIR_AddImm8, /*InsnID*/0, /*SubRegIndex*/11,
      GIR_ConstrainOperandRC, /*InsnID*/0, /*Op*/0, GIMT_Encode2(AMDGPU::VReg_64RegClassID),
      GIR_ConstrainOperandRC, /*InsnID*/0, /*Op*/1, GIMT_Encode2(AMDGPU::VGPR_32RegClassID),
      GIR_ConstrainOperandRC, /*InsnID*/0, /*Op*/3, GIMT_Encode2(AMDGPU::VGPR_32RegClassID),
      GIR_EraseFromParent, /*InsnID*/0,
      // GIR_Coverage, 2086,
      GIR_Done,
    // Label 3665: @239738
    GIM_Try, /*On fail goto*//*Label 3666*/ GIMT_Encode4(239805), // Rule ID 6340 //
      GIM_CheckType, /*MI*/0, /*Op*/1, /*Type*/GILLT_s32,
      GIM_CheckRegBankForClass, /*MI*/0, /*Op*/0, /*RC*/GIMT_Encode2(AMDGPU::SReg_64RegClassID),
      // (anyext:{ *:[i64] } i32:{ *:[i32] }:$src)  =>  (REG_SEQUENCE:{ *:[i64] } SReg_64:{ *:[i32] }, ?:{ *:[i32] }:$src, sub0:{ *:[i32] }, (IMPLICIT_DEF:{ *:[i32] }), sub1:{ *:[i32] })
      GIR_MakeTempReg, /*TempRegID*/0, /*TypeID*/GILLT_s32,
      GIR_BuildMI, /*InsnID*/1, /*Opcode*/GIMT_Encode2(TargetOpcode::IMPLICIT_DEF),
      GIR_AddTempRegister, /*InsnID*/1, /*TempRegID*/0, /*TempRegFlags*/GIMT_Encode2(RegState::Define),
      GIR_ConstrainSelectedInstOperands, /*InsnID*/1,
      GIR_BuildMI, /*InsnID*/0, /*Opcode*/GIMT_Encode2(TargetOpcode::REG_SEQUENCE),
      GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/0, // DstI[dst]
      GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/1, // src
      GIR_AddImm8, /*InsnID*/0, /*SubRegIndex*/3,
      GIR_AddSimpleTempRegister, /*InsnID*/0, /*TempRegID*/0,
      GIR_AddImm8, /*InsnID*/0, /*SubRegIndex*/11,
      GIR_ConstrainOperandRC, /*InsnID*/0, /*Op*/0, GIMT_Encode2(AMDGPU::SReg_64RegClassID),
      GIR_ConstrainOperandRC, /*InsnID*/0, /*Op*/1, GIMT_Encode2(AMDGPU::SReg_32_XEXEC_HI_and_SReg_32_XM0RegClassID),
      GIR_ConstrainOperandRC, /*InsnID*/0, /*Op*/3, GIMT_Encode2(AMDGPU::SReg_32_XM0RegClassID),
      GIR_EraseFromParent, /*InsnID*/0,
      // GIR_Coverage, 6340,
      GIR_Done,
    // Label 3666: @239805
    GIM_Try, /*On fail goto*//*Label 3667*/ GIMT_Encode4(239904), // Rule ID 6342 //
      GIM_CheckType, /*MI*/0, /*Op*/1, /*Type*/GILLT_s1,
      GIM_CheckRegBankForClass, /*MI*/0, /*Op*/0, /*RC*/GIMT_Encode2(AMDGPU::VReg_64RegClassID),
      // (anyext:{ *:[i64] } i1:{ *:[i1] }:$src)  =>  (REG_SEQUENCE:{ *:[i64] } VReg_64:{ *:[i32] }, (V_CNDMASK_B32_e64:{ *:[i16] } 0:{ *:[i32] }, 0:{ *:[i32] }, 0:{ *:[i32] }, 1:{ *:[i32] }, ?:{ *:[i1] }:$src), sub0:{ *:[i32] }, (S_MOV_B32:{ *:[i1] } 0:{ *:[i32] }), sub1:{ *:[i32] })
      GIR_MakeTempReg, /*TempRegID*/0, /*TypeID*/GILLT_s16,
      GIR_MakeTempReg, /*TempRegID*/1, /*TypeID*/GILLT_s1,
      GIR_BuildMI, /*InsnID*/2, /*Opcode*/GIMT_Encode2(AMDGPU::S_MOV_B32),
      GIR_AddTempRegister, /*InsnID*/2, /*TempRegID*/1, /*TempRegFlags*/GIMT_Encode2(RegState::Define),
      GIR_AddImm8, /*InsnID*/2, /*Imm*/0,
      GIR_ConstrainSelectedInstOperands, /*InsnID*/2,
      GIR_BuildMI, /*InsnID*/1, /*Opcode*/GIMT_Encode2(AMDGPU::V_CNDMASK_B32_e64),
      GIR_AddTempRegister, /*InsnID*/1, /*TempRegID*/0, /*TempRegFlags*/GIMT_Encode2(RegState::Define),
      GIR_AddImm8, /*InsnID*/1, /*Imm*/0,
      GIR_AddImm8, /*InsnID*/1, /*Imm*/0,
      GIR_AddImm8, /*InsnID*/1, /*Imm*/0,
      GIR_AddImm8, /*InsnID*/1, /*Imm*/1,
      GIR_Copy, /*NewInsnID*/1, /*OldInsnID*/0, /*OpIdx*/1, // src
      GIR_ConstrainSelectedInstOperands, /*InsnID*/1,
      GIR_BuildMI, /*InsnID*/0, /*Opcode*/GIMT_Encode2(TargetOpcode::REG_SEQUENCE),
      GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/0, // DstI[dst]
      GIR_AddSimpleTempRegister, /*InsnID*/0, /*TempRegID*/0,
      GIR_AddImm8, /*InsnID*/0, /*SubRegIndex*/3,
      GIR_AddSimpleTempRegister, /*InsnID*/0, /*TempRegID*/1,
      GIR_AddImm8, /*InsnID*/0, /*SubRegIndex*/11,
      GIR_ConstrainOperandRC, /*InsnID*/0, /*Op*/0, GIMT_Encode2(AMDGPU::VReg_64RegClassID),
      GIR_ConstrainOperandRC, /*InsnID*/0, /*Op*/1, GIMT_Encode2(AMDGPU::VGPR_32RegClassID),
      GIR_ConstrainOperandRC, /*InsnID*/0, /*Op*/3, GIMT_Encode2(AMDGPU::VGPR_32RegClassID),
      GIR_EraseFromParent, /*InsnID*/0,
      // GIR_Coverage, 6342,
      GIR_Done,
    // Label 3667: @239904
    GIM_Reject,
    // Label 3662: @239905
    GIM_Reject,
    // Label 37: @239906
    GIM_Try, /*On fail goto*//*Label 3668*/ GIMT_Encode4(240045),
      GIM_CheckType, /*MI*/0, /*Op*/0, /*Type*/GILLT_s1,
      GIM_SwitchType, /*MI*/0, /*Op*/1, /*[*/GIMT_Encode2(8), GIMT_Encode2(10), /*)*//*default:*//*Label 3671*/ GIMT_Encode4(240044),
      /*GILLT_s16*//*Label 3669*/ GIMT_Encode4(239934),
      /*GILLT_s32*//*Label 3670*/ GIMT_Encode4(239989),
      // Label 3669: @239934
      GIM_Try, /*On fail goto*//*Label 3672*/ GIMT_Encode4(239988), // Rule ID 6388 //
        GIM_CheckRegBankForClass, /*MI*/0, /*Op*/0, /*RC*/GIMT_Encode2(AMDGPU::SReg_1RegClassID),
        GIM_CheckCxxInsnPredicate, /*MI*/0, /*FnId*/GIMT_Encode2(GICXXPred_MI_Predicate_anonymous_35205),
        // (trunc:{ *:[i1] } i16:{ *:[i16] }:$a)<<P:Predicate_anonymous_35205>>  =>  (V_CMP_EQ_U32_e64:{ *:[i1] } (V_AND_B32_e64:{ *:[i16] } 1:{ *:[i32] }, ?:{ *:[i16] }:$a), 1:{ *:[i32] })
        GIR_MakeTempReg, /*TempRegID*/0, /*TypeID*/GILLT_s16,
        GIR_BuildMI, /*InsnID*/1, /*Opcode*/GIMT_Encode2(AMDGPU::V_AND_B32_e64),
        GIR_AddTempRegister, /*InsnID*/1, /*TempRegID*/0, /*TempRegFlags*/GIMT_Encode2(RegState::Define),
        GIR_AddImm8, /*InsnID*/1, /*Imm*/1,
        GIR_Copy, /*NewInsnID*/1, /*OldInsnID*/0, /*OpIdx*/1, // a
        GIR_ConstrainSelectedInstOperands, /*InsnID*/1,
        GIR_BuildMI, /*InsnID*/0, /*Opcode*/GIMT_Encode2(AMDGPU::V_CMP_EQ_U32_e64),
        GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/0, // DstI[sdst]
        GIR_AddSimpleTempRegister, /*InsnID*/0, /*TempRegID*/0,
        GIR_AddImm8, /*InsnID*/0, /*Imm*/1,
        GIR_ConstrainSelectedInstOperands, /*InsnID*/0,
        GIR_EraseFromParent, /*InsnID*/0,
        // GIR_Coverage, 6388,
        GIR_Done,
      // Label 3672: @239988
      GIM_Reject,
      // Label 3670: @239989
      GIM_Try, /*On fail goto*//*Label 3673*/ GIMT_Encode4(240043), // Rule ID 6387 //
        GIM_CheckRegBankForClass, /*MI*/0, /*Op*/0, /*RC*/GIMT_Encode2(AMDGPU::SReg_1RegClassID),
        GIM_CheckCxxInsnPredicate, /*MI*/0, /*FnId*/GIMT_Encode2(GICXXPred_MI_Predicate_anonymous_35205),
        // (trunc:{ *:[i1] } i32:{ *:[i32] }:$a)<<P:Predicate_anonymous_35205>>  =>  (V_CMP_EQ_U32_e64:{ *:[i1] } (V_AND_B32_e64:{ *:[i16] } 1:{ *:[i32] }, ?:{ *:[i32] }:$a), 1:{ *:[i32] })
        GIR_MakeTempReg, /*TempRegID*/0, /*TypeID*/GILLT_s16,
        GIR_BuildMI, /*InsnID*/1, /*Opcode*/GIMT_Encode2(AMDGPU::V_AND_B32_e64),
        GIR_AddTempRegister, /*InsnID*/1, /*TempRegID*/0, /*TempRegFlags*/GIMT_Encode2(RegState::Define),
        GIR_AddImm8, /*InsnID*/1, /*Imm*/1,
        GIR_Copy, /*NewInsnID*/1, /*OldInsnID*/0, /*OpIdx*/1, // a
        GIR_ConstrainSelectedInstOperands, /*InsnID*/1,
        GIR_BuildMI, /*InsnID*/0, /*Opcode*/GIMT_Encode2(AMDGPU::V_CMP_EQ_U32_e64),
        GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/0, // DstI[sdst]
        GIR_AddSimpleTempRegister, /*InsnID*/0, /*TempRegID*/0,
        GIR_AddImm8, /*InsnID*/0, /*Imm*/1,
        GIR_ConstrainSelectedInstOperands, /*InsnID*/0,
        GIR_EraseFromParent, /*InsnID*/0,
        // GIR_Coverage, 6387,
        GIR_Done,
      // Label 3673: @240043
      GIM_Reject,
      // Label 3671: @240044
      GIM_Reject,
    // Label 3668: @240045
    GIM_Reject,
    // Label 38: @240046
    GIM_SwitchType, /*MI*/0, /*Op*/0, /*[*/GIMT_Encode2(8), GIMT_Encode2(11), /*)*//*default:*//*Label 3677*/ GIMT_Encode4(240180),
    /*GILLT_s16*//*Label 3674*/ GIMT_Encode4(240069),
    /*GILLT_s32*//*Label 3675*/ GIMT_Encode4(240096),
    /*GILLT_s64*//*Label 3676*/ GIMT_Encode4(240123),
    // Label 3674: @240069
    GIM_Try, /*On fail goto*//*Label 3678*/ GIMT_Encode4(240095), // Rule ID 1646 //
      GIM_CheckRegBankForClass, /*MI*/0, /*Op*/0, /*RC*/GIMT_Encode2(AMDGPU::SReg_32RegClassID),
      // MIs[0] Operand 1
      // No operand predicates
      // (imm:{ *:[i16] }):$imm  =>  (S_MOV_B32:{ *:[i16] } (imm:{ *:[i16] }):$imm)
      GIR_BuildMI, /*InsnID*/0, /*Opcode*/GIMT_Encode2(AMDGPU::S_MOV_B32),
      GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/0, // DstI[sdst]
      GIR_CopyConstantAsSImm, /*NewInsnID*/0, /*OldInsnID*/0, // imm
      GIR_ConstrainSelectedInstOperands, /*InsnID*/0,
      GIR_EraseFromParent, /*InsnID*/0,
      // GIR_Coverage, 1646,
      GIR_Done,
    // Label 3678: @240095
    GIM_Reject,
    // Label 3675: @240096
    GIM_Try, /*On fail goto*//*Label 3679*/ GIMT_Encode4(240122), // Rule ID 6246 //
      GIM_CheckRegBankForClass, /*MI*/0, /*Op*/0, /*RC*/GIMT_Encode2(AMDGPU::SReg_32RegClassID),
      // MIs[0] Operand 1
      // No operand predicates
      // (imm:{ *:[i32] }):$imm  =>  (S_MOV_B32:{ *:[i32] } (imm:{ *:[i32] }):$imm)
      GIR_BuildMI, /*InsnID*/0, /*Opcode*/GIMT_Encode2(AMDGPU::S_MOV_B32),
      GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/0, // DstI[sdst]
      GIR_CopyConstantAsSImm, /*NewInsnID*/0, /*OldInsnID*/0, // imm
      GIR_ConstrainSelectedInstOperands, /*InsnID*/0,
      GIR_EraseFromParent, /*InsnID*/0,
      // GIR_Coverage, 6246,
      GIR_Done,
    // Label 3679: @240122
    GIM_Reject,
    // Label 3676: @240123
    GIM_Try, /*On fail goto*//*Label 3680*/ GIMT_Encode4(240153), // Rule ID 6260 //
      GIM_CheckI64ImmPredicate, /*MI*/0, /*Predicate*/GIMT_Encode2(GICXXPred_I64_Predicate_InlineImm64),
      GIM_CheckRegBankForClass, /*MI*/0, /*Op*/0, /*RC*/GIMT_Encode2(AMDGPU::SReg_64RegClassID),
      // MIs[0] Operand 1
      // No operand predicates
      // (imm:{ *:[i64] })<<P:Predicate_InlineImm64>>:$imm  =>  (S_MOV_B64:{ *:[i64] } (imm:{ *:[i64] })<<P:Predicate_InlineImm64>>:$imm)
      GIR_BuildMI, /*InsnID*/0, /*Opcode*/GIMT_Encode2(AMDGPU::S_MOV_B64),
      GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/0, // DstI[sdst]
      GIR_CopyConstantAsSImm, /*NewInsnID*/0, /*OldInsnID*/0, // imm
      GIR_ConstrainSelectedInstOperands, /*InsnID*/0,
      GIR_EraseFromParent, /*InsnID*/0,
      // GIR_Coverage, 6260,
      GIR_Done,
    // Label 3680: @240153
    GIM_Try, /*On fail goto*//*Label 3681*/ GIMT_Encode4(240179), // Rule ID 6253 //
      GIM_CheckRegBankForClass, /*MI*/0, /*Op*/0, /*RC*/GIMT_Encode2(AMDGPU::SReg_64RegClassID),
      // MIs[0] Operand 1
      // No operand predicates
      // (imm:{ *:[i64] }):$imm  =>  (S_MOV_B64_IMM_PSEUDO:{ *:[i64] } (imm:{ *:[i64] }):$imm)
      GIR_BuildMI, /*InsnID*/0, /*Opcode*/GIMT_Encode2(AMDGPU::S_MOV_B64_IMM_PSEUDO),
      GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/0, // DstI[sdst]
      GIR_CopyConstantAsSImm, /*NewInsnID*/0, /*OldInsnID*/0, // imm
      GIR_ConstrainSelectedInstOperands, /*InsnID*/0,
      GIR_EraseFromParent, /*InsnID*/0,
      // GIR_Coverage, 6253,
      GIR_Done,
    // Label 3681: @240179
    GIM_Reject,
    // Label 3677: @240180
    GIM_Reject,
    // Label 39: @240181
    GIM_SwitchType, /*MI*/0, /*Op*/0, /*[*/GIMT_Encode2(8), GIMT_Encode2(10), /*)*//*default:*//*Label 3684*/ GIMT_Encode4(240287),
    /*GILLT_s16*//*Label 3682*/ GIMT_Encode4(240200),
    /*GILLT_s32*//*Label 3683*/ GIMT_Encode4(240258),
    // Label 3682: @240200
    GIM_Try, /*On fail goto*//*Label 3685*/ GIMT_Encode4(240257),
      GIM_CheckRegBankForClass, /*MI*/0, /*Op*/0, /*RC*/GIMT_Encode2(AMDGPU::SReg_32RegClassID),
      GIM_Try, /*On fail goto*//*Label 3686*/ GIMT_Encode4(240233), // Rule ID 6256 //
        // MIs[0] Operand 1
        // No operand predicates
        // (fpimm:{ *:[f16] }):$imm  =>  (S_MOV_B32:{ *:[f16] } (bitcast_fpimm_to_i32:{ *:[i32] } ?:{ *:[f16] }:$imm))
        GIR_BuildMI, /*InsnID*/0, /*Opcode*/GIMT_Encode2(AMDGPU::S_MOV_B32),
        GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/0, // DstI[sdst]
        GIR_CustomRenderer, /*InsnID*/0, /*OldInsnID*/0, /*Renderer*/GIMT_Encode2(GICR_renderBitcastImm), // imm
        GIR_ConstrainSelectedInstOperands, /*InsnID*/0,
        GIR_EraseFromParent, /*InsnID*/0,
        // GIR_Coverage, 6256,
        GIR_Done,
      // Label 3686: @240233
      GIM_Try, /*On fail goto*//*Label 3687*/ GIMT_Encode4(240256), // Rule ID 6257 //
        // MIs[0] Operand 1
        // No operand predicates
        // (fpimm:{ *:[bf16] }):$imm  =>  (S_MOV_B32:{ *:[bf16] } (bitcast_fpimm_to_i32:{ *:[i32] } ?:{ *:[bf16] }:$imm))
        GIR_BuildMI, /*InsnID*/0, /*Opcode*/GIMT_Encode2(AMDGPU::S_MOV_B32),
        GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/0, // DstI[sdst]
        GIR_CustomRenderer, /*InsnID*/0, /*OldInsnID*/0, /*Renderer*/GIMT_Encode2(GICR_renderBitcastImm), // imm
        GIR_ConstrainSelectedInstOperands, /*InsnID*/0,
        GIR_EraseFromParent, /*InsnID*/0,
        // GIR_Coverage, 6257,
        GIR_Done,
      // Label 3687: @240256
      GIM_Reject,
    // Label 3685: @240257
    GIM_Reject,
    // Label 3683: @240258
    GIM_Try, /*On fail goto*//*Label 3688*/ GIMT_Encode4(240286), // Rule ID 6255 //
      GIM_CheckRegBankForClass, /*MI*/0, /*Op*/0, /*RC*/GIMT_Encode2(AMDGPU::SReg_32RegClassID),
      // MIs[0] Operand 1
      // No operand predicates
      // (fpimm:{ *:[f32] }):$imm  =>  (S_MOV_B32:{ *:[f32] } (bitcast_fpimm_to_i32:{ *:[f32] } ?:{ *:[f32] }:$imm))
      GIR_BuildMI, /*InsnID*/0, /*Opcode*/GIMT_Encode2(AMDGPU::S_MOV_B32),
      GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/0, // DstI[sdst]
      GIR_CustomRenderer, /*InsnID*/0, /*OldInsnID*/0, /*Renderer*/GIMT_Encode2(GICR_renderBitcastImm), // imm
      GIR_ConstrainSelectedInstOperands, /*InsnID*/0,
      GIR_EraseFromParent, /*InsnID*/0,
      // GIR_Coverage, 6255,
      GIR_Done,
    // Label 3688: @240286
    GIM_Reject,
    // Label 3684: @240287
    GIM_Reject,
    // Label 40: @240288
    GIM_SwitchType, /*MI*/0, /*Op*/0, /*[*/GIMT_Encode2(8), GIMT_Encode2(11), /*)*//*default:*//*Label 3692*/ GIMT_Encode4(240903),
    /*GILLT_s16*//*Label 3689*/ GIMT_Encode4(240311),
    /*GILLT_s32*//*Label 3690*/ GIMT_Encode4(240358),
    /*GILLT_s64*//*Label 3691*/ GIMT_Encode4(240469),
    // Label 3689: @240311
    GIM_Try, /*On fail goto*//*Label 3693*/ GIMT_Encode4(240357), // Rule ID 2160 //
      GIM_CheckFeatures, GIMT_Encode2(GIFBS_Has16BitInsts),
      GIM_CheckType, /*MI*/0, /*Op*/1, /*Type*/GILLT_s1,
      GIM_CheckRegBankForClass, /*MI*/0, /*Op*/0, /*RC*/GIMT_Encode2(AMDGPU::VGPR_32RegClassID),
      // (sext:{ *:[i16] } i1:{ *:[i1] }:$src)  =>  (V_CNDMASK_B32_e64:{ *:[i16] } 0:{ *:[i32] }, 0:{ *:[i32] }, 0:{ *:[i32] }, -1:{ *:[i32] }, ?:{ *:[i1] }:$src)
      GIR_BuildMI, /*InsnID*/0, /*Opcode*/GIMT_Encode2(AMDGPU::V_CNDMASK_B32_e64),
      GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/0, // DstI[vdst]
      GIR_AddImm8, /*InsnID*/0, /*Imm*/0,
      GIR_AddImm8, /*InsnID*/0, /*Imm*/0,
      GIR_AddImm8, /*InsnID*/0, /*Imm*/0,
      GIR_AddImm8, /*InsnID*/0, /*Imm*/uint8_t(-1),
      GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/1, // src
      GIR_ConstrainSelectedInstOperands, /*InsnID*/0,
      GIR_EraseFromParent, /*InsnID*/0,
      // GIR_Coverage, 2160,
      GIR_Done,
    // Label 3693: @240357
    GIM_Reject,
    // Label 3690: @240358
    GIM_Try, /*On fail goto*//*Label 3694*/ GIMT_Encode4(240384), // Rule ID 1647 //
      GIM_CheckType, /*MI*/0, /*Op*/1, /*Type*/GILLT_s16,
      GIM_CheckRegBankForClass, /*MI*/0, /*Op*/0, /*RC*/GIMT_Encode2(AMDGPU::SReg_32RegClassID),
      GIM_CheckCxxInsnPredicate, /*MI*/0, /*FnId*/GIMT_Encode2(GICXXPred_MI_Predicate_anonymous_17658),
      // (sext:{ *:[i32] } i16:{ *:[i16] }:$src)<<P:Predicate_anonymous_17658>>  =>  (S_SEXT_I32_I16:{ *:[i32] } ?:{ *:[i16] }:$src)
      GIR_MutateOpcode, /*InsnID*/0, /*RecycleInsnID*/0, /*Opcode*/GIMT_Encode2(AMDGPU::S_SEXT_I32_I16),
      GIR_ConstrainSelectedInstOperands, /*InsnID*/0,
      // GIR_Coverage, 1647,
      GIR_Done,
    // Label 3694: @240384
    GIM_Try, /*On fail goto*//*Label 3695*/ GIMT_Encode4(240425), // Rule ID 2167 //
      GIM_CheckType, /*MI*/0, /*Op*/1, /*Type*/GILLT_s16,
      GIM_CheckRegBankForClass, /*MI*/0, /*Op*/0, /*RC*/GIMT_Encode2(AMDGPU::VGPR_32RegClassID),
      GIM_CheckCxxInsnPredicate, /*MI*/0, /*FnId*/GIMT_Encode2(GICXXPred_MI_Predicate_anonymous_23313),
      // (sext:{ *:[i32] } i16:{ *:[i16] }:$src)<<P:Predicate_anonymous_23313>>  =>  (V_BFE_I32_e64:{ *:[i32] } i16:{ *:[i16] }:$src, 0:{ *:[i32] }, 16:{ *:[i32] })
      GIR_BuildMI, /*InsnID*/0, /*Opcode*/GIMT_Encode2(AMDGPU::V_BFE_I32_e64),
      GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/0, // DstI[vdst]
      GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/1, // src
      GIR_AddImm8, /*InsnID*/0, /*Imm*/0,
      GIR_AddImm8, /*InsnID*/0, /*Imm*/16,
      GIR_ConstrainSelectedInstOperands, /*InsnID*/0,
      GIR_EraseFromParent, /*InsnID*/0,
      // GIR_Coverage, 2167,
      GIR_Done,
    // Label 3695: @240425
    GIM_Try, /*On fail goto*//*Label 3696*/ GIMT_Encode4(240468), // Rule ID 6265 //
      GIM_CheckType, /*MI*/0, /*Op*/1, /*Type*/GILLT_s1,
      GIM_CheckRegBankForClass, /*MI*/0, /*Op*/0, /*RC*/GIMT_Encode2(AMDGPU::VGPR_32RegClassID),
      // (sext:{ *:[i32] } i1:{ *:[i1] }:$src0)  =>  (V_CNDMASK_B32_e64:{ *:[i32] } 0:{ *:[i32] }, 0:{ *:[i32] }, 0:{ *:[i32] }, -1:{ *:[i32] }, i1:{ *:[i1] }:$src0)
      GIR_BuildMI, /*InsnID*/0, /*Opcode*/GIMT_Encode2(AMDGPU::V_CNDMASK_B32_e64),
      GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/0, // DstI[vdst]
      GIR_AddImm8, /*InsnID*/0, /*Imm*/0,
      GIR_AddImm8, /*InsnID*/0, /*Imm*/0,
      GIR_AddImm8, /*InsnID*/0, /*Imm*/0,
      GIR_AddImm8, /*InsnID*/0, /*Imm*/uint8_t(-1),
      GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/1, // src0
      GIR_ConstrainSelectedInstOperands, /*InsnID*/0,
      GIR_EraseFromParent, /*InsnID*/0,
      // GIR_Coverage, 6265,
      GIR_Done,
    // Label 3696: @240468
    GIM_Reject,
    // Label 3691: @240469
    GIM_Try, /*On fail goto*//*Label 3697*/ GIMT_Encode4(240695), // Rule ID 2168 //
      GIM_CheckType, /*MI*/0, /*Op*/1, /*Type*/GILLT_s16,
      GIM_CheckRegBankForClass, /*MI*/0, /*Op*/0, /*RC*/GIMT_Encode2(AMDGPU::VReg_64RegClassID),
      GIM_CheckCxxInsnPredicate, /*MI*/0, /*FnId*/GIMT_Encode2(GICXXPred_MI_Predicate_anonymous_23313),
      // (sext:{ *:[i64] } i16:{ *:[i16] }:$src)<<P:Predicate_anonymous_23313>>  =>  (REG_SEQUENCE:{ *:[i64] } VReg_64:{ *:[i32] }, (V_BFE_I32_e64:{ *:[i32] } ?:{ *:[i16] }:$src, (S_MOV_B32:{ *:[i16] } 0:{ *:[i32] }), (S_MOV_B32:{ *:[i16] } 16:{ *:[i32] })), sub0:{ *:[i32] }, (COPY_TO_REGCLASS:{ *:[i32] } (V_ASHRREV_I32_e32:{ *:[i16] } (S_MOV_B32:{ *:[i16] } 31:{ *:[i32] }), (V_BFE_I32_e64:{ *:[i32] } ?:{ *:[i16] }:$src, (S_MOV_B32:{ *:[i16] } 0:{ *:[i32] }), (S_MOV_B32:{ *:[i16] } 16:{ *:[i32] }))), VGPR_32:{ *:[i32] }), sub1:{ *:[i32] })
      GIR_MakeTempReg, /*TempRegID*/0, /*TypeID*/GILLT_s32,
      GIR_MakeTempReg, /*TempRegID*/1, /*TypeID*/GILLT_s16,
      GIR_MakeTempReg, /*TempRegID*/2, /*TypeID*/GILLT_s16,
      GIR_MakeTempReg, /*TempRegID*/3, /*TypeID*/GILLT_s32,
      GIR_MakeTempReg, /*TempRegID*/4, /*TypeID*/GILLT_s16,
      GIR_MakeTempReg, /*TempRegID*/5, /*TypeID*/GILLT_s16,
      GIR_MakeTempReg, /*TempRegID*/6, /*TypeID*/GILLT_s32,
      GIR_MakeTempReg, /*TempRegID*/7, /*TypeID*/GILLT_s16,
      GIR_MakeTempReg, /*TempRegID*/8, /*TypeID*/GILLT_s16,
      GIR_BuildMI, /*InsnID*/9, /*Opcode*/GIMT_Encode2(AMDGPU::S_MOV_B32),
      GIR_AddTempRegister, /*InsnID*/9, /*TempRegID*/8, /*TempRegFlags*/GIMT_Encode2(RegState::Define),
      GIR_AddImm8, /*InsnID*/9, /*Imm*/16,
      GIR_ConstrainSelectedInstOperands, /*InsnID*/9,
      GIR_BuildMI, /*InsnID*/8, /*Opcode*/GIMT_Encode2(AMDGPU::S_MOV_B32),
      GIR_AddTempRegister, /*InsnID*/8, /*TempRegID*/7, /*TempRegFlags*/GIMT_Encode2(RegState::Define),
      GIR_AddImm8, /*InsnID*/8, /*Imm*/0,
      GIR_ConstrainSelectedInstOperands, /*InsnID*/8,
      GIR_BuildMI, /*InsnID*/7, /*Opcode*/GIMT_Encode2(AMDGPU::V_BFE_I32_e64),
      GIR_AddTempRegister, /*InsnID*/7, /*TempRegID*/6, /*TempRegFlags*/GIMT_Encode2(RegState::Define),
      GIR_Copy, /*NewInsnID*/7, /*OldInsnID*/0, /*OpIdx*/1, // src
      GIR_AddSimpleTempRegister, /*InsnID*/7, /*TempRegID*/7,
      GIR_AddSimpleTempRegister, /*InsnID*/7, /*TempRegID*/8,
      GIR_ConstrainSelectedInstOperands, /*InsnID*/7,
      GIR_BuildMI, /*InsnID*/6, /*Opcode*/GIMT_Encode2(AMDGPU::S_MOV_B32),
      GIR_AddTempRegister, /*InsnID*/6, /*TempRegID*/5, /*TempRegFlags*/GIMT_Encode2(RegState::Define),
      GIR_AddImm8, /*InsnID*/6, /*Imm*/31,
      GIR_ConstrainSelectedInstOperands, /*InsnID*/6,
      GIR_BuildMI, /*InsnID*/5, /*Opcode*/GIMT_Encode2(AMDGPU::V_ASHRREV_I32_e32),
      GIR_AddTempRegister, /*InsnID*/5, /*TempRegID*/4, /*TempRegFlags*/GIMT_Encode2(RegState::Define),
      GIR_AddSimpleTempRegister, /*InsnID*/5, /*TempRegID*/5,
      GIR_AddSimpleTempRegister, /*InsnID*/5, /*TempRegID*/6,
      GIR_ConstrainSelectedInstOperands, /*InsnID*/5,
      GIR_BuildMI, /*InsnID*/4, /*Opcode*/GIMT_Encode2(TargetOpcode::COPY),
      GIR_AddTempRegister, /*InsnID*/4, /*TempRegID*/3, /*TempRegFlags*/GIMT_Encode2(RegState::Define),
      GIR_AddSimpleTempRegister, /*InsnID*/4, /*TempRegID*/4,
      GIR_ConstrainSelectedInstOperands, /*InsnID*/4,
      GIR_BuildMI, /*InsnID*/3, /*Opcode*/GIMT_Encode2(AMDGPU::S_MOV_B32),
      GIR_AddTempRegister, /*InsnID*/3, /*TempRegID*/2, /*TempRegFlags*/GIMT_Encode2(RegState::Define),
      GIR_AddImm8, /*InsnID*/3, /*Imm*/16,
      GIR_ConstrainSelectedInstOperands, /*InsnID*/3,
      GIR_BuildMI, /*InsnID*/2, /*Opcode*/GIMT_Encode2(AMDGPU::S_MOV_B32),
      GIR_AddTempRegister, /*InsnID*/2, /*TempRegID*/1, /*TempRegFlags*/GIMT_Encode2(RegState::Define),
      GIR_AddImm8, /*InsnID*/2, /*Imm*/0,
      GIR_ConstrainSelectedInstOperands, /*InsnID*/2,
      GIR_BuildMI, /*InsnID*/1, /*Opcode*/GIMT_Encode2(AMDGPU::V_BFE_I32_e64),
      GIR_AddTempRegister, /*InsnID*/1, /*TempRegID*/0, /*TempRegFlags*/GIMT_Encode2(RegState::Define),
      GIR_Copy, /*NewInsnID*/1, /*OldInsnID*/0, /*OpIdx*/1, // src
      GIR_AddSimpleTempRegister, /*InsnID*/1, /*TempRegID*/1,
      GIR_AddSimpleTempRegister, /*InsnID*/1, /*TempRegID*/2,
      GIR_ConstrainSelectedInstOperands, /*InsnID*/1,
      GIR_BuildMI, /*InsnID*/0, /*Opcode*/GIMT_Encode2(TargetOpcode::REG_SEQUENCE),
      GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/0, // DstI[dst]
      GIR_AddSimpleTempRegister, /*InsnID*/0, /*TempRegID*/0,
      GIR_AddImm8, /*InsnID*/0, /*SubRegIndex*/3,
      GIR_AddSimpleTempRegister, /*InsnID*/0, /*TempRegID*/3,
      GIR_AddImm8, /*InsnID*/0, /*SubRegIndex*/11,
      GIR_ConstrainOperandRC, /*InsnID*/0, /*Op*/0, GIMT_Encode2(AMDGPU::VReg_64RegClassID),
      GIR_ConstrainOperandRC, /*InsnID*/0, /*Op*/1, GIMT_Encode2(AMDGPU::VGPR_32RegClassID),
      GIR_ConstrainOperandRC, /*InsnID*/0, /*Op*/3, GIMT_Encode2(AMDGPU::VGPR_32RegClassID),
      GIR_EraseFromParent, /*InsnID*/0,
      // GIR_Coverage, 2168,
      GIR_Done,
    // Label 3697: @240695
    GIM_Try, /*On fail goto*//*Label 3698*/ GIMT_Encode4(240790), // Rule ID 6344 //
      GIM_CheckType, /*MI*/0, /*Op*/1, /*Type*/GILLT_s32,
      GIM_CheckRegBankForClass, /*MI*/0, /*Op*/0, /*RC*/GIMT_Encode2(AMDGPU::VReg_64RegClassID),
      GIM_CheckCxxInsnPredicate, /*MI*/0, /*FnId*/GIMT_Encode2(GICXXPred_MI_Predicate_anonymous_23313),
      // (sext:{ *:[i64] } i32:{ *:[i32] }:$src)<<P:Predicate_anonymous_23313>>  =>  (REG_SEQUENCE:{ *:[i64] } VReg_64:{ *:[i32] }, ?:{ *:[i32] }:$src, sub0:{ *:[i32] }, (COPY_TO_REGCLASS:{ *:[i32] } (V_ASHRREV_I32_e64:{ *:[i16] } 31:{ *:[i32] }, ?:{ *:[i32] }:$src), VGPR_32:{ *:[i32] }), sub1:{ *:[i32] })
      GIR_MakeTempReg, /*TempRegID*/0, /*TypeID*/GILLT_s32,
      GIR_MakeTempReg, /*TempRegID*/1, /*TypeID*/GILLT_s16,
      GIR_BuildMI, /*InsnID*/2, /*Opcode*/GIMT_Encode2(AMDGPU::V_ASHRREV_I32_e64),
      GIR_AddTempRegister, /*InsnID*/2, /*TempRegID*/1, /*TempRegFlags*/GIMT_Encode2(RegState::Define),
      GIR_AddImm8, /*InsnID*/2, /*Imm*/31,
      GIR_Copy, /*NewInsnID*/2, /*OldInsnID*/0, /*OpIdx*/1, // src
      GIR_ConstrainSelectedInstOperands, /*InsnID*/2,
      GIR_BuildMI, /*InsnID*/1, /*Opcode*/GIMT_Encode2(TargetOpcode::COPY),
      GIR_AddTempRegister, /*InsnID*/1, /*TempRegID*/0, /*TempRegFlags*/GIMT_Encode2(RegState::Define),
      GIR_AddSimpleTempRegister, /*InsnID*/1, /*TempRegID*/1,
      GIR_ConstrainSelectedInstOperands, /*InsnID*/1,
      GIR_BuildMI, /*InsnID*/0, /*Opcode*/GIMT_Encode2(TargetOpcode::REG_SEQUENCE),
      GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/0, // DstI[dst]
      GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/1, // src
      GIR_AddImm8, /*InsnID*/0, /*SubRegIndex*/3,
      GIR_AddSimpleTempRegister, /*InsnID*/0, /*TempRegID*/0,
      GIR_AddImm8, /*InsnID*/0, /*SubRegIndex*/11,
      GIR_ConstrainOperandRC, /*InsnID*/0, /*Op*/0, GIMT_Encode2(AMDGPU::VReg_64RegClassID),
      GIR_ConstrainOperandRC, /*InsnID*/0, /*Op*/1, GIMT_Encode2(AMDGPU::VGPR_32RegClassID),
      GIR_ConstrainOperandRC, /*InsnID*/0, /*Op*/3, GIMT_Encode2(AMDGPU::VGPR_32RegClassID),
      GIR_EraseFromParent, /*InsnID*/0,
      // GIR_Coverage, 6344,
      GIR_Done,
    // Label 3698: @240790
    GIM_Try, /*On fail goto*//*Label 3699*/ GIMT_Encode4(240902), // Rule ID 6345 //
      GIM_CheckType, /*MI*/0, /*Op*/1, /*Type*/GILLT_s1,
      GIM_CheckRegBankForClass, /*MI*/0, /*Op*/0, /*RC*/GIMT_Encode2(AMDGPU::VReg_64RegClassID),
      // (sext:{ *:[i64] } i1:{ *:[i1] }:$src)  =>  (REG_SEQUENCE:{ *:[i64] } VReg_64:{ *:[i32] }, (V_CNDMASK_B32_e64:{ *:[i16] } 0:{ *:[i32] }, 0:{ *:[i32] }, 0:{ *:[i32] }, -1:{ *:[i32] }, ?:{ *:[i1] }:$src), sub0:{ *:[i32] }, (V_CNDMASK_B32_e64:{ *:[i16] } 0:{ *:[i32] }, 0:{ *:[i32] }, 0:{ *:[i32] }, -1:{ *:[i32] }, ?:{ *:[i1] }:$src), sub1:{ *:[i32] })
      GIR_MakeTempReg, /*TempRegID*/0, /*TypeID*/GILLT_s16,
      GIR_MakeTempReg, /*TempRegID*/1, /*TypeID*/GILLT_s16,
      GIR_BuildMI, /*InsnID*/2, /*Opcode*/GIMT_Encode2(AMDGPU::V_CNDMASK_B32_e64),
      GIR_AddTempRegister, /*InsnID*/2, /*TempRegID*/1, /*TempRegFlags*/GIMT_Encode2(RegState::Define),
      GIR_AddImm8, /*InsnID*/2, /*Imm*/0,
      GIR_AddImm8, /*InsnID*/2, /*Imm*/0,
      GIR_AddImm8, /*InsnID*/2, /*Imm*/0,
      GIR_AddImm8, /*InsnID*/2, /*Imm*/uint8_t(-1),
      GIR_Copy, /*NewInsnID*/2, /*OldInsnID*/0, /*OpIdx*/1, // src
      GIR_ConstrainSelectedInstOperands, /*InsnID*/2,
      GIR_BuildMI, /*InsnID*/1, /*Opcode*/GIMT_Encode2(AMDGPU::V_CNDMASK_B32_e64),
      GIR_AddTempRegister, /*InsnID*/1, /*TempRegID*/0, /*TempRegFlags*/GIMT_Encode2(RegState::Define),
      GIR_AddImm8, /*InsnID*/1, /*Imm*/0,
      GIR_AddImm8, /*InsnID*/1, /*Imm*/0,
      GIR_AddImm8, /*InsnID*/1, /*Imm*/0,
      GIR_AddImm8, /*InsnID*/1, /*Imm*/uint8_t(-1),
      GIR_Copy, /*NewInsnID*/1, /*OldInsnID*/0, /*OpIdx*/1, // src
      GIR_ConstrainSelectedInstOperands, /*InsnID*/1,
      GIR_BuildMI, /*InsnID*/0, /*Opcode*/GIMT_Encode2(TargetOpcode::REG_SEQUENCE),
      GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/0, // DstI[dst]
      GIR_AddSimpleTempRegister, /*InsnID*/0, /*TempRegID*/0,
      GIR_AddImm8, /*InsnID*/0, /*SubRegIndex*/3,
      GIR_AddSimpleTempRegister, /*InsnID*/0, /*TempRegID*/1,
      GIR_AddImm8, /*InsnID*/0, /*SubRegIndex*/11,
      GIR_ConstrainOperandRC, /*InsnID*/0, /*Op*/0, GIMT_Encode2(AMDGPU::VReg_64RegClassID),
      GIR_ConstrainOperandRC, /*InsnID*/0, /*Op*/1, GIMT_Encode2(AMDGPU::VGPR_32RegClassID),
      GIR_ConstrainOperandRC, /*InsnID*/0, /*Op*/3, GIMT_Encode2(AMDGPU::VGPR_32RegClassID),
      GIR_EraseFromParent, /*InsnID*/0,
      // GIR_Coverage, 6345,
      GIR_Done,
    // Label 3699: @240902
    GIM_Reject,
    // Label 3692: @240903
    GIM_Reject,
    // Label 41: @240904
    GIM_SwitchType, /*MI*/0, /*Op*/0, /*[*/GIMT_Encode2(8), GIMT_Encode2(11), /*)*//*default:*//*Label 3703*/ GIMT_Encode4(242577),
    /*GILLT_s16*//*Label 3700*/ GIMT_Encode4(240927),
    /*GILLT_s32*//*Label 3701*/ GIMT_Encode4(240974),
    /*GILLT_s64*//*Label 3702*/ GIMT_Encode4(242289),
    // Label 3700: @240927
    GIM_Try, /*On fail goto*//*Label 3704*/ GIMT_Encode4(240973), // Rule ID 2158 //
      GIM_CheckFeatures, GIMT_Encode2(GIFBS_Has16BitInsts),
      GIM_CheckType, /*MI*/0, /*Op*/1, /*Type*/GILLT_s1,
      GIM_CheckRegBankForClass, /*MI*/0, /*Op*/0, /*RC*/GIMT_Encode2(AMDGPU::VGPR_32RegClassID),
      // (zext:{ *:[i16] } i1:{ *:[i1] }:$src)  =>  (V_CNDMASK_B32_e64:{ *:[i16] } 0:{ *:[i32] }, 0:{ *:[i32] }, 0:{ *:[i32] }, 1:{ *:[i32] }, ?:{ *:[i1] }:$src)
      GIR_BuildMI, /*InsnID*/0, /*Opcode*/GIMT_Encode2(AMDGPU::V_CNDMASK_B32_e64),
      GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/0, // DstI[vdst]
      GIR_AddImm8, /*InsnID*/0, /*Imm*/0,
      GIR_AddImm8, /*InsnID*/0, /*Imm*/0,
      GIR_AddImm8, /*InsnID*/0, /*Imm*/0,
      GIR_AddImm8, /*InsnID*/0, /*Imm*/1,
      GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/1, // src
      GIR_ConstrainSelectedInstOperands, /*InsnID*/0,
      GIR_EraseFromParent, /*InsnID*/0,
      // GIR_Coverage, 2158,
      GIR_Done,
    // Label 3704: @240973
    GIM_Reject,
    // Label 3701: @240974
    GIM_Try, /*On fail goto*//*Label 3705*/ GIMT_Encode4(241062), // Rule ID 2155 //
      GIM_CheckFeatures, GIMT_Encode2(GIFBS_Has16BitInsts_isGFX8GFX9),
      GIM_CheckType, /*MI*/0, /*Op*/1, /*Type*/GILLT_s16,
      GIM_CheckRegBankForClass, /*MI*/0, /*Op*/0, /*RC*/GIMT_Encode2(AMDGPU::VGPR_32RegClassID),
      GIM_RecordInsn, /*DefineMI*/1, /*MI*/0, /*OpIdx*/1, // MIs[1]
      GIM_CheckOpcode, /*MI*/1, GIMT_Encode2(TargetOpcode::G_ASHR),
      GIM_CheckType, /*MI*/1, /*Op*/1, /*Type*/GILLT_s16,
      GIM_CheckType, /*MI*/1, /*Op*/2, /*Type*/GILLT_s16,
      GIM_RecordInsn, /*DefineMI*/2, /*MI*/1, /*OpIdx*/2, // MIs[2]
      GIM_CheckOpcode, /*MI*/2, GIMT_Encode2(TargetOpcode::G_AND),
      GIM_CheckType, /*MI*/2, /*Op*/1, /*Type*/GILLT_s16,
      GIM_CheckType, /*MI*/2, /*Op*/2, /*Type*/GILLT_s16,
      GIM_RecordInsn, /*DefineMI*/3, /*MI*/2, /*OpIdx*/2, // MIs[3]
      GIM_CheckOpcode, /*MI*/3, GIMT_Encode2(TargetOpcode::G_CONSTANT),
      // MIs[3] Operand 1
      // No operand predicates
      GIM_CheckCxxInsnPredicate, /*MI*/2, /*FnId*/GIMT_Encode2(GICXXPred_MI_Predicate_csh_mask_16),
      GIM_CheckIsSafeToFold, /*InsnID*/1,
      GIM_CheckIsSafeToFold, /*InsnID*/2,
      GIM_CheckIsSafeToFold, /*InsnID*/3,
      // (zext:{ *:[i32] } (sra:{ *:[i16] } i16:{ *:[i16] }:$src1, (and:{ *:[i16] } i16:{ *:[i16] }:$src0, (imm:{ *:[i16] }))<<P:Predicate_csh_mask_16>>))  =>  (V_ASHRREV_I16_e64:{ *:[i32] } VSrc_b16:{ *:[i16] }:$src0, VSrc_b16:{ *:[i16] }:$src1)
      GIR_BuildMI, /*InsnID*/0, /*Opcode*/GIMT_Encode2(AMDGPU::V_ASHRREV_I16_e64),
      GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/0, // DstI[vdst]
      GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/2, /*OpIdx*/1, // src0
      GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/1, /*OpIdx*/1, // src1
      GIR_ConstrainSelectedInstOperands, /*InsnID*/0,
      GIR_EraseFromParent, /*InsnID*/0,
      // GIR_Coverage, 2155,
      GIR_Done,
    // Label 3705: @241062
    GIM_Try, /*On fail goto*//*Label 3706*/ GIMT_Encode4(241150), // Rule ID 2151 //
      GIM_CheckFeatures, GIMT_Encode2(GIFBS_Has16BitInsts_isGFX8GFX9),
      GIM_CheckType, /*MI*/0, /*Op*/1, /*Type*/GILLT_s16,
      GIM_CheckRegBankForClass, /*MI*/0, /*Op*/0, /*RC*/GIMT_Encode2(AMDGPU::VGPR_32RegClassID),
      GIM_RecordInsn, /*DefineMI*/1, /*MI*/0, /*OpIdx*/1, // MIs[1]
      GIM_CheckOpcode, /*MI*/1, GIMT_Encode2(TargetOpcode::G_LSHR),
      GIM_CheckType, /*MI*/1, /*Op*/1, /*Type*/GILLT_s16,
      GIM_CheckType, /*MI*/1, /*Op*/2, /*Type*/GILLT_s16,
      GIM_RecordInsn, /*DefineMI*/2, /*MI*/1, /*OpIdx*/2, // MIs[2]
      GIM_CheckOpcode, /*MI*/2, GIMT_Encode2(TargetOpcode::G_AND),
      GIM_CheckType, /*MI*/2, /*Op*/1, /*Type*/GILLT_s16,
      GIM_CheckType, /*MI*/2, /*Op*/2, /*Type*/GILLT_s16,
      GIM_RecordInsn, /*DefineMI*/3, /*MI*/2, /*OpIdx*/2, // MIs[3]
      GIM_CheckOpcode, /*MI*/3, GIMT_Encode2(TargetOpcode::G_CONSTANT),
      // MIs[3] Operand 1
      // No operand predicates
      GIM_CheckCxxInsnPredicate, /*MI*/2, /*FnId*/GIMT_Encode2(GICXXPred_MI_Predicate_csh_mask_16),
      GIM_CheckIsSafeToFold, /*InsnID*/1,
      GIM_CheckIsSafeToFold, /*InsnID*/2,
      GIM_CheckIsSafeToFold, /*InsnID*/3,
      // (zext:{ *:[i32] } (srl:{ *:[i16] } i16:{ *:[i16] }:$src1, (and:{ *:[i16] } i16:{ *:[i16] }:$src0, (imm:{ *:[i16] }))<<P:Predicate_csh_mask_16>>))  =>  (V_LSHRREV_B16_e64:{ *:[i32] } VSrc_b16:{ *:[i16] }:$src0, VSrc_b16:{ *:[i16] }:$src1)
      GIR_BuildMI, /*InsnID*/0, /*Opcode*/GIMT_Encode2(AMDGPU::V_LSHRREV_B16_e64),
      GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/0, // DstI[vdst]
      GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/2, /*OpIdx*/1, // src0
      GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/1, /*OpIdx*/1, // src1
      GIR_ConstrainSelectedInstOperands, /*InsnID*/0,
      GIR_EraseFromParent, /*InsnID*/0,
      // GIR_Coverage, 2151,
      GIR_Done,
    // Label 3706: @241150
    GIM_Try, /*On fail goto*//*Label 3707*/ GIMT_Encode4(241238), // Rule ID 2147 //
      GIM_CheckFeatures, GIMT_Encode2(GIFBS_Has16BitInsts_isGFX8GFX9),
      GIM_CheckType, /*MI*/0, /*Op*/1, /*Type*/GILLT_s16,
      GIM_CheckRegBankForClass, /*MI*/0, /*Op*/0, /*RC*/GIMT_Encode2(AMDGPU::VGPR_32RegClassID),
      GIM_RecordInsn, /*DefineMI*/1, /*MI*/0, /*OpIdx*/1, // MIs[1]
      GIM_CheckOpcode, /*MI*/1, GIMT_Encode2(TargetOpcode::G_SHL),
      GIM_CheckType, /*MI*/1, /*Op*/1, /*Type*/GILLT_s16,
      GIM_CheckType, /*MI*/1, /*Op*/2, /*Type*/GILLT_s16,
      GIM_RecordInsn, /*DefineMI*/2, /*MI*/1, /*OpIdx*/2, // MIs[2]
      GIM_CheckOpcode, /*MI*/2, GIMT_Encode2(TargetOpcode::G_AND),
      GIM_CheckType, /*MI*/2, /*Op*/1, /*Type*/GILLT_s16,
      GIM_CheckType, /*MI*/2, /*Op*/2, /*Type*/GILLT_s16,
      GIM_RecordInsn, /*DefineMI*/3, /*MI*/2, /*OpIdx*/2, // MIs[3]
      GIM_CheckOpcode, /*MI*/3, GIMT_Encode2(TargetOpcode::G_CONSTANT),
      // MIs[3] Operand 1
      // No operand predicates
      GIM_CheckCxxInsnPredicate, /*MI*/2, /*FnId*/GIMT_Encode2(GICXXPred_MI_Predicate_csh_mask_16),
      GIM_CheckIsSafeToFold, /*InsnID*/1,
      GIM_CheckIsSafeToFold, /*InsnID*/2,
      GIM_CheckIsSafeToFold, /*InsnID*/3,
      // (zext:{ *:[i32] } (shl:{ *:[i16] } i16:{ *:[i16] }:$src1, (and:{ *:[i16] } i16:{ *:[i16] }:$src0, (imm:{ *:[i16] }))<<P:Predicate_csh_mask_16>>))  =>  (V_LSHLREV_B16_e64:{ *:[i32] } VSrc_b16:{ *:[i16] }:$src0, VSrc_b16:{ *:[i16] }:$src1)
      GIR_BuildMI, /*InsnID*/0, /*Opcode*/GIMT_Encode2(AMDGPU::V_LSHLREV_B16_e64),
      GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/0, // DstI[vdst]
      GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/2, /*OpIdx*/1, // src0
      GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/1, /*OpIdx*/1, // src1
      GIR_ConstrainSelectedInstOperands, /*InsnID*/0,
      GIR_EraseFromParent, /*InsnID*/0,
      // GIR_Coverage, 2147,
      GIR_Done,
    // Label 3707: @241238
    GIM_Try, /*On fail goto*//*Label 3708*/ GIMT_Encode4(241312), // Rule ID 2133 //
      GIM_CheckFeatures, GIMT_Encode2(GIFBS_Has16BitInsts_isGFX8GFX9),
      GIM_CheckType, /*MI*/0, /*Op*/1, /*Type*/GILLT_s16,
      GIM_CheckRegBankForClass, /*MI*/0, /*Op*/0, /*RC*/GIMT_Encode2(AMDGPU::VGPR_32RegClassID),
      GIM_RecordInsn, /*DefineMI*/1, /*MI*/0, /*OpIdx*/1, // MIs[1]
      GIM_CheckOpcode, /*MI*/1, GIMT_Encode2(TargetOpcode::G_ADD),
      GIM_CheckType, /*MI*/1, /*Op*/1, /*Type*/GILLT_s16,
      GIM_CheckType, /*MI*/1, /*Op*/2, /*Type*/GILLT_s16,
      GIM_RecordInsn, /*DefineMI*/2, /*MI*/1, /*OpIdx*/2, // MIs[2]
      GIM_CheckOpcode, /*MI*/2, GIMT_Encode2(TargetOpcode::G_CONSTANT),
      GIM_CheckI64ImmPredicate, /*MI*/2, /*Predicate*/GIMT_Encode2(GICXXPred_I64_Predicate_NegSubInlineIntConst16),
      // MIs[2] Operand 1
      // No operand predicates
      GIM_CheckIsSafeToFold, /*InsnID*/1,
      GIM_CheckIsSafeToFold, /*InsnID*/2,
      // (zext:{ *:[i32] } (add:{ *:[i16] } i16:{ *:[i16] }:$src0, (imm:{ *:[i16] })<<P:Predicate_NegSubInlineIntConst16>><<X:NegateImm>>:$src1))  =>  (V_SUB_U16_e64:{ *:[i32] } VSrc_b16:{ *:[i16] }:$src0, (NegateImm:{ *:[i16 i32 bf16 f16 f32 v2i16 v2f16 v2bf16] } (imm:{ *:[i16] })<<P:Predicate_NegSubInlineIntConst16>>:$src1))
      GIR_BuildMI, /*InsnID*/0, /*Opcode*/GIMT_Encode2(AMDGPU::V_SUB_U16_e64),
      GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/0, // DstI[vdst]
      GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/1, /*OpIdx*/1, // src0
      GIR_CustomRenderer, /*InsnID*/0, /*OldInsnID*/2, /*Renderer*/GIMT_Encode2(GICR_renderNegateImm), // src1
      GIR_AddImm8, /*InsnID*/0, /*Imm*/0,
      GIR_ConstrainSelectedInstOperands, /*InsnID*/0,
      GIR_EraseFromParent, /*InsnID*/0,
      // GIR_Coverage, 2133,
      GIR_Done,
    // Label 3708: @241312
    GIM_Try, /*On fail goto*//*Label 3709*/ GIMT_Encode4(241393), // Rule ID 2169 //
      GIM_CheckFeatures, GIMT_Encode2(GIFBS_Has16BitInsts_isGFX8GFX9),
      GIM_CheckType, /*MI*/0, /*Op*/1, /*Type*/GILLT_s16,
      GIM_CheckRegBankForClass, /*MI*/0, /*Op*/0, /*RC*/GIMT_Encode2(AMDGPU::VGPR_32RegClassID),
      GIM_RecordInsn, /*DefineMI*/1, /*MI*/0, /*OpIdx*/1, // MIs[1]
      GIM_CheckOpcode, /*MI*/1, GIMT_Encode2(TargetOpcode::G_ADD),
      GIM_CheckType, /*MI*/1, /*Op*/1, /*Type*/GILLT_s16,
      GIM_CheckType, /*MI*/1, /*Op*/2, /*Type*/GILLT_s16,
      GIM_RecordInsn, /*DefineMI*/2, /*MI*/1, /*OpIdx*/1, // MIs[2]
      GIM_CheckOpcode, /*MI*/2, GIMT_Encode2(TargetOpcode::G_MUL),
      GIM_CheckType, /*MI*/2, /*Op*/1, /*Type*/GILLT_s16,
      GIM_CheckType, /*MI*/2, /*Op*/2, /*Type*/GILLT_s16,
      GIM_CheckIsSafeToFold, /*InsnID*/1,
      GIM_CheckIsSafeToFold, /*InsnID*/2,
      // (zext:{ *:[i32] } (add:{ *:[i16] } (mul:{ *:[i16] } i16:{ *:[i16] }:$src0, i16:{ *:[i16] }:$src1), i16:{ *:[i16] }:$src2))  =>  (V_MAD_U16_e64:{ *:[i32] } VSrc_b16:{ *:[i16] }:$src0, VSrc_b16:{ *:[i16] }:$src1, VSrc_b16:{ *:[i16] }:$src2)
      GIR_BuildMI, /*InsnID*/0, /*Opcode*/GIMT_Encode2(AMDGPU::V_MAD_U16_e64),
      GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/0, // DstI[vdst]
      GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/2, /*OpIdx*/1, // src0
      GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/2, /*OpIdx*/2, // src1
      GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/1, /*OpIdx*/2, // src2
      GIR_AddImm8, /*InsnID*/0, /*Imm*/0,
      GIR_ConstrainSelectedInstOperands, /*InsnID*/0,
      GIR_EraseFromParent, /*InsnID*/0,
      // GIR_Coverage, 2169,
      GIR_Done,
    // Label 3709: @241393
    GIM_Try, /*On fail goto*//*Label 3710*/ GIMT_Encode4(241474), // Rule ID 7206 //
      GIM_CheckFeatures, GIMT_Encode2(GIFBS_Has16BitInsts_isGFX8GFX9),
      GIM_CheckType, /*MI*/0, /*Op*/1, /*Type*/GILLT_s16,
      GIM_CheckRegBankForClass, /*MI*/0, /*Op*/0, /*RC*/GIMT_Encode2(AMDGPU::VGPR_32RegClassID),
      GIM_RecordInsn, /*DefineMI*/1, /*MI*/0, /*OpIdx*/1, // MIs[1]
      GIM_CheckOpcode, /*MI*/1, GIMT_Encode2(TargetOpcode::G_ADD),
      GIM_CheckType, /*MI*/1, /*Op*/1, /*Type*/GILLT_s16,
      GIM_CheckType, /*MI*/1, /*Op*/2, /*Type*/GILLT_s16,
      GIM_RecordInsn, /*DefineMI*/2, /*MI*/1, /*OpIdx*/2, // MIs[2]
      GIM_CheckOpcode, /*MI*/2, GIMT_Encode2(TargetOpcode::G_MUL),
      GIM_CheckType, /*MI*/2, /*Op*/1, /*Type*/GILLT_s16,
      GIM_CheckType, /*MI*/2, /*Op*/2, /*Type*/GILLT_s16,
      GIM_CheckIsSafeToFold, /*InsnID*/1,
      GIM_CheckIsSafeToFold, /*InsnID*/2,
      // (zext:{ *:[i32] } (add:{ *:[i16] } i16:{ *:[i16] }:$src2, (mul:{ *:[i16] } i16:{ *:[i16] }:$src0, i16:{ *:[i16] }:$src1)))  =>  (V_MAD_U16_e64:{ *:[i32] } VSrc_b16:{ *:[i16] }:$src0, VSrc_b16:{ *:[i16] }:$src1, VSrc_b16:{ *:[i16] }:$src2)
      GIR_BuildMI, /*InsnID*/0, /*Opcode*/GIMT_Encode2(AMDGPU::V_MAD_U16_e64),
      GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/0, // DstI[vdst]
      GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/2, /*OpIdx*/1, // src0
      GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/2, /*OpIdx*/2, // src1
      GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/1, /*OpIdx*/1, // src2
      GIR_AddImm8, /*InsnID*/0, /*Imm*/0,
      GIR_ConstrainSelectedInstOperands, /*InsnID*/0,
      GIR_EraseFromParent, /*InsnID*/0,
      // GIR_Coverage, 7206,
      GIR_Done,
    // Label 3710: @241474
    GIM_Try, /*On fail goto*//*Label 3711*/ GIMT_Encode4(241552), // Rule ID 6397 //
      GIM_CheckFeatures, GIMT_Encode2(GIFBS_isGFX8Plus),
      GIM_CheckType, /*MI*/0, /*Op*/1, /*Type*/GILLT_s16,
      GIM_CheckRegBankForClass, /*MI*/0, /*Op*/0, /*RC*/GIMT_Encode2(AMDGPU::VGPR_32RegClassID),
      GIM_RecordInsn, /*DefineMI*/1, /*MI*/0, /*OpIdx*/1, // MIs[1]
      GIM_CheckOpcode, /*MI*/1, GIMT_Encode2(TargetOpcode::G_BSWAP),
      GIM_CheckType, /*MI*/1, /*Op*/1, /*Type*/GILLT_s16,
      GIM_CheckIsSafeToFold, /*InsnID*/1,
      // (zext:{ *:[i32] } (bswap:{ *:[i16] } i16:{ *:[i16] }:$a))  =>  (V_PERM_B32_e64:{ *:[i32] } 0:{ *:[i32] }, VSrc_b32:{ *:[i16] }:$a, (S_MOV_B32:{ *:[i16] } 202113025:{ *:[i32] }))
      GIR_MakeTempReg, /*TempRegID*/0, /*TypeID*/GILLT_s16,
      GIR_BuildMI, /*InsnID*/1, /*Opcode*/GIMT_Encode2(AMDGPU::S_MOV_B32),
      GIR_AddTempRegister, /*InsnID*/1, /*TempRegID*/0, /*TempRegFlags*/GIMT_Encode2(RegState::Define),
      GIR_AddImm, /*InsnID*/1, /*Imm*/GIMT_Encode8(202113025),
      GIR_ConstrainSelectedInstOperands, /*InsnID*/1,
      GIR_BuildMI, /*InsnID*/0, /*Opcode*/GIMT_Encode2(AMDGPU::V_PERM_B32_e64),
      GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/0, // DstI[vdst]
      GIR_AddImm8, /*InsnID*/0, /*Imm*/0,
      GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/1, /*OpIdx*/1, // a
      GIR_AddSimpleTempRegister, /*InsnID*/0, /*TempRegID*/0,
      GIR_ConstrainSelectedInstOperands, /*InsnID*/0,
      GIR_EraseFromParent, /*InsnID*/0,
      // GIR_Coverage, 6397,
      GIR_Done,
    // Label 3711: @241552
    GIM_Try, /*On fail goto*//*Label 3712*/ GIMT_Encode4(241611), // Rule ID 2124 //
      GIM_CheckFeatures, GIMT_Encode2(GIFBS_Has16BitInsts_isGFX8GFX9),
      GIM_CheckType, /*MI*/0, /*Op*/1, /*Type*/GILLT_s16,
      GIM_CheckRegBankForClass, /*MI*/0, /*Op*/0, /*RC*/GIMT_Encode2(AMDGPU::VGPR_32RegClassID),
      GIM_RecordInsn, /*DefineMI*/1, /*MI*/0, /*OpIdx*/1, // MIs[1]
      GIM_CheckOpcode, /*MI*/1, GIMT_Encode2(TargetOpcode::G_ADD),
      GIM_CheckType, /*MI*/1, /*Op*/1, /*Type*/GILLT_s16,
      GIM_CheckType, /*MI*/1, /*Op*/2, /*Type*/GILLT_s16,
      GIM_CheckIsSafeToFold, /*InsnID*/1,
      // (zext:{ *:[i32] } (add:{ *:[i16] } i16:{ *:[i16] }:$src0, i16:{ *:[i16] }:$src1))  =>  (V_ADD_U16_e64:{ *:[i32] } VSrc_b16:{ *:[i16] }:$src0, VSrc_b16:{ *:[i16] }:$src1)
      GIR_BuildMI, /*InsnID*/0, /*Opcode*/GIMT_Encode2(AMDGPU::V_ADD_U16_e64),
      GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/0, // DstI[vdst]
      GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/1, /*OpIdx*/1, // src0
      GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/1, /*OpIdx*/2, // src1
      GIR_AddImm8, /*InsnID*/0, /*Imm*/0,
      GIR_ConstrainSelectedInstOperands, /*InsnID*/0,
      GIR_EraseFromParent, /*InsnID*/0,
      // GIR_Coverage, 2124,
      GIR_Done,
    // Label 3712: @241611
    GIM_Try, /*On fail goto*//*Label 3713*/ GIMT_Encode4(241667), // Rule ID 2154 //
      GIM_CheckFeatures, GIMT_Encode2(GIFBS_Has16BitInsts_isGFX8GFX9),
      GIM_CheckType, /*MI*/0, /*Op*/1, /*Type*/GILLT_s16,
      GIM_CheckRegBankForClass, /*MI*/0, /*Op*/0, /*RC*/GIMT_Encode2(AMDGPU::VGPR_32RegClassID),
      GIM_RecordInsn, /*DefineMI*/1, /*MI*/0, /*OpIdx*/1, // MIs[1]
      GIM_CheckOpcode, /*MI*/1, GIMT_Encode2(TargetOpcode::G_ASHR),
      GIM_CheckType, /*MI*/1, /*Op*/1, /*Type*/GILLT_s16,
      GIM_CheckType, /*MI*/1, /*Op*/2, /*Type*/GILLT_s16,
      GIM_CheckIsSafeToFold, /*InsnID*/1,
      // (zext:{ *:[i32] } (sra:{ *:[i16] } i16:{ *:[i16] }:$src1, i16:{ *:[i16] }:$src0))  =>  (V_ASHRREV_I16_e64:{ *:[i32] } VSrc_b16:{ *:[i16] }:$src0, VSrc_b16:{ *:[i16] }:$src1)
      GIR_BuildMI, /*InsnID*/0, /*Opcode*/GIMT_Encode2(AMDGPU::V_ASHRREV_I16_e64),
      GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/0, // DstI[vdst]
      GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/1, /*OpIdx*/2, // src0
      GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/1, /*OpIdx*/1, // src1
      GIR_ConstrainSelectedInstOperands, /*InsnID*/0,
      GIR_EraseFromParent, /*InsnID*/0,
      // GIR_Coverage, 2154,
      GIR_Done,
    // Label 3713: @241667
    GIM_Try, /*On fail goto*//*Label 3714*/ GIMT_Encode4(241723), // Rule ID 2150 //
      GIM_CheckFeatures, GIMT_Encode2(GIFBS_Has16BitInsts_isGFX8GFX9),
      GIM_CheckType, /*MI*/0, /*Op*/1, /*Type*/GILLT_s16,
      GIM_CheckRegBankForClass, /*MI*/0, /*Op*/0, /*RC*/GIMT_Encode2(AMDGPU::VGPR_32RegClassID),
      GIM_RecordInsn, /*DefineMI*/1, /*MI*/0, /*OpIdx*/1, // MIs[1]
      GIM_CheckOpcode, /*MI*/1, GIMT_Encode2(TargetOpcode::G_LSHR),
      GIM_CheckType, /*MI*/1, /*Op*/1, /*Type*/GILLT_s16,
      GIM_CheckType, /*MI*/1, /*Op*/2, /*Type*/GILLT_s16,
      GIM_CheckIsSafeToFold, /*InsnID*/1,
      // (zext:{ *:[i32] } (srl:{ *:[i16] } i16:{ *:[i16] }:$src1, i16:{ *:[i16] }:$src0))  =>  (V_LSHRREV_B16_e64:{ *:[i32] } VSrc_b16:{ *:[i16] }:$src0, VSrc_b16:{ *:[i16] }:$src1)
      GIR_BuildMI, /*InsnID*/0, /*Opcode*/GIMT_Encode2(AMDGPU::V_LSHRREV_B16_e64),
      GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/0, // DstI[vdst]
      GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/1, /*OpIdx*/2, // src0
      GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/1, /*OpIdx*/1, // src1
      GIR_ConstrainSelectedInstOperands, /*InsnID*/0,
      GIR_EraseFromParent, /*InsnID*/0,
      // GIR_Coverage, 2150,
      GIR_Done,
    // Label 3714: @241723
    GIM_Try, /*On fail goto*//*Label 3715*/ GIMT_Encode4(241779), // Rule ID 2134 //
      GIM_CheckFeatures, GIMT_Encode2(GIFBS_Has16BitInsts_isGFX8GFX9),
      GIM_CheckType, /*MI*/0, /*Op*/1, /*Type*/GILLT_s16,
      GIM_CheckRegBankForClass, /*MI*/0, /*Op*/0, /*RC*/GIMT_Encode2(AMDGPU::VGPR_32RegClassID),
      GIM_RecordInsn, /*DefineMI*/1, /*MI*/0, /*OpIdx*/1, // MIs[1]
      GIM_CheckOpcode, /*MI*/1, GIMT_Encode2(TargetOpcode::G_MUL),
      GIM_CheckType, /*MI*/1, /*Op*/1, /*Type*/GILLT_s16,
      GIM_CheckType, /*MI*/1, /*Op*/2, /*Type*/GILLT_s16,
      GIM_CheckIsSafeToFold, /*InsnID*/1,
      // (zext:{ *:[i32] } (mul:{ *:[i16] } i16:{ *:[i16] }:$src0, i16:{ *:[i16] }:$src1))  =>  (V_MUL_LO_U16_e64:{ *:[i32] } VSrc_b16:{ *:[i16] }:$src0, VSrc_b16:{ *:[i16] }:$src1)
      GIR_BuildMI, /*InsnID*/0, /*Opcode*/GIMT_Encode2(AMDGPU::V_MUL_LO_U16_e64),
      GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/0, // DstI[vdst]
      GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/1, /*OpIdx*/1, // src0
      GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/1, /*OpIdx*/2, // src1
      GIR_ConstrainSelectedInstOperands, /*InsnID*/0,
      GIR_EraseFromParent, /*InsnID*/0,
      // GIR_Coverage, 2134,
      GIR_Done,
    // Label 3715: @241779
    GIM_Try, /*On fail goto*//*Label 3716*/ GIMT_Encode4(241835), // Rule ID 2146 //
      GIM_CheckFeatures, GIMT_Encode2(GIFBS_Has16BitInsts_isGFX8GFX9),
      GIM_CheckType, /*MI*/0, /*Op*/1, /*Type*/GILLT_s16,
      GIM_CheckRegBankForClass, /*MI*/0, /*Op*/0, /*RC*/GIMT_Encode2(AMDGPU::VGPR_32RegClassID),
      GIM_RecordInsn, /*DefineMI*/1, /*MI*/0, /*OpIdx*/1, // MIs[1]
      GIM_CheckOpcode, /*MI*/1, GIMT_Encode2(TargetOpcode::G_SHL),
      GIM_CheckType, /*MI*/1, /*Op*/1, /*Type*/GILLT_s16,
      GIM_CheckType, /*MI*/1, /*Op*/2, /*Type*/GILLT_s16,
      GIM_CheckIsSafeToFold, /*InsnID*/1,
      // (zext:{ *:[i32] } (shl:{ *:[i16] } i16:{ *:[i16] }:$src1, i16:{ *:[i16] }:$src0))  =>  (V_LSHLREV_B16_e64:{ *:[i32] } VSrc_b16:{ *:[i16] }:$src0, VSrc_b16:{ *:[i16] }:$src1)
      GIR_BuildMI, /*InsnID*/0, /*Opcode*/GIMT_Encode2(AMDGPU::V_LSHLREV_B16_e64),
      GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/0, // DstI[vdst]
      GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/1, /*OpIdx*/2, // src0
      GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/1, /*OpIdx*/1, // src1
      GIR_ConstrainSelectedInstOperands, /*InsnID*/0,
      GIR_EraseFromParent, /*InsnID*/0,
      // GIR_Coverage, 2146,
      GIR_Done,
    // Label 3716: @241835
    GIM_Try, /*On fail goto*//*Label 3717*/ GIMT_Encode4(241891), // Rule ID 2140 //
      GIM_CheckFeatures, GIMT_Encode2(GIFBS_Has16BitInsts_isGFX8GFX9),
      GIM_CheckType, /*MI*/0, /*Op*/1, /*Type*/GILLT_s16,
      GIM_CheckRegBankForClass, /*MI*/0, /*Op*/0, /*RC*/GIMT_Encode2(AMDGPU::VGPR_32RegClassID),
      GIM_RecordInsn, /*DefineMI*/1, /*MI*/0, /*OpIdx*/1, // MIs[1]
      GIM_CheckOpcode, /*MI*/1, GIMT_Encode2(TargetOpcode::G_SMAX),
      GIM_CheckType, /*MI*/1, /*Op*/1, /*Type*/GILLT_s16,
      GIM_CheckType, /*MI*/1, /*Op*/2, /*Type*/GILLT_s16,
      GIM_CheckIsSafeToFold, /*InsnID*/1,
      // (zext:{ *:[i32] } (smax:{ *:[i16] } i16:{ *:[i16] }:$src0, i16:{ *:[i16] }:$src1))  =>  (V_MAX_I16_e64:{ *:[i32] } VSrc_b16:{ *:[i16] }:$src0, VSrc_b16:{ *:[i16] }:$src1)
      GIR_BuildMI, /*InsnID*/0, /*Opcode*/GIMT_Encode2(AMDGPU::V_MAX_I16_e64),
      GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/0, // DstI[vdst]
      GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/1, /*OpIdx*/1, // src0
      GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/1, /*OpIdx*/2, // src1
      GIR_ConstrainSelectedInstOperands, /*InsnID*/0,
      GIR_EraseFromParent, /*InsnID*/0,
      // GIR_Coverage, 2140,
      GIR_Done,
    // Label 3717: @241891
    GIM_Try, /*On fail goto*//*Label 3718*/ GIMT_Encode4(241947), // Rule ID 2138 //
      GIM_CheckFeatures, GIMT_Encode2(GIFBS_Has16BitInsts_isGFX8GFX9),
      GIM_CheckType, /*MI*/0, /*Op*/1, /*Type*/GILLT_s16,
      GIM_CheckRegBankForClass, /*MI*/0, /*Op*/0, /*RC*/GIMT_Encode2(AMDGPU::VGPR_32RegClassID),
      GIM_RecordInsn, /*DefineMI*/1, /*MI*/0, /*OpIdx*/1, // MIs[1]
      GIM_CheckOpcode, /*MI*/1, GIMT_Encode2(TargetOpcode::G_SMIN),
      GIM_CheckType, /*MI*/1, /*Op*/1, /*Type*/GILLT_s16,
      GIM_CheckType, /*MI*/1, /*Op*/2, /*Type*/GILLT_s16,
      GIM_CheckIsSafeToFold, /*InsnID*/1,
      // (zext:{ *:[i32] } (smin:{ *:[i16] } i16:{ *:[i16] }:$src0, i16:{ *:[i16] }:$src1))  =>  (V_MIN_I16_e64:{ *:[i32] } VSrc_b16:{ *:[i16] }:$src0, VSrc_b16:{ *:[i16] }:$src1)
      GIR_BuildMI, /*InsnID*/0, /*Opcode*/GIMT_Encode2(AMDGPU::V_MIN_I16_e64),
      GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/0, // DstI[vdst]
      GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/1, /*OpIdx*/1, // src0
      GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/1, /*OpIdx*/2, // src1
      GIR_ConstrainSelectedInstOperands, /*InsnID*/0,
      GIR_EraseFromParent, /*InsnID*/0,
      // GIR_Coverage, 2138,
      GIR_Done,
    // Label 3718: @241947
    GIM_Try, /*On fail goto*//*Label 3719*/ GIMT_Encode4(242006), // Rule ID 2136 //
      GIM_CheckFeatures, GIMT_Encode2(GIFBS_Has16BitInsts_isGFX8GFX9),
      GIM_CheckType, /*MI*/0, /*Op*/1, /*Type*/GILLT_s16,
      GIM_CheckRegBankForClass, /*MI*/0, /*Op*/0, /*RC*/GIMT_Encode2(AMDGPU::VGPR_32RegClassID),
      GIM_RecordInsn, /*DefineMI*/1, /*MI*/0, /*OpIdx*/1, // MIs[1]
      GIM_CheckOpcode, /*MI*/1, GIMT_Encode2(TargetOpcode::G_SUB),
      GIM_CheckType, /*MI*/1, /*Op*/1, /*Type*/GILLT_s16,
      GIM_CheckType, /*MI*/1, /*Op*/2, /*Type*/GILLT_s16,
      GIM_CheckIsSafeToFold, /*InsnID*/1,
      // (zext:{ *:[i32] } (sub:{ *:[i16] } i16:{ *:[i16] }:$src0, i16:{ *:[i16] }:$src1))  =>  (V_SUB_U16_e64:{ *:[i32] } VSrc_b16:{ *:[i16] }:$src0, VSrc_b16:{ *:[i16] }:$src1)
      GIR_BuildMI, /*InsnID*/0, /*Opcode*/GIMT_Encode2(AMDGPU::V_SUB_U16_e64),
      GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/0, // DstI[vdst]
      GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/1, /*OpIdx*/1, // src0
      GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/1, /*OpIdx*/2, // src1
      GIR_AddImm8, /*InsnID*/0, /*Imm*/0,
      GIR_ConstrainSelectedInstOperands, /*InsnID*/0,
      GIR_EraseFromParent, /*InsnID*/0,
      // GIR_Coverage, 2136,
      GIR_Done,
    // Label 3719: @242006
    GIM_Try, /*On fail goto*//*Label 3720*/ GIMT_Encode4(242062), // Rule ID 2144 //
      GIM_CheckFeatures, GIMT_Encode2(GIFBS_Has16BitInsts_isGFX8GFX9),
      GIM_CheckType, /*MI*/0, /*Op*/1, /*Type*/GILLT_s16,
      GIM_CheckRegBankForClass, /*MI*/0, /*Op*/0, /*RC*/GIMT_Encode2(AMDGPU::VGPR_32RegClassID),
      GIM_RecordInsn, /*DefineMI*/1, /*MI*/0, /*OpIdx*/1, // MIs[1]
      GIM_CheckOpcode, /*MI*/1, GIMT_Encode2(TargetOpcode::G_UMAX),
      GIM_CheckType, /*MI*/1, /*Op*/1, /*Type*/GILLT_s16,
      GIM_CheckType, /*MI*/1, /*Op*/2, /*Type*/GILLT_s16,
      GIM_CheckIsSafeToFold, /*InsnID*/1,
      // (zext:{ *:[i32] } (umax:{ *:[i16] } i16:{ *:[i16] }:$src0, i16:{ *:[i16] }:$src1))  =>  (V_MAX_U16_e64:{ *:[i32] } VSrc_b16:{ *:[i16] }:$src0, VSrc_b16:{ *:[i16] }:$src1)
      GIR_BuildMI, /*InsnID*/0, /*Opcode*/GIMT_Encode2(AMDGPU::V_MAX_U16_e64),
      GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/0, // DstI[vdst]
      GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/1, /*OpIdx*/1, // src0
      GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/1, /*OpIdx*/2, // src1
      GIR_ConstrainSelectedInstOperands, /*InsnID*/0,
      GIR_EraseFromParent, /*InsnID*/0,
      // GIR_Coverage, 2144,
      GIR_Done,
    // Label 3720: @242062
    GIM_Try, /*On fail goto*//*Label 3721*/ GIMT_Encode4(242118), // Rule ID 2142 //
      GIM_CheckFeatures, GIMT_Encode2(GIFBS_Has16BitInsts_isGFX8GFX9),
      GIM_CheckType, /*MI*/0, /*Op*/1, /*Type*/GILLT_s16,
      GIM_CheckRegBankForClass, /*MI*/0, /*Op*/0, /*RC*/GIMT_Encode2(AMDGPU::VGPR_32RegClassID),
      GIM_RecordInsn, /*DefineMI*/1, /*MI*/0, /*OpIdx*/1, // MIs[1]
      GIM_CheckOpcode, /*MI*/1, GIMT_Encode2(TargetOpcode::G_UMIN),
      GIM_CheckType, /*MI*/1, /*Op*/1, /*Type*/GILLT_s16,
      GIM_CheckType, /*MI*/1, /*Op*/2, /*Type*/GILLT_s16,
      GIM_CheckIsSafeToFold, /*InsnID*/1,
      // (zext:{ *:[i32] } (umin:{ *:[i16] } i16:{ *:[i16] }:$src0, i16:{ *:[i16] }:$src1))  =>  (V_MIN_U16_e64:{ *:[i32] } VSrc_b16:{ *:[i16] }:$src0, VSrc_b16:{ *:[i16] }:$src1)
      GIR_BuildMI, /*InsnID*/0, /*Opcode*/GIMT_Encode2(AMDGPU::V_MIN_U16_e64),
      GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/0, // DstI[vdst]
      GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/1, /*OpIdx*/1, // src0
      GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/1, /*OpIdx*/2, // src1
      GIR_ConstrainSelectedInstOperands, /*InsnID*/0,
      GIR_EraseFromParent, /*InsnID*/0,
      // GIR_Coverage, 2142,
      GIR_Done,
    // Label 3721: @242118
    GIM_Try, /*On fail goto*//*Label 3722*/ GIMT_Encode4(242183), // Rule ID 1657 //
      GIM_CheckType, /*MI*/0, /*Op*/1, /*Type*/GILLT_s16,
      GIM_CheckRegBankForClass, /*MI*/0, /*Op*/0, /*RC*/GIMT_Encode2(AMDGPU::SReg_32RegClassID),
      GIM_CheckCxxInsnPredicate, /*MI*/0, /*FnId*/GIMT_Encode2(GICXXPred_MI_Predicate_anonymous_17677),
      // (zext:{ *:[i32] } i16:{ *:[i16] }:$src)<<P:Predicate_anonymous_17677>>  =>  (S_AND_B32:{ *:[i32] }:{ *:[i1] } (S_MOV_B32:{ *:[i1] } 65535:{ *:[i32] }), ?:{ *:[i16] }:$src)
      GIR_MakeTempReg, /*TempRegID*/0, /*TypeID*/GILLT_s1,
      GIR_BuildMI, /*InsnID*/1, /*Opcode*/GIMT_Encode2(AMDGPU::S_MOV_B32),
      GIR_AddTempRegister, /*InsnID*/1, /*TempRegID*/0, /*TempRegFlags*/GIMT_Encode2(RegState::Define),
      GIR_AddImm, /*InsnID*/1, /*Imm*/GIMT_Encode8(65535),
      GIR_ConstrainSelectedInstOperands, /*InsnID*/1,
      GIR_BuildMI, /*InsnID*/0, /*Opcode*/GIMT_Encode2(AMDGPU::S_AND_B32),
      GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/0, // DstI[sdst]
      GIR_AddSimpleTempRegister, /*InsnID*/0, /*TempRegID*/0,
      GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/1, // src
      GIR_SetImplicitDefDead, /*InsnID*/0, /*OpIdx for AMDGPU::SCC*/0,
      GIR_ConstrainSelectedInstOperands, /*InsnID*/0,
      GIR_EraseFromParent, /*InsnID*/0,
      // GIR_Coverage, 1657,
      GIR_Done,
    // Label 3722: @242183
    GIM_Try, /*On fail goto*//*Label 3723*/ GIMT_Encode4(242245), // Rule ID 6380 //
      GIM_CheckType, /*MI*/0, /*Op*/1, /*Type*/GILLT_s16,
      GIM_CheckRegBankForClass, /*MI*/0, /*Op*/0, /*RC*/GIMT_Encode2(AMDGPU::VGPR_32RegClassID),
      GIM_CheckCxxInsnPredicate, /*MI*/0, /*FnId*/GIMT_Encode2(GICXXPred_MI_Predicate_anonymous_35196),
      // (zext:{ *:[i32] } i16:{ *:[i16] }:$src)<<P:Predicate_anonymous_35196>>  =>  (V_AND_B32_e64:{ *:[i32] } (S_MOV_B32:{ *:[i16] } 65535:{ *:[i32] }), ?:{ *:[i16] }:$src)
      GIR_MakeTempReg, /*TempRegID*/0, /*TypeID*/GILLT_s16,
      GIR_BuildMI, /*InsnID*/1, /*Opcode*/GIMT_Encode2(AMDGPU::S_MOV_B32),
      GIR_AddTempRegister, /*InsnID*/1, /*TempRegID*/0, /*TempRegFlags*/GIMT_Encode2(RegState::Define),
      GIR_AddImm, /*InsnID*/1, /*Imm*/GIMT_Encode8(65535),
      GIR_ConstrainSelectedInstOperands, /*InsnID*/1,
      GIR_BuildMI, /*InsnID*/0, /*Opcode*/GIMT_Encode2(AMDGPU::V_AND_B32_e64),
      GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/0, // DstI[vdst]
      GIR_AddSimpleTempRegister, /*InsnID*/0, /*TempRegID*/0,
      GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/1, // src
      GIR_ConstrainSelectedInstOperands, /*InsnID*/0,
      GIR_EraseFromParent, /*InsnID*/0,
      // GIR_Coverage, 6380,
      GIR_Done,
    // Label 3723: @242245
    GIM_Try, /*On fail goto*//*Label 3724*/ GIMT_Encode4(242288), // Rule ID 6266 //
      GIM_CheckType, /*MI*/0, /*Op*/1, /*Type*/GILLT_s1,
      GIM_CheckRegBankForClass, /*MI*/0, /*Op*/0, /*RC*/GIMT_Encode2(AMDGPU::VGPR_32RegClassID),
      // (zext:{ *:[i32] } i1:{ *:[i1] }:$src0)  =>  (V_CNDMASK_B32_e64:{ *:[i32] } 0:{ *:[i32] }, 0:{ *:[i32] }, 0:{ *:[i32] }, 1:{ *:[i32] }, i1:{ *:[i1] }:$src0)
      GIR_BuildMI, /*InsnID*/0, /*Opcode*/GIMT_Encode2(AMDGPU::V_CNDMASK_B32_e64),
      GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/0, // DstI[vdst]
      GIR_AddImm8, /*InsnID*/0, /*Imm*/0,
      GIR_AddImm8, /*InsnID*/0, /*Imm*/0,
      GIR_AddImm8, /*InsnID*/0, /*Imm*/0,
      GIR_AddImm8, /*InsnID*/0, /*Imm*/1,
      GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/1, // src0
      GIR_ConstrainSelectedInstOperands, /*InsnID*/0,
      GIR_EraseFromParent, /*InsnID*/0,
      // GIR_Coverage, 6266,
      GIR_Done,
    // Label 3724: @242288
    GIM_Reject,
    // Label 3702: @242289
    GIM_Try, /*On fail goto*//*Label 3725*/ GIMT_Encode4(242407), // Rule ID 6381 //
      GIM_CheckType, /*MI*/0, /*Op*/1, /*Type*/GILLT_s16,
      GIM_CheckRegBankForClass, /*MI*/0, /*Op*/0, /*RC*/GIMT_Encode2(AMDGPU::VReg_64RegClassID),
      GIM_CheckCxxInsnPredicate, /*MI*/0, /*FnId*/GIMT_Encode2(GICXXPred_MI_Predicate_anonymous_35196),
      // (zext:{ *:[i64] } i16:{ *:[i16] }:$src)<<P:Predicate_anonymous_35196>>  =>  (REG_SEQUENCE:{ *:[i64] } VReg_64:{ *:[i32] }, (V_AND_B32_e64:{ *:[i16] } (S_MOV_B32:{ *:[i16] } 65535:{ *:[i32] }), ?:{ *:[i16] }:$src), sub0:{ *:[i32] }, (S_MOV_B32:{ *:[i1] } 0:{ *:[i32] }), sub1:{ *:[i32] })
      GIR_MakeTempReg, /*TempRegID*/0, /*TypeID*/GILLT_s16,
      GIR_MakeTempReg, /*TempRegID*/1, /*TypeID*/GILLT_s16,
      GIR_MakeTempReg, /*TempRegID*/2, /*TypeID*/GILLT_s1,
      GIR_BuildMI, /*InsnID*/3, /*Opcode*/GIMT_Encode2(AMDGPU::S_MOV_B32),
      GIR_AddTempRegister, /*InsnID*/3, /*TempRegID*/2, /*TempRegFlags*/GIMT_Encode2(RegState::Define),
      GIR_AddImm8, /*InsnID*/3, /*Imm*/0,
      GIR_ConstrainSelectedInstOperands, /*InsnID*/3,
      GIR_BuildMI, /*InsnID*/2, /*Opcode*/GIMT_Encode2(AMDGPU::S_MOV_B32),
      GIR_AddTempRegister, /*InsnID*/2, /*TempRegID*/1, /*TempRegFlags*/GIMT_Encode2(RegState::Define),
      GIR_AddImm, /*InsnID*/2, /*Imm*/GIMT_Encode8(65535),
      GIR_ConstrainSelectedInstOperands, /*InsnID*/2,
      GIR_BuildMI, /*InsnID*/1, /*Opcode*/GIMT_Encode2(AMDGPU::V_AND_B32_e64),
      GIR_AddTempRegister, /*InsnID*/1, /*TempRegID*/0, /*TempRegFlags*/GIMT_Encode2(RegState::Define),
      GIR_AddSimpleTempRegister, /*InsnID*/1, /*TempRegID*/1,
      GIR_Copy, /*NewInsnID*/1, /*OldInsnID*/0, /*OpIdx*/1, // src
      GIR_ConstrainSelectedInstOperands, /*InsnID*/1,
      GIR_BuildMI, /*InsnID*/0, /*Opcode*/GIMT_Encode2(TargetOpcode::REG_SEQUENCE),
      GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/0, // DstI[dst]
      GIR_AddSimpleTempRegister, /*InsnID*/0, /*TempRegID*/0,
      GIR_AddImm8, /*InsnID*/0, /*SubRegIndex*/3,
      GIR_AddSimpleTempRegister, /*InsnID*/0, /*TempRegID*/2,
      GIR_AddImm8, /*InsnID*/0, /*SubRegIndex*/11,
      GIR_ConstrainOperandRC, /*InsnID*/0, /*Op*/0, GIMT_Encode2(AMDGPU::VReg_64RegClassID),
      GIR_ConstrainOperandRC, /*InsnID*/0, /*Op*/1, GIMT_Encode2(AMDGPU::VGPR_32RegClassID),
      GIR_ConstrainOperandRC, /*InsnID*/0, /*Op*/3, GIMT_Encode2(AMDGPU::VGPR_32RegClassID),
      GIR_EraseFromParent, /*InsnID*/0,
      // GIR_Coverage, 6381,
      GIR_Done,
    // Label 3725: @242407
    GIM_Try, /*On fail goto*//*Label 3726*/ GIMT_Encode4(242477), // Rule ID 6339 //
      GIM_CheckType, /*MI*/0, /*Op*/1, /*Type*/GILLT_s32,
      GIM_CheckRegBankForClass, /*MI*/0, /*Op*/0, /*RC*/GIMT_Encode2(AMDGPU::SReg_64RegClassID),
      // (zext:{ *:[i64] } i32:{ *:[i32] }:$src)  =>  (REG_SEQUENCE:{ *:[i64] } SReg_64:{ *:[i32] }, ?:{ *:[i32] }:$src, sub0:{ *:[i32] }, (S_MOV_B32:{ *:[i1] } 0:{ *:[i32] }), sub1:{ *:[i32] })
      GIR_MakeTempReg, /*TempRegID*/0, /*TypeID*/GILLT_s1,
      GIR_BuildMI, /*InsnID*/1, /*Opcode*/GIMT_Encode2(AMDGPU::S_MOV_B32),
      GIR_AddTempRegister, /*InsnID*/1, /*TempRegID*/0, /*TempRegFlags*/GIMT_Encode2(RegState::Define),
      GIR_AddImm8, /*InsnID*/1, /*Imm*/0,
      GIR_ConstrainSelectedInstOperands, /*InsnID*/1,
      GIR_BuildMI, /*InsnID*/0, /*Opcode*/GIMT_Encode2(TargetOpcode::REG_SEQUENCE),
      GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/0, // DstI[dst]
      GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/1, // src
      GIR_AddImm8, /*InsnID*/0, /*SubRegIndex*/3,
      GIR_AddSimpleTempRegister, /*InsnID*/0, /*TempRegID*/0,
      GIR_AddImm8, /*InsnID*/0, /*SubRegIndex*/11,
      GIR_ConstrainOperandRC, /*InsnID*/0, /*Op*/0, GIMT_Encode2(AMDGPU::SReg_64RegClassID),
      GIR_ConstrainOperandRC, /*InsnID*/0, /*Op*/1, GIMT_Encode2(AMDGPU::SReg_32_XEXEC_HI_and_SReg_32_XM0RegClassID),
      GIR_ConstrainOperandRC, /*InsnID*/0, /*Op*/3, GIMT_Encode2(AMDGPU::SReg_32_XM0RegClassID),
      GIR_EraseFromParent, /*InsnID*/0,
      // GIR_Coverage, 6339,
      GIR_Done,
    // Label 3726: @242477
    GIM_Try, /*On fail goto*//*Label 3727*/ GIMT_Encode4(242576), // Rule ID 6341 //
      GIM_CheckType, /*MI*/0, /*Op*/1, /*Type*/GILLT_s1,
      GIM_CheckRegBankForClass, /*MI*/0, /*Op*/0, /*RC*/GIMT_Encode2(AMDGPU::VReg_64RegClassID),
      // (zext:{ *:[i64] } i1:{ *:[i1] }:$src)  =>  (REG_SEQUENCE:{ *:[i64] } VReg_64:{ *:[i32] }, (V_CNDMASK_B32_e64:{ *:[i16] } 0:{ *:[i32] }, 0:{ *:[i32] }, 0:{ *:[i32] }, 1:{ *:[i32] }, ?:{ *:[i1] }:$src), sub0:{ *:[i32] }, (S_MOV_B32:{ *:[i1] } 0:{ *:[i32] }), sub1:{ *:[i32] })
      GIR_MakeTempReg, /*TempRegID*/0, /*TypeID*/GILLT_s16,
      GIR_MakeTempReg, /*TempRegID*/1, /*TypeID*/GILLT_s1,
      GIR_BuildMI, /*InsnID*/2, /*Opcode*/GIMT_Encode2(AMDGPU::S_MOV_B32),
      GIR_AddTempRegister, /*InsnID*/2, /*TempRegID*/1, /*TempRegFlags*/GIMT_Encode2(RegState::Define),
      GIR_AddImm8, /*InsnID*/2, /*Imm*/0,
      GIR_ConstrainSelectedInstOperands, /*InsnID*/2,
      GIR_BuildMI, /*InsnID*/1, /*Opcode*/GIMT_Encode2(AMDGPU::V_CNDMASK_B32_e64),
      GIR_AddTempRegister, /*InsnID*/1, /*TempRegID*/0, /*TempRegFlags*/GIMT_Encode2(RegState::Define),
      GIR_AddImm8, /*InsnID*/1, /*Imm*/0,
      GIR_AddImm8, /*InsnID*/1, /*Imm*/0,
      GIR_AddImm8, /*InsnID*/1, /*Imm*/0,
      GIR_AddImm8, /*InsnID*/1, /*Imm*/1,
      GIR_Copy, /*NewInsnID*/1, /*OldInsnID*/0, /*OpIdx*/1, // src
      GIR_ConstrainSelectedInstOperands, /*InsnID*/1,
      GIR_BuildMI, /*InsnID*/0, /*Opcode*/GIMT_Encode2(TargetOpcode::REG_SEQUENCE),
      GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/0, // DstI[dst]
      GIR_AddSimpleTempRegister, /*InsnID*/0, /*TempRegID*/0,
      GIR_AddImm8, /*InsnID*/0, /*SubRegIndex*/3,
      GIR_AddSimpleTempRegister, /*InsnID*/0, /*TempRegID*/1,
      GIR_AddImm8, /*InsnID*/0, /*SubRegIndex*/11,
      GIR_ConstrainOperandRC, /*InsnID*/0, /*Op*/0, GIMT_Encode2(AMDGPU::VReg_64RegClassID),
      GIR_ConstrainOperandRC, /*InsnID*/0, /*Op*/1, GIMT_Encode2(AMDGPU::VGPR_32RegClassID),
      GIR_ConstrainOperandRC, /*InsnID*/0, /*Op*/3, GIMT_Encode2(AMDGPU::VGPR_32RegClassID),
      GIR_EraseFromParent, /*InsnID*/0,
      // GIR_Coverage, 6341,
      GIR_Done,
    // Label 3727: @242576
    GIM_Reject,
    // Label 3703: @242577
    GIM_Reject,
    // Label 42: @242578
    GIM_SwitchType, /*MI*/0, /*Op*/0, /*[*/GIMT_Encode2(8), GIMT_Encode2(12), /*)*//*default:*//*Label 3732*/ GIMT_Encode4(243993),
    /*GILLT_s16*//*Label 3728*/ GIMT_Encode4(242605),
    /*GILLT_s32*//*Label 3729*/ GIMT_Encode4(242805),
    /*GILLT_s64*//*Label 3730*/ GIMT_Encode4(243342),
    /*GILLT_v2s16*//*Label 3731*/ GIMT_Encode4(243807),
    // Label 3728: @242605
    GIM_Try, /*On fail goto*//*Label 3733*/ GIMT_Encode4(242804),
      GIM_CheckType, /*MI*/0, /*Op*/1, /*Type*/GILLT_s16,
      GIM_CheckType, /*MI*/0, /*Op*/2, /*Type*/GILLT_s16,
      GIM_CheckRegBankForClass, /*MI*/0, /*Op*/0, /*RC*/GIMT_Encode2(AMDGPU::VGPR_32RegClassID),
      GIM_Try, /*On fail goto*//*Label 3734*/ GIMT_Encode4(242684), // Rule ID 782 //
        GIM_CheckFeatures, GIMT_Encode2(GIFBS_Has16BitInsts_NotHasTrue16BitInsts),
        GIM_RecordInsn, /*DefineMI*/1, /*MI*/0, /*OpIdx*/2, // MIs[1]
        GIM_CheckOpcode, /*MI*/1, GIMT_Encode2(TargetOpcode::G_AND),
        GIM_CheckType, /*MI*/1, /*Op*/1, /*Type*/GILLT_s16,
        GIM_CheckType, /*MI*/1, /*Op*/2, /*Type*/GILLT_s16,
        GIM_RecordInsn, /*DefineMI*/2, /*MI*/1, /*OpIdx*/2, // MIs[2]
        GIM_CheckOpcode, /*MI*/2, GIMT_Encode2(TargetOpcode::G_CONSTANT),
        // MIs[2] Operand 1
        // No operand predicates
        GIM_CheckCxxInsnPredicate, /*MI*/1, /*FnId*/GIMT_Encode2(GICXXPred_MI_Predicate_csh_mask_16),
        GIM_CheckIsSafeToFold, /*InsnID*/1,
        GIM_CheckIsSafeToFold, /*InsnID*/2,
        // (shl:{ *:[i16] } i16:{ *:[i16] }:$src1, (and:{ *:[i16] } i16:{ *:[i16] }:$src0, (imm:{ *:[i16] }))<<P:Predicate_csh_mask_16>>)  =>  (V_LSHLREV_B16_e64:{ *:[i16] } i16:{ *:[i16] }:$src0, i16:{ *:[i16] }:$src1)
        GIR_BuildMI, /*InsnID*/0, /*Opcode*/GIMT_Encode2(AMDGPU::V_LSHLREV_B16_e64),
        GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/0, // DstI[vdst]
        GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/1, /*OpIdx*/1, // src0
        GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/1, // src1
        GIR_ConstrainSelectedInstOperands, /*InsnID*/0,
        GIR_EraseFromParent, /*InsnID*/0,
        // GIR_Coverage, 782,
        GIR_Done,
      // Label 3734: @242684
      GIM_Try, /*On fail goto*//*Label 3735*/ GIMT_Encode4(242745), // Rule ID 784 //
        GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasTrue16BitInsts),
        GIM_RecordInsn, /*DefineMI*/1, /*MI*/0, /*OpIdx*/2, // MIs[1]
        GIM_CheckOpcode, /*MI*/1, GIMT_Encode2(TargetOpcode::G_AND),
        GIM_CheckType, /*MI*/1, /*Op*/1, /*Type*/GILLT_s16,
        GIM_CheckType, /*MI*/1, /*Op*/2, /*Type*/GILLT_s16,
        GIM_RecordInsn, /*DefineMI*/2, /*MI*/1, /*OpIdx*/2, // MIs[2]
        GIM_CheckOpcode, /*MI*/2, GIMT_Encode2(TargetOpcode::G_CONSTANT),
        // MIs[2] Operand 1
        // No operand predicates
        GIM_CheckCxxInsnPredicate, /*MI*/1, /*FnId*/GIMT_Encode2(GICXXPred_MI_Predicate_csh_mask_16),
        GIM_CheckIsSafeToFold, /*InsnID*/1,
        GIM_CheckIsSafeToFold, /*InsnID*/2,
        // (shl:{ *:[i16] } i16:{ *:[i16] }:$src1, (and:{ *:[i16] } i16:{ *:[i16] }:$src0, (imm:{ *:[i16] }))<<P:Predicate_csh_mask_16>>)  =>  (V_LSHLREV_B16_t16_e64:{ *:[i16] } i16:{ *:[i16] }:$src0, i16:{ *:[i16] }:$src1)
        GIR_BuildMI, /*InsnID*/0, /*Opcode*/GIMT_Encode2(AMDGPU::V_LSHLREV_B16_t16_e64),
        GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/0, // DstI[vdst]
        GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/1, /*OpIdx*/1, // src0
        GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/1, // src1
        GIR_ConstrainSelectedInstOperands, /*InsnID*/0,
        GIR_EraseFromParent, /*InsnID*/0,
        // GIR_Coverage, 784,
        GIR_Done,
      // Label 3735: @242745
      GIM_Try, /*On fail goto*//*Label 3736*/ GIMT_Encode4(242774), // Rule ID 781 //
        GIM_CheckFeatures, GIMT_Encode2(GIFBS_Has16BitInsts_NotHasTrue16BitInsts),
        // (shl:{ *:[i16] } i16:{ *:[i16] }:$src1, i16:{ *:[i16] }:$src0)  =>  (V_LSHLREV_B16_e64:{ *:[i16] } i16:{ *:[i16] }:$src0, i16:{ *:[i16] }:$src1)
        GIR_BuildMI, /*InsnID*/0, /*Opcode*/GIMT_Encode2(AMDGPU::V_LSHLREV_B16_e64),
        GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/0, // DstI[vdst]
        GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/2, // src0
        GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/1, // src1
        GIR_ConstrainSelectedInstOperands, /*InsnID*/0,
        GIR_EraseFromParent, /*InsnID*/0,
        // GIR_Coverage, 781,
        GIR_Done,
      // Label 3736: @242774
      GIM_Try, /*On fail goto*//*Label 3737*/ GIMT_Encode4(242803), // Rule ID 783 //
        GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasTrue16BitInsts),
        // (shl:{ *:[i16] } i16:{ *:[i16] }:$src1, i16:{ *:[i16] }:$src0)  =>  (V_LSHLREV_B16_t16_e64:{ *:[i16] } i16:{ *:[i16] }:$src0, i16:{ *:[i16] }:$src1)
        GIR_BuildMI, /*InsnID*/0, /*Opcode*/GIMT_Encode2(AMDGPU::V_LSHLREV_B16_t16_e64),
        GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/0, // DstI[vdst]
        GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/2, // src0
        GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/1, // src1
        GIR_ConstrainSelectedInstOperands, /*InsnID*/0,
        GIR_EraseFromParent, /*InsnID*/0,
        // GIR_Coverage, 783,
        GIR_Done,
      // Label 3737: @242803
      GIM_Reject,
    // Label 3733: @242804
    GIM_Reject,
    // Label 3729: @242805
    GIM_Try, /*On fail goto*//*Label 3738*/ GIMT_Encode4(243341),
      GIM_CheckType, /*MI*/0, /*Op*/1, /*Type*/GILLT_s32,
      GIM_CheckType, /*MI*/0, /*Op*/2, /*Type*/GILLT_s32,
      GIM_Try, /*On fail goto*//*Label 3739*/ GIMT_Encode4(242926), // Rule ID 2187 //
        GIM_CheckFeatures, GIMT_Encode2(GIFBS_isGFX9Plus),
        GIM_CheckRegBankForClass, /*MI*/0, /*Op*/0, /*RC*/GIMT_Encode2(AMDGPU::VGPR_32RegClassID),
        GIM_RecordInsn, /*DefineMI*/1, /*MI*/0, /*OpIdx*/1, // MIs[1]
        GIM_CheckOpcode, /*MI*/1, GIMT_Encode2(TargetOpcode::G_ADD),
        GIM_CheckType, /*MI*/1, /*Op*/1, /*Type*/GILLT_s32,
        GIM_CheckType, /*MI*/1, /*Op*/2, /*Type*/GILLT_s32,
        GIM_RecordNamedOperand, /*MI*/1, /*Op*/1, /*StoreIdx*/0, // Name : pred:2:x
        GIM_RecordNamedOperand, /*MI*/1, /*Op*/2, /*StoreIdx*/1, // Name : pred:2:y
        GIM_CheckCxxInsnPredicate, /*MI*/1, /*FnId*/GIMT_Encode2(GICXXPred_MI_Predicate_anonymous_23606),
        GIM_RecordInsn, /*DefineMI*/2, /*MI*/0, /*OpIdx*/2, // MIs[2]
        GIM_CheckOpcode, /*MI*/2, GIMT_Encode2(TargetOpcode::G_AND),
        GIM_CheckType, /*MI*/2, /*Op*/1, /*Type*/GILLT_s32,
        GIM_CheckType, /*MI*/2, /*Op*/2, /*Type*/GILLT_s32,
        GIM_RecordNamedOperand, /*MI*/2, /*Op*/1, /*StoreIdx*/2, // Name : pred:2:z
        GIM_RecordInsn, /*DefineMI*/3, /*MI*/2, /*OpIdx*/2, // MIs[3]
        GIM_CheckOpcode, /*MI*/3, GIMT_Encode2(TargetOpcode::G_CONSTANT),
        // MIs[3] Operand 1
        // No operand predicates
        GIM_CheckCxxInsnPredicate, /*MI*/2, /*FnId*/GIMT_Encode2(GICXXPred_MI_Predicate_csh_mask_32),
        GIM_CheckCxxInsnPredicate, /*MI*/0, /*FnId*/GIMT_Encode2(GICXXPred_MI_Predicate_anonymous_23605),
        GIM_CheckIsSafeToFold, /*InsnID*/1,
        GIM_CheckIsSafeToFold, /*InsnID*/2,
        GIM_CheckIsSafeToFold, /*InsnID*/3,
        // (shl:{ *:[i32] } (add:{ *:[i32] } i32:{ *:[i32] }:$src0:$pred:2:x, i32:{ *:[i32] }:$src1:$pred:2:y)<<P:Predicate_anonymous_23606>>, (and:{ *:[i32] } i32:{ *:[i32] }:$src2:$pred:2:z, (imm:{ *:[i32] }))<<P:Predicate_csh_mask_32>>)<<P:2:Predicate_anonymous_23605>>  =>  (V_ADD_LSHL_U32_e64:{ *:[i32] } VSrc_b32:{ *:[i32] }:$src0, VSrc_b32:{ *:[i32] }:$src1, VSrc_b32:{ *:[i32] }:$src2)
        GIR_BuildMI, /*InsnID*/0, /*Opcode*/GIMT_Encode2(AMDGPU::V_ADD_LSHL_U32_e64),
        GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/0, // DstI[vdst]
        GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/1, /*OpIdx*/1, // src0
        GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/1, /*OpIdx*/2, // src1
        GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/2, /*OpIdx*/1, // src2
        GIR_ConstrainSelectedInstOperands, /*InsnID*/0,
        GIR_EraseFromParent, /*InsnID*/0,
        // GIR_Coverage, 2187,
        GIR_Done,
      // Label 3739: @242926
      GIM_Try, /*On fail goto*//*Label 3740*/ GIMT_Encode4(243006), // Rule ID 71 //
        GIM_CheckRegBankForClass, /*MI*/0, /*Op*/0, /*RC*/GIMT_Encode2(AMDGPU::SReg_32RegClassID),
        GIM_CheckRegBankForClass, /*MI*/0, /*Op*/1, /*RC*/GIMT_Encode2(AMDGPU::SReg_32RegClassID),
        GIM_RecordInsn, /*DefineMI*/1, /*MI*/0, /*OpIdx*/2, // MIs[1]
        GIM_CheckOpcode, /*MI*/1, GIMT_Encode2(TargetOpcode::G_AND),
        GIM_CheckType, /*MI*/1, /*Op*/1, /*Type*/GILLT_s32,
        GIM_CheckType, /*MI*/1, /*Op*/2, /*Type*/GILLT_s32,
        GIM_CheckRegBankForClass, /*MI*/1, /*Op*/1, /*RC*/GIMT_Encode2(AMDGPU::SReg_32RegClassID),
        GIM_RecordInsn, /*DefineMI*/2, /*MI*/1, /*OpIdx*/2, // MIs[2]
        GIM_CheckOpcode, /*MI*/2, GIMT_Encode2(TargetOpcode::G_CONSTANT),
        // MIs[2] Operand 1
        // No operand predicates
        GIM_CheckCxxInsnPredicate, /*MI*/1, /*FnId*/GIMT_Encode2(GICXXPred_MI_Predicate_csh_mask_32),
        GIM_CheckCxxInsnPredicate, /*MI*/0, /*FnId*/GIMT_Encode2(GICXXPred_MI_Predicate_anonymous_17618),
        GIM_CheckIsSafeToFold, /*InsnID*/1,
        GIM_CheckIsSafeToFold, /*InsnID*/2,
        // (shl:{ *:[i32] } SSrc_b32:{ *:[i32] }:$src0, (and:{ *:[i32] } SSrc_b32:{ *:[i32] }:$src1, (imm:{ *:[i32] }))<<P:Predicate_csh_mask_32>>)<<P:Predicate_anonymous_17618>>  =>  (S_LSHL_B32:{ *:[i32] }:{ *:[i1] } SSrc_b32:{ *:[i32] }:$src0, SSrc_b32:{ *:[i32] }:$src1)
        GIR_BuildMI, /*InsnID*/0, /*Opcode*/GIMT_Encode2(AMDGPU::S_LSHL_B32),
        GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/0, // DstI[sdst]
        GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/1, // src0
        GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/1, /*OpIdx*/1, // src1
        GIR_SetImplicitDefDead, /*InsnID*/0, /*OpIdx for AMDGPU::SCC*/0,
        GIR_ConstrainSelectedInstOperands, /*InsnID*/0,
        GIR_EraseFromParent, /*InsnID*/0,
        // GIR_Coverage, 71,
        GIR_Done,
      // Label 3740: @243006
      GIM_Try, /*On fail goto*//*Label 3741*/ GIMT_Encode4(243082), // Rule ID 2186 //
        GIM_CheckFeatures, GIMT_Encode2(GIFBS_isGFX9Plus),
        GIM_CheckRegBankForClass, /*MI*/0, /*Op*/0, /*RC*/GIMT_Encode2(AMDGPU::VGPR_32RegClassID),
        GIM_RecordInsn, /*DefineMI*/1, /*MI*/0, /*OpIdx*/1, // MIs[1]
        GIM_CheckOpcode, /*MI*/1, GIMT_Encode2(TargetOpcode::G_ADD),
        GIM_CheckType, /*MI*/1, /*Op*/1, /*Type*/GILLT_s32,
        GIM_CheckType, /*MI*/1, /*Op*/2, /*Type*/GILLT_s32,
        GIM_RecordNamedOperand, /*MI*/1, /*Op*/1, /*StoreIdx*/0, // Name : pred:2:x
        GIM_RecordNamedOperand, /*MI*/1, /*Op*/2, /*StoreIdx*/1, // Name : pred:2:y
        GIM_CheckCxxInsnPredicate, /*MI*/1, /*FnId*/GIMT_Encode2(GICXXPred_MI_Predicate_anonymous_23606),
        GIM_RecordNamedOperand, /*MI*/0, /*Op*/2, /*StoreIdx*/2, // Name : pred:2:z
        GIM_CheckCxxInsnPredicate, /*MI*/0, /*FnId*/GIMT_Encode2(GICXXPred_MI_Predicate_anonymous_23605),
        GIM_CheckIsSafeToFold, /*InsnID*/1,
        // (shl:{ *:[i32] } (add:{ *:[i32] } i32:{ *:[i32] }:$src0:$pred:2:x, i32:{ *:[i32] }:$src1:$pred:2:y)<<P:Predicate_anonymous_23606>>, i32:{ *:[i32] }:$src2:$pred:2:z)<<P:2:Predicate_anonymous_23605>>  =>  (V_ADD_LSHL_U32_e64:{ *:[i32] } VSrc_b32:{ *:[i32] }:$src0, VSrc_b32:{ *:[i32] }:$src1, VSrc_b32:{ *:[i32] }:$src2)
        GIR_BuildMI, /*InsnID*/0, /*Opcode*/GIMT_Encode2(AMDGPU::V_ADD_LSHL_U32_e64),
        GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/0, // DstI[vdst]
        GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/1, /*OpIdx*/1, // src0
        GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/1, /*OpIdx*/2, // src1
        GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/2, // src2
        GIR_ConstrainSelectedInstOperands, /*InsnID*/0,
        GIR_EraseFromParent, /*InsnID*/0,
        // GIR_Coverage, 2186,
        GIR_Done,
      // Label 3741: @243082
      GIM_Try, /*On fail goto*//*Label 3742*/ GIMT_Encode4(243120), // Rule ID 70 //
        GIM_CheckRegBankForClass, /*MI*/0, /*Op*/0, /*RC*/GIMT_Encode2(AMDGPU::SReg_32RegClassID),
        GIM_CheckRegBankForClass, /*MI*/0, /*Op*/1, /*RC*/GIMT_Encode2(AMDGPU::SReg_32RegClassID),
        GIM_CheckRegBankForClass, /*MI*/0, /*Op*/2, /*RC*/GIMT_Encode2(AMDGPU::SReg_32RegClassID),
        GIM_CheckCxxInsnPredicate, /*MI*/0, /*FnId*/GIMT_Encode2(GICXXPred_MI_Predicate_anonymous_17618),
        // (shl:{ *:[i32] } SSrc_b32:{ *:[i32] }:$src0, SSrc_b32:{ *:[i32] }:$src1)<<P:Predicate_anonymous_17618>>  =>  (S_LSHL_B32:{ *:[i32] }:{ *:[i1] } SSrc_b32:{ *:[i32] }:$src0, SSrc_b32:{ *:[i32] }:$src1)
        GIR_MutateOpcode, /*InsnID*/0, /*RecycleInsnID*/0, /*Opcode*/GIMT_Encode2(AMDGPU::S_LSHL_B32),
        GIR_AddImplicitDef, /*InsnID*/0, GIMT_Encode2(AMDGPU::SCC), GIMT_Encode2(RegState::Dead),
        GIR_ConstrainSelectedInstOperands, /*InsnID*/0,
        // GIR_Coverage, 70,
        GIR_Done,
      // Label 3742: @243120
      GIM_Try, /*On fail goto*//*Label 3743*/ GIMT_Encode4(243155), // Rule ID 2096 //
        GIM_CheckRegBankForClass, /*MI*/0, /*Op*/0, /*RC*/GIMT_Encode2(AMDGPU::VGPR_32RegClassID),
        GIM_CheckCxxInsnPredicate, /*MI*/0, /*FnId*/GIMT_Encode2(GICXXPred_MI_Predicate_anonymous_22543),
        // (shl:{ *:[i32] } i32:{ *:[i32] }:$src0, i32:{ *:[i32] }:$src1)<<P:Predicate_anonymous_22543>>  =>  (V_LSHLREV_B32_e64:{ *:[i32] } ?:{ *:[i32] }:$src1, ?:{ *:[i32] }:$src0)
        GIR_BuildMI, /*InsnID*/0, /*Opcode*/GIMT_Encode2(AMDGPU::V_LSHLREV_B32_e64),
        GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/0, // DstI[vdst]
        GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/2, // src1
        GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/1, // src0
        GIR_ConstrainSelectedInstOperands, /*InsnID*/0,
        GIR_EraseFromParent, /*InsnID*/0,
        // GIR_Coverage, 2096,
        GIR_Done,
      // Label 3743: @243155
      GIM_Try, /*On fail goto*//*Label 3744*/ GIMT_Encode4(243218), // Rule ID 752 //
        GIM_CheckRegBankForClass, /*MI*/0, /*Op*/0, /*RC*/GIMT_Encode2(AMDGPU::VGPR_32RegClassID),
        GIM_RecordInsn, /*DefineMI*/1, /*MI*/0, /*OpIdx*/2, // MIs[1]
        GIM_CheckOpcode, /*MI*/1, GIMT_Encode2(TargetOpcode::G_AND),
        GIM_CheckType, /*MI*/1, /*Op*/1, /*Type*/GILLT_s32,
        GIM_CheckType, /*MI*/1, /*Op*/2, /*Type*/GILLT_s32,
        GIM_RecordInsn, /*DefineMI*/2, /*MI*/1, /*OpIdx*/2, // MIs[2]
        GIM_CheckOpcode, /*MI*/2, GIMT_Encode2(TargetOpcode::G_CONSTANT),
        // MIs[2] Operand 1
        // No operand predicates
        GIM_CheckCxxInsnPredicate, /*MI*/1, /*FnId*/GIMT_Encode2(GICXXPred_MI_Predicate_csh_mask_32),
        GIM_CheckIsSafeToFold, /*InsnID*/1,
        GIM_CheckIsSafeToFold, /*InsnID*/2,
        // (shl:{ *:[i32] } i32:{ *:[i32] }:$src1, (and:{ *:[i32] } i32:{ *:[i32] }:$src0, (imm:{ *:[i32] }))<<P:Predicate_csh_mask_32>>)  =>  (V_LSHLREV_B32_e64:{ *:[i32] } i32:{ *:[i32] }:$src0, i32:{ *:[i32] }:$src1)
        GIR_BuildMI, /*InsnID*/0, /*Opcode*/GIMT_Encode2(AMDGPU::V_LSHLREV_B32_e64),
        GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/0, // DstI[vdst]
        GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/1, /*OpIdx*/1, // src0
        GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/1, // src1
        GIR_ConstrainSelectedInstOperands, /*InsnID*/0,
        GIR_EraseFromParent, /*InsnID*/0,
        // GIR_Coverage, 752,
        GIR_Done,
      // Label 3744: @243218
      GIM_Try, /*On fail goto*//*Label 3745*/ GIMT_Encode4(243284), // Rule ID 780 //
        GIM_CheckFeatures, GIMT_Encode2(GIFBS_isGFX6GFX7),
        GIM_CheckRegBankForClass, /*MI*/0, /*Op*/0, /*RC*/GIMT_Encode2(AMDGPU::VGPR_32RegClassID),
        GIM_RecordInsn, /*DefineMI*/1, /*MI*/0, /*OpIdx*/2, // MIs[1]
        GIM_CheckOpcode, /*MI*/1, GIMT_Encode2(TargetOpcode::G_AND),
        GIM_CheckType, /*MI*/1, /*Op*/1, /*Type*/GILLT_s32,
        GIM_CheckType, /*MI*/1, /*Op*/2, /*Type*/GILLT_s32,
        GIM_RecordInsn, /*DefineMI*/2, /*MI*/1, /*OpIdx*/2, // MIs[2]
        GIM_CheckOpcode, /*MI*/2, GIMT_Encode2(TargetOpcode::G_CONSTANT),
        // MIs[2] Operand 1
        // No operand predicates
        GIM_CheckCxxInsnPredicate, /*MI*/1, /*FnId*/GIMT_Encode2(GICXXPred_MI_Predicate_csh_mask_32),
        GIM_CheckIsSafeToFold, /*InsnID*/1,
        GIM_CheckIsSafeToFold, /*InsnID*/2,
        // (shl:{ *:[i32] } i32:{ *:[i32] }:$src0, (and:{ *:[i32] } i32:{ *:[i32] }:$src1, (imm:{ *:[i32] }))<<P:Predicate_csh_mask_32>>)  =>  (V_LSHL_B32_e64:{ *:[i32] } i32:{ *:[i32] }:$src0, i32:{ *:[i32] }:$src1)
        GIR_BuildMI, /*InsnID*/0, /*Opcode*/GIMT_Encode2(AMDGPU::V_LSHL_B32_e64),
        GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/0, // DstI[vdst]
        GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/1, // src0
        GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/1, /*OpIdx*/1, // src1
        GIR_ConstrainSelectedInstOperands, /*InsnID*/0,
        GIR_EraseFromParent, /*InsnID*/0,
        // GIR_Coverage, 780,
        GIR_Done,
      // Label 3745: @243284
      GIM_Try, /*On fail goto*//*Label 3746*/ GIMT_Encode4(243315), // Rule ID 751 //
        GIM_CheckRegBankForClass, /*MI*/0, /*Op*/0, /*RC*/GIMT_Encode2(AMDGPU::VGPR_32RegClassID),
        // (shl:{ *:[i32] } i32:{ *:[i32] }:$src1, i32:{ *:[i32] }:$src0)  =>  (V_LSHLREV_B32_e64:{ *:[i32] } i32:{ *:[i32] }:$src0, i32:{ *:[i32] }:$src1)
        GIR_BuildMI, /*InsnID*/0, /*Opcode*/GIMT_Encode2(AMDGPU::V_LSHLREV_B32_e64),
        GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/0, // DstI[vdst]
        GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/2, // src0
        GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/1, // src1
        GIR_ConstrainSelectedInstOperands, /*InsnID*/0,
        GIR_EraseFromParent, /*InsnID*/0,
        // GIR_Coverage, 751,
        GIR_Done,
      // Label 3746: @243315
      GIM_Try, /*On fail goto*//*Label 3747*/ GIMT_Encode4(243340), // Rule ID 779 //
        GIM_CheckFeatures, GIMT_Encode2(GIFBS_isGFX6GFX7),
        GIM_CheckRegBankForClass, /*MI*/0, /*Op*/0, /*RC*/GIMT_Encode2(AMDGPU::VGPR_32RegClassID),
        // (shl:{ *:[i32] } i32:{ *:[i32] }:$src0, i32:{ *:[i32] }:$src1)  =>  (V_LSHL_B32_e64:{ *:[i32] } i32:{ *:[i32] }:$src0, i32:{ *:[i32] }:$src1)
        GIR_MutateOpcode, /*InsnID*/0, /*RecycleInsnID*/0, /*Opcode*/GIMT_Encode2(AMDGPU::V_LSHL_B32_e64),
        GIR_AddImplicitUse, /*InsnID*/0, GIMT_Encode2(AMDGPU::EXEC),
        GIR_ConstrainSelectedInstOperands, /*InsnID*/0,
        // GIR_Coverage, 779,
        GIR_Done,
      // Label 3747: @243340
      GIM_Reject,
    // Label 3738: @243341
    GIM_Reject,
    // Label 3730: @243342
    GIM_Try, /*On fail goto*//*Label 3748*/ GIMT_Encode4(243806),
      GIM_CheckType, /*MI*/0, /*Op*/1, /*Type*/GILLT_s64,
      GIM_CheckType, /*MI*/0, /*Op*/2, /*Type*/GILLT_s32,
      GIM_Try, /*On fail goto*//*Label 3749*/ GIMT_Encode4(243435), // Rule ID 73 //
        GIM_CheckRegBankForClass, /*MI*/0, /*Op*/0, /*RC*/GIMT_Encode2(AMDGPU::SReg_64RegClassID),
        GIM_CheckRegBankForClass, /*MI*/0, /*Op*/1, /*RC*/GIMT_Encode2(AMDGPU::SReg_64RegClassID),
        GIM_RecordInsn, /*DefineMI*/1, /*MI*/0, /*OpIdx*/2, // MIs[1]
        GIM_CheckOpcode, /*MI*/1, GIMT_Encode2(TargetOpcode::G_AND),
        GIM_CheckType, /*MI*/1, /*Op*/1, /*Type*/GILLT_s32,
        GIM_CheckType, /*MI*/1, /*Op*/2, /*Type*/GILLT_s32,
        GIM_CheckRegBankForClass, /*MI*/1, /*Op*/1, /*RC*/GIMT_Encode2(AMDGPU::SReg_32RegClassID),
        GIM_RecordInsn, /*DefineMI*/2, /*MI*/1, /*OpIdx*/2, // MIs[2]
        GIM_CheckOpcode, /*MI*/2, GIMT_Encode2(TargetOpcode::G_CONSTANT),
        // MIs[2] Operand 1
        // No operand predicates
        GIM_CheckCxxInsnPredicate, /*MI*/1, /*FnId*/GIMT_Encode2(GICXXPred_MI_Predicate_csh_mask_64),
        GIM_CheckCxxInsnPredicate, /*MI*/0, /*FnId*/GIMT_Encode2(GICXXPred_MI_Predicate_anonymous_17619),
        GIM_CheckIsSafeToFold, /*InsnID*/1,
        GIM_CheckIsSafeToFold, /*InsnID*/2,
        // (shl:{ *:[i64] } SSrc_b64:{ *:[i64] }:$src0, (and:{ *:[i32] } SSrc_b32:{ *:[i32] }:$src1, (imm:{ *:[i32] }))<<P:Predicate_csh_mask_64>>)<<P:Predicate_anonymous_17619>>  =>  (S_LSHL_B64:{ *:[i64] }:{ *:[i1] } SSrc_b64:{ *:[i64] }:$src0, SSrc_b32:{ *:[i32] }:$src1)
        GIR_BuildMI, /*InsnID*/0, /*Opcode*/GIMT_Encode2(AMDGPU::S_LSHL_B64),
        GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/0, // DstI[sdst]
        GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/1, // src0
        GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/1, /*OpIdx*/1, // src1
        GIR_SetImplicitDefDead, /*InsnID*/0, /*OpIdx for AMDGPU::SCC*/0,
        GIR_ConstrainSelectedInstOperands, /*InsnID*/0,
        GIR_EraseFromParent, /*InsnID*/0,
        // GIR_Coverage, 73,
        GIR_Done,
      // Label 3749: @243435
      GIM_Try, /*On fail goto*//*Label 3750*/ GIMT_Encode4(243473), // Rule ID 72 //
        GIM_CheckRegBankForClass, /*MI*/0, /*Op*/0, /*RC*/GIMT_Encode2(AMDGPU::SReg_64RegClassID),
        GIM_CheckRegBankForClass, /*MI*/0, /*Op*/1, /*RC*/GIMT_Encode2(AMDGPU::SReg_64RegClassID),
        GIM_CheckRegBankForClass, /*MI*/0, /*Op*/2, /*RC*/GIMT_Encode2(AMDGPU::SReg_32RegClassID),
        GIM_CheckCxxInsnPredicate, /*MI*/0, /*FnId*/GIMT_Encode2(GICXXPred_MI_Predicate_anonymous_17619),
        // (shl:{ *:[i64] } SSrc_b64:{ *:[i64] }:$src0, SSrc_b32:{ *:[i32] }:$src1)<<P:Predicate_anonymous_17619>>  =>  (S_LSHL_B64:{ *:[i64] }:{ *:[i1] } SSrc_b64:{ *:[i64] }:$src0, SSrc_b32:{ *:[i32] }:$src1)
        GIR_MutateOpcode, /*InsnID*/0, /*RecycleInsnID*/0, /*Opcode*/GIMT_Encode2(AMDGPU::S_LSHL_B64),
        GIR_AddImplicitDef, /*InsnID*/0, GIMT_Encode2(AMDGPU::SCC), GIMT_Encode2(RegState::Dead),
        GIR_ConstrainSelectedInstOperands, /*InsnID*/0,
        // GIR_Coverage, 72,
        GIR_Done,
      // Label 3750: @243473
      GIM_Try, /*On fail goto*//*Label 3751*/ GIMT_Encode4(243547), // Rule ID 906 //
        GIM_CheckFeatures, GIMT_Encode2(GIFBS_isGFX6GFX7),
        GIM_CheckRegBankForClass, /*MI*/0, /*Op*/0, /*RC*/GIMT_Encode2(AMDGPU::VReg_64RegClassID),
        GIM_RecordInsn, /*DefineMI*/1, /*MI*/0, /*OpIdx*/2, // MIs[1]
        GIM_CheckOpcode, /*MI*/1, GIMT_Encode2(TargetOpcode::G_AND),
        GIM_CheckType, /*MI*/1, /*Op*/1, /*Type*/GILLT_s32,
        GIM_CheckType, /*MI*/1, /*Op*/2, /*Type*/GILLT_s32,
        GIM_RecordInsn, /*DefineMI*/2, /*MI*/1, /*OpIdx*/2, // MIs[2]
        GIM_CheckOpcode, /*MI*/2, GIMT_Encode2(TargetOpcode::G_CONSTANT),
        // MIs[2] Operand 1
        // No operand predicates
        GIM_CheckCxxInsnPredicate, /*MI*/1, /*FnId*/GIMT_Encode2(GICXXPred_MI_Predicate_csh_mask_64),
        GIM_CheckIsSafeToFold, /*InsnID*/1,
        GIM_CheckIsSafeToFold, /*InsnID*/2,
        GIM_CheckComplexPattern, /*MI*/0, /*Op*/1, /*Renderer*/GIMT_Encode2(0), GIMT_Encode2(GICP_gi_vop3mods0),
        // (shl:{ *:[i64] } (VOP3Mods0:{ *:[i64] } i64:{ *:[i64] }:$src0), (and:{ *:[i32] } i32:{ *:[i32] }:$src1, (imm:{ *:[i32] }))<<P:Predicate_csh_mask_64>>)  =>  (V_LSHL_B64_e64:{ *:[i64] } i64:{ *:[i64] }:$src0, i32:{ *:[i32] }:$src1)
        GIR_BuildMI, /*InsnID*/0, /*Opcode*/GIMT_Encode2(AMDGPU::V_LSHL_B64_e64),
        GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/0, // DstI[vdst]
        GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/0, // src0
        GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/1, /*OpIdx*/1, // src1
        GIR_ConstrainSelectedInstOperands, /*InsnID*/0,
        GIR_EraseFromParent, /*InsnID*/0,
        // GIR_Coverage, 906,
        GIR_Done,
      // Label 3751: @243547
      GIM_Try, /*On fail goto*//*Label 3752*/ GIMT_Encode4(243621), // Rule ID 916 //
        GIM_CheckFeatures, GIMT_Encode2(GIFBS_isGFX8GFX9GFX10GFX11),
        GIM_CheckRegBankForClass, /*MI*/0, /*Op*/0, /*RC*/GIMT_Encode2(AMDGPU::VReg_64RegClassID),
        GIM_RecordInsn, /*DefineMI*/1, /*MI*/0, /*OpIdx*/2, // MIs[1]
        GIM_CheckOpcode, /*MI*/1, GIMT_Encode2(TargetOpcode::G_AND),
        GIM_CheckType, /*MI*/1, /*Op*/1, /*Type*/GILLT_s32,
        GIM_CheckType, /*MI*/1, /*Op*/2, /*Type*/GILLT_s32,
        GIM_RecordInsn, /*DefineMI*/2, /*MI*/1, /*OpIdx*/2, // MIs[2]
        GIM_CheckOpcode, /*MI*/2, GIMT_Encode2(TargetOpcode::G_CONSTANT),
        // MIs[2] Operand 1
        // No operand predicates
        GIM_CheckCxxInsnPredicate, /*MI*/1, /*FnId*/GIMT_Encode2(GICXXPred_MI_Predicate_csh_mask_64),
        GIM_CheckIsSafeToFold, /*InsnID*/1,
        GIM_CheckIsSafeToFold, /*InsnID*/2,
        GIM_CheckComplexPattern, /*MI*/1, /*Op*/1, /*Renderer*/GIMT_Encode2(0), GIMT_Encode2(GICP_gi_vop3mods0),
        // (shl:{ *:[i64] } i64:{ *:[i64] }:$src1, (and:{ *:[i32] } (VOP3Mods0:{ *:[i32] } i32:{ *:[i32] }:$src0), (imm:{ *:[i32] }))<<P:Predicate_csh_mask_64>>)  =>  (V_LSHLREV_B64_e64:{ *:[i64] } i32:{ *:[i32] }:$src0, i64:{ *:[i64] }:$src1)
        GIR_BuildMI, /*InsnID*/0, /*Opcode*/GIMT_Encode2(AMDGPU::V_LSHLREV_B64_e64),
        GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/0, // DstI[vdst]
        GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/0, // src0
        GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/1, // src1
        GIR_ConstrainSelectedInstOperands, /*InsnID*/0,
        GIR_EraseFromParent, /*InsnID*/0,
        // GIR_Coverage, 916,
        GIR_Done,
      // Label 3752: @243621
      GIM_Try, /*On fail goto*//*Label 3753*/ GIMT_Encode4(243663), // Rule ID 905 //
        GIM_CheckFeatures, GIMT_Encode2(GIFBS_isGFX6GFX7),
        GIM_CheckRegBankForClass, /*MI*/0, /*Op*/0, /*RC*/GIMT_Encode2(AMDGPU::VReg_64RegClassID),
        GIM_CheckComplexPattern, /*MI*/0, /*Op*/1, /*Renderer*/GIMT_Encode2(0), GIMT_Encode2(GICP_gi_vop3mods0),
        // (shl:{ *:[i64] } (VOP3Mods0:{ *:[i64] } i64:{ *:[i64] }:$src0), i32:{ *:[i32] }:$src1)  =>  (V_LSHL_B64_e64:{ *:[i64] } i64:{ *:[i64] }:$src0, i32:{ *:[i32] }:$src1)
        GIR_BuildMI, /*InsnID*/0, /*Opcode*/GIMT_Encode2(AMDGPU::V_LSHL_B64_e64),
        GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/0, // DstI[vdst]
        GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/0, // src0
        GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/2, // src1
        GIR_ConstrainSelectedInstOperands, /*InsnID*/0,
        GIR_EraseFromParent, /*InsnID*/0,
        // GIR_Coverage, 905,
        GIR_Done,
      // Label 3753: @243663
      GIM_Try, /*On fail goto*//*Label 3754*/ GIMT_Encode4(243705), // Rule ID 915 //
        GIM_CheckFeatures, GIMT_Encode2(GIFBS_isGFX8GFX9GFX10GFX11),
        GIM_CheckRegBankForClass, /*MI*/0, /*Op*/0, /*RC*/GIMT_Encode2(AMDGPU::VReg_64RegClassID),
        GIM_CheckComplexPattern, /*MI*/0, /*Op*/2, /*Renderer*/GIMT_Encode2(0), GIMT_Encode2(GICP_gi_vop3mods0),
        // (shl:{ *:[i64] } i64:{ *:[i64] }:$src1, (VOP3Mods0:{ *:[i32] } i32:{ *:[i32] }:$src0))  =>  (V_LSHLREV_B64_e64:{ *:[i64] } i32:{ *:[i32] }:$src0, i64:{ *:[i64] }:$src1)
        GIR_BuildMI, /*InsnID*/0, /*Opcode*/GIMT_Encode2(AMDGPU::V_LSHLREV_B64_e64),
        GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/0, // DstI[vdst]
        GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/0, // src0
        GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/1, // src1
        GIR_ConstrainSelectedInstOperands, /*InsnID*/0,
        GIR_EraseFromParent, /*InsnID*/0,
        // GIR_Coverage, 915,
        GIR_Done,
      // Label 3754: @243705
      GIM_Try, /*On fail goto*//*Label 3755*/ GIMT_Encode4(243771), // Rule ID 847 //
        GIM_CheckFeatures, GIMT_Encode2(GIFBS_isGFX12Plus),
        GIM_CheckRegBankForClass, /*MI*/0, /*Op*/0, /*RC*/GIMT_Encode2(AMDGPU::VReg_64RegClassID),
        GIM_RecordInsn, /*DefineMI*/1, /*MI*/0, /*OpIdx*/2, // MIs[1]
        GIM_CheckOpcode, /*MI*/1, GIMT_Encode2(TargetOpcode::G_AND),
        GIM_CheckType, /*MI*/1, /*Op*/1, /*Type*/GILLT_s32,
        GIM_CheckType, /*MI*/1, /*Op*/2, /*Type*/GILLT_s32,
        GIM_RecordInsn, /*DefineMI*/2, /*MI*/1, /*OpIdx*/2, // MIs[2]
        GIM_CheckOpcode, /*MI*/2, GIMT_Encode2(TargetOpcode::G_CONSTANT),
        // MIs[2] Operand 1
        // No operand predicates
        GIM_CheckCxxInsnPredicate, /*MI*/1, /*FnId*/GIMT_Encode2(GICXXPred_MI_Predicate_csh_mask_64),
        GIM_CheckIsSafeToFold, /*InsnID*/1,
        GIM_CheckIsSafeToFold, /*InsnID*/2,
        // (shl:{ *:[i64] } i64:{ *:[i64] }:$src1, (and:{ *:[i32] } i32:{ *:[i32] }:$src0, (imm:{ *:[i32] }))<<P:Predicate_csh_mask_64>>)  =>  (V_LSHLREV_B64_pseudo_e64:{ *:[i64] } i32:{ *:[i32] }:$src0, i64:{ *:[i64] }:$src1)
        GIR_BuildMI, /*InsnID*/0, /*Opcode*/GIMT_Encode2(AMDGPU::V_LSHLREV_B64_pseudo_e64),
        GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/0, // DstI[vdst]
        GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/1, /*OpIdx*/1, // src0
        GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/1, // src1
        GIR_ConstrainSelectedInstOperands, /*InsnID*/0,
        GIR_EraseFromParent, /*InsnID*/0,
        // GIR_Coverage, 847,
        GIR_Done,
      // Label 3755: @243771
      GIM_Try, /*On fail goto*//*Label 3756*/ GIMT_Encode4(243805), // Rule ID 846 //
        GIM_CheckFeatures, GIMT_Encode2(GIFBS_isGFX12Plus),
        GIM_CheckRegBankForClass, /*MI*/0, /*Op*/0, /*RC*/GIMT_Encode2(AMDGPU::VReg_64RegClassID),
        // (shl:{ *:[i64] } i64:{ *:[i64] }:$src1, i32:{ *:[i32] }:$src0)  =>  (V_LSHLREV_B64_pseudo_e64:{ *:[i64] } i32:{ *:[i32] }:$src0, i64:{ *:[i64] }:$src1)
        GIR_BuildMI, /*InsnID*/0, /*Opcode*/GIMT_Encode2(AMDGPU::V_LSHLREV_B64_pseudo_e64),
        GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/0, // DstI[vdst]
        GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/2, // src0
        GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/1, // src1
        GIR_ConstrainSelectedInstOperands, /*InsnID*/0,
        GIR_EraseFromParent, /*InsnID*/0,
        // GIR_Coverage, 846,
        GIR_Done,
      // Label 3756: @243805
      GIM_Reject,
    // Label 3748: @243806
    GIM_Reject,
    // Label 3731: @243807
    GIM_Try, /*On fail goto*//*Label 3757*/ GIMT_Encode4(243992),
      GIM_CheckType, /*MI*/0, /*Op*/1, /*Type*/GILLT_v2s16,
      GIM_CheckType, /*MI*/0, /*Op*/2, /*Type*/GILLT_v2s16,
      GIM_CheckRegBankForClass, /*MI*/0, /*Op*/0, /*RC*/GIMT_Encode2(AMDGPU::VGPR_32RegClassID),
      GIM_Try, /*On fail goto*//*Label 3758*/ GIMT_Encode4(243924), // Rule ID 978 //
        GIM_RecordInsn, /*DefineMI*/1, /*MI*/0, /*OpIdx*/2, // MIs[1]
        GIM_CheckOpcode, /*MI*/1, GIMT_Encode2(TargetOpcode::G_AND),
        GIM_CheckType, /*MI*/1, /*Op*/1, /*Type*/GILLT_v2s16,
        GIM_CheckType, /*MI*/1, /*Op*/2, /*Type*/GILLT_v2s16,
        GIM_RecordInsn, /*DefineMI*/2, /*MI*/1, /*OpIdx*/2, // MIs[2]
        GIM_CheckOpcode, /*MI*/2, GIMT_Encode2(TargetOpcode::G_CONSTANT),
        // MIs[2] Operand 1
        // No operand predicates
        GIM_CheckCxxInsnPredicate, /*MI*/1, /*FnId*/GIMT_Encode2(GICXXPred_MI_Predicate_csh_mask_16),
        GIM_CheckIsSafeToFold, /*InsnID*/1,
        GIM_CheckIsSafeToFold, /*InsnID*/2,
        GIM_CheckComplexPattern, /*MI*/0, /*Op*/1, /*Renderer*/GIMT_Encode2(0), GIMT_Encode2(GICP_gi_vop3pmods),
        GIM_CheckComplexPattern, /*MI*/1, /*Op*/1, /*Renderer*/GIMT_Encode2(1), GIMT_Encode2(GICP_gi_vop3pmods),
        // (shl:{ *:[v2i16] } (VOP3PMods:{ *:[v2i16] } v2i16:{ *:[v2i16] }:$src1, i32:{ *:[i32] }:$src1_modifiers), (and:{ *:[v2i16] } (VOP3PMods:{ *:[v2i16] } v2i16:{ *:[v2i16] }:$src0, i32:{ *:[i32] }:$src0_modifiers), (imm:{ *:[v2i16] }))<<P:Predicate_csh_mask_16>>)  =>  (V_PK_LSHLREV_B16:{ *:[v2i16] } i32:{ *:[i32] }:$src0_modifiers, v2i16:{ *:[v2i16] }:$src0, i32:{ *:[i32] }:$src1_modifiers, v2i16:{ *:[v2i16] }:$src1)
        GIR_BuildMI, /*InsnID*/0, /*Opcode*/GIMT_Encode2(AMDGPU::V_PK_LSHLREV_B16),
        GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/0, // DstI[vdst]
        GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(1), /*SubOperand*/1, // src0_modifiers
        GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(1), /*SubOperand*/0, // src0
        GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/1, // src1_modifiers
        GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/0, // src1
        GIR_AddImm8, /*InsnID*/0, /*Imm*/0,
        GIR_AddImm8, /*InsnID*/0, /*Imm*/0,
        GIR_AddImm8, /*InsnID*/0, /*Imm*/0,
        GIR_AddImm8, /*InsnID*/0, /*Imm*/0,
        GIR_AddImm8, /*InsnID*/0, /*Imm*/0,
        GIR_ConstrainSelectedInstOperands, /*InsnID*/0,
        GIR_EraseFromParent, /*InsnID*/0,
        // GIR_Coverage, 978,
        GIR_Done,
      // Label 3758: @243924
      GIM_Try, /*On fail goto*//*Label 3759*/ GIMT_Encode4(243991), // Rule ID 977 //
        GIM_CheckComplexPattern, /*MI*/0, /*Op*/1, /*Renderer*/GIMT_Encode2(0), GIMT_Encode2(GICP_gi_vop3pmods),
        GIM_CheckComplexPattern, /*MI*/0, /*Op*/2, /*Renderer*/GIMT_Encode2(1), GIMT_Encode2(GICP_gi_vop3pmods),
        // (shl:{ *:[v2i16] } (VOP3PMods:{ *:[v2i16] } v2i16:{ *:[v2i16] }:$src1, i32:{ *:[i32] }:$src1_modifiers), (VOP3PMods:{ *:[v2i16] } v2i16:{ *:[v2i16] }:$src0, i32:{ *:[i32] }:$src0_modifiers))  =>  (V_PK_LSHLREV_B16:{ *:[v2i16] } i32:{ *:[i32] }:$src0_modifiers, v2i16:{ *:[v2i16] }:$src0, i32:{ *:[i32] }:$src1_modifiers, v2i16:{ *:[v2i16] }:$src1)
        GIR_BuildMI, /*InsnID*/0, /*Opcode*/GIMT_Encode2(AMDGPU::V_PK_LSHLREV_B16),
        GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/0, // DstI[vdst]
        GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(1), /*SubOperand*/1, // src0_modifiers
        GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(1), /*SubOperand*/0, // src0
        GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/1, // src1_modifiers
        GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/0, // src1
        GIR_AddImm8, /*InsnID*/0, /*Imm*/0,
        GIR_AddImm8, /*InsnID*/0, /*Imm*/0,
        GIR_AddImm8, /*InsnID*/0, /*Imm*/0,
        GIR_AddImm8, /*InsnID*/0, /*Imm*/0,
        GIR_AddImm8, /*InsnID*/0, /*Imm*/0,
        GIR_ConstrainSelectedInstOperands, /*InsnID*/0,
        GIR_EraseFromParent, /*InsnID*/0,
        // GIR_Coverage, 977,
        GIR_Done,
      // Label 3759: @243991
      GIM_Reject,
    // Label 3757: @243992
    GIM_Reject,
    // Label 3732: @243993
    GIM_Reject,
    // Label 43: @243994
    GIM_SwitchType, /*MI*/0, /*Op*/0, /*[*/GIMT_Encode2(8), GIMT_Encode2(12), /*)*//*default:*//*Label 3764*/ GIMT_Encode4(245125),
    /*GILLT_s16*//*Label 3760*/ GIMT_Encode4(244021),
    /*GILLT_s32*//*Label 3761*/ GIMT_Encode4(244221),
    /*GILLT_s64*//*Label 3762*/ GIMT_Encode4(244574),
    /*GILLT_v2s16*//*Label 3763*/ GIMT_Encode4(244939),
    // Label 3760: @244021
    GIM_Try, /*On fail goto*//*Label 3765*/ GIMT_Encode4(244220),
      GIM_CheckType, /*MI*/0, /*Op*/1, /*Type*/GILLT_s16,
      GIM_CheckType, /*MI*/0, /*Op*/2, /*Type*/GILLT_s16,
      GIM_CheckRegBankForClass, /*MI*/0, /*Op*/0, /*RC*/GIMT_Encode2(AMDGPU::VGPR_32RegClassID),
      GIM_Try, /*On fail goto*//*Label 3766*/ GIMT_Encode4(244100), // Rule ID 786 //
        GIM_CheckFeatures, GIMT_Encode2(GIFBS_Has16BitInsts_NotHasTrue16BitInsts),
        GIM_RecordInsn, /*DefineMI*/1, /*MI*/0, /*OpIdx*/2, // MIs[1]
        GIM_CheckOpcode, /*MI*/1, GIMT_Encode2(TargetOpcode::G_AND),
        GIM_CheckType, /*MI*/1, /*Op*/1, /*Type*/GILLT_s16,
        GIM_CheckType, /*MI*/1, /*Op*/2, /*Type*/GILLT_s16,
        GIM_RecordInsn, /*DefineMI*/2, /*MI*/1, /*OpIdx*/2, // MIs[2]
        GIM_CheckOpcode, /*MI*/2, GIMT_Encode2(TargetOpcode::G_CONSTANT),
        // MIs[2] Operand 1
        // No operand predicates
        GIM_CheckCxxInsnPredicate, /*MI*/1, /*FnId*/GIMT_Encode2(GICXXPred_MI_Predicate_csh_mask_16),
        GIM_CheckIsSafeToFold, /*InsnID*/1,
        GIM_CheckIsSafeToFold, /*InsnID*/2,
        // (srl:{ *:[i16] } i16:{ *:[i16] }:$src1, (and:{ *:[i16] } i16:{ *:[i16] }:$src0, (imm:{ *:[i16] }))<<P:Predicate_csh_mask_16>>)  =>  (V_LSHRREV_B16_e64:{ *:[i16] } i16:{ *:[i16] }:$src0, i16:{ *:[i16] }:$src1)
        GIR_BuildMI, /*InsnID*/0, /*Opcode*/GIMT_Encode2(AMDGPU::V_LSHRREV_B16_e64),
        GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/0, // DstI[vdst]
        GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/1, /*OpIdx*/1, // src0
        GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/1, // src1
        GIR_ConstrainSelectedInstOperands, /*InsnID*/0,
        GIR_EraseFromParent, /*InsnID*/0,
        // GIR_Coverage, 786,
        GIR_Done,
      // Label 3766: @244100
      GIM_Try, /*On fail goto*//*Label 3767*/ GIMT_Encode4(244161), // Rule ID 788 //
        GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasTrue16BitInsts),
        GIM_RecordInsn, /*DefineMI*/1, /*MI*/0, /*OpIdx*/2, // MIs[1]
        GIM_CheckOpcode, /*MI*/1, GIMT_Encode2(TargetOpcode::G_AND),
        GIM_CheckType, /*MI*/1, /*Op*/1, /*Type*/GILLT_s16,
        GIM_CheckType, /*MI*/1, /*Op*/2, /*Type*/GILLT_s16,
        GIM_RecordInsn, /*DefineMI*/2, /*MI*/1, /*OpIdx*/2, // MIs[2]
        GIM_CheckOpcode, /*MI*/2, GIMT_Encode2(TargetOpcode::G_CONSTANT),
        // MIs[2] Operand 1
        // No operand predicates
        GIM_CheckCxxInsnPredicate, /*MI*/1, /*FnId*/GIMT_Encode2(GICXXPred_MI_Predicate_csh_mask_16),
        GIM_CheckIsSafeToFold, /*InsnID*/1,
        GIM_CheckIsSafeToFold, /*InsnID*/2,
        // (srl:{ *:[i16] } i16:{ *:[i16] }:$src1, (and:{ *:[i16] } i16:{ *:[i16] }:$src0, (imm:{ *:[i16] }))<<P:Predicate_csh_mask_16>>)  =>  (V_LSHRREV_B16_t16_e64:{ *:[i16] } i16:{ *:[i16] }:$src0, i16:{ *:[i16] }:$src1)
        GIR_BuildMI, /*InsnID*/0, /*Opcode*/GIMT_Encode2(AMDGPU::V_LSHRREV_B16_t16_e64),
        GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/0, // DstI[vdst]
        GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/1, /*OpIdx*/1, // src0
        GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/1, // src1
        GIR_ConstrainSelectedInstOperands, /*InsnID*/0,
        GIR_EraseFromParent, /*InsnID*/0,
        // GIR_Coverage, 788,
        GIR_Done,
      // Label 3767: @244161
      GIM_Try, /*On fail goto*//*Label 3768*/ GIMT_Encode4(244190), // Rule ID 785 //
        GIM_CheckFeatures, GIMT_Encode2(GIFBS_Has16BitInsts_NotHasTrue16BitInsts),
        // (srl:{ *:[i16] } i16:{ *:[i16] }:$src1, i16:{ *:[i16] }:$src0)  =>  (V_LSHRREV_B16_e64:{ *:[i16] } i16:{ *:[i16] }:$src0, i16:{ *:[i16] }:$src1)
        GIR_BuildMI, /*InsnID*/0, /*Opcode*/GIMT_Encode2(AMDGPU::V_LSHRREV_B16_e64),
        GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/0, // DstI[vdst]
        GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/2, // src0
        GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/1, // src1
        GIR_ConstrainSelectedInstOperands, /*InsnID*/0,
        GIR_EraseFromParent, /*InsnID*/0,
        // GIR_Coverage, 785,
        GIR_Done,
      // Label 3768: @244190
      GIM_Try, /*On fail goto*//*Label 3769*/ GIMT_Encode4(244219), // Rule ID 787 //
        GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasTrue16BitInsts),
        // (srl:{ *:[i16] } i16:{ *:[i16] }:$src1, i16:{ *:[i16] }:$src0)  =>  (V_LSHRREV_B16_t16_e64:{ *:[i16] } i16:{ *:[i16] }:$src0, i16:{ *:[i16] }:$src1)
        GIR_BuildMI, /*InsnID*/0, /*Opcode*/GIMT_Encode2(AMDGPU::V_LSHRREV_B16_t16_e64),
        GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/0, // DstI[vdst]
        GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/2, // src0
        GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/1, // src1
        GIR_ConstrainSelectedInstOperands, /*InsnID*/0,
        GIR_EraseFromParent, /*InsnID*/0,
        // GIR_Coverage, 787,
        GIR_Done,
      // Label 3769: @244219
      GIM_Reject,
    // Label 3765: @244220
    GIM_Reject,
    // Label 3761: @244221
    GIM_Try, /*On fail goto*//*Label 3770*/ GIMT_Encode4(244573),
      GIM_CheckType, /*MI*/0, /*Op*/1, /*Type*/GILLT_s32,
      GIM_CheckType, /*MI*/0, /*Op*/2, /*Type*/GILLT_s32,
      GIM_Try, /*On fail goto*//*Label 3771*/ GIMT_Encode4(244314), // Rule ID 75 //
        GIM_CheckRegBankForClass, /*MI*/0, /*Op*/0, /*RC*/GIMT_Encode2(AMDGPU::SReg_32RegClassID),
        GIM_CheckRegBankForClass, /*MI*/0, /*Op*/1, /*RC*/GIMT_Encode2(AMDGPU::SReg_32RegClassID),
        GIM_RecordInsn, /*DefineMI*/1, /*MI*/0, /*OpIdx*/2, // MIs[1]
        GIM_CheckOpcode, /*MI*/1, GIMT_Encode2(TargetOpcode::G_AND),
        GIM_CheckType, /*MI*/1, /*Op*/1, /*Type*/GILLT_s32,
        GIM_CheckType, /*MI*/1, /*Op*/2, /*Type*/GILLT_s32,
        GIM_CheckRegBankForClass, /*MI*/1, /*Op*/1, /*RC*/GIMT_Encode2(AMDGPU::SReg_32RegClassID),
        GIM_RecordInsn, /*DefineMI*/2, /*MI*/1, /*OpIdx*/2, // MIs[2]
        GIM_CheckOpcode, /*MI*/2, GIMT_Encode2(TargetOpcode::G_CONSTANT),
        // MIs[2] Operand 1
        // No operand predicates
        GIM_CheckCxxInsnPredicate, /*MI*/1, /*FnId*/GIMT_Encode2(GICXXPred_MI_Predicate_csh_mask_32),
        GIM_CheckCxxInsnPredicate, /*MI*/0, /*FnId*/GIMT_Encode2(GICXXPred_MI_Predicate_anonymous_17620),
        GIM_CheckIsSafeToFold, /*InsnID*/1,
        GIM_CheckIsSafeToFold, /*InsnID*/2,
        // (srl:{ *:[i32] } SSrc_b32:{ *:[i32] }:$src0, (and:{ *:[i32] } SSrc_b32:{ *:[i32] }:$src1, (imm:{ *:[i32] }))<<P:Predicate_csh_mask_32>>)<<P:Predicate_anonymous_17620>>  =>  (S_LSHR_B32:{ *:[i32] }:{ *:[i1] } SSrc_b32:{ *:[i32] }:$src0, SSrc_b32:{ *:[i32] }:$src1)
        GIR_BuildMI, /*InsnID*/0, /*Opcode*/GIMT_Encode2(AMDGPU::S_LSHR_B32),
        GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/0, // DstI[sdst]
        GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/1, // src0
        GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/1, /*OpIdx*/1, // src1
        GIR_SetImplicitDefDead, /*InsnID*/0, /*OpIdx for AMDGPU::SCC*/0,
        GIR_ConstrainSelectedInstOperands, /*InsnID*/0,
        GIR_EraseFromParent, /*InsnID*/0,
        // GIR_Coverage, 75,
        GIR_Done,
      // Label 3771: @244314
      GIM_Try, /*On fail goto*//*Label 3772*/ GIMT_Encode4(244352), // Rule ID 74 //
        GIM_CheckRegBankForClass, /*MI*/0, /*Op*/0, /*RC*/GIMT_Encode2(AMDGPU::SReg_32RegClassID),
        GIM_CheckRegBankForClass, /*MI*/0, /*Op*/1, /*RC*/GIMT_Encode2(AMDGPU::SReg_32RegClassID),
        GIM_CheckRegBankForClass, /*MI*/0, /*Op*/2, /*RC*/GIMT_Encode2(AMDGPU::SReg_32RegClassID),
        GIM_CheckCxxInsnPredicate, /*MI*/0, /*FnId*/GIMT_Encode2(GICXXPred_MI_Predicate_anonymous_17620),
        // (srl:{ *:[i32] } SSrc_b32:{ *:[i32] }:$src0, SSrc_b32:{ *:[i32] }:$src1)<<P:Predicate_anonymous_17620>>  =>  (S_LSHR_B32:{ *:[i32] }:{ *:[i1] } SSrc_b32:{ *:[i32] }:$src0, SSrc_b32:{ *:[i32] }:$src1)
        GIR_MutateOpcode, /*InsnID*/0, /*RecycleInsnID*/0, /*Opcode*/GIMT_Encode2(AMDGPU::S_LSHR_B32),
        GIR_AddImplicitDef, /*InsnID*/0, GIMT_Encode2(AMDGPU::SCC), GIMT_Encode2(RegState::Dead),
        GIR_ConstrainSelectedInstOperands, /*InsnID*/0,
        // GIR_Coverage, 74,
        GIR_Done,
      // Label 3772: @244352
      GIM_Try, /*On fail goto*//*Label 3773*/ GIMT_Encode4(244387), // Rule ID 2092 //
        GIM_CheckRegBankForClass, /*MI*/0, /*Op*/0, /*RC*/GIMT_Encode2(AMDGPU::VGPR_32RegClassID),
        GIM_CheckCxxInsnPredicate, /*MI*/0, /*FnId*/GIMT_Encode2(GICXXPred_MI_Predicate_anonymous_22539),
        // (srl:{ *:[i32] } i32:{ *:[i32] }:$src0, i32:{ *:[i32] }:$src1)<<P:Predicate_anonymous_22539>>  =>  (V_LSHRREV_B32_e64:{ *:[i32] } ?:{ *:[i32] }:$src1, ?:{ *:[i32] }:$src0)
        GIR_BuildMI, /*InsnID*/0, /*Opcode*/GIMT_Encode2(AMDGPU::V_LSHRREV_B32_e64),
        GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/0, // DstI[vdst]
        GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/2, // src1
        GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/1, // src0
        GIR_ConstrainSelectedInstOperands, /*InsnID*/0,
        GIR_EraseFromParent, /*InsnID*/0,
        // GIR_Coverage, 2092,
        GIR_Done,
      // Label 3773: @244387
      GIM_Try, /*On fail goto*//*Label 3774*/ GIMT_Encode4(244450), // Rule ID 748 //
        GIM_CheckRegBankForClass, /*MI*/0, /*Op*/0, /*RC*/GIMT_Encode2(AMDGPU::VGPR_32RegClassID),
        GIM_RecordInsn, /*DefineMI*/1, /*MI*/0, /*OpIdx*/2, // MIs[1]
        GIM_CheckOpcode, /*MI*/1, GIMT_Encode2(TargetOpcode::G_AND),
        GIM_CheckType, /*MI*/1, /*Op*/1, /*Type*/GILLT_s32,
        GIM_CheckType, /*MI*/1, /*Op*/2, /*Type*/GILLT_s32,
        GIM_RecordInsn, /*DefineMI*/2, /*MI*/1, /*OpIdx*/2, // MIs[2]
        GIM_CheckOpcode, /*MI*/2, GIMT_Encode2(TargetOpcode::G_CONSTANT),
        // MIs[2] Operand 1
        // No operand predicates
        GIM_CheckCxxInsnPredicate, /*MI*/1, /*FnId*/GIMT_Encode2(GICXXPred_MI_Predicate_csh_mask_32),
        GIM_CheckIsSafeToFold, /*InsnID*/1,
        GIM_CheckIsSafeToFold, /*InsnID*/2,
        // (srl:{ *:[i32] } i32:{ *:[i32] }:$src1, (and:{ *:[i32] } i32:{ *:[i32] }:$src0, (imm:{ *:[i32] }))<<P:Predicate_csh_mask_32>>)  =>  (V_LSHRREV_B32_e64:{ *:[i32] } i32:{ *:[i32] }:$src0, i32:{ *:[i32] }:$src1)
        GIR_BuildMI, /*InsnID*/0, /*Opcode*/GIMT_Encode2(AMDGPU::V_LSHRREV_B32_e64),
        GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/0, // DstI[vdst]
        GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/1, /*OpIdx*/1, // src0
        GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/1, // src1
        GIR_ConstrainSelectedInstOperands, /*InsnID*/0,
        GIR_EraseFromParent, /*InsnID*/0,
        // GIR_Coverage, 748,
        GIR_Done,
      // Label 3774: @244450
      GIM_Try, /*On fail goto*//*Label 3775*/ GIMT_Encode4(244516), // Rule ID 776 //
        GIM_CheckFeatures, GIMT_Encode2(GIFBS_isGFX6GFX7),
        GIM_CheckRegBankForClass, /*MI*/0, /*Op*/0, /*RC*/GIMT_Encode2(AMDGPU::VGPR_32RegClassID),
        GIM_RecordInsn, /*DefineMI*/1, /*MI*/0, /*OpIdx*/2, // MIs[1]
        GIM_CheckOpcode, /*MI*/1, GIMT_Encode2(TargetOpcode::G_AND),
        GIM_CheckType, /*MI*/1, /*Op*/1, /*Type*/GILLT_s32,
        GIM_CheckType, /*MI*/1, /*Op*/2, /*Type*/GILLT_s32,
        GIM_RecordInsn, /*DefineMI*/2, /*MI*/1, /*OpIdx*/2, // MIs[2]
        GIM_CheckOpcode, /*MI*/2, GIMT_Encode2(TargetOpcode::G_CONSTANT),
        // MIs[2] Operand 1
        // No operand predicates
        GIM_CheckCxxInsnPredicate, /*MI*/1, /*FnId*/GIMT_Encode2(GICXXPred_MI_Predicate_csh_mask_32),
        GIM_CheckIsSafeToFold, /*InsnID*/1,
        GIM_CheckIsSafeToFold, /*InsnID*/2,
        // (srl:{ *:[i32] } i32:{ *:[i32] }:$src0, (and:{ *:[i32] } i32:{ *:[i32] }:$src1, (imm:{ *:[i32] }))<<P:Predicate_csh_mask_32>>)  =>  (V_LSHR_B32_e64:{ *:[i32] } i32:{ *:[i32] }:$src0, i32:{ *:[i32] }:$src1)
        GIR_BuildMI, /*InsnID*/0, /*Opcode*/GIMT_Encode2(AMDGPU::V_LSHR_B32_e64),
        GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/0, // DstI[vdst]
        GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/1, // src0
        GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/1, /*OpIdx*/1, // src1
        GIR_ConstrainSelectedInstOperands, /*InsnID*/0,
        GIR_EraseFromParent, /*InsnID*/0,
        // GIR_Coverage, 776,
        GIR_Done,
      // Label 3775: @244516
      GIM_Try, /*On fail goto*//*Label 3776*/ GIMT_Encode4(244547), // Rule ID 747 //
        GIM_CheckRegBankForClass, /*MI*/0, /*Op*/0, /*RC*/GIMT_Encode2(AMDGPU::VGPR_32RegClassID),
        // (srl:{ *:[i32] } i32:{ *:[i32] }:$src1, i32:{ *:[i32] }:$src0)  =>  (V_LSHRREV_B32_e64:{ *:[i32] } i32:{ *:[i32] }:$src0, i32:{ *:[i32] }:$src1)
        GIR_BuildMI, /*InsnID*/0, /*Opcode*/GIMT_Encode2(AMDGPU::V_LSHRREV_B32_e64),
        GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/0, // DstI[vdst]
        GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/2, // src0
        GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/1, // src1
        GIR_ConstrainSelectedInstOperands, /*InsnID*/0,
        GIR_EraseFromParent, /*InsnID*/0,
        // GIR_Coverage, 747,
        GIR_Done,
      // Label 3776: @244547
      GIM_Try, /*On fail goto*//*Label 3777*/ GIMT_Encode4(244572), // Rule ID 775 //
        GIM_CheckFeatures, GIMT_Encode2(GIFBS_isGFX6GFX7),
        GIM_CheckRegBankForClass, /*MI*/0, /*Op*/0, /*RC*/GIMT_Encode2(AMDGPU::VGPR_32RegClassID),
        // (srl:{ *:[i32] } i32:{ *:[i32] }:$src0, i32:{ *:[i32] }:$src1)  =>  (V_LSHR_B32_e64:{ *:[i32] } i32:{ *:[i32] }:$src0, i32:{ *:[i32] }:$src1)
        GIR_MutateOpcode, /*InsnID*/0, /*RecycleInsnID*/0, /*Opcode*/GIMT_Encode2(AMDGPU::V_LSHR_B32_e64),
        GIR_AddImplicitUse, /*InsnID*/0, GIMT_Encode2(AMDGPU::EXEC),
        GIR_ConstrainSelectedInstOperands, /*InsnID*/0,
        // GIR_Coverage, 775,
        GIR_Done,
      // Label 3777: @244572
      GIM_Reject,
    // Label 3770: @244573
    GIM_Reject,
    // Label 3762: @244574
    GIM_Try, /*On fail goto*//*Label 3778*/ GIMT_Encode4(244938),
      GIM_CheckType, /*MI*/0, /*Op*/1, /*Type*/GILLT_s64,
      GIM_CheckType, /*MI*/0, /*Op*/2, /*Type*/GILLT_s32,
      GIM_Try, /*On fail goto*//*Label 3779*/ GIMT_Encode4(244667), // Rule ID 77 //
        GIM_CheckRegBankForClass, /*MI*/0, /*Op*/0, /*RC*/GIMT_Encode2(AMDGPU::SReg_64RegClassID),
        GIM_CheckRegBankForClass, /*MI*/0, /*Op*/1, /*RC*/GIMT_Encode2(AMDGPU::SReg_64RegClassID),
        GIM_RecordInsn, /*DefineMI*/1, /*MI*/0, /*OpIdx*/2, // MIs[1]
        GIM_CheckOpcode, /*MI*/1, GIMT_Encode2(TargetOpcode::G_AND),
        GIM_CheckType, /*MI*/1, /*Op*/1, /*Type*/GILLT_s32,
        GIM_CheckType, /*MI*/1, /*Op*/2, /*Type*/GILLT_s32,
        GIM_CheckRegBankForClass, /*MI*/1, /*Op*/1, /*RC*/GIMT_Encode2(AMDGPU::SReg_32RegClassID),
        GIM_RecordInsn, /*DefineMI*/2, /*MI*/1, /*OpIdx*/2, // MIs[2]
        GIM_CheckOpcode, /*MI*/2, GIMT_Encode2(TargetOpcode::G_CONSTANT),
        // MIs[2] Operand 1
        // No operand predicates
        GIM_CheckCxxInsnPredicate, /*MI*/1, /*FnId*/GIMT_Encode2(GICXXPred_MI_Predicate_csh_mask_64),
        GIM_CheckCxxInsnPredicate, /*MI*/0, /*FnId*/GIMT_Encode2(GICXXPred_MI_Predicate_anonymous_17621),
        GIM_CheckIsSafeToFold, /*InsnID*/1,
        GIM_CheckIsSafeToFold, /*InsnID*/2,
        // (srl:{ *:[i64] } SSrc_b64:{ *:[i64] }:$src0, (and:{ *:[i32] } SSrc_b32:{ *:[i32] }:$src1, (imm:{ *:[i32] }))<<P:Predicate_csh_mask_64>>)<<P:Predicate_anonymous_17621>>  =>  (S_LSHR_B64:{ *:[i64] }:{ *:[i1] } SSrc_b64:{ *:[i64] }:$src0, SSrc_b32:{ *:[i32] }:$src1)
        GIR_BuildMI, /*InsnID*/0, /*Opcode*/GIMT_Encode2(AMDGPU::S_LSHR_B64),
        GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/0, // DstI[sdst]
        GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/1, // src0
        GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/1, /*OpIdx*/1, // src1
        GIR_SetImplicitDefDead, /*InsnID*/0, /*OpIdx for AMDGPU::SCC*/0,
        GIR_ConstrainSelectedInstOperands, /*InsnID*/0,
        GIR_EraseFromParent, /*InsnID*/0,
        // GIR_Coverage, 77,
        GIR_Done,
      // Label 3779: @244667
      GIM_Try, /*On fail goto*//*Label 3780*/ GIMT_Encode4(244705), // Rule ID 76 //
        GIM_CheckRegBankForClass, /*MI*/0, /*Op*/0, /*RC*/GIMT_Encode2(AMDGPU::SReg_64RegClassID),
        GIM_CheckRegBankForClass, /*MI*/0, /*Op*/1, /*RC*/GIMT_Encode2(AMDGPU::SReg_64RegClassID),
        GIM_CheckRegBankForClass, /*MI*/0, /*Op*/2, /*RC*/GIMT_Encode2(AMDGPU::SReg_32RegClassID),
        GIM_CheckCxxInsnPredicate, /*MI*/0, /*FnId*/GIMT_Encode2(GICXXPred_MI_Predicate_anonymous_17621),
        // (srl:{ *:[i64] } SSrc_b64:{ *:[i64] }:$src0, SSrc_b32:{ *:[i32] }:$src1)<<P:Predicate_anonymous_17621>>  =>  (S_LSHR_B64:{ *:[i64] }:{ *:[i1] } SSrc_b64:{ *:[i64] }:$src0, SSrc_b32:{ *:[i32] }:$src1)
        GIR_MutateOpcode, /*InsnID*/0, /*RecycleInsnID*/0, /*Opcode*/GIMT_Encode2(AMDGPU::S_LSHR_B64),
        GIR_AddImplicitDef, /*InsnID*/0, GIMT_Encode2(AMDGPU::SCC), GIMT_Encode2(RegState::Dead),
        GIR_ConstrainSelectedInstOperands, /*InsnID*/0,
        // GIR_Coverage, 76,
        GIR_Done,
      // Label 3780: @244705
      GIM_Try, /*On fail goto*//*Label 3781*/ GIMT_Encode4(244779), // Rule ID 908 //
        GIM_CheckFeatures, GIMT_Encode2(GIFBS_isGFX6GFX7),
        GIM_CheckRegBankForClass, /*MI*/0, /*Op*/0, /*RC*/GIMT_Encode2(AMDGPU::VReg_64RegClassID),
        GIM_RecordInsn, /*DefineMI*/1, /*MI*/0, /*OpIdx*/2, // MIs[1]
        GIM_CheckOpcode, /*MI*/1, GIMT_Encode2(TargetOpcode::G_AND),
        GIM_CheckType, /*MI*/1, /*Op*/1, /*Type*/GILLT_s32,
        GIM_CheckType, /*MI*/1, /*Op*/2, /*Type*/GILLT_s32,
        GIM_RecordInsn, /*DefineMI*/2, /*MI*/1, /*OpIdx*/2, // MIs[2]
        GIM_CheckOpcode, /*MI*/2, GIMT_Encode2(TargetOpcode::G_CONSTANT),
        // MIs[2] Operand 1
        // No operand predicates
        GIM_CheckCxxInsnPredicate, /*MI*/1, /*FnId*/GIMT_Encode2(GICXXPred_MI_Predicate_csh_mask_64),
        GIM_CheckIsSafeToFold, /*InsnID*/1,
        GIM_CheckIsSafeToFold, /*InsnID*/2,
        GIM_CheckComplexPattern, /*MI*/0, /*Op*/1, /*Renderer*/GIMT_Encode2(0), GIMT_Encode2(GICP_gi_vop3mods0),
        // (srl:{ *:[i64] } (VOP3Mods0:{ *:[i64] } i64:{ *:[i64] }:$src0), (and:{ *:[i32] } i32:{ *:[i32] }:$src1, (imm:{ *:[i32] }))<<P:Predicate_csh_mask_64>>)  =>  (V_LSHR_B64_e64:{ *:[i64] } i64:{ *:[i64] }:$src0, i32:{ *:[i32] }:$src1)
        GIR_BuildMI, /*InsnID*/0, /*Opcode*/GIMT_Encode2(AMDGPU::V_LSHR_B64_e64),
        GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/0, // DstI[vdst]
        GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/0, // src0
        GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/1, /*OpIdx*/1, // src1
        GIR_ConstrainSelectedInstOperands, /*InsnID*/0,
        GIR_EraseFromParent, /*InsnID*/0,
        // GIR_Coverage, 908,
        GIR_Done,
      // Label 3781: @244779
      GIM_Try, /*On fail goto*//*Label 3782*/ GIMT_Encode4(244853), // Rule ID 912 //
        GIM_CheckFeatures, GIMT_Encode2(GIFBS_isGFX8Plus),
        GIM_CheckRegBankForClass, /*MI*/0, /*Op*/0, /*RC*/GIMT_Encode2(AMDGPU::VReg_64RegClassID),
        GIM_RecordInsn, /*DefineMI*/1, /*MI*/0, /*OpIdx*/2, // MIs[1]
        GIM_CheckOpcode, /*MI*/1, GIMT_Encode2(TargetOpcode::G_AND),
        GIM_CheckType, /*MI*/1, /*Op*/1, /*Type*/GILLT_s32,
        GIM_CheckType, /*MI*/1, /*Op*/2, /*Type*/GILLT_s32,
        GIM_RecordInsn, /*DefineMI*/2, /*MI*/1, /*OpIdx*/2, // MIs[2]
        GIM_CheckOpcode, /*MI*/2, GIMT_Encode2(TargetOpcode::G_CONSTANT),
        // MIs[2] Operand 1
        // No operand predicates
        GIM_CheckCxxInsnPredicate, /*MI*/1, /*FnId*/GIMT_Encode2(GICXXPred_MI_Predicate_csh_mask_64),
        GIM_CheckIsSafeToFold, /*InsnID*/1,
        GIM_CheckIsSafeToFold, /*InsnID*/2,
        GIM_CheckComplexPattern, /*MI*/1, /*Op*/1, /*Renderer*/GIMT_Encode2(0), GIMT_Encode2(GICP_gi_vop3mods0),
        // (srl:{ *:[i64] } i64:{ *:[i64] }:$src1, (and:{ *:[i32] } (VOP3Mods0:{ *:[i32] } i32:{ *:[i32] }:$src0), (imm:{ *:[i32] }))<<P:Predicate_csh_mask_64>>)  =>  (V_LSHRREV_B64_e64:{ *:[i64] } i32:{ *:[i32] }:$src0, i64:{ *:[i64] }:$src1)
        GIR_BuildMI, /*InsnID*/0, /*Opcode*/GIMT_Encode2(AMDGPU::V_LSHRREV_B64_e64),
        GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/0, // DstI[vdst]
        GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/0, // src0
        GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/1, // src1
        GIR_ConstrainSelectedInstOperands, /*InsnID*/0,
        GIR_EraseFromParent, /*InsnID*/0,
        // GIR_Coverage, 912,
        GIR_Done,
      // Label 3782: @244853
      GIM_Try, /*On fail goto*//*Label 3783*/ GIMT_Encode4(244895), // Rule ID 907 //
        GIM_CheckFeatures, GIMT_Encode2(GIFBS_isGFX6GFX7),
        GIM_CheckRegBankForClass, /*MI*/0, /*Op*/0, /*RC*/GIMT_Encode2(AMDGPU::VReg_64RegClassID),
        GIM_CheckComplexPattern, /*MI*/0, /*Op*/1, /*Renderer*/GIMT_Encode2(0), GIMT_Encode2(GICP_gi_vop3mods0),
        // (srl:{ *:[i64] } (VOP3Mods0:{ *:[i64] } i64:{ *:[i64] }:$src0), i32:{ *:[i32] }:$src1)  =>  (V_LSHR_B64_e64:{ *:[i64] } i64:{ *:[i64] }:$src0, i32:{ *:[i32] }:$src1)
        GIR_BuildMI, /*InsnID*/0, /*Opcode*/GIMT_Encode2(AMDGPU::V_LSHR_B64_e64),
        GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/0, // DstI[vdst]
        GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/0, // src0
        GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/2, // src1
        GIR_ConstrainSelectedInstOperands, /*InsnID*/0,
        GIR_EraseFromParent, /*InsnID*/0,
        // GIR_Coverage, 907,
        GIR_Done,
      // Label 3783: @244895
      GIM_Try, /*On fail goto*//*Label 3784*/ GIMT_Encode4(244937), // Rule ID 911 //
        GIM_CheckFeatures, GIMT_Encode2(GIFBS_isGFX8Plus),
        GIM_CheckRegBankForClass, /*MI*/0, /*Op*/0, /*RC*/GIMT_Encode2(AMDGPU::VReg_64RegClassID),
        GIM_CheckComplexPattern, /*MI*/0, /*Op*/2, /*Renderer*/GIMT_Encode2(0), GIMT_Encode2(GICP_gi_vop3mods0),
        // (srl:{ *:[i64] } i64:{ *:[i64] }:$src1, (VOP3Mods0:{ *:[i32] } i32:{ *:[i32] }:$src0))  =>  (V_LSHRREV_B64_e64:{ *:[i64] } i32:{ *:[i32] }:$src0, i64:{ *:[i64] }:$src1)
        GIR_BuildMI, /*InsnID*/0, /*Opcode*/GIMT_Encode2(AMDGPU::V_LSHRREV_B64_e64),
        GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/0, // DstI[vdst]
        GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/0, // src0
        GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/1, // src1
        GIR_ConstrainSelectedInstOperands, /*InsnID*/0,
        GIR_EraseFromParent, /*InsnID*/0,
        // GIR_Coverage, 911,
        GIR_Done,
      // Label 3784: @244937
      GIM_Reject,
    // Label 3778: @244938
    GIM_Reject,
    // Label 3763: @244939
    GIM_Try, /*On fail goto*//*Label 3785*/ GIMT_Encode4(245124),
      GIM_CheckType, /*MI*/0, /*Op*/1, /*Type*/GILLT_v2s16,
      GIM_CheckType, /*MI*/0, /*Op*/2, /*Type*/GILLT_v2s16,
      GIM_CheckRegBankForClass, /*MI*/0, /*Op*/0, /*RC*/GIMT_Encode2(AMDGPU::VGPR_32RegClassID),
      GIM_Try, /*On fail goto*//*Label 3786*/ GIMT_Encode4(245056), // Rule ID 982 //
        GIM_RecordInsn, /*DefineMI*/1, /*MI*/0, /*OpIdx*/2, // MIs[1]
        GIM_CheckOpcode, /*MI*/1, GIMT_Encode2(TargetOpcode::G_AND),
        GIM_CheckType, /*MI*/1, /*Op*/1, /*Type*/GILLT_v2s16,
        GIM_CheckType, /*MI*/1, /*Op*/2, /*Type*/GILLT_v2s16,
        GIM_RecordInsn, /*DefineMI*/2, /*MI*/1, /*OpIdx*/2, // MIs[2]
        GIM_CheckOpcode, /*MI*/2, GIMT_Encode2(TargetOpcode::G_CONSTANT),
        // MIs[2] Operand 1
        // No operand predicates
        GIM_CheckCxxInsnPredicate, /*MI*/1, /*FnId*/GIMT_Encode2(GICXXPred_MI_Predicate_csh_mask_16),
        GIM_CheckIsSafeToFold, /*InsnID*/1,
        GIM_CheckIsSafeToFold, /*InsnID*/2,
        GIM_CheckComplexPattern, /*MI*/0, /*Op*/1, /*Renderer*/GIMT_Encode2(0), GIMT_Encode2(GICP_gi_vop3pmods),
        GIM_CheckComplexPattern, /*MI*/1, /*Op*/1, /*Renderer*/GIMT_Encode2(1), GIMT_Encode2(GICP_gi_vop3pmods),
        // (srl:{ *:[v2i16] } (VOP3PMods:{ *:[v2i16] } v2i16:{ *:[v2i16] }:$src1, i32:{ *:[i32] }:$src1_modifiers), (and:{ *:[v2i16] } (VOP3PMods:{ *:[v2i16] } v2i16:{ *:[v2i16] }:$src0, i32:{ *:[i32] }:$src0_modifiers), (imm:{ *:[v2i16] }))<<P:Predicate_csh_mask_16>>)  =>  (V_PK_LSHRREV_B16:{ *:[v2i16] } i32:{ *:[i32] }:$src0_modifiers, v2i16:{ *:[v2i16] }:$src0, i32:{ *:[i32] }:$src1_modifiers, v2i16:{ *:[v2i16] }:$src1)
        GIR_BuildMI, /*InsnID*/0, /*Opcode*/GIMT_Encode2(AMDGPU::V_PK_LSHRREV_B16),
        GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/0, // DstI[vdst]
        GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(1), /*SubOperand*/1, // src0_modifiers
        GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(1), /*SubOperand*/0, // src0
        GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/1, // src1_modifiers
        GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/0, // src1
        GIR_AddImm8, /*InsnID*/0, /*Imm*/0,
        GIR_AddImm8, /*InsnID*/0, /*Imm*/0,
        GIR_AddImm8, /*InsnID*/0, /*Imm*/0,
        GIR_AddImm8, /*InsnID*/0, /*Imm*/0,
        GIR_AddImm8, /*InsnID*/0, /*Imm*/0,
        GIR_ConstrainSelectedInstOperands, /*InsnID*/0,
        GIR_EraseFromParent, /*InsnID*/0,
        // GIR_Coverage, 982,
        GIR_Done,
      // Label 3786: @245056
      GIM_Try, /*On fail goto*//*Label 3787*/ GIMT_Encode4(245123), // Rule ID 981 //
        GIM_CheckComplexPattern, /*MI*/0, /*Op*/1, /*Renderer*/GIMT_Encode2(0), GIMT_Encode2(GICP_gi_vop3pmods),
        GIM_CheckComplexPattern, /*MI*/0, /*Op*/2, /*Renderer*/GIMT_Encode2(1), GIMT_Encode2(GICP_gi_vop3pmods),
        // (srl:{ *:[v2i16] } (VOP3PMods:{ *:[v2i16] } v2i16:{ *:[v2i16] }:$src1, i32:{ *:[i32] }:$src1_modifiers), (VOP3PMods:{ *:[v2i16] } v2i16:{ *:[v2i16] }:$src0, i32:{ *:[i32] }:$src0_modifiers))  =>  (V_PK_LSHRREV_B16:{ *:[v2i16] } i32:{ *:[i32] }:$src0_modifiers, v2i16:{ *:[v2i16] }:$src0, i32:{ *:[i32] }:$src1_modifiers, v2i16:{ *:[v2i16] }:$src1)
        GIR_BuildMI, /*InsnID*/0, /*Opcode*/GIMT_Encode2(AMDGPU::V_PK_LSHRREV_B16),
        GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/0, // DstI[vdst]
        GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(1), /*SubOperand*/1, // src0_modifiers
        GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(1), /*SubOperand*/0, // src0
        GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/1, // src1_modifiers
        GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/0, // src1
        GIR_AddImm8, /*InsnID*/0, /*Imm*/0,
        GIR_AddImm8, /*InsnID*/0, /*Imm*/0,
        GIR_AddImm8, /*InsnID*/0, /*Imm*/0,
        GIR_AddImm8, /*InsnID*/0, /*Imm*/0,
        GIR_AddImm8, /*InsnID*/0, /*Imm*/0,
        GIR_ConstrainSelectedInstOperands, /*InsnID*/0,
        GIR_EraseFromParent, /*InsnID*/0,
        // GIR_Coverage, 981,
        GIR_Done,
      // Label 3787: @245123
      GIM_Reject,
    // Label 3785: @245124
    GIM_Reject,
    // Label 3764: @245125
    GIM_Reject,
    // Label 44: @245126
    GIM_SwitchType, /*MI*/0, /*Op*/0, /*[*/GIMT_Encode2(8), GIMT_Encode2(12), /*)*//*default:*//*Label 3792*/ GIMT_Encode4(246257),
    /*GILLT_s16*//*Label 3788*/ GIMT_Encode4(245153),
    /*GILLT_s32*//*Label 3789*/ GIMT_Encode4(245353),
    /*GILLT_s64*//*Label 3790*/ GIMT_Encode4(245706),
    /*GILLT_v2s16*//*Label 3791*/ GIMT_Encode4(246071),
    // Label 3788: @245153
    GIM_Try, /*On fail goto*//*Label 3793*/ GIMT_Encode4(245352),
      GIM_CheckType, /*MI*/0, /*Op*/1, /*Type*/GILLT_s16,
      GIM_CheckType, /*MI*/0, /*Op*/2, /*Type*/GILLT_s16,
      GIM_CheckRegBankForClass, /*MI*/0, /*Op*/0, /*RC*/GIMT_Encode2(AMDGPU::VGPR_32RegClassID),
      GIM_Try, /*On fail goto*//*Label 3794*/ GIMT_Encode4(245232), // Rule ID 790 //
        GIM_CheckFeatures, GIMT_Encode2(GIFBS_Has16BitInsts_NotHasTrue16BitInsts),
        GIM_RecordInsn, /*DefineMI*/1, /*MI*/0, /*OpIdx*/2, // MIs[1]
        GIM_CheckOpcode, /*MI*/1, GIMT_Encode2(TargetOpcode::G_AND),
        GIM_CheckType, /*MI*/1, /*Op*/1, /*Type*/GILLT_s16,
        GIM_CheckType, /*MI*/1, /*Op*/2, /*Type*/GILLT_s16,
        GIM_RecordInsn, /*DefineMI*/2, /*MI*/1, /*OpIdx*/2, // MIs[2]
        GIM_CheckOpcode, /*MI*/2, GIMT_Encode2(TargetOpcode::G_CONSTANT),
        // MIs[2] Operand 1
        // No operand predicates
        GIM_CheckCxxInsnPredicate, /*MI*/1, /*FnId*/GIMT_Encode2(GICXXPred_MI_Predicate_csh_mask_16),
        GIM_CheckIsSafeToFold, /*InsnID*/1,
        GIM_CheckIsSafeToFold, /*InsnID*/2,
        // (sra:{ *:[i16] } i16:{ *:[i16] }:$src1, (and:{ *:[i16] } i16:{ *:[i16] }:$src0, (imm:{ *:[i16] }))<<P:Predicate_csh_mask_16>>)  =>  (V_ASHRREV_I16_e64:{ *:[i16] } i16:{ *:[i16] }:$src0, i16:{ *:[i16] }:$src1)
        GIR_BuildMI, /*InsnID*/0, /*Opcode*/GIMT_Encode2(AMDGPU::V_ASHRREV_I16_e64),
        GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/0, // DstI[vdst]
        GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/1, /*OpIdx*/1, // src0
        GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/1, // src1
        GIR_ConstrainSelectedInstOperands, /*InsnID*/0,
        GIR_EraseFromParent, /*InsnID*/0,
        // GIR_Coverage, 790,
        GIR_Done,
      // Label 3794: @245232
      GIM_Try, /*On fail goto*//*Label 3795*/ GIMT_Encode4(245293), // Rule ID 792 //
        GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasTrue16BitInsts),
        GIM_RecordInsn, /*DefineMI*/1, /*MI*/0, /*OpIdx*/2, // MIs[1]
        GIM_CheckOpcode, /*MI*/1, GIMT_Encode2(TargetOpcode::G_AND),
        GIM_CheckType, /*MI*/1, /*Op*/1, /*Type*/GILLT_s16,
        GIM_CheckType, /*MI*/1, /*Op*/2, /*Type*/GILLT_s16,
        GIM_RecordInsn, /*DefineMI*/2, /*MI*/1, /*OpIdx*/2, // MIs[2]
        GIM_CheckOpcode, /*MI*/2, GIMT_Encode2(TargetOpcode::G_CONSTANT),
        // MIs[2] Operand 1
        // No operand predicates
        GIM_CheckCxxInsnPredicate, /*MI*/1, /*FnId*/GIMT_Encode2(GICXXPred_MI_Predicate_csh_mask_16),
        GIM_CheckIsSafeToFold, /*InsnID*/1,
        GIM_CheckIsSafeToFold, /*InsnID*/2,
        // (sra:{ *:[i16] } i16:{ *:[i16] }:$src1, (and:{ *:[i16] } i16:{ *:[i16] }:$src0, (imm:{ *:[i16] }))<<P:Predicate_csh_mask_16>>)  =>  (V_ASHRREV_I16_t16_e64:{ *:[i16] } i16:{ *:[i16] }:$src0, i16:{ *:[i16] }:$src1)
        GIR_BuildMI, /*InsnID*/0, /*Opcode*/GIMT_Encode2(AMDGPU::V_ASHRREV_I16_t16_e64),
        GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/0, // DstI[vdst]
        GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/1, /*OpIdx*/1, // src0
        GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/1, // src1
        GIR_ConstrainSelectedInstOperands, /*InsnID*/0,
        GIR_EraseFromParent, /*InsnID*/0,
        // GIR_Coverage, 792,
        GIR_Done,
      // Label 3795: @245293
      GIM_Try, /*On fail goto*//*Label 3796*/ GIMT_Encode4(245322), // Rule ID 789 //
        GIM_CheckFeatures, GIMT_Encode2(GIFBS_Has16BitInsts_NotHasTrue16BitInsts),
        // (sra:{ *:[i16] } i16:{ *:[i16] }:$src1, i16:{ *:[i16] }:$src0)  =>  (V_ASHRREV_I16_e64:{ *:[i16] } i16:{ *:[i16] }:$src0, i16:{ *:[i16] }:$src1)
        GIR_BuildMI, /*InsnID*/0, /*Opcode*/GIMT_Encode2(AMDGPU::V_ASHRREV_I16_e64),
        GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/0, // DstI[vdst]
        GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/2, // src0
        GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/1, // src1
        GIR_ConstrainSelectedInstOperands, /*InsnID*/0,
        GIR_EraseFromParent, /*InsnID*/0,
        // GIR_Coverage, 789,
        GIR_Done,
      // Label 3796: @245322
      GIM_Try, /*On fail goto*//*Label 3797*/ GIMT_Encode4(245351), // Rule ID 791 //
        GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasTrue16BitInsts),
        // (sra:{ *:[i16] } i16:{ *:[i16] }:$src1, i16:{ *:[i16] }:$src0)  =>  (V_ASHRREV_I16_t16_e64:{ *:[i16] } i16:{ *:[i16] }:$src0, i16:{ *:[i16] }:$src1)
        GIR_BuildMI, /*InsnID*/0, /*Opcode*/GIMT_Encode2(AMDGPU::V_ASHRREV_I16_t16_e64),
        GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/0, // DstI[vdst]
        GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/2, // src0
        GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/1, // src1
        GIR_ConstrainSelectedInstOperands, /*InsnID*/0,
        GIR_EraseFromParent, /*InsnID*/0,
        // GIR_Coverage, 791,
        GIR_Done,
      // Label 3797: @245351
      GIM_Reject,
    // Label 3793: @245352
    GIM_Reject,
    // Label 3789: @245353
    GIM_Try, /*On fail goto*//*Label 3798*/ GIMT_Encode4(245705),
      GIM_CheckType, /*MI*/0, /*Op*/1, /*Type*/GILLT_s32,
      GIM_CheckType, /*MI*/0, /*Op*/2, /*Type*/GILLT_s32,
      GIM_Try, /*On fail goto*//*Label 3799*/ GIMT_Encode4(245446), // Rule ID 79 //
        GIM_CheckRegBankForClass, /*MI*/0, /*Op*/0, /*RC*/GIMT_Encode2(AMDGPU::SReg_32RegClassID),
        GIM_CheckRegBankForClass, /*MI*/0, /*Op*/1, /*RC*/GIMT_Encode2(AMDGPU::SReg_32RegClassID),
        GIM_RecordInsn, /*DefineMI*/1, /*MI*/0, /*OpIdx*/2, // MIs[1]
        GIM_CheckOpcode, /*MI*/1, GIMT_Encode2(TargetOpcode::G_AND),
        GIM_CheckType, /*MI*/1, /*Op*/1, /*Type*/GILLT_s32,
        GIM_CheckType, /*MI*/1, /*Op*/2, /*Type*/GILLT_s32,
        GIM_CheckRegBankForClass, /*MI*/1, /*Op*/1, /*RC*/GIMT_Encode2(AMDGPU::SReg_32RegClassID),
        GIM_RecordInsn, /*DefineMI*/2, /*MI*/1, /*OpIdx*/2, // MIs[2]
        GIM_CheckOpcode, /*MI*/2, GIMT_Encode2(TargetOpcode::G_CONSTANT),
        // MIs[2] Operand 1
        // No operand predicates
        GIM_CheckCxxInsnPredicate, /*MI*/1, /*FnId*/GIMT_Encode2(GICXXPred_MI_Predicate_csh_mask_32),
        GIM_CheckCxxInsnPredicate, /*MI*/0, /*FnId*/GIMT_Encode2(GICXXPred_MI_Predicate_anonymous_17622),
        GIM_CheckIsSafeToFold, /*InsnID*/1,
        GIM_CheckIsSafeToFold, /*InsnID*/2,
        // (sra:{ *:[i32] } SSrc_b32:{ *:[i32] }:$src0, (and:{ *:[i32] } SSrc_b32:{ *:[i32] }:$src1, (imm:{ *:[i32] }))<<P:Predicate_csh_mask_32>>)<<P:Predicate_anonymous_17622>>  =>  (S_ASHR_I32:{ *:[i32] }:{ *:[i1] } SSrc_b32:{ *:[i32] }:$src0, SSrc_b32:{ *:[i32] }:$src1)
        GIR_BuildMI, /*InsnID*/0, /*Opcode*/GIMT_Encode2(AMDGPU::S_ASHR_I32),
        GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/0, // DstI[sdst]
        GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/1, // src0
        GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/1, /*OpIdx*/1, // src1
        GIR_SetImplicitDefDead, /*InsnID*/0, /*OpIdx for AMDGPU::SCC*/0,
        GIR_ConstrainSelectedInstOperands, /*InsnID*/0,
        GIR_EraseFromParent, /*InsnID*/0,
        // GIR_Coverage, 79,
        GIR_Done,
      // Label 3799: @245446
      GIM_Try, /*On fail goto*//*Label 3800*/ GIMT_Encode4(245484), // Rule ID 78 //
        GIM_CheckRegBankForClass, /*MI*/0, /*Op*/0, /*RC*/GIMT_Encode2(AMDGPU::SReg_32RegClassID),
        GIM_CheckRegBankForClass, /*MI*/0, /*Op*/1, /*RC*/GIMT_Encode2(AMDGPU::SReg_32RegClassID),
        GIM_CheckRegBankForClass, /*MI*/0, /*Op*/2, /*RC*/GIMT_Encode2(AMDGPU::SReg_32RegClassID),
        GIM_CheckCxxInsnPredicate, /*MI*/0, /*FnId*/GIMT_Encode2(GICXXPred_MI_Predicate_anonymous_17622),
        // (sra:{ *:[i32] } SSrc_b32:{ *:[i32] }:$src0, SSrc_b32:{ *:[i32] }:$src1)<<P:Predicate_anonymous_17622>>  =>  (S_ASHR_I32:{ *:[i32] }:{ *:[i1] } SSrc_b32:{ *:[i32] }:$src0, SSrc_b32:{ *:[i32] }:$src1)
        GIR_MutateOpcode, /*InsnID*/0, /*RecycleInsnID*/0, /*Opcode*/GIMT_Encode2(AMDGPU::S_ASHR_I32),
        GIR_AddImplicitDef, /*InsnID*/0, GIMT_Encode2(AMDGPU::SCC), GIMT_Encode2(RegState::Dead),
        GIR_ConstrainSelectedInstOperands, /*InsnID*/0,
        // GIR_Coverage, 78,
        GIR_Done,
      // Label 3800: @245484
      GIM_Try, /*On fail goto*//*Label 3801*/ GIMT_Encode4(245519), // Rule ID 2094 //
        GIM_CheckRegBankForClass, /*MI*/0, /*Op*/0, /*RC*/GIMT_Encode2(AMDGPU::VGPR_32RegClassID),
        GIM_CheckCxxInsnPredicate, /*MI*/0, /*FnId*/GIMT_Encode2(GICXXPred_MI_Predicate_anonymous_22541),
        // (sra:{ *:[i32] } i32:{ *:[i32] }:$src0, i32:{ *:[i32] }:$src1)<<P:Predicate_anonymous_22541>>  =>  (V_ASHRREV_I32_e64:{ *:[i32] } ?:{ *:[i32] }:$src1, ?:{ *:[i32] }:$src0)
        GIR_BuildMI, /*InsnID*/0, /*Opcode*/GIMT_Encode2(AMDGPU::V_ASHRREV_I32_e64),
        GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/0, // DstI[vdst]
        GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/2, // src1
        GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/1, // src0
        GIR_ConstrainSelectedInstOperands, /*InsnID*/0,
        GIR_EraseFromParent, /*InsnID*/0,
        // GIR_Coverage, 2094,
        GIR_Done,
      // Label 3801: @245519
      GIM_Try, /*On fail goto*//*Label 3802*/ GIMT_Encode4(245582), // Rule ID 750 //
        GIM_CheckRegBankForClass, /*MI*/0, /*Op*/0, /*RC*/GIMT_Encode2(AMDGPU::VGPR_32RegClassID),
        GIM_RecordInsn, /*DefineMI*/1, /*MI*/0, /*OpIdx*/2, // MIs[1]
        GIM_CheckOpcode, /*MI*/1, GIMT_Encode2(TargetOpcode::G_AND),
        GIM_CheckType, /*MI*/1, /*Op*/1, /*Type*/GILLT_s32,
        GIM_CheckType, /*MI*/1, /*Op*/2, /*Type*/GILLT_s32,
        GIM_RecordInsn, /*DefineMI*/2, /*MI*/1, /*OpIdx*/2, // MIs[2]
        GIM_CheckOpcode, /*MI*/2, GIMT_Encode2(TargetOpcode::G_CONSTANT),
        // MIs[2] Operand 1
        // No operand predicates
        GIM_CheckCxxInsnPredicate, /*MI*/1, /*FnId*/GIMT_Encode2(GICXXPred_MI_Predicate_csh_mask_32),
        GIM_CheckIsSafeToFold, /*InsnID*/1,
        GIM_CheckIsSafeToFold, /*InsnID*/2,
        // (sra:{ *:[i32] } i32:{ *:[i32] }:$src1, (and:{ *:[i32] } i32:{ *:[i32] }:$src0, (imm:{ *:[i32] }))<<P:Predicate_csh_mask_32>>)  =>  (V_ASHRREV_I32_e64:{ *:[i32] } i32:{ *:[i32] }:$src0, i32:{ *:[i32] }:$src1)
        GIR_BuildMI, /*InsnID*/0, /*Opcode*/GIMT_Encode2(AMDGPU::V_ASHRREV_I32_e64),
        GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/0, // DstI[vdst]
        GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/1, /*OpIdx*/1, // src0
        GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/1, // src1
        GIR_ConstrainSelectedInstOperands, /*InsnID*/0,
        GIR_EraseFromParent, /*InsnID*/0,
        // GIR_Coverage, 750,
        GIR_Done,
      // Label 3802: @245582
      GIM_Try, /*On fail goto*//*Label 3803*/ GIMT_Encode4(245648), // Rule ID 778 //
        GIM_CheckFeatures, GIMT_Encode2(GIFBS_isGFX6GFX7),
        GIM_CheckRegBankForClass, /*MI*/0, /*Op*/0, /*RC*/GIMT_Encode2(AMDGPU::VGPR_32RegClassID),
        GIM_RecordInsn, /*DefineMI*/1, /*MI*/0, /*OpIdx*/2, // MIs[1]
        GIM_CheckOpcode, /*MI*/1, GIMT_Encode2(TargetOpcode::G_AND),
        GIM_CheckType, /*MI*/1, /*Op*/1, /*Type*/GILLT_s32,
        GIM_CheckType, /*MI*/1, /*Op*/2, /*Type*/GILLT_s32,
        GIM_RecordInsn, /*DefineMI*/2, /*MI*/1, /*OpIdx*/2, // MIs[2]
        GIM_CheckOpcode, /*MI*/2, GIMT_Encode2(TargetOpcode::G_CONSTANT),
        // MIs[2] Operand 1
        // No operand predicates
        GIM_CheckCxxInsnPredicate, /*MI*/1, /*FnId*/GIMT_Encode2(GICXXPred_MI_Predicate_csh_mask_32),
        GIM_CheckIsSafeToFold, /*InsnID*/1,
        GIM_CheckIsSafeToFold, /*InsnID*/2,
        // (sra:{ *:[i32] } i32:{ *:[i32] }:$src0, (and:{ *:[i32] } i32:{ *:[i32] }:$src1, (imm:{ *:[i32] }))<<P:Predicate_csh_mask_32>>)  =>  (V_ASHR_I32_e64:{ *:[i32] } i32:{ *:[i32] }:$src0, i32:{ *:[i32] }:$src1)
        GIR_BuildMI, /*InsnID*/0, /*Opcode*/GIMT_Encode2(AMDGPU::V_ASHR_I32_e64),
        GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/0, // DstI[vdst]
        GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/1, // src0
        GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/1, /*OpIdx*/1, // src1
        GIR_ConstrainSelectedInstOperands, /*InsnID*/0,
        GIR_EraseFromParent, /*InsnID*/0,
        // GIR_Coverage, 778,
        GIR_Done,
      // Label 3803: @245648
      GIM_Try, /*On fail goto*//*Label 3804*/ GIMT_Encode4(245679), // Rule ID 749 //
        GIM_CheckRegBankForClass, /*MI*/0, /*Op*/0, /*RC*/GIMT_Encode2(AMDGPU::VGPR_32RegClassID),
        // (sra:{ *:[i32] } i32:{ *:[i32] }:$src1, i32:{ *:[i32] }:$src0)  =>  (V_ASHRREV_I32_e64:{ *:[i32] } i32:{ *:[i32] }:$src0, i32:{ *:[i32] }:$src1)
        GIR_BuildMI, /*InsnID*/0, /*Opcode*/GIMT_Encode2(AMDGPU::V_ASHRREV_I32_e64),
        GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/0, // DstI[vdst]
        GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/2, // src0
        GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/1, // src1
        GIR_ConstrainSelectedInstOperands, /*InsnID*/0,
        GIR_EraseFromParent, /*InsnID*/0,
        // GIR_Coverage, 749,
        GIR_Done,
      // Label 3804: @245679
      GIM_Try, /*On fail goto*//*Label 3805*/ GIMT_Encode4(245704), // Rule ID 777 //
        GIM_CheckFeatures, GIMT_Encode2(GIFBS_isGFX6GFX7),
        GIM_CheckRegBankForClass, /*MI*/0, /*Op*/0, /*RC*/GIMT_Encode2(AMDGPU::VGPR_32RegClassID),
        // (sra:{ *:[i32] } i32:{ *:[i32] }:$src0, i32:{ *:[i32] }:$src1)  =>  (V_ASHR_I32_e64:{ *:[i32] } i32:{ *:[i32] }:$src0, i32:{ *:[i32] }:$src1)
        GIR_MutateOpcode, /*InsnID*/0, /*RecycleInsnID*/0, /*Opcode*/GIMT_Encode2(AMDGPU::V_ASHR_I32_e64),
        GIR_AddImplicitUse, /*InsnID*/0, GIMT_Encode2(AMDGPU::EXEC),
        GIR_ConstrainSelectedInstOperands, /*InsnID*/0,
        // GIR_Coverage, 777,
        GIR_Done,
      // Label 3805: @245704
      GIM_Reject,
    // Label 3798: @245705
    GIM_Reject,
    // Label 3790: @245706
    GIM_Try, /*On fail goto*//*Label 3806*/ GIMT_Encode4(246070),
      GIM_CheckType, /*MI*/0, /*Op*/1, /*Type*/GILLT_s64,
      GIM_CheckType, /*MI*/0, /*Op*/2, /*Type*/GILLT_s32,
      GIM_Try, /*On fail goto*//*Label 3807*/ GIMT_Encode4(245799), // Rule ID 81 //
        GIM_CheckRegBankForClass, /*MI*/0, /*Op*/0, /*RC*/GIMT_Encode2(AMDGPU::SReg_64RegClassID),
        GIM_CheckRegBankForClass, /*MI*/0, /*Op*/1, /*RC*/GIMT_Encode2(AMDGPU::SReg_64RegClassID),
        GIM_RecordInsn, /*DefineMI*/1, /*MI*/0, /*OpIdx*/2, // MIs[1]
        GIM_CheckOpcode, /*MI*/1, GIMT_Encode2(TargetOpcode::G_AND),
        GIM_CheckType, /*MI*/1, /*Op*/1, /*Type*/GILLT_s32,
        GIM_CheckType, /*MI*/1, /*Op*/2, /*Type*/GILLT_s32,
        GIM_CheckRegBankForClass, /*MI*/1, /*Op*/1, /*RC*/GIMT_Encode2(AMDGPU::SReg_32RegClassID),
        GIM_RecordInsn, /*DefineMI*/2, /*MI*/1, /*OpIdx*/2, // MIs[2]
        GIM_CheckOpcode, /*MI*/2, GIMT_Encode2(TargetOpcode::G_CONSTANT),
        // MIs[2] Operand 1
        // No operand predicates
        GIM_CheckCxxInsnPredicate, /*MI*/1, /*FnId*/GIMT_Encode2(GICXXPred_MI_Predicate_csh_mask_64),
        GIM_CheckCxxInsnPredicate, /*MI*/0, /*FnId*/GIMT_Encode2(GICXXPred_MI_Predicate_anonymous_17623),
        GIM_CheckIsSafeToFold, /*InsnID*/1,
        GIM_CheckIsSafeToFold, /*InsnID*/2,
        // (sra:{ *:[i64] } SSrc_b64:{ *:[i64] }:$src0, (and:{ *:[i32] } SSrc_b32:{ *:[i32] }:$src1, (imm:{ *:[i32] }))<<P:Predicate_csh_mask_64>>)<<P:Predicate_anonymous_17623>>  =>  (S_ASHR_I64:{ *:[i64] }:{ *:[i1] } SSrc_b64:{ *:[i64] }:$src0, SSrc_b32:{ *:[i32] }:$src1)
        GIR_BuildMI, /*InsnID*/0, /*Opcode*/GIMT_Encode2(AMDGPU::S_ASHR_I64),
        GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/0, // DstI[sdst]
        GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/1, // src0
        GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/1, /*OpIdx*/1, // src1
        GIR_SetImplicitDefDead, /*InsnID*/0, /*OpIdx for AMDGPU::SCC*/0,
        GIR_ConstrainSelectedInstOperands, /*InsnID*/0,
        GIR_EraseFromParent, /*InsnID*/0,
        // GIR_Coverage, 81,
        GIR_Done,
      // Label 3807: @245799
      GIM_Try, /*On fail goto*//*Label 3808*/ GIMT_Encode4(245837), // Rule ID 80 //
        GIM_CheckRegBankForClass, /*MI*/0, /*Op*/0, /*RC*/GIMT_Encode2(AMDGPU::SReg_64RegClassID),
        GIM_CheckRegBankForClass, /*MI*/0, /*Op*/1, /*RC*/GIMT_Encode2(AMDGPU::SReg_64RegClassID),
        GIM_CheckRegBankForClass, /*MI*/0, /*Op*/2, /*RC*/GIMT_Encode2(AMDGPU::SReg_32RegClassID),
        GIM_CheckCxxInsnPredicate, /*MI*/0, /*FnId*/GIMT_Encode2(GICXXPred_MI_Predicate_anonymous_17623),
        // (sra:{ *:[i64] } SSrc_b64:{ *:[i64] }:$src0, SSrc_b32:{ *:[i32] }:$src1)<<P:Predicate_anonymous_17623>>  =>  (S_ASHR_I64:{ *:[i64] }:{ *:[i1] } SSrc_b64:{ *:[i64] }:$src0, SSrc_b32:{ *:[i32] }:$src1)
        GIR_MutateOpcode, /*InsnID*/0, /*RecycleInsnID*/0, /*Opcode*/GIMT_Encode2(AMDGPU::S_ASHR_I64),
        GIR_AddImplicitDef, /*InsnID*/0, GIMT_Encode2(AMDGPU::SCC), GIMT_Encode2(RegState::Dead),
        GIR_ConstrainSelectedInstOperands, /*InsnID*/0,
        // GIR_Coverage, 80,
        GIR_Done,
      // Label 3808: @245837
      GIM_Try, /*On fail goto*//*Label 3809*/ GIMT_Encode4(245911), // Rule ID 910 //
        GIM_CheckFeatures, GIMT_Encode2(GIFBS_isGFX6GFX7),
        GIM_CheckRegBankForClass, /*MI*/0, /*Op*/0, /*RC*/GIMT_Encode2(AMDGPU::VReg_64RegClassID),
        GIM_RecordInsn, /*DefineMI*/1, /*MI*/0, /*OpIdx*/2, // MIs[1]
        GIM_CheckOpcode, /*MI*/1, GIMT_Encode2(TargetOpcode::G_AND),
        GIM_CheckType, /*MI*/1, /*Op*/1, /*Type*/GILLT_s32,
        GIM_CheckType, /*MI*/1, /*Op*/2, /*Type*/GILLT_s32,
        GIM_RecordInsn, /*DefineMI*/2, /*MI*/1, /*OpIdx*/2, // MIs[2]
        GIM_CheckOpcode, /*MI*/2, GIMT_Encode2(TargetOpcode::G_CONSTANT),
        // MIs[2] Operand 1
        // No operand predicates
        GIM_CheckCxxInsnPredicate, /*MI*/1, /*FnId*/GIMT_Encode2(GICXXPred_MI_Predicate_csh_mask_64),
        GIM_CheckIsSafeToFold, /*InsnID*/1,
        GIM_CheckIsSafeToFold, /*InsnID*/2,
        GIM_CheckComplexPattern, /*MI*/0, /*Op*/1, /*Renderer*/GIMT_Encode2(0), GIMT_Encode2(GICP_gi_vop3mods0),
        // (sra:{ *:[i64] } (VOP3Mods0:{ *:[i64] } i64:{ *:[i64] }:$src0), (and:{ *:[i32] } i32:{ *:[i32] }:$src1, (imm:{ *:[i32] }))<<P:Predicate_csh_mask_64>>)  =>  (V_ASHR_I64_e64:{ *:[i64] } i64:{ *:[i64] }:$src0, i32:{ *:[i32] }:$src1)
        GIR_BuildMI, /*InsnID*/0, /*Opcode*/GIMT_Encode2(AMDGPU::V_ASHR_I64_e64),
        GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/0, // DstI[vdst]
        GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/0, // src0
        GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/1, /*OpIdx*/1, // src1
        GIR_ConstrainSelectedInstOperands, /*InsnID*/0,
        GIR_EraseFromParent, /*InsnID*/0,
        // GIR_Coverage, 910,
        GIR_Done,
      // Label 3809: @245911
      GIM_Try, /*On fail goto*//*Label 3810*/ GIMT_Encode4(245985), // Rule ID 914 //
        GIM_CheckFeatures, GIMT_Encode2(GIFBS_isGFX8Plus),
        GIM_CheckRegBankForClass, /*MI*/0, /*Op*/0, /*RC*/GIMT_Encode2(AMDGPU::VReg_64RegClassID),
        GIM_RecordInsn, /*DefineMI*/1, /*MI*/0, /*OpIdx*/2, // MIs[1]
        GIM_CheckOpcode, /*MI*/1, GIMT_Encode2(TargetOpcode::G_AND),
        GIM_CheckType, /*MI*/1, /*Op*/1, /*Type*/GILLT_s32,
        GIM_CheckType, /*MI*/1, /*Op*/2, /*Type*/GILLT_s32,
        GIM_RecordInsn, /*DefineMI*/2, /*MI*/1, /*OpIdx*/2, // MIs[2]
        GIM_CheckOpcode, /*MI*/2, GIMT_Encode2(TargetOpcode::G_CONSTANT),
        // MIs[2] Operand 1
        // No operand predicates
        GIM_CheckCxxInsnPredicate, /*MI*/1, /*FnId*/GIMT_Encode2(GICXXPred_MI_Predicate_csh_mask_64),
        GIM_CheckIsSafeToFold, /*InsnID*/1,
        GIM_CheckIsSafeToFold, /*InsnID*/2,
        GIM_CheckComplexPattern, /*MI*/1, /*Op*/1, /*Renderer*/GIMT_Encode2(0), GIMT_Encode2(GICP_gi_vop3mods0),
        // (sra:{ *:[i64] } i64:{ *:[i64] }:$src1, (and:{ *:[i32] } (VOP3Mods0:{ *:[i32] } i32:{ *:[i32] }:$src0), (imm:{ *:[i32] }))<<P:Predicate_csh_mask_64>>)  =>  (V_ASHRREV_I64_e64:{ *:[i64] } i32:{ *:[i32] }:$src0, i64:{ *:[i64] }:$src1)
        GIR_BuildMI, /*InsnID*/0, /*Opcode*/GIMT_Encode2(AMDGPU::V_ASHRREV_I64_e64),
        GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/0, // DstI[vdst]
        GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/0, // src0
        GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/1, // src1
        GIR_ConstrainSelectedInstOperands, /*InsnID*/0,
        GIR_EraseFromParent, /*InsnID*/0,
        // GIR_Coverage, 914,
        GIR_Done,
      // Label 3810: @245985
      GIM_Try, /*On fail goto*//*Label 3811*/ GIMT_Encode4(246027), // Rule ID 909 //
        GIM_CheckFeatures, GIMT_Encode2(GIFBS_isGFX6GFX7),
        GIM_CheckRegBankForClass, /*MI*/0, /*Op*/0, /*RC*/GIMT_Encode2(AMDGPU::VReg_64RegClassID),
        GIM_CheckComplexPattern, /*MI*/0, /*Op*/1, /*Renderer*/GIMT_Encode2(0), GIMT_Encode2(GICP_gi_vop3mods0),
        // (sra:{ *:[i64] } (VOP3Mods0:{ *:[i64] } i64:{ *:[i64] }:$src0), i32:{ *:[i32] }:$src1)  =>  (V_ASHR_I64_e64:{ *:[i64] } i64:{ *:[i64] }:$src0, i32:{ *:[i32] }:$src1)
        GIR_BuildMI, /*InsnID*/0, /*Opcode*/GIMT_Encode2(AMDGPU::V_ASHR_I64_e64),
        GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/0, // DstI[vdst]
        GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/0, // src0
        GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/2, // src1
        GIR_ConstrainSelectedInstOperands, /*InsnID*/0,
        GIR_EraseFromParent, /*InsnID*/0,
        // GIR_Coverage, 909,
        GIR_Done,
      // Label 3811: @246027
      GIM_Try, /*On fail goto*//*Label 3812*/ GIMT_Encode4(246069), // Rule ID 913 //
        GIM_CheckFeatures, GIMT_Encode2(GIFBS_isGFX8Plus),
        GIM_CheckRegBankForClass, /*MI*/0, /*Op*/0, /*RC*/GIMT_Encode2(AMDGPU::VReg_64RegClassID),
        GIM_CheckComplexPattern, /*MI*/0, /*Op*/2, /*Renderer*/GIMT_Encode2(0), GIMT_Encode2(GICP_gi_vop3mods0),
        // (sra:{ *:[i64] } i64:{ *:[i64] }:$src1, (VOP3Mods0:{ *:[i32] } i32:{ *:[i32] }:$src0))  =>  (V_ASHRREV_I64_e64:{ *:[i64] } i32:{ *:[i32] }:$src0, i64:{ *:[i64] }:$src1)
        GIR_BuildMI, /*InsnID*/0, /*Opcode*/GIMT_Encode2(AMDGPU::V_ASHRREV_I64_e64),
        GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/0, // DstI[vdst]
        GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/0, // src0
        GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/1, // src1
        GIR_ConstrainSelectedInstOperands, /*InsnID*/0,
        GIR_EraseFromParent, /*InsnID*/0,
        // GIR_Coverage, 913,
        GIR_Done,
      // Label 3812: @246069
      GIM_Reject,
    // Label 3806: @246070
    GIM_Reject,
    // Label 3791: @246071
    GIM_Try, /*On fail goto*//*Label 3813*/ GIMT_Encode4(246256),
      GIM_CheckType, /*MI*/0, /*Op*/1, /*Type*/GILLT_v2s16,
      GIM_CheckType, /*MI*/0, /*Op*/2, /*Type*/GILLT_v2s16,
      GIM_CheckRegBankForClass, /*MI*/0, /*Op*/0, /*RC*/GIMT_Encode2(AMDGPU::VGPR_32RegClassID),
      GIM_Try, /*On fail goto*//*Label 3814*/ GIMT_Encode4(246188), // Rule ID 980 //
        GIM_RecordInsn, /*DefineMI*/1, /*MI*/0, /*OpIdx*/2, // MIs[1]
        GIM_CheckOpcode, /*MI*/1, GIMT_Encode2(TargetOpcode::G_AND),
        GIM_CheckType, /*MI*/1, /*Op*/1, /*Type*/GILLT_v2s16,
        GIM_CheckType, /*MI*/1, /*Op*/2, /*Type*/GILLT_v2s16,
        GIM_RecordInsn, /*DefineMI*/2, /*MI*/1, /*OpIdx*/2, // MIs[2]
        GIM_CheckOpcode, /*MI*/2, GIMT_Encode2(TargetOpcode::G_CONSTANT),
        // MIs[2] Operand 1
        // No operand predicates
        GIM_CheckCxxInsnPredicate, /*MI*/1, /*FnId*/GIMT_Encode2(GICXXPred_MI_Predicate_csh_mask_16),
        GIM_CheckIsSafeToFold, /*InsnID*/1,
        GIM_CheckIsSafeToFold, /*InsnID*/2,
        GIM_CheckComplexPattern, /*MI*/0, /*Op*/1, /*Renderer*/GIMT_Encode2(0), GIMT_Encode2(GICP_gi_vop3pmods),
        GIM_CheckComplexPattern, /*MI*/1, /*Op*/1, /*Renderer*/GIMT_Encode2(1), GIMT_Encode2(GICP_gi_vop3pmods),
        // (sra:{ *:[v2i16] } (VOP3PMods:{ *:[v2i16] } v2i16:{ *:[v2i16] }:$src1, i32:{ *:[i32] }:$src1_modifiers), (and:{ *:[v2i16] } (VOP3PMods:{ *:[v2i16] } v2i16:{ *:[v2i16] }:$src0, i32:{ *:[i32] }:$src0_modifiers), (imm:{ *:[v2i16] }))<<P:Predicate_csh_mask_16>>)  =>  (V_PK_ASHRREV_I16:{ *:[v2i16] } i32:{ *:[i32] }:$src0_modifiers, v2i16:{ *:[v2i16] }:$src0, i32:{ *:[i32] }:$src1_modifiers, v2i16:{ *:[v2i16] }:$src1)
        GIR_BuildMI, /*InsnID*/0, /*Opcode*/GIMT_Encode2(AMDGPU::V_PK_ASHRREV_I16),
        GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/0, // DstI[vdst]
        GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(1), /*SubOperand*/1, // src0_modifiers
        GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(1), /*SubOperand*/0, // src0
        GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/1, // src1_modifiers
        GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/0, // src1
        GIR_AddImm8, /*InsnID*/0, /*Imm*/0,
        GIR_AddImm8, /*InsnID*/0, /*Imm*/0,
        GIR_AddImm8, /*InsnID*/0, /*Imm*/0,
        GIR_AddImm8, /*InsnID*/0, /*Imm*/0,
        GIR_AddImm8, /*InsnID*/0, /*Imm*/0,
        GIR_ConstrainSelectedInstOperands, /*InsnID*/0,
        GIR_EraseFromParent, /*InsnID*/0,
        // GIR_Coverage, 980,
        GIR_Done,
      // Label 3814: @246188
      GIM_Try, /*On fail goto*//*Label 3815*/ GIMT_Encode4(246255), // Rule ID 979 //
        GIM_CheckComplexPattern, /*MI*/0, /*Op*/1, /*Renderer*/GIMT_Encode2(0), GIMT_Encode2(GICP_gi_vop3pmods),
        GIM_CheckComplexPattern, /*MI*/0, /*Op*/2, /*Renderer*/GIMT_Encode2(1), GIMT_Encode2(GICP_gi_vop3pmods),
        // (sra:{ *:[v2i16] } (VOP3PMods:{ *:[v2i16] } v2i16:{ *:[v2i16] }:$src1, i32:{ *:[i32] }:$src1_modifiers), (VOP3PMods:{ *:[v2i16] } v2i16:{ *:[v2i16] }:$src0, i32:{ *:[i32] }:$src0_modifiers))  =>  (V_PK_ASHRREV_I16:{ *:[v2i16] } i32:{ *:[i32] }:$src0_modifiers, v2i16:{ *:[v2i16] }:$src0, i32:{ *:[i32] }:$src1_modifiers, v2i16:{ *:[v2i16] }:$src1)
        GIR_BuildMI, /*InsnID*/0, /*Opcode*/GIMT_Encode2(AMDGPU::V_PK_ASHRREV_I16),
        GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/0, // DstI[vdst]
        GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(1), /*SubOperand*/1, // src0_modifiers
        GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(1), /*SubOperand*/0, // src0
        GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/1, // src1_modifiers
        GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/0, // src1
        GIR_AddImm8, /*InsnID*/0, /*Imm*/0,
        GIR_AddImm8, /*InsnID*/0, /*Imm*/0,
        GIR_AddImm8, /*InsnID*/0, /*Imm*/0,
        GIR_AddImm8, /*InsnID*/0, /*Imm*/0,
        GIR_AddImm8, /*InsnID*/0, /*Imm*/0,
        GIR_ConstrainSelectedInstOperands, /*InsnID*/0,
        GIR_EraseFromParent, /*InsnID*/0,
        // GIR_Coverage, 979,
        GIR_Done,
      // Label 3815: @246255
      GIM_Reject,
    // Label 3813: @246256
    GIM_Reject,
    // Label 3792: @246257
    GIM_Reject,
    // Label 45: @246258
    GIM_Try, /*On fail goto*//*Label 3816*/ GIMT_Encode4(246317), // Rule ID 883 //
      GIM_CheckType, /*MI*/0, /*Op*/0, /*Type*/GILLT_s32,
      GIM_CheckType, /*MI*/0, /*Op*/1, /*Type*/GILLT_s32,
      GIM_CheckType, /*MI*/0, /*Op*/2, /*Type*/GILLT_s32,
      GIM_CheckType, /*MI*/0, /*Op*/3, /*Type*/GILLT_s32,
      GIM_CheckRegBankForClass, /*MI*/0, /*Op*/0, /*RC*/GIMT_Encode2(AMDGPU::VGPR_32RegClassID),
      GIM_CheckComplexPattern, /*MI*/0, /*Op*/1, /*Renderer*/GIMT_Encode2(0), GIMT_Encode2(GICP_gi_vop3mods0),
      // (fshr:{ *:[i32] } (VOP3Mods0:{ *:[i32] } i32:{ *:[i32] }:$src0), i32:{ *:[i32] }:$src1, i32:{ *:[i32] }:$src2)  =>  (V_ALIGNBIT_B32_e64:{ *:[i32] } i32:{ *:[i32] }:$src0, i32:{ *:[i32] }:$src1, i32:{ *:[i32] }:$src2)
      GIR_BuildMI, /*InsnID*/0, /*Opcode*/GIMT_Encode2(AMDGPU::V_ALIGNBIT_B32_e64),
      GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/0, // DstI[vdst]
      GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/0, // src0
      GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/2, // src1
      GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/3, // src2
      GIR_ConstrainSelectedInstOperands, /*InsnID*/0,
      GIR_EraseFromParent, /*InsnID*/0,
      // GIR_Coverage, 883,
      GIR_Done,
    // Label 3816: @246317
    GIM_Reject,
    // Label 46: @246318
    GIM_Try, /*On fail goto*//*Label 3817*/ GIMT_Encode4(246365), // Rule ID 6282 //
      GIM_CheckType, /*MI*/0, /*Op*/0, /*Type*/GILLT_s32,
      GIM_CheckType, /*MI*/0, /*Op*/1, /*Type*/GILLT_s32,
      GIM_CheckType, /*MI*/0, /*Op*/2, /*Type*/GILLT_s32,
      GIM_CheckRegBankForClass, /*MI*/0, /*Op*/0, /*RC*/GIMT_Encode2(AMDGPU::VGPR_32RegClassID),
      // (rotr:{ *:[i32] } i32:{ *:[i32] }:$src0, i32:{ *:[i32] }:$src1)  =>  (V_ALIGNBIT_B32_e64:{ *:[i32] } ?:{ *:[i32] }:$src0, ?:{ *:[i32] }:$src0, ?:{ *:[i32] }:$src1)
      GIR_BuildMI, /*InsnID*/0, /*Opcode*/GIMT_Encode2(AMDGPU::V_ALIGNBIT_B32_e64),
      GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/0, // DstI[vdst]
      GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/1, // src0
      GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/1, // src0
      GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/2, // src1
      GIR_ConstrainSelectedInstOperands, /*InsnID*/0,
      GIR_EraseFromParent, /*InsnID*/0,
      // GIR_Coverage, 6282,
      GIR_Done,
    // Label 3817: @246365
    GIM_Reject,
    // Label 47: @246366
    GIM_Try, /*On fail goto*//*Label 3818*/ GIMT_Encode4(247798),
      GIM_CheckType, /*MI*/0, /*Op*/0, /*Type*/GILLT_s1,
      GIM_SwitchType, /*MI*/0, /*Op*/2, /*[*/GIMT_Encode2(8), GIMT_Encode2(11), /*)*//*default:*//*Label 3822*/ GIMT_Encode4(247374),
      /*GILLT_s16*//*Label 3819*/ GIMT_Encode4(246398),
      /*GILLT_s32*//*Label 3820*/ GIMT_Encode4(247094),
      /*GILLT_s64*//*Label 3821*/ GIMT_Encode4(247234),
      // Label 3819: @246398
      GIM_Try, /*On fail goto*//*Label 3823*/ GIMT_Encode4(247093),
        GIM_CheckType, /*MI*/0, /*Op*/3, /*Type*/GILLT_s16,
        GIM_CheckRegBankForClass, /*MI*/0, /*Op*/0, /*RC*/GIMT_Encode2(AMDGPU::SReg_1RegClassID),
        GIM_Try, /*On fail goto*//*Label 3824*/ GIMT_Encode4(246446), // Rule ID 423 //
          GIM_CheckFeatures, GIMT_Encode2(GIFBS_Has16BitInsts_NotHasTrue16BitInsts),
          // MIs[0] Operand 1
          GIM_CheckCmpPredicate, /*MI*/0, /*Op*/1, /*Predicate*/GIMT_Encode2(CmpInst::ICMP_SLT),
          // (setcc:{ *:[i1] } i16:{ *:[i16] }:$src0, i16:{ *:[i16] }:$src1, SETLT:{ *:[Other] })  =>  (V_CMP_LT_I16_e64:{ *:[i1] } i16:{ *:[i16] }:$src0, i16:{ *:[i16] }:$src1)
          GIR_BuildMI, /*InsnID*/0, /*Opcode*/GIMT_Encode2(AMDGPU::V_CMP_LT_I16_e64),
          GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/0, // DstI[sdst]
          GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/2, // src0
          GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/3, // src1
          GIR_ConstrainSelectedInstOperands, /*InsnID*/0,
          GIR_EraseFromParent, /*InsnID*/0,
          // GIR_Coverage, 423,
          GIR_Done,
        // Label 3824: @246446
        GIM_Try, /*On fail goto*//*Label 3825*/ GIMT_Encode4(246480), // Rule ID 424 //
          GIM_CheckFeatures, GIMT_Encode2(GIFBS_Has16BitInsts_HasTrue16BitInsts),
          // MIs[0] Operand 1
          GIM_CheckCmpPredicate, /*MI*/0, /*Op*/1, /*Predicate*/GIMT_Encode2(CmpInst::ICMP_SLT),
          // (setcc:{ *:[i1] } i16:{ *:[i16] }:$src0, i16:{ *:[i16] }:$src1, SETLT:{ *:[Other] })  =>  (V_CMP_LT_I16_t16_e64:{ *:[i1] } i16:{ *:[i16] }:$src0, i16:{ *:[i16] }:$src1)
          GIR_BuildMI, /*InsnID*/0, /*Opcode*/GIMT_Encode2(AMDGPU::V_CMP_LT_I16_t16_e64),
          GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/0, // DstI[sdst]
          GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/2, // src0
          GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/3, // src1
          GIR_ConstrainSelectedInstOperands, /*InsnID*/0,
          GIR_EraseFromParent, /*InsnID*/0,
          // GIR_Coverage, 424,
          GIR_Done,
        // Label 3825: @246480
        GIM_Try, /*On fail goto*//*Label 3826*/ GIMT_Encode4(246514), // Rule ID 427 //
          GIM_CheckFeatures, GIMT_Encode2(GIFBS_Has16BitInsts_NotHasTrue16BitInsts),
          // MIs[0] Operand 1
          GIM_CheckCmpPredicate, /*MI*/0, /*Op*/1, /*Predicate*/GIMT_Encode2(CmpInst::ICMP_SLE),
          // (setcc:{ *:[i1] } i16:{ *:[i16] }:$src0, i16:{ *:[i16] }:$src1, SETLE:{ *:[Other] })  =>  (V_CMP_LE_I16_e64:{ *:[i1] } i16:{ *:[i16] }:$src0, i16:{ *:[i16] }:$src1)
          GIR_BuildMI, /*InsnID*/0, /*Opcode*/GIMT_Encode2(AMDGPU::V_CMP_LE_I16_e64),
          GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/0, // DstI[sdst]
          GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/2, // src0
          GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/3, // src1
          GIR_ConstrainSelectedInstOperands, /*InsnID*/0,
          GIR_EraseFromParent, /*InsnID*/0,
          // GIR_Coverage, 427,
          GIR_Done,
        // Label 3826: @246514
        GIM_Try, /*On fail goto*//*Label 3827*/ GIMT_Encode4(246548), // Rule ID 428 //
          GIM_CheckFeatures, GIMT_Encode2(GIFBS_Has16BitInsts_HasTrue16BitInsts),
          // MIs[0] Operand 1
          GIM_CheckCmpPredicate, /*MI*/0, /*Op*/1, /*Predicate*/GIMT_Encode2(CmpInst::ICMP_SLE),
          // (setcc:{ *:[i1] } i16:{ *:[i16] }:$src0, i16:{ *:[i16] }:$src1, SETLE:{ *:[Other] })  =>  (V_CMP_LE_I16_t16_e64:{ *:[i1] } i16:{ *:[i16] }:$src0, i16:{ *:[i16] }:$src1)
          GIR_BuildMI, /*InsnID*/0, /*Opcode*/GIMT_Encode2(AMDGPU::V_CMP_LE_I16_t16_e64),
          GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/0, // DstI[sdst]
          GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/2, // src0
          GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/3, // src1
          GIR_ConstrainSelectedInstOperands, /*InsnID*/0,
          GIR_EraseFromParent, /*InsnID*/0,
          // GIR_Coverage, 428,
          GIR_Done,
        // Label 3827: @246548
        GIM_Try, /*On fail goto*//*Label 3828*/ GIMT_Encode4(246582), // Rule ID 429 //
          GIM_CheckFeatures, GIMT_Encode2(GIFBS_Has16BitInsts_NotHasTrue16BitInsts),
          // MIs[0] Operand 1
          GIM_CheckCmpPredicate, /*MI*/0, /*Op*/1, /*Predicate*/GIMT_Encode2(CmpInst::ICMP_SGT),
          // (setcc:{ *:[i1] } i16:{ *:[i16] }:$src0, i16:{ *:[i16] }:$src1, SETGT:{ *:[Other] })  =>  (V_CMP_GT_I16_e64:{ *:[i1] } i16:{ *:[i16] }:$src0, i16:{ *:[i16] }:$src1)
          GIR_BuildMI, /*InsnID*/0, /*Opcode*/GIMT_Encode2(AMDGPU::V_CMP_GT_I16_e64),
          GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/0, // DstI[sdst]
          GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/2, // src0
          GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/3, // src1
          GIR_ConstrainSelectedInstOperands, /*InsnID*/0,
          GIR_EraseFromParent, /*InsnID*/0,
          // GIR_Coverage, 429,
          GIR_Done,
        // Label 3828: @246582
        GIM_Try, /*On fail goto*//*Label 3829*/ GIMT_Encode4(246616), // Rule ID 430 //
          GIM_CheckFeatures, GIMT_Encode2(GIFBS_Has16BitInsts_HasTrue16BitInsts),
          // MIs[0] Operand 1
          GIM_CheckCmpPredicate, /*MI*/0, /*Op*/1, /*Predicate*/GIMT_Encode2(CmpInst::ICMP_SGT),
          // (setcc:{ *:[i1] } i16:{ *:[i16] }:$src0, i16:{ *:[i16] }:$src1, SETGT:{ *:[Other] })  =>  (V_CMP_GT_I16_t16_e64:{ *:[i1] } i16:{ *:[i16] }:$src0, i16:{ *:[i16] }:$src1)
          GIR_BuildMI, /*InsnID*/0, /*Opcode*/GIMT_Encode2(AMDGPU::V_CMP_GT_I16_t16_e64),
          GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/0, // DstI[sdst]
          GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/2, // src0
          GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/3, // src1
          GIR_ConstrainSelectedInstOperands, /*InsnID*/0,
          GIR_EraseFromParent, /*InsnID*/0,
          // GIR_Coverage, 430,
          GIR_Done,
        // Label 3829: @246616
        GIM_Try, /*On fail goto*//*Label 3830*/ GIMT_Encode4(246650), // Rule ID 433 //
          GIM_CheckFeatures, GIMT_Encode2(GIFBS_Has16BitInsts_NotHasTrue16BitInsts),
          // MIs[0] Operand 1
          GIM_CheckCmpPredicate, /*MI*/0, /*Op*/1, /*Predicate*/GIMT_Encode2(CmpInst::ICMP_SGE),
          // (setcc:{ *:[i1] } i16:{ *:[i16] }:$src0, i16:{ *:[i16] }:$src1, SETGE:{ *:[Other] })  =>  (V_CMP_GE_I16_e64:{ *:[i1] } i16:{ *:[i16] }:$src0, i16:{ *:[i16] }:$src1)
          GIR_BuildMI, /*InsnID*/0, /*Opcode*/GIMT_Encode2(AMDGPU::V_CMP_GE_I16_e64),
          GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/0, // DstI[sdst]
          GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/2, // src0
          GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/3, // src1
          GIR_ConstrainSelectedInstOperands, /*InsnID*/0,
          GIR_EraseFromParent, /*InsnID*/0,
          // GIR_Coverage, 433,
          GIR_Done,
        // Label 3830: @246650
        GIM_Try, /*On fail goto*//*Label 3831*/ GIMT_Encode4(246684), // Rule ID 434 //
          GIM_CheckFeatures, GIMT_Encode2(GIFBS_Has16BitInsts_HasTrue16BitInsts),
          // MIs[0] Operand 1
          GIM_CheckCmpPredicate, /*MI*/0, /*Op*/1, /*Predicate*/GIMT_Encode2(CmpInst::ICMP_SGE),
          // (setcc:{ *:[i1] } i16:{ *:[i16] }:$src0, i16:{ *:[i16] }:$src1, SETGE:{ *:[Other] })  =>  (V_CMP_GE_I16_t16_e64:{ *:[i1] } i16:{ *:[i16] }:$src0, i16:{ *:[i16] }:$src1)
          GIR_BuildMI, /*InsnID*/0, /*Opcode*/GIMT_Encode2(AMDGPU::V_CMP_GE_I16_t16_e64),
          GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/0, // DstI[sdst]
          GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/2, // src0
          GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/3, // src1
          GIR_ConstrainSelectedInstOperands, /*InsnID*/0,
          GIR_EraseFromParent, /*InsnID*/0,
          // GIR_Coverage, 434,
          GIR_Done,
        // Label 3831: @246684
        GIM_Try, /*On fail goto*//*Label 3832*/ GIMT_Encode4(246718), // Rule ID 439 //
          GIM_CheckFeatures, GIMT_Encode2(GIFBS_Has16BitInsts_NotHasTrue16BitInsts),
          // MIs[0] Operand 1
          GIM_CheckCmpPredicate, /*MI*/0, /*Op*/1, /*Predicate*/GIMT_Encode2(CmpInst::ICMP_ULT),
          // (setcc:{ *:[i1] } i16:{ *:[i16] }:$src0, i16:{ *:[i16] }:$src1, SETULT:{ *:[Other] })  =>  (V_CMP_LT_U16_e64:{ *:[i1] } i16:{ *:[i16] }:$src0, i16:{ *:[i16] }:$src1)
          GIR_BuildMI, /*InsnID*/0, /*Opcode*/GIMT_Encode2(AMDGPU::V_CMP_LT_U16_e64),
          GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/0, // DstI[sdst]
          GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/2, // src0
          GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/3, // src1
          GIR_ConstrainSelectedInstOperands, /*InsnID*/0,
          GIR_EraseFromParent, /*InsnID*/0,
          // GIR_Coverage, 439,
          GIR_Done,
        // Label 3832: @246718
        GIM_Try, /*On fail goto*//*Label 3833*/ GIMT_Encode4(246752), // Rule ID 440 //
          GIM_CheckFeatures, GIMT_Encode2(GIFBS_Has16BitInsts_HasTrue16BitInsts),
          // MIs[0] Operand 1
          GIM_CheckCmpPredicate, /*MI*/0, /*Op*/1, /*Predicate*/GIMT_Encode2(CmpInst::ICMP_ULT),
          // (setcc:{ *:[i1] } i16:{ *:[i16] }:$src0, i16:{ *:[i16] }:$src1, SETULT:{ *:[Other] })  =>  (V_CMP_LT_U16_t16_e64:{ *:[i1] } i16:{ *:[i16] }:$src0, i16:{ *:[i16] }:$src1)
          GIR_BuildMI, /*InsnID*/0, /*Opcode*/GIMT_Encode2(AMDGPU::V_CMP_LT_U16_t16_e64),
          GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/0, // DstI[sdst]
          GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/2, // src0
          GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/3, // src1
          GIR_ConstrainSelectedInstOperands, /*InsnID*/0,
          GIR_EraseFromParent, /*InsnID*/0,
          // GIR_Coverage, 440,
          GIR_Done,
        // Label 3833: @246752
        GIM_Try, /*On fail goto*//*Label 3834*/ GIMT_Encode4(246786), // Rule ID 441 //
          GIM_CheckFeatures, GIMT_Encode2(GIFBS_Has16BitInsts_NotHasTrue16BitInsts),
          // MIs[0] Operand 1
          GIM_CheckCmpPredicate, /*MI*/0, /*Op*/1, /*Predicate*/GIMT_Encode2(CmpInst::ICMP_EQ),
          // (setcc:{ *:[i1] } i16:{ *:[i16] }:$src0, i16:{ *:[i16] }:$src1, SETEQ:{ *:[Other] })  =>  (V_CMP_EQ_U16_e64:{ *:[i1] } i16:{ *:[i16] }:$src0, i16:{ *:[i16] }:$src1)
          GIR_BuildMI, /*InsnID*/0, /*Opcode*/GIMT_Encode2(AMDGPU::V_CMP_EQ_U16_e64),
          GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/0, // DstI[sdst]
          GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/2, // src0
          GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/3, // src1
          GIR_ConstrainSelectedInstOperands, /*InsnID*/0,
          GIR_EraseFromParent, /*InsnID*/0,
          // GIR_Coverage, 441,
          GIR_Done,
        // Label 3834: @246786
        GIM_Try, /*On fail goto*//*Label 3835*/ GIMT_Encode4(246820), // Rule ID 443 //
          GIM_CheckFeatures, GIMT_Encode2(GIFBS_Has16BitInsts_HasTrue16BitInsts),
          // MIs[0] Operand 1
          GIM_CheckCmpPredicate, /*MI*/0, /*Op*/1, /*Predicate*/GIMT_Encode2(CmpInst::ICMP_EQ),
          // (setcc:{ *:[i1] } i16:{ *:[i16] }:$src0, i16:{ *:[i16] }:$src1, SETEQ:{ *:[Other] })  =>  (V_CMP_EQ_U16_t16_e64:{ *:[i1] } i16:{ *:[i16] }:$src0, i16:{ *:[i16] }:$src1)
          GIR_BuildMI, /*InsnID*/0, /*Opcode*/GIMT_Encode2(AMDGPU::V_CMP_EQ_U16_t16_e64),
          GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/0, // DstI[sdst]
          GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/2, // src0
          GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/3, // src1
          GIR_ConstrainSelectedInstOperands, /*InsnID*/0,
          GIR_EraseFromParent, /*InsnID*/0,
          // GIR_Coverage, 443,
          GIR_Done,
        // Label 3835: @246820
        GIM_Try, /*On fail goto*//*Label 3836*/ GIMT_Encode4(246854), // Rule ID 445 //
          GIM_CheckFeatures, GIMT_Encode2(GIFBS_Has16BitInsts_NotHasTrue16BitInsts),
          // MIs[0] Operand 1
          GIM_CheckCmpPredicate, /*MI*/0, /*Op*/1, /*Predicate*/GIMT_Encode2(CmpInst::ICMP_ULE),
          // (setcc:{ *:[i1] } i16:{ *:[i16] }:$src0, i16:{ *:[i16] }:$src1, SETULE:{ *:[Other] })  =>  (V_CMP_LE_U16_e64:{ *:[i1] } i16:{ *:[i16] }:$src0, i16:{ *:[i16] }:$src1)
          GIR_BuildMI, /*InsnID*/0, /*Opcode*/GIMT_Encode2(AMDGPU::V_CMP_LE_U16_e64),
          GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/0, // DstI[sdst]
          GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/2, // src0
          GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/3, // src1
          GIR_ConstrainSelectedInstOperands, /*InsnID*/0,
          GIR_EraseFromParent, /*InsnID*/0,
          // GIR_Coverage, 445,
          GIR_Done,
        // Label 3836: @246854
        GIM_Try, /*On fail goto*//*Label 3837*/ GIMT_Encode4(246888), // Rule ID 446 //
          GIM_CheckFeatures, GIMT_Encode2(GIFBS_Has16BitInsts_HasTrue16BitInsts),
          // MIs[0] Operand 1
          GIM_CheckCmpPredicate, /*MI*/0, /*Op*/1, /*Predicate*/GIMT_Encode2(CmpInst::ICMP_ULE),
          // (setcc:{ *:[i1] } i16:{ *:[i16] }:$src0, i16:{ *:[i16] }:$src1, SETULE:{ *:[Other] })  =>  (V_CMP_LE_U16_t16_e64:{ *:[i1] } i16:{ *:[i16] }:$src0, i16:{ *:[i16] }:$src1)
          GIR_BuildMI, /*InsnID*/0, /*Opcode*/GIMT_Encode2(AMDGPU::V_CMP_LE_U16_t16_e64),
          GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/0, // DstI[sdst]
          GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/2, // src0
          GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/3, // src1
          GIR_ConstrainSelectedInstOperands, /*InsnID*/0,
          GIR_EraseFromParent, /*InsnID*/0,
          // GIR_Coverage, 446,
          GIR_Done,
        // Label 3837: @246888
        GIM_Try, /*On fail goto*//*Label 3838*/ GIMT_Encode4(246922), // Rule ID 447 //
          GIM_CheckFeatures, GIMT_Encode2(GIFBS_Has16BitInsts_NotHasTrue16BitInsts),
          // MIs[0] Operand 1
          GIM_CheckCmpPredicate, /*MI*/0, /*Op*/1, /*Predicate*/GIMT_Encode2(CmpInst::ICMP_UGT),
          // (setcc:{ *:[i1] } i16:{ *:[i16] }:$src0, i16:{ *:[i16] }:$src1, SETUGT:{ *:[Other] })  =>  (V_CMP_GT_U16_e64:{ *:[i1] } i16:{ *:[i16] }:$src0, i16:{ *:[i16] }:$src1)
          GIR_BuildMI, /*InsnID*/0, /*Opcode*/GIMT_Encode2(AMDGPU::V_CMP_GT_U16_e64),
          GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/0, // DstI[sdst]
          GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/2, // src0
          GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/3, // src1
          GIR_ConstrainSelectedInstOperands, /*InsnID*/0,
          GIR_EraseFromParent, /*InsnID*/0,
          // GIR_Coverage, 447,
          GIR_Done,
        // Label 3838: @246922
        GIM_Try, /*On fail goto*//*Label 3839*/ GIMT_Encode4(246956), // Rule ID 448 //
          GIM_CheckFeatures, GIMT_Encode2(GIFBS_Has16BitInsts_HasTrue16BitInsts),
          // MIs[0] Operand 1
          GIM_CheckCmpPredicate, /*MI*/0, /*Op*/1, /*Predicate*/GIMT_Encode2(CmpInst::ICMP_UGT),
          // (setcc:{ *:[i1] } i16:{ *:[i16] }:$src0, i16:{ *:[i16] }:$src1, SETUGT:{ *:[Other] })  =>  (V_CMP_GT_U16_t16_e64:{ *:[i1] } i16:{ *:[i16] }:$src0, i16:{ *:[i16] }:$src1)
          GIR_BuildMI, /*InsnID*/0, /*Opcode*/GIMT_Encode2(AMDGPU::V_CMP_GT_U16_t16_e64),
          GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/0, // DstI[sdst]
          GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/2, // src0
          GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/3, // src1
          GIR_ConstrainSelectedInstOperands, /*InsnID*/0,
          GIR_EraseFromParent, /*InsnID*/0,
          // GIR_Coverage, 448,
          GIR_Done,
        // Label 3839: @246956
        GIM_Try, /*On fail goto*//*Label 3840*/ GIMT_Encode4(246990), // Rule ID 449 //
          GIM_CheckFeatures, GIMT_Encode2(GIFBS_Has16BitInsts_NotHasTrue16BitInsts),
          // MIs[0] Operand 1
          GIM_CheckCmpPredicate, /*MI*/0, /*Op*/1, /*Predicate*/GIMT_Encode2(CmpInst::ICMP_NE),
          // (setcc:{ *:[i1] } i16:{ *:[i16] }:$src0, i16:{ *:[i16] }:$src1, SETNE:{ *:[Other] })  =>  (V_CMP_NE_U16_e64:{ *:[i1] } i16:{ *:[i16] }:$src0, i16:{ *:[i16] }:$src1)
          GIR_BuildMI, /*InsnID*/0, /*Opcode*/GIMT_Encode2(AMDGPU::V_CMP_NE_U16_e64),
          GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/0, // DstI[sdst]
          GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/2, // src0
          GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/3, // src1
          GIR_ConstrainSelectedInstOperands, /*InsnID*/0,
          GIR_EraseFromParent, /*InsnID*/0,
          // GIR_Coverage, 449,
          GIR_Done,
        // Label 3840: @246990
        GIM_Try, /*On fail goto*//*Label 3841*/ GIMT_Encode4(247024), // Rule ID 451 //
          GIM_CheckFeatures, GIMT_Encode2(GIFBS_Has16BitInsts_HasTrue16BitInsts),
          // MIs[0] Operand 1
          GIM_CheckCmpPredicate, /*MI*/0, /*Op*/1, /*Predicate*/GIMT_Encode2(CmpInst::ICMP_NE),
          // (setcc:{ *:[i1] } i16:{ *:[i16] }:$src0, i16:{ *:[i16] }:$src1, SETNE:{ *:[Other] })  =>  (V_CMP_NE_U16_t16_e64:{ *:[i1] } i16:{ *:[i16] }:$src0, i16:{ *:[i16] }:$src1)
          GIR_BuildMI, /*InsnID*/0, /*Opcode*/GIMT_Encode2(AMDGPU::V_CMP_NE_U16_t16_e64),
          GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/0, // DstI[sdst]
          GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/2, // src0
          GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/3, // src1
          GIR_ConstrainSelectedInstOperands, /*InsnID*/0,
          GIR_EraseFromParent, /*InsnID*/0,
          // GIR_Coverage, 451,
          GIR_Done,
        // Label 3841: @247024
        GIM_Try, /*On fail goto*//*Label 3842*/ GIMT_Encode4(247058), // Rule ID 453 //
          GIM_CheckFeatures, GIMT_Encode2(GIFBS_Has16BitInsts_NotHasTrue16BitInsts),
          // MIs[0] Operand 1
          GIM_CheckCmpPredicate, /*MI*/0, /*Op*/1, /*Predicate*/GIMT_Encode2(CmpInst::ICMP_UGE),
          // (setcc:{ *:[i1] } i16:{ *:[i16] }:$src0, i16:{ *:[i16] }:$src1, SETUGE:{ *:[Other] })  =>  (V_CMP_GE_U16_e64:{ *:[i1] } i16:{ *:[i16] }:$src0, i16:{ *:[i16] }:$src1)
          GIR_BuildMI, /*InsnID*/0, /*Opcode*/GIMT_Encode2(AMDGPU::V_CMP_GE_U16_e64),
          GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/0, // DstI[sdst]
          GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/2, // src0
          GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/3, // src1
          GIR_ConstrainSelectedInstOperands, /*InsnID*/0,
          GIR_EraseFromParent, /*InsnID*/0,
          // GIR_Coverage, 453,
          GIR_Done,
        // Label 3842: @247058
        GIM_Try, /*On fail goto*//*Label 3843*/ GIMT_Encode4(247092), // Rule ID 454 //
          GIM_CheckFeatures, GIMT_Encode2(GIFBS_Has16BitInsts_HasTrue16BitInsts),
          // MIs[0] Operand 1
          GIM_CheckCmpPredicate, /*MI*/0, /*Op*/1, /*Predicate*/GIMT_Encode2(CmpInst::ICMP_UGE),
          // (setcc:{ *:[i1] } i16:{ *:[i16] }:$src0, i16:{ *:[i16] }:$src1, SETUGE:{ *:[Other] })  =>  (V_CMP_GE_U16_t16_e64:{ *:[i1] } i16:{ *:[i16] }:$src0, i16:{ *:[i16] }:$src1)
          GIR_BuildMI, /*InsnID*/0, /*Opcode*/GIMT_Encode2(AMDGPU::V_CMP_GE_U16_t16_e64),
          GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/0, // DstI[sdst]
          GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/2, // src0
          GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/3, // src1
          GIR_ConstrainSelectedInstOperands, /*InsnID*/0,
          GIR_EraseFromParent, /*InsnID*/0,
          // GIR_Coverage, 454,
          GIR_Done,
        // Label 3843: @247092
        GIM_Reject,
      // Label 3823: @247093
      GIM_Reject,
      // Label 3820: @247094
      GIM_Try, /*On fail goto*//*Label 3844*/ GIMT_Encode4(247233),
        GIM_CheckType, /*MI*/0, /*Op*/3, /*Type*/GILLT_s32,
        GIM_CheckRegBankForClass, /*MI*/0, /*Op*/0, /*RC*/GIMT_Encode2(AMDGPU::SReg_1RegClassID),
        GIM_Try, /*On fail goto*//*Label 3845*/ GIMT_Encode4(247139), // Rule ID 490 //
          // MIs[0] Operand 1
          GIM_CheckCmpPredicate, /*MI*/0, /*Op*/1, /*Predicate*/GIMT_Encode2(CmpInst::ICMP_SLT),
          // (setcc:{ *:[i1] } i32:{ *:[i32] }:$src0, i32:{ *:[i32] }:$src1, SETLT:{ *:[Other] })  =>  (V_CMP_LT_I32_e64:{ *:[i1] } i32:{ *:[i32] }:$src0, i32:{ *:[i32] }:$src1)
          GIR_BuildMI, /*InsnID*/0, /*Opcode*/GIMT_Encode2(AMDGPU::V_CMP_LT_I32_e64),
          GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/0, // DstI[sdst]
          GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/2, // src0
          GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/3, // src1
          GIR_ConstrainSelectedInstOperands, /*InsnID*/0,
          GIR_EraseFromParent, /*InsnID*/0,
          // GIR_Coverage, 490,
          GIR_Done,
        // Label 3845: @247139
        GIM_Try, /*On fail goto*//*Label 3846*/ GIMT_Encode4(247170), // Rule ID 492 //
          // MIs[0] Operand 1
          GIM_CheckCmpPredicate, /*MI*/0, /*Op*/1, /*Predicate*/GIMT_Encode2(CmpInst::ICMP_SLE),
          // (setcc:{ *:[i1] } i32:{ *:[i32] }:$src0, i32:{ *:[i32] }:$src1, SETLE:{ *:[Other] })  =>  (V_CMP_LE_I32_e64:{ *:[i1] } i32:{ *:[i32] }:$src0, i32:{ *:[i32] }:$src1)
          GIR_BuildMI, /*InsnID*/0, /*Opcode*/GIMT_Encode2(AMDGPU::V_CMP_LE_I32_e64),
          GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/0, // DstI[sdst]
          GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/2, // src0
          GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/3, // src1
          GIR_ConstrainSelectedInstOperands, /*InsnID*/0,
          GIR_EraseFromParent, /*InsnID*/0,
          // GIR_Coverage, 492,
          GIR_Done,
        // Label 3846: @247170
        GIM_Try, /*On fail goto*//*Label 3847*/ GIMT_Encode4(247201), // Rule ID 493 //
          // MIs[0] Operand 1
          GIM_CheckCmpPredicate, /*MI*/0, /*Op*/1, /*Predicate*/GIMT_Encode2(CmpInst::ICMP_SGT),
          // (setcc:{ *:[i1] } i32:{ *:[i32] }:$src0, i32:{ *:[i32] }:$src1, SETGT:{ *:[Other] })  =>  (V_CMP_GT_I32_e64:{ *:[i1] } i32:{ *:[i32] }:$src0, i32:{ *:[i32] }:$src1)
          GIR_BuildMI, /*InsnID*/0, /*Opcode*/GIMT_Encode2(AMDGPU::V_CMP_GT_I32_e64),
          GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/0, // DstI[sdst]
          GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/2, // src0
          GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/3, // src1
          GIR_ConstrainSelectedInstOperands, /*InsnID*/0,
          GIR_EraseFromParent, /*InsnID*/0,
          // GIR_Coverage, 493,
          GIR_Done,
        // Label 3847: @247201
        GIM_Try, /*On fail goto*//*Label 3848*/ GIMT_Encode4(247232), // Rule ID 495 //
          // MIs[0] Operand 1
          GIM_CheckCmpPredicate, /*MI*/0, /*Op*/1, /*Predicate*/GIMT_Encode2(CmpInst::ICMP_SGE),
          // (setcc:{ *:[i1] } i32:{ *:[i32] }:$src0, i32:{ *:[i32] }:$src1, SETGE:{ *:[Other] })  =>  (V_CMP_GE_I32_e64:{ *:[i1] } i32:{ *:[i32] }:$src0, i32:{ *:[i32] }:$src1)
          GIR_BuildMI, /*InsnID*/0, /*Opcode*/GIMT_Encode2(AMDGPU::V_CMP_GE_I32_e64),
          GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/0, // DstI[sdst]
          GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/2, // src0
          GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/3, // src1
          GIR_ConstrainSelectedInstOperands, /*InsnID*/0,
          GIR_EraseFromParent, /*InsnID*/0,
          // GIR_Coverage, 495,
          GIR_Done,
        // Label 3848: @247232
        GIM_Reject,
      // Label 3844: @247233
      GIM_Reject,
      // Label 3821: @247234
      GIM_Try, /*On fail goto*//*Label 3849*/ GIMT_Encode4(247373),
        GIM_CheckType, /*MI*/0, /*Op*/3, /*Type*/GILLT_s64,
        GIM_CheckRegBankForClass, /*MI*/0, /*Op*/0, /*RC*/GIMT_Encode2(AMDGPU::SReg_1RegClassID),
        GIM_Try, /*On fail goto*//*Label 3850*/ GIMT_Encode4(247279), // Rule ID 506 //
          // MIs[0] Operand 1
          GIM_CheckCmpPredicate, /*MI*/0, /*Op*/1, /*Predicate*/GIMT_Encode2(CmpInst::ICMP_SLT),
          // (setcc:{ *:[i1] } i64:{ *:[i64] }:$src0, i64:{ *:[i64] }:$src1, SETLT:{ *:[Other] })  =>  (V_CMP_LT_I64_e64:{ *:[i1] } i64:{ *:[i64] }:$src0, i64:{ *:[i64] }:$src1)
          GIR_BuildMI, /*InsnID*/0, /*Opcode*/GIMT_Encode2(AMDGPU::V_CMP_LT_I64_e64),
          GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/0, // DstI[sdst]
          GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/2, // src0
          GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/3, // src1
          GIR_ConstrainSelectedInstOperands, /*InsnID*/0,
          GIR_EraseFromParent, /*InsnID*/0,
          // GIR_Coverage, 506,
          GIR_Done,
        // Label 3850: @247279
        GIM_Try, /*On fail goto*//*Label 3851*/ GIMT_Encode4(247310), // Rule ID 508 //
          // MIs[0] Operand 1
          GIM_CheckCmpPredicate, /*MI*/0, /*Op*/1, /*Predicate*/GIMT_Encode2(CmpInst::ICMP_SLE),
          // (setcc:{ *:[i1] } i64:{ *:[i64] }:$src0, i64:{ *:[i64] }:$src1, SETLE:{ *:[Other] })  =>  (V_CMP_LE_I64_e64:{ *:[i1] } i64:{ *:[i64] }:$src0, i64:{ *:[i64] }:$src1)
          GIR_BuildMI, /*InsnID*/0, /*Opcode*/GIMT_Encode2(AMDGPU::V_CMP_LE_I64_e64),
          GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/0, // DstI[sdst]
          GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/2, // src0
          GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/3, // src1
          GIR_ConstrainSelectedInstOperands, /*InsnID*/0,
          GIR_EraseFromParent, /*InsnID*/0,
          // GIR_Coverage, 508,
          GIR_Done,
        // Label 3851: @247310
        GIM_Try, /*On fail goto*//*Label 3852*/ GIMT_Encode4(247341), // Rule ID 509 //
          // MIs[0] Operand 1
          GIM_CheckCmpPredicate, /*MI*/0, /*Op*/1, /*Predicate*/GIMT_Encode2(CmpInst::ICMP_SGT),
          // (setcc:{ *:[i1] } i64:{ *:[i64] }:$src0, i64:{ *:[i64] }:$src1, SETGT:{ *:[Other] })  =>  (V_CMP_GT_I64_e64:{ *:[i1] } i64:{ *:[i64] }:$src0, i64:{ *:[i64] }:$src1)
          GIR_BuildMI, /*InsnID*/0, /*Opcode*/GIMT_Encode2(AMDGPU::V_CMP_GT_I64_e64),
          GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/0, // DstI[sdst]
          GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/2, // src0
          GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/3, // src1
          GIR_ConstrainSelectedInstOperands, /*InsnID*/0,
          GIR_EraseFromParent, /*InsnID*/0,
          // GIR_Coverage, 509,
          GIR_Done,
        // Label 3852: @247341
        GIM_Try, /*On fail goto*//*Label 3853*/ GIMT_Encode4(247372), // Rule ID 511 //
          // MIs[0] Operand 1
          GIM_CheckCmpPredicate, /*MI*/0, /*Op*/1, /*Predicate*/GIMT_Encode2(CmpInst::ICMP_SGE),
          // (setcc:{ *:[i1] } i64:{ *:[i64] }:$src0, i64:{ *:[i64] }:$src1, SETGE:{ *:[Other] })  =>  (V_CMP_GE_I64_e64:{ *:[i1] } i64:{ *:[i64] }:$src0, i64:{ *:[i64] }:$src1)
          GIR_BuildMI, /*InsnID*/0, /*Opcode*/GIMT_Encode2(AMDGPU::V_CMP_GE_I64_e64),
          GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/0, // DstI[sdst]
          GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/2, // src0
          GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/3, // src1
          GIR_ConstrainSelectedInstOperands, /*InsnID*/0,
          GIR_EraseFromParent, /*InsnID*/0,
          // GIR_Coverage, 511,
          GIR_Done,
        // Label 3853: @247372
        GIM_Reject,
      // Label 3849: @247373
      GIM_Reject,
      // Label 3822: @247374
      GIM_SwitchType, /*MI*/0, /*Op*/2, /*[*/GIMT_Encode2(9), GIMT_Encode2(11), /*)*//*default:*//*Label 3856*/ GIMT_Encode4(247797),
      /*GILLT_s32*//*Label 3854*/ GIMT_Encode4(247393),
      /*GILLT_s64*//*Label 3855*/ GIMT_Encode4(247595),
      // Label 3854: @247393
      GIM_Try, /*On fail goto*//*Label 3857*/ GIMT_Encode4(247594),
        GIM_CheckType, /*MI*/0, /*Op*/3, /*Type*/GILLT_s32,
        GIM_CheckRegBankForClass, /*MI*/0, /*Op*/0, /*RC*/GIMT_Encode2(AMDGPU::SReg_1RegClassID),
        GIM_Try, /*On fail goto*//*Label 3858*/ GIMT_Encode4(247438), // Rule ID 522 //
          // MIs[0] Operand 1
          GIM_CheckCmpPredicate, /*MI*/0, /*Op*/1, /*Predicate*/GIMT_Encode2(CmpInst::ICMP_ULT),
          // (setcc:{ *:[i1] } i32:{ *:[i32] }:$src0, i32:{ *:[i32] }:$src1, SETULT:{ *:[Other] })  =>  (V_CMP_LT_U32_e64:{ *:[i1] } i32:{ *:[i32] }:$src0, i32:{ *:[i32] }:$src1)
          GIR_BuildMI, /*InsnID*/0, /*Opcode*/GIMT_Encode2(AMDGPU::V_CMP_LT_U32_e64),
          GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/0, // DstI[sdst]
          GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/2, // src0
          GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/3, // src1
          GIR_ConstrainSelectedInstOperands, /*InsnID*/0,
          GIR_EraseFromParent, /*InsnID*/0,
          // GIR_Coverage, 522,
          GIR_Done,
        // Label 3858: @247438
        GIM_Try, /*On fail goto*//*Label 3859*/ GIMT_Encode4(247469), // Rule ID 523 //
          // MIs[0] Operand 1
          GIM_CheckCmpPredicate, /*MI*/0, /*Op*/1, /*Predicate*/GIMT_Encode2(CmpInst::ICMP_EQ),
          // (setcc:{ *:[i1] } i32:{ *:[i32] }:$src0, i32:{ *:[i32] }:$src1, SETEQ:{ *:[Other] })  =>  (V_CMP_EQ_U32_e64:{ *:[i1] } i32:{ *:[i32] }:$src0, i32:{ *:[i32] }:$src1)
          GIR_BuildMI, /*InsnID*/0, /*Opcode*/GIMT_Encode2(AMDGPU::V_CMP_EQ_U32_e64),
          GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/0, // DstI[sdst]
          GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/2, // src0
          GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/3, // src1
          GIR_ConstrainSelectedInstOperands, /*InsnID*/0,
          GIR_EraseFromParent, /*InsnID*/0,
          // GIR_Coverage, 523,
          GIR_Done,
        // Label 3859: @247469
        GIM_Try, /*On fail goto*//*Label 3860*/ GIMT_Encode4(247500), // Rule ID 525 //
          // MIs[0] Operand 1
          GIM_CheckCmpPredicate, /*MI*/0, /*Op*/1, /*Predicate*/GIMT_Encode2(CmpInst::ICMP_ULE),
          // (setcc:{ *:[i1] } i32:{ *:[i32] }:$src0, i32:{ *:[i32] }:$src1, SETULE:{ *:[Other] })  =>  (V_CMP_LE_U32_e64:{ *:[i1] } i32:{ *:[i32] }:$src0, i32:{ *:[i32] }:$src1)
          GIR_BuildMI, /*InsnID*/0, /*Opcode*/GIMT_Encode2(AMDGPU::V_CMP_LE_U32_e64),
          GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/0, // DstI[sdst]
          GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/2, // src0
          GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/3, // src1
          GIR_ConstrainSelectedInstOperands, /*InsnID*/0,
          GIR_EraseFromParent, /*InsnID*/0,
          // GIR_Coverage, 525,
          GIR_Done,
        // Label 3860: @247500
        GIM_Try, /*On fail goto*//*Label 3861*/ GIMT_Encode4(247531), // Rule ID 526 //
          // MIs[0] Operand 1
          GIM_CheckCmpPredicate, /*MI*/0, /*Op*/1, /*Predicate*/GIMT_Encode2(CmpInst::ICMP_UGT),
          // (setcc:{ *:[i1] } i32:{ *:[i32] }:$src0, i32:{ *:[i32] }:$src1, SETUGT:{ *:[Other] })  =>  (V_CMP_GT_U32_e64:{ *:[i1] } i32:{ *:[i32] }:$src0, i32:{ *:[i32] }:$src1)
          GIR_BuildMI, /*InsnID*/0, /*Opcode*/GIMT_Encode2(AMDGPU::V_CMP_GT_U32_e64),
          GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/0, // DstI[sdst]
          GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/2, // src0
          GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/3, // src1
          GIR_ConstrainSelectedInstOperands, /*InsnID*/0,
          GIR_EraseFromParent, /*InsnID*/0,
          // GIR_Coverage, 526,
          GIR_Done,
        // Label 3861: @247531
        GIM_Try, /*On fail goto*//*Label 3862*/ GIMT_Encode4(247562), // Rule ID 527 //
          // MIs[0] Operand 1
          GIM_CheckCmpPredicate, /*MI*/0, /*Op*/1, /*Predicate*/GIMT_Encode2(CmpInst::ICMP_NE),
          // (setcc:{ *:[i1] } i32:{ *:[i32] }:$src0, i32:{ *:[i32] }:$src1, SETNE:{ *:[Other] })  =>  (V_CMP_NE_U32_e64:{ *:[i1] } i32:{ *:[i32] }:$src0, i32:{ *:[i32] }:$src1)
          GIR_BuildMI, /*InsnID*/0, /*Opcode*/GIMT_Encode2(AMDGPU::V_CMP_NE_U32_e64),
          GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/0, // DstI[sdst]
          GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/2, // src0
          GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/3, // src1
          GIR_ConstrainSelectedInstOperands, /*InsnID*/0,
          GIR_EraseFromParent, /*InsnID*/0,
          // GIR_Coverage, 527,
          GIR_Done,
        // Label 3862: @247562
        GIM_Try, /*On fail goto*//*Label 3863*/ GIMT_Encode4(247593), // Rule ID 529 //
          // MIs[0] Operand 1
          GIM_CheckCmpPredicate, /*MI*/0, /*Op*/1, /*Predicate*/GIMT_Encode2(CmpInst::ICMP_UGE),
          // (setcc:{ *:[i1] } i32:{ *:[i32] }:$src0, i32:{ *:[i32] }:$src1, SETUGE:{ *:[Other] })  =>  (V_CMP_GE_U32_e64:{ *:[i1] } i32:{ *:[i32] }:$src0, i32:{ *:[i32] }:$src1)
          GIR_BuildMI, /*InsnID*/0, /*Opcode*/GIMT_Encode2(AMDGPU::V_CMP_GE_U32_e64),
          GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/0, // DstI[sdst]
          GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/2, // src0
          GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/3, // src1
          GIR_ConstrainSelectedInstOperands, /*InsnID*/0,
          GIR_EraseFromParent, /*InsnID*/0,
          // GIR_Coverage, 529,
          GIR_Done,
        // Label 3863: @247593
        GIM_Reject,
      // Label 3857: @247594
      GIM_Reject,
      // Label 3855: @247595
      GIM_Try, /*On fail goto*//*Label 3864*/ GIMT_Encode4(247796),
        GIM_CheckType, /*MI*/0, /*Op*/3, /*Type*/GILLT_s64,
        GIM_CheckRegBankForClass, /*MI*/0, /*Op*/0, /*RC*/GIMT_Encode2(AMDGPU::SReg_1RegClassID),
        GIM_Try, /*On fail goto*//*Label 3865*/ GIMT_Encode4(247640), // Rule ID 540 //
          // MIs[0] Operand 1
          GIM_CheckCmpPredicate, /*MI*/0, /*Op*/1, /*Predicate*/GIMT_Encode2(CmpInst::ICMP_ULT),
          // (setcc:{ *:[i1] } i64:{ *:[i64] }:$src0, i64:{ *:[i64] }:$src1, SETULT:{ *:[Other] })  =>  (V_CMP_LT_U64_e64:{ *:[i1] } i64:{ *:[i64] }:$src0, i64:{ *:[i64] }:$src1)
          GIR_BuildMI, /*InsnID*/0, /*Opcode*/GIMT_Encode2(AMDGPU::V_CMP_LT_U64_e64),
          GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/0, // DstI[sdst]
          GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/2, // src0
          GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/3, // src1
          GIR_ConstrainSelectedInstOperands, /*InsnID*/0,
          GIR_EraseFromParent, /*InsnID*/0,
          // GIR_Coverage, 540,
          GIR_Done,
        // Label 3865: @247640
        GIM_Try, /*On fail goto*//*Label 3866*/ GIMT_Encode4(247671), // Rule ID 541 //
          // MIs[0] Operand 1
          GIM_CheckCmpPredicate, /*MI*/0, /*Op*/1, /*Predicate*/GIMT_Encode2(CmpInst::ICMP_EQ),
          // (setcc:{ *:[i1] } i64:{ *:[i64] }:$src0, i64:{ *:[i64] }:$src1, SETEQ:{ *:[Other] })  =>  (V_CMP_EQ_U64_e64:{ *:[i1] } i64:{ *:[i64] }:$src0, i64:{ *:[i64] }:$src1)
          GIR_BuildMI, /*InsnID*/0, /*Opcode*/GIMT_Encode2(AMDGPU::V_CMP_EQ_U64_e64),
          GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/0, // DstI[sdst]
          GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/2, // src0
          GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/3, // src1
          GIR_ConstrainSelectedInstOperands, /*InsnID*/0,
          GIR_EraseFromParent, /*InsnID*/0,
          // GIR_Coverage, 541,
          GIR_Done,
        // Label 3866: @247671
        GIM_Try, /*On fail goto*//*Label 3867*/ GIMT_Encode4(247702), // Rule ID 543 //
          // MIs[0] Operand 1
          GIM_CheckCmpPredicate, /*MI*/0, /*Op*/1, /*Predicate*/GIMT_Encode2(CmpInst::ICMP_ULE),
          // (setcc:{ *:[i1] } i64:{ *:[i64] }:$src0, i64:{ *:[i64] }:$src1, SETULE:{ *:[Other] })  =>  (V_CMP_LE_U64_e64:{ *:[i1] } i64:{ *:[i64] }:$src0, i64:{ *:[i64] }:$src1)
          GIR_BuildMI, /*InsnID*/0, /*Opcode*/GIMT_Encode2(AMDGPU::V_CMP_LE_U64_e64),
          GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/0, // DstI[sdst]
          GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/2, // src0
          GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/3, // src1
          GIR_ConstrainSelectedInstOperands, /*InsnID*/0,
          GIR_EraseFromParent, /*InsnID*/0,
          // GIR_Coverage, 543,
          GIR_Done,
        // Label 3867: @247702
        GIM_Try, /*On fail goto*//*Label 3868*/ GIMT_Encode4(247733), // Rule ID 544 //
          // MIs[0] Operand 1
          GIM_CheckCmpPredicate, /*MI*/0, /*Op*/1, /*Predicate*/GIMT_Encode2(CmpInst::ICMP_UGT),
          // (setcc:{ *:[i1] } i64:{ *:[i64] }:$src0, i64:{ *:[i64] }:$src1, SETUGT:{ *:[Other] })  =>  (V_CMP_GT_U64_e64:{ *:[i1] } i64:{ *:[i64] }:$src0, i64:{ *:[i64] }:$src1)
          GIR_BuildMI, /*InsnID*/0, /*Opcode*/GIMT_Encode2(AMDGPU::V_CMP_GT_U64_e64),
          GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/0, // DstI[sdst]
          GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/2, // src0
          GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/3, // src1
          GIR_ConstrainSelectedInstOperands, /*InsnID*/0,
          GIR_EraseFromParent, /*InsnID*/0,
          // GIR_Coverage, 544,
          GIR_Done,
        // Label 3868: @247733
        GIM_Try, /*On fail goto*//*Label 3869*/ GIMT_Encode4(247764), // Rule ID 545 //
          // MIs[0] Operand 1
          GIM_CheckCmpPredicate, /*MI*/0, /*Op*/1, /*Predicate*/GIMT_Encode2(CmpInst::ICMP_NE),
          // (setcc:{ *:[i1] } i64:{ *:[i64] }:$src0, i64:{ *:[i64] }:$src1, SETNE:{ *:[Other] })  =>  (V_CMP_NE_U64_e64:{ *:[i1] } i64:{ *:[i64] }:$src0, i64:{ *:[i64] }:$src1)
          GIR_BuildMI, /*InsnID*/0, /*Opcode*/GIMT_Encode2(AMDGPU::V_CMP_NE_U64_e64),
          GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/0, // DstI[sdst]
          GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/2, // src0
          GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/3, // src1
          GIR_ConstrainSelectedInstOperands, /*InsnID*/0,
          GIR_EraseFromParent, /*InsnID*/0,
          // GIR_Coverage, 545,
          GIR_Done,
        // Label 3869: @247764
        GIM_Try, /*On fail goto*//*Label 3870*/ GIMT_Encode4(247795), // Rule ID 547 //
          // MIs[0] Operand 1
          GIM_CheckCmpPredicate, /*MI*/0, /*Op*/1, /*Predicate*/GIMT_Encode2(CmpInst::ICMP_UGE),
          // (setcc:{ *:[i1] } i64:{ *:[i64] }:$src0, i64:{ *:[i64] }:$src1, SETUGE:{ *:[Other] })  =>  (V_CMP_GE_U64_e64:{ *:[i1] } i64:{ *:[i64] }:$src0, i64:{ *:[i64] }:$src1)
          GIR_BuildMI, /*InsnID*/0, /*Opcode*/GIMT_Encode2(AMDGPU::V_CMP_GE_U64_e64),
          GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/0, // DstI[sdst]
          GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/2, // src0
          GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/3, // src1
          GIR_ConstrainSelectedInstOperands, /*InsnID*/0,
          GIR_EraseFromParent, /*InsnID*/0,
          // GIR_Coverage, 547,
          GIR_Done,
        // Label 3870: @247795
        GIM_Reject,
      // Label 3864: @247796
      GIM_Reject,
      // Label 3856: @247797
      GIM_Reject,
    // Label 3818: @247798
    GIM_Reject,
    // Label 48: @247799
    GIM_Try, /*On fail goto*//*Label 3871*/ GIMT_Encode4(251436),
      GIM_CheckType, /*MI*/0, /*Op*/0, /*Type*/GILLT_s1,
      GIM_SwitchType, /*MI*/0, /*Op*/2, /*[*/GIMT_Encode2(8), GIMT_Encode2(11), /*)*//*default:*//*Label 3875*/ GIMT_Encode4(251435),
      /*GILLT_s16*//*Label 3872*/ GIMT_Encode4(247831),
      /*GILLT_s32*//*Label 3873*/ GIMT_Encode4(249667),
      /*GILLT_s64*//*Label 3874*/ GIMT_Encode4(250551),
      // Label 3872: @247831
      GIM_Try, /*On fail goto*//*Label 3876*/ GIMT_Encode4(249666),
        GIM_CheckType, /*MI*/0, /*Op*/3, /*Type*/GILLT_s16,
        GIM_CheckRegBankForClass, /*MI*/0, /*Op*/0, /*RC*/GIMT_Encode2(AMDGPU::SReg_1RegClassID),
        GIM_Try, /*On fail goto*//*Label 3877*/ GIMT_Encode4(247910), // Rule ID 347 //
          GIM_CheckFeatures, GIMT_Encode2(GIFBS_Has16BitInsts_NotHasTrue16BitInsts),
          // MIs[0] Operand 1
          GIM_CheckCmpPredicate, /*MI*/0, /*Op*/1, /*Predicate*/GIMT_Encode2(CmpInst::FCMP_OLT),
          GIM_CheckComplexPattern, /*MI*/0, /*Op*/2, /*Renderer*/GIMT_Encode2(0), GIMT_Encode2(GICP_gi_vop3mods0),
          GIM_CheckComplexPattern, /*MI*/0, /*Op*/3, /*Renderer*/GIMT_Encode2(1), GIMT_Encode2(GICP_gi_vop3mods),
          // (setcc:{ *:[i1] } (VOP3Mods0:{ *:[f16] } f16:{ *:[f16] }:$src0, i32:{ *:[i32] }:$src0_modifiers, i1:{ *:[i1] }:$clamp), (VOP3Mods:{ *:[f16] } f16:{ *:[f16] }:$src1, i32:{ *:[i32] }:$src1_modifiers), SETOLT:{ *:[Other] })  =>  (V_CMP_LT_F16_e64:{ *:[i1] } i32:{ *:[i32] }:$src0_modifiers, f16:{ *:[f16] }:$src0, i32:{ *:[i32] }:$src1_modifiers, f16:{ *:[f16] }:$src1, i1:{ *:[i1] }:$clamp)
          GIR_BuildMI, /*InsnID*/0, /*Opcode*/GIMT_Encode2(AMDGPU::V_CMP_LT_F16_e64),
          GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/0, // DstI[sdst]
          GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/1, // src0_modifiers
          GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/0, // src0
          GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(1), /*SubOperand*/1, // src1_modifiers
          GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(1), /*SubOperand*/0, // src1
          GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/2, // clamp
          GIR_ConstrainSelectedInstOperands, /*InsnID*/0,
          GIR_EraseFromParent, /*InsnID*/0,
          // GIR_Coverage, 347,
          GIR_Done,
        // Label 3877: @247910
        GIM_Try, /*On fail goto*//*Label 3878*/ GIMT_Encode4(247975), // Rule ID 349 //
          GIM_CheckFeatures, GIMT_Encode2(GIFBS_Has16BitInsts_HasTrue16BitInsts),
          // MIs[0] Operand 1
          GIM_CheckCmpPredicate, /*MI*/0, /*Op*/1, /*Predicate*/GIMT_Encode2(CmpInst::FCMP_OLT),
          GIM_CheckComplexPattern, /*MI*/0, /*Op*/2, /*Renderer*/GIMT_Encode2(0), GIMT_Encode2(GICP_gi_vop3mods0),
          GIM_CheckComplexPattern, /*MI*/0, /*Op*/3, /*Renderer*/GIMT_Encode2(1), GIMT_Encode2(GICP_gi_vop3mods),
          // (setcc:{ *:[i1] } (VOP3Mods0:{ *:[f16] } f16:{ *:[f16] }:$src0, i32:{ *:[i32] }:$src0_modifiers, i1:{ *:[i1] }:$clamp), (VOP3Mods:{ *:[f16] } f16:{ *:[f16] }:$src1, i32:{ *:[i32] }:$src1_modifiers), SETOLT:{ *:[Other] })  =>  (V_CMP_LT_F16_t16_e64:{ *:[i1] } i32:{ *:[i32] }:$src0_modifiers, f16:{ *:[f16] }:$src0, i32:{ *:[i32] }:$src1_modifiers, f16:{ *:[f16] }:$src1, i1:{ *:[i1] }:$clamp)
          GIR_BuildMI, /*InsnID*/0, /*Opcode*/GIMT_Encode2(AMDGPU::V_CMP_LT_F16_t16_e64),
          GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/0, // DstI[sdst]
          GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/1, // src0_modifiers
          GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/0, // src0
          GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(1), /*SubOperand*/1, // src1_modifiers
          GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(1), /*SubOperand*/0, // src1
          GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/2, // clamp
          GIR_ConstrainSelectedInstOperands, /*InsnID*/0,
          GIR_EraseFromParent, /*InsnID*/0,
          // GIR_Coverage, 349,
          GIR_Done,
        // Label 3878: @247975
        GIM_Try, /*On fail goto*//*Label 3879*/ GIMT_Encode4(248040), // Rule ID 351 //
          GIM_CheckFeatures, GIMT_Encode2(GIFBS_Has16BitInsts_NotHasTrue16BitInsts),
          // MIs[0] Operand 1
          GIM_CheckCmpPredicate, /*MI*/0, /*Op*/1, /*Predicate*/GIMT_Encode2(CmpInst::FCMP_OEQ),
          GIM_CheckComplexPattern, /*MI*/0, /*Op*/2, /*Renderer*/GIMT_Encode2(0), GIMT_Encode2(GICP_gi_vop3mods0),
          GIM_CheckComplexPattern, /*MI*/0, /*Op*/3, /*Renderer*/GIMT_Encode2(1), GIMT_Encode2(GICP_gi_vop3mods),
          // (setcc:{ *:[i1] } (VOP3Mods0:{ *:[f16] } f16:{ *:[f16] }:$src0, i32:{ *:[i32] }:$src0_modifiers, i1:{ *:[i1] }:$clamp), (VOP3Mods:{ *:[f16] } f16:{ *:[f16] }:$src1, i32:{ *:[i32] }:$src1_modifiers), SETOEQ:{ *:[Other] })  =>  (V_CMP_EQ_F16_e64:{ *:[i1] } i32:{ *:[i32] }:$src0_modifiers, f16:{ *:[f16] }:$src0, i32:{ *:[i32] }:$src1_modifiers, f16:{ *:[f16] }:$src1, i1:{ *:[i1] }:$clamp)
          GIR_BuildMI, /*InsnID*/0, /*Opcode*/GIMT_Encode2(AMDGPU::V_CMP_EQ_F16_e64),
          GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/0, // DstI[sdst]
          GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/1, // src0_modifiers
          GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/0, // src0
          GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(1), /*SubOperand*/1, // src1_modifiers
          GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(1), /*SubOperand*/0, // src1
          GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/2, // clamp
          GIR_ConstrainSelectedInstOperands, /*InsnID*/0,
          GIR_EraseFromParent, /*InsnID*/0,
          // GIR_Coverage, 351,
          GIR_Done,
        // Label 3879: @248040
        GIM_Try, /*On fail goto*//*Label 3880*/ GIMT_Encode4(248105), // Rule ID 353 //
          GIM_CheckFeatures, GIMT_Encode2(GIFBS_Has16BitInsts_HasTrue16BitInsts),
          // MIs[0] Operand 1
          GIM_CheckCmpPredicate, /*MI*/0, /*Op*/1, /*Predicate*/GIMT_Encode2(CmpInst::FCMP_OEQ),
          GIM_CheckComplexPattern, /*MI*/0, /*Op*/2, /*Renderer*/GIMT_Encode2(0), GIMT_Encode2(GICP_gi_vop3mods0),
          GIM_CheckComplexPattern, /*MI*/0, /*Op*/3, /*Renderer*/GIMT_Encode2(1), GIMT_Encode2(GICP_gi_vop3mods),
          // (setcc:{ *:[i1] } (VOP3Mods0:{ *:[f16] } f16:{ *:[f16] }:$src0, i32:{ *:[i32] }:$src0_modifiers, i1:{ *:[i1] }:$clamp), (VOP3Mods:{ *:[f16] } f16:{ *:[f16] }:$src1, i32:{ *:[i32] }:$src1_modifiers), SETOEQ:{ *:[Other] })  =>  (V_CMP_EQ_F16_t16_e64:{ *:[i1] } i32:{ *:[i32] }:$src0_modifiers, f16:{ *:[f16] }:$src0, i32:{ *:[i32] }:$src1_modifiers, f16:{ *:[f16] }:$src1, i1:{ *:[i1] }:$clamp)
          GIR_BuildMI, /*InsnID*/0, /*Opcode*/GIMT_Encode2(AMDGPU::V_CMP_EQ_F16_t16_e64),
          GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/0, // DstI[sdst]
          GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/1, // src0_modifiers
          GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/0, // src0
          GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(1), /*SubOperand*/1, // src1_modifiers
          GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(1), /*SubOperand*/0, // src1
          GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/2, // clamp
          GIR_ConstrainSelectedInstOperands, /*InsnID*/0,
          GIR_EraseFromParent, /*InsnID*/0,
          // GIR_Coverage, 353,
          GIR_Done,
        // Label 3880: @248105
        GIM_Try, /*On fail goto*//*Label 3881*/ GIMT_Encode4(248170), // Rule ID 355 //
          GIM_CheckFeatures, GIMT_Encode2(GIFBS_Has16BitInsts_NotHasTrue16BitInsts),
          // MIs[0] Operand 1
          GIM_CheckCmpPredicate, /*MI*/0, /*Op*/1, /*Predicate*/GIMT_Encode2(CmpInst::FCMP_OLE),
          GIM_CheckComplexPattern, /*MI*/0, /*Op*/2, /*Renderer*/GIMT_Encode2(0), GIMT_Encode2(GICP_gi_vop3mods0),
          GIM_CheckComplexPattern, /*MI*/0, /*Op*/3, /*Renderer*/GIMT_Encode2(1), GIMT_Encode2(GICP_gi_vop3mods),
          // (setcc:{ *:[i1] } (VOP3Mods0:{ *:[f16] } f16:{ *:[f16] }:$src0, i32:{ *:[i32] }:$src0_modifiers, i1:{ *:[i1] }:$clamp), (VOP3Mods:{ *:[f16] } f16:{ *:[f16] }:$src1, i32:{ *:[i32] }:$src1_modifiers), SETOLE:{ *:[Other] })  =>  (V_CMP_LE_F16_e64:{ *:[i1] } i32:{ *:[i32] }:$src0_modifiers, f16:{ *:[f16] }:$src0, i32:{ *:[i32] }:$src1_modifiers, f16:{ *:[f16] }:$src1, i1:{ *:[i1] }:$clamp)
          GIR_BuildMI, /*InsnID*/0, /*Opcode*/GIMT_Encode2(AMDGPU::V_CMP_LE_F16_e64),
          GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/0, // DstI[sdst]
          GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/1, // src0_modifiers
          GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/0, // src0
          GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(1), /*SubOperand*/1, // src1_modifiers
          GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(1), /*SubOperand*/0, // src1
          GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/2, // clamp
          GIR_ConstrainSelectedInstOperands, /*InsnID*/0,
          GIR_EraseFromParent, /*InsnID*/0,
          // GIR_Coverage, 355,
          GIR_Done,
        // Label 3881: @248170
        GIM_Try, /*On fail goto*//*Label 3882*/ GIMT_Encode4(248235), // Rule ID 357 //
          GIM_CheckFeatures, GIMT_Encode2(GIFBS_Has16BitInsts_HasTrue16BitInsts),
          // MIs[0] Operand 1
          GIM_CheckCmpPredicate, /*MI*/0, /*Op*/1, /*Predicate*/GIMT_Encode2(CmpInst::FCMP_OLE),
          GIM_CheckComplexPattern, /*MI*/0, /*Op*/2, /*Renderer*/GIMT_Encode2(0), GIMT_Encode2(GICP_gi_vop3mods0),
          GIM_CheckComplexPattern, /*MI*/0, /*Op*/3, /*Renderer*/GIMT_Encode2(1), GIMT_Encode2(GICP_gi_vop3mods),
          // (setcc:{ *:[i1] } (VOP3Mods0:{ *:[f16] } f16:{ *:[f16] }:$src0, i32:{ *:[i32] }:$src0_modifiers, i1:{ *:[i1] }:$clamp), (VOP3Mods:{ *:[f16] } f16:{ *:[f16] }:$src1, i32:{ *:[i32] }:$src1_modifiers), SETOLE:{ *:[Other] })  =>  (V_CMP_LE_F16_t16_e64:{ *:[i1] } i32:{ *:[i32] }:$src0_modifiers, f16:{ *:[f16] }:$src0, i32:{ *:[i32] }:$src1_modifiers, f16:{ *:[f16] }:$src1, i1:{ *:[i1] }:$clamp)
          GIR_BuildMI, /*InsnID*/0, /*Opcode*/GIMT_Encode2(AMDGPU::V_CMP_LE_F16_t16_e64),
          GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/0, // DstI[sdst]
          GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/1, // src0_modifiers
          GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/0, // src0
          GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(1), /*SubOperand*/1, // src1_modifiers
          GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(1), /*SubOperand*/0, // src1
          GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/2, // clamp
          GIR_ConstrainSelectedInstOperands, /*InsnID*/0,
          GIR_EraseFromParent, /*InsnID*/0,
          // GIR_Coverage, 357,
          GIR_Done,
        // Label 3882: @248235
        GIM_Try, /*On fail goto*//*Label 3883*/ GIMT_Encode4(248300), // Rule ID 359 //
          GIM_CheckFeatures, GIMT_Encode2(GIFBS_Has16BitInsts_NotHasTrue16BitInsts),
          // MIs[0] Operand 1
          GIM_CheckCmpPredicate, /*MI*/0, /*Op*/1, /*Predicate*/GIMT_Encode2(CmpInst::FCMP_OGT),
          GIM_CheckComplexPattern, /*MI*/0, /*Op*/2, /*Renderer*/GIMT_Encode2(0), GIMT_Encode2(GICP_gi_vop3mods0),
          GIM_CheckComplexPattern, /*MI*/0, /*Op*/3, /*Renderer*/GIMT_Encode2(1), GIMT_Encode2(GICP_gi_vop3mods),
          // (setcc:{ *:[i1] } (VOP3Mods0:{ *:[f16] } f16:{ *:[f16] }:$src0, i32:{ *:[i32] }:$src0_modifiers, i1:{ *:[i1] }:$clamp), (VOP3Mods:{ *:[f16] } f16:{ *:[f16] }:$src1, i32:{ *:[i32] }:$src1_modifiers), SETOGT:{ *:[Other] })  =>  (V_CMP_GT_F16_e64:{ *:[i1] } i32:{ *:[i32] }:$src0_modifiers, f16:{ *:[f16] }:$src0, i32:{ *:[i32] }:$src1_modifiers, f16:{ *:[f16] }:$src1, i1:{ *:[i1] }:$clamp)
          GIR_BuildMI, /*InsnID*/0, /*Opcode*/GIMT_Encode2(AMDGPU::V_CMP_GT_F16_e64),
          GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/0, // DstI[sdst]
          GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/1, // src0_modifiers
          GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/0, // src0
          GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(1), /*SubOperand*/1, // src1_modifiers
          GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(1), /*SubOperand*/0, // src1
          GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/2, // clamp
          GIR_ConstrainSelectedInstOperands, /*InsnID*/0,
          GIR_EraseFromParent, /*InsnID*/0,
          // GIR_Coverage, 359,
          GIR_Done,
        // Label 3883: @248300
        GIM_Try, /*On fail goto*//*Label 3884*/ GIMT_Encode4(248365), // Rule ID 361 //
          GIM_CheckFeatures, GIMT_Encode2(GIFBS_Has16BitInsts_HasTrue16BitInsts),
          // MIs[0] Operand 1
          GIM_CheckCmpPredicate, /*MI*/0, /*Op*/1, /*Predicate*/GIMT_Encode2(CmpInst::FCMP_OGT),
          GIM_CheckComplexPattern, /*MI*/0, /*Op*/2, /*Renderer*/GIMT_Encode2(0), GIMT_Encode2(GICP_gi_vop3mods0),
          GIM_CheckComplexPattern, /*MI*/0, /*Op*/3, /*Renderer*/GIMT_Encode2(1), GIMT_Encode2(GICP_gi_vop3mods),
          // (setcc:{ *:[i1] } (VOP3Mods0:{ *:[f16] } f16:{ *:[f16] }:$src0, i32:{ *:[i32] }:$src0_modifiers, i1:{ *:[i1] }:$clamp), (VOP3Mods:{ *:[f16] } f16:{ *:[f16] }:$src1, i32:{ *:[i32] }:$src1_modifiers), SETOGT:{ *:[Other] })  =>  (V_CMP_GT_F16_t16_e64:{ *:[i1] } i32:{ *:[i32] }:$src0_modifiers, f16:{ *:[f16] }:$src0, i32:{ *:[i32] }:$src1_modifiers, f16:{ *:[f16] }:$src1, i1:{ *:[i1] }:$clamp)
          GIR_BuildMI, /*InsnID*/0, /*Opcode*/GIMT_Encode2(AMDGPU::V_CMP_GT_F16_t16_e64),
          GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/0, // DstI[sdst]
          GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/1, // src0_modifiers
          GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/0, // src0
          GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(1), /*SubOperand*/1, // src1_modifiers
          GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(1), /*SubOperand*/0, // src1
          GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/2, // clamp
          GIR_ConstrainSelectedInstOperands, /*InsnID*/0,
          GIR_EraseFromParent, /*InsnID*/0,
          // GIR_Coverage, 361,
          GIR_Done,
        // Label 3884: @248365
        GIM_Try, /*On fail goto*//*Label 3885*/ GIMT_Encode4(248430), // Rule ID 363 //
          GIM_CheckFeatures, GIMT_Encode2(GIFBS_Has16BitInsts_NotHasTrue16BitInsts),
          // MIs[0] Operand 1
          GIM_CheckCmpPredicate, /*MI*/0, /*Op*/1, /*Predicate*/GIMT_Encode2(CmpInst::FCMP_ONE),
          GIM_CheckComplexPattern, /*MI*/0, /*Op*/2, /*Renderer*/GIMT_Encode2(0), GIMT_Encode2(GICP_gi_vop3mods0),
          GIM_CheckComplexPattern, /*MI*/0, /*Op*/3, /*Renderer*/GIMT_Encode2(1), GIMT_Encode2(GICP_gi_vop3mods),
          // (setcc:{ *:[i1] } (VOP3Mods0:{ *:[f16] } f16:{ *:[f16] }:$src0, i32:{ *:[i32] }:$src0_modifiers, i1:{ *:[i1] }:$clamp), (VOP3Mods:{ *:[f16] } f16:{ *:[f16] }:$src1, i32:{ *:[i32] }:$src1_modifiers), SETONE:{ *:[Other] })  =>  (V_CMP_LG_F16_e64:{ *:[i1] } i32:{ *:[i32] }:$src0_modifiers, f16:{ *:[f16] }:$src0, i32:{ *:[i32] }:$src1_modifiers, f16:{ *:[f16] }:$src1, i1:{ *:[i1] }:$clamp)
          GIR_BuildMI, /*InsnID*/0, /*Opcode*/GIMT_Encode2(AMDGPU::V_CMP_LG_F16_e64),
          GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/0, // DstI[sdst]
          GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/1, // src0_modifiers
          GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/0, // src0
          GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(1), /*SubOperand*/1, // src1_modifiers
          GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(1), /*SubOperand*/0, // src1
          GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/2, // clamp
          GIR_ConstrainSelectedInstOperands, /*InsnID*/0,
          GIR_EraseFromParent, /*InsnID*/0,
          // GIR_Coverage, 363,
          GIR_Done,
        // Label 3885: @248430
        GIM_Try, /*On fail goto*//*Label 3886*/ GIMT_Encode4(248495), // Rule ID 365 //
          GIM_CheckFeatures, GIMT_Encode2(GIFBS_Has16BitInsts_HasTrue16BitInsts),
          // MIs[0] Operand 1
          GIM_CheckCmpPredicate, /*MI*/0, /*Op*/1, /*Predicate*/GIMT_Encode2(CmpInst::FCMP_ONE),
          GIM_CheckComplexPattern, /*MI*/0, /*Op*/2, /*Renderer*/GIMT_Encode2(0), GIMT_Encode2(GICP_gi_vop3mods0),
          GIM_CheckComplexPattern, /*MI*/0, /*Op*/3, /*Renderer*/GIMT_Encode2(1), GIMT_Encode2(GICP_gi_vop3mods),
          // (setcc:{ *:[i1] } (VOP3Mods0:{ *:[f16] } f16:{ *:[f16] }:$src0, i32:{ *:[i32] }:$src0_modifiers, i1:{ *:[i1] }:$clamp), (VOP3Mods:{ *:[f16] } f16:{ *:[f16] }:$src1, i32:{ *:[i32] }:$src1_modifiers), SETONE:{ *:[Other] })  =>  (V_CMP_LG_F16_t16_e64:{ *:[i1] } i32:{ *:[i32] }:$src0_modifiers, f16:{ *:[f16] }:$src0, i32:{ *:[i32] }:$src1_modifiers, f16:{ *:[f16] }:$src1, i1:{ *:[i1] }:$clamp)
          GIR_BuildMI, /*InsnID*/0, /*Opcode*/GIMT_Encode2(AMDGPU::V_CMP_LG_F16_t16_e64),
          GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/0, // DstI[sdst]
          GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/1, // src0_modifiers
          GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/0, // src0
          GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(1), /*SubOperand*/1, // src1_modifiers
          GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(1), /*SubOperand*/0, // src1
          GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/2, // clamp
          GIR_ConstrainSelectedInstOperands, /*InsnID*/0,
          GIR_EraseFromParent, /*InsnID*/0,
          // GIR_Coverage, 365,
          GIR_Done,
        // Label 3886: @248495
        GIM_Try, /*On fail goto*//*Label 3887*/ GIMT_Encode4(248560), // Rule ID 367 //
          GIM_CheckFeatures, GIMT_Encode2(GIFBS_Has16BitInsts_NotHasTrue16BitInsts),
          // MIs[0] Operand 1
          GIM_CheckCmpPredicate, /*MI*/0, /*Op*/1, /*Predicate*/GIMT_Encode2(CmpInst::FCMP_OGE),
          GIM_CheckComplexPattern, /*MI*/0, /*Op*/2, /*Renderer*/GIMT_Encode2(0), GIMT_Encode2(GICP_gi_vop3mods0),
          GIM_CheckComplexPattern, /*MI*/0, /*Op*/3, /*Renderer*/GIMT_Encode2(1), GIMT_Encode2(GICP_gi_vop3mods),
          // (setcc:{ *:[i1] } (VOP3Mods0:{ *:[f16] } f16:{ *:[f16] }:$src0, i32:{ *:[i32] }:$src0_modifiers, i1:{ *:[i1] }:$clamp), (VOP3Mods:{ *:[f16] } f16:{ *:[f16] }:$src1, i32:{ *:[i32] }:$src1_modifiers), SETOGE:{ *:[Other] })  =>  (V_CMP_GE_F16_e64:{ *:[i1] } i32:{ *:[i32] }:$src0_modifiers, f16:{ *:[f16] }:$src0, i32:{ *:[i32] }:$src1_modifiers, f16:{ *:[f16] }:$src1, i1:{ *:[i1] }:$clamp)
          GIR_BuildMI, /*InsnID*/0, /*Opcode*/GIMT_Encode2(AMDGPU::V_CMP_GE_F16_e64),
          GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/0, // DstI[sdst]
          GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/1, // src0_modifiers
          GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/0, // src0
          GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(1), /*SubOperand*/1, // src1_modifiers
          GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(1), /*SubOperand*/0, // src1
          GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/2, // clamp
          GIR_ConstrainSelectedInstOperands, /*InsnID*/0,
          GIR_EraseFromParent, /*InsnID*/0,
          // GIR_Coverage, 367,
          GIR_Done,
        // Label 3887: @248560
        GIM_Try, /*On fail goto*//*Label 3888*/ GIMT_Encode4(248625), // Rule ID 369 //
          GIM_CheckFeatures, GIMT_Encode2(GIFBS_Has16BitInsts_HasTrue16BitInsts),
          // MIs[0] Operand 1
          GIM_CheckCmpPredicate, /*MI*/0, /*Op*/1, /*Predicate*/GIMT_Encode2(CmpInst::FCMP_OGE),
          GIM_CheckComplexPattern, /*MI*/0, /*Op*/2, /*Renderer*/GIMT_Encode2(0), GIMT_Encode2(GICP_gi_vop3mods0),
          GIM_CheckComplexPattern, /*MI*/0, /*Op*/3, /*Renderer*/GIMT_Encode2(1), GIMT_Encode2(GICP_gi_vop3mods),
          // (setcc:{ *:[i1] } (VOP3Mods0:{ *:[f16] } f16:{ *:[f16] }:$src0, i32:{ *:[i32] }:$src0_modifiers, i1:{ *:[i1] }:$clamp), (VOP3Mods:{ *:[f16] } f16:{ *:[f16] }:$src1, i32:{ *:[i32] }:$src1_modifiers), SETOGE:{ *:[Other] })  =>  (V_CMP_GE_F16_t16_e64:{ *:[i1] } i32:{ *:[i32] }:$src0_modifiers, f16:{ *:[f16] }:$src0, i32:{ *:[i32] }:$src1_modifiers, f16:{ *:[f16] }:$src1, i1:{ *:[i1] }:$clamp)
          GIR_BuildMI, /*InsnID*/0, /*Opcode*/GIMT_Encode2(AMDGPU::V_CMP_GE_F16_t16_e64),
          GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/0, // DstI[sdst]
          GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/1, // src0_modifiers
          GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/0, // src0
          GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(1), /*SubOperand*/1, // src1_modifiers
          GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(1), /*SubOperand*/0, // src1
          GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/2, // clamp
          GIR_ConstrainSelectedInstOperands, /*InsnID*/0,
          GIR_EraseFromParent, /*InsnID*/0,
          // GIR_Coverage, 369,
          GIR_Done,
        // Label 3888: @248625
        GIM_Try, /*On fail goto*//*Label 3889*/ GIMT_Encode4(248690), // Rule ID 371 //
          GIM_CheckFeatures, GIMT_Encode2(GIFBS_Has16BitInsts_NotHasTrue16BitInsts),
          // MIs[0] Operand 1
          GIM_CheckCmpPredicate, /*MI*/0, /*Op*/1, /*Predicate*/GIMT_Encode2(CmpInst::FCMP_ORD),
          GIM_CheckComplexPattern, /*MI*/0, /*Op*/2, /*Renderer*/GIMT_Encode2(0), GIMT_Encode2(GICP_gi_vop3mods0),
          GIM_CheckComplexPattern, /*MI*/0, /*Op*/3, /*Renderer*/GIMT_Encode2(1), GIMT_Encode2(GICP_gi_vop3mods),
          // (setcc:{ *:[i1] } (VOP3Mods0:{ *:[f16] } f16:{ *:[f16] }:$src0, i32:{ *:[i32] }:$src0_modifiers, i1:{ *:[i1] }:$clamp), (VOP3Mods:{ *:[f16] } f16:{ *:[f16] }:$src1, i32:{ *:[i32] }:$src1_modifiers), SETO:{ *:[Other] })  =>  (V_CMP_O_F16_e64:{ *:[i1] } i32:{ *:[i32] }:$src0_modifiers, f16:{ *:[f16] }:$src0, i32:{ *:[i32] }:$src1_modifiers, f16:{ *:[f16] }:$src1, i1:{ *:[i1] }:$clamp)
          GIR_BuildMI, /*InsnID*/0, /*Opcode*/GIMT_Encode2(AMDGPU::V_CMP_O_F16_e64),
          GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/0, // DstI[sdst]
          GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/1, // src0_modifiers
          GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/0, // src0
          GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(1), /*SubOperand*/1, // src1_modifiers
          GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(1), /*SubOperand*/0, // src1
          GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/2, // clamp
          GIR_ConstrainSelectedInstOperands, /*InsnID*/0,
          GIR_EraseFromParent, /*InsnID*/0,
          // GIR_Coverage, 371,
          GIR_Done,
        // Label 3889: @248690
        GIM_Try, /*On fail goto*//*Label 3890*/ GIMT_Encode4(248755), // Rule ID 372 //
          GIM_CheckFeatures, GIMT_Encode2(GIFBS_Has16BitInsts_HasTrue16BitInsts),
          // MIs[0] Operand 1
          GIM_CheckCmpPredicate, /*MI*/0, /*Op*/1, /*Predicate*/GIMT_Encode2(CmpInst::FCMP_ORD),
          GIM_CheckComplexPattern, /*MI*/0, /*Op*/2, /*Renderer*/GIMT_Encode2(0), GIMT_Encode2(GICP_gi_vop3mods0),
          GIM_CheckComplexPattern, /*MI*/0, /*Op*/3, /*Renderer*/GIMT_Encode2(1), GIMT_Encode2(GICP_gi_vop3mods),
          // (setcc:{ *:[i1] } (VOP3Mods0:{ *:[f16] } f16:{ *:[f16] }:$src0, i32:{ *:[i32] }:$src0_modifiers, i1:{ *:[i1] }:$clamp), (VOP3Mods:{ *:[f16] } f16:{ *:[f16] }:$src1, i32:{ *:[i32] }:$src1_modifiers), SETO:{ *:[Other] })  =>  (V_CMP_O_F16_t16_e64:{ *:[i1] } i32:{ *:[i32] }:$src0_modifiers, f16:{ *:[f16] }:$src0, i32:{ *:[i32] }:$src1_modifiers, f16:{ *:[f16] }:$src1, i1:{ *:[i1] }:$clamp)
          GIR_BuildMI, /*InsnID*/0, /*Opcode*/GIMT_Encode2(AMDGPU::V_CMP_O_F16_t16_e64),
          GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/0, // DstI[sdst]
          GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/1, // src0_modifiers
          GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/0, // src0
          GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(1), /*SubOperand*/1, // src1_modifiers
          GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(1), /*SubOperand*/0, // src1
          GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/2, // clamp
          GIR_ConstrainSelectedInstOperands, /*InsnID*/0,
          GIR_EraseFromParent, /*InsnID*/0,
          // GIR_Coverage, 372,
          GIR_Done,
        // Label 3890: @248755
        GIM_Try, /*On fail goto*//*Label 3891*/ GIMT_Encode4(248820), // Rule ID 373 //
          GIM_CheckFeatures, GIMT_Encode2(GIFBS_Has16BitInsts_NotHasTrue16BitInsts),
          // MIs[0] Operand 1
          GIM_CheckCmpPredicate, /*MI*/0, /*Op*/1, /*Predicate*/GIMT_Encode2(CmpInst::FCMP_UNO),
          GIM_CheckComplexPattern, /*MI*/0, /*Op*/2, /*Renderer*/GIMT_Encode2(0), GIMT_Encode2(GICP_gi_vop3mods0),
          GIM_CheckComplexPattern, /*MI*/0, /*Op*/3, /*Renderer*/GIMT_Encode2(1), GIMT_Encode2(GICP_gi_vop3mods),
          // (setcc:{ *:[i1] } (VOP3Mods0:{ *:[f16] } f16:{ *:[f16] }:$src0, i32:{ *:[i32] }:$src0_modifiers, i1:{ *:[i1] }:$clamp), (VOP3Mods:{ *:[f16] } f16:{ *:[f16] }:$src1, i32:{ *:[i32] }:$src1_modifiers), SETUO:{ *:[Other] })  =>  (V_CMP_U_F16_e64:{ *:[i1] } i32:{ *:[i32] }:$src0_modifiers, f16:{ *:[f16] }:$src0, i32:{ *:[i32] }:$src1_modifiers, f16:{ *:[f16] }:$src1, i1:{ *:[i1] }:$clamp)
          GIR_BuildMI, /*InsnID*/0, /*Opcode*/GIMT_Encode2(AMDGPU::V_CMP_U_F16_e64),
          GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/0, // DstI[sdst]
          GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/1, // src0_modifiers
          GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/0, // src0
          GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(1), /*SubOperand*/1, // src1_modifiers
          GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(1), /*SubOperand*/0, // src1
          GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/2, // clamp
          GIR_ConstrainSelectedInstOperands, /*InsnID*/0,
          GIR_EraseFromParent, /*InsnID*/0,
          // GIR_Coverage, 373,
          GIR_Done,
        // Label 3891: @248820
        GIM_Try, /*On fail goto*//*Label 3892*/ GIMT_Encode4(248885), // Rule ID 374 //
          GIM_CheckFeatures, GIMT_Encode2(GIFBS_Has16BitInsts_HasTrue16BitInsts),
          // MIs[0] Operand 1
          GIM_CheckCmpPredicate, /*MI*/0, /*Op*/1, /*Predicate*/GIMT_Encode2(CmpInst::FCMP_UNO),
          GIM_CheckComplexPattern, /*MI*/0, /*Op*/2, /*Renderer*/GIMT_Encode2(0), GIMT_Encode2(GICP_gi_vop3mods0),
          GIM_CheckComplexPattern, /*MI*/0, /*Op*/3, /*Renderer*/GIMT_Encode2(1), GIMT_Encode2(GICP_gi_vop3mods),
          // (setcc:{ *:[i1] } (VOP3Mods0:{ *:[f16] } f16:{ *:[f16] }:$src0, i32:{ *:[i32] }:$src0_modifiers, i1:{ *:[i1] }:$clamp), (VOP3Mods:{ *:[f16] } f16:{ *:[f16] }:$src1, i32:{ *:[i32] }:$src1_modifiers), SETUO:{ *:[Other] })  =>  (V_CMP_U_F16_t16_e64:{ *:[i1] } i32:{ *:[i32] }:$src0_modifiers, f16:{ *:[f16] }:$src0, i32:{ *:[i32] }:$src1_modifiers, f16:{ *:[f16] }:$src1, i1:{ *:[i1] }:$clamp)
          GIR_BuildMI, /*InsnID*/0, /*Opcode*/GIMT_Encode2(AMDGPU::V_CMP_U_F16_t16_e64),
          GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/0, // DstI[sdst]
          GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/1, // src0_modifiers
          GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/0, // src0
          GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(1), /*SubOperand*/1, // src1_modifiers
          GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(1), /*SubOperand*/0, // src1
          GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/2, // clamp
          GIR_ConstrainSelectedInstOperands, /*InsnID*/0,
          GIR_EraseFromParent, /*InsnID*/0,
          // GIR_Coverage, 374,
          GIR_Done,
        // Label 3892: @248885
        GIM_Try, /*On fail goto*//*Label 3893*/ GIMT_Encode4(248950), // Rule ID 375 //
          GIM_CheckFeatures, GIMT_Encode2(GIFBS_Has16BitInsts_NotHasTrue16BitInsts),
          // MIs[0] Operand 1
          GIM_CheckCmpPredicate, /*MI*/0, /*Op*/1, /*Predicate*/GIMT_Encode2(CmpInst::FCMP_ULT),
          GIM_CheckComplexPattern, /*MI*/0, /*Op*/2, /*Renderer*/GIMT_Encode2(0), GIMT_Encode2(GICP_gi_vop3mods0),
          GIM_CheckComplexPattern, /*MI*/0, /*Op*/3, /*Renderer*/GIMT_Encode2(1), GIMT_Encode2(GICP_gi_vop3mods),
          // (setcc:{ *:[i1] } (VOP3Mods0:{ *:[f16] } f16:{ *:[f16] }:$src0, i32:{ *:[i32] }:$src0_modifiers, i1:{ *:[i1] }:$clamp), (VOP3Mods:{ *:[f16] } f16:{ *:[f16] }:$src1, i32:{ *:[i32] }:$src1_modifiers), SETULT:{ *:[Other] })  =>  (V_CMP_NGE_F16_e64:{ *:[i1] } i32:{ *:[i32] }:$src0_modifiers, f16:{ *:[f16] }:$src0, i32:{ *:[i32] }:$src1_modifiers, f16:{ *:[f16] }:$src1, i1:{ *:[i1] }:$clamp)
          GIR_BuildMI, /*InsnID*/0, /*Opcode*/GIMT_Encode2(AMDGPU::V_CMP_NGE_F16_e64),
          GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/0, // DstI[sdst]
          GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/1, // src0_modifiers
          GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/0, // src0
          GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(1), /*SubOperand*/1, // src1_modifiers
          GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(1), /*SubOperand*/0, // src1
          GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/2, // clamp
          GIR_ConstrainSelectedInstOperands, /*InsnID*/0,
          GIR_EraseFromParent, /*InsnID*/0,
          // GIR_Coverage, 375,
          GIR_Done,
        // Label 3893: @248950
        GIM_Try, /*On fail goto*//*Label 3894*/ GIMT_Encode4(249015), // Rule ID 376 //
          GIM_CheckFeatures, GIMT_Encode2(GIFBS_Has16BitInsts_HasTrue16BitInsts),
          // MIs[0] Operand 1
          GIM_CheckCmpPredicate, /*MI*/0, /*Op*/1, /*Predicate*/GIMT_Encode2(CmpInst::FCMP_ULT),
          GIM_CheckComplexPattern, /*MI*/0, /*Op*/2, /*Renderer*/GIMT_Encode2(0), GIMT_Encode2(GICP_gi_vop3mods0),
          GIM_CheckComplexPattern, /*MI*/0, /*Op*/3, /*Renderer*/GIMT_Encode2(1), GIMT_Encode2(GICP_gi_vop3mods),
          // (setcc:{ *:[i1] } (VOP3Mods0:{ *:[f16] } f16:{ *:[f16] }:$src0, i32:{ *:[i32] }:$src0_modifiers, i1:{ *:[i1] }:$clamp), (VOP3Mods:{ *:[f16] } f16:{ *:[f16] }:$src1, i32:{ *:[i32] }:$src1_modifiers), SETULT:{ *:[Other] })  =>  (V_CMP_NGE_F16_t16_e64:{ *:[i1] } i32:{ *:[i32] }:$src0_modifiers, f16:{ *:[f16] }:$src0, i32:{ *:[i32] }:$src1_modifiers, f16:{ *:[f16] }:$src1, i1:{ *:[i1] }:$clamp)
          GIR_BuildMI, /*InsnID*/0, /*Opcode*/GIMT_Encode2(AMDGPU::V_CMP_NGE_F16_t16_e64),
          GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/0, // DstI[sdst]
          GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/1, // src0_modifiers
          GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/0, // src0
          GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(1), /*SubOperand*/1, // src1_modifiers
          GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(1), /*SubOperand*/0, // src1
          GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/2, // clamp
          GIR_ConstrainSelectedInstOperands, /*InsnID*/0,
          GIR_EraseFromParent, /*InsnID*/0,
          // GIR_Coverage, 376,
          GIR_Done,
        // Label 3894: @249015
        GIM_Try, /*On fail goto*//*Label 3895*/ GIMT_Encode4(249080), // Rule ID 377 //
          GIM_CheckFeatures, GIMT_Encode2(GIFBS_Has16BitInsts_NotHasTrue16BitInsts),
          // MIs[0] Operand 1
          GIM_CheckCmpPredicate, /*MI*/0, /*Op*/1, /*Predicate*/GIMT_Encode2(CmpInst::FCMP_UEQ),
          GIM_CheckComplexPattern, /*MI*/0, /*Op*/2, /*Renderer*/GIMT_Encode2(0), GIMT_Encode2(GICP_gi_vop3mods0),
          GIM_CheckComplexPattern, /*MI*/0, /*Op*/3, /*Renderer*/GIMT_Encode2(1), GIMT_Encode2(GICP_gi_vop3mods),
          // (setcc:{ *:[i1] } (VOP3Mods0:{ *:[f16] } f16:{ *:[f16] }:$src0, i32:{ *:[i32] }:$src0_modifiers, i1:{ *:[i1] }:$clamp), (VOP3Mods:{ *:[f16] } f16:{ *:[f16] }:$src1, i32:{ *:[i32] }:$src1_modifiers), SETUEQ:{ *:[Other] })  =>  (V_CMP_NLG_F16_e64:{ *:[i1] } i32:{ *:[i32] }:$src0_modifiers, f16:{ *:[f16] }:$src0, i32:{ *:[i32] }:$src1_modifiers, f16:{ *:[f16] }:$src1, i1:{ *:[i1] }:$clamp)
          GIR_BuildMI, /*InsnID*/0, /*Opcode*/GIMT_Encode2(AMDGPU::V_CMP_NLG_F16_e64),
          GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/0, // DstI[sdst]
          GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/1, // src0_modifiers
          GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/0, // src0
          GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(1), /*SubOperand*/1, // src1_modifiers
          GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(1), /*SubOperand*/0, // src1
          GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/2, // clamp
          GIR_ConstrainSelectedInstOperands, /*InsnID*/0,
          GIR_EraseFromParent, /*InsnID*/0,
          // GIR_Coverage, 377,
          GIR_Done,
        // Label 3895: @249080
        GIM_Try, /*On fail goto*//*Label 3896*/ GIMT_Encode4(249145), // Rule ID 378 //
          GIM_CheckFeatures, GIMT_Encode2(GIFBS_Has16BitInsts_HasTrue16BitInsts),
          // MIs[0] Operand 1
          GIM_CheckCmpPredicate, /*MI*/0, /*Op*/1, /*Predicate*/GIMT_Encode2(CmpInst::FCMP_UEQ),
          GIM_CheckComplexPattern, /*MI*/0, /*Op*/2, /*Renderer*/GIMT_Encode2(0), GIMT_Encode2(GICP_gi_vop3mods0),
          GIM_CheckComplexPattern, /*MI*/0, /*Op*/3, /*Renderer*/GIMT_Encode2(1), GIMT_Encode2(GICP_gi_vop3mods),
          // (setcc:{ *:[i1] } (VOP3Mods0:{ *:[f16] } f16:{ *:[f16] }:$src0, i32:{ *:[i32] }:$src0_modifiers, i1:{ *:[i1] }:$clamp), (VOP3Mods:{ *:[f16] } f16:{ *:[f16] }:$src1, i32:{ *:[i32] }:$src1_modifiers), SETUEQ:{ *:[Other] })  =>  (V_CMP_NLG_F16_t16_e64:{ *:[i1] } i32:{ *:[i32] }:$src0_modifiers, f16:{ *:[f16] }:$src0, i32:{ *:[i32] }:$src1_modifiers, f16:{ *:[f16] }:$src1, i1:{ *:[i1] }:$clamp)
          GIR_BuildMI, /*InsnID*/0, /*Opcode*/GIMT_Encode2(AMDGPU::V_CMP_NLG_F16_t16_e64),
          GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/0, // DstI[sdst]
          GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/1, // src0_modifiers
          GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/0, // src0
          GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(1), /*SubOperand*/1, // src1_modifiers
          GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(1), /*SubOperand*/0, // src1
          GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/2, // clamp
          GIR_ConstrainSelectedInstOperands, /*InsnID*/0,
          GIR_EraseFromParent, /*InsnID*/0,
          // GIR_Coverage, 378,
          GIR_Done,
        // Label 3896: @249145
        GIM_Try, /*On fail goto*//*Label 3897*/ GIMT_Encode4(249210), // Rule ID 379 //
          GIM_CheckFeatures, GIMT_Encode2(GIFBS_Has16BitInsts_NotHasTrue16BitInsts),
          // MIs[0] Operand 1
          GIM_CheckCmpPredicate, /*MI*/0, /*Op*/1, /*Predicate*/GIMT_Encode2(CmpInst::FCMP_ULE),
          GIM_CheckComplexPattern, /*MI*/0, /*Op*/2, /*Renderer*/GIMT_Encode2(0), GIMT_Encode2(GICP_gi_vop3mods0),
          GIM_CheckComplexPattern, /*MI*/0, /*Op*/3, /*Renderer*/GIMT_Encode2(1), GIMT_Encode2(GICP_gi_vop3mods),
          // (setcc:{ *:[i1] } (VOP3Mods0:{ *:[f16] } f16:{ *:[f16] }:$src0, i32:{ *:[i32] }:$src0_modifiers, i1:{ *:[i1] }:$clamp), (VOP3Mods:{ *:[f16] } f16:{ *:[f16] }:$src1, i32:{ *:[i32] }:$src1_modifiers), SETULE:{ *:[Other] })  =>  (V_CMP_NGT_F16_e64:{ *:[i1] } i32:{ *:[i32] }:$src0_modifiers, f16:{ *:[f16] }:$src0, i32:{ *:[i32] }:$src1_modifiers, f16:{ *:[f16] }:$src1, i1:{ *:[i1] }:$clamp)
          GIR_BuildMI, /*InsnID*/0, /*Opcode*/GIMT_Encode2(AMDGPU::V_CMP_NGT_F16_e64),
          GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/0, // DstI[sdst]
          GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/1, // src0_modifiers
          GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/0, // src0
          GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(1), /*SubOperand*/1, // src1_modifiers
          GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(1), /*SubOperand*/0, // src1
          GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/2, // clamp
          GIR_ConstrainSelectedInstOperands, /*InsnID*/0,
          GIR_EraseFromParent, /*InsnID*/0,
          // GIR_Coverage, 379,
          GIR_Done,
        // Label 3897: @249210
        GIM_Try, /*On fail goto*//*Label 3898*/ GIMT_Encode4(249275), // Rule ID 380 //
          GIM_CheckFeatures, GIMT_Encode2(GIFBS_Has16BitInsts_HasTrue16BitInsts),
          // MIs[0] Operand 1
          GIM_CheckCmpPredicate, /*MI*/0, /*Op*/1, /*Predicate*/GIMT_Encode2(CmpInst::FCMP_ULE),
          GIM_CheckComplexPattern, /*MI*/0, /*Op*/2, /*Renderer*/GIMT_Encode2(0), GIMT_Encode2(GICP_gi_vop3mods0),
          GIM_CheckComplexPattern, /*MI*/0, /*Op*/3, /*Renderer*/GIMT_Encode2(1), GIMT_Encode2(GICP_gi_vop3mods),
          // (setcc:{ *:[i1] } (VOP3Mods0:{ *:[f16] } f16:{ *:[f16] }:$src0, i32:{ *:[i32] }:$src0_modifiers, i1:{ *:[i1] }:$clamp), (VOP3Mods:{ *:[f16] } f16:{ *:[f16] }:$src1, i32:{ *:[i32] }:$src1_modifiers), SETULE:{ *:[Other] })  =>  (V_CMP_NGT_F16_t16_e64:{ *:[i1] } i32:{ *:[i32] }:$src0_modifiers, f16:{ *:[f16] }:$src0, i32:{ *:[i32] }:$src1_modifiers, f16:{ *:[f16] }:$src1, i1:{ *:[i1] }:$clamp)
          GIR_BuildMI, /*InsnID*/0, /*Opcode*/GIMT_Encode2(AMDGPU::V_CMP_NGT_F16_t16_e64),
          GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/0, // DstI[sdst]
          GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/1, // src0_modifiers
          GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/0, // src0
          GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(1), /*SubOperand*/1, // src1_modifiers
          GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(1), /*SubOperand*/0, // src1
          GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/2, // clamp
          GIR_ConstrainSelectedInstOperands, /*InsnID*/0,
          GIR_EraseFromParent, /*InsnID*/0,
          // GIR_Coverage, 380,
          GIR_Done,
        // Label 3898: @249275
        GIM_Try, /*On fail goto*//*Label 3899*/ GIMT_Encode4(249340), // Rule ID 381 //
          GIM_CheckFeatures, GIMT_Encode2(GIFBS_Has16BitInsts_NotHasTrue16BitInsts),
          // MIs[0] Operand 1
          GIM_CheckCmpPredicate, /*MI*/0, /*Op*/1, /*Predicate*/GIMT_Encode2(CmpInst::FCMP_UGT),
          GIM_CheckComplexPattern, /*MI*/0, /*Op*/2, /*Renderer*/GIMT_Encode2(0), GIMT_Encode2(GICP_gi_vop3mods0),
          GIM_CheckComplexPattern, /*MI*/0, /*Op*/3, /*Renderer*/GIMT_Encode2(1), GIMT_Encode2(GICP_gi_vop3mods),
          // (setcc:{ *:[i1] } (VOP3Mods0:{ *:[f16] } f16:{ *:[f16] }:$src0, i32:{ *:[i32] }:$src0_modifiers, i1:{ *:[i1] }:$clamp), (VOP3Mods:{ *:[f16] } f16:{ *:[f16] }:$src1, i32:{ *:[i32] }:$src1_modifiers), SETUGT:{ *:[Other] })  =>  (V_CMP_NLE_F16_e64:{ *:[i1] } i32:{ *:[i32] }:$src0_modifiers, f16:{ *:[f16] }:$src0, i32:{ *:[i32] }:$src1_modifiers, f16:{ *:[f16] }:$src1, i1:{ *:[i1] }:$clamp)
          GIR_BuildMI, /*InsnID*/0, /*Opcode*/GIMT_Encode2(AMDGPU::V_CMP_NLE_F16_e64),
          GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/0, // DstI[sdst]
          GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/1, // src0_modifiers
          GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/0, // src0
          GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(1), /*SubOperand*/1, // src1_modifiers
          GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(1), /*SubOperand*/0, // src1
          GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/2, // clamp
          GIR_ConstrainSelectedInstOperands, /*InsnID*/0,
          GIR_EraseFromParent, /*InsnID*/0,
          // GIR_Coverage, 381,
          GIR_Done,
        // Label 3899: @249340
        GIM_Try, /*On fail goto*//*Label 3900*/ GIMT_Encode4(249405), // Rule ID 382 //
          GIM_CheckFeatures, GIMT_Encode2(GIFBS_Has16BitInsts_HasTrue16BitInsts),
          // MIs[0] Operand 1
          GIM_CheckCmpPredicate, /*MI*/0, /*Op*/1, /*Predicate*/GIMT_Encode2(CmpInst::FCMP_UGT),
          GIM_CheckComplexPattern, /*MI*/0, /*Op*/2, /*Renderer*/GIMT_Encode2(0), GIMT_Encode2(GICP_gi_vop3mods0),
          GIM_CheckComplexPattern, /*MI*/0, /*Op*/3, /*Renderer*/GIMT_Encode2(1), GIMT_Encode2(GICP_gi_vop3mods),
          // (setcc:{ *:[i1] } (VOP3Mods0:{ *:[f16] } f16:{ *:[f16] }:$src0, i32:{ *:[i32] }:$src0_modifiers, i1:{ *:[i1] }:$clamp), (VOP3Mods:{ *:[f16] } f16:{ *:[f16] }:$src1, i32:{ *:[i32] }:$src1_modifiers), SETUGT:{ *:[Other] })  =>  (V_CMP_NLE_F16_t16_e64:{ *:[i1] } i32:{ *:[i32] }:$src0_modifiers, f16:{ *:[f16] }:$src0, i32:{ *:[i32] }:$src1_modifiers, f16:{ *:[f16] }:$src1, i1:{ *:[i1] }:$clamp)
          GIR_BuildMI, /*InsnID*/0, /*Opcode*/GIMT_Encode2(AMDGPU::V_CMP_NLE_F16_t16_e64),
          GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/0, // DstI[sdst]
          GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/1, // src0_modifiers
          GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/0, // src0
          GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(1), /*SubOperand*/1, // src1_modifiers
          GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(1), /*SubOperand*/0, // src1
          GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/2, // clamp
          GIR_ConstrainSelectedInstOperands, /*InsnID*/0,
          GIR_EraseFromParent, /*InsnID*/0,
          // GIR_Coverage, 382,
          GIR_Done,
        // Label 3900: @249405
        GIM_Try, /*On fail goto*//*Label 3901*/ GIMT_Encode4(249470), // Rule ID 383 //
          GIM_CheckFeatures, GIMT_Encode2(GIFBS_Has16BitInsts_NotHasTrue16BitInsts),
          // MIs[0] Operand 1
          GIM_CheckCmpPredicate, /*MI*/0, /*Op*/1, /*Predicate*/GIMT_Encode2(CmpInst::FCMP_UNE),
          GIM_CheckComplexPattern, /*MI*/0, /*Op*/2, /*Renderer*/GIMT_Encode2(0), GIMT_Encode2(GICP_gi_vop3mods0),
          GIM_CheckComplexPattern, /*MI*/0, /*Op*/3, /*Renderer*/GIMT_Encode2(1), GIMT_Encode2(GICP_gi_vop3mods),
          // (setcc:{ *:[i1] } (VOP3Mods0:{ *:[f16] } f16:{ *:[f16] }:$src0, i32:{ *:[i32] }:$src0_modifiers, i1:{ *:[i1] }:$clamp), (VOP3Mods:{ *:[f16] } f16:{ *:[f16] }:$src1, i32:{ *:[i32] }:$src1_modifiers), SETUNE:{ *:[Other] })  =>  (V_CMP_NEQ_F16_e64:{ *:[i1] } i32:{ *:[i32] }:$src0_modifiers, f16:{ *:[f16] }:$src0, i32:{ *:[i32] }:$src1_modifiers, f16:{ *:[f16] }:$src1, i1:{ *:[i1] }:$clamp)
          GIR_BuildMI, /*InsnID*/0, /*Opcode*/GIMT_Encode2(AMDGPU::V_CMP_NEQ_F16_e64),
          GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/0, // DstI[sdst]
          GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/1, // src0_modifiers
          GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/0, // src0
          GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(1), /*SubOperand*/1, // src1_modifiers
          GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(1), /*SubOperand*/0, // src1
          GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/2, // clamp
          GIR_ConstrainSelectedInstOperands, /*InsnID*/0,
          GIR_EraseFromParent, /*InsnID*/0,
          // GIR_Coverage, 383,
          GIR_Done,
        // Label 3901: @249470
        GIM_Try, /*On fail goto*//*Label 3902*/ GIMT_Encode4(249535), // Rule ID 384 //
          GIM_CheckFeatures, GIMT_Encode2(GIFBS_Has16BitInsts_HasTrue16BitInsts),
          // MIs[0] Operand 1
          GIM_CheckCmpPredicate, /*MI*/0, /*Op*/1, /*Predicate*/GIMT_Encode2(CmpInst::FCMP_UNE),
          GIM_CheckComplexPattern, /*MI*/0, /*Op*/2, /*Renderer*/GIMT_Encode2(0), GIMT_Encode2(GICP_gi_vop3mods0),
          GIM_CheckComplexPattern, /*MI*/0, /*Op*/3, /*Renderer*/GIMT_Encode2(1), GIMT_Encode2(GICP_gi_vop3mods),
          // (setcc:{ *:[i1] } (VOP3Mods0:{ *:[f16] } f16:{ *:[f16] }:$src0, i32:{ *:[i32] }:$src0_modifiers, i1:{ *:[i1] }:$clamp), (VOP3Mods:{ *:[f16] } f16:{ *:[f16] }:$src1, i32:{ *:[i32] }:$src1_modifiers), SETUNE:{ *:[Other] })  =>  (V_CMP_NEQ_F16_t16_e64:{ *:[i1] } i32:{ *:[i32] }:$src0_modifiers, f16:{ *:[f16] }:$src0, i32:{ *:[i32] }:$src1_modifiers, f16:{ *:[f16] }:$src1, i1:{ *:[i1] }:$clamp)
          GIR_BuildMI, /*InsnID*/0, /*Opcode*/GIMT_Encode2(AMDGPU::V_CMP_NEQ_F16_t16_e64),
          GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/0, // DstI[sdst]
          GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/1, // src0_modifiers
          GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/0, // src0
          GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(1), /*SubOperand*/1, // src1_modifiers
          GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(1), /*SubOperand*/0, // src1
          GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/2, // clamp
          GIR_ConstrainSelectedInstOperands, /*InsnID*/0,
          GIR_EraseFromParent, /*InsnID*/0,
          // GIR_Coverage, 384,
          GIR_Done,
        // Label 3902: @249535
        GIM_Try, /*On fail goto*//*Label 3903*/ GIMT_Encode4(249600), // Rule ID 385 //
          GIM_CheckFeatures, GIMT_Encode2(GIFBS_Has16BitInsts_NotHasTrue16BitInsts),
          // MIs[0] Operand 1
          GIM_CheckCmpPredicate, /*MI*/0, /*Op*/1, /*Predicate*/GIMT_Encode2(CmpInst::FCMP_UGE),
          GIM_CheckComplexPattern, /*MI*/0, /*Op*/2, /*Renderer*/GIMT_Encode2(0), GIMT_Encode2(GICP_gi_vop3mods0),
          GIM_CheckComplexPattern, /*MI*/0, /*Op*/3, /*Renderer*/GIMT_Encode2(1), GIMT_Encode2(GICP_gi_vop3mods),
          // (setcc:{ *:[i1] } (VOP3Mods0:{ *:[f16] } f16:{ *:[f16] }:$src0, i32:{ *:[i32] }:$src0_modifiers, i1:{ *:[i1] }:$clamp), (VOP3Mods:{ *:[f16] } f16:{ *:[f16] }:$src1, i32:{ *:[i32] }:$src1_modifiers), SETUGE:{ *:[Other] })  =>  (V_CMP_NLT_F16_e64:{ *:[i1] } i32:{ *:[i32] }:$src0_modifiers, f16:{ *:[f16] }:$src0, i32:{ *:[i32] }:$src1_modifiers, f16:{ *:[f16] }:$src1, i1:{ *:[i1] }:$clamp)
          GIR_BuildMI, /*InsnID*/0, /*Opcode*/GIMT_Encode2(AMDGPU::V_CMP_NLT_F16_e64),
          GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/0, // DstI[sdst]
          GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/1, // src0_modifiers
          GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/0, // src0
          GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(1), /*SubOperand*/1, // src1_modifiers
          GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(1), /*SubOperand*/0, // src1
          GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/2, // clamp
          GIR_ConstrainSelectedInstOperands, /*InsnID*/0,
          GIR_EraseFromParent, /*InsnID*/0,
          // GIR_Coverage, 385,
          GIR_Done,
        // Label 3903: @249600
        GIM_Try, /*On fail goto*//*Label 3904*/ GIMT_Encode4(249665), // Rule ID 386 //
          GIM_CheckFeatures, GIMT_Encode2(GIFBS_Has16BitInsts_HasTrue16BitInsts),
          // MIs[0] Operand 1
          GIM_CheckCmpPredicate, /*MI*/0, /*Op*/1, /*Predicate*/GIMT_Encode2(CmpInst::FCMP_UGE),
          GIM_CheckComplexPattern, /*MI*/0, /*Op*/2, /*Renderer*/GIMT_Encode2(0), GIMT_Encode2(GICP_gi_vop3mods0),
          GIM_CheckComplexPattern, /*MI*/0, /*Op*/3, /*Renderer*/GIMT_Encode2(1), GIMT_Encode2(GICP_gi_vop3mods),
          // (setcc:{ *:[i1] } (VOP3Mods0:{ *:[f16] } f16:{ *:[f16] }:$src0, i32:{ *:[i32] }:$src0_modifiers, i1:{ *:[i1] }:$clamp), (VOP3Mods:{ *:[f16] } f16:{ *:[f16] }:$src1, i32:{ *:[i32] }:$src1_modifiers), SETUGE:{ *:[Other] })  =>  (V_CMP_NLT_F16_t16_e64:{ *:[i1] } i32:{ *:[i32] }:$src0_modifiers, f16:{ *:[f16] }:$src0, i32:{ *:[i32] }:$src1_modifiers, f16:{ *:[f16] }:$src1, i1:{ *:[i1] }:$clamp)
          GIR_BuildMI, /*InsnID*/0, /*Opcode*/GIMT_Encode2(AMDGPU::V_CMP_NLT_F16_t16_e64),
          GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/0, // DstI[sdst]
          GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/1, // src0_modifiers
          GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/0, // src0
          GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(1), /*SubOperand*/1, // src1_modifiers
          GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(1), /*SubOperand*/0, // src1
          GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/2, // clamp
          GIR_ConstrainSelectedInstOperands, /*InsnID*/0,
          GIR_EraseFromParent, /*InsnID*/0,
          // GIR_Coverage, 386,
          GIR_Done,
        // Label 3904: @249665
        GIM_Reject,
      // Label 3876: @249666
      GIM_Reject,
      // Label 3873: @249667
      GIM_Try, /*On fail goto*//*Label 3905*/ GIMT_Encode4(250550),
        GIM_CheckType, /*MI*/0, /*Op*/3, /*Type*/GILLT_s32,
        GIM_CheckRegBankForClass, /*MI*/0, /*Op*/0, /*RC*/GIMT_Encode2(AMDGPU::SReg_1RegClassID),
        GIM_Try, /*On fail goto*//*Label 3906*/ GIMT_Encode4(249743), // Rule ID 206 //
          // MIs[0] Operand 1
          GIM_CheckCmpPredicate, /*MI*/0, /*Op*/1, /*Predicate*/GIMT_Encode2(CmpInst::FCMP_OLT),
          GIM_CheckComplexPattern, /*MI*/0, /*Op*/2, /*Renderer*/GIMT_Encode2(0), GIMT_Encode2(GICP_gi_vop3mods0),
          GIM_CheckComplexPattern, /*MI*/0, /*Op*/3, /*Renderer*/GIMT_Encode2(1), GIMT_Encode2(GICP_gi_vop3mods),
          // (setcc:{ *:[i1] } (VOP3Mods0:{ *:[f32] } f32:{ *:[f32] }:$src0, i32:{ *:[i32] }:$src0_modifiers, i1:{ *:[i1] }:$clamp), (VOP3Mods:{ *:[f32] } f32:{ *:[f32] }:$src1, i32:{ *:[i32] }:$src1_modifiers), SETOLT:{ *:[Other] })  =>  (V_CMP_LT_F32_e64:{ *:[i1] } i32:{ *:[i32] }:$src0_modifiers, f32:{ *:[f32] }:$src0, i32:{ *:[i32] }:$src1_modifiers, f32:{ *:[f32] }:$src1, i1:{ *:[i1] }:$clamp)
          GIR_BuildMI, /*InsnID*/0, /*Opcode*/GIMT_Encode2(AMDGPU::V_CMP_LT_F32_e64),
          GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/0, // DstI[sdst]
          GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/1, // src0_modifiers
          GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/0, // src0
          GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(1), /*SubOperand*/1, // src1_modifiers
          GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(1), /*SubOperand*/0, // src1
          GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/2, // clamp
          GIR_ConstrainSelectedInstOperands, /*InsnID*/0,
          GIR_EraseFromParent, /*InsnID*/0,
          // GIR_Coverage, 206,
          GIR_Done,
        // Label 3906: @249743
        GIM_Try, /*On fail goto*//*Label 3907*/ GIMT_Encode4(249805), // Rule ID 208 //
          // MIs[0] Operand 1
          GIM_CheckCmpPredicate, /*MI*/0, /*Op*/1, /*Predicate*/GIMT_Encode2(CmpInst::FCMP_OEQ),
          GIM_CheckComplexPattern, /*MI*/0, /*Op*/2, /*Renderer*/GIMT_Encode2(0), GIMT_Encode2(GICP_gi_vop3mods0),
          GIM_CheckComplexPattern, /*MI*/0, /*Op*/3, /*Renderer*/GIMT_Encode2(1), GIMT_Encode2(GICP_gi_vop3mods),
          // (setcc:{ *:[i1] } (VOP3Mods0:{ *:[f32] } f32:{ *:[f32] }:$src0, i32:{ *:[i32] }:$src0_modifiers, i1:{ *:[i1] }:$clamp), (VOP3Mods:{ *:[f32] } f32:{ *:[f32] }:$src1, i32:{ *:[i32] }:$src1_modifiers), SETOEQ:{ *:[Other] })  =>  (V_CMP_EQ_F32_e64:{ *:[i1] } i32:{ *:[i32] }:$src0_modifiers, f32:{ *:[f32] }:$src0, i32:{ *:[i32] }:$src1_modifiers, f32:{ *:[f32] }:$src1, i1:{ *:[i1] }:$clamp)
          GIR_BuildMI, /*InsnID*/0, /*Opcode*/GIMT_Encode2(AMDGPU::V_CMP_EQ_F32_e64),
          GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/0, // DstI[sdst]
          GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/1, // src0_modifiers
          GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/0, // src0
          GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(1), /*SubOperand*/1, // src1_modifiers
          GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(1), /*SubOperand*/0, // src1
          GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/2, // clamp
          GIR_ConstrainSelectedInstOperands, /*InsnID*/0,
          GIR_EraseFromParent, /*InsnID*/0,
          // GIR_Coverage, 208,
          GIR_Done,
        // Label 3907: @249805
        GIM_Try, /*On fail goto*//*Label 3908*/ GIMT_Encode4(249867), // Rule ID 210 //
          // MIs[0] Operand 1
          GIM_CheckCmpPredicate, /*MI*/0, /*Op*/1, /*Predicate*/GIMT_Encode2(CmpInst::FCMP_OLE),
          GIM_CheckComplexPattern, /*MI*/0, /*Op*/2, /*Renderer*/GIMT_Encode2(0), GIMT_Encode2(GICP_gi_vop3mods0),
          GIM_CheckComplexPattern, /*MI*/0, /*Op*/3, /*Renderer*/GIMT_Encode2(1), GIMT_Encode2(GICP_gi_vop3mods),
          // (setcc:{ *:[i1] } (VOP3Mods0:{ *:[f32] } f32:{ *:[f32] }:$src0, i32:{ *:[i32] }:$src0_modifiers, i1:{ *:[i1] }:$clamp), (VOP3Mods:{ *:[f32] } f32:{ *:[f32] }:$src1, i32:{ *:[i32] }:$src1_modifiers), SETOLE:{ *:[Other] })  =>  (V_CMP_LE_F32_e64:{ *:[i1] } i32:{ *:[i32] }:$src0_modifiers, f32:{ *:[f32] }:$src0, i32:{ *:[i32] }:$src1_modifiers, f32:{ *:[f32] }:$src1, i1:{ *:[i1] }:$clamp)
          GIR_BuildMI, /*InsnID*/0, /*Opcode*/GIMT_Encode2(AMDGPU::V_CMP_LE_F32_e64),
          GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/0, // DstI[sdst]
          GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/1, // src0_modifiers
          GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/0, // src0
          GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(1), /*SubOperand*/1, // src1_modifiers
          GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(1), /*SubOperand*/0, // src1
          GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/2, // clamp
          GIR_ConstrainSelectedInstOperands, /*InsnID*/0,
          GIR_EraseFromParent, /*InsnID*/0,
          // GIR_Coverage, 210,
          GIR_Done,
        // Label 3908: @249867
        GIM_Try, /*On fail goto*//*Label 3909*/ GIMT_Encode4(249929), // Rule ID 212 //
          // MIs[0] Operand 1
          GIM_CheckCmpPredicate, /*MI*/0, /*Op*/1, /*Predicate*/GIMT_Encode2(CmpInst::FCMP_OGT),
          GIM_CheckComplexPattern, /*MI*/0, /*Op*/2, /*Renderer*/GIMT_Encode2(0), GIMT_Encode2(GICP_gi_vop3mods0),
          GIM_CheckComplexPattern, /*MI*/0, /*Op*/3, /*Renderer*/GIMT_Encode2(1), GIMT_Encode2(GICP_gi_vop3mods),
          // (setcc:{ *:[i1] } (VOP3Mods0:{ *:[f32] } f32:{ *:[f32] }:$src0, i32:{ *:[i32] }:$src0_modifiers, i1:{ *:[i1] }:$clamp), (VOP3Mods:{ *:[f32] } f32:{ *:[f32] }:$src1, i32:{ *:[i32] }:$src1_modifiers), SETOGT:{ *:[Other] })  =>  (V_CMP_GT_F32_e64:{ *:[i1] } i32:{ *:[i32] }:$src0_modifiers, f32:{ *:[f32] }:$src0, i32:{ *:[i32] }:$src1_modifiers, f32:{ *:[f32] }:$src1, i1:{ *:[i1] }:$clamp)
          GIR_BuildMI, /*InsnID*/0, /*Opcode*/GIMT_Encode2(AMDGPU::V_CMP_GT_F32_e64),
          GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/0, // DstI[sdst]
          GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/1, // src0_modifiers
          GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/0, // src0
          GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(1), /*SubOperand*/1, // src1_modifiers
          GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(1), /*SubOperand*/0, // src1
          GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/2, // clamp
          GIR_ConstrainSelectedInstOperands, /*InsnID*/0,
          GIR_EraseFromParent, /*InsnID*/0,
          // GIR_Coverage, 212,
          GIR_Done,
        // Label 3909: @249929
        GIM_Try, /*On fail goto*//*Label 3910*/ GIMT_Encode4(249991), // Rule ID 214 //
          // MIs[0] Operand 1
          GIM_CheckCmpPredicate, /*MI*/0, /*Op*/1, /*Predicate*/GIMT_Encode2(CmpInst::FCMP_ONE),
          GIM_CheckComplexPattern, /*MI*/0, /*Op*/2, /*Renderer*/GIMT_Encode2(0), GIMT_Encode2(GICP_gi_vop3mods0),
          GIM_CheckComplexPattern, /*MI*/0, /*Op*/3, /*Renderer*/GIMT_Encode2(1), GIMT_Encode2(GICP_gi_vop3mods),
          // (setcc:{ *:[i1] } (VOP3Mods0:{ *:[f32] } f32:{ *:[f32] }:$src0, i32:{ *:[i32] }:$src0_modifiers, i1:{ *:[i1] }:$clamp), (VOP3Mods:{ *:[f32] } f32:{ *:[f32] }:$src1, i32:{ *:[i32] }:$src1_modifiers), SETONE:{ *:[Other] })  =>  (V_CMP_LG_F32_e64:{ *:[i1] } i32:{ *:[i32] }:$src0_modifiers, f32:{ *:[f32] }:$src0, i32:{ *:[i32] }:$src1_modifiers, f32:{ *:[f32] }:$src1, i1:{ *:[i1] }:$clamp)
          GIR_BuildMI, /*InsnID*/0, /*Opcode*/GIMT_Encode2(AMDGPU::V_CMP_LG_F32_e64),
          GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/0, // DstI[sdst]
          GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/1, // src0_modifiers
          GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/0, // src0
          GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(1), /*SubOperand*/1, // src1_modifiers
          GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(1), /*SubOperand*/0, // src1
          GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/2, // clamp
          GIR_ConstrainSelectedInstOperands, /*InsnID*/0,
          GIR_EraseFromParent, /*InsnID*/0,
          // GIR_Coverage, 214,
          GIR_Done,
        // Label 3910: @249991
        GIM_Try, /*On fail goto*//*Label 3911*/ GIMT_Encode4(250053), // Rule ID 216 //
          // MIs[0] Operand 1
          GIM_CheckCmpPredicate, /*MI*/0, /*Op*/1, /*Predicate*/GIMT_Encode2(CmpInst::FCMP_OGE),
          GIM_CheckComplexPattern, /*MI*/0, /*Op*/2, /*Renderer*/GIMT_Encode2(0), GIMT_Encode2(GICP_gi_vop3mods0),
          GIM_CheckComplexPattern, /*MI*/0, /*Op*/3, /*Renderer*/GIMT_Encode2(1), GIMT_Encode2(GICP_gi_vop3mods),
          // (setcc:{ *:[i1] } (VOP3Mods0:{ *:[f32] } f32:{ *:[f32] }:$src0, i32:{ *:[i32] }:$src0_modifiers, i1:{ *:[i1] }:$clamp), (VOP3Mods:{ *:[f32] } f32:{ *:[f32] }:$src1, i32:{ *:[i32] }:$src1_modifiers), SETOGE:{ *:[Other] })  =>  (V_CMP_GE_F32_e64:{ *:[i1] } i32:{ *:[i32] }:$src0_modifiers, f32:{ *:[f32] }:$src0, i32:{ *:[i32] }:$src1_modifiers, f32:{ *:[f32] }:$src1, i1:{ *:[i1] }:$clamp)
          GIR_BuildMI, /*InsnID*/0, /*Opcode*/GIMT_Encode2(AMDGPU::V_CMP_GE_F32_e64),
          GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/0, // DstI[sdst]
          GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/1, // src0_modifiers
          GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/0, // src0
          GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(1), /*SubOperand*/1, // src1_modifiers
          GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(1), /*SubOperand*/0, // src1
          GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/2, // clamp
          GIR_ConstrainSelectedInstOperands, /*InsnID*/0,
          GIR_EraseFromParent, /*InsnID*/0,
          // GIR_Coverage, 216,
          GIR_Done,
        // Label 3911: @250053
        GIM_Try, /*On fail goto*//*Label 3912*/ GIMT_Encode4(250115), // Rule ID 218 //
          // MIs[0] Operand 1
          GIM_CheckCmpPredicate, /*MI*/0, /*Op*/1, /*Predicate*/GIMT_Encode2(CmpInst::FCMP_ORD),
          GIM_CheckComplexPattern, /*MI*/0, /*Op*/2, /*Renderer*/GIMT_Encode2(0), GIMT_Encode2(GICP_gi_vop3mods0),
          GIM_CheckComplexPattern, /*MI*/0, /*Op*/3, /*Renderer*/GIMT_Encode2(1), GIMT_Encode2(GICP_gi_vop3mods),
          // (setcc:{ *:[i1] } (VOP3Mods0:{ *:[f32] } f32:{ *:[f32] }:$src0, i32:{ *:[i32] }:$src0_modifiers, i1:{ *:[i1] }:$clamp), (VOP3Mods:{ *:[f32] } f32:{ *:[f32] }:$src1, i32:{ *:[i32] }:$src1_modifiers), SETO:{ *:[Other] })  =>  (V_CMP_O_F32_e64:{ *:[i1] } i32:{ *:[i32] }:$src0_modifiers, f32:{ *:[f32] }:$src0, i32:{ *:[i32] }:$src1_modifiers, f32:{ *:[f32] }:$src1, i1:{ *:[i1] }:$clamp)
          GIR_BuildMI, /*InsnID*/0, /*Opcode*/GIMT_Encode2(AMDGPU::V_CMP_O_F32_e64),
          GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/0, // DstI[sdst]
          GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/1, // src0_modifiers
          GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/0, // src0
          GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(1), /*SubOperand*/1, // src1_modifiers
          GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(1), /*SubOperand*/0, // src1
          GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/2, // clamp
          GIR_ConstrainSelectedInstOperands, /*InsnID*/0,
          GIR_EraseFromParent, /*InsnID*/0,
          // GIR_Coverage, 218,
          GIR_Done,
        // Label 3912: @250115
        GIM_Try, /*On fail goto*//*Label 3913*/ GIMT_Encode4(250177), // Rule ID 219 //
          // MIs[0] Operand 1
          GIM_CheckCmpPredicate, /*MI*/0, /*Op*/1, /*Predicate*/GIMT_Encode2(CmpInst::FCMP_UNO),
          GIM_CheckComplexPattern, /*MI*/0, /*Op*/2, /*Renderer*/GIMT_Encode2(0), GIMT_Encode2(GICP_gi_vop3mods0),
          GIM_CheckComplexPattern, /*MI*/0, /*Op*/3, /*Renderer*/GIMT_Encode2(1), GIMT_Encode2(GICP_gi_vop3mods),
          // (setcc:{ *:[i1] } (VOP3Mods0:{ *:[f32] } f32:{ *:[f32] }:$src0, i32:{ *:[i32] }:$src0_modifiers, i1:{ *:[i1] }:$clamp), (VOP3Mods:{ *:[f32] } f32:{ *:[f32] }:$src1, i32:{ *:[i32] }:$src1_modifiers), SETUO:{ *:[Other] })  =>  (V_CMP_U_F32_e64:{ *:[i1] } i32:{ *:[i32] }:$src0_modifiers, f32:{ *:[f32] }:$src0, i32:{ *:[i32] }:$src1_modifiers, f32:{ *:[f32] }:$src1, i1:{ *:[i1] }:$clamp)
          GIR_BuildMI, /*InsnID*/0, /*Opcode*/GIMT_Encode2(AMDGPU::V_CMP_U_F32_e64),
          GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/0, // DstI[sdst]
          GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/1, // src0_modifiers
          GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/0, // src0
          GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(1), /*SubOperand*/1, // src1_modifiers
          GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(1), /*SubOperand*/0, // src1
          GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/2, // clamp
          GIR_ConstrainSelectedInstOperands, /*InsnID*/0,
          GIR_EraseFromParent, /*InsnID*/0,
          // GIR_Coverage, 219,
          GIR_Done,
        // Label 3913: @250177
        GIM_Try, /*On fail goto*//*Label 3914*/ GIMT_Encode4(250239), // Rule ID 220 //
          // MIs[0] Operand 1
          GIM_CheckCmpPredicate, /*MI*/0, /*Op*/1, /*Predicate*/GIMT_Encode2(CmpInst::FCMP_ULT),
          GIM_CheckComplexPattern, /*MI*/0, /*Op*/2, /*Renderer*/GIMT_Encode2(0), GIMT_Encode2(GICP_gi_vop3mods0),
          GIM_CheckComplexPattern, /*MI*/0, /*Op*/3, /*Renderer*/GIMT_Encode2(1), GIMT_Encode2(GICP_gi_vop3mods),
          // (setcc:{ *:[i1] } (VOP3Mods0:{ *:[f32] } f32:{ *:[f32] }:$src0, i32:{ *:[i32] }:$src0_modifiers, i1:{ *:[i1] }:$clamp), (VOP3Mods:{ *:[f32] } f32:{ *:[f32] }:$src1, i32:{ *:[i32] }:$src1_modifiers), SETULT:{ *:[Other] })  =>  (V_CMP_NGE_F32_e64:{ *:[i1] } i32:{ *:[i32] }:$src0_modifiers, f32:{ *:[f32] }:$src0, i32:{ *:[i32] }:$src1_modifiers, f32:{ *:[f32] }:$src1, i1:{ *:[i1] }:$clamp)
          GIR_BuildMI, /*InsnID*/0, /*Opcode*/GIMT_Encode2(AMDGPU::V_CMP_NGE_F32_e64),
          GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/0, // DstI[sdst]
          GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/1, // src0_modifiers
          GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/0, // src0
          GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(1), /*SubOperand*/1, // src1_modifiers
          GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(1), /*SubOperand*/0, // src1
          GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/2, // clamp
          GIR_ConstrainSelectedInstOperands, /*InsnID*/0,
          GIR_EraseFromParent, /*InsnID*/0,
          // GIR_Coverage, 220,
          GIR_Done,
        // Label 3914: @250239
        GIM_Try, /*On fail goto*//*Label 3915*/ GIMT_Encode4(250301), // Rule ID 221 //
          // MIs[0] Operand 1
          GIM_CheckCmpPredicate, /*MI*/0, /*Op*/1, /*Predicate*/GIMT_Encode2(CmpInst::FCMP_UEQ),
          GIM_CheckComplexPattern, /*MI*/0, /*Op*/2, /*Renderer*/GIMT_Encode2(0), GIMT_Encode2(GICP_gi_vop3mods0),
          GIM_CheckComplexPattern, /*MI*/0, /*Op*/3, /*Renderer*/GIMT_Encode2(1), GIMT_Encode2(GICP_gi_vop3mods),
          // (setcc:{ *:[i1] } (VOP3Mods0:{ *:[f32] } f32:{ *:[f32] }:$src0, i32:{ *:[i32] }:$src0_modifiers, i1:{ *:[i1] }:$clamp), (VOP3Mods:{ *:[f32] } f32:{ *:[f32] }:$src1, i32:{ *:[i32] }:$src1_modifiers), SETUEQ:{ *:[Other] })  =>  (V_CMP_NLG_F32_e64:{ *:[i1] } i32:{ *:[i32] }:$src0_modifiers, f32:{ *:[f32] }:$src0, i32:{ *:[i32] }:$src1_modifiers, f32:{ *:[f32] }:$src1, i1:{ *:[i1] }:$clamp)
          GIR_BuildMI, /*InsnID*/0, /*Opcode*/GIMT_Encode2(AMDGPU::V_CMP_NLG_F32_e64),
          GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/0, // DstI[sdst]
          GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/1, // src0_modifiers
          GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/0, // src0
          GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(1), /*SubOperand*/1, // src1_modifiers
          GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(1), /*SubOperand*/0, // src1
          GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/2, // clamp
          GIR_ConstrainSelectedInstOperands, /*InsnID*/0,
          GIR_EraseFromParent, /*InsnID*/0,
          // GIR_Coverage, 221,
          GIR_Done,
        // Label 3915: @250301
        GIM_Try, /*On fail goto*//*Label 3916*/ GIMT_Encode4(250363), // Rule ID 222 //
          // MIs[0] Operand 1
          GIM_CheckCmpPredicate, /*MI*/0, /*Op*/1, /*Predicate*/GIMT_Encode2(CmpInst::FCMP_ULE),
          GIM_CheckComplexPattern, /*MI*/0, /*Op*/2, /*Renderer*/GIMT_Encode2(0), GIMT_Encode2(GICP_gi_vop3mods0),
          GIM_CheckComplexPattern, /*MI*/0, /*Op*/3, /*Renderer*/GIMT_Encode2(1), GIMT_Encode2(GICP_gi_vop3mods),
          // (setcc:{ *:[i1] } (VOP3Mods0:{ *:[f32] } f32:{ *:[f32] }:$src0, i32:{ *:[i32] }:$src0_modifiers, i1:{ *:[i1] }:$clamp), (VOP3Mods:{ *:[f32] } f32:{ *:[f32] }:$src1, i32:{ *:[i32] }:$src1_modifiers), SETULE:{ *:[Other] })  =>  (V_CMP_NGT_F32_e64:{ *:[i1] } i32:{ *:[i32] }:$src0_modifiers, f32:{ *:[f32] }:$src0, i32:{ *:[i32] }:$src1_modifiers, f32:{ *:[f32] }:$src1, i1:{ *:[i1] }:$clamp)
          GIR_BuildMI, /*InsnID*/0, /*Opcode*/GIMT_Encode2(AMDGPU::V_CMP_NGT_F32_e64),
          GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/0, // DstI[sdst]
          GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/1, // src0_modifiers
          GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/0, // src0
          GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(1), /*SubOperand*/1, // src1_modifiers
          GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(1), /*SubOperand*/0, // src1
          GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/2, // clamp
          GIR_ConstrainSelectedInstOperands, /*InsnID*/0,
          GIR_EraseFromParent, /*InsnID*/0,
          // GIR_Coverage, 222,
          GIR_Done,
        // Label 3916: @250363
        GIM_Try, /*On fail goto*//*Label 3917*/ GIMT_Encode4(250425), // Rule ID 223 //
          // MIs[0] Operand 1
          GIM_CheckCmpPredicate, /*MI*/0, /*Op*/1, /*Predicate*/GIMT_Encode2(CmpInst::FCMP_UGT),
          GIM_CheckComplexPattern, /*MI*/0, /*Op*/2, /*Renderer*/GIMT_Encode2(0), GIMT_Encode2(GICP_gi_vop3mods0),
          GIM_CheckComplexPattern, /*MI*/0, /*Op*/3, /*Renderer*/GIMT_Encode2(1), GIMT_Encode2(GICP_gi_vop3mods),
          // (setcc:{ *:[i1] } (VOP3Mods0:{ *:[f32] } f32:{ *:[f32] }:$src0, i32:{ *:[i32] }:$src0_modifiers, i1:{ *:[i1] }:$clamp), (VOP3Mods:{ *:[f32] } f32:{ *:[f32] }:$src1, i32:{ *:[i32] }:$src1_modifiers), SETUGT:{ *:[Other] })  =>  (V_CMP_NLE_F32_e64:{ *:[i1] } i32:{ *:[i32] }:$src0_modifiers, f32:{ *:[f32] }:$src0, i32:{ *:[i32] }:$src1_modifiers, f32:{ *:[f32] }:$src1, i1:{ *:[i1] }:$clamp)
          GIR_BuildMI, /*InsnID*/0, /*Opcode*/GIMT_Encode2(AMDGPU::V_CMP_NLE_F32_e64),
          GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/0, // DstI[sdst]
          GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/1, // src0_modifiers
          GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/0, // src0
          GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(1), /*SubOperand*/1, // src1_modifiers
          GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(1), /*SubOperand*/0, // src1
          GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/2, // clamp
          GIR_ConstrainSelectedInstOperands, /*InsnID*/0,
          GIR_EraseFromParent, /*InsnID*/0,
          // GIR_Coverage, 223,
          GIR_Done,
        // Label 3917: @250425
        GIM_Try, /*On fail goto*//*Label 3918*/ GIMT_Encode4(250487), // Rule ID 224 //
          // MIs[0] Operand 1
          GIM_CheckCmpPredicate, /*MI*/0, /*Op*/1, /*Predicate*/GIMT_Encode2(CmpInst::FCMP_UNE),
          GIM_CheckComplexPattern, /*MI*/0, /*Op*/2, /*Renderer*/GIMT_Encode2(0), GIMT_Encode2(GICP_gi_vop3mods0),
          GIM_CheckComplexPattern, /*MI*/0, /*Op*/3, /*Renderer*/GIMT_Encode2(1), GIMT_Encode2(GICP_gi_vop3mods),
          // (setcc:{ *:[i1] } (VOP3Mods0:{ *:[f32] } f32:{ *:[f32] }:$src0, i32:{ *:[i32] }:$src0_modifiers, i1:{ *:[i1] }:$clamp), (VOP3Mods:{ *:[f32] } f32:{ *:[f32] }:$src1, i32:{ *:[i32] }:$src1_modifiers), SETUNE:{ *:[Other] })  =>  (V_CMP_NEQ_F32_e64:{ *:[i1] } i32:{ *:[i32] }:$src0_modifiers, f32:{ *:[f32] }:$src0, i32:{ *:[i32] }:$src1_modifiers, f32:{ *:[f32] }:$src1, i1:{ *:[i1] }:$clamp)
          GIR_BuildMI, /*InsnID*/0, /*Opcode*/GIMT_Encode2(AMDGPU::V_CMP_NEQ_F32_e64),
          GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/0, // DstI[sdst]
          GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/1, // src0_modifiers
          GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/0, // src0
          GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(1), /*SubOperand*/1, // src1_modifiers
          GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(1), /*SubOperand*/0, // src1
          GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/2, // clamp
          GIR_ConstrainSelectedInstOperands, /*InsnID*/0,
          GIR_EraseFromParent, /*InsnID*/0,
          // GIR_Coverage, 224,
          GIR_Done,
        // Label 3918: @250487
        GIM_Try, /*On fail goto*//*Label 3919*/ GIMT_Encode4(250549), // Rule ID 225 //
          // MIs[0] Operand 1
          GIM_CheckCmpPredicate, /*MI*/0, /*Op*/1, /*Predicate*/GIMT_Encode2(CmpInst::FCMP_UGE),
          GIM_CheckComplexPattern, /*MI*/0, /*Op*/2, /*Renderer*/GIMT_Encode2(0), GIMT_Encode2(GICP_gi_vop3mods0),
          GIM_CheckComplexPattern, /*MI*/0, /*Op*/3, /*Renderer*/GIMT_Encode2(1), GIMT_Encode2(GICP_gi_vop3mods),
          // (setcc:{ *:[i1] } (VOP3Mods0:{ *:[f32] } f32:{ *:[f32] }:$src0, i32:{ *:[i32] }:$src0_modifiers, i1:{ *:[i1] }:$clamp), (VOP3Mods:{ *:[f32] } f32:{ *:[f32] }:$src1, i32:{ *:[i32] }:$src1_modifiers), SETUGE:{ *:[Other] })  =>  (V_CMP_NLT_F32_e64:{ *:[i1] } i32:{ *:[i32] }:$src0_modifiers, f32:{ *:[f32] }:$src0, i32:{ *:[i32] }:$src1_modifiers, f32:{ *:[f32] }:$src1, i1:{ *:[i1] }:$clamp)
          GIR_BuildMI, /*InsnID*/0, /*Opcode*/GIMT_Encode2(AMDGPU::V_CMP_NLT_F32_e64),
          GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/0, // DstI[sdst]
          GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/1, // src0_modifiers
          GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/0, // src0
          GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(1), /*SubOperand*/1, // src1_modifiers
          GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(1), /*SubOperand*/0, // src1
          GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/2, // clamp
          GIR_ConstrainSelectedInstOperands, /*InsnID*/0,
          GIR_EraseFromParent, /*InsnID*/0,
          // GIR_Coverage, 225,
          GIR_Done,
        // Label 3919: @250549
        GIM_Reject,
      // Label 3905: @250550
      GIM_Reject,
      // Label 3874: @250551
      GIM_Try, /*On fail goto*//*Label 3920*/ GIMT_Encode4(251434),
        GIM_CheckType, /*MI*/0, /*Op*/3, /*Type*/GILLT_s64,
        GIM_CheckRegBankForClass, /*MI*/0, /*Op*/0, /*RC*/GIMT_Encode2(AMDGPU::SReg_1RegClassID),
        GIM_Try, /*On fail goto*//*Label 3921*/ GIMT_Encode4(250627), // Rule ID 244 //
          // MIs[0] Operand 1
          GIM_CheckCmpPredicate, /*MI*/0, /*Op*/1, /*Predicate*/GIMT_Encode2(CmpInst::FCMP_OLT),
          GIM_CheckComplexPattern, /*MI*/0, /*Op*/2, /*Renderer*/GIMT_Encode2(0), GIMT_Encode2(GICP_gi_vop3mods0),
          GIM_CheckComplexPattern, /*MI*/0, /*Op*/3, /*Renderer*/GIMT_Encode2(1), GIMT_Encode2(GICP_gi_vop3mods),
          // (setcc:{ *:[i1] } (VOP3Mods0:{ *:[f64] } f64:{ *:[f64] }:$src0, i32:{ *:[i32] }:$src0_modifiers, i1:{ *:[i1] }:$clamp), (VOP3Mods:{ *:[f64] } f64:{ *:[f64] }:$src1, i32:{ *:[i32] }:$src1_modifiers), SETOLT:{ *:[Other] })  =>  (V_CMP_LT_F64_e64:{ *:[i1] } i32:{ *:[i32] }:$src0_modifiers, f64:{ *:[f64] }:$src0, i32:{ *:[i32] }:$src1_modifiers, f64:{ *:[f64] }:$src1, i1:{ *:[i1] }:$clamp)
          GIR_BuildMI, /*InsnID*/0, /*Opcode*/GIMT_Encode2(AMDGPU::V_CMP_LT_F64_e64),
          GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/0, // DstI[sdst]
          GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/1, // src0_modifiers
          GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/0, // src0
          GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(1), /*SubOperand*/1, // src1_modifiers
          GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(1), /*SubOperand*/0, // src1
          GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/2, // clamp
          GIR_ConstrainSelectedInstOperands, /*InsnID*/0,
          GIR_EraseFromParent, /*InsnID*/0,
          // GIR_Coverage, 244,
          GIR_Done,
        // Label 3921: @250627
        GIM_Try, /*On fail goto*//*Label 3922*/ GIMT_Encode4(250689), // Rule ID 246 //
          // MIs[0] Operand 1
          GIM_CheckCmpPredicate, /*MI*/0, /*Op*/1, /*Predicate*/GIMT_Encode2(CmpInst::FCMP_OEQ),
          GIM_CheckComplexPattern, /*MI*/0, /*Op*/2, /*Renderer*/GIMT_Encode2(0), GIMT_Encode2(GICP_gi_vop3mods0),
          GIM_CheckComplexPattern, /*MI*/0, /*Op*/3, /*Renderer*/GIMT_Encode2(1), GIMT_Encode2(GICP_gi_vop3mods),
          // (setcc:{ *:[i1] } (VOP3Mods0:{ *:[f64] } f64:{ *:[f64] }:$src0, i32:{ *:[i32] }:$src0_modifiers, i1:{ *:[i1] }:$clamp), (VOP3Mods:{ *:[f64] } f64:{ *:[f64] }:$src1, i32:{ *:[i32] }:$src1_modifiers), SETOEQ:{ *:[Other] })  =>  (V_CMP_EQ_F64_e64:{ *:[i1] } i32:{ *:[i32] }:$src0_modifiers, f64:{ *:[f64] }:$src0, i32:{ *:[i32] }:$src1_modifiers, f64:{ *:[f64] }:$src1, i1:{ *:[i1] }:$clamp)
          GIR_BuildMI, /*InsnID*/0, /*Opcode*/GIMT_Encode2(AMDGPU::V_CMP_EQ_F64_e64),
          GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/0, // DstI[sdst]
          GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/1, // src0_modifiers
          GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/0, // src0
          GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(1), /*SubOperand*/1, // src1_modifiers
          GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(1), /*SubOperand*/0, // src1
          GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/2, // clamp
          GIR_ConstrainSelectedInstOperands, /*InsnID*/0,
          GIR_EraseFromParent, /*InsnID*/0,
          // GIR_Coverage, 246,
          GIR_Done,
        // Label 3922: @250689
        GIM_Try, /*On fail goto*//*Label 3923*/ GIMT_Encode4(250751), // Rule ID 248 //
          // MIs[0] Operand 1
          GIM_CheckCmpPredicate, /*MI*/0, /*Op*/1, /*Predicate*/GIMT_Encode2(CmpInst::FCMP_OLE),
          GIM_CheckComplexPattern, /*MI*/0, /*Op*/2, /*Renderer*/GIMT_Encode2(0), GIMT_Encode2(GICP_gi_vop3mods0),
          GIM_CheckComplexPattern, /*MI*/0, /*Op*/3, /*Renderer*/GIMT_Encode2(1), GIMT_Encode2(GICP_gi_vop3mods),
          // (setcc:{ *:[i1] } (VOP3Mods0:{ *:[f64] } f64:{ *:[f64] }:$src0, i32:{ *:[i32] }:$src0_modifiers, i1:{ *:[i1] }:$clamp), (VOP3Mods:{ *:[f64] } f64:{ *:[f64] }:$src1, i32:{ *:[i32] }:$src1_modifiers), SETOLE:{ *:[Other] })  =>  (V_CMP_LE_F64_e64:{ *:[i1] } i32:{ *:[i32] }:$src0_modifiers, f64:{ *:[f64] }:$src0, i32:{ *:[i32] }:$src1_modifiers, f64:{ *:[f64] }:$src1, i1:{ *:[i1] }:$clamp)
          GIR_BuildMI, /*InsnID*/0, /*Opcode*/GIMT_Encode2(AMDGPU::V_CMP_LE_F64_e64),
          GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/0, // DstI[sdst]
          GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/1, // src0_modifiers
          GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/0, // src0
          GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(1), /*SubOperand*/1, // src1_modifiers
          GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(1), /*SubOperand*/0, // src1
          GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/2, // clamp
          GIR_ConstrainSelectedInstOperands, /*InsnID*/0,
          GIR_EraseFromParent, /*InsnID*/0,
          // GIR_Coverage, 248,
          GIR_Done,
        // Label 3923: @250751
        GIM_Try, /*On fail goto*//*Label 3924*/ GIMT_Encode4(250813), // Rule ID 250 //
          // MIs[0] Operand 1
          GIM_CheckCmpPredicate, /*MI*/0, /*Op*/1, /*Predicate*/GIMT_Encode2(CmpInst::FCMP_OGT),
          GIM_CheckComplexPattern, /*MI*/0, /*Op*/2, /*Renderer*/GIMT_Encode2(0), GIMT_Encode2(GICP_gi_vop3mods0),
          GIM_CheckComplexPattern, /*MI*/0, /*Op*/3, /*Renderer*/GIMT_Encode2(1), GIMT_Encode2(GICP_gi_vop3mods),
          // (setcc:{ *:[i1] } (VOP3Mods0:{ *:[f64] } f64:{ *:[f64] }:$src0, i32:{ *:[i32] }:$src0_modifiers, i1:{ *:[i1] }:$clamp), (VOP3Mods:{ *:[f64] } f64:{ *:[f64] }:$src1, i32:{ *:[i32] }:$src1_modifiers), SETOGT:{ *:[Other] })  =>  (V_CMP_GT_F64_e64:{ *:[i1] } i32:{ *:[i32] }:$src0_modifiers, f64:{ *:[f64] }:$src0, i32:{ *:[i32] }:$src1_modifiers, f64:{ *:[f64] }:$src1, i1:{ *:[i1] }:$clamp)
          GIR_BuildMI, /*InsnID*/0, /*Opcode*/GIMT_Encode2(AMDGPU::V_CMP_GT_F64_e64),
          GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/0, // DstI[sdst]
          GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/1, // src0_modifiers
          GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/0, // src0
          GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(1), /*SubOperand*/1, // src1_modifiers
          GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(1), /*SubOperand*/0, // src1
          GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/2, // clamp
          GIR_ConstrainSelectedInstOperands, /*InsnID*/0,
          GIR_EraseFromParent, /*InsnID*/0,
          // GIR_Coverage, 250,
          GIR_Done,
        // Label 3924: @250813
        GIM_Try, /*On fail goto*//*Label 3925*/ GIMT_Encode4(250875), // Rule ID 252 //
          // MIs[0] Operand 1
          GIM_CheckCmpPredicate, /*MI*/0, /*Op*/1, /*Predicate*/GIMT_Encode2(CmpInst::FCMP_ONE),
          GIM_CheckComplexPattern, /*MI*/0, /*Op*/2, /*Renderer*/GIMT_Encode2(0), GIMT_Encode2(GICP_gi_vop3mods0),
          GIM_CheckComplexPattern, /*MI*/0, /*Op*/3, /*Renderer*/GIMT_Encode2(1), GIMT_Encode2(GICP_gi_vop3mods),
          // (setcc:{ *:[i1] } (VOP3Mods0:{ *:[f64] } f64:{ *:[f64] }:$src0, i32:{ *:[i32] }:$src0_modifiers, i1:{ *:[i1] }:$clamp), (VOP3Mods:{ *:[f64] } f64:{ *:[f64] }:$src1, i32:{ *:[i32] }:$src1_modifiers), SETONE:{ *:[Other] })  =>  (V_CMP_LG_F64_e64:{ *:[i1] } i32:{ *:[i32] }:$src0_modifiers, f64:{ *:[f64] }:$src0, i32:{ *:[i32] }:$src1_modifiers, f64:{ *:[f64] }:$src1, i1:{ *:[i1] }:$clamp)
          GIR_BuildMI, /*InsnID*/0, /*Opcode*/GIMT_Encode2(AMDGPU::V_CMP_LG_F64_e64),
          GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/0, // DstI[sdst]
          GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/1, // src0_modifiers
          GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/0, // src0
          GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(1), /*SubOperand*/1, // src1_modifiers
          GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(1), /*SubOperand*/0, // src1
          GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/2, // clamp
          GIR_ConstrainSelectedInstOperands, /*InsnID*/0,
          GIR_EraseFromParent, /*InsnID*/0,
          // GIR_Coverage, 252,
          GIR_Done,
        // Label 3925: @250875
        GIM_Try, /*On fail goto*//*Label 3926*/ GIMT_Encode4(250937), // Rule ID 254 //
          // MIs[0] Operand 1
          GIM_CheckCmpPredicate, /*MI*/0, /*Op*/1, /*Predicate*/GIMT_Encode2(CmpInst::FCMP_OGE),
          GIM_CheckComplexPattern, /*MI*/0, /*Op*/2, /*Renderer*/GIMT_Encode2(0), GIMT_Encode2(GICP_gi_vop3mods0),
          GIM_CheckComplexPattern, /*MI*/0, /*Op*/3, /*Renderer*/GIMT_Encode2(1), GIMT_Encode2(GICP_gi_vop3mods),
          // (setcc:{ *:[i1] } (VOP3Mods0:{ *:[f64] } f64:{ *:[f64] }:$src0, i32:{ *:[i32] }:$src0_modifiers, i1:{ *:[i1] }:$clamp), (VOP3Mods:{ *:[f64] } f64:{ *:[f64] }:$src1, i32:{ *:[i32] }:$src1_modifiers), SETOGE:{ *:[Other] })  =>  (V_CMP_GE_F64_e64:{ *:[i1] } i32:{ *:[i32] }:$src0_modifiers, f64:{ *:[f64] }:$src0, i32:{ *:[i32] }:$src1_modifiers, f64:{ *:[f64] }:$src1, i1:{ *:[i1] }:$clamp)
          GIR_BuildMI, /*InsnID*/0, /*Opcode*/GIMT_Encode2(AMDGPU::V_CMP_GE_F64_e64),
          GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/0, // DstI[sdst]
          GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/1, // src0_modifiers
          GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/0, // src0
          GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(1), /*SubOperand*/1, // src1_modifiers
          GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(1), /*SubOperand*/0, // src1
          GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/2, // clamp
          GIR_ConstrainSelectedInstOperands, /*InsnID*/0,
          GIR_EraseFromParent, /*InsnID*/0,
          // GIR_Coverage, 254,
          GIR_Done,
        // Label 3926: @250937
        GIM_Try, /*On fail goto*//*Label 3927*/ GIMT_Encode4(250999), // Rule ID 256 //
          // MIs[0] Operand 1
          GIM_CheckCmpPredicate, /*MI*/0, /*Op*/1, /*Predicate*/GIMT_Encode2(CmpInst::FCMP_ORD),
          GIM_CheckComplexPattern, /*MI*/0, /*Op*/2, /*Renderer*/GIMT_Encode2(0), GIMT_Encode2(GICP_gi_vop3mods0),
          GIM_CheckComplexPattern, /*MI*/0, /*Op*/3, /*Renderer*/GIMT_Encode2(1), GIMT_Encode2(GICP_gi_vop3mods),
          // (setcc:{ *:[i1] } (VOP3Mods0:{ *:[f64] } f64:{ *:[f64] }:$src0, i32:{ *:[i32] }:$src0_modifiers, i1:{ *:[i1] }:$clamp), (VOP3Mods:{ *:[f64] } f64:{ *:[f64] }:$src1, i32:{ *:[i32] }:$src1_modifiers), SETO:{ *:[Other] })  =>  (V_CMP_O_F64_e64:{ *:[i1] } i32:{ *:[i32] }:$src0_modifiers, f64:{ *:[f64] }:$src0, i32:{ *:[i32] }:$src1_modifiers, f64:{ *:[f64] }:$src1, i1:{ *:[i1] }:$clamp)
          GIR_BuildMI, /*InsnID*/0, /*Opcode*/GIMT_Encode2(AMDGPU::V_CMP_O_F64_e64),
          GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/0, // DstI[sdst]
          GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/1, // src0_modifiers
          GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/0, // src0
          GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(1), /*SubOperand*/1, // src1_modifiers
          GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(1), /*SubOperand*/0, // src1
          GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/2, // clamp
          GIR_ConstrainSelectedInstOperands, /*InsnID*/0,
          GIR_EraseFromParent, /*InsnID*/0,
          // GIR_Coverage, 256,
          GIR_Done,
        // Label 3927: @250999
        GIM_Try, /*On fail goto*//*Label 3928*/ GIMT_Encode4(251061), // Rule ID 257 //
          // MIs[0] Operand 1
          GIM_CheckCmpPredicate, /*MI*/0, /*Op*/1, /*Predicate*/GIMT_Encode2(CmpInst::FCMP_UNO),
          GIM_CheckComplexPattern, /*MI*/0, /*Op*/2, /*Renderer*/GIMT_Encode2(0), GIMT_Encode2(GICP_gi_vop3mods0),
          GIM_CheckComplexPattern, /*MI*/0, /*Op*/3, /*Renderer*/GIMT_Encode2(1), GIMT_Encode2(GICP_gi_vop3mods),
          // (setcc:{ *:[i1] } (VOP3Mods0:{ *:[f64] } f64:{ *:[f64] }:$src0, i32:{ *:[i32] }:$src0_modifiers, i1:{ *:[i1] }:$clamp), (VOP3Mods:{ *:[f64] } f64:{ *:[f64] }:$src1, i32:{ *:[i32] }:$src1_modifiers), SETUO:{ *:[Other] })  =>  (V_CMP_U_F64_e64:{ *:[i1] } i32:{ *:[i32] }:$src0_modifiers, f64:{ *:[f64] }:$src0, i32:{ *:[i32] }:$src1_modifiers, f64:{ *:[f64] }:$src1, i1:{ *:[i1] }:$clamp)
          GIR_BuildMI, /*InsnID*/0, /*Opcode*/GIMT_Encode2(AMDGPU::V_CMP_U_F64_e64),
          GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/0, // DstI[sdst]
          GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/1, // src0_modifiers
          GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/0, // src0
          GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(1), /*SubOperand*/1, // src1_modifiers
          GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(1), /*SubOperand*/0, // src1
          GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/2, // clamp
          GIR_ConstrainSelectedInstOperands, /*InsnID*/0,
          GIR_EraseFromParent, /*InsnID*/0,
          // GIR_Coverage, 257,
          GIR_Done,
        // Label 3928: @251061
        GIM_Try, /*On fail goto*//*Label 3929*/ GIMT_Encode4(251123), // Rule ID 258 //
          // MIs[0] Operand 1
          GIM_CheckCmpPredicate, /*MI*/0, /*Op*/1, /*Predicate*/GIMT_Encode2(CmpInst::FCMP_ULT),
          GIM_CheckComplexPattern, /*MI*/0, /*Op*/2, /*Renderer*/GIMT_Encode2(0), GIMT_Encode2(GICP_gi_vop3mods0),
          GIM_CheckComplexPattern, /*MI*/0, /*Op*/3, /*Renderer*/GIMT_Encode2(1), GIMT_Encode2(GICP_gi_vop3mods),
          // (setcc:{ *:[i1] } (VOP3Mods0:{ *:[f64] } f64:{ *:[f64] }:$src0, i32:{ *:[i32] }:$src0_modifiers, i1:{ *:[i1] }:$clamp), (VOP3Mods:{ *:[f64] } f64:{ *:[f64] }:$src1, i32:{ *:[i32] }:$src1_modifiers), SETULT:{ *:[Other] })  =>  (V_CMP_NGE_F64_e64:{ *:[i1] } i32:{ *:[i32] }:$src0_modifiers, f64:{ *:[f64] }:$src0, i32:{ *:[i32] }:$src1_modifiers, f64:{ *:[f64] }:$src1, i1:{ *:[i1] }:$clamp)
          GIR_BuildMI, /*InsnID*/0, /*Opcode*/GIMT_Encode2(AMDGPU::V_CMP_NGE_F64_e64),
          GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/0, // DstI[sdst]
          GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/1, // src0_modifiers
          GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/0, // src0
          GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(1), /*SubOperand*/1, // src1_modifiers
          GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(1), /*SubOperand*/0, // src1
          GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/2, // clamp
          GIR_ConstrainSelectedInstOperands, /*InsnID*/0,
          GIR_EraseFromParent, /*InsnID*/0,
          // GIR_Coverage, 258,
          GIR_Done,
        // Label 3929: @251123
        GIM_Try, /*On fail goto*//*Label 3930*/ GIMT_Encode4(251185), // Rule ID 259 //
          // MIs[0] Operand 1
          GIM_CheckCmpPredicate, /*MI*/0, /*Op*/1, /*Predicate*/GIMT_Encode2(CmpInst::FCMP_UEQ),
          GIM_CheckComplexPattern, /*MI*/0, /*Op*/2, /*Renderer*/GIMT_Encode2(0), GIMT_Encode2(GICP_gi_vop3mods0),
          GIM_CheckComplexPattern, /*MI*/0, /*Op*/3, /*Renderer*/GIMT_Encode2(1), GIMT_Encode2(GICP_gi_vop3mods),
          // (setcc:{ *:[i1] } (VOP3Mods0:{ *:[f64] } f64:{ *:[f64] }:$src0, i32:{ *:[i32] }:$src0_modifiers, i1:{ *:[i1] }:$clamp), (VOP3Mods:{ *:[f64] } f64:{ *:[f64] }:$src1, i32:{ *:[i32] }:$src1_modifiers), SETUEQ:{ *:[Other] })  =>  (V_CMP_NLG_F64_e64:{ *:[i1] } i32:{ *:[i32] }:$src0_modifiers, f64:{ *:[f64] }:$src0, i32:{ *:[i32] }:$src1_modifiers, f64:{ *:[f64] }:$src1, i1:{ *:[i1] }:$clamp)
          GIR_BuildMI, /*InsnID*/0, /*Opcode*/GIMT_Encode2(AMDGPU::V_CMP_NLG_F64_e64),
          GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/0, // DstI[sdst]
          GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/1, // src0_modifiers
          GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/0, // src0
          GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(1), /*SubOperand*/1, // src1_modifiers
          GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(1), /*SubOperand*/0, // src1
          GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/2, // clamp
          GIR_ConstrainSelectedInstOperands, /*InsnID*/0,
          GIR_EraseFromParent, /*InsnID*/0,
          // GIR_Coverage, 259,
          GIR_Done,
        // Label 3930: @251185
        GIM_Try, /*On fail goto*//*Label 3931*/ GIMT_Encode4(251247), // Rule ID 260 //
          // MIs[0] Operand 1
          GIM_CheckCmpPredicate, /*MI*/0, /*Op*/1, /*Predicate*/GIMT_Encode2(CmpInst::FCMP_ULE),
          GIM_CheckComplexPattern, /*MI*/0, /*Op*/2, /*Renderer*/GIMT_Encode2(0), GIMT_Encode2(GICP_gi_vop3mods0),
          GIM_CheckComplexPattern, /*MI*/0, /*Op*/3, /*Renderer*/GIMT_Encode2(1), GIMT_Encode2(GICP_gi_vop3mods),
          // (setcc:{ *:[i1] } (VOP3Mods0:{ *:[f64] } f64:{ *:[f64] }:$src0, i32:{ *:[i32] }:$src0_modifiers, i1:{ *:[i1] }:$clamp), (VOP3Mods:{ *:[f64] } f64:{ *:[f64] }:$src1, i32:{ *:[i32] }:$src1_modifiers), SETULE:{ *:[Other] })  =>  (V_CMP_NGT_F64_e64:{ *:[i1] } i32:{ *:[i32] }:$src0_modifiers, f64:{ *:[f64] }:$src0, i32:{ *:[i32] }:$src1_modifiers, f64:{ *:[f64] }:$src1, i1:{ *:[i1] }:$clamp)
          GIR_BuildMI, /*InsnID*/0, /*Opcode*/GIMT_Encode2(AMDGPU::V_CMP_NGT_F64_e64),
          GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/0, // DstI[sdst]
          GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/1, // src0_modifiers
          GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/0, // src0
          GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(1), /*SubOperand*/1, // src1_modifiers
          GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(1), /*SubOperand*/0, // src1
          GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/2, // clamp
          GIR_ConstrainSelectedInstOperands, /*InsnID*/0,
          GIR_EraseFromParent, /*InsnID*/0,
          // GIR_Coverage, 260,
          GIR_Done,
        // Label 3931: @251247
        GIM_Try, /*On fail goto*//*Label 3932*/ GIMT_Encode4(251309), // Rule ID 261 //
          // MIs[0] Operand 1
          GIM_CheckCmpPredicate, /*MI*/0, /*Op*/1, /*Predicate*/GIMT_Encode2(CmpInst::FCMP_UGT),
          GIM_CheckComplexPattern, /*MI*/0, /*Op*/2, /*Renderer*/GIMT_Encode2(0), GIMT_Encode2(GICP_gi_vop3mods0),
          GIM_CheckComplexPattern, /*MI*/0, /*Op*/3, /*Renderer*/GIMT_Encode2(1), GIMT_Encode2(GICP_gi_vop3mods),
          // (setcc:{ *:[i1] } (VOP3Mods0:{ *:[f64] } f64:{ *:[f64] }:$src0, i32:{ *:[i32] }:$src0_modifiers, i1:{ *:[i1] }:$clamp), (VOP3Mods:{ *:[f64] } f64:{ *:[f64] }:$src1, i32:{ *:[i32] }:$src1_modifiers), SETUGT:{ *:[Other] })  =>  (V_CMP_NLE_F64_e64:{ *:[i1] } i32:{ *:[i32] }:$src0_modifiers, f64:{ *:[f64] }:$src0, i32:{ *:[i32] }:$src1_modifiers, f64:{ *:[f64] }:$src1, i1:{ *:[i1] }:$clamp)
          GIR_BuildMI, /*InsnID*/0, /*Opcode*/GIMT_Encode2(AMDGPU::V_CMP_NLE_F64_e64),
          GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/0, // DstI[sdst]
          GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/1, // src0_modifiers
          GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/0, // src0
          GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(1), /*SubOperand*/1, // src1_modifiers
          GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(1), /*SubOperand*/0, // src1
          GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/2, // clamp
          GIR_ConstrainSelectedInstOperands, /*InsnID*/0,
          GIR_EraseFromParent, /*InsnID*/0,
          // GIR_Coverage, 261,
          GIR_Done,
        // Label 3932: @251309
        GIM_Try, /*On fail goto*//*Label 3933*/ GIMT_Encode4(251371), // Rule ID 262 //
          // MIs[0] Operand 1
          GIM_CheckCmpPredicate, /*MI*/0, /*Op*/1, /*Predicate*/GIMT_Encode2(CmpInst::FCMP_UNE),
          GIM_CheckComplexPattern, /*MI*/0, /*Op*/2, /*Renderer*/GIMT_Encode2(0), GIMT_Encode2(GICP_gi_vop3mods0),
          GIM_CheckComplexPattern, /*MI*/0, /*Op*/3, /*Renderer*/GIMT_Encode2(1), GIMT_Encode2(GICP_gi_vop3mods),
          // (setcc:{ *:[i1] } (VOP3Mods0:{ *:[f64] } f64:{ *:[f64] }:$src0, i32:{ *:[i32] }:$src0_modifiers, i1:{ *:[i1] }:$clamp), (VOP3Mods:{ *:[f64] } f64:{ *:[f64] }:$src1, i32:{ *:[i32] }:$src1_modifiers), SETUNE:{ *:[Other] })  =>  (V_CMP_NEQ_F64_e64:{ *:[i1] } i32:{ *:[i32] }:$src0_modifiers, f64:{ *:[f64] }:$src0, i32:{ *:[i32] }:$src1_modifiers, f64:{ *:[f64] }:$src1, i1:{ *:[i1] }:$clamp)
          GIR_BuildMI, /*InsnID*/0, /*Opcode*/GIMT_Encode2(AMDGPU::V_CMP_NEQ_F64_e64),
          GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/0, // DstI[sdst]
          GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/1, // src0_modifiers
          GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/0, // src0
          GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(1), /*SubOperand*/1, // src1_modifiers
          GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(1), /*SubOperand*/0, // src1
          GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/2, // clamp
          GIR_ConstrainSelectedInstOperands, /*InsnID*/0,
          GIR_EraseFromParent, /*InsnID*/0,
          // GIR_Coverage, 262,
          GIR_Done,
        // Label 3933: @251371
        GIM_Try, /*On fail goto*//*Label 3934*/ GIMT_Encode4(251433), // Rule ID 263 //
          // MIs[0] Operand 1
          GIM_CheckCmpPredicate, /*MI*/0, /*Op*/1, /*Predicate*/GIMT_Encode2(CmpInst::FCMP_UGE),
          GIM_CheckComplexPattern, /*MI*/0, /*Op*/2, /*Renderer*/GIMT_Encode2(0), GIMT_Encode2(GICP_gi_vop3mods0),
          GIM_CheckComplexPattern, /*MI*/0, /*Op*/3, /*Renderer*/GIMT_Encode2(1), GIMT_Encode2(GICP_gi_vop3mods),
          // (setcc:{ *:[i1] } (VOP3Mods0:{ *:[f64] } f64:{ *:[f64] }:$src0, i32:{ *:[i32] }:$src0_modifiers, i1:{ *:[i1] }:$clamp), (VOP3Mods:{ *:[f64] } f64:{ *:[f64] }:$src1, i32:{ *:[i32] }:$src1_modifiers), SETUGE:{ *:[Other] })  =>  (V_CMP_NLT_F64_e64:{ *:[i1] } i32:{ *:[i32] }:$src0_modifiers, f64:{ *:[f64] }:$src0, i32:{ *:[i32] }:$src1_modifiers, f64:{ *:[f64] }:$src1, i1:{ *:[i1] }:$clamp)
          GIR_BuildMI, /*InsnID*/0, /*Opcode*/GIMT_Encode2(AMDGPU::V_CMP_NLT_F64_e64),
          GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/0, // DstI[sdst]
          GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/1, // src0_modifiers
          GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/0, // src0
          GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(1), /*SubOperand*/1, // src1_modifiers
          GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(1), /*SubOperand*/0, // src1
          GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/2, // clamp
          GIR_ConstrainSelectedInstOperands, /*InsnID*/0,
          GIR_EraseFromParent, /*InsnID*/0,
          // GIR_Coverage, 263,
          GIR_Done,
        // Label 3934: @251433
        GIM_Reject,
      // Label 3920: @251434
      GIM_Reject,
      // Label 3875: @251435
      GIM_Reject,
    // Label 3871: @251436
    GIM_Reject,
    // Label 49: @251437
    GIM_SwitchType, /*MI*/0, /*Op*/0, /*[*/GIMT_Encode2(8), GIMT_Encode2(10), /*)*//*default:*//*Label 3937*/ GIMT_Encode4(251688),
    /*GILLT_s16*//*Label 3935*/ GIMT_Encode4(251456),
    /*GILLT_s32*//*Label 3936*/ GIMT_Encode4(251552),
    // Label 3935: @251456
    GIM_Try, /*On fail goto*//*Label 3938*/ GIMT_Encode4(251551),
      GIM_CheckType, /*MI*/0, /*Op*/1, /*Type*/GILLT_s1,
      GIM_CheckType, /*MI*/0, /*Op*/2, /*Type*/GILLT_s16,
      GIM_CheckType, /*MI*/0, /*Op*/3, /*Type*/GILLT_s16,
      GIM_CheckRegBankForClass, /*MI*/0, /*Op*/0, /*RC*/GIMT_Encode2(AMDGPU::VGPR_32RegClassID),
      GIM_Try, /*On fail goto*//*Label 3939*/ GIMT_Encode4(251514), // Rule ID 5899 //
        // (select:{ *:[f16] } i1:{ *:[i1] }:$src0, f16:{ *:[f16] }:$src1, f16:{ *:[f16] }:$src2)  =>  (V_CNDMASK_B32_e64:{ *:[f16] } 0:{ *:[i32] }, VSrc_b32:{ *:[f16] }:$src2, 0:{ *:[i32] }, VSrc_b32:{ *:[f16] }:$src1, SSrc_i1:{ *:[i1] }:$src0)
        GIR_BuildMI, /*InsnID*/0, /*Opcode*/GIMT_Encode2(AMDGPU::V_CNDMASK_B32_e64),
        GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/0, // DstI[vdst]
        GIR_AddImm8, /*InsnID*/0, /*Imm*/0,
        GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/3, // src2
        GIR_AddImm8, /*InsnID*/0, /*Imm*/0,
        GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/2, // src1
        GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/1, // src0
        GIR_ConstrainSelectedInstOperands, /*InsnID*/0,
        GIR_EraseFromParent, /*InsnID*/0,
        // GIR_Coverage, 5899,
        GIR_Done,
      // Label 3939: @251514
      GIM_Try, /*On fail goto*//*Label 3940*/ GIMT_Encode4(251550), // Rule ID 5900 //
        // (select:{ *:[i16] } i1:{ *:[i1] }:$src0, i16:{ *:[i16] }:$src1, i16:{ *:[i16] }:$src2)  =>  (V_CNDMASK_B32_e64:{ *:[i16] } 0:{ *:[i32] }, VSrc_b32:{ *:[i16] }:$src2, 0:{ *:[i32] }, VSrc_b32:{ *:[i16] }:$src1, SSrc_i1:{ *:[i1] }:$src0)
        GIR_BuildMI, /*InsnID*/0, /*Opcode*/GIMT_Encode2(AMDGPU::V_CNDMASK_B32_e64),
        GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/0, // DstI[vdst]
        GIR_AddImm8, /*InsnID*/0, /*Imm*/0,
        GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/3, // src2
        GIR_AddImm8, /*InsnID*/0, /*Imm*/0,
        GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/2, // src1
        GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/1, // src0
        GIR_ConstrainSelectedInstOperands, /*InsnID*/0,
        GIR_EraseFromParent, /*InsnID*/0,
        // GIR_Coverage, 5900,
        GIR_Done,
      // Label 3940: @251550
      GIM_Reject,
    // Label 3938: @251551
    GIM_Reject,
    // Label 3936: @251552
    GIM_Try, /*On fail goto*//*Label 3941*/ GIMT_Encode4(251687),
      GIM_CheckType, /*MI*/0, /*Op*/1, /*Type*/GILLT_s1,
      GIM_CheckType, /*MI*/0, /*Op*/2, /*Type*/GILLT_s32,
      GIM_CheckType, /*MI*/0, /*Op*/3, /*Type*/GILLT_s32,
      GIM_CheckRegBankForClass, /*MI*/0, /*Op*/0, /*RC*/GIMT_Encode2(AMDGPU::VGPR_32RegClassID),
      GIM_Try, /*On fail goto*//*Label 3942*/ GIMT_Encode4(251630), // Rule ID 5897 //
        GIM_CheckComplexPattern, /*MI*/0, /*Op*/2, /*Renderer*/GIMT_Encode2(0), GIMT_Encode2(GICP_gi_vop3modsnoncanonicalizing),
        GIM_CheckComplexPattern, /*MI*/0, /*Op*/3, /*Renderer*/GIMT_Encode2(1), GIMT_Encode2(GICP_gi_vop3modsnoncanonicalizing),
        // (select:{ *:[i32] } i1:{ *:[i1] }:$src0, (VOP3ModsNonCanonicalizing:{ *:[i32] } i32:{ *:[i32] }:$src1, i32:{ *:[i32] }:$src1_mods), (VOP3ModsNonCanonicalizing:{ *:[i32] } i32:{ *:[i32] }:$src2, i32:{ *:[i32] }:$src2_mods))  =>  (V_CNDMASK_B32_e64:{ *:[i32] } FP32InputMods:{ *:[i32] }:$src2_mods, VSrc_b32:{ *:[i32] }:$src2, FP32InputMods:{ *:[i32] }:$src1_mods, VSrc_b32:{ *:[i32] }:$src1, SSrc_i1:{ *:[i1] }:$src0)
        GIR_BuildMI, /*InsnID*/0, /*Opcode*/GIMT_Encode2(AMDGPU::V_CNDMASK_B32_e64),
        GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/0, // DstI[vdst]
        GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(1), /*SubOperand*/1, // src2_mods
        GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(1), /*SubOperand*/0, // src2
        GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/1, // src1_mods
        GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/0, // src1
        GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/1, // src0
        GIR_ConstrainSelectedInstOperands, /*InsnID*/0,
        GIR_EraseFromParent, /*InsnID*/0,
        // GIR_Coverage, 5897,
        GIR_Done,
      // Label 3942: @251630
      GIM_Try, /*On fail goto*//*Label 3943*/ GIMT_Encode4(251686), // Rule ID 5898 //
        GIM_CheckComplexPattern, /*MI*/0, /*Op*/2, /*Renderer*/GIMT_Encode2(0), GIMT_Encode2(GICP_gi_vop3modsnoncanonicalizing),
        GIM_CheckComplexPattern, /*MI*/0, /*Op*/3, /*Renderer*/GIMT_Encode2(1), GIMT_Encode2(GICP_gi_vop3modsnoncanonicalizing),
        // (select:{ *:[f32] } i1:{ *:[i1] }:$src0, (VOP3ModsNonCanonicalizing:{ *:[f32] } f32:{ *:[f32] }:$src1, i32:{ *:[i32] }:$src1_mods), (VOP3ModsNonCanonicalizing:{ *:[f32] } f32:{ *:[f32] }:$src2, i32:{ *:[i32] }:$src2_mods))  =>  (V_CNDMASK_B32_e64:{ *:[f32] } FP32InputMods:{ *:[i32] }:$src2_mods, VSrc_b32:{ *:[f32] }:$src2, FP32InputMods:{ *:[i32] }:$src1_mods, VSrc_b32:{ *:[f32] }:$src1, SSrc_i1:{ *:[i1] }:$src0)
        GIR_BuildMI, /*InsnID*/0, /*Opcode*/GIMT_Encode2(AMDGPU::V_CNDMASK_B32_e64),
        GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/0, // DstI[vdst]
        GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(1), /*SubOperand*/1, // src2_mods
        GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(1), /*SubOperand*/0, // src2
        GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/1, // src1_mods
        GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/0, // src1
        GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/1, // src0
        GIR_ConstrainSelectedInstOperands, /*InsnID*/0,
        GIR_EraseFromParent, /*InsnID*/0,
        // GIR_Coverage, 5898,
        GIR_Done,
      // Label 3943: @251686
      GIM_Reject,
    // Label 3941: @251687
    GIM_Reject,
    // Label 3937: @251688
    GIM_Reject,
    // Label 50: @251689
    GIM_Try, /*On fail goto*//*Label 3944*/ GIMT_Encode4(251821),
      GIM_CheckType, /*MI*/0, /*Op*/0, /*Type*/GILLT_s32,
      GIM_CheckType, /*MI*/0, /*Op*/1, /*Type*/GILLT_s32,
      GIM_CheckType, /*MI*/0, /*Op*/2, /*Type*/GILLT_s32,
      GIM_Try, /*On fail goto*//*Label 3945*/ GIMT_Encode4(251741), // Rule ID 88 //
        GIM_CheckFeatures, GIMT_Encode2(GIFBS_isGFX9Plus),
        GIM_CheckRegBankForClass, /*MI*/0, /*Op*/0, /*RC*/GIMT_Encode2(AMDGPU::SReg_32RegClassID),
        GIM_CheckRegBankForClass, /*MI*/0, /*Op*/1, /*RC*/GIMT_Encode2(AMDGPU::SReg_32RegClassID),
        GIM_CheckRegBankForClass, /*MI*/0, /*Op*/2, /*RC*/GIMT_Encode2(AMDGPU::SReg_32RegClassID),
        GIM_CheckCxxInsnPredicate, /*MI*/0, /*FnId*/GIMT_Encode2(GICXXPred_MI_Predicate_anonymous_17628),
        // (mulhu:{ *:[i32] } SSrc_b32:{ *:[i32] }:$src0, SSrc_b32:{ *:[i32] }:$src1)<<P:Predicate_anonymous_17628>>  =>  (S_MUL_HI_U32:{ *:[i32] } SSrc_b32:{ *:[i32] }:$src0, SSrc_b32:{ *:[i32] }:$src1)
        GIR_MutateOpcode, /*InsnID*/0, /*RecycleInsnID*/0, /*Opcode*/GIMT_Encode2(AMDGPU::S_MUL_HI_U32),
        GIR_ConstrainSelectedInstOperands, /*InsnID*/0,
        // GIR_Coverage, 88,
        GIR_Done,
      // Label 3945: @251741
      GIM_Try, /*On fail goto*//*Label 3946*/ GIMT_Encode4(251820),
        GIM_CheckRegBankForClass, /*MI*/0, /*Op*/0, /*RC*/GIMT_Encode2(AMDGPU::VGPR_32RegClassID),
        GIM_Try, /*On fail goto*//*Label 3947*/ GIMT_Encode4(251785), // Rule ID 866 //
          GIM_CheckComplexPattern, /*MI*/0, /*Op*/1, /*Renderer*/GIMT_Encode2(0), GIMT_Encode2(GICP_gi_vop3mods0),
          // (mulhu:{ *:[i32] } (VOP3Mods0:{ *:[i32] } i32:{ *:[i32] }:$src0), i32:{ *:[i32] }:$src1)  =>  (V_MUL_HI_U32_e64:{ *:[i32] } i32:{ *:[i32] }:$src0, i32:{ *:[i32] }:$src1)
          GIR_BuildMI, /*InsnID*/0, /*Opcode*/GIMT_Encode2(AMDGPU::V_MUL_HI_U32_e64),
          GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/0, // DstI[vdst]
          GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/0, // src0
          GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/2, // src1
          GIR_ConstrainSelectedInstOperands, /*InsnID*/0,
          GIR_EraseFromParent, /*InsnID*/0,
          // GIR_Coverage, 866,
          GIR_Done,
        // Label 3947: @251785
        GIM_Try, /*On fail goto*//*Label 3948*/ GIMT_Encode4(251819), // Rule ID 7184 //
          GIM_CheckComplexPattern, /*MI*/0, /*Op*/2, /*Renderer*/GIMT_Encode2(0), GIMT_Encode2(GICP_gi_vop3mods0),
          // (mulhu:{ *:[i32] } i32:{ *:[i32] }:$src1, (VOP3Mods0:{ *:[i32] } i32:{ *:[i32] }:$src0))  =>  (V_MUL_HI_U32_e64:{ *:[i32] } i32:{ *:[i32] }:$src0, i32:{ *:[i32] }:$src1)
          GIR_BuildMI, /*InsnID*/0, /*Opcode*/GIMT_Encode2(AMDGPU::V_MUL_HI_U32_e64),
          GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/0, // DstI[vdst]
          GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/0, // src0
          GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/1, // src1
          GIR_ConstrainSelectedInstOperands, /*InsnID*/0,
          GIR_EraseFromParent, /*InsnID*/0,
          // GIR_Coverage, 7184,
          GIR_Done,
        // Label 3948: @251819
        GIM_Reject,
      // Label 3946: @251820
      GIM_Reject,
    // Label 3944: @251821
    GIM_Reject,
    // Label 51: @251822
    GIM_Try, /*On fail goto*//*Label 3949*/ GIMT_Encode4(251954),
      GIM_CheckType, /*MI*/0, /*Op*/0, /*Type*/GILLT_s32,
      GIM_CheckType, /*MI*/0, /*Op*/1, /*Type*/GILLT_s32,
      GIM_CheckType, /*MI*/0, /*Op*/2, /*Type*/GILLT_s32,
      GIM_Try, /*On fail goto*//*Label 3950*/ GIMT_Encode4(251874), // Rule ID 89 //
        GIM_CheckFeatures, GIMT_Encode2(GIFBS_isGFX9Plus),
        GIM_CheckRegBankForClass, /*MI*/0, /*Op*/0, /*RC*/GIMT_Encode2(AMDGPU::SReg_32RegClassID),
        GIM_CheckRegBankForClass, /*MI*/0, /*Op*/1, /*RC*/GIMT_Encode2(AMDGPU::SReg_32RegClassID),
        GIM_CheckRegBankForClass, /*MI*/0, /*Op*/2, /*RC*/GIMT_Encode2(AMDGPU::SReg_32RegClassID),
        GIM_CheckCxxInsnPredicate, /*MI*/0, /*FnId*/GIMT_Encode2(GICXXPred_MI_Predicate_anonymous_17629),
        // (mulhs:{ *:[i32] } SSrc_b32:{ *:[i32] }:$src0, SSrc_b32:{ *:[i32] }:$src1)<<P:Predicate_anonymous_17629>>  =>  (S_MUL_HI_I32:{ *:[i32] } SSrc_b32:{ *:[i32] }:$src0, SSrc_b32:{ *:[i32] }:$src1)
        GIR_MutateOpcode, /*InsnID*/0, /*RecycleInsnID*/0, /*Opcode*/GIMT_Encode2(AMDGPU::S_MUL_HI_I32),
        GIR_ConstrainSelectedInstOperands, /*InsnID*/0,
        // GIR_Coverage, 89,
        GIR_Done,
      // Label 3950: @251874
      GIM_Try, /*On fail goto*//*Label 3951*/ GIMT_Encode4(251953),
        GIM_CheckRegBankForClass, /*MI*/0, /*Op*/0, /*RC*/GIMT_Encode2(AMDGPU::VGPR_32RegClassID),
        GIM_Try, /*On fail goto*//*Label 3952*/ GIMT_Encode4(251918), // Rule ID 867 //
          GIM_CheckComplexPattern, /*MI*/0, /*Op*/1, /*Renderer*/GIMT_Encode2(0), GIMT_Encode2(GICP_gi_vop3mods0),
          // (mulhs:{ *:[i32] } (VOP3Mods0:{ *:[i32] } i32:{ *:[i32] }:$src0), i32:{ *:[i32] }:$src1)  =>  (V_MUL_HI_I32_e64:{ *:[i32] } i32:{ *:[i32] }:$src0, i32:{ *:[i32] }:$src1)
          GIR_BuildMI, /*InsnID*/0, /*Opcode*/GIMT_Encode2(AMDGPU::V_MUL_HI_I32_e64),
          GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/0, // DstI[vdst]
          GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/0, // src0
          GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/2, // src1
          GIR_ConstrainSelectedInstOperands, /*InsnID*/0,
          GIR_EraseFromParent, /*InsnID*/0,
          // GIR_Coverage, 867,
          GIR_Done,
        // Label 3952: @251918
        GIM_Try, /*On fail goto*//*Label 3953*/ GIMT_Encode4(251952), // Rule ID 7185 //
          GIM_CheckComplexPattern, /*MI*/0, /*Op*/2, /*Renderer*/GIMT_Encode2(0), GIMT_Encode2(GICP_gi_vop3mods0),
          // (mulhs:{ *:[i32] } i32:{ *:[i32] }:$src1, (VOP3Mods0:{ *:[i32] } i32:{ *:[i32] }:$src0))  =>  (V_MUL_HI_I32_e64:{ *:[i32] } i32:{ *:[i32] }:$src0, i32:{ *:[i32] }:$src1)
          GIR_BuildMI, /*InsnID*/0, /*Opcode*/GIMT_Encode2(AMDGPU::V_MUL_HI_I32_e64),
          GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/0, // DstI[vdst]
          GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/0, // src0
          GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/1, // src1
          GIR_ConstrainSelectedInstOperands, /*InsnID*/0,
          GIR_EraseFromParent, /*InsnID*/0,
          // GIR_Coverage, 7185,
          GIR_Done,
        // Label 3953: @251952
        GIM_Reject,
      // Label 3951: @251953
      GIM_Reject,
    // Label 3949: @251954
    GIM_Reject,
    // Label 52: @251955
    GIM_SwitchType, /*MI*/0, /*Op*/0, /*[*/GIMT_Encode2(8), GIMT_Encode2(12), /*)*//*default:*//*Label 3957*/ GIMT_Encode4(252271),
    /*GILLT_s16*//*Label 3954*/ GIMT_Encode4(251982),
    /*GILLT_s32*//*Label 3955*/ GIMT_Encode4(252095), GIMT_Encode4(0),
    /*GILLT_v2s16*//*Label 3956*/ GIMT_Encode4(252187),
    // Label 3954: @251982
    GIM_Try, /*On fail goto*//*Label 3958*/ GIMT_Encode4(252094),
      GIM_CheckType, /*MI*/0, /*Op*/1, /*Type*/GILLT_s16,
      GIM_CheckType, /*MI*/0, /*Op*/2, /*Type*/GILLT_s16,
      GIM_CheckRegBankForClass, /*MI*/0, /*Op*/0, /*RC*/GIMT_Encode2(AMDGPU::VGPR_32RegClassID),
      GIM_Try, /*On fail goto*//*Label 3959*/ GIMT_Encode4(252061), // Rule ID 2213 //
        GIM_CheckFeatures, GIMT_Encode2(GIFBS_isGFX10Plus),
        GIM_CheckComplexPattern, /*MI*/0, /*Op*/1, /*Renderer*/GIMT_Encode2(0), GIMT_Encode2(GICP_gi_vop3opsel),
        GIM_CheckComplexPattern, /*MI*/0, /*Op*/2, /*Renderer*/GIMT_Encode2(1), GIMT_Encode2(GICP_gi_vop3opsel),
        // (uaddsat:{ *:[i16] } (VOP3OpSel:{ *:[i16] } i16:{ *:[i16] }:$src0, i32:{ *:[i32] }:$src0_modifiers), (VOP3OpSel:{ *:[i16] } i16:{ *:[i16] }:$src1, i32:{ *:[i32] }:$src1_modifiers))  =>  (V_ADD_NC_U16_e64:{ *:[i16] } ?:{ *:[i32] }:$src0_modifiers, ?:{ *:[i16] }:$src0, ?:{ *:[i32] }:$src1_modifiers, ?:{ *:[i16] }:$src1, 1:{ *:[i1] }, 0:{ *:[i32] })
        GIR_BuildMI, /*InsnID*/0, /*Opcode*/GIMT_Encode2(AMDGPU::V_ADD_NC_U16_e64),
        GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/0, // DstI[vdst]
        GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/1, // src0_modifiers
        GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/0, // src0
        GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(1), /*SubOperand*/1, // src1_modifiers
        GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(1), /*SubOperand*/0, // src1
        GIR_AddImm8, /*InsnID*/0, /*Imm*/1,
        GIR_AddImm8, /*InsnID*/0, /*Imm*/0,
        GIR_ConstrainSelectedInstOperands, /*InsnID*/0,
        GIR_EraseFromParent, /*InsnID*/0,
        // GIR_Coverage, 2213,
        GIR_Done,
      // Label 3959: @252061
      GIM_Try, /*On fail goto*//*Label 3960*/ GIMT_Encode4(252093), // Rule ID 2165 //
        GIM_CheckFeatures, GIMT_Encode2(GIFBS_Has16BitInsts_HasIntClamp),
        // (uaddsat:{ *:[i16] } i16:{ *:[i16] }:$src0, i16:{ *:[i16] }:$src1)  =>  (V_ADD_U16_e64:{ *:[i16] } VSrc_b16:{ *:[i16] }:$src0, VSrc_b16:{ *:[i16] }:$src1, 1:{ *:[i1] })
        GIR_BuildMI, /*InsnID*/0, /*Opcode*/GIMT_Encode2(AMDGPU::V_ADD_U16_e64),
        GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/0, // DstI[vdst]
        GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/1, // src0
        GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/2, // src1
        GIR_AddImm8, /*InsnID*/0, /*Imm*/1,
        GIR_ConstrainSelectedInstOperands, /*InsnID*/0,
        GIR_EraseFromParent, /*InsnID*/0,
        // GIR_Coverage, 2165,
        GIR_Done,
      // Label 3960: @252093
      GIM_Reject,
    // Label 3958: @252094
    GIM_Reject,
    // Label 3955: @252095
    GIM_Try, /*On fail goto*//*Label 3961*/ GIMT_Encode4(252186),
      GIM_CheckType, /*MI*/0, /*Op*/1, /*Type*/GILLT_s32,
      GIM_CheckType, /*MI*/0, /*Op*/2, /*Type*/GILLT_s32,
      GIM_CheckRegBankForClass, /*MI*/0, /*Op*/0, /*RC*/GIMT_Encode2(AMDGPU::VGPR_32RegClassID),
      GIM_Try, /*On fail goto*//*Label 3962*/ GIMT_Encode4(252145), // Rule ID 2163 //
        GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasAddNoCarryInsts_HasIntClamp),
        // (uaddsat:{ *:[i32] } i32:{ *:[i32] }:$src0, i32:{ *:[i32] }:$src1)  =>  (V_ADD_U32_e64:{ *:[i32] } VSrc_b32:{ *:[i32] }:$src0, VSrc_b32:{ *:[i32] }:$src1, 1:{ *:[i1] })
        GIR_BuildMI, /*InsnID*/0, /*Opcode*/GIMT_Encode2(AMDGPU::V_ADD_U32_e64),
        GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/0, // DstI[vdst]
        GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/1, // src0
        GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/2, // src1
        GIR_AddImm8, /*InsnID*/0, /*Imm*/1,
        GIR_ConstrainSelectedInstOperands, /*InsnID*/0,
        GIR_EraseFromParent, /*InsnID*/0,
        // GIR_Coverage, 2163,
        GIR_Done,
      // Label 3962: @252145
      GIM_Try, /*On fail goto*//*Label 3963*/ GIMT_Encode4(252185), // Rule ID 2161 //
        GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasIntClamp),
        // (uaddsat:{ *:[i32] } i32:{ *:[i32] }:$src0, i32:{ *:[i32] }:$src1)  =>  (V_ADD_CO_U32_e64:{ *:[i32] }:{ *:[i1] } VSrc_b32:{ *:[i32] }:$src0, VSrc_b32:{ *:[i32] }:$src1, 1:{ *:[i1] })
        GIR_MakeTempReg, /*TempRegID*/0, /*TypeID*/GILLT_s1,
        GIR_BuildMI, /*InsnID*/0, /*Opcode*/GIMT_Encode2(AMDGPU::V_ADD_CO_U32_e64),
        GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/0, // DstI[vdst]
        GIR_AddTempRegister, /*InsnID*/0, /*TempRegID*/0, /*TempRegFlags*/GIMT_Encode2(RegState::Define|RegState::Dead),
        GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/1, // src0
        GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/2, // src1
        GIR_AddImm8, /*InsnID*/0, /*Imm*/1,
        GIR_ConstrainSelectedInstOperands, /*InsnID*/0,
        GIR_EraseFromParent, /*InsnID*/0,
        // GIR_Coverage, 2161,
        GIR_Done,
      // Label 3963: @252185
      GIM_Reject,
    // Label 3961: @252186
    GIM_Reject,
    // Label 3956: @252187
    GIM_Try, /*On fail goto*//*Label 3964*/ GIMT_Encode4(252270), // Rule ID 2245 //
      GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasVOP3PInsts),
      GIM_CheckType, /*MI*/0, /*Op*/1, /*Type*/GILLT_v2s16,
      GIM_CheckType, /*MI*/0, /*Op*/2, /*Type*/GILLT_v2s16,
      GIM_CheckRegBankForClass, /*MI*/0, /*Op*/0, /*RC*/GIMT_Encode2(AMDGPU::VGPR_32RegClassID),
      GIM_CheckComplexPattern, /*MI*/0, /*Op*/1, /*Renderer*/GIMT_Encode2(0), GIMT_Encode2(GICP_gi_vop3pmods),
      GIM_CheckComplexPattern, /*MI*/0, /*Op*/2, /*Renderer*/GIMT_Encode2(1), GIMT_Encode2(GICP_gi_vop3pmods),
      // (uaddsat:{ *:[v2i16] } (VOP3PMods:{ *:[v2i16] } v2i16:{ *:[v2i16] }:$src0, i32:{ *:[i32] }:$src0_modifiers), (VOP3PMods:{ *:[v2i16] } v2i16:{ *:[v2i16] }:$src1, i32:{ *:[i32] }:$src1_modifiers))  =>  (V_PK_ADD_U16:{ *:[v2i16] } ?:{ *:[i32] }:$src0_modifiers, ?:{ *:[v2i16] }:$src0, ?:{ *:[i32] }:$src1_modifiers, ?:{ *:[v2i16] }:$src1, 1:{ *:[i1] })
      GIR_BuildMI, /*InsnID*/0, /*Opcode*/GIMT_Encode2(AMDGPU::V_PK_ADD_U16),
      GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/0, // DstI[vdst]
      GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/1, // src0_modifiers
      GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/0, // src0
      GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(1), /*SubOperand*/1, // src1_modifiers
      GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(1), /*SubOperand*/0, // src1
      GIR_AddImm8, /*InsnID*/0, /*Imm*/1,
      GIR_AddImm8, /*InsnID*/0, /*Imm*/0,
      GIR_AddImm8, /*InsnID*/0, /*Imm*/0,
      GIR_AddImm8, /*InsnID*/0, /*Imm*/0,
      GIR_AddImm8, /*InsnID*/0, /*Imm*/0,
      GIR_ConstrainSelectedInstOperands, /*InsnID*/0,
      GIR_EraseFromParent, /*InsnID*/0,
      // GIR_Coverage, 2245,
      GIR_Done,
    // Label 3964: @252270
    GIM_Reject,
    // Label 3957: @252271
    GIM_Reject,
    // Label 53: @252272
    GIM_SwitchType, /*MI*/0, /*Op*/0, /*[*/GIMT_Encode2(8), GIMT_Encode2(12), /*)*//*default:*//*Label 3968*/ GIMT_Encode4(252504),
    /*GILLT_s16*//*Label 3965*/ GIMT_Encode4(252299),
    /*GILLT_s32*//*Label 3966*/ GIMT_Encode4(252374), GIMT_Encode4(0),
    /*GILLT_v2s16*//*Label 3967*/ GIMT_Encode4(252420),
    // Label 3965: @252299
    GIM_Try, /*On fail goto*//*Label 3969*/ GIMT_Encode4(252373), // Rule ID 2200 //
      GIM_CheckFeatures, GIMT_Encode2(GIFBS_isGFX9Plus),
      GIM_CheckType, /*MI*/0, /*Op*/1, /*Type*/GILLT_s16,
      GIM_CheckType, /*MI*/0, /*Op*/2, /*Type*/GILLT_s16,
      GIM_CheckRegBankForClass, /*MI*/0, /*Op*/0, /*RC*/GIMT_Encode2(AMDGPU::VGPR_32RegClassID),
      GIM_CheckComplexPattern, /*MI*/0, /*Op*/1, /*Renderer*/GIMT_Encode2(0), GIMT_Encode2(GICP_gi_vop3opsel),
      GIM_CheckComplexPattern, /*MI*/0, /*Op*/2, /*Renderer*/GIMT_Encode2(1), GIMT_Encode2(GICP_gi_vop3opsel),
      // (saddsat:{ *:[i16] } (VOP3OpSel:{ *:[i16] } i16:{ *:[i16] }:$src0, i32:{ *:[i32] }:$src0_modifiers), (VOP3OpSel:{ *:[i16] } i16:{ *:[i16] }:$src1, i32:{ *:[i32] }:$src1_modifiers))  =>  (V_ADD_I16_e64:{ *:[i16] } ?:{ *:[i32] }:$src0_modifiers, ?:{ *:[i16] }:$src0, ?:{ *:[i32] }:$src1_modifiers, ?:{ *:[i16] }:$src1, 1:{ *:[i1] }, 0:{ *:[i32] })
      GIR_BuildMI, /*InsnID*/0, /*Opcode*/GIMT_Encode2(AMDGPU::V_ADD_I16_e64),
      GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/0, // DstI[vdst]
      GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/1, // src0_modifiers
      GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/0, // src0
      GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(1), /*SubOperand*/1, // src1_modifiers
      GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(1), /*SubOperand*/0, // src1
      GIR_AddImm8, /*InsnID*/0, /*Imm*/1,
      GIR_AddImm8, /*InsnID*/0, /*Imm*/0,
      GIR_ConstrainSelectedInstOperands, /*InsnID*/0,
      GIR_EraseFromParent, /*InsnID*/0,
      // GIR_Coverage, 2200,
      GIR_Done,
    // Label 3969: @252373
    GIM_Reject,
    // Label 3966: @252374
    GIM_Try, /*On fail goto*//*Label 3970*/ GIMT_Encode4(252419), // Rule ID 2197 //
      GIM_CheckFeatures, GIMT_Encode2(GIFBS_isGFX9Plus),
      GIM_CheckType, /*MI*/0, /*Op*/1, /*Type*/GILLT_s32,
      GIM_CheckType, /*MI*/0, /*Op*/2, /*Type*/GILLT_s32,
      GIM_CheckRegBankForClass, /*MI*/0, /*Op*/0, /*RC*/GIMT_Encode2(AMDGPU::VGPR_32RegClassID),
      // (saddsat:{ *:[i32] } i32:{ *:[i32] }:$src0, i32:{ *:[i32] }:$src1)  =>  (V_ADD_I32_e64:{ *:[i32] } VSrc_b32:{ *:[i32] }:$src0, VSrc_b32:{ *:[i32] }:$src1, 1:{ *:[i1] })
      GIR_BuildMI, /*InsnID*/0, /*Opcode*/GIMT_Encode2(AMDGPU::V_ADD_I32_e64),
      GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/0, // DstI[vdst]
      GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/1, // src0
      GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/2, // src1
      GIR_AddImm8, /*InsnID*/0, /*Imm*/1,
      GIR_ConstrainSelectedInstOperands, /*InsnID*/0,
      GIR_EraseFromParent, /*InsnID*/0,
      // GIR_Coverage, 2197,
      GIR_Done,
    // Label 3970: @252419
    GIM_Reject,
    // Label 3967: @252420
    GIM_Try, /*On fail goto*//*Label 3971*/ GIMT_Encode4(252503), // Rule ID 2246 //
      GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasVOP3PInsts),
      GIM_CheckType, /*MI*/0, /*Op*/1, /*Type*/GILLT_v2s16,
      GIM_CheckType, /*MI*/0, /*Op*/2, /*Type*/GILLT_v2s16,
      GIM_CheckRegBankForClass, /*MI*/0, /*Op*/0, /*RC*/GIMT_Encode2(AMDGPU::VGPR_32RegClassID),
      GIM_CheckComplexPattern, /*MI*/0, /*Op*/1, /*Renderer*/GIMT_Encode2(0), GIMT_Encode2(GICP_gi_vop3pmods),
      GIM_CheckComplexPattern, /*MI*/0, /*Op*/2, /*Renderer*/GIMT_Encode2(1), GIMT_Encode2(GICP_gi_vop3pmods),
      // (saddsat:{ *:[v2i16] } (VOP3PMods:{ *:[v2i16] } v2i16:{ *:[v2i16] }:$src0, i32:{ *:[i32] }:$src0_modifiers), (VOP3PMods:{ *:[v2i16] } v2i16:{ *:[v2i16] }:$src1, i32:{ *:[i32] }:$src1_modifiers))  =>  (V_PK_ADD_I16:{ *:[v2i16] } ?:{ *:[i32] }:$src0_modifiers, ?:{ *:[v2i16] }:$src0, ?:{ *:[i32] }:$src1_modifiers, ?:{ *:[v2i16] }:$src1, 1:{ *:[i1] })
      GIR_BuildMI, /*InsnID*/0, /*Opcode*/GIMT_Encode2(AMDGPU::V_PK_ADD_I16),
      GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/0, // DstI[vdst]
      GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/1, // src0_modifiers
      GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/0, // src0
      GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(1), /*SubOperand*/1, // src1_modifiers
      GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(1), /*SubOperand*/0, // src1
      GIR_AddImm8, /*InsnID*/0, /*Imm*/1,
      GIR_AddImm8, /*InsnID*/0, /*Imm*/0,
      GIR_AddImm8, /*InsnID*/0, /*Imm*/0,
      GIR_AddImm8, /*InsnID*/0, /*Imm*/0,
      GIR_AddImm8, /*InsnID*/0, /*Imm*/0,
      GIR_ConstrainSelectedInstOperands, /*InsnID*/0,
      GIR_EraseFromParent, /*InsnID*/0,
      // GIR_Coverage, 2246,
      GIR_Done,
    // Label 3971: @252503
    GIM_Reject,
    // Label 3968: @252504
    GIM_Reject,
    // Label 54: @252505
    GIM_SwitchType, /*MI*/0, /*Op*/0, /*[*/GIMT_Encode2(8), GIMT_Encode2(12), /*)*//*default:*//*Label 3975*/ GIMT_Encode4(252821),
    /*GILLT_s16*//*Label 3972*/ GIMT_Encode4(252532),
    /*GILLT_s32*//*Label 3973*/ GIMT_Encode4(252645), GIMT_Encode4(0),
    /*GILLT_v2s16*//*Label 3974*/ GIMT_Encode4(252737),
    // Label 3972: @252532
    GIM_Try, /*On fail goto*//*Label 3976*/ GIMT_Encode4(252644),
      GIM_CheckType, /*MI*/0, /*Op*/1, /*Type*/GILLT_s16,
      GIM_CheckType, /*MI*/0, /*Op*/2, /*Type*/GILLT_s16,
      GIM_CheckRegBankForClass, /*MI*/0, /*Op*/0, /*RC*/GIMT_Encode2(AMDGPU::VGPR_32RegClassID),
      GIM_Try, /*On fail goto*//*Label 3977*/ GIMT_Encode4(252611), // Rule ID 2214 //
        GIM_CheckFeatures, GIMT_Encode2(GIFBS_isGFX10Plus),
        GIM_CheckComplexPattern, /*MI*/0, /*Op*/1, /*Renderer*/GIMT_Encode2(0), GIMT_Encode2(GICP_gi_vop3opsel),
        GIM_CheckComplexPattern, /*MI*/0, /*Op*/2, /*Renderer*/GIMT_Encode2(1), GIMT_Encode2(GICP_gi_vop3opsel),
        // (usubsat:{ *:[i16] } (VOP3OpSel:{ *:[i16] } i16:{ *:[i16] }:$src0, i32:{ *:[i32] }:$src0_modifiers), (VOP3OpSel:{ *:[i16] } i16:{ *:[i16] }:$src1, i32:{ *:[i32] }:$src1_modifiers))  =>  (V_SUB_NC_U16_e64:{ *:[i16] } ?:{ *:[i32] }:$src0_modifiers, ?:{ *:[i16] }:$src0, ?:{ *:[i32] }:$src1_modifiers, ?:{ *:[i16] }:$src1, 1:{ *:[i1] }, 0:{ *:[i32] })
        GIR_BuildMI, /*InsnID*/0, /*Opcode*/GIMT_Encode2(AMDGPU::V_SUB_NC_U16_e64),
        GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/0, // DstI[vdst]
        GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/1, // src0_modifiers
        GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/0, // src0
        GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(1), /*SubOperand*/1, // src1_modifiers
        GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(1), /*SubOperand*/0, // src1
        GIR_AddImm8, /*InsnID*/0, /*Imm*/1,
        GIR_AddImm8, /*InsnID*/0, /*Imm*/0,
        GIR_ConstrainSelectedInstOperands, /*InsnID*/0,
        GIR_EraseFromParent, /*InsnID*/0,
        // GIR_Coverage, 2214,
        GIR_Done,
      // Label 3977: @252611
      GIM_Try, /*On fail goto*//*Label 3978*/ GIMT_Encode4(252643), // Rule ID 2166 //
        GIM_CheckFeatures, GIMT_Encode2(GIFBS_Has16BitInsts_HasIntClamp),
        // (usubsat:{ *:[i16] } i16:{ *:[i16] }:$src0, i16:{ *:[i16] }:$src1)  =>  (V_SUB_U16_e64:{ *:[i16] } VSrc_b16:{ *:[i16] }:$src0, VSrc_b16:{ *:[i16] }:$src1, 1:{ *:[i1] })
        GIR_BuildMI, /*InsnID*/0, /*Opcode*/GIMT_Encode2(AMDGPU::V_SUB_U16_e64),
        GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/0, // DstI[vdst]
        GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/1, // src0
        GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/2, // src1
        GIR_AddImm8, /*InsnID*/0, /*Imm*/1,
        GIR_ConstrainSelectedInstOperands, /*InsnID*/0,
        GIR_EraseFromParent, /*InsnID*/0,
        // GIR_Coverage, 2166,
        GIR_Done,
      // Label 3978: @252643
      GIM_Reject,
    // Label 3976: @252644
    GIM_Reject,
    // Label 3973: @252645
    GIM_Try, /*On fail goto*//*Label 3979*/ GIMT_Encode4(252736),
      GIM_CheckType, /*MI*/0, /*Op*/1, /*Type*/GILLT_s32,
      GIM_CheckType, /*MI*/0, /*Op*/2, /*Type*/GILLT_s32,
      GIM_CheckRegBankForClass, /*MI*/0, /*Op*/0, /*RC*/GIMT_Encode2(AMDGPU::VGPR_32RegClassID),
      GIM_Try, /*On fail goto*//*Label 3980*/ GIMT_Encode4(252695), // Rule ID 2164 //
        GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasAddNoCarryInsts_HasIntClamp),
        // (usubsat:{ *:[i32] } i32:{ *:[i32] }:$src0, i32:{ *:[i32] }:$src1)  =>  (V_SUB_U32_e64:{ *:[i32] } VSrc_b32:{ *:[i32] }:$src0, VSrc_b32:{ *:[i32] }:$src1, 1:{ *:[i1] })
        GIR_BuildMI, /*InsnID*/0, /*Opcode*/GIMT_Encode2(AMDGPU::V_SUB_U32_e64),
        GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/0, // DstI[vdst]
        GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/1, // src0
        GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/2, // src1
        GIR_AddImm8, /*InsnID*/0, /*Imm*/1,
        GIR_ConstrainSelectedInstOperands, /*InsnID*/0,
        GIR_EraseFromParent, /*InsnID*/0,
        // GIR_Coverage, 2164,
        GIR_Done,
      // Label 3980: @252695
      GIM_Try, /*On fail goto*//*Label 3981*/ GIMT_Encode4(252735), // Rule ID 2162 //
        GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasIntClamp),
        // (usubsat:{ *:[i32] } i32:{ *:[i32] }:$src0, i32:{ *:[i32] }:$src1)  =>  (V_SUB_CO_U32_e64:{ *:[i32] }:{ *:[i1] } VSrc_b32:{ *:[i32] }:$src0, VSrc_b32:{ *:[i32] }:$src1, 1:{ *:[i1] })
        GIR_MakeTempReg, /*TempRegID*/0, /*TypeID*/GILLT_s1,
        GIR_BuildMI, /*InsnID*/0, /*Opcode*/GIMT_Encode2(AMDGPU::V_SUB_CO_U32_e64),
        GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/0, // DstI[vdst]
        GIR_AddTempRegister, /*InsnID*/0, /*TempRegID*/0, /*TempRegFlags*/GIMT_Encode2(RegState::Define|RegState::Dead),
        GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/1, // src0
        GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/2, // src1
        GIR_AddImm8, /*InsnID*/0, /*Imm*/1,
        GIR_ConstrainSelectedInstOperands, /*InsnID*/0,
        GIR_EraseFromParent, /*InsnID*/0,
        // GIR_Coverage, 2162,
        GIR_Done,
      // Label 3981: @252735
      GIM_Reject,
    // Label 3979: @252736
    GIM_Reject,
    // Label 3974: @252737
    GIM_Try, /*On fail goto*//*Label 3982*/ GIMT_Encode4(252820), // Rule ID 2247 //
      GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasVOP3PInsts),
      GIM_CheckType, /*MI*/0, /*Op*/1, /*Type*/GILLT_v2s16,
      GIM_CheckType, /*MI*/0, /*Op*/2, /*Type*/GILLT_v2s16,
      GIM_CheckRegBankForClass, /*MI*/0, /*Op*/0, /*RC*/GIMT_Encode2(AMDGPU::VGPR_32RegClassID),
      GIM_CheckComplexPattern, /*MI*/0, /*Op*/1, /*Renderer*/GIMT_Encode2(0), GIMT_Encode2(GICP_gi_vop3pmods),
      GIM_CheckComplexPattern, /*MI*/0, /*Op*/2, /*Renderer*/GIMT_Encode2(1), GIMT_Encode2(GICP_gi_vop3pmods),
      // (usubsat:{ *:[v2i16] } (VOP3PMods:{ *:[v2i16] } v2i16:{ *:[v2i16] }:$src0, i32:{ *:[i32] }:$src0_modifiers), (VOP3PMods:{ *:[v2i16] } v2i16:{ *:[v2i16] }:$src1, i32:{ *:[i32] }:$src1_modifiers))  =>  (V_PK_SUB_U16:{ *:[v2i16] } ?:{ *:[i32] }:$src0_modifiers, ?:{ *:[v2i16] }:$src0, ?:{ *:[i32] }:$src1_modifiers, ?:{ *:[v2i16] }:$src1, 1:{ *:[i1] })
      GIR_BuildMI, /*InsnID*/0, /*Opcode*/GIMT_Encode2(AMDGPU::V_PK_SUB_U16),
      GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/0, // DstI[vdst]
      GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/1, // src0_modifiers
      GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/0, // src0
      GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(1), /*SubOperand*/1, // src1_modifiers
      GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(1), /*SubOperand*/0, // src1
      GIR_AddImm8, /*InsnID*/0, /*Imm*/1,
      GIR_AddImm8, /*InsnID*/0, /*Imm*/0,
      GIR_AddImm8, /*InsnID*/0, /*Imm*/0,
      GIR_AddImm8, /*InsnID*/0, /*Imm*/0,
      GIR_AddImm8, /*InsnID*/0, /*Imm*/0,
      GIR_ConstrainSelectedInstOperands, /*InsnID*/0,
      GIR_EraseFromParent, /*InsnID*/0,
      // GIR_Coverage, 2247,
      GIR_Done,
    // Label 3982: @252820
    GIM_Reject,
    // Label 3975: @252821
    GIM_Reject,
    // Label 55: @252822
    GIM_SwitchType, /*MI*/0, /*Op*/0, /*[*/GIMT_Encode2(8), GIMT_Encode2(12), /*)*//*default:*//*Label 3986*/ GIMT_Encode4(253054),
    /*GILLT_s16*//*Label 3983*/ GIMT_Encode4(252849),
    /*GILLT_s32*//*Label 3984*/ GIMT_Encode4(252924), GIMT_Encode4(0),
    /*GILLT_v2s16*//*Label 3985*/ GIMT_Encode4(252970),
    // Label 3983: @252849
    GIM_Try, /*On fail goto*//*Label 3987*/ GIMT_Encode4(252923), // Rule ID 2201 //
      GIM_CheckFeatures, GIMT_Encode2(GIFBS_isGFX9Plus),
      GIM_CheckType, /*MI*/0, /*Op*/1, /*Type*/GILLT_s16,
      GIM_CheckType, /*MI*/0, /*Op*/2, /*Type*/GILLT_s16,
      GIM_CheckRegBankForClass, /*MI*/0, /*Op*/0, /*RC*/GIMT_Encode2(AMDGPU::VGPR_32RegClassID),
      GIM_CheckComplexPattern, /*MI*/0, /*Op*/1, /*Renderer*/GIMT_Encode2(0), GIMT_Encode2(GICP_gi_vop3opsel),
      GIM_CheckComplexPattern, /*MI*/0, /*Op*/2, /*Renderer*/GIMT_Encode2(1), GIMT_Encode2(GICP_gi_vop3opsel),
      // (ssubsat:{ *:[i16] } (VOP3OpSel:{ *:[i16] } i16:{ *:[i16] }:$src0, i32:{ *:[i32] }:$src0_modifiers), (VOP3OpSel:{ *:[i16] } i16:{ *:[i16] }:$src1, i32:{ *:[i32] }:$src1_modifiers))  =>  (V_SUB_I16_e64:{ *:[i16] } ?:{ *:[i32] }:$src0_modifiers, ?:{ *:[i16] }:$src0, ?:{ *:[i32] }:$src1_modifiers, ?:{ *:[i16] }:$src1, 1:{ *:[i1] }, 0:{ *:[i32] })
      GIR_BuildMI, /*InsnID*/0, /*Opcode*/GIMT_Encode2(AMDGPU::V_SUB_I16_e64),
      GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/0, // DstI[vdst]
      GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/1, // src0_modifiers
      GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/0, // src0
      GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(1), /*SubOperand*/1, // src1_modifiers
      GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(1), /*SubOperand*/0, // src1
      GIR_AddImm8, /*InsnID*/0, /*Imm*/1,
      GIR_AddImm8, /*InsnID*/0, /*Imm*/0,
      GIR_ConstrainSelectedInstOperands, /*InsnID*/0,
      GIR_EraseFromParent, /*InsnID*/0,
      // GIR_Coverage, 2201,
      GIR_Done,
    // Label 3987: @252923
    GIM_Reject,
    // Label 3984: @252924
    GIM_Try, /*On fail goto*//*Label 3988*/ GIMT_Encode4(252969), // Rule ID 2198 //
      GIM_CheckFeatures, GIMT_Encode2(GIFBS_isGFX9Plus),
      GIM_CheckType, /*MI*/0, /*Op*/1, /*Type*/GILLT_s32,
      GIM_CheckType, /*MI*/0, /*Op*/2, /*Type*/GILLT_s32,
      GIM_CheckRegBankForClass, /*MI*/0, /*Op*/0, /*RC*/GIMT_Encode2(AMDGPU::VGPR_32RegClassID),
      // (ssubsat:{ *:[i32] } i32:{ *:[i32] }:$src0, i32:{ *:[i32] }:$src1)  =>  (V_SUB_I32_e64:{ *:[i32] } VSrc_b32:{ *:[i32] }:$src0, VSrc_b32:{ *:[i32] }:$src1, 1:{ *:[i1] })
      GIR_BuildMI, /*InsnID*/0, /*Opcode*/GIMT_Encode2(AMDGPU::V_SUB_I32_e64),
      GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/0, // DstI[vdst]
      GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/1, // src0
      GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/2, // src1
      GIR_AddImm8, /*InsnID*/0, /*Imm*/1,
      GIR_ConstrainSelectedInstOperands, /*InsnID*/0,
      GIR_EraseFromParent, /*InsnID*/0,
      // GIR_Coverage, 2198,
      GIR_Done,
    // Label 3988: @252969
    GIM_Reject,
    // Label 3985: @252970
    GIM_Try, /*On fail goto*//*Label 3989*/ GIMT_Encode4(253053), // Rule ID 2248 //
      GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasVOP3PInsts),
      GIM_CheckType, /*MI*/0, /*Op*/1, /*Type*/GILLT_v2s16,
      GIM_CheckType, /*MI*/0, /*Op*/2, /*Type*/GILLT_v2s16,
      GIM_CheckRegBankForClass, /*MI*/0, /*Op*/0, /*RC*/GIMT_Encode2(AMDGPU::VGPR_32RegClassID),
      GIM_CheckComplexPattern, /*MI*/0, /*Op*/1, /*Renderer*/GIMT_Encode2(0), GIMT_Encode2(GICP_gi_vop3pmods),
      GIM_CheckComplexPattern, /*MI*/0, /*Op*/2, /*Renderer*/GIMT_Encode2(1), GIMT_Encode2(GICP_gi_vop3pmods),
      // (ssubsat:{ *:[v2i16] } (VOP3PMods:{ *:[v2i16] } v2i16:{ *:[v2i16] }:$src0, i32:{ *:[i32] }:$src0_modifiers), (VOP3PMods:{ *:[v2i16] } v2i16:{ *:[v2i16] }:$src1, i32:{ *:[i32] }:$src1_modifiers))  =>  (V_PK_SUB_I16:{ *:[v2i16] } ?:{ *:[i32] }:$src0_modifiers, ?:{ *:[v2i16] }:$src0, ?:{ *:[i32] }:$src1_modifiers, ?:{ *:[v2i16] }:$src1, 1:{ *:[i1] })
      GIR_BuildMI, /*InsnID*/0, /*Opcode*/GIMT_Encode2(AMDGPU::V_PK_SUB_I16),
      GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/0, // DstI[vdst]
      GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/1, // src0_modifiers
      GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/0, // src0
      GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(1), /*SubOperand*/1, // src1_modifiers
      GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(1), /*SubOperand*/0, // src1
      GIR_AddImm8, /*InsnID*/0, /*Imm*/1,
      GIR_AddImm8, /*InsnID*/0, /*Imm*/0,
      GIR_AddImm8, /*InsnID*/0, /*Imm*/0,
      GIR_AddImm8, /*InsnID*/0, /*Imm*/0,
      GIR_AddImm8, /*InsnID*/0, /*Imm*/0,
      GIR_ConstrainSelectedInstOperands, /*InsnID*/0,
      GIR_EraseFromParent, /*InsnID*/0,
      // GIR_Coverage, 2248,
      GIR_Done,
    // Label 3989: @253053
    GIM_Reject,
    // Label 3986: @253054
    GIM_Reject,
    // Label 56: @253055
    GIM_SwitchType, /*MI*/0, /*Op*/0, /*[*/GIMT_Encode2(8), GIMT_Encode2(13), /*)*//*default:*//*Label 3995*/ GIMT_Encode4(254617),
    /*GILLT_s16*//*Label 3990*/ GIMT_Encode4(253086),
    /*GILLT_s32*//*Label 3991*/ GIMT_Encode4(253560),
    /*GILLT_s64*//*Label 3992*/ GIMT_Encode4(254172),
    /*GILLT_v2s16*//*Label 3993*/ GIMT_Encode4(254452),
    /*GILLT_v2s32*//*Label 3994*/ GIMT_Encode4(254533),
    // Label 3990: @253086
    GIM_Try, /*On fail goto*//*Label 3996*/ GIMT_Encode4(253559),
      GIM_CheckType, /*MI*/0, /*Op*/1, /*Type*/GILLT_s16,
      GIM_CheckType, /*MI*/0, /*Op*/2, /*Type*/GILLT_s16,
      GIM_Try, /*On fail goto*//*Label 3997*/ GIMT_Encode4(253138), // Rule ID 99 //
        GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasSALUFloatInsts),
        GIM_CheckRegBankForClass, /*MI*/0, /*Op*/0, /*RC*/GIMT_Encode2(AMDGPU::SReg_32RegClassID),
        GIM_CheckRegBankForClass, /*MI*/0, /*Op*/1, /*RC*/GIMT_Encode2(AMDGPU::SReg_32RegClassID),
        GIM_CheckRegBankForClass, /*MI*/0, /*Op*/2, /*RC*/GIMT_Encode2(AMDGPU::SReg_32RegClassID),
        GIM_CheckCxxInsnPredicate, /*MI*/0, /*FnId*/GIMT_Encode2(GICXXPred_MI_Predicate_anonymous_17630),
        // (fadd:{ *:[f16] } SSrc_f16:{ *:[f16] }:$src0, SSrc_f16:{ *:[f16] }:$src1)<<P:Predicate_anonymous_17630>>  =>  (S_ADD_F16:{ *:[f16] } SSrc_f16:{ *:[f16] }:$src0, SSrc_f16:{ *:[f16] }:$src1)
        GIR_MutateOpcode, /*InsnID*/0, /*RecycleInsnID*/0, /*Opcode*/GIMT_Encode2(AMDGPU::S_ADD_F16),
        GIR_AddImplicitUse, /*InsnID*/0, GIMT_Encode2(AMDGPU::MODE),
        GIR_ConstrainSelectedInstOperands, /*InsnID*/0,
        // GIR_Coverage, 99,
        GIR_Done,
      // Label 3997: @253138
      GIM_Try, /*On fail goto*//*Label 3998*/ GIMT_Encode4(253208), // Rule ID 794 //
        GIM_CheckFeatures, GIMT_Encode2(GIFBS_Has16BitInsts_NotHasTrue16BitInsts),
        GIM_CheckRegBankForClass, /*MI*/0, /*Op*/0, /*RC*/GIMT_Encode2(AMDGPU::VGPR_32RegClassID),
        GIM_CheckComplexPattern, /*MI*/0, /*Op*/1, /*Renderer*/GIMT_Encode2(0), GIMT_Encode2(GICP_gi_vop3mods0),
        GIM_CheckComplexPattern, /*MI*/0, /*Op*/2, /*Renderer*/GIMT_Encode2(1), GIMT_Encode2(GICP_gi_vop3mods),
        // (fadd:{ *:[f16] } (VOP3Mods0:{ *:[f16] } f16:{ *:[f16] }:$src0, i32:{ *:[i32] }:$src0_modifiers, i1:{ *:[i1] }:$clamp, i32:{ *:[i32] }:$omod), (VOP3Mods:{ *:[f16] } f16:{ *:[f16] }:$src1, i32:{ *:[i32] }:$src1_modifiers))  =>  (V_ADD_F16_e64:{ *:[f16] } i32:{ *:[i32] }:$src0_modifiers, f16:{ *:[f16] }:$src0, i32:{ *:[i32] }:$src1_modifiers, f16:{ *:[f16] }:$src1, i1:{ *:[i1] }:$clamp, i32:{ *:[i32] }:$omod)
        GIR_BuildMI, /*InsnID*/0, /*Opcode*/GIMT_Encode2(AMDGPU::V_ADD_F16_e64),
        GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/0, // DstI[vdst]
        GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/1, // src0_modifiers
        GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/0, // src0
        GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(1), /*SubOperand*/1, // src1_modifiers
        GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(1), /*SubOperand*/0, // src1
        GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/2, // clamp
        GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/3, // omod
        GIR_ConstrainSelectedInstOperands, /*InsnID*/0,
        GIR_EraseFromParent, /*InsnID*/0,
        // GIR_Coverage, 794,
        GIR_Done,
      // Label 3998: @253208
      GIM_Try, /*On fail goto*//*Label 3999*/ GIMT_Encode4(253278), // Rule ID 796 //
        GIM_CheckFeatures, GIMT_Encode2(GIFBS_UseRealTrue16Insts),
        GIM_CheckRegBankForClass, /*MI*/0, /*Op*/0, /*RC*/GIMT_Encode2(AMDGPU::VGPR_16RegClassID),
        GIM_CheckComplexPattern, /*MI*/0, /*Op*/1, /*Renderer*/GIMT_Encode2(0), GIMT_Encode2(GICP_gi_vop3mods0),
        GIM_CheckComplexPattern, /*MI*/0, /*Op*/2, /*Renderer*/GIMT_Encode2(1), GIMT_Encode2(GICP_gi_vop3mods),
        // (fadd:{ *:[f16] } (VOP3Mods0:{ *:[f16] } f16:{ *:[f16] }:$src0, i32:{ *:[i32] }:$src0_modifiers, i1:{ *:[i1] }:$clamp, i32:{ *:[i32] }:$omod), (VOP3Mods:{ *:[f16] } f16:{ *:[f16] }:$src1, i32:{ *:[i32] }:$src1_modifiers))  =>  (V_ADD_F16_t16_e64:{ *:[f16] } i32:{ *:[i32] }:$src0_modifiers, f16:{ *:[f16] }:$src0, i32:{ *:[i32] }:$src1_modifiers, f16:{ *:[f16] }:$src1, i1:{ *:[i1] }:$clamp, i32:{ *:[i32] }:$omod)
        GIR_BuildMI, /*InsnID*/0, /*Opcode*/GIMT_Encode2(AMDGPU::V_ADD_F16_t16_e64),
        GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/0, // DstI[vdst]
        GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/1, // src0_modifiers
        GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/0, // src0
        GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(1), /*SubOperand*/1, // src1_modifiers
        GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(1), /*SubOperand*/0, // src1
        GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/2, // clamp
        GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/3, // omod
        GIR_ConstrainSelectedInstOperands, /*InsnID*/0,
        GIR_EraseFromParent, /*InsnID*/0,
        // GIR_Coverage, 796,
        GIR_Done,
      // Label 3999: @253278
      GIM_Try, /*On fail goto*//*Label 4000*/ GIMT_Encode4(253348), // Rule ID 798 //
        GIM_CheckFeatures, GIMT_Encode2(GIFBS_UseFakeTrue16Insts),
        GIM_CheckRegBankForClass, /*MI*/0, /*Op*/0, /*RC*/GIMT_Encode2(AMDGPU::VGPR_32RegClassID),
        GIM_CheckComplexPattern, /*MI*/0, /*Op*/1, /*Renderer*/GIMT_Encode2(0), GIMT_Encode2(GICP_gi_vop3mods0),
        GIM_CheckComplexPattern, /*MI*/0, /*Op*/2, /*Renderer*/GIMT_Encode2(1), GIMT_Encode2(GICP_gi_vop3mods),
        // (fadd:{ *:[f16] } (VOP3Mods0:{ *:[f16] } f16:{ *:[f16] }:$src0, i32:{ *:[i32] }:$src0_modifiers, i1:{ *:[i1] }:$clamp, i32:{ *:[i32] }:$omod), (VOP3Mods:{ *:[f16] } f16:{ *:[f16] }:$src1, i32:{ *:[i32] }:$src1_modifiers))  =>  (V_ADD_F16_fake16_e64:{ *:[f16] } i32:{ *:[i32] }:$src0_modifiers, f16:{ *:[f16] }:$src0, i32:{ *:[i32] }:$src1_modifiers, f16:{ *:[f16] }:$src1, i1:{ *:[i1] }:$clamp, i32:{ *:[i32] }:$omod)
        GIR_BuildMI, /*InsnID*/0, /*Opcode*/GIMT_Encode2(AMDGPU::V_ADD_F16_fake16_e64),
        GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/0, // DstI[vdst]
        GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/1, // src0_modifiers
        GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/0, // src0
        GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(1), /*SubOperand*/1, // src1_modifiers
        GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(1), /*SubOperand*/0, // src1
        GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/2, // clamp
        GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/3, // omod
        GIR_ConstrainSelectedInstOperands, /*InsnID*/0,
        GIR_EraseFromParent, /*InsnID*/0,
        // GIR_Coverage, 798,
        GIR_Done,
      // Label 4000: @253348
      GIM_Try, /*On fail goto*//*Label 4001*/ GIMT_Encode4(253418), // Rule ID 7137 //
        GIM_CheckFeatures, GIMT_Encode2(GIFBS_Has16BitInsts_NotHasTrue16BitInsts),
        GIM_CheckRegBankForClass, /*MI*/0, /*Op*/0, /*RC*/GIMT_Encode2(AMDGPU::VGPR_32RegClassID),
        GIM_CheckComplexPattern, /*MI*/0, /*Op*/1, /*Renderer*/GIMT_Encode2(0), GIMT_Encode2(GICP_gi_vop3mods),
        GIM_CheckComplexPattern, /*MI*/0, /*Op*/2, /*Renderer*/GIMT_Encode2(1), GIMT_Encode2(GICP_gi_vop3mods0),
        // (fadd:{ *:[f16] } (VOP3Mods:{ *:[f16] } f16:{ *:[f16] }:$src1, i32:{ *:[i32] }:$src1_modifiers), (VOP3Mods0:{ *:[f16] } f16:{ *:[f16] }:$src0, i32:{ *:[i32] }:$src0_modifiers, i1:{ *:[i1] }:$clamp, i32:{ *:[i32] }:$omod))  =>  (V_ADD_F16_e64:{ *:[f16] } i32:{ *:[i32] }:$src0_modifiers, f16:{ *:[f16] }:$src0, i32:{ *:[i32] }:$src1_modifiers, f16:{ *:[f16] }:$src1, i1:{ *:[i1] }:$clamp, i32:{ *:[i32] }:$omod)
        GIR_BuildMI, /*InsnID*/0, /*Opcode*/GIMT_Encode2(AMDGPU::V_ADD_F16_e64),
        GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/0, // DstI[vdst]
        GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(1), /*SubOperand*/1, // src0_modifiers
        GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(1), /*SubOperand*/0, // src0
        GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/1, // src1_modifiers
        GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/0, // src1
        GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(1), /*SubOperand*/2, // clamp
        GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(1), /*SubOperand*/3, // omod
        GIR_ConstrainSelectedInstOperands, /*InsnID*/0,
        GIR_EraseFromParent, /*InsnID*/0,
        // GIR_Coverage, 7137,
        GIR_Done,
      // Label 4001: @253418
      GIM_Try, /*On fail goto*//*Label 4002*/ GIMT_Encode4(253488), // Rule ID 7139 //
        GIM_CheckFeatures, GIMT_Encode2(GIFBS_UseRealTrue16Insts),
        GIM_CheckRegBankForClass, /*MI*/0, /*Op*/0, /*RC*/GIMT_Encode2(AMDGPU::VGPR_16RegClassID),
        GIM_CheckComplexPattern, /*MI*/0, /*Op*/1, /*Renderer*/GIMT_Encode2(0), GIMT_Encode2(GICP_gi_vop3mods),
        GIM_CheckComplexPattern, /*MI*/0, /*Op*/2, /*Renderer*/GIMT_Encode2(1), GIMT_Encode2(GICP_gi_vop3mods0),
        // (fadd:{ *:[f16] } (VOP3Mods:{ *:[f16] } f16:{ *:[f16] }:$src1, i32:{ *:[i32] }:$src1_modifiers), (VOP3Mods0:{ *:[f16] } f16:{ *:[f16] }:$src0, i32:{ *:[i32] }:$src0_modifiers, i1:{ *:[i1] }:$clamp, i32:{ *:[i32] }:$omod))  =>  (V_ADD_F16_t16_e64:{ *:[f16] } i32:{ *:[i32] }:$src0_modifiers, f16:{ *:[f16] }:$src0, i32:{ *:[i32] }:$src1_modifiers, f16:{ *:[f16] }:$src1, i1:{ *:[i1] }:$clamp, i32:{ *:[i32] }:$omod)
        GIR_BuildMI, /*InsnID*/0, /*Opcode*/GIMT_Encode2(AMDGPU::V_ADD_F16_t16_e64),
        GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/0, // DstI[vdst]
        GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(1), /*SubOperand*/1, // src0_modifiers
        GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(1), /*SubOperand*/0, // src0
        GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/1, // src1_modifiers
        GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/0, // src1
        GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(1), /*SubOperand*/2, // clamp
        GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(1), /*SubOperand*/3, // omod
        GIR_ConstrainSelectedInstOperands, /*InsnID*/0,
        GIR_EraseFromParent, /*InsnID*/0,
        // GIR_Coverage, 7139,
        GIR_Done,
      // Label 4002: @253488
      GIM_Try, /*On fail goto*//*Label 4003*/ GIMT_Encode4(253558), // Rule ID 7141 //
        GIM_CheckFeatures, GIMT_Encode2(GIFBS_UseFakeTrue16Insts),
        GIM_CheckRegBankForClass, /*MI*/0, /*Op*/0, /*RC*/GIMT_Encode2(AMDGPU::VGPR_32RegClassID),
        GIM_CheckComplexPattern, /*MI*/0, /*Op*/1, /*Renderer*/GIMT_Encode2(0), GIMT_Encode2(GICP_gi_vop3mods),
        GIM_CheckComplexPattern, /*MI*/0, /*Op*/2, /*Renderer*/GIMT_Encode2(1), GIMT_Encode2(GICP_gi_vop3mods0),
        // (fadd:{ *:[f16] } (VOP3Mods:{ *:[f16] } f16:{ *:[f16] }:$src1, i32:{ *:[i32] }:$src1_modifiers), (VOP3Mods0:{ *:[f16] } f16:{ *:[f16] }:$src0, i32:{ *:[i32] }:$src0_modifiers, i1:{ *:[i1] }:$clamp, i32:{ *:[i32] }:$omod))  =>  (V_ADD_F16_fake16_e64:{ *:[f16] } i32:{ *:[i32] }:$src0_modifiers, f16:{ *:[f16] }:$src0, i32:{ *:[i32] }:$src1_modifiers, f16:{ *:[f16] }:$src1, i1:{ *:[i1] }:$clamp, i32:{ *:[i32] }:$omod)
        GIR_BuildMI, /*InsnID*/0, /*Opcode*/GIMT_Encode2(AMDGPU::V_ADD_F16_fake16_e64),
        GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/0, // DstI[vdst]
        GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(1), /*SubOperand*/1, // src0_modifiers
        GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(1), /*SubOperand*/0, // src0
        GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/1, // src1_modifiers
        GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/0, // src1
        GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(1), /*SubOperand*/2, // clamp
        GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(1), /*SubOperand*/3, // omod
        GIR_ConstrainSelectedInstOperands, /*InsnID*/0,
        GIR_EraseFromParent, /*InsnID*/0,
        // GIR_Coverage, 7141,
        GIR_Done,
      // Label 4003: @253558
      GIM_Reject,
    // Label 3996: @253559
    GIM_Reject,
    // Label 3991: @253560
    GIM_Try, /*On fail goto*//*Label 4004*/ GIMT_Encode4(254171),
      GIM_CheckType, /*MI*/0, /*Op*/1, /*Type*/GILLT_s32,
      GIM_CheckType, /*MI*/0, /*Op*/2, /*Type*/GILLT_s32,
      GIM_Try, /*On fail goto*//*Label 4005*/ GIMT_Encode4(253676), // Rule ID 9860 //
        GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasMadMacF32Insts_NoFP32Denormals_isGFX6GFX7GFX10),
        GIM_CheckRegBankForClass, /*MI*/0, /*Op*/0, /*RC*/GIMT_Encode2(AMDGPU::VGPR_32RegClassID),
        GIM_RecordInsn, /*DefineMI*/1, /*MI*/0, /*OpIdx*/2, // MIs[1]
        GIM_CheckOpcode, /*MI*/1, GIMT_Encode2(TargetOpcode::G_INTRINSIC),
        GIM_CheckNumOperands, /*MI*/1, /*Expected*/4,
        GIM_CheckIntrinsicID, /*MI*/1, /*Op*/1, GIMT_Encode2(Intrinsic::amdgcn_fmul_legacy),
        GIM_CheckType, /*MI*/1, /*Op*/2, /*Type*/GILLT_s32,
        GIM_CheckType, /*MI*/1, /*Op*/3, /*Type*/GILLT_s32,
        GIM_CheckIsSafeToFold, /*InsnID*/1,
        GIM_CheckComplexPattern, /*MI*/0, /*Op*/1, /*Renderer*/GIMT_Encode2(0), GIMT_Encode2(GICP_gi_vop3_no_mods),
        GIM_CheckComplexPattern, /*MI*/1, /*Op*/2, /*Renderer*/GIMT_Encode2(1), GIMT_Encode2(GICP_gi_vop3_no_mods),
        GIM_CheckComplexPattern, /*MI*/1, /*Op*/3, /*Renderer*/GIMT_Encode2(2), GIMT_Encode2(GICP_gi_vop3_no_mods),
        // (fadd:{ *:[f32] } (VOP3NoMods:{ *:[f32] } f32:{ *:[f32] }:$src2), (intrinsic_wo_chain:{ *:[f32] } 1973:{ *:[iPTR] }, (VOP3NoMods:{ *:[f32] } f32:{ *:[f32] }:$src0), (VOP3NoMods:{ *:[f32] } f32:{ *:[f32] }:$src1)))  =>  (V_MAC_LEGACY_F32_e64:{ *:[f32] } 0:{ *:[i32] }, ?:{ *:[f32] }:$src0, 0:{ *:[i32] }, ?:{ *:[f32] }:$src1, 0:{ *:[i32] }, ?:{ *:[f32] }:$src2, 0:{ *:[i1] }, 0:{ *:[i32] })
        GIR_BuildMI, /*InsnID*/0, /*Opcode*/GIMT_Encode2(AMDGPU::V_MAC_LEGACY_F32_e64),
        GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/0, // DstI[vdst]
        GIR_AddImm8, /*InsnID*/0, /*Imm*/0,
        GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(1), /*SubOperand*/0, // src0
        GIR_AddImm8, /*InsnID*/0, /*Imm*/0,
        GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(2), /*SubOperand*/0, // src1
        GIR_AddImm8, /*InsnID*/0, /*Imm*/0,
        GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/0, // src2
        GIR_AddImm8, /*InsnID*/0, /*Imm*/0,
        GIR_AddImm8, /*InsnID*/0, /*Imm*/0,
        GIR_ConstrainSelectedInstOperands, /*InsnID*/0,
        GIR_EraseFromParent, /*InsnID*/0,
        // GIR_Coverage, 9860,
        GIR_Done,
      // Label 4005: @253676
      GIM_Try, /*On fail goto*//*Label 4006*/ GIMT_Encode4(253785), // Rule ID 9862 //
        GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasMadMacF32Insts_NoFP32Denormals),
        GIM_CheckRegBankForClass, /*MI*/0, /*Op*/0, /*RC*/GIMT_Encode2(AMDGPU::VGPR_32RegClassID),
        GIM_RecordInsn, /*DefineMI*/1, /*MI*/0, /*OpIdx*/2, // MIs[1]
        GIM_CheckOpcode, /*MI*/1, GIMT_Encode2(TargetOpcode::G_INTRINSIC),
        GIM_CheckNumOperands, /*MI*/1, /*Expected*/4,
        GIM_CheckIntrinsicID, /*MI*/1, /*Op*/1, GIMT_Encode2(Intrinsic::amdgcn_fmul_legacy),
        GIM_CheckType, /*MI*/1, /*Op*/2, /*Type*/GILLT_s32,
        GIM_CheckType, /*MI*/1, /*Op*/3, /*Type*/GILLT_s32,
        GIM_CheckIsSafeToFold, /*InsnID*/1,
        GIM_CheckComplexPattern, /*MI*/0, /*Op*/1, /*Renderer*/GIMT_Encode2(0), GIMT_Encode2(GICP_gi_vop3mods),
        GIM_CheckComplexPattern, /*MI*/1, /*Op*/2, /*Renderer*/GIMT_Encode2(1), GIMT_Encode2(GICP_gi_vop3mods),
        GIM_CheckComplexPattern, /*MI*/1, /*Op*/3, /*Renderer*/GIMT_Encode2(2), GIMT_Encode2(GICP_gi_vop3mods),
        // (fadd:{ *:[f32] } (VOP3Mods:{ *:[f32] } f32:{ *:[f32] }:$src2, i32:{ *:[i32] }:$src2_mod), (intrinsic_wo_chain:{ *:[f32] } 1973:{ *:[iPTR] }, (VOP3Mods:{ *:[f32] } f32:{ *:[f32] }:$src0, i32:{ *:[i32] }:$src0_mod), (VOP3Mods:{ *:[f32] } f32:{ *:[f32] }:$src1, i32:{ *:[i32] }:$src1_mod)))  =>  (V_MAD_LEGACY_F32_e64:{ *:[f32] } ?:{ *:[i32] }:$src0_mod, ?:{ *:[f32] }:$src0, ?:{ *:[i32] }:$src1_mod, ?:{ *:[f32] }:$src1, ?:{ *:[i32] }:$src2_mod, ?:{ *:[f32] }:$src2, 0:{ *:[i1] }, 0:{ *:[i32] })
        GIR_BuildMI, /*InsnID*/0, /*Opcode*/GIMT_Encode2(AMDGPU::V_MAD_LEGACY_F32_e64),
        GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/0, // DstI[vdst]
        GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(1), /*SubOperand*/1, // src0_mod
        GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(1), /*SubOperand*/0, // src0
        GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(2), /*SubOperand*/1, // src1_mod
        GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(2), /*SubOperand*/0, // src1
        GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/1, // src2_mod
        GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/0, // src2
        GIR_AddImm8, /*InsnID*/0, /*Imm*/0,
        GIR_AddImm8, /*InsnID*/0, /*Imm*/0,
        GIR_ConstrainSelectedInstOperands, /*InsnID*/0,
        GIR_EraseFromParent, /*InsnID*/0,
        // GIR_Coverage, 9862,
        GIR_Done,
      // Label 4006: @253785
      GIM_Try, /*On fail goto*//*Label 4007*/ GIMT_Encode4(253888), // Rule ID 5889 //
        GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasMadMacF32Insts_NoFP32Denormals_isGFX6GFX7GFX10),
        GIM_CheckRegBankForClass, /*MI*/0, /*Op*/0, /*RC*/GIMT_Encode2(AMDGPU::VGPR_32RegClassID),
        GIM_RecordInsn, /*DefineMI*/1, /*MI*/0, /*OpIdx*/1, // MIs[1]
        GIM_CheckOpcode, /*MI*/1, GIMT_Encode2(TargetOpcode::G_INTRINSIC),
        GIM_CheckNumOperands, /*MI*/1, /*Expected*/4,
        GIM_CheckIntrinsicID, /*MI*/1, /*Op*/1, GIMT_Encode2(Intrinsic::amdgcn_fmul_legacy),
        GIM_CheckType, /*MI*/1, /*Op*/2, /*Type*/GILLT_s32,
        GIM_CheckType, /*MI*/1, /*Op*/3, /*Type*/GILLT_s32,
        GIM_CheckIsSafeToFold, /*InsnID*/1,
        GIM_CheckComplexPattern, /*MI*/0, /*Op*/2, /*Renderer*/GIMT_Encode2(2), GIMT_Encode2(GICP_gi_vop3_no_mods),
        GIM_CheckComplexPattern, /*MI*/1, /*Op*/2, /*Renderer*/GIMT_Encode2(0), GIMT_Encode2(GICP_gi_vop3_no_mods),
        GIM_CheckComplexPattern, /*MI*/1, /*Op*/3, /*Renderer*/GIMT_Encode2(1), GIMT_Encode2(GICP_gi_vop3_no_mods),
        // (fadd:{ *:[f32] } (intrinsic_wo_chain:{ *:[f32] } 1973:{ *:[iPTR] }, (VOP3NoMods:{ *:[f32] } f32:{ *:[f32] }:$src0), (VOP3NoMods:{ *:[f32] } f32:{ *:[f32] }:$src1)), (VOP3NoMods:{ *:[f32] } f32:{ *:[f32] }:$src2))  =>  (V_MAC_LEGACY_F32_e64:{ *:[f32] } 0:{ *:[i32] }, ?:{ *:[f32] }:$src0, 0:{ *:[i32] }, ?:{ *:[f32] }:$src1, 0:{ *:[i32] }, ?:{ *:[f32] }:$src2, 0:{ *:[i1] }, 0:{ *:[i32] })
        GIR_BuildMI, /*InsnID*/0, /*Opcode*/GIMT_Encode2(AMDGPU::V_MAC_LEGACY_F32_e64),
        GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/0, // DstI[vdst]
        GIR_AddImm8, /*InsnID*/0, /*Imm*/0,
        GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/0, // src0
        GIR_AddImm8, /*InsnID*/0, /*Imm*/0,
        GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(1), /*SubOperand*/0, // src1
        GIR_AddImm8, /*InsnID*/0, /*Imm*/0,
        GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(2), /*SubOperand*/0, // src2
        GIR_AddImm8, /*InsnID*/0, /*Imm*/0,
        GIR_AddImm8, /*InsnID*/0, /*Imm*/0,
        GIR_ConstrainSelectedInstOperands, /*InsnID*/0,
        GIR_EraseFromParent, /*InsnID*/0,
        // GIR_Coverage, 5889,
        GIR_Done,
      // Label 4007: @253888
      GIM_Try, /*On fail goto*//*Label 4008*/ GIMT_Encode4(253997), // Rule ID 5895 //
        GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasMadMacF32Insts_NoFP32Denormals),
        GIM_CheckRegBankForClass, /*MI*/0, /*Op*/0, /*RC*/GIMT_Encode2(AMDGPU::VGPR_32RegClassID),
        GIM_RecordInsn, /*DefineMI*/1, /*MI*/0, /*OpIdx*/1, // MIs[1]
        GIM_CheckOpcode, /*MI*/1, GIMT_Encode2(TargetOpcode::G_INTRINSIC),
        GIM_CheckNumOperands, /*MI*/1, /*Expected*/4,
        GIM_CheckIntrinsicID, /*MI*/1, /*Op*/1, GIMT_Encode2(Intrinsic::amdgcn_fmul_legacy),
        GIM_CheckType, /*MI*/1, /*Op*/2, /*Type*/GILLT_s32,
        GIM_CheckType, /*MI*/1, /*Op*/3, /*Type*/GILLT_s32,
        GIM_CheckIsSafeToFold, /*InsnID*/1,
        GIM_CheckComplexPattern, /*MI*/0, /*Op*/2, /*Renderer*/GIMT_Encode2(2), GIMT_Encode2(GICP_gi_vop3mods),
        GIM_CheckComplexPattern, /*MI*/1, /*Op*/2, /*Renderer*/GIMT_Encode2(0), GIMT_Encode2(GICP_gi_vop3mods),
        GIM_CheckComplexPattern, /*MI*/1, /*Op*/3, /*Renderer*/GIMT_Encode2(1), GIMT_Encode2(GICP_gi_vop3mods),
        // (fadd:{ *:[f32] } (intrinsic_wo_chain:{ *:[f32] } 1973:{ *:[iPTR] }, (VOP3Mods:{ *:[f32] } f32:{ *:[f32] }:$src0, i32:{ *:[i32] }:$src0_mod), (VOP3Mods:{ *:[f32] } f32:{ *:[f32] }:$src1, i32:{ *:[i32] }:$src1_mod)), (VOP3Mods:{ *:[f32] } f32:{ *:[f32] }:$src2, i32:{ *:[i32] }:$src2_mod))  =>  (V_MAD_LEGACY_F32_e64:{ *:[f32] } ?:{ *:[i32] }:$src0_mod, ?:{ *:[f32] }:$src0, ?:{ *:[i32] }:$src1_mod, ?:{ *:[f32] }:$src1, ?:{ *:[i32] }:$src2_mod, ?:{ *:[f32] }:$src2, 0:{ *:[i1] }, 0:{ *:[i32] })
        GIR_BuildMI, /*InsnID*/0, /*Opcode*/GIMT_Encode2(AMDGPU::V_MAD_LEGACY_F32_e64),
        GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/0, // DstI[vdst]
        GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/1, // src0_mod
        GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/0, // src0
        GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(1), /*SubOperand*/1, // src1_mod
        GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(1), /*SubOperand*/0, // src1
        GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(2), /*SubOperand*/1, // src2_mod
        GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(2), /*SubOperand*/0, // src2
        GIR_AddImm8, /*InsnID*/0, /*Imm*/0,
        GIR_AddImm8, /*InsnID*/0, /*Imm*/0,
        GIR_ConstrainSelectedInstOperands, /*InsnID*/0,
        GIR_EraseFromParent, /*InsnID*/0,
        // GIR_Coverage, 5895,
        GIR_Done,
      // Label 4008: @253997
      GIM_Try, /*On fail goto*//*Label 4009*/ GIMT_Encode4(254036), // Rule ID 91 //
        GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasSALUFloatInsts),
        GIM_CheckRegBankForClass, /*MI*/0, /*Op*/0, /*RC*/GIMT_Encode2(AMDGPU::SReg_32RegClassID),
        GIM_CheckRegBankForClass, /*MI*/0, /*Op*/1, /*RC*/GIMT_Encode2(AMDGPU::SReg_32RegClassID),
        GIM_CheckRegBankForClass, /*MI*/0, /*Op*/2, /*RC*/GIMT_Encode2(AMDGPU::SReg_32RegClassID),
        GIM_CheckCxxInsnPredicate, /*MI*/0, /*FnId*/GIMT_Encode2(GICXXPred_MI_Predicate_anonymous_17630),
        // (fadd:{ *:[f32] } SSrc_f32:{ *:[f32] }:$src0, SSrc_f32:{ *:[f32] }:$src1)<<P:Predicate_anonymous_17630>>  =>  (S_ADD_F32:{ *:[f32] } SSrc_f32:{ *:[f32] }:$src0, SSrc_f32:{ *:[f32] }:$src1)
        GIR_MutateOpcode, /*InsnID*/0, /*RecycleInsnID*/0, /*Opcode*/GIMT_Encode2(AMDGPU::S_ADD_F32),
        GIR_AddImplicitUse, /*InsnID*/0, GIMT_Encode2(AMDGPU::MODE),
        GIR_ConstrainSelectedInstOperands, /*InsnID*/0,
        // GIR_Coverage, 91,
        GIR_Done,
      // Label 4009: @254036
      GIM_Try, /*On fail goto*//*Label 4010*/ GIMT_Encode4(254103), // Rule ID 724 //
        GIM_CheckRegBankForClass, /*MI*/0, /*Op*/0, /*RC*/GIMT_Encode2(AMDGPU::VGPR_32RegClassID),
        GIM_CheckComplexPattern, /*MI*/0, /*Op*/1, /*Renderer*/GIMT_Encode2(0), GIMT_Encode2(GICP_gi_vop3mods0),
        GIM_CheckComplexPattern, /*MI*/0, /*Op*/2, /*Renderer*/GIMT_Encode2(1), GIMT_Encode2(GICP_gi_vop3mods),
        // (fadd:{ *:[f32] } (VOP3Mods0:{ *:[f32] } f32:{ *:[f32] }:$src0, i32:{ *:[i32] }:$src0_modifiers, i1:{ *:[i1] }:$clamp, i32:{ *:[i32] }:$omod), (VOP3Mods:{ *:[f32] } f32:{ *:[f32] }:$src1, i32:{ *:[i32] }:$src1_modifiers))  =>  (V_ADD_F32_e64:{ *:[f32] } i32:{ *:[i32] }:$src0_modifiers, f32:{ *:[f32] }:$src0, i32:{ *:[i32] }:$src1_modifiers, f32:{ *:[f32] }:$src1, i1:{ *:[i1] }:$clamp, i32:{ *:[i32] }:$omod)
        GIR_BuildMI, /*InsnID*/0, /*Opcode*/GIMT_Encode2(AMDGPU::V_ADD_F32_e64),
        GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/0, // DstI[vdst]
        GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/1, // src0_modifiers
        GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/0, // src0
        GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(1), /*SubOperand*/1, // src1_modifiers
        GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(1), /*SubOperand*/0, // src1
        GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/2, // clamp
        GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/3, // omod
        GIR_ConstrainSelectedInstOperands, /*InsnID*/0,
        GIR_EraseFromParent, /*InsnID*/0,
        // GIR_Coverage, 724,
        GIR_Done,
      // Label 4010: @254103
      GIM_Try, /*On fail goto*//*Label 4011*/ GIMT_Encode4(254170), // Rule ID 7126 //
        GIM_CheckRegBankForClass, /*MI*/0, /*Op*/0, /*RC*/GIMT_Encode2(AMDGPU::VGPR_32RegClassID),
        GIM_CheckComplexPattern, /*MI*/0, /*Op*/1, /*Renderer*/GIMT_Encode2(0), GIMT_Encode2(GICP_gi_vop3mods),
        GIM_CheckComplexPattern, /*MI*/0, /*Op*/2, /*Renderer*/GIMT_Encode2(1), GIMT_Encode2(GICP_gi_vop3mods0),
        // (fadd:{ *:[f32] } (VOP3Mods:{ *:[f32] } f32:{ *:[f32] }:$src1, i32:{ *:[i32] }:$src1_modifiers), (VOP3Mods0:{ *:[f32] } f32:{ *:[f32] }:$src0, i32:{ *:[i32] }:$src0_modifiers, i1:{ *:[i1] }:$clamp, i32:{ *:[i32] }:$omod))  =>  (V_ADD_F32_e64:{ *:[f32] } i32:{ *:[i32] }:$src0_modifiers, f32:{ *:[f32] }:$src0, i32:{ *:[i32] }:$src1_modifiers, f32:{ *:[f32] }:$src1, i1:{ *:[i1] }:$clamp, i32:{ *:[i32] }:$omod)
        GIR_BuildMI, /*InsnID*/0, /*Opcode*/GIMT_Encode2(AMDGPU::V_ADD_F32_e64),
        GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/0, // DstI[vdst]
        GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(1), /*SubOperand*/1, // src0_modifiers
        GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(1), /*SubOperand*/0, // src0
        GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/1, // src1_modifiers
        GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/0, // src1
        GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(1), /*SubOperand*/2, // clamp
        GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(1), /*SubOperand*/3, // omod
        GIR_ConstrainSelectedInstOperands, /*InsnID*/0,
        GIR_EraseFromParent, /*InsnID*/0,
        // GIR_Coverage, 7126,
        GIR_Done,
      // Label 4011: @254170
      GIM_Reject,
    // Label 4004: @254171
    GIM_Reject,
    // Label 3992: @254172
    GIM_Try, /*On fail goto*//*Label 4012*/ GIMT_Encode4(254451),
      GIM_CheckType, /*MI*/0, /*Op*/1, /*Type*/GILLT_s64,
      GIM_CheckType, /*MI*/0, /*Op*/2, /*Type*/GILLT_s64,
      GIM_CheckRegBankForClass, /*MI*/0, /*Op*/0, /*RC*/GIMT_Encode2(AMDGPU::VReg_64RegClassID),
      GIM_Try, /*On fail goto*//*Label 4013*/ GIMT_Encode4(254255), // Rule ID 840 //
        GIM_CheckFeatures, GIMT_Encode2(GIFBS_isGFX12Plus),
        GIM_CheckComplexPattern, /*MI*/0, /*Op*/1, /*Renderer*/GIMT_Encode2(0), GIMT_Encode2(GICP_gi_vop3mods0),
        GIM_CheckComplexPattern, /*MI*/0, /*Op*/2, /*Renderer*/GIMT_Encode2(1), GIMT_Encode2(GICP_gi_vop3mods),
        // (fadd:{ *:[f64] } (VOP3Mods0:{ *:[f64] } f64:{ *:[f64] }:$src0, i32:{ *:[i32] }:$src0_modifiers, i1:{ *:[i1] }:$clamp, i32:{ *:[i32] }:$omod), (VOP3Mods:{ *:[f64] } f64:{ *:[f64] }:$src1, i32:{ *:[i32] }:$src1_modifiers))  =>  (V_ADD_F64_pseudo_e64:{ *:[f64] } i32:{ *:[i32] }:$src0_modifiers, f64:{ *:[f64] }:$src0, i32:{ *:[i32] }:$src1_modifiers, f64:{ *:[f64] }:$src1, i1:{ *:[i1] }:$clamp, i32:{ *:[i32] }:$omod)
        GIR_BuildMI, /*InsnID*/0, /*Opcode*/GIMT_Encode2(AMDGPU::V_ADD_F64_pseudo_e64),
        GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/0, // DstI[vdst]
        GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/1, // src0_modifiers
        GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/0, // src0
        GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(1), /*SubOperand*/1, // src1_modifiers
        GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(1), /*SubOperand*/0, // src1
        GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/2, // clamp
        GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/3, // omod
        GIR_ConstrainSelectedInstOperands, /*InsnID*/0,
        GIR_EraseFromParent, /*InsnID*/0,
        // GIR_Coverage, 840,
        GIR_Done,
      // Label 4013: @254255
      GIM_Try, /*On fail goto*//*Label 4014*/ GIMT_Encode4(254320), // Rule ID 858 //
        GIM_CheckFeatures, GIMT_Encode2(GIFBS_isNotGFX12Plus),
        GIM_CheckComplexPattern, /*MI*/0, /*Op*/1, /*Renderer*/GIMT_Encode2(0), GIMT_Encode2(GICP_gi_vop3mods0),
        GIM_CheckComplexPattern, /*MI*/0, /*Op*/2, /*Renderer*/GIMT_Encode2(1), GIMT_Encode2(GICP_gi_vop3mods),
        // (fadd:{ *:[f64] } (VOP3Mods0:{ *:[f64] } f64:{ *:[f64] }:$src0, i32:{ *:[i32] }:$src0_modifiers, i1:{ *:[i1] }:$clamp, i32:{ *:[i32] }:$omod), (VOP3Mods:{ *:[f64] } f64:{ *:[f64] }:$src1, i32:{ *:[i32] }:$src1_modifiers))  =>  (V_ADD_F64_e64:{ *:[f64] } i32:{ *:[i32] }:$src0_modifiers, f64:{ *:[f64] }:$src0, i32:{ *:[i32] }:$src1_modifiers, f64:{ *:[f64] }:$src1, i1:{ *:[i1] }:$clamp, i32:{ *:[i32] }:$omod)
        GIR_BuildMI, /*InsnID*/0, /*Opcode*/GIMT_Encode2(AMDGPU::V_ADD_F64_e64),
        GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/0, // DstI[vdst]
        GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/1, // src0_modifiers
        GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/0, // src0
        GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(1), /*SubOperand*/1, // src1_modifiers
        GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(1), /*SubOperand*/0, // src1
        GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/2, // clamp
        GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/3, // omod
        GIR_ConstrainSelectedInstOperands, /*InsnID*/0,
        GIR_EraseFromParent, /*InsnID*/0,
        // GIR_Coverage, 858,
        GIR_Done,
      // Label 4014: @254320
      GIM_Try, /*On fail goto*//*Label 4015*/ GIMT_Encode4(254385), // Rule ID 7163 //
        GIM_CheckFeatures, GIMT_Encode2(GIFBS_isGFX12Plus),
        GIM_CheckComplexPattern, /*MI*/0, /*Op*/1, /*Renderer*/GIMT_Encode2(0), GIMT_Encode2(GICP_gi_vop3mods),
        GIM_CheckComplexPattern, /*MI*/0, /*Op*/2, /*Renderer*/GIMT_Encode2(1), GIMT_Encode2(GICP_gi_vop3mods0),
        // (fadd:{ *:[f64] } (VOP3Mods:{ *:[f64] } f64:{ *:[f64] }:$src1, i32:{ *:[i32] }:$src1_modifiers), (VOP3Mods0:{ *:[f64] } f64:{ *:[f64] }:$src0, i32:{ *:[i32] }:$src0_modifiers, i1:{ *:[i1] }:$clamp, i32:{ *:[i32] }:$omod))  =>  (V_ADD_F64_pseudo_e64:{ *:[f64] } i32:{ *:[i32] }:$src0_modifiers, f64:{ *:[f64] }:$src0, i32:{ *:[i32] }:$src1_modifiers, f64:{ *:[f64] }:$src1, i1:{ *:[i1] }:$clamp, i32:{ *:[i32] }:$omod)
        GIR_BuildMI, /*InsnID*/0, /*Opcode*/GIMT_Encode2(AMDGPU::V_ADD_F64_pseudo_e64),
        GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/0, // DstI[vdst]
        GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(1), /*SubOperand*/1, // src0_modifiers
        GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(1), /*SubOperand*/0, // src0
        GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/1, // src1_modifiers
        GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/0, // src1
        GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(1), /*SubOperand*/2, // clamp
        GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(1), /*SubOperand*/3, // omod
        GIR_ConstrainSelectedInstOperands, /*InsnID*/0,
        GIR_EraseFromParent, /*InsnID*/0,
        // GIR_Coverage, 7163,
        GIR_Done,
      // Label 4015: @254385
      GIM_Try, /*On fail goto*//*Label 4016*/ GIMT_Encode4(254450), // Rule ID 7176 //
        GIM_CheckFeatures, GIMT_Encode2(GIFBS_isNotGFX12Plus),
        GIM_CheckComplexPattern, /*MI*/0, /*Op*/1, /*Renderer*/GIMT_Encode2(0), GIMT_Encode2(GICP_gi_vop3mods),
        GIM_CheckComplexPattern, /*MI*/0, /*Op*/2, /*Renderer*/GIMT_Encode2(1), GIMT_Encode2(GICP_gi_vop3mods0),
        // (fadd:{ *:[f64] } (VOP3Mods:{ *:[f64] } f64:{ *:[f64] }:$src1, i32:{ *:[i32] }:$src1_modifiers), (VOP3Mods0:{ *:[f64] } f64:{ *:[f64] }:$src0, i32:{ *:[i32] }:$src0_modifiers, i1:{ *:[i1] }:$clamp, i32:{ *:[i32] }:$omod))  =>  (V_ADD_F64_e64:{ *:[f64] } i32:{ *:[i32] }:$src0_modifiers, f64:{ *:[f64] }:$src0, i32:{ *:[i32] }:$src1_modifiers, f64:{ *:[f64] }:$src1, i1:{ *:[i1] }:$clamp, i32:{ *:[i32] }:$omod)
        GIR_BuildMI, /*InsnID*/0, /*Opcode*/GIMT_Encode2(AMDGPU::V_ADD_F64_e64),
        GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/0, // DstI[vdst]
        GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(1), /*SubOperand*/1, // src0_modifiers
        GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(1), /*SubOperand*/0, // src0
        GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/1, // src1_modifiers
        GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/0, // src1
        GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(1), /*SubOperand*/2, // clamp
        GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(1), /*SubOperand*/3, // omod
        GIR_ConstrainSelectedInstOperands, /*InsnID*/0,
        GIR_EraseFromParent, /*InsnID*/0,
        // GIR_Coverage, 7176,
        GIR_Done,
      // Label 4016: @254450
      GIM_Reject,
    // Label 4012: @254451
    GIM_Reject,
    // Label 3993: @254452
    GIM_Try, /*On fail goto*//*Label 4017*/ GIMT_Encode4(254532), // Rule ID 961 //
      GIM_CheckType, /*MI*/0, /*Op*/1, /*Type*/GILLT_v2s16,
      GIM_CheckType, /*MI*/0, /*Op*/2, /*Type*/GILLT_v2s16,
      GIM_CheckRegBankForClass, /*MI*/0, /*Op*/0, /*RC*/GIMT_Encode2(AMDGPU::VGPR_32RegClassID),
      GIM_CheckComplexPattern, /*MI*/0, /*Op*/1, /*Renderer*/GIMT_Encode2(0), GIMT_Encode2(GICP_gi_vop3pmods),
      GIM_CheckComplexPattern, /*MI*/0, /*Op*/2, /*Renderer*/GIMT_Encode2(1), GIMT_Encode2(GICP_gi_vop3pmods),
      // (fadd:{ *:[v2f16] } (VOP3PMods:{ *:[v2f16] } v2f16:{ *:[v2f16] }:$src0, i32:{ *:[i32] }:$src0_modifiers), (VOP3PMods:{ *:[v2f16] } v2f16:{ *:[v2f16] }:$src1, i32:{ *:[i32] }:$src1_modifiers))  =>  (V_PK_ADD_F16:{ *:[v2f16] } i32:{ *:[i32] }:$src0_modifiers, v2f16:{ *:[v2f16] }:$src0, i32:{ *:[i32] }:$src1_modifiers, v2f16:{ *:[v2f16] }:$src1)
      GIR_BuildMI, /*InsnID*/0, /*Opcode*/GIMT_Encode2(AMDGPU::V_PK_ADD_F16),
      GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/0, // DstI[vdst]
      GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/1, // src0_modifiers
      GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/0, // src0
      GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(1), /*SubOperand*/1, // src1_modifiers
      GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(1), /*SubOperand*/0, // src1
      GIR_AddImm8, /*InsnID*/0, /*Imm*/0,
      GIR_AddImm8, /*InsnID*/0, /*Imm*/0,
      GIR_AddImm8, /*InsnID*/0, /*Imm*/0,
      GIR_AddImm8, /*InsnID*/0, /*Imm*/0,
      GIR_AddImm8, /*InsnID*/0, /*Imm*/0,
      GIR_ConstrainSelectedInstOperands, /*InsnID*/0,
      GIR_EraseFromParent, /*InsnID*/0,
      // GIR_Coverage, 961,
      GIR_Done,
    // Label 4017: @254532
    GIM_Reject,
    // Label 3994: @254533
    GIM_Try, /*On fail goto*//*Label 4018*/ GIMT_Encode4(254616), // Rule ID 1089 //
      GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasPackedFP32Ops),
      GIM_CheckType, /*MI*/0, /*Op*/1, /*Type*/GILLT_v2s32,
      GIM_CheckType, /*MI*/0, /*Op*/2, /*Type*/GILLT_v2s32,
      GIM_CheckRegBankForClass, /*MI*/0, /*Op*/0, /*RC*/GIMT_Encode2(AMDGPU::VReg_64RegClassID),
      GIM_CheckComplexPattern, /*MI*/0, /*Op*/1, /*Renderer*/GIMT_Encode2(0), GIMT_Encode2(GICP_gi_vop3pmods),
      GIM_CheckComplexPattern, /*MI*/0, /*Op*/2, /*Renderer*/GIMT_Encode2(1), GIMT_Encode2(GICP_gi_vop3pmods),
      // (fadd:{ *:[v2f32] } (VOP3PMods:{ *:[v2f32] } v2f32:{ *:[v2f32] }:$src0, i32:{ *:[i32] }:$src0_modifiers), (VOP3PMods:{ *:[v2f32] } v2f32:{ *:[v2f32] }:$src1, i32:{ *:[i32] }:$src1_modifiers))  =>  (V_PK_ADD_F32:{ *:[v2f32] } i32:{ *:[i32] }:$src0_modifiers, v2f32:{ *:[v2f32] }:$src0, i32:{ *:[i32] }:$src1_modifiers, v2f32:{ *:[v2f32] }:$src1)
      GIR_BuildMI, /*InsnID*/0, /*Opcode*/GIMT_Encode2(AMDGPU::V_PK_ADD_F32),
      GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/0, // DstI[vdst]
      GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/1, // src0_modifiers
      GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/0, // src0
      GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(1), /*SubOperand*/1, // src1_modifiers
      GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(1), /*SubOperand*/0, // src1
      GIR_AddImm8, /*InsnID*/0, /*Imm*/0,
      GIR_AddImm8, /*InsnID*/0, /*Imm*/0,
      GIR_AddImm8, /*InsnID*/0, /*Imm*/0,
      GIR_AddImm8, /*InsnID*/0, /*Imm*/0,
      GIR_AddImm8, /*InsnID*/0, /*Imm*/0,
      GIR_ConstrainSelectedInstOperands, /*InsnID*/0,
      GIR_EraseFromParent, /*InsnID*/0,
      // GIR_Coverage, 1089,
      GIR_Done,
    // Label 4018: @254616
    GIM_Reject,
    // Label 3995: @254617
    GIM_Reject,
    // Label 57: @254618
    GIM_SwitchType, /*MI*/0, /*Op*/0, /*[*/GIMT_Encode2(8), GIMT_Encode2(10), /*)*//*default:*//*Label 4021*/ GIMT_Encode4(255022),
    /*GILLT_s16*//*Label 4019*/ GIMT_Encode4(254637),
    /*GILLT_s32*//*Label 4020*/ GIMT_Encode4(254901),
    // Label 4019: @254637
    GIM_Try, /*On fail goto*//*Label 4022*/ GIMT_Encode4(254900),
      GIM_CheckType, /*MI*/0, /*Op*/1, /*Type*/GILLT_s16,
      GIM_CheckType, /*MI*/0, /*Op*/2, /*Type*/GILLT_s16,
      GIM_Try, /*On fail goto*//*Label 4023*/ GIMT_Encode4(254689), // Rule ID 107 //
        GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasSALUFloatInsts),
        GIM_CheckRegBankForClass, /*MI*/0, /*Op*/0, /*RC*/GIMT_Encode2(AMDGPU::SReg_32RegClassID),
        GIM_CheckRegBankForClass, /*MI*/0, /*Op*/1, /*RC*/GIMT_Encode2(AMDGPU::SReg_32RegClassID),
        GIM_CheckRegBankForClass, /*MI*/0, /*Op*/2, /*RC*/GIMT_Encode2(AMDGPU::SReg_32RegClassID),
        GIM_CheckCxxInsnPredicate, /*MI*/0, /*FnId*/GIMT_Encode2(GICXXPred_MI_Predicate_anonymous_17634),
        // (fsub:{ *:[f16] } SSrc_f16:{ *:[f16] }:$src0, SSrc_f16:{ *:[f16] }:$src1)<<P:Predicate_anonymous_17634>>  =>  (S_SUB_F16:{ *:[f16] } SSrc_f16:{ *:[f16] }:$src0, SSrc_f16:{ *:[f16] }:$src1)
        GIR_MutateOpcode, /*InsnID*/0, /*RecycleInsnID*/0, /*Opcode*/GIMT_Encode2(AMDGPU::S_SUB_F16),
        GIR_AddImplicitUse, /*InsnID*/0, GIMT_Encode2(AMDGPU::MODE),
        GIR_ConstrainSelectedInstOperands, /*InsnID*/0,
        // GIR_Coverage, 107,
        GIR_Done,
      // Label 4023: @254689
      GIM_Try, /*On fail goto*//*Label 4024*/ GIMT_Encode4(254759), // Rule ID 800 //
        GIM_CheckFeatures, GIMT_Encode2(GIFBS_Has16BitInsts_NotHasTrue16BitInsts),
        GIM_CheckRegBankForClass, /*MI*/0, /*Op*/0, /*RC*/GIMT_Encode2(AMDGPU::VGPR_32RegClassID),
        GIM_CheckComplexPattern, /*MI*/0, /*Op*/1, /*Renderer*/GIMT_Encode2(0), GIMT_Encode2(GICP_gi_vop3mods0),
        GIM_CheckComplexPattern, /*MI*/0, /*Op*/2, /*Renderer*/GIMT_Encode2(1), GIMT_Encode2(GICP_gi_vop3mods),
        // (fsub:{ *:[f16] } (VOP3Mods0:{ *:[f16] } f16:{ *:[f16] }:$src0, i32:{ *:[i32] }:$src0_modifiers, i1:{ *:[i1] }:$clamp, i32:{ *:[i32] }:$omod), (VOP3Mods:{ *:[f16] } f16:{ *:[f16] }:$src1, i32:{ *:[i32] }:$src1_modifiers))  =>  (V_SUB_F16_e64:{ *:[f16] } i32:{ *:[i32] }:$src0_modifiers, f16:{ *:[f16] }:$src0, i32:{ *:[i32] }:$src1_modifiers, f16:{ *:[f16] }:$src1, i1:{ *:[i1] }:$clamp, i32:{ *:[i32] }:$omod)
        GIR_BuildMI, /*InsnID*/0, /*Opcode*/GIMT_Encode2(AMDGPU::V_SUB_F16_e64),
        GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/0, // DstI[vdst]
        GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/1, // src0_modifiers
        GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/0, // src0
        GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(1), /*SubOperand*/1, // src1_modifiers
        GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(1), /*SubOperand*/0, // src1
        GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/2, // clamp
        GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/3, // omod
        GIR_ConstrainSelectedInstOperands, /*InsnID*/0,
        GIR_EraseFromParent, /*InsnID*/0,
        // GIR_Coverage, 800,
        GIR_Done,
      // Label 4024: @254759
      GIM_Try, /*On fail goto*//*Label 4025*/ GIMT_Encode4(254829), // Rule ID 802 //
        GIM_CheckFeatures, GIMT_Encode2(GIFBS_UseRealTrue16Insts),
        GIM_CheckRegBankForClass, /*MI*/0, /*Op*/0, /*RC*/GIMT_Encode2(AMDGPU::VGPR_16RegClassID),
        GIM_CheckComplexPattern, /*MI*/0, /*Op*/1, /*Renderer*/GIMT_Encode2(0), GIMT_Encode2(GICP_gi_vop3mods0),
        GIM_CheckComplexPattern, /*MI*/0, /*Op*/2, /*Renderer*/GIMT_Encode2(1), GIMT_Encode2(GICP_gi_vop3mods),
        // (fsub:{ *:[f16] } (VOP3Mods0:{ *:[f16] } f16:{ *:[f16] }:$src0, i32:{ *:[i32] }:$src0_modifiers, i1:{ *:[i1] }:$clamp, i32:{ *:[i32] }:$omod), (VOP3Mods:{ *:[f16] } f16:{ *:[f16] }:$src1, i32:{ *:[i32] }:$src1_modifiers))  =>  (V_SUB_F16_t16_e64:{ *:[f16] } i32:{ *:[i32] }:$src0_modifiers, f16:{ *:[f16] }:$src0, i32:{ *:[i32] }:$src1_modifiers, f16:{ *:[f16] }:$src1, i1:{ *:[i1] }:$clamp, i32:{ *:[i32] }:$omod)
        GIR_BuildMI, /*InsnID*/0, /*Opcode*/GIMT_Encode2(AMDGPU::V_SUB_F16_t16_e64),
        GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/0, // DstI[vdst]
        GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/1, // src0_modifiers
        GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/0, // src0
        GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(1), /*SubOperand*/1, // src1_modifiers
        GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(1), /*SubOperand*/0, // src1
        GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/2, // clamp
        GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/3, // omod
        GIR_ConstrainSelectedInstOperands, /*InsnID*/0,
        GIR_EraseFromParent, /*InsnID*/0,
        // GIR_Coverage, 802,
        GIR_Done,
      // Label 4025: @254829
      GIM_Try, /*On fail goto*//*Label 4026*/ GIMT_Encode4(254899), // Rule ID 804 //
        GIM_CheckFeatures, GIMT_Encode2(GIFBS_UseFakeTrue16Insts),
        GIM_CheckRegBankForClass, /*MI*/0, /*Op*/0, /*RC*/GIMT_Encode2(AMDGPU::VGPR_32RegClassID),
        GIM_CheckComplexPattern, /*MI*/0, /*Op*/1, /*Renderer*/GIMT_Encode2(0), GIMT_Encode2(GICP_gi_vop3mods0),
        GIM_CheckComplexPattern, /*MI*/0, /*Op*/2, /*Renderer*/GIMT_Encode2(1), GIMT_Encode2(GICP_gi_vop3mods),
        // (fsub:{ *:[f16] } (VOP3Mods0:{ *:[f16] } f16:{ *:[f16] }:$src0, i32:{ *:[i32] }:$src0_modifiers, i1:{ *:[i1] }:$clamp, i32:{ *:[i32] }:$omod), (VOP3Mods:{ *:[f16] } f16:{ *:[f16] }:$src1, i32:{ *:[i32] }:$src1_modifiers))  =>  (V_SUB_F16_fake16_e64:{ *:[f16] } i32:{ *:[i32] }:$src0_modifiers, f16:{ *:[f16] }:$src0, i32:{ *:[i32] }:$src1_modifiers, f16:{ *:[f16] }:$src1, i1:{ *:[i1] }:$clamp, i32:{ *:[i32] }:$omod)
        GIR_BuildMI, /*InsnID*/0, /*Opcode*/GIMT_Encode2(AMDGPU::V_SUB_F16_fake16_e64),
        GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/0, // DstI[vdst]
        GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/1, // src0_modifiers
        GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/0, // src0
        GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(1), /*SubOperand*/1, // src1_modifiers
        GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(1), /*SubOperand*/0, // src1
        GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/2, // clamp
        GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/3, // omod
        GIR_ConstrainSelectedInstOperands, /*InsnID*/0,
        GIR_EraseFromParent, /*InsnID*/0,
        // GIR_Coverage, 804,
        GIR_Done,
      // Label 4026: @254899
      GIM_Reject,
    // Label 4022: @254900
    GIM_Reject,
    // Label 4020: @254901
    GIM_Try, /*On fail goto*//*Label 4027*/ GIMT_Encode4(255021),
      GIM_CheckType, /*MI*/0, /*Op*/1, /*Type*/GILLT_s32,
      GIM_CheckType, /*MI*/0, /*Op*/2, /*Type*/GILLT_s32,
      GIM_Try, /*On fail goto*//*Label 4028*/ GIMT_Encode4(254953), // Rule ID 109 //
        GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasSALUFloatInsts),
        GIM_CheckRegBankForClass, /*MI*/0, /*Op*/0, /*RC*/GIMT_Encode2(AMDGPU::SReg_32RegClassID),
        GIM_CheckRegBankForClass, /*MI*/0, /*Op*/1, /*RC*/GIMT_Encode2(AMDGPU::SReg_32RegClassID),
        GIM_CheckRegBankForClass, /*MI*/0, /*Op*/2, /*RC*/GIMT_Encode2(AMDGPU::SReg_32RegClassID),
        GIM_CheckCxxInsnPredicate, /*MI*/0, /*FnId*/GIMT_Encode2(GICXXPred_MI_Predicate_anonymous_17634),
        // (fsub:{ *:[f32] } SSrc_f32:{ *:[f32] }:$src0, SSrc_f32:{ *:[f32] }:$src1)<<P:Predicate_anonymous_17634>>  =>  (S_SUB_F32:{ *:[f32] } SSrc_f32:{ *:[f32] }:$src0, SSrc_f32:{ *:[f32] }:$src1)
        GIR_MutateOpcode, /*InsnID*/0, /*RecycleInsnID*/0, /*Opcode*/GIMT_Encode2(AMDGPU::S_SUB_F32),
        GIR_AddImplicitUse, /*InsnID*/0, GIMT_Encode2(AMDGPU::MODE),
        GIR_ConstrainSelectedInstOperands, /*InsnID*/0,
        // GIR_Coverage, 109,
        GIR_Done,
      // Label 4028: @254953
      GIM_Try, /*On fail goto*//*Label 4029*/ GIMT_Encode4(255020), // Rule ID 726 //
        GIM_CheckRegBankForClass, /*MI*/0, /*Op*/0, /*RC*/GIMT_Encode2(AMDGPU::VGPR_32RegClassID),
        GIM_CheckComplexPattern, /*MI*/0, /*Op*/1, /*Renderer*/GIMT_Encode2(0), GIMT_Encode2(GICP_gi_vop3mods0),
        GIM_CheckComplexPattern, /*MI*/0, /*Op*/2, /*Renderer*/GIMT_Encode2(1), GIMT_Encode2(GICP_gi_vop3mods),
        // (fsub:{ *:[f32] } (VOP3Mods0:{ *:[f32] } f32:{ *:[f32] }:$src0, i32:{ *:[i32] }:$src0_modifiers, i1:{ *:[i1] }:$clamp, i32:{ *:[i32] }:$omod), (VOP3Mods:{ *:[f32] } f32:{ *:[f32] }:$src1, i32:{ *:[i32] }:$src1_modifiers))  =>  (V_SUB_F32_e64:{ *:[f32] } i32:{ *:[i32] }:$src0_modifiers, f32:{ *:[f32] }:$src0, i32:{ *:[i32] }:$src1_modifiers, f32:{ *:[f32] }:$src1, i1:{ *:[i1] }:$clamp, i32:{ *:[i32] }:$omod)
        GIR_BuildMI, /*InsnID*/0, /*Opcode*/GIMT_Encode2(AMDGPU::V_SUB_F32_e64),
        GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/0, // DstI[vdst]
        GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/1, // src0_modifiers
        GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/0, // src0
        GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(1), /*SubOperand*/1, // src1_modifiers
        GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(1), /*SubOperand*/0, // src1
        GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/2, // clamp
        GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/3, // omod
        GIR_ConstrainSelectedInstOperands, /*InsnID*/0,
        GIR_EraseFromParent, /*InsnID*/0,
        // GIR_Coverage, 726,
        GIR_Done,
      // Label 4029: @255020
      GIM_Reject,
    // Label 4027: @255021
    GIM_Reject,
    // Label 4021: @255022
    GIM_Reject,
    // Label 58: @255023
    GIM_SwitchType, /*MI*/0, /*Op*/0, /*[*/GIMT_Encode2(8), GIMT_Encode2(13), /*)*//*default:*//*Label 4035*/ GIMT_Encode4(256629),
    /*GILLT_s16*//*Label 4030*/ GIMT_Encode4(255054),
    /*GILLT_s32*//*Label 4031*/ GIMT_Encode4(255528),
    /*GILLT_s64*//*Label 4032*/ GIMT_Encode4(255716),
    /*GILLT_v2s16*//*Label 4033*/ GIMT_Encode4(256464),
    /*GILLT_v2s32*//*Label 4034*/ GIMT_Encode4(256545),
    // Label 4030: @255054
    GIM_Try, /*On fail goto*//*Label 4036*/ GIMT_Encode4(255527),
      GIM_CheckType, /*MI*/0, /*Op*/1, /*Type*/GILLT_s16,
      GIM_CheckType, /*MI*/0, /*Op*/2, /*Type*/GILLT_s16,
      GIM_Try, /*On fail goto*//*Label 4037*/ GIMT_Encode4(255106), // Rule ID 101 //
        GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasSALUFloatInsts),
        GIM_CheckRegBankForClass, /*MI*/0, /*Op*/0, /*RC*/GIMT_Encode2(AMDGPU::SReg_32RegClassID),
        GIM_CheckRegBankForClass, /*MI*/0, /*Op*/1, /*RC*/GIMT_Encode2(AMDGPU::SReg_32RegClassID),
        GIM_CheckRegBankForClass, /*MI*/0, /*Op*/2, /*RC*/GIMT_Encode2(AMDGPU::SReg_32RegClassID),
        GIM_CheckCxxInsnPredicate, /*MI*/0, /*FnId*/GIMT_Encode2(GICXXPred_MI_Predicate_anonymous_17633),
        // (fmul:{ *:[f16] } SSrc_f16:{ *:[f16] }:$src0, SSrc_f16:{ *:[f16] }:$src1)<<P:Predicate_anonymous_17633>>  =>  (S_MUL_F16:{ *:[f16] } SSrc_f16:{ *:[f16] }:$src0, SSrc_f16:{ *:[f16] }:$src1)
        GIR_MutateOpcode, /*InsnID*/0, /*RecycleInsnID*/0, /*Opcode*/GIMT_Encode2(AMDGPU::S_MUL_F16),
        GIR_AddImplicitUse, /*InsnID*/0, GIMT_Encode2(AMDGPU::MODE),
        GIR_ConstrainSelectedInstOperands, /*InsnID*/0,
        // GIR_Coverage, 101,
        GIR_Done,
      // Label 4037: @255106
      GIM_Try, /*On fail goto*//*Label 4038*/ GIMT_Encode4(255176), // Rule ID 806 //
        GIM_CheckFeatures, GIMT_Encode2(GIFBS_Has16BitInsts_NotHasTrue16BitInsts),
        GIM_CheckRegBankForClass, /*MI*/0, /*Op*/0, /*RC*/GIMT_Encode2(AMDGPU::VGPR_32RegClassID),
        GIM_CheckComplexPattern, /*MI*/0, /*Op*/1, /*Renderer*/GIMT_Encode2(0), GIMT_Encode2(GICP_gi_vop3mods0),
        GIM_CheckComplexPattern, /*MI*/0, /*Op*/2, /*Renderer*/GIMT_Encode2(1), GIMT_Encode2(GICP_gi_vop3mods),
        // (fmul:{ *:[f16] } (VOP3Mods0:{ *:[f16] } f16:{ *:[f16] }:$src0, i32:{ *:[i32] }:$src0_modifiers, i1:{ *:[i1] }:$clamp, i32:{ *:[i32] }:$omod), (VOP3Mods:{ *:[f16] } f16:{ *:[f16] }:$src1, i32:{ *:[i32] }:$src1_modifiers))  =>  (V_MUL_F16_e64:{ *:[f16] } i32:{ *:[i32] }:$src0_modifiers, f16:{ *:[f16] }:$src0, i32:{ *:[i32] }:$src1_modifiers, f16:{ *:[f16] }:$src1, i1:{ *:[i1] }:$clamp, i32:{ *:[i32] }:$omod)
        GIR_BuildMI, /*InsnID*/0, /*Opcode*/GIMT_Encode2(AMDGPU::V_MUL_F16_e64),
        GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/0, // DstI[vdst]
        GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/1, // src0_modifiers
        GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/0, // src0
        GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(1), /*SubOperand*/1, // src1_modifiers
        GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(1), /*SubOperand*/0, // src1
        GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/2, // clamp
        GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/3, // omod
        GIR_ConstrainSelectedInstOperands, /*InsnID*/0,
        GIR_EraseFromParent, /*InsnID*/0,
        // GIR_Coverage, 806,
        GIR_Done,
      // Label 4038: @255176
      GIM_Try, /*On fail goto*//*Label 4039*/ GIMT_Encode4(255246), // Rule ID 808 //
        GIM_CheckFeatures, GIMT_Encode2(GIFBS_UseRealTrue16Insts),
        GIM_CheckRegBankForClass, /*MI*/0, /*Op*/0, /*RC*/GIMT_Encode2(AMDGPU::VGPR_16RegClassID),
        GIM_CheckComplexPattern, /*MI*/0, /*Op*/1, /*Renderer*/GIMT_Encode2(0), GIMT_Encode2(GICP_gi_vop3mods0),
        GIM_CheckComplexPattern, /*MI*/0, /*Op*/2, /*Renderer*/GIMT_Encode2(1), GIMT_Encode2(GICP_gi_vop3mods),
        // (fmul:{ *:[f16] } (VOP3Mods0:{ *:[f16] } f16:{ *:[f16] }:$src0, i32:{ *:[i32] }:$src0_modifiers, i1:{ *:[i1] }:$clamp, i32:{ *:[i32] }:$omod), (VOP3Mods:{ *:[f16] } f16:{ *:[f16] }:$src1, i32:{ *:[i32] }:$src1_modifiers))  =>  (V_MUL_F16_t16_e64:{ *:[f16] } i32:{ *:[i32] }:$src0_modifiers, f16:{ *:[f16] }:$src0, i32:{ *:[i32] }:$src1_modifiers, f16:{ *:[f16] }:$src1, i1:{ *:[i1] }:$clamp, i32:{ *:[i32] }:$omod)
        GIR_BuildMI, /*InsnID*/0, /*Opcode*/GIMT_Encode2(AMDGPU::V_MUL_F16_t16_e64),
        GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/0, // DstI[vdst]
        GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/1, // src0_modifiers
        GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/0, // src0
        GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(1), /*SubOperand*/1, // src1_modifiers
        GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(1), /*SubOperand*/0, // src1
        GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/2, // clamp
        GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/3, // omod
        GIR_ConstrainSelectedInstOperands, /*InsnID*/0,
        GIR_EraseFromParent, /*InsnID*/0,
        // GIR_Coverage, 808,
        GIR_Done,
      // Label 4039: @255246
      GIM_Try, /*On fail goto*//*Label 4040*/ GIMT_Encode4(255316), // Rule ID 810 //
        GIM_CheckFeatures, GIMT_Encode2(GIFBS_UseFakeTrue16Insts),
        GIM_CheckRegBankForClass, /*MI*/0, /*Op*/0, /*RC*/GIMT_Encode2(AMDGPU::VGPR_32RegClassID),
        GIM_CheckComplexPattern, /*MI*/0, /*Op*/1, /*Renderer*/GIMT_Encode2(0), GIMT_Encode2(GICP_gi_vop3mods0),
        GIM_CheckComplexPattern, /*MI*/0, /*Op*/2, /*Renderer*/GIMT_Encode2(1), GIMT_Encode2(GICP_gi_vop3mods),
        // (fmul:{ *:[f16] } (VOP3Mods0:{ *:[f16] } f16:{ *:[f16] }:$src0, i32:{ *:[i32] }:$src0_modifiers, i1:{ *:[i1] }:$clamp, i32:{ *:[i32] }:$omod), (VOP3Mods:{ *:[f16] } f16:{ *:[f16] }:$src1, i32:{ *:[i32] }:$src1_modifiers))  =>  (V_MUL_F16_fake16_e64:{ *:[f16] } i32:{ *:[i32] }:$src0_modifiers, f16:{ *:[f16] }:$src0, i32:{ *:[i32] }:$src1_modifiers, f16:{ *:[f16] }:$src1, i1:{ *:[i1] }:$clamp, i32:{ *:[i32] }:$omod)
        GIR_BuildMI, /*InsnID*/0, /*Opcode*/GIMT_Encode2(AMDGPU::V_MUL_F16_fake16_e64),
        GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/0, // DstI[vdst]
        GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/1, // src0_modifiers
        GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/0, // src0
        GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(1), /*SubOperand*/1, // src1_modifiers
        GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(1), /*SubOperand*/0, // src1
        GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/2, // clamp
        GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/3, // omod
        GIR_ConstrainSelectedInstOperands, /*InsnID*/0,
        GIR_EraseFromParent, /*InsnID*/0,
        // GIR_Coverage, 810,
        GIR_Done,
      // Label 4040: @255316
      GIM_Try, /*On fail goto*//*Label 4041*/ GIMT_Encode4(255386), // Rule ID 7143 //
        GIM_CheckFeatures, GIMT_Encode2(GIFBS_Has16BitInsts_NotHasTrue16BitInsts),
        GIM_CheckRegBankForClass, /*MI*/0, /*Op*/0, /*RC*/GIMT_Encode2(AMDGPU::VGPR_32RegClassID),
        GIM_CheckComplexPattern, /*MI*/0, /*Op*/1, /*Renderer*/GIMT_Encode2(0), GIMT_Encode2(GICP_gi_vop3mods),
        GIM_CheckComplexPattern, /*MI*/0, /*Op*/2, /*Renderer*/GIMT_Encode2(1), GIMT_Encode2(GICP_gi_vop3mods0),
        // (fmul:{ *:[f16] } (VOP3Mods:{ *:[f16] } f16:{ *:[f16] }:$src1, i32:{ *:[i32] }:$src1_modifiers), (VOP3Mods0:{ *:[f16] } f16:{ *:[f16] }:$src0, i32:{ *:[i32] }:$src0_modifiers, i1:{ *:[i1] }:$clamp, i32:{ *:[i32] }:$omod))  =>  (V_MUL_F16_e64:{ *:[f16] } i32:{ *:[i32] }:$src0_modifiers, f16:{ *:[f16] }:$src0, i32:{ *:[i32] }:$src1_modifiers, f16:{ *:[f16] }:$src1, i1:{ *:[i1] }:$clamp, i32:{ *:[i32] }:$omod)
        GIR_BuildMI, /*InsnID*/0, /*Opcode*/GIMT_Encode2(AMDGPU::V_MUL_F16_e64),
        GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/0, // DstI[vdst]
        GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(1), /*SubOperand*/1, // src0_modifiers
        GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(1), /*SubOperand*/0, // src0
        GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/1, // src1_modifiers
        GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/0, // src1
        GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(1), /*SubOperand*/2, // clamp
        GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(1), /*SubOperand*/3, // omod
        GIR_ConstrainSelectedInstOperands, /*InsnID*/0,
        GIR_EraseFromParent, /*InsnID*/0,
        // GIR_Coverage, 7143,
        GIR_Done,
      // Label 4041: @255386
      GIM_Try, /*On fail goto*//*Label 4042*/ GIMT_Encode4(255456), // Rule ID 7145 //
        GIM_CheckFeatures, GIMT_Encode2(GIFBS_UseRealTrue16Insts),
        GIM_CheckRegBankForClass, /*MI*/0, /*Op*/0, /*RC*/GIMT_Encode2(AMDGPU::VGPR_16RegClassID),
        GIM_CheckComplexPattern, /*MI*/0, /*Op*/1, /*Renderer*/GIMT_Encode2(0), GIMT_Encode2(GICP_gi_vop3mods),
        GIM_CheckComplexPattern, /*MI*/0, /*Op*/2, /*Renderer*/GIMT_Encode2(1), GIMT_Encode2(GICP_gi_vop3mods0),
        // (fmul:{ *:[f16] } (VOP3Mods:{ *:[f16] } f16:{ *:[f16] }:$src1, i32:{ *:[i32] }:$src1_modifiers), (VOP3Mods0:{ *:[f16] } f16:{ *:[f16] }:$src0, i32:{ *:[i32] }:$src0_modifiers, i1:{ *:[i1] }:$clamp, i32:{ *:[i32] }:$omod))  =>  (V_MUL_F16_t16_e64:{ *:[f16] } i32:{ *:[i32] }:$src0_modifiers, f16:{ *:[f16] }:$src0, i32:{ *:[i32] }:$src1_modifiers, f16:{ *:[f16] }:$src1, i1:{ *:[i1] }:$clamp, i32:{ *:[i32] }:$omod)
        GIR_BuildMI, /*InsnID*/0, /*Opcode*/GIMT_Encode2(AMDGPU::V_MUL_F16_t16_e64),
        GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/0, // DstI[vdst]
        GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(1), /*SubOperand*/1, // src0_modifiers
        GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(1), /*SubOperand*/0, // src0
        GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/1, // src1_modifiers
        GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/0, // src1
        GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(1), /*SubOperand*/2, // clamp
        GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(1), /*SubOperand*/3, // omod
        GIR_ConstrainSelectedInstOperands, /*InsnID*/0,
        GIR_EraseFromParent, /*InsnID*/0,
        // GIR_Coverage, 7145,
        GIR_Done,
      // Label 4042: @255456
      GIM_Try, /*On fail goto*//*Label 4043*/ GIMT_Encode4(255526), // Rule ID 7147 //
        GIM_CheckFeatures, GIMT_Encode2(GIFBS_UseFakeTrue16Insts),
        GIM_CheckRegBankForClass, /*MI*/0, /*Op*/0, /*RC*/GIMT_Encode2(AMDGPU::VGPR_32RegClassID),
        GIM_CheckComplexPattern, /*MI*/0, /*Op*/1, /*Renderer*/GIMT_Encode2(0), GIMT_Encode2(GICP_gi_vop3mods),
        GIM_CheckComplexPattern, /*MI*/0, /*Op*/2, /*Renderer*/GIMT_Encode2(1), GIMT_Encode2(GICP_gi_vop3mods0),
        // (fmul:{ *:[f16] } (VOP3Mods:{ *:[f16] } f16:{ *:[f16] }:$src1, i32:{ *:[i32] }:$src1_modifiers), (VOP3Mods0:{ *:[f16] } f16:{ *:[f16] }:$src0, i32:{ *:[i32] }:$src0_modifiers, i1:{ *:[i1] }:$clamp, i32:{ *:[i32] }:$omod))  =>  (V_MUL_F16_fake16_e64:{ *:[f16] } i32:{ *:[i32] }:$src0_modifiers, f16:{ *:[f16] }:$src0, i32:{ *:[i32] }:$src1_modifiers, f16:{ *:[f16] }:$src1, i1:{ *:[i1] }:$clamp, i32:{ *:[i32] }:$omod)
        GIR_BuildMI, /*InsnID*/0, /*Opcode*/GIMT_Encode2(AMDGPU::V_MUL_F16_fake16_e64),
        GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/0, // DstI[vdst]
        GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(1), /*SubOperand*/1, // src0_modifiers
        GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(1), /*SubOperand*/0, // src0
        GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/1, // src1_modifiers
        GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/0, // src1
        GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(1), /*SubOperand*/2, // clamp
        GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(1), /*SubOperand*/3, // omod
        GIR_ConstrainSelectedInstOperands, /*InsnID*/0,
        GIR_EraseFromParent, /*InsnID*/0,
        // GIR_Coverage, 7147,
        GIR_Done,
      // Label 4043: @255526
      GIM_Reject,
    // Label 4036: @255527
    GIM_Reject,
    // Label 4031: @255528
    GIM_Try, /*On fail goto*//*Label 4044*/ GIMT_Encode4(255715),
      GIM_CheckType, /*MI*/0, /*Op*/1, /*Type*/GILLT_s32,
      GIM_CheckType, /*MI*/0, /*Op*/2, /*Type*/GILLT_s32,
      GIM_Try, /*On fail goto*//*Label 4045*/ GIMT_Encode4(255580), // Rule ID 97 //
        GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasSALUFloatInsts),
        GIM_CheckRegBankForClass, /*MI*/0, /*Op*/0, /*RC*/GIMT_Encode2(AMDGPU::SReg_32RegClassID),
        GIM_CheckRegBankForClass, /*MI*/0, /*Op*/1, /*RC*/GIMT_Encode2(AMDGPU::SReg_32RegClassID),
        GIM_CheckRegBankForClass, /*MI*/0, /*Op*/2, /*RC*/GIMT_Encode2(AMDGPU::SReg_32RegClassID),
        GIM_CheckCxxInsnPredicate, /*MI*/0, /*FnId*/GIMT_Encode2(GICXXPred_MI_Predicate_anonymous_17633),
        // (fmul:{ *:[f32] } SSrc_f32:{ *:[f32] }:$src0, SSrc_f32:{ *:[f32] }:$src1)<<P:Predicate_anonymous_17633>>  =>  (S_MUL_F32:{ *:[f32] } SSrc_f32:{ *:[f32] }:$src0, SSrc_f32:{ *:[f32] }:$src1)
        GIR_MutateOpcode, /*InsnID*/0, /*RecycleInsnID*/0, /*Opcode*/GIMT_Encode2(AMDGPU::S_MUL_F32),
        GIR_AddImplicitUse, /*InsnID*/0, GIMT_Encode2(AMDGPU::MODE),
        GIR_ConstrainSelectedInstOperands, /*InsnID*/0,
        // GIR_Coverage, 97,
        GIR_Done,
      // Label 4045: @255580
      GIM_Try, /*On fail goto*//*Label 4046*/ GIMT_Encode4(255647), // Rule ID 730 //
        GIM_CheckRegBankForClass, /*MI*/0, /*Op*/0, /*RC*/GIMT_Encode2(AMDGPU::VGPR_32RegClassID),
        GIM_CheckComplexPattern, /*MI*/0, /*Op*/1, /*Renderer*/GIMT_Encode2(0), GIMT_Encode2(GICP_gi_vop3mods0),
        GIM_CheckComplexPattern, /*MI*/0, /*Op*/2, /*Renderer*/GIMT_Encode2(1), GIMT_Encode2(GICP_gi_vop3mods),
        // (fmul:{ *:[f32] } (VOP3Mods0:{ *:[f32] } f32:{ *:[f32] }:$src0, i32:{ *:[i32] }:$src0_modifiers, i1:{ *:[i1] }:$clamp, i32:{ *:[i32] }:$omod), (VOP3Mods:{ *:[f32] } f32:{ *:[f32] }:$src1, i32:{ *:[i32] }:$src1_modifiers))  =>  (V_MUL_F32_e64:{ *:[f32] } i32:{ *:[i32] }:$src0_modifiers, f32:{ *:[f32] }:$src0, i32:{ *:[i32] }:$src1_modifiers, f32:{ *:[f32] }:$src1, i1:{ *:[i1] }:$clamp, i32:{ *:[i32] }:$omod)
        GIR_BuildMI, /*InsnID*/0, /*Opcode*/GIMT_Encode2(AMDGPU::V_MUL_F32_e64),
        GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/0, // DstI[vdst]
        GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/1, // src0_modifiers
        GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/0, // src0
        GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(1), /*SubOperand*/1, // src1_modifiers
        GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(1), /*SubOperand*/0, // src1
        GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/2, // clamp
        GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/3, // omod
        GIR_ConstrainSelectedInstOperands, /*InsnID*/0,
        GIR_EraseFromParent, /*InsnID*/0,
        // GIR_Coverage, 730,
        GIR_Done,
      // Label 4046: @255647
      GIM_Try, /*On fail goto*//*Label 4047*/ GIMT_Encode4(255714), // Rule ID 7130 //
        GIM_CheckRegBankForClass, /*MI*/0, /*Op*/0, /*RC*/GIMT_Encode2(AMDGPU::VGPR_32RegClassID),
        GIM_CheckComplexPattern, /*MI*/0, /*Op*/1, /*Renderer*/GIMT_Encode2(0), GIMT_Encode2(GICP_gi_vop3mods),
        GIM_CheckComplexPattern, /*MI*/0, /*Op*/2, /*Renderer*/GIMT_Encode2(1), GIMT_Encode2(GICP_gi_vop3mods0),
        // (fmul:{ *:[f32] } (VOP3Mods:{ *:[f32] } f32:{ *:[f32] }:$src1, i32:{ *:[i32] }:$src1_modifiers), (VOP3Mods0:{ *:[f32] } f32:{ *:[f32] }:$src0, i32:{ *:[i32] }:$src0_modifiers, i1:{ *:[i1] }:$clamp, i32:{ *:[i32] }:$omod))  =>  (V_MUL_F32_e64:{ *:[f32] } i32:{ *:[i32] }:$src0_modifiers, f32:{ *:[f32] }:$src0, i32:{ *:[i32] }:$src1_modifiers, f32:{ *:[f32] }:$src1, i1:{ *:[i1] }:$clamp, i32:{ *:[i32] }:$omod)
        GIR_BuildMI, /*InsnID*/0, /*Opcode*/GIMT_Encode2(AMDGPU::V_MUL_F32_e64),
        GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/0, // DstI[vdst]
        GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(1), /*SubOperand*/1, // src0_modifiers
        GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(1), /*SubOperand*/0, // src0
        GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/1, // src1_modifiers
        GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/0, // src1
        GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(1), /*SubOperand*/2, // clamp
        GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(1), /*SubOperand*/3, // omod
        GIR_ConstrainSelectedInstOperands, /*InsnID*/0,
        GIR_EraseFromParent, /*InsnID*/0,
        // GIR_Coverage, 7130,
        GIR_Done,
      // Label 4047: @255714
      GIM_Reject,
    // Label 4044: @255715
    GIM_Reject,
    // Label 4032: @255716
    GIM_Try, /*On fail goto*//*Label 4048*/ GIMT_Encode4(256463),
      GIM_CheckType, /*MI*/0, /*Op*/1, /*Type*/GILLT_s64,
      GIM_CheckType, /*MI*/0, /*Op*/2, /*Type*/GILLT_s64,
      GIM_CheckRegBankForClass, /*MI*/0, /*Op*/0, /*RC*/GIMT_Encode2(AMDGPU::VReg_64RegClassID),
      GIM_Try, /*On fail goto*//*Label 4049*/ GIMT_Encode4(255814), // Rule ID 6559 //
        GIM_RecordInsn, /*DefineMI*/1, /*MI*/0, /*OpIdx*/2, // MIs[1]
        GIM_CheckOpcode, /*MI*/1, GIMT_Encode2(TargetOpcode::G_FCONSTANT),
        GIM_CheckAPFloatImmPredicate, /*MI*/1, /*Predicate*/GIMT_Encode2(GICXXPred_APFloat_Predicate_fpimm_pos_pow2_prefer_ldexp_f64),
        // MIs[1] Operand 1
        // No operand predicates
        GIM_CheckIsSafeToFold, /*InsnID*/1,
        GIM_CheckComplexPattern, /*MI*/0, /*Op*/1, /*Renderer*/GIMT_Encode2(0), GIMT_Encode2(GICP_gi_vop3mods),
        // (fmul:{ *:[f64] } (VOP3Mods:{ *:[f64] } f64:{ *:[f64] }:$src0, i32:{ *:[i32] }:$src0_mods), (fpimm:{ *:[f64] })<<P:Predicate_fpimm_pos_pow2_prefer_ldexp_f64>><<X:FPPow2ToExponentXForm>>:$src1)  =>  (V_LDEXP_F64_e64:{ *:[f64] } i32:{ *:[i32] }:$src0_mods, VSrc_b64:{ *:[f64] }:$src0, 0:{ *:[i32] }, (S_MOV_B32:{ *:[i16] } (FPPow2ToExponentXForm:{ *:[i32] } ?:{ *:[f64] }:$src1)))
        GIR_MakeTempReg, /*TempRegID*/0, /*TypeID*/GILLT_s16,
        GIR_BuildMI, /*InsnID*/1, /*Opcode*/GIMT_Encode2(AMDGPU::S_MOV_B32),
        GIR_AddTempRegister, /*InsnID*/1, /*TempRegID*/0, /*TempRegFlags*/GIMT_Encode2(RegState::Define),
        GIR_CustomRenderer, /*InsnID*/1, /*OldInsnID*/1, /*Renderer*/GIMT_Encode2(GICR_renderFPPow2ToExponent), // src1
        GIR_ConstrainSelectedInstOperands, /*InsnID*/1,
        GIR_BuildMI, /*InsnID*/0, /*Opcode*/GIMT_Encode2(AMDGPU::V_LDEXP_F64_e64),
        GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/0, // DstI[vdst]
        GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/1, // src0_mods
        GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/0, // src0
        GIR_AddImm8, /*InsnID*/0, /*Imm*/0,
        GIR_AddSimpleTempRegister, /*InsnID*/0, /*TempRegID*/0,
        GIR_AddImm8, /*InsnID*/0, /*Imm*/0,
        GIR_AddImm8, /*InsnID*/0, /*Imm*/0,
        GIR_ConstrainSelectedInstOperands, /*InsnID*/0,
        GIR_EraseFromParent, /*InsnID*/0,
        // GIR_Coverage, 6559,
        GIR_Done,
      // Label 4049: @255814
      GIM_Try, /*On fail goto*//*Label 4050*/ GIMT_Encode4(255894), // Rule ID 10805 //
        GIM_RecordInsn, /*DefineMI*/1, /*MI*/0, /*OpIdx*/1, // MIs[1]
        GIM_CheckOpcode, /*MI*/1, GIMT_Encode2(TargetOpcode::G_FCONSTANT),
        GIM_CheckAPFloatImmPredicate, /*MI*/1, /*Predicate*/GIMT_Encode2(GICXXPred_APFloat_Predicate_fpimm_pos_pow2_prefer_ldexp_f64),
        // MIs[1] Operand 1
        // No operand predicates
        GIM_CheckIsSafeToFold, /*InsnID*/1,
        GIM_CheckComplexPattern, /*MI*/0, /*Op*/2, /*Renderer*/GIMT_Encode2(0), GIMT_Encode2(GICP_gi_vop3mods),
        // (fmul:{ *:[f64] } (fpimm:{ *:[f64] })<<P:Predicate_fpimm_pos_pow2_prefer_ldexp_f64>><<X:FPPow2ToExponentXForm>>:$src1, (VOP3Mods:{ *:[f64] } f64:{ *:[f64] }:$src0, i32:{ *:[i32] }:$src0_mods))  =>  (V_LDEXP_F64_e64:{ *:[f64] } i32:{ *:[i32] }:$src0_mods, VSrc_b64:{ *:[f64] }:$src0, 0:{ *:[i32] }, (S_MOV_B32:{ *:[i16] } (FPPow2ToExponentXForm:{ *:[i32] } ?:{ *:[f64] }:$src1)))
        GIR_MakeTempReg, /*TempRegID*/0, /*TypeID*/GILLT_s16,
        GIR_BuildMI, /*InsnID*/1, /*Opcode*/GIMT_Encode2(AMDGPU::S_MOV_B32),
        GIR_AddTempRegister, /*InsnID*/1, /*TempRegID*/0, /*TempRegFlags*/GIMT_Encode2(RegState::Define),
        GIR_CustomRenderer, /*InsnID*/1, /*OldInsnID*/1, /*Renderer*/GIMT_Encode2(GICR_renderFPPow2ToExponent), // src1
        GIR_ConstrainSelectedInstOperands, /*InsnID*/1,
        GIR_BuildMI, /*InsnID*/0, /*Opcode*/GIMT_Encode2(AMDGPU::V_LDEXP_F64_e64),
        GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/0, // DstI[vdst]
        GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/1, // src0_mods
        GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/0, // src0
        GIR_AddImm8, /*InsnID*/0, /*Imm*/0,
        GIR_AddSimpleTempRegister, /*InsnID*/0, /*TempRegID*/0,
        GIR_AddImm8, /*InsnID*/0, /*Imm*/0,
        GIR_AddImm8, /*InsnID*/0, /*Imm*/0,
        GIR_ConstrainSelectedInstOperands, /*InsnID*/0,
        GIR_EraseFromParent, /*InsnID*/0,
        // GIR_Coverage, 10805,
        GIR_Done,
      // Label 4050: @255894
      GIM_Try, /*On fail goto*//*Label 4051*/ GIMT_Encode4(255978), // Rule ID 6563 //
        GIM_RecordInsn, /*DefineMI*/1, /*MI*/0, /*OpIdx*/1, // MIs[1]
        GIM_CheckOpcode, /*MI*/1, GIMT_Encode2(TargetOpcode::G_FABS),
        GIM_CheckType, /*MI*/1, /*Op*/1, /*Type*/GILLT_s64,
        GIM_RecordInsn, /*DefineMI*/2, /*MI*/0, /*OpIdx*/2, // MIs[2]
        GIM_CheckOpcode, /*MI*/2, GIMT_Encode2(TargetOpcode::G_FCONSTANT),
        GIM_CheckAPFloatImmPredicate, /*MI*/2, /*Predicate*/GIMT_Encode2(GICXXPred_APFloat_Predicate_fpimm_neg_pow2_prefer_ldexp_f64),
        // MIs[2] Operand 1
        // No operand predicates
        GIM_CheckIsSafeToFold, /*InsnID*/1,
        GIM_CheckIsSafeToFold, /*InsnID*/2,
        // (fmul:{ *:[f64] } (fabs:{ *:[f64] } f64:{ *:[f64] }:$src0), (fpimm:{ *:[f64] })<<P:Predicate_fpimm_neg_pow2_prefer_ldexp_f64>><<X:FPPow2ToExponentXForm>>:$src1)  =>  (V_LDEXP_F64_e64:{ *:[f64] } 3:{ *:[i32] }, VSrc_b64:{ *:[f64] }:$src0, 0:{ *:[i32] }, (S_MOV_B32:{ *:[i16] } (FPPow2ToExponentXForm:{ *:[i32] } ?:{ *:[f64] }:$src1)))
        GIR_MakeTempReg, /*TempRegID*/0, /*TypeID*/GILLT_s16,
        GIR_BuildMI, /*InsnID*/1, /*Opcode*/GIMT_Encode2(AMDGPU::S_MOV_B32),
        GIR_AddTempRegister, /*InsnID*/1, /*TempRegID*/0, /*TempRegFlags*/GIMT_Encode2(RegState::Define),
        GIR_CustomRenderer, /*InsnID*/1, /*OldInsnID*/2, /*Renderer*/GIMT_Encode2(GICR_renderFPPow2ToExponent), // src1
        GIR_ConstrainSelectedInstOperands, /*InsnID*/1,
        GIR_BuildMI, /*InsnID*/0, /*Opcode*/GIMT_Encode2(AMDGPU::V_LDEXP_F64_e64),
        GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/0, // DstI[vdst]
        GIR_AddImm8, /*InsnID*/0, /*Imm*/3,
        GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/1, /*OpIdx*/1, // src0
        GIR_AddImm8, /*InsnID*/0, /*Imm*/0,
        GIR_AddSimpleTempRegister, /*InsnID*/0, /*TempRegID*/0,
        GIR_AddImm8, /*InsnID*/0, /*Imm*/0,
        GIR_AddImm8, /*InsnID*/0, /*Imm*/0,
        GIR_ConstrainSelectedInstOperands, /*InsnID*/0,
        GIR_EraseFromParent, /*InsnID*/0,
        // GIR_Coverage, 6563,
        GIR_Done,
      // Label 4051: @255978
      GIM_Try, /*On fail goto*//*Label 4052*/ GIMT_Encode4(256062), // Rule ID 10809 //
        GIM_RecordInsn, /*DefineMI*/1, /*MI*/0, /*OpIdx*/1, // MIs[1]
        GIM_CheckOpcode, /*MI*/1, GIMT_Encode2(TargetOpcode::G_FCONSTANT),
        GIM_CheckAPFloatImmPredicate, /*MI*/1, /*Predicate*/GIMT_Encode2(GICXXPred_APFloat_Predicate_fpimm_neg_pow2_prefer_ldexp_f64),
        // MIs[1] Operand 1
        // No operand predicates
        GIM_RecordInsn, /*DefineMI*/2, /*MI*/0, /*OpIdx*/2, // MIs[2]
        GIM_CheckOpcode, /*MI*/2, GIMT_Encode2(TargetOpcode::G_FABS),
        GIM_CheckType, /*MI*/2, /*Op*/1, /*Type*/GILLT_s64,
        GIM_CheckIsSafeToFold, /*InsnID*/1,
        GIM_CheckIsSafeToFold, /*InsnID*/2,
        // (fmul:{ *:[f64] } (fpimm:{ *:[f64] })<<P:Predicate_fpimm_neg_pow2_prefer_ldexp_f64>><<X:FPPow2ToExponentXForm>>:$src1, (fabs:{ *:[f64] } f64:{ *:[f64] }:$src0))  =>  (V_LDEXP_F64_e64:{ *:[f64] } 3:{ *:[i32] }, VSrc_b64:{ *:[f64] }:$src0, 0:{ *:[i32] }, (S_MOV_B32:{ *:[i16] } (FPPow2ToExponentXForm:{ *:[i32] } ?:{ *:[f64] }:$src1)))
        GIR_MakeTempReg, /*TempRegID*/0, /*TypeID*/GILLT_s16,
        GIR_BuildMI, /*InsnID*/1, /*Opcode*/GIMT_Encode2(AMDGPU::S_MOV_B32),
        GIR_AddTempRegister, /*InsnID*/1, /*TempRegID*/0, /*TempRegFlags*/GIMT_Encode2(RegState::Define),
        GIR_CustomRenderer, /*InsnID*/1, /*OldInsnID*/1, /*Renderer*/GIMT_Encode2(GICR_renderFPPow2ToExponent), // src1
        GIR_ConstrainSelectedInstOperands, /*InsnID*/1,
        GIR_BuildMI, /*InsnID*/0, /*Opcode*/GIMT_Encode2(AMDGPU::V_LDEXP_F64_e64),
        GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/0, // DstI[vdst]
        GIR_AddImm8, /*InsnID*/0, /*Imm*/3,
        GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/2, /*OpIdx*/1, // src0
        GIR_AddImm8, /*InsnID*/0, /*Imm*/0,
        GIR_AddSimpleTempRegister, /*InsnID*/0, /*TempRegID*/0,
        GIR_AddImm8, /*InsnID*/0, /*Imm*/0,
        GIR_AddImm8, /*InsnID*/0, /*Imm*/0,
        GIR_ConstrainSelectedInstOperands, /*InsnID*/0,
        GIR_EraseFromParent, /*InsnID*/0,
        // GIR_Coverage, 10809,
        GIR_Done,
      // Label 4052: @256062
      GIM_Try, /*On fail goto*//*Label 4053*/ GIMT_Encode4(256132), // Rule ID 10807 //
        GIM_RecordInsn, /*DefineMI*/1, /*MI*/0, /*OpIdx*/1, // MIs[1]
        GIM_CheckOpcode, /*MI*/1, GIMT_Encode2(TargetOpcode::G_FCONSTANT),
        GIM_CheckAPFloatImmPredicate, /*MI*/1, /*Predicate*/GIMT_Encode2(GICXXPred_APFloat_Predicate_fpimm_neg_pow2_prefer_ldexp_f64),
        // MIs[1] Operand 1
        // No operand predicates
        GIM_CheckIsSafeToFold, /*InsnID*/1,
        // (fmul:{ *:[f64] } (fpimm:{ *:[f64] })<<P:Predicate_fpimm_neg_pow2_prefer_ldexp_f64>><<X:FPPow2ToExponentXForm>>:$src1, f64:{ *:[f64] }:$src0)  =>  (V_LDEXP_F64_e64:{ *:[f64] } 1:{ *:[i32] }, VSrc_b64:{ *:[f64] }:$src0, 0:{ *:[i32] }, (S_MOV_B32:{ *:[i16] } (FPPow2ToExponentXForm:{ *:[i32] } ?:{ *:[f64] }:$src1)))
        GIR_MakeTempReg, /*TempRegID*/0, /*TypeID*/GILLT_s16,
        GIR_BuildMI, /*InsnID*/1, /*Opcode*/GIMT_Encode2(AMDGPU::S_MOV_B32),
        GIR_AddTempRegister, /*InsnID*/1, /*TempRegID*/0, /*TempRegFlags*/GIMT_Encode2(RegState::Define),
        GIR_CustomRenderer, /*InsnID*/1, /*OldInsnID*/1, /*Renderer*/GIMT_Encode2(GICR_renderFPPow2ToExponent), // src1
        GIR_ConstrainSelectedInstOperands, /*InsnID*/1,
        GIR_BuildMI, /*InsnID*/0, /*Opcode*/GIMT_Encode2(AMDGPU::V_LDEXP_F64_e64),
        GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/0, // DstI[vdst]
        GIR_AddImm8, /*InsnID*/0, /*Imm*/1,
        GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/2, // src0
        GIR_AddImm8, /*InsnID*/0, /*Imm*/0,
        GIR_AddSimpleTempRegister, /*InsnID*/0, /*TempRegID*/0,
        GIR_AddImm8, /*InsnID*/0, /*Imm*/0,
        GIR_AddImm8, /*InsnID*/0, /*Imm*/0,
        GIR_ConstrainSelectedInstOperands, /*InsnID*/0,
        GIR_EraseFromParent, /*InsnID*/0,
        // GIR_Coverage, 10807,
        GIR_Done,
      // Label 4053: @256132
      GIM_Try, /*On fail goto*//*Label 4054*/ GIMT_Encode4(256202), // Rule ID 6561 //
        GIM_RecordInsn, /*DefineMI*/1, /*MI*/0, /*OpIdx*/2, // MIs[1]
        GIM_CheckOpcode, /*MI*/1, GIMT_Encode2(TargetOpcode::G_FCONSTANT),
        GIM_CheckAPFloatImmPredicate, /*MI*/1, /*Predicate*/GIMT_Encode2(GICXXPred_APFloat_Predicate_fpimm_neg_pow2_prefer_ldexp_f64),
        // MIs[1] Operand 1
        // No operand predicates
        GIM_CheckIsSafeToFold, /*InsnID*/1,
        // (fmul:{ *:[f64] } f64:{ *:[f64] }:$src0, (fpimm:{ *:[f64] })<<P:Predicate_fpimm_neg_pow2_prefer_ldexp_f64>><<X:FPPow2ToExponentXForm>>:$src1)  =>  (V_LDEXP_F64_e64:{ *:[f64] } 1:{ *:[i32] }, VSrc_b64:{ *:[f64] }:$src0, 0:{ *:[i32] }, (S_MOV_B32:{ *:[i16] } (FPPow2ToExponentXForm:{ *:[i32] } ?:{ *:[f64] }:$src1)))
        GIR_MakeTempReg, /*TempRegID*/0, /*TypeID*/GILLT_s16,
        GIR_BuildMI, /*InsnID*/1, /*Opcode*/GIMT_Encode2(AMDGPU::S_MOV_B32),
        GIR_AddTempRegister, /*InsnID*/1, /*TempRegID*/0, /*TempRegFlags*/GIMT_Encode2(RegState::Define),
        GIR_CustomRenderer, /*InsnID*/1, /*OldInsnID*/1, /*Renderer*/GIMT_Encode2(GICR_renderFPPow2ToExponent), // src1
        GIR_ConstrainSelectedInstOperands, /*InsnID*/1,
        GIR_BuildMI, /*InsnID*/0, /*Opcode*/GIMT_Encode2(AMDGPU::V_LDEXP_F64_e64),
        GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/0, // DstI[vdst]
        GIR_AddImm8, /*InsnID*/0, /*Imm*/1,
        GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/1, // src0
        GIR_AddImm8, /*InsnID*/0, /*Imm*/0,
        GIR_AddSimpleTempRegister, /*InsnID*/0, /*TempRegID*/0,
        GIR_AddImm8, /*InsnID*/0, /*Imm*/0,
        GIR_AddImm8, /*InsnID*/0, /*Imm*/0,
        GIR_ConstrainSelectedInstOperands, /*InsnID*/0,
        GIR_EraseFromParent, /*InsnID*/0,
        // GIR_Coverage, 6561,
        GIR_Done,
      // Label 4054: @256202
      GIM_Try, /*On fail goto*//*Label 4055*/ GIMT_Encode4(256267), // Rule ID 841 //
        GIM_CheckFeatures, GIMT_Encode2(GIFBS_isGFX12Plus),
        GIM_CheckComplexPattern, /*MI*/0, /*Op*/1, /*Renderer*/GIMT_Encode2(0), GIMT_Encode2(GICP_gi_vop3mods0),
        GIM_CheckComplexPattern, /*MI*/0, /*Op*/2, /*Renderer*/GIMT_Encode2(1), GIMT_Encode2(GICP_gi_vop3mods),
        // (fmul:{ *:[f64] } (VOP3Mods0:{ *:[f64] } f64:{ *:[f64] }:$src0, i32:{ *:[i32] }:$src0_modifiers, i1:{ *:[i1] }:$clamp, i32:{ *:[i32] }:$omod), (VOP3Mods:{ *:[f64] } f64:{ *:[f64] }:$src1, i32:{ *:[i32] }:$src1_modifiers))  =>  (V_MUL_F64_pseudo_e64:{ *:[f64] } i32:{ *:[i32] }:$src0_modifiers, f64:{ *:[f64] }:$src0, i32:{ *:[i32] }:$src1_modifiers, f64:{ *:[f64] }:$src1, i1:{ *:[i1] }:$clamp, i32:{ *:[i32] }:$omod)
        GIR_BuildMI, /*InsnID*/0, /*Opcode*/GIMT_Encode2(AMDGPU::V_MUL_F64_pseudo_e64),
        GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/0, // DstI[vdst]
        GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/1, // src0_modifiers
        GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/0, // src0
        GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(1), /*SubOperand*/1, // src1_modifiers
        GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(1), /*SubOperand*/0, // src1
        GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/2, // clamp
        GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/3, // omod
        GIR_ConstrainSelectedInstOperands, /*InsnID*/0,
        GIR_EraseFromParent, /*InsnID*/0,
        // GIR_Coverage, 841,
        GIR_Done,
      // Label 4055: @256267
      GIM_Try, /*On fail goto*//*Label 4056*/ GIMT_Encode4(256332), // Rule ID 860 //
        GIM_CheckFeatures, GIMT_Encode2(GIFBS_isNotGFX12Plus),
        GIM_CheckComplexPattern, /*MI*/0, /*Op*/1, /*Renderer*/GIMT_Encode2(0), GIMT_Encode2(GICP_gi_vop3mods0),
        GIM_CheckComplexPattern, /*MI*/0, /*Op*/2, /*Renderer*/GIMT_Encode2(1), GIMT_Encode2(GICP_gi_vop3mods),
        // (fmul:{ *:[f64] } (VOP3Mods0:{ *:[f64] } f64:{ *:[f64] }:$src0, i32:{ *:[i32] }:$src0_modifiers, i1:{ *:[i1] }:$clamp, i32:{ *:[i32] }:$omod), (VOP3Mods:{ *:[f64] } f64:{ *:[f64] }:$src1, i32:{ *:[i32] }:$src1_modifiers))  =>  (V_MUL_F64_e64:{ *:[f64] } i32:{ *:[i32] }:$src0_modifiers, f64:{ *:[f64] }:$src0, i32:{ *:[i32] }:$src1_modifiers, f64:{ *:[f64] }:$src1, i1:{ *:[i1] }:$clamp, i32:{ *:[i32] }:$omod)
        GIR_BuildMI, /*InsnID*/0, /*Opcode*/GIMT_Encode2(AMDGPU::V_MUL_F64_e64),
        GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/0, // DstI[vdst]
        GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/1, // src0_modifiers
        GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/0, // src0
        GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(1), /*SubOperand*/1, // src1_modifiers
        GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(1), /*SubOperand*/0, // src1
        GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/2, // clamp
        GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/3, // omod
        GIR_ConstrainSelectedInstOperands, /*InsnID*/0,
        GIR_EraseFromParent, /*InsnID*/0,
        // GIR_Coverage, 860,
        GIR_Done,
      // Label 4056: @256332
      GIM_Try, /*On fail goto*//*Label 4057*/ GIMT_Encode4(256397), // Rule ID 7164 //
        GIM_CheckFeatures, GIMT_Encode2(GIFBS_isGFX12Plus),
        GIM_CheckComplexPattern, /*MI*/0, /*Op*/1, /*Renderer*/GIMT_Encode2(0), GIMT_Encode2(GICP_gi_vop3mods),
        GIM_CheckComplexPattern, /*MI*/0, /*Op*/2, /*Renderer*/GIMT_Encode2(1), GIMT_Encode2(GICP_gi_vop3mods0),
        // (fmul:{ *:[f64] } (VOP3Mods:{ *:[f64] } f64:{ *:[f64] }:$src1, i32:{ *:[i32] }:$src1_modifiers), (VOP3Mods0:{ *:[f64] } f64:{ *:[f64] }:$src0, i32:{ *:[i32] }:$src0_modifiers, i1:{ *:[i1] }:$clamp, i32:{ *:[i32] }:$omod))  =>  (V_MUL_F64_pseudo_e64:{ *:[f64] } i32:{ *:[i32] }:$src0_modifiers, f64:{ *:[f64] }:$src0, i32:{ *:[i32] }:$src1_modifiers, f64:{ *:[f64] }:$src1, i1:{ *:[i1] }:$clamp, i32:{ *:[i32] }:$omod)
        GIR_BuildMI, /*InsnID*/0, /*Opcode*/GIMT_Encode2(AMDGPU::V_MUL_F64_pseudo_e64),
        GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/0, // DstI[vdst]
        GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(1), /*SubOperand*/1, // src0_modifiers
        GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(1), /*SubOperand*/0, // src0
        GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/1, // src1_modifiers
        GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/0, // src1
        GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(1), /*SubOperand*/2, // clamp
        GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(1), /*SubOperand*/3, // omod
        GIR_ConstrainSelectedInstOperands, /*InsnID*/0,
        GIR_EraseFromParent, /*InsnID*/0,
        // GIR_Coverage, 7164,
        GIR_Done,
      // Label 4057: @256397
      GIM_Try, /*On fail goto*//*Label 4058*/ GIMT_Encode4(256462), // Rule ID 7178 //
        GIM_CheckFeatures, GIMT_Encode2(GIFBS_isNotGFX12Plus),
        GIM_CheckComplexPattern, /*MI*/0, /*Op*/1, /*Renderer*/GIMT_Encode2(0), GIMT_Encode2(GICP_gi_vop3mods),
        GIM_CheckComplexPattern, /*MI*/0, /*Op*/2, /*Renderer*/GIMT_Encode2(1), GIMT_Encode2(GICP_gi_vop3mods0),
        // (fmul:{ *:[f64] } (VOP3Mods:{ *:[f64] } f64:{ *:[f64] }:$src1, i32:{ *:[i32] }:$src1_modifiers), (VOP3Mods0:{ *:[f64] } f64:{ *:[f64] }:$src0, i32:{ *:[i32] }:$src0_modifiers, i1:{ *:[i1] }:$clamp, i32:{ *:[i32] }:$omod))  =>  (V_MUL_F64_e64:{ *:[f64] } i32:{ *:[i32] }:$src0_modifiers, f64:{ *:[f64] }:$src0, i32:{ *:[i32] }:$src1_modifiers, f64:{ *:[f64] }:$src1, i1:{ *:[i1] }:$clamp, i32:{ *:[i32] }:$omod)
        GIR_BuildMI, /*InsnID*/0, /*Opcode*/GIMT_Encode2(AMDGPU::V_MUL_F64_e64),
        GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/0, // DstI[vdst]
        GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(1), /*SubOperand*/1, // src0_modifiers
        GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(1), /*SubOperand*/0, // src0
        GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/1, // src1_modifiers
        GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/0, // src1
        GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(1), /*SubOperand*/2, // clamp
        GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(1), /*SubOperand*/3, // omod
        GIR_ConstrainSelectedInstOperands, /*InsnID*/0,
        GIR_EraseFromParent, /*InsnID*/0,
        // GIR_Coverage, 7178,
        GIR_Done,
      // Label 4058: @256462
      GIM_Reject,
    // Label 4048: @256463
    GIM_Reject,
    // Label 4033: @256464
    GIM_Try, /*On fail goto*//*Label 4059*/ GIMT_Encode4(256544), // Rule ID 963 //
      GIM_CheckType, /*MI*/0, /*Op*/1, /*Type*/GILLT_v2s16,
      GIM_CheckType, /*MI*/0, /*Op*/2, /*Type*/GILLT_v2s16,
      GIM_CheckRegBankForClass, /*MI*/0, /*Op*/0, /*RC*/GIMT_Encode2(AMDGPU::VGPR_32RegClassID),
      GIM_CheckComplexPattern, /*MI*/0, /*Op*/1, /*Renderer*/GIMT_Encode2(0), GIMT_Encode2(GICP_gi_vop3pmods),
      GIM_CheckComplexPattern, /*MI*/0, /*Op*/2, /*Renderer*/GIMT_Encode2(1), GIMT_Encode2(GICP_gi_vop3pmods),
      // (fmul:{ *:[v2f16] } (VOP3PMods:{ *:[v2f16] } v2f16:{ *:[v2f16] }:$src0, i32:{ *:[i32] }:$src0_modifiers), (VOP3PMods:{ *:[v2f16] } v2f16:{ *:[v2f16] }:$src1, i32:{ *:[i32] }:$src1_modifiers))  =>  (V_PK_MUL_F16:{ *:[v2f16] } i32:{ *:[i32] }:$src0_modifiers, v2f16:{ *:[v2f16] }:$src0, i32:{ *:[i32] }:$src1_modifiers, v2f16:{ *:[v2f16] }:$src1)
      GIR_BuildMI, /*InsnID*/0, /*Opcode*/GIMT_Encode2(AMDGPU::V_PK_MUL_F16),
      GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/0, // DstI[vdst]
      GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/1, // src0_modifiers
      GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/0, // src0
      GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(1), /*SubOperand*/1, // src1_modifiers
      GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(1), /*SubOperand*/0, // src1
      GIR_AddImm8, /*InsnID*/0, /*Imm*/0,
      GIR_AddImm8, /*InsnID*/0, /*Imm*/0,
      GIR_AddImm8, /*InsnID*/0, /*Imm*/0,
      GIR_AddImm8, /*InsnID*/0, /*Imm*/0,
      GIR_AddImm8, /*InsnID*/0, /*Imm*/0,
      GIR_ConstrainSelectedInstOperands, /*InsnID*/0,
      GIR_EraseFromParent, /*InsnID*/0,
      // GIR_Coverage, 963,
      GIR_Done,
    // Label 4059: @256544
    GIM_Reject,
    // Label 4034: @256545
    GIM_Try, /*On fail goto*//*Label 4060*/ GIMT_Encode4(256628), // Rule ID 1087 //
      GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasPackedFP32Ops),
      GIM_CheckType, /*MI*/0, /*Op*/1, /*Type*/GILLT_v2s32,
      GIM_CheckType, /*MI*/0, /*Op*/2, /*Type*/GILLT_v2s32,
      GIM_CheckRegBankForClass, /*MI*/0, /*Op*/0, /*RC*/GIMT_Encode2(AMDGPU::VReg_64RegClassID),
      GIM_CheckComplexPattern, /*MI*/0, /*Op*/1, /*Renderer*/GIMT_Encode2(0), GIMT_Encode2(GICP_gi_vop3pmods),
      GIM_CheckComplexPattern, /*MI*/0, /*Op*/2, /*Renderer*/GIMT_Encode2(1), GIMT_Encode2(GICP_gi_vop3pmods),
      // (fmul:{ *:[v2f32] } (VOP3PMods:{ *:[v2f32] } v2f32:{ *:[v2f32] }:$src0, i32:{ *:[i32] }:$src0_modifiers), (VOP3PMods:{ *:[v2f32] } v2f32:{ *:[v2f32] }:$src1, i32:{ *:[i32] }:$src1_modifiers))  =>  (V_PK_MUL_F32:{ *:[v2f32] } i32:{ *:[i32] }:$src0_modifiers, v2f32:{ *:[v2f32] }:$src0, i32:{ *:[i32] }:$src1_modifiers, v2f32:{ *:[v2f32] }:$src1)
      GIR_BuildMI, /*InsnID*/0, /*Opcode*/GIMT_Encode2(AMDGPU::V_PK_MUL_F32),
      GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/0, // DstI[vdst]
      GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/1, // src0_modifiers
      GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/0, // src0
      GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(1), /*SubOperand*/1, // src1_modifiers
      GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(1), /*SubOperand*/0, // src1
      GIR_AddImm8, /*InsnID*/0, /*Imm*/0,
      GIR_AddImm8, /*InsnID*/0, /*Imm*/0,
      GIR_AddImm8, /*InsnID*/0, /*Imm*/0,
      GIR_AddImm8, /*InsnID*/0, /*Imm*/0,
      GIR_AddImm8, /*InsnID*/0, /*Imm*/0,
      GIR_ConstrainSelectedInstOperands, /*InsnID*/0,
      GIR_EraseFromParent, /*InsnID*/0,
      // GIR_Coverage, 1087,
      GIR_Done,
    // Label 4060: @256628
    GIM_Reject,
    // Label 4035: @256629
    GIM_Reject,
    // Label 59: @256630
    GIM_SwitchType, /*MI*/0, /*Op*/0, /*[*/GIMT_Encode2(8), GIMT_Encode2(13), /*)*//*default:*//*Label 4066*/ GIMT_Encode4(258426),
    /*GILLT_s16*//*Label 4061*/ GIMT_Encode4(256661),
    /*GILLT_s32*//*Label 4062*/ GIMT_Encode4(257141),
    /*GILLT_s64*//*Label 4063*/ GIMT_Encode4(257965),
    /*GILLT_v2s16*//*Label 4064*/ GIMT_Encode4(258219),
    /*GILLT_v2s32*//*Label 4065*/ GIMT_Encode4(258321),
    // Label 4061: @256661
    GIM_Try, /*On fail goto*//*Label 4067*/ GIMT_Encode4(257140),
      GIM_CheckType, /*MI*/0, /*Op*/1, /*Type*/GILLT_s16,
      GIM_CheckType, /*MI*/0, /*Op*/2, /*Type*/GILLT_s16,
      GIM_CheckType, /*MI*/0, /*Op*/3, /*Type*/GILLT_s16,
      GIM_Try, /*On fail goto*//*Label 4068*/ GIMT_Encode4(256722), // Rule ID 115 //
        GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasSALUFloatInsts),
        GIM_CheckRegBankForClass, /*MI*/0, /*Op*/0, /*RC*/GIMT_Encode2(AMDGPU::SReg_32RegClassID),
        GIM_CheckRegBankForClass, /*MI*/0, /*Op*/1, /*RC*/GIMT_Encode2(AMDGPU::SReg_32RegClassID),
        GIM_CheckRegBankForClass, /*MI*/0, /*Op*/2, /*RC*/GIMT_Encode2(AMDGPU::SReg_32RegClassID),
        GIM_CheckRegBankForClass, /*MI*/0, /*Op*/3, /*RC*/GIMT_Encode2(AMDGPU::SReg_32RegClassID),
        GIM_CheckCxxInsnPredicate, /*MI*/0, /*FnId*/GIMT_Encode2(GICXXPred_MI_Predicate_anonymous_17636),
        // (fma:{ *:[f16] } SSrc_f16:{ *:[f16] }:$src0, SSrc_f16:{ *:[f16] }:$src1, SReg_32:{ *:[f16] }:$src2)<<P:Predicate_anonymous_17636>>  =>  (S_FMAC_F16:{ *:[f16] } SSrc_f16:{ *:[f16] }:$src0, SSrc_f16:{ *:[f16] }:$src1, SReg_32:{ *:[f16] }:$src2)
        GIR_MutateOpcode, /*InsnID*/0, /*RecycleInsnID*/0, /*Opcode*/GIMT_Encode2(AMDGPU::S_FMAC_F16),
        GIR_AddImplicitUse, /*InsnID*/0, GIMT_Encode2(AMDGPU::MODE),
        GIR_ConstrainSelectedInstOperands, /*InsnID*/0,
        // GIR_Coverage, 115,
        GIR_Done,
      // Label 4068: @256722
      GIM_Try, /*On fail goto*//*Label 4069*/ GIMT_Encode4(256799), // Rule ID 6422 //
        GIM_CheckFeatures, GIMT_Encode2(GIFBS_NotHasTrue16BitInsts_isGFX10Plus),
        GIM_CheckRegBankForClass, /*MI*/0, /*Op*/0, /*RC*/GIMT_Encode2(AMDGPU::VGPR_32RegClassID),
        GIM_CheckComplexPattern, /*MI*/0, /*Op*/1, /*Renderer*/GIMT_Encode2(0), GIMT_Encode2(GICP_gi_vop3_no_mods),
        GIM_CheckComplexPattern, /*MI*/0, /*Op*/2, /*Renderer*/GIMT_Encode2(1), GIMT_Encode2(GICP_gi_vop3_no_mods),
        GIM_CheckComplexPattern, /*MI*/0, /*Op*/3, /*Renderer*/GIMT_Encode2(2), GIMT_Encode2(GICP_gi_vop3_no_mods),
        // (fma:{ *:[f16] } (VOP3NoMods:{ *:[f16] } f32:{ *:[f32] }:$src0), (VOP3NoMods:{ *:[f16] } f32:{ *:[f32] }:$src1), (VOP3NoMods:{ *:[f16] } f32:{ *:[f32] }:$src2))  =>  (V_FMAC_F16_e64:{ *:[f16] } 0:{ *:[i32] }, ?:{ *:[f32] }:$src0, 0:{ *:[i32] }, ?:{ *:[f32] }:$src1, 0:{ *:[i32] }, ?:{ *:[f32] }:$src2)
        GIR_BuildMI, /*InsnID*/0, /*Opcode*/GIMT_Encode2(AMDGPU::V_FMAC_F16_e64),
        GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/0, // DstI[vdst]
        GIR_AddImm8, /*InsnID*/0, /*Imm*/0,
        GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/0, // src0
        GIR_AddImm8, /*InsnID*/0, /*Imm*/0,
        GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(1), /*SubOperand*/0, // src1
        GIR_AddImm8, /*InsnID*/0, /*Imm*/0,
        GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(2), /*SubOperand*/0, // src2
        GIR_AddImm8, /*InsnID*/0, /*Imm*/0,
        GIR_AddImm8, /*InsnID*/0, /*Imm*/0,
        GIR_ConstrainSelectedInstOperands, /*InsnID*/0,
        GIR_EraseFromParent, /*InsnID*/0,
        // GIR_Coverage, 6422,
        GIR_Done,
      // Label 4069: @256799
      GIM_Try, /*On fail goto*//*Label 4070*/ GIMT_Encode4(256879), // Rule ID 6423 //
        GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasTrue16BitInsts_isGFX10Plus),
        GIM_CheckRegBankForClass, /*MI*/0, /*Op*/0, /*RC*/GIMT_Encode2(AMDGPU::VGPR_32RegClassID),
        GIM_CheckComplexPattern, /*MI*/0, /*Op*/1, /*Renderer*/GIMT_Encode2(0), GIMT_Encode2(GICP_gi_vop3_no_mods),
        GIM_CheckComplexPattern, /*MI*/0, /*Op*/2, /*Renderer*/GIMT_Encode2(1), GIMT_Encode2(GICP_gi_vop3_no_mods),
        GIM_CheckComplexPattern, /*MI*/0, /*Op*/3, /*Renderer*/GIMT_Encode2(2), GIMT_Encode2(GICP_gi_vop3_no_mods),
        // (fma:{ *:[f16] } (VOP3NoMods:{ *:[f16] } f32:{ *:[f32] }:$src0), (VOP3NoMods:{ *:[f16] } f32:{ *:[f32] }:$src1), (VOP3NoMods:{ *:[f16] } f32:{ *:[f32] }:$src2))  =>  (V_FMAC_F16_t16_e64:{ *:[f16] } 0:{ *:[i32] }, ?:{ *:[f32] }:$src0, 0:{ *:[i32] }, ?:{ *:[f32] }:$src1, 0:{ *:[i32] }, ?:{ *:[f32] }:$src2)
        GIR_BuildMI, /*InsnID*/0, /*Opcode*/GIMT_Encode2(AMDGPU::V_FMAC_F16_t16_e64),
        GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/0, // DstI[vdst]
        GIR_AddImm8, /*InsnID*/0, /*Imm*/0,
        GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/0, // src0
        GIR_AddImm8, /*InsnID*/0, /*Imm*/0,
        GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(1), /*SubOperand*/0, // src1
        GIR_AddImm8, /*InsnID*/0, /*Imm*/0,
        GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(2), /*SubOperand*/0, // src2
        GIR_AddImm8, /*InsnID*/0, /*Imm*/0,
        GIR_AddImm8, /*InsnID*/0, /*Imm*/0,
        GIR_AddImm8, /*InsnID*/0, /*Imm*/0,
        GIR_ConstrainSelectedInstOperands, /*InsnID*/0,
        GIR_EraseFromParent, /*InsnID*/0,
        // GIR_Coverage, 6423,
        GIR_Done,
      // Label 4070: @256879
      GIM_Try, /*On fail goto*//*Label 4071*/ GIMT_Encode4(256966), // Rule ID 922 //
        GIM_CheckFeatures, GIMT_Encode2(GIFBS_Has16BitInsts_isGFX8Only),
        GIM_CheckRegBankForClass, /*MI*/0, /*Op*/0, /*RC*/GIMT_Encode2(AMDGPU::VGPR_32RegClassID),
        GIM_CheckComplexPattern, /*MI*/0, /*Op*/1, /*Renderer*/GIMT_Encode2(0), GIMT_Encode2(GICP_gi_vop3mods0),
        GIM_CheckComplexPattern, /*MI*/0, /*Op*/2, /*Renderer*/GIMT_Encode2(1), GIMT_Encode2(GICP_gi_vop3mods),
        GIM_CheckComplexPattern, /*MI*/0, /*Op*/3, /*Renderer*/GIMT_Encode2(2), GIMT_Encode2(GICP_gi_vop3mods),
        // (fma:{ *:[f16] } (VOP3Mods0:{ *:[f16] } f16:{ *:[f16] }:$src0, i32:{ *:[i32] }:$src0_modifiers, i1:{ *:[i1] }:$clamp, i32:{ *:[i32] }:$omod), (VOP3Mods:{ *:[f16] } f16:{ *:[f16] }:$src1, i32:{ *:[i32] }:$src1_modifiers), (VOP3Mods:{ *:[f16] } f16:{ *:[f16] }:$src2, i32:{ *:[i32] }:$src2_modifiers))  =>  (V_FMA_F16_e64:{ *:[f16] } i32:{ *:[i32] }:$src0_modifiers, f16:{ *:[f16] }:$src0, i32:{ *:[i32] }:$src1_modifiers, f16:{ *:[f16] }:$src1, i32:{ *:[i32] }:$src2_modifiers, f16:{ *:[f16] }:$src2, i1:{ *:[i1] }:$clamp, i32:{ *:[i32] }:$omod)
        GIR_BuildMI, /*InsnID*/0, /*Opcode*/GIMT_Encode2(AMDGPU::V_FMA_F16_e64),
        GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/0, // DstI[vdst]
        GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/1, // src0_modifiers
        GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/0, // src0
        GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(1), /*SubOperand*/1, // src1_modifiers
        GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(1), /*SubOperand*/0, // src1
        GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(2), /*SubOperand*/1, // src2_modifiers
        GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(2), /*SubOperand*/0, // src2
        GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/2, // clamp
        GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/3, // omod
        GIR_ConstrainSelectedInstOperands, /*InsnID*/0,
        GIR_EraseFromParent, /*InsnID*/0,
        // GIR_Coverage, 922,
        GIR_Done,
      // Label 4071: @256966
      GIM_Try, /*On fail goto*//*Label 4072*/ GIMT_Encode4(257053), // Rule ID 7193 //
        GIM_CheckFeatures, GIMT_Encode2(GIFBS_Has16BitInsts_isGFX8Only),
        GIM_CheckRegBankForClass, /*MI*/0, /*Op*/0, /*RC*/GIMT_Encode2(AMDGPU::VGPR_32RegClassID),
        GIM_CheckComplexPattern, /*MI*/0, /*Op*/1, /*Renderer*/GIMT_Encode2(0), GIMT_Encode2(GICP_gi_vop3mods),
        GIM_CheckComplexPattern, /*MI*/0, /*Op*/2, /*Renderer*/GIMT_Encode2(1), GIMT_Encode2(GICP_gi_vop3mods0),
        GIM_CheckComplexPattern, /*MI*/0, /*Op*/3, /*Renderer*/GIMT_Encode2(2), GIMT_Encode2(GICP_gi_vop3mods),
        // (fma:{ *:[f16] } (VOP3Mods:{ *:[f16] } f16:{ *:[f16] }:$src1, i32:{ *:[i32] }:$src1_modifiers), (VOP3Mods0:{ *:[f16] } f16:{ *:[f16] }:$src0, i32:{ *:[i32] }:$src0_modifiers, i1:{ *:[i1] }:$clamp, i32:{ *:[i32] }:$omod), (VOP3Mods:{ *:[f16] } f16:{ *:[f16] }:$src2, i32:{ *:[i32] }:$src2_modifiers))  =>  (V_FMA_F16_e64:{ *:[f16] } i32:{ *:[i32] }:$src0_modifiers, f16:{ *:[f16] }:$src0, i32:{ *:[i32] }:$src1_modifiers, f16:{ *:[f16] }:$src1, i32:{ *:[i32] }:$src2_modifiers, f16:{ *:[f16] }:$src2, i1:{ *:[i1] }:$clamp, i32:{ *:[i32] }:$omod)
        GIR_BuildMI, /*InsnID*/0, /*Opcode*/GIMT_Encode2(AMDGPU::V_FMA_F16_e64),
        GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/0, // DstI[vdst]
        GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(1), /*SubOperand*/1, // src0_modifiers
        GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(1), /*SubOperand*/0, // src0
        GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/1, // src1_modifiers
        GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/0, // src1
        GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(2), /*SubOperand*/1, // src2_modifiers
        GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(2), /*SubOperand*/0, // src2
        GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(1), /*SubOperand*/2, // clamp
        GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(1), /*SubOperand*/3, // omod
        GIR_ConstrainSelectedInstOperands, /*InsnID*/0,
        GIR_EraseFromParent, /*InsnID*/0,
        // GIR_Coverage, 7193,
        GIR_Done,
      // Label 4072: @257053
      GIM_Try, /*On fail goto*//*Label 4073*/ GIMT_Encode4(257139), // Rule ID 926 //
        GIM_CheckFeatures, GIMT_Encode2(GIFBS_isGFX9Plus),
        GIM_CheckRegBankForClass, /*MI*/0, /*Op*/0, /*RC*/GIMT_Encode2(AMDGPU::VGPR_32RegClassID),
        GIM_CheckComplexPattern, /*MI*/0, /*Op*/1, /*Renderer*/GIMT_Encode2(0), GIMT_Encode2(GICP_gi_vop3opselmods),
        GIM_CheckComplexPattern, /*MI*/0, /*Op*/2, /*Renderer*/GIMT_Encode2(1), GIMT_Encode2(GICP_gi_vop3opselmods),
        GIM_CheckComplexPattern, /*MI*/0, /*Op*/3, /*Renderer*/GIMT_Encode2(2), GIMT_Encode2(GICP_gi_vop3opselmods),
        // (fma:{ *:[f16] } (VOP3OpSelMods:{ *:[f16] } f16:{ *:[f16] }:$src0, i32:{ *:[i32] }:$src0_modifiers), (VOP3OpSelMods:{ *:[f16] } f16:{ *:[f16] }:$src1, i32:{ *:[i32] }:$src1_modifiers), (VOP3OpSelMods:{ *:[f16] } f16:{ *:[f16] }:$src2, i32:{ *:[i32] }:$src2_modifiers))  =>  (V_FMA_F16_gfx9_e64:{ *:[f16] } i32:{ *:[i32] }:$src0_modifiers, f16:{ *:[f16] }:$src0, i32:{ *:[i32] }:$src1_modifiers, f16:{ *:[f16] }:$src1, i32:{ *:[i32] }:$src2_modifiers, f16:{ *:[f16] }:$src2)
        GIR_BuildMI, /*InsnID*/0, /*Opcode*/GIMT_Encode2(AMDGPU::V_FMA_F16_gfx9_e64),
        GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/0, // DstI[vdst]
        GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/1, // src0_modifiers
        GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/0, // src0
        GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(1), /*SubOperand*/1, // src1_modifiers
        GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(1), /*SubOperand*/0, // src1
        GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(2), /*SubOperand*/1, // src2_modifiers
        GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(2), /*SubOperand*/0, // src2
        GIR_AddImm8, /*InsnID*/0, /*Imm*/0,
        GIR_AddImm8, /*InsnID*/0, /*Imm*/0,
        GIR_AddImm8, /*InsnID*/0, /*Imm*/0,
        GIR_ConstrainSelectedInstOperands, /*InsnID*/0,
        GIR_EraseFromParent, /*InsnID*/0,
        // GIR_Coverage, 926,
        GIR_Done,
      // Label 4073: @257139
      GIM_Reject,
    // Label 4067: @257140
    GIM_Reject,
    // Label 4062: @257141
    GIM_Try, /*On fail goto*//*Label 4074*/ GIMT_Encode4(257964),
      GIM_CheckType, /*MI*/0, /*Op*/1, /*Type*/GILLT_s32,
      GIM_CheckType, /*MI*/0, /*Op*/2, /*Type*/GILLT_s32,
      GIM_CheckType, /*MI*/0, /*Op*/3, /*Type*/GILLT_s32,
      GIM_Try, /*On fail goto*//*Label 4075*/ GIMT_Encode4(257244), // Rule ID 2258 //
        GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasFmaMixInsts),
        GIM_CheckRegBankForClass, /*MI*/0, /*Op*/0, /*RC*/GIMT_Encode2(AMDGPU::VGPR_32RegClassID),
        GIM_CheckComplexPattern, /*MI*/0, /*Op*/1, /*Renderer*/GIMT_Encode2(0), GIMT_Encode2(GICP_gi_vop3_mad_mix_mods_ext),
        GIM_CheckComplexPattern, /*MI*/0, /*Op*/2, /*Renderer*/GIMT_Encode2(1), GIMT_Encode2(GICP_gi_vop3_mad_mix_mods),
        GIM_CheckComplexPattern, /*MI*/0, /*Op*/3, /*Renderer*/GIMT_Encode2(2), GIMT_Encode2(GICP_gi_vop3_mad_mix_mods),
        // (fma:{ *:[f32] } (VOP3PMadMixModsExt:{ *:[f32] } f16:{ *:[f16] }:$src0, i32:{ *:[i32] }:$src0_mods), (VOP3PMadMixMods:{ *:[f32] } f16:{ *:[f16] }:$src1, i32:{ *:[i32] }:$src1_mods), (VOP3PMadMixMods:{ *:[f32] } f16:{ *:[f16] }:$src2, i32:{ *:[i32] }:$src2_mods))  =>  (V_FMA_MIX_F32:{ *:[f32] } ?:{ *:[i32] }:$src0_mods, ?:{ *:[f16] }:$src0, ?:{ *:[i32] }:$src1_mods, ?:{ *:[f16] }:$src1, ?:{ *:[i32] }:$src2_mods, ?:{ *:[f16] }:$src2, 0:{ *:[i1] })
        GIR_BuildMI, /*InsnID*/0, /*Opcode*/GIMT_Encode2(AMDGPU::V_FMA_MIX_F32),
        GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/0, // DstI[vdst]
        GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/1, // src0_mods
        GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/0, // src0
        GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(1), /*SubOperand*/1, // src1_mods
        GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(1), /*SubOperand*/0, // src1
        GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(2), /*SubOperand*/1, // src2_mods
        GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(2), /*SubOperand*/0, // src2
        GIR_AddImm8, /*InsnID*/0, /*Imm*/0,
        GIR_AddImm8, /*InsnID*/0, /*Imm*/0,
        GIR_AddImm8, /*InsnID*/0, /*Imm*/0,
        GIR_ConstrainSelectedInstOperands, /*InsnID*/0,
        GIR_EraseFromParent, /*InsnID*/0,
        // GIR_Coverage, 2258,
        GIR_Done,
      // Label 4075: @257244
      GIM_Try, /*On fail goto*//*Label 4076*/ GIMT_Encode4(257330), // Rule ID 2259 //
        GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasFmaMixInsts),
        GIM_CheckRegBankForClass, /*MI*/0, /*Op*/0, /*RC*/GIMT_Encode2(AMDGPU::VGPR_32RegClassID),
        GIM_CheckComplexPattern, /*MI*/0, /*Op*/1, /*Renderer*/GIMT_Encode2(0), GIMT_Encode2(GICP_gi_vop3_mad_mix_mods),
        GIM_CheckComplexPattern, /*MI*/0, /*Op*/2, /*Renderer*/GIMT_Encode2(1), GIMT_Encode2(GICP_gi_vop3_mad_mix_mods_ext),
        GIM_CheckComplexPattern, /*MI*/0, /*Op*/3, /*Renderer*/GIMT_Encode2(2), GIMT_Encode2(GICP_gi_vop3_mad_mix_mods),
        // (fma:{ *:[f32] } (VOP3PMadMixMods:{ *:[f32] } f16:{ *:[f16] }:$src0, i32:{ *:[i32] }:$src0_mods), (VOP3PMadMixModsExt:{ *:[f32] } f16:{ *:[f16] }:$src1, i32:{ *:[i32] }:$src1_mods), (VOP3PMadMixMods:{ *:[f32] } f32:{ *:[f32] }:$src2, i32:{ *:[i32] }:$src2_mods))  =>  (V_FMA_MIX_F32:{ *:[f32] } ?:{ *:[i32] }:$src0_mods, ?:{ *:[f16] }:$src0, ?:{ *:[i32] }:$src1_mods, ?:{ *:[f16] }:$src1, ?:{ *:[i32] }:$src2_mods, ?:{ *:[f32] }:$src2, 0:{ *:[i1] })
        GIR_BuildMI, /*InsnID*/0, /*Opcode*/GIMT_Encode2(AMDGPU::V_FMA_MIX_F32),
        GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/0, // DstI[vdst]
        GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/1, // src0_mods
        GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/0, // src0
        GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(1), /*SubOperand*/1, // src1_mods
        GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(1), /*SubOperand*/0, // src1
        GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(2), /*SubOperand*/1, // src2_mods
        GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(2), /*SubOperand*/0, // src2
        GIR_AddImm8, /*InsnID*/0, /*Imm*/0,
        GIR_AddImm8, /*InsnID*/0, /*Imm*/0,
        GIR_AddImm8, /*InsnID*/0, /*Imm*/0,
        GIR_ConstrainSelectedInstOperands, /*InsnID*/0,
        GIR_EraseFromParent, /*InsnID*/0,
        // GIR_Coverage, 2259,
        GIR_Done,
      // Label 4076: @257330
      GIM_Try, /*On fail goto*//*Label 4077*/ GIMT_Encode4(257416), // Rule ID 2260 //
        GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasFmaMixInsts),
        GIM_CheckRegBankForClass, /*MI*/0, /*Op*/0, /*RC*/GIMT_Encode2(AMDGPU::VGPR_32RegClassID),
        GIM_CheckComplexPattern, /*MI*/0, /*Op*/1, /*Renderer*/GIMT_Encode2(0), GIMT_Encode2(GICP_gi_vop3_mad_mix_mods),
        GIM_CheckComplexPattern, /*MI*/0, /*Op*/2, /*Renderer*/GIMT_Encode2(1), GIMT_Encode2(GICP_gi_vop3_mad_mix_mods),
        GIM_CheckComplexPattern, /*MI*/0, /*Op*/3, /*Renderer*/GIMT_Encode2(2), GIMT_Encode2(GICP_gi_vop3_mad_mix_mods_ext),
        // (fma:{ *:[f32] } (VOP3PMadMixMods:{ *:[f32] } f16:{ *:[f16] }:$src0, i32:{ *:[i32] }:$src0_mods), (VOP3PMadMixMods:{ *:[f32] } f32:{ *:[f32] }:$src1, i32:{ *:[i32] }:$src1_mods), (VOP3PMadMixModsExt:{ *:[f32] } f16:{ *:[f16] }:$src2, i32:{ *:[i32] }:$src2_mods))  =>  (V_FMA_MIX_F32:{ *:[f32] } ?:{ *:[i32] }:$src0_mods, ?:{ *:[f16] }:$src0, ?:{ *:[i32] }:$src1_mods, ?:{ *:[f32] }:$src1, ?:{ *:[i32] }:$src2_mods, ?:{ *:[f16] }:$src2, 0:{ *:[i1] })
        GIR_BuildMI, /*InsnID*/0, /*Opcode*/GIMT_Encode2(AMDGPU::V_FMA_MIX_F32),
        GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/0, // DstI[vdst]
        GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/1, // src0_mods
        GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/0, // src0
        GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(1), /*SubOperand*/1, // src1_mods
        GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(1), /*SubOperand*/0, // src1
        GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(2), /*SubOperand*/1, // src2_mods
        GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(2), /*SubOperand*/0, // src2
        GIR_AddImm8, /*InsnID*/0, /*Imm*/0,
        GIR_AddImm8, /*InsnID*/0, /*Imm*/0,
        GIR_AddImm8, /*InsnID*/0, /*Imm*/0,
        GIR_ConstrainSelectedInstOperands, /*InsnID*/0,
        GIR_EraseFromParent, /*InsnID*/0,
        // GIR_Coverage, 2260,
        GIR_Done,
      // Label 4077: @257416
      GIM_Try, /*On fail goto*//*Label 4078*/ GIMT_Encode4(257502), // Rule ID 7229 //
        GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasFmaMixInsts),
        GIM_CheckRegBankForClass, /*MI*/0, /*Op*/0, /*RC*/GIMT_Encode2(AMDGPU::VGPR_32RegClassID),
        GIM_CheckComplexPattern, /*MI*/0, /*Op*/1, /*Renderer*/GIMT_Encode2(0), GIMT_Encode2(GICP_gi_vop3_mad_mix_mods),
        GIM_CheckComplexPattern, /*MI*/0, /*Op*/2, /*Renderer*/GIMT_Encode2(1), GIMT_Encode2(GICP_gi_vop3_mad_mix_mods_ext),
        GIM_CheckComplexPattern, /*MI*/0, /*Op*/3, /*Renderer*/GIMT_Encode2(2), GIMT_Encode2(GICP_gi_vop3_mad_mix_mods),
        // (fma:{ *:[f32] } (VOP3PMadMixMods:{ *:[f32] } f16:{ *:[f16] }:$src1, i32:{ *:[i32] }:$src1_mods), (VOP3PMadMixModsExt:{ *:[f32] } f16:{ *:[f16] }:$src0, i32:{ *:[i32] }:$src0_mods), (VOP3PMadMixMods:{ *:[f32] } f16:{ *:[f16] }:$src2, i32:{ *:[i32] }:$src2_mods))  =>  (V_FMA_MIX_F32:{ *:[f32] } ?:{ *:[i32] }:$src0_mods, ?:{ *:[f16] }:$src0, ?:{ *:[i32] }:$src1_mods, ?:{ *:[f16] }:$src1, ?:{ *:[i32] }:$src2_mods, ?:{ *:[f16] }:$src2, 0:{ *:[i1] })
        GIR_BuildMI, /*InsnID*/0, /*Opcode*/GIMT_Encode2(AMDGPU::V_FMA_MIX_F32),
        GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/0, // DstI[vdst]
        GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(1), /*SubOperand*/1, // src0_mods
        GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(1), /*SubOperand*/0, // src0
        GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/1, // src1_mods
        GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/0, // src1
        GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(2), /*SubOperand*/1, // src2_mods
        GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(2), /*SubOperand*/0, // src2
        GIR_AddImm8, /*InsnID*/0, /*Imm*/0,
        GIR_AddImm8, /*InsnID*/0, /*Imm*/0,
        GIR_AddImm8, /*InsnID*/0, /*Imm*/0,
        GIR_ConstrainSelectedInstOperands, /*InsnID*/0,
        GIR_EraseFromParent, /*InsnID*/0,
        // GIR_Coverage, 7229,
        GIR_Done,
      // Label 4078: @257502
      GIM_Try, /*On fail goto*//*Label 4079*/ GIMT_Encode4(257588), // Rule ID 7230 //
        GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasFmaMixInsts),
        GIM_CheckRegBankForClass, /*MI*/0, /*Op*/0, /*RC*/GIMT_Encode2(AMDGPU::VGPR_32RegClassID),
        GIM_CheckComplexPattern, /*MI*/0, /*Op*/1, /*Renderer*/GIMT_Encode2(0), GIMT_Encode2(GICP_gi_vop3_mad_mix_mods_ext),
        GIM_CheckComplexPattern, /*MI*/0, /*Op*/2, /*Renderer*/GIMT_Encode2(1), GIMT_Encode2(GICP_gi_vop3_mad_mix_mods),
        GIM_CheckComplexPattern, /*MI*/0, /*Op*/3, /*Renderer*/GIMT_Encode2(2), GIMT_Encode2(GICP_gi_vop3_mad_mix_mods),
        // (fma:{ *:[f32] } (VOP3PMadMixModsExt:{ *:[f32] } f16:{ *:[f16] }:$src1, i32:{ *:[i32] }:$src1_mods), (VOP3PMadMixMods:{ *:[f32] } f16:{ *:[f16] }:$src0, i32:{ *:[i32] }:$src0_mods), (VOP3PMadMixMods:{ *:[f32] } f32:{ *:[f32] }:$src2, i32:{ *:[i32] }:$src2_mods))  =>  (V_FMA_MIX_F32:{ *:[f32] } ?:{ *:[i32] }:$src0_mods, ?:{ *:[f16] }:$src0, ?:{ *:[i32] }:$src1_mods, ?:{ *:[f16] }:$src1, ?:{ *:[i32] }:$src2_mods, ?:{ *:[f32] }:$src2, 0:{ *:[i1] })
        GIR_BuildMI, /*InsnID*/0, /*Opcode*/GIMT_Encode2(AMDGPU::V_FMA_MIX_F32),
        GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/0, // DstI[vdst]
        GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(1), /*SubOperand*/1, // src0_mods
        GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(1), /*SubOperand*/0, // src0
        GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/1, // src1_mods
        GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/0, // src1
        GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(2), /*SubOperand*/1, // src2_mods
        GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(2), /*SubOperand*/0, // src2
        GIR_AddImm8, /*InsnID*/0, /*Imm*/0,
        GIR_AddImm8, /*InsnID*/0, /*Imm*/0,
        GIR_AddImm8, /*InsnID*/0, /*Imm*/0,
        GIR_ConstrainSelectedInstOperands, /*InsnID*/0,
        GIR_EraseFromParent, /*InsnID*/0,
        // GIR_Coverage, 7230,
        GIR_Done,
      // Label 4079: @257588
      GIM_Try, /*On fail goto*//*Label 4080*/ GIMT_Encode4(257674), // Rule ID 7231 //
        GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasFmaMixInsts),
        GIM_CheckRegBankForClass, /*MI*/0, /*Op*/0, /*RC*/GIMT_Encode2(AMDGPU::VGPR_32RegClassID),
        GIM_CheckComplexPattern, /*MI*/0, /*Op*/1, /*Renderer*/GIMT_Encode2(0), GIMT_Encode2(GICP_gi_vop3_mad_mix_mods),
        GIM_CheckComplexPattern, /*MI*/0, /*Op*/2, /*Renderer*/GIMT_Encode2(1), GIMT_Encode2(GICP_gi_vop3_mad_mix_mods),
        GIM_CheckComplexPattern, /*MI*/0, /*Op*/3, /*Renderer*/GIMT_Encode2(2), GIMT_Encode2(GICP_gi_vop3_mad_mix_mods_ext),
        // (fma:{ *:[f32] } (VOP3PMadMixMods:{ *:[f32] } f32:{ *:[f32] }:$src1, i32:{ *:[i32] }:$src1_mods), (VOP3PMadMixMods:{ *:[f32] } f16:{ *:[f16] }:$src0, i32:{ *:[i32] }:$src0_mods), (VOP3PMadMixModsExt:{ *:[f32] } f16:{ *:[f16] }:$src2, i32:{ *:[i32] }:$src2_mods))  =>  (V_FMA_MIX_F32:{ *:[f32] } ?:{ *:[i32] }:$src0_mods, ?:{ *:[f16] }:$src0, ?:{ *:[i32] }:$src1_mods, ?:{ *:[f32] }:$src1, ?:{ *:[i32] }:$src2_mods, ?:{ *:[f16] }:$src2, 0:{ *:[i1] })
        GIR_BuildMI, /*InsnID*/0, /*Opcode*/GIMT_Encode2(AMDGPU::V_FMA_MIX_F32),
        GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/0, // DstI[vdst]
        GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(1), /*SubOperand*/1, // src0_mods
        GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(1), /*SubOperand*/0, // src0
        GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/1, // src1_mods
        GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/0, // src1
        GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(2), /*SubOperand*/1, // src2_mods
        GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(2), /*SubOperand*/0, // src2
        GIR_AddImm8, /*InsnID*/0, /*Imm*/0,
        GIR_AddImm8, /*InsnID*/0, /*Imm*/0,
        GIR_AddImm8, /*InsnID*/0, /*Imm*/0,
        GIR_ConstrainSelectedInstOperands, /*InsnID*/0,
        GIR_EraseFromParent, /*InsnID*/0,
        // GIR_Coverage, 7231,
        GIR_Done,
      // Label 4080: @257674
      GIM_Try, /*On fail goto*//*Label 4081*/ GIMT_Encode4(257718), // Rule ID 113 //
        GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasSALUFloatInsts),
        GIM_CheckRegBankForClass, /*MI*/0, /*Op*/0, /*RC*/GIMT_Encode2(AMDGPU::SReg_32RegClassID),
        GIM_CheckRegBankForClass, /*MI*/0, /*Op*/1, /*RC*/GIMT_Encode2(AMDGPU::SReg_32RegClassID),
        GIM_CheckRegBankForClass, /*MI*/0, /*Op*/2, /*RC*/GIMT_Encode2(AMDGPU::SReg_32RegClassID),
        GIM_CheckRegBankForClass, /*MI*/0, /*Op*/3, /*RC*/GIMT_Encode2(AMDGPU::SReg_32RegClassID),
        GIM_CheckCxxInsnPredicate, /*MI*/0, /*FnId*/GIMT_Encode2(GICXXPred_MI_Predicate_anonymous_17636),
        // (fma:{ *:[f32] } SSrc_f32:{ *:[f32] }:$src0, SSrc_f32:{ *:[f32] }:$src1, SReg_32:{ *:[f32] }:$src2)<<P:Predicate_anonymous_17636>>  =>  (S_FMAC_F32:{ *:[f32] } SSrc_f32:{ *:[f32] }:$src0, SSrc_f32:{ *:[f32] }:$src1, SReg_32:{ *:[f32] }:$src2)
        GIR_MutateOpcode, /*InsnID*/0, /*RecycleInsnID*/0, /*Opcode*/GIMT_Encode2(AMDGPU::S_FMAC_F32),
        GIR_AddImplicitUse, /*InsnID*/0, GIMT_Encode2(AMDGPU::MODE),
        GIR_ConstrainSelectedInstOperands, /*InsnID*/0,
        // GIR_Coverage, 113,
        GIR_Done,
      // Label 4081: @257718
      GIM_Try, /*On fail goto*//*Label 4082*/ GIMT_Encode4(257795), // Rule ID 6421 //
        GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasDLInsts),
        GIM_CheckRegBankForClass, /*MI*/0, /*Op*/0, /*RC*/GIMT_Encode2(AMDGPU::VGPR_32RegClassID),
        GIM_CheckComplexPattern, /*MI*/0, /*Op*/1, /*Renderer*/GIMT_Encode2(0), GIMT_Encode2(GICP_gi_vop3_no_mods),
        GIM_CheckComplexPattern, /*MI*/0, /*Op*/2, /*Renderer*/GIMT_Encode2(1), GIMT_Encode2(GICP_gi_vop3_no_mods),
        GIM_CheckComplexPattern, /*MI*/0, /*Op*/3, /*Renderer*/GIMT_Encode2(2), GIMT_Encode2(GICP_gi_vop3_no_mods),
        // (fma:{ *:[f32] } (VOP3NoMods:{ *:[f32] } f32:{ *:[f32] }:$src0), (VOP3NoMods:{ *:[f32] } f32:{ *:[f32] }:$src1), (VOP3NoMods:{ *:[f32] } f32:{ *:[f32] }:$src2))  =>  (V_FMAC_F32_e64:{ *:[f32] } 0:{ *:[i32] }, ?:{ *:[f32] }:$src0, 0:{ *:[i32] }, ?:{ *:[f32] }:$src1, 0:{ *:[i32] }, ?:{ *:[f32] }:$src2)
        GIR_BuildMI, /*InsnID*/0, /*Opcode*/GIMT_Encode2(AMDGPU::V_FMAC_F32_e64),
        GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/0, // DstI[vdst]
        GIR_AddImm8, /*InsnID*/0, /*Imm*/0,
        GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/0, // src0
        GIR_AddImm8, /*InsnID*/0, /*Imm*/0,
        GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(1), /*SubOperand*/0, // src1
        GIR_AddImm8, /*InsnID*/0, /*Imm*/0,
        GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(2), /*SubOperand*/0, // src2
        GIR_AddImm8, /*InsnID*/0, /*Imm*/0,
        GIR_AddImm8, /*InsnID*/0, /*Imm*/0,
        GIR_ConstrainSelectedInstOperands, /*InsnID*/0,
        GIR_EraseFromParent, /*InsnID*/0,
        // GIR_Coverage, 6421,
        GIR_Done,
      // Label 4082: @257795
      GIM_Try, /*On fail goto*//*Label 4083*/ GIMT_Encode4(257879), // Rule ID 853 //
        GIM_CheckRegBankForClass, /*MI*/0, /*Op*/0, /*RC*/GIMT_Encode2(AMDGPU::VGPR_32RegClassID),
        GIM_CheckComplexPattern, /*MI*/0, /*Op*/1, /*Renderer*/GIMT_Encode2(0), GIMT_Encode2(GICP_gi_vop3mods0),
        GIM_CheckComplexPattern, /*MI*/0, /*Op*/2, /*Renderer*/GIMT_Encode2(1), GIMT_Encode2(GICP_gi_vop3mods),
        GIM_CheckComplexPattern, /*MI*/0, /*Op*/3, /*Renderer*/GIMT_Encode2(2), GIMT_Encode2(GICP_gi_vop3mods),
        // (fma:{ *:[f32] } (VOP3Mods0:{ *:[f32] } f32:{ *:[f32] }:$src0, i32:{ *:[i32] }:$src0_modifiers, i1:{ *:[i1] }:$clamp, i32:{ *:[i32] }:$omod), (VOP3Mods:{ *:[f32] } f32:{ *:[f32] }:$src1, i32:{ *:[i32] }:$src1_modifiers), (VOP3Mods:{ *:[f32] } f32:{ *:[f32] }:$src2, i32:{ *:[i32] }:$src2_modifiers))  =>  (V_FMA_F32_e64:{ *:[f32] } i32:{ *:[i32] }:$src0_modifiers, f32:{ *:[f32] }:$src0, i32:{ *:[i32] }:$src1_modifiers, f32:{ *:[f32] }:$src1, i32:{ *:[i32] }:$src2_modifiers, f32:{ *:[f32] }:$src2, i1:{ *:[i1] }:$clamp, i32:{ *:[i32] }:$omod)
        GIR_BuildMI, /*InsnID*/0, /*Opcode*/GIMT_Encode2(AMDGPU::V_FMA_F32_e64),
        GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/0, // DstI[vdst]
        GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/1, // src0_modifiers
        GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/0, // src0
        GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(1), /*SubOperand*/1, // src1_modifiers
        GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(1), /*SubOperand*/0, // src1
        GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(2), /*SubOperand*/1, // src2_modifiers
        GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(2), /*SubOperand*/0, // src2
        GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/2, // clamp
        GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/3, // omod
        GIR_ConstrainSelectedInstOperands, /*InsnID*/0,
        GIR_EraseFromParent, /*InsnID*/0,
        // GIR_Coverage, 853,
        GIR_Done,
      // Label 4083: @257879
      GIM_Try, /*On fail goto*//*Label 4084*/ GIMT_Encode4(257963), // Rule ID 7172 //
        GIM_CheckRegBankForClass, /*MI*/0, /*Op*/0, /*RC*/GIMT_Encode2(AMDGPU::VGPR_32RegClassID),
        GIM_CheckComplexPattern, /*MI*/0, /*Op*/1, /*Renderer*/GIMT_Encode2(0), GIMT_Encode2(GICP_gi_vop3mods),
        GIM_CheckComplexPattern, /*MI*/0, /*Op*/2, /*Renderer*/GIMT_Encode2(1), GIMT_Encode2(GICP_gi_vop3mods0),
        GIM_CheckComplexPattern, /*MI*/0, /*Op*/3, /*Renderer*/GIMT_Encode2(2), GIMT_Encode2(GICP_gi_vop3mods),
        // (fma:{ *:[f32] } (VOP3Mods:{ *:[f32] } f32:{ *:[f32] }:$src1, i32:{ *:[i32] }:$src1_modifiers), (VOP3Mods0:{ *:[f32] } f32:{ *:[f32] }:$src0, i32:{ *:[i32] }:$src0_modifiers, i1:{ *:[i1] }:$clamp, i32:{ *:[i32] }:$omod), (VOP3Mods:{ *:[f32] } f32:{ *:[f32] }:$src2, i32:{ *:[i32] }:$src2_modifiers))  =>  (V_FMA_F32_e64:{ *:[f32] } i32:{ *:[i32] }:$src0_modifiers, f32:{ *:[f32] }:$src0, i32:{ *:[i32] }:$src1_modifiers, f32:{ *:[f32] }:$src1, i32:{ *:[i32] }:$src2_modifiers, f32:{ *:[f32] }:$src2, i1:{ *:[i1] }:$clamp, i32:{ *:[i32] }:$omod)
        GIR_BuildMI, /*InsnID*/0, /*Opcode*/GIMT_Encode2(AMDGPU::V_FMA_F32_e64),
        GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/0, // DstI[vdst]
        GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(1), /*SubOperand*/1, // src0_modifiers
        GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(1), /*SubOperand*/0, // src0
        GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/1, // src1_modifiers
        GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/0, // src1
        GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(2), /*SubOperand*/1, // src2_modifiers
        GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(2), /*SubOperand*/0, // src2
        GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(1), /*SubOperand*/2, // clamp
        GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(1), /*SubOperand*/3, // omod
        GIR_ConstrainSelectedInstOperands, /*InsnID*/0,
        GIR_EraseFromParent, /*InsnID*/0,
        // GIR_Coverage, 7172,
        GIR_Done,
      // Label 4084: @257963
      GIM_Reject,
    // Label 4074: @257964
    GIM_Reject,
    // Label 4063: @257965
    GIM_Try, /*On fail goto*//*Label 4085*/ GIMT_Encode4(258218),
      GIM_CheckType, /*MI*/0, /*Op*/1, /*Type*/GILLT_s64,
      GIM_CheckType, /*MI*/0, /*Op*/2, /*Type*/GILLT_s64,
      GIM_CheckType, /*MI*/0, /*Op*/3, /*Type*/GILLT_s64,
      GIM_CheckRegBankForClass, /*MI*/0, /*Op*/0, /*RC*/GIMT_Encode2(AMDGPU::VReg_64RegClassID),
      GIM_Try, /*On fail goto*//*Label 4086*/ GIMT_Encode4(258059), // Rule ID 6424 //
        GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasFmacF64Inst),
        GIM_CheckComplexPattern, /*MI*/0, /*Op*/1, /*Renderer*/GIMT_Encode2(0), GIMT_Encode2(GICP_gi_vop3_no_mods),
        GIM_CheckComplexPattern, /*MI*/0, /*Op*/2, /*Renderer*/GIMT_Encode2(1), GIMT_Encode2(GICP_gi_vop3_no_mods),
        GIM_CheckComplexPattern, /*MI*/0, /*Op*/3, /*Renderer*/GIMT_Encode2(2), GIMT_Encode2(GICP_gi_vop3_no_mods),
        // (fma:{ *:[f64] } (VOP3NoMods:{ *:[f64] } f64:{ *:[f64] }:$src0), (VOP3NoMods:{ *:[f64] } f64:{ *:[f64] }:$src1), (VOP3NoMods:{ *:[f64] } f64:{ *:[f64] }:$src2))  =>  (V_FMAC_F64_e64:{ *:[f64] } 0:{ *:[i32] }, ?:{ *:[f64] }:$src0, 0:{ *:[i32] }, ?:{ *:[f64] }:$src1, 0:{ *:[i32] }, ?:{ *:[f64] }:$src2)
        GIR_BuildMI, /*InsnID*/0, /*Opcode*/GIMT_Encode2(AMDGPU::V_FMAC_F64_e64),
        GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/0, // DstI[vdst]
        GIR_AddImm8, /*InsnID*/0, /*Imm*/0,
        GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/0, // src0
        GIR_AddImm8, /*InsnID*/0, /*Imm*/0,
        GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(1), /*SubOperand*/0, // src1
        GIR_AddImm8, /*InsnID*/0, /*Imm*/0,
        GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(2), /*SubOperand*/0, // src2
        GIR_AddImm8, /*InsnID*/0, /*Imm*/0,
        GIR_AddImm8, /*InsnID*/0, /*Imm*/0,
        GIR_ConstrainSelectedInstOperands, /*InsnID*/0,
        GIR_EraseFromParent, /*InsnID*/0,
        // GIR_Coverage, 6424,
        GIR_Done,
      // Label 4086: @258059
      GIM_Try, /*On fail goto*//*Label 4087*/ GIMT_Encode4(258138), // Rule ID 856 //
        GIM_CheckComplexPattern, /*MI*/0, /*Op*/1, /*Renderer*/GIMT_Encode2(0), GIMT_Encode2(GICP_gi_vop3mods0),
        GIM_CheckComplexPattern, /*MI*/0, /*Op*/2, /*Renderer*/GIMT_Encode2(1), GIMT_Encode2(GICP_gi_vop3mods),
        GIM_CheckComplexPattern, /*MI*/0, /*Op*/3, /*Renderer*/GIMT_Encode2(2), GIMT_Encode2(GICP_gi_vop3mods),
        // (fma:{ *:[f64] } (VOP3Mods0:{ *:[f64] } f64:{ *:[f64] }:$src0, i32:{ *:[i32] }:$src0_modifiers, i1:{ *:[i1] }:$clamp, i32:{ *:[i32] }:$omod), (VOP3Mods:{ *:[f64] } f64:{ *:[f64] }:$src1, i32:{ *:[i32] }:$src1_modifiers), (VOP3Mods:{ *:[f64] } f64:{ *:[f64] }:$src2, i32:{ *:[i32] }:$src2_modifiers))  =>  (V_FMA_F64_e64:{ *:[f64] } i32:{ *:[i32] }:$src0_modifiers, f64:{ *:[f64] }:$src0, i32:{ *:[i32] }:$src1_modifiers, f64:{ *:[f64] }:$src1, i32:{ *:[i32] }:$src2_modifiers, f64:{ *:[f64] }:$src2, i1:{ *:[i1] }:$clamp, i32:{ *:[i32] }:$omod)
        GIR_BuildMI, /*InsnID*/0, /*Opcode*/GIMT_Encode2(AMDGPU::V_FMA_F64_e64),
        GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/0, // DstI[vdst]
        GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/1, // src0_modifiers
        GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/0, // src0
        GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(1), /*SubOperand*/1, // src1_modifiers
        GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(1), /*SubOperand*/0, // src1
        GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(2), /*SubOperand*/1, // src2_modifiers
        GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(2), /*SubOperand*/0, // src2
        GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/2, // clamp
        GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/3, // omod
        GIR_ConstrainSelectedInstOperands, /*InsnID*/0,
        GIR_EraseFromParent, /*InsnID*/0,
        // GIR_Coverage, 856,
        GIR_Done,
      // Label 4087: @258138
      GIM_Try, /*On fail goto*//*Label 4088*/ GIMT_Encode4(258217), // Rule ID 7174 //
        GIM_CheckComplexPattern, /*MI*/0, /*Op*/1, /*Renderer*/GIMT_Encode2(0), GIMT_Encode2(GICP_gi_vop3mods),
        GIM_CheckComplexPattern, /*MI*/0, /*Op*/2, /*Renderer*/GIMT_Encode2(1), GIMT_Encode2(GICP_gi_vop3mods0),
        GIM_CheckComplexPattern, /*MI*/0, /*Op*/3, /*Renderer*/GIMT_Encode2(2), GIMT_Encode2(GICP_gi_vop3mods),
        // (fma:{ *:[f64] } (VOP3Mods:{ *:[f64] } f64:{ *:[f64] }:$src1, i32:{ *:[i32] }:$src1_modifiers), (VOP3Mods0:{ *:[f64] } f64:{ *:[f64] }:$src0, i32:{ *:[i32] }:$src0_modifiers, i1:{ *:[i1] }:$clamp, i32:{ *:[i32] }:$omod), (VOP3Mods:{ *:[f64] } f64:{ *:[f64] }:$src2, i32:{ *:[i32] }:$src2_modifiers))  =>  (V_FMA_F64_e64:{ *:[f64] } i32:{ *:[i32] }:$src0_modifiers, f64:{ *:[f64] }:$src0, i32:{ *:[i32] }:$src1_modifiers, f64:{ *:[f64] }:$src1, i32:{ *:[i32] }:$src2_modifiers, f64:{ *:[f64] }:$src2, i1:{ *:[i1] }:$clamp, i32:{ *:[i32] }:$omod)
        GIR_BuildMI, /*InsnID*/0, /*Opcode*/GIMT_Encode2(AMDGPU::V_FMA_F64_e64),
        GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/0, // DstI[vdst]
        GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(1), /*SubOperand*/1, // src0_modifiers
        GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(1), /*SubOperand*/0, // src0
        GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/1, // src1_modifiers
        GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/0, // src1
        GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(2), /*SubOperand*/1, // src2_modifiers
        GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(2), /*SubOperand*/0, // src2
        GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(1), /*SubOperand*/2, // clamp
        GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(1), /*SubOperand*/3, // omod
        GIR_ConstrainSelectedInstOperands, /*InsnID*/0,
        GIR_EraseFromParent, /*InsnID*/0,
        // GIR_Coverage, 7174,
        GIR_Done,
      // Label 4088: @258217
      GIM_Reject,
    // Label 4085: @258218
    GIM_Reject,
    // Label 4064: @258219
    GIM_Try, /*On fail goto*//*Label 4089*/ GIMT_Encode4(258320), // Rule ID 959 //
      GIM_CheckType, /*MI*/0, /*Op*/1, /*Type*/GILLT_v2s16,
      GIM_CheckType, /*MI*/0, /*Op*/2, /*Type*/GILLT_v2s16,
      GIM_CheckType, /*MI*/0, /*Op*/3, /*Type*/GILLT_v2s16,
      GIM_CheckRegBankForClass, /*MI*/0, /*Op*/0, /*RC*/GIMT_Encode2(AMDGPU::VGPR_32RegClassID),
      GIM_CheckComplexPattern, /*MI*/0, /*Op*/1, /*Renderer*/GIMT_Encode2(0), GIMT_Encode2(GICP_gi_vop3pmods),
      GIM_CheckComplexPattern, /*MI*/0, /*Op*/2, /*Renderer*/GIMT_Encode2(1), GIMT_Encode2(GICP_gi_vop3pmods),
      GIM_CheckComplexPattern, /*MI*/0, /*Op*/3, /*Renderer*/GIMT_Encode2(2), GIMT_Encode2(GICP_gi_vop3pmods),
      // (fma:{ *:[v2f16] } (VOP3PMods:{ *:[v2f16] } v2f16:{ *:[v2f16] }:$src0, i32:{ *:[i32] }:$src0_modifiers), (VOP3PMods:{ *:[v2f16] } v2f16:{ *:[v2f16] }:$src1, i32:{ *:[i32] }:$src1_modifiers), (VOP3PMods:{ *:[v2f16] } v2f16:{ *:[v2f16] }:$src2, i32:{ *:[i32] }:$src2_modifiers))  =>  (V_PK_FMA_F16:{ *:[v2f16] } i32:{ *:[i32] }:$src0_modifiers, v2f16:{ *:[v2f16] }:$src0, i32:{ *:[i32] }:$src1_modifiers, v2f16:{ *:[v2f16] }:$src1, i32:{ *:[i32] }:$src2_modifiers, v2f16:{ *:[v2f16] }:$src2)
      GIR_BuildMI, /*InsnID*/0, /*Opcode*/GIMT_Encode2(AMDGPU::V_PK_FMA_F16),
      GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/0, // DstI[vdst]
      GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/1, // src0_modifiers
      GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/0, // src0
      GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(1), /*SubOperand*/1, // src1_modifiers
      GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(1), /*SubOperand*/0, // src1
      GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(2), /*SubOperand*/1, // src2_modifiers
      GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(2), /*SubOperand*/0, // src2
      GIR_AddImm8, /*InsnID*/0, /*Imm*/0,
      GIR_AddImm8, /*InsnID*/0, /*Imm*/0,
      GIR_AddImm8, /*InsnID*/0, /*Imm*/0,
      GIR_AddImm8, /*InsnID*/0, /*Imm*/0,
      GIR_AddImm8, /*InsnID*/0, /*Imm*/0,
      GIR_ConstrainSelectedInstOperands, /*InsnID*/0,
      GIR_EraseFromParent, /*InsnID*/0,
      // GIR_Coverage, 959,
      GIR_Done,
    // Label 4089: @258320
    GIM_Reject,
    // Label 4065: @258321
    GIM_Try, /*On fail goto*//*Label 4090*/ GIMT_Encode4(258425), // Rule ID 1085 //
      GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasPackedFP32Ops),
      GIM_CheckType, /*MI*/0, /*Op*/1, /*Type*/GILLT_v2s32,
      GIM_CheckType, /*MI*/0, /*Op*/2, /*Type*/GILLT_v2s32,
      GIM_CheckType, /*MI*/0, /*Op*/3, /*Type*/GILLT_v2s32,
      GIM_CheckRegBankForClass, /*MI*/0, /*Op*/0, /*RC*/GIMT_Encode2(AMDGPU::VReg_64RegClassID),
      GIM_CheckComplexPattern, /*MI*/0, /*Op*/1, /*Renderer*/GIMT_Encode2(0), GIMT_Encode2(GICP_gi_vop3pmods),
      GIM_CheckComplexPattern, /*MI*/0, /*Op*/2, /*Renderer*/GIMT_Encode2(1), GIMT_Encode2(GICP_gi_vop3pmods),
      GIM_CheckComplexPattern, /*MI*/0, /*Op*/3, /*Renderer*/GIMT_Encode2(2), GIMT_Encode2(GICP_gi_vop3pmods),
      // (fma:{ *:[v2f32] } (VOP3PMods:{ *:[v2f32] } v2f32:{ *:[v2f32] }:$src0, i32:{ *:[i32] }:$src0_modifiers), (VOP3PMods:{ *:[v2f32] } v2f32:{ *:[v2f32] }:$src1, i32:{ *:[i32] }:$src1_modifiers), (VOP3PMods:{ *:[v2f32] } v2f32:{ *:[v2f32] }:$src2, i32:{ *:[i32] }:$src2_modifiers))  =>  (V_PK_FMA_F32:{ *:[v2f32] } i32:{ *:[i32] }:$src0_modifiers, v2f32:{ *:[v2f32] }:$src0, i32:{ *:[i32] }:$src1_modifiers, v2f32:{ *:[v2f32] }:$src1, i32:{ *:[i32] }:$src2_modifiers, v2f32:{ *:[v2f32] }:$src2)
      GIR_BuildMI, /*InsnID*/0, /*Opcode*/GIMT_Encode2(AMDGPU::V_PK_FMA_F32),
      GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/0, // DstI[vdst]
      GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/1, // src0_modifiers
      GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/0, // src0
      GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(1), /*SubOperand*/1, // src1_modifiers
      GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(1), /*SubOperand*/0, // src1
      GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(2), /*SubOperand*/1, // src2_modifiers
      GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(2), /*SubOperand*/0, // src2
      GIR_AddImm8, /*InsnID*/0, /*Imm*/0,
      GIR_AddImm8, /*InsnID*/0, /*Imm*/0,
      GIR_AddImm8, /*InsnID*/0, /*Imm*/0,
      GIR_AddImm8, /*InsnID*/0, /*Imm*/0,
      GIR_AddImm8, /*InsnID*/0, /*Imm*/0,
      GIR_ConstrainSelectedInstOperands, /*InsnID*/0,
      GIR_EraseFromParent, /*InsnID*/0,
      // GIR_Coverage, 1085,
      GIR_Done,
    // Label 4090: @258425
    GIM_Reject,
    // Label 4066: @258426
    GIM_Reject,
    // Label 60: @258427
    GIM_SwitchType, /*MI*/0, /*Op*/0, /*[*/GIMT_Encode2(8), GIMT_Encode2(10), /*)*//*default:*//*Label 4093*/ GIMT_Encode4(259452),
    /*GILLT_s16*//*Label 4091*/ GIMT_Encode4(258446),
    /*GILLT_s32*//*Label 4092*/ GIMT_Encode4(258706),
    // Label 4091: @258446
    GIM_Try, /*On fail goto*//*Label 4094*/ GIMT_Encode4(258705),
      GIM_CheckType, /*MI*/0, /*Op*/1, /*Type*/GILLT_s16,
      GIM_CheckType, /*MI*/0, /*Op*/2, /*Type*/GILLT_s16,
      GIM_CheckType, /*MI*/0, /*Op*/3, /*Type*/GILLT_s16,
      GIM_CheckRegBankForClass, /*MI*/0, /*Op*/0, /*RC*/GIMT_Encode2(AMDGPU::VGPR_32RegClassID),
      GIM_Try, /*On fail goto*//*Label 4095*/ GIMT_Encode4(258540), // Rule ID 5892 //
        GIM_CheckFeatures, GIMT_Encode2(GIFBS_Has16BitInsts),
        GIM_CheckComplexPattern, /*MI*/0, /*Op*/1, /*Renderer*/GIMT_Encode2(0), GIMT_Encode2(GICP_gi_vop3_no_mods),
        GIM_CheckComplexPattern, /*MI*/0, /*Op*/2, /*Renderer*/GIMT_Encode2(1), GIMT_Encode2(GICP_gi_vop3_no_mods),
        GIM_CheckComplexPattern, /*MI*/0, /*Op*/3, /*Renderer*/GIMT_Encode2(2), GIMT_Encode2(GICP_gi_vop3_no_mods),
        // (fmad:{ *:[f16] } (VOP3NoMods:{ *:[f16] } f16:{ *:[f16] }:$src0), (VOP3NoMods:{ *:[f16] } f16:{ *:[f16] }:$src1), (VOP3NoMods:{ *:[f16] } f16:{ *:[f16] }:$src2))  =>  (V_MAC_F16_e64:{ *:[f16] } 0:{ *:[i32] }, ?:{ *:[f16] }:$src0, 0:{ *:[i32] }, ?:{ *:[f16] }:$src1, 0:{ *:[i32] }, ?:{ *:[f16] }:$src2, 0:{ *:[i1] }, 0:{ *:[i32] })
        GIR_BuildMI, /*InsnID*/0, /*Opcode*/GIMT_Encode2(AMDGPU::V_MAC_F16_e64),
        GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/0, // DstI[vdst]
        GIR_AddImm8, /*InsnID*/0, /*Imm*/0,
        GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/0, // src0
        GIR_AddImm8, /*InsnID*/0, /*Imm*/0,
        GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(1), /*SubOperand*/0, // src1
        GIR_AddImm8, /*InsnID*/0, /*Imm*/0,
        GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(2), /*SubOperand*/0, // src2
        GIR_AddImm8, /*InsnID*/0, /*Imm*/0,
        GIR_AddImm8, /*InsnID*/0, /*Imm*/0,
        GIR_ConstrainSelectedInstOperands, /*InsnID*/0,
        GIR_EraseFromParent, /*InsnID*/0,
        // GIR_Coverage, 5892,
        GIR_Done,
      // Label 4095: @258540
      GIM_Try, /*On fail goto*//*Label 4096*/ GIMT_Encode4(258622), // Rule ID 927 //
        GIM_CheckFeatures, GIMT_Encode2(GIFBS_Has16BitInsts),
        GIM_CheckComplexPattern, /*MI*/0, /*Op*/1, /*Renderer*/GIMT_Encode2(0), GIMT_Encode2(GICP_gi_vop3mods0),
        GIM_CheckComplexPattern, /*MI*/0, /*Op*/2, /*Renderer*/GIMT_Encode2(1), GIMT_Encode2(GICP_gi_vop3mods),
        GIM_CheckComplexPattern, /*MI*/0, /*Op*/3, /*Renderer*/GIMT_Encode2(2), GIMT_Encode2(GICP_gi_vop3mods),
        // (fmad:{ *:[f16] } (VOP3Mods0:{ *:[f16] } f16:{ *:[f16] }:$src0, i32:{ *:[i32] }:$src0_modifiers, i1:{ *:[i1] }:$clamp, i32:{ *:[i32] }:$omod), (VOP3Mods:{ *:[f16] } f16:{ *:[f16] }:$src1, i32:{ *:[i32] }:$src1_modifiers), (VOP3Mods:{ *:[f16] } f16:{ *:[f16] }:$src2, i32:{ *:[i32] }:$src2_modifiers))  =>  (V_MAD_F16_e64:{ *:[f16] } i32:{ *:[i32] }:$src0_modifiers, f16:{ *:[f16] }:$src0, i32:{ *:[i32] }:$src1_modifiers, f16:{ *:[f16] }:$src1, i32:{ *:[i32] }:$src2_modifiers, f16:{ *:[f16] }:$src2, i1:{ *:[i1] }:$clamp, i32:{ *:[i32] }:$omod)
        GIR_BuildMI, /*InsnID*/0, /*Opcode*/GIMT_Encode2(AMDGPU::V_MAD_F16_e64),
        GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/0, // DstI[vdst]
        GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/1, // src0_modifiers
        GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/0, // src0
        GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(1), /*SubOperand*/1, // src1_modifiers
        GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(1), /*SubOperand*/0, // src1
        GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(2), /*SubOperand*/1, // src2_modifiers
        GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(2), /*SubOperand*/0, // src2
        GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/2, // clamp
        GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/3, // omod
        GIR_ConstrainSelectedInstOperands, /*InsnID*/0,
        GIR_EraseFromParent, /*InsnID*/0,
        // GIR_Coverage, 927,
        GIR_Done,
      // Label 4096: @258622
      GIM_Try, /*On fail goto*//*Label 4097*/ GIMT_Encode4(258704), // Rule ID 7194 //
        GIM_CheckFeatures, GIMT_Encode2(GIFBS_Has16BitInsts),
        GIM_CheckComplexPattern, /*MI*/0, /*Op*/1, /*Renderer*/GIMT_Encode2(0), GIMT_Encode2(GICP_gi_vop3mods),
        GIM_CheckComplexPattern, /*MI*/0, /*Op*/2, /*Renderer*/GIMT_Encode2(1), GIMT_Encode2(GICP_gi_vop3mods0),
        GIM_CheckComplexPattern, /*MI*/0, /*Op*/3, /*Renderer*/GIMT_Encode2(2), GIMT_Encode2(GICP_gi_vop3mods),
        // (fmad:{ *:[f16] } (VOP3Mods:{ *:[f16] } f16:{ *:[f16] }:$src1, i32:{ *:[i32] }:$src1_modifiers), (VOP3Mods0:{ *:[f16] } f16:{ *:[f16] }:$src0, i32:{ *:[i32] }:$src0_modifiers, i1:{ *:[i1] }:$clamp, i32:{ *:[i32] }:$omod), (VOP3Mods:{ *:[f16] } f16:{ *:[f16] }:$src2, i32:{ *:[i32] }:$src2_modifiers))  =>  (V_MAD_F16_e64:{ *:[f16] } i32:{ *:[i32] }:$src0_modifiers, f16:{ *:[f16] }:$src0, i32:{ *:[i32] }:$src1_modifiers, f16:{ *:[f16] }:$src1, i32:{ *:[i32] }:$src2_modifiers, f16:{ *:[f16] }:$src2, i1:{ *:[i1] }:$clamp, i32:{ *:[i32] }:$omod)
        GIR_BuildMI, /*InsnID*/0, /*Opcode*/GIMT_Encode2(AMDGPU::V_MAD_F16_e64),
        GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/0, // DstI[vdst]
        GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(1), /*SubOperand*/1, // src0_modifiers
        GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(1), /*SubOperand*/0, // src0
        GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/1, // src1_modifiers
        GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/0, // src1
        GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(2), /*SubOperand*/1, // src2_modifiers
        GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(2), /*SubOperand*/0, // src2
        GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(1), /*SubOperand*/2, // clamp
        GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(1), /*SubOperand*/3, // omod
        GIR_ConstrainSelectedInstOperands, /*InsnID*/0,
        GIR_EraseFromParent, /*InsnID*/0,
        // GIR_Coverage, 7194,
        GIR_Done,
      // Label 4097: @258704
      GIM_Reject,
    // Label 4094: @258705
    GIM_Reject,
    // Label 4092: @258706
    GIM_Try, /*On fail goto*//*Label 4098*/ GIMT_Encode4(259451),
      GIM_CheckType, /*MI*/0, /*Op*/1, /*Type*/GILLT_s32,
      GIM_CheckType, /*MI*/0, /*Op*/2, /*Type*/GILLT_s32,
      GIM_CheckType, /*MI*/0, /*Op*/3, /*Type*/GILLT_s32,
      GIM_CheckRegBankForClass, /*MI*/0, /*Op*/0, /*RC*/GIMT_Encode2(AMDGPU::VGPR_32RegClassID),
      GIM_Try, /*On fail goto*//*Label 4099*/ GIMT_Encode4(258809), // Rule ID 2249 //
        GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasMadMixInsts_NoFP32Denormals),
        GIM_CheckComplexPattern, /*MI*/0, /*Op*/1, /*Renderer*/GIMT_Encode2(0), GIMT_Encode2(GICP_gi_vop3_mad_mix_mods_ext),
        GIM_CheckComplexPattern, /*MI*/0, /*Op*/2, /*Renderer*/GIMT_Encode2(1), GIMT_Encode2(GICP_gi_vop3_mad_mix_mods),
        GIM_CheckComplexPattern, /*MI*/0, /*Op*/3, /*Renderer*/GIMT_Encode2(2), GIMT_Encode2(GICP_gi_vop3_mad_mix_mods),
        // (fmad:{ *:[f32] } (VOP3PMadMixModsExt:{ *:[f32] } f16:{ *:[f16] }:$src0, i32:{ *:[i32] }:$src0_mods), (VOP3PMadMixMods:{ *:[f32] } f16:{ *:[f16] }:$src1, i32:{ *:[i32] }:$src1_mods), (VOP3PMadMixMods:{ *:[f32] } f16:{ *:[f16] }:$src2, i32:{ *:[i32] }:$src2_mods))  =>  (V_MAD_MIX_F32:{ *:[f32] } ?:{ *:[i32] }:$src0_mods, ?:{ *:[f16] }:$src0, ?:{ *:[i32] }:$src1_mods, ?:{ *:[f16] }:$src1, ?:{ *:[i32] }:$src2_mods, ?:{ *:[f16] }:$src2, 0:{ *:[i1] })
        GIR_BuildMI, /*InsnID*/0, /*Opcode*/GIMT_Encode2(AMDGPU::V_MAD_MIX_F32),
        GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/0, // DstI[vdst]
        GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/1, // src0_mods
        GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/0, // src0
        GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(1), /*SubOperand*/1, // src1_mods
        GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(1), /*SubOperand*/0, // src1
        GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(2), /*SubOperand*/1, // src2_mods
        GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(2), /*SubOperand*/0, // src2
        GIR_AddImm8, /*InsnID*/0, /*Imm*/0,
        GIR_AddImm8, /*InsnID*/0, /*Imm*/0,
        GIR_AddImm8, /*InsnID*/0, /*Imm*/0,
        GIR_ConstrainSelectedInstOperands, /*InsnID*/0,
        GIR_EraseFromParent, /*InsnID*/0,
        // GIR_Coverage, 2249,
        GIR_Done,
      // Label 4099: @258809
      GIM_Try, /*On fail goto*//*Label 4100*/ GIMT_Encode4(258890), // Rule ID 2250 //
        GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasMadMixInsts_NoFP32Denormals),
        GIM_CheckComplexPattern, /*MI*/0, /*Op*/1, /*Renderer*/GIMT_Encode2(0), GIMT_Encode2(GICP_gi_vop3_mad_mix_mods),
        GIM_CheckComplexPattern, /*MI*/0, /*Op*/2, /*Renderer*/GIMT_Encode2(1), GIMT_Encode2(GICP_gi_vop3_mad_mix_mods_ext),
        GIM_CheckComplexPattern, /*MI*/0, /*Op*/3, /*Renderer*/GIMT_Encode2(2), GIMT_Encode2(GICP_gi_vop3_mad_mix_mods),
        // (fmad:{ *:[f32] } (VOP3PMadMixMods:{ *:[f32] } f16:{ *:[f16] }:$src0, i32:{ *:[i32] }:$src0_mods), (VOP3PMadMixModsExt:{ *:[f32] } f16:{ *:[f16] }:$src1, i32:{ *:[i32] }:$src1_mods), (VOP3PMadMixMods:{ *:[f32] } f32:{ *:[f32] }:$src2, i32:{ *:[i32] }:$src2_mods))  =>  (V_MAD_MIX_F32:{ *:[f32] } ?:{ *:[i32] }:$src0_mods, ?:{ *:[f16] }:$src0, ?:{ *:[i32] }:$src1_mods, ?:{ *:[f16] }:$src1, ?:{ *:[i32] }:$src2_mods, ?:{ *:[f32] }:$src2, 0:{ *:[i1] })
        GIR_BuildMI, /*InsnID*/0, /*Opcode*/GIMT_Encode2(AMDGPU::V_MAD_MIX_F32),
        GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/0, // DstI[vdst]
        GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/1, // src0_mods
        GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/0, // src0
        GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(1), /*SubOperand*/1, // src1_mods
        GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(1), /*SubOperand*/0, // src1
        GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(2), /*SubOperand*/1, // src2_mods
        GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(2), /*SubOperand*/0, // src2
        GIR_AddImm8, /*InsnID*/0, /*Imm*/0,
        GIR_AddImm8, /*InsnID*/0, /*Imm*/0,
        GIR_AddImm8, /*InsnID*/0, /*Imm*/0,
        GIR_ConstrainSelectedInstOperands, /*InsnID*/0,
        GIR_EraseFromParent, /*InsnID*/0,
        // GIR_Coverage, 2250,
        GIR_Done,
      // Label 4100: @258890
      GIM_Try, /*On fail goto*//*Label 4101*/ GIMT_Encode4(258971), // Rule ID 2251 //
        GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasMadMixInsts_NoFP32Denormals),
        GIM_CheckComplexPattern, /*MI*/0, /*Op*/1, /*Renderer*/GIMT_Encode2(0), GIMT_Encode2(GICP_gi_vop3_mad_mix_mods),
        GIM_CheckComplexPattern, /*MI*/0, /*Op*/2, /*Renderer*/GIMT_Encode2(1), GIMT_Encode2(GICP_gi_vop3_mad_mix_mods),
        GIM_CheckComplexPattern, /*MI*/0, /*Op*/3, /*Renderer*/GIMT_Encode2(2), GIMT_Encode2(GICP_gi_vop3_mad_mix_mods_ext),
        // (fmad:{ *:[f32] } (VOP3PMadMixMods:{ *:[f32] } f16:{ *:[f16] }:$src0, i32:{ *:[i32] }:$src0_mods), (VOP3PMadMixMods:{ *:[f32] } f32:{ *:[f32] }:$src1, i32:{ *:[i32] }:$src1_mods), (VOP3PMadMixModsExt:{ *:[f32] } f16:{ *:[f16] }:$src2, i32:{ *:[i32] }:$src2_mods))  =>  (V_MAD_MIX_F32:{ *:[f32] } ?:{ *:[i32] }:$src0_mods, ?:{ *:[f16] }:$src0, ?:{ *:[i32] }:$src1_mods, ?:{ *:[f32] }:$src1, ?:{ *:[i32] }:$src2_mods, ?:{ *:[f16] }:$src2, 0:{ *:[i1] })
        GIR_BuildMI, /*InsnID*/0, /*Opcode*/GIMT_Encode2(AMDGPU::V_MAD_MIX_F32),
        GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/0, // DstI[vdst]
        GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/1, // src0_mods
        GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/0, // src0
        GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(1), /*SubOperand*/1, // src1_mods
        GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(1), /*SubOperand*/0, // src1
        GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(2), /*SubOperand*/1, // src2_mods
        GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(2), /*SubOperand*/0, // src2
        GIR_AddImm8, /*InsnID*/0, /*Imm*/0,
        GIR_AddImm8, /*InsnID*/0, /*Imm*/0,
        GIR_AddImm8, /*InsnID*/0, /*Imm*/0,
        GIR_ConstrainSelectedInstOperands, /*InsnID*/0,
        GIR_EraseFromParent, /*InsnID*/0,
        // GIR_Coverage, 2251,
        GIR_Done,
      // Label 4101: @258971
      GIM_Try, /*On fail goto*//*Label 4102*/ GIMT_Encode4(259043), // Rule ID 5886 //
        GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasMadMacF32Insts),
        GIM_CheckComplexPattern, /*MI*/0, /*Op*/1, /*Renderer*/GIMT_Encode2(0), GIMT_Encode2(GICP_gi_vop3_no_mods),
        GIM_CheckComplexPattern, /*MI*/0, /*Op*/2, /*Renderer*/GIMT_Encode2(1), GIMT_Encode2(GICP_gi_vop3_no_mods),
        GIM_CheckComplexPattern, /*MI*/0, /*Op*/3, /*Renderer*/GIMT_Encode2(2), GIMT_Encode2(GICP_gi_vop3_no_mods),
        // (fmad:{ *:[f32] } (VOP3NoMods:{ *:[f32] } f32:{ *:[f32] }:$src0), (VOP3NoMods:{ *:[f32] } f32:{ *:[f32] }:$src1), (VOP3NoMods:{ *:[f32] } f32:{ *:[f32] }:$src2))  =>  (V_MAC_F32_e64:{ *:[f32] } 0:{ *:[i32] }, ?:{ *:[f32] }:$src0, 0:{ *:[i32] }, ?:{ *:[f32] }:$src1, 0:{ *:[i32] }, ?:{ *:[f32] }:$src2, 0:{ *:[i1] }, 0:{ *:[i32] })
        GIR_BuildMI, /*InsnID*/0, /*Opcode*/GIMT_Encode2(AMDGPU::V_MAC_F32_e64),
        GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/0, // DstI[vdst]
        GIR_AddImm8, /*InsnID*/0, /*Imm*/0,
        GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/0, // src0
        GIR_AddImm8, /*InsnID*/0, /*Imm*/0,
        GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(1), /*SubOperand*/0, // src1
        GIR_AddImm8, /*InsnID*/0, /*Imm*/0,
        GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(2), /*SubOperand*/0, // src2
        GIR_AddImm8, /*InsnID*/0, /*Imm*/0,
        GIR_AddImm8, /*InsnID*/0, /*Imm*/0,
        GIR_ConstrainSelectedInstOperands, /*InsnID*/0,
        GIR_EraseFromParent, /*InsnID*/0,
        // GIR_Coverage, 5886,
        GIR_Done,
      // Label 4102: @259043
      GIM_Try, /*On fail goto*//*Label 4103*/ GIMT_Encode4(259124), // Rule ID 7226 //
        GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasMadMixInsts_NoFP32Denormals),
        GIM_CheckComplexPattern, /*MI*/0, /*Op*/1, /*Renderer*/GIMT_Encode2(0), GIMT_Encode2(GICP_gi_vop3_mad_mix_mods),
        GIM_CheckComplexPattern, /*MI*/0, /*Op*/2, /*Renderer*/GIMT_Encode2(1), GIMT_Encode2(GICP_gi_vop3_mad_mix_mods_ext),
        GIM_CheckComplexPattern, /*MI*/0, /*Op*/3, /*Renderer*/GIMT_Encode2(2), GIMT_Encode2(GICP_gi_vop3_mad_mix_mods),
        // (fmad:{ *:[f32] } (VOP3PMadMixMods:{ *:[f32] } f16:{ *:[f16] }:$src1, i32:{ *:[i32] }:$src1_mods), (VOP3PMadMixModsExt:{ *:[f32] } f16:{ *:[f16] }:$src0, i32:{ *:[i32] }:$src0_mods), (VOP3PMadMixMods:{ *:[f32] } f16:{ *:[f16] }:$src2, i32:{ *:[i32] }:$src2_mods))  =>  (V_MAD_MIX_F32:{ *:[f32] } ?:{ *:[i32] }:$src0_mods, ?:{ *:[f16] }:$src0, ?:{ *:[i32] }:$src1_mods, ?:{ *:[f16] }:$src1, ?:{ *:[i32] }:$src2_mods, ?:{ *:[f16] }:$src2, 0:{ *:[i1] })
        GIR_BuildMI, /*InsnID*/0, /*Opcode*/GIMT_Encode2(AMDGPU::V_MAD_MIX_F32),
        GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/0, // DstI[vdst]
        GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(1), /*SubOperand*/1, // src0_mods
        GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(1), /*SubOperand*/0, // src0
        GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/1, // src1_mods
        GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/0, // src1
        GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(2), /*SubOperand*/1, // src2_mods
        GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(2), /*SubOperand*/0, // src2
        GIR_AddImm8, /*InsnID*/0, /*Imm*/0,
        GIR_AddImm8, /*InsnID*/0, /*Imm*/0,
        GIR_AddImm8, /*InsnID*/0, /*Imm*/0,
        GIR_ConstrainSelectedInstOperands, /*InsnID*/0,
        GIR_EraseFromParent, /*InsnID*/0,
        // GIR_Coverage, 7226,
        GIR_Done,
      // Label 4103: @259124
      GIM_Try, /*On fail goto*//*Label 4104*/ GIMT_Encode4(259205), // Rule ID 7227 //
        GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasMadMixInsts_NoFP32Denormals),
        GIM_CheckComplexPattern, /*MI*/0, /*Op*/1, /*Renderer*/GIMT_Encode2(0), GIMT_Encode2(GICP_gi_vop3_mad_mix_mods_ext),
        GIM_CheckComplexPattern, /*MI*/0, /*Op*/2, /*Renderer*/GIMT_Encode2(1), GIMT_Encode2(GICP_gi_vop3_mad_mix_mods),
        GIM_CheckComplexPattern, /*MI*/0, /*Op*/3, /*Renderer*/GIMT_Encode2(2), GIMT_Encode2(GICP_gi_vop3_mad_mix_mods),
        // (fmad:{ *:[f32] } (VOP3PMadMixModsExt:{ *:[f32] } f16:{ *:[f16] }:$src1, i32:{ *:[i32] }:$src1_mods), (VOP3PMadMixMods:{ *:[f32] } f16:{ *:[f16] }:$src0, i32:{ *:[i32] }:$src0_mods), (VOP3PMadMixMods:{ *:[f32] } f32:{ *:[f32] }:$src2, i32:{ *:[i32] }:$src2_mods))  =>  (V_MAD_MIX_F32:{ *:[f32] } ?:{ *:[i32] }:$src0_mods, ?:{ *:[f16] }:$src0, ?:{ *:[i32] }:$src1_mods, ?:{ *:[f16] }:$src1, ?:{ *:[i32] }:$src2_mods, ?:{ *:[f32] }:$src2, 0:{ *:[i1] })
        GIR_BuildMI, /*InsnID*/0, /*Opcode*/GIMT_Encode2(AMDGPU::V_MAD_MIX_F32),
        GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/0, // DstI[vdst]
        GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(1), /*SubOperand*/1, // src0_mods
        GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(1), /*SubOperand*/0, // src0
        GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/1, // src1_mods
        GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/0, // src1
        GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(2), /*SubOperand*/1, // src2_mods
        GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(2), /*SubOperand*/0, // src2
        GIR_AddImm8, /*InsnID*/0, /*Imm*/0,
        GIR_AddImm8, /*InsnID*/0, /*Imm*/0,
        GIR_AddImm8, /*InsnID*/0, /*Imm*/0,
        GIR_ConstrainSelectedInstOperands, /*InsnID*/0,
        GIR_EraseFromParent, /*InsnID*/0,
        // GIR_Coverage, 7227,
        GIR_Done,
      // Label 4104: @259205
      GIM_Try, /*On fail goto*//*Label 4105*/ GIMT_Encode4(259286), // Rule ID 7228 //
        GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasMadMixInsts_NoFP32Denormals),
        GIM_CheckComplexPattern, /*MI*/0, /*Op*/1, /*Renderer*/GIMT_Encode2(0), GIMT_Encode2(GICP_gi_vop3_mad_mix_mods),
        GIM_CheckComplexPattern, /*MI*/0, /*Op*/2, /*Renderer*/GIMT_Encode2(1), GIMT_Encode2(GICP_gi_vop3_mad_mix_mods),
        GIM_CheckComplexPattern, /*MI*/0, /*Op*/3, /*Renderer*/GIMT_Encode2(2), GIMT_Encode2(GICP_gi_vop3_mad_mix_mods_ext),
        // (fmad:{ *:[f32] } (VOP3PMadMixMods:{ *:[f32] } f32:{ *:[f32] }:$src1, i32:{ *:[i32] }:$src1_mods), (VOP3PMadMixMods:{ *:[f32] } f16:{ *:[f16] }:$src0, i32:{ *:[i32] }:$src0_mods), (VOP3PMadMixModsExt:{ *:[f32] } f16:{ *:[f16] }:$src2, i32:{ *:[i32] }:$src2_mods))  =>  (V_MAD_MIX_F32:{ *:[f32] } ?:{ *:[i32] }:$src0_mods, ?:{ *:[f16] }:$src0, ?:{ *:[i32] }:$src1_mods, ?:{ *:[f32] }:$src1, ?:{ *:[i32] }:$src2_mods, ?:{ *:[f16] }:$src2, 0:{ *:[i1] })
        GIR_BuildMI, /*InsnID*/0, /*Opcode*/GIMT_Encode2(AMDGPU::V_MAD_MIX_F32),
        GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/0, // DstI[vdst]
        GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(1), /*SubOperand*/1, // src0_mods
        GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(1), /*SubOperand*/0, // src0
        GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/1, // src1_mods
        GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/0, // src1
        GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(2), /*SubOperand*/1, // src2_mods
        GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(2), /*SubOperand*/0, // src2
        GIR_AddImm8, /*InsnID*/0, /*Imm*/0,
        GIR_AddImm8, /*InsnID*/0, /*Imm*/0,
        GIR_AddImm8, /*InsnID*/0, /*Imm*/0,
        GIR_ConstrainSelectedInstOperands, /*InsnID*/0,
        GIR_EraseFromParent, /*InsnID*/0,
        // GIR_Coverage, 7228,
        GIR_Done,
      // Label 4105: @259286
      GIM_Try, /*On fail goto*//*Label 4106*/ GIMT_Encode4(259368), // Rule ID 848 //
        GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasMadMacF32Insts),
        GIM_CheckComplexPattern, /*MI*/0, /*Op*/1, /*Renderer*/GIMT_Encode2(0), GIMT_Encode2(GICP_gi_vop3mods0),
        GIM_CheckComplexPattern, /*MI*/0, /*Op*/2, /*Renderer*/GIMT_Encode2(1), GIMT_Encode2(GICP_gi_vop3mods),
        GIM_CheckComplexPattern, /*MI*/0, /*Op*/3, /*Renderer*/GIMT_Encode2(2), GIMT_Encode2(GICP_gi_vop3mods),
        // (fmad:{ *:[f32] } (VOP3Mods0:{ *:[f32] } f32:{ *:[f32] }:$src0, i32:{ *:[i32] }:$src0_modifiers, i1:{ *:[i1] }:$clamp, i32:{ *:[i32] }:$omod), (VOP3Mods:{ *:[f32] } f32:{ *:[f32] }:$src1, i32:{ *:[i32] }:$src1_modifiers), (VOP3Mods:{ *:[f32] } f32:{ *:[f32] }:$src2, i32:{ *:[i32] }:$src2_modifiers))  =>  (V_MAD_F32_e64:{ *:[f32] } i32:{ *:[i32] }:$src0_modifiers, f32:{ *:[f32] }:$src0, i32:{ *:[i32] }:$src1_modifiers, f32:{ *:[f32] }:$src1, i32:{ *:[i32] }:$src2_modifiers, f32:{ *:[f32] }:$src2, i1:{ *:[i1] }:$clamp, i32:{ *:[i32] }:$omod)
        GIR_BuildMI, /*InsnID*/0, /*Opcode*/GIMT_Encode2(AMDGPU::V_MAD_F32_e64),
        GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/0, // DstI[vdst]
        GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/1, // src0_modifiers
        GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/0, // src0
        GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(1), /*SubOperand*/1, // src1_modifiers
        GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(1), /*SubOperand*/0, // src1
        GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(2), /*SubOperand*/1, // src2_modifiers
        GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(2), /*SubOperand*/0, // src2
        GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/2, // clamp
        GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/3, // omod
        GIR_ConstrainSelectedInstOperands, /*InsnID*/0,
        GIR_EraseFromParent, /*InsnID*/0,
        // GIR_Coverage, 848,
        GIR_Done,
      // Label 4106: @259368
      GIM_Try, /*On fail goto*//*Label 4107*/ GIMT_Encode4(259450), // Rule ID 7169 //
        GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasMadMacF32Insts),
        GIM_CheckComplexPattern, /*MI*/0, /*Op*/1, /*Renderer*/GIMT_Encode2(0), GIMT_Encode2(GICP_gi_vop3mods),
        GIM_CheckComplexPattern, /*MI*/0, /*Op*/2, /*Renderer*/GIMT_Encode2(1), GIMT_Encode2(GICP_gi_vop3mods0),
        GIM_CheckComplexPattern, /*MI*/0, /*Op*/3, /*Renderer*/GIMT_Encode2(2), GIMT_Encode2(GICP_gi_vop3mods),
        // (fmad:{ *:[f32] } (VOP3Mods:{ *:[f32] } f32:{ *:[f32] }:$src1, i32:{ *:[i32] }:$src1_modifiers), (VOP3Mods0:{ *:[f32] } f32:{ *:[f32] }:$src0, i32:{ *:[i32] }:$src0_modifiers, i1:{ *:[i1] }:$clamp, i32:{ *:[i32] }:$omod), (VOP3Mods:{ *:[f32] } f32:{ *:[f32] }:$src2, i32:{ *:[i32] }:$src2_modifiers))  =>  (V_MAD_F32_e64:{ *:[f32] } i32:{ *:[i32] }:$src0_modifiers, f32:{ *:[f32] }:$src0, i32:{ *:[i32] }:$src1_modifiers, f32:{ *:[f32] }:$src1, i32:{ *:[i32] }:$src2_modifiers, f32:{ *:[f32] }:$src2, i1:{ *:[i1] }:$clamp, i32:{ *:[i32] }:$omod)
        GIR_BuildMI, /*InsnID*/0, /*Opcode*/GIMT_Encode2(AMDGPU::V_MAD_F32_e64),
        GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/0, // DstI[vdst]
        GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(1), /*SubOperand*/1, // src0_modifiers
        GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(1), /*SubOperand*/0, // src0
        GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/1, // src1_modifiers
        GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/0, // src1
        GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(2), /*SubOperand*/1, // src2_modifiers
        GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(2), /*SubOperand*/0, // src2
        GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(1), /*SubOperand*/2, // clamp
        GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(1), /*SubOperand*/3, // omod
        GIR_ConstrainSelectedInstOperands, /*InsnID*/0,
        GIR_EraseFromParent, /*InsnID*/0,
        // GIR_Coverage, 7169,
        GIR_Done,
      // Label 4107: @259450
      GIM_Reject,
    // Label 4098: @259451
    GIM_Reject,
    // Label 4093: @259452
    GIM_Reject,
    // Label 61: @259453
    GIM_Try, /*On fail goto*//*Label 4108*/ GIMT_Encode4(259580), // Rule ID 6264 //
      GIM_CheckType, /*MI*/0, /*Op*/0, /*Type*/GILLT_s32,
      GIM_CheckType, /*MI*/0, /*Op*/1, /*Type*/GILLT_s32,
      GIM_CheckType, /*MI*/0, /*Op*/2, /*Type*/GILLT_s32,
      GIM_CheckRegBankForClass, /*MI*/0, /*Op*/0, /*RC*/GIMT_Encode2(AMDGPU::VGPR_32RegClassID),
      GIM_CheckComplexPattern, /*MI*/0, /*Op*/1, /*Renderer*/GIMT_Encode2(0), GIMT_Encode2(GICP_gi_vop3mods),
      GIM_CheckComplexPattern, /*MI*/0, /*Op*/2, /*Renderer*/GIMT_Encode2(1), GIMT_Encode2(GICP_gi_vop3mods),
      // (fpow:{ *:[f32] } (VOP3Mods:{ *:[f32] } f32:{ *:[f32] }:$src0, i32:{ *:[i32] }:$src0_mods), (VOP3Mods:{ *:[f32] } f32:{ *:[f32] }:$src1, i32:{ *:[i32] }:$src1_mods))  =>  (V_EXP_F32_e64:{ *:[f32] } 0:{ *:[i32] }, (V_MUL_LEGACY_F32_e64:{ *:[i16] } ?:{ *:[i32] }:$src1_mods, ?:{ *:[f32] }:$src1, 0:{ *:[i32] }, (V_LOG_F32_e64:{ *:[i16] } ?:{ *:[i32] }:$src0_mods, ?:{ *:[f32] }:$src0), 0:{ *:[i1] }, 0:{ *:[i32] }))
      GIR_MakeTempReg, /*TempRegID*/0, /*TypeID*/GILLT_s16,
      GIR_MakeTempReg, /*TempRegID*/1, /*TypeID*/GILLT_s16,
      GIR_BuildMI, /*InsnID*/2, /*Opcode*/GIMT_Encode2(AMDGPU::V_LOG_F32_e64),
      GIR_AddTempRegister, /*InsnID*/2, /*TempRegID*/1, /*TempRegFlags*/GIMT_Encode2(RegState::Define),
      GIR_ComplexSubOperandRenderer, /*InsnID*/2, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/1, // src0_mods
      GIR_ComplexSubOperandRenderer, /*InsnID*/2, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/0, // src0
      GIR_AddImm8, /*InsnID*/2, /*Imm*/0,
      GIR_AddImm8, /*InsnID*/2, /*Imm*/0,
      GIR_ConstrainSelectedInstOperands, /*InsnID*/2,
      GIR_BuildMI, /*InsnID*/1, /*Opcode*/GIMT_Encode2(AMDGPU::V_MUL_LEGACY_F32_e64),
      GIR_AddTempRegister, /*InsnID*/1, /*TempRegID*/0, /*TempRegFlags*/GIMT_Encode2(RegState::Define),
      GIR_ComplexSubOperandRenderer, /*InsnID*/1, /*RendererID*/GIMT_Encode2(1), /*SubOperand*/1, // src1_mods
      GIR_ComplexSubOperandRenderer, /*InsnID*/1, /*RendererID*/GIMT_Encode2(1), /*SubOperand*/0, // src1
      GIR_AddImm8, /*InsnID*/1, /*Imm*/0,
      GIR_AddSimpleTempRegister, /*InsnID*/1, /*TempRegID*/1,
      GIR_AddImm8, /*InsnID*/1, /*Imm*/0,
      GIR_AddImm8, /*InsnID*/1, /*Imm*/0,
      GIR_ConstrainSelectedInstOperands, /*InsnID*/1,
      GIR_BuildMI, /*InsnID*/0, /*Opcode*/GIMT_Encode2(AMDGPU::V_EXP_F32_e64),
      GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/0, // DstI[vdst]
      GIR_AddImm8, /*InsnID*/0, /*Imm*/0,
      GIR_AddSimpleTempRegister, /*InsnID*/0, /*TempRegID*/0,
      GIR_AddImm8, /*InsnID*/0, /*Imm*/0,
      GIR_AddImm8, /*InsnID*/0, /*Imm*/0,
      GIR_ConstrainSelectedInstOperands, /*InsnID*/0,
      GIR_EraseFromParent, /*InsnID*/0,
      // GIR_Coverage, 6264,
      GIR_Done,
    // Label 4108: @259580
    GIM_Reject,
    // Label 62: @259581
    GIM_Try, /*On fail goto*//*Label 4109*/ GIMT_Encode4(259831),
      GIM_CheckType, /*MI*/0, /*Op*/0, /*Type*/GILLT_s16,
      GIM_CheckType, /*MI*/0, /*Op*/1, /*Type*/GILLT_s16,
      GIM_Try, /*On fail goto*//*Label 4110*/ GIMT_Encode4(259671), // Rule ID 2227 //
        GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasPseudoScalarTrans),
        GIM_CheckRegBankForClass, /*MI*/0, /*Op*/0, /*RC*/GIMT_Encode2(AMDGPU::SReg_32_XEXECRegClassID),
        GIM_CheckCxxInsnPredicate, /*MI*/0, /*FnId*/GIMT_Encode2(GICXXPred_MI_Predicate_anonymous_23778),
        GIM_CheckComplexPattern, /*MI*/0, /*Op*/1, /*Renderer*/GIMT_Encode2(0), GIMT_Encode2(GICP_gi_vop3mods0),
        // (fexp2:{ *:[f16] } (VOP3Mods0:{ *:[f16] } f16:{ *:[f16] }:$src0, i32:{ *:[i32] }:$src0_modifiers, i1:{ *:[i1] }:$clamp, i32:{ *:[i32] }:$omod))<<P:Predicate_anonymous_23778>>  =>  (COPY_TO_REGCLASS:{ *:[f16] } (V_S_EXP_F16_e64:{ *:[f32] } i32:{ *:[i32] }:$src0_modifiers, f16:{ *:[f16] }:$src0, i1:{ *:[i1] }:$clamp, i32:{ *:[i32] }:$omod), SReg_32_XEXEC:{ *:[i32] })
        GIR_MakeTempReg, /*TempRegID*/0, /*TypeID*/GILLT_s32,
        GIR_BuildMI, /*InsnID*/1, /*Opcode*/GIMT_Encode2(AMDGPU::V_S_EXP_F16_e64),
        GIR_AddTempRegister, /*InsnID*/1, /*TempRegID*/0, /*TempRegFlags*/GIMT_Encode2(RegState::Define),
        GIR_ComplexSubOperandRenderer, /*InsnID*/1, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/1, // src0_modifiers
        GIR_ComplexSubOperandRenderer, /*InsnID*/1, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/0, // src0
        GIR_ComplexSubOperandRenderer, /*InsnID*/1, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/2, // clamp
        GIR_ComplexSubOperandRenderer, /*InsnID*/1, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/3, // omod
        GIR_ConstrainSelectedInstOperands, /*InsnID*/1,
        GIR_BuildMI, /*InsnID*/0, /*Opcode*/GIMT_Encode2(TargetOpcode::COPY),
        GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/0, // DstI[dst]
        GIR_AddSimpleTempRegister, /*InsnID*/0, /*TempRegID*/0,
        GIR_ConstrainOperandRC, /*InsnID*/0, /*Op*/0, GIMT_Encode2(AMDGPU::SReg_32_XEXECRegClassID),
        GIR_EraseFromParent, /*InsnID*/0,
        // GIR_Coverage, 2227,
        GIR_Done,
      // Label 4110: @259671
      GIM_Try, /*On fail goto*//*Label 4111*/ GIMT_Encode4(259724), // Rule ID 682 //
        GIM_CheckFeatures, GIMT_Encode2(GIFBS_Has16BitInsts_NotHasTrue16BitInsts),
        GIM_CheckRegBankForClass, /*MI*/0, /*Op*/0, /*RC*/GIMT_Encode2(AMDGPU::VGPR_32RegClassID),
        GIM_CheckComplexPattern, /*MI*/0, /*Op*/1, /*Renderer*/GIMT_Encode2(0), GIMT_Encode2(GICP_gi_vop3mods0),
        // (fexp2:{ *:[f16] } (VOP3Mods0:{ *:[f16] } f16:{ *:[f16] }:$src0, i32:{ *:[i32] }:$src0_modifiers, i1:{ *:[i1] }:$clamp, i32:{ *:[i32] }:$omod))  =>  (V_EXP_F16_e64:{ *:[f16] } i32:{ *:[i32] }:$src0_modifiers, f16:{ *:[f16] }:$src0, i1:{ *:[i1] }:$clamp, i32:{ *:[i32] }:$omod)
        GIR_BuildMI, /*InsnID*/0, /*Opcode*/GIMT_Encode2(AMDGPU::V_EXP_F16_e64),
        GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/0, // DstI[vdst]
        GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/1, // src0_modifiers
        GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/0, // src0
        GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/2, // clamp
        GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/3, // omod
        GIR_ConstrainSelectedInstOperands, /*InsnID*/0,
        GIR_EraseFromParent, /*InsnID*/0,
        // GIR_Coverage, 682,
        GIR_Done,
      // Label 4111: @259724
      GIM_Try, /*On fail goto*//*Label 4112*/ GIMT_Encode4(259777), // Rule ID 684 //
        GIM_CheckFeatures, GIMT_Encode2(GIFBS_UseRealTrue16Insts),
        GIM_CheckRegBankForClass, /*MI*/0, /*Op*/0, /*RC*/GIMT_Encode2(AMDGPU::VGPR_16RegClassID),
        GIM_CheckComplexPattern, /*MI*/0, /*Op*/1, /*Renderer*/GIMT_Encode2(0), GIMT_Encode2(GICP_gi_vop3mods0),
        // (fexp2:{ *:[f16] } (VOP3Mods0:{ *:[f16] } f16:{ *:[f16] }:$src0, i32:{ *:[i32] }:$src0_modifiers, i1:{ *:[i1] }:$clamp, i32:{ *:[i32] }:$omod))  =>  (V_EXP_F16_t16_e64:{ *:[f16] } i32:{ *:[i32] }:$src0_modifiers, f16:{ *:[f16] }:$src0, i1:{ *:[i1] }:$clamp, i32:{ *:[i32] }:$omod)
        GIR_BuildMI, /*InsnID*/0, /*Opcode*/GIMT_Encode2(AMDGPU::V_EXP_F16_t16_e64),
        GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/0, // DstI[vdst]
        GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/1, // src0_modifiers
        GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/0, // src0
        GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/2, // clamp
        GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/3, // omod
        GIR_ConstrainSelectedInstOperands, /*InsnID*/0,
        GIR_EraseFromParent, /*InsnID*/0,
        // GIR_Coverage, 684,
        GIR_Done,
      // Label 4112: @259777
      GIM_Try, /*On fail goto*//*Label 4113*/ GIMT_Encode4(259830), // Rule ID 686 //
        GIM_CheckFeatures, GIMT_Encode2(GIFBS_UseFakeTrue16Insts),
        GIM_CheckRegBankForClass, /*MI*/0, /*Op*/0, /*RC*/GIMT_Encode2(AMDGPU::VGPR_32RegClassID),
        GIM_CheckComplexPattern, /*MI*/0, /*Op*/1, /*Renderer*/GIMT_Encode2(0), GIMT_Encode2(GICP_gi_vop3mods0),
        // (fexp2:{ *:[f16] } (VOP3Mods0:{ *:[f16] } f16:{ *:[f16] }:$src0, i32:{ *:[i32] }:$src0_modifiers, i1:{ *:[i1] }:$clamp, i32:{ *:[i32] }:$omod))  =>  (V_EXP_F16_fake16_e64:{ *:[f16] } i32:{ *:[i32] }:$src0_modifiers, f16:{ *:[f16] }:$src0, i1:{ *:[i1] }:$clamp, i32:{ *:[i32] }:$omod)
        GIR_BuildMI, /*InsnID*/0, /*Opcode*/GIMT_Encode2(AMDGPU::V_EXP_F16_fake16_e64),
        GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/0, // DstI[vdst]
        GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/1, // src0_modifiers
        GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/0, // src0
        GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/2, // clamp
        GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/3, // omod
        GIR_ConstrainSelectedInstOperands, /*InsnID*/0,
        GIR_EraseFromParent, /*InsnID*/0,
        // GIR_Coverage, 686,
        GIR_Done,
      // Label 4113: @259830
      GIM_Reject,
    // Label 4109: @259831
    GIM_Reject,
    // Label 63: @259832
    GIM_Try, /*On fail goto*//*Label 4114*/ GIMT_Encode4(260082),
      GIM_CheckType, /*MI*/0, /*Op*/0, /*Type*/GILLT_s16,
      GIM_CheckType, /*MI*/0, /*Op*/1, /*Type*/GILLT_s16,
      GIM_Try, /*On fail goto*//*Label 4115*/ GIMT_Encode4(259922), // Rule ID 2229 //
        GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasPseudoScalarTrans),
        GIM_CheckRegBankForClass, /*MI*/0, /*Op*/0, /*RC*/GIMT_Encode2(AMDGPU::SReg_32_XEXECRegClassID),
        GIM_CheckCxxInsnPredicate, /*MI*/0, /*FnId*/GIMT_Encode2(GICXXPred_MI_Predicate_anonymous_23780),
        GIM_CheckComplexPattern, /*MI*/0, /*Op*/1, /*Renderer*/GIMT_Encode2(0), GIMT_Encode2(GICP_gi_vop3mods0),
        // (flog2:{ *:[f16] } (VOP3Mods0:{ *:[f16] } f16:{ *:[f16] }:$src0, i32:{ *:[i32] }:$src0_modifiers, i1:{ *:[i1] }:$clamp, i32:{ *:[i32] }:$omod))<<P:Predicate_anonymous_23780>>  =>  (COPY_TO_REGCLASS:{ *:[f16] } (V_S_LOG_F16_e64:{ *:[f32] } i32:{ *:[i32] }:$src0_modifiers, f16:{ *:[f16] }:$src0, i1:{ *:[i1] }:$clamp, i32:{ *:[i32] }:$omod), SReg_32_XEXEC:{ *:[i32] })
        GIR_MakeTempReg, /*TempRegID*/0, /*TypeID*/GILLT_s32,
        GIR_BuildMI, /*InsnID*/1, /*Opcode*/GIMT_Encode2(AMDGPU::V_S_LOG_F16_e64),
        GIR_AddTempRegister, /*InsnID*/1, /*TempRegID*/0, /*TempRegFlags*/GIMT_Encode2(RegState::Define),
        GIR_ComplexSubOperandRenderer, /*InsnID*/1, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/1, // src0_modifiers
        GIR_ComplexSubOperandRenderer, /*InsnID*/1, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/0, // src0
        GIR_ComplexSubOperandRenderer, /*InsnID*/1, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/2, // clamp
        GIR_ComplexSubOperandRenderer, /*InsnID*/1, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/3, // omod
        GIR_ConstrainSelectedInstOperands, /*InsnID*/1,
        GIR_BuildMI, /*InsnID*/0, /*Opcode*/GIMT_Encode2(TargetOpcode::COPY),
        GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/0, // DstI[dst]
        GIR_AddSimpleTempRegister, /*InsnID*/0, /*TempRegID*/0,
        GIR_ConstrainOperandRC, /*InsnID*/0, /*Op*/0, GIMT_Encode2(AMDGPU::SReg_32_XEXECRegClassID),
        GIR_EraseFromParent, /*InsnID*/0,
        // GIR_Coverage, 2229,
        GIR_Done,
      // Label 4115: @259922
      GIM_Try, /*On fail goto*//*Label 4116*/ GIMT_Encode4(259975), // Rule ID 676 //
        GIM_CheckFeatures, GIMT_Encode2(GIFBS_Has16BitInsts_NotHasTrue16BitInsts),
        GIM_CheckRegBankForClass, /*MI*/0, /*Op*/0, /*RC*/GIMT_Encode2(AMDGPU::VGPR_32RegClassID),
        GIM_CheckComplexPattern, /*MI*/0, /*Op*/1, /*Renderer*/GIMT_Encode2(0), GIMT_Encode2(GICP_gi_vop3mods0),
        // (flog2:{ *:[f16] } (VOP3Mods0:{ *:[f16] } f16:{ *:[f16] }:$src0, i32:{ *:[i32] }:$src0_modifiers, i1:{ *:[i1] }:$clamp, i32:{ *:[i32] }:$omod))  =>  (V_LOG_F16_e64:{ *:[f16] } i32:{ *:[i32] }:$src0_modifiers, f16:{ *:[f16] }:$src0, i1:{ *:[i1] }:$clamp, i32:{ *:[i32] }:$omod)
        GIR_BuildMI, /*InsnID*/0, /*Opcode*/GIMT_Encode2(AMDGPU::V_LOG_F16_e64),
        GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/0, // DstI[vdst]
        GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/1, // src0_modifiers
        GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/0, // src0
        GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/2, // clamp
        GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/3, // omod
        GIR_ConstrainSelectedInstOperands, /*InsnID*/0,
        GIR_EraseFromParent, /*InsnID*/0,
        // GIR_Coverage, 676,
        GIR_Done,
      // Label 4116: @259975
      GIM_Try, /*On fail goto*//*Label 4117*/ GIMT_Encode4(260028), // Rule ID 678 //
        GIM_CheckFeatures, GIMT_Encode2(GIFBS_UseRealTrue16Insts),
        GIM_CheckRegBankForClass, /*MI*/0, /*Op*/0, /*RC*/GIMT_Encode2(AMDGPU::VGPR_16RegClassID),
        GIM_CheckComplexPattern, /*MI*/0, /*Op*/1, /*Renderer*/GIMT_Encode2(0), GIMT_Encode2(GICP_gi_vop3mods0),
        // (flog2:{ *:[f16] } (VOP3Mods0:{ *:[f16] } f16:{ *:[f16] }:$src0, i32:{ *:[i32] }:$src0_modifiers, i1:{ *:[i1] }:$clamp, i32:{ *:[i32] }:$omod))  =>  (V_LOG_F16_t16_e64:{ *:[f16] } i32:{ *:[i32] }:$src0_modifiers, f16:{ *:[f16] }:$src0, i1:{ *:[i1] }:$clamp, i32:{ *:[i32] }:$omod)
        GIR_BuildMI, /*InsnID*/0, /*Opcode*/GIMT_Encode2(AMDGPU::V_LOG_F16_t16_e64),
        GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/0, // DstI[vdst]
        GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/1, // src0_modifiers
        GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/0, // src0
        GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/2, // clamp
        GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/3, // omod
        GIR_ConstrainSelectedInstOperands, /*InsnID*/0,
        GIR_EraseFromParent, /*InsnID*/0,
        // GIR_Coverage, 678,
        GIR_Done,
      // Label 4117: @260028
      GIM_Try, /*On fail goto*//*Label 4118*/ GIMT_Encode4(260081), // Rule ID 680 //
        GIM_CheckFeatures, GIMT_Encode2(GIFBS_UseFakeTrue16Insts),
        GIM_CheckRegBankForClass, /*MI*/0, /*Op*/0, /*RC*/GIMT_Encode2(AMDGPU::VGPR_32RegClassID),
        GIM_CheckComplexPattern, /*MI*/0, /*Op*/1, /*Renderer*/GIMT_Encode2(0), GIMT_Encode2(GICP_gi_vop3mods0),
        // (flog2:{ *:[f16] } (VOP3Mods0:{ *:[f16] } f16:{ *:[f16] }:$src0, i32:{ *:[i32] }:$src0_modifiers, i1:{ *:[i1] }:$clamp, i32:{ *:[i32] }:$omod))  =>  (V_LOG_F16_fake16_e64:{ *:[f16] } i32:{ *:[i32] }:$src0_modifiers, f16:{ *:[f16] }:$src0, i1:{ *:[i1] }:$clamp, i32:{ *:[i32] }:$omod)
        GIR_BuildMI, /*InsnID*/0, /*Opcode*/GIMT_Encode2(AMDGPU::V_LOG_F16_fake16_e64),
        GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/0, // DstI[vdst]
        GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/1, // src0_modifiers
        GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/0, // src0
        GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/2, // clamp
        GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/3, // omod
        GIR_ConstrainSelectedInstOperands, /*InsnID*/0,
        GIR_EraseFromParent, /*InsnID*/0,
        // GIR_Coverage, 680,
        GIR_Done,
      // Label 4118: @260081
      GIM_Reject,
    // Label 4114: @260082
    GIM_Reject,
    // Label 64: @260083
    GIM_SwitchType, /*MI*/0, /*Op*/0, /*[*/GIMT_Encode2(8), GIMT_Encode2(11), /*)*//*default:*//*Label 4122*/ GIMT_Encode4(260408),
    /*GILLT_s16*//*Label 4119*/ GIMT_Encode4(260106),
    /*GILLT_s32*//*Label 4120*/ GIMT_Encode4(260256),
    /*GILLT_s64*//*Label 4121*/ GIMT_Encode4(260332),
    // Label 4119: @260106
    GIM_Try, /*On fail goto*//*Label 4123*/ GIMT_Encode4(260255),
      GIM_CheckType, /*MI*/0, /*Op*/1, /*Type*/GILLT_s16,
      GIM_CheckType, /*MI*/0, /*Op*/2, /*Type*/GILLT_s16,
      GIM_CheckRegBankForClass, /*MI*/0, /*Op*/0, /*RC*/GIMT_Encode2(AMDGPU::VGPR_32RegClassID),
      GIM_Try, /*On fail goto*//*Label 4124*/ GIMT_Encode4(260189), // Rule ID 2112 //
        GIM_CheckFeatures, GIMT_Encode2(GIFBS_NotHasTrue16BitInsts),
        GIM_CheckComplexPattern, /*MI*/0, /*Op*/1, /*Renderer*/GIMT_Encode2(0), GIMT_Encode2(GICP_gi_vop3mods0),
        GIM_CheckComplexPattern, /*MI*/0, /*Op*/2, /*Renderer*/GIMT_Encode2(1), GIMT_Encode2(GICP_gi_vop3mods0),
        // (fldexp:{ *:[f16] } (VOP3Mods0:{ *:[f16] } f16:{ *:[f16] }:$src0, i32:{ *:[i32] }:$src0_modifiers, i1:{ *:[i1] }:$clamp, i32:{ *:[i32] }:$omod), (VOP3Mods0:{ *:[i16] } f16:{ *:[f16] }:$src1, i32:{ *:[i32] }:$src1_modifiers))  =>  (V_LDEXP_F16_e64:{ *:[f16] } ?:{ *:[i32] }:$src0_modifiers, ?:{ *:[f16] }:$src0, ?:{ *:[i32] }:$src1_modifiers, ?:{ *:[f16] }:$src1, ?:{ *:[i1] }:$clamp, ?:{ *:[i32] }:$omod)
        GIR_BuildMI, /*InsnID*/0, /*Opcode*/GIMT_Encode2(AMDGPU::V_LDEXP_F16_e64),
        GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/0, // DstI[vdst]
        GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/1, // src0_modifiers
        GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/0, // src0
        GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(1), /*SubOperand*/1, // src1_modifiers
        GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(1), /*SubOperand*/0, // src1
        GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/2, // clamp
        GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/3, // omod
        GIR_ConstrainSelectedInstOperands, /*InsnID*/0,
        GIR_EraseFromParent, /*InsnID*/0,
        // GIR_Coverage, 2112,
        GIR_Done,
      // Label 4124: @260189
      GIM_Try, /*On fail goto*//*Label 4125*/ GIMT_Encode4(260254), // Rule ID 2114 //
        GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasTrue16BitInsts),
        GIM_CheckComplexPattern, /*MI*/0, /*Op*/1, /*Renderer*/GIMT_Encode2(0), GIMT_Encode2(GICP_gi_vop3mods0),
        GIM_CheckComplexPattern, /*MI*/0, /*Op*/2, /*Renderer*/GIMT_Encode2(1), GIMT_Encode2(GICP_gi_vop3mods0),
        // (fldexp:{ *:[f16] } (VOP3Mods0:{ *:[f16] } f16:{ *:[f16] }:$src0, i32:{ *:[i32] }:$src0_modifiers, i1:{ *:[i1] }:$clamp, i32:{ *:[i32] }:$omod), (VOP3Mods0:{ *:[i16] } f16:{ *:[f16] }:$src1, i32:{ *:[i32] }:$src1_modifiers))  =>  (V_LDEXP_F16_t16_e64:{ *:[f16] } ?:{ *:[i32] }:$src0_modifiers, ?:{ *:[f16] }:$src0, ?:{ *:[i32] }:$src1_modifiers, ?:{ *:[f16] }:$src1, ?:{ *:[i1] }:$clamp, ?:{ *:[i32] }:$omod)
        GIR_BuildMI, /*InsnID*/0, /*Opcode*/GIMT_Encode2(AMDGPU::V_LDEXP_F16_t16_e64),
        GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/0, // DstI[vdst]
        GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/1, // src0_modifiers
        GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/0, // src0
        GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(1), /*SubOperand*/1, // src1_modifiers
        GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(1), /*SubOperand*/0, // src1
        GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/2, // clamp
        GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/3, // omod
        GIR_ConstrainSelectedInstOperands, /*InsnID*/0,
        GIR_EraseFromParent, /*InsnID*/0,
        // GIR_Coverage, 2114,
        GIR_Done,
      // Label 4125: @260254
      GIM_Reject,
    // Label 4123: @260255
    GIM_Reject,
    // Label 4120: @260256
    GIM_Try, /*On fail goto*//*Label 4126*/ GIMT_Encode4(260331), // Rule ID 762 //
      GIM_CheckType, /*MI*/0, /*Op*/1, /*Type*/GILLT_s32,
      GIM_CheckType, /*MI*/0, /*Op*/2, /*Type*/GILLT_s32,
      GIM_CheckRegBankForClass, /*MI*/0, /*Op*/0, /*RC*/GIMT_Encode2(AMDGPU::VGPR_32RegClassID),
      GIM_CheckComplexPattern, /*MI*/0, /*Op*/1, /*Renderer*/GIMT_Encode2(0), GIMT_Encode2(GICP_gi_vop3mods0),
      GIM_CheckComplexPattern, /*MI*/0, /*Op*/2, /*Renderer*/GIMT_Encode2(1), GIMT_Encode2(GICP_gi_vop3mods),
      // (fldexp:{ *:[f32] } (VOP3Mods0:{ *:[f32] } f32:{ *:[f32] }:$src0, i32:{ *:[i32] }:$src0_modifiers, i1:{ *:[i1] }:$clamp, i32:{ *:[i32] }:$omod), (VOP3Mods:{ *:[i32] } i32:{ *:[i32] }:$src1, i32:{ *:[i32] }:$src1_modifiers))  =>  (V_LDEXP_F32_e64:{ *:[f32] } i32:{ *:[i32] }:$src0_modifiers, f32:{ *:[f32] }:$src0, i32:{ *:[i32] }:$src1_modifiers, i32:{ *:[i32] }:$src1, i1:{ *:[i1] }:$clamp, i32:{ *:[i32] }:$omod)
      GIR_BuildMI, /*InsnID*/0, /*Opcode*/GIMT_Encode2(AMDGPU::V_LDEXP_F32_e64),
      GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/0, // DstI[vdst]
      GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/1, // src0_modifiers
      GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/0, // src0
      GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(1), /*SubOperand*/1, // src1_modifiers
      GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(1), /*SubOperand*/0, // src1
      GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/2, // clamp
      GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/3, // omod
      GIR_ConstrainSelectedInstOperands, /*InsnID*/0,
      GIR_EraseFromParent, /*InsnID*/0,
      // GIR_Coverage, 762,
      GIR_Done,
    // Label 4126: @260331
    GIM_Reject,
    // Label 4121: @260332
    GIM_Try, /*On fail goto*//*Label 4127*/ GIMT_Encode4(260407), // Rule ID 903 //
      GIM_CheckType, /*MI*/0, /*Op*/1, /*Type*/GILLT_s64,
      GIM_CheckType, /*MI*/0, /*Op*/2, /*Type*/GILLT_s32,
      GIM_CheckRegBankForClass, /*MI*/0, /*Op*/0, /*RC*/GIMT_Encode2(AMDGPU::VReg_64RegClassID),
      GIM_CheckComplexPattern, /*MI*/0, /*Op*/1, /*Renderer*/GIMT_Encode2(0), GIMT_Encode2(GICP_gi_vop3mods0),
      GIM_CheckComplexPattern, /*MI*/0, /*Op*/2, /*Renderer*/GIMT_Encode2(1), GIMT_Encode2(GICP_gi_vop3mods),
      // (fldexp:{ *:[f64] } (VOP3Mods0:{ *:[f64] } f64:{ *:[f64] }:$src0, i32:{ *:[i32] }:$src0_modifiers, i1:{ *:[i1] }:$clamp, i32:{ *:[i32] }:$omod), (VOP3Mods:{ *:[i32] } i32:{ *:[i32] }:$src1, i32:{ *:[i32] }:$src1_modifiers))  =>  (V_LDEXP_F64_e64:{ *:[f64] } i32:{ *:[i32] }:$src0_modifiers, f64:{ *:[f64] }:$src0, i32:{ *:[i32] }:$src1_modifiers, i32:{ *:[i32] }:$src1, i1:{ *:[i1] }:$clamp, i32:{ *:[i32] }:$omod)
      GIR_BuildMI, /*InsnID*/0, /*Opcode*/GIMT_Encode2(AMDGPU::V_LDEXP_F64_e64),
      GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/0, // DstI[vdst]
      GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/1, // src0_modifiers
      GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/0, // src0
      GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(1), /*SubOperand*/1, // src1_modifiers
      GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(1), /*SubOperand*/0, // src1
      GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/2, // clamp
      GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/3, // omod
      GIR_ConstrainSelectedInstOperands, /*InsnID*/0,
      GIR_EraseFromParent, /*InsnID*/0,
      // GIR_Coverage, 903,
      GIR_Done,
    // Label 4127: @260407
    GIM_Reject,
    // Label 4122: @260408
    GIM_Reject,
    // Label 65: @260409
    GIM_SwitchType, /*MI*/0, /*Op*/0, /*[*/GIMT_Encode2(8), GIMT_Encode2(13), /*)*//*default:*//*Label 4133*/ GIMT_Encode4(261814),
    /*GILLT_s16*//*Label 4128*/ GIMT_Encode4(260440),
    /*GILLT_s32*//*Label 4129*/ GIMT_Encode4(260729),
    /*GILLT_s64*//*Label 4130*/ GIMT_Encode4(261018),
    /*GILLT_v2s16*//*Label 4131*/ GIMT_Encode4(261344),
    /*GILLT_v2s32*//*Label 4132*/ GIMT_Encode4(261746),
    // Label 4128: @260440
    GIM_Try, /*On fail goto*//*Label 4134*/ GIMT_Encode4(260728),
      GIM_CheckType, /*MI*/0, /*Op*/1, /*Type*/GILLT_s16,
      GIM_Try, /*On fail goto*//*Label 4135*/ GIMT_Encode4(260529), // Rule ID 6210 //
        GIM_CheckRegBankForClass, /*MI*/0, /*Op*/0, /*RC*/GIMT_Encode2(AMDGPU::SReg_32RegClassID),
        GIM_RecordInsn, /*DefineMI*/1, /*MI*/0, /*OpIdx*/1, // MIs[1]
        GIM_CheckOpcode, /*MI*/1, GIMT_Encode2(TargetOpcode::G_FABS),
        GIM_CheckType, /*MI*/1, /*Op*/1, /*Type*/GILLT_s16,
        GIM_CheckRegBankForClass, /*MI*/1, /*Op*/1, /*RC*/GIMT_Encode2(AMDGPU::SReg_32RegClassID),
        GIM_CheckCxxInsnPredicate, /*MI*/0, /*FnId*/GIMT_Encode2(GICXXPred_MI_Predicate_anonymous_34988),
        GIM_CheckIsSafeToFold, /*InsnID*/1,
        // (fneg:{ *:[f16] } (fabs:{ *:[f16] } SReg_32:{ *:[f16] }:$src))<<P:Predicate_anonymous_34988>>  =>  (S_OR_B32:{ *:[f16] }:{ *:[i1] } SReg_32:{ *:[f16] }:$src, (S_MOV_B32:{ *:[i1] } 32768:{ *:[i32] }))
        GIR_MakeTempReg, /*TempRegID*/0, /*TypeID*/GILLT_s1,
        GIR_BuildMI, /*InsnID*/1, /*Opcode*/GIMT_Encode2(AMDGPU::S_MOV_B32),
        GIR_AddTempRegister, /*InsnID*/1, /*TempRegID*/0, /*TempRegFlags*/GIMT_Encode2(RegState::Define),
        GIR_AddImm, /*InsnID*/1, /*Imm*/GIMT_Encode8(32768),
        GIR_ConstrainSelectedInstOperands, /*InsnID*/1,
        GIR_BuildMI, /*InsnID*/0, /*Opcode*/GIMT_Encode2(AMDGPU::S_OR_B32),
        GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/0, // DstI[sdst]
        GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/1, /*OpIdx*/1, // src
        GIR_AddSimpleTempRegister, /*InsnID*/0, /*TempRegID*/0,
        GIR_SetImplicitDefDead, /*InsnID*/0, /*OpIdx for AMDGPU::SCC*/0,
        GIR_ConstrainSelectedInstOperands, /*InsnID*/0,
        GIR_EraseFromParent, /*InsnID*/0,
        // GIR_Coverage, 6210,
        GIR_Done,
      // Label 4135: @260529
      GIM_Try, /*On fail goto*//*Label 4136*/ GIMT_Encode4(260602), // Rule ID 6226 //
        GIM_CheckRegBankForClass, /*MI*/0, /*Op*/0, /*RC*/GIMT_Encode2(AMDGPU::VGPR_32RegClassID),
        GIM_RecordInsn, /*DefineMI*/1, /*MI*/0, /*OpIdx*/1, // MIs[1]
        GIM_CheckOpcode, /*MI*/1, GIMT_Encode2(TargetOpcode::G_FABS),
        GIM_CheckType, /*MI*/1, /*Op*/1, /*Type*/GILLT_s16,
        GIM_CheckRegBankForClass, /*MI*/1, /*Op*/1, /*RC*/GIMT_Encode2(AMDGPU::VGPR_32RegClassID),
        GIM_CheckIsSafeToFold, /*InsnID*/1,
        // (fneg:{ *:[f16] } (fabs:{ *:[f16] } VGPR_32:{ *:[f16] }:$src))  =>  (V_OR_B32_e64:{ *:[f16] } (S_MOV_B32:{ *:[i16] } 32768:{ *:[i32] }), VGPR_32:{ *:[f16] }:$src)
        GIR_MakeTempReg, /*TempRegID*/0, /*TypeID*/GILLT_s16,
        GIR_BuildMI, /*InsnID*/1, /*Opcode*/GIMT_Encode2(AMDGPU::S_MOV_B32),
        GIR_AddTempRegister, /*InsnID*/1, /*TempRegID*/0, /*TempRegFlags*/GIMT_Encode2(RegState::Define),
        GIR_AddImm, /*InsnID*/1, /*Imm*/GIMT_Encode8(32768),
        GIR_ConstrainSelectedInstOperands, /*InsnID*/1,
        GIR_BuildMI, /*InsnID*/0, /*Opcode*/GIMT_Encode2(AMDGPU::V_OR_B32_e64),
        GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/0, // DstI[vdst]
        GIR_AddSimpleTempRegister, /*InsnID*/0, /*TempRegID*/0,
        GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/1, /*OpIdx*/1, // src
        GIR_ConstrainSelectedInstOperands, /*InsnID*/0,
        GIR_EraseFromParent, /*InsnID*/0,
        // GIR_Coverage, 6226,
        GIR_Done,
      // Label 4136: @260602
      GIM_Try, /*On fail goto*//*Label 4137*/ GIMT_Encode4(260668), // Rule ID 6208 //
        GIM_CheckRegBankForClass, /*MI*/0, /*Op*/0, /*RC*/GIMT_Encode2(AMDGPU::SReg_32RegClassID),
        GIM_CheckRegBankForClass, /*MI*/0, /*Op*/1, /*RC*/GIMT_Encode2(AMDGPU::SReg_32RegClassID),
        GIM_CheckCxxInsnPredicate, /*MI*/0, /*FnId*/GIMT_Encode2(GICXXPred_MI_Predicate_anonymous_34988),
        // (fneg:{ *:[f16] } SReg_32:{ *:[f16] }:$src)<<P:Predicate_anonymous_34988>>  =>  (S_XOR_B32:{ *:[f16] }:{ *:[i1] } SReg_32:{ *:[f16] }:$src, (S_MOV_B32:{ *:[i1] } 32768:{ *:[i32] }))
        GIR_MakeTempReg, /*TempRegID*/0, /*TypeID*/GILLT_s1,
        GIR_BuildMI, /*InsnID*/1, /*Opcode*/GIMT_Encode2(AMDGPU::S_MOV_B32),
        GIR_AddTempRegister, /*InsnID*/1, /*TempRegID*/0, /*TempRegFlags*/GIMT_Encode2(RegState::Define),
        GIR_AddImm, /*InsnID*/1, /*Imm*/GIMT_Encode8(32768),
        GIR_ConstrainSelectedInstOperands, /*InsnID*/1,
        GIR_BuildMI, /*InsnID*/0, /*Opcode*/GIMT_Encode2(AMDGPU::S_XOR_B32),
        GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/0, // DstI[sdst]
        GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/1, // src
        GIR_AddSimpleTempRegister, /*InsnID*/0, /*TempRegID*/0,
        GIR_SetImplicitDefDead, /*InsnID*/0, /*OpIdx for AMDGPU::SCC*/0,
        GIR_ConstrainSelectedInstOperands, /*InsnID*/0,
        GIR_EraseFromParent, /*InsnID*/0,
        // GIR_Coverage, 6208,
        GIR_Done,
      // Label 4137: @260668
      GIM_Try, /*On fail goto*//*Label 4138*/ GIMT_Encode4(260727), // Rule ID 6225 //
        GIM_CheckRegBankForClass, /*MI*/0, /*Op*/0, /*RC*/GIMT_Encode2(AMDGPU::VGPR_32RegClassID),
        GIM_CheckRegBankForClass, /*MI*/0, /*Op*/1, /*RC*/GIMT_Encode2(AMDGPU::VGPR_32RegClassID),
        // (fneg:{ *:[f16] } VGPR_32:{ *:[f16] }:$src)  =>  (V_XOR_B32_e64:{ *:[f16] } (S_MOV_B32:{ *:[i16] } 32768:{ *:[i32] }), VGPR_32:{ *:[f16] }:$src)
        GIR_MakeTempReg, /*TempRegID*/0, /*TypeID*/GILLT_s16,
        GIR_BuildMI, /*InsnID*/1, /*Opcode*/GIMT_Encode2(AMDGPU::S_MOV_B32),
        GIR_AddTempRegister, /*InsnID*/1, /*TempRegID*/0, /*TempRegFlags*/GIMT_Encode2(RegState::Define),
        GIR_AddImm, /*InsnID*/1, /*Imm*/GIMT_Encode8(32768),
        GIR_ConstrainSelectedInstOperands, /*InsnID*/1,
        GIR_BuildMI, /*InsnID*/0, /*Opcode*/GIMT_Encode2(AMDGPU::V_XOR_B32_e64),
        GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/0, // DstI[vdst]
        GIR_AddSimpleTempRegister, /*InsnID*/0, /*TempRegID*/0,
        GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/1, // src
        GIR_ConstrainSelectedInstOperands, /*InsnID*/0,
        GIR_EraseFromParent, /*InsnID*/0,
        // GIR_Coverage, 6225,
        GIR_Done,
      // Label 4138: @260727
      GIM_Reject,
    // Label 4134: @260728
    GIM_Reject,
    // Label 4129: @260729
    GIM_Try, /*On fail goto*//*Label 4139*/ GIMT_Encode4(261017),
      GIM_CheckType, /*MI*/0, /*Op*/1, /*Type*/GILLT_s32,
      GIM_Try, /*On fail goto*//*Label 4140*/ GIMT_Encode4(260818), // Rule ID 6205 //
        GIM_CheckRegBankForClass, /*MI*/0, /*Op*/0, /*RC*/GIMT_Encode2(AMDGPU::SReg_32RegClassID),
        GIM_RecordInsn, /*DefineMI*/1, /*MI*/0, /*OpIdx*/1, // MIs[1]
        GIM_CheckOpcode, /*MI*/1, GIMT_Encode2(TargetOpcode::G_FABS),
        GIM_CheckType, /*MI*/1, /*Op*/1, /*Type*/GILLT_s32,
        GIM_CheckRegBankForClass, /*MI*/1, /*Op*/1, /*RC*/GIMT_Encode2(AMDGPU::SReg_32RegClassID),
        GIM_CheckCxxInsnPredicate, /*MI*/0, /*FnId*/GIMT_Encode2(GICXXPred_MI_Predicate_anonymous_34988),
        GIM_CheckIsSafeToFold, /*InsnID*/1,
        // (fneg:{ *:[f32] } (fabs:{ *:[f32] } SReg_32:{ *:[f32] }:$src))<<P:Predicate_anonymous_34988>>  =>  (S_OR_B32:{ *:[f32] }:{ *:[i1] } SReg_32:{ *:[f32] }:$src, (S_MOV_B32:{ *:[i1] } 2147483648:{ *:[i32] }))
        GIR_MakeTempReg, /*TempRegID*/0, /*TypeID*/GILLT_s1,
        GIR_BuildMI, /*InsnID*/1, /*Opcode*/GIMT_Encode2(AMDGPU::S_MOV_B32),
        GIR_AddTempRegister, /*InsnID*/1, /*TempRegID*/0, /*TempRegFlags*/GIMT_Encode2(RegState::Define),
        GIR_AddImm, /*InsnID*/1, /*Imm*/GIMT_Encode8(2147483648),
        GIR_ConstrainSelectedInstOperands, /*InsnID*/1,
        GIR_BuildMI, /*InsnID*/0, /*Opcode*/GIMT_Encode2(AMDGPU::S_OR_B32),
        GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/0, // DstI[sdst]
        GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/1, /*OpIdx*/1, // src
        GIR_AddSimpleTempRegister, /*InsnID*/0, /*TempRegID*/0,
        GIR_SetImplicitDefDead, /*InsnID*/0, /*OpIdx for AMDGPU::SCC*/0,
        GIR_ConstrainSelectedInstOperands, /*InsnID*/0,
        GIR_EraseFromParent, /*InsnID*/0,
        // GIR_Coverage, 6205,
        GIR_Done,
      // Label 4140: @260818
      GIM_Try, /*On fail goto*//*Label 4141*/ GIMT_Encode4(260891), // Rule ID 6221 //
        GIM_CheckRegBankForClass, /*MI*/0, /*Op*/0, /*RC*/GIMT_Encode2(AMDGPU::VGPR_32RegClassID),
        GIM_RecordInsn, /*DefineMI*/1, /*MI*/0, /*OpIdx*/1, // MIs[1]
        GIM_CheckOpcode, /*MI*/1, GIMT_Encode2(TargetOpcode::G_FABS),
        GIM_CheckType, /*MI*/1, /*Op*/1, /*Type*/GILLT_s32,
        GIM_CheckRegBankForClass, /*MI*/1, /*Op*/1, /*RC*/GIMT_Encode2(AMDGPU::VGPR_32RegClassID),
        GIM_CheckIsSafeToFold, /*InsnID*/1,
        // (fneg:{ *:[f32] } (fabs:{ *:[f32] } VGPR_32:{ *:[f32] }:$src))  =>  (V_OR_B32_e64:{ *:[f32] } (S_MOV_B32:{ *:[i16] } 2147483648:{ *:[i32] }), VGPR_32:{ *:[f32] }:$src)
        GIR_MakeTempReg, /*TempRegID*/0, /*TypeID*/GILLT_s16,
        GIR_BuildMI, /*InsnID*/1, /*Opcode*/GIMT_Encode2(AMDGPU::S_MOV_B32),
        GIR_AddTempRegister, /*InsnID*/1, /*TempRegID*/0, /*TempRegFlags*/GIMT_Encode2(RegState::Define),
        GIR_AddImm, /*InsnID*/1, /*Imm*/GIMT_Encode8(2147483648),
        GIR_ConstrainSelectedInstOperands, /*InsnID*/1,
        GIR_BuildMI, /*InsnID*/0, /*Opcode*/GIMT_Encode2(AMDGPU::V_OR_B32_e64),
        GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/0, // DstI[vdst]
        GIR_AddSimpleTempRegister, /*InsnID*/0, /*TempRegID*/0,
        GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/1, /*OpIdx*/1, // src
        GIR_ConstrainSelectedInstOperands, /*InsnID*/0,
        GIR_EraseFromParent, /*InsnID*/0,
        // GIR_Coverage, 6221,
        GIR_Done,
      // Label 4141: @260891
      GIM_Try, /*On fail goto*//*Label 4142*/ GIMT_Encode4(260957), // Rule ID 6207 //
        GIM_CheckRegBankForClass, /*MI*/0, /*Op*/0, /*RC*/GIMT_Encode2(AMDGPU::SReg_32RegClassID),
        GIM_CheckRegBankForClass, /*MI*/0, /*Op*/1, /*RC*/GIMT_Encode2(AMDGPU::SReg_32RegClassID),
        GIM_CheckCxxInsnPredicate, /*MI*/0, /*FnId*/GIMT_Encode2(GICXXPred_MI_Predicate_anonymous_34988),
        // (fneg:{ *:[f32] } SReg_32:{ *:[f32] }:$src)<<P:Predicate_anonymous_34988>>  =>  (S_XOR_B32:{ *:[f32] }:{ *:[i1] } SReg_32:{ *:[f32] }:$src, (S_MOV_B32:{ *:[i1] } 2147483648:{ *:[i32] }))
        GIR_MakeTempReg, /*TempRegID*/0, /*TypeID*/GILLT_s1,
        GIR_BuildMI, /*InsnID*/1, /*Opcode*/GIMT_Encode2(AMDGPU::S_MOV_B32),
        GIR_AddTempRegister, /*InsnID*/1, /*TempRegID*/0, /*TempRegFlags*/GIMT_Encode2(RegState::Define),
        GIR_AddImm, /*InsnID*/1, /*Imm*/GIMT_Encode8(2147483648),
        GIR_ConstrainSelectedInstOperands, /*InsnID*/1,
        GIR_BuildMI, /*InsnID*/0, /*Opcode*/GIMT_Encode2(AMDGPU::S_XOR_B32),
        GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/0, // DstI[sdst]
        GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/1, // src
        GIR_AddSimpleTempRegister, /*InsnID*/0, /*TempRegID*/0,
        GIR_SetImplicitDefDead, /*InsnID*/0, /*OpIdx for AMDGPU::SCC*/0,
        GIR_ConstrainSelectedInstOperands, /*InsnID*/0,
        GIR_EraseFromParent, /*InsnID*/0,
        // GIR_Coverage, 6207,
        GIR_Done,
      // Label 4142: @260957
      GIM_Try, /*On fail goto*//*Label 4143*/ GIMT_Encode4(261016), // Rule ID 6223 //
        GIM_CheckRegBankForClass, /*MI*/0, /*Op*/0, /*RC*/GIMT_Encode2(AMDGPU::VGPR_32RegClassID),
        GIM_CheckRegBankForClass, /*MI*/0, /*Op*/1, /*RC*/GIMT_Encode2(AMDGPU::VGPR_32RegClassID),
        // (fneg:{ *:[f32] } VGPR_32:{ *:[f32] }:$src)  =>  (V_XOR_B32_e64:{ *:[f32] } (S_MOV_B32:{ *:[i16] } 2147483648:{ *:[i32] }), VGPR_32:{ *:[f32] }:$src)
        GIR_MakeTempReg, /*TempRegID*/0, /*TypeID*/GILLT_s16,
        GIR_BuildMI, /*InsnID*/1, /*Opcode*/GIMT_Encode2(AMDGPU::S_MOV_B32),
        GIR_AddTempRegister, /*InsnID*/1, /*TempRegID*/0, /*TempRegFlags*/GIMT_Encode2(RegState::Define),
        GIR_AddImm, /*InsnID*/1, /*Imm*/GIMT_Encode8(2147483648),
        GIR_ConstrainSelectedInstOperands, /*InsnID*/1,
        GIR_BuildMI, /*InsnID*/0, /*Opcode*/GIMT_Encode2(AMDGPU::V_XOR_B32_e64),
        GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/0, // DstI[vdst]
        GIR_AddSimpleTempRegister, /*InsnID*/0, /*TempRegID*/0,
        GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/1, // src
        GIR_ConstrainSelectedInstOperands, /*InsnID*/0,
        GIR_EraseFromParent, /*InsnID*/0,
        // GIR_Coverage, 6223,
        GIR_Done,
      // Label 4143: @261016
      GIM_Reject,
    // Label 4139: @261017
    GIM_Reject,
    // Label 4130: @261018
    GIM_Try, /*On fail goto*//*Label 4144*/ GIMT_Encode4(261343),
      GIM_CheckType, /*MI*/0, /*Op*/1, /*Type*/GILLT_s64,
      GIM_CheckRegBankForClass, /*MI*/0, /*Op*/0, /*RC*/GIMT_Encode2(AMDGPU::VReg_64RegClassID),
      GIM_Try, /*On fail goto*//*Label 4145*/ GIMT_Encode4(261194), // Rule ID 6232 //
        GIM_RecordInsn, /*DefineMI*/1, /*MI*/0, /*OpIdx*/1, // MIs[1]
        GIM_CheckOpcode, /*MI*/1, GIMT_Encode2(TargetOpcode::G_FABS),
        GIM_CheckType, /*MI*/1, /*Op*/1, /*Type*/GILLT_s64,
        GIM_CheckRegBankForClass, /*MI*/1, /*Op*/1, /*RC*/GIMT_Encode2(AMDGPU::VReg_64RegClassID),
        GIM_CheckIsSafeToFold, /*InsnID*/1,
        // (fneg:{ *:[f64] } (fabs:{ *:[f64] } VReg_64:{ *:[f64] }:$src))  =>  (REG_SEQUENCE:{ *:[f64] } VReg_64:{ *:[i32] }, (EXTRACT_SUBREG:{ *:[i32] } VReg_64:{ *:[f64] }:$src, sub0:{ *:[i32] }), sub0:{ *:[i32] }, (V_OR_B32_e64:{ *:[i16] } (S_MOV_B32:{ *:[i32] } 2147483648:{ *:[i32] }), (EXTRACT_SUBREG:{ *:[i32] } VReg_64:{ *:[f64] }:$src, sub1:{ *:[i32] })), sub1:{ *:[i32] })
        GIR_MakeTempReg, /*TempRegID*/0, /*TypeID*/GILLT_s32,
        GIR_MakeTempReg, /*TempRegID*/1, /*TypeID*/GILLT_s16,
        GIR_MakeTempReg, /*TempRegID*/2, /*TypeID*/GILLT_s32,
        GIR_MakeTempReg, /*TempRegID*/3, /*TypeID*/GILLT_s32,
        GIR_BuildMI, /*InsnID*/4, /*Opcode*/GIMT_Encode2(TargetOpcode::COPY),
        GIR_AddTempRegister, /*InsnID*/4, /*TempRegID*/3, /*TempRegFlags*/GIMT_Encode2(RegState::Define),
        GIR_CopySubReg, /*NewInsnID*/4, /*OldInsnID*/1, /*OpIdx*/1, /*SubRegIdx*/GIMT_Encode2(11), // src
        GIR_ConstrainOperandRC, /*InsnID*/4, /*Op*/0, GIMT_Encode2(AMDGPU::VGPR_32RegClassID),
        GIR_ConstrainOperandRC, /*InsnID*/4, /*Op*/1, GIMT_Encode2(AMDGPU::VReg_64RegClassID),
        GIR_BuildMI, /*InsnID*/3, /*Opcode*/GIMT_Encode2(AMDGPU::S_MOV_B32),
        GIR_AddTempRegister, /*InsnID*/3, /*TempRegID*/2, /*TempRegFlags*/GIMT_Encode2(RegState::Define),
        GIR_AddImm, /*InsnID*/3, /*Imm*/GIMT_Encode8(2147483648),
        GIR_ConstrainSelectedInstOperands, /*InsnID*/3,
        GIR_BuildMI, /*InsnID*/2, /*Opcode*/GIMT_Encode2(AMDGPU::V_OR_B32_e64),
        GIR_AddTempRegister, /*InsnID*/2, /*TempRegID*/1, /*TempRegFlags*/GIMT_Encode2(RegState::Define),
        GIR_AddSimpleTempRegister, /*InsnID*/2, /*TempRegID*/2,
        GIR_AddSimpleTempRegister, /*InsnID*/2, /*TempRegID*/3,
        GIR_ConstrainSelectedInstOperands, /*InsnID*/2,
        GIR_BuildMI, /*InsnID*/1, /*Opcode*/GIMT_Encode2(TargetOpcode::COPY),
        GIR_AddTempRegister, /*InsnID*/1, /*TempRegID*/0, /*TempRegFlags*/GIMT_Encode2(RegState::Define),
        GIR_CopySubReg, /*NewInsnID*/1, /*OldInsnID*/1, /*OpIdx*/1, /*SubRegIdx*/GIMT_Encode2(3), // src
        GIR_ConstrainOperandRC, /*InsnID*/1, /*Op*/0, GIMT_Encode2(AMDGPU::VGPR_32RegClassID),
        GIR_ConstrainOperandRC, /*InsnID*/1, /*Op*/1, GIMT_Encode2(AMDGPU::VReg_64RegClassID),
        GIR_BuildMI, /*InsnID*/0, /*Opcode*/GIMT_Encode2(TargetOpcode::REG_SEQUENCE),
        GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/0, // DstI[dst]
        GIR_AddSimpleTempRegister, /*InsnID*/0, /*TempRegID*/0,
        GIR_AddImm8, /*InsnID*/0, /*SubRegIndex*/3,
        GIR_AddSimpleTempRegister, /*InsnID*/0, /*TempRegID*/1,
        GIR_AddImm8, /*InsnID*/0, /*SubRegIndex*/11,
        GIR_ConstrainOperandRC, /*InsnID*/0, /*Op*/0, GIMT_Encode2(AMDGPU::VReg_64RegClassID),
        GIR_ConstrainOperandRC, /*InsnID*/0, /*Op*/1, GIMT_Encode2(AMDGPU::VGPR_32RegClassID),
        GIR_ConstrainOperandRC, /*InsnID*/0, /*Op*/3, GIMT_Encode2(AMDGPU::VGPR_32RegClassID),
        GIR_EraseFromParent, /*InsnID*/0,
        // GIR_Coverage, 6232,
        GIR_Done,
      // Label 4145: @261194
      GIM_Try, /*On fail goto*//*Label 4146*/ GIMT_Encode4(261342), // Rule ID 6231 //
        GIM_CheckRegBankForClass, /*MI*/0, /*Op*/1, /*RC*/GIMT_Encode2(AMDGPU::VReg_64RegClassID),
        // (fneg:{ *:[f64] } VReg_64:{ *:[f64] }:$src)  =>  (REG_SEQUENCE:{ *:[f64] } VReg_64:{ *:[i32] }, (EXTRACT_SUBREG:{ *:[i32] } VReg_64:{ *:[f64] }:$src, sub0:{ *:[i32] }), sub0:{ *:[i32] }, (V_XOR_B32_e64:{ *:[i16] } (S_MOV_B32:{ *:[i32] } 2147483648:{ *:[i32] }), (EXTRACT_SUBREG:{ *:[i32] } VReg_64:{ *:[f64] }:$src, sub1:{ *:[i32] })), sub1:{ *:[i32] })
        GIR_MakeTempReg, /*TempRegID*/0, /*TypeID*/GILLT_s32,
        GIR_MakeTempReg, /*TempRegID*/1, /*TypeID*/GILLT_s16,
        GIR_MakeTempReg, /*TempRegID*/2, /*TypeID*/GILLT_s32,
        GIR_MakeTempReg, /*TempRegID*/3, /*TypeID*/GILLT_s32,
        GIR_BuildMI, /*InsnID*/4, /*Opcode*/GIMT_Encode2(TargetOpcode::COPY),
        GIR_AddTempRegister, /*InsnID*/4, /*TempRegID*/3, /*TempRegFlags*/GIMT_Encode2(RegState::Define),
        GIR_CopySubReg, /*NewInsnID*/4, /*OldInsnID*/0, /*OpIdx*/1, /*SubRegIdx*/GIMT_Encode2(11), // src
        GIR_ConstrainOperandRC, /*InsnID*/4, /*Op*/0, GIMT_Encode2(AMDGPU::VGPR_32RegClassID),
        GIR_ConstrainOperandRC, /*InsnID*/4, /*Op*/1, GIMT_Encode2(AMDGPU::VReg_64RegClassID),
        GIR_BuildMI, /*InsnID*/3, /*Opcode*/GIMT_Encode2(AMDGPU::S_MOV_B32),
        GIR_AddTempRegister, /*InsnID*/3, /*TempRegID*/2, /*TempRegFlags*/GIMT_Encode2(RegState::Define),
        GIR_AddImm, /*InsnID*/3, /*Imm*/GIMT_Encode8(2147483648),
        GIR_ConstrainSelectedInstOperands, /*InsnID*/3,
        GIR_BuildMI, /*InsnID*/2, /*Opcode*/GIMT_Encode2(AMDGPU::V_XOR_B32_e64),
        GIR_AddTempRegister, /*InsnID*/2, /*TempRegID*/1, /*TempRegFlags*/GIMT_Encode2(RegState::Define),
        GIR_AddSimpleTempRegister, /*InsnID*/2, /*TempRegID*/2,
        GIR_AddSimpleTempRegister, /*InsnID*/2, /*TempRegID*/3,
        GIR_ConstrainSelectedInstOperands, /*InsnID*/2,
        GIR_BuildMI, /*InsnID*/1, /*Opcode*/GIMT_Encode2(TargetOpcode::COPY),
        GIR_AddTempRegister, /*InsnID*/1, /*TempRegID*/0, /*TempRegFlags*/GIMT_Encode2(RegState::Define),
        GIR_CopySubReg, /*NewInsnID*/1, /*OldInsnID*/0, /*OpIdx*/1, /*SubRegIdx*/GIMT_Encode2(3), // src
        GIR_ConstrainOperandRC, /*InsnID*/1, /*Op*/0, GIMT_Encode2(AMDGPU::VGPR_32RegClassID),
        GIR_ConstrainOperandRC, /*InsnID*/1, /*Op*/1, GIMT_Encode2(AMDGPU::VReg_64RegClassID),
        GIR_BuildMI, /*InsnID*/0, /*Opcode*/GIMT_Encode2(TargetOpcode::REG_SEQUENCE),
        GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/0, // DstI[dst]
        GIR_AddSimpleTempRegister, /*InsnID*/0, /*TempRegID*/0,
        GIR_AddImm8, /*InsnID*/0, /*SubRegIndex*/3,
        GIR_AddSimpleTempRegister, /*InsnID*/0, /*TempRegID*/1,
        GIR_AddImm8, /*InsnID*/0, /*SubRegIndex*/11,
        GIR_ConstrainOperandRC, /*InsnID*/0, /*Op*/0, GIMT_Encode2(AMDGPU::VReg_64RegClassID),
        GIR_ConstrainOperandRC, /*InsnID*/0, /*Op*/1, GIMT_Encode2(AMDGPU::VGPR_32RegClassID),
        GIR_ConstrainOperandRC, /*InsnID*/0, /*Op*/3, GIMT_Encode2(AMDGPU::VGPR_32RegClassID),
        GIR_EraseFromParent, /*InsnID*/0,
        // GIR_Coverage, 6231,
        GIR_Done,
      // Label 4146: @261342
      GIM_Reject,
    // Label 4144: @261343
    GIM_Reject,
    // Label 4131: @261344
    GIM_Try, /*On fail goto*//*Label 4147*/ GIMT_Encode4(261745),
      GIM_CheckType, /*MI*/0, /*Op*/1, /*Type*/GILLT_v2s16,
      GIM_Try, /*On fail goto*//*Label 4148*/ GIMT_Encode4(261466), // Rule ID 6213 //
        GIM_CheckRegBankForClass, /*MI*/0, /*Op*/0, /*RC*/GIMT_Encode2(AMDGPU::SReg_32RegClassID),
        GIM_RecordInsn, /*DefineMI*/1, /*MI*/0, /*OpIdx*/1, // MIs[1]
        GIM_CheckOpcode, /*MI*/1, GIMT_Encode2(TargetOpcode::G_BITCAST),
        GIM_CheckType, /*MI*/1, /*Op*/1, /*Type*/GILLT_s32,
        GIM_RecordInsn, /*DefineMI*/2, /*MI*/1, /*OpIdx*/1, // MIs[2]
        GIM_CheckOpcode, /*MI*/2, GIMT_Encode2(TargetOpcode::G_AND),
        GIM_CheckType, /*MI*/2, /*Op*/1, /*Type*/GILLT_s32,
        GIM_CheckType, /*MI*/2, /*Op*/2, /*Type*/GILLT_s32,
        GIM_CheckRegBankForClass, /*MI*/2, /*Op*/1, /*RC*/GIMT_Encode2(AMDGPU::SReg_32RegClassID),
        GIM_CheckConstantInt, /*MI*/2, /*Op*/2, GIMT_Encode8(2147450879),
        GIM_CheckCxxInsnPredicate, /*MI*/2, /*FnId*/GIMT_Encode2(GICXXPred_MI_Predicate_and_oneuse),
        GIM_CheckCxxInsnPredicate, /*MI*/0, /*FnId*/GIMT_Encode2(GICXXPred_MI_Predicate_anonymous_34988),
        GIM_CheckIsSafeToFold, /*InsnID*/1,
        GIM_CheckIsSafeToFold, /*InsnID*/2,
        // (fneg:{ *:[v2f16] } (bitconvert:{ *:[v2f16] } (and:{ *:[i32] } SReg_32:{ *:[i32] }:$src, 2147450879:{ *:[i32] })<<P:Predicate_and_oneuse>>))<<P:Predicate_anonymous_34988>>  =>  (S_OR_B32:{ *:[v2f16] }:{ *:[i1] } SReg_32:{ *:[i32] }:$src, (S_MOV_B32:{ *:[i1] } 2147516416:{ *:[i32] }))
        GIR_MakeTempReg, /*TempRegID*/0, /*TypeID*/GILLT_s1,
        GIR_BuildMI, /*InsnID*/1, /*Opcode*/GIMT_Encode2(AMDGPU::S_MOV_B32),
        GIR_AddTempRegister, /*InsnID*/1, /*TempRegID*/0, /*TempRegFlags*/GIMT_Encode2(RegState::Define),
        GIR_AddImm, /*InsnID*/1, /*Imm*/GIMT_Encode8(2147516416),
        GIR_ConstrainSelectedInstOperands, /*InsnID*/1,
        GIR_BuildMI, /*InsnID*/0, /*Opcode*/GIMT_Encode2(AMDGPU::S_OR_B32),
        GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/0, // DstI[sdst]
        GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/2, /*OpIdx*/1, // src
        GIR_AddSimpleTempRegister, /*InsnID*/0, /*TempRegID*/0,
        GIR_SetImplicitDefDead, /*InsnID*/0, /*OpIdx for AMDGPU::SCC*/0,
        GIR_ConstrainSelectedInstOperands, /*InsnID*/0,
        GIR_EraseFromParent, /*InsnID*/0,
        // GIR_Coverage, 6213,
        GIR_Done,
      // Label 4148: @261466
      GIM_Try, /*On fail goto*//*Label 4149*/ GIMT_Encode4(261546), // Rule ID 6214 //
        GIM_CheckRegBankForClass, /*MI*/0, /*Op*/0, /*RC*/GIMT_Encode2(AMDGPU::SReg_32RegClassID),
        GIM_RecordInsn, /*DefineMI*/1, /*MI*/0, /*OpIdx*/1, // MIs[1]
        GIM_CheckOpcode, /*MI*/1, GIMT_Encode2(TargetOpcode::G_FABS),
        GIM_CheckType, /*MI*/1, /*Op*/1, /*Type*/GILLT_v2s16,
        GIM_CheckRegBankForClass, /*MI*/1, /*Op*/1, /*RC*/GIMT_Encode2(AMDGPU::SReg_32RegClassID),
        GIM_CheckCxxInsnPredicate, /*MI*/0, /*FnId*/GIMT_Encode2(GICXXPred_MI_Predicate_anonymous_34988),
        GIM_CheckIsSafeToFold, /*InsnID*/1,
        // (fneg:{ *:[v2f16] } (fabs:{ *:[v2f16] } SReg_32:{ *:[v2f16] }:$src))<<P:Predicate_anonymous_34988>>  =>  (S_OR_B32:{ *:[v2f16] }:{ *:[i1] } SReg_32:{ *:[v2f16] }:$src, (S_MOV_B32:{ *:[i1] } 2147516416:{ *:[i32] }))
        GIR_MakeTempReg, /*TempRegID*/0, /*TypeID*/GILLT_s1,
        GIR_BuildMI, /*InsnID*/1, /*Opcode*/GIMT_Encode2(AMDGPU::S_MOV_B32),
        GIR_AddTempRegister, /*InsnID*/1, /*TempRegID*/0, /*TempRegFlags*/GIMT_Encode2(RegState::Define),
        GIR_AddImm, /*InsnID*/1, /*Imm*/GIMT_Encode8(2147516416),
        GIR_ConstrainSelectedInstOperands, /*InsnID*/1,
        GIR_BuildMI, /*InsnID*/0, /*Opcode*/GIMT_Encode2(AMDGPU::S_OR_B32),
        GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/0, // DstI[sdst]
        GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/1, /*OpIdx*/1, // src
        GIR_AddSimpleTempRegister, /*InsnID*/0, /*TempRegID*/0,
        GIR_SetImplicitDefDead, /*InsnID*/0, /*OpIdx for AMDGPU::SCC*/0,
        GIR_ConstrainSelectedInstOperands, /*InsnID*/0,
        GIR_EraseFromParent, /*InsnID*/0,
        // GIR_Coverage, 6214,
        GIR_Done,
      // Label 4149: @261546
      GIM_Try, /*On fail goto*//*Label 4150*/ GIMT_Encode4(261619), // Rule ID 6229 //
        GIM_CheckRegBankForClass, /*MI*/0, /*Op*/0, /*RC*/GIMT_Encode2(AMDGPU::VGPR_32RegClassID),
        GIM_RecordInsn, /*DefineMI*/1, /*MI*/0, /*OpIdx*/1, // MIs[1]
        GIM_CheckOpcode, /*MI*/1, GIMT_Encode2(TargetOpcode::G_FABS),
        GIM_CheckType, /*MI*/1, /*Op*/1, /*Type*/GILLT_v2s16,
        GIM_CheckRegBankForClass, /*MI*/1, /*Op*/1, /*RC*/GIMT_Encode2(AMDGPU::VGPR_32RegClassID),
        GIM_CheckIsSafeToFold, /*InsnID*/1,
        // (fneg:{ *:[v2f16] } (fabs:{ *:[v2f16] } VGPR_32:{ *:[v2f16] }:$src))  =>  (V_OR_B32_e64:{ *:[v2f16] } (S_MOV_B32:{ *:[i16] } 2147516416:{ *:[i32] }), VGPR_32:{ *:[v2f16] }:$src)
        GIR_MakeTempReg, /*TempRegID*/0, /*TypeID*/GILLT_s16,
        GIR_BuildMI, /*InsnID*/1, /*Opcode*/GIMT_Encode2(AMDGPU::S_MOV_B32),
        GIR_AddTempRegister, /*InsnID*/1, /*TempRegID*/0, /*TempRegFlags*/GIMT_Encode2(RegState::Define),
        GIR_AddImm, /*InsnID*/1, /*Imm*/GIMT_Encode8(2147516416),
        GIR_ConstrainSelectedInstOperands, /*InsnID*/1,
        GIR_BuildMI, /*InsnID*/0, /*Opcode*/GIMT_Encode2(AMDGPU::V_OR_B32_e64),
        GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/0, // DstI[vdst]
        GIR_AddSimpleTempRegister, /*InsnID*/0, /*TempRegID*/0,
        GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/1, /*OpIdx*/1, // src
        GIR_ConstrainSelectedInstOperands, /*InsnID*/0,
        GIR_EraseFromParent, /*InsnID*/0,
        // GIR_Coverage, 6229,
        GIR_Done,
      // Label 4150: @261619
      GIM_Try, /*On fail goto*//*Label 4151*/ GIMT_Encode4(261685), // Rule ID 6211 //
        GIM_CheckRegBankForClass, /*MI*/0, /*Op*/0, /*RC*/GIMT_Encode2(AMDGPU::SReg_32RegClassID),
        GIM_CheckRegBankForClass, /*MI*/0, /*Op*/1, /*RC*/GIMT_Encode2(AMDGPU::SReg_32RegClassID),
        GIM_CheckCxxInsnPredicate, /*MI*/0, /*FnId*/GIMT_Encode2(GICXXPred_MI_Predicate_anonymous_34988),
        // (fneg:{ *:[v2f16] } SReg_32:{ *:[v2f16] }:$src)<<P:Predicate_anonymous_34988>>  =>  (S_XOR_B32:{ *:[v2f16] }:{ *:[i1] } SReg_32:{ *:[v2f16] }:$src, (S_MOV_B32:{ *:[i1] } 2147516416:{ *:[i32] }))
        GIR_MakeTempReg, /*TempRegID*/0, /*TypeID*/GILLT_s1,
        GIR_BuildMI, /*InsnID*/1, /*Opcode*/GIMT_Encode2(AMDGPU::S_MOV_B32),
        GIR_AddTempRegister, /*InsnID*/1, /*TempRegID*/0, /*TempRegFlags*/GIMT_Encode2(RegState::Define),
        GIR_AddImm, /*InsnID*/1, /*Imm*/GIMT_Encode8(2147516416),
        GIR_ConstrainSelectedInstOperands, /*InsnID*/1,
        GIR_BuildMI, /*InsnID*/0, /*Opcode*/GIMT_Encode2(AMDGPU::S_XOR_B32),
        GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/0, // DstI[sdst]
        GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/1, // src
        GIR_AddSimpleTempRegister, /*InsnID*/0, /*TempRegID*/0,
        GIR_SetImplicitDefDead, /*InsnID*/0, /*OpIdx for AMDGPU::SCC*/0,
        GIR_ConstrainSelectedInstOperands, /*InsnID*/0,
        GIR_EraseFromParent, /*InsnID*/0,
        // GIR_Coverage, 6211,
        GIR_Done,
      // Label 4151: @261685
      GIM_Try, /*On fail goto*//*Label 4152*/ GIMT_Encode4(261744), // Rule ID 6227 //
        GIM_CheckRegBankForClass, /*MI*/0, /*Op*/0, /*RC*/GIMT_Encode2(AMDGPU::VGPR_32RegClassID),
        GIM_CheckRegBankForClass, /*MI*/0, /*Op*/1, /*RC*/GIMT_Encode2(AMDGPU::VGPR_32RegClassID),
        // (fneg:{ *:[v2f16] } VGPR_32:{ *:[v2f16] }:$src)  =>  (V_XOR_B32_e64:{ *:[v2f16] } (S_MOV_B32:{ *:[i16] } 2147516416:{ *:[i32] }), VGPR_32:{ *:[v2f16] }:$src)
        GIR_MakeTempReg, /*TempRegID*/0, /*TypeID*/GILLT_s16,
        GIR_BuildMI, /*InsnID*/1, /*Opcode*/GIMT_Encode2(AMDGPU::S_MOV_B32),
        GIR_AddTempRegister, /*InsnID*/1, /*TempRegID*/0, /*TempRegFlags*/GIMT_Encode2(RegState::Define),
        GIR_AddImm, /*InsnID*/1, /*Imm*/GIMT_Encode8(2147516416),
        GIR_ConstrainSelectedInstOperands, /*InsnID*/1,
        GIR_BuildMI, /*InsnID*/0, /*Opcode*/GIMT_Encode2(AMDGPU::V_XOR_B32_e64),
        GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/0, // DstI[vdst]
        GIR_AddSimpleTempRegister, /*InsnID*/0, /*TempRegID*/0,
        GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/1, // src
        GIR_ConstrainSelectedInstOperands, /*InsnID*/0,
        GIR_EraseFromParent, /*InsnID*/0,
        // GIR_Coverage, 6227,
        GIR_Done,
      // Label 4152: @261744
      GIM_Reject,
    // Label 4147: @261745
    GIM_Reject,
    // Label 4132: @261746
    GIM_Try, /*On fail goto*//*Label 4153*/ GIMT_Encode4(261813), // Rule ID 6233 //
      GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasPackedFP32Ops),
      GIM_CheckType, /*MI*/0, /*Op*/1, /*Type*/GILLT_v2s32,
      GIM_CheckRegBankForClass, /*MI*/0, /*Op*/0, /*RC*/GIMT_Encode2(AMDGPU::VReg_64RegClassID),
      GIM_CheckRegBankForClass, /*MI*/0, /*Op*/1, /*RC*/GIMT_Encode2(AMDGPU::VReg_64RegClassID),
      GIM_CheckCxxInsnPredicate, /*MI*/0, /*FnId*/GIMT_Encode2(GICXXPred_MI_Predicate_anonymous_35018),
      // (fneg:{ *:[v2f32] } VReg_64:{ *:[v2f32] }:$src)<<P:Predicate_anonymous_35018>>  =>  (V_PK_ADD_F32:{ *:[v2f32] } 11:{ *:[i32] }, VReg_64:{ *:[v2f32] }:$src, 11:{ *:[i32] }, 0:{ *:[i64] }, 0:{ *:[i1] }, 0:{ *:[i32] }, 0:{ *:[i32] }, 0:{ *:[i32] }, 0:{ *:[i32] })
      GIR_BuildMI, /*InsnID*/0, /*Opcode*/GIMT_Encode2(AMDGPU::V_PK_ADD_F32),
      GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/0, // DstI[vdst]
      GIR_AddImm8, /*InsnID*/0, /*Imm*/11,
      GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/1, // src
      GIR_AddImm8, /*InsnID*/0, /*Imm*/11,
      GIR_AddImm8, /*InsnID*/0, /*Imm*/0,
      GIR_AddImm8, /*InsnID*/0, /*Imm*/0,
      GIR_AddImm8, /*InsnID*/0, /*Imm*/0,
      GIR_AddImm8, /*InsnID*/0, /*Imm*/0,
      GIR_AddImm8, /*InsnID*/0, /*Imm*/0,
      GIR_AddImm8, /*InsnID*/0, /*Imm*/0,
      GIR_ConstrainSelectedInstOperands, /*InsnID*/0,
      GIR_EraseFromParent, /*InsnID*/0,
      // GIR_Coverage, 6233,
      GIR_Done,
    // Label 4153: @261813
    GIM_Reject,
    // Label 4133: @261814
    GIM_Reject,
    // Label 66: @261815
    GIM_SwitchType, /*MI*/0, /*Op*/0, /*[*/GIMT_Encode2(9), GIMT_Encode2(11), /*)*//*default:*//*Label 4156*/ GIMT_Encode4(262155),
    /*GILLT_s32*//*Label 4154*/ GIMT_Encode4(261834),
    /*GILLT_s64*//*Label 4155*/ GIMT_Encode4(261980),
    // Label 4154: @261834
    GIM_Try, /*On fail goto*//*Label 4157*/ GIMT_Encode4(261979),
      GIM_CheckType, /*MI*/0, /*Op*/1, /*Type*/GILLT_s16,
      GIM_Try, /*On fail goto*//*Label 4158*/ GIMT_Encode4(261872), // Rule ID 31 //
        GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasSALUFloatInsts),
        GIM_CheckRegBankForClass, /*MI*/0, /*Op*/0, /*RC*/GIMT_Encode2(AMDGPU::SReg_32RegClassID),
        GIM_CheckCxxInsnPredicate, /*MI*/0, /*FnId*/GIMT_Encode2(GICXXPred_MI_Predicate_anonymous_17597),
        // (fpextend:{ *:[f32] } f16:{ *:[f16] }:$src0)<<P:Predicate_anonymous_17597>>  =>  (S_CVT_F32_F16:{ *:[f32] } f16:{ *:[f16] }:$src0)
        GIR_MutateOpcode, /*InsnID*/0, /*RecycleInsnID*/0, /*Opcode*/GIMT_Encode2(AMDGPU::S_CVT_F32_F16),
        GIR_AddImplicitUse, /*InsnID*/0, GIMT_Encode2(AMDGPU::MODE),
        GIR_ConstrainSelectedInstOperands, /*InsnID*/0,
        // GIR_Coverage, 31,
        GIR_Done,
      // Label 4158: @261872
      GIM_Try, /*On fail goto*//*Label 4159*/ GIMT_Encode4(261925), // Rule ID 590 //
        GIM_CheckFeatures, GIMT_Encode2(GIFBS_NotHasTrue16BitInsts),
        GIM_CheckRegBankForClass, /*MI*/0, /*Op*/0, /*RC*/GIMT_Encode2(AMDGPU::VGPR_32RegClassID),
        GIM_CheckComplexPattern, /*MI*/0, /*Op*/1, /*Renderer*/GIMT_Encode2(0), GIMT_Encode2(GICP_gi_vop3mods0),
        // (fpextend:{ *:[f32] } (VOP3Mods0:{ *:[f16] } f16:{ *:[f16] }:$src0, i32:{ *:[i32] }:$src0_modifiers, i1:{ *:[i1] }:$clamp, i32:{ *:[i32] }:$omod))  =>  (V_CVT_F32_F16_e64:{ *:[f32] } i32:{ *:[i32] }:$src0_modifiers, f16:{ *:[f16] }:$src0, i1:{ *:[i1] }:$clamp, i32:{ *:[i32] }:$omod)
        GIR_BuildMI, /*InsnID*/0, /*Opcode*/GIMT_Encode2(AMDGPU::V_CVT_F32_F16_e64),
        GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/0, // DstI[vdst]
        GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/1, // src0_modifiers
        GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/0, // src0
        GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/2, // clamp
        GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/3, // omod
        GIR_ConstrainSelectedInstOperands, /*InsnID*/0,
        GIR_EraseFromParent, /*InsnID*/0,
        // GIR_Coverage, 590,
        GIR_Done,
      // Label 4159: @261925
      GIM_Try, /*On fail goto*//*Label 4160*/ GIMT_Encode4(261978), // Rule ID 592 //
        GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasTrue16BitInsts),
        GIM_CheckRegBankForClass, /*MI*/0, /*Op*/0, /*RC*/GIMT_Encode2(AMDGPU::VGPR_32RegClassID),
        GIM_CheckComplexPattern, /*MI*/0, /*Op*/1, /*Renderer*/GIMT_Encode2(0), GIMT_Encode2(GICP_gi_vop3mods0),
        // (fpextend:{ *:[f32] } (VOP3Mods0:{ *:[f16] } f16:{ *:[f16] }:$src0, i32:{ *:[i32] }:$src0_modifiers, i1:{ *:[i1] }:$clamp, i32:{ *:[i32] }:$omod))  =>  (V_CVT_F32_F16_t16_e64:{ *:[f32] } i32:{ *:[i32] }:$src0_modifiers, f16:{ *:[f16] }:$src0, i1:{ *:[i1] }:$clamp, i32:{ *:[i32] }:$omod)
        GIR_BuildMI, /*InsnID*/0, /*Opcode*/GIMT_Encode2(AMDGPU::V_CVT_F32_F16_t16_e64),
        GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/0, // DstI[vdst]
        GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/1, // src0_modifiers
        GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/0, // src0
        GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/2, // clamp
        GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/3, // omod
        GIR_ConstrainSelectedInstOperands, /*InsnID*/0,
        GIR_EraseFromParent, /*InsnID*/0,
        // GIR_Coverage, 592,
        GIR_Done,
      // Label 4160: @261978
      GIM_Reject,
    // Label 4157: @261979
    GIM_Reject,
    // Label 4155: @261980
    GIM_Try, /*On fail goto*//*Label 4161*/ GIMT_Encode4(262040), // Rule ID 5865 //
      GIM_CheckFeatures, GIMT_Encode2(GIFBS_NotHasTrue16BitInsts),
      GIM_CheckType, /*MI*/0, /*Op*/1, /*Type*/GILLT_s16,
      GIM_CheckRegBankForClass, /*MI*/0, /*Op*/0, /*RC*/GIMT_Encode2(AMDGPU::VReg_64RegClassID),
      // (fpextend:{ *:[f64] } f16:{ *:[f16] }:$src)  =>  (V_CVT_F64_F32_e32:{ *:[f64] } (V_CVT_F32_F16_e64:{ *:[i16] } 0:{ *:[i32] }, ?:{ *:[f16] }:$src))
      GIR_MakeTempReg, /*TempRegID*/0, /*TypeID*/GILLT_s16,
      GIR_BuildMI, /*InsnID*/1, /*Opcode*/GIMT_Encode2(AMDGPU::V_CVT_F32_F16_e64),
      GIR_AddTempRegister, /*InsnID*/1, /*TempRegID*/0, /*TempRegFlags*/GIMT_Encode2(RegState::Define),
      GIR_AddImm8, /*InsnID*/1, /*Imm*/0,
      GIR_Copy, /*NewInsnID*/1, /*OldInsnID*/0, /*OpIdx*/1, // src
      GIR_AddImm8, /*InsnID*/1, /*Imm*/0,
      GIR_AddImm8, /*InsnID*/1, /*Imm*/0,
      GIR_ConstrainSelectedInstOperands, /*InsnID*/1,
      GIR_BuildMI, /*InsnID*/0, /*Opcode*/GIMT_Encode2(AMDGPU::V_CVT_F64_F32_e32),
      GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/0, // DstI[vdst]
      GIR_AddSimpleTempRegister, /*InsnID*/0, /*TempRegID*/0,
      GIR_ConstrainSelectedInstOperands, /*InsnID*/0,
      GIR_EraseFromParent, /*InsnID*/0,
      // GIR_Coverage, 5865,
      GIR_Done,
    // Label 4161: @262040
    GIM_Try, /*On fail goto*//*Label 4162*/ GIMT_Encode4(262100), // Rule ID 5879 //
      GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasTrue16BitInsts),
      GIM_CheckType, /*MI*/0, /*Op*/1, /*Type*/GILLT_s16,
      GIM_CheckRegBankForClass, /*MI*/0, /*Op*/0, /*RC*/GIMT_Encode2(AMDGPU::VReg_64RegClassID),
      // (fpextend:{ *:[f64] } f16:{ *:[f16] }:$src)  =>  (V_CVT_F64_F32_e32:{ *:[f64] } (V_CVT_F32_F16_t16_e64:{ *:[i16] } 0:{ *:[i32] }, ?:{ *:[f16] }:$src))
      GIR_MakeTempReg, /*TempRegID*/0, /*TypeID*/GILLT_s16,
      GIR_BuildMI, /*InsnID*/1, /*Opcode*/GIMT_Encode2(AMDGPU::V_CVT_F32_F16_t16_e64),
      GIR_AddTempRegister, /*InsnID*/1, /*TempRegID*/0, /*TempRegFlags*/GIMT_Encode2(RegState::Define),
      GIR_AddImm8, /*InsnID*/1, /*Imm*/0,
      GIR_Copy, /*NewInsnID*/1, /*OldInsnID*/0, /*OpIdx*/1, // src
      GIR_AddImm8, /*InsnID*/1, /*Imm*/0,
      GIR_AddImm8, /*InsnID*/1, /*Imm*/0,
      GIR_ConstrainSelectedInstOperands, /*InsnID*/1,
      GIR_BuildMI, /*InsnID*/0, /*Opcode*/GIMT_Encode2(AMDGPU::V_CVT_F64_F32_e32),
      GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/0, // DstI[vdst]
      GIR_AddSimpleTempRegister, /*InsnID*/0, /*TempRegID*/0,
      GIR_ConstrainSelectedInstOperands, /*InsnID*/0,
      GIR_EraseFromParent, /*InsnID*/0,
      // GIR_Coverage, 5879,
      GIR_Done,
    // Label 4162: @262100
    GIM_Try, /*On fail goto*//*Label 4163*/ GIMT_Encode4(262154), // Rule ID 578 //
      GIM_CheckType, /*MI*/0, /*Op*/1, /*Type*/GILLT_s32,
      GIM_CheckRegBankForClass, /*MI*/0, /*Op*/0, /*RC*/GIMT_Encode2(AMDGPU::VReg_64RegClassID),
      GIM_CheckComplexPattern, /*MI*/0, /*Op*/1, /*Renderer*/GIMT_Encode2(0), GIMT_Encode2(GICP_gi_vop3mods0),
      // (fpextend:{ *:[f64] } (VOP3Mods0:{ *:[f32] } f32:{ *:[f32] }:$src0, i32:{ *:[i32] }:$src0_modifiers, i1:{ *:[i1] }:$clamp, i32:{ *:[i32] }:$omod))  =>  (V_CVT_F64_F32_e64:{ *:[f64] } i32:{ *:[i32] }:$src0_modifiers, f32:{ *:[f32] }:$src0, i1:{ *:[i1] }:$clamp, i32:{ *:[i32] }:$omod)
      GIR_BuildMI, /*InsnID*/0, /*Opcode*/GIMT_Encode2(AMDGPU::V_CVT_F64_F32_e64),
      GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/0, // DstI[vdst]
      GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/1, // src0_modifiers
      GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/0, // src0
      GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/2, // clamp
      GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/3, // omod
      GIR_ConstrainSelectedInstOperands, /*InsnID*/0,
      GIR_EraseFromParent, /*InsnID*/0,
      // GIR_Coverage, 578,
      GIR_Done,
    // Label 4163: @262154
    GIM_Reject,
    // Label 4156: @262155
    GIM_Reject,
    // Label 67: @262156
    GIM_SwitchType, /*MI*/0, /*Op*/0, /*[*/GIMT_Encode2(8), GIMT_Encode2(10), /*)*//*default:*//*Label 4166*/ GIMT_Encode4(262846),
    /*GILLT_s16*//*Label 4164*/ GIMT_Encode4(262175),
    /*GILLT_s32*//*Label 4165*/ GIMT_Encode4(262791),
    // Label 4164: @262175
    GIM_Try, /*On fail goto*//*Label 4167*/ GIMT_Encode4(262790),
      GIM_CheckType, /*MI*/0, /*Op*/1, /*Type*/GILLT_s32,
      GIM_Try, /*On fail goto*//*Label 4168*/ GIMT_Encode4(262309), // Rule ID 2261 //
        GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasFmaMixInsts),
        GIM_CheckRegBankForClass, /*MI*/0, /*Op*/0, /*RC*/GIMT_Encode2(AMDGPU::VGPR_32RegClassID),
        GIM_RecordInsn, /*DefineMI*/1, /*MI*/0, /*OpIdx*/1, // MIs[1]
        GIM_CheckOpcode, /*MI*/1, GIMT_Encode2(TargetOpcode::G_FMA),
        GIM_CheckType, /*MI*/1, /*Op*/1, /*Type*/GILLT_s32,
        GIM_CheckType, /*MI*/1, /*Op*/2, /*Type*/GILLT_s32,
        GIM_CheckType, /*MI*/1, /*Op*/3, /*Type*/GILLT_s32,
        GIM_CheckIsSafeToFold, /*InsnID*/1,
        GIM_CheckComplexPattern, /*MI*/1, /*Op*/1, /*Renderer*/GIMT_Encode2(0), GIMT_Encode2(GICP_gi_vop3_mad_mix_mods),
        GIM_CheckComplexPattern, /*MI*/1, /*Op*/2, /*Renderer*/GIMT_Encode2(1), GIMT_Encode2(GICP_gi_vop3_mad_mix_mods),
        GIM_CheckComplexPattern, /*MI*/1, /*Op*/3, /*Renderer*/GIMT_Encode2(2), GIMT_Encode2(GICP_gi_vop3_mad_mix_mods),
        // (fpround:{ *:[f16] } (fma:{ *:[f32] } (VOP3PMadMixMods:{ *:[f32] } f16:{ *:[f16] }:$src0, i32:{ *:[i32] }:$src0_modifiers), (VOP3PMadMixMods:{ *:[f32] } f16:{ *:[f16] }:$src1, i32:{ *:[i32] }:$src1_modifiers), (VOP3PMadMixMods:{ *:[f32] } f16:{ *:[f16] }:$src2, i32:{ *:[i32] }:$src2_modifiers)))  =>  (V_FMA_MIXLO_F16:{ *:[f16] } ?:{ *:[i32] }:$src0_modifiers, ?:{ *:[f16] }:$src0, ?:{ *:[i32] }:$src1_modifiers, ?:{ *:[f16] }:$src1, ?:{ *:[i32] }:$src2_modifiers, ?:{ *:[f16] }:$src2, 0:{ *:[i1] }, (IMPLICIT_DEF:{ *:[i32] }))
        GIR_MakeTempReg, /*TempRegID*/0, /*TypeID*/GILLT_s32,
        GIR_BuildMI, /*InsnID*/1, /*Opcode*/GIMT_Encode2(TargetOpcode::IMPLICIT_DEF),
        GIR_AddTempRegister, /*InsnID*/1, /*TempRegID*/0, /*TempRegFlags*/GIMT_Encode2(RegState::Define),
        GIR_ConstrainSelectedInstOperands, /*InsnID*/1,
        GIR_BuildMI, /*InsnID*/0, /*Opcode*/GIMT_Encode2(AMDGPU::V_FMA_MIXLO_F16),
        GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/0, // DstI[vdst]
        GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/1, // src0_modifiers
        GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/0, // src0
        GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(1), /*SubOperand*/1, // src1_modifiers
        GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(1), /*SubOperand*/0, // src1
        GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(2), /*SubOperand*/1, // src2_modifiers
        GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(2), /*SubOperand*/0, // src2
        GIR_AddImm8, /*InsnID*/0, /*Imm*/0,
        GIR_AddSimpleTempRegister, /*InsnID*/0, /*TempRegID*/0,
        GIR_AddImm8, /*InsnID*/0, /*Imm*/0,
        GIR_AddImm8, /*InsnID*/0, /*Imm*/0,
        GIR_ConstrainSelectedInstOperands, /*InsnID*/0,
        GIR_EraseFromParent, /*InsnID*/0,
        // GIR_Coverage, 2261,
        GIR_Done,
      // Label 4168: @262309
      GIM_Try, /*On fail goto*//*Label 4169*/ GIMT_Encode4(262434), // Rule ID 2252 //
        GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasMadMixInsts_NoFP32Denormals),
        GIM_CheckRegBankForClass, /*MI*/0, /*Op*/0, /*RC*/GIMT_Encode2(AMDGPU::VGPR_32RegClassID),
        GIM_RecordInsn, /*DefineMI*/1, /*MI*/0, /*OpIdx*/1, // MIs[1]
        GIM_CheckOpcode, /*MI*/1, GIMT_Encode2(TargetOpcode::G_FMAD),
        GIM_CheckType, /*MI*/1, /*Op*/1, /*Type*/GILLT_s32,
        GIM_CheckType, /*MI*/1, /*Op*/2, /*Type*/GILLT_s32,
        GIM_CheckType, /*MI*/1, /*Op*/3, /*Type*/GILLT_s32,
        GIM_CheckIsSafeToFold, /*InsnID*/1,
        GIM_CheckComplexPattern, /*MI*/1, /*Op*/1, /*Renderer*/GIMT_Encode2(0), GIMT_Encode2(GICP_gi_vop3_mad_mix_mods),
        GIM_CheckComplexPattern, /*MI*/1, /*Op*/2, /*Renderer*/GIMT_Encode2(1), GIMT_Encode2(GICP_gi_vop3_mad_mix_mods),
        GIM_CheckComplexPattern, /*MI*/1, /*Op*/3, /*Renderer*/GIMT_Encode2(2), GIMT_Encode2(GICP_gi_vop3_mad_mix_mods),
        // (fpround:{ *:[f16] } (fmad:{ *:[f32] } (VOP3PMadMixMods:{ *:[f32] } f16:{ *:[f16] }:$src0, i32:{ *:[i32] }:$src0_modifiers), (VOP3PMadMixMods:{ *:[f32] } f16:{ *:[f16] }:$src1, i32:{ *:[i32] }:$src1_modifiers), (VOP3PMadMixMods:{ *:[f32] } f16:{ *:[f16] }:$src2, i32:{ *:[i32] }:$src2_modifiers)))  =>  (V_MAD_MIXLO_F16:{ *:[f16] } ?:{ *:[i32] }:$src0_modifiers, ?:{ *:[f16] }:$src0, ?:{ *:[i32] }:$src1_modifiers, ?:{ *:[f16] }:$src1, ?:{ *:[i32] }:$src2_modifiers, ?:{ *:[f16] }:$src2, 0:{ *:[i1] }, (IMPLICIT_DEF:{ *:[i32] }))
        GIR_MakeTempReg, /*TempRegID*/0, /*TypeID*/GILLT_s32,
        GIR_BuildMI, /*InsnID*/1, /*Opcode*/GIMT_Encode2(TargetOpcode::IMPLICIT_DEF),
        GIR_AddTempRegister, /*InsnID*/1, /*TempRegID*/0, /*TempRegFlags*/GIMT_Encode2(RegState::Define),
        GIR_ConstrainSelectedInstOperands, /*InsnID*/1,
        GIR_BuildMI, /*InsnID*/0, /*Opcode*/GIMT_Encode2(AMDGPU::V_MAD_MIXLO_F16),
        GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/0, // DstI[vdst]
        GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/1, // src0_modifiers
        GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/0, // src0
        GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(1), /*SubOperand*/1, // src1_modifiers
        GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(1), /*SubOperand*/0, // src1
        GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(2), /*SubOperand*/1, // src2_modifiers
        GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(2), /*SubOperand*/0, // src2
        GIR_AddImm8, /*InsnID*/0, /*Imm*/0,
        GIR_AddSimpleTempRegister, /*InsnID*/0, /*TempRegID*/0,
        GIR_AddImm8, /*InsnID*/0, /*Imm*/0,
        GIR_AddImm8, /*InsnID*/0, /*Imm*/0,
        GIR_ConstrainSelectedInstOperands, /*InsnID*/0,
        GIR_EraseFromParent, /*InsnID*/0,
        // GIR_Coverage, 2252,
        GIR_Done,
      // Label 4169: @262434
      GIM_Try, /*On fail goto*//*Label 4170*/ GIMT_Encode4(262544), // Rule ID 2256 //
        GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasMadMixInsts_NoFP32Denormals),
        GIM_CheckRegBankForClass, /*MI*/0, /*Op*/0, /*RC*/GIMT_Encode2(AMDGPU::VGPR_32RegClassID),
        GIM_RecordInsn, /*DefineMI*/1, /*MI*/0, /*OpIdx*/1, // MIs[1]
        GIM_CheckOpcode, /*MI*/1, GIMT_Encode2(TargetOpcode::G_FMUL),
        GIM_CheckType, /*MI*/1, /*Op*/1, /*Type*/GILLT_s32,
        GIM_CheckType, /*MI*/1, /*Op*/2, /*Type*/GILLT_s32,
        GIM_CheckIsSafeToFold, /*InsnID*/1,
        GIM_CheckComplexPattern, /*MI*/1, /*Op*/1, /*Renderer*/GIMT_Encode2(0), GIMT_Encode2(GICP_gi_vop3_mad_mix_mods),
        GIM_CheckComplexPattern, /*MI*/1, /*Op*/2, /*Renderer*/GIMT_Encode2(1), GIMT_Encode2(GICP_gi_vop3_mad_mix_mods),
        // (fpround:{ *:[f16] } (fmul:{ *:[f32] } (VOP3PMadMixMods:{ *:[f32] } f32:{ *:[f32] }:$src0, i32:{ *:[i32] }:$src0_modifiers), (VOP3PMadMixMods:{ *:[f32] } f32:{ *:[f32] }:$src1, i32:{ *:[i32] }:$src1_modifiers)))  =>  (V_MAD_MIXLO_F16:{ *:[f16] } ?:{ *:[i32] }:$src0_modifiers, ?:{ *:[f32] }:$src0, ?:{ *:[i32] }:$src1_modifiers, ?:{ *:[f32] }:$src1, 0:{ *:[i32] }, 0:{ *:[i32] }, 0:{ *:[i1] }, (IMPLICIT_DEF:{ *:[i32] }))
        GIR_MakeTempReg, /*TempRegID*/0, /*TypeID*/GILLT_s32,
        GIR_BuildMI, /*InsnID*/1, /*Opcode*/GIMT_Encode2(TargetOpcode::IMPLICIT_DEF),
        GIR_AddTempRegister, /*InsnID*/1, /*TempRegID*/0, /*TempRegFlags*/GIMT_Encode2(RegState::Define),
        GIR_ConstrainSelectedInstOperands, /*InsnID*/1,
        GIR_BuildMI, /*InsnID*/0, /*Opcode*/GIMT_Encode2(AMDGPU::V_MAD_MIXLO_F16),
        GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/0, // DstI[vdst]
        GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/1, // src0_modifiers
        GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/0, // src0
        GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(1), /*SubOperand*/1, // src1_modifiers
        GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(1), /*SubOperand*/0, // src1
        GIR_AddImm8, /*InsnID*/0, /*Imm*/0,
        GIR_AddImm8, /*InsnID*/0, /*Imm*/0,
        GIR_AddImm8, /*InsnID*/0, /*Imm*/0,
        GIR_AddSimpleTempRegister, /*InsnID*/0, /*TempRegID*/0,
        GIR_AddImm8, /*InsnID*/0, /*Imm*/0,
        GIR_AddImm8, /*InsnID*/0, /*Imm*/0,
        GIR_ConstrainSelectedInstOperands, /*InsnID*/0,
        GIR_EraseFromParent, /*InsnID*/0,
        // GIR_Coverage, 2256,
        GIR_Done,
      // Label 4170: @262544
      GIM_Try, /*On fail goto*//*Label 4171*/ GIMT_Encode4(262654), // Rule ID 2265 //
        GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasFmaMixInsts),
        GIM_CheckRegBankForClass, /*MI*/0, /*Op*/0, /*RC*/GIMT_Encode2(AMDGPU::VGPR_32RegClassID),
        GIM_RecordInsn, /*DefineMI*/1, /*MI*/0, /*OpIdx*/1, // MIs[1]
        GIM_CheckOpcode, /*MI*/1, GIMT_Encode2(TargetOpcode::G_FMUL),
        GIM_CheckType, /*MI*/1, /*Op*/1, /*Type*/GILLT_s32,
        GIM_CheckType, /*MI*/1, /*Op*/2, /*Type*/GILLT_s32,
        GIM_CheckIsSafeToFold, /*InsnID*/1,
        GIM_CheckComplexPattern, /*MI*/1, /*Op*/1, /*Renderer*/GIMT_Encode2(0), GIMT_Encode2(GICP_gi_vop3_mad_mix_mods),
        GIM_CheckComplexPattern, /*MI*/1, /*Op*/2, /*Renderer*/GIMT_Encode2(1), GIMT_Encode2(GICP_gi_vop3_mad_mix_mods),
        // (fpround:{ *:[f16] } (fmul:{ *:[f32] } (VOP3PMadMixMods:{ *:[f32] } f32:{ *:[f32] }:$src0, i32:{ *:[i32] }:$src0_modifiers), (VOP3PMadMixMods:{ *:[f32] } f32:{ *:[f32] }:$src1, i32:{ *:[i32] }:$src1_modifiers)))  =>  (V_FMA_MIXLO_F16:{ *:[f16] } ?:{ *:[i32] }:$src0_modifiers, ?:{ *:[f32] }:$src0, ?:{ *:[i32] }:$src1_modifiers, ?:{ *:[f32] }:$src1, 0:{ *:[i32] }, 0:{ *:[i32] }, 0:{ *:[i1] }, (IMPLICIT_DEF:{ *:[i32] }))
        GIR_MakeTempReg, /*TempRegID*/0, /*TypeID*/GILLT_s32,
        GIR_BuildMI, /*InsnID*/1, /*Opcode*/GIMT_Encode2(TargetOpcode::IMPLICIT_DEF),
        GIR_AddTempRegister, /*InsnID*/1, /*TempRegID*/0, /*TempRegFlags*/GIMT_Encode2(RegState::Define),
        GIR_ConstrainSelectedInstOperands, /*InsnID*/1,
        GIR_BuildMI, /*InsnID*/0, /*Opcode*/GIMT_Encode2(AMDGPU::V_FMA_MIXLO_F16),
        GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/0, // DstI[vdst]
        GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/1, // src0_modifiers
        GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/0, // src0
        GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(1), /*SubOperand*/1, // src1_modifiers
        GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(1), /*SubOperand*/0, // src1
        GIR_AddImm8, /*InsnID*/0, /*Imm*/0,
        GIR_AddImm8, /*InsnID*/0, /*Imm*/0,
        GIR_AddImm8, /*InsnID*/0, /*Imm*/0,
        GIR_AddSimpleTempRegister, /*InsnID*/0, /*TempRegID*/0,
        GIR_AddImm8, /*InsnID*/0, /*Imm*/0,
        GIR_AddImm8, /*InsnID*/0, /*Imm*/0,
        GIR_ConstrainSelectedInstOperands, /*InsnID*/0,
        GIR_EraseFromParent, /*InsnID*/0,
        // GIR_Coverage, 2265,
        GIR_Done,
      // Label 4171: @262654
      GIM_Try, /*On fail goto*//*Label 4172*/ GIMT_Encode4(262683), // Rule ID 36 //
        GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasSALUFloatInsts),
        GIM_CheckRegBankForClass, /*MI*/0, /*Op*/0, /*RC*/GIMT_Encode2(AMDGPU::SReg_32RegClassID),
        GIM_CheckCxxInsnPredicate, /*MI*/0, /*FnId*/GIMT_Encode2(GICXXPred_MI_Predicate_anonymous_17602),
        // (fpround:{ *:[f16] } f32:{ *:[f32] }:$src0)<<P:Predicate_anonymous_17602>>  =>  (S_CVT_F16_F32:{ *:[f16] } f32:{ *:[f32] }:$src0)
        GIR_MutateOpcode, /*InsnID*/0, /*RecycleInsnID*/0, /*Opcode*/GIMT_Encode2(AMDGPU::S_CVT_F16_F32),
        GIR_AddImplicitUse, /*InsnID*/0, GIMT_Encode2(AMDGPU::MODE),
        GIR_ConstrainSelectedInstOperands, /*InsnID*/0,
        // GIR_Coverage, 36,
        GIR_Done,
      // Label 4172: @262683
      GIM_Try, /*On fail goto*//*Label 4173*/ GIMT_Encode4(262736), // Rule ID 586 //
        GIM_CheckFeatures, GIMT_Encode2(GIFBS_NotHasTrue16BitInsts),
        GIM_CheckRegBankForClass, /*MI*/0, /*Op*/0, /*RC*/GIMT_Encode2(AMDGPU::VGPR_32RegClassID),
        GIM_CheckComplexPattern, /*MI*/0, /*Op*/1, /*Renderer*/GIMT_Encode2(0), GIMT_Encode2(GICP_gi_vop3mods0),
        // (fpround:{ *:[f16] } (VOP3Mods0:{ *:[f32] } f32:{ *:[f32] }:$src0, i32:{ *:[i32] }:$src0_modifiers, i1:{ *:[i1] }:$clamp, i32:{ *:[i32] }:$omod))  =>  (V_CVT_F16_F32_e64:{ *:[f16] } i32:{ *:[i32] }:$src0_modifiers, f32:{ *:[f32] }:$src0, i1:{ *:[i1] }:$clamp, i32:{ *:[i32] }:$omod)
        GIR_BuildMI, /*InsnID*/0, /*Opcode*/GIMT_Encode2(AMDGPU::V_CVT_F16_F32_e64),
        GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/0, // DstI[vdst]
        GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/1, // src0_modifiers
        GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/0, // src0
        GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/2, // clamp
        GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/3, // omod
        GIR_ConstrainSelectedInstOperands, /*InsnID*/0,
        GIR_EraseFromParent, /*InsnID*/0,
        // GIR_Coverage, 586,
        GIR_Done,
      // Label 4173: @262736
      GIM_Try, /*On fail goto*//*Label 4174*/ GIMT_Encode4(262789), // Rule ID 588 //
        GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasTrue16BitInsts),
        GIM_CheckRegBankForClass, /*MI*/0, /*Op*/0, /*RC*/GIMT_Encode2(AMDGPU::VGPR_32RegClassID),
        GIM_CheckComplexPattern, /*MI*/0, /*Op*/1, /*Renderer*/GIMT_Encode2(0), GIMT_Encode2(GICP_gi_vop3mods0),
        // (fpround:{ *:[f16] } (VOP3Mods0:{ *:[f32] } f32:{ *:[f32] }:$src0, i32:{ *:[i32] }:$src0_modifiers, i1:{ *:[i1] }:$clamp, i32:{ *:[i32] }:$omod))  =>  (V_CVT_F16_F32_t16_e64:{ *:[f16] } i32:{ *:[i32] }:$src0_modifiers, f32:{ *:[f32] }:$src0, i1:{ *:[i1] }:$clamp, i32:{ *:[i32] }:$omod)
        GIR_BuildMI, /*InsnID*/0, /*Opcode*/GIMT_Encode2(AMDGPU::V_CVT_F16_F32_t16_e64),
        GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/0, // DstI[vdst]
        GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/1, // src0_modifiers
        GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/0, // src0
        GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/2, // clamp
        GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/3, // omod
        GIR_ConstrainSelectedInstOperands, /*InsnID*/0,
        GIR_EraseFromParent, /*InsnID*/0,
        // GIR_Coverage, 588,
        GIR_Done,
      // Label 4174: @262789
      GIM_Reject,
    // Label 4167: @262790
    GIM_Reject,
    // Label 4165: @262791
    GIM_Try, /*On fail goto*//*Label 4175*/ GIMT_Encode4(262845), // Rule ID 576 //
      GIM_CheckType, /*MI*/0, /*Op*/1, /*Type*/GILLT_s64,
      GIM_CheckRegBankForClass, /*MI*/0, /*Op*/0, /*RC*/GIMT_Encode2(AMDGPU::VGPR_32RegClassID),
      GIM_CheckComplexPattern, /*MI*/0, /*Op*/1, /*Renderer*/GIMT_Encode2(0), GIMT_Encode2(GICP_gi_vop3mods0),
      // (fpround:{ *:[f32] } (VOP3Mods0:{ *:[f64] } f64:{ *:[f64] }:$src0, i32:{ *:[i32] }:$src0_modifiers, i1:{ *:[i1] }:$clamp, i32:{ *:[i32] }:$omod))  =>  (V_CVT_F32_F64_e64:{ *:[f32] } i32:{ *:[i32] }:$src0_modifiers, f64:{ *:[f64] }:$src0, i1:{ *:[i1] }:$clamp, i32:{ *:[i32] }:$omod)
      GIR_BuildMI, /*InsnID*/0, /*Opcode*/GIMT_Encode2(AMDGPU::V_CVT_F32_F64_e64),
      GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/0, // DstI[vdst]
      GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/1, // src0_modifiers
      GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/0, // src0
      GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/2, // clamp
      GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/3, // omod
      GIR_ConstrainSelectedInstOperands, /*InsnID*/0,
      GIR_EraseFromParent, /*InsnID*/0,
      // GIR_Coverage, 576,
      GIR_Done,
    // Label 4175: @262845
    GIM_Reject,
    // Label 4166: @262846
    GIM_Reject,
    // Label 68: @262847
    GIM_SwitchType, /*MI*/0, /*Op*/0, /*[*/GIMT_Encode2(7), GIMT_Encode2(10), /*)*//*default:*//*Label 4179*/ GIMT_Encode4(263491),
    /*GILLT_s1*//*Label 4176*/ GIMT_Encode4(262870),
    /*GILLT_s16*//*Label 4177*/ GIMT_Encode4(263117),
    /*GILLT_s32*//*Label 4178*/ GIMT_Encode4(263229),
    // Label 4176: @262870
    GIM_Try, /*On fail goto*//*Label 4180*/ GIMT_Encode4(262933), // Rule ID 6347 //
      GIM_CheckFeatures, GIMT_Encode2(GIFBS_NotHasTrue16BitInsts),
      GIM_CheckType, /*MI*/0, /*Op*/1, /*Type*/GILLT_s16,
      GIM_CheckRegBankForClass, /*MI*/0, /*Op*/0, /*RC*/GIMT_Encode2(AMDGPU::SReg_1RegClassID),
      GIM_CheckComplexPattern, /*MI*/0, /*Op*/1, /*Renderer*/GIMT_Encode2(0), GIMT_Encode2(GICP_gi_vop3mods),
      // (fp_to_sint:{ *:[i1] } (VOP3Mods:{ *:[f16] } f16:{ *:[f16] }:$src0, i32:{ *:[i32] }:$src0_modifiers))  =>  (V_CMP_EQ_F16_e64:{ *:[i1] } 0:{ *:[i32] }, 48128:{ *:[i16] }, ?:{ *:[i32] }:$src0_modifiers, ?:{ *:[f16] }:$src0, 0:{ *:[i1] })
      GIR_BuildMI, /*InsnID*/0, /*Opcode*/GIMT_Encode2(AMDGPU::V_CMP_EQ_F16_e64),
      GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/0, // DstI[sdst]
      GIR_AddImm8, /*InsnID*/0, /*Imm*/0,
      GIR_AddImm, /*InsnID*/0, /*Imm*/GIMT_Encode8(48128),
      GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/1, // src0_modifiers
      GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/0, // src0
      GIR_AddImm8, /*InsnID*/0, /*Imm*/0,
      GIR_ConstrainSelectedInstOperands, /*InsnID*/0,
      GIR_EraseFromParent, /*InsnID*/0,
      // GIR_Coverage, 6347,
      GIR_Done,
    // Label 4180: @262933
    GIM_Try, /*On fail goto*//*Label 4181*/ GIMT_Encode4(262996), // Rule ID 6349 //
      GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasTrue16BitInsts),
      GIM_CheckType, /*MI*/0, /*Op*/1, /*Type*/GILLT_s16,
      GIM_CheckRegBankForClass, /*MI*/0, /*Op*/0, /*RC*/GIMT_Encode2(AMDGPU::SReg_1RegClassID),
      GIM_CheckComplexPattern, /*MI*/0, /*Op*/1, /*Renderer*/GIMT_Encode2(0), GIMT_Encode2(GICP_gi_vop3mods),
      // (fp_to_sint:{ *:[i1] } (VOP3Mods:{ *:[f16] } f16:{ *:[f16] }:$src0, i32:{ *:[i32] }:$src0_modifiers))  =>  (V_CMP_EQ_F16_t16_e64:{ *:[i1] } 0:{ *:[i32] }, 48128:{ *:[i16] }, ?:{ *:[i32] }:$src0_modifiers, ?:{ *:[f16] }:$src0, 0:{ *:[i1] })
      GIR_BuildMI, /*InsnID*/0, /*Opcode*/GIMT_Encode2(AMDGPU::V_CMP_EQ_F16_t16_e64),
      GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/0, // DstI[sdst]
      GIR_AddImm8, /*InsnID*/0, /*Imm*/0,
      GIR_AddImm, /*InsnID*/0, /*Imm*/GIMT_Encode8(48128),
      GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/1, // src0_modifiers
      GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/0, // src0
      GIR_AddImm8, /*InsnID*/0, /*Imm*/0,
      GIR_ConstrainSelectedInstOperands, /*InsnID*/0,
      GIR_EraseFromParent, /*InsnID*/0,
      // GIR_Coverage, 6349,
      GIR_Done,
    // Label 4181: @262996
    GIM_Try, /*On fail goto*//*Label 4182*/ GIMT_Encode4(263056), // Rule ID 6351 //
      GIM_CheckType, /*MI*/0, /*Op*/1, /*Type*/GILLT_s32,
      GIM_CheckRegBankForClass, /*MI*/0, /*Op*/0, /*RC*/GIMT_Encode2(AMDGPU::SReg_1RegClassID),
      GIM_CheckComplexPattern, /*MI*/0, /*Op*/1, /*Renderer*/GIMT_Encode2(0), GIMT_Encode2(GICP_gi_vop3mods),
      // (fp_to_sint:{ *:[i1] } (VOP3Mods:{ *:[f32] } f32:{ *:[f32] }:$src0, i32:{ *:[i32] }:$src0_modifiers))  =>  (V_CMP_EQ_F32_e64:{ *:[i1] } 0:{ *:[i32] }, 3212836864:{ *:[i32] }, ?:{ *:[i32] }:$src0_modifiers, ?:{ *:[f32] }:$src0, 0:{ *:[i1] })
      GIR_BuildMI, /*InsnID*/0, /*Opcode*/GIMT_Encode2(AMDGPU::V_CMP_EQ_F32_e64),
      GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/0, // DstI[sdst]
      GIR_AddImm8, /*InsnID*/0, /*Imm*/0,
      GIR_AddImm, /*InsnID*/0, /*Imm*/GIMT_Encode8(3212836864),
      GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/1, // src0_modifiers
      GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/0, // src0
      GIR_AddImm8, /*InsnID*/0, /*Imm*/0,
      GIR_ConstrainSelectedInstOperands, /*InsnID*/0,
      GIR_EraseFromParent, /*InsnID*/0,
      // GIR_Coverage, 6351,
      GIR_Done,
    // Label 4182: @263056
    GIM_Try, /*On fail goto*//*Label 4183*/ GIMT_Encode4(263116), // Rule ID 6353 //
      GIM_CheckType, /*MI*/0, /*Op*/1, /*Type*/GILLT_s64,
      GIM_CheckRegBankForClass, /*MI*/0, /*Op*/0, /*RC*/GIMT_Encode2(AMDGPU::SReg_1RegClassID),
      GIM_CheckComplexPattern, /*MI*/0, /*Op*/1, /*Renderer*/GIMT_Encode2(0), GIMT_Encode2(GICP_gi_vop3mods),
      // (fp_to_sint:{ *:[i1] } (VOP3Mods:{ *:[f64] } f64:{ *:[f64] }:$src0, i32:{ *:[i32] }:$src0_modifiers))  =>  (V_CMP_EQ_F64_e64:{ *:[i1] } 0:{ *:[i32] }, -4616189618054758400:{ *:[i64] }, ?:{ *:[i32] }:$src0_modifiers, ?:{ *:[f64] }:$src0, 0:{ *:[i1] })
      GIR_BuildMI, /*InsnID*/0, /*Opcode*/GIMT_Encode2(AMDGPU::V_CMP_EQ_F64_e64),
      GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/0, // DstI[sdst]
      GIR_AddImm8, /*InsnID*/0, /*Imm*/0,
      GIR_AddImm, /*InsnID*/0, /*Imm*/GIMT_Encode8(-4616189618054758400),
      GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/1, // src0_modifiers
      GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/0, // src0
      GIR_AddImm8, /*InsnID*/0, /*Imm*/0,
      GIR_ConstrainSelectedInstOperands, /*InsnID*/0,
      GIR_EraseFromParent, /*InsnID*/0,
      // GIR_Coverage, 6353,
      GIR_Done,
    // Label 4183: @263116
    GIM_Reject,
    // Label 4177: @263117
    GIM_Try, /*On fail goto*//*Label 4184*/ GIMT_Encode4(263228),
      GIM_CheckType, /*MI*/0, /*Op*/1, /*Type*/GILLT_s16,
      GIM_CheckRegBankForClass, /*MI*/0, /*Op*/0, /*RC*/GIMT_Encode2(AMDGPU::VGPR_32RegClassID),
      GIM_Try, /*On fail goto*//*Label 4185*/ GIMT_Encode4(263179), // Rule ID 654 //
        GIM_CheckFeatures, GIMT_Encode2(GIFBS_Has16BitInsts_NotHasTrue16BitInsts),
        GIM_CheckComplexPattern, /*MI*/0, /*Op*/1, /*Renderer*/GIMT_Encode2(0), GIMT_Encode2(GICP_gi_vop3mods0),
        // (fp_to_sint:{ *:[i16] } (VOP3Mods0:{ *:[f16] } f16:{ *:[f16] }:$src0, i32:{ *:[i32] }:$src0_modifiers, i1:{ *:[i1] }:$clamp, i32:{ *:[i32] }:$omod))  =>  (V_CVT_I16_F16_e64:{ *:[i16] } i32:{ *:[i32] }:$src0_modifiers, f16:{ *:[f16] }:$src0, i1:{ *:[i1] }:$clamp, i32:{ *:[i32] }:$omod)
        GIR_BuildMI, /*InsnID*/0, /*Opcode*/GIMT_Encode2(AMDGPU::V_CVT_I16_F16_e64),
        GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/0, // DstI[vdst]
        GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/1, // src0_modifiers
        GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/0, // src0
        GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/2, // clamp
        GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/3, // omod
        GIR_ConstrainSelectedInstOperands, /*InsnID*/0,
        GIR_EraseFromParent, /*InsnID*/0,
        // GIR_Coverage, 654,
        GIR_Done,
      // Label 4185: @263179
      GIM_Try, /*On fail goto*//*Label 4186*/ GIMT_Encode4(263227), // Rule ID 656 //
        GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasTrue16BitInsts),
        GIM_CheckComplexPattern, /*MI*/0, /*Op*/1, /*Renderer*/GIMT_Encode2(0), GIMT_Encode2(GICP_gi_vop3mods0),
        // (fp_to_sint:{ *:[i16] } (VOP3Mods0:{ *:[f16] } f16:{ *:[f16] }:$src0, i32:{ *:[i32] }:$src0_modifiers, i1:{ *:[i1] }:$clamp, i32:{ *:[i32] }:$omod))  =>  (V_CVT_I16_F16_t16_e64:{ *:[i16] } i32:{ *:[i32] }:$src0_modifiers, f16:{ *:[f16] }:$src0, i1:{ *:[i1] }:$clamp, i32:{ *:[i32] }:$omod)
        GIR_BuildMI, /*InsnID*/0, /*Opcode*/GIMT_Encode2(AMDGPU::V_CVT_I16_F16_t16_e64),
        GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/0, // DstI[vdst]
        GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/1, // src0_modifiers
        GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/0, // src0
        GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/2, // clamp
        GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/3, // omod
        GIR_ConstrainSelectedInstOperands, /*InsnID*/0,
        GIR_EraseFromParent, /*InsnID*/0,
        // GIR_Coverage, 656,
        GIR_Done,
      // Label 4186: @263227
      GIM_Reject,
    // Label 4184: @263228
    GIM_Reject,
    // Label 4178: @263229
    GIM_Try, /*On fail goto*//*Label 4187*/ GIMT_Encode4(263262), // Rule ID 29 //
      GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasSALUFloatInsts),
      GIM_CheckType, /*MI*/0, /*Op*/1, /*Type*/GILLT_s32,
      GIM_CheckRegBankForClass, /*MI*/0, /*Op*/0, /*RC*/GIMT_Encode2(AMDGPU::SReg_32RegClassID),
      GIM_CheckCxxInsnPredicate, /*MI*/0, /*FnId*/GIMT_Encode2(GICXXPred_MI_Predicate_anonymous_17595),
      // (fp_to_sint:{ *:[i32] } f32:{ *:[f32] }:$src0)<<P:Predicate_anonymous_17595>>  =>  (S_CVT_I32_F32:{ *:[i32] } f32:{ *:[f32] }:$src0)
      GIR_MutateOpcode, /*InsnID*/0, /*RecycleInsnID*/0, /*Opcode*/GIMT_Encode2(AMDGPU::S_CVT_I32_F32),
      GIR_AddImplicitUse, /*InsnID*/0, GIMT_Encode2(AMDGPU::MODE),
      GIR_ConstrainSelectedInstOperands, /*InsnID*/0,
      // GIR_Coverage, 29,
      GIR_Done,
    // Label 4187: @263262
    GIM_Try, /*On fail goto*//*Label 4188*/ GIMT_Encode4(263322), // Rule ID 5867 //
      GIM_CheckFeatures, GIMT_Encode2(GIFBS_NotHasTrue16BitInsts),
      GIM_CheckType, /*MI*/0, /*Op*/1, /*Type*/GILLT_s16,
      GIM_CheckRegBankForClass, /*MI*/0, /*Op*/0, /*RC*/GIMT_Encode2(AMDGPU::VGPR_32RegClassID),
      // (fp_to_sint:{ *:[i32] } f16:{ *:[f16] }:$src)  =>  (V_CVT_I32_F32_e32:{ *:[i32] } (V_CVT_F32_F16_e64:{ *:[i16] } 0:{ *:[i32] }, VSrc_b32:{ *:[f16] }:$src))
      GIR_MakeTempReg, /*TempRegID*/0, /*TypeID*/GILLT_s16,
      GIR_BuildMI, /*InsnID*/1, /*Opcode*/GIMT_Encode2(AMDGPU::V_CVT_F32_F16_e64),
      GIR_AddTempRegister, /*InsnID*/1, /*TempRegID*/0, /*TempRegFlags*/GIMT_Encode2(RegState::Define),
      GIR_AddImm8, /*InsnID*/1, /*Imm*/0,
      GIR_Copy, /*NewInsnID*/1, /*OldInsnID*/0, /*OpIdx*/1, // src
      GIR_AddImm8, /*InsnID*/1, /*Imm*/0,
      GIR_AddImm8, /*InsnID*/1, /*Imm*/0,
      GIR_ConstrainSelectedInstOperands, /*InsnID*/1,
      GIR_BuildMI, /*InsnID*/0, /*Opcode*/GIMT_Encode2(AMDGPU::V_CVT_I32_F32_e32),
      GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/0, // DstI[vdst]
      GIR_AddSimpleTempRegister, /*InsnID*/0, /*TempRegID*/0,
      GIR_ConstrainSelectedInstOperands, /*InsnID*/0,
      GIR_EraseFromParent, /*InsnID*/0,
      // GIR_Coverage, 5867,
      GIR_Done,
    // Label 4188: @263322
    GIM_Try, /*On fail goto*//*Label 4189*/ GIMT_Encode4(263382), // Rule ID 5881 //
      GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasTrue16BitInsts),
      GIM_CheckType, /*MI*/0, /*Op*/1, /*Type*/GILLT_s16,
      GIM_CheckRegBankForClass, /*MI*/0, /*Op*/0, /*RC*/GIMT_Encode2(AMDGPU::VGPR_32RegClassID),
      // (fp_to_sint:{ *:[i32] } f16:{ *:[f16] }:$src)  =>  (V_CVT_I32_F32_e32:{ *:[i32] } (V_CVT_F32_F16_t16_e64:{ *:[i16] } 0:{ *:[i32] }, VSrc_b32:{ *:[f16] }:$src))
      GIR_MakeTempReg, /*TempRegID*/0, /*TypeID*/GILLT_s16,
      GIR_BuildMI, /*InsnID*/1, /*Opcode*/GIMT_Encode2(AMDGPU::V_CVT_F32_F16_t16_e64),
      GIR_AddTempRegister, /*InsnID*/1, /*TempRegID*/0, /*TempRegFlags*/GIMT_Encode2(RegState::Define),
      GIR_AddImm8, /*InsnID*/1, /*Imm*/0,
      GIR_Copy, /*NewInsnID*/1, /*OldInsnID*/0, /*OpIdx*/1, // src
      GIR_AddImm8, /*InsnID*/1, /*Imm*/0,
      GIR_AddImm8, /*InsnID*/1, /*Imm*/0,
      GIR_ConstrainSelectedInstOperands, /*InsnID*/1,
      GIR_BuildMI, /*InsnID*/0, /*Opcode*/GIMT_Encode2(AMDGPU::V_CVT_I32_F32_e32),
      GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/0, // DstI[vdst]
      GIR_AddSimpleTempRegister, /*InsnID*/0, /*TempRegID*/0,
      GIR_ConstrainSelectedInstOperands, /*InsnID*/0,
      GIR_EraseFromParent, /*InsnID*/0,
      // GIR_Coverage, 5881,
      GIR_Done,
    // Label 4189: @263382
    GIM_Try, /*On fail goto*//*Label 4190*/ GIMT_Encode4(263436), // Rule ID 574 //
      GIM_CheckType, /*MI*/0, /*Op*/1, /*Type*/GILLT_s64,
      GIM_CheckRegBankForClass, /*MI*/0, /*Op*/0, /*RC*/GIMT_Encode2(AMDGPU::VGPR_32RegClassID),
      GIM_CheckComplexPattern, /*MI*/0, /*Op*/1, /*Renderer*/GIMT_Encode2(0), GIMT_Encode2(GICP_gi_vop3mods0),
      // (fp_to_sint:{ *:[i32] } (VOP3Mods0:{ *:[f64] } f64:{ *:[f64] }:$src0, i32:{ *:[i32] }:$src0_modifiers, i1:{ *:[i1] }:$clamp, i32:{ *:[i32] }:$omod))  =>  (V_CVT_I32_F64_e64:{ *:[i32] } i32:{ *:[i32] }:$src0_modifiers, f64:{ *:[f64] }:$src0, i1:{ *:[i1] }:$clamp, i32:{ *:[i32] }:$omod)
      GIR_BuildMI, /*InsnID*/0, /*Opcode*/GIMT_Encode2(AMDGPU::V_CVT_I32_F64_e64),
      GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/0, // DstI[vdst]
      GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/1, // src0_modifiers
      GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/0, // src0
      GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/2, // clamp
      GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/3, // omod
      GIR_ConstrainSelectedInstOperands, /*InsnID*/0,
      GIR_EraseFromParent, /*InsnID*/0,
      // GIR_Coverage, 574,
      GIR_Done,
    // Label 4190: @263436
    GIM_Try, /*On fail goto*//*Label 4191*/ GIMT_Encode4(263490), // Rule ID 584 //
      GIM_CheckType, /*MI*/0, /*Op*/1, /*Type*/GILLT_s32,
      GIM_CheckRegBankForClass, /*MI*/0, /*Op*/0, /*RC*/GIMT_Encode2(AMDGPU::VGPR_32RegClassID),
      GIM_CheckComplexPattern, /*MI*/0, /*Op*/1, /*Renderer*/GIMT_Encode2(0), GIMT_Encode2(GICP_gi_vop3mods0),
      // (fp_to_sint:{ *:[i32] } (VOP3Mods0:{ *:[f32] } f32:{ *:[f32] }:$src0, i32:{ *:[i32] }:$src0_modifiers, i1:{ *:[i1] }:$clamp, i32:{ *:[i32] }:$omod))  =>  (V_CVT_I32_F32_e64:{ *:[i32] } i32:{ *:[i32] }:$src0_modifiers, f32:{ *:[f32] }:$src0, i1:{ *:[i1] }:$clamp, i32:{ *:[i32] }:$omod)
      GIR_BuildMI, /*InsnID*/0, /*Opcode*/GIMT_Encode2(AMDGPU::V_CVT_I32_F32_e64),
      GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/0, // DstI[vdst]
      GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/1, // src0_modifiers
      GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/0, // src0
      GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/2, // clamp
      GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/3, // omod
      GIR_ConstrainSelectedInstOperands, /*InsnID*/0,
      GIR_EraseFromParent, /*InsnID*/0,
      // GIR_Coverage, 584,
      GIR_Done,
    // Label 4191: @263490
    GIM_Reject,
    // Label 4179: @263491
    GIM_Reject,
    // Label 69: @263492
    GIM_SwitchType, /*MI*/0, /*Op*/0, /*[*/GIMT_Encode2(7), GIMT_Encode2(10), /*)*//*default:*//*Label 4195*/ GIMT_Encode4(264136),
    /*GILLT_s1*//*Label 4192*/ GIMT_Encode4(263515),
    /*GILLT_s16*//*Label 4193*/ GIMT_Encode4(263762),
    /*GILLT_s32*//*Label 4194*/ GIMT_Encode4(263874),
    // Label 4192: @263515
    GIM_Try, /*On fail goto*//*Label 4196*/ GIMT_Encode4(263578), // Rule ID 6346 //
      GIM_CheckFeatures, GIMT_Encode2(GIFBS_NotHasTrue16BitInsts),
      GIM_CheckType, /*MI*/0, /*Op*/1, /*Type*/GILLT_s16,
      GIM_CheckRegBankForClass, /*MI*/0, /*Op*/0, /*RC*/GIMT_Encode2(AMDGPU::SReg_1RegClassID),
      GIM_CheckComplexPattern, /*MI*/0, /*Op*/1, /*Renderer*/GIMT_Encode2(0), GIMT_Encode2(GICP_gi_vop3mods),
      // (fp_to_uint:{ *:[i1] } (VOP3Mods:{ *:[f16] } f16:{ *:[f16] }:$src0, i32:{ *:[i32] }:$src0_modifiers))  =>  (V_CMP_EQ_F16_e64:{ *:[i1] } 0:{ *:[i32] }, 15360:{ *:[i16] }, ?:{ *:[i32] }:$src0_modifiers, ?:{ *:[f16] }:$src0, 0:{ *:[i1] })
      GIR_BuildMI, /*InsnID*/0, /*Opcode*/GIMT_Encode2(AMDGPU::V_CMP_EQ_F16_e64),
      GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/0, // DstI[sdst]
      GIR_AddImm8, /*InsnID*/0, /*Imm*/0,
      GIR_AddImm, /*InsnID*/0, /*Imm*/GIMT_Encode8(15360),
      GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/1, // src0_modifiers
      GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/0, // src0
      GIR_AddImm8, /*InsnID*/0, /*Imm*/0,
      GIR_ConstrainSelectedInstOperands, /*InsnID*/0,
      GIR_EraseFromParent, /*InsnID*/0,
      // GIR_Coverage, 6346,
      GIR_Done,
    // Label 4196: @263578
    GIM_Try, /*On fail goto*//*Label 4197*/ GIMT_Encode4(263641), // Rule ID 6348 //
      GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasTrue16BitInsts),
      GIM_CheckType, /*MI*/0, /*Op*/1, /*Type*/GILLT_s16,
      GIM_CheckRegBankForClass, /*MI*/0, /*Op*/0, /*RC*/GIMT_Encode2(AMDGPU::SReg_1RegClassID),
      GIM_CheckComplexPattern, /*MI*/0, /*Op*/1, /*Renderer*/GIMT_Encode2(0), GIMT_Encode2(GICP_gi_vop3mods),
      // (fp_to_uint:{ *:[i1] } (VOP3Mods:{ *:[f16] } f16:{ *:[f16] }:$src0, i32:{ *:[i32] }:$src0_modifiers))  =>  (V_CMP_EQ_F16_t16_e64:{ *:[i1] } 0:{ *:[i32] }, 15360:{ *:[i16] }, ?:{ *:[i32] }:$src0_modifiers, ?:{ *:[f16] }:$src0, 0:{ *:[i1] })
      GIR_BuildMI, /*InsnID*/0, /*Opcode*/GIMT_Encode2(AMDGPU::V_CMP_EQ_F16_t16_e64),
      GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/0, // DstI[sdst]
      GIR_AddImm8, /*InsnID*/0, /*Imm*/0,
      GIR_AddImm, /*InsnID*/0, /*Imm*/GIMT_Encode8(15360),
      GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/1, // src0_modifiers
      GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/0, // src0
      GIR_AddImm8, /*InsnID*/0, /*Imm*/0,
      GIR_ConstrainSelectedInstOperands, /*InsnID*/0,
      GIR_EraseFromParent, /*InsnID*/0,
      // GIR_Coverage, 6348,
      GIR_Done,
    // Label 4197: @263641
    GIM_Try, /*On fail goto*//*Label 4198*/ GIMT_Encode4(263701), // Rule ID 6350 //
      GIM_CheckType, /*MI*/0, /*Op*/1, /*Type*/GILLT_s32,
      GIM_CheckRegBankForClass, /*MI*/0, /*Op*/0, /*RC*/GIMT_Encode2(AMDGPU::SReg_1RegClassID),
      GIM_CheckComplexPattern, /*MI*/0, /*Op*/1, /*Renderer*/GIMT_Encode2(0), GIMT_Encode2(GICP_gi_vop3mods),
      // (fp_to_uint:{ *:[i1] } (VOP3Mods:{ *:[f32] } f32:{ *:[f32] }:$src0, i32:{ *:[i32] }:$src0_modifiers))  =>  (V_CMP_EQ_F32_e64:{ *:[i1] } 0:{ *:[i32] }, 1065353216:{ *:[i32] }, ?:{ *:[i32] }:$src0_modifiers, ?:{ *:[f32] }:$src0, 0:{ *:[i1] })
      GIR_BuildMI, /*InsnID*/0, /*Opcode*/GIMT_Encode2(AMDGPU::V_CMP_EQ_F32_e64),
      GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/0, // DstI[sdst]
      GIR_AddImm8, /*InsnID*/0, /*Imm*/0,
      GIR_AddImm, /*InsnID*/0, /*Imm*/GIMT_Encode8(1065353216),
      GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/1, // src0_modifiers
      GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/0, // src0
      GIR_AddImm8, /*InsnID*/0, /*Imm*/0,
      GIR_ConstrainSelectedInstOperands, /*InsnID*/0,
      GIR_EraseFromParent, /*InsnID*/0,
      // GIR_Coverage, 6350,
      GIR_Done,
    // Label 4198: @263701
    GIM_Try, /*On fail goto*//*Label 4199*/ GIMT_Encode4(263761), // Rule ID 6352 //
      GIM_CheckType, /*MI*/0, /*Op*/1, /*Type*/GILLT_s64,
      GIM_CheckRegBankForClass, /*MI*/0, /*Op*/0, /*RC*/GIMT_Encode2(AMDGPU::SReg_1RegClassID),
      GIM_CheckComplexPattern, /*MI*/0, /*Op*/1, /*Renderer*/GIMT_Encode2(0), GIMT_Encode2(GICP_gi_vop3mods),
      // (fp_to_uint:{ *:[i1] } (VOP3Mods:{ *:[f64] } f64:{ *:[f64] }:$src0, i32:{ *:[i32] }:$src0_modifiers))  =>  (V_CMP_EQ_F64_e64:{ *:[i1] } 0:{ *:[i32] }, 4607182418800017408:{ *:[i64] }, ?:{ *:[i32] }:$src0_modifiers, ?:{ *:[f64] }:$src0, 0:{ *:[i1] })
      GIR_BuildMI, /*InsnID*/0, /*Opcode*/GIMT_Encode2(AMDGPU::V_CMP_EQ_F64_e64),
      GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/0, // DstI[sdst]
      GIR_AddImm8, /*InsnID*/0, /*Imm*/0,
      GIR_AddImm, /*InsnID*/0, /*Imm*/GIMT_Encode8(4607182418800017408),
      GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/1, // src0_modifiers
      GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/0, // src0
      GIR_AddImm8, /*InsnID*/0, /*Imm*/0,
      GIR_ConstrainSelectedInstOperands, /*InsnID*/0,
      GIR_EraseFromParent, /*InsnID*/0,
      // GIR_Coverage, 6352,
      GIR_Done,
    // Label 4199: @263761
    GIM_Reject,
    // Label 4193: @263762
    GIM_Try, /*On fail goto*//*Label 4200*/ GIMT_Encode4(263873),
      GIM_CheckType, /*MI*/0, /*Op*/1, /*Type*/GILLT_s16,
      GIM_CheckRegBankForClass, /*MI*/0, /*Op*/0, /*RC*/GIMT_Encode2(AMDGPU::VGPR_32RegClassID),
      GIM_Try, /*On fail goto*//*Label 4201*/ GIMT_Encode4(263824), // Rule ID 653 //
        GIM_CheckFeatures, GIMT_Encode2(GIFBS_Has16BitInsts_NotHasTrue16BitInsts),
        GIM_CheckComplexPattern, /*MI*/0, /*Op*/1, /*Renderer*/GIMT_Encode2(0), GIMT_Encode2(GICP_gi_vop3mods0),
        // (fp_to_uint:{ *:[i16] } (VOP3Mods0:{ *:[f16] } f16:{ *:[f16] }:$src0, i32:{ *:[i32] }:$src0_modifiers, i1:{ *:[i1] }:$clamp, i32:{ *:[i32] }:$omod))  =>  (V_CVT_U16_F16_e64:{ *:[i16] } i32:{ *:[i32] }:$src0_modifiers, f16:{ *:[f16] }:$src0, i1:{ *:[i1] }:$clamp, i32:{ *:[i32] }:$omod)
        GIR_BuildMI, /*InsnID*/0, /*Opcode*/GIMT_Encode2(AMDGPU::V_CVT_U16_F16_e64),
        GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/0, // DstI[vdst]
        GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/1, // src0_modifiers
        GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/0, // src0
        GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/2, // clamp
        GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/3, // omod
        GIR_ConstrainSelectedInstOperands, /*InsnID*/0,
        GIR_EraseFromParent, /*InsnID*/0,
        // GIR_Coverage, 653,
        GIR_Done,
      // Label 4201: @263824
      GIM_Try, /*On fail goto*//*Label 4202*/ GIMT_Encode4(263872), // Rule ID 655 //
        GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasTrue16BitInsts),
        GIM_CheckComplexPattern, /*MI*/0, /*Op*/1, /*Renderer*/GIMT_Encode2(0), GIMT_Encode2(GICP_gi_vop3mods0),
        // (fp_to_uint:{ *:[i16] } (VOP3Mods0:{ *:[f16] } f16:{ *:[f16] }:$src0, i32:{ *:[i32] }:$src0_modifiers, i1:{ *:[i1] }:$clamp, i32:{ *:[i32] }:$omod))  =>  (V_CVT_U16_F16_t16_e64:{ *:[i16] } i32:{ *:[i32] }:$src0_modifiers, f16:{ *:[f16] }:$src0, i1:{ *:[i1] }:$clamp, i32:{ *:[i32] }:$omod)
        GIR_BuildMI, /*InsnID*/0, /*Opcode*/GIMT_Encode2(AMDGPU::V_CVT_U16_F16_t16_e64),
        GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/0, // DstI[vdst]
        GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/1, // src0_modifiers
        GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/0, // src0
        GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/2, // clamp
        GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/3, // omod
        GIR_ConstrainSelectedInstOperands, /*InsnID*/0,
        GIR_EraseFromParent, /*InsnID*/0,
        // GIR_Coverage, 655,
        GIR_Done,
      // Label 4202: @263872
      GIM_Reject,
    // Label 4200: @263873
    GIM_Reject,
    // Label 4194: @263874
    GIM_Try, /*On fail goto*//*Label 4203*/ GIMT_Encode4(263907), // Rule ID 30 //
      GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasSALUFloatInsts),
      GIM_CheckType, /*MI*/0, /*Op*/1, /*Type*/GILLT_s32,
      GIM_CheckRegBankForClass, /*MI*/0, /*Op*/0, /*RC*/GIMT_Encode2(AMDGPU::SReg_32RegClassID),
      GIM_CheckCxxInsnPredicate, /*MI*/0, /*FnId*/GIMT_Encode2(GICXXPred_MI_Predicate_anonymous_17596),
      // (fp_to_uint:{ *:[i32] } f32:{ *:[f32] }:$src0)<<P:Predicate_anonymous_17596>>  =>  (S_CVT_U32_F32:{ *:[i32] } f32:{ *:[f32] }:$src0)
      GIR_MutateOpcode, /*InsnID*/0, /*RecycleInsnID*/0, /*Opcode*/GIMT_Encode2(AMDGPU::S_CVT_U32_F32),
      GIR_AddImplicitUse, /*InsnID*/0, GIMT_Encode2(AMDGPU::MODE),
      GIR_ConstrainSelectedInstOperands, /*InsnID*/0,
      // GIR_Coverage, 30,
      GIR_Done,
    // Label 4203: @263907
    GIM_Try, /*On fail goto*//*Label 4204*/ GIMT_Encode4(263967), // Rule ID 5868 //
      GIM_CheckFeatures, GIMT_Encode2(GIFBS_NotHasTrue16BitInsts),
      GIM_CheckType, /*MI*/0, /*Op*/1, /*Type*/GILLT_s16,
      GIM_CheckRegBankForClass, /*MI*/0, /*Op*/0, /*RC*/GIMT_Encode2(AMDGPU::VGPR_32RegClassID),
      // (fp_to_uint:{ *:[i32] } f16:{ *:[f16] }:$src)  =>  (V_CVT_U32_F32_e32:{ *:[i32] } (V_CVT_F32_F16_e64:{ *:[i16] } 0:{ *:[i32] }, VSrc_b32:{ *:[f16] }:$src))
      GIR_MakeTempReg, /*TempRegID*/0, /*TypeID*/GILLT_s16,
      GIR_BuildMI, /*InsnID*/1, /*Opcode*/GIMT_Encode2(AMDGPU::V_CVT_F32_F16_e64),
      GIR_AddTempRegister, /*InsnID*/1, /*TempRegID*/0, /*TempRegFlags*/GIMT_Encode2(RegState::Define),
      GIR_AddImm8, /*InsnID*/1, /*Imm*/0,
      GIR_Copy, /*NewInsnID*/1, /*OldInsnID*/0, /*OpIdx*/1, // src
      GIR_AddImm8, /*InsnID*/1, /*Imm*/0,
      GIR_AddImm8, /*InsnID*/1, /*Imm*/0,
      GIR_ConstrainSelectedInstOperands, /*InsnID*/1,
      GIR_BuildMI, /*InsnID*/0, /*Opcode*/GIMT_Encode2(AMDGPU::V_CVT_U32_F32_e32),
      GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/0, // DstI[vdst]
      GIR_AddSimpleTempRegister, /*InsnID*/0, /*TempRegID*/0,
      GIR_ConstrainSelectedInstOperands, /*InsnID*/0,
      GIR_EraseFromParent, /*InsnID*/0,
      // GIR_Coverage, 5868,
      GIR_Done,
    // Label 4204: @263967
    GIM_Try, /*On fail goto*//*Label 4205*/ GIMT_Encode4(264027), // Rule ID 5882 //
      GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasTrue16BitInsts),
      GIM_CheckType, /*MI*/0, /*Op*/1, /*Type*/GILLT_s16,
      GIM_CheckRegBankForClass, /*MI*/0, /*Op*/0, /*RC*/GIMT_Encode2(AMDGPU::VGPR_32RegClassID),
      // (fp_to_uint:{ *:[i32] } f16:{ *:[f16] }:$src)  =>  (V_CVT_U32_F32_e32:{ *:[i32] } (V_CVT_F32_F16_t16_e64:{ *:[i16] } 0:{ *:[i32] }, VSrc_b32:{ *:[f16] }:$src))
      GIR_MakeTempReg, /*TempRegID*/0, /*TypeID*/GILLT_s16,
      GIR_BuildMI, /*InsnID*/1, /*Opcode*/GIMT_Encode2(AMDGPU::V_CVT_F32_F16_t16_e64),
      GIR_AddTempRegister, /*InsnID*/1, /*TempRegID*/0, /*TempRegFlags*/GIMT_Encode2(RegState::Define),
      GIR_AddImm8, /*InsnID*/1, /*Imm*/0,
      GIR_Copy, /*NewInsnID*/1, /*OldInsnID*/0, /*OpIdx*/1, // src
      GIR_AddImm8, /*InsnID*/1, /*Imm*/0,
      GIR_AddImm8, /*InsnID*/1, /*Imm*/0,
      GIR_ConstrainSelectedInstOperands, /*InsnID*/1,
      GIR_BuildMI, /*InsnID*/0, /*Opcode*/GIMT_Encode2(AMDGPU::V_CVT_U32_F32_e32),
      GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/0, // DstI[vdst]
      GIR_AddSimpleTempRegister, /*InsnID*/0, /*TempRegID*/0,
      GIR_ConstrainSelectedInstOperands, /*InsnID*/0,
      GIR_EraseFromParent, /*InsnID*/0,
      // GIR_Coverage, 5882,
      GIR_Done,
    // Label 4205: @264027
    GIM_Try, /*On fail goto*//*Label 4206*/ GIMT_Encode4(264081), // Rule ID 579 //
      GIM_CheckType, /*MI*/0, /*Op*/1, /*Type*/GILLT_s64,
      GIM_CheckRegBankForClass, /*MI*/0, /*Op*/0, /*RC*/GIMT_Encode2(AMDGPU::VGPR_32RegClassID),
      GIM_CheckComplexPattern, /*MI*/0, /*Op*/1, /*Renderer*/GIMT_Encode2(0), GIMT_Encode2(GICP_gi_vop3mods0),
      // (fp_to_uint:{ *:[i32] } (VOP3Mods0:{ *:[f64] } f64:{ *:[f64] }:$src0, i32:{ *:[i32] }:$src0_modifiers, i1:{ *:[i1] }:$clamp, i32:{ *:[i32] }:$omod))  =>  (V_CVT_U32_F64_e64:{ *:[i32] } i32:{ *:[i32] }:$src0_modifiers, f64:{ *:[f64] }:$src0, i1:{ *:[i1] }:$clamp, i32:{ *:[i32] }:$omod)
      GIR_BuildMI, /*InsnID*/0, /*Opcode*/GIMT_Encode2(AMDGPU::V_CVT_U32_F64_e64),
      GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/0, // DstI[vdst]
      GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/1, // src0_modifiers
      GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/0, // src0
      GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/2, // clamp
      GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/3, // omod
      GIR_ConstrainSelectedInstOperands, /*InsnID*/0,
      GIR_EraseFromParent, /*InsnID*/0,
      // GIR_Coverage, 579,
      GIR_Done,
    // Label 4206: @264081
    GIM_Try, /*On fail goto*//*Label 4207*/ GIMT_Encode4(264135), // Rule ID 583 //
      GIM_CheckType, /*MI*/0, /*Op*/1, /*Type*/GILLT_s32,
      GIM_CheckRegBankForClass, /*MI*/0, /*Op*/0, /*RC*/GIMT_Encode2(AMDGPU::VGPR_32RegClassID),
      GIM_CheckComplexPattern, /*MI*/0, /*Op*/1, /*Renderer*/GIMT_Encode2(0), GIMT_Encode2(GICP_gi_vop3mods0),
      // (fp_to_uint:{ *:[i32] } (VOP3Mods0:{ *:[f32] } f32:{ *:[f32] }:$src0, i32:{ *:[i32] }:$src0_modifiers, i1:{ *:[i1] }:$clamp, i32:{ *:[i32] }:$omod))  =>  (V_CVT_U32_F32_e64:{ *:[i32] } i32:{ *:[i32] }:$src0_modifiers, f32:{ *:[f32] }:$src0, i1:{ *:[i1] }:$clamp, i32:{ *:[i32] }:$omod)
      GIR_BuildMI, /*InsnID*/0, /*Opcode*/GIMT_Encode2(AMDGPU::V_CVT_U32_F32_e64),
      GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/0, // DstI[vdst]
      GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/1, // src0_modifiers
      GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/0, // src0
      GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/2, // clamp
      GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/3, // omod
      GIR_ConstrainSelectedInstOperands, /*InsnID*/0,
      GIR_EraseFromParent, /*InsnID*/0,
      // GIR_Coverage, 583,
      GIR_Done,
    // Label 4207: @264135
    GIM_Reject,
    // Label 4195: @264136
    GIM_Reject,
    // Label 70: @264137
    GIM_SwitchType, /*MI*/0, /*Op*/0, /*[*/GIMT_Encode2(8), GIMT_Encode2(11), /*)*//*default:*//*Label 4211*/ GIMT_Encode4(264768),
    /*GILLT_s16*//*Label 4208*/ GIMT_Encode4(264160),
    /*GILLT_s32*//*Label 4209*/ GIMT_Encode4(264525),
    /*GILLT_s64*//*Label 4210*/ GIMT_Encode4(264658),
    // Label 4208: @264160
    GIM_Try, /*On fail goto*//*Label 4212*/ GIMT_Encode4(264220), // Rule ID 5869 //
      GIM_CheckFeatures, GIMT_Encode2(GIFBS_NotHasTrue16BitInsts),
      GIM_CheckType, /*MI*/0, /*Op*/1, /*Type*/GILLT_s32,
      GIM_CheckRegBankForClass, /*MI*/0, /*Op*/0, /*RC*/GIMT_Encode2(AMDGPU::VGPR_32RegClassID),
      // (sint_to_fp:{ *:[f16] } i32:{ *:[i32] }:$src)  =>  (V_CVT_F16_F32_e64:{ *:[f16] } 0:{ *:[i32] }, (V_CVT_F32_I32_e32:{ *:[i16] } VSrc_b32:{ *:[i32] }:$src))
      GIR_MakeTempReg, /*TempRegID*/0, /*TypeID*/GILLT_s16,
      GIR_BuildMI, /*InsnID*/1, /*Opcode*/GIMT_Encode2(AMDGPU::V_CVT_F32_I32_e32),
      GIR_AddTempRegister, /*InsnID*/1, /*TempRegID*/0, /*TempRegFlags*/GIMT_Encode2(RegState::Define),
      GIR_Copy, /*NewInsnID*/1, /*OldInsnID*/0, /*OpIdx*/1, // src
      GIR_ConstrainSelectedInstOperands, /*InsnID*/1,
      GIR_BuildMI, /*InsnID*/0, /*Opcode*/GIMT_Encode2(AMDGPU::V_CVT_F16_F32_e64),
      GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/0, // DstI[vdst]
      GIR_AddImm8, /*InsnID*/0, /*Imm*/0,
      GIR_AddSimpleTempRegister, /*InsnID*/0, /*TempRegID*/0,
      GIR_AddImm8, /*InsnID*/0, /*Imm*/0,
      GIR_AddImm8, /*InsnID*/0, /*Imm*/0,
      GIR_ConstrainSelectedInstOperands, /*InsnID*/0,
      GIR_EraseFromParent, /*InsnID*/0,
      // GIR_Coverage, 5869,
      GIR_Done,
    // Label 4212: @264220
    GIM_Try, /*On fail goto*//*Label 4213*/ GIMT_Encode4(264280), // Rule ID 5883 //
      GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasTrue16BitInsts),
      GIM_CheckType, /*MI*/0, /*Op*/1, /*Type*/GILLT_s32,
      GIM_CheckRegBankForClass, /*MI*/0, /*Op*/0, /*RC*/GIMT_Encode2(AMDGPU::VGPR_32RegClassID),
      // (sint_to_fp:{ *:[f16] } i32:{ *:[i32] }:$src)  =>  (V_CVT_F16_F32_t16_e64:{ *:[f16] } 0:{ *:[i32] }, (V_CVT_F32_I32_e32:{ *:[i16] } VSrc_b32:{ *:[i32] }:$src))
      GIR_MakeTempReg, /*TempRegID*/0, /*TypeID*/GILLT_s16,
      GIR_BuildMI, /*InsnID*/1, /*Opcode*/GIMT_Encode2(AMDGPU::V_CVT_F32_I32_e32),
      GIR_AddTempRegister, /*InsnID*/1, /*TempRegID*/0, /*TempRegFlags*/GIMT_Encode2(RegState::Define),
      GIR_Copy, /*NewInsnID*/1, /*OldInsnID*/0, /*OpIdx*/1, // src
      GIR_ConstrainSelectedInstOperands, /*InsnID*/1,
      GIR_BuildMI, /*InsnID*/0, /*Opcode*/GIMT_Encode2(AMDGPU::V_CVT_F16_F32_t16_e64),
      GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/0, // DstI[vdst]
      GIR_AddImm8, /*InsnID*/0, /*Imm*/0,
      GIR_AddSimpleTempRegister, /*InsnID*/0, /*TempRegID*/0,
      GIR_AddImm8, /*InsnID*/0, /*Imm*/0,
      GIR_AddImm8, /*InsnID*/0, /*Imm*/0,
      GIR_ConstrainSelectedInstOperands, /*InsnID*/0,
      GIR_EraseFromParent, /*InsnID*/0,
      // GIR_Coverage, 5883,
      GIR_Done,
    // Label 4213: @264280
    GIM_Try, /*On fail goto*//*Label 4214*/ GIMT_Encode4(264350), // Rule ID 6370 //
      GIM_CheckFeatures, GIMT_Encode2(GIFBS_NotHasTrue16BitInsts),
      GIM_CheckType, /*MI*/0, /*Op*/1, /*Type*/GILLT_s1,
      GIM_CheckRegBankForClass, /*MI*/0, /*Op*/0, /*RC*/GIMT_Encode2(AMDGPU::VGPR_32RegClassID),
      // (sint_to_fp:{ *:[f16] } i1:{ *:[i1] }:$src)  =>  (V_CVT_F16_F32_e32:{ *:[f16] } (V_CNDMASK_B32_e64:{ *:[i16] } 0:{ *:[i32] }, 0:{ *:[i32] }, 0:{ *:[i32] }, 3212836864:{ *:[i32] }, SSrc_i1:{ *:[i1] }:$src))
      GIR_MakeTempReg, /*TempRegID*/0, /*TypeID*/GILLT_s16,
      GIR_BuildMI, /*InsnID*/1, /*Opcode*/GIMT_Encode2(AMDGPU::V_CNDMASK_B32_e64),
      GIR_AddTempRegister, /*InsnID*/1, /*TempRegID*/0, /*TempRegFlags*/GIMT_Encode2(RegState::Define),
      GIR_AddImm8, /*InsnID*/1, /*Imm*/0,
      GIR_AddImm8, /*InsnID*/1, /*Imm*/0,
      GIR_AddImm8, /*InsnID*/1, /*Imm*/0,
      GIR_AddImm, /*InsnID*/1, /*Imm*/GIMT_Encode8(3212836864),
      GIR_Copy, /*NewInsnID*/1, /*OldInsnID*/0, /*OpIdx*/1, // src
      GIR_ConstrainSelectedInstOperands, /*InsnID*/1,
      GIR_BuildMI, /*InsnID*/0, /*Opcode*/GIMT_Encode2(AMDGPU::V_CVT_F16_F32_e32),
      GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/0, // DstI[vdst]
      GIR_AddSimpleTempRegister, /*InsnID*/0, /*TempRegID*/0,
      GIR_ConstrainSelectedInstOperands, /*InsnID*/0,
      GIR_EraseFromParent, /*InsnID*/0,
      // GIR_Coverage, 6370,
      GIR_Done,
    // Label 4214: @264350
    GIM_Try, /*On fail goto*//*Label 4215*/ GIMT_Encode4(264420), // Rule ID 6371 //
      GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasTrue16BitInsts),
      GIM_CheckType, /*MI*/0, /*Op*/1, /*Type*/GILLT_s1,
      GIM_CheckRegBankForClass, /*MI*/0, /*Op*/0, /*RC*/GIMT_Encode2(AMDGPU::VGPR_32_Lo128RegClassID),
      // (sint_to_fp:{ *:[f16] } i1:{ *:[i1] }:$src)  =>  (V_CVT_F16_F32_t16_e32:{ *:[f16] } (V_CNDMASK_B32_e64:{ *:[i16] } 0:{ *:[i32] }, 0:{ *:[i32] }, 0:{ *:[i32] }, 3212836864:{ *:[i32] }, SSrc_i1:{ *:[i1] }:$src))
      GIR_MakeTempReg, /*TempRegID*/0, /*TypeID*/GILLT_s16,
      GIR_BuildMI, /*InsnID*/1, /*Opcode*/GIMT_Encode2(AMDGPU::V_CNDMASK_B32_e64),
      GIR_AddTempRegister, /*InsnID*/1, /*TempRegID*/0, /*TempRegFlags*/GIMT_Encode2(RegState::Define),
      GIR_AddImm8, /*InsnID*/1, /*Imm*/0,
      GIR_AddImm8, /*InsnID*/1, /*Imm*/0,
      GIR_AddImm8, /*InsnID*/1, /*Imm*/0,
      GIR_AddImm, /*InsnID*/1, /*Imm*/GIMT_Encode8(3212836864),
      GIR_Copy, /*NewInsnID*/1, /*OldInsnID*/0, /*OpIdx*/1, // src
      GIR_ConstrainSelectedInstOperands, /*InsnID*/1,
      GIR_BuildMI, /*InsnID*/0, /*Opcode*/GIMT_Encode2(AMDGPU::V_CVT_F16_F32_t16_e32),
      GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/0, // DstI[vdst]
      GIR_AddSimpleTempRegister, /*InsnID*/0, /*TempRegID*/0,
      GIR_ConstrainSelectedInstOperands, /*InsnID*/0,
      GIR_EraseFromParent, /*InsnID*/0,
      // GIR_Coverage, 6371,
      GIR_Done,
    // Label 4215: @264420
    GIM_Try, /*On fail goto*//*Label 4216*/ GIMT_Encode4(264472), // Rule ID 650 //
      GIM_CheckFeatures, GIMT_Encode2(GIFBS_Has16BitInsts_NotHasTrue16BitInsts),
      GIM_CheckType, /*MI*/0, /*Op*/1, /*Type*/GILLT_s16,
      GIM_CheckRegBankForClass, /*MI*/0, /*Op*/0, /*RC*/GIMT_Encode2(AMDGPU::VGPR_32RegClassID),
      GIM_CheckComplexPattern, /*MI*/0, /*Op*/1, /*Renderer*/GIMT_Encode2(0), GIMT_Encode2(GICP_gi_vop3mods0),
      // (sint_to_fp:{ *:[f16] } (VOP3Mods0:{ *:[i16] } i16:{ *:[i16] }:$src0, i1:{ *:[i1] }:$clamp, i32:{ *:[i32] }:$omod))  =>  (V_CVT_F16_I16_e64:{ *:[f16] } i16:{ *:[i16] }:$src0, i1:{ *:[i1] }:$clamp, i32:{ *:[i32] }:$omod)
      GIR_BuildMI, /*InsnID*/0, /*Opcode*/GIMT_Encode2(AMDGPU::V_CVT_F16_I16_e64),
      GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/0, // DstI[vdst]
      GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/0, // src0
      GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/1, // clamp
      GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/2, // omod
      GIR_ConstrainSelectedInstOperands, /*InsnID*/0,
      GIR_EraseFromParent, /*InsnID*/0,
      // GIR_Coverage, 650,
      GIR_Done,
    // Label 4216: @264472
    GIM_Try, /*On fail goto*//*Label 4217*/ GIMT_Encode4(264524), // Rule ID 652 //
      GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasTrue16BitInsts),
      GIM_CheckType, /*MI*/0, /*Op*/1, /*Type*/GILLT_s16,
      GIM_CheckRegBankForClass, /*MI*/0, /*Op*/0, /*RC*/GIMT_Encode2(AMDGPU::VGPR_32RegClassID),
      GIM_CheckComplexPattern, /*MI*/0, /*Op*/1, /*Renderer*/GIMT_Encode2(0), GIMT_Encode2(GICP_gi_vop3mods0),
      // (sint_to_fp:{ *:[f16] } (VOP3Mods0:{ *:[i16] } i16:{ *:[i16] }:$src0, i1:{ *:[i1] }:$clamp, i32:{ *:[i32] }:$omod))  =>  (V_CVT_F16_I16_t16_e64:{ *:[f16] } i16:{ *:[i16] }:$src0, i1:{ *:[i1] }:$clamp, i32:{ *:[i32] }:$omod)
      GIR_BuildMI, /*InsnID*/0, /*Opcode*/GIMT_Encode2(AMDGPU::V_CVT_F16_I16_t16_e64),
      GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/0, // DstI[vdst]
      GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/0, // src0
      GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/1, // clamp
      GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/2, // omod
      GIR_ConstrainSelectedInstOperands, /*InsnID*/0,
      GIR_EraseFromParent, /*InsnID*/0,
      // GIR_Coverage, 652,
      GIR_Done,
    // Label 4217: @264524
    GIM_Reject,
    // Label 4209: @264525
    GIM_Try, /*On fail goto*//*Label 4218*/ GIMT_Encode4(264558), // Rule ID 27 //
      GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasSALUFloatInsts),
      GIM_CheckType, /*MI*/0, /*Op*/1, /*Type*/GILLT_s32,
      GIM_CheckRegBankForClass, /*MI*/0, /*Op*/0, /*RC*/GIMT_Encode2(AMDGPU::SReg_32RegClassID),
      GIM_CheckCxxInsnPredicate, /*MI*/0, /*FnId*/GIMT_Encode2(GICXXPred_MI_Predicate_anonymous_17590),
      // (sint_to_fp:{ *:[f32] } i32:{ *:[i32] }:$src0)<<P:Predicate_anonymous_17590>>  =>  (S_CVT_F32_I32:{ *:[f32] } i32:{ *:[i32] }:$src0)
      GIR_MutateOpcode, /*InsnID*/0, /*RecycleInsnID*/0, /*Opcode*/GIMT_Encode2(AMDGPU::S_CVT_F32_I32),
      GIR_AddImplicitUse, /*InsnID*/0, GIMT_Encode2(AMDGPU::MODE),
      GIR_ConstrainSelectedInstOperands, /*InsnID*/0,
      // GIR_Coverage, 27,
      GIR_Done,
    // Label 4218: @264558
    GIM_Try, /*On fail goto*//*Label 4219*/ GIMT_Encode4(264608), // Rule ID 6374 //
      GIM_CheckType, /*MI*/0, /*Op*/1, /*Type*/GILLT_s1,
      GIM_CheckRegBankForClass, /*MI*/0, /*Op*/0, /*RC*/GIMT_Encode2(AMDGPU::VGPR_32RegClassID),
      // (sint_to_fp:{ *:[f32] } i1:{ *:[i1] }:$src)  =>  (V_CNDMASK_B32_e64:{ *:[f32] } 0:{ *:[i32] }, 0:{ *:[i32] }, 0:{ *:[i32] }, 3212836864:{ *:[i32] }, SSrc_i1:{ *:[i1] }:$src)
      GIR_BuildMI, /*InsnID*/0, /*Opcode*/GIMT_Encode2(AMDGPU::V_CNDMASK_B32_e64),
      GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/0, // DstI[vdst]
      GIR_AddImm8, /*InsnID*/0, /*Imm*/0,
      GIR_AddImm8, /*InsnID*/0, /*Imm*/0,
      GIR_AddImm8, /*InsnID*/0, /*Imm*/0,
      GIR_AddImm, /*InsnID*/0, /*Imm*/GIMT_Encode8(3212836864),
      GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/1, // src
      GIR_ConstrainSelectedInstOperands, /*InsnID*/0,
      GIR_EraseFromParent, /*InsnID*/0,
      // GIR_Coverage, 6374,
      GIR_Done,
    // Label 4219: @264608
    GIM_Try, /*On fail goto*//*Label 4220*/ GIMT_Encode4(264657), // Rule ID 581 //
      GIM_CheckType, /*MI*/0, /*Op*/1, /*Type*/GILLT_s32,
      GIM_CheckRegBankForClass, /*MI*/0, /*Op*/0, /*RC*/GIMT_Encode2(AMDGPU::VGPR_32RegClassID),
      GIM_CheckComplexPattern, /*MI*/0, /*Op*/1, /*Renderer*/GIMT_Encode2(0), GIMT_Encode2(GICP_gi_vop3mods0),
      // (sint_to_fp:{ *:[f32] } (VOP3Mods0:{ *:[i32] } i32:{ *:[i32] }:$src0, i1:{ *:[i1] }:$clamp, i32:{ *:[i32] }:$omod))  =>  (V_CVT_F32_I32_e64:{ *:[f32] } i32:{ *:[i32] }:$src0, i1:{ *:[i1] }:$clamp, i32:{ *:[i32] }:$omod)
      GIR_BuildMI, /*InsnID*/0, /*Opcode*/GIMT_Encode2(AMDGPU::V_CVT_F32_I32_e64),
      GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/0, // DstI[vdst]
      GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/0, // src0
      GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/1, // clamp
      GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/2, // omod
      GIR_ConstrainSelectedInstOperands, /*InsnID*/0,
      GIR_EraseFromParent, /*InsnID*/0,
      // GIR_Coverage, 581,
      GIR_Done,
    // Label 4220: @264657
    GIM_Reject,
    // Label 4210: @264658
    GIM_Try, /*On fail goto*//*Label 4221*/ GIMT_Encode4(264718), // Rule ID 6376 //
      GIM_CheckType, /*MI*/0, /*Op*/1, /*Type*/GILLT_s1,
      GIM_CheckRegBankForClass, /*MI*/0, /*Op*/0, /*RC*/GIMT_Encode2(AMDGPU::VReg_64RegClassID),
      // (sint_to_fp:{ *:[f64] } i1:{ *:[i1] }:$src)  =>  (V_CVT_F64_I32_e32:{ *:[f64] } (V_CNDMASK_B32_e64:{ *:[i16] } 0:{ *:[i32] }, 0:{ *:[i32] }, 0:{ *:[i32] }, -1:{ *:[i32] }, SSrc_i1:{ *:[i1] }:$src))
      GIR_MakeTempReg, /*TempRegID*/0, /*TypeID*/GILLT_s16,
      GIR_BuildMI, /*InsnID*/1, /*Opcode*/GIMT_Encode2(AMDGPU::V_CNDMASK_B32_e64),
      GIR_AddTempRegister, /*InsnID*/1, /*TempRegID*/0, /*TempRegFlags*/GIMT_Encode2(RegState::Define),
      GIR_AddImm8, /*InsnID*/1, /*Imm*/0,
      GIR_AddImm8, /*InsnID*/1, /*Imm*/0,
      GIR_AddImm8, /*InsnID*/1, /*Imm*/0,
      GIR_AddImm8, /*InsnID*/1, /*Imm*/uint8_t(-1),
      GIR_Copy, /*NewInsnID*/1, /*OldInsnID*/0, /*OpIdx*/1, // src
      GIR_ConstrainSelectedInstOperands, /*InsnID*/1,
      GIR_BuildMI, /*InsnID*/0, /*Opcode*/GIMT_Encode2(AMDGPU::V_CVT_F64_I32_e32),
      GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/0, // DstI[vdst]
      GIR_AddSimpleTempRegister, /*InsnID*/0, /*TempRegID*/0,
      GIR_ConstrainSelectedInstOperands, /*InsnID*/0,
      GIR_EraseFromParent, /*InsnID*/0,
      // GIR_Coverage, 6376,
      GIR_Done,
    // Label 4221: @264718
    GIM_Try, /*On fail goto*//*Label 4222*/ GIMT_Encode4(264767), // Rule ID 575 //
      GIM_CheckType, /*MI*/0, /*Op*/1, /*Type*/GILLT_s32,
      GIM_CheckRegBankForClass, /*MI*/0, /*Op*/0, /*RC*/GIMT_Encode2(AMDGPU::VReg_64RegClassID),
      GIM_CheckComplexPattern, /*MI*/0, /*Op*/1, /*Renderer*/GIMT_Encode2(0), GIMT_Encode2(GICP_gi_vop3mods0),
      // (sint_to_fp:{ *:[f64] } (VOP3Mods0:{ *:[i32] } i32:{ *:[i32] }:$src0, i1:{ *:[i1] }:$clamp, i32:{ *:[i32] }:$omod))  =>  (V_CVT_F64_I32_e64:{ *:[f64] } i32:{ *:[i32] }:$src0, i1:{ *:[i1] }:$clamp, i32:{ *:[i32] }:$omod)
      GIR_BuildMI, /*InsnID*/0, /*Opcode*/GIMT_Encode2(AMDGPU::V_CVT_F64_I32_e64),
      GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/0, // DstI[vdst]
      GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/0, // src0
      GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/1, // clamp
      GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/2, // omod
      GIR_ConstrainSelectedInstOperands, /*InsnID*/0,
      GIR_EraseFromParent, /*InsnID*/0,
      // GIR_Coverage, 575,
      GIR_Done,
    // Label 4222: @264767
    GIM_Reject,
    // Label 4211: @264768
    GIM_Reject,
    // Label 71: @264769
    GIM_SwitchType, /*MI*/0, /*Op*/0, /*[*/GIMT_Encode2(8), GIMT_Encode2(11), /*)*//*default:*//*Label 4226*/ GIMT_Encode4(265400),
    /*GILLT_s16*//*Label 4223*/ GIMT_Encode4(264792),
    /*GILLT_s32*//*Label 4224*/ GIMT_Encode4(265157),
    /*GILLT_s64*//*Label 4225*/ GIMT_Encode4(265290),
    // Label 4223: @264792
    GIM_Try, /*On fail goto*//*Label 4227*/ GIMT_Encode4(264852), // Rule ID 5870 //
      GIM_CheckFeatures, GIMT_Encode2(GIFBS_NotHasTrue16BitInsts),
      GIM_CheckType, /*MI*/0, /*Op*/1, /*Type*/GILLT_s32,
      GIM_CheckRegBankForClass, /*MI*/0, /*Op*/0, /*RC*/GIMT_Encode2(AMDGPU::VGPR_32RegClassID),
      // (uint_to_fp:{ *:[f16] } i32:{ *:[i32] }:$src)  =>  (V_CVT_F16_F32_e64:{ *:[f16] } 0:{ *:[i32] }, (V_CVT_F32_U32_e32:{ *:[i16] } VSrc_b32:{ *:[i32] }:$src))
      GIR_MakeTempReg, /*TempRegID*/0, /*TypeID*/GILLT_s16,
      GIR_BuildMI, /*InsnID*/1, /*Opcode*/GIMT_Encode2(AMDGPU::V_CVT_F32_U32_e32),
      GIR_AddTempRegister, /*InsnID*/1, /*TempRegID*/0, /*TempRegFlags*/GIMT_Encode2(RegState::Define),
      GIR_Copy, /*NewInsnID*/1, /*OldInsnID*/0, /*OpIdx*/1, // src
      GIR_ConstrainSelectedInstOperands, /*InsnID*/1,
      GIR_BuildMI, /*InsnID*/0, /*Opcode*/GIMT_Encode2(AMDGPU::V_CVT_F16_F32_e64),
      GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/0, // DstI[vdst]
      GIR_AddImm8, /*InsnID*/0, /*Imm*/0,
      GIR_AddSimpleTempRegister, /*InsnID*/0, /*TempRegID*/0,
      GIR_AddImm8, /*InsnID*/0, /*Imm*/0,
      GIR_AddImm8, /*InsnID*/0, /*Imm*/0,
      GIR_ConstrainSelectedInstOperands, /*InsnID*/0,
      GIR_EraseFromParent, /*InsnID*/0,
      // GIR_Coverage, 5870,
      GIR_Done,
    // Label 4227: @264852
    GIM_Try, /*On fail goto*//*Label 4228*/ GIMT_Encode4(264912), // Rule ID 5884 //
      GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasTrue16BitInsts),
      GIM_CheckType, /*MI*/0, /*Op*/1, /*Type*/GILLT_s32,
      GIM_CheckRegBankForClass, /*MI*/0, /*Op*/0, /*RC*/GIMT_Encode2(AMDGPU::VGPR_32RegClassID),
      // (uint_to_fp:{ *:[f16] } i32:{ *:[i32] }:$src)  =>  (V_CVT_F16_F32_t16_e64:{ *:[f16] } 0:{ *:[i32] }, (V_CVT_F32_U32_e32:{ *:[i16] } VSrc_b32:{ *:[i32] }:$src))
      GIR_MakeTempReg, /*TempRegID*/0, /*TypeID*/GILLT_s16,
      GIR_BuildMI, /*InsnID*/1, /*Opcode*/GIMT_Encode2(AMDGPU::V_CVT_F32_U32_e32),
      GIR_AddTempRegister, /*InsnID*/1, /*TempRegID*/0, /*TempRegFlags*/GIMT_Encode2(RegState::Define),
      GIR_Copy, /*NewInsnID*/1, /*OldInsnID*/0, /*OpIdx*/1, // src
      GIR_ConstrainSelectedInstOperands, /*InsnID*/1,
      GIR_BuildMI, /*InsnID*/0, /*Opcode*/GIMT_Encode2(AMDGPU::V_CVT_F16_F32_t16_e64),
      GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/0, // DstI[vdst]
      GIR_AddImm8, /*InsnID*/0, /*Imm*/0,
      GIR_AddSimpleTempRegister, /*InsnID*/0, /*TempRegID*/0,
      GIR_AddImm8, /*InsnID*/0, /*Imm*/0,
      GIR_AddImm8, /*InsnID*/0, /*Imm*/0,
      GIR_ConstrainSelectedInstOperands, /*InsnID*/0,
      GIR_EraseFromParent, /*InsnID*/0,
      // GIR_Coverage, 5884,
      GIR_Done,
    // Label 4228: @264912
    GIM_Try, /*On fail goto*//*Label 4229*/ GIMT_Encode4(264982), // Rule ID 6372 //
      GIM_CheckFeatures, GIMT_Encode2(GIFBS_NotHasTrue16BitInsts),
      GIM_CheckType, /*MI*/0, /*Op*/1, /*Type*/GILLT_s1,
      GIM_CheckRegBankForClass, /*MI*/0, /*Op*/0, /*RC*/GIMT_Encode2(AMDGPU::VGPR_32RegClassID),
      // (uint_to_fp:{ *:[f16] } i1:{ *:[i1] }:$src)  =>  (V_CVT_F16_F32_e32:{ *:[f16] } (V_CNDMASK_B32_e64:{ *:[i16] } 0:{ *:[i32] }, 0:{ *:[i32] }, 0:{ *:[i32] }, 1065353216:{ *:[i32] }, SSrc_i1:{ *:[i1] }:$src))
      GIR_MakeTempReg, /*TempRegID*/0, /*TypeID*/GILLT_s16,
      GIR_BuildMI, /*InsnID*/1, /*Opcode*/GIMT_Encode2(AMDGPU::V_CNDMASK_B32_e64),
      GIR_AddTempRegister, /*InsnID*/1, /*TempRegID*/0, /*TempRegFlags*/GIMT_Encode2(RegState::Define),
      GIR_AddImm8, /*InsnID*/1, /*Imm*/0,
      GIR_AddImm8, /*InsnID*/1, /*Imm*/0,
      GIR_AddImm8, /*InsnID*/1, /*Imm*/0,
      GIR_AddImm, /*InsnID*/1, /*Imm*/GIMT_Encode8(1065353216),
      GIR_Copy, /*NewInsnID*/1, /*OldInsnID*/0, /*OpIdx*/1, // src
      GIR_ConstrainSelectedInstOperands, /*InsnID*/1,
      GIR_BuildMI, /*InsnID*/0, /*Opcode*/GIMT_Encode2(AMDGPU::V_CVT_F16_F32_e32),
      GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/0, // DstI[vdst]
      GIR_AddSimpleTempRegister, /*InsnID*/0, /*TempRegID*/0,
      GIR_ConstrainSelectedInstOperands, /*InsnID*/0,
      GIR_EraseFromParent, /*InsnID*/0,
      // GIR_Coverage, 6372,
      GIR_Done,
    // Label 4229: @264982
    GIM_Try, /*On fail goto*//*Label 4230*/ GIMT_Encode4(265052), // Rule ID 6373 //
      GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasTrue16BitInsts),
      GIM_CheckType, /*MI*/0, /*Op*/1, /*Type*/GILLT_s1,
      GIM_CheckRegBankForClass, /*MI*/0, /*Op*/0, /*RC*/GIMT_Encode2(AMDGPU::VGPR_32_Lo128RegClassID),
      // (uint_to_fp:{ *:[f16] } i1:{ *:[i1] }:$src)  =>  (V_CVT_F16_F32_t16_e32:{ *:[f16] } (V_CNDMASK_B32_e64:{ *:[i16] } 0:{ *:[i32] }, 0:{ *:[i32] }, 0:{ *:[i32] }, 1065353216:{ *:[i32] }, SSrc_i1:{ *:[i1] }:$src))
      GIR_MakeTempReg, /*TempRegID*/0, /*TypeID*/GILLT_s16,
      GIR_BuildMI, /*InsnID*/1, /*Opcode*/GIMT_Encode2(AMDGPU::V_CNDMASK_B32_e64),
      GIR_AddTempRegister, /*InsnID*/1, /*TempRegID*/0, /*TempRegFlags*/GIMT_Encode2(RegState::Define),
      GIR_AddImm8, /*InsnID*/1, /*Imm*/0,
      GIR_AddImm8, /*InsnID*/1, /*Imm*/0,
      GIR_AddImm8, /*InsnID*/1, /*Imm*/0,
      GIR_AddImm, /*InsnID*/1, /*Imm*/GIMT_Encode8(1065353216),
      GIR_Copy, /*NewInsnID*/1, /*OldInsnID*/0, /*OpIdx*/1, // src
      GIR_ConstrainSelectedInstOperands, /*InsnID*/1,
      GIR_BuildMI, /*InsnID*/0, /*Opcode*/GIMT_Encode2(AMDGPU::V_CVT_F16_F32_t16_e32),
      GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/0, // DstI[vdst]
      GIR_AddSimpleTempRegister, /*InsnID*/0, /*TempRegID*/0,
      GIR_ConstrainSelectedInstOperands, /*InsnID*/0,
      GIR_EraseFromParent, /*InsnID*/0,
      // GIR_Coverage, 6373,
      GIR_Done,
    // Label 4230: @265052
    GIM_Try, /*On fail goto*//*Label 4231*/ GIMT_Encode4(265104), // Rule ID 649 //
      GIM_CheckFeatures, GIMT_Encode2(GIFBS_Has16BitInsts_NotHasTrue16BitInsts),
      GIM_CheckType, /*MI*/0, /*Op*/1, /*Type*/GILLT_s16,
      GIM_CheckRegBankForClass, /*MI*/0, /*Op*/0, /*RC*/GIMT_Encode2(AMDGPU::VGPR_32RegClassID),
      GIM_CheckComplexPattern, /*MI*/0, /*Op*/1, /*Renderer*/GIMT_Encode2(0), GIMT_Encode2(GICP_gi_vop3mods0),
      // (uint_to_fp:{ *:[f16] } (VOP3Mods0:{ *:[i16] } i16:{ *:[i16] }:$src0, i1:{ *:[i1] }:$clamp, i32:{ *:[i32] }:$omod))  =>  (V_CVT_F16_U16_e64:{ *:[f16] } i16:{ *:[i16] }:$src0, i1:{ *:[i1] }:$clamp, i32:{ *:[i32] }:$omod)
      GIR_BuildMI, /*InsnID*/0, /*Opcode*/GIMT_Encode2(AMDGPU::V_CVT_F16_U16_e64),
      GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/0, // DstI[vdst]
      GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/0, // src0
      GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/1, // clamp
      GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/2, // omod
      GIR_ConstrainSelectedInstOperands, /*InsnID*/0,
      GIR_EraseFromParent, /*InsnID*/0,
      // GIR_Coverage, 649,
      GIR_Done,
    // Label 4231: @265104
    GIM_Try, /*On fail goto*//*Label 4232*/ GIMT_Encode4(265156), // Rule ID 651 //
      GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasTrue16BitInsts),
      GIM_CheckType, /*MI*/0, /*Op*/1, /*Type*/GILLT_s16,
      GIM_CheckRegBankForClass, /*MI*/0, /*Op*/0, /*RC*/GIMT_Encode2(AMDGPU::VGPR_32RegClassID),
      GIM_CheckComplexPattern, /*MI*/0, /*Op*/1, /*Renderer*/GIMT_Encode2(0), GIMT_Encode2(GICP_gi_vop3mods0),
      // (uint_to_fp:{ *:[f16] } (VOP3Mods0:{ *:[i16] } i16:{ *:[i16] }:$src0, i1:{ *:[i1] }:$clamp, i32:{ *:[i32] }:$omod))  =>  (V_CVT_F16_U16_t16_e64:{ *:[f16] } i16:{ *:[i16] }:$src0, i1:{ *:[i1] }:$clamp, i32:{ *:[i32] }:$omod)
      GIR_BuildMI, /*InsnID*/0, /*Opcode*/GIMT_Encode2(AMDGPU::V_CVT_F16_U16_t16_e64),
      GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/0, // DstI[vdst]
      GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/0, // src0
      GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/1, // clamp
      GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/2, // omod
      GIR_ConstrainSelectedInstOperands, /*InsnID*/0,
      GIR_EraseFromParent, /*InsnID*/0,
      // GIR_Coverage, 651,
      GIR_Done,
    // Label 4232: @265156
    GIM_Reject,
    // Label 4224: @265157
    GIM_Try, /*On fail goto*//*Label 4233*/ GIMT_Encode4(265190), // Rule ID 28 //
      GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasSALUFloatInsts),
      GIM_CheckType, /*MI*/0, /*Op*/1, /*Type*/GILLT_s32,
      GIM_CheckRegBankForClass, /*MI*/0, /*Op*/0, /*RC*/GIMT_Encode2(AMDGPU::SReg_32RegClassID),
      GIM_CheckCxxInsnPredicate, /*MI*/0, /*FnId*/GIMT_Encode2(GICXXPred_MI_Predicate_anonymous_17594),
      // (uint_to_fp:{ *:[f32] } i32:{ *:[i32] }:$src0)<<P:Predicate_anonymous_17594>>  =>  (S_CVT_F32_U32:{ *:[f32] } i32:{ *:[i32] }:$src0)
      GIR_MutateOpcode, /*InsnID*/0, /*RecycleInsnID*/0, /*Opcode*/GIMT_Encode2(AMDGPU::S_CVT_F32_U32),
      GIR_AddImplicitUse, /*InsnID*/0, GIMT_Encode2(AMDGPU::MODE),
      GIR_ConstrainSelectedInstOperands, /*InsnID*/0,
      // GIR_Coverage, 28,
      GIR_Done,
    // Label 4233: @265190
    GIM_Try, /*On fail goto*//*Label 4234*/ GIMT_Encode4(265240), // Rule ID 6375 //
      GIM_CheckType, /*MI*/0, /*Op*/1, /*Type*/GILLT_s1,
      GIM_CheckRegBankForClass, /*MI*/0, /*Op*/0, /*RC*/GIMT_Encode2(AMDGPU::VGPR_32RegClassID),
      // (uint_to_fp:{ *:[f32] } i1:{ *:[i1] }:$src)  =>  (V_CNDMASK_B32_e64:{ *:[f32] } 0:{ *:[i32] }, 0:{ *:[i32] }, 0:{ *:[i32] }, 1065353216:{ *:[i32] }, SSrc_i1:{ *:[i1] }:$src)
      GIR_BuildMI, /*InsnID*/0, /*Opcode*/GIMT_Encode2(AMDGPU::V_CNDMASK_B32_e64),
      GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/0, // DstI[vdst]
      GIR_AddImm8, /*InsnID*/0, /*Imm*/0,
      GIR_AddImm8, /*InsnID*/0, /*Imm*/0,
      GIR_AddImm8, /*InsnID*/0, /*Imm*/0,
      GIR_AddImm, /*InsnID*/0, /*Imm*/GIMT_Encode8(1065353216),
      GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/1, // src
      GIR_ConstrainSelectedInstOperands, /*InsnID*/0,
      GIR_EraseFromParent, /*InsnID*/0,
      // GIR_Coverage, 6375,
      GIR_Done,
    // Label 4234: @265240
    GIM_Try, /*On fail goto*//*Label 4235*/ GIMT_Encode4(265289), // Rule ID 582 //
      GIM_CheckType, /*MI*/0, /*Op*/1, /*Type*/GILLT_s32,
      GIM_CheckRegBankForClass, /*MI*/0, /*Op*/0, /*RC*/GIMT_Encode2(AMDGPU::VGPR_32RegClassID),
      GIM_CheckComplexPattern, /*MI*/0, /*Op*/1, /*Renderer*/GIMT_Encode2(0), GIMT_Encode2(GICP_gi_vop3mods0),
      // (uint_to_fp:{ *:[f32] } (VOP3Mods0:{ *:[i32] } i32:{ *:[i32] }:$src0, i1:{ *:[i1] }:$clamp, i32:{ *:[i32] }:$omod))  =>  (V_CVT_F32_U32_e64:{ *:[f32] } i32:{ *:[i32] }:$src0, i1:{ *:[i1] }:$clamp, i32:{ *:[i32] }:$omod)
      GIR_BuildMI, /*InsnID*/0, /*Opcode*/GIMT_Encode2(AMDGPU::V_CVT_F32_U32_e64),
      GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/0, // DstI[vdst]
      GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/0, // src0
      GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/1, // clamp
      GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/2, // omod
      GIR_ConstrainSelectedInstOperands, /*InsnID*/0,
      GIR_EraseFromParent, /*InsnID*/0,
      // GIR_Coverage, 582,
      GIR_Done,
    // Label 4235: @265289
    GIM_Reject,
    // Label 4225: @265290
    GIM_Try, /*On fail goto*//*Label 4236*/ GIMT_Encode4(265350), // Rule ID 6377 //
      GIM_CheckType, /*MI*/0, /*Op*/1, /*Type*/GILLT_s1,
      GIM_CheckRegBankForClass, /*MI*/0, /*Op*/0, /*RC*/GIMT_Encode2(AMDGPU::VReg_64RegClassID),
      // (uint_to_fp:{ *:[f64] } i1:{ *:[i1] }:$src)  =>  (V_CVT_F64_U32_e32:{ *:[f64] } (V_CNDMASK_B32_e64:{ *:[i16] } 0:{ *:[i32] }, 0:{ *:[i32] }, 0:{ *:[i32] }, 1:{ *:[i32] }, SSrc_i1:{ *:[i1] }:$src))
      GIR_MakeTempReg, /*TempRegID*/0, /*TypeID*/GILLT_s16,
      GIR_BuildMI, /*InsnID*/1, /*Opcode*/GIMT_Encode2(AMDGPU::V_CNDMASK_B32_e64),
      GIR_AddTempRegister, /*InsnID*/1, /*TempRegID*/0, /*TempRegFlags*/GIMT_Encode2(RegState::Define),
      GIR_AddImm8, /*InsnID*/1, /*Imm*/0,
      GIR_AddImm8, /*InsnID*/1, /*Imm*/0,
      GIR_AddImm8, /*InsnID*/1, /*Imm*/0,
      GIR_AddImm8, /*InsnID*/1, /*Imm*/1,
      GIR_Copy, /*NewInsnID*/1, /*OldInsnID*/0, /*OpIdx*/1, // src
      GIR_ConstrainSelectedInstOperands, /*InsnID*/1,
      GIR_BuildMI, /*InsnID*/0, /*Opcode*/GIMT_Encode2(AMDGPU::V_CVT_F64_U32_e32),
      GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/0, // DstI[vdst]
      GIR_AddSimpleTempRegister, /*InsnID*/0, /*TempRegID*/0,
      GIR_ConstrainSelectedInstOperands, /*InsnID*/0,
      GIR_EraseFromParent, /*InsnID*/0,
      // GIR_Coverage, 6377,
      GIR_Done,
    // Label 4236: @265350
    GIM_Try, /*On fail goto*//*Label 4237*/ GIMT_Encode4(265399), // Rule ID 580 //
      GIM_CheckType, /*MI*/0, /*Op*/1, /*Type*/GILLT_s32,
      GIM_CheckRegBankForClass, /*MI*/0, /*Op*/0, /*RC*/GIMT_Encode2(AMDGPU::VReg_64RegClassID),
      GIM_CheckComplexPattern, /*MI*/0, /*Op*/1, /*Renderer*/GIMT_Encode2(0), GIMT_Encode2(GICP_gi_vop3mods0),
      // (uint_to_fp:{ *:[f64] } (VOP3Mods0:{ *:[i32] } i32:{ *:[i32] }:$src0, i1:{ *:[i1] }:$clamp, i32:{ *:[i32] }:$omod))  =>  (V_CVT_F64_U32_e64:{ *:[f64] } i32:{ *:[i32] }:$src0, i1:{ *:[i1] }:$clamp, i32:{ *:[i32] }:$omod)
      GIR_BuildMI, /*InsnID*/0, /*Opcode*/GIMT_Encode2(AMDGPU::V_CVT_F64_U32_e64),
      GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/0, // DstI[vdst]
      GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/0, // src0
      GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/1, // clamp
      GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/2, // omod
      GIR_ConstrainSelectedInstOperands, /*InsnID*/0,
      GIR_EraseFromParent, /*InsnID*/0,
      // GIR_Coverage, 580,
      GIR_Done,
    // Label 4237: @265399
    GIM_Reject,
    // Label 4226: @265400
    GIM_Reject,
    // Label 72: @265401
    GIM_SwitchType, /*MI*/0, /*Op*/0, /*[*/GIMT_Encode2(8), GIMT_Encode2(12), /*)*//*default:*//*Label 4242*/ GIMT_Encode4(265994),
    /*GILLT_s16*//*Label 4238*/ GIMT_Encode4(265428),
    /*GILLT_s32*//*Label 4239*/ GIMT_Encode4(265564),
    /*GILLT_s64*//*Label 4240*/ GIMT_Encode4(265700),
    /*GILLT_v2s16*//*Label 4241*/ GIMT_Encode4(265858),
    // Label 4238: @265428
    GIM_Try, /*On fail goto*//*Label 4243*/ GIMT_Encode4(265563),
      GIM_CheckType, /*MI*/0, /*Op*/1, /*Type*/GILLT_s16,
      GIM_Try, /*On fail goto*//*Label 4244*/ GIMT_Encode4(265503), // Rule ID 6209 //
        GIM_CheckRegBankForClass, /*MI*/0, /*Op*/0, /*RC*/GIMT_Encode2(AMDGPU::SReg_32RegClassID),
        GIM_CheckRegBankForClass, /*MI*/0, /*Op*/1, /*RC*/GIMT_Encode2(AMDGPU::SReg_32RegClassID),
        GIM_CheckCxxInsnPredicate, /*MI*/0, /*FnId*/GIMT_Encode2(GICXXPred_MI_Predicate_anonymous_34990),
        // (fabs:{ *:[f16] } SReg_32:{ *:[f16] }:$src)<<P:Predicate_anonymous_34990>>  =>  (S_AND_B32:{ *:[f16] }:{ *:[i1] } SReg_32:{ *:[f16] }:$src, (S_MOV_B32:{ *:[i1] } 32767:{ *:[i32] }))
        GIR_MakeTempReg, /*TempRegID*/0, /*TypeID*/GILLT_s1,
        GIR_BuildMI, /*InsnID*/1, /*Opcode*/GIMT_Encode2(AMDGPU::S_MOV_B32),
        GIR_AddTempRegister, /*InsnID*/1, /*TempRegID*/0, /*TempRegFlags*/GIMT_Encode2(RegState::Define),
        GIR_AddImm, /*InsnID*/1, /*Imm*/GIMT_Encode8(32767),
        GIR_ConstrainSelectedInstOperands, /*InsnID*/1,
        GIR_BuildMI, /*InsnID*/0, /*Opcode*/GIMT_Encode2(AMDGPU::S_AND_B32),
        GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/0, // DstI[sdst]
        GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/1, // src
        GIR_AddSimpleTempRegister, /*InsnID*/0, /*TempRegID*/0,
        GIR_SetImplicitDefDead, /*InsnID*/0, /*OpIdx for AMDGPU::SCC*/0,
        GIR_ConstrainSelectedInstOperands, /*InsnID*/0,
        GIR_EraseFromParent, /*InsnID*/0,
        // GIR_Coverage, 6209,
        GIR_Done,
      // Label 4244: @265503
      GIM_Try, /*On fail goto*//*Label 4245*/ GIMT_Encode4(265562), // Rule ID 6224 //
        GIM_CheckRegBankForClass, /*MI*/0, /*Op*/0, /*RC*/GIMT_Encode2(AMDGPU::VGPR_32RegClassID),
        GIM_CheckRegBankForClass, /*MI*/0, /*Op*/1, /*RC*/GIMT_Encode2(AMDGPU::VGPR_32RegClassID),
        // (fabs:{ *:[f16] } VGPR_32:{ *:[f16] }:$src)  =>  (V_AND_B32_e64:{ *:[f16] } (S_MOV_B32:{ *:[i16] } 32767:{ *:[i32] }), VGPR_32:{ *:[f16] }:$src)
        GIR_MakeTempReg, /*TempRegID*/0, /*TypeID*/GILLT_s16,
        GIR_BuildMI, /*InsnID*/1, /*Opcode*/GIMT_Encode2(AMDGPU::S_MOV_B32),
        GIR_AddTempRegister, /*InsnID*/1, /*TempRegID*/0, /*TempRegFlags*/GIMT_Encode2(RegState::Define),
        GIR_AddImm, /*InsnID*/1, /*Imm*/GIMT_Encode8(32767),
        GIR_ConstrainSelectedInstOperands, /*InsnID*/1,
        GIR_BuildMI, /*InsnID*/0, /*Opcode*/GIMT_Encode2(AMDGPU::V_AND_B32_e64),
        GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/0, // DstI[vdst]
        GIR_AddSimpleTempRegister, /*InsnID*/0, /*TempRegID*/0,
        GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/1, // src
        GIR_ConstrainSelectedInstOperands, /*InsnID*/0,
        GIR_EraseFromParent, /*InsnID*/0,
        // GIR_Coverage, 6224,
        GIR_Done,
      // Label 4245: @265562
      GIM_Reject,
    // Label 4243: @265563
    GIM_Reject,
    // Label 4239: @265564
    GIM_Try, /*On fail goto*//*Label 4246*/ GIMT_Encode4(265699),
      GIM_CheckType, /*MI*/0, /*Op*/1, /*Type*/GILLT_s32,
      GIM_Try, /*On fail goto*//*Label 4247*/ GIMT_Encode4(265639), // Rule ID 6206 //
        GIM_CheckRegBankForClass, /*MI*/0, /*Op*/0, /*RC*/GIMT_Encode2(AMDGPU::SReg_32RegClassID),
        GIM_CheckRegBankForClass, /*MI*/0, /*Op*/1, /*RC*/GIMT_Encode2(AMDGPU::SReg_32RegClassID),
        GIM_CheckCxxInsnPredicate, /*MI*/0, /*FnId*/GIMT_Encode2(GICXXPred_MI_Predicate_anonymous_34990),
        // (fabs:{ *:[f32] } SReg_32:{ *:[f32] }:$src)<<P:Predicate_anonymous_34990>>  =>  (S_AND_B32:{ *:[f32] }:{ *:[i1] } SReg_32:{ *:[f32] }:$src, (S_MOV_B32:{ *:[i1] } 2147483647:{ *:[i32] }))
        GIR_MakeTempReg, /*TempRegID*/0, /*TypeID*/GILLT_s1,
        GIR_BuildMI, /*InsnID*/1, /*Opcode*/GIMT_Encode2(AMDGPU::S_MOV_B32),
        GIR_AddTempRegister, /*InsnID*/1, /*TempRegID*/0, /*TempRegFlags*/GIMT_Encode2(RegState::Define),
        GIR_AddImm, /*InsnID*/1, /*Imm*/GIMT_Encode8(2147483647),
        GIR_ConstrainSelectedInstOperands, /*InsnID*/1,
        GIR_BuildMI, /*InsnID*/0, /*Opcode*/GIMT_Encode2(AMDGPU::S_AND_B32),
        GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/0, // DstI[sdst]
        GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/1, // src
        GIR_AddSimpleTempRegister, /*InsnID*/0, /*TempRegID*/0,
        GIR_SetImplicitDefDead, /*InsnID*/0, /*OpIdx for AMDGPU::SCC*/0,
        GIR_ConstrainSelectedInstOperands, /*InsnID*/0,
        GIR_EraseFromParent, /*InsnID*/0,
        // GIR_Coverage, 6206,
        GIR_Done,
      // Label 4247: @265639
      GIM_Try, /*On fail goto*//*Label 4248*/ GIMT_Encode4(265698), // Rule ID 6222 //
        GIM_CheckRegBankForClass, /*MI*/0, /*Op*/0, /*RC*/GIMT_Encode2(AMDGPU::VGPR_32RegClassID),
        GIM_CheckRegBankForClass, /*MI*/0, /*Op*/1, /*RC*/GIMT_Encode2(AMDGPU::VGPR_32RegClassID),
        // (fabs:{ *:[f32] } VGPR_32:{ *:[f32] }:$src)  =>  (V_AND_B32_e64:{ *:[f32] } (S_MOV_B32:{ *:[i16] } 2147483647:{ *:[i32] }), VGPR_32:{ *:[f32] }:$src)
        GIR_MakeTempReg, /*TempRegID*/0, /*TypeID*/GILLT_s16,
        GIR_BuildMI, /*InsnID*/1, /*Opcode*/GIMT_Encode2(AMDGPU::S_MOV_B32),
        GIR_AddTempRegister, /*InsnID*/1, /*TempRegID*/0, /*TempRegFlags*/GIMT_Encode2(RegState::Define),
        GIR_AddImm, /*InsnID*/1, /*Imm*/GIMT_Encode8(2147483647),
        GIR_ConstrainSelectedInstOperands, /*InsnID*/1,
        GIR_BuildMI, /*InsnID*/0, /*Opcode*/GIMT_Encode2(AMDGPU::V_AND_B32_e64),
        GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/0, // DstI[vdst]
        GIR_AddSimpleTempRegister, /*InsnID*/0, /*TempRegID*/0,
        GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/1, // src
        GIR_ConstrainSelectedInstOperands, /*InsnID*/0,
        GIR_EraseFromParent, /*InsnID*/0,
        // GIR_Coverage, 6222,
        GIR_Done,
      // Label 4248: @265698
      GIM_Reject,
    // Label 4246: @265699
    GIM_Reject,
    // Label 4240: @265700
    GIM_Try, /*On fail goto*//*Label 4249*/ GIMT_Encode4(265857), // Rule ID 6230 //
      GIM_CheckType, /*MI*/0, /*Op*/1, /*Type*/GILLT_s64,
      GIM_CheckRegBankForClass, /*MI*/0, /*Op*/0, /*RC*/GIMT_Encode2(AMDGPU::VReg_64RegClassID),
      GIM_CheckRegBankForClass, /*MI*/0, /*Op*/1, /*RC*/GIMT_Encode2(AMDGPU::VReg_64RegClassID),
      // (fabs:{ *:[f64] } VReg_64:{ *:[f64] }:$src)  =>  (REG_SEQUENCE:{ *:[f64] } VReg_64:{ *:[i32] }, (EXTRACT_SUBREG:{ *:[i32] } VReg_64:{ *:[f64] }:$src, sub0:{ *:[i32] }), sub0:{ *:[i32] }, (V_AND_B32_e64:{ *:[i16] } (S_MOV_B32:{ *:[i32] } 2147483647:{ *:[i32] }), (EXTRACT_SUBREG:{ *:[i32] } VReg_64:{ *:[f64] }:$src, sub1:{ *:[i32] })), sub1:{ *:[i32] })
      GIR_MakeTempReg, /*TempRegID*/0, /*TypeID*/GILLT_s32,
      GIR_MakeTempReg, /*TempRegID*/1, /*TypeID*/GILLT_s16,
      GIR_MakeTempReg, /*TempRegID*/2, /*TypeID*/GILLT_s32,
      GIR_MakeTempReg, /*TempRegID*/3, /*TypeID*/GILLT_s32,
      GIR_BuildMI, /*InsnID*/4, /*Opcode*/GIMT_Encode2(TargetOpcode::COPY),
      GIR_AddTempRegister, /*InsnID*/4, /*TempRegID*/3, /*TempRegFlags*/GIMT_Encode2(RegState::Define),
      GIR_CopySubReg, /*NewInsnID*/4, /*OldInsnID*/0, /*OpIdx*/1, /*SubRegIdx*/GIMT_Encode2(11), // src
      GIR_ConstrainOperandRC, /*InsnID*/4, /*Op*/0, GIMT_Encode2(AMDGPU::VGPR_32RegClassID),
      GIR_ConstrainOperandRC, /*InsnID*/4, /*Op*/1, GIMT_Encode2(AMDGPU::VReg_64RegClassID),
      GIR_BuildMI, /*InsnID*/3, /*Opcode*/GIMT_Encode2(AMDGPU::S_MOV_B32),
      GIR_AddTempRegister, /*InsnID*/3, /*TempRegID*/2, /*TempRegFlags*/GIMT_Encode2(RegState::Define),
      GIR_AddImm, /*InsnID*/3, /*Imm*/GIMT_Encode8(2147483647),
      GIR_ConstrainSelectedInstOperands, /*InsnID*/3,
      GIR_BuildMI, /*InsnID*/2, /*Opcode*/GIMT_Encode2(AMDGPU::V_AND_B32_e64),
      GIR_AddTempRegister, /*InsnID*/2, /*TempRegID*/1, /*TempRegFlags*/GIMT_Encode2(RegState::Define),
      GIR_AddSimpleTempRegister, /*InsnID*/2, /*TempRegID*/2,
      GIR_AddSimpleTempRegister, /*InsnID*/2, /*TempRegID*/3,
      GIR_ConstrainSelectedInstOperands, /*InsnID*/2,
      GIR_BuildMI, /*InsnID*/1, /*Opcode*/GIMT_Encode2(TargetOpcode::COPY),
      GIR_AddTempRegister, /*InsnID*/1, /*TempRegID*/0, /*TempRegFlags*/GIMT_Encode2(RegState::Define),
      GIR_CopySubReg, /*NewInsnID*/1, /*OldInsnID*/0, /*OpIdx*/1, /*SubRegIdx*/GIMT_Encode2(3), // src
      GIR_ConstrainOperandRC, /*InsnID*/1, /*Op*/0, GIMT_Encode2(AMDGPU::VGPR_32RegClassID),
      GIR_ConstrainOperandRC, /*InsnID*/1, /*Op*/1, GIMT_Encode2(AMDGPU::VReg_64RegClassID),
      GIR_BuildMI, /*InsnID*/0, /*Opcode*/GIMT_Encode2(TargetOpcode::REG_SEQUENCE),
      GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/0, // DstI[dst]
      GIR_AddSimpleTempRegister, /*InsnID*/0, /*TempRegID*/0,
      GIR_AddImm8, /*InsnID*/0, /*SubRegIndex*/3,
      GIR_AddSimpleTempRegister, /*InsnID*/0, /*TempRegID*/1,
      GIR_AddImm8, /*InsnID*/0, /*SubRegIndex*/11,
      GIR_ConstrainOperandRC, /*InsnID*/0, /*Op*/0, GIMT_Encode2(AMDGPU::VReg_64RegClassID),
      GIR_ConstrainOperandRC, /*InsnID*/0, /*Op*/1, GIMT_Encode2(AMDGPU::VGPR_32RegClassID),
      GIR_ConstrainOperandRC, /*InsnID*/0, /*Op*/3, GIMT_Encode2(AMDGPU::VGPR_32RegClassID),
      GIR_EraseFromParent, /*InsnID*/0,
      // GIR_Coverage, 6230,
      GIR_Done,
    // Label 4249: @265857
    GIM_Reject,
    // Label 4241: @265858
    GIM_Try, /*On fail goto*//*Label 4250*/ GIMT_Encode4(265993),
      GIM_CheckType, /*MI*/0, /*Op*/1, /*Type*/GILLT_v2s16,
      GIM_Try, /*On fail goto*//*Label 4251*/ GIMT_Encode4(265933), // Rule ID 6212 //
        GIM_CheckRegBankForClass, /*MI*/0, /*Op*/0, /*RC*/GIMT_Encode2(AMDGPU::SReg_32RegClassID),
        GIM_CheckRegBankForClass, /*MI*/0, /*Op*/1, /*RC*/GIMT_Encode2(AMDGPU::SReg_32RegClassID),
        GIM_CheckCxxInsnPredicate, /*MI*/0, /*FnId*/GIMT_Encode2(GICXXPred_MI_Predicate_anonymous_34990),
        // (fabs:{ *:[v2f16] } SReg_32:{ *:[v2f16] }:$src)<<P:Predicate_anonymous_34990>>  =>  (S_AND_B32:{ *:[v2f16] }:{ *:[i1] } SReg_32:{ *:[v2f16] }:$src, (S_MOV_B32:{ *:[i1] } 2147450879:{ *:[i32] }))
        GIR_MakeTempReg, /*TempRegID*/0, /*TypeID*/GILLT_s1,
        GIR_BuildMI, /*InsnID*/1, /*Opcode*/GIMT_Encode2(AMDGPU::S_MOV_B32),
        GIR_AddTempRegister, /*InsnID*/1, /*TempRegID*/0, /*TempRegFlags*/GIMT_Encode2(RegState::Define),
        GIR_AddImm, /*InsnID*/1, /*Imm*/GIMT_Encode8(2147450879),
        GIR_ConstrainSelectedInstOperands, /*InsnID*/1,
        GIR_BuildMI, /*InsnID*/0, /*Opcode*/GIMT_Encode2(AMDGPU::S_AND_B32),
        GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/0, // DstI[sdst]
        GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/1, // src
        GIR_AddSimpleTempRegister, /*InsnID*/0, /*TempRegID*/0,
        GIR_SetImplicitDefDead, /*InsnID*/0, /*OpIdx for AMDGPU::SCC*/0,
        GIR_ConstrainSelectedInstOperands, /*InsnID*/0,
        GIR_EraseFromParent, /*InsnID*/0,
        // GIR_Coverage, 6212,
        GIR_Done,
      // Label 4251: @265933
      GIM_Try, /*On fail goto*//*Label 4252*/ GIMT_Encode4(265992), // Rule ID 6228 //
        GIM_CheckRegBankForClass, /*MI*/0, /*Op*/0, /*RC*/GIMT_Encode2(AMDGPU::VGPR_32RegClassID),
        GIM_CheckRegBankForClass, /*MI*/0, /*Op*/1, /*RC*/GIMT_Encode2(AMDGPU::VGPR_32RegClassID),
        // (fabs:{ *:[v2f16] } VGPR_32:{ *:[v2f16] }:$src)  =>  (V_AND_B32_e64:{ *:[v2f16] } (S_MOV_B32:{ *:[i16] } 2147450879:{ *:[i32] }), VGPR_32:{ *:[v2f16] }:$src)
        GIR_MakeTempReg, /*TempRegID*/0, /*TypeID*/GILLT_s16,
        GIR_BuildMI, /*InsnID*/1, /*Opcode*/GIMT_Encode2(AMDGPU::S_MOV_B32),
        GIR_AddTempRegister, /*InsnID*/1, /*TempRegID*/0, /*TempRegFlags*/GIMT_Encode2(RegState::Define),
        GIR_AddImm, /*InsnID*/1, /*Imm*/GIMT_Encode8(2147450879),
        GIR_ConstrainSelectedInstOperands, /*InsnID*/1,
        GIR_BuildMI, /*InsnID*/0, /*Opcode*/GIMT_Encode2(AMDGPU::V_AND_B32_e64),
        GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/0, // DstI[vdst]
        GIR_AddSimpleTempRegister, /*InsnID*/0, /*TempRegID*/0,
        GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/1, // src
        GIR_ConstrainSelectedInstOperands, /*InsnID*/0,
        GIR_EraseFromParent, /*InsnID*/0,
        // GIR_Coverage, 6228,
        GIR_Done,
      // Label 4252: @265992
      GIM_Reject,
    // Label 4250: @265993
    GIM_Reject,
    // Label 4242: @265994
    GIM_Reject,
    // Label 73: @265995
    GIM_SwitchType, /*MI*/0, /*Op*/0, /*[*/GIMT_Encode2(8), GIMT_Encode2(10), /*)*//*default:*//*Label 4255*/ GIMT_Encode4(266639),
    /*GILLT_s16*//*Label 4253*/ GIMT_Encode4(266014),
    /*GILLT_s32*//*Label 4254*/ GIMT_Encode4(266313),
    // Label 4253: @266014
    GIM_Try, /*On fail goto*//*Label 4256*/ GIMT_Encode4(266312),
      GIM_CheckType, /*MI*/0, /*Op*/1, /*Type*/GILLT_s16,
      GIM_Try, /*On fail goto*//*Label 4257*/ GIMT_Encode4(266085), // Rule ID 6234 //
        GIM_CheckType, /*MI*/0, /*Op*/2, /*Type*/GILLT_s16,
        GIM_CheckRegBankForClass, /*MI*/0, /*Op*/0, /*RC*/GIMT_Encode2(AMDGPU::VGPR_32RegClassID),
        // (fcopysign:{ *:[f16] } f16:{ *:[f16] }:$src0, f16:{ *:[f16] }:$src1)  =>  (V_BFI_B32_e64:{ *:[f16] } (S_MOV_B32:{ *:[i16] } 32767:{ *:[i32] }), ?:{ *:[f16] }:$src0, ?:{ *:[f16] }:$src1)
        GIR_MakeTempReg, /*TempRegID*/0, /*TypeID*/GILLT_s16,
        GIR_BuildMI, /*InsnID*/1, /*Opcode*/GIMT_Encode2(AMDGPU::S_MOV_B32),
        GIR_AddTempRegister, /*InsnID*/1, /*TempRegID*/0, /*TempRegFlags*/GIMT_Encode2(RegState::Define),
        GIR_AddImm, /*InsnID*/1, /*Imm*/GIMT_Encode8(32767),
        GIR_ConstrainSelectedInstOperands, /*InsnID*/1,
        GIR_BuildMI, /*InsnID*/0, /*Opcode*/GIMT_Encode2(AMDGPU::V_BFI_B32_e64),
        GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/0, // DstI[vdst]
        GIR_AddSimpleTempRegister, /*InsnID*/0, /*TempRegID*/0,
        GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/1, // src0
        GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/2, // src1
        GIR_ConstrainSelectedInstOperands, /*InsnID*/0,
        GIR_EraseFromParent, /*InsnID*/0,
        // GIR_Coverage, 6234,
        GIR_Done,
      // Label 4257: @266085
      GIM_Try, /*On fail goto*//*Label 4258*/ GIMT_Encode4(266167), // Rule ID 6237 //
        GIM_CheckType, /*MI*/0, /*Op*/2, /*Type*/GILLT_s32,
        GIM_CheckRegBankForClass, /*MI*/0, /*Op*/0, /*RC*/GIMT_Encode2(AMDGPU::VGPR_32RegClassID),
        // (fcopysign:{ *:[f16] } f16:{ *:[f16] }:$src0, f32:{ *:[f32] }:$src1)  =>  (V_BFI_B32_e64:{ *:[f16] } (S_MOV_B32:{ *:[i16] } 32767:{ *:[i32] }), ?:{ *:[f16] }:$src0, (V_LSHRREV_B32_e64:{ *:[i16] } 16:{ *:[i32] }, ?:{ *:[f32] }:$src1))
        GIR_MakeTempReg, /*TempRegID*/0, /*TypeID*/GILLT_s16,
        GIR_MakeTempReg, /*TempRegID*/1, /*TypeID*/GILLT_s16,
        GIR_BuildMI, /*InsnID*/2, /*Opcode*/GIMT_Encode2(AMDGPU::V_LSHRREV_B32_e64),
        GIR_AddTempRegister, /*InsnID*/2, /*TempRegID*/1, /*TempRegFlags*/GIMT_Encode2(RegState::Define),
        GIR_AddImm8, /*InsnID*/2, /*Imm*/16,
        GIR_Copy, /*NewInsnID*/2, /*OldInsnID*/0, /*OpIdx*/2, // src1
        GIR_ConstrainSelectedInstOperands, /*InsnID*/2,
        GIR_BuildMI, /*InsnID*/1, /*Opcode*/GIMT_Encode2(AMDGPU::S_MOV_B32),
        GIR_AddTempRegister, /*InsnID*/1, /*TempRegID*/0, /*TempRegFlags*/GIMT_Encode2(RegState::Define),
        GIR_AddImm, /*InsnID*/1, /*Imm*/GIMT_Encode8(32767),
        GIR_ConstrainSelectedInstOperands, /*InsnID*/1,
        GIR_BuildMI, /*InsnID*/0, /*Opcode*/GIMT_Encode2(AMDGPU::V_BFI_B32_e64),
        GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/0, // DstI[vdst]
        GIR_AddSimpleTempRegister, /*InsnID*/0, /*TempRegID*/0,
        GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/1, // src0
        GIR_AddSimpleTempRegister, /*InsnID*/0, /*TempRegID*/1,
        GIR_ConstrainSelectedInstOperands, /*InsnID*/0,
        GIR_EraseFromParent, /*InsnID*/0,
        // GIR_Coverage, 6237,
        GIR_Done,
      // Label 4258: @266167
      GIM_Try, /*On fail goto*//*Label 4259*/ GIMT_Encode4(266229), // Rule ID 6239 //
        GIM_CheckType, /*MI*/0, /*Op*/2, /*Type*/GILLT_s16,
        GIM_CheckRegBankForClass, /*MI*/0, /*Op*/0, /*RC*/GIMT_Encode2(AMDGPU::VGPR_32RegClassID),
        // (fcopysign:{ *:[bf16] } bf16:{ *:[bf16] }:$src0, bf16:{ *:[bf16] }:$src1)  =>  (V_BFI_B32_e64:{ *:[bf16] } (S_MOV_B32:{ *:[i16] } 32767:{ *:[i32] }), ?:{ *:[bf16] }:$src0, ?:{ *:[bf16] }:$src1)
        GIR_MakeTempReg, /*TempRegID*/0, /*TypeID*/GILLT_s16,
        GIR_BuildMI, /*InsnID*/1, /*Opcode*/GIMT_Encode2(AMDGPU::S_MOV_B32),
        GIR_AddTempRegister, /*InsnID*/1, /*TempRegID*/0, /*TempRegFlags*/GIMT_Encode2(RegState::Define),
        GIR_AddImm, /*InsnID*/1, /*Imm*/GIMT_Encode8(32767),
        GIR_ConstrainSelectedInstOperands, /*InsnID*/1,
        GIR_BuildMI, /*InsnID*/0, /*Opcode*/GIMT_Encode2(AMDGPU::V_BFI_B32_e64),
        GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/0, // DstI[vdst]
        GIR_AddSimpleTempRegister, /*InsnID*/0, /*TempRegID*/0,
        GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/1, // src0
        GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/2, // src1
        GIR_ConstrainSelectedInstOperands, /*InsnID*/0,
        GIR_EraseFromParent, /*InsnID*/0,
        // GIR_Coverage, 6239,
        GIR_Done,
      // Label 4259: @266229
      GIM_Try, /*On fail goto*//*Label 4260*/ GIMT_Encode4(266311), // Rule ID 6242 //
        GIM_CheckType, /*MI*/0, /*Op*/2, /*Type*/GILLT_s32,
        GIM_CheckRegBankForClass, /*MI*/0, /*Op*/0, /*RC*/GIMT_Encode2(AMDGPU::VGPR_32RegClassID),
        // (fcopysign:{ *:[bf16] } bf16:{ *:[bf16] }:$src0, f32:{ *:[f32] }:$src1)  =>  (V_BFI_B32_e64:{ *:[bf16] } (S_MOV_B32:{ *:[i16] } 32767:{ *:[i32] }), ?:{ *:[bf16] }:$src0, (V_LSHRREV_B32_e64:{ *:[i16] } 16:{ *:[i32] }, ?:{ *:[f32] }:$src1))
        GIR_MakeTempReg, /*TempRegID*/0, /*TypeID*/GILLT_s16,
        GIR_MakeTempReg, /*TempRegID*/1, /*TypeID*/GILLT_s16,
        GIR_BuildMI, /*InsnID*/2, /*Opcode*/GIMT_Encode2(AMDGPU::V_LSHRREV_B32_e64),
        GIR_AddTempRegister, /*InsnID*/2, /*TempRegID*/1, /*TempRegFlags*/GIMT_Encode2(RegState::Define),
        GIR_AddImm8, /*InsnID*/2, /*Imm*/16,
        GIR_Copy, /*NewInsnID*/2, /*OldInsnID*/0, /*OpIdx*/2, // src1
        GIR_ConstrainSelectedInstOperands, /*InsnID*/2,
        GIR_BuildMI, /*InsnID*/1, /*Opcode*/GIMT_Encode2(AMDGPU::S_MOV_B32),
        GIR_AddTempRegister, /*InsnID*/1, /*TempRegID*/0, /*TempRegFlags*/GIMT_Encode2(RegState::Define),
        GIR_AddImm, /*InsnID*/1, /*Imm*/GIMT_Encode8(32767),
        GIR_ConstrainSelectedInstOperands, /*InsnID*/1,
        GIR_BuildMI, /*InsnID*/0, /*Opcode*/GIMT_Encode2(AMDGPU::V_BFI_B32_e64),
        GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/0, // DstI[vdst]
        GIR_AddSimpleTempRegister, /*InsnID*/0, /*TempRegID*/0,
        GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/1, // src0
        GIR_AddSimpleTempRegister, /*InsnID*/0, /*TempRegID*/1,
        GIR_ConstrainSelectedInstOperands, /*InsnID*/0,
        GIR_EraseFromParent, /*InsnID*/0,
        // GIR_Coverage, 6242,
        GIR_Done,
      // Label 4260: @266311
      GIM_Reject,
    // Label 4256: @266312
    GIM_Reject,
    // Label 4254: @266313
    GIM_Try, /*On fail goto*//*Label 4261*/ GIMT_Encode4(266638),
      GIM_CheckType, /*MI*/0, /*Op*/1, /*Type*/GILLT_s32,
      GIM_Try, /*On fail goto*//*Label 4262*/ GIMT_Encode4(266404), // Rule ID 6235 //
        GIM_CheckType, /*MI*/0, /*Op*/2, /*Type*/GILLT_s16,
        GIM_CheckRegBankForClass, /*MI*/0, /*Op*/0, /*RC*/GIMT_Encode2(AMDGPU::VGPR_32RegClassID),
        // (fcopysign:{ *:[f32] } f32:{ *:[f32] }:$src0, f16:{ *:[f16] }:$src1)  =>  (V_BFI_B32_e64:{ *:[f32] } (S_MOV_B32:{ *:[i16] } 2147483647:{ *:[i32] }), ?:{ *:[f32] }:$src0, (V_LSHLREV_B32_e64:{ *:[i16] } 16:{ *:[i32] }, ?:{ *:[f16] }:$src1))
        GIR_MakeTempReg, /*TempRegID*/0, /*TypeID*/GILLT_s16,
        GIR_MakeTempReg, /*TempRegID*/1, /*TypeID*/GILLT_s16,
        GIR_BuildMI, /*InsnID*/2, /*Opcode*/GIMT_Encode2(AMDGPU::V_LSHLREV_B32_e64),
        GIR_AddTempRegister, /*InsnID*/2, /*TempRegID*/1, /*TempRegFlags*/GIMT_Encode2(RegState::Define),
        GIR_AddImm8, /*InsnID*/2, /*Imm*/16,
        GIR_Copy, /*NewInsnID*/2, /*OldInsnID*/0, /*OpIdx*/2, // src1
        GIR_ConstrainSelectedInstOperands, /*InsnID*/2,
        GIR_BuildMI, /*InsnID*/1, /*Opcode*/GIMT_Encode2(AMDGPU::S_MOV_B32),
        GIR_AddTempRegister, /*InsnID*/1, /*TempRegID*/0, /*TempRegFlags*/GIMT_Encode2(RegState::Define),
        GIR_AddImm, /*InsnID*/1, /*Imm*/GIMT_Encode8(2147483647),
        GIR_ConstrainSelectedInstOperands, /*InsnID*/1,
        GIR_BuildMI, /*InsnID*/0, /*Opcode*/GIMT_Encode2(AMDGPU::V_BFI_B32_e64),
        GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/0, // DstI[vdst]
        GIR_AddSimpleTempRegister, /*InsnID*/0, /*TempRegID*/0,
        GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/1, // src0
        GIR_AddSimpleTempRegister, /*InsnID*/0, /*TempRegID*/1,
        GIR_ConstrainSelectedInstOperands, /*InsnID*/0,
        GIR_EraseFromParent, /*InsnID*/0,
        // GIR_Coverage, 6235,
        GIR_Done,
      // Label 4262: @266404
      GIM_Try, /*On fail goto*//*Label 4263*/ GIMT_Encode4(266486), // Rule ID 6240 //
        GIM_CheckType, /*MI*/0, /*Op*/2, /*Type*/GILLT_s16,
        GIM_CheckRegBankForClass, /*MI*/0, /*Op*/0, /*RC*/GIMT_Encode2(AMDGPU::VGPR_32RegClassID),
        // (fcopysign:{ *:[f32] } f32:{ *:[f32] }:$src0, bf16:{ *:[bf16] }:$src1)  =>  (V_BFI_B32_e64:{ *:[f32] } (S_MOV_B32:{ *:[i16] } 2147483647:{ *:[i32] }), ?:{ *:[f32] }:$src0, (V_LSHLREV_B32_e64:{ *:[i16] } 16:{ *:[i32] }, ?:{ *:[bf16] }:$src1))
        GIR_MakeTempReg, /*TempRegID*/0, /*TypeID*/GILLT_s16,
        GIR_MakeTempReg, /*TempRegID*/1, /*TypeID*/GILLT_s16,
        GIR_BuildMI, /*InsnID*/2, /*Opcode*/GIMT_Encode2(AMDGPU::V_LSHLREV_B32_e64),
        GIR_AddTempRegister, /*InsnID*/2, /*TempRegID*/1, /*TempRegFlags*/GIMT_Encode2(RegState::Define),
        GIR_AddImm8, /*InsnID*/2, /*Imm*/16,
        GIR_Copy, /*NewInsnID*/2, /*OldInsnID*/0, /*OpIdx*/2, // src1
        GIR_ConstrainSelectedInstOperands, /*InsnID*/2,
        GIR_BuildMI, /*InsnID*/1, /*Opcode*/GIMT_Encode2(AMDGPU::S_MOV_B32),
        GIR_AddTempRegister, /*InsnID*/1, /*TempRegID*/0, /*TempRegFlags*/GIMT_Encode2(RegState::Define),
        GIR_AddImm, /*InsnID*/1, /*Imm*/GIMT_Encode8(2147483647),
        GIR_ConstrainSelectedInstOperands, /*InsnID*/1,
        GIR_BuildMI, /*InsnID*/0, /*Opcode*/GIMT_Encode2(AMDGPU::V_BFI_B32_e64),
        GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/0, // DstI[vdst]
        GIR_AddSimpleTempRegister, /*InsnID*/0, /*TempRegID*/0,
        GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/1, // src0
        GIR_AddSimpleTempRegister, /*InsnID*/0, /*TempRegID*/1,
        GIR_ConstrainSelectedInstOperands, /*InsnID*/0,
        GIR_EraseFromParent, /*InsnID*/0,
        // GIR_Coverage, 6240,
        GIR_Done,
      // Label 4263: @266486
      GIM_Try, /*On fail goto*//*Label 4264*/ GIMT_Encode4(266548), // Rule ID 6278 //
        GIM_CheckType, /*MI*/0, /*Op*/2, /*Type*/GILLT_s32,
        GIM_CheckRegBankForClass, /*MI*/0, /*Op*/0, /*RC*/GIMT_Encode2(AMDGPU::VGPR_32RegClassID),
        // (fcopysign:{ *:[f32] } f32:{ *:[f32] }:$src0, f32:{ *:[f32] }:$src1)  =>  (V_BFI_B32_e64:{ *:[f32] } (S_MOV_B32:{ *:[i16] } 2147483647:{ *:[i32] }), ?:{ *:[f32] }:$src0, ?:{ *:[f32] }:$src1)
        GIR_MakeTempReg, /*TempRegID*/0, /*TypeID*/GILLT_s16,
        GIR_BuildMI, /*InsnID*/1, /*Opcode*/GIMT_Encode2(AMDGPU::S_MOV_B32),
        GIR_AddTempRegister, /*InsnID*/1, /*TempRegID*/0, /*TempRegFlags*/GIMT_Encode2(RegState::Define),
        GIR_AddImm, /*InsnID*/1, /*Imm*/GIMT_Encode8(2147483647),
        GIR_ConstrainSelectedInstOperands, /*InsnID*/1,
        GIR_BuildMI, /*InsnID*/0, /*Opcode*/GIMT_Encode2(AMDGPU::V_BFI_B32_e64),
        GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/0, // DstI[vdst]
        GIR_AddSimpleTempRegister, /*InsnID*/0, /*TempRegID*/0,
        GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/1, // src0
        GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/2, // src1
        GIR_ConstrainSelectedInstOperands, /*InsnID*/0,
        GIR_EraseFromParent, /*InsnID*/0,
        // GIR_Coverage, 6278,
        GIR_Done,
      // Label 4264: @266548
      GIM_Try, /*On fail goto*//*Label 4265*/ GIMT_Encode4(266637), // Rule ID 6279 //
        GIM_CheckType, /*MI*/0, /*Op*/2, /*Type*/GILLT_s64,
        GIM_CheckRegBankForClass, /*MI*/0, /*Op*/0, /*RC*/GIMT_Encode2(AMDGPU::VGPR_32RegClassID),
        // (fcopysign:{ *:[f32] } f32:{ *:[f32] }:$src0, f64:{ *:[f64] }:$src1)  =>  (V_BFI_B32_e64:{ *:[f32] } (S_MOV_B32:{ *:[i16] } 2147483647:{ *:[i32] }), ?:{ *:[f32] }:$src0, (EXTRACT_SUBREG:{ *:[i32] } SReg_64:{ *:[f64] }:$src1, sub1:{ *:[i32] }))
        GIR_MakeTempReg, /*TempRegID*/0, /*TypeID*/GILLT_s16,
        GIR_MakeTempReg, /*TempRegID*/1, /*TypeID*/GILLT_s32,
        GIR_BuildMI, /*InsnID*/2, /*Opcode*/GIMT_Encode2(TargetOpcode::COPY),
        GIR_AddTempRegister, /*InsnID*/2, /*TempRegID*/1, /*TempRegFlags*/GIMT_Encode2(RegState::Define),
        GIR_CopySubReg, /*NewInsnID*/2, /*OldInsnID*/0, /*OpIdx*/2, /*SubRegIdx*/GIMT_Encode2(11), // src1
        GIR_ConstrainOperandRC, /*InsnID*/2, /*Op*/0, GIMT_Encode2(AMDGPU::SReg_32_XM0RegClassID),
        GIR_ConstrainOperandRC, /*InsnID*/2, /*Op*/1, GIMT_Encode2(AMDGPU::SReg_64RegClassID),
        GIR_BuildMI, /*InsnID*/1, /*Opcode*/GIMT_Encode2(AMDGPU::S_MOV_B32),
        GIR_AddTempRegister, /*InsnID*/1, /*TempRegID*/0, /*TempRegFlags*/GIMT_Encode2(RegState::Define),
        GIR_AddImm, /*InsnID*/1, /*Imm*/GIMT_Encode8(2147483647),
        GIR_ConstrainSelectedInstOperands, /*InsnID*/1,
        GIR_BuildMI, /*InsnID*/0, /*Opcode*/GIMT_Encode2(AMDGPU::V_BFI_B32_e64),
        GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/0, // DstI[vdst]
        GIR_AddSimpleTempRegister, /*InsnID*/0, /*TempRegID*/0,
        GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/1, // src0
        GIR_AddSimpleTempRegister, /*InsnID*/0, /*TempRegID*/1,
        GIR_ConstrainSelectedInstOperands, /*InsnID*/0,
        GIR_EraseFromParent, /*InsnID*/0,
        // GIR_Coverage, 6279,
        GIR_Done,
      // Label 4265: @266637
      GIM_Reject,
    // Label 4261: @266638
    GIM_Reject,
    // Label 4255: @266639
    GIM_Reject,
    // Label 74: @266640
    GIM_Try, /*On fail goto*//*Label 4266*/ GIMT_Encode4(266936),
      GIM_CheckType, /*MI*/0, /*Op*/0, /*Type*/GILLT_s1,
      GIM_SwitchType, /*MI*/0, /*Op*/1, /*[*/GIMT_Encode2(8), GIMT_Encode2(11), /*)*//*default:*//*Label 4270*/ GIMT_Encode4(266935),
      /*GILLT_s16*//*Label 4267*/ GIMT_Encode4(266672),
      /*GILLT_s32*//*Label 4268*/ GIMT_Encode4(266805),
      /*GILLT_s64*//*Label 4269*/ GIMT_Encode4(266870),
      // Label 4267: @266672
      GIM_Try, /*On fail goto*//*Label 4271*/ GIMT_Encode4(266804),
        GIM_CheckRegBankForClass, /*MI*/0, /*Op*/0, /*RC*/GIMT_Encode2(AMDGPU::SReg_1RegClassID),
        GIM_CheckIsImm, /*MI*/0, /*Op*/2,
        GIM_Try, /*On fail goto*//*Label 4272*/ GIMT_Encode4(266744), // Rule ID 2401 //
          GIM_CheckFeatures, GIMT_Encode2(GIFBS_Has16BitInsts_NotHasTrue16BitInsts),
          GIM_CheckComplexPattern, /*MI*/0, /*Op*/1, /*Renderer*/GIMT_Encode2(0), GIMT_Encode2(GICP_gi_vop3modsnoncanonicalizing),
          // (is_fpclass:{ *:[i1] } (VOP3ModsNonCanonicalizing:{ *:[f16] } f16:{ *:[f16] }:$src0, i32:{ *:[i32] }:$src0_mods), (timm:{ *:[i32] }):$mask)  =>  (V_CMP_CLASS_F16_e64:{ *:[i1] } i32:{ *:[i32] }:$src0_mods, f16:{ *:[f16] }:$src0, (V_MOV_B32_e32:{ *:[i16] } (timm:{ *:[i32] }):$mask))
          GIR_MakeTempReg, /*TempRegID*/0, /*TypeID*/GILLT_s16,
          GIR_BuildMI, /*InsnID*/1, /*Opcode*/GIMT_Encode2(AMDGPU::V_MOV_B32_e32),
          GIR_AddTempRegister, /*InsnID*/1, /*TempRegID*/0, /*TempRegFlags*/GIMT_Encode2(RegState::Define),
          GIR_Copy, /*NewInsnID*/1, /*OldInsnID*/0, /*OpIdx*/2, // mask
          GIR_ConstrainSelectedInstOperands, /*InsnID*/1,
          GIR_BuildMI, /*InsnID*/0, /*Opcode*/GIMT_Encode2(AMDGPU::V_CMP_CLASS_F16_e64),
          GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/0, // DstI[sdst]
          GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/1, // src0_mods
          GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/0, // src0
          GIR_AddSimpleTempRegister, /*InsnID*/0, /*TempRegID*/0,
          GIR_ConstrainSelectedInstOperands, /*InsnID*/0,
          GIR_EraseFromParent, /*InsnID*/0,
          // GIR_Coverage, 2401,
          GIR_Done,
        // Label 4272: @266744
        GIM_Try, /*On fail goto*//*Label 4273*/ GIMT_Encode4(266803), // Rule ID 2402 //
          GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasTrue16BitInsts),
          GIM_CheckComplexPattern, /*MI*/0, /*Op*/1, /*Renderer*/GIMT_Encode2(0), GIMT_Encode2(GICP_gi_vop3modsnoncanonicalizing),
          // (is_fpclass:{ *:[i1] } (VOP3ModsNonCanonicalizing:{ *:[f16] } f16:{ *:[f16] }:$src0, i32:{ *:[i32] }:$src0_mods), (timm:{ *:[i32] }):$mask)  =>  (V_CMP_CLASS_F16_t16_e64:{ *:[i1] } i32:{ *:[i32] }:$src0_mods, f16:{ *:[f16] }:$src0, (V_MOV_B32_e32:{ *:[i16] } (timm:{ *:[i32] }):$mask))
          GIR_MakeTempReg, /*TempRegID*/0, /*TypeID*/GILLT_s16,
          GIR_BuildMI, /*InsnID*/1, /*Opcode*/GIMT_Encode2(AMDGPU::V_MOV_B32_e32),
          GIR_AddTempRegister, /*InsnID*/1, /*TempRegID*/0, /*TempRegFlags*/GIMT_Encode2(RegState::Define),
          GIR_Copy, /*NewInsnID*/1, /*OldInsnID*/0, /*OpIdx*/2, // mask
          GIR_ConstrainSelectedInstOperands, /*InsnID*/1,
          GIR_BuildMI, /*InsnID*/0, /*Opcode*/GIMT_Encode2(AMDGPU::V_CMP_CLASS_F16_t16_e64),
          GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/0, // DstI[sdst]
          GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/1, // src0_mods
          GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/0, // src0
          GIR_AddSimpleTempRegister, /*InsnID*/0, /*TempRegID*/0,
          GIR_ConstrainSelectedInstOperands, /*InsnID*/0,
          GIR_EraseFromParent, /*InsnID*/0,
          // GIR_Coverage, 2402,
          GIR_Done,
        // Label 4273: @266803
        GIM_Reject,
      // Label 4271: @266804
      GIM_Reject,
      // Label 4268: @266805
      GIM_Try, /*On fail goto*//*Label 4274*/ GIMT_Encode4(266869), // Rule ID 2403 //
        GIM_CheckRegBankForClass, /*MI*/0, /*Op*/0, /*RC*/GIMT_Encode2(AMDGPU::SReg_1RegClassID),
        // MIs[0] mask
        GIM_CheckIsImm, /*MI*/0, /*Op*/2,
        GIM_CheckComplexPattern, /*MI*/0, /*Op*/1, /*Renderer*/GIMT_Encode2(0), GIMT_Encode2(GICP_gi_vop3modsnoncanonicalizing),
        // (is_fpclass:{ *:[i1] } (VOP3ModsNonCanonicalizing:{ *:[f32] } f32:{ *:[f32] }:$src0, i32:{ *:[i32] }:$src0_mods), (timm:{ *:[i32] }):$mask)  =>  (V_CMP_CLASS_F32_e64:{ *:[i1] } i32:{ *:[i32] }:$src0_mods, f32:{ *:[f32] }:$src0, (V_MOV_B32_e32:{ *:[i16] } (timm:{ *:[i32] }):$mask))
        GIR_MakeTempReg, /*TempRegID*/0, /*TypeID*/GILLT_s16,
        GIR_BuildMI, /*InsnID*/1, /*Opcode*/GIMT_Encode2(AMDGPU::V_MOV_B32_e32),
        GIR_AddTempRegister, /*InsnID*/1, /*TempRegID*/0, /*TempRegFlags*/GIMT_Encode2(RegState::Define),
        GIR_Copy, /*NewInsnID*/1, /*OldInsnID*/0, /*OpIdx*/2, // mask
        GIR_ConstrainSelectedInstOperands, /*InsnID*/1,
        GIR_BuildMI, /*InsnID*/0, /*Opcode*/GIMT_Encode2(AMDGPU::V_CMP_CLASS_F32_e64),
        GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/0, // DstI[sdst]
        GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/1, // src0_mods
        GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/0, // src0
        GIR_AddSimpleTempRegister, /*InsnID*/0, /*TempRegID*/0,
        GIR_ConstrainSelectedInstOperands, /*InsnID*/0,
        GIR_EraseFromParent, /*InsnID*/0,
        // GIR_Coverage, 2403,
        GIR_Done,
      // Label 4274: @266869
      GIM_Reject,
      // Label 4269: @266870
      GIM_Try, /*On fail goto*//*Label 4275*/ GIMT_Encode4(266934), // Rule ID 2404 //
        GIM_CheckRegBankForClass, /*MI*/0, /*Op*/0, /*RC*/GIMT_Encode2(AMDGPU::SReg_1RegClassID),
        // MIs[0] mask
        GIM_CheckIsImm, /*MI*/0, /*Op*/2,
        GIM_CheckComplexPattern, /*MI*/0, /*Op*/1, /*Renderer*/GIMT_Encode2(0), GIMT_Encode2(GICP_gi_vop3modsnoncanonicalizing),
        // (is_fpclass:{ *:[i1] } (VOP3ModsNonCanonicalizing:{ *:[f64] } f64:{ *:[f64] }:$src0, i32:{ *:[i32] }:$src0_mods), (timm:{ *:[i32] }):$mask)  =>  (V_CMP_CLASS_F64_e64:{ *:[i1] } i32:{ *:[i32] }:$src0_mods, f64:{ *:[f64] }:$src0, (V_MOV_B32_e32:{ *:[i16] } (timm:{ *:[i32] }):$mask))
        GIR_MakeTempReg, /*TempRegID*/0, /*TypeID*/GILLT_s16,
        GIR_BuildMI, /*InsnID*/1, /*Opcode*/GIMT_Encode2(AMDGPU::V_MOV_B32_e32),
        GIR_AddTempRegister, /*InsnID*/1, /*TempRegID*/0, /*TempRegFlags*/GIMT_Encode2(RegState::Define),
        GIR_Copy, /*NewInsnID*/1, /*OldInsnID*/0, /*OpIdx*/2, // mask
        GIR_ConstrainSelectedInstOperands, /*InsnID*/1,
        GIR_BuildMI, /*InsnID*/0, /*Opcode*/GIMT_Encode2(AMDGPU::V_CMP_CLASS_F64_e64),
        GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/0, // DstI[sdst]
        GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/1, // src0_mods
        GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/0, // src0
        GIR_AddSimpleTempRegister, /*InsnID*/0, /*TempRegID*/0,
        GIR_ConstrainSelectedInstOperands, /*InsnID*/0,
        GIR_EraseFromParent, /*InsnID*/0,
        // GIR_Coverage, 2404,
        GIR_Done,
      // Label 4275: @266934
      GIM_Reject,
      // Label 4270: @266935
      GIM_Reject,
    // Label 4266: @266936
    GIM_Reject,
    // Label 75: @266937
    GIM_SwitchType, /*MI*/0, /*Op*/0, /*[*/GIMT_Encode2(8), GIMT_Encode2(13), /*)*//*default:*//*Label 4281*/ GIMT_Encode4(268272),
    /*GILLT_s16*//*Label 4276*/ GIMT_Encode4(266968),
    /*GILLT_s32*//*Label 4277*/ GIMT_Encode4(267456),
    /*GILLT_s64*//*Label 4278*/ GIMT_Encode4(267702),
    /*GILLT_v2s16*//*Label 4279*/ GIMT_Encode4(267991),
    /*GILLT_v2s32*//*Label 4280*/ GIMT_Encode4(268196),
    // Label 4276: @266968
    GIM_Try, /*On fail goto*//*Label 4282*/ GIMT_Encode4(267455),
      GIM_CheckType, /*MI*/0, /*Op*/1, /*Type*/GILLT_s16,
      GIM_CheckRegBankForClass, /*MI*/0, /*Op*/0, /*RC*/GIMT_Encode2(AMDGPU::VGPR_32RegClassID),
      GIM_Try, /*On fail goto*//*Label 4283*/ GIMT_Encode4(267036), // Rule ID 6412 //
        GIM_CheckFeatures, GIMT_Encode2(GIFBS_Has16BitInsts_HasMinMaxDenormModes_NotHasTrue16BitInsts),
        GIM_CheckComplexPattern, /*MI*/0, /*Op*/1, /*Renderer*/GIMT_Encode2(0), GIMT_Encode2(GICP_gi_vop3mods),
        // (fcanonicalize:{ *:[f16] } (VOP3Mods:{ *:[f16] } f16:{ *:[f16] }:$src, i32:{ *:[i32] }:$src_mods))  =>  (V_MAX_F16_e64:{ *:[f16] } ?:{ *:[i32] }:$src_mods, ?:{ *:[f16] }:$src, ?:{ *:[i32] }:$src_mods, ?:{ *:[f16] }:$src, 0:{ *:[i1] }, 0:{ *:[i32] })
        GIR_BuildMI, /*InsnID*/0, /*Opcode*/GIMT_Encode2(AMDGPU::V_MAX_F16_e64),
        GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/0, // DstI[vdst]
        GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/1, // src_mods
        GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/0, // src
        GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/1, // src_mods
        GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/0, // src
        GIR_AddImm8, /*InsnID*/0, /*Imm*/0,
        GIR_AddImm8, /*InsnID*/0, /*Imm*/0,
        GIR_ConstrainSelectedInstOperands, /*InsnID*/0,
        GIR_EraseFromParent, /*InsnID*/0,
        // GIR_Coverage, 6412,
        GIR_Done,
      // Label 4283: @267036
      GIM_Try, /*On fail goto*//*Label 4284*/ GIMT_Encode4(267090), // Rule ID 6413 //
        GIM_CheckFeatures, GIMT_Encode2(GIFBS_Has16BitInsts_HasMinMaxDenormModes_HasTrue16BitInsts),
        GIM_CheckComplexPattern, /*MI*/0, /*Op*/1, /*Renderer*/GIMT_Encode2(0), GIMT_Encode2(GICP_gi_vop3mods),
        // (fcanonicalize:{ *:[f16] } (VOP3Mods:{ *:[f16] } f16:{ *:[f16] }:$src, i32:{ *:[i32] }:$src_mods))  =>  (V_MAX_F16_fake16_e64:{ *:[f16] } ?:{ *:[i32] }:$src_mods, ?:{ *:[f16] }:$src, ?:{ *:[i32] }:$src_mods, ?:{ *:[f16] }:$src, 0:{ *:[i1] }, 0:{ *:[i32] })
        GIR_BuildMI, /*InsnID*/0, /*Opcode*/GIMT_Encode2(AMDGPU::V_MAX_F16_fake16_e64),
        GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/0, // DstI[vdst]
        GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/1, // src_mods
        GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/0, // src
        GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/1, // src_mods
        GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/0, // src
        GIR_AddImm8, /*InsnID*/0, /*Imm*/0,
        GIR_AddImm8, /*InsnID*/0, /*Imm*/0,
        GIR_ConstrainSelectedInstOperands, /*InsnID*/0,
        GIR_EraseFromParent, /*InsnID*/0,
        // GIR_Coverage, 6413,
        GIR_Done,
      // Label 4284: @267090
      GIM_Try, /*On fail goto*//*Label 4285*/ GIMT_Encode4(267144), // Rule ID 6418 //
        GIM_CheckFeatures, GIMT_Encode2(GIFBS_FP16Denormals_Has16BitInsts_NotHasMinMaxDenormModes_NotHasTrue16BitInsts),
        GIM_CheckComplexPattern, /*MI*/0, /*Op*/1, /*Renderer*/GIMT_Encode2(0), GIMT_Encode2(GICP_gi_vop3mods),
        // (fcanonicalize:{ *:[f16] } (VOP3Mods:{ *:[f16] } f16:{ *:[f16] }:$src, i32:{ *:[i32] }:$src_mods))  =>  (V_MAX_F16_e64:{ *:[f16] } ?:{ *:[i32] }:$src_mods, ?:{ *:[f16] }:$src, ?:{ *:[i32] }:$src_mods, ?:{ *:[f16] }:$src, 0:{ *:[i1] }, 0:{ *:[i32] })
        GIR_BuildMI, /*InsnID*/0, /*Opcode*/GIMT_Encode2(AMDGPU::V_MAX_F16_e64),
        GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/0, // DstI[vdst]
        GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/1, // src_mods
        GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/0, // src
        GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/1, // src_mods
        GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/0, // src
        GIR_AddImm8, /*InsnID*/0, /*Imm*/0,
        GIR_AddImm8, /*InsnID*/0, /*Imm*/0,
        GIR_ConstrainSelectedInstOperands, /*InsnID*/0,
        GIR_EraseFromParent, /*InsnID*/0,
        // GIR_Coverage, 6418,
        GIR_Done,
      // Label 4285: @267144
      GIM_Try, /*On fail goto*//*Label 4286*/ GIMT_Encode4(267198), // Rule ID 6419 //
        GIM_CheckFeatures, GIMT_Encode2(GIFBS_FP16Denormals_Has16BitInsts_HasTrue16BitInsts_NotHasMinMaxDenormModes),
        GIM_CheckComplexPattern, /*MI*/0, /*Op*/1, /*Renderer*/GIMT_Encode2(0), GIMT_Encode2(GICP_gi_vop3mods),
        // (fcanonicalize:{ *:[f16] } (VOP3Mods:{ *:[f16] } f16:{ *:[f16] }:$src, i32:{ *:[i32] }:$src_mods))  =>  (V_MAX_F16_fake16_e64:{ *:[f16] } ?:{ *:[i32] }:$src_mods, ?:{ *:[f16] }:$src, ?:{ *:[i32] }:$src_mods, ?:{ *:[f16] }:$src, 0:{ *:[i1] }, 0:{ *:[i32] })
        GIR_BuildMI, /*InsnID*/0, /*Opcode*/GIMT_Encode2(AMDGPU::V_MAX_F16_fake16_e64),
        GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/0, // DstI[vdst]
        GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/1, // src_mods
        GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/0, // src
        GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/1, // src_mods
        GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/0, // src
        GIR_AddImm8, /*InsnID*/0, /*Imm*/0,
        GIR_AddImm8, /*InsnID*/0, /*Imm*/0,
        GIR_ConstrainSelectedInstOperands, /*InsnID*/0,
        GIR_EraseFromParent, /*InsnID*/0,
        // GIR_Coverage, 6419,
        GIR_Done,
      // Label 4286: @267198
      GIM_Try, /*On fail goto*//*Label 4287*/ GIMT_Encode4(267269), // Rule ID 6401 //
        GIM_CheckFeatures, GIMT_Encode2(GIFBS_NotHasTrue16BitInsts),
        GIM_RecordInsn, /*DefineMI*/1, /*MI*/0, /*OpIdx*/1, // MIs[1]
        GIM_CheckOpcode, /*MI*/1, GIMT_Encode2(TargetOpcode::G_FNEG),
        GIM_CheckType, /*MI*/1, /*Op*/1, /*Type*/GILLT_s16,
        GIM_CheckIsSafeToFold, /*InsnID*/1,
        GIM_CheckComplexPattern, /*MI*/1, /*Op*/1, /*Renderer*/GIMT_Encode2(0), GIMT_Encode2(GICP_gi_vop3mods),
        // (fcanonicalize:{ *:[f16] } (fneg:{ *:[f16] } (VOP3Mods:{ *:[f16] } f16:{ *:[f16] }:$src, i32:{ *:[i32] }:$src_mods)))  =>  (V_MUL_F16_e64:{ *:[f16] } 0:{ *:[i32] }, 48128:{ *:[i32] }, ?:{ *:[i32] }:$src_mods, ?:{ *:[f16] }:$src)
        GIR_BuildMI, /*InsnID*/0, /*Opcode*/GIMT_Encode2(AMDGPU::V_MUL_F16_e64),
        GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/0, // DstI[vdst]
        GIR_AddImm8, /*InsnID*/0, /*Imm*/0,
        GIR_AddImm, /*InsnID*/0, /*Imm*/GIMT_Encode8(48128),
        GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/1, // src_mods
        GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/0, // src
        GIR_AddImm8, /*InsnID*/0, /*Imm*/0,
        GIR_AddImm8, /*InsnID*/0, /*Imm*/0,
        GIR_ConstrainSelectedInstOperands, /*InsnID*/0,
        GIR_EraseFromParent, /*InsnID*/0,
        // GIR_Coverage, 6401,
        GIR_Done,
      // Label 4287: @267269
      GIM_Try, /*On fail goto*//*Label 4288*/ GIMT_Encode4(267340), // Rule ID 6403 //
        GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasTrue16BitInsts),
        GIM_RecordInsn, /*DefineMI*/1, /*MI*/0, /*OpIdx*/1, // MIs[1]
        GIM_CheckOpcode, /*MI*/1, GIMT_Encode2(TargetOpcode::G_FNEG),
        GIM_CheckType, /*MI*/1, /*Op*/1, /*Type*/GILLT_s16,
        GIM_CheckIsSafeToFold, /*InsnID*/1,
        GIM_CheckComplexPattern, /*MI*/1, /*Op*/1, /*Renderer*/GIMT_Encode2(0), GIMT_Encode2(GICP_gi_vop3mods),
        // (fcanonicalize:{ *:[f16] } (fneg:{ *:[f16] } (VOP3Mods:{ *:[f16] } f16:{ *:[f16] }:$src, i32:{ *:[i32] }:$src_mods)))  =>  (V_MUL_F16_fake16_e64:{ *:[f16] } 0:{ *:[i32] }, 48128:{ *:[i32] }, ?:{ *:[i32] }:$src_mods, ?:{ *:[f16] }:$src)
        GIR_BuildMI, /*InsnID*/0, /*Opcode*/GIMT_Encode2(AMDGPU::V_MUL_F16_fake16_e64),
        GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/0, // DstI[vdst]
        GIR_AddImm8, /*InsnID*/0, /*Imm*/0,
        GIR_AddImm, /*InsnID*/0, /*Imm*/GIMT_Encode8(48128),
        GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/1, // src_mods
        GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/0, // src
        GIR_AddImm8, /*InsnID*/0, /*Imm*/0,
        GIR_AddImm8, /*InsnID*/0, /*Imm*/0,
        GIR_ConstrainSelectedInstOperands, /*InsnID*/0,
        GIR_EraseFromParent, /*InsnID*/0,
        // GIR_Coverage, 6403,
        GIR_Done,
      // Label 4288: @267340
      GIM_Try, /*On fail goto*//*Label 4289*/ GIMT_Encode4(267397), // Rule ID 6400 //
        GIM_CheckFeatures, GIMT_Encode2(GIFBS_NotHasTrue16BitInsts),
        GIM_CheckComplexPattern, /*MI*/0, /*Op*/1, /*Renderer*/GIMT_Encode2(0), GIMT_Encode2(GICP_gi_vop3mods),
        // (fcanonicalize:{ *:[f16] } (VOP3Mods:{ *:[f16] } f16:{ *:[f16] }:$src, i32:{ *:[i32] }:$src_mods))  =>  (V_MUL_F16_e64:{ *:[f16] } 0:{ *:[i32] }, 15360:{ *:[i32] }, ?:{ *:[i32] }:$src_mods, ?:{ *:[f16] }:$src)
        GIR_BuildMI, /*InsnID*/0, /*Opcode*/GIMT_Encode2(AMDGPU::V_MUL_F16_e64),
        GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/0, // DstI[vdst]
        GIR_AddImm8, /*InsnID*/0, /*Imm*/0,
        GIR_AddImm, /*InsnID*/0, /*Imm*/GIMT_Encode8(15360),
        GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/1, // src_mods
        GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/0, // src
        GIR_AddImm8, /*InsnID*/0, /*Imm*/0,
        GIR_AddImm8, /*InsnID*/0, /*Imm*/0,
        GIR_ConstrainSelectedInstOperands, /*InsnID*/0,
        GIR_EraseFromParent, /*InsnID*/0,
        // GIR_Coverage, 6400,
        GIR_Done,
      // Label 4289: @267397
      GIM_Try, /*On fail goto*//*Label 4290*/ GIMT_Encode4(267454), // Rule ID 6402 //
        GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasTrue16BitInsts),
        GIM_CheckComplexPattern, /*MI*/0, /*Op*/1, /*Renderer*/GIMT_Encode2(0), GIMT_Encode2(GICP_gi_vop3mods),
        // (fcanonicalize:{ *:[f16] } (VOP3Mods:{ *:[f16] } f16:{ *:[f16] }:$src, i32:{ *:[i32] }:$src_mods))  =>  (V_MUL_F16_fake16_e64:{ *:[f16] } 0:{ *:[i32] }, 15360:{ *:[i32] }, ?:{ *:[i32] }:$src_mods, ?:{ *:[f16] }:$src)
        GIR_BuildMI, /*InsnID*/0, /*Opcode*/GIMT_Encode2(AMDGPU::V_MUL_F16_fake16_e64),
        GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/0, // DstI[vdst]
        GIR_AddImm8, /*InsnID*/0, /*Imm*/0,
        GIR_AddImm, /*InsnID*/0, /*Imm*/GIMT_Encode8(15360),
        GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/1, // src_mods
        GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/0, // src
        GIR_AddImm8, /*InsnID*/0, /*Imm*/0,
        GIR_AddImm8, /*InsnID*/0, /*Imm*/0,
        GIR_ConstrainSelectedInstOperands, /*InsnID*/0,
        GIR_EraseFromParent, /*InsnID*/0,
        // GIR_Coverage, 6402,
        GIR_Done,
      // Label 4290: @267454
      GIM_Reject,
    // Label 4282: @267455
    GIM_Reject,
    // Label 4277: @267456
    GIM_Try, /*On fail goto*//*Label 4291*/ GIMT_Encode4(267701),
      GIM_CheckType, /*MI*/0, /*Op*/1, /*Type*/GILLT_s32,
      GIM_CheckRegBankForClass, /*MI*/0, /*Op*/0, /*RC*/GIMT_Encode2(AMDGPU::VGPR_32RegClassID),
      GIM_Try, /*On fail goto*//*Label 4292*/ GIMT_Encode4(267524), // Rule ID 6409 //
        GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasMinMaxDenormModes),
        GIM_CheckComplexPattern, /*MI*/0, /*Op*/1, /*Renderer*/GIMT_Encode2(0), GIMT_Encode2(GICP_gi_vop3mods),
        // (fcanonicalize:{ *:[f32] } (VOP3Mods:{ *:[f32] } f32:{ *:[f32] }:$src, i32:{ *:[i32] }:$src_mods))  =>  (V_MAX_F32_e64:{ *:[f32] } ?:{ *:[i32] }:$src_mods, ?:{ *:[f32] }:$src, ?:{ *:[i32] }:$src_mods, ?:{ *:[f32] }:$src)
        GIR_BuildMI, /*InsnID*/0, /*Opcode*/GIMT_Encode2(AMDGPU::V_MAX_F32_e64),
        GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/0, // DstI[vdst]
        GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/1, // src_mods
        GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/0, // src
        GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/1, // src_mods
        GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/0, // src
        GIR_AddImm8, /*InsnID*/0, /*Imm*/0,
        GIR_AddImm8, /*InsnID*/0, /*Imm*/0,
        GIR_ConstrainSelectedInstOperands, /*InsnID*/0,
        GIR_EraseFromParent, /*InsnID*/0,
        // GIR_Coverage, 6409,
        GIR_Done,
      // Label 4292: @267524
      GIM_Try, /*On fail goto*//*Label 4293*/ GIMT_Encode4(267578), // Rule ID 6415 //
        GIM_CheckFeatures, GIMT_Encode2(GIFBS_FalsePredicate_NotHasMinMaxDenormModes),
        GIM_CheckComplexPattern, /*MI*/0, /*Op*/1, /*Renderer*/GIMT_Encode2(0), GIMT_Encode2(GICP_gi_vop3mods),
        // (fcanonicalize:{ *:[f32] } (VOP3Mods:{ *:[f32] } f32:{ *:[f32] }:$src, i32:{ *:[i32] }:$src_mods))  =>  (V_MAX_F32_e64:{ *:[f32] } ?:{ *:[i32] }:$src_mods, ?:{ *:[f32] }:$src, ?:{ *:[i32] }:$src_mods, ?:{ *:[f32] }:$src)
        GIR_BuildMI, /*InsnID*/0, /*Opcode*/GIMT_Encode2(AMDGPU::V_MAX_F32_e64),
        GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/0, // DstI[vdst]
        GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/1, // src_mods
        GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/0, // src
        GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/1, // src_mods
        GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/0, // src
        GIR_AddImm8, /*InsnID*/0, /*Imm*/0,
        GIR_AddImm8, /*InsnID*/0, /*Imm*/0,
        GIR_ConstrainSelectedInstOperands, /*InsnID*/0,
        GIR_EraseFromParent, /*InsnID*/0,
        // GIR_Coverage, 6415,
        GIR_Done,
      // Label 4293: @267578
      GIM_Try, /*On fail goto*//*Label 4294*/ GIMT_Encode4(267646), // Rule ID 6406 //
        GIM_RecordInsn, /*DefineMI*/1, /*MI*/0, /*OpIdx*/1, // MIs[1]
        GIM_CheckOpcode, /*MI*/1, GIMT_Encode2(TargetOpcode::G_FNEG),
        GIM_CheckType, /*MI*/1, /*Op*/1, /*Type*/GILLT_s32,
        GIM_CheckIsSafeToFold, /*InsnID*/1,
        GIM_CheckComplexPattern, /*MI*/1, /*Op*/1, /*Renderer*/GIMT_Encode2(0), GIMT_Encode2(GICP_gi_vop3mods),
        // (fcanonicalize:{ *:[f32] } (fneg:{ *:[f32] } (VOP3Mods:{ *:[f32] } f32:{ *:[f32] }:$src, i32:{ *:[i32] }:$src_mods)))  =>  (V_MUL_F32_e64:{ *:[f32] } 0:{ *:[i32] }, 3212836864:{ *:[i32] }, ?:{ *:[i32] }:$src_mods, ?:{ *:[f32] }:$src)
        GIR_BuildMI, /*InsnID*/0, /*Opcode*/GIMT_Encode2(AMDGPU::V_MUL_F32_e64),
        GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/0, // DstI[vdst]
        GIR_AddImm8, /*InsnID*/0, /*Imm*/0,
        GIR_AddImm, /*InsnID*/0, /*Imm*/GIMT_Encode8(3212836864),
        GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/1, // src_mods
        GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/0, // src
        GIR_AddImm8, /*InsnID*/0, /*Imm*/0,
        GIR_AddImm8, /*InsnID*/0, /*Imm*/0,
        GIR_ConstrainSelectedInstOperands, /*InsnID*/0,
        GIR_EraseFromParent, /*InsnID*/0,
        // GIR_Coverage, 6406,
        GIR_Done,
      // Label 4294: @267646
      GIM_Try, /*On fail goto*//*Label 4295*/ GIMT_Encode4(267700), // Rule ID 6405 //
        GIM_CheckComplexPattern, /*MI*/0, /*Op*/1, /*Renderer*/GIMT_Encode2(0), GIMT_Encode2(GICP_gi_vop3mods),
        // (fcanonicalize:{ *:[f32] } (VOP3Mods:{ *:[f32] } f32:{ *:[f32] }:$src, i32:{ *:[i32] }:$src_mods))  =>  (V_MUL_F32_e64:{ *:[f32] } 0:{ *:[i32] }, 1065353216:{ *:[i32] }, ?:{ *:[i32] }:$src_mods, ?:{ *:[f32] }:$src)
        GIR_BuildMI, /*InsnID*/0, /*Opcode*/GIMT_Encode2(AMDGPU::V_MUL_F32_e64),
        GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/0, // DstI[vdst]
        GIR_AddImm8, /*InsnID*/0, /*Imm*/0,
        GIR_AddImm, /*InsnID*/0, /*Imm*/GIMT_Encode8(1065353216),
        GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/1, // src_mods
        GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/0, // src
        GIR_AddImm8, /*InsnID*/0, /*Imm*/0,
        GIR_AddImm8, /*InsnID*/0, /*Imm*/0,
        GIR_ConstrainSelectedInstOperands, /*InsnID*/0,
        GIR_EraseFromParent, /*InsnID*/0,
        // GIR_Coverage, 6405,
        GIR_Done,
      // Label 4295: @267700
      GIM_Reject,
    // Label 4291: @267701
    GIM_Reject,
    // Label 4278: @267702
    GIM_Try, /*On fail goto*//*Label 4296*/ GIMT_Encode4(267990),
      GIM_CheckType, /*MI*/0, /*Op*/1, /*Type*/GILLT_s64,
      GIM_CheckRegBankForClass, /*MI*/0, /*Op*/0, /*RC*/GIMT_Encode2(AMDGPU::VReg_64RegClassID),
      GIM_Try, /*On fail goto*//*Label 4297*/ GIMT_Encode4(267770), // Rule ID 6410 //
        GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasMinMaxDenormModes_isNotGFX12Plus),
        GIM_CheckComplexPattern, /*MI*/0, /*Op*/1, /*Renderer*/GIMT_Encode2(0), GIMT_Encode2(GICP_gi_vop3mods),
        // (fcanonicalize:{ *:[f64] } (VOP3Mods:{ *:[f64] } f64:{ *:[f64] }:$src, i32:{ *:[i32] }:$src_mods))  =>  (V_MAX_F64_e64:{ *:[f64] } ?:{ *:[i32] }:$src_mods, ?:{ *:[f64] }:$src, ?:{ *:[i32] }:$src_mods, ?:{ *:[f64] }:$src)
        GIR_BuildMI, /*InsnID*/0, /*Opcode*/GIMT_Encode2(AMDGPU::V_MAX_F64_e64),
        GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/0, // DstI[vdst]
        GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/1, // src_mods
        GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/0, // src
        GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/1, // src_mods
        GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/0, // src
        GIR_AddImm8, /*InsnID*/0, /*Imm*/0,
        GIR_AddImm8, /*InsnID*/0, /*Imm*/0,
        GIR_ConstrainSelectedInstOperands, /*InsnID*/0,
        GIR_EraseFromParent, /*InsnID*/0,
        // GIR_Coverage, 6410,
        GIR_Done,
      // Label 4297: @267770
      GIM_Try, /*On fail goto*//*Label 4298*/ GIMT_Encode4(267824), // Rule ID 6411 //
        GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasMinMaxDenormModes_isGFX12Plus),
        GIM_CheckComplexPattern, /*MI*/0, /*Op*/1, /*Renderer*/GIMT_Encode2(0), GIMT_Encode2(GICP_gi_vop3mods),
        // (fcanonicalize:{ *:[f64] } (VOP3Mods:{ *:[f64] } f64:{ *:[f64] }:$src, i32:{ *:[i32] }:$src_mods))  =>  (V_MAX_NUM_F64_e64:{ *:[f64] } ?:{ *:[i32] }:$src_mods, ?:{ *:[f64] }:$src, ?:{ *:[i32] }:$src_mods, ?:{ *:[f64] }:$src)
        GIR_BuildMI, /*InsnID*/0, /*Opcode*/GIMT_Encode2(AMDGPU::V_MAX_NUM_F64_e64),
        GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/0, // DstI[vdst]
        GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/1, // src_mods
        GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/0, // src
        GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/1, // src_mods
        GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/0, // src
        GIR_AddImm8, /*InsnID*/0, /*Imm*/0,
        GIR_AddImm8, /*InsnID*/0, /*Imm*/0,
        GIR_ConstrainSelectedInstOperands, /*InsnID*/0,
        GIR_EraseFromParent, /*InsnID*/0,
        // GIR_Coverage, 6411,
        GIR_Done,
      // Label 4298: @267824
      GIM_Try, /*On fail goto*//*Label 4299*/ GIMT_Encode4(267878), // Rule ID 6416 //
        GIM_CheckFeatures, GIMT_Encode2(GIFBS_FP64Denormals_NotHasMinMaxDenormModes_isNotGFX12Plus),
        GIM_CheckComplexPattern, /*MI*/0, /*Op*/1, /*Renderer*/GIMT_Encode2(0), GIMT_Encode2(GICP_gi_vop3mods),
        // (fcanonicalize:{ *:[f64] } (VOP3Mods:{ *:[f64] } f64:{ *:[f64] }:$src, i32:{ *:[i32] }:$src_mods))  =>  (V_MAX_F64_e64:{ *:[f64] } ?:{ *:[i32] }:$src_mods, ?:{ *:[f64] }:$src, ?:{ *:[i32] }:$src_mods, ?:{ *:[f64] }:$src)
        GIR_BuildMI, /*InsnID*/0, /*Opcode*/GIMT_Encode2(AMDGPU::V_MAX_F64_e64),
        GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/0, // DstI[vdst]
        GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/1, // src_mods
        GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/0, // src
        GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/1, // src_mods
        GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/0, // src
        GIR_AddImm8, /*InsnID*/0, /*Imm*/0,
        GIR_AddImm8, /*InsnID*/0, /*Imm*/0,
        GIR_ConstrainSelectedInstOperands, /*InsnID*/0,
        GIR_EraseFromParent, /*InsnID*/0,
        // GIR_Coverage, 6416,
        GIR_Done,
      // Label 4299: @267878
      GIM_Try, /*On fail goto*//*Label 4300*/ GIMT_Encode4(267932), // Rule ID 6417 //
        GIM_CheckFeatures, GIMT_Encode2(GIFBS_FP64Denormals_NotHasMinMaxDenormModes_isGFX12Plus),
        GIM_CheckComplexPattern, /*MI*/0, /*Op*/1, /*Renderer*/GIMT_Encode2(0), GIMT_Encode2(GICP_gi_vop3mods),
        // (fcanonicalize:{ *:[f64] } (VOP3Mods:{ *:[f64] } f64:{ *:[f64] }:$src, i32:{ *:[i32] }:$src_mods))  =>  (V_MAX_NUM_F64_e64:{ *:[f64] } ?:{ *:[i32] }:$src_mods, ?:{ *:[f64] }:$src, ?:{ *:[i32] }:$src_mods, ?:{ *:[f64] }:$src)
        GIR_BuildMI, /*InsnID*/0, /*Opcode*/GIMT_Encode2(AMDGPU::V_MAX_NUM_F64_e64),
        GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/0, // DstI[vdst]
        GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/1, // src_mods
        GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/0, // src
        GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/1, // src_mods
        GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/0, // src
        GIR_AddImm8, /*InsnID*/0, /*Imm*/0,
        GIR_AddImm8, /*InsnID*/0, /*Imm*/0,
        GIR_ConstrainSelectedInstOperands, /*InsnID*/0,
        GIR_EraseFromParent, /*InsnID*/0,
        // GIR_Coverage, 6417,
        GIR_Done,
      // Label 4300: @267932
      GIM_Try, /*On fail goto*//*Label 4301*/ GIMT_Encode4(267989), // Rule ID 6408 //
        GIM_CheckFeatures, GIMT_Encode2(GIFBS_isNotGFX12Plus),
        GIM_CheckComplexPattern, /*MI*/0, /*Op*/1, /*Renderer*/GIMT_Encode2(0), GIMT_Encode2(GICP_gi_vop3mods),
        // (fcanonicalize:{ *:[f64] } (VOP3Mods:{ *:[f64] } f64:{ *:[f64] }:$src, i32:{ *:[i32] }:$src_mods))  =>  (V_MUL_F64_e64:{ *:[f64] } 0:{ *:[i32] }, 4607182418800017408:{ *:[i64] }, ?:{ *:[i32] }:$src_mods, ?:{ *:[f64] }:$src)
        GIR_BuildMI, /*InsnID*/0, /*Opcode*/GIMT_Encode2(AMDGPU::V_MUL_F64_e64),
        GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/0, // DstI[vdst]
        GIR_AddImm8, /*InsnID*/0, /*Imm*/0,
        GIR_AddImm, /*InsnID*/0, /*Imm*/GIMT_Encode8(4607182418800017408),
        GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/1, // src_mods
        GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/0, // src
        GIR_AddImm8, /*InsnID*/0, /*Imm*/0,
        GIR_AddImm8, /*InsnID*/0, /*Imm*/0,
        GIR_ConstrainSelectedInstOperands, /*InsnID*/0,
        GIR_EraseFromParent, /*InsnID*/0,
        // GIR_Coverage, 6408,
        GIR_Done,
      // Label 4301: @267989
      GIM_Reject,
    // Label 4296: @267990
    GIM_Reject,
    // Label 4279: @267991
    GIM_Try, /*On fail goto*//*Label 4302*/ GIMT_Encode4(268195),
      GIM_CheckType, /*MI*/0, /*Op*/1, /*Type*/GILLT_v2s16,
      GIM_CheckRegBankForClass, /*MI*/0, /*Op*/0, /*RC*/GIMT_Encode2(AMDGPU::VGPR_32RegClassID),
      GIM_Try, /*On fail goto*//*Label 4303*/ GIMT_Encode4(268068), // Rule ID 6414 //
        GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasMinMaxDenormModes),
        GIM_CheckComplexPattern, /*MI*/0, /*Op*/1, /*Renderer*/GIMT_Encode2(0), GIMT_Encode2(GICP_gi_vop3pmods),
        // (fcanonicalize:{ *:[v2f16] } (VOP3PMods:{ *:[v2f16] } v2f16:{ *:[v2f16] }:$src, i32:{ *:[i32] }:$src_mods))  =>  (V_PK_MAX_F16:{ *:[v2f16] } ?:{ *:[i32] }:$src_mods, ?:{ *:[v2f16] }:$src, ?:{ *:[i32] }:$src_mods, ?:{ *:[v2f16] }:$src, 0:{ *:[i1] })
        GIR_BuildMI, /*InsnID*/0, /*Opcode*/GIMT_Encode2(AMDGPU::V_PK_MAX_F16),
        GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/0, // DstI[vdst]
        GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/1, // src_mods
        GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/0, // src
        GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/1, // src_mods
        GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/0, // src
        GIR_AddImm8, /*InsnID*/0, /*Imm*/0,
        GIR_AddImm8, /*InsnID*/0, /*Imm*/0,
        GIR_AddImm8, /*InsnID*/0, /*Imm*/0,
        GIR_AddImm8, /*InsnID*/0, /*Imm*/0,
        GIR_AddImm8, /*InsnID*/0, /*Imm*/0,
        GIR_ConstrainSelectedInstOperands, /*InsnID*/0,
        GIR_EraseFromParent, /*InsnID*/0,
        // GIR_Coverage, 6414,
        GIR_Done,
      // Label 4303: @268068
      GIM_Try, /*On fail goto*//*Label 4304*/ GIMT_Encode4(268131), // Rule ID 6420 //
        GIM_CheckFeatures, GIMT_Encode2(GIFBS_FP16Denormals_NotHasMinMaxDenormModes),
        GIM_CheckComplexPattern, /*MI*/0, /*Op*/1, /*Renderer*/GIMT_Encode2(0), GIMT_Encode2(GICP_gi_vop3pmods),
        // (fcanonicalize:{ *:[v2f16] } (VOP3PMods:{ *:[v2f16] } v2f16:{ *:[v2f16] }:$src, i32:{ *:[i32] }:$src_mods))  =>  (V_PK_MAX_F16:{ *:[v2f16] } ?:{ *:[i32] }:$src_mods, ?:{ *:[v2f16] }:$src, ?:{ *:[i32] }:$src_mods, ?:{ *:[v2f16] }:$src, 0:{ *:[i1] })
        GIR_BuildMI, /*InsnID*/0, /*Opcode*/GIMT_Encode2(AMDGPU::V_PK_MAX_F16),
        GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/0, // DstI[vdst]
        GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/1, // src_mods
        GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/0, // src
        GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/1, // src_mods
        GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/0, // src
        GIR_AddImm8, /*InsnID*/0, /*Imm*/0,
        GIR_AddImm8, /*InsnID*/0, /*Imm*/0,
        GIR_AddImm8, /*InsnID*/0, /*Imm*/0,
        GIR_AddImm8, /*InsnID*/0, /*Imm*/0,
        GIR_AddImm8, /*InsnID*/0, /*Imm*/0,
        GIR_ConstrainSelectedInstOperands, /*InsnID*/0,
        GIR_EraseFromParent, /*InsnID*/0,
        // GIR_Coverage, 6420,
        GIR_Done,
      // Label 4304: @268131
      GIM_Try, /*On fail goto*//*Label 4305*/ GIMT_Encode4(268194), // Rule ID 6404 //
        GIM_CheckComplexPattern, /*MI*/0, /*Op*/1, /*Renderer*/GIMT_Encode2(0), GIMT_Encode2(GICP_gi_vop3pmods),
        // (fcanonicalize:{ *:[v2f16] } (VOP3PMods:{ *:[v2f16] } v2f16:{ *:[v2f16] }:$src, i32:{ *:[i32] }:$src_mods))  =>  (V_PK_MUL_F16:{ *:[v2f16] } 0:{ *:[i32] }, 15360:{ *:[i32] }, ?:{ *:[i32] }:$src_mods, ?:{ *:[v2f16] }:$src, 0:{ *:[i1] })
        GIR_BuildMI, /*InsnID*/0, /*Opcode*/GIMT_Encode2(AMDGPU::V_PK_MUL_F16),
        GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/0, // DstI[vdst]
        GIR_AddImm8, /*InsnID*/0, /*Imm*/0,
        GIR_AddImm, /*InsnID*/0, /*Imm*/GIMT_Encode8(15360),
        GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/1, // src_mods
        GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/0, // src
        GIR_AddImm8, /*InsnID*/0, /*Imm*/0,
        GIR_AddImm8, /*InsnID*/0, /*Imm*/0,
        GIR_AddImm8, /*InsnID*/0, /*Imm*/0,
        GIR_AddImm8, /*InsnID*/0, /*Imm*/0,
        GIR_AddImm8, /*InsnID*/0, /*Imm*/0,
        GIR_ConstrainSelectedInstOperands, /*InsnID*/0,
        GIR_EraseFromParent, /*InsnID*/0,
        // GIR_Coverage, 6404,
        GIR_Done,
      // Label 4305: @268194
      GIM_Reject,
    // Label 4302: @268195
    GIM_Reject,
    // Label 4280: @268196
    GIM_Try, /*On fail goto*//*Label 4306*/ GIMT_Encode4(268271), // Rule ID 6407 //
      GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasPackedFP32Ops),
      GIM_CheckType, /*MI*/0, /*Op*/1, /*Type*/GILLT_v2s32,
      GIM_CheckRegBankForClass, /*MI*/0, /*Op*/0, /*RC*/GIMT_Encode2(AMDGPU::VReg_64RegClassID),
      GIM_CheckComplexPattern, /*MI*/0, /*Op*/1, /*Renderer*/GIMT_Encode2(0), GIMT_Encode2(GICP_gi_vop3pmods),
      // (fcanonicalize:{ *:[v2f32] } (VOP3PMods:{ *:[v2f32] } v2f32:{ *:[v2f32] }:$src, i32:{ *:[i32] }:$src_mods))  =>  (V_PK_MUL_F32:{ *:[v2f32] } 0:{ *:[i32] }, 1065353216:{ *:[i64] }, ?:{ *:[i32] }:$src_mods, ?:{ *:[v2f32] }:$src)
      GIR_BuildMI, /*InsnID*/0, /*Opcode*/GIMT_Encode2(AMDGPU::V_PK_MUL_F32),
      GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/0, // DstI[vdst]
      GIR_AddImm8, /*InsnID*/0, /*Imm*/0,
      GIR_AddImm, /*InsnID*/0, /*Imm*/GIMT_Encode8(1065353216),
      GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/1, // src_mods
      GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/0, // src
      GIR_AddImm8, /*InsnID*/0, /*Imm*/0,
      GIR_AddImm8, /*InsnID*/0, /*Imm*/0,
      GIR_AddImm8, /*InsnID*/0, /*Imm*/0,
      GIR_AddImm8, /*InsnID*/0, /*Imm*/0,
      GIR_AddImm8, /*InsnID*/0, /*Imm*/0,
      GIR_ConstrainSelectedInstOperands, /*InsnID*/0,
      GIR_EraseFromParent, /*InsnID*/0,
      // GIR_Coverage, 6407,
      GIR_Done,
    // Label 4306: @268271
    GIM_Reject,
    // Label 4281: @268272
    GIM_Reject,
    // Label 76: @268273
    GIM_SwitchType, /*MI*/0, /*Op*/0, /*[*/GIMT_Encode2(8), GIMT_Encode2(12), /*)*//*default:*//*Label 4311*/ GIMT_Encode4(288083),
    /*GILLT_s16*//*Label 4307*/ GIMT_Encode4(268300),
    /*GILLT_s32*//*Label 4308*/ GIMT_Encode4(269194),
    /*GILLT_s64*//*Label 4309*/ GIMT_Encode4(287722),
    /*GILLT_v2s16*//*Label 4310*/ GIMT_Encode4(288002),
    // Label 4307: @268300
    GIM_Try, /*On fail goto*//*Label 4312*/ GIMT_Encode4(269193),
      GIM_CheckType, /*MI*/0, /*Op*/1, /*Type*/GILLT_s16,
      GIM_CheckType, /*MI*/0, /*Op*/2, /*Type*/GILLT_s16,
      GIM_Try, /*On fail goto*//*Label 4313*/ GIMT_Encode4(268418), // Rule ID 10529 //
        GIM_CheckFeatures, GIMT_Encode2(GIFBS_isGFX11Plus),
        GIM_CheckRegBankForClass, /*MI*/0, /*Op*/0, /*RC*/GIMT_Encode2(AMDGPU::VGPR_32RegClassID),
        GIM_RecordInsn, /*DefineMI*/1, /*MI*/0, /*OpIdx*/2, // MIs[1]
        GIM_CheckOpcode, /*MI*/1, GIMT_Encode2(TargetOpcode::G_FMAXNUM),
        GIM_CheckType, /*MI*/1, /*Op*/1, /*Type*/GILLT_s16,
        GIM_CheckType, /*MI*/1, /*Op*/2, /*Type*/GILLT_s16,
        GIM_CheckCxxInsnPredicate, /*MI*/1, /*FnId*/GIMT_Encode2(GICXXPred_MI_Predicate_fmaxnum_oneuse),
        GIM_CheckIsSafeToFold, /*InsnID*/1,
        GIM_CheckComplexPattern, /*MI*/0, /*Op*/1, /*Renderer*/GIMT_Encode2(0), GIMT_Encode2(GICP_gi_vop3mods),
        GIM_CheckComplexPattern, /*MI*/1, /*Op*/1, /*Renderer*/GIMT_Encode2(1), GIMT_Encode2(GICP_gi_vop3mods),
        GIM_CheckComplexPattern, /*MI*/1, /*Op*/2, /*Renderer*/GIMT_Encode2(2), GIMT_Encode2(GICP_gi_vop3mods),
        // (fminnum:{ *:[f16] } (VOP3Mods:{ *:[f16] } f16:{ *:[f16] }:$src2, i32:{ *:[i32] }:$src2_mods), (fmaxnum:{ *:[f16] } (VOP3Mods:{ *:[f16] } f16:{ *:[f16] }:$src0, i32:{ *:[i32] }:$src0_mods), (VOP3Mods:{ *:[f16] } f16:{ *:[f16] }:$src1, i32:{ *:[i32] }:$src1_mods))<<P:Predicate_fmaxnum_oneuse>>)  =>  (V_MAXMIN_F16_e64:{ *:[f16] } ?:{ *:[i32] }:$src0_mods, ?:{ *:[f16] }:$src0, ?:{ *:[i32] }:$src1_mods, ?:{ *:[f16] }:$src1, ?:{ *:[i32] }:$src2_mods, ?:{ *:[f16] }:$src2, 0:{ *:[i1] }, 0:{ *:[i32] })
        GIR_BuildMI, /*InsnID*/0, /*Opcode*/GIMT_Encode2(AMDGPU::V_MAXMIN_F16_e64),
        GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/0, // DstI[vdst]
        GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(1), /*SubOperand*/1, // src0_mods
        GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(1), /*SubOperand*/0, // src0
        GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(2), /*SubOperand*/1, // src1_mods
        GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(2), /*SubOperand*/0, // src1
        GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/1, // src2_mods
        GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/0, // src2
        GIR_AddImm8, /*InsnID*/0, /*Imm*/0,
        GIR_AddImm8, /*InsnID*/0, /*Imm*/0,
        GIR_ConstrainSelectedInstOperands, /*InsnID*/0,
        GIR_EraseFromParent, /*InsnID*/0,
        // GIR_Coverage, 10529,
        GIR_Done,
      // Label 4313: @268418
      GIM_Try, /*On fail goto*//*Label 4314*/ GIMT_Encode4(268523), // Rule ID 10528 //
        GIM_CheckFeatures, GIMT_Encode2(GIFBS_isGFX11Plus),
        GIM_CheckRegBankForClass, /*MI*/0, /*Op*/0, /*RC*/GIMT_Encode2(AMDGPU::VGPR_32RegClassID),
        GIM_RecordInsn, /*DefineMI*/1, /*MI*/0, /*OpIdx*/2, // MIs[1]
        GIM_CheckOpcode, /*MI*/1, GIMT_Encode2(TargetOpcode::G_FMAXNUM_IEEE),
        GIM_CheckType, /*MI*/1, /*Op*/1, /*Type*/GILLT_s16,
        GIM_CheckType, /*MI*/1, /*Op*/2, /*Type*/GILLT_s16,
        GIM_CheckCxxInsnPredicate, /*MI*/1, /*FnId*/GIMT_Encode2(GICXXPred_MI_Predicate_fmaxnum_ieee_oneuse),
        GIM_CheckIsSafeToFold, /*InsnID*/1,
        GIM_CheckComplexPattern, /*MI*/0, /*Op*/1, /*Renderer*/GIMT_Encode2(0), GIMT_Encode2(GICP_gi_vop3mods),
        GIM_CheckComplexPattern, /*MI*/1, /*Op*/1, /*Renderer*/GIMT_Encode2(1), GIMT_Encode2(GICP_gi_vop3mods),
        GIM_CheckComplexPattern, /*MI*/1, /*Op*/2, /*Renderer*/GIMT_Encode2(2), GIMT_Encode2(GICP_gi_vop3mods),
        // (fminnum:{ *:[f16] } (VOP3Mods:{ *:[f16] } f16:{ *:[f16] }:$src2, i32:{ *:[i32] }:$src2_mods), (fmaxnum_ieee:{ *:[f16] } (VOP3Mods:{ *:[f16] } f16:{ *:[f16] }:$src0, i32:{ *:[i32] }:$src0_mods), (VOP3Mods:{ *:[f16] } f16:{ *:[f16] }:$src1, i32:{ *:[i32] }:$src1_mods))<<P:Predicate_fmaxnum_ieee_oneuse>>)  =>  (V_MAXMIN_F16_e64:{ *:[f16] } ?:{ *:[i32] }:$src0_mods, ?:{ *:[f16] }:$src0, ?:{ *:[i32] }:$src1_mods, ?:{ *:[f16] }:$src1, ?:{ *:[i32] }:$src2_mods, ?:{ *:[f16] }:$src2, 0:{ *:[i1] }, 0:{ *:[i32] })
        GIR_BuildMI, /*InsnID*/0, /*Opcode*/GIMT_Encode2(AMDGPU::V_MAXMIN_F16_e64),
        GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/0, // DstI[vdst]
        GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(1), /*SubOperand*/1, // src0_mods
        GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(1), /*SubOperand*/0, // src0
        GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(2), /*SubOperand*/1, // src1_mods
        GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(2), /*SubOperand*/0, // src1
        GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/1, // src2_mods
        GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/0, // src2
        GIR_AddImm8, /*InsnID*/0, /*Imm*/0,
        GIR_AddImm8, /*InsnID*/0, /*Imm*/0,
        GIR_ConstrainSelectedInstOperands, /*InsnID*/0,
        GIR_EraseFromParent, /*InsnID*/0,
        // GIR_Coverage, 10528,
        GIR_Done,
      // Label 4314: @268523
      GIM_Try, /*On fail goto*//*Label 4315*/ GIMT_Encode4(268628), // Rule ID 6535 //
        GIM_CheckFeatures, GIMT_Encode2(GIFBS_isGFX11Plus),
        GIM_CheckRegBankForClass, /*MI*/0, /*Op*/0, /*RC*/GIMT_Encode2(AMDGPU::VGPR_32RegClassID),
        GIM_RecordInsn, /*DefineMI*/1, /*MI*/0, /*OpIdx*/1, // MIs[1]
        GIM_CheckOpcode, /*MI*/1, GIMT_Encode2(TargetOpcode::G_FMAXNUM),
        GIM_CheckType, /*MI*/1, /*Op*/1, /*Type*/GILLT_s16,
        GIM_CheckType, /*MI*/1, /*Op*/2, /*Type*/GILLT_s16,
        GIM_CheckCxxInsnPredicate, /*MI*/1, /*FnId*/GIMT_Encode2(GICXXPred_MI_Predicate_fmaxnum_oneuse),
        GIM_CheckIsSafeToFold, /*InsnID*/1,
        GIM_CheckComplexPattern, /*MI*/0, /*Op*/2, /*Renderer*/GIMT_Encode2(2), GIMT_Encode2(GICP_gi_vop3mods),
        GIM_CheckComplexPattern, /*MI*/1, /*Op*/1, /*Renderer*/GIMT_Encode2(0), GIMT_Encode2(GICP_gi_vop3mods),
        GIM_CheckComplexPattern, /*MI*/1, /*Op*/2, /*Renderer*/GIMT_Encode2(1), GIMT_Encode2(GICP_gi_vop3mods),
        // (fminnum:{ *:[f16] } (fmaxnum:{ *:[f16] } (VOP3Mods:{ *:[f16] } f16:{ *:[f16] }:$src0, i32:{ *:[i32] }:$src0_mods), (VOP3Mods:{ *:[f16] } f16:{ *:[f16] }:$src1, i32:{ *:[i32] }:$src1_mods))<<P:Predicate_fmaxnum_oneuse>>, (VOP3Mods:{ *:[f16] } f16:{ *:[f16] }:$src2, i32:{ *:[i32] }:$src2_mods))  =>  (V_MAXMIN_F16_e64:{ *:[f16] } ?:{ *:[i32] }:$src0_mods, ?:{ *:[f16] }:$src0, ?:{ *:[i32] }:$src1_mods, ?:{ *:[f16] }:$src1, ?:{ *:[i32] }:$src2_mods, ?:{ *:[f16] }:$src2, 0:{ *:[i1] }, 0:{ *:[i32] })
        GIR_BuildMI, /*InsnID*/0, /*Opcode*/GIMT_Encode2(AMDGPU::V_MAXMIN_F16_e64),
        GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/0, // DstI[vdst]
        GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/1, // src0_mods
        GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/0, // src0
        GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(1), /*SubOperand*/1, // src1_mods
        GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(1), /*SubOperand*/0, // src1
        GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(2), /*SubOperand*/1, // src2_mods
        GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(2), /*SubOperand*/0, // src2
        GIR_AddImm8, /*InsnID*/0, /*Imm*/0,
        GIR_AddImm8, /*InsnID*/0, /*Imm*/0,
        GIR_ConstrainSelectedInstOperands, /*InsnID*/0,
        GIR_EraseFromParent, /*InsnID*/0,
        // GIR_Coverage, 6535,
        GIR_Done,
      // Label 4315: @268628
      GIM_Try, /*On fail goto*//*Label 4316*/ GIMT_Encode4(268733), // Rule ID 6534 //
        GIM_CheckFeatures, GIMT_Encode2(GIFBS_isGFX11Plus),
        GIM_CheckRegBankForClass, /*MI*/0, /*Op*/0, /*RC*/GIMT_Encode2(AMDGPU::VGPR_32RegClassID),
        GIM_RecordInsn, /*DefineMI*/1, /*MI*/0, /*OpIdx*/1, // MIs[1]
        GIM_CheckOpcode, /*MI*/1, GIMT_Encode2(TargetOpcode::G_FMAXNUM_IEEE),
        GIM_CheckType, /*MI*/1, /*Op*/1, /*Type*/GILLT_s16,
        GIM_CheckType, /*MI*/1, /*Op*/2, /*Type*/GILLT_s16,
        GIM_CheckCxxInsnPredicate, /*MI*/1, /*FnId*/GIMT_Encode2(GICXXPred_MI_Predicate_fmaxnum_ieee_oneuse),
        GIM_CheckIsSafeToFold, /*InsnID*/1,
        GIM_CheckComplexPattern, /*MI*/0, /*Op*/2, /*Renderer*/GIMT_Encode2(2), GIMT_Encode2(GICP_gi_vop3mods),
        GIM_CheckComplexPattern, /*MI*/1, /*Op*/1, /*Renderer*/GIMT_Encode2(0), GIMT_Encode2(GICP_gi_vop3mods),
        GIM_CheckComplexPattern, /*MI*/1, /*Op*/2, /*Renderer*/GIMT_Encode2(1), GIMT_Encode2(GICP_gi_vop3mods),
        // (fminnum:{ *:[f16] } (fmaxnum_ieee:{ *:[f16] } (VOP3Mods:{ *:[f16] } f16:{ *:[f16] }:$src0, i32:{ *:[i32] }:$src0_mods), (VOP3Mods:{ *:[f16] } f16:{ *:[f16] }:$src1, i32:{ *:[i32] }:$src1_mods))<<P:Predicate_fmaxnum_ieee_oneuse>>, (VOP3Mods:{ *:[f16] } f16:{ *:[f16] }:$src2, i32:{ *:[i32] }:$src2_mods))  =>  (V_MAXMIN_F16_e64:{ *:[f16] } ?:{ *:[i32] }:$src0_mods, ?:{ *:[f16] }:$src0, ?:{ *:[i32] }:$src1_mods, ?:{ *:[f16] }:$src1, ?:{ *:[i32] }:$src2_mods, ?:{ *:[f16] }:$src2, 0:{ *:[i1] }, 0:{ *:[i32] })
        GIR_BuildMI, /*InsnID*/0, /*Opcode*/GIMT_Encode2(AMDGPU::V_MAXMIN_F16_e64),
        GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/0, // DstI[vdst]
        GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/1, // src0_mods
        GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/0, // src0
        GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(1), /*SubOperand*/1, // src1_mods
        GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(1), /*SubOperand*/0, // src1
        GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(2), /*SubOperand*/1, // src2_mods
        GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(2), /*SubOperand*/0, // src2
        GIR_AddImm8, /*InsnID*/0, /*Imm*/0,
        GIR_AddImm8, /*InsnID*/0, /*Imm*/0,
        GIR_ConstrainSelectedInstOperands, /*InsnID*/0,
        GIR_EraseFromParent, /*InsnID*/0,
        // GIR_Coverage, 6534,
        GIR_Done,
      // Label 4316: @268733
      GIM_Try, /*On fail goto*//*Label 4317*/ GIMT_Encode4(268772), // Rule ID 103 //
        GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasSALUFloatInsts),
        GIM_CheckRegBankForClass, /*MI*/0, /*Op*/0, /*RC*/GIMT_Encode2(AMDGPU::SReg_32RegClassID),
        GIM_CheckRegBankForClass, /*MI*/0, /*Op*/1, /*RC*/GIMT_Encode2(AMDGPU::SReg_32RegClassID),
        GIM_CheckRegBankForClass, /*MI*/0, /*Op*/2, /*RC*/GIMT_Encode2(AMDGPU::SReg_32RegClassID),
        GIM_CheckCxxInsnPredicate, /*MI*/0, /*FnId*/GIMT_Encode2(GICXXPred_MI_Predicate_anonymous_17631),
        // (fminnum:{ *:[f16] } SSrc_f16:{ *:[f16] }:$src0, SSrc_f16:{ *:[f16] }:$src1)<<P:Predicate_anonymous_17631>>  =>  (S_MIN_F16:{ *:[f16] } SSrc_f16:{ *:[f16] }:$src0, SSrc_f16:{ *:[f16] }:$src1)
        GIR_MutateOpcode, /*InsnID*/0, /*RecycleInsnID*/0, /*Opcode*/GIMT_Encode2(AMDGPU::S_MIN_F16),
        GIR_AddImplicitUse, /*InsnID*/0, GIMT_Encode2(AMDGPU::MODE),
        GIR_ConstrainSelectedInstOperands, /*InsnID*/0,
        // GIR_Coverage, 103,
        GIR_Done,
      // Label 4317: @268772
      GIM_Try, /*On fail goto*//*Label 4318*/ GIMT_Encode4(268842), // Rule ID 820 //
        GIM_CheckFeatures, GIMT_Encode2(GIFBS_Has16BitInsts_NotHasTrue16BitInsts),
        GIM_CheckRegBankForClass, /*MI*/0, /*Op*/0, /*RC*/GIMT_Encode2(AMDGPU::VGPR_32RegClassID),
        GIM_CheckComplexPattern, /*MI*/0, /*Op*/1, /*Renderer*/GIMT_Encode2(0), GIMT_Encode2(GICP_gi_vop3mods0),
        GIM_CheckComplexPattern, /*MI*/0, /*Op*/2, /*Renderer*/GIMT_Encode2(1), GIMT_Encode2(GICP_gi_vop3mods),
        // (fminnum:{ *:[f16] } (VOP3Mods0:{ *:[f16] } f16:{ *:[f16] }:$src0, i32:{ *:[i32] }:$src0_modifiers, i1:{ *:[i1] }:$clamp, i32:{ *:[i32] }:$omod), (VOP3Mods:{ *:[f16] } f16:{ *:[f16] }:$src1, i32:{ *:[i32] }:$src1_modifiers))  =>  (V_MIN_F16_e64:{ *:[f16] } i32:{ *:[i32] }:$src0_modifiers, f16:{ *:[f16] }:$src0, i32:{ *:[i32] }:$src1_modifiers, f16:{ *:[f16] }:$src1, i1:{ *:[i1] }:$clamp, i32:{ *:[i32] }:$omod)
        GIR_BuildMI, /*InsnID*/0, /*Opcode*/GIMT_Encode2(AMDGPU::V_MIN_F16_e64),
        GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/0, // DstI[vdst]
        GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/1, // src0_modifiers
        GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/0, // src0
        GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(1), /*SubOperand*/1, // src1_modifiers
        GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(1), /*SubOperand*/0, // src1
        GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/2, // clamp
        GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/3, // omod
        GIR_ConstrainSelectedInstOperands, /*InsnID*/0,
        GIR_EraseFromParent, /*InsnID*/0,
        // GIR_Coverage, 820,
        GIR_Done,
      // Label 4318: @268842
      GIM_Try, /*On fail goto*//*Label 4319*/ GIMT_Encode4(268912), // Rule ID 822 //
        GIM_CheckFeatures, GIMT_Encode2(GIFBS_UseRealTrue16Insts),
        GIM_CheckRegBankForClass, /*MI*/0, /*Op*/0, /*RC*/GIMT_Encode2(AMDGPU::VGPR_16RegClassID),
        GIM_CheckComplexPattern, /*MI*/0, /*Op*/1, /*Renderer*/GIMT_Encode2(0), GIMT_Encode2(GICP_gi_vop3mods0),
        GIM_CheckComplexPattern, /*MI*/0, /*Op*/2, /*Renderer*/GIMT_Encode2(1), GIMT_Encode2(GICP_gi_vop3mods),
        // (fminnum:{ *:[f16] } (VOP3Mods0:{ *:[f16] } f16:{ *:[f16] }:$src0, i32:{ *:[i32] }:$src0_modifiers, i1:{ *:[i1] }:$clamp, i32:{ *:[i32] }:$omod), (VOP3Mods:{ *:[f16] } f16:{ *:[f16] }:$src1, i32:{ *:[i32] }:$src1_modifiers))  =>  (V_MIN_F16_t16_e64:{ *:[f16] } i32:{ *:[i32] }:$src0_modifiers, f16:{ *:[f16] }:$src0, i32:{ *:[i32] }:$src1_modifiers, f16:{ *:[f16] }:$src1, i1:{ *:[i1] }:$clamp, i32:{ *:[i32] }:$omod)
        GIR_BuildMI, /*InsnID*/0, /*Opcode*/GIMT_Encode2(AMDGPU::V_MIN_F16_t16_e64),
        GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/0, // DstI[vdst]
        GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/1, // src0_modifiers
        GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/0, // src0
        GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(1), /*SubOperand*/1, // src1_modifiers
        GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(1), /*SubOperand*/0, // src1
        GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/2, // clamp
        GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/3, // omod
        GIR_ConstrainSelectedInstOperands, /*InsnID*/0,
        GIR_EraseFromParent, /*InsnID*/0,
        // GIR_Coverage, 822,
        GIR_Done,
      // Label 4319: @268912
      GIM_Try, /*On fail goto*//*Label 4320*/ GIMT_Encode4(268982), // Rule ID 824 //
        GIM_CheckFeatures, GIMT_Encode2(GIFBS_UseFakeTrue16Insts),
        GIM_CheckRegBankForClass, /*MI*/0, /*Op*/0, /*RC*/GIMT_Encode2(AMDGPU::VGPR_32RegClassID),
        GIM_CheckComplexPattern, /*MI*/0, /*Op*/1, /*Renderer*/GIMT_Encode2(0), GIMT_Encode2(GICP_gi_vop3mods0),
        GIM_CheckComplexPattern, /*MI*/0, /*Op*/2, /*Renderer*/GIMT_Encode2(1), GIMT_Encode2(GICP_gi_vop3mods),
        // (fminnum:{ *:[f16] } (VOP3Mods0:{ *:[f16] } f16:{ *:[f16] }:$src0, i32:{ *:[i32] }:$src0_modifiers, i1:{ *:[i1] }:$clamp, i32:{ *:[i32] }:$omod), (VOP3Mods:{ *:[f16] } f16:{ *:[f16] }:$src1, i32:{ *:[i32] }:$src1_modifiers))  =>  (V_MIN_F16_fake16_e64:{ *:[f16] } i32:{ *:[i32] }:$src0_modifiers, f16:{ *:[f16] }:$src0, i32:{ *:[i32] }:$src1_modifiers, f16:{ *:[f16] }:$src1, i1:{ *:[i1] }:$clamp, i32:{ *:[i32] }:$omod)
        GIR_BuildMI, /*InsnID*/0, /*Opcode*/GIMT_Encode2(AMDGPU::V_MIN_F16_fake16_e64),
        GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/0, // DstI[vdst]
        GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/1, // src0_modifiers
        GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/0, // src0
        GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(1), /*SubOperand*/1, // src1_modifiers
        GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(1), /*SubOperand*/0, // src1
        GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/2, // clamp
        GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/3, // omod
        GIR_ConstrainSelectedInstOperands, /*InsnID*/0,
        GIR_EraseFromParent, /*InsnID*/0,
        // GIR_Coverage, 824,
        GIR_Done,
      // Label 4320: @268982
      GIM_Try, /*On fail goto*//*Label 4321*/ GIMT_Encode4(269052), // Rule ID 7155 //
        GIM_CheckFeatures, GIMT_Encode2(GIFBS_Has16BitInsts_NotHasTrue16BitInsts),
        GIM_CheckRegBankForClass, /*MI*/0, /*Op*/0, /*RC*/GIMT_Encode2(AMDGPU::VGPR_32RegClassID),
        GIM_CheckComplexPattern, /*MI*/0, /*Op*/1, /*Renderer*/GIMT_Encode2(0), GIMT_Encode2(GICP_gi_vop3mods),
        GIM_CheckComplexPattern, /*MI*/0, /*Op*/2, /*Renderer*/GIMT_Encode2(1), GIMT_Encode2(GICP_gi_vop3mods0),
        // (fminnum:{ *:[f16] } (VOP3Mods:{ *:[f16] } f16:{ *:[f16] }:$src1, i32:{ *:[i32] }:$src1_modifiers), (VOP3Mods0:{ *:[f16] } f16:{ *:[f16] }:$src0, i32:{ *:[i32] }:$src0_modifiers, i1:{ *:[i1] }:$clamp, i32:{ *:[i32] }:$omod))  =>  (V_MIN_F16_e64:{ *:[f16] } i32:{ *:[i32] }:$src0_modifiers, f16:{ *:[f16] }:$src0, i32:{ *:[i32] }:$src1_modifiers, f16:{ *:[f16] }:$src1, i1:{ *:[i1] }:$clamp, i32:{ *:[i32] }:$omod)
        GIR_BuildMI, /*InsnID*/0, /*Opcode*/GIMT_Encode2(AMDGPU::V_MIN_F16_e64),
        GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/0, // DstI[vdst]
        GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(1), /*SubOperand*/1, // src0_modifiers
        GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(1), /*SubOperand*/0, // src0
        GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/1, // src1_modifiers
        GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/0, // src1
        GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(1), /*SubOperand*/2, // clamp
        GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(1), /*SubOperand*/3, // omod
        GIR_ConstrainSelectedInstOperands, /*InsnID*/0,
        GIR_EraseFromParent, /*InsnID*/0,
        // GIR_Coverage, 7155,
        GIR_Done,
      // Label 4321: @269052
      GIM_Try, /*On fail goto*//*Label 4322*/ GIMT_Encode4(269122), // Rule ID 7157 //
        GIM_CheckFeatures, GIMT_Encode2(GIFBS_UseRealTrue16Insts),
        GIM_CheckRegBankForClass, /*MI*/0, /*Op*/0, /*RC*/GIMT_Encode2(AMDGPU::VGPR_16RegClassID),
        GIM_CheckComplexPattern, /*MI*/0, /*Op*/1, /*Renderer*/GIMT_Encode2(0), GIMT_Encode2(GICP_gi_vop3mods),
        GIM_CheckComplexPattern, /*MI*/0, /*Op*/2, /*Renderer*/GIMT_Encode2(1), GIMT_Encode2(GICP_gi_vop3mods0),
        // (fminnum:{ *:[f16] } (VOP3Mods:{ *:[f16] } f16:{ *:[f16] }:$src1, i32:{ *:[i32] }:$src1_modifiers), (VOP3Mods0:{ *:[f16] } f16:{ *:[f16] }:$src0, i32:{ *:[i32] }:$src0_modifiers, i1:{ *:[i1] }:$clamp, i32:{ *:[i32] }:$omod))  =>  (V_MIN_F16_t16_e64:{ *:[f16] } i32:{ *:[i32] }:$src0_modifiers, f16:{ *:[f16] }:$src0, i32:{ *:[i32] }:$src1_modifiers, f16:{ *:[f16] }:$src1, i1:{ *:[i1] }:$clamp, i32:{ *:[i32] }:$omod)
        GIR_BuildMI, /*InsnID*/0, /*Opcode*/GIMT_Encode2(AMDGPU::V_MIN_F16_t16_e64),
        GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/0, // DstI[vdst]
        GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(1), /*SubOperand*/1, // src0_modifiers
        GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(1), /*SubOperand*/0, // src0
        GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/1, // src1_modifiers
        GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/0, // src1
        GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(1), /*SubOperand*/2, // clamp
        GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(1), /*SubOperand*/3, // omod
        GIR_ConstrainSelectedInstOperands, /*InsnID*/0,
        GIR_EraseFromParent, /*InsnID*/0,
        // GIR_Coverage, 7157,
        GIR_Done,
      // Label 4322: @269122
      GIM_Try, /*On fail goto*//*Label 4323*/ GIMT_Encode4(269192), // Rule ID 7159 //
        GIM_CheckFeatures, GIMT_Encode2(GIFBS_UseFakeTrue16Insts),
        GIM_CheckRegBankForClass, /*MI*/0, /*Op*/0, /*RC*/GIMT_Encode2(AMDGPU::VGPR_32RegClassID),
        GIM_CheckComplexPattern, /*MI*/0, /*Op*/1, /*Renderer*/GIMT_Encode2(0), GIMT_Encode2(GICP_gi_vop3mods),
        GIM_CheckComplexPattern, /*MI*/0, /*Op*/2, /*Renderer*/GIMT_Encode2(1), GIMT_Encode2(GICP_gi_vop3mods0),
        // (fminnum:{ *:[f16] } (VOP3Mods:{ *:[f16] } f16:{ *:[f16] }:$src1, i32:{ *:[i32] }:$src1_modifiers), (VOP3Mods0:{ *:[f16] } f16:{ *:[f16] }:$src0, i32:{ *:[i32] }:$src0_modifiers, i1:{ *:[i1] }:$clamp, i32:{ *:[i32] }:$omod))  =>  (V_MIN_F16_fake16_e64:{ *:[f16] } i32:{ *:[i32] }:$src0_modifiers, f16:{ *:[f16] }:$src0, i32:{ *:[i32] }:$src1_modifiers, f16:{ *:[f16] }:$src1, i1:{ *:[i1] }:$clamp, i32:{ *:[i32] }:$omod)
        GIR_BuildMI, /*InsnID*/0, /*Opcode*/GIMT_Encode2(AMDGPU::V_MIN_F16_fake16_e64),
        GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/0, // DstI[vdst]
        GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(1), /*SubOperand*/1, // src0_modifiers
        GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(1), /*SubOperand*/0, // src0
        GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/1, // src1_modifiers
        GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/0, // src1
        GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(1), /*SubOperand*/2, // clamp
        GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(1), /*SubOperand*/3, // omod
        GIR_ConstrainSelectedInstOperands, /*InsnID*/0,
        GIR_EraseFromParent, /*InsnID*/0,
        // GIR_Coverage, 7159,
        GIR_Done,
      // Label 4323: @269192
      GIM_Reject,
    // Label 4312: @269193
    GIM_Reject,
    // Label 4308: @269194
    GIM_Try, /*On fail goto*//*Label 4324*/ GIMT_Encode4(287721),
      GIM_CheckType, /*MI*/0, /*Op*/1, /*Type*/GILLT_s32,
      GIM_CheckType, /*MI*/0, /*Op*/2, /*Type*/GILLT_s32,
      GIM_Try, /*On fail goto*//*Label 4325*/ GIMT_Encode4(269347), // Rule ID 10466 //
        GIM_CheckRegBankForClass, /*MI*/0, /*Op*/0, /*RC*/GIMT_Encode2(AMDGPU::VGPR_32RegClassID),
        GIM_RecordInsn, /*DefineMI*/1, /*MI*/0, /*OpIdx*/1, // MIs[1]
        GIM_CheckOpcode, /*MI*/1, GIMT_Encode2(TargetOpcode::G_FMAXNUM),
        GIM_CheckType, /*MI*/1, /*Op*/1, /*Type*/GILLT_s32,
        GIM_CheckType, /*MI*/1, /*Op*/2, /*Type*/GILLT_s32,
        GIM_RecordInsn, /*DefineMI*/2, /*MI*/0, /*OpIdx*/2, // MIs[2]
        GIM_CheckOpcode, /*MI*/2, GIMT_Encode2(TargetOpcode::G_FMAXNUM),
        GIM_CheckType, /*MI*/2, /*Op*/1, /*Type*/GILLT_s32,
        GIM_CheckType, /*MI*/2, /*Op*/2, /*Type*/GILLT_s32,
        GIM_RecordInsn, /*DefineMI*/3, /*MI*/2, /*OpIdx*/2, // MIs[3]
        GIM_CheckOpcode, /*MI*/3, GIMT_Encode2(TargetOpcode::G_FMINNUM),
        // MIs[3] VOP3Mods:src0:src0_mods
        GIM_CheckIsSameOperand, /*MI*/3, /*OpIdx*/1, /*OtherMI*/1, /*OtherOpIdx*/1,
        // MIs[3] VOP3Mods:src1:src1_mods
        GIM_CheckIsSameOperand, /*MI*/3, /*OpIdx*/2, /*OtherMI*/1, /*OtherOpIdx*/2,
        GIM_CheckCxxInsnPredicate, /*MI*/0, /*FnId*/GIMT_Encode2(GICXXPred_MI_Predicate_fminnum_like_nnan),
        GIM_CheckIsSafeToFold, /*InsnID*/1,
        GIM_CheckIsSafeToFold, /*InsnID*/2,
        GIM_CheckIsSafeToFold, /*InsnID*/3,
        GIM_CheckComplexPattern, /*MI*/1, /*Op*/1, /*Renderer*/GIMT_Encode2(0), GIMT_Encode2(GICP_gi_vop3mods),
        GIM_CheckComplexPattern, /*MI*/1, /*Op*/2, /*Renderer*/GIMT_Encode2(1), GIMT_Encode2(GICP_gi_vop3mods),
        GIM_CheckComplexPattern, /*MI*/2, /*Op*/1, /*Renderer*/GIMT_Encode2(2), GIMT_Encode2(GICP_gi_vop3mods),
        // (fminnum:{ *:[f32] } (fmaxnum:{ *:[f32] } (VOP3Mods:{ *:[f32] } f32:{ *:[f32] }:$src0, i32:{ *:[i32] }:$src0_mods), (VOP3Mods:{ *:[f32] } f32:{ *:[f32] }:$src1, i32:{ *:[i32] }:$src1_mods)), (fmaxnum:{ *:[f32] } (VOP3Mods:{ *:[f32] } f32:{ *:[f32] }:$src2, i32:{ *:[i32] }:$src2_mods), (fminnum:{ *:[f32] } (VOP3Mods:{ *:[f32] } f32:{ *:[f32] }:$src0, i32:{ *:[i32] }:$src0_mods), (VOP3Mods:{ *:[f32] } f32:{ *:[f32] }:$src1, i32:{ *:[i32] }:$src1_mods))))<<P:Predicate_fminnum_like_nnan>>  =>  (V_MED3_F32_e64:{ *:[f32] } ?:{ *:[i32] }:$src0_mods, ?:{ *:[f32] }:$src0, ?:{ *:[i32] }:$src1_mods, ?:{ *:[f32] }:$src1, ?:{ *:[i32] }:$src2_mods, ?:{ *:[f32] }:$src2, 0:{ *:[i1] }, 0:{ *:[i32] })
        GIR_BuildMI, /*InsnID*/0, /*Opcode*/GIMT_Encode2(AMDGPU::V_MED3_F32_e64),
        GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/0, // DstI[vdst]
        GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/1, // src0_mods
        GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/0, // src0
        GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(1), /*SubOperand*/1, // src1_mods
        GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(1), /*SubOperand*/0, // src1
        GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(2), /*SubOperand*/1, // src2_mods
        GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(2), /*SubOperand*/0, // src2
        GIR_AddImm8, /*InsnID*/0, /*Imm*/0,
        GIR_AddImm8, /*InsnID*/0, /*Imm*/0,
        GIR_ConstrainSelectedInstOperands, /*InsnID*/0,
        GIR_EraseFromParent, /*InsnID*/0,
        // GIR_Coverage, 10466,
        GIR_Done,
      // Label 4325: @269347
      GIM_Try, /*On fail goto*//*Label 4326*/ GIMT_Encode4(269487), // Rule ID 10467 //
        GIM_CheckRegBankForClass, /*MI*/0, /*Op*/0, /*RC*/GIMT_Encode2(AMDGPU::VGPR_32RegClassID),
        GIM_RecordInsn, /*DefineMI*/1, /*MI*/0, /*OpIdx*/1, // MIs[1]
        GIM_CheckOpcode, /*MI*/1, GIMT_Encode2(TargetOpcode::G_FMAXNUM),
        GIM_CheckType, /*MI*/1, /*Op*/1, /*Type*/GILLT_s32,
        GIM_CheckType, /*MI*/1, /*Op*/2, /*Type*/GILLT_s32,
        GIM_RecordInsn, /*DefineMI*/2, /*MI*/0, /*OpIdx*/2, // MIs[2]
        GIM_CheckOpcode, /*MI*/2, GIMT_Encode2(TargetOpcode::G_FMAXNUM),
        GIM_CheckType, /*MI*/2, /*Op*/1, /*Type*/GILLT_s32,
        GIM_CheckType, /*MI*/2, /*Op*/2, /*Type*/GILLT_s32,
        GIM_RecordInsn, /*DefineMI*/3, /*MI*/2, /*OpIdx*/2, // MIs[3]
        GIM_CheckOpcode, /*MI*/3, GIMT_Encode2(TargetOpcode::G_FMINNUM),
        // MIs[3] VOP3Mods:src1:src1_mods
        GIM_CheckIsSameOperand, /*MI*/3, /*OpIdx*/1, /*OtherMI*/1, /*OtherOpIdx*/2,
        // MIs[3] VOP3Mods:src0:src0_mods
        GIM_CheckIsSameOperand, /*MI*/3, /*OpIdx*/2, /*OtherMI*/1, /*OtherOpIdx*/1,
        GIM_CheckCxxInsnPredicate, /*MI*/0, /*FnId*/GIMT_Encode2(GICXXPred_MI_Predicate_fminnum_like_nnan),
        GIM_CheckIsSafeToFold, /*InsnID*/1,
        GIM_CheckIsSafeToFold, /*InsnID*/2,
        GIM_CheckIsSafeToFold, /*InsnID*/3,
        GIM_CheckComplexPattern, /*MI*/1, /*Op*/1, /*Renderer*/GIMT_Encode2(0), GIMT_Encode2(GICP_gi_vop3mods),
        GIM_CheckComplexPattern, /*MI*/1, /*Op*/2, /*Renderer*/GIMT_Encode2(1), GIMT_Encode2(GICP_gi_vop3mods),
        GIM_CheckComplexPattern, /*MI*/2, /*Op*/1, /*Renderer*/GIMT_Encode2(2), GIMT_Encode2(GICP_gi_vop3mods),
        // (fminnum:{ *:[f32] } (fmaxnum:{ *:[f32] } (VOP3Mods:{ *:[f32] } f32:{ *:[f32] }:$src0, i32:{ *:[i32] }:$src0_mods), (VOP3Mods:{ *:[f32] } f32:{ *:[f32] }:$src1, i32:{ *:[i32] }:$src1_mods)), (fmaxnum:{ *:[f32] } (VOP3Mods:{ *:[f32] } f32:{ *:[f32] }:$src2, i32:{ *:[i32] }:$src2_mods), (fminnum:{ *:[f32] } (VOP3Mods:{ *:[f32] } f32:{ *:[f32] }:$src1, i32:{ *:[i32] }:$src1_mods), (VOP3Mods:{ *:[f32] } f32:{ *:[f32] }:$src0, i32:{ *:[i32] }:$src0_mods))))<<P:Predicate_fminnum_like_nnan>>  =>  (V_MED3_F32_e64:{ *:[f32] } ?:{ *:[i32] }:$src0_mods, ?:{ *:[f32] }:$src0, ?:{ *:[i32] }:$src1_mods, ?:{ *:[f32] }:$src1, ?:{ *:[i32] }:$src2_mods, ?:{ *:[f32] }:$src2, 0:{ *:[i1] }, 0:{ *:[i32] })
        GIR_BuildMI, /*InsnID*/0, /*Opcode*/GIMT_Encode2(AMDGPU::V_MED3_F32_e64),
        GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/0, // DstI[vdst]
        GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/1, // src0_mods
        GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/0, // src0
        GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(1), /*SubOperand*/1, // src1_mods
        GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(1), /*SubOperand*/0, // src1
        GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(2), /*SubOperand*/1, // src2_mods
        GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(2), /*SubOperand*/0, // src2
        GIR_AddImm8, /*InsnID*/0, /*Imm*/0,
        GIR_AddImm8, /*InsnID*/0, /*Imm*/0,
        GIR_ConstrainSelectedInstOperands, /*InsnID*/0,
        GIR_EraseFromParent, /*InsnID*/0,
        // GIR_Coverage, 10467,
        GIR_Done,
      // Label 4326: @269487
      GIM_Try, /*On fail goto*//*Label 4327*/ GIMT_Encode4(269627), // Rule ID 10470 //
        GIM_CheckRegBankForClass, /*MI*/0, /*Op*/0, /*RC*/GIMT_Encode2(AMDGPU::VGPR_32RegClassID),
        GIM_RecordInsn, /*DefineMI*/1, /*MI*/0, /*OpIdx*/1, // MIs[1]
        GIM_CheckOpcode, /*MI*/1, GIMT_Encode2(TargetOpcode::G_FMAXNUM),
        GIM_CheckType, /*MI*/1, /*Op*/1, /*Type*/GILLT_s32,
        GIM_CheckType, /*MI*/1, /*Op*/2, /*Type*/GILLT_s32,
        GIM_RecordInsn, /*DefineMI*/2, /*MI*/0, /*OpIdx*/2, // MIs[2]
        GIM_CheckOpcode, /*MI*/2, GIMT_Encode2(TargetOpcode::G_FMAXNUM),
        GIM_CheckType, /*MI*/2, /*Op*/1, /*Type*/GILLT_s32,
        GIM_CheckType, /*MI*/2, /*Op*/2, /*Type*/GILLT_s32,
        GIM_RecordInsn, /*DefineMI*/3, /*MI*/2, /*OpIdx*/2, // MIs[3]
        GIM_CheckOpcode, /*MI*/3, GIMT_Encode2(TargetOpcode::G_FMINNUM),
        // MIs[3] VOP3Mods:src0:src0_mods
        GIM_CheckIsSameOperand, /*MI*/3, /*OpIdx*/1, /*OtherMI*/1, /*OtherOpIdx*/2,
        // MIs[3] VOP3Mods:src1:src1_mods
        GIM_CheckIsSameOperand, /*MI*/3, /*OpIdx*/2, /*OtherMI*/1, /*OtherOpIdx*/1,
        GIM_CheckCxxInsnPredicate, /*MI*/0, /*FnId*/GIMT_Encode2(GICXXPred_MI_Predicate_fminnum_like_nnan),
        GIM_CheckIsSafeToFold, /*InsnID*/1,
        GIM_CheckIsSafeToFold, /*InsnID*/2,
        GIM_CheckIsSafeToFold, /*InsnID*/3,
        GIM_CheckComplexPattern, /*MI*/1, /*Op*/1, /*Renderer*/GIMT_Encode2(0), GIMT_Encode2(GICP_gi_vop3mods),
        GIM_CheckComplexPattern, /*MI*/1, /*Op*/2, /*Renderer*/GIMT_Encode2(1), GIMT_Encode2(GICP_gi_vop3mods),
        GIM_CheckComplexPattern, /*MI*/2, /*Op*/1, /*Renderer*/GIMT_Encode2(2), GIMT_Encode2(GICP_gi_vop3mods),
        // (fminnum:{ *:[f32] } (fmaxnum:{ *:[f32] } (VOP3Mods:{ *:[f32] } f32:{ *:[f32] }:$src1, i32:{ *:[i32] }:$src1_mods), (VOP3Mods:{ *:[f32] } f32:{ *:[f32] }:$src0, i32:{ *:[i32] }:$src0_mods)), (fmaxnum:{ *:[f32] } (VOP3Mods:{ *:[f32] } f32:{ *:[f32] }:$src2, i32:{ *:[i32] }:$src2_mods), (fminnum:{ *:[f32] } (VOP3Mods:{ *:[f32] } f32:{ *:[f32] }:$src0, i32:{ *:[i32] }:$src0_mods), (VOP3Mods:{ *:[f32] } f32:{ *:[f32] }:$src1, i32:{ *:[i32] }:$src1_mods))))<<P:Predicate_fminnum_like_nnan>>  =>  (V_MED3_F32_e64:{ *:[f32] } ?:{ *:[i32] }:$src0_mods, ?:{ *:[f32] }:$src0, ?:{ *:[i32] }:$src1_mods, ?:{ *:[f32] }:$src1, ?:{ *:[i32] }:$src2_mods, ?:{ *:[f32] }:$src2, 0:{ *:[i1] }, 0:{ *:[i32] })
        GIR_BuildMI, /*InsnID*/0, /*Opcode*/GIMT_Encode2(AMDGPU::V_MED3_F32_e64),
        GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/0, // DstI[vdst]
        GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(1), /*SubOperand*/1, // src0_mods
        GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(1), /*SubOperand*/0, // src0
        GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/1, // src1_mods
        GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/0, // src1
        GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(2), /*SubOperand*/1, // src2_mods
        GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(2), /*SubOperand*/0, // src2
        GIR_AddImm8, /*InsnID*/0, /*Imm*/0,
        GIR_AddImm8, /*InsnID*/0, /*Imm*/0,
        GIR_ConstrainSelectedInstOperands, /*InsnID*/0,
        GIR_EraseFromParent, /*InsnID*/0,
        // GIR_Coverage, 10470,
        GIR_Done,
      // Label 4327: @269627
      GIM_Try, /*On fail goto*//*Label 4328*/ GIMT_Encode4(269767), // Rule ID 10471 //
        GIM_CheckRegBankForClass, /*MI*/0, /*Op*/0, /*RC*/GIMT_Encode2(AMDGPU::VGPR_32RegClassID),
        GIM_RecordInsn, /*DefineMI*/1, /*MI*/0, /*OpIdx*/1, // MIs[1]
        GIM_CheckOpcode, /*MI*/1, GIMT_Encode2(TargetOpcode::G_FMAXNUM),
        GIM_CheckType, /*MI*/1, /*Op*/1, /*Type*/GILLT_s32,
        GIM_CheckType, /*MI*/1, /*Op*/2, /*Type*/GILLT_s32,
        GIM_RecordInsn, /*DefineMI*/2, /*MI*/0, /*OpIdx*/2, // MIs[2]
        GIM_CheckOpcode, /*MI*/2, GIMT_Encode2(TargetOpcode::G_FMAXNUM),
        GIM_CheckType, /*MI*/2, /*Op*/1, /*Type*/GILLT_s32,
        GIM_CheckType, /*MI*/2, /*Op*/2, /*Type*/GILLT_s32,
        GIM_RecordInsn, /*DefineMI*/3, /*MI*/2, /*OpIdx*/2, // MIs[3]
        GIM_CheckOpcode, /*MI*/3, GIMT_Encode2(TargetOpcode::G_FMINNUM),
        // MIs[3] VOP3Mods:src1:src1_mods
        GIM_CheckIsSameOperand, /*MI*/3, /*OpIdx*/1, /*OtherMI*/1, /*OtherOpIdx*/1,
        // MIs[3] VOP3Mods:src0:src0_mods
        GIM_CheckIsSameOperand, /*MI*/3, /*OpIdx*/2, /*OtherMI*/1, /*OtherOpIdx*/2,
        GIM_CheckCxxInsnPredicate, /*MI*/0, /*FnId*/GIMT_Encode2(GICXXPred_MI_Predicate_fminnum_like_nnan),
        GIM_CheckIsSafeToFold, /*InsnID*/1,
        GIM_CheckIsSafeToFold, /*InsnID*/2,
        GIM_CheckIsSafeToFold, /*InsnID*/3,
        GIM_CheckComplexPattern, /*MI*/1, /*Op*/1, /*Renderer*/GIMT_Encode2(0), GIMT_Encode2(GICP_gi_vop3mods),
        GIM_CheckComplexPattern, /*MI*/1, /*Op*/2, /*Renderer*/GIMT_Encode2(1), GIMT_Encode2(GICP_gi_vop3mods),
        GIM_CheckComplexPattern, /*MI*/2, /*Op*/1, /*Renderer*/GIMT_Encode2(2), GIMT_Encode2(GICP_gi_vop3mods),
        // (fminnum:{ *:[f32] } (fmaxnum:{ *:[f32] } (VOP3Mods:{ *:[f32] } f32:{ *:[f32] }:$src1, i32:{ *:[i32] }:$src1_mods), (VOP3Mods:{ *:[f32] } f32:{ *:[f32] }:$src0, i32:{ *:[i32] }:$src0_mods)), (fmaxnum:{ *:[f32] } (VOP3Mods:{ *:[f32] } f32:{ *:[f32] }:$src2, i32:{ *:[i32] }:$src2_mods), (fminnum:{ *:[f32] } (VOP3Mods:{ *:[f32] } f32:{ *:[f32] }:$src1, i32:{ *:[i32] }:$src1_mods), (VOP3Mods:{ *:[f32] } f32:{ *:[f32] }:$src0, i32:{ *:[i32] }:$src0_mods))))<<P:Predicate_fminnum_like_nnan>>  =>  (V_MED3_F32_e64:{ *:[f32] } ?:{ *:[i32] }:$src0_mods, ?:{ *:[f32] }:$src0, ?:{ *:[i32] }:$src1_mods, ?:{ *:[f32] }:$src1, ?:{ *:[i32] }:$src2_mods, ?:{ *:[f32] }:$src2, 0:{ *:[i1] }, 0:{ *:[i32] })
        GIR_BuildMI, /*InsnID*/0, /*Opcode*/GIMT_Encode2(AMDGPU::V_MED3_F32_e64),
        GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/0, // DstI[vdst]
        GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(1), /*SubOperand*/1, // src0_mods
        GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(1), /*SubOperand*/0, // src0
        GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/1, // src1_mods
        GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/0, // src1
        GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(2), /*SubOperand*/1, // src2_mods
        GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(2), /*SubOperand*/0, // src2
        GIR_AddImm8, /*InsnID*/0, /*Imm*/0,
        GIR_AddImm8, /*InsnID*/0, /*Imm*/0,
        GIR_ConstrainSelectedInstOperands, /*InsnID*/0,
        GIR_EraseFromParent, /*InsnID*/0,
        // GIR_Coverage, 10471,
        GIR_Done,
      // Label 4328: @269767
      GIM_Try, /*On fail goto*//*Label 4329*/ GIMT_Encode4(269907), // Rule ID 10451 //
        GIM_CheckRegBankForClass, /*MI*/0, /*Op*/0, /*RC*/GIMT_Encode2(AMDGPU::VGPR_32RegClassID),
        GIM_RecordInsn, /*DefineMI*/1, /*MI*/0, /*OpIdx*/1, // MIs[1]
        GIM_CheckOpcode, /*MI*/1, GIMT_Encode2(TargetOpcode::G_FMAXNUM),
        GIM_CheckType, /*MI*/1, /*Op*/1, /*Type*/GILLT_s32,
        GIM_CheckType, /*MI*/1, /*Op*/2, /*Type*/GILLT_s32,
        GIM_RecordInsn, /*DefineMI*/2, /*MI*/0, /*OpIdx*/2, // MIs[2]
        GIM_CheckOpcode, /*MI*/2, GIMT_Encode2(TargetOpcode::G_FMAXNUM),
        GIM_CheckType, /*MI*/2, /*Op*/1, /*Type*/GILLT_s32,
        GIM_CheckType, /*MI*/2, /*Op*/2, /*Type*/GILLT_s32,
        GIM_RecordInsn, /*DefineMI*/3, /*MI*/2, /*OpIdx*/2, // MIs[3]
        GIM_CheckOpcode, /*MI*/3, GIMT_Encode2(TargetOpcode::G_FMINNUM_IEEE),
        // MIs[3] VOP3Mods:src0:src0_mods
        GIM_CheckIsSameOperand, /*MI*/3, /*OpIdx*/1, /*OtherMI*/1, /*OtherOpIdx*/1,
        // MIs[3] VOP3Mods:src1:src1_mods
        GIM_CheckIsSameOperand, /*MI*/3, /*OpIdx*/2, /*OtherMI*/1, /*OtherOpIdx*/2,
        GIM_CheckCxxInsnPredicate, /*MI*/0, /*FnId*/GIMT_Encode2(GICXXPred_MI_Predicate_fminnum_like_nnan),
        GIM_CheckIsSafeToFold, /*InsnID*/1,
        GIM_CheckIsSafeToFold, /*InsnID*/2,
        GIM_CheckIsSafeToFold, /*InsnID*/3,
        GIM_CheckComplexPattern, /*MI*/1, /*Op*/1, /*Renderer*/GIMT_Encode2(0), GIMT_Encode2(GICP_gi_vop3mods),
        GIM_CheckComplexPattern, /*MI*/1, /*Op*/2, /*Renderer*/GIMT_Encode2(1), GIMT_Encode2(GICP_gi_vop3mods),
        GIM_CheckComplexPattern, /*MI*/2, /*Op*/1, /*Renderer*/GIMT_Encode2(2), GIMT_Encode2(GICP_gi_vop3mods),
        // (fminnum:{ *:[f32] } (fmaxnum:{ *:[f32] } (VOP3Mods:{ *:[f32] } f32:{ *:[f32] }:$src0, i32:{ *:[i32] }:$src0_mods), (VOP3Mods:{ *:[f32] } f32:{ *:[f32] }:$src1, i32:{ *:[i32] }:$src1_mods)), (fmaxnum:{ *:[f32] } (VOP3Mods:{ *:[f32] } f32:{ *:[f32] }:$src2, i32:{ *:[i32] }:$src2_mods), (fminnum_ieee:{ *:[f32] } (VOP3Mods:{ *:[f32] } f32:{ *:[f32] }:$src0, i32:{ *:[i32] }:$src0_mods), (VOP3Mods:{ *:[f32] } f32:{ *:[f32] }:$src1, i32:{ *:[i32] }:$src1_mods))))<<P:Predicate_fminnum_like_nnan>>  =>  (V_MED3_F32_e64:{ *:[f32] } ?:{ *:[i32] }:$src0_mods, ?:{ *:[f32] }:$src0, ?:{ *:[i32] }:$src1_mods, ?:{ *:[f32] }:$src1, ?:{ *:[i32] }:$src2_mods, ?:{ *:[f32] }:$src2, 0:{ *:[i1] }, 0:{ *:[i32] })
        GIR_BuildMI, /*InsnID*/0, /*Opcode*/GIMT_Encode2(AMDGPU::V_MED3_F32_e64),
        GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/0, // DstI[vdst]
        GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/1, // src0_mods
        GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/0, // src0
        GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(1), /*SubOperand*/1, // src1_mods
        GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(1), /*SubOperand*/0, // src1
        GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(2), /*SubOperand*/1, // src2_mods
        GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(2), /*SubOperand*/0, // src2
        GIR_AddImm8, /*InsnID*/0, /*Imm*/0,
        GIR_AddImm8, /*InsnID*/0, /*Imm*/0,
        GIR_ConstrainSelectedInstOperands, /*InsnID*/0,
        GIR_EraseFromParent, /*InsnID*/0,
        // GIR_Coverage, 10451,
        GIR_Done,
      // Label 4329: @269907
      GIM_Try, /*On fail goto*//*Label 4330*/ GIMT_Encode4(270047), // Rule ID 10452 //
        GIM_CheckRegBankForClass, /*MI*/0, /*Op*/0, /*RC*/GIMT_Encode2(AMDGPU::VGPR_32RegClassID),
        GIM_RecordInsn, /*DefineMI*/1, /*MI*/0, /*OpIdx*/1, // MIs[1]
        GIM_CheckOpcode, /*MI*/1, GIMT_Encode2(TargetOpcode::G_FMAXNUM),
        GIM_CheckType, /*MI*/1, /*Op*/1, /*Type*/GILLT_s32,
        GIM_CheckType, /*MI*/1, /*Op*/2, /*Type*/GILLT_s32,
        GIM_RecordInsn, /*DefineMI*/2, /*MI*/0, /*OpIdx*/2, // MIs[2]
        GIM_CheckOpcode, /*MI*/2, GIMT_Encode2(TargetOpcode::G_FMAXNUM),
        GIM_CheckType, /*MI*/2, /*Op*/1, /*Type*/GILLT_s32,
        GIM_CheckType, /*MI*/2, /*Op*/2, /*Type*/GILLT_s32,
        GIM_RecordInsn, /*DefineMI*/3, /*MI*/2, /*OpIdx*/2, // MIs[3]
        GIM_CheckOpcode, /*MI*/3, GIMT_Encode2(TargetOpcode::G_FMINNUM_IEEE),
        // MIs[3] VOP3Mods:src1:src1_mods
        GIM_CheckIsSameOperand, /*MI*/3, /*OpIdx*/1, /*OtherMI*/1, /*OtherOpIdx*/2,
        // MIs[3] VOP3Mods:src0:src0_mods
        GIM_CheckIsSameOperand, /*MI*/3, /*OpIdx*/2, /*OtherMI*/1, /*OtherOpIdx*/1,
        GIM_CheckCxxInsnPredicate, /*MI*/0, /*FnId*/GIMT_Encode2(GICXXPred_MI_Predicate_fminnum_like_nnan),
        GIM_CheckIsSafeToFold, /*InsnID*/1,
        GIM_CheckIsSafeToFold, /*InsnID*/2,
        GIM_CheckIsSafeToFold, /*InsnID*/3,
        GIM_CheckComplexPattern, /*MI*/1, /*Op*/1, /*Renderer*/GIMT_Encode2(0), GIMT_Encode2(GICP_gi_vop3mods),
        GIM_CheckComplexPattern, /*MI*/1, /*Op*/2, /*Renderer*/GIMT_Encode2(1), GIMT_Encode2(GICP_gi_vop3mods),
        GIM_CheckComplexPattern, /*MI*/2, /*Op*/1, /*Renderer*/GIMT_Encode2(2), GIMT_Encode2(GICP_gi_vop3mods),
        // (fminnum:{ *:[f32] } (fmaxnum:{ *:[f32] } (VOP3Mods:{ *:[f32] } f32:{ *:[f32] }:$src0, i32:{ *:[i32] }:$src0_mods), (VOP3Mods:{ *:[f32] } f32:{ *:[f32] }:$src1, i32:{ *:[i32] }:$src1_mods)), (fmaxnum:{ *:[f32] } (VOP3Mods:{ *:[f32] } f32:{ *:[f32] }:$src2, i32:{ *:[i32] }:$src2_mods), (fminnum_ieee:{ *:[f32] } (VOP3Mods:{ *:[f32] } f32:{ *:[f32] }:$src1, i32:{ *:[i32] }:$src1_mods), (VOP3Mods:{ *:[f32] } f32:{ *:[f32] }:$src0, i32:{ *:[i32] }:$src0_mods))))<<P:Predicate_fminnum_like_nnan>>  =>  (V_MED3_F32_e64:{ *:[f32] } ?:{ *:[i32] }:$src0_mods, ?:{ *:[f32] }:$src0, ?:{ *:[i32] }:$src1_mods, ?:{ *:[f32] }:$src1, ?:{ *:[i32] }:$src2_mods, ?:{ *:[f32] }:$src2, 0:{ *:[i1] }, 0:{ *:[i32] })
        GIR_BuildMI, /*InsnID*/0, /*Opcode*/GIMT_Encode2(AMDGPU::V_MED3_F32_e64),
        GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/0, // DstI[vdst]
        GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/1, // src0_mods
        GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/0, // src0
        GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(1), /*SubOperand*/1, // src1_mods
        GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(1), /*SubOperand*/0, // src1
        GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(2), /*SubOperand*/1, // src2_mods
        GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(2), /*SubOperand*/0, // src2
        GIR_AddImm8, /*InsnID*/0, /*Imm*/0,
        GIR_AddImm8, /*InsnID*/0, /*Imm*/0,
        GIR_ConstrainSelectedInstOperands, /*InsnID*/0,
        GIR_EraseFromParent, /*InsnID*/0,
        // GIR_Coverage, 10452,
        GIR_Done,
      // Label 4330: @270047
      GIM_Try, /*On fail goto*//*Label 4331*/ GIMT_Encode4(270187), // Rule ID 10455 //
        GIM_CheckRegBankForClass, /*MI*/0, /*Op*/0, /*RC*/GIMT_Encode2(AMDGPU::VGPR_32RegClassID),
        GIM_RecordInsn, /*DefineMI*/1, /*MI*/0, /*OpIdx*/1, // MIs[1]
        GIM_CheckOpcode, /*MI*/1, GIMT_Encode2(TargetOpcode::G_FMAXNUM),
        GIM_CheckType, /*MI*/1, /*Op*/1, /*Type*/GILLT_s32,
        GIM_CheckType, /*MI*/1, /*Op*/2, /*Type*/GILLT_s32,
        GIM_RecordInsn, /*DefineMI*/2, /*MI*/0, /*OpIdx*/2, // MIs[2]
        GIM_CheckOpcode, /*MI*/2, GIMT_Encode2(TargetOpcode::G_FMAXNUM),
        GIM_CheckType, /*MI*/2, /*Op*/1, /*Type*/GILLT_s32,
        GIM_CheckType, /*MI*/2, /*Op*/2, /*Type*/GILLT_s32,
        GIM_RecordInsn, /*DefineMI*/3, /*MI*/2, /*OpIdx*/2, // MIs[3]
        GIM_CheckOpcode, /*MI*/3, GIMT_Encode2(TargetOpcode::G_FMINNUM_IEEE),
        // MIs[3] VOP3Mods:src0:src0_mods
        GIM_CheckIsSameOperand, /*MI*/3, /*OpIdx*/1, /*OtherMI*/1, /*OtherOpIdx*/2,
        // MIs[3] VOP3Mods:src1:src1_mods
        GIM_CheckIsSameOperand, /*MI*/3, /*OpIdx*/2, /*OtherMI*/1, /*OtherOpIdx*/1,
        GIM_CheckCxxInsnPredicate, /*MI*/0, /*FnId*/GIMT_Encode2(GICXXPred_MI_Predicate_fminnum_like_nnan),
        GIM_CheckIsSafeToFold, /*InsnID*/1,
        GIM_CheckIsSafeToFold, /*InsnID*/2,
        GIM_CheckIsSafeToFold, /*InsnID*/3,
        GIM_CheckComplexPattern, /*MI*/1, /*Op*/1, /*Renderer*/GIMT_Encode2(0), GIMT_Encode2(GICP_gi_vop3mods),
        GIM_CheckComplexPattern, /*MI*/1, /*Op*/2, /*Renderer*/GIMT_Encode2(1), GIMT_Encode2(GICP_gi_vop3mods),
        GIM_CheckComplexPattern, /*MI*/2, /*Op*/1, /*Renderer*/GIMT_Encode2(2), GIMT_Encode2(GICP_gi_vop3mods),
        // (fminnum:{ *:[f32] } (fmaxnum:{ *:[f32] } (VOP3Mods:{ *:[f32] } f32:{ *:[f32] }:$src1, i32:{ *:[i32] }:$src1_mods), (VOP3Mods:{ *:[f32] } f32:{ *:[f32] }:$src0, i32:{ *:[i32] }:$src0_mods)), (fmaxnum:{ *:[f32] } (VOP3Mods:{ *:[f32] } f32:{ *:[f32] }:$src2, i32:{ *:[i32] }:$src2_mods), (fminnum_ieee:{ *:[f32] } (VOP3Mods:{ *:[f32] } f32:{ *:[f32] }:$src0, i32:{ *:[i32] }:$src0_mods), (VOP3Mods:{ *:[f32] } f32:{ *:[f32] }:$src1, i32:{ *:[i32] }:$src1_mods))))<<P:Predicate_fminnum_like_nnan>>  =>  (V_MED3_F32_e64:{ *:[f32] } ?:{ *:[i32] }:$src0_mods, ?:{ *:[f32] }:$src0, ?:{ *:[i32] }:$src1_mods, ?:{ *:[f32] }:$src1, ?:{ *:[i32] }:$src2_mods, ?:{ *:[f32] }:$src2, 0:{ *:[i1] }, 0:{ *:[i32] })
        GIR_BuildMI, /*InsnID*/0, /*Opcode*/GIMT_Encode2(AMDGPU::V_MED3_F32_e64),
        GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/0, // DstI[vdst]
        GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(1), /*SubOperand*/1, // src0_mods
        GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(1), /*SubOperand*/0, // src0
        GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/1, // src1_mods
        GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/0, // src1
        GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(2), /*SubOperand*/1, // src2_mods
        GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(2), /*SubOperand*/0, // src2
        GIR_AddImm8, /*InsnID*/0, /*Imm*/0,
        GIR_AddImm8, /*InsnID*/0, /*Imm*/0,
        GIR_ConstrainSelectedInstOperands, /*InsnID*/0,
        GIR_EraseFromParent, /*InsnID*/0,
        // GIR_Coverage, 10455,
        GIR_Done,
      // Label 4331: @270187
      GIM_Try, /*On fail goto*//*Label 4332*/ GIMT_Encode4(270327), // Rule ID 10456 //
        GIM_CheckRegBankForClass, /*MI*/0, /*Op*/0, /*RC*/GIMT_Encode2(AMDGPU::VGPR_32RegClassID),
        GIM_RecordInsn, /*DefineMI*/1, /*MI*/0, /*OpIdx*/1, // MIs[1]
        GIM_CheckOpcode, /*MI*/1, GIMT_Encode2(TargetOpcode::G_FMAXNUM),
        GIM_CheckType, /*MI*/1, /*Op*/1, /*Type*/GILLT_s32,
        GIM_CheckType, /*MI*/1, /*Op*/2, /*Type*/GILLT_s32,
        GIM_RecordInsn, /*DefineMI*/2, /*MI*/0, /*OpIdx*/2, // MIs[2]
        GIM_CheckOpcode, /*MI*/2, GIMT_Encode2(TargetOpcode::G_FMAXNUM),
        GIM_CheckType, /*MI*/2, /*Op*/1, /*Type*/GILLT_s32,
        GIM_CheckType, /*MI*/2, /*Op*/2, /*Type*/GILLT_s32,
        GIM_RecordInsn, /*DefineMI*/3, /*MI*/2, /*OpIdx*/2, // MIs[3]
        GIM_CheckOpcode, /*MI*/3, GIMT_Encode2(TargetOpcode::G_FMINNUM_IEEE),
        // MIs[3] VOP3Mods:src1:src1_mods
        GIM_CheckIsSameOperand, /*MI*/3, /*OpIdx*/1, /*OtherMI*/1, /*OtherOpIdx*/1,
        // MIs[3] VOP3Mods:src0:src0_mods
        GIM_CheckIsSameOperand, /*MI*/3, /*OpIdx*/2, /*OtherMI*/1, /*OtherOpIdx*/2,
        GIM_CheckCxxInsnPredicate, /*MI*/0, /*FnId*/GIMT_Encode2(GICXXPred_MI_Predicate_fminnum_like_nnan),
        GIM_CheckIsSafeToFold, /*InsnID*/1,
        GIM_CheckIsSafeToFold, /*InsnID*/2,
        GIM_CheckIsSafeToFold, /*InsnID*/3,
        GIM_CheckComplexPattern, /*MI*/1, /*Op*/1, /*Renderer*/GIMT_Encode2(0), GIMT_Encode2(GICP_gi_vop3mods),
        GIM_CheckComplexPattern, /*MI*/1, /*Op*/2, /*Renderer*/GIMT_Encode2(1), GIMT_Encode2(GICP_gi_vop3mods),
        GIM_CheckComplexPattern, /*MI*/2, /*Op*/1, /*Renderer*/GIMT_Encode2(2), GIMT_Encode2(GICP_gi_vop3mods),
        // (fminnum:{ *:[f32] } (fmaxnum:{ *:[f32] } (VOP3Mods:{ *:[f32] } f32:{ *:[f32] }:$src1, i32:{ *:[i32] }:$src1_mods), (VOP3Mods:{ *:[f32] } f32:{ *:[f32] }:$src0, i32:{ *:[i32] }:$src0_mods)), (fmaxnum:{ *:[f32] } (VOP3Mods:{ *:[f32] } f32:{ *:[f32] }:$src2, i32:{ *:[i32] }:$src2_mods), (fminnum_ieee:{ *:[f32] } (VOP3Mods:{ *:[f32] } f32:{ *:[f32] }:$src1, i32:{ *:[i32] }:$src1_mods), (VOP3Mods:{ *:[f32] } f32:{ *:[f32] }:$src0, i32:{ *:[i32] }:$src0_mods))))<<P:Predicate_fminnum_like_nnan>>  =>  (V_MED3_F32_e64:{ *:[f32] } ?:{ *:[i32] }:$src0_mods, ?:{ *:[f32] }:$src0, ?:{ *:[i32] }:$src1_mods, ?:{ *:[f32] }:$src1, ?:{ *:[i32] }:$src2_mods, ?:{ *:[f32] }:$src2, 0:{ *:[i1] }, 0:{ *:[i32] })
        GIR_BuildMI, /*InsnID*/0, /*Opcode*/GIMT_Encode2(AMDGPU::V_MED3_F32_e64),
        GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/0, // DstI[vdst]
        GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(1), /*SubOperand*/1, // src0_mods
        GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(1), /*SubOperand*/0, // src0
        GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/1, // src1_mods
        GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/0, // src1
        GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(2), /*SubOperand*/1, // src2_mods
        GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(2), /*SubOperand*/0, // src2
        GIR_AddImm8, /*InsnID*/0, /*Imm*/0,
        GIR_AddImm8, /*InsnID*/0, /*Imm*/0,
        GIR_ConstrainSelectedInstOperands, /*InsnID*/0,
        GIR_EraseFromParent, /*InsnID*/0,
        // GIR_Coverage, 10456,
        GIR_Done,
      // Label 4332: @270327
      GIM_Try, /*On fail goto*//*Label 4333*/ GIMT_Encode4(270467), // Rule ID 6513 //
        GIM_CheckRegBankForClass, /*MI*/0, /*Op*/0, /*RC*/GIMT_Encode2(AMDGPU::VGPR_32RegClassID),
        GIM_RecordInsn, /*DefineMI*/1, /*MI*/0, /*OpIdx*/1, // MIs[1]
        GIM_CheckOpcode, /*MI*/1, GIMT_Encode2(TargetOpcode::G_FMAXNUM),
        GIM_CheckType, /*MI*/1, /*Op*/1, /*Type*/GILLT_s32,
        GIM_CheckType, /*MI*/1, /*Op*/2, /*Type*/GILLT_s32,
        GIM_RecordInsn, /*DefineMI*/2, /*MI*/0, /*OpIdx*/2, // MIs[2]
        GIM_CheckOpcode, /*MI*/2, GIMT_Encode2(TargetOpcode::G_FMAXNUM),
        GIM_CheckType, /*MI*/2, /*Op*/1, /*Type*/GILLT_s32,
        GIM_CheckType, /*MI*/2, /*Op*/2, /*Type*/GILLT_s32,
        GIM_RecordInsn, /*DefineMI*/3, /*MI*/2, /*OpIdx*/1, // MIs[3]
        GIM_CheckOpcode, /*MI*/3, GIMT_Encode2(TargetOpcode::G_FMINNUM),
        // MIs[3] VOP3Mods:src0:src0_mods
        GIM_CheckIsSameOperand, /*MI*/3, /*OpIdx*/1, /*OtherMI*/1, /*OtherOpIdx*/1,
        // MIs[3] VOP3Mods:src1:src1_mods
        GIM_CheckIsSameOperand, /*MI*/3, /*OpIdx*/2, /*OtherMI*/1, /*OtherOpIdx*/2,
        GIM_CheckCxxInsnPredicate, /*MI*/0, /*FnId*/GIMT_Encode2(GICXXPred_MI_Predicate_fminnum_like_nnan),
        GIM_CheckIsSafeToFold, /*InsnID*/1,
        GIM_CheckIsSafeToFold, /*InsnID*/2,
        GIM_CheckIsSafeToFold, /*InsnID*/3,
        GIM_CheckComplexPattern, /*MI*/1, /*Op*/1, /*Renderer*/GIMT_Encode2(0), GIMT_Encode2(GICP_gi_vop3mods),
        GIM_CheckComplexPattern, /*MI*/1, /*Op*/2, /*Renderer*/GIMT_Encode2(1), GIMT_Encode2(GICP_gi_vop3mods),
        GIM_CheckComplexPattern, /*MI*/2, /*Op*/2, /*Renderer*/GIMT_Encode2(2), GIMT_Encode2(GICP_gi_vop3mods),
        // (fminnum:{ *:[f32] } (fmaxnum:{ *:[f32] } (VOP3Mods:{ *:[f32] } f32:{ *:[f32] }:$src0, i32:{ *:[i32] }:$src0_mods), (VOP3Mods:{ *:[f32] } f32:{ *:[f32] }:$src1, i32:{ *:[i32] }:$src1_mods)), (fmaxnum:{ *:[f32] } (fminnum:{ *:[f32] } (VOP3Mods:{ *:[f32] } f32:{ *:[f32] }:$src0, i32:{ *:[i32] }:$src0_mods), (VOP3Mods:{ *:[f32] } f32:{ *:[f32] }:$src1, i32:{ *:[i32] }:$src1_mods)), (VOP3Mods:{ *:[f32] } f32:{ *:[f32] }:$src2, i32:{ *:[i32] }:$src2_mods)))<<P:Predicate_fminnum_like_nnan>>  =>  (V_MED3_F32_e64:{ *:[f32] } ?:{ *:[i32] }:$src0_mods, ?:{ *:[f32] }:$src0, ?:{ *:[i32] }:$src1_mods, ?:{ *:[f32] }:$src1, ?:{ *:[i32] }:$src2_mods, ?:{ *:[f32] }:$src2, 0:{ *:[i1] }, 0:{ *:[i32] })
        GIR_BuildMI, /*InsnID*/0, /*Opcode*/GIMT_Encode2(AMDGPU::V_MED3_F32_e64),
        GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/0, // DstI[vdst]
        GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/1, // src0_mods
        GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/0, // src0
        GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(1), /*SubOperand*/1, // src1_mods
        GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(1), /*SubOperand*/0, // src1
        GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(2), /*SubOperand*/1, // src2_mods
        GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(2), /*SubOperand*/0, // src2
        GIR_AddImm8, /*InsnID*/0, /*Imm*/0,
        GIR_AddImm8, /*InsnID*/0, /*Imm*/0,
        GIR_ConstrainSelectedInstOperands, /*InsnID*/0,
        GIR_EraseFromParent, /*InsnID*/0,
        // GIR_Coverage, 6513,
        GIR_Done,
      // Label 4333: @270467
      GIM_Try, /*On fail goto*//*Label 4334*/ GIMT_Encode4(270607), // Rule ID 10465 //
        GIM_CheckRegBankForClass, /*MI*/0, /*Op*/0, /*RC*/GIMT_Encode2(AMDGPU::VGPR_32RegClassID),
        GIM_RecordInsn, /*DefineMI*/1, /*MI*/0, /*OpIdx*/1, // MIs[1]
        GIM_CheckOpcode, /*MI*/1, GIMT_Encode2(TargetOpcode::G_FMAXNUM),
        GIM_CheckType, /*MI*/1, /*Op*/1, /*Type*/GILLT_s32,
        GIM_CheckType, /*MI*/1, /*Op*/2, /*Type*/GILLT_s32,
        GIM_RecordInsn, /*DefineMI*/2, /*MI*/0, /*OpIdx*/2, // MIs[2]
        GIM_CheckOpcode, /*MI*/2, GIMT_Encode2(TargetOpcode::G_FMAXNUM),
        GIM_CheckType, /*MI*/2, /*Op*/1, /*Type*/GILLT_s32,
        GIM_CheckType, /*MI*/2, /*Op*/2, /*Type*/GILLT_s32,
        GIM_RecordInsn, /*DefineMI*/3, /*MI*/2, /*OpIdx*/1, // MIs[3]
        GIM_CheckOpcode, /*MI*/3, GIMT_Encode2(TargetOpcode::G_FMINNUM),
        // MIs[3] VOP3Mods:src1:src1_mods
        GIM_CheckIsSameOperand, /*MI*/3, /*OpIdx*/1, /*OtherMI*/1, /*OtherOpIdx*/2,
        // MIs[3] VOP3Mods:src0:src0_mods
        GIM_CheckIsSameOperand, /*MI*/3, /*OpIdx*/2, /*OtherMI*/1, /*OtherOpIdx*/1,
        GIM_CheckCxxInsnPredicate, /*MI*/0, /*FnId*/GIMT_Encode2(GICXXPred_MI_Predicate_fminnum_like_nnan),
        GIM_CheckIsSafeToFold, /*InsnID*/1,
        GIM_CheckIsSafeToFold, /*InsnID*/2,
        GIM_CheckIsSafeToFold, /*InsnID*/3,
        GIM_CheckComplexPattern, /*MI*/1, /*Op*/1, /*Renderer*/GIMT_Encode2(0), GIMT_Encode2(GICP_gi_vop3mods),
        GIM_CheckComplexPattern, /*MI*/1, /*Op*/2, /*Renderer*/GIMT_Encode2(1), GIMT_Encode2(GICP_gi_vop3mods),
        GIM_CheckComplexPattern, /*MI*/2, /*Op*/2, /*Renderer*/GIMT_Encode2(2), GIMT_Encode2(GICP_gi_vop3mods),
        // (fminnum:{ *:[f32] } (fmaxnum:{ *:[f32] } (VOP3Mods:{ *:[f32] } f32:{ *:[f32] }:$src0, i32:{ *:[i32] }:$src0_mods), (VOP3Mods:{ *:[f32] } f32:{ *:[f32] }:$src1, i32:{ *:[i32] }:$src1_mods)), (fmaxnum:{ *:[f32] } (fminnum:{ *:[f32] } (VOP3Mods:{ *:[f32] } f32:{ *:[f32] }:$src1, i32:{ *:[i32] }:$src1_mods), (VOP3Mods:{ *:[f32] } f32:{ *:[f32] }:$src0, i32:{ *:[i32] }:$src0_mods)), (VOP3Mods:{ *:[f32] } f32:{ *:[f32] }:$src2, i32:{ *:[i32] }:$src2_mods)))<<P:Predicate_fminnum_like_nnan>>  =>  (V_MED3_F32_e64:{ *:[f32] } ?:{ *:[i32] }:$src0_mods, ?:{ *:[f32] }:$src0, ?:{ *:[i32] }:$src1_mods, ?:{ *:[f32] }:$src1, ?:{ *:[i32] }:$src2_mods, ?:{ *:[f32] }:$src2, 0:{ *:[i1] }, 0:{ *:[i32] })
        GIR_BuildMI, /*InsnID*/0, /*Opcode*/GIMT_Encode2(AMDGPU::V_MED3_F32_e64),
        GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/0, // DstI[vdst]
        GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/1, // src0_mods
        GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/0, // src0
        GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(1), /*SubOperand*/1, // src1_mods
        GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(1), /*SubOperand*/0, // src1
        GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(2), /*SubOperand*/1, // src2_mods
        GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(2), /*SubOperand*/0, // src2
        GIR_AddImm8, /*InsnID*/0, /*Imm*/0,
        GIR_AddImm8, /*InsnID*/0, /*Imm*/0,
        GIR_ConstrainSelectedInstOperands, /*InsnID*/0,
        GIR_EraseFromParent, /*InsnID*/0,
        // GIR_Coverage, 10465,
        GIR_Done,
      // Label 4334: @270607
      GIM_Try, /*On fail goto*//*Label 4335*/ GIMT_Encode4(270747), // Rule ID 10468 //
        GIM_CheckRegBankForClass, /*MI*/0, /*Op*/0, /*RC*/GIMT_Encode2(AMDGPU::VGPR_32RegClassID),
        GIM_RecordInsn, /*DefineMI*/1, /*MI*/0, /*OpIdx*/1, // MIs[1]
        GIM_CheckOpcode, /*MI*/1, GIMT_Encode2(TargetOpcode::G_FMAXNUM),
        GIM_CheckType, /*MI*/1, /*Op*/1, /*Type*/GILLT_s32,
        GIM_CheckType, /*MI*/1, /*Op*/2, /*Type*/GILLT_s32,
        GIM_RecordInsn, /*DefineMI*/2, /*MI*/0, /*OpIdx*/2, // MIs[2]
        GIM_CheckOpcode, /*MI*/2, GIMT_Encode2(TargetOpcode::G_FMAXNUM),
        GIM_CheckType, /*MI*/2, /*Op*/1, /*Type*/GILLT_s32,
        GIM_CheckType, /*MI*/2, /*Op*/2, /*Type*/GILLT_s32,
        GIM_RecordInsn, /*DefineMI*/3, /*MI*/2, /*OpIdx*/1, // MIs[3]
        GIM_CheckOpcode, /*MI*/3, GIMT_Encode2(TargetOpcode::G_FMINNUM),
        // MIs[3] VOP3Mods:src0:src0_mods
        GIM_CheckIsSameOperand, /*MI*/3, /*OpIdx*/1, /*OtherMI*/1, /*OtherOpIdx*/2,
        // MIs[3] VOP3Mods:src1:src1_mods
        GIM_CheckIsSameOperand, /*MI*/3, /*OpIdx*/2, /*OtherMI*/1, /*OtherOpIdx*/1,
        GIM_CheckCxxInsnPredicate, /*MI*/0, /*FnId*/GIMT_Encode2(GICXXPred_MI_Predicate_fminnum_like_nnan),
        GIM_CheckIsSafeToFold, /*InsnID*/1,
        GIM_CheckIsSafeToFold, /*InsnID*/2,
        GIM_CheckIsSafeToFold, /*InsnID*/3,
        GIM_CheckComplexPattern, /*MI*/1, /*Op*/1, /*Renderer*/GIMT_Encode2(0), GIMT_Encode2(GICP_gi_vop3mods),
        GIM_CheckComplexPattern, /*MI*/1, /*Op*/2, /*Renderer*/GIMT_Encode2(1), GIMT_Encode2(GICP_gi_vop3mods),
        GIM_CheckComplexPattern, /*MI*/2, /*Op*/2, /*Renderer*/GIMT_Encode2(2), GIMT_Encode2(GICP_gi_vop3mods),
        // (fminnum:{ *:[f32] } (fmaxnum:{ *:[f32] } (VOP3Mods:{ *:[f32] } f32:{ *:[f32] }:$src1, i32:{ *:[i32] }:$src1_mods), (VOP3Mods:{ *:[f32] } f32:{ *:[f32] }:$src0, i32:{ *:[i32] }:$src0_mods)), (fmaxnum:{ *:[f32] } (fminnum:{ *:[f32] } (VOP3Mods:{ *:[f32] } f32:{ *:[f32] }:$src0, i32:{ *:[i32] }:$src0_mods), (VOP3Mods:{ *:[f32] } f32:{ *:[f32] }:$src1, i32:{ *:[i32] }:$src1_mods)), (VOP3Mods:{ *:[f32] } f32:{ *:[f32] }:$src2, i32:{ *:[i32] }:$src2_mods)))<<P:Predicate_fminnum_like_nnan>>  =>  (V_MED3_F32_e64:{ *:[f32] } ?:{ *:[i32] }:$src0_mods, ?:{ *:[f32] }:$src0, ?:{ *:[i32] }:$src1_mods, ?:{ *:[f32] }:$src1, ?:{ *:[i32] }:$src2_mods, ?:{ *:[f32] }:$src2, 0:{ *:[i1] }, 0:{ *:[i32] })
        GIR_BuildMI, /*InsnID*/0, /*Opcode*/GIMT_Encode2(AMDGPU::V_MED3_F32_e64),
        GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/0, // DstI[vdst]
        GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(1), /*SubOperand*/1, // src0_mods
        GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(1), /*SubOperand*/0, // src0
        GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/1, // src1_mods
        GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/0, // src1
        GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(2), /*SubOperand*/1, // src2_mods
        GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(2), /*SubOperand*/0, // src2
        GIR_AddImm8, /*InsnID*/0, /*Imm*/0,
        GIR_AddImm8, /*InsnID*/0, /*Imm*/0,
        GIR_ConstrainSelectedInstOperands, /*InsnID*/0,
        GIR_EraseFromParent, /*InsnID*/0,
        // GIR_Coverage, 10468,
        GIR_Done,
      // Label 4335: @270747
      GIM_Try, /*On fail goto*//*Label 4336*/ GIMT_Encode4(270887), // Rule ID 10469 //
        GIM_CheckRegBankForClass, /*MI*/0, /*Op*/0, /*RC*/GIMT_Encode2(AMDGPU::VGPR_32RegClassID),
        GIM_RecordInsn, /*DefineMI*/1, /*MI*/0, /*OpIdx*/1, // MIs[1]
        GIM_CheckOpcode, /*MI*/1, GIMT_Encode2(TargetOpcode::G_FMAXNUM),
        GIM_CheckType, /*MI*/1, /*Op*/1, /*Type*/GILLT_s32,
        GIM_CheckType, /*MI*/1, /*Op*/2, /*Type*/GILLT_s32,
        GIM_RecordInsn, /*DefineMI*/2, /*MI*/0, /*OpIdx*/2, // MIs[2]
        GIM_CheckOpcode, /*MI*/2, GIMT_Encode2(TargetOpcode::G_FMAXNUM),
        GIM_CheckType, /*MI*/2, /*Op*/1, /*Type*/GILLT_s32,
        GIM_CheckType, /*MI*/2, /*Op*/2, /*Type*/GILLT_s32,
        GIM_RecordInsn, /*DefineMI*/3, /*MI*/2, /*OpIdx*/1, // MIs[3]
        GIM_CheckOpcode, /*MI*/3, GIMT_Encode2(TargetOpcode::G_FMINNUM),
        // MIs[3] VOP3Mods:src1:src1_mods
        GIM_CheckIsSameOperand, /*MI*/3, /*OpIdx*/1, /*OtherMI*/1, /*OtherOpIdx*/1,
        // MIs[3] VOP3Mods:src0:src0_mods
        GIM_CheckIsSameOperand, /*MI*/3, /*OpIdx*/2, /*OtherMI*/1, /*OtherOpIdx*/2,
        GIM_CheckCxxInsnPredicate, /*MI*/0, /*FnId*/GIMT_Encode2(GICXXPred_MI_Predicate_fminnum_like_nnan),
        GIM_CheckIsSafeToFold, /*InsnID*/1,
        GIM_CheckIsSafeToFold, /*InsnID*/2,
        GIM_CheckIsSafeToFold, /*InsnID*/3,
        GIM_CheckComplexPattern, /*MI*/1, /*Op*/1, /*Renderer*/GIMT_Encode2(0), GIMT_Encode2(GICP_gi_vop3mods),
        GIM_CheckComplexPattern, /*MI*/1, /*Op*/2, /*Renderer*/GIMT_Encode2(1), GIMT_Encode2(GICP_gi_vop3mods),
        GIM_CheckComplexPattern, /*MI*/2, /*Op*/2, /*Renderer*/GIMT_Encode2(2), GIMT_Encode2(GICP_gi_vop3mods),
        // (fminnum:{ *:[f32] } (fmaxnum:{ *:[f32] } (VOP3Mods:{ *:[f32] } f32:{ *:[f32] }:$src1, i32:{ *:[i32] }:$src1_mods), (VOP3Mods:{ *:[f32] } f32:{ *:[f32] }:$src0, i32:{ *:[i32] }:$src0_mods)), (fmaxnum:{ *:[f32] } (fminnum:{ *:[f32] } (VOP3Mods:{ *:[f32] } f32:{ *:[f32] }:$src1, i32:{ *:[i32] }:$src1_mods), (VOP3Mods:{ *:[f32] } f32:{ *:[f32] }:$src0, i32:{ *:[i32] }:$src0_mods)), (VOP3Mods:{ *:[f32] } f32:{ *:[f32] }:$src2, i32:{ *:[i32] }:$src2_mods)))<<P:Predicate_fminnum_like_nnan>>  =>  (V_MED3_F32_e64:{ *:[f32] } ?:{ *:[i32] }:$src0_mods, ?:{ *:[f32] }:$src0, ?:{ *:[i32] }:$src1_mods, ?:{ *:[f32] }:$src1, ?:{ *:[i32] }:$src2_mods, ?:{ *:[f32] }:$src2, 0:{ *:[i1] }, 0:{ *:[i32] })
        GIR_BuildMI, /*InsnID*/0, /*Opcode*/GIMT_Encode2(AMDGPU::V_MED3_F32_e64),
        GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/0, // DstI[vdst]
        GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(1), /*SubOperand*/1, // src0_mods
        GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(1), /*SubOperand*/0, // src0
        GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/1, // src1_mods
        GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/0, // src1
        GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(2), /*SubOperand*/1, // src2_mods
        GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(2), /*SubOperand*/0, // src2
        GIR_AddImm8, /*InsnID*/0, /*Imm*/0,
        GIR_AddImm8, /*InsnID*/0, /*Imm*/0,
        GIR_ConstrainSelectedInstOperands, /*InsnID*/0,
        GIR_EraseFromParent, /*InsnID*/0,
        // GIR_Coverage, 10469,
        GIR_Done,
      // Label 4336: @270887
      GIM_Try, /*On fail goto*//*Label 4337*/ GIMT_Encode4(271027), // Rule ID 6512 //
        GIM_CheckRegBankForClass, /*MI*/0, /*Op*/0, /*RC*/GIMT_Encode2(AMDGPU::VGPR_32RegClassID),
        GIM_RecordInsn, /*DefineMI*/1, /*MI*/0, /*OpIdx*/1, // MIs[1]
        GIM_CheckOpcode, /*MI*/1, GIMT_Encode2(TargetOpcode::G_FMAXNUM),
        GIM_CheckType, /*MI*/1, /*Op*/1, /*Type*/GILLT_s32,
        GIM_CheckType, /*MI*/1, /*Op*/2, /*Type*/GILLT_s32,
        GIM_RecordInsn, /*DefineMI*/2, /*MI*/0, /*OpIdx*/2, // MIs[2]
        GIM_CheckOpcode, /*MI*/2, GIMT_Encode2(TargetOpcode::G_FMAXNUM),
        GIM_CheckType, /*MI*/2, /*Op*/1, /*Type*/GILLT_s32,
        GIM_CheckType, /*MI*/2, /*Op*/2, /*Type*/GILLT_s32,
        GIM_RecordInsn, /*DefineMI*/3, /*MI*/2, /*OpIdx*/1, // MIs[3]
        GIM_CheckOpcode, /*MI*/3, GIMT_Encode2(TargetOpcode::G_FMINNUM_IEEE),
        // MIs[3] VOP3Mods:src0:src0_mods
        GIM_CheckIsSameOperand, /*MI*/3, /*OpIdx*/1, /*OtherMI*/1, /*OtherOpIdx*/1,
        // MIs[3] VOP3Mods:src1:src1_mods
        GIM_CheckIsSameOperand, /*MI*/3, /*OpIdx*/2, /*OtherMI*/1, /*OtherOpIdx*/2,
        GIM_CheckCxxInsnPredicate, /*MI*/0, /*FnId*/GIMT_Encode2(GICXXPred_MI_Predicate_fminnum_like_nnan),
        GIM_CheckIsSafeToFold, /*InsnID*/1,
        GIM_CheckIsSafeToFold, /*InsnID*/2,
        GIM_CheckIsSafeToFold, /*InsnID*/3,
        GIM_CheckComplexPattern, /*MI*/1, /*Op*/1, /*Renderer*/GIMT_Encode2(0), GIMT_Encode2(GICP_gi_vop3mods),
        GIM_CheckComplexPattern, /*MI*/1, /*Op*/2, /*Renderer*/GIMT_Encode2(1), GIMT_Encode2(GICP_gi_vop3mods),
        GIM_CheckComplexPattern, /*MI*/2, /*Op*/2, /*Renderer*/GIMT_Encode2(2), GIMT_Encode2(GICP_gi_vop3mods),
        // (fminnum:{ *:[f32] } (fmaxnum:{ *:[f32] } (VOP3Mods:{ *:[f32] } f32:{ *:[f32] }:$src0, i32:{ *:[i32] }:$src0_mods), (VOP3Mods:{ *:[f32] } f32:{ *:[f32] }:$src1, i32:{ *:[i32] }:$src1_mods)), (fmaxnum:{ *:[f32] } (fminnum_ieee:{ *:[f32] } (VOP3Mods:{ *:[f32] } f32:{ *:[f32] }:$src0, i32:{ *:[i32] }:$src0_mods), (VOP3Mods:{ *:[f32] } f32:{ *:[f32] }:$src1, i32:{ *:[i32] }:$src1_mods)), (VOP3Mods:{ *:[f32] } f32:{ *:[f32] }:$src2, i32:{ *:[i32] }:$src2_mods)))<<P:Predicate_fminnum_like_nnan>>  =>  (V_MED3_F32_e64:{ *:[f32] } ?:{ *:[i32] }:$src0_mods, ?:{ *:[f32] }:$src0, ?:{ *:[i32] }:$src1_mods, ?:{ *:[f32] }:$src1, ?:{ *:[i32] }:$src2_mods, ?:{ *:[f32] }:$src2, 0:{ *:[i1] }, 0:{ *:[i32] })
        GIR_BuildMI, /*InsnID*/0, /*Opcode*/GIMT_Encode2(AMDGPU::V_MED3_F32_e64),
        GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/0, // DstI[vdst]
        GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/1, // src0_mods
        GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/0, // src0
        GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(1), /*SubOperand*/1, // src1_mods
        GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(1), /*SubOperand*/0, // src1
        GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(2), /*SubOperand*/1, // src2_mods
        GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(2), /*SubOperand*/0, // src2
        GIR_AddImm8, /*InsnID*/0, /*Imm*/0,
        GIR_AddImm8, /*InsnID*/0, /*Imm*/0,
        GIR_ConstrainSelectedInstOperands, /*InsnID*/0,
        GIR_EraseFromParent, /*InsnID*/0,
        // GIR_Coverage, 6512,
        GIR_Done,
      // Label 4337: @271027
      GIM_Try, /*On fail goto*//*Label 4338*/ GIMT_Encode4(271167), // Rule ID 10450 //
        GIM_CheckRegBankForClass, /*MI*/0, /*Op*/0, /*RC*/GIMT_Encode2(AMDGPU::VGPR_32RegClassID),
        GIM_RecordInsn, /*DefineMI*/1, /*MI*/0, /*OpIdx*/1, // MIs[1]
        GIM_CheckOpcode, /*MI*/1, GIMT_Encode2(TargetOpcode::G_FMAXNUM),
        GIM_CheckType, /*MI*/1, /*Op*/1, /*Type*/GILLT_s32,
        GIM_CheckType, /*MI*/1, /*Op*/2, /*Type*/GILLT_s32,
        GIM_RecordInsn, /*DefineMI*/2, /*MI*/0, /*OpIdx*/2, // MIs[2]
        GIM_CheckOpcode, /*MI*/2, GIMT_Encode2(TargetOpcode::G_FMAXNUM),
        GIM_CheckType, /*MI*/2, /*Op*/1, /*Type*/GILLT_s32,
        GIM_CheckType, /*MI*/2, /*Op*/2, /*Type*/GILLT_s32,
        GIM_RecordInsn, /*DefineMI*/3, /*MI*/2, /*OpIdx*/1, // MIs[3]
        GIM_CheckOpcode, /*MI*/3, GIMT_Encode2(TargetOpcode::G_FMINNUM_IEEE),
        // MIs[3] VOP3Mods:src1:src1_mods
        GIM_CheckIsSameOperand, /*MI*/3, /*OpIdx*/1, /*OtherMI*/1, /*OtherOpIdx*/2,
        // MIs[3] VOP3Mods:src0:src0_mods
        GIM_CheckIsSameOperand, /*MI*/3, /*OpIdx*/2, /*OtherMI*/1, /*OtherOpIdx*/1,
        GIM_CheckCxxInsnPredicate, /*MI*/0, /*FnId*/GIMT_Encode2(GICXXPred_MI_Predicate_fminnum_like_nnan),
        GIM_CheckIsSafeToFold, /*InsnID*/1,
        GIM_CheckIsSafeToFold, /*InsnID*/2,
        GIM_CheckIsSafeToFold, /*InsnID*/3,
        GIM_CheckComplexPattern, /*MI*/1, /*Op*/1, /*Renderer*/GIMT_Encode2(0), GIMT_Encode2(GICP_gi_vop3mods),
        GIM_CheckComplexPattern, /*MI*/1, /*Op*/2, /*Renderer*/GIMT_Encode2(1), GIMT_Encode2(GICP_gi_vop3mods),
        GIM_CheckComplexPattern, /*MI*/2, /*Op*/2, /*Renderer*/GIMT_Encode2(2), GIMT_Encode2(GICP_gi_vop3mods),
        // (fminnum:{ *:[f32] } (fmaxnum:{ *:[f32] } (VOP3Mods:{ *:[f32] } f32:{ *:[f32] }:$src0, i32:{ *:[i32] }:$src0_mods), (VOP3Mods:{ *:[f32] } f32:{ *:[f32] }:$src1, i32:{ *:[i32] }:$src1_mods)), (fmaxnum:{ *:[f32] } (fminnum_ieee:{ *:[f32] } (VOP3Mods:{ *:[f32] } f32:{ *:[f32] }:$src1, i32:{ *:[i32] }:$src1_mods), (VOP3Mods:{ *:[f32] } f32:{ *:[f32] }:$src0, i32:{ *:[i32] }:$src0_mods)), (VOP3Mods:{ *:[f32] } f32:{ *:[f32] }:$src2, i32:{ *:[i32] }:$src2_mods)))<<P:Predicate_fminnum_like_nnan>>  =>  (V_MED3_F32_e64:{ *:[f32] } ?:{ *:[i32] }:$src0_mods, ?:{ *:[f32] }:$src0, ?:{ *:[i32] }:$src1_mods, ?:{ *:[f32] }:$src1, ?:{ *:[i32] }:$src2_mods, ?:{ *:[f32] }:$src2, 0:{ *:[i1] }, 0:{ *:[i32] })
        GIR_BuildMI, /*InsnID*/0, /*Opcode*/GIMT_Encode2(AMDGPU::V_MED3_F32_e64),
        GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/0, // DstI[vdst]
        GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/1, // src0_mods
        GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/0, // src0
        GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(1), /*SubOperand*/1, // src1_mods
        GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(1), /*SubOperand*/0, // src1
        GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(2), /*SubOperand*/1, // src2_mods
        GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(2), /*SubOperand*/0, // src2
        GIR_AddImm8, /*InsnID*/0, /*Imm*/0,
        GIR_AddImm8, /*InsnID*/0, /*Imm*/0,
        GIR_ConstrainSelectedInstOperands, /*InsnID*/0,
        GIR_EraseFromParent, /*InsnID*/0,
        // GIR_Coverage, 10450,
        GIR_Done,
      // Label 4338: @271167
      GIM_Try, /*On fail goto*//*Label 4339*/ GIMT_Encode4(271307), // Rule ID 10453 //
        GIM_CheckRegBankForClass, /*MI*/0, /*Op*/0, /*RC*/GIMT_Encode2(AMDGPU::VGPR_32RegClassID),
        GIM_RecordInsn, /*DefineMI*/1, /*MI*/0, /*OpIdx*/1, // MIs[1]
        GIM_CheckOpcode, /*MI*/1, GIMT_Encode2(TargetOpcode::G_FMAXNUM),
        GIM_CheckType, /*MI*/1, /*Op*/1, /*Type*/GILLT_s32,
        GIM_CheckType, /*MI*/1, /*Op*/2, /*Type*/GILLT_s32,
        GIM_RecordInsn, /*DefineMI*/2, /*MI*/0, /*OpIdx*/2, // MIs[2]
        GIM_CheckOpcode, /*MI*/2, GIMT_Encode2(TargetOpcode::G_FMAXNUM),
        GIM_CheckType, /*MI*/2, /*Op*/1, /*Type*/GILLT_s32,
        GIM_CheckType, /*MI*/2, /*Op*/2, /*Type*/GILLT_s32,
        GIM_RecordInsn, /*DefineMI*/3, /*MI*/2, /*OpIdx*/1, // MIs[3]
        GIM_CheckOpcode, /*MI*/3, GIMT_Encode2(TargetOpcode::G_FMINNUM_IEEE),
        // MIs[3] VOP3Mods:src0:src0_mods
        GIM_CheckIsSameOperand, /*MI*/3, /*OpIdx*/1, /*OtherMI*/1, /*OtherOpIdx*/2,
        // MIs[3] VOP3Mods:src1:src1_mods
        GIM_CheckIsSameOperand, /*MI*/3, /*OpIdx*/2, /*OtherMI*/1, /*OtherOpIdx*/1,
        GIM_CheckCxxInsnPredicate, /*MI*/0, /*FnId*/GIMT_Encode2(GICXXPred_MI_Predicate_fminnum_like_nnan),
        GIM_CheckIsSafeToFold, /*InsnID*/1,
        GIM_CheckIsSafeToFold, /*InsnID*/2,
        GIM_CheckIsSafeToFold, /*InsnID*/3,
        GIM_CheckComplexPattern, /*MI*/1, /*Op*/1, /*Renderer*/GIMT_Encode2(0), GIMT_Encode2(GICP_gi_vop3mods),
        GIM_CheckComplexPattern, /*MI*/1, /*Op*/2, /*Renderer*/GIMT_Encode2(1), GIMT_Encode2(GICP_gi_vop3mods),
        GIM_CheckComplexPattern, /*MI*/2, /*Op*/2, /*Renderer*/GIMT_Encode2(2), GIMT_Encode2(GICP_gi_vop3mods),
        // (fminnum:{ *:[f32] } (fmaxnum:{ *:[f32] } (VOP3Mods:{ *:[f32] } f32:{ *:[f32] }:$src1, i32:{ *:[i32] }:$src1_mods), (VOP3Mods:{ *:[f32] } f32:{ *:[f32] }:$src0, i32:{ *:[i32] }:$src0_mods)), (fmaxnum:{ *:[f32] } (fminnum_ieee:{ *:[f32] } (VOP3Mods:{ *:[f32] } f32:{ *:[f32] }:$src0, i32:{ *:[i32] }:$src0_mods), (VOP3Mods:{ *:[f32] } f32:{ *:[f32] }:$src1, i32:{ *:[i32] }:$src1_mods)), (VOP3Mods:{ *:[f32] } f32:{ *:[f32] }:$src2, i32:{ *:[i32] }:$src2_mods)))<<P:Predicate_fminnum_like_nnan>>  =>  (V_MED3_F32_e64:{ *:[f32] } ?:{ *:[i32] }:$src0_mods, ?:{ *:[f32] }:$src0, ?:{ *:[i32] }:$src1_mods, ?:{ *:[f32] }:$src1, ?:{ *:[i32] }:$src2_mods, ?:{ *:[f32] }:$src2, 0:{ *:[i1] }, 0:{ *:[i32] })
        GIR_BuildMI, /*InsnID*/0, /*Opcode*/GIMT_Encode2(AMDGPU::V_MED3_F32_e64),
        GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/0, // DstI[vdst]
        GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(1), /*SubOperand*/1, // src0_mods
        GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(1), /*SubOperand*/0, // src0
        GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/1, // src1_mods
        GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/0, // src1
        GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(2), /*SubOperand*/1, // src2_mods
        GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(2), /*SubOperand*/0, // src2
        GIR_AddImm8, /*InsnID*/0, /*Imm*/0,
        GIR_AddImm8, /*InsnID*/0, /*Imm*/0,
        GIR_ConstrainSelectedInstOperands, /*InsnID*/0,
        GIR_EraseFromParent, /*InsnID*/0,
        // GIR_Coverage, 10453,
        GIR_Done,
      // Label 4339: @271307
      GIM_Try, /*On fail goto*//*Label 4340*/ GIMT_Encode4(271447), // Rule ID 10454 //
        GIM_CheckRegBankForClass, /*MI*/0, /*Op*/0, /*RC*/GIMT_Encode2(AMDGPU::VGPR_32RegClassID),
        GIM_RecordInsn, /*DefineMI*/1, /*MI*/0, /*OpIdx*/1, // MIs[1]
        GIM_CheckOpcode, /*MI*/1, GIMT_Encode2(TargetOpcode::G_FMAXNUM),
        GIM_CheckType, /*MI*/1, /*Op*/1, /*Type*/GILLT_s32,
        GIM_CheckType, /*MI*/1, /*Op*/2, /*Type*/GILLT_s32,
        GIM_RecordInsn, /*DefineMI*/2, /*MI*/0, /*OpIdx*/2, // MIs[2]
        GIM_CheckOpcode, /*MI*/2, GIMT_Encode2(TargetOpcode::G_FMAXNUM),
        GIM_CheckType, /*MI*/2, /*Op*/1, /*Type*/GILLT_s32,
        GIM_CheckType, /*MI*/2, /*Op*/2, /*Type*/GILLT_s32,
        GIM_RecordInsn, /*DefineMI*/3, /*MI*/2, /*OpIdx*/1, // MIs[3]
        GIM_CheckOpcode, /*MI*/3, GIMT_Encode2(TargetOpcode::G_FMINNUM_IEEE),
        // MIs[3] VOP3Mods:src1:src1_mods
        GIM_CheckIsSameOperand, /*MI*/3, /*OpIdx*/1, /*OtherMI*/1, /*OtherOpIdx*/1,
        // MIs[3] VOP3Mods:src0:src0_mods
        GIM_CheckIsSameOperand, /*MI*/3, /*OpIdx*/2, /*OtherMI*/1, /*OtherOpIdx*/2,
        GIM_CheckCxxInsnPredicate, /*MI*/0, /*FnId*/GIMT_Encode2(GICXXPred_MI_Predicate_fminnum_like_nnan),
        GIM_CheckIsSafeToFold, /*InsnID*/1,
        GIM_CheckIsSafeToFold, /*InsnID*/2,
        GIM_CheckIsSafeToFold, /*InsnID*/3,
        GIM_CheckComplexPattern, /*MI*/1, /*Op*/1, /*Renderer*/GIMT_Encode2(0), GIMT_Encode2(GICP_gi_vop3mods),
        GIM_CheckComplexPattern, /*MI*/1, /*Op*/2, /*Renderer*/GIMT_Encode2(1), GIMT_Encode2(GICP_gi_vop3mods),
        GIM_CheckComplexPattern, /*MI*/2, /*Op*/2, /*Renderer*/GIMT_Encode2(2), GIMT_Encode2(GICP_gi_vop3mods),
        // (fminnum:{ *:[f32] } (fmaxnum:{ *:[f32] } (VOP3Mods:{ *:[f32] } f32:{ *:[f32] }:$src1, i32:{ *:[i32] }:$src1_mods), (VOP3Mods:{ *:[f32] } f32:{ *:[f32] }:$src0, i32:{ *:[i32] }:$src0_mods)), (fmaxnum:{ *:[f32] } (fminnum_ieee:{ *:[f32] } (VOP3Mods:{ *:[f32] } f32:{ *:[f32] }:$src1, i32:{ *:[i32] }:$src1_mods), (VOP3Mods:{ *:[f32] } f32:{ *:[f32] }:$src0, i32:{ *:[i32] }:$src0_mods)), (VOP3Mods:{ *:[f32] } f32:{ *:[f32] }:$src2, i32:{ *:[i32] }:$src2_mods)))<<P:Predicate_fminnum_like_nnan>>  =>  (V_MED3_F32_e64:{ *:[f32] } ?:{ *:[i32] }:$src0_mods, ?:{ *:[f32] }:$src0, ?:{ *:[i32] }:$src1_mods, ?:{ *:[f32] }:$src1, ?:{ *:[i32] }:$src2_mods, ?:{ *:[f32] }:$src2, 0:{ *:[i1] }, 0:{ *:[i32] })
        GIR_BuildMI, /*InsnID*/0, /*Opcode*/GIMT_Encode2(AMDGPU::V_MED3_F32_e64),
        GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/0, // DstI[vdst]
        GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(1), /*SubOperand*/1, // src0_mods
        GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(1), /*SubOperand*/0, // src0
        GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/1, // src1_mods
        GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/0, // src1
        GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(2), /*SubOperand*/1, // src2_mods
        GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(2), /*SubOperand*/0, // src2
        GIR_AddImm8, /*InsnID*/0, /*Imm*/0,
        GIR_AddImm8, /*InsnID*/0, /*Imm*/0,
        GIR_ConstrainSelectedInstOperands, /*InsnID*/0,
        GIR_EraseFromParent, /*InsnID*/0,
        // GIR_Coverage, 10454,
        GIR_Done,
      // Label 4340: @271447
      GIM_Try, /*On fail goto*//*Label 4341*/ GIMT_Encode4(271587), // Rule ID 10436 //
        GIM_CheckRegBankForClass, /*MI*/0, /*Op*/0, /*RC*/GIMT_Encode2(AMDGPU::VGPR_32RegClassID),
        GIM_RecordInsn, /*DefineMI*/1, /*MI*/0, /*OpIdx*/1, // MIs[1]
        GIM_CheckOpcode, /*MI*/1, GIMT_Encode2(TargetOpcode::G_FMAXNUM),
        GIM_CheckType, /*MI*/1, /*Op*/1, /*Type*/GILLT_s32,
        GIM_CheckType, /*MI*/1, /*Op*/2, /*Type*/GILLT_s32,
        GIM_RecordInsn, /*DefineMI*/2, /*MI*/0, /*OpIdx*/2, // MIs[2]
        GIM_CheckOpcode, /*MI*/2, GIMT_Encode2(TargetOpcode::G_FMAXNUM_IEEE),
        GIM_CheckType, /*MI*/2, /*Op*/1, /*Type*/GILLT_s32,
        GIM_CheckType, /*MI*/2, /*Op*/2, /*Type*/GILLT_s32,
        GIM_RecordInsn, /*DefineMI*/3, /*MI*/2, /*OpIdx*/2, // MIs[3]
        GIM_CheckOpcode, /*MI*/3, GIMT_Encode2(TargetOpcode::G_FMINNUM),
        // MIs[3] VOP3Mods:src0:src0_mods
        GIM_CheckIsSameOperand, /*MI*/3, /*OpIdx*/1, /*OtherMI*/1, /*OtherOpIdx*/1,
        // MIs[3] VOP3Mods:src1:src1_mods
        GIM_CheckIsSameOperand, /*MI*/3, /*OpIdx*/2, /*OtherMI*/1, /*OtherOpIdx*/2,
        GIM_CheckCxxInsnPredicate, /*MI*/0, /*FnId*/GIMT_Encode2(GICXXPred_MI_Predicate_fminnum_like_nnan),
        GIM_CheckIsSafeToFold, /*InsnID*/1,
        GIM_CheckIsSafeToFold, /*InsnID*/2,
        GIM_CheckIsSafeToFold, /*InsnID*/3,
        GIM_CheckComplexPattern, /*MI*/1, /*Op*/1, /*Renderer*/GIMT_Encode2(0), GIMT_Encode2(GICP_gi_vop3mods),
        GIM_CheckComplexPattern, /*MI*/1, /*Op*/2, /*Renderer*/GIMT_Encode2(1), GIMT_Encode2(GICP_gi_vop3mods),
        GIM_CheckComplexPattern, /*MI*/2, /*Op*/1, /*Renderer*/GIMT_Encode2(2), GIMT_Encode2(GICP_gi_vop3mods),
        // (fminnum:{ *:[f32] } (fmaxnum:{ *:[f32] } (VOP3Mods:{ *:[f32] } f32:{ *:[f32] }:$src0, i32:{ *:[i32] }:$src0_mods), (VOP3Mods:{ *:[f32] } f32:{ *:[f32] }:$src1, i32:{ *:[i32] }:$src1_mods)), (fmaxnum_ieee:{ *:[f32] } (VOP3Mods:{ *:[f32] } f32:{ *:[f32] }:$src2, i32:{ *:[i32] }:$src2_mods), (fminnum:{ *:[f32] } (VOP3Mods:{ *:[f32] } f32:{ *:[f32] }:$src0, i32:{ *:[i32] }:$src0_mods), (VOP3Mods:{ *:[f32] } f32:{ *:[f32] }:$src1, i32:{ *:[i32] }:$src1_mods))))<<P:Predicate_fminnum_like_nnan>>  =>  (V_MED3_F32_e64:{ *:[f32] } ?:{ *:[i32] }:$src0_mods, ?:{ *:[f32] }:$src0, ?:{ *:[i32] }:$src1_mods, ?:{ *:[f32] }:$src1, ?:{ *:[i32] }:$src2_mods, ?:{ *:[f32] }:$src2, 0:{ *:[i1] }, 0:{ *:[i32] })
        GIR_BuildMI, /*InsnID*/0, /*Opcode*/GIMT_Encode2(AMDGPU::V_MED3_F32_e64),
        GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/0, // DstI[vdst]
        GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/1, // src0_mods
        GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/0, // src0
        GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(1), /*SubOperand*/1, // src1_mods
        GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(1), /*SubOperand*/0, // src1
        GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(2), /*SubOperand*/1, // src2_mods
        GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(2), /*SubOperand*/0, // src2
        GIR_AddImm8, /*InsnID*/0, /*Imm*/0,
        GIR_AddImm8, /*InsnID*/0, /*Imm*/0,
        GIR_ConstrainSelectedInstOperands, /*InsnID*/0,
        GIR_EraseFromParent, /*InsnID*/0,
        // GIR_Coverage, 10436,
        GIR_Done,
      // Label 4341: @271587
      GIM_Try, /*On fail goto*//*Label 4342*/ GIMT_Encode4(271727), // Rule ID 10437 //
        GIM_CheckRegBankForClass, /*MI*/0, /*Op*/0, /*RC*/GIMT_Encode2(AMDGPU::VGPR_32RegClassID),
        GIM_RecordInsn, /*DefineMI*/1, /*MI*/0, /*OpIdx*/1, // MIs[1]
        GIM_CheckOpcode, /*MI*/1, GIMT_Encode2(TargetOpcode::G_FMAXNUM),
        GIM_CheckType, /*MI*/1, /*Op*/1, /*Type*/GILLT_s32,
        GIM_CheckType, /*MI*/1, /*Op*/2, /*Type*/GILLT_s32,
        GIM_RecordInsn, /*DefineMI*/2, /*MI*/0, /*OpIdx*/2, // MIs[2]
        GIM_CheckOpcode, /*MI*/2, GIMT_Encode2(TargetOpcode::G_FMAXNUM_IEEE),
        GIM_CheckType, /*MI*/2, /*Op*/1, /*Type*/GILLT_s32,
        GIM_CheckType, /*MI*/2, /*Op*/2, /*Type*/GILLT_s32,
        GIM_RecordInsn, /*DefineMI*/3, /*MI*/2, /*OpIdx*/2, // MIs[3]
        GIM_CheckOpcode, /*MI*/3, GIMT_Encode2(TargetOpcode::G_FMINNUM),
        // MIs[3] VOP3Mods:src1:src1_mods
        GIM_CheckIsSameOperand, /*MI*/3, /*OpIdx*/1, /*OtherMI*/1, /*OtherOpIdx*/2,
        // MIs[3] VOP3Mods:src0:src0_mods
        GIM_CheckIsSameOperand, /*MI*/3, /*OpIdx*/2, /*OtherMI*/1, /*OtherOpIdx*/1,
        GIM_CheckCxxInsnPredicate, /*MI*/0, /*FnId*/GIMT_Encode2(GICXXPred_MI_Predicate_fminnum_like_nnan),
        GIM_CheckIsSafeToFold, /*InsnID*/1,
        GIM_CheckIsSafeToFold, /*InsnID*/2,
        GIM_CheckIsSafeToFold, /*InsnID*/3,
        GIM_CheckComplexPattern, /*MI*/1, /*Op*/1, /*Renderer*/GIMT_Encode2(0), GIMT_Encode2(GICP_gi_vop3mods),
        GIM_CheckComplexPattern, /*MI*/1, /*Op*/2, /*Renderer*/GIMT_Encode2(1), GIMT_Encode2(GICP_gi_vop3mods),
        GIM_CheckComplexPattern, /*MI*/2, /*Op*/1, /*Renderer*/GIMT_Encode2(2), GIMT_Encode2(GICP_gi_vop3mods),
        // (fminnum:{ *:[f32] } (fmaxnum:{ *:[f32] } (VOP3Mods:{ *:[f32] } f32:{ *:[f32] }:$src0, i32:{ *:[i32] }:$src0_mods), (VOP3Mods:{ *:[f32] } f32:{ *:[f32] }:$src1, i32:{ *:[i32] }:$src1_mods)), (fmaxnum_ieee:{ *:[f32] } (VOP3Mods:{ *:[f32] } f32:{ *:[f32] }:$src2, i32:{ *:[i32] }:$src2_mods), (fminnum:{ *:[f32] } (VOP3Mods:{ *:[f32] } f32:{ *:[f32] }:$src1, i32:{ *:[i32] }:$src1_mods), (VOP3Mods:{ *:[f32] } f32:{ *:[f32] }:$src0, i32:{ *:[i32] }:$src0_mods))))<<P:Predicate_fminnum_like_nnan>>  =>  (V_MED3_F32_e64:{ *:[f32] } ?:{ *:[i32] }:$src0_mods, ?:{ *:[f32] }:$src0, ?:{ *:[i32] }:$src1_mods, ?:{ *:[f32] }:$src1, ?:{ *:[i32] }:$src2_mods, ?:{ *:[f32] }:$src2, 0:{ *:[i1] }, 0:{ *:[i32] })
        GIR_BuildMI, /*InsnID*/0, /*Opcode*/GIMT_Encode2(AMDGPU::V_MED3_F32_e64),
        GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/0, // DstI[vdst]
        GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/1, // src0_mods
        GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/0, // src0
        GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(1), /*SubOperand*/1, // src1_mods
        GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(1), /*SubOperand*/0, // src1
        GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(2), /*SubOperand*/1, // src2_mods
        GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(2), /*SubOperand*/0, // src2
        GIR_AddImm8, /*InsnID*/0, /*Imm*/0,
        GIR_AddImm8, /*InsnID*/0, /*Imm*/0,
        GIR_ConstrainSelectedInstOperands, /*InsnID*/0,
        GIR_EraseFromParent, /*InsnID*/0,
        // GIR_Coverage, 10437,
        GIR_Done,
      // Label 4342: @271727
      GIM_Try, /*On fail goto*//*Label 4343*/ GIMT_Encode4(271867), // Rule ID 10440 //
        GIM_CheckRegBankForClass, /*MI*/0, /*Op*/0, /*RC*/GIMT_Encode2(AMDGPU::VGPR_32RegClassID),
        GIM_RecordInsn, /*DefineMI*/1, /*MI*/0, /*OpIdx*/1, // MIs[1]
        GIM_CheckOpcode, /*MI*/1, GIMT_Encode2(TargetOpcode::G_FMAXNUM),
        GIM_CheckType, /*MI*/1, /*Op*/1, /*Type*/GILLT_s32,
        GIM_CheckType, /*MI*/1, /*Op*/2, /*Type*/GILLT_s32,
        GIM_RecordInsn, /*DefineMI*/2, /*MI*/0, /*OpIdx*/2, // MIs[2]
        GIM_CheckOpcode, /*MI*/2, GIMT_Encode2(TargetOpcode::G_FMAXNUM_IEEE),
        GIM_CheckType, /*MI*/2, /*Op*/1, /*Type*/GILLT_s32,
        GIM_CheckType, /*MI*/2, /*Op*/2, /*Type*/GILLT_s32,
        GIM_RecordInsn, /*DefineMI*/3, /*MI*/2, /*OpIdx*/2, // MIs[3]
        GIM_CheckOpcode, /*MI*/3, GIMT_Encode2(TargetOpcode::G_FMINNUM),
        // MIs[3] VOP3Mods:src0:src0_mods
        GIM_CheckIsSameOperand, /*MI*/3, /*OpIdx*/1, /*OtherMI*/1, /*OtherOpIdx*/2,
        // MIs[3] VOP3Mods:src1:src1_mods
        GIM_CheckIsSameOperand, /*MI*/3, /*OpIdx*/2, /*OtherMI*/1, /*OtherOpIdx*/1,
        GIM_CheckCxxInsnPredicate, /*MI*/0, /*FnId*/GIMT_Encode2(GICXXPred_MI_Predicate_fminnum_like_nnan),
        GIM_CheckIsSafeToFold, /*InsnID*/1,
        GIM_CheckIsSafeToFold, /*InsnID*/2,
        GIM_CheckIsSafeToFold, /*InsnID*/3,
        GIM_CheckComplexPattern, /*MI*/1, /*Op*/1, /*Renderer*/GIMT_Encode2(0), GIMT_Encode2(GICP_gi_vop3mods),
        GIM_CheckComplexPattern, /*MI*/1, /*Op*/2, /*Renderer*/GIMT_Encode2(1), GIMT_Encode2(GICP_gi_vop3mods),
        GIM_CheckComplexPattern, /*MI*/2, /*Op*/1, /*Renderer*/GIMT_Encode2(2), GIMT_Encode2(GICP_gi_vop3mods),
        // (fminnum:{ *:[f32] } (fmaxnum:{ *:[f32] } (VOP3Mods:{ *:[f32] } f32:{ *:[f32] }:$src1, i32:{ *:[i32] }:$src1_mods), (VOP3Mods:{ *:[f32] } f32:{ *:[f32] }:$src0, i32:{ *:[i32] }:$src0_mods)), (fmaxnum_ieee:{ *:[f32] } (VOP3Mods:{ *:[f32] } f32:{ *:[f32] }:$src2, i32:{ *:[i32] }:$src2_mods), (fminnum:{ *:[f32] } (VOP3Mods:{ *:[f32] } f32:{ *:[f32] }:$src0, i32:{ *:[i32] }:$src0_mods), (VOP3Mods:{ *:[f32] } f32:{ *:[f32] }:$src1, i32:{ *:[i32] }:$src1_mods))))<<P:Predicate_fminnum_like_nnan>>  =>  (V_MED3_F32_e64:{ *:[f32] } ?:{ *:[i32] }:$src0_mods, ?:{ *:[f32] }:$src0, ?:{ *:[i32] }:$src1_mods, ?:{ *:[f32] }:$src1, ?:{ *:[i32] }:$src2_mods, ?:{ *:[f32] }:$src2, 0:{ *:[i1] }, 0:{ *:[i32] })
        GIR_BuildMI, /*InsnID*/0, /*Opcode*/GIMT_Encode2(AMDGPU::V_MED3_F32_e64),
        GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/0, // DstI[vdst]
        GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(1), /*SubOperand*/1, // src0_mods
        GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(1), /*SubOperand*/0, // src0
        GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/1, // src1_mods
        GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/0, // src1
        GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(2), /*SubOperand*/1, // src2_mods
        GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(2), /*SubOperand*/0, // src2
        GIR_AddImm8, /*InsnID*/0, /*Imm*/0,
        GIR_AddImm8, /*InsnID*/0, /*Imm*/0,
        GIR_ConstrainSelectedInstOperands, /*InsnID*/0,
        GIR_EraseFromParent, /*InsnID*/0,
        // GIR_Coverage, 10440,
        GIR_Done,
      // Label 4343: @271867
      GIM_Try, /*On fail goto*//*Label 4344*/ GIMT_Encode4(272007), // Rule ID 10441 //
        GIM_CheckRegBankForClass, /*MI*/0, /*Op*/0, /*RC*/GIMT_Encode2(AMDGPU::VGPR_32RegClassID),
        GIM_RecordInsn, /*DefineMI*/1, /*MI*/0, /*OpIdx*/1, // MIs[1]
        GIM_CheckOpcode, /*MI*/1, GIMT_Encode2(TargetOpcode::G_FMAXNUM),
        GIM_CheckType, /*MI*/1, /*Op*/1, /*Type*/GILLT_s32,
        GIM_CheckType, /*MI*/1, /*Op*/2, /*Type*/GILLT_s32,
        GIM_RecordInsn, /*DefineMI*/2, /*MI*/0, /*OpIdx*/2, // MIs[2]
        GIM_CheckOpcode, /*MI*/2, GIMT_Encode2(TargetOpcode::G_FMAXNUM_IEEE),
        GIM_CheckType, /*MI*/2, /*Op*/1, /*Type*/GILLT_s32,
        GIM_CheckType, /*MI*/2, /*Op*/2, /*Type*/GILLT_s32,
        GIM_RecordInsn, /*DefineMI*/3, /*MI*/2, /*OpIdx*/2, // MIs[3]
        GIM_CheckOpcode, /*MI*/3, GIMT_Encode2(TargetOpcode::G_FMINNUM),
        // MIs[3] VOP3Mods:src1:src1_mods
        GIM_CheckIsSameOperand, /*MI*/3, /*OpIdx*/1, /*OtherMI*/1, /*OtherOpIdx*/1,
        // MIs[3] VOP3Mods:src0:src0_mods
        GIM_CheckIsSameOperand, /*MI*/3, /*OpIdx*/2, /*OtherMI*/1, /*OtherOpIdx*/2,
        GIM_CheckCxxInsnPredicate, /*MI*/0, /*FnId*/GIMT_Encode2(GICXXPred_MI_Predicate_fminnum_like_nnan),
        GIM_CheckIsSafeToFold, /*InsnID*/1,
        GIM_CheckIsSafeToFold, /*InsnID*/2,
        GIM_CheckIsSafeToFold, /*InsnID*/3,
        GIM_CheckComplexPattern, /*MI*/1, /*Op*/1, /*Renderer*/GIMT_Encode2(0), GIMT_Encode2(GICP_gi_vop3mods),
        GIM_CheckComplexPattern, /*MI*/1, /*Op*/2, /*Renderer*/GIMT_Encode2(1), GIMT_Encode2(GICP_gi_vop3mods),
        GIM_CheckComplexPattern, /*MI*/2, /*Op*/1, /*Renderer*/GIMT_Encode2(2), GIMT_Encode2(GICP_gi_vop3mods),
        // (fminnum:{ *:[f32] } (fmaxnum:{ *:[f32] } (VOP3Mods:{ *:[f32] } f32:{ *:[f32] }:$src1, i32:{ *:[i32] }:$src1_mods), (VOP3Mods:{ *:[f32] } f32:{ *:[f32] }:$src0, i32:{ *:[i32] }:$src0_mods)), (fmaxnum_ieee:{ *:[f32] } (VOP3Mods:{ *:[f32] } f32:{ *:[f32] }:$src2, i32:{ *:[i32] }:$src2_mods), (fminnum:{ *:[f32] } (VOP3Mods:{ *:[f32] } f32:{ *:[f32] }:$src1, i32:{ *:[i32] }:$src1_mods), (VOP3Mods:{ *:[f32] } f32:{ *:[f32] }:$src0, i32:{ *:[i32] }:$src0_mods))))<<P:Predicate_fminnum_like_nnan>>  =>  (V_MED3_F32_e64:{ *:[f32] } ?:{ *:[i32] }:$src0_mods, ?:{ *:[f32] }:$src0, ?:{ *:[i32] }:$src1_mods, ?:{ *:[f32] }:$src1, ?:{ *:[i32] }:$src2_mods, ?:{ *:[f32] }:$src2, 0:{ *:[i1] }, 0:{ *:[i32] })
        GIR_BuildMI, /*InsnID*/0, /*Opcode*/GIMT_Encode2(AMDGPU::V_MED3_F32_e64),
        GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/0, // DstI[vdst]
        GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(1), /*SubOperand*/1, // src0_mods
        GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(1), /*SubOperand*/0, // src0
        GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/1, // src1_mods
        GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/0, // src1
        GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(2), /*SubOperand*/1, // src2_mods
        GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(2), /*SubOperand*/0, // src2
        GIR_AddImm8, /*InsnID*/0, /*Imm*/0,
        GIR_AddImm8, /*InsnID*/0, /*Imm*/0,
        GIR_ConstrainSelectedInstOperands, /*InsnID*/0,
        GIR_EraseFromParent, /*InsnID*/0,
        // GIR_Coverage, 10441,
        GIR_Done,
      // Label 4344: @272007
      GIM_Try, /*On fail goto*//*Label 4345*/ GIMT_Encode4(272147), // Rule ID 10421 //
        GIM_CheckRegBankForClass, /*MI*/0, /*Op*/0, /*RC*/GIMT_Encode2(AMDGPU::VGPR_32RegClassID),
        GIM_RecordInsn, /*DefineMI*/1, /*MI*/0, /*OpIdx*/1, // MIs[1]
        GIM_CheckOpcode, /*MI*/1, GIMT_Encode2(TargetOpcode::G_FMAXNUM),
        GIM_CheckType, /*MI*/1, /*Op*/1, /*Type*/GILLT_s32,
        GIM_CheckType, /*MI*/1, /*Op*/2, /*Type*/GILLT_s32,
        GIM_RecordInsn, /*DefineMI*/2, /*MI*/0, /*OpIdx*/2, // MIs[2]
        GIM_CheckOpcode, /*MI*/2, GIMT_Encode2(TargetOpcode::G_FMAXNUM_IEEE),
        GIM_CheckType, /*MI*/2, /*Op*/1, /*Type*/GILLT_s32,
        GIM_CheckType, /*MI*/2, /*Op*/2, /*Type*/GILLT_s32,
        GIM_RecordInsn, /*DefineMI*/3, /*MI*/2, /*OpIdx*/2, // MIs[3]
        GIM_CheckOpcode, /*MI*/3, GIMT_Encode2(TargetOpcode::G_FMINNUM_IEEE),
        // MIs[3] VOP3Mods:src0:src0_mods
        GIM_CheckIsSameOperand, /*MI*/3, /*OpIdx*/1, /*OtherMI*/1, /*OtherOpIdx*/1,
        // MIs[3] VOP3Mods:src1:src1_mods
        GIM_CheckIsSameOperand, /*MI*/3, /*OpIdx*/2, /*OtherMI*/1, /*OtherOpIdx*/2,
        GIM_CheckCxxInsnPredicate, /*MI*/0, /*FnId*/GIMT_Encode2(GICXXPred_MI_Predicate_fminnum_like_nnan),
        GIM_CheckIsSafeToFold, /*InsnID*/1,
        GIM_CheckIsSafeToFold, /*InsnID*/2,
        GIM_CheckIsSafeToFold, /*InsnID*/3,
        GIM_CheckComplexPattern, /*MI*/1, /*Op*/1, /*Renderer*/GIMT_Encode2(0), GIMT_Encode2(GICP_gi_vop3mods),
        GIM_CheckComplexPattern, /*MI*/1, /*Op*/2, /*Renderer*/GIMT_Encode2(1), GIMT_Encode2(GICP_gi_vop3mods),
        GIM_CheckComplexPattern, /*MI*/2, /*Op*/1, /*Renderer*/GIMT_Encode2(2), GIMT_Encode2(GICP_gi_vop3mods),
        // (fminnum:{ *:[f32] } (fmaxnum:{ *:[f32] } (VOP3Mods:{ *:[f32] } f32:{ *:[f32] }:$src0, i32:{ *:[i32] }:$src0_mods), (VOP3Mods:{ *:[f32] } f32:{ *:[f32] }:$src1, i32:{ *:[i32] }:$src1_mods)), (fmaxnum_ieee:{ *:[f32] } (VOP3Mods:{ *:[f32] } f32:{ *:[f32] }:$src2, i32:{ *:[i32] }:$src2_mods), (fminnum_ieee:{ *:[f32] } (VOP3Mods:{ *:[f32] } f32:{ *:[f32] }:$src0, i32:{ *:[i32] }:$src0_mods), (VOP3Mods:{ *:[f32] } f32:{ *:[f32] }:$src1, i32:{ *:[i32] }:$src1_mods))))<<P:Predicate_fminnum_like_nnan>>  =>  (V_MED3_F32_e64:{ *:[f32] } ?:{ *:[i32] }:$src0_mods, ?:{ *:[f32] }:$src0, ?:{ *:[i32] }:$src1_mods, ?:{ *:[f32] }:$src1, ?:{ *:[i32] }:$src2_mods, ?:{ *:[f32] }:$src2, 0:{ *:[i1] }, 0:{ *:[i32] })
        GIR_BuildMI, /*InsnID*/0, /*Opcode*/GIMT_Encode2(AMDGPU::V_MED3_F32_e64),
        GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/0, // DstI[vdst]
        GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/1, // src0_mods
        GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/0, // src0
        GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(1), /*SubOperand*/1, // src1_mods
        GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(1), /*SubOperand*/0, // src1
        GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(2), /*SubOperand*/1, // src2_mods
        GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(2), /*SubOperand*/0, // src2
        GIR_AddImm8, /*InsnID*/0, /*Imm*/0,
        GIR_AddImm8, /*InsnID*/0, /*Imm*/0,
        GIR_ConstrainSelectedInstOperands, /*InsnID*/0,
        GIR_EraseFromParent, /*InsnID*/0,
        // GIR_Coverage, 10421,
        GIR_Done,
      // Label 4345: @272147
      GIM_Try, /*On fail goto*//*Label 4346*/ GIMT_Encode4(272287), // Rule ID 10422 //
        GIM_CheckRegBankForClass, /*MI*/0, /*Op*/0, /*RC*/GIMT_Encode2(AMDGPU::VGPR_32RegClassID),
        GIM_RecordInsn, /*DefineMI*/1, /*MI*/0, /*OpIdx*/1, // MIs[1]
        GIM_CheckOpcode, /*MI*/1, GIMT_Encode2(TargetOpcode::G_FMAXNUM),
        GIM_CheckType, /*MI*/1, /*Op*/1, /*Type*/GILLT_s32,
        GIM_CheckType, /*MI*/1, /*Op*/2, /*Type*/GILLT_s32,
        GIM_RecordInsn, /*DefineMI*/2, /*MI*/0, /*OpIdx*/2, // MIs[2]
        GIM_CheckOpcode, /*MI*/2, GIMT_Encode2(TargetOpcode::G_FMAXNUM_IEEE),
        GIM_CheckType, /*MI*/2, /*Op*/1, /*Type*/GILLT_s32,
        GIM_CheckType, /*MI*/2, /*Op*/2, /*Type*/GILLT_s32,
        GIM_RecordInsn, /*DefineMI*/3, /*MI*/2, /*OpIdx*/2, // MIs[3]
        GIM_CheckOpcode, /*MI*/3, GIMT_Encode2(TargetOpcode::G_FMINNUM_IEEE),
        // MIs[3] VOP3Mods:src1:src1_mods
        GIM_CheckIsSameOperand, /*MI*/3, /*OpIdx*/1, /*OtherMI*/1, /*OtherOpIdx*/2,
        // MIs[3] VOP3Mods:src0:src0_mods
        GIM_CheckIsSameOperand, /*MI*/3, /*OpIdx*/2, /*OtherMI*/1, /*OtherOpIdx*/1,
        GIM_CheckCxxInsnPredicate, /*MI*/0, /*FnId*/GIMT_Encode2(GICXXPred_MI_Predicate_fminnum_like_nnan),
        GIM_CheckIsSafeToFold, /*InsnID*/1,
        GIM_CheckIsSafeToFold, /*InsnID*/2,
        GIM_CheckIsSafeToFold, /*InsnID*/3,
        GIM_CheckComplexPattern, /*MI*/1, /*Op*/1, /*Renderer*/GIMT_Encode2(0), GIMT_Encode2(GICP_gi_vop3mods),
        GIM_CheckComplexPattern, /*MI*/1, /*Op*/2, /*Renderer*/GIMT_Encode2(1), GIMT_Encode2(GICP_gi_vop3mods),
        GIM_CheckComplexPattern, /*MI*/2, /*Op*/1, /*Renderer*/GIMT_Encode2(2), GIMT_Encode2(GICP_gi_vop3mods),
        // (fminnum:{ *:[f32] } (fmaxnum:{ *:[f32] } (VOP3Mods:{ *:[f32] } f32:{ *:[f32] }:$src0, i32:{ *:[i32] }:$src0_mods), (VOP3Mods:{ *:[f32] } f32:{ *:[f32] }:$src1, i32:{ *:[i32] }:$src1_mods)), (fmaxnum_ieee:{ *:[f32] } (VOP3Mods:{ *:[f32] } f32:{ *:[f32] }:$src2, i32:{ *:[i32] }:$src2_mods), (fminnum_ieee:{ *:[f32] } (VOP3Mods:{ *:[f32] } f32:{ *:[f32] }:$src1, i32:{ *:[i32] }:$src1_mods), (VOP3Mods:{ *:[f32] } f32:{ *:[f32] }:$src0, i32:{ *:[i32] }:$src0_mods))))<<P:Predicate_fminnum_like_nnan>>  =>  (V_MED3_F32_e64:{ *:[f32] } ?:{ *:[i32] }:$src0_mods, ?:{ *:[f32] }:$src0, ?:{ *:[i32] }:$src1_mods, ?:{ *:[f32] }:$src1, ?:{ *:[i32] }:$src2_mods, ?:{ *:[f32] }:$src2, 0:{ *:[i1] }, 0:{ *:[i32] })
        GIR_BuildMI, /*InsnID*/0, /*Opcode*/GIMT_Encode2(AMDGPU::V_MED3_F32_e64),
        GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/0, // DstI[vdst]
        GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/1, // src0_mods
        GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/0, // src0
        GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(1), /*SubOperand*/1, // src1_mods
        GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(1), /*SubOperand*/0, // src1
        GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(2), /*SubOperand*/1, // src2_mods
        GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(2), /*SubOperand*/0, // src2
        GIR_AddImm8, /*InsnID*/0, /*Imm*/0,
        GIR_AddImm8, /*InsnID*/0, /*Imm*/0,
        GIR_ConstrainSelectedInstOperands, /*InsnID*/0,
        GIR_EraseFromParent, /*InsnID*/0,
        // GIR_Coverage, 10422,
        GIR_Done,
      // Label 4346: @272287
      GIM_Try, /*On fail goto*//*Label 4347*/ GIMT_Encode4(272427), // Rule ID 10425 //
        GIM_CheckRegBankForClass, /*MI*/0, /*Op*/0, /*RC*/GIMT_Encode2(AMDGPU::VGPR_32RegClassID),
        GIM_RecordInsn, /*DefineMI*/1, /*MI*/0, /*OpIdx*/1, // MIs[1]
        GIM_CheckOpcode, /*MI*/1, GIMT_Encode2(TargetOpcode::G_FMAXNUM),
        GIM_CheckType, /*MI*/1, /*Op*/1, /*Type*/GILLT_s32,
        GIM_CheckType, /*MI*/1, /*Op*/2, /*Type*/GILLT_s32,
        GIM_RecordInsn, /*DefineMI*/2, /*MI*/0, /*OpIdx*/2, // MIs[2]
        GIM_CheckOpcode, /*MI*/2, GIMT_Encode2(TargetOpcode::G_FMAXNUM_IEEE),
        GIM_CheckType, /*MI*/2, /*Op*/1, /*Type*/GILLT_s32,
        GIM_CheckType, /*MI*/2, /*Op*/2, /*Type*/GILLT_s32,
        GIM_RecordInsn, /*DefineMI*/3, /*MI*/2, /*OpIdx*/2, // MIs[3]
        GIM_CheckOpcode, /*MI*/3, GIMT_Encode2(TargetOpcode::G_FMINNUM_IEEE),
        // MIs[3] VOP3Mods:src0:src0_mods
        GIM_CheckIsSameOperand, /*MI*/3, /*OpIdx*/1, /*OtherMI*/1, /*OtherOpIdx*/2,
        // MIs[3] VOP3Mods:src1:src1_mods
        GIM_CheckIsSameOperand, /*MI*/3, /*OpIdx*/2, /*OtherMI*/1, /*OtherOpIdx*/1,
        GIM_CheckCxxInsnPredicate, /*MI*/0, /*FnId*/GIMT_Encode2(GICXXPred_MI_Predicate_fminnum_like_nnan),
        GIM_CheckIsSafeToFold, /*InsnID*/1,
        GIM_CheckIsSafeToFold, /*InsnID*/2,
        GIM_CheckIsSafeToFold, /*InsnID*/3,
        GIM_CheckComplexPattern, /*MI*/1, /*Op*/1, /*Renderer*/GIMT_Encode2(0), GIMT_Encode2(GICP_gi_vop3mods),
        GIM_CheckComplexPattern, /*MI*/1, /*Op*/2, /*Renderer*/GIMT_Encode2(1), GIMT_Encode2(GICP_gi_vop3mods),
        GIM_CheckComplexPattern, /*MI*/2, /*Op*/1, /*Renderer*/GIMT_Encode2(2), GIMT_Encode2(GICP_gi_vop3mods),
        // (fminnum:{ *:[f32] } (fmaxnum:{ *:[f32] } (VOP3Mods:{ *:[f32] } f32:{ *:[f32] }:$src1, i32:{ *:[i32] }:$src1_mods), (VOP3Mods:{ *:[f32] } f32:{ *:[f32] }:$src0, i32:{ *:[i32] }:$src0_mods)), (fmaxnum_ieee:{ *:[f32] } (VOP3Mods:{ *:[f32] } f32:{ *:[f32] }:$src2, i32:{ *:[i32] }:$src2_mods), (fminnum_ieee:{ *:[f32] } (VOP3Mods:{ *:[f32] } f32:{ *:[f32] }:$src0, i32:{ *:[i32] }:$src0_mods), (VOP3Mods:{ *:[f32] } f32:{ *:[f32] }:$src1, i32:{ *:[i32] }:$src1_mods))))<<P:Predicate_fminnum_like_nnan>>  =>  (V_MED3_F32_e64:{ *:[f32] } ?:{ *:[i32] }:$src0_mods, ?:{ *:[f32] }:$src0, ?:{ *:[i32] }:$src1_mods, ?:{ *:[f32] }:$src1, ?:{ *:[i32] }:$src2_mods, ?:{ *:[f32] }:$src2, 0:{ *:[i1] }, 0:{ *:[i32] })
        GIR_BuildMI, /*InsnID*/0, /*Opcode*/GIMT_Encode2(AMDGPU::V_MED3_F32_e64),
        GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/0, // DstI[vdst]
        GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(1), /*SubOperand*/1, // src0_mods
        GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(1), /*SubOperand*/0, // src0
        GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/1, // src1_mods
        GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/0, // src1
        GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(2), /*SubOperand*/1, // src2_mods
        GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(2), /*SubOperand*/0, // src2
        GIR_AddImm8, /*InsnID*/0, /*Imm*/0,
        GIR_AddImm8, /*InsnID*/0, /*Imm*/0,
        GIR_ConstrainSelectedInstOperands, /*InsnID*/0,
        GIR_EraseFromParent, /*InsnID*/0,
        // GIR_Coverage, 10425,
        GIR_Done,
      // Label 4347: @272427
      GIM_Try, /*On fail goto*//*Label 4348*/ GIMT_Encode4(272567), // Rule ID 10426 //
        GIM_CheckRegBankForClass, /*MI*/0, /*Op*/0, /*RC*/GIMT_Encode2(AMDGPU::VGPR_32RegClassID),
        GIM_RecordInsn, /*DefineMI*/1, /*MI*/0, /*OpIdx*/1, // MIs[1]
        GIM_CheckOpcode, /*MI*/1, GIMT_Encode2(TargetOpcode::G_FMAXNUM),
        GIM_CheckType, /*MI*/1, /*Op*/1, /*Type*/GILLT_s32,
        GIM_CheckType, /*MI*/1, /*Op*/2, /*Type*/GILLT_s32,
        GIM_RecordInsn, /*DefineMI*/2, /*MI*/0, /*OpIdx*/2, // MIs[2]
        GIM_CheckOpcode, /*MI*/2, GIMT_Encode2(TargetOpcode::G_FMAXNUM_IEEE),
        GIM_CheckType, /*MI*/2, /*Op*/1, /*Type*/GILLT_s32,
        GIM_CheckType, /*MI*/2, /*Op*/2, /*Type*/GILLT_s32,
        GIM_RecordInsn, /*DefineMI*/3, /*MI*/2, /*OpIdx*/2, // MIs[3]
        GIM_CheckOpcode, /*MI*/3, GIMT_Encode2(TargetOpcode::G_FMINNUM_IEEE),
        // MIs[3] VOP3Mods:src1:src1_mods
        GIM_CheckIsSameOperand, /*MI*/3, /*OpIdx*/1, /*OtherMI*/1, /*OtherOpIdx*/1,
        // MIs[3] VOP3Mods:src0:src0_mods
        GIM_CheckIsSameOperand, /*MI*/3, /*OpIdx*/2, /*OtherMI*/1, /*OtherOpIdx*/2,
        GIM_CheckCxxInsnPredicate, /*MI*/0, /*FnId*/GIMT_Encode2(GICXXPred_MI_Predicate_fminnum_like_nnan),
        GIM_CheckIsSafeToFold, /*InsnID*/1,
        GIM_CheckIsSafeToFold, /*InsnID*/2,
        GIM_CheckIsSafeToFold, /*InsnID*/3,
        GIM_CheckComplexPattern, /*MI*/1, /*Op*/1, /*Renderer*/GIMT_Encode2(0), GIMT_Encode2(GICP_gi_vop3mods),
        GIM_CheckComplexPattern, /*MI*/1, /*Op*/2, /*Renderer*/GIMT_Encode2(1), GIMT_Encode2(GICP_gi_vop3mods),
        GIM_CheckComplexPattern, /*MI*/2, /*Op*/1, /*Renderer*/GIMT_Encode2(2), GIMT_Encode2(GICP_gi_vop3mods),
        // (fminnum:{ *:[f32] } (fmaxnum:{ *:[f32] } (VOP3Mods:{ *:[f32] } f32:{ *:[f32] }:$src1, i32:{ *:[i32] }:$src1_mods), (VOP3Mods:{ *:[f32] } f32:{ *:[f32] }:$src0, i32:{ *:[i32] }:$src0_mods)), (fmaxnum_ieee:{ *:[f32] } (VOP3Mods:{ *:[f32] } f32:{ *:[f32] }:$src2, i32:{ *:[i32] }:$src2_mods), (fminnum_ieee:{ *:[f32] } (VOP3Mods:{ *:[f32] } f32:{ *:[f32] }:$src1, i32:{ *:[i32] }:$src1_mods), (VOP3Mods:{ *:[f32] } f32:{ *:[f32] }:$src0, i32:{ *:[i32] }:$src0_mods))))<<P:Predicate_fminnum_like_nnan>>  =>  (V_MED3_F32_e64:{ *:[f32] } ?:{ *:[i32] }:$src0_mods, ?:{ *:[f32] }:$src0, ?:{ *:[i32] }:$src1_mods, ?:{ *:[f32] }:$src1, ?:{ *:[i32] }:$src2_mods, ?:{ *:[f32] }:$src2, 0:{ *:[i1] }, 0:{ *:[i32] })
        GIR_BuildMI, /*InsnID*/0, /*Opcode*/GIMT_Encode2(AMDGPU::V_MED3_F32_e64),
        GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/0, // DstI[vdst]
        GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(1), /*SubOperand*/1, // src0_mods
        GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(1), /*SubOperand*/0, // src0
        GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/1, // src1_mods
        GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/0, // src1
        GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(2), /*SubOperand*/1, // src2_mods
        GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(2), /*SubOperand*/0, // src2
        GIR_AddImm8, /*InsnID*/0, /*Imm*/0,
        GIR_AddImm8, /*InsnID*/0, /*Imm*/0,
        GIR_ConstrainSelectedInstOperands, /*InsnID*/0,
        GIR_EraseFromParent, /*InsnID*/0,
        // GIR_Coverage, 10426,
        GIR_Done,
      // Label 4348: @272567
      GIM_Try, /*On fail goto*//*Label 4349*/ GIMT_Encode4(272707), // Rule ID 6511 //
        GIM_CheckRegBankForClass, /*MI*/0, /*Op*/0, /*RC*/GIMT_Encode2(AMDGPU::VGPR_32RegClassID),
        GIM_RecordInsn, /*DefineMI*/1, /*MI*/0, /*OpIdx*/1, // MIs[1]
        GIM_CheckOpcode, /*MI*/1, GIMT_Encode2(TargetOpcode::G_FMAXNUM),
        GIM_CheckType, /*MI*/1, /*Op*/1, /*Type*/GILLT_s32,
        GIM_CheckType, /*MI*/1, /*Op*/2, /*Type*/GILLT_s32,
        GIM_RecordInsn, /*DefineMI*/2, /*MI*/0, /*OpIdx*/2, // MIs[2]
        GIM_CheckOpcode, /*MI*/2, GIMT_Encode2(TargetOpcode::G_FMAXNUM_IEEE),
        GIM_CheckType, /*MI*/2, /*Op*/1, /*Type*/GILLT_s32,
        GIM_CheckType, /*MI*/2, /*Op*/2, /*Type*/GILLT_s32,
        GIM_RecordInsn, /*DefineMI*/3, /*MI*/2, /*OpIdx*/1, // MIs[3]
        GIM_CheckOpcode, /*MI*/3, GIMT_Encode2(TargetOpcode::G_FMINNUM),
        // MIs[3] VOP3Mods:src0:src0_mods
        GIM_CheckIsSameOperand, /*MI*/3, /*OpIdx*/1, /*OtherMI*/1, /*OtherOpIdx*/1,
        // MIs[3] VOP3Mods:src1:src1_mods
        GIM_CheckIsSameOperand, /*MI*/3, /*OpIdx*/2, /*OtherMI*/1, /*OtherOpIdx*/2,
        GIM_CheckCxxInsnPredicate, /*MI*/0, /*FnId*/GIMT_Encode2(GICXXPred_MI_Predicate_fminnum_like_nnan),
        GIM_CheckIsSafeToFold, /*InsnID*/1,
        GIM_CheckIsSafeToFold, /*InsnID*/2,
        GIM_CheckIsSafeToFold, /*InsnID*/3,
        GIM_CheckComplexPattern, /*MI*/1, /*Op*/1, /*Renderer*/GIMT_Encode2(0), GIMT_Encode2(GICP_gi_vop3mods),
        GIM_CheckComplexPattern, /*MI*/1, /*Op*/2, /*Renderer*/GIMT_Encode2(1), GIMT_Encode2(GICP_gi_vop3mods),
        GIM_CheckComplexPattern, /*MI*/2, /*Op*/2, /*Renderer*/GIMT_Encode2(2), GIMT_Encode2(GICP_gi_vop3mods),
        // (fminnum:{ *:[f32] } (fmaxnum:{ *:[f32] } (VOP3Mods:{ *:[f32] } f32:{ *:[f32] }:$src0, i32:{ *:[i32] }:$src0_mods), (VOP3Mods:{ *:[f32] } f32:{ *:[f32] }:$src1, i32:{ *:[i32] }:$src1_mods)), (fmaxnum_ieee:{ *:[f32] } (fminnum:{ *:[f32] } (VOP3Mods:{ *:[f32] } f32:{ *:[f32] }:$src0, i32:{ *:[i32] }:$src0_mods), (VOP3Mods:{ *:[f32] } f32:{ *:[f32] }:$src1, i32:{ *:[i32] }:$src1_mods)), (VOP3Mods:{ *:[f32] } f32:{ *:[f32] }:$src2, i32:{ *:[i32] }:$src2_mods)))<<P:Predicate_fminnum_like_nnan>>  =>  (V_MED3_F32_e64:{ *:[f32] } ?:{ *:[i32] }:$src0_mods, ?:{ *:[f32] }:$src0, ?:{ *:[i32] }:$src1_mods, ?:{ *:[f32] }:$src1, ?:{ *:[i32] }:$src2_mods, ?:{ *:[f32] }:$src2, 0:{ *:[i1] }, 0:{ *:[i32] })
        GIR_BuildMI, /*InsnID*/0, /*Opcode*/GIMT_Encode2(AMDGPU::V_MED3_F32_e64),
        GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/0, // DstI[vdst]
        GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/1, // src0_mods
        GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/0, // src0
        GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(1), /*SubOperand*/1, // src1_mods
        GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(1), /*SubOperand*/0, // src1
        GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(2), /*SubOperand*/1, // src2_mods
        GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(2), /*SubOperand*/0, // src2
        GIR_AddImm8, /*InsnID*/0, /*Imm*/0,
        GIR_AddImm8, /*InsnID*/0, /*Imm*/0,
        GIR_ConstrainSelectedInstOperands, /*InsnID*/0,
        GIR_EraseFromParent, /*InsnID*/0,
        // GIR_Coverage, 6511,
        GIR_Done,
      // Label 4349: @272707
      GIM_Try, /*On fail goto*//*Label 4350*/ GIMT_Encode4(272847), // Rule ID 10435 //
        GIM_CheckRegBankForClass, /*MI*/0, /*Op*/0, /*RC*/GIMT_Encode2(AMDGPU::VGPR_32RegClassID),
        GIM_RecordInsn, /*DefineMI*/1, /*MI*/0, /*OpIdx*/1, // MIs[1]
        GIM_CheckOpcode, /*MI*/1, GIMT_Encode2(TargetOpcode::G_FMAXNUM),
        GIM_CheckType, /*MI*/1, /*Op*/1, /*Type*/GILLT_s32,
        GIM_CheckType, /*MI*/1, /*Op*/2, /*Type*/GILLT_s32,
        GIM_RecordInsn, /*DefineMI*/2, /*MI*/0, /*OpIdx*/2, // MIs[2]
        GIM_CheckOpcode, /*MI*/2, GIMT_Encode2(TargetOpcode::G_FMAXNUM_IEEE),
        GIM_CheckType, /*MI*/2, /*Op*/1, /*Type*/GILLT_s32,
        GIM_CheckType, /*MI*/2, /*Op*/2, /*Type*/GILLT_s32,
        GIM_RecordInsn, /*DefineMI*/3, /*MI*/2, /*OpIdx*/1, // MIs[3]
        GIM_CheckOpcode, /*MI*/3, GIMT_Encode2(TargetOpcode::G_FMINNUM),
        // MIs[3] VOP3Mods:src1:src1_mods
        GIM_CheckIsSameOperand, /*MI*/3, /*OpIdx*/1, /*OtherMI*/1, /*OtherOpIdx*/2,
        // MIs[3] VOP3Mods:src0:src0_mods
        GIM_CheckIsSameOperand, /*MI*/3, /*OpIdx*/2, /*OtherMI*/1, /*OtherOpIdx*/1,
        GIM_CheckCxxInsnPredicate, /*MI*/0, /*FnId*/GIMT_Encode2(GICXXPred_MI_Predicate_fminnum_like_nnan),
        GIM_CheckIsSafeToFold, /*InsnID*/1,
        GIM_CheckIsSafeToFold, /*InsnID*/2,
        GIM_CheckIsSafeToFold, /*InsnID*/3,
        GIM_CheckComplexPattern, /*MI*/1, /*Op*/1, /*Renderer*/GIMT_Encode2(0), GIMT_Encode2(GICP_gi_vop3mods),
        GIM_CheckComplexPattern, /*MI*/1, /*Op*/2, /*Renderer*/GIMT_Encode2(1), GIMT_Encode2(GICP_gi_vop3mods),
        GIM_CheckComplexPattern, /*MI*/2, /*Op*/2, /*Renderer*/GIMT_Encode2(2), GIMT_Encode2(GICP_gi_vop3mods),
        // (fminnum:{ *:[f32] } (fmaxnum:{ *:[f32] } (VOP3Mods:{ *:[f32] } f32:{ *:[f32] }:$src0, i32:{ *:[i32] }:$src0_mods), (VOP3Mods:{ *:[f32] } f32:{ *:[f32] }:$src1, i32:{ *:[i32] }:$src1_mods)), (fmaxnum_ieee:{ *:[f32] } (fminnum:{ *:[f32] } (VOP3Mods:{ *:[f32] } f32:{ *:[f32] }:$src1, i32:{ *:[i32] }:$src1_mods), (VOP3Mods:{ *:[f32] } f32:{ *:[f32] }:$src0, i32:{ *:[i32] }:$src0_mods)), (VOP3Mods:{ *:[f32] } f32:{ *:[f32] }:$src2, i32:{ *:[i32] }:$src2_mods)))<<P:Predicate_fminnum_like_nnan>>  =>  (V_MED3_F32_e64:{ *:[f32] } ?:{ *:[i32] }:$src0_mods, ?:{ *:[f32] }:$src0, ?:{ *:[i32] }:$src1_mods, ?:{ *:[f32] }:$src1, ?:{ *:[i32] }:$src2_mods, ?:{ *:[f32] }:$src2, 0:{ *:[i1] }, 0:{ *:[i32] })
        GIR_BuildMI, /*InsnID*/0, /*Opcode*/GIMT_Encode2(AMDGPU::V_MED3_F32_e64),
        GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/0, // DstI[vdst]
        GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/1, // src0_mods
        GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/0, // src0
        GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(1), /*SubOperand*/1, // src1_mods
        GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(1), /*SubOperand*/0, // src1
        GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(2), /*SubOperand*/1, // src2_mods
        GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(2), /*SubOperand*/0, // src2
        GIR_AddImm8, /*InsnID*/0, /*Imm*/0,
        GIR_AddImm8, /*InsnID*/0, /*Imm*/0,
        GIR_ConstrainSelectedInstOperands, /*InsnID*/0,
        GIR_EraseFromParent, /*InsnID*/0,
        // GIR_Coverage, 10435,
        GIR_Done,
      // Label 4350: @272847
      GIM_Try, /*On fail goto*//*Label 4351*/ GIMT_Encode4(272987), // Rule ID 10438 //
        GIM_CheckRegBankForClass, /*MI*/0, /*Op*/0, /*RC*/GIMT_Encode2(AMDGPU::VGPR_32RegClassID),
        GIM_RecordInsn, /*DefineMI*/1, /*MI*/0, /*OpIdx*/1, // MIs[1]
        GIM_CheckOpcode, /*MI*/1, GIMT_Encode2(TargetOpcode::G_FMAXNUM),
        GIM_CheckType, /*MI*/1, /*Op*/1, /*Type*/GILLT_s32,
        GIM_CheckType, /*MI*/1, /*Op*/2, /*Type*/GILLT_s32,
        GIM_RecordInsn, /*DefineMI*/2, /*MI*/0, /*OpIdx*/2, // MIs[2]
        GIM_CheckOpcode, /*MI*/2, GIMT_Encode2(TargetOpcode::G_FMAXNUM_IEEE),
        GIM_CheckType, /*MI*/2, /*Op*/1, /*Type*/GILLT_s32,
        GIM_CheckType, /*MI*/2, /*Op*/2, /*Type*/GILLT_s32,
        GIM_RecordInsn, /*DefineMI*/3, /*MI*/2, /*OpIdx*/1, // MIs[3]
        GIM_CheckOpcode, /*MI*/3, GIMT_Encode2(TargetOpcode::G_FMINNUM),
        // MIs[3] VOP3Mods:src0:src0_mods
        GIM_CheckIsSameOperand, /*MI*/3, /*OpIdx*/1, /*OtherMI*/1, /*OtherOpIdx*/2,
        // MIs[3] VOP3Mods:src1:src1_mods
        GIM_CheckIsSameOperand, /*MI*/3, /*OpIdx*/2, /*OtherMI*/1, /*OtherOpIdx*/1,
        GIM_CheckCxxInsnPredicate, /*MI*/0, /*FnId*/GIMT_Encode2(GICXXPred_MI_Predicate_fminnum_like_nnan),
        GIM_CheckIsSafeToFold, /*InsnID*/1,
        GIM_CheckIsSafeToFold, /*InsnID*/2,
        GIM_CheckIsSafeToFold, /*InsnID*/3,
        GIM_CheckComplexPattern, /*MI*/1, /*Op*/1, /*Renderer*/GIMT_Encode2(0), GIMT_Encode2(GICP_gi_vop3mods),
        GIM_CheckComplexPattern, /*MI*/1, /*Op*/2, /*Renderer*/GIMT_Encode2(1), GIMT_Encode2(GICP_gi_vop3mods),
        GIM_CheckComplexPattern, /*MI*/2, /*Op*/2, /*Renderer*/GIMT_Encode2(2), GIMT_Encode2(GICP_gi_vop3mods),
        // (fminnum:{ *:[f32] } (fmaxnum:{ *:[f32] } (VOP3Mods:{ *:[f32] } f32:{ *:[f32] }:$src1, i32:{ *:[i32] }:$src1_mods), (VOP3Mods:{ *:[f32] } f32:{ *:[f32] }:$src0, i32:{ *:[i32] }:$src0_mods)), (fmaxnum_ieee:{ *:[f32] } (fminnum:{ *:[f32] } (VOP3Mods:{ *:[f32] } f32:{ *:[f32] }:$src0, i32:{ *:[i32] }:$src0_mods), (VOP3Mods:{ *:[f32] } f32:{ *:[f32] }:$src1, i32:{ *:[i32] }:$src1_mods)), (VOP3Mods:{ *:[f32] } f32:{ *:[f32] }:$src2, i32:{ *:[i32] }:$src2_mods)))<<P:Predicate_fminnum_like_nnan>>  =>  (V_MED3_F32_e64:{ *:[f32] } ?:{ *:[i32] }:$src0_mods, ?:{ *:[f32] }:$src0, ?:{ *:[i32] }:$src1_mods, ?:{ *:[f32] }:$src1, ?:{ *:[i32] }:$src2_mods, ?:{ *:[f32] }:$src2, 0:{ *:[i1] }, 0:{ *:[i32] })
        GIR_BuildMI, /*InsnID*/0, /*Opcode*/GIMT_Encode2(AMDGPU::V_MED3_F32_e64),
        GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/0, // DstI[vdst]
        GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(1), /*SubOperand*/1, // src0_mods
        GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(1), /*SubOperand*/0, // src0
        GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/1, // src1_mods
        GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/0, // src1
        GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(2), /*SubOperand*/1, // src2_mods
        GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(2), /*SubOperand*/0, // src2
        GIR_AddImm8, /*InsnID*/0, /*Imm*/0,
        GIR_AddImm8, /*InsnID*/0, /*Imm*/0,
        GIR_ConstrainSelectedInstOperands, /*InsnID*/0,
        GIR_EraseFromParent, /*InsnID*/0,
        // GIR_Coverage, 10438,
        GIR_Done,
      // Label 4351: @272987
      GIM_Try, /*On fail goto*//*Label 4352*/ GIMT_Encode4(273127), // Rule ID 10439 //
        GIM_CheckRegBankForClass, /*MI*/0, /*Op*/0, /*RC*/GIMT_Encode2(AMDGPU::VGPR_32RegClassID),
        GIM_RecordInsn, /*DefineMI*/1, /*MI*/0, /*OpIdx*/1, // MIs[1]
        GIM_CheckOpcode, /*MI*/1, GIMT_Encode2(TargetOpcode::G_FMAXNUM),
        GIM_CheckType, /*MI*/1, /*Op*/1, /*Type*/GILLT_s32,
        GIM_CheckType, /*MI*/1, /*Op*/2, /*Type*/GILLT_s32,
        GIM_RecordInsn, /*DefineMI*/2, /*MI*/0, /*OpIdx*/2, // MIs[2]
        GIM_CheckOpcode, /*MI*/2, GIMT_Encode2(TargetOpcode::G_FMAXNUM_IEEE),
        GIM_CheckType, /*MI*/2, /*Op*/1, /*Type*/GILLT_s32,
        GIM_CheckType, /*MI*/2, /*Op*/2, /*Type*/GILLT_s32,
        GIM_RecordInsn, /*DefineMI*/3, /*MI*/2, /*OpIdx*/1, // MIs[3]
        GIM_CheckOpcode, /*MI*/3, GIMT_Encode2(TargetOpcode::G_FMINNUM),
        // MIs[3] VOP3Mods:src1:src1_mods
        GIM_CheckIsSameOperand, /*MI*/3, /*OpIdx*/1, /*OtherMI*/1, /*OtherOpIdx*/1,
        // MIs[3] VOP3Mods:src0:src0_mods
        GIM_CheckIsSameOperand, /*MI*/3, /*OpIdx*/2, /*OtherMI*/1, /*OtherOpIdx*/2,
        GIM_CheckCxxInsnPredicate, /*MI*/0, /*FnId*/GIMT_Encode2(GICXXPred_MI_Predicate_fminnum_like_nnan),
        GIM_CheckIsSafeToFold, /*InsnID*/1,
        GIM_CheckIsSafeToFold, /*InsnID*/2,
        GIM_CheckIsSafeToFold, /*InsnID*/3,
        GIM_CheckComplexPattern, /*MI*/1, /*Op*/1, /*Renderer*/GIMT_Encode2(0), GIMT_Encode2(GICP_gi_vop3mods),
        GIM_CheckComplexPattern, /*MI*/1, /*Op*/2, /*Renderer*/GIMT_Encode2(1), GIMT_Encode2(GICP_gi_vop3mods),
        GIM_CheckComplexPattern, /*MI*/2, /*Op*/2, /*Renderer*/GIMT_Encode2(2), GIMT_Encode2(GICP_gi_vop3mods),
        // (fminnum:{ *:[f32] } (fmaxnum:{ *:[f32] } (VOP3Mods:{ *:[f32] } f32:{ *:[f32] }:$src1, i32:{ *:[i32] }:$src1_mods), (VOP3Mods:{ *:[f32] } f32:{ *:[f32] }:$src0, i32:{ *:[i32] }:$src0_mods)), (fmaxnum_ieee:{ *:[f32] } (fminnum:{ *:[f32] } (VOP3Mods:{ *:[f32] } f32:{ *:[f32] }:$src1, i32:{ *:[i32] }:$src1_mods), (VOP3Mods:{ *:[f32] } f32:{ *:[f32] }:$src0, i32:{ *:[i32] }:$src0_mods)), (VOP3Mods:{ *:[f32] } f32:{ *:[f32] }:$src2, i32:{ *:[i32] }:$src2_mods)))<<P:Predicate_fminnum_like_nnan>>  =>  (V_MED3_F32_e64:{ *:[f32] } ?:{ *:[i32] }:$src0_mods, ?:{ *:[f32] }:$src0, ?:{ *:[i32] }:$src1_mods, ?:{ *:[f32] }:$src1, ?:{ *:[i32] }:$src2_mods, ?:{ *:[f32] }:$src2, 0:{ *:[i1] }, 0:{ *:[i32] })
        GIR_BuildMI, /*InsnID*/0, /*Opcode*/GIMT_Encode2(AMDGPU::V_MED3_F32_e64),
        GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/0, // DstI[vdst]
        GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(1), /*SubOperand*/1, // src0_mods
        GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(1), /*SubOperand*/0, // src0
        GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/1, // src1_mods
        GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/0, // src1
        GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(2), /*SubOperand*/1, // src2_mods
        GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(2), /*SubOperand*/0, // src2
        GIR_AddImm8, /*InsnID*/0, /*Imm*/0,
        GIR_AddImm8, /*InsnID*/0, /*Imm*/0,
        GIR_ConstrainSelectedInstOperands, /*InsnID*/0,
        GIR_EraseFromParent, /*InsnID*/0,
        // GIR_Coverage, 10439,
        GIR_Done,
      // Label 4352: @273127
      GIM_Try, /*On fail goto*//*Label 4353*/ GIMT_Encode4(273267), // Rule ID 6510 //
        GIM_CheckRegBankForClass, /*MI*/0, /*Op*/0, /*RC*/GIMT_Encode2(AMDGPU::VGPR_32RegClassID),
        GIM_RecordInsn, /*DefineMI*/1, /*MI*/0, /*OpIdx*/1, // MIs[1]
        GIM_CheckOpcode, /*MI*/1, GIMT_Encode2(TargetOpcode::G_FMAXNUM),
        GIM_CheckType, /*MI*/1, /*Op*/1, /*Type*/GILLT_s32,
        GIM_CheckType, /*MI*/1, /*Op*/2, /*Type*/GILLT_s32,
        GIM_RecordInsn, /*DefineMI*/2, /*MI*/0, /*OpIdx*/2, // MIs[2]
        GIM_CheckOpcode, /*MI*/2, GIMT_Encode2(TargetOpcode::G_FMAXNUM_IEEE),
        GIM_CheckType, /*MI*/2, /*Op*/1, /*Type*/GILLT_s32,
        GIM_CheckType, /*MI*/2, /*Op*/2, /*Type*/GILLT_s32,
        GIM_RecordInsn, /*DefineMI*/3, /*MI*/2, /*OpIdx*/1, // MIs[3]
        GIM_CheckOpcode, /*MI*/3, GIMT_Encode2(TargetOpcode::G_FMINNUM_IEEE),
        // MIs[3] VOP3Mods:src0:src0_mods
        GIM_CheckIsSameOperand, /*MI*/3, /*OpIdx*/1, /*OtherMI*/1, /*OtherOpIdx*/1,
        // MIs[3] VOP3Mods:src1:src1_mods
        GIM_CheckIsSameOperand, /*MI*/3, /*OpIdx*/2, /*OtherMI*/1, /*OtherOpIdx*/2,
        GIM_CheckCxxInsnPredicate, /*MI*/0, /*FnId*/GIMT_Encode2(GICXXPred_MI_Predicate_fminnum_like_nnan),
        GIM_CheckIsSafeToFold, /*InsnID*/1,
        GIM_CheckIsSafeToFold, /*InsnID*/2,
        GIM_CheckIsSafeToFold, /*InsnID*/3,
        GIM_CheckComplexPattern, /*MI*/1, /*Op*/1, /*Renderer*/GIMT_Encode2(0), GIMT_Encode2(GICP_gi_vop3mods),
        GIM_CheckComplexPattern, /*MI*/1, /*Op*/2, /*Renderer*/GIMT_Encode2(1), GIMT_Encode2(GICP_gi_vop3mods),
        GIM_CheckComplexPattern, /*MI*/2, /*Op*/2, /*Renderer*/GIMT_Encode2(2), GIMT_Encode2(GICP_gi_vop3mods),
        // (fminnum:{ *:[f32] } (fmaxnum:{ *:[f32] } (VOP3Mods:{ *:[f32] } f32:{ *:[f32] }:$src0, i32:{ *:[i32] }:$src0_mods), (VOP3Mods:{ *:[f32] } f32:{ *:[f32] }:$src1, i32:{ *:[i32] }:$src1_mods)), (fmaxnum_ieee:{ *:[f32] } (fminnum_ieee:{ *:[f32] } (VOP3Mods:{ *:[f32] } f32:{ *:[f32] }:$src0, i32:{ *:[i32] }:$src0_mods), (VOP3Mods:{ *:[f32] } f32:{ *:[f32] }:$src1, i32:{ *:[i32] }:$src1_mods)), (VOP3Mods:{ *:[f32] } f32:{ *:[f32] }:$src2, i32:{ *:[i32] }:$src2_mods)))<<P:Predicate_fminnum_like_nnan>>  =>  (V_MED3_F32_e64:{ *:[f32] } ?:{ *:[i32] }:$src0_mods, ?:{ *:[f32] }:$src0, ?:{ *:[i32] }:$src1_mods, ?:{ *:[f32] }:$src1, ?:{ *:[i32] }:$src2_mods, ?:{ *:[f32] }:$src2, 0:{ *:[i1] }, 0:{ *:[i32] })
        GIR_BuildMI, /*InsnID*/0, /*Opcode*/GIMT_Encode2(AMDGPU::V_MED3_F32_e64),
        GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/0, // DstI[vdst]
        GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/1, // src0_mods
        GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/0, // src0
        GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(1), /*SubOperand*/1, // src1_mods
        GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(1), /*SubOperand*/0, // src1
        GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(2), /*SubOperand*/1, // src2_mods
        GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(2), /*SubOperand*/0, // src2
        GIR_AddImm8, /*InsnID*/0, /*Imm*/0,
        GIR_AddImm8, /*InsnID*/0, /*Imm*/0,
        GIR_ConstrainSelectedInstOperands, /*InsnID*/0,
        GIR_EraseFromParent, /*InsnID*/0,
        // GIR_Coverage, 6510,
        GIR_Done,
      // Label 4353: @273267
      GIM_Try, /*On fail goto*//*Label 4354*/ GIMT_Encode4(273407), // Rule ID 10420 //
        GIM_CheckRegBankForClass, /*MI*/0, /*Op*/0, /*RC*/GIMT_Encode2(AMDGPU::VGPR_32RegClassID),
        GIM_RecordInsn, /*DefineMI*/1, /*MI*/0, /*OpIdx*/1, // MIs[1]
        GIM_CheckOpcode, /*MI*/1, GIMT_Encode2(TargetOpcode::G_FMAXNUM),
        GIM_CheckType, /*MI*/1, /*Op*/1, /*Type*/GILLT_s32,
        GIM_CheckType, /*MI*/1, /*Op*/2, /*Type*/GILLT_s32,
        GIM_RecordInsn, /*DefineMI*/2, /*MI*/0, /*OpIdx*/2, // MIs[2]
        GIM_CheckOpcode, /*MI*/2, GIMT_Encode2(TargetOpcode::G_FMAXNUM_IEEE),
        GIM_CheckType, /*MI*/2, /*Op*/1, /*Type*/GILLT_s32,
        GIM_CheckType, /*MI*/2, /*Op*/2, /*Type*/GILLT_s32,
        GIM_RecordInsn, /*DefineMI*/3, /*MI*/2, /*OpIdx*/1, // MIs[3]
        GIM_CheckOpcode, /*MI*/3, GIMT_Encode2(TargetOpcode::G_FMINNUM_IEEE),
        // MIs[3] VOP3Mods:src1:src1_mods
        GIM_CheckIsSameOperand, /*MI*/3, /*OpIdx*/1, /*OtherMI*/1, /*OtherOpIdx*/2,
        // MIs[3] VOP3Mods:src0:src0_mods
        GIM_CheckIsSameOperand, /*MI*/3, /*OpIdx*/2, /*OtherMI*/1, /*OtherOpIdx*/1,
        GIM_CheckCxxInsnPredicate, /*MI*/0, /*FnId*/GIMT_Encode2(GICXXPred_MI_Predicate_fminnum_like_nnan),
        GIM_CheckIsSafeToFold, /*InsnID*/1,
        GIM_CheckIsSafeToFold, /*InsnID*/2,
        GIM_CheckIsSafeToFold, /*InsnID*/3,
        GIM_CheckComplexPattern, /*MI*/1, /*Op*/1, /*Renderer*/GIMT_Encode2(0), GIMT_Encode2(GICP_gi_vop3mods),
        GIM_CheckComplexPattern, /*MI*/1, /*Op*/2, /*Renderer*/GIMT_Encode2(1), GIMT_Encode2(GICP_gi_vop3mods),
        GIM_CheckComplexPattern, /*MI*/2, /*Op*/2, /*Renderer*/GIMT_Encode2(2), GIMT_Encode2(GICP_gi_vop3mods),
        // (fminnum:{ *:[f32] } (fmaxnum:{ *:[f32] } (VOP3Mods:{ *:[f32] } f32:{ *:[f32] }:$src0, i32:{ *:[i32] }:$src0_mods), (VOP3Mods:{ *:[f32] } f32:{ *:[f32] }:$src1, i32:{ *:[i32] }:$src1_mods)), (fmaxnum_ieee:{ *:[f32] } (fminnum_ieee:{ *:[f32] } (VOP3Mods:{ *:[f32] } f32:{ *:[f32] }:$src1, i32:{ *:[i32] }:$src1_mods), (VOP3Mods:{ *:[f32] } f32:{ *:[f32] }:$src0, i32:{ *:[i32] }:$src0_mods)), (VOP3Mods:{ *:[f32] } f32:{ *:[f32] }:$src2, i32:{ *:[i32] }:$src2_mods)))<<P:Predicate_fminnum_like_nnan>>  =>  (V_MED3_F32_e64:{ *:[f32] } ?:{ *:[i32] }:$src0_mods, ?:{ *:[f32] }:$src0, ?:{ *:[i32] }:$src1_mods, ?:{ *:[f32] }:$src1, ?:{ *:[i32] }:$src2_mods, ?:{ *:[f32] }:$src2, 0:{ *:[i1] }, 0:{ *:[i32] })
        GIR_BuildMI, /*InsnID*/0, /*Opcode*/GIMT_Encode2(AMDGPU::V_MED3_F32_e64),
        GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/0, // DstI[vdst]
        GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/1, // src0_mods
        GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/0, // src0
        GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(1), /*SubOperand*/1, // src1_mods
        GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(1), /*SubOperand*/0, // src1
        GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(2), /*SubOperand*/1, // src2_mods
        GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(2), /*SubOperand*/0, // src2
        GIR_AddImm8, /*InsnID*/0, /*Imm*/0,
        GIR_AddImm8, /*InsnID*/0, /*Imm*/0,
        GIR_ConstrainSelectedInstOperands, /*InsnID*/0,
        GIR_EraseFromParent, /*InsnID*/0,
        // GIR_Coverage, 10420,
        GIR_Done,
      // Label 4354: @273407
      GIM_Try, /*On fail goto*//*Label 4355*/ GIMT_Encode4(273547), // Rule ID 10423 //
        GIM_CheckRegBankForClass, /*MI*/0, /*Op*/0, /*RC*/GIMT_Encode2(AMDGPU::VGPR_32RegClassID),
        GIM_RecordInsn, /*DefineMI*/1, /*MI*/0, /*OpIdx*/1, // MIs[1]
        GIM_CheckOpcode, /*MI*/1, GIMT_Encode2(TargetOpcode::G_FMAXNUM),
        GIM_CheckType, /*MI*/1, /*Op*/1, /*Type*/GILLT_s32,
        GIM_CheckType, /*MI*/1, /*Op*/2, /*Type*/GILLT_s32,
        GIM_RecordInsn, /*DefineMI*/2, /*MI*/0, /*OpIdx*/2, // MIs[2]
        GIM_CheckOpcode, /*MI*/2, GIMT_Encode2(TargetOpcode::G_FMAXNUM_IEEE),
        GIM_CheckType, /*MI*/2, /*Op*/1, /*Type*/GILLT_s32,
        GIM_CheckType, /*MI*/2, /*Op*/2, /*Type*/GILLT_s32,
        GIM_RecordInsn, /*DefineMI*/3, /*MI*/2, /*OpIdx*/1, // MIs[3]
        GIM_CheckOpcode, /*MI*/3, GIMT_Encode2(TargetOpcode::G_FMINNUM_IEEE),
        // MIs[3] VOP3Mods:src0:src0_mods
        GIM_CheckIsSameOperand, /*MI*/3, /*OpIdx*/1, /*OtherMI*/1, /*OtherOpIdx*/2,
        // MIs[3] VOP3Mods:src1:src1_mods
        GIM_CheckIsSameOperand, /*MI*/3, /*OpIdx*/2, /*OtherMI*/1, /*OtherOpIdx*/1,
        GIM_CheckCxxInsnPredicate, /*MI*/0, /*FnId*/GIMT_Encode2(GICXXPred_MI_Predicate_fminnum_like_nnan),
        GIM_CheckIsSafeToFold, /*InsnID*/1,
        GIM_CheckIsSafeToFold, /*InsnID*/2,
        GIM_CheckIsSafeToFold, /*InsnID*/3,
        GIM_CheckComplexPattern, /*MI*/1, /*Op*/1, /*Renderer*/GIMT_Encode2(0), GIMT_Encode2(GICP_gi_vop3mods),
        GIM_CheckComplexPattern, /*MI*/1, /*Op*/2, /*Renderer*/GIMT_Encode2(1), GIMT_Encode2(GICP_gi_vop3mods),
        GIM_CheckComplexPattern, /*MI*/2, /*Op*/2, /*Renderer*/GIMT_Encode2(2), GIMT_Encode2(GICP_gi_vop3mods),
        // (fminnum:{ *:[f32] } (fmaxnum:{ *:[f32] } (VOP3Mods:{ *:[f32] } f32:{ *:[f32] }:$src1, i32:{ *:[i32] }:$src1_mods), (VOP3Mods:{ *:[f32] } f32:{ *:[f32] }:$src0, i32:{ *:[i32] }:$src0_mods)), (fmaxnum_ieee:{ *:[f32] } (fminnum_ieee:{ *:[f32] } (VOP3Mods:{ *:[f32] } f32:{ *:[f32] }:$src0, i32:{ *:[i32] }:$src0_mods), (VOP3Mods:{ *:[f32] } f32:{ *:[f32] }:$src1, i32:{ *:[i32] }:$src1_mods)), (VOP3Mods:{ *:[f32] } f32:{ *:[f32] }:$src2, i32:{ *:[i32] }:$src2_mods)))<<P:Predicate_fminnum_like_nnan>>  =>  (V_MED3_F32_e64:{ *:[f32] } ?:{ *:[i32] }:$src0_mods, ?:{ *:[f32] }:$src0, ?:{ *:[i32] }:$src1_mods, ?:{ *:[f32] }:$src1, ?:{ *:[i32] }:$src2_mods, ?:{ *:[f32] }:$src2, 0:{ *:[i1] }, 0:{ *:[i32] })
        GIR_BuildMI, /*InsnID*/0, /*Opcode*/GIMT_Encode2(AMDGPU::V_MED3_F32_e64),
        GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/0, // DstI[vdst]
        GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(1), /*SubOperand*/1, // src0_mods
        GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(1), /*SubOperand*/0, // src0
        GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/1, // src1_mods
        GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/0, // src1
        GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(2), /*SubOperand*/1, // src2_mods
        GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(2), /*SubOperand*/0, // src2
        GIR_AddImm8, /*InsnID*/0, /*Imm*/0,
        GIR_AddImm8, /*InsnID*/0, /*Imm*/0,
        GIR_ConstrainSelectedInstOperands, /*InsnID*/0,
        GIR_EraseFromParent, /*InsnID*/0,
        // GIR_Coverage, 10423,
        GIR_Done,
      // Label 4355: @273547
      GIM_Try, /*On fail goto*//*Label 4356*/ GIMT_Encode4(273687), // Rule ID 10424 //
        GIM_CheckRegBankForClass, /*MI*/0, /*Op*/0, /*RC*/GIMT_Encode2(AMDGPU::VGPR_32RegClassID),
        GIM_RecordInsn, /*DefineMI*/1, /*MI*/0, /*OpIdx*/1, // MIs[1]
        GIM_CheckOpcode, /*MI*/1, GIMT_Encode2(TargetOpcode::G_FMAXNUM),
        GIM_CheckType, /*MI*/1, /*Op*/1, /*Type*/GILLT_s32,
        GIM_CheckType, /*MI*/1, /*Op*/2, /*Type*/GILLT_s32,
        GIM_RecordInsn, /*DefineMI*/2, /*MI*/0, /*OpIdx*/2, // MIs[2]
        GIM_CheckOpcode, /*MI*/2, GIMT_Encode2(TargetOpcode::G_FMAXNUM_IEEE),
        GIM_CheckType, /*MI*/2, /*Op*/1, /*Type*/GILLT_s32,
        GIM_CheckType, /*MI*/2, /*Op*/2, /*Type*/GILLT_s32,
        GIM_RecordInsn, /*DefineMI*/3, /*MI*/2, /*OpIdx*/1, // MIs[3]
        GIM_CheckOpcode, /*MI*/3, GIMT_Encode2(TargetOpcode::G_FMINNUM_IEEE),
        // MIs[3] VOP3Mods:src1:src1_mods
        GIM_CheckIsSameOperand, /*MI*/3, /*OpIdx*/1, /*OtherMI*/1, /*OtherOpIdx*/1,
        // MIs[3] VOP3Mods:src0:src0_mods
        GIM_CheckIsSameOperand, /*MI*/3, /*OpIdx*/2, /*OtherMI*/1, /*OtherOpIdx*/2,
        GIM_CheckCxxInsnPredicate, /*MI*/0, /*FnId*/GIMT_Encode2(GICXXPred_MI_Predicate_fminnum_like_nnan),
        GIM_CheckIsSafeToFold, /*InsnID*/1,
        GIM_CheckIsSafeToFold, /*InsnID*/2,
        GIM_CheckIsSafeToFold, /*InsnID*/3,
        GIM_CheckComplexPattern, /*MI*/1, /*Op*/1, /*Renderer*/GIMT_Encode2(0), GIMT_Encode2(GICP_gi_vop3mods),
        GIM_CheckComplexPattern, /*MI*/1, /*Op*/2, /*Renderer*/GIMT_Encode2(1), GIMT_Encode2(GICP_gi_vop3mods),
        GIM_CheckComplexPattern, /*MI*/2, /*Op*/2, /*Renderer*/GIMT_Encode2(2), GIMT_Encode2(GICP_gi_vop3mods),
        // (fminnum:{ *:[f32] } (fmaxnum:{ *:[f32] } (VOP3Mods:{ *:[f32] } f32:{ *:[f32] }:$src1, i32:{ *:[i32] }:$src1_mods), (VOP3Mods:{ *:[f32] } f32:{ *:[f32] }:$src0, i32:{ *:[i32] }:$src0_mods)), (fmaxnum_ieee:{ *:[f32] } (fminnum_ieee:{ *:[f32] } (VOP3Mods:{ *:[f32] } f32:{ *:[f32] }:$src1, i32:{ *:[i32] }:$src1_mods), (VOP3Mods:{ *:[f32] } f32:{ *:[f32] }:$src0, i32:{ *:[i32] }:$src0_mods)), (VOP3Mods:{ *:[f32] } f32:{ *:[f32] }:$src2, i32:{ *:[i32] }:$src2_mods)))<<P:Predicate_fminnum_like_nnan>>  =>  (V_MED3_F32_e64:{ *:[f32] } ?:{ *:[i32] }:$src0_mods, ?:{ *:[f32] }:$src0, ?:{ *:[i32] }:$src1_mods, ?:{ *:[f32] }:$src1, ?:{ *:[i32] }:$src2_mods, ?:{ *:[f32] }:$src2, 0:{ *:[i1] }, 0:{ *:[i32] })
        GIR_BuildMI, /*InsnID*/0, /*Opcode*/GIMT_Encode2(AMDGPU::V_MED3_F32_e64),
        GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/0, // DstI[vdst]
        GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(1), /*SubOperand*/1, // src0_mods
        GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(1), /*SubOperand*/0, // src0
        GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/1, // src1_mods
        GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/0, // src1
        GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(2), /*SubOperand*/1, // src2_mods
        GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(2), /*SubOperand*/0, // src2
        GIR_AddImm8, /*InsnID*/0, /*Imm*/0,
        GIR_AddImm8, /*InsnID*/0, /*Imm*/0,
        GIR_ConstrainSelectedInstOperands, /*InsnID*/0,
        GIR_EraseFromParent, /*InsnID*/0,
        // GIR_Coverage, 10424,
        GIR_Done,
      // Label 4356: @273687
      GIM_Try, /*On fail goto*//*Label 4357*/ GIMT_Encode4(273827), // Rule ID 10476 //
        GIM_CheckRegBankForClass, /*MI*/0, /*Op*/0, /*RC*/GIMT_Encode2(AMDGPU::VGPR_32RegClassID),
        GIM_RecordInsn, /*DefineMI*/1, /*MI*/0, /*OpIdx*/1, // MIs[1]
        GIM_CheckOpcode, /*MI*/1, GIMT_Encode2(TargetOpcode::G_FMAXNUM),
        GIM_CheckType, /*MI*/1, /*Op*/1, /*Type*/GILLT_s32,
        GIM_CheckType, /*MI*/1, /*Op*/2, /*Type*/GILLT_s32,
        GIM_RecordInsn, /*DefineMI*/2, /*MI*/1, /*OpIdx*/2, // MIs[2]
        GIM_CheckOpcode, /*MI*/2, GIMT_Encode2(TargetOpcode::G_FMINNUM),
        GIM_CheckType, /*MI*/2, /*Op*/1, /*Type*/GILLT_s32,
        GIM_CheckType, /*MI*/2, /*Op*/2, /*Type*/GILLT_s32,
        GIM_RecordInsn, /*DefineMI*/3, /*MI*/0, /*OpIdx*/2, // MIs[3]
        GIM_CheckOpcode, /*MI*/3, GIMT_Encode2(TargetOpcode::G_FMAXNUM),
        // MIs[3] VOP3Mods:src0:src0_mods
        GIM_CheckIsSameOperand, /*MI*/3, /*OpIdx*/1, /*OtherMI*/2, /*OtherOpIdx*/1,
        // MIs[3] VOP3Mods:src1:src1_mods
        GIM_CheckIsSameOperand, /*MI*/3, /*OpIdx*/2, /*OtherMI*/2, /*OtherOpIdx*/2,
        GIM_CheckCxxInsnPredicate, /*MI*/0, /*FnId*/GIMT_Encode2(GICXXPred_MI_Predicate_fminnum_like_nnan),
        GIM_CheckIsSafeToFold, /*InsnID*/1,
        GIM_CheckIsSafeToFold, /*InsnID*/2,
        GIM_CheckIsSafeToFold, /*InsnID*/3,
        GIM_CheckComplexPattern, /*MI*/1, /*Op*/1, /*Renderer*/GIMT_Encode2(0), GIMT_Encode2(GICP_gi_vop3mods),
        GIM_CheckComplexPattern, /*MI*/2, /*Op*/1, /*Renderer*/GIMT_Encode2(1), GIMT_Encode2(GICP_gi_vop3mods),
        GIM_CheckComplexPattern, /*MI*/2, /*Op*/2, /*Renderer*/GIMT_Encode2(2), GIMT_Encode2(GICP_gi_vop3mods),
        // (fminnum:{ *:[f32] } (fmaxnum:{ *:[f32] } (VOP3Mods:{ *:[f32] } f32:{ *:[f32] }:$src2, i32:{ *:[i32] }:$src2_mods), (fminnum:{ *:[f32] } (VOP3Mods:{ *:[f32] } f32:{ *:[f32] }:$src0, i32:{ *:[i32] }:$src0_mods), (VOP3Mods:{ *:[f32] } f32:{ *:[f32] }:$src1, i32:{ *:[i32] }:$src1_mods))), (fmaxnum:{ *:[f32] } (VOP3Mods:{ *:[f32] } f32:{ *:[f32] }:$src0, i32:{ *:[i32] }:$src0_mods), (VOP3Mods:{ *:[f32] } f32:{ *:[f32] }:$src1, i32:{ *:[i32] }:$src1_mods)))<<P:Predicate_fminnum_like_nnan>>  =>  (V_MED3_F32_e64:{ *:[f32] } ?:{ *:[i32] }:$src0_mods, ?:{ *:[f32] }:$src0, ?:{ *:[i32] }:$src1_mods, ?:{ *:[f32] }:$src1, ?:{ *:[i32] }:$src2_mods, ?:{ *:[f32] }:$src2, 0:{ *:[i1] }, 0:{ *:[i32] })
        GIR_BuildMI, /*InsnID*/0, /*Opcode*/GIMT_Encode2(AMDGPU::V_MED3_F32_e64),
        GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/0, // DstI[vdst]
        GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(1), /*SubOperand*/1, // src0_mods
        GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(1), /*SubOperand*/0, // src0
        GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(2), /*SubOperand*/1, // src1_mods
        GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(2), /*SubOperand*/0, // src1
        GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/1, // src2_mods
        GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/0, // src2
        GIR_AddImm8, /*InsnID*/0, /*Imm*/0,
        GIR_AddImm8, /*InsnID*/0, /*Imm*/0,
        GIR_ConstrainSelectedInstOperands, /*InsnID*/0,
        GIR_EraseFromParent, /*InsnID*/0,
        // GIR_Coverage, 10476,
        GIR_Done,
      // Label 4357: @273827
      GIM_Try, /*On fail goto*//*Label 4358*/ GIMT_Encode4(273967), // Rule ID 10477 //
        GIM_CheckRegBankForClass, /*MI*/0, /*Op*/0, /*RC*/GIMT_Encode2(AMDGPU::VGPR_32RegClassID),
        GIM_RecordInsn, /*DefineMI*/1, /*MI*/0, /*OpIdx*/1, // MIs[1]
        GIM_CheckOpcode, /*MI*/1, GIMT_Encode2(TargetOpcode::G_FMAXNUM),
        GIM_CheckType, /*MI*/1, /*Op*/1, /*Type*/GILLT_s32,
        GIM_CheckType, /*MI*/1, /*Op*/2, /*Type*/GILLT_s32,
        GIM_RecordInsn, /*DefineMI*/2, /*MI*/1, /*OpIdx*/2, // MIs[2]
        GIM_CheckOpcode, /*MI*/2, GIMT_Encode2(TargetOpcode::G_FMINNUM),
        GIM_CheckType, /*MI*/2, /*Op*/1, /*Type*/GILLT_s32,
        GIM_CheckType, /*MI*/2, /*Op*/2, /*Type*/GILLT_s32,
        GIM_RecordInsn, /*DefineMI*/3, /*MI*/0, /*OpIdx*/2, // MIs[3]
        GIM_CheckOpcode, /*MI*/3, GIMT_Encode2(TargetOpcode::G_FMAXNUM),
        // MIs[3] VOP3Mods:src1:src1_mods
        GIM_CheckIsSameOperand, /*MI*/3, /*OpIdx*/1, /*OtherMI*/2, /*OtherOpIdx*/2,
        // MIs[3] VOP3Mods:src0:src0_mods
        GIM_CheckIsSameOperand, /*MI*/3, /*OpIdx*/2, /*OtherMI*/2, /*OtherOpIdx*/1,
        GIM_CheckCxxInsnPredicate, /*MI*/0, /*FnId*/GIMT_Encode2(GICXXPred_MI_Predicate_fminnum_like_nnan),
        GIM_CheckIsSafeToFold, /*InsnID*/1,
        GIM_CheckIsSafeToFold, /*InsnID*/2,
        GIM_CheckIsSafeToFold, /*InsnID*/3,
        GIM_CheckComplexPattern, /*MI*/1, /*Op*/1, /*Renderer*/GIMT_Encode2(0), GIMT_Encode2(GICP_gi_vop3mods),
        GIM_CheckComplexPattern, /*MI*/2, /*Op*/1, /*Renderer*/GIMT_Encode2(1), GIMT_Encode2(GICP_gi_vop3mods),
        GIM_CheckComplexPattern, /*MI*/2, /*Op*/2, /*Renderer*/GIMT_Encode2(2), GIMT_Encode2(GICP_gi_vop3mods),
        // (fminnum:{ *:[f32] } (fmaxnum:{ *:[f32] } (VOP3Mods:{ *:[f32] } f32:{ *:[f32] }:$src2, i32:{ *:[i32] }:$src2_mods), (fminnum:{ *:[f32] } (VOP3Mods:{ *:[f32] } f32:{ *:[f32] }:$src0, i32:{ *:[i32] }:$src0_mods), (VOP3Mods:{ *:[f32] } f32:{ *:[f32] }:$src1, i32:{ *:[i32] }:$src1_mods))), (fmaxnum:{ *:[f32] } (VOP3Mods:{ *:[f32] } f32:{ *:[f32] }:$src1, i32:{ *:[i32] }:$src1_mods), (VOP3Mods:{ *:[f32] } f32:{ *:[f32] }:$src0, i32:{ *:[i32] }:$src0_mods)))<<P:Predicate_fminnum_like_nnan>>  =>  (V_MED3_F32_e64:{ *:[f32] } ?:{ *:[i32] }:$src0_mods, ?:{ *:[f32] }:$src0, ?:{ *:[i32] }:$src1_mods, ?:{ *:[f32] }:$src1, ?:{ *:[i32] }:$src2_mods, ?:{ *:[f32] }:$src2, 0:{ *:[i1] }, 0:{ *:[i32] })
        GIR_BuildMI, /*InsnID*/0, /*Opcode*/GIMT_Encode2(AMDGPU::V_MED3_F32_e64),
        GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/0, // DstI[vdst]
        GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(1), /*SubOperand*/1, // src0_mods
        GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(1), /*SubOperand*/0, // src0
        GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(2), /*SubOperand*/1, // src1_mods
        GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(2), /*SubOperand*/0, // src1
        GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/1, // src2_mods
        GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/0, // src2
        GIR_AddImm8, /*InsnID*/0, /*Imm*/0,
        GIR_AddImm8, /*InsnID*/0, /*Imm*/0,
        GIR_ConstrainSelectedInstOperands, /*InsnID*/0,
        GIR_EraseFromParent, /*InsnID*/0,
        // GIR_Coverage, 10477,
        GIR_Done,
      // Label 4358: @273967
      GIM_Try, /*On fail goto*//*Label 4359*/ GIMT_Encode4(274107), // Rule ID 10478 //
        GIM_CheckRegBankForClass, /*MI*/0, /*Op*/0, /*RC*/GIMT_Encode2(AMDGPU::VGPR_32RegClassID),
        GIM_RecordInsn, /*DefineMI*/1, /*MI*/0, /*OpIdx*/1, // MIs[1]
        GIM_CheckOpcode, /*MI*/1, GIMT_Encode2(TargetOpcode::G_FMAXNUM),
        GIM_CheckType, /*MI*/1, /*Op*/1, /*Type*/GILLT_s32,
        GIM_CheckType, /*MI*/1, /*Op*/2, /*Type*/GILLT_s32,
        GIM_RecordInsn, /*DefineMI*/2, /*MI*/1, /*OpIdx*/2, // MIs[2]
        GIM_CheckOpcode, /*MI*/2, GIMT_Encode2(TargetOpcode::G_FMINNUM),
        GIM_CheckType, /*MI*/2, /*Op*/1, /*Type*/GILLT_s32,
        GIM_CheckType, /*MI*/2, /*Op*/2, /*Type*/GILLT_s32,
        GIM_RecordInsn, /*DefineMI*/3, /*MI*/0, /*OpIdx*/2, // MIs[3]
        GIM_CheckOpcode, /*MI*/3, GIMT_Encode2(TargetOpcode::G_FMAXNUM),
        // MIs[3] VOP3Mods:src0:src0_mods
        GIM_CheckIsSameOperand, /*MI*/3, /*OpIdx*/1, /*OtherMI*/2, /*OtherOpIdx*/2,
        // MIs[3] VOP3Mods:src1:src1_mods
        GIM_CheckIsSameOperand, /*MI*/3, /*OpIdx*/2, /*OtherMI*/2, /*OtherOpIdx*/1,
        GIM_CheckCxxInsnPredicate, /*MI*/0, /*FnId*/GIMT_Encode2(GICXXPred_MI_Predicate_fminnum_like_nnan),
        GIM_CheckIsSafeToFold, /*InsnID*/1,
        GIM_CheckIsSafeToFold, /*InsnID*/2,
        GIM_CheckIsSafeToFold, /*InsnID*/3,
        GIM_CheckComplexPattern, /*MI*/1, /*Op*/1, /*Renderer*/GIMT_Encode2(0), GIMT_Encode2(GICP_gi_vop3mods),
        GIM_CheckComplexPattern, /*MI*/2, /*Op*/1, /*Renderer*/GIMT_Encode2(1), GIMT_Encode2(GICP_gi_vop3mods),
        GIM_CheckComplexPattern, /*MI*/2, /*Op*/2, /*Renderer*/GIMT_Encode2(2), GIMT_Encode2(GICP_gi_vop3mods),
        // (fminnum:{ *:[f32] } (fmaxnum:{ *:[f32] } (VOP3Mods:{ *:[f32] } f32:{ *:[f32] }:$src2, i32:{ *:[i32] }:$src2_mods), (fminnum:{ *:[f32] } (VOP3Mods:{ *:[f32] } f32:{ *:[f32] }:$src1, i32:{ *:[i32] }:$src1_mods), (VOP3Mods:{ *:[f32] } f32:{ *:[f32] }:$src0, i32:{ *:[i32] }:$src0_mods))), (fmaxnum:{ *:[f32] } (VOP3Mods:{ *:[f32] } f32:{ *:[f32] }:$src0, i32:{ *:[i32] }:$src0_mods), (VOP3Mods:{ *:[f32] } f32:{ *:[f32] }:$src1, i32:{ *:[i32] }:$src1_mods)))<<P:Predicate_fminnum_like_nnan>>  =>  (V_MED3_F32_e64:{ *:[f32] } ?:{ *:[i32] }:$src0_mods, ?:{ *:[f32] }:$src0, ?:{ *:[i32] }:$src1_mods, ?:{ *:[f32] }:$src1, ?:{ *:[i32] }:$src2_mods, ?:{ *:[f32] }:$src2, 0:{ *:[i1] }, 0:{ *:[i32] })
        GIR_BuildMI, /*InsnID*/0, /*Opcode*/GIMT_Encode2(AMDGPU::V_MED3_F32_e64),
        GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/0, // DstI[vdst]
        GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(2), /*SubOperand*/1, // src0_mods
        GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(2), /*SubOperand*/0, // src0
        GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(1), /*SubOperand*/1, // src1_mods
        GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(1), /*SubOperand*/0, // src1
        GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/1, // src2_mods
        GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/0, // src2
        GIR_AddImm8, /*InsnID*/0, /*Imm*/0,
        GIR_AddImm8, /*InsnID*/0, /*Imm*/0,
        GIR_ConstrainSelectedInstOperands, /*InsnID*/0,
        GIR_EraseFromParent, /*InsnID*/0,
        // GIR_Coverage, 10478,
        GIR_Done,
      // Label 4359: @274107
      GIM_Try, /*On fail goto*//*Label 4360*/ GIMT_Encode4(274247), // Rule ID 10479 //
        GIM_CheckRegBankForClass, /*MI*/0, /*Op*/0, /*RC*/GIMT_Encode2(AMDGPU::VGPR_32RegClassID),
        GIM_RecordInsn, /*DefineMI*/1, /*MI*/0, /*OpIdx*/1, // MIs[1]
        GIM_CheckOpcode, /*MI*/1, GIMT_Encode2(TargetOpcode::G_FMAXNUM),
        GIM_CheckType, /*MI*/1, /*Op*/1, /*Type*/GILLT_s32,
        GIM_CheckType, /*MI*/1, /*Op*/2, /*Type*/GILLT_s32,
        GIM_RecordInsn, /*DefineMI*/2, /*MI*/1, /*OpIdx*/2, // MIs[2]
        GIM_CheckOpcode, /*MI*/2, GIMT_Encode2(TargetOpcode::G_FMINNUM),
        GIM_CheckType, /*MI*/2, /*Op*/1, /*Type*/GILLT_s32,
        GIM_CheckType, /*MI*/2, /*Op*/2, /*Type*/GILLT_s32,
        GIM_RecordInsn, /*DefineMI*/3, /*MI*/0, /*OpIdx*/2, // MIs[3]
        GIM_CheckOpcode, /*MI*/3, GIMT_Encode2(TargetOpcode::G_FMAXNUM),
        // MIs[3] VOP3Mods:src1:src1_mods
        GIM_CheckIsSameOperand, /*MI*/3, /*OpIdx*/1, /*OtherMI*/2, /*OtherOpIdx*/1,
        // MIs[3] VOP3Mods:src0:src0_mods
        GIM_CheckIsSameOperand, /*MI*/3, /*OpIdx*/2, /*OtherMI*/2, /*OtherOpIdx*/2,
        GIM_CheckCxxInsnPredicate, /*MI*/0, /*FnId*/GIMT_Encode2(GICXXPred_MI_Predicate_fminnum_like_nnan),
        GIM_CheckIsSafeToFold, /*InsnID*/1,
        GIM_CheckIsSafeToFold, /*InsnID*/2,
        GIM_CheckIsSafeToFold, /*InsnID*/3,
        GIM_CheckComplexPattern, /*MI*/1, /*Op*/1, /*Renderer*/GIMT_Encode2(0), GIMT_Encode2(GICP_gi_vop3mods),
        GIM_CheckComplexPattern, /*MI*/2, /*Op*/1, /*Renderer*/GIMT_Encode2(1), GIMT_Encode2(GICP_gi_vop3mods),
        GIM_CheckComplexPattern, /*MI*/2, /*Op*/2, /*Renderer*/GIMT_Encode2(2), GIMT_Encode2(GICP_gi_vop3mods),
        // (fminnum:{ *:[f32] } (fmaxnum:{ *:[f32] } (VOP3Mods:{ *:[f32] } f32:{ *:[f32] }:$src2, i32:{ *:[i32] }:$src2_mods), (fminnum:{ *:[f32] } (VOP3Mods:{ *:[f32] } f32:{ *:[f32] }:$src1, i32:{ *:[i32] }:$src1_mods), (VOP3Mods:{ *:[f32] } f32:{ *:[f32] }:$src0, i32:{ *:[i32] }:$src0_mods))), (fmaxnum:{ *:[f32] } (VOP3Mods:{ *:[f32] } f32:{ *:[f32] }:$src1, i32:{ *:[i32] }:$src1_mods), (VOP3Mods:{ *:[f32] } f32:{ *:[f32] }:$src0, i32:{ *:[i32] }:$src0_mods)))<<P:Predicate_fminnum_like_nnan>>  =>  (V_MED3_F32_e64:{ *:[f32] } ?:{ *:[i32] }:$src0_mods, ?:{ *:[f32] }:$src0, ?:{ *:[i32] }:$src1_mods, ?:{ *:[f32] }:$src1, ?:{ *:[i32] }:$src2_mods, ?:{ *:[f32] }:$src2, 0:{ *:[i1] }, 0:{ *:[i32] })
        GIR_BuildMI, /*InsnID*/0, /*Opcode*/GIMT_Encode2(AMDGPU::V_MED3_F32_e64),
        GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/0, // DstI[vdst]
        GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(2), /*SubOperand*/1, // src0_mods
        GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(2), /*SubOperand*/0, // src0
        GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(1), /*SubOperand*/1, // src1_mods
        GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(1), /*SubOperand*/0, // src1
        GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/1, // src2_mods
        GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/0, // src2
        GIR_AddImm8, /*InsnID*/0, /*Imm*/0,
        GIR_AddImm8, /*InsnID*/0, /*Imm*/0,
        GIR_ConstrainSelectedInstOperands, /*InsnID*/0,
        GIR_EraseFromParent, /*InsnID*/0,
        // GIR_Coverage, 10479,
        GIR_Done,
      // Label 4360: @274247
      GIM_Try, /*On fail goto*//*Label 4361*/ GIMT_Encode4(274387), // Rule ID 10416 //
        GIM_CheckRegBankForClass, /*MI*/0, /*Op*/0, /*RC*/GIMT_Encode2(AMDGPU::VGPR_32RegClassID),
        GIM_RecordInsn, /*DefineMI*/1, /*MI*/0, /*OpIdx*/1, // MIs[1]
        GIM_CheckOpcode, /*MI*/1, GIMT_Encode2(TargetOpcode::G_FMAXNUM),
        GIM_CheckType, /*MI*/1, /*Op*/1, /*Type*/GILLT_s32,
        GIM_CheckType, /*MI*/1, /*Op*/2, /*Type*/GILLT_s32,
        GIM_RecordInsn, /*DefineMI*/2, /*MI*/1, /*OpIdx*/2, // MIs[2]
        GIM_CheckOpcode, /*MI*/2, GIMT_Encode2(TargetOpcode::G_FMINNUM),
        GIM_CheckType, /*MI*/2, /*Op*/1, /*Type*/GILLT_s32,
        GIM_CheckType, /*MI*/2, /*Op*/2, /*Type*/GILLT_s32,
        GIM_RecordInsn, /*DefineMI*/3, /*MI*/0, /*OpIdx*/2, // MIs[3]
        GIM_CheckOpcode, /*MI*/3, GIMT_Encode2(TargetOpcode::G_FMAXNUM_IEEE),
        // MIs[3] VOP3Mods:src0:src0_mods
        GIM_CheckIsSameOperand, /*MI*/3, /*OpIdx*/1, /*OtherMI*/2, /*OtherOpIdx*/1,
        // MIs[3] VOP3Mods:src1:src1_mods
        GIM_CheckIsSameOperand, /*MI*/3, /*OpIdx*/2, /*OtherMI*/2, /*OtherOpIdx*/2,
        GIM_CheckCxxInsnPredicate, /*MI*/0, /*FnId*/GIMT_Encode2(GICXXPred_MI_Predicate_fminnum_like_nnan),
        GIM_CheckIsSafeToFold, /*InsnID*/1,
        GIM_CheckIsSafeToFold, /*InsnID*/2,
        GIM_CheckIsSafeToFold, /*InsnID*/3,
        GIM_CheckComplexPattern, /*MI*/1, /*Op*/1, /*Renderer*/GIMT_Encode2(0), GIMT_Encode2(GICP_gi_vop3mods),
        GIM_CheckComplexPattern, /*MI*/2, /*Op*/1, /*Renderer*/GIMT_Encode2(1), GIMT_Encode2(GICP_gi_vop3mods),
        GIM_CheckComplexPattern, /*MI*/2, /*Op*/2, /*Renderer*/GIMT_Encode2(2), GIMT_Encode2(GICP_gi_vop3mods),
        // (fminnum:{ *:[f32] } (fmaxnum:{ *:[f32] } (VOP3Mods:{ *:[f32] } f32:{ *:[f32] }:$src2, i32:{ *:[i32] }:$src2_mods), (fminnum:{ *:[f32] } (VOP3Mods:{ *:[f32] } f32:{ *:[f32] }:$src0, i32:{ *:[i32] }:$src0_mods), (VOP3Mods:{ *:[f32] } f32:{ *:[f32] }:$src1, i32:{ *:[i32] }:$src1_mods))), (fmaxnum_ieee:{ *:[f32] } (VOP3Mods:{ *:[f32] } f32:{ *:[f32] }:$src0, i32:{ *:[i32] }:$src0_mods), (VOP3Mods:{ *:[f32] } f32:{ *:[f32] }:$src1, i32:{ *:[i32] }:$src1_mods)))<<P:Predicate_fminnum_like_nnan>>  =>  (V_MED3_F32_e64:{ *:[f32] } ?:{ *:[i32] }:$src0_mods, ?:{ *:[f32] }:$src0, ?:{ *:[i32] }:$src1_mods, ?:{ *:[f32] }:$src1, ?:{ *:[i32] }:$src2_mods, ?:{ *:[f32] }:$src2, 0:{ *:[i1] }, 0:{ *:[i32] })
        GIR_BuildMI, /*InsnID*/0, /*Opcode*/GIMT_Encode2(AMDGPU::V_MED3_F32_e64),
        GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/0, // DstI[vdst]
        GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(1), /*SubOperand*/1, // src0_mods
        GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(1), /*SubOperand*/0, // src0
        GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(2), /*SubOperand*/1, // src1_mods
        GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(2), /*SubOperand*/0, // src1
        GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/1, // src2_mods
        GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/0, // src2
        GIR_AddImm8, /*InsnID*/0, /*Imm*/0,
        GIR_AddImm8, /*InsnID*/0, /*Imm*/0,
        GIR_ConstrainSelectedInstOperands, /*InsnID*/0,
        GIR_EraseFromParent, /*InsnID*/0,
        // GIR_Coverage, 10416,
        GIR_Done,
      // Label 4361: @274387
      GIM_Try, /*On fail goto*//*Label 4362*/ GIMT_Encode4(274527), // Rule ID 10417 //
        GIM_CheckRegBankForClass, /*MI*/0, /*Op*/0, /*RC*/GIMT_Encode2(AMDGPU::VGPR_32RegClassID),
        GIM_RecordInsn, /*DefineMI*/1, /*MI*/0, /*OpIdx*/1, // MIs[1]
        GIM_CheckOpcode, /*MI*/1, GIMT_Encode2(TargetOpcode::G_FMAXNUM),
        GIM_CheckType, /*MI*/1, /*Op*/1, /*Type*/GILLT_s32,
        GIM_CheckType, /*MI*/1, /*Op*/2, /*Type*/GILLT_s32,
        GIM_RecordInsn, /*DefineMI*/2, /*MI*/1, /*OpIdx*/2, // MIs[2]
        GIM_CheckOpcode, /*MI*/2, GIMT_Encode2(TargetOpcode::G_FMINNUM),
        GIM_CheckType, /*MI*/2, /*Op*/1, /*Type*/GILLT_s32,
        GIM_CheckType, /*MI*/2, /*Op*/2, /*Type*/GILLT_s32,
        GIM_RecordInsn, /*DefineMI*/3, /*MI*/0, /*OpIdx*/2, // MIs[3]
        GIM_CheckOpcode, /*MI*/3, GIMT_Encode2(TargetOpcode::G_FMAXNUM_IEEE),
        // MIs[3] VOP3Mods:src1:src1_mods
        GIM_CheckIsSameOperand, /*MI*/3, /*OpIdx*/1, /*OtherMI*/2, /*OtherOpIdx*/2,
        // MIs[3] VOP3Mods:src0:src0_mods
        GIM_CheckIsSameOperand, /*MI*/3, /*OpIdx*/2, /*OtherMI*/2, /*OtherOpIdx*/1,
        GIM_CheckCxxInsnPredicate, /*MI*/0, /*FnId*/GIMT_Encode2(GICXXPred_MI_Predicate_fminnum_like_nnan),
        GIM_CheckIsSafeToFold, /*InsnID*/1,
        GIM_CheckIsSafeToFold, /*InsnID*/2,
        GIM_CheckIsSafeToFold, /*InsnID*/3,
        GIM_CheckComplexPattern, /*MI*/1, /*Op*/1, /*Renderer*/GIMT_Encode2(0), GIMT_Encode2(GICP_gi_vop3mods),
        GIM_CheckComplexPattern, /*MI*/2, /*Op*/1, /*Renderer*/GIMT_Encode2(1), GIMT_Encode2(GICP_gi_vop3mods),
        GIM_CheckComplexPattern, /*MI*/2, /*Op*/2, /*Renderer*/GIMT_Encode2(2), GIMT_Encode2(GICP_gi_vop3mods),
        // (fminnum:{ *:[f32] } (fmaxnum:{ *:[f32] } (VOP3Mods:{ *:[f32] } f32:{ *:[f32] }:$src2, i32:{ *:[i32] }:$src2_mods), (fminnum:{ *:[f32] } (VOP3Mods:{ *:[f32] } f32:{ *:[f32] }:$src0, i32:{ *:[i32] }:$src0_mods), (VOP3Mods:{ *:[f32] } f32:{ *:[f32] }:$src1, i32:{ *:[i32] }:$src1_mods))), (fmaxnum_ieee:{ *:[f32] } (VOP3Mods:{ *:[f32] } f32:{ *:[f32] }:$src1, i32:{ *:[i32] }:$src1_mods), (VOP3Mods:{ *:[f32] } f32:{ *:[f32] }:$src0, i32:{ *:[i32] }:$src0_mods)))<<P:Predicate_fminnum_like_nnan>>  =>  (V_MED3_F32_e64:{ *:[f32] } ?:{ *:[i32] }:$src0_mods, ?:{ *:[f32] }:$src0, ?:{ *:[i32] }:$src1_mods, ?:{ *:[f32] }:$src1, ?:{ *:[i32] }:$src2_mods, ?:{ *:[f32] }:$src2, 0:{ *:[i1] }, 0:{ *:[i32] })
        GIR_BuildMI, /*InsnID*/0, /*Opcode*/GIMT_Encode2(AMDGPU::V_MED3_F32_e64),
        GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/0, // DstI[vdst]
        GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(1), /*SubOperand*/1, // src0_mods
        GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(1), /*SubOperand*/0, // src0
        GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(2), /*SubOperand*/1, // src1_mods
        GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(2), /*SubOperand*/0, // src1
        GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/1, // src2_mods
        GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/0, // src2
        GIR_AddImm8, /*InsnID*/0, /*Imm*/0,
        GIR_AddImm8, /*InsnID*/0, /*Imm*/0,
        GIR_ConstrainSelectedInstOperands, /*InsnID*/0,
        GIR_EraseFromParent, /*InsnID*/0,
        // GIR_Coverage, 10417,
        GIR_Done,
      // Label 4362: @274527
      GIM_Try, /*On fail goto*//*Label 4363*/ GIMT_Encode4(274667), // Rule ID 10418 //
        GIM_CheckRegBankForClass, /*MI*/0, /*Op*/0, /*RC*/GIMT_Encode2(AMDGPU::VGPR_32RegClassID),
        GIM_RecordInsn, /*DefineMI*/1, /*MI*/0, /*OpIdx*/1, // MIs[1]
        GIM_CheckOpcode, /*MI*/1, GIMT_Encode2(TargetOpcode::G_FMAXNUM),
        GIM_CheckType, /*MI*/1, /*Op*/1, /*Type*/GILLT_s32,
        GIM_CheckType, /*MI*/1, /*Op*/2, /*Type*/GILLT_s32,
        GIM_RecordInsn, /*DefineMI*/2, /*MI*/1, /*OpIdx*/2, // MIs[2]
        GIM_CheckOpcode, /*MI*/2, GIMT_Encode2(TargetOpcode::G_FMINNUM),
        GIM_CheckType, /*MI*/2, /*Op*/1, /*Type*/GILLT_s32,
        GIM_CheckType, /*MI*/2, /*Op*/2, /*Type*/GILLT_s32,
        GIM_RecordInsn, /*DefineMI*/3, /*MI*/0, /*OpIdx*/2, // MIs[3]
        GIM_CheckOpcode, /*MI*/3, GIMT_Encode2(TargetOpcode::G_FMAXNUM_IEEE),
        // MIs[3] VOP3Mods:src0:src0_mods
        GIM_CheckIsSameOperand, /*MI*/3, /*OpIdx*/1, /*OtherMI*/2, /*OtherOpIdx*/2,
        // MIs[3] VOP3Mods:src1:src1_mods
        GIM_CheckIsSameOperand, /*MI*/3, /*OpIdx*/2, /*OtherMI*/2, /*OtherOpIdx*/1,
        GIM_CheckCxxInsnPredicate, /*MI*/0, /*FnId*/GIMT_Encode2(GICXXPred_MI_Predicate_fminnum_like_nnan),
        GIM_CheckIsSafeToFold, /*InsnID*/1,
        GIM_CheckIsSafeToFold, /*InsnID*/2,
        GIM_CheckIsSafeToFold, /*InsnID*/3,
        GIM_CheckComplexPattern, /*MI*/1, /*Op*/1, /*Renderer*/GIMT_Encode2(0), GIMT_Encode2(GICP_gi_vop3mods),
        GIM_CheckComplexPattern, /*MI*/2, /*Op*/1, /*Renderer*/GIMT_Encode2(1), GIMT_Encode2(GICP_gi_vop3mods),
        GIM_CheckComplexPattern, /*MI*/2, /*Op*/2, /*Renderer*/GIMT_Encode2(2), GIMT_Encode2(GICP_gi_vop3mods),
        // (fminnum:{ *:[f32] } (fmaxnum:{ *:[f32] } (VOP3Mods:{ *:[f32] } f32:{ *:[f32] }:$src2, i32:{ *:[i32] }:$src2_mods), (fminnum:{ *:[f32] } (VOP3Mods:{ *:[f32] } f32:{ *:[f32] }:$src1, i32:{ *:[i32] }:$src1_mods), (VOP3Mods:{ *:[f32] } f32:{ *:[f32] }:$src0, i32:{ *:[i32] }:$src0_mods))), (fmaxnum_ieee:{ *:[f32] } (VOP3Mods:{ *:[f32] } f32:{ *:[f32] }:$src0, i32:{ *:[i32] }:$src0_mods), (VOP3Mods:{ *:[f32] } f32:{ *:[f32] }:$src1, i32:{ *:[i32] }:$src1_mods)))<<P:Predicate_fminnum_like_nnan>>  =>  (V_MED3_F32_e64:{ *:[f32] } ?:{ *:[i32] }:$src0_mods, ?:{ *:[f32] }:$src0, ?:{ *:[i32] }:$src1_mods, ?:{ *:[f32] }:$src1, ?:{ *:[i32] }:$src2_mods, ?:{ *:[f32] }:$src2, 0:{ *:[i1] }, 0:{ *:[i32] })
        GIR_BuildMI, /*InsnID*/0, /*Opcode*/GIMT_Encode2(AMDGPU::V_MED3_F32_e64),
        GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/0, // DstI[vdst]
        GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(2), /*SubOperand*/1, // src0_mods
        GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(2), /*SubOperand*/0, // src0
        GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(1), /*SubOperand*/1, // src1_mods
        GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(1), /*SubOperand*/0, // src1
        GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/1, // src2_mods
        GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/0, // src2
        GIR_AddImm8, /*InsnID*/0, /*Imm*/0,
        GIR_AddImm8, /*InsnID*/0, /*Imm*/0,
        GIR_ConstrainSelectedInstOperands, /*InsnID*/0,
        GIR_EraseFromParent, /*InsnID*/0,
        // GIR_Coverage, 10418,
        GIR_Done,
      // Label 4363: @274667
      GIM_Try, /*On fail goto*//*Label 4364*/ GIMT_Encode4(274807), // Rule ID 10419 //
        GIM_CheckRegBankForClass, /*MI*/0, /*Op*/0, /*RC*/GIMT_Encode2(AMDGPU::VGPR_32RegClassID),
        GIM_RecordInsn, /*DefineMI*/1, /*MI*/0, /*OpIdx*/1, // MIs[1]
        GIM_CheckOpcode, /*MI*/1, GIMT_Encode2(TargetOpcode::G_FMAXNUM),
        GIM_CheckType, /*MI*/1, /*Op*/1, /*Type*/GILLT_s32,
        GIM_CheckType, /*MI*/1, /*Op*/2, /*Type*/GILLT_s32,
        GIM_RecordInsn, /*DefineMI*/2, /*MI*/1, /*OpIdx*/2, // MIs[2]
        GIM_CheckOpcode, /*MI*/2, GIMT_Encode2(TargetOpcode::G_FMINNUM),
        GIM_CheckType, /*MI*/2, /*Op*/1, /*Type*/GILLT_s32,
        GIM_CheckType, /*MI*/2, /*Op*/2, /*Type*/GILLT_s32,
        GIM_RecordInsn, /*DefineMI*/3, /*MI*/0, /*OpIdx*/2, // MIs[3]
        GIM_CheckOpcode, /*MI*/3, GIMT_Encode2(TargetOpcode::G_FMAXNUM_IEEE),
        // MIs[3] VOP3Mods:src1:src1_mods
        GIM_CheckIsSameOperand, /*MI*/3, /*OpIdx*/1, /*OtherMI*/2, /*OtherOpIdx*/1,
        // MIs[3] VOP3Mods:src0:src0_mods
        GIM_CheckIsSameOperand, /*MI*/3, /*OpIdx*/2, /*OtherMI*/2, /*OtherOpIdx*/2,
        GIM_CheckCxxInsnPredicate, /*MI*/0, /*FnId*/GIMT_Encode2(GICXXPred_MI_Predicate_fminnum_like_nnan),
        GIM_CheckIsSafeToFold, /*InsnID*/1,
        GIM_CheckIsSafeToFold, /*InsnID*/2,
        GIM_CheckIsSafeToFold, /*InsnID*/3,
        GIM_CheckComplexPattern, /*MI*/1, /*Op*/1, /*Renderer*/GIMT_Encode2(0), GIMT_Encode2(GICP_gi_vop3mods),
        GIM_CheckComplexPattern, /*MI*/2, /*Op*/1, /*Renderer*/GIMT_Encode2(1), GIMT_Encode2(GICP_gi_vop3mods),
        GIM_CheckComplexPattern, /*MI*/2, /*Op*/2, /*Renderer*/GIMT_Encode2(2), GIMT_Encode2(GICP_gi_vop3mods),
        // (fminnum:{ *:[f32] } (fmaxnum:{ *:[f32] } (VOP3Mods:{ *:[f32] } f32:{ *:[f32] }:$src2, i32:{ *:[i32] }:$src2_mods), (fminnum:{ *:[f32] } (VOP3Mods:{ *:[f32] } f32:{ *:[f32] }:$src1, i32:{ *:[i32] }:$src1_mods), (VOP3Mods:{ *:[f32] } f32:{ *:[f32] }:$src0, i32:{ *:[i32] }:$src0_mods))), (fmaxnum_ieee:{ *:[f32] } (VOP3Mods:{ *:[f32] } f32:{ *:[f32] }:$src1, i32:{ *:[i32] }:$src1_mods), (VOP3Mods:{ *:[f32] } f32:{ *:[f32] }:$src0, i32:{ *:[i32] }:$src0_mods)))<<P:Predicate_fminnum_like_nnan>>  =>  (V_MED3_F32_e64:{ *:[f32] } ?:{ *:[i32] }:$src0_mods, ?:{ *:[f32] }:$src0, ?:{ *:[i32] }:$src1_mods, ?:{ *:[f32] }:$src1, ?:{ *:[i32] }:$src2_mods, ?:{ *:[f32] }:$src2, 0:{ *:[i1] }, 0:{ *:[i32] })
        GIR_BuildMI, /*InsnID*/0, /*Opcode*/GIMT_Encode2(AMDGPU::V_MED3_F32_e64),
        GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/0, // DstI[vdst]
        GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(2), /*SubOperand*/1, // src0_mods
        GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(2), /*SubOperand*/0, // src0
        GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(1), /*SubOperand*/1, // src1_mods
        GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(1), /*SubOperand*/0, // src1
        GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/1, // src2_mods
        GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/0, // src2
        GIR_AddImm8, /*InsnID*/0, /*Imm*/0,
        GIR_AddImm8, /*InsnID*/0, /*Imm*/0,
        GIR_ConstrainSelectedInstOperands, /*InsnID*/0,
        GIR_EraseFromParent, /*InsnID*/0,
        // GIR_Coverage, 10419,
        GIR_Done,
      // Label 4364: @274807
      GIM_Try, /*On fail goto*//*Label 4365*/ GIMT_Encode4(274947), // Rule ID 10461 //
        GIM_CheckRegBankForClass, /*MI*/0, /*Op*/0, /*RC*/GIMT_Encode2(AMDGPU::VGPR_32RegClassID),
        GIM_RecordInsn, /*DefineMI*/1, /*MI*/0, /*OpIdx*/1, // MIs[1]
        GIM_CheckOpcode, /*MI*/1, GIMT_Encode2(TargetOpcode::G_FMAXNUM),
        GIM_CheckType, /*MI*/1, /*Op*/1, /*Type*/GILLT_s32,
        GIM_CheckType, /*MI*/1, /*Op*/2, /*Type*/GILLT_s32,
        GIM_RecordInsn, /*DefineMI*/2, /*MI*/1, /*OpIdx*/2, // MIs[2]
        GIM_CheckOpcode, /*MI*/2, GIMT_Encode2(TargetOpcode::G_FMINNUM_IEEE),
        GIM_CheckType, /*MI*/2, /*Op*/1, /*Type*/GILLT_s32,
        GIM_CheckType, /*MI*/2, /*Op*/2, /*Type*/GILLT_s32,
        GIM_RecordInsn, /*DefineMI*/3, /*MI*/0, /*OpIdx*/2, // MIs[3]
        GIM_CheckOpcode, /*MI*/3, GIMT_Encode2(TargetOpcode::G_FMAXNUM),
        // MIs[3] VOP3Mods:src0:src0_mods
        GIM_CheckIsSameOperand, /*MI*/3, /*OpIdx*/1, /*OtherMI*/2, /*OtherOpIdx*/1,
        // MIs[3] VOP3Mods:src1:src1_mods
        GIM_CheckIsSameOperand, /*MI*/3, /*OpIdx*/2, /*OtherMI*/2, /*OtherOpIdx*/2,
        GIM_CheckCxxInsnPredicate, /*MI*/0, /*FnId*/GIMT_Encode2(GICXXPred_MI_Predicate_fminnum_like_nnan),
        GIM_CheckIsSafeToFold, /*InsnID*/1,
        GIM_CheckIsSafeToFold, /*InsnID*/2,
        GIM_CheckIsSafeToFold, /*InsnID*/3,
        GIM_CheckComplexPattern, /*MI*/1, /*Op*/1, /*Renderer*/GIMT_Encode2(0), GIMT_Encode2(GICP_gi_vop3mods),
        GIM_CheckComplexPattern, /*MI*/2, /*Op*/1, /*Renderer*/GIMT_Encode2(1), GIMT_Encode2(GICP_gi_vop3mods),
        GIM_CheckComplexPattern, /*MI*/2, /*Op*/2, /*Renderer*/GIMT_Encode2(2), GIMT_Encode2(GICP_gi_vop3mods),
        // (fminnum:{ *:[f32] } (fmaxnum:{ *:[f32] } (VOP3Mods:{ *:[f32] } f32:{ *:[f32] }:$src2, i32:{ *:[i32] }:$src2_mods), (fminnum_ieee:{ *:[f32] } (VOP3Mods:{ *:[f32] } f32:{ *:[f32] }:$src0, i32:{ *:[i32] }:$src0_mods), (VOP3Mods:{ *:[f32] } f32:{ *:[f32] }:$src1, i32:{ *:[i32] }:$src1_mods))), (fmaxnum:{ *:[f32] } (VOP3Mods:{ *:[f32] } f32:{ *:[f32] }:$src0, i32:{ *:[i32] }:$src0_mods), (VOP3Mods:{ *:[f32] } f32:{ *:[f32] }:$src1, i32:{ *:[i32] }:$src1_mods)))<<P:Predicate_fminnum_like_nnan>>  =>  (V_MED3_F32_e64:{ *:[f32] } ?:{ *:[i32] }:$src0_mods, ?:{ *:[f32] }:$src0, ?:{ *:[i32] }:$src1_mods, ?:{ *:[f32] }:$src1, ?:{ *:[i32] }:$src2_mods, ?:{ *:[f32] }:$src2, 0:{ *:[i1] }, 0:{ *:[i32] })
        GIR_BuildMI, /*InsnID*/0, /*Opcode*/GIMT_Encode2(AMDGPU::V_MED3_F32_e64),
        GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/0, // DstI[vdst]
        GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(1), /*SubOperand*/1, // src0_mods
        GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(1), /*SubOperand*/0, // src0
        GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(2), /*SubOperand*/1, // src1_mods
        GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(2), /*SubOperand*/0, // src1
        GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/1, // src2_mods
        GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/0, // src2
        GIR_AddImm8, /*InsnID*/0, /*Imm*/0,
        GIR_AddImm8, /*InsnID*/0, /*Imm*/0,
        GIR_ConstrainSelectedInstOperands, /*InsnID*/0,
        GIR_EraseFromParent, /*InsnID*/0,
        // GIR_Coverage, 10461,
        GIR_Done,
      // Label 4365: @274947
      GIM_Try, /*On fail goto*//*Label 4366*/ GIMT_Encode4(275087), // Rule ID 10462 //
        GIM_CheckRegBankForClass, /*MI*/0, /*Op*/0, /*RC*/GIMT_Encode2(AMDGPU::VGPR_32RegClassID),
        GIM_RecordInsn, /*DefineMI*/1, /*MI*/0, /*OpIdx*/1, // MIs[1]
        GIM_CheckOpcode, /*MI*/1, GIMT_Encode2(TargetOpcode::G_FMAXNUM),
        GIM_CheckType, /*MI*/1, /*Op*/1, /*Type*/GILLT_s32,
        GIM_CheckType, /*MI*/1, /*Op*/2, /*Type*/GILLT_s32,
        GIM_RecordInsn, /*DefineMI*/2, /*MI*/1, /*OpIdx*/2, // MIs[2]
        GIM_CheckOpcode, /*MI*/2, GIMT_Encode2(TargetOpcode::G_FMINNUM_IEEE),
        GIM_CheckType, /*MI*/2, /*Op*/1, /*Type*/GILLT_s32,
        GIM_CheckType, /*MI*/2, /*Op*/2, /*Type*/GILLT_s32,
        GIM_RecordInsn, /*DefineMI*/3, /*MI*/0, /*OpIdx*/2, // MIs[3]
        GIM_CheckOpcode, /*MI*/3, GIMT_Encode2(TargetOpcode::G_FMAXNUM),
        // MIs[3] VOP3Mods:src1:src1_mods
        GIM_CheckIsSameOperand, /*MI*/3, /*OpIdx*/1, /*OtherMI*/2, /*OtherOpIdx*/2,
        // MIs[3] VOP3Mods:src0:src0_mods
        GIM_CheckIsSameOperand, /*MI*/3, /*OpIdx*/2, /*OtherMI*/2, /*OtherOpIdx*/1,
        GIM_CheckCxxInsnPredicate, /*MI*/0, /*FnId*/GIMT_Encode2(GICXXPred_MI_Predicate_fminnum_like_nnan),
        GIM_CheckIsSafeToFold, /*InsnID*/1,
        GIM_CheckIsSafeToFold, /*InsnID*/2,
        GIM_CheckIsSafeToFold, /*InsnID*/3,
        GIM_CheckComplexPattern, /*MI*/1, /*Op*/1, /*Renderer*/GIMT_Encode2(0), GIMT_Encode2(GICP_gi_vop3mods),
        GIM_CheckComplexPattern, /*MI*/2, /*Op*/1, /*Renderer*/GIMT_Encode2(1), GIMT_Encode2(GICP_gi_vop3mods),
        GIM_CheckComplexPattern, /*MI*/2, /*Op*/2, /*Renderer*/GIMT_Encode2(2), GIMT_Encode2(GICP_gi_vop3mods),
        // (fminnum:{ *:[f32] } (fmaxnum:{ *:[f32] } (VOP3Mods:{ *:[f32] } f32:{ *:[f32] }:$src2, i32:{ *:[i32] }:$src2_mods), (fminnum_ieee:{ *:[f32] } (VOP3Mods:{ *:[f32] } f32:{ *:[f32] }:$src0, i32:{ *:[i32] }:$src0_mods), (VOP3Mods:{ *:[f32] } f32:{ *:[f32] }:$src1, i32:{ *:[i32] }:$src1_mods))), (fmaxnum:{ *:[f32] } (VOP3Mods:{ *:[f32] } f32:{ *:[f32] }:$src1, i32:{ *:[i32] }:$src1_mods), (VOP3Mods:{ *:[f32] } f32:{ *:[f32] }:$src0, i32:{ *:[i32] }:$src0_mods)))<<P:Predicate_fminnum_like_nnan>>  =>  (V_MED3_F32_e64:{ *:[f32] } ?:{ *:[i32] }:$src0_mods, ?:{ *:[f32] }:$src0, ?:{ *:[i32] }:$src1_mods, ?:{ *:[f32] }:$src1, ?:{ *:[i32] }:$src2_mods, ?:{ *:[f32] }:$src2, 0:{ *:[i1] }, 0:{ *:[i32] })
        GIR_BuildMI, /*InsnID*/0, /*Opcode*/GIMT_Encode2(AMDGPU::V_MED3_F32_e64),
        GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/0, // DstI[vdst]
        GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(1), /*SubOperand*/1, // src0_mods
        GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(1), /*SubOperand*/0, // src0
        GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(2), /*SubOperand*/1, // src1_mods
        GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(2), /*SubOperand*/0, // src1
        GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/1, // src2_mods
        GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/0, // src2
        GIR_AddImm8, /*InsnID*/0, /*Imm*/0,
        GIR_AddImm8, /*InsnID*/0, /*Imm*/0,
        GIR_ConstrainSelectedInstOperands, /*InsnID*/0,
        GIR_EraseFromParent, /*InsnID*/0,
        // GIR_Coverage, 10462,
        GIR_Done,
      // Label 4366: @275087
      GIM_Try, /*On fail goto*//*Label 4367*/ GIMT_Encode4(275227), // Rule ID 10463 //
        GIM_CheckRegBankForClass, /*MI*/0, /*Op*/0, /*RC*/GIMT_Encode2(AMDGPU::VGPR_32RegClassID),
        GIM_RecordInsn, /*DefineMI*/1, /*MI*/0, /*OpIdx*/1, // MIs[1]
        GIM_CheckOpcode, /*MI*/1, GIMT_Encode2(TargetOpcode::G_FMAXNUM),
        GIM_CheckType, /*MI*/1, /*Op*/1, /*Type*/GILLT_s32,
        GIM_CheckType, /*MI*/1, /*Op*/2, /*Type*/GILLT_s32,
        GIM_RecordInsn, /*DefineMI*/2, /*MI*/1, /*OpIdx*/2, // MIs[2]
        GIM_CheckOpcode, /*MI*/2, GIMT_Encode2(TargetOpcode::G_FMINNUM_IEEE),
        GIM_CheckType, /*MI*/2, /*Op*/1, /*Type*/GILLT_s32,
        GIM_CheckType, /*MI*/2, /*Op*/2, /*Type*/GILLT_s32,
        GIM_RecordInsn, /*DefineMI*/3, /*MI*/0, /*OpIdx*/2, // MIs[3]
        GIM_CheckOpcode, /*MI*/3, GIMT_Encode2(TargetOpcode::G_FMAXNUM),
        // MIs[3] VOP3Mods:src0:src0_mods
        GIM_CheckIsSameOperand, /*MI*/3, /*OpIdx*/1, /*OtherMI*/2, /*OtherOpIdx*/2,
        // MIs[3] VOP3Mods:src1:src1_mods
        GIM_CheckIsSameOperand, /*MI*/3, /*OpIdx*/2, /*OtherMI*/2, /*OtherOpIdx*/1,
        GIM_CheckCxxInsnPredicate, /*MI*/0, /*FnId*/GIMT_Encode2(GICXXPred_MI_Predicate_fminnum_like_nnan),
        GIM_CheckIsSafeToFold, /*InsnID*/1,
        GIM_CheckIsSafeToFold, /*InsnID*/2,
        GIM_CheckIsSafeToFold, /*InsnID*/3,
        GIM_CheckComplexPattern, /*MI*/1, /*Op*/1, /*Renderer*/GIMT_Encode2(0), GIMT_Encode2(GICP_gi_vop3mods),
        GIM_CheckComplexPattern, /*MI*/2, /*Op*/1, /*Renderer*/GIMT_Encode2(1), GIMT_Encode2(GICP_gi_vop3mods),
        GIM_CheckComplexPattern, /*MI*/2, /*Op*/2, /*Renderer*/GIMT_Encode2(2), GIMT_Encode2(GICP_gi_vop3mods),
        // (fminnum:{ *:[f32] } (fmaxnum:{ *:[f32] } (VOP3Mods:{ *:[f32] } f32:{ *:[f32] }:$src2, i32:{ *:[i32] }:$src2_mods), (fminnum_ieee:{ *:[f32] } (VOP3Mods:{ *:[f32] } f32:{ *:[f32] }:$src1, i32:{ *:[i32] }:$src1_mods), (VOP3Mods:{ *:[f32] } f32:{ *:[f32] }:$src0, i32:{ *:[i32] }:$src0_mods))), (fmaxnum:{ *:[f32] } (VOP3Mods:{ *:[f32] } f32:{ *:[f32] }:$src0, i32:{ *:[i32] }:$src0_mods), (VOP3Mods:{ *:[f32] } f32:{ *:[f32] }:$src1, i32:{ *:[i32] }:$src1_mods)))<<P:Predicate_fminnum_like_nnan>>  =>  (V_MED3_F32_e64:{ *:[f32] } ?:{ *:[i32] }:$src0_mods, ?:{ *:[f32] }:$src0, ?:{ *:[i32] }:$src1_mods, ?:{ *:[f32] }:$src1, ?:{ *:[i32] }:$src2_mods, ?:{ *:[f32] }:$src2, 0:{ *:[i1] }, 0:{ *:[i32] })
        GIR_BuildMI, /*InsnID*/0, /*Opcode*/GIMT_Encode2(AMDGPU::V_MED3_F32_e64),
        GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/0, // DstI[vdst]
        GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(2), /*SubOperand*/1, // src0_mods
        GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(2), /*SubOperand*/0, // src0
        GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(1), /*SubOperand*/1, // src1_mods
        GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(1), /*SubOperand*/0, // src1
        GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/1, // src2_mods
        GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/0, // src2
        GIR_AddImm8, /*InsnID*/0, /*Imm*/0,
        GIR_AddImm8, /*InsnID*/0, /*Imm*/0,
        GIR_ConstrainSelectedInstOperands, /*InsnID*/0,
        GIR_EraseFromParent, /*InsnID*/0,
        // GIR_Coverage, 10463,
        GIR_Done,
      // Label 4367: @275227
      GIM_Try, /*On fail goto*//*Label 4368*/ GIMT_Encode4(275367), // Rule ID 10464 //
        GIM_CheckRegBankForClass, /*MI*/0, /*Op*/0, /*RC*/GIMT_Encode2(AMDGPU::VGPR_32RegClassID),
        GIM_RecordInsn, /*DefineMI*/1, /*MI*/0, /*OpIdx*/1, // MIs[1]
        GIM_CheckOpcode, /*MI*/1, GIMT_Encode2(TargetOpcode::G_FMAXNUM),
        GIM_CheckType, /*MI*/1, /*Op*/1, /*Type*/GILLT_s32,
        GIM_CheckType, /*MI*/1, /*Op*/2, /*Type*/GILLT_s32,
        GIM_RecordInsn, /*DefineMI*/2, /*MI*/1, /*OpIdx*/2, // MIs[2]
        GIM_CheckOpcode, /*MI*/2, GIMT_Encode2(TargetOpcode::G_FMINNUM_IEEE),
        GIM_CheckType, /*MI*/2, /*Op*/1, /*Type*/GILLT_s32,
        GIM_CheckType, /*MI*/2, /*Op*/2, /*Type*/GILLT_s32,
        GIM_RecordInsn, /*DefineMI*/3, /*MI*/0, /*OpIdx*/2, // MIs[3]
        GIM_CheckOpcode, /*MI*/3, GIMT_Encode2(TargetOpcode::G_FMAXNUM),
        // MIs[3] VOP3Mods:src1:src1_mods
        GIM_CheckIsSameOperand, /*MI*/3, /*OpIdx*/1, /*OtherMI*/2, /*OtherOpIdx*/1,
        // MIs[3] VOP3Mods:src0:src0_mods
        GIM_CheckIsSameOperand, /*MI*/3, /*OpIdx*/2, /*OtherMI*/2, /*OtherOpIdx*/2,
        GIM_CheckCxxInsnPredicate, /*MI*/0, /*FnId*/GIMT_Encode2(GICXXPred_MI_Predicate_fminnum_like_nnan),
        GIM_CheckIsSafeToFold, /*InsnID*/1,
        GIM_CheckIsSafeToFold, /*InsnID*/2,
        GIM_CheckIsSafeToFold, /*InsnID*/3,
        GIM_CheckComplexPattern, /*MI*/1, /*Op*/1, /*Renderer*/GIMT_Encode2(0), GIMT_Encode2(GICP_gi_vop3mods),
        GIM_CheckComplexPattern, /*MI*/2, /*Op*/1, /*Renderer*/GIMT_Encode2(1), GIMT_Encode2(GICP_gi_vop3mods),
        GIM_CheckComplexPattern, /*MI*/2, /*Op*/2, /*Renderer*/GIMT_Encode2(2), GIMT_Encode2(GICP_gi_vop3mods),
        // (fminnum:{ *:[f32] } (fmaxnum:{ *:[f32] } (VOP3Mods:{ *:[f32] } f32:{ *:[f32] }:$src2, i32:{ *:[i32] }:$src2_mods), (fminnum_ieee:{ *:[f32] } (VOP3Mods:{ *:[f32] } f32:{ *:[f32] }:$src1, i32:{ *:[i32] }:$src1_mods), (VOP3Mods:{ *:[f32] } f32:{ *:[f32] }:$src0, i32:{ *:[i32] }:$src0_mods))), (fmaxnum:{ *:[f32] } (VOP3Mods:{ *:[f32] } f32:{ *:[f32] }:$src1, i32:{ *:[i32] }:$src1_mods), (VOP3Mods:{ *:[f32] } f32:{ *:[f32] }:$src0, i32:{ *:[i32] }:$src0_mods)))<<P:Predicate_fminnum_like_nnan>>  =>  (V_MED3_F32_e64:{ *:[f32] } ?:{ *:[i32] }:$src0_mods, ?:{ *:[f32] }:$src0, ?:{ *:[i32] }:$src1_mods, ?:{ *:[f32] }:$src1, ?:{ *:[i32] }:$src2_mods, ?:{ *:[f32] }:$src2, 0:{ *:[i1] }, 0:{ *:[i32] })
        GIR_BuildMI, /*InsnID*/0, /*Opcode*/GIMT_Encode2(AMDGPU::V_MED3_F32_e64),
        GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/0, // DstI[vdst]
        GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(2), /*SubOperand*/1, // src0_mods
        GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(2), /*SubOperand*/0, // src0
        GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(1), /*SubOperand*/1, // src1_mods
        GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(1), /*SubOperand*/0, // src1
        GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/1, // src2_mods
        GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/0, // src2
        GIR_AddImm8, /*InsnID*/0, /*Imm*/0,
        GIR_AddImm8, /*InsnID*/0, /*Imm*/0,
        GIR_ConstrainSelectedInstOperands, /*InsnID*/0,
        GIR_EraseFromParent, /*InsnID*/0,
        // GIR_Coverage, 10464,
        GIR_Done,
      // Label 4368: @275367
      GIM_Try, /*On fail goto*//*Label 4369*/ GIMT_Encode4(275507), // Rule ID 10401 //
        GIM_CheckRegBankForClass, /*MI*/0, /*Op*/0, /*RC*/GIMT_Encode2(AMDGPU::VGPR_32RegClassID),
        GIM_RecordInsn, /*DefineMI*/1, /*MI*/0, /*OpIdx*/1, // MIs[1]
        GIM_CheckOpcode, /*MI*/1, GIMT_Encode2(TargetOpcode::G_FMAXNUM),
        GIM_CheckType, /*MI*/1, /*Op*/1, /*Type*/GILLT_s32,
        GIM_CheckType, /*MI*/1, /*Op*/2, /*Type*/GILLT_s32,
        GIM_RecordInsn, /*DefineMI*/2, /*MI*/1, /*OpIdx*/2, // MIs[2]
        GIM_CheckOpcode, /*MI*/2, GIMT_Encode2(TargetOpcode::G_FMINNUM_IEEE),
        GIM_CheckType, /*MI*/2, /*Op*/1, /*Type*/GILLT_s32,
        GIM_CheckType, /*MI*/2, /*Op*/2, /*Type*/GILLT_s32,
        GIM_RecordInsn, /*DefineMI*/3, /*MI*/0, /*OpIdx*/2, // MIs[3]
        GIM_CheckOpcode, /*MI*/3, GIMT_Encode2(TargetOpcode::G_FMAXNUM_IEEE),
        // MIs[3] VOP3Mods:src0:src0_mods
        GIM_CheckIsSameOperand, /*MI*/3, /*OpIdx*/1, /*OtherMI*/2, /*OtherOpIdx*/1,
        // MIs[3] VOP3Mods:src1:src1_mods
        GIM_CheckIsSameOperand, /*MI*/3, /*OpIdx*/2, /*OtherMI*/2, /*OtherOpIdx*/2,
        GIM_CheckCxxInsnPredicate, /*MI*/0, /*FnId*/GIMT_Encode2(GICXXPred_MI_Predicate_fminnum_like_nnan),
        GIM_CheckIsSafeToFold, /*InsnID*/1,
        GIM_CheckIsSafeToFold, /*InsnID*/2,
        GIM_CheckIsSafeToFold, /*InsnID*/3,
        GIM_CheckComplexPattern, /*MI*/1, /*Op*/1, /*Renderer*/GIMT_Encode2(0), GIMT_Encode2(GICP_gi_vop3mods),
        GIM_CheckComplexPattern, /*MI*/2, /*Op*/1, /*Renderer*/GIMT_Encode2(1), GIMT_Encode2(GICP_gi_vop3mods),
        GIM_CheckComplexPattern, /*MI*/2, /*Op*/2, /*Renderer*/GIMT_Encode2(2), GIMT_Encode2(GICP_gi_vop3mods),
        // (fminnum:{ *:[f32] } (fmaxnum:{ *:[f32] } (VOP3Mods:{ *:[f32] } f32:{ *:[f32] }:$src2, i32:{ *:[i32] }:$src2_mods), (fminnum_ieee:{ *:[f32] } (VOP3Mods:{ *:[f32] } f32:{ *:[f32] }:$src0, i32:{ *:[i32] }:$src0_mods), (VOP3Mods:{ *:[f32] } f32:{ *:[f32] }:$src1, i32:{ *:[i32] }:$src1_mods))), (fmaxnum_ieee:{ *:[f32] } (VOP3Mods:{ *:[f32] } f32:{ *:[f32] }:$src0, i32:{ *:[i32] }:$src0_mods), (VOP3Mods:{ *:[f32] } f32:{ *:[f32] }:$src1, i32:{ *:[i32] }:$src1_mods)))<<P:Predicate_fminnum_like_nnan>>  =>  (V_MED3_F32_e64:{ *:[f32] } ?:{ *:[i32] }:$src0_mods, ?:{ *:[f32] }:$src0, ?:{ *:[i32] }:$src1_mods, ?:{ *:[f32] }:$src1, ?:{ *:[i32] }:$src2_mods, ?:{ *:[f32] }:$src2, 0:{ *:[i1] }, 0:{ *:[i32] })
        GIR_BuildMI, /*InsnID*/0, /*Opcode*/GIMT_Encode2(AMDGPU::V_MED3_F32_e64),
        GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/0, // DstI[vdst]
        GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(1), /*SubOperand*/1, // src0_mods
        GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(1), /*SubOperand*/0, // src0
        GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(2), /*SubOperand*/1, // src1_mods
        GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(2), /*SubOperand*/0, // src1
        GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/1, // src2_mods
        GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/0, // src2
        GIR_AddImm8, /*InsnID*/0, /*Imm*/0,
        GIR_AddImm8, /*InsnID*/0, /*Imm*/0,
        GIR_ConstrainSelectedInstOperands, /*InsnID*/0,
        GIR_EraseFromParent, /*InsnID*/0,
        // GIR_Coverage, 10401,
        GIR_Done,
      // Label 4369: @275507
      GIM_Try, /*On fail goto*//*Label 4370*/ GIMT_Encode4(275647), // Rule ID 10402 //
        GIM_CheckRegBankForClass, /*MI*/0, /*Op*/0, /*RC*/GIMT_Encode2(AMDGPU::VGPR_32RegClassID),
        GIM_RecordInsn, /*DefineMI*/1, /*MI*/0, /*OpIdx*/1, // MIs[1]
        GIM_CheckOpcode, /*MI*/1, GIMT_Encode2(TargetOpcode::G_FMAXNUM),
        GIM_CheckType, /*MI*/1, /*Op*/1, /*Type*/GILLT_s32,
        GIM_CheckType, /*MI*/1, /*Op*/2, /*Type*/GILLT_s32,
        GIM_RecordInsn, /*DefineMI*/2, /*MI*/1, /*OpIdx*/2, // MIs[2]
        GIM_CheckOpcode, /*MI*/2, GIMT_Encode2(TargetOpcode::G_FMINNUM_IEEE),
        GIM_CheckType, /*MI*/2, /*Op*/1, /*Type*/GILLT_s32,
        GIM_CheckType, /*MI*/2, /*Op*/2, /*Type*/GILLT_s32,
        GIM_RecordInsn, /*DefineMI*/3, /*MI*/0, /*OpIdx*/2, // MIs[3]
        GIM_CheckOpcode, /*MI*/3, GIMT_Encode2(TargetOpcode::G_FMAXNUM_IEEE),
        // MIs[3] VOP3Mods:src1:src1_mods
        GIM_CheckIsSameOperand, /*MI*/3, /*OpIdx*/1, /*OtherMI*/2, /*OtherOpIdx*/2,
        // MIs[3] VOP3Mods:src0:src0_mods
        GIM_CheckIsSameOperand, /*MI*/3, /*OpIdx*/2, /*OtherMI*/2, /*OtherOpIdx*/1,
        GIM_CheckCxxInsnPredicate, /*MI*/0, /*FnId*/GIMT_Encode2(GICXXPred_MI_Predicate_fminnum_like_nnan),
        GIM_CheckIsSafeToFold, /*InsnID*/1,
        GIM_CheckIsSafeToFold, /*InsnID*/2,
        GIM_CheckIsSafeToFold, /*InsnID*/3,
        GIM_CheckComplexPattern, /*MI*/1, /*Op*/1, /*Renderer*/GIMT_Encode2(0), GIMT_Encode2(GICP_gi_vop3mods),
        GIM_CheckComplexPattern, /*MI*/2, /*Op*/1, /*Renderer*/GIMT_Encode2(1), GIMT_Encode2(GICP_gi_vop3mods),
        GIM_CheckComplexPattern, /*MI*/2, /*Op*/2, /*Renderer*/GIMT_Encode2(2), GIMT_Encode2(GICP_gi_vop3mods),
        // (fminnum:{ *:[f32] } (fmaxnum:{ *:[f32] } (VOP3Mods:{ *:[f32] } f32:{ *:[f32] }:$src2, i32:{ *:[i32] }:$src2_mods), (fminnum_ieee:{ *:[f32] } (VOP3Mods:{ *:[f32] } f32:{ *:[f32] }:$src0, i32:{ *:[i32] }:$src0_mods), (VOP3Mods:{ *:[f32] } f32:{ *:[f32] }:$src1, i32:{ *:[i32] }:$src1_mods))), (fmaxnum_ieee:{ *:[f32] } (VOP3Mods:{ *:[f32] } f32:{ *:[f32] }:$src1, i32:{ *:[i32] }:$src1_mods), (VOP3Mods:{ *:[f32] } f32:{ *:[f32] }:$src0, i32:{ *:[i32] }:$src0_mods)))<<P:Predicate_fminnum_like_nnan>>  =>  (V_MED3_F32_e64:{ *:[f32] } ?:{ *:[i32] }:$src0_mods, ?:{ *:[f32] }:$src0, ?:{ *:[i32] }:$src1_mods, ?:{ *:[f32] }:$src1, ?:{ *:[i32] }:$src2_mods, ?:{ *:[f32] }:$src2, 0:{ *:[i1] }, 0:{ *:[i32] })
        GIR_BuildMI, /*InsnID*/0, /*Opcode*/GIMT_Encode2(AMDGPU::V_MED3_F32_e64),
        GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/0, // DstI[vdst]
        GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(1), /*SubOperand*/1, // src0_mods
        GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(1), /*SubOperand*/0, // src0
        GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(2), /*SubOperand*/1, // src1_mods
        GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(2), /*SubOperand*/0, // src1
        GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/1, // src2_mods
        GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/0, // src2
        GIR_AddImm8, /*InsnID*/0, /*Imm*/0,
        GIR_AddImm8, /*InsnID*/0, /*Imm*/0,
        GIR_ConstrainSelectedInstOperands, /*InsnID*/0,
        GIR_EraseFromParent, /*InsnID*/0,
        // GIR_Coverage, 10402,
        GIR_Done,
      // Label 4370: @275647
      GIM_Try, /*On fail goto*//*Label 4371*/ GIMT_Encode4(275787), // Rule ID 10403 //
        GIM_CheckRegBankForClass, /*MI*/0, /*Op*/0, /*RC*/GIMT_Encode2(AMDGPU::VGPR_32RegClassID),
        GIM_RecordInsn, /*DefineMI*/1, /*MI*/0, /*OpIdx*/1, // MIs[1]
        GIM_CheckOpcode, /*MI*/1, GIMT_Encode2(TargetOpcode::G_FMAXNUM),
        GIM_CheckType, /*MI*/1, /*Op*/1, /*Type*/GILLT_s32,
        GIM_CheckType, /*MI*/1, /*Op*/2, /*Type*/GILLT_s32,
        GIM_RecordInsn, /*DefineMI*/2, /*MI*/1, /*OpIdx*/2, // MIs[2]
        GIM_CheckOpcode, /*MI*/2, GIMT_Encode2(TargetOpcode::G_FMINNUM_IEEE),
        GIM_CheckType, /*MI*/2, /*Op*/1, /*Type*/GILLT_s32,
        GIM_CheckType, /*MI*/2, /*Op*/2, /*Type*/GILLT_s32,
        GIM_RecordInsn, /*DefineMI*/3, /*MI*/0, /*OpIdx*/2, // MIs[3]
        GIM_CheckOpcode, /*MI*/3, GIMT_Encode2(TargetOpcode::G_FMAXNUM_IEEE),
        // MIs[3] VOP3Mods:src0:src0_mods
        GIM_CheckIsSameOperand, /*MI*/3, /*OpIdx*/1, /*OtherMI*/2, /*OtherOpIdx*/2,
        // MIs[3] VOP3Mods:src1:src1_mods
        GIM_CheckIsSameOperand, /*MI*/3, /*OpIdx*/2, /*OtherMI*/2, /*OtherOpIdx*/1,
        GIM_CheckCxxInsnPredicate, /*MI*/0, /*FnId*/GIMT_Encode2(GICXXPred_MI_Predicate_fminnum_like_nnan),
        GIM_CheckIsSafeToFold, /*InsnID*/1,
        GIM_CheckIsSafeToFold, /*InsnID*/2,
        GIM_CheckIsSafeToFold, /*InsnID*/3,
        GIM_CheckComplexPattern, /*MI*/1, /*Op*/1, /*Renderer*/GIMT_Encode2(0), GIMT_Encode2(GICP_gi_vop3mods),
        GIM_CheckComplexPattern, /*MI*/2, /*Op*/1, /*Renderer*/GIMT_Encode2(1), GIMT_Encode2(GICP_gi_vop3mods),
        GIM_CheckComplexPattern, /*MI*/2, /*Op*/2, /*Renderer*/GIMT_Encode2(2), GIMT_Encode2(GICP_gi_vop3mods),
        // (fminnum:{ *:[f32] } (fmaxnum:{ *:[f32] } (VOP3Mods:{ *:[f32] } f32:{ *:[f32] }:$src2, i32:{ *:[i32] }:$src2_mods), (fminnum_ieee:{ *:[f32] } (VOP3Mods:{ *:[f32] } f32:{ *:[f32] }:$src1, i32:{ *:[i32] }:$src1_mods), (VOP3Mods:{ *:[f32] } f32:{ *:[f32] }:$src0, i32:{ *:[i32] }:$src0_mods))), (fmaxnum_ieee:{ *:[f32] } (VOP3Mods:{ *:[f32] } f32:{ *:[f32] }:$src0, i32:{ *:[i32] }:$src0_mods), (VOP3Mods:{ *:[f32] } f32:{ *:[f32] }:$src1, i32:{ *:[i32] }:$src1_mods)))<<P:Predicate_fminnum_like_nnan>>  =>  (V_MED3_F32_e64:{ *:[f32] } ?:{ *:[i32] }:$src0_mods, ?:{ *:[f32] }:$src0, ?:{ *:[i32] }:$src1_mods, ?:{ *:[f32] }:$src1, ?:{ *:[i32] }:$src2_mods, ?:{ *:[f32] }:$src2, 0:{ *:[i1] }, 0:{ *:[i32] })
        GIR_BuildMI, /*InsnID*/0, /*Opcode*/GIMT_Encode2(AMDGPU::V_MED3_F32_e64),
        GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/0, // DstI[vdst]
        GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(2), /*SubOperand*/1, // src0_mods
        GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(2), /*SubOperand*/0, // src0
        GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(1), /*SubOperand*/1, // src1_mods
        GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(1), /*SubOperand*/0, // src1
        GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/1, // src2_mods
        GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/0, // src2
        GIR_AddImm8, /*InsnID*/0, /*Imm*/0,
        GIR_AddImm8, /*InsnID*/0, /*Imm*/0,
        GIR_ConstrainSelectedInstOperands, /*InsnID*/0,
        GIR_EraseFromParent, /*InsnID*/0,
        // GIR_Coverage, 10403,
        GIR_Done,
      // Label 4371: @275787
      GIM_Try, /*On fail goto*//*Label 4372*/ GIMT_Encode4(275927), // Rule ID 10404 //
        GIM_CheckRegBankForClass, /*MI*/0, /*Op*/0, /*RC*/GIMT_Encode2(AMDGPU::VGPR_32RegClassID),
        GIM_RecordInsn, /*DefineMI*/1, /*MI*/0, /*OpIdx*/1, // MIs[1]
        GIM_CheckOpcode, /*MI*/1, GIMT_Encode2(TargetOpcode::G_FMAXNUM),
        GIM_CheckType, /*MI*/1, /*Op*/1, /*Type*/GILLT_s32,
        GIM_CheckType, /*MI*/1, /*Op*/2, /*Type*/GILLT_s32,
        GIM_RecordInsn, /*DefineMI*/2, /*MI*/1, /*OpIdx*/2, // MIs[2]
        GIM_CheckOpcode, /*MI*/2, GIMT_Encode2(TargetOpcode::G_FMINNUM_IEEE),
        GIM_CheckType, /*MI*/2, /*Op*/1, /*Type*/GILLT_s32,
        GIM_CheckType, /*MI*/2, /*Op*/2, /*Type*/GILLT_s32,
        GIM_RecordInsn, /*DefineMI*/3, /*MI*/0, /*OpIdx*/2, // MIs[3]
        GIM_CheckOpcode, /*MI*/3, GIMT_Encode2(TargetOpcode::G_FMAXNUM_IEEE),
        // MIs[3] VOP3Mods:src1:src1_mods
        GIM_CheckIsSameOperand, /*MI*/3, /*OpIdx*/1, /*OtherMI*/2, /*OtherOpIdx*/1,
        // MIs[3] VOP3Mods:src0:src0_mods
        GIM_CheckIsSameOperand, /*MI*/3, /*OpIdx*/2, /*OtherMI*/2, /*OtherOpIdx*/2,
        GIM_CheckCxxInsnPredicate, /*MI*/0, /*FnId*/GIMT_Encode2(GICXXPred_MI_Predicate_fminnum_like_nnan),
        GIM_CheckIsSafeToFold, /*InsnID*/1,
        GIM_CheckIsSafeToFold, /*InsnID*/2,
        GIM_CheckIsSafeToFold, /*InsnID*/3,
        GIM_CheckComplexPattern, /*MI*/1, /*Op*/1, /*Renderer*/GIMT_Encode2(0), GIMT_Encode2(GICP_gi_vop3mods),
        GIM_CheckComplexPattern, /*MI*/2, /*Op*/1, /*Renderer*/GIMT_Encode2(1), GIMT_Encode2(GICP_gi_vop3mods),
        GIM_CheckComplexPattern, /*MI*/2, /*Op*/2, /*Renderer*/GIMT_Encode2(2), GIMT_Encode2(GICP_gi_vop3mods),
        // (fminnum:{ *:[f32] } (fmaxnum:{ *:[f32] } (VOP3Mods:{ *:[f32] } f32:{ *:[f32] }:$src2, i32:{ *:[i32] }:$src2_mods), (fminnum_ieee:{ *:[f32] } (VOP3Mods:{ *:[f32] } f32:{ *:[f32] }:$src1, i32:{ *:[i32] }:$src1_mods), (VOP3Mods:{ *:[f32] } f32:{ *:[f32] }:$src0, i32:{ *:[i32] }:$src0_mods))), (fmaxnum_ieee:{ *:[f32] } (VOP3Mods:{ *:[f32] } f32:{ *:[f32] }:$src1, i32:{ *:[i32] }:$src1_mods), (VOP3Mods:{ *:[f32] } f32:{ *:[f32] }:$src0, i32:{ *:[i32] }:$src0_mods)))<<P:Predicate_fminnum_like_nnan>>  =>  (V_MED3_F32_e64:{ *:[f32] } ?:{ *:[i32] }:$src0_mods, ?:{ *:[f32] }:$src0, ?:{ *:[i32] }:$src1_mods, ?:{ *:[f32] }:$src1, ?:{ *:[i32] }:$src2_mods, ?:{ *:[f32] }:$src2, 0:{ *:[i1] }, 0:{ *:[i32] })
        GIR_BuildMI, /*InsnID*/0, /*Opcode*/GIMT_Encode2(AMDGPU::V_MED3_F32_e64),
        GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/0, // DstI[vdst]
        GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(2), /*SubOperand*/1, // src0_mods
        GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(2), /*SubOperand*/0, // src0
        GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(1), /*SubOperand*/1, // src1_mods
        GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(1), /*SubOperand*/0, // src1
        GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/1, // src2_mods
        GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/0, // src2
        GIR_AddImm8, /*InsnID*/0, /*Imm*/0,
        GIR_AddImm8, /*InsnID*/0, /*Imm*/0,
        GIR_ConstrainSelectedInstOperands, /*InsnID*/0,
        GIR_EraseFromParent, /*InsnID*/0,
        // GIR_Coverage, 10404,
        GIR_Done,
      // Label 4372: @275927
      GIM_Try, /*On fail goto*//*Label 4373*/ GIMT_Encode4(276067), // Rule ID 10472 //
        GIM_CheckRegBankForClass, /*MI*/0, /*Op*/0, /*RC*/GIMT_Encode2(AMDGPU::VGPR_32RegClassID),
        GIM_RecordInsn, /*DefineMI*/1, /*MI*/0, /*OpIdx*/1, // MIs[1]
        GIM_CheckOpcode, /*MI*/1, GIMT_Encode2(TargetOpcode::G_FMAXNUM),
        GIM_CheckType, /*MI*/1, /*Op*/1, /*Type*/GILLT_s32,
        GIM_CheckType, /*MI*/1, /*Op*/2, /*Type*/GILLT_s32,
        GIM_RecordInsn, /*DefineMI*/2, /*MI*/1, /*OpIdx*/1, // MIs[2]
        GIM_CheckOpcode, /*MI*/2, GIMT_Encode2(TargetOpcode::G_FMINNUM),
        GIM_CheckType, /*MI*/2, /*Op*/1, /*Type*/GILLT_s32,
        GIM_CheckType, /*MI*/2, /*Op*/2, /*Type*/GILLT_s32,
        GIM_RecordInsn, /*DefineMI*/3, /*MI*/0, /*OpIdx*/2, // MIs[3]
        GIM_CheckOpcode, /*MI*/3, GIMT_Encode2(TargetOpcode::G_FMAXNUM),
        // MIs[3] VOP3Mods:src0:src0_mods
        GIM_CheckIsSameOperand, /*MI*/3, /*OpIdx*/1, /*OtherMI*/2, /*OtherOpIdx*/1,
        // MIs[3] VOP3Mods:src1:src1_mods
        GIM_CheckIsSameOperand, /*MI*/3, /*OpIdx*/2, /*OtherMI*/2, /*OtherOpIdx*/2,
        GIM_CheckCxxInsnPredicate, /*MI*/0, /*FnId*/GIMT_Encode2(GICXXPred_MI_Predicate_fminnum_like_nnan),
        GIM_CheckIsSafeToFold, /*InsnID*/1,
        GIM_CheckIsSafeToFold, /*InsnID*/2,
        GIM_CheckIsSafeToFold, /*InsnID*/3,
        GIM_CheckComplexPattern, /*MI*/1, /*Op*/2, /*Renderer*/GIMT_Encode2(2), GIMT_Encode2(GICP_gi_vop3mods),
        GIM_CheckComplexPattern, /*MI*/2, /*Op*/1, /*Renderer*/GIMT_Encode2(0), GIMT_Encode2(GICP_gi_vop3mods),
        GIM_CheckComplexPattern, /*MI*/2, /*Op*/2, /*Renderer*/GIMT_Encode2(1), GIMT_Encode2(GICP_gi_vop3mods),
        // (fminnum:{ *:[f32] } (fmaxnum:{ *:[f32] } (fminnum:{ *:[f32] } (VOP3Mods:{ *:[f32] } f32:{ *:[f32] }:$src0, i32:{ *:[i32] }:$src0_mods), (VOP3Mods:{ *:[f32] } f32:{ *:[f32] }:$src1, i32:{ *:[i32] }:$src1_mods)), (VOP3Mods:{ *:[f32] } f32:{ *:[f32] }:$src2, i32:{ *:[i32] }:$src2_mods)), (fmaxnum:{ *:[f32] } (VOP3Mods:{ *:[f32] } f32:{ *:[f32] }:$src0, i32:{ *:[i32] }:$src0_mods), (VOP3Mods:{ *:[f32] } f32:{ *:[f32] }:$src1, i32:{ *:[i32] }:$src1_mods)))<<P:Predicate_fminnum_like_nnan>>  =>  (V_MED3_F32_e64:{ *:[f32] } ?:{ *:[i32] }:$src0_mods, ?:{ *:[f32] }:$src0, ?:{ *:[i32] }:$src1_mods, ?:{ *:[f32] }:$src1, ?:{ *:[i32] }:$src2_mods, ?:{ *:[f32] }:$src2, 0:{ *:[i1] }, 0:{ *:[i32] })
        GIR_BuildMI, /*InsnID*/0, /*Opcode*/GIMT_Encode2(AMDGPU::V_MED3_F32_e64),
        GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/0, // DstI[vdst]
        GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/1, // src0_mods
        GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/0, // src0
        GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(1), /*SubOperand*/1, // src1_mods
        GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(1), /*SubOperand*/0, // src1
        GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(2), /*SubOperand*/1, // src2_mods
        GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(2), /*SubOperand*/0, // src2
        GIR_AddImm8, /*InsnID*/0, /*Imm*/0,
        GIR_AddImm8, /*InsnID*/0, /*Imm*/0,
        GIR_ConstrainSelectedInstOperands, /*InsnID*/0,
        GIR_EraseFromParent, /*InsnID*/0,
        // GIR_Coverage, 10472,
        GIR_Done,
      // Label 4373: @276067
      GIM_Try, /*On fail goto*//*Label 4374*/ GIMT_Encode4(276207), // Rule ID 10473 //
        GIM_CheckRegBankForClass, /*MI*/0, /*Op*/0, /*RC*/GIMT_Encode2(AMDGPU::VGPR_32RegClassID),
        GIM_RecordInsn, /*DefineMI*/1, /*MI*/0, /*OpIdx*/1, // MIs[1]
        GIM_CheckOpcode, /*MI*/1, GIMT_Encode2(TargetOpcode::G_FMAXNUM),
        GIM_CheckType, /*MI*/1, /*Op*/1, /*Type*/GILLT_s32,
        GIM_CheckType, /*MI*/1, /*Op*/2, /*Type*/GILLT_s32,
        GIM_RecordInsn, /*DefineMI*/2, /*MI*/1, /*OpIdx*/1, // MIs[2]
        GIM_CheckOpcode, /*MI*/2, GIMT_Encode2(TargetOpcode::G_FMINNUM),
        GIM_CheckType, /*MI*/2, /*Op*/1, /*Type*/GILLT_s32,
        GIM_CheckType, /*MI*/2, /*Op*/2, /*Type*/GILLT_s32,
        GIM_RecordInsn, /*DefineMI*/3, /*MI*/0, /*OpIdx*/2, // MIs[3]
        GIM_CheckOpcode, /*MI*/3, GIMT_Encode2(TargetOpcode::G_FMAXNUM),
        // MIs[3] VOP3Mods:src1:src1_mods
        GIM_CheckIsSameOperand, /*MI*/3, /*OpIdx*/1, /*OtherMI*/2, /*OtherOpIdx*/2,
        // MIs[3] VOP3Mods:src0:src0_mods
        GIM_CheckIsSameOperand, /*MI*/3, /*OpIdx*/2, /*OtherMI*/2, /*OtherOpIdx*/1,
        GIM_CheckCxxInsnPredicate, /*MI*/0, /*FnId*/GIMT_Encode2(GICXXPred_MI_Predicate_fminnum_like_nnan),
        GIM_CheckIsSafeToFold, /*InsnID*/1,
        GIM_CheckIsSafeToFold, /*InsnID*/2,
        GIM_CheckIsSafeToFold, /*InsnID*/3,
        GIM_CheckComplexPattern, /*MI*/1, /*Op*/2, /*Renderer*/GIMT_Encode2(2), GIMT_Encode2(GICP_gi_vop3mods),
        GIM_CheckComplexPattern, /*MI*/2, /*Op*/1, /*Renderer*/GIMT_Encode2(0), GIMT_Encode2(GICP_gi_vop3mods),
        GIM_CheckComplexPattern, /*MI*/2, /*Op*/2, /*Renderer*/GIMT_Encode2(1), GIMT_Encode2(GICP_gi_vop3mods),
        // (fminnum:{ *:[f32] } (fmaxnum:{ *:[f32] } (fminnum:{ *:[f32] } (VOP3Mods:{ *:[f32] } f32:{ *:[f32] }:$src0, i32:{ *:[i32] }:$src0_mods), (VOP3Mods:{ *:[f32] } f32:{ *:[f32] }:$src1, i32:{ *:[i32] }:$src1_mods)), (VOP3Mods:{ *:[f32] } f32:{ *:[f32] }:$src2, i32:{ *:[i32] }:$src2_mods)), (fmaxnum:{ *:[f32] } (VOP3Mods:{ *:[f32] } f32:{ *:[f32] }:$src1, i32:{ *:[i32] }:$src1_mods), (VOP3Mods:{ *:[f32] } f32:{ *:[f32] }:$src0, i32:{ *:[i32] }:$src0_mods)))<<P:Predicate_fminnum_like_nnan>>  =>  (V_MED3_F32_e64:{ *:[f32] } ?:{ *:[i32] }:$src0_mods, ?:{ *:[f32] }:$src0, ?:{ *:[i32] }:$src1_mods, ?:{ *:[f32] }:$src1, ?:{ *:[i32] }:$src2_mods, ?:{ *:[f32] }:$src2, 0:{ *:[i1] }, 0:{ *:[i32] })
        GIR_BuildMI, /*InsnID*/0, /*Opcode*/GIMT_Encode2(AMDGPU::V_MED3_F32_e64),
        GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/0, // DstI[vdst]
        GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/1, // src0_mods
        GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/0, // src0
        GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(1), /*SubOperand*/1, // src1_mods
        GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(1), /*SubOperand*/0, // src1
        GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(2), /*SubOperand*/1, // src2_mods
        GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(2), /*SubOperand*/0, // src2
        GIR_AddImm8, /*InsnID*/0, /*Imm*/0,
        GIR_AddImm8, /*InsnID*/0, /*Imm*/0,
        GIR_ConstrainSelectedInstOperands, /*InsnID*/0,
        GIR_EraseFromParent, /*InsnID*/0,
        // GIR_Coverage, 10473,
        GIR_Done,
      // Label 4374: @276207
      GIM_Try, /*On fail goto*//*Label 4375*/ GIMT_Encode4(276347), // Rule ID 10474 //
        GIM_CheckRegBankForClass, /*MI*/0, /*Op*/0, /*RC*/GIMT_Encode2(AMDGPU::VGPR_32RegClassID),
        GIM_RecordInsn, /*DefineMI*/1, /*MI*/0, /*OpIdx*/1, // MIs[1]
        GIM_CheckOpcode, /*MI*/1, GIMT_Encode2(TargetOpcode::G_FMAXNUM),
        GIM_CheckType, /*MI*/1, /*Op*/1, /*Type*/GILLT_s32,
        GIM_CheckType, /*MI*/1, /*Op*/2, /*Type*/GILLT_s32,
        GIM_RecordInsn, /*DefineMI*/2, /*MI*/1, /*OpIdx*/1, // MIs[2]
        GIM_CheckOpcode, /*MI*/2, GIMT_Encode2(TargetOpcode::G_FMINNUM),
        GIM_CheckType, /*MI*/2, /*Op*/1, /*Type*/GILLT_s32,
        GIM_CheckType, /*MI*/2, /*Op*/2, /*Type*/GILLT_s32,
        GIM_RecordInsn, /*DefineMI*/3, /*MI*/0, /*OpIdx*/2, // MIs[3]
        GIM_CheckOpcode, /*MI*/3, GIMT_Encode2(TargetOpcode::G_FMAXNUM),
        // MIs[3] VOP3Mods:src0:src0_mods
        GIM_CheckIsSameOperand, /*MI*/3, /*OpIdx*/1, /*OtherMI*/2, /*OtherOpIdx*/2,
        // MIs[3] VOP3Mods:src1:src1_mods
        GIM_CheckIsSameOperand, /*MI*/3, /*OpIdx*/2, /*OtherMI*/2, /*OtherOpIdx*/1,
        GIM_CheckCxxInsnPredicate, /*MI*/0, /*FnId*/GIMT_Encode2(GICXXPred_MI_Predicate_fminnum_like_nnan),
        GIM_CheckIsSafeToFold, /*InsnID*/1,
        GIM_CheckIsSafeToFold, /*InsnID*/2,
        GIM_CheckIsSafeToFold, /*InsnID*/3,
        GIM_CheckComplexPattern, /*MI*/1, /*Op*/2, /*Renderer*/GIMT_Encode2(2), GIMT_Encode2(GICP_gi_vop3mods),
        GIM_CheckComplexPattern, /*MI*/2, /*Op*/1, /*Renderer*/GIMT_Encode2(0), GIMT_Encode2(GICP_gi_vop3mods),
        GIM_CheckComplexPattern, /*MI*/2, /*Op*/2, /*Renderer*/GIMT_Encode2(1), GIMT_Encode2(GICP_gi_vop3mods),
        // (fminnum:{ *:[f32] } (fmaxnum:{ *:[f32] } (fminnum:{ *:[f32] } (VOP3Mods:{ *:[f32] } f32:{ *:[f32] }:$src1, i32:{ *:[i32] }:$src1_mods), (VOP3Mods:{ *:[f32] } f32:{ *:[f32] }:$src0, i32:{ *:[i32] }:$src0_mods)), (VOP3Mods:{ *:[f32] } f32:{ *:[f32] }:$src2, i32:{ *:[i32] }:$src2_mods)), (fmaxnum:{ *:[f32] } (VOP3Mods:{ *:[f32] } f32:{ *:[f32] }:$src0, i32:{ *:[i32] }:$src0_mods), (VOP3Mods:{ *:[f32] } f32:{ *:[f32] }:$src1, i32:{ *:[i32] }:$src1_mods)))<<P:Predicate_fminnum_like_nnan>>  =>  (V_MED3_F32_e64:{ *:[f32] } ?:{ *:[i32] }:$src0_mods, ?:{ *:[f32] }:$src0, ?:{ *:[i32] }:$src1_mods, ?:{ *:[f32] }:$src1, ?:{ *:[i32] }:$src2_mods, ?:{ *:[f32] }:$src2, 0:{ *:[i1] }, 0:{ *:[i32] })
        GIR_BuildMI, /*InsnID*/0, /*Opcode*/GIMT_Encode2(AMDGPU::V_MED3_F32_e64),
        GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/0, // DstI[vdst]
        GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(1), /*SubOperand*/1, // src0_mods
        GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(1), /*SubOperand*/0, // src0
        GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/1, // src1_mods
        GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/0, // src1
        GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(2), /*SubOperand*/1, // src2_mods
        GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(2), /*SubOperand*/0, // src2
        GIR_AddImm8, /*InsnID*/0, /*Imm*/0,
        GIR_AddImm8, /*InsnID*/0, /*Imm*/0,
        GIR_ConstrainSelectedInstOperands, /*InsnID*/0,
        GIR_EraseFromParent, /*InsnID*/0,
        // GIR_Coverage, 10474,
        GIR_Done,
      // Label 4375: @276347
      GIM_Try, /*On fail goto*//*Label 4376*/ GIMT_Encode4(276487), // Rule ID 10475 //
        GIM_CheckRegBankForClass, /*MI*/0, /*Op*/0, /*RC*/GIMT_Encode2(AMDGPU::VGPR_32RegClassID),
        GIM_RecordInsn, /*DefineMI*/1, /*MI*/0, /*OpIdx*/1, // MIs[1]
        GIM_CheckOpcode, /*MI*/1, GIMT_Encode2(TargetOpcode::G_FMAXNUM),
        GIM_CheckType, /*MI*/1, /*Op*/1, /*Type*/GILLT_s32,
        GIM_CheckType, /*MI*/1, /*Op*/2, /*Type*/GILLT_s32,
        GIM_RecordInsn, /*DefineMI*/2, /*MI*/1, /*OpIdx*/1, // MIs[2]
        GIM_CheckOpcode, /*MI*/2, GIMT_Encode2(TargetOpcode::G_FMINNUM),
        GIM_CheckType, /*MI*/2, /*Op*/1, /*Type*/GILLT_s32,
        GIM_CheckType, /*MI*/2, /*Op*/2, /*Type*/GILLT_s32,
        GIM_RecordInsn, /*DefineMI*/3, /*MI*/0, /*OpIdx*/2, // MIs[3]
        GIM_CheckOpcode, /*MI*/3, GIMT_Encode2(TargetOpcode::G_FMAXNUM),
        // MIs[3] VOP3Mods:src1:src1_mods
        GIM_CheckIsSameOperand, /*MI*/3, /*OpIdx*/1, /*OtherMI*/2, /*OtherOpIdx*/1,
        // MIs[3] VOP3Mods:src0:src0_mods
        GIM_CheckIsSameOperand, /*MI*/3, /*OpIdx*/2, /*OtherMI*/2, /*OtherOpIdx*/2,
        GIM_CheckCxxInsnPredicate, /*MI*/0, /*FnId*/GIMT_Encode2(GICXXPred_MI_Predicate_fminnum_like_nnan),
        GIM_CheckIsSafeToFold, /*InsnID*/1,
        GIM_CheckIsSafeToFold, /*InsnID*/2,
        GIM_CheckIsSafeToFold, /*InsnID*/3,
        GIM_CheckComplexPattern, /*MI*/1, /*Op*/2, /*Renderer*/GIMT_Encode2(2), GIMT_Encode2(GICP_gi_vop3mods),
        GIM_CheckComplexPattern, /*MI*/2, /*Op*/1, /*Renderer*/GIMT_Encode2(0), GIMT_Encode2(GICP_gi_vop3mods),
        GIM_CheckComplexPattern, /*MI*/2, /*Op*/2, /*Renderer*/GIMT_Encode2(1), GIMT_Encode2(GICP_gi_vop3mods),
        // (fminnum:{ *:[f32] } (fmaxnum:{ *:[f32] } (fminnum:{ *:[f32] } (VOP3Mods:{ *:[f32] } f32:{ *:[f32] }:$src1, i32:{ *:[i32] }:$src1_mods), (VOP3Mods:{ *:[f32] } f32:{ *:[f32] }:$src0, i32:{ *:[i32] }:$src0_mods)), (VOP3Mods:{ *:[f32] } f32:{ *:[f32] }:$src2, i32:{ *:[i32] }:$src2_mods)), (fmaxnum:{ *:[f32] } (VOP3Mods:{ *:[f32] } f32:{ *:[f32] }:$src1, i32:{ *:[i32] }:$src1_mods), (VOP3Mods:{ *:[f32] } f32:{ *:[f32] }:$src0, i32:{ *:[i32] }:$src0_mods)))<<P:Predicate_fminnum_like_nnan>>  =>  (V_MED3_F32_e64:{ *:[f32] } ?:{ *:[i32] }:$src0_mods, ?:{ *:[f32] }:$src0, ?:{ *:[i32] }:$src1_mods, ?:{ *:[f32] }:$src1, ?:{ *:[i32] }:$src2_mods, ?:{ *:[f32] }:$src2, 0:{ *:[i1] }, 0:{ *:[i32] })
        GIR_BuildMI, /*InsnID*/0, /*Opcode*/GIMT_Encode2(AMDGPU::V_MED3_F32_e64),
        GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/0, // DstI[vdst]
        GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(1), /*SubOperand*/1, // src0_mods
        GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(1), /*SubOperand*/0, // src0
        GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/1, // src1_mods
        GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/0, // src1
        GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(2), /*SubOperand*/1, // src2_mods
        GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(2), /*SubOperand*/0, // src2
        GIR_AddImm8, /*InsnID*/0, /*Imm*/0,
        GIR_AddImm8, /*InsnID*/0, /*Imm*/0,
        GIR_ConstrainSelectedInstOperands, /*InsnID*/0,
        GIR_EraseFromParent, /*InsnID*/0,
        // GIR_Coverage, 10475,
        GIR_Done,
      // Label 4376: @276487
      GIM_Try, /*On fail goto*//*Label 4377*/ GIMT_Encode4(276627), // Rule ID 10412 //
        GIM_CheckRegBankForClass, /*MI*/0, /*Op*/0, /*RC*/GIMT_Encode2(AMDGPU::VGPR_32RegClassID),
        GIM_RecordInsn, /*DefineMI*/1, /*MI*/0, /*OpIdx*/1, // MIs[1]
        GIM_CheckOpcode, /*MI*/1, GIMT_Encode2(TargetOpcode::G_FMAXNUM),
        GIM_CheckType, /*MI*/1, /*Op*/1, /*Type*/GILLT_s32,
        GIM_CheckType, /*MI*/1, /*Op*/2, /*Type*/GILLT_s32,
        GIM_RecordInsn, /*DefineMI*/2, /*MI*/1, /*OpIdx*/1, // MIs[2]
        GIM_CheckOpcode, /*MI*/2, GIMT_Encode2(TargetOpcode::G_FMINNUM),
        GIM_CheckType, /*MI*/2, /*Op*/1, /*Type*/GILLT_s32,
        GIM_CheckType, /*MI*/2, /*Op*/2, /*Type*/GILLT_s32,
        GIM_RecordInsn, /*DefineMI*/3, /*MI*/0, /*OpIdx*/2, // MIs[3]
        GIM_CheckOpcode, /*MI*/3, GIMT_Encode2(TargetOpcode::G_FMAXNUM_IEEE),
        // MIs[3] VOP3Mods:src0:src0_mods
        GIM_CheckIsSameOperand, /*MI*/3, /*OpIdx*/1, /*OtherMI*/2, /*OtherOpIdx*/1,
        // MIs[3] VOP3Mods:src1:src1_mods
        GIM_CheckIsSameOperand, /*MI*/3, /*OpIdx*/2, /*OtherMI*/2, /*OtherOpIdx*/2,
        GIM_CheckCxxInsnPredicate, /*MI*/0, /*FnId*/GIMT_Encode2(GICXXPred_MI_Predicate_fminnum_like_nnan),
        GIM_CheckIsSafeToFold, /*InsnID*/1,
        GIM_CheckIsSafeToFold, /*InsnID*/2,
        GIM_CheckIsSafeToFold, /*InsnID*/3,
        GIM_CheckComplexPattern, /*MI*/1, /*Op*/2, /*Renderer*/GIMT_Encode2(2), GIMT_Encode2(GICP_gi_vop3mods),
        GIM_CheckComplexPattern, /*MI*/2, /*Op*/1, /*Renderer*/GIMT_Encode2(0), GIMT_Encode2(GICP_gi_vop3mods),
        GIM_CheckComplexPattern, /*MI*/2, /*Op*/2, /*Renderer*/GIMT_Encode2(1), GIMT_Encode2(GICP_gi_vop3mods),
        // (fminnum:{ *:[f32] } (fmaxnum:{ *:[f32] } (fminnum:{ *:[f32] } (VOP3Mods:{ *:[f32] } f32:{ *:[f32] }:$src0, i32:{ *:[i32] }:$src0_mods), (VOP3Mods:{ *:[f32] } f32:{ *:[f32] }:$src1, i32:{ *:[i32] }:$src1_mods)), (VOP3Mods:{ *:[f32] } f32:{ *:[f32] }:$src2, i32:{ *:[i32] }:$src2_mods)), (fmaxnum_ieee:{ *:[f32] } (VOP3Mods:{ *:[f32] } f32:{ *:[f32] }:$src0, i32:{ *:[i32] }:$src0_mods), (VOP3Mods:{ *:[f32] } f32:{ *:[f32] }:$src1, i32:{ *:[i32] }:$src1_mods)))<<P:Predicate_fminnum_like_nnan>>  =>  (V_MED3_F32_e64:{ *:[f32] } ?:{ *:[i32] }:$src0_mods, ?:{ *:[f32] }:$src0, ?:{ *:[i32] }:$src1_mods, ?:{ *:[f32] }:$src1, ?:{ *:[i32] }:$src2_mods, ?:{ *:[f32] }:$src2, 0:{ *:[i1] }, 0:{ *:[i32] })
        GIR_BuildMI, /*InsnID*/0, /*Opcode*/GIMT_Encode2(AMDGPU::V_MED3_F32_e64),
        GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/0, // DstI[vdst]
        GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/1, // src0_mods
        GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/0, // src0
        GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(1), /*SubOperand*/1, // src1_mods
        GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(1), /*SubOperand*/0, // src1
        GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(2), /*SubOperand*/1, // src2_mods
        GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(2), /*SubOperand*/0, // src2
        GIR_AddImm8, /*InsnID*/0, /*Imm*/0,
        GIR_AddImm8, /*InsnID*/0, /*Imm*/0,
        GIR_ConstrainSelectedInstOperands, /*InsnID*/0,
        GIR_EraseFromParent, /*InsnID*/0,
        // GIR_Coverage, 10412,
        GIR_Done,
      // Label 4377: @276627
      GIM_Try, /*On fail goto*//*Label 4378*/ GIMT_Encode4(276767), // Rule ID 10413 //
        GIM_CheckRegBankForClass, /*MI*/0, /*Op*/0, /*RC*/GIMT_Encode2(AMDGPU::VGPR_32RegClassID),
        GIM_RecordInsn, /*DefineMI*/1, /*MI*/0, /*OpIdx*/1, // MIs[1]
        GIM_CheckOpcode, /*MI*/1, GIMT_Encode2(TargetOpcode::G_FMAXNUM),
        GIM_CheckType, /*MI*/1, /*Op*/1, /*Type*/GILLT_s32,
        GIM_CheckType, /*MI*/1, /*Op*/2, /*Type*/GILLT_s32,
        GIM_RecordInsn, /*DefineMI*/2, /*MI*/1, /*OpIdx*/1, // MIs[2]
        GIM_CheckOpcode, /*MI*/2, GIMT_Encode2(TargetOpcode::G_FMINNUM),
        GIM_CheckType, /*MI*/2, /*Op*/1, /*Type*/GILLT_s32,
        GIM_CheckType, /*MI*/2, /*Op*/2, /*Type*/GILLT_s32,
        GIM_RecordInsn, /*DefineMI*/3, /*MI*/0, /*OpIdx*/2, // MIs[3]
        GIM_CheckOpcode, /*MI*/3, GIMT_Encode2(TargetOpcode::G_FMAXNUM_IEEE),
        // MIs[3] VOP3Mods:src1:src1_mods
        GIM_CheckIsSameOperand, /*MI*/3, /*OpIdx*/1, /*OtherMI*/2, /*OtherOpIdx*/2,
        // MIs[3] VOP3Mods:src0:src0_mods
        GIM_CheckIsSameOperand, /*MI*/3, /*OpIdx*/2, /*OtherMI*/2, /*OtherOpIdx*/1,
        GIM_CheckCxxInsnPredicate, /*MI*/0, /*FnId*/GIMT_Encode2(GICXXPred_MI_Predicate_fminnum_like_nnan),
        GIM_CheckIsSafeToFold, /*InsnID*/1,
        GIM_CheckIsSafeToFold, /*InsnID*/2,
        GIM_CheckIsSafeToFold, /*InsnID*/3,
        GIM_CheckComplexPattern, /*MI*/1, /*Op*/2, /*Renderer*/GIMT_Encode2(2), GIMT_Encode2(GICP_gi_vop3mods),
        GIM_CheckComplexPattern, /*MI*/2, /*Op*/1, /*Renderer*/GIMT_Encode2(0), GIMT_Encode2(GICP_gi_vop3mods),
        GIM_CheckComplexPattern, /*MI*/2, /*Op*/2, /*Renderer*/GIMT_Encode2(1), GIMT_Encode2(GICP_gi_vop3mods),
        // (fminnum:{ *:[f32] } (fmaxnum:{ *:[f32] } (fminnum:{ *:[f32] } (VOP3Mods:{ *:[f32] } f32:{ *:[f32] }:$src0, i32:{ *:[i32] }:$src0_mods), (VOP3Mods:{ *:[f32] } f32:{ *:[f32] }:$src1, i32:{ *:[i32] }:$src1_mods)), (VOP3Mods:{ *:[f32] } f32:{ *:[f32] }:$src2, i32:{ *:[i32] }:$src2_mods)), (fmaxnum_ieee:{ *:[f32] } (VOP3Mods:{ *:[f32] } f32:{ *:[f32] }:$src1, i32:{ *:[i32] }:$src1_mods), (VOP3Mods:{ *:[f32] } f32:{ *:[f32] }:$src0, i32:{ *:[i32] }:$src0_mods)))<<P:Predicate_fminnum_like_nnan>>  =>  (V_MED3_F32_e64:{ *:[f32] } ?:{ *:[i32] }:$src0_mods, ?:{ *:[f32] }:$src0, ?:{ *:[i32] }:$src1_mods, ?:{ *:[f32] }:$src1, ?:{ *:[i32] }:$src2_mods, ?:{ *:[f32] }:$src2, 0:{ *:[i1] }, 0:{ *:[i32] })
        GIR_BuildMI, /*InsnID*/0, /*Opcode*/GIMT_Encode2(AMDGPU::V_MED3_F32_e64),
        GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/0, // DstI[vdst]
        GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/1, // src0_mods
        GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/0, // src0
        GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(1), /*SubOperand*/1, // src1_mods
        GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(1), /*SubOperand*/0, // src1
        GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(2), /*SubOperand*/1, // src2_mods
        GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(2), /*SubOperand*/0, // src2
        GIR_AddImm8, /*InsnID*/0, /*Imm*/0,
        GIR_AddImm8, /*InsnID*/0, /*Imm*/0,
        GIR_ConstrainSelectedInstOperands, /*InsnID*/0,
        GIR_EraseFromParent, /*InsnID*/0,
        // GIR_Coverage, 10413,
        GIR_Done,
      // Label 4378: @276767
      GIM_Try, /*On fail goto*//*Label 4379*/ GIMT_Encode4(276907), // Rule ID 10414 //
        GIM_CheckRegBankForClass, /*MI*/0, /*Op*/0, /*RC*/GIMT_Encode2(AMDGPU::VGPR_32RegClassID),
        GIM_RecordInsn, /*DefineMI*/1, /*MI*/0, /*OpIdx*/1, // MIs[1]
        GIM_CheckOpcode, /*MI*/1, GIMT_Encode2(TargetOpcode::G_FMAXNUM),
        GIM_CheckType, /*MI*/1, /*Op*/1, /*Type*/GILLT_s32,
        GIM_CheckType, /*MI*/1, /*Op*/2, /*Type*/GILLT_s32,
        GIM_RecordInsn, /*DefineMI*/2, /*MI*/1, /*OpIdx*/1, // MIs[2]
        GIM_CheckOpcode, /*MI*/2, GIMT_Encode2(TargetOpcode::G_FMINNUM),
        GIM_CheckType, /*MI*/2, /*Op*/1, /*Type*/GILLT_s32,
        GIM_CheckType, /*MI*/2, /*Op*/2, /*Type*/GILLT_s32,
        GIM_RecordInsn, /*DefineMI*/3, /*MI*/0, /*OpIdx*/2, // MIs[3]
        GIM_CheckOpcode, /*MI*/3, GIMT_Encode2(TargetOpcode::G_FMAXNUM_IEEE),
        // MIs[3] VOP3Mods:src0:src0_mods
        GIM_CheckIsSameOperand, /*MI*/3, /*OpIdx*/1, /*OtherMI*/2, /*OtherOpIdx*/2,
        // MIs[3] VOP3Mods:src1:src1_mods
        GIM_CheckIsSameOperand, /*MI*/3, /*OpIdx*/2, /*OtherMI*/2, /*OtherOpIdx*/1,
        GIM_CheckCxxInsnPredicate, /*MI*/0, /*FnId*/GIMT_Encode2(GICXXPred_MI_Predicate_fminnum_like_nnan),
        GIM_CheckIsSafeToFold, /*InsnID*/1,
        GIM_CheckIsSafeToFold, /*InsnID*/2,
        GIM_CheckIsSafeToFold, /*InsnID*/3,
        GIM_CheckComplexPattern, /*MI*/1, /*Op*/2, /*Renderer*/GIMT_Encode2(2), GIMT_Encode2(GICP_gi_vop3mods),
        GIM_CheckComplexPattern, /*MI*/2, /*Op*/1, /*Renderer*/GIMT_Encode2(0), GIMT_Encode2(GICP_gi_vop3mods),
        GIM_CheckComplexPattern, /*MI*/2, /*Op*/2, /*Renderer*/GIMT_Encode2(1), GIMT_Encode2(GICP_gi_vop3mods),
        // (fminnum:{ *:[f32] } (fmaxnum:{ *:[f32] } (fminnum:{ *:[f32] } (VOP3Mods:{ *:[f32] } f32:{ *:[f32] }:$src1, i32:{ *:[i32] }:$src1_mods), (VOP3Mods:{ *:[f32] } f32:{ *:[f32] }:$src0, i32:{ *:[i32] }:$src0_mods)), (VOP3Mods:{ *:[f32] } f32:{ *:[f32] }:$src2, i32:{ *:[i32] }:$src2_mods)), (fmaxnum_ieee:{ *:[f32] } (VOP3Mods:{ *:[f32] } f32:{ *:[f32] }:$src0, i32:{ *:[i32] }:$src0_mods), (VOP3Mods:{ *:[f32] } f32:{ *:[f32] }:$src1, i32:{ *:[i32] }:$src1_mods)))<<P:Predicate_fminnum_like_nnan>>  =>  (V_MED3_F32_e64:{ *:[f32] } ?:{ *:[i32] }:$src0_mods, ?:{ *:[f32] }:$src0, ?:{ *:[i32] }:$src1_mods, ?:{ *:[f32] }:$src1, ?:{ *:[i32] }:$src2_mods, ?:{ *:[f32] }:$src2, 0:{ *:[i1] }, 0:{ *:[i32] })
        GIR_BuildMI, /*InsnID*/0, /*Opcode*/GIMT_Encode2(AMDGPU::V_MED3_F32_e64),
        GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/0, // DstI[vdst]
        GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(1), /*SubOperand*/1, // src0_mods
        GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(1), /*SubOperand*/0, // src0
        GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/1, // src1_mods
        GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/0, // src1
        GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(2), /*SubOperand*/1, // src2_mods
        GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(2), /*SubOperand*/0, // src2
        GIR_AddImm8, /*InsnID*/0, /*Imm*/0,
        GIR_AddImm8, /*InsnID*/0, /*Imm*/0,
        GIR_ConstrainSelectedInstOperands, /*InsnID*/0,
        GIR_EraseFromParent, /*InsnID*/0,
        // GIR_Coverage, 10414,
        GIR_Done,
      // Label 4379: @276907
      GIM_Try, /*On fail goto*//*Label 4380*/ GIMT_Encode4(277047), // Rule ID 10415 //
        GIM_CheckRegBankForClass, /*MI*/0, /*Op*/0, /*RC*/GIMT_Encode2(AMDGPU::VGPR_32RegClassID),
        GIM_RecordInsn, /*DefineMI*/1, /*MI*/0, /*OpIdx*/1, // MIs[1]
        GIM_CheckOpcode, /*MI*/1, GIMT_Encode2(TargetOpcode::G_FMAXNUM),
        GIM_CheckType, /*MI*/1, /*Op*/1, /*Type*/GILLT_s32,
        GIM_CheckType, /*MI*/1, /*Op*/2, /*Type*/GILLT_s32,
        GIM_RecordInsn, /*DefineMI*/2, /*MI*/1, /*OpIdx*/1, // MIs[2]
        GIM_CheckOpcode, /*MI*/2, GIMT_Encode2(TargetOpcode::G_FMINNUM),
        GIM_CheckType, /*MI*/2, /*Op*/1, /*Type*/GILLT_s32,
        GIM_CheckType, /*MI*/2, /*Op*/2, /*Type*/GILLT_s32,
        GIM_RecordInsn, /*DefineMI*/3, /*MI*/0, /*OpIdx*/2, // MIs[3]
        GIM_CheckOpcode, /*MI*/3, GIMT_Encode2(TargetOpcode::G_FMAXNUM_IEEE),
        // MIs[3] VOP3Mods:src1:src1_mods
        GIM_CheckIsSameOperand, /*MI*/3, /*OpIdx*/1, /*OtherMI*/2, /*OtherOpIdx*/1,
        // MIs[3] VOP3Mods:src0:src0_mods
        GIM_CheckIsSameOperand, /*MI*/3, /*OpIdx*/2, /*OtherMI*/2, /*OtherOpIdx*/2,
        GIM_CheckCxxInsnPredicate, /*MI*/0, /*FnId*/GIMT_Encode2(GICXXPred_MI_Predicate_fminnum_like_nnan),
        GIM_CheckIsSafeToFold, /*InsnID*/1,
        GIM_CheckIsSafeToFold, /*InsnID*/2,
        GIM_CheckIsSafeToFold, /*InsnID*/3,
        GIM_CheckComplexPattern, /*MI*/1, /*Op*/2, /*Renderer*/GIMT_Encode2(2), GIMT_Encode2(GICP_gi_vop3mods),
        GIM_CheckComplexPattern, /*MI*/2, /*Op*/1, /*Renderer*/GIMT_Encode2(0), GIMT_Encode2(GICP_gi_vop3mods),
        GIM_CheckComplexPattern, /*MI*/2, /*Op*/2, /*Renderer*/GIMT_Encode2(1), GIMT_Encode2(GICP_gi_vop3mods),
        // (fminnum:{ *:[f32] } (fmaxnum:{ *:[f32] } (fminnum:{ *:[f32] } (VOP3Mods:{ *:[f32] } f32:{ *:[f32] }:$src1, i32:{ *:[i32] }:$src1_mods), (VOP3Mods:{ *:[f32] } f32:{ *:[f32] }:$src0, i32:{ *:[i32] }:$src0_mods)), (VOP3Mods:{ *:[f32] } f32:{ *:[f32] }:$src2, i32:{ *:[i32] }:$src2_mods)), (fmaxnum_ieee:{ *:[f32] } (VOP3Mods:{ *:[f32] } f32:{ *:[f32] }:$src1, i32:{ *:[i32] }:$src1_mods), (VOP3Mods:{ *:[f32] } f32:{ *:[f32] }:$src0, i32:{ *:[i32] }:$src0_mods)))<<P:Predicate_fminnum_like_nnan>>  =>  (V_MED3_F32_e64:{ *:[f32] } ?:{ *:[i32] }:$src0_mods, ?:{ *:[f32] }:$src0, ?:{ *:[i32] }:$src1_mods, ?:{ *:[f32] }:$src1, ?:{ *:[i32] }:$src2_mods, ?:{ *:[f32] }:$src2, 0:{ *:[i1] }, 0:{ *:[i32] })
        GIR_BuildMI, /*InsnID*/0, /*Opcode*/GIMT_Encode2(AMDGPU::V_MED3_F32_e64),
        GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/0, // DstI[vdst]
        GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(1), /*SubOperand*/1, // src0_mods
        GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(1), /*SubOperand*/0, // src0
        GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/1, // src1_mods
        GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/0, // src1
        GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(2), /*SubOperand*/1, // src2_mods
        GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(2), /*SubOperand*/0, // src2
        GIR_AddImm8, /*InsnID*/0, /*Imm*/0,
        GIR_AddImm8, /*InsnID*/0, /*Imm*/0,
        GIR_ConstrainSelectedInstOperands, /*InsnID*/0,
        GIR_EraseFromParent, /*InsnID*/0,
        // GIR_Coverage, 10415,
        GIR_Done,
      // Label 4380: @277047
      GIM_Try, /*On fail goto*//*Label 4381*/ GIMT_Encode4(277187), // Rule ID 10457 //
        GIM_CheckRegBankForClass, /*MI*/0, /*Op*/0, /*RC*/GIMT_Encode2(AMDGPU::VGPR_32RegClassID),
        GIM_RecordInsn, /*DefineMI*/1, /*MI*/0, /*OpIdx*/1, // MIs[1]
        GIM_CheckOpcode, /*MI*/1, GIMT_Encode2(TargetOpcode::G_FMAXNUM),
        GIM_CheckType, /*MI*/1, /*Op*/1, /*Type*/GILLT_s32,
        GIM_CheckType, /*MI*/1, /*Op*/2, /*Type*/GILLT_s32,
        GIM_RecordInsn, /*DefineMI*/2, /*MI*/1, /*OpIdx*/1, // MIs[2]
        GIM_CheckOpcode, /*MI*/2, GIMT_Encode2(TargetOpcode::G_FMINNUM_IEEE),
        GIM_CheckType, /*MI*/2, /*Op*/1, /*Type*/GILLT_s32,
        GIM_CheckType, /*MI*/2, /*Op*/2, /*Type*/GILLT_s32,
        GIM_RecordInsn, /*DefineMI*/3, /*MI*/0, /*OpIdx*/2, // MIs[3]
        GIM_CheckOpcode, /*MI*/3, GIMT_Encode2(TargetOpcode::G_FMAXNUM),
        // MIs[3] VOP3Mods:src0:src0_mods
        GIM_CheckIsSameOperand, /*MI*/3, /*OpIdx*/1, /*OtherMI*/2, /*OtherOpIdx*/1,
        // MIs[3] VOP3Mods:src1:src1_mods
        GIM_CheckIsSameOperand, /*MI*/3, /*OpIdx*/2, /*OtherMI*/2, /*OtherOpIdx*/2,
        GIM_CheckCxxInsnPredicate, /*MI*/0, /*FnId*/GIMT_Encode2(GICXXPred_MI_Predicate_fminnum_like_nnan),
        GIM_CheckIsSafeToFold, /*InsnID*/1,
        GIM_CheckIsSafeToFold, /*InsnID*/2,
        GIM_CheckIsSafeToFold, /*InsnID*/3,
        GIM_CheckComplexPattern, /*MI*/1, /*Op*/2, /*Renderer*/GIMT_Encode2(2), GIMT_Encode2(GICP_gi_vop3mods),
        GIM_CheckComplexPattern, /*MI*/2, /*Op*/1, /*Renderer*/GIMT_Encode2(0), GIMT_Encode2(GICP_gi_vop3mods),
        GIM_CheckComplexPattern, /*MI*/2, /*Op*/2, /*Renderer*/GIMT_Encode2(1), GIMT_Encode2(GICP_gi_vop3mods),
        // (fminnum:{ *:[f32] } (fmaxnum:{ *:[f32] } (fminnum_ieee:{ *:[f32] } (VOP3Mods:{ *:[f32] } f32:{ *:[f32] }:$src0, i32:{ *:[i32] }:$src0_mods), (VOP3Mods:{ *:[f32] } f32:{ *:[f32] }:$src1, i32:{ *:[i32] }:$src1_mods)), (VOP3Mods:{ *:[f32] } f32:{ *:[f32] }:$src2, i32:{ *:[i32] }:$src2_mods)), (fmaxnum:{ *:[f32] } (VOP3Mods:{ *:[f32] } f32:{ *:[f32] }:$src0, i32:{ *:[i32] }:$src0_mods), (VOP3Mods:{ *:[f32] } f32:{ *:[f32] }:$src1, i32:{ *:[i32] }:$src1_mods)))<<P:Predicate_fminnum_like_nnan>>  =>  (V_MED3_F32_e64:{ *:[f32] } ?:{ *:[i32] }:$src0_mods, ?:{ *:[f32] }:$src0, ?:{ *:[i32] }:$src1_mods, ?:{ *:[f32] }:$src1, ?:{ *:[i32] }:$src2_mods, ?:{ *:[f32] }:$src2, 0:{ *:[i1] }, 0:{ *:[i32] })
        GIR_BuildMI, /*InsnID*/0, /*Opcode*/GIMT_Encode2(AMDGPU::V_MED3_F32_e64),
        GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/0, // DstI[vdst]
        GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/1, // src0_mods
        GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/0, // src0
        GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(1), /*SubOperand*/1, // src1_mods
        GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(1), /*SubOperand*/0, // src1
        GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(2), /*SubOperand*/1, // src2_mods
        GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(2), /*SubOperand*/0, // src2
        GIR_AddImm8, /*InsnID*/0, /*Imm*/0,
        GIR_AddImm8, /*InsnID*/0, /*Imm*/0,
        GIR_ConstrainSelectedInstOperands, /*InsnID*/0,
        GIR_EraseFromParent, /*InsnID*/0,
        // GIR_Coverage, 10457,
        GIR_Done,
      // Label 4381: @277187
      GIM_Try, /*On fail goto*//*Label 4382*/ GIMT_Encode4(277327), // Rule ID 10458 //
        GIM_CheckRegBankForClass, /*MI*/0, /*Op*/0, /*RC*/GIMT_Encode2(AMDGPU::VGPR_32RegClassID),
        GIM_RecordInsn, /*DefineMI*/1, /*MI*/0, /*OpIdx*/1, // MIs[1]
        GIM_CheckOpcode, /*MI*/1, GIMT_Encode2(TargetOpcode::G_FMAXNUM),
        GIM_CheckType, /*MI*/1, /*Op*/1, /*Type*/GILLT_s32,
        GIM_CheckType, /*MI*/1, /*Op*/2, /*Type*/GILLT_s32,
        GIM_RecordInsn, /*DefineMI*/2, /*MI*/1, /*OpIdx*/1, // MIs[2]
        GIM_CheckOpcode, /*MI*/2, GIMT_Encode2(TargetOpcode::G_FMINNUM_IEEE),
        GIM_CheckType, /*MI*/2, /*Op*/1, /*Type*/GILLT_s32,
        GIM_CheckType, /*MI*/2, /*Op*/2, /*Type*/GILLT_s32,
        GIM_RecordInsn, /*DefineMI*/3, /*MI*/0, /*OpIdx*/2, // MIs[3]
        GIM_CheckOpcode, /*MI*/3, GIMT_Encode2(TargetOpcode::G_FMAXNUM),
        // MIs[3] VOP3Mods:src1:src1_mods
        GIM_CheckIsSameOperand, /*MI*/3, /*OpIdx*/1, /*OtherMI*/2, /*OtherOpIdx*/2,
        // MIs[3] VOP3Mods:src0:src0_mods
        GIM_CheckIsSameOperand, /*MI*/3, /*OpIdx*/2, /*OtherMI*/2, /*OtherOpIdx*/1,
        GIM_CheckCxxInsnPredicate, /*MI*/0, /*FnId*/GIMT_Encode2(GICXXPred_MI_Predicate_fminnum_like_nnan),
        GIM_CheckIsSafeToFold, /*InsnID*/1,
        GIM_CheckIsSafeToFold, /*InsnID*/2,
        GIM_CheckIsSafeToFold, /*InsnID*/3,
        GIM_CheckComplexPattern, /*MI*/1, /*Op*/2, /*Renderer*/GIMT_Encode2(2), GIMT_Encode2(GICP_gi_vop3mods),
        GIM_CheckComplexPattern, /*MI*/2, /*Op*/1, /*Renderer*/GIMT_Encode2(0), GIMT_Encode2(GICP_gi_vop3mods),
        GIM_CheckComplexPattern, /*MI*/2, /*Op*/2, /*Renderer*/GIMT_Encode2(1), GIMT_Encode2(GICP_gi_vop3mods),
        // (fminnum:{ *:[f32] } (fmaxnum:{ *:[f32] } (fminnum_ieee:{ *:[f32] } (VOP3Mods:{ *:[f32] } f32:{ *:[f32] }:$src0, i32:{ *:[i32] }:$src0_mods), (VOP3Mods:{ *:[f32] } f32:{ *:[f32] }:$src1, i32:{ *:[i32] }:$src1_mods)), (VOP3Mods:{ *:[f32] } f32:{ *:[f32] }:$src2, i32:{ *:[i32] }:$src2_mods)), (fmaxnum:{ *:[f32] } (VOP3Mods:{ *:[f32] } f32:{ *:[f32] }:$src1, i32:{ *:[i32] }:$src1_mods), (VOP3Mods:{ *:[f32] } f32:{ *:[f32] }:$src0, i32:{ *:[i32] }:$src0_mods)))<<P:Predicate_fminnum_like_nnan>>  =>  (V_MED3_F32_e64:{ *:[f32] } ?:{ *:[i32] }:$src0_mods, ?:{ *:[f32] }:$src0, ?:{ *:[i32] }:$src1_mods, ?:{ *:[f32] }:$src1, ?:{ *:[i32] }:$src2_mods, ?:{ *:[f32] }:$src2, 0:{ *:[i1] }, 0:{ *:[i32] })
        GIR_BuildMI, /*InsnID*/0, /*Opcode*/GIMT_Encode2(AMDGPU::V_MED3_F32_e64),
        GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/0, // DstI[vdst]
        GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/1, // src0_mods
        GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/0, // src0
        GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(1), /*SubOperand*/1, // src1_mods
        GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(1), /*SubOperand*/0, // src1
        GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(2), /*SubOperand*/1, // src2_mods
        GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(2), /*SubOperand*/0, // src2
        GIR_AddImm8, /*InsnID*/0, /*Imm*/0,
        GIR_AddImm8, /*InsnID*/0, /*Imm*/0,
        GIR_ConstrainSelectedInstOperands, /*InsnID*/0,
        GIR_EraseFromParent, /*InsnID*/0,
        // GIR_Coverage, 10458,
        GIR_Done,
      // Label 4382: @277327
      GIM_Try, /*On fail goto*//*Label 4383*/ GIMT_Encode4(277467), // Rule ID 10459 //
        GIM_CheckRegBankForClass, /*MI*/0, /*Op*/0, /*RC*/GIMT_Encode2(AMDGPU::VGPR_32RegClassID),
        GIM_RecordInsn, /*DefineMI*/1, /*MI*/0, /*OpIdx*/1, // MIs[1]
        GIM_CheckOpcode, /*MI*/1, GIMT_Encode2(TargetOpcode::G_FMAXNUM),
        GIM_CheckType, /*MI*/1, /*Op*/1, /*Type*/GILLT_s32,
        GIM_CheckType, /*MI*/1, /*Op*/2, /*Type*/GILLT_s32,
        GIM_RecordInsn, /*DefineMI*/2, /*MI*/1, /*OpIdx*/1, // MIs[2]
        GIM_CheckOpcode, /*MI*/2, GIMT_Encode2(TargetOpcode::G_FMINNUM_IEEE),
        GIM_CheckType, /*MI*/2, /*Op*/1, /*Type*/GILLT_s32,
        GIM_CheckType, /*MI*/2, /*Op*/2, /*Type*/GILLT_s32,
        GIM_RecordInsn, /*DefineMI*/3, /*MI*/0, /*OpIdx*/2, // MIs[3]
        GIM_CheckOpcode, /*MI*/3, GIMT_Encode2(TargetOpcode::G_FMAXNUM),
        // MIs[3] VOP3Mods:src0:src0_mods
        GIM_CheckIsSameOperand, /*MI*/3, /*OpIdx*/1, /*OtherMI*/2, /*OtherOpIdx*/2,
        // MIs[3] VOP3Mods:src1:src1_mods
        GIM_CheckIsSameOperand, /*MI*/3, /*OpIdx*/2, /*OtherMI*/2, /*OtherOpIdx*/1,
        GIM_CheckCxxInsnPredicate, /*MI*/0, /*FnId*/GIMT_Encode2(GICXXPred_MI_Predicate_fminnum_like_nnan),
        GIM_CheckIsSafeToFold, /*InsnID*/1,
        GIM_CheckIsSafeToFold, /*InsnID*/2,
        GIM_CheckIsSafeToFold, /*InsnID*/3,
        GIM_CheckComplexPattern, /*MI*/1, /*Op*/2, /*Renderer*/GIMT_Encode2(2), GIMT_Encode2(GICP_gi_vop3mods),
        GIM_CheckComplexPattern, /*MI*/2, /*Op*/1, /*Renderer*/GIMT_Encode2(0), GIMT_Encode2(GICP_gi_vop3mods),
        GIM_CheckComplexPattern, /*MI*/2, /*Op*/2, /*Renderer*/GIMT_Encode2(1), GIMT_Encode2(GICP_gi_vop3mods),
        // (fminnum:{ *:[f32] } (fmaxnum:{ *:[f32] } (fminnum_ieee:{ *:[f32] } (VOP3Mods:{ *:[f32] } f32:{ *:[f32] }:$src1, i32:{ *:[i32] }:$src1_mods), (VOP3Mods:{ *:[f32] } f32:{ *:[f32] }:$src0, i32:{ *:[i32] }:$src0_mods)), (VOP3Mods:{ *:[f32] } f32:{ *:[f32] }:$src2, i32:{ *:[i32] }:$src2_mods)), (fmaxnum:{ *:[f32] } (VOP3Mods:{ *:[f32] } f32:{ *:[f32] }:$src0, i32:{ *:[i32] }:$src0_mods), (VOP3Mods:{ *:[f32] } f32:{ *:[f32] }:$src1, i32:{ *:[i32] }:$src1_mods)))<<P:Predicate_fminnum_like_nnan>>  =>  (V_MED3_F32_e64:{ *:[f32] } ?:{ *:[i32] }:$src0_mods, ?:{ *:[f32] }:$src0, ?:{ *:[i32] }:$src1_mods, ?:{ *:[f32] }:$src1, ?:{ *:[i32] }:$src2_mods, ?:{ *:[f32] }:$src2, 0:{ *:[i1] }, 0:{ *:[i32] })
        GIR_BuildMI, /*InsnID*/0, /*Opcode*/GIMT_Encode2(AMDGPU::V_MED3_F32_e64),
        GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/0, // DstI[vdst]
        GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(1), /*SubOperand*/1, // src0_mods
        GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(1), /*SubOperand*/0, // src0
        GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/1, // src1_mods
        GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/0, // src1
        GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(2), /*SubOperand*/1, // src2_mods
        GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(2), /*SubOperand*/0, // src2
        GIR_AddImm8, /*InsnID*/0, /*Imm*/0,
        GIR_AddImm8, /*InsnID*/0, /*Imm*/0,
        GIR_ConstrainSelectedInstOperands, /*InsnID*/0,
        GIR_EraseFromParent, /*InsnID*/0,
        // GIR_Coverage, 10459,
        GIR_Done,
      // Label 4383: @277467
      GIM_Try, /*On fail goto*//*Label 4384*/ GIMT_Encode4(277607), // Rule ID 10460 //
        GIM_CheckRegBankForClass, /*MI*/0, /*Op*/0, /*RC*/GIMT_Encode2(AMDGPU::VGPR_32RegClassID),
        GIM_RecordInsn, /*DefineMI*/1, /*MI*/0, /*OpIdx*/1, // MIs[1]
        GIM_CheckOpcode, /*MI*/1, GIMT_Encode2(TargetOpcode::G_FMAXNUM),
        GIM_CheckType, /*MI*/1, /*Op*/1, /*Type*/GILLT_s32,
        GIM_CheckType, /*MI*/1, /*Op*/2, /*Type*/GILLT_s32,
        GIM_RecordInsn, /*DefineMI*/2, /*MI*/1, /*OpIdx*/1, // MIs[2]
        GIM_CheckOpcode, /*MI*/2, GIMT_Encode2(TargetOpcode::G_FMINNUM_IEEE),
        GIM_CheckType, /*MI*/2, /*Op*/1, /*Type*/GILLT_s32,
        GIM_CheckType, /*MI*/2, /*Op*/2, /*Type*/GILLT_s32,
        GIM_RecordInsn, /*DefineMI*/3, /*MI*/0, /*OpIdx*/2, // MIs[3]
        GIM_CheckOpcode, /*MI*/3, GIMT_Encode2(TargetOpcode::G_FMAXNUM),
        // MIs[3] VOP3Mods:src1:src1_mods
        GIM_CheckIsSameOperand, /*MI*/3, /*OpIdx*/1, /*OtherMI*/2, /*OtherOpIdx*/1,
        // MIs[3] VOP3Mods:src0:src0_mods
        GIM_CheckIsSameOperand, /*MI*/3, /*OpIdx*/2, /*OtherMI*/2, /*OtherOpIdx*/2,
        GIM_CheckCxxInsnPredicate, /*MI*/0, /*FnId*/GIMT_Encode2(GICXXPred_MI_Predicate_fminnum_like_nnan),
        GIM_CheckIsSafeToFold, /*InsnID*/1,
        GIM_CheckIsSafeToFold, /*InsnID*/2,
        GIM_CheckIsSafeToFold, /*InsnID*/3,
        GIM_CheckComplexPattern, /*MI*/1, /*Op*/2, /*Renderer*/GIMT_Encode2(2), GIMT_Encode2(GICP_gi_vop3mods),
        GIM_CheckComplexPattern, /*MI*/2, /*Op*/1, /*Renderer*/GIMT_Encode2(0), GIMT_Encode2(GICP_gi_vop3mods),
        GIM_CheckComplexPattern, /*MI*/2, /*Op*/2, /*Renderer*/GIMT_Encode2(1), GIMT_Encode2(GICP_gi_vop3mods),
        // (fminnum:{ *:[f32] } (fmaxnum:{ *:[f32] } (fminnum_ieee:{ *:[f32] } (VOP3Mods:{ *:[f32] } f32:{ *:[f32] }:$src1, i32:{ *:[i32] }:$src1_mods), (VOP3Mods:{ *:[f32] } f32:{ *:[f32] }:$src0, i32:{ *:[i32] }:$src0_mods)), (VOP3Mods:{ *:[f32] } f32:{ *:[f32] }:$src2, i32:{ *:[i32] }:$src2_mods)), (fmaxnum:{ *:[f32] } (VOP3Mods:{ *:[f32] } f32:{ *:[f32] }:$src1, i32:{ *:[i32] }:$src1_mods), (VOP3Mods:{ *:[f32] } f32:{ *:[f32] }:$src0, i32:{ *:[i32] }:$src0_mods)))<<P:Predicate_fminnum_like_nnan>>  =>  (V_MED3_F32_e64:{ *:[f32] } ?:{ *:[i32] }:$src0_mods, ?:{ *:[f32] }:$src0, ?:{ *:[i32] }:$src1_mods, ?:{ *:[f32] }:$src1, ?:{ *:[i32] }:$src2_mods, ?:{ *:[f32] }:$src2, 0:{ *:[i1] }, 0:{ *:[i32] })
        GIR_BuildMI, /*InsnID*/0, /*Opcode*/GIMT_Encode2(AMDGPU::V_MED3_F32_e64),
        GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/0, // DstI[vdst]
        GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(1), /*SubOperand*/1, // src0_mods
        GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(1), /*SubOperand*/0, // src0
        GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/1, // src1_mods
        GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/0, // src1
        GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(2), /*SubOperand*/1, // src2_mods
        GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(2), /*SubOperand*/0, // src2
        GIR_AddImm8, /*InsnID*/0, /*Imm*/0,
        GIR_AddImm8, /*InsnID*/0, /*Imm*/0,
        GIR_ConstrainSelectedInstOperands, /*InsnID*/0,
        GIR_EraseFromParent, /*InsnID*/0,
        // GIR_Coverage, 10460,
        GIR_Done,
      // Label 4384: @277607
      GIM_Try, /*On fail goto*//*Label 4385*/ GIMT_Encode4(277747), // Rule ID 10397 //
        GIM_CheckRegBankForClass, /*MI*/0, /*Op*/0, /*RC*/GIMT_Encode2(AMDGPU::VGPR_32RegClassID),
        GIM_RecordInsn, /*DefineMI*/1, /*MI*/0, /*OpIdx*/1, // MIs[1]
        GIM_CheckOpcode, /*MI*/1, GIMT_Encode2(TargetOpcode::G_FMAXNUM),
        GIM_CheckType, /*MI*/1, /*Op*/1, /*Type*/GILLT_s32,
        GIM_CheckType, /*MI*/1, /*Op*/2, /*Type*/GILLT_s32,
        GIM_RecordInsn, /*DefineMI*/2, /*MI*/1, /*OpIdx*/1, // MIs[2]
        GIM_CheckOpcode, /*MI*/2, GIMT_Encode2(TargetOpcode::G_FMINNUM_IEEE),
        GIM_CheckType, /*MI*/2, /*Op*/1, /*Type*/GILLT_s32,
        GIM_CheckType, /*MI*/2, /*Op*/2, /*Type*/GILLT_s32,
        GIM_RecordInsn, /*DefineMI*/3, /*MI*/0, /*OpIdx*/2, // MIs[3]
        GIM_CheckOpcode, /*MI*/3, GIMT_Encode2(TargetOpcode::G_FMAXNUM_IEEE),
        // MIs[3] VOP3Mods:src0:src0_mods
        GIM_CheckIsSameOperand, /*MI*/3, /*OpIdx*/1, /*OtherMI*/2, /*OtherOpIdx*/1,
        // MIs[3] VOP3Mods:src1:src1_mods
        GIM_CheckIsSameOperand, /*MI*/3, /*OpIdx*/2, /*OtherMI*/2, /*OtherOpIdx*/2,
        GIM_CheckCxxInsnPredicate, /*MI*/0, /*FnId*/GIMT_Encode2(GICXXPred_MI_Predicate_fminnum_like_nnan),
        GIM_CheckIsSafeToFold, /*InsnID*/1,
        GIM_CheckIsSafeToFold, /*InsnID*/2,
        GIM_CheckIsSafeToFold, /*InsnID*/3,
        GIM_CheckComplexPattern, /*MI*/1, /*Op*/2, /*Renderer*/GIMT_Encode2(2), GIMT_Encode2(GICP_gi_vop3mods),
        GIM_CheckComplexPattern, /*MI*/2, /*Op*/1, /*Renderer*/GIMT_Encode2(0), GIMT_Encode2(GICP_gi_vop3mods),
        GIM_CheckComplexPattern, /*MI*/2, /*Op*/2, /*Renderer*/GIMT_Encode2(1), GIMT_Encode2(GICP_gi_vop3mods),
        // (fminnum:{ *:[f32] } (fmaxnum:{ *:[f32] } (fminnum_ieee:{ *:[f32] } (VOP3Mods:{ *:[f32] } f32:{ *:[f32] }:$src0, i32:{ *:[i32] }:$src0_mods), (VOP3Mods:{ *:[f32] } f32:{ *:[f32] }:$src1, i32:{ *:[i32] }:$src1_mods)), (VOP3Mods:{ *:[f32] } f32:{ *:[f32] }:$src2, i32:{ *:[i32] }:$src2_mods)), (fmaxnum_ieee:{ *:[f32] } (VOP3Mods:{ *:[f32] } f32:{ *:[f32] }:$src0, i32:{ *:[i32] }:$src0_mods), (VOP3Mods:{ *:[f32] } f32:{ *:[f32] }:$src1, i32:{ *:[i32] }:$src1_mods)))<<P:Predicate_fminnum_like_nnan>>  =>  (V_MED3_F32_e64:{ *:[f32] } ?:{ *:[i32] }:$src0_mods, ?:{ *:[f32] }:$src0, ?:{ *:[i32] }:$src1_mods, ?:{ *:[f32] }:$src1, ?:{ *:[i32] }:$src2_mods, ?:{ *:[f32] }:$src2, 0:{ *:[i1] }, 0:{ *:[i32] })
        GIR_BuildMI, /*InsnID*/0, /*Opcode*/GIMT_Encode2(AMDGPU::V_MED3_F32_e64),
        GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/0, // DstI[vdst]
        GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/1, // src0_mods
        GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/0, // src0
        GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(1), /*SubOperand*/1, // src1_mods
        GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(1), /*SubOperand*/0, // src1
        GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(2), /*SubOperand*/1, // src2_mods
        GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(2), /*SubOperand*/0, // src2
        GIR_AddImm8, /*InsnID*/0, /*Imm*/0,
        GIR_AddImm8, /*InsnID*/0, /*Imm*/0,
        GIR_ConstrainSelectedInstOperands, /*InsnID*/0,
        GIR_EraseFromParent, /*InsnID*/0,
        // GIR_Coverage, 10397,
        GIR_Done,
      // Label 4385: @277747
      GIM_Try, /*On fail goto*//*Label 4386*/ GIMT_Encode4(277887), // Rule ID 10398 //
        GIM_CheckRegBankForClass, /*MI*/0, /*Op*/0, /*RC*/GIMT_Encode2(AMDGPU::VGPR_32RegClassID),
        GIM_RecordInsn, /*DefineMI*/1, /*MI*/0, /*OpIdx*/1, // MIs[1]
        GIM_CheckOpcode, /*MI*/1, GIMT_Encode2(TargetOpcode::G_FMAXNUM),
        GIM_CheckType, /*MI*/1, /*Op*/1, /*Type*/GILLT_s32,
        GIM_CheckType, /*MI*/1, /*Op*/2, /*Type*/GILLT_s32,
        GIM_RecordInsn, /*DefineMI*/2, /*MI*/1, /*OpIdx*/1, // MIs[2]
        GIM_CheckOpcode, /*MI*/2, GIMT_Encode2(TargetOpcode::G_FMINNUM_IEEE),
        GIM_CheckType, /*MI*/2, /*Op*/1, /*Type*/GILLT_s32,
        GIM_CheckType, /*MI*/2, /*Op*/2, /*Type*/GILLT_s32,
        GIM_RecordInsn, /*DefineMI*/3, /*MI*/0, /*OpIdx*/2, // MIs[3]
        GIM_CheckOpcode, /*MI*/3, GIMT_Encode2(TargetOpcode::G_FMAXNUM_IEEE),
        // MIs[3] VOP3Mods:src1:src1_mods
        GIM_CheckIsSameOperand, /*MI*/3, /*OpIdx*/1, /*OtherMI*/2, /*OtherOpIdx*/2,
        // MIs[3] VOP3Mods:src0:src0_mods
        GIM_CheckIsSameOperand, /*MI*/3, /*OpIdx*/2, /*OtherMI*/2, /*OtherOpIdx*/1,
        GIM_CheckCxxInsnPredicate, /*MI*/0, /*FnId*/GIMT_Encode2(GICXXPred_MI_Predicate_fminnum_like_nnan),
        GIM_CheckIsSafeToFold, /*InsnID*/1,
        GIM_CheckIsSafeToFold, /*InsnID*/2,
        GIM_CheckIsSafeToFold, /*InsnID*/3,
        GIM_CheckComplexPattern, /*MI*/1, /*Op*/2, /*Renderer*/GIMT_Encode2(2), GIMT_Encode2(GICP_gi_vop3mods),
        GIM_CheckComplexPattern, /*MI*/2, /*Op*/1, /*Renderer*/GIMT_Encode2(0), GIMT_Encode2(GICP_gi_vop3mods),
        GIM_CheckComplexPattern, /*MI*/2, /*Op*/2, /*Renderer*/GIMT_Encode2(1), GIMT_Encode2(GICP_gi_vop3mods),
        // (fminnum:{ *:[f32] } (fmaxnum:{ *:[f32] } (fminnum_ieee:{ *:[f32] } (VOP3Mods:{ *:[f32] } f32:{ *:[f32] }:$src0, i32:{ *:[i32] }:$src0_mods), (VOP3Mods:{ *:[f32] } f32:{ *:[f32] }:$src1, i32:{ *:[i32] }:$src1_mods)), (VOP3Mods:{ *:[f32] } f32:{ *:[f32] }:$src2, i32:{ *:[i32] }:$src2_mods)), (fmaxnum_ieee:{ *:[f32] } (VOP3Mods:{ *:[f32] } f32:{ *:[f32] }:$src1, i32:{ *:[i32] }:$src1_mods), (VOP3Mods:{ *:[f32] } f32:{ *:[f32] }:$src0, i32:{ *:[i32] }:$src0_mods)))<<P:Predicate_fminnum_like_nnan>>  =>  (V_MED3_F32_e64:{ *:[f32] } ?:{ *:[i32] }:$src0_mods, ?:{ *:[f32] }:$src0, ?:{ *:[i32] }:$src1_mods, ?:{ *:[f32] }:$src1, ?:{ *:[i32] }:$src2_mods, ?:{ *:[f32] }:$src2, 0:{ *:[i1] }, 0:{ *:[i32] })
        GIR_BuildMI, /*InsnID*/0, /*Opcode*/GIMT_Encode2(AMDGPU::V_MED3_F32_e64),
        GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/0, // DstI[vdst]
        GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/1, // src0_mods
        GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/0, // src0
        GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(1), /*SubOperand*/1, // src1_mods
        GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(1), /*SubOperand*/0, // src1
        GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(2), /*SubOperand*/1, // src2_mods
        GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(2), /*SubOperand*/0, // src2
        GIR_AddImm8, /*InsnID*/0, /*Imm*/0,
        GIR_AddImm8, /*InsnID*/0, /*Imm*/0,
        GIR_ConstrainSelectedInstOperands, /*InsnID*/0,
        GIR_EraseFromParent, /*InsnID*/0,
        // GIR_Coverage, 10398,
        GIR_Done,
      // Label 4386: @277887
      GIM_Try, /*On fail goto*//*Label 4387*/ GIMT_Encode4(278027), // Rule ID 10399 //
        GIM_CheckRegBankForClass, /*MI*/0, /*Op*/0, /*RC*/GIMT_Encode2(AMDGPU::VGPR_32RegClassID),
        GIM_RecordInsn, /*DefineMI*/1, /*MI*/0, /*OpIdx*/1, // MIs[1]
        GIM_CheckOpcode, /*MI*/1, GIMT_Encode2(TargetOpcode::G_FMAXNUM),
        GIM_CheckType, /*MI*/1, /*Op*/1, /*Type*/GILLT_s32,
        GIM_CheckType, /*MI*/1, /*Op*/2, /*Type*/GILLT_s32,
        GIM_RecordInsn, /*DefineMI*/2, /*MI*/1, /*OpIdx*/1, // MIs[2]
        GIM_CheckOpcode, /*MI*/2, GIMT_Encode2(TargetOpcode::G_FMINNUM_IEEE),
        GIM_CheckType, /*MI*/2, /*Op*/1, /*Type*/GILLT_s32,
        GIM_CheckType, /*MI*/2, /*Op*/2, /*Type*/GILLT_s32,
        GIM_RecordInsn, /*DefineMI*/3, /*MI*/0, /*OpIdx*/2, // MIs[3]
        GIM_CheckOpcode, /*MI*/3, GIMT_Encode2(TargetOpcode::G_FMAXNUM_IEEE),
        // MIs[3] VOP3Mods:src0:src0_mods
        GIM_CheckIsSameOperand, /*MI*/3, /*OpIdx*/1, /*OtherMI*/2, /*OtherOpIdx*/2,
        // MIs[3] VOP3Mods:src1:src1_mods
        GIM_CheckIsSameOperand, /*MI*/3, /*OpIdx*/2, /*OtherMI*/2, /*OtherOpIdx*/1,
        GIM_CheckCxxInsnPredicate, /*MI*/0, /*FnId*/GIMT_Encode2(GICXXPred_MI_Predicate_fminnum_like_nnan),
        GIM_CheckIsSafeToFold, /*InsnID*/1,
        GIM_CheckIsSafeToFold, /*InsnID*/2,
        GIM_CheckIsSafeToFold, /*InsnID*/3,
        GIM_CheckComplexPattern, /*MI*/1, /*Op*/2, /*Renderer*/GIMT_Encode2(2), GIMT_Encode2(GICP_gi_vop3mods),
        GIM_CheckComplexPattern, /*MI*/2, /*Op*/1, /*Renderer*/GIMT_Encode2(0), GIMT_Encode2(GICP_gi_vop3mods),
        GIM_CheckComplexPattern, /*MI*/2, /*Op*/2, /*Renderer*/GIMT_Encode2(1), GIMT_Encode2(GICP_gi_vop3mods),
        // (fminnum:{ *:[f32] } (fmaxnum:{ *:[f32] } (fminnum_ieee:{ *:[f32] } (VOP3Mods:{ *:[f32] } f32:{ *:[f32] }:$src1, i32:{ *:[i32] }:$src1_mods), (VOP3Mods:{ *:[f32] } f32:{ *:[f32] }:$src0, i32:{ *:[i32] }:$src0_mods)), (VOP3Mods:{ *:[f32] } f32:{ *:[f32] }:$src2, i32:{ *:[i32] }:$src2_mods)), (fmaxnum_ieee:{ *:[f32] } (VOP3Mods:{ *:[f32] } f32:{ *:[f32] }:$src0, i32:{ *:[i32] }:$src0_mods), (VOP3Mods:{ *:[f32] } f32:{ *:[f32] }:$src1, i32:{ *:[i32] }:$src1_mods)))<<P:Predicate_fminnum_like_nnan>>  =>  (V_MED3_F32_e64:{ *:[f32] } ?:{ *:[i32] }:$src0_mods, ?:{ *:[f32] }:$src0, ?:{ *:[i32] }:$src1_mods, ?:{ *:[f32] }:$src1, ?:{ *:[i32] }:$src2_mods, ?:{ *:[f32] }:$src2, 0:{ *:[i1] }, 0:{ *:[i32] })
        GIR_BuildMI, /*InsnID*/0, /*Opcode*/GIMT_Encode2(AMDGPU::V_MED3_F32_e64),
        GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/0, // DstI[vdst]
        GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(1), /*SubOperand*/1, // src0_mods
        GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(1), /*SubOperand*/0, // src0
        GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/1, // src1_mods
        GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/0, // src1
        GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(2), /*SubOperand*/1, // src2_mods
        GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(2), /*SubOperand*/0, // src2
        GIR_AddImm8, /*InsnID*/0, /*Imm*/0,
        GIR_AddImm8, /*InsnID*/0, /*Imm*/0,
        GIR_ConstrainSelectedInstOperands, /*InsnID*/0,
        GIR_EraseFromParent, /*InsnID*/0,
        // GIR_Coverage, 10399,
        GIR_Done,
      // Label 4387: @278027
      GIM_Try, /*On fail goto*//*Label 4388*/ GIMT_Encode4(278167), // Rule ID 10400 //
        GIM_CheckRegBankForClass, /*MI*/0, /*Op*/0, /*RC*/GIMT_Encode2(AMDGPU::VGPR_32RegClassID),
        GIM_RecordInsn, /*DefineMI*/1, /*MI*/0, /*OpIdx*/1, // MIs[1]
        GIM_CheckOpcode, /*MI*/1, GIMT_Encode2(TargetOpcode::G_FMAXNUM),
        GIM_CheckType, /*MI*/1, /*Op*/1, /*Type*/GILLT_s32,
        GIM_CheckType, /*MI*/1, /*Op*/2, /*Type*/GILLT_s32,
        GIM_RecordInsn, /*DefineMI*/2, /*MI*/1, /*OpIdx*/1, // MIs[2]
        GIM_CheckOpcode, /*MI*/2, GIMT_Encode2(TargetOpcode::G_FMINNUM_IEEE),
        GIM_CheckType, /*MI*/2, /*Op*/1, /*Type*/GILLT_s32,
        GIM_CheckType, /*MI*/2, /*Op*/2, /*Type*/GILLT_s32,
        GIM_RecordInsn, /*DefineMI*/3, /*MI*/0, /*OpIdx*/2, // MIs[3]
        GIM_CheckOpcode, /*MI*/3, GIMT_Encode2(TargetOpcode::G_FMAXNUM_IEEE),
        // MIs[3] VOP3Mods:src1:src1_mods
        GIM_CheckIsSameOperand, /*MI*/3, /*OpIdx*/1, /*OtherMI*/2, /*OtherOpIdx*/1,
        // MIs[3] VOP3Mods:src0:src0_mods
        GIM_CheckIsSameOperand, /*MI*/3, /*OpIdx*/2, /*OtherMI*/2, /*OtherOpIdx*/2,
        GIM_CheckCxxInsnPredicate, /*MI*/0, /*FnId*/GIMT_Encode2(GICXXPred_MI_Predicate_fminnum_like_nnan),
        GIM_CheckIsSafeToFold, /*InsnID*/1,
        GIM_CheckIsSafeToFold, /*InsnID*/2,
        GIM_CheckIsSafeToFold, /*InsnID*/3,
        GIM_CheckComplexPattern, /*MI*/1, /*Op*/2, /*Renderer*/GIMT_Encode2(2), GIMT_Encode2(GICP_gi_vop3mods),
        GIM_CheckComplexPattern, /*MI*/2, /*Op*/1, /*Renderer*/GIMT_Encode2(0), GIMT_Encode2(GICP_gi_vop3mods),
        GIM_CheckComplexPattern, /*MI*/2, /*Op*/2, /*Renderer*/GIMT_Encode2(1), GIMT_Encode2(GICP_gi_vop3mods),
        // (fminnum:{ *:[f32] } (fmaxnum:{ *:[f32] } (fminnum_ieee:{ *:[f32] } (VOP3Mods:{ *:[f32] } f32:{ *:[f32] }:$src1, i32:{ *:[i32] }:$src1_mods), (VOP3Mods:{ *:[f32] } f32:{ *:[f32] }:$src0, i32:{ *:[i32] }:$src0_mods)), (VOP3Mods:{ *:[f32] } f32:{ *:[f32] }:$src2, i32:{ *:[i32] }:$src2_mods)), (fmaxnum_ieee:{ *:[f32] } (VOP3Mods:{ *:[f32] } f32:{ *:[f32] }:$src1, i32:{ *:[i32] }:$src1_mods), (VOP3Mods:{ *:[f32] } f32:{ *:[f32] }:$src0, i32:{ *:[i32] }:$src0_mods)))<<P:Predicate_fminnum_like_nnan>>  =>  (V_MED3_F32_e64:{ *:[f32] } ?:{ *:[i32] }:$src0_mods, ?:{ *:[f32] }:$src0, ?:{ *:[i32] }:$src1_mods, ?:{ *:[f32] }:$src1, ?:{ *:[i32] }:$src2_mods, ?:{ *:[f32] }:$src2, 0:{ *:[i1] }, 0:{ *:[i32] })
        GIR_BuildMI, /*InsnID*/0, /*Opcode*/GIMT_Encode2(AMDGPU::V_MED3_F32_e64),
        GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/0, // DstI[vdst]
        GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(1), /*SubOperand*/1, // src0_mods
        GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(1), /*SubOperand*/0, // src0
        GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/1, // src1_mods
        GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/0, // src1
        GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(2), /*SubOperand*/1, // src2_mods
        GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(2), /*SubOperand*/0, // src2
        GIR_AddImm8, /*InsnID*/0, /*Imm*/0,
        GIR_AddImm8, /*InsnID*/0, /*Imm*/0,
        GIR_ConstrainSelectedInstOperands, /*InsnID*/0,
        GIR_EraseFromParent, /*InsnID*/0,
        // GIR_Coverage, 10400,
        GIR_Done,
      // Label 4388: @278167
      GIM_Try, /*On fail goto*//*Label 4389*/ GIMT_Encode4(278307), // Rule ID 10406 //
        GIM_CheckRegBankForClass, /*MI*/0, /*Op*/0, /*RC*/GIMT_Encode2(AMDGPU::VGPR_32RegClassID),
        GIM_RecordInsn, /*DefineMI*/1, /*MI*/0, /*OpIdx*/1, // MIs[1]
        GIM_CheckOpcode, /*MI*/1, GIMT_Encode2(TargetOpcode::G_FMAXNUM_IEEE),
        GIM_CheckType, /*MI*/1, /*Op*/1, /*Type*/GILLT_s32,
        GIM_CheckType, /*MI*/1, /*Op*/2, /*Type*/GILLT_s32,
        GIM_RecordInsn, /*DefineMI*/2, /*MI*/0, /*OpIdx*/2, // MIs[2]
        GIM_CheckOpcode, /*MI*/2, GIMT_Encode2(TargetOpcode::G_FMAXNUM),
        GIM_CheckType, /*MI*/2, /*Op*/1, /*Type*/GILLT_s32,
        GIM_CheckType, /*MI*/2, /*Op*/2, /*Type*/GILLT_s32,
        GIM_RecordInsn, /*DefineMI*/3, /*MI*/2, /*OpIdx*/2, // MIs[3]
        GIM_CheckOpcode, /*MI*/3, GIMT_Encode2(TargetOpcode::G_FMINNUM),
        // MIs[3] VOP3Mods:src0:src0_mods
        GIM_CheckIsSameOperand, /*MI*/3, /*OpIdx*/1, /*OtherMI*/1, /*OtherOpIdx*/1,
        // MIs[3] VOP3Mods:src1:src1_mods
        GIM_CheckIsSameOperand, /*MI*/3, /*OpIdx*/2, /*OtherMI*/1, /*OtherOpIdx*/2,
        GIM_CheckCxxInsnPredicate, /*MI*/0, /*FnId*/GIMT_Encode2(GICXXPred_MI_Predicate_fminnum_like_nnan),
        GIM_CheckIsSafeToFold, /*InsnID*/1,
        GIM_CheckIsSafeToFold, /*InsnID*/2,
        GIM_CheckIsSafeToFold, /*InsnID*/3,
        GIM_CheckComplexPattern, /*MI*/1, /*Op*/1, /*Renderer*/GIMT_Encode2(0), GIMT_Encode2(GICP_gi_vop3mods),
        GIM_CheckComplexPattern, /*MI*/1, /*Op*/2, /*Renderer*/GIMT_Encode2(1), GIMT_Encode2(GICP_gi_vop3mods),
        GIM_CheckComplexPattern, /*MI*/2, /*Op*/1, /*Renderer*/GIMT_Encode2(2), GIMT_Encode2(GICP_gi_vop3mods),
        // (fminnum:{ *:[f32] } (fmaxnum_ieee:{ *:[f32] } (VOP3Mods:{ *:[f32] } f32:{ *:[f32] }:$src0, i32:{ *:[i32] }:$src0_mods), (VOP3Mods:{ *:[f32] } f32:{ *:[f32] }:$src1, i32:{ *:[i32] }:$src1_mods)), (fmaxnum:{ *:[f32] } (VOP3Mods:{ *:[f32] } f32:{ *:[f32] }:$src2, i32:{ *:[i32] }:$src2_mods), (fminnum:{ *:[f32] } (VOP3Mods:{ *:[f32] } f32:{ *:[f32] }:$src0, i32:{ *:[i32] }:$src0_mods), (VOP3Mods:{ *:[f32] } f32:{ *:[f32] }:$src1, i32:{ *:[i32] }:$src1_mods))))<<P:Predicate_fminnum_like_nnan>>  =>  (V_MED3_F32_e64:{ *:[f32] } ?:{ *:[i32] }:$src0_mods, ?:{ *:[f32] }:$src0, ?:{ *:[i32] }:$src1_mods, ?:{ *:[f32] }:$src1, ?:{ *:[i32] }:$src2_mods, ?:{ *:[f32] }:$src2, 0:{ *:[i1] }, 0:{ *:[i32] })
        GIR_BuildMI, /*InsnID*/0, /*Opcode*/GIMT_Encode2(AMDGPU::V_MED3_F32_e64),
        GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/0, // DstI[vdst]
        GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/1, // src0_mods
        GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/0, // src0
        GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(1), /*SubOperand*/1, // src1_mods
        GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(1), /*SubOperand*/0, // src1
        GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(2), /*SubOperand*/1, // src2_mods
        GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(2), /*SubOperand*/0, // src2
        GIR_AddImm8, /*InsnID*/0, /*Imm*/0,
        GIR_AddImm8, /*InsnID*/0, /*Imm*/0,
        GIR_ConstrainSelectedInstOperands, /*InsnID*/0,
        GIR_EraseFromParent, /*InsnID*/0,
        // GIR_Coverage, 10406,
        GIR_Done,
      // Label 4389: @278307
      GIM_Try, /*On fail goto*//*Label 4390*/ GIMT_Encode4(278447), // Rule ID 10407 //
        GIM_CheckRegBankForClass, /*MI*/0, /*Op*/0, /*RC*/GIMT_Encode2(AMDGPU::VGPR_32RegClassID),
        GIM_RecordInsn, /*DefineMI*/1, /*MI*/0, /*OpIdx*/1, // MIs[1]
        GIM_CheckOpcode, /*MI*/1, GIMT_Encode2(TargetOpcode::G_FMAXNUM_IEEE),
        GIM_CheckType, /*MI*/1, /*Op*/1, /*Type*/GILLT_s32,
        GIM_CheckType, /*MI*/1, /*Op*/2, /*Type*/GILLT_s32,
        GIM_RecordInsn, /*DefineMI*/2, /*MI*/0, /*OpIdx*/2, // MIs[2]
        GIM_CheckOpcode, /*MI*/2, GIMT_Encode2(TargetOpcode::G_FMAXNUM),
        GIM_CheckType, /*MI*/2, /*Op*/1, /*Type*/GILLT_s32,
        GIM_CheckType, /*MI*/2, /*Op*/2, /*Type*/GILLT_s32,
        GIM_RecordInsn, /*DefineMI*/3, /*MI*/2, /*OpIdx*/2, // MIs[3]
        GIM_CheckOpcode, /*MI*/3, GIMT_Encode2(TargetOpcode::G_FMINNUM),
        // MIs[3] VOP3Mods:src1:src1_mods
        GIM_CheckIsSameOperand, /*MI*/3, /*OpIdx*/1, /*OtherMI*/1, /*OtherOpIdx*/2,
        // MIs[3] VOP3Mods:src0:src0_mods
        GIM_CheckIsSameOperand, /*MI*/3, /*OpIdx*/2, /*OtherMI*/1, /*OtherOpIdx*/1,
        GIM_CheckCxxInsnPredicate, /*MI*/0, /*FnId*/GIMT_Encode2(GICXXPred_MI_Predicate_fminnum_like_nnan),
        GIM_CheckIsSafeToFold, /*InsnID*/1,
        GIM_CheckIsSafeToFold, /*InsnID*/2,
        GIM_CheckIsSafeToFold, /*InsnID*/3,
        GIM_CheckComplexPattern, /*MI*/1, /*Op*/1, /*Renderer*/GIMT_Encode2(0), GIMT_Encode2(GICP_gi_vop3mods),
        GIM_CheckComplexPattern, /*MI*/1, /*Op*/2, /*Renderer*/GIMT_Encode2(1), GIMT_Encode2(GICP_gi_vop3mods),
        GIM_CheckComplexPattern, /*MI*/2, /*Op*/1, /*Renderer*/GIMT_Encode2(2), GIMT_Encode2(GICP_gi_vop3mods),
        // (fminnum:{ *:[f32] } (fmaxnum_ieee:{ *:[f32] } (VOP3Mods:{ *:[f32] } f32:{ *:[f32] }:$src0, i32:{ *:[i32] }:$src0_mods), (VOP3Mods:{ *:[f32] } f32:{ *:[f32] }:$src1, i32:{ *:[i32] }:$src1_mods)), (fmaxnum:{ *:[f32] } (VOP3Mods:{ *:[f32] } f32:{ *:[f32] }:$src2, i32:{ *:[i32] }:$src2_mods), (fminnum:{ *:[f32] } (VOP3Mods:{ *:[f32] } f32:{ *:[f32] }:$src1, i32:{ *:[i32] }:$src1_mods), (VOP3Mods:{ *:[f32] } f32:{ *:[f32] }:$src0, i32:{ *:[i32] }:$src0_mods))))<<P:Predicate_fminnum_like_nnan>>  =>  (V_MED3_F32_e64:{ *:[f32] } ?:{ *:[i32] }:$src0_mods, ?:{ *:[f32] }:$src0, ?:{ *:[i32] }:$src1_mods, ?:{ *:[f32] }:$src1, ?:{ *:[i32] }:$src2_mods, ?:{ *:[f32] }:$src2, 0:{ *:[i1] }, 0:{ *:[i32] })
        GIR_BuildMI, /*InsnID*/0, /*Opcode*/GIMT_Encode2(AMDGPU::V_MED3_F32_e64),
        GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/0, // DstI[vdst]
        GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/1, // src0_mods
        GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/0, // src0
        GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(1), /*SubOperand*/1, // src1_mods
        GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(1), /*SubOperand*/0, // src1
        GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(2), /*SubOperand*/1, // src2_mods
        GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(2), /*SubOperand*/0, // src2
        GIR_AddImm8, /*InsnID*/0, /*Imm*/0,
        GIR_AddImm8, /*InsnID*/0, /*Imm*/0,
        GIR_ConstrainSelectedInstOperands, /*InsnID*/0,
        GIR_EraseFromParent, /*InsnID*/0,
        // GIR_Coverage, 10407,
        GIR_Done,
      // Label 4390: @278447
      GIM_Try, /*On fail goto*//*Label 4391*/ GIMT_Encode4(278587), // Rule ID 10410 //
        GIM_CheckRegBankForClass, /*MI*/0, /*Op*/0, /*RC*/GIMT_Encode2(AMDGPU::VGPR_32RegClassID),
        GIM_RecordInsn, /*DefineMI*/1, /*MI*/0, /*OpIdx*/1, // MIs[1]
        GIM_CheckOpcode, /*MI*/1, GIMT_Encode2(TargetOpcode::G_FMAXNUM_IEEE),
        GIM_CheckType, /*MI*/1, /*Op*/1, /*Type*/GILLT_s32,
        GIM_CheckType, /*MI*/1, /*Op*/2, /*Type*/GILLT_s32,
        GIM_RecordInsn, /*DefineMI*/2, /*MI*/0, /*OpIdx*/2, // MIs[2]
        GIM_CheckOpcode, /*MI*/2, GIMT_Encode2(TargetOpcode::G_FMAXNUM),
        GIM_CheckType, /*MI*/2, /*Op*/1, /*Type*/GILLT_s32,
        GIM_CheckType, /*MI*/2, /*Op*/2, /*Type*/GILLT_s32,
        GIM_RecordInsn, /*DefineMI*/3, /*MI*/2, /*OpIdx*/2, // MIs[3]
        GIM_CheckOpcode, /*MI*/3, GIMT_Encode2(TargetOpcode::G_FMINNUM),
        // MIs[3] VOP3Mods:src0:src0_mods
        GIM_CheckIsSameOperand, /*MI*/3, /*OpIdx*/1, /*OtherMI*/1, /*OtherOpIdx*/2,
        // MIs[3] VOP3Mods:src1:src1_mods
        GIM_CheckIsSameOperand, /*MI*/3, /*OpIdx*/2, /*OtherMI*/1, /*OtherOpIdx*/1,
        GIM_CheckCxxInsnPredicate, /*MI*/0, /*FnId*/GIMT_Encode2(GICXXPred_MI_Predicate_fminnum_like_nnan),
        GIM_CheckIsSafeToFold, /*InsnID*/1,
        GIM_CheckIsSafeToFold, /*InsnID*/2,
        GIM_CheckIsSafeToFold, /*InsnID*/3,
        GIM_CheckComplexPattern, /*MI*/1, /*Op*/1, /*Renderer*/GIMT_Encode2(0), GIMT_Encode2(GICP_gi_vop3mods),
        GIM_CheckComplexPattern, /*MI*/1, /*Op*/2, /*Renderer*/GIMT_Encode2(1), GIMT_Encode2(GICP_gi_vop3mods),
        GIM_CheckComplexPattern, /*MI*/2, /*Op*/1, /*Renderer*/GIMT_Encode2(2), GIMT_Encode2(GICP_gi_vop3mods),
        // (fminnum:{ *:[f32] } (fmaxnum_ieee:{ *:[f32] } (VOP3Mods:{ *:[f32] } f32:{ *:[f32] }:$src1, i32:{ *:[i32] }:$src1_mods), (VOP3Mods:{ *:[f32] } f32:{ *:[f32] }:$src0, i32:{ *:[i32] }:$src0_mods)), (fmaxnum:{ *:[f32] } (VOP3Mods:{ *:[f32] } f32:{ *:[f32] }:$src2, i32:{ *:[i32] }:$src2_mods), (fminnum:{ *:[f32] } (VOP3Mods:{ *:[f32] } f32:{ *:[f32] }:$src0, i32:{ *:[i32] }:$src0_mods), (VOP3Mods:{ *:[f32] } f32:{ *:[f32] }:$src1, i32:{ *:[i32] }:$src1_mods))))<<P:Predicate_fminnum_like_nnan>>  =>  (V_MED3_F32_e64:{ *:[f32] } ?:{ *:[i32] }:$src0_mods, ?:{ *:[f32] }:$src0, ?:{ *:[i32] }:$src1_mods, ?:{ *:[f32] }:$src1, ?:{ *:[i32] }:$src2_mods, ?:{ *:[f32] }:$src2, 0:{ *:[i1] }, 0:{ *:[i32] })
        GIR_BuildMI, /*InsnID*/0, /*Opcode*/GIMT_Encode2(AMDGPU::V_MED3_F32_e64),
        GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/0, // DstI[vdst]
        GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(1), /*SubOperand*/1, // src0_mods
        GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(1), /*SubOperand*/0, // src0
        GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/1, // src1_mods
        GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/0, // src1
        GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(2), /*SubOperand*/1, // src2_mods
        GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(2), /*SubOperand*/0, // src2
        GIR_AddImm8, /*InsnID*/0, /*Imm*/0,
        GIR_AddImm8, /*InsnID*/0, /*Imm*/0,
        GIR_ConstrainSelectedInstOperands, /*InsnID*/0,
        GIR_EraseFromParent, /*InsnID*/0,
        // GIR_Coverage, 10410,
        GIR_Done,
      // Label 4391: @278587
      GIM_Try, /*On fail goto*//*Label 4392*/ GIMT_Encode4(278727), // Rule ID 10411 //
        GIM_CheckRegBankForClass, /*MI*/0, /*Op*/0, /*RC*/GIMT_Encode2(AMDGPU::VGPR_32RegClassID),
        GIM_RecordInsn, /*DefineMI*/1, /*MI*/0, /*OpIdx*/1, // MIs[1]
        GIM_CheckOpcode, /*MI*/1, GIMT_Encode2(TargetOpcode::G_FMAXNUM_IEEE),
        GIM_CheckType, /*MI*/1, /*Op*/1, /*Type*/GILLT_s32,
        GIM_CheckType, /*MI*/1, /*Op*/2, /*Type*/GILLT_s32,
        GIM_RecordInsn, /*DefineMI*/2, /*MI*/0, /*OpIdx*/2, // MIs[2]
        GIM_CheckOpcode, /*MI*/2, GIMT_Encode2(TargetOpcode::G_FMAXNUM),
        GIM_CheckType, /*MI*/2, /*Op*/1, /*Type*/GILLT_s32,
        GIM_CheckType, /*MI*/2, /*Op*/2, /*Type*/GILLT_s32,
        GIM_RecordInsn, /*DefineMI*/3, /*MI*/2, /*OpIdx*/2, // MIs[3]
        GIM_CheckOpcode, /*MI*/3, GIMT_Encode2(TargetOpcode::G_FMINNUM),
        // MIs[3] VOP3Mods:src1:src1_mods
        GIM_CheckIsSameOperand, /*MI*/3, /*OpIdx*/1, /*OtherMI*/1, /*OtherOpIdx*/1,
        // MIs[3] VOP3Mods:src0:src0_mods
        GIM_CheckIsSameOperand, /*MI*/3, /*OpIdx*/2, /*OtherMI*/1, /*OtherOpIdx*/2,
        GIM_CheckCxxInsnPredicate, /*MI*/0, /*FnId*/GIMT_Encode2(GICXXPred_MI_Predicate_fminnum_like_nnan),
        GIM_CheckIsSafeToFold, /*InsnID*/1,
        GIM_CheckIsSafeToFold, /*InsnID*/2,
        GIM_CheckIsSafeToFold, /*InsnID*/3,
        GIM_CheckComplexPattern, /*MI*/1, /*Op*/1, /*Renderer*/GIMT_Encode2(0), GIMT_Encode2(GICP_gi_vop3mods),
        GIM_CheckComplexPattern, /*MI*/1, /*Op*/2, /*Renderer*/GIMT_Encode2(1), GIMT_Encode2(GICP_gi_vop3mods),
        GIM_CheckComplexPattern, /*MI*/2, /*Op*/1, /*Renderer*/GIMT_Encode2(2), GIMT_Encode2(GICP_gi_vop3mods),
        // (fminnum:{ *:[f32] } (fmaxnum_ieee:{ *:[f32] } (VOP3Mods:{ *:[f32] } f32:{ *:[f32] }:$src1, i32:{ *:[i32] }:$src1_mods), (VOP3Mods:{ *:[f32] } f32:{ *:[f32] }:$src0, i32:{ *:[i32] }:$src0_mods)), (fmaxnum:{ *:[f32] } (VOP3Mods:{ *:[f32] } f32:{ *:[f32] }:$src2, i32:{ *:[i32] }:$src2_mods), (fminnum:{ *:[f32] } (VOP3Mods:{ *:[f32] } f32:{ *:[f32] }:$src1, i32:{ *:[i32] }:$src1_mods), (VOP3Mods:{ *:[f32] } f32:{ *:[f32] }:$src0, i32:{ *:[i32] }:$src0_mods))))<<P:Predicate_fminnum_like_nnan>>  =>  (V_MED3_F32_e64:{ *:[f32] } ?:{ *:[i32] }:$src0_mods, ?:{ *:[f32] }:$src0, ?:{ *:[i32] }:$src1_mods, ?:{ *:[f32] }:$src1, ?:{ *:[i32] }:$src2_mods, ?:{ *:[f32] }:$src2, 0:{ *:[i1] }, 0:{ *:[i32] })
        GIR_BuildMI, /*InsnID*/0, /*Opcode*/GIMT_Encode2(AMDGPU::V_MED3_F32_e64),
        GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/0, // DstI[vdst]
        GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(1), /*SubOperand*/1, // src0_mods
        GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(1), /*SubOperand*/0, // src0
        GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/1, // src1_mods
        GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/0, // src1
        GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(2), /*SubOperand*/1, // src2_mods
        GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(2), /*SubOperand*/0, // src2
        GIR_AddImm8, /*InsnID*/0, /*Imm*/0,
        GIR_AddImm8, /*InsnID*/0, /*Imm*/0,
        GIR_ConstrainSelectedInstOperands, /*InsnID*/0,
        GIR_EraseFromParent, /*InsnID*/0,
        // GIR_Coverage, 10411,
        GIR_Done,
      // Label 4392: @278727
      GIM_Try, /*On fail goto*//*Label 4393*/ GIMT_Encode4(278867), // Rule ID 10391 //
        GIM_CheckRegBankForClass, /*MI*/0, /*Op*/0, /*RC*/GIMT_Encode2(AMDGPU::VGPR_32RegClassID),
        GIM_RecordInsn, /*DefineMI*/1, /*MI*/0, /*OpIdx*/1, // MIs[1]
        GIM_CheckOpcode, /*MI*/1, GIMT_Encode2(TargetOpcode::G_FMAXNUM_IEEE),
        GIM_CheckType, /*MI*/1, /*Op*/1, /*Type*/GILLT_s32,
        GIM_CheckType, /*MI*/1, /*Op*/2, /*Type*/GILLT_s32,
        GIM_RecordInsn, /*DefineMI*/2, /*MI*/0, /*OpIdx*/2, // MIs[2]
        GIM_CheckOpcode, /*MI*/2, GIMT_Encode2(TargetOpcode::G_FMAXNUM),
        GIM_CheckType, /*MI*/2, /*Op*/1, /*Type*/GILLT_s32,
        GIM_CheckType, /*MI*/2, /*Op*/2, /*Type*/GILLT_s32,
        GIM_RecordInsn, /*DefineMI*/3, /*MI*/2, /*OpIdx*/2, // MIs[3]
        GIM_CheckOpcode, /*MI*/3, GIMT_Encode2(TargetOpcode::G_FMINNUM_IEEE),
        // MIs[3] VOP3Mods:src0:src0_mods
        GIM_CheckIsSameOperand, /*MI*/3, /*OpIdx*/1, /*OtherMI*/1, /*OtherOpIdx*/1,
        // MIs[3] VOP3Mods:src1:src1_mods
        GIM_CheckIsSameOperand, /*MI*/3, /*OpIdx*/2, /*OtherMI*/1, /*OtherOpIdx*/2,
        GIM_CheckCxxInsnPredicate, /*MI*/0, /*FnId*/GIMT_Encode2(GICXXPred_MI_Predicate_fminnum_like_nnan),
        GIM_CheckIsSafeToFold, /*InsnID*/1,
        GIM_CheckIsSafeToFold, /*InsnID*/2,
        GIM_CheckIsSafeToFold, /*InsnID*/3,
        GIM_CheckComplexPattern, /*MI*/1, /*Op*/1, /*Renderer*/GIMT_Encode2(0), GIMT_Encode2(GICP_gi_vop3mods),
        GIM_CheckComplexPattern, /*MI*/1, /*Op*/2, /*Renderer*/GIMT_Encode2(1), GIMT_Encode2(GICP_gi_vop3mods),
        GIM_CheckComplexPattern, /*MI*/2, /*Op*/1, /*Renderer*/GIMT_Encode2(2), GIMT_Encode2(GICP_gi_vop3mods),
        // (fminnum:{ *:[f32] } (fmaxnum_ieee:{ *:[f32] } (VOP3Mods:{ *:[f32] } f32:{ *:[f32] }:$src0, i32:{ *:[i32] }:$src0_mods), (VOP3Mods:{ *:[f32] } f32:{ *:[f32] }:$src1, i32:{ *:[i32] }:$src1_mods)), (fmaxnum:{ *:[f32] } (VOP3Mods:{ *:[f32] } f32:{ *:[f32] }:$src2, i32:{ *:[i32] }:$src2_mods), (fminnum_ieee:{ *:[f32] } (VOP3Mods:{ *:[f32] } f32:{ *:[f32] }:$src0, i32:{ *:[i32] }:$src0_mods), (VOP3Mods:{ *:[f32] } f32:{ *:[f32] }:$src1, i32:{ *:[i32] }:$src1_mods))))<<P:Predicate_fminnum_like_nnan>>  =>  (V_MED3_F32_e64:{ *:[f32] } ?:{ *:[i32] }:$src0_mods, ?:{ *:[f32] }:$src0, ?:{ *:[i32] }:$src1_mods, ?:{ *:[f32] }:$src1, ?:{ *:[i32] }:$src2_mods, ?:{ *:[f32] }:$src2, 0:{ *:[i1] }, 0:{ *:[i32] })
        GIR_BuildMI, /*InsnID*/0, /*Opcode*/GIMT_Encode2(AMDGPU::V_MED3_F32_e64),
        GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/0, // DstI[vdst]
        GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/1, // src0_mods
        GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/0, // src0
        GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(1), /*SubOperand*/1, // src1_mods
        GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(1), /*SubOperand*/0, // src1
        GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(2), /*SubOperand*/1, // src2_mods
        GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(2), /*SubOperand*/0, // src2
        GIR_AddImm8, /*InsnID*/0, /*Imm*/0,
        GIR_AddImm8, /*InsnID*/0, /*Imm*/0,
        GIR_ConstrainSelectedInstOperands, /*InsnID*/0,
        GIR_EraseFromParent, /*InsnID*/0,
        // GIR_Coverage, 10391,
        GIR_Done,
      // Label 4393: @278867
      GIM_Try, /*On fail goto*//*Label 4394*/ GIMT_Encode4(279007), // Rule ID 10392 //
        GIM_CheckRegBankForClass, /*MI*/0, /*Op*/0, /*RC*/GIMT_Encode2(AMDGPU::VGPR_32RegClassID),
        GIM_RecordInsn, /*DefineMI*/1, /*MI*/0, /*OpIdx*/1, // MIs[1]
        GIM_CheckOpcode, /*MI*/1, GIMT_Encode2(TargetOpcode::G_FMAXNUM_IEEE),
        GIM_CheckType, /*MI*/1, /*Op*/1, /*Type*/GILLT_s32,
        GIM_CheckType, /*MI*/1, /*Op*/2, /*Type*/GILLT_s32,
        GIM_RecordInsn, /*DefineMI*/2, /*MI*/0, /*OpIdx*/2, // MIs[2]
        GIM_CheckOpcode, /*MI*/2, GIMT_Encode2(TargetOpcode::G_FMAXNUM),
        GIM_CheckType, /*MI*/2, /*Op*/1, /*Type*/GILLT_s32,
        GIM_CheckType, /*MI*/2, /*Op*/2, /*Type*/GILLT_s32,
        GIM_RecordInsn, /*DefineMI*/3, /*MI*/2, /*OpIdx*/2, // MIs[3]
        GIM_CheckOpcode, /*MI*/3, GIMT_Encode2(TargetOpcode::G_FMINNUM_IEEE),
        // MIs[3] VOP3Mods:src1:src1_mods
        GIM_CheckIsSameOperand, /*MI*/3, /*OpIdx*/1, /*OtherMI*/1, /*OtherOpIdx*/2,
        // MIs[3] VOP3Mods:src0:src0_mods
        GIM_CheckIsSameOperand, /*MI*/3, /*OpIdx*/2, /*OtherMI*/1, /*OtherOpIdx*/1,
        GIM_CheckCxxInsnPredicate, /*MI*/0, /*FnId*/GIMT_Encode2(GICXXPred_MI_Predicate_fminnum_like_nnan),
        GIM_CheckIsSafeToFold, /*InsnID*/1,
        GIM_CheckIsSafeToFold, /*InsnID*/2,
        GIM_CheckIsSafeToFold, /*InsnID*/3,
        GIM_CheckComplexPattern, /*MI*/1, /*Op*/1, /*Renderer*/GIMT_Encode2(0), GIMT_Encode2(GICP_gi_vop3mods),
        GIM_CheckComplexPattern, /*MI*/1, /*Op*/2, /*Renderer*/GIMT_Encode2(1), GIMT_Encode2(GICP_gi_vop3mods),
        GIM_CheckComplexPattern, /*MI*/2, /*Op*/1, /*Renderer*/GIMT_Encode2(2), GIMT_Encode2(GICP_gi_vop3mods),
        // (fminnum:{ *:[f32] } (fmaxnum_ieee:{ *:[f32] } (VOP3Mods:{ *:[f32] } f32:{ *:[f32] }:$src0, i32:{ *:[i32] }:$src0_mods), (VOP3Mods:{ *:[f32] } f32:{ *:[f32] }:$src1, i32:{ *:[i32] }:$src1_mods)), (fmaxnum:{ *:[f32] } (VOP3Mods:{ *:[f32] } f32:{ *:[f32] }:$src2, i32:{ *:[i32] }:$src2_mods), (fminnum_ieee:{ *:[f32] } (VOP3Mods:{ *:[f32] } f32:{ *:[f32] }:$src1, i32:{ *:[i32] }:$src1_mods), (VOP3Mods:{ *:[f32] } f32:{ *:[f32] }:$src0, i32:{ *:[i32] }:$src0_mods))))<<P:Predicate_fminnum_like_nnan>>  =>  (V_MED3_F32_e64:{ *:[f32] } ?:{ *:[i32] }:$src0_mods, ?:{ *:[f32] }:$src0, ?:{ *:[i32] }:$src1_mods, ?:{ *:[f32] }:$src1, ?:{ *:[i32] }:$src2_mods, ?:{ *:[f32] }:$src2, 0:{ *:[i1] }, 0:{ *:[i32] })
        GIR_BuildMI, /*InsnID*/0, /*Opcode*/GIMT_Encode2(AMDGPU::V_MED3_F32_e64),
        GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/0, // DstI[vdst]
        GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/1, // src0_mods
        GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/0, // src0
        GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(1), /*SubOperand*/1, // src1_mods
        GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(1), /*SubOperand*/0, // src1
        GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(2), /*SubOperand*/1, // src2_mods
        GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(2), /*SubOperand*/0, // src2
        GIR_AddImm8, /*InsnID*/0, /*Imm*/0,
        GIR_AddImm8, /*InsnID*/0, /*Imm*/0,
        GIR_ConstrainSelectedInstOperands, /*InsnID*/0,
        GIR_EraseFromParent, /*InsnID*/0,
        // GIR_Coverage, 10392,
        GIR_Done,
      // Label 4394: @279007
      GIM_Try, /*On fail goto*//*Label 4395*/ GIMT_Encode4(279147), // Rule ID 10395 //
        GIM_CheckRegBankForClass, /*MI*/0, /*Op*/0, /*RC*/GIMT_Encode2(AMDGPU::VGPR_32RegClassID),
        GIM_RecordInsn, /*DefineMI*/1, /*MI*/0, /*OpIdx*/1, // MIs[1]
        GIM_CheckOpcode, /*MI*/1, GIMT_Encode2(TargetOpcode::G_FMAXNUM_IEEE),
        GIM_CheckType, /*MI*/1, /*Op*/1, /*Type*/GILLT_s32,
        GIM_CheckType, /*MI*/1, /*Op*/2, /*Type*/GILLT_s32,
        GIM_RecordInsn, /*DefineMI*/2, /*MI*/0, /*OpIdx*/2, // MIs[2]
        GIM_CheckOpcode, /*MI*/2, GIMT_Encode2(TargetOpcode::G_FMAXNUM),
        GIM_CheckType, /*MI*/2, /*Op*/1, /*Type*/GILLT_s32,
        GIM_CheckType, /*MI*/2, /*Op*/2, /*Type*/GILLT_s32,
        GIM_RecordInsn, /*DefineMI*/3, /*MI*/2, /*OpIdx*/2, // MIs[3]
        GIM_CheckOpcode, /*MI*/3, GIMT_Encode2(TargetOpcode::G_FMINNUM_IEEE),
        // MIs[3] VOP3Mods:src0:src0_mods
        GIM_CheckIsSameOperand, /*MI*/3, /*OpIdx*/1, /*OtherMI*/1, /*OtherOpIdx*/2,
        // MIs[3] VOP3Mods:src1:src1_mods
        GIM_CheckIsSameOperand, /*MI*/3, /*OpIdx*/2, /*OtherMI*/1, /*OtherOpIdx*/1,
        GIM_CheckCxxInsnPredicate, /*MI*/0, /*FnId*/GIMT_Encode2(GICXXPred_MI_Predicate_fminnum_like_nnan),
        GIM_CheckIsSafeToFold, /*InsnID*/1,
        GIM_CheckIsSafeToFold, /*InsnID*/2,
        GIM_CheckIsSafeToFold, /*InsnID*/3,
        GIM_CheckComplexPattern, /*MI*/1, /*Op*/1, /*Renderer*/GIMT_Encode2(0), GIMT_Encode2(GICP_gi_vop3mods),
        GIM_CheckComplexPattern, /*MI*/1, /*Op*/2, /*Renderer*/GIMT_Encode2(1), GIMT_Encode2(GICP_gi_vop3mods),
        GIM_CheckComplexPattern, /*MI*/2, /*Op*/1, /*Renderer*/GIMT_Encode2(2), GIMT_Encode2(GICP_gi_vop3mods),
        // (fminnum:{ *:[f32] } (fmaxnum_ieee:{ *:[f32] } (VOP3Mods:{ *:[f32] } f32:{ *:[f32] }:$src1, i32:{ *:[i32] }:$src1_mods), (VOP3Mods:{ *:[f32] } f32:{ *:[f32] }:$src0, i32:{ *:[i32] }:$src0_mods)), (fmaxnum:{ *:[f32] } (VOP3Mods:{ *:[f32] } f32:{ *:[f32] }:$src2, i32:{ *:[i32] }:$src2_mods), (fminnum_ieee:{ *:[f32] } (VOP3Mods:{ *:[f32] } f32:{ *:[f32] }:$src0, i32:{ *:[i32] }:$src0_mods), (VOP3Mods:{ *:[f32] } f32:{ *:[f32] }:$src1, i32:{ *:[i32] }:$src1_mods))))<<P:Predicate_fminnum_like_nnan>>  =>  (V_MED3_F32_e64:{ *:[f32] } ?:{ *:[i32] }:$src0_mods, ?:{ *:[f32] }:$src0, ?:{ *:[i32] }:$src1_mods, ?:{ *:[f32] }:$src1, ?:{ *:[i32] }:$src2_mods, ?:{ *:[f32] }:$src2, 0:{ *:[i1] }, 0:{ *:[i32] })
        GIR_BuildMI, /*InsnID*/0, /*Opcode*/GIMT_Encode2(AMDGPU::V_MED3_F32_e64),
        GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/0, // DstI[vdst]
        GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(1), /*SubOperand*/1, // src0_mods
        GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(1), /*SubOperand*/0, // src0
        GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/1, // src1_mods
        GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/0, // src1
        GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(2), /*SubOperand*/1, // src2_mods
        GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(2), /*SubOperand*/0, // src2
        GIR_AddImm8, /*InsnID*/0, /*Imm*/0,
        GIR_AddImm8, /*InsnID*/0, /*Imm*/0,
        GIR_ConstrainSelectedInstOperands, /*InsnID*/0,
        GIR_EraseFromParent, /*InsnID*/0,
        // GIR_Coverage, 10395,
        GIR_Done,
      // Label 4395: @279147
      GIM_Try, /*On fail goto*//*Label 4396*/ GIMT_Encode4(279287), // Rule ID 10396 //
        GIM_CheckRegBankForClass, /*MI*/0, /*Op*/0, /*RC*/GIMT_Encode2(AMDGPU::VGPR_32RegClassID),
        GIM_RecordInsn, /*DefineMI*/1, /*MI*/0, /*OpIdx*/1, // MIs[1]
        GIM_CheckOpcode, /*MI*/1, GIMT_Encode2(TargetOpcode::G_FMAXNUM_IEEE),
        GIM_CheckType, /*MI*/1, /*Op*/1, /*Type*/GILLT_s32,
        GIM_CheckType, /*MI*/1, /*Op*/2, /*Type*/GILLT_s32,
        GIM_RecordInsn, /*DefineMI*/2, /*MI*/0, /*OpIdx*/2, // MIs[2]
        GIM_CheckOpcode, /*MI*/2, GIMT_Encode2(TargetOpcode::G_FMAXNUM),
        GIM_CheckType, /*MI*/2, /*Op*/1, /*Type*/GILLT_s32,
        GIM_CheckType, /*MI*/2, /*Op*/2, /*Type*/GILLT_s32,
        GIM_RecordInsn, /*DefineMI*/3, /*MI*/2, /*OpIdx*/2, // MIs[3]
        GIM_CheckOpcode, /*MI*/3, GIMT_Encode2(TargetOpcode::G_FMINNUM_IEEE),
        // MIs[3] VOP3Mods:src1:src1_mods
        GIM_CheckIsSameOperand, /*MI*/3, /*OpIdx*/1, /*OtherMI*/1, /*OtherOpIdx*/1,
        // MIs[3] VOP3Mods:src0:src0_mods
        GIM_CheckIsSameOperand, /*MI*/3, /*OpIdx*/2, /*OtherMI*/1, /*OtherOpIdx*/2,
        GIM_CheckCxxInsnPredicate, /*MI*/0, /*FnId*/GIMT_Encode2(GICXXPred_MI_Predicate_fminnum_like_nnan),
        GIM_CheckIsSafeToFold, /*InsnID*/1,
        GIM_CheckIsSafeToFold, /*InsnID*/2,
        GIM_CheckIsSafeToFold, /*InsnID*/3,
        GIM_CheckComplexPattern, /*MI*/1, /*Op*/1, /*Renderer*/GIMT_Encode2(0), GIMT_Encode2(GICP_gi_vop3mods),
        GIM_CheckComplexPattern, /*MI*/1, /*Op*/2, /*Renderer*/GIMT_Encode2(1), GIMT_Encode2(GICP_gi_vop3mods),
        GIM_CheckComplexPattern, /*MI*/2, /*Op*/1, /*Renderer*/GIMT_Encode2(2), GIMT_Encode2(GICP_gi_vop3mods),
        // (fminnum:{ *:[f32] } (fmaxnum_ieee:{ *:[f32] } (VOP3Mods:{ *:[f32] } f32:{ *:[f32] }:$src1, i32:{ *:[i32] }:$src1_mods), (VOP3Mods:{ *:[f32] } f32:{ *:[f32] }:$src0, i32:{ *:[i32] }:$src0_mods)), (fmaxnum:{ *:[f32] } (VOP3Mods:{ *:[f32] } f32:{ *:[f32] }:$src2, i32:{ *:[i32] }:$src2_mods), (fminnum_ieee:{ *:[f32] } (VOP3Mods:{ *:[f32] } f32:{ *:[f32] }:$src1, i32:{ *:[i32] }:$src1_mods), (VOP3Mods:{ *:[f32] } f32:{ *:[f32] }:$src0, i32:{ *:[i32] }:$src0_mods))))<<P:Predicate_fminnum_like_nnan>>  =>  (V_MED3_F32_e64:{ *:[f32] } ?:{ *:[i32] }:$src0_mods, ?:{ *:[f32] }:$src0, ?:{ *:[i32] }:$src1_mods, ?:{ *:[f32] }:$src1, ?:{ *:[i32] }:$src2_mods, ?:{ *:[f32] }:$src2, 0:{ *:[i1] }, 0:{ *:[i32] })
        GIR_BuildMI, /*InsnID*/0, /*Opcode*/GIMT_Encode2(AMDGPU::V_MED3_F32_e64),
        GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/0, // DstI[vdst]
        GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(1), /*SubOperand*/1, // src0_mods
        GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(1), /*SubOperand*/0, // src0
        GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/1, // src1_mods
        GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/0, // src1
        GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(2), /*SubOperand*/1, // src2_mods
        GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(2), /*SubOperand*/0, // src2
        GIR_AddImm8, /*InsnID*/0, /*Imm*/0,
        GIR_AddImm8, /*InsnID*/0, /*Imm*/0,
        GIR_ConstrainSelectedInstOperands, /*InsnID*/0,
        GIR_EraseFromParent, /*InsnID*/0,
        // GIR_Coverage, 10396,
        GIR_Done,
      // Label 4396: @279287
      GIM_Try, /*On fail goto*//*Label 4397*/ GIMT_Encode4(279427), // Rule ID 6509 //
        GIM_CheckRegBankForClass, /*MI*/0, /*Op*/0, /*RC*/GIMT_Encode2(AMDGPU::VGPR_32RegClassID),
        GIM_RecordInsn, /*DefineMI*/1, /*MI*/0, /*OpIdx*/1, // MIs[1]
        GIM_CheckOpcode, /*MI*/1, GIMT_Encode2(TargetOpcode::G_FMAXNUM_IEEE),
        GIM_CheckType, /*MI*/1, /*Op*/1, /*Type*/GILLT_s32,
        GIM_CheckType, /*MI*/1, /*Op*/2, /*Type*/GILLT_s32,
        GIM_RecordInsn, /*DefineMI*/2, /*MI*/0, /*OpIdx*/2, // MIs[2]
        GIM_CheckOpcode, /*MI*/2, GIMT_Encode2(TargetOpcode::G_FMAXNUM),
        GIM_CheckType, /*MI*/2, /*Op*/1, /*Type*/GILLT_s32,
        GIM_CheckType, /*MI*/2, /*Op*/2, /*Type*/GILLT_s32,
        GIM_RecordInsn, /*DefineMI*/3, /*MI*/2, /*OpIdx*/1, // MIs[3]
        GIM_CheckOpcode, /*MI*/3, GIMT_Encode2(TargetOpcode::G_FMINNUM),
        // MIs[3] VOP3Mods:src0:src0_mods
        GIM_CheckIsSameOperand, /*MI*/3, /*OpIdx*/1, /*OtherMI*/1, /*OtherOpIdx*/1,
        // MIs[3] VOP3Mods:src1:src1_mods
        GIM_CheckIsSameOperand, /*MI*/3, /*OpIdx*/2, /*OtherMI*/1, /*OtherOpIdx*/2,
        GIM_CheckCxxInsnPredicate, /*MI*/0, /*FnId*/GIMT_Encode2(GICXXPred_MI_Predicate_fminnum_like_nnan),
        GIM_CheckIsSafeToFold, /*InsnID*/1,
        GIM_CheckIsSafeToFold, /*InsnID*/2,
        GIM_CheckIsSafeToFold, /*InsnID*/3,
        GIM_CheckComplexPattern, /*MI*/1, /*Op*/1, /*Renderer*/GIMT_Encode2(0), GIMT_Encode2(GICP_gi_vop3mods),
        GIM_CheckComplexPattern, /*MI*/1, /*Op*/2, /*Renderer*/GIMT_Encode2(1), GIMT_Encode2(GICP_gi_vop3mods),
        GIM_CheckComplexPattern, /*MI*/2, /*Op*/2, /*Renderer*/GIMT_Encode2(2), GIMT_Encode2(GICP_gi_vop3mods),
        // (fminnum:{ *:[f32] } (fmaxnum_ieee:{ *:[f32] } (VOP3Mods:{ *:[f32] } f32:{ *:[f32] }:$src0, i32:{ *:[i32] }:$src0_mods), (VOP3Mods:{ *:[f32] } f32:{ *:[f32] }:$src1, i32:{ *:[i32] }:$src1_mods)), (fmaxnum:{ *:[f32] } (fminnum:{ *:[f32] } (VOP3Mods:{ *:[f32] } f32:{ *:[f32] }:$src0, i32:{ *:[i32] }:$src0_mods), (VOP3Mods:{ *:[f32] } f32:{ *:[f32] }:$src1, i32:{ *:[i32] }:$src1_mods)), (VOP3Mods:{ *:[f32] } f32:{ *:[f32] }:$src2, i32:{ *:[i32] }:$src2_mods)))<<P:Predicate_fminnum_like_nnan>>  =>  (V_MED3_F32_e64:{ *:[f32] } ?:{ *:[i32] }:$src0_mods, ?:{ *:[f32] }:$src0, ?:{ *:[i32] }:$src1_mods, ?:{ *:[f32] }:$src1, ?:{ *:[i32] }:$src2_mods, ?:{ *:[f32] }:$src2, 0:{ *:[i1] }, 0:{ *:[i32] })
        GIR_BuildMI, /*InsnID*/0, /*Opcode*/GIMT_Encode2(AMDGPU::V_MED3_F32_e64),
        GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/0, // DstI[vdst]
        GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/1, // src0_mods
        GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/0, // src0
        GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(1), /*SubOperand*/1, // src1_mods
        GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(1), /*SubOperand*/0, // src1
        GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(2), /*SubOperand*/1, // src2_mods
        GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(2), /*SubOperand*/0, // src2
        GIR_AddImm8, /*InsnID*/0, /*Imm*/0,
        GIR_AddImm8, /*InsnID*/0, /*Imm*/0,
        GIR_ConstrainSelectedInstOperands, /*InsnID*/0,
        GIR_EraseFromParent, /*InsnID*/0,
        // GIR_Coverage, 6509,
        GIR_Done,
      // Label 4397: @279427
      GIM_Try, /*On fail goto*//*Label 4398*/ GIMT_Encode4(279567), // Rule ID 10405 //
        GIM_CheckRegBankForClass, /*MI*/0, /*Op*/0, /*RC*/GIMT_Encode2(AMDGPU::VGPR_32RegClassID),
        GIM_RecordInsn, /*DefineMI*/1, /*MI*/0, /*OpIdx*/1, // MIs[1]
        GIM_CheckOpcode, /*MI*/1, GIMT_Encode2(TargetOpcode::G_FMAXNUM_IEEE),
        GIM_CheckType, /*MI*/1, /*Op*/1, /*Type*/GILLT_s32,
        GIM_CheckType, /*MI*/1, /*Op*/2, /*Type*/GILLT_s32,
        GIM_RecordInsn, /*DefineMI*/2, /*MI*/0, /*OpIdx*/2, // MIs[2]
        GIM_CheckOpcode, /*MI*/2, GIMT_Encode2(TargetOpcode::G_FMAXNUM),
        GIM_CheckType, /*MI*/2, /*Op*/1, /*Type*/GILLT_s32,
        GIM_CheckType, /*MI*/2, /*Op*/2, /*Type*/GILLT_s32,
        GIM_RecordInsn, /*DefineMI*/3, /*MI*/2, /*OpIdx*/1, // MIs[3]
        GIM_CheckOpcode, /*MI*/3, GIMT_Encode2(TargetOpcode::G_FMINNUM),
        // MIs[3] VOP3Mods:src1:src1_mods
        GIM_CheckIsSameOperand, /*MI*/3, /*OpIdx*/1, /*OtherMI*/1, /*OtherOpIdx*/2,
        // MIs[3] VOP3Mods:src0:src0_mods
        GIM_CheckIsSameOperand, /*MI*/3, /*OpIdx*/2, /*OtherMI*/1, /*OtherOpIdx*/1,
        GIM_CheckCxxInsnPredicate, /*MI*/0, /*FnId*/GIMT_Encode2(GICXXPred_MI_Predicate_fminnum_like_nnan),
        GIM_CheckIsSafeToFold, /*InsnID*/1,
        GIM_CheckIsSafeToFold, /*InsnID*/2,
        GIM_CheckIsSafeToFold, /*InsnID*/3,
        GIM_CheckComplexPattern, /*MI*/1, /*Op*/1, /*Renderer*/GIMT_Encode2(0), GIMT_Encode2(GICP_gi_vop3mods),
        GIM_CheckComplexPattern, /*MI*/1, /*Op*/2, /*Renderer*/GIMT_Encode2(1), GIMT_Encode2(GICP_gi_vop3mods),
        GIM_CheckComplexPattern, /*MI*/2, /*Op*/2, /*Renderer*/GIMT_Encode2(2), GIMT_Encode2(GICP_gi_vop3mods),
        // (fminnum:{ *:[f32] } (fmaxnum_ieee:{ *:[f32] } (VOP3Mods:{ *:[f32] } f32:{ *:[f32] }:$src0, i32:{ *:[i32] }:$src0_mods), (VOP3Mods:{ *:[f32] } f32:{ *:[f32] }:$src1, i32:{ *:[i32] }:$src1_mods)), (fmaxnum:{ *:[f32] } (fminnum:{ *:[f32] } (VOP3Mods:{ *:[f32] } f32:{ *:[f32] }:$src1, i32:{ *:[i32] }:$src1_mods), (VOP3Mods:{ *:[f32] } f32:{ *:[f32] }:$src0, i32:{ *:[i32] }:$src0_mods)), (VOP3Mods:{ *:[f32] } f32:{ *:[f32] }:$src2, i32:{ *:[i32] }:$src2_mods)))<<P:Predicate_fminnum_like_nnan>>  =>  (V_MED3_F32_e64:{ *:[f32] } ?:{ *:[i32] }:$src0_mods, ?:{ *:[f32] }:$src0, ?:{ *:[i32] }:$src1_mods, ?:{ *:[f32] }:$src1, ?:{ *:[i32] }:$src2_mods, ?:{ *:[f32] }:$src2, 0:{ *:[i1] }, 0:{ *:[i32] })
        GIR_BuildMI, /*InsnID*/0, /*Opcode*/GIMT_Encode2(AMDGPU::V_MED3_F32_e64),
        GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/0, // DstI[vdst]
        GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/1, // src0_mods
        GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/0, // src0
        GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(1), /*SubOperand*/1, // src1_mods
        GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(1), /*SubOperand*/0, // src1
        GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(2), /*SubOperand*/1, // src2_mods
        GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(2), /*SubOperand*/0, // src2
        GIR_AddImm8, /*InsnID*/0, /*Imm*/0,
        GIR_AddImm8, /*InsnID*/0, /*Imm*/0,
        GIR_ConstrainSelectedInstOperands, /*InsnID*/0,
        GIR_EraseFromParent, /*InsnID*/0,
        // GIR_Coverage, 10405,
        GIR_Done,
      // Label 4398: @279567
      GIM_Try, /*On fail goto*//*Label 4399*/ GIMT_Encode4(279707), // Rule ID 10408 //
        GIM_CheckRegBankForClass, /*MI*/0, /*Op*/0, /*RC*/GIMT_Encode2(AMDGPU::VGPR_32RegClassID),
        GIM_RecordInsn, /*DefineMI*/1, /*MI*/0, /*OpIdx*/1, // MIs[1]
        GIM_CheckOpcode, /*MI*/1, GIMT_Encode2(TargetOpcode::G_FMAXNUM_IEEE),
        GIM_CheckType, /*MI*/1, /*Op*/1, /*Type*/GILLT_s32,
        GIM_CheckType, /*MI*/1, /*Op*/2, /*Type*/GILLT_s32,
        GIM_RecordInsn, /*DefineMI*/2, /*MI*/0, /*OpIdx*/2, // MIs[2]
        GIM_CheckOpcode, /*MI*/2, GIMT_Encode2(TargetOpcode::G_FMAXNUM),
        GIM_CheckType, /*MI*/2, /*Op*/1, /*Type*/GILLT_s32,
        GIM_CheckType, /*MI*/2, /*Op*/2, /*Type*/GILLT_s32,
        GIM_RecordInsn, /*DefineMI*/3, /*MI*/2, /*OpIdx*/1, // MIs[3]
        GIM_CheckOpcode, /*MI*/3, GIMT_Encode2(TargetOpcode::G_FMINNUM),
        // MIs[3] VOP3Mods:src0:src0_mods
        GIM_CheckIsSameOperand, /*MI*/3, /*OpIdx*/1, /*OtherMI*/1, /*OtherOpIdx*/2,
        // MIs[3] VOP3Mods:src1:src1_mods
        GIM_CheckIsSameOperand, /*MI*/3, /*OpIdx*/2, /*OtherMI*/1, /*OtherOpIdx*/1,
        GIM_CheckCxxInsnPredicate, /*MI*/0, /*FnId*/GIMT_Encode2(GICXXPred_MI_Predicate_fminnum_like_nnan),
        GIM_CheckIsSafeToFold, /*InsnID*/1,
        GIM_CheckIsSafeToFold, /*InsnID*/2,
        GIM_CheckIsSafeToFold, /*InsnID*/3,
        GIM_CheckComplexPattern, /*MI*/1, /*Op*/1, /*Renderer*/GIMT_Encode2(0), GIMT_Encode2(GICP_gi_vop3mods),
        GIM_CheckComplexPattern, /*MI*/1, /*Op*/2, /*Renderer*/GIMT_Encode2(1), GIMT_Encode2(GICP_gi_vop3mods),
        GIM_CheckComplexPattern, /*MI*/2, /*Op*/2, /*Renderer*/GIMT_Encode2(2), GIMT_Encode2(GICP_gi_vop3mods),
        // (fminnum:{ *:[f32] } (fmaxnum_ieee:{ *:[f32] } (VOP3Mods:{ *:[f32] } f32:{ *:[f32] }:$src1, i32:{ *:[i32] }:$src1_mods), (VOP3Mods:{ *:[f32] } f32:{ *:[f32] }:$src0, i32:{ *:[i32] }:$src0_mods)), (fmaxnum:{ *:[f32] } (fminnum:{ *:[f32] } (VOP3Mods:{ *:[f32] } f32:{ *:[f32] }:$src0, i32:{ *:[i32] }:$src0_mods), (VOP3Mods:{ *:[f32] } f32:{ *:[f32] }:$src1, i32:{ *:[i32] }:$src1_mods)), (VOP3Mods:{ *:[f32] } f32:{ *:[f32] }:$src2, i32:{ *:[i32] }:$src2_mods)))<<P:Predicate_fminnum_like_nnan>>  =>  (V_MED3_F32_e64:{ *:[f32] } ?:{ *:[i32] }:$src0_mods, ?:{ *:[f32] }:$src0, ?:{ *:[i32] }:$src1_mods, ?:{ *:[f32] }:$src1, ?:{ *:[i32] }:$src2_mods, ?:{ *:[f32] }:$src2, 0:{ *:[i1] }, 0:{ *:[i32] })
        GIR_BuildMI, /*InsnID*/0, /*Opcode*/GIMT_Encode2(AMDGPU::V_MED3_F32_e64),
        GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/0, // DstI[vdst]
        GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(1), /*SubOperand*/1, // src0_mods
        GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(1), /*SubOperand*/0, // src0
        GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/1, // src1_mods
        GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/0, // src1
        GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(2), /*SubOperand*/1, // src2_mods
        GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(2), /*SubOperand*/0, // src2
        GIR_AddImm8, /*InsnID*/0, /*Imm*/0,
        GIR_AddImm8, /*InsnID*/0, /*Imm*/0,
        GIR_ConstrainSelectedInstOperands, /*InsnID*/0,
        GIR_EraseFromParent, /*InsnID*/0,
        // GIR_Coverage, 10408,
        GIR_Done,
      // Label 4399: @279707
      GIM_Try, /*On fail goto*//*Label 4400*/ GIMT_Encode4(279847), // Rule ID 10409 //
        GIM_CheckRegBankForClass, /*MI*/0, /*Op*/0, /*RC*/GIMT_Encode2(AMDGPU::VGPR_32RegClassID),
        GIM_RecordInsn, /*DefineMI*/1, /*MI*/0, /*OpIdx*/1, // MIs[1]
        GIM_CheckOpcode, /*MI*/1, GIMT_Encode2(TargetOpcode::G_FMAXNUM_IEEE),
        GIM_CheckType, /*MI*/1, /*Op*/1, /*Type*/GILLT_s32,
        GIM_CheckType, /*MI*/1, /*Op*/2, /*Type*/GILLT_s32,
        GIM_RecordInsn, /*DefineMI*/2, /*MI*/0, /*OpIdx*/2, // MIs[2]
        GIM_CheckOpcode, /*MI*/2, GIMT_Encode2(TargetOpcode::G_FMAXNUM),
        GIM_CheckType, /*MI*/2, /*Op*/1, /*Type*/GILLT_s32,
        GIM_CheckType, /*MI*/2, /*Op*/2, /*Type*/GILLT_s32,
        GIM_RecordInsn, /*DefineMI*/3, /*MI*/2, /*OpIdx*/1, // MIs[3]
        GIM_CheckOpcode, /*MI*/3, GIMT_Encode2(TargetOpcode::G_FMINNUM),
        // MIs[3] VOP3Mods:src1:src1_mods
        GIM_CheckIsSameOperand, /*MI*/3, /*OpIdx*/1, /*OtherMI*/1, /*OtherOpIdx*/1,
        // MIs[3] VOP3Mods:src0:src0_mods
        GIM_CheckIsSameOperand, /*MI*/3, /*OpIdx*/2, /*OtherMI*/1, /*OtherOpIdx*/2,
        GIM_CheckCxxInsnPredicate, /*MI*/0, /*FnId*/GIMT_Encode2(GICXXPred_MI_Predicate_fminnum_like_nnan),
        GIM_CheckIsSafeToFold, /*InsnID*/1,
        GIM_CheckIsSafeToFold, /*InsnID*/2,
        GIM_CheckIsSafeToFold, /*InsnID*/3,
        GIM_CheckComplexPattern, /*MI*/1, /*Op*/1, /*Renderer*/GIMT_Encode2(0), GIMT_Encode2(GICP_gi_vop3mods),
        GIM_CheckComplexPattern, /*MI*/1, /*Op*/2, /*Renderer*/GIMT_Encode2(1), GIMT_Encode2(GICP_gi_vop3mods),
        GIM_CheckComplexPattern, /*MI*/2, /*Op*/2, /*Renderer*/GIMT_Encode2(2), GIMT_Encode2(GICP_gi_vop3mods),
        // (fminnum:{ *:[f32] } (fmaxnum_ieee:{ *:[f32] } (VOP3Mods:{ *:[f32] } f32:{ *:[f32] }:$src1, i32:{ *:[i32] }:$src1_mods), (VOP3Mods:{ *:[f32] } f32:{ *:[f32] }:$src0, i32:{ *:[i32] }:$src0_mods)), (fmaxnum:{ *:[f32] } (fminnum:{ *:[f32] } (VOP3Mods:{ *:[f32] } f32:{ *:[f32] }:$src1, i32:{ *:[i32] }:$src1_mods), (VOP3Mods:{ *:[f32] } f32:{ *:[f32] }:$src0, i32:{ *:[i32] }:$src0_mods)), (VOP3Mods:{ *:[f32] } f32:{ *:[f32] }:$src2, i32:{ *:[i32] }:$src2_mods)))<<P:Predicate_fminnum_like_nnan>>  =>  (V_MED3_F32_e64:{ *:[f32] } ?:{ *:[i32] }:$src0_mods, ?:{ *:[f32] }:$src0, ?:{ *:[i32] }:$src1_mods, ?:{ *:[f32] }:$src1, ?:{ *:[i32] }:$src2_mods, ?:{ *:[f32] }:$src2, 0:{ *:[i1] }, 0:{ *:[i32] })
        GIR_BuildMI, /*InsnID*/0, /*Opcode*/GIMT_Encode2(AMDGPU::V_MED3_F32_e64),
        GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/0, // DstI[vdst]
        GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(1), /*SubOperand*/1, // src0_mods
        GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(1), /*SubOperand*/0, // src0
        GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/1, // src1_mods
        GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/0, // src1
        GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(2), /*SubOperand*/1, // src2_mods
        GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(2), /*SubOperand*/0, // src2
        GIR_AddImm8, /*InsnID*/0, /*Imm*/0,
        GIR_AddImm8, /*InsnID*/0, /*Imm*/0,
        GIR_ConstrainSelectedInstOperands, /*InsnID*/0,
        GIR_EraseFromParent, /*InsnID*/0,
        // GIR_Coverage, 10409,
        GIR_Done,
      // Label 4400: @279847
      GIM_Try, /*On fail goto*//*Label 4401*/ GIMT_Encode4(279987), // Rule ID 6508 //
        GIM_CheckRegBankForClass, /*MI*/0, /*Op*/0, /*RC*/GIMT_Encode2(AMDGPU::VGPR_32RegClassID),
        GIM_RecordInsn, /*DefineMI*/1, /*MI*/0, /*OpIdx*/1, // MIs[1]
        GIM_CheckOpcode, /*MI*/1, GIMT_Encode2(TargetOpcode::G_FMAXNUM_IEEE),
        GIM_CheckType, /*MI*/1, /*Op*/1, /*Type*/GILLT_s32,
        GIM_CheckType, /*MI*/1, /*Op*/2, /*Type*/GILLT_s32,
        GIM_RecordInsn, /*DefineMI*/2, /*MI*/0, /*OpIdx*/2, // MIs[2]
        GIM_CheckOpcode, /*MI*/2, GIMT_Encode2(TargetOpcode::G_FMAXNUM),
        GIM_CheckType, /*MI*/2, /*Op*/1, /*Type*/GILLT_s32,
        GIM_CheckType, /*MI*/2, /*Op*/2, /*Type*/GILLT_s32,
        GIM_RecordInsn, /*DefineMI*/3, /*MI*/2, /*OpIdx*/1, // MIs[3]
        GIM_CheckOpcode, /*MI*/3, GIMT_Encode2(TargetOpcode::G_FMINNUM_IEEE),
        // MIs[3] VOP3Mods:src0:src0_mods
        GIM_CheckIsSameOperand, /*MI*/3, /*OpIdx*/1, /*OtherMI*/1, /*OtherOpIdx*/1,
        // MIs[3] VOP3Mods:src1:src1_mods
        GIM_CheckIsSameOperand, /*MI*/3, /*OpIdx*/2, /*OtherMI*/1, /*OtherOpIdx*/2,
        GIM_CheckCxxInsnPredicate, /*MI*/0, /*FnId*/GIMT_Encode2(GICXXPred_MI_Predicate_fminnum_like_nnan),
        GIM_CheckIsSafeToFold, /*InsnID*/1,
        GIM_CheckIsSafeToFold, /*InsnID*/2,
        GIM_CheckIsSafeToFold, /*InsnID*/3,
        GIM_CheckComplexPattern, /*MI*/1, /*Op*/1, /*Renderer*/GIMT_Encode2(0), GIMT_Encode2(GICP_gi_vop3mods),
        GIM_CheckComplexPattern, /*MI*/1, /*Op*/2, /*Renderer*/GIMT_Encode2(1), GIMT_Encode2(GICP_gi_vop3mods),
        GIM_CheckComplexPattern, /*MI*/2, /*Op*/2, /*Renderer*/GIMT_Encode2(2), GIMT_Encode2(GICP_gi_vop3mods),
        // (fminnum:{ *:[f32] } (fmaxnum_ieee:{ *:[f32] } (VOP3Mods:{ *:[f32] } f32:{ *:[f32] }:$src0, i32:{ *:[i32] }:$src0_mods), (VOP3Mods:{ *:[f32] } f32:{ *:[f32] }:$src1, i32:{ *:[i32] }:$src1_mods)), (fmaxnum:{ *:[f32] } (fminnum_ieee:{ *:[f32] } (VOP3Mods:{ *:[f32] } f32:{ *:[f32] }:$src0, i32:{ *:[i32] }:$src0_mods), (VOP3Mods:{ *:[f32] } f32:{ *:[f32] }:$src1, i32:{ *:[i32] }:$src1_mods)), (VOP3Mods:{ *:[f32] } f32:{ *:[f32] }:$src2, i32:{ *:[i32] }:$src2_mods)))<<P:Predicate_fminnum_like_nnan>>  =>  (V_MED3_F32_e64:{ *:[f32] } ?:{ *:[i32] }:$src0_mods, ?:{ *:[f32] }:$src0, ?:{ *:[i32] }:$src1_mods, ?:{ *:[f32] }:$src1, ?:{ *:[i32] }:$src2_mods, ?:{ *:[f32] }:$src2, 0:{ *:[i1] }, 0:{ *:[i32] })
        GIR_BuildMI, /*InsnID*/0, /*Opcode*/GIMT_Encode2(AMDGPU::V_MED3_F32_e64),
        GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/0, // DstI[vdst]
        GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/1, // src0_mods
        GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/0, // src0
        GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(1), /*SubOperand*/1, // src1_mods
        GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(1), /*SubOperand*/0, // src1
        GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(2), /*SubOperand*/1, // src2_mods
        GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(2), /*SubOperand*/0, // src2
        GIR_AddImm8, /*InsnID*/0, /*Imm*/0,
        GIR_AddImm8, /*InsnID*/0, /*Imm*/0,
        GIR_ConstrainSelectedInstOperands, /*InsnID*/0,
        GIR_EraseFromParent, /*InsnID*/0,
        // GIR_Coverage, 6508,
        GIR_Done,
      // Label 4401: @279987
      GIM_Try, /*On fail goto*//*Label 4402*/ GIMT_Encode4(280127), // Rule ID 10390 //
        GIM_CheckRegBankForClass, /*MI*/0, /*Op*/0, /*RC*/GIMT_Encode2(AMDGPU::VGPR_32RegClassID),
        GIM_RecordInsn, /*DefineMI*/1, /*MI*/0, /*OpIdx*/1, // MIs[1]
        GIM_CheckOpcode, /*MI*/1, GIMT_Encode2(TargetOpcode::G_FMAXNUM_IEEE),
        GIM_CheckType, /*MI*/1, /*Op*/1, /*Type*/GILLT_s32,
        GIM_CheckType, /*MI*/1, /*Op*/2, /*Type*/GILLT_s32,
        GIM_RecordInsn, /*DefineMI*/2, /*MI*/0, /*OpIdx*/2, // MIs[2]
        GIM_CheckOpcode, /*MI*/2, GIMT_Encode2(TargetOpcode::G_FMAXNUM),
        GIM_CheckType, /*MI*/2, /*Op*/1, /*Type*/GILLT_s32,
        GIM_CheckType, /*MI*/2, /*Op*/2, /*Type*/GILLT_s32,
        GIM_RecordInsn, /*DefineMI*/3, /*MI*/2, /*OpIdx*/1, // MIs[3]
        GIM_CheckOpcode, /*MI*/3, GIMT_Encode2(TargetOpcode::G_FMINNUM_IEEE),
        // MIs[3] VOP3Mods:src1:src1_mods
        GIM_CheckIsSameOperand, /*MI*/3, /*OpIdx*/1, /*OtherMI*/1, /*OtherOpIdx*/2,
        // MIs[3] VOP3Mods:src0:src0_mods
        GIM_CheckIsSameOperand, /*MI*/3, /*OpIdx*/2, /*OtherMI*/1, /*OtherOpIdx*/1,
        GIM_CheckCxxInsnPredicate, /*MI*/0, /*FnId*/GIMT_Encode2(GICXXPred_MI_Predicate_fminnum_like_nnan),
        GIM_CheckIsSafeToFold, /*InsnID*/1,
        GIM_CheckIsSafeToFold, /*InsnID*/2,
        GIM_CheckIsSafeToFold, /*InsnID*/3,
        GIM_CheckComplexPattern, /*MI*/1, /*Op*/1, /*Renderer*/GIMT_Encode2(0), GIMT_Encode2(GICP_gi_vop3mods),
        GIM_CheckComplexPattern, /*MI*/1, /*Op*/2, /*Renderer*/GIMT_Encode2(1), GIMT_Encode2(GICP_gi_vop3mods),
        GIM_CheckComplexPattern, /*MI*/2, /*Op*/2, /*Renderer*/GIMT_Encode2(2), GIMT_Encode2(GICP_gi_vop3mods),
        // (fminnum:{ *:[f32] } (fmaxnum_ieee:{ *:[f32] } (VOP3Mods:{ *:[f32] } f32:{ *:[f32] }:$src0, i32:{ *:[i32] }:$src0_mods), (VOP3Mods:{ *:[f32] } f32:{ *:[f32] }:$src1, i32:{ *:[i32] }:$src1_mods)), (fmaxnum:{ *:[f32] } (fminnum_ieee:{ *:[f32] } (VOP3Mods:{ *:[f32] } f32:{ *:[f32] }:$src1, i32:{ *:[i32] }:$src1_mods), (VOP3Mods:{ *:[f32] } f32:{ *:[f32] }:$src0, i32:{ *:[i32] }:$src0_mods)), (VOP3Mods:{ *:[f32] } f32:{ *:[f32] }:$src2, i32:{ *:[i32] }:$src2_mods)))<<P:Predicate_fminnum_like_nnan>>  =>  (V_MED3_F32_e64:{ *:[f32] } ?:{ *:[i32] }:$src0_mods, ?:{ *:[f32] }:$src0, ?:{ *:[i32] }:$src1_mods, ?:{ *:[f32] }:$src1, ?:{ *:[i32] }:$src2_mods, ?:{ *:[f32] }:$src2, 0:{ *:[i1] }, 0:{ *:[i32] })
        GIR_BuildMI, /*InsnID*/0, /*Opcode*/GIMT_Encode2(AMDGPU::V_MED3_F32_e64),
        GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/0, // DstI[vdst]
        GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/1, // src0_mods
        GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/0, // src0
        GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(1), /*SubOperand*/1, // src1_mods
        GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(1), /*SubOperand*/0, // src1
        GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(2), /*SubOperand*/1, // src2_mods
        GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(2), /*SubOperand*/0, // src2
        GIR_AddImm8, /*InsnID*/0, /*Imm*/0,
        GIR_AddImm8, /*InsnID*/0, /*Imm*/0,
        GIR_ConstrainSelectedInstOperands, /*InsnID*/0,
        GIR_EraseFromParent, /*InsnID*/0,
        // GIR_Coverage, 10390,
        GIR_Done,
      // Label 4402: @280127
      GIM_Try, /*On fail goto*//*Label 4403*/ GIMT_Encode4(280267), // Rule ID 10393 //
        GIM_CheckRegBankForClass, /*MI*/0, /*Op*/0, /*RC*/GIMT_Encode2(AMDGPU::VGPR_32RegClassID),
        GIM_RecordInsn, /*DefineMI*/1, /*MI*/0, /*OpIdx*/1, // MIs[1]
        GIM_CheckOpcode, /*MI*/1, GIMT_Encode2(TargetOpcode::G_FMAXNUM_IEEE),
        GIM_CheckType, /*MI*/1, /*Op*/1, /*Type*/GILLT_s32,
        GIM_CheckType, /*MI*/1, /*Op*/2, /*Type*/GILLT_s32,
        GIM_RecordInsn, /*DefineMI*/2, /*MI*/0, /*OpIdx*/2, // MIs[2]
        GIM_CheckOpcode, /*MI*/2, GIMT_Encode2(TargetOpcode::G_FMAXNUM),
        GIM_CheckType, /*MI*/2, /*Op*/1, /*Type*/GILLT_s32,
        GIM_CheckType, /*MI*/2, /*Op*/2, /*Type*/GILLT_s32,
        GIM_RecordInsn, /*DefineMI*/3, /*MI*/2, /*OpIdx*/1, // MIs[3]
        GIM_CheckOpcode, /*MI*/3, GIMT_Encode2(TargetOpcode::G_FMINNUM_IEEE),
        // MIs[3] VOP3Mods:src0:src0_mods
        GIM_CheckIsSameOperand, /*MI*/3, /*OpIdx*/1, /*OtherMI*/1, /*OtherOpIdx*/2,
        // MIs[3] VOP3Mods:src1:src1_mods
        GIM_CheckIsSameOperand, /*MI*/3, /*OpIdx*/2, /*OtherMI*/1, /*OtherOpIdx*/1,
        GIM_CheckCxxInsnPredicate, /*MI*/0, /*FnId*/GIMT_Encode2(GICXXPred_MI_Predicate_fminnum_like_nnan),
        GIM_CheckIsSafeToFold, /*InsnID*/1,
        GIM_CheckIsSafeToFold, /*InsnID*/2,
        GIM_CheckIsSafeToFold, /*InsnID*/3,
        GIM_CheckComplexPattern, /*MI*/1, /*Op*/1, /*Renderer*/GIMT_Encode2(0), GIMT_Encode2(GICP_gi_vop3mods),
        GIM_CheckComplexPattern, /*MI*/1, /*Op*/2, /*Renderer*/GIMT_Encode2(1), GIMT_Encode2(GICP_gi_vop3mods),
        GIM_CheckComplexPattern, /*MI*/2, /*Op*/2, /*Renderer*/GIMT_Encode2(2), GIMT_Encode2(GICP_gi_vop3mods),
        // (fminnum:{ *:[f32] } (fmaxnum_ieee:{ *:[f32] } (VOP3Mods:{ *:[f32] } f32:{ *:[f32] }:$src1, i32:{ *:[i32] }:$src1_mods), (VOP3Mods:{ *:[f32] } f32:{ *:[f32] }:$src0, i32:{ *:[i32] }:$src0_mods)), (fmaxnum:{ *:[f32] } (fminnum_ieee:{ *:[f32] } (VOP3Mods:{ *:[f32] } f32:{ *:[f32] }:$src0, i32:{ *:[i32] }:$src0_mods), (VOP3Mods:{ *:[f32] } f32:{ *:[f32] }:$src1, i32:{ *:[i32] }:$src1_mods)), (VOP3Mods:{ *:[f32] } f32:{ *:[f32] }:$src2, i32:{ *:[i32] }:$src2_mods)))<<P:Predicate_fminnum_like_nnan>>  =>  (V_MED3_F32_e64:{ *:[f32] } ?:{ *:[i32] }:$src0_mods, ?:{ *:[f32] }:$src0, ?:{ *:[i32] }:$src1_mods, ?:{ *:[f32] }:$src1, ?:{ *:[i32] }:$src2_mods, ?:{ *:[f32] }:$src2, 0:{ *:[i1] }, 0:{ *:[i32] })
        GIR_BuildMI, /*InsnID*/0, /*Opcode*/GIMT_Encode2(AMDGPU::V_MED3_F32_e64),
        GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/0, // DstI[vdst]
        GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(1), /*SubOperand*/1, // src0_mods
        GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(1), /*SubOperand*/0, // src0
        GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/1, // src1_mods
        GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/0, // src1
        GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(2), /*SubOperand*/1, // src2_mods
        GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(2), /*SubOperand*/0, // src2
        GIR_AddImm8, /*InsnID*/0, /*Imm*/0,
        GIR_AddImm8, /*InsnID*/0, /*Imm*/0,
        GIR_ConstrainSelectedInstOperands, /*InsnID*/0,
        GIR_EraseFromParent, /*InsnID*/0,
        // GIR_Coverage, 10393,
        GIR_Done,
      // Label 4403: @280267
      GIM_Try, /*On fail goto*//*Label 4404*/ GIMT_Encode4(280407), // Rule ID 10394 //
        GIM_CheckRegBankForClass, /*MI*/0, /*Op*/0, /*RC*/GIMT_Encode2(AMDGPU::VGPR_32RegClassID),
        GIM_RecordInsn, /*DefineMI*/1, /*MI*/0, /*OpIdx*/1, // MIs[1]
        GIM_CheckOpcode, /*MI*/1, GIMT_Encode2(TargetOpcode::G_FMAXNUM_IEEE),
        GIM_CheckType, /*MI*/1, /*Op*/1, /*Type*/GILLT_s32,
        GIM_CheckType, /*MI*/1, /*Op*/2, /*Type*/GILLT_s32,
        GIM_RecordInsn, /*DefineMI*/2, /*MI*/0, /*OpIdx*/2, // MIs[2]
        GIM_CheckOpcode, /*MI*/2, GIMT_Encode2(TargetOpcode::G_FMAXNUM),
        GIM_CheckType, /*MI*/2, /*Op*/1, /*Type*/GILLT_s32,
        GIM_CheckType, /*MI*/2, /*Op*/2, /*Type*/GILLT_s32,
        GIM_RecordInsn, /*DefineMI*/3, /*MI*/2, /*OpIdx*/1, // MIs[3]
        GIM_CheckOpcode, /*MI*/3, GIMT_Encode2(TargetOpcode::G_FMINNUM_IEEE),
        // MIs[3] VOP3Mods:src1:src1_mods
        GIM_CheckIsSameOperand, /*MI*/3, /*OpIdx*/1, /*OtherMI*/1, /*OtherOpIdx*/1,
        // MIs[3] VOP3Mods:src0:src0_mods
        GIM_CheckIsSameOperand, /*MI*/3, /*OpIdx*/2, /*OtherMI*/1, /*OtherOpIdx*/2,
        GIM_CheckCxxInsnPredicate, /*MI*/0, /*FnId*/GIMT_Encode2(GICXXPred_MI_Predicate_fminnum_like_nnan),
        GIM_CheckIsSafeToFold, /*InsnID*/1,
        GIM_CheckIsSafeToFold, /*InsnID*/2,
        GIM_CheckIsSafeToFold, /*InsnID*/3,
        GIM_CheckComplexPattern, /*MI*/1, /*Op*/1, /*Renderer*/GIMT_Encode2(0), GIMT_Encode2(GICP_gi_vop3mods),
        GIM_CheckComplexPattern, /*MI*/1, /*Op*/2, /*Renderer*/GIMT_Encode2(1), GIMT_Encode2(GICP_gi_vop3mods),
        GIM_CheckComplexPattern, /*MI*/2, /*Op*/2, /*Renderer*/GIMT_Encode2(2), GIMT_Encode2(GICP_gi_vop3mods),
        // (fminnum:{ *:[f32] } (fmaxnum_ieee:{ *:[f32] } (VOP3Mods:{ *:[f32] } f32:{ *:[f32] }:$src1, i32:{ *:[i32] }:$src1_mods), (VOP3Mods:{ *:[f32] } f32:{ *:[f32] }:$src0, i32:{ *:[i32] }:$src0_mods)), (fmaxnum:{ *:[f32] } (fminnum_ieee:{ *:[f32] } (VOP3Mods:{ *:[f32] } f32:{ *:[f32] }:$src1, i32:{ *:[i32] }:$src1_mods), (VOP3Mods:{ *:[f32] } f32:{ *:[f32] }:$src0, i32:{ *:[i32] }:$src0_mods)), (VOP3Mods:{ *:[f32] } f32:{ *:[f32] }:$src2, i32:{ *:[i32] }:$src2_mods)))<<P:Predicate_fminnum_like_nnan>>  =>  (V_MED3_F32_e64:{ *:[f32] } ?:{ *:[i32] }:$src0_mods, ?:{ *:[f32] }:$src0, ?:{ *:[i32] }:$src1_mods, ?:{ *:[f32] }:$src1, ?:{ *:[i32] }:$src2_mods, ?:{ *:[f32] }:$src2, 0:{ *:[i1] }, 0:{ *:[i32] })
        GIR_BuildMI, /*InsnID*/0, /*Opcode*/GIMT_Encode2(AMDGPU::V_MED3_F32_e64),
        GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/0, // DstI[vdst]
        GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(1), /*SubOperand*/1, // src0_mods
        GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(1), /*SubOperand*/0, // src0
        GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/1, // src1_mods
        GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/0, // src1
        GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(2), /*SubOperand*/1, // src2_mods
        GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(2), /*SubOperand*/0, // src2
        GIR_AddImm8, /*InsnID*/0, /*Imm*/0,
        GIR_AddImm8, /*InsnID*/0, /*Imm*/0,
        GIR_ConstrainSelectedInstOperands, /*InsnID*/0,
        GIR_EraseFromParent, /*InsnID*/0,
        // GIR_Coverage, 10394,
        GIR_Done,
      // Label 4404: @280407
      GIM_Try, /*On fail goto*//*Label 4405*/ GIMT_Encode4(280547), // Rule ID 10376 //
        GIM_CheckRegBankForClass, /*MI*/0, /*Op*/0, /*RC*/GIMT_Encode2(AMDGPU::VGPR_32RegClassID),
        GIM_RecordInsn, /*DefineMI*/1, /*MI*/0, /*OpIdx*/1, // MIs[1]
        GIM_CheckOpcode, /*MI*/1, GIMT_Encode2(TargetOpcode::G_FMAXNUM_IEEE),
        GIM_CheckType, /*MI*/1, /*Op*/1, /*Type*/GILLT_s32,
        GIM_CheckType, /*MI*/1, /*Op*/2, /*Type*/GILLT_s32,
        GIM_RecordInsn, /*DefineMI*/2, /*MI*/0, /*OpIdx*/2, // MIs[2]
        GIM_CheckOpcode, /*MI*/2, GIMT_Encode2(TargetOpcode::G_FMAXNUM_IEEE),
        GIM_CheckType, /*MI*/2, /*Op*/1, /*Type*/GILLT_s32,
        GIM_CheckType, /*MI*/2, /*Op*/2, /*Type*/GILLT_s32,
        GIM_RecordInsn, /*DefineMI*/3, /*MI*/2, /*OpIdx*/2, // MIs[3]
        GIM_CheckOpcode, /*MI*/3, GIMT_Encode2(TargetOpcode::G_FMINNUM),
        // MIs[3] VOP3Mods:src0:src0_mods
        GIM_CheckIsSameOperand, /*MI*/3, /*OpIdx*/1, /*OtherMI*/1, /*OtherOpIdx*/1,
        // MIs[3] VOP3Mods:src1:src1_mods
        GIM_CheckIsSameOperand, /*MI*/3, /*OpIdx*/2, /*OtherMI*/1, /*OtherOpIdx*/2,
        GIM_CheckCxxInsnPredicate, /*MI*/0, /*FnId*/GIMT_Encode2(GICXXPred_MI_Predicate_fminnum_like_nnan),
        GIM_CheckIsSafeToFold, /*InsnID*/1,
        GIM_CheckIsSafeToFold, /*InsnID*/2,
        GIM_CheckIsSafeToFold, /*InsnID*/3,
        GIM_CheckComplexPattern, /*MI*/1, /*Op*/1, /*Renderer*/GIMT_Encode2(0), GIMT_Encode2(GICP_gi_vop3mods),
        GIM_CheckComplexPattern, /*MI*/1, /*Op*/2, /*Renderer*/GIMT_Encode2(1), GIMT_Encode2(GICP_gi_vop3mods),
        GIM_CheckComplexPattern, /*MI*/2, /*Op*/1, /*Renderer*/GIMT_Encode2(2), GIMT_Encode2(GICP_gi_vop3mods),
        // (fminnum:{ *:[f32] } (fmaxnum_ieee:{ *:[f32] } (VOP3Mods:{ *:[f32] } f32:{ *:[f32] }:$src0, i32:{ *:[i32] }:$src0_mods), (VOP3Mods:{ *:[f32] } f32:{ *:[f32] }:$src1, i32:{ *:[i32] }:$src1_mods)), (fmaxnum_ieee:{ *:[f32] } (VOP3Mods:{ *:[f32] } f32:{ *:[f32] }:$src2, i32:{ *:[i32] }:$src2_mods), (fminnum:{ *:[f32] } (VOP3Mods:{ *:[f32] } f32:{ *:[f32] }:$src0, i32:{ *:[i32] }:$src0_mods), (VOP3Mods:{ *:[f32] } f32:{ *:[f32] }:$src1, i32:{ *:[i32] }:$src1_mods))))<<P:Predicate_fminnum_like_nnan>>  =>  (V_MED3_F32_e64:{ *:[f32] } ?:{ *:[i32] }:$src0_mods, ?:{ *:[f32] }:$src0, ?:{ *:[i32] }:$src1_mods, ?:{ *:[f32] }:$src1, ?:{ *:[i32] }:$src2_mods, ?:{ *:[f32] }:$src2, 0:{ *:[i1] }, 0:{ *:[i32] })
        GIR_BuildMI, /*InsnID*/0, /*Opcode*/GIMT_Encode2(AMDGPU::V_MED3_F32_e64),
        GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/0, // DstI[vdst]
        GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/1, // src0_mods
        GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/0, // src0
        GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(1), /*SubOperand*/1, // src1_mods
        GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(1), /*SubOperand*/0, // src1
        GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(2), /*SubOperand*/1, // src2_mods
        GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(2), /*SubOperand*/0, // src2
        GIR_AddImm8, /*InsnID*/0, /*Imm*/0,
        GIR_AddImm8, /*InsnID*/0, /*Imm*/0,
        GIR_ConstrainSelectedInstOperands, /*InsnID*/0,
        GIR_EraseFromParent, /*InsnID*/0,
        // GIR_Coverage, 10376,
        GIR_Done,
      // Label 4405: @280547
      GIM_Try, /*On fail goto*//*Label 4406*/ GIMT_Encode4(280687), // Rule ID 10377 //
        GIM_CheckRegBankForClass, /*MI*/0, /*Op*/0, /*RC*/GIMT_Encode2(AMDGPU::VGPR_32RegClassID),
        GIM_RecordInsn, /*DefineMI*/1, /*MI*/0, /*OpIdx*/1, // MIs[1]
        GIM_CheckOpcode, /*MI*/1, GIMT_Encode2(TargetOpcode::G_FMAXNUM_IEEE),
        GIM_CheckType, /*MI*/1, /*Op*/1, /*Type*/GILLT_s32,
        GIM_CheckType, /*MI*/1, /*Op*/2, /*Type*/GILLT_s32,
        GIM_RecordInsn, /*DefineMI*/2, /*MI*/0, /*OpIdx*/2, // MIs[2]
        GIM_CheckOpcode, /*MI*/2, GIMT_Encode2(TargetOpcode::G_FMAXNUM_IEEE),
        GIM_CheckType, /*MI*/2, /*Op*/1, /*Type*/GILLT_s32,
        GIM_CheckType, /*MI*/2, /*Op*/2, /*Type*/GILLT_s32,
        GIM_RecordInsn, /*DefineMI*/3, /*MI*/2, /*OpIdx*/2, // MIs[3]
        GIM_CheckOpcode, /*MI*/3, GIMT_Encode2(TargetOpcode::G_FMINNUM),
        // MIs[3] VOP3Mods:src1:src1_mods
        GIM_CheckIsSameOperand, /*MI*/3, /*OpIdx*/1, /*OtherMI*/1, /*OtherOpIdx*/2,
        // MIs[3] VOP3Mods:src0:src0_mods
        GIM_CheckIsSameOperand, /*MI*/3, /*OpIdx*/2, /*OtherMI*/1, /*OtherOpIdx*/1,
        GIM_CheckCxxInsnPredicate, /*MI*/0, /*FnId*/GIMT_Encode2(GICXXPred_MI_Predicate_fminnum_like_nnan),
        GIM_CheckIsSafeToFold, /*InsnID*/1,
        GIM_CheckIsSafeToFold, /*InsnID*/2,
        GIM_CheckIsSafeToFold, /*InsnID*/3,
        GIM_CheckComplexPattern, /*MI*/1, /*Op*/1, /*Renderer*/GIMT_Encode2(0), GIMT_Encode2(GICP_gi_vop3mods),
        GIM_CheckComplexPattern, /*MI*/1, /*Op*/2, /*Renderer*/GIMT_Encode2(1), GIMT_Encode2(GICP_gi_vop3mods),
        GIM_CheckComplexPattern, /*MI*/2, /*Op*/1, /*Renderer*/GIMT_Encode2(2), GIMT_Encode2(GICP_gi_vop3mods),
        // (fminnum:{ *:[f32] } (fmaxnum_ieee:{ *:[f32] } (VOP3Mods:{ *:[f32] } f32:{ *:[f32] }:$src0, i32:{ *:[i32] }:$src0_mods), (VOP3Mods:{ *:[f32] } f32:{ *:[f32] }:$src1, i32:{ *:[i32] }:$src1_mods)), (fmaxnum_ieee:{ *:[f32] } (VOP3Mods:{ *:[f32] } f32:{ *:[f32] }:$src2, i32:{ *:[i32] }:$src2_mods), (fminnum:{ *:[f32] } (VOP3Mods:{ *:[f32] } f32:{ *:[f32] }:$src1, i32:{ *:[i32] }:$src1_mods), (VOP3Mods:{ *:[f32] } f32:{ *:[f32] }:$src0, i32:{ *:[i32] }:$src0_mods))))<<P:Predicate_fminnum_like_nnan>>  =>  (V_MED3_F32_e64:{ *:[f32] } ?:{ *:[i32] }:$src0_mods, ?:{ *:[f32] }:$src0, ?:{ *:[i32] }:$src1_mods, ?:{ *:[f32] }:$src1, ?:{ *:[i32] }:$src2_mods, ?:{ *:[f32] }:$src2, 0:{ *:[i1] }, 0:{ *:[i32] })
        GIR_BuildMI, /*InsnID*/0, /*Opcode*/GIMT_Encode2(AMDGPU::V_MED3_F32_e64),
        GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/0, // DstI[vdst]
        GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/1, // src0_mods
        GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/0, // src0
        GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(1), /*SubOperand*/1, // src1_mods
        GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(1), /*SubOperand*/0, // src1
        GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(2), /*SubOperand*/1, // src2_mods
        GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(2), /*SubOperand*/0, // src2
        GIR_AddImm8, /*InsnID*/0, /*Imm*/0,
        GIR_AddImm8, /*InsnID*/0, /*Imm*/0,
        GIR_ConstrainSelectedInstOperands, /*InsnID*/0,
        GIR_EraseFromParent, /*InsnID*/0,
        // GIR_Coverage, 10377,
        GIR_Done,
      // Label 4406: @280687
      GIM_Try, /*On fail goto*//*Label 4407*/ GIMT_Encode4(280827), // Rule ID 10380 //
        GIM_CheckRegBankForClass, /*MI*/0, /*Op*/0, /*RC*/GIMT_Encode2(AMDGPU::VGPR_32RegClassID),
        GIM_RecordInsn, /*DefineMI*/1, /*MI*/0, /*OpIdx*/1, // MIs[1]
        GIM_CheckOpcode, /*MI*/1, GIMT_Encode2(TargetOpcode::G_FMAXNUM_IEEE),
        GIM_CheckType, /*MI*/1, /*Op*/1, /*Type*/GILLT_s32,
        GIM_CheckType, /*MI*/1, /*Op*/2, /*Type*/GILLT_s32,
        GIM_RecordInsn, /*DefineMI*/2, /*MI*/0, /*OpIdx*/2, // MIs[2]
        GIM_CheckOpcode, /*MI*/2, GIMT_Encode2(TargetOpcode::G_FMAXNUM_IEEE),
        GIM_CheckType, /*MI*/2, /*Op*/1, /*Type*/GILLT_s32,
        GIM_CheckType, /*MI*/2, /*Op*/2, /*Type*/GILLT_s32,
        GIM_RecordInsn, /*DefineMI*/3, /*MI*/2, /*OpIdx*/2, // MIs[3]
        GIM_CheckOpcode, /*MI*/3, GIMT_Encode2(TargetOpcode::G_FMINNUM),
        // MIs[3] VOP3Mods:src0:src0_mods
        GIM_CheckIsSameOperand, /*MI*/3, /*OpIdx*/1, /*OtherMI*/1, /*OtherOpIdx*/2,
        // MIs[3] VOP3Mods:src1:src1_mods
        GIM_CheckIsSameOperand, /*MI*/3, /*OpIdx*/2, /*OtherMI*/1, /*OtherOpIdx*/1,
        GIM_CheckCxxInsnPredicate, /*MI*/0, /*FnId*/GIMT_Encode2(GICXXPred_MI_Predicate_fminnum_like_nnan),
        GIM_CheckIsSafeToFold, /*InsnID*/1,
        GIM_CheckIsSafeToFold, /*InsnID*/2,
        GIM_CheckIsSafeToFold, /*InsnID*/3,
        GIM_CheckComplexPattern, /*MI*/1, /*Op*/1, /*Renderer*/GIMT_Encode2(0), GIMT_Encode2(GICP_gi_vop3mods),
        GIM_CheckComplexPattern, /*MI*/1, /*Op*/2, /*Renderer*/GIMT_Encode2(1), GIMT_Encode2(GICP_gi_vop3mods),
        GIM_CheckComplexPattern, /*MI*/2, /*Op*/1, /*Renderer*/GIMT_Encode2(2), GIMT_Encode2(GICP_gi_vop3mods),
        // (fminnum:{ *:[f32] } (fmaxnum_ieee:{ *:[f32] } (VOP3Mods:{ *:[f32] } f32:{ *:[f32] }:$src1, i32:{ *:[i32] }:$src1_mods), (VOP3Mods:{ *:[f32] } f32:{ *:[f32] }:$src0, i32:{ *:[i32] }:$src0_mods)), (fmaxnum_ieee:{ *:[f32] } (VOP3Mods:{ *:[f32] } f32:{ *:[f32] }:$src2, i32:{ *:[i32] }:$src2_mods), (fminnum:{ *:[f32] } (VOP3Mods:{ *:[f32] } f32:{ *:[f32] }:$src0, i32:{ *:[i32] }:$src0_mods), (VOP3Mods:{ *:[f32] } f32:{ *:[f32] }:$src1, i32:{ *:[i32] }:$src1_mods))))<<P:Predicate_fminnum_like_nnan>>  =>  (V_MED3_F32_e64:{ *:[f32] } ?:{ *:[i32] }:$src0_mods, ?:{ *:[f32] }:$src0, ?:{ *:[i32] }:$src1_mods, ?:{ *:[f32] }:$src1, ?:{ *:[i32] }:$src2_mods, ?:{ *:[f32] }:$src2, 0:{ *:[i1] }, 0:{ *:[i32] })
        GIR_BuildMI, /*InsnID*/0, /*Opcode*/GIMT_Encode2(AMDGPU::V_MED3_F32_e64),
        GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/0, // DstI[vdst]
        GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(1), /*SubOperand*/1, // src0_mods
        GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(1), /*SubOperand*/0, // src0
        GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/1, // src1_mods
        GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/0, // src1
        GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(2), /*SubOperand*/1, // src2_mods
        GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(2), /*SubOperand*/0, // src2
        GIR_AddImm8, /*InsnID*/0, /*Imm*/0,
        GIR_AddImm8, /*InsnID*/0, /*Imm*/0,
        GIR_ConstrainSelectedInstOperands, /*InsnID*/0,
        GIR_EraseFromParent, /*InsnID*/0,
        // GIR_Coverage, 10380,
        GIR_Done,
      // Label 4407: @280827
      GIM_Try, /*On fail goto*//*Label 4408*/ GIMT_Encode4(280967), // Rule ID 10381 //
        GIM_CheckRegBankForClass, /*MI*/0, /*Op*/0, /*RC*/GIMT_Encode2(AMDGPU::VGPR_32RegClassID),
        GIM_RecordInsn, /*DefineMI*/1, /*MI*/0, /*OpIdx*/1, // MIs[1]
        GIM_CheckOpcode, /*MI*/1, GIMT_Encode2(TargetOpcode::G_FMAXNUM_IEEE),
        GIM_CheckType, /*MI*/1, /*Op*/1, /*Type*/GILLT_s32,
        GIM_CheckType, /*MI*/1, /*Op*/2, /*Type*/GILLT_s32,
        GIM_RecordInsn, /*DefineMI*/2, /*MI*/0, /*OpIdx*/2, // MIs[2]
        GIM_CheckOpcode, /*MI*/2, GIMT_Encode2(TargetOpcode::G_FMAXNUM_IEEE),
        GIM_CheckType, /*MI*/2, /*Op*/1, /*Type*/GILLT_s32,
        GIM_CheckType, /*MI*/2, /*Op*/2, /*Type*/GILLT_s32,
        GIM_RecordInsn, /*DefineMI*/3, /*MI*/2, /*OpIdx*/2, // MIs[3]
        GIM_CheckOpcode, /*MI*/3, GIMT_Encode2(TargetOpcode::G_FMINNUM),
        // MIs[3] VOP3Mods:src1:src1_mods
        GIM_CheckIsSameOperand, /*MI*/3, /*OpIdx*/1, /*OtherMI*/1, /*OtherOpIdx*/1,
        // MIs[3] VOP3Mods:src0:src0_mods
        GIM_CheckIsSameOperand, /*MI*/3, /*OpIdx*/2, /*OtherMI*/1, /*OtherOpIdx*/2,
        GIM_CheckCxxInsnPredicate, /*MI*/0, /*FnId*/GIMT_Encode2(GICXXPred_MI_Predicate_fminnum_like_nnan),
        GIM_CheckIsSafeToFold, /*InsnID*/1,
        GIM_CheckIsSafeToFold, /*InsnID*/2,
        GIM_CheckIsSafeToFold, /*InsnID*/3,
        GIM_CheckComplexPattern, /*MI*/1, /*Op*/1, /*Renderer*/GIMT_Encode2(0), GIMT_Encode2(GICP_gi_vop3mods),
        GIM_CheckComplexPattern, /*MI*/1, /*Op*/2, /*Renderer*/GIMT_Encode2(1), GIMT_Encode2(GICP_gi_vop3mods),
        GIM_CheckComplexPattern, /*MI*/2, /*Op*/1, /*Renderer*/GIMT_Encode2(2), GIMT_Encode2(GICP_gi_vop3mods),
        // (fminnum:{ *:[f32] } (fmaxnum_ieee:{ *:[f32] } (VOP3Mods:{ *:[f32] } f32:{ *:[f32] }:$src1, i32:{ *:[i32] }:$src1_mods), (VOP3Mods:{ *:[f32] } f32:{ *:[f32] }:$src0, i32:{ *:[i32] }:$src0_mods)), (fmaxnum_ieee:{ *:[f32] } (VOP3Mods:{ *:[f32] } f32:{ *:[f32] }:$src2, i32:{ *:[i32] }:$src2_mods), (fminnum:{ *:[f32] } (VOP3Mods:{ *:[f32] } f32:{ *:[f32] }:$src1, i32:{ *:[i32] }:$src1_mods), (VOP3Mods:{ *:[f32] } f32:{ *:[f32] }:$src0, i32:{ *:[i32] }:$src0_mods))))<<P:Predicate_fminnum_like_nnan>>  =>  (V_MED3_F32_e64:{ *:[f32] } ?:{ *:[i32] }:$src0_mods, ?:{ *:[f32] }:$src0, ?:{ *:[i32] }:$src1_mods, ?:{ *:[f32] }:$src1, ?:{ *:[i32] }:$src2_mods, ?:{ *:[f32] }:$src2, 0:{ *:[i1] }, 0:{ *:[i32] })
        GIR_BuildMI, /*InsnID*/0, /*Opcode*/GIMT_Encode2(AMDGPU::V_MED3_F32_e64),
        GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/0, // DstI[vdst]
        GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(1), /*SubOperand*/1, // src0_mods
        GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(1), /*SubOperand*/0, // src0
        GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/1, // src1_mods
        GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/0, // src1
        GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(2), /*SubOperand*/1, // src2_mods
        GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(2), /*SubOperand*/0, // src2
        GIR_AddImm8, /*InsnID*/0, /*Imm*/0,
        GIR_AddImm8, /*InsnID*/0, /*Imm*/0,
        GIR_ConstrainSelectedInstOperands, /*InsnID*/0,
        GIR_EraseFromParent, /*InsnID*/0,
        // GIR_Coverage, 10381,
        GIR_Done,
      // Label 4408: @280967
      GIM_Try, /*On fail goto*//*Label 4409*/ GIMT_Encode4(281107), // Rule ID 10361 //
        GIM_CheckRegBankForClass, /*MI*/0, /*Op*/0, /*RC*/GIMT_Encode2(AMDGPU::VGPR_32RegClassID),
        GIM_RecordInsn, /*DefineMI*/1, /*MI*/0, /*OpIdx*/1, // MIs[1]
        GIM_CheckOpcode, /*MI*/1, GIMT_Encode2(TargetOpcode::G_FMAXNUM_IEEE),
        GIM_CheckType, /*MI*/1, /*Op*/1, /*Type*/GILLT_s32,
        GIM_CheckType, /*MI*/1, /*Op*/2, /*Type*/GILLT_s32,
        GIM_RecordInsn, /*DefineMI*/2, /*MI*/0, /*OpIdx*/2, // MIs[2]
        GIM_CheckOpcode, /*MI*/2, GIMT_Encode2(TargetOpcode::G_FMAXNUM_IEEE),
        GIM_CheckType, /*MI*/2, /*Op*/1, /*Type*/GILLT_s32,
        GIM_CheckType, /*MI*/2, /*Op*/2, /*Type*/GILLT_s32,
        GIM_RecordInsn, /*DefineMI*/3, /*MI*/2, /*OpIdx*/2, // MIs[3]
        GIM_CheckOpcode, /*MI*/3, GIMT_Encode2(TargetOpcode::G_FMINNUM_IEEE),
        // MIs[3] VOP3Mods:src0:src0_mods
        GIM_CheckIsSameOperand, /*MI*/3, /*OpIdx*/1, /*OtherMI*/1, /*OtherOpIdx*/1,
        // MIs[3] VOP3Mods:src1:src1_mods
        GIM_CheckIsSameOperand, /*MI*/3, /*OpIdx*/2, /*OtherMI*/1, /*OtherOpIdx*/2,
        GIM_CheckCxxInsnPredicate, /*MI*/0, /*FnId*/GIMT_Encode2(GICXXPred_MI_Predicate_fminnum_like_nnan),
        GIM_CheckIsSafeToFold, /*InsnID*/1,
        GIM_CheckIsSafeToFold, /*InsnID*/2,
        GIM_CheckIsSafeToFold, /*InsnID*/3,
        GIM_CheckComplexPattern, /*MI*/1, /*Op*/1, /*Renderer*/GIMT_Encode2(0), GIMT_Encode2(GICP_gi_vop3mods),
        GIM_CheckComplexPattern, /*MI*/1, /*Op*/2, /*Renderer*/GIMT_Encode2(1), GIMT_Encode2(GICP_gi_vop3mods),
        GIM_CheckComplexPattern, /*MI*/2, /*Op*/1, /*Renderer*/GIMT_Encode2(2), GIMT_Encode2(GICP_gi_vop3mods),
        // (fminnum:{ *:[f32] } (fmaxnum_ieee:{ *:[f32] } (VOP3Mods:{ *:[f32] } f32:{ *:[f32] }:$src0, i32:{ *:[i32] }:$src0_mods), (VOP3Mods:{ *:[f32] } f32:{ *:[f32] }:$src1, i32:{ *:[i32] }:$src1_mods)), (fmaxnum_ieee:{ *:[f32] } (VOP3Mods:{ *:[f32] } f32:{ *:[f32] }:$src2, i32:{ *:[i32] }:$src2_mods), (fminnum_ieee:{ *:[f32] } (VOP3Mods:{ *:[f32] } f32:{ *:[f32] }:$src0, i32:{ *:[i32] }:$src0_mods), (VOP3Mods:{ *:[f32] } f32:{ *:[f32] }:$src1, i32:{ *:[i32] }:$src1_mods))))<<P:Predicate_fminnum_like_nnan>>  =>  (V_MED3_F32_e64:{ *:[f32] } ?:{ *:[i32] }:$src0_mods, ?:{ *:[f32] }:$src0, ?:{ *:[i32] }:$src1_mods, ?:{ *:[f32] }:$src1, ?:{ *:[i32] }:$src2_mods, ?:{ *:[f32] }:$src2, 0:{ *:[i1] }, 0:{ *:[i32] })
        GIR_BuildMI, /*InsnID*/0, /*Opcode*/GIMT_Encode2(AMDGPU::V_MED3_F32_e64),
        GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/0, // DstI[vdst]
        GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/1, // src0_mods
        GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/0, // src0
        GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(1), /*SubOperand*/1, // src1_mods
        GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(1), /*SubOperand*/0, // src1
        GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(2), /*SubOperand*/1, // src2_mods
        GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(2), /*SubOperand*/0, // src2
        GIR_AddImm8, /*InsnID*/0, /*Imm*/0,
        GIR_AddImm8, /*InsnID*/0, /*Imm*/0,
        GIR_ConstrainSelectedInstOperands, /*InsnID*/0,
        GIR_EraseFromParent, /*InsnID*/0,
        // GIR_Coverage, 10361,
        GIR_Done,
      // Label 4409: @281107
      GIM_Try, /*On fail goto*//*Label 4410*/ GIMT_Encode4(281247), // Rule ID 10362 //
        GIM_CheckRegBankForClass, /*MI*/0, /*Op*/0, /*RC*/GIMT_Encode2(AMDGPU::VGPR_32RegClassID),
        GIM_RecordInsn, /*DefineMI*/1, /*MI*/0, /*OpIdx*/1, // MIs[1]
        GIM_CheckOpcode, /*MI*/1, GIMT_Encode2(TargetOpcode::G_FMAXNUM_IEEE),
        GIM_CheckType, /*MI*/1, /*Op*/1, /*Type*/GILLT_s32,
        GIM_CheckType, /*MI*/1, /*Op*/2, /*Type*/GILLT_s32,
        GIM_RecordInsn, /*DefineMI*/2, /*MI*/0, /*OpIdx*/2, // MIs[2]
        GIM_CheckOpcode, /*MI*/2, GIMT_Encode2(TargetOpcode::G_FMAXNUM_IEEE),
        GIM_CheckType, /*MI*/2, /*Op*/1, /*Type*/GILLT_s32,
        GIM_CheckType, /*MI*/2, /*Op*/2, /*Type*/GILLT_s32,
        GIM_RecordInsn, /*DefineMI*/3, /*MI*/2, /*OpIdx*/2, // MIs[3]
        GIM_CheckOpcode, /*MI*/3, GIMT_Encode2(TargetOpcode::G_FMINNUM_IEEE),
        // MIs[3] VOP3Mods:src1:src1_mods
        GIM_CheckIsSameOperand, /*MI*/3, /*OpIdx*/1, /*OtherMI*/1, /*OtherOpIdx*/2,
        // MIs[3] VOP3Mods:src0:src0_mods
        GIM_CheckIsSameOperand, /*MI*/3, /*OpIdx*/2, /*OtherMI*/1, /*OtherOpIdx*/1,
        GIM_CheckCxxInsnPredicate, /*MI*/0, /*FnId*/GIMT_Encode2(GICXXPred_MI_Predicate_fminnum_like_nnan),
        GIM_CheckIsSafeToFold, /*InsnID*/1,
        GIM_CheckIsSafeToFold, /*InsnID*/2,
        GIM_CheckIsSafeToFold, /*InsnID*/3,
        GIM_CheckComplexPattern, /*MI*/1, /*Op*/1, /*Renderer*/GIMT_Encode2(0), GIMT_Encode2(GICP_gi_vop3mods),
        GIM_CheckComplexPattern, /*MI*/1, /*Op*/2, /*Renderer*/GIMT_Encode2(1), GIMT_Encode2(GICP_gi_vop3mods),
        GIM_CheckComplexPattern, /*MI*/2, /*Op*/1, /*Renderer*/GIMT_Encode2(2), GIMT_Encode2(GICP_gi_vop3mods),
        // (fminnum:{ *:[f32] } (fmaxnum_ieee:{ *:[f32] } (VOP3Mods:{ *:[f32] } f32:{ *:[f32] }:$src0, i32:{ *:[i32] }:$src0_mods), (VOP3Mods:{ *:[f32] } f32:{ *:[f32] }:$src1, i32:{ *:[i32] }:$src1_mods)), (fmaxnum_ieee:{ *:[f32] } (VOP3Mods:{ *:[f32] } f32:{ *:[f32] }:$src2, i32:{ *:[i32] }:$src2_mods), (fminnum_ieee:{ *:[f32] } (VOP3Mods:{ *:[f32] } f32:{ *:[f32] }:$src1, i32:{ *:[i32] }:$src1_mods), (VOP3Mods:{ *:[f32] } f32:{ *:[f32] }:$src0, i32:{ *:[i32] }:$src0_mods))))<<P:Predicate_fminnum_like_nnan>>  =>  (V_MED3_F32_e64:{ *:[f32] } ?:{ *:[i32] }:$src0_mods, ?:{ *:[f32] }:$src0, ?:{ *:[i32] }:$src1_mods, ?:{ *:[f32] }:$src1, ?:{ *:[i32] }:$src2_mods, ?:{ *:[f32] }:$src2, 0:{ *:[i1] }, 0:{ *:[i32] })
        GIR_BuildMI, /*InsnID*/0, /*Opcode*/GIMT_Encode2(AMDGPU::V_MED3_F32_e64),
        GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/0, // DstI[vdst]
        GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/1, // src0_mods
        GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/0, // src0
        GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(1), /*SubOperand*/1, // src1_mods
        GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(1), /*SubOperand*/0, // src1
        GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(2), /*SubOperand*/1, // src2_mods
        GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(2), /*SubOperand*/0, // src2
        GIR_AddImm8, /*InsnID*/0, /*Imm*/0,
        GIR_AddImm8, /*InsnID*/0, /*Imm*/0,
        GIR_ConstrainSelectedInstOperands, /*InsnID*/0,
        GIR_EraseFromParent, /*InsnID*/0,
        // GIR_Coverage, 10362,
        GIR_Done,
      // Label 4410: @281247
      GIM_Try, /*On fail goto*//*Label 4411*/ GIMT_Encode4(281387), // Rule ID 10365 //
        GIM_CheckRegBankForClass, /*MI*/0, /*Op*/0, /*RC*/GIMT_Encode2(AMDGPU::VGPR_32RegClassID),
        GIM_RecordInsn, /*DefineMI*/1, /*MI*/0, /*OpIdx*/1, // MIs[1]
        GIM_CheckOpcode, /*MI*/1, GIMT_Encode2(TargetOpcode::G_FMAXNUM_IEEE),
        GIM_CheckType, /*MI*/1, /*Op*/1, /*Type*/GILLT_s32,
        GIM_CheckType, /*MI*/1, /*Op*/2, /*Type*/GILLT_s32,
        GIM_RecordInsn, /*DefineMI*/2, /*MI*/0, /*OpIdx*/2, // MIs[2]
        GIM_CheckOpcode, /*MI*/2, GIMT_Encode2(TargetOpcode::G_FMAXNUM_IEEE),
        GIM_CheckType, /*MI*/2, /*Op*/1, /*Type*/GILLT_s32,
        GIM_CheckType, /*MI*/2, /*Op*/2, /*Type*/GILLT_s32,
        GIM_RecordInsn, /*DefineMI*/3, /*MI*/2, /*OpIdx*/2, // MIs[3]
        GIM_CheckOpcode, /*MI*/3, GIMT_Encode2(TargetOpcode::G_FMINNUM_IEEE),
        // MIs[3] VOP3Mods:src0:src0_mods
        GIM_CheckIsSameOperand, /*MI*/3, /*OpIdx*/1, /*OtherMI*/1, /*OtherOpIdx*/2,
        // MIs[3] VOP3Mods:src1:src1_mods
        GIM_CheckIsSameOperand, /*MI*/3, /*OpIdx*/2, /*OtherMI*/1, /*OtherOpIdx*/1,
        GIM_CheckCxxInsnPredicate, /*MI*/0, /*FnId*/GIMT_Encode2(GICXXPred_MI_Predicate_fminnum_like_nnan),
        GIM_CheckIsSafeToFold, /*InsnID*/1,
        GIM_CheckIsSafeToFold, /*InsnID*/2,
        GIM_CheckIsSafeToFold, /*InsnID*/3,
        GIM_CheckComplexPattern, /*MI*/1, /*Op*/1, /*Renderer*/GIMT_Encode2(0), GIMT_Encode2(GICP_gi_vop3mods),
        GIM_CheckComplexPattern, /*MI*/1, /*Op*/2, /*Renderer*/GIMT_Encode2(1), GIMT_Encode2(GICP_gi_vop3mods),
        GIM_CheckComplexPattern, /*MI*/2, /*Op*/1, /*Renderer*/GIMT_Encode2(2), GIMT_Encode2(GICP_gi_vop3mods),
        // (fminnum:{ *:[f32] } (fmaxnum_ieee:{ *:[f32] } (VOP3Mods:{ *:[f32] } f32:{ *:[f32] }:$src1, i32:{ *:[i32] }:$src1_mods), (VOP3Mods:{ *:[f32] } f32:{ *:[f32] }:$src0, i32:{ *:[i32] }:$src0_mods)), (fmaxnum_ieee:{ *:[f32] } (VOP3Mods:{ *:[f32] } f32:{ *:[f32] }:$src2, i32:{ *:[i32] }:$src2_mods), (fminnum_ieee:{ *:[f32] } (VOP3Mods:{ *:[f32] } f32:{ *:[f32] }:$src0, i32:{ *:[i32] }:$src0_mods), (VOP3Mods:{ *:[f32] } f32:{ *:[f32] }:$src1, i32:{ *:[i32] }:$src1_mods))))<<P:Predicate_fminnum_like_nnan>>  =>  (V_MED3_F32_e64:{ *:[f32] } ?:{ *:[i32] }:$src0_mods, ?:{ *:[f32] }:$src0, ?:{ *:[i32] }:$src1_mods, ?:{ *:[f32] }:$src1, ?:{ *:[i32] }:$src2_mods, ?:{ *:[f32] }:$src2, 0:{ *:[i1] }, 0:{ *:[i32] })
        GIR_BuildMI, /*InsnID*/0, /*Opcode*/GIMT_Encode2(AMDGPU::V_MED3_F32_e64),
        GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/0, // DstI[vdst]
        GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(1), /*SubOperand*/1, // src0_mods
        GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(1), /*SubOperand*/0, // src0
        GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/1, // src1_mods
        GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/0, // src1
        GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(2), /*SubOperand*/1, // src2_mods
        GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(2), /*SubOperand*/0, // src2
        GIR_AddImm8, /*InsnID*/0, /*Imm*/0,
        GIR_AddImm8, /*InsnID*/0, /*Imm*/0,
        GIR_ConstrainSelectedInstOperands, /*InsnID*/0,
        GIR_EraseFromParent, /*InsnID*/0,
        // GIR_Coverage, 10365,
        GIR_Done,
      // Label 4411: @281387
      GIM_Try, /*On fail goto*//*Label 4412*/ GIMT_Encode4(281527), // Rule ID 10366 //
        GIM_CheckRegBankForClass, /*MI*/0, /*Op*/0, /*RC*/GIMT_Encode2(AMDGPU::VGPR_32RegClassID),
        GIM_RecordInsn, /*DefineMI*/1, /*MI*/0, /*OpIdx*/1, // MIs[1]
        GIM_CheckOpcode, /*MI*/1, GIMT_Encode2(TargetOpcode::G_FMAXNUM_IEEE),
        GIM_CheckType, /*MI*/1, /*Op*/1, /*Type*/GILLT_s32,
        GIM_CheckType, /*MI*/1, /*Op*/2, /*Type*/GILLT_s32,
        GIM_RecordInsn, /*DefineMI*/2, /*MI*/0, /*OpIdx*/2, // MIs[2]
        GIM_CheckOpcode, /*MI*/2, GIMT_Encode2(TargetOpcode::G_FMAXNUM_IEEE),
        GIM_CheckType, /*MI*/2, /*Op*/1, /*Type*/GILLT_s32,
        GIM_CheckType, /*MI*/2, /*Op*/2, /*Type*/GILLT_s32,
        GIM_RecordInsn, /*DefineMI*/3, /*MI*/2, /*OpIdx*/2, // MIs[3]
        GIM_CheckOpcode, /*MI*/3, GIMT_Encode2(TargetOpcode::G_FMINNUM_IEEE),
        // MIs[3] VOP3Mods:src1:src1_mods
        GIM_CheckIsSameOperand, /*MI*/3, /*OpIdx*/1, /*OtherMI*/1, /*OtherOpIdx*/1,
        // MIs[3] VOP3Mods:src0:src0_mods
        GIM_CheckIsSameOperand, /*MI*/3, /*OpIdx*/2, /*OtherMI*/1, /*OtherOpIdx*/2,
        GIM_CheckCxxInsnPredicate, /*MI*/0, /*FnId*/GIMT_Encode2(GICXXPred_MI_Predicate_fminnum_like_nnan),
        GIM_CheckIsSafeToFold, /*InsnID*/1,
        GIM_CheckIsSafeToFold, /*InsnID*/2,
        GIM_CheckIsSafeToFold, /*InsnID*/3,
        GIM_CheckComplexPattern, /*MI*/1, /*Op*/1, /*Renderer*/GIMT_Encode2(0), GIMT_Encode2(GICP_gi_vop3mods),
        GIM_CheckComplexPattern, /*MI*/1, /*Op*/2, /*Renderer*/GIMT_Encode2(1), GIMT_Encode2(GICP_gi_vop3mods),
        GIM_CheckComplexPattern, /*MI*/2, /*Op*/1, /*Renderer*/GIMT_Encode2(2), GIMT_Encode2(GICP_gi_vop3mods),
        // (fminnum:{ *:[f32] } (fmaxnum_ieee:{ *:[f32] } (VOP3Mods:{ *:[f32] } f32:{ *:[f32] }:$src1, i32:{ *:[i32] }:$src1_mods), (VOP3Mods:{ *:[f32] } f32:{ *:[f32] }:$src0, i32:{ *:[i32] }:$src0_mods)), (fmaxnum_ieee:{ *:[f32] } (VOP3Mods:{ *:[f32] } f32:{ *:[f32] }:$src2, i32:{ *:[i32] }:$src2_mods), (fminnum_ieee:{ *:[f32] } (VOP3Mods:{ *:[f32] } f32:{ *:[f32] }:$src1, i32:{ *:[i32] }:$src1_mods), (VOP3Mods:{ *:[f32] } f32:{ *:[f32] }:$src0, i32:{ *:[i32] }:$src0_mods))))<<P:Predicate_fminnum_like_nnan>>  =>  (V_MED3_F32_e64:{ *:[f32] } ?:{ *:[i32] }:$src0_mods, ?:{ *:[f32] }:$src0, ?:{ *:[i32] }:$src1_mods, ?:{ *:[f32] }:$src1, ?:{ *:[i32] }:$src2_mods, ?:{ *:[f32] }:$src2, 0:{ *:[i1] }, 0:{ *:[i32] })
        GIR_BuildMI, /*InsnID*/0, /*Opcode*/GIMT_Encode2(AMDGPU::V_MED3_F32_e64),
        GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/0, // DstI[vdst]
        GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(1), /*SubOperand*/1, // src0_mods
        GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(1), /*SubOperand*/0, // src0
        GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/1, // src1_mods
        GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/0, // src1
        GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(2), /*SubOperand*/1, // src2_mods
        GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(2), /*SubOperand*/0, // src2
        GIR_AddImm8, /*InsnID*/0, /*Imm*/0,
        GIR_AddImm8, /*InsnID*/0, /*Imm*/0,
        GIR_ConstrainSelectedInstOperands, /*InsnID*/0,
        GIR_EraseFromParent, /*InsnID*/0,
        // GIR_Coverage, 10366,
        GIR_Done,
      // Label 4412: @281527
      GIM_Try, /*On fail goto*//*Label 4413*/ GIMT_Encode4(281667), // Rule ID 6507 //
        GIM_CheckRegBankForClass, /*MI*/0, /*Op*/0, /*RC*/GIMT_Encode2(AMDGPU::VGPR_32RegClassID),
        GIM_RecordInsn, /*DefineMI*/1, /*MI*/0, /*OpIdx*/1, // MIs[1]
        GIM_CheckOpcode, /*MI*/1, GIMT_Encode2(TargetOpcode::G_FMAXNUM_IEEE),
        GIM_CheckType, /*MI*/1, /*Op*/1, /*Type*/GILLT_s32,
        GIM_CheckType, /*MI*/1, /*Op*/2, /*Type*/GILLT_s32,
        GIM_RecordInsn, /*DefineMI*/2, /*MI*/0, /*OpIdx*/2, // MIs[2]
        GIM_CheckOpcode, /*MI*/2, GIMT_Encode2(TargetOpcode::G_FMAXNUM_IEEE),
        GIM_CheckType, /*MI*/2, /*Op*/1, /*Type*/GILLT_s32,
        GIM_CheckType, /*MI*/2, /*Op*/2, /*Type*/GILLT_s32,
        GIM_RecordInsn, /*DefineMI*/3, /*MI*/2, /*OpIdx*/1, // MIs[3]
        GIM_CheckOpcode, /*MI*/3, GIMT_Encode2(TargetOpcode::G_FMINNUM),
        // MIs[3] VOP3Mods:src0:src0_mods
        GIM_CheckIsSameOperand, /*MI*/3, /*OpIdx*/1, /*OtherMI*/1, /*OtherOpIdx*/1,
        // MIs[3] VOP3Mods:src1:src1_mods
        GIM_CheckIsSameOperand, /*MI*/3, /*OpIdx*/2, /*OtherMI*/1, /*OtherOpIdx*/2,
        GIM_CheckCxxInsnPredicate, /*MI*/0, /*FnId*/GIMT_Encode2(GICXXPred_MI_Predicate_fminnum_like_nnan),
        GIM_CheckIsSafeToFold, /*InsnID*/1,
        GIM_CheckIsSafeToFold, /*InsnID*/2,
        GIM_CheckIsSafeToFold, /*InsnID*/3,
        GIM_CheckComplexPattern, /*MI*/1, /*Op*/1, /*Renderer*/GIMT_Encode2(0), GIMT_Encode2(GICP_gi_vop3mods),
        GIM_CheckComplexPattern, /*MI*/1, /*Op*/2, /*Renderer*/GIMT_Encode2(1), GIMT_Encode2(GICP_gi_vop3mods),
        GIM_CheckComplexPattern, /*MI*/2, /*Op*/2, /*Renderer*/GIMT_Encode2(2), GIMT_Encode2(GICP_gi_vop3mods),
        // (fminnum:{ *:[f32] } (fmaxnum_ieee:{ *:[f32] } (VOP3Mods:{ *:[f32] } f32:{ *:[f32] }:$src0, i32:{ *:[i32] }:$src0_mods), (VOP3Mods:{ *:[f32] } f32:{ *:[f32] }:$src1, i32:{ *:[i32] }:$src1_mods)), (fmaxnum_ieee:{ *:[f32] } (fminnum:{ *:[f32] } (VOP3Mods:{ *:[f32] } f32:{ *:[f32] }:$src0, i32:{ *:[i32] }:$src0_mods), (VOP3Mods:{ *:[f32] } f32:{ *:[f32] }:$src1, i32:{ *:[i32] }:$src1_mods)), (VOP3Mods:{ *:[f32] } f32:{ *:[f32] }:$src2, i32:{ *:[i32] }:$src2_mods)))<<P:Predicate_fminnum_like_nnan>>  =>  (V_MED3_F32_e64:{ *:[f32] } ?:{ *:[i32] }:$src0_mods, ?:{ *:[f32] }:$src0, ?:{ *:[i32] }:$src1_mods, ?:{ *:[f32] }:$src1, ?:{ *:[i32] }:$src2_mods, ?:{ *:[f32] }:$src2, 0:{ *:[i1] }, 0:{ *:[i32] })
        GIR_BuildMI, /*InsnID*/0, /*Opcode*/GIMT_Encode2(AMDGPU::V_MED3_F32_e64),
        GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/0, // DstI[vdst]
        GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/1, // src0_mods
        GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/0, // src0
        GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(1), /*SubOperand*/1, // src1_mods
        GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(1), /*SubOperand*/0, // src1
        GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(2), /*SubOperand*/1, // src2_mods
        GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(2), /*SubOperand*/0, // src2
        GIR_AddImm8, /*InsnID*/0, /*Imm*/0,
        GIR_AddImm8, /*InsnID*/0, /*Imm*/0,
        GIR_ConstrainSelectedInstOperands, /*InsnID*/0,
        GIR_EraseFromParent, /*InsnID*/0,
        // GIR_Coverage, 6507,
        GIR_Done,
      // Label 4413: @281667
      GIM_Try, /*On fail goto*//*Label 4414*/ GIMT_Encode4(281807), // Rule ID 10375 //
        GIM_CheckRegBankForClass, /*MI*/0, /*Op*/0, /*RC*/GIMT_Encode2(AMDGPU::VGPR_32RegClassID),
        GIM_RecordInsn, /*DefineMI*/1, /*MI*/0, /*OpIdx*/1, // MIs[1]
        GIM_CheckOpcode, /*MI*/1, GIMT_Encode2(TargetOpcode::G_FMAXNUM_IEEE),
        GIM_CheckType, /*MI*/1, /*Op*/1, /*Type*/GILLT_s32,
        GIM_CheckType, /*MI*/1, /*Op*/2, /*Type*/GILLT_s32,
        GIM_RecordInsn, /*DefineMI*/2, /*MI*/0, /*OpIdx*/2, // MIs[2]
        GIM_CheckOpcode, /*MI*/2, GIMT_Encode2(TargetOpcode::G_FMAXNUM_IEEE),
        GIM_CheckType, /*MI*/2, /*Op*/1, /*Type*/GILLT_s32,
        GIM_CheckType, /*MI*/2, /*Op*/2, /*Type*/GILLT_s32,
        GIM_RecordInsn, /*DefineMI*/3, /*MI*/2, /*OpIdx*/1, // MIs[3]
        GIM_CheckOpcode, /*MI*/3, GIMT_Encode2(TargetOpcode::G_FMINNUM),
        // MIs[3] VOP3Mods:src1:src1_mods
        GIM_CheckIsSameOperand, /*MI*/3, /*OpIdx*/1, /*OtherMI*/1, /*OtherOpIdx*/2,
        // MIs[3] VOP3Mods:src0:src0_mods
        GIM_CheckIsSameOperand, /*MI*/3, /*OpIdx*/2, /*OtherMI*/1, /*OtherOpIdx*/1,
        GIM_CheckCxxInsnPredicate, /*MI*/0, /*FnId*/GIMT_Encode2(GICXXPred_MI_Predicate_fminnum_like_nnan),
        GIM_CheckIsSafeToFold, /*InsnID*/1,
        GIM_CheckIsSafeToFold, /*InsnID*/2,
        GIM_CheckIsSafeToFold, /*InsnID*/3,
        GIM_CheckComplexPattern, /*MI*/1, /*Op*/1, /*Renderer*/GIMT_Encode2(0), GIMT_Encode2(GICP_gi_vop3mods),
        GIM_CheckComplexPattern, /*MI*/1, /*Op*/2, /*Renderer*/GIMT_Encode2(1), GIMT_Encode2(GICP_gi_vop3mods),
        GIM_CheckComplexPattern, /*MI*/2, /*Op*/2, /*Renderer*/GIMT_Encode2(2), GIMT_Encode2(GICP_gi_vop3mods),
        // (fminnum:{ *:[f32] } (fmaxnum_ieee:{ *:[f32] } (VOP3Mods:{ *:[f32] } f32:{ *:[f32] }:$src0, i32:{ *:[i32] }:$src0_mods), (VOP3Mods:{ *:[f32] } f32:{ *:[f32] }:$src1, i32:{ *:[i32] }:$src1_mods)), (fmaxnum_ieee:{ *:[f32] } (fminnum:{ *:[f32] } (VOP3Mods:{ *:[f32] } f32:{ *:[f32] }:$src1, i32:{ *:[i32] }:$src1_mods), (VOP3Mods:{ *:[f32] } f32:{ *:[f32] }:$src0, i32:{ *:[i32] }:$src0_mods)), (VOP3Mods:{ *:[f32] } f32:{ *:[f32] }:$src2, i32:{ *:[i32] }:$src2_mods)))<<P:Predicate_fminnum_like_nnan>>  =>  (V_MED3_F32_e64:{ *:[f32] } ?:{ *:[i32] }:$src0_mods, ?:{ *:[f32] }:$src0, ?:{ *:[i32] }:$src1_mods, ?:{ *:[f32] }:$src1, ?:{ *:[i32] }:$src2_mods, ?:{ *:[f32] }:$src2, 0:{ *:[i1] }, 0:{ *:[i32] })
        GIR_BuildMI, /*InsnID*/0, /*Opcode*/GIMT_Encode2(AMDGPU::V_MED3_F32_e64),
        GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/0, // DstI[vdst]
        GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/1, // src0_mods
        GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/0, // src0
        GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(1), /*SubOperand*/1, // src1_mods
        GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(1), /*SubOperand*/0, // src1
        GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(2), /*SubOperand*/1, // src2_mods
        GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(2), /*SubOperand*/0, // src2
        GIR_AddImm8, /*InsnID*/0, /*Imm*/0,
        GIR_AddImm8, /*InsnID*/0, /*Imm*/0,
        GIR_ConstrainSelectedInstOperands, /*InsnID*/0,
        GIR_EraseFromParent, /*InsnID*/0,
        // GIR_Coverage, 10375,
        GIR_Done,
      // Label 4414: @281807
      GIM_Try, /*On fail goto*//*Label 4415*/ GIMT_Encode4(281947), // Rule ID 10378 //
        GIM_CheckRegBankForClass, /*MI*/0, /*Op*/0, /*RC*/GIMT_Encode2(AMDGPU::VGPR_32RegClassID),
        GIM_RecordInsn, /*DefineMI*/1, /*MI*/0, /*OpIdx*/1, // MIs[1]
        GIM_CheckOpcode, /*MI*/1, GIMT_Encode2(TargetOpcode::G_FMAXNUM_IEEE),
        GIM_CheckType, /*MI*/1, /*Op*/1, /*Type*/GILLT_s32,
        GIM_CheckType, /*MI*/1, /*Op*/2, /*Type*/GILLT_s32,
        GIM_RecordInsn, /*DefineMI*/2, /*MI*/0, /*OpIdx*/2, // MIs[2]
        GIM_CheckOpcode, /*MI*/2, GIMT_Encode2(TargetOpcode::G_FMAXNUM_IEEE),
        GIM_CheckType, /*MI*/2, /*Op*/1, /*Type*/GILLT_s32,
        GIM_CheckType, /*MI*/2, /*Op*/2, /*Type*/GILLT_s32,
        GIM_RecordInsn, /*DefineMI*/3, /*MI*/2, /*OpIdx*/1, // MIs[3]
        GIM_CheckOpcode, /*MI*/3, GIMT_Encode2(TargetOpcode::G_FMINNUM),
        // MIs[3] VOP3Mods:src0:src0_mods
        GIM_CheckIsSameOperand, /*MI*/3, /*OpIdx*/1, /*OtherMI*/1, /*OtherOpIdx*/2,
        // MIs[3] VOP3Mods:src1:src1_mods
        GIM_CheckIsSameOperand, /*MI*/3, /*OpIdx*/2, /*OtherMI*/1, /*OtherOpIdx*/1,
        GIM_CheckCxxInsnPredicate, /*MI*/0, /*FnId*/GIMT_Encode2(GICXXPred_MI_Predicate_fminnum_like_nnan),
        GIM_CheckIsSafeToFold, /*InsnID*/1,
        GIM_CheckIsSafeToFold, /*InsnID*/2,
        GIM_CheckIsSafeToFold, /*InsnID*/3,
        GIM_CheckComplexPattern, /*MI*/1, /*Op*/1, /*Renderer*/GIMT_Encode2(0), GIMT_Encode2(GICP_gi_vop3mods),
        GIM_CheckComplexPattern, /*MI*/1, /*Op*/2, /*Renderer*/GIMT_Encode2(1), GIMT_Encode2(GICP_gi_vop3mods),
        GIM_CheckComplexPattern, /*MI*/2, /*Op*/2, /*Renderer*/GIMT_Encode2(2), GIMT_Encode2(GICP_gi_vop3mods),
        // (fminnum:{ *:[f32] } (fmaxnum_ieee:{ *:[f32] } (VOP3Mods:{ *:[f32] } f32:{ *:[f32] }:$src1, i32:{ *:[i32] }:$src1_mods), (VOP3Mods:{ *:[f32] } f32:{ *:[f32] }:$src0, i32:{ *:[i32] }:$src0_mods)), (fmaxnum_ieee:{ *:[f32] } (fminnum:{ *:[f32] } (VOP3Mods:{ *:[f32] } f32:{ *:[f32] }:$src0, i32:{ *:[i32] }:$src0_mods), (VOP3Mods:{ *:[f32] } f32:{ *:[f32] }:$src1, i32:{ *:[i32] }:$src1_mods)), (VOP3Mods:{ *:[f32] } f32:{ *:[f32] }:$src2, i32:{ *:[i32] }:$src2_mods)))<<P:Predicate_fminnum_like_nnan>>  =>  (V_MED3_F32_e64:{ *:[f32] } ?:{ *:[i32] }:$src0_mods, ?:{ *:[f32] }:$src0, ?:{ *:[i32] }:$src1_mods, ?:{ *:[f32] }:$src1, ?:{ *:[i32] }:$src2_mods, ?:{ *:[f32] }:$src2, 0:{ *:[i1] }, 0:{ *:[i32] })
        GIR_BuildMI, /*InsnID*/0, /*Opcode*/GIMT_Encode2(AMDGPU::V_MED3_F32_e64),
        GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/0, // DstI[vdst]
        GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(1), /*SubOperand*/1, // src0_mods
        GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(1), /*SubOperand*/0, // src0
        GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/1, // src1_mods
        GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/0, // src1
        GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(2), /*SubOperand*/1, // src2_mods
        GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(2), /*SubOperand*/0, // src2
        GIR_AddImm8, /*InsnID*/0, /*Imm*/0,
        GIR_AddImm8, /*InsnID*/0, /*Imm*/0,
        GIR_ConstrainSelectedInstOperands, /*InsnID*/0,
        GIR_EraseFromParent, /*InsnID*/0,
        // GIR_Coverage, 10378,
        GIR_Done,
      // Label 4415: @281947
      GIM_Try, /*On fail goto*//*Label 4416*/ GIMT_Encode4(282087), // Rule ID 10379 //
        GIM_CheckRegBankForClass, /*MI*/0, /*Op*/0, /*RC*/GIMT_Encode2(AMDGPU::VGPR_32RegClassID),
        GIM_RecordInsn, /*DefineMI*/1, /*MI*/0, /*OpIdx*/1, // MIs[1]
        GIM_CheckOpcode, /*MI*/1, GIMT_Encode2(TargetOpcode::G_FMAXNUM_IEEE),
        GIM_CheckType, /*MI*/1, /*Op*/1, /*Type*/GILLT_s32,
        GIM_CheckType, /*MI*/1, /*Op*/2, /*Type*/GILLT_s32,
        GIM_RecordInsn, /*DefineMI*/2, /*MI*/0, /*OpIdx*/2, // MIs[2]
        GIM_CheckOpcode, /*MI*/2, GIMT_Encode2(TargetOpcode::G_FMAXNUM_IEEE),
        GIM_CheckType, /*MI*/2, /*Op*/1, /*Type*/GILLT_s32,
        GIM_CheckType, /*MI*/2, /*Op*/2, /*Type*/GILLT_s32,
        GIM_RecordInsn, /*DefineMI*/3, /*MI*/2, /*OpIdx*/1, // MIs[3]
        GIM_CheckOpcode, /*MI*/3, GIMT_Encode2(TargetOpcode::G_FMINNUM),
        // MIs[3] VOP3Mods:src1:src1_mods
        GIM_CheckIsSameOperand, /*MI*/3, /*OpIdx*/1, /*OtherMI*/1, /*OtherOpIdx*/1,
        // MIs[3] VOP3Mods:src0:src0_mods
        GIM_CheckIsSameOperand, /*MI*/3, /*OpIdx*/2, /*OtherMI*/1, /*OtherOpIdx*/2,
        GIM_CheckCxxInsnPredicate, /*MI*/0, /*FnId*/GIMT_Encode2(GICXXPred_MI_Predicate_fminnum_like_nnan),
        GIM_CheckIsSafeToFold, /*InsnID*/1,
        GIM_CheckIsSafeToFold, /*InsnID*/2,
        GIM_CheckIsSafeToFold, /*InsnID*/3,
        GIM_CheckComplexPattern, /*MI*/1, /*Op*/1, /*Renderer*/GIMT_Encode2(0), GIMT_Encode2(GICP_gi_vop3mods),
        GIM_CheckComplexPattern, /*MI*/1, /*Op*/2, /*Renderer*/GIMT_Encode2(1), GIMT_Encode2(GICP_gi_vop3mods),
        GIM_CheckComplexPattern, /*MI*/2, /*Op*/2, /*Renderer*/GIMT_Encode2(2), GIMT_Encode2(GICP_gi_vop3mods),
        // (fminnum:{ *:[f32] } (fmaxnum_ieee:{ *:[f32] } (VOP3Mods:{ *:[f32] } f32:{ *:[f32] }:$src1, i32:{ *:[i32] }:$src1_mods), (VOP3Mods:{ *:[f32] } f32:{ *:[f32] }:$src0, i32:{ *:[i32] }:$src0_mods)), (fmaxnum_ieee:{ *:[f32] } (fminnum:{ *:[f32] } (VOP3Mods:{ *:[f32] } f32:{ *:[f32] }:$src1, i32:{ *:[i32] }:$src1_mods), (VOP3Mods:{ *:[f32] } f32:{ *:[f32] }:$src0, i32:{ *:[i32] }:$src0_mods)), (VOP3Mods:{ *:[f32] } f32:{ *:[f32] }:$src2, i32:{ *:[i32] }:$src2_mods)))<<P:Predicate_fminnum_like_nnan>>  =>  (V_MED3_F32_e64:{ *:[f32] } ?:{ *:[i32] }:$src0_mods, ?:{ *:[f32] }:$src0, ?:{ *:[i32] }:$src1_mods, ?:{ *:[f32] }:$src1, ?:{ *:[i32] }:$src2_mods, ?:{ *:[f32] }:$src2, 0:{ *:[i1] }, 0:{ *:[i32] })
        GIR_BuildMI, /*InsnID*/0, /*Opcode*/GIMT_Encode2(AMDGPU::V_MED3_F32_e64),
        GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/0, // DstI[vdst]
        GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(1), /*SubOperand*/1, // src0_mods
        GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(1), /*SubOperand*/0, // src0
        GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/1, // src1_mods
        GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/0, // src1
        GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(2), /*SubOperand*/1, // src2_mods
        GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(2), /*SubOperand*/0, // src2
        GIR_AddImm8, /*InsnID*/0, /*Imm*/0,
        GIR_AddImm8, /*InsnID*/0, /*Imm*/0,
        GIR_ConstrainSelectedInstOperands, /*InsnID*/0,
        GIR_EraseFromParent, /*InsnID*/0,
        // GIR_Coverage, 10379,
        GIR_Done,
      // Label 4416: @282087
      GIM_Try, /*On fail goto*//*Label 4417*/ GIMT_Encode4(282227), // Rule ID 6506 //
        GIM_CheckRegBankForClass, /*MI*/0, /*Op*/0, /*RC*/GIMT_Encode2(AMDGPU::VGPR_32RegClassID),
        GIM_RecordInsn, /*DefineMI*/1, /*MI*/0, /*OpIdx*/1, // MIs[1]
        GIM_CheckOpcode, /*MI*/1, GIMT_Encode2(TargetOpcode::G_FMAXNUM_IEEE),
        GIM_CheckType, /*MI*/1, /*Op*/1, /*Type*/GILLT_s32,
        GIM_CheckType, /*MI*/1, /*Op*/2, /*Type*/GILLT_s32,
        GIM_RecordInsn, /*DefineMI*/2, /*MI*/0, /*OpIdx*/2, // MIs[2]
        GIM_CheckOpcode, /*MI*/2, GIMT_Encode2(TargetOpcode::G_FMAXNUM_IEEE),
        GIM_CheckType, /*MI*/2, /*Op*/1, /*Type*/GILLT_s32,
        GIM_CheckType, /*MI*/2, /*Op*/2, /*Type*/GILLT_s32,
        GIM_RecordInsn, /*DefineMI*/3, /*MI*/2, /*OpIdx*/1, // MIs[3]
        GIM_CheckOpcode, /*MI*/3, GIMT_Encode2(TargetOpcode::G_FMINNUM_IEEE),
        // MIs[3] VOP3Mods:src0:src0_mods
        GIM_CheckIsSameOperand, /*MI*/3, /*OpIdx*/1, /*OtherMI*/1, /*OtherOpIdx*/1,
        // MIs[3] VOP3Mods:src1:src1_mods
        GIM_CheckIsSameOperand, /*MI*/3, /*OpIdx*/2, /*OtherMI*/1, /*OtherOpIdx*/2,
        GIM_CheckCxxInsnPredicate, /*MI*/0, /*FnId*/GIMT_Encode2(GICXXPred_MI_Predicate_fminnum_like_nnan),
        GIM_CheckIsSafeToFold, /*InsnID*/1,
        GIM_CheckIsSafeToFold, /*InsnID*/2,
        GIM_CheckIsSafeToFold, /*InsnID*/3,
        GIM_CheckComplexPattern, /*MI*/1, /*Op*/1, /*Renderer*/GIMT_Encode2(0), GIMT_Encode2(GICP_gi_vop3mods),
        GIM_CheckComplexPattern, /*MI*/1, /*Op*/2, /*Renderer*/GIMT_Encode2(1), GIMT_Encode2(GICP_gi_vop3mods),
        GIM_CheckComplexPattern, /*MI*/2, /*Op*/2, /*Renderer*/GIMT_Encode2(2), GIMT_Encode2(GICP_gi_vop3mods),
        // (fminnum:{ *:[f32] } (fmaxnum_ieee:{ *:[f32] } (VOP3Mods:{ *:[f32] } f32:{ *:[f32] }:$src0, i32:{ *:[i32] }:$src0_mods), (VOP3Mods:{ *:[f32] } f32:{ *:[f32] }:$src1, i32:{ *:[i32] }:$src1_mods)), (fmaxnum_ieee:{ *:[f32] } (fminnum_ieee:{ *:[f32] } (VOP3Mods:{ *:[f32] } f32:{ *:[f32] }:$src0, i32:{ *:[i32] }:$src0_mods), (VOP3Mods:{ *:[f32] } f32:{ *:[f32] }:$src1, i32:{ *:[i32] }:$src1_mods)), (VOP3Mods:{ *:[f32] } f32:{ *:[f32] }:$src2, i32:{ *:[i32] }:$src2_mods)))<<P:Predicate_fminnum_like_nnan>>  =>  (V_MED3_F32_e64:{ *:[f32] } ?:{ *:[i32] }:$src0_mods, ?:{ *:[f32] }:$src0, ?:{ *:[i32] }:$src1_mods, ?:{ *:[f32] }:$src1, ?:{ *:[i32] }:$src2_mods, ?:{ *:[f32] }:$src2, 0:{ *:[i1] }, 0:{ *:[i32] })
        GIR_BuildMI, /*InsnID*/0, /*Opcode*/GIMT_Encode2(AMDGPU::V_MED3_F32_e64),
        GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/0, // DstI[vdst]
        GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/1, // src0_mods
        GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/0, // src0
        GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(1), /*SubOperand*/1, // src1_mods
        GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(1), /*SubOperand*/0, // src1
        GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(2), /*SubOperand*/1, // src2_mods
        GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(2), /*SubOperand*/0, // src2
        GIR_AddImm8, /*InsnID*/0, /*Imm*/0,
        GIR_AddImm8, /*InsnID*/0, /*Imm*/0,
        GIR_ConstrainSelectedInstOperands, /*InsnID*/0,
        GIR_EraseFromParent, /*InsnID*/0,
        // GIR_Coverage, 6506,
        GIR_Done,
      // Label 4417: @282227
      GIM_Try, /*On fail goto*//*Label 4418*/ GIMT_Encode4(282367), // Rule ID 10360 //
        GIM_CheckRegBankForClass, /*MI*/0, /*Op*/0, /*RC*/GIMT_Encode2(AMDGPU::VGPR_32RegClassID),
        GIM_RecordInsn, /*DefineMI*/1, /*MI*/0, /*OpIdx*/1, // MIs[1]
        GIM_CheckOpcode, /*MI*/1, GIMT_Encode2(TargetOpcode::G_FMAXNUM_IEEE),
        GIM_CheckType, /*MI*/1, /*Op*/1, /*Type*/GILLT_s32,
        GIM_CheckType, /*MI*/1, /*Op*/2, /*Type*/GILLT_s32,
        GIM_RecordInsn, /*DefineMI*/2, /*MI*/0, /*OpIdx*/2, // MIs[2]
        GIM_CheckOpcode, /*MI*/2, GIMT_Encode2(TargetOpcode::G_FMAXNUM_IEEE),
        GIM_CheckType, /*MI*/2, /*Op*/1, /*Type*/GILLT_s32,
        GIM_CheckType, /*MI*/2, /*Op*/2, /*Type*/GILLT_s32,
        GIM_RecordInsn, /*DefineMI*/3, /*MI*/2, /*OpIdx*/1, // MIs[3]
        GIM_CheckOpcode, /*MI*/3, GIMT_Encode2(TargetOpcode::G_FMINNUM_IEEE),
        // MIs[3] VOP3Mods:src1:src1_mods
        GIM_CheckIsSameOperand, /*MI*/3, /*OpIdx*/1, /*OtherMI*/1, /*OtherOpIdx*/2,
        // MIs[3] VOP3Mods:src0:src0_mods
        GIM_CheckIsSameOperand, /*MI*/3, /*OpIdx*/2, /*OtherMI*/1, /*OtherOpIdx*/1,
        GIM_CheckCxxInsnPredicate, /*MI*/0, /*FnId*/GIMT_Encode2(GICXXPred_MI_Predicate_fminnum_like_nnan),
        GIM_CheckIsSafeToFold, /*InsnID*/1,
        GIM_CheckIsSafeToFold, /*InsnID*/2,
        GIM_CheckIsSafeToFold, /*InsnID*/3,
        GIM_CheckComplexPattern, /*MI*/1, /*Op*/1, /*Renderer*/GIMT_Encode2(0), GIMT_Encode2(GICP_gi_vop3mods),
        GIM_CheckComplexPattern, /*MI*/1, /*Op*/2, /*Renderer*/GIMT_Encode2(1), GIMT_Encode2(GICP_gi_vop3mods),
        GIM_CheckComplexPattern, /*MI*/2, /*Op*/2, /*Renderer*/GIMT_Encode2(2), GIMT_Encode2(GICP_gi_vop3mods),
        // (fminnum:{ *:[f32] } (fmaxnum_ieee:{ *:[f32] } (VOP3Mods:{ *:[f32] } f32:{ *:[f32] }:$src0, i32:{ *:[i32] }:$src0_mods), (VOP3Mods:{ *:[f32] } f32:{ *:[f32] }:$src1, i32:{ *:[i32] }:$src1_mods)), (fmaxnum_ieee:{ *:[f32] } (fminnum_ieee:{ *:[f32] } (VOP3Mods:{ *:[f32] } f32:{ *:[f32] }:$src1, i32:{ *:[i32] }:$src1_mods), (VOP3Mods:{ *:[f32] } f32:{ *:[f32] }:$src0, i32:{ *:[i32] }:$src0_mods)), (VOP3Mods:{ *:[f32] } f32:{ *:[f32] }:$src2, i32:{ *:[i32] }:$src2_mods)))<<P:Predicate_fminnum_like_nnan>>  =>  (V_MED3_F32_e64:{ *:[f32] } ?:{ *:[i32] }:$src0_mods, ?:{ *:[f32] }:$src0, ?:{ *:[i32] }:$src1_mods, ?:{ *:[f32] }:$src1, ?:{ *:[i32] }:$src2_mods, ?:{ *:[f32] }:$src2, 0:{ *:[i1] }, 0:{ *:[i32] })
        GIR_BuildMI, /*InsnID*/0, /*Opcode*/GIMT_Encode2(AMDGPU::V_MED3_F32_e64),
        GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/0, // DstI[vdst]
        GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/1, // src0_mods
        GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/0, // src0
        GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(1), /*SubOperand*/1, // src1_mods
        GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(1), /*SubOperand*/0, // src1
        GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(2), /*SubOperand*/1, // src2_mods
        GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(2), /*SubOperand*/0, // src2
        GIR_AddImm8, /*InsnID*/0, /*Imm*/0,
        GIR_AddImm8, /*InsnID*/0, /*Imm*/0,
        GIR_ConstrainSelectedInstOperands, /*InsnID*/0,
        GIR_EraseFromParent, /*InsnID*/0,
        // GIR_Coverage, 10360,
        GIR_Done,
      // Label 4418: @282367
      GIM_Try, /*On fail goto*//*Label 4419*/ GIMT_Encode4(282507), // Rule ID 10363 //
        GIM_CheckRegBankForClass, /*MI*/0, /*Op*/0, /*RC*/GIMT_Encode2(AMDGPU::VGPR_32RegClassID),
        GIM_RecordInsn, /*DefineMI*/1, /*MI*/0, /*OpIdx*/1, // MIs[1]
        GIM_CheckOpcode, /*MI*/1, GIMT_Encode2(TargetOpcode::G_FMAXNUM_IEEE),
        GIM_CheckType, /*MI*/1, /*Op*/1, /*Type*/GILLT_s32,
        GIM_CheckType, /*MI*/1, /*Op*/2, /*Type*/GILLT_s32,
        GIM_RecordInsn, /*DefineMI*/2, /*MI*/0, /*OpIdx*/2, // MIs[2]
        GIM_CheckOpcode, /*MI*/2, GIMT_Encode2(TargetOpcode::G_FMAXNUM_IEEE),
        GIM_CheckType, /*MI*/2, /*Op*/1, /*Type*/GILLT_s32,
        GIM_CheckType, /*MI*/2, /*Op*/2, /*Type*/GILLT_s32,
        GIM_RecordInsn, /*DefineMI*/3, /*MI*/2, /*OpIdx*/1, // MIs[3]
        GIM_CheckOpcode, /*MI*/3, GIMT_Encode2(TargetOpcode::G_FMINNUM_IEEE),
        // MIs[3] VOP3Mods:src0:src0_mods
        GIM_CheckIsSameOperand, /*MI*/3, /*OpIdx*/1, /*OtherMI*/1, /*OtherOpIdx*/2,
        // MIs[3] VOP3Mods:src1:src1_mods
        GIM_CheckIsSameOperand, /*MI*/3, /*OpIdx*/2, /*OtherMI*/1, /*OtherOpIdx*/1,
        GIM_CheckCxxInsnPredicate, /*MI*/0, /*FnId*/GIMT_Encode2(GICXXPred_MI_Predicate_fminnum_like_nnan),
        GIM_CheckIsSafeToFold, /*InsnID*/1,
        GIM_CheckIsSafeToFold, /*InsnID*/2,
        GIM_CheckIsSafeToFold, /*InsnID*/3,
        GIM_CheckComplexPattern, /*MI*/1, /*Op*/1, /*Renderer*/GIMT_Encode2(0), GIMT_Encode2(GICP_gi_vop3mods),
        GIM_CheckComplexPattern, /*MI*/1, /*Op*/2, /*Renderer*/GIMT_Encode2(1), GIMT_Encode2(GICP_gi_vop3mods),
        GIM_CheckComplexPattern, /*MI*/2, /*Op*/2, /*Renderer*/GIMT_Encode2(2), GIMT_Encode2(GICP_gi_vop3mods),
        // (fminnum:{ *:[f32] } (fmaxnum_ieee:{ *:[f32] } (VOP3Mods:{ *:[f32] } f32:{ *:[f32] }:$src1, i32:{ *:[i32] }:$src1_mods), (VOP3Mods:{ *:[f32] } f32:{ *:[f32] }:$src0, i32:{ *:[i32] }:$src0_mods)), (fmaxnum_ieee:{ *:[f32] } (fminnum_ieee:{ *:[f32] } (VOP3Mods:{ *:[f32] } f32:{ *:[f32] }:$src0, i32:{ *:[i32] }:$src0_mods), (VOP3Mods:{ *:[f32] } f32:{ *:[f32] }:$src1, i32:{ *:[i32] }:$src1_mods)), (VOP3Mods:{ *:[f32] } f32:{ *:[f32] }:$src2, i32:{ *:[i32] }:$src2_mods)))<<P:Predicate_fminnum_like_nnan>>  =>  (V_MED3_F32_e64:{ *:[f32] } ?:{ *:[i32] }:$src0_mods, ?:{ *:[f32] }:$src0, ?:{ *:[i32] }:$src1_mods, ?:{ *:[f32] }:$src1, ?:{ *:[i32] }:$src2_mods, ?:{ *:[f32] }:$src2, 0:{ *:[i1] }, 0:{ *:[i32] })
        GIR_BuildMI, /*InsnID*/0, /*Opcode*/GIMT_Encode2(AMDGPU::V_MED3_F32_e64),
        GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/0, // DstI[vdst]
        GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(1), /*SubOperand*/1, // src0_mods
        GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(1), /*SubOperand*/0, // src0
        GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/1, // src1_mods
        GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/0, // src1
        GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(2), /*SubOperand*/1, // src2_mods
        GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(2), /*SubOperand*/0, // src2
        GIR_AddImm8, /*InsnID*/0, /*Imm*/0,
        GIR_AddImm8, /*InsnID*/0, /*Imm*/0,
        GIR_ConstrainSelectedInstOperands, /*InsnID*/0,
        GIR_EraseFromParent, /*InsnID*/0,
        // GIR_Coverage, 10363,
        GIR_Done,
      // Label 4419: @282507
      GIM_Try, /*On fail goto*//*Label 4420*/ GIMT_Encode4(282647), // Rule ID 10364 //
        GIM_CheckRegBankForClass, /*MI*/0, /*Op*/0, /*RC*/GIMT_Encode2(AMDGPU::VGPR_32RegClassID),
        GIM_RecordInsn, /*DefineMI*/1, /*MI*/0, /*OpIdx*/1, // MIs[1]
        GIM_CheckOpcode, /*MI*/1, GIMT_Encode2(TargetOpcode::G_FMAXNUM_IEEE),
        GIM_CheckType, /*MI*/1, /*Op*/1, /*Type*/GILLT_s32,
        GIM_CheckType, /*MI*/1, /*Op*/2, /*Type*/GILLT_s32,
        GIM_RecordInsn, /*DefineMI*/2, /*MI*/0, /*OpIdx*/2, // MIs[2]
        GIM_CheckOpcode, /*MI*/2, GIMT_Encode2(TargetOpcode::G_FMAXNUM_IEEE),
        GIM_CheckType, /*MI*/2, /*Op*/1, /*Type*/GILLT_s32,
        GIM_CheckType, /*MI*/2, /*Op*/2, /*Type*/GILLT_s32,
        GIM_RecordInsn, /*DefineMI*/3, /*MI*/2, /*OpIdx*/1, // MIs[3]
        GIM_CheckOpcode, /*MI*/3, GIMT_Encode2(TargetOpcode::G_FMINNUM_IEEE),
        // MIs[3] VOP3Mods:src1:src1_mods
        GIM_CheckIsSameOperand, /*MI*/3, /*OpIdx*/1, /*OtherMI*/1, /*OtherOpIdx*/1,
        // MIs[3] VOP3Mods:src0:src0_mods
        GIM_CheckIsSameOperand, /*MI*/3, /*OpIdx*/2, /*OtherMI*/1, /*OtherOpIdx*/2,
        GIM_CheckCxxInsnPredicate, /*MI*/0, /*FnId*/GIMT_Encode2(GICXXPred_MI_Predicate_fminnum_like_nnan),
        GIM_CheckIsSafeToFold, /*InsnID*/1,
        GIM_CheckIsSafeToFold, /*InsnID*/2,
        GIM_CheckIsSafeToFold, /*InsnID*/3,
        GIM_CheckComplexPattern, /*MI*/1, /*Op*/1, /*Renderer*/GIMT_Encode2(0), GIMT_Encode2(GICP_gi_vop3mods),
        GIM_CheckComplexPattern, /*MI*/1, /*Op*/2, /*Renderer*/GIMT_Encode2(1), GIMT_Encode2(GICP_gi_vop3mods),
        GIM_CheckComplexPattern, /*MI*/2, /*Op*/2, /*Renderer*/GIMT_Encode2(2), GIMT_Encode2(GICP_gi_vop3mods),
        // (fminnum:{ *:[f32] } (fmaxnum_ieee:{ *:[f32] } (VOP3Mods:{ *:[f32] } f32:{ *:[f32] }:$src1, i32:{ *:[i32] }:$src1_mods), (VOP3Mods:{ *:[f32] } f32:{ *:[f32] }:$src0, i32:{ *:[i32] }:$src0_mods)), (fmaxnum_ieee:{ *:[f32] } (fminnum_ieee:{ *:[f32] } (VOP3Mods:{ *:[f32] } f32:{ *:[f32] }:$src1, i32:{ *:[i32] }:$src1_mods), (VOP3Mods:{ *:[f32] } f32:{ *:[f32] }:$src0, i32:{ *:[i32] }:$src0_mods)), (VOP3Mods:{ *:[f32] } f32:{ *:[f32] }:$src2, i32:{ *:[i32] }:$src2_mods)))<<P:Predicate_fminnum_like_nnan>>  =>  (V_MED3_F32_e64:{ *:[f32] } ?:{ *:[i32] }:$src0_mods, ?:{ *:[f32] }:$src0, ?:{ *:[i32] }:$src1_mods, ?:{ *:[f32] }:$src1, ?:{ *:[i32] }:$src2_mods, ?:{ *:[f32] }:$src2, 0:{ *:[i1] }, 0:{ *:[i32] })
        GIR_BuildMI, /*InsnID*/0, /*Opcode*/GIMT_Encode2(AMDGPU::V_MED3_F32_e64),
        GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/0, // DstI[vdst]
        GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(1), /*SubOperand*/1, // src0_mods
        GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(1), /*SubOperand*/0, // src0
        GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/1, // src1_mods
        GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/0, // src1
        GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(2), /*SubOperand*/1, // src2_mods
        GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(2), /*SubOperand*/0, // src2
        GIR_AddImm8, /*InsnID*/0, /*Imm*/0,
        GIR_AddImm8, /*InsnID*/0, /*Imm*/0,
        GIR_ConstrainSelectedInstOperands, /*InsnID*/0,
        GIR_EraseFromParent, /*InsnID*/0,
        // GIR_Coverage, 10364,
        GIR_Done,
      // Label 4420: @282647
      GIM_Try, /*On fail goto*//*Label 4421*/ GIMT_Encode4(282787), // Rule ID 10446 //
        GIM_CheckRegBankForClass, /*MI*/0, /*Op*/0, /*RC*/GIMT_Encode2(AMDGPU::VGPR_32RegClassID),
        GIM_RecordInsn, /*DefineMI*/1, /*MI*/0, /*OpIdx*/1, // MIs[1]
        GIM_CheckOpcode, /*MI*/1, GIMT_Encode2(TargetOpcode::G_FMAXNUM_IEEE),
        GIM_CheckType, /*MI*/1, /*Op*/1, /*Type*/GILLT_s32,
        GIM_CheckType, /*MI*/1, /*Op*/2, /*Type*/GILLT_s32,
        GIM_RecordInsn, /*DefineMI*/2, /*MI*/1, /*OpIdx*/2, // MIs[2]
        GIM_CheckOpcode, /*MI*/2, GIMT_Encode2(TargetOpcode::G_FMINNUM),
        GIM_CheckType, /*MI*/2, /*Op*/1, /*Type*/GILLT_s32,
        GIM_CheckType, /*MI*/2, /*Op*/2, /*Type*/GILLT_s32,
        GIM_RecordInsn, /*DefineMI*/3, /*MI*/0, /*OpIdx*/2, // MIs[3]
        GIM_CheckOpcode, /*MI*/3, GIMT_Encode2(TargetOpcode::G_FMAXNUM),
        // MIs[3] VOP3Mods:src0:src0_mods
        GIM_CheckIsSameOperand, /*MI*/3, /*OpIdx*/1, /*OtherMI*/2, /*OtherOpIdx*/1,
        // MIs[3] VOP3Mods:src1:src1_mods
        GIM_CheckIsSameOperand, /*MI*/3, /*OpIdx*/2, /*OtherMI*/2, /*OtherOpIdx*/2,
        GIM_CheckCxxInsnPredicate, /*MI*/0, /*FnId*/GIMT_Encode2(GICXXPred_MI_Predicate_fminnum_like_nnan),
        GIM_CheckIsSafeToFold, /*InsnID*/1,
        GIM_CheckIsSafeToFold, /*InsnID*/2,
        GIM_CheckIsSafeToFold, /*InsnID*/3,
        GIM_CheckComplexPattern, /*MI*/1, /*Op*/1, /*Renderer*/GIMT_Encode2(0), GIMT_Encode2(GICP_gi_vop3mods),
        GIM_CheckComplexPattern, /*MI*/2, /*Op*/1, /*Renderer*/GIMT_Encode2(1), GIMT_Encode2(GICP_gi_vop3mods),
        GIM_CheckComplexPattern, /*MI*/2, /*Op*/2, /*Renderer*/GIMT_Encode2(2), GIMT_Encode2(GICP_gi_vop3mods),
        // (fminnum:{ *:[f32] } (fmaxnum_ieee:{ *:[f32] } (VOP3Mods:{ *:[f32] } f32:{ *:[f32] }:$src2, i32:{ *:[i32] }:$src2_mods), (fminnum:{ *:[f32] } (VOP3Mods:{ *:[f32] } f32:{ *:[f32] }:$src0, i32:{ *:[i32] }:$src0_mods), (VOP3Mods:{ *:[f32] } f32:{ *:[f32] }:$src1, i32:{ *:[i32] }:$src1_mods))), (fmaxnum:{ *:[f32] } (VOP3Mods:{ *:[f32] } f32:{ *:[f32] }:$src0, i32:{ *:[i32] }:$src0_mods), (VOP3Mods:{ *:[f32] } f32:{ *:[f32] }:$src1, i32:{ *:[i32] }:$src1_mods)))<<P:Predicate_fminnum_like_nnan>>  =>  (V_MED3_F32_e64:{ *:[f32] } ?:{ *:[i32] }:$src0_mods, ?:{ *:[f32] }:$src0, ?:{ *:[i32] }:$src1_mods, ?:{ *:[f32] }:$src1, ?:{ *:[i32] }:$src2_mods, ?:{ *:[f32] }:$src2, 0:{ *:[i1] }, 0:{ *:[i32] })
        GIR_BuildMI, /*InsnID*/0, /*Opcode*/GIMT_Encode2(AMDGPU::V_MED3_F32_e64),
        GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/0, // DstI[vdst]
        GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(1), /*SubOperand*/1, // src0_mods
        GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(1), /*SubOperand*/0, // src0
        GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(2), /*SubOperand*/1, // src1_mods
        GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(2), /*SubOperand*/0, // src1
        GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/1, // src2_mods
        GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/0, // src2
        GIR_AddImm8, /*InsnID*/0, /*Imm*/0,
        GIR_AddImm8, /*InsnID*/0, /*Imm*/0,
        GIR_ConstrainSelectedInstOperands, /*InsnID*/0,
        GIR_EraseFromParent, /*InsnID*/0,
        // GIR_Coverage, 10446,
        GIR_Done,
      // Label 4421: @282787
      GIM_Try, /*On fail goto*//*Label 4422*/ GIMT_Encode4(282927), // Rule ID 10447 //
        GIM_CheckRegBankForClass, /*MI*/0, /*Op*/0, /*RC*/GIMT_Encode2(AMDGPU::VGPR_32RegClassID),
        GIM_RecordInsn, /*DefineMI*/1, /*MI*/0, /*OpIdx*/1, // MIs[1]
        GIM_CheckOpcode, /*MI*/1, GIMT_Encode2(TargetOpcode::G_FMAXNUM_IEEE),
        GIM_CheckType, /*MI*/1, /*Op*/1, /*Type*/GILLT_s32,
        GIM_CheckType, /*MI*/1, /*Op*/2, /*Type*/GILLT_s32,
        GIM_RecordInsn, /*DefineMI*/2, /*MI*/1, /*OpIdx*/2, // MIs[2]
        GIM_CheckOpcode, /*MI*/2, GIMT_Encode2(TargetOpcode::G_FMINNUM),
        GIM_CheckType, /*MI*/2, /*Op*/1, /*Type*/GILLT_s32,
        GIM_CheckType, /*MI*/2, /*Op*/2, /*Type*/GILLT_s32,
        GIM_RecordInsn, /*DefineMI*/3, /*MI*/0, /*OpIdx*/2, // MIs[3]
        GIM_CheckOpcode, /*MI*/3, GIMT_Encode2(TargetOpcode::G_FMAXNUM),
        // MIs[3] VOP3Mods:src1:src1_mods
        GIM_CheckIsSameOperand, /*MI*/3, /*OpIdx*/1, /*OtherMI*/2, /*OtherOpIdx*/2,
        // MIs[3] VOP3Mods:src0:src0_mods
        GIM_CheckIsSameOperand, /*MI*/3, /*OpIdx*/2, /*OtherMI*/2, /*OtherOpIdx*/1,
        GIM_CheckCxxInsnPredicate, /*MI*/0, /*FnId*/GIMT_Encode2(GICXXPred_MI_Predicate_fminnum_like_nnan),
        GIM_CheckIsSafeToFold, /*InsnID*/1,
        GIM_CheckIsSafeToFold, /*InsnID*/2,
        GIM_CheckIsSafeToFold, /*InsnID*/3,
        GIM_CheckComplexPattern, /*MI*/1, /*Op*/1, /*Renderer*/GIMT_Encode2(0), GIMT_Encode2(GICP_gi_vop3mods),
        GIM_CheckComplexPattern, /*MI*/2, /*Op*/1, /*Renderer*/GIMT_Encode2(1), GIMT_Encode2(GICP_gi_vop3mods),
        GIM_CheckComplexPattern, /*MI*/2, /*Op*/2, /*Renderer*/GIMT_Encode2(2), GIMT_Encode2(GICP_gi_vop3mods),
        // (fminnum:{ *:[f32] } (fmaxnum_ieee:{ *:[f32] } (VOP3Mods:{ *:[f32] } f32:{ *:[f32] }:$src2, i32:{ *:[i32] }:$src2_mods), (fminnum:{ *:[f32] } (VOP3Mods:{ *:[f32] } f32:{ *:[f32] }:$src0, i32:{ *:[i32] }:$src0_mods), (VOP3Mods:{ *:[f32] } f32:{ *:[f32] }:$src1, i32:{ *:[i32] }:$src1_mods))), (fmaxnum:{ *:[f32] } (VOP3Mods:{ *:[f32] } f32:{ *:[f32] }:$src1, i32:{ *:[i32] }:$src1_mods), (VOP3Mods:{ *:[f32] } f32:{ *:[f32] }:$src0, i32:{ *:[i32] }:$src0_mods)))<<P:Predicate_fminnum_like_nnan>>  =>  (V_MED3_F32_e64:{ *:[f32] } ?:{ *:[i32] }:$src0_mods, ?:{ *:[f32] }:$src0, ?:{ *:[i32] }:$src1_mods, ?:{ *:[f32] }:$src1, ?:{ *:[i32] }:$src2_mods, ?:{ *:[f32] }:$src2, 0:{ *:[i1] }, 0:{ *:[i32] })
        GIR_BuildMI, /*InsnID*/0, /*Opcode*/GIMT_Encode2(AMDGPU::V_MED3_F32_e64),
        GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/0, // DstI[vdst]
        GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(1), /*SubOperand*/1, // src0_mods
        GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(1), /*SubOperand*/0, // src0
        GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(2), /*SubOperand*/1, // src1_mods
        GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(2), /*SubOperand*/0, // src1
        GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/1, // src2_mods
        GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/0, // src2
        GIR_AddImm8, /*InsnID*/0, /*Imm*/0,
        GIR_AddImm8, /*InsnID*/0, /*Imm*/0,
        GIR_ConstrainSelectedInstOperands, /*InsnID*/0,
        GIR_EraseFromParent, /*InsnID*/0,
        // GIR_Coverage, 10447,
        GIR_Done,
      // Label 4422: @282927
      GIM_Try, /*On fail goto*//*Label 4423*/ GIMT_Encode4(283067), // Rule ID 10448 //
        GIM_CheckRegBankForClass, /*MI*/0, /*Op*/0, /*RC*/GIMT_Encode2(AMDGPU::VGPR_32RegClassID),
        GIM_RecordInsn, /*DefineMI*/1, /*MI*/0, /*OpIdx*/1, // MIs[1]
        GIM_CheckOpcode, /*MI*/1, GIMT_Encode2(TargetOpcode::G_FMAXNUM_IEEE),
        GIM_CheckType, /*MI*/1, /*Op*/1, /*Type*/GILLT_s32,
        GIM_CheckType, /*MI*/1, /*Op*/2, /*Type*/GILLT_s32,
        GIM_RecordInsn, /*DefineMI*/2, /*MI*/1, /*OpIdx*/2, // MIs[2]
        GIM_CheckOpcode, /*MI*/2, GIMT_Encode2(TargetOpcode::G_FMINNUM),
        GIM_CheckType, /*MI*/2, /*Op*/1, /*Type*/GILLT_s32,
        GIM_CheckType, /*MI*/2, /*Op*/2, /*Type*/GILLT_s32,
        GIM_RecordInsn, /*DefineMI*/3, /*MI*/0, /*OpIdx*/2, // MIs[3]
        GIM_CheckOpcode, /*MI*/3, GIMT_Encode2(TargetOpcode::G_FMAXNUM),
        // MIs[3] VOP3Mods:src0:src0_mods
        GIM_CheckIsSameOperand, /*MI*/3, /*OpIdx*/1, /*OtherMI*/2, /*OtherOpIdx*/2,
        // MIs[3] VOP3Mods:src1:src1_mods
        GIM_CheckIsSameOperand, /*MI*/3, /*OpIdx*/2, /*OtherMI*/2, /*OtherOpIdx*/1,
        GIM_CheckCxxInsnPredicate, /*MI*/0, /*FnId*/GIMT_Encode2(GICXXPred_MI_Predicate_fminnum_like_nnan),
        GIM_CheckIsSafeToFold, /*InsnID*/1,
        GIM_CheckIsSafeToFold, /*InsnID*/2,
        GIM_CheckIsSafeToFold, /*InsnID*/3,
        GIM_CheckComplexPattern, /*MI*/1, /*Op*/1, /*Renderer*/GIMT_Encode2(0), GIMT_Encode2(GICP_gi_vop3mods),
        GIM_CheckComplexPattern, /*MI*/2, /*Op*/1, /*Renderer*/GIMT_Encode2(1), GIMT_Encode2(GICP_gi_vop3mods),
        GIM_CheckComplexPattern, /*MI*/2, /*Op*/2, /*Renderer*/GIMT_Encode2(2), GIMT_Encode2(GICP_gi_vop3mods),
        // (fminnum:{ *:[f32] } (fmaxnum_ieee:{ *:[f32] } (VOP3Mods:{ *:[f32] } f32:{ *:[f32] }:$src2, i32:{ *:[i32] }:$src2_mods), (fminnum:{ *:[f32] } (VOP3Mods:{ *:[f32] } f32:{ *:[f32] }:$src1, i32:{ *:[i32] }:$src1_mods), (VOP3Mods:{ *:[f32] } f32:{ *:[f32] }:$src0, i32:{ *:[i32] }:$src0_mods))), (fmaxnum:{ *:[f32] } (VOP3Mods:{ *:[f32] } f32:{ *:[f32] }:$src0, i32:{ *:[i32] }:$src0_mods), (VOP3Mods:{ *:[f32] } f32:{ *:[f32] }:$src1, i32:{ *:[i32] }:$src1_mods)))<<P:Predicate_fminnum_like_nnan>>  =>  (V_MED3_F32_e64:{ *:[f32] } ?:{ *:[i32] }:$src0_mods, ?:{ *:[f32] }:$src0, ?:{ *:[i32] }:$src1_mods, ?:{ *:[f32] }:$src1, ?:{ *:[i32] }:$src2_mods, ?:{ *:[f32] }:$src2, 0:{ *:[i1] }, 0:{ *:[i32] })
        GIR_BuildMI, /*InsnID*/0, /*Opcode*/GIMT_Encode2(AMDGPU::V_MED3_F32_e64),
        GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/0, // DstI[vdst]
        GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(2), /*SubOperand*/1, // src0_mods
        GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(2), /*SubOperand*/0, // src0
        GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(1), /*SubOperand*/1, // src1_mods
        GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(1), /*SubOperand*/0, // src1
        GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/1, // src2_mods
        GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/0, // src2
        GIR_AddImm8, /*InsnID*/0, /*Imm*/0,
        GIR_AddImm8, /*InsnID*/0, /*Imm*/0,
        GIR_ConstrainSelectedInstOperands, /*InsnID*/0,
        GIR_EraseFromParent, /*InsnID*/0,
        // GIR_Coverage, 10448,
        GIR_Done,
      // Label 4423: @283067
      GIM_Try, /*On fail goto*//*Label 4424*/ GIMT_Encode4(283207), // Rule ID 10449 //
        GIM_CheckRegBankForClass, /*MI*/0, /*Op*/0, /*RC*/GIMT_Encode2(AMDGPU::VGPR_32RegClassID),
        GIM_RecordInsn, /*DefineMI*/1, /*MI*/0, /*OpIdx*/1, // MIs[1]
        GIM_CheckOpcode, /*MI*/1, GIMT_Encode2(TargetOpcode::G_FMAXNUM_IEEE),
        GIM_CheckType, /*MI*/1, /*Op*/1, /*Type*/GILLT_s32,
        GIM_CheckType, /*MI*/1, /*Op*/2, /*Type*/GILLT_s32,
        GIM_RecordInsn, /*DefineMI*/2, /*MI*/1, /*OpIdx*/2, // MIs[2]
        GIM_CheckOpcode, /*MI*/2, GIMT_Encode2(TargetOpcode::G_FMINNUM),
        GIM_CheckType, /*MI*/2, /*Op*/1, /*Type*/GILLT_s32,
        GIM_CheckType, /*MI*/2, /*Op*/2, /*Type*/GILLT_s32,
        GIM_RecordInsn, /*DefineMI*/3, /*MI*/0, /*OpIdx*/2, // MIs[3]
        GIM_CheckOpcode, /*MI*/3, GIMT_Encode2(TargetOpcode::G_FMAXNUM),
        // MIs[3] VOP3Mods:src1:src1_mods
        GIM_CheckIsSameOperand, /*MI*/3, /*OpIdx*/1, /*OtherMI*/2, /*OtherOpIdx*/1,
        // MIs[3] VOP3Mods:src0:src0_mods
        GIM_CheckIsSameOperand, /*MI*/3, /*OpIdx*/2, /*OtherMI*/2, /*OtherOpIdx*/2,
        GIM_CheckCxxInsnPredicate, /*MI*/0, /*FnId*/GIMT_Encode2(GICXXPred_MI_Predicate_fminnum_like_nnan),
        GIM_CheckIsSafeToFold, /*InsnID*/1,
        GIM_CheckIsSafeToFold, /*InsnID*/2,
        GIM_CheckIsSafeToFold, /*InsnID*/3,
        GIM_CheckComplexPattern, /*MI*/1, /*Op*/1, /*Renderer*/GIMT_Encode2(0), GIMT_Encode2(GICP_gi_vop3mods),
        GIM_CheckComplexPattern, /*MI*/2, /*Op*/1, /*Renderer*/GIMT_Encode2(1), GIMT_Encode2(GICP_gi_vop3mods),
        GIM_CheckComplexPattern, /*MI*/2, /*Op*/2, /*Renderer*/GIMT_Encode2(2), GIMT_Encode2(GICP_gi_vop3mods),
        // (fminnum:{ *:[f32] } (fmaxnum_ieee:{ *:[f32] } (VOP3Mods:{ *:[f32] } f32:{ *:[f32] }:$src2, i32:{ *:[i32] }:$src2_mods), (fminnum:{ *:[f32] } (VOP3Mods:{ *:[f32] } f32:{ *:[f32] }:$src1, i32:{ *:[i32] }:$src1_mods), (VOP3Mods:{ *:[f32] } f32:{ *:[f32] }:$src0, i32:{ *:[i32] }:$src0_mods))), (fmaxnum:{ *:[f32] } (VOP3Mods:{ *:[f32] } f32:{ *:[f32] }:$src1, i32:{ *:[i32] }:$src1_mods), (VOP3Mods:{ *:[f32] } f32:{ *:[f32] }:$src0, i32:{ *:[i32] }:$src0_mods)))<<P:Predicate_fminnum_like_nnan>>  =>  (V_MED3_F32_e64:{ *:[f32] } ?:{ *:[i32] }:$src0_mods, ?:{ *:[f32] }:$src0, ?:{ *:[i32] }:$src1_mods, ?:{ *:[f32] }:$src1, ?:{ *:[i32] }:$src2_mods, ?:{ *:[f32] }:$src2, 0:{ *:[i1] }, 0:{ *:[i32] })
        GIR_BuildMI, /*InsnID*/0, /*Opcode*/GIMT_Encode2(AMDGPU::V_MED3_F32_e64),
        GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/0, // DstI[vdst]
        GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(2), /*SubOperand*/1, // src0_mods
        GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(2), /*SubOperand*/0, // src0
        GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(1), /*SubOperand*/1, // src1_mods
        GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(1), /*SubOperand*/0, // src1
        GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/1, // src2_mods
        GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/0, // src2
        GIR_AddImm8, /*InsnID*/0, /*Imm*/0,
        GIR_AddImm8, /*InsnID*/0, /*Imm*/0,
        GIR_ConstrainSelectedInstOperands, /*InsnID*/0,
        GIR_EraseFromParent, /*InsnID*/0,
        // GIR_Coverage, 10449,
        GIR_Done,
      // Label 4424: @283207
      GIM_Try, /*On fail goto*//*Label 4425*/ GIMT_Encode4(283347), // Rule ID 10386 //
        GIM_CheckRegBankForClass, /*MI*/0, /*Op*/0, /*RC*/GIMT_Encode2(AMDGPU::VGPR_32RegClassID),
        GIM_RecordInsn, /*DefineMI*/1, /*MI*/0, /*OpIdx*/1, // MIs[1]
        GIM_CheckOpcode, /*MI*/1, GIMT_Encode2(TargetOpcode::G_FMAXNUM_IEEE),
        GIM_CheckType, /*MI*/1, /*Op*/1, /*Type*/GILLT_s32,
        GIM_CheckType, /*MI*/1, /*Op*/2, /*Type*/GILLT_s32,
        GIM_RecordInsn, /*DefineMI*/2, /*MI*/1, /*OpIdx*/2, // MIs[2]
        GIM_CheckOpcode, /*MI*/2, GIMT_Encode2(TargetOpcode::G_FMINNUM),
        GIM_CheckType, /*MI*/2, /*Op*/1, /*Type*/GILLT_s32,
        GIM_CheckType, /*MI*/2, /*Op*/2, /*Type*/GILLT_s32,
        GIM_RecordInsn, /*DefineMI*/3, /*MI*/0, /*OpIdx*/2, // MIs[3]
        GIM_CheckOpcode, /*MI*/3, GIMT_Encode2(TargetOpcode::G_FMAXNUM_IEEE),
        // MIs[3] VOP3Mods:src0:src0_mods
        GIM_CheckIsSameOperand, /*MI*/3, /*OpIdx*/1, /*OtherMI*/2, /*OtherOpIdx*/1,
        // MIs[3] VOP3Mods:src1:src1_mods
        GIM_CheckIsSameOperand, /*MI*/3, /*OpIdx*/2, /*OtherMI*/2, /*OtherOpIdx*/2,
        GIM_CheckCxxInsnPredicate, /*MI*/0, /*FnId*/GIMT_Encode2(GICXXPred_MI_Predicate_fminnum_like_nnan),
        GIM_CheckIsSafeToFold, /*InsnID*/1,
        GIM_CheckIsSafeToFold, /*InsnID*/2,
        GIM_CheckIsSafeToFold, /*InsnID*/3,
        GIM_CheckComplexPattern, /*MI*/1, /*Op*/1, /*Renderer*/GIMT_Encode2(0), GIMT_Encode2(GICP_gi_vop3mods),
        GIM_CheckComplexPattern, /*MI*/2, /*Op*/1, /*Renderer*/GIMT_Encode2(1), GIMT_Encode2(GICP_gi_vop3mods),
        GIM_CheckComplexPattern, /*MI*/2, /*Op*/2, /*Renderer*/GIMT_Encode2(2), GIMT_Encode2(GICP_gi_vop3mods),
        // (fminnum:{ *:[f32] } (fmaxnum_ieee:{ *:[f32] } (VOP3Mods:{ *:[f32] } f32:{ *:[f32] }:$src2, i32:{ *:[i32] }:$src2_mods), (fminnum:{ *:[f32] } (VOP3Mods:{ *:[f32] } f32:{ *:[f32] }:$src0, i32:{ *:[i32] }:$src0_mods), (VOP3Mods:{ *:[f32] } f32:{ *:[f32] }:$src1, i32:{ *:[i32] }:$src1_mods))), (fmaxnum_ieee:{ *:[f32] } (VOP3Mods:{ *:[f32] } f32:{ *:[f32] }:$src0, i32:{ *:[i32] }:$src0_mods), (VOP3Mods:{ *:[f32] } f32:{ *:[f32] }:$src1, i32:{ *:[i32] }:$src1_mods)))<<P:Predicate_fminnum_like_nnan>>  =>  (V_MED3_F32_e64:{ *:[f32] } ?:{ *:[i32] }:$src0_mods, ?:{ *:[f32] }:$src0, ?:{ *:[i32] }:$src1_mods, ?:{ *:[f32] }:$src1, ?:{ *:[i32] }:$src2_mods, ?:{ *:[f32] }:$src2, 0:{ *:[i1] }, 0:{ *:[i32] })
        GIR_BuildMI, /*InsnID*/0, /*Opcode*/GIMT_Encode2(AMDGPU::V_MED3_F32_e64),
        GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/0, // DstI[vdst]
        GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(1), /*SubOperand*/1, // src0_mods
        GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(1), /*SubOperand*/0, // src0
        GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(2), /*SubOperand*/1, // src1_mods
        GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(2), /*SubOperand*/0, // src1
        GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/1, // src2_mods
        GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/0, // src2
        GIR_AddImm8, /*InsnID*/0, /*Imm*/0,
        GIR_AddImm8, /*InsnID*/0, /*Imm*/0,
        GIR_ConstrainSelectedInstOperands, /*InsnID*/0,
        GIR_EraseFromParent, /*InsnID*/0,
        // GIR_Coverage, 10386,
        GIR_Done,
      // Label 4425: @283347
      GIM_Try, /*On fail goto*//*Label 4426*/ GIMT_Encode4(283487), // Rule ID 10387 //
        GIM_CheckRegBankForClass, /*MI*/0, /*Op*/0, /*RC*/GIMT_Encode2(AMDGPU::VGPR_32RegClassID),
        GIM_RecordInsn, /*DefineMI*/1, /*MI*/0, /*OpIdx*/1, // MIs[1]
        GIM_CheckOpcode, /*MI*/1, GIMT_Encode2(TargetOpcode::G_FMAXNUM_IEEE),
        GIM_CheckType, /*MI*/1, /*Op*/1, /*Type*/GILLT_s32,
        GIM_CheckType, /*MI*/1, /*Op*/2, /*Type*/GILLT_s32,
        GIM_RecordInsn, /*DefineMI*/2, /*MI*/1, /*OpIdx*/2, // MIs[2]
        GIM_CheckOpcode, /*MI*/2, GIMT_Encode2(TargetOpcode::G_FMINNUM),
        GIM_CheckType, /*MI*/2, /*Op*/1, /*Type*/GILLT_s32,
        GIM_CheckType, /*MI*/2, /*Op*/2, /*Type*/GILLT_s32,
        GIM_RecordInsn, /*DefineMI*/3, /*MI*/0, /*OpIdx*/2, // MIs[3]
        GIM_CheckOpcode, /*MI*/3, GIMT_Encode2(TargetOpcode::G_FMAXNUM_IEEE),
        // MIs[3] VOP3Mods:src1:src1_mods
        GIM_CheckIsSameOperand, /*MI*/3, /*OpIdx*/1, /*OtherMI*/2, /*OtherOpIdx*/2,
        // MIs[3] VOP3Mods:src0:src0_mods
        GIM_CheckIsSameOperand, /*MI*/3, /*OpIdx*/2, /*OtherMI*/2, /*OtherOpIdx*/1,
        GIM_CheckCxxInsnPredicate, /*MI*/0, /*FnId*/GIMT_Encode2(GICXXPred_MI_Predicate_fminnum_like_nnan),
        GIM_CheckIsSafeToFold, /*InsnID*/1,
        GIM_CheckIsSafeToFold, /*InsnID*/2,
        GIM_CheckIsSafeToFold, /*InsnID*/3,
        GIM_CheckComplexPattern, /*MI*/1, /*Op*/1, /*Renderer*/GIMT_Encode2(0), GIMT_Encode2(GICP_gi_vop3mods),
        GIM_CheckComplexPattern, /*MI*/2, /*Op*/1, /*Renderer*/GIMT_Encode2(1), GIMT_Encode2(GICP_gi_vop3mods),
        GIM_CheckComplexPattern, /*MI*/2, /*Op*/2, /*Renderer*/GIMT_Encode2(2), GIMT_Encode2(GICP_gi_vop3mods),
        // (fminnum:{ *:[f32] } (fmaxnum_ieee:{ *:[f32] } (VOP3Mods:{ *:[f32] } f32:{ *:[f32] }:$src2, i32:{ *:[i32] }:$src2_mods), (fminnum:{ *:[f32] } (VOP3Mods:{ *:[f32] } f32:{ *:[f32] }:$src0, i32:{ *:[i32] }:$src0_mods), (VOP3Mods:{ *:[f32] } f32:{ *:[f32] }:$src1, i32:{ *:[i32] }:$src1_mods))), (fmaxnum_ieee:{ *:[f32] } (VOP3Mods:{ *:[f32] } f32:{ *:[f32] }:$src1, i32:{ *:[i32] }:$src1_mods), (VOP3Mods:{ *:[f32] } f32:{ *:[f32] }:$src0, i32:{ *:[i32] }:$src0_mods)))<<P:Predicate_fminnum_like_nnan>>  =>  (V_MED3_F32_e64:{ *:[f32] } ?:{ *:[i32] }:$src0_mods, ?:{ *:[f32] }:$src0, ?:{ *:[i32] }:$src1_mods, ?:{ *:[f32] }:$src1, ?:{ *:[i32] }:$src2_mods, ?:{ *:[f32] }:$src2, 0:{ *:[i1] }, 0:{ *:[i32] })
        GIR_BuildMI, /*InsnID*/0, /*Opcode*/GIMT_Encode2(AMDGPU::V_MED3_F32_e64),
        GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/0, // DstI[vdst]
        GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(1), /*SubOperand*/1, // src0_mods
        GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(1), /*SubOperand*/0, // src0
        GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(2), /*SubOperand*/1, // src1_mods
        GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(2), /*SubOperand*/0, // src1
        GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/1, // src2_mods
        GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/0, // src2
        GIR_AddImm8, /*InsnID*/0, /*Imm*/0,
        GIR_AddImm8, /*InsnID*/0, /*Imm*/0,
        GIR_ConstrainSelectedInstOperands, /*InsnID*/0,
        GIR_EraseFromParent, /*InsnID*/0,
        // GIR_Coverage, 10387,
        GIR_Done,
      // Label 4426: @283487
      GIM_Try, /*On fail goto*//*Label 4427*/ GIMT_Encode4(283627), // Rule ID 10388 //
        GIM_CheckRegBankForClass, /*MI*/0, /*Op*/0, /*RC*/GIMT_Encode2(AMDGPU::VGPR_32RegClassID),
        GIM_RecordInsn, /*DefineMI*/1, /*MI*/0, /*OpIdx*/1, // MIs[1]
        GIM_CheckOpcode, /*MI*/1, GIMT_Encode2(TargetOpcode::G_FMAXNUM_IEEE),
        GIM_CheckType, /*MI*/1, /*Op*/1, /*Type*/GILLT_s32,
        GIM_CheckType, /*MI*/1, /*Op*/2, /*Type*/GILLT_s32,
        GIM_RecordInsn, /*DefineMI*/2, /*MI*/1, /*OpIdx*/2, // MIs[2]
        GIM_CheckOpcode, /*MI*/2, GIMT_Encode2(TargetOpcode::G_FMINNUM),
        GIM_CheckType, /*MI*/2, /*Op*/1, /*Type*/GILLT_s32,
        GIM_CheckType, /*MI*/2, /*Op*/2, /*Type*/GILLT_s32,
        GIM_RecordInsn, /*DefineMI*/3, /*MI*/0, /*OpIdx*/2, // MIs[3]
        GIM_CheckOpcode, /*MI*/3, GIMT_Encode2(TargetOpcode::G_FMAXNUM_IEEE),
        // MIs[3] VOP3Mods:src0:src0_mods
        GIM_CheckIsSameOperand, /*MI*/3, /*OpIdx*/1, /*OtherMI*/2, /*OtherOpIdx*/2,
        // MIs[3] VOP3Mods:src1:src1_mods
        GIM_CheckIsSameOperand, /*MI*/3, /*OpIdx*/2, /*OtherMI*/2, /*OtherOpIdx*/1,
        GIM_CheckCxxInsnPredicate, /*MI*/0, /*FnId*/GIMT_Encode2(GICXXPred_MI_Predicate_fminnum_like_nnan),
        GIM_CheckIsSafeToFold, /*InsnID*/1,
        GIM_CheckIsSafeToFold, /*InsnID*/2,
        GIM_CheckIsSafeToFold, /*InsnID*/3,
        GIM_CheckComplexPattern, /*MI*/1, /*Op*/1, /*Renderer*/GIMT_Encode2(0), GIMT_Encode2(GICP_gi_vop3mods),
        GIM_CheckComplexPattern, /*MI*/2, /*Op*/1, /*Renderer*/GIMT_Encode2(1), GIMT_Encode2(GICP_gi_vop3mods),
        GIM_CheckComplexPattern, /*MI*/2, /*Op*/2, /*Renderer*/GIMT_Encode2(2), GIMT_Encode2(GICP_gi_vop3mods),
        // (fminnum:{ *:[f32] } (fmaxnum_ieee:{ *:[f32] } (VOP3Mods:{ *:[f32] } f32:{ *:[f32] }:$src2, i32:{ *:[i32] }:$src2_mods), (fminnum:{ *:[f32] } (VOP3Mods:{ *:[f32] } f32:{ *:[f32] }:$src1, i32:{ *:[i32] }:$src1_mods), (VOP3Mods:{ *:[f32] } f32:{ *:[f32] }:$src0, i32:{ *:[i32] }:$src0_mods))), (fmaxnum_ieee:{ *:[f32] } (VOP3Mods:{ *:[f32] } f32:{ *:[f32] }:$src0, i32:{ *:[i32] }:$src0_mods), (VOP3Mods:{ *:[f32] } f32:{ *:[f32] }:$src1, i32:{ *:[i32] }:$src1_mods)))<<P:Predicate_fminnum_like_nnan>>  =>  (V_MED3_F32_e64:{ *:[f32] } ?:{ *:[i32] }:$src0_mods, ?:{ *:[f32] }:$src0, ?:{ *:[i32] }:$src1_mods, ?:{ *:[f32] }:$src1, ?:{ *:[i32] }:$src2_mods, ?:{ *:[f32] }:$src2, 0:{ *:[i1] }, 0:{ *:[i32] })
        GIR_BuildMI, /*InsnID*/0, /*Opcode*/GIMT_Encode2(AMDGPU::V_MED3_F32_e64),
        GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/0, // DstI[vdst]
        GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(2), /*SubOperand*/1, // src0_mods
        GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(2), /*SubOperand*/0, // src0
        GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(1), /*SubOperand*/1, // src1_mods
        GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(1), /*SubOperand*/0, // src1
        GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/1, // src2_mods
        GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/0, // src2
        GIR_AddImm8, /*InsnID*/0, /*Imm*/0,
        GIR_AddImm8, /*InsnID*/0, /*Imm*/0,
        GIR_ConstrainSelectedInstOperands, /*InsnID*/0,
        GIR_EraseFromParent, /*InsnID*/0,
        // GIR_Coverage, 10388,
        GIR_Done,
      // Label 4427: @283627
      GIM_Try, /*On fail goto*//*Label 4428*/ GIMT_Encode4(283767), // Rule ID 10389 //
        GIM_CheckRegBankForClass, /*MI*/0, /*Op*/0, /*RC*/GIMT_Encode2(AMDGPU::VGPR_32RegClassID),
        GIM_RecordInsn, /*DefineMI*/1, /*MI*/0, /*OpIdx*/1, // MIs[1]
        GIM_CheckOpcode, /*MI*/1, GIMT_Encode2(TargetOpcode::G_FMAXNUM_IEEE),
        GIM_CheckType, /*MI*/1, /*Op*/1, /*Type*/GILLT_s32,
        GIM_CheckType, /*MI*/1, /*Op*/2, /*Type*/GILLT_s32,
        GIM_RecordInsn, /*DefineMI*/2, /*MI*/1, /*OpIdx*/2, // MIs[2]
        GIM_CheckOpcode, /*MI*/2, GIMT_Encode2(TargetOpcode::G_FMINNUM),
        GIM_CheckType, /*MI*/2, /*Op*/1, /*Type*/GILLT_s32,
        GIM_CheckType, /*MI*/2, /*Op*/2, /*Type*/GILLT_s32,
        GIM_RecordInsn, /*DefineMI*/3, /*MI*/0, /*OpIdx*/2, // MIs[3]
        GIM_CheckOpcode, /*MI*/3, GIMT_Encode2(TargetOpcode::G_FMAXNUM_IEEE),
        // MIs[3] VOP3Mods:src1:src1_mods
        GIM_CheckIsSameOperand, /*MI*/3, /*OpIdx*/1, /*OtherMI*/2, /*OtherOpIdx*/1,
        // MIs[3] VOP3Mods:src0:src0_mods
        GIM_CheckIsSameOperand, /*MI*/3, /*OpIdx*/2, /*OtherMI*/2, /*OtherOpIdx*/2,
        GIM_CheckCxxInsnPredicate, /*MI*/0, /*FnId*/GIMT_Encode2(GICXXPred_MI_Predicate_fminnum_like_nnan),
        GIM_CheckIsSafeToFold, /*InsnID*/1,
        GIM_CheckIsSafeToFold, /*InsnID*/2,
        GIM_CheckIsSafeToFold, /*InsnID*/3,
        GIM_CheckComplexPattern, /*MI*/1, /*Op*/1, /*Renderer*/GIMT_Encode2(0), GIMT_Encode2(GICP_gi_vop3mods),
        GIM_CheckComplexPattern, /*MI*/2, /*Op*/1, /*Renderer*/GIMT_Encode2(1), GIMT_Encode2(GICP_gi_vop3mods),
        GIM_CheckComplexPattern, /*MI*/2, /*Op*/2, /*Renderer*/GIMT_Encode2(2), GIMT_Encode2(GICP_gi_vop3mods),
        // (fminnum:{ *:[f32] } (fmaxnum_ieee:{ *:[f32] } (VOP3Mods:{ *:[f32] } f32:{ *:[f32] }:$src2, i32:{ *:[i32] }:$src2_mods), (fminnum:{ *:[f32] } (VOP3Mods:{ *:[f32] } f32:{ *:[f32] }:$src1, i32:{ *:[i32] }:$src1_mods), (VOP3Mods:{ *:[f32] } f32:{ *:[f32] }:$src0, i32:{ *:[i32] }:$src0_mods))), (fmaxnum_ieee:{ *:[f32] } (VOP3Mods:{ *:[f32] } f32:{ *:[f32] }:$src1, i32:{ *:[i32] }:$src1_mods), (VOP3Mods:{ *:[f32] } f32:{ *:[f32] }:$src0, i32:{ *:[i32] }:$src0_mods)))<<P:Predicate_fminnum_like_nnan>>  =>  (V_MED3_F32_e64:{ *:[f32] } ?:{ *:[i32] }:$src0_mods, ?:{ *:[f32] }:$src0, ?:{ *:[i32] }:$src1_mods, ?:{ *:[f32] }:$src1, ?:{ *:[i32] }:$src2_mods, ?:{ *:[f32] }:$src2, 0:{ *:[i1] }, 0:{ *:[i32] })
        GIR_BuildMI, /*InsnID*/0, /*Opcode*/GIMT_Encode2(AMDGPU::V_MED3_F32_e64),
        GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/0, // DstI[vdst]
        GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(2), /*SubOperand*/1, // src0_mods
        GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(2), /*SubOperand*/0, // src0
        GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(1), /*SubOperand*/1, // src1_mods
        GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(1), /*SubOperand*/0, // src1
        GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/1, // src2_mods
        GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/0, // src2
        GIR_AddImm8, /*InsnID*/0, /*Imm*/0,
        GIR_AddImm8, /*InsnID*/0, /*Imm*/0,
        GIR_ConstrainSelectedInstOperands, /*InsnID*/0,
        GIR_EraseFromParent, /*InsnID*/0,
        // GIR_Coverage, 10389,
        GIR_Done,
      // Label 4428: @283767
      GIM_Try, /*On fail goto*//*Label 4429*/ GIMT_Encode4(283907), // Rule ID 10431 //
        GIM_CheckRegBankForClass, /*MI*/0, /*Op*/0, /*RC*/GIMT_Encode2(AMDGPU::VGPR_32RegClassID),
        GIM_RecordInsn, /*DefineMI*/1, /*MI*/0, /*OpIdx*/1, // MIs[1]
        GIM_CheckOpcode, /*MI*/1, GIMT_Encode2(TargetOpcode::G_FMAXNUM_IEEE),
        GIM_CheckType, /*MI*/1, /*Op*/1, /*Type*/GILLT_s32,
        GIM_CheckType, /*MI*/1, /*Op*/2, /*Type*/GILLT_s32,
        GIM_RecordInsn, /*DefineMI*/2, /*MI*/1, /*OpIdx*/2, // MIs[2]
        GIM_CheckOpcode, /*MI*/2, GIMT_Encode2(TargetOpcode::G_FMINNUM_IEEE),
        GIM_CheckType, /*MI*/2, /*Op*/1, /*Type*/GILLT_s32,
        GIM_CheckType, /*MI*/2, /*Op*/2, /*Type*/GILLT_s32,
        GIM_RecordInsn, /*DefineMI*/3, /*MI*/0, /*OpIdx*/2, // MIs[3]
        GIM_CheckOpcode, /*MI*/3, GIMT_Encode2(TargetOpcode::G_FMAXNUM),
        // MIs[3] VOP3Mods:src0:src0_mods
        GIM_CheckIsSameOperand, /*MI*/3, /*OpIdx*/1, /*OtherMI*/2, /*OtherOpIdx*/1,
        // MIs[3] VOP3Mods:src1:src1_mods
        GIM_CheckIsSameOperand, /*MI*/3, /*OpIdx*/2, /*OtherMI*/2, /*OtherOpIdx*/2,
        GIM_CheckCxxInsnPredicate, /*MI*/0, /*FnId*/GIMT_Encode2(GICXXPred_MI_Predicate_fminnum_like_nnan),
        GIM_CheckIsSafeToFold, /*InsnID*/1,
        GIM_CheckIsSafeToFold, /*InsnID*/2,
        GIM_CheckIsSafeToFold, /*InsnID*/3,
        GIM_CheckComplexPattern, /*MI*/1, /*Op*/1, /*Renderer*/GIMT_Encode2(0), GIMT_Encode2(GICP_gi_vop3mods),
        GIM_CheckComplexPattern, /*MI*/2, /*Op*/1, /*Renderer*/GIMT_Encode2(1), GIMT_Encode2(GICP_gi_vop3mods),
        GIM_CheckComplexPattern, /*MI*/2, /*Op*/2, /*Renderer*/GIMT_Encode2(2), GIMT_Encode2(GICP_gi_vop3mods),
        // (fminnum:{ *:[f32] } (fmaxnum_ieee:{ *:[f32] } (VOP3Mods:{ *:[f32] } f32:{ *:[f32] }:$src2, i32:{ *:[i32] }:$src2_mods), (fminnum_ieee:{ *:[f32] } (VOP3Mods:{ *:[f32] } f32:{ *:[f32] }:$src0, i32:{ *:[i32] }:$src0_mods), (VOP3Mods:{ *:[f32] } f32:{ *:[f32] }:$src1, i32:{ *:[i32] }:$src1_mods))), (fmaxnum:{ *:[f32] } (VOP3Mods:{ *:[f32] } f32:{ *:[f32] }:$src0, i32:{ *:[i32] }:$src0_mods), (VOP3Mods:{ *:[f32] } f32:{ *:[f32] }:$src1, i32:{ *:[i32] }:$src1_mods)))<<P:Predicate_fminnum_like_nnan>>  =>  (V_MED3_F32_e64:{ *:[f32] } ?:{ *:[i32] }:$src0_mods, ?:{ *:[f32] }:$src0, ?:{ *:[i32] }:$src1_mods, ?:{ *:[f32] }:$src1, ?:{ *:[i32] }:$src2_mods, ?:{ *:[f32] }:$src2, 0:{ *:[i1] }, 0:{ *:[i32] })
        GIR_BuildMI, /*InsnID*/0, /*Opcode*/GIMT_Encode2(AMDGPU::V_MED3_F32_e64),
        GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/0, // DstI[vdst]
        GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(1), /*SubOperand*/1, // src0_mods
        GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(1), /*SubOperand*/0, // src0
        GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(2), /*SubOperand*/1, // src1_mods
        GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(2), /*SubOperand*/0, // src1
        GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/1, // src2_mods
        GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/0, // src2
        GIR_AddImm8, /*InsnID*/0, /*Imm*/0,
        GIR_AddImm8, /*InsnID*/0, /*Imm*/0,
        GIR_ConstrainSelectedInstOperands, /*InsnID*/0,
        GIR_EraseFromParent, /*InsnID*/0,
        // GIR_Coverage, 10431,
        GIR_Done,
      // Label 4429: @283907
      GIM_Try, /*On fail goto*//*Label 4430*/ GIMT_Encode4(284047), // Rule ID 10432 //
        GIM_CheckRegBankForClass, /*MI*/0, /*Op*/0, /*RC*/GIMT_Encode2(AMDGPU::VGPR_32RegClassID),
        GIM_RecordInsn, /*DefineMI*/1, /*MI*/0, /*OpIdx*/1, // MIs[1]
        GIM_CheckOpcode, /*MI*/1, GIMT_Encode2(TargetOpcode::G_FMAXNUM_IEEE),
        GIM_CheckType, /*MI*/1, /*Op*/1, /*Type*/GILLT_s32,
        GIM_CheckType, /*MI*/1, /*Op*/2, /*Type*/GILLT_s32,
        GIM_RecordInsn, /*DefineMI*/2, /*MI*/1, /*OpIdx*/2, // MIs[2]
        GIM_CheckOpcode, /*MI*/2, GIMT_Encode2(TargetOpcode::G_FMINNUM_IEEE),
        GIM_CheckType, /*MI*/2, /*Op*/1, /*Type*/GILLT_s32,
        GIM_CheckType, /*MI*/2, /*Op*/2, /*Type*/GILLT_s32,
        GIM_RecordInsn, /*DefineMI*/3, /*MI*/0, /*OpIdx*/2, // MIs[3]
        GIM_CheckOpcode, /*MI*/3, GIMT_Encode2(TargetOpcode::G_FMAXNUM),
        // MIs[3] VOP3Mods:src1:src1_mods
        GIM_CheckIsSameOperand, /*MI*/3, /*OpIdx*/1, /*OtherMI*/2, /*OtherOpIdx*/2,
        // MIs[3] VOP3Mods:src0:src0_mods
        GIM_CheckIsSameOperand, /*MI*/3, /*OpIdx*/2, /*OtherMI*/2, /*OtherOpIdx*/1,
        GIM_CheckCxxInsnPredicate, /*MI*/0, /*FnId*/GIMT_Encode2(GICXXPred_MI_Predicate_fminnum_like_nnan),
        GIM_CheckIsSafeToFold, /*InsnID*/1,
        GIM_CheckIsSafeToFold, /*InsnID*/2,
        GIM_CheckIsSafeToFold, /*InsnID*/3,
        GIM_CheckComplexPattern, /*MI*/1, /*Op*/1, /*Renderer*/GIMT_Encode2(0), GIMT_Encode2(GICP_gi_vop3mods),
        GIM_CheckComplexPattern, /*MI*/2, /*Op*/1, /*Renderer*/GIMT_Encode2(1), GIMT_Encode2(GICP_gi_vop3mods),
        GIM_CheckComplexPattern, /*MI*/2, /*Op*/2, /*Renderer*/GIMT_Encode2(2), GIMT_Encode2(GICP_gi_vop3mods),
        // (fminnum:{ *:[f32] } (fmaxnum_ieee:{ *:[f32] } (VOP3Mods:{ *:[f32] } f32:{ *:[f32] }:$src2, i32:{ *:[i32] }:$src2_mods), (fminnum_ieee:{ *:[f32] } (VOP3Mods:{ *:[f32] } f32:{ *:[f32] }:$src0, i32:{ *:[i32] }:$src0_mods), (VOP3Mods:{ *:[f32] } f32:{ *:[f32] }:$src1, i32:{ *:[i32] }:$src1_mods))), (fmaxnum:{ *:[f32] } (VOP3Mods:{ *:[f32] } f32:{ *:[f32] }:$src1, i32:{ *:[i32] }:$src1_mods), (VOP3Mods:{ *:[f32] } f32:{ *:[f32] }:$src0, i32:{ *:[i32] }:$src0_mods)))<<P:Predicate_fminnum_like_nnan>>  =>  (V_MED3_F32_e64:{ *:[f32] } ?:{ *:[i32] }:$src0_mods, ?:{ *:[f32] }:$src0, ?:{ *:[i32] }:$src1_mods, ?:{ *:[f32] }:$src1, ?:{ *:[i32] }:$src2_mods, ?:{ *:[f32] }:$src2, 0:{ *:[i1] }, 0:{ *:[i32] })
        GIR_BuildMI, /*InsnID*/0, /*Opcode*/GIMT_Encode2(AMDGPU::V_MED3_F32_e64),
        GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/0, // DstI[vdst]
        GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(1), /*SubOperand*/1, // src0_mods
        GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(1), /*SubOperand*/0, // src0
        GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(2), /*SubOperand*/1, // src1_mods
        GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(2), /*SubOperand*/0, // src1
        GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/1, // src2_mods
        GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/0, // src2
        GIR_AddImm8, /*InsnID*/0, /*Imm*/0,
        GIR_AddImm8, /*InsnID*/0, /*Imm*/0,
        GIR_ConstrainSelectedInstOperands, /*InsnID*/0,
        GIR_EraseFromParent, /*InsnID*/0,
        // GIR_Coverage, 10432,
        GIR_Done,
      // Label 4430: @284047
      GIM_Try, /*On fail goto*//*Label 4431*/ GIMT_Encode4(284187), // Rule ID 10433 //
        GIM_CheckRegBankForClass, /*MI*/0, /*Op*/0, /*RC*/GIMT_Encode2(AMDGPU::VGPR_32RegClassID),
        GIM_RecordInsn, /*DefineMI*/1, /*MI*/0, /*OpIdx*/1, // MIs[1]
        GIM_CheckOpcode, /*MI*/1, GIMT_Encode2(TargetOpcode::G_FMAXNUM_IEEE),
        GIM_CheckType, /*MI*/1, /*Op*/1, /*Type*/GILLT_s32,
        GIM_CheckType, /*MI*/1, /*Op*/2, /*Type*/GILLT_s32,
        GIM_RecordInsn, /*DefineMI*/2, /*MI*/1, /*OpIdx*/2, // MIs[2]
        GIM_CheckOpcode, /*MI*/2, GIMT_Encode2(TargetOpcode::G_FMINNUM_IEEE),
        GIM_CheckType, /*MI*/2, /*Op*/1, /*Type*/GILLT_s32,
        GIM_CheckType, /*MI*/2, /*Op*/2, /*Type*/GILLT_s32,
        GIM_RecordInsn, /*DefineMI*/3, /*MI*/0, /*OpIdx*/2, // MIs[3]
        GIM_CheckOpcode, /*MI*/3, GIMT_Encode2(TargetOpcode::G_FMAXNUM),
        // MIs[3] VOP3Mods:src0:src0_mods
        GIM_CheckIsSameOperand, /*MI*/3, /*OpIdx*/1, /*OtherMI*/2, /*OtherOpIdx*/2,
        // MIs[3] VOP3Mods:src1:src1_mods
        GIM_CheckIsSameOperand, /*MI*/3, /*OpIdx*/2, /*OtherMI*/2, /*OtherOpIdx*/1,
        GIM_CheckCxxInsnPredicate, /*MI*/0, /*FnId*/GIMT_Encode2(GICXXPred_MI_Predicate_fminnum_like_nnan),
        GIM_CheckIsSafeToFold, /*InsnID*/1,
        GIM_CheckIsSafeToFold, /*InsnID*/2,
        GIM_CheckIsSafeToFold, /*InsnID*/3,
        GIM_CheckComplexPattern, /*MI*/1, /*Op*/1, /*Renderer*/GIMT_Encode2(0), GIMT_Encode2(GICP_gi_vop3mods),
        GIM_CheckComplexPattern, /*MI*/2, /*Op*/1, /*Renderer*/GIMT_Encode2(1), GIMT_Encode2(GICP_gi_vop3mods),
        GIM_CheckComplexPattern, /*MI*/2, /*Op*/2, /*Renderer*/GIMT_Encode2(2), GIMT_Encode2(GICP_gi_vop3mods),
        // (fminnum:{ *:[f32] } (fmaxnum_ieee:{ *:[f32] } (VOP3Mods:{ *:[f32] } f32:{ *:[f32] }:$src2, i32:{ *:[i32] }:$src2_mods), (fminnum_ieee:{ *:[f32] } (VOP3Mods:{ *:[f32] } f32:{ *:[f32] }:$src1, i32:{ *:[i32] }:$src1_mods), (VOP3Mods:{ *:[f32] } f32:{ *:[f32] }:$src0, i32:{ *:[i32] }:$src0_mods))), (fmaxnum:{ *:[f32] } (VOP3Mods:{ *:[f32] } f32:{ *:[f32] }:$src0, i32:{ *:[i32] }:$src0_mods), (VOP3Mods:{ *:[f32] } f32:{ *:[f32] }:$src1, i32:{ *:[i32] }:$src1_mods)))<<P:Predicate_fminnum_like_nnan>>  =>  (V_MED3_F32_e64:{ *:[f32] } ?:{ *:[i32] }:$src0_mods, ?:{ *:[f32] }:$src0, ?:{ *:[i32] }:$src1_mods, ?:{ *:[f32] }:$src1, ?:{ *:[i32] }:$src2_mods, ?:{ *:[f32] }:$src2, 0:{ *:[i1] }, 0:{ *:[i32] })
        GIR_BuildMI, /*InsnID*/0, /*Opcode*/GIMT_Encode2(AMDGPU::V_MED3_F32_e64),
        GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/0, // DstI[vdst]
        GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(2), /*SubOperand*/1, // src0_mods
        GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(2), /*SubOperand*/0, // src0
        GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(1), /*SubOperand*/1, // src1_mods
        GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(1), /*SubOperand*/0, // src1
        GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/1, // src2_mods
        GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/0, // src2
        GIR_AddImm8, /*InsnID*/0, /*Imm*/0,
        GIR_AddImm8, /*InsnID*/0, /*Imm*/0,
        GIR_ConstrainSelectedInstOperands, /*InsnID*/0,
        GIR_EraseFromParent, /*InsnID*/0,
        // GIR_Coverage, 10433,
        GIR_Done,
      // Label 4431: @284187
      GIM_Try, /*On fail goto*//*Label 4432*/ GIMT_Encode4(284327), // Rule ID 10434 //
        GIM_CheckRegBankForClass, /*MI*/0, /*Op*/0, /*RC*/GIMT_Encode2(AMDGPU::VGPR_32RegClassID),
        GIM_RecordInsn, /*DefineMI*/1, /*MI*/0, /*OpIdx*/1, // MIs[1]
        GIM_CheckOpcode, /*MI*/1, GIMT_Encode2(TargetOpcode::G_FMAXNUM_IEEE),
        GIM_CheckType, /*MI*/1, /*Op*/1, /*Type*/GILLT_s32,
        GIM_CheckType, /*MI*/1, /*Op*/2, /*Type*/GILLT_s32,
        GIM_RecordInsn, /*DefineMI*/2, /*MI*/1, /*OpIdx*/2, // MIs[2]
        GIM_CheckOpcode, /*MI*/2, GIMT_Encode2(TargetOpcode::G_FMINNUM_IEEE),
        GIM_CheckType, /*MI*/2, /*Op*/1, /*Type*/GILLT_s32,
        GIM_CheckType, /*MI*/2, /*Op*/2, /*Type*/GILLT_s32,
        GIM_RecordInsn, /*DefineMI*/3, /*MI*/0, /*OpIdx*/2, // MIs[3]
        GIM_CheckOpcode, /*MI*/3, GIMT_Encode2(TargetOpcode::G_FMAXNUM),
        // MIs[3] VOP3Mods:src1:src1_mods
        GIM_CheckIsSameOperand, /*MI*/3, /*OpIdx*/1, /*OtherMI*/2, /*OtherOpIdx*/1,
        // MIs[3] VOP3Mods:src0:src0_mods
        GIM_CheckIsSameOperand, /*MI*/3, /*OpIdx*/2, /*OtherMI*/2, /*OtherOpIdx*/2,
        GIM_CheckCxxInsnPredicate, /*MI*/0, /*FnId*/GIMT_Encode2(GICXXPred_MI_Predicate_fminnum_like_nnan),
        GIM_CheckIsSafeToFold, /*InsnID*/1,
        GIM_CheckIsSafeToFold, /*InsnID*/2,
        GIM_CheckIsSafeToFold, /*InsnID*/3,
        GIM_CheckComplexPattern, /*MI*/1, /*Op*/1, /*Renderer*/GIMT_Encode2(0), GIMT_Encode2(GICP_gi_vop3mods),
        GIM_CheckComplexPattern, /*MI*/2, /*Op*/1, /*Renderer*/GIMT_Encode2(1), GIMT_Encode2(GICP_gi_vop3mods),
        GIM_CheckComplexPattern, /*MI*/2, /*Op*/2, /*Renderer*/GIMT_Encode2(2), GIMT_Encode2(GICP_gi_vop3mods),
        // (fminnum:{ *:[f32] } (fmaxnum_ieee:{ *:[f32] } (VOP3Mods:{ *:[f32] } f32:{ *:[f32] }:$src2, i32:{ *:[i32] }:$src2_mods), (fminnum_ieee:{ *:[f32] } (VOP3Mods:{ *:[f32] } f32:{ *:[f32] }:$src1, i32:{ *:[i32] }:$src1_mods), (VOP3Mods:{ *:[f32] } f32:{ *:[f32] }:$src0, i32:{ *:[i32] }:$src0_mods))), (fmaxnum:{ *:[f32] } (VOP3Mods:{ *:[f32] } f32:{ *:[f32] }:$src1, i32:{ *:[i32] }:$src1_mods), (VOP3Mods:{ *:[f32] } f32:{ *:[f32] }:$src0, i32:{ *:[i32] }:$src0_mods)))<<P:Predicate_fminnum_like_nnan>>  =>  (V_MED3_F32_e64:{ *:[f32] } ?:{ *:[i32] }:$src0_mods, ?:{ *:[f32] }:$src0, ?:{ *:[i32] }:$src1_mods, ?:{ *:[f32] }:$src1, ?:{ *:[i32] }:$src2_mods, ?:{ *:[f32] }:$src2, 0:{ *:[i1] }, 0:{ *:[i32] })
        GIR_BuildMI, /*InsnID*/0, /*Opcode*/GIMT_Encode2(AMDGPU::V_MED3_F32_e64),
        GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/0, // DstI[vdst]
        GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(2), /*SubOperand*/1, // src0_mods
        GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(2), /*SubOperand*/0, // src0
        GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(1), /*SubOperand*/1, // src1_mods
        GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(1), /*SubOperand*/0, // src1
        GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/1, // src2_mods
        GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/0, // src2
        GIR_AddImm8, /*InsnID*/0, /*Imm*/0,
        GIR_AddImm8, /*InsnID*/0, /*Imm*/0,
        GIR_ConstrainSelectedInstOperands, /*InsnID*/0,
        GIR_EraseFromParent, /*InsnID*/0,
        // GIR_Coverage, 10434,
        GIR_Done,
      // Label 4432: @284327
      GIM_Try, /*On fail goto*//*Label 4433*/ GIMT_Encode4(284467), // Rule ID 10371 //
        GIM_CheckRegBankForClass, /*MI*/0, /*Op*/0, /*RC*/GIMT_Encode2(AMDGPU::VGPR_32RegClassID),
        GIM_RecordInsn, /*DefineMI*/1, /*MI*/0, /*OpIdx*/1, // MIs[1]
        GIM_CheckOpcode, /*MI*/1, GIMT_Encode2(TargetOpcode::G_FMAXNUM_IEEE),
        GIM_CheckType, /*MI*/1, /*Op*/1, /*Type*/GILLT_s32,
        GIM_CheckType, /*MI*/1, /*Op*/2, /*Type*/GILLT_s32,
        GIM_RecordInsn, /*DefineMI*/2, /*MI*/1, /*OpIdx*/2, // MIs[2]
        GIM_CheckOpcode, /*MI*/2, GIMT_Encode2(TargetOpcode::G_FMINNUM_IEEE),
        GIM_CheckType, /*MI*/2, /*Op*/1, /*Type*/GILLT_s32,
        GIM_CheckType, /*MI*/2, /*Op*/2, /*Type*/GILLT_s32,
        GIM_RecordInsn, /*DefineMI*/3, /*MI*/0, /*OpIdx*/2, // MIs[3]
        GIM_CheckOpcode, /*MI*/3, GIMT_Encode2(TargetOpcode::G_FMAXNUM_IEEE),
        // MIs[3] VOP3Mods:src0:src0_mods
        GIM_CheckIsSameOperand, /*MI*/3, /*OpIdx*/1, /*OtherMI*/2, /*OtherOpIdx*/1,
        // MIs[3] VOP3Mods:src1:src1_mods
        GIM_CheckIsSameOperand, /*MI*/3, /*OpIdx*/2, /*OtherMI*/2, /*OtherOpIdx*/2,
        GIM_CheckCxxInsnPredicate, /*MI*/0, /*FnId*/GIMT_Encode2(GICXXPred_MI_Predicate_fminnum_like_nnan),
        GIM_CheckIsSafeToFold, /*InsnID*/1,
        GIM_CheckIsSafeToFold, /*InsnID*/2,
        GIM_CheckIsSafeToFold, /*InsnID*/3,
        GIM_CheckComplexPattern, /*MI*/1, /*Op*/1, /*Renderer*/GIMT_Encode2(0), GIMT_Encode2(GICP_gi_vop3mods),
        GIM_CheckComplexPattern, /*MI*/2, /*Op*/1, /*Renderer*/GIMT_Encode2(1), GIMT_Encode2(GICP_gi_vop3mods),
        GIM_CheckComplexPattern, /*MI*/2, /*Op*/2, /*Renderer*/GIMT_Encode2(2), GIMT_Encode2(GICP_gi_vop3mods),
        // (fminnum:{ *:[f32] } (fmaxnum_ieee:{ *:[f32] } (VOP3Mods:{ *:[f32] } f32:{ *:[f32] }:$src2, i32:{ *:[i32] }:$src2_mods), (fminnum_ieee:{ *:[f32] } (VOP3Mods:{ *:[f32] } f32:{ *:[f32] }:$src0, i32:{ *:[i32] }:$src0_mods), (VOP3Mods:{ *:[f32] } f32:{ *:[f32] }:$src1, i32:{ *:[i32] }:$src1_mods))), (fmaxnum_ieee:{ *:[f32] } (VOP3Mods:{ *:[f32] } f32:{ *:[f32] }:$src0, i32:{ *:[i32] }:$src0_mods), (VOP3Mods:{ *:[f32] } f32:{ *:[f32] }:$src1, i32:{ *:[i32] }:$src1_mods)))<<P:Predicate_fminnum_like_nnan>>  =>  (V_MED3_F32_e64:{ *:[f32] } ?:{ *:[i32] }:$src0_mods, ?:{ *:[f32] }:$src0, ?:{ *:[i32] }:$src1_mods, ?:{ *:[f32] }:$src1, ?:{ *:[i32] }:$src2_mods, ?:{ *:[f32] }:$src2, 0:{ *:[i1] }, 0:{ *:[i32] })
        GIR_BuildMI, /*InsnID*/0, /*Opcode*/GIMT_Encode2(AMDGPU::V_MED3_F32_e64),
        GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/0, // DstI[vdst]
        GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(1), /*SubOperand*/1, // src0_mods
        GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(1), /*SubOperand*/0, // src0
        GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(2), /*SubOperand*/1, // src1_mods
        GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(2), /*SubOperand*/0, // src1
        GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/1, // src2_mods
        GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/0, // src2
        GIR_AddImm8, /*InsnID*/0, /*Imm*/0,
        GIR_AddImm8, /*InsnID*/0, /*Imm*/0,
        GIR_ConstrainSelectedInstOperands, /*InsnID*/0,
        GIR_EraseFromParent, /*InsnID*/0,
        // GIR_Coverage, 10371,
        GIR_Done,
      // Label 4433: @284467
      GIM_Try, /*On fail goto*//*Label 4434*/ GIMT_Encode4(284607), // Rule ID 10372 //
        GIM_CheckRegBankForClass, /*MI*/0, /*Op*/0, /*RC*/GIMT_Encode2(AMDGPU::VGPR_32RegClassID),
        GIM_RecordInsn, /*DefineMI*/1, /*MI*/0, /*OpIdx*/1, // MIs[1]
        GIM_CheckOpcode, /*MI*/1, GIMT_Encode2(TargetOpcode::G_FMAXNUM_IEEE),
        GIM_CheckType, /*MI*/1, /*Op*/1, /*Type*/GILLT_s32,
        GIM_CheckType, /*MI*/1, /*Op*/2, /*Type*/GILLT_s32,
        GIM_RecordInsn, /*DefineMI*/2, /*MI*/1, /*OpIdx*/2, // MIs[2]
        GIM_CheckOpcode, /*MI*/2, GIMT_Encode2(TargetOpcode::G_FMINNUM_IEEE),
        GIM_CheckType, /*MI*/2, /*Op*/1, /*Type*/GILLT_s32,
        GIM_CheckType, /*MI*/2, /*Op*/2, /*Type*/GILLT_s32,
        GIM_RecordInsn, /*DefineMI*/3, /*MI*/0, /*OpIdx*/2, // MIs[3]
        GIM_CheckOpcode, /*MI*/3, GIMT_Encode2(TargetOpcode::G_FMAXNUM_IEEE),
        // MIs[3] VOP3Mods:src1:src1_mods
        GIM_CheckIsSameOperand, /*MI*/3, /*OpIdx*/1, /*OtherMI*/2, /*OtherOpIdx*/2,
        // MIs[3] VOP3Mods:src0:src0_mods
        GIM_CheckIsSameOperand, /*MI*/3, /*OpIdx*/2, /*OtherMI*/2, /*OtherOpIdx*/1,
        GIM_CheckCxxInsnPredicate, /*MI*/0, /*FnId*/GIMT_Encode2(GICXXPred_MI_Predicate_fminnum_like_nnan),
        GIM_CheckIsSafeToFold, /*InsnID*/1,
        GIM_CheckIsSafeToFold, /*InsnID*/2,
        GIM_CheckIsSafeToFold, /*InsnID*/3,
        GIM_CheckComplexPattern, /*MI*/1, /*Op*/1, /*Renderer*/GIMT_Encode2(0), GIMT_Encode2(GICP_gi_vop3mods),
        GIM_CheckComplexPattern, /*MI*/2, /*Op*/1, /*Renderer*/GIMT_Encode2(1), GIMT_Encode2(GICP_gi_vop3mods),
        GIM_CheckComplexPattern, /*MI*/2, /*Op*/2, /*Renderer*/GIMT_Encode2(2), GIMT_Encode2(GICP_gi_vop3mods),
        // (fminnum:{ *:[f32] } (fmaxnum_ieee:{ *:[f32] } (VOP3Mods:{ *:[f32] } f32:{ *:[f32] }:$src2, i32:{ *:[i32] }:$src2_mods), (fminnum_ieee:{ *:[f32] } (VOP3Mods:{ *:[f32] } f32:{ *:[f32] }:$src0, i32:{ *:[i32] }:$src0_mods), (VOP3Mods:{ *:[f32] } f32:{ *:[f32] }:$src1, i32:{ *:[i32] }:$src1_mods))), (fmaxnum_ieee:{ *:[f32] } (VOP3Mods:{ *:[f32] } f32:{ *:[f32] }:$src1, i32:{ *:[i32] }:$src1_mods), (VOP3Mods:{ *:[f32] } f32:{ *:[f32] }:$src0, i32:{ *:[i32] }:$src0_mods)))<<P:Predicate_fminnum_like_nnan>>  =>  (V_MED3_F32_e64:{ *:[f32] } ?:{ *:[i32] }:$src0_mods, ?:{ *:[f32] }:$src0, ?:{ *:[i32] }:$src1_mods, ?:{ *:[f32] }:$src1, ?:{ *:[i32] }:$src2_mods, ?:{ *:[f32] }:$src2, 0:{ *:[i1] }, 0:{ *:[i32] })
        GIR_BuildMI, /*InsnID*/0, /*Opcode*/GIMT_Encode2(AMDGPU::V_MED3_F32_e64),
        GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/0, // DstI[vdst]
        GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(1), /*SubOperand*/1, // src0_mods
        GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(1), /*SubOperand*/0, // src0
        GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(2), /*SubOperand*/1, // src1_mods
        GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(2), /*SubOperand*/0, // src1
        GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/1, // src2_mods
        GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/0, // src2
        GIR_AddImm8, /*InsnID*/0, /*Imm*/0,
        GIR_AddImm8, /*InsnID*/0, /*Imm*/0,
        GIR_ConstrainSelectedInstOperands, /*InsnID*/0,
        GIR_EraseFromParent, /*InsnID*/0,
        // GIR_Coverage, 10372,
        GIR_Done,
      // Label 4434: @284607
      GIM_Try, /*On fail goto*//*Label 4435*/ GIMT_Encode4(284747), // Rule ID 10373 //
        GIM_CheckRegBankForClass, /*MI*/0, /*Op*/0, /*RC*/GIMT_Encode2(AMDGPU::VGPR_32RegClassID),
        GIM_RecordInsn, /*DefineMI*/1, /*MI*/0, /*OpIdx*/1, // MIs[1]
        GIM_CheckOpcode, /*MI*/1, GIMT_Encode2(TargetOpcode::G_FMAXNUM_IEEE),
        GIM_CheckType, /*MI*/1, /*Op*/1, /*Type*/GILLT_s32,
        GIM_CheckType, /*MI*/1, /*Op*/2, /*Type*/GILLT_s32,
        GIM_RecordInsn, /*DefineMI*/2, /*MI*/1, /*OpIdx*/2, // MIs[2]
        GIM_CheckOpcode, /*MI*/2, GIMT_Encode2(TargetOpcode::G_FMINNUM_IEEE),
        GIM_CheckType, /*MI*/2, /*Op*/1, /*Type*/GILLT_s32,
        GIM_CheckType, /*MI*/2, /*Op*/2, /*Type*/GILLT_s32,
        GIM_RecordInsn, /*DefineMI*/3, /*MI*/0, /*OpIdx*/2, // MIs[3]
        GIM_CheckOpcode, /*MI*/3, GIMT_Encode2(TargetOpcode::G_FMAXNUM_IEEE),
        // MIs[3] VOP3Mods:src0:src0_mods
        GIM_CheckIsSameOperand, /*MI*/3, /*OpIdx*/1, /*OtherMI*/2, /*OtherOpIdx*/2,
        // MIs[3] VOP3Mods:src1:src1_mods
        GIM_CheckIsSameOperand, /*MI*/3, /*OpIdx*/2, /*OtherMI*/2, /*OtherOpIdx*/1,
        GIM_CheckCxxInsnPredicate, /*MI*/0, /*FnId*/GIMT_Encode2(GICXXPred_MI_Predicate_fminnum_like_nnan),
        GIM_CheckIsSafeToFold, /*InsnID*/1,
        GIM_CheckIsSafeToFold, /*InsnID*/2,
        GIM_CheckIsSafeToFold, /*InsnID*/3,
        GIM_CheckComplexPattern, /*MI*/1, /*Op*/1, /*Renderer*/GIMT_Encode2(0), GIMT_Encode2(GICP_gi_vop3mods),
        GIM_CheckComplexPattern, /*MI*/2, /*Op*/1, /*Renderer*/GIMT_Encode2(1), GIMT_Encode2(GICP_gi_vop3mods),
        GIM_CheckComplexPattern, /*MI*/2, /*Op*/2, /*Renderer*/GIMT_Encode2(2), GIMT_Encode2(GICP_gi_vop3mods),
        // (fminnum:{ *:[f32] } (fmaxnum_ieee:{ *:[f32] } (VOP3Mods:{ *:[f32] } f32:{ *:[f32] }:$src2, i32:{ *:[i32] }:$src2_mods), (fminnum_ieee:{ *:[f32] } (VOP3Mods:{ *:[f32] } f32:{ *:[f32] }:$src1, i32:{ *:[i32] }:$src1_mods), (VOP3Mods:{ *:[f32] } f32:{ *:[f32] }:$src0, i32:{ *:[i32] }:$src0_mods))), (fmaxnum_ieee:{ *:[f32] } (VOP3Mods:{ *:[f32] } f32:{ *:[f32] }:$src0, i32:{ *:[i32] }:$src0_mods), (VOP3Mods:{ *:[f32] } f32:{ *:[f32] }:$src1, i32:{ *:[i32] }:$src1_mods)))<<P:Predicate_fminnum_like_nnan>>  =>  (V_MED3_F32_e64:{ *:[f32] } ?:{ *:[i32] }:$src0_mods, ?:{ *:[f32] }:$src0, ?:{ *:[i32] }:$src1_mods, ?:{ *:[f32] }:$src1, ?:{ *:[i32] }:$src2_mods, ?:{ *:[f32] }:$src2, 0:{ *:[i1] }, 0:{ *:[i32] })
        GIR_BuildMI, /*InsnID*/0, /*Opcode*/GIMT_Encode2(AMDGPU::V_MED3_F32_e64),
        GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/0, // DstI[vdst]
        GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(2), /*SubOperand*/1, // src0_mods
        GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(2), /*SubOperand*/0, // src0
        GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(1), /*SubOperand*/1, // src1_mods
        GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(1), /*SubOperand*/0, // src1
        GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/1, // src2_mods
        GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/0, // src2
        GIR_AddImm8, /*InsnID*/0, /*Imm*/0,
        GIR_AddImm8, /*InsnID*/0, /*Imm*/0,
        GIR_ConstrainSelectedInstOperands, /*InsnID*/0,
        GIR_EraseFromParent, /*InsnID*/0,
        // GIR_Coverage, 10373,
        GIR_Done,
      // Label 4435: @284747
      GIM_Try, /*On fail goto*//*Label 4436*/ GIMT_Encode4(284887), // Rule ID 10374 //
        GIM_CheckRegBankForClass, /*MI*/0, /*Op*/0, /*RC*/GIMT_Encode2(AMDGPU::VGPR_32RegClassID),
        GIM_RecordInsn, /*DefineMI*/1, /*MI*/0, /*OpIdx*/1, // MIs[1]
        GIM_CheckOpcode, /*MI*/1, GIMT_Encode2(TargetOpcode::G_FMAXNUM_IEEE),
        GIM_CheckType, /*MI*/1, /*Op*/1, /*Type*/GILLT_s32,
        GIM_CheckType, /*MI*/1, /*Op*/2, /*Type*/GILLT_s32,
        GIM_RecordInsn, /*DefineMI*/2, /*MI*/1, /*OpIdx*/2, // MIs[2]
        GIM_CheckOpcode, /*MI*/2, GIMT_Encode2(TargetOpcode::G_FMINNUM_IEEE),
        GIM_CheckType, /*MI*/2, /*Op*/1, /*Type*/GILLT_s32,
        GIM_CheckType, /*MI*/2, /*Op*/2, /*Type*/GILLT_s32,
        GIM_RecordInsn, /*DefineMI*/3, /*MI*/0, /*OpIdx*/2, // MIs[3]
        GIM_CheckOpcode, /*MI*/3, GIMT_Encode2(TargetOpcode::G_FMAXNUM_IEEE),
        // MIs[3] VOP3Mods:src1:src1_mods
        GIM_CheckIsSameOperand, /*MI*/3, /*OpIdx*/1, /*OtherMI*/2, /*OtherOpIdx*/1,
        // MIs[3] VOP3Mods:src0:src0_mods
        GIM_CheckIsSameOperand, /*MI*/3, /*OpIdx*/2, /*OtherMI*/2, /*OtherOpIdx*/2,
        GIM_CheckCxxInsnPredicate, /*MI*/0, /*FnId*/GIMT_Encode2(GICXXPred_MI_Predicate_fminnum_like_nnan),
        GIM_CheckIsSafeToFold, /*InsnID*/1,
        GIM_CheckIsSafeToFold, /*InsnID*/2,
        GIM_CheckIsSafeToFold, /*InsnID*/3,
        GIM_CheckComplexPattern, /*MI*/1, /*Op*/1, /*Renderer*/GIMT_Encode2(0), GIMT_Encode2(GICP_gi_vop3mods),
        GIM_CheckComplexPattern, /*MI*/2, /*Op*/1, /*Renderer*/GIMT_Encode2(1), GIMT_Encode2(GICP_gi_vop3mods),
        GIM_CheckComplexPattern, /*MI*/2, /*Op*/2, /*Renderer*/GIMT_Encode2(2), GIMT_Encode2(GICP_gi_vop3mods),
        // (fminnum:{ *:[f32] } (fmaxnum_ieee:{ *:[f32] } (VOP3Mods:{ *:[f32] } f32:{ *:[f32] }:$src2, i32:{ *:[i32] }:$src2_mods), (fminnum_ieee:{ *:[f32] } (VOP3Mods:{ *:[f32] } f32:{ *:[f32] }:$src1, i32:{ *:[i32] }:$src1_mods), (VOP3Mods:{ *:[f32] } f32:{ *:[f32] }:$src0, i32:{ *:[i32] }:$src0_mods))), (fmaxnum_ieee:{ *:[f32] } (VOP3Mods:{ *:[f32] } f32:{ *:[f32] }:$src1, i32:{ *:[i32] }:$src1_mods), (VOP3Mods:{ *:[f32] } f32:{ *:[f32] }:$src0, i32:{ *:[i32] }:$src0_mods)))<<P:Predicate_fminnum_like_nnan>>  =>  (V_MED3_F32_e64:{ *:[f32] } ?:{ *:[i32] }:$src0_mods, ?:{ *:[f32] }:$src0, ?:{ *:[i32] }:$src1_mods, ?:{ *:[f32] }:$src1, ?:{ *:[i32] }:$src2_mods, ?:{ *:[f32] }:$src2, 0:{ *:[i1] }, 0:{ *:[i32] })
        GIR_BuildMI, /*InsnID*/0, /*Opcode*/GIMT_Encode2(AMDGPU::V_MED3_F32_e64),
        GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/0, // DstI[vdst]
        GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(2), /*SubOperand*/1, // src0_mods
        GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(2), /*SubOperand*/0, // src0
        GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(1), /*SubOperand*/1, // src1_mods
        GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(1), /*SubOperand*/0, // src1
        GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/1, // src2_mods
        GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/0, // src2
        GIR_AddImm8, /*InsnID*/0, /*Imm*/0,
        GIR_AddImm8, /*InsnID*/0, /*Imm*/0,
        GIR_ConstrainSelectedInstOperands, /*InsnID*/0,
        GIR_EraseFromParent, /*InsnID*/0,
        // GIR_Coverage, 10374,
        GIR_Done,
      // Label 4436: @284887
      GIM_Try, /*On fail goto*//*Label 4437*/ GIMT_Encode4(285027), // Rule ID 10442 //
        GIM_CheckRegBankForClass, /*MI*/0, /*Op*/0, /*RC*/GIMT_Encode2(AMDGPU::VGPR_32RegClassID),
        GIM_RecordInsn, /*DefineMI*/1, /*MI*/0, /*OpIdx*/1, // MIs[1]
        GIM_CheckOpcode, /*MI*/1, GIMT_Encode2(TargetOpcode::G_FMAXNUM_IEEE),
        GIM_CheckType, /*MI*/1, /*Op*/1, /*Type*/GILLT_s32,
        GIM_CheckType, /*MI*/1, /*Op*/2, /*Type*/GILLT_s32,
        GIM_RecordInsn, /*DefineMI*/2, /*MI*/1, /*OpIdx*/1, // MIs[2]
        GIM_CheckOpcode, /*MI*/2, GIMT_Encode2(TargetOpcode::G_FMINNUM),
        GIM_CheckType, /*MI*/2, /*Op*/1, /*Type*/GILLT_s32,
        GIM_CheckType, /*MI*/2, /*Op*/2, /*Type*/GILLT_s32,
        GIM_RecordInsn, /*DefineMI*/3, /*MI*/0, /*OpIdx*/2, // MIs[3]
        GIM_CheckOpcode, /*MI*/3, GIMT_Encode2(TargetOpcode::G_FMAXNUM),
        // MIs[3] VOP3Mods:src0:src0_mods
        GIM_CheckIsSameOperand, /*MI*/3, /*OpIdx*/1, /*OtherMI*/2, /*OtherOpIdx*/1,
        // MIs[3] VOP3Mods:src1:src1_mods
        GIM_CheckIsSameOperand, /*MI*/3, /*OpIdx*/2, /*OtherMI*/2, /*OtherOpIdx*/2,
        GIM_CheckCxxInsnPredicate, /*MI*/0, /*FnId*/GIMT_Encode2(GICXXPred_MI_Predicate_fminnum_like_nnan),
        GIM_CheckIsSafeToFold, /*InsnID*/1,
        GIM_CheckIsSafeToFold, /*InsnID*/2,
        GIM_CheckIsSafeToFold, /*InsnID*/3,
        GIM_CheckComplexPattern, /*MI*/1, /*Op*/2, /*Renderer*/GIMT_Encode2(2), GIMT_Encode2(GICP_gi_vop3mods),
        GIM_CheckComplexPattern, /*MI*/2, /*Op*/1, /*Renderer*/GIMT_Encode2(0), GIMT_Encode2(GICP_gi_vop3mods),
        GIM_CheckComplexPattern, /*MI*/2, /*Op*/2, /*Renderer*/GIMT_Encode2(1), GIMT_Encode2(GICP_gi_vop3mods),
        // (fminnum:{ *:[f32] } (fmaxnum_ieee:{ *:[f32] } (fminnum:{ *:[f32] } (VOP3Mods:{ *:[f32] } f32:{ *:[f32] }:$src0, i32:{ *:[i32] }:$src0_mods), (VOP3Mods:{ *:[f32] } f32:{ *:[f32] }:$src1, i32:{ *:[i32] }:$src1_mods)), (VOP3Mods:{ *:[f32] } f32:{ *:[f32] }:$src2, i32:{ *:[i32] }:$src2_mods)), (fmaxnum:{ *:[f32] } (VOP3Mods:{ *:[f32] } f32:{ *:[f32] }:$src0, i32:{ *:[i32] }:$src0_mods), (VOP3Mods:{ *:[f32] } f32:{ *:[f32] }:$src1, i32:{ *:[i32] }:$src1_mods)))<<P:Predicate_fminnum_like_nnan>>  =>  (V_MED3_F32_e64:{ *:[f32] } ?:{ *:[i32] }:$src0_mods, ?:{ *:[f32] }:$src0, ?:{ *:[i32] }:$src1_mods, ?:{ *:[f32] }:$src1, ?:{ *:[i32] }:$src2_mods, ?:{ *:[f32] }:$src2, 0:{ *:[i1] }, 0:{ *:[i32] })
        GIR_BuildMI, /*InsnID*/0, /*Opcode*/GIMT_Encode2(AMDGPU::V_MED3_F32_e64),
        GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/0, // DstI[vdst]
        GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/1, // src0_mods
        GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/0, // src0
        GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(1), /*SubOperand*/1, // src1_mods
        GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(1), /*SubOperand*/0, // src1
        GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(2), /*SubOperand*/1, // src2_mods
        GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(2), /*SubOperand*/0, // src2
        GIR_AddImm8, /*InsnID*/0, /*Imm*/0,
        GIR_AddImm8, /*InsnID*/0, /*Imm*/0,
        GIR_ConstrainSelectedInstOperands, /*InsnID*/0,
        GIR_EraseFromParent, /*InsnID*/0,
        // GIR_Coverage, 10442,
        GIR_Done,
      // Label 4437: @285027
      GIM_Try, /*On fail goto*//*Label 4438*/ GIMT_Encode4(285167), // Rule ID 10443 //
        GIM_CheckRegBankForClass, /*MI*/0, /*Op*/0, /*RC*/GIMT_Encode2(AMDGPU::VGPR_32RegClassID),
        GIM_RecordInsn, /*DefineMI*/1, /*MI*/0, /*OpIdx*/1, // MIs[1]
        GIM_CheckOpcode, /*MI*/1, GIMT_Encode2(TargetOpcode::G_FMAXNUM_IEEE),
        GIM_CheckType, /*MI*/1, /*Op*/1, /*Type*/GILLT_s32,
        GIM_CheckType, /*MI*/1, /*Op*/2, /*Type*/GILLT_s32,
        GIM_RecordInsn, /*DefineMI*/2, /*MI*/1, /*OpIdx*/1, // MIs[2]
        GIM_CheckOpcode, /*MI*/2, GIMT_Encode2(TargetOpcode::G_FMINNUM),
        GIM_CheckType, /*MI*/2, /*Op*/1, /*Type*/GILLT_s32,
        GIM_CheckType, /*MI*/2, /*Op*/2, /*Type*/GILLT_s32,
        GIM_RecordInsn, /*DefineMI*/3, /*MI*/0, /*OpIdx*/2, // MIs[3]
        GIM_CheckOpcode, /*MI*/3, GIMT_Encode2(TargetOpcode::G_FMAXNUM),
        // MIs[3] VOP3Mods:src1:src1_mods
        GIM_CheckIsSameOperand, /*MI*/3, /*OpIdx*/1, /*OtherMI*/2, /*OtherOpIdx*/2,
        // MIs[3] VOP3Mods:src0:src0_mods
        GIM_CheckIsSameOperand, /*MI*/3, /*OpIdx*/2, /*OtherMI*/2, /*OtherOpIdx*/1,
        GIM_CheckCxxInsnPredicate, /*MI*/0, /*FnId*/GIMT_Encode2(GICXXPred_MI_Predicate_fminnum_like_nnan),
        GIM_CheckIsSafeToFold, /*InsnID*/1,
        GIM_CheckIsSafeToFold, /*InsnID*/2,
        GIM_CheckIsSafeToFold, /*InsnID*/3,
        GIM_CheckComplexPattern, /*MI*/1, /*Op*/2, /*Renderer*/GIMT_Encode2(2), GIMT_Encode2(GICP_gi_vop3mods),
        GIM_CheckComplexPattern, /*MI*/2, /*Op*/1, /*Renderer*/GIMT_Encode2(0), GIMT_Encode2(GICP_gi_vop3mods),
        GIM_CheckComplexPattern, /*MI*/2, /*Op*/2, /*Renderer*/GIMT_Encode2(1), GIMT_Encode2(GICP_gi_vop3mods),
        // (fminnum:{ *:[f32] } (fmaxnum_ieee:{ *:[f32] } (fminnum:{ *:[f32] } (VOP3Mods:{ *:[f32] } f32:{ *:[f32] }:$src0, i32:{ *:[i32] }:$src0_mods), (VOP3Mods:{ *:[f32] } f32:{ *:[f32] }:$src1, i32:{ *:[i32] }:$src1_mods)), (VOP3Mods:{ *:[f32] } f32:{ *:[f32] }:$src2, i32:{ *:[i32] }:$src2_mods)), (fmaxnum:{ *:[f32] } (VOP3Mods:{ *:[f32] } f32:{ *:[f32] }:$src1, i32:{ *:[i32] }:$src1_mods), (VOP3Mods:{ *:[f32] } f32:{ *:[f32] }:$src0, i32:{ *:[i32] }:$src0_mods)))<<P:Predicate_fminnum_like_nnan>>  =>  (V_MED3_F32_e64:{ *:[f32] } ?:{ *:[i32] }:$src0_mods, ?:{ *:[f32] }:$src0, ?:{ *:[i32] }:$src1_mods, ?:{ *:[f32] }:$src1, ?:{ *:[i32] }:$src2_mods, ?:{ *:[f32] }:$src2, 0:{ *:[i1] }, 0:{ *:[i32] })
        GIR_BuildMI, /*InsnID*/0, /*Opcode*/GIMT_Encode2(AMDGPU::V_MED3_F32_e64),
        GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/0, // DstI[vdst]
        GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/1, // src0_mods
        GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/0, // src0
        GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(1), /*SubOperand*/1, // src1_mods
        GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(1), /*SubOperand*/0, // src1
        GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(2), /*SubOperand*/1, // src2_mods
        GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(2), /*SubOperand*/0, // src2
        GIR_AddImm8, /*InsnID*/0, /*Imm*/0,
        GIR_AddImm8, /*InsnID*/0, /*Imm*/0,
        GIR_ConstrainSelectedInstOperands, /*InsnID*/0,
        GIR_EraseFromParent, /*InsnID*/0,
        // GIR_Coverage, 10443,
        GIR_Done,
      // Label 4438: @285167
      GIM_Try, /*On fail goto*//*Label 4439*/ GIMT_Encode4(285307), // Rule ID 10444 //
        GIM_CheckRegBankForClass, /*MI*/0, /*Op*/0, /*RC*/GIMT_Encode2(AMDGPU::VGPR_32RegClassID),
        GIM_RecordInsn, /*DefineMI*/1, /*MI*/0, /*OpIdx*/1, // MIs[1]
        GIM_CheckOpcode, /*MI*/1, GIMT_Encode2(TargetOpcode::G_FMAXNUM_IEEE),
        GIM_CheckType, /*MI*/1, /*Op*/1, /*Type*/GILLT_s32,
        GIM_CheckType, /*MI*/1, /*Op*/2, /*Type*/GILLT_s32,
        GIM_RecordInsn, /*DefineMI*/2, /*MI*/1, /*OpIdx*/1, // MIs[2]
        GIM_CheckOpcode, /*MI*/2, GIMT_Encode2(TargetOpcode::G_FMINNUM),
        GIM_CheckType, /*MI*/2, /*Op*/1, /*Type*/GILLT_s32,
        GIM_CheckType, /*MI*/2, /*Op*/2, /*Type*/GILLT_s32,
        GIM_RecordInsn, /*DefineMI*/3, /*MI*/0, /*OpIdx*/2, // MIs[3]
        GIM_CheckOpcode, /*MI*/3, GIMT_Encode2(TargetOpcode::G_FMAXNUM),
        // MIs[3] VOP3Mods:src0:src0_mods
        GIM_CheckIsSameOperand, /*MI*/3, /*OpIdx*/1, /*OtherMI*/2, /*OtherOpIdx*/2,
        // MIs[3] VOP3Mods:src1:src1_mods
        GIM_CheckIsSameOperand, /*MI*/3, /*OpIdx*/2, /*OtherMI*/2, /*OtherOpIdx*/1,
        GIM_CheckCxxInsnPredicate, /*MI*/0, /*FnId*/GIMT_Encode2(GICXXPred_MI_Predicate_fminnum_like_nnan),
        GIM_CheckIsSafeToFold, /*InsnID*/1,
        GIM_CheckIsSafeToFold, /*InsnID*/2,
        GIM_CheckIsSafeToFold, /*InsnID*/3,
        GIM_CheckComplexPattern, /*MI*/1, /*Op*/2, /*Renderer*/GIMT_Encode2(2), GIMT_Encode2(GICP_gi_vop3mods),
        GIM_CheckComplexPattern, /*MI*/2, /*Op*/1, /*Renderer*/GIMT_Encode2(0), GIMT_Encode2(GICP_gi_vop3mods),
        GIM_CheckComplexPattern, /*MI*/2, /*Op*/2, /*Renderer*/GIMT_Encode2(1), GIMT_Encode2(GICP_gi_vop3mods),
        // (fminnum:{ *:[f32] } (fmaxnum_ieee:{ *:[f32] } (fminnum:{ *:[f32] } (VOP3Mods:{ *:[f32] } f32:{ *:[f32] }:$src1, i32:{ *:[i32] }:$src1_mods), (VOP3Mods:{ *:[f32] } f32:{ *:[f32] }:$src0, i32:{ *:[i32] }:$src0_mods)), (VOP3Mods:{ *:[f32] } f32:{ *:[f32] }:$src2, i32:{ *:[i32] }:$src2_mods)), (fmaxnum:{ *:[f32] } (VOP3Mods:{ *:[f32] } f32:{ *:[f32] }:$src0, i32:{ *:[i32] }:$src0_mods), (VOP3Mods:{ *:[f32] } f32:{ *:[f32] }:$src1, i32:{ *:[i32] }:$src1_mods)))<<P:Predicate_fminnum_like_nnan>>  =>  (V_MED3_F32_e64:{ *:[f32] } ?:{ *:[i32] }:$src0_mods, ?:{ *:[f32] }:$src0, ?:{ *:[i32] }:$src1_mods, ?:{ *:[f32] }:$src1, ?:{ *:[i32] }:$src2_mods, ?:{ *:[f32] }:$src2, 0:{ *:[i1] }, 0:{ *:[i32] })
        GIR_BuildMI, /*InsnID*/0, /*Opcode*/GIMT_Encode2(AMDGPU::V_MED3_F32_e64),
        GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/0, // DstI[vdst]
        GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(1), /*SubOperand*/1, // src0_mods
        GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(1), /*SubOperand*/0, // src0
        GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/1, // src1_mods
        GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/0, // src1
        GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(2), /*SubOperand*/1, // src2_mods
        GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(2), /*SubOperand*/0, // src2
        GIR_AddImm8, /*InsnID*/0, /*Imm*/0,
        GIR_AddImm8, /*InsnID*/0, /*Imm*/0,
        GIR_ConstrainSelectedInstOperands, /*InsnID*/0,
        GIR_EraseFromParent, /*InsnID*/0,
        // GIR_Coverage, 10444,
        GIR_Done,
      // Label 4439: @285307
      GIM_Try, /*On fail goto*//*Label 4440*/ GIMT_Encode4(285447), // Rule ID 10445 //
        GIM_CheckRegBankForClass, /*MI*/0, /*Op*/0, /*RC*/GIMT_Encode2(AMDGPU::VGPR_32RegClassID),
        GIM_RecordInsn, /*DefineMI*/1, /*MI*/0, /*OpIdx*/1, // MIs[1]
        GIM_CheckOpcode, /*MI*/1, GIMT_Encode2(TargetOpcode::G_FMAXNUM_IEEE),
        GIM_CheckType, /*MI*/1, /*Op*/1, /*Type*/GILLT_s32,
        GIM_CheckType, /*MI*/1, /*Op*/2, /*Type*/GILLT_s32,
        GIM_RecordInsn, /*DefineMI*/2, /*MI*/1, /*OpIdx*/1, // MIs[2]
        GIM_CheckOpcode, /*MI*/2, GIMT_Encode2(TargetOpcode::G_FMINNUM),
        GIM_CheckType, /*MI*/2, /*Op*/1, /*Type*/GILLT_s32,
        GIM_CheckType, /*MI*/2, /*Op*/2, /*Type*/GILLT_s32,
        GIM_RecordInsn, /*DefineMI*/3, /*MI*/0, /*OpIdx*/2, // MIs[3]
        GIM_CheckOpcode, /*MI*/3, GIMT_Encode2(TargetOpcode::G_FMAXNUM),
        // MIs[3] VOP3Mods:src1:src1_mods
        GIM_CheckIsSameOperand, /*MI*/3, /*OpIdx*/1, /*OtherMI*/2, /*OtherOpIdx*/1,
        // MIs[3] VOP3Mods:src0:src0_mods
        GIM_CheckIsSameOperand, /*MI*/3, /*OpIdx*/2, /*OtherMI*/2, /*OtherOpIdx*/2,
        GIM_CheckCxxInsnPredicate, /*MI*/0, /*FnId*/GIMT_Encode2(GICXXPred_MI_Predicate_fminnum_like_nnan),
        GIM_CheckIsSafeToFold, /*InsnID*/1,
        GIM_CheckIsSafeToFold, /*InsnID*/2,
        GIM_CheckIsSafeToFold, /*InsnID*/3,
        GIM_CheckComplexPattern, /*MI*/1, /*Op*/2, /*Renderer*/GIMT_Encode2(2), GIMT_Encode2(GICP_gi_vop3mods),
        GIM_CheckComplexPattern, /*MI*/2, /*Op*/1, /*Renderer*/GIMT_Encode2(0), GIMT_Encode2(GICP_gi_vop3mods),
        GIM_CheckComplexPattern, /*MI*/2, /*Op*/2, /*Renderer*/GIMT_Encode2(1), GIMT_Encode2(GICP_gi_vop3mods),
        // (fminnum:{ *:[f32] } (fmaxnum_ieee:{ *:[f32] } (fminnum:{ *:[f32] } (VOP3Mods:{ *:[f32] } f32:{ *:[f32] }:$src1, i32:{ *:[i32] }:$src1_mods), (VOP3Mods:{ *:[f32] } f32:{ *:[f32] }:$src0, i32:{ *:[i32] }:$src0_mods)), (VOP3Mods:{ *:[f32] } f32:{ *:[f32] }:$src2, i32:{ *:[i32] }:$src2_mods)), (fmaxnum:{ *:[f32] } (VOP3Mods:{ *:[f32] } f32:{ *:[f32] }:$src1, i32:{ *:[i32] }:$src1_mods), (VOP3Mods:{ *:[f32] } f32:{ *:[f32] }:$src0, i32:{ *:[i32] }:$src0_mods)))<<P:Predicate_fminnum_like_nnan>>  =>  (V_MED3_F32_e64:{ *:[f32] } ?:{ *:[i32] }:$src0_mods, ?:{ *:[f32] }:$src0, ?:{ *:[i32] }:$src1_mods, ?:{ *:[f32] }:$src1, ?:{ *:[i32] }:$src2_mods, ?:{ *:[f32] }:$src2, 0:{ *:[i1] }, 0:{ *:[i32] })
        GIR_BuildMI, /*InsnID*/0, /*Opcode*/GIMT_Encode2(AMDGPU::V_MED3_F32_e64),
        GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/0, // DstI[vdst]
        GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(1), /*SubOperand*/1, // src0_mods
        GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(1), /*SubOperand*/0, // src0
        GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/1, // src1_mods
        GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/0, // src1
        GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(2), /*SubOperand*/1, // src2_mods
        GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(2), /*SubOperand*/0, // src2
        GIR_AddImm8, /*InsnID*/0, /*Imm*/0,
        GIR_AddImm8, /*InsnID*/0, /*Imm*/0,
        GIR_ConstrainSelectedInstOperands, /*InsnID*/0,
        GIR_EraseFromParent, /*InsnID*/0,
        // GIR_Coverage, 10445,
        GIR_Done,
      // Label 4440: @285447
      GIM_Try, /*On fail goto*//*Label 4441*/ GIMT_Encode4(285587), // Rule ID 10382 //
        GIM_CheckRegBankForClass, /*MI*/0, /*Op*/0, /*RC*/GIMT_Encode2(AMDGPU::VGPR_32RegClassID),
        GIM_RecordInsn, /*DefineMI*/1, /*MI*/0, /*OpIdx*/1, // MIs[1]
        GIM_CheckOpcode, /*MI*/1, GIMT_Encode2(TargetOpcode::G_FMAXNUM_IEEE),
        GIM_CheckType, /*MI*/1, /*Op*/1, /*Type*/GILLT_s32,
        GIM_CheckType, /*MI*/1, /*Op*/2, /*Type*/GILLT_s32,
        GIM_RecordInsn, /*DefineMI*/2, /*MI*/1, /*OpIdx*/1, // MIs[2]
        GIM_CheckOpcode, /*MI*/2, GIMT_Encode2(TargetOpcode::G_FMINNUM),
        GIM_CheckType, /*MI*/2, /*Op*/1, /*Type*/GILLT_s32,
        GIM_CheckType, /*MI*/2, /*Op*/2, /*Type*/GILLT_s32,
        GIM_RecordInsn, /*DefineMI*/3, /*MI*/0, /*OpIdx*/2, // MIs[3]
        GIM_CheckOpcode, /*MI*/3, GIMT_Encode2(TargetOpcode::G_FMAXNUM_IEEE),
        // MIs[3] VOP3Mods:src0:src0_mods
        GIM_CheckIsSameOperand, /*MI*/3, /*OpIdx*/1, /*OtherMI*/2, /*OtherOpIdx*/1,
        // MIs[3] VOP3Mods:src1:src1_mods
        GIM_CheckIsSameOperand, /*MI*/3, /*OpIdx*/2, /*OtherMI*/2, /*OtherOpIdx*/2,
        GIM_CheckCxxInsnPredicate, /*MI*/0, /*FnId*/GIMT_Encode2(GICXXPred_MI_Predicate_fminnum_like_nnan),
        GIM_CheckIsSafeToFold, /*InsnID*/1,
        GIM_CheckIsSafeToFold, /*InsnID*/2,
        GIM_CheckIsSafeToFold, /*InsnID*/3,
        GIM_CheckComplexPattern, /*MI*/1, /*Op*/2, /*Renderer*/GIMT_Encode2(2), GIMT_Encode2(GICP_gi_vop3mods),
        GIM_CheckComplexPattern, /*MI*/2, /*Op*/1, /*Renderer*/GIMT_Encode2(0), GIMT_Encode2(GICP_gi_vop3mods),
        GIM_CheckComplexPattern, /*MI*/2, /*Op*/2, /*Renderer*/GIMT_Encode2(1), GIMT_Encode2(GICP_gi_vop3mods),
        // (fminnum:{ *:[f32] } (fmaxnum_ieee:{ *:[f32] } (fminnum:{ *:[f32] } (VOP3Mods:{ *:[f32] } f32:{ *:[f32] }:$src0, i32:{ *:[i32] }:$src0_mods), (VOP3Mods:{ *:[f32] } f32:{ *:[f32] }:$src1, i32:{ *:[i32] }:$src1_mods)), (VOP3Mods:{ *:[f32] } f32:{ *:[f32] }:$src2, i32:{ *:[i32] }:$src2_mods)), (fmaxnum_ieee:{ *:[f32] } (VOP3Mods:{ *:[f32] } f32:{ *:[f32] }:$src0, i32:{ *:[i32] }:$src0_mods), (VOP3Mods:{ *:[f32] } f32:{ *:[f32] }:$src1, i32:{ *:[i32] }:$src1_mods)))<<P:Predicate_fminnum_like_nnan>>  =>  (V_MED3_F32_e64:{ *:[f32] } ?:{ *:[i32] }:$src0_mods, ?:{ *:[f32] }:$src0, ?:{ *:[i32] }:$src1_mods, ?:{ *:[f32] }:$src1, ?:{ *:[i32] }:$src2_mods, ?:{ *:[f32] }:$src2, 0:{ *:[i1] }, 0:{ *:[i32] })
        GIR_BuildMI, /*InsnID*/0, /*Opcode*/GIMT_Encode2(AMDGPU::V_MED3_F32_e64),
        GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/0, // DstI[vdst]
        GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/1, // src0_mods
        GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/0, // src0
        GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(1), /*SubOperand*/1, // src1_mods
        GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(1), /*SubOperand*/0, // src1
        GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(2), /*SubOperand*/1, // src2_mods
        GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(2), /*SubOperand*/0, // src2
        GIR_AddImm8, /*InsnID*/0, /*Imm*/0,
        GIR_AddImm8, /*InsnID*/0, /*Imm*/0,
        GIR_ConstrainSelectedInstOperands, /*InsnID*/0,
        GIR_EraseFromParent, /*InsnID*/0,
        // GIR_Coverage, 10382,
        GIR_Done,
      // Label 4441: @285587
      GIM_Try, /*On fail goto*//*Label 4442*/ GIMT_Encode4(285727), // Rule ID 10383 //
        GIM_CheckRegBankForClass, /*MI*/0, /*Op*/0, /*RC*/GIMT_Encode2(AMDGPU::VGPR_32RegClassID),
        GIM_RecordInsn, /*DefineMI*/1, /*MI*/0, /*OpIdx*/1, // MIs[1]
        GIM_CheckOpcode, /*MI*/1, GIMT_Encode2(TargetOpcode::G_FMAXNUM_IEEE),
        GIM_CheckType, /*MI*/1, /*Op*/1, /*Type*/GILLT_s32,
        GIM_CheckType, /*MI*/1, /*Op*/2, /*Type*/GILLT_s32,
        GIM_RecordInsn, /*DefineMI*/2, /*MI*/1, /*OpIdx*/1, // MIs[2]
        GIM_CheckOpcode, /*MI*/2, GIMT_Encode2(TargetOpcode::G_FMINNUM),
        GIM_CheckType, /*MI*/2, /*Op*/1, /*Type*/GILLT_s32,
        GIM_CheckType, /*MI*/2, /*Op*/2, /*Type*/GILLT_s32,
        GIM_RecordInsn, /*DefineMI*/3, /*MI*/0, /*OpIdx*/2, // MIs[3]
        GIM_CheckOpcode, /*MI*/3, GIMT_Encode2(TargetOpcode::G_FMAXNUM_IEEE),
        // MIs[3] VOP3Mods:src1:src1_mods
        GIM_CheckIsSameOperand, /*MI*/3, /*OpIdx*/1, /*OtherMI*/2, /*OtherOpIdx*/2,
        // MIs[3] VOP3Mods:src0:src0_mods
        GIM_CheckIsSameOperand, /*MI*/3, /*OpIdx*/2, /*OtherMI*/2, /*OtherOpIdx*/1,
        GIM_CheckCxxInsnPredicate, /*MI*/0, /*FnId*/GIMT_Encode2(GICXXPred_MI_Predicate_fminnum_like_nnan),
        GIM_CheckIsSafeToFold, /*InsnID*/1,
        GIM_CheckIsSafeToFold, /*InsnID*/2,
        GIM_CheckIsSafeToFold, /*InsnID*/3,
        GIM_CheckComplexPattern, /*MI*/1, /*Op*/2, /*Renderer*/GIMT_Encode2(2), GIMT_Encode2(GICP_gi_vop3mods),
        GIM_CheckComplexPattern, /*MI*/2, /*Op*/1, /*Renderer*/GIMT_Encode2(0), GIMT_Encode2(GICP_gi_vop3mods),
        GIM_CheckComplexPattern, /*MI*/2, /*Op*/2, /*Renderer*/GIMT_Encode2(1), GIMT_Encode2(GICP_gi_vop3mods),
        // (fminnum:{ *:[f32] } (fmaxnum_ieee:{ *:[f32] } (fminnum:{ *:[f32] } (VOP3Mods:{ *:[f32] } f32:{ *:[f32] }:$src0, i32:{ *:[i32] }:$src0_mods), (VOP3Mods:{ *:[f32] } f32:{ *:[f32] }:$src1, i32:{ *:[i32] }:$src1_mods)), (VOP3Mods:{ *:[f32] } f32:{ *:[f32] }:$src2, i32:{ *:[i32] }:$src2_mods)), (fmaxnum_ieee:{ *:[f32] } (VOP3Mods:{ *:[f32] } f32:{ *:[f32] }:$src1, i32:{ *:[i32] }:$src1_mods), (VOP3Mods:{ *:[f32] } f32:{ *:[f32] }:$src0, i32:{ *:[i32] }:$src0_mods)))<<P:Predicate_fminnum_like_nnan>>  =>  (V_MED3_F32_e64:{ *:[f32] } ?:{ *:[i32] }:$src0_mods, ?:{ *:[f32] }:$src0, ?:{ *:[i32] }:$src1_mods, ?:{ *:[f32] }:$src1, ?:{ *:[i32] }:$src2_mods, ?:{ *:[f32] }:$src2, 0:{ *:[i1] }, 0:{ *:[i32] })
        GIR_BuildMI, /*InsnID*/0, /*Opcode*/GIMT_Encode2(AMDGPU::V_MED3_F32_e64),
        GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/0, // DstI[vdst]
        GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/1, // src0_mods
        GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/0, // src0
        GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(1), /*SubOperand*/1, // src1_mods
        GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(1), /*SubOperand*/0, // src1
        GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(2), /*SubOperand*/1, // src2_mods
        GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(2), /*SubOperand*/0, // src2
        GIR_AddImm8, /*InsnID*/0, /*Imm*/0,
        GIR_AddImm8, /*InsnID*/0, /*Imm*/0,
        GIR_ConstrainSelectedInstOperands, /*InsnID*/0,
        GIR_EraseFromParent, /*InsnID*/0,
        // GIR_Coverage, 10383,
        GIR_Done,
      // Label 4442: @285727
      GIM_Try, /*On fail goto*//*Label 4443*/ GIMT_Encode4(285867), // Rule ID 10384 //
        GIM_CheckRegBankForClass, /*MI*/0, /*Op*/0, /*RC*/GIMT_Encode2(AMDGPU::VGPR_32RegClassID),
        GIM_RecordInsn, /*DefineMI*/1, /*MI*/0, /*OpIdx*/1, // MIs[1]
        GIM_CheckOpcode, /*MI*/1, GIMT_Encode2(TargetOpcode::G_FMAXNUM_IEEE),
        GIM_CheckType, /*MI*/1, /*Op*/1, /*Type*/GILLT_s32,
        GIM_CheckType, /*MI*/1, /*Op*/2, /*Type*/GILLT_s32,
        GIM_RecordInsn, /*DefineMI*/2, /*MI*/1, /*OpIdx*/1, // MIs[2]
        GIM_CheckOpcode, /*MI*/2, GIMT_Encode2(TargetOpcode::G_FMINNUM),
        GIM_CheckType, /*MI*/2, /*Op*/1, /*Type*/GILLT_s32,
        GIM_CheckType, /*MI*/2, /*Op*/2, /*Type*/GILLT_s32,
        GIM_RecordInsn, /*DefineMI*/3, /*MI*/0, /*OpIdx*/2, // MIs[3]
        GIM_CheckOpcode, /*MI*/3, GIMT_Encode2(TargetOpcode::G_FMAXNUM_IEEE),
        // MIs[3] VOP3Mods:src0:src0_mods
        GIM_CheckIsSameOperand, /*MI*/3, /*OpIdx*/1, /*OtherMI*/2, /*OtherOpIdx*/2,
        // MIs[3] VOP3Mods:src1:src1_mods
        GIM_CheckIsSameOperand, /*MI*/3, /*OpIdx*/2, /*OtherMI*/2, /*OtherOpIdx*/1,
        GIM_CheckCxxInsnPredicate, /*MI*/0, /*FnId*/GIMT_Encode2(GICXXPred_MI_Predicate_fminnum_like_nnan),
        GIM_CheckIsSafeToFold, /*InsnID*/1,
        GIM_CheckIsSafeToFold, /*InsnID*/2,
        GIM_CheckIsSafeToFold, /*InsnID*/3,
        GIM_CheckComplexPattern, /*MI*/1, /*Op*/2, /*Renderer*/GIMT_Encode2(2), GIMT_Encode2(GICP_gi_vop3mods),
        GIM_CheckComplexPattern, /*MI*/2, /*Op*/1, /*Renderer*/GIMT_Encode2(0), GIMT_Encode2(GICP_gi_vop3mods),
        GIM_CheckComplexPattern, /*MI*/2, /*Op*/2, /*Renderer*/GIMT_Encode2(1), GIMT_Encode2(GICP_gi_vop3mods),
        // (fminnum:{ *:[f32] } (fmaxnum_ieee:{ *:[f32] } (fminnum:{ *:[f32] } (VOP3Mods:{ *:[f32] } f32:{ *:[f32] }:$src1, i32:{ *:[i32] }:$src1_mods), (VOP3Mods:{ *:[f32] } f32:{ *:[f32] }:$src0, i32:{ *:[i32] }:$src0_mods)), (VOP3Mods:{ *:[f32] } f32:{ *:[f32] }:$src2, i32:{ *:[i32] }:$src2_mods)), (fmaxnum_ieee:{ *:[f32] } (VOP3Mods:{ *:[f32] } f32:{ *:[f32] }:$src0, i32:{ *:[i32] }:$src0_mods), (VOP3Mods:{ *:[f32] } f32:{ *:[f32] }:$src1, i32:{ *:[i32] }:$src1_mods)))<<P:Predicate_fminnum_like_nnan>>  =>  (V_MED3_F32_e64:{ *:[f32] } ?:{ *:[i32] }:$src0_mods, ?:{ *:[f32] }:$src0, ?:{ *:[i32] }:$src1_mods, ?:{ *:[f32] }:$src1, ?:{ *:[i32] }:$src2_mods, ?:{ *:[f32] }:$src2, 0:{ *:[i1] }, 0:{ *:[i32] })
        GIR_BuildMI, /*InsnID*/0, /*Opcode*/GIMT_Encode2(AMDGPU::V_MED3_F32_e64),
        GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/0, // DstI[vdst]
        GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(1), /*SubOperand*/1, // src0_mods
        GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(1), /*SubOperand*/0, // src0
        GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/1, // src1_mods
        GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/0, // src1
        GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(2), /*SubOperand*/1, // src2_mods
        GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(2), /*SubOperand*/0, // src2
        GIR_AddImm8, /*InsnID*/0, /*Imm*/0,
        GIR_AddImm8, /*InsnID*/0, /*Imm*/0,
        GIR_ConstrainSelectedInstOperands, /*InsnID*/0,
        GIR_EraseFromParent, /*InsnID*/0,
        // GIR_Coverage, 10384,
        GIR_Done,
      // Label 4443: @285867
      GIM_Try, /*On fail goto*//*Label 4444*/ GIMT_Encode4(286007), // Rule ID 10385 //
        GIM_CheckRegBankForClass, /*MI*/0, /*Op*/0, /*RC*/GIMT_Encode2(AMDGPU::VGPR_32RegClassID),
        GIM_RecordInsn, /*DefineMI*/1, /*MI*/0, /*OpIdx*/1, // MIs[1]
        GIM_CheckOpcode, /*MI*/1, GIMT_Encode2(TargetOpcode::G_FMAXNUM_IEEE),
        GIM_CheckType, /*MI*/1, /*Op*/1, /*Type*/GILLT_s32,
        GIM_CheckType, /*MI*/1, /*Op*/2, /*Type*/GILLT_s32,
        GIM_RecordInsn, /*DefineMI*/2, /*MI*/1, /*OpIdx*/1, // MIs[2]
        GIM_CheckOpcode, /*MI*/2, GIMT_Encode2(TargetOpcode::G_FMINNUM),
        GIM_CheckType, /*MI*/2, /*Op*/1, /*Type*/GILLT_s32,
        GIM_CheckType, /*MI*/2, /*Op*/2, /*Type*/GILLT_s32,
        GIM_RecordInsn, /*DefineMI*/3, /*MI*/0, /*OpIdx*/2, // MIs[3]
        GIM_CheckOpcode, /*MI*/3, GIMT_Encode2(TargetOpcode::G_FMAXNUM_IEEE),
        // MIs[3] VOP3Mods:src1:src1_mods
        GIM_CheckIsSameOperand, /*MI*/3, /*OpIdx*/1, /*OtherMI*/2, /*OtherOpIdx*/1,
        // MIs[3] VOP3Mods:src0:src0_mods
        GIM_CheckIsSameOperand, /*MI*/3, /*OpIdx*/2, /*OtherMI*/2, /*OtherOpIdx*/2,
        GIM_CheckCxxInsnPredicate, /*MI*/0, /*FnId*/GIMT_Encode2(GICXXPred_MI_Predicate_fminnum_like_nnan),
        GIM_CheckIsSafeToFold, /*InsnID*/1,
        GIM_CheckIsSafeToFold, /*InsnID*/2,
        GIM_CheckIsSafeToFold, /*InsnID*/3,
        GIM_CheckComplexPattern, /*MI*/1, /*Op*/2, /*Renderer*/GIMT_Encode2(2), GIMT_Encode2(GICP_gi_vop3mods),
        GIM_CheckComplexPattern, /*MI*/2, /*Op*/1, /*Renderer*/GIMT_Encode2(0), GIMT_Encode2(GICP_gi_vop3mods),
        GIM_CheckComplexPattern, /*MI*/2, /*Op*/2, /*Renderer*/GIMT_Encode2(1), GIMT_Encode2(GICP_gi_vop3mods),
        // (fminnum:{ *:[f32] } (fmaxnum_ieee:{ *:[f32] } (fminnum:{ *:[f32] } (VOP3Mods:{ *:[f32] } f32:{ *:[f32] }:$src1, i32:{ *:[i32] }:$src1_mods), (VOP3Mods:{ *:[f32] } f32:{ *:[f32] }:$src0, i32:{ *:[i32] }:$src0_mods)), (VOP3Mods:{ *:[f32] } f32:{ *:[f32] }:$src2, i32:{ *:[i32] }:$src2_mods)), (fmaxnum_ieee:{ *:[f32] } (VOP3Mods:{ *:[f32] } f32:{ *:[f32] }:$src1, i32:{ *:[i32] }:$src1_mods), (VOP3Mods:{ *:[f32] } f32:{ *:[f32] }:$src0, i32:{ *:[i32] }:$src0_mods)))<<P:Predicate_fminnum_like_nnan>>  =>  (V_MED3_F32_e64:{ *:[f32] } ?:{ *:[i32] }:$src0_mods, ?:{ *:[f32] }:$src0, ?:{ *:[i32] }:$src1_mods, ?:{ *:[f32] }:$src1, ?:{ *:[i32] }:$src2_mods, ?:{ *:[f32] }:$src2, 0:{ *:[i1] }, 0:{ *:[i32] })
        GIR_BuildMI, /*InsnID*/0, /*Opcode*/GIMT_Encode2(AMDGPU::V_MED3_F32_e64),
        GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/0, // DstI[vdst]
        GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(1), /*SubOperand*/1, // src0_mods
        GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(1), /*SubOperand*/0, // src0
        GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/1, // src1_mods
        GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/0, // src1
        GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(2), /*SubOperand*/1, // src2_mods
        GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(2), /*SubOperand*/0, // src2
        GIR_AddImm8, /*InsnID*/0, /*Imm*/0,
        GIR_AddImm8, /*InsnID*/0, /*Imm*/0,
        GIR_ConstrainSelectedInstOperands, /*InsnID*/0,
        GIR_EraseFromParent, /*InsnID*/0,
        // GIR_Coverage, 10385,
        GIR_Done,
      // Label 4444: @286007
      GIM_Try, /*On fail goto*//*Label 4445*/ GIMT_Encode4(286147), // Rule ID 10427 //
        GIM_CheckRegBankForClass, /*MI*/0, /*Op*/0, /*RC*/GIMT_Encode2(AMDGPU::VGPR_32RegClassID),
        GIM_RecordInsn, /*DefineMI*/1, /*MI*/0, /*OpIdx*/1, // MIs[1]
        GIM_CheckOpcode, /*MI*/1, GIMT_Encode2(TargetOpcode::G_FMAXNUM_IEEE),
        GIM_CheckType, /*MI*/1, /*Op*/1, /*Type*/GILLT_s32,
        GIM_CheckType, /*MI*/1, /*Op*/2, /*Type*/GILLT_s32,
        GIM_RecordInsn, /*DefineMI*/2, /*MI*/1, /*OpIdx*/1, // MIs[2]
        GIM_CheckOpcode, /*MI*/2, GIMT_Encode2(TargetOpcode::G_FMINNUM_IEEE),
        GIM_CheckType, /*MI*/2, /*Op*/1, /*Type*/GILLT_s32,
        GIM_CheckType, /*MI*/2, /*Op*/2, /*Type*/GILLT_s32,
        GIM_RecordInsn, /*DefineMI*/3, /*MI*/0, /*OpIdx*/2, // MIs[3]
        GIM_CheckOpcode, /*MI*/3, GIMT_Encode2(TargetOpcode::G_FMAXNUM),
        // MIs[3] VOP3Mods:src0:src0_mods
        GIM_CheckIsSameOperand, /*MI*/3, /*OpIdx*/1, /*OtherMI*/2, /*OtherOpIdx*/1,
        // MIs[3] VOP3Mods:src1:src1_mods
        GIM_CheckIsSameOperand, /*MI*/3, /*OpIdx*/2, /*OtherMI*/2, /*OtherOpIdx*/2,
        GIM_CheckCxxInsnPredicate, /*MI*/0, /*FnId*/GIMT_Encode2(GICXXPred_MI_Predicate_fminnum_like_nnan),
        GIM_CheckIsSafeToFold, /*InsnID*/1,
        GIM_CheckIsSafeToFold, /*InsnID*/2,
        GIM_CheckIsSafeToFold, /*InsnID*/3,
        GIM_CheckComplexPattern, /*MI*/1, /*Op*/2, /*Renderer*/GIMT_Encode2(2), GIMT_Encode2(GICP_gi_vop3mods),
        GIM_CheckComplexPattern, /*MI*/2, /*Op*/1, /*Renderer*/GIMT_Encode2(0), GIMT_Encode2(GICP_gi_vop3mods),
        GIM_CheckComplexPattern, /*MI*/2, /*Op*/2, /*Renderer*/GIMT_Encode2(1), GIMT_Encode2(GICP_gi_vop3mods),
        // (fminnum:{ *:[f32] } (fmaxnum_ieee:{ *:[f32] } (fminnum_ieee:{ *:[f32] } (VOP3Mods:{ *:[f32] } f32:{ *:[f32] }:$src0, i32:{ *:[i32] }:$src0_mods), (VOP3Mods:{ *:[f32] } f32:{ *:[f32] }:$src1, i32:{ *:[i32] }:$src1_mods)), (VOP3Mods:{ *:[f32] } f32:{ *:[f32] }:$src2, i32:{ *:[i32] }:$src2_mods)), (fmaxnum:{ *:[f32] } (VOP3Mods:{ *:[f32] } f32:{ *:[f32] }:$src0, i32:{ *:[i32] }:$src0_mods), (VOP3Mods:{ *:[f32] } f32:{ *:[f32] }:$src1, i32:{ *:[i32] }:$src1_mods)))<<P:Predicate_fminnum_like_nnan>>  =>  (V_MED3_F32_e64:{ *:[f32] } ?:{ *:[i32] }:$src0_mods, ?:{ *:[f32] }:$src0, ?:{ *:[i32] }:$src1_mods, ?:{ *:[f32] }:$src1, ?:{ *:[i32] }:$src2_mods, ?:{ *:[f32] }:$src2, 0:{ *:[i1] }, 0:{ *:[i32] })
        GIR_BuildMI, /*InsnID*/0, /*Opcode*/GIMT_Encode2(AMDGPU::V_MED3_F32_e64),
        GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/0, // DstI[vdst]
        GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/1, // src0_mods
        GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/0, // src0
        GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(1), /*SubOperand*/1, // src1_mods
        GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(1), /*SubOperand*/0, // src1
        GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(2), /*SubOperand*/1, // src2_mods
        GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(2), /*SubOperand*/0, // src2
        GIR_AddImm8, /*InsnID*/0, /*Imm*/0,
        GIR_AddImm8, /*InsnID*/0, /*Imm*/0,
        GIR_ConstrainSelectedInstOperands, /*InsnID*/0,
        GIR_EraseFromParent, /*InsnID*/0,
        // GIR_Coverage, 10427,
        GIR_Done,
      // Label 4445: @286147
      GIM_Try, /*On fail goto*//*Label 4446*/ GIMT_Encode4(286287), // Rule ID 10428 //
        GIM_CheckRegBankForClass, /*MI*/0, /*Op*/0, /*RC*/GIMT_Encode2(AMDGPU::VGPR_32RegClassID),
        GIM_RecordInsn, /*DefineMI*/1, /*MI*/0, /*OpIdx*/1, // MIs[1]
        GIM_CheckOpcode, /*MI*/1, GIMT_Encode2(TargetOpcode::G_FMAXNUM_IEEE),
        GIM_CheckType, /*MI*/1, /*Op*/1, /*Type*/GILLT_s32,
        GIM_CheckType, /*MI*/1, /*Op*/2, /*Type*/GILLT_s32,
        GIM_RecordInsn, /*DefineMI*/2, /*MI*/1, /*OpIdx*/1, // MIs[2]
        GIM_CheckOpcode, /*MI*/2, GIMT_Encode2(TargetOpcode::G_FMINNUM_IEEE),
        GIM_CheckType, /*MI*/2, /*Op*/1, /*Type*/GILLT_s32,
        GIM_CheckType, /*MI*/2, /*Op*/2, /*Type*/GILLT_s32,
        GIM_RecordInsn, /*DefineMI*/3, /*MI*/0, /*OpIdx*/2, // MIs[3]
        GIM_CheckOpcode, /*MI*/3, GIMT_Encode2(TargetOpcode::G_FMAXNUM),
        // MIs[3] VOP3Mods:src1:src1_mods
        GIM_CheckIsSameOperand, /*MI*/3, /*OpIdx*/1, /*OtherMI*/2, /*OtherOpIdx*/2,
        // MIs[3] VOP3Mods:src0:src0_mods
        GIM_CheckIsSameOperand, /*MI*/3, /*OpIdx*/2, /*OtherMI*/2, /*OtherOpIdx*/1,
        GIM_CheckCxxInsnPredicate, /*MI*/0, /*FnId*/GIMT_Encode2(GICXXPred_MI_Predicate_fminnum_like_nnan),
        GIM_CheckIsSafeToFold, /*InsnID*/1,
        GIM_CheckIsSafeToFold, /*InsnID*/2,
        GIM_CheckIsSafeToFold, /*InsnID*/3,
        GIM_CheckComplexPattern, /*MI*/1, /*Op*/2, /*Renderer*/GIMT_Encode2(2), GIMT_Encode2(GICP_gi_vop3mods),
        GIM_CheckComplexPattern, /*MI*/2, /*Op*/1, /*Renderer*/GIMT_Encode2(0), GIMT_Encode2(GICP_gi_vop3mods),
        GIM_CheckComplexPattern, /*MI*/2, /*Op*/2, /*Renderer*/GIMT_Encode2(1), GIMT_Encode2(GICP_gi_vop3mods),
        // (fminnum:{ *:[f32] } (fmaxnum_ieee:{ *:[f32] } (fminnum_ieee:{ *:[f32] } (VOP3Mods:{ *:[f32] } f32:{ *:[f32] }:$src0, i32:{ *:[i32] }:$src0_mods), (VOP3Mods:{ *:[f32] } f32:{ *:[f32] }:$src1, i32:{ *:[i32] }:$src1_mods)), (VOP3Mods:{ *:[f32] } f32:{ *:[f32] }:$src2, i32:{ *:[i32] }:$src2_mods)), (fmaxnum:{ *:[f32] } (VOP3Mods:{ *:[f32] } f32:{ *:[f32] }:$src1, i32:{ *:[i32] }:$src1_mods), (VOP3Mods:{ *:[f32] } f32:{ *:[f32] }:$src0, i32:{ *:[i32] }:$src0_mods)))<<P:Predicate_fminnum_like_nnan>>  =>  (V_MED3_F32_e64:{ *:[f32] } ?:{ *:[i32] }:$src0_mods, ?:{ *:[f32] }:$src0, ?:{ *:[i32] }:$src1_mods, ?:{ *:[f32] }:$src1, ?:{ *:[i32] }:$src2_mods, ?:{ *:[f32] }:$src2, 0:{ *:[i1] }, 0:{ *:[i32] })
        GIR_BuildMI, /*InsnID*/0, /*Opcode*/GIMT_Encode2(AMDGPU::V_MED3_F32_e64),
        GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/0, // DstI[vdst]
        GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/1, // src0_mods
        GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/0, // src0
        GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(1), /*SubOperand*/1, // src1_mods
        GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(1), /*SubOperand*/0, // src1
        GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(2), /*SubOperand*/1, // src2_mods
        GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(2), /*SubOperand*/0, // src2
        GIR_AddImm8, /*InsnID*/0, /*Imm*/0,
        GIR_AddImm8, /*InsnID*/0, /*Imm*/0,
        GIR_ConstrainSelectedInstOperands, /*InsnID*/0,
        GIR_EraseFromParent, /*InsnID*/0,
        // GIR_Coverage, 10428,
        GIR_Done,
      // Label 4446: @286287
      GIM_Try, /*On fail goto*//*Label 4447*/ GIMT_Encode4(286427), // Rule ID 10429 //
        GIM_CheckRegBankForClass, /*MI*/0, /*Op*/0, /*RC*/GIMT_Encode2(AMDGPU::VGPR_32RegClassID),
        GIM_RecordInsn, /*DefineMI*/1, /*MI*/0, /*OpIdx*/1, // MIs[1]
        GIM_CheckOpcode, /*MI*/1, GIMT_Encode2(TargetOpcode::G_FMAXNUM_IEEE),
        GIM_CheckType, /*MI*/1, /*Op*/1, /*Type*/GILLT_s32,
        GIM_CheckType, /*MI*/1, /*Op*/2, /*Type*/GILLT_s32,
        GIM_RecordInsn, /*DefineMI*/2, /*MI*/1, /*OpIdx*/1, // MIs[2]
        GIM_CheckOpcode, /*MI*/2, GIMT_Encode2(TargetOpcode::G_FMINNUM_IEEE),
        GIM_CheckType, /*MI*/2, /*Op*/1, /*Type*/GILLT_s32,
        GIM_CheckType, /*MI*/2, /*Op*/2, /*Type*/GILLT_s32,
        GIM_RecordInsn, /*DefineMI*/3, /*MI*/0, /*OpIdx*/2, // MIs[3]
        GIM_CheckOpcode, /*MI*/3, GIMT_Encode2(TargetOpcode::G_FMAXNUM),
        // MIs[3] VOP3Mods:src0:src0_mods
        GIM_CheckIsSameOperand, /*MI*/3, /*OpIdx*/1, /*OtherMI*/2, /*OtherOpIdx*/2,
        // MIs[3] VOP3Mods:src1:src1_mods
        GIM_CheckIsSameOperand, /*MI*/3, /*OpIdx*/2, /*OtherMI*/2, /*OtherOpIdx*/1,
        GIM_CheckCxxInsnPredicate, /*MI*/0, /*FnId*/GIMT_Encode2(GICXXPred_MI_Predicate_fminnum_like_nnan),
        GIM_CheckIsSafeToFold, /*InsnID*/1,
        GIM_CheckIsSafeToFold, /*InsnID*/2,
        GIM_CheckIsSafeToFold, /*InsnID*/3,
        GIM_CheckComplexPattern, /*MI*/1, /*Op*/2, /*Renderer*/GIMT_Encode2(2), GIMT_Encode2(GICP_gi_vop3mods),
        GIM_CheckComplexPattern, /*MI*/2, /*Op*/1, /*Renderer*/GIMT_Encode2(0), GIMT_Encode2(GICP_gi_vop3mods),
        GIM_CheckComplexPattern, /*MI*/2, /*Op*/2, /*Renderer*/GIMT_Encode2(1), GIMT_Encode2(GICP_gi_vop3mods),
        // (fminnum:{ *:[f32] } (fmaxnum_ieee:{ *:[f32] } (fminnum_ieee:{ *:[f32] } (VOP3Mods:{ *:[f32] } f32:{ *:[f32] }:$src1, i32:{ *:[i32] }:$src1_mods), (VOP3Mods:{ *:[f32] } f32:{ *:[f32] }:$src0, i32:{ *:[i32] }:$src0_mods)), (VOP3Mods:{ *:[f32] } f32:{ *:[f32] }:$src2, i32:{ *:[i32] }:$src2_mods)), (fmaxnum:{ *:[f32] } (VOP3Mods:{ *:[f32] } f32:{ *:[f32] }:$src0, i32:{ *:[i32] }:$src0_mods), (VOP3Mods:{ *:[f32] } f32:{ *:[f32] }:$src1, i32:{ *:[i32] }:$src1_mods)))<<P:Predicate_fminnum_like_nnan>>  =>  (V_MED3_F32_e64:{ *:[f32] } ?:{ *:[i32] }:$src0_mods, ?:{ *:[f32] }:$src0, ?:{ *:[i32] }:$src1_mods, ?:{ *:[f32] }:$src1, ?:{ *:[i32] }:$src2_mods, ?:{ *:[f32] }:$src2, 0:{ *:[i1] }, 0:{ *:[i32] })
        GIR_BuildMI, /*InsnID*/0, /*Opcode*/GIMT_Encode2(AMDGPU::V_MED3_F32_e64),
        GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/0, // DstI[vdst]
        GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(1), /*SubOperand*/1, // src0_mods
        GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(1), /*SubOperand*/0, // src0
        GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/1, // src1_mods
        GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/0, // src1
        GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(2), /*SubOperand*/1, // src2_mods
        GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(2), /*SubOperand*/0, // src2
        GIR_AddImm8, /*InsnID*/0, /*Imm*/0,
        GIR_AddImm8, /*InsnID*/0, /*Imm*/0,
        GIR_ConstrainSelectedInstOperands, /*InsnID*/0,
        GIR_EraseFromParent, /*InsnID*/0,
        // GIR_Coverage, 10429,
        GIR_Done,
      // Label 4447: @286427
      GIM_Try, /*On fail goto*//*Label 4448*/ GIMT_Encode4(286567), // Rule ID 10430 //
        GIM_CheckRegBankForClass, /*MI*/0, /*Op*/0, /*RC*/GIMT_Encode2(AMDGPU::VGPR_32RegClassID),
        GIM_RecordInsn, /*DefineMI*/1, /*MI*/0, /*OpIdx*/1, // MIs[1]
        GIM_CheckOpcode, /*MI*/1, GIMT_Encode2(TargetOpcode::G_FMAXNUM_IEEE),
        GIM_CheckType, /*MI*/1, /*Op*/1, /*Type*/GILLT_s32,
        GIM_CheckType, /*MI*/1, /*Op*/2, /*Type*/GILLT_s32,
        GIM_RecordInsn, /*DefineMI*/2, /*MI*/1, /*OpIdx*/1, // MIs[2]
        GIM_CheckOpcode, /*MI*/2, GIMT_Encode2(TargetOpcode::G_FMINNUM_IEEE),
        GIM_CheckType, /*MI*/2, /*Op*/1, /*Type*/GILLT_s32,
        GIM_CheckType, /*MI*/2, /*Op*/2, /*Type*/GILLT_s32,
        GIM_RecordInsn, /*DefineMI*/3, /*MI*/0, /*OpIdx*/2, // MIs[3]
        GIM_CheckOpcode, /*MI*/3, GIMT_Encode2(TargetOpcode::G_FMAXNUM),
        // MIs[3] VOP3Mods:src1:src1_mods
        GIM_CheckIsSameOperand, /*MI*/3, /*OpIdx*/1, /*OtherMI*/2, /*OtherOpIdx*/1,
        // MIs[3] VOP3Mods:src0:src0_mods
        GIM_CheckIsSameOperand, /*MI*/3, /*OpIdx*/2, /*OtherMI*/2, /*OtherOpIdx*/2,
        GIM_CheckCxxInsnPredicate, /*MI*/0, /*FnId*/GIMT_Encode2(GICXXPred_MI_Predicate_fminnum_like_nnan),
        GIM_CheckIsSafeToFold, /*InsnID*/1,
        GIM_CheckIsSafeToFold, /*InsnID*/2,
        GIM_CheckIsSafeToFold, /*InsnID*/3,
        GIM_CheckComplexPattern, /*MI*/1, /*Op*/2, /*Renderer*/GIMT_Encode2(2), GIMT_Encode2(GICP_gi_vop3mods),
        GIM_CheckComplexPattern, /*MI*/2, /*Op*/1, /*Renderer*/GIMT_Encode2(0), GIMT_Encode2(GICP_gi_vop3mods),
        GIM_CheckComplexPattern, /*MI*/2, /*Op*/2, /*Renderer*/GIMT_Encode2(1), GIMT_Encode2(GICP_gi_vop3mods),
        // (fminnum:{ *:[f32] } (fmaxnum_ieee:{ *:[f32] } (fminnum_ieee:{ *:[f32] } (VOP3Mods:{ *:[f32] } f32:{ *:[f32] }:$src1, i32:{ *:[i32] }:$src1_mods), (VOP3Mods:{ *:[f32] } f32:{ *:[f32] }:$src0, i32:{ *:[i32] }:$src0_mods)), (VOP3Mods:{ *:[f32] } f32:{ *:[f32] }:$src2, i32:{ *:[i32] }:$src2_mods)), (fmaxnum:{ *:[f32] } (VOP3Mods:{ *:[f32] } f32:{ *:[f32] }:$src1, i32:{ *:[i32] }:$src1_mods), (VOP3Mods:{ *:[f32] } f32:{ *:[f32] }:$src0, i32:{ *:[i32] }:$src0_mods)))<<P:Predicate_fminnum_like_nnan>>  =>  (V_MED3_F32_e64:{ *:[f32] } ?:{ *:[i32] }:$src0_mods, ?:{ *:[f32] }:$src0, ?:{ *:[i32] }:$src1_mods, ?:{ *:[f32] }:$src1, ?:{ *:[i32] }:$src2_mods, ?:{ *:[f32] }:$src2, 0:{ *:[i1] }, 0:{ *:[i32] })
        GIR_BuildMI, /*InsnID*/0, /*Opcode*/GIMT_Encode2(AMDGPU::V_MED3_F32_e64),
        GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/0, // DstI[vdst]
        GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(1), /*SubOperand*/1, // src0_mods
        GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(1), /*SubOperand*/0, // src0
        GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/1, // src1_mods
        GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/0, // src1
        GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(2), /*SubOperand*/1, // src2_mods
        GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(2), /*SubOperand*/0, // src2
        GIR_AddImm8, /*InsnID*/0, /*Imm*/0,
        GIR_AddImm8, /*InsnID*/0, /*Imm*/0,
        GIR_ConstrainSelectedInstOperands, /*InsnID*/0,
        GIR_EraseFromParent, /*InsnID*/0,
        // GIR_Coverage, 10430,
        GIR_Done,
      // Label 4448: @286567
      GIM_Try, /*On fail goto*//*Label 4449*/ GIMT_Encode4(286707), // Rule ID 10367 //
        GIM_CheckRegBankForClass, /*MI*/0, /*Op*/0, /*RC*/GIMT_Encode2(AMDGPU::VGPR_32RegClassID),
        GIM_RecordInsn, /*DefineMI*/1, /*MI*/0, /*OpIdx*/1, // MIs[1]
        GIM_CheckOpcode, /*MI*/1, GIMT_Encode2(TargetOpcode::G_FMAXNUM_IEEE),
        GIM_CheckType, /*MI*/1, /*Op*/1, /*Type*/GILLT_s32,
        GIM_CheckType, /*MI*/1, /*Op*/2, /*Type*/GILLT_s32,
        GIM_RecordInsn, /*DefineMI*/2, /*MI*/1, /*OpIdx*/1, // MIs[2]
        GIM_CheckOpcode, /*MI*/2, GIMT_Encode2(TargetOpcode::G_FMINNUM_IEEE),
        GIM_CheckType, /*MI*/2, /*Op*/1, /*Type*/GILLT_s32,
        GIM_CheckType, /*MI*/2, /*Op*/2, /*Type*/GILLT_s32,
        GIM_RecordInsn, /*DefineMI*/3, /*MI*/0, /*OpIdx*/2, // MIs[3]
        GIM_CheckOpcode, /*MI*/3, GIMT_Encode2(TargetOpcode::G_FMAXNUM_IEEE),
        // MIs[3] VOP3Mods:src0:src0_mods
        GIM_CheckIsSameOperand, /*MI*/3, /*OpIdx*/1, /*OtherMI*/2, /*OtherOpIdx*/1,
        // MIs[3] VOP3Mods:src1:src1_mods
        GIM_CheckIsSameOperand, /*MI*/3, /*OpIdx*/2, /*OtherMI*/2, /*OtherOpIdx*/2,
        GIM_CheckCxxInsnPredicate, /*MI*/0, /*FnId*/GIMT_Encode2(GICXXPred_MI_Predicate_fminnum_like_nnan),
        GIM_CheckIsSafeToFold, /*InsnID*/1,
        GIM_CheckIsSafeToFold, /*InsnID*/2,
        GIM_CheckIsSafeToFold, /*InsnID*/3,
        GIM_CheckComplexPattern, /*MI*/1, /*Op*/2, /*Renderer*/GIMT_Encode2(2), GIMT_Encode2(GICP_gi_vop3mods),
        GIM_CheckComplexPattern, /*MI*/2, /*Op*/1, /*Renderer*/GIMT_Encode2(0), GIMT_Encode2(GICP_gi_vop3mods),
        GIM_CheckComplexPattern, /*MI*/2, /*Op*/2, /*Renderer*/GIMT_Encode2(1), GIMT_Encode2(GICP_gi_vop3mods),
        // (fminnum:{ *:[f32] } (fmaxnum_ieee:{ *:[f32] } (fminnum_ieee:{ *:[f32] } (VOP3Mods:{ *:[f32] } f32:{ *:[f32] }:$src0, i32:{ *:[i32] }:$src0_mods), (VOP3Mods:{ *:[f32] } f32:{ *:[f32] }:$src1, i32:{ *:[i32] }:$src1_mods)), (VOP3Mods:{ *:[f32] } f32:{ *:[f32] }:$src2, i32:{ *:[i32] }:$src2_mods)), (fmaxnum_ieee:{ *:[f32] } (VOP3Mods:{ *:[f32] } f32:{ *:[f32] }:$src0, i32:{ *:[i32] }:$src0_mods), (VOP3Mods:{ *:[f32] } f32:{ *:[f32] }:$src1, i32:{ *:[i32] }:$src1_mods)))<<P:Predicate_fminnum_like_nnan>>  =>  (V_MED3_F32_e64:{ *:[f32] } ?:{ *:[i32] }:$src0_mods, ?:{ *:[f32] }:$src0, ?:{ *:[i32] }:$src1_mods, ?:{ *:[f32] }:$src1, ?:{ *:[i32] }:$src2_mods, ?:{ *:[f32] }:$src2, 0:{ *:[i1] }, 0:{ *:[i32] })
        GIR_BuildMI, /*InsnID*/0, /*Opcode*/GIMT_Encode2(AMDGPU::V_MED3_F32_e64),
        GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/0, // DstI[vdst]
        GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/1, // src0_mods
        GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/0, // src0
        GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(1), /*SubOperand*/1, // src1_mods
        GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(1), /*SubOperand*/0, // src1
        GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(2), /*SubOperand*/1, // src2_mods
        GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(2), /*SubOperand*/0, // src2
        GIR_AddImm8, /*InsnID*/0, /*Imm*/0,
        GIR_AddImm8, /*InsnID*/0, /*Imm*/0,
        GIR_ConstrainSelectedInstOperands, /*InsnID*/0,
        GIR_EraseFromParent, /*InsnID*/0,
        // GIR_Coverage, 10367,
        GIR_Done,
      // Label 4449: @286707
      GIM_Try, /*On fail goto*//*Label 4450*/ GIMT_Encode4(286847), // Rule ID 10368 //
        GIM_CheckRegBankForClass, /*MI*/0, /*Op*/0, /*RC*/GIMT_Encode2(AMDGPU::VGPR_32RegClassID),
        GIM_RecordInsn, /*DefineMI*/1, /*MI*/0, /*OpIdx*/1, // MIs[1]
        GIM_CheckOpcode, /*MI*/1, GIMT_Encode2(TargetOpcode::G_FMAXNUM_IEEE),
        GIM_CheckType, /*MI*/1, /*Op*/1, /*Type*/GILLT_s32,
        GIM_CheckType, /*MI*/1, /*Op*/2, /*Type*/GILLT_s32,
        GIM_RecordInsn, /*DefineMI*/2, /*MI*/1, /*OpIdx*/1, // MIs[2]
        GIM_CheckOpcode, /*MI*/2, GIMT_Encode2(TargetOpcode::G_FMINNUM_IEEE),
        GIM_CheckType, /*MI*/2, /*Op*/1, /*Type*/GILLT_s32,
        GIM_CheckType, /*MI*/2, /*Op*/2, /*Type*/GILLT_s32,
        GIM_RecordInsn, /*DefineMI*/3, /*MI*/0, /*OpIdx*/2, // MIs[3]
        GIM_CheckOpcode, /*MI*/3, GIMT_Encode2(TargetOpcode::G_FMAXNUM_IEEE),
        // MIs[3] VOP3Mods:src1:src1_mods
        GIM_CheckIsSameOperand, /*MI*/3, /*OpIdx*/1, /*OtherMI*/2, /*OtherOpIdx*/2,
        // MIs[3] VOP3Mods:src0:src0_mods
        GIM_CheckIsSameOperand, /*MI*/3, /*OpIdx*/2, /*OtherMI*/2, /*OtherOpIdx*/1,
        GIM_CheckCxxInsnPredicate, /*MI*/0, /*FnId*/GIMT_Encode2(GICXXPred_MI_Predicate_fminnum_like_nnan),
        GIM_CheckIsSafeToFold, /*InsnID*/1,
        GIM_CheckIsSafeToFold, /*InsnID*/2,
        GIM_CheckIsSafeToFold, /*InsnID*/3,
        GIM_CheckComplexPattern, /*MI*/1, /*Op*/2, /*Renderer*/GIMT_Encode2(2), GIMT_Encode2(GICP_gi_vop3mods),
        GIM_CheckComplexPattern, /*MI*/2, /*Op*/1, /*Renderer*/GIMT_Encode2(0), GIMT_Encode2(GICP_gi_vop3mods),
        GIM_CheckComplexPattern, /*MI*/2, /*Op*/2, /*Renderer*/GIMT_Encode2(1), GIMT_Encode2(GICP_gi_vop3mods),
        // (fminnum:{ *:[f32] } (fmaxnum_ieee:{ *:[f32] } (fminnum_ieee:{ *:[f32] } (VOP3Mods:{ *:[f32] } f32:{ *:[f32] }:$src0, i32:{ *:[i32] }:$src0_mods), (VOP3Mods:{ *:[f32] } f32:{ *:[f32] }:$src1, i32:{ *:[i32] }:$src1_mods)), (VOP3Mods:{ *:[f32] } f32:{ *:[f32] }:$src2, i32:{ *:[i32] }:$src2_mods)), (fmaxnum_ieee:{ *:[f32] } (VOP3Mods:{ *:[f32] } f32:{ *:[f32] }:$src1, i32:{ *:[i32] }:$src1_mods), (VOP3Mods:{ *:[f32] } f32:{ *:[f32] }:$src0, i32:{ *:[i32] }:$src0_mods)))<<P:Predicate_fminnum_like_nnan>>  =>  (V_MED3_F32_e64:{ *:[f32] } ?:{ *:[i32] }:$src0_mods, ?:{ *:[f32] }:$src0, ?:{ *:[i32] }:$src1_mods, ?:{ *:[f32] }:$src1, ?:{ *:[i32] }:$src2_mods, ?:{ *:[f32] }:$src2, 0:{ *:[i1] }, 0:{ *:[i32] })
        GIR_BuildMI, /*InsnID*/0, /*Opcode*/GIMT_Encode2(AMDGPU::V_MED3_F32_e64),
        GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/0, // DstI[vdst]
        GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/1, // src0_mods
        GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/0, // src0
        GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(1), /*SubOperand*/1, // src1_mods
        GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(1), /*SubOperand*/0, // src1
        GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(2), /*SubOperand*/1, // src2_mods
        GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(2), /*SubOperand*/0, // src2
        GIR_AddImm8, /*InsnID*/0, /*Imm*/0,
        GIR_AddImm8, /*InsnID*/0, /*Imm*/0,
        GIR_ConstrainSelectedInstOperands, /*InsnID*/0,
        GIR_EraseFromParent, /*InsnID*/0,
        // GIR_Coverage, 10368,
        GIR_Done,
      // Label 4450: @286847
      GIM_Try, /*On fail goto*//*Label 4451*/ GIMT_Encode4(286987), // Rule ID 10369 //
        GIM_CheckRegBankForClass, /*MI*/0, /*Op*/0, /*RC*/GIMT_Encode2(AMDGPU::VGPR_32RegClassID),
        GIM_RecordInsn, /*DefineMI*/1, /*MI*/0, /*OpIdx*/1, // MIs[1]
        GIM_CheckOpcode, /*MI*/1, GIMT_Encode2(TargetOpcode::G_FMAXNUM_IEEE),
        GIM_CheckType, /*MI*/1, /*Op*/1, /*Type*/GILLT_s32,
        GIM_CheckType, /*MI*/1, /*Op*/2, /*Type*/GILLT_s32,
        GIM_RecordInsn, /*DefineMI*/2, /*MI*/1, /*OpIdx*/1, // MIs[2]
        GIM_CheckOpcode, /*MI*/2, GIMT_Encode2(TargetOpcode::G_FMINNUM_IEEE),
        GIM_CheckType, /*MI*/2, /*Op*/1, /*Type*/GILLT_s32,
        GIM_CheckType, /*MI*/2, /*Op*/2, /*Type*/GILLT_s32,
        GIM_RecordInsn, /*DefineMI*/3, /*MI*/0, /*OpIdx*/2, // MIs[3]
        GIM_CheckOpcode, /*MI*/3, GIMT_Encode2(TargetOpcode::G_FMAXNUM_IEEE),
        // MIs[3] VOP3Mods:src0:src0_mods
        GIM_CheckIsSameOperand, /*MI*/3, /*OpIdx*/1, /*OtherMI*/2, /*OtherOpIdx*/2,
        // MIs[3] VOP3Mods:src1:src1_mods
        GIM_CheckIsSameOperand, /*MI*/3, /*OpIdx*/2, /*OtherMI*/2, /*OtherOpIdx*/1,
        GIM_CheckCxxInsnPredicate, /*MI*/0, /*FnId*/GIMT_Encode2(GICXXPred_MI_Predicate_fminnum_like_nnan),
        GIM_CheckIsSafeToFold, /*InsnID*/1,
        GIM_CheckIsSafeToFold, /*InsnID*/2,
        GIM_CheckIsSafeToFold, /*InsnID*/3,
        GIM_CheckComplexPattern, /*MI*/1, /*Op*/2, /*Renderer*/GIMT_Encode2(2), GIMT_Encode2(GICP_gi_vop3mods),
        GIM_CheckComplexPattern, /*MI*/2, /*Op*/1, /*Renderer*/GIMT_Encode2(0), GIMT_Encode2(GICP_gi_vop3mods),
        GIM_CheckComplexPattern, /*MI*/2, /*Op*/2, /*Renderer*/GIMT_Encode2(1), GIMT_Encode2(GICP_gi_vop3mods),
        // (fminnum:{ *:[f32] } (fmaxnum_ieee:{ *:[f32] } (fminnum_ieee:{ *:[f32] } (VOP3Mods:{ *:[f32] } f32:{ *:[f32] }:$src1, i32:{ *:[i32] }:$src1_mods), (VOP3Mods:{ *:[f32] } f32:{ *:[f32] }:$src0, i32:{ *:[i32] }:$src0_mods)), (VOP3Mods:{ *:[f32] } f32:{ *:[f32] }:$src2, i32:{ *:[i32] }:$src2_mods)), (fmaxnum_ieee:{ *:[f32] } (VOP3Mods:{ *:[f32] } f32:{ *:[f32] }:$src0, i32:{ *:[i32] }:$src0_mods), (VOP3Mods:{ *:[f32] } f32:{ *:[f32] }:$src1, i32:{ *:[i32] }:$src1_mods)))<<P:Predicate_fminnum_like_nnan>>  =>  (V_MED3_F32_e64:{ *:[f32] } ?:{ *:[i32] }:$src0_mods, ?:{ *:[f32] }:$src0, ?:{ *:[i32] }:$src1_mods, ?:{ *:[f32] }:$src1, ?:{ *:[i32] }:$src2_mods, ?:{ *:[f32] }:$src2, 0:{ *:[i1] }, 0:{ *:[i32] })
        GIR_BuildMI, /*InsnID*/0, /*Opcode*/GIMT_Encode2(AMDGPU::V_MED3_F32_e64),
        GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/0, // DstI[vdst]
        GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(1), /*SubOperand*/1, // src0_mods
        GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(1), /*SubOperand*/0, // src0
        GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/1, // src1_mods
        GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/0, // src1
        GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(2), /*SubOperand*/1, // src2_mods
        GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(2), /*SubOperand*/0, // src2
        GIR_AddImm8, /*InsnID*/0, /*Imm*/0,
        GIR_AddImm8, /*InsnID*/0, /*Imm*/0,
        GIR_ConstrainSelectedInstOperands, /*InsnID*/0,
        GIR_EraseFromParent, /*InsnID*/0,
        // GIR_Coverage, 10369,
        GIR_Done,
      // Label 4451: @286987
      GIM_Try, /*On fail goto*//*Label 4452*/ GIMT_Encode4(287127), // Rule ID 10370 //
        GIM_CheckRegBankForClass, /*MI*/0, /*Op*/0, /*RC*/GIMT_Encode2(AMDGPU::VGPR_32RegClassID),
        GIM_RecordInsn, /*DefineMI*/1, /*MI*/0, /*OpIdx*/1, // MIs[1]
        GIM_CheckOpcode, /*MI*/1, GIMT_Encode2(TargetOpcode::G_FMAXNUM_IEEE),
        GIM_CheckType, /*MI*/1, /*Op*/1, /*Type*/GILLT_s32,
        GIM_CheckType, /*MI*/1, /*Op*/2, /*Type*/GILLT_s32,
        GIM_RecordInsn, /*DefineMI*/2, /*MI*/1, /*OpIdx*/1, // MIs[2]
        GIM_CheckOpcode, /*MI*/2, GIMT_Encode2(TargetOpcode::G_FMINNUM_IEEE),
        GIM_CheckType, /*MI*/2, /*Op*/1, /*Type*/GILLT_s32,
        GIM_CheckType, /*MI*/2, /*Op*/2, /*Type*/GILLT_s32,
        GIM_RecordInsn, /*DefineMI*/3, /*MI*/0, /*OpIdx*/2, // MIs[3]
        GIM_CheckOpcode, /*MI*/3, GIMT_Encode2(TargetOpcode::G_FMAXNUM_IEEE),
        // MIs[3] VOP3Mods:src1:src1_mods
        GIM_CheckIsSameOperand, /*MI*/3, /*OpIdx*/1, /*OtherMI*/2, /*OtherOpIdx*/1,
        // MIs[3] VOP3Mods:src0:src0_mods
        GIM_CheckIsSameOperand, /*MI*/3, /*OpIdx*/2, /*OtherMI*/2, /*OtherOpIdx*/2,
        GIM_CheckCxxInsnPredicate, /*MI*/0, /*FnId*/GIMT_Encode2(GICXXPred_MI_Predicate_fminnum_like_nnan),
        GIM_CheckIsSafeToFold, /*InsnID*/1,
        GIM_CheckIsSafeToFold, /*InsnID*/2,
        GIM_CheckIsSafeToFold, /*InsnID*/3,
        GIM_CheckComplexPattern, /*MI*/1, /*Op*/2, /*Renderer*/GIMT_Encode2(2), GIMT_Encode2(GICP_gi_vop3mods),
        GIM_CheckComplexPattern, /*MI*/2, /*Op*/1, /*Renderer*/GIMT_Encode2(0), GIMT_Encode2(GICP_gi_vop3mods),
        GIM_CheckComplexPattern, /*MI*/2, /*Op*/2, /*Renderer*/GIMT_Encode2(1), GIMT_Encode2(GICP_gi_vop3mods),
        // (fminnum:{ *:[f32] } (fmaxnum_ieee:{ *:[f32] } (fminnum_ieee:{ *:[f32] } (VOP3Mods:{ *:[f32] } f32:{ *:[f32] }:$src1, i32:{ *:[i32] }:$src1_mods), (VOP3Mods:{ *:[f32] } f32:{ *:[f32] }:$src0, i32:{ *:[i32] }:$src0_mods)), (VOP3Mods:{ *:[f32] } f32:{ *:[f32] }:$src2, i32:{ *:[i32] }:$src2_mods)), (fmaxnum_ieee:{ *:[f32] } (VOP3Mods:{ *:[f32] } f32:{ *:[f32] }:$src1, i32:{ *:[i32] }:$src1_mods), (VOP3Mods:{ *:[f32] } f32:{ *:[f32] }:$src0, i32:{ *:[i32] }:$src0_mods)))<<P:Predicate_fminnum_like_nnan>>  =>  (V_MED3_F32_e64:{ *:[f32] } ?:{ *:[i32] }:$src0_mods, ?:{ *:[f32] }:$src0, ?:{ *:[i32] }:$src1_mods, ?:{ *:[f32] }:$src1, ?:{ *:[i32] }:$src2_mods, ?:{ *:[f32] }:$src2, 0:{ *:[i1] }, 0:{ *:[i32] })
        GIR_BuildMI, /*InsnID*/0, /*Opcode*/GIMT_Encode2(AMDGPU::V_MED3_F32_e64),
        GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/0, // DstI[vdst]
        GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(1), /*SubOperand*/1, // src0_mods
        GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(1), /*SubOperand*/0, // src0
        GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/1, // src1_mods
        GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/0, // src1
        GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(2), /*SubOperand*/1, // src2_mods
        GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(2), /*SubOperand*/0, // src2
        GIR_AddImm8, /*InsnID*/0, /*Imm*/0,
        GIR_AddImm8, /*InsnID*/0, /*Imm*/0,
        GIR_ConstrainSelectedInstOperands, /*InsnID*/0,
        GIR_EraseFromParent, /*InsnID*/0,
        // GIR_Coverage, 10370,
        GIR_Done,
      // Label 4452: @287127
      GIM_Try, /*On fail goto*//*Label 4453*/ GIMT_Encode4(287232), // Rule ID 10521 //
        GIM_CheckFeatures, GIMT_Encode2(GIFBS_isGFX11Plus),
        GIM_CheckRegBankForClass, /*MI*/0, /*Op*/0, /*RC*/GIMT_Encode2(AMDGPU::VGPR_32RegClassID),
        GIM_RecordInsn, /*DefineMI*/1, /*MI*/0, /*OpIdx*/2, // MIs[1]
        GIM_CheckOpcode, /*MI*/1, GIMT_Encode2(TargetOpcode::G_FMAXNUM),
        GIM_CheckType, /*MI*/1, /*Op*/1, /*Type*/GILLT_s32,
        GIM_CheckType, /*MI*/1, /*Op*/2, /*Type*/GILLT_s32,
        GIM_CheckCxxInsnPredicate, /*MI*/1, /*FnId*/GIMT_Encode2(GICXXPred_MI_Predicate_fmaxnum_oneuse),
        GIM_CheckIsSafeToFold, /*InsnID*/1,
        GIM_CheckComplexPattern, /*MI*/0, /*Op*/1, /*Renderer*/GIMT_Encode2(0), GIMT_Encode2(GICP_gi_vop3mods),
        GIM_CheckComplexPattern, /*MI*/1, /*Op*/1, /*Renderer*/GIMT_Encode2(1), GIMT_Encode2(GICP_gi_vop3mods),
        GIM_CheckComplexPattern, /*MI*/1, /*Op*/2, /*Renderer*/GIMT_Encode2(2), GIMT_Encode2(GICP_gi_vop3mods),
        // (fminnum:{ *:[f32] } (VOP3Mods:{ *:[f32] } f32:{ *:[f32] }:$src2, i32:{ *:[i32] }:$src2_mods), (fmaxnum:{ *:[f32] } (VOP3Mods:{ *:[f32] } f32:{ *:[f32] }:$src0, i32:{ *:[i32] }:$src0_mods), (VOP3Mods:{ *:[f32] } f32:{ *:[f32] }:$src1, i32:{ *:[i32] }:$src1_mods))<<P:Predicate_fmaxnum_oneuse>>)  =>  (V_MAXMIN_F32_e64:{ *:[f32] } ?:{ *:[i32] }:$src0_mods, ?:{ *:[f32] }:$src0, ?:{ *:[i32] }:$src1_mods, ?:{ *:[f32] }:$src1, ?:{ *:[i32] }:$src2_mods, ?:{ *:[f32] }:$src2, 0:{ *:[i1] }, 0:{ *:[i32] })
        GIR_BuildMI, /*InsnID*/0, /*Opcode*/GIMT_Encode2(AMDGPU::V_MAXMIN_F32_e64),
        GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/0, // DstI[vdst]
        GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(1), /*SubOperand*/1, // src0_mods
        GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(1), /*SubOperand*/0, // src0
        GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(2), /*SubOperand*/1, // src1_mods
        GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(2), /*SubOperand*/0, // src1
        GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/1, // src2_mods
        GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/0, // src2
        GIR_AddImm8, /*InsnID*/0, /*Imm*/0,
        GIR_AddImm8, /*InsnID*/0, /*Imm*/0,
        GIR_ConstrainSelectedInstOperands, /*InsnID*/0,
        GIR_EraseFromParent, /*InsnID*/0,
        // GIR_Coverage, 10521,
        GIR_Done,
      // Label 4453: @287232
      GIM_Try, /*On fail goto*//*Label 4454*/ GIMT_Encode4(287337), // Rule ID 10520 //
        GIM_CheckFeatures, GIMT_Encode2(GIFBS_isGFX11Plus),
        GIM_CheckRegBankForClass, /*MI*/0, /*Op*/0, /*RC*/GIMT_Encode2(AMDGPU::VGPR_32RegClassID),
        GIM_RecordInsn, /*DefineMI*/1, /*MI*/0, /*OpIdx*/2, // MIs[1]
        GIM_CheckOpcode, /*MI*/1, GIMT_Encode2(TargetOpcode::G_FMAXNUM_IEEE),
        GIM_CheckType, /*MI*/1, /*Op*/1, /*Type*/GILLT_s32,
        GIM_CheckType, /*MI*/1, /*Op*/2, /*Type*/GILLT_s32,
        GIM_CheckCxxInsnPredicate, /*MI*/1, /*FnId*/GIMT_Encode2(GICXXPred_MI_Predicate_fmaxnum_ieee_oneuse),
        GIM_CheckIsSafeToFold, /*InsnID*/1,
        GIM_CheckComplexPattern, /*MI*/0, /*Op*/1, /*Renderer*/GIMT_Encode2(0), GIMT_Encode2(GICP_gi_vop3mods),
        GIM_CheckComplexPattern, /*MI*/1, /*Op*/1, /*Renderer*/GIMT_Encode2(1), GIMT_Encode2(GICP_gi_vop3mods),
        GIM_CheckComplexPattern, /*MI*/1, /*Op*/2, /*Renderer*/GIMT_Encode2(2), GIMT_Encode2(GICP_gi_vop3mods),
        // (fminnum:{ *:[f32] } (VOP3Mods:{ *:[f32] } f32:{ *:[f32] }:$src2, i32:{ *:[i32] }:$src2_mods), (fmaxnum_ieee:{ *:[f32] } (VOP3Mods:{ *:[f32] } f32:{ *:[f32] }:$src0, i32:{ *:[i32] }:$src0_mods), (VOP3Mods:{ *:[f32] } f32:{ *:[f32] }:$src1, i32:{ *:[i32] }:$src1_mods))<<P:Predicate_fmaxnum_ieee_oneuse>>)  =>  (V_MAXMIN_F32_e64:{ *:[f32] } ?:{ *:[i32] }:$src0_mods, ?:{ *:[f32] }:$src0, ?:{ *:[i32] }:$src1_mods, ?:{ *:[f32] }:$src1, ?:{ *:[i32] }:$src2_mods, ?:{ *:[f32] }:$src2, 0:{ *:[i1] }, 0:{ *:[i32] })
        GIR_BuildMI, /*InsnID*/0, /*Opcode*/GIMT_Encode2(AMDGPU::V_MAXMIN_F32_e64),
        GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/0, // DstI[vdst]
        GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(1), /*SubOperand*/1, // src0_mods
        GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(1), /*SubOperand*/0, // src0
        GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(2), /*SubOperand*/1, // src1_mods
        GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(2), /*SubOperand*/0, // src1
        GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/1, // src2_mods
        GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/0, // src2
        GIR_AddImm8, /*InsnID*/0, /*Imm*/0,
        GIR_AddImm8, /*InsnID*/0, /*Imm*/0,
        GIR_ConstrainSelectedInstOperands, /*InsnID*/0,
        GIR_EraseFromParent, /*InsnID*/0,
        // GIR_Coverage, 10520,
        GIR_Done,
      // Label 4454: @287337
      GIM_Try, /*On fail goto*//*Label 4455*/ GIMT_Encode4(287442), // Rule ID 6527 //
        GIM_CheckFeatures, GIMT_Encode2(GIFBS_isGFX11Plus),
        GIM_CheckRegBankForClass, /*MI*/0, /*Op*/0, /*RC*/GIMT_Encode2(AMDGPU::VGPR_32RegClassID),
        GIM_RecordInsn, /*DefineMI*/1, /*MI*/0, /*OpIdx*/1, // MIs[1]
        GIM_CheckOpcode, /*MI*/1, GIMT_Encode2(TargetOpcode::G_FMAXNUM),
        GIM_CheckType, /*MI*/1, /*Op*/1, /*Type*/GILLT_s32,
        GIM_CheckType, /*MI*/1, /*Op*/2, /*Type*/GILLT_s32,
        GIM_CheckCxxInsnPredicate, /*MI*/1, /*FnId*/GIMT_Encode2(GICXXPred_MI_Predicate_fmaxnum_oneuse),
        GIM_CheckIsSafeToFold, /*InsnID*/1,
        GIM_CheckComplexPattern, /*MI*/0, /*Op*/2, /*Renderer*/GIMT_Encode2(2), GIMT_Encode2(GICP_gi_vop3mods),
        GIM_CheckComplexPattern, /*MI*/1, /*Op*/1, /*Renderer*/GIMT_Encode2(0), GIMT_Encode2(GICP_gi_vop3mods),
        GIM_CheckComplexPattern, /*MI*/1, /*Op*/2, /*Renderer*/GIMT_Encode2(1), GIMT_Encode2(GICP_gi_vop3mods),
        // (fminnum:{ *:[f32] } (fmaxnum:{ *:[f32] } (VOP3Mods:{ *:[f32] } f32:{ *:[f32] }:$src0, i32:{ *:[i32] }:$src0_mods), (VOP3Mods:{ *:[f32] } f32:{ *:[f32] }:$src1, i32:{ *:[i32] }:$src1_mods))<<P:Predicate_fmaxnum_oneuse>>, (VOP3Mods:{ *:[f32] } f32:{ *:[f32] }:$src2, i32:{ *:[i32] }:$src2_mods))  =>  (V_MAXMIN_F32_e64:{ *:[f32] } ?:{ *:[i32] }:$src0_mods, ?:{ *:[f32] }:$src0, ?:{ *:[i32] }:$src1_mods, ?:{ *:[f32] }:$src1, ?:{ *:[i32] }:$src2_mods, ?:{ *:[f32] }:$src2, 0:{ *:[i1] }, 0:{ *:[i32] })
        GIR_BuildMI, /*InsnID*/0, /*Opcode*/GIMT_Encode2(AMDGPU::V_MAXMIN_F32_e64),
        GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/0, // DstI[vdst]
        GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/1, // src0_mods
        GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/0, // src0
        GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(1), /*SubOperand*/1, // src1_mods
        GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(1), /*SubOperand*/0, // src1
        GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(2), /*SubOperand*/1, // src2_mods
        GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(2), /*SubOperand*/0, // src2
        GIR_AddImm8, /*InsnID*/0, /*Imm*/0,
        GIR_AddImm8, /*InsnID*/0, /*Imm*/0,
        GIR_ConstrainSelectedInstOperands, /*InsnID*/0,
        GIR_EraseFromParent, /*InsnID*/0,
        // GIR_Coverage, 6527,
        GIR_Done,
      // Label 4455: @287442
      GIM_Try, /*On fail goto*//*Label 4456*/ GIMT_Encode4(287547), // Rule ID 6526 //
        GIM_CheckFeatures, GIMT_Encode2(GIFBS_isGFX11Plus),
        GIM_CheckRegBankForClass, /*MI*/0, /*Op*/0, /*RC*/GIMT_Encode2(AMDGPU::VGPR_32RegClassID),
        GIM_RecordInsn, /*DefineMI*/1, /*MI*/0, /*OpIdx*/1, // MIs[1]
        GIM_CheckOpcode, /*MI*/1, GIMT_Encode2(TargetOpcode::G_FMAXNUM_IEEE),
        GIM_CheckType, /*MI*/1, /*Op*/1, /*Type*/GILLT_s32,
        GIM_CheckType, /*MI*/1, /*Op*/2, /*Type*/GILLT_s32,
        GIM_CheckCxxInsnPredicate, /*MI*/1, /*FnId*/GIMT_Encode2(GICXXPred_MI_Predicate_fmaxnum_ieee_oneuse),
        GIM_CheckIsSafeToFold, /*InsnID*/1,
        GIM_CheckComplexPattern, /*MI*/0, /*Op*/2, /*Renderer*/GIMT_Encode2(2), GIMT_Encode2(GICP_gi_vop3mods),
        GIM_CheckComplexPattern, /*MI*/1, /*Op*/1, /*Renderer*/GIMT_Encode2(0), GIMT_Encode2(GICP_gi_vop3mods),
        GIM_CheckComplexPattern, /*MI*/1, /*Op*/2, /*Renderer*/GIMT_Encode2(1), GIMT_Encode2(GICP_gi_vop3mods),
        // (fminnum:{ *:[f32] } (fmaxnum_ieee:{ *:[f32] } (VOP3Mods:{ *:[f32] } f32:{ *:[f32] }:$src0, i32:{ *:[i32] }:$src0_mods), (VOP3Mods:{ *:[f32] } f32:{ *:[f32] }:$src1, i32:{ *:[i32] }:$src1_mods))<<P:Predicate_fmaxnum_ieee_oneuse>>, (VOP3Mods:{ *:[f32] } f32:{ *:[f32] }:$src2, i32:{ *:[i32] }:$src2_mods))  =>  (V_MAXMIN_F32_e64:{ *:[f32] } ?:{ *:[i32] }:$src0_mods, ?:{ *:[f32] }:$src0, ?:{ *:[i32] }:$src1_mods, ?:{ *:[f32] }:$src1, ?:{ *:[i32] }:$src2_mods, ?:{ *:[f32] }:$src2, 0:{ *:[i1] }, 0:{ *:[i32] })
        GIR_BuildMI, /*InsnID*/0, /*Opcode*/GIMT_Encode2(AMDGPU::V_MAXMIN_F32_e64),
        GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/0, // DstI[vdst]
        GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/1, // src0_mods
        GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/0, // src0
        GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(1), /*SubOperand*/1, // src1_mods
        GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(1), /*SubOperand*/0, // src1
        GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(2), /*SubOperand*/1, // src2_mods
        GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(2), /*SubOperand*/0, // src2
        GIR_AddImm8, /*InsnID*/0, /*Imm*/0,
        GIR_AddImm8, /*InsnID*/0, /*Imm*/0,
        GIR_ConstrainSelectedInstOperands, /*InsnID*/0,
        GIR_EraseFromParent, /*InsnID*/0,
        // GIR_Coverage, 6526,
        GIR_Done,
      // Label 4456: @287547
      GIM_Try, /*On fail goto*//*Label 4457*/ GIMT_Encode4(287586), // Rule ID 93 //
        GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasSALUFloatInsts),
        GIM_CheckRegBankForClass, /*MI*/0, /*Op*/0, /*RC*/GIMT_Encode2(AMDGPU::SReg_32RegClassID),
        GIM_CheckRegBankForClass, /*MI*/0, /*Op*/1, /*RC*/GIMT_Encode2(AMDGPU::SReg_32RegClassID),
        GIM_CheckRegBankForClass, /*MI*/0, /*Op*/2, /*RC*/GIMT_Encode2(AMDGPU::SReg_32RegClassID),
        GIM_CheckCxxInsnPredicate, /*MI*/0, /*FnId*/GIMT_Encode2(GICXXPred_MI_Predicate_anonymous_17631),
        // (fminnum:{ *:[f32] } SSrc_f32:{ *:[f32] }:$src0, SSrc_f32:{ *:[f32] }:$src1)<<P:Predicate_anonymous_17631>>  =>  (S_MIN_F32:{ *:[f32] } SSrc_f32:{ *:[f32] }:$src0, SSrc_f32:{ *:[f32] }:$src1)
        GIR_MutateOpcode, /*InsnID*/0, /*RecycleInsnID*/0, /*Opcode*/GIMT_Encode2(AMDGPU::S_MIN_F32),
        GIR_AddImplicitUse, /*InsnID*/0, GIMT_Encode2(AMDGPU::MODE),
        GIR_ConstrainSelectedInstOperands, /*InsnID*/0,
        // GIR_Coverage, 93,
        GIR_Done,
      // Label 4457: @287586
      GIM_Try, /*On fail goto*//*Label 4458*/ GIMT_Encode4(287653), // Rule ID 740 //
        GIM_CheckRegBankForClass, /*MI*/0, /*Op*/0, /*RC*/GIMT_Encode2(AMDGPU::VGPR_32RegClassID),
        GIM_CheckComplexPattern, /*MI*/0, /*Op*/1, /*Renderer*/GIMT_Encode2(0), GIMT_Encode2(GICP_gi_vop3mods0),
        GIM_CheckComplexPattern, /*MI*/0, /*Op*/2, /*Renderer*/GIMT_Encode2(1), GIMT_Encode2(GICP_gi_vop3mods),
        // (fminnum:{ *:[f32] } (VOP3Mods0:{ *:[f32] } f32:{ *:[f32] }:$src0, i32:{ *:[i32] }:$src0_modifiers, i1:{ *:[i1] }:$clamp, i32:{ *:[i32] }:$omod), (VOP3Mods:{ *:[f32] } f32:{ *:[f32] }:$src1, i32:{ *:[i32] }:$src1_modifiers))  =>  (V_MIN_F32_e64:{ *:[f32] } i32:{ *:[i32] }:$src0_modifiers, f32:{ *:[f32] }:$src0, i32:{ *:[i32] }:$src1_modifiers, f32:{ *:[f32] }:$src1, i1:{ *:[i1] }:$clamp, i32:{ *:[i32] }:$omod)
        GIR_BuildMI, /*InsnID*/0, /*Opcode*/GIMT_Encode2(AMDGPU::V_MIN_F32_e64),
        GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/0, // DstI[vdst]
        GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/1, // src0_modifiers
        GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/0, // src0
        GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(1), /*SubOperand*/1, // src1_modifiers
        GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(1), /*SubOperand*/0, // src1
        GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/2, // clamp
        GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/3, // omod
        GIR_ConstrainSelectedInstOperands, /*InsnID*/0,
        GIR_EraseFromParent, /*InsnID*/0,
        // GIR_Coverage, 740,
        GIR_Done,
      // Label 4458: @287653
      GIM_Try, /*On fail goto*//*Label 4459*/ GIMT_Encode4(287720), // Rule ID 7132 //
        GIM_CheckRegBankForClass, /*MI*/0, /*Op*/0, /*RC*/GIMT_Encode2(AMDGPU::VGPR_32RegClassID),
        GIM_CheckComplexPattern, /*MI*/0, /*Op*/1, /*Renderer*/GIMT_Encode2(0), GIMT_Encode2(GICP_gi_vop3mods),
        GIM_CheckComplexPattern, /*MI*/0, /*Op*/2, /*Renderer*/GIMT_Encode2(1), GIMT_Encode2(GICP_gi_vop3mods0),
        // (fminnum:{ *:[f32] } (VOP3Mods:{ *:[f32] } f32:{ *:[f32] }:$src1, i32:{ *:[i32] }:$src1_modifiers), (VOP3Mods0:{ *:[f32] } f32:{ *:[f32] }:$src0, i32:{ *:[i32] }:$src0_modifiers, i1:{ *:[i1] }:$clamp, i32:{ *:[i32] }:$omod))  =>  (V_MIN_F32_e64:{ *:[f32] } i32:{ *:[i32] }:$src0_modifiers, f32:{ *:[f32] }:$src0, i32:{ *:[i32] }:$src1_modifiers, f32:{ *:[f32] }:$src1, i1:{ *:[i1] }:$clamp, i32:{ *:[i32] }:$omod)
        GIR_BuildMI, /*InsnID*/0, /*Opcode*/GIMT_Encode2(AMDGPU::V_MIN_F32_e64),
        GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/0, // DstI[vdst]
        GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(1), /*SubOperand*/1, // src0_modifiers
        GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(1), /*SubOperand*/0, // src0
        GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/1, // src1_modifiers
        GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/0, // src1
        GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(1), /*SubOperand*/2, // clamp
        GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(1), /*SubOperand*/3, // omod
        GIR_ConstrainSelectedInstOperands, /*InsnID*/0,
        GIR_EraseFromParent, /*InsnID*/0,
        // GIR_Coverage, 7132,
        GIR_Done,
      // Label 4459: @287720
      GIM_Reject,
    // Label 4324: @287721
    GIM_Reject,
    // Label 4309: @287722
    GIM_Try, /*On fail goto*//*Label 4460*/ GIMT_Encode4(288001),
      GIM_CheckType, /*MI*/0, /*Op*/1, /*Type*/GILLT_s64,
      GIM_CheckType, /*MI*/0, /*Op*/2, /*Type*/GILLT_s64,
      GIM_CheckRegBankForClass, /*MI*/0, /*Op*/0, /*RC*/GIMT_Encode2(AMDGPU::VReg_64RegClassID),
      GIM_Try, /*On fail goto*//*Label 4461*/ GIMT_Encode4(287805), // Rule ID 843 //
        GIM_CheckFeatures, GIMT_Encode2(GIFBS_isGFX12Plus),
        GIM_CheckComplexPattern, /*MI*/0, /*Op*/1, /*Renderer*/GIMT_Encode2(0), GIMT_Encode2(GICP_gi_vop3mods0),
        GIM_CheckComplexPattern, /*MI*/0, /*Op*/2, /*Renderer*/GIMT_Encode2(1), GIMT_Encode2(GICP_gi_vop3mods),
        // (fminnum:{ *:[f64] } (VOP3Mods0:{ *:[f64] } f64:{ *:[f64] }:$src0, i32:{ *:[i32] }:$src0_modifiers, i1:{ *:[i1] }:$clamp, i32:{ *:[i32] }:$omod), (VOP3Mods:{ *:[f64] } f64:{ *:[f64] }:$src1, i32:{ *:[i32] }:$src1_modifiers))  =>  (V_MIN_NUM_F64_e64:{ *:[f64] } i32:{ *:[i32] }:$src0_modifiers, f64:{ *:[f64] }:$src0, i32:{ *:[i32] }:$src1_modifiers, f64:{ *:[f64] }:$src1, i1:{ *:[i1] }:$clamp, i32:{ *:[i32] }:$omod)
        GIR_BuildMI, /*InsnID*/0, /*Opcode*/GIMT_Encode2(AMDGPU::V_MIN_NUM_F64_e64),
        GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/0, // DstI[vdst]
        GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/1, // src0_modifiers
        GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/0, // src0
        GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(1), /*SubOperand*/1, // src1_modifiers
        GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(1), /*SubOperand*/0, // src1
        GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/2, // clamp
        GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/3, // omod
        GIR_ConstrainSelectedInstOperands, /*InsnID*/0,
        GIR_EraseFromParent, /*InsnID*/0,
        // GIR_Coverage, 843,
        GIR_Done,
      // Label 4461: @287805
      GIM_Try, /*On fail goto*//*Label 4462*/ GIMT_Encode4(287870), // Rule ID 862 //
        GIM_CheckFeatures, GIMT_Encode2(GIFBS_isNotGFX12Plus),
        GIM_CheckComplexPattern, /*MI*/0, /*Op*/1, /*Renderer*/GIMT_Encode2(0), GIMT_Encode2(GICP_gi_vop3mods0),
        GIM_CheckComplexPattern, /*MI*/0, /*Op*/2, /*Renderer*/GIMT_Encode2(1), GIMT_Encode2(GICP_gi_vop3mods),
        // (fminnum:{ *:[f64] } (VOP3Mods0:{ *:[f64] } f64:{ *:[f64] }:$src0, i32:{ *:[i32] }:$src0_modifiers, i1:{ *:[i1] }:$clamp, i32:{ *:[i32] }:$omod), (VOP3Mods:{ *:[f64] } f64:{ *:[f64] }:$src1, i32:{ *:[i32] }:$src1_modifiers))  =>  (V_MIN_F64_e64:{ *:[f64] } i32:{ *:[i32] }:$src0_modifiers, f64:{ *:[f64] }:$src0, i32:{ *:[i32] }:$src1_modifiers, f64:{ *:[f64] }:$src1, i1:{ *:[i1] }:$clamp, i32:{ *:[i32] }:$omod)
        GIR_BuildMI, /*InsnID*/0, /*Opcode*/GIMT_Encode2(AMDGPU::V_MIN_F64_e64),
        GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/0, // DstI[vdst]
        GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/1, // src0_modifiers
        GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/0, // src0
        GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(1), /*SubOperand*/1, // src1_modifiers
        GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(1), /*SubOperand*/0, // src1
        GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/2, // clamp
        GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/3, // omod
        GIR_ConstrainSelectedInstOperands, /*InsnID*/0,
        GIR_EraseFromParent, /*InsnID*/0,
        // GIR_Coverage, 862,
        GIR_Done,
      // Label 4462: @287870
      GIM_Try, /*On fail goto*//*Label 4463*/ GIMT_Encode4(287935), // Rule ID 7166 //
        GIM_CheckFeatures, GIMT_Encode2(GIFBS_isGFX12Plus),
        GIM_CheckComplexPattern, /*MI*/0, /*Op*/1, /*Renderer*/GIMT_Encode2(0), GIMT_Encode2(GICP_gi_vop3mods),
        GIM_CheckComplexPattern, /*MI*/0, /*Op*/2, /*Renderer*/GIMT_Encode2(1), GIMT_Encode2(GICP_gi_vop3mods0),
        // (fminnum:{ *:[f64] } (VOP3Mods:{ *:[f64] } f64:{ *:[f64] }:$src1, i32:{ *:[i32] }:$src1_modifiers), (VOP3Mods0:{ *:[f64] } f64:{ *:[f64] }:$src0, i32:{ *:[i32] }:$src0_modifiers, i1:{ *:[i1] }:$clamp, i32:{ *:[i32] }:$omod))  =>  (V_MIN_NUM_F64_e64:{ *:[f64] } i32:{ *:[i32] }:$src0_modifiers, f64:{ *:[f64] }:$src0, i32:{ *:[i32] }:$src1_modifiers, f64:{ *:[f64] }:$src1, i1:{ *:[i1] }:$clamp, i32:{ *:[i32] }:$omod)
        GIR_BuildMI, /*InsnID*/0, /*Opcode*/GIMT_Encode2(AMDGPU::V_MIN_NUM_F64_e64),
        GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/0, // DstI[vdst]
        GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(1), /*SubOperand*/1, // src0_modifiers
        GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(1), /*SubOperand*/0, // src0
        GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/1, // src1_modifiers
        GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/0, // src1
        GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(1), /*SubOperand*/2, // clamp
        GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(1), /*SubOperand*/3, // omod
        GIR_ConstrainSelectedInstOperands, /*InsnID*/0,
        GIR_EraseFromParent, /*InsnID*/0,
        // GIR_Coverage, 7166,
        GIR_Done,
      // Label 4463: @287935
      GIM_Try, /*On fail goto*//*Label 4464*/ GIMT_Encode4(288000), // Rule ID 7180 //
        GIM_CheckFeatures, GIMT_Encode2(GIFBS_isNotGFX12Plus),
        GIM_CheckComplexPattern, /*MI*/0, /*Op*/1, /*Renderer*/GIMT_Encode2(0), GIMT_Encode2(GICP_gi_vop3mods),
        GIM_CheckComplexPattern, /*MI*/0, /*Op*/2, /*Renderer*/GIMT_Encode2(1), GIMT_Encode2(GICP_gi_vop3mods0),
        // (fminnum:{ *:[f64] } (VOP3Mods:{ *:[f64] } f64:{ *:[f64] }:$src1, i32:{ *:[i32] }:$src1_modifiers), (VOP3Mods0:{ *:[f64] } f64:{ *:[f64] }:$src0, i32:{ *:[i32] }:$src0_modifiers, i1:{ *:[i1] }:$clamp, i32:{ *:[i32] }:$omod))  =>  (V_MIN_F64_e64:{ *:[f64] } i32:{ *:[i32] }:$src0_modifiers, f64:{ *:[f64] }:$src0, i32:{ *:[i32] }:$src1_modifiers, f64:{ *:[f64] }:$src1, i1:{ *:[i1] }:$clamp, i32:{ *:[i32] }:$omod)
        GIR_BuildMI, /*InsnID*/0, /*Opcode*/GIMT_Encode2(AMDGPU::V_MIN_F64_e64),
        GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/0, // DstI[vdst]
        GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(1), /*SubOperand*/1, // src0_modifiers
        GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(1), /*SubOperand*/0, // src0
        GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/1, // src1_modifiers
        GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/0, // src1
        GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(1), /*SubOperand*/2, // clamp
        GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(1), /*SubOperand*/3, // omod
        GIR_ConstrainSelectedInstOperands, /*InsnID*/0,
        GIR_EraseFromParent, /*InsnID*/0,
        // GIR_Coverage, 7180,
        GIR_Done,
      // Label 4464: @288000
      GIM_Reject,
    // Label 4460: @288001
    GIM_Reject,
    // Label 4310: @288002
    GIM_Try, /*On fail goto*//*Label 4465*/ GIMT_Encode4(288082), // Rule ID 967 //
      GIM_CheckType, /*MI*/0, /*Op*/1, /*Type*/GILLT_v2s16,
      GIM_CheckType, /*MI*/0, /*Op*/2, /*Type*/GILLT_v2s16,
      GIM_CheckRegBankForClass, /*MI*/0, /*Op*/0, /*RC*/GIMT_Encode2(AMDGPU::VGPR_32RegClassID),
      GIM_CheckComplexPattern, /*MI*/0, /*Op*/1, /*Renderer*/GIMT_Encode2(0), GIMT_Encode2(GICP_gi_vop3pmods),
      GIM_CheckComplexPattern, /*MI*/0, /*Op*/2, /*Renderer*/GIMT_Encode2(1), GIMT_Encode2(GICP_gi_vop3pmods),
      // (fminnum:{ *:[v2f16] } (VOP3PMods:{ *:[v2f16] } v2f16:{ *:[v2f16] }:$src0, i32:{ *:[i32] }:$src0_modifiers), (VOP3PMods:{ *:[v2f16] } v2f16:{ *:[v2f16] }:$src1, i32:{ *:[i32] }:$src1_modifiers))  =>  (V_PK_MIN_F16:{ *:[v2f16] } i32:{ *:[i32] }:$src0_modifiers, v2f16:{ *:[v2f16] }:$src0, i32:{ *:[i32] }:$src1_modifiers, v2f16:{ *:[v2f16] }:$src1)
      GIR_BuildMI, /*InsnID*/0, /*Opcode*/GIMT_Encode2(AMDGPU::V_PK_MIN_F16),
      GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/0, // DstI[vdst]
      GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/1, // src0_modifiers
      GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/0, // src0
      GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(1), /*SubOperand*/1, // src1_modifiers
      GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(1), /*SubOperand*/0, // src1
      GIR_AddImm8, /*InsnID*/0, /*Imm*/0,
      GIR_AddImm8, /*InsnID*/0, /*Imm*/0,
      GIR_AddImm8, /*InsnID*/0, /*Imm*/0,
      GIR_AddImm8, /*InsnID*/0, /*Imm*/0,
      GIR_AddImm8, /*InsnID*/0, /*Imm*/0,
      GIR_ConstrainSelectedInstOperands, /*InsnID*/0,
      GIR_EraseFromParent, /*InsnID*/0,
      // GIR_Coverage, 967,
      GIR_Done,
    // Label 4465: @288082
    GIM_Reject,
    // Label 4311: @288083
    GIM_Reject,
    // Label 77: @288084
    GIM_SwitchType, /*MI*/0, /*Op*/0, /*[*/GIMT_Encode2(8), GIMT_Encode2(12), /*)*//*default:*//*Label 4470*/ GIMT_Encode4(326582),
    /*GILLT_s16*//*Label 4466*/ GIMT_Encode4(288111),
    /*GILLT_s32*//*Label 4467*/ GIMT_Encode4(307693),
    /*GILLT_s64*//*Label 4468*/ GIMT_Encode4(326221),
    /*GILLT_v2s16*//*Label 4469*/ GIMT_Encode4(326501),
    // Label 4466: @288111
    GIM_Try, /*On fail goto*//*Label 4471*/ GIMT_Encode4(307692),
      GIM_CheckType, /*MI*/0, /*Op*/1, /*Type*/GILLT_s16,
      GIM_CheckType, /*MI*/0, /*Op*/2, /*Type*/GILLT_s16,
      GIM_Try, /*On fail goto*//*Label 4472*/ GIMT_Encode4(288270), // Rule ID 10756 //
        GIM_CheckFeatures, GIMT_Encode2(GIFBS_isGFX9Plus),
        GIM_CheckRegBankForClass, /*MI*/0, /*Op*/0, /*RC*/GIMT_Encode2(AMDGPU::VGPR_32RegClassID),
        GIM_RecordInsn, /*DefineMI*/1, /*MI*/0, /*OpIdx*/1, // MIs[1]
        GIM_CheckOpcode, /*MI*/1, GIMT_Encode2(TargetOpcode::G_FMINNUM),
        GIM_CheckType, /*MI*/1, /*Op*/1, /*Type*/GILLT_s16,
        GIM_CheckType, /*MI*/1, /*Op*/2, /*Type*/GILLT_s16,
        GIM_RecordInsn, /*DefineMI*/2, /*MI*/0, /*OpIdx*/2, // MIs[2]
        GIM_CheckOpcode, /*MI*/2, GIMT_Encode2(TargetOpcode::G_FMINNUM),
        GIM_CheckType, /*MI*/2, /*Op*/1, /*Type*/GILLT_s16,
        GIM_CheckType, /*MI*/2, /*Op*/2, /*Type*/GILLT_s16,
        GIM_RecordInsn, /*DefineMI*/3, /*MI*/2, /*OpIdx*/2, // MIs[3]
        GIM_CheckOpcode, /*MI*/3, GIMT_Encode2(TargetOpcode::G_FMAXNUM),
        // MIs[3] VOP3Mods:src0:src0_mods
        GIM_CheckIsSameOperand, /*MI*/3, /*OpIdx*/1, /*OtherMI*/1, /*OtherOpIdx*/1,
        // MIs[3] VOP3Mods:src1:src1_mods
        GIM_CheckIsSameOperand, /*MI*/3, /*OpIdx*/2, /*OtherMI*/1, /*OtherOpIdx*/2,
        GIM_CheckCxxInsnPredicate, /*MI*/0, /*FnId*/GIMT_Encode2(GICXXPred_MI_Predicate_fmaxnum_like_nnan),
        GIM_CheckIsSafeToFold, /*InsnID*/1,
        GIM_CheckIsSafeToFold, /*InsnID*/2,
        GIM_CheckIsSafeToFold, /*InsnID*/3,
        GIM_CheckComplexPattern, /*MI*/1, /*Op*/1, /*Renderer*/GIMT_Encode2(0), GIMT_Encode2(GICP_gi_vop3mods),
        GIM_CheckComplexPattern, /*MI*/1, /*Op*/2, /*Renderer*/GIMT_Encode2(1), GIMT_Encode2(GICP_gi_vop3mods),
        GIM_CheckComplexPattern, /*MI*/2, /*Op*/1, /*Renderer*/GIMT_Encode2(2), GIMT_Encode2(GICP_gi_vop3mods),
        // (fmaxnum:{ *:[f16] } (fminnum:{ *:[f16] } (VOP3Mods:{ *:[f16] } f16:{ *:[f16] }:$src0, i32:{ *:[i32] }:$src0_mods), (VOP3Mods:{ *:[f16] } f16:{ *:[f16] }:$src1, i32:{ *:[i32] }:$src1_mods)), (fminnum:{ *:[f16] } (VOP3Mods:{ *:[f16] } f16:{ *:[f16] }:$src2, i32:{ *:[i32] }:$src2_mods), (fmaxnum:{ *:[f16] } (VOP3Mods:{ *:[f16] } f16:{ *:[f16] }:$src0, i32:{ *:[i32] }:$src0_mods), (VOP3Mods:{ *:[f16] } f16:{ *:[f16] }:$src1, i32:{ *:[i32] }:$src1_mods))))<<P:Predicate_fmaxnum_like_nnan>>  =>  (V_MED3_F16_e64:{ *:[f16] } ?:{ *:[i32] }:$src0_mods, ?:{ *:[f16] }:$src0, ?:{ *:[i32] }:$src1_mods, ?:{ *:[f16] }:$src1, ?:{ *:[i32] }:$src2_mods, ?:{ *:[f16] }:$src2, 0:{ *:[i1] })
        GIR_BuildMI, /*InsnID*/0, /*Opcode*/GIMT_Encode2(AMDGPU::V_MED3_F16_e64),
        GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/0, // DstI[vdst]
        GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/1, // src0_mods
        GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/0, // src0
        GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(1), /*SubOperand*/1, // src1_mods
        GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(1), /*SubOperand*/0, // src1
        GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(2), /*SubOperand*/1, // src2_mods
        GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(2), /*SubOperand*/0, // src2
        GIR_AddImm8, /*InsnID*/0, /*Imm*/0,
        GIR_AddImm8, /*InsnID*/0, /*Imm*/0,
        GIR_AddImm8, /*InsnID*/0, /*Imm*/0,
        GIR_ConstrainSelectedInstOperands, /*InsnID*/0,
        GIR_EraseFromParent, /*InsnID*/0,
        // GIR_Coverage, 10756,
        GIR_Done,
      // Label 4472: @288270
      GIM_Try, /*On fail goto*//*Label 4473*/ GIMT_Encode4(288416), // Rule ID 10757 //
        GIM_CheckFeatures, GIMT_Encode2(GIFBS_isGFX9Plus),
        GIM_CheckRegBankForClass, /*MI*/0, /*Op*/0, /*RC*/GIMT_Encode2(AMDGPU::VGPR_32RegClassID),
        GIM_RecordInsn, /*DefineMI*/1, /*MI*/0, /*OpIdx*/1, // MIs[1]
        GIM_CheckOpcode, /*MI*/1, GIMT_Encode2(TargetOpcode::G_FMINNUM),
        GIM_CheckType, /*MI*/1, /*Op*/1, /*Type*/GILLT_s16,
        GIM_CheckType, /*MI*/1, /*Op*/2, /*Type*/GILLT_s16,
        GIM_RecordInsn, /*DefineMI*/2, /*MI*/0, /*OpIdx*/2, // MIs[2]
        GIM_CheckOpcode, /*MI*/2, GIMT_Encode2(TargetOpcode::G_FMINNUM),
        GIM_CheckType, /*MI*/2, /*Op*/1, /*Type*/GILLT_s16,
        GIM_CheckType, /*MI*/2, /*Op*/2, /*Type*/GILLT_s16,
        GIM_RecordInsn, /*DefineMI*/3, /*MI*/2, /*OpIdx*/2, // MIs[3]
        GIM_CheckOpcode, /*MI*/3, GIMT_Encode2(TargetOpcode::G_FMAXNUM),
        // MIs[3] VOP3Mods:src1:src1_mods
        GIM_CheckIsSameOperand, /*MI*/3, /*OpIdx*/1, /*OtherMI*/1, /*OtherOpIdx*/2,
        // MIs[3] VOP3Mods:src0:src0_mods
        GIM_CheckIsSameOperand, /*MI*/3, /*OpIdx*/2, /*OtherMI*/1, /*OtherOpIdx*/1,
        GIM_CheckCxxInsnPredicate, /*MI*/0, /*FnId*/GIMT_Encode2(GICXXPred_MI_Predicate_fmaxnum_like_nnan),
        GIM_CheckIsSafeToFold, /*InsnID*/1,
        GIM_CheckIsSafeToFold, /*InsnID*/2,
        GIM_CheckIsSafeToFold, /*InsnID*/3,
        GIM_CheckComplexPattern, /*MI*/1, /*Op*/1, /*Renderer*/GIMT_Encode2(0), GIMT_Encode2(GICP_gi_vop3mods),
        GIM_CheckComplexPattern, /*MI*/1, /*Op*/2, /*Renderer*/GIMT_Encode2(1), GIMT_Encode2(GICP_gi_vop3mods),
        GIM_CheckComplexPattern, /*MI*/2, /*Op*/1, /*Renderer*/GIMT_Encode2(2), GIMT_Encode2(GICP_gi_vop3mods),
        // (fmaxnum:{ *:[f16] } (fminnum:{ *:[f16] } (VOP3Mods:{ *:[f16] } f16:{ *:[f16] }:$src0, i32:{ *:[i32] }:$src0_mods), (VOP3Mods:{ *:[f16] } f16:{ *:[f16] }:$src1, i32:{ *:[i32] }:$src1_mods)), (fminnum:{ *:[f16] } (VOP3Mods:{ *:[f16] } f16:{ *:[f16] }:$src2, i32:{ *:[i32] }:$src2_mods), (fmaxnum:{ *:[f16] } (VOP3Mods:{ *:[f16] } f16:{ *:[f16] }:$src1, i32:{ *:[i32] }:$src1_mods), (VOP3Mods:{ *:[f16] } f16:{ *:[f16] }:$src0, i32:{ *:[i32] }:$src0_mods))))<<P:Predicate_fmaxnum_like_nnan>>  =>  (V_MED3_F16_e64:{ *:[f16] } ?:{ *:[i32] }:$src0_mods, ?:{ *:[f16] }:$src0, ?:{ *:[i32] }:$src1_mods, ?:{ *:[f16] }:$src1, ?:{ *:[i32] }:$src2_mods, ?:{ *:[f16] }:$src2, 0:{ *:[i1] })
        GIR_BuildMI, /*InsnID*/0, /*Opcode*/GIMT_Encode2(AMDGPU::V_MED3_F16_e64),
        GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/0, // DstI[vdst]
        GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/1, // src0_mods
        GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/0, // src0
        GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(1), /*SubOperand*/1, // src1_mods
        GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(1), /*SubOperand*/0, // src1
        GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(2), /*SubOperand*/1, // src2_mods
        GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(2), /*SubOperand*/0, // src2
        GIR_AddImm8, /*InsnID*/0, /*Imm*/0,
        GIR_AddImm8, /*InsnID*/0, /*Imm*/0,
        GIR_AddImm8, /*InsnID*/0, /*Imm*/0,
        GIR_ConstrainSelectedInstOperands, /*InsnID*/0,
        GIR_EraseFromParent, /*InsnID*/0,
        // GIR_Coverage, 10757,
        GIR_Done,
      // Label 4473: @288416
      GIM_Try, /*On fail goto*//*Label 4474*/ GIMT_Encode4(288562), // Rule ID 10760 //
        GIM_CheckFeatures, GIMT_Encode2(GIFBS_isGFX9Plus),
        GIM_CheckRegBankForClass, /*MI*/0, /*Op*/0, /*RC*/GIMT_Encode2(AMDGPU::VGPR_32RegClassID),
        GIM_RecordInsn, /*DefineMI*/1, /*MI*/0, /*OpIdx*/1, // MIs[1]
        GIM_CheckOpcode, /*MI*/1, GIMT_Encode2(TargetOpcode::G_FMINNUM),
        GIM_CheckType, /*MI*/1, /*Op*/1, /*Type*/GILLT_s16,
        GIM_CheckType, /*MI*/1, /*Op*/2, /*Type*/GILLT_s16,
        GIM_RecordInsn, /*DefineMI*/2, /*MI*/0, /*OpIdx*/2, // MIs[2]
        GIM_CheckOpcode, /*MI*/2, GIMT_Encode2(TargetOpcode::G_FMINNUM),
        GIM_CheckType, /*MI*/2, /*Op*/1, /*Type*/GILLT_s16,
        GIM_CheckType, /*MI*/2, /*Op*/2, /*Type*/GILLT_s16,
        GIM_RecordInsn, /*DefineMI*/3, /*MI*/2, /*OpIdx*/2, // MIs[3]
        GIM_CheckOpcode, /*MI*/3, GIMT_Encode2(TargetOpcode::G_FMAXNUM),
        // MIs[3] VOP3Mods:src0:src0_mods
        GIM_CheckIsSameOperand, /*MI*/3, /*OpIdx*/1, /*OtherMI*/1, /*OtherOpIdx*/2,
        // MIs[3] VOP3Mods:src1:src1_mods
        GIM_CheckIsSameOperand, /*MI*/3, /*OpIdx*/2, /*OtherMI*/1, /*OtherOpIdx*/1,
        GIM_CheckCxxInsnPredicate, /*MI*/0, /*FnId*/GIMT_Encode2(GICXXPred_MI_Predicate_fmaxnum_like_nnan),
        GIM_CheckIsSafeToFold, /*InsnID*/1,
        GIM_CheckIsSafeToFold, /*InsnID*/2,
        GIM_CheckIsSafeToFold, /*InsnID*/3,
        GIM_CheckComplexPattern, /*MI*/1, /*Op*/1, /*Renderer*/GIMT_Encode2(0), GIMT_Encode2(GICP_gi_vop3mods),
        GIM_CheckComplexPattern, /*MI*/1, /*Op*/2, /*Renderer*/GIMT_Encode2(1), GIMT_Encode2(GICP_gi_vop3mods),
        GIM_CheckComplexPattern, /*MI*/2, /*Op*/1, /*Renderer*/GIMT_Encode2(2), GIMT_Encode2(GICP_gi_vop3mods),
        // (fmaxnum:{ *:[f16] } (fminnum:{ *:[f16] } (VOP3Mods:{ *:[f16] } f16:{ *:[f16] }:$src1, i32:{ *:[i32] }:$src1_mods), (VOP3Mods:{ *:[f16] } f16:{ *:[f16] }:$src0, i32:{ *:[i32] }:$src0_mods)), (fminnum:{ *:[f16] } (VOP3Mods:{ *:[f16] } f16:{ *:[f16] }:$src2, i32:{ *:[i32] }:$src2_mods), (fmaxnum:{ *:[f16] } (VOP3Mods:{ *:[f16] } f16:{ *:[f16] }:$src0, i32:{ *:[i32] }:$src0_mods), (VOP3Mods:{ *:[f16] } f16:{ *:[f16] }:$src1, i32:{ *:[i32] }:$src1_mods))))<<P:Predicate_fmaxnum_like_nnan>>  =>  (V_MED3_F16_e64:{ *:[f16] } ?:{ *:[i32] }:$src0_mods, ?:{ *:[f16] }:$src0, ?:{ *:[i32] }:$src1_mods, ?:{ *:[f16] }:$src1, ?:{ *:[i32] }:$src2_mods, ?:{ *:[f16] }:$src2, 0:{ *:[i1] })
        GIR_BuildMI, /*InsnID*/0, /*Opcode*/GIMT_Encode2(AMDGPU::V_MED3_F16_e64),
        GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/0, // DstI[vdst]
        GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(1), /*SubOperand*/1, // src0_mods
        GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(1), /*SubOperand*/0, // src0
        GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/1, // src1_mods
        GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/0, // src1
        GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(2), /*SubOperand*/1, // src2_mods
        GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(2), /*SubOperand*/0, // src2
        GIR_AddImm8, /*InsnID*/0, /*Imm*/0,
        GIR_AddImm8, /*InsnID*/0, /*Imm*/0,
        GIR_AddImm8, /*InsnID*/0, /*Imm*/0,
        GIR_ConstrainSelectedInstOperands, /*InsnID*/0,
        GIR_EraseFromParent, /*InsnID*/0,
        // GIR_Coverage, 10760,
        GIR_Done,
      // Label 4474: @288562
      GIM_Try, /*On fail goto*//*Label 4475*/ GIMT_Encode4(288708), // Rule ID 10761 //
        GIM_CheckFeatures, GIMT_Encode2(GIFBS_isGFX9Plus),
        GIM_CheckRegBankForClass, /*MI*/0, /*Op*/0, /*RC*/GIMT_Encode2(AMDGPU::VGPR_32RegClassID),
        GIM_RecordInsn, /*DefineMI*/1, /*MI*/0, /*OpIdx*/1, // MIs[1]
        GIM_CheckOpcode, /*MI*/1, GIMT_Encode2(TargetOpcode::G_FMINNUM),
        GIM_CheckType, /*MI*/1, /*Op*/1, /*Type*/GILLT_s16,
        GIM_CheckType, /*MI*/1, /*Op*/2, /*Type*/GILLT_s16,
        GIM_RecordInsn, /*DefineMI*/2, /*MI*/0, /*OpIdx*/2, // MIs[2]
        GIM_CheckOpcode, /*MI*/2, GIMT_Encode2(TargetOpcode::G_FMINNUM),
        GIM_CheckType, /*MI*/2, /*Op*/1, /*Type*/GILLT_s16,
        GIM_CheckType, /*MI*/2, /*Op*/2, /*Type*/GILLT_s16,
        GIM_RecordInsn, /*DefineMI*/3, /*MI*/2, /*OpIdx*/2, // MIs[3]
        GIM_CheckOpcode, /*MI*/3, GIMT_Encode2(TargetOpcode::G_FMAXNUM),
        // MIs[3] VOP3Mods:src1:src1_mods
        GIM_CheckIsSameOperand, /*MI*/3, /*OpIdx*/1, /*OtherMI*/1, /*OtherOpIdx*/1,
        // MIs[3] VOP3Mods:src0:src0_mods
        GIM_CheckIsSameOperand, /*MI*/3, /*OpIdx*/2, /*OtherMI*/1, /*OtherOpIdx*/2,
        GIM_CheckCxxInsnPredicate, /*MI*/0, /*FnId*/GIMT_Encode2(GICXXPred_MI_Predicate_fmaxnum_like_nnan),
        GIM_CheckIsSafeToFold, /*InsnID*/1,
        GIM_CheckIsSafeToFold, /*InsnID*/2,
        GIM_CheckIsSafeToFold, /*InsnID*/3,
        GIM_CheckComplexPattern, /*MI*/1, /*Op*/1, /*Renderer*/GIMT_Encode2(0), GIMT_Encode2(GICP_gi_vop3mods),
        GIM_CheckComplexPattern, /*MI*/1, /*Op*/2, /*Renderer*/GIMT_Encode2(1), GIMT_Encode2(GICP_gi_vop3mods),
        GIM_CheckComplexPattern, /*MI*/2, /*Op*/1, /*Renderer*/GIMT_Encode2(2), GIMT_Encode2(GICP_gi_vop3mods),
        // (fmaxnum:{ *:[f16] } (fminnum:{ *:[f16] } (VOP3Mods:{ *:[f16] } f16:{ *:[f16] }:$src1, i32:{ *:[i32] }:$src1_mods), (VOP3Mods:{ *:[f16] } f16:{ *:[f16] }:$src0, i32:{ *:[i32] }:$src0_mods)), (fminnum:{ *:[f16] } (VOP3Mods:{ *:[f16] } f16:{ *:[f16] }:$src2, i32:{ *:[i32] }:$src2_mods), (fmaxnum:{ *:[f16] } (VOP3Mods:{ *:[f16] } f16:{ *:[f16] }:$src1, i32:{ *:[i32] }:$src1_mods), (VOP3Mods:{ *:[f16] } f16:{ *:[f16] }:$src0, i32:{ *:[i32] }:$src0_mods))))<<P:Predicate_fmaxnum_like_nnan>>  =>  (V_MED3_F16_e64:{ *:[f16] } ?:{ *:[i32] }:$src0_mods, ?:{ *:[f16] }:$src0, ?:{ *:[i32] }:$src1_mods, ?:{ *:[f16] }:$src1, ?:{ *:[i32] }:$src2_mods, ?:{ *:[f16] }:$src2, 0:{ *:[i1] })
        GIR_BuildMI, /*InsnID*/0, /*Opcode*/GIMT_Encode2(AMDGPU::V_MED3_F16_e64),
        GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/0, // DstI[vdst]
        GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(1), /*SubOperand*/1, // src0_mods
        GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(1), /*SubOperand*/0, // src0
        GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/1, // src1_mods
        GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/0, // src1
        GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(2), /*SubOperand*/1, // src2_mods
        GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(2), /*SubOperand*/0, // src2
        GIR_AddImm8, /*InsnID*/0, /*Imm*/0,
        GIR_AddImm8, /*InsnID*/0, /*Imm*/0,
        GIR_AddImm8, /*InsnID*/0, /*Imm*/0,
        GIR_ConstrainSelectedInstOperands, /*InsnID*/0,
        GIR_EraseFromParent, /*InsnID*/0,
        // GIR_Coverage, 10761,
        GIR_Done,
      // Label 4475: @288708
      GIM_Try, /*On fail goto*//*Label 4476*/ GIMT_Encode4(288854), // Rule ID 10741 //
        GIM_CheckFeatures, GIMT_Encode2(GIFBS_isGFX9Plus),
        GIM_CheckRegBankForClass, /*MI*/0, /*Op*/0, /*RC*/GIMT_Encode2(AMDGPU::VGPR_32RegClassID),
        GIM_RecordInsn, /*DefineMI*/1, /*MI*/0, /*OpIdx*/1, // MIs[1]
        GIM_CheckOpcode, /*MI*/1, GIMT_Encode2(TargetOpcode::G_FMINNUM),
        GIM_CheckType, /*MI*/1, /*Op*/1, /*Type*/GILLT_s16,
        GIM_CheckType, /*MI*/1, /*Op*/2, /*Type*/GILLT_s16,
        GIM_RecordInsn, /*DefineMI*/2, /*MI*/0, /*OpIdx*/2, // MIs[2]
        GIM_CheckOpcode, /*MI*/2, GIMT_Encode2(TargetOpcode::G_FMINNUM),
        GIM_CheckType, /*MI*/2, /*Op*/1, /*Type*/GILLT_s16,
        GIM_CheckType, /*MI*/2, /*Op*/2, /*Type*/GILLT_s16,
        GIM_RecordInsn, /*DefineMI*/3, /*MI*/2, /*OpIdx*/2, // MIs[3]
        GIM_CheckOpcode, /*MI*/3, GIMT_Encode2(TargetOpcode::G_FMAXNUM_IEEE),
        // MIs[3] VOP3Mods:src0:src0_mods
        GIM_CheckIsSameOperand, /*MI*/3, /*OpIdx*/1, /*OtherMI*/1, /*OtherOpIdx*/1,
        // MIs[3] VOP3Mods:src1:src1_mods
        GIM_CheckIsSameOperand, /*MI*/3, /*OpIdx*/2, /*OtherMI*/1, /*OtherOpIdx*/2,
        GIM_CheckCxxInsnPredicate, /*MI*/0, /*FnId*/GIMT_Encode2(GICXXPred_MI_Predicate_fmaxnum_like_nnan),
        GIM_CheckIsSafeToFold, /*InsnID*/1,
        GIM_CheckIsSafeToFold, /*InsnID*/2,
        GIM_CheckIsSafeToFold, /*InsnID*/3,
        GIM_CheckComplexPattern, /*MI*/1, /*Op*/1, /*Renderer*/GIMT_Encode2(0), GIMT_Encode2(GICP_gi_vop3mods),
        GIM_CheckComplexPattern, /*MI*/1, /*Op*/2, /*Renderer*/GIMT_Encode2(1), GIMT_Encode2(GICP_gi_vop3mods),
        GIM_CheckComplexPattern, /*MI*/2, /*Op*/1, /*Renderer*/GIMT_Encode2(2), GIMT_Encode2(GICP_gi_vop3mods),
        // (fmaxnum:{ *:[f16] } (fminnum:{ *:[f16] } (VOP3Mods:{ *:[f16] } f16:{ *:[f16] }:$src0, i32:{ *:[i32] }:$src0_mods), (VOP3Mods:{ *:[f16] } f16:{ *:[f16] }:$src1, i32:{ *:[i32] }:$src1_mods)), (fminnum:{ *:[f16] } (VOP3Mods:{ *:[f16] } f16:{ *:[f16] }:$src2, i32:{ *:[i32] }:$src2_mods), (fmaxnum_ieee:{ *:[f16] } (VOP3Mods:{ *:[f16] } f16:{ *:[f16] }:$src0, i32:{ *:[i32] }:$src0_mods), (VOP3Mods:{ *:[f16] } f16:{ *:[f16] }:$src1, i32:{ *:[i32] }:$src1_mods))))<<P:Predicate_fmaxnum_like_nnan>>  =>  (V_MED3_F16_e64:{ *:[f16] } ?:{ *:[i32] }:$src0_mods, ?:{ *:[f16] }:$src0, ?:{ *:[i32] }:$src1_mods, ?:{ *:[f16] }:$src1, ?:{ *:[i32] }:$src2_mods, ?:{ *:[f16] }:$src2, 0:{ *:[i1] })
        GIR_BuildMI, /*InsnID*/0, /*Opcode*/GIMT_Encode2(AMDGPU::V_MED3_F16_e64),
        GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/0, // DstI[vdst]
        GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/1, // src0_mods
        GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/0, // src0
        GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(1), /*SubOperand*/1, // src1_mods
        GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(1), /*SubOperand*/0, // src1
        GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(2), /*SubOperand*/1, // src2_mods
        GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(2), /*SubOperand*/0, // src2
        GIR_AddImm8, /*InsnID*/0, /*Imm*/0,
        GIR_AddImm8, /*InsnID*/0, /*Imm*/0,
        GIR_AddImm8, /*InsnID*/0, /*Imm*/0,
        GIR_ConstrainSelectedInstOperands, /*InsnID*/0,
        GIR_EraseFromParent, /*InsnID*/0,
        // GIR_Coverage, 10741,
        GIR_Done,
      // Label 4476: @288854
      GIM_Try, /*On fail goto*//*Label 4477*/ GIMT_Encode4(289000), // Rule ID 10742 //
        GIM_CheckFeatures, GIMT_Encode2(GIFBS_isGFX9Plus),
        GIM_CheckRegBankForClass, /*MI*/0, /*Op*/0, /*RC*/GIMT_Encode2(AMDGPU::VGPR_32RegClassID),
        GIM_RecordInsn, /*DefineMI*/1, /*MI*/0, /*OpIdx*/1, // MIs[1]
        GIM_CheckOpcode, /*MI*/1, GIMT_Encode2(TargetOpcode::G_FMINNUM),
        GIM_CheckType, /*MI*/1, /*Op*/1, /*Type*/GILLT_s16,
        GIM_CheckType, /*MI*/1, /*Op*/2, /*Type*/GILLT_s16,
        GIM_RecordInsn, /*DefineMI*/2, /*MI*/0, /*OpIdx*/2, // MIs[2]
        GIM_CheckOpcode, /*MI*/2, GIMT_Encode2(TargetOpcode::G_FMINNUM),
        GIM_CheckType, /*MI*/2, /*Op*/1, /*Type*/GILLT_s16,
        GIM_CheckType, /*MI*/2, /*Op*/2, /*Type*/GILLT_s16,
        GIM_RecordInsn, /*DefineMI*/3, /*MI*/2, /*OpIdx*/2, // MIs[3]
        GIM_CheckOpcode, /*MI*/3, GIMT_Encode2(TargetOpcode::G_FMAXNUM_IEEE),
        // MIs[3] VOP3Mods:src1:src1_mods
        GIM_CheckIsSameOperand, /*MI*/3, /*OpIdx*/1, /*OtherMI*/1, /*OtherOpIdx*/2,
        // MIs[3] VOP3Mods:src0:src0_mods
        GIM_CheckIsSameOperand, /*MI*/3, /*OpIdx*/2, /*OtherMI*/1, /*OtherOpIdx*/1,
        GIM_CheckCxxInsnPredicate, /*MI*/0, /*FnId*/GIMT_Encode2(GICXXPred_MI_Predicate_fmaxnum_like_nnan),
        GIM_CheckIsSafeToFold, /*InsnID*/1,
        GIM_CheckIsSafeToFold, /*InsnID*/2,
        GIM_CheckIsSafeToFold, /*InsnID*/3,
        GIM_CheckComplexPattern, /*MI*/1, /*Op*/1, /*Renderer*/GIMT_Encode2(0), GIMT_Encode2(GICP_gi_vop3mods),
        GIM_CheckComplexPattern, /*MI*/1, /*Op*/2, /*Renderer*/GIMT_Encode2(1), GIMT_Encode2(GICP_gi_vop3mods),
        GIM_CheckComplexPattern, /*MI*/2, /*Op*/1, /*Renderer*/GIMT_Encode2(2), GIMT_Encode2(GICP_gi_vop3mods),
        // (fmaxnum:{ *:[f16] } (fminnum:{ *:[f16] } (VOP3Mods:{ *:[f16] } f16:{ *:[f16] }:$src0, i32:{ *:[i32] }:$src0_mods), (VOP3Mods:{ *:[f16] } f16:{ *:[f16] }:$src1, i32:{ *:[i32] }:$src1_mods)), (fminnum:{ *:[f16] } (VOP3Mods:{ *:[f16] } f16:{ *:[f16] }:$src2, i32:{ *:[i32] }:$src2_mods), (fmaxnum_ieee:{ *:[f16] } (VOP3Mods:{ *:[f16] } f16:{ *:[f16] }:$src1, i32:{ *:[i32] }:$src1_mods), (VOP3Mods:{ *:[f16] } f16:{ *:[f16] }:$src0, i32:{ *:[i32] }:$src0_mods))))<<P:Predicate_fmaxnum_like_nnan>>  =>  (V_MED3_F16_e64:{ *:[f16] } ?:{ *:[i32] }:$src0_mods, ?:{ *:[f16] }:$src0, ?:{ *:[i32] }:$src1_mods, ?:{ *:[f16] }:$src1, ?:{ *:[i32] }:$src2_mods, ?:{ *:[f16] }:$src2, 0:{ *:[i1] })
        GIR_BuildMI, /*InsnID*/0, /*Opcode*/GIMT_Encode2(AMDGPU::V_MED3_F16_e64),
        GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/0, // DstI[vdst]
        GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/1, // src0_mods
        GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/0, // src0
        GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(1), /*SubOperand*/1, // src1_mods
        GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(1), /*SubOperand*/0, // src1
        GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(2), /*SubOperand*/1, // src2_mods
        GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(2), /*SubOperand*/0, // src2
        GIR_AddImm8, /*InsnID*/0, /*Imm*/0,
        GIR_AddImm8, /*InsnID*/0, /*Imm*/0,
        GIR_AddImm8, /*InsnID*/0, /*Imm*/0,
        GIR_ConstrainSelectedInstOperands, /*InsnID*/0,
        GIR_EraseFromParent, /*InsnID*/0,
        // GIR_Coverage, 10742,
        GIR_Done,
      // Label 4477: @289000
      GIM_Try, /*On fail goto*//*Label 4478*/ GIMT_Encode4(289146), // Rule ID 10745 //
        GIM_CheckFeatures, GIMT_Encode2(GIFBS_isGFX9Plus),
        GIM_CheckRegBankForClass, /*MI*/0, /*Op*/0, /*RC*/GIMT_Encode2(AMDGPU::VGPR_32RegClassID),
        GIM_RecordInsn, /*DefineMI*/1, /*MI*/0, /*OpIdx*/1, // MIs[1]
        GIM_CheckOpcode, /*MI*/1, GIMT_Encode2(TargetOpcode::G_FMINNUM),
        GIM_CheckType, /*MI*/1, /*Op*/1, /*Type*/GILLT_s16,
        GIM_CheckType, /*MI*/1, /*Op*/2, /*Type*/GILLT_s16,
        GIM_RecordInsn, /*DefineMI*/2, /*MI*/0, /*OpIdx*/2, // MIs[2]
        GIM_CheckOpcode, /*MI*/2, GIMT_Encode2(TargetOpcode::G_FMINNUM),
        GIM_CheckType, /*MI*/2, /*Op*/1, /*Type*/GILLT_s16,
        GIM_CheckType, /*MI*/2, /*Op*/2, /*Type*/GILLT_s16,
        GIM_RecordInsn, /*DefineMI*/3, /*MI*/2, /*OpIdx*/2, // MIs[3]
        GIM_CheckOpcode, /*MI*/3, GIMT_Encode2(TargetOpcode::G_FMAXNUM_IEEE),
        // MIs[3] VOP3Mods:src0:src0_mods
        GIM_CheckIsSameOperand, /*MI*/3, /*OpIdx*/1, /*OtherMI*/1, /*OtherOpIdx*/2,
        // MIs[3] VOP3Mods:src1:src1_mods
        GIM_CheckIsSameOperand, /*MI*/3, /*OpIdx*/2, /*OtherMI*/1, /*OtherOpIdx*/1,
        GIM_CheckCxxInsnPredicate, /*MI*/0, /*FnId*/GIMT_Encode2(GICXXPred_MI_Predicate_fmaxnum_like_nnan),
        GIM_CheckIsSafeToFold, /*InsnID*/1,
        GIM_CheckIsSafeToFold, /*InsnID*/2,
        GIM_CheckIsSafeToFold, /*InsnID*/3,
        GIM_CheckComplexPattern, /*MI*/1, /*Op*/1, /*Renderer*/GIMT_Encode2(0), GIMT_Encode2(GICP_gi_vop3mods),
        GIM_CheckComplexPattern, /*MI*/1, /*Op*/2, /*Renderer*/GIMT_Encode2(1), GIMT_Encode2(GICP_gi_vop3mods),
        GIM_CheckComplexPattern, /*MI*/2, /*Op*/1, /*Renderer*/GIMT_Encode2(2), GIMT_Encode2(GICP_gi_vop3mods),
        // (fmaxnum:{ *:[f16] } (fminnum:{ *:[f16] } (VOP3Mods:{ *:[f16] } f16:{ *:[f16] }:$src1, i32:{ *:[i32] }:$src1_mods), (VOP3Mods:{ *:[f16] } f16:{ *:[f16] }:$src0, i32:{ *:[i32] }:$src0_mods)), (fminnum:{ *:[f16] } (VOP3Mods:{ *:[f16] } f16:{ *:[f16] }:$src2, i32:{ *:[i32] }:$src2_mods), (fmaxnum_ieee:{ *:[f16] } (VOP3Mods:{ *:[f16] } f16:{ *:[f16] }:$src0, i32:{ *:[i32] }:$src0_mods), (VOP3Mods:{ *:[f16] } f16:{ *:[f16] }:$src1, i32:{ *:[i32] }:$src1_mods))))<<P:Predicate_fmaxnum_like_nnan>>  =>  (V_MED3_F16_e64:{ *:[f16] } ?:{ *:[i32] }:$src0_mods, ?:{ *:[f16] }:$src0, ?:{ *:[i32] }:$src1_mods, ?:{ *:[f16] }:$src1, ?:{ *:[i32] }:$src2_mods, ?:{ *:[f16] }:$src2, 0:{ *:[i1] })
        GIR_BuildMI, /*InsnID*/0, /*Opcode*/GIMT_Encode2(AMDGPU::V_MED3_F16_e64),
        GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/0, // DstI[vdst]
        GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(1), /*SubOperand*/1, // src0_mods
        GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(1), /*SubOperand*/0, // src0
        GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/1, // src1_mods
        GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/0, // src1
        GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(2), /*SubOperand*/1, // src2_mods
        GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(2), /*SubOperand*/0, // src2
        GIR_AddImm8, /*InsnID*/0, /*Imm*/0,
        GIR_AddImm8, /*InsnID*/0, /*Imm*/0,
        GIR_AddImm8, /*InsnID*/0, /*Imm*/0,
        GIR_ConstrainSelectedInstOperands, /*InsnID*/0,
        GIR_EraseFromParent, /*InsnID*/0,
        // GIR_Coverage, 10745,
        GIR_Done,
      // Label 4478: @289146
      GIM_Try, /*On fail goto*//*Label 4479*/ GIMT_Encode4(289292), // Rule ID 10746 //
        GIM_CheckFeatures, GIMT_Encode2(GIFBS_isGFX9Plus),
        GIM_CheckRegBankForClass, /*MI*/0, /*Op*/0, /*RC*/GIMT_Encode2(AMDGPU::VGPR_32RegClassID),
        GIM_RecordInsn, /*DefineMI*/1, /*MI*/0, /*OpIdx*/1, // MIs[1]
        GIM_CheckOpcode, /*MI*/1, GIMT_Encode2(TargetOpcode::G_FMINNUM),
        GIM_CheckType, /*MI*/1, /*Op*/1, /*Type*/GILLT_s16,
        GIM_CheckType, /*MI*/1, /*Op*/2, /*Type*/GILLT_s16,
        GIM_RecordInsn, /*DefineMI*/2, /*MI*/0, /*OpIdx*/2, // MIs[2]
        GIM_CheckOpcode, /*MI*/2, GIMT_Encode2(TargetOpcode::G_FMINNUM),
        GIM_CheckType, /*MI*/2, /*Op*/1, /*Type*/GILLT_s16,
        GIM_CheckType, /*MI*/2, /*Op*/2, /*Type*/GILLT_s16,
        GIM_RecordInsn, /*DefineMI*/3, /*MI*/2, /*OpIdx*/2, // MIs[3]
        GIM_CheckOpcode, /*MI*/3, GIMT_Encode2(TargetOpcode::G_FMAXNUM_IEEE),
        // MIs[3] VOP3Mods:src1:src1_mods
        GIM_CheckIsSameOperand, /*MI*/3, /*OpIdx*/1, /*OtherMI*/1, /*OtherOpIdx*/1,
        // MIs[3] VOP3Mods:src0:src0_mods
        GIM_CheckIsSameOperand, /*MI*/3, /*OpIdx*/2, /*OtherMI*/1, /*OtherOpIdx*/2,
        GIM_CheckCxxInsnPredicate, /*MI*/0, /*FnId*/GIMT_Encode2(GICXXPred_MI_Predicate_fmaxnum_like_nnan),
        GIM_CheckIsSafeToFold, /*InsnID*/1,
        GIM_CheckIsSafeToFold, /*InsnID*/2,
        GIM_CheckIsSafeToFold, /*InsnID*/3,
        GIM_CheckComplexPattern, /*MI*/1, /*Op*/1, /*Renderer*/GIMT_Encode2(0), GIMT_Encode2(GICP_gi_vop3mods),
        GIM_CheckComplexPattern, /*MI*/1, /*Op*/2, /*Renderer*/GIMT_Encode2(1), GIMT_Encode2(GICP_gi_vop3mods),
        GIM_CheckComplexPattern, /*MI*/2, /*Op*/1, /*Renderer*/GIMT_Encode2(2), GIMT_Encode2(GICP_gi_vop3mods),
        // (fmaxnum:{ *:[f16] } (fminnum:{ *:[f16] } (VOP3Mods:{ *:[f16] } f16:{ *:[f16] }:$src1, i32:{ *:[i32] }:$src1_mods), (VOP3Mods:{ *:[f16] } f16:{ *:[f16] }:$src0, i32:{ *:[i32] }:$src0_mods)), (fminnum:{ *:[f16] } (VOP3Mods:{ *:[f16] } f16:{ *:[f16] }:$src2, i32:{ *:[i32] }:$src2_mods), (fmaxnum_ieee:{ *:[f16] } (VOP3Mods:{ *:[f16] } f16:{ *:[f16] }:$src1, i32:{ *:[i32] }:$src1_mods), (VOP3Mods:{ *:[f16] } f16:{ *:[f16] }:$src0, i32:{ *:[i32] }:$src0_mods))))<<P:Predicate_fmaxnum_like_nnan>>  =>  (V_MED3_F16_e64:{ *:[f16] } ?:{ *:[i32] }:$src0_mods, ?:{ *:[f16] }:$src0, ?:{ *:[i32] }:$src1_mods, ?:{ *:[f16] }:$src1, ?:{ *:[i32] }:$src2_mods, ?:{ *:[f16] }:$src2, 0:{ *:[i1] })
        GIR_BuildMI, /*InsnID*/0, /*Opcode*/GIMT_Encode2(AMDGPU::V_MED3_F16_e64),
        GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/0, // DstI[vdst]
        GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(1), /*SubOperand*/1, // src0_mods
        GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(1), /*SubOperand*/0, // src0
        GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/1, // src1_mods
        GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/0, // src1
        GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(2), /*SubOperand*/1, // src2_mods
        GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(2), /*SubOperand*/0, // src2
        GIR_AddImm8, /*InsnID*/0, /*Imm*/0,
        GIR_AddImm8, /*InsnID*/0, /*Imm*/0,
        GIR_AddImm8, /*InsnID*/0, /*Imm*/0,
        GIR_ConstrainSelectedInstOperands, /*InsnID*/0,
        GIR_EraseFromParent, /*InsnID*/0,
        // GIR_Coverage, 10746,
        GIR_Done,
      // Label 4479: @289292
      GIM_Try, /*On fail goto*//*Label 4480*/ GIMT_Encode4(289438), // Rule ID 6551 //
        GIM_CheckFeatures, GIMT_Encode2(GIFBS_isGFX9Plus),
        GIM_CheckRegBankForClass, /*MI*/0, /*Op*/0, /*RC*/GIMT_Encode2(AMDGPU::VGPR_32RegClassID),
        GIM_RecordInsn, /*DefineMI*/1, /*MI*/0, /*OpIdx*/1, // MIs[1]
        GIM_CheckOpcode, /*MI*/1, GIMT_Encode2(TargetOpcode::G_FMINNUM),
        GIM_CheckType, /*MI*/1, /*Op*/1, /*Type*/GILLT_s16,
        GIM_CheckType, /*MI*/1, /*Op*/2, /*Type*/GILLT_s16,
        GIM_RecordInsn, /*DefineMI*/2, /*MI*/0, /*OpIdx*/2, // MIs[2]
        GIM_CheckOpcode, /*MI*/2, GIMT_Encode2(TargetOpcode::G_FMINNUM),
        GIM_CheckType, /*MI*/2, /*Op*/1, /*Type*/GILLT_s16,
        GIM_CheckType, /*MI*/2, /*Op*/2, /*Type*/GILLT_s16,
        GIM_RecordInsn, /*DefineMI*/3, /*MI*/2, /*OpIdx*/1, // MIs[3]
        GIM_CheckOpcode, /*MI*/3, GIMT_Encode2(TargetOpcode::G_FMAXNUM),
        // MIs[3] VOP3Mods:src0:src0_mods
        GIM_CheckIsSameOperand, /*MI*/3, /*OpIdx*/1, /*OtherMI*/1, /*OtherOpIdx*/1,
        // MIs[3] VOP3Mods:src1:src1_mods
        GIM_CheckIsSameOperand, /*MI*/3, /*OpIdx*/2, /*OtherMI*/1, /*OtherOpIdx*/2,
        GIM_CheckCxxInsnPredicate, /*MI*/0, /*FnId*/GIMT_Encode2(GICXXPred_MI_Predicate_fmaxnum_like_nnan),
        GIM_CheckIsSafeToFold, /*InsnID*/1,
        GIM_CheckIsSafeToFold, /*InsnID*/2,
        GIM_CheckIsSafeToFold, /*InsnID*/3,
        GIM_CheckComplexPattern, /*MI*/1, /*Op*/1, /*Renderer*/GIMT_Encode2(0), GIMT_Encode2(GICP_gi_vop3mods),
        GIM_CheckComplexPattern, /*MI*/1, /*Op*/2, /*Renderer*/GIMT_Encode2(1), GIMT_Encode2(GICP_gi_vop3mods),
        GIM_CheckComplexPattern, /*MI*/2, /*Op*/2, /*Renderer*/GIMT_Encode2(2), GIMT_Encode2(GICP_gi_vop3mods),
        // (fmaxnum:{ *:[f16] } (fminnum:{ *:[f16] } (VOP3Mods:{ *:[f16] } f16:{ *:[f16] }:$src0, i32:{ *:[i32] }:$src0_mods), (VOP3Mods:{ *:[f16] } f16:{ *:[f16] }:$src1, i32:{ *:[i32] }:$src1_mods)), (fminnum:{ *:[f16] } (fmaxnum:{ *:[f16] } (VOP3Mods:{ *:[f16] } f16:{ *:[f16] }:$src0, i32:{ *:[i32] }:$src0_mods), (VOP3Mods:{ *:[f16] } f16:{ *:[f16] }:$src1, i32:{ *:[i32] }:$src1_mods)), (VOP3Mods:{ *:[f16] } f16:{ *:[f16] }:$src2, i32:{ *:[i32] }:$src2_mods)))<<P:Predicate_fmaxnum_like_nnan>>  =>  (V_MED3_F16_e64:{ *:[f16] } ?:{ *:[i32] }:$src0_mods, ?:{ *:[f16] }:$src0, ?:{ *:[i32] }:$src1_mods, ?:{ *:[f16] }:$src1, ?:{ *:[i32] }:$src2_mods, ?:{ *:[f16] }:$src2, 0:{ *:[i1] })
        GIR_BuildMI, /*InsnID*/0, /*Opcode*/GIMT_Encode2(AMDGPU::V_MED3_F16_e64),
        GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/0, // DstI[vdst]
        GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/1, // src0_mods
        GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/0, // src0
        GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(1), /*SubOperand*/1, // src1_mods
        GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(1), /*SubOperand*/0, // src1
        GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(2), /*SubOperand*/1, // src2_mods
        GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(2), /*SubOperand*/0, // src2
        GIR_AddImm8, /*InsnID*/0, /*Imm*/0,
        GIR_AddImm8, /*InsnID*/0, /*Imm*/0,
        GIR_AddImm8, /*InsnID*/0, /*Imm*/0,
        GIR_ConstrainSelectedInstOperands, /*InsnID*/0,
        GIR_EraseFromParent, /*InsnID*/0,
        // GIR_Coverage, 6551,
        GIR_Done,
      // Label 4480: @289438
      GIM_Try, /*On fail goto*//*Label 4481*/ GIMT_Encode4(289584), // Rule ID 10755 //
        GIM_CheckFeatures, GIMT_Encode2(GIFBS_isGFX9Plus),
        GIM_CheckRegBankForClass, /*MI*/0, /*Op*/0, /*RC*/GIMT_Encode2(AMDGPU::VGPR_32RegClassID),
        GIM_RecordInsn, /*DefineMI*/1, /*MI*/0, /*OpIdx*/1, // MIs[1]
        GIM_CheckOpcode, /*MI*/1, GIMT_Encode2(TargetOpcode::G_FMINNUM),
        GIM_CheckType, /*MI*/1, /*Op*/1, /*Type*/GILLT_s16,
        GIM_CheckType, /*MI*/1, /*Op*/2, /*Type*/GILLT_s16,
        GIM_RecordInsn, /*DefineMI*/2, /*MI*/0, /*OpIdx*/2, // MIs[2]
        GIM_CheckOpcode, /*MI*/2, GIMT_Encode2(TargetOpcode::G_FMINNUM),
        GIM_CheckType, /*MI*/2, /*Op*/1, /*Type*/GILLT_s16,
        GIM_CheckType, /*MI*/2, /*Op*/2, /*Type*/GILLT_s16,
        GIM_RecordInsn, /*DefineMI*/3, /*MI*/2, /*OpIdx*/1, // MIs[3]
        GIM_CheckOpcode, /*MI*/3, GIMT_Encode2(TargetOpcode::G_FMAXNUM),
        // MIs[3] VOP3Mods:src1:src1_mods
        GIM_CheckIsSameOperand, /*MI*/3, /*OpIdx*/1, /*OtherMI*/1, /*OtherOpIdx*/2,
        // MIs[3] VOP3Mods:src0:src0_mods
        GIM_CheckIsSameOperand, /*MI*/3, /*OpIdx*/2, /*OtherMI*/1, /*OtherOpIdx*/1,
        GIM_CheckCxxInsnPredicate, /*MI*/0, /*FnId*/GIMT_Encode2(GICXXPred_MI_Predicate_fmaxnum_like_nnan),
        GIM_CheckIsSafeToFold, /*InsnID*/1,
        GIM_CheckIsSafeToFold, /*InsnID*/2,
        GIM_CheckIsSafeToFold, /*InsnID*/3,
        GIM_CheckComplexPattern, /*MI*/1, /*Op*/1, /*Renderer*/GIMT_Encode2(0), GIMT_Encode2(GICP_gi_vop3mods),
        GIM_CheckComplexPattern, /*MI*/1, /*Op*/2, /*Renderer*/GIMT_Encode2(1), GIMT_Encode2(GICP_gi_vop3mods),
        GIM_CheckComplexPattern, /*MI*/2, /*Op*/2, /*Renderer*/GIMT_Encode2(2), GIMT_Encode2(GICP_gi_vop3mods),
        // (fmaxnum:{ *:[f16] } (fminnum:{ *:[f16] } (VOP3Mods:{ *:[f16] } f16:{ *:[f16] }:$src0, i32:{ *:[i32] }:$src0_mods), (VOP3Mods:{ *:[f16] } f16:{ *:[f16] }:$src1, i32:{ *:[i32] }:$src1_mods)), (fminnum:{ *:[f16] } (fmaxnum:{ *:[f16] } (VOP3Mods:{ *:[f16] } f16:{ *:[f16] }:$src1, i32:{ *:[i32] }:$src1_mods), (VOP3Mods:{ *:[f16] } f16:{ *:[f16] }:$src0, i32:{ *:[i32] }:$src0_mods)), (VOP3Mods:{ *:[f16] } f16:{ *:[f16] }:$src2, i32:{ *:[i32] }:$src2_mods)))<<P:Predicate_fmaxnum_like_nnan>>  =>  (V_MED3_F16_e64:{ *:[f16] } ?:{ *:[i32] }:$src0_mods, ?:{ *:[f16] }:$src0, ?:{ *:[i32] }:$src1_mods, ?:{ *:[f16] }:$src1, ?:{ *:[i32] }:$src2_mods, ?:{ *:[f16] }:$src2, 0:{ *:[i1] })
        GIR_BuildMI, /*InsnID*/0, /*Opcode*/GIMT_Encode2(AMDGPU::V_MED3_F16_e64),
        GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/0, // DstI[vdst]
        GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/1, // src0_mods
        GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/0, // src0
        GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(1), /*SubOperand*/1, // src1_mods
        GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(1), /*SubOperand*/0, // src1
        GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(2), /*SubOperand*/1, // src2_mods
        GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(2), /*SubOperand*/0, // src2
        GIR_AddImm8, /*InsnID*/0, /*Imm*/0,
        GIR_AddImm8, /*InsnID*/0, /*Imm*/0,
        GIR_AddImm8, /*InsnID*/0, /*Imm*/0,
        GIR_ConstrainSelectedInstOperands, /*InsnID*/0,
        GIR_EraseFromParent, /*InsnID*/0,
        // GIR_Coverage, 10755,
        GIR_Done,
      // Label 4481: @289584
      GIM_Try, /*On fail goto*//*Label 4482*/ GIMT_Encode4(289730), // Rule ID 10758 //
        GIM_CheckFeatures, GIMT_Encode2(GIFBS_isGFX9Plus),
        GIM_CheckRegBankForClass, /*MI*/0, /*Op*/0, /*RC*/GIMT_Encode2(AMDGPU::VGPR_32RegClassID),
        GIM_RecordInsn, /*DefineMI*/1, /*MI*/0, /*OpIdx*/1, // MIs[1]
        GIM_CheckOpcode, /*MI*/1, GIMT_Encode2(TargetOpcode::G_FMINNUM),
        GIM_CheckType, /*MI*/1, /*Op*/1, /*Type*/GILLT_s16,
        GIM_CheckType, /*MI*/1, /*Op*/2, /*Type*/GILLT_s16,
        GIM_RecordInsn, /*DefineMI*/2, /*MI*/0, /*OpIdx*/2, // MIs[2]
        GIM_CheckOpcode, /*MI*/2, GIMT_Encode2(TargetOpcode::G_FMINNUM),
        GIM_CheckType, /*MI*/2, /*Op*/1, /*Type*/GILLT_s16,
        GIM_CheckType, /*MI*/2, /*Op*/2, /*Type*/GILLT_s16,
        GIM_RecordInsn, /*DefineMI*/3, /*MI*/2, /*OpIdx*/1, // MIs[3]
        GIM_CheckOpcode, /*MI*/3, GIMT_Encode2(TargetOpcode::G_FMAXNUM),
        // MIs[3] VOP3Mods:src0:src0_mods
        GIM_CheckIsSameOperand, /*MI*/3, /*OpIdx*/1, /*OtherMI*/1, /*OtherOpIdx*/2,
        // MIs[3] VOP3Mods:src1:src1_mods
        GIM_CheckIsSameOperand, /*MI*/3, /*OpIdx*/2, /*OtherMI*/1, /*OtherOpIdx*/1,
        GIM_CheckCxxInsnPredicate, /*MI*/0, /*FnId*/GIMT_Encode2(GICXXPred_MI_Predicate_fmaxnum_like_nnan),
        GIM_CheckIsSafeToFold, /*InsnID*/1,
        GIM_CheckIsSafeToFold, /*InsnID*/2,
        GIM_CheckIsSafeToFold, /*InsnID*/3,
        GIM_CheckComplexPattern, /*MI*/1, /*Op*/1, /*Renderer*/GIMT_Encode2(0), GIMT_Encode2(GICP_gi_vop3mods),
        GIM_CheckComplexPattern, /*MI*/1, /*Op*/2, /*Renderer*/GIMT_Encode2(1), GIMT_Encode2(GICP_gi_vop3mods),
        GIM_CheckComplexPattern, /*MI*/2, /*Op*/2, /*Renderer*/GIMT_Encode2(2), GIMT_Encode2(GICP_gi_vop3mods),
        // (fmaxnum:{ *:[f16] } (fminnum:{ *:[f16] } (VOP3Mods:{ *:[f16] } f16:{ *:[f16] }:$src1, i32:{ *:[i32] }:$src1_mods), (VOP3Mods:{ *:[f16] } f16:{ *:[f16] }:$src0, i32:{ *:[i32] }:$src0_mods)), (fminnum:{ *:[f16] } (fmaxnum:{ *:[f16] } (VOP3Mods:{ *:[f16] } f16:{ *:[f16] }:$src0, i32:{ *:[i32] }:$src0_mods), (VOP3Mods:{ *:[f16] } f16:{ *:[f16] }:$src1, i32:{ *:[i32] }:$src1_mods)), (VOP3Mods:{ *:[f16] } f16:{ *:[f16] }:$src2, i32:{ *:[i32] }:$src2_mods)))<<P:Predicate_fmaxnum_like_nnan>>  =>  (V_MED3_F16_e64:{ *:[f16] } ?:{ *:[i32] }:$src0_mods, ?:{ *:[f16] }:$src0, ?:{ *:[i32] }:$src1_mods, ?:{ *:[f16] }:$src1, ?:{ *:[i32] }:$src2_mods, ?:{ *:[f16] }:$src2, 0:{ *:[i1] })
        GIR_BuildMI, /*InsnID*/0, /*Opcode*/GIMT_Encode2(AMDGPU::V_MED3_F16_e64),
        GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/0, // DstI[vdst]
        GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(1), /*SubOperand*/1, // src0_mods
        GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(1), /*SubOperand*/0, // src0
        GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/1, // src1_mods
        GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/0, // src1
        GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(2), /*SubOperand*/1, // src2_mods
        GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(2), /*SubOperand*/0, // src2
        GIR_AddImm8, /*InsnID*/0, /*Imm*/0,
        GIR_AddImm8, /*InsnID*/0, /*Imm*/0,
        GIR_AddImm8, /*InsnID*/0, /*Imm*/0,
        GIR_ConstrainSelectedInstOperands, /*InsnID*/0,
        GIR_EraseFromParent, /*InsnID*/0,
        // GIR_Coverage, 10758,
        GIR_Done,
      // Label 4482: @289730
      GIM_Try, /*On fail goto*//*Label 4483*/ GIMT_Encode4(289876), // Rule ID 10759 //
        GIM_CheckFeatures, GIMT_Encode2(GIFBS_isGFX9Plus),
        GIM_CheckRegBankForClass, /*MI*/0, /*Op*/0, /*RC*/GIMT_Encode2(AMDGPU::VGPR_32RegClassID),
        GIM_RecordInsn, /*DefineMI*/1, /*MI*/0, /*OpIdx*/1, // MIs[1]
        GIM_CheckOpcode, /*MI*/1, GIMT_Encode2(TargetOpcode::G_FMINNUM),
        GIM_CheckType, /*MI*/1, /*Op*/1, /*Type*/GILLT_s16,
        GIM_CheckType, /*MI*/1, /*Op*/2, /*Type*/GILLT_s16,
        GIM_RecordInsn, /*DefineMI*/2, /*MI*/0, /*OpIdx*/2, // MIs[2]
        GIM_CheckOpcode, /*MI*/2, GIMT_Encode2(TargetOpcode::G_FMINNUM),
        GIM_CheckType, /*MI*/2, /*Op*/1, /*Type*/GILLT_s16,
        GIM_CheckType, /*MI*/2, /*Op*/2, /*Type*/GILLT_s16,
        GIM_RecordInsn, /*DefineMI*/3, /*MI*/2, /*OpIdx*/1, // MIs[3]
        GIM_CheckOpcode, /*MI*/3, GIMT_Encode2(TargetOpcode::G_FMAXNUM),
        // MIs[3] VOP3Mods:src1:src1_mods
        GIM_CheckIsSameOperand, /*MI*/3, /*OpIdx*/1, /*OtherMI*/1, /*OtherOpIdx*/1,
        // MIs[3] VOP3Mods:src0:src0_mods
        GIM_CheckIsSameOperand, /*MI*/3, /*OpIdx*/2, /*OtherMI*/1, /*OtherOpIdx*/2,
        GIM_CheckCxxInsnPredicate, /*MI*/0, /*FnId*/GIMT_Encode2(GICXXPred_MI_Predicate_fmaxnum_like_nnan),
        GIM_CheckIsSafeToFold, /*InsnID*/1,
        GIM_CheckIsSafeToFold, /*InsnID*/2,
        GIM_CheckIsSafeToFold, /*InsnID*/3,
        GIM_CheckComplexPattern, /*MI*/1, /*Op*/1, /*Renderer*/GIMT_Encode2(0), GIMT_Encode2(GICP_gi_vop3mods),
        GIM_CheckComplexPattern, /*MI*/1, /*Op*/2, /*Renderer*/GIMT_Encode2(1), GIMT_Encode2(GICP_gi_vop3mods),
        GIM_CheckComplexPattern, /*MI*/2, /*Op*/2, /*Renderer*/GIMT_Encode2(2), GIMT_Encode2(GICP_gi_vop3mods),
        // (fmaxnum:{ *:[f16] } (fminnum:{ *:[f16] } (VOP3Mods:{ *:[f16] } f16:{ *:[f16] }:$src1, i32:{ *:[i32] }:$src1_mods), (VOP3Mods:{ *:[f16] } f16:{ *:[f16] }:$src0, i32:{ *:[i32] }:$src0_mods)), (fminnum:{ *:[f16] } (fmaxnum:{ *:[f16] } (VOP3Mods:{ *:[f16] } f16:{ *:[f16] }:$src1, i32:{ *:[i32] }:$src1_mods), (VOP3Mods:{ *:[f16] } f16:{ *:[f16] }:$src0, i32:{ *:[i32] }:$src0_mods)), (VOP3Mods:{ *:[f16] } f16:{ *:[f16] }:$src2, i32:{ *:[i32] }:$src2_mods)))<<P:Predicate_fmaxnum_like_nnan>>  =>  (V_MED3_F16_e64:{ *:[f16] } ?:{ *:[i32] }:$src0_mods, ?:{ *:[f16] }:$src0, ?:{ *:[i32] }:$src1_mods, ?:{ *:[f16] }:$src1, ?:{ *:[i32] }:$src2_mods, ?:{ *:[f16] }:$src2, 0:{ *:[i1] })
        GIR_BuildMI, /*InsnID*/0, /*Opcode*/GIMT_Encode2(AMDGPU::V_MED3_F16_e64),
        GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/0, // DstI[vdst]
        GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(1), /*SubOperand*/1, // src0_mods
        GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(1), /*SubOperand*/0, // src0
        GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/1, // src1_mods
        GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/0, // src1
        GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(2), /*SubOperand*/1, // src2_mods
        GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(2), /*SubOperand*/0, // src2
        GIR_AddImm8, /*InsnID*/0, /*Imm*/0,
        GIR_AddImm8, /*InsnID*/0, /*Imm*/0,
        GIR_AddImm8, /*InsnID*/0, /*Imm*/0,
        GIR_ConstrainSelectedInstOperands, /*InsnID*/0,
        GIR_EraseFromParent, /*InsnID*/0,
        // GIR_Coverage, 10759,
        GIR_Done,
      // Label 4483: @289876
      GIM_Try, /*On fail goto*//*Label 4484*/ GIMT_Encode4(290022), // Rule ID 6550 //
        GIM_CheckFeatures, GIMT_Encode2(GIFBS_isGFX9Plus),
        GIM_CheckRegBankForClass, /*MI*/0, /*Op*/0, /*RC*/GIMT_Encode2(AMDGPU::VGPR_32RegClassID),
        GIM_RecordInsn, /*DefineMI*/1, /*MI*/0, /*OpIdx*/1, // MIs[1]
        GIM_CheckOpcode, /*MI*/1, GIMT_Encode2(TargetOpcode::G_FMINNUM),
        GIM_CheckType, /*MI*/1, /*Op*/1, /*Type*/GILLT_s16,
        GIM_CheckType, /*MI*/1, /*Op*/2, /*Type*/GILLT_s16,
        GIM_RecordInsn, /*DefineMI*/2, /*MI*/0, /*OpIdx*/2, // MIs[2]
        GIM_CheckOpcode, /*MI*/2, GIMT_Encode2(TargetOpcode::G_FMINNUM),
        GIM_CheckType, /*MI*/2, /*Op*/1, /*Type*/GILLT_s16,
        GIM_CheckType, /*MI*/2, /*Op*/2, /*Type*/GILLT_s16,
        GIM_RecordInsn, /*DefineMI*/3, /*MI*/2, /*OpIdx*/1, // MIs[3]
        GIM_CheckOpcode, /*MI*/3, GIMT_Encode2(TargetOpcode::G_FMAXNUM_IEEE),
        // MIs[3] VOP3Mods:src0:src0_mods
        GIM_CheckIsSameOperand, /*MI*/3, /*OpIdx*/1, /*OtherMI*/1, /*OtherOpIdx*/1,
        // MIs[3] VOP3Mods:src1:src1_mods
        GIM_CheckIsSameOperand, /*MI*/3, /*OpIdx*/2, /*OtherMI*/1, /*OtherOpIdx*/2,
        GIM_CheckCxxInsnPredicate, /*MI*/0, /*FnId*/GIMT_Encode2(GICXXPred_MI_Predicate_fmaxnum_like_nnan),
        GIM_CheckIsSafeToFold, /*InsnID*/1,
        GIM_CheckIsSafeToFold, /*InsnID*/2,
        GIM_CheckIsSafeToFold, /*InsnID*/3,
        GIM_CheckComplexPattern, /*MI*/1, /*Op*/1, /*Renderer*/GIMT_Encode2(0), GIMT_Encode2(GICP_gi_vop3mods),
        GIM_CheckComplexPattern, /*MI*/1, /*Op*/2, /*Renderer*/GIMT_Encode2(1), GIMT_Encode2(GICP_gi_vop3mods),
        GIM_CheckComplexPattern, /*MI*/2, /*Op*/2, /*Renderer*/GIMT_Encode2(2), GIMT_Encode2(GICP_gi_vop3mods),
        // (fmaxnum:{ *:[f16] } (fminnum:{ *:[f16] } (VOP3Mods:{ *:[f16] } f16:{ *:[f16] }:$src0, i32:{ *:[i32] }:$src0_mods), (VOP3Mods:{ *:[f16] } f16:{ *:[f16] }:$src1, i32:{ *:[i32] }:$src1_mods)), (fminnum:{ *:[f16] } (fmaxnum_ieee:{ *:[f16] } (VOP3Mods:{ *:[f16] } f16:{ *:[f16] }:$src0, i32:{ *:[i32] }:$src0_mods), (VOP3Mods:{ *:[f16] } f16:{ *:[f16] }:$src1, i32:{ *:[i32] }:$src1_mods)), (VOP3Mods:{ *:[f16] } f16:{ *:[f16] }:$src2, i32:{ *:[i32] }:$src2_mods)))<<P:Predicate_fmaxnum_like_nnan>>  =>  (V_MED3_F16_e64:{ *:[f16] } ?:{ *:[i32] }:$src0_mods, ?:{ *:[f16] }:$src0, ?:{ *:[i32] }:$src1_mods, ?:{ *:[f16] }:$src1, ?:{ *:[i32] }:$src2_mods, ?:{ *:[f16] }:$src2, 0:{ *:[i1] })
        GIR_BuildMI, /*InsnID*/0, /*Opcode*/GIMT_Encode2(AMDGPU::V_MED3_F16_e64),
        GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/0, // DstI[vdst]
        GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/1, // src0_mods
        GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/0, // src0
        GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(1), /*SubOperand*/1, // src1_mods
        GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(1), /*SubOperand*/0, // src1
        GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(2), /*SubOperand*/1, // src2_mods
        GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(2), /*SubOperand*/0, // src2
        GIR_AddImm8, /*InsnID*/0, /*Imm*/0,
        GIR_AddImm8, /*InsnID*/0, /*Imm*/0,
        GIR_AddImm8, /*InsnID*/0, /*Imm*/0,
        GIR_ConstrainSelectedInstOperands, /*InsnID*/0,
        GIR_EraseFromParent, /*InsnID*/0,
        // GIR_Coverage, 6550,
        GIR_Done,
      // Label 4484: @290022
      GIM_Try, /*On fail goto*//*Label 4485*/ GIMT_Encode4(290168), // Rule ID 10740 //
        GIM_CheckFeatures, GIMT_Encode2(GIFBS_isGFX9Plus),
        GIM_CheckRegBankForClass, /*MI*/0, /*Op*/0, /*RC*/GIMT_Encode2(AMDGPU::VGPR_32RegClassID),
        GIM_RecordInsn, /*DefineMI*/1, /*MI*/0, /*OpIdx*/1, // MIs[1]
        GIM_CheckOpcode, /*MI*/1, GIMT_Encode2(TargetOpcode::G_FMINNUM),
        GIM_CheckType, /*MI*/1, /*Op*/1, /*Type*/GILLT_s16,
        GIM_CheckType, /*MI*/1, /*Op*/2, /*Type*/GILLT_s16,
        GIM_RecordInsn, /*DefineMI*/2, /*MI*/0, /*OpIdx*/2, // MIs[2]
        GIM_CheckOpcode, /*MI*/2, GIMT_Encode2(TargetOpcode::G_FMINNUM),
        GIM_CheckType, /*MI*/2, /*Op*/1, /*Type*/GILLT_s16,
        GIM_CheckType, /*MI*/2, /*Op*/2, /*Type*/GILLT_s16,
        GIM_RecordInsn, /*DefineMI*/3, /*MI*/2, /*OpIdx*/1, // MIs[3]
        GIM_CheckOpcode, /*MI*/3, GIMT_Encode2(TargetOpcode::G_FMAXNUM_IEEE),
        // MIs[3] VOP3Mods:src1:src1_mods
        GIM_CheckIsSameOperand, /*MI*/3, /*OpIdx*/1, /*OtherMI*/1, /*OtherOpIdx*/2,
        // MIs[3] VOP3Mods:src0:src0_mods
        GIM_CheckIsSameOperand, /*MI*/3, /*OpIdx*/2, /*OtherMI*/1, /*OtherOpIdx*/1,
        GIM_CheckCxxInsnPredicate, /*MI*/0, /*FnId*/GIMT_Encode2(GICXXPred_MI_Predicate_fmaxnum_like_nnan),
        GIM_CheckIsSafeToFold, /*InsnID*/1,
        GIM_CheckIsSafeToFold, /*InsnID*/2,
        GIM_CheckIsSafeToFold, /*InsnID*/3,
        GIM_CheckComplexPattern, /*MI*/1, /*Op*/1, /*Renderer*/GIMT_Encode2(0), GIMT_Encode2(GICP_gi_vop3mods),
        GIM_CheckComplexPattern, /*MI*/1, /*Op*/2, /*Renderer*/GIMT_Encode2(1), GIMT_Encode2(GICP_gi_vop3mods),
        GIM_CheckComplexPattern, /*MI*/2, /*Op*/2, /*Renderer*/GIMT_Encode2(2), GIMT_Encode2(GICP_gi_vop3mods),
        // (fmaxnum:{ *:[f16] } (fminnum:{ *:[f16] } (VOP3Mods:{ *:[f16] } f16:{ *:[f16] }:$src0, i32:{ *:[i32] }:$src0_mods), (VOP3Mods:{ *:[f16] } f16:{ *:[f16] }:$src1, i32:{ *:[i32] }:$src1_mods)), (fminnum:{ *:[f16] } (fmaxnum_ieee:{ *:[f16] } (VOP3Mods:{ *:[f16] } f16:{ *:[f16] }:$src1, i32:{ *:[i32] }:$src1_mods), (VOP3Mods:{ *:[f16] } f16:{ *:[f16] }:$src0, i32:{ *:[i32] }:$src0_mods)), (VOP3Mods:{ *:[f16] } f16:{ *:[f16] }:$src2, i32:{ *:[i32] }:$src2_mods)))<<P:Predicate_fmaxnum_like_nnan>>  =>  (V_MED3_F16_e64:{ *:[f16] } ?:{ *:[i32] }:$src0_mods, ?:{ *:[f16] }:$src0, ?:{ *:[i32] }:$src1_mods, ?:{ *:[f16] }:$src1, ?:{ *:[i32] }:$src2_mods, ?:{ *:[f16] }:$src2, 0:{ *:[i1] })
        GIR_BuildMI, /*InsnID*/0, /*Opcode*/GIMT_Encode2(AMDGPU::V_MED3_F16_e64),
        GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/0, // DstI[vdst]
        GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/1, // src0_mods
        GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/0, // src0
        GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(1), /*SubOperand*/1, // src1_mods
        GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(1), /*SubOperand*/0, // src1
        GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(2), /*SubOperand*/1, // src2_mods
        GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(2), /*SubOperand*/0, // src2
        GIR_AddImm8, /*InsnID*/0, /*Imm*/0,
        GIR_AddImm8, /*InsnID*/0, /*Imm*/0,
        GIR_AddImm8, /*InsnID*/0, /*Imm*/0,
        GIR_ConstrainSelectedInstOperands, /*InsnID*/0,
        GIR_EraseFromParent, /*InsnID*/0,
        // GIR_Coverage, 10740,
        GIR_Done,
      // Label 4485: @290168
      GIM_Try, /*On fail goto*//*Label 4486*/ GIMT_Encode4(290314), // Rule ID 10743 //
        GIM_CheckFeatures, GIMT_Encode2(GIFBS_isGFX9Plus),
        GIM_CheckRegBankForClass, /*MI*/0, /*Op*/0, /*RC*/GIMT_Encode2(AMDGPU::VGPR_32RegClassID),
        GIM_RecordInsn, /*DefineMI*/1, /*MI*/0, /*OpIdx*/1, // MIs[1]
        GIM_CheckOpcode, /*MI*/1, GIMT_Encode2(TargetOpcode::G_FMINNUM),
        GIM_CheckType, /*MI*/1, /*Op*/1, /*Type*/GILLT_s16,
        GIM_CheckType, /*MI*/1, /*Op*/2, /*Type*/GILLT_s16,
        GIM_RecordInsn, /*DefineMI*/2, /*MI*/0, /*OpIdx*/2, // MIs[2]
        GIM_CheckOpcode, /*MI*/2, GIMT_Encode2(TargetOpcode::G_FMINNUM),
        GIM_CheckType, /*MI*/2, /*Op*/1, /*Type*/GILLT_s16,
        GIM_CheckType, /*MI*/2, /*Op*/2, /*Type*/GILLT_s16,
        GIM_RecordInsn, /*DefineMI*/3, /*MI*/2, /*OpIdx*/1, // MIs[3]
        GIM_CheckOpcode, /*MI*/3, GIMT_Encode2(TargetOpcode::G_FMAXNUM_IEEE),
        // MIs[3] VOP3Mods:src0:src0_mods
        GIM_CheckIsSameOperand, /*MI*/3, /*OpIdx*/1, /*OtherMI*/1, /*OtherOpIdx*/2,
        // MIs[3] VOP3Mods:src1:src1_mods
        GIM_CheckIsSameOperand, /*MI*/3, /*OpIdx*/2, /*OtherMI*/1, /*OtherOpIdx*/1,
        GIM_CheckCxxInsnPredicate, /*MI*/0, /*FnId*/GIMT_Encode2(GICXXPred_MI_Predicate_fmaxnum_like_nnan),
        GIM_CheckIsSafeToFold, /*InsnID*/1,
        GIM_CheckIsSafeToFold, /*InsnID*/2,
        GIM_CheckIsSafeToFold, /*InsnID*/3,
        GIM_CheckComplexPattern, /*MI*/1, /*Op*/1, /*Renderer*/GIMT_Encode2(0), GIMT_Encode2(GICP_gi_vop3mods),
        GIM_CheckComplexPattern, /*MI*/1, /*Op*/2, /*Renderer*/GIMT_Encode2(1), GIMT_Encode2(GICP_gi_vop3mods),
        GIM_CheckComplexPattern, /*MI*/2, /*Op*/2, /*Renderer*/GIMT_Encode2(2), GIMT_Encode2(GICP_gi_vop3mods),
        // (fmaxnum:{ *:[f16] } (fminnum:{ *:[f16] } (VOP3Mods:{ *:[f16] } f16:{ *:[f16] }:$src1, i32:{ *:[i32] }:$src1_mods), (VOP3Mods:{ *:[f16] } f16:{ *:[f16] }:$src0, i32:{ *:[i32] }:$src0_mods)), (fminnum:{ *:[f16] } (fmaxnum_ieee:{ *:[f16] } (VOP3Mods:{ *:[f16] } f16:{ *:[f16] }:$src0, i32:{ *:[i32] }:$src0_mods), (VOP3Mods:{ *:[f16] } f16:{ *:[f16] }:$src1, i32:{ *:[i32] }:$src1_mods)), (VOP3Mods:{ *:[f16] } f16:{ *:[f16] }:$src2, i32:{ *:[i32] }:$src2_mods)))<<P:Predicate_fmaxnum_like_nnan>>  =>  (V_MED3_F16_e64:{ *:[f16] } ?:{ *:[i32] }:$src0_mods, ?:{ *:[f16] }:$src0, ?:{ *:[i32] }:$src1_mods, ?:{ *:[f16] }:$src1, ?:{ *:[i32] }:$src2_mods, ?:{ *:[f16] }:$src2, 0:{ *:[i1] })
        GIR_BuildMI, /*InsnID*/0, /*Opcode*/GIMT_Encode2(AMDGPU::V_MED3_F16_e64),
        GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/0, // DstI[vdst]
        GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(1), /*SubOperand*/1, // src0_mods
        GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(1), /*SubOperand*/0, // src0
        GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/1, // src1_mods
        GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/0, // src1
        GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(2), /*SubOperand*/1, // src2_mods
        GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(2), /*SubOperand*/0, // src2
        GIR_AddImm8, /*InsnID*/0, /*Imm*/0,
        GIR_AddImm8, /*InsnID*/0, /*Imm*/0,
        GIR_AddImm8, /*InsnID*/0, /*Imm*/0,
        GIR_ConstrainSelectedInstOperands, /*InsnID*/0,
        GIR_EraseFromParent, /*InsnID*/0,
        // GIR_Coverage, 10743,
        GIR_Done,
      // Label 4486: @290314
      GIM_Try, /*On fail goto*//*Label 4487*/ GIMT_Encode4(290460), // Rule ID 10744 //
        GIM_CheckFeatures, GIMT_Encode2(GIFBS_isGFX9Plus),
        GIM_CheckRegBankForClass, /*MI*/0, /*Op*/0, /*RC*/GIMT_Encode2(AMDGPU::VGPR_32RegClassID),
        GIM_RecordInsn, /*DefineMI*/1, /*MI*/0, /*OpIdx*/1, // MIs[1]
        GIM_CheckOpcode, /*MI*/1, GIMT_Encode2(TargetOpcode::G_FMINNUM),
        GIM_CheckType, /*MI*/1, /*Op*/1, /*Type*/GILLT_s16,
        GIM_CheckType, /*MI*/1, /*Op*/2, /*Type*/GILLT_s16,
        GIM_RecordInsn, /*DefineMI*/2, /*MI*/0, /*OpIdx*/2, // MIs[2]
        GIM_CheckOpcode, /*MI*/2, GIMT_Encode2(TargetOpcode::G_FMINNUM),
        GIM_CheckType, /*MI*/2, /*Op*/1, /*Type*/GILLT_s16,
        GIM_CheckType, /*MI*/2, /*Op*/2, /*Type*/GILLT_s16,
        GIM_RecordInsn, /*DefineMI*/3, /*MI*/2, /*OpIdx*/1, // MIs[3]
        GIM_CheckOpcode, /*MI*/3, GIMT_Encode2(TargetOpcode::G_FMAXNUM_IEEE),
        // MIs[3] VOP3Mods:src1:src1_mods
        GIM_CheckIsSameOperand, /*MI*/3, /*OpIdx*/1, /*OtherMI*/1, /*OtherOpIdx*/1,
        // MIs[3] VOP3Mods:src0:src0_mods
        GIM_CheckIsSameOperand, /*MI*/3, /*OpIdx*/2, /*OtherMI*/1, /*OtherOpIdx*/2,
        GIM_CheckCxxInsnPredicate, /*MI*/0, /*FnId*/GIMT_Encode2(GICXXPred_MI_Predicate_fmaxnum_like_nnan),
        GIM_CheckIsSafeToFold, /*InsnID*/1,
        GIM_CheckIsSafeToFold, /*InsnID*/2,
        GIM_CheckIsSafeToFold, /*InsnID*/3,
        GIM_CheckComplexPattern, /*MI*/1, /*Op*/1, /*Renderer*/GIMT_Encode2(0), GIMT_Encode2(GICP_gi_vop3mods),
        GIM_CheckComplexPattern, /*MI*/1, /*Op*/2, /*Renderer*/GIMT_Encode2(1), GIMT_Encode2(GICP_gi_vop3mods),
        GIM_CheckComplexPattern, /*MI*/2, /*Op*/2, /*Renderer*/GIMT_Encode2(2), GIMT_Encode2(GICP_gi_vop3mods),
        // (fmaxnum:{ *:[f16] } (fminnum:{ *:[f16] } (VOP3Mods:{ *:[f16] } f16:{ *:[f16] }:$src1, i32:{ *:[i32] }:$src1_mods), (VOP3Mods:{ *:[f16] } f16:{ *:[f16] }:$src0, i32:{ *:[i32] }:$src0_mods)), (fminnum:{ *:[f16] } (fmaxnum_ieee:{ *:[f16] } (VOP3Mods:{ *:[f16] } f16:{ *:[f16] }:$src1, i32:{ *:[i32] }:$src1_mods), (VOP3Mods:{ *:[f16] } f16:{ *:[f16] }:$src0, i32:{ *:[i32] }:$src0_mods)), (VOP3Mods:{ *:[f16] } f16:{ *:[f16] }:$src2, i32:{ *:[i32] }:$src2_mods)))<<P:Predicate_fmaxnum_like_nnan>>  =>  (V_MED3_F16_e64:{ *:[f16] } ?:{ *:[i32] }:$src0_mods, ?:{ *:[f16] }:$src0, ?:{ *:[i32] }:$src1_mods, ?:{ *:[f16] }:$src1, ?:{ *:[i32] }:$src2_mods, ?:{ *:[f16] }:$src2, 0:{ *:[i1] })
        GIR_BuildMI, /*InsnID*/0, /*Opcode*/GIMT_Encode2(AMDGPU::V_MED3_F16_e64),
        GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/0, // DstI[vdst]
        GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(1), /*SubOperand*/1, // src0_mods
        GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(1), /*SubOperand*/0, // src0
        GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/1, // src1_mods
        GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/0, // src1
        GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(2), /*SubOperand*/1, // src2_mods
        GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(2), /*SubOperand*/0, // src2
        GIR_AddImm8, /*InsnID*/0, /*Imm*/0,
        GIR_AddImm8, /*InsnID*/0, /*Imm*/0,
        GIR_AddImm8, /*InsnID*/0, /*Imm*/0,
        GIR_ConstrainSelectedInstOperands, /*InsnID*/0,
        GIR_EraseFromParent, /*InsnID*/0,
        // GIR_Coverage, 10744,
        GIR_Done,
      // Label 4487: @290460
      GIM_Try, /*On fail goto*//*Label 4488*/ GIMT_Encode4(290606), // Rule ID 10726 //
        GIM_CheckFeatures, GIMT_Encode2(GIFBS_isGFX9Plus),
        GIM_CheckRegBankForClass, /*MI*/0, /*Op*/0, /*RC*/GIMT_Encode2(AMDGPU::VGPR_32RegClassID),
        GIM_RecordInsn, /*DefineMI*/1, /*MI*/0, /*OpIdx*/1, // MIs[1]
        GIM_CheckOpcode, /*MI*/1, GIMT_Encode2(TargetOpcode::G_FMINNUM),
        GIM_CheckType, /*MI*/1, /*Op*/1, /*Type*/GILLT_s16,
        GIM_CheckType, /*MI*/1, /*Op*/2, /*Type*/GILLT_s16,
        GIM_RecordInsn, /*DefineMI*/2, /*MI*/0, /*OpIdx*/2, // MIs[2]
        GIM_CheckOpcode, /*MI*/2, GIMT_Encode2(TargetOpcode::G_FMINNUM_IEEE),
        GIM_CheckType, /*MI*/2, /*Op*/1, /*Type*/GILLT_s16,
        GIM_CheckType, /*MI*/2, /*Op*/2, /*Type*/GILLT_s16,
        GIM_RecordInsn, /*DefineMI*/3, /*MI*/2, /*OpIdx*/2, // MIs[3]
        GIM_CheckOpcode, /*MI*/3, GIMT_Encode2(TargetOpcode::G_FMAXNUM),
        // MIs[3] VOP3Mods:src0:src0_mods
        GIM_CheckIsSameOperand, /*MI*/3, /*OpIdx*/1, /*OtherMI*/1, /*OtherOpIdx*/1,
        // MIs[3] VOP3Mods:src1:src1_mods
        GIM_CheckIsSameOperand, /*MI*/3, /*OpIdx*/2, /*OtherMI*/1, /*OtherOpIdx*/2,
        GIM_CheckCxxInsnPredicate, /*MI*/0, /*FnId*/GIMT_Encode2(GICXXPred_MI_Predicate_fmaxnum_like_nnan),
        GIM_CheckIsSafeToFold, /*InsnID*/1,
        GIM_CheckIsSafeToFold, /*InsnID*/2,
        GIM_CheckIsSafeToFold, /*InsnID*/3,
        GIM_CheckComplexPattern, /*MI*/1, /*Op*/1, /*Renderer*/GIMT_Encode2(0), GIMT_Encode2(GICP_gi_vop3mods),
        GIM_CheckComplexPattern, /*MI*/1, /*Op*/2, /*Renderer*/GIMT_Encode2(1), GIMT_Encode2(GICP_gi_vop3mods),
        GIM_CheckComplexPattern, /*MI*/2, /*Op*/1, /*Renderer*/GIMT_Encode2(2), GIMT_Encode2(GICP_gi_vop3mods),
        // (fmaxnum:{ *:[f16] } (fminnum:{ *:[f16] } (VOP3Mods:{ *:[f16] } f16:{ *:[f16] }:$src0, i32:{ *:[i32] }:$src0_mods), (VOP3Mods:{ *:[f16] } f16:{ *:[f16] }:$src1, i32:{ *:[i32] }:$src1_mods)), (fminnum_ieee:{ *:[f16] } (VOP3Mods:{ *:[f16] } f16:{ *:[f16] }:$src2, i32:{ *:[i32] }:$src2_mods), (fmaxnum:{ *:[f16] } (VOP3Mods:{ *:[f16] } f16:{ *:[f16] }:$src0, i32:{ *:[i32] }:$src0_mods), (VOP3Mods:{ *:[f16] } f16:{ *:[f16] }:$src1, i32:{ *:[i32] }:$src1_mods))))<<P:Predicate_fmaxnum_like_nnan>>  =>  (V_MED3_F16_e64:{ *:[f16] } ?:{ *:[i32] }:$src0_mods, ?:{ *:[f16] }:$src0, ?:{ *:[i32] }:$src1_mods, ?:{ *:[f16] }:$src1, ?:{ *:[i32] }:$src2_mods, ?:{ *:[f16] }:$src2, 0:{ *:[i1] })
        GIR_BuildMI, /*InsnID*/0, /*Opcode*/GIMT_Encode2(AMDGPU::V_MED3_F16_e64),
        GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/0, // DstI[vdst]
        GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/1, // src0_mods
        GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/0, // src0
        GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(1), /*SubOperand*/1, // src1_mods
        GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(1), /*SubOperand*/0, // src1
        GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(2), /*SubOperand*/1, // src2_mods
        GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(2), /*SubOperand*/0, // src2
        GIR_AddImm8, /*InsnID*/0, /*Imm*/0,
        GIR_AddImm8, /*InsnID*/0, /*Imm*/0,
        GIR_AddImm8, /*InsnID*/0, /*Imm*/0,
        GIR_ConstrainSelectedInstOperands, /*InsnID*/0,
        GIR_EraseFromParent, /*InsnID*/0,
        // GIR_Coverage, 10726,
        GIR_Done,
      // Label 4488: @290606
      GIM_Try, /*On fail goto*//*Label 4489*/ GIMT_Encode4(290752), // Rule ID 10727 //
        GIM_CheckFeatures, GIMT_Encode2(GIFBS_isGFX9Plus),
        GIM_CheckRegBankForClass, /*MI*/0, /*Op*/0, /*RC*/GIMT_Encode2(AMDGPU::VGPR_32RegClassID),
        GIM_RecordInsn, /*DefineMI*/1, /*MI*/0, /*OpIdx*/1, // MIs[1]
        GIM_CheckOpcode, /*MI*/1, GIMT_Encode2(TargetOpcode::G_FMINNUM),
        GIM_CheckType, /*MI*/1, /*Op*/1, /*Type*/GILLT_s16,
        GIM_CheckType, /*MI*/1, /*Op*/2, /*Type*/GILLT_s16,
        GIM_RecordInsn, /*DefineMI*/2, /*MI*/0, /*OpIdx*/2, // MIs[2]
        GIM_CheckOpcode, /*MI*/2, GIMT_Encode2(TargetOpcode::G_FMINNUM_IEEE),
        GIM_CheckType, /*MI*/2, /*Op*/1, /*Type*/GILLT_s16,
        GIM_CheckType, /*MI*/2, /*Op*/2, /*Type*/GILLT_s16,
        GIM_RecordInsn, /*DefineMI*/3, /*MI*/2, /*OpIdx*/2, // MIs[3]
        GIM_CheckOpcode, /*MI*/3, GIMT_Encode2(TargetOpcode::G_FMAXNUM),
        // MIs[3] VOP3Mods:src1:src1_mods
        GIM_CheckIsSameOperand, /*MI*/3, /*OpIdx*/1, /*OtherMI*/1, /*OtherOpIdx*/2,
        // MIs[3] VOP3Mods:src0:src0_mods
        GIM_CheckIsSameOperand, /*MI*/3, /*OpIdx*/2, /*OtherMI*/1, /*OtherOpIdx*/1,
        GIM_CheckCxxInsnPredicate, /*MI*/0, /*FnId*/GIMT_Encode2(GICXXPred_MI_Predicate_fmaxnum_like_nnan),
        GIM_CheckIsSafeToFold, /*InsnID*/1,
        GIM_CheckIsSafeToFold, /*InsnID*/2,
        GIM_CheckIsSafeToFold, /*InsnID*/3,
        GIM_CheckComplexPattern, /*MI*/1, /*Op*/1, /*Renderer*/GIMT_Encode2(0), GIMT_Encode2(GICP_gi_vop3mods),
        GIM_CheckComplexPattern, /*MI*/1, /*Op*/2, /*Renderer*/GIMT_Encode2(1), GIMT_Encode2(GICP_gi_vop3mods),
        GIM_CheckComplexPattern, /*MI*/2, /*Op*/1, /*Renderer*/GIMT_Encode2(2), GIMT_Encode2(GICP_gi_vop3mods),
        // (fmaxnum:{ *:[f16] } (fminnum:{ *:[f16] } (VOP3Mods:{ *:[f16] } f16:{ *:[f16] }:$src0, i32:{ *:[i32] }:$src0_mods), (VOP3Mods:{ *:[f16] } f16:{ *:[f16] }:$src1, i32:{ *:[i32] }:$src1_mods)), (fminnum_ieee:{ *:[f16] } (VOP3Mods:{ *:[f16] } f16:{ *:[f16] }:$src2, i32:{ *:[i32] }:$src2_mods), (fmaxnum:{ *:[f16] } (VOP3Mods:{ *:[f16] } f16:{ *:[f16] }:$src1, i32:{ *:[i32] }:$src1_mods), (VOP3Mods:{ *:[f16] } f16:{ *:[f16] }:$src0, i32:{ *:[i32] }:$src0_mods))))<<P:Predicate_fmaxnum_like_nnan>>  =>  (V_MED3_F16_e64:{ *:[f16] } ?:{ *:[i32] }:$src0_mods, ?:{ *:[f16] }:$src0, ?:{ *:[i32] }:$src1_mods, ?:{ *:[f16] }:$src1, ?:{ *:[i32] }:$src2_mods, ?:{ *:[f16] }:$src2, 0:{ *:[i1] })
        GIR_BuildMI, /*InsnID*/0, /*Opcode*/GIMT_Encode2(AMDGPU::V_MED3_F16_e64),
        GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/0, // DstI[vdst]
        GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/1, // src0_mods
        GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/0, // src0
        GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(1), /*SubOperand*/1, // src1_mods
        GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(1), /*SubOperand*/0, // src1
        GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(2), /*SubOperand*/1, // src2_mods
        GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(2), /*SubOperand*/0, // src2
        GIR_AddImm8, /*InsnID*/0, /*Imm*/0,
        GIR_AddImm8, /*InsnID*/0, /*Imm*/0,
        GIR_AddImm8, /*InsnID*/0, /*Imm*/0,
        GIR_ConstrainSelectedInstOperands, /*InsnID*/0,
        GIR_EraseFromParent, /*InsnID*/0,
        // GIR_Coverage, 10727,
        GIR_Done,
      // Label 4489: @290752
      GIM_Try, /*On fail goto*//*Label 4490*/ GIMT_Encode4(290898), // Rule ID 10730 //
        GIM_CheckFeatures, GIMT_Encode2(GIFBS_isGFX9Plus),
        GIM_CheckRegBankForClass, /*MI*/0, /*Op*/0, /*RC*/GIMT_Encode2(AMDGPU::VGPR_32RegClassID),
        GIM_RecordInsn, /*DefineMI*/1, /*MI*/0, /*OpIdx*/1, // MIs[1]
        GIM_CheckOpcode, /*MI*/1, GIMT_Encode2(TargetOpcode::G_FMINNUM),
        GIM_CheckType, /*MI*/1, /*Op*/1, /*Type*/GILLT_s16,
        GIM_CheckType, /*MI*/1, /*Op*/2, /*Type*/GILLT_s16,
        GIM_RecordInsn, /*DefineMI*/2, /*MI*/0, /*OpIdx*/2, // MIs[2]
        GIM_CheckOpcode, /*MI*/2, GIMT_Encode2(TargetOpcode::G_FMINNUM_IEEE),
        GIM_CheckType, /*MI*/2, /*Op*/1, /*Type*/GILLT_s16,
        GIM_CheckType, /*MI*/2, /*Op*/2, /*Type*/GILLT_s16,
        GIM_RecordInsn, /*DefineMI*/3, /*MI*/2, /*OpIdx*/2, // MIs[3]
        GIM_CheckOpcode, /*MI*/3, GIMT_Encode2(TargetOpcode::G_FMAXNUM),
        // MIs[3] VOP3Mods:src0:src0_mods
        GIM_CheckIsSameOperand, /*MI*/3, /*OpIdx*/1, /*OtherMI*/1, /*OtherOpIdx*/2,
        // MIs[3] VOP3Mods:src1:src1_mods
        GIM_CheckIsSameOperand, /*MI*/3, /*OpIdx*/2, /*OtherMI*/1, /*OtherOpIdx*/1,
        GIM_CheckCxxInsnPredicate, /*MI*/0, /*FnId*/GIMT_Encode2(GICXXPred_MI_Predicate_fmaxnum_like_nnan),
        GIM_CheckIsSafeToFold, /*InsnID*/1,
        GIM_CheckIsSafeToFold, /*InsnID*/2,
        GIM_CheckIsSafeToFold, /*InsnID*/3,
        GIM_CheckComplexPattern, /*MI*/1, /*Op*/1, /*Renderer*/GIMT_Encode2(0), GIMT_Encode2(GICP_gi_vop3mods),
        GIM_CheckComplexPattern, /*MI*/1, /*Op*/2, /*Renderer*/GIMT_Encode2(1), GIMT_Encode2(GICP_gi_vop3mods),
        GIM_CheckComplexPattern, /*MI*/2, /*Op*/1, /*Renderer*/GIMT_Encode2(2), GIMT_Encode2(GICP_gi_vop3mods),
        // (fmaxnum:{ *:[f16] } (fminnum:{ *:[f16] } (VOP3Mods:{ *:[f16] } f16:{ *:[f16] }:$src1, i32:{ *:[i32] }:$src1_mods), (VOP3Mods:{ *:[f16] } f16:{ *:[f16] }:$src0, i32:{ *:[i32] }:$src0_mods)), (fminnum_ieee:{ *:[f16] } (VOP3Mods:{ *:[f16] } f16:{ *:[f16] }:$src2, i32:{ *:[i32] }:$src2_mods), (fmaxnum:{ *:[f16] } (VOP3Mods:{ *:[f16] } f16:{ *:[f16] }:$src0, i32:{ *:[i32] }:$src0_mods), (VOP3Mods:{ *:[f16] } f16:{ *:[f16] }:$src1, i32:{ *:[i32] }:$src1_mods))))<<P:Predicate_fmaxnum_like_nnan>>  =>  (V_MED3_F16_e64:{ *:[f16] } ?:{ *:[i32] }:$src0_mods, ?:{ *:[f16] }:$src0, ?:{ *:[i32] }:$src1_mods, ?:{ *:[f16] }:$src1, ?:{ *:[i32] }:$src2_mods, ?:{ *:[f16] }:$src2, 0:{ *:[i1] })
        GIR_BuildMI, /*InsnID*/0, /*Opcode*/GIMT_Encode2(AMDGPU::V_MED3_F16_e64),
        GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/0, // DstI[vdst]
        GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(1), /*SubOperand*/1, // src0_mods
        GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(1), /*SubOperand*/0, // src0
        GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/1, // src1_mods
        GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/0, // src1
        GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(2), /*SubOperand*/1, // src2_mods
        GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(2), /*SubOperand*/0, // src2
        GIR_AddImm8, /*InsnID*/0, /*Imm*/0,
        GIR_AddImm8, /*InsnID*/0, /*Imm*/0,
        GIR_AddImm8, /*InsnID*/0, /*Imm*/0,
        GIR_ConstrainSelectedInstOperands, /*InsnID*/0,
        GIR_EraseFromParent, /*InsnID*/0,
        // GIR_Coverage, 10730,
        GIR_Done,
      // Label 4490: @290898
      GIM_Try, /*On fail goto*//*Label 4491*/ GIMT_Encode4(291044), // Rule ID 10731 //
        GIM_CheckFeatures, GIMT_Encode2(GIFBS_isGFX9Plus),
        GIM_CheckRegBankForClass, /*MI*/0, /*Op*/0, /*RC*/GIMT_Encode2(AMDGPU::VGPR_32RegClassID),
        GIM_RecordInsn, /*DefineMI*/1, /*MI*/0, /*OpIdx*/1, // MIs[1]
        GIM_CheckOpcode, /*MI*/1, GIMT_Encode2(TargetOpcode::G_FMINNUM),
        GIM_CheckType, /*MI*/1, /*Op*/1, /*Type*/GILLT_s16,
        GIM_CheckType, /*MI*/1, /*Op*/2, /*Type*/GILLT_s16,
        GIM_RecordInsn, /*DefineMI*/2, /*MI*/0, /*OpIdx*/2, // MIs[2]
        GIM_CheckOpcode, /*MI*/2, GIMT_Encode2(TargetOpcode::G_FMINNUM_IEEE),
        GIM_CheckType, /*MI*/2, /*Op*/1, /*Type*/GILLT_s16,
        GIM_CheckType, /*MI*/2, /*Op*/2, /*Type*/GILLT_s16,
        GIM_RecordInsn, /*DefineMI*/3, /*MI*/2, /*OpIdx*/2, // MIs[3]
        GIM_CheckOpcode, /*MI*/3, GIMT_Encode2(TargetOpcode::G_FMAXNUM),
        // MIs[3] VOP3Mods:src1:src1_mods
        GIM_CheckIsSameOperand, /*MI*/3, /*OpIdx*/1, /*OtherMI*/1, /*OtherOpIdx*/1,
        // MIs[3] VOP3Mods:src0:src0_mods
        GIM_CheckIsSameOperand, /*MI*/3, /*OpIdx*/2, /*OtherMI*/1, /*OtherOpIdx*/2,
        GIM_CheckCxxInsnPredicate, /*MI*/0, /*FnId*/GIMT_Encode2(GICXXPred_MI_Predicate_fmaxnum_like_nnan),
        GIM_CheckIsSafeToFold, /*InsnID*/1,
        GIM_CheckIsSafeToFold, /*InsnID*/2,
        GIM_CheckIsSafeToFold, /*InsnID*/3,
        GIM_CheckComplexPattern, /*MI*/1, /*Op*/1, /*Renderer*/GIMT_Encode2(0), GIMT_Encode2(GICP_gi_vop3mods),
        GIM_CheckComplexPattern, /*MI*/1, /*Op*/2, /*Renderer*/GIMT_Encode2(1), GIMT_Encode2(GICP_gi_vop3mods),
        GIM_CheckComplexPattern, /*MI*/2, /*Op*/1, /*Renderer*/GIMT_Encode2(2), GIMT_Encode2(GICP_gi_vop3mods),
        // (fmaxnum:{ *:[f16] } (fminnum:{ *:[f16] } (VOP3Mods:{ *:[f16] } f16:{ *:[f16] }:$src1, i32:{ *:[i32] }:$src1_mods), (VOP3Mods:{ *:[f16] } f16:{ *:[f16] }:$src0, i32:{ *:[i32] }:$src0_mods)), (fminnum_ieee:{ *:[f16] } (VOP3Mods:{ *:[f16] } f16:{ *:[f16] }:$src2, i32:{ *:[i32] }:$src2_mods), (fmaxnum:{ *:[f16] } (VOP3Mods:{ *:[f16] } f16:{ *:[f16] }:$src1, i32:{ *:[i32] }:$src1_mods), (VOP3Mods:{ *:[f16] } f16:{ *:[f16] }:$src0, i32:{ *:[i32] }:$src0_mods))))<<P:Predicate_fmaxnum_like_nnan>>  =>  (V_MED3_F16_e64:{ *:[f16] } ?:{ *:[i32] }:$src0_mods, ?:{ *:[f16] }:$src0, ?:{ *:[i32] }:$src1_mods, ?:{ *:[f16] }:$src1, ?:{ *:[i32] }:$src2_mods, ?:{ *:[f16] }:$src2, 0:{ *:[i1] })
        GIR_BuildMI, /*InsnID*/0, /*Opcode*/GIMT_Encode2(AMDGPU::V_MED3_F16_e64),
        GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/0, // DstI[vdst]
        GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(1), /*SubOperand*/1, // src0_mods
        GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(1), /*SubOperand*/0, // src0
        GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/1, // src1_mods
        GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/0, // src1
        GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(2), /*SubOperand*/1, // src2_mods
        GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(2), /*SubOperand*/0, // src2
        GIR_AddImm8, /*InsnID*/0, /*Imm*/0,
        GIR_AddImm8, /*InsnID*/0, /*Imm*/0,
        GIR_AddImm8, /*InsnID*/0, /*Imm*/0,
        GIR_ConstrainSelectedInstOperands, /*InsnID*/0,
        GIR_EraseFromParent, /*InsnID*/0,
        // GIR_Coverage, 10731,
        GIR_Done,
      // Label 4491: @291044
      GIM_Try, /*On fail goto*//*Label 4492*/ GIMT_Encode4(291190), // Rule ID 10711 //
        GIM_CheckFeatures, GIMT_Encode2(GIFBS_isGFX9Plus),
        GIM_CheckRegBankForClass, /*MI*/0, /*Op*/0, /*RC*/GIMT_Encode2(AMDGPU::VGPR_32RegClassID),
        GIM_RecordInsn, /*DefineMI*/1, /*MI*/0, /*OpIdx*/1, // MIs[1]
        GIM_CheckOpcode, /*MI*/1, GIMT_Encode2(TargetOpcode::G_FMINNUM),
        GIM_CheckType, /*MI*/1, /*Op*/1, /*Type*/GILLT_s16,
        GIM_CheckType, /*MI*/1, /*Op*/2, /*Type*/GILLT_s16,
        GIM_RecordInsn, /*DefineMI*/2, /*MI*/0, /*OpIdx*/2, // MIs[2]
        GIM_CheckOpcode, /*MI*/2, GIMT_Encode2(TargetOpcode::G_FMINNUM_IEEE),
        GIM_CheckType, /*MI*/2, /*Op*/1, /*Type*/GILLT_s16,
        GIM_CheckType, /*MI*/2, /*Op*/2, /*Type*/GILLT_s16,
        GIM_RecordInsn, /*DefineMI*/3, /*MI*/2, /*OpIdx*/2, // MIs[3]
        GIM_CheckOpcode, /*MI*/3, GIMT_Encode2(TargetOpcode::G_FMAXNUM_IEEE),
        // MIs[3] VOP3Mods:src0:src0_mods
        GIM_CheckIsSameOperand, /*MI*/3, /*OpIdx*/1, /*OtherMI*/1, /*OtherOpIdx*/1,
        // MIs[3] VOP3Mods:src1:src1_mods
        GIM_CheckIsSameOperand, /*MI*/3, /*OpIdx*/2, /*OtherMI*/1, /*OtherOpIdx*/2,
        GIM_CheckCxxInsnPredicate, /*MI*/0, /*FnId*/GIMT_Encode2(GICXXPred_MI_Predicate_fmaxnum_like_nnan),
        GIM_CheckIsSafeToFold, /*InsnID*/1,
        GIM_CheckIsSafeToFold, /*InsnID*/2,
        GIM_CheckIsSafeToFold, /*InsnID*/3,
        GIM_CheckComplexPattern, /*MI*/1, /*Op*/1, /*Renderer*/GIMT_Encode2(0), GIMT_Encode2(GICP_gi_vop3mods),
        GIM_CheckComplexPattern, /*MI*/1, /*Op*/2, /*Renderer*/GIMT_Encode2(1), GIMT_Encode2(GICP_gi_vop3mods),
        GIM_CheckComplexPattern, /*MI*/2, /*Op*/1, /*Renderer*/GIMT_Encode2(2), GIMT_Encode2(GICP_gi_vop3mods),
        // (fmaxnum:{ *:[f16] } (fminnum:{ *:[f16] } (VOP3Mods:{ *:[f16] } f16:{ *:[f16] }:$src0, i32:{ *:[i32] }:$src0_mods), (VOP3Mods:{ *:[f16] } f16:{ *:[f16] }:$src1, i32:{ *:[i32] }:$src1_mods)), (fminnum_ieee:{ *:[f16] } (VOP3Mods:{ *:[f16] } f16:{ *:[f16] }:$src2, i32:{ *:[i32] }:$src2_mods), (fmaxnum_ieee:{ *:[f16] } (VOP3Mods:{ *:[f16] } f16:{ *:[f16] }:$src0, i32:{ *:[i32] }:$src0_mods), (VOP3Mods:{ *:[f16] } f16:{ *:[f16] }:$src1, i32:{ *:[i32] }:$src1_mods))))<<P:Predicate_fmaxnum_like_nnan>>  =>  (V_MED3_F16_e64:{ *:[f16] } ?:{ *:[i32] }:$src0_mods, ?:{ *:[f16] }:$src0, ?:{ *:[i32] }:$src1_mods, ?:{ *:[f16] }:$src1, ?:{ *:[i32] }:$src2_mods, ?:{ *:[f16] }:$src2, 0:{ *:[i1] })
        GIR_BuildMI, /*InsnID*/0, /*Opcode*/GIMT_Encode2(AMDGPU::V_MED3_F16_e64),
        GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/0, // DstI[vdst]
        GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/1, // src0_mods
        GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/0, // src0
        GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(1), /*SubOperand*/1, // src1_mods
        GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(1), /*SubOperand*/0, // src1
        GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(2), /*SubOperand*/1, // src2_mods
        GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(2), /*SubOperand*/0, // src2
        GIR_AddImm8, /*InsnID*/0, /*Imm*/0,
        GIR_AddImm8, /*InsnID*/0, /*Imm*/0,
        GIR_AddImm8, /*InsnID*/0, /*Imm*/0,
        GIR_ConstrainSelectedInstOperands, /*InsnID*/0,
        GIR_EraseFromParent, /*InsnID*/0,
        // GIR_Coverage, 10711,
        GIR_Done,
      // Label 4492: @291190
      GIM_Try, /*On fail goto*//*Label 4493*/ GIMT_Encode4(291336), // Rule ID 10712 //
        GIM_CheckFeatures, GIMT_Encode2(GIFBS_isGFX9Plus),
        GIM_CheckRegBankForClass, /*MI*/0, /*Op*/0, /*RC*/GIMT_Encode2(AMDGPU::VGPR_32RegClassID),
        GIM_RecordInsn, /*DefineMI*/1, /*MI*/0, /*OpIdx*/1, // MIs[1]
        GIM_CheckOpcode, /*MI*/1, GIMT_Encode2(TargetOpcode::G_FMINNUM),
        GIM_CheckType, /*MI*/1, /*Op*/1, /*Type*/GILLT_s16,
        GIM_CheckType, /*MI*/1, /*Op*/2, /*Type*/GILLT_s16,
        GIM_RecordInsn, /*DefineMI*/2, /*MI*/0, /*OpIdx*/2, // MIs[2]
        GIM_CheckOpcode, /*MI*/2, GIMT_Encode2(TargetOpcode::G_FMINNUM_IEEE),
        GIM_CheckType, /*MI*/2, /*Op*/1, /*Type*/GILLT_s16,
        GIM_CheckType, /*MI*/2, /*Op*/2, /*Type*/GILLT_s16,
        GIM_RecordInsn, /*DefineMI*/3, /*MI*/2, /*OpIdx*/2, // MIs[3]
        GIM_CheckOpcode, /*MI*/3, GIMT_Encode2(TargetOpcode::G_FMAXNUM_IEEE),
        // MIs[3] VOP3Mods:src1:src1_mods
        GIM_CheckIsSameOperand, /*MI*/3, /*OpIdx*/1, /*OtherMI*/1, /*OtherOpIdx*/2,
        // MIs[3] VOP3Mods:src0:src0_mods
        GIM_CheckIsSameOperand, /*MI*/3, /*OpIdx*/2, /*OtherMI*/1, /*OtherOpIdx*/1,
        GIM_CheckCxxInsnPredicate, /*MI*/0, /*FnId*/GIMT_Encode2(GICXXPred_MI_Predicate_fmaxnum_like_nnan),
        GIM_CheckIsSafeToFold, /*InsnID*/1,
        GIM_CheckIsSafeToFold, /*InsnID*/2,
        GIM_CheckIsSafeToFold, /*InsnID*/3,
        GIM_CheckComplexPattern, /*MI*/1, /*Op*/1, /*Renderer*/GIMT_Encode2(0), GIMT_Encode2(GICP_gi_vop3mods),
        GIM_CheckComplexPattern, /*MI*/1, /*Op*/2, /*Renderer*/GIMT_Encode2(1), GIMT_Encode2(GICP_gi_vop3mods),
        GIM_CheckComplexPattern, /*MI*/2, /*Op*/1, /*Renderer*/GIMT_Encode2(2), GIMT_Encode2(GICP_gi_vop3mods),
        // (fmaxnum:{ *:[f16] } (fminnum:{ *:[f16] } (VOP3Mods:{ *:[f16] } f16:{ *:[f16] }:$src0, i32:{ *:[i32] }:$src0_mods), (VOP3Mods:{ *:[f16] } f16:{ *:[f16] }:$src1, i32:{ *:[i32] }:$src1_mods)), (fminnum_ieee:{ *:[f16] } (VOP3Mods:{ *:[f16] } f16:{ *:[f16] }:$src2, i32:{ *:[i32] }:$src2_mods), (fmaxnum_ieee:{ *:[f16] } (VOP3Mods:{ *:[f16] } f16:{ *:[f16] }:$src1, i32:{ *:[i32] }:$src1_mods), (VOP3Mods:{ *:[f16] } f16:{ *:[f16] }:$src0, i32:{ *:[i32] }:$src0_mods))))<<P:Predicate_fmaxnum_like_nnan>>  =>  (V_MED3_F16_e64:{ *:[f16] } ?:{ *:[i32] }:$src0_mods, ?:{ *:[f16] }:$src0, ?:{ *:[i32] }:$src1_mods, ?:{ *:[f16] }:$src1, ?:{ *:[i32] }:$src2_mods, ?:{ *:[f16] }:$src2, 0:{ *:[i1] })
        GIR_BuildMI, /*InsnID*/0, /*Opcode*/GIMT_Encode2(AMDGPU::V_MED3_F16_e64),
        GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/0, // DstI[vdst]
        GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/1, // src0_mods
        GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/0, // src0
        GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(1), /*SubOperand*/1, // src1_mods
        GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(1), /*SubOperand*/0, // src1
        GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(2), /*SubOperand*/1, // src2_mods
        GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(2), /*SubOperand*/0, // src2
        GIR_AddImm8, /*InsnID*/0, /*Imm*/0,
        GIR_AddImm8, /*InsnID*/0, /*Imm*/0,
        GIR_AddImm8, /*InsnID*/0, /*Imm*/0,
        GIR_ConstrainSelectedInstOperands, /*InsnID*/0,
        GIR_EraseFromParent, /*InsnID*/0,
        // GIR_Coverage, 10712,
        GIR_Done,
      // Label 4493: @291336
      GIM_Try, /*On fail goto*//*Label 4494*/ GIMT_Encode4(291482), // Rule ID 10715 //
        GIM_CheckFeatures, GIMT_Encode2(GIFBS_isGFX9Plus),
        GIM_CheckRegBankForClass, /*MI*/0, /*Op*/0, /*RC*/GIMT_Encode2(AMDGPU::VGPR_32RegClassID),
        GIM_RecordInsn, /*DefineMI*/1, /*MI*/0, /*OpIdx*/1, // MIs[1]
        GIM_CheckOpcode, /*MI*/1, GIMT_Encode2(TargetOpcode::G_FMINNUM),
        GIM_CheckType, /*MI*/1, /*Op*/1, /*Type*/GILLT_s16,
        GIM_CheckType, /*MI*/1, /*Op*/2, /*Type*/GILLT_s16,
        GIM_RecordInsn, /*DefineMI*/2, /*MI*/0, /*OpIdx*/2, // MIs[2]
        GIM_CheckOpcode, /*MI*/2, GIMT_Encode2(TargetOpcode::G_FMINNUM_IEEE),
        GIM_CheckType, /*MI*/2, /*Op*/1, /*Type*/GILLT_s16,
        GIM_CheckType, /*MI*/2, /*Op*/2, /*Type*/GILLT_s16,
        GIM_RecordInsn, /*DefineMI*/3, /*MI*/2, /*OpIdx*/2, // MIs[3]
        GIM_CheckOpcode, /*MI*/3, GIMT_Encode2(TargetOpcode::G_FMAXNUM_IEEE),
        // MIs[3] VOP3Mods:src0:src0_mods
        GIM_CheckIsSameOperand, /*MI*/3, /*OpIdx*/1, /*OtherMI*/1, /*OtherOpIdx*/2,
        // MIs[3] VOP3Mods:src1:src1_mods
        GIM_CheckIsSameOperand, /*MI*/3, /*OpIdx*/2, /*OtherMI*/1, /*OtherOpIdx*/1,
        GIM_CheckCxxInsnPredicate, /*MI*/0, /*FnId*/GIMT_Encode2(GICXXPred_MI_Predicate_fmaxnum_like_nnan),
        GIM_CheckIsSafeToFold, /*InsnID*/1,
        GIM_CheckIsSafeToFold, /*InsnID*/2,
        GIM_CheckIsSafeToFold, /*InsnID*/3,
        GIM_CheckComplexPattern, /*MI*/1, /*Op*/1, /*Renderer*/GIMT_Encode2(0), GIMT_Encode2(GICP_gi_vop3mods),
        GIM_CheckComplexPattern, /*MI*/1, /*Op*/2, /*Renderer*/GIMT_Encode2(1), GIMT_Encode2(GICP_gi_vop3mods),
        GIM_CheckComplexPattern, /*MI*/2, /*Op*/1, /*Renderer*/GIMT_Encode2(2), GIMT_Encode2(GICP_gi_vop3mods),
        // (fmaxnum:{ *:[f16] } (fminnum:{ *:[f16] } (VOP3Mods:{ *:[f16] } f16:{ *:[f16] }:$src1, i32:{ *:[i32] }:$src1_mods), (VOP3Mods:{ *:[f16] } f16:{ *:[f16] }:$src0, i32:{ *:[i32] }:$src0_mods)), (fminnum_ieee:{ *:[f16] } (VOP3Mods:{ *:[f16] } f16:{ *:[f16] }:$src2, i32:{ *:[i32] }:$src2_mods), (fmaxnum_ieee:{ *:[f16] } (VOP3Mods:{ *:[f16] } f16:{ *:[f16] }:$src0, i32:{ *:[i32] }:$src0_mods), (VOP3Mods:{ *:[f16] } f16:{ *:[f16] }:$src1, i32:{ *:[i32] }:$src1_mods))))<<P:Predicate_fmaxnum_like_nnan>>  =>  (V_MED3_F16_e64:{ *:[f16] } ?:{ *:[i32] }:$src0_mods, ?:{ *:[f16] }:$src0, ?:{ *:[i32] }:$src1_mods, ?:{ *:[f16] }:$src1, ?:{ *:[i32] }:$src2_mods, ?:{ *:[f16] }:$src2, 0:{ *:[i1] })
        GIR_BuildMI, /*InsnID*/0, /*Opcode*/GIMT_Encode2(AMDGPU::V_MED3_F16_e64),
        GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/0, // DstI[vdst]
        GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(1), /*SubOperand*/1, // src0_mods
        GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(1), /*SubOperand*/0, // src0
        GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/1, // src1_mods
        GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/0, // src1
        GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(2), /*SubOperand*/1, // src2_mods
        GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(2), /*SubOperand*/0, // src2
        GIR_AddImm8, /*InsnID*/0, /*Imm*/0,
        GIR_AddImm8, /*InsnID*/0, /*Imm*/0,
        GIR_AddImm8, /*InsnID*/0, /*Imm*/0,
        GIR_ConstrainSelectedInstOperands, /*InsnID*/0,
        GIR_EraseFromParent, /*InsnID*/0,
        // GIR_Coverage, 10715,
        GIR_Done,
      // Label 4494: @291482
      GIM_Try, /*On fail goto*//*Label 4495*/ GIMT_Encode4(291628), // Rule ID 10716 //
        GIM_CheckFeatures, GIMT_Encode2(GIFBS_isGFX9Plus),
        GIM_CheckRegBankForClass, /*MI*/0, /*Op*/0, /*RC*/GIMT_Encode2(AMDGPU::VGPR_32RegClassID),
        GIM_RecordInsn, /*DefineMI*/1, /*MI*/0, /*OpIdx*/1, // MIs[1]
        GIM_CheckOpcode, /*MI*/1, GIMT_Encode2(TargetOpcode::G_FMINNUM),
        GIM_CheckType, /*MI*/1, /*Op*/1, /*Type*/GILLT_s16,
        GIM_CheckType, /*MI*/1, /*Op*/2, /*Type*/GILLT_s16,
        GIM_RecordInsn, /*DefineMI*/2, /*MI*/0, /*OpIdx*/2, // MIs[2]
        GIM_CheckOpcode, /*MI*/2, GIMT_Encode2(TargetOpcode::G_FMINNUM_IEEE),
        GIM_CheckType, /*MI*/2, /*Op*/1, /*Type*/GILLT_s16,
        GIM_CheckType, /*MI*/2, /*Op*/2, /*Type*/GILLT_s16,
        GIM_RecordInsn, /*DefineMI*/3, /*MI*/2, /*OpIdx*/2, // MIs[3]
        GIM_CheckOpcode, /*MI*/3, GIMT_Encode2(TargetOpcode::G_FMAXNUM_IEEE),
        // MIs[3] VOP3Mods:src1:src1_mods
        GIM_CheckIsSameOperand, /*MI*/3, /*OpIdx*/1, /*OtherMI*/1, /*OtherOpIdx*/1,
        // MIs[3] VOP3Mods:src0:src0_mods
        GIM_CheckIsSameOperand, /*MI*/3, /*OpIdx*/2, /*OtherMI*/1, /*OtherOpIdx*/2,
        GIM_CheckCxxInsnPredicate, /*MI*/0, /*FnId*/GIMT_Encode2(GICXXPred_MI_Predicate_fmaxnum_like_nnan),
        GIM_CheckIsSafeToFold, /*InsnID*/1,
        GIM_CheckIsSafeToFold, /*InsnID*/2,
        GIM_CheckIsSafeToFold, /*InsnID*/3,
        GIM_CheckComplexPattern, /*MI*/1, /*Op*/1, /*Renderer*/GIMT_Encode2(0), GIMT_Encode2(GICP_gi_vop3mods),
        GIM_CheckComplexPattern, /*MI*/1, /*Op*/2, /*Renderer*/GIMT_Encode2(1), GIMT_Encode2(GICP_gi_vop3mods),
        GIM_CheckComplexPattern, /*MI*/2, /*Op*/1, /*Renderer*/GIMT_Encode2(2), GIMT_Encode2(GICP_gi_vop3mods),
        // (fmaxnum:{ *:[f16] } (fminnum:{ *:[f16] } (VOP3Mods:{ *:[f16] } f16:{ *:[f16] }:$src1, i32:{ *:[i32] }:$src1_mods), (VOP3Mods:{ *:[f16] } f16:{ *:[f16] }:$src0, i32:{ *:[i32] }:$src0_mods)), (fminnum_ieee:{ *:[f16] } (VOP3Mods:{ *:[f16] } f16:{ *:[f16] }:$src2, i32:{ *:[i32] }:$src2_mods), (fmaxnum_ieee:{ *:[f16] } (VOP3Mods:{ *:[f16] } f16:{ *:[f16] }:$src1, i32:{ *:[i32] }:$src1_mods), (VOP3Mods:{ *:[f16] } f16:{ *:[f16] }:$src0, i32:{ *:[i32] }:$src0_mods))))<<P:Predicate_fmaxnum_like_nnan>>  =>  (V_MED3_F16_e64:{ *:[f16] } ?:{ *:[i32] }:$src0_mods, ?:{ *:[f16] }:$src0, ?:{ *:[i32] }:$src1_mods, ?:{ *:[f16] }:$src1, ?:{ *:[i32] }:$src2_mods, ?:{ *:[f16] }:$src2, 0:{ *:[i1] })
        GIR_BuildMI, /*InsnID*/0, /*Opcode*/GIMT_Encode2(AMDGPU::V_MED3_F16_e64),
        GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/0, // DstI[vdst]
        GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(1), /*SubOperand*/1, // src0_mods
        GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(1), /*SubOperand*/0, // src0
        GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/1, // src1_mods
        GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/0, // src1
        GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(2), /*SubOperand*/1, // src2_mods
        GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(2), /*SubOperand*/0, // src2
        GIR_AddImm8, /*InsnID*/0, /*Imm*/0,
        GIR_AddImm8, /*InsnID*/0, /*Imm*/0,
        GIR_AddImm8, /*InsnID*/0, /*Imm*/0,
        GIR_ConstrainSelectedInstOperands, /*InsnID*/0,
        GIR_EraseFromParent, /*InsnID*/0,
        // GIR_Coverage, 10716,
        GIR_Done,
      // Label 4495: @291628
      GIM_Try, /*On fail goto*//*Label 4496*/ GIMT_Encode4(291774), // Rule ID 6549 //
        GIM_CheckFeatures, GIMT_Encode2(GIFBS_isGFX9Plus),
        GIM_CheckRegBankForClass, /*MI*/0, /*Op*/0, /*RC*/GIMT_Encode2(AMDGPU::VGPR_32RegClassID),
        GIM_RecordInsn, /*DefineMI*/1, /*MI*/0, /*OpIdx*/1, // MIs[1]
        GIM_CheckOpcode, /*MI*/1, GIMT_Encode2(TargetOpcode::G_FMINNUM),
        GIM_CheckType, /*MI*/1, /*Op*/1, /*Type*/GILLT_s16,
        GIM_CheckType, /*MI*/1, /*Op*/2, /*Type*/GILLT_s16,
        GIM_RecordInsn, /*DefineMI*/2, /*MI*/0, /*OpIdx*/2, // MIs[2]
        GIM_CheckOpcode, /*MI*/2, GIMT_Encode2(TargetOpcode::G_FMINNUM_IEEE),
        GIM_CheckType, /*MI*/2, /*Op*/1, /*Type*/GILLT_s16,
        GIM_CheckType, /*MI*/2, /*Op*/2, /*Type*/GILLT_s16,
        GIM_RecordInsn, /*DefineMI*/3, /*MI*/2, /*OpIdx*/1, // MIs[3]
        GIM_CheckOpcode, /*MI*/3, GIMT_Encode2(TargetOpcode::G_FMAXNUM),
        // MIs[3] VOP3Mods:src0:src0_mods
        GIM_CheckIsSameOperand, /*MI*/3, /*OpIdx*/1, /*OtherMI*/1, /*OtherOpIdx*/1,
        // MIs[3] VOP3Mods:src1:src1_mods
        GIM_CheckIsSameOperand, /*MI*/3, /*OpIdx*/2, /*OtherMI*/1, /*OtherOpIdx*/2,
        GIM_CheckCxxInsnPredicate, /*MI*/0, /*FnId*/GIMT_Encode2(GICXXPred_MI_Predicate_fmaxnum_like_nnan),
        GIM_CheckIsSafeToFold, /*InsnID*/1,
        GIM_CheckIsSafeToFold, /*InsnID*/2,
        GIM_CheckIsSafeToFold, /*InsnID*/3,
        GIM_CheckComplexPattern, /*MI*/1, /*Op*/1, /*Renderer*/GIMT_Encode2(0), GIMT_Encode2(GICP_gi_vop3mods),
        GIM_CheckComplexPattern, /*MI*/1, /*Op*/2, /*Renderer*/GIMT_Encode2(1), GIMT_Encode2(GICP_gi_vop3mods),
        GIM_CheckComplexPattern, /*MI*/2, /*Op*/2, /*Renderer*/GIMT_Encode2(2), GIMT_Encode2(GICP_gi_vop3mods),
        // (fmaxnum:{ *:[f16] } (fminnum:{ *:[f16] } (VOP3Mods:{ *:[f16] } f16:{ *:[f16] }:$src0, i32:{ *:[i32] }:$src0_mods), (VOP3Mods:{ *:[f16] } f16:{ *:[f16] }:$src1, i32:{ *:[i32] }:$src1_mods)), (fminnum_ieee:{ *:[f16] } (fmaxnum:{ *:[f16] } (VOP3Mods:{ *:[f16] } f16:{ *:[f16] }:$src0, i32:{ *:[i32] }:$src0_mods), (VOP3Mods:{ *:[f16] } f16:{ *:[f16] }:$src1, i32:{ *:[i32] }:$src1_mods)), (VOP3Mods:{ *:[f16] } f16:{ *:[f16] }:$src2, i32:{ *:[i32] }:$src2_mods)))<<P:Predicate_fmaxnum_like_nnan>>  =>  (V_MED3_F16_e64:{ *:[f16] } ?:{ *:[i32] }:$src0_mods, ?:{ *:[f16] }:$src0, ?:{ *:[i32] }:$src1_mods, ?:{ *:[f16] }:$src1, ?:{ *:[i32] }:$src2_mods, ?:{ *:[f16] }:$src2, 0:{ *:[i1] })
        GIR_BuildMI, /*InsnID*/0, /*Opcode*/GIMT_Encode2(AMDGPU::V_MED3_F16_e64),
        GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/0, // DstI[vdst]
        GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/1, // src0_mods
        GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/0, // src0
        GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(1), /*SubOperand*/1, // src1_mods
        GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(1), /*SubOperand*/0, // src1
        GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(2), /*SubOperand*/1, // src2_mods
        GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(2), /*SubOperand*/0, // src2
        GIR_AddImm8, /*InsnID*/0, /*Imm*/0,
        GIR_AddImm8, /*InsnID*/0, /*Imm*/0,
        GIR_AddImm8, /*InsnID*/0, /*Imm*/0,
        GIR_ConstrainSelectedInstOperands, /*InsnID*/0,
        GIR_EraseFromParent, /*InsnID*/0,
        // GIR_Coverage, 6549,
        GIR_Done,
      // Label 4496: @291774
      GIM_Try, /*On fail goto*//*Label 4497*/ GIMT_Encode4(291920), // Rule ID 10725 //
        GIM_CheckFeatures, GIMT_Encode2(GIFBS_isGFX9Plus),
        GIM_CheckRegBankForClass, /*MI*/0, /*Op*/0, /*RC*/GIMT_Encode2(AMDGPU::VGPR_32RegClassID),
        GIM_RecordInsn, /*DefineMI*/1, /*MI*/0, /*OpIdx*/1, // MIs[1]
        GIM_CheckOpcode, /*MI*/1, GIMT_Encode2(TargetOpcode::G_FMINNUM),
        GIM_CheckType, /*MI*/1, /*Op*/1, /*Type*/GILLT_s16,
        GIM_CheckType, /*MI*/1, /*Op*/2, /*Type*/GILLT_s16,
        GIM_RecordInsn, /*DefineMI*/2, /*MI*/0, /*OpIdx*/2, // MIs[2]
        GIM_CheckOpcode, /*MI*/2, GIMT_Encode2(TargetOpcode::G_FMINNUM_IEEE),
        GIM_CheckType, /*MI*/2, /*Op*/1, /*Type*/GILLT_s16,
        GIM_CheckType, /*MI*/2, /*Op*/2, /*Type*/GILLT_s16,
        GIM_RecordInsn, /*DefineMI*/3, /*MI*/2, /*OpIdx*/1, // MIs[3]
        GIM_CheckOpcode, /*MI*/3, GIMT_Encode2(TargetOpcode::G_FMAXNUM),
        // MIs[3] VOP3Mods:src1:src1_mods
        GIM_CheckIsSameOperand, /*MI*/3, /*OpIdx*/1, /*OtherMI*/1, /*OtherOpIdx*/2,
        // MIs[3] VOP3Mods:src0:src0_mods
        GIM_CheckIsSameOperand, /*MI*/3, /*OpIdx*/2, /*OtherMI*/1, /*OtherOpIdx*/1,
        GIM_CheckCxxInsnPredicate, /*MI*/0, /*FnId*/GIMT_Encode2(GICXXPred_MI_Predicate_fmaxnum_like_nnan),
        GIM_CheckIsSafeToFold, /*InsnID*/1,
        GIM_CheckIsSafeToFold, /*InsnID*/2,
        GIM_CheckIsSafeToFold, /*InsnID*/3,
        GIM_CheckComplexPattern, /*MI*/1, /*Op*/1, /*Renderer*/GIMT_Encode2(0), GIMT_Encode2(GICP_gi_vop3mods),
        GIM_CheckComplexPattern, /*MI*/1, /*Op*/2, /*Renderer*/GIMT_Encode2(1), GIMT_Encode2(GICP_gi_vop3mods),
        GIM_CheckComplexPattern, /*MI*/2, /*Op*/2, /*Renderer*/GIMT_Encode2(2), GIMT_Encode2(GICP_gi_vop3mods),
        // (fmaxnum:{ *:[f16] } (fminnum:{ *:[f16] } (VOP3Mods:{ *:[f16] } f16:{ *:[f16] }:$src0, i32:{ *:[i32] }:$src0_mods), (VOP3Mods:{ *:[f16] } f16:{ *:[f16] }:$src1, i32:{ *:[i32] }:$src1_mods)), (fminnum_ieee:{ *:[f16] } (fmaxnum:{ *:[f16] } (VOP3Mods:{ *:[f16] } f16:{ *:[f16] }:$src1, i32:{ *:[i32] }:$src1_mods), (VOP3Mods:{ *:[f16] } f16:{ *:[f16] }:$src0, i32:{ *:[i32] }:$src0_mods)), (VOP3Mods:{ *:[f16] } f16:{ *:[f16] }:$src2, i32:{ *:[i32] }:$src2_mods)))<<P:Predicate_fmaxnum_like_nnan>>  =>  (V_MED3_F16_e64:{ *:[f16] } ?:{ *:[i32] }:$src0_mods, ?:{ *:[f16] }:$src0, ?:{ *:[i32] }:$src1_mods, ?:{ *:[f16] }:$src1, ?:{ *:[i32] }:$src2_mods, ?:{ *:[f16] }:$src2, 0:{ *:[i1] })
        GIR_BuildMI, /*InsnID*/0, /*Opcode*/GIMT_Encode2(AMDGPU::V_MED3_F16_e64),
        GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/0, // DstI[vdst]
        GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/1, // src0_mods
        GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/0, // src0
        GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(1), /*SubOperand*/1, // src1_mods
        GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(1), /*SubOperand*/0, // src1
        GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(2), /*SubOperand*/1, // src2_mods
        GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(2), /*SubOperand*/0, // src2
        GIR_AddImm8, /*InsnID*/0, /*Imm*/0,
        GIR_AddImm8, /*InsnID*/0, /*Imm*/0,
        GIR_AddImm8, /*InsnID*/0, /*Imm*/0,
        GIR_ConstrainSelectedInstOperands, /*InsnID*/0,
        GIR_EraseFromParent, /*InsnID*/0,
        // GIR_Coverage, 10725,
        GIR_Done,
      // Label 4497: @291920
      GIM_Try, /*On fail goto*//*Label 4498*/ GIMT_Encode4(292066), // Rule ID 10728 //
        GIM_CheckFeatures, GIMT_Encode2(GIFBS_isGFX9Plus),
        GIM_CheckRegBankForClass, /*MI*/0, /*Op*/0, /*RC*/GIMT_Encode2(AMDGPU::VGPR_32RegClassID),
        GIM_RecordInsn, /*DefineMI*/1, /*MI*/0, /*OpIdx*/1, // MIs[1]
        GIM_CheckOpcode, /*MI*/1, GIMT_Encode2(TargetOpcode::G_FMINNUM),
        GIM_CheckType, /*MI*/1, /*Op*/1, /*Type*/GILLT_s16,
        GIM_CheckType, /*MI*/1, /*Op*/2, /*Type*/GILLT_s16,
        GIM_RecordInsn, /*DefineMI*/2, /*MI*/0, /*OpIdx*/2, // MIs[2]
        GIM_CheckOpcode, /*MI*/2, GIMT_Encode2(TargetOpcode::G_FMINNUM_IEEE),
        GIM_CheckType, /*MI*/2, /*Op*/1, /*Type*/GILLT_s16,
        GIM_CheckType, /*MI*/2, /*Op*/2, /*Type*/GILLT_s16,
        GIM_RecordInsn, /*DefineMI*/3, /*MI*/2, /*OpIdx*/1, // MIs[3]
        GIM_CheckOpcode, /*MI*/3, GIMT_Encode2(TargetOpcode::G_FMAXNUM),
        // MIs[3] VOP3Mods:src0:src0_mods
        GIM_CheckIsSameOperand, /*MI*/3, /*OpIdx*/1, /*OtherMI*/1, /*OtherOpIdx*/2,
        // MIs[3] VOP3Mods:src1:src1_mods
        GIM_CheckIsSameOperand, /*MI*/3, /*OpIdx*/2, /*OtherMI*/1, /*OtherOpIdx*/1,
        GIM_CheckCxxInsnPredicate, /*MI*/0, /*FnId*/GIMT_Encode2(GICXXPred_MI_Predicate_fmaxnum_like_nnan),
        GIM_CheckIsSafeToFold, /*InsnID*/1,
        GIM_CheckIsSafeToFold, /*InsnID*/2,
        GIM_CheckIsSafeToFold, /*InsnID*/3,
        GIM_CheckComplexPattern, /*MI*/1, /*Op*/1, /*Renderer*/GIMT_Encode2(0), GIMT_Encode2(GICP_gi_vop3mods),
        GIM_CheckComplexPattern, /*MI*/1, /*Op*/2, /*Renderer*/GIMT_Encode2(1), GIMT_Encode2(GICP_gi_vop3mods),
        GIM_CheckComplexPattern, /*MI*/2, /*Op*/2, /*Renderer*/GIMT_Encode2(2), GIMT_Encode2(GICP_gi_vop3mods),
        // (fmaxnum:{ *:[f16] } (fminnum:{ *:[f16] } (VOP3Mods:{ *:[f16] } f16:{ *:[f16] }:$src1, i32:{ *:[i32] }:$src1_mods), (VOP3Mods:{ *:[f16] } f16:{ *:[f16] }:$src0, i32:{ *:[i32] }:$src0_mods)), (fminnum_ieee:{ *:[f16] } (fmaxnum:{ *:[f16] } (VOP3Mods:{ *:[f16] } f16:{ *:[f16] }:$src0, i32:{ *:[i32] }:$src0_mods), (VOP3Mods:{ *:[f16] } f16:{ *:[f16] }:$src1, i32:{ *:[i32] }:$src1_mods)), (VOP3Mods:{ *:[f16] } f16:{ *:[f16] }:$src2, i32:{ *:[i32] }:$src2_mods)))<<P:Predicate_fmaxnum_like_nnan>>  =>  (V_MED3_F16_e64:{ *:[f16] } ?:{ *:[i32] }:$src0_mods, ?:{ *:[f16] }:$src0, ?:{ *:[i32] }:$src1_mods, ?:{ *:[f16] }:$src1, ?:{ *:[i32] }:$src2_mods, ?:{ *:[f16] }:$src2, 0:{ *:[i1] })
        GIR_BuildMI, /*InsnID*/0, /*Opcode*/GIMT_Encode2(AMDGPU::V_MED3_F16_e64),
        GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/0, // DstI[vdst]
        GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(1), /*SubOperand*/1, // src0_mods
        GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(1), /*SubOperand*/0, // src0
        GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/1, // src1_mods
        GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/0, // src1
        GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(2), /*SubOperand*/1, // src2_mods
        GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(2), /*SubOperand*/0, // src2
        GIR_AddImm8, /*InsnID*/0, /*Imm*/0,
        GIR_AddImm8, /*InsnID*/0, /*Imm*/0,
        GIR_AddImm8, /*InsnID*/0, /*Imm*/0,
        GIR_ConstrainSelectedInstOperands, /*InsnID*/0,
        GIR_EraseFromParent, /*InsnID*/0,
        // GIR_Coverage, 10728,
        GIR_Done,
      // Label 4498: @292066
      GIM_Try, /*On fail goto*//*Label 4499*/ GIMT_Encode4(292212), // Rule ID 10729 //
        GIM_CheckFeatures, GIMT_Encode2(GIFBS_isGFX9Plus),
        GIM_CheckRegBankForClass, /*MI*/0, /*Op*/0, /*RC*/GIMT_Encode2(AMDGPU::VGPR_32RegClassID),
        GIM_RecordInsn, /*DefineMI*/1, /*MI*/0, /*OpIdx*/1, // MIs[1]
        GIM_CheckOpcode, /*MI*/1, GIMT_Encode2(TargetOpcode::G_FMINNUM),
        GIM_CheckType, /*MI*/1, /*Op*/1, /*Type*/GILLT_s16,
        GIM_CheckType, /*MI*/1, /*Op*/2, /*Type*/GILLT_s16,
        GIM_RecordInsn, /*DefineMI*/2, /*MI*/0, /*OpIdx*/2, // MIs[2]
        GIM_CheckOpcode, /*MI*/2, GIMT_Encode2(TargetOpcode::G_FMINNUM_IEEE),
        GIM_CheckType, /*MI*/2, /*Op*/1, /*Type*/GILLT_s16,
        GIM_CheckType, /*MI*/2, /*Op*/2, /*Type*/GILLT_s16,
        GIM_RecordInsn, /*DefineMI*/3, /*MI*/2, /*OpIdx*/1, // MIs[3]
        GIM_CheckOpcode, /*MI*/3, GIMT_Encode2(TargetOpcode::G_FMAXNUM),
        // MIs[3] VOP3Mods:src1:src1_mods
        GIM_CheckIsSameOperand, /*MI*/3, /*OpIdx*/1, /*OtherMI*/1, /*OtherOpIdx*/1,
        // MIs[3] VOP3Mods:src0:src0_mods
        GIM_CheckIsSameOperand, /*MI*/3, /*OpIdx*/2, /*OtherMI*/1, /*OtherOpIdx*/2,
        GIM_CheckCxxInsnPredicate, /*MI*/0, /*FnId*/GIMT_Encode2(GICXXPred_MI_Predicate_fmaxnum_like_nnan),
        GIM_CheckIsSafeToFold, /*InsnID*/1,
        GIM_CheckIsSafeToFold, /*InsnID*/2,
        GIM_CheckIsSafeToFold, /*InsnID*/3,
        GIM_CheckComplexPattern, /*MI*/1, /*Op*/1, /*Renderer*/GIMT_Encode2(0), GIMT_Encode2(GICP_gi_vop3mods),
        GIM_CheckComplexPattern, /*MI*/1, /*Op*/2, /*Renderer*/GIMT_Encode2(1), GIMT_Encode2(GICP_gi_vop3mods),
        GIM_CheckComplexPattern, /*MI*/2, /*Op*/2, /*Renderer*/GIMT_Encode2(2), GIMT_Encode2(GICP_gi_vop3mods),
        // (fmaxnum:{ *:[f16] } (fminnum:{ *:[f16] } (VOP3Mods:{ *:[f16] } f16:{ *:[f16] }:$src1, i32:{ *:[i32] }:$src1_mods), (VOP3Mods:{ *:[f16] } f16:{ *:[f16] }:$src0, i32:{ *:[i32] }:$src0_mods)), (fminnum_ieee:{ *:[f16] } (fmaxnum:{ *:[f16] } (VOP3Mods:{ *:[f16] } f16:{ *:[f16] }:$src1, i32:{ *:[i32] }:$src1_mods), (VOP3Mods:{ *:[f16] } f16:{ *:[f16] }:$src0, i32:{ *:[i32] }:$src0_mods)), (VOP3Mods:{ *:[f16] } f16:{ *:[f16] }:$src2, i32:{ *:[i32] }:$src2_mods)))<<P:Predicate_fmaxnum_like_nnan>>  =>  (V_MED3_F16_e64:{ *:[f16] } ?:{ *:[i32] }:$src0_mods, ?:{ *:[f16] }:$src0, ?:{ *:[i32] }:$src1_mods, ?:{ *:[f16] }:$src1, ?:{ *:[i32] }:$src2_mods, ?:{ *:[f16] }:$src2, 0:{ *:[i1] })
        GIR_BuildMI, /*InsnID*/0, /*Opcode*/GIMT_Encode2(AMDGPU::V_MED3_F16_e64),
        GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/0, // DstI[vdst]
        GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(1), /*SubOperand*/1, // src0_mods
        GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(1), /*SubOperand*/0, // src0
        GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/1, // src1_mods
        GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/0, // src1
        GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(2), /*SubOperand*/1, // src2_mods
        GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(2), /*SubOperand*/0, // src2
        GIR_AddImm8, /*InsnID*/0, /*Imm*/0,
        GIR_AddImm8, /*InsnID*/0, /*Imm*/0,
        GIR_AddImm8, /*InsnID*/0, /*Imm*/0,
        GIR_ConstrainSelectedInstOperands, /*InsnID*/0,
        GIR_EraseFromParent, /*InsnID*/0,
        // GIR_Coverage, 10729,
        GIR_Done,
      // Label 4499: @292212
      GIM_Try, /*On fail goto*//*Label 4500*/ GIMT_Encode4(292358), // Rule ID 6548 //
        GIM_CheckFeatures, GIMT_Encode2(GIFBS_isGFX9Plus),
        GIM_CheckRegBankForClass, /*MI*/0, /*Op*/0, /*RC*/GIMT_Encode2(AMDGPU::VGPR_32RegClassID),
        GIM_RecordInsn, /*DefineMI*/1, /*MI*/0, /*OpIdx*/1, // MIs[1]
        GIM_CheckOpcode, /*MI*/1, GIMT_Encode2(TargetOpcode::G_FMINNUM),
        GIM_CheckType, /*MI*/1, /*Op*/1, /*Type*/GILLT_s16,
        GIM_CheckType, /*MI*/1, /*Op*/2, /*Type*/GILLT_s16,
        GIM_RecordInsn, /*DefineMI*/2, /*MI*/0, /*OpIdx*/2, // MIs[2]
        GIM_CheckOpcode, /*MI*/2, GIMT_Encode2(TargetOpcode::G_FMINNUM_IEEE),
        GIM_CheckType, /*MI*/2, /*Op*/1, /*Type*/GILLT_s16,
        GIM_CheckType, /*MI*/2, /*Op*/2, /*Type*/GILLT_s16,
        GIM_RecordInsn, /*DefineMI*/3, /*MI*/2, /*OpIdx*/1, // MIs[3]
        GIM_CheckOpcode, /*MI*/3, GIMT_Encode2(TargetOpcode::G_FMAXNUM_IEEE),
        // MIs[3] VOP3Mods:src0:src0_mods
        GIM_CheckIsSameOperand, /*MI*/3, /*OpIdx*/1, /*OtherMI*/1, /*OtherOpIdx*/1,
        // MIs[3] VOP3Mods:src1:src1_mods
        GIM_CheckIsSameOperand, /*MI*/3, /*OpIdx*/2, /*OtherMI*/1, /*OtherOpIdx*/2,
        GIM_CheckCxxInsnPredicate, /*MI*/0, /*FnId*/GIMT_Encode2(GICXXPred_MI_Predicate_fmaxnum_like_nnan),
        GIM_CheckIsSafeToFold, /*InsnID*/1,
        GIM_CheckIsSafeToFold, /*InsnID*/2,
        GIM_CheckIsSafeToFold, /*InsnID*/3,
        GIM_CheckComplexPattern, /*MI*/1, /*Op*/1, /*Renderer*/GIMT_Encode2(0), GIMT_Encode2(GICP_gi_vop3mods),
        GIM_CheckComplexPattern, /*MI*/1, /*Op*/2, /*Renderer*/GIMT_Encode2(1), GIMT_Encode2(GICP_gi_vop3mods),
        GIM_CheckComplexPattern, /*MI*/2, /*Op*/2, /*Renderer*/GIMT_Encode2(2), GIMT_Encode2(GICP_gi_vop3mods),
        // (fmaxnum:{ *:[f16] } (fminnum:{ *:[f16] } (VOP3Mods:{ *:[f16] } f16:{ *:[f16] }:$src0, i32:{ *:[i32] }:$src0_mods), (VOP3Mods:{ *:[f16] } f16:{ *:[f16] }:$src1, i32:{ *:[i32] }:$src1_mods)), (fminnum_ieee:{ *:[f16] } (fmaxnum_ieee:{ *:[f16] } (VOP3Mods:{ *:[f16] } f16:{ *:[f16] }:$src0, i32:{ *:[i32] }:$src0_mods), (VOP3Mods:{ *:[f16] } f16:{ *:[f16] }:$src1, i32:{ *:[i32] }:$src1_mods)), (VOP3Mods:{ *:[f16] } f16:{ *:[f16] }:$src2, i32:{ *:[i32] }:$src2_mods)))<<P:Predicate_fmaxnum_like_nnan>>  =>  (V_MED3_F16_e64:{ *:[f16] } ?:{ *:[i32] }:$src0_mods, ?:{ *:[f16] }:$src0, ?:{ *:[i32] }:$src1_mods, ?:{ *:[f16] }:$src1, ?:{ *:[i32] }:$src2_mods, ?:{ *:[f16] }:$src2, 0:{ *:[i1] })
        GIR_BuildMI, /*InsnID*/0, /*Opcode*/GIMT_Encode2(AMDGPU::V_MED3_F16_e64),
        GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/0, // DstI[vdst]
        GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/1, // src0_mods
        GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/0, // src0
        GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(1), /*SubOperand*/1, // src1_mods
        GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(1), /*SubOperand*/0, // src1
        GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(2), /*SubOperand*/1, // src2_mods
        GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(2), /*SubOperand*/0, // src2
        GIR_AddImm8, /*InsnID*/0, /*Imm*/0,
        GIR_AddImm8, /*InsnID*/0, /*Imm*/0,
        GIR_AddImm8, /*InsnID*/0, /*Imm*/0,
        GIR_ConstrainSelectedInstOperands, /*InsnID*/0,
        GIR_EraseFromParent, /*InsnID*/0,
        // GIR_Coverage, 6548,
        GIR_Done,
      // Label 4500: @292358
      GIM_Try, /*On fail goto*//*Label 4501*/ GIMT_Encode4(292504), // Rule ID 10710 //
        GIM_CheckFeatures, GIMT_Encode2(GIFBS_isGFX9Plus),
        GIM_CheckRegBankForClass, /*MI*/0, /*Op*/0, /*RC*/GIMT_Encode2(AMDGPU::VGPR_32RegClassID),
        GIM_RecordInsn, /*DefineMI*/1, /*MI*/0, /*OpIdx*/1, // MIs[1]
        GIM_CheckOpcode, /*MI*/1, GIMT_Encode2(TargetOpcode::G_FMINNUM),
        GIM_CheckType, /*MI*/1, /*Op*/1, /*Type*/GILLT_s16,
        GIM_CheckType, /*MI*/1, /*Op*/2, /*Type*/GILLT_s16,
        GIM_RecordInsn, /*DefineMI*/2, /*MI*/0, /*OpIdx*/2, // MIs[2]
        GIM_CheckOpcode, /*MI*/2, GIMT_Encode2(TargetOpcode::G_FMINNUM_IEEE),
        GIM_CheckType, /*MI*/2, /*Op*/1, /*Type*/GILLT_s16,
        GIM_CheckType, /*MI*/2, /*Op*/2, /*Type*/GILLT_s16,
        GIM_RecordInsn, /*DefineMI*/3, /*MI*/2, /*OpIdx*/1, // MIs[3]
        GIM_CheckOpcode, /*MI*/3, GIMT_Encode2(TargetOpcode::G_FMAXNUM_IEEE),
        // MIs[3] VOP3Mods:src1:src1_mods
        GIM_CheckIsSameOperand, /*MI*/3, /*OpIdx*/1, /*OtherMI*/1, /*OtherOpIdx*/2,
        // MIs[3] VOP3Mods:src0:src0_mods
        GIM_CheckIsSameOperand, /*MI*/3, /*OpIdx*/2, /*OtherMI*/1, /*OtherOpIdx*/1,
        GIM_CheckCxxInsnPredicate, /*MI*/0, /*FnId*/GIMT_Encode2(GICXXPred_MI_Predicate_fmaxnum_like_nnan),
        GIM_CheckIsSafeToFold, /*InsnID*/1,
        GIM_CheckIsSafeToFold, /*InsnID*/2,
        GIM_CheckIsSafeToFold, /*InsnID*/3,
        GIM_CheckComplexPattern, /*MI*/1, /*Op*/1, /*Renderer*/GIMT_Encode2(0), GIMT_Encode2(GICP_gi_vop3mods),
        GIM_CheckComplexPattern, /*MI*/1, /*Op*/2, /*Renderer*/GIMT_Encode2(1), GIMT_Encode2(GICP_gi_vop3mods),
        GIM_CheckComplexPattern, /*MI*/2, /*Op*/2, /*Renderer*/GIMT_Encode2(2), GIMT_Encode2(GICP_gi_vop3mods),
        // (fmaxnum:{ *:[f16] } (fminnum:{ *:[f16] } (VOP3Mods:{ *:[f16] } f16:{ *:[f16] }:$src0, i32:{ *:[i32] }:$src0_mods), (VOP3Mods:{ *:[f16] } f16:{ *:[f16] }:$src1, i32:{ *:[i32] }:$src1_mods)), (fminnum_ieee:{ *:[f16] } (fmaxnum_ieee:{ *:[f16] } (VOP3Mods:{ *:[f16] } f16:{ *:[f16] }:$src1, i32:{ *:[i32] }:$src1_mods), (VOP3Mods:{ *:[f16] } f16:{ *:[f16] }:$src0, i32:{ *:[i32] }:$src0_mods)), (VOP3Mods:{ *:[f16] } f16:{ *:[f16] }:$src2, i32:{ *:[i32] }:$src2_mods)))<<P:Predicate_fmaxnum_like_nnan>>  =>  (V_MED3_F16_e64:{ *:[f16] } ?:{ *:[i32] }:$src0_mods, ?:{ *:[f16] }:$src0, ?:{ *:[i32] }:$src1_mods, ?:{ *:[f16] }:$src1, ?:{ *:[i32] }:$src2_mods, ?:{ *:[f16] }:$src2, 0:{ *:[i1] })
        GIR_BuildMI, /*InsnID*/0, /*Opcode*/GIMT_Encode2(AMDGPU::V_MED3_F16_e64),
        GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/0, // DstI[vdst]
        GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/1, // src0_mods
        GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/0, // src0
        GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(1), /*SubOperand*/1, // src1_mods
        GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(1), /*SubOperand*/0, // src1
        GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(2), /*SubOperand*/1, // src2_mods
        GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(2), /*SubOperand*/0, // src2
        GIR_AddImm8, /*InsnID*/0, /*Imm*/0,
        GIR_AddImm8, /*InsnID*/0, /*Imm*/0,
        GIR_AddImm8, /*InsnID*/0, /*Imm*/0,
        GIR_ConstrainSelectedInstOperands, /*InsnID*/0,
        GIR_EraseFromParent, /*InsnID*/0,
        // GIR_Coverage, 10710,
        GIR_Done,
      // Label 4501: @292504
      GIM_Try, /*On fail goto*//*Label 4502*/ GIMT_Encode4(292650), // Rule ID 10713 //
        GIM_CheckFeatures, GIMT_Encode2(GIFBS_isGFX9Plus),
        GIM_CheckRegBankForClass, /*MI*/0, /*Op*/0, /*RC*/GIMT_Encode2(AMDGPU::VGPR_32RegClassID),
        GIM_RecordInsn, /*DefineMI*/1, /*MI*/0, /*OpIdx*/1, // MIs[1]
        GIM_CheckOpcode, /*MI*/1, GIMT_Encode2(TargetOpcode::G_FMINNUM),
        GIM_CheckType, /*MI*/1, /*Op*/1, /*Type*/GILLT_s16,
        GIM_CheckType, /*MI*/1, /*Op*/2, /*Type*/GILLT_s16,
        GIM_RecordInsn, /*DefineMI*/2, /*MI*/0, /*OpIdx*/2, // MIs[2]
        GIM_CheckOpcode, /*MI*/2, GIMT_Encode2(TargetOpcode::G_FMINNUM_IEEE),
        GIM_CheckType, /*MI*/2, /*Op*/1, /*Type*/GILLT_s16,
        GIM_CheckType, /*MI*/2, /*Op*/2, /*Type*/GILLT_s16,
        GIM_RecordInsn, /*DefineMI*/3, /*MI*/2, /*OpIdx*/1, // MIs[3]
        GIM_CheckOpcode, /*MI*/3, GIMT_Encode2(TargetOpcode::G_FMAXNUM_IEEE),
        // MIs[3] VOP3Mods:src0:src0_mods
        GIM_CheckIsSameOperand, /*MI*/3, /*OpIdx*/1, /*OtherMI*/1, /*OtherOpIdx*/2,
        // MIs[3] VOP3Mods:src1:src1_mods
        GIM_CheckIsSameOperand, /*MI*/3, /*OpIdx*/2, /*OtherMI*/1, /*OtherOpIdx*/1,
        GIM_CheckCxxInsnPredicate, /*MI*/0, /*FnId*/GIMT_Encode2(GICXXPred_MI_Predicate_fmaxnum_like_nnan),
        GIM_CheckIsSafeToFold, /*InsnID*/1,
        GIM_CheckIsSafeToFold, /*InsnID*/2,
        GIM_CheckIsSafeToFold, /*InsnID*/3,
        GIM_CheckComplexPattern, /*MI*/1, /*Op*/1, /*Renderer*/GIMT_Encode2(0), GIMT_Encode2(GICP_gi_vop3mods),
        GIM_CheckComplexPattern, /*MI*/1, /*Op*/2, /*Renderer*/GIMT_Encode2(1), GIMT_Encode2(GICP_gi_vop3mods),
        GIM_CheckComplexPattern, /*MI*/2, /*Op*/2, /*Renderer*/GIMT_Encode2(2), GIMT_Encode2(GICP_gi_vop3mods),
        // (fmaxnum:{ *:[f16] } (fminnum:{ *:[f16] } (VOP3Mods:{ *:[f16] } f16:{ *:[f16] }:$src1, i32:{ *:[i32] }:$src1_mods), (VOP3Mods:{ *:[f16] } f16:{ *:[f16] }:$src0, i32:{ *:[i32] }:$src0_mods)), (fminnum_ieee:{ *:[f16] } (fmaxnum_ieee:{ *:[f16] } (VOP3Mods:{ *:[f16] } f16:{ *:[f16] }:$src0, i32:{ *:[i32] }:$src0_mods), (VOP3Mods:{ *:[f16] } f16:{ *:[f16] }:$src1, i32:{ *:[i32] }:$src1_mods)), (VOP3Mods:{ *:[f16] } f16:{ *:[f16] }:$src2, i32:{ *:[i32] }:$src2_mods)))<<P:Predicate_fmaxnum_like_nnan>>  =>  (V_MED3_F16_e64:{ *:[f16] } ?:{ *:[i32] }:$src0_mods, ?:{ *:[f16] }:$src0, ?:{ *:[i32] }:$src1_mods, ?:{ *:[f16] }:$src1, ?:{ *:[i32] }:$src2_mods, ?:{ *:[f16] }:$src2, 0:{ *:[i1] })
        GIR_BuildMI, /*InsnID*/0, /*Opcode*/GIMT_Encode2(AMDGPU::V_MED3_F16_e64),
        GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/0, // DstI[vdst]
        GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(1), /*SubOperand*/1, // src0_mods
        GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(1), /*SubOperand*/0, // src0
        GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/1, // src1_mods
        GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/0, // src1
        GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(2), /*SubOperand*/1, // src2_mods
        GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(2), /*SubOperand*/0, // src2
        GIR_AddImm8, /*InsnID*/0, /*Imm*/0,
        GIR_AddImm8, /*InsnID*/0, /*Imm*/0,
        GIR_AddImm8, /*InsnID*/0, /*Imm*/0,
        GIR_ConstrainSelectedInstOperands, /*InsnID*/0,
        GIR_EraseFromParent, /*InsnID*/0,
        // GIR_Coverage, 10713,
        GIR_Done,
      // Label 4502: @292650
      GIM_Try, /*On fail goto*//*Label 4503*/ GIMT_Encode4(292796), // Rule ID 10714 //
        GIM_CheckFeatures, GIMT_Encode2(GIFBS_isGFX9Plus),
        GIM_CheckRegBankForClass, /*MI*/0, /*Op*/0, /*RC*/GIMT_Encode2(AMDGPU::VGPR_32RegClassID),
        GIM_RecordInsn, /*DefineMI*/1, /*MI*/0, /*OpIdx*/1, // MIs[1]
        GIM_CheckOpcode, /*MI*/1, GIMT_Encode2(TargetOpcode::G_FMINNUM),
        GIM_CheckType, /*MI*/1, /*Op*/1, /*Type*/GILLT_s16,
        GIM_CheckType, /*MI*/1, /*Op*/2, /*Type*/GILLT_s16,
        GIM_RecordInsn, /*DefineMI*/2, /*MI*/0, /*OpIdx*/2, // MIs[2]
        GIM_CheckOpcode, /*MI*/2, GIMT_Encode2(TargetOpcode::G_FMINNUM_IEEE),
        GIM_CheckType, /*MI*/2, /*Op*/1, /*Type*/GILLT_s16,
        GIM_CheckType, /*MI*/2, /*Op*/2, /*Type*/GILLT_s16,
        GIM_RecordInsn, /*DefineMI*/3, /*MI*/2, /*OpIdx*/1, // MIs[3]
        GIM_CheckOpcode, /*MI*/3, GIMT_Encode2(TargetOpcode::G_FMAXNUM_IEEE),
        // MIs[3] VOP3Mods:src1:src1_mods
        GIM_CheckIsSameOperand, /*MI*/3, /*OpIdx*/1, /*OtherMI*/1, /*OtherOpIdx*/1,
        // MIs[3] VOP3Mods:src0:src0_mods
        GIM_CheckIsSameOperand, /*MI*/3, /*OpIdx*/2, /*OtherMI*/1, /*OtherOpIdx*/2,
        GIM_CheckCxxInsnPredicate, /*MI*/0, /*FnId*/GIMT_Encode2(GICXXPred_MI_Predicate_fmaxnum_like_nnan),
        GIM_CheckIsSafeToFold, /*InsnID*/1,
        GIM_CheckIsSafeToFold, /*InsnID*/2,
        GIM_CheckIsSafeToFold, /*InsnID*/3,
        GIM_CheckComplexPattern, /*MI*/1, /*Op*/1, /*Renderer*/GIMT_Encode2(0), GIMT_Encode2(GICP_gi_vop3mods),
        GIM_CheckComplexPattern, /*MI*/1, /*Op*/2, /*Renderer*/GIMT_Encode2(1), GIMT_Encode2(GICP_gi_vop3mods),
        GIM_CheckComplexPattern, /*MI*/2, /*Op*/2, /*Renderer*/GIMT_Encode2(2), GIMT_Encode2(GICP_gi_vop3mods),
        // (fmaxnum:{ *:[f16] } (fminnum:{ *:[f16] } (VOP3Mods:{ *:[f16] } f16:{ *:[f16] }:$src1, i32:{ *:[i32] }:$src1_mods), (VOP3Mods:{ *:[f16] } f16:{ *:[f16] }:$src0, i32:{ *:[i32] }:$src0_mods)), (fminnum_ieee:{ *:[f16] } (fmaxnum_ieee:{ *:[f16] } (VOP3Mods:{ *:[f16] } f16:{ *:[f16] }:$src1, i32:{ *:[i32] }:$src1_mods), (VOP3Mods:{ *:[f16] } f16:{ *:[f16] }:$src0, i32:{ *:[i32] }:$src0_mods)), (VOP3Mods:{ *:[f16] } f16:{ *:[f16] }:$src2, i32:{ *:[i32] }:$src2_mods)))<<P:Predicate_fmaxnum_like_nnan>>  =>  (V_MED3_F16_e64:{ *:[f16] } ?:{ *:[i32] }:$src0_mods, ?:{ *:[f16] }:$src0, ?:{ *:[i32] }:$src1_mods, ?:{ *:[f16] }:$src1, ?:{ *:[i32] }:$src2_mods, ?:{ *:[f16] }:$src2, 0:{ *:[i1] })
        GIR_BuildMI, /*InsnID*/0, /*Opcode*/GIMT_Encode2(AMDGPU::V_MED3_F16_e64),
        GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/0, // DstI[vdst]
        GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(1), /*SubOperand*/1, // src0_mods
        GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(1), /*SubOperand*/0, // src0
        GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/1, // src1_mods
        GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/0, // src1
        GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(2), /*SubOperand*/1, // src2_mods
        GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(2), /*SubOperand*/0, // src2
        GIR_AddImm8, /*InsnID*/0, /*Imm*/0,
        GIR_AddImm8, /*InsnID*/0, /*Imm*/0,
        GIR_AddImm8, /*InsnID*/0, /*Imm*/0,
        GIR_ConstrainSelectedInstOperands, /*InsnID*/0,
        GIR_EraseFromParent, /*InsnID*/0,
        // GIR_Coverage, 10714,
        GIR_Done,
      // Label 4503: @292796
      GIM_Try, /*On fail goto*//*Label 4504*/ GIMT_Encode4(292942), // Rule ID 10766 //
        GIM_CheckFeatures, GIMT_Encode2(GIFBS_isGFX9Plus),
        GIM_CheckRegBankForClass, /*MI*/0, /*Op*/0, /*RC*/GIMT_Encode2(AMDGPU::VGPR_32RegClassID),
        GIM_RecordInsn, /*DefineMI*/1, /*MI*/0, /*OpIdx*/1, // MIs[1]
        GIM_CheckOpcode, /*MI*/1, GIMT_Encode2(TargetOpcode::G_FMINNUM),
        GIM_CheckType, /*MI*/1, /*Op*/1, /*Type*/GILLT_s16,
        GIM_CheckType, /*MI*/1, /*Op*/2, /*Type*/GILLT_s16,
        GIM_RecordInsn, /*DefineMI*/2, /*MI*/1, /*OpIdx*/2, // MIs[2]
        GIM_CheckOpcode, /*MI*/2, GIMT_Encode2(TargetOpcode::G_FMAXNUM),
        GIM_CheckType, /*MI*/2, /*Op*/1, /*Type*/GILLT_s16,
        GIM_CheckType, /*MI*/2, /*Op*/2, /*Type*/GILLT_s16,
        GIM_RecordInsn, /*DefineMI*/3, /*MI*/0, /*OpIdx*/2, // MIs[3]
        GIM_CheckOpcode, /*MI*/3, GIMT_Encode2(TargetOpcode::G_FMINNUM),
        // MIs[3] VOP3Mods:src0:src0_mods
        GIM_CheckIsSameOperand, /*MI*/3, /*OpIdx*/1, /*OtherMI*/2, /*OtherOpIdx*/1,
        // MIs[3] VOP3Mods:src1:src1_mods
        GIM_CheckIsSameOperand, /*MI*/3, /*OpIdx*/2, /*OtherMI*/2, /*OtherOpIdx*/2,
        GIM_CheckCxxInsnPredicate, /*MI*/0, /*FnId*/GIMT_Encode2(GICXXPred_MI_Predicate_fmaxnum_like_nnan),
        GIM_CheckIsSafeToFold, /*InsnID*/1,
        GIM_CheckIsSafeToFold, /*InsnID*/2,
        GIM_CheckIsSafeToFold, /*InsnID*/3,
        GIM_CheckComplexPattern, /*MI*/1, /*Op*/1, /*Renderer*/GIMT_Encode2(0), GIMT_Encode2(GICP_gi_vop3mods),
        GIM_CheckComplexPattern, /*MI*/2, /*Op*/1, /*Renderer*/GIMT_Encode2(1), GIMT_Encode2(GICP_gi_vop3mods),
        GIM_CheckComplexPattern, /*MI*/2, /*Op*/2, /*Renderer*/GIMT_Encode2(2), GIMT_Encode2(GICP_gi_vop3mods),
        // (fmaxnum:{ *:[f16] } (fminnum:{ *:[f16] } (VOP3Mods:{ *:[f16] } f16:{ *:[f16] }:$src2, i32:{ *:[i32] }:$src2_mods), (fmaxnum:{ *:[f16] } (VOP3Mods:{ *:[f16] } f16:{ *:[f16] }:$src0, i32:{ *:[i32] }:$src0_mods), (VOP3Mods:{ *:[f16] } f16:{ *:[f16] }:$src1, i32:{ *:[i32] }:$src1_mods))), (fminnum:{ *:[f16] } (VOP3Mods:{ *:[f16] } f16:{ *:[f16] }:$src0, i32:{ *:[i32] }:$src0_mods), (VOP3Mods:{ *:[f16] } f16:{ *:[f16] }:$src1, i32:{ *:[i32] }:$src1_mods)))<<P:Predicate_fmaxnum_like_nnan>>  =>  (V_MED3_F16_e64:{ *:[f16] } ?:{ *:[i32] }:$src0_mods, ?:{ *:[f16] }:$src0, ?:{ *:[i32] }:$src1_mods, ?:{ *:[f16] }:$src1, ?:{ *:[i32] }:$src2_mods, ?:{ *:[f16] }:$src2, 0:{ *:[i1] })
        GIR_BuildMI, /*InsnID*/0, /*Opcode*/GIMT_Encode2(AMDGPU::V_MED3_F16_e64),
        GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/0, // DstI[vdst]
        GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(1), /*SubOperand*/1, // src0_mods
        GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(1), /*SubOperand*/0, // src0
        GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(2), /*SubOperand*/1, // src1_mods
        GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(2), /*SubOperand*/0, // src1
        GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/1, // src2_mods
        GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/0, // src2
        GIR_AddImm8, /*InsnID*/0, /*Imm*/0,
        GIR_AddImm8, /*InsnID*/0, /*Imm*/0,
        GIR_AddImm8, /*InsnID*/0, /*Imm*/0,
        GIR_ConstrainSelectedInstOperands, /*InsnID*/0,
        GIR_EraseFromParent, /*InsnID*/0,
        // GIR_Coverage, 10766,
        GIR_Done,
      // Label 4504: @292942
      GIM_Try, /*On fail goto*//*Label 4505*/ GIMT_Encode4(293088), // Rule ID 10767 //
        GIM_CheckFeatures, GIMT_Encode2(GIFBS_isGFX9Plus),
        GIM_CheckRegBankForClass, /*MI*/0, /*Op*/0, /*RC*/GIMT_Encode2(AMDGPU::VGPR_32RegClassID),
        GIM_RecordInsn, /*DefineMI*/1, /*MI*/0, /*OpIdx*/1, // MIs[1]
        GIM_CheckOpcode, /*MI*/1, GIMT_Encode2(TargetOpcode::G_FMINNUM),
        GIM_CheckType, /*MI*/1, /*Op*/1, /*Type*/GILLT_s16,
        GIM_CheckType, /*MI*/1, /*Op*/2, /*Type*/GILLT_s16,
        GIM_RecordInsn, /*DefineMI*/2, /*MI*/1, /*OpIdx*/2, // MIs[2]
        GIM_CheckOpcode, /*MI*/2, GIMT_Encode2(TargetOpcode::G_FMAXNUM),
        GIM_CheckType, /*MI*/2, /*Op*/1, /*Type*/GILLT_s16,
        GIM_CheckType, /*MI*/2, /*Op*/2, /*Type*/GILLT_s16,
        GIM_RecordInsn, /*DefineMI*/3, /*MI*/0, /*OpIdx*/2, // MIs[3]
        GIM_CheckOpcode, /*MI*/3, GIMT_Encode2(TargetOpcode::G_FMINNUM),
        // MIs[3] VOP3Mods:src1:src1_mods
        GIM_CheckIsSameOperand, /*MI*/3, /*OpIdx*/1, /*OtherMI*/2, /*OtherOpIdx*/2,
        // MIs[3] VOP3Mods:src0:src0_mods
        GIM_CheckIsSameOperand, /*MI*/3, /*OpIdx*/2, /*OtherMI*/2, /*OtherOpIdx*/1,
        GIM_CheckCxxInsnPredicate, /*MI*/0, /*FnId*/GIMT_Encode2(GICXXPred_MI_Predicate_fmaxnum_like_nnan),
        GIM_CheckIsSafeToFold, /*InsnID*/1,
        GIM_CheckIsSafeToFold, /*InsnID*/2,
        GIM_CheckIsSafeToFold, /*InsnID*/3,
        GIM_CheckComplexPattern, /*MI*/1, /*Op*/1, /*Renderer*/GIMT_Encode2(0), GIMT_Encode2(GICP_gi_vop3mods),
        GIM_CheckComplexPattern, /*MI*/2, /*Op*/1, /*Renderer*/GIMT_Encode2(1), GIMT_Encode2(GICP_gi_vop3mods),
        GIM_CheckComplexPattern, /*MI*/2, /*Op*/2, /*Renderer*/GIMT_Encode2(2), GIMT_Encode2(GICP_gi_vop3mods),
        // (fmaxnum:{ *:[f16] } (fminnum:{ *:[f16] } (VOP3Mods:{ *:[f16] } f16:{ *:[f16] }:$src2, i32:{ *:[i32] }:$src2_mods), (fmaxnum:{ *:[f16] } (VOP3Mods:{ *:[f16] } f16:{ *:[f16] }:$src0, i32:{ *:[i32] }:$src0_mods), (VOP3Mods:{ *:[f16] } f16:{ *:[f16] }:$src1, i32:{ *:[i32] }:$src1_mods))), (fminnum:{ *:[f16] } (VOP3Mods:{ *:[f16] } f16:{ *:[f16] }:$src1, i32:{ *:[i32] }:$src1_mods), (VOP3Mods:{ *:[f16] } f16:{ *:[f16] }:$src0, i32:{ *:[i32] }:$src0_mods)))<<P:Predicate_fmaxnum_like_nnan>>  =>  (V_MED3_F16_e64:{ *:[f16] } ?:{ *:[i32] }:$src0_mods, ?:{ *:[f16] }:$src0, ?:{ *:[i32] }:$src1_mods, ?:{ *:[f16] }:$src1, ?:{ *:[i32] }:$src2_mods, ?:{ *:[f16] }:$src2, 0:{ *:[i1] })
        GIR_BuildMI, /*InsnID*/0, /*Opcode*/GIMT_Encode2(AMDGPU::V_MED3_F16_e64),
        GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/0, // DstI[vdst]
        GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(1), /*SubOperand*/1, // src0_mods
        GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(1), /*SubOperand*/0, // src0
        GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(2), /*SubOperand*/1, // src1_mods
        GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(2), /*SubOperand*/0, // src1
        GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/1, // src2_mods
        GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/0, // src2
        GIR_AddImm8, /*InsnID*/0, /*Imm*/0,
        GIR_AddImm8, /*InsnID*/0, /*Imm*/0,
        GIR_AddImm8, /*InsnID*/0, /*Imm*/0,
        GIR_ConstrainSelectedInstOperands, /*InsnID*/0,
        GIR_EraseFromParent, /*InsnID*/0,
        // GIR_Coverage, 10767,
        GIR_Done,
      // Label 4505: @293088
      GIM_Try, /*On fail goto*//*Label 4506*/ GIMT_Encode4(293234), // Rule ID 10768 //
        GIM_CheckFeatures, GIMT_Encode2(GIFBS_isGFX9Plus),
        GIM_CheckRegBankForClass, /*MI*/0, /*Op*/0, /*RC*/GIMT_Encode2(AMDGPU::VGPR_32RegClassID),
        GIM_RecordInsn, /*DefineMI*/1, /*MI*/0, /*OpIdx*/1, // MIs[1]
        GIM_CheckOpcode, /*MI*/1, GIMT_Encode2(TargetOpcode::G_FMINNUM),
        GIM_CheckType, /*MI*/1, /*Op*/1, /*Type*/GILLT_s16,
        GIM_CheckType, /*MI*/1, /*Op*/2, /*Type*/GILLT_s16,
        GIM_RecordInsn, /*DefineMI*/2, /*MI*/1, /*OpIdx*/2, // MIs[2]
        GIM_CheckOpcode, /*MI*/2, GIMT_Encode2(TargetOpcode::G_FMAXNUM),
        GIM_CheckType, /*MI*/2, /*Op*/1, /*Type*/GILLT_s16,
        GIM_CheckType, /*MI*/2, /*Op*/2, /*Type*/GILLT_s16,
        GIM_RecordInsn, /*DefineMI*/3, /*MI*/0, /*OpIdx*/2, // MIs[3]
        GIM_CheckOpcode, /*MI*/3, GIMT_Encode2(TargetOpcode::G_FMINNUM),
        // MIs[3] VOP3Mods:src0:src0_mods
        GIM_CheckIsSameOperand, /*MI*/3, /*OpIdx*/1, /*OtherMI*/2, /*OtherOpIdx*/2,
        // MIs[3] VOP3Mods:src1:src1_mods
        GIM_CheckIsSameOperand, /*MI*/3, /*OpIdx*/2, /*OtherMI*/2, /*OtherOpIdx*/1,
        GIM_CheckCxxInsnPredicate, /*MI*/0, /*FnId*/GIMT_Encode2(GICXXPred_MI_Predicate_fmaxnum_like_nnan),
        GIM_CheckIsSafeToFold, /*InsnID*/1,
        GIM_CheckIsSafeToFold, /*InsnID*/2,
        GIM_CheckIsSafeToFold, /*InsnID*/3,
        GIM_CheckComplexPattern, /*MI*/1, /*Op*/1, /*Renderer*/GIMT_Encode2(0), GIMT_Encode2(GICP_gi_vop3mods),
        GIM_CheckComplexPattern, /*MI*/2, /*Op*/1, /*Renderer*/GIMT_Encode2(1), GIMT_Encode2(GICP_gi_vop3mods),
        GIM_CheckComplexPattern, /*MI*/2, /*Op*/2, /*Renderer*/GIMT_Encode2(2), GIMT_Encode2(GICP_gi_vop3mods),
        // (fmaxnum:{ *:[f16] } (fminnum:{ *:[f16] } (VOP3Mods:{ *:[f16] } f16:{ *:[f16] }:$src2, i32:{ *:[i32] }:$src2_mods), (fmaxnum:{ *:[f16] } (VOP3Mods:{ *:[f16] } f16:{ *:[f16] }:$src1, i32:{ *:[i32] }:$src1_mods), (VOP3Mods:{ *:[f16] } f16:{ *:[f16] }:$src0, i32:{ *:[i32] }:$src0_mods))), (fminnum:{ *:[f16] } (VOP3Mods:{ *:[f16] } f16:{ *:[f16] }:$src0, i32:{ *:[i32] }:$src0_mods), (VOP3Mods:{ *:[f16] } f16:{ *:[f16] }:$src1, i32:{ *:[i32] }:$src1_mods)))<<P:Predicate_fmaxnum_like_nnan>>  =>  (V_MED3_F16_e64:{ *:[f16] } ?:{ *:[i32] }:$src0_mods, ?:{ *:[f16] }:$src0, ?:{ *:[i32] }:$src1_mods, ?:{ *:[f16] }:$src1, ?:{ *:[i32] }:$src2_mods, ?:{ *:[f16] }:$src2, 0:{ *:[i1] })
        GIR_BuildMI, /*InsnID*/0, /*Opcode*/GIMT_Encode2(AMDGPU::V_MED3_F16_e64),
        GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/0, // DstI[vdst]
        GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(2), /*SubOperand*/1, // src0_mods
        GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(2), /*SubOperand*/0, // src0
        GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(1), /*SubOperand*/1, // src1_mods
        GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(1), /*SubOperand*/0, // src1
        GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/1, // src2_mods
        GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/0, // src2
        GIR_AddImm8, /*InsnID*/0, /*Imm*/0,
        GIR_AddImm8, /*InsnID*/0, /*Imm*/0,
        GIR_AddImm8, /*InsnID*/0, /*Imm*/0,
        GIR_ConstrainSelectedInstOperands, /*InsnID*/0,
        GIR_EraseFromParent, /*InsnID*/0,
        // GIR_Coverage, 10768,
        GIR_Done,
      // Label 4506: @293234
      GIM_Try, /*On fail goto*//*Label 4507*/ GIMT_Encode4(293380), // Rule ID 10769 //
        GIM_CheckFeatures, GIMT_Encode2(GIFBS_isGFX9Plus),
        GIM_CheckRegBankForClass, /*MI*/0, /*Op*/0, /*RC*/GIMT_Encode2(AMDGPU::VGPR_32RegClassID),
        GIM_RecordInsn, /*DefineMI*/1, /*MI*/0, /*OpIdx*/1, // MIs[1]
        GIM_CheckOpcode, /*MI*/1, GIMT_Encode2(TargetOpcode::G_FMINNUM),
        GIM_CheckType, /*MI*/1, /*Op*/1, /*Type*/GILLT_s16,
        GIM_CheckType, /*MI*/1, /*Op*/2, /*Type*/GILLT_s16,
        GIM_RecordInsn, /*DefineMI*/2, /*MI*/1, /*OpIdx*/2, // MIs[2]
        GIM_CheckOpcode, /*MI*/2, GIMT_Encode2(TargetOpcode::G_FMAXNUM),
        GIM_CheckType, /*MI*/2, /*Op*/1, /*Type*/GILLT_s16,
        GIM_CheckType, /*MI*/2, /*Op*/2, /*Type*/GILLT_s16,
        GIM_RecordInsn, /*DefineMI*/3, /*MI*/0, /*OpIdx*/2, // MIs[3]
        GIM_CheckOpcode, /*MI*/3, GIMT_Encode2(TargetOpcode::G_FMINNUM),
        // MIs[3] VOP3Mods:src1:src1_mods
        GIM_CheckIsSameOperand, /*MI*/3, /*OpIdx*/1, /*OtherMI*/2, /*OtherOpIdx*/1,
        // MIs[3] VOP3Mods:src0:src0_mods
        GIM_CheckIsSameOperand, /*MI*/3, /*OpIdx*/2, /*OtherMI*/2, /*OtherOpIdx*/2,
        GIM_CheckCxxInsnPredicate, /*MI*/0, /*FnId*/GIMT_Encode2(GICXXPred_MI_Predicate_fmaxnum_like_nnan),
        GIM_CheckIsSafeToFold, /*InsnID*/1,
        GIM_CheckIsSafeToFold, /*InsnID*/2,
        GIM_CheckIsSafeToFold, /*InsnID*/3,
        GIM_CheckComplexPattern, /*MI*/1, /*Op*/1, /*Renderer*/GIMT_Encode2(0), GIMT_Encode2(GICP_gi_vop3mods),
        GIM_CheckComplexPattern, /*MI*/2, /*Op*/1, /*Renderer*/GIMT_Encode2(1), GIMT_Encode2(GICP_gi_vop3mods),
        GIM_CheckComplexPattern, /*MI*/2, /*Op*/2, /*Renderer*/GIMT_Encode2(2), GIMT_Encode2(GICP_gi_vop3mods),
        // (fmaxnum:{ *:[f16] } (fminnum:{ *:[f16] } (VOP3Mods:{ *:[f16] } f16:{ *:[f16] }:$src2, i32:{ *:[i32] }:$src2_mods), (fmaxnum:{ *:[f16] } (VOP3Mods:{ *:[f16] } f16:{ *:[f16] }:$src1, i32:{ *:[i32] }:$src1_mods), (VOP3Mods:{ *:[f16] } f16:{ *:[f16] }:$src0, i32:{ *:[i32] }:$src0_mods))), (fminnum:{ *:[f16] } (VOP3Mods:{ *:[f16] } f16:{ *:[f16] }:$src1, i32:{ *:[i32] }:$src1_mods), (VOP3Mods:{ *:[f16] } f16:{ *:[f16] }:$src0, i32:{ *:[i32] }:$src0_mods)))<<P:Predicate_fmaxnum_like_nnan>>  =>  (V_MED3_F16_e64:{ *:[f16] } ?:{ *:[i32] }:$src0_mods, ?:{ *:[f16] }:$src0, ?:{ *:[i32] }:$src1_mods, ?:{ *:[f16] }:$src1, ?:{ *:[i32] }:$src2_mods, ?:{ *:[f16] }:$src2, 0:{ *:[i1] })
        GIR_BuildMI, /*InsnID*/0, /*Opcode*/GIMT_Encode2(AMDGPU::V_MED3_F16_e64),
        GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/0, // DstI[vdst]
        GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(2), /*SubOperand*/1, // src0_mods
        GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(2), /*SubOperand*/0, // src0
        GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(1), /*SubOperand*/1, // src1_mods
        GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(1), /*SubOperand*/0, // src1
        GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/1, // src2_mods
        GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/0, // src2
        GIR_AddImm8, /*InsnID*/0, /*Imm*/0,
        GIR_AddImm8, /*InsnID*/0, /*Imm*/0,
        GIR_AddImm8, /*InsnID*/0, /*Imm*/0,
        GIR_ConstrainSelectedInstOperands, /*InsnID*/0,
        GIR_EraseFromParent, /*InsnID*/0,
        // GIR_Coverage, 10769,
        GIR_Done,
      // Label 4507: @293380
      GIM_Try, /*On fail goto*//*Label 4508*/ GIMT_Encode4(293526), // Rule ID 10706 //
        GIM_CheckFeatures, GIMT_Encode2(GIFBS_isGFX9Plus),
        GIM_CheckRegBankForClass, /*MI*/0, /*Op*/0, /*RC*/GIMT_Encode2(AMDGPU::VGPR_32RegClassID),
        GIM_RecordInsn, /*DefineMI*/1, /*MI*/0, /*OpIdx*/1, // MIs[1]
        GIM_CheckOpcode, /*MI*/1, GIMT_Encode2(TargetOpcode::G_FMINNUM),
        GIM_CheckType, /*MI*/1, /*Op*/1, /*Type*/GILLT_s16,
        GIM_CheckType, /*MI*/1, /*Op*/2, /*Type*/GILLT_s16,
        GIM_RecordInsn, /*DefineMI*/2, /*MI*/1, /*OpIdx*/2, // MIs[2]
        GIM_CheckOpcode, /*MI*/2, GIMT_Encode2(TargetOpcode::G_FMAXNUM),
        GIM_CheckType, /*MI*/2, /*Op*/1, /*Type*/GILLT_s16,
        GIM_CheckType, /*MI*/2, /*Op*/2, /*Type*/GILLT_s16,
        GIM_RecordInsn, /*DefineMI*/3, /*MI*/0, /*OpIdx*/2, // MIs[3]
        GIM_CheckOpcode, /*MI*/3, GIMT_Encode2(TargetOpcode::G_FMINNUM_IEEE),
        // MIs[3] VOP3Mods:src0:src0_mods
        GIM_CheckIsSameOperand, /*MI*/3, /*OpIdx*/1, /*OtherMI*/2, /*OtherOpIdx*/1,
        // MIs[3] VOP3Mods:src1:src1_mods
        GIM_CheckIsSameOperand, /*MI*/3, /*OpIdx*/2, /*OtherMI*/2, /*OtherOpIdx*/2,
        GIM_CheckCxxInsnPredicate, /*MI*/0, /*FnId*/GIMT_Encode2(GICXXPred_MI_Predicate_fmaxnum_like_nnan),
        GIM_CheckIsSafeToFold, /*InsnID*/1,
        GIM_CheckIsSafeToFold, /*InsnID*/2,
        GIM_CheckIsSafeToFold, /*InsnID*/3,
        GIM_CheckComplexPattern, /*MI*/1, /*Op*/1, /*Renderer*/GIMT_Encode2(0), GIMT_Encode2(GICP_gi_vop3mods),
        GIM_CheckComplexPattern, /*MI*/2, /*Op*/1, /*Renderer*/GIMT_Encode2(1), GIMT_Encode2(GICP_gi_vop3mods),
        GIM_CheckComplexPattern, /*MI*/2, /*Op*/2, /*Renderer*/GIMT_Encode2(2), GIMT_Encode2(GICP_gi_vop3mods),
        // (fmaxnum:{ *:[f16] } (fminnum:{ *:[f16] } (VOP3Mods:{ *:[f16] } f16:{ *:[f16] }:$src2, i32:{ *:[i32] }:$src2_mods), (fmaxnum:{ *:[f16] } (VOP3Mods:{ *:[f16] } f16:{ *:[f16] }:$src0, i32:{ *:[i32] }:$src0_mods), (VOP3Mods:{ *:[f16] } f16:{ *:[f16] }:$src1, i32:{ *:[i32] }:$src1_mods))), (fminnum_ieee:{ *:[f16] } (VOP3Mods:{ *:[f16] } f16:{ *:[f16] }:$src0, i32:{ *:[i32] }:$src0_mods), (VOP3Mods:{ *:[f16] } f16:{ *:[f16] }:$src1, i32:{ *:[i32] }:$src1_mods)))<<P:Predicate_fmaxnum_like_nnan>>  =>  (V_MED3_F16_e64:{ *:[f16] } ?:{ *:[i32] }:$src0_mods, ?:{ *:[f16] }:$src0, ?:{ *:[i32] }:$src1_mods, ?:{ *:[f16] }:$src1, ?:{ *:[i32] }:$src2_mods, ?:{ *:[f16] }:$src2, 0:{ *:[i1] })
        GIR_BuildMI, /*InsnID*/0, /*Opcode*/GIMT_Encode2(AMDGPU::V_MED3_F16_e64),
        GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/0, // DstI[vdst]
        GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(1), /*SubOperand*/1, // src0_mods
        GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(1), /*SubOperand*/0, // src0
        GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(2), /*SubOperand*/1, // src1_mods
        GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(2), /*SubOperand*/0, // src1
        GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/1, // src2_mods
        GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/0, // src2
        GIR_AddImm8, /*InsnID*/0, /*Imm*/0,
        GIR_AddImm8, /*InsnID*/0, /*Imm*/0,
        GIR_AddImm8, /*InsnID*/0, /*Imm*/0,
        GIR_ConstrainSelectedInstOperands, /*InsnID*/0,
        GIR_EraseFromParent, /*InsnID*/0,
        // GIR_Coverage, 10706,
        GIR_Done,
      // Label 4508: @293526
      GIM_Try, /*On fail goto*//*Label 4509*/ GIMT_Encode4(293672), // Rule ID 10707 //
        GIM_CheckFeatures, GIMT_Encode2(GIFBS_isGFX9Plus),
        GIM_CheckRegBankForClass, /*MI*/0, /*Op*/0, /*RC*/GIMT_Encode2(AMDGPU::VGPR_32RegClassID),
        GIM_RecordInsn, /*DefineMI*/1, /*MI*/0, /*OpIdx*/1, // MIs[1]
        GIM_CheckOpcode, /*MI*/1, GIMT_Encode2(TargetOpcode::G_FMINNUM),
        GIM_CheckType, /*MI*/1, /*Op*/1, /*Type*/GILLT_s16,
        GIM_CheckType, /*MI*/1, /*Op*/2, /*Type*/GILLT_s16,
        GIM_RecordInsn, /*DefineMI*/2, /*MI*/1, /*OpIdx*/2, // MIs[2]
        GIM_CheckOpcode, /*MI*/2, GIMT_Encode2(TargetOpcode::G_FMAXNUM),
        GIM_CheckType, /*MI*/2, /*Op*/1, /*Type*/GILLT_s16,
        GIM_CheckType, /*MI*/2, /*Op*/2, /*Type*/GILLT_s16,
        GIM_RecordInsn, /*DefineMI*/3, /*MI*/0, /*OpIdx*/2, // MIs[3]
        GIM_CheckOpcode, /*MI*/3, GIMT_Encode2(TargetOpcode::G_FMINNUM_IEEE),
        // MIs[3] VOP3Mods:src1:src1_mods
        GIM_CheckIsSameOperand, /*MI*/3, /*OpIdx*/1, /*OtherMI*/2, /*OtherOpIdx*/2,
        // MIs[3] VOP3Mods:src0:src0_mods
        GIM_CheckIsSameOperand, /*MI*/3, /*OpIdx*/2, /*OtherMI*/2, /*OtherOpIdx*/1,
        GIM_CheckCxxInsnPredicate, /*MI*/0, /*FnId*/GIMT_Encode2(GICXXPred_MI_Predicate_fmaxnum_like_nnan),
        GIM_CheckIsSafeToFold, /*InsnID*/1,
        GIM_CheckIsSafeToFold, /*InsnID*/2,
        GIM_CheckIsSafeToFold, /*InsnID*/3,
        GIM_CheckComplexPattern, /*MI*/1, /*Op*/1, /*Renderer*/GIMT_Encode2(0), GIMT_Encode2(GICP_gi_vop3mods),
        GIM_CheckComplexPattern, /*MI*/2, /*Op*/1, /*Renderer*/GIMT_Encode2(1), GIMT_Encode2(GICP_gi_vop3mods),
        GIM_CheckComplexPattern, /*MI*/2, /*Op*/2, /*Renderer*/GIMT_Encode2(2), GIMT_Encode2(GICP_gi_vop3mods),
        // (fmaxnum:{ *:[f16] } (fminnum:{ *:[f16] } (VOP3Mods:{ *:[f16] } f16:{ *:[f16] }:$src2, i32:{ *:[i32] }:$src2_mods), (fmaxnum:{ *:[f16] } (VOP3Mods:{ *:[f16] } f16:{ *:[f16] }:$src0, i32:{ *:[i32] }:$src0_mods), (VOP3Mods:{ *:[f16] } f16:{ *:[f16] }:$src1, i32:{ *:[i32] }:$src1_mods))), (fminnum_ieee:{ *:[f16] } (VOP3Mods:{ *:[f16] } f16:{ *:[f16] }:$src1, i32:{ *:[i32] }:$src1_mods), (VOP3Mods:{ *:[f16] } f16:{ *:[f16] }:$src0, i32:{ *:[i32] }:$src0_mods)))<<P:Predicate_fmaxnum_like_nnan>>  =>  (V_MED3_F16_e64:{ *:[f16] } ?:{ *:[i32] }:$src0_mods, ?:{ *:[f16] }:$src0, ?:{ *:[i32] }:$src1_mods, ?:{ *:[f16] }:$src1, ?:{ *:[i32] }:$src2_mods, ?:{ *:[f16] }:$src2, 0:{ *:[i1] })
        GIR_BuildMI, /*InsnID*/0, /*Opcode*/GIMT_Encode2(AMDGPU::V_MED3_F16_e64),
        GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/0, // DstI[vdst]
        GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(1), /*SubOperand*/1, // src0_mods
        GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(1), /*SubOperand*/0, // src0
        GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(2), /*SubOperand*/1, // src1_mods
        GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(2), /*SubOperand*/0, // src1
        GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/1, // src2_mods
        GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/0, // src2
        GIR_AddImm8, /*InsnID*/0, /*Imm*/0,
        GIR_AddImm8, /*InsnID*/0, /*Imm*/0,
        GIR_AddImm8, /*InsnID*/0, /*Imm*/0,
        GIR_ConstrainSelectedInstOperands, /*InsnID*/0,
        GIR_EraseFromParent, /*InsnID*/0,
        // GIR_Coverage, 10707,
        GIR_Done,
      // Label 4509: @293672
      GIM_Try, /*On fail goto*//*Label 4510*/ GIMT_Encode4(293818), // Rule ID 10708 //
        GIM_CheckFeatures, GIMT_Encode2(GIFBS_isGFX9Plus),
        GIM_CheckRegBankForClass, /*MI*/0, /*Op*/0, /*RC*/GIMT_Encode2(AMDGPU::VGPR_32RegClassID),
        GIM_RecordInsn, /*DefineMI*/1, /*MI*/0, /*OpIdx*/1, // MIs[1]
        GIM_CheckOpcode, /*MI*/1, GIMT_Encode2(TargetOpcode::G_FMINNUM),
        GIM_CheckType, /*MI*/1, /*Op*/1, /*Type*/GILLT_s16,
        GIM_CheckType, /*MI*/1, /*Op*/2, /*Type*/GILLT_s16,
        GIM_RecordInsn, /*DefineMI*/2, /*MI*/1, /*OpIdx*/2, // MIs[2]
        GIM_CheckOpcode, /*MI*/2, GIMT_Encode2(TargetOpcode::G_FMAXNUM),
        GIM_CheckType, /*MI*/2, /*Op*/1, /*Type*/GILLT_s16,
        GIM_CheckType, /*MI*/2, /*Op*/2, /*Type*/GILLT_s16,
        GIM_RecordInsn, /*DefineMI*/3, /*MI*/0, /*OpIdx*/2, // MIs[3]
        GIM_CheckOpcode, /*MI*/3, GIMT_Encode2(TargetOpcode::G_FMINNUM_IEEE),
        // MIs[3] VOP3Mods:src0:src0_mods
        GIM_CheckIsSameOperand, /*MI*/3, /*OpIdx*/1, /*OtherMI*/2, /*OtherOpIdx*/2,
        // MIs[3] VOP3Mods:src1:src1_mods
        GIM_CheckIsSameOperand, /*MI*/3, /*OpIdx*/2, /*OtherMI*/2, /*OtherOpIdx*/1,
        GIM_CheckCxxInsnPredicate, /*MI*/0, /*FnId*/GIMT_Encode2(GICXXPred_MI_Predicate_fmaxnum_like_nnan),
        GIM_CheckIsSafeToFold, /*InsnID*/1,
        GIM_CheckIsSafeToFold, /*InsnID*/2,
        GIM_CheckIsSafeToFold, /*InsnID*/3,
        GIM_CheckComplexPattern, /*MI*/1, /*Op*/1, /*Renderer*/GIMT_Encode2(0), GIMT_Encode2(GICP_gi_vop3mods),
        GIM_CheckComplexPattern, /*MI*/2, /*Op*/1, /*Renderer*/GIMT_Encode2(1), GIMT_Encode2(GICP_gi_vop3mods),
        GIM_CheckComplexPattern, /*MI*/2, /*Op*/2, /*Renderer*/GIMT_Encode2(2), GIMT_Encode2(GICP_gi_vop3mods),
        // (fmaxnum:{ *:[f16] } (fminnum:{ *:[f16] } (VOP3Mods:{ *:[f16] } f16:{ *:[f16] }:$src2, i32:{ *:[i32] }:$src2_mods), (fmaxnum:{ *:[f16] } (VOP3Mods:{ *:[f16] } f16:{ *:[f16] }:$src1, i32:{ *:[i32] }:$src1_mods), (VOP3Mods:{ *:[f16] } f16:{ *:[f16] }:$src0, i32:{ *:[i32] }:$src0_mods))), (fminnum_ieee:{ *:[f16] } (VOP3Mods:{ *:[f16] } f16:{ *:[f16] }:$src0, i32:{ *:[i32] }:$src0_mods), (VOP3Mods:{ *:[f16] } f16:{ *:[f16] }:$src1, i32:{ *:[i32] }:$src1_mods)))<<P:Predicate_fmaxnum_like_nnan>>  =>  (V_MED3_F16_e64:{ *:[f16] } ?:{ *:[i32] }:$src0_mods, ?:{ *:[f16] }:$src0, ?:{ *:[i32] }:$src1_mods, ?:{ *:[f16] }:$src1, ?:{ *:[i32] }:$src2_mods, ?:{ *:[f16] }:$src2, 0:{ *:[i1] })
        GIR_BuildMI, /*InsnID*/0, /*Opcode*/GIMT_Encode2(AMDGPU::V_MED3_F16_e64),
        GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/0, // DstI[vdst]
        GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(2), /*SubOperand*/1, // src0_mods
        GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(2), /*SubOperand*/0, // src0
        GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(1), /*SubOperand*/1, // src1_mods
        GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(1), /*SubOperand*/0, // src1
        GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/1, // src2_mods
        GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/0, // src2
        GIR_AddImm8, /*InsnID*/0, /*Imm*/0,
        GIR_AddImm8, /*InsnID*/0, /*Imm*/0,
        GIR_AddImm8, /*InsnID*/0, /*Imm*/0,
        GIR_ConstrainSelectedInstOperands, /*InsnID*/0,
        GIR_EraseFromParent, /*InsnID*/0,
        // GIR_Coverage, 10708,
        GIR_Done,
      // Label 4510: @293818
      GIM_Try, /*On fail goto*//*Label 4511*/ GIMT_Encode4(293964), // Rule ID 10709 //
        GIM_CheckFeatures, GIMT_Encode2(GIFBS_isGFX9Plus),
        GIM_CheckRegBankForClass, /*MI*/0, /*Op*/0, /*RC*/GIMT_Encode2(AMDGPU::VGPR_32RegClassID),
        GIM_RecordInsn, /*DefineMI*/1, /*MI*/0, /*OpIdx*/1, // MIs[1]
        GIM_CheckOpcode, /*MI*/1, GIMT_Encode2(TargetOpcode::G_FMINNUM),
        GIM_CheckType, /*MI*/1, /*Op*/1, /*Type*/GILLT_s16,
        GIM_CheckType, /*MI*/1, /*Op*/2, /*Type*/GILLT_s16,
        GIM_RecordInsn, /*DefineMI*/2, /*MI*/1, /*OpIdx*/2, // MIs[2]
        GIM_CheckOpcode, /*MI*/2, GIMT_Encode2(TargetOpcode::G_FMAXNUM),
        GIM_CheckType, /*MI*/2, /*Op*/1, /*Type*/GILLT_s16,
        GIM_CheckType, /*MI*/2, /*Op*/2, /*Type*/GILLT_s16,
        GIM_RecordInsn, /*DefineMI*/3, /*MI*/0, /*OpIdx*/2, // MIs[3]
        GIM_CheckOpcode, /*MI*/3, GIMT_Encode2(TargetOpcode::G_FMINNUM_IEEE),
        // MIs[3] VOP3Mods:src1:src1_mods
        GIM_CheckIsSameOperand, /*MI*/3, /*OpIdx*/1, /*OtherMI*/2, /*OtherOpIdx*/1,
        // MIs[3] VOP3Mods:src0:src0_mods
        GIM_CheckIsSameOperand, /*MI*/3, /*OpIdx*/2, /*OtherMI*/2, /*OtherOpIdx*/2,
        GIM_CheckCxxInsnPredicate, /*MI*/0, /*FnId*/GIMT_Encode2(GICXXPred_MI_Predicate_fmaxnum_like_nnan),
        GIM_CheckIsSafeToFold, /*InsnID*/1,
        GIM_CheckIsSafeToFold, /*InsnID*/2,
        GIM_CheckIsSafeToFold, /*InsnID*/3,
        GIM_CheckComplexPattern, /*MI*/1, /*Op*/1, /*Renderer*/GIMT_Encode2(0), GIMT_Encode2(GICP_gi_vop3mods),
        GIM_CheckComplexPattern, /*MI*/2, /*Op*/1, /*Renderer*/GIMT_Encode2(1), GIMT_Encode2(GICP_gi_vop3mods),
        GIM_CheckComplexPattern, /*MI*/2, /*Op*/2, /*Renderer*/GIMT_Encode2(2), GIMT_Encode2(GICP_gi_vop3mods),
        // (fmaxnum:{ *:[f16] } (fminnum:{ *:[f16] } (VOP3Mods:{ *:[f16] } f16:{ *:[f16] }:$src2, i32:{ *:[i32] }:$src2_mods), (fmaxnum:{ *:[f16] } (VOP3Mods:{ *:[f16] } f16:{ *:[f16] }:$src1, i32:{ *:[i32] }:$src1_mods), (VOP3Mods:{ *:[f16] } f16:{ *:[f16] }:$src0, i32:{ *:[i32] }:$src0_mods))), (fminnum_ieee:{ *:[f16] } (VOP3Mods:{ *:[f16] } f16:{ *:[f16] }:$src1, i32:{ *:[i32] }:$src1_mods), (VOP3Mods:{ *:[f16] } f16:{ *:[f16] }:$src0, i32:{ *:[i32] }:$src0_mods)))<<P:Predicate_fmaxnum_like_nnan>>  =>  (V_MED3_F16_e64:{ *:[f16] } ?:{ *:[i32] }:$src0_mods, ?:{ *:[f16] }:$src0, ?:{ *:[i32] }:$src1_mods, ?:{ *:[f16] }:$src1, ?:{ *:[i32] }:$src2_mods, ?:{ *:[f16] }:$src2, 0:{ *:[i1] })
        GIR_BuildMI, /*InsnID*/0, /*Opcode*/GIMT_Encode2(AMDGPU::V_MED3_F16_e64),
        GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/0, // DstI[vdst]
        GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(2), /*SubOperand*/1, // src0_mods
        GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(2), /*SubOperand*/0, // src0
        GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(1), /*SubOperand*/1, // src1_mods
        GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(1), /*SubOperand*/0, // src1
        GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/1, // src2_mods
        GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/0, // src2
        GIR_AddImm8, /*InsnID*/0, /*Imm*/0,
        GIR_AddImm8, /*InsnID*/0, /*Imm*/0,
        GIR_AddImm8, /*InsnID*/0, /*Imm*/0,
        GIR_ConstrainSelectedInstOperands, /*InsnID*/0,
        GIR_EraseFromParent, /*InsnID*/0,
        // GIR_Coverage, 10709,
        GIR_Done,
      // Label 4511: @293964
      GIM_Try, /*On fail goto*//*Label 4512*/ GIMT_Encode4(294110), // Rule ID 10751 //
        GIM_CheckFeatures, GIMT_Encode2(GIFBS_isGFX9Plus),
        GIM_CheckRegBankForClass, /*MI*/0, /*Op*/0, /*RC*/GIMT_Encode2(AMDGPU::VGPR_32RegClassID),
        GIM_RecordInsn, /*DefineMI*/1, /*MI*/0, /*OpIdx*/1, // MIs[1]
        GIM_CheckOpcode, /*MI*/1, GIMT_Encode2(TargetOpcode::G_FMINNUM),
        GIM_CheckType, /*MI*/1, /*Op*/1, /*Type*/GILLT_s16,
        GIM_CheckType, /*MI*/1, /*Op*/2, /*Type*/GILLT_s16,
        GIM_RecordInsn, /*DefineMI*/2, /*MI*/1, /*OpIdx*/2, // MIs[2]
        GIM_CheckOpcode, /*MI*/2, GIMT_Encode2(TargetOpcode::G_FMAXNUM_IEEE),
        GIM_CheckType, /*MI*/2, /*Op*/1, /*Type*/GILLT_s16,
        GIM_CheckType, /*MI*/2, /*Op*/2, /*Type*/GILLT_s16,
        GIM_RecordInsn, /*DefineMI*/3, /*MI*/0, /*OpIdx*/2, // MIs[3]
        GIM_CheckOpcode, /*MI*/3, GIMT_Encode2(TargetOpcode::G_FMINNUM),
        // MIs[3] VOP3Mods:src0:src0_mods
        GIM_CheckIsSameOperand, /*MI*/3, /*OpIdx*/1, /*OtherMI*/2, /*OtherOpIdx*/1,
        // MIs[3] VOP3Mods:src1:src1_mods
        GIM_CheckIsSameOperand, /*MI*/3, /*OpIdx*/2, /*OtherMI*/2, /*OtherOpIdx*/2,
        GIM_CheckCxxInsnPredicate, /*MI*/0, /*FnId*/GIMT_Encode2(GICXXPred_MI_Predicate_fmaxnum_like_nnan),
        GIM_CheckIsSafeToFold, /*InsnID*/1,
        GIM_CheckIsSafeToFold, /*InsnID*/2,
        GIM_CheckIsSafeToFold, /*InsnID*/3,
        GIM_CheckComplexPattern, /*MI*/1, /*Op*/1, /*Renderer*/GIMT_Encode2(0), GIMT_Encode2(GICP_gi_vop3mods),
        GIM_CheckComplexPattern, /*MI*/2, /*Op*/1, /*Renderer*/GIMT_Encode2(1), GIMT_Encode2(GICP_gi_vop3mods),
        GIM_CheckComplexPattern, /*MI*/2, /*Op*/2, /*Renderer*/GIMT_Encode2(2), GIMT_Encode2(GICP_gi_vop3mods),
        // (fmaxnum:{ *:[f16] } (fminnum:{ *:[f16] } (VOP3Mods:{ *:[f16] } f16:{ *:[f16] }:$src2, i32:{ *:[i32] }:$src2_mods), (fmaxnum_ieee:{ *:[f16] } (VOP3Mods:{ *:[f16] } f16:{ *:[f16] }:$src0, i32:{ *:[i32] }:$src0_mods), (VOP3Mods:{ *:[f16] } f16:{ *:[f16] }:$src1, i32:{ *:[i32] }:$src1_mods))), (fminnum:{ *:[f16] } (VOP3Mods:{ *:[f16] } f16:{ *:[f16] }:$src0, i32:{ *:[i32] }:$src0_mods), (VOP3Mods:{ *:[f16] } f16:{ *:[f16] }:$src1, i32:{ *:[i32] }:$src1_mods)))<<P:Predicate_fmaxnum_like_nnan>>  =>  (V_MED3_F16_e64:{ *:[f16] } ?:{ *:[i32] }:$src0_mods, ?:{ *:[f16] }:$src0, ?:{ *:[i32] }:$src1_mods, ?:{ *:[f16] }:$src1, ?:{ *:[i32] }:$src2_mods, ?:{ *:[f16] }:$src2, 0:{ *:[i1] })
        GIR_BuildMI, /*InsnID*/0, /*Opcode*/GIMT_Encode2(AMDGPU::V_MED3_F16_e64),
        GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/0, // DstI[vdst]
        GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(1), /*SubOperand*/1, // src0_mods
        GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(1), /*SubOperand*/0, // src0
        GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(2), /*SubOperand*/1, // src1_mods
        GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(2), /*SubOperand*/0, // src1
        GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/1, // src2_mods
        GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/0, // src2
        GIR_AddImm8, /*InsnID*/0, /*Imm*/0,
        GIR_AddImm8, /*InsnID*/0, /*Imm*/0,
        GIR_AddImm8, /*InsnID*/0, /*Imm*/0,
        GIR_ConstrainSelectedInstOperands, /*InsnID*/0,
        GIR_EraseFromParent, /*InsnID*/0,
        // GIR_Coverage, 10751,
        GIR_Done,
      // Label 4512: @294110
      GIM_Try, /*On fail goto*//*Label 4513*/ GIMT_Encode4(294256), // Rule ID 10752 //
        GIM_CheckFeatures, GIMT_Encode2(GIFBS_isGFX9Plus),
        GIM_CheckRegBankForClass, /*MI*/0, /*Op*/0, /*RC*/GIMT_Encode2(AMDGPU::VGPR_32RegClassID),
        GIM_RecordInsn, /*DefineMI*/1, /*MI*/0, /*OpIdx*/1, // MIs[1]
        GIM_CheckOpcode, /*MI*/1, GIMT_Encode2(TargetOpcode::G_FMINNUM),
        GIM_CheckType, /*MI*/1, /*Op*/1, /*Type*/GILLT_s16,
        GIM_CheckType, /*MI*/1, /*Op*/2, /*Type*/GILLT_s16,
        GIM_RecordInsn, /*DefineMI*/2, /*MI*/1, /*OpIdx*/2, // MIs[2]
        GIM_CheckOpcode, /*MI*/2, GIMT_Encode2(TargetOpcode::G_FMAXNUM_IEEE),
        GIM_CheckType, /*MI*/2, /*Op*/1, /*Type*/GILLT_s16,
        GIM_CheckType, /*MI*/2, /*Op*/2, /*Type*/GILLT_s16,
        GIM_RecordInsn, /*DefineMI*/3, /*MI*/0, /*OpIdx*/2, // MIs[3]
        GIM_CheckOpcode, /*MI*/3, GIMT_Encode2(TargetOpcode::G_FMINNUM),
        // MIs[3] VOP3Mods:src1:src1_mods
        GIM_CheckIsSameOperand, /*MI*/3, /*OpIdx*/1, /*OtherMI*/2, /*OtherOpIdx*/2,
        // MIs[3] VOP3Mods:src0:src0_mods
        GIM_CheckIsSameOperand, /*MI*/3, /*OpIdx*/2, /*OtherMI*/2, /*OtherOpIdx*/1,
        GIM_CheckCxxInsnPredicate, /*MI*/0, /*FnId*/GIMT_Encode2(GICXXPred_MI_Predicate_fmaxnum_like_nnan),
        GIM_CheckIsSafeToFold, /*InsnID*/1,
        GIM_CheckIsSafeToFold, /*InsnID*/2,
        GIM_CheckIsSafeToFold, /*InsnID*/3,
        GIM_CheckComplexPattern, /*MI*/1, /*Op*/1, /*Renderer*/GIMT_Encode2(0), GIMT_Encode2(GICP_gi_vop3mods),
        GIM_CheckComplexPattern, /*MI*/2, /*Op*/1, /*Renderer*/GIMT_Encode2(1), GIMT_Encode2(GICP_gi_vop3mods),
        GIM_CheckComplexPattern, /*MI*/2, /*Op*/2, /*Renderer*/GIMT_Encode2(2), GIMT_Encode2(GICP_gi_vop3mods),
        // (fmaxnum:{ *:[f16] } (fminnum:{ *:[f16] } (VOP3Mods:{ *:[f16] } f16:{ *:[f16] }:$src2, i32:{ *:[i32] }:$src2_mods), (fmaxnum_ieee:{ *:[f16] } (VOP3Mods:{ *:[f16] } f16:{ *:[f16] }:$src0, i32:{ *:[i32] }:$src0_mods), (VOP3Mods:{ *:[f16] } f16:{ *:[f16] }:$src1, i32:{ *:[i32] }:$src1_mods))), (fminnum:{ *:[f16] } (VOP3Mods:{ *:[f16] } f16:{ *:[f16] }:$src1, i32:{ *:[i32] }:$src1_mods), (VOP3Mods:{ *:[f16] } f16:{ *:[f16] }:$src0, i32:{ *:[i32] }:$src0_mods)))<<P:Predicate_fmaxnum_like_nnan>>  =>  (V_MED3_F16_e64:{ *:[f16] } ?:{ *:[i32] }:$src0_mods, ?:{ *:[f16] }:$src0, ?:{ *:[i32] }:$src1_mods, ?:{ *:[f16] }:$src1, ?:{ *:[i32] }:$src2_mods, ?:{ *:[f16] }:$src2, 0:{ *:[i1] })
        GIR_BuildMI, /*InsnID*/0, /*Opcode*/GIMT_Encode2(AMDGPU::V_MED3_F16_e64),
        GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/0, // DstI[vdst]
        GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(1), /*SubOperand*/1, // src0_mods
        GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(1), /*SubOperand*/0, // src0
        GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(2), /*SubOperand*/1, // src1_mods
        GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(2), /*SubOperand*/0, // src1
        GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/1, // src2_mods
        GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/0, // src2
        GIR_AddImm8, /*InsnID*/0, /*Imm*/0,
        GIR_AddImm8, /*InsnID*/0, /*Imm*/0,
        GIR_AddImm8, /*InsnID*/0, /*Imm*/0,
        GIR_ConstrainSelectedInstOperands, /*InsnID*/0,
        GIR_EraseFromParent, /*InsnID*/0,
        // GIR_Coverage, 10752,
        GIR_Done,
      // Label 4513: @294256
      GIM_Try, /*On fail goto*//*Label 4514*/ GIMT_Encode4(294402), // Rule ID 10753 //
        GIM_CheckFeatures, GIMT_Encode2(GIFBS_isGFX9Plus),
        GIM_CheckRegBankForClass, /*MI*/0, /*Op*/0, /*RC*/GIMT_Encode2(AMDGPU::VGPR_32RegClassID),
        GIM_RecordInsn, /*DefineMI*/1, /*MI*/0, /*OpIdx*/1, // MIs[1]
        GIM_CheckOpcode, /*MI*/1, GIMT_Encode2(TargetOpcode::G_FMINNUM),
        GIM_CheckType, /*MI*/1, /*Op*/1, /*Type*/GILLT_s16,
        GIM_CheckType, /*MI*/1, /*Op*/2, /*Type*/GILLT_s16,
        GIM_RecordInsn, /*DefineMI*/2, /*MI*/1, /*OpIdx*/2, // MIs[2]
        GIM_CheckOpcode, /*MI*/2, GIMT_Encode2(TargetOpcode::G_FMAXNUM_IEEE),
        GIM_CheckType, /*MI*/2, /*Op*/1, /*Type*/GILLT_s16,
        GIM_CheckType, /*MI*/2, /*Op*/2, /*Type*/GILLT_s16,
        GIM_RecordInsn, /*DefineMI*/3, /*MI*/0, /*OpIdx*/2, // MIs[3]
        GIM_CheckOpcode, /*MI*/3, GIMT_Encode2(TargetOpcode::G_FMINNUM),
        // MIs[3] VOP3Mods:src0:src0_mods
        GIM_CheckIsSameOperand, /*MI*/3, /*OpIdx*/1, /*OtherMI*/2, /*OtherOpIdx*/2,
        // MIs[3] VOP3Mods:src1:src1_mods
        GIM_CheckIsSameOperand, /*MI*/3, /*OpIdx*/2, /*OtherMI*/2, /*OtherOpIdx*/1,
        GIM_CheckCxxInsnPredicate, /*MI*/0, /*FnId*/GIMT_Encode2(GICXXPred_MI_Predicate_fmaxnum_like_nnan),
        GIM_CheckIsSafeToFold, /*InsnID*/1,
        GIM_CheckIsSafeToFold, /*InsnID*/2,
        GIM_CheckIsSafeToFold, /*InsnID*/3,
        GIM_CheckComplexPattern, /*MI*/1, /*Op*/1, /*Renderer*/GIMT_Encode2(0), GIMT_Encode2(GICP_gi_vop3mods),
        GIM_CheckComplexPattern, /*MI*/2, /*Op*/1, /*Renderer*/GIMT_Encode2(1), GIMT_Encode2(GICP_gi_vop3mods),
        GIM_CheckComplexPattern, /*MI*/2, /*Op*/2, /*Renderer*/GIMT_Encode2(2), GIMT_Encode2(GICP_gi_vop3mods),
        // (fmaxnum:{ *:[f16] } (fminnum:{ *:[f16] } (VOP3Mods:{ *:[f16] } f16:{ *:[f16] }:$src2, i32:{ *:[i32] }:$src2_mods), (fmaxnum_ieee:{ *:[f16] } (VOP3Mods:{ *:[f16] } f16:{ *:[f16] }:$src1, i32:{ *:[i32] }:$src1_mods), (VOP3Mods:{ *:[f16] } f16:{ *:[f16] }:$src0, i32:{ *:[i32] }:$src0_mods))), (fminnum:{ *:[f16] } (VOP3Mods:{ *:[f16] } f16:{ *:[f16] }:$src0, i32:{ *:[i32] }:$src0_mods), (VOP3Mods:{ *:[f16] } f16:{ *:[f16] }:$src1, i32:{ *:[i32] }:$src1_mods)))<<P:Predicate_fmaxnum_like_nnan>>  =>  (V_MED3_F16_e64:{ *:[f16] } ?:{ *:[i32] }:$src0_mods, ?:{ *:[f16] }:$src0, ?:{ *:[i32] }:$src1_mods, ?:{ *:[f16] }:$src1, ?:{ *:[i32] }:$src2_mods, ?:{ *:[f16] }:$src2, 0:{ *:[i1] })
        GIR_BuildMI, /*InsnID*/0, /*Opcode*/GIMT_Encode2(AMDGPU::V_MED3_F16_e64),
        GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/0, // DstI[vdst]
        GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(2), /*SubOperand*/1, // src0_mods
        GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(2), /*SubOperand*/0, // src0
        GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(1), /*SubOperand*/1, // src1_mods
        GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(1), /*SubOperand*/0, // src1
        GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/1, // src2_mods
        GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/0, // src2
        GIR_AddImm8, /*InsnID*/0, /*Imm*/0,
        GIR_AddImm8, /*InsnID*/0, /*Imm*/0,
        GIR_AddImm8, /*InsnID*/0, /*Imm*/0,
        GIR_ConstrainSelectedInstOperands, /*InsnID*/0,
        GIR_EraseFromParent, /*InsnID*/0,
        // GIR_Coverage, 10753,
        GIR_Done,
      // Label 4514: @294402
      GIM_Try, /*On fail goto*//*Label 4515*/ GIMT_Encode4(294548), // Rule ID 10754 //
        GIM_CheckFeatures, GIMT_Encode2(GIFBS_isGFX9Plus),
        GIM_CheckRegBankForClass, /*MI*/0, /*Op*/0, /*RC*/GIMT_Encode2(AMDGPU::VGPR_32RegClassID),
        GIM_RecordInsn, /*DefineMI*/1, /*MI*/0, /*OpIdx*/1, // MIs[1]
        GIM_CheckOpcode, /*MI*/1, GIMT_Encode2(TargetOpcode::G_FMINNUM),
        GIM_CheckType, /*MI*/1, /*Op*/1, /*Type*/GILLT_s16,
        GIM_CheckType, /*MI*/1, /*Op*/2, /*Type*/GILLT_s16,
        GIM_RecordInsn, /*DefineMI*/2, /*MI*/1, /*OpIdx*/2, // MIs[2]
        GIM_CheckOpcode, /*MI*/2, GIMT_Encode2(TargetOpcode::G_FMAXNUM_IEEE),
        GIM_CheckType, /*MI*/2, /*Op*/1, /*Type*/GILLT_s16,
        GIM_CheckType, /*MI*/2, /*Op*/2, /*Type*/GILLT_s16,
        GIM_RecordInsn, /*DefineMI*/3, /*MI*/0, /*OpIdx*/2, // MIs[3]
        GIM_CheckOpcode, /*MI*/3, GIMT_Encode2(TargetOpcode::G_FMINNUM),
        // MIs[3] VOP3Mods:src1:src1_mods
        GIM_CheckIsSameOperand, /*MI*/3, /*OpIdx*/1, /*OtherMI*/2, /*OtherOpIdx*/1,
        // MIs[3] VOP3Mods:src0:src0_mods
        GIM_CheckIsSameOperand, /*MI*/3, /*OpIdx*/2, /*OtherMI*/2, /*OtherOpIdx*/2,
        GIM_CheckCxxInsnPredicate, /*MI*/0, /*FnId*/GIMT_Encode2(GICXXPred_MI_Predicate_fmaxnum_like_nnan),
        GIM_CheckIsSafeToFold, /*InsnID*/1,
        GIM_CheckIsSafeToFold, /*InsnID*/2,
        GIM_CheckIsSafeToFold, /*InsnID*/3,
        GIM_CheckComplexPattern, /*MI*/1, /*Op*/1, /*Renderer*/GIMT_Encode2(0), GIMT_Encode2(GICP_gi_vop3mods),
        GIM_CheckComplexPattern, /*MI*/2, /*Op*/1, /*Renderer*/GIMT_Encode2(1), GIMT_Encode2(GICP_gi_vop3mods),
        GIM_CheckComplexPattern, /*MI*/2, /*Op*/2, /*Renderer*/GIMT_Encode2(2), GIMT_Encode2(GICP_gi_vop3mods),
        // (fmaxnum:{ *:[f16] } (fminnum:{ *:[f16] } (VOP3Mods:{ *:[f16] } f16:{ *:[f16] }:$src2, i32:{ *:[i32] }:$src2_mods), (fmaxnum_ieee:{ *:[f16] } (VOP3Mods:{ *:[f16] } f16:{ *:[f16] }:$src1, i32:{ *:[i32] }:$src1_mods), (VOP3Mods:{ *:[f16] } f16:{ *:[f16] }:$src0, i32:{ *:[i32] }:$src0_mods))), (fminnum:{ *:[f16] } (VOP3Mods:{ *:[f16] } f16:{ *:[f16] }:$src1, i32:{ *:[i32] }:$src1_mods), (VOP3Mods:{ *:[f16] } f16:{ *:[f16] }:$src0, i32:{ *:[i32] }:$src0_mods)))<<P:Predicate_fmaxnum_like_nnan>>  =>  (V_MED3_F16_e64:{ *:[f16] } ?:{ *:[i32] }:$src0_mods, ?:{ *:[f16] }:$src0, ?:{ *:[i32] }:$src1_mods, ?:{ *:[f16] }:$src1, ?:{ *:[i32] }:$src2_mods, ?:{ *:[f16] }:$src2, 0:{ *:[i1] })
        GIR_BuildMI, /*InsnID*/0, /*Opcode*/GIMT_Encode2(AMDGPU::V_MED3_F16_e64),
        GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/0, // DstI[vdst]
        GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(2), /*SubOperand*/1, // src0_mods
        GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(2), /*SubOperand*/0, // src0
        GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(1), /*SubOperand*/1, // src1_mods
        GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(1), /*SubOperand*/0, // src1
        GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/1, // src2_mods
        GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/0, // src2
        GIR_AddImm8, /*InsnID*/0, /*Imm*/0,
        GIR_AddImm8, /*InsnID*/0, /*Imm*/0,
        GIR_AddImm8, /*InsnID*/0, /*Imm*/0,
        GIR_ConstrainSelectedInstOperands, /*InsnID*/0,
        GIR_EraseFromParent, /*InsnID*/0,
        // GIR_Coverage, 10754,
        GIR_Done,
      // Label 4515: @294548
      GIM_Try, /*On fail goto*//*Label 4516*/ GIMT_Encode4(294694), // Rule ID 10691 //
        GIM_CheckFeatures, GIMT_Encode2(GIFBS_isGFX9Plus),
        GIM_CheckRegBankForClass, /*MI*/0, /*Op*/0, /*RC*/GIMT_Encode2(AMDGPU::VGPR_32RegClassID),
        GIM_RecordInsn, /*DefineMI*/1, /*MI*/0, /*OpIdx*/1, // MIs[1]
        GIM_CheckOpcode, /*MI*/1, GIMT_Encode2(TargetOpcode::G_FMINNUM),
        GIM_CheckType, /*MI*/1, /*Op*/1, /*Type*/GILLT_s16,
        GIM_CheckType, /*MI*/1, /*Op*/2, /*Type*/GILLT_s16,
        GIM_RecordInsn, /*DefineMI*/2, /*MI*/1, /*OpIdx*/2, // MIs[2]
        GIM_CheckOpcode, /*MI*/2, GIMT_Encode2(TargetOpcode::G_FMAXNUM_IEEE),
        GIM_CheckType, /*MI*/2, /*Op*/1, /*Type*/GILLT_s16,
        GIM_CheckType, /*MI*/2, /*Op*/2, /*Type*/GILLT_s16,
        GIM_RecordInsn, /*DefineMI*/3, /*MI*/0, /*OpIdx*/2, // MIs[3]
        GIM_CheckOpcode, /*MI*/3, GIMT_Encode2(TargetOpcode::G_FMINNUM_IEEE),
        // MIs[3] VOP3Mods:src0:src0_mods
        GIM_CheckIsSameOperand, /*MI*/3, /*OpIdx*/1, /*OtherMI*/2, /*OtherOpIdx*/1,
        // MIs[3] VOP3Mods:src1:src1_mods
        GIM_CheckIsSameOperand, /*MI*/3, /*OpIdx*/2, /*OtherMI*/2, /*OtherOpIdx*/2,
        GIM_CheckCxxInsnPredicate, /*MI*/0, /*FnId*/GIMT_Encode2(GICXXPred_MI_Predicate_fmaxnum_like_nnan),
        GIM_CheckIsSafeToFold, /*InsnID*/1,
        GIM_CheckIsSafeToFold, /*InsnID*/2,
        GIM_CheckIsSafeToFold, /*InsnID*/3,
        GIM_CheckComplexPattern, /*MI*/1, /*Op*/1, /*Renderer*/GIMT_Encode2(0), GIMT_Encode2(GICP_gi_vop3mods),
        GIM_CheckComplexPattern, /*MI*/2, /*Op*/1, /*Renderer*/GIMT_Encode2(1), GIMT_Encode2(GICP_gi_vop3mods),
        GIM_CheckComplexPattern, /*MI*/2, /*Op*/2, /*Renderer*/GIMT_Encode2(2), GIMT_Encode2(GICP_gi_vop3mods),
        // (fmaxnum:{ *:[f16] } (fminnum:{ *:[f16] } (VOP3Mods:{ *:[f16] } f16:{ *:[f16] }:$src2, i32:{ *:[i32] }:$src2_mods), (fmaxnum_ieee:{ *:[f16] } (VOP3Mods:{ *:[f16] } f16:{ *:[f16] }:$src0, i32:{ *:[i32] }:$src0_mods), (VOP3Mods:{ *:[f16] } f16:{ *:[f16] }:$src1, i32:{ *:[i32] }:$src1_mods))), (fminnum_ieee:{ *:[f16] } (VOP3Mods:{ *:[f16] } f16:{ *:[f16] }:$src0, i32:{ *:[i32] }:$src0_mods), (VOP3Mods:{ *:[f16] } f16:{ *:[f16] }:$src1, i32:{ *:[i32] }:$src1_mods)))<<P:Predicate_fmaxnum_like_nnan>>  =>  (V_MED3_F16_e64:{ *:[f16] } ?:{ *:[i32] }:$src0_mods, ?:{ *:[f16] }:$src0, ?:{ *:[i32] }:$src1_mods, ?:{ *:[f16] }:$src1, ?:{ *:[i32] }:$src2_mods, ?:{ *:[f16] }:$src2, 0:{ *:[i1] })
        GIR_BuildMI, /*InsnID*/0, /*Opcode*/GIMT_Encode2(AMDGPU::V_MED3_F16_e64),
        GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/0, // DstI[vdst]
        GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(1), /*SubOperand*/1, // src0_mods
        GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(1), /*SubOperand*/0, // src0
        GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(2), /*SubOperand*/1, // src1_mods
        GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(2), /*SubOperand*/0, // src1
        GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/1, // src2_mods
        GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/0, // src2
        GIR_AddImm8, /*InsnID*/0, /*Imm*/0,
        GIR_AddImm8, /*InsnID*/0, /*Imm*/0,
        GIR_AddImm8, /*InsnID*/0, /*Imm*/0,
        GIR_ConstrainSelectedInstOperands, /*InsnID*/0,
        GIR_EraseFromParent, /*InsnID*/0,
        // GIR_Coverage, 10691,
        GIR_Done,
      // Label 4516: @294694
      GIM_Try, /*On fail goto*//*Label 4517*/ GIMT_Encode4(294840), // Rule ID 10692 //
        GIM_CheckFeatures, GIMT_Encode2(GIFBS_isGFX9Plus),
        GIM_CheckRegBankForClass, /*MI*/0, /*Op*/0, /*RC*/GIMT_Encode2(AMDGPU::VGPR_32RegClassID),
        GIM_RecordInsn, /*DefineMI*/1, /*MI*/0, /*OpIdx*/1, // MIs[1]
        GIM_CheckOpcode, /*MI*/1, GIMT_Encode2(TargetOpcode::G_FMINNUM),
        GIM_CheckType, /*MI*/1, /*Op*/1, /*Type*/GILLT_s16,
        GIM_CheckType, /*MI*/1, /*Op*/2, /*Type*/GILLT_s16,
        GIM_RecordInsn, /*DefineMI*/2, /*MI*/1, /*OpIdx*/2, // MIs[2]
        GIM_CheckOpcode, /*MI*/2, GIMT_Encode2(TargetOpcode::G_FMAXNUM_IEEE),
        GIM_CheckType, /*MI*/2, /*Op*/1, /*Type*/GILLT_s16,
        GIM_CheckType, /*MI*/2, /*Op*/2, /*Type*/GILLT_s16,
        GIM_RecordInsn, /*DefineMI*/3, /*MI*/0, /*OpIdx*/2, // MIs[3]
        GIM_CheckOpcode, /*MI*/3, GIMT_Encode2(TargetOpcode::G_FMINNUM_IEEE),
        // MIs[3] VOP3Mods:src1:src1_mods
        GIM_CheckIsSameOperand, /*MI*/3, /*OpIdx*/1, /*OtherMI*/2, /*OtherOpIdx*/2,
        // MIs[3] VOP3Mods:src0:src0_mods
        GIM_CheckIsSameOperand, /*MI*/3, /*OpIdx*/2, /*OtherMI*/2, /*OtherOpIdx*/1,
        GIM_CheckCxxInsnPredicate, /*MI*/0, /*FnId*/GIMT_Encode2(GICXXPred_MI_Predicate_fmaxnum_like_nnan),
        GIM_CheckIsSafeToFold, /*InsnID*/1,
        GIM_CheckIsSafeToFold, /*InsnID*/2,
        GIM_CheckIsSafeToFold, /*InsnID*/3,
        GIM_CheckComplexPattern, /*MI*/1, /*Op*/1, /*Renderer*/GIMT_Encode2(0), GIMT_Encode2(GICP_gi_vop3mods),
        GIM_CheckComplexPattern, /*MI*/2, /*Op*/1, /*Renderer*/GIMT_Encode2(1), GIMT_Encode2(GICP_gi_vop3mods),
        GIM_CheckComplexPattern, /*MI*/2, /*Op*/2, /*Renderer*/GIMT_Encode2(2), GIMT_Encode2(GICP_gi_vop3mods),
        // (fmaxnum:{ *:[f16] } (fminnum:{ *:[f16] } (VOP3Mods:{ *:[f16] } f16:{ *:[f16] }:$src2, i32:{ *:[i32] }:$src2_mods), (fmaxnum_ieee:{ *:[f16] } (VOP3Mods:{ *:[f16] } f16:{ *:[f16] }:$src0, i32:{ *:[i32] }:$src0_mods), (VOP3Mods:{ *:[f16] } f16:{ *:[f16] }:$src1, i32:{ *:[i32] }:$src1_mods))), (fminnum_ieee:{ *:[f16] } (VOP3Mods:{ *:[f16] } f16:{ *:[f16] }:$src1, i32:{ *:[i32] }:$src1_mods), (VOP3Mods:{ *:[f16] } f16:{ *:[f16] }:$src0, i32:{ *:[i32] }:$src0_mods)))<<P:Predicate_fmaxnum_like_nnan>>  =>  (V_MED3_F16_e64:{ *:[f16] } ?:{ *:[i32] }:$src0_mods, ?:{ *:[f16] }:$src0, ?:{ *:[i32] }:$src1_mods, ?:{ *:[f16] }:$src1, ?:{ *:[i32] }:$src2_mods, ?:{ *:[f16] }:$src2, 0:{ *:[i1] })
        GIR_BuildMI, /*InsnID*/0, /*Opcode*/GIMT_Encode2(AMDGPU::V_MED3_F16_e64),
        GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/0, // DstI[vdst]
        GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(1), /*SubOperand*/1, // src0_mods
        GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(1), /*SubOperand*/0, // src0
        GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(2), /*SubOperand*/1, // src1_mods
        GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(2), /*SubOperand*/0, // src1
        GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/1, // src2_mods
        GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/0, // src2
        GIR_AddImm8, /*InsnID*/0, /*Imm*/0,
        GIR_AddImm8, /*InsnID*/0, /*Imm*/0,
        GIR_AddImm8, /*InsnID*/0, /*Imm*/0,
        GIR_ConstrainSelectedInstOperands, /*InsnID*/0,
        GIR_EraseFromParent, /*InsnID*/0,
        // GIR_Coverage, 10692,
        GIR_Done,
      // Label 4517: @294840
      GIM_Try, /*On fail goto*//*Label 4518*/ GIMT_Encode4(294986), // Rule ID 10693 //
        GIM_CheckFeatures, GIMT_Encode2(GIFBS_isGFX9Plus),
        GIM_CheckRegBankForClass, /*MI*/0, /*Op*/0, /*RC*/GIMT_Encode2(AMDGPU::VGPR_32RegClassID),
        GIM_RecordInsn, /*DefineMI*/1, /*MI*/0, /*OpIdx*/1, // MIs[1]
        GIM_CheckOpcode, /*MI*/1, GIMT_Encode2(TargetOpcode::G_FMINNUM),
        GIM_CheckType, /*MI*/1, /*Op*/1, /*Type*/GILLT_s16,
        GIM_CheckType, /*MI*/1, /*Op*/2, /*Type*/GILLT_s16,
        GIM_RecordInsn, /*DefineMI*/2, /*MI*/1, /*OpIdx*/2, // MIs[2]
        GIM_CheckOpcode, /*MI*/2, GIMT_Encode2(TargetOpcode::G_FMAXNUM_IEEE),
        GIM_CheckType, /*MI*/2, /*Op*/1, /*Type*/GILLT_s16,
        GIM_CheckType, /*MI*/2, /*Op*/2, /*Type*/GILLT_s16,
        GIM_RecordInsn, /*DefineMI*/3, /*MI*/0, /*OpIdx*/2, // MIs[3]
        GIM_CheckOpcode, /*MI*/3, GIMT_Encode2(TargetOpcode::G_FMINNUM_IEEE),
        // MIs[3] VOP3Mods:src0:src0_mods
        GIM_CheckIsSameOperand, /*MI*/3, /*OpIdx*/1, /*OtherMI*/2, /*OtherOpIdx*/2,
        // MIs[3] VOP3Mods:src1:src1_mods
        GIM_CheckIsSameOperand, /*MI*/3, /*OpIdx*/2, /*OtherMI*/2, /*OtherOpIdx*/1,
        GIM_CheckCxxInsnPredicate, /*MI*/0, /*FnId*/GIMT_Encode2(GICXXPred_MI_Predicate_fmaxnum_like_nnan),
        GIM_CheckIsSafeToFold, /*InsnID*/1,
        GIM_CheckIsSafeToFold, /*InsnID*/2,
        GIM_CheckIsSafeToFold, /*InsnID*/3,
        GIM_CheckComplexPattern, /*MI*/1, /*Op*/1, /*Renderer*/GIMT_Encode2(0), GIMT_Encode2(GICP_gi_vop3mods),
        GIM_CheckComplexPattern, /*MI*/2, /*Op*/1, /*Renderer*/GIMT_Encode2(1), GIMT_Encode2(GICP_gi_vop3mods),
        GIM_CheckComplexPattern, /*MI*/2, /*Op*/2, /*Renderer*/GIMT_Encode2(2), GIMT_Encode2(GICP_gi_vop3mods),
        // (fmaxnum:{ *:[f16] } (fminnum:{ *:[f16] } (VOP3Mods:{ *:[f16] } f16:{ *:[f16] }:$src2, i32:{ *:[i32] }:$src2_mods), (fmaxnum_ieee:{ *:[f16] } (VOP3Mods:{ *:[f16] } f16:{ *:[f16] }:$src1, i32:{ *:[i32] }:$src1_mods), (VOP3Mods:{ *:[f16] } f16:{ *:[f16] }:$src0, i32:{ *:[i32] }:$src0_mods))), (fminnum_ieee:{ *:[f16] } (VOP3Mods:{ *:[f16] } f16:{ *:[f16] }:$src0, i32:{ *:[i32] }:$src0_mods), (VOP3Mods:{ *:[f16] } f16:{ *:[f16] }:$src1, i32:{ *:[i32] }:$src1_mods)))<<P:Predicate_fmaxnum_like_nnan>>  =>  (V_MED3_F16_e64:{ *:[f16] } ?:{ *:[i32] }:$src0_mods, ?:{ *:[f16] }:$src0, ?:{ *:[i32] }:$src1_mods, ?:{ *:[f16] }:$src1, ?:{ *:[i32] }:$src2_mods, ?:{ *:[f16] }:$src2, 0:{ *:[i1] })
        GIR_BuildMI, /*InsnID*/0, /*Opcode*/GIMT_Encode2(AMDGPU::V_MED3_F16_e64),
        GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/0, // DstI[vdst]
        GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(2), /*SubOperand*/1, // src0_mods
        GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(2), /*SubOperand*/0, // src0
        GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(1), /*SubOperand*/1, // src1_mods
        GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(1), /*SubOperand*/0, // src1
        GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/1, // src2_mods
        GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/0, // src2
        GIR_AddImm8, /*InsnID*/0, /*Imm*/0,
        GIR_AddImm8, /*InsnID*/0, /*Imm*/0,
        GIR_AddImm8, /*InsnID*/0, /*Imm*/0,
        GIR_ConstrainSelectedInstOperands, /*InsnID*/0,
        GIR_EraseFromParent, /*InsnID*/0,
        // GIR_Coverage, 10693,
        GIR_Done,
      // Label 4518: @294986
      GIM_Try, /*On fail goto*//*Label 4519*/ GIMT_Encode4(295132), // Rule ID 10694 //
        GIM_CheckFeatures, GIMT_Encode2(GIFBS_isGFX9Plus),
        GIM_CheckRegBankForClass, /*MI*/0, /*Op*/0, /*RC*/GIMT_Encode2(AMDGPU::VGPR_32RegClassID),
        GIM_RecordInsn, /*DefineMI*/1, /*MI*/0, /*OpIdx*/1, // MIs[1]
        GIM_CheckOpcode, /*MI*/1, GIMT_Encode2(TargetOpcode::G_FMINNUM),
        GIM_CheckType, /*MI*/1, /*Op*/1, /*Type*/GILLT_s16,
        GIM_CheckType, /*MI*/1, /*Op*/2, /*Type*/GILLT_s16,
        GIM_RecordInsn, /*DefineMI*/2, /*MI*/1, /*OpIdx*/2, // MIs[2]
        GIM_CheckOpcode, /*MI*/2, GIMT_Encode2(TargetOpcode::G_FMAXNUM_IEEE),
        GIM_CheckType, /*MI*/2, /*Op*/1, /*Type*/GILLT_s16,
        GIM_CheckType, /*MI*/2, /*Op*/2, /*Type*/GILLT_s16,
        GIM_RecordInsn, /*DefineMI*/3, /*MI*/0, /*OpIdx*/2, // MIs[3]
        GIM_CheckOpcode, /*MI*/3, GIMT_Encode2(TargetOpcode::G_FMINNUM_IEEE),
        // MIs[3] VOP3Mods:src1:src1_mods
        GIM_CheckIsSameOperand, /*MI*/3, /*OpIdx*/1, /*OtherMI*/2, /*OtherOpIdx*/1,
        // MIs[3] VOP3Mods:src0:src0_mods
        GIM_CheckIsSameOperand, /*MI*/3, /*OpIdx*/2, /*OtherMI*/2, /*OtherOpIdx*/2,
        GIM_CheckCxxInsnPredicate, /*MI*/0, /*FnId*/GIMT_Encode2(GICXXPred_MI_Predicate_fmaxnum_like_nnan),
        GIM_CheckIsSafeToFold, /*InsnID*/1,
        GIM_CheckIsSafeToFold, /*InsnID*/2,
        GIM_CheckIsSafeToFold, /*InsnID*/3,
        GIM_CheckComplexPattern, /*MI*/1, /*Op*/1, /*Renderer*/GIMT_Encode2(0), GIMT_Encode2(GICP_gi_vop3mods),
        GIM_CheckComplexPattern, /*MI*/2, /*Op*/1, /*Renderer*/GIMT_Encode2(1), GIMT_Encode2(GICP_gi_vop3mods),
        GIM_CheckComplexPattern, /*MI*/2, /*Op*/2, /*Renderer*/GIMT_Encode2(2), GIMT_Encode2(GICP_gi_vop3mods),
        // (fmaxnum:{ *:[f16] } (fminnum:{ *:[f16] } (VOP3Mods:{ *:[f16] } f16:{ *:[f16] }:$src2, i32:{ *:[i32] }:$src2_mods), (fmaxnum_ieee:{ *:[f16] } (VOP3Mods:{ *:[f16] } f16:{ *:[f16] }:$src1, i32:{ *:[i32] }:$src1_mods), (VOP3Mods:{ *:[f16] } f16:{ *:[f16] }:$src0, i32:{ *:[i32] }:$src0_mods))), (fminnum_ieee:{ *:[f16] } (VOP3Mods:{ *:[f16] } f16:{ *:[f16] }:$src1, i32:{ *:[i32] }:$src1_mods), (VOP3Mods:{ *:[f16] } f16:{ *:[f16] }:$src0, i32:{ *:[i32] }:$src0_mods)))<<P:Predicate_fmaxnum_like_nnan>>  =>  (V_MED3_F16_e64:{ *:[f16] } ?:{ *:[i32] }:$src0_mods, ?:{ *:[f16] }:$src0, ?:{ *:[i32] }:$src1_mods, ?:{ *:[f16] }:$src1, ?:{ *:[i32] }:$src2_mods, ?:{ *:[f16] }:$src2, 0:{ *:[i1] })
        GIR_BuildMI, /*InsnID*/0, /*Opcode*/GIMT_Encode2(AMDGPU::V_MED3_F16_e64),
        GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/0, // DstI[vdst]
        GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(2), /*SubOperand*/1, // src0_mods
        GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(2), /*SubOperand*/0, // src0
        GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(1), /*SubOperand*/1, // src1_mods
        GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(1), /*SubOperand*/0, // src1
        GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/1, // src2_mods
        GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/0, // src2
        GIR_AddImm8, /*InsnID*/0, /*Imm*/0,
        GIR_AddImm8, /*InsnID*/0, /*Imm*/0,
        GIR_AddImm8, /*InsnID*/0, /*Imm*/0,
        GIR_ConstrainSelectedInstOperands, /*InsnID*/0,
        GIR_EraseFromParent, /*InsnID*/0,
        // GIR_Coverage, 10694,
        GIR_Done,
      // Label 4519: @295132
      GIM_Try, /*On fail goto*//*Label 4520*/ GIMT_Encode4(295278), // Rule ID 10762 //
        GIM_CheckFeatures, GIMT_Encode2(GIFBS_isGFX9Plus),
        GIM_CheckRegBankForClass, /*MI*/0, /*Op*/0, /*RC*/GIMT_Encode2(AMDGPU::VGPR_32RegClassID),
        GIM_RecordInsn, /*DefineMI*/1, /*MI*/0, /*OpIdx*/1, // MIs[1]
        GIM_CheckOpcode, /*MI*/1, GIMT_Encode2(TargetOpcode::G_FMINNUM),
        GIM_CheckType, /*MI*/1, /*Op*/1, /*Type*/GILLT_s16,
        GIM_CheckType, /*MI*/1, /*Op*/2, /*Type*/GILLT_s16,
        GIM_RecordInsn, /*DefineMI*/2, /*MI*/1, /*OpIdx*/1, // MIs[2]
        GIM_CheckOpcode, /*MI*/2, GIMT_Encode2(TargetOpcode::G_FMAXNUM),
        GIM_CheckType, /*MI*/2, /*Op*/1, /*Type*/GILLT_s16,
        GIM_CheckType, /*MI*/2, /*Op*/2, /*Type*/GILLT_s16,
        GIM_RecordInsn, /*DefineMI*/3, /*MI*/0, /*OpIdx*/2, // MIs[3]
        GIM_CheckOpcode, /*MI*/3, GIMT_Encode2(TargetOpcode::G_FMINNUM),
        // MIs[3] VOP3Mods:src0:src0_mods
        GIM_CheckIsSameOperand, /*MI*/3, /*OpIdx*/1, /*OtherMI*/2, /*OtherOpIdx*/1,
        // MIs[3] VOP3Mods:src1:src1_mods
        GIM_CheckIsSameOperand, /*MI*/3, /*OpIdx*/2, /*OtherMI*/2, /*OtherOpIdx*/2,
        GIM_CheckCxxInsnPredicate, /*MI*/0, /*FnId*/GIMT_Encode2(GICXXPred_MI_Predicate_fmaxnum_like_nnan),
        GIM_CheckIsSafeToFold, /*InsnID*/1,
        GIM_CheckIsSafeToFold, /*InsnID*/2,
        GIM_CheckIsSafeToFold, /*InsnID*/3,
        GIM_CheckComplexPattern, /*MI*/1, /*Op*/2, /*Renderer*/GIMT_Encode2(2), GIMT_Encode2(GICP_gi_vop3mods),
        GIM_CheckComplexPattern, /*MI*/2, /*Op*/1, /*Renderer*/GIMT_Encode2(0), GIMT_Encode2(GICP_gi_vop3mods),
        GIM_CheckComplexPattern, /*MI*/2, /*Op*/2, /*Renderer*/GIMT_Encode2(1), GIMT_Encode2(GICP_gi_vop3mods),
        // (fmaxnum:{ *:[f16] } (fminnum:{ *:[f16] } (fmaxnum:{ *:[f16] } (VOP3Mods:{ *:[f16] } f16:{ *:[f16] }:$src0, i32:{ *:[i32] }:$src0_mods), (VOP3Mods:{ *:[f16] } f16:{ *:[f16] }:$src1, i32:{ *:[i32] }:$src1_mods)), (VOP3Mods:{ *:[f16] } f16:{ *:[f16] }:$src2, i32:{ *:[i32] }:$src2_mods)), (fminnum:{ *:[f16] } (VOP3Mods:{ *:[f16] } f16:{ *:[f16] }:$src0, i32:{ *:[i32] }:$src0_mods), (VOP3Mods:{ *:[f16] } f16:{ *:[f16] }:$src1, i32:{ *:[i32] }:$src1_mods)))<<P:Predicate_fmaxnum_like_nnan>>  =>  (V_MED3_F16_e64:{ *:[f16] } ?:{ *:[i32] }:$src0_mods, ?:{ *:[f16] }:$src0, ?:{ *:[i32] }:$src1_mods, ?:{ *:[f16] }:$src1, ?:{ *:[i32] }:$src2_mods, ?:{ *:[f16] }:$src2, 0:{ *:[i1] })
        GIR_BuildMI, /*InsnID*/0, /*Opcode*/GIMT_Encode2(AMDGPU::V_MED3_F16_e64),
        GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/0, // DstI[vdst]
        GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/1, // src0_mods
        GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/0, // src0
        GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(1), /*SubOperand*/1, // src1_mods
        GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(1), /*SubOperand*/0, // src1
        GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(2), /*SubOperand*/1, // src2_mods
        GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(2), /*SubOperand*/0, // src2
        GIR_AddImm8, /*InsnID*/0, /*Imm*/0,
        GIR_AddImm8, /*InsnID*/0, /*Imm*/0,
        GIR_AddImm8, /*InsnID*/0, /*Imm*/0,
        GIR_ConstrainSelectedInstOperands, /*InsnID*/0,
        GIR_EraseFromParent, /*InsnID*/0,
        // GIR_Coverage, 10762,
        GIR_Done,
      // Label 4520: @295278
      GIM_Try, /*On fail goto*//*Label 4521*/ GIMT_Encode4(295424), // Rule ID 10763 //
        GIM_CheckFeatures, GIMT_Encode2(GIFBS_isGFX9Plus),
        GIM_CheckRegBankForClass, /*MI*/0, /*Op*/0, /*RC*/GIMT_Encode2(AMDGPU::VGPR_32RegClassID),
        GIM_RecordInsn, /*DefineMI*/1, /*MI*/0, /*OpIdx*/1, // MIs[1]
        GIM_CheckOpcode, /*MI*/1, GIMT_Encode2(TargetOpcode::G_FMINNUM),
        GIM_CheckType, /*MI*/1, /*Op*/1, /*Type*/GILLT_s16,
        GIM_CheckType, /*MI*/1, /*Op*/2, /*Type*/GILLT_s16,
        GIM_RecordInsn, /*DefineMI*/2, /*MI*/1, /*OpIdx*/1, // MIs[2]
        GIM_CheckOpcode, /*MI*/2, GIMT_Encode2(TargetOpcode::G_FMAXNUM),
        GIM_CheckType, /*MI*/2, /*Op*/1, /*Type*/GILLT_s16,
        GIM_CheckType, /*MI*/2, /*Op*/2, /*Type*/GILLT_s16,
        GIM_RecordInsn, /*DefineMI*/3, /*MI*/0, /*OpIdx*/2, // MIs[3]
        GIM_CheckOpcode, /*MI*/3, GIMT_Encode2(TargetOpcode::G_FMINNUM),
        // MIs[3] VOP3Mods:src1:src1_mods
        GIM_CheckIsSameOperand, /*MI*/3, /*OpIdx*/1, /*OtherMI*/2, /*OtherOpIdx*/2,
        // MIs[3] VOP3Mods:src0:src0_mods
        GIM_CheckIsSameOperand, /*MI*/3, /*OpIdx*/2, /*OtherMI*/2, /*OtherOpIdx*/1,
        GIM_CheckCxxInsnPredicate, /*MI*/0, /*FnId*/GIMT_Encode2(GICXXPred_MI_Predicate_fmaxnum_like_nnan),
        GIM_CheckIsSafeToFold, /*InsnID*/1,
        GIM_CheckIsSafeToFold, /*InsnID*/2,
        GIM_CheckIsSafeToFold, /*InsnID*/3,
        GIM_CheckComplexPattern, /*MI*/1, /*Op*/2, /*Renderer*/GIMT_Encode2(2), GIMT_Encode2(GICP_gi_vop3mods),
        GIM_CheckComplexPattern, /*MI*/2, /*Op*/1, /*Renderer*/GIMT_Encode2(0), GIMT_Encode2(GICP_gi_vop3mods),
        GIM_CheckComplexPattern, /*MI*/2, /*Op*/2, /*Renderer*/GIMT_Encode2(1), GIMT_Encode2(GICP_gi_vop3mods),
        // (fmaxnum:{ *:[f16] } (fminnum:{ *:[f16] } (fmaxnum:{ *:[f16] } (VOP3Mods:{ *:[f16] } f16:{ *:[f16] }:$src0, i32:{ *:[i32] }:$src0_mods), (VOP3Mods:{ *:[f16] } f16:{ *:[f16] }:$src1, i32:{ *:[i32] }:$src1_mods)), (VOP3Mods:{ *:[f16] } f16:{ *:[f16] }:$src2, i32:{ *:[i32] }:$src2_mods)), (fminnum:{ *:[f16] } (VOP3Mods:{ *:[f16] } f16:{ *:[f16] }:$src1, i32:{ *:[i32] }:$src1_mods), (VOP3Mods:{ *:[f16] } f16:{ *:[f16] }:$src0, i32:{ *:[i32] }:$src0_mods)))<<P:Predicate_fmaxnum_like_nnan>>  =>  (V_MED3_F16_e64:{ *:[f16] } ?:{ *:[i32] }:$src0_mods, ?:{ *:[f16] }:$src0, ?:{ *:[i32] }:$src1_mods, ?:{ *:[f16] }:$src1, ?:{ *:[i32] }:$src2_mods, ?:{ *:[f16] }:$src2, 0:{ *:[i1] })
        GIR_BuildMI, /*InsnID*/0, /*Opcode*/GIMT_Encode2(AMDGPU::V_MED3_F16_e64),
        GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/0, // DstI[vdst]
        GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/1, // src0_mods
        GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/0, // src0
        GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(1), /*SubOperand*/1, // src1_mods
        GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(1), /*SubOperand*/0, // src1
        GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(2), /*SubOperand*/1, // src2_mods
        GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(2), /*SubOperand*/0, // src2
        GIR_AddImm8, /*InsnID*/0, /*Imm*/0,
        GIR_AddImm8, /*InsnID*/0, /*Imm*/0,
        GIR_AddImm8, /*InsnID*/0, /*Imm*/0,
        GIR_ConstrainSelectedInstOperands, /*InsnID*/0,
        GIR_EraseFromParent, /*InsnID*/0,
        // GIR_Coverage, 10763,
        GIR_Done,
      // Label 4521: @295424
      GIM_Try, /*On fail goto*//*Label 4522*/ GIMT_Encode4(295570), // Rule ID 10764 //
        GIM_CheckFeatures, GIMT_Encode2(GIFBS_isGFX9Plus),
        GIM_CheckRegBankForClass, /*MI*/0, /*Op*/0, /*RC*/GIMT_Encode2(AMDGPU::VGPR_32RegClassID),
        GIM_RecordInsn, /*DefineMI*/1, /*MI*/0, /*OpIdx*/1, // MIs[1]
        GIM_CheckOpcode, /*MI*/1, GIMT_Encode2(TargetOpcode::G_FMINNUM),
        GIM_CheckType, /*MI*/1, /*Op*/1, /*Type*/GILLT_s16,
        GIM_CheckType, /*MI*/1, /*Op*/2, /*Type*/GILLT_s16,
        GIM_RecordInsn, /*DefineMI*/2, /*MI*/1, /*OpIdx*/1, // MIs[2]
        GIM_CheckOpcode, /*MI*/2, GIMT_Encode2(TargetOpcode::G_FMAXNUM),
        GIM_CheckType, /*MI*/2, /*Op*/1, /*Type*/GILLT_s16,
        GIM_CheckType, /*MI*/2, /*Op*/2, /*Type*/GILLT_s16,
        GIM_RecordInsn, /*DefineMI*/3, /*MI*/0, /*OpIdx*/2, // MIs[3]
        GIM_CheckOpcode, /*MI*/3, GIMT_Encode2(TargetOpcode::G_FMINNUM),
        // MIs[3] VOP3Mods:src0:src0_mods
        GIM_CheckIsSameOperand, /*MI*/3, /*OpIdx*/1, /*OtherMI*/2, /*OtherOpIdx*/2,
        // MIs[3] VOP3Mods:src1:src1_mods
        GIM_CheckIsSameOperand, /*MI*/3, /*OpIdx*/2, /*OtherMI*/2, /*OtherOpIdx*/1,
        GIM_CheckCxxInsnPredicate, /*MI*/0, /*FnId*/GIMT_Encode2(GICXXPred_MI_Predicate_fmaxnum_like_nnan),
        GIM_CheckIsSafeToFold, /*InsnID*/1,
        GIM_CheckIsSafeToFold, /*InsnID*/2,
        GIM_CheckIsSafeToFold, /*InsnID*/3,
        GIM_CheckComplexPattern, /*MI*/1, /*Op*/2, /*Renderer*/GIMT_Encode2(2), GIMT_Encode2(GICP_gi_vop3mods),
        GIM_CheckComplexPattern, /*MI*/2, /*Op*/1, /*Renderer*/GIMT_Encode2(0), GIMT_Encode2(GICP_gi_vop3mods),
        GIM_CheckComplexPattern, /*MI*/2, /*Op*/2, /*Renderer*/GIMT_Encode2(1), GIMT_Encode2(GICP_gi_vop3mods),
        // (fmaxnum:{ *:[f16] } (fminnum:{ *:[f16] } (fmaxnum:{ *:[f16] } (VOP3Mods:{ *:[f16] } f16:{ *:[f16] }:$src1, i32:{ *:[i32] }:$src1_mods), (VOP3Mods:{ *:[f16] } f16:{ *:[f16] }:$src0, i32:{ *:[i32] }:$src0_mods)), (VOP3Mods:{ *:[f16] } f16:{ *:[f16] }:$src2, i32:{ *:[i32] }:$src2_mods)), (fminnum:{ *:[f16] } (VOP3Mods:{ *:[f16] } f16:{ *:[f16] }:$src0, i32:{ *:[i32] }:$src0_mods), (VOP3Mods:{ *:[f16] } f16:{ *:[f16] }:$src1, i32:{ *:[i32] }:$src1_mods)))<<P:Predicate_fmaxnum_like_nnan>>  =>  (V_MED3_F16_e64:{ *:[f16] } ?:{ *:[i32] }:$src0_mods, ?:{ *:[f16] }:$src0, ?:{ *:[i32] }:$src1_mods, ?:{ *:[f16] }:$src1, ?:{ *:[i32] }:$src2_mods, ?:{ *:[f16] }:$src2, 0:{ *:[i1] })
        GIR_BuildMI, /*InsnID*/0, /*Opcode*/GIMT_Encode2(AMDGPU::V_MED3_F16_e64),
        GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/0, // DstI[vdst]
        GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(1), /*SubOperand*/1, // src0_mods
        GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(1), /*SubOperand*/0, // src0
        GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/1, // src1_mods
        GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/0, // src1
        GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(2), /*SubOperand*/1, // src2_mods
        GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(2), /*SubOperand*/0, // src2
        GIR_AddImm8, /*InsnID*/0, /*Imm*/0,
        GIR_AddImm8, /*InsnID*/0, /*Imm*/0,
        GIR_AddImm8, /*InsnID*/0, /*Imm*/0,
        GIR_ConstrainSelectedInstOperands, /*InsnID*/0,
        GIR_EraseFromParent, /*InsnID*/0,
        // GIR_Coverage, 10764,
        GIR_Done,
      // Label 4522: @295570
      GIM_Try, /*On fail goto*//*Label 4523*/ GIMT_Encode4(295716), // Rule ID 10765 //
        GIM_CheckFeatures, GIMT_Encode2(GIFBS_isGFX9Plus),
        GIM_CheckRegBankForClass, /*MI*/0, /*Op*/0, /*RC*/GIMT_Encode2(AMDGPU::VGPR_32RegClassID),
        GIM_RecordInsn, /*DefineMI*/1, /*MI*/0, /*OpIdx*/1, // MIs[1]
        GIM_CheckOpcode, /*MI*/1, GIMT_Encode2(TargetOpcode::G_FMINNUM),
        GIM_CheckType, /*MI*/1, /*Op*/1, /*Type*/GILLT_s16,
        GIM_CheckType, /*MI*/1, /*Op*/2, /*Type*/GILLT_s16,
        GIM_RecordInsn, /*DefineMI*/2, /*MI*/1, /*OpIdx*/1, // MIs[2]
        GIM_CheckOpcode, /*MI*/2, GIMT_Encode2(TargetOpcode::G_FMAXNUM),
        GIM_CheckType, /*MI*/2, /*Op*/1, /*Type*/GILLT_s16,
        GIM_CheckType, /*MI*/2, /*Op*/2, /*Type*/GILLT_s16,
        GIM_RecordInsn, /*DefineMI*/3, /*MI*/0, /*OpIdx*/2, // MIs[3]
        GIM_CheckOpcode, /*MI*/3, GIMT_Encode2(TargetOpcode::G_FMINNUM),
        // MIs[3] VOP3Mods:src1:src1_mods
        GIM_CheckIsSameOperand, /*MI*/3, /*OpIdx*/1, /*OtherMI*/2, /*OtherOpIdx*/1,
        // MIs[3] VOP3Mods:src0:src0_mods
        GIM_CheckIsSameOperand, /*MI*/3, /*OpIdx*/2, /*OtherMI*/2, /*OtherOpIdx*/2,
        GIM_CheckCxxInsnPredicate, /*MI*/0, /*FnId*/GIMT_Encode2(GICXXPred_MI_Predicate_fmaxnum_like_nnan),
        GIM_CheckIsSafeToFold, /*InsnID*/1,
        GIM_CheckIsSafeToFold, /*InsnID*/2,
        GIM_CheckIsSafeToFold, /*InsnID*/3,
        GIM_CheckComplexPattern, /*MI*/1, /*Op*/2, /*Renderer*/GIMT_Encode2(2), GIMT_Encode2(GICP_gi_vop3mods),
        GIM_CheckComplexPattern, /*MI*/2, /*Op*/1, /*Renderer*/GIMT_Encode2(0), GIMT_Encode2(GICP_gi_vop3mods),
        GIM_CheckComplexPattern, /*MI*/2, /*Op*/2, /*Renderer*/GIMT_Encode2(1), GIMT_Encode2(GICP_gi_vop3mods),
        // (fmaxnum:{ *:[f16] } (fminnum:{ *:[f16] } (fmaxnum:{ *:[f16] } (VOP3Mods:{ *:[f16] } f16:{ *:[f16] }:$src1, i32:{ *:[i32] }:$src1_mods), (VOP3Mods:{ *:[f16] } f16:{ *:[f16] }:$src0, i32:{ *:[i32] }:$src0_mods)), (VOP3Mods:{ *:[f16] } f16:{ *:[f16] }:$src2, i32:{ *:[i32] }:$src2_mods)), (fminnum:{ *:[f16] } (VOP3Mods:{ *:[f16] } f16:{ *:[f16] }:$src1, i32:{ *:[i32] }:$src1_mods), (VOP3Mods:{ *:[f16] } f16:{ *:[f16] }:$src0, i32:{ *:[i32] }:$src0_mods)))<<P:Predicate_fmaxnum_like_nnan>>  =>  (V_MED3_F16_e64:{ *:[f16] } ?:{ *:[i32] }:$src0_mods, ?:{ *:[f16] }:$src0, ?:{ *:[i32] }:$src1_mods, ?:{ *:[f16] }:$src1, ?:{ *:[i32] }:$src2_mods, ?:{ *:[f16] }:$src2, 0:{ *:[i1] })
        GIR_BuildMI, /*InsnID*/0, /*Opcode*/GIMT_Encode2(AMDGPU::V_MED3_F16_e64),
        GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/0, // DstI[vdst]
        GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(1), /*SubOperand*/1, // src0_mods
        GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(1), /*SubOperand*/0, // src0
        GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/1, // src1_mods
        GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/0, // src1
        GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(2), /*SubOperand*/1, // src2_mods
        GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(2), /*SubOperand*/0, // src2
        GIR_AddImm8, /*InsnID*/0, /*Imm*/0,
        GIR_AddImm8, /*InsnID*/0, /*Imm*/0,
        GIR_AddImm8, /*InsnID*/0, /*Imm*/0,
        GIR_ConstrainSelectedInstOperands, /*InsnID*/0,
        GIR_EraseFromParent, /*InsnID*/0,
        // GIR_Coverage, 10765,
        GIR_Done,
      // Label 4523: @295716
      GIM_Try, /*On fail goto*//*Label 4524*/ GIMT_Encode4(295862), // Rule ID 10702 //
        GIM_CheckFeatures, GIMT_Encode2(GIFBS_isGFX9Plus),
        GIM_CheckRegBankForClass, /*MI*/0, /*Op*/0, /*RC*/GIMT_Encode2(AMDGPU::VGPR_32RegClassID),
        GIM_RecordInsn, /*DefineMI*/1, /*MI*/0, /*OpIdx*/1, // MIs[1]
        GIM_CheckOpcode, /*MI*/1, GIMT_Encode2(TargetOpcode::G_FMINNUM),
        GIM_CheckType, /*MI*/1, /*Op*/1, /*Type*/GILLT_s16,
        GIM_CheckType, /*MI*/1, /*Op*/2, /*Type*/GILLT_s16,
        GIM_RecordInsn, /*DefineMI*/2, /*MI*/1, /*OpIdx*/1, // MIs[2]
        GIM_CheckOpcode, /*MI*/2, GIMT_Encode2(TargetOpcode::G_FMAXNUM),
        GIM_CheckType, /*MI*/2, /*Op*/1, /*Type*/GILLT_s16,
        GIM_CheckType, /*MI*/2, /*Op*/2, /*Type*/GILLT_s16,
        GIM_RecordInsn, /*DefineMI*/3, /*MI*/0, /*OpIdx*/2, // MIs[3]
        GIM_CheckOpcode, /*MI*/3, GIMT_Encode2(TargetOpcode::G_FMINNUM_IEEE),
        // MIs[3] VOP3Mods:src0:src0_mods
        GIM_CheckIsSameOperand, /*MI*/3, /*OpIdx*/1, /*OtherMI*/2, /*OtherOpIdx*/1,
        // MIs[3] VOP3Mods:src1:src1_mods
        GIM_CheckIsSameOperand, /*MI*/3, /*OpIdx*/2, /*OtherMI*/2, /*OtherOpIdx*/2,
        GIM_CheckCxxInsnPredicate, /*MI*/0, /*FnId*/GIMT_Encode2(GICXXPred_MI_Predicate_fmaxnum_like_nnan),
        GIM_CheckIsSafeToFold, /*InsnID*/1,
        GIM_CheckIsSafeToFold, /*InsnID*/2,
        GIM_CheckIsSafeToFold, /*InsnID*/3,
        GIM_CheckComplexPattern, /*MI*/1, /*Op*/2, /*Renderer*/GIMT_Encode2(2), GIMT_Encode2(GICP_gi_vop3mods),
        GIM_CheckComplexPattern, /*MI*/2, /*Op*/1, /*Renderer*/GIMT_Encode2(0), GIMT_Encode2(GICP_gi_vop3mods),
        GIM_CheckComplexPattern, /*MI*/2, /*Op*/2, /*Renderer*/GIMT_Encode2(1), GIMT_Encode2(GICP_gi_vop3mods),
        // (fmaxnum:{ *:[f16] } (fminnum:{ *:[f16] } (fmaxnum:{ *:[f16] } (VOP3Mods:{ *:[f16] } f16:{ *:[f16] }:$src0, i32:{ *:[i32] }:$src0_mods), (VOP3Mods:{ *:[f16] } f16:{ *:[f16] }:$src1, i32:{ *:[i32] }:$src1_mods)), (VOP3Mods:{ *:[f16] } f16:{ *:[f16] }:$src2, i32:{ *:[i32] }:$src2_mods)), (fminnum_ieee:{ *:[f16] } (VOP3Mods:{ *:[f16] } f16:{ *:[f16] }:$src0, i32:{ *:[i32] }:$src0_mods), (VOP3Mods:{ *:[f16] } f16:{ *:[f16] }:$src1, i32:{ *:[i32] }:$src1_mods)))<<P:Predicate_fmaxnum_like_nnan>>  =>  (V_MED3_F16_e64:{ *:[f16] } ?:{ *:[i32] }:$src0_mods, ?:{ *:[f16] }:$src0, ?:{ *:[i32] }:$src1_mods, ?:{ *:[f16] }:$src1, ?:{ *:[i32] }:$src2_mods, ?:{ *:[f16] }:$src2, 0:{ *:[i1] })
        GIR_BuildMI, /*InsnID*/0, /*Opcode*/GIMT_Encode2(AMDGPU::V_MED3_F16_e64),
        GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/0, // DstI[vdst]
        GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/1, // src0_mods
        GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/0, // src0
        GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(1), /*SubOperand*/1, // src1_mods
        GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(1), /*SubOperand*/0, // src1
        GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(2), /*SubOperand*/1, // src2_mods
        GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(2), /*SubOperand*/0, // src2
        GIR_AddImm8, /*InsnID*/0, /*Imm*/0,
        GIR_AddImm8, /*InsnID*/0, /*Imm*/0,
        GIR_AddImm8, /*InsnID*/0, /*Imm*/0,
        GIR_ConstrainSelectedInstOperands, /*InsnID*/0,
        GIR_EraseFromParent, /*InsnID*/0,
        // GIR_Coverage, 10702,
        GIR_Done,
      // Label 4524: @295862
      GIM_Try, /*On fail goto*//*Label 4525*/ GIMT_Encode4(296008), // Rule ID 10703 //
        GIM_CheckFeatures, GIMT_Encode2(GIFBS_isGFX9Plus),
        GIM_CheckRegBankForClass, /*MI*/0, /*Op*/0, /*RC*/GIMT_Encode2(AMDGPU::VGPR_32RegClassID),
        GIM_RecordInsn, /*DefineMI*/1, /*MI*/0, /*OpIdx*/1, // MIs[1]
        GIM_CheckOpcode, /*MI*/1, GIMT_Encode2(TargetOpcode::G_FMINNUM),
        GIM_CheckType, /*MI*/1, /*Op*/1, /*Type*/GILLT_s16,
        GIM_CheckType, /*MI*/1, /*Op*/2, /*Type*/GILLT_s16,
        GIM_RecordInsn, /*DefineMI*/2, /*MI*/1, /*OpIdx*/1, // MIs[2]
        GIM_CheckOpcode, /*MI*/2, GIMT_Encode2(TargetOpcode::G_FMAXNUM),
        GIM_CheckType, /*MI*/2, /*Op*/1, /*Type*/GILLT_s16,
        GIM_CheckType, /*MI*/2, /*Op*/2, /*Type*/GILLT_s16,
        GIM_RecordInsn, /*DefineMI*/3, /*MI*/0, /*OpIdx*/2, // MIs[3]
        GIM_CheckOpcode, /*MI*/3, GIMT_Encode2(TargetOpcode::G_FMINNUM_IEEE),
        // MIs[3] VOP3Mods:src1:src1_mods
        GIM_CheckIsSameOperand, /*MI*/3, /*OpIdx*/1, /*OtherMI*/2, /*OtherOpIdx*/2,
        // MIs[3] VOP3Mods:src0:src0_mods
        GIM_CheckIsSameOperand, /*MI*/3, /*OpIdx*/2, /*OtherMI*/2, /*OtherOpIdx*/1,
        GIM_CheckCxxInsnPredicate, /*MI*/0, /*FnId*/GIMT_Encode2(GICXXPred_MI_Predicate_fmaxnum_like_nnan),
        GIM_CheckIsSafeToFold, /*InsnID*/1,
        GIM_CheckIsSafeToFold, /*InsnID*/2,
        GIM_CheckIsSafeToFold, /*InsnID*/3,
        GIM_CheckComplexPattern, /*MI*/1, /*Op*/2, /*Renderer*/GIMT_Encode2(2), GIMT_Encode2(GICP_gi_vop3mods),
        GIM_CheckComplexPattern, /*MI*/2, /*Op*/1, /*Renderer*/GIMT_Encode2(0), GIMT_Encode2(GICP_gi_vop3mods),
        GIM_CheckComplexPattern, /*MI*/2, /*Op*/2, /*Renderer*/GIMT_Encode2(1), GIMT_Encode2(GICP_gi_vop3mods),
        // (fmaxnum:{ *:[f16] } (fminnum:{ *:[f16] } (fmaxnum:{ *:[f16] } (VOP3Mods:{ *:[f16] } f16:{ *:[f16] }:$src0, i32:{ *:[i32] }:$src0_mods), (VOP3Mods:{ *:[f16] } f16:{ *:[f16] }:$src1, i32:{ *:[i32] }:$src1_mods)), (VOP3Mods:{ *:[f16] } f16:{ *:[f16] }:$src2, i32:{ *:[i32] }:$src2_mods)), (fminnum_ieee:{ *:[f16] } (VOP3Mods:{ *:[f16] } f16:{ *:[f16] }:$src1, i32:{ *:[i32] }:$src1_mods), (VOP3Mods:{ *:[f16] } f16:{ *:[f16] }:$src0, i32:{ *:[i32] }:$src0_mods)))<<P:Predicate_fmaxnum_like_nnan>>  =>  (V_MED3_F16_e64:{ *:[f16] } ?:{ *:[i32] }:$src0_mods, ?:{ *:[f16] }:$src0, ?:{ *:[i32] }:$src1_mods, ?:{ *:[f16] }:$src1, ?:{ *:[i32] }:$src2_mods, ?:{ *:[f16] }:$src2, 0:{ *:[i1] })
        GIR_BuildMI, /*InsnID*/0, /*Opcode*/GIMT_Encode2(AMDGPU::V_MED3_F16_e64),
        GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/0, // DstI[vdst]
        GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/1, // src0_mods
        GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/0, // src0
        GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(1), /*SubOperand*/1, // src1_mods
        GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(1), /*SubOperand*/0, // src1
        GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(2), /*SubOperand*/1, // src2_mods
        GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(2), /*SubOperand*/0, // src2
        GIR_AddImm8, /*InsnID*/0, /*Imm*/0,
        GIR_AddImm8, /*InsnID*/0, /*Imm*/0,
        GIR_AddImm8, /*InsnID*/0, /*Imm*/0,
        GIR_ConstrainSelectedInstOperands, /*InsnID*/0,
        GIR_EraseFromParent, /*InsnID*/0,
        // GIR_Coverage, 10703,
        GIR_Done,
      // Label 4525: @296008
      GIM_Try, /*On fail goto*//*Label 4526*/ GIMT_Encode4(296154), // Rule ID 10704 //
        GIM_CheckFeatures, GIMT_Encode2(GIFBS_isGFX9Plus),
        GIM_CheckRegBankForClass, /*MI*/0, /*Op*/0, /*RC*/GIMT_Encode2(AMDGPU::VGPR_32RegClassID),
        GIM_RecordInsn, /*DefineMI*/1, /*MI*/0, /*OpIdx*/1, // MIs[1]
        GIM_CheckOpcode, /*MI*/1, GIMT_Encode2(TargetOpcode::G_FMINNUM),
        GIM_CheckType, /*MI*/1, /*Op*/1, /*Type*/GILLT_s16,
        GIM_CheckType, /*MI*/1, /*Op*/2, /*Type*/GILLT_s16,
        GIM_RecordInsn, /*DefineMI*/2, /*MI*/1, /*OpIdx*/1, // MIs[2]
        GIM_CheckOpcode, /*MI*/2, GIMT_Encode2(TargetOpcode::G_FMAXNUM),
        GIM_CheckType, /*MI*/2, /*Op*/1, /*Type*/GILLT_s16,
        GIM_CheckType, /*MI*/2, /*Op*/2, /*Type*/GILLT_s16,
        GIM_RecordInsn, /*DefineMI*/3, /*MI*/0, /*OpIdx*/2, // MIs[3]
        GIM_CheckOpcode, /*MI*/3, GIMT_Encode2(TargetOpcode::G_FMINNUM_IEEE),
        // MIs[3] VOP3Mods:src0:src0_mods
        GIM_CheckIsSameOperand, /*MI*/3, /*OpIdx*/1, /*OtherMI*/2, /*OtherOpIdx*/2,
        // MIs[3] VOP3Mods:src1:src1_mods
        GIM_CheckIsSameOperand, /*MI*/3, /*OpIdx*/2, /*OtherMI*/2, /*OtherOpIdx*/1,
        GIM_CheckCxxInsnPredicate, /*MI*/0, /*FnId*/GIMT_Encode2(GICXXPred_MI_Predicate_fmaxnum_like_nnan),
        GIM_CheckIsSafeToFold, /*InsnID*/1,
        GIM_CheckIsSafeToFold, /*InsnID*/2,
        GIM_CheckIsSafeToFold, /*InsnID*/3,
        GIM_CheckComplexPattern, /*MI*/1, /*Op*/2, /*Renderer*/GIMT_Encode2(2), GIMT_Encode2(GICP_gi_vop3mods),
        GIM_CheckComplexPattern, /*MI*/2, /*Op*/1, /*Renderer*/GIMT_Encode2(0), GIMT_Encode2(GICP_gi_vop3mods),
        GIM_CheckComplexPattern, /*MI*/2, /*Op*/2, /*Renderer*/GIMT_Encode2(1), GIMT_Encode2(GICP_gi_vop3mods),
        // (fmaxnum:{ *:[f16] } (fminnum:{ *:[f16] } (fmaxnum:{ *:[f16] } (VOP3Mods:{ *:[f16] } f16:{ *:[f16] }:$src1, i32:{ *:[i32] }:$src1_mods), (VOP3Mods:{ *:[f16] } f16:{ *:[f16] }:$src0, i32:{ *:[i32] }:$src0_mods)), (VOP3Mods:{ *:[f16] } f16:{ *:[f16] }:$src2, i32:{ *:[i32] }:$src2_mods)), (fminnum_ieee:{ *:[f16] } (VOP3Mods:{ *:[f16] } f16:{ *:[f16] }:$src0, i32:{ *:[i32] }:$src0_mods), (VOP3Mods:{ *:[f16] } f16:{ *:[f16] }:$src1, i32:{ *:[i32] }:$src1_mods)))<<P:Predicate_fmaxnum_like_nnan>>  =>  (V_MED3_F16_e64:{ *:[f16] } ?:{ *:[i32] }:$src0_mods, ?:{ *:[f16] }:$src0, ?:{ *:[i32] }:$src1_mods, ?:{ *:[f16] }:$src1, ?:{ *:[i32] }:$src2_mods, ?:{ *:[f16] }:$src2, 0:{ *:[i1] })
        GIR_BuildMI, /*InsnID*/0, /*Opcode*/GIMT_Encode2(AMDGPU::V_MED3_F16_e64),
        GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/0, // DstI[vdst]
        GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(1), /*SubOperand*/1, // src0_mods
        GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(1), /*SubOperand*/0, // src0
        GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/1, // src1_mods
        GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/0, // src1
        GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(2), /*SubOperand*/1, // src2_mods
        GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(2), /*SubOperand*/0, // src2
        GIR_AddImm8, /*InsnID*/0, /*Imm*/0,
        GIR_AddImm8, /*InsnID*/0, /*Imm*/0,
        GIR_AddImm8, /*InsnID*/0, /*Imm*/0,
        GIR_ConstrainSelectedInstOperands, /*InsnID*/0,
        GIR_EraseFromParent, /*InsnID*/0,
        // GIR_Coverage, 10704,
        GIR_Done,
      // Label 4526: @296154
      GIM_Try, /*On fail goto*//*Label 4527*/ GIMT_Encode4(296300), // Rule ID 10705 //
        GIM_CheckFeatures, GIMT_Encode2(GIFBS_isGFX9Plus),
        GIM_CheckRegBankForClass, /*MI*/0, /*Op*/0, /*RC*/GIMT_Encode2(AMDGPU::VGPR_32RegClassID),
        GIM_RecordInsn, /*DefineMI*/1, /*MI*/0, /*OpIdx*/1, // MIs[1]
        GIM_CheckOpcode, /*MI*/1, GIMT_Encode2(TargetOpcode::G_FMINNUM),
        GIM_CheckType, /*MI*/1, /*Op*/1, /*Type*/GILLT_s16,
        GIM_CheckType, /*MI*/1, /*Op*/2, /*Type*/GILLT_s16,
        GIM_RecordInsn, /*DefineMI*/2, /*MI*/1, /*OpIdx*/1, // MIs[2]
        GIM_CheckOpcode, /*MI*/2, GIMT_Encode2(TargetOpcode::G_FMAXNUM),
        GIM_CheckType, /*MI*/2, /*Op*/1, /*Type*/GILLT_s16,
        GIM_CheckType, /*MI*/2, /*Op*/2, /*Type*/GILLT_s16,
        GIM_RecordInsn, /*DefineMI*/3, /*MI*/0, /*OpIdx*/2, // MIs[3]
        GIM_CheckOpcode, /*MI*/3, GIMT_Encode2(TargetOpcode::G_FMINNUM_IEEE),
        // MIs[3] VOP3Mods:src1:src1_mods
        GIM_CheckIsSameOperand, /*MI*/3, /*OpIdx*/1, /*OtherMI*/2, /*OtherOpIdx*/1,
        // MIs[3] VOP3Mods:src0:src0_mods
        GIM_CheckIsSameOperand, /*MI*/3, /*OpIdx*/2, /*OtherMI*/2, /*OtherOpIdx*/2,
        GIM_CheckCxxInsnPredicate, /*MI*/0, /*FnId*/GIMT_Encode2(GICXXPred_MI_Predicate_fmaxnum_like_nnan),
        GIM_CheckIsSafeToFold, /*InsnID*/1,
        GIM_CheckIsSafeToFold, /*InsnID*/2,
        GIM_CheckIsSafeToFold, /*InsnID*/3,
        GIM_CheckComplexPattern, /*MI*/1, /*Op*/2, /*Renderer*/GIMT_Encode2(2), GIMT_Encode2(GICP_gi_vop3mods),
        GIM_CheckComplexPattern, /*MI*/2, /*Op*/1, /*Renderer*/GIMT_Encode2(0), GIMT_Encode2(GICP_gi_vop3mods),
        GIM_CheckComplexPattern, /*MI*/2, /*Op*/2, /*Renderer*/GIMT_Encode2(1), GIMT_Encode2(GICP_gi_vop3mods),
        // (fmaxnum:{ *:[f16] } (fminnum:{ *:[f16] } (fmaxnum:{ *:[f16] } (VOP3Mods:{ *:[f16] } f16:{ *:[f16] }:$src1, i32:{ *:[i32] }:$src1_mods), (VOP3Mods:{ *:[f16] } f16:{ *:[f16] }:$src0, i32:{ *:[i32] }:$src0_mods)), (VOP3Mods:{ *:[f16] } f16:{ *:[f16] }:$src2, i32:{ *:[i32] }:$src2_mods)), (fminnum_ieee:{ *:[f16] } (VOP3Mods:{ *:[f16] } f16:{ *:[f16] }:$src1, i32:{ *:[i32] }:$src1_mods), (VOP3Mods:{ *:[f16] } f16:{ *:[f16] }:$src0, i32:{ *:[i32] }:$src0_mods)))<<P:Predicate_fmaxnum_like_nnan>>  =>  (V_MED3_F16_e64:{ *:[f16] } ?:{ *:[i32] }:$src0_mods, ?:{ *:[f16] }:$src0, ?:{ *:[i32] }:$src1_mods, ?:{ *:[f16] }:$src1, ?:{ *:[i32] }:$src2_mods, ?:{ *:[f16] }:$src2, 0:{ *:[i1] })
        GIR_BuildMI, /*InsnID*/0, /*Opcode*/GIMT_Encode2(AMDGPU::V_MED3_F16_e64),
        GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/0, // DstI[vdst]
        GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(1), /*SubOperand*/1, // src0_mods
        GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(1), /*SubOperand*/0, // src0
        GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/1, // src1_mods
        GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/0, // src1
        GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(2), /*SubOperand*/1, // src2_mods
        GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(2), /*SubOperand*/0, // src2
        GIR_AddImm8, /*InsnID*/0, /*Imm*/0,
        GIR_AddImm8, /*InsnID*/0, /*Imm*/0,
        GIR_AddImm8, /*InsnID*/0, /*Imm*/0,
        GIR_ConstrainSelectedInstOperands, /*InsnID*/0,
        GIR_EraseFromParent, /*InsnID*/0,
        // GIR_Coverage, 10705,
        GIR_Done,
      // Label 4527: @296300
      GIM_Try, /*On fail goto*//*Label 4528*/ GIMT_Encode4(296446), // Rule ID 10747 //
        GIM_CheckFeatures, GIMT_Encode2(GIFBS_isGFX9Plus),
        GIM_CheckRegBankForClass, /*MI*/0, /*Op*/0, /*RC*/GIMT_Encode2(AMDGPU::VGPR_32RegClassID),
        GIM_RecordInsn, /*DefineMI*/1, /*MI*/0, /*OpIdx*/1, // MIs[1]
        GIM_CheckOpcode, /*MI*/1, GIMT_Encode2(TargetOpcode::G_FMINNUM),
        GIM_CheckType, /*MI*/1, /*Op*/1, /*Type*/GILLT_s16,
        GIM_CheckType, /*MI*/1, /*Op*/2, /*Type*/GILLT_s16,
        GIM_RecordInsn, /*DefineMI*/2, /*MI*/1, /*OpIdx*/1, // MIs[2]
        GIM_CheckOpcode, /*MI*/2, GIMT_Encode2(TargetOpcode::G_FMAXNUM_IEEE),
        GIM_CheckType, /*MI*/2, /*Op*/1, /*Type*/GILLT_s16,
        GIM_CheckType, /*MI*/2, /*Op*/2, /*Type*/GILLT_s16,
        GIM_RecordInsn, /*DefineMI*/3, /*MI*/0, /*OpIdx*/2, // MIs[3]
        GIM_CheckOpcode, /*MI*/3, GIMT_Encode2(TargetOpcode::G_FMINNUM),
        // MIs[3] VOP3Mods:src0:src0_mods
        GIM_CheckIsSameOperand, /*MI*/3, /*OpIdx*/1, /*OtherMI*/2, /*OtherOpIdx*/1,
        // MIs[3] VOP3Mods:src1:src1_mods
        GIM_CheckIsSameOperand, /*MI*/3, /*OpIdx*/2, /*OtherMI*/2, /*OtherOpIdx*/2,
        GIM_CheckCxxInsnPredicate, /*MI*/0, /*FnId*/GIMT_Encode2(GICXXPred_MI_Predicate_fmaxnum_like_nnan),
        GIM_CheckIsSafeToFold, /*InsnID*/1,
        GIM_CheckIsSafeToFold, /*InsnID*/2,
        GIM_CheckIsSafeToFold, /*InsnID*/3,
        GIM_CheckComplexPattern, /*MI*/1, /*Op*/2, /*Renderer*/GIMT_Encode2(2), GIMT_Encode2(GICP_gi_vop3mods),
        GIM_CheckComplexPattern, /*MI*/2, /*Op*/1, /*Renderer*/GIMT_Encode2(0), GIMT_Encode2(GICP_gi_vop3mods),
        GIM_CheckComplexPattern, /*MI*/2, /*Op*/2, /*Renderer*/GIMT_Encode2(1), GIMT_Encode2(GICP_gi_vop3mods),
        // (fmaxnum:{ *:[f16] } (fminnum:{ *:[f16] } (fmaxnum_ieee:{ *:[f16] } (VOP3Mods:{ *:[f16] } f16:{ *:[f16] }:$src0, i32:{ *:[i32] }:$src0_mods), (VOP3Mods:{ *:[f16] } f16:{ *:[f16] }:$src1, i32:{ *:[i32] }:$src1_mods)), (VOP3Mods:{ *:[f16] } f16:{ *:[f16] }:$src2, i32:{ *:[i32] }:$src2_mods)), (fminnum:{ *:[f16] } (VOP3Mods:{ *:[f16] } f16:{ *:[f16] }:$src0, i32:{ *:[i32] }:$src0_mods), (VOP3Mods:{ *:[f16] } f16:{ *:[f16] }:$src1, i32:{ *:[i32] }:$src1_mods)))<<P:Predicate_fmaxnum_like_nnan>>  =>  (V_MED3_F16_e64:{ *:[f16] } ?:{ *:[i32] }:$src0_mods, ?:{ *:[f16] }:$src0, ?:{ *:[i32] }:$src1_mods, ?:{ *:[f16] }:$src1, ?:{ *:[i32] }:$src2_mods, ?:{ *:[f16] }:$src2, 0:{ *:[i1] })
        GIR_BuildMI, /*InsnID*/0, /*Opcode*/GIMT_Encode2(AMDGPU::V_MED3_F16_e64),
        GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/0, // DstI[vdst]
        GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/1, // src0_mods
        GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/0, // src0
        GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(1), /*SubOperand*/1, // src1_mods
        GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(1), /*SubOperand*/0, // src1
        GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(2), /*SubOperand*/1, // src2_mods
        GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(2), /*SubOperand*/0, // src2
        GIR_AddImm8, /*InsnID*/0, /*Imm*/0,
        GIR_AddImm8, /*InsnID*/0, /*Imm*/0,
        GIR_AddImm8, /*InsnID*/0, /*Imm*/0,
        GIR_ConstrainSelectedInstOperands, /*InsnID*/0,
        GIR_EraseFromParent, /*InsnID*/0,
        // GIR_Coverage, 10747,
        GIR_Done,
      // Label 4528: @296446
      GIM_Try, /*On fail goto*//*Label 4529*/ GIMT_Encode4(296592), // Rule ID 10748 //
        GIM_CheckFeatures, GIMT_Encode2(GIFBS_isGFX9Plus),
        GIM_CheckRegBankForClass, /*MI*/0, /*Op*/0, /*RC*/GIMT_Encode2(AMDGPU::VGPR_32RegClassID),
        GIM_RecordInsn, /*DefineMI*/1, /*MI*/0, /*OpIdx*/1, // MIs[1]
        GIM_CheckOpcode, /*MI*/1, GIMT_Encode2(TargetOpcode::G_FMINNUM),
        GIM_CheckType, /*MI*/1, /*Op*/1, /*Type*/GILLT_s16,
        GIM_CheckType, /*MI*/1, /*Op*/2, /*Type*/GILLT_s16,
        GIM_RecordInsn, /*DefineMI*/2, /*MI*/1, /*OpIdx*/1, // MIs[2]
        GIM_CheckOpcode, /*MI*/2, GIMT_Encode2(TargetOpcode::G_FMAXNUM_IEEE),
        GIM_CheckType, /*MI*/2, /*Op*/1, /*Type*/GILLT_s16,
        GIM_CheckType, /*MI*/2, /*Op*/2, /*Type*/GILLT_s16,
        GIM_RecordInsn, /*DefineMI*/3, /*MI*/0, /*OpIdx*/2, // MIs[3]
        GIM_CheckOpcode, /*MI*/3, GIMT_Encode2(TargetOpcode::G_FMINNUM),
        // MIs[3] VOP3Mods:src1:src1_mods
        GIM_CheckIsSameOperand, /*MI*/3, /*OpIdx*/1, /*OtherMI*/2, /*OtherOpIdx*/2,
        // MIs[3] VOP3Mods:src0:src0_mods
        GIM_CheckIsSameOperand, /*MI*/3, /*OpIdx*/2, /*OtherMI*/2, /*OtherOpIdx*/1,
        GIM_CheckCxxInsnPredicate, /*MI*/0, /*FnId*/GIMT_Encode2(GICXXPred_MI_Predicate_fmaxnum_like_nnan),
        GIM_CheckIsSafeToFold, /*InsnID*/1,
        GIM_CheckIsSafeToFold, /*InsnID*/2,
        GIM_CheckIsSafeToFold, /*InsnID*/3,
        GIM_CheckComplexPattern, /*MI*/1, /*Op*/2, /*Renderer*/GIMT_Encode2(2), GIMT_Encode2(GICP_gi_vop3mods),
        GIM_CheckComplexPattern, /*MI*/2, /*Op*/1, /*Renderer*/GIMT_Encode2(0), GIMT_Encode2(GICP_gi_vop3mods),
        GIM_CheckComplexPattern, /*MI*/2, /*Op*/2, /*Renderer*/GIMT_Encode2(1), GIMT_Encode2(GICP_gi_vop3mods),
        // (fmaxnum:{ *:[f16] } (fminnum:{ *:[f16] } (fmaxnum_ieee:{ *:[f16] } (VOP3Mods:{ *:[f16] } f16:{ *:[f16] }:$src0, i32:{ *:[i32] }:$src0_mods), (VOP3Mods:{ *:[f16] } f16:{ *:[f16] }:$src1, i32:{ *:[i32] }:$src1_mods)), (VOP3Mods:{ *:[f16] } f16:{ *:[f16] }:$src2, i32:{ *:[i32] }:$src2_mods)), (fminnum:{ *:[f16] } (VOP3Mods:{ *:[f16] } f16:{ *:[f16] }:$src1, i32:{ *:[i32] }:$src1_mods), (VOP3Mods:{ *:[f16] } f16:{ *:[f16] }:$src0, i32:{ *:[i32] }:$src0_mods)))<<P:Predicate_fmaxnum_like_nnan>>  =>  (V_MED3_F16_e64:{ *:[f16] } ?:{ *:[i32] }:$src0_mods, ?:{ *:[f16] }:$src0, ?:{ *:[i32] }:$src1_mods, ?:{ *:[f16] }:$src1, ?:{ *:[i32] }:$src2_mods, ?:{ *:[f16] }:$src2, 0:{ *:[i1] })
        GIR_BuildMI, /*InsnID*/0, /*Opcode*/GIMT_Encode2(AMDGPU::V_MED3_F16_e64),
        GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/0, // DstI[vdst]
        GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/1, // src0_mods
        GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/0, // src0
        GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(1), /*SubOperand*/1, // src1_mods
        GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(1), /*SubOperand*/0, // src1
        GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(2), /*SubOperand*/1, // src2_mods
        GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(2), /*SubOperand*/0, // src2
        GIR_AddImm8, /*InsnID*/0, /*Imm*/0,
        GIR_AddImm8, /*InsnID*/0, /*Imm*/0,
        GIR_AddImm8, /*InsnID*/0, /*Imm*/0,
        GIR_ConstrainSelectedInstOperands, /*InsnID*/0,
        GIR_EraseFromParent, /*InsnID*/0,
        // GIR_Coverage, 10748,
        GIR_Done,
      // Label 4529: @296592
      GIM_Try, /*On fail goto*//*Label 4530*/ GIMT_Encode4(296738), // Rule ID 10749 //
        GIM_CheckFeatures, GIMT_Encode2(GIFBS_isGFX9Plus),
        GIM_CheckRegBankForClass, /*MI*/0, /*Op*/0, /*RC*/GIMT_Encode2(AMDGPU::VGPR_32RegClassID),
        GIM_RecordInsn, /*DefineMI*/1, /*MI*/0, /*OpIdx*/1, // MIs[1]
        GIM_CheckOpcode, /*MI*/1, GIMT_Encode2(TargetOpcode::G_FMINNUM),
        GIM_CheckType, /*MI*/1, /*Op*/1, /*Type*/GILLT_s16,
        GIM_CheckType, /*MI*/1, /*Op*/2, /*Type*/GILLT_s16,
        GIM_RecordInsn, /*DefineMI*/2, /*MI*/1, /*OpIdx*/1, // MIs[2]
        GIM_CheckOpcode, /*MI*/2, GIMT_Encode2(TargetOpcode::G_FMAXNUM_IEEE),
        GIM_CheckType, /*MI*/2, /*Op*/1, /*Type*/GILLT_s16,
        GIM_CheckType, /*MI*/2, /*Op*/2, /*Type*/GILLT_s16,
        GIM_RecordInsn, /*DefineMI*/3, /*MI*/0, /*OpIdx*/2, // MIs[3]
        GIM_CheckOpcode, /*MI*/3, GIMT_Encode2(TargetOpcode::G_FMINNUM),
        // MIs[3] VOP3Mods:src0:src0_mods
        GIM_CheckIsSameOperand, /*MI*/3, /*OpIdx*/1, /*OtherMI*/2, /*OtherOpIdx*/2,
        // MIs[3] VOP3Mods:src1:src1_mods
        GIM_CheckIsSameOperand, /*MI*/3, /*OpIdx*/2, /*OtherMI*/2, /*OtherOpIdx*/1,
        GIM_CheckCxxInsnPredicate, /*MI*/0, /*FnId*/GIMT_Encode2(GICXXPred_MI_Predicate_fmaxnum_like_nnan),
        GIM_CheckIsSafeToFold, /*InsnID*/1,
        GIM_CheckIsSafeToFold, /*InsnID*/2,
        GIM_CheckIsSafeToFold, /*InsnID*/3,
        GIM_CheckComplexPattern, /*MI*/1, /*Op*/2, /*Renderer*/GIMT_Encode2(2), GIMT_Encode2(GICP_gi_vop3mods),
        GIM_CheckComplexPattern, /*MI*/2, /*Op*/1, /*Renderer*/GIMT_Encode2(0), GIMT_Encode2(GICP_gi_vop3mods),
        GIM_CheckComplexPattern, /*MI*/2, /*Op*/2, /*Renderer*/GIMT_Encode2(1), GIMT_Encode2(GICP_gi_vop3mods),
        // (fmaxnum:{ *:[f16] } (fminnum:{ *:[f16] } (fmaxnum_ieee:{ *:[f16] } (VOP3Mods:{ *:[f16] } f16:{ *:[f16] }:$src1, i32:{ *:[i32] }:$src1_mods), (VOP3Mods:{ *:[f16] } f16:{ *:[f16] }:$src0, i32:{ *:[i32] }:$src0_mods)), (VOP3Mods:{ *:[f16] } f16:{ *:[f16] }:$src2, i32:{ *:[i32] }:$src2_mods)), (fminnum:{ *:[f16] } (VOP3Mods:{ *:[f16] } f16:{ *:[f16] }:$src0, i32:{ *:[i32] }:$src0_mods), (VOP3Mods:{ *:[f16] } f16:{ *:[f16] }:$src1, i32:{ *:[i32] }:$src1_mods)))<<P:Predicate_fmaxnum_like_nnan>>  =>  (V_MED3_F16_e64:{ *:[f16] } ?:{ *:[i32] }:$src0_mods, ?:{ *:[f16] }:$src0, ?:{ *:[i32] }:$src1_mods, ?:{ *:[f16] }:$src1, ?:{ *:[i32] }:$src2_mods, ?:{ *:[f16] }:$src2, 0:{ *:[i1] })
        GIR_BuildMI, /*InsnID*/0, /*Opcode*/GIMT_Encode2(AMDGPU::V_MED3_F16_e64),
        GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/0, // DstI[vdst]
        GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(1), /*SubOperand*/1, // src0_mods
        GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(1), /*SubOperand*/0, // src0
        GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/1, // src1_mods
        GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/0, // src1
        GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(2), /*SubOperand*/1, // src2_mods
        GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(2), /*SubOperand*/0, // src2
        GIR_AddImm8, /*InsnID*/0, /*Imm*/0,
        GIR_AddImm8, /*InsnID*/0, /*Imm*/0,
        GIR_AddImm8, /*InsnID*/0, /*Imm*/0,
        GIR_ConstrainSelectedInstOperands, /*InsnID*/0,
        GIR_EraseFromParent, /*InsnID*/0,
        // GIR_Coverage, 10749,
        GIR_Done,
      // Label 4530: @296738
      GIM_Try, /*On fail goto*//*Label 4531*/ GIMT_Encode4(296884), // Rule ID 10750 //
        GIM_CheckFeatures, GIMT_Encode2(GIFBS_isGFX9Plus),
        GIM_CheckRegBankForClass, /*MI*/0, /*Op*/0, /*RC*/GIMT_Encode2(AMDGPU::VGPR_32RegClassID),
        GIM_RecordInsn, /*DefineMI*/1, /*MI*/0, /*OpIdx*/1, // MIs[1]
        GIM_CheckOpcode, /*MI*/1, GIMT_Encode2(TargetOpcode::G_FMINNUM),
        GIM_CheckType, /*MI*/1, /*Op*/1, /*Type*/GILLT_s16,
        GIM_CheckType, /*MI*/1, /*Op*/2, /*Type*/GILLT_s16,
        GIM_RecordInsn, /*DefineMI*/2, /*MI*/1, /*OpIdx*/1, // MIs[2]
        GIM_CheckOpcode, /*MI*/2, GIMT_Encode2(TargetOpcode::G_FMAXNUM_IEEE),
        GIM_CheckType, /*MI*/2, /*Op*/1, /*Type*/GILLT_s16,
        GIM_CheckType, /*MI*/2, /*Op*/2, /*Type*/GILLT_s16,
        GIM_RecordInsn, /*DefineMI*/3, /*MI*/0, /*OpIdx*/2, // MIs[3]
        GIM_CheckOpcode, /*MI*/3, GIMT_Encode2(TargetOpcode::G_FMINNUM),
        // MIs[3] VOP3Mods:src1:src1_mods
        GIM_CheckIsSameOperand, /*MI*/3, /*OpIdx*/1, /*OtherMI*/2, /*OtherOpIdx*/1,
        // MIs[3] VOP3Mods:src0:src0_mods
        GIM_CheckIsSameOperand, /*MI*/3, /*OpIdx*/2, /*OtherMI*/2, /*OtherOpIdx*/2,
        GIM_CheckCxxInsnPredicate, /*MI*/0, /*FnId*/GIMT_Encode2(GICXXPred_MI_Predicate_fmaxnum_like_nnan),
        GIM_CheckIsSafeToFold, /*InsnID*/1,
        GIM_CheckIsSafeToFold, /*InsnID*/2,
        GIM_CheckIsSafeToFold, /*InsnID*/3,
        GIM_CheckComplexPattern, /*MI*/1, /*Op*/2, /*Renderer*/GIMT_Encode2(2), GIMT_Encode2(GICP_gi_vop3mods),
        GIM_CheckComplexPattern, /*MI*/2, /*Op*/1, /*Renderer*/GIMT_Encode2(0), GIMT_Encode2(GICP_gi_vop3mods),
        GIM_CheckComplexPattern, /*MI*/2, /*Op*/2, /*Renderer*/GIMT_Encode2(1), GIMT_Encode2(GICP_gi_vop3mods),
        // (fmaxnum:{ *:[f16] } (fminnum:{ *:[f16] } (fmaxnum_ieee:{ *:[f16] } (VOP3Mods:{ *:[f16] } f16:{ *:[f16] }:$src1, i32:{ *:[i32] }:$src1_mods), (VOP3Mods:{ *:[f16] } f16:{ *:[f16] }:$src0, i32:{ *:[i32] }:$src0_mods)), (VOP3Mods:{ *:[f16] } f16:{ *:[f16] }:$src2, i32:{ *:[i32] }:$src2_mods)), (fminnum:{ *:[f16] } (VOP3Mods:{ *:[f16] } f16:{ *:[f16] }:$src1, i32:{ *:[i32] }:$src1_mods), (VOP3Mods:{ *:[f16] } f16:{ *:[f16] }:$src0, i32:{ *:[i32] }:$src0_mods)))<<P:Predicate_fmaxnum_like_nnan>>  =>  (V_MED3_F16_e64:{ *:[f16] } ?:{ *:[i32] }:$src0_mods, ?:{ *:[f16] }:$src0, ?:{ *:[i32] }:$src1_mods, ?:{ *:[f16] }:$src1, ?:{ *:[i32] }:$src2_mods, ?:{ *:[f16] }:$src2, 0:{ *:[i1] })
        GIR_BuildMI, /*InsnID*/0, /*Opcode*/GIMT_Encode2(AMDGPU::V_MED3_F16_e64),
        GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/0, // DstI[vdst]
        GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(1), /*SubOperand*/1, // src0_mods
        GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(1), /*SubOperand*/0, // src0
        GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/1, // src1_mods
        GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/0, // src1
        GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(2), /*SubOperand*/1, // src2_mods
        GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(2), /*SubOperand*/0, // src2
        GIR_AddImm8, /*InsnID*/0, /*Imm*/0,
        GIR_AddImm8, /*InsnID*/0, /*Imm*/0,
        GIR_AddImm8, /*InsnID*/0, /*Imm*/0,
        GIR_ConstrainSelectedInstOperands, /*InsnID*/0,
        GIR_EraseFromParent, /*InsnID*/0,
        // GIR_Coverage, 10750,
        GIR_Done,
      // Label 4531: @296884
      GIM_Try, /*On fail goto*//*Label 4532*/ GIMT_Encode4(297030), // Rule ID 10687 //
        GIM_CheckFeatures, GIMT_Encode2(GIFBS_isGFX9Plus),
        GIM_CheckRegBankForClass, /*MI*/0, /*Op*/0, /*RC*/GIMT_Encode2(AMDGPU::VGPR_32RegClassID),
        GIM_RecordInsn, /*DefineMI*/1, /*MI*/0, /*OpIdx*/1, // MIs[1]
        GIM_CheckOpcode, /*MI*/1, GIMT_Encode2(TargetOpcode::G_FMINNUM),
        GIM_CheckType, /*MI*/1, /*Op*/1, /*Type*/GILLT_s16,
        GIM_CheckType, /*MI*/1, /*Op*/2, /*Type*/GILLT_s16,
        GIM_RecordInsn, /*DefineMI*/2, /*MI*/1, /*OpIdx*/1, // MIs[2]
        GIM_CheckOpcode, /*MI*/2, GIMT_Encode2(TargetOpcode::G_FMAXNUM_IEEE),
        GIM_CheckType, /*MI*/2, /*Op*/1, /*Type*/GILLT_s16,
        GIM_CheckType, /*MI*/2, /*Op*/2, /*Type*/GILLT_s16,
        GIM_RecordInsn, /*DefineMI*/3, /*MI*/0, /*OpIdx*/2, // MIs[3]
        GIM_CheckOpcode, /*MI*/3, GIMT_Encode2(TargetOpcode::G_FMINNUM_IEEE),
        // MIs[3] VOP3Mods:src0:src0_mods
        GIM_CheckIsSameOperand, /*MI*/3, /*OpIdx*/1, /*OtherMI*/2, /*OtherOpIdx*/1,
        // MIs[3] VOP3Mods:src1:src1_mods
        GIM_CheckIsSameOperand, /*MI*/3, /*OpIdx*/2, /*OtherMI*/2, /*OtherOpIdx*/2,
        GIM_CheckCxxInsnPredicate, /*MI*/0, /*FnId*/GIMT_Encode2(GICXXPred_MI_Predicate_fmaxnum_like_nnan),
        GIM_CheckIsSafeToFold, /*InsnID*/1,
        GIM_CheckIsSafeToFold, /*InsnID*/2,
        GIM_CheckIsSafeToFold, /*InsnID*/3,
        GIM_CheckComplexPattern, /*MI*/1, /*Op*/2, /*Renderer*/GIMT_Encode2(2), GIMT_Encode2(GICP_gi_vop3mods),
        GIM_CheckComplexPattern, /*MI*/2, /*Op*/1, /*Renderer*/GIMT_Encode2(0), GIMT_Encode2(GICP_gi_vop3mods),
        GIM_CheckComplexPattern, /*MI*/2, /*Op*/2, /*Renderer*/GIMT_Encode2(1), GIMT_Encode2(GICP_gi_vop3mods),
        // (fmaxnum:{ *:[f16] } (fminnum:{ *:[f16] } (fmaxnum_ieee:{ *:[f16] } (VOP3Mods:{ *:[f16] } f16:{ *:[f16] }:$src0, i32:{ *:[i32] }:$src0_mods), (VOP3Mods:{ *:[f16] } f16:{ *:[f16] }:$src1, i32:{ *:[i32] }:$src1_mods)), (VOP3Mods:{ *:[f16] } f16:{ *:[f16] }:$src2, i32:{ *:[i32] }:$src2_mods)), (fminnum_ieee:{ *:[f16] } (VOP3Mods:{ *:[f16] } f16:{ *:[f16] }:$src0, i32:{ *:[i32] }:$src0_mods), (VOP3Mods:{ *:[f16] } f16:{ *:[f16] }:$src1, i32:{ *:[i32] }:$src1_mods)))<<P:Predicate_fmaxnum_like_nnan>>  =>  (V_MED3_F16_e64:{ *:[f16] } ?:{ *:[i32] }:$src0_mods, ?:{ *:[f16] }:$src0, ?:{ *:[i32] }:$src1_mods, ?:{ *:[f16] }:$src1, ?:{ *:[i32] }:$src2_mods, ?:{ *:[f16] }:$src2, 0:{ *:[i1] })
        GIR_BuildMI, /*InsnID*/0, /*Opcode*/GIMT_Encode2(AMDGPU::V_MED3_F16_e64),
        GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/0, // DstI[vdst]
        GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/1, // src0_mods
        GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/0, // src0
        GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(1), /*SubOperand*/1, // src1_mods
        GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(1), /*SubOperand*/0, // src1
        GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(2), /*SubOperand*/1, // src2_mods
        GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(2), /*SubOperand*/0, // src2
        GIR_AddImm8, /*InsnID*/0, /*Imm*/0,
        GIR_AddImm8, /*InsnID*/0, /*Imm*/0,
        GIR_AddImm8, /*InsnID*/0, /*Imm*/0,
        GIR_ConstrainSelectedInstOperands, /*InsnID*/0,
        GIR_EraseFromParent, /*InsnID*/0,
        // GIR_Coverage, 10687,
        GIR_Done,
      // Label 4532: @297030
      GIM_Try, /*On fail goto*//*Label 4533*/ GIMT_Encode4(297176), // Rule ID 10688 //
        GIM_CheckFeatures, GIMT_Encode2(GIFBS_isGFX9Plus),
        GIM_CheckRegBankForClass, /*MI*/0, /*Op*/0, /*RC*/GIMT_Encode2(AMDGPU::VGPR_32RegClassID),
        GIM_RecordInsn, /*DefineMI*/1, /*MI*/0, /*OpIdx*/1, // MIs[1]
        GIM_CheckOpcode, /*MI*/1, GIMT_Encode2(TargetOpcode::G_FMINNUM),
        GIM_CheckType, /*MI*/1, /*Op*/1, /*Type*/GILLT_s16,
        GIM_CheckType, /*MI*/1, /*Op*/2, /*Type*/GILLT_s16,
        GIM_RecordInsn, /*DefineMI*/2, /*MI*/1, /*OpIdx*/1, // MIs[2]
        GIM_CheckOpcode, /*MI*/2, GIMT_Encode2(TargetOpcode::G_FMAXNUM_IEEE),
        GIM_CheckType, /*MI*/2, /*Op*/1, /*Type*/GILLT_s16,
        GIM_CheckType, /*MI*/2, /*Op*/2, /*Type*/GILLT_s16,
        GIM_RecordInsn, /*DefineMI*/3, /*MI*/0, /*OpIdx*/2, // MIs[3]
        GIM_CheckOpcode, /*MI*/3, GIMT_Encode2(TargetOpcode::G_FMINNUM_IEEE),
        // MIs[3] VOP3Mods:src1:src1_mods
        GIM_CheckIsSameOperand, /*MI*/3, /*OpIdx*/1, /*OtherMI*/2, /*OtherOpIdx*/2,
        // MIs[3] VOP3Mods:src0:src0_mods
        GIM_CheckIsSameOperand, /*MI*/3, /*OpIdx*/2, /*OtherMI*/2, /*OtherOpIdx*/1,
        GIM_CheckCxxInsnPredicate, /*MI*/0, /*FnId*/GIMT_Encode2(GICXXPred_MI_Predicate_fmaxnum_like_nnan),
        GIM_CheckIsSafeToFold, /*InsnID*/1,
        GIM_CheckIsSafeToFold, /*InsnID*/2,
        GIM_CheckIsSafeToFold, /*InsnID*/3,
        GIM_CheckComplexPattern, /*MI*/1, /*Op*/2, /*Renderer*/GIMT_Encode2(2), GIMT_Encode2(GICP_gi_vop3mods),
        GIM_CheckComplexPattern, /*MI*/2, /*Op*/1, /*Renderer*/GIMT_Encode2(0), GIMT_Encode2(GICP_gi_vop3mods),
        GIM_CheckComplexPattern, /*MI*/2, /*Op*/2, /*Renderer*/GIMT_Encode2(1), GIMT_Encode2(GICP_gi_vop3mods),
        // (fmaxnum:{ *:[f16] } (fminnum:{ *:[f16] } (fmaxnum_ieee:{ *:[f16] } (VOP3Mods:{ *:[f16] } f16:{ *:[f16] }:$src0, i32:{ *:[i32] }:$src0_mods), (VOP3Mods:{ *:[f16] } f16:{ *:[f16] }:$src1, i32:{ *:[i32] }:$src1_mods)), (VOP3Mods:{ *:[f16] } f16:{ *:[f16] }:$src2, i32:{ *:[i32] }:$src2_mods)), (fminnum_ieee:{ *:[f16] } (VOP3Mods:{ *:[f16] } f16:{ *:[f16] }:$src1, i32:{ *:[i32] }:$src1_mods), (VOP3Mods:{ *:[f16] } f16:{ *:[f16] }:$src0, i32:{ *:[i32] }:$src0_mods)))<<P:Predicate_fmaxnum_like_nnan>>  =>  (V_MED3_F16_e64:{ *:[f16] } ?:{ *:[i32] }:$src0_mods, ?:{ *:[f16] }:$src0, ?:{ *:[i32] }:$src1_mods, ?:{ *:[f16] }:$src1, ?:{ *:[i32] }:$src2_mods, ?:{ *:[f16] }:$src2, 0:{ *:[i1] })
        GIR_BuildMI, /*InsnID*/0, /*Opcode*/GIMT_Encode2(AMDGPU::V_MED3_F16_e64),
        GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/0, // DstI[vdst]
        GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/1, // src0_mods
        GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/0, // src0
        GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(1), /*SubOperand*/1, // src1_mods
        GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(1), /*SubOperand*/0, // src1
        GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(2), /*SubOperand*/1, // src2_mods
        GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(2), /*SubOperand*/0, // src2
        GIR_AddImm8, /*InsnID*/0, /*Imm*/0,
        GIR_AddImm8, /*InsnID*/0, /*Imm*/0,
        GIR_AddImm8, /*InsnID*/0, /*Imm*/0,
        GIR_ConstrainSelectedInstOperands, /*InsnID*/0,
        GIR_EraseFromParent, /*InsnID*/0,
        // GIR_Coverage, 10688,
        GIR_Done,
      // Label 4533: @297176
      GIM_Try, /*On fail goto*//*Label 4534*/ GIMT_Encode4(297322), // Rule ID 10689 //
        GIM_CheckFeatures, GIMT_Encode2(GIFBS_isGFX9Plus),
        GIM_CheckRegBankForClass, /*MI*/0, /*Op*/0, /*RC*/GIMT_Encode2(AMDGPU::VGPR_32RegClassID),
        GIM_RecordInsn, /*DefineMI*/1, /*MI*/0, /*OpIdx*/1, // MIs[1]
        GIM_CheckOpcode, /*MI*/1, GIMT_Encode2(TargetOpcode::G_FMINNUM),
        GIM_CheckType, /*MI*/1, /*Op*/1, /*Type*/GILLT_s16,
        GIM_CheckType, /*MI*/1, /*Op*/2, /*Type*/GILLT_s16,
        GIM_RecordInsn, /*DefineMI*/2, /*MI*/1, /*OpIdx*/1, // MIs[2]
        GIM_CheckOpcode, /*MI*/2, GIMT_Encode2(TargetOpcode::G_FMAXNUM_IEEE),
        GIM_CheckType, /*MI*/2, /*Op*/1, /*Type*/GILLT_s16,
        GIM_CheckType, /*MI*/2, /*Op*/2, /*Type*/GILLT_s16,
        GIM_RecordInsn, /*DefineMI*/3, /*MI*/0, /*OpIdx*/2, // MIs[3]
        GIM_CheckOpcode, /*MI*/3, GIMT_Encode2(TargetOpcode::G_FMINNUM_IEEE),
        // MIs[3] VOP3Mods:src0:src0_mods
        GIM_CheckIsSameOperand, /*MI*/3, /*OpIdx*/1, /*OtherMI*/2, /*OtherOpIdx*/2,
        // MIs[3] VOP3Mods:src1:src1_mods
        GIM_CheckIsSameOperand, /*MI*/3, /*OpIdx*/2, /*OtherMI*/2, /*OtherOpIdx*/1,
        GIM_CheckCxxInsnPredicate, /*MI*/0, /*FnId*/GIMT_Encode2(GICXXPred_MI_Predicate_fmaxnum_like_nnan),
        GIM_CheckIsSafeToFold, /*InsnID*/1,
        GIM_CheckIsSafeToFold, /*InsnID*/2,
        GIM_CheckIsSafeToFold, /*InsnID*/3,
        GIM_CheckComplexPattern, /*MI*/1, /*Op*/2, /*Renderer*/GIMT_Encode2(2), GIMT_Encode2(GICP_gi_vop3mods),
        GIM_CheckComplexPattern, /*MI*/2, /*Op*/1, /*Renderer*/GIMT_Encode2(0), GIMT_Encode2(GICP_gi_vop3mods),
        GIM_CheckComplexPattern, /*MI*/2, /*Op*/2, /*Renderer*/GIMT_Encode2(1), GIMT_Encode2(GICP_gi_vop3mods),
        // (fmaxnum:{ *:[f16] } (fminnum:{ *:[f16] } (fmaxnum_ieee:{ *:[f16] } (VOP3Mods:{ *:[f16] } f16:{ *:[f16] }:$src1, i32:{ *:[i32] }:$src1_mods), (VOP3Mods:{ *:[f16] } f16:{ *:[f16] }:$src0, i32:{ *:[i32] }:$src0_mods)), (VOP3Mods:{ *:[f16] } f16:{ *:[f16] }:$src2, i32:{ *:[i32] }:$src2_mods)), (fminnum_ieee:{ *:[f16] } (VOP3Mods:{ *:[f16] } f16:{ *:[f16] }:$src0, i32:{ *:[i32] }:$src0_mods), (VOP3Mods:{ *:[f16] } f16:{ *:[f16] }:$src1, i32:{ *:[i32] }:$src1_mods)))<<P:Predicate_fmaxnum_like_nnan>>  =>  (V_MED3_F16_e64:{ *:[f16] } ?:{ *:[i32] }:$src0_mods, ?:{ *:[f16] }:$src0, ?:{ *:[i32] }:$src1_mods, ?:{ *:[f16] }:$src1, ?:{ *:[i32] }:$src2_mods, ?:{ *:[f16] }:$src2, 0:{ *:[i1] })
        GIR_BuildMI, /*InsnID*/0, /*Opcode*/GIMT_Encode2(AMDGPU::V_MED3_F16_e64),
        GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/0, // DstI[vdst]
        GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(1), /*SubOperand*/1, // src0_mods
        GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(1), /*SubOperand*/0, // src0
        GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/1, // src1_mods
        GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/0, // src1
        GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(2), /*SubOperand*/1, // src2_mods
        GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(2), /*SubOperand*/0, // src2
        GIR_AddImm8, /*InsnID*/0, /*Imm*/0,
        GIR_AddImm8, /*InsnID*/0, /*Imm*/0,
        GIR_AddImm8, /*InsnID*/0, /*Imm*/0,
        GIR_ConstrainSelectedInstOperands, /*InsnID*/0,
        GIR_EraseFromParent, /*InsnID*/0,
        // GIR_Coverage, 10689,
        GIR_Done,
      // Label 4534: @297322
      GIM_Try, /*On fail goto*//*Label 4535*/ GIMT_Encode4(297468), // Rule ID 10690 //
        GIM_CheckFeatures, GIMT_Encode2(GIFBS_isGFX9Plus),
        GIM_CheckRegBankForClass, /*MI*/0, /*Op*/0, /*RC*/GIMT_Encode2(AMDGPU::VGPR_32RegClassID),
        GIM_RecordInsn, /*DefineMI*/1, /*MI*/0, /*OpIdx*/1, // MIs[1]
        GIM_CheckOpcode, /*MI*/1, GIMT_Encode2(TargetOpcode::G_FMINNUM),
        GIM_CheckType, /*MI*/1, /*Op*/1, /*Type*/GILLT_s16,
        GIM_CheckType, /*MI*/1, /*Op*/2, /*Type*/GILLT_s16,
        GIM_RecordInsn, /*DefineMI*/2, /*MI*/1, /*OpIdx*/1, // MIs[2]
        GIM_CheckOpcode, /*MI*/2, GIMT_Encode2(TargetOpcode::G_FMAXNUM_IEEE),
        GIM_CheckType, /*MI*/2, /*Op*/1, /*Type*/GILLT_s16,
        GIM_CheckType, /*MI*/2, /*Op*/2, /*Type*/GILLT_s16,
        GIM_RecordInsn, /*DefineMI*/3, /*MI*/0, /*OpIdx*/2, // MIs[3]
        GIM_CheckOpcode, /*MI*/3, GIMT_Encode2(TargetOpcode::G_FMINNUM_IEEE),
        // MIs[3] VOP3Mods:src1:src1_mods
        GIM_CheckIsSameOperand, /*MI*/3, /*OpIdx*/1, /*OtherMI*/2, /*OtherOpIdx*/1,
        // MIs[3] VOP3Mods:src0:src0_mods
        GIM_CheckIsSameOperand, /*MI*/3, /*OpIdx*/2, /*OtherMI*/2, /*OtherOpIdx*/2,
        GIM_CheckCxxInsnPredicate, /*MI*/0, /*FnId*/GIMT_Encode2(GICXXPred_MI_Predicate_fmaxnum_like_nnan),
        GIM_CheckIsSafeToFold, /*InsnID*/1,
        GIM_CheckIsSafeToFold, /*InsnID*/2,
        GIM_CheckIsSafeToFold, /*InsnID*/3,
        GIM_CheckComplexPattern, /*MI*/1, /*Op*/2, /*Renderer*/GIMT_Encode2(2), GIMT_Encode2(GICP_gi_vop3mods),
        GIM_CheckComplexPattern, /*MI*/2, /*Op*/1, /*Renderer*/GIMT_Encode2(0), GIMT_Encode2(GICP_gi_vop3mods),
        GIM_CheckComplexPattern, /*MI*/2, /*Op*/2, /*Renderer*/GIMT_Encode2(1), GIMT_Encode2(GICP_gi_vop3mods),
        // (fmaxnum:{ *:[f16] } (fminnum:{ *:[f16] } (fmaxnum_ieee:{ *:[f16] } (VOP3Mods:{ *:[f16] } f16:{ *:[f16] }:$src1, i32:{ *:[i32] }:$src1_mods), (VOP3Mods:{ *:[f16] } f16:{ *:[f16] }:$src0, i32:{ *:[i32] }:$src0_mods)), (VOP3Mods:{ *:[f16] } f16:{ *:[f16] }:$src2, i32:{ *:[i32] }:$src2_mods)), (fminnum_ieee:{ *:[f16] } (VOP3Mods:{ *:[f16] } f16:{ *:[f16] }:$src1, i32:{ *:[i32] }:$src1_mods), (VOP3Mods:{ *:[f16] } f16:{ *:[f16] }:$src0, i32:{ *:[i32] }:$src0_mods)))<<P:Predicate_fmaxnum_like_nnan>>  =>  (V_MED3_F16_e64:{ *:[f16] } ?:{ *:[i32] }:$src0_mods, ?:{ *:[f16] }:$src0, ?:{ *:[i32] }:$src1_mods, ?:{ *:[f16] }:$src1, ?:{ *:[i32] }:$src2_mods, ?:{ *:[f16] }:$src2, 0:{ *:[i1] })
        GIR_BuildMI, /*InsnID*/0, /*Opcode*/GIMT_Encode2(AMDGPU::V_MED3_F16_e64),
        GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/0, // DstI[vdst]
        GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(1), /*SubOperand*/1, // src0_mods
        GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(1), /*SubOperand*/0, // src0
        GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/1, // src1_mods
        GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/0, // src1
        GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(2), /*SubOperand*/1, // src2_mods
        GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(2), /*SubOperand*/0, // src2
        GIR_AddImm8, /*InsnID*/0, /*Imm*/0,
        GIR_AddImm8, /*InsnID*/0, /*Imm*/0,
        GIR_AddImm8, /*InsnID*/0, /*Imm*/0,
        GIR_ConstrainSelectedInstOperands, /*InsnID*/0,
        GIR_EraseFromParent, /*InsnID*/0,
        // GIR_Coverage, 10690,
        GIR_Done,
      // Label 4535: @297468
      GIM_Try, /*On fail goto*//*Label 4536*/ GIMT_Encode4(297614), // Rule ID 10696 //
        GIM_CheckFeatures, GIMT_Encode2(GIFBS_isGFX9Plus),
        GIM_CheckRegBankForClass, /*MI*/0, /*Op*/0, /*RC*/GIMT_Encode2(AMDGPU::VGPR_32RegClassID),
        GIM_RecordInsn, /*DefineMI*/1, /*MI*/0, /*OpIdx*/1, // MIs[1]
        GIM_CheckOpcode, /*MI*/1, GIMT_Encode2(TargetOpcode::G_FMINNUM_IEEE),
        GIM_CheckType, /*MI*/1, /*Op*/1, /*Type*/GILLT_s16,
        GIM_CheckType, /*MI*/1, /*Op*/2, /*Type*/GILLT_s16,
        GIM_RecordInsn, /*DefineMI*/2, /*MI*/0, /*OpIdx*/2, // MIs[2]
        GIM_CheckOpcode, /*MI*/2, GIMT_Encode2(TargetOpcode::G_FMINNUM),
        GIM_CheckType, /*MI*/2, /*Op*/1, /*Type*/GILLT_s16,
        GIM_CheckType, /*MI*/2, /*Op*/2, /*Type*/GILLT_s16,
        GIM_RecordInsn, /*DefineMI*/3, /*MI*/2, /*OpIdx*/2, // MIs[3]
        GIM_CheckOpcode, /*MI*/3, GIMT_Encode2(TargetOpcode::G_FMAXNUM),
        // MIs[3] VOP3Mods:src0:src0_mods
        GIM_CheckIsSameOperand, /*MI*/3, /*OpIdx*/1, /*OtherMI*/1, /*OtherOpIdx*/1,
        // MIs[3] VOP3Mods:src1:src1_mods
        GIM_CheckIsSameOperand, /*MI*/3, /*OpIdx*/2, /*OtherMI*/1, /*OtherOpIdx*/2,
        GIM_CheckCxxInsnPredicate, /*MI*/0, /*FnId*/GIMT_Encode2(GICXXPred_MI_Predicate_fmaxnum_like_nnan),
        GIM_CheckIsSafeToFold, /*InsnID*/1,
        GIM_CheckIsSafeToFold, /*InsnID*/2,
        GIM_CheckIsSafeToFold, /*InsnID*/3,
        GIM_CheckComplexPattern, /*MI*/1, /*Op*/1, /*Renderer*/GIMT_Encode2(0), GIMT_Encode2(GICP_gi_vop3mods),
        GIM_CheckComplexPattern, /*MI*/1, /*Op*/2, /*Renderer*/GIMT_Encode2(1), GIMT_Encode2(GICP_gi_vop3mods),
        GIM_CheckComplexPattern, /*MI*/2, /*Op*/1, /*Renderer*/GIMT_Encode2(2), GIMT_Encode2(GICP_gi_vop3mods),
        // (fmaxnum:{ *:[f16] } (fminnum_ieee:{ *:[f16] } (VOP3Mods:{ *:[f16] } f16:{ *:[f16] }:$src0, i32:{ *:[i32] }:$src0_mods), (VOP3Mods:{ *:[f16] } f16:{ *:[f16] }:$src1, i32:{ *:[i32] }:$src1_mods)), (fminnum:{ *:[f16] } (VOP3Mods:{ *:[f16] } f16:{ *:[f16] }:$src2, i32:{ *:[i32] }:$src2_mods), (fmaxnum:{ *:[f16] } (VOP3Mods:{ *:[f16] } f16:{ *:[f16] }:$src0, i32:{ *:[i32] }:$src0_mods), (VOP3Mods:{ *:[f16] } f16:{ *:[f16] }:$src1, i32:{ *:[i32] }:$src1_mods))))<<P:Predicate_fmaxnum_like_nnan>>  =>  (V_MED3_F16_e64:{ *:[f16] } ?:{ *:[i32] }:$src0_mods, ?:{ *:[f16] }:$src0, ?:{ *:[i32] }:$src1_mods, ?:{ *:[f16] }:$src1, ?:{ *:[i32] }:$src2_mods, ?:{ *:[f16] }:$src2, 0:{ *:[i1] })
        GIR_BuildMI, /*InsnID*/0, /*Opcode*/GIMT_Encode2(AMDGPU::V_MED3_F16_e64),
        GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/0, // DstI[vdst]
        GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/1, // src0_mods
        GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/0, // src0
        GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(1), /*SubOperand*/1, // src1_mods
        GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(1), /*SubOperand*/0, // src1
        GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(2), /*SubOperand*/1, // src2_mods
        GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(2), /*SubOperand*/0, // src2
        GIR_AddImm8, /*InsnID*/0, /*Imm*/0,
        GIR_AddImm8, /*InsnID*/0, /*Imm*/0,
        GIR_AddImm8, /*InsnID*/0, /*Imm*/0,
        GIR_ConstrainSelectedInstOperands, /*InsnID*/0,
        GIR_EraseFromParent, /*InsnID*/0,
        // GIR_Coverage, 10696,
        GIR_Done,
      // Label 4536: @297614
      GIM_Try, /*On fail goto*//*Label 4537*/ GIMT_Encode4(297760), // Rule ID 10697 //
        GIM_CheckFeatures, GIMT_Encode2(GIFBS_isGFX9Plus),
        GIM_CheckRegBankForClass, /*MI*/0, /*Op*/0, /*RC*/GIMT_Encode2(AMDGPU::VGPR_32RegClassID),
        GIM_RecordInsn, /*DefineMI*/1, /*MI*/0, /*OpIdx*/1, // MIs[1]
        GIM_CheckOpcode, /*MI*/1, GIMT_Encode2(TargetOpcode::G_FMINNUM_IEEE),
        GIM_CheckType, /*MI*/1, /*Op*/1, /*Type*/GILLT_s16,
        GIM_CheckType, /*MI*/1, /*Op*/2, /*Type*/GILLT_s16,
        GIM_RecordInsn, /*DefineMI*/2, /*MI*/0, /*OpIdx*/2, // MIs[2]
        GIM_CheckOpcode, /*MI*/2, GIMT_Encode2(TargetOpcode::G_FMINNUM),
        GIM_CheckType, /*MI*/2, /*Op*/1, /*Type*/GILLT_s16,
        GIM_CheckType, /*MI*/2, /*Op*/2, /*Type*/GILLT_s16,
        GIM_RecordInsn, /*DefineMI*/3, /*MI*/2, /*OpIdx*/2, // MIs[3]
        GIM_CheckOpcode, /*MI*/3, GIMT_Encode2(TargetOpcode::G_FMAXNUM),
        // MIs[3] VOP3Mods:src1:src1_mods
        GIM_CheckIsSameOperand, /*MI*/3, /*OpIdx*/1, /*OtherMI*/1, /*OtherOpIdx*/2,
        // MIs[3] VOP3Mods:src0:src0_mods
        GIM_CheckIsSameOperand, /*MI*/3, /*OpIdx*/2, /*OtherMI*/1, /*OtherOpIdx*/1,
        GIM_CheckCxxInsnPredicate, /*MI*/0, /*FnId*/GIMT_Encode2(GICXXPred_MI_Predicate_fmaxnum_like_nnan),
        GIM_CheckIsSafeToFold, /*InsnID*/1,
        GIM_CheckIsSafeToFold, /*InsnID*/2,
        GIM_CheckIsSafeToFold, /*InsnID*/3,
        GIM_CheckComplexPattern, /*MI*/1, /*Op*/1, /*Renderer*/GIMT_Encode2(0), GIMT_Encode2(GICP_gi_vop3mods),
        GIM_CheckComplexPattern, /*MI*/1, /*Op*/2, /*Renderer*/GIMT_Encode2(1), GIMT_Encode2(GICP_gi_vop3mods),
        GIM_CheckComplexPattern, /*MI*/2, /*Op*/1, /*Renderer*/GIMT_Encode2(2), GIMT_Encode2(GICP_gi_vop3mods),
        // (fmaxnum:{ *:[f16] } (fminnum_ieee:{ *:[f16] } (VOP3Mods:{ *:[f16] } f16:{ *:[f16] }:$src0, i32:{ *:[i32] }:$src0_mods), (VOP3Mods:{ *:[f16] } f16:{ *:[f16] }:$src1, i32:{ *:[i32] }:$src1_mods)), (fminnum:{ *:[f16] } (VOP3Mods:{ *:[f16] } f16:{ *:[f16] }:$src2, i32:{ *:[i32] }:$src2_mods), (fmaxnum:{ *:[f16] } (VOP3Mods:{ *:[f16] } f16:{ *:[f16] }:$src1, i32:{ *:[i32] }:$src1_mods), (VOP3Mods:{ *:[f16] } f16:{ *:[f16] }:$src0, i32:{ *:[i32] }:$src0_mods))))<<P:Predicate_fmaxnum_like_nnan>>  =>  (V_MED3_F16_e64:{ *:[f16] } ?:{ *:[i32] }:$src0_mods, ?:{ *:[f16] }:$src0, ?:{ *:[i32] }:$src1_mods, ?:{ *:[f16] }:$src1, ?:{ *:[i32] }:$src2_mods, ?:{ *:[f16] }:$src2, 0:{ *:[i1] })
        GIR_BuildMI, /*InsnID*/0, /*Opcode*/GIMT_Encode2(AMDGPU::V_MED3_F16_e64),
        GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/0, // DstI[vdst]
        GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/1, // src0_mods
        GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/0, // src0
        GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(1), /*SubOperand*/1, // src1_mods
        GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(1), /*SubOperand*/0, // src1
        GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(2), /*SubOperand*/1, // src2_mods
        GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(2), /*SubOperand*/0, // src2
        GIR_AddImm8, /*InsnID*/0, /*Imm*/0,
        GIR_AddImm8, /*InsnID*/0, /*Imm*/0,
        GIR_AddImm8, /*InsnID*/0, /*Imm*/0,
        GIR_ConstrainSelectedInstOperands, /*InsnID*/0,
        GIR_EraseFromParent, /*InsnID*/0,
        // GIR_Coverage, 10697,
        GIR_Done,
      // Label 4537: @297760
      GIM_Try, /*On fail goto*//*Label 4538*/ GIMT_Encode4(297906), // Rule ID 10700 //
        GIM_CheckFeatures, GIMT_Encode2(GIFBS_isGFX9Plus),
        GIM_CheckRegBankForClass, /*MI*/0, /*Op*/0, /*RC*/GIMT_Encode2(AMDGPU::VGPR_32RegClassID),
        GIM_RecordInsn, /*DefineMI*/1, /*MI*/0, /*OpIdx*/1, // MIs[1]
        GIM_CheckOpcode, /*MI*/1, GIMT_Encode2(TargetOpcode::G_FMINNUM_IEEE),
        GIM_CheckType, /*MI*/1, /*Op*/1, /*Type*/GILLT_s16,
        GIM_CheckType, /*MI*/1, /*Op*/2, /*Type*/GILLT_s16,
        GIM_RecordInsn, /*DefineMI*/2, /*MI*/0, /*OpIdx*/2, // MIs[2]
        GIM_CheckOpcode, /*MI*/2, GIMT_Encode2(TargetOpcode::G_FMINNUM),
        GIM_CheckType, /*MI*/2, /*Op*/1, /*Type*/GILLT_s16,
        GIM_CheckType, /*MI*/2, /*Op*/2, /*Type*/GILLT_s16,
        GIM_RecordInsn, /*DefineMI*/3, /*MI*/2, /*OpIdx*/2, // MIs[3]
        GIM_CheckOpcode, /*MI*/3, GIMT_Encode2(TargetOpcode::G_FMAXNUM),
        // MIs[3] VOP3Mods:src0:src0_mods
        GIM_CheckIsSameOperand, /*MI*/3, /*OpIdx*/1, /*OtherMI*/1, /*OtherOpIdx*/2,
        // MIs[3] VOP3Mods:src1:src1_mods
        GIM_CheckIsSameOperand, /*MI*/3, /*OpIdx*/2, /*OtherMI*/1, /*OtherOpIdx*/1,
        GIM_CheckCxxInsnPredicate, /*MI*/0, /*FnId*/GIMT_Encode2(GICXXPred_MI_Predicate_fmaxnum_like_nnan),
        GIM_CheckIsSafeToFold, /*InsnID*/1,
        GIM_CheckIsSafeToFold, /*InsnID*/2,
        GIM_CheckIsSafeToFold, /*InsnID*/3,
        GIM_CheckComplexPattern, /*MI*/1, /*Op*/1, /*Renderer*/GIMT_Encode2(0), GIMT_Encode2(GICP_gi_vop3mods),
        GIM_CheckComplexPattern, /*MI*/1, /*Op*/2, /*Renderer*/GIMT_Encode2(1), GIMT_Encode2(GICP_gi_vop3mods),
        GIM_CheckComplexPattern, /*MI*/2, /*Op*/1, /*Renderer*/GIMT_Encode2(2), GIMT_Encode2(GICP_gi_vop3mods),
        // (fmaxnum:{ *:[f16] } (fminnum_ieee:{ *:[f16] } (VOP3Mods:{ *:[f16] } f16:{ *:[f16] }:$src1, i32:{ *:[i32] }:$src1_mods), (VOP3Mods:{ *:[f16] } f16:{ *:[f16] }:$src0, i32:{ *:[i32] }:$src0_mods)), (fminnum:{ *:[f16] } (VOP3Mods:{ *:[f16] } f16:{ *:[f16] }:$src2, i32:{ *:[i32] }:$src2_mods), (fmaxnum:{ *:[f16] } (VOP3Mods:{ *:[f16] } f16:{ *:[f16] }:$src0, i32:{ *:[i32] }:$src0_mods), (VOP3Mods:{ *:[f16] } f16:{ *:[f16] }:$src1, i32:{ *:[i32] }:$src1_mods))))<<P:Predicate_fmaxnum_like_nnan>>  =>  (V_MED3_F16_e64:{ *:[f16] } ?:{ *:[i32] }:$src0_mods, ?:{ *:[f16] }:$src0, ?:{ *:[i32] }:$src1_mods, ?:{ *:[f16] }:$src1, ?:{ *:[i32] }:$src2_mods, ?:{ *:[f16] }:$src2, 0:{ *:[i1] })
        GIR_BuildMI, /*InsnID*/0, /*Opcode*/GIMT_Encode2(AMDGPU::V_MED3_F16_e64),
        GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/0, // DstI[vdst]
        GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(1), /*SubOperand*/1, // src0_mods
        GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(1), /*SubOperand*/0, // src0
        GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/1, // src1_mods
        GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/0, // src1
        GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(2), /*SubOperand*/1, // src2_mods
        GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(2), /*SubOperand*/0, // src2
        GIR_AddImm8, /*InsnID*/0, /*Imm*/0,
        GIR_AddImm8, /*InsnID*/0, /*Imm*/0,
        GIR_AddImm8, /*InsnID*/0, /*Imm*/0,
        GIR_ConstrainSelectedInstOperands, /*InsnID*/0,
        GIR_EraseFromParent, /*InsnID*/0,
        // GIR_Coverage, 10700,
        GIR_Done,
      // Label 4538: @297906
      GIM_Try, /*On fail goto*//*Label 4539*/ GIMT_Encode4(298052), // Rule ID 10701 //
        GIM_CheckFeatures, GIMT_Encode2(GIFBS_isGFX9Plus),
        GIM_CheckRegBankForClass, /*MI*/0, /*Op*/0, /*RC*/GIMT_Encode2(AMDGPU::VGPR_32RegClassID),
        GIM_RecordInsn, /*DefineMI*/1, /*MI*/0, /*OpIdx*/1, // MIs[1]
        GIM_CheckOpcode, /*MI*/1, GIMT_Encode2(TargetOpcode::G_FMINNUM_IEEE),
        GIM_CheckType, /*MI*/1, /*Op*/1, /*Type*/GILLT_s16,
        GIM_CheckType, /*MI*/1, /*Op*/2, /*Type*/GILLT_s16,
        GIM_RecordInsn, /*DefineMI*/2, /*MI*/0, /*OpIdx*/2, // MIs[2]
        GIM_CheckOpcode, /*MI*/2, GIMT_Encode2(TargetOpcode::G_FMINNUM),
        GIM_CheckType, /*MI*/2, /*Op*/1, /*Type*/GILLT_s16,
        GIM_CheckType, /*MI*/2, /*Op*/2, /*Type*/GILLT_s16,
        GIM_RecordInsn, /*DefineMI*/3, /*MI*/2, /*OpIdx*/2, // MIs[3]
        GIM_CheckOpcode, /*MI*/3, GIMT_Encode2(TargetOpcode::G_FMAXNUM),
        // MIs[3] VOP3Mods:src1:src1_mods
        GIM_CheckIsSameOperand, /*MI*/3, /*OpIdx*/1, /*OtherMI*/1, /*OtherOpIdx*/1,
        // MIs[3] VOP3Mods:src0:src0_mods
        GIM_CheckIsSameOperand, /*MI*/3, /*OpIdx*/2, /*OtherMI*/1, /*OtherOpIdx*/2,
        GIM_CheckCxxInsnPredicate, /*MI*/0, /*FnId*/GIMT_Encode2(GICXXPred_MI_Predicate_fmaxnum_like_nnan),
        GIM_CheckIsSafeToFold, /*InsnID*/1,
        GIM_CheckIsSafeToFold, /*InsnID*/2,
        GIM_CheckIsSafeToFold, /*InsnID*/3,
        GIM_CheckComplexPattern, /*MI*/1, /*Op*/1, /*Renderer*/GIMT_Encode2(0), GIMT_Encode2(GICP_gi_vop3mods),
        GIM_CheckComplexPattern, /*MI*/1, /*Op*/2, /*Renderer*/GIMT_Encode2(1), GIMT_Encode2(GICP_gi_vop3mods),
        GIM_CheckComplexPattern, /*MI*/2, /*Op*/1, /*Renderer*/GIMT_Encode2(2), GIMT_Encode2(GICP_gi_vop3mods),
        // (fmaxnum:{ *:[f16] } (fminnum_ieee:{ *:[f16] } (VOP3Mods:{ *:[f16] } f16:{ *:[f16] }:$src1, i32:{ *:[i32] }:$src1_mods), (VOP3Mods:{ *:[f16] } f16:{ *:[f16] }:$src0, i32:{ *:[i32] }:$src0_mods)), (fminnum:{ *:[f16] } (VOP3Mods:{ *:[f16] } f16:{ *:[f16] }:$src2, i32:{ *:[i32] }:$src2_mods), (fmaxnum:{ *:[f16] } (VOP3Mods:{ *:[f16] } f16:{ *:[f16] }:$src1, i32:{ *:[i32] }:$src1_mods), (VOP3Mods:{ *:[f16] } f16:{ *:[f16] }:$src0, i32:{ *:[i32] }:$src0_mods))))<<P:Predicate_fmaxnum_like_nnan>>  =>  (V_MED3_F16_e64:{ *:[f16] } ?:{ *:[i32] }:$src0_mods, ?:{ *:[f16] }:$src0, ?:{ *:[i32] }:$src1_mods, ?:{ *:[f16] }:$src1, ?:{ *:[i32] }:$src2_mods, ?:{ *:[f16] }:$src2, 0:{ *:[i1] })
        GIR_BuildMI, /*InsnID*/0, /*Opcode*/GIMT_Encode2(AMDGPU::V_MED3_F16_e64),
        GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/0, // DstI[vdst]
        GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(1), /*SubOperand*/1, // src0_mods
        GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(1), /*SubOperand*/0, // src0
        GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/1, // src1_mods
        GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/0, // src1
        GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(2), /*SubOperand*/1, // src2_mods
        GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(2), /*SubOperand*/0, // src2
        GIR_AddImm8, /*InsnID*/0, /*Imm*/0,
        GIR_AddImm8, /*InsnID*/0, /*Imm*/0,
        GIR_AddImm8, /*InsnID*/0, /*Imm*/0,
        GIR_ConstrainSelectedInstOperands, /*InsnID*/0,
        GIR_EraseFromParent, /*InsnID*/0,
        // GIR_Coverage, 10701,
        GIR_Done,
      // Label 4539: @298052
      GIM_Try, /*On fail goto*//*Label 4540*/ GIMT_Encode4(298198), // Rule ID 10681 //
        GIM_CheckFeatures, GIMT_Encode2(GIFBS_isGFX9Plus),
        GIM_CheckRegBankForClass, /*MI*/0, /*Op*/0, /*RC*/GIMT_Encode2(AMDGPU::VGPR_32RegClassID),
        GIM_RecordInsn, /*DefineMI*/1, /*MI*/0, /*OpIdx*/1, // MIs[1]
        GIM_CheckOpcode, /*MI*/1, GIMT_Encode2(TargetOpcode::G_FMINNUM_IEEE),
        GIM_CheckType, /*MI*/1, /*Op*/1, /*Type*/GILLT_s16,
        GIM_CheckType, /*MI*/1, /*Op*/2, /*Type*/GILLT_s16,
        GIM_RecordInsn, /*DefineMI*/2, /*MI*/0, /*OpIdx*/2, // MIs[2]
        GIM_CheckOpcode, /*MI*/2, GIMT_Encode2(TargetOpcode::G_FMINNUM),
        GIM_CheckType, /*MI*/2, /*Op*/1, /*Type*/GILLT_s16,
        GIM_CheckType, /*MI*/2, /*Op*/2, /*Type*/GILLT_s16,
        GIM_RecordInsn, /*DefineMI*/3, /*MI*/2, /*OpIdx*/2, // MIs[3]
        GIM_CheckOpcode, /*MI*/3, GIMT_Encode2(TargetOpcode::G_FMAXNUM_IEEE),
        // MIs[3] VOP3Mods:src0:src0_mods
        GIM_CheckIsSameOperand, /*MI*/3, /*OpIdx*/1, /*OtherMI*/1, /*OtherOpIdx*/1,
        // MIs[3] VOP3Mods:src1:src1_mods
        GIM_CheckIsSameOperand, /*MI*/3, /*OpIdx*/2, /*OtherMI*/1, /*OtherOpIdx*/2,
        GIM_CheckCxxInsnPredicate, /*MI*/0, /*FnId*/GIMT_Encode2(GICXXPred_MI_Predicate_fmaxnum_like_nnan),
        GIM_CheckIsSafeToFold, /*InsnID*/1,
        GIM_CheckIsSafeToFold, /*InsnID*/2,
        GIM_CheckIsSafeToFold, /*InsnID*/3,
        GIM_CheckComplexPattern, /*MI*/1, /*Op*/1, /*Renderer*/GIMT_Encode2(0), GIMT_Encode2(GICP_gi_vop3mods),
        GIM_CheckComplexPattern, /*MI*/1, /*Op*/2, /*Renderer*/GIMT_Encode2(1), GIMT_Encode2(GICP_gi_vop3mods),
        GIM_CheckComplexPattern, /*MI*/2, /*Op*/1, /*Renderer*/GIMT_Encode2(2), GIMT_Encode2(GICP_gi_vop3mods),
        // (fmaxnum:{ *:[f16] } (fminnum_ieee:{ *:[f16] } (VOP3Mods:{ *:[f16] } f16:{ *:[f16] }:$src0, i32:{ *:[i32] }:$src0_mods), (VOP3Mods:{ *:[f16] } f16:{ *:[f16] }:$src1, i32:{ *:[i32] }:$src1_mods)), (fminnum:{ *:[f16] } (VOP3Mods:{ *:[f16] } f16:{ *:[f16] }:$src2, i32:{ *:[i32] }:$src2_mods), (fmaxnum_ieee:{ *:[f16] } (VOP3Mods:{ *:[f16] } f16:{ *:[f16] }:$src0, i32:{ *:[i32] }:$src0_mods), (VOP3Mods:{ *:[f16] } f16:{ *:[f16] }:$src1, i32:{ *:[i32] }:$src1_mods))))<<P:Predicate_fmaxnum_like_nnan>>  =>  (V_MED3_F16_e64:{ *:[f16] } ?:{ *:[i32] }:$src0_mods, ?:{ *:[f16] }:$src0, ?:{ *:[i32] }:$src1_mods, ?:{ *:[f16] }:$src1, ?:{ *:[i32] }:$src2_mods, ?:{ *:[f16] }:$src2, 0:{ *:[i1] })
        GIR_BuildMI, /*InsnID*/0, /*Opcode*/GIMT_Encode2(AMDGPU::V_MED3_F16_e64),
        GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/0, // DstI[vdst]
        GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/1, // src0_mods
        GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/0, // src0
        GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(1), /*SubOperand*/1, // src1_mods
        GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(1), /*SubOperand*/0, // src1
        GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(2), /*SubOperand*/1, // src2_mods
        GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(2), /*SubOperand*/0, // src2
        GIR_AddImm8, /*InsnID*/0, /*Imm*/0,
        GIR_AddImm8, /*InsnID*/0, /*Imm*/0,
        GIR_AddImm8, /*InsnID*/0, /*Imm*/0,
        GIR_ConstrainSelectedInstOperands, /*InsnID*/0,
        GIR_EraseFromParent, /*InsnID*/0,
        // GIR_Coverage, 10681,
        GIR_Done,
      // Label 4540: @298198
      GIM_Try, /*On fail goto*//*Label 4541*/ GIMT_Encode4(298344), // Rule ID 10682 //
        GIM_CheckFeatures, GIMT_Encode2(GIFBS_isGFX9Plus),
        GIM_CheckRegBankForClass, /*MI*/0, /*Op*/0, /*RC*/GIMT_Encode2(AMDGPU::VGPR_32RegClassID),
        GIM_RecordInsn, /*DefineMI*/1, /*MI*/0, /*OpIdx*/1, // MIs[1]
        GIM_CheckOpcode, /*MI*/1, GIMT_Encode2(TargetOpcode::G_FMINNUM_IEEE),
        GIM_CheckType, /*MI*/1, /*Op*/1, /*Type*/GILLT_s16,
        GIM_CheckType, /*MI*/1, /*Op*/2, /*Type*/GILLT_s16,
        GIM_RecordInsn, /*DefineMI*/2, /*MI*/0, /*OpIdx*/2, // MIs[2]
        GIM_CheckOpcode, /*MI*/2, GIMT_Encode2(TargetOpcode::G_FMINNUM),
        GIM_CheckType, /*MI*/2, /*Op*/1, /*Type*/GILLT_s16,
        GIM_CheckType, /*MI*/2, /*Op*/2, /*Type*/GILLT_s16,
        GIM_RecordInsn, /*DefineMI*/3, /*MI*/2, /*OpIdx*/2, // MIs[3]
        GIM_CheckOpcode, /*MI*/3, GIMT_Encode2(TargetOpcode::G_FMAXNUM_IEEE),
        // MIs[3] VOP3Mods:src1:src1_mods
        GIM_CheckIsSameOperand, /*MI*/3, /*OpIdx*/1, /*OtherMI*/1, /*OtherOpIdx*/2,
        // MIs[3] VOP3Mods:src0:src0_mods
        GIM_CheckIsSameOperand, /*MI*/3, /*OpIdx*/2, /*OtherMI*/1, /*OtherOpIdx*/1,
        GIM_CheckCxxInsnPredicate, /*MI*/0, /*FnId*/GIMT_Encode2(GICXXPred_MI_Predicate_fmaxnum_like_nnan),
        GIM_CheckIsSafeToFold, /*InsnID*/1,
        GIM_CheckIsSafeToFold, /*InsnID*/2,
        GIM_CheckIsSafeToFold, /*InsnID*/3,
        GIM_CheckComplexPattern, /*MI*/1, /*Op*/1, /*Renderer*/GIMT_Encode2(0), GIMT_Encode2(GICP_gi_vop3mods),
        GIM_CheckComplexPattern, /*MI*/1, /*Op*/2, /*Renderer*/GIMT_Encode2(1), GIMT_Encode2(GICP_gi_vop3mods),
        GIM_CheckComplexPattern, /*MI*/2, /*Op*/1, /*Renderer*/GIMT_Encode2(2), GIMT_Encode2(GICP_gi_vop3mods),
        // (fmaxnum:{ *:[f16] } (fminnum_ieee:{ *:[f16] } (VOP3Mods:{ *:[f16] } f16:{ *:[f16] }:$src0, i32:{ *:[i32] }:$src0_mods), (VOP3Mods:{ *:[f16] } f16:{ *:[f16] }:$src1, i32:{ *:[i32] }:$src1_mods)), (fminnum:{ *:[f16] } (VOP3Mods:{ *:[f16] } f16:{ *:[f16] }:$src2, i32:{ *:[i32] }:$src2_mods), (fmaxnum_ieee:{ *:[f16] } (VOP3Mods:{ *:[f16] } f16:{ *:[f16] }:$src1, i32:{ *:[i32] }:$src1_mods), (VOP3Mods:{ *:[f16] } f16:{ *:[f16] }:$src0, i32:{ *:[i32] }:$src0_mods))))<<P:Predicate_fmaxnum_like_nnan>>  =>  (V_MED3_F16_e64:{ *:[f16] } ?:{ *:[i32] }:$src0_mods, ?:{ *:[f16] }:$src0, ?:{ *:[i32] }:$src1_mods, ?:{ *:[f16] }:$src1, ?:{ *:[i32] }:$src2_mods, ?:{ *:[f16] }:$src2, 0:{ *:[i1] })
        GIR_BuildMI, /*InsnID*/0, /*Opcode*/GIMT_Encode2(AMDGPU::V_MED3_F16_e64),
        GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/0, // DstI[vdst]
        GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/1, // src0_mods
        GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/0, // src0
        GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(1), /*SubOperand*/1, // src1_mods
        GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(1), /*SubOperand*/0, // src1
        GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(2), /*SubOperand*/1, // src2_mods
        GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(2), /*SubOperand*/0, // src2
        GIR_AddImm8, /*InsnID*/0, /*Imm*/0,
        GIR_AddImm8, /*InsnID*/0, /*Imm*/0,
        GIR_AddImm8, /*InsnID*/0, /*Imm*/0,
        GIR_ConstrainSelectedInstOperands, /*InsnID*/0,
        GIR_EraseFromParent, /*InsnID*/0,
        // GIR_Coverage, 10682,
        GIR_Done,
      // Label 4541: @298344
      GIM_Try, /*On fail goto*//*Label 4542*/ GIMT_Encode4(298490), // Rule ID 10685 //
        GIM_CheckFeatures, GIMT_Encode2(GIFBS_isGFX9Plus),
        GIM_CheckRegBankForClass, /*MI*/0, /*Op*/0, /*RC*/GIMT_Encode2(AMDGPU::VGPR_32RegClassID),
        GIM_RecordInsn, /*DefineMI*/1, /*MI*/0, /*OpIdx*/1, // MIs[1]
        GIM_CheckOpcode, /*MI*/1, GIMT_Encode2(TargetOpcode::G_FMINNUM_IEEE),
        GIM_CheckType, /*MI*/1, /*Op*/1, /*Type*/GILLT_s16,
        GIM_CheckType, /*MI*/1, /*Op*/2, /*Type*/GILLT_s16,
        GIM_RecordInsn, /*DefineMI*/2, /*MI*/0, /*OpIdx*/2, // MIs[2]
        GIM_CheckOpcode, /*MI*/2, GIMT_Encode2(TargetOpcode::G_FMINNUM),
        GIM_CheckType, /*MI*/2, /*Op*/1, /*Type*/GILLT_s16,
        GIM_CheckType, /*MI*/2, /*Op*/2, /*Type*/GILLT_s16,
        GIM_RecordInsn, /*DefineMI*/3, /*MI*/2, /*OpIdx*/2, // MIs[3]
        GIM_CheckOpcode, /*MI*/3, GIMT_Encode2(TargetOpcode::G_FMAXNUM_IEEE),
        // MIs[3] VOP3Mods:src0:src0_mods
        GIM_CheckIsSameOperand, /*MI*/3, /*OpIdx*/1, /*OtherMI*/1, /*OtherOpIdx*/2,
        // MIs[3] VOP3Mods:src1:src1_mods
        GIM_CheckIsSameOperand, /*MI*/3, /*OpIdx*/2, /*OtherMI*/1, /*OtherOpIdx*/1,
        GIM_CheckCxxInsnPredicate, /*MI*/0, /*FnId*/GIMT_Encode2(GICXXPred_MI_Predicate_fmaxnum_like_nnan),
        GIM_CheckIsSafeToFold, /*InsnID*/1,
        GIM_CheckIsSafeToFold, /*InsnID*/2,
        GIM_CheckIsSafeToFold, /*InsnID*/3,
        GIM_CheckComplexPattern, /*MI*/1, /*Op*/1, /*Renderer*/GIMT_Encode2(0), GIMT_Encode2(GICP_gi_vop3mods),
        GIM_CheckComplexPattern, /*MI*/1, /*Op*/2, /*Renderer*/GIMT_Encode2(1), GIMT_Encode2(GICP_gi_vop3mods),
        GIM_CheckComplexPattern, /*MI*/2, /*Op*/1, /*Renderer*/GIMT_Encode2(2), GIMT_Encode2(GICP_gi_vop3mods),
        // (fmaxnum:{ *:[f16] } (fminnum_ieee:{ *:[f16] } (VOP3Mods:{ *:[f16] } f16:{ *:[f16] }:$src1, i32:{ *:[i32] }:$src1_mods), (VOP3Mods:{ *:[f16] } f16:{ *:[f16] }:$src0, i32:{ *:[i32] }:$src0_mods)), (fminnum:{ *:[f16] } (VOP3Mods:{ *:[f16] } f16:{ *:[f16] }:$src2, i32:{ *:[i32] }:$src2_mods), (fmaxnum_ieee:{ *:[f16] } (VOP3Mods:{ *:[f16] } f16:{ *:[f16] }:$src0, i32:{ *:[i32] }:$src0_mods), (VOP3Mods:{ *:[f16] } f16:{ *:[f16] }:$src1, i32:{ *:[i32] }:$src1_mods))))<<P:Predicate_fmaxnum_like_nnan>>  =>  (V_MED3_F16_e64:{ *:[f16] } ?:{ *:[i32] }:$src0_mods, ?:{ *:[f16] }:$src0, ?:{ *:[i32] }:$src1_mods, ?:{ *:[f16] }:$src1, ?:{ *:[i32] }:$src2_mods, ?:{ *:[f16] }:$src2, 0:{ *:[i1] })
        GIR_BuildMI, /*InsnID*/0, /*Opcode*/GIMT_Encode2(AMDGPU::V_MED3_F16_e64),
        GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/0, // DstI[vdst]
        GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(1), /*SubOperand*/1, // src0_mods
        GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(1), /*SubOperand*/0, // src0
        GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/1, // src1_mods
        GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/0, // src1
        GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(2), /*SubOperand*/1, // src2_mods
        GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(2), /*SubOperand*/0, // src2
        GIR_AddImm8, /*InsnID*/0, /*Imm*/0,
        GIR_AddImm8, /*InsnID*/0, /*Imm*/0,
        GIR_AddImm8, /*InsnID*/0, /*Imm*/0,
        GIR_ConstrainSelectedInstOperands, /*InsnID*/0,
        GIR_EraseFromParent, /*InsnID*/0,
        // GIR_Coverage, 10685,
        GIR_Done,
      // Label 4542: @298490
      GIM_Try, /*On fail goto*//*Label 4543*/ GIMT_Encode4(298636), // Rule ID 10686 //
        GIM_CheckFeatures, GIMT_Encode2(GIFBS_isGFX9Plus),
        GIM_CheckRegBankForClass, /*MI*/0, /*Op*/0, /*RC*/GIMT_Encode2(AMDGPU::VGPR_32RegClassID),
        GIM_RecordInsn, /*DefineMI*/1, /*MI*/0, /*OpIdx*/1, // MIs[1]
        GIM_CheckOpcode, /*MI*/1, GIMT_Encode2(TargetOpcode::G_FMINNUM_IEEE),
        GIM_CheckType, /*MI*/1, /*Op*/1, /*Type*/GILLT_s16,
        GIM_CheckType, /*MI*/1, /*Op*/2, /*Type*/GILLT_s16,
        GIM_RecordInsn, /*DefineMI*/2, /*MI*/0, /*OpIdx*/2, // MIs[2]
        GIM_CheckOpcode, /*MI*/2, GIMT_Encode2(TargetOpcode::G_FMINNUM),
        GIM_CheckType, /*MI*/2, /*Op*/1, /*Type*/GILLT_s16,
        GIM_CheckType, /*MI*/2, /*Op*/2, /*Type*/GILLT_s16,
        GIM_RecordInsn, /*DefineMI*/3, /*MI*/2, /*OpIdx*/2, // MIs[3]
        GIM_CheckOpcode, /*MI*/3, GIMT_Encode2(TargetOpcode::G_FMAXNUM_IEEE),
        // MIs[3] VOP3Mods:src1:src1_mods
        GIM_CheckIsSameOperand, /*MI*/3, /*OpIdx*/1, /*OtherMI*/1, /*OtherOpIdx*/1,
        // MIs[3] VOP3Mods:src0:src0_mods
        GIM_CheckIsSameOperand, /*MI*/3, /*OpIdx*/2, /*OtherMI*/1, /*OtherOpIdx*/2,
        GIM_CheckCxxInsnPredicate, /*MI*/0, /*FnId*/GIMT_Encode2(GICXXPred_MI_Predicate_fmaxnum_like_nnan),
        GIM_CheckIsSafeToFold, /*InsnID*/1,
        GIM_CheckIsSafeToFold, /*InsnID*/2,
        GIM_CheckIsSafeToFold, /*InsnID*/3,
        GIM_CheckComplexPattern, /*MI*/1, /*Op*/1, /*Renderer*/GIMT_Encode2(0), GIMT_Encode2(GICP_gi_vop3mods),
        GIM_CheckComplexPattern, /*MI*/1, /*Op*/2, /*Renderer*/GIMT_Encode2(1), GIMT_Encode2(GICP_gi_vop3mods),
        GIM_CheckComplexPattern, /*MI*/2, /*Op*/1, /*Renderer*/GIMT_Encode2(2), GIMT_Encode2(GICP_gi_vop3mods),
        // (fmaxnum:{ *:[f16] } (fminnum_ieee:{ *:[f16] } (VOP3Mods:{ *:[f16] } f16:{ *:[f16] }:$src1, i32:{ *:[i32] }:$src1_mods), (VOP3Mods:{ *:[f16] } f16:{ *:[f16] }:$src0, i32:{ *:[i32] }:$src0_mods)), (fminnum:{ *:[f16] } (VOP3Mods:{ *:[f16] } f16:{ *:[f16] }:$src2, i32:{ *:[i32] }:$src2_mods), (fmaxnum_ieee:{ *:[f16] } (VOP3Mods:{ *:[f16] } f16:{ *:[f16] }:$src1, i32:{ *:[i32] }:$src1_mods), (VOP3Mods:{ *:[f16] } f16:{ *:[f16] }:$src0, i32:{ *:[i32] }:$src0_mods))))<<P:Predicate_fmaxnum_like_nnan>>  =>  (V_MED3_F16_e64:{ *:[f16] } ?:{ *:[i32] }:$src0_mods, ?:{ *:[f16] }:$src0, ?:{ *:[i32] }:$src1_mods, ?:{ *:[f16] }:$src1, ?:{ *:[i32] }:$src2_mods, ?:{ *:[f16] }:$src2, 0:{ *:[i1] })
        GIR_BuildMI, /*InsnID*/0, /*Opcode*/GIMT_Encode2(AMDGPU::V_MED3_F16_e64),
        GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/0, // DstI[vdst]
        GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(1), /*SubOperand*/1, // src0_mods
        GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(1), /*SubOperand*/0, // src0
        GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/1, // src1_mods
        GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/0, // src1
        GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(2), /*SubOperand*/1, // src2_mods
        GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(2), /*SubOperand*/0, // src2
        GIR_AddImm8, /*InsnID*/0, /*Imm*/0,
        GIR_AddImm8, /*InsnID*/0, /*Imm*/0,
        GIR_AddImm8, /*InsnID*/0, /*Imm*/0,
        GIR_ConstrainSelectedInstOperands, /*InsnID*/0,
        GIR_EraseFromParent, /*InsnID*/0,
        // GIR_Coverage, 10686,
        GIR_Done,
      // Label 4543: @298636
      GIM_Try, /*On fail goto*//*Label 4544*/ GIMT_Encode4(298782), // Rule ID 6547 //
        GIM_CheckFeatures, GIMT_Encode2(GIFBS_isGFX9Plus),
        GIM_CheckRegBankForClass, /*MI*/0, /*Op*/0, /*RC*/GIMT_Encode2(AMDGPU::VGPR_32RegClassID),
        GIM_RecordInsn, /*DefineMI*/1, /*MI*/0, /*OpIdx*/1, // MIs[1]
        GIM_CheckOpcode, /*MI*/1, GIMT_Encode2(TargetOpcode::G_FMINNUM_IEEE),
        GIM_CheckType, /*MI*/1, /*Op*/1, /*Type*/GILLT_s16,
        GIM_CheckType, /*MI*/1, /*Op*/2, /*Type*/GILLT_s16,
        GIM_RecordInsn, /*DefineMI*/2, /*MI*/0, /*OpIdx*/2, // MIs[2]
        GIM_CheckOpcode, /*MI*/2, GIMT_Encode2(TargetOpcode::G_FMINNUM),
        GIM_CheckType, /*MI*/2, /*Op*/1, /*Type*/GILLT_s16,
        GIM_CheckType, /*MI*/2, /*Op*/2, /*Type*/GILLT_s16,
        GIM_RecordInsn, /*DefineMI*/3, /*MI*/2, /*OpIdx*/1, // MIs[3]
        GIM_CheckOpcode, /*MI*/3, GIMT_Encode2(TargetOpcode::G_FMAXNUM),
        // MIs[3] VOP3Mods:src0:src0_mods
        GIM_CheckIsSameOperand, /*MI*/3, /*OpIdx*/1, /*OtherMI*/1, /*OtherOpIdx*/1,
        // MIs[3] VOP3Mods:src1:src1_mods
        GIM_CheckIsSameOperand, /*MI*/3, /*OpIdx*/2, /*OtherMI*/1, /*OtherOpIdx*/2,
        GIM_CheckCxxInsnPredicate, /*MI*/0, /*FnId*/GIMT_Encode2(GICXXPred_MI_Predicate_fmaxnum_like_nnan),
        GIM_CheckIsSafeToFold, /*InsnID*/1,
        GIM_CheckIsSafeToFold, /*InsnID*/2,
        GIM_CheckIsSafeToFold, /*InsnID*/3,
        GIM_CheckComplexPattern, /*MI*/1, /*Op*/1, /*Renderer*/GIMT_Encode2(0), GIMT_Encode2(GICP_gi_vop3mods),
        GIM_CheckComplexPattern, /*MI*/1, /*Op*/2, /*Renderer*/GIMT_Encode2(1), GIMT_Encode2(GICP_gi_vop3mods),
        GIM_CheckComplexPattern, /*MI*/2, /*Op*/2, /*Renderer*/GIMT_Encode2(2), GIMT_Encode2(GICP_gi_vop3mods),
        // (fmaxnum:{ *:[f16] } (fminnum_ieee:{ *:[f16] } (VOP3Mods:{ *:[f16] } f16:{ *:[f16] }:$src0, i32:{ *:[i32] }:$src0_mods), (VOP3Mods:{ *:[f16] } f16:{ *:[f16] }:$src1, i32:{ *:[i32] }:$src1_mods)), (fminnum:{ *:[f16] } (fmaxnum:{ *:[f16] } (VOP3Mods:{ *:[f16] } f16:{ *:[f16] }:$src0, i32:{ *:[i32] }:$src0_mods), (VOP3Mods:{ *:[f16] } f16:{ *:[f16] }:$src1, i32:{ *:[i32] }:$src1_mods)), (VOP3Mods:{ *:[f16] } f16:{ *:[f16] }:$src2, i32:{ *:[i32] }:$src2_mods)))<<P:Predicate_fmaxnum_like_nnan>>  =>  (V_MED3_F16_e64:{ *:[f16] } ?:{ *:[i32] }:$src0_mods, ?:{ *:[f16] }:$src0, ?:{ *:[i32] }:$src1_mods, ?:{ *:[f16] }:$src1, ?:{ *:[i32] }:$src2_mods, ?:{ *:[f16] }:$src2, 0:{ *:[i1] })
        GIR_BuildMI, /*InsnID*/0, /*Opcode*/GIMT_Encode2(AMDGPU::V_MED3_F16_e64),
        GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/0, // DstI[vdst]
        GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/1, // src0_mods
        GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/0, // src0
        GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(1), /*SubOperand*/1, // src1_mods
        GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(1), /*SubOperand*/0, // src1
        GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(2), /*SubOperand*/1, // src2_mods
        GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(2), /*SubOperand*/0, // src2
        GIR_AddImm8, /*InsnID*/0, /*Imm*/0,
        GIR_AddImm8, /*InsnID*/0, /*Imm*/0,
        GIR_AddImm8, /*InsnID*/0, /*Imm*/0,
        GIR_ConstrainSelectedInstOperands, /*InsnID*/0,
        GIR_EraseFromParent, /*InsnID*/0,
        // GIR_Coverage, 6547,
        GIR_Done,
      // Label 4544: @298782
      GIM_Try, /*On fail goto*//*Label 4545*/ GIMT_Encode4(298928), // Rule ID 10695 //
        GIM_CheckFeatures, GIMT_Encode2(GIFBS_isGFX9Plus),
        GIM_CheckRegBankForClass, /*MI*/0, /*Op*/0, /*RC*/GIMT_Encode2(AMDGPU::VGPR_32RegClassID),
        GIM_RecordInsn, /*DefineMI*/1, /*MI*/0, /*OpIdx*/1, // MIs[1]
        GIM_CheckOpcode, /*MI*/1, GIMT_Encode2(TargetOpcode::G_FMINNUM_IEEE),
        GIM_CheckType, /*MI*/1, /*Op*/1, /*Type*/GILLT_s16,
        GIM_CheckType, /*MI*/1, /*Op*/2, /*Type*/GILLT_s16,
        GIM_RecordInsn, /*DefineMI*/2, /*MI*/0, /*OpIdx*/2, // MIs[2]
        GIM_CheckOpcode, /*MI*/2, GIMT_Encode2(TargetOpcode::G_FMINNUM),
        GIM_CheckType, /*MI*/2, /*Op*/1, /*Type*/GILLT_s16,
        GIM_CheckType, /*MI*/2, /*Op*/2, /*Type*/GILLT_s16,
        GIM_RecordInsn, /*DefineMI*/3, /*MI*/2, /*OpIdx*/1, // MIs[3]
        GIM_CheckOpcode, /*MI*/3, GIMT_Encode2(TargetOpcode::G_FMAXNUM),
        // MIs[3] VOP3Mods:src1:src1_mods
        GIM_CheckIsSameOperand, /*MI*/3, /*OpIdx*/1, /*OtherMI*/1, /*OtherOpIdx*/2,
        // MIs[3] VOP3Mods:src0:src0_mods
        GIM_CheckIsSameOperand, /*MI*/3, /*OpIdx*/2, /*OtherMI*/1, /*OtherOpIdx*/1,
        GIM_CheckCxxInsnPredicate, /*MI*/0, /*FnId*/GIMT_Encode2(GICXXPred_MI_Predicate_fmaxnum_like_nnan),
        GIM_CheckIsSafeToFold, /*InsnID*/1,
        GIM_CheckIsSafeToFold, /*InsnID*/2,
        GIM_CheckIsSafeToFold, /*InsnID*/3,
        GIM_CheckComplexPattern, /*MI*/1, /*Op*/1, /*Renderer*/GIMT_Encode2(0), GIMT_Encode2(GICP_gi_vop3mods),
        GIM_CheckComplexPattern, /*MI*/1, /*Op*/2, /*Renderer*/GIMT_Encode2(1), GIMT_Encode2(GICP_gi_vop3mods),
        GIM_CheckComplexPattern, /*MI*/2, /*Op*/2, /*Renderer*/GIMT_Encode2(2), GIMT_Encode2(GICP_gi_vop3mods),
        // (fmaxnum:{ *:[f16] } (fminnum_ieee:{ *:[f16] } (VOP3Mods:{ *:[f16] } f16:{ *:[f16] }:$src0, i32:{ *:[i32] }:$src0_mods), (VOP3Mods:{ *:[f16] } f16:{ *:[f16] }:$src1, i32:{ *:[i32] }:$src1_mods)), (fminnum:{ *:[f16] } (fmaxnum:{ *:[f16] } (VOP3Mods:{ *:[f16] } f16:{ *:[f16] }:$src1, i32:{ *:[i32] }:$src1_mods), (VOP3Mods:{ *:[f16] } f16:{ *:[f16] }:$src0, i32:{ *:[i32] }:$src0_mods)), (VOP3Mods:{ *:[f16] } f16:{ *:[f16] }:$src2, i32:{ *:[i32] }:$src2_mods)))<<P:Predicate_fmaxnum_like_nnan>>  =>  (V_MED3_F16_e64:{ *:[f16] } ?:{ *:[i32] }:$src0_mods, ?:{ *:[f16] }:$src0, ?:{ *:[i32] }:$src1_mods, ?:{ *:[f16] }:$src1, ?:{ *:[i32] }:$src2_mods, ?:{ *:[f16] }:$src2, 0:{ *:[i1] })
        GIR_BuildMI, /*InsnID*/0, /*Opcode*/GIMT_Encode2(AMDGPU::V_MED3_F16_e64),
        GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/0, // DstI[vdst]
        GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/1, // src0_mods
        GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/0, // src0
        GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(1), /*SubOperand*/1, // src1_mods
        GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(1), /*SubOperand*/0, // src1
        GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(2), /*SubOperand*/1, // src2_mods
        GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(2), /*SubOperand*/0, // src2
        GIR_AddImm8, /*InsnID*/0, /*Imm*/0,
        GIR_AddImm8, /*InsnID*/0, /*Imm*/0,
        GIR_AddImm8, /*InsnID*/0, /*Imm*/0,
        GIR_ConstrainSelectedInstOperands, /*InsnID*/0,
        GIR_EraseFromParent, /*InsnID*/0,
        // GIR_Coverage, 10695,
        GIR_Done,
      // Label 4545: @298928
      GIM_Try, /*On fail goto*//*Label 4546*/ GIMT_Encode4(299074), // Rule ID 10698 //
        GIM_CheckFeatures, GIMT_Encode2(GIFBS_isGFX9Plus),
        GIM_CheckRegBankForClass, /*MI*/0, /*Op*/0, /*RC*/GIMT_Encode2(AMDGPU::VGPR_32RegClassID),
        GIM_RecordInsn, /*DefineMI*/1, /*MI*/0, /*OpIdx*/1, // MIs[1]
        GIM_CheckOpcode, /*MI*/1, GIMT_Encode2(TargetOpcode::G_FMINNUM_IEEE),
        GIM_CheckType, /*MI*/1, /*Op*/1, /*Type*/GILLT_s16,
        GIM_CheckType, /*MI*/1, /*Op*/2, /*Type*/GILLT_s16,
        GIM_RecordInsn, /*DefineMI*/2, /*MI*/0, /*OpIdx*/2, // MIs[2]
        GIM_CheckOpcode, /*MI*/2, GIMT_Encode2(TargetOpcode::G_FMINNUM),
        GIM_CheckType, /*MI*/2, /*Op*/1, /*Type*/GILLT_s16,
        GIM_CheckType, /*MI*/2, /*Op*/2, /*Type*/GILLT_s16,
        GIM_RecordInsn, /*DefineMI*/3, /*MI*/2, /*OpIdx*/1, // MIs[3]
        GIM_CheckOpcode, /*MI*/3, GIMT_Encode2(TargetOpcode::G_FMAXNUM),
        // MIs[3] VOP3Mods:src0:src0_mods
        GIM_CheckIsSameOperand, /*MI*/3, /*OpIdx*/1, /*OtherMI*/1, /*OtherOpIdx*/2,
        // MIs[3] VOP3Mods:src1:src1_mods
        GIM_CheckIsSameOperand, /*MI*/3, /*OpIdx*/2, /*OtherMI*/1, /*OtherOpIdx*/1,
        GIM_CheckCxxInsnPredicate, /*MI*/0, /*FnId*/GIMT_Encode2(GICXXPred_MI_Predicate_fmaxnum_like_nnan),
        GIM_CheckIsSafeToFold, /*InsnID*/1,
        GIM_CheckIsSafeToFold, /*InsnID*/2,
        GIM_CheckIsSafeToFold, /*InsnID*/3,
        GIM_CheckComplexPattern, /*MI*/1, /*Op*/1, /*Renderer*/GIMT_Encode2(0), GIMT_Encode2(GICP_gi_vop3mods),
        GIM_CheckComplexPattern, /*MI*/1, /*Op*/2, /*Renderer*/GIMT_Encode2(1), GIMT_Encode2(GICP_gi_vop3mods),
        GIM_CheckComplexPattern, /*MI*/2, /*Op*/2, /*Renderer*/GIMT_Encode2(2), GIMT_Encode2(GICP_gi_vop3mods),
        // (fmaxnum:{ *:[f16] } (fminnum_ieee:{ *:[f16] } (VOP3Mods:{ *:[f16] } f16:{ *:[f16] }:$src1, i32:{ *:[i32] }:$src1_mods), (VOP3Mods:{ *:[f16] } f16:{ *:[f16] }:$src0, i32:{ *:[i32] }:$src0_mods)), (fminnum:{ *:[f16] } (fmaxnum:{ *:[f16] } (VOP3Mods:{ *:[f16] } f16:{ *:[f16] }:$src0, i32:{ *:[i32] }:$src0_mods), (VOP3Mods:{ *:[f16] } f16:{ *:[f16] }:$src1, i32:{ *:[i32] }:$src1_mods)), (VOP3Mods:{ *:[f16] } f16:{ *:[f16] }:$src2, i32:{ *:[i32] }:$src2_mods)))<<P:Predicate_fmaxnum_like_nnan>>  =>  (V_MED3_F16_e64:{ *:[f16] } ?:{ *:[i32] }:$src0_mods, ?:{ *:[f16] }:$src0, ?:{ *:[i32] }:$src1_mods, ?:{ *:[f16] }:$src1, ?:{ *:[i32] }:$src2_mods, ?:{ *:[f16] }:$src2, 0:{ *:[i1] })
        GIR_BuildMI, /*InsnID*/0, /*Opcode*/GIMT_Encode2(AMDGPU::V_MED3_F16_e64),
        GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/0, // DstI[vdst]
        GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(1), /*SubOperand*/1, // src0_mods
        GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(1), /*SubOperand*/0, // src0
        GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/1, // src1_mods
        GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/0, // src1
        GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(2), /*SubOperand*/1, // src2_mods
        GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(2), /*SubOperand*/0, // src2
        GIR_AddImm8, /*InsnID*/0, /*Imm*/0,
        GIR_AddImm8, /*InsnID*/0, /*Imm*/0,
        GIR_AddImm8, /*InsnID*/0, /*Imm*/0,
        GIR_ConstrainSelectedInstOperands, /*InsnID*/0,
        GIR_EraseFromParent, /*InsnID*/0,
        // GIR_Coverage, 10698,
        GIR_Done,
      // Label 4546: @299074
      GIM_Try, /*On fail goto*//*Label 4547*/ GIMT_Encode4(299220), // Rule ID 10699 //
        GIM_CheckFeatures, GIMT_Encode2(GIFBS_isGFX9Plus),
        GIM_CheckRegBankForClass, /*MI*/0, /*Op*/0, /*RC*/GIMT_Encode2(AMDGPU::VGPR_32RegClassID),
        GIM_RecordInsn, /*DefineMI*/1, /*MI*/0, /*OpIdx*/1, // MIs[1]
        GIM_CheckOpcode, /*MI*/1, GIMT_Encode2(TargetOpcode::G_FMINNUM_IEEE),
        GIM_CheckType, /*MI*/1, /*Op*/1, /*Type*/GILLT_s16,
        GIM_CheckType, /*MI*/1, /*Op*/2, /*Type*/GILLT_s16,
        GIM_RecordInsn, /*DefineMI*/2, /*MI*/0, /*OpIdx*/2, // MIs[2]
        GIM_CheckOpcode, /*MI*/2, GIMT_Encode2(TargetOpcode::G_FMINNUM),
        GIM_CheckType, /*MI*/2, /*Op*/1, /*Type*/GILLT_s16,
        GIM_CheckType, /*MI*/2, /*Op*/2, /*Type*/GILLT_s16,
        GIM_RecordInsn, /*DefineMI*/3, /*MI*/2, /*OpIdx*/1, // MIs[3]
        GIM_CheckOpcode, /*MI*/3, GIMT_Encode2(TargetOpcode::G_FMAXNUM),
        // MIs[3] VOP3Mods:src1:src1_mods
        GIM_CheckIsSameOperand, /*MI*/3, /*OpIdx*/1, /*OtherMI*/1, /*OtherOpIdx*/1,
        // MIs[3] VOP3Mods:src0:src0_mods
        GIM_CheckIsSameOperand, /*MI*/3, /*OpIdx*/2, /*OtherMI*/1, /*OtherOpIdx*/2,
        GIM_CheckCxxInsnPredicate, /*MI*/0, /*FnId*/GIMT_Encode2(GICXXPred_MI_Predicate_fmaxnum_like_nnan),
        GIM_CheckIsSafeToFold, /*InsnID*/1,
        GIM_CheckIsSafeToFold, /*InsnID*/2,
        GIM_CheckIsSafeToFold, /*InsnID*/3,
        GIM_CheckComplexPattern, /*MI*/1, /*Op*/1, /*Renderer*/GIMT_Encode2(0), GIMT_Encode2(GICP_gi_vop3mods),
        GIM_CheckComplexPattern, /*MI*/1, /*Op*/2, /*Renderer*/GIMT_Encode2(1), GIMT_Encode2(GICP_gi_vop3mods),
        GIM_CheckComplexPattern, /*MI*/2, /*Op*/2, /*Renderer*/GIMT_Encode2(2), GIMT_Encode2(GICP_gi_vop3mods),
        // (fmaxnum:{ *:[f16] } (fminnum_ieee:{ *:[f16] } (VOP3Mods:{ *:[f16] } f16:{ *:[f16] }:$src1, i32:{ *:[i32] }:$src1_mods), (VOP3Mods:{ *:[f16] } f16:{ *:[f16] }:$src0, i32:{ *:[i32] }:$src0_mods)), (fminnum:{ *:[f16] } (fmaxnum:{ *:[f16] } (VOP3Mods:{ *:[f16] } f16:{ *:[f16] }:$src1, i32:{ *:[i32] }:$src1_mods), (VOP3Mods:{ *:[f16] } f16:{ *:[f16] }:$src0, i32:{ *:[i32] }:$src0_mods)), (VOP3Mods:{ *:[f16] } f16:{ *:[f16] }:$src2, i32:{ *:[i32] }:$src2_mods)))<<P:Predicate_fmaxnum_like_nnan>>  =>  (V_MED3_F16_e64:{ *:[f16] } ?:{ *:[i32] }:$src0_mods, ?:{ *:[f16] }:$src0, ?:{ *:[i32] }:$src1_mods, ?:{ *:[f16] }:$src1, ?:{ *:[i32] }:$src2_mods, ?:{ *:[f16] }:$src2, 0:{ *:[i1] })
        GIR_BuildMI, /*InsnID*/0, /*Opcode*/GIMT_Encode2(AMDGPU::V_MED3_F16_e64),
        GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/0, // DstI[vdst]
        GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(1), /*SubOperand*/1, // src0_mods
        GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(1), /*SubOperand*/0, // src0
        GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/1, // src1_mods
        GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/0, // src1
        GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(2), /*SubOperand*/1, // src2_mods
        GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(2), /*SubOperand*/0, // src2
        GIR_AddImm8, /*InsnID*/0, /*Imm*/0,
        GIR_AddImm8, /*InsnID*/0, /*Imm*/0,
        GIR_AddImm8, /*InsnID*/0, /*Imm*/0,
        GIR_ConstrainSelectedInstOperands, /*InsnID*/0,
        GIR_EraseFromParent, /*InsnID*/0,
        // GIR_Coverage, 10699,
        GIR_Done,
      // Label 4547: @299220
      GIM_Try, /*On fail goto*//*Label 4548*/ GIMT_Encode4(299366), // Rule ID 6546 //
        GIM_CheckFeatures, GIMT_Encode2(GIFBS_isGFX9Plus),
        GIM_CheckRegBankForClass, /*MI*/0, /*Op*/0, /*RC*/GIMT_Encode2(AMDGPU::VGPR_32RegClassID),
        GIM_RecordInsn, /*DefineMI*/1, /*MI*/0, /*OpIdx*/1, // MIs[1]
        GIM_CheckOpcode, /*MI*/1, GIMT_Encode2(TargetOpcode::G_FMINNUM_IEEE),
        GIM_CheckType, /*MI*/1, /*Op*/1, /*Type*/GILLT_s16,
        GIM_CheckType, /*MI*/1, /*Op*/2, /*Type*/GILLT_s16,
        GIM_RecordInsn, /*DefineMI*/2, /*MI*/0, /*OpIdx*/2, // MIs[2]
        GIM_CheckOpcode, /*MI*/2, GIMT_Encode2(TargetOpcode::G_FMINNUM),
        GIM_CheckType, /*MI*/2, /*Op*/1, /*Type*/GILLT_s16,
        GIM_CheckType, /*MI*/2, /*Op*/2, /*Type*/GILLT_s16,
        GIM_RecordInsn, /*DefineMI*/3, /*MI*/2, /*OpIdx*/1, // MIs[3]
        GIM_CheckOpcode, /*MI*/3, GIMT_Encode2(TargetOpcode::G_FMAXNUM_IEEE),
        // MIs[3] VOP3Mods:src0:src0_mods
        GIM_CheckIsSameOperand, /*MI*/3, /*OpIdx*/1, /*OtherMI*/1, /*OtherOpIdx*/1,
        // MIs[3] VOP3Mods:src1:src1_mods
        GIM_CheckIsSameOperand, /*MI*/3, /*OpIdx*/2, /*OtherMI*/1, /*OtherOpIdx*/2,
        GIM_CheckCxxInsnPredicate, /*MI*/0, /*FnId*/GIMT_Encode2(GICXXPred_MI_Predicate_fmaxnum_like_nnan),
        GIM_CheckIsSafeToFold, /*InsnID*/1,
        GIM_CheckIsSafeToFold, /*InsnID*/2,
        GIM_CheckIsSafeToFold, /*InsnID*/3,
        GIM_CheckComplexPattern, /*MI*/1, /*Op*/1, /*Renderer*/GIMT_Encode2(0), GIMT_Encode2(GICP_gi_vop3mods),
        GIM_CheckComplexPattern, /*MI*/1, /*Op*/2, /*Renderer*/GIMT_Encode2(1), GIMT_Encode2(GICP_gi_vop3mods),
        GIM_CheckComplexPattern, /*MI*/2, /*Op*/2, /*Renderer*/GIMT_Encode2(2), GIMT_Encode2(GICP_gi_vop3mods),
        // (fmaxnum:{ *:[f16] } (fminnum_ieee:{ *:[f16] } (VOP3Mods:{ *:[f16] } f16:{ *:[f16] }:$src0, i32:{ *:[i32] }:$src0_mods), (VOP3Mods:{ *:[f16] } f16:{ *:[f16] }:$src1, i32:{ *:[i32] }:$src1_mods)), (fminnum:{ *:[f16] } (fmaxnum_ieee:{ *:[f16] } (VOP3Mods:{ *:[f16] } f16:{ *:[f16] }:$src0, i32:{ *:[i32] }:$src0_mods), (VOP3Mods:{ *:[f16] } f16:{ *:[f16] }:$src1, i32:{ *:[i32] }:$src1_mods)), (VOP3Mods:{ *:[f16] } f16:{ *:[f16] }:$src2, i32:{ *:[i32] }:$src2_mods)))<<P:Predicate_fmaxnum_like_nnan>>  =>  (V_MED3_F16_e64:{ *:[f16] } ?:{ *:[i32] }:$src0_mods, ?:{ *:[f16] }:$src0, ?:{ *:[i32] }:$src1_mods, ?:{ *:[f16] }:$src1, ?:{ *:[i32] }:$src2_mods, ?:{ *:[f16] }:$src2, 0:{ *:[i1] })
        GIR_BuildMI, /*InsnID*/0, /*Opcode*/GIMT_Encode2(AMDGPU::V_MED3_F16_e64),
        GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/0, // DstI[vdst]
        GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/1, // src0_mods
        GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/0, // src0
        GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(1), /*SubOperand*/1, // src1_mods
        GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(1), /*SubOperand*/0, // src1
        GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(2), /*SubOperand*/1, // src2_mods
        GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(2), /*SubOperand*/0, // src2
        GIR_AddImm8, /*InsnID*/0, /*Imm*/0,
        GIR_AddImm8, /*InsnID*/0, /*Imm*/0,
        GIR_AddImm8, /*InsnID*/0, /*Imm*/0,
        GIR_ConstrainSelectedInstOperands, /*InsnID*/0,
        GIR_EraseFromParent, /*InsnID*/0,
        // GIR_Coverage, 6546,
        GIR_Done,
      // Label 4548: @299366
      GIM_Try, /*On fail goto*//*Label 4549*/ GIMT_Encode4(299512), // Rule ID 10680 //
        GIM_CheckFeatures, GIMT_Encode2(GIFBS_isGFX9Plus),
        GIM_CheckRegBankForClass, /*MI*/0, /*Op*/0, /*RC*/GIMT_Encode2(AMDGPU::VGPR_32RegClassID),
        GIM_RecordInsn, /*DefineMI*/1, /*MI*/0, /*OpIdx*/1, // MIs[1]
        GIM_CheckOpcode, /*MI*/1, GIMT_Encode2(TargetOpcode::G_FMINNUM_IEEE),
        GIM_CheckType, /*MI*/1, /*Op*/1, /*Type*/GILLT_s16,
        GIM_CheckType, /*MI*/1, /*Op*/2, /*Type*/GILLT_s16,
        GIM_RecordInsn, /*DefineMI*/2, /*MI*/0, /*OpIdx*/2, // MIs[2]
        GIM_CheckOpcode, /*MI*/2, GIMT_Encode2(TargetOpcode::G_FMINNUM),
        GIM_CheckType, /*MI*/2, /*Op*/1, /*Type*/GILLT_s16,
        GIM_CheckType, /*MI*/2, /*Op*/2, /*Type*/GILLT_s16,
        GIM_RecordInsn, /*DefineMI*/3, /*MI*/2, /*OpIdx*/1, // MIs[3]
        GIM_CheckOpcode, /*MI*/3, GIMT_Encode2(TargetOpcode::G_FMAXNUM_IEEE),
        // MIs[3] VOP3Mods:src1:src1_mods
        GIM_CheckIsSameOperand, /*MI*/3, /*OpIdx*/1, /*OtherMI*/1, /*OtherOpIdx*/2,
        // MIs[3] VOP3Mods:src0:src0_mods
        GIM_CheckIsSameOperand, /*MI*/3, /*OpIdx*/2, /*OtherMI*/1, /*OtherOpIdx*/1,
        GIM_CheckCxxInsnPredicate, /*MI*/0, /*FnId*/GIMT_Encode2(GICXXPred_MI_Predicate_fmaxnum_like_nnan),
        GIM_CheckIsSafeToFold, /*InsnID*/1,
        GIM_CheckIsSafeToFold, /*InsnID*/2,
        GIM_CheckIsSafeToFold, /*InsnID*/3,
        GIM_CheckComplexPattern, /*MI*/1, /*Op*/1, /*Renderer*/GIMT_Encode2(0), GIMT_Encode2(GICP_gi_vop3mods),
        GIM_CheckComplexPattern, /*MI*/1, /*Op*/2, /*Renderer*/GIMT_Encode2(1), GIMT_Encode2(GICP_gi_vop3mods),
        GIM_CheckComplexPattern, /*MI*/2, /*Op*/2, /*Renderer*/GIMT_Encode2(2), GIMT_Encode2(GICP_gi_vop3mods),
        // (fmaxnum:{ *:[f16] } (fminnum_ieee:{ *:[f16] } (VOP3Mods:{ *:[f16] } f16:{ *:[f16] }:$src0, i32:{ *:[i32] }:$src0_mods), (VOP3Mods:{ *:[f16] } f16:{ *:[f16] }:$src1, i32:{ *:[i32] }:$src1_mods)), (fminnum:{ *:[f16] } (fmaxnum_ieee:{ *:[f16] } (VOP3Mods:{ *:[f16] } f16:{ *:[f16] }:$src1, i32:{ *:[i32] }:$src1_mods), (VOP3Mods:{ *:[f16] } f16:{ *:[f16] }:$src0, i32:{ *:[i32] }:$src0_mods)), (VOP3Mods:{ *:[f16] } f16:{ *:[f16] }:$src2, i32:{ *:[i32] }:$src2_mods)))<<P:Predicate_fmaxnum_like_nnan>>  =>  (V_MED3_F16_e64:{ *:[f16] } ?:{ *:[i32] }:$src0_mods, ?:{ *:[f16] }:$src0, ?:{ *:[i32] }:$src1_mods, ?:{ *:[f16] }:$src1, ?:{ *:[i32] }:$src2_mods, ?:{ *:[f16] }:$src2, 0:{ *:[i1] })
        GIR_BuildMI, /*InsnID*/0, /*Opcode*/GIMT_Encode2(AMDGPU::V_MED3_F16_e64),
        GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/0, // DstI[vdst]
        GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/1, // src0_mods
        GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/0, // src0
        GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(1), /*SubOperand*/1, // src1_mods
        GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(1), /*SubOperand*/0, // src1
        GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(2), /*SubOperand*/1, // src2_mods
        GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(2), /*SubOperand*/0, // src2
        GIR_AddImm8, /*InsnID*/0, /*Imm*/0,
        GIR_AddImm8, /*InsnID*/0, /*Imm*/0,
        GIR_AddImm8, /*InsnID*/0, /*Imm*/0,
        GIR_ConstrainSelectedInstOperands, /*InsnID*/0,
        GIR_EraseFromParent, /*InsnID*/0,
        // GIR_Coverage, 10680,
        GIR_Done,
      // Label 4549: @299512
      GIM_Try, /*On fail goto*//*Label 4550*/ GIMT_Encode4(299658), // Rule ID 10683 //
        GIM_CheckFeatures, GIMT_Encode2(GIFBS_isGFX9Plus),
        GIM_CheckRegBankForClass, /*MI*/0, /*Op*/0, /*RC*/GIMT_Encode2(AMDGPU::VGPR_32RegClassID),
        GIM_RecordInsn, /*DefineMI*/1, /*MI*/0, /*OpIdx*/1, // MIs[1]
        GIM_CheckOpcode, /*MI*/1, GIMT_Encode2(TargetOpcode::G_FMINNUM_IEEE),
        GIM_CheckType, /*MI*/1, /*Op*/1, /*Type*/GILLT_s16,
        GIM_CheckType, /*MI*/1, /*Op*/2, /*Type*/GILLT_s16,
        GIM_RecordInsn, /*DefineMI*/2, /*MI*/0, /*OpIdx*/2, // MIs[2]
        GIM_CheckOpcode, /*MI*/2, GIMT_Encode2(TargetOpcode::G_FMINNUM),
        GIM_CheckType, /*MI*/2, /*Op*/1, /*Type*/GILLT_s16,
        GIM_CheckType, /*MI*/2, /*Op*/2, /*Type*/GILLT_s16,
        GIM_RecordInsn, /*DefineMI*/3, /*MI*/2, /*OpIdx*/1, // MIs[3]
        GIM_CheckOpcode, /*MI*/3, GIMT_Encode2(TargetOpcode::G_FMAXNUM_IEEE),
        // MIs[3] VOP3Mods:src0:src0_mods
        GIM_CheckIsSameOperand, /*MI*/3, /*OpIdx*/1, /*OtherMI*/1, /*OtherOpIdx*/2,
        // MIs[3] VOP3Mods:src1:src1_mods
        GIM_CheckIsSameOperand, /*MI*/3, /*OpIdx*/2, /*OtherMI*/1, /*OtherOpIdx*/1,
        GIM_CheckCxxInsnPredicate, /*MI*/0, /*FnId*/GIMT_Encode2(GICXXPred_MI_Predicate_fmaxnum_like_nnan),
        GIM_CheckIsSafeToFold, /*InsnID*/1,
        GIM_CheckIsSafeToFold, /*InsnID*/2,
        GIM_CheckIsSafeToFold, /*InsnID*/3,
        GIM_CheckComplexPattern, /*MI*/1, /*Op*/1, /*Renderer*/GIMT_Encode2(0), GIMT_Encode2(GICP_gi_vop3mods),
        GIM_CheckComplexPattern, /*MI*/1, /*Op*/2, /*Renderer*/GIMT_Encode2(1), GIMT_Encode2(GICP_gi_vop3mods),
        GIM_CheckComplexPattern, /*MI*/2, /*Op*/2, /*Renderer*/GIMT_Encode2(2), GIMT_Encode2(GICP_gi_vop3mods),
        // (fmaxnum:{ *:[f16] } (fminnum_ieee:{ *:[f16] } (VOP3Mods:{ *:[f16] } f16:{ *:[f16] }:$src1, i32:{ *:[i32] }:$src1_mods), (VOP3Mods:{ *:[f16] } f16:{ *:[f16] }:$src0, i32:{ *:[i32] }:$src0_mods)), (fminnum:{ *:[f16] } (fmaxnum_ieee:{ *:[f16] } (VOP3Mods:{ *:[f16] } f16:{ *:[f16] }:$src0, i32:{ *:[i32] }:$src0_mods), (VOP3Mods:{ *:[f16] } f16:{ *:[f16] }:$src1, i32:{ *:[i32] }:$src1_mods)), (VOP3Mods:{ *:[f16] } f16:{ *:[f16] }:$src2, i32:{ *:[i32] }:$src2_mods)))<<P:Predicate_fmaxnum_like_nnan>>  =>  (V_MED3_F16_e64:{ *:[f16] } ?:{ *:[i32] }:$src0_mods, ?:{ *:[f16] }:$src0, ?:{ *:[i32] }:$src1_mods, ?:{ *:[f16] }:$src1, ?:{ *:[i32] }:$src2_mods, ?:{ *:[f16] }:$src2, 0:{ *:[i1] })
        GIR_BuildMI, /*InsnID*/0, /*Opcode*/GIMT_Encode2(AMDGPU::V_MED3_F16_e64),
        GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/0, // DstI[vdst]
        GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(1), /*SubOperand*/1, // src0_mods
        GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(1), /*SubOperand*/0, // src0
        GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/1, // src1_mods
        GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/0, // src1
        GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(2), /*SubOperand*/1, // src2_mods
        GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(2), /*SubOperand*/0, // src2
        GIR_AddImm8, /*InsnID*/0, /*Imm*/0,
        GIR_AddImm8, /*InsnID*/0, /*Imm*/0,
        GIR_AddImm8, /*InsnID*/0, /*Imm*/0,
        GIR_ConstrainSelectedInstOperands, /*InsnID*/0,
        GIR_EraseFromParent, /*InsnID*/0,
        // GIR_Coverage, 10683,
        GIR_Done,
      // Label 4550: @299658
      GIM_Try, /*On fail goto*//*Label 4551*/ GIMT_Encode4(299804), // Rule ID 10684 //
        GIM_CheckFeatures, GIMT_Encode2(GIFBS_isGFX9Plus),
        GIM_CheckRegBankForClass, /*MI*/0, /*Op*/0, /*RC*/GIMT_Encode2(AMDGPU::VGPR_32RegClassID),
        GIM_RecordInsn, /*DefineMI*/1, /*MI*/0, /*OpIdx*/1, // MIs[1]
        GIM_CheckOpcode, /*MI*/1, GIMT_Encode2(TargetOpcode::G_FMINNUM_IEEE),
        GIM_CheckType, /*MI*/1, /*Op*/1, /*Type*/GILLT_s16,
        GIM_CheckType, /*MI*/1, /*Op*/2, /*Type*/GILLT_s16,
        GIM_RecordInsn, /*DefineMI*/2, /*MI*/0, /*OpIdx*/2, // MIs[2]
        GIM_CheckOpcode, /*MI*/2, GIMT_Encode2(TargetOpcode::G_FMINNUM),
        GIM_CheckType, /*MI*/2, /*Op*/1, /*Type*/GILLT_s16,
        GIM_CheckType, /*MI*/2, /*Op*/2, /*Type*/GILLT_s16,
        GIM_RecordInsn, /*DefineMI*/3, /*MI*/2, /*OpIdx*/1, // MIs[3]
        GIM_CheckOpcode, /*MI*/3, GIMT_Encode2(TargetOpcode::G_FMAXNUM_IEEE),
        // MIs[3] VOP3Mods:src1:src1_mods
        GIM_CheckIsSameOperand, /*MI*/3, /*OpIdx*/1, /*OtherMI*/1, /*OtherOpIdx*/1,
        // MIs[3] VOP3Mods:src0:src0_mods
        GIM_CheckIsSameOperand, /*MI*/3, /*OpIdx*/2, /*OtherMI*/1, /*OtherOpIdx*/2,
        GIM_CheckCxxInsnPredicate, /*MI*/0, /*FnId*/GIMT_Encode2(GICXXPred_MI_Predicate_fmaxnum_like_nnan),
        GIM_CheckIsSafeToFold, /*InsnID*/1,
        GIM_CheckIsSafeToFold, /*InsnID*/2,
        GIM_CheckIsSafeToFold, /*InsnID*/3,
        GIM_CheckComplexPattern, /*MI*/1, /*Op*/1, /*Renderer*/GIMT_Encode2(0), GIMT_Encode2(GICP_gi_vop3mods),
        GIM_CheckComplexPattern, /*MI*/1, /*Op*/2, /*Renderer*/GIMT_Encode2(1), GIMT_Encode2(GICP_gi_vop3mods),
        GIM_CheckComplexPattern, /*MI*/2, /*Op*/2, /*Renderer*/GIMT_Encode2(2), GIMT_Encode2(GICP_gi_vop3mods),
        // (fmaxnum:{ *:[f16] } (fminnum_ieee:{ *:[f16] } (VOP3Mods:{ *:[f16] } f16:{ *:[f16] }:$src1, i32:{ *:[i32] }:$src1_mods), (VOP3Mods:{ *:[f16] } f16:{ *:[f16] }:$src0, i32:{ *:[i32] }:$src0_mods)), (fminnum:{ *:[f16] } (fmaxnum_ieee:{ *:[f16] } (VOP3Mods:{ *:[f16] } f16:{ *:[f16] }:$src1, i32:{ *:[i32] }:$src1_mods), (VOP3Mods:{ *:[f16] } f16:{ *:[f16] }:$src0, i32:{ *:[i32] }:$src0_mods)), (VOP3Mods:{ *:[f16] } f16:{ *:[f16] }:$src2, i32:{ *:[i32] }:$src2_mods)))<<P:Predicate_fmaxnum_like_nnan>>  =>  (V_MED3_F16_e64:{ *:[f16] } ?:{ *:[i32] }:$src0_mods, ?:{ *:[f16] }:$src0, ?:{ *:[i32] }:$src1_mods, ?:{ *:[f16] }:$src1, ?:{ *:[i32] }:$src2_mods, ?:{ *:[f16] }:$src2, 0:{ *:[i1] })
        GIR_BuildMI, /*InsnID*/0, /*Opcode*/GIMT_Encode2(AMDGPU::V_MED3_F16_e64),
        GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/0, // DstI[vdst]
        GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(1), /*SubOperand*/1, // src0_mods
        GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(1), /*SubOperand*/0, // src0
        GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/1, // src1_mods
        GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/0, // src1
        GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(2), /*SubOperand*/1, // src2_mods
        GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(2), /*SubOperand*/0, // src2
        GIR_AddImm8, /*InsnID*/0, /*Imm*/0,
        GIR_AddImm8, /*InsnID*/0, /*Imm*/0,
        GIR_AddImm8, /*InsnID*/0, /*Imm*/0,
        GIR_ConstrainSelectedInstOperands, /*InsnID*/0,
        GIR_EraseFromParent, /*InsnID*/0,
        // GIR_Coverage, 10684,
        GIR_Done,
      // Label 4551: @299804
      GIM_Try, /*On fail goto*//*Label 4552*/ GIMT_Encode4(299950), // Rule ID 10666 //
        GIM_CheckFeatures, GIMT_Encode2(GIFBS_isGFX9Plus),
        GIM_CheckRegBankForClass, /*MI*/0, /*Op*/0, /*RC*/GIMT_Encode2(AMDGPU::VGPR_32RegClassID),
        GIM_RecordInsn, /*DefineMI*/1, /*MI*/0, /*OpIdx*/1, // MIs[1]
        GIM_CheckOpcode, /*MI*/1, GIMT_Encode2(TargetOpcode::G_FMINNUM_IEEE),
        GIM_CheckType, /*MI*/1, /*Op*/1, /*Type*/GILLT_s16,
        GIM_CheckType, /*MI*/1, /*Op*/2, /*Type*/GILLT_s16,
        GIM_RecordInsn, /*DefineMI*/2, /*MI*/0, /*OpIdx*/2, // MIs[2]
        GIM_CheckOpcode, /*MI*/2, GIMT_Encode2(TargetOpcode::G_FMINNUM_IEEE),
        GIM_CheckType, /*MI*/2, /*Op*/1, /*Type*/GILLT_s16,
        GIM_CheckType, /*MI*/2, /*Op*/2, /*Type*/GILLT_s16,
        GIM_RecordInsn, /*DefineMI*/3, /*MI*/2, /*OpIdx*/2, // MIs[3]
        GIM_CheckOpcode, /*MI*/3, GIMT_Encode2(TargetOpcode::G_FMAXNUM),
        // MIs[3] VOP3Mods:src0:src0_mods
        GIM_CheckIsSameOperand, /*MI*/3, /*OpIdx*/1, /*OtherMI*/1, /*OtherOpIdx*/1,
        // MIs[3] VOP3Mods:src1:src1_mods
        GIM_CheckIsSameOperand, /*MI*/3, /*OpIdx*/2, /*OtherMI*/1, /*OtherOpIdx*/2,
        GIM_CheckCxxInsnPredicate, /*MI*/0, /*FnId*/GIMT_Encode2(GICXXPred_MI_Predicate_fmaxnum_like_nnan),
        GIM_CheckIsSafeToFold, /*InsnID*/1,
        GIM_CheckIsSafeToFold, /*InsnID*/2,
        GIM_CheckIsSafeToFold, /*InsnID*/3,
        GIM_CheckComplexPattern, /*MI*/1, /*Op*/1, /*Renderer*/GIMT_Encode2(0), GIMT_Encode2(GICP_gi_vop3mods),
        GIM_CheckComplexPattern, /*MI*/1, /*Op*/2, /*Renderer*/GIMT_Encode2(1), GIMT_Encode2(GICP_gi_vop3mods),
        GIM_CheckComplexPattern, /*MI*/2, /*Op*/1, /*Renderer*/GIMT_Encode2(2), GIMT_Encode2(GICP_gi_vop3mods),
        // (fmaxnum:{ *:[f16] } (fminnum_ieee:{ *:[f16] } (VOP3Mods:{ *:[f16] } f16:{ *:[f16] }:$src0, i32:{ *:[i32] }:$src0_mods), (VOP3Mods:{ *:[f16] } f16:{ *:[f16] }:$src1, i32:{ *:[i32] }:$src1_mods)), (fminnum_ieee:{ *:[f16] } (VOP3Mods:{ *:[f16] } f16:{ *:[f16] }:$src2, i32:{ *:[i32] }:$src2_mods), (fmaxnum:{ *:[f16] } (VOP3Mods:{ *:[f16] } f16:{ *:[f16] }:$src0, i32:{ *:[i32] }:$src0_mods), (VOP3Mods:{ *:[f16] } f16:{ *:[f16] }:$src1, i32:{ *:[i32] }:$src1_mods))))<<P:Predicate_fmaxnum_like_nnan>>  =>  (V_MED3_F16_e64:{ *:[f16] } ?:{ *:[i32] }:$src0_mods, ?:{ *:[f16] }:$src0, ?:{ *:[i32] }:$src1_mods, ?:{ *:[f16] }:$src1, ?:{ *:[i32] }:$src2_mods, ?:{ *:[f16] }:$src2, 0:{ *:[i1] })
        GIR_BuildMI, /*InsnID*/0, /*Opcode*/GIMT_Encode2(AMDGPU::V_MED3_F16_e64),
        GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/0, // DstI[vdst]
        GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/1, // src0_mods
        GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/0, // src0
        GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(1), /*SubOperand*/1, // src1_mods
        GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(1), /*SubOperand*/0, // src1
        GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(2), /*SubOperand*/1, // src2_mods
        GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(2), /*SubOperand*/0, // src2
        GIR_AddImm8, /*InsnID*/0, /*Imm*/0,
        GIR_AddImm8, /*InsnID*/0, /*Imm*/0,
        GIR_AddImm8, /*InsnID*/0, /*Imm*/0,
        GIR_ConstrainSelectedInstOperands, /*InsnID*/0,
        GIR_EraseFromParent, /*InsnID*/0,
        // GIR_Coverage, 10666,
        GIR_Done,
      // Label 4552: @299950
      GIM_Try, /*On fail goto*//*Label 4553*/ GIMT_Encode4(300096), // Rule ID 10667 //
        GIM_CheckFeatures, GIMT_Encode2(GIFBS_isGFX9Plus),
        GIM_CheckRegBankForClass, /*MI*/0, /*Op*/0, /*RC*/GIMT_Encode2(AMDGPU::VGPR_32RegClassID),
        GIM_RecordInsn, /*DefineMI*/1, /*MI*/0, /*OpIdx*/1, // MIs[1]
        GIM_CheckOpcode, /*MI*/1, GIMT_Encode2(TargetOpcode::G_FMINNUM_IEEE),
        GIM_CheckType, /*MI*/1, /*Op*/1, /*Type*/GILLT_s16,
        GIM_CheckType, /*MI*/1, /*Op*/2, /*Type*/GILLT_s16,
        GIM_RecordInsn, /*DefineMI*/2, /*MI*/0, /*OpIdx*/2, // MIs[2]
        GIM_CheckOpcode, /*MI*/2, GIMT_Encode2(TargetOpcode::G_FMINNUM_IEEE),
        GIM_CheckType, /*MI*/2, /*Op*/1, /*Type*/GILLT_s16,
        GIM_CheckType, /*MI*/2, /*Op*/2, /*Type*/GILLT_s16,
        GIM_RecordInsn, /*DefineMI*/3, /*MI*/2, /*OpIdx*/2, // MIs[3]
        GIM_CheckOpcode, /*MI*/3, GIMT_Encode2(TargetOpcode::G_FMAXNUM),
        // MIs[3] VOP3Mods:src1:src1_mods
        GIM_CheckIsSameOperand, /*MI*/3, /*OpIdx*/1, /*OtherMI*/1, /*OtherOpIdx*/2,
        // MIs[3] VOP3Mods:src0:src0_mods
        GIM_CheckIsSameOperand, /*MI*/3, /*OpIdx*/2, /*OtherMI*/1, /*OtherOpIdx*/1,
        GIM_CheckCxxInsnPredicate, /*MI*/0, /*FnId*/GIMT_Encode2(GICXXPred_MI_Predicate_fmaxnum_like_nnan),
        GIM_CheckIsSafeToFold, /*InsnID*/1,
        GIM_CheckIsSafeToFold, /*InsnID*/2,
        GIM_CheckIsSafeToFold, /*InsnID*/3,
        GIM_CheckComplexPattern, /*MI*/1, /*Op*/1, /*Renderer*/GIMT_Encode2(0), GIMT_Encode2(GICP_gi_vop3mods),
        GIM_CheckComplexPattern, /*MI*/1, /*Op*/2, /*Renderer*/GIMT_Encode2(1), GIMT_Encode2(GICP_gi_vop3mods),
        GIM_CheckComplexPattern, /*MI*/2, /*Op*/1, /*Renderer*/GIMT_Encode2(2), GIMT_Encode2(GICP_gi_vop3mods),
        // (fmaxnum:{ *:[f16] } (fminnum_ieee:{ *:[f16] } (VOP3Mods:{ *:[f16] } f16:{ *:[f16] }:$src0, i32:{ *:[i32] }:$src0_mods), (VOP3Mods:{ *:[f16] } f16:{ *:[f16] }:$src1, i32:{ *:[i32] }:$src1_mods)), (fminnum_ieee:{ *:[f16] } (VOP3Mods:{ *:[f16] } f16:{ *:[f16] }:$src2, i32:{ *:[i32] }:$src2_mods), (fmaxnum:{ *:[f16] } (VOP3Mods:{ *:[f16] } f16:{ *:[f16] }:$src1, i32:{ *:[i32] }:$src1_mods), (VOP3Mods:{ *:[f16] } f16:{ *:[f16] }:$src0, i32:{ *:[i32] }:$src0_mods))))<<P:Predicate_fmaxnum_like_nnan>>  =>  (V_MED3_F16_e64:{ *:[f16] } ?:{ *:[i32] }:$src0_mods, ?:{ *:[f16] }:$src0, ?:{ *:[i32] }:$src1_mods, ?:{ *:[f16] }:$src1, ?:{ *:[i32] }:$src2_mods, ?:{ *:[f16] }:$src2, 0:{ *:[i1] })
        GIR_BuildMI, /*InsnID*/0, /*Opcode*/GIMT_Encode2(AMDGPU::V_MED3_F16_e64),
        GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/0, // DstI[vdst]
        GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/1, // src0_mods
        GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/0, // src0
        GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(1), /*SubOperand*/1, // src1_mods
        GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(1), /*SubOperand*/0, // src1
        GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(2), /*SubOperand*/1, // src2_mods
        GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(2), /*SubOperand*/0, // src2
        GIR_AddImm8, /*InsnID*/0, /*Imm*/0,
        GIR_AddImm8, /*InsnID*/0, /*Imm*/0,
        GIR_AddImm8, /*InsnID*/0, /*Imm*/0,
        GIR_ConstrainSelectedInstOperands, /*InsnID*/0,
        GIR_EraseFromParent, /*InsnID*/0,
        // GIR_Coverage, 10667,
        GIR_Done,
      // Label 4553: @300096
      GIM_Try, /*On fail goto*//*Label 4554*/ GIMT_Encode4(300242), // Rule ID 10670 //
        GIM_CheckFeatures, GIMT_Encode2(GIFBS_isGFX9Plus),
        GIM_CheckRegBankForClass, /*MI*/0, /*Op*/0, /*RC*/GIMT_Encode2(AMDGPU::VGPR_32RegClassID),
        GIM_RecordInsn, /*DefineMI*/1, /*MI*/0, /*OpIdx*/1, // MIs[1]
        GIM_CheckOpcode, /*MI*/1, GIMT_Encode2(TargetOpcode::G_FMINNUM_IEEE),
        GIM_CheckType, /*MI*/1, /*Op*/1, /*Type*/GILLT_s16,
        GIM_CheckType, /*MI*/1, /*Op*/2, /*Type*/GILLT_s16,
        GIM_RecordInsn, /*DefineMI*/2, /*MI*/0, /*OpIdx*/2, // MIs[2]
        GIM_CheckOpcode, /*MI*/2, GIMT_Encode2(TargetOpcode::G_FMINNUM_IEEE),
        GIM_CheckType, /*MI*/2, /*Op*/1, /*Type*/GILLT_s16,
        GIM_CheckType, /*MI*/2, /*Op*/2, /*Type*/GILLT_s16,
        GIM_RecordInsn, /*DefineMI*/3, /*MI*/2, /*OpIdx*/2, // MIs[3]
        GIM_CheckOpcode, /*MI*/3, GIMT_Encode2(TargetOpcode::G_FMAXNUM),
        // MIs[3] VOP3Mods:src0:src0_mods
        GIM_CheckIsSameOperand, /*MI*/3, /*OpIdx*/1, /*OtherMI*/1, /*OtherOpIdx*/2,
        // MIs[3] VOP3Mods:src1:src1_mods
        GIM_CheckIsSameOperand, /*MI*/3, /*OpIdx*/2, /*OtherMI*/1, /*OtherOpIdx*/1,
        GIM_CheckCxxInsnPredicate, /*MI*/0, /*FnId*/GIMT_Encode2(GICXXPred_MI_Predicate_fmaxnum_like_nnan),
        GIM_CheckIsSafeToFold, /*InsnID*/1,
        GIM_CheckIsSafeToFold, /*InsnID*/2,
        GIM_CheckIsSafeToFold, /*InsnID*/3,
        GIM_CheckComplexPattern, /*MI*/1, /*Op*/1, /*Renderer*/GIMT_Encode2(0), GIMT_Encode2(GICP_gi_vop3mods),
        GIM_CheckComplexPattern, /*MI*/1, /*Op*/2, /*Renderer*/GIMT_Encode2(1), GIMT_Encode2(GICP_gi_vop3mods),
        GIM_CheckComplexPattern, /*MI*/2, /*Op*/1, /*Renderer*/GIMT_Encode2(2), GIMT_Encode2(GICP_gi_vop3mods),
        // (fmaxnum:{ *:[f16] } (fminnum_ieee:{ *:[f16] } (VOP3Mods:{ *:[f16] } f16:{ *:[f16] }:$src1, i32:{ *:[i32] }:$src1_mods), (VOP3Mods:{ *:[f16] } f16:{ *:[f16] }:$src0, i32:{ *:[i32] }:$src0_mods)), (fminnum_ieee:{ *:[f16] } (VOP3Mods:{ *:[f16] } f16:{ *:[f16] }:$src2, i32:{ *:[i32] }:$src2_mods), (fmaxnum:{ *:[f16] } (VOP3Mods:{ *:[f16] } f16:{ *:[f16] }:$src0, i32:{ *:[i32] }:$src0_mods), (VOP3Mods:{ *:[f16] } f16:{ *:[f16] }:$src1, i32:{ *:[i32] }:$src1_mods))))<<P:Predicate_fmaxnum_like_nnan>>  =>  (V_MED3_F16_e64:{ *:[f16] } ?:{ *:[i32] }:$src0_mods, ?:{ *:[f16] }:$src0, ?:{ *:[i32] }:$src1_mods, ?:{ *:[f16] }:$src1, ?:{ *:[i32] }:$src2_mods, ?:{ *:[f16] }:$src2, 0:{ *:[i1] })
        GIR_BuildMI, /*InsnID*/0, /*Opcode*/GIMT_Encode2(AMDGPU::V_MED3_F16_e64),
        GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/0, // DstI[vdst]
        GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(1), /*SubOperand*/1, // src0_mods
        GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(1), /*SubOperand*/0, // src0
        GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/1, // src1_mods
        GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/0, // src1
        GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(2), /*SubOperand*/1, // src2_mods
        GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(2), /*SubOperand*/0, // src2
        GIR_AddImm8, /*InsnID*/0, /*Imm*/0,
        GIR_AddImm8, /*InsnID*/0, /*Imm*/0,
        GIR_AddImm8, /*InsnID*/0, /*Imm*/0,
        GIR_ConstrainSelectedInstOperands, /*InsnID*/0,
        GIR_EraseFromParent, /*InsnID*/0,
        // GIR_Coverage, 10670,
        GIR_Done,
      // Label 4554: @300242
      GIM_Try, /*On fail goto*//*Label 4555*/ GIMT_Encode4(300388), // Rule ID 10671 //
        GIM_CheckFeatures, GIMT_Encode2(GIFBS_isGFX9Plus),
        GIM_CheckRegBankForClass, /*MI*/0, /*Op*/0, /*RC*/GIMT_Encode2(AMDGPU::VGPR_32RegClassID),
        GIM_RecordInsn, /*DefineMI*/1, /*MI*/0, /*OpIdx*/1, // MIs[1]
        GIM_CheckOpcode, /*MI*/1, GIMT_Encode2(TargetOpcode::G_FMINNUM_IEEE),
        GIM_CheckType, /*MI*/1, /*Op*/1, /*Type*/GILLT_s16,
        GIM_CheckType, /*MI*/1, /*Op*/2, /*Type*/GILLT_s16,
        GIM_RecordInsn, /*DefineMI*/2, /*MI*/0, /*OpIdx*/2, // MIs[2]
        GIM_CheckOpcode, /*MI*/2, GIMT_Encode2(TargetOpcode::G_FMINNUM_IEEE),
        GIM_CheckType, /*MI*/2, /*Op*/1, /*Type*/GILLT_s16,
        GIM_CheckType, /*MI*/2, /*Op*/2, /*Type*/GILLT_s16,
        GIM_RecordInsn, /*DefineMI*/3, /*MI*/2, /*OpIdx*/2, // MIs[3]
        GIM_CheckOpcode, /*MI*/3, GIMT_Encode2(TargetOpcode::G_FMAXNUM),
        // MIs[3] VOP3Mods:src1:src1_mods
        GIM_CheckIsSameOperand, /*MI*/3, /*OpIdx*/1, /*OtherMI*/1, /*OtherOpIdx*/1,
        // MIs[3] VOP3Mods:src0:src0_mods
        GIM_CheckIsSameOperand, /*MI*/3, /*OpIdx*/2, /*OtherMI*/1, /*OtherOpIdx*/2,
        GIM_CheckCxxInsnPredicate, /*MI*/0, /*FnId*/GIMT_Encode2(GICXXPred_MI_Predicate_fmaxnum_like_nnan),
        GIM_CheckIsSafeToFold, /*InsnID*/1,
        GIM_CheckIsSafeToFold, /*InsnID*/2,
        GIM_CheckIsSafeToFold, /*InsnID*/3,
        GIM_CheckComplexPattern, /*MI*/1, /*Op*/1, /*Renderer*/GIMT_Encode2(0), GIMT_Encode2(GICP_gi_vop3mods),
        GIM_CheckComplexPattern, /*MI*/1, /*Op*/2, /*Renderer*/GIMT_Encode2(1), GIMT_Encode2(GICP_gi_vop3mods),
        GIM_CheckComplexPattern, /*MI*/2, /*Op*/1, /*Renderer*/GIMT_Encode2(2), GIMT_Encode2(GICP_gi_vop3mods),
        // (fmaxnum:{ *:[f16] } (fminnum_ieee:{ *:[f16] } (VOP3Mods:{ *:[f16] } f16:{ *:[f16] }:$src1, i32:{ *:[i32] }:$src1_mods), (VOP3Mods:{ *:[f16] } f16:{ *:[f16] }:$src0, i32:{ *:[i32] }:$src0_mods)), (fminnum_ieee:{ *:[f16] } (VOP3Mods:{ *:[f16] } f16:{ *:[f16] }:$src2, i32:{ *:[i32] }:$src2_mods), (fmaxnum:{ *:[f16] } (VOP3Mods:{ *:[f16] } f16:{ *:[f16] }:$src1, i32:{ *:[i32] }:$src1_mods), (VOP3Mods:{ *:[f16] } f16:{ *:[f16] }:$src0, i32:{ *:[i32] }:$src0_mods))))<<P:Predicate_fmaxnum_like_nnan>>  =>  (V_MED3_F16_e64:{ *:[f16] } ?:{ *:[i32] }:$src0_mods, ?:{ *:[f16] }:$src0, ?:{ *:[i32] }:$src1_mods, ?:{ *:[f16] }:$src1, ?:{ *:[i32] }:$src2_mods, ?:{ *:[f16] }:$src2, 0:{ *:[i1] })
        GIR_BuildMI, /*InsnID*/0, /*Opcode*/GIMT_Encode2(AMDGPU::V_MED3_F16_e64),
        GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/0, // DstI[vdst]
        GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(1), /*SubOperand*/1, // src0_mods
        GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(1), /*SubOperand*/0, // src0
        GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/1, // src1_mods
        GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/0, // src1
        GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(2), /*SubOperand*/1, // src2_mods
        GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(2), /*SubOperand*/0, // src2
        GIR_AddImm8, /*InsnID*/0, /*Imm*/0,
        GIR_AddImm8, /*InsnID*/0, /*Imm*/0,
        GIR_AddImm8, /*InsnID*/0, /*Imm*/0,
        GIR_ConstrainSelectedInstOperands, /*InsnID*/0,
        GIR_EraseFromParent, /*InsnID*/0,
        // GIR_Coverage, 10671,
        GIR_Done,
      // Label 4555: @300388
      GIM_Try, /*On fail goto*//*Label 4556*/ GIMT_Encode4(300534), // Rule ID 10651 //
        GIM_CheckFeatures, GIMT_Encode2(GIFBS_isGFX9Plus),
        GIM_CheckRegBankForClass, /*MI*/0, /*Op*/0, /*RC*/GIMT_Encode2(AMDGPU::VGPR_32RegClassID),
        GIM_RecordInsn, /*DefineMI*/1, /*MI*/0, /*OpIdx*/1, // MIs[1]
        GIM_CheckOpcode, /*MI*/1, GIMT_Encode2(TargetOpcode::G_FMINNUM_IEEE),
        GIM_CheckType, /*MI*/1, /*Op*/1, /*Type*/GILLT_s16,
        GIM_CheckType, /*MI*/1, /*Op*/2, /*Type*/GILLT_s16,
        GIM_RecordInsn, /*DefineMI*/2, /*MI*/0, /*OpIdx*/2, // MIs[2]
        GIM_CheckOpcode, /*MI*/2, GIMT_Encode2(TargetOpcode::G_FMINNUM_IEEE),
        GIM_CheckType, /*MI*/2, /*Op*/1, /*Type*/GILLT_s16,
        GIM_CheckType, /*MI*/2, /*Op*/2, /*Type*/GILLT_s16,
        GIM_RecordInsn, /*DefineMI*/3, /*MI*/2, /*OpIdx*/2, // MIs[3]
        GIM_CheckOpcode, /*MI*/3, GIMT_Encode2(TargetOpcode::G_FMAXNUM_IEEE),
        // MIs[3] VOP3Mods:src0:src0_mods
        GIM_CheckIsSameOperand, /*MI*/3, /*OpIdx*/1, /*OtherMI*/1, /*OtherOpIdx*/1,
        // MIs[3] VOP3Mods:src1:src1_mods
        GIM_CheckIsSameOperand, /*MI*/3, /*OpIdx*/2, /*OtherMI*/1, /*OtherOpIdx*/2,
        GIM_CheckCxxInsnPredicate, /*MI*/0, /*FnId*/GIMT_Encode2(GICXXPred_MI_Predicate_fmaxnum_like_nnan),
        GIM_CheckIsSafeToFold, /*InsnID*/1,
        GIM_CheckIsSafeToFold, /*InsnID*/2,
        GIM_CheckIsSafeToFold, /*InsnID*/3,
        GIM_CheckComplexPattern, /*MI*/1, /*Op*/1, /*Renderer*/GIMT_Encode2(0), GIMT_Encode2(GICP_gi_vop3mods),
        GIM_CheckComplexPattern, /*MI*/1, /*Op*/2, /*Renderer*/GIMT_Encode2(1), GIMT_Encode2(GICP_gi_vop3mods),
        GIM_CheckComplexPattern, /*MI*/2, /*Op*/1, /*Renderer*/GIMT_Encode2(2), GIMT_Encode2(GICP_gi_vop3mods),
        // (fmaxnum:{ *:[f16] } (fminnum_ieee:{ *:[f16] } (VOP3Mods:{ *:[f16] } f16:{ *:[f16] }:$src0, i32:{ *:[i32] }:$src0_mods), (VOP3Mods:{ *:[f16] } f16:{ *:[f16] }:$src1, i32:{ *:[i32] }:$src1_mods)), (fminnum_ieee:{ *:[f16] } (VOP3Mods:{ *:[f16] } f16:{ *:[f16] }:$src2, i32:{ *:[i32] }:$src2_mods), (fmaxnum_ieee:{ *:[f16] } (VOP3Mods:{ *:[f16] } f16:{ *:[f16] }:$src0, i32:{ *:[i32] }:$src0_mods), (VOP3Mods:{ *:[f16] } f16:{ *:[f16] }:$src1, i32:{ *:[i32] }:$src1_mods))))<<P:Predicate_fmaxnum_like_nnan>>  =>  (V_MED3_F16_e64:{ *:[f16] } ?:{ *:[i32] }:$src0_mods, ?:{ *:[f16] }:$src0, ?:{ *:[i32] }:$src1_mods, ?:{ *:[f16] }:$src1, ?:{ *:[i32] }:$src2_mods, ?:{ *:[f16] }:$src2, 0:{ *:[i1] })
        GIR_BuildMI, /*InsnID*/0, /*Opcode*/GIMT_Encode2(AMDGPU::V_MED3_F16_e64),
        GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/0, // DstI[vdst]
        GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/1, // src0_mods
        GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/0, // src0
        GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(1), /*SubOperand*/1, // src1_mods
        GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(1), /*SubOperand*/0, // src1
        GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(2), /*SubOperand*/1, // src2_mods
        GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(2), /*SubOperand*/0, // src2
        GIR_AddImm8, /*InsnID*/0, /*Imm*/0,
        GIR_AddImm8, /*InsnID*/0, /*Imm*/0,
        GIR_AddImm8, /*InsnID*/0, /*Imm*/0,
        GIR_ConstrainSelectedInstOperands, /*InsnID*/0,
        GIR_EraseFromParent, /*InsnID*/0,
        // GIR_Coverage, 10651,
        GIR_Done,
      // Label 4556: @300534
      GIM_Try, /*On fail goto*//*Label 4557*/ GIMT_Encode4(300680), // Rule ID 10652 //
        GIM_CheckFeatures, GIMT_Encode2(GIFBS_isGFX9Plus),
        GIM_CheckRegBankForClass, /*MI*/0, /*Op*/0, /*RC*/GIMT_Encode2(AMDGPU::VGPR_32RegClassID),
        GIM_RecordInsn, /*DefineMI*/1, /*MI*/0, /*OpIdx*/1, // MIs[1]
        GIM_CheckOpcode, /*MI*/1, GIMT_Encode2(TargetOpcode::G_FMINNUM_IEEE),
        GIM_CheckType, /*MI*/1, /*Op*/1, /*Type*/GILLT_s16,
        GIM_CheckType, /*MI*/1, /*Op*/2, /*Type*/GILLT_s16,
        GIM_RecordInsn, /*DefineMI*/2, /*MI*/0, /*OpIdx*/2, // MIs[2]
        GIM_CheckOpcode, /*MI*/2, GIMT_Encode2(TargetOpcode::G_FMINNUM_IEEE),
        GIM_CheckType, /*MI*/2, /*Op*/1, /*Type*/GILLT_s16,
        GIM_CheckType, /*MI*/2, /*Op*/2, /*Type*/GILLT_s16,
        GIM_RecordInsn, /*DefineMI*/3, /*MI*/2, /*OpIdx*/2, // MIs[3]
        GIM_CheckOpcode, /*MI*/3, GIMT_Encode2(TargetOpcode::G_FMAXNUM_IEEE),
        // MIs[3] VOP3Mods:src1:src1_mods
        GIM_CheckIsSameOperand, /*MI*/3, /*OpIdx*/1, /*OtherMI*/1, /*OtherOpIdx*/2,
        // MIs[3] VOP3Mods:src0:src0_mods
        GIM_CheckIsSameOperand, /*MI*/3, /*OpIdx*/2, /*OtherMI*/1, /*OtherOpIdx*/1,
        GIM_CheckCxxInsnPredicate, /*MI*/0, /*FnId*/GIMT_Encode2(GICXXPred_MI_Predicate_fmaxnum_like_nnan),
        GIM_CheckIsSafeToFold, /*InsnID*/1,
        GIM_CheckIsSafeToFold, /*InsnID*/2,
        GIM_CheckIsSafeToFold, /*InsnID*/3,
        GIM_CheckComplexPattern, /*MI*/1, /*Op*/1, /*Renderer*/GIMT_Encode2(0), GIMT_Encode2(GICP_gi_vop3mods),
        GIM_CheckComplexPattern, /*MI*/1, /*Op*/2, /*Renderer*/GIMT_Encode2(1), GIMT_Encode2(GICP_gi_vop3mods),
        GIM_CheckComplexPattern, /*MI*/2, /*Op*/1, /*Renderer*/GIMT_Encode2(2), GIMT_Encode2(GICP_gi_vop3mods),
        // (fmaxnum:{ *:[f16] } (fminnum_ieee:{ *:[f16] } (VOP3Mods:{ *:[f16] } f16:{ *:[f16] }:$src0, i32:{ *:[i32] }:$src0_mods), (VOP3Mods:{ *:[f16] } f16:{ *:[f16] }:$src1, i32:{ *:[i32] }:$src1_mods)), (fminnum_ieee:{ *:[f16] } (VOP3Mods:{ *:[f16] } f16:{ *:[f16] }:$src2, i32:{ *:[i32] }:$src2_mods), (fmaxnum_ieee:{ *:[f16] } (VOP3Mods:{ *:[f16] } f16:{ *:[f16] }:$src1, i32:{ *:[i32] }:$src1_mods), (VOP3Mods:{ *:[f16] } f16:{ *:[f16] }:$src0, i32:{ *:[i32] }:$src0_mods))))<<P:Predicate_fmaxnum_like_nnan>>  =>  (V_MED3_F16_e64:{ *:[f16] } ?:{ *:[i32] }:$src0_mods, ?:{ *:[f16] }:$src0, ?:{ *:[i32] }:$src1_mods, ?:{ *:[f16] }:$src1, ?:{ *:[i32] }:$src2_mods, ?:{ *:[f16] }:$src2, 0:{ *:[i1] })
        GIR_BuildMI, /*InsnID*/0, /*Opcode*/GIMT_Encode2(AMDGPU::V_MED3_F16_e64),
        GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/0, // DstI[vdst]
        GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/1, // src0_mods
        GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/0, // src0
        GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(1), /*SubOperand*/1, // src1_mods
        GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(1), /*SubOperand*/0, // src1
        GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(2), /*SubOperand*/1, // src2_mods
        GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(2), /*SubOperand*/0, // src2
        GIR_AddImm8, /*InsnID*/0, /*Imm*/0,
        GIR_AddImm8, /*InsnID*/0, /*Imm*/0,
        GIR_AddImm8, /*InsnID*/0, /*Imm*/0,
        GIR_ConstrainSelectedInstOperands, /*InsnID*/0,
        GIR_EraseFromParent, /*InsnID*/0,
        // GIR_Coverage, 10652,
        GIR_Done,
      // Label 4557: @300680
      GIM_Try, /*On fail goto*//*Label 4558*/ GIMT_Encode4(300826), // Rule ID 10655 //
        GIM_CheckFeatures, GIMT_Encode2(GIFBS_isGFX9Plus),
        GIM_CheckRegBankForClass, /*MI*/0, /*Op*/0, /*RC*/GIMT_Encode2(AMDGPU::VGPR_32RegClassID),
        GIM_RecordInsn, /*DefineMI*/1, /*MI*/0, /*OpIdx*/1, // MIs[1]
        GIM_CheckOpcode, /*MI*/1, GIMT_Encode2(TargetOpcode::G_FMINNUM_IEEE),
        GIM_CheckType, /*MI*/1, /*Op*/1, /*Type*/GILLT_s16,
        GIM_CheckType, /*MI*/1, /*Op*/2, /*Type*/GILLT_s16,
        GIM_RecordInsn, /*DefineMI*/2, /*MI*/0, /*OpIdx*/2, // MIs[2]
        GIM_CheckOpcode, /*MI*/2, GIMT_Encode2(TargetOpcode::G_FMINNUM_IEEE),
        GIM_CheckType, /*MI*/2, /*Op*/1, /*Type*/GILLT_s16,
        GIM_CheckType, /*MI*/2, /*Op*/2, /*Type*/GILLT_s16,
        GIM_RecordInsn, /*DefineMI*/3, /*MI*/2, /*OpIdx*/2, // MIs[3]
        GIM_CheckOpcode, /*MI*/3, GIMT_Encode2(TargetOpcode::G_FMAXNUM_IEEE),
        // MIs[3] VOP3Mods:src0:src0_mods
        GIM_CheckIsSameOperand, /*MI*/3, /*OpIdx*/1, /*OtherMI*/1, /*OtherOpIdx*/2,
        // MIs[3] VOP3Mods:src1:src1_mods
        GIM_CheckIsSameOperand, /*MI*/3, /*OpIdx*/2, /*OtherMI*/1, /*OtherOpIdx*/1,
        GIM_CheckCxxInsnPredicate, /*MI*/0, /*FnId*/GIMT_Encode2(GICXXPred_MI_Predicate_fmaxnum_like_nnan),
        GIM_CheckIsSafeToFold, /*InsnID*/1,
        GIM_CheckIsSafeToFold, /*InsnID*/2,
        GIM_CheckIsSafeToFold, /*InsnID*/3,
        GIM_CheckComplexPattern, /*MI*/1, /*Op*/1, /*Renderer*/GIMT_Encode2(0), GIMT_Encode2(GICP_gi_vop3mods),
        GIM_CheckComplexPattern, /*MI*/1, /*Op*/2, /*Renderer*/GIMT_Encode2(1), GIMT_Encode2(GICP_gi_vop3mods),
        GIM_CheckComplexPattern, /*MI*/2, /*Op*/1, /*Renderer*/GIMT_Encode2(2), GIMT_Encode2(GICP_gi_vop3mods),
        // (fmaxnum:{ *:[f16] } (fminnum_ieee:{ *:[f16] } (VOP3Mods:{ *:[f16] } f16:{ *:[f16] }:$src1, i32:{ *:[i32] }:$src1_mods), (VOP3Mods:{ *:[f16] } f16:{ *:[f16] }:$src0, i32:{ *:[i32] }:$src0_mods)), (fminnum_ieee:{ *:[f16] } (VOP3Mods:{ *:[f16] } f16:{ *:[f16] }:$src2, i32:{ *:[i32] }:$src2_mods), (fmaxnum_ieee:{ *:[f16] } (VOP3Mods:{ *:[f16] } f16:{ *:[f16] }:$src0, i32:{ *:[i32] }:$src0_mods), (VOP3Mods:{ *:[f16] } f16:{ *:[f16] }:$src1, i32:{ *:[i32] }:$src1_mods))))<<P:Predicate_fmaxnum_like_nnan>>  =>  (V_MED3_F16_e64:{ *:[f16] } ?:{ *:[i32] }:$src0_mods, ?:{ *:[f16] }:$src0, ?:{ *:[i32] }:$src1_mods, ?:{ *:[f16] }:$src1, ?:{ *:[i32] }:$src2_mods, ?:{ *:[f16] }:$src2, 0:{ *:[i1] })
        GIR_BuildMI, /*InsnID*/0, /*Opcode*/GIMT_Encode2(AMDGPU::V_MED3_F16_e64),
        GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/0, // DstI[vdst]
        GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(1), /*SubOperand*/1, // src0_mods
        GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(1), /*SubOperand*/0, // src0
        GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/1, // src1_mods
        GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/0, // src1
        GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(2), /*SubOperand*/1, // src2_mods
        GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(2), /*SubOperand*/0, // src2
        GIR_AddImm8, /*InsnID*/0, /*Imm*/0,
        GIR_AddImm8, /*InsnID*/0, /*Imm*/0,
        GIR_AddImm8, /*InsnID*/0, /*Imm*/0,
        GIR_ConstrainSelectedInstOperands, /*InsnID*/0,
        GIR_EraseFromParent, /*InsnID*/0,
        // GIR_Coverage, 10655,
        GIR_Done,
      // Label 4558: @300826
      GIM_Try, /*On fail goto*//*Label 4559*/ GIMT_Encode4(300972), // Rule ID 10656 //
        GIM_CheckFeatures, GIMT_Encode2(GIFBS_isGFX9Plus),
        GIM_CheckRegBankForClass, /*MI*/0, /*Op*/0, /*RC*/GIMT_Encode2(AMDGPU::VGPR_32RegClassID),
        GIM_RecordInsn, /*DefineMI*/1, /*MI*/0, /*OpIdx*/1, // MIs[1]
        GIM_CheckOpcode, /*MI*/1, GIMT_Encode2(TargetOpcode::G_FMINNUM_IEEE),
        GIM_CheckType, /*MI*/1, /*Op*/1, /*Type*/GILLT_s16,
        GIM_CheckType, /*MI*/1, /*Op*/2, /*Type*/GILLT_s16,
        GIM_RecordInsn, /*DefineMI*/2, /*MI*/0, /*OpIdx*/2, // MIs[2]
        GIM_CheckOpcode, /*MI*/2, GIMT_Encode2(TargetOpcode::G_FMINNUM_IEEE),
        GIM_CheckType, /*MI*/2, /*Op*/1, /*Type*/GILLT_s16,
        GIM_CheckType, /*MI*/2, /*Op*/2, /*Type*/GILLT_s16,
        GIM_RecordInsn, /*DefineMI*/3, /*MI*/2, /*OpIdx*/2, // MIs[3]
        GIM_CheckOpcode, /*MI*/3, GIMT_Encode2(TargetOpcode::G_FMAXNUM_IEEE),
        // MIs[3] VOP3Mods:src1:src1_mods
        GIM_CheckIsSameOperand, /*MI*/3, /*OpIdx*/1, /*OtherMI*/1, /*OtherOpIdx*/1,
        // MIs[3] VOP3Mods:src0:src0_mods
        GIM_CheckIsSameOperand, /*MI*/3, /*OpIdx*/2, /*OtherMI*/1, /*OtherOpIdx*/2,
        GIM_CheckCxxInsnPredicate, /*MI*/0, /*FnId*/GIMT_Encode2(GICXXPred_MI_Predicate_fmaxnum_like_nnan),
        GIM_CheckIsSafeToFold, /*InsnID*/1,
        GIM_CheckIsSafeToFold, /*InsnID*/2,
        GIM_CheckIsSafeToFold, /*InsnID*/3,
        GIM_CheckComplexPattern, /*MI*/1, /*Op*/1, /*Renderer*/GIMT_Encode2(0), GIMT_Encode2(GICP_gi_vop3mods),
        GIM_CheckComplexPattern, /*MI*/1, /*Op*/2, /*Renderer*/GIMT_Encode2(1), GIMT_Encode2(GICP_gi_vop3mods),
        GIM_CheckComplexPattern, /*MI*/2, /*Op*/1, /*Renderer*/GIMT_Encode2(2), GIMT_Encode2(GICP_gi_vop3mods),
        // (fmaxnum:{ *:[f16] } (fminnum_ieee:{ *:[f16] } (VOP3Mods:{ *:[f16] } f16:{ *:[f16] }:$src1, i32:{ *:[i32] }:$src1_mods), (VOP3Mods:{ *:[f16] } f16:{ *:[f16] }:$src0, i32:{ *:[i32] }:$src0_mods)), (fminnum_ieee:{ *:[f16] } (VOP3Mods:{ *:[f16] } f16:{ *:[f16] }:$src2, i32:{ *:[i32] }:$src2_mods), (fmaxnum_ieee:{ *:[f16] } (VOP3Mods:{ *:[f16] } f16:{ *:[f16] }:$src1, i32:{ *:[i32] }:$src1_mods), (VOP3Mods:{ *:[f16] } f16:{ *:[f16] }:$src0, i32:{ *:[i32] }:$src0_mods))))<<P:Predicate_fmaxnum_like_nnan>>  =>  (V_MED3_F16_e64:{ *:[f16] } ?:{ *:[i32] }:$src0_mods, ?:{ *:[f16] }:$src0, ?:{ *:[i32] }:$src1_mods, ?:{ *:[f16] }:$src1, ?:{ *:[i32] }:$src2_mods, ?:{ *:[f16] }:$src2, 0:{ *:[i1] })
        GIR_BuildMI, /*InsnID*/0, /*Opcode*/GIMT_Encode2(AMDGPU::V_MED3_F16_e64),
        GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/0, // DstI[vdst]
        GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(1), /*SubOperand*/1, // src0_mods
        GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(1), /*SubOperand*/0, // src0
        GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/1, // src1_mods
        GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/0, // src1
        GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(2), /*SubOperand*/1, // src2_mods
        GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(2), /*SubOperand*/0, // src2
        GIR_AddImm8, /*InsnID*/0, /*Imm*/0,
        GIR_AddImm8, /*InsnID*/0, /*Imm*/0,
        GIR_AddImm8, /*InsnID*/0, /*Imm*/0,
        GIR_ConstrainSelectedInstOperands, /*InsnID*/0,
        GIR_EraseFromParent, /*InsnID*/0,
        // GIR_Coverage, 10656,
        GIR_Done,
      // Label 4559: @300972
      GIM_Try, /*On fail goto*//*Label 4560*/ GIMT_Encode4(301118), // Rule ID 6545 //
        GIM_CheckFeatures, GIMT_Encode2(GIFBS_isGFX9Plus),
        GIM_CheckRegBankForClass, /*MI*/0, /*Op*/0, /*RC*/GIMT_Encode2(AMDGPU::VGPR_32RegClassID),
        GIM_RecordInsn, /*DefineMI*/1, /*MI*/0, /*OpIdx*/1, // MIs[1]
        GIM_CheckOpcode, /*MI*/1, GIMT_Encode2(TargetOpcode::G_FMINNUM_IEEE),
        GIM_CheckType, /*MI*/1, /*Op*/1, /*Type*/GILLT_s16,
        GIM_CheckType, /*MI*/1, /*Op*/2, /*Type*/GILLT_s16,
        GIM_RecordInsn, /*DefineMI*/2, /*MI*/0, /*OpIdx*/2, // MIs[2]
        GIM_CheckOpcode, /*MI*/2, GIMT_Encode2(TargetOpcode::G_FMINNUM_IEEE),
        GIM_CheckType, /*MI*/2, /*Op*/1, /*Type*/GILLT_s16,
        GIM_CheckType, /*MI*/2, /*Op*/2, /*Type*/GILLT_s16,
        GIM_RecordInsn, /*DefineMI*/3, /*MI*/2, /*OpIdx*/1, // MIs[3]
        GIM_CheckOpcode, /*MI*/3, GIMT_Encode2(TargetOpcode::G_FMAXNUM),
        // MIs[3] VOP3Mods:src0:src0_mods
        GIM_CheckIsSameOperand, /*MI*/3, /*OpIdx*/1, /*OtherMI*/1, /*OtherOpIdx*/1,
        // MIs[3] VOP3Mods:src1:src1_mods
        GIM_CheckIsSameOperand, /*MI*/3, /*OpIdx*/2, /*OtherMI*/1, /*OtherOpIdx*/2,
        GIM_CheckCxxInsnPredicate, /*MI*/0, /*FnId*/GIMT_Encode2(GICXXPred_MI_Predicate_fmaxnum_like_nnan),
        GIM_CheckIsSafeToFold, /*InsnID*/1,
        GIM_CheckIsSafeToFold, /*InsnID*/2,
        GIM_CheckIsSafeToFold, /*InsnID*/3,
        GIM_CheckComplexPattern, /*MI*/1, /*Op*/1, /*Renderer*/GIMT_Encode2(0), GIMT_Encode2(GICP_gi_vop3mods),
        GIM_CheckComplexPattern, /*MI*/1, /*Op*/2, /*Renderer*/GIMT_Encode2(1), GIMT_Encode2(GICP_gi_vop3mods),
        GIM_CheckComplexPattern, /*MI*/2, /*Op*/2, /*Renderer*/GIMT_Encode2(2), GIMT_Encode2(GICP_gi_vop3mods),
        // (fmaxnum:{ *:[f16] } (fminnum_ieee:{ *:[f16] } (VOP3Mods:{ *:[f16] } f16:{ *:[f16] }:$src0, i32:{ *:[i32] }:$src0_mods), (VOP3Mods:{ *:[f16] } f16:{ *:[f16] }:$src1, i32:{ *:[i32] }:$src1_mods)), (fminnum_ieee:{ *:[f16] } (fmaxnum:{ *:[f16] } (VOP3Mods:{ *:[f16] } f16:{ *:[f16] }:$src0, i32:{ *:[i32] }:$src0_mods), (VOP3Mods:{ *:[f16] } f16:{ *:[f16] }:$src1, i32:{ *:[i32] }:$src1_mods)), (VOP3Mods:{ *:[f16] } f16:{ *:[f16] }:$src2, i32:{ *:[i32] }:$src2_mods)))<<P:Predicate_fmaxnum_like_nnan>>  =>  (V_MED3_F16_e64:{ *:[f16] } ?:{ *:[i32] }:$src0_mods, ?:{ *:[f16] }:$src0, ?:{ *:[i32] }:$src1_mods, ?:{ *:[f16] }:$src1, ?:{ *:[i32] }:$src2_mods, ?:{ *:[f16] }:$src2, 0:{ *:[i1] })
        GIR_BuildMI, /*InsnID*/0, /*Opcode*/GIMT_Encode2(AMDGPU::V_MED3_F16_e64),
        GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/0, // DstI[vdst]
        GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/1, // src0_mods
        GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/0, // src0
        GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(1), /*SubOperand*/1, // src1_mods
        GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(1), /*SubOperand*/0, // src1
        GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(2), /*SubOperand*/1, // src2_mods
        GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(2), /*SubOperand*/0, // src2
        GIR_AddImm8, /*InsnID*/0, /*Imm*/0,
        GIR_AddImm8, /*InsnID*/0, /*Imm*/0,
        GIR_AddImm8, /*InsnID*/0, /*Imm*/0,
        GIR_ConstrainSelectedInstOperands, /*InsnID*/0,
        GIR_EraseFromParent, /*InsnID*/0,
        // GIR_Coverage, 6545,
        GIR_Done,
      // Label 4560: @301118
      GIM_Try, /*On fail goto*//*Label 4561*/ GIMT_Encode4(301264), // Rule ID 10665 //
        GIM_CheckFeatures, GIMT_Encode2(GIFBS_isGFX9Plus),
        GIM_CheckRegBankForClass, /*MI*/0, /*Op*/0, /*RC*/GIMT_Encode2(AMDGPU::VGPR_32RegClassID),
        GIM_RecordInsn, /*DefineMI*/1, /*MI*/0, /*OpIdx*/1, // MIs[1]
        GIM_CheckOpcode, /*MI*/1, GIMT_Encode2(TargetOpcode::G_FMINNUM_IEEE),
        GIM_CheckType, /*MI*/1, /*Op*/1, /*Type*/GILLT_s16,
        GIM_CheckType, /*MI*/1, /*Op*/2, /*Type*/GILLT_s16,
        GIM_RecordInsn, /*DefineMI*/2, /*MI*/0, /*OpIdx*/2, // MIs[2]
        GIM_CheckOpcode, /*MI*/2, GIMT_Encode2(TargetOpcode::G_FMINNUM_IEEE),
        GIM_CheckType, /*MI*/2, /*Op*/1, /*Type*/GILLT_s16,
        GIM_CheckType, /*MI*/2, /*Op*/2, /*Type*/GILLT_s16,
        GIM_RecordInsn, /*DefineMI*/3, /*MI*/2, /*OpIdx*/1, // MIs[3]
        GIM_CheckOpcode, /*MI*/3, GIMT_Encode2(TargetOpcode::G_FMAXNUM),
        // MIs[3] VOP3Mods:src1:src1_mods
        GIM_CheckIsSameOperand, /*MI*/3, /*OpIdx*/1, /*OtherMI*/1, /*OtherOpIdx*/2,
        // MIs[3] VOP3Mods:src0:src0_mods
        GIM_CheckIsSameOperand, /*MI*/3, /*OpIdx*/2, /*OtherMI*/1, /*OtherOpIdx*/1,
        GIM_CheckCxxInsnPredicate, /*MI*/0, /*FnId*/GIMT_Encode2(GICXXPred_MI_Predicate_fmaxnum_like_nnan),
        GIM_CheckIsSafeToFold, /*InsnID*/1,
        GIM_CheckIsSafeToFold, /*InsnID*/2,
        GIM_CheckIsSafeToFold, /*InsnID*/3,
        GIM_CheckComplexPattern, /*MI*/1, /*Op*/1, /*Renderer*/GIMT_Encode2(0), GIMT_Encode2(GICP_gi_vop3mods),
        GIM_CheckComplexPattern, /*MI*/1, /*Op*/2, /*Renderer*/GIMT_Encode2(1), GIMT_Encode2(GICP_gi_vop3mods),
        GIM_CheckComplexPattern, /*MI*/2, /*Op*/2, /*Renderer*/GIMT_Encode2(2), GIMT_Encode2(GICP_gi_vop3mods),
        // (fmaxnum:{ *:[f16] } (fminnum_ieee:{ *:[f16] } (VOP3Mods:{ *:[f16] } f16:{ *:[f16] }:$src0, i32:{ *:[i32] }:$src0_mods), (VOP3Mods:{ *:[f16] } f16:{ *:[f16] }:$src1, i32:{ *:[i32] }:$src1_mods)), (fminnum_ieee:{ *:[f16] } (fmaxnum:{ *:[f16] } (VOP3Mods:{ *:[f16] } f16:{ *:[f16] }:$src1, i32:{ *:[i32] }:$src1_mods), (VOP3Mods:{ *:[f16] } f16:{ *:[f16] }:$src0, i32:{ *:[i32] }:$src0_mods)), (VOP3Mods:{ *:[f16] } f16:{ *:[f16] }:$src2, i32:{ *:[i32] }:$src2_mods)))<<P:Predicate_fmaxnum_like_nnan>>  =>  (V_MED3_F16_e64:{ *:[f16] } ?:{ *:[i32] }:$src0_mods, ?:{ *:[f16] }:$src0, ?:{ *:[i32] }:$src1_mods, ?:{ *:[f16] }:$src1, ?:{ *:[i32] }:$src2_mods, ?:{ *:[f16] }:$src2, 0:{ *:[i1] })
        GIR_BuildMI, /*InsnID*/0, /*Opcode*/GIMT_Encode2(AMDGPU::V_MED3_F16_e64),
        GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/0, // DstI[vdst]
        GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/1, // src0_mods
        GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/0, // src0
        GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(1), /*SubOperand*/1, // src1_mods
        GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(1), /*SubOperand*/0, // src1
        GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(2), /*SubOperand*/1, // src2_mods
        GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(2), /*SubOperand*/0, // src2
        GIR_AddImm8, /*InsnID*/0, /*Imm*/0,
        GIR_AddImm8, /*InsnID*/0, /*Imm*/0,
        GIR_AddImm8, /*InsnID*/0, /*Imm*/0,
        GIR_ConstrainSelectedInstOperands, /*InsnID*/0,
        GIR_EraseFromParent, /*InsnID*/0,
        // GIR_Coverage, 10665,
        GIR_Done,
      // Label 4561: @301264
      GIM_Try, /*On fail goto*//*Label 4562*/ GIMT_Encode4(301410), // Rule ID 10668 //
        GIM_CheckFeatures, GIMT_Encode2(GIFBS_isGFX9Plus),
        GIM_CheckRegBankForClass, /*MI*/0, /*Op*/0, /*RC*/GIMT_Encode2(AMDGPU::VGPR_32RegClassID),
        GIM_RecordInsn, /*DefineMI*/1, /*MI*/0, /*OpIdx*/1, // MIs[1]
        GIM_CheckOpcode, /*MI*/1, GIMT_Encode2(TargetOpcode::G_FMINNUM_IEEE),
        GIM_CheckType, /*MI*/1, /*Op*/1, /*Type*/GILLT_s16,
        GIM_CheckType, /*MI*/1, /*Op*/2, /*Type*/GILLT_s16,
        GIM_RecordInsn, /*DefineMI*/2, /*MI*/0, /*OpIdx*/2, // MIs[2]
        GIM_CheckOpcode, /*MI*/2, GIMT_Encode2(TargetOpcode::G_FMINNUM_IEEE),
        GIM_CheckType, /*MI*/2, /*Op*/1, /*Type*/GILLT_s16,
        GIM_CheckType, /*MI*/2, /*Op*/2, /*Type*/GILLT_s16,
        GIM_RecordInsn, /*DefineMI*/3, /*MI*/2, /*OpIdx*/1, // MIs[3]
        GIM_CheckOpcode, /*MI*/3, GIMT_Encode2(TargetOpcode::G_FMAXNUM),
        // MIs[3] VOP3Mods:src0:src0_mods
        GIM_CheckIsSameOperand, /*MI*/3, /*OpIdx*/1, /*OtherMI*/1, /*OtherOpIdx*/2,
        // MIs[3] VOP3Mods:src1:src1_mods
        GIM_CheckIsSameOperand, /*MI*/3, /*OpIdx*/2, /*OtherMI*/1, /*OtherOpIdx*/1,
        GIM_CheckCxxInsnPredicate, /*MI*/0, /*FnId*/GIMT_Encode2(GICXXPred_MI_Predicate_fmaxnum_like_nnan),
        GIM_CheckIsSafeToFold, /*InsnID*/1,
        GIM_CheckIsSafeToFold, /*InsnID*/2,
        GIM_CheckIsSafeToFold, /*InsnID*/3,
        GIM_CheckComplexPattern, /*MI*/1, /*Op*/1, /*Renderer*/GIMT_Encode2(0), GIMT_Encode2(GICP_gi_vop3mods),
        GIM_CheckComplexPattern, /*MI*/1, /*Op*/2, /*Renderer*/GIMT_Encode2(1), GIMT_Encode2(GICP_gi_vop3mods),
        GIM_CheckComplexPattern, /*MI*/2, /*Op*/2, /*Renderer*/GIMT_Encode2(2), GIMT_Encode2(GICP_gi_vop3mods),
        // (fmaxnum:{ *:[f16] } (fminnum_ieee:{ *:[f16] } (VOP3Mods:{ *:[f16] } f16:{ *:[f16] }:$src1, i32:{ *:[i32] }:$src1_mods), (VOP3Mods:{ *:[f16] } f16:{ *:[f16] }:$src0, i32:{ *:[i32] }:$src0_mods)), (fminnum_ieee:{ *:[f16] } (fmaxnum:{ *:[f16] } (VOP3Mods:{ *:[f16] } f16:{ *:[f16] }:$src0, i32:{ *:[i32] }:$src0_mods), (VOP3Mods:{ *:[f16] } f16:{ *:[f16] }:$src1, i32:{ *:[i32] }:$src1_mods)), (VOP3Mods:{ *:[f16] } f16:{ *:[f16] }:$src2, i32:{ *:[i32] }:$src2_mods)))<<P:Predicate_fmaxnum_like_nnan>>  =>  (V_MED3_F16_e64:{ *:[f16] } ?:{ *:[i32] }:$src0_mods, ?:{ *:[f16] }:$src0, ?:{ *:[i32] }:$src1_mods, ?:{ *:[f16] }:$src1, ?:{ *:[i32] }:$src2_mods, ?:{ *:[f16] }:$src2, 0:{ *:[i1] })
        GIR_BuildMI, /*InsnID*/0, /*Opcode*/GIMT_Encode2(AMDGPU::V_MED3_F16_e64),
        GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/0, // DstI[vdst]
        GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(1), /*SubOperand*/1, // src0_mods
        GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(1), /*SubOperand*/0, // src0
        GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/1, // src1_mods
        GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/0, // src1
        GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(2), /*SubOperand*/1, // src2_mods
        GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(2), /*SubOperand*/0, // src2
        GIR_AddImm8, /*InsnID*/0, /*Imm*/0,
        GIR_AddImm8, /*InsnID*/0, /*Imm*/0,
        GIR_AddImm8, /*InsnID*/0, /*Imm*/0,
        GIR_ConstrainSelectedInstOperands, /*InsnID*/0,
        GIR_EraseFromParent, /*InsnID*/0,
        // GIR_Coverage, 10668,
        GIR_Done,
      // Label 4562: @301410
      GIM_Try, /*On fail goto*//*Label 4563*/ GIMT_Encode4(301556), // Rule ID 10669 //
        GIM_CheckFeatures, GIMT_Encode2(GIFBS_isGFX9Plus),
        GIM_CheckRegBankForClass, /*MI*/0, /*Op*/0, /*RC*/GIMT_Encode2(AMDGPU::VGPR_32RegClassID),
        GIM_RecordInsn, /*DefineMI*/1, /*MI*/0, /*OpIdx*/1, // MIs[1]
        GIM_CheckOpcode, /*MI*/1, GIMT_Encode2(TargetOpcode::G_FMINNUM_IEEE),
        GIM_CheckType, /*MI*/1, /*Op*/1, /*Type*/GILLT_s16,
        GIM_CheckType, /*MI*/1, /*Op*/2, /*Type*/GILLT_s16,
        GIM_RecordInsn, /*DefineMI*/2, /*MI*/0, /*OpIdx*/2, // MIs[2]
        GIM_CheckOpcode, /*MI*/2, GIMT_Encode2(TargetOpcode::G_FMINNUM_IEEE),
        GIM_CheckType, /*MI*/2, /*Op*/1, /*Type*/GILLT_s16,
        GIM_CheckType, /*MI*/2, /*Op*/2, /*Type*/GILLT_s16,
        GIM_RecordInsn, /*DefineMI*/3, /*MI*/2, /*OpIdx*/1, // MIs[3]
        GIM_CheckOpcode, /*MI*/3, GIMT_Encode2(TargetOpcode::G_FMAXNUM),
        // MIs[3] VOP3Mods:src1:src1_mods
        GIM_CheckIsSameOperand, /*MI*/3, /*OpIdx*/1, /*OtherMI*/1, /*OtherOpIdx*/1,
        // MIs[3] VOP3Mods:src0:src0_mods
        GIM_CheckIsSameOperand, /*MI*/3, /*OpIdx*/2, /*OtherMI*/1, /*OtherOpIdx*/2,
        GIM_CheckCxxInsnPredicate, /*MI*/0, /*FnId*/GIMT_Encode2(GICXXPred_MI_Predicate_fmaxnum_like_nnan),
        GIM_CheckIsSafeToFold, /*InsnID*/1,
        GIM_CheckIsSafeToFold, /*InsnID*/2,
        GIM_CheckIsSafeToFold, /*InsnID*/3,
        GIM_CheckComplexPattern, /*MI*/1, /*Op*/1, /*Renderer*/GIMT_Encode2(0), GIMT_Encode2(GICP_gi_vop3mods),
        GIM_CheckComplexPattern, /*MI*/1, /*Op*/2, /*Renderer*/GIMT_Encode2(1), GIMT_Encode2(GICP_gi_vop3mods),
        GIM_CheckComplexPattern, /*MI*/2, /*Op*/2, /*Renderer*/GIMT_Encode2(2), GIMT_Encode2(GICP_gi_vop3mods),
        // (fmaxnum:{ *:[f16] } (fminnum_ieee:{ *:[f16] } (VOP3Mods:{ *:[f16] } f16:{ *:[f16] }:$src1, i32:{ *:[i32] }:$src1_mods), (VOP3Mods:{ *:[f16] } f16:{ *:[f16] }:$src0, i32:{ *:[i32] }:$src0_mods)), (fminnum_ieee:{ *:[f16] } (fmaxnum:{ *:[f16] } (VOP3Mods:{ *:[f16] } f16:{ *:[f16] }:$src1, i32:{ *:[i32] }:$src1_mods), (VOP3Mods:{ *:[f16] } f16:{ *:[f16] }:$src0, i32:{ *:[i32] }:$src0_mods)), (VOP3Mods:{ *:[f16] } f16:{ *:[f16] }:$src2, i32:{ *:[i32] }:$src2_mods)))<<P:Predicate_fmaxnum_like_nnan>>  =>  (V_MED3_F16_e64:{ *:[f16] } ?:{ *:[i32] }:$src0_mods, ?:{ *:[f16] }:$src0, ?:{ *:[i32] }:$src1_mods, ?:{ *:[f16] }:$src1, ?:{ *:[i32] }:$src2_mods, ?:{ *:[f16] }:$src2, 0:{ *:[i1] })
        GIR_BuildMI, /*InsnID*/0, /*Opcode*/GIMT_Encode2(AMDGPU::V_MED3_F16_e64),
        GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/0, // DstI[vdst]
        GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(1), /*SubOperand*/1, // src0_mods
        GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(1), /*SubOperand*/0, // src0
        GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/1, // src1_mods
        GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/0, // src1
        GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(2), /*SubOperand*/1, // src2_mods
        GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(2), /*SubOperand*/0, // src2
        GIR_AddImm8, /*InsnID*/0, /*Imm*/0,
        GIR_AddImm8, /*InsnID*/0, /*Imm*/0,
        GIR_AddImm8, /*InsnID*/0, /*Imm*/0,
        GIR_ConstrainSelectedInstOperands, /*InsnID*/0,
        GIR_EraseFromParent, /*InsnID*/0,
        // GIR_Coverage, 10669,
        GIR_Done,
      // Label 4563: @301556
      GIM_Try, /*On fail goto*//*Label 4564*/ GIMT_Encode4(301702), // Rule ID 6544 //
        GIM_CheckFeatures, GIMT_Encode2(GIFBS_isGFX9Plus),
        GIM_CheckRegBankForClass, /*MI*/0, /*Op*/0, /*RC*/GIMT_Encode2(AMDGPU::VGPR_32RegClassID),
        GIM_RecordInsn, /*DefineMI*/1, /*MI*/0, /*OpIdx*/1, // MIs[1]
        GIM_CheckOpcode, /*MI*/1, GIMT_Encode2(TargetOpcode::G_FMINNUM_IEEE),
        GIM_CheckType, /*MI*/1, /*Op*/1, /*Type*/GILLT_s16,
        GIM_CheckType, /*MI*/1, /*Op*/2, /*Type*/GILLT_s16,
        GIM_RecordInsn, /*DefineMI*/2, /*MI*/0, /*OpIdx*/2, // MIs[2]
        GIM_CheckOpcode, /*MI*/2, GIMT_Encode2(TargetOpcode::G_FMINNUM_IEEE),
        GIM_CheckType, /*MI*/2, /*Op*/1, /*Type*/GILLT_s16,
        GIM_CheckType, /*MI*/2, /*Op*/2, /*Type*/GILLT_s16,
        GIM_RecordInsn, /*DefineMI*/3, /*MI*/2, /*OpIdx*/1, // MIs[3]
        GIM_CheckOpcode, /*MI*/3, GIMT_Encode2(TargetOpcode::G_FMAXNUM_IEEE),
        // MIs[3] VOP3Mods:src0:src0_mods
        GIM_CheckIsSameOperand, /*MI*/3, /*OpIdx*/1, /*OtherMI*/1, /*OtherOpIdx*/1,
        // MIs[3] VOP3Mods:src1:src1_mods
        GIM_CheckIsSameOperand, /*MI*/3, /*OpIdx*/2, /*OtherMI*/1, /*OtherOpIdx*/2,
        GIM_CheckCxxInsnPredicate, /*MI*/0, /*FnId*/GIMT_Encode2(GICXXPred_MI_Predicate_fmaxnum_like_nnan),
        GIM_CheckIsSafeToFold, /*InsnID*/1,
        GIM_CheckIsSafeToFold, /*InsnID*/2,
        GIM_CheckIsSafeToFold, /*InsnID*/3,
        GIM_CheckComplexPattern, /*MI*/1, /*Op*/1, /*Renderer*/GIMT_Encode2(0), GIMT_Encode2(GICP_gi_vop3mods),
        GIM_CheckComplexPattern, /*MI*/1, /*Op*/2, /*Renderer*/GIMT_Encode2(1), GIMT_Encode2(GICP_gi_vop3mods),
        GIM_CheckComplexPattern, /*MI*/2, /*Op*/2, /*Renderer*/GIMT_Encode2(2), GIMT_Encode2(GICP_gi_vop3mods),
        // (fmaxnum:{ *:[f16] } (fminnum_ieee:{ *:[f16] } (VOP3Mods:{ *:[f16] } f16:{ *:[f16] }:$src0, i32:{ *:[i32] }:$src0_mods), (VOP3Mods:{ *:[f16] } f16:{ *:[f16] }:$src1, i32:{ *:[i32] }:$src1_mods)), (fminnum_ieee:{ *:[f16] } (fmaxnum_ieee:{ *:[f16] } (VOP3Mods:{ *:[f16] } f16:{ *:[f16] }:$src0, i32:{ *:[i32] }:$src0_mods), (VOP3Mods:{ *:[f16] } f16:{ *:[f16] }:$src1, i32:{ *:[i32] }:$src1_mods)), (VOP3Mods:{ *:[f16] } f16:{ *:[f16] }:$src2, i32:{ *:[i32] }:$src2_mods)))<<P:Predicate_fmaxnum_like_nnan>>  =>  (V_MED3_F16_e64:{ *:[f16] } ?:{ *:[i32] }:$src0_mods, ?:{ *:[f16] }:$src0, ?:{ *:[i32] }:$src1_mods, ?:{ *:[f16] }:$src1, ?:{ *:[i32] }:$src2_mods, ?:{ *:[f16] }:$src2, 0:{ *:[i1] })
        GIR_BuildMI, /*InsnID*/0, /*Opcode*/GIMT_Encode2(AMDGPU::V_MED3_F16_e64),
        GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/0, // DstI[vdst]
        GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/1, // src0_mods
        GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/0, // src0
        GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(1), /*SubOperand*/1, // src1_mods
        GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(1), /*SubOperand*/0, // src1
        GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(2), /*SubOperand*/1, // src2_mods
        GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(2), /*SubOperand*/0, // src2
        GIR_AddImm8, /*InsnID*/0, /*Imm*/0,
        GIR_AddImm8, /*InsnID*/0, /*Imm*/0,
        GIR_AddImm8, /*InsnID*/0, /*Imm*/0,
        GIR_ConstrainSelectedInstOperands, /*InsnID*/0,
        GIR_EraseFromParent, /*InsnID*/0,
        // GIR_Coverage, 6544,
        GIR_Done,
      // Label 4564: @301702
      GIM_Try, /*On fail goto*//*Label 4565*/ GIMT_Encode4(301848), // Rule ID 10650 //
        GIM_CheckFeatures, GIMT_Encode2(GIFBS_isGFX9Plus),
        GIM_CheckRegBankForClass, /*MI*/0, /*Op*/0, /*RC*/GIMT_Encode2(AMDGPU::VGPR_32RegClassID),
        GIM_RecordInsn, /*DefineMI*/1, /*MI*/0, /*OpIdx*/1, // MIs[1]
        GIM_CheckOpcode, /*MI*/1, GIMT_Encode2(TargetOpcode::G_FMINNUM_IEEE),
        GIM_CheckType, /*MI*/1, /*Op*/1, /*Type*/GILLT_s16,
        GIM_CheckType, /*MI*/1, /*Op*/2, /*Type*/GILLT_s16,
        GIM_RecordInsn, /*DefineMI*/2, /*MI*/0, /*OpIdx*/2, // MIs[2]
        GIM_CheckOpcode, /*MI*/2, GIMT_Encode2(TargetOpcode::G_FMINNUM_IEEE),
        GIM_CheckType, /*MI*/2, /*Op*/1, /*Type*/GILLT_s16,
        GIM_CheckType, /*MI*/2, /*Op*/2, /*Type*/GILLT_s16,
        GIM_RecordInsn, /*DefineMI*/3, /*MI*/2, /*OpIdx*/1, // MIs[3]
        GIM_CheckOpcode, /*MI*/3, GIMT_Encode2(TargetOpcode::G_FMAXNUM_IEEE),
        // MIs[3] VOP3Mods:src1:src1_mods
        GIM_CheckIsSameOperand, /*MI*/3, /*OpIdx*/1, /*OtherMI*/1, /*OtherOpIdx*/2,
        // MIs[3] VOP3Mods:src0:src0_mods
        GIM_CheckIsSameOperand, /*MI*/3, /*OpIdx*/2, /*OtherMI*/1, /*OtherOpIdx*/1,
        GIM_CheckCxxInsnPredicate, /*MI*/0, /*FnId*/GIMT_Encode2(GICXXPred_MI_Predicate_fmaxnum_like_nnan),
        GIM_CheckIsSafeToFold, /*InsnID*/1,
        GIM_CheckIsSafeToFold, /*InsnID*/2,
        GIM_CheckIsSafeToFold, /*InsnID*/3,
        GIM_CheckComplexPattern, /*MI*/1, /*Op*/1, /*Renderer*/GIMT_Encode2(0), GIMT_Encode2(GICP_gi_vop3mods),
        GIM_CheckComplexPattern, /*MI*/1, /*Op*/2, /*Renderer*/GIMT_Encode2(1), GIMT_Encode2(GICP_gi_vop3mods),
        GIM_CheckComplexPattern, /*MI*/2, /*Op*/2, /*Renderer*/GIMT_Encode2(2), GIMT_Encode2(GICP_gi_vop3mods),
        // (fmaxnum:{ *:[f16] } (fminnum_ieee:{ *:[f16] } (VOP3Mods:{ *:[f16] } f16:{ *:[f16] }:$src0, i32:{ *:[i32] }:$src0_mods), (VOP3Mods:{ *:[f16] } f16:{ *:[f16] }:$src1, i32:{ *:[i32] }:$src1_mods)), (fminnum_ieee:{ *:[f16] } (fmaxnum_ieee:{ *:[f16] } (VOP3Mods:{ *:[f16] } f16:{ *:[f16] }:$src1, i32:{ *:[i32] }:$src1_mods), (VOP3Mods:{ *:[f16] } f16:{ *:[f16] }:$src0, i32:{ *:[i32] }:$src0_mods)), (VOP3Mods:{ *:[f16] } f16:{ *:[f16] }:$src2, i32:{ *:[i32] }:$src2_mods)))<<P:Predicate_fmaxnum_like_nnan>>  =>  (V_MED3_F16_e64:{ *:[f16] } ?:{ *:[i32] }:$src0_mods, ?:{ *:[f16] }:$src0, ?:{ *:[i32] }:$src1_mods, ?:{ *:[f16] }:$src1, ?:{ *:[i32] }:$src2_mods, ?:{ *:[f16] }:$src2, 0:{ *:[i1] })
        GIR_BuildMI, /*InsnID*/0, /*Opcode*/GIMT_Encode2(AMDGPU::V_MED3_F16_e64),
        GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/0, // DstI[vdst]
        GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/1, // src0_mods
        GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/0, // src0
        GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(1), /*SubOperand*/1, // src1_mods
        GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(1), /*SubOperand*/0, // src1
        GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(2), /*SubOperand*/1, // src2_mods
        GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(2), /*SubOperand*/0, // src2
        GIR_AddImm8, /*InsnID*/0, /*Imm*/0,
        GIR_AddImm8, /*InsnID*/0, /*Imm*/0,
        GIR_AddImm8, /*InsnID*/0, /*Imm*/0,
        GIR_ConstrainSelectedInstOperands, /*InsnID*/0,
        GIR_EraseFromParent, /*InsnID*/0,
        // GIR_Coverage, 10650,
        GIR_Done,
      // Label 4565: @301848
      GIM_Try, /*On fail goto*//*Label 4566*/ GIMT_Encode4(301994), // Rule ID 10653 //
        GIM_CheckFeatures, GIMT_Encode2(GIFBS_isGFX9Plus),
        GIM_CheckRegBankForClass, /*MI*/0, /*Op*/0, /*RC*/GIMT_Encode2(AMDGPU::VGPR_32RegClassID),
        GIM_RecordInsn, /*DefineMI*/1, /*MI*/0, /*OpIdx*/1, // MIs[1]
        GIM_CheckOpcode, /*MI*/1, GIMT_Encode2(TargetOpcode::G_FMINNUM_IEEE),
        GIM_CheckType, /*MI*/1, /*Op*/1, /*Type*/GILLT_s16,
        GIM_CheckType, /*MI*/1, /*Op*/2, /*Type*/GILLT_s16,
        GIM_RecordInsn, /*DefineMI*/2, /*MI*/0, /*OpIdx*/2, // MIs[2]
        GIM_CheckOpcode, /*MI*/2, GIMT_Encode2(TargetOpcode::G_FMINNUM_IEEE),
        GIM_CheckType, /*MI*/2, /*Op*/1, /*Type*/GILLT_s16,
        GIM_CheckType, /*MI*/2, /*Op*/2, /*Type*/GILLT_s16,
        GIM_RecordInsn, /*DefineMI*/3, /*MI*/2, /*OpIdx*/1, // MIs[3]
        GIM_CheckOpcode, /*MI*/3, GIMT_Encode2(TargetOpcode::G_FMAXNUM_IEEE),
        // MIs[3] VOP3Mods:src0:src0_mods
        GIM_CheckIsSameOperand, /*MI*/3, /*OpIdx*/1, /*OtherMI*/1, /*OtherOpIdx*/2,
        // MIs[3] VOP3Mods:src1:src1_mods
        GIM_CheckIsSameOperand, /*MI*/3, /*OpIdx*/2, /*OtherMI*/1, /*OtherOpIdx*/1,
        GIM_CheckCxxInsnPredicate, /*MI*/0, /*FnId*/GIMT_Encode2(GICXXPred_MI_Predicate_fmaxnum_like_nnan),
        GIM_CheckIsSafeToFold, /*InsnID*/1,
        GIM_CheckIsSafeToFold, /*InsnID*/2,
        GIM_CheckIsSafeToFold, /*InsnID*/3,
        GIM_CheckComplexPattern, /*MI*/1, /*Op*/1, /*Renderer*/GIMT_Encode2(0), GIMT_Encode2(GICP_gi_vop3mods),
        GIM_CheckComplexPattern, /*MI*/1, /*Op*/2, /*Renderer*/GIMT_Encode2(1), GIMT_Encode2(GICP_gi_vop3mods),
        GIM_CheckComplexPattern, /*MI*/2, /*Op*/2, /*Renderer*/GIMT_Encode2(2), GIMT_Encode2(GICP_gi_vop3mods),
        // (fmaxnum:{ *:[f16] } (fminnum_ieee:{ *:[f16] } (VOP3Mods:{ *:[f16] } f16:{ *:[f16] }:$src1, i32:{ *:[i32] }:$src1_mods), (VOP3Mods:{ *:[f16] } f16:{ *:[f16] }:$src0, i32:{ *:[i32] }:$src0_mods)), (fminnum_ieee:{ *:[f16] } (fmaxnum_ieee:{ *:[f16] } (VOP3Mods:{ *:[f16] } f16:{ *:[f16] }:$src0, i32:{ *:[i32] }:$src0_mods), (VOP3Mods:{ *:[f16] } f16:{ *:[f16] }:$src1, i32:{ *:[i32] }:$src1_mods)), (VOP3Mods:{ *:[f16] } f16:{ *:[f16] }:$src2, i32:{ *:[i32] }:$src2_mods)))<<P:Predicate_fmaxnum_like_nnan>>  =>  (V_MED3_F16_e64:{ *:[f16] } ?:{ *:[i32] }:$src0_mods, ?:{ *:[f16] }:$src0, ?:{ *:[i32] }:$src1_mods, ?:{ *:[f16] }:$src1, ?:{ *:[i32] }:$src2_mods, ?:{ *:[f16] }:$src2, 0:{ *:[i1] })
        GIR_BuildMI, /*InsnID*/0, /*Opcode*/GIMT_Encode2(AMDGPU::V_MED3_F16_e64),
        GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/0, // DstI[vdst]
        GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(1), /*SubOperand*/1, // src0_mods
        GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(1), /*SubOperand*/0, // src0
        GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/1, // src1_mods
        GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/0, // src1
        GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(2), /*SubOperand*/1, // src2_mods
        GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(2), /*SubOperand*/0, // src2
        GIR_AddImm8, /*InsnID*/0, /*Imm*/0,
        GIR_AddImm8, /*InsnID*/0, /*Imm*/0,
        GIR_AddImm8, /*InsnID*/0, /*Imm*/0,
        GIR_ConstrainSelectedInstOperands, /*InsnID*/0,
        GIR_EraseFromParent, /*InsnID*/0,
        // GIR_Coverage, 10653,
        GIR_Done,
      // Label 4566: @301994
      GIM_Try, /*On fail goto*//*Label 4567*/ GIMT_Encode4(302140), // Rule ID 10654 //
        GIM_CheckFeatures, GIMT_Encode2(GIFBS_isGFX9Plus),
        GIM_CheckRegBankForClass, /*MI*/0, /*Op*/0, /*RC*/GIMT_Encode2(AMDGPU::VGPR_32RegClassID),
        GIM_RecordInsn, /*DefineMI*/1, /*MI*/0, /*OpIdx*/1, // MIs[1]
        GIM_CheckOpcode, /*MI*/1, GIMT_Encode2(TargetOpcode::G_FMINNUM_IEEE),
        GIM_CheckType, /*MI*/1, /*Op*/1, /*Type*/GILLT_s16,
        GIM_CheckType, /*MI*/1, /*Op*/2, /*Type*/GILLT_s16,
        GIM_RecordInsn, /*DefineMI*/2, /*MI*/0, /*OpIdx*/2, // MIs[2]
        GIM_CheckOpcode, /*MI*/2, GIMT_Encode2(TargetOpcode::G_FMINNUM_IEEE),
        GIM_CheckType, /*MI*/2, /*Op*/1, /*Type*/GILLT_s16,
        GIM_CheckType, /*MI*/2, /*Op*/2, /*Type*/GILLT_s16,
        GIM_RecordInsn, /*DefineMI*/3, /*MI*/2, /*OpIdx*/1, // MIs[3]
        GIM_CheckOpcode, /*MI*/3, GIMT_Encode2(TargetOpcode::G_FMAXNUM_IEEE),
        // MIs[3] VOP3Mods:src1:src1_mods
        GIM_CheckIsSameOperand, /*MI*/3, /*OpIdx*/1, /*OtherMI*/1, /*OtherOpIdx*/1,
        // MIs[3] VOP3Mods:src0:src0_mods
        GIM_CheckIsSameOperand, /*MI*/3, /*OpIdx*/2, /*OtherMI*/1, /*OtherOpIdx*/2,
        GIM_CheckCxxInsnPredicate, /*MI*/0, /*FnId*/GIMT_Encode2(GICXXPred_MI_Predicate_fmaxnum_like_nnan),
        GIM_CheckIsSafeToFold, /*InsnID*/1,
        GIM_CheckIsSafeToFold, /*InsnID*/2,
        GIM_CheckIsSafeToFold, /*InsnID*/3,
        GIM_CheckComplexPattern, /*MI*/1, /*Op*/1, /*Renderer*/GIMT_Encode2(0), GIMT_Encode2(GICP_gi_vop3mods),
        GIM_CheckComplexPattern, /*MI*/1, /*Op*/2, /*Renderer*/GIMT_Encode2(1), GIMT_Encode2(GICP_gi_vop3mods),
        GIM_CheckComplexPattern, /*MI*/2, /*Op*/2, /*Renderer*/GIMT_Encode2(2), GIMT_Encode2(GICP_gi_vop3mods),
        // (fmaxnum:{ *:[f16] } (fminnum_ieee:{ *:[f16] } (VOP3Mods:{ *:[f16] } f16:{ *:[f16] }:$src1, i32:{ *:[i32] }:$src1_mods), (VOP3Mods:{ *:[f16] } f16:{ *:[f16] }:$src0, i32:{ *:[i32] }:$src0_mods)), (fminnum_ieee:{ *:[f16] } (fmaxnum_ieee:{ *:[f16] } (VOP3Mods:{ *:[f16] } f16:{ *:[f16] }:$src1, i32:{ *:[i32] }:$src1_mods), (VOP3Mods:{ *:[f16] } f16:{ *:[f16] }:$src0, i32:{ *:[i32] }:$src0_mods)), (VOP3Mods:{ *:[f16] } f16:{ *:[f16] }:$src2, i32:{ *:[i32] }:$src2_mods)))<<P:Predicate_fmaxnum_like_nnan>>  =>  (V_MED3_F16_e64:{ *:[f16] } ?:{ *:[i32] }:$src0_mods, ?:{ *:[f16] }:$src0, ?:{ *:[i32] }:$src1_mods, ?:{ *:[f16] }:$src1, ?:{ *:[i32] }:$src2_mods, ?:{ *:[f16] }:$src2, 0:{ *:[i1] })
        GIR_BuildMI, /*InsnID*/0, /*Opcode*/GIMT_Encode2(AMDGPU::V_MED3_F16_e64),
        GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/0, // DstI[vdst]
        GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(1), /*SubOperand*/1, // src0_mods
        GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(1), /*SubOperand*/0, // src0
        GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/1, // src1_mods
        GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/0, // src1
        GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(2), /*SubOperand*/1, // src2_mods
        GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(2), /*SubOperand*/0, // src2
        GIR_AddImm8, /*InsnID*/0, /*Imm*/0,
        GIR_AddImm8, /*InsnID*/0, /*Imm*/0,
        GIR_AddImm8, /*InsnID*/0, /*Imm*/0,
        GIR_ConstrainSelectedInstOperands, /*InsnID*/0,
        GIR_EraseFromParent, /*InsnID*/0,
        // GIR_Coverage, 10654,
        GIR_Done,
      // Label 4567: @302140
      GIM_Try, /*On fail goto*//*Label 4568*/ GIMT_Encode4(302286), // Rule ID 10736 //
        GIM_CheckFeatures, GIMT_Encode2(GIFBS_isGFX9Plus),
        GIM_CheckRegBankForClass, /*MI*/0, /*Op*/0, /*RC*/GIMT_Encode2(AMDGPU::VGPR_32RegClassID),
        GIM_RecordInsn, /*DefineMI*/1, /*MI*/0, /*OpIdx*/1, // MIs[1]
        GIM_CheckOpcode, /*MI*/1, GIMT_Encode2(TargetOpcode::G_FMINNUM_IEEE),
        GIM_CheckType, /*MI*/1, /*Op*/1, /*Type*/GILLT_s16,
        GIM_CheckType, /*MI*/1, /*Op*/2, /*Type*/GILLT_s16,
        GIM_RecordInsn, /*DefineMI*/2, /*MI*/1, /*OpIdx*/2, // MIs[2]
        GIM_CheckOpcode, /*MI*/2, GIMT_Encode2(TargetOpcode::G_FMAXNUM),
        GIM_CheckType, /*MI*/2, /*Op*/1, /*Type*/GILLT_s16,
        GIM_CheckType, /*MI*/2, /*Op*/2, /*Type*/GILLT_s16,
        GIM_RecordInsn, /*DefineMI*/3, /*MI*/0, /*OpIdx*/2, // MIs[3]
        GIM_CheckOpcode, /*MI*/3, GIMT_Encode2(TargetOpcode::G_FMINNUM),
        // MIs[3] VOP3Mods:src0:src0_mods
        GIM_CheckIsSameOperand, /*MI*/3, /*OpIdx*/1, /*OtherMI*/2, /*OtherOpIdx*/1,
        // MIs[3] VOP3Mods:src1:src1_mods
        GIM_CheckIsSameOperand, /*MI*/3, /*OpIdx*/2, /*OtherMI*/2, /*OtherOpIdx*/2,
        GIM_CheckCxxInsnPredicate, /*MI*/0, /*FnId*/GIMT_Encode2(GICXXPred_MI_Predicate_fmaxnum_like_nnan),
        GIM_CheckIsSafeToFold, /*InsnID*/1,
        GIM_CheckIsSafeToFold, /*InsnID*/2,
        GIM_CheckIsSafeToFold, /*InsnID*/3,
        GIM_CheckComplexPattern, /*MI*/1, /*Op*/1, /*Renderer*/GIMT_Encode2(0), GIMT_Encode2(GICP_gi_vop3mods),
        GIM_CheckComplexPattern, /*MI*/2, /*Op*/1, /*Renderer*/GIMT_Encode2(1), GIMT_Encode2(GICP_gi_vop3mods),
        GIM_CheckComplexPattern, /*MI*/2, /*Op*/2, /*Renderer*/GIMT_Encode2(2), GIMT_Encode2(GICP_gi_vop3mods),
        // (fmaxnum:{ *:[f16] } (fminnum_ieee:{ *:[f16] } (VOP3Mods:{ *:[f16] } f16:{ *:[f16] }:$src2, i32:{ *:[i32] }:$src2_mods), (fmaxnum:{ *:[f16] } (VOP3Mods:{ *:[f16] } f16:{ *:[f16] }:$src0, i32:{ *:[i32] }:$src0_mods), (VOP3Mods:{ *:[f16] } f16:{ *:[f16] }:$src1, i32:{ *:[i32] }:$src1_mods))), (fminnum:{ *:[f16] } (VOP3Mods:{ *:[f16] } f16:{ *:[f16] }:$src0, i32:{ *:[i32] }:$src0_mods), (VOP3Mods:{ *:[f16] } f16:{ *:[f16] }:$src1, i32:{ *:[i32] }:$src1_mods)))<<P:Predicate_fmaxnum_like_nnan>>  =>  (V_MED3_F16_e64:{ *:[f16] } ?:{ *:[i32] }:$src0_mods, ?:{ *:[f16] }:$src0, ?:{ *:[i32] }:$src1_mods, ?:{ *:[f16] }:$src1, ?:{ *:[i32] }:$src2_mods, ?:{ *:[f16] }:$src2, 0:{ *:[i1] })
        GIR_BuildMI, /*InsnID*/0, /*Opcode*/GIMT_Encode2(AMDGPU::V_MED3_F16_e64),
        GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/0, // DstI[vdst]
        GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(1), /*SubOperand*/1, // src0_mods
        GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(1), /*SubOperand*/0, // src0
        GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(2), /*SubOperand*/1, // src1_mods
        GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(2), /*SubOperand*/0, // src1
        GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/1, // src2_mods
        GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/0, // src2
        GIR_AddImm8, /*InsnID*/0, /*Imm*/0,
        GIR_AddImm8, /*InsnID*/0, /*Imm*/0,
        GIR_AddImm8, /*InsnID*/0, /*Imm*/0,
        GIR_ConstrainSelectedInstOperands, /*InsnID*/0,
        GIR_EraseFromParent, /*InsnID*/0,
        // GIR_Coverage, 10736,
        GIR_Done,
      // Label 4568: @302286
      GIM_Try, /*On fail goto*//*Label 4569*/ GIMT_Encode4(302432), // Rule ID 10737 //
        GIM_CheckFeatures, GIMT_Encode2(GIFBS_isGFX9Plus),
        GIM_CheckRegBankForClass, /*MI*/0, /*Op*/0, /*RC*/GIMT_Encode2(AMDGPU::VGPR_32RegClassID),
        GIM_RecordInsn, /*DefineMI*/1, /*MI*/0, /*OpIdx*/1, // MIs[1]
        GIM_CheckOpcode, /*MI*/1, GIMT_Encode2(TargetOpcode::G_FMINNUM_IEEE),
        GIM_CheckType, /*MI*/1, /*Op*/1, /*Type*/GILLT_s16,
        GIM_CheckType, /*MI*/1, /*Op*/2, /*Type*/GILLT_s16,
        GIM_RecordInsn, /*DefineMI*/2, /*MI*/1, /*OpIdx*/2, // MIs[2]
        GIM_CheckOpcode, /*MI*/2, GIMT_Encode2(TargetOpcode::G_FMAXNUM),
        GIM_CheckType, /*MI*/2, /*Op*/1, /*Type*/GILLT_s16,
        GIM_CheckType, /*MI*/2, /*Op*/2, /*Type*/GILLT_s16,
        GIM_RecordInsn, /*DefineMI*/3, /*MI*/0, /*OpIdx*/2, // MIs[3]
        GIM_CheckOpcode, /*MI*/3, GIMT_Encode2(TargetOpcode::G_FMINNUM),
        // MIs[3] VOP3Mods:src1:src1_mods
        GIM_CheckIsSameOperand, /*MI*/3, /*OpIdx*/1, /*OtherMI*/2, /*OtherOpIdx*/2,
        // MIs[3] VOP3Mods:src0:src0_mods
        GIM_CheckIsSameOperand, /*MI*/3, /*OpIdx*/2, /*OtherMI*/2, /*OtherOpIdx*/1,
        GIM_CheckCxxInsnPredicate, /*MI*/0, /*FnId*/GIMT_Encode2(GICXXPred_MI_Predicate_fmaxnum_like_nnan),
        GIM_CheckIsSafeToFold, /*InsnID*/1,
        GIM_CheckIsSafeToFold, /*InsnID*/2,
        GIM_CheckIsSafeToFold, /*InsnID*/3,
        GIM_CheckComplexPattern, /*MI*/1, /*Op*/1, /*Renderer*/GIMT_Encode2(0), GIMT_Encode2(GICP_gi_vop3mods),
        GIM_CheckComplexPattern, /*MI*/2, /*Op*/1, /*Renderer*/GIMT_Encode2(1), GIMT_Encode2(GICP_gi_vop3mods),
        GIM_CheckComplexPattern, /*MI*/2, /*Op*/2, /*Renderer*/GIMT_Encode2(2), GIMT_Encode2(GICP_gi_vop3mods),
        // (fmaxnum:{ *:[f16] } (fminnum_ieee:{ *:[f16] } (VOP3Mods:{ *:[f16] } f16:{ *:[f16] }:$src2, i32:{ *:[i32] }:$src2_mods), (fmaxnum:{ *:[f16] } (VOP3Mods:{ *:[f16] } f16:{ *:[f16] }:$src0, i32:{ *:[i32] }:$src0_mods), (VOP3Mods:{ *:[f16] } f16:{ *:[f16] }:$src1, i32:{ *:[i32] }:$src1_mods))), (fminnum:{ *:[f16] } (VOP3Mods:{ *:[f16] } f16:{ *:[f16] }:$src1, i32:{ *:[i32] }:$src1_mods), (VOP3Mods:{ *:[f16] } f16:{ *:[f16] }:$src0, i32:{ *:[i32] }:$src0_mods)))<<P:Predicate_fmaxnum_like_nnan>>  =>  (V_MED3_F16_e64:{ *:[f16] } ?:{ *:[i32] }:$src0_mods, ?:{ *:[f16] }:$src0, ?:{ *:[i32] }:$src1_mods, ?:{ *:[f16] }:$src1, ?:{ *:[i32] }:$src2_mods, ?:{ *:[f16] }:$src2, 0:{ *:[i1] })
        GIR_BuildMI, /*InsnID*/0, /*Opcode*/GIMT_Encode2(AMDGPU::V_MED3_F16_e64),
        GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/0, // DstI[vdst]
        GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(1), /*SubOperand*/1, // src0_mods
        GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(1), /*SubOperand*/0, // src0
        GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(2), /*SubOperand*/1, // src1_mods
        GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(2), /*SubOperand*/0, // src1
        GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/1, // src2_mods
        GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/0, // src2
        GIR_AddImm8, /*InsnID*/0, /*Imm*/0,
        GIR_AddImm8, /*InsnID*/0, /*Imm*/0,
        GIR_AddImm8, /*InsnID*/0, /*Imm*/0,
        GIR_ConstrainSelectedInstOperands, /*InsnID*/0,
        GIR_EraseFromParent, /*InsnID*/0,
        // GIR_Coverage, 10737,
        GIR_Done,
      // Label 4569: @302432
      GIM_Try, /*On fail goto*//*Label 4570*/ GIMT_Encode4(302578), // Rule ID 10738 //
        GIM_CheckFeatures, GIMT_Encode2(GIFBS_isGFX9Plus),
        GIM_CheckRegBankForClass, /*MI*/0, /*Op*/0, /*RC*/GIMT_Encode2(AMDGPU::VGPR_32RegClassID),
        GIM_RecordInsn, /*DefineMI*/1, /*MI*/0, /*OpIdx*/1, // MIs[1]
        GIM_CheckOpcode, /*MI*/1, GIMT_Encode2(TargetOpcode::G_FMINNUM_IEEE),
        GIM_CheckType, /*MI*/1, /*Op*/1, /*Type*/GILLT_s16,
        GIM_CheckType, /*MI*/1, /*Op*/2, /*Type*/GILLT_s16,
        GIM_RecordInsn, /*DefineMI*/2, /*MI*/1, /*OpIdx*/2, // MIs[2]
        GIM_CheckOpcode, /*MI*/2, GIMT_Encode2(TargetOpcode::G_FMAXNUM),
        GIM_CheckType, /*MI*/2, /*Op*/1, /*Type*/GILLT_s16,
        GIM_CheckType, /*MI*/2, /*Op*/2, /*Type*/GILLT_s16,
        GIM_RecordInsn, /*DefineMI*/3, /*MI*/0, /*OpIdx*/2, // MIs[3]
        GIM_CheckOpcode, /*MI*/3, GIMT_Encode2(TargetOpcode::G_FMINNUM),
        // MIs[3] VOP3Mods:src0:src0_mods
        GIM_CheckIsSameOperand, /*MI*/3, /*OpIdx*/1, /*OtherMI*/2, /*OtherOpIdx*/2,
        // MIs[3] VOP3Mods:src1:src1_mods
        GIM_CheckIsSameOperand, /*MI*/3, /*OpIdx*/2, /*OtherMI*/2, /*OtherOpIdx*/1,
        GIM_CheckCxxInsnPredicate, /*MI*/0, /*FnId*/GIMT_Encode2(GICXXPred_MI_Predicate_fmaxnum_like_nnan),
        GIM_CheckIsSafeToFold, /*InsnID*/1,
        GIM_CheckIsSafeToFold, /*InsnID*/2,
        GIM_CheckIsSafeToFold, /*InsnID*/3,
        GIM_CheckComplexPattern, /*MI*/1, /*Op*/1, /*Renderer*/GIMT_Encode2(0), GIMT_Encode2(GICP_gi_vop3mods),
        GIM_CheckComplexPattern, /*MI*/2, /*Op*/1, /*Renderer*/GIMT_Encode2(1), GIMT_Encode2(GICP_gi_vop3mods),
        GIM_CheckComplexPattern, /*MI*/2, /*Op*/2, /*Renderer*/GIMT_Encode2(2), GIMT_Encode2(GICP_gi_vop3mods),
        // (fmaxnum:{ *:[f16] } (fminnum_ieee:{ *:[f16] } (VOP3Mods:{ *:[f16] } f16:{ *:[f16] }:$src2, i32:{ *:[i32] }:$src2_mods), (fmaxnum:{ *:[f16] } (VOP3Mods:{ *:[f16] } f16:{ *:[f16] }:$src1, i32:{ *:[i32] }:$src1_mods), (VOP3Mods:{ *:[f16] } f16:{ *:[f16] }:$src0, i32:{ *:[i32] }:$src0_mods))), (fminnum:{ *:[f16] } (VOP3Mods:{ *:[f16] } f16:{ *:[f16] }:$src0, i32:{ *:[i32] }:$src0_mods), (VOP3Mods:{ *:[f16] } f16:{ *:[f16] }:$src1, i32:{ *:[i32] }:$src1_mods)))<<P:Predicate_fmaxnum_like_nnan>>  =>  (V_MED3_F16_e64:{ *:[f16] } ?:{ *:[i32] }:$src0_mods, ?:{ *:[f16] }:$src0, ?:{ *:[i32] }:$src1_mods, ?:{ *:[f16] }:$src1, ?:{ *:[i32] }:$src2_mods, ?:{ *:[f16] }:$src2, 0:{ *:[i1] })
        GIR_BuildMI, /*InsnID*/0, /*Opcode*/GIMT_Encode2(AMDGPU::V_MED3_F16_e64),
        GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/0, // DstI[vdst]
        GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(2), /*SubOperand*/1, // src0_mods
        GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(2), /*SubOperand*/0, // src0
        GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(1), /*SubOperand*/1, // src1_mods
        GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(1), /*SubOperand*/0, // src1
        GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/1, // src2_mods
        GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/0, // src2
        GIR_AddImm8, /*InsnID*/0, /*Imm*/0,
        GIR_AddImm8, /*InsnID*/0, /*Imm*/0,
        GIR_AddImm8, /*InsnID*/0, /*Imm*/0,
        GIR_ConstrainSelectedInstOperands, /*InsnID*/0,
        GIR_EraseFromParent, /*InsnID*/0,
        // GIR_Coverage, 10738,
        GIR_Done,
      // Label 4570: @302578
      GIM_Try, /*On fail goto*//*Label 4571*/ GIMT_Encode4(302724), // Rule ID 10739 //
        GIM_CheckFeatures, GIMT_Encode2(GIFBS_isGFX9Plus),
        GIM_CheckRegBankForClass, /*MI*/0, /*Op*/0, /*RC*/GIMT_Encode2(AMDGPU::VGPR_32RegClassID),
        GIM_RecordInsn, /*DefineMI*/1, /*MI*/0, /*OpIdx*/1, // MIs[1]
        GIM_CheckOpcode, /*MI*/1, GIMT_Encode2(TargetOpcode::G_FMINNUM_IEEE),
        GIM_CheckType, /*MI*/1, /*Op*/1, /*Type*/GILLT_s16,
        GIM_CheckType, /*MI*/1, /*Op*/2, /*Type*/GILLT_s16,
        GIM_RecordInsn, /*DefineMI*/2, /*MI*/1, /*OpIdx*/2, // MIs[2]
        GIM_CheckOpcode, /*MI*/2, GIMT_Encode2(TargetOpcode::G_FMAXNUM),
        GIM_CheckType, /*MI*/2, /*Op*/1, /*Type*/GILLT_s16,
        GIM_CheckType, /*MI*/2, /*Op*/2, /*Type*/GILLT_s16,
        GIM_RecordInsn, /*DefineMI*/3, /*MI*/0, /*OpIdx*/2, // MIs[3]
        GIM_CheckOpcode, /*MI*/3, GIMT_Encode2(TargetOpcode::G_FMINNUM),
        // MIs[3] VOP3Mods:src1:src1_mods
        GIM_CheckIsSameOperand, /*MI*/3, /*OpIdx*/1, /*OtherMI*/2, /*OtherOpIdx*/1,
        // MIs[3] VOP3Mods:src0:src0_mods
        GIM_CheckIsSameOperand, /*MI*/3, /*OpIdx*/2, /*OtherMI*/2, /*OtherOpIdx*/2,
        GIM_CheckCxxInsnPredicate, /*MI*/0, /*FnId*/GIMT_Encode2(GICXXPred_MI_Predicate_fmaxnum_like_nnan),
        GIM_CheckIsSafeToFold, /*InsnID*/1,
        GIM_CheckIsSafeToFold, /*InsnID*/2,
        GIM_CheckIsSafeToFold, /*InsnID*/3,
        GIM_CheckComplexPattern, /*MI*/1, /*Op*/1, /*Renderer*/GIMT_Encode2(0), GIMT_Encode2(GICP_gi_vop3mods),
        GIM_CheckComplexPattern, /*MI*/2, /*Op*/1, /*Renderer*/GIMT_Encode2(1), GIMT_Encode2(GICP_gi_vop3mods),
        GIM_CheckComplexPattern, /*MI*/2, /*Op*/2, /*Renderer*/GIMT_Encode2(2), GIMT_Encode2(GICP_gi_vop3mods),
        // (fmaxnum:{ *:[f16] } (fminnum_ieee:{ *:[f16] } (VOP3Mods:{ *:[f16] } f16:{ *:[f16] }:$src2, i32:{ *:[i32] }:$src2_mods), (fmaxnum:{ *:[f16] } (VOP3Mods:{ *:[f16] } f16:{ *:[f16] }:$src1, i32:{ *:[i32] }:$src1_mods), (VOP3Mods:{ *:[f16] } f16:{ *:[f16] }:$src0, i32:{ *:[i32] }:$src0_mods))), (fminnum:{ *:[f16] } (VOP3Mods:{ *:[f16] } f16:{ *:[f16] }:$src1, i32:{ *:[i32] }:$src1_mods), (VOP3Mods:{ *:[f16] } f16:{ *:[f16] }:$src0, i32:{ *:[i32] }:$src0_mods)))<<P:Predicate_fmaxnum_like_nnan>>  =>  (V_MED3_F16_e64:{ *:[f16] } ?:{ *:[i32] }:$src0_mods, ?:{ *:[f16] }:$src0, ?:{ *:[i32] }:$src1_mods, ?:{ *:[f16] }:$src1, ?:{ *:[i32] }:$src2_mods, ?:{ *:[f16] }:$src2, 0:{ *:[i1] })
        GIR_BuildMI, /*InsnID*/0, /*Opcode*/GIMT_Encode2(AMDGPU::V_MED3_F16_e64),
        GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/0, // DstI[vdst]
        GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(2), /*SubOperand*/1, // src0_mods
        GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(2), /*SubOperand*/0, // src0
        GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(1), /*SubOperand*/1, // src1_mods
        GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(1), /*SubOperand*/0, // src1
        GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/1, // src2_mods
        GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/0, // src2
        GIR_AddImm8, /*InsnID*/0, /*Imm*/0,
        GIR_AddImm8, /*InsnID*/0, /*Imm*/0,
        GIR_AddImm8, /*InsnID*/0, /*Imm*/0,
        GIR_ConstrainSelectedInstOperands, /*InsnID*/0,
        GIR_EraseFromParent, /*InsnID*/0,
        // GIR_Coverage, 10739,
        GIR_Done,
      // Label 4571: @302724
      GIM_Try, /*On fail goto*//*Label 4572*/ GIMT_Encode4(302870), // Rule ID 10676 //
        GIM_CheckFeatures, GIMT_Encode2(GIFBS_isGFX9Plus),
        GIM_CheckRegBankForClass, /*MI*/0, /*Op*/0, /*RC*/GIMT_Encode2(AMDGPU::VGPR_32RegClassID),
        GIM_RecordInsn, /*DefineMI*/1, /*MI*/0, /*OpIdx*/1, // MIs[1]
        GIM_CheckOpcode, /*MI*/1, GIMT_Encode2(TargetOpcode::G_FMINNUM_IEEE),
        GIM_CheckType, /*MI*/1, /*Op*/1, /*Type*/GILLT_s16,
        GIM_CheckType, /*MI*/1, /*Op*/2, /*Type*/GILLT_s16,
        GIM_RecordInsn, /*DefineMI*/2, /*MI*/1, /*OpIdx*/2, // MIs[2]
        GIM_CheckOpcode, /*MI*/2, GIMT_Encode2(TargetOpcode::G_FMAXNUM),
        GIM_CheckType, /*MI*/2, /*Op*/1, /*Type*/GILLT_s16,
        GIM_CheckType, /*MI*/2, /*Op*/2, /*Type*/GILLT_s16,
        GIM_RecordInsn, /*DefineMI*/3, /*MI*/0, /*OpIdx*/2, // MIs[3]
        GIM_CheckOpcode, /*MI*/3, GIMT_Encode2(TargetOpcode::G_FMINNUM_IEEE),
        // MIs[3] VOP3Mods:src0:src0_mods
        GIM_CheckIsSameOperand, /*MI*/3, /*OpIdx*/1, /*OtherMI*/2, /*OtherOpIdx*/1,
        // MIs[3] VOP3Mods:src1:src1_mods
        GIM_CheckIsSameOperand, /*MI*/3, /*OpIdx*/2, /*OtherMI*/2, /*OtherOpIdx*/2,
        GIM_CheckCxxInsnPredicate, /*MI*/0, /*FnId*/GIMT_Encode2(GICXXPred_MI_Predicate_fmaxnum_like_nnan),
        GIM_CheckIsSafeToFold, /*InsnID*/1,
        GIM_CheckIsSafeToFold, /*InsnID*/2,
        GIM_CheckIsSafeToFold, /*InsnID*/3,
        GIM_CheckComplexPattern, /*MI*/1, /*Op*/1, /*Renderer*/GIMT_Encode2(0), GIMT_Encode2(GICP_gi_vop3mods),
        GIM_CheckComplexPattern, /*MI*/2, /*Op*/1, /*Renderer*/GIMT_Encode2(1), GIMT_Encode2(GICP_gi_vop3mods),
        GIM_CheckComplexPattern, /*MI*/2, /*Op*/2, /*Renderer*/GIMT_Encode2(2), GIMT_Encode2(GICP_gi_vop3mods),
        // (fmaxnum:{ *:[f16] } (fminnum_ieee:{ *:[f16] } (VOP3Mods:{ *:[f16] } f16:{ *:[f16] }:$src2, i32:{ *:[i32] }:$src2_mods), (fmaxnum:{ *:[f16] } (VOP3Mods:{ *:[f16] } f16:{ *:[f16] }:$src0, i32:{ *:[i32] }:$src0_mods), (VOP3Mods:{ *:[f16] } f16:{ *:[f16] }:$src1, i32:{ *:[i32] }:$src1_mods))), (fminnum_ieee:{ *:[f16] } (VOP3Mods:{ *:[f16] } f16:{ *:[f16] }:$src0, i32:{ *:[i32] }:$src0_mods), (VOP3Mods:{ *:[f16] } f16:{ *:[f16] }:$src1, i32:{ *:[i32] }:$src1_mods)))<<P:Predicate_fmaxnum_like_nnan>>  =>  (V_MED3_F16_e64:{ *:[f16] } ?:{ *:[i32] }:$src0_mods, ?:{ *:[f16] }:$src0, ?:{ *:[i32] }:$src1_mods, ?:{ *:[f16] }:$src1, ?:{ *:[i32] }:$src2_mods, ?:{ *:[f16] }:$src2, 0:{ *:[i1] })
        GIR_BuildMI, /*InsnID*/0, /*Opcode*/GIMT_Encode2(AMDGPU::V_MED3_F16_e64),
        GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/0, // DstI[vdst]
        GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(1), /*SubOperand*/1, // src0_mods
        GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(1), /*SubOperand*/0, // src0
        GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(2), /*SubOperand*/1, // src1_mods
        GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(2), /*SubOperand*/0, // src1
        GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/1, // src2_mods
        GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/0, // src2
        GIR_AddImm8, /*InsnID*/0, /*Imm*/0,
        GIR_AddImm8, /*InsnID*/0, /*Imm*/0,
        GIR_AddImm8, /*InsnID*/0, /*Imm*/0,
        GIR_ConstrainSelectedInstOperands, /*InsnID*/0,
        GIR_EraseFromParent, /*InsnID*/0,
        // GIR_Coverage, 10676,
        GIR_Done,
      // Label 4572: @302870
      GIM_Try, /*On fail goto*//*Label 4573*/ GIMT_Encode4(303016), // Rule ID 10677 //
        GIM_CheckFeatures, GIMT_Encode2(GIFBS_isGFX9Plus),
        GIM_CheckRegBankForClass, /*MI*/0, /*Op*/0, /*RC*/GIMT_Encode2(AMDGPU::VGPR_32RegClassID),
        GIM_RecordInsn, /*DefineMI*/1, /*MI*/0, /*OpIdx*/1, // MIs[1]
        GIM_CheckOpcode, /*MI*/1, GIMT_Encode2(TargetOpcode::G_FMINNUM_IEEE),
        GIM_CheckType, /*MI*/1, /*Op*/1, /*Type*/GILLT_s16,
        GIM_CheckType, /*MI*/1, /*Op*/2, /*Type*/GILLT_s16,
        GIM_RecordInsn, /*DefineMI*/2, /*MI*/1, /*OpIdx*/2, // MIs[2]
        GIM_CheckOpcode, /*MI*/2, GIMT_Encode2(TargetOpcode::G_FMAXNUM),
        GIM_CheckType, /*MI*/2, /*Op*/1, /*Type*/GILLT_s16,
        GIM_CheckType, /*MI*/2, /*Op*/2, /*Type*/GILLT_s16,
        GIM_RecordInsn, /*DefineMI*/3, /*MI*/0, /*OpIdx*/2, // MIs[3]
        GIM_CheckOpcode, /*MI*/3, GIMT_Encode2(TargetOpcode::G_FMINNUM_IEEE),
        // MIs[3] VOP3Mods:src1:src1_mods
        GIM_CheckIsSameOperand, /*MI*/3, /*OpIdx*/1, /*OtherMI*/2, /*OtherOpIdx*/2,
        // MIs[3] VOP3Mods:src0:src0_mods
        GIM_CheckIsSameOperand, /*MI*/3, /*OpIdx*/2, /*OtherMI*/2, /*OtherOpIdx*/1,
        GIM_CheckCxxInsnPredicate, /*MI*/0, /*FnId*/GIMT_Encode2(GICXXPred_MI_Predicate_fmaxnum_like_nnan),
        GIM_CheckIsSafeToFold, /*InsnID*/1,
        GIM_CheckIsSafeToFold, /*InsnID*/2,
        GIM_CheckIsSafeToFold, /*InsnID*/3,
        GIM_CheckComplexPattern, /*MI*/1, /*Op*/1, /*Renderer*/GIMT_Encode2(0), GIMT_Encode2(GICP_gi_vop3mods),
        GIM_CheckComplexPattern, /*MI*/2, /*Op*/1, /*Renderer*/GIMT_Encode2(1), GIMT_Encode2(GICP_gi_vop3mods),
        GIM_CheckComplexPattern, /*MI*/2, /*Op*/2, /*Renderer*/GIMT_Encode2(2), GIMT_Encode2(GICP_gi_vop3mods),
        // (fmaxnum:{ *:[f16] } (fminnum_ieee:{ *:[f16] } (VOP3Mods:{ *:[f16] } f16:{ *:[f16] }:$src2, i32:{ *:[i32] }:$src2_mods), (fmaxnum:{ *:[f16] } (VOP3Mods:{ *:[f16] } f16:{ *:[f16] }:$src0, i32:{ *:[i32] }:$src0_mods), (VOP3Mods:{ *:[f16] } f16:{ *:[f16] }:$src1, i32:{ *:[i32] }:$src1_mods))), (fminnum_ieee:{ *:[f16] } (VOP3Mods:{ *:[f16] } f16:{ *:[f16] }:$src1, i32:{ *:[i32] }:$src1_mods), (VOP3Mods:{ *:[f16] } f16:{ *:[f16] }:$src0, i32:{ *:[i32] }:$src0_mods)))<<P:Predicate_fmaxnum_like_nnan>>  =>  (V_MED3_F16_e64:{ *:[f16] } ?:{ *:[i32] }:$src0_mods, ?:{ *:[f16] }:$src0, ?:{ *:[i32] }:$src1_mods, ?:{ *:[f16] }:$src1, ?:{ *:[i32] }:$src2_mods, ?:{ *:[f16] }:$src2, 0:{ *:[i1] })
        GIR_BuildMI, /*InsnID*/0, /*Opcode*/GIMT_Encode2(AMDGPU::V_MED3_F16_e64),
        GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/0, // DstI[vdst]
        GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(1), /*SubOperand*/1, // src0_mods
        GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(1), /*SubOperand*/0, // src0
        GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(2), /*SubOperand*/1, // src1_mods
        GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(2), /*SubOperand*/0, // src1
        GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/1, // src2_mods
        GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/0, // src2
        GIR_AddImm8, /*InsnID*/0, /*Imm*/0,
        GIR_AddImm8, /*InsnID*/0, /*Imm*/0,
        GIR_AddImm8, /*InsnID*/0, /*Imm*/0,
        GIR_ConstrainSelectedInstOperands, /*InsnID*/0,
        GIR_EraseFromParent, /*InsnID*/0,
        // GIR_Coverage, 10677,
        GIR_Done,
      // Label 4573: @303016
      GIM_Try, /*On fail goto*//*Label 4574*/ GIMT_Encode4(303162), // Rule ID 10678 //
        GIM_CheckFeatures, GIMT_Encode2(GIFBS_isGFX9Plus),
        GIM_CheckRegBankForClass, /*MI*/0, /*Op*/0, /*RC*/GIMT_Encode2(AMDGPU::VGPR_32RegClassID),
        GIM_RecordInsn, /*DefineMI*/1, /*MI*/0, /*OpIdx*/1, // MIs[1]
        GIM_CheckOpcode, /*MI*/1, GIMT_Encode2(TargetOpcode::G_FMINNUM_IEEE),
        GIM_CheckType, /*MI*/1, /*Op*/1, /*Type*/GILLT_s16,
        GIM_CheckType, /*MI*/1, /*Op*/2, /*Type*/GILLT_s16,
        GIM_RecordInsn, /*DefineMI*/2, /*MI*/1, /*OpIdx*/2, // MIs[2]
        GIM_CheckOpcode, /*MI*/2, GIMT_Encode2(TargetOpcode::G_FMAXNUM),
        GIM_CheckType, /*MI*/2, /*Op*/1, /*Type*/GILLT_s16,
        GIM_CheckType, /*MI*/2, /*Op*/2, /*Type*/GILLT_s16,
        GIM_RecordInsn, /*DefineMI*/3, /*MI*/0, /*OpIdx*/2, // MIs[3]
        GIM_CheckOpcode, /*MI*/3, GIMT_Encode2(TargetOpcode::G_FMINNUM_IEEE),
        // MIs[3] VOP3Mods:src0:src0_mods
        GIM_CheckIsSameOperand, /*MI*/3, /*OpIdx*/1, /*OtherMI*/2, /*OtherOpIdx*/2,
        // MIs[3] VOP3Mods:src1:src1_mods
        GIM_CheckIsSameOperand, /*MI*/3, /*OpIdx*/2, /*OtherMI*/2, /*OtherOpIdx*/1,
        GIM_CheckCxxInsnPredicate, /*MI*/0, /*FnId*/GIMT_Encode2(GICXXPred_MI_Predicate_fmaxnum_like_nnan),
        GIM_CheckIsSafeToFold, /*InsnID*/1,
        GIM_CheckIsSafeToFold, /*InsnID*/2,
        GIM_CheckIsSafeToFold, /*InsnID*/3,
        GIM_CheckComplexPattern, /*MI*/1, /*Op*/1, /*Renderer*/GIMT_Encode2(0), GIMT_Encode2(GICP_gi_vop3mods),
        GIM_CheckComplexPattern, /*MI*/2, /*Op*/1, /*Renderer*/GIMT_Encode2(1), GIMT_Encode2(GICP_gi_vop3mods),
        GIM_CheckComplexPattern, /*MI*/2, /*Op*/2, /*Renderer*/GIMT_Encode2(2), GIMT_Encode2(GICP_gi_vop3mods),
        // (fmaxnum:{ *:[f16] } (fminnum_ieee:{ *:[f16] } (VOP3Mods:{ *:[f16] } f16:{ *:[f16] }:$src2, i32:{ *:[i32] }:$src2_mods), (fmaxnum:{ *:[f16] } (VOP3Mods:{ *:[f16] } f16:{ *:[f16] }:$src1, i32:{ *:[i32] }:$src1_mods), (VOP3Mods:{ *:[f16] } f16:{ *:[f16] }:$src0, i32:{ *:[i32] }:$src0_mods))), (fminnum_ieee:{ *:[f16] } (VOP3Mods:{ *:[f16] } f16:{ *:[f16] }:$src0, i32:{ *:[i32] }:$src0_mods), (VOP3Mods:{ *:[f16] } f16:{ *:[f16] }:$src1, i32:{ *:[i32] }:$src1_mods)))<<P:Predicate_fmaxnum_like_nnan>>  =>  (V_MED3_F16_e64:{ *:[f16] } ?:{ *:[i32] }:$src0_mods, ?:{ *:[f16] }:$src0, ?:{ *:[i32] }:$src1_mods, ?:{ *:[f16] }:$src1, ?:{ *:[i32] }:$src2_mods, ?:{ *:[f16] }:$src2, 0:{ *:[i1] })
        GIR_BuildMI, /*InsnID*/0, /*Opcode*/GIMT_Encode2(AMDGPU::V_MED3_F16_e64),
        GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/0, // DstI[vdst]
        GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(2), /*SubOperand*/1, // src0_mods
        GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(2), /*SubOperand*/0, // src0
        GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(1), /*SubOperand*/1, // src1_mods
        GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(1), /*SubOperand*/0, // src1
        GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/1, // src2_mods
        GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/0, // src2
        GIR_AddImm8, /*InsnID*/0, /*Imm*/0,
        GIR_AddImm8, /*InsnID*/0, /*Imm*/0,
        GIR_AddImm8, /*InsnID*/0, /*Imm*/0,
        GIR_ConstrainSelectedInstOperands, /*InsnID*/0,
        GIR_EraseFromParent, /*InsnID*/0,
        // GIR_Coverage, 10678,
        GIR_Done,
      // Label 4574: @303162
      GIM_Try, /*On fail goto*//*Label 4575*/ GIMT_Encode4(303308), // Rule ID 10679 //
        GIM_CheckFeatures, GIMT_Encode2(GIFBS_isGFX9Plus),
        GIM_CheckRegBankForClass, /*MI*/0, /*Op*/0, /*RC*/GIMT_Encode2(AMDGPU::VGPR_32RegClassID),
        GIM_RecordInsn, /*DefineMI*/1, /*MI*/0, /*OpIdx*/1, // MIs[1]
        GIM_CheckOpcode, /*MI*/1, GIMT_Encode2(TargetOpcode::G_FMINNUM_IEEE),
        GIM_CheckType, /*MI*/1, /*Op*/1, /*Type*/GILLT_s16,
        GIM_CheckType, /*MI*/1, /*Op*/2, /*Type*/GILLT_s16,
        GIM_RecordInsn, /*DefineMI*/2, /*MI*/1, /*OpIdx*/2, // MIs[2]
        GIM_CheckOpcode, /*MI*/2, GIMT_Encode2(TargetOpcode::G_FMAXNUM),
        GIM_CheckType, /*MI*/2, /*Op*/1, /*Type*/GILLT_s16,
        GIM_CheckType, /*MI*/2, /*Op*/2, /*Type*/GILLT_s16,
        GIM_RecordInsn, /*DefineMI*/3, /*MI*/0, /*OpIdx*/2, // MIs[3]
        GIM_CheckOpcode, /*MI*/3, GIMT_Encode2(TargetOpcode::G_FMINNUM_IEEE),
        // MIs[3] VOP3Mods:src1:src1_mods
        GIM_CheckIsSameOperand, /*MI*/3, /*OpIdx*/1, /*OtherMI*/2, /*OtherOpIdx*/1,
        // MIs[3] VOP3Mods:src0:src0_mods
        GIM_CheckIsSameOperand, /*MI*/3, /*OpIdx*/2, /*OtherMI*/2, /*OtherOpIdx*/2,
        GIM_CheckCxxInsnPredicate, /*MI*/0, /*FnId*/GIMT_Encode2(GICXXPred_MI_Predicate_fmaxnum_like_nnan),
        GIM_CheckIsSafeToFold, /*InsnID*/1,
        GIM_CheckIsSafeToFold, /*InsnID*/2,
        GIM_CheckIsSafeToFold, /*InsnID*/3,
        GIM_CheckComplexPattern, /*MI*/1, /*Op*/1, /*Renderer*/GIMT_Encode2(0), GIMT_Encode2(GICP_gi_vop3mods),
        GIM_CheckComplexPattern, /*MI*/2, /*Op*/1, /*Renderer*/GIMT_Encode2(1), GIMT_Encode2(GICP_gi_vop3mods),
        GIM_CheckComplexPattern, /*MI*/2, /*Op*/2, /*Renderer*/GIMT_Encode2(2), GIMT_Encode2(GICP_gi_vop3mods),
        // (fmaxnum:{ *:[f16] } (fminnum_ieee:{ *:[f16] } (VOP3Mods:{ *:[f16] } f16:{ *:[f16] }:$src2, i32:{ *:[i32] }:$src2_mods), (fmaxnum:{ *:[f16] } (VOP3Mods:{ *:[f16] } f16:{ *:[f16] }:$src1, i32:{ *:[i32] }:$src1_mods), (VOP3Mods:{ *:[f16] } f16:{ *:[f16] }:$src0, i32:{ *:[i32] }:$src0_mods))), (fminnum_ieee:{ *:[f16] } (VOP3Mods:{ *:[f16] } f16:{ *:[f16] }:$src1, i32:{ *:[i32] }:$src1_mods), (VOP3Mods:{ *:[f16] } f16:{ *:[f16] }:$src0, i32:{ *:[i32] }:$src0_mods)))<<P:Predicate_fmaxnum_like_nnan>>  =>  (V_MED3_F16_e64:{ *:[f16] } ?:{ *:[i32] }:$src0_mods, ?:{ *:[f16] }:$src0, ?:{ *:[i32] }:$src1_mods, ?:{ *:[f16] }:$src1, ?:{ *:[i32] }:$src2_mods, ?:{ *:[f16] }:$src2, 0:{ *:[i1] })
        GIR_BuildMI, /*InsnID*/0, /*Opcode*/GIMT_Encode2(AMDGPU::V_MED3_F16_e64),
        GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/0, // DstI[vdst]
        GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(2), /*SubOperand*/1, // src0_mods
        GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(2), /*SubOperand*/0, // src0
        GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(1), /*SubOperand*/1, // src1_mods
        GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(1), /*SubOperand*/0, // src1
        GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/1, // src2_mods
        GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/0, // src2
        GIR_AddImm8, /*InsnID*/0, /*Imm*/0,
        GIR_AddImm8, /*InsnID*/0, /*Imm*/0,
        GIR_AddImm8, /*InsnID*/0, /*Imm*/0,
        GIR_ConstrainSelectedInstOperands, /*InsnID*/0,
        GIR_EraseFromParent, /*InsnID*/0,
        // GIR_Coverage, 10679,
        GIR_Done,
      // Label 4575: @303308
      GIM_Try, /*On fail goto*//*Label 4576*/ GIMT_Encode4(303454), // Rule ID 10721 //
        GIM_CheckFeatures, GIMT_Encode2(GIFBS_isGFX9Plus),
        GIM_CheckRegBankForClass, /*MI*/0, /*Op*/0, /*RC*/GIMT_Encode2(AMDGPU::VGPR_32RegClassID),
        GIM_RecordInsn, /*DefineMI*/1, /*MI*/0, /*OpIdx*/1, // MIs[1]
        GIM_CheckOpcode, /*MI*/1, GIMT_Encode2(TargetOpcode::G_FMINNUM_IEEE),
        GIM_CheckType, /*MI*/1, /*Op*/1, /*Type*/GILLT_s16,
        GIM_CheckType, /*MI*/1, /*Op*/2, /*Type*/GILLT_s16,
        GIM_RecordInsn, /*DefineMI*/2, /*MI*/1, /*OpIdx*/2, // MIs[2]
        GIM_CheckOpcode, /*MI*/2, GIMT_Encode2(TargetOpcode::G_FMAXNUM_IEEE),
        GIM_CheckType, /*MI*/2, /*Op*/1, /*Type*/GILLT_s16,
        GIM_CheckType, /*MI*/2, /*Op*/2, /*Type*/GILLT_s16,
        GIM_RecordInsn, /*DefineMI*/3, /*MI*/0, /*OpIdx*/2, // MIs[3]
        GIM_CheckOpcode, /*MI*/3, GIMT_Encode2(TargetOpcode::G_FMINNUM),
        // MIs[3] VOP3Mods:src0:src0_mods
        GIM_CheckIsSameOperand, /*MI*/3, /*OpIdx*/1, /*OtherMI*/2, /*OtherOpIdx*/1,
        // MIs[3] VOP3Mods:src1:src1_mods
        GIM_CheckIsSameOperand, /*MI*/3, /*OpIdx*/2, /*OtherMI*/2, /*OtherOpIdx*/2,
        GIM_CheckCxxInsnPredicate, /*MI*/0, /*FnId*/GIMT_Encode2(GICXXPred_MI_Predicate_fmaxnum_like_nnan),
        GIM_CheckIsSafeToFold, /*InsnID*/1,
        GIM_CheckIsSafeToFold, /*InsnID*/2,
        GIM_CheckIsSafeToFold, /*InsnID*/3,
        GIM_CheckComplexPattern, /*MI*/1, /*Op*/1, /*Renderer*/GIMT_Encode2(0), GIMT_Encode2(GICP_gi_vop3mods),
        GIM_CheckComplexPattern, /*MI*/2, /*Op*/1, /*Renderer*/GIMT_Encode2(1), GIMT_Encode2(GICP_gi_vop3mods),
        GIM_CheckComplexPattern, /*MI*/2, /*Op*/2, /*Renderer*/GIMT_Encode2(2), GIMT_Encode2(GICP_gi_vop3mods),
        // (fmaxnum:{ *:[f16] } (fminnum_ieee:{ *:[f16] } (VOP3Mods:{ *:[f16] } f16:{ *:[f16] }:$src2, i32:{ *:[i32] }:$src2_mods), (fmaxnum_ieee:{ *:[f16] } (VOP3Mods:{ *:[f16] } f16:{ *:[f16] }:$src0, i32:{ *:[i32] }:$src0_mods), (VOP3Mods:{ *:[f16] } f16:{ *:[f16] }:$src1, i32:{ *:[i32] }:$src1_mods))), (fminnum:{ *:[f16] } (VOP3Mods:{ *:[f16] } f16:{ *:[f16] }:$src0, i32:{ *:[i32] }:$src0_mods), (VOP3Mods:{ *:[f16] } f16:{ *:[f16] }:$src1, i32:{ *:[i32] }:$src1_mods)))<<P:Predicate_fmaxnum_like_nnan>>  =>  (V_MED3_F16_e64:{ *:[f16] } ?:{ *:[i32] }:$src0_mods, ?:{ *:[f16] }:$src0, ?:{ *:[i32] }:$src1_mods, ?:{ *:[f16] }:$src1, ?:{ *:[i32] }:$src2_mods, ?:{ *:[f16] }:$src2, 0:{ *:[i1] })
        GIR_BuildMI, /*InsnID*/0, /*Opcode*/GIMT_Encode2(AMDGPU::V_MED3_F16_e64),
        GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/0, // DstI[vdst]
        GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(1), /*SubOperand*/1, // src0_mods
        GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(1), /*SubOperand*/0, // src0
        GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(2), /*SubOperand*/1, // src1_mods
        GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(2), /*SubOperand*/0, // src1
        GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/1, // src2_mods
        GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/0, // src2
        GIR_AddImm8, /*InsnID*/0, /*Imm*/0,
        GIR_AddImm8, /*InsnID*/0, /*Imm*/0,
        GIR_AddImm8, /*InsnID*/0, /*Imm*/0,
        GIR_ConstrainSelectedInstOperands, /*InsnID*/0,
        GIR_EraseFromParent, /*InsnID*/0,
        // GIR_Coverage, 10721,
        GIR_Done,
      // Label 4576: @303454
      GIM_Try, /*On fail goto*//*Label 4577*/ GIMT_Encode4(303600), // Rule ID 10722 //
        GIM_CheckFeatures, GIMT_Encode2(GIFBS_isGFX9Plus),
        GIM_CheckRegBankForClass, /*MI*/0, /*Op*/0, /*RC*/GIMT_Encode2(AMDGPU::VGPR_32RegClassID),
        GIM_RecordInsn, /*DefineMI*/1, /*MI*/0, /*OpIdx*/1, // MIs[1]
        GIM_CheckOpcode, /*MI*/1, GIMT_Encode2(TargetOpcode::G_FMINNUM_IEEE),
        GIM_CheckType, /*MI*/1, /*Op*/1, /*Type*/GILLT_s16,
        GIM_CheckType, /*MI*/1, /*Op*/2, /*Type*/GILLT_s16,
        GIM_RecordInsn, /*DefineMI*/2, /*MI*/1, /*OpIdx*/2, // MIs[2]
        GIM_CheckOpcode, /*MI*/2, GIMT_Encode2(TargetOpcode::G_FMAXNUM_IEEE),
        GIM_CheckType, /*MI*/2, /*Op*/1, /*Type*/GILLT_s16,
        GIM_CheckType, /*MI*/2, /*Op*/2, /*Type*/GILLT_s16,
        GIM_RecordInsn, /*DefineMI*/3, /*MI*/0, /*OpIdx*/2, // MIs[3]
        GIM_CheckOpcode, /*MI*/3, GIMT_Encode2(TargetOpcode::G_FMINNUM),
        // MIs[3] VOP3Mods:src1:src1_mods
        GIM_CheckIsSameOperand, /*MI*/3, /*OpIdx*/1, /*OtherMI*/2, /*OtherOpIdx*/2,
        // MIs[3] VOP3Mods:src0:src0_mods
        GIM_CheckIsSameOperand, /*MI*/3, /*OpIdx*/2, /*OtherMI*/2, /*OtherOpIdx*/1,
        GIM_CheckCxxInsnPredicate, /*MI*/0, /*FnId*/GIMT_Encode2(GICXXPred_MI_Predicate_fmaxnum_like_nnan),
        GIM_CheckIsSafeToFold, /*InsnID*/1,
        GIM_CheckIsSafeToFold, /*InsnID*/2,
        GIM_CheckIsSafeToFold, /*InsnID*/3,
        GIM_CheckComplexPattern, /*MI*/1, /*Op*/1, /*Renderer*/GIMT_Encode2(0), GIMT_Encode2(GICP_gi_vop3mods),
        GIM_CheckComplexPattern, /*MI*/2, /*Op*/1, /*Renderer*/GIMT_Encode2(1), GIMT_Encode2(GICP_gi_vop3mods),
        GIM_CheckComplexPattern, /*MI*/2, /*Op*/2, /*Renderer*/GIMT_Encode2(2), GIMT_Encode2(GICP_gi_vop3mods),
        // (fmaxnum:{ *:[f16] } (fminnum_ieee:{ *:[f16] } (VOP3Mods:{ *:[f16] } f16:{ *:[f16] }:$src2, i32:{ *:[i32] }:$src2_mods), (fmaxnum_ieee:{ *:[f16] } (VOP3Mods:{ *:[f16] } f16:{ *:[f16] }:$src0, i32:{ *:[i32] }:$src0_mods), (VOP3Mods:{ *:[f16] } f16:{ *:[f16] }:$src1, i32:{ *:[i32] }:$src1_mods))), (fminnum:{ *:[f16] } (VOP3Mods:{ *:[f16] } f16:{ *:[f16] }:$src1, i32:{ *:[i32] }:$src1_mods), (VOP3Mods:{ *:[f16] } f16:{ *:[f16] }:$src0, i32:{ *:[i32] }:$src0_mods)))<<P:Predicate_fmaxnum_like_nnan>>  =>  (V_MED3_F16_e64:{ *:[f16] } ?:{ *:[i32] }:$src0_mods, ?:{ *:[f16] }:$src0, ?:{ *:[i32] }:$src1_mods, ?:{ *:[f16] }:$src1, ?:{ *:[i32] }:$src2_mods, ?:{ *:[f16] }:$src2, 0:{ *:[i1] })
        GIR_BuildMI, /*InsnID*/0, /*Opcode*/GIMT_Encode2(AMDGPU::V_MED3_F16_e64),
        GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/0, // DstI[vdst]
        GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(1), /*SubOperand*/1, // src0_mods
        GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(1), /*SubOperand*/0, // src0
        GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(2), /*SubOperand*/1, // src1_mods
        GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(2), /*SubOperand*/0, // src1
        GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/1, // src2_mods
        GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/0, // src2
        GIR_AddImm8, /*InsnID*/0, /*Imm*/0,
        GIR_AddImm8, /*InsnID*/0, /*Imm*/0,
        GIR_AddImm8, /*InsnID*/0, /*Imm*/0,
        GIR_ConstrainSelectedInstOperands, /*InsnID*/0,
        GIR_EraseFromParent, /*InsnID*/0,
        // GIR_Coverage, 10722,
        GIR_Done,
      // Label 4577: @303600
      GIM_Try, /*On fail goto*//*Label 4578*/ GIMT_Encode4(303746), // Rule ID 10723 //
        GIM_CheckFeatures, GIMT_Encode2(GIFBS_isGFX9Plus),
        GIM_CheckRegBankForClass, /*MI*/0, /*Op*/0, /*RC*/GIMT_Encode2(AMDGPU::VGPR_32RegClassID),
        GIM_RecordInsn, /*DefineMI*/1, /*MI*/0, /*OpIdx*/1, // MIs[1]
        GIM_CheckOpcode, /*MI*/1, GIMT_Encode2(TargetOpcode::G_FMINNUM_IEEE),
        GIM_CheckType, /*MI*/1, /*Op*/1, /*Type*/GILLT_s16,
        GIM_CheckType, /*MI*/1, /*Op*/2, /*Type*/GILLT_s16,
        GIM_RecordInsn, /*DefineMI*/2, /*MI*/1, /*OpIdx*/2, // MIs[2]
        GIM_CheckOpcode, /*MI*/2, GIMT_Encode2(TargetOpcode::G_FMAXNUM_IEEE),
        GIM_CheckType, /*MI*/2, /*Op*/1, /*Type*/GILLT_s16,
        GIM_CheckType, /*MI*/2, /*Op*/2, /*Type*/GILLT_s16,
        GIM_RecordInsn, /*DefineMI*/3, /*MI*/0, /*OpIdx*/2, // MIs[3]
        GIM_CheckOpcode, /*MI*/3, GIMT_Encode2(TargetOpcode::G_FMINNUM),
        // MIs[3] VOP3Mods:src0:src0_mods
        GIM_CheckIsSameOperand, /*MI*/3, /*OpIdx*/1, /*OtherMI*/2, /*OtherOpIdx*/2,
        // MIs[3] VOP3Mods:src1:src1_mods
        GIM_CheckIsSameOperand, /*MI*/3, /*OpIdx*/2, /*OtherMI*/2, /*OtherOpIdx*/1,
        GIM_CheckCxxInsnPredicate, /*MI*/0, /*FnId*/GIMT_Encode2(GICXXPred_MI_Predicate_fmaxnum_like_nnan),
        GIM_CheckIsSafeToFold, /*InsnID*/1,
        GIM_CheckIsSafeToFold, /*InsnID*/2,
        GIM_CheckIsSafeToFold, /*InsnID*/3,
        GIM_CheckComplexPattern, /*MI*/1, /*Op*/1, /*Renderer*/GIMT_Encode2(0), GIMT_Encode2(GICP_gi_vop3mods),
        GIM_CheckComplexPattern, /*MI*/2, /*Op*/1, /*Renderer*/GIMT_Encode2(1), GIMT_Encode2(GICP_gi_vop3mods),
        GIM_CheckComplexPattern, /*MI*/2, /*Op*/2, /*Renderer*/GIMT_Encode2(2), GIMT_Encode2(GICP_gi_vop3mods),
        // (fmaxnum:{ *:[f16] } (fminnum_ieee:{ *:[f16] } (VOP3Mods:{ *:[f16] } f16:{ *:[f16] }:$src2, i32:{ *:[i32] }:$src2_mods), (fmaxnum_ieee:{ *:[f16] } (VOP3Mods:{ *:[f16] } f16:{ *:[f16] }:$src1, i32:{ *:[i32] }:$src1_mods), (VOP3Mods:{ *:[f16] } f16:{ *:[f16] }:$src0, i32:{ *:[i32] }:$src0_mods))), (fminnum:{ *:[f16] } (VOP3Mods:{ *:[f16] } f16:{ *:[f16] }:$src0, i32:{ *:[i32] }:$src0_mods), (VOP3Mods:{ *:[f16] } f16:{ *:[f16] }:$src1, i32:{ *:[i32] }:$src1_mods)))<<P:Predicate_fmaxnum_like_nnan>>  =>  (V_MED3_F16_e64:{ *:[f16] } ?:{ *:[i32] }:$src0_mods, ?:{ *:[f16] }:$src0, ?:{ *:[i32] }:$src1_mods, ?:{ *:[f16] }:$src1, ?:{ *:[i32] }:$src2_mods, ?:{ *:[f16] }:$src2, 0:{ *:[i1] })
        GIR_BuildMI, /*InsnID*/0, /*Opcode*/GIMT_Encode2(AMDGPU::V_MED3_F16_e64),
        GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/0, // DstI[vdst]
        GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(2), /*SubOperand*/1, // src0_mods
        GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(2), /*SubOperand*/0, // src0
        GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(1), /*SubOperand*/1, // src1_mods
        GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(1), /*SubOperand*/0, // src1
        GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/1, // src2_mods
        GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/0, // src2
        GIR_AddImm8, /*InsnID*/0, /*Imm*/0,
        GIR_AddImm8, /*InsnID*/0, /*Imm*/0,
        GIR_AddImm8, /*InsnID*/0, /*Imm*/0,
        GIR_ConstrainSelectedInstOperands, /*InsnID*/0,
        GIR_EraseFromParent, /*InsnID*/0,
        // GIR_Coverage, 10723,
        GIR_Done,
      // Label 4578: @303746
      GIM_Try, /*On fail goto*//*Label 4579*/ GIMT_Encode4(303892), // Rule ID 10724 //
        GIM_CheckFeatures, GIMT_Encode2(GIFBS_isGFX9Plus),
        GIM_CheckRegBankForClass, /*MI*/0, /*Op*/0, /*RC*/GIMT_Encode2(AMDGPU::VGPR_32RegClassID),
        GIM_RecordInsn, /*DefineMI*/1, /*MI*/0, /*OpIdx*/1, // MIs[1]
        GIM_CheckOpcode, /*MI*/1, GIMT_Encode2(TargetOpcode::G_FMINNUM_IEEE),
        GIM_CheckType, /*MI*/1, /*Op*/1, /*Type*/GILLT_s16,
        GIM_CheckType, /*MI*/1, /*Op*/2, /*Type*/GILLT_s16,
        GIM_RecordInsn, /*DefineMI*/2, /*MI*/1, /*OpIdx*/2, // MIs[2]
        GIM_CheckOpcode, /*MI*/2, GIMT_Encode2(TargetOpcode::G_FMAXNUM_IEEE),
        GIM_CheckType, /*MI*/2, /*Op*/1, /*Type*/GILLT_s16,
        GIM_CheckType, /*MI*/2, /*Op*/2, /*Type*/GILLT_s16,
        GIM_RecordInsn, /*DefineMI*/3, /*MI*/0, /*OpIdx*/2, // MIs[3]
        GIM_CheckOpcode, /*MI*/3, GIMT_Encode2(TargetOpcode::G_FMINNUM),
        // MIs[3] VOP3Mods:src1:src1_mods
        GIM_CheckIsSameOperand, /*MI*/3, /*OpIdx*/1, /*OtherMI*/2, /*OtherOpIdx*/1,
        // MIs[3] VOP3Mods:src0:src0_mods
        GIM_CheckIsSameOperand, /*MI*/3, /*OpIdx*/2, /*OtherMI*/2, /*OtherOpIdx*/2,
        GIM_CheckCxxInsnPredicate, /*MI*/0, /*FnId*/GIMT_Encode2(GICXXPred_MI_Predicate_fmaxnum_like_nnan),
        GIM_CheckIsSafeToFold, /*InsnID*/1,
        GIM_CheckIsSafeToFold, /*InsnID*/2,
        GIM_CheckIsSafeToFold, /*InsnID*/3,
        GIM_CheckComplexPattern, /*MI*/1, /*Op*/1, /*Renderer*/GIMT_Encode2(0), GIMT_Encode2(GICP_gi_vop3mods),
        GIM_CheckComplexPattern, /*MI*/2, /*Op*/1, /*Renderer*/GIMT_Encode2(1), GIMT_Encode2(GICP_gi_vop3mods),
        GIM_CheckComplexPattern, /*MI*/2, /*Op*/2, /*Renderer*/GIMT_Encode2(2), GIMT_Encode2(GICP_gi_vop3mods),
        // (fmaxnum:{ *:[f16] } (fminnum_ieee:{ *:[f16] } (VOP3Mods:{ *:[f16] } f16:{ *:[f16] }:$src2, i32:{ *:[i32] }:$src2_mods), (fmaxnum_ieee:{ *:[f16] } (VOP3Mods:{ *:[f16] } f16:{ *:[f16] }:$src1, i32:{ *:[i32] }:$src1_mods), (VOP3Mods:{ *:[f16] } f16:{ *:[f16] }:$src0, i32:{ *:[i32] }:$src0_mods))), (fminnum:{ *:[f16] } (VOP3Mods:{ *:[f16] } f16:{ *:[f16] }:$src1, i32:{ *:[i32] }:$src1_mods), (VOP3Mods:{ *:[f16] } f16:{ *:[f16] }:$src0, i32:{ *:[i32] }:$src0_mods)))<<P:Predicate_fmaxnum_like_nnan>>  =>  (V_MED3_F16_e64:{ *:[f16] } ?:{ *:[i32] }:$src0_mods, ?:{ *:[f16] }:$src0, ?:{ *:[i32] }:$src1_mods, ?:{ *:[f16] }:$src1, ?:{ *:[i32] }:$src2_mods, ?:{ *:[f16] }:$src2, 0:{ *:[i1] })
        GIR_BuildMI, /*InsnID*/0, /*Opcode*/GIMT_Encode2(AMDGPU::V_MED3_F16_e64),
        GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/0, // DstI[vdst]
        GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(2), /*SubOperand*/1, // src0_mods
        GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(2), /*SubOperand*/0, // src0
        GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(1), /*SubOperand*/1, // src1_mods
        GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(1), /*SubOperand*/0, // src1
        GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/1, // src2_mods
        GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/0, // src2
        GIR_AddImm8, /*InsnID*/0, /*Imm*/0,
        GIR_AddImm8, /*InsnID*/0, /*Imm*/0,
        GIR_AddImm8, /*InsnID*/0, /*Imm*/0,
        GIR_ConstrainSelectedInstOperands, /*InsnID*/0,
        GIR_EraseFromParent, /*InsnID*/0,
        // GIR_Coverage, 10724,
        GIR_Done,
      // Label 4579: @303892
      GIM_Try, /*On fail goto*//*Label 4580*/ GIMT_Encode4(304038), // Rule ID 10661 //
        GIM_CheckFeatures, GIMT_Encode2(GIFBS_isGFX9Plus),
        GIM_CheckRegBankForClass, /*MI*/0, /*Op*/0, /*RC*/GIMT_Encode2(AMDGPU::VGPR_32RegClassID),
        GIM_RecordInsn, /*DefineMI*/1, /*MI*/0, /*OpIdx*/1, // MIs[1]
        GIM_CheckOpcode, /*MI*/1, GIMT_Encode2(TargetOpcode::G_FMINNUM_IEEE),
        GIM_CheckType, /*MI*/1, /*Op*/1, /*Type*/GILLT_s16,
        GIM_CheckType, /*MI*/1, /*Op*/2, /*Type*/GILLT_s16,
        GIM_RecordInsn, /*DefineMI*/2, /*MI*/1, /*OpIdx*/2, // MIs[2]
        GIM_CheckOpcode, /*MI*/2, GIMT_Encode2(TargetOpcode::G_FMAXNUM_IEEE),
        GIM_CheckType, /*MI*/2, /*Op*/1, /*Type*/GILLT_s16,
        GIM_CheckType, /*MI*/2, /*Op*/2, /*Type*/GILLT_s16,
        GIM_RecordInsn, /*DefineMI*/3, /*MI*/0, /*OpIdx*/2, // MIs[3]
        GIM_CheckOpcode, /*MI*/3, GIMT_Encode2(TargetOpcode::G_FMINNUM_IEEE),
        // MIs[3] VOP3Mods:src0:src0_mods
        GIM_CheckIsSameOperand, /*MI*/3, /*OpIdx*/1, /*OtherMI*/2, /*OtherOpIdx*/1,
        // MIs[3] VOP3Mods:src1:src1_mods
        GIM_CheckIsSameOperand, /*MI*/3, /*OpIdx*/2, /*OtherMI*/2, /*OtherOpIdx*/2,
        GIM_CheckCxxInsnPredicate, /*MI*/0, /*FnId*/GIMT_Encode2(GICXXPred_MI_Predicate_fmaxnum_like_nnan),
        GIM_CheckIsSafeToFold, /*InsnID*/1,
        GIM_CheckIsSafeToFold, /*InsnID*/2,
        GIM_CheckIsSafeToFold, /*InsnID*/3,
        GIM_CheckComplexPattern, /*MI*/1, /*Op*/1, /*Renderer*/GIMT_Encode2(0), GIMT_Encode2(GICP_gi_vop3mods),
        GIM_CheckComplexPattern, /*MI*/2, /*Op*/1, /*Renderer*/GIMT_Encode2(1), GIMT_Encode2(GICP_gi_vop3mods),
        GIM_CheckComplexPattern, /*MI*/2, /*Op*/2, /*Renderer*/GIMT_Encode2(2), GIMT_Encode2(GICP_gi_vop3mods),
        // (fmaxnum:{ *:[f16] } (fminnum_ieee:{ *:[f16] } (VOP3Mods:{ *:[f16] } f16:{ *:[f16] }:$src2, i32:{ *:[i32] }:$src2_mods), (fmaxnum_ieee:{ *:[f16] } (VOP3Mods:{ *:[f16] } f16:{ *:[f16] }:$src0, i32:{ *:[i32] }:$src0_mods), (VOP3Mods:{ *:[f16] } f16:{ *:[f16] }:$src1, i32:{ *:[i32] }:$src1_mods))), (fminnum_ieee:{ *:[f16] } (VOP3Mods:{ *:[f16] } f16:{ *:[f16] }:$src0, i32:{ *:[i32] }:$src0_mods), (VOP3Mods:{ *:[f16] } f16:{ *:[f16] }:$src1, i32:{ *:[i32] }:$src1_mods)))<<P:Predicate_fmaxnum_like_nnan>>  =>  (V_MED3_F16_e64:{ *:[f16] } ?:{ *:[i32] }:$src0_mods, ?:{ *:[f16] }:$src0, ?:{ *:[i32] }:$src1_mods, ?:{ *:[f16] }:$src1, ?:{ *:[i32] }:$src2_mods, ?:{ *:[f16] }:$src2, 0:{ *:[i1] })
        GIR_BuildMI, /*InsnID*/0, /*Opcode*/GIMT_Encode2(AMDGPU::V_MED3_F16_e64),
        GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/0, // DstI[vdst]
        GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(1), /*SubOperand*/1, // src0_mods
        GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(1), /*SubOperand*/0, // src0
        GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(2), /*SubOperand*/1, // src1_mods
        GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(2), /*SubOperand*/0, // src1
        GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/1, // src2_mods
        GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/0, // src2
        GIR_AddImm8, /*InsnID*/0, /*Imm*/0,
        GIR_AddImm8, /*InsnID*/0, /*Imm*/0,
        GIR_AddImm8, /*InsnID*/0, /*Imm*/0,
        GIR_ConstrainSelectedInstOperands, /*InsnID*/0,
        GIR_EraseFromParent, /*InsnID*/0,
        // GIR_Coverage, 10661,
        GIR_Done,
      // Label 4580: @304038
      GIM_Try, /*On fail goto*//*Label 4581*/ GIMT_Encode4(304184), // Rule ID 10662 //
        GIM_CheckFeatures, GIMT_Encode2(GIFBS_isGFX9Plus),
        GIM_CheckRegBankForClass, /*MI*/0, /*Op*/0, /*RC*/GIMT_Encode2(AMDGPU::VGPR_32RegClassID),
        GIM_RecordInsn, /*DefineMI*/1, /*MI*/0, /*OpIdx*/1, // MIs[1]
        GIM_CheckOpcode, /*MI*/1, GIMT_Encode2(TargetOpcode::G_FMINNUM_IEEE),
        GIM_CheckType, /*MI*/1, /*Op*/1, /*Type*/GILLT_s16,
        GIM_CheckType, /*MI*/1, /*Op*/2, /*Type*/GILLT_s16,
        GIM_RecordInsn, /*DefineMI*/2, /*MI*/1, /*OpIdx*/2, // MIs[2]
        GIM_CheckOpcode, /*MI*/2, GIMT_Encode2(TargetOpcode::G_FMAXNUM_IEEE),
        GIM_CheckType, /*MI*/2, /*Op*/1, /*Type*/GILLT_s16,
        GIM_CheckType, /*MI*/2, /*Op*/2, /*Type*/GILLT_s16,
        GIM_RecordInsn, /*DefineMI*/3, /*MI*/0, /*OpIdx*/2, // MIs[3]
        GIM_CheckOpcode, /*MI*/3, GIMT_Encode2(TargetOpcode::G_FMINNUM_IEEE),
        // MIs[3] VOP3Mods:src1:src1_mods
        GIM_CheckIsSameOperand, /*MI*/3, /*OpIdx*/1, /*OtherMI*/2, /*OtherOpIdx*/2,
        // MIs[3] VOP3Mods:src0:src0_mods
        GIM_CheckIsSameOperand, /*MI*/3, /*OpIdx*/2, /*OtherMI*/2, /*OtherOpIdx*/1,
        GIM_CheckCxxInsnPredicate, /*MI*/0, /*FnId*/GIMT_Encode2(GICXXPred_MI_Predicate_fmaxnum_like_nnan),
        GIM_CheckIsSafeToFold, /*InsnID*/1,
        GIM_CheckIsSafeToFold, /*InsnID*/2,
        GIM_CheckIsSafeToFold, /*InsnID*/3,
        GIM_CheckComplexPattern, /*MI*/1, /*Op*/1, /*Renderer*/GIMT_Encode2(0), GIMT_Encode2(GICP_gi_vop3mods),
        GIM_CheckComplexPattern, /*MI*/2, /*Op*/1, /*Renderer*/GIMT_Encode2(1), GIMT_Encode2(GICP_gi_vop3mods),
        GIM_CheckComplexPattern, /*MI*/2, /*Op*/2, /*Renderer*/GIMT_Encode2(2), GIMT_Encode2(GICP_gi_vop3mods),
        // (fmaxnum:{ *:[f16] } (fminnum_ieee:{ *:[f16] } (VOP3Mods:{ *:[f16] } f16:{ *:[f16] }:$src2, i32:{ *:[i32] }:$src2_mods), (fmaxnum_ieee:{ *:[f16] } (VOP3Mods:{ *:[f16] } f16:{ *:[f16] }:$src0, i32:{ *:[i32] }:$src0_mods), (VOP3Mods:{ *:[f16] } f16:{ *:[f16] }:$src1, i32:{ *:[i32] }:$src1_mods))), (fminnum_ieee:{ *:[f16] } (VOP3Mods:{ *:[f16] } f16:{ *:[f16] }:$src1, i32:{ *:[i32] }:$src1_mods), (VOP3Mods:{ *:[f16] } f16:{ *:[f16] }:$src0, i32:{ *:[i32] }:$src0_mods)))<<P:Predicate_fmaxnum_like_nnan>>  =>  (V_MED3_F16_e64:{ *:[f16] } ?:{ *:[i32] }:$src0_mods, ?:{ *:[f16] }:$src0, ?:{ *:[i32] }:$src1_mods, ?:{ *:[f16] }:$src1, ?:{ *:[i32] }:$src2_mods, ?:{ *:[f16] }:$src2, 0:{ *:[i1] })
        GIR_BuildMI, /*InsnID*/0, /*Opcode*/GIMT_Encode2(AMDGPU::V_MED3_F16_e64),
        GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/0, // DstI[vdst]
        GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(1), /*SubOperand*/1, // src0_mods
        GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(1), /*SubOperand*/0, // src0
        GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(2), /*SubOperand*/1, // src1_mods
        GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(2), /*SubOperand*/0, // src1
        GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/1, // src2_mods
        GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/0, // src2
        GIR_AddImm8, /*InsnID*/0, /*Imm*/0,
        GIR_AddImm8, /*InsnID*/0, /*Imm*/0,
        GIR_AddImm8, /*InsnID*/0, /*Imm*/0,
        GIR_ConstrainSelectedInstOperands, /*InsnID*/0,
        GIR_EraseFromParent, /*InsnID*/0,
        // GIR_Coverage, 10662,
        GIR_Done,
      // Label 4581: @304184
      GIM_Try, /*On fail goto*//*Label 4582*/ GIMT_Encode4(304330), // Rule ID 10663 //
        GIM_CheckFeatures, GIMT_Encode2(GIFBS_isGFX9Plus),
        GIM_CheckRegBankForClass, /*MI*/0, /*Op*/0, /*RC*/GIMT_Encode2(AMDGPU::VGPR_32RegClassID),
        GIM_RecordInsn, /*DefineMI*/1, /*MI*/0, /*OpIdx*/1, // MIs[1]
        GIM_CheckOpcode, /*MI*/1, GIMT_Encode2(TargetOpcode::G_FMINNUM_IEEE),
        GIM_CheckType, /*MI*/1, /*Op*/1, /*Type*/GILLT_s16,
        GIM_CheckType, /*MI*/1, /*Op*/2, /*Type*/GILLT_s16,
        GIM_RecordInsn, /*DefineMI*/2, /*MI*/1, /*OpIdx*/2, // MIs[2]
        GIM_CheckOpcode, /*MI*/2, GIMT_Encode2(TargetOpcode::G_FMAXNUM_IEEE),
        GIM_CheckType, /*MI*/2, /*Op*/1, /*Type*/GILLT_s16,
        GIM_CheckType, /*MI*/2, /*Op*/2, /*Type*/GILLT_s16,
        GIM_RecordInsn, /*DefineMI*/3, /*MI*/0, /*OpIdx*/2, // MIs[3]
        GIM_CheckOpcode, /*MI*/3, GIMT_Encode2(TargetOpcode::G_FMINNUM_IEEE),
        // MIs[3] VOP3Mods:src0:src0_mods
        GIM_CheckIsSameOperand, /*MI*/3, /*OpIdx*/1, /*OtherMI*/2, /*OtherOpIdx*/2,
        // MIs[3] VOP3Mods:src1:src1_mods
        GIM_CheckIsSameOperand, /*MI*/3, /*OpIdx*/2, /*OtherMI*/2, /*OtherOpIdx*/1,
        GIM_CheckCxxInsnPredicate, /*MI*/0, /*FnId*/GIMT_Encode2(GICXXPred_MI_Predicate_fmaxnum_like_nnan),
        GIM_CheckIsSafeToFold, /*InsnID*/1,
        GIM_CheckIsSafeToFold, /*InsnID*/2,
        GIM_CheckIsSafeToFold, /*InsnID*/3,
        GIM_CheckComplexPattern, /*MI*/1, /*Op*/1, /*Renderer*/GIMT_Encode2(0), GIMT_Encode2(GICP_gi_vop3mods),
        GIM_CheckComplexPattern, /*MI*/2, /*Op*/1, /*Renderer*/GIMT_Encode2(1), GIMT_Encode2(GICP_gi_vop3mods),
        GIM_CheckComplexPattern, /*MI*/2, /*Op*/2, /*Renderer*/GIMT_Encode2(2), GIMT_Encode2(GICP_gi_vop3mods),
        // (fmaxnum:{ *:[f16] } (fminnum_ieee:{ *:[f16] } (VOP3Mods:{ *:[f16] } f16:{ *:[f16] }:$src2, i32:{ *:[i32] }:$src2_mods), (fmaxnum_ieee:{ *:[f16] } (VOP3Mods:{ *:[f16] } f16:{ *:[f16] }:$src1, i32:{ *:[i32] }:$src1_mods), (VOP3Mods:{ *:[f16] } f16:{ *:[f16] }:$src0, i32:{ *:[i32] }:$src0_mods))), (fminnum_ieee:{ *:[f16] } (VOP3Mods:{ *:[f16] } f16:{ *:[f16] }:$src0, i32:{ *:[i32] }:$src0_mods), (VOP3Mods:{ *:[f16] } f16:{ *:[f16] }:$src1, i32:{ *:[i32] }:$src1_mods)))<<P:Predicate_fmaxnum_like_nnan>>  =>  (V_MED3_F16_e64:{ *:[f16] } ?:{ *:[i32] }:$src0_mods, ?:{ *:[f16] }:$src0, ?:{ *:[i32] }:$src1_mods, ?:{ *:[f16] }:$src1, ?:{ *:[i32] }:$src2_mods, ?:{ *:[f16] }:$src2, 0:{ *:[i1] })
        GIR_BuildMI, /*InsnID*/0, /*Opcode*/GIMT_Encode2(AMDGPU::V_MED3_F16_e64),
        GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/0, // DstI[vdst]
        GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(2), /*SubOperand*/1, // src0_mods
        GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(2), /*SubOperand*/0, // src0
        GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(1), /*SubOperand*/1, // src1_mods
        GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(1), /*SubOperand*/0, // src1
        GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/1, // src2_mods
        GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/0, // src2
        GIR_AddImm8, /*InsnID*/0, /*Imm*/0,
        GIR_AddImm8, /*InsnID*/0, /*Imm*/0,
        GIR_AddImm8, /*InsnID*/0, /*Imm*/0,
        GIR_ConstrainSelectedInstOperands, /*InsnID*/0,
        GIR_EraseFromParent, /*InsnID*/0,
        // GIR_Coverage, 10663,
        GIR_Done,
      // Label 4582: @304330
      GIM_Try, /*On fail goto*//*Label 4583*/ GIMT_Encode4(304476), // Rule ID 10664 //
        GIM_CheckFeatures, GIMT_Encode2(GIFBS_isGFX9Plus),
        GIM_CheckRegBankForClass, /*MI*/0, /*Op*/0, /*RC*/GIMT_Encode2(AMDGPU::VGPR_32RegClassID),
        GIM_RecordInsn, /*DefineMI*/1, /*MI*/0, /*OpIdx*/1, // MIs[1]
        GIM_CheckOpcode, /*MI*/1, GIMT_Encode2(TargetOpcode::G_FMINNUM_IEEE),
        GIM_CheckType, /*MI*/1, /*Op*/1, /*Type*/GILLT_s16,
        GIM_CheckType, /*MI*/1, /*Op*/2, /*Type*/GILLT_s16,
        GIM_RecordInsn, /*DefineMI*/2, /*MI*/1, /*OpIdx*/2, // MIs[2]
        GIM_CheckOpcode, /*MI*/2, GIMT_Encode2(TargetOpcode::G_FMAXNUM_IEEE),
        GIM_CheckType, /*MI*/2, /*Op*/1, /*Type*/GILLT_s16,
        GIM_CheckType, /*MI*/2, /*Op*/2, /*Type*/GILLT_s16,
        GIM_RecordInsn, /*DefineMI*/3, /*MI*/0, /*OpIdx*/2, // MIs[3]
        GIM_CheckOpcode, /*MI*/3, GIMT_Encode2(TargetOpcode::G_FMINNUM_IEEE),
        // MIs[3] VOP3Mods:src1:src1_mods
        GIM_CheckIsSameOperand, /*MI*/3, /*OpIdx*/1, /*OtherMI*/2, /*OtherOpIdx*/1,
        // MIs[3] VOP3Mods:src0:src0_mods
        GIM_CheckIsSameOperand, /*MI*/3, /*OpIdx*/2, /*OtherMI*/2, /*OtherOpIdx*/2,
        GIM_CheckCxxInsnPredicate, /*MI*/0, /*FnId*/GIMT_Encode2(GICXXPred_MI_Predicate_fmaxnum_like_nnan),
        GIM_CheckIsSafeToFold, /*InsnID*/1,
        GIM_CheckIsSafeToFold, /*InsnID*/2,
        GIM_CheckIsSafeToFold, /*InsnID*/3,
        GIM_CheckComplexPattern, /*MI*/1, /*Op*/1, /*Renderer*/GIMT_Encode2(0), GIMT_Encode2(GICP_gi_vop3mods),
        GIM_CheckComplexPattern, /*MI*/2, /*Op*/1, /*Renderer*/GIMT_Encode2(1), GIMT_Encode2(GICP_gi_vop3mods),
        GIM_CheckComplexPattern, /*MI*/2, /*Op*/2, /*Renderer*/GIMT_Encode2(2), GIMT_Encode2(GICP_gi_vop3mods),
        // (fmaxnum:{ *:[f16] } (fminnum_ieee:{ *:[f16] } (VOP3Mods:{ *:[f16] } f16:{ *:[f16] }:$src2, i32:{ *:[i32] }:$src2_mods), (fmaxnum_ieee:{ *:[f16] } (VOP3Mods:{ *:[f16] } f16:{ *:[f16] }:$src1, i32:{ *:[i32] }:$src1_mods), (VOP3Mods:{ *:[f16] } f16:{ *:[f16] }:$src0, i32:{ *:[i32] }:$src0_mods))), (fminnum_ieee:{ *:[f16] } (VOP3Mods:{ *:[f16] } f16:{ *:[f16] }:$src1, i32:{ *:[i32] }:$src1_mods), (VOP3Mods:{ *:[f16] } f16:{ *:[f16] }:$src0, i32:{ *:[i32] }:$src0_mods)))<<P:Predicate_fmaxnum_like_nnan>>  =>  (V_MED3_F16_e64:{ *:[f16] } ?:{ *:[i32] }:$src0_mods, ?:{ *:[f16] }:$src0, ?:{ *:[i32] }:$src1_mods, ?:{ *:[f16] }:$src1, ?:{ *:[i32] }:$src2_mods, ?:{ *:[f16] }:$src2, 0:{ *:[i1] })
        GIR_BuildMI, /*InsnID*/0, /*Opcode*/GIMT_Encode2(AMDGPU::V_MED3_F16_e64),
        GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/0, // DstI[vdst]
        GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(2), /*SubOperand*/1, // src0_mods
        GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(2), /*SubOperand*/0, // src0
        GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(1), /*SubOperand*/1, // src1_mods
        GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(1), /*SubOperand*/0, // src1
        GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/1, // src2_mods
        GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/0, // src2
        GIR_AddImm8, /*InsnID*/0, /*Imm*/0,
        GIR_AddImm8, /*InsnID*/0, /*Imm*/0,
        GIR_AddImm8, /*InsnID*/0, /*Imm*/0,
        GIR_ConstrainSelectedInstOperands, /*InsnID*/0,
        GIR_EraseFromParent, /*InsnID*/0,
        // GIR_Coverage, 10664,
        GIR_Done,
      // Label 4583: @304476
      GIM_Try, /*On fail goto*//*Label 4584*/ GIMT_Encode4(304622), // Rule ID 10732 //
        GIM_CheckFeatures, GIMT_Encode2(GIFBS_isGFX9Plus),
        GIM_CheckRegBankForClass, /*MI*/0, /*Op*/0, /*RC*/GIMT_Encode2(AMDGPU::VGPR_32RegClassID),
        GIM_RecordInsn, /*DefineMI*/1, /*MI*/0, /*OpIdx*/1, // MIs[1]
        GIM_CheckOpcode, /*MI*/1, GIMT_Encode2(TargetOpcode::G_FMINNUM_IEEE),
        GIM_CheckType, /*MI*/1, /*Op*/1, /*Type*/GILLT_s16,
        GIM_CheckType, /*MI*/1, /*Op*/2, /*Type*/GILLT_s16,
        GIM_RecordInsn, /*DefineMI*/2, /*MI*/1, /*OpIdx*/1, // MIs[2]
        GIM_CheckOpcode, /*MI*/2, GIMT_Encode2(TargetOpcode::G_FMAXNUM),
        GIM_CheckType, /*MI*/2, /*Op*/1, /*Type*/GILLT_s16,
        GIM_CheckType, /*MI*/2, /*Op*/2, /*Type*/GILLT_s16,
        GIM_RecordInsn, /*DefineMI*/3, /*MI*/0, /*OpIdx*/2, // MIs[3]
        GIM_CheckOpcode, /*MI*/3, GIMT_Encode2(TargetOpcode::G_FMINNUM),
        // MIs[3] VOP3Mods:src0:src0_mods
        GIM_CheckIsSameOperand, /*MI*/3, /*OpIdx*/1, /*OtherMI*/2, /*OtherOpIdx*/1,
        // MIs[3] VOP3Mods:src1:src1_mods
        GIM_CheckIsSameOperand, /*MI*/3, /*OpIdx*/2, /*OtherMI*/2, /*OtherOpIdx*/2,
        GIM_CheckCxxInsnPredicate, /*MI*/0, /*FnId*/GIMT_Encode2(GICXXPred_MI_Predicate_fmaxnum_like_nnan),
        GIM_CheckIsSafeToFold, /*InsnID*/1,
        GIM_CheckIsSafeToFold, /*InsnID*/2,
        GIM_CheckIsSafeToFold, /*InsnID*/3,
        GIM_CheckComplexPattern, /*MI*/1, /*Op*/2, /*Renderer*/GIMT_Encode2(2), GIMT_Encode2(GICP_gi_vop3mods),
        GIM_CheckComplexPattern, /*MI*/2, /*Op*/1, /*Renderer*/GIMT_Encode2(0), GIMT_Encode2(GICP_gi_vop3mods),
        GIM_CheckComplexPattern, /*MI*/2, /*Op*/2, /*Renderer*/GIMT_Encode2(1), GIMT_Encode2(GICP_gi_vop3mods),
        // (fmaxnum:{ *:[f16] } (fminnum_ieee:{ *:[f16] } (fmaxnum:{ *:[f16] } (VOP3Mods:{ *:[f16] } f16:{ *:[f16] }:$src0, i32:{ *:[i32] }:$src0_mods), (VOP3Mods:{ *:[f16] } f16:{ *:[f16] }:$src1, i32:{ *:[i32] }:$src1_mods)), (VOP3Mods:{ *:[f16] } f16:{ *:[f16] }:$src2, i32:{ *:[i32] }:$src2_mods)), (fminnum:{ *:[f16] } (VOP3Mods:{ *:[f16] } f16:{ *:[f16] }:$src0, i32:{ *:[i32] }:$src0_mods), (VOP3Mods:{ *:[f16] } f16:{ *:[f16] }:$src1, i32:{ *:[i32] }:$src1_mods)))<<P:Predicate_fmaxnum_like_nnan>>  =>  (V_MED3_F16_e64:{ *:[f16] } ?:{ *:[i32] }:$src0_mods, ?:{ *:[f16] }:$src0, ?:{ *:[i32] }:$src1_mods, ?:{ *:[f16] }:$src1, ?:{ *:[i32] }:$src2_mods, ?:{ *:[f16] }:$src2, 0:{ *:[i1] })
        GIR_BuildMI, /*InsnID*/0, /*Opcode*/GIMT_Encode2(AMDGPU::V_MED3_F16_e64),
        GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/0, // DstI[vdst]
        GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/1, // src0_mods
        GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/0, // src0
        GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(1), /*SubOperand*/1, // src1_mods
        GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(1), /*SubOperand*/0, // src1
        GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(2), /*SubOperand*/1, // src2_mods
        GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(2), /*SubOperand*/0, // src2
        GIR_AddImm8, /*InsnID*/0, /*Imm*/0,
        GIR_AddImm8, /*InsnID*/0, /*Imm*/0,
        GIR_AddImm8, /*InsnID*/0, /*Imm*/0,
        GIR_ConstrainSelectedInstOperands, /*InsnID*/0,
        GIR_EraseFromParent, /*InsnID*/0,
        // GIR_Coverage, 10732,
        GIR_Done,
      // Label 4584: @304622
      GIM_Try, /*On fail goto*//*Label 4585*/ GIMT_Encode4(304768), // Rule ID 10733 //
        GIM_CheckFeatures, GIMT_Encode2(GIFBS_isGFX9Plus),
        GIM_CheckRegBankForClass, /*MI*/0, /*Op*/0, /*RC*/GIMT_Encode2(AMDGPU::VGPR_32RegClassID),
        GIM_RecordInsn, /*DefineMI*/1, /*MI*/0, /*OpIdx*/1, // MIs[1]
        GIM_CheckOpcode, /*MI*/1, GIMT_Encode2(TargetOpcode::G_FMINNUM_IEEE),
        GIM_CheckType, /*MI*/1, /*Op*/1, /*Type*/GILLT_s16,
        GIM_CheckType, /*MI*/1, /*Op*/2, /*Type*/GILLT_s16,
        GIM_RecordInsn, /*DefineMI*/2, /*MI*/1, /*OpIdx*/1, // MIs[2]
        GIM_CheckOpcode, /*MI*/2, GIMT_Encode2(TargetOpcode::G_FMAXNUM),
        GIM_CheckType, /*MI*/2, /*Op*/1, /*Type*/GILLT_s16,
        GIM_CheckType, /*MI*/2, /*Op*/2, /*Type*/GILLT_s16,
        GIM_RecordInsn, /*DefineMI*/3, /*MI*/0, /*OpIdx*/2, // MIs[3]
        GIM_CheckOpcode, /*MI*/3, GIMT_Encode2(TargetOpcode::G_FMINNUM),
        // MIs[3] VOP3Mods:src1:src1_mods
        GIM_CheckIsSameOperand, /*MI*/3, /*OpIdx*/1, /*OtherMI*/2, /*OtherOpIdx*/2,
        // MIs[3] VOP3Mods:src0:src0_mods
        GIM_CheckIsSameOperand, /*MI*/3, /*OpIdx*/2, /*OtherMI*/2, /*OtherOpIdx*/1,
        GIM_CheckCxxInsnPredicate, /*MI*/0, /*FnId*/GIMT_Encode2(GICXXPred_MI_Predicate_fmaxnum_like_nnan),
        GIM_CheckIsSafeToFold, /*InsnID*/1,
        GIM_CheckIsSafeToFold, /*InsnID*/2,
        GIM_CheckIsSafeToFold, /*InsnID*/3,
        GIM_CheckComplexPattern, /*MI*/1, /*Op*/2, /*Renderer*/GIMT_Encode2(2), GIMT_Encode2(GICP_gi_vop3mods),
        GIM_CheckComplexPattern, /*MI*/2, /*Op*/1, /*Renderer*/GIMT_Encode2(0), GIMT_Encode2(GICP_gi_vop3mods),
        GIM_CheckComplexPattern, /*MI*/2, /*Op*/2, /*Renderer*/GIMT_Encode2(1), GIMT_Encode2(GICP_gi_vop3mods),
        // (fmaxnum:{ *:[f16] } (fminnum_ieee:{ *:[f16] } (fmaxnum:{ *:[f16] } (VOP3Mods:{ *:[f16] } f16:{ *:[f16] }:$src0, i32:{ *:[i32] }:$src0_mods), (VOP3Mods:{ *:[f16] } f16:{ *:[f16] }:$src1, i32:{ *:[i32] }:$src1_mods)), (VOP3Mods:{ *:[f16] } f16:{ *:[f16] }:$src2, i32:{ *:[i32] }:$src2_mods)), (fminnum:{ *:[f16] } (VOP3Mods:{ *:[f16] } f16:{ *:[f16] }:$src1, i32:{ *:[i32] }:$src1_mods), (VOP3Mods:{ *:[f16] } f16:{ *:[f16] }:$src0, i32:{ *:[i32] }:$src0_mods)))<<P:Predicate_fmaxnum_like_nnan>>  =>  (V_MED3_F16_e64:{ *:[f16] } ?:{ *:[i32] }:$src0_mods, ?:{ *:[f16] }:$src0, ?:{ *:[i32] }:$src1_mods, ?:{ *:[f16] }:$src1, ?:{ *:[i32] }:$src2_mods, ?:{ *:[f16] }:$src2, 0:{ *:[i1] })
        GIR_BuildMI, /*InsnID*/0, /*Opcode*/GIMT_Encode2(AMDGPU::V_MED3_F16_e64),
        GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/0, // DstI[vdst]
        GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/1, // src0_mods
        GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/0, // src0
        GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(1), /*SubOperand*/1, // src1_mods
        GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(1), /*SubOperand*/0, // src1
        GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(2), /*SubOperand*/1, // src2_mods
        GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(2), /*SubOperand*/0, // src2
        GIR_AddImm8, /*InsnID*/0, /*Imm*/0,
        GIR_AddImm8, /*InsnID*/0, /*Imm*/0,
        GIR_AddImm8, /*InsnID*/0, /*Imm*/0,
        GIR_ConstrainSelectedInstOperands, /*InsnID*/0,
        GIR_EraseFromParent, /*InsnID*/0,
        // GIR_Coverage, 10733,
        GIR_Done,
      // Label 4585: @304768
      GIM_Try, /*On fail goto*//*Label 4586*/ GIMT_Encode4(304914), // Rule ID 10734 //
        GIM_CheckFeatures, GIMT_Encode2(GIFBS_isGFX9Plus),
        GIM_CheckRegBankForClass, /*MI*/0, /*Op*/0, /*RC*/GIMT_Encode2(AMDGPU::VGPR_32RegClassID),
        GIM_RecordInsn, /*DefineMI*/1, /*MI*/0, /*OpIdx*/1, // MIs[1]
        GIM_CheckOpcode, /*MI*/1, GIMT_Encode2(TargetOpcode::G_FMINNUM_IEEE),
        GIM_CheckType, /*MI*/1, /*Op*/1, /*Type*/GILLT_s16,
        GIM_CheckType, /*MI*/1, /*Op*/2, /*Type*/GILLT_s16,
        GIM_RecordInsn, /*DefineMI*/2, /*MI*/1, /*OpIdx*/1, // MIs[2]
        GIM_CheckOpcode, /*MI*/2, GIMT_Encode2(TargetOpcode::G_FMAXNUM),
        GIM_CheckType, /*MI*/2, /*Op*/1, /*Type*/GILLT_s16,
        GIM_CheckType, /*MI*/2, /*Op*/2, /*Type*/GILLT_s16,
        GIM_RecordInsn, /*DefineMI*/3, /*MI*/0, /*OpIdx*/2, // MIs[3]
        GIM_CheckOpcode, /*MI*/3, GIMT_Encode2(TargetOpcode::G_FMINNUM),
        // MIs[3] VOP3Mods:src0:src0_mods
        GIM_CheckIsSameOperand, /*MI*/3, /*OpIdx*/1, /*OtherMI*/2, /*OtherOpIdx*/2,
        // MIs[3] VOP3Mods:src1:src1_mods
        GIM_CheckIsSameOperand, /*MI*/3, /*OpIdx*/2, /*OtherMI*/2, /*OtherOpIdx*/1,
        GIM_CheckCxxInsnPredicate, /*MI*/0, /*FnId*/GIMT_Encode2(GICXXPred_MI_Predicate_fmaxnum_like_nnan),
        GIM_CheckIsSafeToFold, /*InsnID*/1,
        GIM_CheckIsSafeToFold, /*InsnID*/2,
        GIM_CheckIsSafeToFold, /*InsnID*/3,
        GIM_CheckComplexPattern, /*MI*/1, /*Op*/2, /*Renderer*/GIMT_Encode2(2), GIMT_Encode2(GICP_gi_vop3mods),
        GIM_CheckComplexPattern, /*MI*/2, /*Op*/1, /*Renderer*/GIMT_Encode2(0), GIMT_Encode2(GICP_gi_vop3mods),
        GIM_CheckComplexPattern, /*MI*/2, /*Op*/2, /*Renderer*/GIMT_Encode2(1), GIMT_Encode2(GICP_gi_vop3mods),
        // (fmaxnum:{ *:[f16] } (fminnum_ieee:{ *:[f16] } (fmaxnum:{ *:[f16] } (VOP3Mods:{ *:[f16] } f16:{ *:[f16] }:$src1, i32:{ *:[i32] }:$src1_mods), (VOP3Mods:{ *:[f16] } f16:{ *:[f16] }:$src0, i32:{ *:[i32] }:$src0_mods)), (VOP3Mods:{ *:[f16] } f16:{ *:[f16] }:$src2, i32:{ *:[i32] }:$src2_mods)), (fminnum:{ *:[f16] } (VOP3Mods:{ *:[f16] } f16:{ *:[f16] }:$src0, i32:{ *:[i32] }:$src0_mods), (VOP3Mods:{ *:[f16] } f16:{ *:[f16] }:$src1, i32:{ *:[i32] }:$src1_mods)))<<P:Predicate_fmaxnum_like_nnan>>  =>  (V_MED3_F16_e64:{ *:[f16] } ?:{ *:[i32] }:$src0_mods, ?:{ *:[f16] }:$src0, ?:{ *:[i32] }:$src1_mods, ?:{ *:[f16] }:$src1, ?:{ *:[i32] }:$src2_mods, ?:{ *:[f16] }:$src2, 0:{ *:[i1] })
        GIR_BuildMI, /*InsnID*/0, /*Opcode*/GIMT_Encode2(AMDGPU::V_MED3_F16_e64),
        GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/0, // DstI[vdst]
        GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(1), /*SubOperand*/1, // src0_mods
        GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(1), /*SubOperand*/0, // src0
        GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/1, // src1_mods
        GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/0, // src1
        GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(2), /*SubOperand*/1, // src2_mods
        GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(2), /*SubOperand*/0, // src2
        GIR_AddImm8, /*InsnID*/0, /*Imm*/0,
        GIR_AddImm8, /*InsnID*/0, /*Imm*/0,
        GIR_AddImm8, /*InsnID*/0, /*Imm*/0,
        GIR_ConstrainSelectedInstOperands, /*InsnID*/0,
        GIR_EraseFromParent, /*InsnID*/0,
        // GIR_Coverage, 10734,
        GIR_Done,
      // Label 4586: @304914
      GIM_Try, /*On fail goto*//*Label 4587*/ GIMT_Encode4(305060), // Rule ID 10735 //
        GIM_CheckFeatures, GIMT_Encode2(GIFBS_isGFX9Plus),
        GIM_CheckRegBankForClass, /*MI*/0, /*Op*/0, /*RC*/GIMT_Encode2(AMDGPU::VGPR_32RegClassID),
        GIM_RecordInsn, /*DefineMI*/1, /*MI*/0, /*OpIdx*/1, // MIs[1]
        GIM_CheckOpcode, /*MI*/1, GIMT_Encode2(TargetOpcode::G_FMINNUM_IEEE),
        GIM_CheckType, /*MI*/1, /*Op*/1, /*Type*/GILLT_s16,
        GIM_CheckType, /*MI*/1, /*Op*/2, /*Type*/GILLT_s16,
        GIM_RecordInsn, /*DefineMI*/2, /*MI*/1, /*OpIdx*/1, // MIs[2]
        GIM_CheckOpcode, /*MI*/2, GIMT_Encode2(TargetOpcode::G_FMAXNUM),
        GIM_CheckType, /*MI*/2, /*Op*/1, /*Type*/GILLT_s16,
        GIM_CheckType, /*MI*/2, /*Op*/2, /*Type*/GILLT_s16,
        GIM_RecordInsn, /*DefineMI*/3, /*MI*/0, /*OpIdx*/2, // MIs[3]
        GIM_CheckOpcode, /*MI*/3, GIMT_Encode2(TargetOpcode::G_FMINNUM),
        // MIs[3] VOP3Mods:src1:src1_mods
        GIM_CheckIsSameOperand, /*MI*/3, /*OpIdx*/1, /*OtherMI*/2, /*OtherOpIdx*/1,
        // MIs[3] VOP3Mods:src0:src0_mods
        GIM_CheckIsSameOperand, /*MI*/3, /*OpIdx*/2, /*OtherMI*/2, /*OtherOpIdx*/2,
        GIM_CheckCxxInsnPredicate, /*MI*/0, /*FnId*/GIMT_Encode2(GICXXPred_MI_Predicate_fmaxnum_like_nnan),
        GIM_CheckIsSafeToFold, /*InsnID*/1,
        GIM_CheckIsSafeToFold, /*InsnID*/2,
        GIM_CheckIsSafeToFold, /*InsnID*/3,
        GIM_CheckComplexPattern, /*MI*/1, /*Op*/2, /*Renderer*/GIMT_Encode2(2), GIMT_Encode2(GICP_gi_vop3mods),
        GIM_CheckComplexPattern, /*MI*/2, /*Op*/1, /*Renderer*/GIMT_Encode2(0), GIMT_Encode2(GICP_gi_vop3mods),
        GIM_CheckComplexPattern, /*MI*/2, /*Op*/2, /*Renderer*/GIMT_Encode2(1), GIMT_Encode2(GICP_gi_vop3mods),
        // (fmaxnum:{ *:[f16] } (fminnum_ieee:{ *:[f16] } (fmaxnum:{ *:[f16] } (VOP3Mods:{ *:[f16] } f16:{ *:[f16] }:$src1, i32:{ *:[i32] }:$src1_mods), (VOP3Mods:{ *:[f16] } f16:{ *:[f16] }:$src0, i32:{ *:[i32] }:$src0_mods)), (VOP3Mods:{ *:[f16] } f16:{ *:[f16] }:$src2, i32:{ *:[i32] }:$src2_mods)), (fminnum:{ *:[f16] } (VOP3Mods:{ *:[f16] } f16:{ *:[f16] }:$src1, i32:{ *:[i32] }:$src1_mods), (VOP3Mods:{ *:[f16] } f16:{ *:[f16] }:$src0, i32:{ *:[i32] }:$src0_mods)))<<P:Predicate_fmaxnum_like_nnan>>  =>  (V_MED3_F16_e64:{ *:[f16] } ?:{ *:[i32] }:$src0_mods, ?:{ *:[f16] }:$src0, ?:{ *:[i32] }:$src1_mods, ?:{ *:[f16] }:$src1, ?:{ *:[i32] }:$src2_mods, ?:{ *:[f16] }:$src2, 0:{ *:[i1] })
        GIR_BuildMI, /*InsnID*/0, /*Opcode*/GIMT_Encode2(AMDGPU::V_MED3_F16_e64),
        GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/0, // DstI[vdst]
        GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(1), /*SubOperand*/1, // src0_mods
        GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(1), /*SubOperand*/0, // src0
        GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/1, // src1_mods
        GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/0, // src1
        GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(2), /*SubOperand*/1, // src2_mods
        GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(2), /*SubOperand*/0, // src2
        GIR_AddImm8, /*InsnID*/0, /*Imm*/0,
        GIR_AddImm8, /*InsnID*/0, /*Imm*/0,
        GIR_AddImm8, /*InsnID*/0, /*Imm*/0,
        GIR_ConstrainSelectedInstOperands, /*InsnID*/0,
        GIR_EraseFromParent, /*InsnID*/0,
        // GIR_Coverage, 10735,
        GIR_Done,
      // Label 4587: @305060
      GIM_Try, /*On fail goto*//*Label 4588*/ GIMT_Encode4(305206), // Rule ID 10672 //
        GIM_CheckFeatures, GIMT_Encode2(GIFBS_isGFX9Plus),
        GIM_CheckRegBankForClass, /*MI*/0, /*Op*/0, /*RC*/GIMT_Encode2(AMDGPU::VGPR_32RegClassID),
        GIM_RecordInsn, /*DefineMI*/1, /*MI*/0, /*OpIdx*/1, // MIs[1]
        GIM_CheckOpcode, /*MI*/1, GIMT_Encode2(TargetOpcode::G_FMINNUM_IEEE),
        GIM_CheckType, /*MI*/1, /*Op*/1, /*Type*/GILLT_s16,
        GIM_CheckType, /*MI*/1, /*Op*/2, /*Type*/GILLT_s16,
        GIM_RecordInsn, /*DefineMI*/2, /*MI*/1, /*OpIdx*/1, // MIs[2]
        GIM_CheckOpcode, /*MI*/2, GIMT_Encode2(TargetOpcode::G_FMAXNUM),
        GIM_CheckType, /*MI*/2, /*Op*/1, /*Type*/GILLT_s16,
        GIM_CheckType, /*MI*/2, /*Op*/2, /*Type*/GILLT_s16,
        GIM_RecordInsn, /*DefineMI*/3, /*MI*/0, /*OpIdx*/2, // MIs[3]
        GIM_CheckOpcode, /*MI*/3, GIMT_Encode2(TargetOpcode::G_FMINNUM_IEEE),
        // MIs[3] VOP3Mods:src0:src0_mods
        GIM_CheckIsSameOperand, /*MI*/3, /*OpIdx*/1, /*OtherMI*/2, /*OtherOpIdx*/1,
        // MIs[3] VOP3Mods:src1:src1_mods
        GIM_CheckIsSameOperand, /*MI*/3, /*OpIdx*/2, /*OtherMI*/2, /*OtherOpIdx*/2,
        GIM_CheckCxxInsnPredicate, /*MI*/0, /*FnId*/GIMT_Encode2(GICXXPred_MI_Predicate_fmaxnum_like_nnan),
        GIM_CheckIsSafeToFold, /*InsnID*/1,
        GIM_CheckIsSafeToFold, /*InsnID*/2,
        GIM_CheckIsSafeToFold, /*InsnID*/3,
        GIM_CheckComplexPattern, /*MI*/1, /*Op*/2, /*Renderer*/GIMT_Encode2(2), GIMT_Encode2(GICP_gi_vop3mods),
        GIM_CheckComplexPattern, /*MI*/2, /*Op*/1, /*Renderer*/GIMT_Encode2(0), GIMT_Encode2(GICP_gi_vop3mods),
        GIM_CheckComplexPattern, /*MI*/2, /*Op*/2, /*Renderer*/GIMT_Encode2(1), GIMT_Encode2(GICP_gi_vop3mods),
        // (fmaxnum:{ *:[f16] } (fminnum_ieee:{ *:[f16] } (fmaxnum:{ *:[f16] } (VOP3Mods:{ *:[f16] } f16:{ *:[f16] }:$src0, i32:{ *:[i32] }:$src0_mods), (VOP3Mods:{ *:[f16] } f16:{ *:[f16] }:$src1, i32:{ *:[i32] }:$src1_mods)), (VOP3Mods:{ *:[f16] } f16:{ *:[f16] }:$src2, i32:{ *:[i32] }:$src2_mods)), (fminnum_ieee:{ *:[f16] } (VOP3Mods:{ *:[f16] } f16:{ *:[f16] }:$src0, i32:{ *:[i32] }:$src0_mods), (VOP3Mods:{ *:[f16] } f16:{ *:[f16] }:$src1, i32:{ *:[i32] }:$src1_mods)))<<P:Predicate_fmaxnum_like_nnan>>  =>  (V_MED3_F16_e64:{ *:[f16] } ?:{ *:[i32] }:$src0_mods, ?:{ *:[f16] }:$src0, ?:{ *:[i32] }:$src1_mods, ?:{ *:[f16] }:$src1, ?:{ *:[i32] }:$src2_mods, ?:{ *:[f16] }:$src2, 0:{ *:[i1] })
        GIR_BuildMI, /*InsnID*/0, /*Opcode*/GIMT_Encode2(AMDGPU::V_MED3_F16_e64),
        GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/0, // DstI[vdst]
        GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/1, // src0_mods
        GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/0, // src0
        GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(1), /*SubOperand*/1, // src1_mods
        GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(1), /*SubOperand*/0, // src1
        GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(2), /*SubOperand*/1, // src2_mods
        GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(2), /*SubOperand*/0, // src2
        GIR_AddImm8, /*InsnID*/0, /*Imm*/0,
        GIR_AddImm8, /*InsnID*/0, /*Imm*/0,
        GIR_AddImm8, /*InsnID*/0, /*Imm*/0,
        GIR_ConstrainSelectedInstOperands, /*InsnID*/0,
        GIR_EraseFromParent, /*InsnID*/0,
        // GIR_Coverage, 10672,
        GIR_Done,
      // Label 4588: @305206
      GIM_Try, /*On fail goto*//*Label 4589*/ GIMT_Encode4(305352), // Rule ID 10673 //
        GIM_CheckFeatures, GIMT_Encode2(GIFBS_isGFX9Plus),
        GIM_CheckRegBankForClass, /*MI*/0, /*Op*/0, /*RC*/GIMT_Encode2(AMDGPU::VGPR_32RegClassID),
        GIM_RecordInsn, /*DefineMI*/1, /*MI*/0, /*OpIdx*/1, // MIs[1]
        GIM_CheckOpcode, /*MI*/1, GIMT_Encode2(TargetOpcode::G_FMINNUM_IEEE),
        GIM_CheckType, /*MI*/1, /*Op*/1, /*Type*/GILLT_s16,
        GIM_CheckType, /*MI*/1, /*Op*/2, /*Type*/GILLT_s16,
        GIM_RecordInsn, /*DefineMI*/2, /*MI*/1, /*OpIdx*/1, // MIs[2]
        GIM_CheckOpcode, /*MI*/2, GIMT_Encode2(TargetOpcode::G_FMAXNUM),
        GIM_CheckType, /*MI*/2, /*Op*/1, /*Type*/GILLT_s16,
        GIM_CheckType, /*MI*/2, /*Op*/2, /*Type*/GILLT_s16,
        GIM_RecordInsn, /*DefineMI*/3, /*MI*/0, /*OpIdx*/2, // MIs[3]
        GIM_CheckOpcode, /*MI*/3, GIMT_Encode2(TargetOpcode::G_FMINNUM_IEEE),
        // MIs[3] VOP3Mods:src1:src1_mods
        GIM_CheckIsSameOperand, /*MI*/3, /*OpIdx*/1, /*OtherMI*/2, /*OtherOpIdx*/2,
        // MIs[3] VOP3Mods:src0:src0_mods
        GIM_CheckIsSameOperand, /*MI*/3, /*OpIdx*/2, /*OtherMI*/2, /*OtherOpIdx*/1,
        GIM_CheckCxxInsnPredicate, /*MI*/0, /*FnId*/GIMT_Encode2(GICXXPred_MI_Predicate_fmaxnum_like_nnan),
        GIM_CheckIsSafeToFold, /*InsnID*/1,
        GIM_CheckIsSafeToFold, /*InsnID*/2,
        GIM_CheckIsSafeToFold, /*InsnID*/3,
        GIM_CheckComplexPattern, /*MI*/1, /*Op*/2, /*Renderer*/GIMT_Encode2(2), GIMT_Encode2(GICP_gi_vop3mods),
        GIM_CheckComplexPattern, /*MI*/2, /*Op*/1, /*Renderer*/GIMT_Encode2(0), GIMT_Encode2(GICP_gi_vop3mods),
        GIM_CheckComplexPattern, /*MI*/2, /*Op*/2, /*Renderer*/GIMT_Encode2(1), GIMT_Encode2(GICP_gi_vop3mods),
        // (fmaxnum:{ *:[f16] } (fminnum_ieee:{ *:[f16] } (fmaxnum:{ *:[f16] } (VOP3Mods:{ *:[f16] } f16:{ *:[f16] }:$src0, i32:{ *:[i32] }:$src0_mods), (VOP3Mods:{ *:[f16] } f16:{ *:[f16] }:$src1, i32:{ *:[i32] }:$src1_mods)), (VOP3Mods:{ *:[f16] } f16:{ *:[f16] }:$src2, i32:{ *:[i32] }:$src2_mods)), (fminnum_ieee:{ *:[f16] } (VOP3Mods:{ *:[f16] } f16:{ *:[f16] }:$src1, i32:{ *:[i32] }:$src1_mods), (VOP3Mods:{ *:[f16] } f16:{ *:[f16] }:$src0, i32:{ *:[i32] }:$src0_mods)))<<P:Predicate_fmaxnum_like_nnan>>  =>  (V_MED3_F16_e64:{ *:[f16] } ?:{ *:[i32] }:$src0_mods, ?:{ *:[f16] }:$src0, ?:{ *:[i32] }:$src1_mods, ?:{ *:[f16] }:$src1, ?:{ *:[i32] }:$src2_mods, ?:{ *:[f16] }:$src2, 0:{ *:[i1] })
        GIR_BuildMI, /*InsnID*/0, /*Opcode*/GIMT_Encode2(AMDGPU::V_MED3_F16_e64),
        GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/0, // DstI[vdst]
        GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/1, // src0_mods
        GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/0, // src0
        GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(1), /*SubOperand*/1, // src1_mods
        GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(1), /*SubOperand*/0, // src1
        GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(2), /*SubOperand*/1, // src2_mods
        GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(2), /*SubOperand*/0, // src2
        GIR_AddImm8, /*InsnID*/0, /*Imm*/0,
        GIR_AddImm8, /*InsnID*/0, /*Imm*/0,
        GIR_AddImm8, /*InsnID*/0, /*Imm*/0,
        GIR_ConstrainSelectedInstOperands, /*InsnID*/0,
        GIR_EraseFromParent, /*InsnID*/0,
        // GIR_Coverage, 10673,
        GIR_Done,
      // Label 4589: @305352
      GIM_Try, /*On fail goto*//*Label 4590*/ GIMT_Encode4(305498), // Rule ID 10674 //
        GIM_CheckFeatures, GIMT_Encode2(GIFBS_isGFX9Plus),
        GIM_CheckRegBankForClass, /*MI*/0, /*Op*/0, /*RC*/GIMT_Encode2(AMDGPU::VGPR_32RegClassID),
        GIM_RecordInsn, /*DefineMI*/1, /*MI*/0, /*OpIdx*/1, // MIs[1]
        GIM_CheckOpcode, /*MI*/1, GIMT_Encode2(TargetOpcode::G_FMINNUM_IEEE),
        GIM_CheckType, /*MI*/1, /*Op*/1, /*Type*/GILLT_s16,
        GIM_CheckType, /*MI*/1, /*Op*/2, /*Type*/GILLT_s16,
        GIM_RecordInsn, /*DefineMI*/2, /*MI*/1, /*OpIdx*/1, // MIs[2]
        GIM_CheckOpcode, /*MI*/2, GIMT_Encode2(TargetOpcode::G_FMAXNUM),
        GIM_CheckType, /*MI*/2, /*Op*/1, /*Type*/GILLT_s16,
        GIM_CheckType, /*MI*/2, /*Op*/2, /*Type*/GILLT_s16,
        GIM_RecordInsn, /*DefineMI*/3, /*MI*/0, /*OpIdx*/2, // MIs[3]
        GIM_CheckOpcode, /*MI*/3, GIMT_Encode2(TargetOpcode::G_FMINNUM_IEEE),
        // MIs[3] VOP3Mods:src0:src0_mods
        GIM_CheckIsSameOperand, /*MI*/3, /*OpIdx*/1, /*OtherMI*/2, /*OtherOpIdx*/2,
        // MIs[3] VOP3Mods:src1:src1_mods
        GIM_CheckIsSameOperand, /*MI*/3, /*OpIdx*/2, /*OtherMI*/2, /*OtherOpIdx*/1,
        GIM_CheckCxxInsnPredicate, /*MI*/0, /*FnId*/GIMT_Encode2(GICXXPred_MI_Predicate_fmaxnum_like_nnan),
        GIM_CheckIsSafeToFold, /*InsnID*/1,
        GIM_CheckIsSafeToFold, /*InsnID*/2,
        GIM_CheckIsSafeToFold, /*InsnID*/3,
        GIM_CheckComplexPattern, /*MI*/1, /*Op*/2, /*Renderer*/GIMT_Encode2(2), GIMT_Encode2(GICP_gi_vop3mods),
        GIM_CheckComplexPattern, /*MI*/2, /*Op*/1, /*Renderer*/GIMT_Encode2(0), GIMT_Encode2(GICP_gi_vop3mods),
        GIM_CheckComplexPattern, /*MI*/2, /*Op*/2, /*Renderer*/GIMT_Encode2(1), GIMT_Encode2(GICP_gi_vop3mods),
        // (fmaxnum:{ *:[f16] } (fminnum_ieee:{ *:[f16] } (fmaxnum:{ *:[f16] } (VOP3Mods:{ *:[f16] } f16:{ *:[f16] }:$src1, i32:{ *:[i32] }:$src1_mods), (VOP3Mods:{ *:[f16] } f16:{ *:[f16] }:$src0, i32:{ *:[i32] }:$src0_mods)), (VOP3Mods:{ *:[f16] } f16:{ *:[f16] }:$src2, i32:{ *:[i32] }:$src2_mods)), (fminnum_ieee:{ *:[f16] } (VOP3Mods:{ *:[f16] } f16:{ *:[f16] }:$src0, i32:{ *:[i32] }:$src0_mods), (VOP3Mods:{ *:[f16] } f16:{ *:[f16] }:$src1, i32:{ *:[i32] }:$src1_mods)))<<P:Predicate_fmaxnum_like_nnan>>  =>  (V_MED3_F16_e64:{ *:[f16] } ?:{ *:[i32] }:$src0_mods, ?:{ *:[f16] }:$src0, ?:{ *:[i32] }:$src1_mods, ?:{ *:[f16] }:$src1, ?:{ *:[i32] }:$src2_mods, ?:{ *:[f16] }:$src2, 0:{ *:[i1] })
        GIR_BuildMI, /*InsnID*/0, /*Opcode*/GIMT_Encode2(AMDGPU::V_MED3_F16_e64),
        GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/0, // DstI[vdst]
        GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(1), /*SubOperand*/1, // src0_mods
        GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(1), /*SubOperand*/0, // src0
        GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/1, // src1_mods
        GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/0, // src1
        GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(2), /*SubOperand*/1, // src2_mods
        GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(2), /*SubOperand*/0, // src2
        GIR_AddImm8, /*InsnID*/0, /*Imm*/0,
        GIR_AddImm8, /*InsnID*/0, /*Imm*/0,
        GIR_AddImm8, /*InsnID*/0, /*Imm*/0,
        GIR_ConstrainSelectedInstOperands, /*InsnID*/0,
        GIR_EraseFromParent, /*InsnID*/0,
        // GIR_Coverage, 10674,
        GIR_Done,
      // Label 4590: @305498
      GIM_Try, /*On fail goto*//*Label 4591*/ GIMT_Encode4(305644), // Rule ID 10675 //
        GIM_CheckFeatures, GIMT_Encode2(GIFBS_isGFX9Plus),
        GIM_CheckRegBankForClass, /*MI*/0, /*Op*/0, /*RC*/GIMT_Encode2(AMDGPU::VGPR_32RegClassID),
        GIM_RecordInsn, /*DefineMI*/1, /*MI*/0, /*OpIdx*/1, // MIs[1]
        GIM_CheckOpcode, /*MI*/1, GIMT_Encode2(TargetOpcode::G_FMINNUM_IEEE),
        GIM_CheckType, /*MI*/1, /*Op*/1, /*Type*/GILLT_s16,
        GIM_CheckType, /*MI*/1, /*Op*/2, /*Type*/GILLT_s16,
        GIM_RecordInsn, /*DefineMI*/2, /*MI*/1, /*OpIdx*/1, // MIs[2]
        GIM_CheckOpcode, /*MI*/2, GIMT_Encode2(TargetOpcode::G_FMAXNUM),
        GIM_CheckType, /*MI*/2, /*Op*/1, /*Type*/GILLT_s16,
        GIM_CheckType, /*MI*/2, /*Op*/2, /*Type*/GILLT_s16,
        GIM_RecordInsn, /*DefineMI*/3, /*MI*/0, /*OpIdx*/2, // MIs[3]
        GIM_CheckOpcode, /*MI*/3, GIMT_Encode2(TargetOpcode::G_FMINNUM_IEEE),
        // MIs[3] VOP3Mods:src1:src1_mods
        GIM_CheckIsSameOperand, /*MI*/3, /*OpIdx*/1, /*OtherMI*/2, /*OtherOpIdx*/1,
        // MIs[3] VOP3Mods:src0:src0_mods
        GIM_CheckIsSameOperand, /*MI*/3, /*OpIdx*/2, /*OtherMI*/2, /*OtherOpIdx*/2,
        GIM_CheckCxxInsnPredicate, /*MI*/0, /*FnId*/GIMT_Encode2(GICXXPred_MI_Predicate_fmaxnum_like_nnan),
        GIM_CheckIsSafeToFold, /*InsnID*/1,
        GIM_CheckIsSafeToFold, /*InsnID*/2,
        GIM_CheckIsSafeToFold, /*InsnID*/3,
        GIM_CheckComplexPattern, /*MI*/1, /*Op*/2, /*Renderer*/GIMT_Encode2(2), GIMT_Encode2(GICP_gi_vop3mods),
        GIM_CheckComplexPattern, /*MI*/2, /*Op*/1, /*Renderer*/GIMT_Encode2(0), GIMT_Encode2(GICP_gi_vop3mods),
        GIM_CheckComplexPattern, /*MI*/2, /*Op*/2, /*Renderer*/GIMT_Encode2(1), GIMT_Encode2(GICP_gi_vop3mods),
        // (fmaxnum:{ *:[f16] } (fminnum_ieee:{ *:[f16] } (fmaxnum:{ *:[f16] } (VOP3Mods:{ *:[f16] } f16:{ *:[f16] }:$src1, i32:{ *:[i32] }:$src1_mods), (VOP3Mods:{ *:[f16] } f16:{ *:[f16] }:$src0, i32:{ *:[i32] }:$src0_mods)), (VOP3Mods:{ *:[f16] } f16:{ *:[f16] }:$src2, i32:{ *:[i32] }:$src2_mods)), (fminnum_ieee:{ *:[f16] } (VOP3Mods:{ *:[f16] } f16:{ *:[f16] }:$src1, i32:{ *:[i32] }:$src1_mods), (VOP3Mods:{ *:[f16] } f16:{ *:[f16] }:$src0, i32:{ *:[i32] }:$src0_mods)))<<P:Predicate_fmaxnum_like_nnan>>  =>  (V_MED3_F16_e64:{ *:[f16] } ?:{ *:[i32] }:$src0_mods, ?:{ *:[f16] }:$src0, ?:{ *:[i32] }:$src1_mods, ?:{ *:[f16] }:$src1, ?:{ *:[i32] }:$src2_mods, ?:{ *:[f16] }:$src2, 0:{ *:[i1] })
        GIR_BuildMI, /*InsnID*/0, /*Opcode*/GIMT_Encode2(AMDGPU::V_MED3_F16_e64),
        GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/0, // DstI[vdst]
        GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(1), /*SubOperand*/1, // src0_mods
        GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(1), /*SubOperand*/0, // src0
        GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/1, // src1_mods
        GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/0, // src1
        GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(2), /*SubOperand*/1, // src2_mods
        GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(2), /*SubOperand*/0, // src2
        GIR_AddImm8, /*InsnID*/0, /*Imm*/0,
        GIR_AddImm8, /*InsnID*/0, /*Imm*/0,
        GIR_AddImm8, /*InsnID*/0, /*Imm*/0,
        GIR_ConstrainSelectedInstOperands, /*InsnID*/0,
        GIR_EraseFromParent, /*InsnID*/0,
        // GIR_Coverage, 10675,
        GIR_Done,
      // Label 4591: @305644
      GIM_Try, /*On fail goto*//*Label 4592*/ GIMT_Encode4(305790), // Rule ID 10717 //
        GIM_CheckFeatures, GIMT_Encode2(GIFBS_isGFX9Plus),
        GIM_CheckRegBankForClass, /*MI*/0, /*Op*/0, /*RC*/GIMT_Encode2(AMDGPU::VGPR_32RegClassID),
        GIM_RecordInsn, /*DefineMI*/1, /*MI*/0, /*OpIdx*/1, // MIs[1]
        GIM_CheckOpcode, /*MI*/1, GIMT_Encode2(TargetOpcode::G_FMINNUM_IEEE),
        GIM_CheckType, /*MI*/1, /*Op*/1, /*Type*/GILLT_s16,
        GIM_CheckType, /*MI*/1, /*Op*/2, /*Type*/GILLT_s16,
        GIM_RecordInsn, /*DefineMI*/2, /*MI*/1, /*OpIdx*/1, // MIs[2]
        GIM_CheckOpcode, /*MI*/2, GIMT_Encode2(TargetOpcode::G_FMAXNUM_IEEE),
        GIM_CheckType, /*MI*/2, /*Op*/1, /*Type*/GILLT_s16,
        GIM_CheckType, /*MI*/2, /*Op*/2, /*Type*/GILLT_s16,
        GIM_RecordInsn, /*DefineMI*/3, /*MI*/0, /*OpIdx*/2, // MIs[3]
        GIM_CheckOpcode, /*MI*/3, GIMT_Encode2(TargetOpcode::G_FMINNUM),
        // MIs[3] VOP3Mods:src0:src0_mods
        GIM_CheckIsSameOperand, /*MI*/3, /*OpIdx*/1, /*OtherMI*/2, /*OtherOpIdx*/1,
        // MIs[3] VOP3Mods:src1:src1_mods
        GIM_CheckIsSameOperand, /*MI*/3, /*OpIdx*/2, /*OtherMI*/2, /*OtherOpIdx*/2,
        GIM_CheckCxxInsnPredicate, /*MI*/0, /*FnId*/GIMT_Encode2(GICXXPred_MI_Predicate_fmaxnum_like_nnan),
        GIM_CheckIsSafeToFold, /*InsnID*/1,
        GIM_CheckIsSafeToFold, /*InsnID*/2,
        GIM_CheckIsSafeToFold, /*InsnID*/3,
        GIM_CheckComplexPattern, /*MI*/1, /*Op*/2, /*Renderer*/GIMT_Encode2(2), GIMT_Encode2(GICP_gi_vop3mods),
        GIM_CheckComplexPattern, /*MI*/2, /*Op*/1, /*Renderer*/GIMT_Encode2(0), GIMT_Encode2(GICP_gi_vop3mods),
        GIM_CheckComplexPattern, /*MI*/2, /*Op*/2, /*Renderer*/GIMT_Encode2(1), GIMT_Encode2(GICP_gi_vop3mods),
        // (fmaxnum:{ *:[f16] } (fminnum_ieee:{ *:[f16] } (fmaxnum_ieee:{ *:[f16] } (VOP3Mods:{ *:[f16] } f16:{ *:[f16] }:$src0, i32:{ *:[i32] }:$src0_mods), (VOP3Mods:{ *:[f16] } f16:{ *:[f16] }:$src1, i32:{ *:[i32] }:$src1_mods)), (VOP3Mods:{ *:[f16] } f16:{ *:[f16] }:$src2, i32:{ *:[i32] }:$src2_mods)), (fminnum:{ *:[f16] } (VOP3Mods:{ *:[f16] } f16:{ *:[f16] }:$src0, i32:{ *:[i32] }:$src0_mods), (VOP3Mods:{ *:[f16] } f16:{ *:[f16] }:$src1, i32:{ *:[i32] }:$src1_mods)))<<P:Predicate_fmaxnum_like_nnan>>  =>  (V_MED3_F16_e64:{ *:[f16] } ?:{ *:[i32] }:$src0_mods, ?:{ *:[f16] }:$src0, ?:{ *:[i32] }:$src1_mods, ?:{ *:[f16] }:$src1, ?:{ *:[i32] }:$src2_mods, ?:{ *:[f16] }:$src2, 0:{ *:[i1] })
        GIR_BuildMI, /*InsnID*/0, /*Opcode*/GIMT_Encode2(AMDGPU::V_MED3_F16_e64),
        GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/0, // DstI[vdst]
        GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/1, // src0_mods
        GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/0, // src0
        GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(1), /*SubOperand*/1, // src1_mods
        GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(1), /*SubOperand*/0, // src1
        GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(2), /*SubOperand*/1, // src2_mods
        GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(2), /*SubOperand*/0, // src2
        GIR_AddImm8, /*InsnID*/0, /*Imm*/0,
        GIR_AddImm8, /*InsnID*/0, /*Imm*/0,
        GIR_AddImm8, /*InsnID*/0, /*Imm*/0,
        GIR_ConstrainSelectedInstOperands, /*InsnID*/0,
        GIR_EraseFromParent, /*InsnID*/0,
        // GIR_Coverage, 10717,
        GIR_Done,
      // Label 4592: @305790
      GIM_Try, /*On fail goto*//*Label 4593*/ GIMT_Encode4(305936), // Rule ID 10718 //
        GIM_CheckFeatures, GIMT_Encode2(GIFBS_isGFX9Plus),
        GIM_CheckRegBankForClass, /*MI*/0, /*Op*/0, /*RC*/GIMT_Encode2(AMDGPU::VGPR_32RegClassID),
        GIM_RecordInsn, /*DefineMI*/1, /*MI*/0, /*OpIdx*/1, // MIs[1]
        GIM_CheckOpcode, /*MI*/1, GIMT_Encode2(TargetOpcode::G_FMINNUM_IEEE),
        GIM_CheckType, /*MI*/1, /*Op*/1, /*Type*/GILLT_s16,
        GIM_CheckType, /*MI*/1, /*Op*/2, /*Type*/GILLT_s16,
        GIM_RecordInsn, /*DefineMI*/2, /*MI*/1, /*OpIdx*/1, // MIs[2]
        GIM_CheckOpcode, /*MI*/2, GIMT_Encode2(TargetOpcode::G_FMAXNUM_IEEE),
        GIM_CheckType, /*MI*/2, /*Op*/1, /*Type*/GILLT_s16,
        GIM_CheckType, /*MI*/2, /*Op*/2, /*Type*/GILLT_s16,
        GIM_RecordInsn, /*DefineMI*/3, /*MI*/0, /*OpIdx*/2, // MIs[3]
        GIM_CheckOpcode, /*MI*/3, GIMT_Encode2(TargetOpcode::G_FMINNUM),
        // MIs[3] VOP3Mods:src1:src1_mods
        GIM_CheckIsSameOperand, /*MI*/3, /*OpIdx*/1, /*OtherMI*/2, /*OtherOpIdx*/2,
        // MIs[3] VOP3Mods:src0:src0_mods
        GIM_CheckIsSameOperand, /*MI*/3, /*OpIdx*/2, /*OtherMI*/2, /*OtherOpIdx*/1,
        GIM_CheckCxxInsnPredicate, /*MI*/0, /*FnId*/GIMT_Encode2(GICXXPred_MI_Predicate_fmaxnum_like_nnan),
        GIM_CheckIsSafeToFold, /*InsnID*/1,
        GIM_CheckIsSafeToFold, /*InsnID*/2,
        GIM_CheckIsSafeToFold, /*InsnID*/3,
        GIM_CheckComplexPattern, /*MI*/1, /*Op*/2, /*Renderer*/GIMT_Encode2(2), GIMT_Encode2(GICP_gi_vop3mods),
        GIM_CheckComplexPattern, /*MI*/2, /*Op*/1, /*Renderer*/GIMT_Encode2(0), GIMT_Encode2(GICP_gi_vop3mods),
        GIM_CheckComplexPattern, /*MI*/2, /*Op*/2, /*Renderer*/GIMT_Encode2(1), GIMT_Encode2(GICP_gi_vop3mods),
        // (fmaxnum:{ *:[f16] } (fminnum_ieee:{ *:[f16] } (fmaxnum_ieee:{ *:[f16] } (VOP3Mods:{ *:[f16] } f16:{ *:[f16] }:$src0, i32:{ *:[i32] }:$src0_mods), (VOP3Mods:{ *:[f16] } f16:{ *:[f16] }:$src1, i32:{ *:[i32] }:$src1_mods)), (VOP3Mods:{ *:[f16] } f16:{ *:[f16] }:$src2, i32:{ *:[i32] }:$src2_mods)), (fminnum:{ *:[f16] } (VOP3Mods:{ *:[f16] } f16:{ *:[f16] }:$src1, i32:{ *:[i32] }:$src1_mods), (VOP3Mods:{ *:[f16] } f16:{ *:[f16] }:$src0, i32:{ *:[i32] }:$src0_mods)))<<P:Predicate_fmaxnum_like_nnan>>  =>  (V_MED3_F16_e64:{ *:[f16] } ?:{ *:[i32] }:$src0_mods, ?:{ *:[f16] }:$src0, ?:{ *:[i32] }:$src1_mods, ?:{ *:[f16] }:$src1, ?:{ *:[i32] }:$src2_mods, ?:{ *:[f16] }:$src2, 0:{ *:[i1] })
        GIR_BuildMI, /*InsnID*/0, /*Opcode*/GIMT_Encode2(AMDGPU::V_MED3_F16_e64),
        GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/0, // DstI[vdst]
        GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/1, // src0_mods
        GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/0, // src0
        GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(1), /*SubOperand*/1, // src1_mods
        GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(1), /*SubOperand*/0, // src1
        GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(2), /*SubOperand*/1, // src2_mods
        GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(2), /*SubOperand*/0, // src2
        GIR_AddImm8, /*InsnID*/0, /*Imm*/0,
        GIR_AddImm8, /*InsnID*/0, /*Imm*/0,
        GIR_AddImm8, /*InsnID*/0, /*Imm*/0,
        GIR_ConstrainSelectedInstOperands, /*InsnID*/0,
        GIR_EraseFromParent, /*InsnID*/0,
        // GIR_Coverage, 10718,
        GIR_Done,
      // Label 4593: @305936
      GIM_Try, /*On fail goto*//*Label 4594*/ GIMT_Encode4(306082), // Rule ID 10719 //
        GIM_CheckFeatures, GIMT_Encode2(GIFBS_isGFX9Plus),
        GIM_CheckRegBankForClass, /*MI*/0, /*Op*/0, /*RC*/GIMT_Encode2(AMDGPU::VGPR_32RegClassID),
        GIM_RecordInsn, /*DefineMI*/1, /*MI*/0, /*OpIdx*/1, // MIs[1]
        GIM_CheckOpcode, /*MI*/1, GIMT_Encode2(TargetOpcode::G_FMINNUM_IEEE),
        GIM_CheckType, /*MI*/1, /*Op*/1, /*Type*/GILLT_s16,
        GIM_CheckType, /*MI*/1, /*Op*/2, /*Type*/GILLT_s16,
        GIM_RecordInsn, /*DefineMI*/2, /*MI*/1, /*OpIdx*/1, // MIs[2]
        GIM_CheckOpcode, /*MI*/2, GIMT_Encode2(TargetOpcode::G_FMAXNUM_IEEE),
        GIM_CheckType, /*MI*/2, /*Op*/1, /*Type*/GILLT_s16,
        GIM_CheckType, /*MI*/2, /*Op*/2, /*Type*/GILLT_s16,
        GIM_RecordInsn, /*DefineMI*/3, /*MI*/0, /*OpIdx*/2, // MIs[3]
        GIM_CheckOpcode, /*MI*/3, GIMT_Encode2(TargetOpcode::G_FMINNUM),
        // MIs[3] VOP3Mods:src0:src0_mods
        GIM_CheckIsSameOperand, /*MI*/3, /*OpIdx*/1, /*OtherMI*/2, /*OtherOpIdx*/2,
        // MIs[3] VOP3Mods:src1:src1_mods
        GIM_CheckIsSameOperand, /*MI*/3, /*OpIdx*/2, /*OtherMI*/2, /*OtherOpIdx*/1,
        GIM_CheckCxxInsnPredicate, /*MI*/0, /*FnId*/GIMT_Encode2(GICXXPred_MI_Predicate_fmaxnum_like_nnan),
        GIM_CheckIsSafeToFold, /*InsnID*/1,
        GIM_CheckIsSafeToFold, /*InsnID*/2,
        GIM_CheckIsSafeToFold, /*InsnID*/3,
        GIM_CheckComplexPattern, /*MI*/1, /*Op*/2, /*Renderer*/GIMT_Encode2(2), GIMT_Encode2(GICP_gi_vop3mods),
        GIM_CheckComplexPattern, /*MI*/2, /*Op*/1, /*Renderer*/GIMT_Encode2(0), GIMT_Encode2(GICP_gi_vop3mods),
        GIM_CheckComplexPattern, /*MI*/2, /*Op*/2, /*Renderer*/GIMT_Encode2(1), GIMT_Encode2(GICP_gi_vop3mods),
        // (fmaxnum:{ *:[f16] } (fminnum_ieee:{ *:[f16] } (fmaxnum_ieee:{ *:[f16] } (VOP3Mods:{ *:[f16] } f16:{ *:[f16] }:$src1, i32:{ *:[i32] }:$src1_mods), (VOP3Mods:{ *:[f16] } f16:{ *:[f16] }:$src0, i32:{ *:[i32] }:$src0_mods)), (VOP3Mods:{ *:[f16] } f16:{ *:[f16] }:$src2, i32:{ *:[i32] }:$src2_mods)), (fminnum:{ *:[f16] } (VOP3Mods:{ *:[f16] } f16:{ *:[f16] }:$src0, i32:{ *:[i32] }:$src0_mods), (VOP3Mods:{ *:[f16] } f16:{ *:[f16] }:$src1, i32:{ *:[i32] }:$src1_mods)))<<P:Predicate_fmaxnum_like_nnan>>  =>  (V_MED3_F16_e64:{ *:[f16] } ?:{ *:[i32] }:$src0_mods, ?:{ *:[f16] }:$src0, ?:{ *:[i32] }:$src1_mods, ?:{ *:[f16] }:$src1, ?:{ *:[i32] }:$src2_mods, ?:{ *:[f16] }:$src2, 0:{ *:[i1] })
        GIR_BuildMI, /*InsnID*/0, /*Opcode*/GIMT_Encode2(AMDGPU::V_MED3_F16_e64),
        GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/0, // DstI[vdst]
        GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(1), /*SubOperand*/1, // src0_mods
        GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(1), /*SubOperand*/0, // src0
        GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/1, // src1_mods
        GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/0, // src1
        GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(2), /*SubOperand*/1, // src2_mods
        GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(2), /*SubOperand*/0, // src2
        GIR_AddImm8, /*InsnID*/0, /*Imm*/0,
        GIR_AddImm8, /*InsnID*/0, /*Imm*/0,
        GIR_AddImm8, /*InsnID*/0, /*Imm*/0,
        GIR_ConstrainSelectedInstOperands, /*InsnID*/0,
        GIR_EraseFromParent, /*InsnID*/0,
        // GIR_Coverage, 10719,
        GIR_Done,
      // Label 4594: @306082
      GIM_Try, /*On fail goto*//*Label 4595*/ GIMT_Encode4(306228), // Rule ID 10720 //
        GIM_CheckFeatures, GIMT_Encode2(GIFBS_isGFX9Plus),
        GIM_CheckRegBankForClass, /*MI*/0, /*Op*/0, /*RC*/GIMT_Encode2(AMDGPU::VGPR_32RegClassID),
        GIM_RecordInsn, /*DefineMI*/1, /*MI*/0, /*OpIdx*/1, // MIs[1]
        GIM_CheckOpcode, /*MI*/1, GIMT_Encode2(TargetOpcode::G_FMINNUM_IEEE),
        GIM_CheckType, /*MI*/1, /*Op*/1, /*Type*/GILLT_s16,
        GIM_CheckType, /*MI*/1, /*Op*/2, /*Type*/GILLT_s16,
        GIM_RecordInsn, /*DefineMI*/2, /*MI*/1, /*OpIdx*/1, // MIs[2]
        GIM_CheckOpcode, /*MI*/2, GIMT_Encode2(TargetOpcode::G_FMAXNUM_IEEE),
        GIM_CheckType, /*MI*/2, /*Op*/1, /*Type*/GILLT_s16,
        GIM_CheckType, /*MI*/2, /*Op*/2, /*Type*/GILLT_s16,
        GIM_RecordInsn, /*DefineMI*/3, /*MI*/0, /*OpIdx*/2, // MIs[3]
        GIM_CheckOpcode, /*MI*/3, GIMT_Encode2(TargetOpcode::G_FMINNUM),
        // MIs[3] VOP3Mods:src1:src1_mods
        GIM_CheckIsSameOperand, /*MI*/3, /*OpIdx*/1, /*OtherMI*/2, /*OtherOpIdx*/1,
        // MIs[3] VOP3Mods:src0:src0_mods
        GIM_CheckIsSameOperand, /*MI*/3, /*OpIdx*/2, /*OtherMI*/2, /*OtherOpIdx*/2,
        GIM_CheckCxxInsnPredicate, /*MI*/0, /*FnId*/GIMT_Encode2(GICXXPred_MI_Predicate_fmaxnum_like_nnan),
        GIM_CheckIsSafeToFold, /*InsnID*/1,
        GIM_CheckIsSafeToFold, /*InsnID*/2,
        GIM_CheckIsSafeToFold, /*InsnID*/3,
        GIM_CheckComplexPattern, /*MI*/1, /*Op*/2, /*Renderer*/GIMT_Encode2(2), GIMT_Encode2(GICP_gi_vop3mods),
        GIM_CheckComplexPattern, /*MI*/2, /*Op*/1, /*Renderer*/GIMT_Encode2(0), GIMT_Encode2(GICP_gi_vop3mods),
        GIM_CheckComplexPattern, /*MI*/2, /*Op*/2, /*Renderer*/GIMT_Encode2(1), GIMT_Encode2(GICP_gi_vop3mods),
        // (fmaxnum:{ *:[f16] } (fminnum_ieee:{ *:[f16] } (fmaxnum_ieee:{ *:[f16] } (VOP3Mods:{ *:[f16] } f16:{ *:[f16] }:$src1, i32:{ *:[i32] }:$src1_mods), (VOP3Mods:{ *:[f16] } f16:{ *:[f16] }:$src0, i32:{ *:[i32] }:$src0_mods)), (VOP3Mods:{ *:[f16] } f16:{ *:[f16] }:$src2, i32:{ *:[i32] }:$src2_mods)), (fminnum:{ *:[f16] } (VOP3Mods:{ *:[f16] } f16:{ *:[f16] }:$src1, i32:{ *:[i32] }:$src1_mods), (VOP3Mods:{ *:[f16] } f16:{ *:[f16] }:$src0, i32:{ *:[i32] }:$src0_mods)))<<P:Predicate_fmaxnum_like_nnan>>  =>  (V_MED3_F16_e64:{ *:[f16] } ?:{ *:[i32] }:$src0_mods, ?:{ *:[f16] }:$src0, ?:{ *:[i32] }:$src1_mods, ?:{ *:[f16] }:$src1, ?:{ *:[i32] }:$src2_mods, ?:{ *:[f16] }:$src2, 0:{ *:[i1] })
        GIR_BuildMI, /*InsnID*/0, /*Opcode*/GIMT_Encode2(AMDGPU::V_MED3_F16_e64),
        GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/0, // DstI[vdst]
        GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(1), /*SubOperand*/1, // src0_mods
        GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(1), /*SubOperand*/0, // src0
        GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/1, // src1_mods
        GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/0, // src1
        GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(2), /*SubOperand*/1, // src2_mods
        GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(2), /*SubOperand*/0, // src2
        GIR_AddImm8, /*InsnID*/0, /*Imm*/0,
        GIR_AddImm8, /*InsnID*/0, /*Imm*/0,
        GIR_AddImm8, /*InsnID*/0, /*Imm*/0,
        GIR_ConstrainSelectedInstOperands, /*InsnID*/0,
        GIR_EraseFromParent, /*InsnID*/0,
        // GIR_Coverage, 10720,
        GIR_Done,
      // Label 4595: @306228
      GIM_Try, /*On fail goto*//*Label 4596*/ GIMT_Encode4(306374), // Rule ID 10657 //
        GIM_CheckFeatures, GIMT_Encode2(GIFBS_isGFX9Plus),
        GIM_CheckRegBankForClass, /*MI*/0, /*Op*/0, /*RC*/GIMT_Encode2(AMDGPU::VGPR_32RegClassID),
        GIM_RecordInsn, /*DefineMI*/1, /*MI*/0, /*OpIdx*/1, // MIs[1]
        GIM_CheckOpcode, /*MI*/1, GIMT_Encode2(TargetOpcode::G_FMINNUM_IEEE),
        GIM_CheckType, /*MI*/1, /*Op*/1, /*Type*/GILLT_s16,
        GIM_CheckType, /*MI*/1, /*Op*/2, /*Type*/GILLT_s16,
        GIM_RecordInsn, /*DefineMI*/2, /*MI*/1, /*OpIdx*/1, // MIs[2]
        GIM_CheckOpcode, /*MI*/2, GIMT_Encode2(TargetOpcode::G_FMAXNUM_IEEE),
        GIM_CheckType, /*MI*/2, /*Op*/1, /*Type*/GILLT_s16,
        GIM_CheckType, /*MI*/2, /*Op*/2, /*Type*/GILLT_s16,
        GIM_RecordInsn, /*DefineMI*/3, /*MI*/0, /*OpIdx*/2, // MIs[3]
        GIM_CheckOpcode, /*MI*/3, GIMT_Encode2(TargetOpcode::G_FMINNUM_IEEE),
        // MIs[3] VOP3Mods:src0:src0_mods
        GIM_CheckIsSameOperand, /*MI*/3, /*OpIdx*/1, /*OtherMI*/2, /*OtherOpIdx*/1,
        // MIs[3] VOP3Mods:src1:src1_mods
        GIM_CheckIsSameOperand, /*MI*/3, /*OpIdx*/2, /*OtherMI*/2, /*OtherOpIdx*/2,
        GIM_CheckCxxInsnPredicate, /*MI*/0, /*FnId*/GIMT_Encode2(GICXXPred_MI_Predicate_fmaxnum_like_nnan),
        GIM_CheckIsSafeToFold, /*InsnID*/1,
        GIM_CheckIsSafeToFold, /*InsnID*/2,
        GIM_CheckIsSafeToFold, /*InsnID*/3,
        GIM_CheckComplexPattern, /*MI*/1, /*Op*/2, /*Renderer*/GIMT_Encode2(2), GIMT_Encode2(GICP_gi_vop3mods),
        GIM_CheckComplexPattern, /*MI*/2, /*Op*/1, /*Renderer*/GIMT_Encode2(0), GIMT_Encode2(GICP_gi_vop3mods),
        GIM_CheckComplexPattern, /*MI*/2, /*Op*/2, /*Renderer*/GIMT_Encode2(1), GIMT_Encode2(GICP_gi_vop3mods),
        // (fmaxnum:{ *:[f16] } (fminnum_ieee:{ *:[f16] } (fmaxnum_ieee:{ *:[f16] } (VOP3Mods:{ *:[f16] } f16:{ *:[f16] }:$src0, i32:{ *:[i32] }:$src0_mods), (VOP3Mods:{ *:[f16] } f16:{ *:[f16] }:$src1, i32:{ *:[i32] }:$src1_mods)), (VOP3Mods:{ *:[f16] } f16:{ *:[f16] }:$src2, i32:{ *:[i32] }:$src2_mods)), (fminnum_ieee:{ *:[f16] } (VOP3Mods:{ *:[f16] } f16:{ *:[f16] }:$src0, i32:{ *:[i32] }:$src0_mods), (VOP3Mods:{ *:[f16] } f16:{ *:[f16] }:$src1, i32:{ *:[i32] }:$src1_mods)))<<P:Predicate_fmaxnum_like_nnan>>  =>  (V_MED3_F16_e64:{ *:[f16] } ?:{ *:[i32] }:$src0_mods, ?:{ *:[f16] }:$src0, ?:{ *:[i32] }:$src1_mods, ?:{ *:[f16] }:$src1, ?:{ *:[i32] }:$src2_mods, ?:{ *:[f16] }:$src2, 0:{ *:[i1] })
        GIR_BuildMI, /*InsnID*/0, /*Opcode*/GIMT_Encode2(AMDGPU::V_MED3_F16_e64),
        GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/0, // DstI[vdst]
        GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/1, // src0_mods
        GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/0, // src0
        GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(1), /*SubOperand*/1, // src1_mods
        GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(1), /*SubOperand*/0, // src1
        GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(2), /*SubOperand*/1, // src2_mods
        GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(2), /*SubOperand*/0, // src2
        GIR_AddImm8, /*InsnID*/0, /*Imm*/0,
        GIR_AddImm8, /*InsnID*/0, /*Imm*/0,
        GIR_AddImm8, /*InsnID*/0, /*Imm*/0,
        GIR_ConstrainSelectedInstOperands, /*InsnID*/0,
        GIR_EraseFromParent, /*InsnID*/0,
        // GIR_Coverage, 10657,
        GIR_Done,
      // Label 4596: @306374
      GIM_Try, /*On fail goto*//*Label 4597*/ GIMT_Encode4(306520), // Rule ID 10658 //
        GIM_CheckFeatures, GIMT_Encode2(GIFBS_isGFX9Plus),
        GIM_CheckRegBankForClass, /*MI*/0, /*Op*/0, /*RC*/GIMT_Encode2(AMDGPU::VGPR_32RegClassID),
        GIM_RecordInsn, /*DefineMI*/1, /*MI*/0, /*OpIdx*/1, // MIs[1]
        GIM_CheckOpcode, /*MI*/1, GIMT_Encode2(TargetOpcode::G_FMINNUM_IEEE),
        GIM_CheckType, /*MI*/1, /*Op*/1, /*Type*/GILLT_s16,
        GIM_CheckType, /*MI*/1, /*Op*/2, /*Type*/GILLT_s16,
        GIM_RecordInsn, /*DefineMI*/2, /*MI*/1, /*OpIdx*/1, // MIs[2]
        GIM_CheckOpcode, /*MI*/2, GIMT_Encode2(TargetOpcode::G_FMAXNUM_IEEE),
        GIM_CheckType, /*MI*/2, /*Op*/1, /*Type*/GILLT_s16,
        GIM_CheckType, /*MI*/2, /*Op*/2, /*Type*/GILLT_s16,
        GIM_RecordInsn, /*DefineMI*/3, /*MI*/0, /*OpIdx*/2, // MIs[3]
        GIM_CheckOpcode, /*MI*/3, GIMT_Encode2(TargetOpcode::G_FMINNUM_IEEE),
        // MIs[3] VOP3Mods:src1:src1_mods
        GIM_CheckIsSameOperand, /*MI*/3, /*OpIdx*/1, /*OtherMI*/2, /*OtherOpIdx*/2,
        // MIs[3] VOP3Mods:src0:src0_mods
        GIM_CheckIsSameOperand, /*MI*/3, /*OpIdx*/2, /*OtherMI*/2, /*OtherOpIdx*/1,
        GIM_CheckCxxInsnPredicate, /*MI*/0, /*FnId*/GIMT_Encode2(GICXXPred_MI_Predicate_fmaxnum_like_nnan),
        GIM_CheckIsSafeToFold, /*InsnID*/1,
        GIM_CheckIsSafeToFold, /*InsnID*/2,
        GIM_CheckIsSafeToFold, /*InsnID*/3,
        GIM_CheckComplexPattern, /*MI*/1, /*Op*/2, /*Renderer*/GIMT_Encode2(2), GIMT_Encode2(GICP_gi_vop3mods),
        GIM_CheckComplexPattern, /*MI*/2, /*Op*/1, /*Renderer*/GIMT_Encode2(0), GIMT_Encode2(GICP_gi_vop3mods),
        GIM_CheckComplexPattern, /*MI*/2, /*Op*/2, /*Renderer*/GIMT_Encode2(1), GIMT_Encode2(GICP_gi_vop3mods),
        // (fmaxnum:{ *:[f16] } (fminnum_ieee:{ *:[f16] } (fmaxnum_ieee:{ *:[f16] } (VOP3Mods:{ *:[f16] } f16:{ *:[f16] }:$src0, i32:{ *:[i32] }:$src0_mods), (VOP3Mods:{ *:[f16] } f16:{ *:[f16] }:$src1, i32:{ *:[i32] }:$src1_mods)), (VOP3Mods:{ *:[f16] } f16:{ *:[f16] }:$src2, i32:{ *:[i32] }:$src2_mods)), (fminnum_ieee:{ *:[f16] } (VOP3Mods:{ *:[f16] } f16:{ *:[f16] }:$src1, i32:{ *:[i32] }:$src1_mods), (VOP3Mods:{ *:[f16] } f16:{ *:[f16] }:$src0, i32:{ *:[i32] }:$src0_mods)))<<P:Predicate_fmaxnum_like_nnan>>  =>  (V_MED3_F16_e64:{ *:[f16] } ?:{ *:[i32] }:$src0_mods, ?:{ *:[f16] }:$src0, ?:{ *:[i32] }:$src1_mods, ?:{ *:[f16] }:$src1, ?:{ *:[i32] }:$src2_mods, ?:{ *:[f16] }:$src2, 0:{ *:[i1] })
        GIR_BuildMI, /*InsnID*/0, /*Opcode*/GIMT_Encode2(AMDGPU::V_MED3_F16_e64),
        GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/0, // DstI[vdst]
        GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/1, // src0_mods
        GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/0, // src0
        GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(1), /*SubOperand*/1, // src1_mods
        GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(1), /*SubOperand*/0, // src1
        GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(2), /*SubOperand*/1, // src2_mods
        GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(2), /*SubOperand*/0, // src2
        GIR_AddImm8, /*InsnID*/0, /*Imm*/0,
        GIR_AddImm8, /*InsnID*/0, /*Imm*/0,
        GIR_AddImm8, /*InsnID*/0, /*Imm*/0,
        GIR_ConstrainSelectedInstOperands, /*InsnID*/0,
        GIR_EraseFromParent, /*InsnID*/0,
        // GIR_Coverage, 10658,
        GIR_Done,
      // Label 4597: @306520
      GIM_Try, /*On fail goto*//*Label 4598*/ GIMT_Encode4(306666), // Rule ID 10659 //
        GIM_CheckFeatures, GIMT_Encode2(GIFBS_isGFX9Plus),
        GIM_CheckRegBankForClass, /*MI*/0, /*Op*/0, /*RC*/GIMT_Encode2(AMDGPU::VGPR_32RegClassID),
        GIM_RecordInsn, /*DefineMI*/1, /*MI*/0, /*OpIdx*/1, // MIs[1]
        GIM_CheckOpcode, /*MI*/1, GIMT_Encode2(TargetOpcode::G_FMINNUM_IEEE),
        GIM_CheckType, /*MI*/1, /*Op*/1, /*Type*/GILLT_s16,
        GIM_CheckType, /*MI*/1, /*Op*/2, /*Type*/GILLT_s16,
        GIM_RecordInsn, /*DefineMI*/2, /*MI*/1, /*OpIdx*/1, // MIs[2]
        GIM_CheckOpcode, /*MI*/2, GIMT_Encode2(TargetOpcode::G_FMAXNUM_IEEE),
        GIM_CheckType, /*MI*/2, /*Op*/1, /*Type*/GILLT_s16,
        GIM_CheckType, /*MI*/2, /*Op*/2, /*Type*/GILLT_s16,
        GIM_RecordInsn, /*DefineMI*/3, /*MI*/0, /*OpIdx*/2, // MIs[3]
        GIM_CheckOpcode, /*MI*/3, GIMT_Encode2(TargetOpcode::G_FMINNUM_IEEE),
        // MIs[3] VOP3Mods:src0:src0_mods
        GIM_CheckIsSameOperand, /*MI*/3, /*OpIdx*/1, /*OtherMI*/2, /*OtherOpIdx*/2,
        // MIs[3] VOP3Mods:src1:src1_mods
        GIM_CheckIsSameOperand, /*MI*/3, /*OpIdx*/2, /*OtherMI*/2, /*OtherOpIdx*/1,
        GIM_CheckCxxInsnPredicate, /*MI*/0, /*FnId*/GIMT_Encode2(GICXXPred_MI_Predicate_fmaxnum_like_nnan),
        GIM_CheckIsSafeToFold, /*InsnID*/1,
        GIM_CheckIsSafeToFold, /*InsnID*/2,
        GIM_CheckIsSafeToFold, /*InsnID*/3,
        GIM_CheckComplexPattern, /*MI*/1, /*Op*/2, /*Renderer*/GIMT_Encode2(2), GIMT_Encode2(GICP_gi_vop3mods),
        GIM_CheckComplexPattern, /*MI*/2, /*Op*/1, /*Renderer*/GIMT_Encode2(0), GIMT_Encode2(GICP_gi_vop3mods),
        GIM_CheckComplexPattern, /*MI*/2, /*Op*/2, /*Renderer*/GIMT_Encode2(1), GIMT_Encode2(GICP_gi_vop3mods),
        // (fmaxnum:{ *:[f16] } (fminnum_ieee:{ *:[f16] } (fmaxnum_ieee:{ *:[f16] } (VOP3Mods:{ *:[f16] } f16:{ *:[f16] }:$src1, i32:{ *:[i32] }:$src1_mods), (VOP3Mods:{ *:[f16] } f16:{ *:[f16] }:$src0, i32:{ *:[i32] }:$src0_mods)), (VOP3Mods:{ *:[f16] } f16:{ *:[f16] }:$src2, i32:{ *:[i32] }:$src2_mods)), (fminnum_ieee:{ *:[f16] } (VOP3Mods:{ *:[f16] } f16:{ *:[f16] }:$src0, i32:{ *:[i32] }:$src0_mods), (VOP3Mods:{ *:[f16] } f16:{ *:[f16] }:$src1, i32:{ *:[i32] }:$src1_mods)))<<P:Predicate_fmaxnum_like_nnan>>  =>  (V_MED3_F16_e64:{ *:[f16] } ?:{ *:[i32] }:$src0_mods, ?:{ *:[f16] }:$src0, ?:{ *:[i32] }:$src1_mods, ?:{ *:[f16] }:$src1, ?:{ *:[i32] }:$src2_mods, ?:{ *:[f16] }:$src2, 0:{ *:[i1] })
        GIR_BuildMI, /*InsnID*/0, /*Opcode*/GIMT_Encode2(AMDGPU::V_MED3_F16_e64),
        GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/0, // DstI[vdst]
        GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(1), /*SubOperand*/1, // src0_mods
        GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(1), /*SubOperand*/0, // src0
        GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/1, // src1_mods
        GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/0, // src1
        GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(2), /*SubOperand*/1, // src2_mods
        GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(2), /*SubOperand*/0, // src2
        GIR_AddImm8, /*InsnID*/0, /*Imm*/0,
        GIR_AddImm8, /*InsnID*/0, /*Imm*/0,
        GIR_AddImm8, /*InsnID*/0, /*Imm*/0,
        GIR_ConstrainSelectedInstOperands, /*InsnID*/0,
        GIR_EraseFromParent, /*InsnID*/0,
        // GIR_Coverage, 10659,
        GIR_Done,
      // Label 4598: @306666
      GIM_Try, /*On fail goto*//*Label 4599*/ GIMT_Encode4(306812), // Rule ID 10660 //
        GIM_CheckFeatures, GIMT_Encode2(GIFBS_isGFX9Plus),
        GIM_CheckRegBankForClass, /*MI*/0, /*Op*/0, /*RC*/GIMT_Encode2(AMDGPU::VGPR_32RegClassID),
        GIM_RecordInsn, /*DefineMI*/1, /*MI*/0, /*OpIdx*/1, // MIs[1]
        GIM_CheckOpcode, /*MI*/1, GIMT_Encode2(TargetOpcode::G_FMINNUM_IEEE),
        GIM_CheckType, /*MI*/1, /*Op*/1, /*Type*/GILLT_s16,
        GIM_CheckType, /*MI*/1, /*Op*/2, /*Type*/GILLT_s16,
        GIM_RecordInsn, /*DefineMI*/2, /*MI*/1, /*OpIdx*/1, // MIs[2]
        GIM_CheckOpcode, /*MI*/2, GIMT_Encode2(TargetOpcode::G_FMAXNUM_IEEE),
        GIM_CheckType, /*MI*/2, /*Op*/1, /*Type*/GILLT_s16,
        GIM_CheckType, /*MI*/2, /*Op*/2, /*Type*/GILLT_s16,
        GIM_RecordInsn, /*DefineMI*/3, /*MI*/0, /*OpIdx*/2, // MIs[3]
        GIM_CheckOpcode, /*MI*/3, GIMT_Encode2(TargetOpcode::G_FMINNUM_IEEE),
        // MIs[3] VOP3Mods:src1:src1_mods
        GIM_CheckIsSameOperand, /*MI*/3, /*OpIdx*/1, /*OtherMI*/2, /*OtherOpIdx*/1,
        // MIs[3] VOP3Mods:src0:src0_mods
        GIM_CheckIsSameOperand, /*MI*/3, /*OpIdx*/2, /*OtherMI*/2, /*OtherOpIdx*/2,
        GIM_CheckCxxInsnPredicate, /*MI*/0, /*FnId*/GIMT_Encode2(GICXXPred_MI_Predicate_fmaxnum_like_nnan),
        GIM_CheckIsSafeToFold, /*InsnID*/1,
        GIM_CheckIsSafeToFold, /*InsnID*/2,
        GIM_CheckIsSafeToFold, /*InsnID*/3,
        GIM_CheckComplexPattern, /*MI*/1, /*Op*/2, /*Renderer*/GIMT_Encode2(2), GIMT_Encode2(GICP_gi_vop3mods),
        GIM_CheckComplexPattern, /*MI*/2, /*Op*/1, /*Renderer*/GIMT_Encode2(0), GIMT_Encode2(GICP_gi_vop3mods),
        GIM_CheckComplexPattern, /*MI*/2, /*Op*/2, /*Renderer*/GIMT_Encode2(1), GIMT_Encode2(GICP_gi_vop3mods),
        // (fmaxnum:{ *:[f16] } (fminnum_ieee:{ *:[f16] } (fmaxnum_ieee:{ *:[f16] } (VOP3Mods:{ *:[f16] } f16:{ *:[f16] }:$src1, i32:{ *:[i32] }:$src1_mods), (VOP3Mods:{ *:[f16] } f16:{ *:[f16] }:$src0, i32:{ *:[i32] }:$src0_mods)), (VOP3Mods:{ *:[f16] } f16:{ *:[f16] }:$src2, i32:{ *:[i32] }:$src2_mods)), (fminnum_ieee:{ *:[f16] } (VOP3Mods:{ *:[f16] } f16:{ *:[f16] }:$src1, i32:{ *:[i32] }:$src1_mods), (VOP3Mods:{ *:[f16] } f16:{ *:[f16] }:$src0, i32:{ *:[i32] }:$src0_mods)))<<P:Predicate_fmaxnum_like_nnan>>  =>  (V_MED3_F16_e64:{ *:[f16] } ?:{ *:[i32] }:$src0_mods, ?:{ *:[f16] }:$src0, ?:{ *:[i32] }:$src1_mods, ?:{ *:[f16] }:$src1, ?:{ *:[i32] }:$src2_mods, ?:{ *:[f16] }:$src2, 0:{ *:[i1] })
        GIR_BuildMI, /*InsnID*/0, /*Opcode*/GIMT_Encode2(AMDGPU::V_MED3_F16_e64),
        GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/0, // DstI[vdst]
        GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(1), /*SubOperand*/1, // src0_mods
        GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(1), /*SubOperand*/0, // src0
        GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/1, // src1_mods
        GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/0, // src1
        GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(2), /*SubOperand*/1, // src2_mods
        GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(2), /*SubOperand*/0, // src2
        GIR_AddImm8, /*InsnID*/0, /*Imm*/0,
        GIR_AddImm8, /*InsnID*/0, /*Imm*/0,
        GIR_AddImm8, /*InsnID*/0, /*Imm*/0,
        GIR_ConstrainSelectedInstOperands, /*InsnID*/0,
        GIR_EraseFromParent, /*InsnID*/0,
        // GIR_Coverage, 10660,
        GIR_Done,
      // Label 4599: @306812
      GIM_Try, /*On fail goto*//*Label 4600*/ GIMT_Encode4(306917), // Rule ID 10525 //
        GIM_CheckFeatures, GIMT_Encode2(GIFBS_isGFX11Plus),
        GIM_CheckRegBankForClass, /*MI*/0, /*Op*/0, /*RC*/GIMT_Encode2(AMDGPU::VGPR_32RegClassID),
        GIM_RecordInsn, /*DefineMI*/1, /*MI*/0, /*OpIdx*/2, // MIs[1]
        GIM_CheckOpcode, /*MI*/1, GIMT_Encode2(TargetOpcode::G_FMINNUM),
        GIM_CheckType, /*MI*/1, /*Op*/1, /*Type*/GILLT_s16,
        GIM_CheckType, /*MI*/1, /*Op*/2, /*Type*/GILLT_s16,
        GIM_CheckCxxInsnPredicate, /*MI*/1, /*FnId*/GIMT_Encode2(GICXXPred_MI_Predicate_fminnum_oneuse),
        GIM_CheckIsSafeToFold, /*InsnID*/1,
        GIM_CheckComplexPattern, /*MI*/0, /*Op*/1, /*Renderer*/GIMT_Encode2(0), GIMT_Encode2(GICP_gi_vop3mods),
        GIM_CheckComplexPattern, /*MI*/1, /*Op*/1, /*Renderer*/GIMT_Encode2(1), GIMT_Encode2(GICP_gi_vop3mods),
        GIM_CheckComplexPattern, /*MI*/1, /*Op*/2, /*Renderer*/GIMT_Encode2(2), GIMT_Encode2(GICP_gi_vop3mods),
        // (fmaxnum:{ *:[f16] } (VOP3Mods:{ *:[f16] } f16:{ *:[f16] }:$src2, i32:{ *:[i32] }:$src2_mods), (fminnum:{ *:[f16] } (VOP3Mods:{ *:[f16] } f16:{ *:[f16] }:$src0, i32:{ *:[i32] }:$src0_mods), (VOP3Mods:{ *:[f16] } f16:{ *:[f16] }:$src1, i32:{ *:[i32] }:$src1_mods))<<P:Predicate_fminnum_oneuse>>)  =>  (V_MINMAX_F16_e64:{ *:[f16] } ?:{ *:[i32] }:$src0_mods, ?:{ *:[f16] }:$src0, ?:{ *:[i32] }:$src1_mods, ?:{ *:[f16] }:$src1, ?:{ *:[i32] }:$src2_mods, ?:{ *:[f16] }:$src2, 0:{ *:[i1] }, 0:{ *:[i32] })
        GIR_BuildMI, /*InsnID*/0, /*Opcode*/GIMT_Encode2(AMDGPU::V_MINMAX_F16_e64),
        GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/0, // DstI[vdst]
        GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(1), /*SubOperand*/1, // src0_mods
        GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(1), /*SubOperand*/0, // src0
        GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(2), /*SubOperand*/1, // src1_mods
        GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(2), /*SubOperand*/0, // src1
        GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/1, // src2_mods
        GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/0, // src2
        GIR_AddImm8, /*InsnID*/0, /*Imm*/0,
        GIR_AddImm8, /*InsnID*/0, /*Imm*/0,
        GIR_ConstrainSelectedInstOperands, /*InsnID*/0,
        GIR_EraseFromParent, /*InsnID*/0,
        // GIR_Coverage, 10525,
        GIR_Done,
      // Label 4600: @306917
      GIM_Try, /*On fail goto*//*Label 4601*/ GIMT_Encode4(307022), // Rule ID 10524 //
        GIM_CheckFeatures, GIMT_Encode2(GIFBS_isGFX11Plus),
        GIM_CheckRegBankForClass, /*MI*/0, /*Op*/0, /*RC*/GIMT_Encode2(AMDGPU::VGPR_32RegClassID),
        GIM_RecordInsn, /*DefineMI*/1, /*MI*/0, /*OpIdx*/2, // MIs[1]
        GIM_CheckOpcode, /*MI*/1, GIMT_Encode2(TargetOpcode::G_FMINNUM_IEEE),
        GIM_CheckType, /*MI*/1, /*Op*/1, /*Type*/GILLT_s16,
        GIM_CheckType, /*MI*/1, /*Op*/2, /*Type*/GILLT_s16,
        GIM_CheckCxxInsnPredicate, /*MI*/1, /*FnId*/GIMT_Encode2(GICXXPred_MI_Predicate_fminnum_ieee_oneuse),
        GIM_CheckIsSafeToFold, /*InsnID*/1,
        GIM_CheckComplexPattern, /*MI*/0, /*Op*/1, /*Renderer*/GIMT_Encode2(0), GIMT_Encode2(GICP_gi_vop3mods),
        GIM_CheckComplexPattern, /*MI*/1, /*Op*/1, /*Renderer*/GIMT_Encode2(1), GIMT_Encode2(GICP_gi_vop3mods),
        GIM_CheckComplexPattern, /*MI*/1, /*Op*/2, /*Renderer*/GIMT_Encode2(2), GIMT_Encode2(GICP_gi_vop3mods),
        // (fmaxnum:{ *:[f16] } (VOP3Mods:{ *:[f16] } f16:{ *:[f16] }:$src2, i32:{ *:[i32] }:$src2_mods), (fminnum_ieee:{ *:[f16] } (VOP3Mods:{ *:[f16] } f16:{ *:[f16] }:$src0, i32:{ *:[i32] }:$src0_mods), (VOP3Mods:{ *:[f16] } f16:{ *:[f16] }:$src1, i32:{ *:[i32] }:$src1_mods))<<P:Predicate_fminnum_ieee_oneuse>>)  =>  (V_MINMAX_F16_e64:{ *:[f16] } ?:{ *:[i32] }:$src0_mods, ?:{ *:[f16] }:$src0, ?:{ *:[i32] }:$src1_mods, ?:{ *:[f16] }:$src1, ?:{ *:[i32] }:$src2_mods, ?:{ *:[f16] }:$src2, 0:{ *:[i1] }, 0:{ *:[i32] })
        GIR_BuildMI, /*InsnID*/0, /*Opcode*/GIMT_Encode2(AMDGPU::V_MINMAX_F16_e64),
        GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/0, // DstI[vdst]
        GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(1), /*SubOperand*/1, // src0_mods
        GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(1), /*SubOperand*/0, // src0
        GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(2), /*SubOperand*/1, // src1_mods
        GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(2), /*SubOperand*/0, // src1
        GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/1, // src2_mods
        GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/0, // src2
        GIR_AddImm8, /*InsnID*/0, /*Imm*/0,
        GIR_AddImm8, /*InsnID*/0, /*Imm*/0,
        GIR_ConstrainSelectedInstOperands, /*InsnID*/0,
        GIR_EraseFromParent, /*InsnID*/0,
        // GIR_Coverage, 10524,
        GIR_Done,
      // Label 4601: @307022
      GIM_Try, /*On fail goto*//*Label 4602*/ GIMT_Encode4(307127), // Rule ID 6531 //
        GIM_CheckFeatures, GIMT_Encode2(GIFBS_isGFX11Plus),
        GIM_CheckRegBankForClass, /*MI*/0, /*Op*/0, /*RC*/GIMT_Encode2(AMDGPU::VGPR_32RegClassID),
        GIM_RecordInsn, /*DefineMI*/1, /*MI*/0, /*OpIdx*/1, // MIs[1]
        GIM_CheckOpcode, /*MI*/1, GIMT_Encode2(TargetOpcode::G_FMINNUM),
        GIM_CheckType, /*MI*/1, /*Op*/1, /*Type*/GILLT_s16,
        GIM_CheckType, /*MI*/1, /*Op*/2, /*Type*/GILLT_s16,
        GIM_CheckCxxInsnPredicate, /*MI*/1, /*FnId*/GIMT_Encode2(GICXXPred_MI_Predicate_fminnum_oneuse),
        GIM_CheckIsSafeToFold, /*InsnID*/1,
        GIM_CheckComplexPattern, /*MI*/0, /*Op*/2, /*Renderer*/GIMT_Encode2(2), GIMT_Encode2(GICP_gi_vop3mods),
        GIM_CheckComplexPattern, /*MI*/1, /*Op*/1, /*Renderer*/GIMT_Encode2(0), GIMT_Encode2(GICP_gi_vop3mods),
        GIM_CheckComplexPattern, /*MI*/1, /*Op*/2, /*Renderer*/GIMT_Encode2(1), GIMT_Encode2(GICP_gi_vop3mods),
        // (fmaxnum:{ *:[f16] } (fminnum:{ *:[f16] } (VOP3Mods:{ *:[f16] } f16:{ *:[f16] }:$src0, i32:{ *:[i32] }:$src0_mods), (VOP3Mods:{ *:[f16] } f16:{ *:[f16] }:$src1, i32:{ *:[i32] }:$src1_mods))<<P:Predicate_fminnum_oneuse>>, (VOP3Mods:{ *:[f16] } f16:{ *:[f16] }:$src2, i32:{ *:[i32] }:$src2_mods))  =>  (V_MINMAX_F16_e64:{ *:[f16] } ?:{ *:[i32] }:$src0_mods, ?:{ *:[f16] }:$src0, ?:{ *:[i32] }:$src1_mods, ?:{ *:[f16] }:$src1, ?:{ *:[i32] }:$src2_mods, ?:{ *:[f16] }:$src2, 0:{ *:[i1] }, 0:{ *:[i32] })
        GIR_BuildMI, /*InsnID*/0, /*Opcode*/GIMT_Encode2(AMDGPU::V_MINMAX_F16_e64),
        GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/0, // DstI[vdst]
        GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/1, // src0_mods
        GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/0, // src0
        GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(1), /*SubOperand*/1, // src1_mods
        GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(1), /*SubOperand*/0, // src1
        GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(2), /*SubOperand*/1, // src2_mods
        GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(2), /*SubOperand*/0, // src2
        GIR_AddImm8, /*InsnID*/0, /*Imm*/0,
        GIR_AddImm8, /*InsnID*/0, /*Imm*/0,
        GIR_ConstrainSelectedInstOperands, /*InsnID*/0,
        GIR_EraseFromParent, /*InsnID*/0,
        // GIR_Coverage, 6531,
        GIR_Done,
      // Label 4602: @307127
      GIM_Try, /*On fail goto*//*Label 4603*/ GIMT_Encode4(307232), // Rule ID 6530 //
        GIM_CheckFeatures, GIMT_Encode2(GIFBS_isGFX11Plus),
        GIM_CheckRegBankForClass, /*MI*/0, /*Op*/0, /*RC*/GIMT_Encode2(AMDGPU::VGPR_32RegClassID),
        GIM_RecordInsn, /*DefineMI*/1, /*MI*/0, /*OpIdx*/1, // MIs[1]
        GIM_CheckOpcode, /*MI*/1, GIMT_Encode2(TargetOpcode::G_FMINNUM_IEEE),
        GIM_CheckType, /*MI*/1, /*Op*/1, /*Type*/GILLT_s16,
        GIM_CheckType, /*MI*/1, /*Op*/2, /*Type*/GILLT_s16,
        GIM_CheckCxxInsnPredicate, /*MI*/1, /*FnId*/GIMT_Encode2(GICXXPred_MI_Predicate_fminnum_ieee_oneuse),
        GIM_CheckIsSafeToFold, /*InsnID*/1,
        GIM_CheckComplexPattern, /*MI*/0, /*Op*/2, /*Renderer*/GIMT_Encode2(2), GIMT_Encode2(GICP_gi_vop3mods),
        GIM_CheckComplexPattern, /*MI*/1, /*Op*/1, /*Renderer*/GIMT_Encode2(0), GIMT_Encode2(GICP_gi_vop3mods),
        GIM_CheckComplexPattern, /*MI*/1, /*Op*/2, /*Renderer*/GIMT_Encode2(1), GIMT_Encode2(GICP_gi_vop3mods),
        // (fmaxnum:{ *:[f16] } (fminnum_ieee:{ *:[f16] } (VOP3Mods:{ *:[f16] } f16:{ *:[f16] }:$src0, i32:{ *:[i32] }:$src0_mods), (VOP3Mods:{ *:[f16] } f16:{ *:[f16] }:$src1, i32:{ *:[i32] }:$src1_mods))<<P:Predicate_fminnum_ieee_oneuse>>, (VOP3Mods:{ *:[f16] } f16:{ *:[f16] }:$src2, i32:{ *:[i32] }:$src2_mods))  =>  (V_MINMAX_F16_e64:{ *:[f16] } ?:{ *:[i32] }:$src0_mods, ?:{ *:[f16] }:$src0, ?:{ *:[i32] }:$src1_mods, ?:{ *:[f16] }:$src1, ?:{ *:[i32] }:$src2_mods, ?:{ *:[f16] }:$src2, 0:{ *:[i1] }, 0:{ *:[i32] })
        GIR_BuildMI, /*InsnID*/0, /*Opcode*/GIMT_Encode2(AMDGPU::V_MINMAX_F16_e64),
        GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/0, // DstI[vdst]
        GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/1, // src0_mods
        GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/0, // src0
        GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(1), /*SubOperand*/1, // src1_mods
        GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(1), /*SubOperand*/0, // src1
        GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(2), /*SubOperand*/1, // src2_mods
        GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(2), /*SubOperand*/0, // src2
        GIR_AddImm8, /*InsnID*/0, /*Imm*/0,
        GIR_AddImm8, /*InsnID*/0, /*Imm*/0,
        GIR_ConstrainSelectedInstOperands, /*InsnID*/0,
        GIR_EraseFromParent, /*InsnID*/0,
        // GIR_Coverage, 6530,
        GIR_Done,
      // Label 4603: @307232
      GIM_Try, /*On fail goto*//*Label 4604*/ GIMT_Encode4(307271), // Rule ID 105 //
        GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasSALUFloatInsts),
        GIM_CheckRegBankForClass, /*MI*/0, /*Op*/0, /*RC*/GIMT_Encode2(AMDGPU::SReg_32RegClassID),
        GIM_CheckRegBankForClass, /*MI*/0, /*Op*/1, /*RC*/GIMT_Encode2(AMDGPU::SReg_32RegClassID),
        GIM_CheckRegBankForClass, /*MI*/0, /*Op*/2, /*RC*/GIMT_Encode2(AMDGPU::SReg_32RegClassID),
        GIM_CheckCxxInsnPredicate, /*MI*/0, /*FnId*/GIMT_Encode2(GICXXPred_MI_Predicate_anonymous_17632),
        // (fmaxnum:{ *:[f16] } SSrc_f16:{ *:[f16] }:$src0, SSrc_f16:{ *:[f16] }:$src1)<<P:Predicate_anonymous_17632>>  =>  (S_MAX_F16:{ *:[f16] } SSrc_f16:{ *:[f16] }:$src0, SSrc_f16:{ *:[f16] }:$src1)
        GIR_MutateOpcode, /*InsnID*/0, /*RecycleInsnID*/0, /*Opcode*/GIMT_Encode2(AMDGPU::S_MAX_F16),
        GIR_AddImplicitUse, /*InsnID*/0, GIMT_Encode2(AMDGPU::MODE),
        GIR_ConstrainSelectedInstOperands, /*InsnID*/0,
        // GIR_Coverage, 105,
        GIR_Done,
      // Label 4604: @307271
      GIM_Try, /*On fail goto*//*Label 4605*/ GIMT_Encode4(307341), // Rule ID 814 //
        GIM_CheckFeatures, GIMT_Encode2(GIFBS_Has16BitInsts_NotHasTrue16BitInsts),
        GIM_CheckRegBankForClass, /*MI*/0, /*Op*/0, /*RC*/GIMT_Encode2(AMDGPU::VGPR_32RegClassID),
        GIM_CheckComplexPattern, /*MI*/0, /*Op*/1, /*Renderer*/GIMT_Encode2(0), GIMT_Encode2(GICP_gi_vop3mods0),
        GIM_CheckComplexPattern, /*MI*/0, /*Op*/2, /*Renderer*/GIMT_Encode2(1), GIMT_Encode2(GICP_gi_vop3mods),
        // (fmaxnum:{ *:[f16] } (VOP3Mods0:{ *:[f16] } f16:{ *:[f16] }:$src0, i32:{ *:[i32] }:$src0_modifiers, i1:{ *:[i1] }:$clamp, i32:{ *:[i32] }:$omod), (VOP3Mods:{ *:[f16] } f16:{ *:[f16] }:$src1, i32:{ *:[i32] }:$src1_modifiers))  =>  (V_MAX_F16_e64:{ *:[f16] } i32:{ *:[i32] }:$src0_modifiers, f16:{ *:[f16] }:$src0, i32:{ *:[i32] }:$src1_modifiers, f16:{ *:[f16] }:$src1, i1:{ *:[i1] }:$clamp, i32:{ *:[i32] }:$omod)
        GIR_BuildMI, /*InsnID*/0, /*Opcode*/GIMT_Encode2(AMDGPU::V_MAX_F16_e64),
        GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/0, // DstI[vdst]
        GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/1, // src0_modifiers
        GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/0, // src0
        GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(1), /*SubOperand*/1, // src1_modifiers
        GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(1), /*SubOperand*/0, // src1
        GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/2, // clamp
        GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/3, // omod
        GIR_ConstrainSelectedInstOperands, /*InsnID*/0,
        GIR_EraseFromParent, /*InsnID*/0,
        // GIR_Coverage, 814,
        GIR_Done,
      // Label 4605: @307341
      GIM_Try, /*On fail goto*//*Label 4606*/ GIMT_Encode4(307411), // Rule ID 816 //
        GIM_CheckFeatures, GIMT_Encode2(GIFBS_UseRealTrue16Insts),
        GIM_CheckRegBankForClass, /*MI*/0, /*Op*/0, /*RC*/GIMT_Encode2(AMDGPU::VGPR_16RegClassID),
        GIM_CheckComplexPattern, /*MI*/0, /*Op*/1, /*Renderer*/GIMT_Encode2(0), GIMT_Encode2(GICP_gi_vop3mods0),
        GIM_CheckComplexPattern, /*MI*/0, /*Op*/2, /*Renderer*/GIMT_Encode2(1), GIMT_Encode2(GICP_gi_vop3mods),
        // (fmaxnum:{ *:[f16] } (VOP3Mods0:{ *:[f16] } f16:{ *:[f16] }:$src0, i32:{ *:[i32] }:$src0_modifiers, i1:{ *:[i1] }:$clamp, i32:{ *:[i32] }:$omod), (VOP3Mods:{ *:[f16] } f16:{ *:[f16] }:$src1, i32:{ *:[i32] }:$src1_modifiers))  =>  (V_MAX_F16_t16_e64:{ *:[f16] } i32:{ *:[i32] }:$src0_modifiers, f16:{ *:[f16] }:$src0, i32:{ *:[i32] }:$src1_modifiers, f16:{ *:[f16] }:$src1, i1:{ *:[i1] }:$clamp, i32:{ *:[i32] }:$omod)
        GIR_BuildMI, /*InsnID*/0, /*Opcode*/GIMT_Encode2(AMDGPU::V_MAX_F16_t16_e64),
        GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/0, // DstI[vdst]
        GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/1, // src0_modifiers
        GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/0, // src0
        GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(1), /*SubOperand*/1, // src1_modifiers
        GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(1), /*SubOperand*/0, // src1
        GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/2, // clamp
        GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/3, // omod
        GIR_ConstrainSelectedInstOperands, /*InsnID*/0,
        GIR_EraseFromParent, /*InsnID*/0,
        // GIR_Coverage, 816,
        GIR_Done,
      // Label 4606: @307411
      GIM_Try, /*On fail goto*//*Label 4607*/ GIMT_Encode4(307481), // Rule ID 818 //
        GIM_CheckFeatures, GIMT_Encode2(GIFBS_UseFakeTrue16Insts),
        GIM_CheckRegBankForClass, /*MI*/0, /*Op*/0, /*RC*/GIMT_Encode2(AMDGPU::VGPR_32RegClassID),
        GIM_CheckComplexPattern, /*MI*/0, /*Op*/1, /*Renderer*/GIMT_Encode2(0), GIMT_Encode2(GICP_gi_vop3mods0),
        GIM_CheckComplexPattern, /*MI*/0, /*Op*/2, /*Renderer*/GIMT_Encode2(1), GIMT_Encode2(GICP_gi_vop3mods),
        // (fmaxnum:{ *:[f16] } (VOP3Mods0:{ *:[f16] } f16:{ *:[f16] }:$src0, i32:{ *:[i32] }:$src0_modifiers, i1:{ *:[i1] }:$clamp, i32:{ *:[i32] }:$omod), (VOP3Mods:{ *:[f16] } f16:{ *:[f16] }:$src1, i32:{ *:[i32] }:$src1_modifiers))  =>  (V_MAX_F16_fake16_e64:{ *:[f16] } i32:{ *:[i32] }:$src0_modifiers, f16:{ *:[f16] }:$src0, i32:{ *:[i32] }:$src1_modifiers, f16:{ *:[f16] }:$src1, i1:{ *:[i1] }:$clamp, i32:{ *:[i32] }:$omod)
        GIR_BuildMI, /*InsnID*/0, /*Opcode*/GIMT_Encode2(AMDGPU::V_MAX_F16_fake16_e64),
        GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/0, // DstI[vdst]
        GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/1, // src0_modifiers
        GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/0, // src0
        GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(1), /*SubOperand*/1, // src1_modifiers
        GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(1), /*SubOperand*/0, // src1
        GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/2, // clamp
        GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/3, // omod
        GIR_ConstrainSelectedInstOperands, /*InsnID*/0,
        GIR_EraseFromParent, /*InsnID*/0,
        // GIR_Coverage, 818,
        GIR_Done,
      // Label 4607: @307481
      GIM_Try, /*On fail goto*//*Label 4608*/ GIMT_Encode4(307551), // Rule ID 7149 //
        GIM_CheckFeatures, GIMT_Encode2(GIFBS_Has16BitInsts_NotHasTrue16BitInsts),
        GIM_CheckRegBankForClass, /*MI*/0, /*Op*/0, /*RC*/GIMT_Encode2(AMDGPU::VGPR_32RegClassID),
        GIM_CheckComplexPattern, /*MI*/0, /*Op*/1, /*Renderer*/GIMT_Encode2(0), GIMT_Encode2(GICP_gi_vop3mods),
        GIM_CheckComplexPattern, /*MI*/0, /*Op*/2, /*Renderer*/GIMT_Encode2(1), GIMT_Encode2(GICP_gi_vop3mods0),
        // (fmaxnum:{ *:[f16] } (VOP3Mods:{ *:[f16] } f16:{ *:[f16] }:$src1, i32:{ *:[i32] }:$src1_modifiers), (VOP3Mods0:{ *:[f16] } f16:{ *:[f16] }:$src0, i32:{ *:[i32] }:$src0_modifiers, i1:{ *:[i1] }:$clamp, i32:{ *:[i32] }:$omod))  =>  (V_MAX_F16_e64:{ *:[f16] } i32:{ *:[i32] }:$src0_modifiers, f16:{ *:[f16] }:$src0, i32:{ *:[i32] }:$src1_modifiers, f16:{ *:[f16] }:$src1, i1:{ *:[i1] }:$clamp, i32:{ *:[i32] }:$omod)
        GIR_BuildMI, /*InsnID*/0, /*Opcode*/GIMT_Encode2(AMDGPU::V_MAX_F16_e64),
        GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/0, // DstI[vdst]
        GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(1), /*SubOperand*/1, // src0_modifiers
        GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(1), /*SubOperand*/0, // src0
        GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/1, // src1_modifiers
        GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/0, // src1
        GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(1), /*SubOperand*/2, // clamp
        GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(1), /*SubOperand*/3, // omod
        GIR_ConstrainSelectedInstOperands, /*InsnID*/0,
        GIR_EraseFromParent, /*InsnID*/0,
        // GIR_Coverage, 7149,
        GIR_Done,
      // Label 4608: @307551
      GIM_Try, /*On fail goto*//*Label 4609*/ GIMT_Encode4(307621), // Rule ID 7151 //
        GIM_CheckFeatures, GIMT_Encode2(GIFBS_UseRealTrue16Insts),
        GIM_CheckRegBankForClass, /*MI*/0, /*Op*/0, /*RC*/GIMT_Encode2(AMDGPU::VGPR_16RegClassID),
        GIM_CheckComplexPattern, /*MI*/0, /*Op*/1, /*Renderer*/GIMT_Encode2(0), GIMT_Encode2(GICP_gi_vop3mods),
        GIM_CheckComplexPattern, /*MI*/0, /*Op*/2, /*Renderer*/GIMT_Encode2(1), GIMT_Encode2(GICP_gi_vop3mods0),
        // (fmaxnum:{ *:[f16] } (VOP3Mods:{ *:[f16] } f16:{ *:[f16] }:$src1, i32:{ *:[i32] }:$src1_modifiers), (VOP3Mods0:{ *:[f16] } f16:{ *:[f16] }:$src0, i32:{ *:[i32] }:$src0_modifiers, i1:{ *:[i1] }:$clamp, i32:{ *:[i32] }:$omod))  =>  (V_MAX_F16_t16_e64:{ *:[f16] } i32:{ *:[i32] }:$src0_modifiers, f16:{ *:[f16] }:$src0, i32:{ *:[i32] }:$src1_modifiers, f16:{ *:[f16] }:$src1, i1:{ *:[i1] }:$clamp, i32:{ *:[i32] }:$omod)
        GIR_BuildMI, /*InsnID*/0, /*Opcode*/GIMT_Encode2(AMDGPU::V_MAX_F16_t16_e64),
        GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/0, // DstI[vdst]
        GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(1), /*SubOperand*/1, // src0_modifiers
        GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(1), /*SubOperand*/0, // src0
        GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/1, // src1_modifiers
        GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/0, // src1
        GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(1), /*SubOperand*/2, // clamp
        GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(1), /*SubOperand*/3, // omod
        GIR_ConstrainSelectedInstOperands, /*InsnID*/0,
        GIR_EraseFromParent, /*InsnID*/0,
        // GIR_Coverage, 7151,
        GIR_Done,
      // Label 4609: @307621
      GIM_Try, /*On fail goto*//*Label 4610*/ GIMT_Encode4(307691), // Rule ID 7153 //
        GIM_CheckFeatures, GIMT_Encode2(GIFBS_UseFakeTrue16Insts),
        GIM_CheckRegBankForClass, /*MI*/0, /*Op*/0, /*RC*/GIMT_Encode2(AMDGPU::VGPR_32RegClassID),
        GIM_CheckComplexPattern, /*MI*/0, /*Op*/1, /*Renderer*/GIMT_Encode2(0), GIMT_Encode2(GICP_gi_vop3mods),
        GIM_CheckComplexPattern, /*MI*/0, /*Op*/2, /*Renderer*/GIMT_Encode2(1), GIMT_Encode2(GICP_gi_vop3mods0),
        // (fmaxnum:{ *:[f16] } (VOP3Mods:{ *:[f16] } f16:{ *:[f16] }:$src1, i32:{ *:[i32] }:$src1_modifiers), (VOP3Mods0:{ *:[f16] } f16:{ *:[f16] }:$src0, i32:{ *:[i32] }:$src0_modifiers, i1:{ *:[i1] }:$clamp, i32:{ *:[i32] }:$omod))  =>  (V_MAX_F16_fake16_e64:{ *:[f16] } i32:{ *:[i32] }:$src0_modifiers, f16:{ *:[f16] }:$src0, i32:{ *:[i32] }:$src1_modifiers, f16:{ *:[f16] }:$src1, i1:{ *:[i1] }:$clamp, i32:{ *:[i32] }:$omod)
        GIR_BuildMI, /*InsnID*/0, /*Opcode*/GIMT_Encode2(AMDGPU::V_MAX_F16_fake16_e64),
        GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/0, // DstI[vdst]
        GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(1), /*SubOperand*/1, // src0_modifiers
        GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(1), /*SubOperand*/0, // src0
        GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/1, // src1_modifiers
        GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/0, // src1
        GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(1), /*SubOperand*/2, // clamp
        GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(1), /*SubOperand*/3, // omod
        GIR_ConstrainSelectedInstOperands, /*InsnID*/0,
        GIR_EraseFromParent, /*InsnID*/0,
        // GIR_Coverage, 7153,
        GIR_Done,
      // Label 4610: @307691
      GIM_Reject,
    // Label 4471: @307692
    GIM_Reject,
    // Label 4467: @307693
    GIM_Try, /*On fail goto*//*Label 4611*/ GIMT_Encode4(326220),
      GIM_CheckType, /*MI*/0, /*Op*/1, /*Type*/GILLT_s32,
      GIM_CheckType, /*MI*/0, /*Op*/2, /*Type*/GILLT_s32,
      GIM_Try, /*On fail goto*//*Label 4612*/ GIMT_Encode4(307846), // Rule ID 10226 //
        GIM_CheckRegBankForClass, /*MI*/0, /*Op*/0, /*RC*/GIMT_Encode2(AMDGPU::VGPR_32RegClassID),
        GIM_RecordInsn, /*DefineMI*/1, /*MI*/0, /*OpIdx*/1, // MIs[1]
        GIM_CheckOpcode, /*MI*/1, GIMT_Encode2(TargetOpcode::G_FMINNUM),
        GIM_CheckType, /*MI*/1, /*Op*/1, /*Type*/GILLT_s32,
        GIM_CheckType, /*MI*/1, /*Op*/2, /*Type*/GILLT_s32,
        GIM_RecordInsn, /*DefineMI*/2, /*MI*/0, /*OpIdx*/2, // MIs[2]
        GIM_CheckOpcode, /*MI*/2, GIMT_Encode2(TargetOpcode::G_FMINNUM),
        GIM_CheckType, /*MI*/2, /*Op*/1, /*Type*/GILLT_s32,
        GIM_CheckType, /*MI*/2, /*Op*/2, /*Type*/GILLT_s32,
        GIM_RecordInsn, /*DefineMI*/3, /*MI*/2, /*OpIdx*/2, // MIs[3]
        GIM_CheckOpcode, /*MI*/3, GIMT_Encode2(TargetOpcode::G_FMAXNUM),
        // MIs[3] VOP3Mods:src0:src0_mods
        GIM_CheckIsSameOperand, /*MI*/3, /*OpIdx*/1, /*OtherMI*/1, /*OtherOpIdx*/1,
        // MIs[3] VOP3Mods:src1:src1_mods
        GIM_CheckIsSameOperand, /*MI*/3, /*OpIdx*/2, /*OtherMI*/1, /*OtherOpIdx*/2,
        GIM_CheckCxxInsnPredicate, /*MI*/0, /*FnId*/GIMT_Encode2(GICXXPred_MI_Predicate_fmaxnum_like_nnan),
        GIM_CheckIsSafeToFold, /*InsnID*/1,
        GIM_CheckIsSafeToFold, /*InsnID*/2,
        GIM_CheckIsSafeToFold, /*InsnID*/3,
        GIM_CheckComplexPattern, /*MI*/1, /*Op*/1, /*Renderer*/GIMT_Encode2(0), GIMT_Encode2(GICP_gi_vop3mods),
        GIM_CheckComplexPattern, /*MI*/1, /*Op*/2, /*Renderer*/GIMT_Encode2(1), GIMT_Encode2(GICP_gi_vop3mods),
        GIM_CheckComplexPattern, /*MI*/2, /*Op*/1, /*Renderer*/GIMT_Encode2(2), GIMT_Encode2(GICP_gi_vop3mods),
        // (fmaxnum:{ *:[f32] } (fminnum:{ *:[f32] } (VOP3Mods:{ *:[f32] } f32:{ *:[f32] }:$src0, i32:{ *:[i32] }:$src0_mods), (VOP3Mods:{ *:[f32] } f32:{ *:[f32] }:$src1, i32:{ *:[i32] }:$src1_mods)), (fminnum:{ *:[f32] } (VOP3Mods:{ *:[f32] } f32:{ *:[f32] }:$src2, i32:{ *:[i32] }:$src2_mods), (fmaxnum:{ *:[f32] } (VOP3Mods:{ *:[f32] } f32:{ *:[f32] }:$src0, i32:{ *:[i32] }:$src0_mods), (VOP3Mods:{ *:[f32] } f32:{ *:[f32] }:$src1, i32:{ *:[i32] }:$src1_mods))))<<P:Predicate_fmaxnum_like_nnan>>  =>  (V_MED3_F32_e64:{ *:[f32] } ?:{ *:[i32] }:$src0_mods, ?:{ *:[f32] }:$src0, ?:{ *:[i32] }:$src1_mods, ?:{ *:[f32] }:$src1, ?:{ *:[i32] }:$src2_mods, ?:{ *:[f32] }:$src2, 0:{ *:[i1] }, 0:{ *:[i32] })
        GIR_BuildMI, /*InsnID*/0, /*Opcode*/GIMT_Encode2(AMDGPU::V_MED3_F32_e64),
        GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/0, // DstI[vdst]
        GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/1, // src0_mods
        GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/0, // src0
        GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(1), /*SubOperand*/1, // src1_mods
        GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(1), /*SubOperand*/0, // src1
        GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(2), /*SubOperand*/1, // src2_mods
        GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(2), /*SubOperand*/0, // src2
        GIR_AddImm8, /*InsnID*/0, /*Imm*/0,
        GIR_AddImm8, /*InsnID*/0, /*Imm*/0,
        GIR_ConstrainSelectedInstOperands, /*InsnID*/0,
        GIR_EraseFromParent, /*InsnID*/0,
        // GIR_Coverage, 10226,
        GIR_Done,
      // Label 4612: @307846
      GIM_Try, /*On fail goto*//*Label 4613*/ GIMT_Encode4(307986), // Rule ID 10227 //
        GIM_CheckRegBankForClass, /*MI*/0, /*Op*/0, /*RC*/GIMT_Encode2(AMDGPU::VGPR_32RegClassID),
        GIM_RecordInsn, /*DefineMI*/1, /*MI*/0, /*OpIdx*/1, // MIs[1]
        GIM_CheckOpcode, /*MI*/1, GIMT_Encode2(TargetOpcode::G_FMINNUM),
        GIM_CheckType, /*MI*/1, /*Op*/1, /*Type*/GILLT_s32,
        GIM_CheckType, /*MI*/1, /*Op*/2, /*Type*/GILLT_s32,
        GIM_RecordInsn, /*DefineMI*/2, /*MI*/0, /*OpIdx*/2, // MIs[2]
        GIM_CheckOpcode, /*MI*/2, GIMT_Encode2(TargetOpcode::G_FMINNUM),
        GIM_CheckType, /*MI*/2, /*Op*/1, /*Type*/GILLT_s32,
        GIM_CheckType, /*MI*/2, /*Op*/2, /*Type*/GILLT_s32,
        GIM_RecordInsn, /*DefineMI*/3, /*MI*/2, /*OpIdx*/2, // MIs[3]
        GIM_CheckOpcode, /*MI*/3, GIMT_Encode2(TargetOpcode::G_FMAXNUM),
        // MIs[3] VOP3Mods:src1:src1_mods
        GIM_CheckIsSameOperand, /*MI*/3, /*OpIdx*/1, /*OtherMI*/1, /*OtherOpIdx*/2,
        // MIs[3] VOP3Mods:src0:src0_mods
        GIM_CheckIsSameOperand, /*MI*/3, /*OpIdx*/2, /*OtherMI*/1, /*OtherOpIdx*/1,
        GIM_CheckCxxInsnPredicate, /*MI*/0, /*FnId*/GIMT_Encode2(GICXXPred_MI_Predicate_fmaxnum_like_nnan),
        GIM_CheckIsSafeToFold, /*InsnID*/1,
        GIM_CheckIsSafeToFold, /*InsnID*/2,
        GIM_CheckIsSafeToFold, /*InsnID*/3,
        GIM_CheckComplexPattern, /*MI*/1, /*Op*/1, /*Renderer*/GIMT_Encode2(0), GIMT_Encode2(GICP_gi_vop3mods),
        GIM_CheckComplexPattern, /*MI*/1, /*Op*/2, /*Renderer*/GIMT_Encode2(1), GIMT_Encode2(GICP_gi_vop3mods),
        GIM_CheckComplexPattern, /*MI*/2, /*Op*/1, /*Renderer*/GIMT_Encode2(2), GIMT_Encode2(GICP_gi_vop3mods),
        // (fmaxnum:{ *:[f32] } (fminnum:{ *:[f32] } (VOP3Mods:{ *:[f32] } f32:{ *:[f32] }:$src0, i32:{ *:[i32] }:$src0_mods), (VOP3Mods:{ *:[f32] } f32:{ *:[f32] }:$src1, i32:{ *:[i32] }:$src1_mods)), (fminnum:{ *:[f32] } (VOP3Mods:{ *:[f32] } f32:{ *:[f32] }:$src2, i32:{ *:[i32] }:$src2_mods), (fmaxnum:{ *:[f32] } (VOP3Mods:{ *:[f32] } f32:{ *:[f32] }:$src1, i32:{ *:[i32] }:$src1_mods), (VOP3Mods:{ *:[f32] } f32:{ *:[f32] }:$src0, i32:{ *:[i32] }:$src0_mods))))<<P:Predicate_fmaxnum_like_nnan>>  =>  (V_MED3_F32_e64:{ *:[f32] } ?:{ *:[i32] }:$src0_mods, ?:{ *:[f32] }:$src0, ?:{ *:[i32] }:$src1_mods, ?:{ *:[f32] }:$src1, ?:{ *:[i32] }:$src2_mods, ?:{ *:[f32] }:$src2, 0:{ *:[i1] }, 0:{ *:[i32] })
        GIR_BuildMI, /*InsnID*/0, /*Opcode*/GIMT_Encode2(AMDGPU::V_MED3_F32_e64),
        GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/0, // DstI[vdst]
        GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/1, // src0_mods
        GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/0, // src0
        GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(1), /*SubOperand*/1, // src1_mods
        GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(1), /*SubOperand*/0, // src1
        GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(2), /*SubOperand*/1, // src2_mods
        GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(2), /*SubOperand*/0, // src2
        GIR_AddImm8, /*InsnID*/0, /*Imm*/0,
        GIR_AddImm8, /*InsnID*/0, /*Imm*/0,
        GIR_ConstrainSelectedInstOperands, /*InsnID*/0,
        GIR_EraseFromParent, /*InsnID*/0,
        // GIR_Coverage, 10227,
        GIR_Done,
      // Label 4613: @307986
      GIM_Try, /*On fail goto*//*Label 4614*/ GIMT_Encode4(308126), // Rule ID 10230 //
        GIM_CheckRegBankForClass, /*MI*/0, /*Op*/0, /*RC*/GIMT_Encode2(AMDGPU::VGPR_32RegClassID),
        GIM_RecordInsn, /*DefineMI*/1, /*MI*/0, /*OpIdx*/1, // MIs[1]
        GIM_CheckOpcode, /*MI*/1, GIMT_Encode2(TargetOpcode::G_FMINNUM),
        GIM_CheckType, /*MI*/1, /*Op*/1, /*Type*/GILLT_s32,
        GIM_CheckType, /*MI*/1, /*Op*/2, /*Type*/GILLT_s32,
        GIM_RecordInsn, /*DefineMI*/2, /*MI*/0, /*OpIdx*/2, // MIs[2]
        GIM_CheckOpcode, /*MI*/2, GIMT_Encode2(TargetOpcode::G_FMINNUM),
        GIM_CheckType, /*MI*/2, /*Op*/1, /*Type*/GILLT_s32,
        GIM_CheckType, /*MI*/2, /*Op*/2, /*Type*/GILLT_s32,
        GIM_RecordInsn, /*DefineMI*/3, /*MI*/2, /*OpIdx*/2, // MIs[3]
        GIM_CheckOpcode, /*MI*/3, GIMT_Encode2(TargetOpcode::G_FMAXNUM),
        // MIs[3] VOP3Mods:src0:src0_mods
        GIM_CheckIsSameOperand, /*MI*/3, /*OpIdx*/1, /*OtherMI*/1, /*OtherOpIdx*/2,
        // MIs[3] VOP3Mods:src1:src1_mods
        GIM_CheckIsSameOperand, /*MI*/3, /*OpIdx*/2, /*OtherMI*/1, /*OtherOpIdx*/1,
        GIM_CheckCxxInsnPredicate, /*MI*/0, /*FnId*/GIMT_Encode2(GICXXPred_MI_Predicate_fmaxnum_like_nnan),
        GIM_CheckIsSafeToFold, /*InsnID*/1,
        GIM_CheckIsSafeToFold, /*InsnID*/2,
        GIM_CheckIsSafeToFold, /*InsnID*/3,
        GIM_CheckComplexPattern, /*MI*/1, /*Op*/1, /*Renderer*/GIMT_Encode2(0), GIMT_Encode2(GICP_gi_vop3mods),
        GIM_CheckComplexPattern, /*MI*/1, /*Op*/2, /*Renderer*/GIMT_Encode2(1), GIMT_Encode2(GICP_gi_vop3mods),
        GIM_CheckComplexPattern, /*MI*/2, /*Op*/1, /*Renderer*/GIMT_Encode2(2), GIMT_Encode2(GICP_gi_vop3mods),
        // (fmaxnum:{ *:[f32] } (fminnum:{ *:[f32] } (VOP3Mods:{ *:[f32] } f32:{ *:[f32] }:$src1, i32:{ *:[i32] }:$src1_mods), (VOP3Mods:{ *:[f32] } f32:{ *:[f32] }:$src0, i32:{ *:[i32] }:$src0_mods)), (fminnum:{ *:[f32] } (VOP3Mods:{ *:[f32] } f32:{ *:[f32] }:$src2, i32:{ *:[i32] }:$src2_mods), (fmaxnum:{ *:[f32] } (VOP3Mods:{ *:[f32] } f32:{ *:[f32] }:$src0, i32:{ *:[i32] }:$src0_mods), (VOP3Mods:{ *:[f32] } f32:{ *:[f32] }:$src1, i32:{ *:[i32] }:$src1_mods))))<<P:Predicate_fmaxnum_like_nnan>>  =>  (V_MED3_F32_e64:{ *:[f32] } ?:{ *:[i32] }:$src0_mods, ?:{ *:[f32] }:$src0, ?:{ *:[i32] }:$src1_mods, ?:{ *:[f32] }:$src1, ?:{ *:[i32] }:$src2_mods, ?:{ *:[f32] }:$src2, 0:{ *:[i1] }, 0:{ *:[i32] })
        GIR_BuildMI, /*InsnID*/0, /*Opcode*/GIMT_Encode2(AMDGPU::V_MED3_F32_e64),
        GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/0, // DstI[vdst]
        GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(1), /*SubOperand*/1, // src0_mods
        GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(1), /*SubOperand*/0, // src0
        GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/1, // src1_mods
        GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/0, // src1
        GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(2), /*SubOperand*/1, // src2_mods
        GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(2), /*SubOperand*/0, // src2
        GIR_AddImm8, /*InsnID*/0, /*Imm*/0,
        GIR_AddImm8, /*InsnID*/0, /*Imm*/0,
        GIR_ConstrainSelectedInstOperands, /*InsnID*/0,
        GIR_EraseFromParent, /*InsnID*/0,
        // GIR_Coverage, 10230,
        GIR_Done,
      // Label 4614: @308126
      GIM_Try, /*On fail goto*//*Label 4615*/ GIMT_Encode4(308266), // Rule ID 10231 //
        GIM_CheckRegBankForClass, /*MI*/0, /*Op*/0, /*RC*/GIMT_Encode2(AMDGPU::VGPR_32RegClassID),
        GIM_RecordInsn, /*DefineMI*/1, /*MI*/0, /*OpIdx*/1, // MIs[1]
        GIM_CheckOpcode, /*MI*/1, GIMT_Encode2(TargetOpcode::G_FMINNUM),
        GIM_CheckType, /*MI*/1, /*Op*/1, /*Type*/GILLT_s32,
        GIM_CheckType, /*MI*/1, /*Op*/2, /*Type*/GILLT_s32,
        GIM_RecordInsn, /*DefineMI*/2, /*MI*/0, /*OpIdx*/2, // MIs[2]
        GIM_CheckOpcode, /*MI*/2, GIMT_Encode2(TargetOpcode::G_FMINNUM),
        GIM_CheckType, /*MI*/2, /*Op*/1, /*Type*/GILLT_s32,
        GIM_CheckType, /*MI*/2, /*Op*/2, /*Type*/GILLT_s32,
        GIM_RecordInsn, /*DefineMI*/3, /*MI*/2, /*OpIdx*/2, // MIs[3]
        GIM_CheckOpcode, /*MI*/3, GIMT_Encode2(TargetOpcode::G_FMAXNUM),
        // MIs[3] VOP3Mods:src1:src1_mods
        GIM_CheckIsSameOperand, /*MI*/3, /*OpIdx*/1, /*OtherMI*/1, /*OtherOpIdx*/1,
        // MIs[3] VOP3Mods:src0:src0_mods
        GIM_CheckIsSameOperand, /*MI*/3, /*OpIdx*/2, /*OtherMI*/1, /*OtherOpIdx*/2,
        GIM_CheckCxxInsnPredicate, /*MI*/0, /*FnId*/GIMT_Encode2(GICXXPred_MI_Predicate_fmaxnum_like_nnan),
        GIM_CheckIsSafeToFold, /*InsnID*/1,
        GIM_CheckIsSafeToFold, /*InsnID*/2,
        GIM_CheckIsSafeToFold, /*InsnID*/3,
        GIM_CheckComplexPattern, /*MI*/1, /*Op*/1, /*Renderer*/GIMT_Encode2(0), GIMT_Encode2(GICP_gi_vop3mods),
        GIM_CheckComplexPattern, /*MI*/1, /*Op*/2, /*Renderer*/GIMT_Encode2(1), GIMT_Encode2(GICP_gi_vop3mods),
        GIM_CheckComplexPattern, /*MI*/2, /*Op*/1, /*Renderer*/GIMT_Encode2(2), GIMT_Encode2(GICP_gi_vop3mods),
        // (fmaxnum:{ *:[f32] } (fminnum:{ *:[f32] } (VOP3Mods:{ *:[f32] } f32:{ *:[f32] }:$src1, i32:{ *:[i32] }:$src1_mods), (VOP3Mods:{ *:[f32] } f32:{ *:[f32] }:$src0, i32:{ *:[i32] }:$src0_mods)), (fminnum:{ *:[f32] } (VOP3Mods:{ *:[f32] } f32:{ *:[f32] }:$src2, i32:{ *:[i32] }:$src2_mods), (fmaxnum:{ *:[f32] } (VOP3Mods:{ *:[f32] } f32:{ *:[f32] }:$src1, i32:{ *:[i32] }:$src1_mods), (VOP3Mods:{ *:[f32] } f32:{ *:[f32] }:$src0, i32:{ *:[i32] }:$src0_mods))))<<P:Predicate_fmaxnum_like_nnan>>  =>  (V_MED3_F32_e64:{ *:[f32] } ?:{ *:[i32] }:$src0_mods, ?:{ *:[f32] }:$src0, ?:{ *:[i32] }:$src1_mods, ?:{ *:[f32] }:$src1, ?:{ *:[i32] }:$src2_mods, ?:{ *:[f32] }:$src2, 0:{ *:[i1] }, 0:{ *:[i32] })
        GIR_BuildMI, /*InsnID*/0, /*Opcode*/GIMT_Encode2(AMDGPU::V_MED3_F32_e64),
        GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/0, // DstI[vdst]
        GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(1), /*SubOperand*/1, // src0_mods
        GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(1), /*SubOperand*/0, // src0
        GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/1, // src1_mods
        GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/0, // src1
        GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(2), /*SubOperand*/1, // src2_mods
        GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(2), /*SubOperand*/0, // src2
        GIR_AddImm8, /*InsnID*/0, /*Imm*/0,
        GIR_AddImm8, /*InsnID*/0, /*Imm*/0,
        GIR_ConstrainSelectedInstOperands, /*InsnID*/0,
        GIR_EraseFromParent, /*InsnID*/0,
        // GIR_Coverage, 10231,
        GIR_Done,
      // Label 4615: @308266
      GIM_Try, /*On fail goto*//*Label 4616*/ GIMT_Encode4(308406), // Rule ID 10211 //
        GIM_CheckRegBankForClass, /*MI*/0, /*Op*/0, /*RC*/GIMT_Encode2(AMDGPU::VGPR_32RegClassID),
        GIM_RecordInsn, /*DefineMI*/1, /*MI*/0, /*OpIdx*/1, // MIs[1]
        GIM_CheckOpcode, /*MI*/1, GIMT_Encode2(TargetOpcode::G_FMINNUM),
        GIM_CheckType, /*MI*/1, /*Op*/1, /*Type*/GILLT_s32,
        GIM_CheckType, /*MI*/1, /*Op*/2, /*Type*/GILLT_s32,
        GIM_RecordInsn, /*DefineMI*/2, /*MI*/0, /*OpIdx*/2, // MIs[2]
        GIM_CheckOpcode, /*MI*/2, GIMT_Encode2(TargetOpcode::G_FMINNUM),
        GIM_CheckType, /*MI*/2, /*Op*/1, /*Type*/GILLT_s32,
        GIM_CheckType, /*MI*/2, /*Op*/2, /*Type*/GILLT_s32,
        GIM_RecordInsn, /*DefineMI*/3, /*MI*/2, /*OpIdx*/2, // MIs[3]
        GIM_CheckOpcode, /*MI*/3, GIMT_Encode2(TargetOpcode::G_FMAXNUM_IEEE),
        // MIs[3] VOP3Mods:src0:src0_mods
        GIM_CheckIsSameOperand, /*MI*/3, /*OpIdx*/1, /*OtherMI*/1, /*OtherOpIdx*/1,
        // MIs[3] VOP3Mods:src1:src1_mods
        GIM_CheckIsSameOperand, /*MI*/3, /*OpIdx*/2, /*OtherMI*/1, /*OtherOpIdx*/2,
        GIM_CheckCxxInsnPredicate, /*MI*/0, /*FnId*/GIMT_Encode2(GICXXPred_MI_Predicate_fmaxnum_like_nnan),
        GIM_CheckIsSafeToFold, /*InsnID*/1,
        GIM_CheckIsSafeToFold, /*InsnID*/2,
        GIM_CheckIsSafeToFold, /*InsnID*/3,
        GIM_CheckComplexPattern, /*MI*/1, /*Op*/1, /*Renderer*/GIMT_Encode2(0), GIMT_Encode2(GICP_gi_vop3mods),
        GIM_CheckComplexPattern, /*MI*/1, /*Op*/2, /*Renderer*/GIMT_Encode2(1), GIMT_Encode2(GICP_gi_vop3mods),
        GIM_CheckComplexPattern, /*MI*/2, /*Op*/1, /*Renderer*/GIMT_Encode2(2), GIMT_Encode2(GICP_gi_vop3mods),
        // (fmaxnum:{ *:[f32] } (fminnum:{ *:[f32] } (VOP3Mods:{ *:[f32] } f32:{ *:[f32] }:$src0, i32:{ *:[i32] }:$src0_mods), (VOP3Mods:{ *:[f32] } f32:{ *:[f32] }:$src1, i32:{ *:[i32] }:$src1_mods)), (fminnum:{ *:[f32] } (VOP3Mods:{ *:[f32] } f32:{ *:[f32] }:$src2, i32:{ *:[i32] }:$src2_mods), (fmaxnum_ieee:{ *:[f32] } (VOP3Mods:{ *:[f32] } f32:{ *:[f32] }:$src0, i32:{ *:[i32] }:$src0_mods), (VOP3Mods:{ *:[f32] } f32:{ *:[f32] }:$src1, i32:{ *:[i32] }:$src1_mods))))<<P:Predicate_fmaxnum_like_nnan>>  =>  (V_MED3_F32_e64:{ *:[f32] } ?:{ *:[i32] }:$src0_mods, ?:{ *:[f32] }:$src0, ?:{ *:[i32] }:$src1_mods, ?:{ *:[f32] }:$src1, ?:{ *:[i32] }:$src2_mods, ?:{ *:[f32] }:$src2, 0:{ *:[i1] }, 0:{ *:[i32] })
        GIR_BuildMI, /*InsnID*/0, /*Opcode*/GIMT_Encode2(AMDGPU::V_MED3_F32_e64),
        GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/0, // DstI[vdst]
        GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/1, // src0_mods
        GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/0, // src0
        GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(1), /*SubOperand*/1, // src1_mods
        GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(1), /*SubOperand*/0, // src1
        GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(2), /*SubOperand*/1, // src2_mods
        GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(2), /*SubOperand*/0, // src2
        GIR_AddImm8, /*InsnID*/0, /*Imm*/0,
        GIR_AddImm8, /*InsnID*/0, /*Imm*/0,
        GIR_ConstrainSelectedInstOperands, /*InsnID*/0,
        GIR_EraseFromParent, /*InsnID*/0,
        // GIR_Coverage, 10211,
        GIR_Done,
      // Label 4616: @308406
      GIM_Try, /*On fail goto*//*Label 4617*/ GIMT_Encode4(308546), // Rule ID 10212 //
        GIM_CheckRegBankForClass, /*MI*/0, /*Op*/0, /*RC*/GIMT_Encode2(AMDGPU::VGPR_32RegClassID),
        GIM_RecordInsn, /*DefineMI*/1, /*MI*/0, /*OpIdx*/1, // MIs[1]
        GIM_CheckOpcode, /*MI*/1, GIMT_Encode2(TargetOpcode::G_FMINNUM),
        GIM_CheckType, /*MI*/1, /*Op*/1, /*Type*/GILLT_s32,
        GIM_CheckType, /*MI*/1, /*Op*/2, /*Type*/GILLT_s32,
        GIM_RecordInsn, /*DefineMI*/2, /*MI*/0, /*OpIdx*/2, // MIs[2]
        GIM_CheckOpcode, /*MI*/2, GIMT_Encode2(TargetOpcode::G_FMINNUM),
        GIM_CheckType, /*MI*/2, /*Op*/1, /*Type*/GILLT_s32,
        GIM_CheckType, /*MI*/2, /*Op*/2, /*Type*/GILLT_s32,
        GIM_RecordInsn, /*DefineMI*/3, /*MI*/2, /*OpIdx*/2, // MIs[3]
        GIM_CheckOpcode, /*MI*/3, GIMT_Encode2(TargetOpcode::G_FMAXNUM_IEEE),
        // MIs[3] VOP3Mods:src1:src1_mods
        GIM_CheckIsSameOperand, /*MI*/3, /*OpIdx*/1, /*OtherMI*/1, /*OtherOpIdx*/2,
        // MIs[3] VOP3Mods:src0:src0_mods
        GIM_CheckIsSameOperand, /*MI*/3, /*OpIdx*/2, /*OtherMI*/1, /*OtherOpIdx*/1,
        GIM_CheckCxxInsnPredicate, /*MI*/0, /*FnId*/GIMT_Encode2(GICXXPred_MI_Predicate_fmaxnum_like_nnan),
        GIM_CheckIsSafeToFold, /*InsnID*/1,
        GIM_CheckIsSafeToFold, /*InsnID*/2,
        GIM_CheckIsSafeToFold, /*InsnID*/3,
        GIM_CheckComplexPattern, /*MI*/1, /*Op*/1, /*Renderer*/GIMT_Encode2(0), GIMT_Encode2(GICP_gi_vop3mods),
        GIM_CheckComplexPattern, /*MI*/1, /*Op*/2, /*Renderer*/GIMT_Encode2(1), GIMT_Encode2(GICP_gi_vop3mods),
        GIM_CheckComplexPattern, /*MI*/2, /*Op*/1, /*Renderer*/GIMT_Encode2(2), GIMT_Encode2(GICP_gi_vop3mods),
        // (fmaxnum:{ *:[f32] } (fminnum:{ *:[f32] } (VOP3Mods:{ *:[f32] } f32:{ *:[f32] }:$src0, i32:{ *:[i32] }:$src0_mods), (VOP3Mods:{ *:[f32] } f32:{ *:[f32] }:$src1, i32:{ *:[i32] }:$src1_mods)), (fminnum:{ *:[f32] } (VOP3Mods:{ *:[f32] } f32:{ *:[f32] }:$src2, i32:{ *:[i32] }:$src2_mods), (fmaxnum_ieee:{ *:[f32] } (VOP3Mods:{ *:[f32] } f32:{ *:[f32] }:$src1, i32:{ *:[i32] }:$src1_mods), (VOP3Mods:{ *:[f32] } f32:{ *:[f32] }:$src0, i32:{ *:[i32] }:$src0_mods))))<<P:Predicate_fmaxnum_like_nnan>>  =>  (V_MED3_F32_e64:{ *:[f32] } ?:{ *:[i32] }:$src0_mods, ?:{ *:[f32] }:$src0, ?:{ *:[i32] }:$src1_mods, ?:{ *:[f32] }:$src1, ?:{ *:[i32] }:$src2_mods, ?:{ *:[f32] }:$src2, 0:{ *:[i1] }, 0:{ *:[i32] })
        GIR_BuildMI, /*InsnID*/0, /*Opcode*/GIMT_Encode2(AMDGPU::V_MED3_F32_e64),
        GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/0, // DstI[vdst]
        GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/1, // src0_mods
        GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/0, // src0
        GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(1), /*SubOperand*/1, // src1_mods
        GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(1), /*SubOperand*/0, // src1
        GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(2), /*SubOperand*/1, // src2_mods
        GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(2), /*SubOperand*/0, // src2
        GIR_AddImm8, /*InsnID*/0, /*Imm*/0,
        GIR_AddImm8, /*InsnID*/0, /*Imm*/0,
        GIR_ConstrainSelectedInstOperands, /*InsnID*/0,
        GIR_EraseFromParent, /*InsnID*/0,
        // GIR_Coverage, 10212,
        GIR_Done,
      // Label 4617: @308546
      GIM_Try, /*On fail goto*//*Label 4618*/ GIMT_Encode4(308686), // Rule ID 10215 //
        GIM_CheckRegBankForClass, /*MI*/0, /*Op*/0, /*RC*/GIMT_Encode2(AMDGPU::VGPR_32RegClassID),
        GIM_RecordInsn, /*DefineMI*/1, /*MI*/0, /*OpIdx*/1, // MIs[1]
        GIM_CheckOpcode, /*MI*/1, GIMT_Encode2(TargetOpcode::G_FMINNUM),
        GIM_CheckType, /*MI*/1, /*Op*/1, /*Type*/GILLT_s32,
        GIM_CheckType, /*MI*/1, /*Op*/2, /*Type*/GILLT_s32,
        GIM_RecordInsn, /*DefineMI*/2, /*MI*/0, /*OpIdx*/2, // MIs[2]
        GIM_CheckOpcode, /*MI*/2, GIMT_Encode2(TargetOpcode::G_FMINNUM),
        GIM_CheckType, /*MI*/2, /*Op*/1, /*Type*/GILLT_s32,
        GIM_CheckType, /*MI*/2, /*Op*/2, /*Type*/GILLT_s32,
        GIM_RecordInsn, /*DefineMI*/3, /*MI*/2, /*OpIdx*/2, // MIs[3]
        GIM_CheckOpcode, /*MI*/3, GIMT_Encode2(TargetOpcode::G_FMAXNUM_IEEE),
        // MIs[3] VOP3Mods:src0:src0_mods
        GIM_CheckIsSameOperand, /*MI*/3, /*OpIdx*/1, /*OtherMI*/1, /*OtherOpIdx*/2,
        // MIs[3] VOP3Mods:src1:src1_mods
        GIM_CheckIsSameOperand, /*MI*/3, /*OpIdx*/2, /*OtherMI*/1, /*OtherOpIdx*/1,
        GIM_CheckCxxInsnPredicate, /*MI*/0, /*FnId*/GIMT_Encode2(GICXXPred_MI_Predicate_fmaxnum_like_nnan),
        GIM_CheckIsSafeToFold, /*InsnID*/1,
        GIM_CheckIsSafeToFold, /*InsnID*/2,
        GIM_CheckIsSafeToFold, /*InsnID*/3,
        GIM_CheckComplexPattern, /*MI*/1, /*Op*/1, /*Renderer*/GIMT_Encode2(0), GIMT_Encode2(GICP_gi_vop3mods),
        GIM_CheckComplexPattern, /*MI*/1, /*Op*/2, /*Renderer*/GIMT_Encode2(1), GIMT_Encode2(GICP_gi_vop3mods),
        GIM_CheckComplexPattern, /*MI*/2, /*Op*/1, /*Renderer*/GIMT_Encode2(2), GIMT_Encode2(GICP_gi_vop3mods),
        // (fmaxnum:{ *:[f32] } (fminnum:{ *:[f32] } (VOP3Mods:{ *:[f32] } f32:{ *:[f32] }:$src1, i32:{ *:[i32] }:$src1_mods), (VOP3Mods:{ *:[f32] } f32:{ *:[f32] }:$src0, i32:{ *:[i32] }:$src0_mods)), (fminnum:{ *:[f32] } (VOP3Mods:{ *:[f32] } f32:{ *:[f32] }:$src2, i32:{ *:[i32] }:$src2_mods), (fmaxnum_ieee:{ *:[f32] } (VOP3Mods:{ *:[f32] } f32:{ *:[f32] }:$src0, i32:{ *:[i32] }:$src0_mods), (VOP3Mods:{ *:[f32] } f32:{ *:[f32] }:$src1, i32:{ *:[i32] }:$src1_mods))))<<P:Predicate_fmaxnum_like_nnan>>  =>  (V_MED3_F32_e64:{ *:[f32] } ?:{ *:[i32] }:$src0_mods, ?:{ *:[f32] }:$src0, ?:{ *:[i32] }:$src1_mods, ?:{ *:[f32] }:$src1, ?:{ *:[i32] }:$src2_mods, ?:{ *:[f32] }:$src2, 0:{ *:[i1] }, 0:{ *:[i32] })
        GIR_BuildMI, /*InsnID*/0, /*Opcode*/GIMT_Encode2(AMDGPU::V_MED3_F32_e64),
        GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/0, // DstI[vdst]
        GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(1), /*SubOperand*/1, // src0_mods
        GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(1), /*SubOperand*/0, // src0
        GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/1, // src1_mods
        GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/0, // src1
        GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(2), /*SubOperand*/1, // src2_mods
        GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(2), /*SubOperand*/0, // src2
        GIR_AddImm8, /*InsnID*/0, /*Imm*/0,
        GIR_AddImm8, /*InsnID*/0, /*Imm*/0,
        GIR_ConstrainSelectedInstOperands, /*InsnID*/0,
        GIR_EraseFromParent, /*InsnID*/0,
        // GIR_Coverage, 10215,
        GIR_Done,
      // Label 4618: @308686
      GIM_Try, /*On fail goto*//*Label 4619*/ GIMT_Encode4(308826), // Rule ID 10216 //
        GIM_CheckRegBankForClass, /*MI*/0, /*Op*/0, /*RC*/GIMT_Encode2(AMDGPU::VGPR_32RegClassID),
        GIM_RecordInsn, /*DefineMI*/1, /*MI*/0, /*OpIdx*/1, // MIs[1]
        GIM_CheckOpcode, /*MI*/1, GIMT_Encode2(TargetOpcode::G_FMINNUM),
        GIM_CheckType, /*MI*/1, /*Op*/1, /*Type*/GILLT_s32,
        GIM_CheckType, /*MI*/1, /*Op*/2, /*Type*/GILLT_s32,
        GIM_RecordInsn, /*DefineMI*/2, /*MI*/0, /*OpIdx*/2, // MIs[2]
        GIM_CheckOpcode, /*MI*/2, GIMT_Encode2(TargetOpcode::G_FMINNUM),
        GIM_CheckType, /*MI*/2, /*Op*/1, /*Type*/GILLT_s32,
        GIM_CheckType, /*MI*/2, /*Op*/2, /*Type*/GILLT_s32,
        GIM_RecordInsn, /*DefineMI*/3, /*MI*/2, /*OpIdx*/2, // MIs[3]
        GIM_CheckOpcode, /*MI*/3, GIMT_Encode2(TargetOpcode::G_FMAXNUM_IEEE),
        // MIs[3] VOP3Mods:src1:src1_mods
        GIM_CheckIsSameOperand, /*MI*/3, /*OpIdx*/1, /*OtherMI*/1, /*OtherOpIdx*/1,
        // MIs[3] VOP3Mods:src0:src0_mods
        GIM_CheckIsSameOperand, /*MI*/3, /*OpIdx*/2, /*OtherMI*/1, /*OtherOpIdx*/2,
        GIM_CheckCxxInsnPredicate, /*MI*/0, /*FnId*/GIMT_Encode2(GICXXPred_MI_Predicate_fmaxnum_like_nnan),
        GIM_CheckIsSafeToFold, /*InsnID*/1,
        GIM_CheckIsSafeToFold, /*InsnID*/2,
        GIM_CheckIsSafeToFold, /*InsnID*/3,
        GIM_CheckComplexPattern, /*MI*/1, /*Op*/1, /*Renderer*/GIMT_Encode2(0), GIMT_Encode2(GICP_gi_vop3mods),
        GIM_CheckComplexPattern, /*MI*/1, /*Op*/2, /*Renderer*/GIMT_Encode2(1), GIMT_Encode2(GICP_gi_vop3mods),
        GIM_CheckComplexPattern, /*MI*/2, /*Op*/1, /*Renderer*/GIMT_Encode2(2), GIMT_Encode2(GICP_gi_vop3mods),
        // (fmaxnum:{ *:[f32] } (fminnum:{ *:[f32] } (VOP3Mods:{ *:[f32] } f32:{ *:[f32] }:$src1, i32:{ *:[i32] }:$src1_mods), (VOP3Mods:{ *:[f32] } f32:{ *:[f32] }:$src0, i32:{ *:[i32] }:$src0_mods)), (fminnum:{ *:[f32] } (VOP3Mods:{ *:[f32] } f32:{ *:[f32] }:$src2, i32:{ *:[i32] }:$src2_mods), (fmaxnum_ieee:{ *:[f32] } (VOP3Mods:{ *:[f32] } f32:{ *:[f32] }:$src1, i32:{ *:[i32] }:$src1_mods), (VOP3Mods:{ *:[f32] } f32:{ *:[f32] }:$src0, i32:{ *:[i32] }:$src0_mods))))<<P:Predicate_fmaxnum_like_nnan>>  =>  (V_MED3_F32_e64:{ *:[f32] } ?:{ *:[i32] }:$src0_mods, ?:{ *:[f32] }:$src0, ?:{ *:[i32] }:$src1_mods, ?:{ *:[f32] }:$src1, ?:{ *:[i32] }:$src2_mods, ?:{ *:[f32] }:$src2, 0:{ *:[i1] }, 0:{ *:[i32] })
        GIR_BuildMI, /*InsnID*/0, /*Opcode*/GIMT_Encode2(AMDGPU::V_MED3_F32_e64),
        GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/0, // DstI[vdst]
        GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(1), /*SubOperand*/1, // src0_mods
        GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(1), /*SubOperand*/0, // src0
        GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/1, // src1_mods
        GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/0, // src1
        GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(2), /*SubOperand*/1, // src2_mods
        GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(2), /*SubOperand*/0, // src2
        GIR_AddImm8, /*InsnID*/0, /*Imm*/0,
        GIR_AddImm8, /*InsnID*/0, /*Imm*/0,
        GIR_ConstrainSelectedInstOperands, /*InsnID*/0,
        GIR_EraseFromParent, /*InsnID*/0,
        // GIR_Coverage, 10216,
        GIR_Done,
      // Label 4619: @308826
      GIM_Try, /*On fail goto*//*Label 4620*/ GIMT_Encode4(308966), // Rule ID 6497 //
        GIM_CheckRegBankForClass, /*MI*/0, /*Op*/0, /*RC*/GIMT_Encode2(AMDGPU::VGPR_32RegClassID),
        GIM_RecordInsn, /*DefineMI*/1, /*MI*/0, /*OpIdx*/1, // MIs[1]
        GIM_CheckOpcode, /*MI*/1, GIMT_Encode2(TargetOpcode::G_FMINNUM),
        GIM_CheckType, /*MI*/1, /*Op*/1, /*Type*/GILLT_s32,
        GIM_CheckType, /*MI*/1, /*Op*/2, /*Type*/GILLT_s32,
        GIM_RecordInsn, /*DefineMI*/2, /*MI*/0, /*OpIdx*/2, // MIs[2]
        GIM_CheckOpcode, /*MI*/2, GIMT_Encode2(TargetOpcode::G_FMINNUM),
        GIM_CheckType, /*MI*/2, /*Op*/1, /*Type*/GILLT_s32,
        GIM_CheckType, /*MI*/2, /*Op*/2, /*Type*/GILLT_s32,
        GIM_RecordInsn, /*DefineMI*/3, /*MI*/2, /*OpIdx*/1, // MIs[3]
        GIM_CheckOpcode, /*MI*/3, GIMT_Encode2(TargetOpcode::G_FMAXNUM),
        // MIs[3] VOP3Mods:src0:src0_mods
        GIM_CheckIsSameOperand, /*MI*/3, /*OpIdx*/1, /*OtherMI*/1, /*OtherOpIdx*/1,
        // MIs[3] VOP3Mods:src1:src1_mods
        GIM_CheckIsSameOperand, /*MI*/3, /*OpIdx*/2, /*OtherMI*/1, /*OtherOpIdx*/2,
        GIM_CheckCxxInsnPredicate, /*MI*/0, /*FnId*/GIMT_Encode2(GICXXPred_MI_Predicate_fmaxnum_like_nnan),
        GIM_CheckIsSafeToFold, /*InsnID*/1,
        GIM_CheckIsSafeToFold, /*InsnID*/2,
        GIM_CheckIsSafeToFold, /*InsnID*/3,
        GIM_CheckComplexPattern, /*MI*/1, /*Op*/1, /*Renderer*/GIMT_Encode2(0), GIMT_Encode2(GICP_gi_vop3mods),
        GIM_CheckComplexPattern, /*MI*/1, /*Op*/2, /*Renderer*/GIMT_Encode2(1), GIMT_Encode2(GICP_gi_vop3mods),
        GIM_CheckComplexPattern, /*MI*/2, /*Op*/2, /*Renderer*/GIMT_Encode2(2), GIMT_Encode2(GICP_gi_vop3mods),
        // (fmaxnum:{ *:[f32] } (fminnum:{ *:[f32] } (VOP3Mods:{ *:[f32] } f32:{ *:[f32] }:$src0, i32:{ *:[i32] }:$src0_mods), (VOP3Mods:{ *:[f32] } f32:{ *:[f32] }:$src1, i32:{ *:[i32] }:$src1_mods)), (fminnum:{ *:[f32] } (fmaxnum:{ *:[f32] } (VOP3Mods:{ *:[f32] } f32:{ *:[f32] }:$src0, i32:{ *:[i32] }:$src0_mods), (VOP3Mods:{ *:[f32] } f32:{ *:[f32] }:$src1, i32:{ *:[i32] }:$src1_mods)), (VOP3Mods:{ *:[f32] } f32:{ *:[f32] }:$src2, i32:{ *:[i32] }:$src2_mods)))<<P:Predicate_fmaxnum_like_nnan>>  =>  (V_MED3_F32_e64:{ *:[f32] } ?:{ *:[i32] }:$src0_mods, ?:{ *:[f32] }:$src0, ?:{ *:[i32] }:$src1_mods, ?:{ *:[f32] }:$src1, ?:{ *:[i32] }:$src2_mods, ?:{ *:[f32] }:$src2, 0:{ *:[i1] }, 0:{ *:[i32] })
        GIR_BuildMI, /*InsnID*/0, /*Opcode*/GIMT_Encode2(AMDGPU::V_MED3_F32_e64),
        GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/0, // DstI[vdst]
        GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/1, // src0_mods
        GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/0, // src0
        GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(1), /*SubOperand*/1, // src1_mods
        GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(1), /*SubOperand*/0, // src1
        GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(2), /*SubOperand*/1, // src2_mods
        GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(2), /*SubOperand*/0, // src2
        GIR_AddImm8, /*InsnID*/0, /*Imm*/0,
        GIR_AddImm8, /*InsnID*/0, /*Imm*/0,
        GIR_ConstrainSelectedInstOperands, /*InsnID*/0,
        GIR_EraseFromParent, /*InsnID*/0,
        // GIR_Coverage, 6497,
        GIR_Done,
      // Label 4620: @308966
      GIM_Try, /*On fail goto*//*Label 4621*/ GIMT_Encode4(309106), // Rule ID 10225 //
        GIM_CheckRegBankForClass, /*MI*/0, /*Op*/0, /*RC*/GIMT_Encode2(AMDGPU::VGPR_32RegClassID),
        GIM_RecordInsn, /*DefineMI*/1, /*MI*/0, /*OpIdx*/1, // MIs[1]
        GIM_CheckOpcode, /*MI*/1, GIMT_Encode2(TargetOpcode::G_FMINNUM),
        GIM_CheckType, /*MI*/1, /*Op*/1, /*Type*/GILLT_s32,
        GIM_CheckType, /*MI*/1, /*Op*/2, /*Type*/GILLT_s32,
        GIM_RecordInsn, /*DefineMI*/2, /*MI*/0, /*OpIdx*/2, // MIs[2]
        GIM_CheckOpcode, /*MI*/2, GIMT_Encode2(TargetOpcode::G_FMINNUM),
        GIM_CheckType, /*MI*/2, /*Op*/1, /*Type*/GILLT_s32,
        GIM_CheckType, /*MI*/2, /*Op*/2, /*Type*/GILLT_s32,
        GIM_RecordInsn, /*DefineMI*/3, /*MI*/2, /*OpIdx*/1, // MIs[3]
        GIM_CheckOpcode, /*MI*/3, GIMT_Encode2(TargetOpcode::G_FMAXNUM),
        // MIs[3] VOP3Mods:src1:src1_mods
        GIM_CheckIsSameOperand, /*MI*/3, /*OpIdx*/1, /*OtherMI*/1, /*OtherOpIdx*/2,
        // MIs[3] VOP3Mods:src0:src0_mods
        GIM_CheckIsSameOperand, /*MI*/3, /*OpIdx*/2, /*OtherMI*/1, /*OtherOpIdx*/1,
        GIM_CheckCxxInsnPredicate, /*MI*/0, /*FnId*/GIMT_Encode2(GICXXPred_MI_Predicate_fmaxnum_like_nnan),
        GIM_CheckIsSafeToFold, /*InsnID*/1,
        GIM_CheckIsSafeToFold, /*InsnID*/2,
        GIM_CheckIsSafeToFold, /*InsnID*/3,
        GIM_CheckComplexPattern, /*MI*/1, /*Op*/1, /*Renderer*/GIMT_Encode2(0), GIMT_Encode2(GICP_gi_vop3mods),
        GIM_CheckComplexPattern, /*MI*/1, /*Op*/2, /*Renderer*/GIMT_Encode2(1), GIMT_Encode2(GICP_gi_vop3mods),
        GIM_CheckComplexPattern, /*MI*/2, /*Op*/2, /*Renderer*/GIMT_Encode2(2), GIMT_Encode2(GICP_gi_vop3mods),
        // (fmaxnum:{ *:[f32] } (fminnum:{ *:[f32] } (VOP3Mods:{ *:[f32] } f32:{ *:[f32] }:$src0, i32:{ *:[i32] }:$src0_mods), (VOP3Mods:{ *:[f32] } f32:{ *:[f32] }:$src1, i32:{ *:[i32] }:$src1_mods)), (fminnum:{ *:[f32] } (fmaxnum:{ *:[f32] } (VOP3Mods:{ *:[f32] } f32:{ *:[f32] }:$src1, i32:{ *:[i32] }:$src1_mods), (VOP3Mods:{ *:[f32] } f32:{ *:[f32] }:$src0, i32:{ *:[i32] }:$src0_mods)), (VOP3Mods:{ *:[f32] } f32:{ *:[f32] }:$src2, i32:{ *:[i32] }:$src2_mods)))<<P:Predicate_fmaxnum_like_nnan>>  =>  (V_MED3_F32_e64:{ *:[f32] } ?:{ *:[i32] }:$src0_mods, ?:{ *:[f32] }:$src0, ?:{ *:[i32] }:$src1_mods, ?:{ *:[f32] }:$src1, ?:{ *:[i32] }:$src2_mods, ?:{ *:[f32] }:$src2, 0:{ *:[i1] }, 0:{ *:[i32] })
        GIR_BuildMI, /*InsnID*/0, /*Opcode*/GIMT_Encode2(AMDGPU::V_MED3_F32_e64),
        GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/0, // DstI[vdst]
        GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/1, // src0_mods
        GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/0, // src0
        GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(1), /*SubOperand*/1, // src1_mods
        GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(1), /*SubOperand*/0, // src1
        GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(2), /*SubOperand*/1, // src2_mods
        GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(2), /*SubOperand*/0, // src2
        GIR_AddImm8, /*InsnID*/0, /*Imm*/0,
        GIR_AddImm8, /*InsnID*/0, /*Imm*/0,
        GIR_ConstrainSelectedInstOperands, /*InsnID*/0,
        GIR_EraseFromParent, /*InsnID*/0,
        // GIR_Coverage, 10225,
        GIR_Done,
      // Label 4621: @309106
      GIM_Try, /*On fail goto*//*Label 4622*/ GIMT_Encode4(309246), // Rule ID 10228 //
        GIM_CheckRegBankForClass, /*MI*/0, /*Op*/0, /*RC*/GIMT_Encode2(AMDGPU::VGPR_32RegClassID),
        GIM_RecordInsn, /*DefineMI*/1, /*MI*/0, /*OpIdx*/1, // MIs[1]
        GIM_CheckOpcode, /*MI*/1, GIMT_Encode2(TargetOpcode::G_FMINNUM),
        GIM_CheckType, /*MI*/1, /*Op*/1, /*Type*/GILLT_s32,
        GIM_CheckType, /*MI*/1, /*Op*/2, /*Type*/GILLT_s32,
        GIM_RecordInsn, /*DefineMI*/2, /*MI*/0, /*OpIdx*/2, // MIs[2]
        GIM_CheckOpcode, /*MI*/2, GIMT_Encode2(TargetOpcode::G_FMINNUM),
        GIM_CheckType, /*MI*/2, /*Op*/1, /*Type*/GILLT_s32,
        GIM_CheckType, /*MI*/2, /*Op*/2, /*Type*/GILLT_s32,
        GIM_RecordInsn, /*DefineMI*/3, /*MI*/2, /*OpIdx*/1, // MIs[3]
        GIM_CheckOpcode, /*MI*/3, GIMT_Encode2(TargetOpcode::G_FMAXNUM),
        // MIs[3] VOP3Mods:src0:src0_mods
        GIM_CheckIsSameOperand, /*MI*/3, /*OpIdx*/1, /*OtherMI*/1, /*OtherOpIdx*/2,
        // MIs[3] VOP3Mods:src1:src1_mods
        GIM_CheckIsSameOperand, /*MI*/3, /*OpIdx*/2, /*OtherMI*/1, /*OtherOpIdx*/1,
        GIM_CheckCxxInsnPredicate, /*MI*/0, /*FnId*/GIMT_Encode2(GICXXPred_MI_Predicate_fmaxnum_like_nnan),
        GIM_CheckIsSafeToFold, /*InsnID*/1,
        GIM_CheckIsSafeToFold, /*InsnID*/2,
        GIM_CheckIsSafeToFold, /*InsnID*/3,
        GIM_CheckComplexPattern, /*MI*/1, /*Op*/1, /*Renderer*/GIMT_Encode2(0), GIMT_Encode2(GICP_gi_vop3mods),
        GIM_CheckComplexPattern, /*MI*/1, /*Op*/2, /*Renderer*/GIMT_Encode2(1), GIMT_Encode2(GICP_gi_vop3mods),
        GIM_CheckComplexPattern, /*MI*/2, /*Op*/2, /*Renderer*/GIMT_Encode2(2), GIMT_Encode2(GICP_gi_vop3mods),
        // (fmaxnum:{ *:[f32] } (fminnum:{ *:[f32] } (VOP3Mods:{ *:[f32] } f32:{ *:[f32] }:$src1, i32:{ *:[i32] }:$src1_mods), (VOP3Mods:{ *:[f32] } f32:{ *:[f32] }:$src0, i32:{ *:[i32] }:$src0_mods)), (fminnum:{ *:[f32] } (fmaxnum:{ *:[f32] } (VOP3Mods:{ *:[f32] } f32:{ *:[f32] }:$src0, i32:{ *:[i32] }:$src0_mods), (VOP3Mods:{ *:[f32] } f32:{ *:[f32] }:$src1, i32:{ *:[i32] }:$src1_mods)), (VOP3Mods:{ *:[f32] } f32:{ *:[f32] }:$src2, i32:{ *:[i32] }:$src2_mods)))<<P:Predicate_fmaxnum_like_nnan>>  =>  (V_MED3_F32_e64:{ *:[f32] } ?:{ *:[i32] }:$src0_mods, ?:{ *:[f32] }:$src0, ?:{ *:[i32] }:$src1_mods, ?:{ *:[f32] }:$src1, ?:{ *:[i32] }:$src2_mods, ?:{ *:[f32] }:$src2, 0:{ *:[i1] }, 0:{ *:[i32] })
        GIR_BuildMI, /*InsnID*/0, /*Opcode*/GIMT_Encode2(AMDGPU::V_MED3_F32_e64),
        GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/0, // DstI[vdst]
        GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(1), /*SubOperand*/1, // src0_mods
        GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(1), /*SubOperand*/0, // src0
        GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/1, // src1_mods
        GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/0, // src1
        GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(2), /*SubOperand*/1, // src2_mods
        GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(2), /*SubOperand*/0, // src2
        GIR_AddImm8, /*InsnID*/0, /*Imm*/0,
        GIR_AddImm8, /*InsnID*/0, /*Imm*/0,
        GIR_ConstrainSelectedInstOperands, /*InsnID*/0,
        GIR_EraseFromParent, /*InsnID*/0,
        // GIR_Coverage, 10228,
        GIR_Done,
      // Label 4622: @309246
      GIM_Try, /*On fail goto*//*Label 4623*/ GIMT_Encode4(309386), // Rule ID 10229 //
        GIM_CheckRegBankForClass, /*MI*/0, /*Op*/0, /*RC*/GIMT_Encode2(AMDGPU::VGPR_32RegClassID),
        GIM_RecordInsn, /*DefineMI*/1, /*MI*/0, /*OpIdx*/1, // MIs[1]
        GIM_CheckOpcode, /*MI*/1, GIMT_Encode2(TargetOpcode::G_FMINNUM),
        GIM_CheckType, /*MI*/1, /*Op*/1, /*Type*/GILLT_s32,
        GIM_CheckType, /*MI*/1, /*Op*/2, /*Type*/GILLT_s32,
        GIM_RecordInsn, /*DefineMI*/2, /*MI*/0, /*OpIdx*/2, // MIs[2]
        GIM_CheckOpcode, /*MI*/2, GIMT_Encode2(TargetOpcode::G_FMINNUM),
        GIM_CheckType, /*MI*/2, /*Op*/1, /*Type*/GILLT_s32,
        GIM_CheckType, /*MI*/2, /*Op*/2, /*Type*/GILLT_s32,
        GIM_RecordInsn, /*DefineMI*/3, /*MI*/2, /*OpIdx*/1, // MIs[3]
        GIM_CheckOpcode, /*MI*/3, GIMT_Encode2(TargetOpcode::G_FMAXNUM),
        // MIs[3] VOP3Mods:src1:src1_mods
        GIM_CheckIsSameOperand, /*MI*/3, /*OpIdx*/1, /*OtherMI*/1, /*OtherOpIdx*/1,
        // MIs[3] VOP3Mods:src0:src0_mods
        GIM_CheckIsSameOperand, /*MI*/3, /*OpIdx*/2, /*OtherMI*/1, /*OtherOpIdx*/2,
        GIM_CheckCxxInsnPredicate, /*MI*/0, /*FnId*/GIMT_Encode2(GICXXPred_MI_Predicate_fmaxnum_like_nnan),
        GIM_CheckIsSafeToFold, /*InsnID*/1,
        GIM_CheckIsSafeToFold, /*InsnID*/2,
        GIM_CheckIsSafeToFold, /*InsnID*/3,
        GIM_CheckComplexPattern, /*MI*/1, /*Op*/1, /*Renderer*/GIMT_Encode2(0), GIMT_Encode2(GICP_gi_vop3mods),
        GIM_CheckComplexPattern, /*MI*/1, /*Op*/2, /*Renderer*/GIMT_Encode2(1), GIMT_Encode2(GICP_gi_vop3mods),
        GIM_CheckComplexPattern, /*MI*/2, /*Op*/2, /*Renderer*/GIMT_Encode2(2), GIMT_Encode2(GICP_gi_vop3mods),
        // (fmaxnum:{ *:[f32] } (fminnum:{ *:[f32] } (VOP3Mods:{ *:[f32] } f32:{ *:[f32] }:$src1, i32:{ *:[i32] }:$src1_mods), (VOP3Mods:{ *:[f32] } f32:{ *:[f32] }:$src0, i32:{ *:[i32] }:$src0_mods)), (fminnum:{ *:[f32] } (fmaxnum:{ *:[f32] } (VOP3Mods:{ *:[f32] } f32:{ *:[f32] }:$src1, i32:{ *:[i32] }:$src1_mods), (VOP3Mods:{ *:[f32] } f32:{ *:[f32] }:$src0, i32:{ *:[i32] }:$src0_mods)), (VOP3Mods:{ *:[f32] } f32:{ *:[f32] }:$src2, i32:{ *:[i32] }:$src2_mods)))<<P:Predicate_fmaxnum_like_nnan>>  =>  (V_MED3_F32_e64:{ *:[f32] } ?:{ *:[i32] }:$src0_mods, ?:{ *:[f32] }:$src0, ?:{ *:[i32] }:$src1_mods, ?:{ *:[f32] }:$src1, ?:{ *:[i32] }:$src2_mods, ?:{ *:[f32] }:$src2, 0:{ *:[i1] }, 0:{ *:[i32] })
        GIR_BuildMI, /*InsnID*/0, /*Opcode*/GIMT_Encode2(AMDGPU::V_MED3_F32_e64),
        GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/0, // DstI[vdst]
        GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(1), /*SubOperand*/1, // src0_mods
        GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(1), /*SubOperand*/0, // src0
        GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/1, // src1_mods
        GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/0, // src1
        GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(2), /*SubOperand*/1, // src2_mods
        GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(2), /*SubOperand*/0, // src2
        GIR_AddImm8, /*InsnID*/0, /*Imm*/0,
        GIR_AddImm8, /*InsnID*/0, /*Imm*/0,
        GIR_ConstrainSelectedInstOperands, /*InsnID*/0,
        GIR_EraseFromParent, /*InsnID*/0,
        // GIR_Coverage, 10229,
        GIR_Done,
      // Label 4623: @309386
      GIM_Try, /*On fail goto*//*Label 4624*/ GIMT_Encode4(309526), // Rule ID 6496 //
        GIM_CheckRegBankForClass, /*MI*/0, /*Op*/0, /*RC*/GIMT_Encode2(AMDGPU::VGPR_32RegClassID),
        GIM_RecordInsn, /*DefineMI*/1, /*MI*/0, /*OpIdx*/1, // MIs[1]
        GIM_CheckOpcode, /*MI*/1, GIMT_Encode2(TargetOpcode::G_FMINNUM),
        GIM_CheckType, /*MI*/1, /*Op*/1, /*Type*/GILLT_s32,
        GIM_CheckType, /*MI*/1, /*Op*/2, /*Type*/GILLT_s32,
        GIM_RecordInsn, /*DefineMI*/2, /*MI*/0, /*OpIdx*/2, // MIs[2]
        GIM_CheckOpcode, /*MI*/2, GIMT_Encode2(TargetOpcode::G_FMINNUM),
        GIM_CheckType, /*MI*/2, /*Op*/1, /*Type*/GILLT_s32,
        GIM_CheckType, /*MI*/2, /*Op*/2, /*Type*/GILLT_s32,
        GIM_RecordInsn, /*DefineMI*/3, /*MI*/2, /*OpIdx*/1, // MIs[3]
        GIM_CheckOpcode, /*MI*/3, GIMT_Encode2(TargetOpcode::G_FMAXNUM_IEEE),
        // MIs[3] VOP3Mods:src0:src0_mods
        GIM_CheckIsSameOperand, /*MI*/3, /*OpIdx*/1, /*OtherMI*/1, /*OtherOpIdx*/1,
        // MIs[3] VOP3Mods:src1:src1_mods
        GIM_CheckIsSameOperand, /*MI*/3, /*OpIdx*/2, /*OtherMI*/1, /*OtherOpIdx*/2,
        GIM_CheckCxxInsnPredicate, /*MI*/0, /*FnId*/GIMT_Encode2(GICXXPred_MI_Predicate_fmaxnum_like_nnan),
        GIM_CheckIsSafeToFold, /*InsnID*/1,
        GIM_CheckIsSafeToFold, /*InsnID*/2,
        GIM_CheckIsSafeToFold, /*InsnID*/3,
        GIM_CheckComplexPattern, /*MI*/1, /*Op*/1, /*Renderer*/GIMT_Encode2(0), GIMT_Encode2(GICP_gi_vop3mods),
        GIM_CheckComplexPattern, /*MI*/1, /*Op*/2, /*Renderer*/GIMT_Encode2(1), GIMT_Encode2(GICP_gi_vop3mods),
        GIM_CheckComplexPattern, /*MI*/2, /*Op*/2, /*Renderer*/GIMT_Encode2(2), GIMT_Encode2(GICP_gi_vop3mods),
        // (fmaxnum:{ *:[f32] } (fminnum:{ *:[f32] } (VOP3Mods:{ *:[f32] } f32:{ *:[f32] }:$src0, i32:{ *:[i32] }:$src0_mods), (VOP3Mods:{ *:[f32] } f32:{ *:[f32] }:$src1, i32:{ *:[i32] }:$src1_mods)), (fminnum:{ *:[f32] } (fmaxnum_ieee:{ *:[f32] } (VOP3Mods:{ *:[f32] } f32:{ *:[f32] }:$src0, i32:{ *:[i32] }:$src0_mods), (VOP3Mods:{ *:[f32] } f32:{ *:[f32] }:$src1, i32:{ *:[i32] }:$src1_mods)), (VOP3Mods:{ *:[f32] } f32:{ *:[f32] }:$src2, i32:{ *:[i32] }:$src2_mods)))<<P:Predicate_fmaxnum_like_nnan>>  =>  (V_MED3_F32_e64:{ *:[f32] } ?:{ *:[i32] }:$src0_mods, ?:{ *:[f32] }:$src0, ?:{ *:[i32] }:$src1_mods, ?:{ *:[f32] }:$src1, ?:{ *:[i32] }:$src2_mods, ?:{ *:[f32] }:$src2, 0:{ *:[i1] }, 0:{ *:[i32] })
        GIR_BuildMI, /*InsnID*/0, /*Opcode*/GIMT_Encode2(AMDGPU::V_MED3_F32_e64),
        GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/0, // DstI[vdst]
        GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/1, // src0_mods
        GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/0, // src0
        GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(1), /*SubOperand*/1, // src1_mods
        GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(1), /*SubOperand*/0, // src1
        GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(2), /*SubOperand*/1, // src2_mods
        GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(2), /*SubOperand*/0, // src2
        GIR_AddImm8, /*InsnID*/0, /*Imm*/0,
        GIR_AddImm8, /*InsnID*/0, /*Imm*/0,
        GIR_ConstrainSelectedInstOperands, /*InsnID*/0,
        GIR_EraseFromParent, /*InsnID*/0,
        // GIR_Coverage, 6496,
        GIR_Done,
      // Label 4624: @309526
      GIM_Try, /*On fail goto*//*Label 4625*/ GIMT_Encode4(309666), // Rule ID 10210 //
        GIM_CheckRegBankForClass, /*MI*/0, /*Op*/0, /*RC*/GIMT_Encode2(AMDGPU::VGPR_32RegClassID),
        GIM_RecordInsn, /*DefineMI*/1, /*MI*/0, /*OpIdx*/1, // MIs[1]
        GIM_CheckOpcode, /*MI*/1, GIMT_Encode2(TargetOpcode::G_FMINNUM),
        GIM_CheckType, /*MI*/1, /*Op*/1, /*Type*/GILLT_s32,
        GIM_CheckType, /*MI*/1, /*Op*/2, /*Type*/GILLT_s32,
        GIM_RecordInsn, /*DefineMI*/2, /*MI*/0, /*OpIdx*/2, // MIs[2]
        GIM_CheckOpcode, /*MI*/2, GIMT_Encode2(TargetOpcode::G_FMINNUM),
        GIM_CheckType, /*MI*/2, /*Op*/1, /*Type*/GILLT_s32,
        GIM_CheckType, /*MI*/2, /*Op*/2, /*Type*/GILLT_s32,
        GIM_RecordInsn, /*DefineMI*/3, /*MI*/2, /*OpIdx*/1, // MIs[3]
        GIM_CheckOpcode, /*MI*/3, GIMT_Encode2(TargetOpcode::G_FMAXNUM_IEEE),
        // MIs[3] VOP3Mods:src1:src1_mods
        GIM_CheckIsSameOperand, /*MI*/3, /*OpIdx*/1, /*OtherMI*/1, /*OtherOpIdx*/2,
        // MIs[3] VOP3Mods:src0:src0_mods
        GIM_CheckIsSameOperand, /*MI*/3, /*OpIdx*/2, /*OtherMI*/1, /*OtherOpIdx*/1,
        GIM_CheckCxxInsnPredicate, /*MI*/0, /*FnId*/GIMT_Encode2(GICXXPred_MI_Predicate_fmaxnum_like_nnan),
        GIM_CheckIsSafeToFold, /*InsnID*/1,
        GIM_CheckIsSafeToFold, /*InsnID*/2,
        GIM_CheckIsSafeToFold, /*InsnID*/3,
        GIM_CheckComplexPattern, /*MI*/1, /*Op*/1, /*Renderer*/GIMT_Encode2(0), GIMT_Encode2(GICP_gi_vop3mods),
        GIM_CheckComplexPattern, /*MI*/1, /*Op*/2, /*Renderer*/GIMT_Encode2(1), GIMT_Encode2(GICP_gi_vop3mods),
        GIM_CheckComplexPattern, /*MI*/2, /*Op*/2, /*Renderer*/GIMT_Encode2(2), GIMT_Encode2(GICP_gi_vop3mods),
        // (fmaxnum:{ *:[f32] } (fminnum:{ *:[f32] } (VOP3Mods:{ *:[f32] } f32:{ *:[f32] }:$src0, i32:{ *:[i32] }:$src0_mods), (VOP3Mods:{ *:[f32] } f32:{ *:[f32] }:$src1, i32:{ *:[i32] }:$src1_mods)), (fminnum:{ *:[f32] } (fmaxnum_ieee:{ *:[f32] } (VOP3Mods:{ *:[f32] } f32:{ *:[f32] }:$src1, i32:{ *:[i32] }:$src1_mods), (VOP3Mods:{ *:[f32] } f32:{ *:[f32] }:$src0, i32:{ *:[i32] }:$src0_mods)), (VOP3Mods:{ *:[f32] } f32:{ *:[f32] }:$src2, i32:{ *:[i32] }:$src2_mods)))<<P:Predicate_fmaxnum_like_nnan>>  =>  (V_MED3_F32_e64:{ *:[f32] } ?:{ *:[i32] }:$src0_mods, ?:{ *:[f32] }:$src0, ?:{ *:[i32] }:$src1_mods, ?:{ *:[f32] }:$src1, ?:{ *:[i32] }:$src2_mods, ?:{ *:[f32] }:$src2, 0:{ *:[i1] }, 0:{ *:[i32] })
        GIR_BuildMI, /*InsnID*/0, /*Opcode*/GIMT_Encode2(AMDGPU::V_MED3_F32_e64),
        GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/0, // DstI[vdst]
        GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/1, // src0_mods
        GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/0, // src0
        GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(1), /*SubOperand*/1, // src1_mods
        GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(1), /*SubOperand*/0, // src1
        GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(2), /*SubOperand*/1, // src2_mods
        GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(2), /*SubOperand*/0, // src2
        GIR_AddImm8, /*InsnID*/0, /*Imm*/0,
        GIR_AddImm8, /*InsnID*/0, /*Imm*/0,
        GIR_ConstrainSelectedInstOperands, /*InsnID*/0,
        GIR_EraseFromParent, /*InsnID*/0,
        // GIR_Coverage, 10210,
        GIR_Done,
      // Label 4625: @309666
      GIM_Try, /*On fail goto*//*Label 4626*/ GIMT_Encode4(309806), // Rule ID 10213 //
        GIM_CheckRegBankForClass, /*MI*/0, /*Op*/0, /*RC*/GIMT_Encode2(AMDGPU::VGPR_32RegClassID),
        GIM_RecordInsn, /*DefineMI*/1, /*MI*/0, /*OpIdx*/1, // MIs[1]
        GIM_CheckOpcode, /*MI*/1, GIMT_Encode2(TargetOpcode::G_FMINNUM),
        GIM_CheckType, /*MI*/1, /*Op*/1, /*Type*/GILLT_s32,
        GIM_CheckType, /*MI*/1, /*Op*/2, /*Type*/GILLT_s32,
        GIM_RecordInsn, /*DefineMI*/2, /*MI*/0, /*OpIdx*/2, // MIs[2]
        GIM_CheckOpcode, /*MI*/2, GIMT_Encode2(TargetOpcode::G_FMINNUM),
        GIM_CheckType, /*MI*/2, /*Op*/1, /*Type*/GILLT_s32,
        GIM_CheckType, /*MI*/2, /*Op*/2, /*Type*/GILLT_s32,
        GIM_RecordInsn, /*DefineMI*/3, /*MI*/2, /*OpIdx*/1, // MIs[3]
        GIM_CheckOpcode, /*MI*/3, GIMT_Encode2(TargetOpcode::G_FMAXNUM_IEEE),
        // MIs[3] VOP3Mods:src0:src0_mods
        GIM_CheckIsSameOperand, /*MI*/3, /*OpIdx*/1, /*OtherMI*/1, /*OtherOpIdx*/2,
        // MIs[3] VOP3Mods:src1:src1_mods
        GIM_CheckIsSameOperand, /*MI*/3, /*OpIdx*/2, /*OtherMI*/1, /*OtherOpIdx*/1,
        GIM_CheckCxxInsnPredicate, /*MI*/0, /*FnId*/GIMT_Encode2(GICXXPred_MI_Predicate_fmaxnum_like_nnan),
        GIM_CheckIsSafeToFold, /*InsnID*/1,
        GIM_CheckIsSafeToFold, /*InsnID*/2,
        GIM_CheckIsSafeToFold, /*InsnID*/3,
        GIM_CheckComplexPattern, /*MI*/1, /*Op*/1, /*Renderer*/GIMT_Encode2(0), GIMT_Encode2(GICP_gi_vop3mods),
        GIM_CheckComplexPattern, /*MI*/1, /*Op*/2, /*Renderer*/GIMT_Encode2(1), GIMT_Encode2(GICP_gi_vop3mods),
        GIM_CheckComplexPattern, /*MI*/2, /*Op*/2, /*Renderer*/GIMT_Encode2(2), GIMT_Encode2(GICP_gi_vop3mods),
        // (fmaxnum:{ *:[f32] } (fminnum:{ *:[f32] } (VOP3Mods:{ *:[f32] } f32:{ *:[f32] }:$src1, i32:{ *:[i32] }:$src1_mods), (VOP3Mods:{ *:[f32] } f32:{ *:[f32] }:$src0, i32:{ *:[i32] }:$src0_mods)), (fminnum:{ *:[f32] } (fmaxnum_ieee:{ *:[f32] } (VOP3Mods:{ *:[f32] } f32:{ *:[f32] }:$src0, i32:{ *:[i32] }:$src0_mods), (VOP3Mods:{ *:[f32] } f32:{ *:[f32] }:$src1, i32:{ *:[i32] }:$src1_mods)), (VOP3Mods:{ *:[f32] } f32:{ *:[f32] }:$src2, i32:{ *:[i32] }:$src2_mods)))<<P:Predicate_fmaxnum_like_nnan>>  =>  (V_MED3_F32_e64:{ *:[f32] } ?:{ *:[i32] }:$src0_mods, ?:{ *:[f32] }:$src0, ?:{ *:[i32] }:$src1_mods, ?:{ *:[f32] }:$src1, ?:{ *:[i32] }:$src2_mods, ?:{ *:[f32] }:$src2, 0:{ *:[i1] }, 0:{ *:[i32] })
        GIR_BuildMI, /*InsnID*/0, /*Opcode*/GIMT_Encode2(AMDGPU::V_MED3_F32_e64),
        GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/0, // DstI[vdst]
        GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(1), /*SubOperand*/1, // src0_mods
        GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(1), /*SubOperand*/0, // src0
        GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/1, // src1_mods
        GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/0, // src1
        GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(2), /*SubOperand*/1, // src2_mods
        GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(2), /*SubOperand*/0, // src2
        GIR_AddImm8, /*InsnID*/0, /*Imm*/0,
        GIR_AddImm8, /*InsnID*/0, /*Imm*/0,
        GIR_ConstrainSelectedInstOperands, /*InsnID*/0,
        GIR_EraseFromParent, /*InsnID*/0,
        // GIR_Coverage, 10213,
        GIR_Done,
      // Label 4626: @309806
      GIM_Try, /*On fail goto*//*Label 4627*/ GIMT_Encode4(309946), // Rule ID 10214 //
        GIM_CheckRegBankForClass, /*MI*/0, /*Op*/0, /*RC*/GIMT_Encode2(AMDGPU::VGPR_32RegClassID),
        GIM_RecordInsn, /*DefineMI*/1, /*MI*/0, /*OpIdx*/1, // MIs[1]
        GIM_CheckOpcode, /*MI*/1, GIMT_Encode2(TargetOpcode::G_FMINNUM),
        GIM_CheckType, /*MI*/1, /*Op*/1, /*Type*/GILLT_s32,
        GIM_CheckType, /*MI*/1, /*Op*/2, /*Type*/GILLT_s32,
        GIM_RecordInsn, /*DefineMI*/2, /*MI*/0, /*OpIdx*/2, // MIs[2]
        GIM_CheckOpcode, /*MI*/2, GIMT_Encode2(TargetOpcode::G_FMINNUM),
        GIM_CheckType, /*MI*/2, /*Op*/1, /*Type*/GILLT_s32,
        GIM_CheckType, /*MI*/2, /*Op*/2, /*Type*/GILLT_s32,
        GIM_RecordInsn, /*DefineMI*/3, /*MI*/2, /*OpIdx*/1, // MIs[3]
        GIM_CheckOpcode, /*MI*/3, GIMT_Encode2(TargetOpcode::G_FMAXNUM_IEEE),
        // MIs[3] VOP3Mods:src1:src1_mods
        GIM_CheckIsSameOperand, /*MI*/3, /*OpIdx*/1, /*OtherMI*/1, /*OtherOpIdx*/1,
        // MIs[3] VOP3Mods:src0:src0_mods
        GIM_CheckIsSameOperand, /*MI*/3, /*OpIdx*/2, /*OtherMI*/1, /*OtherOpIdx*/2,
        GIM_CheckCxxInsnPredicate, /*MI*/0, /*FnId*/GIMT_Encode2(GICXXPred_MI_Predicate_fmaxnum_like_nnan),
        GIM_CheckIsSafeToFold, /*InsnID*/1,
        GIM_CheckIsSafeToFold, /*InsnID*/2,
        GIM_CheckIsSafeToFold, /*InsnID*/3,
        GIM_CheckComplexPattern, /*MI*/1, /*Op*/1, /*Renderer*/GIMT_Encode2(0), GIMT_Encode2(GICP_gi_vop3mods),
        GIM_CheckComplexPattern, /*MI*/1, /*Op*/2, /*Renderer*/GIMT_Encode2(1), GIMT_Encode2(GICP_gi_vop3mods),
        GIM_CheckComplexPattern, /*MI*/2, /*Op*/2, /*Renderer*/GIMT_Encode2(2), GIMT_Encode2(GICP_gi_vop3mods),
        // (fmaxnum:{ *:[f32] } (fminnum:{ *:[f32] } (VOP3Mods:{ *:[f32] } f32:{ *:[f32] }:$src1, i32:{ *:[i32] }:$src1_mods), (VOP3Mods:{ *:[f32] } f32:{ *:[f32] }:$src0, i32:{ *:[i32] }:$src0_mods)), (fminnum:{ *:[f32] } (fmaxnum_ieee:{ *:[f32] } (VOP3Mods:{ *:[f32] } f32:{ *:[f32] }:$src1, i32:{ *:[i32] }:$src1_mods), (VOP3Mods:{ *:[f32] } f32:{ *:[f32] }:$src0, i32:{ *:[i32] }:$src0_mods)), (VOP3Mods:{ *:[f32] } f32:{ *:[f32] }:$src2, i32:{ *:[i32] }:$src2_mods)))<<P:Predicate_fmaxnum_like_nnan>>  =>  (V_MED3_F32_e64:{ *:[f32] } ?:{ *:[i32] }:$src0_mods, ?:{ *:[f32] }:$src0, ?:{ *:[i32] }:$src1_mods, ?:{ *:[f32] }:$src1, ?:{ *:[i32] }:$src2_mods, ?:{ *:[f32] }:$src2, 0:{ *:[i1] }, 0:{ *:[i32] })
        GIR_BuildMI, /*InsnID*/0, /*Opcode*/GIMT_Encode2(AMDGPU::V_MED3_F32_e64),
        GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/0, // DstI[vdst]
        GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(1), /*SubOperand*/1, // src0_mods
        GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(1), /*SubOperand*/0, // src0
        GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/1, // src1_mods
        GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/0, // src1
        GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(2), /*SubOperand*/1, // src2_mods
        GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(2), /*SubOperand*/0, // src2
        GIR_AddImm8, /*InsnID*/0, /*Imm*/0,
        GIR_AddImm8, /*InsnID*/0, /*Imm*/0,
        GIR_ConstrainSelectedInstOperands, /*InsnID*/0,
        GIR_EraseFromParent, /*InsnID*/0,
        // GIR_Coverage, 10214,
        GIR_Done,
      // Label 4627: @309946
      GIM_Try, /*On fail goto*//*Label 4628*/ GIMT_Encode4(310086), // Rule ID 10196 //
        GIM_CheckRegBankForClass, /*MI*/0, /*Op*/0, /*RC*/GIMT_Encode2(AMDGPU::VGPR_32RegClassID),
        GIM_RecordInsn, /*DefineMI*/1, /*MI*/0, /*OpIdx*/1, // MIs[1]
        GIM_CheckOpcode, /*MI*/1, GIMT_Encode2(TargetOpcode::G_FMINNUM),
        GIM_CheckType, /*MI*/1, /*Op*/1, /*Type*/GILLT_s32,
        GIM_CheckType, /*MI*/1, /*Op*/2, /*Type*/GILLT_s32,
        GIM_RecordInsn, /*DefineMI*/2, /*MI*/0, /*OpIdx*/2, // MIs[2]
        GIM_CheckOpcode, /*MI*/2, GIMT_Encode2(TargetOpcode::G_FMINNUM_IEEE),
        GIM_CheckType, /*MI*/2, /*Op*/1, /*Type*/GILLT_s32,
        GIM_CheckType, /*MI*/2, /*Op*/2, /*Type*/GILLT_s32,
        GIM_RecordInsn, /*DefineMI*/3, /*MI*/2, /*OpIdx*/2, // MIs[3]
        GIM_CheckOpcode, /*MI*/3, GIMT_Encode2(TargetOpcode::G_FMAXNUM),
        // MIs[3] VOP3Mods:src0:src0_mods
        GIM_CheckIsSameOperand, /*MI*/3, /*OpIdx*/1, /*OtherMI*/1, /*OtherOpIdx*/1,
        // MIs[3] VOP3Mods:src1:src1_mods
        GIM_CheckIsSameOperand, /*MI*/3, /*OpIdx*/2, /*OtherMI*/1, /*OtherOpIdx*/2,
        GIM_CheckCxxInsnPredicate, /*MI*/0, /*FnId*/GIMT_Encode2(GICXXPred_MI_Predicate_fmaxnum_like_nnan),
        GIM_CheckIsSafeToFold, /*InsnID*/1,
        GIM_CheckIsSafeToFold, /*InsnID*/2,
        GIM_CheckIsSafeToFold, /*InsnID*/3,
        GIM_CheckComplexPattern, /*MI*/1, /*Op*/1, /*Renderer*/GIMT_Encode2(0), GIMT_Encode2(GICP_gi_vop3mods),
        GIM_CheckComplexPattern, /*MI*/1, /*Op*/2, /*Renderer*/GIMT_Encode2(1), GIMT_Encode2(GICP_gi_vop3mods),
        GIM_CheckComplexPattern, /*MI*/2, /*Op*/1, /*Renderer*/GIMT_Encode2(2), GIMT_Encode2(GICP_gi_vop3mods),
        // (fmaxnum:{ *:[f32] } (fminnum:{ *:[f32] } (VOP3Mods:{ *:[f32] } f32:{ *:[f32] }:$src0, i32:{ *:[i32] }:$src0_mods), (VOP3Mods:{ *:[f32] } f32:{ *:[f32] }:$src1, i32:{ *:[i32] }:$src1_mods)), (fminnum_ieee:{ *:[f32] } (VOP3Mods:{ *:[f32] } f32:{ *:[f32] }:$src2, i32:{ *:[i32] }:$src2_mods), (fmaxnum:{ *:[f32] } (VOP3Mods:{ *:[f32] } f32:{ *:[f32] }:$src0, i32:{ *:[i32] }:$src0_mods), (VOP3Mods:{ *:[f32] } f32:{ *:[f32] }:$src1, i32:{ *:[i32] }:$src1_mods))))<<P:Predicate_fmaxnum_like_nnan>>  =>  (V_MED3_F32_e64:{ *:[f32] } ?:{ *:[i32] }:$src0_mods, ?:{ *:[f32] }:$src0, ?:{ *:[i32] }:$src1_mods, ?:{ *:[f32] }:$src1, ?:{ *:[i32] }:$src2_mods, ?:{ *:[f32] }:$src2, 0:{ *:[i1] }, 0:{ *:[i32] })
        GIR_BuildMI, /*InsnID*/0, /*Opcode*/GIMT_Encode2(AMDGPU::V_MED3_F32_e64),
        GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/0, // DstI[vdst]
        GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/1, // src0_mods
        GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/0, // src0
        GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(1), /*SubOperand*/1, // src1_mods
        GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(1), /*SubOperand*/0, // src1
        GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(2), /*SubOperand*/1, // src2_mods
        GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(2), /*SubOperand*/0, // src2
        GIR_AddImm8, /*InsnID*/0, /*Imm*/0,
        GIR_AddImm8, /*InsnID*/0, /*Imm*/0,
        GIR_ConstrainSelectedInstOperands, /*InsnID*/0,
        GIR_EraseFromParent, /*InsnID*/0,
        // GIR_Coverage, 10196,
        GIR_Done,
      // Label 4628: @310086
      GIM_Try, /*On fail goto*//*Label 4629*/ GIMT_Encode4(310226), // Rule ID 10197 //
        GIM_CheckRegBankForClass, /*MI*/0, /*Op*/0, /*RC*/GIMT_Encode2(AMDGPU::VGPR_32RegClassID),
        GIM_RecordInsn, /*DefineMI*/1, /*MI*/0, /*OpIdx*/1, // MIs[1]
        GIM_CheckOpcode, /*MI*/1, GIMT_Encode2(TargetOpcode::G_FMINNUM),
        GIM_CheckType, /*MI*/1, /*Op*/1, /*Type*/GILLT_s32,
        GIM_CheckType, /*MI*/1, /*Op*/2, /*Type*/GILLT_s32,
        GIM_RecordInsn, /*DefineMI*/2, /*MI*/0, /*OpIdx*/2, // MIs[2]
        GIM_CheckOpcode, /*MI*/2, GIMT_Encode2(TargetOpcode::G_FMINNUM_IEEE),
        GIM_CheckType, /*MI*/2, /*Op*/1, /*Type*/GILLT_s32,
        GIM_CheckType, /*MI*/2, /*Op*/2, /*Type*/GILLT_s32,
        GIM_RecordInsn, /*DefineMI*/3, /*MI*/2, /*OpIdx*/2, // MIs[3]
        GIM_CheckOpcode, /*MI*/3, GIMT_Encode2(TargetOpcode::G_FMAXNUM),
        // MIs[3] VOP3Mods:src1:src1_mods
        GIM_CheckIsSameOperand, /*MI*/3, /*OpIdx*/1, /*OtherMI*/1, /*OtherOpIdx*/2,
        // MIs[3] VOP3Mods:src0:src0_mods
        GIM_CheckIsSameOperand, /*MI*/3, /*OpIdx*/2, /*OtherMI*/1, /*OtherOpIdx*/1,
        GIM_CheckCxxInsnPredicate, /*MI*/0, /*FnId*/GIMT_Encode2(GICXXPred_MI_Predicate_fmaxnum_like_nnan),
        GIM_CheckIsSafeToFold, /*InsnID*/1,
        GIM_CheckIsSafeToFold, /*InsnID*/2,
        GIM_CheckIsSafeToFold, /*InsnID*/3,
        GIM_CheckComplexPattern, /*MI*/1, /*Op*/1, /*Renderer*/GIMT_Encode2(0), GIMT_Encode2(GICP_gi_vop3mods),
        GIM_CheckComplexPattern, /*MI*/1, /*Op*/2, /*Renderer*/GIMT_Encode2(1), GIMT_Encode2(GICP_gi_vop3mods),
        GIM_CheckComplexPattern, /*MI*/2, /*Op*/1, /*Renderer*/GIMT_Encode2(2), GIMT_Encode2(GICP_gi_vop3mods),
        // (fmaxnum:{ *:[f32] } (fminnum:{ *:[f32] } (VOP3Mods:{ *:[f32] } f32:{ *:[f32] }:$src0, i32:{ *:[i32] }:$src0_mods), (VOP3Mods:{ *:[f32] } f32:{ *:[f32] }:$src1, i32:{ *:[i32] }:$src1_mods)), (fminnum_ieee:{ *:[f32] } (VOP3Mods:{ *:[f32] } f32:{ *:[f32] }:$src2, i32:{ *:[i32] }:$src2_mods), (fmaxnum:{ *:[f32] } (VOP3Mods:{ *:[f32] } f32:{ *:[f32] }:$src1, i32:{ *:[i32] }:$src1_mods), (VOP3Mods:{ *:[f32] } f32:{ *:[f32] }:$src0, i32:{ *:[i32] }:$src0_mods))))<<P:Predicate_fmaxnum_like_nnan>>  =>  (V_MED3_F32_e64:{ *:[f32] } ?:{ *:[i32] }:$src0_mods, ?:{ *:[f32] }:$src0, ?:{ *:[i32] }:$src1_mods, ?:{ *:[f32] }:$src1, ?:{ *:[i32] }:$src2_mods, ?:{ *:[f32] }:$src2, 0:{ *:[i1] }, 0:{ *:[i32] })
        GIR_BuildMI, /*InsnID*/0, /*Opcode*/GIMT_Encode2(AMDGPU::V_MED3_F32_e64),
        GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/0, // DstI[vdst]
        GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/1, // src0_mods
        GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/0, // src0
        GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(1), /*SubOperand*/1, // src1_mods
        GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(1), /*SubOperand*/0, // src1
        GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(2), /*SubOperand*/1, // src2_mods
        GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(2), /*SubOperand*/0, // src2
        GIR_AddImm8, /*InsnID*/0, /*Imm*/0,
        GIR_AddImm8, /*InsnID*/0, /*Imm*/0,
        GIR_ConstrainSelectedInstOperands, /*InsnID*/0,
        GIR_EraseFromParent, /*InsnID*/0,
        // GIR_Coverage, 10197,
        GIR_Done,
      // Label 4629: @310226
      GIM_Try, /*On fail goto*//*Label 4630*/ GIMT_Encode4(310366), // Rule ID 10200 //
        GIM_CheckRegBankForClass, /*MI*/0, /*Op*/0, /*RC*/GIMT_Encode2(AMDGPU::VGPR_32RegClassID),
        GIM_RecordInsn, /*DefineMI*/1, /*MI*/0, /*OpIdx*/1, // MIs[1]
        GIM_CheckOpcode, /*MI*/1, GIMT_Encode2(TargetOpcode::G_FMINNUM),
        GIM_CheckType, /*MI*/1, /*Op*/1, /*Type*/GILLT_s32,
        GIM_CheckType, /*MI*/1, /*Op*/2, /*Type*/GILLT_s32,
        GIM_RecordInsn, /*DefineMI*/2, /*MI*/0, /*OpIdx*/2, // MIs[2]
        GIM_CheckOpcode, /*MI*/2, GIMT_Encode2(TargetOpcode::G_FMINNUM_IEEE),
        GIM_CheckType, /*MI*/2, /*Op*/1, /*Type*/GILLT_s32,
        GIM_CheckType, /*MI*/2, /*Op*/2, /*Type*/GILLT_s32,
        GIM_RecordInsn, /*DefineMI*/3, /*MI*/2, /*OpIdx*/2, // MIs[3]
        GIM_CheckOpcode, /*MI*/3, GIMT_Encode2(TargetOpcode::G_FMAXNUM),
        // MIs[3] VOP3Mods:src0:src0_mods
        GIM_CheckIsSameOperand, /*MI*/3, /*OpIdx*/1, /*OtherMI*/1, /*OtherOpIdx*/2,
        // MIs[3] VOP3Mods:src1:src1_mods
        GIM_CheckIsSameOperand, /*MI*/3, /*OpIdx*/2, /*OtherMI*/1, /*OtherOpIdx*/1,
        GIM_CheckCxxInsnPredicate, /*MI*/0, /*FnId*/GIMT_Encode2(GICXXPred_MI_Predicate_fmaxnum_like_nnan),
        GIM_CheckIsSafeToFold, /*InsnID*/1,
        GIM_CheckIsSafeToFold, /*InsnID*/2,
        GIM_CheckIsSafeToFold, /*InsnID*/3,
        GIM_CheckComplexPattern, /*MI*/1, /*Op*/1, /*Renderer*/GIMT_Encode2(0), GIMT_Encode2(GICP_gi_vop3mods),
        GIM_CheckComplexPattern, /*MI*/1, /*Op*/2, /*Renderer*/GIMT_Encode2(1), GIMT_Encode2(GICP_gi_vop3mods),
        GIM_CheckComplexPattern, /*MI*/2, /*Op*/1, /*Renderer*/GIMT_Encode2(2), GIMT_Encode2(GICP_gi_vop3mods),
        // (fmaxnum:{ *:[f32] } (fminnum:{ *:[f32] } (VOP3Mods:{ *:[f32] } f32:{ *:[f32] }:$src1, i32:{ *:[i32] }:$src1_mods), (VOP3Mods:{ *:[f32] } f32:{ *:[f32] }:$src0, i32:{ *:[i32] }:$src0_mods)), (fminnum_ieee:{ *:[f32] } (VOP3Mods:{ *:[f32] } f32:{ *:[f32] }:$src2, i32:{ *:[i32] }:$src2_mods), (fmaxnum:{ *:[f32] } (VOP3Mods:{ *:[f32] } f32:{ *:[f32] }:$src0, i32:{ *:[i32] }:$src0_mods), (VOP3Mods:{ *:[f32] } f32:{ *:[f32] }:$src1, i32:{ *:[i32] }:$src1_mods))))<<P:Predicate_fmaxnum_like_nnan>>  =>  (V_MED3_F32_e64:{ *:[f32] } ?:{ *:[i32] }:$src0_mods, ?:{ *:[f32] }:$src0, ?:{ *:[i32] }:$src1_mods, ?:{ *:[f32] }:$src1, ?:{ *:[i32] }:$src2_mods, ?:{ *:[f32] }:$src2, 0:{ *:[i1] }, 0:{ *:[i32] })
        GIR_BuildMI, /*InsnID*/0, /*Opcode*/GIMT_Encode2(AMDGPU::V_MED3_F32_e64),
        GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/0, // DstI[vdst]
        GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(1), /*SubOperand*/1, // src0_mods
        GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(1), /*SubOperand*/0, // src0
        GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/1, // src1_mods
        GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/0, // src1
        GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(2), /*SubOperand*/1, // src2_mods
        GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(2), /*SubOperand*/0, // src2
        GIR_AddImm8, /*InsnID*/0, /*Imm*/0,
        GIR_AddImm8, /*InsnID*/0, /*Imm*/0,
        GIR_ConstrainSelectedInstOperands, /*InsnID*/0,
        GIR_EraseFromParent, /*InsnID*/0,
        // GIR_Coverage, 10200,
        GIR_Done,
      // Label 4630: @310366
      GIM_Try, /*On fail goto*//*Label 4631*/ GIMT_Encode4(310506), // Rule ID 10201 //
        GIM_CheckRegBankForClass, /*MI*/0, /*Op*/0, /*RC*/GIMT_Encode2(AMDGPU::VGPR_32RegClassID),
        GIM_RecordInsn, /*DefineMI*/1, /*MI*/0, /*OpIdx*/1, // MIs[1]
        GIM_CheckOpcode, /*MI*/1, GIMT_Encode2(TargetOpcode::G_FMINNUM),
        GIM_CheckType, /*MI*/1, /*Op*/1, /*Type*/GILLT_s32,
        GIM_CheckType, /*MI*/1, /*Op*/2, /*Type*/GILLT_s32,
        GIM_RecordInsn, /*DefineMI*/2, /*MI*/0, /*OpIdx*/2, // MIs[2]
        GIM_CheckOpcode, /*MI*/2, GIMT_Encode2(TargetOpcode::G_FMINNUM_IEEE),
        GIM_CheckType, /*MI*/2, /*Op*/1, /*Type*/GILLT_s32,
        GIM_CheckType, /*MI*/2, /*Op*/2, /*Type*/GILLT_s32,
        GIM_RecordInsn, /*DefineMI*/3, /*MI*/2, /*OpIdx*/2, // MIs[3]
        GIM_CheckOpcode, /*MI*/3, GIMT_Encode2(TargetOpcode::G_FMAXNUM),
        // MIs[3] VOP3Mods:src1:src1_mods
        GIM_CheckIsSameOperand, /*MI*/3, /*OpIdx*/1, /*OtherMI*/1, /*OtherOpIdx*/1,
        // MIs[3] VOP3Mods:src0:src0_mods
        GIM_CheckIsSameOperand, /*MI*/3, /*OpIdx*/2, /*OtherMI*/1, /*OtherOpIdx*/2,
        GIM_CheckCxxInsnPredicate, /*MI*/0, /*FnId*/GIMT_Encode2(GICXXPred_MI_Predicate_fmaxnum_like_nnan),
        GIM_CheckIsSafeToFold, /*InsnID*/1,
        GIM_CheckIsSafeToFold, /*InsnID*/2,
        GIM_CheckIsSafeToFold, /*InsnID*/3,
        GIM_CheckComplexPattern, /*MI*/1, /*Op*/1, /*Renderer*/GIMT_Encode2(0), GIMT_Encode2(GICP_gi_vop3mods),
        GIM_CheckComplexPattern, /*MI*/1, /*Op*/2, /*Renderer*/GIMT_Encode2(1), GIMT_Encode2(GICP_gi_vop3mods),
        GIM_CheckComplexPattern, /*MI*/2, /*Op*/1, /*Renderer*/GIMT_Encode2(2), GIMT_Encode2(GICP_gi_vop3mods),
        // (fmaxnum:{ *:[f32] } (fminnum:{ *:[f32] } (VOP3Mods:{ *:[f32] } f32:{ *:[f32] }:$src1, i32:{ *:[i32] }:$src1_mods), (VOP3Mods:{ *:[f32] } f32:{ *:[f32] }:$src0, i32:{ *:[i32] }:$src0_mods)), (fminnum_ieee:{ *:[f32] } (VOP3Mods:{ *:[f32] } f32:{ *:[f32] }:$src2, i32:{ *:[i32] }:$src2_mods), (fmaxnum:{ *:[f32] } (VOP3Mods:{ *:[f32] } f32:{ *:[f32] }:$src1, i32:{ *:[i32] }:$src1_mods), (VOP3Mods:{ *:[f32] } f32:{ *:[f32] }:$src0, i32:{ *:[i32] }:$src0_mods))))<<P:Predicate_fmaxnum_like_nnan>>  =>  (V_MED3_F32_e64:{ *:[f32] } ?:{ *:[i32] }:$src0_mods, ?:{ *:[f32] }:$src0, ?:{ *:[i32] }:$src1_mods, ?:{ *:[f32] }:$src1, ?:{ *:[i32] }:$src2_mods, ?:{ *:[f32] }:$src2, 0:{ *:[i1] }, 0:{ *:[i32] })
        GIR_BuildMI, /*InsnID*/0, /*Opcode*/GIMT_Encode2(AMDGPU::V_MED3_F32_e64),
        GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/0, // DstI[vdst]
        GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(1), /*SubOperand*/1, // src0_mods
        GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(1), /*SubOperand*/0, // src0
        GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/1, // src1_mods
        GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/0, // src1
        GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(2), /*SubOperand*/1, // src2_mods
        GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(2), /*SubOperand*/0, // src2
        GIR_AddImm8, /*InsnID*/0, /*Imm*/0,
        GIR_AddImm8, /*InsnID*/0, /*Imm*/0,
        GIR_ConstrainSelectedInstOperands, /*InsnID*/0,
        GIR_EraseFromParent, /*InsnID*/0,
        // GIR_Coverage, 10201,
        GIR_Done,
      // Label 4631: @310506
      GIM_Try, /*On fail goto*//*Label 4632*/ GIMT_Encode4(310646), // Rule ID 10181 //
        GIM_CheckRegBankForClass, /*MI*/0, /*Op*/0, /*RC*/GIMT_Encode2(AMDGPU::VGPR_32RegClassID),
        GIM_RecordInsn, /*DefineMI*/1, /*MI*/0, /*OpIdx*/1, // MIs[1]
        GIM_CheckOpcode, /*MI*/1, GIMT_Encode2(TargetOpcode::G_FMINNUM),
        GIM_CheckType, /*MI*/1, /*Op*/1, /*Type*/GILLT_s32,
        GIM_CheckType, /*MI*/1, /*Op*/2, /*Type*/GILLT_s32,
        GIM_RecordInsn, /*DefineMI*/2, /*MI*/0, /*OpIdx*/2, // MIs[2]
        GIM_CheckOpcode, /*MI*/2, GIMT_Encode2(TargetOpcode::G_FMINNUM_IEEE),
        GIM_CheckType, /*MI*/2, /*Op*/1, /*Type*/GILLT_s32,
        GIM_CheckType, /*MI*/2, /*Op*/2, /*Type*/GILLT_s32,
        GIM_RecordInsn, /*DefineMI*/3, /*MI*/2, /*OpIdx*/2, // MIs[3]
        GIM_CheckOpcode, /*MI*/3, GIMT_Encode2(TargetOpcode::G_FMAXNUM_IEEE),
        // MIs[3] VOP3Mods:src0:src0_mods
        GIM_CheckIsSameOperand, /*MI*/3, /*OpIdx*/1, /*OtherMI*/1, /*OtherOpIdx*/1,
        // MIs[3] VOP3Mods:src1:src1_mods
        GIM_CheckIsSameOperand, /*MI*/3, /*OpIdx*/2, /*OtherMI*/1, /*OtherOpIdx*/2,
        GIM_CheckCxxInsnPredicate, /*MI*/0, /*FnId*/GIMT_Encode2(GICXXPred_MI_Predicate_fmaxnum_like_nnan),
        GIM_CheckIsSafeToFold, /*InsnID*/1,
        GIM_CheckIsSafeToFold, /*InsnID*/2,
        GIM_CheckIsSafeToFold, /*InsnID*/3,
        GIM_CheckComplexPattern, /*MI*/1, /*Op*/1, /*Renderer*/GIMT_Encode2(0), GIMT_Encode2(GICP_gi_vop3mods),
        GIM_CheckComplexPattern, /*MI*/1, /*Op*/2, /*Renderer*/GIMT_Encode2(1), GIMT_Encode2(GICP_gi_vop3mods),
        GIM_CheckComplexPattern, /*MI*/2, /*Op*/1, /*Renderer*/GIMT_Encode2(2), GIMT_Encode2(GICP_gi_vop3mods),
        // (fmaxnum:{ *:[f32] } (fminnum:{ *:[f32] } (VOP3Mods:{ *:[f32] } f32:{ *:[f32] }:$src0, i32:{ *:[i32] }:$src0_mods), (VOP3Mods:{ *:[f32] } f32:{ *:[f32] }:$src1, i32:{ *:[i32] }:$src1_mods)), (fminnum_ieee:{ *:[f32] } (VOP3Mods:{ *:[f32] } f32:{ *:[f32] }:$src2, i32:{ *:[i32] }:$src2_mods), (fmaxnum_ieee:{ *:[f32] } (VOP3Mods:{ *:[f32] } f32:{ *:[f32] }:$src0, i32:{ *:[i32] }:$src0_mods), (VOP3Mods:{ *:[f32] } f32:{ *:[f32] }:$src1, i32:{ *:[i32] }:$src1_mods))))<<P:Predicate_fmaxnum_like_nnan>>  =>  (V_MED3_F32_e64:{ *:[f32] } ?:{ *:[i32] }:$src0_mods, ?:{ *:[f32] }:$src0, ?:{ *:[i32] }:$src1_mods, ?:{ *:[f32] }:$src1, ?:{ *:[i32] }:$src2_mods, ?:{ *:[f32] }:$src2, 0:{ *:[i1] }, 0:{ *:[i32] })
        GIR_BuildMI, /*InsnID*/0, /*Opcode*/GIMT_Encode2(AMDGPU::V_MED3_F32_e64),
        GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/0, // DstI[vdst]
        GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/1, // src0_mods
        GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/0, // src0
        GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(1), /*SubOperand*/1, // src1_mods
        GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(1), /*SubOperand*/0, // src1
        GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(2), /*SubOperand*/1, // src2_mods
        GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(2), /*SubOperand*/0, // src2
        GIR_AddImm8, /*InsnID*/0, /*Imm*/0,
        GIR_AddImm8, /*InsnID*/0, /*Imm*/0,
        GIR_ConstrainSelectedInstOperands, /*InsnID*/0,
        GIR_EraseFromParent, /*InsnID*/0,
        // GIR_Coverage, 10181,
        GIR_Done,
      // Label 4632: @310646
      GIM_Try, /*On fail goto*//*Label 4633*/ GIMT_Encode4(310786), // Rule ID 10182 //
        GIM_CheckRegBankForClass, /*MI*/0, /*Op*/0, /*RC*/GIMT_Encode2(AMDGPU::VGPR_32RegClassID),
        GIM_RecordInsn, /*DefineMI*/1, /*MI*/0, /*OpIdx*/1, // MIs[1]
        GIM_CheckOpcode, /*MI*/1, GIMT_Encode2(TargetOpcode::G_FMINNUM),
        GIM_CheckType, /*MI*/1, /*Op*/1, /*Type*/GILLT_s32,
        GIM_CheckType, /*MI*/1, /*Op*/2, /*Type*/GILLT_s32,
        GIM_RecordInsn, /*DefineMI*/2, /*MI*/0, /*OpIdx*/2, // MIs[2]
        GIM_CheckOpcode, /*MI*/2, GIMT_Encode2(TargetOpcode::G_FMINNUM_IEEE),
        GIM_CheckType, /*MI*/2, /*Op*/1, /*Type*/GILLT_s32,
        GIM_CheckType, /*MI*/2, /*Op*/2, /*Type*/GILLT_s32,
        GIM_RecordInsn, /*DefineMI*/3, /*MI*/2, /*OpIdx*/2, // MIs[3]
        GIM_CheckOpcode, /*MI*/3, GIMT_Encode2(TargetOpcode::G_FMAXNUM_IEEE),
        // MIs[3] VOP3Mods:src1:src1_mods
        GIM_CheckIsSameOperand, /*MI*/3, /*OpIdx*/1, /*OtherMI*/1, /*OtherOpIdx*/2,
        // MIs[3] VOP3Mods:src0:src0_mods
        GIM_CheckIsSameOperand, /*MI*/3, /*OpIdx*/2, /*OtherMI*/1, /*OtherOpIdx*/1,
        GIM_CheckCxxInsnPredicate, /*MI*/0, /*FnId*/GIMT_Encode2(GICXXPred_MI_Predicate_fmaxnum_like_nnan),
        GIM_CheckIsSafeToFold, /*InsnID*/1,
        GIM_CheckIsSafeToFold, /*InsnID*/2,
        GIM_CheckIsSafeToFold, /*InsnID*/3,
        GIM_CheckComplexPattern, /*MI*/1, /*Op*/1, /*Renderer*/GIMT_Encode2(0), GIMT_Encode2(GICP_gi_vop3mods),
        GIM_CheckComplexPattern, /*MI*/1, /*Op*/2, /*Renderer*/GIMT_Encode2(1), GIMT_Encode2(GICP_gi_vop3mods),
        GIM_CheckComplexPattern, /*MI*/2, /*Op*/1, /*Renderer*/GIMT_Encode2(2), GIMT_Encode2(GICP_gi_vop3mods),
        // (fmaxnum:{ *:[f32] } (fminnum:{ *:[f32] } (VOP3Mods:{ *:[f32] } f32:{ *:[f32] }:$src0, i32:{ *:[i32] }:$src0_mods), (VOP3Mods:{ *:[f32] } f32:{ *:[f32] }:$src1, i32:{ *:[i32] }:$src1_mods)), (fminnum_ieee:{ *:[f32] } (VOP3Mods:{ *:[f32] } f32:{ *:[f32] }:$src2, i32:{ *:[i32] }:$src2_mods), (fmaxnum_ieee:{ *:[f32] } (VOP3Mods:{ *:[f32] } f32:{ *:[f32] }:$src1, i32:{ *:[i32] }:$src1_mods), (VOP3Mods:{ *:[f32] } f32:{ *:[f32] }:$src0, i32:{ *:[i32] }:$src0_mods))))<<P:Predicate_fmaxnum_like_nnan>>  =>  (V_MED3_F32_e64:{ *:[f32] } ?:{ *:[i32] }:$src0_mods, ?:{ *:[f32] }:$src0, ?:{ *:[i32] }:$src1_mods, ?:{ *:[f32] }:$src1, ?:{ *:[i32] }:$src2_mods, ?:{ *:[f32] }:$src2, 0:{ *:[i1] }, 0:{ *:[i32] })
        GIR_BuildMI, /*InsnID*/0, /*Opcode*/GIMT_Encode2(AMDGPU::V_MED3_F32_e64),
        GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/0, // DstI[vdst]
        GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/1, // src0_mods
        GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/0, // src0
        GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(1), /*SubOperand*/1, // src1_mods
        GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(1), /*SubOperand*/0, // src1
        GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(2), /*SubOperand*/1, // src2_mods
        GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(2), /*SubOperand*/0, // src2
        GIR_AddImm8, /*InsnID*/0, /*Imm*/0,
        GIR_AddImm8, /*InsnID*/0, /*Imm*/0,
        GIR_ConstrainSelectedInstOperands, /*InsnID*/0,
        GIR_EraseFromParent, /*InsnID*/0,
        // GIR_Coverage, 10182,
        GIR_Done,
      // Label 4633: @310786
      GIM_Try, /*On fail goto*//*Label 4634*/ GIMT_Encode4(310926), // Rule ID 10185 //
        GIM_CheckRegBankForClass, /*MI*/0, /*Op*/0, /*RC*/GIMT_Encode2(AMDGPU::VGPR_32RegClassID),
        GIM_RecordInsn, /*DefineMI*/1, /*MI*/0, /*OpIdx*/1, // MIs[1]
        GIM_CheckOpcode, /*MI*/1, GIMT_Encode2(TargetOpcode::G_FMINNUM),
        GIM_CheckType, /*MI*/1, /*Op*/1, /*Type*/GILLT_s32,
        GIM_CheckType, /*MI*/1, /*Op*/2, /*Type*/GILLT_s32,
        GIM_RecordInsn, /*DefineMI*/2, /*MI*/0, /*OpIdx*/2, // MIs[2]
        GIM_CheckOpcode, /*MI*/2, GIMT_Encode2(TargetOpcode::G_FMINNUM_IEEE),
        GIM_CheckType, /*MI*/2, /*Op*/1, /*Type*/GILLT_s32,
        GIM_CheckType, /*MI*/2, /*Op*/2, /*Type*/GILLT_s32,
        GIM_RecordInsn, /*DefineMI*/3, /*MI*/2, /*OpIdx*/2, // MIs[3]
        GIM_CheckOpcode, /*MI*/3, GIMT_Encode2(TargetOpcode::G_FMAXNUM_IEEE),
        // MIs[3] VOP3Mods:src0:src0_mods
        GIM_CheckIsSameOperand, /*MI*/3, /*OpIdx*/1, /*OtherMI*/1, /*OtherOpIdx*/2,
        // MIs[3] VOP3Mods:src1:src1_mods
        GIM_CheckIsSameOperand, /*MI*/3, /*OpIdx*/2, /*OtherMI*/1, /*OtherOpIdx*/1,
        GIM_CheckCxxInsnPredicate, /*MI*/0, /*FnId*/GIMT_Encode2(GICXXPred_MI_Predicate_fmaxnum_like_nnan),
        GIM_CheckIsSafeToFold, /*InsnID*/1,
        GIM_CheckIsSafeToFold, /*InsnID*/2,
        GIM_CheckIsSafeToFold, /*InsnID*/3,
        GIM_CheckComplexPattern, /*MI*/1, /*Op*/1, /*Renderer*/GIMT_Encode2(0), GIMT_Encode2(GICP_gi_vop3mods),
        GIM_CheckComplexPattern, /*MI*/1, /*Op*/2, /*Renderer*/GIMT_Encode2(1), GIMT_Encode2(GICP_gi_vop3mods),
        GIM_CheckComplexPattern, /*MI*/2, /*Op*/1, /*Renderer*/GIMT_Encode2(2), GIMT_Encode2(GICP_gi_vop3mods),
        // (fmaxnum:{ *:[f32] } (fminnum:{ *:[f32] } (VOP3Mods:{ *:[f32] } f32:{ *:[f32] }:$src1, i32:{ *:[i32] }:$src1_mods), (VOP3Mods:{ *:[f32] } f32:{ *:[f32] }:$src0, i32:{ *:[i32] }:$src0_mods)), (fminnum_ieee:{ *:[f32] } (VOP3Mods:{ *:[f32] } f32:{ *:[f32] }:$src2, i32:{ *:[i32] }:$src2_mods), (fmaxnum_ieee:{ *:[f32] } (VOP3Mods:{ *:[f32] } f32:{ *:[f32] }:$src0, i32:{ *:[i32] }:$src0_mods), (VOP3Mods:{ *:[f32] } f32:{ *:[f32] }:$src1, i32:{ *:[i32] }:$src1_mods))))<<P:Predicate_fmaxnum_like_nnan>>  =>  (V_MED3_F32_e64:{ *:[f32] } ?:{ *:[i32] }:$src0_mods, ?:{ *:[f32] }:$src0, ?:{ *:[i32] }:$src1_mods, ?:{ *:[f32] }:$src1, ?:{ *:[i32] }:$src2_mods, ?:{ *:[f32] }:$src2, 0:{ *:[i1] }, 0:{ *:[i32] })
        GIR_BuildMI, /*InsnID*/0, /*Opcode*/GIMT_Encode2(AMDGPU::V_MED3_F32_e64),
        GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/0, // DstI[vdst]
        GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(1), /*SubOperand*/1, // src0_mods
        GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(1), /*SubOperand*/0, // src0
        GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/1, // src1_mods
        GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/0, // src1
        GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(2), /*SubOperand*/1, // src2_mods
        GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(2), /*SubOperand*/0, // src2
        GIR_AddImm8, /*InsnID*/0, /*Imm*/0,
        GIR_AddImm8, /*InsnID*/0, /*Imm*/0,
        GIR_ConstrainSelectedInstOperands, /*InsnID*/0,
        GIR_EraseFromParent, /*InsnID*/0,
        // GIR_Coverage, 10185,
        GIR_Done,
      // Label 4634: @310926
      GIM_Try, /*On fail goto*//*Label 4635*/ GIMT_Encode4(311066), // Rule ID 10186 //
        GIM_CheckRegBankForClass, /*MI*/0, /*Op*/0, /*RC*/GIMT_Encode2(AMDGPU::VGPR_32RegClassID),
        GIM_RecordInsn, /*DefineMI*/1, /*MI*/0, /*OpIdx*/1, // MIs[1]
        GIM_CheckOpcode, /*MI*/1, GIMT_Encode2(TargetOpcode::G_FMINNUM),
        GIM_CheckType, /*MI*/1, /*Op*/1, /*Type*/GILLT_s32,
        GIM_CheckType, /*MI*/1, /*Op*/2, /*Type*/GILLT_s32,
        GIM_RecordInsn, /*DefineMI*/2, /*MI*/0, /*OpIdx*/2, // MIs[2]
        GIM_CheckOpcode, /*MI*/2, GIMT_Encode2(TargetOpcode::G_FMINNUM_IEEE),
        GIM_CheckType, /*MI*/2, /*Op*/1, /*Type*/GILLT_s32,
        GIM_CheckType, /*MI*/2, /*Op*/2, /*Type*/GILLT_s32,
        GIM_RecordInsn, /*DefineMI*/3, /*MI*/2, /*OpIdx*/2, // MIs[3]
        GIM_CheckOpcode, /*MI*/3, GIMT_Encode2(TargetOpcode::G_FMAXNUM_IEEE),
        // MIs[3] VOP3Mods:src1:src1_mods
        GIM_CheckIsSameOperand, /*MI*/3, /*OpIdx*/1, /*OtherMI*/1, /*OtherOpIdx*/1,
        // MIs[3] VOP3Mods:src0:src0_mods
        GIM_CheckIsSameOperand, /*MI*/3, /*OpIdx*/2, /*OtherMI*/1, /*OtherOpIdx*/2,
        GIM_CheckCxxInsnPredicate, /*MI*/0, /*FnId*/GIMT_Encode2(GICXXPred_MI_Predicate_fmaxnum_like_nnan),
        GIM_CheckIsSafeToFold, /*InsnID*/1,
        GIM_CheckIsSafeToFold, /*InsnID*/2,
        GIM_CheckIsSafeToFold, /*InsnID*/3,
        GIM_CheckComplexPattern, /*MI*/1, /*Op*/1, /*Renderer*/GIMT_Encode2(0), GIMT_Encode2(GICP_gi_vop3mods),
        GIM_CheckComplexPattern, /*MI*/1, /*Op*/2, /*Renderer*/GIMT_Encode2(1), GIMT_Encode2(GICP_gi_vop3mods),
        GIM_CheckComplexPattern, /*MI*/2, /*Op*/1, /*Renderer*/GIMT_Encode2(2), GIMT_Encode2(GICP_gi_vop3mods),
        // (fmaxnum:{ *:[f32] } (fminnum:{ *:[f32] } (VOP3Mods:{ *:[f32] } f32:{ *:[f32] }:$src1, i32:{ *:[i32] }:$src1_mods), (VOP3Mods:{ *:[f32] } f32:{ *:[f32] }:$src0, i32:{ *:[i32] }:$src0_mods)), (fminnum_ieee:{ *:[f32] } (VOP3Mods:{ *:[f32] } f32:{ *:[f32] }:$src2, i32:{ *:[i32] }:$src2_mods), (fmaxnum_ieee:{ *:[f32] } (VOP3Mods:{ *:[f32] } f32:{ *:[f32] }:$src1, i32:{ *:[i32] }:$src1_mods), (VOP3Mods:{ *:[f32] } f32:{ *:[f32] }:$src0, i32:{ *:[i32] }:$src0_mods))))<<P:Predicate_fmaxnum_like_nnan>>  =>  (V_MED3_F32_e64:{ *:[f32] } ?:{ *:[i32] }:$src0_mods, ?:{ *:[f32] }:$src0, ?:{ *:[i32] }:$src1_mods, ?:{ *:[f32] }:$src1, ?:{ *:[i32] }:$src2_mods, ?:{ *:[f32] }:$src2, 0:{ *:[i1] }, 0:{ *:[i32] })
        GIR_BuildMI, /*InsnID*/0, /*Opcode*/GIMT_Encode2(AMDGPU::V_MED3_F32_e64),
        GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/0, // DstI[vdst]
        GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(1), /*SubOperand*/1, // src0_mods
        GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(1), /*SubOperand*/0, // src0
        GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/1, // src1_mods
        GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/0, // src1
        GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(2), /*SubOperand*/1, // src2_mods
        GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(2), /*SubOperand*/0, // src2
        GIR_AddImm8, /*InsnID*/0, /*Imm*/0,
        GIR_AddImm8, /*InsnID*/0, /*Imm*/0,
        GIR_ConstrainSelectedInstOperands, /*InsnID*/0,
        GIR_EraseFromParent, /*InsnID*/0,
        // GIR_Coverage, 10186,
        GIR_Done,
      // Label 4635: @311066
      GIM_Try, /*On fail goto*//*Label 4636*/ GIMT_Encode4(311206), // Rule ID 6495 //
        GIM_CheckRegBankForClass, /*MI*/0, /*Op*/0, /*RC*/GIMT_Encode2(AMDGPU::VGPR_32RegClassID),
        GIM_RecordInsn, /*DefineMI*/1, /*MI*/0, /*OpIdx*/1, // MIs[1]
        GIM_CheckOpcode, /*MI*/1, GIMT_Encode2(TargetOpcode::G_FMINNUM),
        GIM_CheckType, /*MI*/1, /*Op*/1, /*Type*/GILLT_s32,
        GIM_CheckType, /*MI*/1, /*Op*/2, /*Type*/GILLT_s32,
        GIM_RecordInsn, /*DefineMI*/2, /*MI*/0, /*OpIdx*/2, // MIs[2]
        GIM_CheckOpcode, /*MI*/2, GIMT_Encode2(TargetOpcode::G_FMINNUM_IEEE),
        GIM_CheckType, /*MI*/2, /*Op*/1, /*Type*/GILLT_s32,
        GIM_CheckType, /*MI*/2, /*Op*/2, /*Type*/GILLT_s32,
        GIM_RecordInsn, /*DefineMI*/3, /*MI*/2, /*OpIdx*/1, // MIs[3]
        GIM_CheckOpcode, /*MI*/3, GIMT_Encode2(TargetOpcode::G_FMAXNUM),
        // MIs[3] VOP3Mods:src0:src0_mods
        GIM_CheckIsSameOperand, /*MI*/3, /*OpIdx*/1, /*OtherMI*/1, /*OtherOpIdx*/1,
        // MIs[3] VOP3Mods:src1:src1_mods
        GIM_CheckIsSameOperand, /*MI*/3, /*OpIdx*/2, /*OtherMI*/1, /*OtherOpIdx*/2,
        GIM_CheckCxxInsnPredicate, /*MI*/0, /*FnId*/GIMT_Encode2(GICXXPred_MI_Predicate_fmaxnum_like_nnan),
        GIM_CheckIsSafeToFold, /*InsnID*/1,
        GIM_CheckIsSafeToFold, /*InsnID*/2,
        GIM_CheckIsSafeToFold, /*InsnID*/3,
        GIM_CheckComplexPattern, /*MI*/1, /*Op*/1, /*Renderer*/GIMT_Encode2(0), GIMT_Encode2(GICP_gi_vop3mods),
        GIM_CheckComplexPattern, /*MI*/1, /*Op*/2, /*Renderer*/GIMT_Encode2(1), GIMT_Encode2(GICP_gi_vop3mods),
        GIM_CheckComplexPattern, /*MI*/2, /*Op*/2, /*Renderer*/GIMT_Encode2(2), GIMT_Encode2(GICP_gi_vop3mods),
        // (fmaxnum:{ *:[f32] } (fminnum:{ *:[f32] } (VOP3Mods:{ *:[f32] } f32:{ *:[f32] }:$src0, i32:{ *:[i32] }:$src0_mods), (VOP3Mods:{ *:[f32] } f32:{ *:[f32] }:$src1, i32:{ *:[i32] }:$src1_mods)), (fminnum_ieee:{ *:[f32] } (fmaxnum:{ *:[f32] } (VOP3Mods:{ *:[f32] } f32:{ *:[f32] }:$src0, i32:{ *:[i32] }:$src0_mods), (VOP3Mods:{ *:[f32] } f32:{ *:[f32] }:$src1, i32:{ *:[i32] }:$src1_mods)), (VOP3Mods:{ *:[f32] } f32:{ *:[f32] }:$src2, i32:{ *:[i32] }:$src2_mods)))<<P:Predicate_fmaxnum_like_nnan>>  =>  (V_MED3_F32_e64:{ *:[f32] } ?:{ *:[i32] }:$src0_mods, ?:{ *:[f32] }:$src0, ?:{ *:[i32] }:$src1_mods, ?:{ *:[f32] }:$src1, ?:{ *:[i32] }:$src2_mods, ?:{ *:[f32] }:$src2, 0:{ *:[i1] }, 0:{ *:[i32] })
        GIR_BuildMI, /*InsnID*/0, /*Opcode*/GIMT_Encode2(AMDGPU::V_MED3_F32_e64),
        GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/0, // DstI[vdst]
        GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/1, // src0_mods
        GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/0, // src0
        GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(1), /*SubOperand*/1, // src1_mods
        GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(1), /*SubOperand*/0, // src1
        GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(2), /*SubOperand*/1, // src2_mods
        GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(2), /*SubOperand*/0, // src2
        GIR_AddImm8, /*InsnID*/0, /*Imm*/0,
        GIR_AddImm8, /*InsnID*/0, /*Imm*/0,
        GIR_ConstrainSelectedInstOperands, /*InsnID*/0,
        GIR_EraseFromParent, /*InsnID*/0,
        // GIR_Coverage, 6495,
        GIR_Done,
      // Label 4636: @311206
      GIM_Try, /*On fail goto*//*Label 4637*/ GIMT_Encode4(311346), // Rule ID 10195 //
        GIM_CheckRegBankForClass, /*MI*/0, /*Op*/0, /*RC*/GIMT_Encode2(AMDGPU::VGPR_32RegClassID),
        GIM_RecordInsn, /*DefineMI*/1, /*MI*/0, /*OpIdx*/1, // MIs[1]
        GIM_CheckOpcode, /*MI*/1, GIMT_Encode2(TargetOpcode::G_FMINNUM),
        GIM_CheckType, /*MI*/1, /*Op*/1, /*Type*/GILLT_s32,
        GIM_CheckType, /*MI*/1, /*Op*/2, /*Type*/GILLT_s32,
        GIM_RecordInsn, /*DefineMI*/2, /*MI*/0, /*OpIdx*/2, // MIs[2]
        GIM_CheckOpcode, /*MI*/2, GIMT_Encode2(TargetOpcode::G_FMINNUM_IEEE),
        GIM_CheckType, /*MI*/2, /*Op*/1, /*Type*/GILLT_s32,
        GIM_CheckType, /*MI*/2, /*Op*/2, /*Type*/GILLT_s32,
        GIM_RecordInsn, /*DefineMI*/3, /*MI*/2, /*OpIdx*/1, // MIs[3]
        GIM_CheckOpcode, /*MI*/3, GIMT_Encode2(TargetOpcode::G_FMAXNUM),
        // MIs[3] VOP3Mods:src1:src1_mods
        GIM_CheckIsSameOperand, /*MI*/3, /*OpIdx*/1, /*OtherMI*/1, /*OtherOpIdx*/2,
        // MIs[3] VOP3Mods:src0:src0_mods
        GIM_CheckIsSameOperand, /*MI*/3, /*OpIdx*/2, /*OtherMI*/1, /*OtherOpIdx*/1,
        GIM_CheckCxxInsnPredicate, /*MI*/0, /*FnId*/GIMT_Encode2(GICXXPred_MI_Predicate_fmaxnum_like_nnan),
        GIM_CheckIsSafeToFold, /*InsnID*/1,
        GIM_CheckIsSafeToFold, /*InsnID*/2,
        GIM_CheckIsSafeToFold, /*InsnID*/3,
        GIM_CheckComplexPattern, /*MI*/1, /*Op*/1, /*Renderer*/GIMT_Encode2(0), GIMT_Encode2(GICP_gi_vop3mods),
        GIM_CheckComplexPattern, /*MI*/1, /*Op*/2, /*Renderer*/GIMT_Encode2(1), GIMT_Encode2(GICP_gi_vop3mods),
        GIM_CheckComplexPattern, /*MI*/2, /*Op*/2, /*Renderer*/GIMT_Encode2(2), GIMT_Encode2(GICP_gi_vop3mods),
        // (fmaxnum:{ *:[f32] } (fminnum:{ *:[f32] } (VOP3Mods:{ *:[f32] } f32:{ *:[f32] }:$src0, i32:{ *:[i32] }:$src0_mods), (VOP3Mods:{ *:[f32] } f32:{ *:[f32] }:$src1, i32:{ *:[i32] }:$src1_mods)), (fminnum_ieee:{ *:[f32] } (fmaxnum:{ *:[f32] } (VOP3Mods:{ *:[f32] } f32:{ *:[f32] }:$src1, i32:{ *:[i32] }:$src1_mods), (VOP3Mods:{ *:[f32] } f32:{ *:[f32] }:$src0, i32:{ *:[i32] }:$src0_mods)), (VOP3Mods:{ *:[f32] } f32:{ *:[f32] }:$src2, i32:{ *:[i32] }:$src2_mods)))<<P:Predicate_fmaxnum_like_nnan>>  =>  (V_MED3_F32_e64:{ *:[f32] } ?:{ *:[i32] }:$src0_mods, ?:{ *:[f32] }:$src0, ?:{ *:[i32] }:$src1_mods, ?:{ *:[f32] }:$src1, ?:{ *:[i32] }:$src2_mods, ?:{ *:[f32] }:$src2, 0:{ *:[i1] }, 0:{ *:[i32] })
        GIR_BuildMI, /*InsnID*/0, /*Opcode*/GIMT_Encode2(AMDGPU::V_MED3_F32_e64),
        GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/0, // DstI[vdst]
        GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/1, // src0_mods
        GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/0, // src0
        GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(1), /*SubOperand*/1, // src1_mods
        GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(1), /*SubOperand*/0, // src1
        GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(2), /*SubOperand*/1, // src2_mods
        GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(2), /*SubOperand*/0, // src2
        GIR_AddImm8, /*InsnID*/0, /*Imm*/0,
        GIR_AddImm8, /*InsnID*/0, /*Imm*/0,
        GIR_ConstrainSelectedInstOperands, /*InsnID*/0,
        GIR_EraseFromParent, /*InsnID*/0,
        // GIR_Coverage, 10195,
        GIR_Done,
      // Label 4637: @311346
      GIM_Try, /*On fail goto*//*Label 4638*/ GIMT_Encode4(311486), // Rule ID 10198 //
        GIM_CheckRegBankForClass, /*MI*/0, /*Op*/0, /*RC*/GIMT_Encode2(AMDGPU::VGPR_32RegClassID),
        GIM_RecordInsn, /*DefineMI*/1, /*MI*/0, /*OpIdx*/1, // MIs[1]
        GIM_CheckOpcode, /*MI*/1, GIMT_Encode2(TargetOpcode::G_FMINNUM),
        GIM_CheckType, /*MI*/1, /*Op*/1, /*Type*/GILLT_s32,
        GIM_CheckType, /*MI*/1, /*Op*/2, /*Type*/GILLT_s32,
        GIM_RecordInsn, /*DefineMI*/2, /*MI*/0, /*OpIdx*/2, // MIs[2]
        GIM_CheckOpcode, /*MI*/2, GIMT_Encode2(TargetOpcode::G_FMINNUM_IEEE),
        GIM_CheckType, /*MI*/2, /*Op*/1, /*Type*/GILLT_s32,
        GIM_CheckType, /*MI*/2, /*Op*/2, /*Type*/GILLT_s32,
        GIM_RecordInsn, /*DefineMI*/3, /*MI*/2, /*OpIdx*/1, // MIs[3]
        GIM_CheckOpcode, /*MI*/3, GIMT_Encode2(TargetOpcode::G_FMAXNUM),
        // MIs[3] VOP3Mods:src0:src0_mods
        GIM_CheckIsSameOperand, /*MI*/3, /*OpIdx*/1, /*OtherMI*/1, /*OtherOpIdx*/2,
        // MIs[3] VOP3Mods:src1:src1_mods
        GIM_CheckIsSameOperand, /*MI*/3, /*OpIdx*/2, /*OtherMI*/1, /*OtherOpIdx*/1,
        GIM_CheckCxxInsnPredicate, /*MI*/0, /*FnId*/GIMT_Encode2(GICXXPred_MI_Predicate_fmaxnum_like_nnan),
        GIM_CheckIsSafeToFold, /*InsnID*/1,
        GIM_CheckIsSafeToFold, /*InsnID*/2,
        GIM_CheckIsSafeToFold, /*InsnID*/3,
        GIM_CheckComplexPattern, /*MI*/1, /*Op*/1, /*Renderer*/GIMT_Encode2(0), GIMT_Encode2(GICP_gi_vop3mods),
        GIM_CheckComplexPattern, /*MI*/1, /*Op*/2, /*Renderer*/GIMT_Encode2(1), GIMT_Encode2(GICP_gi_vop3mods),
        GIM_CheckComplexPattern, /*MI*/2, /*Op*/2, /*Renderer*/GIMT_Encode2(2), GIMT_Encode2(GICP_gi_vop3mods),
        // (fmaxnum:{ *:[f32] } (fminnum:{ *:[f32] } (VOP3Mods:{ *:[f32] } f32:{ *:[f32] }:$src1, i32:{ *:[i32] }:$src1_mods), (VOP3Mods:{ *:[f32] } f32:{ *:[f32] }:$src0, i32:{ *:[i32] }:$src0_mods)), (fminnum_ieee:{ *:[f32] } (fmaxnum:{ *:[f32] } (VOP3Mods:{ *:[f32] } f32:{ *:[f32] }:$src0, i32:{ *:[i32] }:$src0_mods), (VOP3Mods:{ *:[f32] } f32:{ *:[f32] }:$src1, i32:{ *:[i32] }:$src1_mods)), (VOP3Mods:{ *:[f32] } f32:{ *:[f32] }:$src2, i32:{ *:[i32] }:$src2_mods)))<<P:Predicate_fmaxnum_like_nnan>>  =>  (V_MED3_F32_e64:{ *:[f32] } ?:{ *:[i32] }:$src0_mods, ?:{ *:[f32] }:$src0, ?:{ *:[i32] }:$src1_mods, ?:{ *:[f32] }:$src1, ?:{ *:[i32] }:$src2_mods, ?:{ *:[f32] }:$src2, 0:{ *:[i1] }, 0:{ *:[i32] })
        GIR_BuildMI, /*InsnID*/0, /*Opcode*/GIMT_Encode2(AMDGPU::V_MED3_F32_e64),
        GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/0, // DstI[vdst]
        GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(1), /*SubOperand*/1, // src0_mods
        GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(1), /*SubOperand*/0, // src0
        GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/1, // src1_mods
        GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/0, // src1
        GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(2), /*SubOperand*/1, // src2_mods
        GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(2), /*SubOperand*/0, // src2
        GIR_AddImm8, /*InsnID*/0, /*Imm*/0,
        GIR_AddImm8, /*InsnID*/0, /*Imm*/0,
        GIR_ConstrainSelectedInstOperands, /*InsnID*/0,
        GIR_EraseFromParent, /*InsnID*/0,
        // GIR_Coverage, 10198,
        GIR_Done,
      // Label 4638: @311486
      GIM_Try, /*On fail goto*//*Label 4639*/ GIMT_Encode4(311626), // Rule ID 10199 //
        GIM_CheckRegBankForClass, /*MI*/0, /*Op*/0, /*RC*/GIMT_Encode2(AMDGPU::VGPR_32RegClassID),
        GIM_RecordInsn, /*DefineMI*/1, /*MI*/0, /*OpIdx*/1, // MIs[1]
        GIM_CheckOpcode, /*MI*/1, GIMT_Encode2(TargetOpcode::G_FMINNUM),
        GIM_CheckType, /*MI*/1, /*Op*/1, /*Type*/GILLT_s32,
        GIM_CheckType, /*MI*/1, /*Op*/2, /*Type*/GILLT_s32,
        GIM_RecordInsn, /*DefineMI*/2, /*MI*/0, /*OpIdx*/2, // MIs[2]
        GIM_CheckOpcode, /*MI*/2, GIMT_Encode2(TargetOpcode::G_FMINNUM_IEEE),
        GIM_CheckType, /*MI*/2, /*Op*/1, /*Type*/GILLT_s32,
        GIM_CheckType, /*MI*/2, /*Op*/2, /*Type*/GILLT_s32,
        GIM_RecordInsn, /*DefineMI*/3, /*MI*/2, /*OpIdx*/1, // MIs[3]
        GIM_CheckOpcode, /*MI*/3, GIMT_Encode2(TargetOpcode::G_FMAXNUM),
        // MIs[3] VOP3Mods:src1:src1_mods
        GIM_CheckIsSameOperand, /*MI*/3, /*OpIdx*/1, /*OtherMI*/1, /*OtherOpIdx*/1,
        // MIs[3] VOP3Mods:src0:src0_mods
        GIM_CheckIsSameOperand, /*MI*/3, /*OpIdx*/2, /*OtherMI*/1, /*OtherOpIdx*/2,
        GIM_CheckCxxInsnPredicate, /*MI*/0, /*FnId*/GIMT_Encode2(GICXXPred_MI_Predicate_fmaxnum_like_nnan),
        GIM_CheckIsSafeToFold, /*InsnID*/1,
        GIM_CheckIsSafeToFold, /*InsnID*/2,
        GIM_CheckIsSafeToFold, /*InsnID*/3,
        GIM_CheckComplexPattern, /*MI*/1, /*Op*/1, /*Renderer*/GIMT_Encode2(0), GIMT_Encode2(GICP_gi_vop3mods),
        GIM_CheckComplexPattern, /*MI*/1, /*Op*/2, /*Renderer*/GIMT_Encode2(1), GIMT_Encode2(GICP_gi_vop3mods),
        GIM_CheckComplexPattern, /*MI*/2, /*Op*/2, /*Renderer*/GIMT_Encode2(2), GIMT_Encode2(GICP_gi_vop3mods),
        // (fmaxnum:{ *:[f32] } (fminnum:{ *:[f32] } (VOP3Mods:{ *:[f32] } f32:{ *:[f32] }:$src1, i32:{ *:[i32] }:$src1_mods), (VOP3Mods:{ *:[f32] } f32:{ *:[f32] }:$src0, i32:{ *:[i32] }:$src0_mods)), (fminnum_ieee:{ *:[f32] } (fmaxnum:{ *:[f32] } (VOP3Mods:{ *:[f32] } f32:{ *:[f32] }:$src1, i32:{ *:[i32] }:$src1_mods), (VOP3Mods:{ *:[f32] } f32:{ *:[f32] }:$src0, i32:{ *:[i32] }:$src0_mods)), (VOP3Mods:{ *:[f32] } f32:{ *:[f32] }:$src2, i32:{ *:[i32] }:$src2_mods)))<<P:Predicate_fmaxnum_like_nnan>>  =>  (V_MED3_F32_e64:{ *:[f32] } ?:{ *:[i32] }:$src0_mods, ?:{ *:[f32] }:$src0, ?:{ *:[i32] }:$src1_mods, ?:{ *:[f32] }:$src1, ?:{ *:[i32] }:$src2_mods, ?:{ *:[f32] }:$src2, 0:{ *:[i1] }, 0:{ *:[i32] })
        GIR_BuildMI, /*InsnID*/0, /*Opcode*/GIMT_Encode2(AMDGPU::V_MED3_F32_e64),
        GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/0, // DstI[vdst]
        GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(1), /*SubOperand*/1, // src0_mods
        GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(1), /*SubOperand*/0, // src0
        GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/1, // src1_mods
        GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/0, // src1
        GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(2), /*SubOperand*/1, // src2_mods
        GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(2), /*SubOperand*/0, // src2
        GIR_AddImm8, /*InsnID*/0, /*Imm*/0,
        GIR_AddImm8, /*InsnID*/0, /*Imm*/0,
        GIR_ConstrainSelectedInstOperands, /*InsnID*/0,
        GIR_EraseFromParent, /*InsnID*/0,
        // GIR_Coverage, 10199,
        GIR_Done,
      // Label 4639: @311626
      GIM_Try, /*On fail goto*//*Label 4640*/ GIMT_Encode4(311766), // Rule ID 6494 //
        GIM_CheckRegBankForClass, /*MI*/0, /*Op*/0, /*RC*/GIMT_Encode2(AMDGPU::VGPR_32RegClassID),
        GIM_RecordInsn, /*DefineMI*/1, /*MI*/0, /*OpIdx*/1, // MIs[1]
        GIM_CheckOpcode, /*MI*/1, GIMT_Encode2(TargetOpcode::G_FMINNUM),
        GIM_CheckType, /*MI*/1, /*Op*/1, /*Type*/GILLT_s32,
        GIM_CheckType, /*MI*/1, /*Op*/2, /*Type*/GILLT_s32,
        GIM_RecordInsn, /*DefineMI*/2, /*MI*/0, /*OpIdx*/2, // MIs[2]
        GIM_CheckOpcode, /*MI*/2, GIMT_Encode2(TargetOpcode::G_FMINNUM_IEEE),
        GIM_CheckType, /*MI*/2, /*Op*/1, /*Type*/GILLT_s32,
        GIM_CheckType, /*MI*/2, /*Op*/2, /*Type*/GILLT_s32,
        GIM_RecordInsn, /*DefineMI*/3, /*MI*/2, /*OpIdx*/1, // MIs[3]
        GIM_CheckOpcode, /*MI*/3, GIMT_Encode2(TargetOpcode::G_FMAXNUM_IEEE),
        // MIs[3] VOP3Mods:src0:src0_mods
        GIM_CheckIsSameOperand, /*MI*/3, /*OpIdx*/1, /*OtherMI*/1, /*OtherOpIdx*/1,
        // MIs[3] VOP3Mods:src1:src1_mods
        GIM_CheckIsSameOperand, /*MI*/3, /*OpIdx*/2, /*OtherMI*/1, /*OtherOpIdx*/2,
        GIM_CheckCxxInsnPredicate, /*MI*/0, /*FnId*/GIMT_Encode2(GICXXPred_MI_Predicate_fmaxnum_like_nnan),
        GIM_CheckIsSafeToFold, /*InsnID*/1,
        GIM_CheckIsSafeToFold, /*InsnID*/2,
        GIM_CheckIsSafeToFold, /*InsnID*/3,
        GIM_CheckComplexPattern, /*MI*/1, /*Op*/1, /*Renderer*/GIMT_Encode2(0), GIMT_Encode2(GICP_gi_vop3mods),
        GIM_CheckComplexPattern, /*MI*/1, /*Op*/2, /*Renderer*/GIMT_Encode2(1), GIMT_Encode2(GICP_gi_vop3mods),
        GIM_CheckComplexPattern, /*MI*/2, /*Op*/2, /*Renderer*/GIMT_Encode2(2), GIMT_Encode2(GICP_gi_vop3mods),
        // (fmaxnum:{ *:[f32] } (fminnum:{ *:[f32] } (VOP3Mods:{ *:[f32] } f32:{ *:[f32] }:$src0, i32:{ *:[i32] }:$src0_mods), (VOP3Mods:{ *:[f32] } f32:{ *:[f32] }:$src1, i32:{ *:[i32] }:$src1_mods)), (fminnum_ieee:{ *:[f32] } (fmaxnum_ieee:{ *:[f32] } (VOP3Mods:{ *:[f32] } f32:{ *:[f32] }:$src0, i32:{ *:[i32] }:$src0_mods), (VOP3Mods:{ *:[f32] } f32:{ *:[f32] }:$src1, i32:{ *:[i32] }:$src1_mods)), (VOP3Mods:{ *:[f32] } f32:{ *:[f32] }:$src2, i32:{ *:[i32] }:$src2_mods)))<<P:Predicate_fmaxnum_like_nnan>>  =>  (V_MED3_F32_e64:{ *:[f32] } ?:{ *:[i32] }:$src0_mods, ?:{ *:[f32] }:$src0, ?:{ *:[i32] }:$src1_mods, ?:{ *:[f32] }:$src1, ?:{ *:[i32] }:$src2_mods, ?:{ *:[f32] }:$src2, 0:{ *:[i1] }, 0:{ *:[i32] })
        GIR_BuildMI, /*InsnID*/0, /*Opcode*/GIMT_Encode2(AMDGPU::V_MED3_F32_e64),
        GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/0, // DstI[vdst]
        GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/1, // src0_mods
        GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/0, // src0
        GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(1), /*SubOperand*/1, // src1_mods
        GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(1), /*SubOperand*/0, // src1
        GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(2), /*SubOperand*/1, // src2_mods
        GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(2), /*SubOperand*/0, // src2
        GIR_AddImm8, /*InsnID*/0, /*Imm*/0,
        GIR_AddImm8, /*InsnID*/0, /*Imm*/0,
        GIR_ConstrainSelectedInstOperands, /*InsnID*/0,
        GIR_EraseFromParent, /*InsnID*/0,
        // GIR_Coverage, 6494,
        GIR_Done,
      // Label 4640: @311766
      GIM_Try, /*On fail goto*//*Label 4641*/ GIMT_Encode4(311906), // Rule ID 10180 //
        GIM_CheckRegBankForClass, /*MI*/0, /*Op*/0, /*RC*/GIMT_Encode2(AMDGPU::VGPR_32RegClassID),
        GIM_RecordInsn, /*DefineMI*/1, /*MI*/0, /*OpIdx*/1, // MIs[1]
        GIM_CheckOpcode, /*MI*/1, GIMT_Encode2(TargetOpcode::G_FMINNUM),
        GIM_CheckType, /*MI*/1, /*Op*/1, /*Type*/GILLT_s32,
        GIM_CheckType, /*MI*/1, /*Op*/2, /*Type*/GILLT_s32,
        GIM_RecordInsn, /*DefineMI*/2, /*MI*/0, /*OpIdx*/2, // MIs[2]
        GIM_CheckOpcode, /*MI*/2, GIMT_Encode2(TargetOpcode::G_FMINNUM_IEEE),
        GIM_CheckType, /*MI*/2, /*Op*/1, /*Type*/GILLT_s32,
        GIM_CheckType, /*MI*/2, /*Op*/2, /*Type*/GILLT_s32,
        GIM_RecordInsn, /*DefineMI*/3, /*MI*/2, /*OpIdx*/1, // MIs[3]
        GIM_CheckOpcode, /*MI*/3, GIMT_Encode2(TargetOpcode::G_FMAXNUM_IEEE),
        // MIs[3] VOP3Mods:src1:src1_mods
        GIM_CheckIsSameOperand, /*MI*/3, /*OpIdx*/1, /*OtherMI*/1, /*OtherOpIdx*/2,
        // MIs[3] VOP3Mods:src0:src0_mods
        GIM_CheckIsSameOperand, /*MI*/3, /*OpIdx*/2, /*OtherMI*/1, /*OtherOpIdx*/1,
        GIM_CheckCxxInsnPredicate, /*MI*/0, /*FnId*/GIMT_Encode2(GICXXPred_MI_Predicate_fmaxnum_like_nnan),
        GIM_CheckIsSafeToFold, /*InsnID*/1,
        GIM_CheckIsSafeToFold, /*InsnID*/2,
        GIM_CheckIsSafeToFold, /*InsnID*/3,
        GIM_CheckComplexPattern, /*MI*/1, /*Op*/1, /*Renderer*/GIMT_Encode2(0), GIMT_Encode2(GICP_gi_vop3mods),
        GIM_CheckComplexPattern, /*MI*/1, /*Op*/2, /*Renderer*/GIMT_Encode2(1), GIMT_Encode2(GICP_gi_vop3mods),
        GIM_CheckComplexPattern, /*MI*/2, /*Op*/2, /*Renderer*/GIMT_Encode2(2), GIMT_Encode2(GICP_gi_vop3mods),
        // (fmaxnum:{ *:[f32] } (fminnum:{ *:[f32] } (VOP3Mods:{ *:[f32] } f32:{ *:[f32] }:$src0, i32:{ *:[i32] }:$src0_mods), (VOP3Mods:{ *:[f32] } f32:{ *:[f32] }:$src1, i32:{ *:[i32] }:$src1_mods)), (fminnum_ieee:{ *:[f32] } (fmaxnum_ieee:{ *:[f32] } (VOP3Mods:{ *:[f32] } f32:{ *:[f32] }:$src1, i32:{ *:[i32] }:$src1_mods), (VOP3Mods:{ *:[f32] } f32:{ *:[f32] }:$src0, i32:{ *:[i32] }:$src0_mods)), (VOP3Mods:{ *:[f32] } f32:{ *:[f32] }:$src2, i32:{ *:[i32] }:$src2_mods)))<<P:Predicate_fmaxnum_like_nnan>>  =>  (V_MED3_F32_e64:{ *:[f32] } ?:{ *:[i32] }:$src0_mods, ?:{ *:[f32] }:$src0, ?:{ *:[i32] }:$src1_mods, ?:{ *:[f32] }:$src1, ?:{ *:[i32] }:$src2_mods, ?:{ *:[f32] }:$src2, 0:{ *:[i1] }, 0:{ *:[i32] })
        GIR_BuildMI, /*InsnID*/0, /*Opcode*/GIMT_Encode2(AMDGPU::V_MED3_F32_e64),
        GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/0, // DstI[vdst]
        GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/1, // src0_mods
        GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/0, // src0
        GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(1), /*SubOperand*/1, // src1_mods
        GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(1), /*SubOperand*/0, // src1
        GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(2), /*SubOperand*/1, // src2_mods
        GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(2), /*SubOperand*/0, // src2
        GIR_AddImm8, /*InsnID*/0, /*Imm*/0,
        GIR_AddImm8, /*InsnID*/0, /*Imm*/0,
        GIR_ConstrainSelectedInstOperands, /*InsnID*/0,
        GIR_EraseFromParent, /*InsnID*/0,
        // GIR_Coverage, 10180,
        GIR_Done,
      // Label 4641: @311906
      GIM_Try, /*On fail goto*//*Label 4642*/ GIMT_Encode4(312046), // Rule ID 10183 //
        GIM_CheckRegBankForClass, /*MI*/0, /*Op*/0, /*RC*/GIMT_Encode2(AMDGPU::VGPR_32RegClassID),
        GIM_RecordInsn, /*DefineMI*/1, /*MI*/0, /*OpIdx*/1, // MIs[1]
        GIM_CheckOpcode, /*MI*/1, GIMT_Encode2(TargetOpcode::G_FMINNUM),
        GIM_CheckType, /*MI*/1, /*Op*/1, /*Type*/GILLT_s32,
        GIM_CheckType, /*MI*/1, /*Op*/2, /*Type*/GILLT_s32,
        GIM_RecordInsn, /*DefineMI*/2, /*MI*/0, /*OpIdx*/2, // MIs[2]
        GIM_CheckOpcode, /*MI*/2, GIMT_Encode2(TargetOpcode::G_FMINNUM_IEEE),
        GIM_CheckType, /*MI*/2, /*Op*/1, /*Type*/GILLT_s32,
        GIM_CheckType, /*MI*/2, /*Op*/2, /*Type*/GILLT_s32,
        GIM_RecordInsn, /*DefineMI*/3, /*MI*/2, /*OpIdx*/1, // MIs[3]
        GIM_CheckOpcode, /*MI*/3, GIMT_Encode2(TargetOpcode::G_FMAXNUM_IEEE),
        // MIs[3] VOP3Mods:src0:src0_mods
        GIM_CheckIsSameOperand, /*MI*/3, /*OpIdx*/1, /*OtherMI*/1, /*OtherOpIdx*/2,
        // MIs[3] VOP3Mods:src1:src1_mods
        GIM_CheckIsSameOperand, /*MI*/3, /*OpIdx*/2, /*OtherMI*/1, /*OtherOpIdx*/1,
        GIM_CheckCxxInsnPredicate, /*MI*/0, /*FnId*/GIMT_Encode2(GICXXPred_MI_Predicate_fmaxnum_like_nnan),
        GIM_CheckIsSafeToFold, /*InsnID*/1,
        GIM_CheckIsSafeToFold, /*InsnID*/2,
        GIM_CheckIsSafeToFold, /*InsnID*/3,
        GIM_CheckComplexPattern, /*MI*/1, /*Op*/1, /*Renderer*/GIMT_Encode2(0), GIMT_Encode2(GICP_gi_vop3mods),
        GIM_CheckComplexPattern, /*MI*/1, /*Op*/2, /*Renderer*/GIMT_Encode2(1), GIMT_Encode2(GICP_gi_vop3mods),
        GIM_CheckComplexPattern, /*MI*/2, /*Op*/2, /*Renderer*/GIMT_Encode2(2), GIMT_Encode2(GICP_gi_vop3mods),
        // (fmaxnum:{ *:[f32] } (fminnum:{ *:[f32] } (VOP3Mods:{ *:[f32] } f32:{ *:[f32] }:$src1, i32:{ *:[i32] }:$src1_mods), (VOP3Mods:{ *:[f32] } f32:{ *:[f32] }:$src0, i32:{ *:[i32] }:$src0_mods)), (fminnum_ieee:{ *:[f32] } (fmaxnum_ieee:{ *:[f32] } (VOP3Mods:{ *:[f32] } f32:{ *:[f32] }:$src0, i32:{ *:[i32] }:$src0_mods), (VOP3Mods:{ *:[f32] } f32:{ *:[f32] }:$src1, i32:{ *:[i32] }:$src1_mods)), (VOP3Mods:{ *:[f32] } f32:{ *:[f32] }:$src2, i32:{ *:[i32] }:$src2_mods)))<<P:Predicate_fmaxnum_like_nnan>>  =>  (V_MED3_F32_e64:{ *:[f32] } ?:{ *:[i32] }:$src0_mods, ?:{ *:[f32] }:$src0, ?:{ *:[i32] }:$src1_mods, ?:{ *:[f32] }:$src1, ?:{ *:[i32] }:$src2_mods, ?:{ *:[f32] }:$src2, 0:{ *:[i1] }, 0:{ *:[i32] })
        GIR_BuildMI, /*InsnID*/0, /*Opcode*/GIMT_Encode2(AMDGPU::V_MED3_F32_e64),
        GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/0, // DstI[vdst]
        GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(1), /*SubOperand*/1, // src0_mods
        GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(1), /*SubOperand*/0, // src0
        GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/1, // src1_mods
        GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/0, // src1
        GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(2), /*SubOperand*/1, // src2_mods
        GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(2), /*SubOperand*/0, // src2
        GIR_AddImm8, /*InsnID*/0, /*Imm*/0,
        GIR_AddImm8, /*InsnID*/0, /*Imm*/0,
        GIR_ConstrainSelectedInstOperands, /*InsnID*/0,
        GIR_EraseFromParent, /*InsnID*/0,
        // GIR_Coverage, 10183,
        GIR_Done,
      // Label 4642: @312046
      GIM_Try, /*On fail goto*//*Label 4643*/ GIMT_Encode4(312186), // Rule ID 10184 //
        GIM_CheckRegBankForClass, /*MI*/0, /*Op*/0, /*RC*/GIMT_Encode2(AMDGPU::VGPR_32RegClassID),
        GIM_RecordInsn, /*DefineMI*/1, /*MI*/0, /*OpIdx*/1, // MIs[1]
        GIM_CheckOpcode, /*MI*/1, GIMT_Encode2(TargetOpcode::G_FMINNUM),
        GIM_CheckType, /*MI*/1, /*Op*/1, /*Type*/GILLT_s32,
        GIM_CheckType, /*MI*/1, /*Op*/2, /*Type*/GILLT_s32,
        GIM_RecordInsn, /*DefineMI*/2, /*MI*/0, /*OpIdx*/2, // MIs[2]
        GIM_CheckOpcode, /*MI*/2, GIMT_Encode2(TargetOpcode::G_FMINNUM_IEEE),
        GIM_CheckType, /*MI*/2, /*Op*/1, /*Type*/GILLT_s32,
        GIM_CheckType, /*MI*/2, /*Op*/2, /*Type*/GILLT_s32,
        GIM_RecordInsn, /*DefineMI*/3, /*MI*/2, /*OpIdx*/1, // MIs[3]
        GIM_CheckOpcode, /*MI*/3, GIMT_Encode2(TargetOpcode::G_FMAXNUM_IEEE),
        // MIs[3] VOP3Mods:src1:src1_mods
        GIM_CheckIsSameOperand, /*MI*/3, /*OpIdx*/1, /*OtherMI*/1, /*OtherOpIdx*/1,
        // MIs[3] VOP3Mods:src0:src0_mods
        GIM_CheckIsSameOperand, /*MI*/3, /*OpIdx*/2, /*OtherMI*/1, /*OtherOpIdx*/2,
        GIM_CheckCxxInsnPredicate, /*MI*/0, /*FnId*/GIMT_Encode2(GICXXPred_MI_Predicate_fmaxnum_like_nnan),
        GIM_CheckIsSafeToFold, /*InsnID*/1,
        GIM_CheckIsSafeToFold, /*InsnID*/2,
        GIM_CheckIsSafeToFold, /*InsnID*/3,
        GIM_CheckComplexPattern, /*MI*/1, /*Op*/1, /*Renderer*/GIMT_Encode2(0), GIMT_Encode2(GICP_gi_vop3mods),
        GIM_CheckComplexPattern, /*MI*/1, /*Op*/2, /*Renderer*/GIMT_Encode2(1), GIMT_Encode2(GICP_gi_vop3mods),
        GIM_CheckComplexPattern, /*MI*/2, /*Op*/2, /*Renderer*/GIMT_Encode2(2), GIMT_Encode2(GICP_gi_vop3mods),
        // (fmaxnum:{ *:[f32] } (fminnum:{ *:[f32] } (VOP3Mods:{ *:[f32] } f32:{ *:[f32] }:$src1, i32:{ *:[i32] }:$src1_mods), (VOP3Mods:{ *:[f32] } f32:{ *:[f32] }:$src0, i32:{ *:[i32] }:$src0_mods)), (fminnum_ieee:{ *:[f32] } (fmaxnum_ieee:{ *:[f32] } (VOP3Mods:{ *:[f32] } f32:{ *:[f32] }:$src1, i32:{ *:[i32] }:$src1_mods), (VOP3Mods:{ *:[f32] } f32:{ *:[f32] }:$src0, i32:{ *:[i32] }:$src0_mods)), (VOP3Mods:{ *:[f32] } f32:{ *:[f32] }:$src2, i32:{ *:[i32] }:$src2_mods)))<<P:Predicate_fmaxnum_like_nnan>>  =>  (V_MED3_F32_e64:{ *:[f32] } ?:{ *:[i32] }:$src0_mods, ?:{ *:[f32] }:$src0, ?:{ *:[i32] }:$src1_mods, ?:{ *:[f32] }:$src1, ?:{ *:[i32] }:$src2_mods, ?:{ *:[f32] }:$src2, 0:{ *:[i1] }, 0:{ *:[i32] })
        GIR_BuildMI, /*InsnID*/0, /*Opcode*/GIMT_Encode2(AMDGPU::V_MED3_F32_e64),
        GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/0, // DstI[vdst]
        GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(1), /*SubOperand*/1, // src0_mods
        GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(1), /*SubOperand*/0, // src0
        GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/1, // src1_mods
        GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/0, // src1
        GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(2), /*SubOperand*/1, // src2_mods
        GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(2), /*SubOperand*/0, // src2
        GIR_AddImm8, /*InsnID*/0, /*Imm*/0,
        GIR_AddImm8, /*InsnID*/0, /*Imm*/0,
        GIR_ConstrainSelectedInstOperands, /*InsnID*/0,
        GIR_EraseFromParent, /*InsnID*/0,
        // GIR_Coverage, 10184,
        GIR_Done,
      // Label 4643: @312186
      GIM_Try, /*On fail goto*//*Label 4644*/ GIMT_Encode4(312326), // Rule ID 10236 //
        GIM_CheckRegBankForClass, /*MI*/0, /*Op*/0, /*RC*/GIMT_Encode2(AMDGPU::VGPR_32RegClassID),
        GIM_RecordInsn, /*DefineMI*/1, /*MI*/0, /*OpIdx*/1, // MIs[1]
        GIM_CheckOpcode, /*MI*/1, GIMT_Encode2(TargetOpcode::G_FMINNUM),
        GIM_CheckType, /*MI*/1, /*Op*/1, /*Type*/GILLT_s32,
        GIM_CheckType, /*MI*/1, /*Op*/2, /*Type*/GILLT_s32,
        GIM_RecordInsn, /*DefineMI*/2, /*MI*/1, /*OpIdx*/2, // MIs[2]
        GIM_CheckOpcode, /*MI*/2, GIMT_Encode2(TargetOpcode::G_FMAXNUM),
        GIM_CheckType, /*MI*/2, /*Op*/1, /*Type*/GILLT_s32,
        GIM_CheckType, /*MI*/2, /*Op*/2, /*Type*/GILLT_s32,
        GIM_RecordInsn, /*DefineMI*/3, /*MI*/0, /*OpIdx*/2, // MIs[3]
        GIM_CheckOpcode, /*MI*/3, GIMT_Encode2(TargetOpcode::G_FMINNUM),
        // MIs[3] VOP3Mods:src0:src0_mods
        GIM_CheckIsSameOperand, /*MI*/3, /*OpIdx*/1, /*OtherMI*/2, /*OtherOpIdx*/1,
        // MIs[3] VOP3Mods:src1:src1_mods
        GIM_CheckIsSameOperand, /*MI*/3, /*OpIdx*/2, /*OtherMI*/2, /*OtherOpIdx*/2,
        GIM_CheckCxxInsnPredicate, /*MI*/0, /*FnId*/GIMT_Encode2(GICXXPred_MI_Predicate_fmaxnum_like_nnan),
        GIM_CheckIsSafeToFold, /*InsnID*/1,
        GIM_CheckIsSafeToFold, /*InsnID*/2,
        GIM_CheckIsSafeToFold, /*InsnID*/3,
        GIM_CheckComplexPattern, /*MI*/1, /*Op*/1, /*Renderer*/GIMT_Encode2(0), GIMT_Encode2(GICP_gi_vop3mods),
        GIM_CheckComplexPattern, /*MI*/2, /*Op*/1, /*Renderer*/GIMT_Encode2(1), GIMT_Encode2(GICP_gi_vop3mods),
        GIM_CheckComplexPattern, /*MI*/2, /*Op*/2, /*Renderer*/GIMT_Encode2(2), GIMT_Encode2(GICP_gi_vop3mods),
        // (fmaxnum:{ *:[f32] } (fminnum:{ *:[f32] } (VOP3Mods:{ *:[f32] } f32:{ *:[f32] }:$src2, i32:{ *:[i32] }:$src2_mods), (fmaxnum:{ *:[f32] } (VOP3Mods:{ *:[f32] } f32:{ *:[f32] }:$src0, i32:{ *:[i32] }:$src0_mods), (VOP3Mods:{ *:[f32] } f32:{ *:[f32] }:$src1, i32:{ *:[i32] }:$src1_mods))), (fminnum:{ *:[f32] } (VOP3Mods:{ *:[f32] } f32:{ *:[f32] }:$src0, i32:{ *:[i32] }:$src0_mods), (VOP3Mods:{ *:[f32] } f32:{ *:[f32] }:$src1, i32:{ *:[i32] }:$src1_mods)))<<P:Predicate_fmaxnum_like_nnan>>  =>  (V_MED3_F32_e64:{ *:[f32] } ?:{ *:[i32] }:$src0_mods, ?:{ *:[f32] }:$src0, ?:{ *:[i32] }:$src1_mods, ?:{ *:[f32] }:$src1, ?:{ *:[i32] }:$src2_mods, ?:{ *:[f32] }:$src2, 0:{ *:[i1] }, 0:{ *:[i32] })
        GIR_BuildMI, /*InsnID*/0, /*Opcode*/GIMT_Encode2(AMDGPU::V_MED3_F32_e64),
        GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/0, // DstI[vdst]
        GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(1), /*SubOperand*/1, // src0_mods
        GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(1), /*SubOperand*/0, // src0
        GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(2), /*SubOperand*/1, // src1_mods
        GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(2), /*SubOperand*/0, // src1
        GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/1, // src2_mods
        GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/0, // src2
        GIR_AddImm8, /*InsnID*/0, /*Imm*/0,
        GIR_AddImm8, /*InsnID*/0, /*Imm*/0,
        GIR_ConstrainSelectedInstOperands, /*InsnID*/0,
        GIR_EraseFromParent, /*InsnID*/0,
        // GIR_Coverage, 10236,
        GIR_Done,
      // Label 4644: @312326
      GIM_Try, /*On fail goto*//*Label 4645*/ GIMT_Encode4(312466), // Rule ID 10237 //
        GIM_CheckRegBankForClass, /*MI*/0, /*Op*/0, /*RC*/GIMT_Encode2(AMDGPU::VGPR_32RegClassID),
        GIM_RecordInsn, /*DefineMI*/1, /*MI*/0, /*OpIdx*/1, // MIs[1]
        GIM_CheckOpcode, /*MI*/1, GIMT_Encode2(TargetOpcode::G_FMINNUM),
        GIM_CheckType, /*MI*/1, /*Op*/1, /*Type*/GILLT_s32,
        GIM_CheckType, /*MI*/1, /*Op*/2, /*Type*/GILLT_s32,
        GIM_RecordInsn, /*DefineMI*/2, /*MI*/1, /*OpIdx*/2, // MIs[2]
        GIM_CheckOpcode, /*MI*/2, GIMT_Encode2(TargetOpcode::G_FMAXNUM),
        GIM_CheckType, /*MI*/2, /*Op*/1, /*Type*/GILLT_s32,
        GIM_CheckType, /*MI*/2, /*Op*/2, /*Type*/GILLT_s32,
        GIM_RecordInsn, /*DefineMI*/3, /*MI*/0, /*OpIdx*/2, // MIs[3]
        GIM_CheckOpcode, /*MI*/3, GIMT_Encode2(TargetOpcode::G_FMINNUM),
        // MIs[3] VOP3Mods:src1:src1_mods
        GIM_CheckIsSameOperand, /*MI*/3, /*OpIdx*/1, /*OtherMI*/2, /*OtherOpIdx*/2,
        // MIs[3] VOP3Mods:src0:src0_mods
        GIM_CheckIsSameOperand, /*MI*/3, /*OpIdx*/2, /*OtherMI*/2, /*OtherOpIdx*/1,
        GIM_CheckCxxInsnPredicate, /*MI*/0, /*FnId*/GIMT_Encode2(GICXXPred_MI_Predicate_fmaxnum_like_nnan),
        GIM_CheckIsSafeToFold, /*InsnID*/1,
        GIM_CheckIsSafeToFold, /*InsnID*/2,
        GIM_CheckIsSafeToFold, /*InsnID*/3,
        GIM_CheckComplexPattern, /*MI*/1, /*Op*/1, /*Renderer*/GIMT_Encode2(0), GIMT_Encode2(GICP_gi_vop3mods),
        GIM_CheckComplexPattern, /*MI*/2, /*Op*/1, /*Renderer*/GIMT_Encode2(1), GIMT_Encode2(GICP_gi_vop3mods),
        GIM_CheckComplexPattern, /*MI*/2, /*Op*/2, /*Renderer*/GIMT_Encode2(2), GIMT_Encode2(GICP_gi_vop3mods),
        // (fmaxnum:{ *:[f32] } (fminnum:{ *:[f32] } (VOP3Mods:{ *:[f32] } f32:{ *:[f32] }:$src2, i32:{ *:[i32] }:$src2_mods), (fmaxnum:{ *:[f32] } (VOP3Mods:{ *:[f32] } f32:{ *:[f32] }:$src0, i32:{ *:[i32] }:$src0_mods), (VOP3Mods:{ *:[f32] } f32:{ *:[f32] }:$src1, i32:{ *:[i32] }:$src1_mods))), (fminnum:{ *:[f32] } (VOP3Mods:{ *:[f32] } f32:{ *:[f32] }:$src1, i32:{ *:[i32] }:$src1_mods), (VOP3Mods:{ *:[f32] } f32:{ *:[f32] }:$src0, i32:{ *:[i32] }:$src0_mods)))<<P:Predicate_fmaxnum_like_nnan>>  =>  (V_MED3_F32_e64:{ *:[f32] } ?:{ *:[i32] }:$src0_mods, ?:{ *:[f32] }:$src0, ?:{ *:[i32] }:$src1_mods, ?:{ *:[f32] }:$src1, ?:{ *:[i32] }:$src2_mods, ?:{ *:[f32] }:$src2, 0:{ *:[i1] }, 0:{ *:[i32] })
        GIR_BuildMI, /*InsnID*/0, /*Opcode*/GIMT_Encode2(AMDGPU::V_MED3_F32_e64),
        GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/0, // DstI[vdst]
        GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(1), /*SubOperand*/1, // src0_mods
        GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(1), /*SubOperand*/0, // src0
        GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(2), /*SubOperand*/1, // src1_mods
        GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(2), /*SubOperand*/0, // src1
        GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/1, // src2_mods
        GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/0, // src2
        GIR_AddImm8, /*InsnID*/0, /*Imm*/0,
        GIR_AddImm8, /*InsnID*/0, /*Imm*/0,
        GIR_ConstrainSelectedInstOperands, /*InsnID*/0,
        GIR_EraseFromParent, /*InsnID*/0,
        // GIR_Coverage, 10237,
        GIR_Done,
      // Label 4645: @312466
      GIM_Try, /*On fail goto*//*Label 4646*/ GIMT_Encode4(312606), // Rule ID 10238 //
        GIM_CheckRegBankForClass, /*MI*/0, /*Op*/0, /*RC*/GIMT_Encode2(AMDGPU::VGPR_32RegClassID),
        GIM_RecordInsn, /*DefineMI*/1, /*MI*/0, /*OpIdx*/1, // MIs[1]
        GIM_CheckOpcode, /*MI*/1, GIMT_Encode2(TargetOpcode::G_FMINNUM),
        GIM_CheckType, /*MI*/1, /*Op*/1, /*Type*/GILLT_s32,
        GIM_CheckType, /*MI*/1, /*Op*/2, /*Type*/GILLT_s32,
        GIM_RecordInsn, /*DefineMI*/2, /*MI*/1, /*OpIdx*/2, // MIs[2]
        GIM_CheckOpcode, /*MI*/2, GIMT_Encode2(TargetOpcode::G_FMAXNUM),
        GIM_CheckType, /*MI*/2, /*Op*/1, /*Type*/GILLT_s32,
        GIM_CheckType, /*MI*/2, /*Op*/2, /*Type*/GILLT_s32,
        GIM_RecordInsn, /*DefineMI*/3, /*MI*/0, /*OpIdx*/2, // MIs[3]
        GIM_CheckOpcode, /*MI*/3, GIMT_Encode2(TargetOpcode::G_FMINNUM),
        // MIs[3] VOP3Mods:src0:src0_mods
        GIM_CheckIsSameOperand, /*MI*/3, /*OpIdx*/1, /*OtherMI*/2, /*OtherOpIdx*/2,
        // MIs[3] VOP3Mods:src1:src1_mods
        GIM_CheckIsSameOperand, /*MI*/3, /*OpIdx*/2, /*OtherMI*/2, /*OtherOpIdx*/1,
        GIM_CheckCxxInsnPredicate, /*MI*/0, /*FnId*/GIMT_Encode2(GICXXPred_MI_Predicate_fmaxnum_like_nnan),
        GIM_CheckIsSafeToFold, /*InsnID*/1,
        GIM_CheckIsSafeToFold, /*InsnID*/2,
        GIM_CheckIsSafeToFold, /*InsnID*/3,
        GIM_CheckComplexPattern, /*MI*/1, /*Op*/1, /*Renderer*/GIMT_Encode2(0), GIMT_Encode2(GICP_gi_vop3mods),
        GIM_CheckComplexPattern, /*MI*/2, /*Op*/1, /*Renderer*/GIMT_Encode2(1), GIMT_Encode2(GICP_gi_vop3mods),
        GIM_CheckComplexPattern, /*MI*/2, /*Op*/2, /*Renderer*/GIMT_Encode2(2), GIMT_Encode2(GICP_gi_vop3mods),
        // (fmaxnum:{ *:[f32] } (fminnum:{ *:[f32] } (VOP3Mods:{ *:[f32] } f32:{ *:[f32] }:$src2, i32:{ *:[i32] }:$src2_mods), (fmaxnum:{ *:[f32] } (VOP3Mods:{ *:[f32] } f32:{ *:[f32] }:$src1, i32:{ *:[i32] }:$src1_mods), (VOP3Mods:{ *:[f32] } f32:{ *:[f32] }:$src0, i32:{ *:[i32] }:$src0_mods))), (fminnum:{ *:[f32] } (VOP3Mods:{ *:[f32] } f32:{ *:[f32] }:$src0, i32:{ *:[i32] }:$src0_mods), (VOP3Mods:{ *:[f32] } f32:{ *:[f32] }:$src1, i32:{ *:[i32] }:$src1_mods)))<<P:Predicate_fmaxnum_like_nnan>>  =>  (V_MED3_F32_e64:{ *:[f32] } ?:{ *:[i32] }:$src0_mods, ?:{ *:[f32] }:$src0, ?:{ *:[i32] }:$src1_mods, ?:{ *:[f32] }:$src1, ?:{ *:[i32] }:$src2_mods, ?:{ *:[f32] }:$src2, 0:{ *:[i1] }, 0:{ *:[i32] })
        GIR_BuildMI, /*InsnID*/0, /*Opcode*/GIMT_Encode2(AMDGPU::V_MED3_F32_e64),
        GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/0, // DstI[vdst]
        GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(2), /*SubOperand*/1, // src0_mods
        GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(2), /*SubOperand*/0, // src0
        GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(1), /*SubOperand*/1, // src1_mods
        GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(1), /*SubOperand*/0, // src1
        GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/1, // src2_mods
        GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/0, // src2
        GIR_AddImm8, /*InsnID*/0, /*Imm*/0,
        GIR_AddImm8, /*InsnID*/0, /*Imm*/0,
        GIR_ConstrainSelectedInstOperands, /*InsnID*/0,
        GIR_EraseFromParent, /*InsnID*/0,
        // GIR_Coverage, 10238,
        GIR_Done,
      // Label 4646: @312606
      GIM_Try, /*On fail goto*//*Label 4647*/ GIMT_Encode4(312746), // Rule ID 10239 //
        GIM_CheckRegBankForClass, /*MI*/0, /*Op*/0, /*RC*/GIMT_Encode2(AMDGPU::VGPR_32RegClassID),
        GIM_RecordInsn, /*DefineMI*/1, /*MI*/0, /*OpIdx*/1, // MIs[1]
        GIM_CheckOpcode, /*MI*/1, GIMT_Encode2(TargetOpcode::G_FMINNUM),
        GIM_CheckType, /*MI*/1, /*Op*/1, /*Type*/GILLT_s32,
        GIM_CheckType, /*MI*/1, /*Op*/2, /*Type*/GILLT_s32,
        GIM_RecordInsn, /*DefineMI*/2, /*MI*/1, /*OpIdx*/2, // MIs[2]
        GIM_CheckOpcode, /*MI*/2, GIMT_Encode2(TargetOpcode::G_FMAXNUM),
        GIM_CheckType, /*MI*/2, /*Op*/1, /*Type*/GILLT_s32,
        GIM_CheckType, /*MI*/2, /*Op*/2, /*Type*/GILLT_s32,
        GIM_RecordInsn, /*DefineMI*/3, /*MI*/0, /*OpIdx*/2, // MIs[3]
        GIM_CheckOpcode, /*MI*/3, GIMT_Encode2(TargetOpcode::G_FMINNUM),
        // MIs[3] VOP3Mods:src1:src1_mods
        GIM_CheckIsSameOperand, /*MI*/3, /*OpIdx*/1, /*OtherMI*/2, /*OtherOpIdx*/1,
        // MIs[3] VOP3Mods:src0:src0_mods
        GIM_CheckIsSameOperand, /*MI*/3, /*OpIdx*/2, /*OtherMI*/2, /*OtherOpIdx*/2,
        GIM_CheckCxxInsnPredicate, /*MI*/0, /*FnId*/GIMT_Encode2(GICXXPred_MI_Predicate_fmaxnum_like_nnan),
        GIM_CheckIsSafeToFold, /*InsnID*/1,
        GIM_CheckIsSafeToFold, /*InsnID*/2,
        GIM_CheckIsSafeToFold, /*InsnID*/3,
        GIM_CheckComplexPattern, /*MI*/1, /*Op*/1, /*Renderer*/GIMT_Encode2(0), GIMT_Encode2(GICP_gi_vop3mods),
        GIM_CheckComplexPattern, /*MI*/2, /*Op*/1, /*Renderer*/GIMT_Encode2(1), GIMT_Encode2(GICP_gi_vop3mods),
        GIM_CheckComplexPattern, /*MI*/2, /*Op*/2, /*Renderer*/GIMT_Encode2(2), GIMT_Encode2(GICP_gi_vop3mods),
        // (fmaxnum:{ *:[f32] } (fminnum:{ *:[f32] } (VOP3Mods:{ *:[f32] } f32:{ *:[f32] }:$src2, i32:{ *:[i32] }:$src2_mods), (fmaxnum:{ *:[f32] } (VOP3Mods:{ *:[f32] } f32:{ *:[f32] }:$src1, i32:{ *:[i32] }:$src1_mods), (VOP3Mods:{ *:[f32] } f32:{ *:[f32] }:$src0, i32:{ *:[i32] }:$src0_mods))), (fminnum:{ *:[f32] } (VOP3Mods:{ *:[f32] } f32:{ *:[f32] }:$src1, i32:{ *:[i32] }:$src1_mods), (VOP3Mods:{ *:[f32] } f32:{ *:[f32] }:$src0, i32:{ *:[i32] }:$src0_mods)))<<P:Predicate_fmaxnum_like_nnan>>  =>  (V_MED3_F32_e64:{ *:[f32] } ?:{ *:[i32] }:$src0_mods, ?:{ *:[f32] }:$src0, ?:{ *:[i32] }:$src1_mods, ?:{ *:[f32] }:$src1, ?:{ *:[i32] }:$src2_mods, ?:{ *:[f32] }:$src2, 0:{ *:[i1] }, 0:{ *:[i32] })
        GIR_BuildMI, /*InsnID*/0, /*Opcode*/GIMT_Encode2(AMDGPU::V_MED3_F32_e64),
        GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/0, // DstI[vdst]
        GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(2), /*SubOperand*/1, // src0_mods
        GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(2), /*SubOperand*/0, // src0
        GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(1), /*SubOperand*/1, // src1_mods
        GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(1), /*SubOperand*/0, // src1
        GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/1, // src2_mods
        GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/0, // src2
        GIR_AddImm8, /*InsnID*/0, /*Imm*/0,
        GIR_AddImm8, /*InsnID*/0, /*Imm*/0,
        GIR_ConstrainSelectedInstOperands, /*InsnID*/0,
        GIR_EraseFromParent, /*InsnID*/0,
        // GIR_Coverage, 10239,
        GIR_Done,
      // Label 4647: @312746
      GIM_Try, /*On fail goto*//*Label 4648*/ GIMT_Encode4(312886), // Rule ID 10176 //
        GIM_CheckRegBankForClass, /*MI*/0, /*Op*/0, /*RC*/GIMT_Encode2(AMDGPU::VGPR_32RegClassID),
        GIM_RecordInsn, /*DefineMI*/1, /*MI*/0, /*OpIdx*/1, // MIs[1]
        GIM_CheckOpcode, /*MI*/1, GIMT_Encode2(TargetOpcode::G_FMINNUM),
        GIM_CheckType, /*MI*/1, /*Op*/1, /*Type*/GILLT_s32,
        GIM_CheckType, /*MI*/1, /*Op*/2, /*Type*/GILLT_s32,
        GIM_RecordInsn, /*DefineMI*/2, /*MI*/1, /*OpIdx*/2, // MIs[2]
        GIM_CheckOpcode, /*MI*/2, GIMT_Encode2(TargetOpcode::G_FMAXNUM),
        GIM_CheckType, /*MI*/2, /*Op*/1, /*Type*/GILLT_s32,
        GIM_CheckType, /*MI*/2, /*Op*/2, /*Type*/GILLT_s32,
        GIM_RecordInsn, /*DefineMI*/3, /*MI*/0, /*OpIdx*/2, // MIs[3]
        GIM_CheckOpcode, /*MI*/3, GIMT_Encode2(TargetOpcode::G_FMINNUM_IEEE),
        // MIs[3] VOP3Mods:src0:src0_mods
        GIM_CheckIsSameOperand, /*MI*/3, /*OpIdx*/1, /*OtherMI*/2, /*OtherOpIdx*/1,
        // MIs[3] VOP3Mods:src1:src1_mods
        GIM_CheckIsSameOperand, /*MI*/3, /*OpIdx*/2, /*OtherMI*/2, /*OtherOpIdx*/2,
        GIM_CheckCxxInsnPredicate, /*MI*/0, /*FnId*/GIMT_Encode2(GICXXPred_MI_Predicate_fmaxnum_like_nnan),
        GIM_CheckIsSafeToFold, /*InsnID*/1,
        GIM_CheckIsSafeToFold, /*InsnID*/2,
        GIM_CheckIsSafeToFold, /*InsnID*/3,
        GIM_CheckComplexPattern, /*MI*/1, /*Op*/1, /*Renderer*/GIMT_Encode2(0), GIMT_Encode2(GICP_gi_vop3mods),
        GIM_CheckComplexPattern, /*MI*/2, /*Op*/1, /*Renderer*/GIMT_Encode2(1), GIMT_Encode2(GICP_gi_vop3mods),
        GIM_CheckComplexPattern, /*MI*/2, /*Op*/2, /*Renderer*/GIMT_Encode2(2), GIMT_Encode2(GICP_gi_vop3mods),
        // (fmaxnum:{ *:[f32] } (fminnum:{ *:[f32] } (VOP3Mods:{ *:[f32] } f32:{ *:[f32] }:$src2, i32:{ *:[i32] }:$src2_mods), (fmaxnum:{ *:[f32] } (VOP3Mods:{ *:[f32] } f32:{ *:[f32] }:$src0, i32:{ *:[i32] }:$src0_mods), (VOP3Mods:{ *:[f32] } f32:{ *:[f32] }:$src1, i32:{ *:[i32] }:$src1_mods))), (fminnum_ieee:{ *:[f32] } (VOP3Mods:{ *:[f32] } f32:{ *:[f32] }:$src0, i32:{ *:[i32] }:$src0_mods), (VOP3Mods:{ *:[f32] } f32:{ *:[f32] }:$src1, i32:{ *:[i32] }:$src1_mods)))<<P:Predicate_fmaxnum_like_nnan>>  =>  (V_MED3_F32_e64:{ *:[f32] } ?:{ *:[i32] }:$src0_mods, ?:{ *:[f32] }:$src0, ?:{ *:[i32] }:$src1_mods, ?:{ *:[f32] }:$src1, ?:{ *:[i32] }:$src2_mods, ?:{ *:[f32] }:$src2, 0:{ *:[i1] }, 0:{ *:[i32] })
        GIR_BuildMI, /*InsnID*/0, /*Opcode*/GIMT_Encode2(AMDGPU::V_MED3_F32_e64),
        GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/0, // DstI[vdst]
        GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(1), /*SubOperand*/1, // src0_mods
        GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(1), /*SubOperand*/0, // src0
        GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(2), /*SubOperand*/1, // src1_mods
        GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(2), /*SubOperand*/0, // src1
        GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/1, // src2_mods
        GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/0, // src2
        GIR_AddImm8, /*InsnID*/0, /*Imm*/0,
        GIR_AddImm8, /*InsnID*/0, /*Imm*/0,
        GIR_ConstrainSelectedInstOperands, /*InsnID*/0,
        GIR_EraseFromParent, /*InsnID*/0,
        // GIR_Coverage, 10176,
        GIR_Done,
      // Label 4648: @312886
      GIM_Try, /*On fail goto*//*Label 4649*/ GIMT_Encode4(313026), // Rule ID 10177 //
        GIM_CheckRegBankForClass, /*MI*/0, /*Op*/0, /*RC*/GIMT_Encode2(AMDGPU::VGPR_32RegClassID),
        GIM_RecordInsn, /*DefineMI*/1, /*MI*/0, /*OpIdx*/1, // MIs[1]
        GIM_CheckOpcode, /*MI*/1, GIMT_Encode2(TargetOpcode::G_FMINNUM),
        GIM_CheckType, /*MI*/1, /*Op*/1, /*Type*/GILLT_s32,
        GIM_CheckType, /*MI*/1, /*Op*/2, /*Type*/GILLT_s32,
        GIM_RecordInsn, /*DefineMI*/2, /*MI*/1, /*OpIdx*/2, // MIs[2]
        GIM_CheckOpcode, /*MI*/2, GIMT_Encode2(TargetOpcode::G_FMAXNUM),
        GIM_CheckType, /*MI*/2, /*Op*/1, /*Type*/GILLT_s32,
        GIM_CheckType, /*MI*/2, /*Op*/2, /*Type*/GILLT_s32,
        GIM_RecordInsn, /*DefineMI*/3, /*MI*/0, /*OpIdx*/2, // MIs[3]
        GIM_CheckOpcode, /*MI*/3, GIMT_Encode2(TargetOpcode::G_FMINNUM_IEEE),
        // MIs[3] VOP3Mods:src1:src1_mods
        GIM_CheckIsSameOperand, /*MI*/3, /*OpIdx*/1, /*OtherMI*/2, /*OtherOpIdx*/2,
        // MIs[3] VOP3Mods:src0:src0_mods
        GIM_CheckIsSameOperand, /*MI*/3, /*OpIdx*/2, /*OtherMI*/2, /*OtherOpIdx*/1,
        GIM_CheckCxxInsnPredicate, /*MI*/0, /*FnId*/GIMT_Encode2(GICXXPred_MI_Predicate_fmaxnum_like_nnan),
        GIM_CheckIsSafeToFold, /*InsnID*/1,
        GIM_CheckIsSafeToFold, /*InsnID*/2,
        GIM_CheckIsSafeToFold, /*InsnID*/3,
        GIM_CheckComplexPattern, /*MI*/1, /*Op*/1, /*Renderer*/GIMT_Encode2(0), GIMT_Encode2(GICP_gi_vop3mods),
        GIM_CheckComplexPattern, /*MI*/2, /*Op*/1, /*Renderer*/GIMT_Encode2(1), GIMT_Encode2(GICP_gi_vop3mods),
        GIM_CheckComplexPattern, /*MI*/2, /*Op*/2, /*Renderer*/GIMT_Encode2(2), GIMT_Encode2(GICP_gi_vop3mods),
        // (fmaxnum:{ *:[f32] } (fminnum:{ *:[f32] } (VOP3Mods:{ *:[f32] } f32:{ *:[f32] }:$src2, i32:{ *:[i32] }:$src2_mods), (fmaxnum:{ *:[f32] } (VOP3Mods:{ *:[f32] } f32:{ *:[f32] }:$src0, i32:{ *:[i32] }:$src0_mods), (VOP3Mods:{ *:[f32] } f32:{ *:[f32] }:$src1, i32:{ *:[i32] }:$src1_mods))), (fminnum_ieee:{ *:[f32] } (VOP3Mods:{ *:[f32] } f32:{ *:[f32] }:$src1, i32:{ *:[i32] }:$src1_mods), (VOP3Mods:{ *:[f32] } f32:{ *:[f32] }:$src0, i32:{ *:[i32] }:$src0_mods)))<<P:Predicate_fmaxnum_like_nnan>>  =>  (V_MED3_F32_e64:{ *:[f32] } ?:{ *:[i32] }:$src0_mods, ?:{ *:[f32] }:$src0, ?:{ *:[i32] }:$src1_mods, ?:{ *:[f32] }:$src1, ?:{ *:[i32] }:$src2_mods, ?:{ *:[f32] }:$src2, 0:{ *:[i1] }, 0:{ *:[i32] })
        GIR_BuildMI, /*InsnID*/0, /*Opcode*/GIMT_Encode2(AMDGPU::V_MED3_F32_e64),
        GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/0, // DstI[vdst]
        GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(1), /*SubOperand*/1, // src0_mods
        GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(1), /*SubOperand*/0, // src0
        GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(2), /*SubOperand*/1, // src1_mods
        GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(2), /*SubOperand*/0, // src1
        GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/1, // src2_mods
        GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/0, // src2
        GIR_AddImm8, /*InsnID*/0, /*Imm*/0,
        GIR_AddImm8, /*InsnID*/0, /*Imm*/0,
        GIR_ConstrainSelectedInstOperands, /*InsnID*/0,
        GIR_EraseFromParent, /*InsnID*/0,
        // GIR_Coverage, 10177,
        GIR_Done,
      // Label 4649: @313026
      GIM_Try, /*On fail goto*//*Label 4650*/ GIMT_Encode4(313166), // Rule ID 10178 //
        GIM_CheckRegBankForClass, /*MI*/0, /*Op*/0, /*RC*/GIMT_Encode2(AMDGPU::VGPR_32RegClassID),
        GIM_RecordInsn, /*DefineMI*/1, /*MI*/0, /*OpIdx*/1, // MIs[1]
        GIM_CheckOpcode, /*MI*/1, GIMT_Encode2(TargetOpcode::G_FMINNUM),
        GIM_CheckType, /*MI*/1, /*Op*/1, /*Type*/GILLT_s32,
        GIM_CheckType, /*MI*/1, /*Op*/2, /*Type*/GILLT_s32,
        GIM_RecordInsn, /*DefineMI*/2, /*MI*/1, /*OpIdx*/2, // MIs[2]
        GIM_CheckOpcode, /*MI*/2, GIMT_Encode2(TargetOpcode::G_FMAXNUM),
        GIM_CheckType, /*MI*/2, /*Op*/1, /*Type*/GILLT_s32,
        GIM_CheckType, /*MI*/2, /*Op*/2, /*Type*/GILLT_s32,
        GIM_RecordInsn, /*DefineMI*/3, /*MI*/0, /*OpIdx*/2, // MIs[3]
        GIM_CheckOpcode, /*MI*/3, GIMT_Encode2(TargetOpcode::G_FMINNUM_IEEE),
        // MIs[3] VOP3Mods:src0:src0_mods
        GIM_CheckIsSameOperand, /*MI*/3, /*OpIdx*/1, /*OtherMI*/2, /*OtherOpIdx*/2,
        // MIs[3] VOP3Mods:src1:src1_mods
        GIM_CheckIsSameOperand, /*MI*/3, /*OpIdx*/2, /*OtherMI*/2, /*OtherOpIdx*/1,
        GIM_CheckCxxInsnPredicate, /*MI*/0, /*FnId*/GIMT_Encode2(GICXXPred_MI_Predicate_fmaxnum_like_nnan),
        GIM_CheckIsSafeToFold, /*InsnID*/1,
        GIM_CheckIsSafeToFold, /*InsnID*/2,
        GIM_CheckIsSafeToFold, /*InsnID*/3,
        GIM_CheckComplexPattern, /*MI*/1, /*Op*/1, /*Renderer*/GIMT_Encode2(0), GIMT_Encode2(GICP_gi_vop3mods),
        GIM_CheckComplexPattern, /*MI*/2, /*Op*/1, /*Renderer*/GIMT_Encode2(1), GIMT_Encode2(GICP_gi_vop3mods),
        GIM_CheckComplexPattern, /*MI*/2, /*Op*/2, /*Renderer*/GIMT_Encode2(2), GIMT_Encode2(GICP_gi_vop3mods),
        // (fmaxnum:{ *:[f32] } (fminnum:{ *:[f32] } (VOP3Mods:{ *:[f32] } f32:{ *:[f32] }:$src2, i32:{ *:[i32] }:$src2_mods), (fmaxnum:{ *:[f32] } (VOP3Mods:{ *:[f32] } f32:{ *:[f32] }:$src1, i32:{ *:[i32] }:$src1_mods), (VOP3Mods:{ *:[f32] } f32:{ *:[f32] }:$src0, i32:{ *:[i32] }:$src0_mods))), (fminnum_ieee:{ *:[f32] } (VOP3Mods:{ *:[f32] } f32:{ *:[f32] }:$src0, i32:{ *:[i32] }:$src0_mods), (VOP3Mods:{ *:[f32] } f32:{ *:[f32] }:$src1, i32:{ *:[i32] }:$src1_mods)))<<P:Predicate_fmaxnum_like_nnan>>  =>  (V_MED3_F32_e64:{ *:[f32] } ?:{ *:[i32] }:$src0_mods, ?:{ *:[f32] }:$src0, ?:{ *:[i32] }:$src1_mods, ?:{ *:[f32] }:$src1, ?:{ *:[i32] }:$src2_mods, ?:{ *:[f32] }:$src2, 0:{ *:[i1] }, 0:{ *:[i32] })
        GIR_BuildMI, /*InsnID*/0, /*Opcode*/GIMT_Encode2(AMDGPU::V_MED3_F32_e64),
        GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/0, // DstI[vdst]
        GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(2), /*SubOperand*/1, // src0_mods
        GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(2), /*SubOperand*/0, // src0
        GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(1), /*SubOperand*/1, // src1_mods
        GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(1), /*SubOperand*/0, // src1
        GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/1, // src2_mods
        GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/0, // src2
        GIR_AddImm8, /*InsnID*/0, /*Imm*/0,
        GIR_AddImm8, /*InsnID*/0, /*Imm*/0,
        GIR_ConstrainSelectedInstOperands, /*InsnID*/0,
        GIR_EraseFromParent, /*InsnID*/0,
        // GIR_Coverage, 10178,
        GIR_Done,
      // Label 4650: @313166
      GIM_Try, /*On fail goto*//*Label 4651*/ GIMT_Encode4(313306), // Rule ID 10179 //
        GIM_CheckRegBankForClass, /*MI*/0, /*Op*/0, /*RC*/GIMT_Encode2(AMDGPU::VGPR_32RegClassID),
        GIM_RecordInsn, /*DefineMI*/1, /*MI*/0, /*OpIdx*/1, // MIs[1]
        GIM_CheckOpcode, /*MI*/1, GIMT_Encode2(TargetOpcode::G_FMINNUM),
        GIM_CheckType, /*MI*/1, /*Op*/1, /*Type*/GILLT_s32,
        GIM_CheckType, /*MI*/1, /*Op*/2, /*Type*/GILLT_s32,
        GIM_RecordInsn, /*DefineMI*/2, /*MI*/1, /*OpIdx*/2, // MIs[2]
        GIM_CheckOpcode, /*MI*/2, GIMT_Encode2(TargetOpcode::G_FMAXNUM),
        GIM_CheckType, /*MI*/2, /*Op*/1, /*Type*/GILLT_s32,
        GIM_CheckType, /*MI*/2, /*Op*/2, /*Type*/GILLT_s32,
        GIM_RecordInsn, /*DefineMI*/3, /*MI*/0, /*OpIdx*/2, // MIs[3]
        GIM_CheckOpcode, /*MI*/3, GIMT_Encode2(TargetOpcode::G_FMINNUM_IEEE),
        // MIs[3] VOP3Mods:src1:src1_mods
        GIM_CheckIsSameOperand, /*MI*/3, /*OpIdx*/1, /*OtherMI*/2, /*OtherOpIdx*/1,
        // MIs[3] VOP3Mods:src0:src0_mods
        GIM_CheckIsSameOperand, /*MI*/3, /*OpIdx*/2, /*OtherMI*/2, /*OtherOpIdx*/2,
        GIM_CheckCxxInsnPredicate, /*MI*/0, /*FnId*/GIMT_Encode2(GICXXPred_MI_Predicate_fmaxnum_like_nnan),
        GIM_CheckIsSafeToFold, /*InsnID*/1,
        GIM_CheckIsSafeToFold, /*InsnID*/2,
        GIM_CheckIsSafeToFold, /*InsnID*/3,
        GIM_CheckComplexPattern, /*MI*/1, /*Op*/1, /*Renderer*/GIMT_Encode2(0), GIMT_Encode2(GICP_gi_vop3mods),
        GIM_CheckComplexPattern, /*MI*/2, /*Op*/1, /*Renderer*/GIMT_Encode2(1), GIMT_Encode2(GICP_gi_vop3mods),
        GIM_CheckComplexPattern, /*MI*/2, /*Op*/2, /*Renderer*/GIMT_Encode2(2), GIMT_Encode2(GICP_gi_vop3mods),
        // (fmaxnum:{ *:[f32] } (fminnum:{ *:[f32] } (VOP3Mods:{ *:[f32] } f32:{ *:[f32] }:$src2, i32:{ *:[i32] }:$src2_mods), (fmaxnum:{ *:[f32] } (VOP3Mods:{ *:[f32] } f32:{ *:[f32] }:$src1, i32:{ *:[i32] }:$src1_mods), (VOP3Mods:{ *:[f32] } f32:{ *:[f32] }:$src0, i32:{ *:[i32] }:$src0_mods))), (fminnum_ieee:{ *:[f32] } (VOP3Mods:{ *:[f32] } f32:{ *:[f32] }:$src1, i32:{ *:[i32] }:$src1_mods), (VOP3Mods:{ *:[f32] } f32:{ *:[f32] }:$src0, i32:{ *:[i32] }:$src0_mods)))<<P:Predicate_fmaxnum_like_nnan>>  =>  (V_MED3_F32_e64:{ *:[f32] } ?:{ *:[i32] }:$src0_mods, ?:{ *:[f32] }:$src0, ?:{ *:[i32] }:$src1_mods, ?:{ *:[f32] }:$src1, ?:{ *:[i32] }:$src2_mods, ?:{ *:[f32] }:$src2, 0:{ *:[i1] }, 0:{ *:[i32] })
        GIR_BuildMI, /*InsnID*/0, /*Opcode*/GIMT_Encode2(AMDGPU::V_MED3_F32_e64),
        GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/0, // DstI[vdst]
        GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(2), /*SubOperand*/1, // src0_mods
        GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(2), /*SubOperand*/0, // src0
        GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(1), /*SubOperand*/1, // src1_mods
        GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(1), /*SubOperand*/0, // src1
        GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/1, // src2_mods
        GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/0, // src2
        GIR_AddImm8, /*InsnID*/0, /*Imm*/0,
        GIR_AddImm8, /*InsnID*/0, /*Imm*/0,
        GIR_ConstrainSelectedInstOperands, /*InsnID*/0,
        GIR_EraseFromParent, /*InsnID*/0,
        // GIR_Coverage, 10179,
        GIR_Done,
      // Label 4651: @313306
      GIM_Try, /*On fail goto*//*Label 4652*/ GIMT_Encode4(313446), // Rule ID 10221 //
        GIM_CheckRegBankForClass, /*MI*/0, /*Op*/0, /*RC*/GIMT_Encode2(AMDGPU::VGPR_32RegClassID),
        GIM_RecordInsn, /*DefineMI*/1, /*MI*/0, /*OpIdx*/1, // MIs[1]
        GIM_CheckOpcode, /*MI*/1, GIMT_Encode2(TargetOpcode::G_FMINNUM),
        GIM_CheckType, /*MI*/1, /*Op*/1, /*Type*/GILLT_s32,
        GIM_CheckType, /*MI*/1, /*Op*/2, /*Type*/GILLT_s32,
        GIM_RecordInsn, /*DefineMI*/2, /*MI*/1, /*OpIdx*/2, // MIs[2]
        GIM_CheckOpcode, /*MI*/2, GIMT_Encode2(TargetOpcode::G_FMAXNUM_IEEE),
        GIM_CheckType, /*MI*/2, /*Op*/1, /*Type*/GILLT_s32,
        GIM_CheckType, /*MI*/2, /*Op*/2, /*Type*/GILLT_s32,
        GIM_RecordInsn, /*DefineMI*/3, /*MI*/0, /*OpIdx*/2, // MIs[3]
        GIM_CheckOpcode, /*MI*/3, GIMT_Encode2(TargetOpcode::G_FMINNUM),
        // MIs[3] VOP3Mods:src0:src0_mods
        GIM_CheckIsSameOperand, /*MI*/3, /*OpIdx*/1, /*OtherMI*/2, /*OtherOpIdx*/1,
        // MIs[3] VOP3Mods:src1:src1_mods
        GIM_CheckIsSameOperand, /*MI*/3, /*OpIdx*/2, /*OtherMI*/2, /*OtherOpIdx*/2,
        GIM_CheckCxxInsnPredicate, /*MI*/0, /*FnId*/GIMT_Encode2(GICXXPred_MI_Predicate_fmaxnum_like_nnan),
        GIM_CheckIsSafeToFold, /*InsnID*/1,
        GIM_CheckIsSafeToFold, /*InsnID*/2,
        GIM_CheckIsSafeToFold, /*InsnID*/3,
        GIM_CheckComplexPattern, /*MI*/1, /*Op*/1, /*Renderer*/GIMT_Encode2(0), GIMT_Encode2(GICP_gi_vop3mods),
        GIM_CheckComplexPattern, /*MI*/2, /*Op*/1, /*Renderer*/GIMT_Encode2(1), GIMT_Encode2(GICP_gi_vop3mods),
        GIM_CheckComplexPattern, /*MI*/2, /*Op*/2, /*Renderer*/GIMT_Encode2(2), GIMT_Encode2(GICP_gi_vop3mods),
        // (fmaxnum:{ *:[f32] } (fminnum:{ *:[f32] } (VOP3Mods:{ *:[f32] } f32:{ *:[f32] }:$src2, i32:{ *:[i32] }:$src2_mods), (fmaxnum_ieee:{ *:[f32] } (VOP3Mods:{ *:[f32] } f32:{ *:[f32] }:$src0, i32:{ *:[i32] }:$src0_mods), (VOP3Mods:{ *:[f32] } f32:{ *:[f32] }:$src1, i32:{ *:[i32] }:$src1_mods))), (fminnum:{ *:[f32] } (VOP3Mods:{ *:[f32] } f32:{ *:[f32] }:$src0, i32:{ *:[i32] }:$src0_mods), (VOP3Mods:{ *:[f32] } f32:{ *:[f32] }:$src1, i32:{ *:[i32] }:$src1_mods)))<<P:Predicate_fmaxnum_like_nnan>>  =>  (V_MED3_F32_e64:{ *:[f32] } ?:{ *:[i32] }:$src0_mods, ?:{ *:[f32] }:$src0, ?:{ *:[i32] }:$src1_mods, ?:{ *:[f32] }:$src1, ?:{ *:[i32] }:$src2_mods, ?:{ *:[f32] }:$src2, 0:{ *:[i1] }, 0:{ *:[i32] })
        GIR_BuildMI, /*InsnID*/0, /*Opcode*/GIMT_Encode2(AMDGPU::V_MED3_F32_e64),
        GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/0, // DstI[vdst]
        GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(1), /*SubOperand*/1, // src0_mods
        GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(1), /*SubOperand*/0, // src0
        GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(2), /*SubOperand*/1, // src1_mods
        GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(2), /*SubOperand*/0, // src1
        GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/1, // src2_mods
        GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/0, // src2
        GIR_AddImm8, /*InsnID*/0, /*Imm*/0,
        GIR_AddImm8, /*InsnID*/0, /*Imm*/0,
        GIR_ConstrainSelectedInstOperands, /*InsnID*/0,
        GIR_EraseFromParent, /*InsnID*/0,
        // GIR_Coverage, 10221,
        GIR_Done,
      // Label 4652: @313446
      GIM_Try, /*On fail goto*//*Label 4653*/ GIMT_Encode4(313586), // Rule ID 10222 //
        GIM_CheckRegBankForClass, /*MI*/0, /*Op*/0, /*RC*/GIMT_Encode2(AMDGPU::VGPR_32RegClassID),
        GIM_RecordInsn, /*DefineMI*/1, /*MI*/0, /*OpIdx*/1, // MIs[1]
        GIM_CheckOpcode, /*MI*/1, GIMT_Encode2(TargetOpcode::G_FMINNUM),
        GIM_CheckType, /*MI*/1, /*Op*/1, /*Type*/GILLT_s32,
        GIM_CheckType, /*MI*/1, /*Op*/2, /*Type*/GILLT_s32,
        GIM_RecordInsn, /*DefineMI*/2, /*MI*/1, /*OpIdx*/2, // MIs[2]
        GIM_CheckOpcode, /*MI*/2, GIMT_Encode2(TargetOpcode::G_FMAXNUM_IEEE),
        GIM_CheckType, /*MI*/2, /*Op*/1, /*Type*/GILLT_s32,
        GIM_CheckType, /*MI*/2, /*Op*/2, /*Type*/GILLT_s32,
        GIM_RecordInsn, /*DefineMI*/3, /*MI*/0, /*OpIdx*/2, // MIs[3]
        GIM_CheckOpcode, /*MI*/3, GIMT_Encode2(TargetOpcode::G_FMINNUM),
        // MIs[3] VOP3Mods:src1:src1_mods
        GIM_CheckIsSameOperand, /*MI*/3, /*OpIdx*/1, /*OtherMI*/2, /*OtherOpIdx*/2,
        // MIs[3] VOP3Mods:src0:src0_mods
        GIM_CheckIsSameOperand, /*MI*/3, /*OpIdx*/2, /*OtherMI*/2, /*OtherOpIdx*/1,
        GIM_CheckCxxInsnPredicate, /*MI*/0, /*FnId*/GIMT_Encode2(GICXXPred_MI_Predicate_fmaxnum_like_nnan),
        GIM_CheckIsSafeToFold, /*InsnID*/1,
        GIM_CheckIsSafeToFold, /*InsnID*/2,
        GIM_CheckIsSafeToFold, /*InsnID*/3,
        GIM_CheckComplexPattern, /*MI*/1, /*Op*/1, /*Renderer*/GIMT_Encode2(0), GIMT_Encode2(GICP_gi_vop3mods),
        GIM_CheckComplexPattern, /*MI*/2, /*Op*/1, /*Renderer*/GIMT_Encode2(1), GIMT_Encode2(GICP_gi_vop3mods),
        GIM_CheckComplexPattern, /*MI*/2, /*Op*/2, /*Renderer*/GIMT_Encode2(2), GIMT_Encode2(GICP_gi_vop3mods),
        // (fmaxnum:{ *:[f32] } (fminnum:{ *:[f32] } (VOP3Mods:{ *:[f32] } f32:{ *:[f32] }:$src2, i32:{ *:[i32] }:$src2_mods), (fmaxnum_ieee:{ *:[f32] } (VOP3Mods:{ *:[f32] } f32:{ *:[f32] }:$src0, i32:{ *:[i32] }:$src0_mods), (VOP3Mods:{ *:[f32] } f32:{ *:[f32] }:$src1, i32:{ *:[i32] }:$src1_mods))), (fminnum:{ *:[f32] } (VOP3Mods:{ *:[f32] } f32:{ *:[f32] }:$src1, i32:{ *:[i32] }:$src1_mods), (VOP3Mods:{ *:[f32] } f32:{ *:[f32] }:$src0, i32:{ *:[i32] }:$src0_mods)))<<P:Predicate_fmaxnum_like_nnan>>  =>  (V_MED3_F32_e64:{ *:[f32] } ?:{ *:[i32] }:$src0_mods, ?:{ *:[f32] }:$src0, ?:{ *:[i32] }:$src1_mods, ?:{ *:[f32] }:$src1, ?:{ *:[i32] }:$src2_mods, ?:{ *:[f32] }:$src2, 0:{ *:[i1] }, 0:{ *:[i32] })
        GIR_BuildMI, /*InsnID*/0, /*Opcode*/GIMT_Encode2(AMDGPU::V_MED3_F32_e64),
        GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/0, // DstI[vdst]
        GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(1), /*SubOperand*/1, // src0_mods
        GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(1), /*SubOperand*/0, // src0
        GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(2), /*SubOperand*/1, // src1_mods
        GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(2), /*SubOperand*/0, // src1
        GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/1, // src2_mods
        GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/0, // src2
        GIR_AddImm8, /*InsnID*/0, /*Imm*/0,
        GIR_AddImm8, /*InsnID*/0, /*Imm*/0,
        GIR_ConstrainSelectedInstOperands, /*InsnID*/0,
        GIR_EraseFromParent, /*InsnID*/0,
        // GIR_Coverage, 10222,
        GIR_Done,
      // Label 4653: @313586
      GIM_Try, /*On fail goto*//*Label 4654*/ GIMT_Encode4(313726), // Rule ID 10223 //
        GIM_CheckRegBankForClass, /*MI*/0, /*Op*/0, /*RC*/GIMT_Encode2(AMDGPU::VGPR_32RegClassID),
        GIM_RecordInsn, /*DefineMI*/1, /*MI*/0, /*OpIdx*/1, // MIs[1]
        GIM_CheckOpcode, /*MI*/1, GIMT_Encode2(TargetOpcode::G_FMINNUM),
        GIM_CheckType, /*MI*/1, /*Op*/1, /*Type*/GILLT_s32,
        GIM_CheckType, /*MI*/1, /*Op*/2, /*Type*/GILLT_s32,
        GIM_RecordInsn, /*DefineMI*/2, /*MI*/1, /*OpIdx*/2, // MIs[2]
        GIM_CheckOpcode, /*MI*/2, GIMT_Encode2(TargetOpcode::G_FMAXNUM_IEEE),
        GIM_CheckType, /*MI*/2, /*Op*/1, /*Type*/GILLT_s32,
        GIM_CheckType, /*MI*/2, /*Op*/2, /*Type*/GILLT_s32,
        GIM_RecordInsn, /*DefineMI*/3, /*MI*/0, /*OpIdx*/2, // MIs[3]
        GIM_CheckOpcode, /*MI*/3, GIMT_Encode2(TargetOpcode::G_FMINNUM),
        // MIs[3] VOP3Mods:src0:src0_mods
        GIM_CheckIsSameOperand, /*MI*/3, /*OpIdx*/1, /*OtherMI*/2, /*OtherOpIdx*/2,
        // MIs[3] VOP3Mods:src1:src1_mods
        GIM_CheckIsSameOperand, /*MI*/3, /*OpIdx*/2, /*OtherMI*/2, /*OtherOpIdx*/1,
        GIM_CheckCxxInsnPredicate, /*MI*/0, /*FnId*/GIMT_Encode2(GICXXPred_MI_Predicate_fmaxnum_like_nnan),
        GIM_CheckIsSafeToFold, /*InsnID*/1,
        GIM_CheckIsSafeToFold, /*InsnID*/2,
        GIM_CheckIsSafeToFold, /*InsnID*/3,
        GIM_CheckComplexPattern, /*MI*/1, /*Op*/1, /*Renderer*/GIMT_Encode2(0), GIMT_Encode2(GICP_gi_vop3mods),
        GIM_CheckComplexPattern, /*MI*/2, /*Op*/1, /*Renderer*/GIMT_Encode2(1), GIMT_Encode2(GICP_gi_vop3mods),
        GIM_CheckComplexPattern, /*MI*/2, /*Op*/2, /*Renderer*/GIMT_Encode2(2), GIMT_Encode2(GICP_gi_vop3mods),
        // (fmaxnum:{ *:[f32] } (fminnum:{ *:[f32] } (VOP3Mods:{ *:[f32] } f32:{ *:[f32] }:$src2, i32:{ *:[i32] }:$src2_mods), (fmaxnum_ieee:{ *:[f32] } (VOP3Mods:{ *:[f32] } f32:{ *:[f32] }:$src1, i32:{ *:[i32] }:$src1_mods), (VOP3Mods:{ *:[f32] } f32:{ *:[f32] }:$src0, i32:{ *:[i32] }:$src0_mods))), (fminnum:{ *:[f32] } (VOP3Mods:{ *:[f32] } f32:{ *:[f32] }:$src0, i32:{ *:[i32] }:$src0_mods), (VOP3Mods:{ *:[f32] } f32:{ *:[f32] }:$src1, i32:{ *:[i32] }:$src1_mods)))<<P:Predicate_fmaxnum_like_nnan>>  =>  (V_MED3_F32_e64:{ *:[f32] } ?:{ *:[i32] }:$src0_mods, ?:{ *:[f32] }:$src0, ?:{ *:[i32] }:$src1_mods, ?:{ *:[f32] }:$src1, ?:{ *:[i32] }:$src2_mods, ?:{ *:[f32] }:$src2, 0:{ *:[i1] }, 0:{ *:[i32] })
        GIR_BuildMI, /*InsnID*/0, /*Opcode*/GIMT_Encode2(AMDGPU::V_MED3_F32_e64),
        GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/0, // DstI[vdst]
        GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(2), /*SubOperand*/1, // src0_mods
        GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(2), /*SubOperand*/0, // src0
        GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(1), /*SubOperand*/1, // src1_mods
        GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(1), /*SubOperand*/0, // src1
        GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/1, // src2_mods
        GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/0, // src2
        GIR_AddImm8, /*InsnID*/0, /*Imm*/0,
        GIR_AddImm8, /*InsnID*/0, /*Imm*/0,
        GIR_ConstrainSelectedInstOperands, /*InsnID*/0,
        GIR_EraseFromParent, /*InsnID*/0,
        // GIR_Coverage, 10223,
        GIR_Done,
      // Label 4654: @313726
      GIM_Try, /*On fail goto*//*Label 4655*/ GIMT_Encode4(313866), // Rule ID 10224 //
        GIM_CheckRegBankForClass, /*MI*/0, /*Op*/0, /*RC*/GIMT_Encode2(AMDGPU::VGPR_32RegClassID),
        GIM_RecordInsn, /*DefineMI*/1, /*MI*/0, /*OpIdx*/1, // MIs[1]
        GIM_CheckOpcode, /*MI*/1, GIMT_Encode2(TargetOpcode::G_FMINNUM),
        GIM_CheckType, /*MI*/1, /*Op*/1, /*Type*/GILLT_s32,
        GIM_CheckType, /*MI*/1, /*Op*/2, /*Type*/GILLT_s32,
        GIM_RecordInsn, /*DefineMI*/2, /*MI*/1, /*OpIdx*/2, // MIs[2]
        GIM_CheckOpcode, /*MI*/2, GIMT_Encode2(TargetOpcode::G_FMAXNUM_IEEE),
        GIM_CheckType, /*MI*/2, /*Op*/1, /*Type*/GILLT_s32,
        GIM_CheckType, /*MI*/2, /*Op*/2, /*Type*/GILLT_s32,
        GIM_RecordInsn, /*DefineMI*/3, /*MI*/0, /*OpIdx*/2, // MIs[3]
        GIM_CheckOpcode, /*MI*/3, GIMT_Encode2(TargetOpcode::G_FMINNUM),
        // MIs[3] VOP3Mods:src1:src1_mods
        GIM_CheckIsSameOperand, /*MI*/3, /*OpIdx*/1, /*OtherMI*/2, /*OtherOpIdx*/1,
        // MIs[3] VOP3Mods:src0:src0_mods
        GIM_CheckIsSameOperand, /*MI*/3, /*OpIdx*/2, /*OtherMI*/2, /*OtherOpIdx*/2,
        GIM_CheckCxxInsnPredicate, /*MI*/0, /*FnId*/GIMT_Encode2(GICXXPred_MI_Predicate_fmaxnum_like_nnan),
        GIM_CheckIsSafeToFold, /*InsnID*/1,
        GIM_CheckIsSafeToFold, /*InsnID*/2,
        GIM_CheckIsSafeToFold, /*InsnID*/3,
        GIM_CheckComplexPattern, /*MI*/1, /*Op*/1, /*Renderer*/GIMT_Encode2(0), GIMT_Encode2(GICP_gi_vop3mods),
        GIM_CheckComplexPattern, /*MI*/2, /*Op*/1, /*Renderer*/GIMT_Encode2(1), GIMT_Encode2(GICP_gi_vop3mods),
        GIM_CheckComplexPattern, /*MI*/2, /*Op*/2, /*Renderer*/GIMT_Encode2(2), GIMT_Encode2(GICP_gi_vop3mods),
        // (fmaxnum:{ *:[f32] } (fminnum:{ *:[f32] } (VOP3Mods:{ *:[f32] } f32:{ *:[f32] }:$src2, i32:{ *:[i32] }:$src2_mods), (fmaxnum_ieee:{ *:[f32] } (VOP3Mods:{ *:[f32] } f32:{ *:[f32] }:$src1, i32:{ *:[i32] }:$src1_mods), (VOP3Mods:{ *:[f32] } f32:{ *:[f32] }:$src0, i32:{ *:[i32] }:$src0_mods))), (fminnum:{ *:[f32] } (VOP3Mods:{ *:[f32] } f32:{ *:[f32] }:$src1, i32:{ *:[i32] }:$src1_mods), (VOP3Mods:{ *:[f32] } f32:{ *:[f32] }:$src0, i32:{ *:[i32] }:$src0_mods)))<<P:Predicate_fmaxnum_like_nnan>>  =>  (V_MED3_F32_e64:{ *:[f32] } ?:{ *:[i32] }:$src0_mods, ?:{ *:[f32] }:$src0, ?:{ *:[i32] }:$src1_mods, ?:{ *:[f32] }:$src1, ?:{ *:[i32] }:$src2_mods, ?:{ *:[f32] }:$src2, 0:{ *:[i1] }, 0:{ *:[i32] })
        GIR_BuildMI, /*InsnID*/0, /*Opcode*/GIMT_Encode2(AMDGPU::V_MED3_F32_e64),
        GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/0, // DstI[vdst]
        GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(2), /*SubOperand*/1, // src0_mods
        GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(2), /*SubOperand*/0, // src0
        GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(1), /*SubOperand*/1, // src1_mods
        GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(1), /*SubOperand*/0, // src1
        GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/1, // src2_mods
        GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/0, // src2
        GIR_AddImm8, /*InsnID*/0, /*Imm*/0,
        GIR_AddImm8, /*InsnID*/0, /*Imm*/0,
        GIR_ConstrainSelectedInstOperands, /*InsnID*/0,
        GIR_EraseFromParent, /*InsnID*/0,
        // GIR_Coverage, 10224,
        GIR_Done,
      // Label 4655: @313866
      GIM_Try, /*On fail goto*//*Label 4656*/ GIMT_Encode4(314006), // Rule ID 10161 //
        GIM_CheckRegBankForClass, /*MI*/0, /*Op*/0, /*RC*/GIMT_Encode2(AMDGPU::VGPR_32RegClassID),
        GIM_RecordInsn, /*DefineMI*/1, /*MI*/0, /*OpIdx*/1, // MIs[1]
        GIM_CheckOpcode, /*MI*/1, GIMT_Encode2(TargetOpcode::G_FMINNUM),
        GIM_CheckType, /*MI*/1, /*Op*/1, /*Type*/GILLT_s32,
        GIM_CheckType, /*MI*/1, /*Op*/2, /*Type*/GILLT_s32,
        GIM_RecordInsn, /*DefineMI*/2, /*MI*/1, /*OpIdx*/2, // MIs[2]
        GIM_CheckOpcode, /*MI*/2, GIMT_Encode2(TargetOpcode::G_FMAXNUM_IEEE),
        GIM_CheckType, /*MI*/2, /*Op*/1, /*Type*/GILLT_s32,
        GIM_CheckType, /*MI*/2, /*Op*/2, /*Type*/GILLT_s32,
        GIM_RecordInsn, /*DefineMI*/3, /*MI*/0, /*OpIdx*/2, // MIs[3]
        GIM_CheckOpcode, /*MI*/3, GIMT_Encode2(TargetOpcode::G_FMINNUM_IEEE),
        // MIs[3] VOP3Mods:src0:src0_mods
        GIM_CheckIsSameOperand, /*MI*/3, /*OpIdx*/1, /*OtherMI*/2, /*OtherOpIdx*/1,
        // MIs[3] VOP3Mods:src1:src1_mods
        GIM_CheckIsSameOperand, /*MI*/3, /*OpIdx*/2, /*OtherMI*/2, /*OtherOpIdx*/2,
        GIM_CheckCxxInsnPredicate, /*MI*/0, /*FnId*/GIMT_Encode2(GICXXPred_MI_Predicate_fmaxnum_like_nnan),
        GIM_CheckIsSafeToFold, /*InsnID*/1,
        GIM_CheckIsSafeToFold, /*InsnID*/2,
        GIM_CheckIsSafeToFold, /*InsnID*/3,
        GIM_CheckComplexPattern, /*MI*/1, /*Op*/1, /*Renderer*/GIMT_Encode2(0), GIMT_Encode2(GICP_gi_vop3mods),
        GIM_CheckComplexPattern, /*MI*/2, /*Op*/1, /*Renderer*/GIMT_Encode2(1), GIMT_Encode2(GICP_gi_vop3mods),
        GIM_CheckComplexPattern, /*MI*/2, /*Op*/2, /*Renderer*/GIMT_Encode2(2), GIMT_Encode2(GICP_gi_vop3mods),
        // (fmaxnum:{ *:[f32] } (fminnum:{ *:[f32] } (VOP3Mods:{ *:[f32] } f32:{ *:[f32] }:$src2, i32:{ *:[i32] }:$src2_mods), (fmaxnum_ieee:{ *:[f32] } (VOP3Mods:{ *:[f32] } f32:{ *:[f32] }:$src0, i32:{ *:[i32] }:$src0_mods), (VOP3Mods:{ *:[f32] } f32:{ *:[f32] }:$src1, i32:{ *:[i32] }:$src1_mods))), (fminnum_ieee:{ *:[f32] } (VOP3Mods:{ *:[f32] } f32:{ *:[f32] }:$src0, i32:{ *:[i32] }:$src0_mods), (VOP3Mods:{ *:[f32] } f32:{ *:[f32] }:$src1, i32:{ *:[i32] }:$src1_mods)))<<P:Predicate_fmaxnum_like_nnan>>  =>  (V_MED3_F32_e64:{ *:[f32] } ?:{ *:[i32] }:$src0_mods, ?:{ *:[f32] }:$src0, ?:{ *:[i32] }:$src1_mods, ?:{ *:[f32] }:$src1, ?:{ *:[i32] }:$src2_mods, ?:{ *:[f32] }:$src2, 0:{ *:[i1] }, 0:{ *:[i32] })
        GIR_BuildMI, /*InsnID*/0, /*Opcode*/GIMT_Encode2(AMDGPU::V_MED3_F32_e64),
        GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/0, // DstI[vdst]
        GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(1), /*SubOperand*/1, // src0_mods
        GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(1), /*SubOperand*/0, // src0
        GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(2), /*SubOperand*/1, // src1_mods
        GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(2), /*SubOperand*/0, // src1
        GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/1, // src2_mods
        GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/0, // src2
        GIR_AddImm8, /*InsnID*/0, /*Imm*/0,
        GIR_AddImm8, /*InsnID*/0, /*Imm*/0,
        GIR_ConstrainSelectedInstOperands, /*InsnID*/0,
        GIR_EraseFromParent, /*InsnID*/0,
        // GIR_Coverage, 10161,
        GIR_Done,
      // Label 4656: @314006
      GIM_Try, /*On fail goto*//*Label 4657*/ GIMT_Encode4(314146), // Rule ID 10162 //
        GIM_CheckRegBankForClass, /*MI*/0, /*Op*/0, /*RC*/GIMT_Encode2(AMDGPU::VGPR_32RegClassID),
        GIM_RecordInsn, /*DefineMI*/1, /*MI*/0, /*OpIdx*/1, // MIs[1]
        GIM_CheckOpcode, /*MI*/1, GIMT_Encode2(TargetOpcode::G_FMINNUM),
        GIM_CheckType, /*MI*/1, /*Op*/1, /*Type*/GILLT_s32,
        GIM_CheckType, /*MI*/1, /*Op*/2, /*Type*/GILLT_s32,
        GIM_RecordInsn, /*DefineMI*/2, /*MI*/1, /*OpIdx*/2, // MIs[2]
        GIM_CheckOpcode, /*MI*/2, GIMT_Encode2(TargetOpcode::G_FMAXNUM_IEEE),
        GIM_CheckType, /*MI*/2, /*Op*/1, /*Type*/GILLT_s32,
        GIM_CheckType, /*MI*/2, /*Op*/2, /*Type*/GILLT_s32,
        GIM_RecordInsn, /*DefineMI*/3, /*MI*/0, /*OpIdx*/2, // MIs[3]
        GIM_CheckOpcode, /*MI*/3, GIMT_Encode2(TargetOpcode::G_FMINNUM_IEEE),
        // MIs[3] VOP3Mods:src1:src1_mods
        GIM_CheckIsSameOperand, /*MI*/3, /*OpIdx*/1, /*OtherMI*/2, /*OtherOpIdx*/2,
        // MIs[3] VOP3Mods:src0:src0_mods
        GIM_CheckIsSameOperand, /*MI*/3, /*OpIdx*/2, /*OtherMI*/2, /*OtherOpIdx*/1,
        GIM_CheckCxxInsnPredicate, /*MI*/0, /*FnId*/GIMT_Encode2(GICXXPred_MI_Predicate_fmaxnum_like_nnan),
        GIM_CheckIsSafeToFold, /*InsnID*/1,
        GIM_CheckIsSafeToFold, /*InsnID*/2,
        GIM_CheckIsSafeToFold, /*InsnID*/3,
        GIM_CheckComplexPattern, /*MI*/1, /*Op*/1, /*Renderer*/GIMT_Encode2(0), GIMT_Encode2(GICP_gi_vop3mods),
        GIM_CheckComplexPattern, /*MI*/2, /*Op*/1, /*Renderer*/GIMT_Encode2(1), GIMT_Encode2(GICP_gi_vop3mods),
        GIM_CheckComplexPattern, /*MI*/2, /*Op*/2, /*Renderer*/GIMT_Encode2(2), GIMT_Encode2(GICP_gi_vop3mods),
        // (fmaxnum:{ *:[f32] } (fminnum:{ *:[f32] } (VOP3Mods:{ *:[f32] } f32:{ *:[f32] }:$src2, i32:{ *:[i32] }:$src2_mods), (fmaxnum_ieee:{ *:[f32] } (VOP3Mods:{ *:[f32] } f32:{ *:[f32] }:$src0, i32:{ *:[i32] }:$src0_mods), (VOP3Mods:{ *:[f32] } f32:{ *:[f32] }:$src1, i32:{ *:[i32] }:$src1_mods))), (fminnum_ieee:{ *:[f32] } (VOP3Mods:{ *:[f32] } f32:{ *:[f32] }:$src1, i32:{ *:[i32] }:$src1_mods), (VOP3Mods:{ *:[f32] } f32:{ *:[f32] }:$src0, i32:{ *:[i32] }:$src0_mods)))<<P:Predicate_fmaxnum_like_nnan>>  =>  (V_MED3_F32_e64:{ *:[f32] } ?:{ *:[i32] }:$src0_mods, ?:{ *:[f32] }:$src0, ?:{ *:[i32] }:$src1_mods, ?:{ *:[f32] }:$src1, ?:{ *:[i32] }:$src2_mods, ?:{ *:[f32] }:$src2, 0:{ *:[i1] }, 0:{ *:[i32] })
        GIR_BuildMI, /*InsnID*/0, /*Opcode*/GIMT_Encode2(AMDGPU::V_MED3_F32_e64),
        GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/0, // DstI[vdst]
        GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(1), /*SubOperand*/1, // src0_mods
        GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(1), /*SubOperand*/0, // src0
        GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(2), /*SubOperand*/1, // src1_mods
        GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(2), /*SubOperand*/0, // src1
        GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/1, // src2_mods
        GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/0, // src2
        GIR_AddImm8, /*InsnID*/0, /*Imm*/0,
        GIR_AddImm8, /*InsnID*/0, /*Imm*/0,
        GIR_ConstrainSelectedInstOperands, /*InsnID*/0,
        GIR_EraseFromParent, /*InsnID*/0,
        // GIR_Coverage, 10162,
        GIR_Done,
      // Label 4657: @314146
      GIM_Try, /*On fail goto*//*Label 4658*/ GIMT_Encode4(314286), // Rule ID 10163 //
        GIM_CheckRegBankForClass, /*MI*/0, /*Op*/0, /*RC*/GIMT_Encode2(AMDGPU::VGPR_32RegClassID),
        GIM_RecordInsn, /*DefineMI*/1, /*MI*/0, /*OpIdx*/1, // MIs[1]
        GIM_CheckOpcode, /*MI*/1, GIMT_Encode2(TargetOpcode::G_FMINNUM),
        GIM_CheckType, /*MI*/1, /*Op*/1, /*Type*/GILLT_s32,
        GIM_CheckType, /*MI*/1, /*Op*/2, /*Type*/GILLT_s32,
        GIM_RecordInsn, /*DefineMI*/2, /*MI*/1, /*OpIdx*/2, // MIs[2]
        GIM_CheckOpcode, /*MI*/2, GIMT_Encode2(TargetOpcode::G_FMAXNUM_IEEE),
        GIM_CheckType, /*MI*/2, /*Op*/1, /*Type*/GILLT_s32,
        GIM_CheckType, /*MI*/2, /*Op*/2, /*Type*/GILLT_s32,
        GIM_RecordInsn, /*DefineMI*/3, /*MI*/0, /*OpIdx*/2, // MIs[3]
        GIM_CheckOpcode, /*MI*/3, GIMT_Encode2(TargetOpcode::G_FMINNUM_IEEE),
        // MIs[3] VOP3Mods:src0:src0_mods
        GIM_CheckIsSameOperand, /*MI*/3, /*OpIdx*/1, /*OtherMI*/2, /*OtherOpIdx*/2,
        // MIs[3] VOP3Mods:src1:src1_mods
        GIM_CheckIsSameOperand, /*MI*/3, /*OpIdx*/2, /*OtherMI*/2, /*OtherOpIdx*/1,
        GIM_CheckCxxInsnPredicate, /*MI*/0, /*FnId*/GIMT_Encode2(GICXXPred_MI_Predicate_fmaxnum_like_nnan),
        GIM_CheckIsSafeToFold, /*InsnID*/1,
        GIM_CheckIsSafeToFold, /*InsnID*/2,
        GIM_CheckIsSafeToFold, /*InsnID*/3,
        GIM_CheckComplexPattern, /*MI*/1, /*Op*/1, /*Renderer*/GIMT_Encode2(0), GIMT_Encode2(GICP_gi_vop3mods),
        GIM_CheckComplexPattern, /*MI*/2, /*Op*/1, /*Renderer*/GIMT_Encode2(1), GIMT_Encode2(GICP_gi_vop3mods),
        GIM_CheckComplexPattern, /*MI*/2, /*Op*/2, /*Renderer*/GIMT_Encode2(2), GIMT_Encode2(GICP_gi_vop3mods),
        // (fmaxnum:{ *:[f32] } (fminnum:{ *:[f32] } (VOP3Mods:{ *:[f32] } f32:{ *:[f32] }:$src2, i32:{ *:[i32] }:$src2_mods), (fmaxnum_ieee:{ *:[f32] } (VOP3Mods:{ *:[f32] } f32:{ *:[f32] }:$src1, i32:{ *:[i32] }:$src1_mods), (VOP3Mods:{ *:[f32] } f32:{ *:[f32] }:$src0, i32:{ *:[i32] }:$src0_mods))), (fminnum_ieee:{ *:[f32] } (VOP3Mods:{ *:[f32] } f32:{ *:[f32] }:$src0, i32:{ *:[i32] }:$src0_mods), (VOP3Mods:{ *:[f32] } f32:{ *:[f32] }:$src1, i32:{ *:[i32] }:$src1_mods)))<<P:Predicate_fmaxnum_like_nnan>>  =>  (V_MED3_F32_e64:{ *:[f32] } ?:{ *:[i32] }:$src0_mods, ?:{ *:[f32] }:$src0, ?:{ *:[i32] }:$src1_mods, ?:{ *:[f32] }:$src1, ?:{ *:[i32] }:$src2_mods, ?:{ *:[f32] }:$src2, 0:{ *:[i1] }, 0:{ *:[i32] })
        GIR_BuildMI, /*InsnID*/0, /*Opcode*/GIMT_Encode2(AMDGPU::V_MED3_F32_e64),
        GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/0, // DstI[vdst]
        GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(2), /*SubOperand*/1, // src0_mods
        GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(2), /*SubOperand*/0, // src0
        GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(1), /*SubOperand*/1, // src1_mods
        GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(1), /*SubOperand*/0, // src1
        GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/1, // src2_mods
        GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/0, // src2
        GIR_AddImm8, /*InsnID*/0, /*Imm*/0,
        GIR_AddImm8, /*InsnID*/0, /*Imm*/0,
        GIR_ConstrainSelectedInstOperands, /*InsnID*/0,
        GIR_EraseFromParent, /*InsnID*/0,
        // GIR_Coverage, 10163,
        GIR_Done,
      // Label 4658: @314286
      GIM_Try, /*On fail goto*//*Label 4659*/ GIMT_Encode4(314426), // Rule ID 10164 //
        GIM_CheckRegBankForClass, /*MI*/0, /*Op*/0, /*RC*/GIMT_Encode2(AMDGPU::VGPR_32RegClassID),
        GIM_RecordInsn, /*DefineMI*/1, /*MI*/0, /*OpIdx*/1, // MIs[1]
        GIM_CheckOpcode, /*MI*/1, GIMT_Encode2(TargetOpcode::G_FMINNUM),
        GIM_CheckType, /*MI*/1, /*Op*/1, /*Type*/GILLT_s32,
        GIM_CheckType, /*MI*/1, /*Op*/2, /*Type*/GILLT_s32,
        GIM_RecordInsn, /*DefineMI*/2, /*MI*/1, /*OpIdx*/2, // MIs[2]
        GIM_CheckOpcode, /*MI*/2, GIMT_Encode2(TargetOpcode::G_FMAXNUM_IEEE),
        GIM_CheckType, /*MI*/2, /*Op*/1, /*Type*/GILLT_s32,
        GIM_CheckType, /*MI*/2, /*Op*/2, /*Type*/GILLT_s32,
        GIM_RecordInsn, /*DefineMI*/3, /*MI*/0, /*OpIdx*/2, // MIs[3]
        GIM_CheckOpcode, /*MI*/3, GIMT_Encode2(TargetOpcode::G_FMINNUM_IEEE),
        // MIs[3] VOP3Mods:src1:src1_mods
        GIM_CheckIsSameOperand, /*MI*/3, /*OpIdx*/1, /*OtherMI*/2, /*OtherOpIdx*/1,
        // MIs[3] VOP3Mods:src0:src0_mods
        GIM_CheckIsSameOperand, /*MI*/3, /*OpIdx*/2, /*OtherMI*/2, /*OtherOpIdx*/2,
        GIM_CheckCxxInsnPredicate, /*MI*/0, /*FnId*/GIMT_Encode2(GICXXPred_MI_Predicate_fmaxnum_like_nnan),
        GIM_CheckIsSafeToFold, /*InsnID*/1,
        GIM_CheckIsSafeToFold, /*InsnID*/2,
        GIM_CheckIsSafeToFold, /*InsnID*/3,
        GIM_CheckComplexPattern, /*MI*/1, /*Op*/1, /*Renderer*/GIMT_Encode2(0), GIMT_Encode2(GICP_gi_vop3mods),
        GIM_CheckComplexPattern, /*MI*/2, /*Op*/1, /*Renderer*/GIMT_Encode2(1), GIMT_Encode2(GICP_gi_vop3mods),
        GIM_CheckComplexPattern, /*MI*/2, /*Op*/2, /*Renderer*/GIMT_Encode2(2), GIMT_Encode2(GICP_gi_vop3mods),
        // (fmaxnum:{ *:[f32] } (fminnum:{ *:[f32] } (VOP3Mods:{ *:[f32] } f32:{ *:[f32] }:$src2, i32:{ *:[i32] }:$src2_mods), (fmaxnum_ieee:{ *:[f32] } (VOP3Mods:{ *:[f32] } f32:{ *:[f32] }:$src1, i32:{ *:[i32] }:$src1_mods), (VOP3Mods:{ *:[f32] } f32:{ *:[f32] }:$src0, i32:{ *:[i32] }:$src0_mods))), (fminnum_ieee:{ *:[f32] } (VOP3Mods:{ *:[f32] } f32:{ *:[f32] }:$src1, i32:{ *:[i32] }:$src1_mods), (VOP3Mods:{ *:[f32] } f32:{ *:[f32] }:$src0, i32:{ *:[i32] }:$src0_mods)))<<P:Predicate_fmaxnum_like_nnan>>  =>  (V_MED3_F32_e64:{ *:[f32] } ?:{ *:[i32] }:$src0_mods, ?:{ *:[f32] }:$src0, ?:{ *:[i32] }:$src1_mods, ?:{ *:[f32] }:$src1, ?:{ *:[i32] }:$src2_mods, ?:{ *:[f32] }:$src2, 0:{ *:[i1] }, 0:{ *:[i32] })
        GIR_BuildMI, /*InsnID*/0, /*Opcode*/GIMT_Encode2(AMDGPU::V_MED3_F32_e64),
        GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/0, // DstI[vdst]
        GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(2), /*SubOperand*/1, // src0_mods
        GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(2), /*SubOperand*/0, // src0
        GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(1), /*SubOperand*/1, // src1_mods
        GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(1), /*SubOperand*/0, // src1
        GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/1, // src2_mods
        GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/0, // src2
        GIR_AddImm8, /*InsnID*/0, /*Imm*/0,
        GIR_AddImm8, /*InsnID*/0, /*Imm*/0,
        GIR_ConstrainSelectedInstOperands, /*InsnID*/0,
        GIR_EraseFromParent, /*InsnID*/0,
        // GIR_Coverage, 10164,
        GIR_Done,
      // Label 4659: @314426
      GIM_Try, /*On fail goto*//*Label 4660*/ GIMT_Encode4(314566), // Rule ID 10232 //
        GIM_CheckRegBankForClass, /*MI*/0, /*Op*/0, /*RC*/GIMT_Encode2(AMDGPU::VGPR_32RegClassID),
        GIM_RecordInsn, /*DefineMI*/1, /*MI*/0, /*OpIdx*/1, // MIs[1]
        GIM_CheckOpcode, /*MI*/1, GIMT_Encode2(TargetOpcode::G_FMINNUM),
        GIM_CheckType, /*MI*/1, /*Op*/1, /*Type*/GILLT_s32,
        GIM_CheckType, /*MI*/1, /*Op*/2, /*Type*/GILLT_s32,
        GIM_RecordInsn, /*DefineMI*/2, /*MI*/1, /*OpIdx*/1, // MIs[2]
        GIM_CheckOpcode, /*MI*/2, GIMT_Encode2(TargetOpcode::G_FMAXNUM),
        GIM_CheckType, /*MI*/2, /*Op*/1, /*Type*/GILLT_s32,
        GIM_CheckType, /*MI*/2, /*Op*/2, /*Type*/GILLT_s32,
        GIM_RecordInsn, /*DefineMI*/3, /*MI*/0, /*OpIdx*/2, // MIs[3]
        GIM_CheckOpcode, /*MI*/3, GIMT_Encode2(TargetOpcode::G_FMINNUM),
        // MIs[3] VOP3Mods:src0:src0_mods
        GIM_CheckIsSameOperand, /*MI*/3, /*OpIdx*/1, /*OtherMI*/2, /*OtherOpIdx*/1,
        // MIs[3] VOP3Mods:src1:src1_mods
        GIM_CheckIsSameOperand, /*MI*/3, /*OpIdx*/2, /*OtherMI*/2, /*OtherOpIdx*/2,
        GIM_CheckCxxInsnPredicate, /*MI*/0, /*FnId*/GIMT_Encode2(GICXXPred_MI_Predicate_fmaxnum_like_nnan),
        GIM_CheckIsSafeToFold, /*InsnID*/1,
        GIM_CheckIsSafeToFold, /*InsnID*/2,
        GIM_CheckIsSafeToFold, /*InsnID*/3,
        GIM_CheckComplexPattern, /*MI*/1, /*Op*/2, /*Renderer*/GIMT_Encode2(2), GIMT_Encode2(GICP_gi_vop3mods),
        GIM_CheckComplexPattern, /*MI*/2, /*Op*/1, /*Renderer*/GIMT_Encode2(0), GIMT_Encode2(GICP_gi_vop3mods),
        GIM_CheckComplexPattern, /*MI*/2, /*Op*/2, /*Renderer*/GIMT_Encode2(1), GIMT_Encode2(GICP_gi_vop3mods),
        // (fmaxnum:{ *:[f32] } (fminnum:{ *:[f32] } (fmaxnum:{ *:[f32] } (VOP3Mods:{ *:[f32] } f32:{ *:[f32] }:$src0, i32:{ *:[i32] }:$src0_mods), (VOP3Mods:{ *:[f32] } f32:{ *:[f32] }:$src1, i32:{ *:[i32] }:$src1_mods)), (VOP3Mods:{ *:[f32] } f32:{ *:[f32] }:$src2, i32:{ *:[i32] }:$src2_mods)), (fminnum:{ *:[f32] } (VOP3Mods:{ *:[f32] } f32:{ *:[f32] }:$src0, i32:{ *:[i32] }:$src0_mods), (VOP3Mods:{ *:[f32] } f32:{ *:[f32] }:$src1, i32:{ *:[i32] }:$src1_mods)))<<P:Predicate_fmaxnum_like_nnan>>  =>  (V_MED3_F32_e64:{ *:[f32] } ?:{ *:[i32] }:$src0_mods, ?:{ *:[f32] }:$src0, ?:{ *:[i32] }:$src1_mods, ?:{ *:[f32] }:$src1, ?:{ *:[i32] }:$src2_mods, ?:{ *:[f32] }:$src2, 0:{ *:[i1] }, 0:{ *:[i32] })
        GIR_BuildMI, /*InsnID*/0, /*Opcode*/GIMT_Encode2(AMDGPU::V_MED3_F32_e64),
        GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/0, // DstI[vdst]
        GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/1, // src0_mods
        GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/0, // src0
        GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(1), /*SubOperand*/1, // src1_mods
        GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(1), /*SubOperand*/0, // src1
        GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(2), /*SubOperand*/1, // src2_mods
        GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(2), /*SubOperand*/0, // src2
        GIR_AddImm8, /*InsnID*/0, /*Imm*/0,
        GIR_AddImm8, /*InsnID*/0, /*Imm*/0,
        GIR_ConstrainSelectedInstOperands, /*InsnID*/0,
        GIR_EraseFromParent, /*InsnID*/0,
        // GIR_Coverage, 10232,
        GIR_Done,
      // Label 4660: @314566
      GIM_Try, /*On fail goto*//*Label 4661*/ GIMT_Encode4(314706), // Rule ID 10233 //
        GIM_CheckRegBankForClass, /*MI*/0, /*Op*/0, /*RC*/GIMT_Encode2(AMDGPU::VGPR_32RegClassID),
        GIM_RecordInsn, /*DefineMI*/1, /*MI*/0, /*OpIdx*/1, // MIs[1]
        GIM_CheckOpcode, /*MI*/1, GIMT_Encode2(TargetOpcode::G_FMINNUM),
        GIM_CheckType, /*MI*/1, /*Op*/1, /*Type*/GILLT_s32,
        GIM_CheckType, /*MI*/1, /*Op*/2, /*Type*/GILLT_s32,
        GIM_RecordInsn, /*DefineMI*/2, /*MI*/1, /*OpIdx*/1, // MIs[2]
        GIM_CheckOpcode, /*MI*/2, GIMT_Encode2(TargetOpcode::G_FMAXNUM),
        GIM_CheckType, /*MI*/2, /*Op*/1, /*Type*/GILLT_s32,
        GIM_CheckType, /*MI*/2, /*Op*/2, /*Type*/GILLT_s32,
        GIM_RecordInsn, /*DefineMI*/3, /*MI*/0, /*OpIdx*/2, // MIs[3]
        GIM_CheckOpcode, /*MI*/3, GIMT_Encode2(TargetOpcode::G_FMINNUM),
        // MIs[3] VOP3Mods:src1:src1_mods
        GIM_CheckIsSameOperand, /*MI*/3, /*OpIdx*/1, /*OtherMI*/2, /*OtherOpIdx*/2,
        // MIs[3] VOP3Mods:src0:src0_mods
        GIM_CheckIsSameOperand, /*MI*/3, /*OpIdx*/2, /*OtherMI*/2, /*OtherOpIdx*/1,
        GIM_CheckCxxInsnPredicate, /*MI*/0, /*FnId*/GIMT_Encode2(GICXXPred_MI_Predicate_fmaxnum_like_nnan),
        GIM_CheckIsSafeToFold, /*InsnID*/1,
        GIM_CheckIsSafeToFold, /*InsnID*/2,
        GIM_CheckIsSafeToFold, /*InsnID*/3,
        GIM_CheckComplexPattern, /*MI*/1, /*Op*/2, /*Renderer*/GIMT_Encode2(2), GIMT_Encode2(GICP_gi_vop3mods),
        GIM_CheckComplexPattern, /*MI*/2, /*Op*/1, /*Renderer*/GIMT_Encode2(0), GIMT_Encode2(GICP_gi_vop3mods),
        GIM_CheckComplexPattern, /*MI*/2, /*Op*/2, /*Renderer*/GIMT_Encode2(1), GIMT_Encode2(GICP_gi_vop3mods),
        // (fmaxnum:{ *:[f32] } (fminnum:{ *:[f32] } (fmaxnum:{ *:[f32] } (VOP3Mods:{ *:[f32] } f32:{ *:[f32] }:$src0, i32:{ *:[i32] }:$src0_mods), (VOP3Mods:{ *:[f32] } f32:{ *:[f32] }:$src1, i32:{ *:[i32] }:$src1_mods)), (VOP3Mods:{ *:[f32] } f32:{ *:[f32] }:$src2, i32:{ *:[i32] }:$src2_mods)), (fminnum:{ *:[f32] } (VOP3Mods:{ *:[f32] } f32:{ *:[f32] }:$src1, i32:{ *:[i32] }:$src1_mods), (VOP3Mods:{ *:[f32] } f32:{ *:[f32] }:$src0, i32:{ *:[i32] }:$src0_mods)))<<P:Predicate_fmaxnum_like_nnan>>  =>  (V_MED3_F32_e64:{ *:[f32] } ?:{ *:[i32] }:$src0_mods, ?:{ *:[f32] }:$src0, ?:{ *:[i32] }:$src1_mods, ?:{ *:[f32] }:$src1, ?:{ *:[i32] }:$src2_mods, ?:{ *:[f32] }:$src2, 0:{ *:[i1] }, 0:{ *:[i32] })
        GIR_BuildMI, /*InsnID*/0, /*Opcode*/GIMT_Encode2(AMDGPU::V_MED3_F32_e64),
        GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/0, // DstI[vdst]
        GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/1, // src0_mods
        GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/0, // src0
        GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(1), /*SubOperand*/1, // src1_mods
        GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(1), /*SubOperand*/0, // src1
        GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(2), /*SubOperand*/1, // src2_mods
        GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(2), /*SubOperand*/0, // src2
        GIR_AddImm8, /*InsnID*/0, /*Imm*/0,
        GIR_AddImm8, /*InsnID*/0, /*Imm*/0,
        GIR_ConstrainSelectedInstOperands, /*InsnID*/0,
        GIR_EraseFromParent, /*InsnID*/0,
        // GIR_Coverage, 10233,
        GIR_Done,
      // Label 4661: @314706
      GIM_Try, /*On fail goto*//*Label 4662*/ GIMT_Encode4(314846), // Rule ID 10234 //
        GIM_CheckRegBankForClass, /*MI*/0, /*Op*/0, /*RC*/GIMT_Encode2(AMDGPU::VGPR_32RegClassID),
        GIM_RecordInsn, /*DefineMI*/1, /*MI*/0, /*OpIdx*/1, // MIs[1]
        GIM_CheckOpcode, /*MI*/1, GIMT_Encode2(TargetOpcode::G_FMINNUM),
        GIM_CheckType, /*MI*/1, /*Op*/1, /*Type*/GILLT_s32,
        GIM_CheckType, /*MI*/1, /*Op*/2, /*Type*/GILLT_s32,
        GIM_RecordInsn, /*DefineMI*/2, /*MI*/1, /*OpIdx*/1, // MIs[2]
        GIM_CheckOpcode, /*MI*/2, GIMT_Encode2(TargetOpcode::G_FMAXNUM),
        GIM_CheckType, /*MI*/2, /*Op*/1, /*Type*/GILLT_s32,
        GIM_CheckType, /*MI*/2, /*Op*/2, /*Type*/GILLT_s32,
        GIM_RecordInsn, /*DefineMI*/3, /*MI*/0, /*OpIdx*/2, // MIs[3]
        GIM_CheckOpcode, /*MI*/3, GIMT_Encode2(TargetOpcode::G_FMINNUM),
        // MIs[3] VOP3Mods:src0:src0_mods
        GIM_CheckIsSameOperand, /*MI*/3, /*OpIdx*/1, /*OtherMI*/2, /*OtherOpIdx*/2,
        // MIs[3] VOP3Mods:src1:src1_mods
        GIM_CheckIsSameOperand, /*MI*/3, /*OpIdx*/2, /*OtherMI*/2, /*OtherOpIdx*/1,
        GIM_CheckCxxInsnPredicate, /*MI*/0, /*FnId*/GIMT_Encode2(GICXXPred_MI_Predicate_fmaxnum_like_nnan),
        GIM_CheckIsSafeToFold, /*InsnID*/1,
        GIM_CheckIsSafeToFold, /*InsnID*/2,
        GIM_CheckIsSafeToFold, /*InsnID*/3,
        GIM_CheckComplexPattern, /*MI*/1, /*Op*/2, /*Renderer*/GIMT_Encode2(2), GIMT_Encode2(GICP_gi_vop3mods),
        GIM_CheckComplexPattern, /*MI*/2, /*Op*/1, /*Renderer*/GIMT_Encode2(0), GIMT_Encode2(GICP_gi_vop3mods),
        GIM_CheckComplexPattern, /*MI*/2, /*Op*/2, /*Renderer*/GIMT_Encode2(1), GIMT_Encode2(GICP_gi_vop3mods),
        // (fmaxnum:{ *:[f32] } (fminnum:{ *:[f32] } (fmaxnum:{ *:[f32] } (VOP3Mods:{ *:[f32] } f32:{ *:[f32] }:$src1, i32:{ *:[i32] }:$src1_mods), (VOP3Mods:{ *:[f32] } f32:{ *:[f32] }:$src0, i32:{ *:[i32] }:$src0_mods)), (VOP3Mods:{ *:[f32] } f32:{ *:[f32] }:$src2, i32:{ *:[i32] }:$src2_mods)), (fminnum:{ *:[f32] } (VOP3Mods:{ *:[f32] } f32:{ *:[f32] }:$src0, i32:{ *:[i32] }:$src0_mods), (VOP3Mods:{ *:[f32] } f32:{ *:[f32] }:$src1, i32:{ *:[i32] }:$src1_mods)))<<P:Predicate_fmaxnum_like_nnan>>  =>  (V_MED3_F32_e64:{ *:[f32] } ?:{ *:[i32] }:$src0_mods, ?:{ *:[f32] }:$src0, ?:{ *:[i32] }:$src1_mods, ?:{ *:[f32] }:$src1, ?:{ *:[i32] }:$src2_mods, ?:{ *:[f32] }:$src2, 0:{ *:[i1] }, 0:{ *:[i32] })
        GIR_BuildMI, /*InsnID*/0, /*Opcode*/GIMT_Encode2(AMDGPU::V_MED3_F32_e64),
        GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/0, // DstI[vdst]
        GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(1), /*SubOperand*/1, // src0_mods
        GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(1), /*SubOperand*/0, // src0
        GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/1, // src1_mods
        GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/0, // src1
        GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(2), /*SubOperand*/1, // src2_mods
        GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(2), /*SubOperand*/0, // src2
        GIR_AddImm8, /*InsnID*/0, /*Imm*/0,
        GIR_AddImm8, /*InsnID*/0, /*Imm*/0,
        GIR_ConstrainSelectedInstOperands, /*InsnID*/0,
        GIR_EraseFromParent, /*InsnID*/0,
        // GIR_Coverage, 10234,
        GIR_Done,
      // Label 4662: @314846
      GIM_Try, /*On fail goto*//*Label 4663*/ GIMT_Encode4(314986), // Rule ID 10235 //
        GIM_CheckRegBankForClass, /*MI*/0, /*Op*/0, /*RC*/GIMT_Encode2(AMDGPU::VGPR_32RegClassID),
        GIM_RecordInsn, /*DefineMI*/1, /*MI*/0, /*OpIdx*/1, // MIs[1]
        GIM_CheckOpcode, /*MI*/1, GIMT_Encode2(TargetOpcode::G_FMINNUM),
        GIM_CheckType, /*MI*/1, /*Op*/1, /*Type*/GILLT_s32,
        GIM_CheckType, /*MI*/1, /*Op*/2, /*Type*/GILLT_s32,
        GIM_RecordInsn, /*DefineMI*/2, /*MI*/1, /*OpIdx*/1, // MIs[2]
        GIM_CheckOpcode, /*MI*/2, GIMT_Encode2(TargetOpcode::G_FMAXNUM),
        GIM_CheckType, /*MI*/2, /*Op*/1, /*Type*/GILLT_s32,
        GIM_CheckType, /*MI*/2, /*Op*/2, /*Type*/GILLT_s32,
        GIM_RecordInsn, /*DefineMI*/3, /*MI*/0, /*OpIdx*/2, // MIs[3]
        GIM_CheckOpcode, /*MI*/3, GIMT_Encode2(TargetOpcode::G_FMINNUM),
        // MIs[3] VOP3Mods:src1:src1_mods
        GIM_CheckIsSameOperand, /*MI*/3, /*OpIdx*/1, /*OtherMI*/2, /*OtherOpIdx*/1,
        // MIs[3] VOP3Mods:src0:src0_mods
        GIM_CheckIsSameOperand, /*MI*/3, /*OpIdx*/2, /*OtherMI*/2, /*OtherOpIdx*/2,
        GIM_CheckCxxInsnPredicate, /*MI*/0, /*FnId*/GIMT_Encode2(GICXXPred_MI_Predicate_fmaxnum_like_nnan),
        GIM_CheckIsSafeToFold, /*InsnID*/1,
        GIM_CheckIsSafeToFold, /*InsnID*/2,
        GIM_CheckIsSafeToFold, /*InsnID*/3,
        GIM_CheckComplexPattern, /*MI*/1, /*Op*/2, /*Renderer*/GIMT_Encode2(2), GIMT_Encode2(GICP_gi_vop3mods),
        GIM_CheckComplexPattern, /*MI*/2, /*Op*/1, /*Renderer*/GIMT_Encode2(0), GIMT_Encode2(GICP_gi_vop3mods),
        GIM_CheckComplexPattern, /*MI*/2, /*Op*/2, /*Renderer*/GIMT_Encode2(1), GIMT_Encode2(GICP_gi_vop3mods),
        // (fmaxnum:{ *:[f32] } (fminnum:{ *:[f32] } (fmaxnum:{ *:[f32] } (VOP3Mods:{ *:[f32] } f32:{ *:[f32] }:$src1, i32:{ *:[i32] }:$src1_mods), (VOP3Mods:{ *:[f32] } f32:{ *:[f32] }:$src0, i32:{ *:[i32] }:$src0_mods)), (VOP3Mods:{ *:[f32] } f32:{ *:[f32] }:$src2, i32:{ *:[i32] }:$src2_mods)), (fminnum:{ *:[f32] } (VOP3Mods:{ *:[f32] } f32:{ *:[f32] }:$src1, i32:{ *:[i32] }:$src1_mods), (VOP3Mods:{ *:[f32] } f32:{ *:[f32] }:$src0, i32:{ *:[i32] }:$src0_mods)))<<P:Predicate_fmaxnum_like_nnan>>  =>  (V_MED3_F32_e64:{ *:[f32] } ?:{ *:[i32] }:$src0_mods, ?:{ *:[f32] }:$src0, ?:{ *:[i32] }:$src1_mods, ?:{ *:[f32] }:$src1, ?:{ *:[i32] }:$src2_mods, ?:{ *:[f32] }:$src2, 0:{ *:[i1] }, 0:{ *:[i32] })
        GIR_BuildMI, /*InsnID*/0, /*Opcode*/GIMT_Encode2(AMDGPU::V_MED3_F32_e64),
        GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/0, // DstI[vdst]
        GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(1), /*SubOperand*/1, // src0_mods
        GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(1), /*SubOperand*/0, // src0
        GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/1, // src1_mods
        GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/0, // src1
        GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(2), /*SubOperand*/1, // src2_mods
        GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(2), /*SubOperand*/0, // src2
        GIR_AddImm8, /*InsnID*/0, /*Imm*/0,
        GIR_AddImm8, /*InsnID*/0, /*Imm*/0,
        GIR_ConstrainSelectedInstOperands, /*InsnID*/0,
        GIR_EraseFromParent, /*InsnID*/0,
        // GIR_Coverage, 10235,
        GIR_Done,
      // Label 4663: @314986
      GIM_Try, /*On fail goto*//*Label 4664*/ GIMT_Encode4(315126), // Rule ID 10172 //
        GIM_CheckRegBankForClass, /*MI*/0, /*Op*/0, /*RC*/GIMT_Encode2(AMDGPU::VGPR_32RegClassID),
        GIM_RecordInsn, /*DefineMI*/1, /*MI*/0, /*OpIdx*/1, // MIs[1]
        GIM_CheckOpcode, /*MI*/1, GIMT_Encode2(TargetOpcode::G_FMINNUM),
        GIM_CheckType, /*MI*/1, /*Op*/1, /*Type*/GILLT_s32,
        GIM_CheckType, /*MI*/1, /*Op*/2, /*Type*/GILLT_s32,
        GIM_RecordInsn, /*DefineMI*/2, /*MI*/1, /*OpIdx*/1, // MIs[2]
        GIM_CheckOpcode, /*MI*/2, GIMT_Encode2(TargetOpcode::G_FMAXNUM),
        GIM_CheckType, /*MI*/2, /*Op*/1, /*Type*/GILLT_s32,
        GIM_CheckType, /*MI*/2, /*Op*/2, /*Type*/GILLT_s32,
        GIM_RecordInsn, /*DefineMI*/3, /*MI*/0, /*OpIdx*/2, // MIs[3]
        GIM_CheckOpcode, /*MI*/3, GIMT_Encode2(TargetOpcode::G_FMINNUM_IEEE),
        // MIs[3] VOP3Mods:src0:src0_mods
        GIM_CheckIsSameOperand, /*MI*/3, /*OpIdx*/1, /*OtherMI*/2, /*OtherOpIdx*/1,
        // MIs[3] VOP3Mods:src1:src1_mods
        GIM_CheckIsSameOperand, /*MI*/3, /*OpIdx*/2, /*OtherMI*/2, /*OtherOpIdx*/2,
        GIM_CheckCxxInsnPredicate, /*MI*/0, /*FnId*/GIMT_Encode2(GICXXPred_MI_Predicate_fmaxnum_like_nnan),
        GIM_CheckIsSafeToFold, /*InsnID*/1,
        GIM_CheckIsSafeToFold, /*InsnID*/2,
        GIM_CheckIsSafeToFold, /*InsnID*/3,
        GIM_CheckComplexPattern, /*MI*/1, /*Op*/2, /*Renderer*/GIMT_Encode2(2), GIMT_Encode2(GICP_gi_vop3mods),
        GIM_CheckComplexPattern, /*MI*/2, /*Op*/1, /*Renderer*/GIMT_Encode2(0), GIMT_Encode2(GICP_gi_vop3mods),
        GIM_CheckComplexPattern, /*MI*/2, /*Op*/2, /*Renderer*/GIMT_Encode2(1), GIMT_Encode2(GICP_gi_vop3mods),
        // (fmaxnum:{ *:[f32] } (fminnum:{ *:[f32] } (fmaxnum:{ *:[f32] } (VOP3Mods:{ *:[f32] } f32:{ *:[f32] }:$src0, i32:{ *:[i32] }:$src0_mods), (VOP3Mods:{ *:[f32] } f32:{ *:[f32] }:$src1, i32:{ *:[i32] }:$src1_mods)), (VOP3Mods:{ *:[f32] } f32:{ *:[f32] }:$src2, i32:{ *:[i32] }:$src2_mods)), (fminnum_ieee:{ *:[f32] } (VOP3Mods:{ *:[f32] } f32:{ *:[f32] }:$src0, i32:{ *:[i32] }:$src0_mods), (VOP3Mods:{ *:[f32] } f32:{ *:[f32] }:$src1, i32:{ *:[i32] }:$src1_mods)))<<P:Predicate_fmaxnum_like_nnan>>  =>  (V_MED3_F32_e64:{ *:[f32] } ?:{ *:[i32] }:$src0_mods, ?:{ *:[f32] }:$src0, ?:{ *:[i32] }:$src1_mods, ?:{ *:[f32] }:$src1, ?:{ *:[i32] }:$src2_mods, ?:{ *:[f32] }:$src2, 0:{ *:[i1] }, 0:{ *:[i32] })
        GIR_BuildMI, /*InsnID*/0, /*Opcode*/GIMT_Encode2(AMDGPU::V_MED3_F32_e64),
        GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/0, // DstI[vdst]
        GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/1, // src0_mods
        GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/0, // src0
        GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(1), /*SubOperand*/1, // src1_mods
        GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(1), /*SubOperand*/0, // src1
        GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(2), /*SubOperand*/1, // src2_mods
        GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(2), /*SubOperand*/0, // src2
        GIR_AddImm8, /*InsnID*/0, /*Imm*/0,
        GIR_AddImm8, /*InsnID*/0, /*Imm*/0,
        GIR_ConstrainSelectedInstOperands, /*InsnID*/0,
        GIR_EraseFromParent, /*InsnID*/0,
        // GIR_Coverage, 10172,
        GIR_Done,
      // Label 4664: @315126
      GIM_Try, /*On fail goto*//*Label 4665*/ GIMT_Encode4(315266), // Rule ID 10173 //
        GIM_CheckRegBankForClass, /*MI*/0, /*Op*/0, /*RC*/GIMT_Encode2(AMDGPU::VGPR_32RegClassID),
        GIM_RecordInsn, /*DefineMI*/1, /*MI*/0, /*OpIdx*/1, // MIs[1]
        GIM_CheckOpcode, /*MI*/1, GIMT_Encode2(TargetOpcode::G_FMINNUM),
        GIM_CheckType, /*MI*/1, /*Op*/1, /*Type*/GILLT_s32,
        GIM_CheckType, /*MI*/1, /*Op*/2, /*Type*/GILLT_s32,
        GIM_RecordInsn, /*DefineMI*/2, /*MI*/1, /*OpIdx*/1, // MIs[2]
        GIM_CheckOpcode, /*MI*/2, GIMT_Encode2(TargetOpcode::G_FMAXNUM),
        GIM_CheckType, /*MI*/2, /*Op*/1, /*Type*/GILLT_s32,
        GIM_CheckType, /*MI*/2, /*Op*/2, /*Type*/GILLT_s32,
        GIM_RecordInsn, /*DefineMI*/3, /*MI*/0, /*OpIdx*/2, // MIs[3]
        GIM_CheckOpcode, /*MI*/3, GIMT_Encode2(TargetOpcode::G_FMINNUM_IEEE),
        // MIs[3] VOP3Mods:src1:src1_mods
        GIM_CheckIsSameOperand, /*MI*/3, /*OpIdx*/1, /*OtherMI*/2, /*OtherOpIdx*/2,
        // MIs[3] VOP3Mods:src0:src0_mods
        GIM_CheckIsSameOperand, /*MI*/3, /*OpIdx*/2, /*OtherMI*/2, /*OtherOpIdx*/1,
        GIM_CheckCxxInsnPredicate, /*MI*/0, /*FnId*/GIMT_Encode2(GICXXPred_MI_Predicate_fmaxnum_like_nnan),
        GIM_CheckIsSafeToFold, /*InsnID*/1,
        GIM_CheckIsSafeToFold, /*InsnID*/2,
        GIM_CheckIsSafeToFold, /*InsnID*/3,
        GIM_CheckComplexPattern, /*MI*/1, /*Op*/2, /*Renderer*/GIMT_Encode2(2), GIMT_Encode2(GICP_gi_vop3mods),
        GIM_CheckComplexPattern, /*MI*/2, /*Op*/1, /*Renderer*/GIMT_Encode2(0), GIMT_Encode2(GICP_gi_vop3mods),
        GIM_CheckComplexPattern, /*MI*/2, /*Op*/2, /*Renderer*/GIMT_Encode2(1), GIMT_Encode2(GICP_gi_vop3mods),
        // (fmaxnum:{ *:[f32] } (fminnum:{ *:[f32] } (fmaxnum:{ *:[f32] } (VOP3Mods:{ *:[f32] } f32:{ *:[f32] }:$src0, i32:{ *:[i32] }:$src0_mods), (VOP3Mods:{ *:[f32] } f32:{ *:[f32] }:$src1, i32:{ *:[i32] }:$src1_mods)), (VOP3Mods:{ *:[f32] } f32:{ *:[f32] }:$src2, i32:{ *:[i32] }:$src2_mods)), (fminnum_ieee:{ *:[f32] } (VOP3Mods:{ *:[f32] } f32:{ *:[f32] }:$src1, i32:{ *:[i32] }:$src1_mods), (VOP3Mods:{ *:[f32] } f32:{ *:[f32] }:$src0, i32:{ *:[i32] }:$src0_mods)))<<P:Predicate_fmaxnum_like_nnan>>  =>  (V_MED3_F32_e64:{ *:[f32] } ?:{ *:[i32] }:$src0_mods, ?:{ *:[f32] }:$src0, ?:{ *:[i32] }:$src1_mods, ?:{ *:[f32] }:$src1, ?:{ *:[i32] }:$src2_mods, ?:{ *:[f32] }:$src2, 0:{ *:[i1] }, 0:{ *:[i32] })
        GIR_BuildMI, /*InsnID*/0, /*Opcode*/GIMT_Encode2(AMDGPU::V_MED3_F32_e64),
        GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/0, // DstI[vdst]
        GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/1, // src0_mods
        GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/0, // src0
        GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(1), /*SubOperand*/1, // src1_mods
        GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(1), /*SubOperand*/0, // src1
        GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(2), /*SubOperand*/1, // src2_mods
        GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(2), /*SubOperand*/0, // src2
        GIR_AddImm8, /*InsnID*/0, /*Imm*/0,
        GIR_AddImm8, /*InsnID*/0, /*Imm*/0,
        GIR_ConstrainSelectedInstOperands, /*InsnID*/0,
        GIR_EraseFromParent, /*InsnID*/0,
        // GIR_Coverage, 10173,
        GIR_Done,
      // Label 4665: @315266
      GIM_Try, /*On fail goto*//*Label 4666*/ GIMT_Encode4(315406), // Rule ID 10174 //
        GIM_CheckRegBankForClass, /*MI*/0, /*Op*/0, /*RC*/GIMT_Encode2(AMDGPU::VGPR_32RegClassID),
        GIM_RecordInsn, /*DefineMI*/1, /*MI*/0, /*OpIdx*/1, // MIs[1]
        GIM_CheckOpcode, /*MI*/1, GIMT_Encode2(TargetOpcode::G_FMINNUM),
        GIM_CheckType, /*MI*/1, /*Op*/1, /*Type*/GILLT_s32,
        GIM_CheckType, /*MI*/1, /*Op*/2, /*Type*/GILLT_s32,
        GIM_RecordInsn, /*DefineMI*/2, /*MI*/1, /*OpIdx*/1, // MIs[2]
        GIM_CheckOpcode, /*MI*/2, GIMT_Encode2(TargetOpcode::G_FMAXNUM),
        GIM_CheckType, /*MI*/2, /*Op*/1, /*Type*/GILLT_s32,
        GIM_CheckType, /*MI*/2, /*Op*/2, /*Type*/GILLT_s32,
        GIM_RecordInsn, /*DefineMI*/3, /*MI*/0, /*OpIdx*/2, // MIs[3]
        GIM_CheckOpcode, /*MI*/3, GIMT_Encode2(TargetOpcode::G_FMINNUM_IEEE),
        // MIs[3] VOP3Mods:src0:src0_mods
        GIM_CheckIsSameOperand, /*MI*/3, /*OpIdx*/1, /*OtherMI*/2, /*OtherOpIdx*/2,
        // MIs[3] VOP3Mods:src1:src1_mods
        GIM_CheckIsSameOperand, /*MI*/3, /*OpIdx*/2, /*OtherMI*/2, /*OtherOpIdx*/1,
        GIM_CheckCxxInsnPredicate, /*MI*/0, /*FnId*/GIMT_Encode2(GICXXPred_MI_Predicate_fmaxnum_like_nnan),
        GIM_CheckIsSafeToFold, /*InsnID*/1,
        GIM_CheckIsSafeToFold, /*InsnID*/2,
        GIM_CheckIsSafeToFold, /*InsnID*/3,
        GIM_CheckComplexPattern, /*MI*/1, /*Op*/2, /*Renderer*/GIMT_Encode2(2), GIMT_Encode2(GICP_gi_vop3mods),
        GIM_CheckComplexPattern, /*MI*/2, /*Op*/1, /*Renderer*/GIMT_Encode2(0), GIMT_Encode2(GICP_gi_vop3mods),
        GIM_CheckComplexPattern, /*MI*/2, /*Op*/2, /*Renderer*/GIMT_Encode2(1), GIMT_Encode2(GICP_gi_vop3mods),
        // (fmaxnum:{ *:[f32] } (fminnum:{ *:[f32] } (fmaxnum:{ *:[f32] } (VOP3Mods:{ *:[f32] } f32:{ *:[f32] }:$src1, i32:{ *:[i32] }:$src1_mods), (VOP3Mods:{ *:[f32] } f32:{ *:[f32] }:$src0, i32:{ *:[i32] }:$src0_mods)), (VOP3Mods:{ *:[f32] } f32:{ *:[f32] }:$src2, i32:{ *:[i32] }:$src2_mods)), (fminnum_ieee:{ *:[f32] } (VOP3Mods:{ *:[f32] } f32:{ *:[f32] }:$src0, i32:{ *:[i32] }:$src0_mods), (VOP3Mods:{ *:[f32] } f32:{ *:[f32] }:$src1, i32:{ *:[i32] }:$src1_mods)))<<P:Predicate_fmaxnum_like_nnan>>  =>  (V_MED3_F32_e64:{ *:[f32] } ?:{ *:[i32] }:$src0_mods, ?:{ *:[f32] }:$src0, ?:{ *:[i32] }:$src1_mods, ?:{ *:[f32] }:$src1, ?:{ *:[i32] }:$src2_mods, ?:{ *:[f32] }:$src2, 0:{ *:[i1] }, 0:{ *:[i32] })
        GIR_BuildMI, /*InsnID*/0, /*Opcode*/GIMT_Encode2(AMDGPU::V_MED3_F32_e64),
        GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/0, // DstI[vdst]
        GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(1), /*SubOperand*/1, // src0_mods
        GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(1), /*SubOperand*/0, // src0
        GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/1, // src1_mods
        GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/0, // src1
        GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(2), /*SubOperand*/1, // src2_mods
        GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(2), /*SubOperand*/0, // src2
        GIR_AddImm8, /*InsnID*/0, /*Imm*/0,
        GIR_AddImm8, /*InsnID*/0, /*Imm*/0,
        GIR_ConstrainSelectedInstOperands, /*InsnID*/0,
        GIR_EraseFromParent, /*InsnID*/0,
        // GIR_Coverage, 10174,
        GIR_Done,
      // Label 4666: @315406
      GIM_Try, /*On fail goto*//*Label 4667*/ GIMT_Encode4(315546), // Rule ID 10175 //
        GIM_CheckRegBankForClass, /*MI*/0, /*Op*/0, /*RC*/GIMT_Encode2(AMDGPU::VGPR_32RegClassID),
        GIM_RecordInsn, /*DefineMI*/1, /*MI*/0, /*OpIdx*/1, // MIs[1]
        GIM_CheckOpcode, /*MI*/1, GIMT_Encode2(TargetOpcode::G_FMINNUM),
        GIM_CheckType, /*MI*/1, /*Op*/1, /*Type*/GILLT_s32,
        GIM_CheckType, /*MI*/1, /*Op*/2, /*Type*/GILLT_s32,
        GIM_RecordInsn, /*DefineMI*/2, /*MI*/1, /*OpIdx*/1, // MIs[2]
        GIM_CheckOpcode, /*MI*/2, GIMT_Encode2(TargetOpcode::G_FMAXNUM),
        GIM_CheckType, /*MI*/2, /*Op*/1, /*Type*/GILLT_s32,
        GIM_CheckType, /*MI*/2, /*Op*/2, /*Type*/GILLT_s32,
        GIM_RecordInsn, /*DefineMI*/3, /*MI*/0, /*OpIdx*/2, // MIs[3]
        GIM_CheckOpcode, /*MI*/3, GIMT_Encode2(TargetOpcode::G_FMINNUM_IEEE),
        // MIs[3] VOP3Mods:src1:src1_mods
        GIM_CheckIsSameOperand, /*MI*/3, /*OpIdx*/1, /*OtherMI*/2, /*OtherOpIdx*/1,
        // MIs[3] VOP3Mods:src0:src0_mods
        GIM_CheckIsSameOperand, /*MI*/3, /*OpIdx*/2, /*OtherMI*/2, /*OtherOpIdx*/2,
        GIM_CheckCxxInsnPredicate, /*MI*/0, /*FnId*/GIMT_Encode2(GICXXPred_MI_Predicate_fmaxnum_like_nnan),
        GIM_CheckIsSafeToFold, /*InsnID*/1,
        GIM_CheckIsSafeToFold, /*InsnID*/2,
        GIM_CheckIsSafeToFold, /*InsnID*/3,
        GIM_CheckComplexPattern, /*MI*/1, /*Op*/2, /*Renderer*/GIMT_Encode2(2), GIMT_Encode2(GICP_gi_vop3mods),
        GIM_CheckComplexPattern, /*MI*/2, /*Op*/1, /*Renderer*/GIMT_Encode2(0), GIMT_Encode2(GICP_gi_vop3mods),
        GIM_CheckComplexPattern, /*MI*/2, /*Op*/2, /*Renderer*/GIMT_Encode2(1), GIMT_Encode2(GICP_gi_vop3mods),
        // (fmaxnum:{ *:[f32] } (fminnum:{ *:[f32] } (fmaxnum:{ *:[f32] } (VOP3Mods:{ *:[f32] } f32:{ *:[f32] }:$src1, i32:{ *:[i32] }:$src1_mods), (VOP3Mods:{ *:[f32] } f32:{ *:[f32] }:$src0, i32:{ *:[i32] }:$src0_mods)), (VOP3Mods:{ *:[f32] } f32:{ *:[f32] }:$src2, i32:{ *:[i32] }:$src2_mods)), (fminnum_ieee:{ *:[f32] } (VOP3Mods:{ *:[f32] } f32:{ *:[f32] }:$src1, i32:{ *:[i32] }:$src1_mods), (VOP3Mods:{ *:[f32] } f32:{ *:[f32] }:$src0, i32:{ *:[i32] }:$src0_mods)))<<P:Predicate_fmaxnum_like_nnan>>  =>  (V_MED3_F32_e64:{ *:[f32] } ?:{ *:[i32] }:$src0_mods, ?:{ *:[f32] }:$src0, ?:{ *:[i32] }:$src1_mods, ?:{ *:[f32] }:$src1, ?:{ *:[i32] }:$src2_mods, ?:{ *:[f32] }:$src2, 0:{ *:[i1] }, 0:{ *:[i32] })
        GIR_BuildMI, /*InsnID*/0, /*Opcode*/GIMT_Encode2(AMDGPU::V_MED3_F32_e64),
        GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/0, // DstI[vdst]
        GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(1), /*SubOperand*/1, // src0_mods
        GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(1), /*SubOperand*/0, // src0
        GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/1, // src1_mods
        GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/0, // src1
        GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(2), /*SubOperand*/1, // src2_mods
        GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(2), /*SubOperand*/0, // src2
        GIR_AddImm8, /*InsnID*/0, /*Imm*/0,
        GIR_AddImm8, /*InsnID*/0, /*Imm*/0,
        GIR_ConstrainSelectedInstOperands, /*InsnID*/0,
        GIR_EraseFromParent, /*InsnID*/0,
        // GIR_Coverage, 10175,
        GIR_Done,
      // Label 4667: @315546
      GIM_Try, /*On fail goto*//*Label 4668*/ GIMT_Encode4(315686), // Rule ID 10217 //
        GIM_CheckRegBankForClass, /*MI*/0, /*Op*/0, /*RC*/GIMT_Encode2(AMDGPU::VGPR_32RegClassID),
        GIM_RecordInsn, /*DefineMI*/1, /*MI*/0, /*OpIdx*/1, // MIs[1]
        GIM_CheckOpcode, /*MI*/1, GIMT_Encode2(TargetOpcode::G_FMINNUM),
        GIM_CheckType, /*MI*/1, /*Op*/1, /*Type*/GILLT_s32,
        GIM_CheckType, /*MI*/1, /*Op*/2, /*Type*/GILLT_s32,
        GIM_RecordInsn, /*DefineMI*/2, /*MI*/1, /*OpIdx*/1, // MIs[2]
        GIM_CheckOpcode, /*MI*/2, GIMT_Encode2(TargetOpcode::G_FMAXNUM_IEEE),
        GIM_CheckType, /*MI*/2, /*Op*/1, /*Type*/GILLT_s32,
        GIM_CheckType, /*MI*/2, /*Op*/2, /*Type*/GILLT_s32,
        GIM_RecordInsn, /*DefineMI*/3, /*MI*/0, /*OpIdx*/2, // MIs[3]
        GIM_CheckOpcode, /*MI*/3, GIMT_Encode2(TargetOpcode::G_FMINNUM),
        // MIs[3] VOP3Mods:src0:src0_mods
        GIM_CheckIsSameOperand, /*MI*/3, /*OpIdx*/1, /*OtherMI*/2, /*OtherOpIdx*/1,
        // MIs[3] VOP3Mods:src1:src1_mods
        GIM_CheckIsSameOperand, /*MI*/3, /*OpIdx*/2, /*OtherMI*/2, /*OtherOpIdx*/2,
        GIM_CheckCxxInsnPredicate, /*MI*/0, /*FnId*/GIMT_Encode2(GICXXPred_MI_Predicate_fmaxnum_like_nnan),
        GIM_CheckIsSafeToFold, /*InsnID*/1,
        GIM_CheckIsSafeToFold, /*InsnID*/2,
        GIM_CheckIsSafeToFold, /*InsnID*/3,
        GIM_CheckComplexPattern, /*MI*/1, /*Op*/2, /*Renderer*/GIMT_Encode2(2), GIMT_Encode2(GICP_gi_vop3mods),
        GIM_CheckComplexPattern, /*MI*/2, /*Op*/1, /*Renderer*/GIMT_Encode2(0), GIMT_Encode2(GICP_gi_vop3mods),
        GIM_CheckComplexPattern, /*MI*/2, /*Op*/2, /*Renderer*/GIMT_Encode2(1), GIMT_Encode2(GICP_gi_vop3mods),
        // (fmaxnum:{ *:[f32] } (fminnum:{ *:[f32] } (fmaxnum_ieee:{ *:[f32] } (VOP3Mods:{ *:[f32] } f32:{ *:[f32] }:$src0, i32:{ *:[i32] }:$src0_mods), (VOP3Mods:{ *:[f32] } f32:{ *:[f32] }:$src1, i32:{ *:[i32] }:$src1_mods)), (VOP3Mods:{ *:[f32] } f32:{ *:[f32] }:$src2, i32:{ *:[i32] }:$src2_mods)), (fminnum:{ *:[f32] } (VOP3Mods:{ *:[f32] } f32:{ *:[f32] }:$src0, i32:{ *:[i32] }:$src0_mods), (VOP3Mods:{ *:[f32] } f32:{ *:[f32] }:$src1, i32:{ *:[i32] }:$src1_mods)))<<P:Predicate_fmaxnum_like_nnan>>  =>  (V_MED3_F32_e64:{ *:[f32] } ?:{ *:[i32] }:$src0_mods, ?:{ *:[f32] }:$src0, ?:{ *:[i32] }:$src1_mods, ?:{ *:[f32] }:$src1, ?:{ *:[i32] }:$src2_mods, ?:{ *:[f32] }:$src2, 0:{ *:[i1] }, 0:{ *:[i32] })
        GIR_BuildMI, /*InsnID*/0, /*Opcode*/GIMT_Encode2(AMDGPU::V_MED3_F32_e64),
        GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/0, // DstI[vdst]
        GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/1, // src0_mods
        GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/0, // src0
        GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(1), /*SubOperand*/1, // src1_mods
        GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(1), /*SubOperand*/0, // src1
        GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(2), /*SubOperand*/1, // src2_mods
        GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(2), /*SubOperand*/0, // src2
        GIR_AddImm8, /*InsnID*/0, /*Imm*/0,
        GIR_AddImm8, /*InsnID*/0, /*Imm*/0,
        GIR_ConstrainSelectedInstOperands, /*InsnID*/0,
        GIR_EraseFromParent, /*InsnID*/0,
        // GIR_Coverage, 10217,
        GIR_Done,
      // Label 4668: @315686
      GIM_Try, /*On fail goto*//*Label 4669*/ GIMT_Encode4(315826), // Rule ID 10218 //
        GIM_CheckRegBankForClass, /*MI*/0, /*Op*/0, /*RC*/GIMT_Encode2(AMDGPU::VGPR_32RegClassID),
        GIM_RecordInsn, /*DefineMI*/1, /*MI*/0, /*OpIdx*/1, // MIs[1]
        GIM_CheckOpcode, /*MI*/1, GIMT_Encode2(TargetOpcode::G_FMINNUM),
        GIM_CheckType, /*MI*/1, /*Op*/1, /*Type*/GILLT_s32,
        GIM_CheckType, /*MI*/1, /*Op*/2, /*Type*/GILLT_s32,
        GIM_RecordInsn, /*DefineMI*/2, /*MI*/1, /*OpIdx*/1, // MIs[2]
        GIM_CheckOpcode, /*MI*/2, GIMT_Encode2(TargetOpcode::G_FMAXNUM_IEEE),
        GIM_CheckType, /*MI*/2, /*Op*/1, /*Type*/GILLT_s32,
        GIM_CheckType, /*MI*/2, /*Op*/2, /*Type*/GILLT_s32,
        GIM_RecordInsn, /*DefineMI*/3, /*MI*/0, /*OpIdx*/2, // MIs[3]
        GIM_CheckOpcode, /*MI*/3, GIMT_Encode2(TargetOpcode::G_FMINNUM),
        // MIs[3] VOP3Mods:src1:src1_mods
        GIM_CheckIsSameOperand, /*MI*/3, /*OpIdx*/1, /*OtherMI*/2, /*OtherOpIdx*/2,
        // MIs[3] VOP3Mods:src0:src0_mods
        GIM_CheckIsSameOperand, /*MI*/3, /*OpIdx*/2, /*OtherMI*/2, /*OtherOpIdx*/1,
        GIM_CheckCxxInsnPredicate, /*MI*/0, /*FnId*/GIMT_Encode2(GICXXPred_MI_Predicate_fmaxnum_like_nnan),
        GIM_CheckIsSafeToFold, /*InsnID*/1,
        GIM_CheckIsSafeToFold, /*InsnID*/2,
        GIM_CheckIsSafeToFold, /*InsnID*/3,
        GIM_CheckComplexPattern, /*MI*/1, /*Op*/2, /*Renderer*/GIMT_Encode2(2), GIMT_Encode2(GICP_gi_vop3mods),
        GIM_CheckComplexPattern, /*MI*/2, /*Op*/1, /*Renderer*/GIMT_Encode2(0), GIMT_Encode2(GICP_gi_vop3mods),
        GIM_CheckComplexPattern, /*MI*/2, /*Op*/2, /*Renderer*/GIMT_Encode2(1), GIMT_Encode2(GICP_gi_vop3mods),
        // (fmaxnum:{ *:[f32] } (fminnum:{ *:[f32] } (fmaxnum_ieee:{ *:[f32] } (VOP3Mods:{ *:[f32] } f32:{ *:[f32] }:$src0, i32:{ *:[i32] }:$src0_mods), (VOP3Mods:{ *:[f32] } f32:{ *:[f32] }:$src1, i32:{ *:[i32] }:$src1_mods)), (VOP3Mods:{ *:[f32] } f32:{ *:[f32] }:$src2, i32:{ *:[i32] }:$src2_mods)), (fminnum:{ *:[f32] } (VOP3Mods:{ *:[f32] } f32:{ *:[f32] }:$src1, i32:{ *:[i32] }:$src1_mods), (VOP3Mods:{ *:[f32] } f32:{ *:[f32] }:$src0, i32:{ *:[i32] }:$src0_mods)))<<P:Predicate_fmaxnum_like_nnan>>  =>  (V_MED3_F32_e64:{ *:[f32] } ?:{ *:[i32] }:$src0_mods, ?:{ *:[f32] }:$src0, ?:{ *:[i32] }:$src1_mods, ?:{ *:[f32] }:$src1, ?:{ *:[i32] }:$src2_mods, ?:{ *:[f32] }:$src2, 0:{ *:[i1] }, 0:{ *:[i32] })
        GIR_BuildMI, /*InsnID*/0, /*Opcode*/GIMT_Encode2(AMDGPU::V_MED3_F32_e64),
        GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/0, // DstI[vdst]
        GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/1, // src0_mods
        GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/0, // src0
        GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(1), /*SubOperand*/1, // src1_mods
        GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(1), /*SubOperand*/0, // src1
        GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(2), /*SubOperand*/1, // src2_mods
        GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(2), /*SubOperand*/0, // src2
        GIR_AddImm8, /*InsnID*/0, /*Imm*/0,
        GIR_AddImm8, /*InsnID*/0, /*Imm*/0,
        GIR_ConstrainSelectedInstOperands, /*InsnID*/0,
        GIR_EraseFromParent, /*InsnID*/0,
        // GIR_Coverage, 10218,
        GIR_Done,
      // Label 4669: @315826
      GIM_Try, /*On fail goto*//*Label 4670*/ GIMT_Encode4(315966), // Rule ID 10219 //
        GIM_CheckRegBankForClass, /*MI*/0, /*Op*/0, /*RC*/GIMT_Encode2(AMDGPU::VGPR_32RegClassID),
        GIM_RecordInsn, /*DefineMI*/1, /*MI*/0, /*OpIdx*/1, // MIs[1]
        GIM_CheckOpcode, /*MI*/1, GIMT_Encode2(TargetOpcode::G_FMINNUM),
        GIM_CheckType, /*MI*/1, /*Op*/1, /*Type*/GILLT_s32,
        GIM_CheckType, /*MI*/1, /*Op*/2, /*Type*/GILLT_s32,
        GIM_RecordInsn, /*DefineMI*/2, /*MI*/1, /*OpIdx*/1, // MIs[2]
        GIM_CheckOpcode, /*MI*/2, GIMT_Encode2(TargetOpcode::G_FMAXNUM_IEEE),
        GIM_CheckType, /*MI*/2, /*Op*/1, /*Type*/GILLT_s32,
        GIM_CheckType, /*MI*/2, /*Op*/2, /*Type*/GILLT_s32,
        GIM_RecordInsn, /*DefineMI*/3, /*MI*/0, /*OpIdx*/2, // MIs[3]
        GIM_CheckOpcode, /*MI*/3, GIMT_Encode2(TargetOpcode::G_FMINNUM),
        // MIs[3] VOP3Mods:src0:src0_mods
        GIM_CheckIsSameOperand, /*MI*/3, /*OpIdx*/1, /*OtherMI*/2, /*OtherOpIdx*/2,
        // MIs[3] VOP3Mods:src1:src1_mods
        GIM_CheckIsSameOperand, /*MI*/3, /*OpIdx*/2, /*OtherMI*/2, /*OtherOpIdx*/1,
        GIM_CheckCxxInsnPredicate, /*MI*/0, /*FnId*/GIMT_Encode2(GICXXPred_MI_Predicate_fmaxnum_like_nnan),
        GIM_CheckIsSafeToFold, /*InsnID*/1,
        GIM_CheckIsSafeToFold, /*InsnID*/2,
        GIM_CheckIsSafeToFold, /*InsnID*/3,
        GIM_CheckComplexPattern, /*MI*/1, /*Op*/2, /*Renderer*/GIMT_Encode2(2), GIMT_Encode2(GICP_gi_vop3mods),
        GIM_CheckComplexPattern, /*MI*/2, /*Op*/1, /*Renderer*/GIMT_Encode2(0), GIMT_Encode2(GICP_gi_vop3mods),
        GIM_CheckComplexPattern, /*MI*/2, /*Op*/2, /*Renderer*/GIMT_Encode2(1), GIMT_Encode2(GICP_gi_vop3mods),
        // (fmaxnum:{ *:[f32] } (fminnum:{ *:[f32] } (fmaxnum_ieee:{ *:[f32] } (VOP3Mods:{ *:[f32] } f32:{ *:[f32] }:$src1, i32:{ *:[i32] }:$src1_mods), (VOP3Mods:{ *:[f32] } f32:{ *:[f32] }:$src0, i32:{ *:[i32] }:$src0_mods)), (VOP3Mods:{ *:[f32] } f32:{ *:[f32] }:$src2, i32:{ *:[i32] }:$src2_mods)), (fminnum:{ *:[f32] } (VOP3Mods:{ *:[f32] } f32:{ *:[f32] }:$src0, i32:{ *:[i32] }:$src0_mods), (VOP3Mods:{ *:[f32] } f32:{ *:[f32] }:$src1, i32:{ *:[i32] }:$src1_mods)))<<P:Predicate_fmaxnum_like_nnan>>  =>  (V_MED3_F32_e64:{ *:[f32] } ?:{ *:[i32] }:$src0_mods, ?:{ *:[f32] }:$src0, ?:{ *:[i32] }:$src1_mods, ?:{ *:[f32] }:$src1, ?:{ *:[i32] }:$src2_mods, ?:{ *:[f32] }:$src2, 0:{ *:[i1] }, 0:{ *:[i32] })
        GIR_BuildMI, /*InsnID*/0, /*Opcode*/GIMT_Encode2(AMDGPU::V_MED3_F32_e64),
        GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/0, // DstI[vdst]
        GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(1), /*SubOperand*/1, // src0_mods
        GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(1), /*SubOperand*/0, // src0
        GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/1, // src1_mods
        GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/0, // src1
        GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(2), /*SubOperand*/1, // src2_mods
        GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(2), /*SubOperand*/0, // src2
        GIR_AddImm8, /*InsnID*/0, /*Imm*/0,
        GIR_AddImm8, /*InsnID*/0, /*Imm*/0,
        GIR_ConstrainSelectedInstOperands, /*InsnID*/0,
        GIR_EraseFromParent, /*InsnID*/0,
        // GIR_Coverage, 10219,
        GIR_Done,
      // Label 4670: @315966
      GIM_Try, /*On fail goto*//*Label 4671*/ GIMT_Encode4(316106), // Rule ID 10220 //
        GIM_CheckRegBankForClass, /*MI*/0, /*Op*/0, /*RC*/GIMT_Encode2(AMDGPU::VGPR_32RegClassID),
        GIM_RecordInsn, /*DefineMI*/1, /*MI*/0, /*OpIdx*/1, // MIs[1]
        GIM_CheckOpcode, /*MI*/1, GIMT_Encode2(TargetOpcode::G_FMINNUM),
        GIM_CheckType, /*MI*/1, /*Op*/1, /*Type*/GILLT_s32,
        GIM_CheckType, /*MI*/1, /*Op*/2, /*Type*/GILLT_s32,
        GIM_RecordInsn, /*DefineMI*/2, /*MI*/1, /*OpIdx*/1, // MIs[2]
        GIM_CheckOpcode, /*MI*/2, GIMT_Encode2(TargetOpcode::G_FMAXNUM_IEEE),
        GIM_CheckType, /*MI*/2, /*Op*/1, /*Type*/GILLT_s32,
        GIM_CheckType, /*MI*/2, /*Op*/2, /*Type*/GILLT_s32,
        GIM_RecordInsn, /*DefineMI*/3, /*MI*/0, /*OpIdx*/2, // MIs[3]
        GIM_CheckOpcode, /*MI*/3, GIMT_Encode2(TargetOpcode::G_FMINNUM),
        // MIs[3] VOP3Mods:src1:src1_mods
        GIM_CheckIsSameOperand, /*MI*/3, /*OpIdx*/1, /*OtherMI*/2, /*OtherOpIdx*/1,
        // MIs[3] VOP3Mods:src0:src0_mods
        GIM_CheckIsSameOperand, /*MI*/3, /*OpIdx*/2, /*OtherMI*/2, /*OtherOpIdx*/2,
        GIM_CheckCxxInsnPredicate, /*MI*/0, /*FnId*/GIMT_Encode2(GICXXPred_MI_Predicate_fmaxnum_like_nnan),
        GIM_CheckIsSafeToFold, /*InsnID*/1,
        GIM_CheckIsSafeToFold, /*InsnID*/2,
        GIM_CheckIsSafeToFold, /*InsnID*/3,
        GIM_CheckComplexPattern, /*MI*/1, /*Op*/2, /*Renderer*/GIMT_Encode2(2), GIMT_Encode2(GICP_gi_vop3mods),
        GIM_CheckComplexPattern, /*MI*/2, /*Op*/1, /*Renderer*/GIMT_Encode2(0), GIMT_Encode2(GICP_gi_vop3mods),
        GIM_CheckComplexPattern, /*MI*/2, /*Op*/2, /*Renderer*/GIMT_Encode2(1), GIMT_Encode2(GICP_gi_vop3mods),
        // (fmaxnum:{ *:[f32] } (fminnum:{ *:[f32] } (fmaxnum_ieee:{ *:[f32] } (VOP3Mods:{ *:[f32] } f32:{ *:[f32] }:$src1, i32:{ *:[i32] }:$src1_mods), (VOP3Mods:{ *:[f32] } f32:{ *:[f32] }:$src0, i32:{ *:[i32] }:$src0_mods)), (VOP3Mods:{ *:[f32] } f32:{ *:[f32] }:$src2, i32:{ *:[i32] }:$src2_mods)), (fminnum:{ *:[f32] } (VOP3Mods:{ *:[f32] } f32:{ *:[f32] }:$src1, i32:{ *:[i32] }:$src1_mods), (VOP3Mods:{ *:[f32] } f32:{ *:[f32] }:$src0, i32:{ *:[i32] }:$src0_mods)))<<P:Predicate_fmaxnum_like_nnan>>  =>  (V_MED3_F32_e64:{ *:[f32] } ?:{ *:[i32] }:$src0_mods, ?:{ *:[f32] }:$src0, ?:{ *:[i32] }:$src1_mods, ?:{ *:[f32] }:$src1, ?:{ *:[i32] }:$src2_mods, ?:{ *:[f32] }:$src2, 0:{ *:[i1] }, 0:{ *:[i32] })
        GIR_BuildMI, /*InsnID*/0, /*Opcode*/GIMT_Encode2(AMDGPU::V_MED3_F32_e64),
        GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/0, // DstI[vdst]
        GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(1), /*SubOperand*/1, // src0_mods
        GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(1), /*SubOperand*/0, // src0
        GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/1, // src1_mods
        GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/0, // src1
        GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(2), /*SubOperand*/1, // src2_mods
        GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(2), /*SubOperand*/0, // src2
        GIR_AddImm8, /*InsnID*/0, /*Imm*/0,
        GIR_AddImm8, /*InsnID*/0, /*Imm*/0,
        GIR_ConstrainSelectedInstOperands, /*InsnID*/0,
        GIR_EraseFromParent, /*InsnID*/0,
        // GIR_Coverage, 10220,
        GIR_Done,
      // Label 4671: @316106
      GIM_Try, /*On fail goto*//*Label 4672*/ GIMT_Encode4(316246), // Rule ID 10157 //
        GIM_CheckRegBankForClass, /*MI*/0, /*Op*/0, /*RC*/GIMT_Encode2(AMDGPU::VGPR_32RegClassID),
        GIM_RecordInsn, /*DefineMI*/1, /*MI*/0, /*OpIdx*/1, // MIs[1]
        GIM_CheckOpcode, /*MI*/1, GIMT_Encode2(TargetOpcode::G_FMINNUM),
        GIM_CheckType, /*MI*/1, /*Op*/1, /*Type*/GILLT_s32,
        GIM_CheckType, /*MI*/1, /*Op*/2, /*Type*/GILLT_s32,
        GIM_RecordInsn, /*DefineMI*/2, /*MI*/1, /*OpIdx*/1, // MIs[2]
        GIM_CheckOpcode, /*MI*/2, GIMT_Encode2(TargetOpcode::G_FMAXNUM_IEEE),
        GIM_CheckType, /*MI*/2, /*Op*/1, /*Type*/GILLT_s32,
        GIM_CheckType, /*MI*/2, /*Op*/2, /*Type*/GILLT_s32,
        GIM_RecordInsn, /*DefineMI*/3, /*MI*/0, /*OpIdx*/2, // MIs[3]
        GIM_CheckOpcode, /*MI*/3, GIMT_Encode2(TargetOpcode::G_FMINNUM_IEEE),
        // MIs[3] VOP3Mods:src0:src0_mods
        GIM_CheckIsSameOperand, /*MI*/3, /*OpIdx*/1, /*OtherMI*/2, /*OtherOpIdx*/1,
        // MIs[3] VOP3Mods:src1:src1_mods
        GIM_CheckIsSameOperand, /*MI*/3, /*OpIdx*/2, /*OtherMI*/2, /*OtherOpIdx*/2,
        GIM_CheckCxxInsnPredicate, /*MI*/0, /*FnId*/GIMT_Encode2(GICXXPred_MI_Predicate_fmaxnum_like_nnan),
        GIM_CheckIsSafeToFold, /*InsnID*/1,
        GIM_CheckIsSafeToFold, /*InsnID*/2,
        GIM_CheckIsSafeToFold, /*InsnID*/3,
        GIM_CheckComplexPattern, /*MI*/1, /*Op*/2, /*Renderer*/GIMT_Encode2(2), GIMT_Encode2(GICP_gi_vop3mods),
        GIM_CheckComplexPattern, /*MI*/2, /*Op*/1, /*Renderer*/GIMT_Encode2(0), GIMT_Encode2(GICP_gi_vop3mods),
        GIM_CheckComplexPattern, /*MI*/2, /*Op*/2, /*Renderer*/GIMT_Encode2(1), GIMT_Encode2(GICP_gi_vop3mods),
        // (fmaxnum:{ *:[f32] } (fminnum:{ *:[f32] } (fmaxnum_ieee:{ *:[f32] } (VOP3Mods:{ *:[f32] } f32:{ *:[f32] }:$src0, i32:{ *:[i32] }:$src0_mods), (VOP3Mods:{ *:[f32] } f32:{ *:[f32] }:$src1, i32:{ *:[i32] }:$src1_mods)), (VOP3Mods:{ *:[f32] } f32:{ *:[f32] }:$src2, i32:{ *:[i32] }:$src2_mods)), (fminnum_ieee:{ *:[f32] } (VOP3Mods:{ *:[f32] } f32:{ *:[f32] }:$src0, i32:{ *:[i32] }:$src0_mods), (VOP3Mods:{ *:[f32] } f32:{ *:[f32] }:$src1, i32:{ *:[i32] }:$src1_mods)))<<P:Predicate_fmaxnum_like_nnan>>  =>  (V_MED3_F32_e64:{ *:[f32] } ?:{ *:[i32] }:$src0_mods, ?:{ *:[f32] }:$src0, ?:{ *:[i32] }:$src1_mods, ?:{ *:[f32] }:$src1, ?:{ *:[i32] }:$src2_mods, ?:{ *:[f32] }:$src2, 0:{ *:[i1] }, 0:{ *:[i32] })
        GIR_BuildMI, /*InsnID*/0, /*Opcode*/GIMT_Encode2(AMDGPU::V_MED3_F32_e64),
        GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/0, // DstI[vdst]
        GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/1, // src0_mods
        GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/0, // src0
        GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(1), /*SubOperand*/1, // src1_mods
        GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(1), /*SubOperand*/0, // src1
        GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(2), /*SubOperand*/1, // src2_mods
        GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(2), /*SubOperand*/0, // src2
        GIR_AddImm8, /*InsnID*/0, /*Imm*/0,
        GIR_AddImm8, /*InsnID*/0, /*Imm*/0,
        GIR_ConstrainSelectedInstOperands, /*InsnID*/0,
        GIR_EraseFromParent, /*InsnID*/0,
        // GIR_Coverage, 10157,
        GIR_Done,
      // Label 4672: @316246
      GIM_Try, /*On fail goto*//*Label 4673*/ GIMT_Encode4(316386), // Rule ID 10158 //
        GIM_CheckRegBankForClass, /*MI*/0, /*Op*/0, /*RC*/GIMT_Encode2(AMDGPU::VGPR_32RegClassID),
        GIM_RecordInsn, /*DefineMI*/1, /*MI*/0, /*OpIdx*/1, // MIs[1]
        GIM_CheckOpcode, /*MI*/1, GIMT_Encode2(TargetOpcode::G_FMINNUM),
        GIM_CheckType, /*MI*/1, /*Op*/1, /*Type*/GILLT_s32,
        GIM_CheckType, /*MI*/1, /*Op*/2, /*Type*/GILLT_s32,
        GIM_RecordInsn, /*DefineMI*/2, /*MI*/1, /*OpIdx*/1, // MIs[2]
        GIM_CheckOpcode, /*MI*/2, GIMT_Encode2(TargetOpcode::G_FMAXNUM_IEEE),
        GIM_CheckType, /*MI*/2, /*Op*/1, /*Type*/GILLT_s32,
        GIM_CheckType, /*MI*/2, /*Op*/2, /*Type*/GILLT_s32,
        GIM_RecordInsn, /*DefineMI*/3, /*MI*/0, /*OpIdx*/2, // MIs[3]
        GIM_CheckOpcode, /*MI*/3, GIMT_Encode2(TargetOpcode::G_FMINNUM_IEEE),
        // MIs[3] VOP3Mods:src1:src1_mods
        GIM_CheckIsSameOperand, /*MI*/3, /*OpIdx*/1, /*OtherMI*/2, /*OtherOpIdx*/2,
        // MIs[3] VOP3Mods:src0:src0_mods
        GIM_CheckIsSameOperand, /*MI*/3, /*OpIdx*/2, /*OtherMI*/2, /*OtherOpIdx*/1,
        GIM_CheckCxxInsnPredicate, /*MI*/0, /*FnId*/GIMT_Encode2(GICXXPred_MI_Predicate_fmaxnum_like_nnan),
        GIM_CheckIsSafeToFold, /*InsnID*/1,
        GIM_CheckIsSafeToFold, /*InsnID*/2,
        GIM_CheckIsSafeToFold, /*InsnID*/3,
        GIM_CheckComplexPattern, /*MI*/1, /*Op*/2, /*Renderer*/GIMT_Encode2(2), GIMT_Encode2(GICP_gi_vop3mods),
        GIM_CheckComplexPattern, /*MI*/2, /*Op*/1, /*Renderer*/GIMT_Encode2(0), GIMT_Encode2(GICP_gi_vop3mods),
        GIM_CheckComplexPattern, /*MI*/2, /*Op*/2, /*Renderer*/GIMT_Encode2(1), GIMT_Encode2(GICP_gi_vop3mods),
        // (fmaxnum:{ *:[f32] } (fminnum:{ *:[f32] } (fmaxnum_ieee:{ *:[f32] } (VOP3Mods:{ *:[f32] } f32:{ *:[f32] }:$src0, i32:{ *:[i32] }:$src0_mods), (VOP3Mods:{ *:[f32] } f32:{ *:[f32] }:$src1, i32:{ *:[i32] }:$src1_mods)), (VOP3Mods:{ *:[f32] } f32:{ *:[f32] }:$src2, i32:{ *:[i32] }:$src2_mods)), (fminnum_ieee:{ *:[f32] } (VOP3Mods:{ *:[f32] } f32:{ *:[f32] }:$src1, i32:{ *:[i32] }:$src1_mods), (VOP3Mods:{ *:[f32] } f32:{ *:[f32] }:$src0, i32:{ *:[i32] }:$src0_mods)))<<P:Predicate_fmaxnum_like_nnan>>  =>  (V_MED3_F32_e64:{ *:[f32] } ?:{ *:[i32] }:$src0_mods, ?:{ *:[f32] }:$src0, ?:{ *:[i32] }:$src1_mods, ?:{ *:[f32] }:$src1, ?:{ *:[i32] }:$src2_mods, ?:{ *:[f32] }:$src2, 0:{ *:[i1] }, 0:{ *:[i32] })
        GIR_BuildMI, /*InsnID*/0, /*Opcode*/GIMT_Encode2(AMDGPU::V_MED3_F32_e64),
        GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/0, // DstI[vdst]
        GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/1, // src0_mods
        GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/0, // src0
        GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(1), /*SubOperand*/1, // src1_mods
        GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(1), /*SubOperand*/0, // src1
        GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(2), /*SubOperand*/1, // src2_mods
        GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(2), /*SubOperand*/0, // src2
        GIR_AddImm8, /*InsnID*/0, /*Imm*/0,
        GIR_AddImm8, /*InsnID*/0, /*Imm*/0,
        GIR_ConstrainSelectedInstOperands, /*InsnID*/0,
        GIR_EraseFromParent, /*InsnID*/0,
        // GIR_Coverage, 10158,
        GIR_Done,
      // Label 4673: @316386
      GIM_Try, /*On fail goto*//*Label 4674*/ GIMT_Encode4(316526), // Rule ID 10159 //
        GIM_CheckRegBankForClass, /*MI*/0, /*Op*/0, /*RC*/GIMT_Encode2(AMDGPU::VGPR_32RegClassID),
        GIM_RecordInsn, /*DefineMI*/1, /*MI*/0, /*OpIdx*/1, // MIs[1]
        GIM_CheckOpcode, /*MI*/1, GIMT_Encode2(TargetOpcode::G_FMINNUM),
        GIM_CheckType, /*MI*/1, /*Op*/1, /*Type*/GILLT_s32,
        GIM_CheckType, /*MI*/1, /*Op*/2, /*Type*/GILLT_s32,
        GIM_RecordInsn, /*DefineMI*/2, /*MI*/1, /*OpIdx*/1, // MIs[2]
        GIM_CheckOpcode, /*MI*/2, GIMT_Encode2(TargetOpcode::G_FMAXNUM_IEEE),
        GIM_CheckType, /*MI*/2, /*Op*/1, /*Type*/GILLT_s32,
        GIM_CheckType, /*MI*/2, /*Op*/2, /*Type*/GILLT_s32,
        GIM_RecordInsn, /*DefineMI*/3, /*MI*/0, /*OpIdx*/2, // MIs[3]
        GIM_CheckOpcode, /*MI*/3, GIMT_Encode2(TargetOpcode::G_FMINNUM_IEEE),
        // MIs[3] VOP3Mods:src0:src0_mods
        GIM_CheckIsSameOperand, /*MI*/3, /*OpIdx*/1, /*OtherMI*/2, /*OtherOpIdx*/2,
        // MIs[3] VOP3Mods:src1:src1_mods
        GIM_CheckIsSameOperand, /*MI*/3, /*OpIdx*/2, /*OtherMI*/2, /*OtherOpIdx*/1,
        GIM_CheckCxxInsnPredicate, /*MI*/0, /*FnId*/GIMT_Encode2(GICXXPred_MI_Predicate_fmaxnum_like_nnan),
        GIM_CheckIsSafeToFold, /*InsnID*/1,
        GIM_CheckIsSafeToFold, /*InsnID*/2,
        GIM_CheckIsSafeToFold, /*InsnID*/3,
        GIM_CheckComplexPattern, /*MI*/1, /*Op*/2, /*Renderer*/GIMT_Encode2(2), GIMT_Encode2(GICP_gi_vop3mods),
        GIM_CheckComplexPattern, /*MI*/2, /*Op*/1, /*Renderer*/GIMT_Encode2(0), GIMT_Encode2(GICP_gi_vop3mods),
        GIM_CheckComplexPattern, /*MI*/2, /*Op*/2, /*Renderer*/GIMT_Encode2(1), GIMT_Encode2(GICP_gi_vop3mods),
        // (fmaxnum:{ *:[f32] } (fminnum:{ *:[f32] } (fmaxnum_ieee:{ *:[f32] } (VOP3Mods:{ *:[f32] } f32:{ *:[f32] }:$src1, i32:{ *:[i32] }:$src1_mods), (VOP3Mods:{ *:[f32] } f32:{ *:[f32] }:$src0, i32:{ *:[i32] }:$src0_mods)), (VOP3Mods:{ *:[f32] } f32:{ *:[f32] }:$src2, i32:{ *:[i32] }:$src2_mods)), (fminnum_ieee:{ *:[f32] } (VOP3Mods:{ *:[f32] } f32:{ *:[f32] }:$src0, i32:{ *:[i32] }:$src0_mods), (VOP3Mods:{ *:[f32] } f32:{ *:[f32] }:$src1, i32:{ *:[i32] }:$src1_mods)))<<P:Predicate_fmaxnum_like_nnan>>  =>  (V_MED3_F32_e64:{ *:[f32] } ?:{ *:[i32] }:$src0_mods, ?:{ *:[f32] }:$src0, ?:{ *:[i32] }:$src1_mods, ?:{ *:[f32] }:$src1, ?:{ *:[i32] }:$src2_mods, ?:{ *:[f32] }:$src2, 0:{ *:[i1] }, 0:{ *:[i32] })
        GIR_BuildMI, /*InsnID*/0, /*Opcode*/GIMT_Encode2(AMDGPU::V_MED3_F32_e64),
        GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/0, // DstI[vdst]
        GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(1), /*SubOperand*/1, // src0_mods
        GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(1), /*SubOperand*/0, // src0
        GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/1, // src1_mods
        GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/0, // src1
        GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(2), /*SubOperand*/1, // src2_mods
        GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(2), /*SubOperand*/0, // src2
        GIR_AddImm8, /*InsnID*/0, /*Imm*/0,
        GIR_AddImm8, /*InsnID*/0, /*Imm*/0,
        GIR_ConstrainSelectedInstOperands, /*InsnID*/0,
        GIR_EraseFromParent, /*InsnID*/0,
        // GIR_Coverage, 10159,
        GIR_Done,
      // Label 4674: @316526
      GIM_Try, /*On fail goto*//*Label 4675*/ GIMT_Encode4(316666), // Rule ID 10160 //
        GIM_CheckRegBankForClass, /*MI*/0, /*Op*/0, /*RC*/GIMT_Encode2(AMDGPU::VGPR_32RegClassID),
        GIM_RecordInsn, /*DefineMI*/1, /*MI*/0, /*OpIdx*/1, // MIs[1]
        GIM_CheckOpcode, /*MI*/1, GIMT_Encode2(TargetOpcode::G_FMINNUM),
        GIM_CheckType, /*MI*/1, /*Op*/1, /*Type*/GILLT_s32,
        GIM_CheckType, /*MI*/1, /*Op*/2, /*Type*/GILLT_s32,
        GIM_RecordInsn, /*DefineMI*/2, /*MI*/1, /*OpIdx*/1, // MIs[2]
        GIM_CheckOpcode, /*MI*/2, GIMT_Encode2(TargetOpcode::G_FMAXNUM_IEEE),
        GIM_CheckType, /*MI*/2, /*Op*/1, /*Type*/GILLT_s32,
        GIM_CheckType, /*MI*/2, /*Op*/2, /*Type*/GILLT_s32,
        GIM_RecordInsn, /*DefineMI*/3, /*MI*/0, /*OpIdx*/2, // MIs[3]
        GIM_CheckOpcode, /*MI*/3, GIMT_Encode2(TargetOpcode::G_FMINNUM_IEEE),
        // MIs[3] VOP3Mods:src1:src1_mods
        GIM_CheckIsSameOperand, /*MI*/3, /*OpIdx*/1, /*OtherMI*/2, /*OtherOpIdx*/1,
        // MIs[3] VOP3Mods:src0:src0_mods
        GIM_CheckIsSameOperand, /*MI*/3, /*OpIdx*/2, /*OtherMI*/2, /*OtherOpIdx*/2,
        GIM_CheckCxxInsnPredicate, /*MI*/0, /*FnId*/GIMT_Encode2(GICXXPred_MI_Predicate_fmaxnum_like_nnan),
        GIM_CheckIsSafeToFold, /*InsnID*/1,
        GIM_CheckIsSafeToFold, /*InsnID*/2,
        GIM_CheckIsSafeToFold, /*InsnID*/3,
        GIM_CheckComplexPattern, /*MI*/1, /*Op*/2, /*Renderer*/GIMT_Encode2(2), GIMT_Encode2(GICP_gi_vop3mods),
        GIM_CheckComplexPattern, /*MI*/2, /*Op*/1, /*Renderer*/GIMT_Encode2(0), GIMT_Encode2(GICP_gi_vop3mods),
        GIM_CheckComplexPattern, /*MI*/2, /*Op*/2, /*Renderer*/GIMT_Encode2(1), GIMT_Encode2(GICP_gi_vop3mods),
        // (fmaxnum:{ *:[f32] } (fminnum:{ *:[f32] } (fmaxnum_ieee:{ *:[f32] } (VOP3Mods:{ *:[f32] } f32:{ *:[f32] }:$src1, i32:{ *:[i32] }:$src1_mods), (VOP3Mods:{ *:[f32] } f32:{ *:[f32] }:$src0, i32:{ *:[i32] }:$src0_mods)), (VOP3Mods:{ *:[f32] } f32:{ *:[f32] }:$src2, i32:{ *:[i32] }:$src2_mods)), (fminnum_ieee:{ *:[f32] } (VOP3Mods:{ *:[f32] } f32:{ *:[f32] }:$src1, i32:{ *:[i32] }:$src1_mods), (VOP3Mods:{ *:[f32] } f32:{ *:[f32] }:$src0, i32:{ *:[i32] }:$src0_mods)))<<P:Predicate_fmaxnum_like_nnan>>  =>  (V_MED3_F32_e64:{ *:[f32] } ?:{ *:[i32] }:$src0_mods, ?:{ *:[f32] }:$src0, ?:{ *:[i32] }:$src1_mods, ?:{ *:[f32] }:$src1, ?:{ *:[i32] }:$src2_mods, ?:{ *:[f32] }:$src2, 0:{ *:[i1] }, 0:{ *:[i32] })
        GIR_BuildMI, /*InsnID*/0, /*Opcode*/GIMT_Encode2(AMDGPU::V_MED3_F32_e64),
        GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/0, // DstI[vdst]
        GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(1), /*SubOperand*/1, // src0_mods
        GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(1), /*SubOperand*/0, // src0
        GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/1, // src1_mods
        GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/0, // src1
        GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(2), /*SubOperand*/1, // src2_mods
        GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(2), /*SubOperand*/0, // src2
        GIR_AddImm8, /*InsnID*/0, /*Imm*/0,
        GIR_AddImm8, /*InsnID*/0, /*Imm*/0,
        GIR_ConstrainSelectedInstOperands, /*InsnID*/0,
        GIR_EraseFromParent, /*InsnID*/0,
        // GIR_Coverage, 10160,
        GIR_Done,
      // Label 4675: @316666
      GIM_Try, /*On fail goto*//*Label 4676*/ GIMT_Encode4(316806), // Rule ID 10166 //
        GIM_CheckRegBankForClass, /*MI*/0, /*Op*/0, /*RC*/GIMT_Encode2(AMDGPU::VGPR_32RegClassID),
        GIM_RecordInsn, /*DefineMI*/1, /*MI*/0, /*OpIdx*/1, // MIs[1]
        GIM_CheckOpcode, /*MI*/1, GIMT_Encode2(TargetOpcode::G_FMINNUM_IEEE),
        GIM_CheckType, /*MI*/1, /*Op*/1, /*Type*/GILLT_s32,
        GIM_CheckType, /*MI*/1, /*Op*/2, /*Type*/GILLT_s32,
        GIM_RecordInsn, /*DefineMI*/2, /*MI*/0, /*OpIdx*/2, // MIs[2]
        GIM_CheckOpcode, /*MI*/2, GIMT_Encode2(TargetOpcode::G_FMINNUM),
        GIM_CheckType, /*MI*/2, /*Op*/1, /*Type*/GILLT_s32,
        GIM_CheckType, /*MI*/2, /*Op*/2, /*Type*/GILLT_s32,
        GIM_RecordInsn, /*DefineMI*/3, /*MI*/2, /*OpIdx*/2, // MIs[3]
        GIM_CheckOpcode, /*MI*/3, GIMT_Encode2(TargetOpcode::G_FMAXNUM),
        // MIs[3] VOP3Mods:src0:src0_mods
        GIM_CheckIsSameOperand, /*MI*/3, /*OpIdx*/1, /*OtherMI*/1, /*OtherOpIdx*/1,
        // MIs[3] VOP3Mods:src1:src1_mods
        GIM_CheckIsSameOperand, /*MI*/3, /*OpIdx*/2, /*OtherMI*/1, /*OtherOpIdx*/2,
        GIM_CheckCxxInsnPredicate, /*MI*/0, /*FnId*/GIMT_Encode2(GICXXPred_MI_Predicate_fmaxnum_like_nnan),
        GIM_CheckIsSafeToFold, /*InsnID*/1,
        GIM_CheckIsSafeToFold, /*InsnID*/2,
        GIM_CheckIsSafeToFold, /*InsnID*/3,
        GIM_CheckComplexPattern, /*MI*/1, /*Op*/1, /*Renderer*/GIMT_Encode2(0), GIMT_Encode2(GICP_gi_vop3mods),
        GIM_CheckComplexPattern, /*MI*/1, /*Op*/2, /*Renderer*/GIMT_Encode2(1), GIMT_Encode2(GICP_gi_vop3mods),
        GIM_CheckComplexPattern, /*MI*/2, /*Op*/1, /*Renderer*/GIMT_Encode2(2), GIMT_Encode2(GICP_gi_vop3mods),
        // (fmaxnum:{ *:[f32] } (fminnum_ieee:{ *:[f32] } (VOP3Mods:{ *:[f32] } f32:{ *:[f32] }:$src0, i32:{ *:[i32] }:$src0_mods), (VOP3Mods:{ *:[f32] } f32:{ *:[f32] }:$src1, i32:{ *:[i32] }:$src1_mods)), (fminnum:{ *:[f32] } (VOP3Mods:{ *:[f32] } f32:{ *:[f32] }:$src2, i32:{ *:[i32] }:$src2_mods), (fmaxnum:{ *:[f32] } (VOP3Mods:{ *:[f32] } f32:{ *:[f32] }:$src0, i32:{ *:[i32] }:$src0_mods), (VOP3Mods:{ *:[f32] } f32:{ *:[f32] }:$src1, i32:{ *:[i32] }:$src1_mods))))<<P:Predicate_fmaxnum_like_nnan>>  =>  (V_MED3_F32_e64:{ *:[f32] } ?:{ *:[i32] }:$src0_mods, ?:{ *:[f32] }:$src0, ?:{ *:[i32] }:$src1_mods, ?:{ *:[f32] }:$src1, ?:{ *:[i32] }:$src2_mods, ?:{ *:[f32] }:$src2, 0:{ *:[i1] }, 0:{ *:[i32] })
        GIR_BuildMI, /*InsnID*/0, /*Opcode*/GIMT_Encode2(AMDGPU::V_MED3_F32_e64),
        GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/0, // DstI[vdst]
        GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/1, // src0_mods
        GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/0, // src0
        GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(1), /*SubOperand*/1, // src1_mods
        GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(1), /*SubOperand*/0, // src1
        GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(2), /*SubOperand*/1, // src2_mods
        GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(2), /*SubOperand*/0, // src2
        GIR_AddImm8, /*InsnID*/0, /*Imm*/0,
        GIR_AddImm8, /*InsnID*/0, /*Imm*/0,
        GIR_ConstrainSelectedInstOperands, /*InsnID*/0,
        GIR_EraseFromParent, /*InsnID*/0,
        // GIR_Coverage, 10166,
        GIR_Done,
      // Label 4676: @316806
      GIM_Try, /*On fail goto*//*Label 4677*/ GIMT_Encode4(316946), // Rule ID 10167 //
        GIM_CheckRegBankForClass, /*MI*/0, /*Op*/0, /*RC*/GIMT_Encode2(AMDGPU::VGPR_32RegClassID),
        GIM_RecordInsn, /*DefineMI*/1, /*MI*/0, /*OpIdx*/1, // MIs[1]
        GIM_CheckOpcode, /*MI*/1, GIMT_Encode2(TargetOpcode::G_FMINNUM_IEEE),
        GIM_CheckType, /*MI*/1, /*Op*/1, /*Type*/GILLT_s32,
        GIM_CheckType, /*MI*/1, /*Op*/2, /*Type*/GILLT_s32,
        GIM_RecordInsn, /*DefineMI*/2, /*MI*/0, /*OpIdx*/2, // MIs[2]
        GIM_CheckOpcode, /*MI*/2, GIMT_Encode2(TargetOpcode::G_FMINNUM),
        GIM_CheckType, /*MI*/2, /*Op*/1, /*Type*/GILLT_s32,
        GIM_CheckType, /*MI*/2, /*Op*/2, /*Type*/GILLT_s32,
        GIM_RecordInsn, /*DefineMI*/3, /*MI*/2, /*OpIdx*/2, // MIs[3]
        GIM_CheckOpcode, /*MI*/3, GIMT_Encode2(TargetOpcode::G_FMAXNUM),
        // MIs[3] VOP3Mods:src1:src1_mods
        GIM_CheckIsSameOperand, /*MI*/3, /*OpIdx*/1, /*OtherMI*/1, /*OtherOpIdx*/2,
        // MIs[3] VOP3Mods:src0:src0_mods
        GIM_CheckIsSameOperand, /*MI*/3, /*OpIdx*/2, /*OtherMI*/1, /*OtherOpIdx*/1,
        GIM_CheckCxxInsnPredicate, /*MI*/0, /*FnId*/GIMT_Encode2(GICXXPred_MI_Predicate_fmaxnum_like_nnan),
        GIM_CheckIsSafeToFold, /*InsnID*/1,
        GIM_CheckIsSafeToFold, /*InsnID*/2,
        GIM_CheckIsSafeToFold, /*InsnID*/3,
        GIM_CheckComplexPattern, /*MI*/1, /*Op*/1, /*Renderer*/GIMT_Encode2(0), GIMT_Encode2(GICP_gi_vop3mods),
        GIM_CheckComplexPattern, /*MI*/1, /*Op*/2, /*Renderer*/GIMT_Encode2(1), GIMT_Encode2(GICP_gi_vop3mods),
        GIM_CheckComplexPattern, /*MI*/2, /*Op*/1, /*Renderer*/GIMT_Encode2(2), GIMT_Encode2(GICP_gi_vop3mods),
        // (fmaxnum:{ *:[f32] } (fminnum_ieee:{ *:[f32] } (VOP3Mods:{ *:[f32] } f32:{ *:[f32] }:$src0, i32:{ *:[i32] }:$src0_mods), (VOP3Mods:{ *:[f32] } f32:{ *:[f32] }:$src1, i32:{ *:[i32] }:$src1_mods)), (fminnum:{ *:[f32] } (VOP3Mods:{ *:[f32] } f32:{ *:[f32] }:$src2, i32:{ *:[i32] }:$src2_mods), (fmaxnum:{ *:[f32] } (VOP3Mods:{ *:[f32] } f32:{ *:[f32] }:$src1, i32:{ *:[i32] }:$src1_mods), (VOP3Mods:{ *:[f32] } f32:{ *:[f32] }:$src0, i32:{ *:[i32] }:$src0_mods))))<<P:Predicate_fmaxnum_like_nnan>>  =>  (V_MED3_F32_e64:{ *:[f32] } ?:{ *:[i32] }:$src0_mods, ?:{ *:[f32] }:$src0, ?:{ *:[i32] }:$src1_mods, ?:{ *:[f32] }:$src1, ?:{ *:[i32] }:$src2_mods, ?:{ *:[f32] }:$src2, 0:{ *:[i1] }, 0:{ *:[i32] })
        GIR_BuildMI, /*InsnID*/0, /*Opcode*/GIMT_Encode2(AMDGPU::V_MED3_F32_e64),
        GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/0, // DstI[vdst]
        GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/1, // src0_mods
        GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/0, // src0
        GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(1), /*SubOperand*/1, // src1_mods
        GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(1), /*SubOperand*/0, // src1
        GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(2), /*SubOperand*/1, // src2_mods
        GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(2), /*SubOperand*/0, // src2
        GIR_AddImm8, /*InsnID*/0, /*Imm*/0,
        GIR_AddImm8, /*InsnID*/0, /*Imm*/0,
        GIR_ConstrainSelectedInstOperands, /*InsnID*/0,
        GIR_EraseFromParent, /*InsnID*/0,
        // GIR_Coverage, 10167,
        GIR_Done,
      // Label 4677: @316946
      GIM_Try, /*On fail goto*//*Label 4678*/ GIMT_Encode4(317086), // Rule ID 10170 //
        GIM_CheckRegBankForClass, /*MI*/0, /*Op*/0, /*RC*/GIMT_Encode2(AMDGPU::VGPR_32RegClassID),
        GIM_RecordInsn, /*DefineMI*/1, /*MI*/0, /*OpIdx*/1, // MIs[1]
        GIM_CheckOpcode, /*MI*/1, GIMT_Encode2(TargetOpcode::G_FMINNUM_IEEE),
        GIM_CheckType, /*MI*/1, /*Op*/1, /*Type*/GILLT_s32,
        GIM_CheckType, /*MI*/1, /*Op*/2, /*Type*/GILLT_s32,
        GIM_RecordInsn, /*DefineMI*/2, /*MI*/0, /*OpIdx*/2, // MIs[2]
        GIM_CheckOpcode, /*MI*/2, GIMT_Encode2(TargetOpcode::G_FMINNUM),
        GIM_CheckType, /*MI*/2, /*Op*/1, /*Type*/GILLT_s32,
        GIM_CheckType, /*MI*/2, /*Op*/2, /*Type*/GILLT_s32,
        GIM_RecordInsn, /*DefineMI*/3, /*MI*/2, /*OpIdx*/2, // MIs[3]
        GIM_CheckOpcode, /*MI*/3, GIMT_Encode2(TargetOpcode::G_FMAXNUM),
        // MIs[3] VOP3Mods:src0:src0_mods
        GIM_CheckIsSameOperand, /*MI*/3, /*OpIdx*/1, /*OtherMI*/1, /*OtherOpIdx*/2,
        // MIs[3] VOP3Mods:src1:src1_mods
        GIM_CheckIsSameOperand, /*MI*/3, /*OpIdx*/2, /*OtherMI*/1, /*OtherOpIdx*/1,
        GIM_CheckCxxInsnPredicate, /*MI*/0, /*FnId*/GIMT_Encode2(GICXXPred_MI_Predicate_fmaxnum_like_nnan),
        GIM_CheckIsSafeToFold, /*InsnID*/1,
        GIM_CheckIsSafeToFold, /*InsnID*/2,
        GIM_CheckIsSafeToFold, /*InsnID*/3,
        GIM_CheckComplexPattern, /*MI*/1, /*Op*/1, /*Renderer*/GIMT_Encode2(0), GIMT_Encode2(GICP_gi_vop3mods),
        GIM_CheckComplexPattern, /*MI*/1, /*Op*/2, /*Renderer*/GIMT_Encode2(1), GIMT_Encode2(GICP_gi_vop3mods),
        GIM_CheckComplexPattern, /*MI*/2, /*Op*/1, /*Renderer*/GIMT_Encode2(2), GIMT_Encode2(GICP_gi_vop3mods),
        // (fmaxnum:{ *:[f32] } (fminnum_ieee:{ *:[f32] } (VOP3Mods:{ *:[f32] } f32:{ *:[f32] }:$src1, i32:{ *:[i32] }:$src1_mods), (VOP3Mods:{ *:[f32] } f32:{ *:[f32] }:$src0, i32:{ *:[i32] }:$src0_mods)), (fminnum:{ *:[f32] } (VOP3Mods:{ *:[f32] } f32:{ *:[f32] }:$src2, i32:{ *:[i32] }:$src2_mods), (fmaxnum:{ *:[f32] } (VOP3Mods:{ *:[f32] } f32:{ *:[f32] }:$src0, i32:{ *:[i32] }:$src0_mods), (VOP3Mods:{ *:[f32] } f32:{ *:[f32] }:$src1, i32:{ *:[i32] }:$src1_mods))))<<P:Predicate_fmaxnum_like_nnan>>  =>  (V_MED3_F32_e64:{ *:[f32] } ?:{ *:[i32] }:$src0_mods, ?:{ *:[f32] }:$src0, ?:{ *:[i32] }:$src1_mods, ?:{ *:[f32] }:$src1, ?:{ *:[i32] }:$src2_mods, ?:{ *:[f32] }:$src2, 0:{ *:[i1] }, 0:{ *:[i32] })
        GIR_BuildMI, /*InsnID*/0, /*Opcode*/GIMT_Encode2(AMDGPU::V_MED3_F32_e64),
        GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/0, // DstI[vdst]
        GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(1), /*SubOperand*/1, // src0_mods
        GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(1), /*SubOperand*/0, // src0
        GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/1, // src1_mods
        GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/0, // src1
        GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(2), /*SubOperand*/1, // src2_mods
        GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(2), /*SubOperand*/0, // src2
        GIR_AddImm8, /*InsnID*/0, /*Imm*/0,
        GIR_AddImm8, /*InsnID*/0, /*Imm*/0,
        GIR_ConstrainSelectedInstOperands, /*InsnID*/0,
        GIR_EraseFromParent, /*InsnID*/0,
        // GIR_Coverage, 10170,
        GIR_Done,
      // Label 4678: @317086
      GIM_Try, /*On fail goto*//*Label 4679*/ GIMT_Encode4(317226), // Rule ID 10171 //
        GIM_CheckRegBankForClass, /*MI*/0, /*Op*/0, /*RC*/GIMT_Encode2(AMDGPU::VGPR_32RegClassID),
        GIM_RecordInsn, /*DefineMI*/1, /*MI*/0, /*OpIdx*/1, // MIs[1]
        GIM_CheckOpcode, /*MI*/1, GIMT_Encode2(TargetOpcode::G_FMINNUM_IEEE),
        GIM_CheckType, /*MI*/1, /*Op*/1, /*Type*/GILLT_s32,
        GIM_CheckType, /*MI*/1, /*Op*/2, /*Type*/GILLT_s32,
        GIM_RecordInsn, /*DefineMI*/2, /*MI*/0, /*OpIdx*/2, // MIs[2]
        GIM_CheckOpcode, /*MI*/2, GIMT_Encode2(TargetOpcode::G_FMINNUM),
        GIM_CheckType, /*MI*/2, /*Op*/1, /*Type*/GILLT_s32,
        GIM_CheckType, /*MI*/2, /*Op*/2, /*Type*/GILLT_s32,
        GIM_RecordInsn, /*DefineMI*/3, /*MI*/2, /*OpIdx*/2, // MIs[3]
        GIM_CheckOpcode, /*MI*/3, GIMT_Encode2(TargetOpcode::G_FMAXNUM),
        // MIs[3] VOP3Mods:src1:src1_mods
        GIM_CheckIsSameOperand, /*MI*/3, /*OpIdx*/1, /*OtherMI*/1, /*OtherOpIdx*/1,
        // MIs[3] VOP3Mods:src0:src0_mods
        GIM_CheckIsSameOperand, /*MI*/3, /*OpIdx*/2, /*OtherMI*/1, /*OtherOpIdx*/2,
        GIM_CheckCxxInsnPredicate, /*MI*/0, /*FnId*/GIMT_Encode2(GICXXPred_MI_Predicate_fmaxnum_like_nnan),
        GIM_CheckIsSafeToFold, /*InsnID*/1,
        GIM_CheckIsSafeToFold, /*InsnID*/2,
        GIM_CheckIsSafeToFold, /*InsnID*/3,
        GIM_CheckComplexPattern, /*MI*/1, /*Op*/1, /*Renderer*/GIMT_Encode2(0), GIMT_Encode2(GICP_gi_vop3mods),
        GIM_CheckComplexPattern, /*MI*/1, /*Op*/2, /*Renderer*/GIMT_Encode2(1), GIMT_Encode2(GICP_gi_vop3mods),
        GIM_CheckComplexPattern, /*MI*/2, /*Op*/1, /*Renderer*/GIMT_Encode2(2), GIMT_Encode2(GICP_gi_vop3mods),
        // (fmaxnum:{ *:[f32] } (fminnum_ieee:{ *:[f32] } (VOP3Mods:{ *:[f32] } f32:{ *:[f32] }:$src1, i32:{ *:[i32] }:$src1_mods), (VOP3Mods:{ *:[f32] } f32:{ *:[f32] }:$src0, i32:{ *:[i32] }:$src0_mods)), (fminnum:{ *:[f32] } (VOP3Mods:{ *:[f32] } f32:{ *:[f32] }:$src2, i32:{ *:[i32] }:$src2_mods), (fmaxnum:{ *:[f32] } (VOP3Mods:{ *:[f32] } f32:{ *:[f32] }:$src1, i32:{ *:[i32] }:$src1_mods), (VOP3Mods:{ *:[f32] } f32:{ *:[f32] }:$src0, i32:{ *:[i32] }:$src0_mods))))<<P:Predicate_fmaxnum_like_nnan>>  =>  (V_MED3_F32_e64:{ *:[f32] } ?:{ *:[i32] }:$src0_mods, ?:{ *:[f32] }:$src0, ?:{ *:[i32] }:$src1_mods, ?:{ *:[f32] }:$src1, ?:{ *:[i32] }:$src2_mods, ?:{ *:[f32] }:$src2, 0:{ *:[i1] }, 0:{ *:[i32] })
        GIR_BuildMI, /*InsnID*/0, /*Opcode*/GIMT_Encode2(AMDGPU::V_MED3_F32_e64),
        GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/0, // DstI[vdst]
        GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(1), /*SubOperand*/1, // src0_mods
        GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(1), /*SubOperand*/0, // src0
        GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/1, // src1_mods
        GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/0, // src1
        GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(2), /*SubOperand*/1, // src2_mods
        GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(2), /*SubOperand*/0, // src2
        GIR_AddImm8, /*InsnID*/0, /*Imm*/0,
        GIR_AddImm8, /*InsnID*/0, /*Imm*/0,
        GIR_ConstrainSelectedInstOperands, /*InsnID*/0,
        GIR_EraseFromParent, /*InsnID*/0,
        // GIR_Coverage, 10171,
        GIR_Done,
      // Label 4679: @317226
      GIM_Try, /*On fail goto*//*Label 4680*/ GIMT_Encode4(317366), // Rule ID 10151 //
        GIM_CheckRegBankForClass, /*MI*/0, /*Op*/0, /*RC*/GIMT_Encode2(AMDGPU::VGPR_32RegClassID),
        GIM_RecordInsn, /*DefineMI*/1, /*MI*/0, /*OpIdx*/1, // MIs[1]
        GIM_CheckOpcode, /*MI*/1, GIMT_Encode2(TargetOpcode::G_FMINNUM_IEEE),
        GIM_CheckType, /*MI*/1, /*Op*/1, /*Type*/GILLT_s32,
        GIM_CheckType, /*MI*/1, /*Op*/2, /*Type*/GILLT_s32,
        GIM_RecordInsn, /*DefineMI*/2, /*MI*/0, /*OpIdx*/2, // MIs[2]
        GIM_CheckOpcode, /*MI*/2, GIMT_Encode2(TargetOpcode::G_FMINNUM),
        GIM_CheckType, /*MI*/2, /*Op*/1, /*Type*/GILLT_s32,
        GIM_CheckType, /*MI*/2, /*Op*/2, /*Type*/GILLT_s32,
        GIM_RecordInsn, /*DefineMI*/3, /*MI*/2, /*OpIdx*/2, // MIs[3]
        GIM_CheckOpcode, /*MI*/3, GIMT_Encode2(TargetOpcode::G_FMAXNUM_IEEE),
        // MIs[3] VOP3Mods:src0:src0_mods
        GIM_CheckIsSameOperand, /*MI*/3, /*OpIdx*/1, /*OtherMI*/1, /*OtherOpIdx*/1,
        // MIs[3] VOP3Mods:src1:src1_mods
        GIM_CheckIsSameOperand, /*MI*/3, /*OpIdx*/2, /*OtherMI*/1, /*OtherOpIdx*/2,
        GIM_CheckCxxInsnPredicate, /*MI*/0, /*FnId*/GIMT_Encode2(GICXXPred_MI_Predicate_fmaxnum_like_nnan),
        GIM_CheckIsSafeToFold, /*InsnID*/1,
        GIM_CheckIsSafeToFold, /*InsnID*/2,
        GIM_CheckIsSafeToFold, /*InsnID*/3,
        GIM_CheckComplexPattern, /*MI*/1, /*Op*/1, /*Renderer*/GIMT_Encode2(0), GIMT_Encode2(GICP_gi_vop3mods),
        GIM_CheckComplexPattern, /*MI*/1, /*Op*/2, /*Renderer*/GIMT_Encode2(1), GIMT_Encode2(GICP_gi_vop3mods),
        GIM_CheckComplexPattern, /*MI*/2, /*Op*/1, /*Renderer*/GIMT_Encode2(2), GIMT_Encode2(GICP_gi_vop3mods),
        // (fmaxnum:{ *:[f32] } (fminnum_ieee:{ *:[f32] } (VOP3Mods:{ *:[f32] } f32:{ *:[f32] }:$src0, i32:{ *:[i32] }:$src0_mods), (VOP3Mods:{ *:[f32] } f32:{ *:[f32] }:$src1, i32:{ *:[i32] }:$src1_mods)), (fminnum:{ *:[f32] } (VOP3Mods:{ *:[f32] } f32:{ *:[f32] }:$src2, i32:{ *:[i32] }:$src2_mods), (fmaxnum_ieee:{ *:[f32] } (VOP3Mods:{ *:[f32] } f32:{ *:[f32] }:$src0, i32:{ *:[i32] }:$src0_mods), (VOP3Mods:{ *:[f32] } f32:{ *:[f32] }:$src1, i32:{ *:[i32] }:$src1_mods))))<<P:Predicate_fmaxnum_like_nnan>>  =>  (V_MED3_F32_e64:{ *:[f32] } ?:{ *:[i32] }:$src0_mods, ?:{ *:[f32] }:$src0, ?:{ *:[i32] }:$src1_mods, ?:{ *:[f32] }:$src1, ?:{ *:[i32] }:$src2_mods, ?:{ *:[f32] }:$src2, 0:{ *:[i1] }, 0:{ *:[i32] })
        GIR_BuildMI, /*InsnID*/0, /*Opcode*/GIMT_Encode2(AMDGPU::V_MED3_F32_e64),
        GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/0, // DstI[vdst]
        GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/1, // src0_mods
        GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/0, // src0
        GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(1), /*SubOperand*/1, // src1_mods
        GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(1), /*SubOperand*/0, // src1
        GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(2), /*SubOperand*/1, // src2_mods
        GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(2), /*SubOperand*/0, // src2
        GIR_AddImm8, /*InsnID*/0, /*Imm*/0,
        GIR_AddImm8, /*InsnID*/0, /*Imm*/0,
        GIR_ConstrainSelectedInstOperands, /*InsnID*/0,
        GIR_EraseFromParent, /*InsnID*/0,
        // GIR_Coverage, 10151,
        GIR_Done,
      // Label 4680: @317366
      GIM_Try, /*On fail goto*//*Label 4681*/ GIMT_Encode4(317506), // Rule ID 10152 //
        GIM_CheckRegBankForClass, /*MI*/0, /*Op*/0, /*RC*/GIMT_Encode2(AMDGPU::VGPR_32RegClassID),
        GIM_RecordInsn, /*DefineMI*/1, /*MI*/0, /*OpIdx*/1, // MIs[1]
        GIM_CheckOpcode, /*MI*/1, GIMT_Encode2(TargetOpcode::G_FMINNUM_IEEE),
        GIM_CheckType, /*MI*/1, /*Op*/1, /*Type*/GILLT_s32,
        GIM_CheckType, /*MI*/1, /*Op*/2, /*Type*/GILLT_s32,
        GIM_RecordInsn, /*DefineMI*/2, /*MI*/0, /*OpIdx*/2, // MIs[2]
        GIM_CheckOpcode, /*MI*/2, GIMT_Encode2(TargetOpcode::G_FMINNUM),
        GIM_CheckType, /*MI*/2, /*Op*/1, /*Type*/GILLT_s32,
        GIM_CheckType, /*MI*/2, /*Op*/2, /*Type*/GILLT_s32,
        GIM_RecordInsn, /*DefineMI*/3, /*MI*/2, /*OpIdx*/2, // MIs[3]
        GIM_CheckOpcode, /*MI*/3, GIMT_Encode2(TargetOpcode::G_FMAXNUM_IEEE),
        // MIs[3] VOP3Mods:src1:src1_mods
        GIM_CheckIsSameOperand, /*MI*/3, /*OpIdx*/1, /*OtherMI*/1, /*OtherOpIdx*/2,
        // MIs[3] VOP3Mods:src0:src0_mods
        GIM_CheckIsSameOperand, /*MI*/3, /*OpIdx*/2, /*OtherMI*/1, /*OtherOpIdx*/1,
        GIM_CheckCxxInsnPredicate, /*MI*/0, /*FnId*/GIMT_Encode2(GICXXPred_MI_Predicate_fmaxnum_like_nnan),
        GIM_CheckIsSafeToFold, /*InsnID*/1,
        GIM_CheckIsSafeToFold, /*InsnID*/2,
        GIM_CheckIsSafeToFold, /*InsnID*/3,
        GIM_CheckComplexPattern, /*MI*/1, /*Op*/1, /*Renderer*/GIMT_Encode2(0), GIMT_Encode2(GICP_gi_vop3mods),
        GIM_CheckComplexPattern, /*MI*/1, /*Op*/2, /*Renderer*/GIMT_Encode2(1), GIMT_Encode2(GICP_gi_vop3mods),
        GIM_CheckComplexPattern, /*MI*/2, /*Op*/1, /*Renderer*/GIMT_Encode2(2), GIMT_Encode2(GICP_gi_vop3mods),
        // (fmaxnum:{ *:[f32] } (fminnum_ieee:{ *:[f32] } (VOP3Mods:{ *:[f32] } f32:{ *:[f32] }:$src0, i32:{ *:[i32] }:$src0_mods), (VOP3Mods:{ *:[f32] } f32:{ *:[f32] }:$src1, i32:{ *:[i32] }:$src1_mods)), (fminnum:{ *:[f32] } (VOP3Mods:{ *:[f32] } f32:{ *:[f32] }:$src2, i32:{ *:[i32] }:$src2_mods), (fmaxnum_ieee:{ *:[f32] } (VOP3Mods:{ *:[f32] } f32:{ *:[f32] }:$src1, i32:{ *:[i32] }:$src1_mods), (VOP3Mods:{ *:[f32] } f32:{ *:[f32] }:$src0, i32:{ *:[i32] }:$src0_mods))))<<P:Predicate_fmaxnum_like_nnan>>  =>  (V_MED3_F32_e64:{ *:[f32] } ?:{ *:[i32] }:$src0_mods, ?:{ *:[f32] }:$src0, ?:{ *:[i32] }:$src1_mods, ?:{ *:[f32] }:$src1, ?:{ *:[i32] }:$src2_mods, ?:{ *:[f32] }:$src2, 0:{ *:[i1] }, 0:{ *:[i32] })
        GIR_BuildMI, /*InsnID*/0, /*Opcode*/GIMT_Encode2(AMDGPU::V_MED3_F32_e64),
        GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/0, // DstI[vdst]
        GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/1, // src0_mods
        GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/0, // src0
        GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(1), /*SubOperand*/1, // src1_mods
        GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(1), /*SubOperand*/0, // src1
        GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(2), /*SubOperand*/1, // src2_mods
        GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(2), /*SubOperand*/0, // src2
        GIR_AddImm8, /*InsnID*/0, /*Imm*/0,
        GIR_AddImm8, /*InsnID*/0, /*Imm*/0,
        GIR_ConstrainSelectedInstOperands, /*InsnID*/0,
        GIR_EraseFromParent, /*InsnID*/0,
        // GIR_Coverage, 10152,
        GIR_Done,
      // Label 4681: @317506
      GIM_Try, /*On fail goto*//*Label 4682*/ GIMT_Encode4(317646), // Rule ID 10155 //
        GIM_CheckRegBankForClass, /*MI*/0, /*Op*/0, /*RC*/GIMT_Encode2(AMDGPU::VGPR_32RegClassID),
        GIM_RecordInsn, /*DefineMI*/1, /*MI*/0, /*OpIdx*/1, // MIs[1]
        GIM_CheckOpcode, /*MI*/1, GIMT_Encode2(TargetOpcode::G_FMINNUM_IEEE),
        GIM_CheckType, /*MI*/1, /*Op*/1, /*Type*/GILLT_s32,
        GIM_CheckType, /*MI*/1, /*Op*/2, /*Type*/GILLT_s32,
        GIM_RecordInsn, /*DefineMI*/2, /*MI*/0, /*OpIdx*/2, // MIs[2]
        GIM_CheckOpcode, /*MI*/2, GIMT_Encode2(TargetOpcode::G_FMINNUM),
        GIM_CheckType, /*MI*/2, /*Op*/1, /*Type*/GILLT_s32,
        GIM_CheckType, /*MI*/2, /*Op*/2, /*Type*/GILLT_s32,
        GIM_RecordInsn, /*DefineMI*/3, /*MI*/2, /*OpIdx*/2, // MIs[3]
        GIM_CheckOpcode, /*MI*/3, GIMT_Encode2(TargetOpcode::G_FMAXNUM_IEEE),
        // MIs[3] VOP3Mods:src0:src0_mods
        GIM_CheckIsSameOperand, /*MI*/3, /*OpIdx*/1, /*OtherMI*/1, /*OtherOpIdx*/2,
        // MIs[3] VOP3Mods:src1:src1_mods
        GIM_CheckIsSameOperand, /*MI*/3, /*OpIdx*/2, /*OtherMI*/1, /*OtherOpIdx*/1,
        GIM_CheckCxxInsnPredicate, /*MI*/0, /*FnId*/GIMT_Encode2(GICXXPred_MI_Predicate_fmaxnum_like_nnan),
        GIM_CheckIsSafeToFold, /*InsnID*/1,
        GIM_CheckIsSafeToFold, /*InsnID*/2,
        GIM_CheckIsSafeToFold, /*InsnID*/3,
        GIM_CheckComplexPattern, /*MI*/1, /*Op*/1, /*Renderer*/GIMT_Encode2(0), GIMT_Encode2(GICP_gi_vop3mods),
        GIM_CheckComplexPattern, /*MI*/1, /*Op*/2, /*Renderer*/GIMT_Encode2(1), GIMT_Encode2(GICP_gi_vop3mods),
        GIM_CheckComplexPattern, /*MI*/2, /*Op*/1, /*Renderer*/GIMT_Encode2(2), GIMT_Encode2(GICP_gi_vop3mods),
        // (fmaxnum:{ *:[f32] } (fminnum_ieee:{ *:[f32] } (VOP3Mods:{ *:[f32] } f32:{ *:[f32] }:$src1, i32:{ *:[i32] }:$src1_mods), (VOP3Mods:{ *:[f32] } f32:{ *:[f32] }:$src0, i32:{ *:[i32] }:$src0_mods)), (fminnum:{ *:[f32] } (VOP3Mods:{ *:[f32] } f32:{ *:[f32] }:$src2, i32:{ *:[i32] }:$src2_mods), (fmaxnum_ieee:{ *:[f32] } (VOP3Mods:{ *:[f32] } f32:{ *:[f32] }:$src0, i32:{ *:[i32] }:$src0_mods), (VOP3Mods:{ *:[f32] } f32:{ *:[f32] }:$src1, i32:{ *:[i32] }:$src1_mods))))<<P:Predicate_fmaxnum_like_nnan>>  =>  (V_MED3_F32_e64:{ *:[f32] } ?:{ *:[i32] }:$src0_mods, ?:{ *:[f32] }:$src0, ?:{ *:[i32] }:$src1_mods, ?:{ *:[f32] }:$src1, ?:{ *:[i32] }:$src2_mods, ?:{ *:[f32] }:$src2, 0:{ *:[i1] }, 0:{ *:[i32] })
        GIR_BuildMI, /*InsnID*/0, /*Opcode*/GIMT_Encode2(AMDGPU::V_MED3_F32_e64),
        GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/0, // DstI[vdst]
        GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(1), /*SubOperand*/1, // src0_mods
        GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(1), /*SubOperand*/0, // src0
        GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/1, // src1_mods
        GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/0, // src1
        GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(2), /*SubOperand*/1, // src2_mods
        GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(2), /*SubOperand*/0, // src2
        GIR_AddImm8, /*InsnID*/0, /*Imm*/0,
        GIR_AddImm8, /*InsnID*/0, /*Imm*/0,
        GIR_ConstrainSelectedInstOperands, /*InsnID*/0,
        GIR_EraseFromParent, /*InsnID*/0,
        // GIR_Coverage, 10155,
        GIR_Done,
      // Label 4682: @317646
      GIM_Try, /*On fail goto*//*Label 4683*/ GIMT_Encode4(317786), // Rule ID 10156 //
        GIM_CheckRegBankForClass, /*MI*/0, /*Op*/0, /*RC*/GIMT_Encode2(AMDGPU::VGPR_32RegClassID),
        GIM_RecordInsn, /*DefineMI*/1, /*MI*/0, /*OpIdx*/1, // MIs[1]
        GIM_CheckOpcode, /*MI*/1, GIMT_Encode2(TargetOpcode::G_FMINNUM_IEEE),
        GIM_CheckType, /*MI*/1, /*Op*/1, /*Type*/GILLT_s32,
        GIM_CheckType, /*MI*/1, /*Op*/2, /*Type*/GILLT_s32,
        GIM_RecordInsn, /*DefineMI*/2, /*MI*/0, /*OpIdx*/2, // MIs[2]
        GIM_CheckOpcode, /*MI*/2, GIMT_Encode2(TargetOpcode::G_FMINNUM),
        GIM_CheckType, /*MI*/2, /*Op*/1, /*Type*/GILLT_s32,
        GIM_CheckType, /*MI*/2, /*Op*/2, /*Type*/GILLT_s32,
        GIM_RecordInsn, /*DefineMI*/3, /*MI*/2, /*OpIdx*/2, // MIs[3]
        GIM_CheckOpcode, /*MI*/3, GIMT_Encode2(TargetOpcode::G_FMAXNUM_IEEE),
        // MIs[3] VOP3Mods:src1:src1_mods
        GIM_CheckIsSameOperand, /*MI*/3, /*OpIdx*/1, /*OtherMI*/1, /*OtherOpIdx*/1,
        // MIs[3] VOP3Mods:src0:src0_mods
        GIM_CheckIsSameOperand, /*MI*/3, /*OpIdx*/2, /*OtherMI*/1, /*OtherOpIdx*/2,
        GIM_CheckCxxInsnPredicate, /*MI*/0, /*FnId*/GIMT_Encode2(GICXXPred_MI_Predicate_fmaxnum_like_nnan),
        GIM_CheckIsSafeToFold, /*InsnID*/1,
        GIM_CheckIsSafeToFold, /*InsnID*/2,
        GIM_CheckIsSafeToFold, /*InsnID*/3,
        GIM_CheckComplexPattern, /*MI*/1, /*Op*/1, /*Renderer*/GIMT_Encode2(0), GIMT_Encode2(GICP_gi_vop3mods),
        GIM_CheckComplexPattern, /*MI*/1, /*Op*/2, /*Renderer*/GIMT_Encode2(1), GIMT_Encode2(GICP_gi_vop3mods),
        GIM_CheckComplexPattern, /*MI*/2, /*Op*/1, /*Renderer*/GIMT_Encode2(2), GIMT_Encode2(GICP_gi_vop3mods),
        // (fmaxnum:{ *:[f32] } (fminnum_ieee:{ *:[f32] } (VOP3Mods:{ *:[f32] } f32:{ *:[f32] }:$src1, i32:{ *:[i32] }:$src1_mods), (VOP3Mods:{ *:[f32] } f32:{ *:[f32] }:$src0, i32:{ *:[i32] }:$src0_mods)), (fminnum:{ *:[f32] } (VOP3Mods:{ *:[f32] } f32:{ *:[f32] }:$src2, i32:{ *:[i32] }:$src2_mods), (fmaxnum_ieee:{ *:[f32] } (VOP3Mods:{ *:[f32] } f32:{ *:[f32] }:$src1, i32:{ *:[i32] }:$src1_mods), (VOP3Mods:{ *:[f32] } f32:{ *:[f32] }:$src0, i32:{ *:[i32] }:$src0_mods))))<<P:Predicate_fmaxnum_like_nnan>>  =>  (V_MED3_F32_e64:{ *:[f32] } ?:{ *:[i32] }:$src0_mods, ?:{ *:[f32] }:$src0, ?:{ *:[i32] }:$src1_mods, ?:{ *:[f32] }:$src1, ?:{ *:[i32] }:$src2_mods, ?:{ *:[f32] }:$src2, 0:{ *:[i1] }, 0:{ *:[i32] })
        GIR_BuildMI, /*InsnID*/0, /*Opcode*/GIMT_Encode2(AMDGPU::V_MED3_F32_e64),
        GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/0, // DstI[vdst]
        GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(1), /*SubOperand*/1, // src0_mods
        GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(1), /*SubOperand*/0, // src0
        GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/1, // src1_mods
        GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/0, // src1
        GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(2), /*SubOperand*/1, // src2_mods
        GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(2), /*SubOperand*/0, // src2
        GIR_AddImm8, /*InsnID*/0, /*Imm*/0,
        GIR_AddImm8, /*InsnID*/0, /*Imm*/0,
        GIR_ConstrainSelectedInstOperands, /*InsnID*/0,
        GIR_EraseFromParent, /*InsnID*/0,
        // GIR_Coverage, 10156,
        GIR_Done,
      // Label 4683: @317786
      GIM_Try, /*On fail goto*//*Label 4684*/ GIMT_Encode4(317926), // Rule ID 6493 //
        GIM_CheckRegBankForClass, /*MI*/0, /*Op*/0, /*RC*/GIMT_Encode2(AMDGPU::VGPR_32RegClassID),
        GIM_RecordInsn, /*DefineMI*/1, /*MI*/0, /*OpIdx*/1, // MIs[1]
        GIM_CheckOpcode, /*MI*/1, GIMT_Encode2(TargetOpcode::G_FMINNUM_IEEE),
        GIM_CheckType, /*MI*/1, /*Op*/1, /*Type*/GILLT_s32,
        GIM_CheckType, /*MI*/1, /*Op*/2, /*Type*/GILLT_s32,
        GIM_RecordInsn, /*DefineMI*/2, /*MI*/0, /*OpIdx*/2, // MIs[2]
        GIM_CheckOpcode, /*MI*/2, GIMT_Encode2(TargetOpcode::G_FMINNUM),
        GIM_CheckType, /*MI*/2, /*Op*/1, /*Type*/GILLT_s32,
        GIM_CheckType, /*MI*/2, /*Op*/2, /*Type*/GILLT_s32,
        GIM_RecordInsn, /*DefineMI*/3, /*MI*/2, /*OpIdx*/1, // MIs[3]
        GIM_CheckOpcode, /*MI*/3, GIMT_Encode2(TargetOpcode::G_FMAXNUM),
        // MIs[3] VOP3Mods:src0:src0_mods
        GIM_CheckIsSameOperand, /*MI*/3, /*OpIdx*/1, /*OtherMI*/1, /*OtherOpIdx*/1,
        // MIs[3] VOP3Mods:src1:src1_mods
        GIM_CheckIsSameOperand, /*MI*/3, /*OpIdx*/2, /*OtherMI*/1, /*OtherOpIdx*/2,
        GIM_CheckCxxInsnPredicate, /*MI*/0, /*FnId*/GIMT_Encode2(GICXXPred_MI_Predicate_fmaxnum_like_nnan),
        GIM_CheckIsSafeToFold, /*InsnID*/1,
        GIM_CheckIsSafeToFold, /*InsnID*/2,
        GIM_CheckIsSafeToFold, /*InsnID*/3,
        GIM_CheckComplexPattern, /*MI*/1, /*Op*/1, /*Renderer*/GIMT_Encode2(0), GIMT_Encode2(GICP_gi_vop3mods),
        GIM_CheckComplexPattern, /*MI*/1, /*Op*/2, /*Renderer*/GIMT_Encode2(1), GIMT_Encode2(GICP_gi_vop3mods),
        GIM_CheckComplexPattern, /*MI*/2, /*Op*/2, /*Renderer*/GIMT_Encode2(2), GIMT_Encode2(GICP_gi_vop3mods),
        // (fmaxnum:{ *:[f32] } (fminnum_ieee:{ *:[f32] } (VOP3Mods:{ *:[f32] } f32:{ *:[f32] }:$src0, i32:{ *:[i32] }:$src0_mods), (VOP3Mods:{ *:[f32] } f32:{ *:[f32] }:$src1, i32:{ *:[i32] }:$src1_mods)), (fminnum:{ *:[f32] } (fmaxnum:{ *:[f32] } (VOP3Mods:{ *:[f32] } f32:{ *:[f32] }:$src0, i32:{ *:[i32] }:$src0_mods), (VOP3Mods:{ *:[f32] } f32:{ *:[f32] }:$src1, i32:{ *:[i32] }:$src1_mods)), (VOP3Mods:{ *:[f32] } f32:{ *:[f32] }:$src2, i32:{ *:[i32] }:$src2_mods)))<<P:Predicate_fmaxnum_like_nnan>>  =>  (V_MED3_F32_e64:{ *:[f32] } ?:{ *:[i32] }:$src0_mods, ?:{ *:[f32] }:$src0, ?:{ *:[i32] }:$src1_mods, ?:{ *:[f32] }:$src1, ?:{ *:[i32] }:$src2_mods, ?:{ *:[f32] }:$src2, 0:{ *:[i1] }, 0:{ *:[i32] })
        GIR_BuildMI, /*InsnID*/0, /*Opcode*/GIMT_Encode2(AMDGPU::V_MED3_F32_e64),
        GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/0, // DstI[vdst]
        GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/1, // src0_mods
        GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/0, // src0
        GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(1), /*SubOperand*/1, // src1_mods
        GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(1), /*SubOperand*/0, // src1
        GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(2), /*SubOperand*/1, // src2_mods
        GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(2), /*SubOperand*/0, // src2
        GIR_AddImm8, /*InsnID*/0, /*Imm*/0,
        GIR_AddImm8, /*InsnID*/0, /*Imm*/0,
        GIR_ConstrainSelectedInstOperands, /*InsnID*/0,
        GIR_EraseFromParent, /*InsnID*/0,
        // GIR_Coverage, 6493,
        GIR_Done,
      // Label 4684: @317926
      GIM_Try, /*On fail goto*//*Label 4685*/ GIMT_Encode4(318066), // Rule ID 10165 //
        GIM_CheckRegBankForClass, /*MI*/0, /*Op*/0, /*RC*/GIMT_Encode2(AMDGPU::VGPR_32RegClassID),
        GIM_RecordInsn, /*DefineMI*/1, /*MI*/0, /*OpIdx*/1, // MIs[1]
        GIM_CheckOpcode, /*MI*/1, GIMT_Encode2(TargetOpcode::G_FMINNUM_IEEE),
        GIM_CheckType, /*MI*/1, /*Op*/1, /*Type*/GILLT_s32,
        GIM_CheckType, /*MI*/1, /*Op*/2, /*Type*/GILLT_s32,
        GIM_RecordInsn, /*DefineMI*/2, /*MI*/0, /*OpIdx*/2, // MIs[2]
        GIM_CheckOpcode, /*MI*/2, GIMT_Encode2(TargetOpcode::G_FMINNUM),
        GIM_CheckType, /*MI*/2, /*Op*/1, /*Type*/GILLT_s32,
        GIM_CheckType, /*MI*/2, /*Op*/2, /*Type*/GILLT_s32,
        GIM_RecordInsn, /*DefineMI*/3, /*MI*/2, /*OpIdx*/1, // MIs[3]
        GIM_CheckOpcode, /*MI*/3, GIMT_Encode2(TargetOpcode::G_FMAXNUM),
        // MIs[3] VOP3Mods:src1:src1_mods
        GIM_CheckIsSameOperand, /*MI*/3, /*OpIdx*/1, /*OtherMI*/1, /*OtherOpIdx*/2,
        // MIs[3] VOP3Mods:src0:src0_mods
        GIM_CheckIsSameOperand, /*MI*/3, /*OpIdx*/2, /*OtherMI*/1, /*OtherOpIdx*/1,
        GIM_CheckCxxInsnPredicate, /*MI*/0, /*FnId*/GIMT_Encode2(GICXXPred_MI_Predicate_fmaxnum_like_nnan),
        GIM_CheckIsSafeToFold, /*InsnID*/1,
        GIM_CheckIsSafeToFold, /*InsnID*/2,
        GIM_CheckIsSafeToFold, /*InsnID*/3,
        GIM_CheckComplexPattern, /*MI*/1, /*Op*/1, /*Renderer*/GIMT_Encode2(0), GIMT_Encode2(GICP_gi_vop3mods),
        GIM_CheckComplexPattern, /*MI*/1, /*Op*/2, /*Renderer*/GIMT_Encode2(1), GIMT_Encode2(GICP_gi_vop3mods),
        GIM_CheckComplexPattern, /*MI*/2, /*Op*/2, /*Renderer*/GIMT_Encode2(2), GIMT_Encode2(GICP_gi_vop3mods),
        // (fmaxnum:{ *:[f32] } (fminnum_ieee:{ *:[f32] } (VOP3Mods:{ *:[f32] } f32:{ *:[f32] }:$src0, i32:{ *:[i32] }:$src0_mods), (VOP3Mods:{ *:[f32] } f32:{ *:[f32] }:$src1, i32:{ *:[i32] }:$src1_mods)), (fminnum:{ *:[f32] } (fmaxnum:{ *:[f32] } (VOP3Mods:{ *:[f32] } f32:{ *:[f32] }:$src1, i32:{ *:[i32] }:$src1_mods), (VOP3Mods:{ *:[f32] } f32:{ *:[f32] }:$src0, i32:{ *:[i32] }:$src0_mods)), (VOP3Mods:{ *:[f32] } f32:{ *:[f32] }:$src2, i32:{ *:[i32] }:$src2_mods)))<<P:Predicate_fmaxnum_like_nnan>>  =>  (V_MED3_F32_e64:{ *:[f32] } ?:{ *:[i32] }:$src0_mods, ?:{ *:[f32] }:$src0, ?:{ *:[i32] }:$src1_mods, ?:{ *:[f32] }:$src1, ?:{ *:[i32] }:$src2_mods, ?:{ *:[f32] }:$src2, 0:{ *:[i1] }, 0:{ *:[i32] })
        GIR_BuildMI, /*InsnID*/0, /*Opcode*/GIMT_Encode2(AMDGPU::V_MED3_F32_e64),
        GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/0, // DstI[vdst]
        GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/1, // src0_mods
        GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/0, // src0
        GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(1), /*SubOperand*/1, // src1_mods
        GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(1), /*SubOperand*/0, // src1
        GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(2), /*SubOperand*/1, // src2_mods
        GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(2), /*SubOperand*/0, // src2
        GIR_AddImm8, /*InsnID*/0, /*Imm*/0,
        GIR_AddImm8, /*InsnID*/0, /*Imm*/0,
        GIR_ConstrainSelectedInstOperands, /*InsnID*/0,
        GIR_EraseFromParent, /*InsnID*/0,
        // GIR_Coverage, 10165,
        GIR_Done,
      // Label 4685: @318066
      GIM_Try, /*On fail goto*//*Label 4686*/ GIMT_Encode4(318206), // Rule ID 10168 //
        GIM_CheckRegBankForClass, /*MI*/0, /*Op*/0, /*RC*/GIMT_Encode2(AMDGPU::VGPR_32RegClassID),
        GIM_RecordInsn, /*DefineMI*/1, /*MI*/0, /*OpIdx*/1, // MIs[1]
        GIM_CheckOpcode, /*MI*/1, GIMT_Encode2(TargetOpcode::G_FMINNUM_IEEE),
        GIM_CheckType, /*MI*/1, /*Op*/1, /*Type*/GILLT_s32,
        GIM_CheckType, /*MI*/1, /*Op*/2, /*Type*/GILLT_s32,
        GIM_RecordInsn, /*DefineMI*/2, /*MI*/0, /*OpIdx*/2, // MIs[2]
        GIM_CheckOpcode, /*MI*/2, GIMT_Encode2(TargetOpcode::G_FMINNUM),
        GIM_CheckType, /*MI*/2, /*Op*/1, /*Type*/GILLT_s32,
        GIM_CheckType, /*MI*/2, /*Op*/2, /*Type*/GILLT_s32,
        GIM_RecordInsn, /*DefineMI*/3, /*MI*/2, /*OpIdx*/1, // MIs[3]
        GIM_CheckOpcode, /*MI*/3, GIMT_Encode2(TargetOpcode::G_FMAXNUM),
        // MIs[3] VOP3Mods:src0:src0_mods
        GIM_CheckIsSameOperand, /*MI*/3, /*OpIdx*/1, /*OtherMI*/1, /*OtherOpIdx*/2,
        // MIs[3] VOP3Mods:src1:src1_mods
        GIM_CheckIsSameOperand, /*MI*/3, /*OpIdx*/2, /*OtherMI*/1, /*OtherOpIdx*/1,
        GIM_CheckCxxInsnPredicate, /*MI*/0, /*FnId*/GIMT_Encode2(GICXXPred_MI_Predicate_fmaxnum_like_nnan),
        GIM_CheckIsSafeToFold, /*InsnID*/1,
        GIM_CheckIsSafeToFold, /*InsnID*/2,
        GIM_CheckIsSafeToFold, /*InsnID*/3,
        GIM_CheckComplexPattern, /*MI*/1, /*Op*/1, /*Renderer*/GIMT_Encode2(0), GIMT_Encode2(GICP_gi_vop3mods),
        GIM_CheckComplexPattern, /*MI*/1, /*Op*/2, /*Renderer*/GIMT_Encode2(1), GIMT_Encode2(GICP_gi_vop3mods),
        GIM_CheckComplexPattern, /*MI*/2, /*Op*/2, /*Renderer*/GIMT_Encode2(2), GIMT_Encode2(GICP_gi_vop3mods),
        // (fmaxnum:{ *:[f32] } (fminnum_ieee:{ *:[f32] } (VOP3Mods:{ *:[f32] } f32:{ *:[f32] }:$src1, i32:{ *:[i32] }:$src1_mods), (VOP3Mods:{ *:[f32] } f32:{ *:[f32] }:$src0, i32:{ *:[i32] }:$src0_mods)), (fminnum:{ *:[f32] } (fmaxnum:{ *:[f32] } (VOP3Mods:{ *:[f32] } f32:{ *:[f32] }:$src0, i32:{ *:[i32] }:$src0_mods), (VOP3Mods:{ *:[f32] } f32:{ *:[f32] }:$src1, i32:{ *:[i32] }:$src1_mods)), (VOP3Mods:{ *:[f32] } f32:{ *:[f32] }:$src2, i32:{ *:[i32] }:$src2_mods)))<<P:Predicate_fmaxnum_like_nnan>>  =>  (V_MED3_F32_e64:{ *:[f32] } ?:{ *:[i32] }:$src0_mods, ?:{ *:[f32] }:$src0, ?:{ *:[i32] }:$src1_mods, ?:{ *:[f32] }:$src1, ?:{ *:[i32] }:$src2_mods, ?:{ *:[f32] }:$src2, 0:{ *:[i1] }, 0:{ *:[i32] })
        GIR_BuildMI, /*InsnID*/0, /*Opcode*/GIMT_Encode2(AMDGPU::V_MED3_F32_e64),
        GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/0, // DstI[vdst]
        GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(1), /*SubOperand*/1, // src0_mods
        GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(1), /*SubOperand*/0, // src0
        GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/1, // src1_mods
        GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/0, // src1
        GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(2), /*SubOperand*/1, // src2_mods
        GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(2), /*SubOperand*/0, // src2
        GIR_AddImm8, /*InsnID*/0, /*Imm*/0,
        GIR_AddImm8, /*InsnID*/0, /*Imm*/0,
        GIR_ConstrainSelectedInstOperands, /*InsnID*/0,
        GIR_EraseFromParent, /*InsnID*/0,
        // GIR_Coverage, 10168,
        GIR_Done,
      // Label 4686: @318206
      GIM_Try, /*On fail goto*//*Label 4687*/ GIMT_Encode4(318346), // Rule ID 10169 //
        GIM_CheckRegBankForClass, /*MI*/0, /*Op*/0, /*RC*/GIMT_Encode2(AMDGPU::VGPR_32RegClassID),
        GIM_RecordInsn, /*DefineMI*/1, /*MI*/0, /*OpIdx*/1, // MIs[1]
        GIM_CheckOpcode, /*MI*/1, GIMT_Encode2(TargetOpcode::G_FMINNUM_IEEE),
        GIM_CheckType, /*MI*/1, /*Op*/1, /*Type*/GILLT_s32,
        GIM_CheckType, /*MI*/1, /*Op*/2, /*Type*/GILLT_s32,
        GIM_RecordInsn, /*DefineMI*/2, /*MI*/0, /*OpIdx*/2, // MIs[2]
        GIM_CheckOpcode, /*MI*/2, GIMT_Encode2(TargetOpcode::G_FMINNUM),
        GIM_CheckType, /*MI*/2, /*Op*/1, /*Type*/GILLT_s32,
        GIM_CheckType, /*MI*/2, /*Op*/2, /*Type*/GILLT_s32,
        GIM_RecordInsn, /*DefineMI*/3, /*MI*/2, /*OpIdx*/1, // MIs[3]
        GIM_CheckOpcode, /*MI*/3, GIMT_Encode2(TargetOpcode::G_FMAXNUM),
        // MIs[3] VOP3Mods:src1:src1_mods
        GIM_CheckIsSameOperand, /*MI*/3, /*OpIdx*/1, /*OtherMI*/1, /*OtherOpIdx*/1,
        // MIs[3] VOP3Mods:src0:src0_mods
        GIM_CheckIsSameOperand, /*MI*/3, /*OpIdx*/2, /*OtherMI*/1, /*OtherOpIdx*/2,
        GIM_CheckCxxInsnPredicate, /*MI*/0, /*FnId*/GIMT_Encode2(GICXXPred_MI_Predicate_fmaxnum_like_nnan),
        GIM_CheckIsSafeToFold, /*InsnID*/1,
        GIM_CheckIsSafeToFold, /*InsnID*/2,
        GIM_CheckIsSafeToFold, /*InsnID*/3,
        GIM_CheckComplexPattern, /*MI*/1, /*Op*/1, /*Renderer*/GIMT_Encode2(0), GIMT_Encode2(GICP_gi_vop3mods),
        GIM_CheckComplexPattern, /*MI*/1, /*Op*/2, /*Renderer*/GIMT_Encode2(1), GIMT_Encode2(GICP_gi_vop3mods),
        GIM_CheckComplexPattern, /*MI*/2, /*Op*/2, /*Renderer*/GIMT_Encode2(2), GIMT_Encode2(GICP_gi_vop3mods),
        // (fmaxnum:{ *:[f32] } (fminnum_ieee:{ *:[f32] } (VOP3Mods:{ *:[f32] } f32:{ *:[f32] }:$src1, i32:{ *:[i32] }:$src1_mods), (VOP3Mods:{ *:[f32] } f32:{ *:[f32] }:$src0, i32:{ *:[i32] }:$src0_mods)), (fminnum:{ *:[f32] } (fmaxnum:{ *:[f32] } (VOP3Mods:{ *:[f32] } f32:{ *:[f32] }:$src1, i32:{ *:[i32] }:$src1_mods), (VOP3Mods:{ *:[f32] } f32:{ *:[f32] }:$src0, i32:{ *:[i32] }:$src0_mods)), (VOP3Mods:{ *:[f32] } f32:{ *:[f32] }:$src2, i32:{ *:[i32] }:$src2_mods)))<<P:Predicate_fmaxnum_like_nnan>>  =>  (V_MED3_F32_e64:{ *:[f32] } ?:{ *:[i32] }:$src0_mods, ?:{ *:[f32] }:$src0, ?:{ *:[i32] }:$src1_mods, ?:{ *:[f32] }:$src1, ?:{ *:[i32] }:$src2_mods, ?:{ *:[f32] }:$src2, 0:{ *:[i1] }, 0:{ *:[i32] })
        GIR_BuildMI, /*InsnID*/0, /*Opcode*/GIMT_Encode2(AMDGPU::V_MED3_F32_e64),
        GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/0, // DstI[vdst]
        GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(1), /*SubOperand*/1, // src0_mods
        GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(1), /*SubOperand*/0, // src0
        GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/1, // src1_mods
        GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/0, // src1
        GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(2), /*SubOperand*/1, // src2_mods
        GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(2), /*SubOperand*/0, // src2
        GIR_AddImm8, /*InsnID*/0, /*Imm*/0,
        GIR_AddImm8, /*InsnID*/0, /*Imm*/0,
        GIR_ConstrainSelectedInstOperands, /*InsnID*/0,
        GIR_EraseFromParent, /*InsnID*/0,
        // GIR_Coverage, 10169,
        GIR_Done,
      // Label 4687: @318346
      GIM_Try, /*On fail goto*//*Label 4688*/ GIMT_Encode4(318486), // Rule ID 6492 //
        GIM_CheckRegBankForClass, /*MI*/0, /*Op*/0, /*RC*/GIMT_Encode2(AMDGPU::VGPR_32RegClassID),
        GIM_RecordInsn, /*DefineMI*/1, /*MI*/0, /*OpIdx*/1, // MIs[1]
        GIM_CheckOpcode, /*MI*/1, GIMT_Encode2(TargetOpcode::G_FMINNUM_IEEE),
        GIM_CheckType, /*MI*/1, /*Op*/1, /*Type*/GILLT_s32,
        GIM_CheckType, /*MI*/1, /*Op*/2, /*Type*/GILLT_s32,
        GIM_RecordInsn, /*DefineMI*/2, /*MI*/0, /*OpIdx*/2, // MIs[2]
        GIM_CheckOpcode, /*MI*/2, GIMT_Encode2(TargetOpcode::G_FMINNUM),
        GIM_CheckType, /*MI*/2, /*Op*/1, /*Type*/GILLT_s32,
        GIM_CheckType, /*MI*/2, /*Op*/2, /*Type*/GILLT_s32,
        GIM_RecordInsn, /*DefineMI*/3, /*MI*/2, /*OpIdx*/1, // MIs[3]
        GIM_CheckOpcode, /*MI*/3, GIMT_Encode2(TargetOpcode::G_FMAXNUM_IEEE),
        // MIs[3] VOP3Mods:src0:src0_mods
        GIM_CheckIsSameOperand, /*MI*/3, /*OpIdx*/1, /*OtherMI*/1, /*OtherOpIdx*/1,
        // MIs[3] VOP3Mods:src1:src1_mods
        GIM_CheckIsSameOperand, /*MI*/3, /*OpIdx*/2, /*OtherMI*/1, /*OtherOpIdx*/2,
        GIM_CheckCxxInsnPredicate, /*MI*/0, /*FnId*/GIMT_Encode2(GICXXPred_MI_Predicate_fmaxnum_like_nnan),
        GIM_CheckIsSafeToFold, /*InsnID*/1,
        GIM_CheckIsSafeToFold, /*InsnID*/2,
        GIM_CheckIsSafeToFold, /*InsnID*/3,
        GIM_CheckComplexPattern, /*MI*/1, /*Op*/1, /*Renderer*/GIMT_Encode2(0), GIMT_Encode2(GICP_gi_vop3mods),
        GIM_CheckComplexPattern, /*MI*/1, /*Op*/2, /*Renderer*/GIMT_Encode2(1), GIMT_Encode2(GICP_gi_vop3mods),
        GIM_CheckComplexPattern, /*MI*/2, /*Op*/2, /*Renderer*/GIMT_Encode2(2), GIMT_Encode2(GICP_gi_vop3mods),
        // (fmaxnum:{ *:[f32] } (fminnum_ieee:{ *:[f32] } (VOP3Mods:{ *:[f32] } f32:{ *:[f32] }:$src0, i32:{ *:[i32] }:$src0_mods), (VOP3Mods:{ *:[f32] } f32:{ *:[f32] }:$src1, i32:{ *:[i32] }:$src1_mods)), (fminnum:{ *:[f32] } (fmaxnum_ieee:{ *:[f32] } (VOP3Mods:{ *:[f32] } f32:{ *:[f32] }:$src0, i32:{ *:[i32] }:$src0_mods), (VOP3Mods:{ *:[f32] } f32:{ *:[f32] }:$src1, i32:{ *:[i32] }:$src1_mods)), (VOP3Mods:{ *:[f32] } f32:{ *:[f32] }:$src2, i32:{ *:[i32] }:$src2_mods)))<<P:Predicate_fmaxnum_like_nnan>>  =>  (V_MED3_F32_e64:{ *:[f32] } ?:{ *:[i32] }:$src0_mods, ?:{ *:[f32] }:$src0, ?:{ *:[i32] }:$src1_mods, ?:{ *:[f32] }:$src1, ?:{ *:[i32] }:$src2_mods, ?:{ *:[f32] }:$src2, 0:{ *:[i1] }, 0:{ *:[i32] })
        GIR_BuildMI, /*InsnID*/0, /*Opcode*/GIMT_Encode2(AMDGPU::V_MED3_F32_e64),
        GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/0, // DstI[vdst]
        GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/1, // src0_mods
        GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/0, // src0
        GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(1), /*SubOperand*/1, // src1_mods
        GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(1), /*SubOperand*/0, // src1
        GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(2), /*SubOperand*/1, // src2_mods
        GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(2), /*SubOperand*/0, // src2
        GIR_AddImm8, /*InsnID*/0, /*Imm*/0,
        GIR_AddImm8, /*InsnID*/0, /*Imm*/0,
        GIR_ConstrainSelectedInstOperands, /*InsnID*/0,
        GIR_EraseFromParent, /*InsnID*/0,
        // GIR_Coverage, 6492,
        GIR_Done,
      // Label 4688: @318486
      GIM_Try, /*On fail goto*//*Label 4689*/ GIMT_Encode4(318626), // Rule ID 10150 //
        GIM_CheckRegBankForClass, /*MI*/0, /*Op*/0, /*RC*/GIMT_Encode2(AMDGPU::VGPR_32RegClassID),
        GIM_RecordInsn, /*DefineMI*/1, /*MI*/0, /*OpIdx*/1, // MIs[1]
        GIM_CheckOpcode, /*MI*/1, GIMT_Encode2(TargetOpcode::G_FMINNUM_IEEE),
        GIM_CheckType, /*MI*/1, /*Op*/1, /*Type*/GILLT_s32,
        GIM_CheckType, /*MI*/1, /*Op*/2, /*Type*/GILLT_s32,
        GIM_RecordInsn, /*DefineMI*/2, /*MI*/0, /*OpIdx*/2, // MIs[2]
        GIM_CheckOpcode, /*MI*/2, GIMT_Encode2(TargetOpcode::G_FMINNUM),
        GIM_CheckType, /*MI*/2, /*Op*/1, /*Type*/GILLT_s32,
        GIM_CheckType, /*MI*/2, /*Op*/2, /*Type*/GILLT_s32,
        GIM_RecordInsn, /*DefineMI*/3, /*MI*/2, /*OpIdx*/1, // MIs[3]
        GIM_CheckOpcode, /*MI*/3, GIMT_Encode2(TargetOpcode::G_FMAXNUM_IEEE),
        // MIs[3] VOP3Mods:src1:src1_mods
        GIM_CheckIsSameOperand, /*MI*/3, /*OpIdx*/1, /*OtherMI*/1, /*OtherOpIdx*/2,
        // MIs[3] VOP3Mods:src0:src0_mods
        GIM_CheckIsSameOperand, /*MI*/3, /*OpIdx*/2, /*OtherMI*/1, /*OtherOpIdx*/1,
        GIM_CheckCxxInsnPredicate, /*MI*/0, /*FnId*/GIMT_Encode2(GICXXPred_MI_Predicate_fmaxnum_like_nnan),
        GIM_CheckIsSafeToFold, /*InsnID*/1,
        GIM_CheckIsSafeToFold, /*InsnID*/2,
        GIM_CheckIsSafeToFold, /*InsnID*/3,
        GIM_CheckComplexPattern, /*MI*/1, /*Op*/1, /*Renderer*/GIMT_Encode2(0), GIMT_Encode2(GICP_gi_vop3mods),
        GIM_CheckComplexPattern, /*MI*/1, /*Op*/2, /*Renderer*/GIMT_Encode2(1), GIMT_Encode2(GICP_gi_vop3mods),
        GIM_CheckComplexPattern, /*MI*/2, /*Op*/2, /*Renderer*/GIMT_Encode2(2), GIMT_Encode2(GICP_gi_vop3mods),
        // (fmaxnum:{ *:[f32] } (fminnum_ieee:{ *:[f32] } (VOP3Mods:{ *:[f32] } f32:{ *:[f32] }:$src0, i32:{ *:[i32] }:$src0_mods), (VOP3Mods:{ *:[f32] } f32:{ *:[f32] }:$src1, i32:{ *:[i32] }:$src1_mods)), (fminnum:{ *:[f32] } (fmaxnum_ieee:{ *:[f32] } (VOP3Mods:{ *:[f32] } f32:{ *:[f32] }:$src1, i32:{ *:[i32] }:$src1_mods), (VOP3Mods:{ *:[f32] } f32:{ *:[f32] }:$src0, i32:{ *:[i32] }:$src0_mods)), (VOP3Mods:{ *:[f32] } f32:{ *:[f32] }:$src2, i32:{ *:[i32] }:$src2_mods)))<<P:Predicate_fmaxnum_like_nnan>>  =>  (V_MED3_F32_e64:{ *:[f32] } ?:{ *:[i32] }:$src0_mods, ?:{ *:[f32] }:$src0, ?:{ *:[i32] }:$src1_mods, ?:{ *:[f32] }:$src1, ?:{ *:[i32] }:$src2_mods, ?:{ *:[f32] }:$src2, 0:{ *:[i1] }, 0:{ *:[i32] })
        GIR_BuildMI, /*InsnID*/0, /*Opcode*/GIMT_Encode2(AMDGPU::V_MED3_F32_e64),
        GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/0, // DstI[vdst]
        GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/1, // src0_mods
        GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/0, // src0
        GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(1), /*SubOperand*/1, // src1_mods
        GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(1), /*SubOperand*/0, // src1
        GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(2), /*SubOperand*/1, // src2_mods
        GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(2), /*SubOperand*/0, // src2
        GIR_AddImm8, /*InsnID*/0, /*Imm*/0,
        GIR_AddImm8, /*InsnID*/0, /*Imm*/0,
        GIR_ConstrainSelectedInstOperands, /*InsnID*/0,
        GIR_EraseFromParent, /*InsnID*/0,
        // GIR_Coverage, 10150,
        GIR_Done,
      // Label 4689: @318626
      GIM_Try, /*On fail goto*//*Label 4690*/ GIMT_Encode4(318766), // Rule ID 10153 //
        GIM_CheckRegBankForClass, /*MI*/0, /*Op*/0, /*RC*/GIMT_Encode2(AMDGPU::VGPR_32RegClassID),
        GIM_RecordInsn, /*DefineMI*/1, /*MI*/0, /*OpIdx*/1, // MIs[1]
        GIM_CheckOpcode, /*MI*/1, GIMT_Encode2(TargetOpcode::G_FMINNUM_IEEE),
        GIM_CheckType, /*MI*/1, /*Op*/1, /*Type*/GILLT_s32,
        GIM_CheckType, /*MI*/1, /*Op*/2, /*Type*/GILLT_s32,
        GIM_RecordInsn, /*DefineMI*/2, /*MI*/0, /*OpIdx*/2, // MIs[2]
        GIM_CheckOpcode, /*MI*/2, GIMT_Encode2(TargetOpcode::G_FMINNUM),
        GIM_CheckType, /*MI*/2, /*Op*/1, /*Type*/GILLT_s32,
        GIM_CheckType, /*MI*/2, /*Op*/2, /*Type*/GILLT_s32,
        GIM_RecordInsn, /*DefineMI*/3, /*MI*/2, /*OpIdx*/1, // MIs[3]
        GIM_CheckOpcode, /*MI*/3, GIMT_Encode2(TargetOpcode::G_FMAXNUM_IEEE),
        // MIs[3] VOP3Mods:src0:src0_mods
        GIM_CheckIsSameOperand, /*MI*/3, /*OpIdx*/1, /*OtherMI*/1, /*OtherOpIdx*/2,
        // MIs[3] VOP3Mods:src1:src1_mods
        GIM_CheckIsSameOperand, /*MI*/3, /*OpIdx*/2, /*OtherMI*/1, /*OtherOpIdx*/1,
        GIM_CheckCxxInsnPredicate, /*MI*/0, /*FnId*/GIMT_Encode2(GICXXPred_MI_Predicate_fmaxnum_like_nnan),
        GIM_CheckIsSafeToFold, /*InsnID*/1,
        GIM_CheckIsSafeToFold, /*InsnID*/2,
        GIM_CheckIsSafeToFold, /*InsnID*/3,
        GIM_CheckComplexPattern, /*MI*/1, /*Op*/1, /*Renderer*/GIMT_Encode2(0), GIMT_Encode2(GICP_gi_vop3mods),
        GIM_CheckComplexPattern, /*MI*/1, /*Op*/2, /*Renderer*/GIMT_Encode2(1), GIMT_Encode2(GICP_gi_vop3mods),
        GIM_CheckComplexPattern, /*MI*/2, /*Op*/2, /*Renderer*/GIMT_Encode2(2), GIMT_Encode2(GICP_gi_vop3mods),
        // (fmaxnum:{ *:[f32] } (fminnum_ieee:{ *:[f32] } (VOP3Mods:{ *:[f32] } f32:{ *:[f32] }:$src1, i32:{ *:[i32] }:$src1_mods), (VOP3Mods:{ *:[f32] } f32:{ *:[f32] }:$src0, i32:{ *:[i32] }:$src0_mods)), (fminnum:{ *:[f32] } (fmaxnum_ieee:{ *:[f32] } (VOP3Mods:{ *:[f32] } f32:{ *:[f32] }:$src0, i32:{ *:[i32] }:$src0_mods), (VOP3Mods:{ *:[f32] } f32:{ *:[f32] }:$src1, i32:{ *:[i32] }:$src1_mods)), (VOP3Mods:{ *:[f32] } f32:{ *:[f32] }:$src2, i32:{ *:[i32] }:$src2_mods)))<<P:Predicate_fmaxnum_like_nnan>>  =>  (V_MED3_F32_e64:{ *:[f32] } ?:{ *:[i32] }:$src0_mods, ?:{ *:[f32] }:$src0, ?:{ *:[i32] }:$src1_mods, ?:{ *:[f32] }:$src1, ?:{ *:[i32] }:$src2_mods, ?:{ *:[f32] }:$src2, 0:{ *:[i1] }, 0:{ *:[i32] })
        GIR_BuildMI, /*InsnID*/0, /*Opcode*/GIMT_Encode2(AMDGPU::V_MED3_F32_e64),
        GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/0, // DstI[vdst]
        GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(1), /*SubOperand*/1, // src0_mods
        GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(1), /*SubOperand*/0, // src0
        GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/1, // src1_mods
        GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/0, // src1
        GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(2), /*SubOperand*/1, // src2_mods
        GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(2), /*SubOperand*/0, // src2
        GIR_AddImm8, /*InsnID*/0, /*Imm*/0,
        GIR_AddImm8, /*InsnID*/0, /*Imm*/0,
        GIR_ConstrainSelectedInstOperands, /*InsnID*/0,
        GIR_EraseFromParent, /*InsnID*/0,
        // GIR_Coverage, 10153,
        GIR_Done,
      // Label 4690: @318766
      GIM_Try, /*On fail goto*//*Label 4691*/ GIMT_Encode4(318906), // Rule ID 10154 //
        GIM_CheckRegBankForClass, /*MI*/0, /*Op*/0, /*RC*/GIMT_Encode2(AMDGPU::VGPR_32RegClassID),
        GIM_RecordInsn, /*DefineMI*/1, /*MI*/0, /*OpIdx*/1, // MIs[1]
        GIM_CheckOpcode, /*MI*/1, GIMT_Encode2(TargetOpcode::G_FMINNUM_IEEE),
        GIM_CheckType, /*MI*/1, /*Op*/1, /*Type*/GILLT_s32,
        GIM_CheckType, /*MI*/1, /*Op*/2, /*Type*/GILLT_s32,
        GIM_RecordInsn, /*DefineMI*/2, /*MI*/0, /*OpIdx*/2, // MIs[2]
        GIM_CheckOpcode, /*MI*/2, GIMT_Encode2(TargetOpcode::G_FMINNUM),
        GIM_CheckType, /*MI*/2, /*Op*/1, /*Type*/GILLT_s32,
        GIM_CheckType, /*MI*/2, /*Op*/2, /*Type*/GILLT_s32,
        GIM_RecordInsn, /*DefineMI*/3, /*MI*/2, /*OpIdx*/1, // MIs[3]
        GIM_CheckOpcode, /*MI*/3, GIMT_Encode2(TargetOpcode::G_FMAXNUM_IEEE),
        // MIs[3] VOP3Mods:src1:src1_mods
        GIM_CheckIsSameOperand, /*MI*/3, /*OpIdx*/1, /*OtherMI*/1, /*OtherOpIdx*/1,
        // MIs[3] VOP3Mods:src0:src0_mods
        GIM_CheckIsSameOperand, /*MI*/3, /*OpIdx*/2, /*OtherMI*/1, /*OtherOpIdx*/2,
        GIM_CheckCxxInsnPredicate, /*MI*/0, /*FnId*/GIMT_Encode2(GICXXPred_MI_Predicate_fmaxnum_like_nnan),
        GIM_CheckIsSafeToFold, /*InsnID*/1,
        GIM_CheckIsSafeToFold, /*InsnID*/2,
        GIM_CheckIsSafeToFold, /*InsnID*/3,
        GIM_CheckComplexPattern, /*MI*/1, /*Op*/1, /*Renderer*/GIMT_Encode2(0), GIMT_Encode2(GICP_gi_vop3mods),
        GIM_CheckComplexPattern, /*MI*/1, /*Op*/2, /*Renderer*/GIMT_Encode2(1), GIMT_Encode2(GICP_gi_vop3mods),
        GIM_CheckComplexPattern, /*MI*/2, /*Op*/2, /*Renderer*/GIMT_Encode2(2), GIMT_Encode2(GICP_gi_vop3mods),
        // (fmaxnum:{ *:[f32] } (fminnum_ieee:{ *:[f32] } (VOP3Mods:{ *:[f32] } f32:{ *:[f32] }:$src1, i32:{ *:[i32] }:$src1_mods), (VOP3Mods:{ *:[f32] } f32:{ *:[f32] }:$src0, i32:{ *:[i32] }:$src0_mods)), (fminnum:{ *:[f32] } (fmaxnum_ieee:{ *:[f32] } (VOP3Mods:{ *:[f32] } f32:{ *:[f32] }:$src1, i32:{ *:[i32] }:$src1_mods), (VOP3Mods:{ *:[f32] } f32:{ *:[f32] }:$src0, i32:{ *:[i32] }:$src0_mods)), (VOP3Mods:{ *:[f32] } f32:{ *:[f32] }:$src2, i32:{ *:[i32] }:$src2_mods)))<<P:Predicate_fmaxnum_like_nnan>>  =>  (V_MED3_F32_e64:{ *:[f32] } ?:{ *:[i32] }:$src0_mods, ?:{ *:[f32] }:$src0, ?:{ *:[i32] }:$src1_mods, ?:{ *:[f32] }:$src1, ?:{ *:[i32] }:$src2_mods, ?:{ *:[f32] }:$src2, 0:{ *:[i1] }, 0:{ *:[i32] })
        GIR_BuildMI, /*InsnID*/0, /*Opcode*/GIMT_Encode2(AMDGPU::V_MED3_F32_e64),
        GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/0, // DstI[vdst]
        GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(1), /*SubOperand*/1, // src0_mods
        GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(1), /*SubOperand*/0, // src0
        GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/1, // src1_mods
        GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/0, // src1
        GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(2), /*SubOperand*/1, // src2_mods
        GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(2), /*SubOperand*/0, // src2
        GIR_AddImm8, /*InsnID*/0, /*Imm*/0,
        GIR_AddImm8, /*InsnID*/0, /*Imm*/0,
        GIR_ConstrainSelectedInstOperands, /*InsnID*/0,
        GIR_EraseFromParent, /*InsnID*/0,
        // GIR_Coverage, 10154,
        GIR_Done,
      // Label 4691: @318906
      GIM_Try, /*On fail goto*//*Label 4692*/ GIMT_Encode4(319046), // Rule ID 10136 //
        GIM_CheckRegBankForClass, /*MI*/0, /*Op*/0, /*RC*/GIMT_Encode2(AMDGPU::VGPR_32RegClassID),
        GIM_RecordInsn, /*DefineMI*/1, /*MI*/0, /*OpIdx*/1, // MIs[1]
        GIM_CheckOpcode, /*MI*/1, GIMT_Encode2(TargetOpcode::G_FMINNUM_IEEE),
        GIM_CheckType, /*MI*/1, /*Op*/1, /*Type*/GILLT_s32,
        GIM_CheckType, /*MI*/1, /*Op*/2, /*Type*/GILLT_s32,
        GIM_RecordInsn, /*DefineMI*/2, /*MI*/0, /*OpIdx*/2, // MIs[2]
        GIM_CheckOpcode, /*MI*/2, GIMT_Encode2(TargetOpcode::G_FMINNUM_IEEE),
        GIM_CheckType, /*MI*/2, /*Op*/1, /*Type*/GILLT_s32,
        GIM_CheckType, /*MI*/2, /*Op*/2, /*Type*/GILLT_s32,
        GIM_RecordInsn, /*DefineMI*/3, /*MI*/2, /*OpIdx*/2, // MIs[3]
        GIM_CheckOpcode, /*MI*/3, GIMT_Encode2(TargetOpcode::G_FMAXNUM),
        // MIs[3] VOP3Mods:src0:src0_mods
        GIM_CheckIsSameOperand, /*MI*/3, /*OpIdx*/1, /*OtherMI*/1, /*OtherOpIdx*/1,
        // MIs[3] VOP3Mods:src1:src1_mods
        GIM_CheckIsSameOperand, /*MI*/3, /*OpIdx*/2, /*OtherMI*/1, /*OtherOpIdx*/2,
        GIM_CheckCxxInsnPredicate, /*MI*/0, /*FnId*/GIMT_Encode2(GICXXPred_MI_Predicate_fmaxnum_like_nnan),
        GIM_CheckIsSafeToFold, /*InsnID*/1,
        GIM_CheckIsSafeToFold, /*InsnID*/2,
        GIM_CheckIsSafeToFold, /*InsnID*/3,
        GIM_CheckComplexPattern, /*MI*/1, /*Op*/1, /*Renderer*/GIMT_Encode2(0), GIMT_Encode2(GICP_gi_vop3mods),
        GIM_CheckComplexPattern, /*MI*/1, /*Op*/2, /*Renderer*/GIMT_Encode2(1), GIMT_Encode2(GICP_gi_vop3mods),
        GIM_CheckComplexPattern, /*MI*/2, /*Op*/1, /*Renderer*/GIMT_Encode2(2), GIMT_Encode2(GICP_gi_vop3mods),
        // (fmaxnum:{ *:[f32] } (fminnum_ieee:{ *:[f32] } (VOP3Mods:{ *:[f32] } f32:{ *:[f32] }:$src0, i32:{ *:[i32] }:$src0_mods), (VOP3Mods:{ *:[f32] } f32:{ *:[f32] }:$src1, i32:{ *:[i32] }:$src1_mods)), (fminnum_ieee:{ *:[f32] } (VOP3Mods:{ *:[f32] } f32:{ *:[f32] }:$src2, i32:{ *:[i32] }:$src2_mods), (fmaxnum:{ *:[f32] } (VOP3Mods:{ *:[f32] } f32:{ *:[f32] }:$src0, i32:{ *:[i32] }:$src0_mods), (VOP3Mods:{ *:[f32] } f32:{ *:[f32] }:$src1, i32:{ *:[i32] }:$src1_mods))))<<P:Predicate_fmaxnum_like_nnan>>  =>  (V_MED3_F32_e64:{ *:[f32] } ?:{ *:[i32] }:$src0_mods, ?:{ *:[f32] }:$src0, ?:{ *:[i32] }:$src1_mods, ?:{ *:[f32] }:$src1, ?:{ *:[i32] }:$src2_mods, ?:{ *:[f32] }:$src2, 0:{ *:[i1] }, 0:{ *:[i32] })
        GIR_BuildMI, /*InsnID*/0, /*Opcode*/GIMT_Encode2(AMDGPU::V_MED3_F32_e64),
        GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/0, // DstI[vdst]
        GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/1, // src0_mods
        GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/0, // src0
        GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(1), /*SubOperand*/1, // src1_mods
        GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(1), /*SubOperand*/0, // src1
        GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(2), /*SubOperand*/1, // src2_mods
        GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(2), /*SubOperand*/0, // src2
        GIR_AddImm8, /*InsnID*/0, /*Imm*/0,
        GIR_AddImm8, /*InsnID*/0, /*Imm*/0,
        GIR_ConstrainSelectedInstOperands, /*InsnID*/0,
        GIR_EraseFromParent, /*InsnID*/0,
        // GIR_Coverage, 10136,
        GIR_Done,
      // Label 4692: @319046
      GIM_Try, /*On fail goto*//*Label 4693*/ GIMT_Encode4(319186), // Rule ID 10137 //
        GIM_CheckRegBankForClass, /*MI*/0, /*Op*/0, /*RC*/GIMT_Encode2(AMDGPU::VGPR_32RegClassID),
        GIM_RecordInsn, /*DefineMI*/1, /*MI*/0, /*OpIdx*/1, // MIs[1]
        GIM_CheckOpcode, /*MI*/1, GIMT_Encode2(TargetOpcode::G_FMINNUM_IEEE),
        GIM_CheckType, /*MI*/1, /*Op*/1, /*Type*/GILLT_s32,
        GIM_CheckType, /*MI*/1, /*Op*/2, /*Type*/GILLT_s32,
        GIM_RecordInsn, /*DefineMI*/2, /*MI*/0, /*OpIdx*/2, // MIs[2]
        GIM_CheckOpcode, /*MI*/2, GIMT_Encode2(TargetOpcode::G_FMINNUM_IEEE),
        GIM_CheckType, /*MI*/2, /*Op*/1, /*Type*/GILLT_s32,
        GIM_CheckType, /*MI*/2, /*Op*/2, /*Type*/GILLT_s32,
        GIM_RecordInsn, /*DefineMI*/3, /*MI*/2, /*OpIdx*/2, // MIs[3]
        GIM_CheckOpcode, /*MI*/3, GIMT_Encode2(TargetOpcode::G_FMAXNUM),
        // MIs[3] VOP3Mods:src1:src1_mods
        GIM_CheckIsSameOperand, /*MI*/3, /*OpIdx*/1, /*OtherMI*/1, /*OtherOpIdx*/2,
        // MIs[3] VOP3Mods:src0:src0_mods
        GIM_CheckIsSameOperand, /*MI*/3, /*OpIdx*/2, /*OtherMI*/1, /*OtherOpIdx*/1,
        GIM_CheckCxxInsnPredicate, /*MI*/0, /*FnId*/GIMT_Encode2(GICXXPred_MI_Predicate_fmaxnum_like_nnan),
        GIM_CheckIsSafeToFold, /*InsnID*/1,
        GIM_CheckIsSafeToFold, /*InsnID*/2,
        GIM_CheckIsSafeToFold, /*InsnID*/3,
        GIM_CheckComplexPattern, /*MI*/1, /*Op*/1, /*Renderer*/GIMT_Encode2(0), GIMT_Encode2(GICP_gi_vop3mods),
        GIM_CheckComplexPattern, /*MI*/1, /*Op*/2, /*Renderer*/GIMT_Encode2(1), GIMT_Encode2(GICP_gi_vop3mods),
        GIM_CheckComplexPattern, /*MI*/2, /*Op*/1, /*Renderer*/GIMT_Encode2(2), GIMT_Encode2(GICP_gi_vop3mods),
        // (fmaxnum:{ *:[f32] } (fminnum_ieee:{ *:[f32] } (VOP3Mods:{ *:[f32] } f32:{ *:[f32] }:$src0, i32:{ *:[i32] }:$src0_mods), (VOP3Mods:{ *:[f32] } f32:{ *:[f32] }:$src1, i32:{ *:[i32] }:$src1_mods)), (fminnum_ieee:{ *:[f32] } (VOP3Mods:{ *:[f32] } f32:{ *:[f32] }:$src2, i32:{ *:[i32] }:$src2_mods), (fmaxnum:{ *:[f32] } (VOP3Mods:{ *:[f32] } f32:{ *:[f32] }:$src1, i32:{ *:[i32] }:$src1_mods), (VOP3Mods:{ *:[f32] } f32:{ *:[f32] }:$src0, i32:{ *:[i32] }:$src0_mods))))<<P:Predicate_fmaxnum_like_nnan>>  =>  (V_MED3_F32_e64:{ *:[f32] } ?:{ *:[i32] }:$src0_mods, ?:{ *:[f32] }:$src0, ?:{ *:[i32] }:$src1_mods, ?:{ *:[f32] }:$src1, ?:{ *:[i32] }:$src2_mods, ?:{ *:[f32] }:$src2, 0:{ *:[i1] }, 0:{ *:[i32] })
        GIR_BuildMI, /*InsnID*/0, /*Opcode*/GIMT_Encode2(AMDGPU::V_MED3_F32_e64),
        GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/0, // DstI[vdst]
        GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/1, // src0_mods
        GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/0, // src0
        GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(1), /*SubOperand*/1, // src1_mods
        GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(1), /*SubOperand*/0, // src1
        GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(2), /*SubOperand*/1, // src2_mods
        GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(2), /*SubOperand*/0, // src2
        GIR_AddImm8, /*InsnID*/0, /*Imm*/0,
        GIR_AddImm8, /*InsnID*/0, /*Imm*/0,
        GIR_ConstrainSelectedInstOperands, /*InsnID*/0,
        GIR_EraseFromParent, /*InsnID*/0,
        // GIR_Coverage, 10137,
        GIR_Done,
      // Label 4693: @319186
      GIM_Try, /*On fail goto*//*Label 4694*/ GIMT_Encode4(319326), // Rule ID 10140 //
        GIM_CheckRegBankForClass, /*MI*/0, /*Op*/0, /*RC*/GIMT_Encode2(AMDGPU::VGPR_32RegClassID),
        GIM_RecordInsn, /*DefineMI*/1, /*MI*/0, /*OpIdx*/1, // MIs[1]
        GIM_CheckOpcode, /*MI*/1, GIMT_Encode2(TargetOpcode::G_FMINNUM_IEEE),
        GIM_CheckType, /*MI*/1, /*Op*/1, /*Type*/GILLT_s32,
        GIM_CheckType, /*MI*/1, /*Op*/2, /*Type*/GILLT_s32,
        GIM_RecordInsn, /*DefineMI*/2, /*MI*/0, /*OpIdx*/2, // MIs[2]
        GIM_CheckOpcode, /*MI*/2, GIMT_Encode2(TargetOpcode::G_FMINNUM_IEEE),
        GIM_CheckType, /*MI*/2, /*Op*/1, /*Type*/GILLT_s32,
        GIM_CheckType, /*MI*/2, /*Op*/2, /*Type*/GILLT_s32,
        GIM_RecordInsn, /*DefineMI*/3, /*MI*/2, /*OpIdx*/2, // MIs[3]
        GIM_CheckOpcode, /*MI*/3, GIMT_Encode2(TargetOpcode::G_FMAXNUM),
        // MIs[3] VOP3Mods:src0:src0_mods
        GIM_CheckIsSameOperand, /*MI*/3, /*OpIdx*/1, /*OtherMI*/1, /*OtherOpIdx*/2,
        // MIs[3] VOP3Mods:src1:src1_mods
        GIM_CheckIsSameOperand, /*MI*/3, /*OpIdx*/2, /*OtherMI*/1, /*OtherOpIdx*/1,
        GIM_CheckCxxInsnPredicate, /*MI*/0, /*FnId*/GIMT_Encode2(GICXXPred_MI_Predicate_fmaxnum_like_nnan),
        GIM_CheckIsSafeToFold, /*InsnID*/1,
        GIM_CheckIsSafeToFold, /*InsnID*/2,
        GIM_CheckIsSafeToFold, /*InsnID*/3,
        GIM_CheckComplexPattern, /*MI*/1, /*Op*/1, /*Renderer*/GIMT_Encode2(0), GIMT_Encode2(GICP_gi_vop3mods),
        GIM_CheckComplexPattern, /*MI*/1, /*Op*/2, /*Renderer*/GIMT_Encode2(1), GIMT_Encode2(GICP_gi_vop3mods),
        GIM_CheckComplexPattern, /*MI*/2, /*Op*/1, /*Renderer*/GIMT_Encode2(2), GIMT_Encode2(GICP_gi_vop3mods),
        // (fmaxnum:{ *:[f32] } (fminnum_ieee:{ *:[f32] } (VOP3Mods:{ *:[f32] } f32:{ *:[f32] }:$src1, i32:{ *:[i32] }:$src1_mods), (VOP3Mods:{ *:[f32] } f32:{ *:[f32] }:$src0, i32:{ *:[i32] }:$src0_mods)), (fminnum_ieee:{ *:[f32] } (VOP3Mods:{ *:[f32] } f32:{ *:[f32] }:$src2, i32:{ *:[i32] }:$src2_mods), (fmaxnum:{ *:[f32] } (VOP3Mods:{ *:[f32] } f32:{ *:[f32] }:$src0, i32:{ *:[i32] }:$src0_mods), (VOP3Mods:{ *:[f32] } f32:{ *:[f32] }:$src1, i32:{ *:[i32] }:$src1_mods))))<<P:Predicate_fmaxnum_like_nnan>>  =>  (V_MED3_F32_e64:{ *:[f32] } ?:{ *:[i32] }:$src0_mods, ?:{ *:[f32] }:$src0, ?:{ *:[i32] }:$src1_mods, ?:{ *:[f32] }:$src1, ?:{ *:[i32] }:$src2_mods, ?:{ *:[f32] }:$src2, 0:{ *:[i1] }, 0:{ *:[i32] })
        GIR_BuildMI, /*InsnID*/0, /*Opcode*/GIMT_Encode2(AMDGPU::V_MED3_F32_e64),
        GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/0, // DstI[vdst]
        GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(1), /*SubOperand*/1, // src0_mods
        GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(1), /*SubOperand*/0, // src0
        GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/1, // src1_mods
        GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/0, // src1
        GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(2), /*SubOperand*/1, // src2_mods
        GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(2), /*SubOperand*/0, // src2
        GIR_AddImm8, /*InsnID*/0, /*Imm*/0,
        GIR_AddImm8, /*InsnID*/0, /*Imm*/0,
        GIR_ConstrainSelectedInstOperands, /*InsnID*/0,
        GIR_EraseFromParent, /*InsnID*/0,
        // GIR_Coverage, 10140,
        GIR_Done,
      // Label 4694: @319326
      GIM_Try, /*On fail goto*//*Label 4695*/ GIMT_Encode4(319466), // Rule ID 10141 //
        GIM_CheckRegBankForClass, /*MI*/0, /*Op*/0, /*RC*/GIMT_Encode2(AMDGPU::VGPR_32RegClassID),
        GIM_RecordInsn, /*DefineMI*/1, /*MI*/0, /*OpIdx*/1, // MIs[1]
        GIM_CheckOpcode, /*MI*/1, GIMT_Encode2(TargetOpcode::G_FMINNUM_IEEE),
        GIM_CheckType, /*MI*/1, /*Op*/1, /*Type*/GILLT_s32,
        GIM_CheckType, /*MI*/1, /*Op*/2, /*Type*/GILLT_s32,
        GIM_RecordInsn, /*DefineMI*/2, /*MI*/0, /*OpIdx*/2, // MIs[2]
        GIM_CheckOpcode, /*MI*/2, GIMT_Encode2(TargetOpcode::G_FMINNUM_IEEE),
        GIM_CheckType, /*MI*/2, /*Op*/1, /*Type*/GILLT_s32,
        GIM_CheckType, /*MI*/2, /*Op*/2, /*Type*/GILLT_s32,
        GIM_RecordInsn, /*DefineMI*/3, /*MI*/2, /*OpIdx*/2, // MIs[3]
        GIM_CheckOpcode, /*MI*/3, GIMT_Encode2(TargetOpcode::G_FMAXNUM),
        // MIs[3] VOP3Mods:src1:src1_mods
        GIM_CheckIsSameOperand, /*MI*/3, /*OpIdx*/1, /*OtherMI*/1, /*OtherOpIdx*/1,
        // MIs[3] VOP3Mods:src0:src0_mods
        GIM_CheckIsSameOperand, /*MI*/3, /*OpIdx*/2, /*OtherMI*/1, /*OtherOpIdx*/2,
        GIM_CheckCxxInsnPredicate, /*MI*/0, /*FnId*/GIMT_Encode2(GICXXPred_MI_Predicate_fmaxnum_like_nnan),
        GIM_CheckIsSafeToFold, /*InsnID*/1,
        GIM_CheckIsSafeToFold, /*InsnID*/2,
        GIM_CheckIsSafeToFold, /*InsnID*/3,
        GIM_CheckComplexPattern, /*MI*/1, /*Op*/1, /*Renderer*/GIMT_Encode2(0), GIMT_Encode2(GICP_gi_vop3mods),
        GIM_CheckComplexPattern, /*MI*/1, /*Op*/2, /*Renderer*/GIMT_Encode2(1), GIMT_Encode2(GICP_gi_vop3mods),
        GIM_CheckComplexPattern, /*MI*/2, /*Op*/1, /*Renderer*/GIMT_Encode2(2), GIMT_Encode2(GICP_gi_vop3mods),
        // (fmaxnum:{ *:[f32] } (fminnum_ieee:{ *:[f32] } (VOP3Mods:{ *:[f32] } f32:{ *:[f32] }:$src1, i32:{ *:[i32] }:$src1_mods), (VOP3Mods:{ *:[f32] } f32:{ *:[f32] }:$src0, i32:{ *:[i32] }:$src0_mods)), (fminnum_ieee:{ *:[f32] } (VOP3Mods:{ *:[f32] } f32:{ *:[f32] }:$src2, i32:{ *:[i32] }:$src2_mods), (fmaxnum:{ *:[f32] } (VOP3Mods:{ *:[f32] } f32:{ *:[f32] }:$src1, i32:{ *:[i32] }:$src1_mods), (VOP3Mods:{ *:[f32] } f32:{ *:[f32] }:$src0, i32:{ *:[i32] }:$src0_mods))))<<P:Predicate_fmaxnum_like_nnan>>  =>  (V_MED3_F32_e64:{ *:[f32] } ?:{ *:[i32] }:$src0_mods, ?:{ *:[f32] }:$src0, ?:{ *:[i32] }:$src1_mods, ?:{ *:[f32] }:$src1, ?:{ *:[i32] }:$src2_mods, ?:{ *:[f32] }:$src2, 0:{ *:[i1] }, 0:{ *:[i32] })
        GIR_BuildMI, /*InsnID*/0, /*Opcode*/GIMT_Encode2(AMDGPU::V_MED3_F32_e64),
        GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/0, // DstI[vdst]
        GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(1), /*SubOperand*/1, // src0_mods
        GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(1), /*SubOperand*/0, // src0
        GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/1, // src1_mods
        GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/0, // src1
        GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(2), /*SubOperand*/1, // src2_mods
        GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(2), /*SubOperand*/0, // src2
        GIR_AddImm8, /*InsnID*/0, /*Imm*/0,
        GIR_AddImm8, /*InsnID*/0, /*Imm*/0,
        GIR_ConstrainSelectedInstOperands, /*InsnID*/0,
        GIR_EraseFromParent, /*InsnID*/0,
        // GIR_Coverage, 10141,
        GIR_Done,
      // Label 4695: @319466
      GIM_Try, /*On fail goto*//*Label 4696*/ GIMT_Encode4(319606), // Rule ID 10121 //
        GIM_CheckRegBankForClass, /*MI*/0, /*Op*/0, /*RC*/GIMT_Encode2(AMDGPU::VGPR_32RegClassID),
        GIM_RecordInsn, /*DefineMI*/1, /*MI*/0, /*OpIdx*/1, // MIs[1]
        GIM_CheckOpcode, /*MI*/1, GIMT_Encode2(TargetOpcode::G_FMINNUM_IEEE),
        GIM_CheckType, /*MI*/1, /*Op*/1, /*Type*/GILLT_s32,
        GIM_CheckType, /*MI*/1, /*Op*/2, /*Type*/GILLT_s32,
        GIM_RecordInsn, /*DefineMI*/2, /*MI*/0, /*OpIdx*/2, // MIs[2]
        GIM_CheckOpcode, /*MI*/2, GIMT_Encode2(TargetOpcode::G_FMINNUM_IEEE),
        GIM_CheckType, /*MI*/2, /*Op*/1, /*Type*/GILLT_s32,
        GIM_CheckType, /*MI*/2, /*Op*/2, /*Type*/GILLT_s32,
        GIM_RecordInsn, /*DefineMI*/3, /*MI*/2, /*OpIdx*/2, // MIs[3]
        GIM_CheckOpcode, /*MI*/3, GIMT_Encode2(TargetOpcode::G_FMAXNUM_IEEE),
        // MIs[3] VOP3Mods:src0:src0_mods
        GIM_CheckIsSameOperand, /*MI*/3, /*OpIdx*/1, /*OtherMI*/1, /*OtherOpIdx*/1,
        // MIs[3] VOP3Mods:src1:src1_mods
        GIM_CheckIsSameOperand, /*MI*/3, /*OpIdx*/2, /*OtherMI*/1, /*OtherOpIdx*/2,
        GIM_CheckCxxInsnPredicate, /*MI*/0, /*FnId*/GIMT_Encode2(GICXXPred_MI_Predicate_fmaxnum_like_nnan),
        GIM_CheckIsSafeToFold, /*InsnID*/1,
        GIM_CheckIsSafeToFold, /*InsnID*/2,
        GIM_CheckIsSafeToFold, /*InsnID*/3,
        GIM_CheckComplexPattern, /*MI*/1, /*Op*/1, /*Renderer*/GIMT_Encode2(0), GIMT_Encode2(GICP_gi_vop3mods),
        GIM_CheckComplexPattern, /*MI*/1, /*Op*/2, /*Renderer*/GIMT_Encode2(1), GIMT_Encode2(GICP_gi_vop3mods),
        GIM_CheckComplexPattern, /*MI*/2, /*Op*/1, /*Renderer*/GIMT_Encode2(2), GIMT_Encode2(GICP_gi_vop3mods),
        // (fmaxnum:{ *:[f32] } (fminnum_ieee:{ *:[f32] } (VOP3Mods:{ *:[f32] } f32:{ *:[f32] }:$src0, i32:{ *:[i32] }:$src0_mods), (VOP3Mods:{ *:[f32] } f32:{ *:[f32] }:$src1, i32:{ *:[i32] }:$src1_mods)), (fminnum_ieee:{ *:[f32] } (VOP3Mods:{ *:[f32] } f32:{ *:[f32] }:$src2, i32:{ *:[i32] }:$src2_mods), (fmaxnum_ieee:{ *:[f32] } (VOP3Mods:{ *:[f32] } f32:{ *:[f32] }:$src0, i32:{ *:[i32] }:$src0_mods), (VOP3Mods:{ *:[f32] } f32:{ *:[f32] }:$src1, i32:{ *:[i32] }:$src1_mods))))<<P:Predicate_fmaxnum_like_nnan>>  =>  (V_MED3_F32_e64:{ *:[f32] } ?:{ *:[i32] }:$src0_mods, ?:{ *:[f32] }:$src0, ?:{ *:[i32] }:$src1_mods, ?:{ *:[f32] }:$src1, ?:{ *:[i32] }:$src2_mods, ?:{ *:[f32] }:$src2, 0:{ *:[i1] }, 0:{ *:[i32] })
        GIR_BuildMI, /*InsnID*/0, /*Opcode*/GIMT_Encode2(AMDGPU::V_MED3_F32_e64),
        GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/0, // DstI[vdst]
        GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/1, // src0_mods
        GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/0, // src0
        GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(1), /*SubOperand*/1, // src1_mods
        GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(1), /*SubOperand*/0, // src1
        GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(2), /*SubOperand*/1, // src2_mods
        GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(2), /*SubOperand*/0, // src2
        GIR_AddImm8, /*InsnID*/0, /*Imm*/0,
        GIR_AddImm8, /*InsnID*/0, /*Imm*/0,
        GIR_ConstrainSelectedInstOperands, /*InsnID*/0,
        GIR_EraseFromParent, /*InsnID*/0,
        // GIR_Coverage, 10121,
        GIR_Done,
      // Label 4696: @319606
      GIM_Try, /*On fail goto*//*Label 4697*/ GIMT_Encode4(319746), // Rule ID 10122 //
        GIM_CheckRegBankForClass, /*MI*/0, /*Op*/0, /*RC*/GIMT_Encode2(AMDGPU::VGPR_32RegClassID),
        GIM_RecordInsn, /*DefineMI*/1, /*MI*/0, /*OpIdx*/1, // MIs[1]
        GIM_CheckOpcode, /*MI*/1, GIMT_Encode2(TargetOpcode::G_FMINNUM_IEEE),
        GIM_CheckType, /*MI*/1, /*Op*/1, /*Type*/GILLT_s32,
        GIM_CheckType, /*MI*/1, /*Op*/2, /*Type*/GILLT_s32,
        GIM_RecordInsn, /*DefineMI*/2, /*MI*/0, /*OpIdx*/2, // MIs[2]
        GIM_CheckOpcode, /*MI*/2, GIMT_Encode2(TargetOpcode::G_FMINNUM_IEEE),
        GIM_CheckType, /*MI*/2, /*Op*/1, /*Type*/GILLT_s32,
        GIM_CheckType, /*MI*/2, /*Op*/2, /*Type*/GILLT_s32,
        GIM_RecordInsn, /*DefineMI*/3, /*MI*/2, /*OpIdx*/2, // MIs[3]
        GIM_CheckOpcode, /*MI*/3, GIMT_Encode2(TargetOpcode::G_FMAXNUM_IEEE),
        // MIs[3] VOP3Mods:src1:src1_mods
        GIM_CheckIsSameOperand, /*MI*/3, /*OpIdx*/1, /*OtherMI*/1, /*OtherOpIdx*/2,
        // MIs[3] VOP3Mods:src0:src0_mods
        GIM_CheckIsSameOperand, /*MI*/3, /*OpIdx*/2, /*OtherMI*/1, /*OtherOpIdx*/1,
        GIM_CheckCxxInsnPredicate, /*MI*/0, /*FnId*/GIMT_Encode2(GICXXPred_MI_Predicate_fmaxnum_like_nnan),
        GIM_CheckIsSafeToFold, /*InsnID*/1,
        GIM_CheckIsSafeToFold, /*InsnID*/2,
        GIM_CheckIsSafeToFold, /*InsnID*/3,
        GIM_CheckComplexPattern, /*MI*/1, /*Op*/1, /*Renderer*/GIMT_Encode2(0), GIMT_Encode2(GICP_gi_vop3mods),
        GIM_CheckComplexPattern, /*MI*/1, /*Op*/2, /*Renderer*/GIMT_Encode2(1), GIMT_Encode2(GICP_gi_vop3mods),
        GIM_CheckComplexPattern, /*MI*/2, /*Op*/1, /*Renderer*/GIMT_Encode2(2), GIMT_Encode2(GICP_gi_vop3mods),
        // (fmaxnum:{ *:[f32] } (fminnum_ieee:{ *:[f32] } (VOP3Mods:{ *:[f32] } f32:{ *:[f32] }:$src0, i32:{ *:[i32] }:$src0_mods), (VOP3Mods:{ *:[f32] } f32:{ *:[f32] }:$src1, i32:{ *:[i32] }:$src1_mods)), (fminnum_ieee:{ *:[f32] } (VOP3Mods:{ *:[f32] } f32:{ *:[f32] }:$src2, i32:{ *:[i32] }:$src2_mods), (fmaxnum_ieee:{ *:[f32] } (VOP3Mods:{ *:[f32] } f32:{ *:[f32] }:$src1, i32:{ *:[i32] }:$src1_mods), (VOP3Mods:{ *:[f32] } f32:{ *:[f32] }:$src0, i32:{ *:[i32] }:$src0_mods))))<<P:Predicate_fmaxnum_like_nnan>>  =>  (V_MED3_F32_e64:{ *:[f32] } ?:{ *:[i32] }:$src0_mods, ?:{ *:[f32] }:$src0, ?:{ *:[i32] }:$src1_mods, ?:{ *:[f32] }:$src1, ?:{ *:[i32] }:$src2_mods, ?:{ *:[f32] }:$src2, 0:{ *:[i1] }, 0:{ *:[i32] })
        GIR_BuildMI, /*InsnID*/0, /*Opcode*/GIMT_Encode2(AMDGPU::V_MED3_F32_e64),
        GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/0, // DstI[vdst]
        GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/1, // src0_mods
        GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/0, // src0
        GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(1), /*SubOperand*/1, // src1_mods
        GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(1), /*SubOperand*/0, // src1
        GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(2), /*SubOperand*/1, // src2_mods
        GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(2), /*SubOperand*/0, // src2
        GIR_AddImm8, /*InsnID*/0, /*Imm*/0,
        GIR_AddImm8, /*InsnID*/0, /*Imm*/0,
        GIR_ConstrainSelectedInstOperands, /*InsnID*/0,
        GIR_EraseFromParent, /*InsnID*/0,
        // GIR_Coverage, 10122,
        GIR_Done,
      // Label 4697: @319746
      GIM_Try, /*On fail goto*//*Label 4698*/ GIMT_Encode4(319886), // Rule ID 10125 //
        GIM_CheckRegBankForClass, /*MI*/0, /*Op*/0, /*RC*/GIMT_Encode2(AMDGPU::VGPR_32RegClassID),
        GIM_RecordInsn, /*DefineMI*/1, /*MI*/0, /*OpIdx*/1, // MIs[1]
        GIM_CheckOpcode, /*MI*/1, GIMT_Encode2(TargetOpcode::G_FMINNUM_IEEE),
        GIM_CheckType, /*MI*/1, /*Op*/1, /*Type*/GILLT_s32,
        GIM_CheckType, /*MI*/1, /*Op*/2, /*Type*/GILLT_s32,
        GIM_RecordInsn, /*DefineMI*/2, /*MI*/0, /*OpIdx*/2, // MIs[2]
        GIM_CheckOpcode, /*MI*/2, GIMT_Encode2(TargetOpcode::G_FMINNUM_IEEE),
        GIM_CheckType, /*MI*/2, /*Op*/1, /*Type*/GILLT_s32,
        GIM_CheckType, /*MI*/2, /*Op*/2, /*Type*/GILLT_s32,
        GIM_RecordInsn, /*DefineMI*/3, /*MI*/2, /*OpIdx*/2, // MIs[3]
        GIM_CheckOpcode, /*MI*/3, GIMT_Encode2(TargetOpcode::G_FMAXNUM_IEEE),
        // MIs[3] VOP3Mods:src0:src0_mods
        GIM_CheckIsSameOperand, /*MI*/3, /*OpIdx*/1, /*OtherMI*/1, /*OtherOpIdx*/2,
        // MIs[3] VOP3Mods:src1:src1_mods
        GIM_CheckIsSameOperand, /*MI*/3, /*OpIdx*/2, /*OtherMI*/1, /*OtherOpIdx*/1,
        GIM_CheckCxxInsnPredicate, /*MI*/0, /*FnId*/GIMT_Encode2(GICXXPred_MI_Predicate_fmaxnum_like_nnan),
        GIM_CheckIsSafeToFold, /*InsnID*/1,
        GIM_CheckIsSafeToFold, /*InsnID*/2,
        GIM_CheckIsSafeToFold, /*InsnID*/3,
        GIM_CheckComplexPattern, /*MI*/1, /*Op*/1, /*Renderer*/GIMT_Encode2(0), GIMT_Encode2(GICP_gi_vop3mods),
        GIM_CheckComplexPattern, /*MI*/1, /*Op*/2, /*Renderer*/GIMT_Encode2(1), GIMT_Encode2(GICP_gi_vop3mods),
        GIM_CheckComplexPattern, /*MI*/2, /*Op*/1, /*Renderer*/GIMT_Encode2(2), GIMT_Encode2(GICP_gi_vop3mods),
        // (fmaxnum:{ *:[f32] } (fminnum_ieee:{ *:[f32] } (VOP3Mods:{ *:[f32] } f32:{ *:[f32] }:$src1, i32:{ *:[i32] }:$src1_mods), (VOP3Mods:{ *:[f32] } f32:{ *:[f32] }:$src0, i32:{ *:[i32] }:$src0_mods)), (fminnum_ieee:{ *:[f32] } (VOP3Mods:{ *:[f32] } f32:{ *:[f32] }:$src2, i32:{ *:[i32] }:$src2_mods), (fmaxnum_ieee:{ *:[f32] } (VOP3Mods:{ *:[f32] } f32:{ *:[f32] }:$src0, i32:{ *:[i32] }:$src0_mods), (VOP3Mods:{ *:[f32] } f32:{ *:[f32] }:$src1, i32:{ *:[i32] }:$src1_mods))))<<P:Predicate_fmaxnum_like_nnan>>  =>  (V_MED3_F32_e64:{ *:[f32] } ?:{ *:[i32] }:$src0_mods, ?:{ *:[f32] }:$src0, ?:{ *:[i32] }:$src1_mods, ?:{ *:[f32] }:$src1, ?:{ *:[i32] }:$src2_mods, ?:{ *:[f32] }:$src2, 0:{ *:[i1] }, 0:{ *:[i32] })
        GIR_BuildMI, /*InsnID*/0, /*Opcode*/GIMT_Encode2(AMDGPU::V_MED3_F32_e64),
        GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/0, // DstI[vdst]
        GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(1), /*SubOperand*/1, // src0_mods
        GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(1), /*SubOperand*/0, // src0
        GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/1, // src1_mods
        GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/0, // src1
        GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(2), /*SubOperand*/1, // src2_mods
        GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(2), /*SubOperand*/0, // src2
        GIR_AddImm8, /*InsnID*/0, /*Imm*/0,
        GIR_AddImm8, /*InsnID*/0, /*Imm*/0,
        GIR_ConstrainSelectedInstOperands, /*InsnID*/0,
        GIR_EraseFromParent, /*InsnID*/0,
        // GIR_Coverage, 10125,
        GIR_Done,
      // Label 4698: @319886
      GIM_Try, /*On fail goto*//*Label 4699*/ GIMT_Encode4(320026), // Rule ID 10126 //
        GIM_CheckRegBankForClass, /*MI*/0, /*Op*/0, /*RC*/GIMT_Encode2(AMDGPU::VGPR_32RegClassID),
        GIM_RecordInsn, /*DefineMI*/1, /*MI*/0, /*OpIdx*/1, // MIs[1]
        GIM_CheckOpcode, /*MI*/1, GIMT_Encode2(TargetOpcode::G_FMINNUM_IEEE),
        GIM_CheckType, /*MI*/1, /*Op*/1, /*Type*/GILLT_s32,
        GIM_CheckType, /*MI*/1, /*Op*/2, /*Type*/GILLT_s32,
        GIM_RecordInsn, /*DefineMI*/2, /*MI*/0, /*OpIdx*/2, // MIs[2]
        GIM_CheckOpcode, /*MI*/2, GIMT_Encode2(TargetOpcode::G_FMINNUM_IEEE),
        GIM_CheckType, /*MI*/2, /*Op*/1, /*Type*/GILLT_s32,
        GIM_CheckType, /*MI*/2, /*Op*/2, /*Type*/GILLT_s32,
        GIM_RecordInsn, /*DefineMI*/3, /*MI*/2, /*OpIdx*/2, // MIs[3]
        GIM_CheckOpcode, /*MI*/3, GIMT_Encode2(TargetOpcode::G_FMAXNUM_IEEE),
        // MIs[3] VOP3Mods:src1:src1_mods
        GIM_CheckIsSameOperand, /*MI*/3, /*OpIdx*/1, /*OtherMI*/1, /*OtherOpIdx*/1,
        // MIs[3] VOP3Mods:src0:src0_mods
        GIM_CheckIsSameOperand, /*MI*/3, /*OpIdx*/2, /*OtherMI*/1, /*OtherOpIdx*/2,
        GIM_CheckCxxInsnPredicate, /*MI*/0, /*FnId*/GIMT_Encode2(GICXXPred_MI_Predicate_fmaxnum_like_nnan),
        GIM_CheckIsSafeToFold, /*InsnID*/1,
        GIM_CheckIsSafeToFold, /*InsnID*/2,
        GIM_CheckIsSafeToFold, /*InsnID*/3,
        GIM_CheckComplexPattern, /*MI*/1, /*Op*/1, /*Renderer*/GIMT_Encode2(0), GIMT_Encode2(GICP_gi_vop3mods),
        GIM_CheckComplexPattern, /*MI*/1, /*Op*/2, /*Renderer*/GIMT_Encode2(1), GIMT_Encode2(GICP_gi_vop3mods),
        GIM_CheckComplexPattern, /*MI*/2, /*Op*/1, /*Renderer*/GIMT_Encode2(2), GIMT_Encode2(GICP_gi_vop3mods),
        // (fmaxnum:{ *:[f32] } (fminnum_ieee:{ *:[f32] } (VOP3Mods:{ *:[f32] } f32:{ *:[f32] }:$src1, i32:{ *:[i32] }:$src1_mods), (VOP3Mods:{ *:[f32] } f32:{ *:[f32] }:$src0, i32:{ *:[i32] }:$src0_mods)), (fminnum_ieee:{ *:[f32] } (VOP3Mods:{ *:[f32] } f32:{ *:[f32] }:$src2, i32:{ *:[i32] }:$src2_mods), (fmaxnum_ieee:{ *:[f32] } (VOP3Mods:{ *:[f32] } f32:{ *:[f32] }:$src1, i32:{ *:[i32] }:$src1_mods), (VOP3Mods:{ *:[f32] } f32:{ *:[f32] }:$src0, i32:{ *:[i32] }:$src0_mods))))<<P:Predicate_fmaxnum_like_nnan>>  =>  (V_MED3_F32_e64:{ *:[f32] } ?:{ *:[i32] }:$src0_mods, ?:{ *:[f32] }:$src0, ?:{ *:[i32] }:$src1_mods, ?:{ *:[f32] }:$src1, ?:{ *:[i32] }:$src2_mods, ?:{ *:[f32] }:$src2, 0:{ *:[i1] }, 0:{ *:[i32] })
        GIR_BuildMI, /*InsnID*/0, /*Opcode*/GIMT_Encode2(AMDGPU::V_MED3_F32_e64),
        GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/0, // DstI[vdst]
        GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(1), /*SubOperand*/1, // src0_mods
        GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(1), /*SubOperand*/0, // src0
        GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/1, // src1_mods
        GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/0, // src1
        GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(2), /*SubOperand*/1, // src2_mods
        GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(2), /*SubOperand*/0, // src2
        GIR_AddImm8, /*InsnID*/0, /*Imm*/0,
        GIR_AddImm8, /*InsnID*/0, /*Imm*/0,
        GIR_ConstrainSelectedInstOperands, /*InsnID*/0,
        GIR_EraseFromParent, /*InsnID*/0,
        // GIR_Coverage, 10126,
        GIR_Done,
      // Label 4699: @320026
      GIM_Try, /*On fail goto*//*Label 4700*/ GIMT_Encode4(320166), // Rule ID 6491 //
        GIM_CheckRegBankForClass, /*MI*/0, /*Op*/0, /*RC*/GIMT_Encode2(AMDGPU::VGPR_32RegClassID),
        GIM_RecordInsn, /*DefineMI*/1, /*MI*/0, /*OpIdx*/1, // MIs[1]
        GIM_CheckOpcode, /*MI*/1, GIMT_Encode2(TargetOpcode::G_FMINNUM_IEEE),
        GIM_CheckType, /*MI*/1, /*Op*/1, /*Type*/GILLT_s32,
        GIM_CheckType, /*MI*/1, /*Op*/2, /*Type*/GILLT_s32,
        GIM_RecordInsn, /*DefineMI*/2, /*MI*/0, /*OpIdx*/2, // MIs[2]
        GIM_CheckOpcode, /*MI*/2, GIMT_Encode2(TargetOpcode::G_FMINNUM_IEEE),
        GIM_CheckType, /*MI*/2, /*Op*/1, /*Type*/GILLT_s32,
        GIM_CheckType, /*MI*/2, /*Op*/2, /*Type*/GILLT_s32,
        GIM_RecordInsn, /*DefineMI*/3, /*MI*/2, /*OpIdx*/1, // MIs[3]
        GIM_CheckOpcode, /*MI*/3, GIMT_Encode2(TargetOpcode::G_FMAXNUM),
        // MIs[3] VOP3Mods:src0:src0_mods
        GIM_CheckIsSameOperand, /*MI*/3, /*OpIdx*/1, /*OtherMI*/1, /*OtherOpIdx*/1,
        // MIs[3] VOP3Mods:src1:src1_mods
        GIM_CheckIsSameOperand, /*MI*/3, /*OpIdx*/2, /*OtherMI*/1, /*OtherOpIdx*/2,
        GIM_CheckCxxInsnPredicate, /*MI*/0, /*FnId*/GIMT_Encode2(GICXXPred_MI_Predicate_fmaxnum_like_nnan),
        GIM_CheckIsSafeToFold, /*InsnID*/1,
        GIM_CheckIsSafeToFold, /*InsnID*/2,
        GIM_CheckIsSafeToFold, /*InsnID*/3,
        GIM_CheckComplexPattern, /*MI*/1, /*Op*/1, /*Renderer*/GIMT_Encode2(0), GIMT_Encode2(GICP_gi_vop3mods),
        GIM_CheckComplexPattern, /*MI*/1, /*Op*/2, /*Renderer*/GIMT_Encode2(1), GIMT_Encode2(GICP_gi_vop3mods),
        GIM_CheckComplexPattern, /*MI*/2, /*Op*/2, /*Renderer*/GIMT_Encode2(2), GIMT_Encode2(GICP_gi_vop3mods),
        // (fmaxnum:{ *:[f32] } (fminnum_ieee:{ *:[f32] } (VOP3Mods:{ *:[f32] } f32:{ *:[f32] }:$src0, i32:{ *:[i32] }:$src0_mods), (VOP3Mods:{ *:[f32] } f32:{ *:[f32] }:$src1, i32:{ *:[i32] }:$src1_mods)), (fminnum_ieee:{ *:[f32] } (fmaxnum:{ *:[f32] } (VOP3Mods:{ *:[f32] } f32:{ *:[f32] }:$src0, i32:{ *:[i32] }:$src0_mods), (VOP3Mods:{ *:[f32] } f32:{ *:[f32] }:$src1, i32:{ *:[i32] }:$src1_mods)), (VOP3Mods:{ *:[f32] } f32:{ *:[f32] }:$src2, i32:{ *:[i32] }:$src2_mods)))<<P:Predicate_fmaxnum_like_nnan>>  =>  (V_MED3_F32_e64:{ *:[f32] } ?:{ *:[i32] }:$src0_mods, ?:{ *:[f32] }:$src0, ?:{ *:[i32] }:$src1_mods, ?:{ *:[f32] }:$src1, ?:{ *:[i32] }:$src2_mods, ?:{ *:[f32] }:$src2, 0:{ *:[i1] }, 0:{ *:[i32] })
        GIR_BuildMI, /*InsnID*/0, /*Opcode*/GIMT_Encode2(AMDGPU::V_MED3_F32_e64),
        GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/0, // DstI[vdst]
        GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/1, // src0_mods
        GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/0, // src0
        GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(1), /*SubOperand*/1, // src1_mods
        GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(1), /*SubOperand*/0, // src1
        GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(2), /*SubOperand*/1, // src2_mods
        GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(2), /*SubOperand*/0, // src2
        GIR_AddImm8, /*InsnID*/0, /*Imm*/0,
        GIR_AddImm8, /*InsnID*/0, /*Imm*/0,
        GIR_ConstrainSelectedInstOperands, /*InsnID*/0,
        GIR_EraseFromParent, /*InsnID*/0,
        // GIR_Coverage, 6491,
        GIR_Done,
      // Label 4700: @320166
      GIM_Try, /*On fail goto*//*Label 4701*/ GIMT_Encode4(320306), // Rule ID 10135 //
        GIM_CheckRegBankForClass, /*MI*/0, /*Op*/0, /*RC*/GIMT_Encode2(AMDGPU::VGPR_32RegClassID),
        GIM_RecordInsn, /*DefineMI*/1, /*MI*/0, /*OpIdx*/1, // MIs[1]
        GIM_CheckOpcode, /*MI*/1, GIMT_Encode2(TargetOpcode::G_FMINNUM_IEEE),
        GIM_CheckType, /*MI*/1, /*Op*/1, /*Type*/GILLT_s32,
        GIM_CheckType, /*MI*/1, /*Op*/2, /*Type*/GILLT_s32,
        GIM_RecordInsn, /*DefineMI*/2, /*MI*/0, /*OpIdx*/2, // MIs[2]
        GIM_CheckOpcode, /*MI*/2, GIMT_Encode2(TargetOpcode::G_FMINNUM_IEEE),
        GIM_CheckType, /*MI*/2, /*Op*/1, /*Type*/GILLT_s32,
        GIM_CheckType, /*MI*/2, /*Op*/2, /*Type*/GILLT_s32,
        GIM_RecordInsn, /*DefineMI*/3, /*MI*/2, /*OpIdx*/1, // MIs[3]
        GIM_CheckOpcode, /*MI*/3, GIMT_Encode2(TargetOpcode::G_FMAXNUM),
        // MIs[3] VOP3Mods:src1:src1_mods
        GIM_CheckIsSameOperand, /*MI*/3, /*OpIdx*/1, /*OtherMI*/1, /*OtherOpIdx*/2,
        // MIs[3] VOP3Mods:src0:src0_mods
        GIM_CheckIsSameOperand, /*MI*/3, /*OpIdx*/2, /*OtherMI*/1, /*OtherOpIdx*/1,
        GIM_CheckCxxInsnPredicate, /*MI*/0, /*FnId*/GIMT_Encode2(GICXXPred_MI_Predicate_fmaxnum_like_nnan),
        GIM_CheckIsSafeToFold, /*InsnID*/1,
        GIM_CheckIsSafeToFold, /*InsnID*/2,
        GIM_CheckIsSafeToFold, /*InsnID*/3,
        GIM_CheckComplexPattern, /*MI*/1, /*Op*/1, /*Renderer*/GIMT_Encode2(0), GIMT_Encode2(GICP_gi_vop3mods),
        GIM_CheckComplexPattern, /*MI*/1, /*Op*/2, /*Renderer*/GIMT_Encode2(1), GIMT_Encode2(GICP_gi_vop3mods),
        GIM_CheckComplexPattern, /*MI*/2, /*Op*/2, /*Renderer*/GIMT_Encode2(2), GIMT_Encode2(GICP_gi_vop3mods),
        // (fmaxnum:{ *:[f32] } (fminnum_ieee:{ *:[f32] } (VOP3Mods:{ *:[f32] } f32:{ *:[f32] }:$src0, i32:{ *:[i32] }:$src0_mods), (VOP3Mods:{ *:[f32] } f32:{ *:[f32] }:$src1, i32:{ *:[i32] }:$src1_mods)), (fminnum_ieee:{ *:[f32] } (fmaxnum:{ *:[f32] } (VOP3Mods:{ *:[f32] } f32:{ *:[f32] }:$src1, i32:{ *:[i32] }:$src1_mods), (VOP3Mods:{ *:[f32] } f32:{ *:[f32] }:$src0, i32:{ *:[i32] }:$src0_mods)), (VOP3Mods:{ *:[f32] } f32:{ *:[f32] }:$src2, i32:{ *:[i32] }:$src2_mods)))<<P:Predicate_fmaxnum_like_nnan>>  =>  (V_MED3_F32_e64:{ *:[f32] } ?:{ *:[i32] }:$src0_mods, ?:{ *:[f32] }:$src0, ?:{ *:[i32] }:$src1_mods, ?:{ *:[f32] }:$src1, ?:{ *:[i32] }:$src2_mods, ?:{ *:[f32] }:$src2, 0:{ *:[i1] }, 0:{ *:[i32] })
        GIR_BuildMI, /*InsnID*/0, /*Opcode*/GIMT_Encode2(AMDGPU::V_MED3_F32_e64),
        GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/0, // DstI[vdst]
        GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/1, // src0_mods
        GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/0, // src0
        GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(1), /*SubOperand*/1, // src1_mods
        GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(1), /*SubOperand*/0, // src1
        GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(2), /*SubOperand*/1, // src2_mods
        GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(2), /*SubOperand*/0, // src2
        GIR_AddImm8, /*InsnID*/0, /*Imm*/0,
        GIR_AddImm8, /*InsnID*/0, /*Imm*/0,
        GIR_ConstrainSelectedInstOperands, /*InsnID*/0,
        GIR_EraseFromParent, /*InsnID*/0,
        // GIR_Coverage, 10135,
        GIR_Done,
      // Label 4701: @320306
      GIM_Try, /*On fail goto*//*Label 4702*/ GIMT_Encode4(320446), // Rule ID 10138 //
        GIM_CheckRegBankForClass, /*MI*/0, /*Op*/0, /*RC*/GIMT_Encode2(AMDGPU::VGPR_32RegClassID),
        GIM_RecordInsn, /*DefineMI*/1, /*MI*/0, /*OpIdx*/1, // MIs[1]
        GIM_CheckOpcode, /*MI*/1, GIMT_Encode2(TargetOpcode::G_FMINNUM_IEEE),
        GIM_CheckType, /*MI*/1, /*Op*/1, /*Type*/GILLT_s32,
        GIM_CheckType, /*MI*/1, /*Op*/2, /*Type*/GILLT_s32,
        GIM_RecordInsn, /*DefineMI*/2, /*MI*/0, /*OpIdx*/2, // MIs[2]
        GIM_CheckOpcode, /*MI*/2, GIMT_Encode2(TargetOpcode::G_FMINNUM_IEEE),
        GIM_CheckType, /*MI*/2, /*Op*/1, /*Type*/GILLT_s32,
        GIM_CheckType, /*MI*/2, /*Op*/2, /*Type*/GILLT_s32,
        GIM_RecordInsn, /*DefineMI*/3, /*MI*/2, /*OpIdx*/1, // MIs[3]
        GIM_CheckOpcode, /*MI*/3, GIMT_Encode2(TargetOpcode::G_FMAXNUM),
        // MIs[3] VOP3Mods:src0:src0_mods
        GIM_CheckIsSameOperand, /*MI*/3, /*OpIdx*/1, /*OtherMI*/1, /*OtherOpIdx*/2,
        // MIs[3] VOP3Mods:src1:src1_mods
        GIM_CheckIsSameOperand, /*MI*/3, /*OpIdx*/2, /*OtherMI*/1, /*OtherOpIdx*/1,
        GIM_CheckCxxInsnPredicate, /*MI*/0, /*FnId*/GIMT_Encode2(GICXXPred_MI_Predicate_fmaxnum_like_nnan),
        GIM_CheckIsSafeToFold, /*InsnID*/1,
        GIM_CheckIsSafeToFold, /*InsnID*/2,
        GIM_CheckIsSafeToFold, /*InsnID*/3,
        GIM_CheckComplexPattern, /*MI*/1, /*Op*/1, /*Renderer*/GIMT_Encode2(0), GIMT_Encode2(GICP_gi_vop3mods),
        GIM_CheckComplexPattern, /*MI*/1, /*Op*/2, /*Renderer*/GIMT_Encode2(1), GIMT_Encode2(GICP_gi_vop3mods),
        GIM_CheckComplexPattern, /*MI*/2, /*Op*/2, /*Renderer*/GIMT_Encode2(2), GIMT_Encode2(GICP_gi_vop3mods),
        // (fmaxnum:{ *:[f32] } (fminnum_ieee:{ *:[f32] } (VOP3Mods:{ *:[f32] } f32:{ *:[f32] }:$src1, i32:{ *:[i32] }:$src1_mods), (VOP3Mods:{ *:[f32] } f32:{ *:[f32] }:$src0, i32:{ *:[i32] }:$src0_mods)), (fminnum_ieee:{ *:[f32] } (fmaxnum:{ *:[f32] } (VOP3Mods:{ *:[f32] } f32:{ *:[f32] }:$src0, i32:{ *:[i32] }:$src0_mods), (VOP3Mods:{ *:[f32] } f32:{ *:[f32] }:$src1, i32:{ *:[i32] }:$src1_mods)), (VOP3Mods:{ *:[f32] } f32:{ *:[f32] }:$src2, i32:{ *:[i32] }:$src2_mods)))<<P:Predicate_fmaxnum_like_nnan>>  =>  (V_MED3_F32_e64:{ *:[f32] } ?:{ *:[i32] }:$src0_mods, ?:{ *:[f32] }:$src0, ?:{ *:[i32] }:$src1_mods, ?:{ *:[f32] }:$src1, ?:{ *:[i32] }:$src2_mods, ?:{ *:[f32] }:$src2, 0:{ *:[i1] }, 0:{ *:[i32] })
        GIR_BuildMI, /*InsnID*/0, /*Opcode*/GIMT_Encode2(AMDGPU::V_MED3_F32_e64),
        GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/0, // DstI[vdst]
        GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(1), /*SubOperand*/1, // src0_mods
        GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(1), /*SubOperand*/0, // src0
        GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/1, // src1_mods
        GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/0, // src1
        GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(2), /*SubOperand*/1, // src2_mods
        GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(2), /*SubOperand*/0, // src2
        GIR_AddImm8, /*InsnID*/0, /*Imm*/0,
        GIR_AddImm8, /*InsnID*/0, /*Imm*/0,
        GIR_ConstrainSelectedInstOperands, /*InsnID*/0,
        GIR_EraseFromParent, /*InsnID*/0,
        // GIR_Coverage, 10138,
        GIR_Done,
      // Label 4702: @320446
      GIM_Try, /*On fail goto*//*Label 4703*/ GIMT_Encode4(320586), // Rule ID 10139 //
        GIM_CheckRegBankForClass, /*MI*/0, /*Op*/0, /*RC*/GIMT_Encode2(AMDGPU::VGPR_32RegClassID),
        GIM_RecordInsn, /*DefineMI*/1, /*MI*/0, /*OpIdx*/1, // MIs[1]
        GIM_CheckOpcode, /*MI*/1, GIMT_Encode2(TargetOpcode::G_FMINNUM_IEEE),
        GIM_CheckType, /*MI*/1, /*Op*/1, /*Type*/GILLT_s32,
        GIM_CheckType, /*MI*/1, /*Op*/2, /*Type*/GILLT_s32,
        GIM_RecordInsn, /*DefineMI*/2, /*MI*/0, /*OpIdx*/2, // MIs[2]
        GIM_CheckOpcode, /*MI*/2, GIMT_Encode2(TargetOpcode::G_FMINNUM_IEEE),
        GIM_CheckType, /*MI*/2, /*Op*/1, /*Type*/GILLT_s32,
        GIM_CheckType, /*MI*/2, /*Op*/2, /*Type*/GILLT_s32,
        GIM_RecordInsn, /*DefineMI*/3, /*MI*/2, /*OpIdx*/1, // MIs[3]
        GIM_CheckOpcode, /*MI*/3, GIMT_Encode2(TargetOpcode::G_FMAXNUM),
        // MIs[3] VOP3Mods:src1:src1_mods
        GIM_CheckIsSameOperand, /*MI*/3, /*OpIdx*/1, /*OtherMI*/1, /*OtherOpIdx*/1,
        // MIs[3] VOP3Mods:src0:src0_mods
        GIM_CheckIsSameOperand, /*MI*/3, /*OpIdx*/2, /*OtherMI*/1, /*OtherOpIdx*/2,
        GIM_CheckCxxInsnPredicate, /*MI*/0, /*FnId*/GIMT_Encode2(GICXXPred_MI_Predicate_fmaxnum_like_nnan),
        GIM_CheckIsSafeToFold, /*InsnID*/1,
        GIM_CheckIsSafeToFold, /*InsnID*/2,
        GIM_CheckIsSafeToFold, /*InsnID*/3,
        GIM_CheckComplexPattern, /*MI*/1, /*Op*/1, /*Renderer*/GIMT_Encode2(0), GIMT_Encode2(GICP_gi_vop3mods),
        GIM_CheckComplexPattern, /*MI*/1, /*Op*/2, /*Renderer*/GIMT_Encode2(1), GIMT_Encode2(GICP_gi_vop3mods),
        GIM_CheckComplexPattern, /*MI*/2, /*Op*/2, /*Renderer*/GIMT_Encode2(2), GIMT_Encode2(GICP_gi_vop3mods),
        // (fmaxnum:{ *:[f32] } (fminnum_ieee:{ *:[f32] } (VOP3Mods:{ *:[f32] } f32:{ *:[f32] }:$src1, i32:{ *:[i32] }:$src1_mods), (VOP3Mods:{ *:[f32] } f32:{ *:[f32] }:$src0, i32:{ *:[i32] }:$src0_mods)), (fminnum_ieee:{ *:[f32] } (fmaxnum:{ *:[f32] } (VOP3Mods:{ *:[f32] } f32:{ *:[f32] }:$src1, i32:{ *:[i32] }:$src1_mods), (VOP3Mods:{ *:[f32] } f32:{ *:[f32] }:$src0, i32:{ *:[i32] }:$src0_mods)), (VOP3Mods:{ *:[f32] } f32:{ *:[f32] }:$src2, i32:{ *:[i32] }:$src2_mods)))<<P:Predicate_fmaxnum_like_nnan>>  =>  (V_MED3_F32_e64:{ *:[f32] } ?:{ *:[i32] }:$src0_mods, ?:{ *:[f32] }:$src0, ?:{ *:[i32] }:$src1_mods, ?:{ *:[f32] }:$src1, ?:{ *:[i32] }:$src2_mods, ?:{ *:[f32] }:$src2, 0:{ *:[i1] }, 0:{ *:[i32] })
        GIR_BuildMI, /*InsnID*/0, /*Opcode*/GIMT_Encode2(AMDGPU::V_MED3_F32_e64),
        GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/0, // DstI[vdst]
        GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(1), /*SubOperand*/1, // src0_mods
        GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(1), /*SubOperand*/0, // src0
        GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/1, // src1_mods
        GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/0, // src1
        GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(2), /*SubOperand*/1, // src2_mods
        GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(2), /*SubOperand*/0, // src2
        GIR_AddImm8, /*InsnID*/0, /*Imm*/0,
        GIR_AddImm8, /*InsnID*/0, /*Imm*/0,
        GIR_ConstrainSelectedInstOperands, /*InsnID*/0,
        GIR_EraseFromParent, /*InsnID*/0,
        // GIR_Coverage, 10139,
        GIR_Done,
      // Label 4703: @320586
      GIM_Try, /*On fail goto*//*Label 4704*/ GIMT_Encode4(320726), // Rule ID 6490 //
        GIM_CheckRegBankForClass, /*MI*/0, /*Op*/0, /*RC*/GIMT_Encode2(AMDGPU::VGPR_32RegClassID),
        GIM_RecordInsn, /*DefineMI*/1, /*MI*/0, /*OpIdx*/1, // MIs[1]
        GIM_CheckOpcode, /*MI*/1, GIMT_Encode2(TargetOpcode::G_FMINNUM_IEEE),
        GIM_CheckType, /*MI*/1, /*Op*/1, /*Type*/GILLT_s32,
        GIM_CheckType, /*MI*/1, /*Op*/2, /*Type*/GILLT_s32,
        GIM_RecordInsn, /*DefineMI*/2, /*MI*/0, /*OpIdx*/2, // MIs[2]
        GIM_CheckOpcode, /*MI*/2, GIMT_Encode2(TargetOpcode::G_FMINNUM_IEEE),
        GIM_CheckType, /*MI*/2, /*Op*/1, /*Type*/GILLT_s32,
        GIM_CheckType, /*MI*/2, /*Op*/2, /*Type*/GILLT_s32,
        GIM_RecordInsn, /*DefineMI*/3, /*MI*/2, /*OpIdx*/1, // MIs[3]
        GIM_CheckOpcode, /*MI*/3, GIMT_Encode2(TargetOpcode::G_FMAXNUM_IEEE),
        // MIs[3] VOP3Mods:src0:src0_mods
        GIM_CheckIsSameOperand, /*MI*/3, /*OpIdx*/1, /*OtherMI*/1, /*OtherOpIdx*/1,
        // MIs[3] VOP3Mods:src1:src1_mods
        GIM_CheckIsSameOperand, /*MI*/3, /*OpIdx*/2, /*OtherMI*/1, /*OtherOpIdx*/2,
        GIM_CheckCxxInsnPredicate, /*MI*/0, /*FnId*/GIMT_Encode2(GICXXPred_MI_Predicate_fmaxnum_like_nnan),
        GIM_CheckIsSafeToFold, /*InsnID*/1,
        GIM_CheckIsSafeToFold, /*InsnID*/2,
        GIM_CheckIsSafeToFold, /*InsnID*/3,
        GIM_CheckComplexPattern, /*MI*/1, /*Op*/1, /*Renderer*/GIMT_Encode2(0), GIMT_Encode2(GICP_gi_vop3mods),
        GIM_CheckComplexPattern, /*MI*/1, /*Op*/2, /*Renderer*/GIMT_Encode2(1), GIMT_Encode2(GICP_gi_vop3mods),
        GIM_CheckComplexPattern, /*MI*/2, /*Op*/2, /*Renderer*/GIMT_Encode2(2), GIMT_Encode2(GICP_gi_vop3mods),
        // (fmaxnum:{ *:[f32] } (fminnum_ieee:{ *:[f32] } (VOP3Mods:{ *:[f32] } f32:{ *:[f32] }:$src0, i32:{ *:[i32] }:$src0_mods), (VOP3Mods:{ *:[f32] } f32:{ *:[f32] }:$src1, i32:{ *:[i32] }:$src1_mods)), (fminnum_ieee:{ *:[f32] } (fmaxnum_ieee:{ *:[f32] } (VOP3Mods:{ *:[f32] } f32:{ *:[f32] }:$src0, i32:{ *:[i32] }:$src0_mods), (VOP3Mods:{ *:[f32] } f32:{ *:[f32] }:$src1, i32:{ *:[i32] }:$src1_mods)), (VOP3Mods:{ *:[f32] } f32:{ *:[f32] }:$src2, i32:{ *:[i32] }:$src2_mods)))<<P:Predicate_fmaxnum_like_nnan>>  =>  (V_MED3_F32_e64:{ *:[f32] } ?:{ *:[i32] }:$src0_mods, ?:{ *:[f32] }:$src0, ?:{ *:[i32] }:$src1_mods, ?:{ *:[f32] }:$src1, ?:{ *:[i32] }:$src2_mods, ?:{ *:[f32] }:$src2, 0:{ *:[i1] }, 0:{ *:[i32] })
        GIR_BuildMI, /*InsnID*/0, /*Opcode*/GIMT_Encode2(AMDGPU::V_MED3_F32_e64),
        GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/0, // DstI[vdst]
        GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/1, // src0_mods
        GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/0, // src0
        GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(1), /*SubOperand*/1, // src1_mods
        GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(1), /*SubOperand*/0, // src1
        GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(2), /*SubOperand*/1, // src2_mods
        GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(2), /*SubOperand*/0, // src2
        GIR_AddImm8, /*InsnID*/0, /*Imm*/0,
        GIR_AddImm8, /*InsnID*/0, /*Imm*/0,
        GIR_ConstrainSelectedInstOperands, /*InsnID*/0,
        GIR_EraseFromParent, /*InsnID*/0,
        // GIR_Coverage, 6490,
        GIR_Done,
      // Label 4704: @320726
      GIM_Try, /*On fail goto*//*Label 4705*/ GIMT_Encode4(320866), // Rule ID 10120 //
        GIM_CheckRegBankForClass, /*MI*/0, /*Op*/0, /*RC*/GIMT_Encode2(AMDGPU::VGPR_32RegClassID),
        GIM_RecordInsn, /*DefineMI*/1, /*MI*/0, /*OpIdx*/1, // MIs[1]
        GIM_CheckOpcode, /*MI*/1, GIMT_Encode2(TargetOpcode::G_FMINNUM_IEEE),
        GIM_CheckType, /*MI*/1, /*Op*/1, /*Type*/GILLT_s32,
        GIM_CheckType, /*MI*/1, /*Op*/2, /*Type*/GILLT_s32,
        GIM_RecordInsn, /*DefineMI*/2, /*MI*/0, /*OpIdx*/2, // MIs[2]
        GIM_CheckOpcode, /*MI*/2, GIMT_Encode2(TargetOpcode::G_FMINNUM_IEEE),
        GIM_CheckType, /*MI*/2, /*Op*/1, /*Type*/GILLT_s32,
        GIM_CheckType, /*MI*/2, /*Op*/2, /*Type*/GILLT_s32,
        GIM_RecordInsn, /*DefineMI*/3, /*MI*/2, /*OpIdx*/1, // MIs[3]
        GIM_CheckOpcode, /*MI*/3, GIMT_Encode2(TargetOpcode::G_FMAXNUM_IEEE),
        // MIs[3] VOP3Mods:src1:src1_mods
        GIM_CheckIsSameOperand, /*MI*/3, /*OpIdx*/1, /*OtherMI*/1, /*OtherOpIdx*/2,
        // MIs[3] VOP3Mods:src0:src0_mods
        GIM_CheckIsSameOperand, /*MI*/3, /*OpIdx*/2, /*OtherMI*/1, /*OtherOpIdx*/1,
        GIM_CheckCxxInsnPredicate, /*MI*/0, /*FnId*/GIMT_Encode2(GICXXPred_MI_Predicate_fmaxnum_like_nnan),
        GIM_CheckIsSafeToFold, /*InsnID*/1,
        GIM_CheckIsSafeToFold, /*InsnID*/2,
        GIM_CheckIsSafeToFold, /*InsnID*/3,
        GIM_CheckComplexPattern, /*MI*/1, /*Op*/1, /*Renderer*/GIMT_Encode2(0), GIMT_Encode2(GICP_gi_vop3mods),
        GIM_CheckComplexPattern, /*MI*/1, /*Op*/2, /*Renderer*/GIMT_Encode2(1), GIMT_Encode2(GICP_gi_vop3mods),
        GIM_CheckComplexPattern, /*MI*/2, /*Op*/2, /*Renderer*/GIMT_Encode2(2), GIMT_Encode2(GICP_gi_vop3mods),
        // (fmaxnum:{ *:[f32] } (fminnum_ieee:{ *:[f32] } (VOP3Mods:{ *:[f32] } f32:{ *:[f32] }:$src0, i32:{ *:[i32] }:$src0_mods), (VOP3Mods:{ *:[f32] } f32:{ *:[f32] }:$src1, i32:{ *:[i32] }:$src1_mods)), (fminnum_ieee:{ *:[f32] } (fmaxnum_ieee:{ *:[f32] } (VOP3Mods:{ *:[f32] } f32:{ *:[f32] }:$src1, i32:{ *:[i32] }:$src1_mods), (VOP3Mods:{ *:[f32] } f32:{ *:[f32] }:$src0, i32:{ *:[i32] }:$src0_mods)), (VOP3Mods:{ *:[f32] } f32:{ *:[f32] }:$src2, i32:{ *:[i32] }:$src2_mods)))<<P:Predicate_fmaxnum_like_nnan>>  =>  (V_MED3_F32_e64:{ *:[f32] } ?:{ *:[i32] }:$src0_mods, ?:{ *:[f32] }:$src0, ?:{ *:[i32] }:$src1_mods, ?:{ *:[f32] }:$src1, ?:{ *:[i32] }:$src2_mods, ?:{ *:[f32] }:$src2, 0:{ *:[i1] }, 0:{ *:[i32] })
        GIR_BuildMI, /*InsnID*/0, /*Opcode*/GIMT_Encode2(AMDGPU::V_MED3_F32_e64),
        GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/0, // DstI[vdst]
        GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/1, // src0_mods
        GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/0, // src0
        GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(1), /*SubOperand*/1, // src1_mods
        GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(1), /*SubOperand*/0, // src1
        GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(2), /*SubOperand*/1, // src2_mods
        GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(2), /*SubOperand*/0, // src2
        GIR_AddImm8, /*InsnID*/0, /*Imm*/0,
        GIR_AddImm8, /*InsnID*/0, /*Imm*/0,
        GIR_ConstrainSelectedInstOperands, /*InsnID*/0,
        GIR_EraseFromParent, /*InsnID*/0,
        // GIR_Coverage, 10120,
        GIR_Done,
      // Label 4705: @320866
      GIM_Try, /*On fail goto*//*Label 4706*/ GIMT_Encode4(321006), // Rule ID 10123 //
        GIM_CheckRegBankForClass, /*MI*/0, /*Op*/0, /*RC*/GIMT_Encode2(AMDGPU::VGPR_32RegClassID),
        GIM_RecordInsn, /*DefineMI*/1, /*MI*/0, /*OpIdx*/1, // MIs[1]
        GIM_CheckOpcode, /*MI*/1, GIMT_Encode2(TargetOpcode::G_FMINNUM_IEEE),
        GIM_CheckType, /*MI*/1, /*Op*/1, /*Type*/GILLT_s32,
        GIM_CheckType, /*MI*/1, /*Op*/2, /*Type*/GILLT_s32,
        GIM_RecordInsn, /*DefineMI*/2, /*MI*/0, /*OpIdx*/2, // MIs[2]
        GIM_CheckOpcode, /*MI*/2, GIMT_Encode2(TargetOpcode::G_FMINNUM_IEEE),
        GIM_CheckType, /*MI*/2, /*Op*/1, /*Type*/GILLT_s32,
        GIM_CheckType, /*MI*/2, /*Op*/2, /*Type*/GILLT_s32,
        GIM_RecordInsn, /*DefineMI*/3, /*MI*/2, /*OpIdx*/1, // MIs[3]
        GIM_CheckOpcode, /*MI*/3, GIMT_Encode2(TargetOpcode::G_FMAXNUM_IEEE),
        // MIs[3] VOP3Mods:src0:src0_mods
        GIM_CheckIsSameOperand, /*MI*/3, /*OpIdx*/1, /*OtherMI*/1, /*OtherOpIdx*/2,
        // MIs[3] VOP3Mods:src1:src1_mods
        GIM_CheckIsSameOperand, /*MI*/3, /*OpIdx*/2, /*OtherMI*/1, /*OtherOpIdx*/1,
        GIM_CheckCxxInsnPredicate, /*MI*/0, /*FnId*/GIMT_Encode2(GICXXPred_MI_Predicate_fmaxnum_like_nnan),
        GIM_CheckIsSafeToFold, /*InsnID*/1,
        GIM_CheckIsSafeToFold, /*InsnID*/2,
        GIM_CheckIsSafeToFold, /*InsnID*/3,
        GIM_CheckComplexPattern, /*MI*/1, /*Op*/1, /*Renderer*/GIMT_Encode2(0), GIMT_Encode2(GICP_gi_vop3mods),
        GIM_CheckComplexPattern, /*MI*/1, /*Op*/2, /*Renderer*/GIMT_Encode2(1), GIMT_Encode2(GICP_gi_vop3mods),
        GIM_CheckComplexPattern, /*MI*/2, /*Op*/2, /*Renderer*/GIMT_Encode2(2), GIMT_Encode2(GICP_gi_vop3mods),
        // (fmaxnum:{ *:[f32] } (fminnum_ieee:{ *:[f32] } (VOP3Mods:{ *:[f32] } f32:{ *:[f32] }:$src1, i32:{ *:[i32] }:$src1_mods), (VOP3Mods:{ *:[f32] } f32:{ *:[f32] }:$src0, i32:{ *:[i32] }:$src0_mods)), (fminnum_ieee:{ *:[f32] } (fmaxnum_ieee:{ *:[f32] } (VOP3Mods:{ *:[f32] } f32:{ *:[f32] }:$src0, i32:{ *:[i32] }:$src0_mods), (VOP3Mods:{ *:[f32] } f32:{ *:[f32] }:$src1, i32:{ *:[i32] }:$src1_mods)), (VOP3Mods:{ *:[f32] } f32:{ *:[f32] }:$src2, i32:{ *:[i32] }:$src2_mods)))<<P:Predicate_fmaxnum_like_nnan>>  =>  (V_MED3_F32_e64:{ *:[f32] } ?:{ *:[i32] }:$src0_mods, ?:{ *:[f32] }:$src0, ?:{ *:[i32] }:$src1_mods, ?:{ *:[f32] }:$src1, ?:{ *:[i32] }:$src2_mods, ?:{ *:[f32] }:$src2, 0:{ *:[i1] }, 0:{ *:[i32] })
        GIR_BuildMI, /*InsnID*/0, /*Opcode*/GIMT_Encode2(AMDGPU::V_MED3_F32_e64),
        GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/0, // DstI[vdst]
        GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(1), /*SubOperand*/1, // src0_mods
        GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(1), /*SubOperand*/0, // src0
        GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/1, // src1_mods
        GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/0, // src1
        GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(2), /*SubOperand*/1, // src2_mods
        GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(2), /*SubOperand*/0, // src2
        GIR_AddImm8, /*InsnID*/0, /*Imm*/0,
        GIR_AddImm8, /*InsnID*/0, /*Imm*/0,
        GIR_ConstrainSelectedInstOperands, /*InsnID*/0,
        GIR_EraseFromParent, /*InsnID*/0,
        // GIR_Coverage, 10123,
        GIR_Done,
      // Label 4706: @321006
      GIM_Try, /*On fail goto*//*Label 4707*/ GIMT_Encode4(321146), // Rule ID 10124 //
        GIM_CheckRegBankForClass, /*MI*/0, /*Op*/0, /*RC*/GIMT_Encode2(AMDGPU::VGPR_32RegClassID),
        GIM_RecordInsn, /*DefineMI*/1, /*MI*/0, /*OpIdx*/1, // MIs[1]
        GIM_CheckOpcode, /*MI*/1, GIMT_Encode2(TargetOpcode::G_FMINNUM_IEEE),
        GIM_CheckType, /*MI*/1, /*Op*/1, /*Type*/GILLT_s32,
        GIM_CheckType, /*MI*/1, /*Op*/2, /*Type*/GILLT_s32,
        GIM_RecordInsn, /*DefineMI*/2, /*MI*/0, /*OpIdx*/2, // MIs[2]
        GIM_CheckOpcode, /*MI*/2, GIMT_Encode2(TargetOpcode::G_FMINNUM_IEEE),
        GIM_CheckType, /*MI*/2, /*Op*/1, /*Type*/GILLT_s32,
        GIM_CheckType, /*MI*/2, /*Op*/2, /*Type*/GILLT_s32,
        GIM_RecordInsn, /*DefineMI*/3, /*MI*/2, /*OpIdx*/1, // MIs[3]
        GIM_CheckOpcode, /*MI*/3, GIMT_Encode2(TargetOpcode::G_FMAXNUM_IEEE),
        // MIs[3] VOP3Mods:src1:src1_mods
        GIM_CheckIsSameOperand, /*MI*/3, /*OpIdx*/1, /*OtherMI*/1, /*OtherOpIdx*/1,
        // MIs[3] VOP3Mods:src0:src0_mods
        GIM_CheckIsSameOperand, /*MI*/3, /*OpIdx*/2, /*OtherMI*/1, /*OtherOpIdx*/2,
        GIM_CheckCxxInsnPredicate, /*MI*/0, /*FnId*/GIMT_Encode2(GICXXPred_MI_Predicate_fmaxnum_like_nnan),
        GIM_CheckIsSafeToFold, /*InsnID*/1,
        GIM_CheckIsSafeToFold, /*InsnID*/2,
        GIM_CheckIsSafeToFold, /*InsnID*/3,
        GIM_CheckComplexPattern, /*MI*/1, /*Op*/1, /*Renderer*/GIMT_Encode2(0), GIMT_Encode2(GICP_gi_vop3mods),
        GIM_CheckComplexPattern, /*MI*/1, /*Op*/2, /*Renderer*/GIMT_Encode2(1), GIMT_Encode2(GICP_gi_vop3mods),
        GIM_CheckComplexPattern, /*MI*/2, /*Op*/2, /*Renderer*/GIMT_Encode2(2), GIMT_Encode2(GICP_gi_vop3mods),
        // (fmaxnum:{ *:[f32] } (fminnum_ieee:{ *:[f32] } (VOP3Mods:{ *:[f32] } f32:{ *:[f32] }:$src1, i32:{ *:[i32] }:$src1_mods), (VOP3Mods:{ *:[f32] } f32:{ *:[f32] }:$src0, i32:{ *:[i32] }:$src0_mods)), (fminnum_ieee:{ *:[f32] } (fmaxnum_ieee:{ *:[f32] } (VOP3Mods:{ *:[f32] } f32:{ *:[f32] }:$src1, i32:{ *:[i32] }:$src1_mods), (VOP3Mods:{ *:[f32] } f32:{ *:[f32] }:$src0, i32:{ *:[i32] }:$src0_mods)), (VOP3Mods:{ *:[f32] } f32:{ *:[f32] }:$src2, i32:{ *:[i32] }:$src2_mods)))<<P:Predicate_fmaxnum_like_nnan>>  =>  (V_MED3_F32_e64:{ *:[f32] } ?:{ *:[i32] }:$src0_mods, ?:{ *:[f32] }:$src0, ?:{ *:[i32] }:$src1_mods, ?:{ *:[f32] }:$src1, ?:{ *:[i32] }:$src2_mods, ?:{ *:[f32] }:$src2, 0:{ *:[i1] }, 0:{ *:[i32] })
        GIR_BuildMI, /*InsnID*/0, /*Opcode*/GIMT_Encode2(AMDGPU::V_MED3_F32_e64),
        GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/0, // DstI[vdst]
        GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(1), /*SubOperand*/1, // src0_mods
        GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(1), /*SubOperand*/0, // src0
        GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/1, // src1_mods
        GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/0, // src1
        GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(2), /*SubOperand*/1, // src2_mods
        GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(2), /*SubOperand*/0, // src2
        GIR_AddImm8, /*InsnID*/0, /*Imm*/0,
        GIR_AddImm8, /*InsnID*/0, /*Imm*/0,
        GIR_ConstrainSelectedInstOperands, /*InsnID*/0,
        GIR_EraseFromParent, /*InsnID*/0,
        // GIR_Coverage, 10124,
        GIR_Done,
      // Label 4707: @321146
      GIM_Try, /*On fail goto*//*Label 4708*/ GIMT_Encode4(321286), // Rule ID 10206 //
        GIM_CheckRegBankForClass, /*MI*/0, /*Op*/0, /*RC*/GIMT_Encode2(AMDGPU::VGPR_32RegClassID),
        GIM_RecordInsn, /*DefineMI*/1, /*MI*/0, /*OpIdx*/1, // MIs[1]
        GIM_CheckOpcode, /*MI*/1, GIMT_Encode2(TargetOpcode::G_FMINNUM_IEEE),
        GIM_CheckType, /*MI*/1, /*Op*/1, /*Type*/GILLT_s32,
        GIM_CheckType, /*MI*/1, /*Op*/2, /*Type*/GILLT_s32,
        GIM_RecordInsn, /*DefineMI*/2, /*MI*/1, /*OpIdx*/2, // MIs[2]
        GIM_CheckOpcode, /*MI*/2, GIMT_Encode2(TargetOpcode::G_FMAXNUM),
        GIM_CheckType, /*MI*/2, /*Op*/1, /*Type*/GILLT_s32,
        GIM_CheckType, /*MI*/2, /*Op*/2, /*Type*/GILLT_s32,
        GIM_RecordInsn, /*DefineMI*/3, /*MI*/0, /*OpIdx*/2, // MIs[3]
        GIM_CheckOpcode, /*MI*/3, GIMT_Encode2(TargetOpcode::G_FMINNUM),
        // MIs[3] VOP3Mods:src0:src0_mods
        GIM_CheckIsSameOperand, /*MI*/3, /*OpIdx*/1, /*OtherMI*/2, /*OtherOpIdx*/1,
        // MIs[3] VOP3Mods:src1:src1_mods
        GIM_CheckIsSameOperand, /*MI*/3, /*OpIdx*/2, /*OtherMI*/2, /*OtherOpIdx*/2,
        GIM_CheckCxxInsnPredicate, /*MI*/0, /*FnId*/GIMT_Encode2(GICXXPred_MI_Predicate_fmaxnum_like_nnan),
        GIM_CheckIsSafeToFold, /*InsnID*/1,
        GIM_CheckIsSafeToFold, /*InsnID*/2,
        GIM_CheckIsSafeToFold, /*InsnID*/3,
        GIM_CheckComplexPattern, /*MI*/1, /*Op*/1, /*Renderer*/GIMT_Encode2(0), GIMT_Encode2(GICP_gi_vop3mods),
        GIM_CheckComplexPattern, /*MI*/2, /*Op*/1, /*Renderer*/GIMT_Encode2(1), GIMT_Encode2(GICP_gi_vop3mods),
        GIM_CheckComplexPattern, /*MI*/2, /*Op*/2, /*Renderer*/GIMT_Encode2(2), GIMT_Encode2(GICP_gi_vop3mods),
        // (fmaxnum:{ *:[f32] } (fminnum_ieee:{ *:[f32] } (VOP3Mods:{ *:[f32] } f32:{ *:[f32] }:$src2, i32:{ *:[i32] }:$src2_mods), (fmaxnum:{ *:[f32] } (VOP3Mods:{ *:[f32] } f32:{ *:[f32] }:$src0, i32:{ *:[i32] }:$src0_mods), (VOP3Mods:{ *:[f32] } f32:{ *:[f32] }:$src1, i32:{ *:[i32] }:$src1_mods))), (fminnum:{ *:[f32] } (VOP3Mods:{ *:[f32] } f32:{ *:[f32] }:$src0, i32:{ *:[i32] }:$src0_mods), (VOP3Mods:{ *:[f32] } f32:{ *:[f32] }:$src1, i32:{ *:[i32] }:$src1_mods)))<<P:Predicate_fmaxnum_like_nnan>>  =>  (V_MED3_F32_e64:{ *:[f32] } ?:{ *:[i32] }:$src0_mods, ?:{ *:[f32] }:$src0, ?:{ *:[i32] }:$src1_mods, ?:{ *:[f32] }:$src1, ?:{ *:[i32] }:$src2_mods, ?:{ *:[f32] }:$src2, 0:{ *:[i1] }, 0:{ *:[i32] })
        GIR_BuildMI, /*InsnID*/0, /*Opcode*/GIMT_Encode2(AMDGPU::V_MED3_F32_e64),
        GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/0, // DstI[vdst]
        GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(1), /*SubOperand*/1, // src0_mods
        GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(1), /*SubOperand*/0, // src0
        GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(2), /*SubOperand*/1, // src1_mods
        GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(2), /*SubOperand*/0, // src1
        GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/1, // src2_mods
        GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/0, // src2
        GIR_AddImm8, /*InsnID*/0, /*Imm*/0,
        GIR_AddImm8, /*InsnID*/0, /*Imm*/0,
        GIR_ConstrainSelectedInstOperands, /*InsnID*/0,
        GIR_EraseFromParent, /*InsnID*/0,
        // GIR_Coverage, 10206,
        GIR_Done,
      // Label 4708: @321286
      GIM_Try, /*On fail goto*//*Label 4709*/ GIMT_Encode4(321426), // Rule ID 10207 //
        GIM_CheckRegBankForClass, /*MI*/0, /*Op*/0, /*RC*/GIMT_Encode2(AMDGPU::VGPR_32RegClassID),
        GIM_RecordInsn, /*DefineMI*/1, /*MI*/0, /*OpIdx*/1, // MIs[1]
        GIM_CheckOpcode, /*MI*/1, GIMT_Encode2(TargetOpcode::G_FMINNUM_IEEE),
        GIM_CheckType, /*MI*/1, /*Op*/1, /*Type*/GILLT_s32,
        GIM_CheckType, /*MI*/1, /*Op*/2, /*Type*/GILLT_s32,
        GIM_RecordInsn, /*DefineMI*/2, /*MI*/1, /*OpIdx*/2, // MIs[2]
        GIM_CheckOpcode, /*MI*/2, GIMT_Encode2(TargetOpcode::G_FMAXNUM),
        GIM_CheckType, /*MI*/2, /*Op*/1, /*Type*/GILLT_s32,
        GIM_CheckType, /*MI*/2, /*Op*/2, /*Type*/GILLT_s32,
        GIM_RecordInsn, /*DefineMI*/3, /*MI*/0, /*OpIdx*/2, // MIs[3]
        GIM_CheckOpcode, /*MI*/3, GIMT_Encode2(TargetOpcode::G_FMINNUM),
        // MIs[3] VOP3Mods:src1:src1_mods
        GIM_CheckIsSameOperand, /*MI*/3, /*OpIdx*/1, /*OtherMI*/2, /*OtherOpIdx*/2,
        // MIs[3] VOP3Mods:src0:src0_mods
        GIM_CheckIsSameOperand, /*MI*/3, /*OpIdx*/2, /*OtherMI*/2, /*OtherOpIdx*/1,
        GIM_CheckCxxInsnPredicate, /*MI*/0, /*FnId*/GIMT_Encode2(GICXXPred_MI_Predicate_fmaxnum_like_nnan),
        GIM_CheckIsSafeToFold, /*InsnID*/1,
        GIM_CheckIsSafeToFold, /*InsnID*/2,
        GIM_CheckIsSafeToFold, /*InsnID*/3,
        GIM_CheckComplexPattern, /*MI*/1, /*Op*/1, /*Renderer*/GIMT_Encode2(0), GIMT_Encode2(GICP_gi_vop3mods),
        GIM_CheckComplexPattern, /*MI*/2, /*Op*/1, /*Renderer*/GIMT_Encode2(1), GIMT_Encode2(GICP_gi_vop3mods),
        GIM_CheckComplexPattern, /*MI*/2, /*Op*/2, /*Renderer*/GIMT_Encode2(2), GIMT_Encode2(GICP_gi_vop3mods),
        // (fmaxnum:{ *:[f32] } (fminnum_ieee:{ *:[f32] } (VOP3Mods:{ *:[f32] } f32:{ *:[f32] }:$src2, i32:{ *:[i32] }:$src2_mods), (fmaxnum:{ *:[f32] } (VOP3Mods:{ *:[f32] } f32:{ *:[f32] }:$src0, i32:{ *:[i32] }:$src0_mods), (VOP3Mods:{ *:[f32] } f32:{ *:[f32] }:$src1, i32:{ *:[i32] }:$src1_mods))), (fminnum:{ *:[f32] } (VOP3Mods:{ *:[f32] } f32:{ *:[f32] }:$src1, i32:{ *:[i32] }:$src1_mods), (VOP3Mods:{ *:[f32] } f32:{ *:[f32] }:$src0, i32:{ *:[i32] }:$src0_mods)))<<P:Predicate_fmaxnum_like_nnan>>  =>  (V_MED3_F32_e64:{ *:[f32] } ?:{ *:[i32] }:$src0_mods, ?:{ *:[f32] }:$src0, ?:{ *:[i32] }:$src1_mods, ?:{ *:[f32] }:$src1, ?:{ *:[i32] }:$src2_mods, ?:{ *:[f32] }:$src2, 0:{ *:[i1] }, 0:{ *:[i32] })
        GIR_BuildMI, /*InsnID*/0, /*Opcode*/GIMT_Encode2(AMDGPU::V_MED3_F32_e64),
        GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/0, // DstI[vdst]
        GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(1), /*SubOperand*/1, // src0_mods
        GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(1), /*SubOperand*/0, // src0
        GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(2), /*SubOperand*/1, // src1_mods
        GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(2), /*SubOperand*/0, // src1
        GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/1, // src2_mods
        GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/0, // src2
        GIR_AddImm8, /*InsnID*/0, /*Imm*/0,
        GIR_AddImm8, /*InsnID*/0, /*Imm*/0,
        GIR_ConstrainSelectedInstOperands, /*InsnID*/0,
        GIR_EraseFromParent, /*InsnID*/0,
        // GIR_Coverage, 10207,
        GIR_Done,
      // Label 4709: @321426
      GIM_Try, /*On fail goto*//*Label 4710*/ GIMT_Encode4(321566), // Rule ID 10208 //
        GIM_CheckRegBankForClass, /*MI*/0, /*Op*/0, /*RC*/GIMT_Encode2(AMDGPU::VGPR_32RegClassID),
        GIM_RecordInsn, /*DefineMI*/1, /*MI*/0, /*OpIdx*/1, // MIs[1]
        GIM_CheckOpcode, /*MI*/1, GIMT_Encode2(TargetOpcode::G_FMINNUM_IEEE),
        GIM_CheckType, /*MI*/1, /*Op*/1, /*Type*/GILLT_s32,
        GIM_CheckType, /*MI*/1, /*Op*/2, /*Type*/GILLT_s32,
        GIM_RecordInsn, /*DefineMI*/2, /*MI*/1, /*OpIdx*/2, // MIs[2]
        GIM_CheckOpcode, /*MI*/2, GIMT_Encode2(TargetOpcode::G_FMAXNUM),
        GIM_CheckType, /*MI*/2, /*Op*/1, /*Type*/GILLT_s32,
        GIM_CheckType, /*MI*/2, /*Op*/2, /*Type*/GILLT_s32,
        GIM_RecordInsn, /*DefineMI*/3, /*MI*/0, /*OpIdx*/2, // MIs[3]
        GIM_CheckOpcode, /*MI*/3, GIMT_Encode2(TargetOpcode::G_FMINNUM),
        // MIs[3] VOP3Mods:src0:src0_mods
        GIM_CheckIsSameOperand, /*MI*/3, /*OpIdx*/1, /*OtherMI*/2, /*OtherOpIdx*/2,
        // MIs[3] VOP3Mods:src1:src1_mods
        GIM_CheckIsSameOperand, /*MI*/3, /*OpIdx*/2, /*OtherMI*/2, /*OtherOpIdx*/1,
        GIM_CheckCxxInsnPredicate, /*MI*/0, /*FnId*/GIMT_Encode2(GICXXPred_MI_Predicate_fmaxnum_like_nnan),
        GIM_CheckIsSafeToFold, /*InsnID*/1,
        GIM_CheckIsSafeToFold, /*InsnID*/2,
        GIM_CheckIsSafeToFold, /*InsnID*/3,
        GIM_CheckComplexPattern, /*MI*/1, /*Op*/1, /*Renderer*/GIMT_Encode2(0), GIMT_Encode2(GICP_gi_vop3mods),
        GIM_CheckComplexPattern, /*MI*/2, /*Op*/1, /*Renderer*/GIMT_Encode2(1), GIMT_Encode2(GICP_gi_vop3mods),
        GIM_CheckComplexPattern, /*MI*/2, /*Op*/2, /*Renderer*/GIMT_Encode2(2), GIMT_Encode2(GICP_gi_vop3mods),
        // (fmaxnum:{ *:[f32] } (fminnum_ieee:{ *:[f32] } (VOP3Mods:{ *:[f32] } f32:{ *:[f32] }:$src2, i32:{ *:[i32] }:$src2_mods), (fmaxnum:{ *:[f32] } (VOP3Mods:{ *:[f32] } f32:{ *:[f32] }:$src1, i32:{ *:[i32] }:$src1_mods), (VOP3Mods:{ *:[f32] } f32:{ *:[f32] }:$src0, i32:{ *:[i32] }:$src0_mods))), (fminnum:{ *:[f32] } (VOP3Mods:{ *:[f32] } f32:{ *:[f32] }:$src0, i32:{ *:[i32] }:$src0_mods), (VOP3Mods:{ *:[f32] } f32:{ *:[f32] }:$src1, i32:{ *:[i32] }:$src1_mods)))<<P:Predicate_fmaxnum_like_nnan>>  =>  (V_MED3_F32_e64:{ *:[f32] } ?:{ *:[i32] }:$src0_mods, ?:{ *:[f32] }:$src0, ?:{ *:[i32] }:$src1_mods, ?:{ *:[f32] }:$src1, ?:{ *:[i32] }:$src2_mods, ?:{ *:[f32] }:$src2, 0:{ *:[i1] }, 0:{ *:[i32] })
        GIR_BuildMI, /*InsnID*/0, /*Opcode*/GIMT_Encode2(AMDGPU::V_MED3_F32_e64),
        GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/0, // DstI[vdst]
        GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(2), /*SubOperand*/1, // src0_mods
        GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(2), /*SubOperand*/0, // src0
        GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(1), /*SubOperand*/1, // src1_mods
        GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(1), /*SubOperand*/0, // src1
        GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/1, // src2_mods
        GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/0, // src2
        GIR_AddImm8, /*InsnID*/0, /*Imm*/0,
        GIR_AddImm8, /*InsnID*/0, /*Imm*/0,
        GIR_ConstrainSelectedInstOperands, /*InsnID*/0,
        GIR_EraseFromParent, /*InsnID*/0,
        // GIR_Coverage, 10208,
        GIR_Done,
      // Label 4710: @321566
      GIM_Try, /*On fail goto*//*Label 4711*/ GIMT_Encode4(321706), // Rule ID 10209 //
        GIM_CheckRegBankForClass, /*MI*/0, /*Op*/0, /*RC*/GIMT_Encode2(AMDGPU::VGPR_32RegClassID),
        GIM_RecordInsn, /*DefineMI*/1, /*MI*/0, /*OpIdx*/1, // MIs[1]
        GIM_CheckOpcode, /*MI*/1, GIMT_Encode2(TargetOpcode::G_FMINNUM_IEEE),
        GIM_CheckType, /*MI*/1, /*Op*/1, /*Type*/GILLT_s32,
        GIM_CheckType, /*MI*/1, /*Op*/2, /*Type*/GILLT_s32,
        GIM_RecordInsn, /*DefineMI*/2, /*MI*/1, /*OpIdx*/2, // MIs[2]
        GIM_CheckOpcode, /*MI*/2, GIMT_Encode2(TargetOpcode::G_FMAXNUM),
        GIM_CheckType, /*MI*/2, /*Op*/1, /*Type*/GILLT_s32,
        GIM_CheckType, /*MI*/2, /*Op*/2, /*Type*/GILLT_s32,
        GIM_RecordInsn, /*DefineMI*/3, /*MI*/0, /*OpIdx*/2, // MIs[3]
        GIM_CheckOpcode, /*MI*/3, GIMT_Encode2(TargetOpcode::G_FMINNUM),
        // MIs[3] VOP3Mods:src1:src1_mods
        GIM_CheckIsSameOperand, /*MI*/3, /*OpIdx*/1, /*OtherMI*/2, /*OtherOpIdx*/1,
        // MIs[3] VOP3Mods:src0:src0_mods
        GIM_CheckIsSameOperand, /*MI*/3, /*OpIdx*/2, /*OtherMI*/2, /*OtherOpIdx*/2,
        GIM_CheckCxxInsnPredicate, /*MI*/0, /*FnId*/GIMT_Encode2(GICXXPred_MI_Predicate_fmaxnum_like_nnan),
        GIM_CheckIsSafeToFold, /*InsnID*/1,
        GIM_CheckIsSafeToFold, /*InsnID*/2,
        GIM_CheckIsSafeToFold, /*InsnID*/3,
        GIM_CheckComplexPattern, /*MI*/1, /*Op*/1, /*Renderer*/GIMT_Encode2(0), GIMT_Encode2(GICP_gi_vop3mods),
        GIM_CheckComplexPattern, /*MI*/2, /*Op*/1, /*Renderer*/GIMT_Encode2(1), GIMT_Encode2(GICP_gi_vop3mods),
        GIM_CheckComplexPattern, /*MI*/2, /*Op*/2, /*Renderer*/GIMT_Encode2(2), GIMT_Encode2(GICP_gi_vop3mods),
        // (fmaxnum:{ *:[f32] } (fminnum_ieee:{ *:[f32] } (VOP3Mods:{ *:[f32] } f32:{ *:[f32] }:$src2, i32:{ *:[i32] }:$src2_mods), (fmaxnum:{ *:[f32] } (VOP3Mods:{ *:[f32] } f32:{ *:[f32] }:$src1, i32:{ *:[i32] }:$src1_mods), (VOP3Mods:{ *:[f32] } f32:{ *:[f32] }:$src0, i32:{ *:[i32] }:$src0_mods))), (fminnum:{ *:[f32] } (VOP3Mods:{ *:[f32] } f32:{ *:[f32] }:$src1, i32:{ *:[i32] }:$src1_mods), (VOP3Mods:{ *:[f32] } f32:{ *:[f32] }:$src0, i32:{ *:[i32] }:$src0_mods)))<<P:Predicate_fmaxnum_like_nnan>>  =>  (V_MED3_F32_e64:{ *:[f32] } ?:{ *:[i32] }:$src0_mods, ?:{ *:[f32] }:$src0, ?:{ *:[i32] }:$src1_mods, ?:{ *:[f32] }:$src1, ?:{ *:[i32] }:$src2_mods, ?:{ *:[f32] }:$src2, 0:{ *:[i1] }, 0:{ *:[i32] })
        GIR_BuildMI, /*InsnID*/0, /*Opcode*/GIMT_Encode2(AMDGPU::V_MED3_F32_e64),
        GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/0, // DstI[vdst]
        GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(2), /*SubOperand*/1, // src0_mods
        GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(2), /*SubOperand*/0, // src0
        GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(1), /*SubOperand*/1, // src1_mods
        GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(1), /*SubOperand*/0, // src1
        GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/1, // src2_mods
        GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/0, // src2
        GIR_AddImm8, /*InsnID*/0, /*Imm*/0,
        GIR_AddImm8, /*InsnID*/0, /*Imm*/0,
        GIR_ConstrainSelectedInstOperands, /*InsnID*/0,
        GIR_EraseFromParent, /*InsnID*/0,
        // GIR_Coverage, 10209,
        GIR_Done,
      // Label 4711: @321706
      GIM_Try, /*On fail goto*//*Label 4712*/ GIMT_Encode4(321846), // Rule ID 10146 //
        GIM_CheckRegBankForClass, /*MI*/0, /*Op*/0, /*RC*/GIMT_Encode2(AMDGPU::VGPR_32RegClassID),
        GIM_RecordInsn, /*DefineMI*/1, /*MI*/0, /*OpIdx*/1, // MIs[1]
        GIM_CheckOpcode, /*MI*/1, GIMT_Encode2(TargetOpcode::G_FMINNUM_IEEE),
        GIM_CheckType, /*MI*/1, /*Op*/1, /*Type*/GILLT_s32,
        GIM_CheckType, /*MI*/1, /*Op*/2, /*Type*/GILLT_s32,
        GIM_RecordInsn, /*DefineMI*/2, /*MI*/1, /*OpIdx*/2, // MIs[2]
        GIM_CheckOpcode, /*MI*/2, GIMT_Encode2(TargetOpcode::G_FMAXNUM),
        GIM_CheckType, /*MI*/2, /*Op*/1, /*Type*/GILLT_s32,
        GIM_CheckType, /*MI*/2, /*Op*/2, /*Type*/GILLT_s32,
        GIM_RecordInsn, /*DefineMI*/3, /*MI*/0, /*OpIdx*/2, // MIs[3]
        GIM_CheckOpcode, /*MI*/3, GIMT_Encode2(TargetOpcode::G_FMINNUM_IEEE),
        // MIs[3] VOP3Mods:src0:src0_mods
        GIM_CheckIsSameOperand, /*MI*/3, /*OpIdx*/1, /*OtherMI*/2, /*OtherOpIdx*/1,
        // MIs[3] VOP3Mods:src1:src1_mods
        GIM_CheckIsSameOperand, /*MI*/3, /*OpIdx*/2, /*OtherMI*/2, /*OtherOpIdx*/2,
        GIM_CheckCxxInsnPredicate, /*MI*/0, /*FnId*/GIMT_Encode2(GICXXPred_MI_Predicate_fmaxnum_like_nnan),
        GIM_CheckIsSafeToFold, /*InsnID*/1,
        GIM_CheckIsSafeToFold, /*InsnID*/2,
        GIM_CheckIsSafeToFold, /*InsnID*/3,
        GIM_CheckComplexPattern, /*MI*/1, /*Op*/1, /*Renderer*/GIMT_Encode2(0), GIMT_Encode2(GICP_gi_vop3mods),
        GIM_CheckComplexPattern, /*MI*/2, /*Op*/1, /*Renderer*/GIMT_Encode2(1), GIMT_Encode2(GICP_gi_vop3mods),
        GIM_CheckComplexPattern, /*MI*/2, /*Op*/2, /*Renderer*/GIMT_Encode2(2), GIMT_Encode2(GICP_gi_vop3mods),
        // (fmaxnum:{ *:[f32] } (fminnum_ieee:{ *:[f32] } (VOP3Mods:{ *:[f32] } f32:{ *:[f32] }:$src2, i32:{ *:[i32] }:$src2_mods), (fmaxnum:{ *:[f32] } (VOP3Mods:{ *:[f32] } f32:{ *:[f32] }:$src0, i32:{ *:[i32] }:$src0_mods), (VOP3Mods:{ *:[f32] } f32:{ *:[f32] }:$src1, i32:{ *:[i32] }:$src1_mods))), (fminnum_ieee:{ *:[f32] } (VOP3Mods:{ *:[f32] } f32:{ *:[f32] }:$src0, i32:{ *:[i32] }:$src0_mods), (VOP3Mods:{ *:[f32] } f32:{ *:[f32] }:$src1, i32:{ *:[i32] }:$src1_mods)))<<P:Predicate_fmaxnum_like_nnan>>  =>  (V_MED3_F32_e64:{ *:[f32] } ?:{ *:[i32] }:$src0_mods, ?:{ *:[f32] }:$src0, ?:{ *:[i32] }:$src1_mods, ?:{ *:[f32] }:$src1, ?:{ *:[i32] }:$src2_mods, ?:{ *:[f32] }:$src2, 0:{ *:[i1] }, 0:{ *:[i32] })
        GIR_BuildMI, /*InsnID*/0, /*Opcode*/GIMT_Encode2(AMDGPU::V_MED3_F32_e64),
        GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/0, // DstI[vdst]
        GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(1), /*SubOperand*/1, // src0_mods
        GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(1), /*SubOperand*/0, // src0
        GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(2), /*SubOperand*/1, // src1_mods
        GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(2), /*SubOperand*/0, // src1
        GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/1, // src2_mods
        GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/0, // src2
        GIR_AddImm8, /*InsnID*/0, /*Imm*/0,
        GIR_AddImm8, /*InsnID*/0, /*Imm*/0,
        GIR_ConstrainSelectedInstOperands, /*InsnID*/0,
        GIR_EraseFromParent, /*InsnID*/0,
        // GIR_Coverage, 10146,
        GIR_Done,
      // Label 4712: @321846
      GIM_Try, /*On fail goto*//*Label 4713*/ GIMT_Encode4(321986), // Rule ID 10147 //
        GIM_CheckRegBankForClass, /*MI*/0, /*Op*/0, /*RC*/GIMT_Encode2(AMDGPU::VGPR_32RegClassID),
        GIM_RecordInsn, /*DefineMI*/1, /*MI*/0, /*OpIdx*/1, // MIs[1]
        GIM_CheckOpcode, /*MI*/1, GIMT_Encode2(TargetOpcode::G_FMINNUM_IEEE),
        GIM_CheckType, /*MI*/1, /*Op*/1, /*Type*/GILLT_s32,
        GIM_CheckType, /*MI*/1, /*Op*/2, /*Type*/GILLT_s32,
        GIM_RecordInsn, /*DefineMI*/2, /*MI*/1, /*OpIdx*/2, // MIs[2]
        GIM_CheckOpcode, /*MI*/2, GIMT_Encode2(TargetOpcode::G_FMAXNUM),
        GIM_CheckType, /*MI*/2, /*Op*/1, /*Type*/GILLT_s32,
        GIM_CheckType, /*MI*/2, /*Op*/2, /*Type*/GILLT_s32,
        GIM_RecordInsn, /*DefineMI*/3, /*MI*/0, /*OpIdx*/2, // MIs[3]
        GIM_CheckOpcode, /*MI*/3, GIMT_Encode2(TargetOpcode::G_FMINNUM_IEEE),
        // MIs[3] VOP3Mods:src1:src1_mods
        GIM_CheckIsSameOperand, /*MI*/3, /*OpIdx*/1, /*OtherMI*/2, /*OtherOpIdx*/2,
        // MIs[3] VOP3Mods:src0:src0_mods
        GIM_CheckIsSameOperand, /*MI*/3, /*OpIdx*/2, /*OtherMI*/2, /*OtherOpIdx*/1,
        GIM_CheckCxxInsnPredicate, /*MI*/0, /*FnId*/GIMT_Encode2(GICXXPred_MI_Predicate_fmaxnum_like_nnan),
        GIM_CheckIsSafeToFold, /*InsnID*/1,
        GIM_CheckIsSafeToFold, /*InsnID*/2,
        GIM_CheckIsSafeToFold, /*InsnID*/3,
        GIM_CheckComplexPattern, /*MI*/1, /*Op*/1, /*Renderer*/GIMT_Encode2(0), GIMT_Encode2(GICP_gi_vop3mods),
        GIM_CheckComplexPattern, /*MI*/2, /*Op*/1, /*Renderer*/GIMT_Encode2(1), GIMT_Encode2(GICP_gi_vop3mods),
        GIM_CheckComplexPattern, /*MI*/2, /*Op*/2, /*Renderer*/GIMT_Encode2(2), GIMT_Encode2(GICP_gi_vop3mods),
        // (fmaxnum:{ *:[f32] } (fminnum_ieee:{ *:[f32] } (VOP3Mods:{ *:[f32] } f32:{ *:[f32] }:$src2, i32:{ *:[i32] }:$src2_mods), (fmaxnum:{ *:[f32] } (VOP3Mods:{ *:[f32] } f32:{ *:[f32] }:$src0, i32:{ *:[i32] }:$src0_mods), (VOP3Mods:{ *:[f32] } f32:{ *:[f32] }:$src1, i32:{ *:[i32] }:$src1_mods))), (fminnum_ieee:{ *:[f32] } (VOP3Mods:{ *:[f32] } f32:{ *:[f32] }:$src1, i32:{ *:[i32] }:$src1_mods), (VOP3Mods:{ *:[f32] } f32:{ *:[f32] }:$src0, i32:{ *:[i32] }:$src0_mods)))<<P:Predicate_fmaxnum_like_nnan>>  =>  (V_MED3_F32_e64:{ *:[f32] } ?:{ *:[i32] }:$src0_mods, ?:{ *:[f32] }:$src0, ?:{ *:[i32] }:$src1_mods, ?:{ *:[f32] }:$src1, ?:{ *:[i32] }:$src2_mods, ?:{ *:[f32] }:$src2, 0:{ *:[i1] }, 0:{ *:[i32] })
        GIR_BuildMI, /*InsnID*/0, /*Opcode*/GIMT_Encode2(AMDGPU::V_MED3_F32_e64),
        GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/0, // DstI[vdst]
        GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(1), /*SubOperand*/1, // src0_mods
        GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(1), /*SubOperand*/0, // src0
        GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(2), /*SubOperand*/1, // src1_mods
        GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(2), /*SubOperand*/0, // src1
        GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/1, // src2_mods
        GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/0, // src2
        GIR_AddImm8, /*InsnID*/0, /*Imm*/0,
        GIR_AddImm8, /*InsnID*/0, /*Imm*/0,
        GIR_ConstrainSelectedInstOperands, /*InsnID*/0,
        GIR_EraseFromParent, /*InsnID*/0,
        // GIR_Coverage, 10147,
        GIR_Done,
      // Label 4713: @321986
      GIM_Try, /*On fail goto*//*Label 4714*/ GIMT_Encode4(322126), // Rule ID 10148 //
        GIM_CheckRegBankForClass, /*MI*/0, /*Op*/0, /*RC*/GIMT_Encode2(AMDGPU::VGPR_32RegClassID),
        GIM_RecordInsn, /*DefineMI*/1, /*MI*/0, /*OpIdx*/1, // MIs[1]
        GIM_CheckOpcode, /*MI*/1, GIMT_Encode2(TargetOpcode::G_FMINNUM_IEEE),
        GIM_CheckType, /*MI*/1, /*Op*/1, /*Type*/GILLT_s32,
        GIM_CheckType, /*MI*/1, /*Op*/2, /*Type*/GILLT_s32,
        GIM_RecordInsn, /*DefineMI*/2, /*MI*/1, /*OpIdx*/2, // MIs[2]
        GIM_CheckOpcode, /*MI*/2, GIMT_Encode2(TargetOpcode::G_FMAXNUM),
        GIM_CheckType, /*MI*/2, /*Op*/1, /*Type*/GILLT_s32,
        GIM_CheckType, /*MI*/2, /*Op*/2, /*Type*/GILLT_s32,
        GIM_RecordInsn, /*DefineMI*/3, /*MI*/0, /*OpIdx*/2, // MIs[3]
        GIM_CheckOpcode, /*MI*/3, GIMT_Encode2(TargetOpcode::G_FMINNUM_IEEE),
        // MIs[3] VOP3Mods:src0:src0_mods
        GIM_CheckIsSameOperand, /*MI*/3, /*OpIdx*/1, /*OtherMI*/2, /*OtherOpIdx*/2,
        // MIs[3] VOP3Mods:src1:src1_mods
        GIM_CheckIsSameOperand, /*MI*/3, /*OpIdx*/2, /*OtherMI*/2, /*OtherOpIdx*/1,
        GIM_CheckCxxInsnPredicate, /*MI*/0, /*FnId*/GIMT_Encode2(GICXXPred_MI_Predicate_fmaxnum_like_nnan),
        GIM_CheckIsSafeToFold, /*InsnID*/1,
        GIM_CheckIsSafeToFold, /*InsnID*/2,
        GIM_CheckIsSafeToFold, /*InsnID*/3,
        GIM_CheckComplexPattern, /*MI*/1, /*Op*/1, /*Renderer*/GIMT_Encode2(0), GIMT_Encode2(GICP_gi_vop3mods),
        GIM_CheckComplexPattern, /*MI*/2, /*Op*/1, /*Renderer*/GIMT_Encode2(1), GIMT_Encode2(GICP_gi_vop3mods),
        GIM_CheckComplexPattern, /*MI*/2, /*Op*/2, /*Renderer*/GIMT_Encode2(2), GIMT_Encode2(GICP_gi_vop3mods),
        // (fmaxnum:{ *:[f32] } (fminnum_ieee:{ *:[f32] } (VOP3Mods:{ *:[f32] } f32:{ *:[f32] }:$src2, i32:{ *:[i32] }:$src2_mods), (fmaxnum:{ *:[f32] } (VOP3Mods:{ *:[f32] } f32:{ *:[f32] }:$src1, i32:{ *:[i32] }:$src1_mods), (VOP3Mods:{ *:[f32] } f32:{ *:[f32] }:$src0, i32:{ *:[i32] }:$src0_mods))), (fminnum_ieee:{ *:[f32] } (VOP3Mods:{ *:[f32] } f32:{ *:[f32] }:$src0, i32:{ *:[i32] }:$src0_mods), (VOP3Mods:{ *:[f32] } f32:{ *:[f32] }:$src1, i32:{ *:[i32] }:$src1_mods)))<<P:Predicate_fmaxnum_like_nnan>>  =>  (V_MED3_F32_e64:{ *:[f32] } ?:{ *:[i32] }:$src0_mods, ?:{ *:[f32] }:$src0, ?:{ *:[i32] }:$src1_mods, ?:{ *:[f32] }:$src1, ?:{ *:[i32] }:$src2_mods, ?:{ *:[f32] }:$src2, 0:{ *:[i1] }, 0:{ *:[i32] })
        GIR_BuildMI, /*InsnID*/0, /*Opcode*/GIMT_Encode2(AMDGPU::V_MED3_F32_e64),
        GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/0, // DstI[vdst]
        GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(2), /*SubOperand*/1, // src0_mods
        GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(2), /*SubOperand*/0, // src0
        GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(1), /*SubOperand*/1, // src1_mods
        GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(1), /*SubOperand*/0, // src1
        GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/1, // src2_mods
        GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/0, // src2
        GIR_AddImm8, /*InsnID*/0, /*Imm*/0,
        GIR_AddImm8, /*InsnID*/0, /*Imm*/0,
        GIR_ConstrainSelectedInstOperands, /*InsnID*/0,
        GIR_EraseFromParent, /*InsnID*/0,
        // GIR_Coverage, 10148,
        GIR_Done,
      // Label 4714: @322126
      GIM_Try, /*On fail goto*//*Label 4715*/ GIMT_Encode4(322266), // Rule ID 10149 //
        GIM_CheckRegBankForClass, /*MI*/0, /*Op*/0, /*RC*/GIMT_Encode2(AMDGPU::VGPR_32RegClassID),
        GIM_RecordInsn, /*DefineMI*/1, /*MI*/0, /*OpIdx*/1, // MIs[1]
        GIM_CheckOpcode, /*MI*/1, GIMT_Encode2(TargetOpcode::G_FMINNUM_IEEE),
        GIM_CheckType, /*MI*/1, /*Op*/1, /*Type*/GILLT_s32,
        GIM_CheckType, /*MI*/1, /*Op*/2, /*Type*/GILLT_s32,
        GIM_RecordInsn, /*DefineMI*/2, /*MI*/1, /*OpIdx*/2, // MIs[2]
        GIM_CheckOpcode, /*MI*/2, GIMT_Encode2(TargetOpcode::G_FMAXNUM),
        GIM_CheckType, /*MI*/2, /*Op*/1, /*Type*/GILLT_s32,
        GIM_CheckType, /*MI*/2, /*Op*/2, /*Type*/GILLT_s32,
        GIM_RecordInsn, /*DefineMI*/3, /*MI*/0, /*OpIdx*/2, // MIs[3]
        GIM_CheckOpcode, /*MI*/3, GIMT_Encode2(TargetOpcode::G_FMINNUM_IEEE),
        // MIs[3] VOP3Mods:src1:src1_mods
        GIM_CheckIsSameOperand, /*MI*/3, /*OpIdx*/1, /*OtherMI*/2, /*OtherOpIdx*/1,
        // MIs[3] VOP3Mods:src0:src0_mods
        GIM_CheckIsSameOperand, /*MI*/3, /*OpIdx*/2, /*OtherMI*/2, /*OtherOpIdx*/2,
        GIM_CheckCxxInsnPredicate, /*MI*/0, /*FnId*/GIMT_Encode2(GICXXPred_MI_Predicate_fmaxnum_like_nnan),
        GIM_CheckIsSafeToFold, /*InsnID*/1,
        GIM_CheckIsSafeToFold, /*InsnID*/2,
        GIM_CheckIsSafeToFold, /*InsnID*/3,
        GIM_CheckComplexPattern, /*MI*/1, /*Op*/1, /*Renderer*/GIMT_Encode2(0), GIMT_Encode2(GICP_gi_vop3mods),
        GIM_CheckComplexPattern, /*MI*/2, /*Op*/1, /*Renderer*/GIMT_Encode2(1), GIMT_Encode2(GICP_gi_vop3mods),
        GIM_CheckComplexPattern, /*MI*/2, /*Op*/2, /*Renderer*/GIMT_Encode2(2), GIMT_Encode2(GICP_gi_vop3mods),
        // (fmaxnum:{ *:[f32] } (fminnum_ieee:{ *:[f32] } (VOP3Mods:{ *:[f32] } f32:{ *:[f32] }:$src2, i32:{ *:[i32] }:$src2_mods), (fmaxnum:{ *:[f32] } (VOP3Mods:{ *:[f32] } f32:{ *:[f32] }:$src1, i32:{ *:[i32] }:$src1_mods), (VOP3Mods:{ *:[f32] } f32:{ *:[f32] }:$src0, i32:{ *:[i32] }:$src0_mods))), (fminnum_ieee:{ *:[f32] } (VOP3Mods:{ *:[f32] } f32:{ *:[f32] }:$src1, i32:{ *:[i32] }:$src1_mods), (VOP3Mods:{ *:[f32] } f32:{ *:[f32] }:$src0, i32:{ *:[i32] }:$src0_mods)))<<P:Predicate_fmaxnum_like_nnan>>  =>  (V_MED3_F32_e64:{ *:[f32] } ?:{ *:[i32] }:$src0_mods, ?:{ *:[f32] }:$src0, ?:{ *:[i32] }:$src1_mods, ?:{ *:[f32] }:$src1, ?:{ *:[i32] }:$src2_mods, ?:{ *:[f32] }:$src2, 0:{ *:[i1] }, 0:{ *:[i32] })
        GIR_BuildMI, /*InsnID*/0, /*Opcode*/GIMT_Encode2(AMDGPU::V_MED3_F32_e64),
        GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/0, // DstI[vdst]
        GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(2), /*SubOperand*/1, // src0_mods
        GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(2), /*SubOperand*/0, // src0
        GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(1), /*SubOperand*/1, // src1_mods
        GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(1), /*SubOperand*/0, // src1
        GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/1, // src2_mods
        GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/0, // src2
        GIR_AddImm8, /*InsnID*/0, /*Imm*/0,
        GIR_AddImm8, /*InsnID*/0, /*Imm*/0,
        GIR_ConstrainSelectedInstOperands, /*InsnID*/0,
        GIR_EraseFromParent, /*InsnID*/0,
        // GIR_Coverage, 10149,
        GIR_Done,
      // Label 4715: @322266
      GIM_Try, /*On fail goto*//*Label 4716*/ GIMT_Encode4(322406), // Rule ID 10191 //
        GIM_CheckRegBankForClass, /*MI*/0, /*Op*/0, /*RC*/GIMT_Encode2(AMDGPU::VGPR_32RegClassID),
        GIM_RecordInsn, /*DefineMI*/1, /*MI*/0, /*OpIdx*/1, // MIs[1]
        GIM_CheckOpcode, /*MI*/1, GIMT_Encode2(TargetOpcode::G_FMINNUM_IEEE),
        GIM_CheckType, /*MI*/1, /*Op*/1, /*Type*/GILLT_s32,
        GIM_CheckType, /*MI*/1, /*Op*/2, /*Type*/GILLT_s32,
        GIM_RecordInsn, /*DefineMI*/2, /*MI*/1, /*OpIdx*/2, // MIs[2]
        GIM_CheckOpcode, /*MI*/2, GIMT_Encode2(TargetOpcode::G_FMAXNUM_IEEE),
        GIM_CheckType, /*MI*/2, /*Op*/1, /*Type*/GILLT_s32,
        GIM_CheckType, /*MI*/2, /*Op*/2, /*Type*/GILLT_s32,
        GIM_RecordInsn, /*DefineMI*/3, /*MI*/0, /*OpIdx*/2, // MIs[3]
        GIM_CheckOpcode, /*MI*/3, GIMT_Encode2(TargetOpcode::G_FMINNUM),
        // MIs[3] VOP3Mods:src0:src0_mods
        GIM_CheckIsSameOperand, /*MI*/3, /*OpIdx*/1, /*OtherMI*/2, /*OtherOpIdx*/1,
        // MIs[3] VOP3Mods:src1:src1_mods
        GIM_CheckIsSameOperand, /*MI*/3, /*OpIdx*/2, /*OtherMI*/2, /*OtherOpIdx*/2,
        GIM_CheckCxxInsnPredicate, /*MI*/0, /*FnId*/GIMT_Encode2(GICXXPred_MI_Predicate_fmaxnum_like_nnan),
        GIM_CheckIsSafeToFold, /*InsnID*/1,
        GIM_CheckIsSafeToFold, /*InsnID*/2,
        GIM_CheckIsSafeToFold, /*InsnID*/3,
        GIM_CheckComplexPattern, /*MI*/1, /*Op*/1, /*Renderer*/GIMT_Encode2(0), GIMT_Encode2(GICP_gi_vop3mods),
        GIM_CheckComplexPattern, /*MI*/2, /*Op*/1, /*Renderer*/GIMT_Encode2(1), GIMT_Encode2(GICP_gi_vop3mods),
        GIM_CheckComplexPattern, /*MI*/2, /*Op*/2, /*Renderer*/GIMT_Encode2(2), GIMT_Encode2(GICP_gi_vop3mods),
        // (fmaxnum:{ *:[f32] } (fminnum_ieee:{ *:[f32] } (VOP3Mods:{ *:[f32] } f32:{ *:[f32] }:$src2, i32:{ *:[i32] }:$src2_mods), (fmaxnum_ieee:{ *:[f32] } (VOP3Mods:{ *:[f32] } f32:{ *:[f32] }:$src0, i32:{ *:[i32] }:$src0_mods), (VOP3Mods:{ *:[f32] } f32:{ *:[f32] }:$src1, i32:{ *:[i32] }:$src1_mods))), (fminnum:{ *:[f32] } (VOP3Mods:{ *:[f32] } f32:{ *:[f32] }:$src0, i32:{ *:[i32] }:$src0_mods), (VOP3Mods:{ *:[f32] } f32:{ *:[f32] }:$src1, i32:{ *:[i32] }:$src1_mods)))<<P:Predicate_fmaxnum_like_nnan>>  =>  (V_MED3_F32_e64:{ *:[f32] } ?:{ *:[i32] }:$src0_mods, ?:{ *:[f32] }:$src0, ?:{ *:[i32] }:$src1_mods, ?:{ *:[f32] }:$src1, ?:{ *:[i32] }:$src2_mods, ?:{ *:[f32] }:$src2, 0:{ *:[i1] }, 0:{ *:[i32] })
        GIR_BuildMI, /*InsnID*/0, /*Opcode*/GIMT_Encode2(AMDGPU::V_MED3_F32_e64),
        GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/0, // DstI[vdst]
        GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(1), /*SubOperand*/1, // src0_mods
        GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(1), /*SubOperand*/0, // src0
        GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(2), /*SubOperand*/1, // src1_mods
        GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(2), /*SubOperand*/0, // src1
        GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/1, // src2_mods
        GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/0, // src2
        GIR_AddImm8, /*InsnID*/0, /*Imm*/0,
        GIR_AddImm8, /*InsnID*/0, /*Imm*/0,
        GIR_ConstrainSelectedInstOperands, /*InsnID*/0,
        GIR_EraseFromParent, /*InsnID*/0,
        // GIR_Coverage, 10191,
        GIR_Done,
      // Label 4716: @322406
      GIM_Try, /*On fail goto*//*Label 4717*/ GIMT_Encode4(322546), // Rule ID 10192 //
        GIM_CheckRegBankForClass, /*MI*/0, /*Op*/0, /*RC*/GIMT_Encode2(AMDGPU::VGPR_32RegClassID),
        GIM_RecordInsn, /*DefineMI*/1, /*MI*/0, /*OpIdx*/1, // MIs[1]
        GIM_CheckOpcode, /*MI*/1, GIMT_Encode2(TargetOpcode::G_FMINNUM_IEEE),
        GIM_CheckType, /*MI*/1, /*Op*/1, /*Type*/GILLT_s32,
        GIM_CheckType, /*MI*/1, /*Op*/2, /*Type*/GILLT_s32,
        GIM_RecordInsn, /*DefineMI*/2, /*MI*/1, /*OpIdx*/2, // MIs[2]
        GIM_CheckOpcode, /*MI*/2, GIMT_Encode2(TargetOpcode::G_FMAXNUM_IEEE),
        GIM_CheckType, /*MI*/2, /*Op*/1, /*Type*/GILLT_s32,
        GIM_CheckType, /*MI*/2, /*Op*/2, /*Type*/GILLT_s32,
        GIM_RecordInsn, /*DefineMI*/3, /*MI*/0, /*OpIdx*/2, // MIs[3]
        GIM_CheckOpcode, /*MI*/3, GIMT_Encode2(TargetOpcode::G_FMINNUM),
        // MIs[3] VOP3Mods:src1:src1_mods
        GIM_CheckIsSameOperand, /*MI*/3, /*OpIdx*/1, /*OtherMI*/2, /*OtherOpIdx*/2,
        // MIs[3] VOP3Mods:src0:src0_mods
        GIM_CheckIsSameOperand, /*MI*/3, /*OpIdx*/2, /*OtherMI*/2, /*OtherOpIdx*/1,
        GIM_CheckCxxInsnPredicate, /*MI*/0, /*FnId*/GIMT_Encode2(GICXXPred_MI_Predicate_fmaxnum_like_nnan),
        GIM_CheckIsSafeToFold, /*InsnID*/1,
        GIM_CheckIsSafeToFold, /*InsnID*/2,
        GIM_CheckIsSafeToFold, /*InsnID*/3,
        GIM_CheckComplexPattern, /*MI*/1, /*Op*/1, /*Renderer*/GIMT_Encode2(0), GIMT_Encode2(GICP_gi_vop3mods),
        GIM_CheckComplexPattern, /*MI*/2, /*Op*/1, /*Renderer*/GIMT_Encode2(1), GIMT_Encode2(GICP_gi_vop3mods),
        GIM_CheckComplexPattern, /*MI*/2, /*Op*/2, /*Renderer*/GIMT_Encode2(2), GIMT_Encode2(GICP_gi_vop3mods),
        // (fmaxnum:{ *:[f32] } (fminnum_ieee:{ *:[f32] } (VOP3Mods:{ *:[f32] } f32:{ *:[f32] }:$src2, i32:{ *:[i32] }:$src2_mods), (fmaxnum_ieee:{ *:[f32] } (VOP3Mods:{ *:[f32] } f32:{ *:[f32] }:$src0, i32:{ *:[i32] }:$src0_mods), (VOP3Mods:{ *:[f32] } f32:{ *:[f32] }:$src1, i32:{ *:[i32] }:$src1_mods))), (fminnum:{ *:[f32] } (VOP3Mods:{ *:[f32] } f32:{ *:[f32] }:$src1, i32:{ *:[i32] }:$src1_mods), (VOP3Mods:{ *:[f32] } f32:{ *:[f32] }:$src0, i32:{ *:[i32] }:$src0_mods)))<<P:Predicate_fmaxnum_like_nnan>>  =>  (V_MED3_F32_e64:{ *:[f32] } ?:{ *:[i32] }:$src0_mods, ?:{ *:[f32] }:$src0, ?:{ *:[i32] }:$src1_mods, ?:{ *:[f32] }:$src1, ?:{ *:[i32] }:$src2_mods, ?:{ *:[f32] }:$src2, 0:{ *:[i1] }, 0:{ *:[i32] })
        GIR_BuildMI, /*InsnID*/0, /*Opcode*/GIMT_Encode2(AMDGPU::V_MED3_F32_e64),
        GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/0, // DstI[vdst]
        GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(1), /*SubOperand*/1, // src0_mods
        GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(1), /*SubOperand*/0, // src0
        GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(2), /*SubOperand*/1, // src1_mods
        GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(2), /*SubOperand*/0, // src1
        GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/1, // src2_mods
        GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/0, // src2
        GIR_AddImm8, /*InsnID*/0, /*Imm*/0,
        GIR_AddImm8, /*InsnID*/0, /*Imm*/0,
        GIR_ConstrainSelectedInstOperands, /*InsnID*/0,
        GIR_EraseFromParent, /*InsnID*/0,
        // GIR_Coverage, 10192,
        GIR_Done,
      // Label 4717: @322546
      GIM_Try, /*On fail goto*//*Label 4718*/ GIMT_Encode4(322686), // Rule ID 10193 //
        GIM_CheckRegBankForClass, /*MI*/0, /*Op*/0, /*RC*/GIMT_Encode2(AMDGPU::VGPR_32RegClassID),
        GIM_RecordInsn, /*DefineMI*/1, /*MI*/0, /*OpIdx*/1, // MIs[1]
        GIM_CheckOpcode, /*MI*/1, GIMT_Encode2(TargetOpcode::G_FMINNUM_IEEE),
        GIM_CheckType, /*MI*/1, /*Op*/1, /*Type*/GILLT_s32,
        GIM_CheckType, /*MI*/1, /*Op*/2, /*Type*/GILLT_s32,
        GIM_RecordInsn, /*DefineMI*/2, /*MI*/1, /*OpIdx*/2, // MIs[2]
        GIM_CheckOpcode, /*MI*/2, GIMT_Encode2(TargetOpcode::G_FMAXNUM_IEEE),
        GIM_CheckType, /*MI*/2, /*Op*/1, /*Type*/GILLT_s32,
        GIM_CheckType, /*MI*/2, /*Op*/2, /*Type*/GILLT_s32,
        GIM_RecordInsn, /*DefineMI*/3, /*MI*/0, /*OpIdx*/2, // MIs[3]
        GIM_CheckOpcode, /*MI*/3, GIMT_Encode2(TargetOpcode::G_FMINNUM),
        // MIs[3] VOP3Mods:src0:src0_mods
        GIM_CheckIsSameOperand, /*MI*/3, /*OpIdx*/1, /*OtherMI*/2, /*OtherOpIdx*/2,
        // MIs[3] VOP3Mods:src1:src1_mods
        GIM_CheckIsSameOperand, /*MI*/3, /*OpIdx*/2, /*OtherMI*/2, /*OtherOpIdx*/1,
        GIM_CheckCxxInsnPredicate, /*MI*/0, /*FnId*/GIMT_Encode2(GICXXPred_MI_Predicate_fmaxnum_like_nnan),
        GIM_CheckIsSafeToFold, /*InsnID*/1,
        GIM_CheckIsSafeToFold, /*InsnID*/2,
        GIM_CheckIsSafeToFold, /*InsnID*/3,
        GIM_CheckComplexPattern, /*MI*/1, /*Op*/1, /*Renderer*/GIMT_Encode2(0), GIMT_Encode2(GICP_gi_vop3mods),
        GIM_CheckComplexPattern, /*MI*/2, /*Op*/1, /*Renderer*/GIMT_Encode2(1), GIMT_Encode2(GICP_gi_vop3mods),
        GIM_CheckComplexPattern, /*MI*/2, /*Op*/2, /*Renderer*/GIMT_Encode2(2), GIMT_Encode2(GICP_gi_vop3mods),
        // (fmaxnum:{ *:[f32] } (fminnum_ieee:{ *:[f32] } (VOP3Mods:{ *:[f32] } f32:{ *:[f32] }:$src2, i32:{ *:[i32] }:$src2_mods), (fmaxnum_ieee:{ *:[f32] } (VOP3Mods:{ *:[f32] } f32:{ *:[f32] }:$src1, i32:{ *:[i32] }:$src1_mods), (VOP3Mods:{ *:[f32] } f32:{ *:[f32] }:$src0, i32:{ *:[i32] }:$src0_mods))), (fminnum:{ *:[f32] } (VOP3Mods:{ *:[f32] } f32:{ *:[f32] }:$src0, i32:{ *:[i32] }:$src0_mods), (VOP3Mods:{ *:[f32] } f32:{ *:[f32] }:$src1, i32:{ *:[i32] }:$src1_mods)))<<P:Predicate_fmaxnum_like_nnan>>  =>  (V_MED3_F32_e64:{ *:[f32] } ?:{ *:[i32] }:$src0_mods, ?:{ *:[f32] }:$src0, ?:{ *:[i32] }:$src1_mods, ?:{ *:[f32] }:$src1, ?:{ *:[i32] }:$src2_mods, ?:{ *:[f32] }:$src2, 0:{ *:[i1] }, 0:{ *:[i32] })
        GIR_BuildMI, /*InsnID*/0, /*Opcode*/GIMT_Encode2(AMDGPU::V_MED3_F32_e64),
        GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/0, // DstI[vdst]
        GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(2), /*SubOperand*/1, // src0_mods
        GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(2), /*SubOperand*/0, // src0
        GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(1), /*SubOperand*/1, // src1_mods
        GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(1), /*SubOperand*/0, // src1
        GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/1, // src2_mods
        GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/0, // src2
        GIR_AddImm8, /*InsnID*/0, /*Imm*/0,
        GIR_AddImm8, /*InsnID*/0, /*Imm*/0,
        GIR_ConstrainSelectedInstOperands, /*InsnID*/0,
        GIR_EraseFromParent, /*InsnID*/0,
        // GIR_Coverage, 10193,
        GIR_Done,
      // Label 4718: @322686
      GIM_Try, /*On fail goto*//*Label 4719*/ GIMT_Encode4(322826), // Rule ID 10194 //
        GIM_CheckRegBankForClass, /*MI*/0, /*Op*/0, /*RC*/GIMT_Encode2(AMDGPU::VGPR_32RegClassID),
        GIM_RecordInsn, /*DefineMI*/1, /*MI*/0, /*OpIdx*/1, // MIs[1]
        GIM_CheckOpcode, /*MI*/1, GIMT_Encode2(TargetOpcode::G_FMINNUM_IEEE),
        GIM_CheckType, /*MI*/1, /*Op*/1, /*Type*/GILLT_s32,
        GIM_CheckType, /*MI*/1, /*Op*/2, /*Type*/GILLT_s32,
        GIM_RecordInsn, /*DefineMI*/2, /*MI*/1, /*OpIdx*/2, // MIs[2]
        GIM_CheckOpcode, /*MI*/2, GIMT_Encode2(TargetOpcode::G_FMAXNUM_IEEE),
        GIM_CheckType, /*MI*/2, /*Op*/1, /*Type*/GILLT_s32,
        GIM_CheckType, /*MI*/2, /*Op*/2, /*Type*/GILLT_s32,
        GIM_RecordInsn, /*DefineMI*/3, /*MI*/0, /*OpIdx*/2, // MIs[3]
        GIM_CheckOpcode, /*MI*/3, GIMT_Encode2(TargetOpcode::G_FMINNUM),
        // MIs[3] VOP3Mods:src1:src1_mods
        GIM_CheckIsSameOperand, /*MI*/3, /*OpIdx*/1, /*OtherMI*/2, /*OtherOpIdx*/1,
        // MIs[3] VOP3Mods:src0:src0_mods
        GIM_CheckIsSameOperand, /*MI*/3, /*OpIdx*/2, /*OtherMI*/2, /*OtherOpIdx*/2,
        GIM_CheckCxxInsnPredicate, /*MI*/0, /*FnId*/GIMT_Encode2(GICXXPred_MI_Predicate_fmaxnum_like_nnan),
        GIM_CheckIsSafeToFold, /*InsnID*/1,
        GIM_CheckIsSafeToFold, /*InsnID*/2,
        GIM_CheckIsSafeToFold, /*InsnID*/3,
        GIM_CheckComplexPattern, /*MI*/1, /*Op*/1, /*Renderer*/GIMT_Encode2(0), GIMT_Encode2(GICP_gi_vop3mods),
        GIM_CheckComplexPattern, /*MI*/2, /*Op*/1, /*Renderer*/GIMT_Encode2(1), GIMT_Encode2(GICP_gi_vop3mods),
        GIM_CheckComplexPattern, /*MI*/2, /*Op*/2, /*Renderer*/GIMT_Encode2(2), GIMT_Encode2(GICP_gi_vop3mods),
        // (fmaxnum:{ *:[f32] } (fminnum_ieee:{ *:[f32] } (VOP3Mods:{ *:[f32] } f32:{ *:[f32] }:$src2, i32:{ *:[i32] }:$src2_mods), (fmaxnum_ieee:{ *:[f32] } (VOP3Mods:{ *:[f32] } f32:{ *:[f32] }:$src1, i32:{ *:[i32] }:$src1_mods), (VOP3Mods:{ *:[f32] } f32:{ *:[f32] }:$src0, i32:{ *:[i32] }:$src0_mods))), (fminnum:{ *:[f32] } (VOP3Mods:{ *:[f32] } f32:{ *:[f32] }:$src1, i32:{ *:[i32] }:$src1_mods), (VOP3Mods:{ *:[f32] } f32:{ *:[f32] }:$src0, i32:{ *:[i32] }:$src0_mods)))<<P:Predicate_fmaxnum_like_nnan>>  =>  (V_MED3_F32_e64:{ *:[f32] } ?:{ *:[i32] }:$src0_mods, ?:{ *:[f32] }:$src0, ?:{ *:[i32] }:$src1_mods, ?:{ *:[f32] }:$src1, ?:{ *:[i32] }:$src2_mods, ?:{ *:[f32] }:$src2, 0:{ *:[i1] }, 0:{ *:[i32] })
        GIR_BuildMI, /*InsnID*/0, /*Opcode*/GIMT_Encode2(AMDGPU::V_MED3_F32_e64),
        GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/0, // DstI[vdst]
        GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(2), /*SubOperand*/1, // src0_mods
        GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(2), /*SubOperand*/0, // src0
        GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(1), /*SubOperand*/1, // src1_mods
        GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(1), /*SubOperand*/0, // src1
        GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/1, // src2_mods
        GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/0, // src2
        GIR_AddImm8, /*InsnID*/0, /*Imm*/0,
        GIR_AddImm8, /*InsnID*/0, /*Imm*/0,
        GIR_ConstrainSelectedInstOperands, /*InsnID*/0,
        GIR_EraseFromParent, /*InsnID*/0,
        // GIR_Coverage, 10194,
        GIR_Done,
      // Label 4719: @322826
      GIM_Try, /*On fail goto*//*Label 4720*/ GIMT_Encode4(322966), // Rule ID 10131 //
        GIM_CheckRegBankForClass, /*MI*/0, /*Op*/0, /*RC*/GIMT_Encode2(AMDGPU::VGPR_32RegClassID),
        GIM_RecordInsn, /*DefineMI*/1, /*MI*/0, /*OpIdx*/1, // MIs[1]
        GIM_CheckOpcode, /*MI*/1, GIMT_Encode2(TargetOpcode::G_FMINNUM_IEEE),
        GIM_CheckType, /*MI*/1, /*Op*/1, /*Type*/GILLT_s32,
        GIM_CheckType, /*MI*/1, /*Op*/2, /*Type*/GILLT_s32,
        GIM_RecordInsn, /*DefineMI*/2, /*MI*/1, /*OpIdx*/2, // MIs[2]
        GIM_CheckOpcode, /*MI*/2, GIMT_Encode2(TargetOpcode::G_FMAXNUM_IEEE),
        GIM_CheckType, /*MI*/2, /*Op*/1, /*Type*/GILLT_s32,
        GIM_CheckType, /*MI*/2, /*Op*/2, /*Type*/GILLT_s32,
        GIM_RecordInsn, /*DefineMI*/3, /*MI*/0, /*OpIdx*/2, // MIs[3]
        GIM_CheckOpcode, /*MI*/3, GIMT_Encode2(TargetOpcode::G_FMINNUM_IEEE),
        // MIs[3] VOP3Mods:src0:src0_mods
        GIM_CheckIsSameOperand, /*MI*/3, /*OpIdx*/1, /*OtherMI*/2, /*OtherOpIdx*/1,
        // MIs[3] VOP3Mods:src1:src1_mods
        GIM_CheckIsSameOperand, /*MI*/3, /*OpIdx*/2, /*OtherMI*/2, /*OtherOpIdx*/2,
        GIM_CheckCxxInsnPredicate, /*MI*/0, /*FnId*/GIMT_Encode2(GICXXPred_MI_Predicate_fmaxnum_like_nnan),
        GIM_CheckIsSafeToFold, /*InsnID*/1,
        GIM_CheckIsSafeToFold, /*InsnID*/2,
        GIM_CheckIsSafeToFold, /*InsnID*/3,
        GIM_CheckComplexPattern, /*MI*/1, /*Op*/1, /*Renderer*/GIMT_Encode2(0), GIMT_Encode2(GICP_gi_vop3mods),
        GIM_CheckComplexPattern, /*MI*/2, /*Op*/1, /*Renderer*/GIMT_Encode2(1), GIMT_Encode2(GICP_gi_vop3mods),
        GIM_CheckComplexPattern, /*MI*/2, /*Op*/2, /*Renderer*/GIMT_Encode2(2), GIMT_Encode2(GICP_gi_vop3mods),
        // (fmaxnum:{ *:[f32] } (fminnum_ieee:{ *:[f32] } (VOP3Mods:{ *:[f32] } f32:{ *:[f32] }:$src2, i32:{ *:[i32] }:$src2_mods), (fmaxnum_ieee:{ *:[f32] } (VOP3Mods:{ *:[f32] } f32:{ *:[f32] }:$src0, i32:{ *:[i32] }:$src0_mods), (VOP3Mods:{ *:[f32] } f32:{ *:[f32] }:$src1, i32:{ *:[i32] }:$src1_mods))), (fminnum_ieee:{ *:[f32] } (VOP3Mods:{ *:[f32] } f32:{ *:[f32] }:$src0, i32:{ *:[i32] }:$src0_mods), (VOP3Mods:{ *:[f32] } f32:{ *:[f32] }:$src1, i32:{ *:[i32] }:$src1_mods)))<<P:Predicate_fmaxnum_like_nnan>>  =>  (V_MED3_F32_e64:{ *:[f32] } ?:{ *:[i32] }:$src0_mods, ?:{ *:[f32] }:$src0, ?:{ *:[i32] }:$src1_mods, ?:{ *:[f32] }:$src1, ?:{ *:[i32] }:$src2_mods, ?:{ *:[f32] }:$src2, 0:{ *:[i1] }, 0:{ *:[i32] })
        GIR_BuildMI, /*InsnID*/0, /*Opcode*/GIMT_Encode2(AMDGPU::V_MED3_F32_e64),
        GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/0, // DstI[vdst]
        GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(1), /*SubOperand*/1, // src0_mods
        GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(1), /*SubOperand*/0, // src0
        GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(2), /*SubOperand*/1, // src1_mods
        GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(2), /*SubOperand*/0, // src1
        GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/1, // src2_mods
        GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/0, // src2
        GIR_AddImm8, /*InsnID*/0, /*Imm*/0,
        GIR_AddImm8, /*InsnID*/0, /*Imm*/0,
        GIR_ConstrainSelectedInstOperands, /*InsnID*/0,
        GIR_EraseFromParent, /*InsnID*/0,
        // GIR_Coverage, 10131,
        GIR_Done,
      // Label 4720: @322966
      GIM_Try, /*On fail goto*//*Label 4721*/ GIMT_Encode4(323106), // Rule ID 10132 //
        GIM_CheckRegBankForClass, /*MI*/0, /*Op*/0, /*RC*/GIMT_Encode2(AMDGPU::VGPR_32RegClassID),
        GIM_RecordInsn, /*DefineMI*/1, /*MI*/0, /*OpIdx*/1, // MIs[1]
        GIM_CheckOpcode, /*MI*/1, GIMT_Encode2(TargetOpcode::G_FMINNUM_IEEE),
        GIM_CheckType, /*MI*/1, /*Op*/1, /*Type*/GILLT_s32,
        GIM_CheckType, /*MI*/1, /*Op*/2, /*Type*/GILLT_s32,
        GIM_RecordInsn, /*DefineMI*/2, /*MI*/1, /*OpIdx*/2, // MIs[2]
        GIM_CheckOpcode, /*MI*/2, GIMT_Encode2(TargetOpcode::G_FMAXNUM_IEEE),
        GIM_CheckType, /*MI*/2, /*Op*/1, /*Type*/GILLT_s32,
        GIM_CheckType, /*MI*/2, /*Op*/2, /*Type*/GILLT_s32,
        GIM_RecordInsn, /*DefineMI*/3, /*MI*/0, /*OpIdx*/2, // MIs[3]
        GIM_CheckOpcode, /*MI*/3, GIMT_Encode2(TargetOpcode::G_FMINNUM_IEEE),
        // MIs[3] VOP3Mods:src1:src1_mods
        GIM_CheckIsSameOperand, /*MI*/3, /*OpIdx*/1, /*OtherMI*/2, /*OtherOpIdx*/2,
        // MIs[3] VOP3Mods:src0:src0_mods
        GIM_CheckIsSameOperand, /*MI*/3, /*OpIdx*/2, /*OtherMI*/2, /*OtherOpIdx*/1,
        GIM_CheckCxxInsnPredicate, /*MI*/0, /*FnId*/GIMT_Encode2(GICXXPred_MI_Predicate_fmaxnum_like_nnan),
        GIM_CheckIsSafeToFold, /*InsnID*/1,
        GIM_CheckIsSafeToFold, /*InsnID*/2,
        GIM_CheckIsSafeToFold, /*InsnID*/3,
        GIM_CheckComplexPattern, /*MI*/1, /*Op*/1, /*Renderer*/GIMT_Encode2(0), GIMT_Encode2(GICP_gi_vop3mods),
        GIM_CheckComplexPattern, /*MI*/2, /*Op*/1, /*Renderer*/GIMT_Encode2(1), GIMT_Encode2(GICP_gi_vop3mods),
        GIM_CheckComplexPattern, /*MI*/2, /*Op*/2, /*Renderer*/GIMT_Encode2(2), GIMT_Encode2(GICP_gi_vop3mods),
        // (fmaxnum:{ *:[f32] } (fminnum_ieee:{ *:[f32] } (VOP3Mods:{ *:[f32] } f32:{ *:[f32] }:$src2, i32:{ *:[i32] }:$src2_mods), (fmaxnum_ieee:{ *:[f32] } (VOP3Mods:{ *:[f32] } f32:{ *:[f32] }:$src0, i32:{ *:[i32] }:$src0_mods), (VOP3Mods:{ *:[f32] } f32:{ *:[f32] }:$src1, i32:{ *:[i32] }:$src1_mods))), (fminnum_ieee:{ *:[f32] } (VOP3Mods:{ *:[f32] } f32:{ *:[f32] }:$src1, i32:{ *:[i32] }:$src1_mods), (VOP3Mods:{ *:[f32] } f32:{ *:[f32] }:$src0, i32:{ *:[i32] }:$src0_mods)))<<P:Predicate_fmaxnum_like_nnan>>  =>  (V_MED3_F32_e64:{ *:[f32] } ?:{ *:[i32] }:$src0_mods, ?:{ *:[f32] }:$src0, ?:{ *:[i32] }:$src1_mods, ?:{ *:[f32] }:$src1, ?:{ *:[i32] }:$src2_mods, ?:{ *:[f32] }:$src2, 0:{ *:[i1] }, 0:{ *:[i32] })
        GIR_BuildMI, /*InsnID*/0, /*Opcode*/GIMT_Encode2(AMDGPU::V_MED3_F32_e64),
        GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/0, // DstI[vdst]
        GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(1), /*SubOperand*/1, // src0_mods
        GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(1), /*SubOperand*/0, // src0
        GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(2), /*SubOperand*/1, // src1_mods
        GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(2), /*SubOperand*/0, // src1
        GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/1, // src2_mods
        GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/0, // src2
        GIR_AddImm8, /*InsnID*/0, /*Imm*/0,
        GIR_AddImm8, /*InsnID*/0, /*Imm*/0,
        GIR_ConstrainSelectedInstOperands, /*InsnID*/0,
        GIR_EraseFromParent, /*InsnID*/0,
        // GIR_Coverage, 10132,
        GIR_Done,
      // Label 4721: @323106
      GIM_Try, /*On fail goto*//*Label 4722*/ GIMT_Encode4(323246), // Rule ID 10133 //
        GIM_CheckRegBankForClass, /*MI*/0, /*Op*/0, /*RC*/GIMT_Encode2(AMDGPU::VGPR_32RegClassID),
        GIM_RecordInsn, /*DefineMI*/1, /*MI*/0, /*OpIdx*/1, // MIs[1]
        GIM_CheckOpcode, /*MI*/1, GIMT_Encode2(TargetOpcode::G_FMINNUM_IEEE),
        GIM_CheckType, /*MI*/1, /*Op*/1, /*Type*/GILLT_s32,
        GIM_CheckType, /*MI*/1, /*Op*/2, /*Type*/GILLT_s32,
        GIM_RecordInsn, /*DefineMI*/2, /*MI*/1, /*OpIdx*/2, // MIs[2]
        GIM_CheckOpcode, /*MI*/2, GIMT_Encode2(TargetOpcode::G_FMAXNUM_IEEE),
        GIM_CheckType, /*MI*/2, /*Op*/1, /*Type*/GILLT_s32,
        GIM_CheckType, /*MI*/2, /*Op*/2, /*Type*/GILLT_s32,
        GIM_RecordInsn, /*DefineMI*/3, /*MI*/0, /*OpIdx*/2, // MIs[3]
        GIM_CheckOpcode, /*MI*/3, GIMT_Encode2(TargetOpcode::G_FMINNUM_IEEE),
        // MIs[3] VOP3Mods:src0:src0_mods
        GIM_CheckIsSameOperand, /*MI*/3, /*OpIdx*/1, /*OtherMI*/2, /*OtherOpIdx*/2,
        // MIs[3] VOP3Mods:src1:src1_mods
        GIM_CheckIsSameOperand, /*MI*/3, /*OpIdx*/2, /*OtherMI*/2, /*OtherOpIdx*/1,
        GIM_CheckCxxInsnPredicate, /*MI*/0, /*FnId*/GIMT_Encode2(GICXXPred_MI_Predicate_fmaxnum_like_nnan),
        GIM_CheckIsSafeToFold, /*InsnID*/1,
        GIM_CheckIsSafeToFold, /*InsnID*/2,
        GIM_CheckIsSafeToFold, /*InsnID*/3,
        GIM_CheckComplexPattern, /*MI*/1, /*Op*/1, /*Renderer*/GIMT_Encode2(0), GIMT_Encode2(GICP_gi_vop3mods),
        GIM_CheckComplexPattern, /*MI*/2, /*Op*/1, /*Renderer*/GIMT_Encode2(1), GIMT_Encode2(GICP_gi_vop3mods),
        GIM_CheckComplexPattern, /*MI*/2, /*Op*/2, /*Renderer*/GIMT_Encode2(2), GIMT_Encode2(GICP_gi_vop3mods),
        // (fmaxnum:{ *:[f32] } (fminnum_ieee:{ *:[f32] } (VOP3Mods:{ *:[f32] } f32:{ *:[f32] }:$src2, i32:{ *:[i32] }:$src2_mods), (fmaxnum_ieee:{ *:[f32] } (VOP3Mods:{ *:[f32] } f32:{ *:[f32] }:$src1, i32:{ *:[i32] }:$src1_mods), (VOP3Mods:{ *:[f32] } f32:{ *:[f32] }:$src0, i32:{ *:[i32] }:$src0_mods))), (fminnum_ieee:{ *:[f32] } (VOP3Mods:{ *:[f32] } f32:{ *:[f32] }:$src0, i32:{ *:[i32] }:$src0_mods), (VOP3Mods:{ *:[f32] } f32:{ *:[f32] }:$src1, i32:{ *:[i32] }:$src1_mods)))<<P:Predicate_fmaxnum_like_nnan>>  =>  (V_MED3_F32_e64:{ *:[f32] } ?:{ *:[i32] }:$src0_mods, ?:{ *:[f32] }:$src0, ?:{ *:[i32] }:$src1_mods, ?:{ *:[f32] }:$src1, ?:{ *:[i32] }:$src2_mods, ?:{ *:[f32] }:$src2, 0:{ *:[i1] }, 0:{ *:[i32] })
        GIR_BuildMI, /*InsnID*/0, /*Opcode*/GIMT_Encode2(AMDGPU::V_MED3_F32_e64),
        GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/0, // DstI[vdst]
        GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(2), /*SubOperand*/1, // src0_mods
        GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(2), /*SubOperand*/0, // src0
        GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(1), /*SubOperand*/1, // src1_mods
        GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(1), /*SubOperand*/0, // src1
        GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/1, // src2_mods
        GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/0, // src2
        GIR_AddImm8, /*InsnID*/0, /*Imm*/0,
        GIR_AddImm8, /*InsnID*/0, /*Imm*/0,
        GIR_ConstrainSelectedInstOperands, /*InsnID*/0,
        GIR_EraseFromParent, /*InsnID*/0,
        // GIR_Coverage, 10133,
        GIR_Done,
      // Label 4722: @323246
      GIM_Try, /*On fail goto*//*Label 4723*/ GIMT_Encode4(323386), // Rule ID 10134 //
        GIM_CheckRegBankForClass, /*MI*/0, /*Op*/0, /*RC*/GIMT_Encode2(AMDGPU::VGPR_32RegClassID),
        GIM_RecordInsn, /*DefineMI*/1, /*MI*/0, /*OpIdx*/1, // MIs[1]
        GIM_CheckOpcode, /*MI*/1, GIMT_Encode2(TargetOpcode::G_FMINNUM_IEEE),
        GIM_CheckType, /*MI*/1, /*Op*/1, /*Type*/GILLT_s32,
        GIM_CheckType, /*MI*/1, /*Op*/2, /*Type*/GILLT_s32,
        GIM_RecordInsn, /*DefineMI*/2, /*MI*/1, /*OpIdx*/2, // MIs[2]
        GIM_CheckOpcode, /*MI*/2, GIMT_Encode2(TargetOpcode::G_FMAXNUM_IEEE),
        GIM_CheckType, /*MI*/2, /*Op*/1, /*Type*/GILLT_s32,
        GIM_CheckType, /*MI*/2, /*Op*/2, /*Type*/GILLT_s32,
        GIM_RecordInsn, /*DefineMI*/3, /*MI*/0, /*OpIdx*/2, // MIs[3]
        GIM_CheckOpcode, /*MI*/3, GIMT_Encode2(TargetOpcode::G_FMINNUM_IEEE),
        // MIs[3] VOP3Mods:src1:src1_mods
        GIM_CheckIsSameOperand, /*MI*/3, /*OpIdx*/1, /*OtherMI*/2, /*OtherOpIdx*/1,
        // MIs[3] VOP3Mods:src0:src0_mods
        GIM_CheckIsSameOperand, /*MI*/3, /*OpIdx*/2, /*OtherMI*/2, /*OtherOpIdx*/2,
        GIM_CheckCxxInsnPredicate, /*MI*/0, /*FnId*/GIMT_Encode2(GICXXPred_MI_Predicate_fmaxnum_like_nnan),
        GIM_CheckIsSafeToFold, /*InsnID*/1,
        GIM_CheckIsSafeToFold, /*InsnID*/2,
        GIM_CheckIsSafeToFold, /*InsnID*/3,
        GIM_CheckComplexPattern, /*MI*/1, /*Op*/1, /*Renderer*/GIMT_Encode2(0), GIMT_Encode2(GICP_gi_vop3mods),
        GIM_CheckComplexPattern, /*MI*/2, /*Op*/1, /*Renderer*/GIMT_Encode2(1), GIMT_Encode2(GICP_gi_vop3mods),
        GIM_CheckComplexPattern, /*MI*/2, /*Op*/2, /*Renderer*/GIMT_Encode2(2), GIMT_Encode2(GICP_gi_vop3mods),
        // (fmaxnum:{ *:[f32] } (fminnum_ieee:{ *:[f32] } (VOP3Mods:{ *:[f32] } f32:{ *:[f32] }:$src2, i32:{ *:[i32] }:$src2_mods), (fmaxnum_ieee:{ *:[f32] } (VOP3Mods:{ *:[f32] } f32:{ *:[f32] }:$src1, i32:{ *:[i32] }:$src1_mods), (VOP3Mods:{ *:[f32] } f32:{ *:[f32] }:$src0, i32:{ *:[i32] }:$src0_mods))), (fminnum_ieee:{ *:[f32] } (VOP3Mods:{ *:[f32] } f32:{ *:[f32] }:$src1, i32:{ *:[i32] }:$src1_mods), (VOP3Mods:{ *:[f32] } f32:{ *:[f32] }:$src0, i32:{ *:[i32] }:$src0_mods)))<<P:Predicate_fmaxnum_like_nnan>>  =>  (V_MED3_F32_e64:{ *:[f32] } ?:{ *:[i32] }:$src0_mods, ?:{ *:[f32] }:$src0, ?:{ *:[i32] }:$src1_mods, ?:{ *:[f32] }:$src1, ?:{ *:[i32] }:$src2_mods, ?:{ *:[f32] }:$src2, 0:{ *:[i1] }, 0:{ *:[i32] })
        GIR_BuildMI, /*InsnID*/0, /*Opcode*/GIMT_Encode2(AMDGPU::V_MED3_F32_e64),
        GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/0, // DstI[vdst]
        GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(2), /*SubOperand*/1, // src0_mods
        GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(2), /*SubOperand*/0, // src0
        GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(1), /*SubOperand*/1, // src1_mods
        GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(1), /*SubOperand*/0, // src1
        GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/1, // src2_mods
        GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/0, // src2
        GIR_AddImm8, /*InsnID*/0, /*Imm*/0,
        GIR_AddImm8, /*InsnID*/0, /*Imm*/0,
        GIR_ConstrainSelectedInstOperands, /*InsnID*/0,
        GIR_EraseFromParent, /*InsnID*/0,
        // GIR_Coverage, 10134,
        GIR_Done,
      // Label 4723: @323386
      GIM_Try, /*On fail goto*//*Label 4724*/ GIMT_Encode4(323526), // Rule ID 10202 //
        GIM_CheckRegBankForClass, /*MI*/0, /*Op*/0, /*RC*/GIMT_Encode2(AMDGPU::VGPR_32RegClassID),
        GIM_RecordInsn, /*DefineMI*/1, /*MI*/0, /*OpIdx*/1, // MIs[1]
        GIM_CheckOpcode, /*MI*/1, GIMT_Encode2(TargetOpcode::G_FMINNUM_IEEE),
        GIM_CheckType, /*MI*/1, /*Op*/1, /*Type*/GILLT_s32,
        GIM_CheckType, /*MI*/1, /*Op*/2, /*Type*/GILLT_s32,
        GIM_RecordInsn, /*DefineMI*/2, /*MI*/1, /*OpIdx*/1, // MIs[2]
        GIM_CheckOpcode, /*MI*/2, GIMT_Encode2(TargetOpcode::G_FMAXNUM),
        GIM_CheckType, /*MI*/2, /*Op*/1, /*Type*/GILLT_s32,
        GIM_CheckType, /*MI*/2, /*Op*/2, /*Type*/GILLT_s32,
        GIM_RecordInsn, /*DefineMI*/3, /*MI*/0, /*OpIdx*/2, // MIs[3]
        GIM_CheckOpcode, /*MI*/3, GIMT_Encode2(TargetOpcode::G_FMINNUM),
        // MIs[3] VOP3Mods:src0:src0_mods
        GIM_CheckIsSameOperand, /*MI*/3, /*OpIdx*/1, /*OtherMI*/2, /*OtherOpIdx*/1,
        // MIs[3] VOP3Mods:src1:src1_mods
        GIM_CheckIsSameOperand, /*MI*/3, /*OpIdx*/2, /*OtherMI*/2, /*OtherOpIdx*/2,
        GIM_CheckCxxInsnPredicate, /*MI*/0, /*FnId*/GIMT_Encode2(GICXXPred_MI_Predicate_fmaxnum_like_nnan),
        GIM_CheckIsSafeToFold, /*InsnID*/1,
        GIM_CheckIsSafeToFold, /*InsnID*/2,
        GIM_CheckIsSafeToFold, /*InsnID*/3,
        GIM_CheckComplexPattern, /*MI*/1, /*Op*/2, /*Renderer*/GIMT_Encode2(2), GIMT_Encode2(GICP_gi_vop3mods),
        GIM_CheckComplexPattern, /*MI*/2, /*Op*/1, /*Renderer*/GIMT_Encode2(0), GIMT_Encode2(GICP_gi_vop3mods),
        GIM_CheckComplexPattern, /*MI*/2, /*Op*/2, /*Renderer*/GIMT_Encode2(1), GIMT_Encode2(GICP_gi_vop3mods),
        // (fmaxnum:{ *:[f32] } (fminnum_ieee:{ *:[f32] } (fmaxnum:{ *:[f32] } (VOP3Mods:{ *:[f32] } f32:{ *:[f32] }:$src0, i32:{ *:[i32] }:$src0_mods), (VOP3Mods:{ *:[f32] } f32:{ *:[f32] }:$src1, i32:{ *:[i32] }:$src1_mods)), (VOP3Mods:{ *:[f32] } f32:{ *:[f32] }:$src2, i32:{ *:[i32] }:$src2_mods)), (fminnum:{ *:[f32] } (VOP3Mods:{ *:[f32] } f32:{ *:[f32] }:$src0, i32:{ *:[i32] }:$src0_mods), (VOP3Mods:{ *:[f32] } f32:{ *:[f32] }:$src1, i32:{ *:[i32] }:$src1_mods)))<<P:Predicate_fmaxnum_like_nnan>>  =>  (V_MED3_F32_e64:{ *:[f32] } ?:{ *:[i32] }:$src0_mods, ?:{ *:[f32] }:$src0, ?:{ *:[i32] }:$src1_mods, ?:{ *:[f32] }:$src1, ?:{ *:[i32] }:$src2_mods, ?:{ *:[f32] }:$src2, 0:{ *:[i1] }, 0:{ *:[i32] })
        GIR_BuildMI, /*InsnID*/0, /*Opcode*/GIMT_Encode2(AMDGPU::V_MED3_F32_e64),
        GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/0, // DstI[vdst]
        GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/1, // src0_mods
        GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/0, // src0
        GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(1), /*SubOperand*/1, // src1_mods
        GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(1), /*SubOperand*/0, // src1
        GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(2), /*SubOperand*/1, // src2_mods
        GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(2), /*SubOperand*/0, // src2
        GIR_AddImm8, /*InsnID*/0, /*Imm*/0,
        GIR_AddImm8, /*InsnID*/0, /*Imm*/0,
        GIR_ConstrainSelectedInstOperands, /*InsnID*/0,
        GIR_EraseFromParent, /*InsnID*/0,
        // GIR_Coverage, 10202,
        GIR_Done,
      // Label 4724: @323526
      GIM_Try, /*On fail goto*//*Label 4725*/ GIMT_Encode4(323666), // Rule ID 10203 //
        GIM_CheckRegBankForClass, /*MI*/0, /*Op*/0, /*RC*/GIMT_Encode2(AMDGPU::VGPR_32RegClassID),
        GIM_RecordInsn, /*DefineMI*/1, /*MI*/0, /*OpIdx*/1, // MIs[1]
        GIM_CheckOpcode, /*MI*/1, GIMT_Encode2(TargetOpcode::G_FMINNUM_IEEE),
        GIM_CheckType, /*MI*/1, /*Op*/1, /*Type*/GILLT_s32,
        GIM_CheckType, /*MI*/1, /*Op*/2, /*Type*/GILLT_s32,
        GIM_RecordInsn, /*DefineMI*/2, /*MI*/1, /*OpIdx*/1, // MIs[2]
        GIM_CheckOpcode, /*MI*/2, GIMT_Encode2(TargetOpcode::G_FMAXNUM),
        GIM_CheckType, /*MI*/2, /*Op*/1, /*Type*/GILLT_s32,
        GIM_CheckType, /*MI*/2, /*Op*/2, /*Type*/GILLT_s32,
        GIM_RecordInsn, /*DefineMI*/3, /*MI*/0, /*OpIdx*/2, // MIs[3]
        GIM_CheckOpcode, /*MI*/3, GIMT_Encode2(TargetOpcode::G_FMINNUM),
        // MIs[3] VOP3Mods:src1:src1_mods
        GIM_CheckIsSameOperand, /*MI*/3, /*OpIdx*/1, /*OtherMI*/2, /*OtherOpIdx*/2,
        // MIs[3] VOP3Mods:src0:src0_mods
        GIM_CheckIsSameOperand, /*MI*/3, /*OpIdx*/2, /*OtherMI*/2, /*OtherOpIdx*/1,
        GIM_CheckCxxInsnPredicate, /*MI*/0, /*FnId*/GIMT_Encode2(GICXXPred_MI_Predicate_fmaxnum_like_nnan),
        GIM_CheckIsSafeToFold, /*InsnID*/1,
        GIM_CheckIsSafeToFold, /*InsnID*/2,
        GIM_CheckIsSafeToFold, /*InsnID*/3,
        GIM_CheckComplexPattern, /*MI*/1, /*Op*/2, /*Renderer*/GIMT_Encode2(2), GIMT_Encode2(GICP_gi_vop3mods),
        GIM_CheckComplexPattern, /*MI*/2, /*Op*/1, /*Renderer*/GIMT_Encode2(0), GIMT_Encode2(GICP_gi_vop3mods),
        GIM_CheckComplexPattern, /*MI*/2, /*Op*/2, /*Renderer*/GIMT_Encode2(1), GIMT_Encode2(GICP_gi_vop3mods),
        // (fmaxnum:{ *:[f32] } (fminnum_ieee:{ *:[f32] } (fmaxnum:{ *:[f32] } (VOP3Mods:{ *:[f32] } f32:{ *:[f32] }:$src0, i32:{ *:[i32] }:$src0_mods), (VOP3Mods:{ *:[f32] } f32:{ *:[f32] }:$src1, i32:{ *:[i32] }:$src1_mods)), (VOP3Mods:{ *:[f32] } f32:{ *:[f32] }:$src2, i32:{ *:[i32] }:$src2_mods)), (fminnum:{ *:[f32] } (VOP3Mods:{ *:[f32] } f32:{ *:[f32] }:$src1, i32:{ *:[i32] }:$src1_mods), (VOP3Mods:{ *:[f32] } f32:{ *:[f32] }:$src0, i32:{ *:[i32] }:$src0_mods)))<<P:Predicate_fmaxnum_like_nnan>>  =>  (V_MED3_F32_e64:{ *:[f32] } ?:{ *:[i32] }:$src0_mods, ?:{ *:[f32] }:$src0, ?:{ *:[i32] }:$src1_mods, ?:{ *:[f32] }:$src1, ?:{ *:[i32] }:$src2_mods, ?:{ *:[f32] }:$src2, 0:{ *:[i1] }, 0:{ *:[i32] })
        GIR_BuildMI, /*InsnID*/0, /*Opcode*/GIMT_Encode2(AMDGPU::V_MED3_F32_e64),
        GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/0, // DstI[vdst]
        GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/1, // src0_mods
        GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/0, // src0
        GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(1), /*SubOperand*/1, // src1_mods
        GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(1), /*SubOperand*/0, // src1
        GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(2), /*SubOperand*/1, // src2_mods
        GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(2), /*SubOperand*/0, // src2
        GIR_AddImm8, /*InsnID*/0, /*Imm*/0,
        GIR_AddImm8, /*InsnID*/0, /*Imm*/0,
        GIR_ConstrainSelectedInstOperands, /*InsnID*/0,
        GIR_EraseFromParent, /*InsnID*/0,
        // GIR_Coverage, 10203,
        GIR_Done,
      // Label 4725: @323666
      GIM_Try, /*On fail goto*//*Label 4726*/ GIMT_Encode4(323806), // Rule ID 10204 //
        GIM_CheckRegBankForClass, /*MI*/0, /*Op*/0, /*RC*/GIMT_Encode2(AMDGPU::VGPR_32RegClassID),
        GIM_RecordInsn, /*DefineMI*/1, /*MI*/0, /*OpIdx*/1, // MIs[1]
        GIM_CheckOpcode, /*MI*/1, GIMT_Encode2(TargetOpcode::G_FMINNUM_IEEE),
        GIM_CheckType, /*MI*/1, /*Op*/1, /*Type*/GILLT_s32,
        GIM_CheckType, /*MI*/1, /*Op*/2, /*Type*/GILLT_s32,
        GIM_RecordInsn, /*DefineMI*/2, /*MI*/1, /*OpIdx*/1, // MIs[2]
        GIM_CheckOpcode, /*MI*/2, GIMT_Encode2(TargetOpcode::G_FMAXNUM),
        GIM_CheckType, /*MI*/2, /*Op*/1, /*Type*/GILLT_s32,
        GIM_CheckType, /*MI*/2, /*Op*/2, /*Type*/GILLT_s32,
        GIM_RecordInsn, /*DefineMI*/3, /*MI*/0, /*OpIdx*/2, // MIs[3]
        GIM_CheckOpcode, /*MI*/3, GIMT_Encode2(TargetOpcode::G_FMINNUM),
        // MIs[3] VOP3Mods:src0:src0_mods
        GIM_CheckIsSameOperand, /*MI*/3, /*OpIdx*/1, /*OtherMI*/2, /*OtherOpIdx*/2,
        // MIs[3] VOP3Mods:src1:src1_mods
        GIM_CheckIsSameOperand, /*MI*/3, /*OpIdx*/2, /*OtherMI*/2, /*OtherOpIdx*/1,
        GIM_CheckCxxInsnPredicate, /*MI*/0, /*FnId*/GIMT_Encode2(GICXXPred_MI_Predicate_fmaxnum_like_nnan),
        GIM_CheckIsSafeToFold, /*InsnID*/1,
        GIM_CheckIsSafeToFold, /*InsnID*/2,
        GIM_CheckIsSafeToFold, /*InsnID*/3,
        GIM_CheckComplexPattern, /*MI*/1, /*Op*/2, /*Renderer*/GIMT_Encode2(2), GIMT_Encode2(GICP_gi_vop3mods),
        GIM_CheckComplexPattern, /*MI*/2, /*Op*/1, /*Renderer*/GIMT_Encode2(0), GIMT_Encode2(GICP_gi_vop3mods),
        GIM_CheckComplexPattern, /*MI*/2, /*Op*/2, /*Renderer*/GIMT_Encode2(1), GIMT_Encode2(GICP_gi_vop3mods),
        // (fmaxnum:{ *:[f32] } (fminnum_ieee:{ *:[f32] } (fmaxnum:{ *:[f32] } (VOP3Mods:{ *:[f32] } f32:{ *:[f32] }:$src1, i32:{ *:[i32] }:$src1_mods), (VOP3Mods:{ *:[f32] } f32:{ *:[f32] }:$src0, i32:{ *:[i32] }:$src0_mods)), (VOP3Mods:{ *:[f32] } f32:{ *:[f32] }:$src2, i32:{ *:[i32] }:$src2_mods)), (fminnum:{ *:[f32] } (VOP3Mods:{ *:[f32] } f32:{ *:[f32] }:$src0, i32:{ *:[i32] }:$src0_mods), (VOP3Mods:{ *:[f32] } f32:{ *:[f32] }:$src1, i32:{ *:[i32] }:$src1_mods)))<<P:Predicate_fmaxnum_like_nnan>>  =>  (V_MED3_F32_e64:{ *:[f32] } ?:{ *:[i32] }:$src0_mods, ?:{ *:[f32] }:$src0, ?:{ *:[i32] }:$src1_mods, ?:{ *:[f32] }:$src1, ?:{ *:[i32] }:$src2_mods, ?:{ *:[f32] }:$src2, 0:{ *:[i1] }, 0:{ *:[i32] })
        GIR_BuildMI, /*InsnID*/0, /*Opcode*/GIMT_Encode2(AMDGPU::V_MED3_F32_e64),
        GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/0, // DstI[vdst]
        GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(1), /*SubOperand*/1, // src0_mods
        GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(1), /*SubOperand*/0, // src0
        GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/1, // src1_mods
        GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/0, // src1
        GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(2), /*SubOperand*/1, // src2_mods
        GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(2), /*SubOperand*/0, // src2
        GIR_AddImm8, /*InsnID*/0, /*Imm*/0,
        GIR_AddImm8, /*InsnID*/0, /*Imm*/0,
        GIR_ConstrainSelectedInstOperands, /*InsnID*/0,
        GIR_EraseFromParent, /*InsnID*/0,
        // GIR_Coverage, 10204,
        GIR_Done,
      // Label 4726: @323806
      GIM_Try, /*On fail goto*//*Label 4727*/ GIMT_Encode4(323946), // Rule ID 10205 //
        GIM_CheckRegBankForClass, /*MI*/0, /*Op*/0, /*RC*/GIMT_Encode2(AMDGPU::VGPR_32RegClassID),
        GIM_RecordInsn, /*DefineMI*/1, /*MI*/0, /*OpIdx*/1, // MIs[1]
        GIM_CheckOpcode, /*MI*/1, GIMT_Encode2(TargetOpcode::G_FMINNUM_IEEE),
        GIM_CheckType, /*MI*/1, /*Op*/1, /*Type*/GILLT_s32,
        GIM_CheckType, /*MI*/1, /*Op*/2, /*Type*/GILLT_s32,
        GIM_RecordInsn, /*DefineMI*/2, /*MI*/1, /*OpIdx*/1, // MIs[2]
        GIM_CheckOpcode, /*MI*/2, GIMT_Encode2(TargetOpcode::G_FMAXNUM),
        GIM_CheckType, /*MI*/2, /*Op*/1, /*Type*/GILLT_s32,
        GIM_CheckType, /*MI*/2, /*Op*/2, /*Type*/GILLT_s32,
        GIM_RecordInsn, /*DefineMI*/3, /*MI*/0, /*OpIdx*/2, // MIs[3]
        GIM_CheckOpcode, /*MI*/3, GIMT_Encode2(TargetOpcode::G_FMINNUM),
        // MIs[3] VOP3Mods:src1:src1_mods
        GIM_CheckIsSameOperand, /*MI*/3, /*OpIdx*/1, /*OtherMI*/2, /*OtherOpIdx*/1,
        // MIs[3] VOP3Mods:src0:src0_mods
        GIM_CheckIsSameOperand, /*MI*/3, /*OpIdx*/2, /*OtherMI*/2, /*OtherOpIdx*/2,
        GIM_CheckCxxInsnPredicate, /*MI*/0, /*FnId*/GIMT_Encode2(GICXXPred_MI_Predicate_fmaxnum_like_nnan),
        GIM_CheckIsSafeToFold, /*InsnID*/1,
        GIM_CheckIsSafeToFold, /*InsnID*/2,
        GIM_CheckIsSafeToFold, /*InsnID*/3,
        GIM_CheckComplexPattern, /*MI*/1, /*Op*/2, /*Renderer*/GIMT_Encode2(2), GIMT_Encode2(GICP_gi_vop3mods),
        GIM_CheckComplexPattern, /*MI*/2, /*Op*/1, /*Renderer*/GIMT_Encode2(0), GIMT_Encode2(GICP_gi_vop3mods),
        GIM_CheckComplexPattern, /*MI*/2, /*Op*/2, /*Renderer*/GIMT_Encode2(1), GIMT_Encode2(GICP_gi_vop3mods),
        // (fmaxnum:{ *:[f32] } (fminnum_ieee:{ *:[f32] } (fmaxnum:{ *:[f32] } (VOP3Mods:{ *:[f32] } f32:{ *:[f32] }:$src1, i32:{ *:[i32] }:$src1_mods), (VOP3Mods:{ *:[f32] } f32:{ *:[f32] }:$src0, i32:{ *:[i32] }:$src0_mods)), (VOP3Mods:{ *:[f32] } f32:{ *:[f32] }:$src2, i32:{ *:[i32] }:$src2_mods)), (fminnum:{ *:[f32] } (VOP3Mods:{ *:[f32] } f32:{ *:[f32] }:$src1, i32:{ *:[i32] }:$src1_mods), (VOP3Mods:{ *:[f32] } f32:{ *:[f32] }:$src0, i32:{ *:[i32] }:$src0_mods)))<<P:Predicate_fmaxnum_like_nnan>>  =>  (V_MED3_F32_e64:{ *:[f32] } ?:{ *:[i32] }:$src0_mods, ?:{ *:[f32] }:$src0, ?:{ *:[i32] }:$src1_mods, ?:{ *:[f32] }:$src1, ?:{ *:[i32] }:$src2_mods, ?:{ *:[f32] }:$src2, 0:{ *:[i1] }, 0:{ *:[i32] })
        GIR_BuildMI, /*InsnID*/0, /*Opcode*/GIMT_Encode2(AMDGPU::V_MED3_F32_e64),
        GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/0, // DstI[vdst]
        GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(1), /*SubOperand*/1, // src0_mods
        GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(1), /*SubOperand*/0, // src0
        GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/1, // src1_mods
        GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/0, // src1
        GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(2), /*SubOperand*/1, // src2_mods
        GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(2), /*SubOperand*/0, // src2
        GIR_AddImm8, /*InsnID*/0, /*Imm*/0,
        GIR_AddImm8, /*InsnID*/0, /*Imm*/0,
        GIR_ConstrainSelectedInstOperands, /*InsnID*/0,
        GIR_EraseFromParent, /*InsnID*/0,
        // GIR_Coverage, 10205,
        GIR_Done,
      // Label 4727: @323946
      GIM_Try, /*On fail goto*//*Label 4728*/ GIMT_Encode4(324086), // Rule ID 10142 //
        GIM_CheckRegBankForClass, /*MI*/0, /*Op*/0, /*RC*/GIMT_Encode2(AMDGPU::VGPR_32RegClassID),
        GIM_RecordInsn, /*DefineMI*/1, /*MI*/0, /*OpIdx*/1, // MIs[1]
        GIM_CheckOpcode, /*MI*/1, GIMT_Encode2(TargetOpcode::G_FMINNUM_IEEE),
        GIM_CheckType, /*MI*/1, /*Op*/1, /*Type*/GILLT_s32,
        GIM_CheckType, /*MI*/1, /*Op*/2, /*Type*/GILLT_s32,
        GIM_RecordInsn, /*DefineMI*/2, /*MI*/1, /*OpIdx*/1, // MIs[2]
        GIM_CheckOpcode, /*MI*/2, GIMT_Encode2(TargetOpcode::G_FMAXNUM),
        GIM_CheckType, /*MI*/2, /*Op*/1, /*Type*/GILLT_s32,
        GIM_CheckType, /*MI*/2, /*Op*/2, /*Type*/GILLT_s32,
        GIM_RecordInsn, /*DefineMI*/3, /*MI*/0, /*OpIdx*/2, // MIs[3]
        GIM_CheckOpcode, /*MI*/3, GIMT_Encode2(TargetOpcode::G_FMINNUM_IEEE),
        // MIs[3] VOP3Mods:src0:src0_mods
        GIM_CheckIsSameOperand, /*MI*/3, /*OpIdx*/1, /*OtherMI*/2, /*OtherOpIdx*/1,
        // MIs[3] VOP3Mods:src1:src1_mods
        GIM_CheckIsSameOperand, /*MI*/3, /*OpIdx*/2, /*OtherMI*/2, /*OtherOpIdx*/2,
        GIM_CheckCxxInsnPredicate, /*MI*/0, /*FnId*/GIMT_Encode2(GICXXPred_MI_Predicate_fmaxnum_like_nnan),
        GIM_CheckIsSafeToFold, /*InsnID*/1,
        GIM_CheckIsSafeToFold, /*InsnID*/2,
        GIM_CheckIsSafeToFold, /*InsnID*/3,
        GIM_CheckComplexPattern, /*MI*/1, /*Op*/2, /*Renderer*/GIMT_Encode2(2), GIMT_Encode2(GICP_gi_vop3mods),
        GIM_CheckComplexPattern, /*MI*/2, /*Op*/1, /*Renderer*/GIMT_Encode2(0), GIMT_Encode2(GICP_gi_vop3mods),
        GIM_CheckComplexPattern, /*MI*/2, /*Op*/2, /*Renderer*/GIMT_Encode2(1), GIMT_Encode2(GICP_gi_vop3mods),
        // (fmaxnum:{ *:[f32] } (fminnum_ieee:{ *:[f32] } (fmaxnum:{ *:[f32] } (VOP3Mods:{ *:[f32] } f32:{ *:[f32] }:$src0, i32:{ *:[i32] }:$src0_mods), (VOP3Mods:{ *:[f32] } f32:{ *:[f32] }:$src1, i32:{ *:[i32] }:$src1_mods)), (VOP3Mods:{ *:[f32] } f32:{ *:[f32] }:$src2, i32:{ *:[i32] }:$src2_mods)), (fminnum_ieee:{ *:[f32] } (VOP3Mods:{ *:[f32] } f32:{ *:[f32] }:$src0, i32:{ *:[i32] }:$src0_mods), (VOP3Mods:{ *:[f32] } f32:{ *:[f32] }:$src1, i32:{ *:[i32] }:$src1_mods)))<<P:Predicate_fmaxnum_like_nnan>>  =>  (V_MED3_F32_e64:{ *:[f32] } ?:{ *:[i32] }:$src0_mods, ?:{ *:[f32] }:$src0, ?:{ *:[i32] }:$src1_mods, ?:{ *:[f32] }:$src1, ?:{ *:[i32] }:$src2_mods, ?:{ *:[f32] }:$src2, 0:{ *:[i1] }, 0:{ *:[i32] })
        GIR_BuildMI, /*InsnID*/0, /*Opcode*/GIMT_Encode2(AMDGPU::V_MED3_F32_e64),
        GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/0, // DstI[vdst]
        GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/1, // src0_mods
        GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/0, // src0
        GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(1), /*SubOperand*/1, // src1_mods
        GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(1), /*SubOperand*/0, // src1
        GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(2), /*SubOperand*/1, // src2_mods
        GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(2), /*SubOperand*/0, // src2
        GIR_AddImm8, /*InsnID*/0, /*Imm*/0,
        GIR_AddImm8, /*InsnID*/0, /*Imm*/0,
        GIR_ConstrainSelectedInstOperands, /*InsnID*/0,
        GIR_EraseFromParent, /*InsnID*/0,
        // GIR_Coverage, 10142,
        GIR_Done,
      // Label 4728: @324086
      GIM_Try, /*On fail goto*//*Label 4729*/ GIMT_Encode4(324226), // Rule ID 10143 //
        GIM_CheckRegBankForClass, /*MI*/0, /*Op*/0, /*RC*/GIMT_Encode2(AMDGPU::VGPR_32RegClassID),
        GIM_RecordInsn, /*DefineMI*/1, /*MI*/0, /*OpIdx*/1, // MIs[1]
        GIM_CheckOpcode, /*MI*/1, GIMT_Encode2(TargetOpcode::G_FMINNUM_IEEE),
        GIM_CheckType, /*MI*/1, /*Op*/1, /*Type*/GILLT_s32,
        GIM_CheckType, /*MI*/1, /*Op*/2, /*Type*/GILLT_s32,
        GIM_RecordInsn, /*DefineMI*/2, /*MI*/1, /*OpIdx*/1, // MIs[2]
        GIM_CheckOpcode, /*MI*/2, GIMT_Encode2(TargetOpcode::G_FMAXNUM),
        GIM_CheckType, /*MI*/2, /*Op*/1, /*Type*/GILLT_s32,
        GIM_CheckType, /*MI*/2, /*Op*/2, /*Type*/GILLT_s32,
        GIM_RecordInsn, /*DefineMI*/3, /*MI*/0, /*OpIdx*/2, // MIs[3]
        GIM_CheckOpcode, /*MI*/3, GIMT_Encode2(TargetOpcode::G_FMINNUM_IEEE),
        // MIs[3] VOP3Mods:src1:src1_mods
        GIM_CheckIsSameOperand, /*MI*/3, /*OpIdx*/1, /*OtherMI*/2, /*OtherOpIdx*/2,
        // MIs[3] VOP3Mods:src0:src0_mods
        GIM_CheckIsSameOperand, /*MI*/3, /*OpIdx*/2, /*OtherMI*/2, /*OtherOpIdx*/1,
        GIM_CheckCxxInsnPredicate, /*MI*/0, /*FnId*/GIMT_Encode2(GICXXPred_MI_Predicate_fmaxnum_like_nnan),
        GIM_CheckIsSafeToFold, /*InsnID*/1,
        GIM_CheckIsSafeToFold, /*InsnID*/2,
        GIM_CheckIsSafeToFold, /*InsnID*/3,
        GIM_CheckComplexPattern, /*MI*/1, /*Op*/2, /*Renderer*/GIMT_Encode2(2), GIMT_Encode2(GICP_gi_vop3mods),
        GIM_CheckComplexPattern, /*MI*/2, /*Op*/1, /*Renderer*/GIMT_Encode2(0), GIMT_Encode2(GICP_gi_vop3mods),
        GIM_CheckComplexPattern, /*MI*/2, /*Op*/2, /*Renderer*/GIMT_Encode2(1), GIMT_Encode2(GICP_gi_vop3mods),
        // (fmaxnum:{ *:[f32] } (fminnum_ieee:{ *:[f32] } (fmaxnum:{ *:[f32] } (VOP3Mods:{ *:[f32] } f32:{ *:[f32] }:$src0, i32:{ *:[i32] }:$src0_mods), (VOP3Mods:{ *:[f32] } f32:{ *:[f32] }:$src1, i32:{ *:[i32] }:$src1_mods)), (VOP3Mods:{ *:[f32] } f32:{ *:[f32] }:$src2, i32:{ *:[i32] }:$src2_mods)), (fminnum_ieee:{ *:[f32] } (VOP3Mods:{ *:[f32] } f32:{ *:[f32] }:$src1, i32:{ *:[i32] }:$src1_mods), (VOP3Mods:{ *:[f32] } f32:{ *:[f32] }:$src0, i32:{ *:[i32] }:$src0_mods)))<<P:Predicate_fmaxnum_like_nnan>>  =>  (V_MED3_F32_e64:{ *:[f32] } ?:{ *:[i32] }:$src0_mods, ?:{ *:[f32] }:$src0, ?:{ *:[i32] }:$src1_mods, ?:{ *:[f32] }:$src1, ?:{ *:[i32] }:$src2_mods, ?:{ *:[f32] }:$src2, 0:{ *:[i1] }, 0:{ *:[i32] })
        GIR_BuildMI, /*InsnID*/0, /*Opcode*/GIMT_Encode2(AMDGPU::V_MED3_F32_e64),
        GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/0, // DstI[vdst]
        GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/1, // src0_mods
        GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/0, // src0
        GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(1), /*SubOperand*/1, // src1_mods
        GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(1), /*SubOperand*/0, // src1
        GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(2), /*SubOperand*/1, // src2_mods
        GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(2), /*SubOperand*/0, // src2
        GIR_AddImm8, /*InsnID*/0, /*Imm*/0,
        GIR_AddImm8, /*InsnID*/0, /*Imm*/0,
        GIR_ConstrainSelectedInstOperands, /*InsnID*/0,
        GIR_EraseFromParent, /*InsnID*/0,
        // GIR_Coverage, 10143,
        GIR_Done,
      // Label 4729: @324226
      GIM_Try, /*On fail goto*//*Label 4730*/ GIMT_Encode4(324366), // Rule ID 10144 //
        GIM_CheckRegBankForClass, /*MI*/0, /*Op*/0, /*RC*/GIMT_Encode2(AMDGPU::VGPR_32RegClassID),
        GIM_RecordInsn, /*DefineMI*/1, /*MI*/0, /*OpIdx*/1, // MIs[1]
        GIM_CheckOpcode, /*MI*/1, GIMT_Encode2(TargetOpcode::G_FMINNUM_IEEE),
        GIM_CheckType, /*MI*/1, /*Op*/1, /*Type*/GILLT_s32,
        GIM_CheckType, /*MI*/1, /*Op*/2, /*Type*/GILLT_s32,
        GIM_RecordInsn, /*DefineMI*/2, /*MI*/1, /*OpIdx*/1, // MIs[2]
        GIM_CheckOpcode, /*MI*/2, GIMT_Encode2(TargetOpcode::G_FMAXNUM),
        GIM_CheckType, /*MI*/2, /*Op*/1, /*Type*/GILLT_s32,
        GIM_CheckType, /*MI*/2, /*Op*/2, /*Type*/GILLT_s32,
        GIM_RecordInsn, /*DefineMI*/3, /*MI*/0, /*OpIdx*/2, // MIs[3]
        GIM_CheckOpcode, /*MI*/3, GIMT_Encode2(TargetOpcode::G_FMINNUM_IEEE),
        // MIs[3] VOP3Mods:src0:src0_mods
        GIM_CheckIsSameOperand, /*MI*/3, /*OpIdx*/1, /*OtherMI*/2, /*OtherOpIdx*/2,
        // MIs[3] VOP3Mods:src1:src1_mods
        GIM_CheckIsSameOperand, /*MI*/3, /*OpIdx*/2, /*OtherMI*/2, /*OtherOpIdx*/1,
        GIM_CheckCxxInsnPredicate, /*MI*/0, /*FnId*/GIMT_Encode2(GICXXPred_MI_Predicate_fmaxnum_like_nnan),
        GIM_CheckIsSafeToFold, /*InsnID*/1,
        GIM_CheckIsSafeToFold, /*InsnID*/2,
        GIM_CheckIsSafeToFold, /*InsnID*/3,
        GIM_CheckComplexPattern, /*MI*/1, /*Op*/2, /*Renderer*/GIMT_Encode2(2), GIMT_Encode2(GICP_gi_vop3mods),
        GIM_CheckComplexPattern, /*MI*/2, /*Op*/1, /*Renderer*/GIMT_Encode2(0), GIMT_Encode2(GICP_gi_vop3mods),
        GIM_CheckComplexPattern, /*MI*/2, /*Op*/2, /*Renderer*/GIMT_Encode2(1), GIMT_Encode2(GICP_gi_vop3mods),
        // (fmaxnum:{ *:[f32] } (fminnum_ieee:{ *:[f32] } (fmaxnum:{ *:[f32] } (VOP3Mods:{ *:[f32] } f32:{ *:[f32] }:$src1, i32:{ *:[i32] }:$src1_mods), (VOP3Mods:{ *:[f32] } f32:{ *:[f32] }:$src0, i32:{ *:[i32] }:$src0_mods)), (VOP3Mods:{ *:[f32] } f32:{ *:[f32] }:$src2, i32:{ *:[i32] }:$src2_mods)), (fminnum_ieee:{ *:[f32] } (VOP3Mods:{ *:[f32] } f32:{ *:[f32] }:$src0, i32:{ *:[i32] }:$src0_mods), (VOP3Mods:{ *:[f32] } f32:{ *:[f32] }:$src1, i32:{ *:[i32] }:$src1_mods)))<<P:Predicate_fmaxnum_like_nnan>>  =>  (V_MED3_F32_e64:{ *:[f32] } ?:{ *:[i32] }:$src0_mods, ?:{ *:[f32] }:$src0, ?:{ *:[i32] }:$src1_mods, ?:{ *:[f32] }:$src1, ?:{ *:[i32] }:$src2_mods, ?:{ *:[f32] }:$src2, 0:{ *:[i1] }, 0:{ *:[i32] })
        GIR_BuildMI, /*InsnID*/0, /*Opcode*/GIMT_Encode2(AMDGPU::V_MED3_F32_e64),
        GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/0, // DstI[vdst]
        GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(1), /*SubOperand*/1, // src0_mods
        GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(1), /*SubOperand*/0, // src0
        GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/1, // src1_mods
        GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/0, // src1
        GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(2), /*SubOperand*/1, // src2_mods
        GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(2), /*SubOperand*/0, // src2
        GIR_AddImm8, /*InsnID*/0, /*Imm*/0,
        GIR_AddImm8, /*InsnID*/0, /*Imm*/0,
        GIR_ConstrainSelectedInstOperands, /*InsnID*/0,
        GIR_EraseFromParent, /*InsnID*/0,
        // GIR_Coverage, 10144,
        GIR_Done,
      // Label 4730: @324366
      GIM_Try, /*On fail goto*//*Label 4731*/ GIMT_Encode4(324506), // Rule ID 10145 //
        GIM_CheckRegBankForClass, /*MI*/0, /*Op*/0, /*RC*/GIMT_Encode2(AMDGPU::VGPR_32RegClassID),
        GIM_RecordInsn, /*DefineMI*/1, /*MI*/0, /*OpIdx*/1, // MIs[1]
        GIM_CheckOpcode, /*MI*/1, GIMT_Encode2(TargetOpcode::G_FMINNUM_IEEE),
        GIM_CheckType, /*MI*/1, /*Op*/1, /*Type*/GILLT_s32,
        GIM_CheckType, /*MI*/1, /*Op*/2, /*Type*/GILLT_s32,
        GIM_RecordInsn, /*DefineMI*/2, /*MI*/1, /*OpIdx*/1, // MIs[2]
        GIM_CheckOpcode, /*MI*/2, GIMT_Encode2(TargetOpcode::G_FMAXNUM),
        GIM_CheckType, /*MI*/2, /*Op*/1, /*Type*/GILLT_s32,
        GIM_CheckType, /*MI*/2, /*Op*/2, /*Type*/GILLT_s32,
        GIM_RecordInsn, /*DefineMI*/3, /*MI*/0, /*OpIdx*/2, // MIs[3]
        GIM_CheckOpcode, /*MI*/3, GIMT_Encode2(TargetOpcode::G_FMINNUM_IEEE),
        // MIs[3] VOP3Mods:src1:src1_mods
        GIM_CheckIsSameOperand, /*MI*/3, /*OpIdx*/1, /*OtherMI*/2, /*OtherOpIdx*/1,
        // MIs[3] VOP3Mods:src0:src0_mods
        GIM_CheckIsSameOperand, /*MI*/3, /*OpIdx*/2, /*OtherMI*/2, /*OtherOpIdx*/2,
        GIM_CheckCxxInsnPredicate, /*MI*/0, /*FnId*/GIMT_Encode2(GICXXPred_MI_Predicate_fmaxnum_like_nnan),
        GIM_CheckIsSafeToFold, /*InsnID*/1,
        GIM_CheckIsSafeToFold, /*InsnID*/2,
        GIM_CheckIsSafeToFold, /*InsnID*/3,
        GIM_CheckComplexPattern, /*MI*/1, /*Op*/2, /*Renderer*/GIMT_Encode2(2), GIMT_Encode2(GICP_gi_vop3mods),
        GIM_CheckComplexPattern, /*MI*/2, /*Op*/1, /*Renderer*/GIMT_Encode2(0), GIMT_Encode2(GICP_gi_vop3mods),
        GIM_CheckComplexPattern, /*MI*/2, /*Op*/2, /*Renderer*/GIMT_Encode2(1), GIMT_Encode2(GICP_gi_vop3mods),
        // (fmaxnum:{ *:[f32] } (fminnum_ieee:{ *:[f32] } (fmaxnum:{ *:[f32] } (VOP3Mods:{ *:[f32] } f32:{ *:[f32] }:$src1, i32:{ *:[i32] }:$src1_mods), (VOP3Mods:{ *:[f32] } f32:{ *:[f32] }:$src0, i32:{ *:[i32] }:$src0_mods)), (VOP3Mods:{ *:[f32] } f32:{ *:[f32] }:$src2, i32:{ *:[i32] }:$src2_mods)), (fminnum_ieee:{ *:[f32] } (VOP3Mods:{ *:[f32] } f32:{ *:[f32] }:$src1, i32:{ *:[i32] }:$src1_mods), (VOP3Mods:{ *:[f32] } f32:{ *:[f32] }:$src0, i32:{ *:[i32] }:$src0_mods)))<<P:Predicate_fmaxnum_like_nnan>>  =>  (V_MED3_F32_e64:{ *:[f32] } ?:{ *:[i32] }:$src0_mods, ?:{ *:[f32] }:$src0, ?:{ *:[i32] }:$src1_mods, ?:{ *:[f32] }:$src1, ?:{ *:[i32] }:$src2_mods, ?:{ *:[f32] }:$src2, 0:{ *:[i1] }, 0:{ *:[i32] })
        GIR_BuildMI, /*InsnID*/0, /*Opcode*/GIMT_Encode2(AMDGPU::V_MED3_F32_e64),
        GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/0, // DstI[vdst]
        GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(1), /*SubOperand*/1, // src0_mods
        GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(1), /*SubOperand*/0, // src0
        GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/1, // src1_mods
        GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/0, // src1
        GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(2), /*SubOperand*/1, // src2_mods
        GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(2), /*SubOperand*/0, // src2
        GIR_AddImm8, /*InsnID*/0, /*Imm*/0,
        GIR_AddImm8, /*InsnID*/0, /*Imm*/0,
        GIR_ConstrainSelectedInstOperands, /*InsnID*/0,
        GIR_EraseFromParent, /*InsnID*/0,
        // GIR_Coverage, 10145,
        GIR_Done,
      // Label 4731: @324506
      GIM_Try, /*On fail goto*//*Label 4732*/ GIMT_Encode4(324646), // Rule ID 10187 //
        GIM_CheckRegBankForClass, /*MI*/0, /*Op*/0, /*RC*/GIMT_Encode2(AMDGPU::VGPR_32RegClassID),
        GIM_RecordInsn, /*DefineMI*/1, /*MI*/0, /*OpIdx*/1, // MIs[1]
        GIM_CheckOpcode, /*MI*/1, GIMT_Encode2(TargetOpcode::G_FMINNUM_IEEE),
        GIM_CheckType, /*MI*/1, /*Op*/1, /*Type*/GILLT_s32,
        GIM_CheckType, /*MI*/1, /*Op*/2, /*Type*/GILLT_s32,
        GIM_RecordInsn, /*DefineMI*/2, /*MI*/1, /*OpIdx*/1, // MIs[2]
        GIM_CheckOpcode, /*MI*/2, GIMT_Encode2(TargetOpcode::G_FMAXNUM_IEEE),
        GIM_CheckType, /*MI*/2, /*Op*/1, /*Type*/GILLT_s32,
        GIM_CheckType, /*MI*/2, /*Op*/2, /*Type*/GILLT_s32,
        GIM_RecordInsn, /*DefineMI*/3, /*MI*/0, /*OpIdx*/2, // MIs[3]
        GIM_CheckOpcode, /*MI*/3, GIMT_Encode2(TargetOpcode::G_FMINNUM),
        // MIs[3] VOP3Mods:src0:src0_mods
        GIM_CheckIsSameOperand, /*MI*/3, /*OpIdx*/1, /*OtherMI*/2, /*OtherOpIdx*/1,
        // MIs[3] VOP3Mods:src1:src1_mods
        GIM_CheckIsSameOperand, /*MI*/3, /*OpIdx*/2, /*OtherMI*/2, /*OtherOpIdx*/2,
        GIM_CheckCxxInsnPredicate, /*MI*/0, /*FnId*/GIMT_Encode2(GICXXPred_MI_Predicate_fmaxnum_like_nnan),
        GIM_CheckIsSafeToFold, /*InsnID*/1,
        GIM_CheckIsSafeToFold, /*InsnID*/2,
        GIM_CheckIsSafeToFold, /*InsnID*/3,
        GIM_CheckComplexPattern, /*MI*/1, /*Op*/2, /*Renderer*/GIMT_Encode2(2), GIMT_Encode2(GICP_gi_vop3mods),
        GIM_CheckComplexPattern, /*MI*/2, /*Op*/1, /*Renderer*/GIMT_Encode2(0), GIMT_Encode2(GICP_gi_vop3mods),
        GIM_CheckComplexPattern, /*MI*/2, /*Op*/2, /*Renderer*/GIMT_Encode2(1), GIMT_Encode2(GICP_gi_vop3mods),
        // (fmaxnum:{ *:[f32] } (fminnum_ieee:{ *:[f32] } (fmaxnum_ieee:{ *:[f32] } (VOP3Mods:{ *:[f32] } f32:{ *:[f32] }:$src0, i32:{ *:[i32] }:$src0_mods), (VOP3Mods:{ *:[f32] } f32:{ *:[f32] }:$src1, i32:{ *:[i32] }:$src1_mods)), (VOP3Mods:{ *:[f32] } f32:{ *:[f32] }:$src2, i32:{ *:[i32] }:$src2_mods)), (fminnum:{ *:[f32] } (VOP3Mods:{ *:[f32] } f32:{ *:[f32] }:$src0, i32:{ *:[i32] }:$src0_mods), (VOP3Mods:{ *:[f32] } f32:{ *:[f32] }:$src1, i32:{ *:[i32] }:$src1_mods)))<<P:Predicate_fmaxnum_like_nnan>>  =>  (V_MED3_F32_e64:{ *:[f32] } ?:{ *:[i32] }:$src0_mods, ?:{ *:[f32] }:$src0, ?:{ *:[i32] }:$src1_mods, ?:{ *:[f32] }:$src1, ?:{ *:[i32] }:$src2_mods, ?:{ *:[f32] }:$src2, 0:{ *:[i1] }, 0:{ *:[i32] })
        GIR_BuildMI, /*InsnID*/0, /*Opcode*/GIMT_Encode2(AMDGPU::V_MED3_F32_e64),
        GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/0, // DstI[vdst]
        GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/1, // src0_mods
        GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/0, // src0
        GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(1), /*SubOperand*/1, // src1_mods
        GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(1), /*SubOperand*/0, // src1
        GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(2), /*SubOperand*/1, // src2_mods
        GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(2), /*SubOperand*/0, // src2
        GIR_AddImm8, /*InsnID*/0, /*Imm*/0,
        GIR_AddImm8, /*InsnID*/0, /*Imm*/0,
        GIR_ConstrainSelectedInstOperands, /*InsnID*/0,
        GIR_EraseFromParent, /*InsnID*/0,
        // GIR_Coverage, 10187,
        GIR_Done,
      // Label 4732: @324646
      GIM_Try, /*On fail goto*//*Label 4733*/ GIMT_Encode4(324786), // Rule ID 10188 //
        GIM_CheckRegBankForClass, /*MI*/0, /*Op*/0, /*RC*/GIMT_Encode2(AMDGPU::VGPR_32RegClassID),
        GIM_RecordInsn, /*DefineMI*/1, /*MI*/0, /*OpIdx*/1, // MIs[1]
        GIM_CheckOpcode, /*MI*/1, GIMT_Encode2(TargetOpcode::G_FMINNUM_IEEE),
        GIM_CheckType, /*MI*/1, /*Op*/1, /*Type*/GILLT_s32,
        GIM_CheckType, /*MI*/1, /*Op*/2, /*Type*/GILLT_s32,
        GIM_RecordInsn, /*DefineMI*/2, /*MI*/1, /*OpIdx*/1, // MIs[2]
        GIM_CheckOpcode, /*MI*/2, GIMT_Encode2(TargetOpcode::G_FMAXNUM_IEEE),
        GIM_CheckType, /*MI*/2, /*Op*/1, /*Type*/GILLT_s32,
        GIM_CheckType, /*MI*/2, /*Op*/2, /*Type*/GILLT_s32,
        GIM_RecordInsn, /*DefineMI*/3, /*MI*/0, /*OpIdx*/2, // MIs[3]
        GIM_CheckOpcode, /*MI*/3, GIMT_Encode2(TargetOpcode::G_FMINNUM),
        // MIs[3] VOP3Mods:src1:src1_mods
        GIM_CheckIsSameOperand, /*MI*/3, /*OpIdx*/1, /*OtherMI*/2, /*OtherOpIdx*/2,
        // MIs[3] VOP3Mods:src0:src0_mods
        GIM_CheckIsSameOperand, /*MI*/3, /*OpIdx*/2, /*OtherMI*/2, /*OtherOpIdx*/1,
        GIM_CheckCxxInsnPredicate, /*MI*/0, /*FnId*/GIMT_Encode2(GICXXPred_MI_Predicate_fmaxnum_like_nnan),
        GIM_CheckIsSafeToFold, /*InsnID*/1,
        GIM_CheckIsSafeToFold, /*InsnID*/2,
        GIM_CheckIsSafeToFold, /*InsnID*/3,
        GIM_CheckComplexPattern, /*MI*/1, /*Op*/2, /*Renderer*/GIMT_Encode2(2), GIMT_Encode2(GICP_gi_vop3mods),
        GIM_CheckComplexPattern, /*MI*/2, /*Op*/1, /*Renderer*/GIMT_Encode2(0), GIMT_Encode2(GICP_gi_vop3mods),
        GIM_CheckComplexPattern, /*MI*/2, /*Op*/2, /*Renderer*/GIMT_Encode2(1), GIMT_Encode2(GICP_gi_vop3mods),
        // (fmaxnum:{ *:[f32] } (fminnum_ieee:{ *:[f32] } (fmaxnum_ieee:{ *:[f32] } (VOP3Mods:{ *:[f32] } f32:{ *:[f32] }:$src0, i32:{ *:[i32] }:$src0_mods), (VOP3Mods:{ *:[f32] } f32:{ *:[f32] }:$src1, i32:{ *:[i32] }:$src1_mods)), (VOP3Mods:{ *:[f32] } f32:{ *:[f32] }:$src2, i32:{ *:[i32] }:$src2_mods)), (fminnum:{ *:[f32] } (VOP3Mods:{ *:[f32] } f32:{ *:[f32] }:$src1, i32:{ *:[i32] }:$src1_mods), (VOP3Mods:{ *:[f32] } f32:{ *:[f32] }:$src0, i32:{ *:[i32] }:$src0_mods)))<<P:Predicate_fmaxnum_like_nnan>>  =>  (V_MED3_F32_e64:{ *:[f32] } ?:{ *:[i32] }:$src0_mods, ?:{ *:[f32] }:$src0, ?:{ *:[i32] }:$src1_mods, ?:{ *:[f32] }:$src1, ?:{ *:[i32] }:$src2_mods, ?:{ *:[f32] }:$src2, 0:{ *:[i1] }, 0:{ *:[i32] })
        GIR_BuildMI, /*InsnID*/0, /*Opcode*/GIMT_Encode2(AMDGPU::V_MED3_F32_e64),
        GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/0, // DstI[vdst]
        GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/1, // src0_mods
        GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/0, // src0
        GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(1), /*SubOperand*/1, // src1_mods
        GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(1), /*SubOperand*/0, // src1
        GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(2), /*SubOperand*/1, // src2_mods
        GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(2), /*SubOperand*/0, // src2
        GIR_AddImm8, /*InsnID*/0, /*Imm*/0,
        GIR_AddImm8, /*InsnID*/0, /*Imm*/0,
        GIR_ConstrainSelectedInstOperands, /*InsnID*/0,
        GIR_EraseFromParent, /*InsnID*/0,
        // GIR_Coverage, 10188,
        GIR_Done,
      // Label 4733: @324786
      GIM_Try, /*On fail goto*//*Label 4734*/ GIMT_Encode4(324926), // Rule ID 10189 //
        GIM_CheckRegBankForClass, /*MI*/0, /*Op*/0, /*RC*/GIMT_Encode2(AMDGPU::VGPR_32RegClassID),
        GIM_RecordInsn, /*DefineMI*/1, /*MI*/0, /*OpIdx*/1, // MIs[1]
        GIM_CheckOpcode, /*MI*/1, GIMT_Encode2(TargetOpcode::G_FMINNUM_IEEE),
        GIM_CheckType, /*MI*/1, /*Op*/1, /*Type*/GILLT_s32,
        GIM_CheckType, /*MI*/1, /*Op*/2, /*Type*/GILLT_s32,
        GIM_RecordInsn, /*DefineMI*/2, /*MI*/1, /*OpIdx*/1, // MIs[2]
        GIM_CheckOpcode, /*MI*/2, GIMT_Encode2(TargetOpcode::G_FMAXNUM_IEEE),
        GIM_CheckType, /*MI*/2, /*Op*/1, /*Type*/GILLT_s32,
        GIM_CheckType, /*MI*/2, /*Op*/2, /*Type*/GILLT_s32,
        GIM_RecordInsn, /*DefineMI*/3, /*MI*/0, /*OpIdx*/2, // MIs[3]
        GIM_CheckOpcode, /*MI*/3, GIMT_Encode2(TargetOpcode::G_FMINNUM),
        // MIs[3] VOP3Mods:src0:src0_mods
        GIM_CheckIsSameOperand, /*MI*/3, /*OpIdx*/1, /*OtherMI*/2, /*OtherOpIdx*/2,
        // MIs[3] VOP3Mods:src1:src1_mods
        GIM_CheckIsSameOperand, /*MI*/3, /*OpIdx*/2, /*OtherMI*/2, /*OtherOpIdx*/1,
        GIM_CheckCxxInsnPredicate, /*MI*/0, /*FnId*/GIMT_Encode2(GICXXPred_MI_Predicate_fmaxnum_like_nnan),
        GIM_CheckIsSafeToFold, /*InsnID*/1,
        GIM_CheckIsSafeToFold, /*InsnID*/2,
        GIM_CheckIsSafeToFold, /*InsnID*/3,
        GIM_CheckComplexPattern, /*MI*/1, /*Op*/2, /*Renderer*/GIMT_Encode2(2), GIMT_Encode2(GICP_gi_vop3mods),
        GIM_CheckComplexPattern, /*MI*/2, /*Op*/1, /*Renderer*/GIMT_Encode2(0), GIMT_Encode2(GICP_gi_vop3mods),
        GIM_CheckComplexPattern, /*MI*/2, /*Op*/2, /*Renderer*/GIMT_Encode2(1), GIMT_Encode2(GICP_gi_vop3mods),
        // (fmaxnum:{ *:[f32] } (fminnum_ieee:{ *:[f32] } (fmaxnum_ieee:{ *:[f32] } (VOP3Mods:{ *:[f32] } f32:{ *:[f32] }:$src1, i32:{ *:[i32] }:$src1_mods), (VOP3Mods:{ *:[f32] } f32:{ *:[f32] }:$src0, i32:{ *:[i32] }:$src0_mods)), (VOP3Mods:{ *:[f32] } f32:{ *:[f32] }:$src2, i32:{ *:[i32] }:$src2_mods)), (fminnum:{ *:[f32] } (VOP3Mods:{ *:[f32] } f32:{ *:[f32] }:$src0, i32:{ *:[i32] }:$src0_mods), (VOP3Mods:{ *:[f32] } f32:{ *:[f32] }:$src1, i32:{ *:[i32] }:$src1_mods)))<<P:Predicate_fmaxnum_like_nnan>>  =>  (V_MED3_F32_e64:{ *:[f32] } ?:{ *:[i32] }:$src0_mods, ?:{ *:[f32] }:$src0, ?:{ *:[i32] }:$src1_mods, ?:{ *:[f32] }:$src1, ?:{ *:[i32] }:$src2_mods, ?:{ *:[f32] }:$src2, 0:{ *:[i1] }, 0:{ *:[i32] })
        GIR_BuildMI, /*InsnID*/0, /*Opcode*/GIMT_Encode2(AMDGPU::V_MED3_F32_e64),
        GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/0, // DstI[vdst]
        GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(1), /*SubOperand*/1, // src0_mods
        GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(1), /*SubOperand*/0, // src0
        GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/1, // src1_mods
        GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/0, // src1
        GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(2), /*SubOperand*/1, // src2_mods
        GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(2), /*SubOperand*/0, // src2
        GIR_AddImm8, /*InsnID*/0, /*Imm*/0,
        GIR_AddImm8, /*InsnID*/0, /*Imm*/0,
        GIR_ConstrainSelectedInstOperands, /*InsnID*/0,
        GIR_EraseFromParent, /*InsnID*/0,
        // GIR_Coverage, 10189,
        GIR_Done,
      // Label 4734: @324926
      GIM_Try, /*On fail goto*//*Label 4735*/ GIMT_Encode4(325066), // Rule ID 10190 //
        GIM_CheckRegBankForClass, /*MI*/0, /*Op*/0, /*RC*/GIMT_Encode2(AMDGPU::VGPR_32RegClassID),
        GIM_RecordInsn, /*DefineMI*/1, /*MI*/0, /*OpIdx*/1, // MIs[1]
        GIM_CheckOpcode, /*MI*/1, GIMT_Encode2(TargetOpcode::G_FMINNUM_IEEE),
        GIM_CheckType, /*MI*/1, /*Op*/1, /*Type*/GILLT_s32,
        GIM_CheckType, /*MI*/1, /*Op*/2, /*Type*/GILLT_s32,
        GIM_RecordInsn, /*DefineMI*/2, /*MI*/1, /*OpIdx*/1, // MIs[2]
        GIM_CheckOpcode, /*MI*/2, GIMT_Encode2(TargetOpcode::G_FMAXNUM_IEEE),
        GIM_CheckType, /*MI*/2, /*Op*/1, /*Type*/GILLT_s32,
        GIM_CheckType, /*MI*/2, /*Op*/2, /*Type*/GILLT_s32,
        GIM_RecordInsn, /*DefineMI*/3, /*MI*/0, /*OpIdx*/2, // MIs[3]
        GIM_CheckOpcode, /*MI*/3, GIMT_Encode2(TargetOpcode::G_FMINNUM),
        // MIs[3] VOP3Mods:src1:src1_mods
        GIM_CheckIsSameOperand, /*MI*/3, /*OpIdx*/1, /*OtherMI*/2, /*OtherOpIdx*/1,
        // MIs[3] VOP3Mods:src0:src0_mods
        GIM_CheckIsSameOperand, /*MI*/3, /*OpIdx*/2, /*OtherMI*/2, /*OtherOpIdx*/2,
        GIM_CheckCxxInsnPredicate, /*MI*/0, /*FnId*/GIMT_Encode2(GICXXPred_MI_Predicate_fmaxnum_like_nnan),
        GIM_CheckIsSafeToFold, /*InsnID*/1,
        GIM_CheckIsSafeToFold, /*InsnID*/2,
        GIM_CheckIsSafeToFold, /*InsnID*/3,
        GIM_CheckComplexPattern, /*MI*/1, /*Op*/2, /*Renderer*/GIMT_Encode2(2), GIMT_Encode2(GICP_gi_vop3mods),
        GIM_CheckComplexPattern, /*MI*/2, /*Op*/1, /*Renderer*/GIMT_Encode2(0), GIMT_Encode2(GICP_gi_vop3mods),
        GIM_CheckComplexPattern, /*MI*/2, /*Op*/2, /*Renderer*/GIMT_Encode2(1), GIMT_Encode2(GICP_gi_vop3mods),
        // (fmaxnum:{ *:[f32] } (fminnum_ieee:{ *:[f32] } (fmaxnum_ieee:{ *:[f32] } (VOP3Mods:{ *:[f32] } f32:{ *:[f32] }:$src1, i32:{ *:[i32] }:$src1_mods), (VOP3Mods:{ *:[f32] } f32:{ *:[f32] }:$src0, i32:{ *:[i32] }:$src0_mods)), (VOP3Mods:{ *:[f32] } f32:{ *:[f32] }:$src2, i32:{ *:[i32] }:$src2_mods)), (fminnum:{ *:[f32] } (VOP3Mods:{ *:[f32] } f32:{ *:[f32] }:$src1, i32:{ *:[i32] }:$src1_mods), (VOP3Mods:{ *:[f32] } f32:{ *:[f32] }:$src0, i32:{ *:[i32] }:$src0_mods)))<<P:Predicate_fmaxnum_like_nnan>>  =>  (V_MED3_F32_e64:{ *:[f32] } ?:{ *:[i32] }:$src0_mods, ?:{ *:[f32] }:$src0, ?:{ *:[i32] }:$src1_mods, ?:{ *:[f32] }:$src1, ?:{ *:[i32] }:$src2_mods, ?:{ *:[f32] }:$src2, 0:{ *:[i1] }, 0:{ *:[i32] })
        GIR_BuildMI, /*InsnID*/0, /*Opcode*/GIMT_Encode2(AMDGPU::V_MED3_F32_e64),
        GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/0, // DstI[vdst]
        GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(1), /*SubOperand*/1, // src0_mods
        GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(1), /*SubOperand*/0, // src0
        GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/1, // src1_mods
        GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/0, // src1
        GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(2), /*SubOperand*/1, // src2_mods
        GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(2), /*SubOperand*/0, // src2
        GIR_AddImm8, /*InsnID*/0, /*Imm*/0,
        GIR_AddImm8, /*InsnID*/0, /*Imm*/0,
        GIR_ConstrainSelectedInstOperands, /*InsnID*/0,
        GIR_EraseFromParent, /*InsnID*/0,
        // GIR_Coverage, 10190,
        GIR_Done,
      // Label 4735: @325066
      GIM_Try, /*On fail goto*//*Label 4736*/ GIMT_Encode4(325206), // Rule ID 10127 //
        GIM_CheckRegBankForClass, /*MI*/0, /*Op*/0, /*RC*/GIMT_Encode2(AMDGPU::VGPR_32RegClassID),
        GIM_RecordInsn, /*DefineMI*/1, /*MI*/0, /*OpIdx*/1, // MIs[1]
        GIM_CheckOpcode, /*MI*/1, GIMT_Encode2(TargetOpcode::G_FMINNUM_IEEE),
        GIM_CheckType, /*MI*/1, /*Op*/1, /*Type*/GILLT_s32,
        GIM_CheckType, /*MI*/1, /*Op*/2, /*Type*/GILLT_s32,
        GIM_RecordInsn, /*DefineMI*/2, /*MI*/1, /*OpIdx*/1, // MIs[2]
        GIM_CheckOpcode, /*MI*/2, GIMT_Encode2(TargetOpcode::G_FMAXNUM_IEEE),
        GIM_CheckType, /*MI*/2, /*Op*/1, /*Type*/GILLT_s32,
        GIM_CheckType, /*MI*/2, /*Op*/2, /*Type*/GILLT_s32,
        GIM_RecordInsn, /*DefineMI*/3, /*MI*/0, /*OpIdx*/2, // MIs[3]
        GIM_CheckOpcode, /*MI*/3, GIMT_Encode2(TargetOpcode::G_FMINNUM_IEEE),
        // MIs[3] VOP3Mods:src0:src0_mods
        GIM_CheckIsSameOperand, /*MI*/3, /*OpIdx*/1, /*OtherMI*/2, /*OtherOpIdx*/1,
        // MIs[3] VOP3Mods:src1:src1_mods
        GIM_CheckIsSameOperand, /*MI*/3, /*OpIdx*/2, /*OtherMI*/2, /*OtherOpIdx*/2,
        GIM_CheckCxxInsnPredicate, /*MI*/0, /*FnId*/GIMT_Encode2(GICXXPred_MI_Predicate_fmaxnum_like_nnan),
        GIM_CheckIsSafeToFold, /*InsnID*/1,
        GIM_CheckIsSafeToFold, /*InsnID*/2,
        GIM_CheckIsSafeToFold, /*InsnID*/3,
        GIM_CheckComplexPattern, /*MI*/1, /*Op*/2, /*Renderer*/GIMT_Encode2(2), GIMT_Encode2(GICP_gi_vop3mods),
        GIM_CheckComplexPattern, /*MI*/2, /*Op*/1, /*Renderer*/GIMT_Encode2(0), GIMT_Encode2(GICP_gi_vop3mods),
        GIM_CheckComplexPattern, /*MI*/2, /*Op*/2, /*Renderer*/GIMT_Encode2(1), GIMT_Encode2(GICP_gi_vop3mods),
        // (fmaxnum:{ *:[f32] } (fminnum_ieee:{ *:[f32] } (fmaxnum_ieee:{ *:[f32] } (VOP3Mods:{ *:[f32] } f32:{ *:[f32] }:$src0, i32:{ *:[i32] }:$src0_mods), (VOP3Mods:{ *:[f32] } f32:{ *:[f32] }:$src1, i32:{ *:[i32] }:$src1_mods)), (VOP3Mods:{ *:[f32] } f32:{ *:[f32] }:$src2, i32:{ *:[i32] }:$src2_mods)), (fminnum_ieee:{ *:[f32] } (VOP3Mods:{ *:[f32] } f32:{ *:[f32] }:$src0, i32:{ *:[i32] }:$src0_mods), (VOP3Mods:{ *:[f32] } f32:{ *:[f32] }:$src1, i32:{ *:[i32] }:$src1_mods)))<<P:Predicate_fmaxnum_like_nnan>>  =>  (V_MED3_F32_e64:{ *:[f32] } ?:{ *:[i32] }:$src0_mods, ?:{ *:[f32] }:$src0, ?:{ *:[i32] }:$src1_mods, ?:{ *:[f32] }:$src1, ?:{ *:[i32] }:$src2_mods, ?:{ *:[f32] }:$src2, 0:{ *:[i1] }, 0:{ *:[i32] })
        GIR_BuildMI, /*InsnID*/0, /*Opcode*/GIMT_Encode2(AMDGPU::V_MED3_F32_e64),
        GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/0, // DstI[vdst]
        GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/1, // src0_mods
        GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/0, // src0
        GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(1), /*SubOperand*/1, // src1_mods
        GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(1), /*SubOperand*/0, // src1
        GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(2), /*SubOperand*/1, // src2_mods
        GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(2), /*SubOperand*/0, // src2
        GIR_AddImm8, /*InsnID*/0, /*Imm*/0,
        GIR_AddImm8, /*InsnID*/0, /*Imm*/0,
        GIR_ConstrainSelectedInstOperands, /*InsnID*/0,
        GIR_EraseFromParent, /*InsnID*/0,
        // GIR_Coverage, 10127,
        GIR_Done,
      // Label 4736: @325206
      GIM_Try, /*On fail goto*//*Label 4737*/ GIMT_Encode4(325346), // Rule ID 10128 //
        GIM_CheckRegBankForClass, /*MI*/0, /*Op*/0, /*RC*/GIMT_Encode2(AMDGPU::VGPR_32RegClassID),
        GIM_RecordInsn, /*DefineMI*/1, /*MI*/0, /*OpIdx*/1, // MIs[1]
        GIM_CheckOpcode, /*MI*/1, GIMT_Encode2(TargetOpcode::G_FMINNUM_IEEE),
        GIM_CheckType, /*MI*/1, /*Op*/1, /*Type*/GILLT_s32,
        GIM_CheckType, /*MI*/1, /*Op*/2, /*Type*/GILLT_s32,
        GIM_RecordInsn, /*DefineMI*/2, /*MI*/1, /*OpIdx*/1, // MIs[2]
        GIM_CheckOpcode, /*MI*/2, GIMT_Encode2(TargetOpcode::G_FMAXNUM_IEEE),
        GIM_CheckType, /*MI*/2, /*Op*/1, /*Type*/GILLT_s32,
        GIM_CheckType, /*MI*/2, /*Op*/2, /*Type*/GILLT_s32,
        GIM_RecordInsn, /*DefineMI*/3, /*MI*/0, /*OpIdx*/2, // MIs[3]
        GIM_CheckOpcode, /*MI*/3, GIMT_Encode2(TargetOpcode::G_FMINNUM_IEEE),
        // MIs[3] VOP3Mods:src1:src1_mods
        GIM_CheckIsSameOperand, /*MI*/3, /*OpIdx*/1, /*OtherMI*/2, /*OtherOpIdx*/2,
        // MIs[3] VOP3Mods:src0:src0_mods
        GIM_CheckIsSameOperand, /*MI*/3, /*OpIdx*/2, /*OtherMI*/2, /*OtherOpIdx*/1,
        GIM_CheckCxxInsnPredicate, /*MI*/0, /*FnId*/GIMT_Encode2(GICXXPred_MI_Predicate_fmaxnum_like_nnan),
        GIM_CheckIsSafeToFold, /*InsnID*/1,
        GIM_CheckIsSafeToFold, /*InsnID*/2,
        GIM_CheckIsSafeToFold, /*InsnID*/3,
        GIM_CheckComplexPattern, /*MI*/1, /*Op*/2, /*Renderer*/GIMT_Encode2(2), GIMT_Encode2(GICP_gi_vop3mods),
        GIM_CheckComplexPattern, /*MI*/2, /*Op*/1, /*Renderer*/GIMT_Encode2(0), GIMT_Encode2(GICP_gi_vop3mods),
        GIM_CheckComplexPattern, /*MI*/2, /*Op*/2, /*Renderer*/GIMT_Encode2(1), GIMT_Encode2(GICP_gi_vop3mods),
        // (fmaxnum:{ *:[f32] } (fminnum_ieee:{ *:[f32] } (fmaxnum_ieee:{ *:[f32] } (VOP3Mods:{ *:[f32] } f32:{ *:[f32] }:$src0, i32:{ *:[i32] }:$src0_mods), (VOP3Mods:{ *:[f32] } f32:{ *:[f32] }:$src1, i32:{ *:[i32] }:$src1_mods)), (VOP3Mods:{ *:[f32] } f32:{ *:[f32] }:$src2, i32:{ *:[i32] }:$src2_mods)), (fminnum_ieee:{ *:[f32] } (VOP3Mods:{ *:[f32] } f32:{ *:[f32] }:$src1, i32:{ *:[i32] }:$src1_mods), (VOP3Mods:{ *:[f32] } f32:{ *:[f32] }:$src0, i32:{ *:[i32] }:$src0_mods)))<<P:Predicate_fmaxnum_like_nnan>>  =>  (V_MED3_F32_e64:{ *:[f32] } ?:{ *:[i32] }:$src0_mods, ?:{ *:[f32] }:$src0, ?:{ *:[i32] }:$src1_mods, ?:{ *:[f32] }:$src1, ?:{ *:[i32] }:$src2_mods, ?:{ *:[f32] }:$src2, 0:{ *:[i1] }, 0:{ *:[i32] })
        GIR_BuildMI, /*InsnID*/0, /*Opcode*/GIMT_Encode2(AMDGPU::V_MED3_F32_e64),
        GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/0, // DstI[vdst]
        GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/1, // src0_mods
        GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/0, // src0
        GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(1), /*SubOperand*/1, // src1_mods
        GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(1), /*SubOperand*/0, // src1
        GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(2), /*SubOperand*/1, // src2_mods
        GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(2), /*SubOperand*/0, // src2
        GIR_AddImm8, /*InsnID*/0, /*Imm*/0,
        GIR_AddImm8, /*InsnID*/0, /*Imm*/0,
        GIR_ConstrainSelectedInstOperands, /*InsnID*/0,
        GIR_EraseFromParent, /*InsnID*/0,
        // GIR_Coverage, 10128,
        GIR_Done,
      // Label 4737: @325346
      GIM_Try, /*On fail goto*//*Label 4738*/ GIMT_Encode4(325486), // Rule ID 10129 //
        GIM_CheckRegBankForClass, /*MI*/0, /*Op*/0, /*RC*/GIMT_Encode2(AMDGPU::VGPR_32RegClassID),
        GIM_RecordInsn, /*DefineMI*/1, /*MI*/0, /*OpIdx*/1, // MIs[1]
        GIM_CheckOpcode, /*MI*/1, GIMT_Encode2(TargetOpcode::G_FMINNUM_IEEE),
        GIM_CheckType, /*MI*/1, /*Op*/1, /*Type*/GILLT_s32,
        GIM_CheckType, /*MI*/1, /*Op*/2, /*Type*/GILLT_s32,
        GIM_RecordInsn, /*DefineMI*/2, /*MI*/1, /*OpIdx*/1, // MIs[2]
        GIM_CheckOpcode, /*MI*/2, GIMT_Encode2(TargetOpcode::G_FMAXNUM_IEEE),
        GIM_CheckType, /*MI*/2, /*Op*/1, /*Type*/GILLT_s32,
        GIM_CheckType, /*MI*/2, /*Op*/2, /*Type*/GILLT_s32,
        GIM_RecordInsn, /*DefineMI*/3, /*MI*/0, /*OpIdx*/2, // MIs[3]
        GIM_CheckOpcode, /*MI*/3, GIMT_Encode2(TargetOpcode::G_FMINNUM_IEEE),
        // MIs[3] VOP3Mods:src0:src0_mods
        GIM_CheckIsSameOperand, /*MI*/3, /*OpIdx*/1, /*OtherMI*/2, /*OtherOpIdx*/2,
        // MIs[3] VOP3Mods:src1:src1_mods
        GIM_CheckIsSameOperand, /*MI*/3, /*OpIdx*/2, /*OtherMI*/2, /*OtherOpIdx*/1,
        GIM_CheckCxxInsnPredicate, /*MI*/0, /*FnId*/GIMT_Encode2(GICXXPred_MI_Predicate_fmaxnum_like_nnan),
        GIM_CheckIsSafeToFold, /*InsnID*/1,
        GIM_CheckIsSafeToFold, /*InsnID*/2,
        GIM_CheckIsSafeToFold, /*InsnID*/3,
        GIM_CheckComplexPattern, /*MI*/1, /*Op*/2, /*Renderer*/GIMT_Encode2(2), GIMT_Encode2(GICP_gi_vop3mods),
        GIM_CheckComplexPattern, /*MI*/2, /*Op*/1, /*Renderer*/GIMT_Encode2(0), GIMT_Encode2(GICP_gi_vop3mods),
        GIM_CheckComplexPattern, /*MI*/2, /*Op*/2, /*Renderer*/GIMT_Encode2(1), GIMT_Encode2(GICP_gi_vop3mods),
        // (fmaxnum:{ *:[f32] } (fminnum_ieee:{ *:[f32] } (fmaxnum_ieee:{ *:[f32] } (VOP3Mods:{ *:[f32] } f32:{ *:[f32] }:$src1, i32:{ *:[i32] }:$src1_mods), (VOP3Mods:{ *:[f32] } f32:{ *:[f32] }:$src0, i32:{ *:[i32] }:$src0_mods)), (VOP3Mods:{ *:[f32] } f32:{ *:[f32] }:$src2, i32:{ *:[i32] }:$src2_mods)), (fminnum_ieee:{ *:[f32] } (VOP3Mods:{ *:[f32] } f32:{ *:[f32] }:$src0, i32:{ *:[i32] }:$src0_mods), (VOP3Mods:{ *:[f32] } f32:{ *:[f32] }:$src1, i32:{ *:[i32] }:$src1_mods)))<<P:Predicate_fmaxnum_like_nnan>>  =>  (V_MED3_F32_e64:{ *:[f32] } ?:{ *:[i32] }:$src0_mods, ?:{ *:[f32] }:$src0, ?:{ *:[i32] }:$src1_mods, ?:{ *:[f32] }:$src1, ?:{ *:[i32] }:$src2_mods, ?:{ *:[f32] }:$src2, 0:{ *:[i1] }, 0:{ *:[i32] })
        GIR_BuildMI, /*InsnID*/0, /*Opcode*/GIMT_Encode2(AMDGPU::V_MED3_F32_e64),
        GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/0, // DstI[vdst]
        GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(1), /*SubOperand*/1, // src0_mods
        GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(1), /*SubOperand*/0, // src0
        GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/1, // src1_mods
        GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/0, // src1
        GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(2), /*SubOperand*/1, // src2_mods
        GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(2), /*SubOperand*/0, // src2
        GIR_AddImm8, /*InsnID*/0, /*Imm*/0,
        GIR_AddImm8, /*InsnID*/0, /*Imm*/0,
        GIR_ConstrainSelectedInstOperands, /*InsnID*/0,
        GIR_EraseFromParent, /*InsnID*/0,
        // GIR_Coverage, 10129,
        GIR_Done,
      // Label 4738: @325486
      GIM_Try, /*On fail goto*//*Label 4739*/ GIMT_Encode4(325626), // Rule ID 10130 //
        GIM_CheckRegBankForClass, /*MI*/0, /*Op*/0, /*RC*/GIMT_Encode2(AMDGPU::VGPR_32RegClassID),
        GIM_RecordInsn, /*DefineMI*/1, /*MI*/0, /*OpIdx*/1, // MIs[1]
        GIM_CheckOpcode, /*MI*/1, GIMT_Encode2(TargetOpcode::G_FMINNUM_IEEE),
        GIM_CheckType, /*MI*/1, /*Op*/1, /*Type*/GILLT_s32,
        GIM_CheckType, /*MI*/1, /*Op*/2, /*Type*/GILLT_s32,
        GIM_RecordInsn, /*DefineMI*/2, /*MI*/1, /*OpIdx*/1, // MIs[2]
        GIM_CheckOpcode, /*MI*/2, GIMT_Encode2(TargetOpcode::G_FMAXNUM_IEEE),
        GIM_CheckType, /*MI*/2, /*Op*/1, /*Type*/GILLT_s32,
        GIM_CheckType, /*MI*/2, /*Op*/2, /*Type*/GILLT_s32,
        GIM_RecordInsn, /*DefineMI*/3, /*MI*/0, /*OpIdx*/2, // MIs[3]
        GIM_CheckOpcode, /*MI*/3, GIMT_Encode2(TargetOpcode::G_FMINNUM_IEEE),
        // MIs[3] VOP3Mods:src1:src1_mods
        GIM_CheckIsSameOperand, /*MI*/3, /*OpIdx*/1, /*OtherMI*/2, /*OtherOpIdx*/1,
        // MIs[3] VOP3Mods:src0:src0_mods
        GIM_CheckIsSameOperand, /*MI*/3, /*OpIdx*/2, /*OtherMI*/2, /*OtherOpIdx*/2,
        GIM_CheckCxxInsnPredicate, /*MI*/0, /*FnId*/GIMT_Encode2(GICXXPred_MI_Predicate_fmaxnum_like_nnan),
        GIM_CheckIsSafeToFold, /*InsnID*/1,
        GIM_CheckIsSafeToFold, /*InsnID*/2,
        GIM_CheckIsSafeToFold, /*InsnID*/3,
        GIM_CheckComplexPattern, /*MI*/1, /*Op*/2, /*Renderer*/GIMT_Encode2(2), GIMT_Encode2(GICP_gi_vop3mods),
        GIM_CheckComplexPattern, /*MI*/2, /*Op*/1, /*Renderer*/GIMT_Encode2(0), GIMT_Encode2(GICP_gi_vop3mods),
        GIM_CheckComplexPattern, /*MI*/2, /*Op*/2, /*Renderer*/GIMT_Encode2(1), GIMT_Encode2(GICP_gi_vop3mods),
        // (fmaxnum:{ *:[f32] } (fminnum_ieee:{ *:[f32] } (fmaxnum_ieee:{ *:[f32] } (VOP3Mods:{ *:[f32] } f32:{ *:[f32] }:$src1, i32:{ *:[i32] }:$src1_mods), (VOP3Mods:{ *:[f32] } f32:{ *:[f32] }:$src0, i32:{ *:[i32] }:$src0_mods)), (VOP3Mods:{ *:[f32] } f32:{ *:[f32] }:$src2, i32:{ *:[i32] }:$src2_mods)), (fminnum_ieee:{ *:[f32] } (VOP3Mods:{ *:[f32] } f32:{ *:[f32] }:$src1, i32:{ *:[i32] }:$src1_mods), (VOP3Mods:{ *:[f32] } f32:{ *:[f32] }:$src0, i32:{ *:[i32] }:$src0_mods)))<<P:Predicate_fmaxnum_like_nnan>>  =>  (V_MED3_F32_e64:{ *:[f32] } ?:{ *:[i32] }:$src0_mods, ?:{ *:[f32] }:$src0, ?:{ *:[i32] }:$src1_mods, ?:{ *:[f32] }:$src1, ?:{ *:[i32] }:$src2_mods, ?:{ *:[f32] }:$src2, 0:{ *:[i1] }, 0:{ *:[i32] })
        GIR_BuildMI, /*InsnID*/0, /*Opcode*/GIMT_Encode2(AMDGPU::V_MED3_F32_e64),
        GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/0, // DstI[vdst]
        GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(1), /*SubOperand*/1, // src0_mods
        GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(1), /*SubOperand*/0, // src0
        GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/1, // src1_mods
        GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/0, // src1
        GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(2), /*SubOperand*/1, // src2_mods
        GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(2), /*SubOperand*/0, // src2
        GIR_AddImm8, /*InsnID*/0, /*Imm*/0,
        GIR_AddImm8, /*InsnID*/0, /*Imm*/0,
        GIR_ConstrainSelectedInstOperands, /*InsnID*/0,
        GIR_EraseFromParent, /*InsnID*/0,
        // GIR_Coverage, 10130,
        GIR_Done,
      // Label 4739: @325626
      GIM_Try, /*On fail goto*//*Label 4740*/ GIMT_Encode4(325731), // Rule ID 10517 //
        GIM_CheckFeatures, GIMT_Encode2(GIFBS_isGFX11Plus),
        GIM_CheckRegBankForClass, /*MI*/0, /*Op*/0, /*RC*/GIMT_Encode2(AMDGPU::VGPR_32RegClassID),
        GIM_RecordInsn, /*DefineMI*/1, /*MI*/0, /*OpIdx*/2, // MIs[1]
        GIM_CheckOpcode, /*MI*/1, GIMT_Encode2(TargetOpcode::G_FMINNUM),
        GIM_CheckType, /*MI*/1, /*Op*/1, /*Type*/GILLT_s32,
        GIM_CheckType, /*MI*/1, /*Op*/2, /*Type*/GILLT_s32,
        GIM_CheckCxxInsnPredicate, /*MI*/1, /*FnId*/GIMT_Encode2(GICXXPred_MI_Predicate_fminnum_oneuse),
        GIM_CheckIsSafeToFold, /*InsnID*/1,
        GIM_CheckComplexPattern, /*MI*/0, /*Op*/1, /*Renderer*/GIMT_Encode2(0), GIMT_Encode2(GICP_gi_vop3mods),
        GIM_CheckComplexPattern, /*MI*/1, /*Op*/1, /*Renderer*/GIMT_Encode2(1), GIMT_Encode2(GICP_gi_vop3mods),
        GIM_CheckComplexPattern, /*MI*/1, /*Op*/2, /*Renderer*/GIMT_Encode2(2), GIMT_Encode2(GICP_gi_vop3mods),
        // (fmaxnum:{ *:[f32] } (VOP3Mods:{ *:[f32] } f32:{ *:[f32] }:$src2, i32:{ *:[i32] }:$src2_mods), (fminnum:{ *:[f32] } (VOP3Mods:{ *:[f32] } f32:{ *:[f32] }:$src0, i32:{ *:[i32] }:$src0_mods), (VOP3Mods:{ *:[f32] } f32:{ *:[f32] }:$src1, i32:{ *:[i32] }:$src1_mods))<<P:Predicate_fminnum_oneuse>>)  =>  (V_MINMAX_F32_e64:{ *:[f32] } ?:{ *:[i32] }:$src0_mods, ?:{ *:[f32] }:$src0, ?:{ *:[i32] }:$src1_mods, ?:{ *:[f32] }:$src1, ?:{ *:[i32] }:$src2_mods, ?:{ *:[f32] }:$src2, 0:{ *:[i1] }, 0:{ *:[i32] })
        GIR_BuildMI, /*InsnID*/0, /*Opcode*/GIMT_Encode2(AMDGPU::V_MINMAX_F32_e64),
        GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/0, // DstI[vdst]
        GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(1), /*SubOperand*/1, // src0_mods
        GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(1), /*SubOperand*/0, // src0
        GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(2), /*SubOperand*/1, // src1_mods
        GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(2), /*SubOperand*/0, // src1
        GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/1, // src2_mods
        GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/0, // src2
        GIR_AddImm8, /*InsnID*/0, /*Imm*/0,
        GIR_AddImm8, /*InsnID*/0, /*Imm*/0,
        GIR_ConstrainSelectedInstOperands, /*InsnID*/0,
        GIR_EraseFromParent, /*InsnID*/0,
        // GIR_Coverage, 10517,
        GIR_Done,
      // Label 4740: @325731
      GIM_Try, /*On fail goto*//*Label 4741*/ GIMT_Encode4(325836), // Rule ID 10516 //
        GIM_CheckFeatures, GIMT_Encode2(GIFBS_isGFX11Plus),
        GIM_CheckRegBankForClass, /*MI*/0, /*Op*/0, /*RC*/GIMT_Encode2(AMDGPU::VGPR_32RegClassID),
        GIM_RecordInsn, /*DefineMI*/1, /*MI*/0, /*OpIdx*/2, // MIs[1]
        GIM_CheckOpcode, /*MI*/1, GIMT_Encode2(TargetOpcode::G_FMINNUM_IEEE),
        GIM_CheckType, /*MI*/1, /*Op*/1, /*Type*/GILLT_s32,
        GIM_CheckType, /*MI*/1, /*Op*/2, /*Type*/GILLT_s32,
        GIM_CheckCxxInsnPredicate, /*MI*/1, /*FnId*/GIMT_Encode2(GICXXPred_MI_Predicate_fminnum_ieee_oneuse),
        GIM_CheckIsSafeToFold, /*InsnID*/1,
        GIM_CheckComplexPattern, /*MI*/0, /*Op*/1, /*Renderer*/GIMT_Encode2(0), GIMT_Encode2(GICP_gi_vop3mods),
        GIM_CheckComplexPattern, /*MI*/1, /*Op*/1, /*Renderer*/GIMT_Encode2(1), GIMT_Encode2(GICP_gi_vop3mods),
        GIM_CheckComplexPattern, /*MI*/1, /*Op*/2, /*Renderer*/GIMT_Encode2(2), GIMT_Encode2(GICP_gi_vop3mods),
        // (fmaxnum:{ *:[f32] } (VOP3Mods:{ *:[f32] } f32:{ *:[f32] }:$src2, i32:{ *:[i32] }:$src2_mods), (fminnum_ieee:{ *:[f32] } (VOP3Mods:{ *:[f32] } f32:{ *:[f32] }:$src0, i32:{ *:[i32] }:$src0_mods), (VOP3Mods:{ *:[f32] } f32:{ *:[f32] }:$src1, i32:{ *:[i32] }:$src1_mods))<<P:Predicate_fminnum_ieee_oneuse>>)  =>  (V_MINMAX_F32_e64:{ *:[f32] } ?:{ *:[i32] }:$src0_mods, ?:{ *:[f32] }:$src0, ?:{ *:[i32] }:$src1_mods, ?:{ *:[f32] }:$src1, ?:{ *:[i32] }:$src2_mods, ?:{ *:[f32] }:$src2, 0:{ *:[i1] }, 0:{ *:[i32] })
        GIR_BuildMI, /*InsnID*/0, /*Opcode*/GIMT_Encode2(AMDGPU::V_MINMAX_F32_e64),
        GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/0, // DstI[vdst]
        GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(1), /*SubOperand*/1, // src0_mods
        GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(1), /*SubOperand*/0, // src0
        GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(2), /*SubOperand*/1, // src1_mods
        GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(2), /*SubOperand*/0, // src1
        GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/1, // src2_mods
        GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/0, // src2
        GIR_AddImm8, /*InsnID*/0, /*Imm*/0,
        GIR_AddImm8, /*InsnID*/0, /*Imm*/0,
        GIR_ConstrainSelectedInstOperands, /*InsnID*/0,
        GIR_EraseFromParent, /*InsnID*/0,
        // GIR_Coverage, 10516,
        GIR_Done,
      // Label 4741: @325836
      GIM_Try, /*On fail goto*//*Label 4742*/ GIMT_Encode4(325941), // Rule ID 6523 //
        GIM_CheckFeatures, GIMT_Encode2(GIFBS_isGFX11Plus),
        GIM_CheckRegBankForClass, /*MI*/0, /*Op*/0, /*RC*/GIMT_Encode2(AMDGPU::VGPR_32RegClassID),
        GIM_RecordInsn, /*DefineMI*/1, /*MI*/0, /*OpIdx*/1, // MIs[1]
        GIM_CheckOpcode, /*MI*/1, GIMT_Encode2(TargetOpcode::G_FMINNUM),
        GIM_CheckType, /*MI*/1, /*Op*/1, /*Type*/GILLT_s32,
        GIM_CheckType, /*MI*/1, /*Op*/2, /*Type*/GILLT_s32,
        GIM_CheckCxxInsnPredicate, /*MI*/1, /*FnId*/GIMT_Encode2(GICXXPred_MI_Predicate_fminnum_oneuse),
        GIM_CheckIsSafeToFold, /*InsnID*/1,
        GIM_CheckComplexPattern, /*MI*/0, /*Op*/2, /*Renderer*/GIMT_Encode2(2), GIMT_Encode2(GICP_gi_vop3mods),
        GIM_CheckComplexPattern, /*MI*/1, /*Op*/1, /*Renderer*/GIMT_Encode2(0), GIMT_Encode2(GICP_gi_vop3mods),
        GIM_CheckComplexPattern, /*MI*/1, /*Op*/2, /*Renderer*/GIMT_Encode2(1), GIMT_Encode2(GICP_gi_vop3mods),
        // (fmaxnum:{ *:[f32] } (fminnum:{ *:[f32] } (VOP3Mods:{ *:[f32] } f32:{ *:[f32] }:$src0, i32:{ *:[i32] }:$src0_mods), (VOP3Mods:{ *:[f32] } f32:{ *:[f32] }:$src1, i32:{ *:[i32] }:$src1_mods))<<P:Predicate_fminnum_oneuse>>, (VOP3Mods:{ *:[f32] } f32:{ *:[f32] }:$src2, i32:{ *:[i32] }:$src2_mods))  =>  (V_MINMAX_F32_e64:{ *:[f32] } ?:{ *:[i32] }:$src0_mods, ?:{ *:[f32] }:$src0, ?:{ *:[i32] }:$src1_mods, ?:{ *:[f32] }:$src1, ?:{ *:[i32] }:$src2_mods, ?:{ *:[f32] }:$src2, 0:{ *:[i1] }, 0:{ *:[i32] })
        GIR_BuildMI, /*InsnID*/0, /*Opcode*/GIMT_Encode2(AMDGPU::V_MINMAX_F32_e64),
        GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/0, // DstI[vdst]
        GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/1, // src0_mods
        GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/0, // src0
        GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(1), /*SubOperand*/1, // src1_mods
        GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(1), /*SubOperand*/0, // src1
        GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(2), /*SubOperand*/1, // src2_mods
        GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(2), /*SubOperand*/0, // src2
        GIR_AddImm8, /*InsnID*/0, /*Imm*/0,
        GIR_AddImm8, /*InsnID*/0, /*Imm*/0,
        GIR_ConstrainSelectedInstOperands, /*InsnID*/0,
        GIR_EraseFromParent, /*InsnID*/0,
        // GIR_Coverage, 6523,
        GIR_Done,
      // Label 4742: @325941
      GIM_Try, /*On fail goto*//*Label 4743*/ GIMT_Encode4(326046), // Rule ID 6522 //
        GIM_CheckFeatures, GIMT_Encode2(GIFBS_isGFX11Plus),
        GIM_CheckRegBankForClass, /*MI*/0, /*Op*/0, /*RC*/GIMT_Encode2(AMDGPU::VGPR_32RegClassID),
        GIM_RecordInsn, /*DefineMI*/1, /*MI*/0, /*OpIdx*/1, // MIs[1]
        GIM_CheckOpcode, /*MI*/1, GIMT_Encode2(TargetOpcode::G_FMINNUM_IEEE),
        GIM_CheckType, /*MI*/1, /*Op*/1, /*Type*/GILLT_s32,
        GIM_CheckType, /*MI*/1, /*Op*/2, /*Type*/GILLT_s32,
        GIM_CheckCxxInsnPredicate, /*MI*/1, /*FnId*/GIMT_Encode2(GICXXPred_MI_Predicate_fminnum_ieee_oneuse),
        GIM_CheckIsSafeToFold, /*InsnID*/1,
        GIM_CheckComplexPattern, /*MI*/0, /*Op*/2, /*Renderer*/GIMT_Encode2(2), GIMT_Encode2(GICP_gi_vop3mods),
        GIM_CheckComplexPattern, /*MI*/1, /*Op*/1, /*Renderer*/GIMT_Encode2(0), GIMT_Encode2(GICP_gi_vop3mods),
        GIM_CheckComplexPattern, /*MI*/1, /*Op*/2, /*Renderer*/GIMT_Encode2(1), GIMT_Encode2(GICP_gi_vop3mods),
        // (fmaxnum:{ *:[f32] } (fminnum_ieee:{ *:[f32] } (VOP3Mods:{ *:[f32] } f32:{ *:[f32] }:$src0, i32:{ *:[i32] }:$src0_mods), (VOP3Mods:{ *:[f32] } f32:{ *:[f32] }:$src1, i32:{ *:[i32] }:$src1_mods))<<P:Predicate_fminnum_ieee_oneuse>>, (VOP3Mods:{ *:[f32] } f32:{ *:[f32] }:$src2, i32:{ *:[i32] }:$src2_mods))  =>  (V_MINMAX_F32_e64:{ *:[f32] } ?:{ *:[i32] }:$src0_mods, ?:{ *:[f32] }:$src0, ?:{ *:[i32] }:$src1_mods, ?:{ *:[f32] }:$src1, ?:{ *:[i32] }:$src2_mods, ?:{ *:[f32] }:$src2, 0:{ *:[i1] }, 0:{ *:[i32] })
        GIR_BuildMI, /*InsnID*/0, /*Opcode*/GIMT_Encode2(AMDGPU::V_MINMAX_F32_e64),
        GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/0, // DstI[vdst]
        GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/1, // src0_mods
        GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/0, // src0
        GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(1), /*SubOperand*/1, // src1_mods
        GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(1), /*SubOperand*/0, // src1
        GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(2), /*SubOperand*/1, // src2_mods
        GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(2), /*SubOperand*/0, // src2
        GIR_AddImm8, /*InsnID*/0, /*Imm*/0,
        GIR_AddImm8, /*InsnID*/0, /*Imm*/0,
        GIR_ConstrainSelectedInstOperands, /*InsnID*/0,
        GIR_EraseFromParent, /*InsnID*/0,
        // GIR_Coverage, 6522,
        GIR_Done,
      // Label 4743: @326046
      GIM_Try, /*On fail goto*//*Label 4744*/ GIMT_Encode4(326085), // Rule ID 95 //
        GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasSALUFloatInsts),
        GIM_CheckRegBankForClass, /*MI*/0, /*Op*/0, /*RC*/GIMT_Encode2(AMDGPU::SReg_32RegClassID),
        GIM_CheckRegBankForClass, /*MI*/0, /*Op*/1, /*RC*/GIMT_Encode2(AMDGPU::SReg_32RegClassID),
        GIM_CheckRegBankForClass, /*MI*/0, /*Op*/2, /*RC*/GIMT_Encode2(AMDGPU::SReg_32RegClassID),
        GIM_CheckCxxInsnPredicate, /*MI*/0, /*FnId*/GIMT_Encode2(GICXXPred_MI_Predicate_anonymous_17632),
        // (fmaxnum:{ *:[f32] } SSrc_f32:{ *:[f32] }:$src0, SSrc_f32:{ *:[f32] }:$src1)<<P:Predicate_anonymous_17632>>  =>  (S_MAX_F32:{ *:[f32] } SSrc_f32:{ *:[f32] }:$src0, SSrc_f32:{ *:[f32] }:$src1)
        GIR_MutateOpcode, /*InsnID*/0, /*RecycleInsnID*/0, /*Opcode*/GIMT_Encode2(AMDGPU::S_MAX_F32),
        GIR_AddImplicitUse, /*InsnID*/0, GIMT_Encode2(AMDGPU::MODE),
        GIR_ConstrainSelectedInstOperands, /*InsnID*/0,
        // GIR_Coverage, 95,
        GIR_Done,
      // Label 4744: @326085
      GIM_Try, /*On fail goto*//*Label 4745*/ GIMT_Encode4(326152), // Rule ID 742 //
        GIM_CheckRegBankForClass, /*MI*/0, /*Op*/0, /*RC*/GIMT_Encode2(AMDGPU::VGPR_32RegClassID),
        GIM_CheckComplexPattern, /*MI*/0, /*Op*/1, /*Renderer*/GIMT_Encode2(0), GIMT_Encode2(GICP_gi_vop3mods0),
        GIM_CheckComplexPattern, /*MI*/0, /*Op*/2, /*Renderer*/GIMT_Encode2(1), GIMT_Encode2(GICP_gi_vop3mods),
        // (fmaxnum:{ *:[f32] } (VOP3Mods0:{ *:[f32] } f32:{ *:[f32] }:$src0, i32:{ *:[i32] }:$src0_modifiers, i1:{ *:[i1] }:$clamp, i32:{ *:[i32] }:$omod), (VOP3Mods:{ *:[f32] } f32:{ *:[f32] }:$src1, i32:{ *:[i32] }:$src1_modifiers))  =>  (V_MAX_F32_e64:{ *:[f32] } i32:{ *:[i32] }:$src0_modifiers, f32:{ *:[f32] }:$src0, i32:{ *:[i32] }:$src1_modifiers, f32:{ *:[f32] }:$src1, i1:{ *:[i1] }:$clamp, i32:{ *:[i32] }:$omod)
        GIR_BuildMI, /*InsnID*/0, /*Opcode*/GIMT_Encode2(AMDGPU::V_MAX_F32_e64),
        GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/0, // DstI[vdst]
        GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/1, // src0_modifiers
        GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/0, // src0
        GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(1), /*SubOperand*/1, // src1_modifiers
        GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(1), /*SubOperand*/0, // src1
        GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/2, // clamp
        GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/3, // omod
        GIR_ConstrainSelectedInstOperands, /*InsnID*/0,
        GIR_EraseFromParent, /*InsnID*/0,
        // GIR_Coverage, 742,
        GIR_Done,
      // Label 4745: @326152
      GIM_Try, /*On fail goto*//*Label 4746*/ GIMT_Encode4(326219), // Rule ID 7134 //
        GIM_CheckRegBankForClass, /*MI*/0, /*Op*/0, /*RC*/GIMT_Encode2(AMDGPU::VGPR_32RegClassID),
        GIM_CheckComplexPattern, /*MI*/0, /*Op*/1, /*Renderer*/GIMT_Encode2(0), GIMT_Encode2(GICP_gi_vop3mods),
        GIM_CheckComplexPattern, /*MI*/0, /*Op*/2, /*Renderer*/GIMT_Encode2(1), GIMT_Encode2(GICP_gi_vop3mods0),
        // (fmaxnum:{ *:[f32] } (VOP3Mods:{ *:[f32] } f32:{ *:[f32] }:$src1, i32:{ *:[i32] }:$src1_modifiers), (VOP3Mods0:{ *:[f32] } f32:{ *:[f32] }:$src0, i32:{ *:[i32] }:$src0_modifiers, i1:{ *:[i1] }:$clamp, i32:{ *:[i32] }:$omod))  =>  (V_MAX_F32_e64:{ *:[f32] } i32:{ *:[i32] }:$src0_modifiers, f32:{ *:[f32] }:$src0, i32:{ *:[i32] }:$src1_modifiers, f32:{ *:[f32] }:$src1, i1:{ *:[i1] }:$clamp, i32:{ *:[i32] }:$omod)
        GIR_BuildMI, /*InsnID*/0, /*Opcode*/GIMT_Encode2(AMDGPU::V_MAX_F32_e64),
        GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/0, // DstI[vdst]
        GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(1), /*SubOperand*/1, // src0_modifiers
        GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(1), /*SubOperand*/0, // src0
        GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/1, // src1_modifiers
        GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/0, // src1
        GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(1), /*SubOperand*/2, // clamp
        GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(1), /*SubOperand*/3, // omod
        GIR_ConstrainSelectedInstOperands, /*InsnID*/0,
        GIR_EraseFromParent, /*InsnID*/0,
        // GIR_Coverage, 7134,
        GIR_Done,
      // Label 4746: @326219
      GIM_Reject,
    // Label 4611: @326220
    GIM_Reject,
    // Label 4468: @326221
    GIM_Try, /*On fail goto*//*Label 4747*/ GIMT_Encode4(326500),
      GIM_CheckType, /*MI*/0, /*Op*/1, /*Type*/GILLT_s64,
      GIM_CheckType, /*MI*/0, /*Op*/2, /*Type*/GILLT_s64,
      GIM_CheckRegBankForClass, /*MI*/0, /*Op*/0, /*RC*/GIMT_Encode2(AMDGPU::VReg_64RegClassID),
      GIM_Try, /*On fail goto*//*Label 4748*/ GIMT_Encode4(326304), // Rule ID 845 //
        GIM_CheckFeatures, GIMT_Encode2(GIFBS_isGFX12Plus),
        GIM_CheckComplexPattern, /*MI*/0, /*Op*/1, /*Renderer*/GIMT_Encode2(0), GIMT_Encode2(GICP_gi_vop3mods0),
        GIM_CheckComplexPattern, /*MI*/0, /*Op*/2, /*Renderer*/GIMT_Encode2(1), GIMT_Encode2(GICP_gi_vop3mods),
        // (fmaxnum:{ *:[f64] } (VOP3Mods0:{ *:[f64] } f64:{ *:[f64] }:$src0, i32:{ *:[i32] }:$src0_modifiers, i1:{ *:[i1] }:$clamp, i32:{ *:[i32] }:$omod), (VOP3Mods:{ *:[f64] } f64:{ *:[f64] }:$src1, i32:{ *:[i32] }:$src1_modifiers))  =>  (V_MAX_NUM_F64_e64:{ *:[f64] } i32:{ *:[i32] }:$src0_modifiers, f64:{ *:[f64] }:$src0, i32:{ *:[i32] }:$src1_modifiers, f64:{ *:[f64] }:$src1, i1:{ *:[i1] }:$clamp, i32:{ *:[i32] }:$omod)
        GIR_BuildMI, /*InsnID*/0, /*Opcode*/GIMT_Encode2(AMDGPU::V_MAX_NUM_F64_e64),
        GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/0, // DstI[vdst]
        GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/1, // src0_modifiers
        GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/0, // src0
        GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(1), /*SubOperand*/1, // src1_modifiers
        GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(1), /*SubOperand*/0, // src1
        GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/2, // clamp
        GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/3, // omod
        GIR_ConstrainSelectedInstOperands, /*InsnID*/0,
        GIR_EraseFromParent, /*InsnID*/0,
        // GIR_Coverage, 845,
        GIR_Done,
      // Label 4748: @326304
      GIM_Try, /*On fail goto*//*Label 4749*/ GIMT_Encode4(326369), // Rule ID 864 //
        GIM_CheckFeatures, GIMT_Encode2(GIFBS_isNotGFX12Plus),
        GIM_CheckComplexPattern, /*MI*/0, /*Op*/1, /*Renderer*/GIMT_Encode2(0), GIMT_Encode2(GICP_gi_vop3mods0),
        GIM_CheckComplexPattern, /*MI*/0, /*Op*/2, /*Renderer*/GIMT_Encode2(1), GIMT_Encode2(GICP_gi_vop3mods),
        // (fmaxnum:{ *:[f64] } (VOP3Mods0:{ *:[f64] } f64:{ *:[f64] }:$src0, i32:{ *:[i32] }:$src0_modifiers, i1:{ *:[i1] }:$clamp, i32:{ *:[i32] }:$omod), (VOP3Mods:{ *:[f64] } f64:{ *:[f64] }:$src1, i32:{ *:[i32] }:$src1_modifiers))  =>  (V_MAX_F64_e64:{ *:[f64] } i32:{ *:[i32] }:$src0_modifiers, f64:{ *:[f64] }:$src0, i32:{ *:[i32] }:$src1_modifiers, f64:{ *:[f64] }:$src1, i1:{ *:[i1] }:$clamp, i32:{ *:[i32] }:$omod)
        GIR_BuildMI, /*InsnID*/0, /*Opcode*/GIMT_Encode2(AMDGPU::V_MAX_F64_e64),
        GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/0, // DstI[vdst]
        GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/1, // src0_modifiers
        GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/0, // src0
        GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(1), /*SubOperand*/1, // src1_modifiers
        GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(1), /*SubOperand*/0, // src1
        GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/2, // clamp
        GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/3, // omod
        GIR_ConstrainSelectedInstOperands, /*InsnID*/0,
        GIR_EraseFromParent, /*InsnID*/0,
        // GIR_Coverage, 864,
        GIR_Done,
      // Label 4749: @326369
      GIM_Try, /*On fail goto*//*Label 4750*/ GIMT_Encode4(326434), // Rule ID 7168 //
        GIM_CheckFeatures, GIMT_Encode2(GIFBS_isGFX12Plus),
        GIM_CheckComplexPattern, /*MI*/0, /*Op*/1, /*Renderer*/GIMT_Encode2(0), GIMT_Encode2(GICP_gi_vop3mods),
        GIM_CheckComplexPattern, /*MI*/0, /*Op*/2, /*Renderer*/GIMT_Encode2(1), GIMT_Encode2(GICP_gi_vop3mods0),
        // (fmaxnum:{ *:[f64] } (VOP3Mods:{ *:[f64] } f64:{ *:[f64] }:$src1, i32:{ *:[i32] }:$src1_modifiers), (VOP3Mods0:{ *:[f64] } f64:{ *:[f64] }:$src0, i32:{ *:[i32] }:$src0_modifiers, i1:{ *:[i1] }:$clamp, i32:{ *:[i32] }:$omod))  =>  (V_MAX_NUM_F64_e64:{ *:[f64] } i32:{ *:[i32] }:$src0_modifiers, f64:{ *:[f64] }:$src0, i32:{ *:[i32] }:$src1_modifiers, f64:{ *:[f64] }:$src1, i1:{ *:[i1] }:$clamp, i32:{ *:[i32] }:$omod)
        GIR_BuildMI, /*InsnID*/0, /*Opcode*/GIMT_Encode2(AMDGPU::V_MAX_NUM_F64_e64),
        GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/0, // DstI[vdst]
        GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(1), /*SubOperand*/1, // src0_modifiers
        GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(1), /*SubOperand*/0, // src0
        GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/1, // src1_modifiers
        GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/0, // src1
        GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(1), /*SubOperand*/2, // clamp
        GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(1), /*SubOperand*/3, // omod
        GIR_ConstrainSelectedInstOperands, /*InsnID*/0,
        GIR_EraseFromParent, /*InsnID*/0,
        // GIR_Coverage, 7168,
        GIR_Done,
      // Label 4750: @326434
      GIM_Try, /*On fail goto*//*Label 4751*/ GIMT_Encode4(326499), // Rule ID 7182 //
        GIM_CheckFeatures, GIMT_Encode2(GIFBS_isNotGFX12Plus),
        GIM_CheckComplexPattern, /*MI*/0, /*Op*/1, /*Renderer*/GIMT_Encode2(0), GIMT_Encode2(GICP_gi_vop3mods),
        GIM_CheckComplexPattern, /*MI*/0, /*Op*/2, /*Renderer*/GIMT_Encode2(1), GIMT_Encode2(GICP_gi_vop3mods0),
        // (fmaxnum:{ *:[f64] } (VOP3Mods:{ *:[f64] } f64:{ *:[f64] }:$src1, i32:{ *:[i32] }:$src1_modifiers), (VOP3Mods0:{ *:[f64] } f64:{ *:[f64] }:$src0, i32:{ *:[i32] }:$src0_modifiers, i1:{ *:[i1] }:$clamp, i32:{ *:[i32] }:$omod))  =>  (V_MAX_F64_e64:{ *:[f64] } i32:{ *:[i32] }:$src0_modifiers, f64:{ *:[f64] }:$src0, i32:{ *:[i32] }:$src1_modifiers, f64:{ *:[f64] }:$src1, i1:{ *:[i1] }:$clamp, i32:{ *:[i32] }:$omod)
        GIR_BuildMI, /*InsnID*/0, /*Opcode*/GIMT_Encode2(AMDGPU::V_MAX_F64_e64),
        GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/0, // DstI[vdst]
        GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(1), /*SubOperand*/1, // src0_modifiers
        GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(1), /*SubOperand*/0, // src0
        GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/1, // src1_modifiers
        GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/0, // src1
        GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(1), /*SubOperand*/2, // clamp
        GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(1), /*SubOperand*/3, // omod
        GIR_ConstrainSelectedInstOperands, /*InsnID*/0,
        GIR_EraseFromParent, /*InsnID*/0,
        // GIR_Coverage, 7182,
        GIR_Done,
      // Label 4751: @326499
      GIM_Reject,
    // Label 4747: @326500
    GIM_Reject,
    // Label 4469: @326501
    GIM_Try, /*On fail goto*//*Label 4752*/ GIMT_Encode4(326581), // Rule ID 965 //
      GIM_CheckType, /*MI*/0, /*Op*/1, /*Type*/GILLT_v2s16,
      GIM_CheckType, /*MI*/0, /*Op*/2, /*Type*/GILLT_v2s16,
      GIM_CheckRegBankForClass, /*MI*/0, /*Op*/0, /*RC*/GIMT_Encode2(AMDGPU::VGPR_32RegClassID),
      GIM_CheckComplexPattern, /*MI*/0, /*Op*/1, /*Renderer*/GIMT_Encode2(0), GIMT_Encode2(GICP_gi_vop3pmods),
      GIM_CheckComplexPattern, /*MI*/0, /*Op*/2, /*Renderer*/GIMT_Encode2(1), GIMT_Encode2(GICP_gi_vop3pmods),
      // (fmaxnum:{ *:[v2f16] } (VOP3PMods:{ *:[v2f16] } v2f16:{ *:[v2f16] }:$src0, i32:{ *:[i32] }:$src0_modifiers), (VOP3PMods:{ *:[v2f16] } v2f16:{ *:[v2f16] }:$src1, i32:{ *:[i32] }:$src1_modifiers))  =>  (V_PK_MAX_F16:{ *:[v2f16] } i32:{ *:[i32] }:$src0_modifiers, v2f16:{ *:[v2f16] }:$src0, i32:{ *:[i32] }:$src1_modifiers, v2f16:{ *:[v2f16] }:$src1)
      GIR_BuildMI, /*InsnID*/0, /*Opcode*/GIMT_Encode2(AMDGPU::V_PK_MAX_F16),
      GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/0, // DstI[vdst]
      GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/1, // src0_modifiers
      GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/0, // src0
      GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(1), /*SubOperand*/1, // src1_modifiers
      GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(1), /*SubOperand*/0, // src1
      GIR_AddImm8, /*InsnID*/0, /*Imm*/0,
      GIR_AddImm8, /*InsnID*/0, /*Imm*/0,
      GIR_AddImm8, /*InsnID*/0, /*Imm*/0,
      GIR_AddImm8, /*InsnID*/0, /*Imm*/0,
      GIR_AddImm8, /*InsnID*/0, /*Imm*/0,
      GIR_ConstrainSelectedInstOperands, /*InsnID*/0,
      GIR_EraseFromParent, /*InsnID*/0,
      // GIR_Coverage, 965,
      GIR_Done,
    // Label 4752: @326581
    GIM_Reject,
    // Label 4470: @326582
    GIM_Reject,
    // Label 78: @326583
    GIM_SwitchType, /*MI*/0, /*Op*/0, /*[*/GIMT_Encode2(8), GIMT_Encode2(12), /*)*//*default:*//*Label 4757*/ GIMT_Encode4(346393),
    /*GILLT_s16*//*Label 4753*/ GIMT_Encode4(326610),
    /*GILLT_s32*//*Label 4754*/ GIMT_Encode4(327504),
    /*GILLT_s64*//*Label 4755*/ GIMT_Encode4(346032),
    /*GILLT_v2s16*//*Label 4756*/ GIMT_Encode4(346312),
    // Label 4753: @326610
    GIM_Try, /*On fail goto*//*Label 4758*/ GIMT_Encode4(327503),
      GIM_CheckType, /*MI*/0, /*Op*/1, /*Type*/GILLT_s16,
      GIM_CheckType, /*MI*/0, /*Op*/2, /*Type*/GILLT_s16,
      GIM_Try, /*On fail goto*//*Label 4759*/ GIMT_Encode4(326728), // Rule ID 10527 //
        GIM_CheckFeatures, GIMT_Encode2(GIFBS_isGFX11Plus),
        GIM_CheckRegBankForClass, /*MI*/0, /*Op*/0, /*RC*/GIMT_Encode2(AMDGPU::VGPR_32RegClassID),
        GIM_RecordInsn, /*DefineMI*/1, /*MI*/0, /*OpIdx*/2, // MIs[1]
        GIM_CheckOpcode, /*MI*/1, GIMT_Encode2(TargetOpcode::G_FMAXNUM),
        GIM_CheckType, /*MI*/1, /*Op*/1, /*Type*/GILLT_s16,
        GIM_CheckType, /*MI*/1, /*Op*/2, /*Type*/GILLT_s16,
        GIM_CheckCxxInsnPredicate, /*MI*/1, /*FnId*/GIMT_Encode2(GICXXPred_MI_Predicate_fmaxnum_oneuse),
        GIM_CheckIsSafeToFold, /*InsnID*/1,
        GIM_CheckComplexPattern, /*MI*/0, /*Op*/1, /*Renderer*/GIMT_Encode2(0), GIMT_Encode2(GICP_gi_vop3mods),
        GIM_CheckComplexPattern, /*MI*/1, /*Op*/1, /*Renderer*/GIMT_Encode2(1), GIMT_Encode2(GICP_gi_vop3mods),
        GIM_CheckComplexPattern, /*MI*/1, /*Op*/2, /*Renderer*/GIMT_Encode2(2), GIMT_Encode2(GICP_gi_vop3mods),
        // (fminnum_ieee:{ *:[f16] } (VOP3Mods:{ *:[f16] } f16:{ *:[f16] }:$src2, i32:{ *:[i32] }:$src2_mods), (fmaxnum:{ *:[f16] } (VOP3Mods:{ *:[f16] } f16:{ *:[f16] }:$src0, i32:{ *:[i32] }:$src0_mods), (VOP3Mods:{ *:[f16] } f16:{ *:[f16] }:$src1, i32:{ *:[i32] }:$src1_mods))<<P:Predicate_fmaxnum_oneuse>>)  =>  (V_MAXMIN_F16_e64:{ *:[f16] } ?:{ *:[i32] }:$src0_mods, ?:{ *:[f16] }:$src0, ?:{ *:[i32] }:$src1_mods, ?:{ *:[f16] }:$src1, ?:{ *:[i32] }:$src2_mods, ?:{ *:[f16] }:$src2, 0:{ *:[i1] }, 0:{ *:[i32] })
        GIR_BuildMI, /*InsnID*/0, /*Opcode*/GIMT_Encode2(AMDGPU::V_MAXMIN_F16_e64),
        GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/0, // DstI[vdst]
        GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(1), /*SubOperand*/1, // src0_mods
        GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(1), /*SubOperand*/0, // src0
        GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(2), /*SubOperand*/1, // src1_mods
        GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(2), /*SubOperand*/0, // src1
        GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/1, // src2_mods
        GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/0, // src2
        GIR_AddImm8, /*InsnID*/0, /*Imm*/0,
        GIR_AddImm8, /*InsnID*/0, /*Imm*/0,
        GIR_ConstrainSelectedInstOperands, /*InsnID*/0,
        GIR_EraseFromParent, /*InsnID*/0,
        // GIR_Coverage, 10527,
        GIR_Done,
      // Label 4759: @326728
      GIM_Try, /*On fail goto*//*Label 4760*/ GIMT_Encode4(326833), // Rule ID 10526 //
        GIM_CheckFeatures, GIMT_Encode2(GIFBS_isGFX11Plus),
        GIM_CheckRegBankForClass, /*MI*/0, /*Op*/0, /*RC*/GIMT_Encode2(AMDGPU::VGPR_32RegClassID),
        GIM_RecordInsn, /*DefineMI*/1, /*MI*/0, /*OpIdx*/2, // MIs[1]
        GIM_CheckOpcode, /*MI*/1, GIMT_Encode2(TargetOpcode::G_FMAXNUM_IEEE),
        GIM_CheckType, /*MI*/1, /*Op*/1, /*Type*/GILLT_s16,
        GIM_CheckType, /*MI*/1, /*Op*/2, /*Type*/GILLT_s16,
        GIM_CheckCxxInsnPredicate, /*MI*/1, /*FnId*/GIMT_Encode2(GICXXPred_MI_Predicate_fmaxnum_ieee_oneuse),
        GIM_CheckIsSafeToFold, /*InsnID*/1,
        GIM_CheckComplexPattern, /*MI*/0, /*Op*/1, /*Renderer*/GIMT_Encode2(0), GIMT_Encode2(GICP_gi_vop3mods),
        GIM_CheckComplexPattern, /*MI*/1, /*Op*/1, /*Renderer*/GIMT_Encode2(1), GIMT_Encode2(GICP_gi_vop3mods),
        GIM_CheckComplexPattern, /*MI*/1, /*Op*/2, /*Renderer*/GIMT_Encode2(2), GIMT_Encode2(GICP_gi_vop3mods),
        // (fminnum_ieee:{ *:[f16] } (VOP3Mods:{ *:[f16] } f16:{ *:[f16] }:$src2, i32:{ *:[i32] }:$src2_mods), (fmaxnum_ieee:{ *:[f16] } (VOP3Mods:{ *:[f16] } f16:{ *:[f16] }:$src0, i32:{ *:[i32] }:$src0_mods), (VOP3Mods:{ *:[f16] } f16:{ *:[f16] }:$src1, i32:{ *:[i32] }:$src1_mods))<<P:Predicate_fmaxnum_ieee_oneuse>>)  =>  (V_MAXMIN_F16_e64:{ *:[f16] } ?:{ *:[i32] }:$src0_mods, ?:{ *:[f16] }:$src0, ?:{ *:[i32] }:$src1_mods, ?:{ *:[f16] }:$src1, ?:{ *:[i32] }:$src2_mods, ?:{ *:[f16] }:$src2, 0:{ *:[i1] }, 0:{ *:[i32] })
        GIR_BuildMI, /*InsnID*/0, /*Opcode*/GIMT_Encode2(AMDGPU::V_MAXMIN_F16_e64),
        GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/0, // DstI[vdst]
        GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(1), /*SubOperand*/1, // src0_mods
        GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(1), /*SubOperand*/0, // src0
        GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(2), /*SubOperand*/1, // src1_mods
        GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(2), /*SubOperand*/0, // src1
        GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/1, // src2_mods
        GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/0, // src2
        GIR_AddImm8, /*InsnID*/0, /*Imm*/0,
        GIR_AddImm8, /*InsnID*/0, /*Imm*/0,
        GIR_ConstrainSelectedInstOperands, /*InsnID*/0,
        GIR_EraseFromParent, /*InsnID*/0,
        // GIR_Coverage, 10526,
        GIR_Done,
      // Label 4760: @326833
      GIM_Try, /*On fail goto*//*Label 4761*/ GIMT_Encode4(326938), // Rule ID 6533 //
        GIM_CheckFeatures, GIMT_Encode2(GIFBS_isGFX11Plus),
        GIM_CheckRegBankForClass, /*MI*/0, /*Op*/0, /*RC*/GIMT_Encode2(AMDGPU::VGPR_32RegClassID),
        GIM_RecordInsn, /*DefineMI*/1, /*MI*/0, /*OpIdx*/1, // MIs[1]
        GIM_CheckOpcode, /*MI*/1, GIMT_Encode2(TargetOpcode::G_FMAXNUM),
        GIM_CheckType, /*MI*/1, /*Op*/1, /*Type*/GILLT_s16,
        GIM_CheckType, /*MI*/1, /*Op*/2, /*Type*/GILLT_s16,
        GIM_CheckCxxInsnPredicate, /*MI*/1, /*FnId*/GIMT_Encode2(GICXXPred_MI_Predicate_fmaxnum_oneuse),
        GIM_CheckIsSafeToFold, /*InsnID*/1,
        GIM_CheckComplexPattern, /*MI*/0, /*Op*/2, /*Renderer*/GIMT_Encode2(2), GIMT_Encode2(GICP_gi_vop3mods),
        GIM_CheckComplexPattern, /*MI*/1, /*Op*/1, /*Renderer*/GIMT_Encode2(0), GIMT_Encode2(GICP_gi_vop3mods),
        GIM_CheckComplexPattern, /*MI*/1, /*Op*/2, /*Renderer*/GIMT_Encode2(1), GIMT_Encode2(GICP_gi_vop3mods),
        // (fminnum_ieee:{ *:[f16] } (fmaxnum:{ *:[f16] } (VOP3Mods:{ *:[f16] } f16:{ *:[f16] }:$src0, i32:{ *:[i32] }:$src0_mods), (VOP3Mods:{ *:[f16] } f16:{ *:[f16] }:$src1, i32:{ *:[i32] }:$src1_mods))<<P:Predicate_fmaxnum_oneuse>>, (VOP3Mods:{ *:[f16] } f16:{ *:[f16] }:$src2, i32:{ *:[i32] }:$src2_mods))  =>  (V_MAXMIN_F16_e64:{ *:[f16] } ?:{ *:[i32] }:$src0_mods, ?:{ *:[f16] }:$src0, ?:{ *:[i32] }:$src1_mods, ?:{ *:[f16] }:$src1, ?:{ *:[i32] }:$src2_mods, ?:{ *:[f16] }:$src2, 0:{ *:[i1] }, 0:{ *:[i32] })
        GIR_BuildMI, /*InsnID*/0, /*Opcode*/GIMT_Encode2(AMDGPU::V_MAXMIN_F16_e64),
        GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/0, // DstI[vdst]
        GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/1, // src0_mods
        GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/0, // src0
        GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(1), /*SubOperand*/1, // src1_mods
        GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(1), /*SubOperand*/0, // src1
        GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(2), /*SubOperand*/1, // src2_mods
        GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(2), /*SubOperand*/0, // src2
        GIR_AddImm8, /*InsnID*/0, /*Imm*/0,
        GIR_AddImm8, /*InsnID*/0, /*Imm*/0,
        GIR_ConstrainSelectedInstOperands, /*InsnID*/0,
        GIR_EraseFromParent, /*InsnID*/0,
        // GIR_Coverage, 6533,
        GIR_Done,
      // Label 4761: @326938
      GIM_Try, /*On fail goto*//*Label 4762*/ GIMT_Encode4(327043), // Rule ID 6532 //
        GIM_CheckFeatures, GIMT_Encode2(GIFBS_isGFX11Plus),
        GIM_CheckRegBankForClass, /*MI*/0, /*Op*/0, /*RC*/GIMT_Encode2(AMDGPU::VGPR_32RegClassID),
        GIM_RecordInsn, /*DefineMI*/1, /*MI*/0, /*OpIdx*/1, // MIs[1]
        GIM_CheckOpcode, /*MI*/1, GIMT_Encode2(TargetOpcode::G_FMAXNUM_IEEE),
        GIM_CheckType, /*MI*/1, /*Op*/1, /*Type*/GILLT_s16,
        GIM_CheckType, /*MI*/1, /*Op*/2, /*Type*/GILLT_s16,
        GIM_CheckCxxInsnPredicate, /*MI*/1, /*FnId*/GIMT_Encode2(GICXXPred_MI_Predicate_fmaxnum_ieee_oneuse),
        GIM_CheckIsSafeToFold, /*InsnID*/1,
        GIM_CheckComplexPattern, /*MI*/0, /*Op*/2, /*Renderer*/GIMT_Encode2(2), GIMT_Encode2(GICP_gi_vop3mods),
        GIM_CheckComplexPattern, /*MI*/1, /*Op*/1, /*Renderer*/GIMT_Encode2(0), GIMT_Encode2(GICP_gi_vop3mods),
        GIM_CheckComplexPattern, /*MI*/1, /*Op*/2, /*Renderer*/GIMT_Encode2(1), GIMT_Encode2(GICP_gi_vop3mods),
        // (fminnum_ieee:{ *:[f16] } (fmaxnum_ieee:{ *:[f16] } (VOP3Mods:{ *:[f16] } f16:{ *:[f16] }:$src0, i32:{ *:[i32] }:$src0_mods), (VOP3Mods:{ *:[f16] } f16:{ *:[f16] }:$src1, i32:{ *:[i32] }:$src1_mods))<<P:Predicate_fmaxnum_ieee_oneuse>>, (VOP3Mods:{ *:[f16] } f16:{ *:[f16] }:$src2, i32:{ *:[i32] }:$src2_mods))  =>  (V_MAXMIN_F16_e64:{ *:[f16] } ?:{ *:[i32] }:$src0_mods, ?:{ *:[f16] }:$src0, ?:{ *:[i32] }:$src1_mods, ?:{ *:[f16] }:$src1, ?:{ *:[i32] }:$src2_mods, ?:{ *:[f16] }:$src2, 0:{ *:[i1] }, 0:{ *:[i32] })
        GIR_BuildMI, /*InsnID*/0, /*Opcode*/GIMT_Encode2(AMDGPU::V_MAXMIN_F16_e64),
        GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/0, // DstI[vdst]
        GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/1, // src0_mods
        GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/0, // src0
        GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(1), /*SubOperand*/1, // src1_mods
        GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(1), /*SubOperand*/0, // src1
        GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(2), /*SubOperand*/1, // src2_mods
        GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(2), /*SubOperand*/0, // src2
        GIR_AddImm8, /*InsnID*/0, /*Imm*/0,
        GIR_AddImm8, /*InsnID*/0, /*Imm*/0,
        GIR_ConstrainSelectedInstOperands, /*InsnID*/0,
        GIR_EraseFromParent, /*InsnID*/0,
        // GIR_Coverage, 6532,
        GIR_Done,
      // Label 4762: @327043
      GIM_Try, /*On fail goto*//*Label 4763*/ GIMT_Encode4(327082), // Rule ID 102 //
        GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasSALUFloatInsts),
        GIM_CheckRegBankForClass, /*MI*/0, /*Op*/0, /*RC*/GIMT_Encode2(AMDGPU::SReg_32RegClassID),
        GIM_CheckRegBankForClass, /*MI*/0, /*Op*/1, /*RC*/GIMT_Encode2(AMDGPU::SReg_32RegClassID),
        GIM_CheckRegBankForClass, /*MI*/0, /*Op*/2, /*RC*/GIMT_Encode2(AMDGPU::SReg_32RegClassID),
        GIM_CheckCxxInsnPredicate, /*MI*/0, /*FnId*/GIMT_Encode2(GICXXPred_MI_Predicate_anonymous_17631),
        // (fminnum_ieee:{ *:[f16] } SSrc_f16:{ *:[f16] }:$src0, SSrc_f16:{ *:[f16] }:$src1)<<P:Predicate_anonymous_17631>>  =>  (S_MIN_F16:{ *:[f16] } SSrc_f16:{ *:[f16] }:$src0, SSrc_f16:{ *:[f16] }:$src1)
        GIR_MutateOpcode, /*InsnID*/0, /*RecycleInsnID*/0, /*Opcode*/GIMT_Encode2(AMDGPU::S_MIN_F16),
        GIR_AddImplicitUse, /*InsnID*/0, GIMT_Encode2(AMDGPU::MODE),
        GIR_ConstrainSelectedInstOperands, /*InsnID*/0,
        // GIR_Coverage, 102,
        GIR_Done,
      // Label 4763: @327082
      GIM_Try, /*On fail goto*//*Label 4764*/ GIMT_Encode4(327152), // Rule ID 819 //
        GIM_CheckFeatures, GIMT_Encode2(GIFBS_Has16BitInsts_NotHasTrue16BitInsts),
        GIM_CheckRegBankForClass, /*MI*/0, /*Op*/0, /*RC*/GIMT_Encode2(AMDGPU::VGPR_32RegClassID),
        GIM_CheckComplexPattern, /*MI*/0, /*Op*/1, /*Renderer*/GIMT_Encode2(0), GIMT_Encode2(GICP_gi_vop3mods0),
        GIM_CheckComplexPattern, /*MI*/0, /*Op*/2, /*Renderer*/GIMT_Encode2(1), GIMT_Encode2(GICP_gi_vop3mods),
        // (fminnum_ieee:{ *:[f16] } (VOP3Mods0:{ *:[f16] } f16:{ *:[f16] }:$src0, i32:{ *:[i32] }:$src0_modifiers, i1:{ *:[i1] }:$clamp, i32:{ *:[i32] }:$omod), (VOP3Mods:{ *:[f16] } f16:{ *:[f16] }:$src1, i32:{ *:[i32] }:$src1_modifiers))  =>  (V_MIN_F16_e64:{ *:[f16] } i32:{ *:[i32] }:$src0_modifiers, f16:{ *:[f16] }:$src0, i32:{ *:[i32] }:$src1_modifiers, f16:{ *:[f16] }:$src1, i1:{ *:[i1] }:$clamp, i32:{ *:[i32] }:$omod)
        GIR_BuildMI, /*InsnID*/0, /*Opcode*/GIMT_Encode2(AMDGPU::V_MIN_F16_e64),
        GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/0, // DstI[vdst]
        GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/1, // src0_modifiers
        GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/0, // src0
        GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(1), /*SubOperand*/1, // src1_modifiers
        GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(1), /*SubOperand*/0, // src1
        GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/2, // clamp
        GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/3, // omod
        GIR_ConstrainSelectedInstOperands, /*InsnID*/0,
        GIR_EraseFromParent, /*InsnID*/0,
        // GIR_Coverage, 819,
        GIR_Done,
      // Label 4764: @327152
      GIM_Try, /*On fail goto*//*Label 4765*/ GIMT_Encode4(327222), // Rule ID 821 //
        GIM_CheckFeatures, GIMT_Encode2(GIFBS_UseRealTrue16Insts),
        GIM_CheckRegBankForClass, /*MI*/0, /*Op*/0, /*RC*/GIMT_Encode2(AMDGPU::VGPR_16RegClassID),
        GIM_CheckComplexPattern, /*MI*/0, /*Op*/1, /*Renderer*/GIMT_Encode2(0), GIMT_Encode2(GICP_gi_vop3mods0),
        GIM_CheckComplexPattern, /*MI*/0, /*Op*/2, /*Renderer*/GIMT_Encode2(1), GIMT_Encode2(GICP_gi_vop3mods),
        // (fminnum_ieee:{ *:[f16] } (VOP3Mods0:{ *:[f16] } f16:{ *:[f16] }:$src0, i32:{ *:[i32] }:$src0_modifiers, i1:{ *:[i1] }:$clamp, i32:{ *:[i32] }:$omod), (VOP3Mods:{ *:[f16] } f16:{ *:[f16] }:$src1, i32:{ *:[i32] }:$src1_modifiers))  =>  (V_MIN_F16_t16_e64:{ *:[f16] } i32:{ *:[i32] }:$src0_modifiers, f16:{ *:[f16] }:$src0, i32:{ *:[i32] }:$src1_modifiers, f16:{ *:[f16] }:$src1, i1:{ *:[i1] }:$clamp, i32:{ *:[i32] }:$omod)
        GIR_BuildMI, /*InsnID*/0, /*Opcode*/GIMT_Encode2(AMDGPU::V_MIN_F16_t16_e64),
        GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/0, // DstI[vdst]
        GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/1, // src0_modifiers
        GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/0, // src0
        GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(1), /*SubOperand*/1, // src1_modifiers
        GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(1), /*SubOperand*/0, // src1
        GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/2, // clamp
        GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/3, // omod
        GIR_ConstrainSelectedInstOperands, /*InsnID*/0,
        GIR_EraseFromParent, /*InsnID*/0,
        // GIR_Coverage, 821,
        GIR_Done,
      // Label 4765: @327222
      GIM_Try, /*On fail goto*//*Label 4766*/ GIMT_Encode4(327292), // Rule ID 823 //
        GIM_CheckFeatures, GIMT_Encode2(GIFBS_UseFakeTrue16Insts),
        GIM_CheckRegBankForClass, /*MI*/0, /*Op*/0, /*RC*/GIMT_Encode2(AMDGPU::VGPR_32RegClassID),
        GIM_CheckComplexPattern, /*MI*/0, /*Op*/1, /*Renderer*/GIMT_Encode2(0), GIMT_Encode2(GICP_gi_vop3mods0),
        GIM_CheckComplexPattern, /*MI*/0, /*Op*/2, /*Renderer*/GIMT_Encode2(1), GIMT_Encode2(GICP_gi_vop3mods),
        // (fminnum_ieee:{ *:[f16] } (VOP3Mods0:{ *:[f16] } f16:{ *:[f16] }:$src0, i32:{ *:[i32] }:$src0_modifiers, i1:{ *:[i1] }:$clamp, i32:{ *:[i32] }:$omod), (VOP3Mods:{ *:[f16] } f16:{ *:[f16] }:$src1, i32:{ *:[i32] }:$src1_modifiers))  =>  (V_MIN_F16_fake16_e64:{ *:[f16] } i32:{ *:[i32] }:$src0_modifiers, f16:{ *:[f16] }:$src0, i32:{ *:[i32] }:$src1_modifiers, f16:{ *:[f16] }:$src1, i1:{ *:[i1] }:$clamp, i32:{ *:[i32] }:$omod)
        GIR_BuildMI, /*InsnID*/0, /*Opcode*/GIMT_Encode2(AMDGPU::V_MIN_F16_fake16_e64),
        GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/0, // DstI[vdst]
        GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/1, // src0_modifiers
        GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/0, // src0
        GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(1), /*SubOperand*/1, // src1_modifiers
        GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(1), /*SubOperand*/0, // src1
        GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/2, // clamp
        GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/3, // omod
        GIR_ConstrainSelectedInstOperands, /*InsnID*/0,
        GIR_EraseFromParent, /*InsnID*/0,
        // GIR_Coverage, 823,
        GIR_Done,
      // Label 4766: @327292
      GIM_Try, /*On fail goto*//*Label 4767*/ GIMT_Encode4(327362), // Rule ID 7154 //
        GIM_CheckFeatures, GIMT_Encode2(GIFBS_Has16BitInsts_NotHasTrue16BitInsts),
        GIM_CheckRegBankForClass, /*MI*/0, /*Op*/0, /*RC*/GIMT_Encode2(AMDGPU::VGPR_32RegClassID),
        GIM_CheckComplexPattern, /*MI*/0, /*Op*/1, /*Renderer*/GIMT_Encode2(0), GIMT_Encode2(GICP_gi_vop3mods),
        GIM_CheckComplexPattern, /*MI*/0, /*Op*/2, /*Renderer*/GIMT_Encode2(1), GIMT_Encode2(GICP_gi_vop3mods0),
        // (fminnum_ieee:{ *:[f16] } (VOP3Mods:{ *:[f16] } f16:{ *:[f16] }:$src1, i32:{ *:[i32] }:$src1_modifiers), (VOP3Mods0:{ *:[f16] } f16:{ *:[f16] }:$src0, i32:{ *:[i32] }:$src0_modifiers, i1:{ *:[i1] }:$clamp, i32:{ *:[i32] }:$omod))  =>  (V_MIN_F16_e64:{ *:[f16] } i32:{ *:[i32] }:$src0_modifiers, f16:{ *:[f16] }:$src0, i32:{ *:[i32] }:$src1_modifiers, f16:{ *:[f16] }:$src1, i1:{ *:[i1] }:$clamp, i32:{ *:[i32] }:$omod)
        GIR_BuildMI, /*InsnID*/0, /*Opcode*/GIMT_Encode2(AMDGPU::V_MIN_F16_e64),
        GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/0, // DstI[vdst]
        GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(1), /*SubOperand*/1, // src0_modifiers
        GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(1), /*SubOperand*/0, // src0
        GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/1, // src1_modifiers
        GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/0, // src1
        GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(1), /*SubOperand*/2, // clamp
        GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(1), /*SubOperand*/3, // omod
        GIR_ConstrainSelectedInstOperands, /*InsnID*/0,
        GIR_EraseFromParent, /*InsnID*/0,
        // GIR_Coverage, 7154,
        GIR_Done,
      // Label 4767: @327362
      GIM_Try, /*On fail goto*//*Label 4768*/ GIMT_Encode4(327432), // Rule ID 7156 //
        GIM_CheckFeatures, GIMT_Encode2(GIFBS_UseRealTrue16Insts),
        GIM_CheckRegBankForClass, /*MI*/0, /*Op*/0, /*RC*/GIMT_Encode2(AMDGPU::VGPR_16RegClassID),
        GIM_CheckComplexPattern, /*MI*/0, /*Op*/1, /*Renderer*/GIMT_Encode2(0), GIMT_Encode2(GICP_gi_vop3mods),
        GIM_CheckComplexPattern, /*MI*/0, /*Op*/2, /*Renderer*/GIMT_Encode2(1), GIMT_Encode2(GICP_gi_vop3mods0),
        // (fminnum_ieee:{ *:[f16] } (VOP3Mods:{ *:[f16] } f16:{ *:[f16] }:$src1, i32:{ *:[i32] }:$src1_modifiers), (VOP3Mods0:{ *:[f16] } f16:{ *:[f16] }:$src0, i32:{ *:[i32] }:$src0_modifiers, i1:{ *:[i1] }:$clamp, i32:{ *:[i32] }:$omod))  =>  (V_MIN_F16_t16_e64:{ *:[f16] } i32:{ *:[i32] }:$src0_modifiers, f16:{ *:[f16] }:$src0, i32:{ *:[i32] }:$src1_modifiers, f16:{ *:[f16] }:$src1, i1:{ *:[i1] }:$clamp, i32:{ *:[i32] }:$omod)
        GIR_BuildMI, /*InsnID*/0, /*Opcode*/GIMT_Encode2(AMDGPU::V_MIN_F16_t16_e64),
        GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/0, // DstI[vdst]
        GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(1), /*SubOperand*/1, // src0_modifiers
        GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(1), /*SubOperand*/0, // src0
        GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/1, // src1_modifiers
        GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/0, // src1
        GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(1), /*SubOperand*/2, // clamp
        GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(1), /*SubOperand*/3, // omod
        GIR_ConstrainSelectedInstOperands, /*InsnID*/0,
        GIR_EraseFromParent, /*InsnID*/0,
        // GIR_Coverage, 7156,
        GIR_Done,
      // Label 4768: @327432
      GIM_Try, /*On fail goto*//*Label 4769*/ GIMT_Encode4(327502), // Rule ID 7158 //
        GIM_CheckFeatures, GIMT_Encode2(GIFBS_UseFakeTrue16Insts),
        GIM_CheckRegBankForClass, /*MI*/0, /*Op*/0, /*RC*/GIMT_Encode2(AMDGPU::VGPR_32RegClassID),
        GIM_CheckComplexPattern, /*MI*/0, /*Op*/1, /*Renderer*/GIMT_Encode2(0), GIMT_Encode2(GICP_gi_vop3mods),
        GIM_CheckComplexPattern, /*MI*/0, /*Op*/2, /*Renderer*/GIMT_Encode2(1), GIMT_Encode2(GICP_gi_vop3mods0),
        // (fminnum_ieee:{ *:[f16] } (VOP3Mods:{ *:[f16] } f16:{ *:[f16] }:$src1, i32:{ *:[i32] }:$src1_modifiers), (VOP3Mods0:{ *:[f16] } f16:{ *:[f16] }:$src0, i32:{ *:[i32] }:$src0_modifiers, i1:{ *:[i1] }:$clamp, i32:{ *:[i32] }:$omod))  =>  (V_MIN_F16_fake16_e64:{ *:[f16] } i32:{ *:[i32] }:$src0_modifiers, f16:{ *:[f16] }:$src0, i32:{ *:[i32] }:$src1_modifiers, f16:{ *:[f16] }:$src1, i1:{ *:[i1] }:$clamp, i32:{ *:[i32] }:$omod)
        GIR_BuildMI, /*InsnID*/0, /*Opcode*/GIMT_Encode2(AMDGPU::V_MIN_F16_fake16_e64),
        GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/0, // DstI[vdst]
        GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(1), /*SubOperand*/1, // src0_modifiers
        GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(1), /*SubOperand*/0, // src0
        GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/1, // src1_modifiers
        GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/0, // src1
        GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(1), /*SubOperand*/2, // clamp
        GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(1), /*SubOperand*/3, // omod
        GIR_ConstrainSelectedInstOperands, /*InsnID*/0,
        GIR_EraseFromParent, /*InsnID*/0,
        // GIR_Coverage, 7158,
        GIR_Done,
      // Label 4769: @327502
      GIM_Reject,
    // Label 4758: @327503
    GIM_Reject,
    // Label 4754: @327504
    GIM_Try, /*On fail goto*//*Label 4770*/ GIMT_Encode4(346031),
      GIM_CheckType, /*MI*/0, /*Op*/1, /*Type*/GILLT_s32,
      GIM_CheckType, /*MI*/0, /*Op*/2, /*Type*/GILLT_s32,
      GIM_Try, /*On fail goto*//*Label 4771*/ GIMT_Encode4(327657), // Rule ID 10346 //
        GIM_CheckRegBankForClass, /*MI*/0, /*Op*/0, /*RC*/GIMT_Encode2(AMDGPU::VGPR_32RegClassID),
        GIM_RecordInsn, /*DefineMI*/1, /*MI*/0, /*OpIdx*/1, // MIs[1]
        GIM_CheckOpcode, /*MI*/1, GIMT_Encode2(TargetOpcode::G_FMAXNUM),
        GIM_CheckType, /*MI*/1, /*Op*/1, /*Type*/GILLT_s32,
        GIM_CheckType, /*MI*/1, /*Op*/2, /*Type*/GILLT_s32,
        GIM_RecordInsn, /*DefineMI*/2, /*MI*/0, /*OpIdx*/2, // MIs[2]
        GIM_CheckOpcode, /*MI*/2, GIMT_Encode2(TargetOpcode::G_FMAXNUM),
        GIM_CheckType, /*MI*/2, /*Op*/1, /*Type*/GILLT_s32,
        GIM_CheckType, /*MI*/2, /*Op*/2, /*Type*/GILLT_s32,
        GIM_RecordInsn, /*DefineMI*/3, /*MI*/2, /*OpIdx*/2, // MIs[3]
        GIM_CheckOpcode, /*MI*/3, GIMT_Encode2(TargetOpcode::G_FMINNUM),
        // MIs[3] VOP3Mods:src0:src0_mods
        GIM_CheckIsSameOperand, /*MI*/3, /*OpIdx*/1, /*OtherMI*/1, /*OtherOpIdx*/1,
        // MIs[3] VOP3Mods:src1:src1_mods
        GIM_CheckIsSameOperand, /*MI*/3, /*OpIdx*/2, /*OtherMI*/1, /*OtherOpIdx*/2,
        GIM_CheckCxxInsnPredicate, /*MI*/0, /*FnId*/GIMT_Encode2(GICXXPred_MI_Predicate_fminnum_like_nnan),
        GIM_CheckIsSafeToFold, /*InsnID*/1,
        GIM_CheckIsSafeToFold, /*InsnID*/2,
        GIM_CheckIsSafeToFold, /*InsnID*/3,
        GIM_CheckComplexPattern, /*MI*/1, /*Op*/1, /*Renderer*/GIMT_Encode2(0), GIMT_Encode2(GICP_gi_vop3mods),
        GIM_CheckComplexPattern, /*MI*/1, /*Op*/2, /*Renderer*/GIMT_Encode2(1), GIMT_Encode2(GICP_gi_vop3mods),
        GIM_CheckComplexPattern, /*MI*/2, /*Op*/1, /*Renderer*/GIMT_Encode2(2), GIMT_Encode2(GICP_gi_vop3mods),
        // (fminnum_ieee:{ *:[f32] } (fmaxnum:{ *:[f32] } (VOP3Mods:{ *:[f32] } f32:{ *:[f32] }:$src0, i32:{ *:[i32] }:$src0_mods), (VOP3Mods:{ *:[f32] } f32:{ *:[f32] }:$src1, i32:{ *:[i32] }:$src1_mods)), (fmaxnum:{ *:[f32] } (VOP3Mods:{ *:[f32] } f32:{ *:[f32] }:$src2, i32:{ *:[i32] }:$src2_mods), (fminnum:{ *:[f32] } (VOP3Mods:{ *:[f32] } f32:{ *:[f32] }:$src0, i32:{ *:[i32] }:$src0_mods), (VOP3Mods:{ *:[f32] } f32:{ *:[f32] }:$src1, i32:{ *:[i32] }:$src1_mods))))<<P:Predicate_fminnum_like_nnan>>  =>  (V_MED3_F32_e64:{ *:[f32] } ?:{ *:[i32] }:$src0_mods, ?:{ *:[f32] }:$src0, ?:{ *:[i32] }:$src1_mods, ?:{ *:[f32] }:$src1, ?:{ *:[i32] }:$src2_mods, ?:{ *:[f32] }:$src2, 0:{ *:[i1] }, 0:{ *:[i32] })
        GIR_BuildMI, /*InsnID*/0, /*Opcode*/GIMT_Encode2(AMDGPU::V_MED3_F32_e64),
        GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/0, // DstI[vdst]
        GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/1, // src0_mods
        GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/0, // src0
        GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(1), /*SubOperand*/1, // src1_mods
        GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(1), /*SubOperand*/0, // src1
        GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(2), /*SubOperand*/1, // src2_mods
        GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(2), /*SubOperand*/0, // src2
        GIR_AddImm8, /*InsnID*/0, /*Imm*/0,
        GIR_AddImm8, /*InsnID*/0, /*Imm*/0,
        GIR_ConstrainSelectedInstOperands, /*InsnID*/0,
        GIR_EraseFromParent, /*InsnID*/0,
        // GIR_Coverage, 10346,
        GIR_Done,
      // Label 4771: @327657
      GIM_Try, /*On fail goto*//*Label 4772*/ GIMT_Encode4(327797), // Rule ID 10347 //
        GIM_CheckRegBankForClass, /*MI*/0, /*Op*/0, /*RC*/GIMT_Encode2(AMDGPU::VGPR_32RegClassID),
        GIM_RecordInsn, /*DefineMI*/1, /*MI*/0, /*OpIdx*/1, // MIs[1]
        GIM_CheckOpcode, /*MI*/1, GIMT_Encode2(TargetOpcode::G_FMAXNUM),
        GIM_CheckType, /*MI*/1, /*Op*/1, /*Type*/GILLT_s32,
        GIM_CheckType, /*MI*/1, /*Op*/2, /*Type*/GILLT_s32,
        GIM_RecordInsn, /*DefineMI*/2, /*MI*/0, /*OpIdx*/2, // MIs[2]
        GIM_CheckOpcode, /*MI*/2, GIMT_Encode2(TargetOpcode::G_FMAXNUM),
        GIM_CheckType, /*MI*/2, /*Op*/1, /*Type*/GILLT_s32,
        GIM_CheckType, /*MI*/2, /*Op*/2, /*Type*/GILLT_s32,
        GIM_RecordInsn, /*DefineMI*/3, /*MI*/2, /*OpIdx*/2, // MIs[3]
        GIM_CheckOpcode, /*MI*/3, GIMT_Encode2(TargetOpcode::G_FMINNUM),
        // MIs[3] VOP3Mods:src1:src1_mods
        GIM_CheckIsSameOperand, /*MI*/3, /*OpIdx*/1, /*OtherMI*/1, /*OtherOpIdx*/2,
        // MIs[3] VOP3Mods:src0:src0_mods
        GIM_CheckIsSameOperand, /*MI*/3, /*OpIdx*/2, /*OtherMI*/1, /*OtherOpIdx*/1,
        GIM_CheckCxxInsnPredicate, /*MI*/0, /*FnId*/GIMT_Encode2(GICXXPred_MI_Predicate_fminnum_like_nnan),
        GIM_CheckIsSafeToFold, /*InsnID*/1,
        GIM_CheckIsSafeToFold, /*InsnID*/2,
        GIM_CheckIsSafeToFold, /*InsnID*/3,
        GIM_CheckComplexPattern, /*MI*/1, /*Op*/1, /*Renderer*/GIMT_Encode2(0), GIMT_Encode2(GICP_gi_vop3mods),
        GIM_CheckComplexPattern, /*MI*/1, /*Op*/2, /*Renderer*/GIMT_Encode2(1), GIMT_Encode2(GICP_gi_vop3mods),
        GIM_CheckComplexPattern, /*MI*/2, /*Op*/1, /*Renderer*/GIMT_Encode2(2), GIMT_Encode2(GICP_gi_vop3mods),
        // (fminnum_ieee:{ *:[f32] } (fmaxnum:{ *:[f32] } (VOP3Mods:{ *:[f32] } f32:{ *:[f32] }:$src0, i32:{ *:[i32] }:$src0_mods), (VOP3Mods:{ *:[f32] } f32:{ *:[f32] }:$src1, i32:{ *:[i32] }:$src1_mods)), (fmaxnum:{ *:[f32] } (VOP3Mods:{ *:[f32] } f32:{ *:[f32] }:$src2, i32:{ *:[i32] }:$src2_mods), (fminnum:{ *:[f32] } (VOP3Mods:{ *:[f32] } f32:{ *:[f32] }:$src1, i32:{ *:[i32] }:$src1_mods), (VOP3Mods:{ *:[f32] } f32:{ *:[f32] }:$src0, i32:{ *:[i32] }:$src0_mods))))<<P:Predicate_fminnum_like_nnan>>  =>  (V_MED3_F32_e64:{ *:[f32] } ?:{ *:[i32] }:$src0_mods, ?:{ *:[f32] }:$src0, ?:{ *:[i32] }:$src1_mods, ?:{ *:[f32] }:$src1, ?:{ *:[i32] }:$src2_mods, ?:{ *:[f32] }:$src2, 0:{ *:[i1] }, 0:{ *:[i32] })
        GIR_BuildMI, /*InsnID*/0, /*Opcode*/GIMT_Encode2(AMDGPU::V_MED3_F32_e64),
        GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/0, // DstI[vdst]
        GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/1, // src0_mods
        GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/0, // src0
        GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(1), /*SubOperand*/1, // src1_mods
        GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(1), /*SubOperand*/0, // src1
        GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(2), /*SubOperand*/1, // src2_mods
        GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(2), /*SubOperand*/0, // src2
        GIR_AddImm8, /*InsnID*/0, /*Imm*/0,
        GIR_AddImm8, /*InsnID*/0, /*Imm*/0,
        GIR_ConstrainSelectedInstOperands, /*InsnID*/0,
        GIR_EraseFromParent, /*InsnID*/0,
        // GIR_Coverage, 10347,
        GIR_Done,
      // Label 4772: @327797
      GIM_Try, /*On fail goto*//*Label 4773*/ GIMT_Encode4(327937), // Rule ID 10350 //
        GIM_CheckRegBankForClass, /*MI*/0, /*Op*/0, /*RC*/GIMT_Encode2(AMDGPU::VGPR_32RegClassID),
        GIM_RecordInsn, /*DefineMI*/1, /*MI*/0, /*OpIdx*/1, // MIs[1]
        GIM_CheckOpcode, /*MI*/1, GIMT_Encode2(TargetOpcode::G_FMAXNUM),
        GIM_CheckType, /*MI*/1, /*Op*/1, /*Type*/GILLT_s32,
        GIM_CheckType, /*MI*/1, /*Op*/2, /*Type*/GILLT_s32,
        GIM_RecordInsn, /*DefineMI*/2, /*MI*/0, /*OpIdx*/2, // MIs[2]
        GIM_CheckOpcode, /*MI*/2, GIMT_Encode2(TargetOpcode::G_FMAXNUM),
        GIM_CheckType, /*MI*/2, /*Op*/1, /*Type*/GILLT_s32,
        GIM_CheckType, /*MI*/2, /*Op*/2, /*Type*/GILLT_s32,
        GIM_RecordInsn, /*DefineMI*/3, /*MI*/2, /*OpIdx*/2, // MIs[3]
        GIM_CheckOpcode, /*MI*/3, GIMT_Encode2(TargetOpcode::G_FMINNUM),
        // MIs[3] VOP3Mods:src0:src0_mods
        GIM_CheckIsSameOperand, /*MI*/3, /*OpIdx*/1, /*OtherMI*/1, /*OtherOpIdx*/2,
        // MIs[3] VOP3Mods:src1:src1_mods
        GIM_CheckIsSameOperand, /*MI*/3, /*OpIdx*/2, /*OtherMI*/1, /*OtherOpIdx*/1,
        GIM_CheckCxxInsnPredicate, /*MI*/0, /*FnId*/GIMT_Encode2(GICXXPred_MI_Predicate_fminnum_like_nnan),
        GIM_CheckIsSafeToFold, /*InsnID*/1,
        GIM_CheckIsSafeToFold, /*InsnID*/2,
        GIM_CheckIsSafeToFold, /*InsnID*/3,
        GIM_CheckComplexPattern, /*MI*/1, /*Op*/1, /*Renderer*/GIMT_Encode2(0), GIMT_Encode2(GICP_gi_vop3mods),
        GIM_CheckComplexPattern, /*MI*/1, /*Op*/2, /*Renderer*/GIMT_Encode2(1), GIMT_Encode2(GICP_gi_vop3mods),
        GIM_CheckComplexPattern, /*MI*/2, /*Op*/1, /*Renderer*/GIMT_Encode2(2), GIMT_Encode2(GICP_gi_vop3mods),
        // (fminnum_ieee:{ *:[f32] } (fmaxnum:{ *:[f32] } (VOP3Mods:{ *:[f32] } f32:{ *:[f32] }:$src1, i32:{ *:[i32] }:$src1_mods), (VOP3Mods:{ *:[f32] } f32:{ *:[f32] }:$src0, i32:{ *:[i32] }:$src0_mods)), (fmaxnum:{ *:[f32] } (VOP3Mods:{ *:[f32] } f32:{ *:[f32] }:$src2, i32:{ *:[i32] }:$src2_mods), (fminnum:{ *:[f32] } (VOP3Mods:{ *:[f32] } f32:{ *:[f32] }:$src0, i32:{ *:[i32] }:$src0_mods), (VOP3Mods:{ *:[f32] } f32:{ *:[f32] }:$src1, i32:{ *:[i32] }:$src1_mods))))<<P:Predicate_fminnum_like_nnan>>  =>  (V_MED3_F32_e64:{ *:[f32] } ?:{ *:[i32] }:$src0_mods, ?:{ *:[f32] }:$src0, ?:{ *:[i32] }:$src1_mods, ?:{ *:[f32] }:$src1, ?:{ *:[i32] }:$src2_mods, ?:{ *:[f32] }:$src2, 0:{ *:[i1] }, 0:{ *:[i32] })
        GIR_BuildMI, /*InsnID*/0, /*Opcode*/GIMT_Encode2(AMDGPU::V_MED3_F32_e64),
        GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/0, // DstI[vdst]
        GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(1), /*SubOperand*/1, // src0_mods
        GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(1), /*SubOperand*/0, // src0
        GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/1, // src1_mods
        GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/0, // src1
        GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(2), /*SubOperand*/1, // src2_mods
        GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(2), /*SubOperand*/0, // src2
        GIR_AddImm8, /*InsnID*/0, /*Imm*/0,
        GIR_AddImm8, /*InsnID*/0, /*Imm*/0,
        GIR_ConstrainSelectedInstOperands, /*InsnID*/0,
        GIR_EraseFromParent, /*InsnID*/0,
        // GIR_Coverage, 10350,
        GIR_Done,
      // Label 4773: @327937
      GIM_Try, /*On fail goto*//*Label 4774*/ GIMT_Encode4(328077), // Rule ID 10351 //
        GIM_CheckRegBankForClass, /*MI*/0, /*Op*/0, /*RC*/GIMT_Encode2(AMDGPU::VGPR_32RegClassID),
        GIM_RecordInsn, /*DefineMI*/1, /*MI*/0, /*OpIdx*/1, // MIs[1]
        GIM_CheckOpcode, /*MI*/1, GIMT_Encode2(TargetOpcode::G_FMAXNUM),
        GIM_CheckType, /*MI*/1, /*Op*/1, /*Type*/GILLT_s32,
        GIM_CheckType, /*MI*/1, /*Op*/2, /*Type*/GILLT_s32,
        GIM_RecordInsn, /*DefineMI*/2, /*MI*/0, /*OpIdx*/2, // MIs[2]
        GIM_CheckOpcode, /*MI*/2, GIMT_Encode2(TargetOpcode::G_FMAXNUM),
        GIM_CheckType, /*MI*/2, /*Op*/1, /*Type*/GILLT_s32,
        GIM_CheckType, /*MI*/2, /*Op*/2, /*Type*/GILLT_s32,
        GIM_RecordInsn, /*DefineMI*/3, /*MI*/2, /*OpIdx*/2, // MIs[3]
        GIM_CheckOpcode, /*MI*/3, GIMT_Encode2(TargetOpcode::G_FMINNUM),
        // MIs[3] VOP3Mods:src1:src1_mods
        GIM_CheckIsSameOperand, /*MI*/3, /*OpIdx*/1, /*OtherMI*/1, /*OtherOpIdx*/1,
        // MIs[3] VOP3Mods:src0:src0_mods
        GIM_CheckIsSameOperand, /*MI*/3, /*OpIdx*/2, /*OtherMI*/1, /*OtherOpIdx*/2,
        GIM_CheckCxxInsnPredicate, /*MI*/0, /*FnId*/GIMT_Encode2(GICXXPred_MI_Predicate_fminnum_like_nnan),
        GIM_CheckIsSafeToFold, /*InsnID*/1,
        GIM_CheckIsSafeToFold, /*InsnID*/2,
        GIM_CheckIsSafeToFold, /*InsnID*/3,
        GIM_CheckComplexPattern, /*MI*/1, /*Op*/1, /*Renderer*/GIMT_Encode2(0), GIMT_Encode2(GICP_gi_vop3mods),
        GIM_CheckComplexPattern, /*MI*/1, /*Op*/2, /*Renderer*/GIMT_Encode2(1), GIMT_Encode2(GICP_gi_vop3mods),
        GIM_CheckComplexPattern, /*MI*/2, /*Op*/1, /*Renderer*/GIMT_Encode2(2), GIMT_Encode2(GICP_gi_vop3mods),
        // (fminnum_ieee:{ *:[f32] } (fmaxnum:{ *:[f32] } (VOP3Mods:{ *:[f32] } f32:{ *:[f32] }:$src1, i32:{ *:[i32] }:$src1_mods), (VOP3Mods:{ *:[f32] } f32:{ *:[f32] }:$src0, i32:{ *:[i32] }:$src0_mods)), (fmaxnum:{ *:[f32] } (VOP3Mods:{ *:[f32] } f32:{ *:[f32] }:$src2, i32:{ *:[i32] }:$src2_mods), (fminnum:{ *:[f32] } (VOP3Mods:{ *:[f32] } f32:{ *:[f32] }:$src1, i32:{ *:[i32] }:$src1_mods), (VOP3Mods:{ *:[f32] } f32:{ *:[f32] }:$src0, i32:{ *:[i32] }:$src0_mods))))<<P:Predicate_fminnum_like_nnan>>  =>  (V_MED3_F32_e64:{ *:[f32] } ?:{ *:[i32] }:$src0_mods, ?:{ *:[f32] }:$src0, ?:{ *:[i32] }:$src1_mods, ?:{ *:[f32] }:$src1, ?:{ *:[i32] }:$src2_mods, ?:{ *:[f32] }:$src2, 0:{ *:[i1] }, 0:{ *:[i32] })
        GIR_BuildMI, /*InsnID*/0, /*Opcode*/GIMT_Encode2(AMDGPU::V_MED3_F32_e64),
        GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/0, // DstI[vdst]
        GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(1), /*SubOperand*/1, // src0_mods
        GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(1), /*SubOperand*/0, // src0
        GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/1, // src1_mods
        GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/0, // src1
        GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(2), /*SubOperand*/1, // src2_mods
        GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(2), /*SubOperand*/0, // src2
        GIR_AddImm8, /*InsnID*/0, /*Imm*/0,
        GIR_AddImm8, /*InsnID*/0, /*Imm*/0,
        GIR_ConstrainSelectedInstOperands, /*InsnID*/0,
        GIR_EraseFromParent, /*InsnID*/0,
        // GIR_Coverage, 10351,
        GIR_Done,
      // Label 4774: @328077
      GIM_Try, /*On fail goto*//*Label 4775*/ GIMT_Encode4(328217), // Rule ID 10331 //
        GIM_CheckRegBankForClass, /*MI*/0, /*Op*/0, /*RC*/GIMT_Encode2(AMDGPU::VGPR_32RegClassID),
        GIM_RecordInsn, /*DefineMI*/1, /*MI*/0, /*OpIdx*/1, // MIs[1]
        GIM_CheckOpcode, /*MI*/1, GIMT_Encode2(TargetOpcode::G_FMAXNUM),
        GIM_CheckType, /*MI*/1, /*Op*/1, /*Type*/GILLT_s32,
        GIM_CheckType, /*MI*/1, /*Op*/2, /*Type*/GILLT_s32,
        GIM_RecordInsn, /*DefineMI*/2, /*MI*/0, /*OpIdx*/2, // MIs[2]
        GIM_CheckOpcode, /*MI*/2, GIMT_Encode2(TargetOpcode::G_FMAXNUM),
        GIM_CheckType, /*MI*/2, /*Op*/1, /*Type*/GILLT_s32,
        GIM_CheckType, /*MI*/2, /*Op*/2, /*Type*/GILLT_s32,
        GIM_RecordInsn, /*DefineMI*/3, /*MI*/2, /*OpIdx*/2, // MIs[3]
        GIM_CheckOpcode, /*MI*/3, GIMT_Encode2(TargetOpcode::G_FMINNUM_IEEE),
        // MIs[3] VOP3Mods:src0:src0_mods
        GIM_CheckIsSameOperand, /*MI*/3, /*OpIdx*/1, /*OtherMI*/1, /*OtherOpIdx*/1,
        // MIs[3] VOP3Mods:src1:src1_mods
        GIM_CheckIsSameOperand, /*MI*/3, /*OpIdx*/2, /*OtherMI*/1, /*OtherOpIdx*/2,
        GIM_CheckCxxInsnPredicate, /*MI*/0, /*FnId*/GIMT_Encode2(GICXXPred_MI_Predicate_fminnum_like_nnan),
        GIM_CheckIsSafeToFold, /*InsnID*/1,
        GIM_CheckIsSafeToFold, /*InsnID*/2,
        GIM_CheckIsSafeToFold, /*InsnID*/3,
        GIM_CheckComplexPattern, /*MI*/1, /*Op*/1, /*Renderer*/GIMT_Encode2(0), GIMT_Encode2(GICP_gi_vop3mods),
        GIM_CheckComplexPattern, /*MI*/1, /*Op*/2, /*Renderer*/GIMT_Encode2(1), GIMT_Encode2(GICP_gi_vop3mods),
        GIM_CheckComplexPattern, /*MI*/2, /*Op*/1, /*Renderer*/GIMT_Encode2(2), GIMT_Encode2(GICP_gi_vop3mods),
        // (fminnum_ieee:{ *:[f32] } (fmaxnum:{ *:[f32] } (VOP3Mods:{ *:[f32] } f32:{ *:[f32] }:$src0, i32:{ *:[i32] }:$src0_mods), (VOP3Mods:{ *:[f32] } f32:{ *:[f32] }:$src1, i32:{ *:[i32] }:$src1_mods)), (fmaxnum:{ *:[f32] } (VOP3Mods:{ *:[f32] } f32:{ *:[f32] }:$src2, i32:{ *:[i32] }:$src2_mods), (fminnum_ieee:{ *:[f32] } (VOP3Mods:{ *:[f32] } f32:{ *:[f32] }:$src0, i32:{ *:[i32] }:$src0_mods), (VOP3Mods:{ *:[f32] } f32:{ *:[f32] }:$src1, i32:{ *:[i32] }:$src1_mods))))<<P:Predicate_fminnum_like_nnan>>  =>  (V_MED3_F32_e64:{ *:[f32] } ?:{ *:[i32] }:$src0_mods, ?:{ *:[f32] }:$src0, ?:{ *:[i32] }:$src1_mods, ?:{ *:[f32] }:$src1, ?:{ *:[i32] }:$src2_mods, ?:{ *:[f32] }:$src2, 0:{ *:[i1] }, 0:{ *:[i32] })
        GIR_BuildMI, /*InsnID*/0, /*Opcode*/GIMT_Encode2(AMDGPU::V_MED3_F32_e64),
        GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/0, // DstI[vdst]
        GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/1, // src0_mods
        GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/0, // src0
        GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(1), /*SubOperand*/1, // src1_mods
        GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(1), /*SubOperand*/0, // src1
        GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(2), /*SubOperand*/1, // src2_mods
        GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(2), /*SubOperand*/0, // src2
        GIR_AddImm8, /*InsnID*/0, /*Imm*/0,
        GIR_AddImm8, /*InsnID*/0, /*Imm*/0,
        GIR_ConstrainSelectedInstOperands, /*InsnID*/0,
        GIR_EraseFromParent, /*InsnID*/0,
        // GIR_Coverage, 10331,
        GIR_Done,
      // Label 4775: @328217
      GIM_Try, /*On fail goto*//*Label 4776*/ GIMT_Encode4(328357), // Rule ID 10332 //
        GIM_CheckRegBankForClass, /*MI*/0, /*Op*/0, /*RC*/GIMT_Encode2(AMDGPU::VGPR_32RegClassID),
        GIM_RecordInsn, /*DefineMI*/1, /*MI*/0, /*OpIdx*/1, // MIs[1]
        GIM_CheckOpcode, /*MI*/1, GIMT_Encode2(TargetOpcode::G_FMAXNUM),
        GIM_CheckType, /*MI*/1, /*Op*/1, /*Type*/GILLT_s32,
        GIM_CheckType, /*MI*/1, /*Op*/2, /*Type*/GILLT_s32,
        GIM_RecordInsn, /*DefineMI*/2, /*MI*/0, /*OpIdx*/2, // MIs[2]
        GIM_CheckOpcode, /*MI*/2, GIMT_Encode2(TargetOpcode::G_FMAXNUM),
        GIM_CheckType, /*MI*/2, /*Op*/1, /*Type*/GILLT_s32,
        GIM_CheckType, /*MI*/2, /*Op*/2, /*Type*/GILLT_s32,
        GIM_RecordInsn, /*DefineMI*/3, /*MI*/2, /*OpIdx*/2, // MIs[3]
        GIM_CheckOpcode, /*MI*/3, GIMT_Encode2(TargetOpcode::G_FMINNUM_IEEE),
        // MIs[3] VOP3Mods:src1:src1_mods
        GIM_CheckIsSameOperand, /*MI*/3, /*OpIdx*/1, /*OtherMI*/1, /*OtherOpIdx*/2,
        // MIs[3] VOP3Mods:src0:src0_mods
        GIM_CheckIsSameOperand, /*MI*/3, /*OpIdx*/2, /*OtherMI*/1, /*OtherOpIdx*/1,
        GIM_CheckCxxInsnPredicate, /*MI*/0, /*FnId*/GIMT_Encode2(GICXXPred_MI_Predicate_fminnum_like_nnan),
        GIM_CheckIsSafeToFold, /*InsnID*/1,
        GIM_CheckIsSafeToFold, /*InsnID*/2,
        GIM_CheckIsSafeToFold, /*InsnID*/3,
        GIM_CheckComplexPattern, /*MI*/1, /*Op*/1, /*Renderer*/GIMT_Encode2(0), GIMT_Encode2(GICP_gi_vop3mods),
        GIM_CheckComplexPattern, /*MI*/1, /*Op*/2, /*Renderer*/GIMT_Encode2(1), GIMT_Encode2(GICP_gi_vop3mods),
        GIM_CheckComplexPattern, /*MI*/2, /*Op*/1, /*Renderer*/GIMT_Encode2(2), GIMT_Encode2(GICP_gi_vop3mods),
        // (fminnum_ieee:{ *:[f32] } (fmaxnum:{ *:[f32] } (VOP3Mods:{ *:[f32] } f32:{ *:[f32] }:$src0, i32:{ *:[i32] }:$src0_mods), (VOP3Mods:{ *:[f32] } f32:{ *:[f32] }:$src1, i32:{ *:[i32] }:$src1_mods)), (fmaxnum:{ *:[f32] } (VOP3Mods:{ *:[f32] } f32:{ *:[f32] }:$src2, i32:{ *:[i32] }:$src2_mods), (fminnum_ieee:{ *:[f32] } (VOP3Mods:{ *:[f32] } f32:{ *:[f32] }:$src1, i32:{ *:[i32] }:$src1_mods), (VOP3Mods:{ *:[f32] } f32:{ *:[f32] }:$src0, i32:{ *:[i32] }:$src0_mods))))<<P:Predicate_fminnum_like_nnan>>  =>  (V_MED3_F32_e64:{ *:[f32] } ?:{ *:[i32] }:$src0_mods, ?:{ *:[f32] }:$src0, ?:{ *:[i32] }:$src1_mods, ?:{ *:[f32] }:$src1, ?:{ *:[i32] }:$src2_mods, ?:{ *:[f32] }:$src2, 0:{ *:[i1] }, 0:{ *:[i32] })
        GIR_BuildMI, /*InsnID*/0, /*Opcode*/GIMT_Encode2(AMDGPU::V_MED3_F32_e64),
        GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/0, // DstI[vdst]
        GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/1, // src0_mods
        GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/0, // src0
        GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(1), /*SubOperand*/1, // src1_mods
        GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(1), /*SubOperand*/0, // src1
        GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(2), /*SubOperand*/1, // src2_mods
        GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(2), /*SubOperand*/0, // src2
        GIR_AddImm8, /*InsnID*/0, /*Imm*/0,
        GIR_AddImm8, /*InsnID*/0, /*Imm*/0,
        GIR_ConstrainSelectedInstOperands, /*InsnID*/0,
        GIR_EraseFromParent, /*InsnID*/0,
        // GIR_Coverage, 10332,
        GIR_Done,
      // Label 4776: @328357
      GIM_Try, /*On fail goto*//*Label 4777*/ GIMT_Encode4(328497), // Rule ID 10335 //
        GIM_CheckRegBankForClass, /*MI*/0, /*Op*/0, /*RC*/GIMT_Encode2(AMDGPU::VGPR_32RegClassID),
        GIM_RecordInsn, /*DefineMI*/1, /*MI*/0, /*OpIdx*/1, // MIs[1]
        GIM_CheckOpcode, /*MI*/1, GIMT_Encode2(TargetOpcode::G_FMAXNUM),
        GIM_CheckType, /*MI*/1, /*Op*/1, /*Type*/GILLT_s32,
        GIM_CheckType, /*MI*/1, /*Op*/2, /*Type*/GILLT_s32,
        GIM_RecordInsn, /*DefineMI*/2, /*MI*/0, /*OpIdx*/2, // MIs[2]
        GIM_CheckOpcode, /*MI*/2, GIMT_Encode2(TargetOpcode::G_FMAXNUM),
        GIM_CheckType, /*MI*/2, /*Op*/1, /*Type*/GILLT_s32,
        GIM_CheckType, /*MI*/2, /*Op*/2, /*Type*/GILLT_s32,
        GIM_RecordInsn, /*DefineMI*/3, /*MI*/2, /*OpIdx*/2, // MIs[3]
        GIM_CheckOpcode, /*MI*/3, GIMT_Encode2(TargetOpcode::G_FMINNUM_IEEE),
        // MIs[3] VOP3Mods:src0:src0_mods
        GIM_CheckIsSameOperand, /*MI*/3, /*OpIdx*/1, /*OtherMI*/1, /*OtherOpIdx*/2,
        // MIs[3] VOP3Mods:src1:src1_mods
        GIM_CheckIsSameOperand, /*MI*/3, /*OpIdx*/2, /*OtherMI*/1, /*OtherOpIdx*/1,
        GIM_CheckCxxInsnPredicate, /*MI*/0, /*FnId*/GIMT_Encode2(GICXXPred_MI_Predicate_fminnum_like_nnan),
        GIM_CheckIsSafeToFold, /*InsnID*/1,
        GIM_CheckIsSafeToFold, /*InsnID*/2,
        GIM_CheckIsSafeToFold, /*InsnID*/3,
        GIM_CheckComplexPattern, /*MI*/1, /*Op*/1, /*Renderer*/GIMT_Encode2(0), GIMT_Encode2(GICP_gi_vop3mods),
        GIM_CheckComplexPattern, /*MI*/1, /*Op*/2, /*Renderer*/GIMT_Encode2(1), GIMT_Encode2(GICP_gi_vop3mods),
        GIM_CheckComplexPattern, /*MI*/2, /*Op*/1, /*Renderer*/GIMT_Encode2(2), GIMT_Encode2(GICP_gi_vop3mods),
        // (fminnum_ieee:{ *:[f32] } (fmaxnum:{ *:[f32] } (VOP3Mods:{ *:[f32] } f32:{ *:[f32] }:$src1, i32:{ *:[i32] }:$src1_mods), (VOP3Mods:{ *:[f32] } f32:{ *:[f32] }:$src0, i32:{ *:[i32] }:$src0_mods)), (fmaxnum:{ *:[f32] } (VOP3Mods:{ *:[f32] } f32:{ *:[f32] }:$src2, i32:{ *:[i32] }:$src2_mods), (fminnum_ieee:{ *:[f32] } (VOP3Mods:{ *:[f32] } f32:{ *:[f32] }:$src0, i32:{ *:[i32] }:$src0_mods), (VOP3Mods:{ *:[f32] } f32:{ *:[f32] }:$src1, i32:{ *:[i32] }:$src1_mods))))<<P:Predicate_fminnum_like_nnan>>  =>  (V_MED3_F32_e64:{ *:[f32] } ?:{ *:[i32] }:$src0_mods, ?:{ *:[f32] }:$src0, ?:{ *:[i32] }:$src1_mods, ?:{ *:[f32] }:$src1, ?:{ *:[i32] }:$src2_mods, ?:{ *:[f32] }:$src2, 0:{ *:[i1] }, 0:{ *:[i32] })
        GIR_BuildMI, /*InsnID*/0, /*Opcode*/GIMT_Encode2(AMDGPU::V_MED3_F32_e64),
        GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/0, // DstI[vdst]
        GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(1), /*SubOperand*/1, // src0_mods
        GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(1), /*SubOperand*/0, // src0
        GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/1, // src1_mods
        GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/0, // src1
        GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(2), /*SubOperand*/1, // src2_mods
        GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(2), /*SubOperand*/0, // src2
        GIR_AddImm8, /*InsnID*/0, /*Imm*/0,
        GIR_AddImm8, /*InsnID*/0, /*Imm*/0,
        GIR_ConstrainSelectedInstOperands, /*InsnID*/0,
        GIR_EraseFromParent, /*InsnID*/0,
        // GIR_Coverage, 10335,
        GIR_Done,
      // Label 4777: @328497
      GIM_Try, /*On fail goto*//*Label 4778*/ GIMT_Encode4(328637), // Rule ID 10336 //
        GIM_CheckRegBankForClass, /*MI*/0, /*Op*/0, /*RC*/GIMT_Encode2(AMDGPU::VGPR_32RegClassID),
        GIM_RecordInsn, /*DefineMI*/1, /*MI*/0, /*OpIdx*/1, // MIs[1]
        GIM_CheckOpcode, /*MI*/1, GIMT_Encode2(TargetOpcode::G_FMAXNUM),
        GIM_CheckType, /*MI*/1, /*Op*/1, /*Type*/GILLT_s32,
        GIM_CheckType, /*MI*/1, /*Op*/2, /*Type*/GILLT_s32,
        GIM_RecordInsn, /*DefineMI*/2, /*MI*/0, /*OpIdx*/2, // MIs[2]
        GIM_CheckOpcode, /*MI*/2, GIMT_Encode2(TargetOpcode::G_FMAXNUM),
        GIM_CheckType, /*MI*/2, /*Op*/1, /*Type*/GILLT_s32,
        GIM_CheckType, /*MI*/2, /*Op*/2, /*Type*/GILLT_s32,
        GIM_RecordInsn, /*DefineMI*/3, /*MI*/2, /*OpIdx*/2, // MIs[3]
        GIM_CheckOpcode, /*MI*/3, GIMT_Encode2(TargetOpcode::G_FMINNUM_IEEE),
        // MIs[3] VOP3Mods:src1:src1_mods
        GIM_CheckIsSameOperand, /*MI*/3, /*OpIdx*/1, /*OtherMI*/1, /*OtherOpIdx*/1,
        // MIs[3] VOP3Mods:src0:src0_mods
        GIM_CheckIsSameOperand, /*MI*/3, /*OpIdx*/2, /*OtherMI*/1, /*OtherOpIdx*/2,
        GIM_CheckCxxInsnPredicate, /*MI*/0, /*FnId*/GIMT_Encode2(GICXXPred_MI_Predicate_fminnum_like_nnan),
        GIM_CheckIsSafeToFold, /*InsnID*/1,
        GIM_CheckIsSafeToFold, /*InsnID*/2,
        GIM_CheckIsSafeToFold, /*InsnID*/3,
        GIM_CheckComplexPattern, /*MI*/1, /*Op*/1, /*Renderer*/GIMT_Encode2(0), GIMT_Encode2(GICP_gi_vop3mods),
        GIM_CheckComplexPattern, /*MI*/1, /*Op*/2, /*Renderer*/GIMT_Encode2(1), GIMT_Encode2(GICP_gi_vop3mods),
        GIM_CheckComplexPattern, /*MI*/2, /*Op*/1, /*Renderer*/GIMT_Encode2(2), GIMT_Encode2(GICP_gi_vop3mods),
        // (fminnum_ieee:{ *:[f32] } (fmaxnum:{ *:[f32] } (VOP3Mods:{ *:[f32] } f32:{ *:[f32] }:$src1, i32:{ *:[i32] }:$src1_mods), (VOP3Mods:{ *:[f32] } f32:{ *:[f32] }:$src0, i32:{ *:[i32] }:$src0_mods)), (fmaxnum:{ *:[f32] } (VOP3Mods:{ *:[f32] } f32:{ *:[f32] }:$src2, i32:{ *:[i32] }:$src2_mods), (fminnum_ieee:{ *:[f32] } (VOP3Mods:{ *:[f32] } f32:{ *:[f32] }:$src1, i32:{ *:[i32] }:$src1_mods), (VOP3Mods:{ *:[f32] } f32:{ *:[f32] }:$src0, i32:{ *:[i32] }:$src0_mods))))<<P:Predicate_fminnum_like_nnan>>  =>  (V_MED3_F32_e64:{ *:[f32] } ?:{ *:[i32] }:$src0_mods, ?:{ *:[f32] }:$src0, ?:{ *:[i32] }:$src1_mods, ?:{ *:[f32] }:$src1, ?:{ *:[i32] }:$src2_mods, ?:{ *:[f32] }:$src2, 0:{ *:[i1] }, 0:{ *:[i32] })
        GIR_BuildMI, /*InsnID*/0, /*Opcode*/GIMT_Encode2(AMDGPU::V_MED3_F32_e64),
        GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/0, // DstI[vdst]
        GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(1), /*SubOperand*/1, // src0_mods
        GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(1), /*SubOperand*/0, // src0
        GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/1, // src1_mods
        GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/0, // src1
        GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(2), /*SubOperand*/1, // src2_mods
        GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(2), /*SubOperand*/0, // src2
        GIR_AddImm8, /*InsnID*/0, /*Imm*/0,
        GIR_AddImm8, /*InsnID*/0, /*Imm*/0,
        GIR_ConstrainSelectedInstOperands, /*InsnID*/0,
        GIR_EraseFromParent, /*InsnID*/0,
        // GIR_Coverage, 10336,
        GIR_Done,
      // Label 4778: @328637
      GIM_Try, /*On fail goto*//*Label 4779*/ GIMT_Encode4(328777), // Rule ID 6505 //
        GIM_CheckRegBankForClass, /*MI*/0, /*Op*/0, /*RC*/GIMT_Encode2(AMDGPU::VGPR_32RegClassID),
        GIM_RecordInsn, /*DefineMI*/1, /*MI*/0, /*OpIdx*/1, // MIs[1]
        GIM_CheckOpcode, /*MI*/1, GIMT_Encode2(TargetOpcode::G_FMAXNUM),
        GIM_CheckType, /*MI*/1, /*Op*/1, /*Type*/GILLT_s32,
        GIM_CheckType, /*MI*/1, /*Op*/2, /*Type*/GILLT_s32,
        GIM_RecordInsn, /*DefineMI*/2, /*MI*/0, /*OpIdx*/2, // MIs[2]
        GIM_CheckOpcode, /*MI*/2, GIMT_Encode2(TargetOpcode::G_FMAXNUM),
        GIM_CheckType, /*MI*/2, /*Op*/1, /*Type*/GILLT_s32,
        GIM_CheckType, /*MI*/2, /*Op*/2, /*Type*/GILLT_s32,
        GIM_RecordInsn, /*DefineMI*/3, /*MI*/2, /*OpIdx*/1, // MIs[3]
        GIM_CheckOpcode, /*MI*/3, GIMT_Encode2(TargetOpcode::G_FMINNUM),
        // MIs[3] VOP3Mods:src0:src0_mods
        GIM_CheckIsSameOperand, /*MI*/3, /*OpIdx*/1, /*OtherMI*/1, /*OtherOpIdx*/1,
        // MIs[3] VOP3Mods:src1:src1_mods
        GIM_CheckIsSameOperand, /*MI*/3, /*OpIdx*/2, /*OtherMI*/1, /*OtherOpIdx*/2,
        GIM_CheckCxxInsnPredicate, /*MI*/0, /*FnId*/GIMT_Encode2(GICXXPred_MI_Predicate_fminnum_like_nnan),
        GIM_CheckIsSafeToFold, /*InsnID*/1,
        GIM_CheckIsSafeToFold, /*InsnID*/2,
        GIM_CheckIsSafeToFold, /*InsnID*/3,
        GIM_CheckComplexPattern, /*MI*/1, /*Op*/1, /*Renderer*/GIMT_Encode2(0), GIMT_Encode2(GICP_gi_vop3mods),
        GIM_CheckComplexPattern, /*MI*/1, /*Op*/2, /*Renderer*/GIMT_Encode2(1), GIMT_Encode2(GICP_gi_vop3mods),
        GIM_CheckComplexPattern, /*MI*/2, /*Op*/2, /*Renderer*/GIMT_Encode2(2), GIMT_Encode2(GICP_gi_vop3mods),
        // (fminnum_ieee:{ *:[f32] } (fmaxnum:{ *:[f32] } (VOP3Mods:{ *:[f32] } f32:{ *:[f32] }:$src0, i32:{ *:[i32] }:$src0_mods), (VOP3Mods:{ *:[f32] } f32:{ *:[f32] }:$src1, i32:{ *:[i32] }:$src1_mods)), (fmaxnum:{ *:[f32] } (fminnum:{ *:[f32] } (VOP3Mods:{ *:[f32] } f32:{ *:[f32] }:$src0, i32:{ *:[i32] }:$src0_mods), (VOP3Mods:{ *:[f32] } f32:{ *:[f32] }:$src1, i32:{ *:[i32] }:$src1_mods)), (VOP3Mods:{ *:[f32] } f32:{ *:[f32] }:$src2, i32:{ *:[i32] }:$src2_mods)))<<P:Predicate_fminnum_like_nnan>>  =>  (V_MED3_F32_e64:{ *:[f32] } ?:{ *:[i32] }:$src0_mods, ?:{ *:[f32] }:$src0, ?:{ *:[i32] }:$src1_mods, ?:{ *:[f32] }:$src1, ?:{ *:[i32] }:$src2_mods, ?:{ *:[f32] }:$src2, 0:{ *:[i1] }, 0:{ *:[i32] })
        GIR_BuildMI, /*InsnID*/0, /*Opcode*/GIMT_Encode2(AMDGPU::V_MED3_F32_e64),
        GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/0, // DstI[vdst]
        GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/1, // src0_mods
        GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/0, // src0
        GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(1), /*SubOperand*/1, // src1_mods
        GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(1), /*SubOperand*/0, // src1
        GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(2), /*SubOperand*/1, // src2_mods
        GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(2), /*SubOperand*/0, // src2
        GIR_AddImm8, /*InsnID*/0, /*Imm*/0,
        GIR_AddImm8, /*InsnID*/0, /*Imm*/0,
        GIR_ConstrainSelectedInstOperands, /*InsnID*/0,
        GIR_EraseFromParent, /*InsnID*/0,
        // GIR_Coverage, 6505,
        GIR_Done,
      // Label 4779: @328777
      GIM_Try, /*On fail goto*//*Label 4780*/ GIMT_Encode4(328917), // Rule ID 10345 //
        GIM_CheckRegBankForClass, /*MI*/0, /*Op*/0, /*RC*/GIMT_Encode2(AMDGPU::VGPR_32RegClassID),
        GIM_RecordInsn, /*DefineMI*/1, /*MI*/0, /*OpIdx*/1, // MIs[1]
        GIM_CheckOpcode, /*MI*/1, GIMT_Encode2(TargetOpcode::G_FMAXNUM),
        GIM_CheckType, /*MI*/1, /*Op*/1, /*Type*/GILLT_s32,
        GIM_CheckType, /*MI*/1, /*Op*/2, /*Type*/GILLT_s32,
        GIM_RecordInsn, /*DefineMI*/2, /*MI*/0, /*OpIdx*/2, // MIs[2]
        GIM_CheckOpcode, /*MI*/2, GIMT_Encode2(TargetOpcode::G_FMAXNUM),
        GIM_CheckType, /*MI*/2, /*Op*/1, /*Type*/GILLT_s32,
        GIM_CheckType, /*MI*/2, /*Op*/2, /*Type*/GILLT_s32,
        GIM_RecordInsn, /*DefineMI*/3, /*MI*/2, /*OpIdx*/1, // MIs[3]
        GIM_CheckOpcode, /*MI*/3, GIMT_Encode2(TargetOpcode::G_FMINNUM),
        // MIs[3] VOP3Mods:src1:src1_mods
        GIM_CheckIsSameOperand, /*MI*/3, /*OpIdx*/1, /*OtherMI*/1, /*OtherOpIdx*/2,
        // MIs[3] VOP3Mods:src0:src0_mods
        GIM_CheckIsSameOperand, /*MI*/3, /*OpIdx*/2, /*OtherMI*/1, /*OtherOpIdx*/1,
        GIM_CheckCxxInsnPredicate, /*MI*/0, /*FnId*/GIMT_Encode2(GICXXPred_MI_Predicate_fminnum_like_nnan),
        GIM_CheckIsSafeToFold, /*InsnID*/1,
        GIM_CheckIsSafeToFold, /*InsnID*/2,
        GIM_CheckIsSafeToFold, /*InsnID*/3,
        GIM_CheckComplexPattern, /*MI*/1, /*Op*/1, /*Renderer*/GIMT_Encode2(0), GIMT_Encode2(GICP_gi_vop3mods),
        GIM_CheckComplexPattern, /*MI*/1, /*Op*/2, /*Renderer*/GIMT_Encode2(1), GIMT_Encode2(GICP_gi_vop3mods),
        GIM_CheckComplexPattern, /*MI*/2, /*Op*/2, /*Renderer*/GIMT_Encode2(2), GIMT_Encode2(GICP_gi_vop3mods),
        // (fminnum_ieee:{ *:[f32] } (fmaxnum:{ *:[f32] } (VOP3Mods:{ *:[f32] } f32:{ *:[f32] }:$src0, i32:{ *:[i32] }:$src0_mods), (VOP3Mods:{ *:[f32] } f32:{ *:[f32] }:$src1, i32:{ *:[i32] }:$src1_mods)), (fmaxnum:{ *:[f32] } (fminnum:{ *:[f32] } (VOP3Mods:{ *:[f32] } f32:{ *:[f32] }:$src1, i32:{ *:[i32] }:$src1_mods), (VOP3Mods:{ *:[f32] } f32:{ *:[f32] }:$src0, i32:{ *:[i32] }:$src0_mods)), (VOP3Mods:{ *:[f32] } f32:{ *:[f32] }:$src2, i32:{ *:[i32] }:$src2_mods)))<<P:Predicate_fminnum_like_nnan>>  =>  (V_MED3_F32_e64:{ *:[f32] } ?:{ *:[i32] }:$src0_mods, ?:{ *:[f32] }:$src0, ?:{ *:[i32] }:$src1_mods, ?:{ *:[f32] }:$src1, ?:{ *:[i32] }:$src2_mods, ?:{ *:[f32] }:$src2, 0:{ *:[i1] }, 0:{ *:[i32] })
        GIR_BuildMI, /*InsnID*/0, /*Opcode*/GIMT_Encode2(AMDGPU::V_MED3_F32_e64),
        GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/0, // DstI[vdst]
        GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/1, // src0_mods
        GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/0, // src0
        GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(1), /*SubOperand*/1, // src1_mods
        GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(1), /*SubOperand*/0, // src1
        GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(2), /*SubOperand*/1, // src2_mods
        GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(2), /*SubOperand*/0, // src2
        GIR_AddImm8, /*InsnID*/0, /*Imm*/0,
        GIR_AddImm8, /*InsnID*/0, /*Imm*/0,
        GIR_ConstrainSelectedInstOperands, /*InsnID*/0,
        GIR_EraseFromParent, /*InsnID*/0,
        // GIR_Coverage, 10345,
        GIR_Done,
      // Label 4780: @328917
      GIM_Try, /*On fail goto*//*Label 4781*/ GIMT_Encode4(329057), // Rule ID 10348 //
        GIM_CheckRegBankForClass, /*MI*/0, /*Op*/0, /*RC*/GIMT_Encode2(AMDGPU::VGPR_32RegClassID),
        GIM_RecordInsn, /*DefineMI*/1, /*MI*/0, /*OpIdx*/1, // MIs[1]
        GIM_CheckOpcode, /*MI*/1, GIMT_Encode2(TargetOpcode::G_FMAXNUM),
        GIM_CheckType, /*MI*/1, /*Op*/1, /*Type*/GILLT_s32,
        GIM_CheckType, /*MI*/1, /*Op*/2, /*Type*/GILLT_s32,
        GIM_RecordInsn, /*DefineMI*/2, /*MI*/0, /*OpIdx*/2, // MIs[2]
        GIM_CheckOpcode, /*MI*/2, GIMT_Encode2(TargetOpcode::G_FMAXNUM),
        GIM_CheckType, /*MI*/2, /*Op*/1, /*Type*/GILLT_s32,
        GIM_CheckType, /*MI*/2, /*Op*/2, /*Type*/GILLT_s32,
        GIM_RecordInsn, /*DefineMI*/3, /*MI*/2, /*OpIdx*/1, // MIs[3]
        GIM_CheckOpcode, /*MI*/3, GIMT_Encode2(TargetOpcode::G_FMINNUM),
        // MIs[3] VOP3Mods:src0:src0_mods
        GIM_CheckIsSameOperand, /*MI*/3, /*OpIdx*/1, /*OtherMI*/1, /*OtherOpIdx*/2,
        // MIs[3] VOP3Mods:src1:src1_mods
        GIM_CheckIsSameOperand, /*MI*/3, /*OpIdx*/2, /*OtherMI*/1, /*OtherOpIdx*/1,
        GIM_CheckCxxInsnPredicate, /*MI*/0, /*FnId*/GIMT_Encode2(GICXXPred_MI_Predicate_fminnum_like_nnan),
        GIM_CheckIsSafeToFold, /*InsnID*/1,
        GIM_CheckIsSafeToFold, /*InsnID*/2,
        GIM_CheckIsSafeToFold, /*InsnID*/3,
        GIM_CheckComplexPattern, /*MI*/1, /*Op*/1, /*Renderer*/GIMT_Encode2(0), GIMT_Encode2(GICP_gi_vop3mods),
        GIM_CheckComplexPattern, /*MI*/1, /*Op*/2, /*Renderer*/GIMT_Encode2(1), GIMT_Encode2(GICP_gi_vop3mods),
        GIM_CheckComplexPattern, /*MI*/2, /*Op*/2, /*Renderer*/GIMT_Encode2(2), GIMT_Encode2(GICP_gi_vop3mods),
        // (fminnum_ieee:{ *:[f32] } (fmaxnum:{ *:[f32] } (VOP3Mods:{ *:[f32] } f32:{ *:[f32] }:$src1, i32:{ *:[i32] }:$src1_mods), (VOP3Mods:{ *:[f32] } f32:{ *:[f32] }:$src0, i32:{ *:[i32] }:$src0_mods)), (fmaxnum:{ *:[f32] } (fminnum:{ *:[f32] } (VOP3Mods:{ *:[f32] } f32:{ *:[f32] }:$src0, i32:{ *:[i32] }:$src0_mods), (VOP3Mods:{ *:[f32] } f32:{ *:[f32] }:$src1, i32:{ *:[i32] }:$src1_mods)), (VOP3Mods:{ *:[f32] } f32:{ *:[f32] }:$src2, i32:{ *:[i32] }:$src2_mods)))<<P:Predicate_fminnum_like_nnan>>  =>  (V_MED3_F32_e64:{ *:[f32] } ?:{ *:[i32] }:$src0_mods, ?:{ *:[f32] }:$src0, ?:{ *:[i32] }:$src1_mods, ?:{ *:[f32] }:$src1, ?:{ *:[i32] }:$src2_mods, ?:{ *:[f32] }:$src2, 0:{ *:[i1] }, 0:{ *:[i32] })
        GIR_BuildMI, /*InsnID*/0, /*Opcode*/GIMT_Encode2(AMDGPU::V_MED3_F32_e64),
        GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/0, // DstI[vdst]
        GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(1), /*SubOperand*/1, // src0_mods
        GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(1), /*SubOperand*/0, // src0
        GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/1, // src1_mods
        GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/0, // src1
        GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(2), /*SubOperand*/1, // src2_mods
        GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(2), /*SubOperand*/0, // src2
        GIR_AddImm8, /*InsnID*/0, /*Imm*/0,
        GIR_AddImm8, /*InsnID*/0, /*Imm*/0,
        GIR_ConstrainSelectedInstOperands, /*InsnID*/0,
        GIR_EraseFromParent, /*InsnID*/0,
        // GIR_Coverage, 10348,
        GIR_Done,
      // Label 4781: @329057
      GIM_Try, /*On fail goto*//*Label 4782*/ GIMT_Encode4(329197), // Rule ID 10349 //
        GIM_CheckRegBankForClass, /*MI*/0, /*Op*/0, /*RC*/GIMT_Encode2(AMDGPU::VGPR_32RegClassID),
        GIM_RecordInsn, /*DefineMI*/1, /*MI*/0, /*OpIdx*/1, // MIs[1]
        GIM_CheckOpcode, /*MI*/1, GIMT_Encode2(TargetOpcode::G_FMAXNUM),
        GIM_CheckType, /*MI*/1, /*Op*/1, /*Type*/GILLT_s32,
        GIM_CheckType, /*MI*/1, /*Op*/2, /*Type*/GILLT_s32,
        GIM_RecordInsn, /*DefineMI*/2, /*MI*/0, /*OpIdx*/2, // MIs[2]
        GIM_CheckOpcode, /*MI*/2, GIMT_Encode2(TargetOpcode::G_FMAXNUM),
        GIM_CheckType, /*MI*/2, /*Op*/1, /*Type*/GILLT_s32,
        GIM_CheckType, /*MI*/2, /*Op*/2, /*Type*/GILLT_s32,
        GIM_RecordInsn, /*DefineMI*/3, /*MI*/2, /*OpIdx*/1, // MIs[3]
        GIM_CheckOpcode, /*MI*/3, GIMT_Encode2(TargetOpcode::G_FMINNUM),
        // MIs[3] VOP3Mods:src1:src1_mods
        GIM_CheckIsSameOperand, /*MI*/3, /*OpIdx*/1, /*OtherMI*/1, /*OtherOpIdx*/1,
        // MIs[3] VOP3Mods:src0:src0_mods
        GIM_CheckIsSameOperand, /*MI*/3, /*OpIdx*/2, /*OtherMI*/1, /*OtherOpIdx*/2,
        GIM_CheckCxxInsnPredicate, /*MI*/0, /*FnId*/GIMT_Encode2(GICXXPred_MI_Predicate_fminnum_like_nnan),
        GIM_CheckIsSafeToFold, /*InsnID*/1,
        GIM_CheckIsSafeToFold, /*InsnID*/2,
        GIM_CheckIsSafeToFold, /*InsnID*/3,
        GIM_CheckComplexPattern, /*MI*/1, /*Op*/1, /*Renderer*/GIMT_Encode2(0), GIMT_Encode2(GICP_gi_vop3mods),
        GIM_CheckComplexPattern, /*MI*/1, /*Op*/2, /*Renderer*/GIMT_Encode2(1), GIMT_Encode2(GICP_gi_vop3mods),
        GIM_CheckComplexPattern, /*MI*/2, /*Op*/2, /*Renderer*/GIMT_Encode2(2), GIMT_Encode2(GICP_gi_vop3mods),
        // (fminnum_ieee:{ *:[f32] } (fmaxnum:{ *:[f32] } (VOP3Mods:{ *:[f32] } f32:{ *:[f32] }:$src1, i32:{ *:[i32] }:$src1_mods), (VOP3Mods:{ *:[f32] } f32:{ *:[f32] }:$src0, i32:{ *:[i32] }:$src0_mods)), (fmaxnum:{ *:[f32] } (fminnum:{ *:[f32] } (VOP3Mods:{ *:[f32] } f32:{ *:[f32] }:$src1, i32:{ *:[i32] }:$src1_mods), (VOP3Mods:{ *:[f32] } f32:{ *:[f32] }:$src0, i32:{ *:[i32] }:$src0_mods)), (VOP3Mods:{ *:[f32] } f32:{ *:[f32] }:$src2, i32:{ *:[i32] }:$src2_mods)))<<P:Predicate_fminnum_like_nnan>>  =>  (V_MED3_F32_e64:{ *:[f32] } ?:{ *:[i32] }:$src0_mods, ?:{ *:[f32] }:$src0, ?:{ *:[i32] }:$src1_mods, ?:{ *:[f32] }:$src1, ?:{ *:[i32] }:$src2_mods, ?:{ *:[f32] }:$src2, 0:{ *:[i1] }, 0:{ *:[i32] })
        GIR_BuildMI, /*InsnID*/0, /*Opcode*/GIMT_Encode2(AMDGPU::V_MED3_F32_e64),
        GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/0, // DstI[vdst]
        GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(1), /*SubOperand*/1, // src0_mods
        GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(1), /*SubOperand*/0, // src0
        GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/1, // src1_mods
        GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/0, // src1
        GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(2), /*SubOperand*/1, // src2_mods
        GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(2), /*SubOperand*/0, // src2
        GIR_AddImm8, /*InsnID*/0, /*Imm*/0,
        GIR_AddImm8, /*InsnID*/0, /*Imm*/0,
        GIR_ConstrainSelectedInstOperands, /*InsnID*/0,
        GIR_EraseFromParent, /*InsnID*/0,
        // GIR_Coverage, 10349,
        GIR_Done,
      // Label 4782: @329197
      GIM_Try, /*On fail goto*//*Label 4783*/ GIMT_Encode4(329337), // Rule ID 6504 //
        GIM_CheckRegBankForClass, /*MI*/0, /*Op*/0, /*RC*/GIMT_Encode2(AMDGPU::VGPR_32RegClassID),
        GIM_RecordInsn, /*DefineMI*/1, /*MI*/0, /*OpIdx*/1, // MIs[1]
        GIM_CheckOpcode, /*MI*/1, GIMT_Encode2(TargetOpcode::G_FMAXNUM),
        GIM_CheckType, /*MI*/1, /*Op*/1, /*Type*/GILLT_s32,
        GIM_CheckType, /*MI*/1, /*Op*/2, /*Type*/GILLT_s32,
        GIM_RecordInsn, /*DefineMI*/2, /*MI*/0, /*OpIdx*/2, // MIs[2]
        GIM_CheckOpcode, /*MI*/2, GIMT_Encode2(TargetOpcode::G_FMAXNUM),
        GIM_CheckType, /*MI*/2, /*Op*/1, /*Type*/GILLT_s32,
        GIM_CheckType, /*MI*/2, /*Op*/2, /*Type*/GILLT_s32,
        GIM_RecordInsn, /*DefineMI*/3, /*MI*/2, /*OpIdx*/1, // MIs[3]
        GIM_CheckOpcode, /*MI*/3, GIMT_Encode2(TargetOpcode::G_FMINNUM_IEEE),
        // MIs[3] VOP3Mods:src0:src0_mods
        GIM_CheckIsSameOperand, /*MI*/3, /*OpIdx*/1, /*OtherMI*/1, /*OtherOpIdx*/1,
        // MIs[3] VOP3Mods:src1:src1_mods
        GIM_CheckIsSameOperand, /*MI*/3, /*OpIdx*/2, /*OtherMI*/1, /*OtherOpIdx*/2,
        GIM_CheckCxxInsnPredicate, /*MI*/0, /*FnId*/GIMT_Encode2(GICXXPred_MI_Predicate_fminnum_like_nnan),
        GIM_CheckIsSafeToFold, /*InsnID*/1,
        GIM_CheckIsSafeToFold, /*InsnID*/2,
        GIM_CheckIsSafeToFold, /*InsnID*/3,
        GIM_CheckComplexPattern, /*MI*/1, /*Op*/1, /*Renderer*/GIMT_Encode2(0), GIMT_Encode2(GICP_gi_vop3mods),
        GIM_CheckComplexPattern, /*MI*/1, /*Op*/2, /*Renderer*/GIMT_Encode2(1), GIMT_Encode2(GICP_gi_vop3mods),
        GIM_CheckComplexPattern, /*MI*/2, /*Op*/2, /*Renderer*/GIMT_Encode2(2), GIMT_Encode2(GICP_gi_vop3mods),
        // (fminnum_ieee:{ *:[f32] } (fmaxnum:{ *:[f32] } (VOP3Mods:{ *:[f32] } f32:{ *:[f32] }:$src0, i32:{ *:[i32] }:$src0_mods), (VOP3Mods:{ *:[f32] } f32:{ *:[f32] }:$src1, i32:{ *:[i32] }:$src1_mods)), (fmaxnum:{ *:[f32] } (fminnum_ieee:{ *:[f32] } (VOP3Mods:{ *:[f32] } f32:{ *:[f32] }:$src0, i32:{ *:[i32] }:$src0_mods), (VOP3Mods:{ *:[f32] } f32:{ *:[f32] }:$src1, i32:{ *:[i32] }:$src1_mods)), (VOP3Mods:{ *:[f32] } f32:{ *:[f32] }:$src2, i32:{ *:[i32] }:$src2_mods)))<<P:Predicate_fminnum_like_nnan>>  =>  (V_MED3_F32_e64:{ *:[f32] } ?:{ *:[i32] }:$src0_mods, ?:{ *:[f32] }:$src0, ?:{ *:[i32] }:$src1_mods, ?:{ *:[f32] }:$src1, ?:{ *:[i32] }:$src2_mods, ?:{ *:[f32] }:$src2, 0:{ *:[i1] }, 0:{ *:[i32] })
        GIR_BuildMI, /*InsnID*/0, /*Opcode*/GIMT_Encode2(AMDGPU::V_MED3_F32_e64),
        GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/0, // DstI[vdst]
        GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/1, // src0_mods
        GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/0, // src0
        GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(1), /*SubOperand*/1, // src1_mods
        GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(1), /*SubOperand*/0, // src1
        GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(2), /*SubOperand*/1, // src2_mods
        GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(2), /*SubOperand*/0, // src2
        GIR_AddImm8, /*InsnID*/0, /*Imm*/0,
        GIR_AddImm8, /*InsnID*/0, /*Imm*/0,
        GIR_ConstrainSelectedInstOperands, /*InsnID*/0,
        GIR_EraseFromParent, /*InsnID*/0,
        // GIR_Coverage, 6504,
        GIR_Done,
      // Label 4783: @329337
      GIM_Try, /*On fail goto*//*Label 4784*/ GIMT_Encode4(329477), // Rule ID 10330 //
        GIM_CheckRegBankForClass, /*MI*/0, /*Op*/0, /*RC*/GIMT_Encode2(AMDGPU::VGPR_32RegClassID),
        GIM_RecordInsn, /*DefineMI*/1, /*MI*/0, /*OpIdx*/1, // MIs[1]
        GIM_CheckOpcode, /*MI*/1, GIMT_Encode2(TargetOpcode::G_FMAXNUM),
        GIM_CheckType, /*MI*/1, /*Op*/1, /*Type*/GILLT_s32,
        GIM_CheckType, /*MI*/1, /*Op*/2, /*Type*/GILLT_s32,
        GIM_RecordInsn, /*DefineMI*/2, /*MI*/0, /*OpIdx*/2, // MIs[2]
        GIM_CheckOpcode, /*MI*/2, GIMT_Encode2(TargetOpcode::G_FMAXNUM),
        GIM_CheckType, /*MI*/2, /*Op*/1, /*Type*/GILLT_s32,
        GIM_CheckType, /*MI*/2, /*Op*/2, /*Type*/GILLT_s32,
        GIM_RecordInsn, /*DefineMI*/3, /*MI*/2, /*OpIdx*/1, // MIs[3]
        GIM_CheckOpcode, /*MI*/3, GIMT_Encode2(TargetOpcode::G_FMINNUM_IEEE),
        // MIs[3] VOP3Mods:src1:src1_mods
        GIM_CheckIsSameOperand, /*MI*/3, /*OpIdx*/1, /*OtherMI*/1, /*OtherOpIdx*/2,
        // MIs[3] VOP3Mods:src0:src0_mods
        GIM_CheckIsSameOperand, /*MI*/3, /*OpIdx*/2, /*OtherMI*/1, /*OtherOpIdx*/1,
        GIM_CheckCxxInsnPredicate, /*MI*/0, /*FnId*/GIMT_Encode2(GICXXPred_MI_Predicate_fminnum_like_nnan),
        GIM_CheckIsSafeToFold, /*InsnID*/1,
        GIM_CheckIsSafeToFold, /*InsnID*/2,
        GIM_CheckIsSafeToFold, /*InsnID*/3,
        GIM_CheckComplexPattern, /*MI*/1, /*Op*/1, /*Renderer*/GIMT_Encode2(0), GIMT_Encode2(GICP_gi_vop3mods),
        GIM_CheckComplexPattern, /*MI*/1, /*Op*/2, /*Renderer*/GIMT_Encode2(1), GIMT_Encode2(GICP_gi_vop3mods),
        GIM_CheckComplexPattern, /*MI*/2, /*Op*/2, /*Renderer*/GIMT_Encode2(2), GIMT_Encode2(GICP_gi_vop3mods),
        // (fminnum_ieee:{ *:[f32] } (fmaxnum:{ *:[f32] } (VOP3Mods:{ *:[f32] } f32:{ *:[f32] }:$src0, i32:{ *:[i32] }:$src0_mods), (VOP3Mods:{ *:[f32] } f32:{ *:[f32] }:$src1, i32:{ *:[i32] }:$src1_mods)), (fmaxnum:{ *:[f32] } (fminnum_ieee:{ *:[f32] } (VOP3Mods:{ *:[f32] } f32:{ *:[f32] }:$src1, i32:{ *:[i32] }:$src1_mods), (VOP3Mods:{ *:[f32] } f32:{ *:[f32] }:$src0, i32:{ *:[i32] }:$src0_mods)), (VOP3Mods:{ *:[f32] } f32:{ *:[f32] }:$src2, i32:{ *:[i32] }:$src2_mods)))<<P:Predicate_fminnum_like_nnan>>  =>  (V_MED3_F32_e64:{ *:[f32] } ?:{ *:[i32] }:$src0_mods, ?:{ *:[f32] }:$src0, ?:{ *:[i32] }:$src1_mods, ?:{ *:[f32] }:$src1, ?:{ *:[i32] }:$src2_mods, ?:{ *:[f32] }:$src2, 0:{ *:[i1] }, 0:{ *:[i32] })
        GIR_BuildMI, /*InsnID*/0, /*Opcode*/GIMT_Encode2(AMDGPU::V_MED3_F32_e64),
        GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/0, // DstI[vdst]
        GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/1, // src0_mods
        GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/0, // src0
        GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(1), /*SubOperand*/1, // src1_mods
        GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(1), /*SubOperand*/0, // src1
        GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(2), /*SubOperand*/1, // src2_mods
        GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(2), /*SubOperand*/0, // src2
        GIR_AddImm8, /*InsnID*/0, /*Imm*/0,
        GIR_AddImm8, /*InsnID*/0, /*Imm*/0,
        GIR_ConstrainSelectedInstOperands, /*InsnID*/0,
        GIR_EraseFromParent, /*InsnID*/0,
        // GIR_Coverage, 10330,
        GIR_Done,
      // Label 4784: @329477
      GIM_Try, /*On fail goto*//*Label 4785*/ GIMT_Encode4(329617), // Rule ID 10333 //
        GIM_CheckRegBankForClass, /*MI*/0, /*Op*/0, /*RC*/GIMT_Encode2(AMDGPU::VGPR_32RegClassID),
        GIM_RecordInsn, /*DefineMI*/1, /*MI*/0, /*OpIdx*/1, // MIs[1]
        GIM_CheckOpcode, /*MI*/1, GIMT_Encode2(TargetOpcode::G_FMAXNUM),
        GIM_CheckType, /*MI*/1, /*Op*/1, /*Type*/GILLT_s32,
        GIM_CheckType, /*MI*/1, /*Op*/2, /*Type*/GILLT_s32,
        GIM_RecordInsn, /*DefineMI*/2, /*MI*/0, /*OpIdx*/2, // MIs[2]
        GIM_CheckOpcode, /*MI*/2, GIMT_Encode2(TargetOpcode::G_FMAXNUM),
        GIM_CheckType, /*MI*/2, /*Op*/1, /*Type*/GILLT_s32,
        GIM_CheckType, /*MI*/2, /*Op*/2, /*Type*/GILLT_s32,
        GIM_RecordInsn, /*DefineMI*/3, /*MI*/2, /*OpIdx*/1, // MIs[3]
        GIM_CheckOpcode, /*MI*/3, GIMT_Encode2(TargetOpcode::G_FMINNUM_IEEE),
        // MIs[3] VOP3Mods:src0:src0_mods
        GIM_CheckIsSameOperand, /*MI*/3, /*OpIdx*/1, /*OtherMI*/1, /*OtherOpIdx*/2,
        // MIs[3] VOP3Mods:src1:src1_mods
        GIM_CheckIsSameOperand, /*MI*/3, /*OpIdx*/2, /*OtherMI*/1, /*OtherOpIdx*/1,
        GIM_CheckCxxInsnPredicate, /*MI*/0, /*FnId*/GIMT_Encode2(GICXXPred_MI_Predicate_fminnum_like_nnan),
        GIM_CheckIsSafeToFold, /*InsnID*/1,
        GIM_CheckIsSafeToFold, /*InsnID*/2,
        GIM_CheckIsSafeToFold, /*InsnID*/3,
        GIM_CheckComplexPattern, /*MI*/1, /*Op*/1, /*Renderer*/GIMT_Encode2(0), GIMT_Encode2(GICP_gi_vop3mods),
        GIM_CheckComplexPattern, /*MI*/1, /*Op*/2, /*Renderer*/GIMT_Encode2(1), GIMT_Encode2(GICP_gi_vop3mods),
        GIM_CheckComplexPattern, /*MI*/2, /*Op*/2, /*Renderer*/GIMT_Encode2(2), GIMT_Encode2(GICP_gi_vop3mods),
        // (fminnum_ieee:{ *:[f32] } (fmaxnum:{ *:[f32] } (VOP3Mods:{ *:[f32] } f32:{ *:[f32] }:$src1, i32:{ *:[i32] }:$src1_mods), (VOP3Mods:{ *:[f32] } f32:{ *:[f32] }:$src0, i32:{ *:[i32] }:$src0_mods)), (fmaxnum:{ *:[f32] } (fminnum_ieee:{ *:[f32] } (VOP3Mods:{ *:[f32] } f32:{ *:[f32] }:$src0, i32:{ *:[i32] }:$src0_mods), (VOP3Mods:{ *:[f32] } f32:{ *:[f32] }:$src1, i32:{ *:[i32] }:$src1_mods)), (VOP3Mods:{ *:[f32] } f32:{ *:[f32] }:$src2, i32:{ *:[i32] }:$src2_mods)))<<P:Predicate_fminnum_like_nnan>>  =>  (V_MED3_F32_e64:{ *:[f32] } ?:{ *:[i32] }:$src0_mods, ?:{ *:[f32] }:$src0, ?:{ *:[i32] }:$src1_mods, ?:{ *:[f32] }:$src1, ?:{ *:[i32] }:$src2_mods, ?:{ *:[f32] }:$src2, 0:{ *:[i1] }, 0:{ *:[i32] })
        GIR_BuildMI, /*InsnID*/0, /*Opcode*/GIMT_Encode2(AMDGPU::V_MED3_F32_e64),
        GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/0, // DstI[vdst]
        GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(1), /*SubOperand*/1, // src0_mods
        GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(1), /*SubOperand*/0, // src0
        GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/1, // src1_mods
        GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/0, // src1
        GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(2), /*SubOperand*/1, // src2_mods
        GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(2), /*SubOperand*/0, // src2
        GIR_AddImm8, /*InsnID*/0, /*Imm*/0,
        GIR_AddImm8, /*InsnID*/0, /*Imm*/0,
        GIR_ConstrainSelectedInstOperands, /*InsnID*/0,
        GIR_EraseFromParent, /*InsnID*/0,
        // GIR_Coverage, 10333,
        GIR_Done,
      // Label 4785: @329617
      GIM_Try, /*On fail goto*//*Label 4786*/ GIMT_Encode4(329757), // Rule ID 10334 //
        GIM_CheckRegBankForClass, /*MI*/0, /*Op*/0, /*RC*/GIMT_Encode2(AMDGPU::VGPR_32RegClassID),
        GIM_RecordInsn, /*DefineMI*/1, /*MI*/0, /*OpIdx*/1, // MIs[1]
        GIM_CheckOpcode, /*MI*/1, GIMT_Encode2(TargetOpcode::G_FMAXNUM),
        GIM_CheckType, /*MI*/1, /*Op*/1, /*Type*/GILLT_s32,
        GIM_CheckType, /*MI*/1, /*Op*/2, /*Type*/GILLT_s32,
        GIM_RecordInsn, /*DefineMI*/2, /*MI*/0, /*OpIdx*/2, // MIs[2]
        GIM_CheckOpcode, /*MI*/2, GIMT_Encode2(TargetOpcode::G_FMAXNUM),
        GIM_CheckType, /*MI*/2, /*Op*/1, /*Type*/GILLT_s32,
        GIM_CheckType, /*MI*/2, /*Op*/2, /*Type*/GILLT_s32,
        GIM_RecordInsn, /*DefineMI*/3, /*MI*/2, /*OpIdx*/1, // MIs[3]
        GIM_CheckOpcode, /*MI*/3, GIMT_Encode2(TargetOpcode::G_FMINNUM_IEEE),
        // MIs[3] VOP3Mods:src1:src1_mods
        GIM_CheckIsSameOperand, /*MI*/3, /*OpIdx*/1, /*OtherMI*/1, /*OtherOpIdx*/1,
        // MIs[3] VOP3Mods:src0:src0_mods
        GIM_CheckIsSameOperand, /*MI*/3, /*OpIdx*/2, /*OtherMI*/1, /*OtherOpIdx*/2,
        GIM_CheckCxxInsnPredicate, /*MI*/0, /*FnId*/GIMT_Encode2(GICXXPred_MI_Predicate_fminnum_like_nnan),
        GIM_CheckIsSafeToFold, /*InsnID*/1,
        GIM_CheckIsSafeToFold, /*InsnID*/2,
        GIM_CheckIsSafeToFold, /*InsnID*/3,
        GIM_CheckComplexPattern, /*MI*/1, /*Op*/1, /*Renderer*/GIMT_Encode2(0), GIMT_Encode2(GICP_gi_vop3mods),
        GIM_CheckComplexPattern, /*MI*/1, /*Op*/2, /*Renderer*/GIMT_Encode2(1), GIMT_Encode2(GICP_gi_vop3mods),
        GIM_CheckComplexPattern, /*MI*/2, /*Op*/2, /*Renderer*/GIMT_Encode2(2), GIMT_Encode2(GICP_gi_vop3mods),
        // (fminnum_ieee:{ *:[f32] } (fmaxnum:{ *:[f32] } (VOP3Mods:{ *:[f32] } f32:{ *:[f32] }:$src1, i32:{ *:[i32] }:$src1_mods), (VOP3Mods:{ *:[f32] } f32:{ *:[f32] }:$src0, i32:{ *:[i32] }:$src0_mods)), (fmaxnum:{ *:[f32] } (fminnum_ieee:{ *:[f32] } (VOP3Mods:{ *:[f32] } f32:{ *:[f32] }:$src1, i32:{ *:[i32] }:$src1_mods), (VOP3Mods:{ *:[f32] } f32:{ *:[f32] }:$src0, i32:{ *:[i32] }:$src0_mods)), (VOP3Mods:{ *:[f32] } f32:{ *:[f32] }:$src2, i32:{ *:[i32] }:$src2_mods)))<<P:Predicate_fminnum_like_nnan>>  =>  (V_MED3_F32_e64:{ *:[f32] } ?:{ *:[i32] }:$src0_mods, ?:{ *:[f32] }:$src0, ?:{ *:[i32] }:$src1_mods, ?:{ *:[f32] }:$src1, ?:{ *:[i32] }:$src2_mods, ?:{ *:[f32] }:$src2, 0:{ *:[i1] }, 0:{ *:[i32] })
        GIR_BuildMI, /*InsnID*/0, /*Opcode*/GIMT_Encode2(AMDGPU::V_MED3_F32_e64),
        GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/0, // DstI[vdst]
        GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(1), /*SubOperand*/1, // src0_mods
        GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(1), /*SubOperand*/0, // src0
        GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/1, // src1_mods
        GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/0, // src1
        GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(2), /*SubOperand*/1, // src2_mods
        GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(2), /*SubOperand*/0, // src2
        GIR_AddImm8, /*InsnID*/0, /*Imm*/0,
        GIR_AddImm8, /*InsnID*/0, /*Imm*/0,
        GIR_ConstrainSelectedInstOperands, /*InsnID*/0,
        GIR_EraseFromParent, /*InsnID*/0,
        // GIR_Coverage, 10334,
        GIR_Done,
      // Label 4786: @329757
      GIM_Try, /*On fail goto*//*Label 4787*/ GIMT_Encode4(329897), // Rule ID 10316 //
        GIM_CheckRegBankForClass, /*MI*/0, /*Op*/0, /*RC*/GIMT_Encode2(AMDGPU::VGPR_32RegClassID),
        GIM_RecordInsn, /*DefineMI*/1, /*MI*/0, /*OpIdx*/1, // MIs[1]
        GIM_CheckOpcode, /*MI*/1, GIMT_Encode2(TargetOpcode::G_FMAXNUM),
        GIM_CheckType, /*MI*/1, /*Op*/1, /*Type*/GILLT_s32,
        GIM_CheckType, /*MI*/1, /*Op*/2, /*Type*/GILLT_s32,
        GIM_RecordInsn, /*DefineMI*/2, /*MI*/0, /*OpIdx*/2, // MIs[2]
        GIM_CheckOpcode, /*MI*/2, GIMT_Encode2(TargetOpcode::G_FMAXNUM_IEEE),
        GIM_CheckType, /*MI*/2, /*Op*/1, /*Type*/GILLT_s32,
        GIM_CheckType, /*MI*/2, /*Op*/2, /*Type*/GILLT_s32,
        GIM_RecordInsn, /*DefineMI*/3, /*MI*/2, /*OpIdx*/2, // MIs[3]
        GIM_CheckOpcode, /*MI*/3, GIMT_Encode2(TargetOpcode::G_FMINNUM),
        // MIs[3] VOP3Mods:src0:src0_mods
        GIM_CheckIsSameOperand, /*MI*/3, /*OpIdx*/1, /*OtherMI*/1, /*OtherOpIdx*/1,
        // MIs[3] VOP3Mods:src1:src1_mods
        GIM_CheckIsSameOperand, /*MI*/3, /*OpIdx*/2, /*OtherMI*/1, /*OtherOpIdx*/2,
        GIM_CheckCxxInsnPredicate, /*MI*/0, /*FnId*/GIMT_Encode2(GICXXPred_MI_Predicate_fminnum_like_nnan),
        GIM_CheckIsSafeToFold, /*InsnID*/1,
        GIM_CheckIsSafeToFold, /*InsnID*/2,
        GIM_CheckIsSafeToFold, /*InsnID*/3,
        GIM_CheckComplexPattern, /*MI*/1, /*Op*/1, /*Renderer*/GIMT_Encode2(0), GIMT_Encode2(GICP_gi_vop3mods),
        GIM_CheckComplexPattern, /*MI*/1, /*Op*/2, /*Renderer*/GIMT_Encode2(1), GIMT_Encode2(GICP_gi_vop3mods),
        GIM_CheckComplexPattern, /*MI*/2, /*Op*/1, /*Renderer*/GIMT_Encode2(2), GIMT_Encode2(GICP_gi_vop3mods),
        // (fminnum_ieee:{ *:[f32] } (fmaxnum:{ *:[f32] } (VOP3Mods:{ *:[f32] } f32:{ *:[f32] }:$src0, i32:{ *:[i32] }:$src0_mods), (VOP3Mods:{ *:[f32] } f32:{ *:[f32] }:$src1, i32:{ *:[i32] }:$src1_mods)), (fmaxnum_ieee:{ *:[f32] } (VOP3Mods:{ *:[f32] } f32:{ *:[f32] }:$src2, i32:{ *:[i32] }:$src2_mods), (fminnum:{ *:[f32] } (VOP3Mods:{ *:[f32] } f32:{ *:[f32] }:$src0, i32:{ *:[i32] }:$src0_mods), (VOP3Mods:{ *:[f32] } f32:{ *:[f32] }:$src1, i32:{ *:[i32] }:$src1_mods))))<<P:Predicate_fminnum_like_nnan>>  =>  (V_MED3_F32_e64:{ *:[f32] } ?:{ *:[i32] }:$src0_mods, ?:{ *:[f32] }:$src0, ?:{ *:[i32] }:$src1_mods, ?:{ *:[f32] }:$src1, ?:{ *:[i32] }:$src2_mods, ?:{ *:[f32] }:$src2, 0:{ *:[i1] }, 0:{ *:[i32] })
        GIR_BuildMI, /*InsnID*/0, /*Opcode*/GIMT_Encode2(AMDGPU::V_MED3_F32_e64),
        GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/0, // DstI[vdst]
        GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/1, // src0_mods
        GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/0, // src0
        GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(1), /*SubOperand*/1, // src1_mods
        GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(1), /*SubOperand*/0, // src1
        GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(2), /*SubOperand*/1, // src2_mods
        GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(2), /*SubOperand*/0, // src2
        GIR_AddImm8, /*InsnID*/0, /*Imm*/0,
        GIR_AddImm8, /*InsnID*/0, /*Imm*/0,
        GIR_ConstrainSelectedInstOperands, /*InsnID*/0,
        GIR_EraseFromParent, /*InsnID*/0,
        // GIR_Coverage, 10316,
        GIR_Done,
      // Label 4787: @329897
      GIM_Try, /*On fail goto*//*Label 4788*/ GIMT_Encode4(330037), // Rule ID 10317 //
        GIM_CheckRegBankForClass, /*MI*/0, /*Op*/0, /*RC*/GIMT_Encode2(AMDGPU::VGPR_32RegClassID),
        GIM_RecordInsn, /*DefineMI*/1, /*MI*/0, /*OpIdx*/1, // MIs[1]
        GIM_CheckOpcode, /*MI*/1, GIMT_Encode2(TargetOpcode::G_FMAXNUM),
        GIM_CheckType, /*MI*/1, /*Op*/1, /*Type*/GILLT_s32,
        GIM_CheckType, /*MI*/1, /*Op*/2, /*Type*/GILLT_s32,
        GIM_RecordInsn, /*DefineMI*/2, /*MI*/0, /*OpIdx*/2, // MIs[2]
        GIM_CheckOpcode, /*MI*/2, GIMT_Encode2(TargetOpcode::G_FMAXNUM_IEEE),
        GIM_CheckType, /*MI*/2, /*Op*/1, /*Type*/GILLT_s32,
        GIM_CheckType, /*MI*/2, /*Op*/2, /*Type*/GILLT_s32,
        GIM_RecordInsn, /*DefineMI*/3, /*MI*/2, /*OpIdx*/2, // MIs[3]
        GIM_CheckOpcode, /*MI*/3, GIMT_Encode2(TargetOpcode::G_FMINNUM),
        // MIs[3] VOP3Mods:src1:src1_mods
        GIM_CheckIsSameOperand, /*MI*/3, /*OpIdx*/1, /*OtherMI*/1, /*OtherOpIdx*/2,
        // MIs[3] VOP3Mods:src0:src0_mods
        GIM_CheckIsSameOperand, /*MI*/3, /*OpIdx*/2, /*OtherMI*/1, /*OtherOpIdx*/1,
        GIM_CheckCxxInsnPredicate, /*MI*/0, /*FnId*/GIMT_Encode2(GICXXPred_MI_Predicate_fminnum_like_nnan),
        GIM_CheckIsSafeToFold, /*InsnID*/1,
        GIM_CheckIsSafeToFold, /*InsnID*/2,
        GIM_CheckIsSafeToFold, /*InsnID*/3,
        GIM_CheckComplexPattern, /*MI*/1, /*Op*/1, /*Renderer*/GIMT_Encode2(0), GIMT_Encode2(GICP_gi_vop3mods),
        GIM_CheckComplexPattern, /*MI*/1, /*Op*/2, /*Renderer*/GIMT_Encode2(1), GIMT_Encode2(GICP_gi_vop3mods),
        GIM_CheckComplexPattern, /*MI*/2, /*Op*/1, /*Renderer*/GIMT_Encode2(2), GIMT_Encode2(GICP_gi_vop3mods),
        // (fminnum_ieee:{ *:[f32] } (fmaxnum:{ *:[f32] } (VOP3Mods:{ *:[f32] } f32:{ *:[f32] }:$src0, i32:{ *:[i32] }:$src0_mods), (VOP3Mods:{ *:[f32] } f32:{ *:[f32] }:$src1, i32:{ *:[i32] }:$src1_mods)), (fmaxnum_ieee:{ *:[f32] } (VOP3Mods:{ *:[f32] } f32:{ *:[f32] }:$src2, i32:{ *:[i32] }:$src2_mods), (fminnum:{ *:[f32] } (VOP3Mods:{ *:[f32] } f32:{ *:[f32] }:$src1, i32:{ *:[i32] }:$src1_mods), (VOP3Mods:{ *:[f32] } f32:{ *:[f32] }:$src0, i32:{ *:[i32] }:$src0_mods))))<<P:Predicate_fminnum_like_nnan>>  =>  (V_MED3_F32_e64:{ *:[f32] } ?:{ *:[i32] }:$src0_mods, ?:{ *:[f32] }:$src0, ?:{ *:[i32] }:$src1_mods, ?:{ *:[f32] }:$src1, ?:{ *:[i32] }:$src2_mods, ?:{ *:[f32] }:$src2, 0:{ *:[i1] }, 0:{ *:[i32] })
        GIR_BuildMI, /*InsnID*/0, /*Opcode*/GIMT_Encode2(AMDGPU::V_MED3_F32_e64),
        GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/0, // DstI[vdst]
        GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/1, // src0_mods
        GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/0, // src0
        GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(1), /*SubOperand*/1, // src1_mods
        GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(1), /*SubOperand*/0, // src1
        GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(2), /*SubOperand*/1, // src2_mods
        GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(2), /*SubOperand*/0, // src2
        GIR_AddImm8, /*InsnID*/0, /*Imm*/0,
        GIR_AddImm8, /*InsnID*/0, /*Imm*/0,
        GIR_ConstrainSelectedInstOperands, /*InsnID*/0,
        GIR_EraseFromParent, /*InsnID*/0,
        // GIR_Coverage, 10317,
        GIR_Done,
      // Label 4788: @330037
      GIM_Try, /*On fail goto*//*Label 4789*/ GIMT_Encode4(330177), // Rule ID 10320 //
        GIM_CheckRegBankForClass, /*MI*/0, /*Op*/0, /*RC*/GIMT_Encode2(AMDGPU::VGPR_32RegClassID),
        GIM_RecordInsn, /*DefineMI*/1, /*MI*/0, /*OpIdx*/1, // MIs[1]
        GIM_CheckOpcode, /*MI*/1, GIMT_Encode2(TargetOpcode::G_FMAXNUM),
        GIM_CheckType, /*MI*/1, /*Op*/1, /*Type*/GILLT_s32,
        GIM_CheckType, /*MI*/1, /*Op*/2, /*Type*/GILLT_s32,
        GIM_RecordInsn, /*DefineMI*/2, /*MI*/0, /*OpIdx*/2, // MIs[2]
        GIM_CheckOpcode, /*MI*/2, GIMT_Encode2(TargetOpcode::G_FMAXNUM_IEEE),
        GIM_CheckType, /*MI*/2, /*Op*/1, /*Type*/GILLT_s32,
        GIM_CheckType, /*MI*/2, /*Op*/2, /*Type*/GILLT_s32,
        GIM_RecordInsn, /*DefineMI*/3, /*MI*/2, /*OpIdx*/2, // MIs[3]
        GIM_CheckOpcode, /*MI*/3, GIMT_Encode2(TargetOpcode::G_FMINNUM),
        // MIs[3] VOP3Mods:src0:src0_mods
        GIM_CheckIsSameOperand, /*MI*/3, /*OpIdx*/1, /*OtherMI*/1, /*OtherOpIdx*/2,
        // MIs[3] VOP3Mods:src1:src1_mods
        GIM_CheckIsSameOperand, /*MI*/3, /*OpIdx*/2, /*OtherMI*/1, /*OtherOpIdx*/1,
        GIM_CheckCxxInsnPredicate, /*MI*/0, /*FnId*/GIMT_Encode2(GICXXPred_MI_Predicate_fminnum_like_nnan),
        GIM_CheckIsSafeToFold, /*InsnID*/1,
        GIM_CheckIsSafeToFold, /*InsnID*/2,
        GIM_CheckIsSafeToFold, /*InsnID*/3,
        GIM_CheckComplexPattern, /*MI*/1, /*Op*/1, /*Renderer*/GIMT_Encode2(0), GIMT_Encode2(GICP_gi_vop3mods),
        GIM_CheckComplexPattern, /*MI*/1, /*Op*/2, /*Renderer*/GIMT_Encode2(1), GIMT_Encode2(GICP_gi_vop3mods),
        GIM_CheckComplexPattern, /*MI*/2, /*Op*/1, /*Renderer*/GIMT_Encode2(2), GIMT_Encode2(GICP_gi_vop3mods),
        // (fminnum_ieee:{ *:[f32] } (fmaxnum:{ *:[f32] } (VOP3Mods:{ *:[f32] } f32:{ *:[f32] }:$src1, i32:{ *:[i32] }:$src1_mods), (VOP3Mods:{ *:[f32] } f32:{ *:[f32] }:$src0, i32:{ *:[i32] }:$src0_mods)), (fmaxnum_ieee:{ *:[f32] } (VOP3Mods:{ *:[f32] } f32:{ *:[f32] }:$src2, i32:{ *:[i32] }:$src2_mods), (fminnum:{ *:[f32] } (VOP3Mods:{ *:[f32] } f32:{ *:[f32] }:$src0, i32:{ *:[i32] }:$src0_mods), (VOP3Mods:{ *:[f32] } f32:{ *:[f32] }:$src1, i32:{ *:[i32] }:$src1_mods))))<<P:Predicate_fminnum_like_nnan>>  =>  (V_MED3_F32_e64:{ *:[f32] } ?:{ *:[i32] }:$src0_mods, ?:{ *:[f32] }:$src0, ?:{ *:[i32] }:$src1_mods, ?:{ *:[f32] }:$src1, ?:{ *:[i32] }:$src2_mods, ?:{ *:[f32] }:$src2, 0:{ *:[i1] }, 0:{ *:[i32] })
        GIR_BuildMI, /*InsnID*/0, /*Opcode*/GIMT_Encode2(AMDGPU::V_MED3_F32_e64),
        GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/0, // DstI[vdst]
        GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(1), /*SubOperand*/1, // src0_mods
        GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(1), /*SubOperand*/0, // src0
        GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/1, // src1_mods
        GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/0, // src1
        GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(2), /*SubOperand*/1, // src2_mods
        GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(2), /*SubOperand*/0, // src2
        GIR_AddImm8, /*InsnID*/0, /*Imm*/0,
        GIR_AddImm8, /*InsnID*/0, /*Imm*/0,
        GIR_ConstrainSelectedInstOperands, /*InsnID*/0,
        GIR_EraseFromParent, /*InsnID*/0,
        // GIR_Coverage, 10320,
        GIR_Done,
      // Label 4789: @330177
      GIM_Try, /*On fail goto*//*Label 4790*/ GIMT_Encode4(330317), // Rule ID 10321 //
        GIM_CheckRegBankForClass, /*MI*/0, /*Op*/0, /*RC*/GIMT_Encode2(AMDGPU::VGPR_32RegClassID),
        GIM_RecordInsn, /*DefineMI*/1, /*MI*/0, /*OpIdx*/1, // MIs[1]
        GIM_CheckOpcode, /*MI*/1, GIMT_Encode2(TargetOpcode::G_FMAXNUM),
        GIM_CheckType, /*MI*/1, /*Op*/1, /*Type*/GILLT_s32,
        GIM_CheckType, /*MI*/1, /*Op*/2, /*Type*/GILLT_s32,
        GIM_RecordInsn, /*DefineMI*/2, /*MI*/0, /*OpIdx*/2, // MIs[2]
        GIM_CheckOpcode, /*MI*/2, GIMT_Encode2(TargetOpcode::G_FMAXNUM_IEEE),
        GIM_CheckType, /*MI*/2, /*Op*/1, /*Type*/GILLT_s32,
        GIM_CheckType, /*MI*/2, /*Op*/2, /*Type*/GILLT_s32,
        GIM_RecordInsn, /*DefineMI*/3, /*MI*/2, /*OpIdx*/2, // MIs[3]
        GIM_CheckOpcode, /*MI*/3, GIMT_Encode2(TargetOpcode::G_FMINNUM),
        // MIs[3] VOP3Mods:src1:src1_mods
        GIM_CheckIsSameOperand, /*MI*/3, /*OpIdx*/1, /*OtherMI*/1, /*OtherOpIdx*/1,
        // MIs[3] VOP3Mods:src0:src0_mods
        GIM_CheckIsSameOperand, /*MI*/3, /*OpIdx*/2, /*OtherMI*/1, /*OtherOpIdx*/2,
        GIM_CheckCxxInsnPredicate, /*MI*/0, /*FnId*/GIMT_Encode2(GICXXPred_MI_Predicate_fminnum_like_nnan),
        GIM_CheckIsSafeToFold, /*InsnID*/1,
        GIM_CheckIsSafeToFold, /*InsnID*/2,
        GIM_CheckIsSafeToFold, /*InsnID*/3,
        GIM_CheckComplexPattern, /*MI*/1, /*Op*/1, /*Renderer*/GIMT_Encode2(0), GIMT_Encode2(GICP_gi_vop3mods),
        GIM_CheckComplexPattern, /*MI*/1, /*Op*/2, /*Renderer*/GIMT_Encode2(1), GIMT_Encode2(GICP_gi_vop3mods),
        GIM_CheckComplexPattern, /*MI*/2, /*Op*/1, /*Renderer*/GIMT_Encode2(2), GIMT_Encode2(GICP_gi_vop3mods),
        // (fminnum_ieee:{ *:[f32] } (fmaxnum:{ *:[f32] } (VOP3Mods:{ *:[f32] } f32:{ *:[f32] }:$src1, i32:{ *:[i32] }:$src1_mods), (VOP3Mods:{ *:[f32] } f32:{ *:[f32] }:$src0, i32:{ *:[i32] }:$src0_mods)), (fmaxnum_ieee:{ *:[f32] } (VOP3Mods:{ *:[f32] } f32:{ *:[f32] }:$src2, i32:{ *:[i32] }:$src2_mods), (fminnum:{ *:[f32] } (VOP3Mods:{ *:[f32] } f32:{ *:[f32] }:$src1, i32:{ *:[i32] }:$src1_mods), (VOP3Mods:{ *:[f32] } f32:{ *:[f32] }:$src0, i32:{ *:[i32] }:$src0_mods))))<<P:Predicate_fminnum_like_nnan>>  =>  (V_MED3_F32_e64:{ *:[f32] } ?:{ *:[i32] }:$src0_mods, ?:{ *:[f32] }:$src0, ?:{ *:[i32] }:$src1_mods, ?:{ *:[f32] }:$src1, ?:{ *:[i32] }:$src2_mods, ?:{ *:[f32] }:$src2, 0:{ *:[i1] }, 0:{ *:[i32] })
        GIR_BuildMI, /*InsnID*/0, /*Opcode*/GIMT_Encode2(AMDGPU::V_MED3_F32_e64),
        GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/0, // DstI[vdst]
        GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(1), /*SubOperand*/1, // src0_mods
        GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(1), /*SubOperand*/0, // src0
        GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/1, // src1_mods
        GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/0, // src1
        GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(2), /*SubOperand*/1, // src2_mods
        GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(2), /*SubOperand*/0, // src2
        GIR_AddImm8, /*InsnID*/0, /*Imm*/0,
        GIR_AddImm8, /*InsnID*/0, /*Imm*/0,
        GIR_ConstrainSelectedInstOperands, /*InsnID*/0,
        GIR_EraseFromParent, /*InsnID*/0,
        // GIR_Coverage, 10321,
        GIR_Done,
      // Label 4790: @330317
      GIM_Try, /*On fail goto*//*Label 4791*/ GIMT_Encode4(330457), // Rule ID 10301 //
        GIM_CheckRegBankForClass, /*MI*/0, /*Op*/0, /*RC*/GIMT_Encode2(AMDGPU::VGPR_32RegClassID),
        GIM_RecordInsn, /*DefineMI*/1, /*MI*/0, /*OpIdx*/1, // MIs[1]
        GIM_CheckOpcode, /*MI*/1, GIMT_Encode2(TargetOpcode::G_FMAXNUM),
        GIM_CheckType, /*MI*/1, /*Op*/1, /*Type*/GILLT_s32,
        GIM_CheckType, /*MI*/1, /*Op*/2, /*Type*/GILLT_s32,
        GIM_RecordInsn, /*DefineMI*/2, /*MI*/0, /*OpIdx*/2, // MIs[2]
        GIM_CheckOpcode, /*MI*/2, GIMT_Encode2(TargetOpcode::G_FMAXNUM_IEEE),
        GIM_CheckType, /*MI*/2, /*Op*/1, /*Type*/GILLT_s32,
        GIM_CheckType, /*MI*/2, /*Op*/2, /*Type*/GILLT_s32,
        GIM_RecordInsn, /*DefineMI*/3, /*MI*/2, /*OpIdx*/2, // MIs[3]
        GIM_CheckOpcode, /*MI*/3, GIMT_Encode2(TargetOpcode::G_FMINNUM_IEEE),
        // MIs[3] VOP3Mods:src0:src0_mods
        GIM_CheckIsSameOperand, /*MI*/3, /*OpIdx*/1, /*OtherMI*/1, /*OtherOpIdx*/1,
        // MIs[3] VOP3Mods:src1:src1_mods
        GIM_CheckIsSameOperand, /*MI*/3, /*OpIdx*/2, /*OtherMI*/1, /*OtherOpIdx*/2,
        GIM_CheckCxxInsnPredicate, /*MI*/0, /*FnId*/GIMT_Encode2(GICXXPred_MI_Predicate_fminnum_like_nnan),
        GIM_CheckIsSafeToFold, /*InsnID*/1,
        GIM_CheckIsSafeToFold, /*InsnID*/2,
        GIM_CheckIsSafeToFold, /*InsnID*/3,
        GIM_CheckComplexPattern, /*MI*/1, /*Op*/1, /*Renderer*/GIMT_Encode2(0), GIMT_Encode2(GICP_gi_vop3mods),
        GIM_CheckComplexPattern, /*MI*/1, /*Op*/2, /*Renderer*/GIMT_Encode2(1), GIMT_Encode2(GICP_gi_vop3mods),
        GIM_CheckComplexPattern, /*MI*/2, /*Op*/1, /*Renderer*/GIMT_Encode2(2), GIMT_Encode2(GICP_gi_vop3mods),
        // (fminnum_ieee:{ *:[f32] } (fmaxnum:{ *:[f32] } (VOP3Mods:{ *:[f32] } f32:{ *:[f32] }:$src0, i32:{ *:[i32] }:$src0_mods), (VOP3Mods:{ *:[f32] } f32:{ *:[f32] }:$src1, i32:{ *:[i32] }:$src1_mods)), (fmaxnum_ieee:{ *:[f32] } (VOP3Mods:{ *:[f32] } f32:{ *:[f32] }:$src2, i32:{ *:[i32] }:$src2_mods), (fminnum_ieee:{ *:[f32] } (VOP3Mods:{ *:[f32] } f32:{ *:[f32] }:$src0, i32:{ *:[i32] }:$src0_mods), (VOP3Mods:{ *:[f32] } f32:{ *:[f32] }:$src1, i32:{ *:[i32] }:$src1_mods))))<<P:Predicate_fminnum_like_nnan>>  =>  (V_MED3_F32_e64:{ *:[f32] } ?:{ *:[i32] }:$src0_mods, ?:{ *:[f32] }:$src0, ?:{ *:[i32] }:$src1_mods, ?:{ *:[f32] }:$src1, ?:{ *:[i32] }:$src2_mods, ?:{ *:[f32] }:$src2, 0:{ *:[i1] }, 0:{ *:[i32] })
        GIR_BuildMI, /*InsnID*/0, /*Opcode*/GIMT_Encode2(AMDGPU::V_MED3_F32_e64),
        GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/0, // DstI[vdst]
        GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/1, // src0_mods
        GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/0, // src0
        GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(1), /*SubOperand*/1, // src1_mods
        GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(1), /*SubOperand*/0, // src1
        GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(2), /*SubOperand*/1, // src2_mods
        GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(2), /*SubOperand*/0, // src2
        GIR_AddImm8, /*InsnID*/0, /*Imm*/0,
        GIR_AddImm8, /*InsnID*/0, /*Imm*/0,
        GIR_ConstrainSelectedInstOperands, /*InsnID*/0,
        GIR_EraseFromParent, /*InsnID*/0,
        // GIR_Coverage, 10301,
        GIR_Done,
      // Label 4791: @330457
      GIM_Try, /*On fail goto*//*Label 4792*/ GIMT_Encode4(330597), // Rule ID 10302 //
        GIM_CheckRegBankForClass, /*MI*/0, /*Op*/0, /*RC*/GIMT_Encode2(AMDGPU::VGPR_32RegClassID),
        GIM_RecordInsn, /*DefineMI*/1, /*MI*/0, /*OpIdx*/1, // MIs[1]
        GIM_CheckOpcode, /*MI*/1, GIMT_Encode2(TargetOpcode::G_FMAXNUM),
        GIM_CheckType, /*MI*/1, /*Op*/1, /*Type*/GILLT_s32,
        GIM_CheckType, /*MI*/1, /*Op*/2, /*Type*/GILLT_s32,
        GIM_RecordInsn, /*DefineMI*/2, /*MI*/0, /*OpIdx*/2, // MIs[2]
        GIM_CheckOpcode, /*MI*/2, GIMT_Encode2(TargetOpcode::G_FMAXNUM_IEEE),
        GIM_CheckType, /*MI*/2, /*Op*/1, /*Type*/GILLT_s32,
        GIM_CheckType, /*MI*/2, /*Op*/2, /*Type*/GILLT_s32,
        GIM_RecordInsn, /*DefineMI*/3, /*MI*/2, /*OpIdx*/2, // MIs[3]
        GIM_CheckOpcode, /*MI*/3, GIMT_Encode2(TargetOpcode::G_FMINNUM_IEEE),
        // MIs[3] VOP3Mods:src1:src1_mods
        GIM_CheckIsSameOperand, /*MI*/3, /*OpIdx*/1, /*OtherMI*/1, /*OtherOpIdx*/2,
        // MIs[3] VOP3Mods:src0:src0_mods
        GIM_CheckIsSameOperand, /*MI*/3, /*OpIdx*/2, /*OtherMI*/1, /*OtherOpIdx*/1,
        GIM_CheckCxxInsnPredicate, /*MI*/0, /*FnId*/GIMT_Encode2(GICXXPred_MI_Predicate_fminnum_like_nnan),
        GIM_CheckIsSafeToFold, /*InsnID*/1,
        GIM_CheckIsSafeToFold, /*InsnID*/2,
        GIM_CheckIsSafeToFold, /*InsnID*/3,
        GIM_CheckComplexPattern, /*MI*/1, /*Op*/1, /*Renderer*/GIMT_Encode2(0), GIMT_Encode2(GICP_gi_vop3mods),
        GIM_CheckComplexPattern, /*MI*/1, /*Op*/2, /*Renderer*/GIMT_Encode2(1), GIMT_Encode2(GICP_gi_vop3mods),
        GIM_CheckComplexPattern, /*MI*/2, /*Op*/1, /*Renderer*/GIMT_Encode2(2), GIMT_Encode2(GICP_gi_vop3mods),
        // (fminnum_ieee:{ *:[f32] } (fmaxnum:{ *:[f32] } (VOP3Mods:{ *:[f32] } f32:{ *:[f32] }:$src0, i32:{ *:[i32] }:$src0_mods), (VOP3Mods:{ *:[f32] } f32:{ *:[f32] }:$src1, i32:{ *:[i32] }:$src1_mods)), (fmaxnum_ieee:{ *:[f32] } (VOP3Mods:{ *:[f32] } f32:{ *:[f32] }:$src2, i32:{ *:[i32] }:$src2_mods), (fminnum_ieee:{ *:[f32] } (VOP3Mods:{ *:[f32] } f32:{ *:[f32] }:$src1, i32:{ *:[i32] }:$src1_mods), (VOP3Mods:{ *:[f32] } f32:{ *:[f32] }:$src0, i32:{ *:[i32] }:$src0_mods))))<<P:Predicate_fminnum_like_nnan>>  =>  (V_MED3_F32_e64:{ *:[f32] } ?:{ *:[i32] }:$src0_mods, ?:{ *:[f32] }:$src0, ?:{ *:[i32] }:$src1_mods, ?:{ *:[f32] }:$src1, ?:{ *:[i32] }:$src2_mods, ?:{ *:[f32] }:$src2, 0:{ *:[i1] }, 0:{ *:[i32] })
        GIR_BuildMI, /*InsnID*/0, /*Opcode*/GIMT_Encode2(AMDGPU::V_MED3_F32_e64),
        GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/0, // DstI[vdst]
        GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/1, // src0_mods
        GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/0, // src0
        GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(1), /*SubOperand*/1, // src1_mods
        GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(1), /*SubOperand*/0, // src1
        GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(2), /*SubOperand*/1, // src2_mods
        GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(2), /*SubOperand*/0, // src2
        GIR_AddImm8, /*InsnID*/0, /*Imm*/0,
        GIR_AddImm8, /*InsnID*/0, /*Imm*/0,
        GIR_ConstrainSelectedInstOperands, /*InsnID*/0,
        GIR_EraseFromParent, /*InsnID*/0,
        // GIR_Coverage, 10302,
        GIR_Done,
      // Label 4792: @330597
      GIM_Try, /*On fail goto*//*Label 4793*/ GIMT_Encode4(330737), // Rule ID 10305 //
        GIM_CheckRegBankForClass, /*MI*/0, /*Op*/0, /*RC*/GIMT_Encode2(AMDGPU::VGPR_32RegClassID),
        GIM_RecordInsn, /*DefineMI*/1, /*MI*/0, /*OpIdx*/1, // MIs[1]
        GIM_CheckOpcode, /*MI*/1, GIMT_Encode2(TargetOpcode::G_FMAXNUM),
        GIM_CheckType, /*MI*/1, /*Op*/1, /*Type*/GILLT_s32,
        GIM_CheckType, /*MI*/1, /*Op*/2, /*Type*/GILLT_s32,
        GIM_RecordInsn, /*DefineMI*/2, /*MI*/0, /*OpIdx*/2, // MIs[2]
        GIM_CheckOpcode, /*MI*/2, GIMT_Encode2(TargetOpcode::G_FMAXNUM_IEEE),
        GIM_CheckType, /*MI*/2, /*Op*/1, /*Type*/GILLT_s32,
        GIM_CheckType, /*MI*/2, /*Op*/2, /*Type*/GILLT_s32,
        GIM_RecordInsn, /*DefineMI*/3, /*MI*/2, /*OpIdx*/2, // MIs[3]
        GIM_CheckOpcode, /*MI*/3, GIMT_Encode2(TargetOpcode::G_FMINNUM_IEEE),
        // MIs[3] VOP3Mods:src0:src0_mods
        GIM_CheckIsSameOperand, /*MI*/3, /*OpIdx*/1, /*OtherMI*/1, /*OtherOpIdx*/2,
        // MIs[3] VOP3Mods:src1:src1_mods
        GIM_CheckIsSameOperand, /*MI*/3, /*OpIdx*/2, /*OtherMI*/1, /*OtherOpIdx*/1,
        GIM_CheckCxxInsnPredicate, /*MI*/0, /*FnId*/GIMT_Encode2(GICXXPred_MI_Predicate_fminnum_like_nnan),
        GIM_CheckIsSafeToFold, /*InsnID*/1,
        GIM_CheckIsSafeToFold, /*InsnID*/2,
        GIM_CheckIsSafeToFold, /*InsnID*/3,
        GIM_CheckComplexPattern, /*MI*/1, /*Op*/1, /*Renderer*/GIMT_Encode2(0), GIMT_Encode2(GICP_gi_vop3mods),
        GIM_CheckComplexPattern, /*MI*/1, /*Op*/2, /*Renderer*/GIMT_Encode2(1), GIMT_Encode2(GICP_gi_vop3mods),
        GIM_CheckComplexPattern, /*MI*/2, /*Op*/1, /*Renderer*/GIMT_Encode2(2), GIMT_Encode2(GICP_gi_vop3mods),
        // (fminnum_ieee:{ *:[f32] } (fmaxnum:{ *:[f32] } (VOP3Mods:{ *:[f32] } f32:{ *:[f32] }:$src1, i32:{ *:[i32] }:$src1_mods), (VOP3Mods:{ *:[f32] } f32:{ *:[f32] }:$src0, i32:{ *:[i32] }:$src0_mods)), (fmaxnum_ieee:{ *:[f32] } (VOP3Mods:{ *:[f32] } f32:{ *:[f32] }:$src2, i32:{ *:[i32] }:$src2_mods), (fminnum_ieee:{ *:[f32] } (VOP3Mods:{ *:[f32] } f32:{ *:[f32] }:$src0, i32:{ *:[i32] }:$src0_mods), (VOP3Mods:{ *:[f32] } f32:{ *:[f32] }:$src1, i32:{ *:[i32] }:$src1_mods))))<<P:Predicate_fminnum_like_nnan>>  =>  (V_MED3_F32_e64:{ *:[f32] } ?:{ *:[i32] }:$src0_mods, ?:{ *:[f32] }:$src0, ?:{ *:[i32] }:$src1_mods, ?:{ *:[f32] }:$src1, ?:{ *:[i32] }:$src2_mods, ?:{ *:[f32] }:$src2, 0:{ *:[i1] }, 0:{ *:[i32] })
        GIR_BuildMI, /*InsnID*/0, /*Opcode*/GIMT_Encode2(AMDGPU::V_MED3_F32_e64),
        GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/0, // DstI[vdst]
        GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(1), /*SubOperand*/1, // src0_mods
        GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(1), /*SubOperand*/0, // src0
        GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/1, // src1_mods
        GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/0, // src1
        GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(2), /*SubOperand*/1, // src2_mods
        GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(2), /*SubOperand*/0, // src2
        GIR_AddImm8, /*InsnID*/0, /*Imm*/0,
        GIR_AddImm8, /*InsnID*/0, /*Imm*/0,
        GIR_ConstrainSelectedInstOperands, /*InsnID*/0,
        GIR_EraseFromParent, /*InsnID*/0,
        // GIR_Coverage, 10305,
        GIR_Done,
      // Label 4793: @330737
      GIM_Try, /*On fail goto*//*Label 4794*/ GIMT_Encode4(330877), // Rule ID 10306 //
        GIM_CheckRegBankForClass, /*MI*/0, /*Op*/0, /*RC*/GIMT_Encode2(AMDGPU::VGPR_32RegClassID),
        GIM_RecordInsn, /*DefineMI*/1, /*MI*/0, /*OpIdx*/1, // MIs[1]
        GIM_CheckOpcode, /*MI*/1, GIMT_Encode2(TargetOpcode::G_FMAXNUM),
        GIM_CheckType, /*MI*/1, /*Op*/1, /*Type*/GILLT_s32,
        GIM_CheckType, /*MI*/1, /*Op*/2, /*Type*/GILLT_s32,
        GIM_RecordInsn, /*DefineMI*/2, /*MI*/0, /*OpIdx*/2, // MIs[2]
        GIM_CheckOpcode, /*MI*/2, GIMT_Encode2(TargetOpcode::G_FMAXNUM_IEEE),
        GIM_CheckType, /*MI*/2, /*Op*/1, /*Type*/GILLT_s32,
        GIM_CheckType, /*MI*/2, /*Op*/2, /*Type*/GILLT_s32,
        GIM_RecordInsn, /*DefineMI*/3, /*MI*/2, /*OpIdx*/2, // MIs[3]
        GIM_CheckOpcode, /*MI*/3, GIMT_Encode2(TargetOpcode::G_FMINNUM_IEEE),
        // MIs[3] VOP3Mods:src1:src1_mods
        GIM_CheckIsSameOperand, /*MI*/3, /*OpIdx*/1, /*OtherMI*/1, /*OtherOpIdx*/1,
        // MIs[3] VOP3Mods:src0:src0_mods
        GIM_CheckIsSameOperand, /*MI*/3, /*OpIdx*/2, /*OtherMI*/1, /*OtherOpIdx*/2,
        GIM_CheckCxxInsnPredicate, /*MI*/0, /*FnId*/GIMT_Encode2(GICXXPred_MI_Predicate_fminnum_like_nnan),
        GIM_CheckIsSafeToFold, /*InsnID*/1,
        GIM_CheckIsSafeToFold, /*InsnID*/2,
        GIM_CheckIsSafeToFold, /*InsnID*/3,
        GIM_CheckComplexPattern, /*MI*/1, /*Op*/1, /*Renderer*/GIMT_Encode2(0), GIMT_Encode2(GICP_gi_vop3mods),
        GIM_CheckComplexPattern, /*MI*/1, /*Op*/2, /*Renderer*/GIMT_Encode2(1), GIMT_Encode2(GICP_gi_vop3mods),
        GIM_CheckComplexPattern, /*MI*/2, /*Op*/1, /*Renderer*/GIMT_Encode2(2), GIMT_Encode2(GICP_gi_vop3mods),
        // (fminnum_ieee:{ *:[f32] } (fmaxnum:{ *:[f32] } (VOP3Mods:{ *:[f32] } f32:{ *:[f32] }:$src1, i32:{ *:[i32] }:$src1_mods), (VOP3Mods:{ *:[f32] } f32:{ *:[f32] }:$src0, i32:{ *:[i32] }:$src0_mods)), (fmaxnum_ieee:{ *:[f32] } (VOP3Mods:{ *:[f32] } f32:{ *:[f32] }:$src2, i32:{ *:[i32] }:$src2_mods), (fminnum_ieee:{ *:[f32] } (VOP3Mods:{ *:[f32] } f32:{ *:[f32] }:$src1, i32:{ *:[i32] }:$src1_mods), (VOP3Mods:{ *:[f32] } f32:{ *:[f32] }:$src0, i32:{ *:[i32] }:$src0_mods))))<<P:Predicate_fminnum_like_nnan>>  =>  (V_MED3_F32_e64:{ *:[f32] } ?:{ *:[i32] }:$src0_mods, ?:{ *:[f32] }:$src0, ?:{ *:[i32] }:$src1_mods, ?:{ *:[f32] }:$src1, ?:{ *:[i32] }:$src2_mods, ?:{ *:[f32] }:$src2, 0:{ *:[i1] }, 0:{ *:[i32] })
        GIR_BuildMI, /*InsnID*/0, /*Opcode*/GIMT_Encode2(AMDGPU::V_MED3_F32_e64),
        GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/0, // DstI[vdst]
        GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(1), /*SubOperand*/1, // src0_mods
        GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(1), /*SubOperand*/0, // src0
        GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/1, // src1_mods
        GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/0, // src1
        GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(2), /*SubOperand*/1, // src2_mods
        GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(2), /*SubOperand*/0, // src2
        GIR_AddImm8, /*InsnID*/0, /*Imm*/0,
        GIR_AddImm8, /*InsnID*/0, /*Imm*/0,
        GIR_ConstrainSelectedInstOperands, /*InsnID*/0,
        GIR_EraseFromParent, /*InsnID*/0,
        // GIR_Coverage, 10306,
        GIR_Done,
      // Label 4794: @330877
      GIM_Try, /*On fail goto*//*Label 4795*/ GIMT_Encode4(331017), // Rule ID 6503 //
        GIM_CheckRegBankForClass, /*MI*/0, /*Op*/0, /*RC*/GIMT_Encode2(AMDGPU::VGPR_32RegClassID),
        GIM_RecordInsn, /*DefineMI*/1, /*MI*/0, /*OpIdx*/1, // MIs[1]
        GIM_CheckOpcode, /*MI*/1, GIMT_Encode2(TargetOpcode::G_FMAXNUM),
        GIM_CheckType, /*MI*/1, /*Op*/1, /*Type*/GILLT_s32,
        GIM_CheckType, /*MI*/1, /*Op*/2, /*Type*/GILLT_s32,
        GIM_RecordInsn, /*DefineMI*/2, /*MI*/0, /*OpIdx*/2, // MIs[2]
        GIM_CheckOpcode, /*MI*/2, GIMT_Encode2(TargetOpcode::G_FMAXNUM_IEEE),
        GIM_CheckType, /*MI*/2, /*Op*/1, /*Type*/GILLT_s32,
        GIM_CheckType, /*MI*/2, /*Op*/2, /*Type*/GILLT_s32,
        GIM_RecordInsn, /*DefineMI*/3, /*MI*/2, /*OpIdx*/1, // MIs[3]
        GIM_CheckOpcode, /*MI*/3, GIMT_Encode2(TargetOpcode::G_FMINNUM),
        // MIs[3] VOP3Mods:src0:src0_mods
        GIM_CheckIsSameOperand, /*MI*/3, /*OpIdx*/1, /*OtherMI*/1, /*OtherOpIdx*/1,
        // MIs[3] VOP3Mods:src1:src1_mods
        GIM_CheckIsSameOperand, /*MI*/3, /*OpIdx*/2, /*OtherMI*/1, /*OtherOpIdx*/2,
        GIM_CheckCxxInsnPredicate, /*MI*/0, /*FnId*/GIMT_Encode2(GICXXPred_MI_Predicate_fminnum_like_nnan),
        GIM_CheckIsSafeToFold, /*InsnID*/1,
        GIM_CheckIsSafeToFold, /*InsnID*/2,
        GIM_CheckIsSafeToFold, /*InsnID*/3,
        GIM_CheckComplexPattern, /*MI*/1, /*Op*/1, /*Renderer*/GIMT_Encode2(0), GIMT_Encode2(GICP_gi_vop3mods),
        GIM_CheckComplexPattern, /*MI*/1, /*Op*/2, /*Renderer*/GIMT_Encode2(1), GIMT_Encode2(GICP_gi_vop3mods),
        GIM_CheckComplexPattern, /*MI*/2, /*Op*/2, /*Renderer*/GIMT_Encode2(2), GIMT_Encode2(GICP_gi_vop3mods),
        // (fminnum_ieee:{ *:[f32] } (fmaxnum:{ *:[f32] } (VOP3Mods:{ *:[f32] } f32:{ *:[f32] }:$src0, i32:{ *:[i32] }:$src0_mods), (VOP3Mods:{ *:[f32] } f32:{ *:[f32] }:$src1, i32:{ *:[i32] }:$src1_mods)), (fmaxnum_ieee:{ *:[f32] } (fminnum:{ *:[f32] } (VOP3Mods:{ *:[f32] } f32:{ *:[f32] }:$src0, i32:{ *:[i32] }:$src0_mods), (VOP3Mods:{ *:[f32] } f32:{ *:[f32] }:$src1, i32:{ *:[i32] }:$src1_mods)), (VOP3Mods:{ *:[f32] } f32:{ *:[f32] }:$src2, i32:{ *:[i32] }:$src2_mods)))<<P:Predicate_fminnum_like_nnan>>  =>  (V_MED3_F32_e64:{ *:[f32] } ?:{ *:[i32] }:$src0_mods, ?:{ *:[f32] }:$src0, ?:{ *:[i32] }:$src1_mods, ?:{ *:[f32] }:$src1, ?:{ *:[i32] }:$src2_mods, ?:{ *:[f32] }:$src2, 0:{ *:[i1] }, 0:{ *:[i32] })
        GIR_BuildMI, /*InsnID*/0, /*Opcode*/GIMT_Encode2(AMDGPU::V_MED3_F32_e64),
        GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/0, // DstI[vdst]
        GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/1, // src0_mods
        GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/0, // src0
        GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(1), /*SubOperand*/1, // src1_mods
        GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(1), /*SubOperand*/0, // src1
        GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(2), /*SubOperand*/1, // src2_mods
        GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(2), /*SubOperand*/0, // src2
        GIR_AddImm8, /*InsnID*/0, /*Imm*/0,
        GIR_AddImm8, /*InsnID*/0, /*Imm*/0,
        GIR_ConstrainSelectedInstOperands, /*InsnID*/0,
        GIR_EraseFromParent, /*InsnID*/0,
        // GIR_Coverage, 6503,
        GIR_Done,
      // Label 4795: @331017
      GIM_Try, /*On fail goto*//*Label 4796*/ GIMT_Encode4(331157), // Rule ID 10315 //
        GIM_CheckRegBankForClass, /*MI*/0, /*Op*/0, /*RC*/GIMT_Encode2(AMDGPU::VGPR_32RegClassID),
        GIM_RecordInsn, /*DefineMI*/1, /*MI*/0, /*OpIdx*/1, // MIs[1]
        GIM_CheckOpcode, /*MI*/1, GIMT_Encode2(TargetOpcode::G_FMAXNUM),
        GIM_CheckType, /*MI*/1, /*Op*/1, /*Type*/GILLT_s32,
        GIM_CheckType, /*MI*/1, /*Op*/2, /*Type*/GILLT_s32,
        GIM_RecordInsn, /*DefineMI*/2, /*MI*/0, /*OpIdx*/2, // MIs[2]
        GIM_CheckOpcode, /*MI*/2, GIMT_Encode2(TargetOpcode::G_FMAXNUM_IEEE),
        GIM_CheckType, /*MI*/2, /*Op*/1, /*Type*/GILLT_s32,
        GIM_CheckType, /*MI*/2, /*Op*/2, /*Type*/GILLT_s32,
        GIM_RecordInsn, /*DefineMI*/3, /*MI*/2, /*OpIdx*/1, // MIs[3]
        GIM_CheckOpcode, /*MI*/3, GIMT_Encode2(TargetOpcode::G_FMINNUM),
        // MIs[3] VOP3Mods:src1:src1_mods
        GIM_CheckIsSameOperand, /*MI*/3, /*OpIdx*/1, /*OtherMI*/1, /*OtherOpIdx*/2,
        // MIs[3] VOP3Mods:src0:src0_mods
        GIM_CheckIsSameOperand, /*MI*/3, /*OpIdx*/2, /*OtherMI*/1, /*OtherOpIdx*/1,
        GIM_CheckCxxInsnPredicate, /*MI*/0, /*FnId*/GIMT_Encode2(GICXXPred_MI_Predicate_fminnum_like_nnan),
        GIM_CheckIsSafeToFold, /*InsnID*/1,
        GIM_CheckIsSafeToFold, /*InsnID*/2,
        GIM_CheckIsSafeToFold, /*InsnID*/3,
        GIM_CheckComplexPattern, /*MI*/1, /*Op*/1, /*Renderer*/GIMT_Encode2(0), GIMT_Encode2(GICP_gi_vop3mods),
        GIM_CheckComplexPattern, /*MI*/1, /*Op*/2, /*Renderer*/GIMT_Encode2(1), GIMT_Encode2(GICP_gi_vop3mods),
        GIM_CheckComplexPattern, /*MI*/2, /*Op*/2, /*Renderer*/GIMT_Encode2(2), GIMT_Encode2(GICP_gi_vop3mods),
        // (fminnum_ieee:{ *:[f32] } (fmaxnum:{ *:[f32] } (VOP3Mods:{ *:[f32] } f32:{ *:[f32] }:$src0, i32:{ *:[i32] }:$src0_mods), (VOP3Mods:{ *:[f32] } f32:{ *:[f32] }:$src1, i32:{ *:[i32] }:$src1_mods)), (fmaxnum_ieee:{ *:[f32] } (fminnum:{ *:[f32] } (VOP3Mods:{ *:[f32] } f32:{ *:[f32] }:$src1, i32:{ *:[i32] }:$src1_mods), (VOP3Mods:{ *:[f32] } f32:{ *:[f32] }:$src0, i32:{ *:[i32] }:$src0_mods)), (VOP3Mods:{ *:[f32] } f32:{ *:[f32] }:$src2, i32:{ *:[i32] }:$src2_mods)))<<P:Predicate_fminnum_like_nnan>>  =>  (V_MED3_F32_e64:{ *:[f32] } ?:{ *:[i32] }:$src0_mods, ?:{ *:[f32] }:$src0, ?:{ *:[i32] }:$src1_mods, ?:{ *:[f32] }:$src1, ?:{ *:[i32] }:$src2_mods, ?:{ *:[f32] }:$src2, 0:{ *:[i1] }, 0:{ *:[i32] })
        GIR_BuildMI, /*InsnID*/0, /*Opcode*/GIMT_Encode2(AMDGPU::V_MED3_F32_e64),
        GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/0, // DstI[vdst]
        GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/1, // src0_mods
        GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/0, // src0
        GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(1), /*SubOperand*/1, // src1_mods
        GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(1), /*SubOperand*/0, // src1
        GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(2), /*SubOperand*/1, // src2_mods
        GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(2), /*SubOperand*/0, // src2
        GIR_AddImm8, /*InsnID*/0, /*Imm*/0,
        GIR_AddImm8, /*InsnID*/0, /*Imm*/0,
        GIR_ConstrainSelectedInstOperands, /*InsnID*/0,
        GIR_EraseFromParent, /*InsnID*/0,
        // GIR_Coverage, 10315,
        GIR_Done,
      // Label 4796: @331157
      GIM_Try, /*On fail goto*//*Label 4797*/ GIMT_Encode4(331297), // Rule ID 10318 //
        GIM_CheckRegBankForClass, /*MI*/0, /*Op*/0, /*RC*/GIMT_Encode2(AMDGPU::VGPR_32RegClassID),
        GIM_RecordInsn, /*DefineMI*/1, /*MI*/0, /*OpIdx*/1, // MIs[1]
        GIM_CheckOpcode, /*MI*/1, GIMT_Encode2(TargetOpcode::G_FMAXNUM),
        GIM_CheckType, /*MI*/1, /*Op*/1, /*Type*/GILLT_s32,
        GIM_CheckType, /*MI*/1, /*Op*/2, /*Type*/GILLT_s32,
        GIM_RecordInsn, /*DefineMI*/2, /*MI*/0, /*OpIdx*/2, // MIs[2]
        GIM_CheckOpcode, /*MI*/2, GIMT_Encode2(TargetOpcode::G_FMAXNUM_IEEE),
        GIM_CheckType, /*MI*/2, /*Op*/1, /*Type*/GILLT_s32,
        GIM_CheckType, /*MI*/2, /*Op*/2, /*Type*/GILLT_s32,
        GIM_RecordInsn, /*DefineMI*/3, /*MI*/2, /*OpIdx*/1, // MIs[3]
        GIM_CheckOpcode, /*MI*/3, GIMT_Encode2(TargetOpcode::G_FMINNUM),
        // MIs[3] VOP3Mods:src0:src0_mods
        GIM_CheckIsSameOperand, /*MI*/3, /*OpIdx*/1, /*OtherMI*/1, /*OtherOpIdx*/2,
        // MIs[3] VOP3Mods:src1:src1_mods
        GIM_CheckIsSameOperand, /*MI*/3, /*OpIdx*/2, /*OtherMI*/1, /*OtherOpIdx*/1,
        GIM_CheckCxxInsnPredicate, /*MI*/0, /*FnId*/GIMT_Encode2(GICXXPred_MI_Predicate_fminnum_like_nnan),
        GIM_CheckIsSafeToFold, /*InsnID*/1,
        GIM_CheckIsSafeToFold, /*InsnID*/2,
        GIM_CheckIsSafeToFold, /*InsnID*/3,
        GIM_CheckComplexPattern, /*MI*/1, /*Op*/1, /*Renderer*/GIMT_Encode2(0), GIMT_Encode2(GICP_gi_vop3mods),
        GIM_CheckComplexPattern, /*MI*/1, /*Op*/2, /*Renderer*/GIMT_Encode2(1), GIMT_Encode2(GICP_gi_vop3mods),
        GIM_CheckComplexPattern, /*MI*/2, /*Op*/2, /*Renderer*/GIMT_Encode2(2), GIMT_Encode2(GICP_gi_vop3mods),
        // (fminnum_ieee:{ *:[f32] } (fmaxnum:{ *:[f32] } (VOP3Mods:{ *:[f32] } f32:{ *:[f32] }:$src1, i32:{ *:[i32] }:$src1_mods), (VOP3Mods:{ *:[f32] } f32:{ *:[f32] }:$src0, i32:{ *:[i32] }:$src0_mods)), (fmaxnum_ieee:{ *:[f32] } (fminnum:{ *:[f32] } (VOP3Mods:{ *:[f32] } f32:{ *:[f32] }:$src0, i32:{ *:[i32] }:$src0_mods), (VOP3Mods:{ *:[f32] } f32:{ *:[f32] }:$src1, i32:{ *:[i32] }:$src1_mods)), (VOP3Mods:{ *:[f32] } f32:{ *:[f32] }:$src2, i32:{ *:[i32] }:$src2_mods)))<<P:Predicate_fminnum_like_nnan>>  =>  (V_MED3_F32_e64:{ *:[f32] } ?:{ *:[i32] }:$src0_mods, ?:{ *:[f32] }:$src0, ?:{ *:[i32] }:$src1_mods, ?:{ *:[f32] }:$src1, ?:{ *:[i32] }:$src2_mods, ?:{ *:[f32] }:$src2, 0:{ *:[i1] }, 0:{ *:[i32] })
        GIR_BuildMI, /*InsnID*/0, /*Opcode*/GIMT_Encode2(AMDGPU::V_MED3_F32_e64),
        GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/0, // DstI[vdst]
        GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(1), /*SubOperand*/1, // src0_mods
        GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(1), /*SubOperand*/0, // src0
        GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/1, // src1_mods
        GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/0, // src1
        GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(2), /*SubOperand*/1, // src2_mods
        GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(2), /*SubOperand*/0, // src2
        GIR_AddImm8, /*InsnID*/0, /*Imm*/0,
        GIR_AddImm8, /*InsnID*/0, /*Imm*/0,
        GIR_ConstrainSelectedInstOperands, /*InsnID*/0,
        GIR_EraseFromParent, /*InsnID*/0,
        // GIR_Coverage, 10318,
        GIR_Done,
      // Label 4797: @331297
      GIM_Try, /*On fail goto*//*Label 4798*/ GIMT_Encode4(331437), // Rule ID 10319 //
        GIM_CheckRegBankForClass, /*MI*/0, /*Op*/0, /*RC*/GIMT_Encode2(AMDGPU::VGPR_32RegClassID),
        GIM_RecordInsn, /*DefineMI*/1, /*MI*/0, /*OpIdx*/1, // MIs[1]
        GIM_CheckOpcode, /*MI*/1, GIMT_Encode2(TargetOpcode::G_FMAXNUM),
        GIM_CheckType, /*MI*/1, /*Op*/1, /*Type*/GILLT_s32,
        GIM_CheckType, /*MI*/1, /*Op*/2, /*Type*/GILLT_s32,
        GIM_RecordInsn, /*DefineMI*/2, /*MI*/0, /*OpIdx*/2, // MIs[2]
        GIM_CheckOpcode, /*MI*/2, GIMT_Encode2(TargetOpcode::G_FMAXNUM_IEEE),
        GIM_CheckType, /*MI*/2, /*Op*/1, /*Type*/GILLT_s32,
        GIM_CheckType, /*MI*/2, /*Op*/2, /*Type*/GILLT_s32,
        GIM_RecordInsn, /*DefineMI*/3, /*MI*/2, /*OpIdx*/1, // MIs[3]
        GIM_CheckOpcode, /*MI*/3, GIMT_Encode2(TargetOpcode::G_FMINNUM),
        // MIs[3] VOP3Mods:src1:src1_mods
        GIM_CheckIsSameOperand, /*MI*/3, /*OpIdx*/1, /*OtherMI*/1, /*OtherOpIdx*/1,
        // MIs[3] VOP3Mods:src0:src0_mods
        GIM_CheckIsSameOperand, /*MI*/3, /*OpIdx*/2, /*OtherMI*/1, /*OtherOpIdx*/2,
        GIM_CheckCxxInsnPredicate, /*MI*/0, /*FnId*/GIMT_Encode2(GICXXPred_MI_Predicate_fminnum_like_nnan),
        GIM_CheckIsSafeToFold, /*InsnID*/1,
        GIM_CheckIsSafeToFold, /*InsnID*/2,
        GIM_CheckIsSafeToFold, /*InsnID*/3,
        GIM_CheckComplexPattern, /*MI*/1, /*Op*/1, /*Renderer*/GIMT_Encode2(0), GIMT_Encode2(GICP_gi_vop3mods),
        GIM_CheckComplexPattern, /*MI*/1, /*Op*/2, /*Renderer*/GIMT_Encode2(1), GIMT_Encode2(GICP_gi_vop3mods),
        GIM_CheckComplexPattern, /*MI*/2, /*Op*/2, /*Renderer*/GIMT_Encode2(2), GIMT_Encode2(GICP_gi_vop3mods),
        // (fminnum_ieee:{ *:[f32] } (fmaxnum:{ *:[f32] } (VOP3Mods:{ *:[f32] } f32:{ *:[f32] }:$src1, i32:{ *:[i32] }:$src1_mods), (VOP3Mods:{ *:[f32] } f32:{ *:[f32] }:$src0, i32:{ *:[i32] }:$src0_mods)), (fmaxnum_ieee:{ *:[f32] } (fminnum:{ *:[f32] } (VOP3Mods:{ *:[f32] } f32:{ *:[f32] }:$src1, i32:{ *:[i32] }:$src1_mods), (VOP3Mods:{ *:[f32] } f32:{ *:[f32] }:$src0, i32:{ *:[i32] }:$src0_mods)), (VOP3Mods:{ *:[f32] } f32:{ *:[f32] }:$src2, i32:{ *:[i32] }:$src2_mods)))<<P:Predicate_fminnum_like_nnan>>  =>  (V_MED3_F32_e64:{ *:[f32] } ?:{ *:[i32] }:$src0_mods, ?:{ *:[f32] }:$src0, ?:{ *:[i32] }:$src1_mods, ?:{ *:[f32] }:$src1, ?:{ *:[i32] }:$src2_mods, ?:{ *:[f32] }:$src2, 0:{ *:[i1] }, 0:{ *:[i32] })
        GIR_BuildMI, /*InsnID*/0, /*Opcode*/GIMT_Encode2(AMDGPU::V_MED3_F32_e64),
        GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/0, // DstI[vdst]
        GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(1), /*SubOperand*/1, // src0_mods
        GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(1), /*SubOperand*/0, // src0
        GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/1, // src1_mods
        GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/0, // src1
        GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(2), /*SubOperand*/1, // src2_mods
        GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(2), /*SubOperand*/0, // src2
        GIR_AddImm8, /*InsnID*/0, /*Imm*/0,
        GIR_AddImm8, /*InsnID*/0, /*Imm*/0,
        GIR_ConstrainSelectedInstOperands, /*InsnID*/0,
        GIR_EraseFromParent, /*InsnID*/0,
        // GIR_Coverage, 10319,
        GIR_Done,
      // Label 4798: @331437
      GIM_Try, /*On fail goto*//*Label 4799*/ GIMT_Encode4(331577), // Rule ID 6502 //
        GIM_CheckRegBankForClass, /*MI*/0, /*Op*/0, /*RC*/GIMT_Encode2(AMDGPU::VGPR_32RegClassID),
        GIM_RecordInsn, /*DefineMI*/1, /*MI*/0, /*OpIdx*/1, // MIs[1]
        GIM_CheckOpcode, /*MI*/1, GIMT_Encode2(TargetOpcode::G_FMAXNUM),
        GIM_CheckType, /*MI*/1, /*Op*/1, /*Type*/GILLT_s32,
        GIM_CheckType, /*MI*/1, /*Op*/2, /*Type*/GILLT_s32,
        GIM_RecordInsn, /*DefineMI*/2, /*MI*/0, /*OpIdx*/2, // MIs[2]
        GIM_CheckOpcode, /*MI*/2, GIMT_Encode2(TargetOpcode::G_FMAXNUM_IEEE),
        GIM_CheckType, /*MI*/2, /*Op*/1, /*Type*/GILLT_s32,
        GIM_CheckType, /*MI*/2, /*Op*/2, /*Type*/GILLT_s32,
        GIM_RecordInsn, /*DefineMI*/3, /*MI*/2, /*OpIdx*/1, // MIs[3]
        GIM_CheckOpcode, /*MI*/3, GIMT_Encode2(TargetOpcode::G_FMINNUM_IEEE),
        // MIs[3] VOP3Mods:src0:src0_mods
        GIM_CheckIsSameOperand, /*MI*/3, /*OpIdx*/1, /*OtherMI*/1, /*OtherOpIdx*/1,
        // MIs[3] VOP3Mods:src1:src1_mods
        GIM_CheckIsSameOperand, /*MI*/3, /*OpIdx*/2, /*OtherMI*/1, /*OtherOpIdx*/2,
        GIM_CheckCxxInsnPredicate, /*MI*/0, /*FnId*/GIMT_Encode2(GICXXPred_MI_Predicate_fminnum_like_nnan),
        GIM_CheckIsSafeToFold, /*InsnID*/1,
        GIM_CheckIsSafeToFold, /*InsnID*/2,
        GIM_CheckIsSafeToFold, /*InsnID*/3,
        GIM_CheckComplexPattern, /*MI*/1, /*Op*/1, /*Renderer*/GIMT_Encode2(0), GIMT_Encode2(GICP_gi_vop3mods),
        GIM_CheckComplexPattern, /*MI*/1, /*Op*/2, /*Renderer*/GIMT_Encode2(1), GIMT_Encode2(GICP_gi_vop3mods),
        GIM_CheckComplexPattern, /*MI*/2, /*Op*/2, /*Renderer*/GIMT_Encode2(2), GIMT_Encode2(GICP_gi_vop3mods),
        // (fminnum_ieee:{ *:[f32] } (fmaxnum:{ *:[f32] } (VOP3Mods:{ *:[f32] } f32:{ *:[f32] }:$src0, i32:{ *:[i32] }:$src0_mods), (VOP3Mods:{ *:[f32] } f32:{ *:[f32] }:$src1, i32:{ *:[i32] }:$src1_mods)), (fmaxnum_ieee:{ *:[f32] } (fminnum_ieee:{ *:[f32] } (VOP3Mods:{ *:[f32] } f32:{ *:[f32] }:$src0, i32:{ *:[i32] }:$src0_mods), (VOP3Mods:{ *:[f32] } f32:{ *:[f32] }:$src1, i32:{ *:[i32] }:$src1_mods)), (VOP3Mods:{ *:[f32] } f32:{ *:[f32] }:$src2, i32:{ *:[i32] }:$src2_mods)))<<P:Predicate_fminnum_like_nnan>>  =>  (V_MED3_F32_e64:{ *:[f32] } ?:{ *:[i32] }:$src0_mods, ?:{ *:[f32] }:$src0, ?:{ *:[i32] }:$src1_mods, ?:{ *:[f32] }:$src1, ?:{ *:[i32] }:$src2_mods, ?:{ *:[f32] }:$src2, 0:{ *:[i1] }, 0:{ *:[i32] })
        GIR_BuildMI, /*InsnID*/0, /*Opcode*/GIMT_Encode2(AMDGPU::V_MED3_F32_e64),
        GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/0, // DstI[vdst]
        GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/1, // src0_mods
        GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/0, // src0
        GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(1), /*SubOperand*/1, // src1_mods
        GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(1), /*SubOperand*/0, // src1
        GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(2), /*SubOperand*/1, // src2_mods
        GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(2), /*SubOperand*/0, // src2
        GIR_AddImm8, /*InsnID*/0, /*Imm*/0,
        GIR_AddImm8, /*InsnID*/0, /*Imm*/0,
        GIR_ConstrainSelectedInstOperands, /*InsnID*/0,
        GIR_EraseFromParent, /*InsnID*/0,
        // GIR_Coverage, 6502,
        GIR_Done,
      // Label 4799: @331577
      GIM_Try, /*On fail goto*//*Label 4800*/ GIMT_Encode4(331717), // Rule ID 10300 //
        GIM_CheckRegBankForClass, /*MI*/0, /*Op*/0, /*RC*/GIMT_Encode2(AMDGPU::VGPR_32RegClassID),
        GIM_RecordInsn, /*DefineMI*/1, /*MI*/0, /*OpIdx*/1, // MIs[1]
        GIM_CheckOpcode, /*MI*/1, GIMT_Encode2(TargetOpcode::G_FMAXNUM),
        GIM_CheckType, /*MI*/1, /*Op*/1, /*Type*/GILLT_s32,
        GIM_CheckType, /*MI*/1, /*Op*/2, /*Type*/GILLT_s32,
        GIM_RecordInsn, /*DefineMI*/2, /*MI*/0, /*OpIdx*/2, // MIs[2]
        GIM_CheckOpcode, /*MI*/2, GIMT_Encode2(TargetOpcode::G_FMAXNUM_IEEE),
        GIM_CheckType, /*MI*/2, /*Op*/1, /*Type*/GILLT_s32,
        GIM_CheckType, /*MI*/2, /*Op*/2, /*Type*/GILLT_s32,
        GIM_RecordInsn, /*DefineMI*/3, /*MI*/2, /*OpIdx*/1, // MIs[3]
        GIM_CheckOpcode, /*MI*/3, GIMT_Encode2(TargetOpcode::G_FMINNUM_IEEE),
        // MIs[3] VOP3Mods:src1:src1_mods
        GIM_CheckIsSameOperand, /*MI*/3, /*OpIdx*/1, /*OtherMI*/1, /*OtherOpIdx*/2,
        // MIs[3] VOP3Mods:src0:src0_mods
        GIM_CheckIsSameOperand, /*MI*/3, /*OpIdx*/2, /*OtherMI*/1, /*OtherOpIdx*/1,
        GIM_CheckCxxInsnPredicate, /*MI*/0, /*FnId*/GIMT_Encode2(GICXXPred_MI_Predicate_fminnum_like_nnan),
        GIM_CheckIsSafeToFold, /*InsnID*/1,
        GIM_CheckIsSafeToFold, /*InsnID*/2,
        GIM_CheckIsSafeToFold, /*InsnID*/3,
        GIM_CheckComplexPattern, /*MI*/1, /*Op*/1, /*Renderer*/GIMT_Encode2(0), GIMT_Encode2(GICP_gi_vop3mods),
        GIM_CheckComplexPattern, /*MI*/1, /*Op*/2, /*Renderer*/GIMT_Encode2(1), GIMT_Encode2(GICP_gi_vop3mods),
        GIM_CheckComplexPattern, /*MI*/2, /*Op*/2, /*Renderer*/GIMT_Encode2(2), GIMT_Encode2(GICP_gi_vop3mods),
        // (fminnum_ieee:{ *:[f32] } (fmaxnum:{ *:[f32] } (VOP3Mods:{ *:[f32] } f32:{ *:[f32] }:$src0, i32:{ *:[i32] }:$src0_mods), (VOP3Mods:{ *:[f32] } f32:{ *:[f32] }:$src1, i32:{ *:[i32] }:$src1_mods)), (fmaxnum_ieee:{ *:[f32] } (fminnum_ieee:{ *:[f32] } (VOP3Mods:{ *:[f32] } f32:{ *:[f32] }:$src1, i32:{ *:[i32] }:$src1_mods), (VOP3Mods:{ *:[f32] } f32:{ *:[f32] }:$src0, i32:{ *:[i32] }:$src0_mods)), (VOP3Mods:{ *:[f32] } f32:{ *:[f32] }:$src2, i32:{ *:[i32] }:$src2_mods)))<<P:Predicate_fminnum_like_nnan>>  =>  (V_MED3_F32_e64:{ *:[f32] } ?:{ *:[i32] }:$src0_mods, ?:{ *:[f32] }:$src0, ?:{ *:[i32] }:$src1_mods, ?:{ *:[f32] }:$src1, ?:{ *:[i32] }:$src2_mods, ?:{ *:[f32] }:$src2, 0:{ *:[i1] }, 0:{ *:[i32] })
        GIR_BuildMI, /*InsnID*/0, /*Opcode*/GIMT_Encode2(AMDGPU::V_MED3_F32_e64),
        GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/0, // DstI[vdst]
        GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/1, // src0_mods
        GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/0, // src0
        GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(1), /*SubOperand*/1, // src1_mods
        GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(1), /*SubOperand*/0, // src1
        GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(2), /*SubOperand*/1, // src2_mods
        GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(2), /*SubOperand*/0, // src2
        GIR_AddImm8, /*InsnID*/0, /*Imm*/0,
        GIR_AddImm8, /*InsnID*/0, /*Imm*/0,
        GIR_ConstrainSelectedInstOperands, /*InsnID*/0,
        GIR_EraseFromParent, /*InsnID*/0,
        // GIR_Coverage, 10300,
        GIR_Done,
      // Label 4800: @331717
      GIM_Try, /*On fail goto*//*Label 4801*/ GIMT_Encode4(331857), // Rule ID 10303 //
        GIM_CheckRegBankForClass, /*MI*/0, /*Op*/0, /*RC*/GIMT_Encode2(AMDGPU::VGPR_32RegClassID),
        GIM_RecordInsn, /*DefineMI*/1, /*MI*/0, /*OpIdx*/1, // MIs[1]
        GIM_CheckOpcode, /*MI*/1, GIMT_Encode2(TargetOpcode::G_FMAXNUM),
        GIM_CheckType, /*MI*/1, /*Op*/1, /*Type*/GILLT_s32,
        GIM_CheckType, /*MI*/1, /*Op*/2, /*Type*/GILLT_s32,
        GIM_RecordInsn, /*DefineMI*/2, /*MI*/0, /*OpIdx*/2, // MIs[2]
        GIM_CheckOpcode, /*MI*/2, GIMT_Encode2(TargetOpcode::G_FMAXNUM_IEEE),
        GIM_CheckType, /*MI*/2, /*Op*/1, /*Type*/GILLT_s32,
        GIM_CheckType, /*MI*/2, /*Op*/2, /*Type*/GILLT_s32,
        GIM_RecordInsn, /*DefineMI*/3, /*MI*/2, /*OpIdx*/1, // MIs[3]
        GIM_CheckOpcode, /*MI*/3, GIMT_Encode2(TargetOpcode::G_FMINNUM_IEEE),
        // MIs[3] VOP3Mods:src0:src0_mods
        GIM_CheckIsSameOperand, /*MI*/3, /*OpIdx*/1, /*OtherMI*/1, /*OtherOpIdx*/2,
        // MIs[3] VOP3Mods:src1:src1_mods
        GIM_CheckIsSameOperand, /*MI*/3, /*OpIdx*/2, /*OtherMI*/1, /*OtherOpIdx*/1,
        GIM_CheckCxxInsnPredicate, /*MI*/0, /*FnId*/GIMT_Encode2(GICXXPred_MI_Predicate_fminnum_like_nnan),
        GIM_CheckIsSafeToFold, /*InsnID*/1,
        GIM_CheckIsSafeToFold, /*InsnID*/2,
        GIM_CheckIsSafeToFold, /*InsnID*/3,
        GIM_CheckComplexPattern, /*MI*/1, /*Op*/1, /*Renderer*/GIMT_Encode2(0), GIMT_Encode2(GICP_gi_vop3mods),
        GIM_CheckComplexPattern, /*MI*/1, /*Op*/2, /*Renderer*/GIMT_Encode2(1), GIMT_Encode2(GICP_gi_vop3mods),
        GIM_CheckComplexPattern, /*MI*/2, /*Op*/2, /*Renderer*/GIMT_Encode2(2), GIMT_Encode2(GICP_gi_vop3mods),
        // (fminnum_ieee:{ *:[f32] } (fmaxnum:{ *:[f32] } (VOP3Mods:{ *:[f32] } f32:{ *:[f32] }:$src1, i32:{ *:[i32] }:$src1_mods), (VOP3Mods:{ *:[f32] } f32:{ *:[f32] }:$src0, i32:{ *:[i32] }:$src0_mods)), (fmaxnum_ieee:{ *:[f32] } (fminnum_ieee:{ *:[f32] } (VOP3Mods:{ *:[f32] } f32:{ *:[f32] }:$src0, i32:{ *:[i32] }:$src0_mods), (VOP3Mods:{ *:[f32] } f32:{ *:[f32] }:$src1, i32:{ *:[i32] }:$src1_mods)), (VOP3Mods:{ *:[f32] } f32:{ *:[f32] }:$src2, i32:{ *:[i32] }:$src2_mods)))<<P:Predicate_fminnum_like_nnan>>  =>  (V_MED3_F32_e64:{ *:[f32] } ?:{ *:[i32] }:$src0_mods, ?:{ *:[f32] }:$src0, ?:{ *:[i32] }:$src1_mods, ?:{ *:[f32] }:$src1, ?:{ *:[i32] }:$src2_mods, ?:{ *:[f32] }:$src2, 0:{ *:[i1] }, 0:{ *:[i32] })
        GIR_BuildMI, /*InsnID*/0, /*Opcode*/GIMT_Encode2(AMDGPU::V_MED3_F32_e64),
        GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/0, // DstI[vdst]
        GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(1), /*SubOperand*/1, // src0_mods
        GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(1), /*SubOperand*/0, // src0
        GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/1, // src1_mods
        GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/0, // src1
        GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(2), /*SubOperand*/1, // src2_mods
        GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(2), /*SubOperand*/0, // src2
        GIR_AddImm8, /*InsnID*/0, /*Imm*/0,
        GIR_AddImm8, /*InsnID*/0, /*Imm*/0,
        GIR_ConstrainSelectedInstOperands, /*InsnID*/0,
        GIR_EraseFromParent, /*InsnID*/0,
        // GIR_Coverage, 10303,
        GIR_Done,
      // Label 4801: @331857
      GIM_Try, /*On fail goto*//*Label 4802*/ GIMT_Encode4(331997), // Rule ID 10304 //
        GIM_CheckRegBankForClass, /*MI*/0, /*Op*/0, /*RC*/GIMT_Encode2(AMDGPU::VGPR_32RegClassID),
        GIM_RecordInsn, /*DefineMI*/1, /*MI*/0, /*OpIdx*/1, // MIs[1]
        GIM_CheckOpcode, /*MI*/1, GIMT_Encode2(TargetOpcode::G_FMAXNUM),
        GIM_CheckType, /*MI*/1, /*Op*/1, /*Type*/GILLT_s32,
        GIM_CheckType, /*MI*/1, /*Op*/2, /*Type*/GILLT_s32,
        GIM_RecordInsn, /*DefineMI*/2, /*MI*/0, /*OpIdx*/2, // MIs[2]
        GIM_CheckOpcode, /*MI*/2, GIMT_Encode2(TargetOpcode::G_FMAXNUM_IEEE),
        GIM_CheckType, /*MI*/2, /*Op*/1, /*Type*/GILLT_s32,
        GIM_CheckType, /*MI*/2, /*Op*/2, /*Type*/GILLT_s32,
        GIM_RecordInsn, /*DefineMI*/3, /*MI*/2, /*OpIdx*/1, // MIs[3]
        GIM_CheckOpcode, /*MI*/3, GIMT_Encode2(TargetOpcode::G_FMINNUM_IEEE),
        // MIs[3] VOP3Mods:src1:src1_mods
        GIM_CheckIsSameOperand, /*MI*/3, /*OpIdx*/1, /*OtherMI*/1, /*OtherOpIdx*/1,
        // MIs[3] VOP3Mods:src0:src0_mods
        GIM_CheckIsSameOperand, /*MI*/3, /*OpIdx*/2, /*OtherMI*/1, /*OtherOpIdx*/2,
        GIM_CheckCxxInsnPredicate, /*MI*/0, /*FnId*/GIMT_Encode2(GICXXPred_MI_Predicate_fminnum_like_nnan),
        GIM_CheckIsSafeToFold, /*InsnID*/1,
        GIM_CheckIsSafeToFold, /*InsnID*/2,
        GIM_CheckIsSafeToFold, /*InsnID*/3,
        GIM_CheckComplexPattern, /*MI*/1, /*Op*/1, /*Renderer*/GIMT_Encode2(0), GIMT_Encode2(GICP_gi_vop3mods),
        GIM_CheckComplexPattern, /*MI*/1, /*Op*/2, /*Renderer*/GIMT_Encode2(1), GIMT_Encode2(GICP_gi_vop3mods),
        GIM_CheckComplexPattern, /*MI*/2, /*Op*/2, /*Renderer*/GIMT_Encode2(2), GIMT_Encode2(GICP_gi_vop3mods),
        // (fminnum_ieee:{ *:[f32] } (fmaxnum:{ *:[f32] } (VOP3Mods:{ *:[f32] } f32:{ *:[f32] }:$src1, i32:{ *:[i32] }:$src1_mods), (VOP3Mods:{ *:[f32] } f32:{ *:[f32] }:$src0, i32:{ *:[i32] }:$src0_mods)), (fmaxnum_ieee:{ *:[f32] } (fminnum_ieee:{ *:[f32] } (VOP3Mods:{ *:[f32] } f32:{ *:[f32] }:$src1, i32:{ *:[i32] }:$src1_mods), (VOP3Mods:{ *:[f32] } f32:{ *:[f32] }:$src0, i32:{ *:[i32] }:$src0_mods)), (VOP3Mods:{ *:[f32] } f32:{ *:[f32] }:$src2, i32:{ *:[i32] }:$src2_mods)))<<P:Predicate_fminnum_like_nnan>>  =>  (V_MED3_F32_e64:{ *:[f32] } ?:{ *:[i32] }:$src0_mods, ?:{ *:[f32] }:$src0, ?:{ *:[i32] }:$src1_mods, ?:{ *:[f32] }:$src1, ?:{ *:[i32] }:$src2_mods, ?:{ *:[f32] }:$src2, 0:{ *:[i1] }, 0:{ *:[i32] })
        GIR_BuildMI, /*InsnID*/0, /*Opcode*/GIMT_Encode2(AMDGPU::V_MED3_F32_e64),
        GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/0, // DstI[vdst]
        GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(1), /*SubOperand*/1, // src0_mods
        GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(1), /*SubOperand*/0, // src0
        GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/1, // src1_mods
        GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/0, // src1
        GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(2), /*SubOperand*/1, // src2_mods
        GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(2), /*SubOperand*/0, // src2
        GIR_AddImm8, /*InsnID*/0, /*Imm*/0,
        GIR_AddImm8, /*InsnID*/0, /*Imm*/0,
        GIR_ConstrainSelectedInstOperands, /*InsnID*/0,
        GIR_EraseFromParent, /*InsnID*/0,
        // GIR_Coverage, 10304,
        GIR_Done,
      // Label 4802: @331997
      GIM_Try, /*On fail goto*//*Label 4803*/ GIMT_Encode4(332137), // Rule ID 10356 //
        GIM_CheckRegBankForClass, /*MI*/0, /*Op*/0, /*RC*/GIMT_Encode2(AMDGPU::VGPR_32RegClassID),
        GIM_RecordInsn, /*DefineMI*/1, /*MI*/0, /*OpIdx*/1, // MIs[1]
        GIM_CheckOpcode, /*MI*/1, GIMT_Encode2(TargetOpcode::G_FMAXNUM),
        GIM_CheckType, /*MI*/1, /*Op*/1, /*Type*/GILLT_s32,
        GIM_CheckType, /*MI*/1, /*Op*/2, /*Type*/GILLT_s32,
        GIM_RecordInsn, /*DefineMI*/2, /*MI*/1, /*OpIdx*/2, // MIs[2]
        GIM_CheckOpcode, /*MI*/2, GIMT_Encode2(TargetOpcode::G_FMINNUM),
        GIM_CheckType, /*MI*/2, /*Op*/1, /*Type*/GILLT_s32,
        GIM_CheckType, /*MI*/2, /*Op*/2, /*Type*/GILLT_s32,
        GIM_RecordInsn, /*DefineMI*/3, /*MI*/0, /*OpIdx*/2, // MIs[3]
        GIM_CheckOpcode, /*MI*/3, GIMT_Encode2(TargetOpcode::G_FMAXNUM),
        // MIs[3] VOP3Mods:src0:src0_mods
        GIM_CheckIsSameOperand, /*MI*/3, /*OpIdx*/1, /*OtherMI*/2, /*OtherOpIdx*/1,
        // MIs[3] VOP3Mods:src1:src1_mods
        GIM_CheckIsSameOperand, /*MI*/3, /*OpIdx*/2, /*OtherMI*/2, /*OtherOpIdx*/2,
        GIM_CheckCxxInsnPredicate, /*MI*/0, /*FnId*/GIMT_Encode2(GICXXPred_MI_Predicate_fminnum_like_nnan),
        GIM_CheckIsSafeToFold, /*InsnID*/1,
        GIM_CheckIsSafeToFold, /*InsnID*/2,
        GIM_CheckIsSafeToFold, /*InsnID*/3,
        GIM_CheckComplexPattern, /*MI*/1, /*Op*/1, /*Renderer*/GIMT_Encode2(0), GIMT_Encode2(GICP_gi_vop3mods),
        GIM_CheckComplexPattern, /*MI*/2, /*Op*/1, /*Renderer*/GIMT_Encode2(1), GIMT_Encode2(GICP_gi_vop3mods),
        GIM_CheckComplexPattern, /*MI*/2, /*Op*/2, /*Renderer*/GIMT_Encode2(2), GIMT_Encode2(GICP_gi_vop3mods),
        // (fminnum_ieee:{ *:[f32] } (fmaxnum:{ *:[f32] } (VOP3Mods:{ *:[f32] } f32:{ *:[f32] }:$src2, i32:{ *:[i32] }:$src2_mods), (fminnum:{ *:[f32] } (VOP3Mods:{ *:[f32] } f32:{ *:[f32] }:$src0, i32:{ *:[i32] }:$src0_mods), (VOP3Mods:{ *:[f32] } f32:{ *:[f32] }:$src1, i32:{ *:[i32] }:$src1_mods))), (fmaxnum:{ *:[f32] } (VOP3Mods:{ *:[f32] } f32:{ *:[f32] }:$src0, i32:{ *:[i32] }:$src0_mods), (VOP3Mods:{ *:[f32] } f32:{ *:[f32] }:$src1, i32:{ *:[i32] }:$src1_mods)))<<P:Predicate_fminnum_like_nnan>>  =>  (V_MED3_F32_e64:{ *:[f32] } ?:{ *:[i32] }:$src0_mods, ?:{ *:[f32] }:$src0, ?:{ *:[i32] }:$src1_mods, ?:{ *:[f32] }:$src1, ?:{ *:[i32] }:$src2_mods, ?:{ *:[f32] }:$src2, 0:{ *:[i1] }, 0:{ *:[i32] })
        GIR_BuildMI, /*InsnID*/0, /*Opcode*/GIMT_Encode2(AMDGPU::V_MED3_F32_e64),
        GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/0, // DstI[vdst]
        GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(1), /*SubOperand*/1, // src0_mods
        GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(1), /*SubOperand*/0, // src0
        GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(2), /*SubOperand*/1, // src1_mods
        GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(2), /*SubOperand*/0, // src1
        GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/1, // src2_mods
        GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/0, // src2
        GIR_AddImm8, /*InsnID*/0, /*Imm*/0,
        GIR_AddImm8, /*InsnID*/0, /*Imm*/0,
        GIR_ConstrainSelectedInstOperands, /*InsnID*/0,
        GIR_EraseFromParent, /*InsnID*/0,
        // GIR_Coverage, 10356,
        GIR_Done,
      // Label 4803: @332137
      GIM_Try, /*On fail goto*//*Label 4804*/ GIMT_Encode4(332277), // Rule ID 10357 //
        GIM_CheckRegBankForClass, /*MI*/0, /*Op*/0, /*RC*/GIMT_Encode2(AMDGPU::VGPR_32RegClassID),
        GIM_RecordInsn, /*DefineMI*/1, /*MI*/0, /*OpIdx*/1, // MIs[1]
        GIM_CheckOpcode, /*MI*/1, GIMT_Encode2(TargetOpcode::G_FMAXNUM),
        GIM_CheckType, /*MI*/1, /*Op*/1, /*Type*/GILLT_s32,
        GIM_CheckType, /*MI*/1, /*Op*/2, /*Type*/GILLT_s32,
        GIM_RecordInsn, /*DefineMI*/2, /*MI*/1, /*OpIdx*/2, // MIs[2]
        GIM_CheckOpcode, /*MI*/2, GIMT_Encode2(TargetOpcode::G_FMINNUM),
        GIM_CheckType, /*MI*/2, /*Op*/1, /*Type*/GILLT_s32,
        GIM_CheckType, /*MI*/2, /*Op*/2, /*Type*/GILLT_s32,
        GIM_RecordInsn, /*DefineMI*/3, /*MI*/0, /*OpIdx*/2, // MIs[3]
        GIM_CheckOpcode, /*MI*/3, GIMT_Encode2(TargetOpcode::G_FMAXNUM),
        // MIs[3] VOP3Mods:src1:src1_mods
        GIM_CheckIsSameOperand, /*MI*/3, /*OpIdx*/1, /*OtherMI*/2, /*OtherOpIdx*/2,
        // MIs[3] VOP3Mods:src0:src0_mods
        GIM_CheckIsSameOperand, /*MI*/3, /*OpIdx*/2, /*OtherMI*/2, /*OtherOpIdx*/1,
        GIM_CheckCxxInsnPredicate, /*MI*/0, /*FnId*/GIMT_Encode2(GICXXPred_MI_Predicate_fminnum_like_nnan),
        GIM_CheckIsSafeToFold, /*InsnID*/1,
        GIM_CheckIsSafeToFold, /*InsnID*/2,
        GIM_CheckIsSafeToFold, /*InsnID*/3,
        GIM_CheckComplexPattern, /*MI*/1, /*Op*/1, /*Renderer*/GIMT_Encode2(0), GIMT_Encode2(GICP_gi_vop3mods),
        GIM_CheckComplexPattern, /*MI*/2, /*Op*/1, /*Renderer*/GIMT_Encode2(1), GIMT_Encode2(GICP_gi_vop3mods),
        GIM_CheckComplexPattern, /*MI*/2, /*Op*/2, /*Renderer*/GIMT_Encode2(2), GIMT_Encode2(GICP_gi_vop3mods),
        // (fminnum_ieee:{ *:[f32] } (fmaxnum:{ *:[f32] } (VOP3Mods:{ *:[f32] } f32:{ *:[f32] }:$src2, i32:{ *:[i32] }:$src2_mods), (fminnum:{ *:[f32] } (VOP3Mods:{ *:[f32] } f32:{ *:[f32] }:$src0, i32:{ *:[i32] }:$src0_mods), (VOP3Mods:{ *:[f32] } f32:{ *:[f32] }:$src1, i32:{ *:[i32] }:$src1_mods))), (fmaxnum:{ *:[f32] } (VOP3Mods:{ *:[f32] } f32:{ *:[f32] }:$src1, i32:{ *:[i32] }:$src1_mods), (VOP3Mods:{ *:[f32] } f32:{ *:[f32] }:$src0, i32:{ *:[i32] }:$src0_mods)))<<P:Predicate_fminnum_like_nnan>>  =>  (V_MED3_F32_e64:{ *:[f32] } ?:{ *:[i32] }:$src0_mods, ?:{ *:[f32] }:$src0, ?:{ *:[i32] }:$src1_mods, ?:{ *:[f32] }:$src1, ?:{ *:[i32] }:$src2_mods, ?:{ *:[f32] }:$src2, 0:{ *:[i1] }, 0:{ *:[i32] })
        GIR_BuildMI, /*InsnID*/0, /*Opcode*/GIMT_Encode2(AMDGPU::V_MED3_F32_e64),
        GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/0, // DstI[vdst]
        GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(1), /*SubOperand*/1, // src0_mods
        GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(1), /*SubOperand*/0, // src0
        GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(2), /*SubOperand*/1, // src1_mods
        GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(2), /*SubOperand*/0, // src1
        GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/1, // src2_mods
        GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/0, // src2
        GIR_AddImm8, /*InsnID*/0, /*Imm*/0,
        GIR_AddImm8, /*InsnID*/0, /*Imm*/0,
        GIR_ConstrainSelectedInstOperands, /*InsnID*/0,
        GIR_EraseFromParent, /*InsnID*/0,
        // GIR_Coverage, 10357,
        GIR_Done,
      // Label 4804: @332277
      GIM_Try, /*On fail goto*//*Label 4805*/ GIMT_Encode4(332417), // Rule ID 10358 //
        GIM_CheckRegBankForClass, /*MI*/0, /*Op*/0, /*RC*/GIMT_Encode2(AMDGPU::VGPR_32RegClassID),
        GIM_RecordInsn, /*DefineMI*/1, /*MI*/0, /*OpIdx*/1, // MIs[1]
        GIM_CheckOpcode, /*MI*/1, GIMT_Encode2(TargetOpcode::G_FMAXNUM),
        GIM_CheckType, /*MI*/1, /*Op*/1, /*Type*/GILLT_s32,
        GIM_CheckType, /*MI*/1, /*Op*/2, /*Type*/GILLT_s32,
        GIM_RecordInsn, /*DefineMI*/2, /*MI*/1, /*OpIdx*/2, // MIs[2]
        GIM_CheckOpcode, /*MI*/2, GIMT_Encode2(TargetOpcode::G_FMINNUM),
        GIM_CheckType, /*MI*/2, /*Op*/1, /*Type*/GILLT_s32,
        GIM_CheckType, /*MI*/2, /*Op*/2, /*Type*/GILLT_s32,
        GIM_RecordInsn, /*DefineMI*/3, /*MI*/0, /*OpIdx*/2, // MIs[3]
        GIM_CheckOpcode, /*MI*/3, GIMT_Encode2(TargetOpcode::G_FMAXNUM),
        // MIs[3] VOP3Mods:src0:src0_mods
        GIM_CheckIsSameOperand, /*MI*/3, /*OpIdx*/1, /*OtherMI*/2, /*OtherOpIdx*/2,
        // MIs[3] VOP3Mods:src1:src1_mods
        GIM_CheckIsSameOperand, /*MI*/3, /*OpIdx*/2, /*OtherMI*/2, /*OtherOpIdx*/1,
        GIM_CheckCxxInsnPredicate, /*MI*/0, /*FnId*/GIMT_Encode2(GICXXPred_MI_Predicate_fminnum_like_nnan),
        GIM_CheckIsSafeToFold, /*InsnID*/1,
        GIM_CheckIsSafeToFold, /*InsnID*/2,
        GIM_CheckIsSafeToFold, /*InsnID*/3,
        GIM_CheckComplexPattern, /*MI*/1, /*Op*/1, /*Renderer*/GIMT_Encode2(0), GIMT_Encode2(GICP_gi_vop3mods),
        GIM_CheckComplexPattern, /*MI*/2, /*Op*/1, /*Renderer*/GIMT_Encode2(1), GIMT_Encode2(GICP_gi_vop3mods),
        GIM_CheckComplexPattern, /*MI*/2, /*Op*/2, /*Renderer*/GIMT_Encode2(2), GIMT_Encode2(GICP_gi_vop3mods),
        // (fminnum_ieee:{ *:[f32] } (fmaxnum:{ *:[f32] } (VOP3Mods:{ *:[f32] } f32:{ *:[f32] }:$src2, i32:{ *:[i32] }:$src2_mods), (fminnum:{ *:[f32] } (VOP3Mods:{ *:[f32] } f32:{ *:[f32] }:$src1, i32:{ *:[i32] }:$src1_mods), (VOP3Mods:{ *:[f32] } f32:{ *:[f32] }:$src0, i32:{ *:[i32] }:$src0_mods))), (fmaxnum:{ *:[f32] } (VOP3Mods:{ *:[f32] } f32:{ *:[f32] }:$src0, i32:{ *:[i32] }:$src0_mods), (VOP3Mods:{ *:[f32] } f32:{ *:[f32] }:$src1, i32:{ *:[i32] }:$src1_mods)))<<P:Predicate_fminnum_like_nnan>>  =>  (V_MED3_F32_e64:{ *:[f32] } ?:{ *:[i32] }:$src0_mods, ?:{ *:[f32] }:$src0, ?:{ *:[i32] }:$src1_mods, ?:{ *:[f32] }:$src1, ?:{ *:[i32] }:$src2_mods, ?:{ *:[f32] }:$src2, 0:{ *:[i1] }, 0:{ *:[i32] })
        GIR_BuildMI, /*InsnID*/0, /*Opcode*/GIMT_Encode2(AMDGPU::V_MED3_F32_e64),
        GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/0, // DstI[vdst]
        GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(2), /*SubOperand*/1, // src0_mods
        GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(2), /*SubOperand*/0, // src0
        GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(1), /*SubOperand*/1, // src1_mods
        GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(1), /*SubOperand*/0, // src1
        GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/1, // src2_mods
        GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/0, // src2
        GIR_AddImm8, /*InsnID*/0, /*Imm*/0,
        GIR_AddImm8, /*InsnID*/0, /*Imm*/0,
        GIR_ConstrainSelectedInstOperands, /*InsnID*/0,
        GIR_EraseFromParent, /*InsnID*/0,
        // GIR_Coverage, 10358,
        GIR_Done,
      // Label 4805: @332417
      GIM_Try, /*On fail goto*//*Label 4806*/ GIMT_Encode4(332557), // Rule ID 10359 //
        GIM_CheckRegBankForClass, /*MI*/0, /*Op*/0, /*RC*/GIMT_Encode2(AMDGPU::VGPR_32RegClassID),
        GIM_RecordInsn, /*DefineMI*/1, /*MI*/0, /*OpIdx*/1, // MIs[1]
        GIM_CheckOpcode, /*MI*/1, GIMT_Encode2(TargetOpcode::G_FMAXNUM),
        GIM_CheckType, /*MI*/1, /*Op*/1, /*Type*/GILLT_s32,
        GIM_CheckType, /*MI*/1, /*Op*/2, /*Type*/GILLT_s32,
        GIM_RecordInsn, /*DefineMI*/2, /*MI*/1, /*OpIdx*/2, // MIs[2]
        GIM_CheckOpcode, /*MI*/2, GIMT_Encode2(TargetOpcode::G_FMINNUM),
        GIM_CheckType, /*MI*/2, /*Op*/1, /*Type*/GILLT_s32,
        GIM_CheckType, /*MI*/2, /*Op*/2, /*Type*/GILLT_s32,
        GIM_RecordInsn, /*DefineMI*/3, /*MI*/0, /*OpIdx*/2, // MIs[3]
        GIM_CheckOpcode, /*MI*/3, GIMT_Encode2(TargetOpcode::G_FMAXNUM),
        // MIs[3] VOP3Mods:src1:src1_mods
        GIM_CheckIsSameOperand, /*MI*/3, /*OpIdx*/1, /*OtherMI*/2, /*OtherOpIdx*/1,
        // MIs[3] VOP3Mods:src0:src0_mods
        GIM_CheckIsSameOperand, /*MI*/3, /*OpIdx*/2, /*OtherMI*/2, /*OtherOpIdx*/2,
        GIM_CheckCxxInsnPredicate, /*MI*/0, /*FnId*/GIMT_Encode2(GICXXPred_MI_Predicate_fminnum_like_nnan),
        GIM_CheckIsSafeToFold, /*InsnID*/1,
        GIM_CheckIsSafeToFold, /*InsnID*/2,
        GIM_CheckIsSafeToFold, /*InsnID*/3,
        GIM_CheckComplexPattern, /*MI*/1, /*Op*/1, /*Renderer*/GIMT_Encode2(0), GIMT_Encode2(GICP_gi_vop3mods),
        GIM_CheckComplexPattern, /*MI*/2, /*Op*/1, /*Renderer*/GIMT_Encode2(1), GIMT_Encode2(GICP_gi_vop3mods),
        GIM_CheckComplexPattern, /*MI*/2, /*Op*/2, /*Renderer*/GIMT_Encode2(2), GIMT_Encode2(GICP_gi_vop3mods),
        // (fminnum_ieee:{ *:[f32] } (fmaxnum:{ *:[f32] } (VOP3Mods:{ *:[f32] } f32:{ *:[f32] }:$src2, i32:{ *:[i32] }:$src2_mods), (fminnum:{ *:[f32] } (VOP3Mods:{ *:[f32] } f32:{ *:[f32] }:$src1, i32:{ *:[i32] }:$src1_mods), (VOP3Mods:{ *:[f32] } f32:{ *:[f32] }:$src0, i32:{ *:[i32] }:$src0_mods))), (fmaxnum:{ *:[f32] } (VOP3Mods:{ *:[f32] } f32:{ *:[f32] }:$src1, i32:{ *:[i32] }:$src1_mods), (VOP3Mods:{ *:[f32] } f32:{ *:[f32] }:$src0, i32:{ *:[i32] }:$src0_mods)))<<P:Predicate_fminnum_like_nnan>>  =>  (V_MED3_F32_e64:{ *:[f32] } ?:{ *:[i32] }:$src0_mods, ?:{ *:[f32] }:$src0, ?:{ *:[i32] }:$src1_mods, ?:{ *:[f32] }:$src1, ?:{ *:[i32] }:$src2_mods, ?:{ *:[f32] }:$src2, 0:{ *:[i1] }, 0:{ *:[i32] })
        GIR_BuildMI, /*InsnID*/0, /*Opcode*/GIMT_Encode2(AMDGPU::V_MED3_F32_e64),
        GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/0, // DstI[vdst]
        GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(2), /*SubOperand*/1, // src0_mods
        GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(2), /*SubOperand*/0, // src0
        GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(1), /*SubOperand*/1, // src1_mods
        GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(1), /*SubOperand*/0, // src1
        GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/1, // src2_mods
        GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/0, // src2
        GIR_AddImm8, /*InsnID*/0, /*Imm*/0,
        GIR_AddImm8, /*InsnID*/0, /*Imm*/0,
        GIR_ConstrainSelectedInstOperands, /*InsnID*/0,
        GIR_EraseFromParent, /*InsnID*/0,
        // GIR_Coverage, 10359,
        GIR_Done,
      // Label 4806: @332557
      GIM_Try, /*On fail goto*//*Label 4807*/ GIMT_Encode4(332697), // Rule ID 10296 //
        GIM_CheckRegBankForClass, /*MI*/0, /*Op*/0, /*RC*/GIMT_Encode2(AMDGPU::VGPR_32RegClassID),
        GIM_RecordInsn, /*DefineMI*/1, /*MI*/0, /*OpIdx*/1, // MIs[1]
        GIM_CheckOpcode, /*MI*/1, GIMT_Encode2(TargetOpcode::G_FMAXNUM),
        GIM_CheckType, /*MI*/1, /*Op*/1, /*Type*/GILLT_s32,
        GIM_CheckType, /*MI*/1, /*Op*/2, /*Type*/GILLT_s32,
        GIM_RecordInsn, /*DefineMI*/2, /*MI*/1, /*OpIdx*/2, // MIs[2]
        GIM_CheckOpcode, /*MI*/2, GIMT_Encode2(TargetOpcode::G_FMINNUM),
        GIM_CheckType, /*MI*/2, /*Op*/1, /*Type*/GILLT_s32,
        GIM_CheckType, /*MI*/2, /*Op*/2, /*Type*/GILLT_s32,
        GIM_RecordInsn, /*DefineMI*/3, /*MI*/0, /*OpIdx*/2, // MIs[3]
        GIM_CheckOpcode, /*MI*/3, GIMT_Encode2(TargetOpcode::G_FMAXNUM_IEEE),
        // MIs[3] VOP3Mods:src0:src0_mods
        GIM_CheckIsSameOperand, /*MI*/3, /*OpIdx*/1, /*OtherMI*/2, /*OtherOpIdx*/1,
        // MIs[3] VOP3Mods:src1:src1_mods
        GIM_CheckIsSameOperand, /*MI*/3, /*OpIdx*/2, /*OtherMI*/2, /*OtherOpIdx*/2,
        GIM_CheckCxxInsnPredicate, /*MI*/0, /*FnId*/GIMT_Encode2(GICXXPred_MI_Predicate_fminnum_like_nnan),
        GIM_CheckIsSafeToFold, /*InsnID*/1,
        GIM_CheckIsSafeToFold, /*InsnID*/2,
        GIM_CheckIsSafeToFold, /*InsnID*/3,
        GIM_CheckComplexPattern, /*MI*/1, /*Op*/1, /*Renderer*/GIMT_Encode2(0), GIMT_Encode2(GICP_gi_vop3mods),
        GIM_CheckComplexPattern, /*MI*/2, /*Op*/1, /*Renderer*/GIMT_Encode2(1), GIMT_Encode2(GICP_gi_vop3mods),
        GIM_CheckComplexPattern, /*MI*/2, /*Op*/2, /*Renderer*/GIMT_Encode2(2), GIMT_Encode2(GICP_gi_vop3mods),
        // (fminnum_ieee:{ *:[f32] } (fmaxnum:{ *:[f32] } (VOP3Mods:{ *:[f32] } f32:{ *:[f32] }:$src2, i32:{ *:[i32] }:$src2_mods), (fminnum:{ *:[f32] } (VOP3Mods:{ *:[f32] } f32:{ *:[f32] }:$src0, i32:{ *:[i32] }:$src0_mods), (VOP3Mods:{ *:[f32] } f32:{ *:[f32] }:$src1, i32:{ *:[i32] }:$src1_mods))), (fmaxnum_ieee:{ *:[f32] } (VOP3Mods:{ *:[f32] } f32:{ *:[f32] }:$src0, i32:{ *:[i32] }:$src0_mods), (VOP3Mods:{ *:[f32] } f32:{ *:[f32] }:$src1, i32:{ *:[i32] }:$src1_mods)))<<P:Predicate_fminnum_like_nnan>>  =>  (V_MED3_F32_e64:{ *:[f32] } ?:{ *:[i32] }:$src0_mods, ?:{ *:[f32] }:$src0, ?:{ *:[i32] }:$src1_mods, ?:{ *:[f32] }:$src1, ?:{ *:[i32] }:$src2_mods, ?:{ *:[f32] }:$src2, 0:{ *:[i1] }, 0:{ *:[i32] })
        GIR_BuildMI, /*InsnID*/0, /*Opcode*/GIMT_Encode2(AMDGPU::V_MED3_F32_e64),
        GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/0, // DstI[vdst]
        GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(1), /*SubOperand*/1, // src0_mods
        GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(1), /*SubOperand*/0, // src0
        GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(2), /*SubOperand*/1, // src1_mods
        GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(2), /*SubOperand*/0, // src1
        GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/1, // src2_mods
        GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/0, // src2
        GIR_AddImm8, /*InsnID*/0, /*Imm*/0,
        GIR_AddImm8, /*InsnID*/0, /*Imm*/0,
        GIR_ConstrainSelectedInstOperands, /*InsnID*/0,
        GIR_EraseFromParent, /*InsnID*/0,
        // GIR_Coverage, 10296,
        GIR_Done,
      // Label 4807: @332697
      GIM_Try, /*On fail goto*//*Label 4808*/ GIMT_Encode4(332837), // Rule ID 10297 //
        GIM_CheckRegBankForClass, /*MI*/0, /*Op*/0, /*RC*/GIMT_Encode2(AMDGPU::VGPR_32RegClassID),
        GIM_RecordInsn, /*DefineMI*/1, /*MI*/0, /*OpIdx*/1, // MIs[1]
        GIM_CheckOpcode, /*MI*/1, GIMT_Encode2(TargetOpcode::G_FMAXNUM),
        GIM_CheckType, /*MI*/1, /*Op*/1, /*Type*/GILLT_s32,
        GIM_CheckType, /*MI*/1, /*Op*/2, /*Type*/GILLT_s32,
        GIM_RecordInsn, /*DefineMI*/2, /*MI*/1, /*OpIdx*/2, // MIs[2]
        GIM_CheckOpcode, /*MI*/2, GIMT_Encode2(TargetOpcode::G_FMINNUM),
        GIM_CheckType, /*MI*/2, /*Op*/1, /*Type*/GILLT_s32,
        GIM_CheckType, /*MI*/2, /*Op*/2, /*Type*/GILLT_s32,
        GIM_RecordInsn, /*DefineMI*/3, /*MI*/0, /*OpIdx*/2, // MIs[3]
        GIM_CheckOpcode, /*MI*/3, GIMT_Encode2(TargetOpcode::G_FMAXNUM_IEEE),
        // MIs[3] VOP3Mods:src1:src1_mods
        GIM_CheckIsSameOperand, /*MI*/3, /*OpIdx*/1, /*OtherMI*/2, /*OtherOpIdx*/2,
        // MIs[3] VOP3Mods:src0:src0_mods
        GIM_CheckIsSameOperand, /*MI*/3, /*OpIdx*/2, /*OtherMI*/2, /*OtherOpIdx*/1,
        GIM_CheckCxxInsnPredicate, /*MI*/0, /*FnId*/GIMT_Encode2(GICXXPred_MI_Predicate_fminnum_like_nnan),
        GIM_CheckIsSafeToFold, /*InsnID*/1,
        GIM_CheckIsSafeToFold, /*InsnID*/2,
        GIM_CheckIsSafeToFold, /*InsnID*/3,
        GIM_CheckComplexPattern, /*MI*/1, /*Op*/1, /*Renderer*/GIMT_Encode2(0), GIMT_Encode2(GICP_gi_vop3mods),
        GIM_CheckComplexPattern, /*MI*/2, /*Op*/1, /*Renderer*/GIMT_Encode2(1), GIMT_Encode2(GICP_gi_vop3mods),
        GIM_CheckComplexPattern, /*MI*/2, /*Op*/2, /*Renderer*/GIMT_Encode2(2), GIMT_Encode2(GICP_gi_vop3mods),
        // (fminnum_ieee:{ *:[f32] } (fmaxnum:{ *:[f32] } (VOP3Mods:{ *:[f32] } f32:{ *:[f32] }:$src2, i32:{ *:[i32] }:$src2_mods), (fminnum:{ *:[f32] } (VOP3Mods:{ *:[f32] } f32:{ *:[f32] }:$src0, i32:{ *:[i32] }:$src0_mods), (VOP3Mods:{ *:[f32] } f32:{ *:[f32] }:$src1, i32:{ *:[i32] }:$src1_mods))), (fmaxnum_ieee:{ *:[f32] } (VOP3Mods:{ *:[f32] } f32:{ *:[f32] }:$src1, i32:{ *:[i32] }:$src1_mods), (VOP3Mods:{ *:[f32] } f32:{ *:[f32] }:$src0, i32:{ *:[i32] }:$src0_mods)))<<P:Predicate_fminnum_like_nnan>>  =>  (V_MED3_F32_e64:{ *:[f32] } ?:{ *:[i32] }:$src0_mods, ?:{ *:[f32] }:$src0, ?:{ *:[i32] }:$src1_mods, ?:{ *:[f32] }:$src1, ?:{ *:[i32] }:$src2_mods, ?:{ *:[f32] }:$src2, 0:{ *:[i1] }, 0:{ *:[i32] })
        GIR_BuildMI, /*InsnID*/0, /*Opcode*/GIMT_Encode2(AMDGPU::V_MED3_F32_e64),
        GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/0, // DstI[vdst]
        GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(1), /*SubOperand*/1, // src0_mods
        GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(1), /*SubOperand*/0, // src0
        GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(2), /*SubOperand*/1, // src1_mods
        GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(2), /*SubOperand*/0, // src1
        GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/1, // src2_mods
        GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/0, // src2
        GIR_AddImm8, /*InsnID*/0, /*Imm*/0,
        GIR_AddImm8, /*InsnID*/0, /*Imm*/0,
        GIR_ConstrainSelectedInstOperands, /*InsnID*/0,
        GIR_EraseFromParent, /*InsnID*/0,
        // GIR_Coverage, 10297,
        GIR_Done,
      // Label 4808: @332837
      GIM_Try, /*On fail goto*//*Label 4809*/ GIMT_Encode4(332977), // Rule ID 10298 //
        GIM_CheckRegBankForClass, /*MI*/0, /*Op*/0, /*RC*/GIMT_Encode2(AMDGPU::VGPR_32RegClassID),
        GIM_RecordInsn, /*DefineMI*/1, /*MI*/0, /*OpIdx*/1, // MIs[1]
        GIM_CheckOpcode, /*MI*/1, GIMT_Encode2(TargetOpcode::G_FMAXNUM),
        GIM_CheckType, /*MI*/1, /*Op*/1, /*Type*/GILLT_s32,
        GIM_CheckType, /*MI*/1, /*Op*/2, /*Type*/GILLT_s32,
        GIM_RecordInsn, /*DefineMI*/2, /*MI*/1, /*OpIdx*/2, // MIs[2]
        GIM_CheckOpcode, /*MI*/2, GIMT_Encode2(TargetOpcode::G_FMINNUM),
        GIM_CheckType, /*MI*/2, /*Op*/1, /*Type*/GILLT_s32,
        GIM_CheckType, /*MI*/2, /*Op*/2, /*Type*/GILLT_s32,
        GIM_RecordInsn, /*DefineMI*/3, /*MI*/0, /*OpIdx*/2, // MIs[3]
        GIM_CheckOpcode, /*MI*/3, GIMT_Encode2(TargetOpcode::G_FMAXNUM_IEEE),
        // MIs[3] VOP3Mods:src0:src0_mods
        GIM_CheckIsSameOperand, /*MI*/3, /*OpIdx*/1, /*OtherMI*/2, /*OtherOpIdx*/2,
        // MIs[3] VOP3Mods:src1:src1_mods
        GIM_CheckIsSameOperand, /*MI*/3, /*OpIdx*/2, /*OtherMI*/2, /*OtherOpIdx*/1,
        GIM_CheckCxxInsnPredicate, /*MI*/0, /*FnId*/GIMT_Encode2(GICXXPred_MI_Predicate_fminnum_like_nnan),
        GIM_CheckIsSafeToFold, /*InsnID*/1,
        GIM_CheckIsSafeToFold, /*InsnID*/2,
        GIM_CheckIsSafeToFold, /*InsnID*/3,
        GIM_CheckComplexPattern, /*MI*/1, /*Op*/1, /*Renderer*/GIMT_Encode2(0), GIMT_Encode2(GICP_gi_vop3mods),
        GIM_CheckComplexPattern, /*MI*/2, /*Op*/1, /*Renderer*/GIMT_Encode2(1), GIMT_Encode2(GICP_gi_vop3mods),
        GIM_CheckComplexPattern, /*MI*/2, /*Op*/2, /*Renderer*/GIMT_Encode2(2), GIMT_Encode2(GICP_gi_vop3mods),
        // (fminnum_ieee:{ *:[f32] } (fmaxnum:{ *:[f32] } (VOP3Mods:{ *:[f32] } f32:{ *:[f32] }:$src2, i32:{ *:[i32] }:$src2_mods), (fminnum:{ *:[f32] } (VOP3Mods:{ *:[f32] } f32:{ *:[f32] }:$src1, i32:{ *:[i32] }:$src1_mods), (VOP3Mods:{ *:[f32] } f32:{ *:[f32] }:$src0, i32:{ *:[i32] }:$src0_mods))), (fmaxnum_ieee:{ *:[f32] } (VOP3Mods:{ *:[f32] } f32:{ *:[f32] }:$src0, i32:{ *:[i32] }:$src0_mods), (VOP3Mods:{ *:[f32] } f32:{ *:[f32] }:$src1, i32:{ *:[i32] }:$src1_mods)))<<P:Predicate_fminnum_like_nnan>>  =>  (V_MED3_F32_e64:{ *:[f32] } ?:{ *:[i32] }:$src0_mods, ?:{ *:[f32] }:$src0, ?:{ *:[i32] }:$src1_mods, ?:{ *:[f32] }:$src1, ?:{ *:[i32] }:$src2_mods, ?:{ *:[f32] }:$src2, 0:{ *:[i1] }, 0:{ *:[i32] })
        GIR_BuildMI, /*InsnID*/0, /*Opcode*/GIMT_Encode2(AMDGPU::V_MED3_F32_e64),
        GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/0, // DstI[vdst]
        GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(2), /*SubOperand*/1, // src0_mods
        GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(2), /*SubOperand*/0, // src0
        GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(1), /*SubOperand*/1, // src1_mods
        GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(1), /*SubOperand*/0, // src1
        GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/1, // src2_mods
        GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/0, // src2
        GIR_AddImm8, /*InsnID*/0, /*Imm*/0,
        GIR_AddImm8, /*InsnID*/0, /*Imm*/0,
        GIR_ConstrainSelectedInstOperands, /*InsnID*/0,
        GIR_EraseFromParent, /*InsnID*/0,
        // GIR_Coverage, 10298,
        GIR_Done,
      // Label 4809: @332977
      GIM_Try, /*On fail goto*//*Label 4810*/ GIMT_Encode4(333117), // Rule ID 10299 //
        GIM_CheckRegBankForClass, /*MI*/0, /*Op*/0, /*RC*/GIMT_Encode2(AMDGPU::VGPR_32RegClassID),
        GIM_RecordInsn, /*DefineMI*/1, /*MI*/0, /*OpIdx*/1, // MIs[1]
        GIM_CheckOpcode, /*MI*/1, GIMT_Encode2(TargetOpcode::G_FMAXNUM),
        GIM_CheckType, /*MI*/1, /*Op*/1, /*Type*/GILLT_s32,
        GIM_CheckType, /*MI*/1, /*Op*/2, /*Type*/GILLT_s32,
        GIM_RecordInsn, /*DefineMI*/2, /*MI*/1, /*OpIdx*/2, // MIs[2]
        GIM_CheckOpcode, /*MI*/2, GIMT_Encode2(TargetOpcode::G_FMINNUM),
        GIM_CheckType, /*MI*/2, /*Op*/1, /*Type*/GILLT_s32,
        GIM_CheckType, /*MI*/2, /*Op*/2, /*Type*/GILLT_s32,
        GIM_RecordInsn, /*DefineMI*/3, /*MI*/0, /*OpIdx*/2, // MIs[3]
        GIM_CheckOpcode, /*MI*/3, GIMT_Encode2(TargetOpcode::G_FMAXNUM_IEEE),
        // MIs[3] VOP3Mods:src1:src1_mods
        GIM_CheckIsSameOperand, /*MI*/3, /*OpIdx*/1, /*OtherMI*/2, /*OtherOpIdx*/1,
        // MIs[3] VOP3Mods:src0:src0_mods
        GIM_CheckIsSameOperand, /*MI*/3, /*OpIdx*/2, /*OtherMI*/2, /*OtherOpIdx*/2,
        GIM_CheckCxxInsnPredicate, /*MI*/0, /*FnId*/GIMT_Encode2(GICXXPred_MI_Predicate_fminnum_like_nnan),
        GIM_CheckIsSafeToFold, /*InsnID*/1,
        GIM_CheckIsSafeToFold, /*InsnID*/2,
        GIM_CheckIsSafeToFold, /*InsnID*/3,
        GIM_CheckComplexPattern, /*MI*/1, /*Op*/1, /*Renderer*/GIMT_Encode2(0), GIMT_Encode2(GICP_gi_vop3mods),
        GIM_CheckComplexPattern, /*MI*/2, /*Op*/1, /*Renderer*/GIMT_Encode2(1), GIMT_Encode2(GICP_gi_vop3mods),
        GIM_CheckComplexPattern, /*MI*/2, /*Op*/2, /*Renderer*/GIMT_Encode2(2), GIMT_Encode2(GICP_gi_vop3mods),
        // (fminnum_ieee:{ *:[f32] } (fmaxnum:{ *:[f32] } (VOP3Mods:{ *:[f32] } f32:{ *:[f32] }:$src2, i32:{ *:[i32] }:$src2_mods), (fminnum:{ *:[f32] } (VOP3Mods:{ *:[f32] } f32:{ *:[f32] }:$src1, i32:{ *:[i32] }:$src1_mods), (VOP3Mods:{ *:[f32] } f32:{ *:[f32] }:$src0, i32:{ *:[i32] }:$src0_mods))), (fmaxnum_ieee:{ *:[f32] } (VOP3Mods:{ *:[f32] } f32:{ *:[f32] }:$src1, i32:{ *:[i32] }:$src1_mods), (VOP3Mods:{ *:[f32] } f32:{ *:[f32] }:$src0, i32:{ *:[i32] }:$src0_mods)))<<P:Predicate_fminnum_like_nnan>>  =>  (V_MED3_F32_e64:{ *:[f32] } ?:{ *:[i32] }:$src0_mods, ?:{ *:[f32] }:$src0, ?:{ *:[i32] }:$src1_mods, ?:{ *:[f32] }:$src1, ?:{ *:[i32] }:$src2_mods, ?:{ *:[f32] }:$src2, 0:{ *:[i1] }, 0:{ *:[i32] })
        GIR_BuildMI, /*InsnID*/0, /*Opcode*/GIMT_Encode2(AMDGPU::V_MED3_F32_e64),
        GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/0, // DstI[vdst]
        GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(2), /*SubOperand*/1, // src0_mods
        GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(2), /*SubOperand*/0, // src0
        GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(1), /*SubOperand*/1, // src1_mods
        GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(1), /*SubOperand*/0, // src1
        GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/1, // src2_mods
        GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/0, // src2
        GIR_AddImm8, /*InsnID*/0, /*Imm*/0,
        GIR_AddImm8, /*InsnID*/0, /*Imm*/0,
        GIR_ConstrainSelectedInstOperands, /*InsnID*/0,
        GIR_EraseFromParent, /*InsnID*/0,
        // GIR_Coverage, 10299,
        GIR_Done,
      // Label 4810: @333117
      GIM_Try, /*On fail goto*//*Label 4811*/ GIMT_Encode4(333257), // Rule ID 10341 //
        GIM_CheckRegBankForClass, /*MI*/0, /*Op*/0, /*RC*/GIMT_Encode2(AMDGPU::VGPR_32RegClassID),
        GIM_RecordInsn, /*DefineMI*/1, /*MI*/0, /*OpIdx*/1, // MIs[1]
        GIM_CheckOpcode, /*MI*/1, GIMT_Encode2(TargetOpcode::G_FMAXNUM),
        GIM_CheckType, /*MI*/1, /*Op*/1, /*Type*/GILLT_s32,
        GIM_CheckType, /*MI*/1, /*Op*/2, /*Type*/GILLT_s32,
        GIM_RecordInsn, /*DefineMI*/2, /*MI*/1, /*OpIdx*/2, // MIs[2]
        GIM_CheckOpcode, /*MI*/2, GIMT_Encode2(TargetOpcode::G_FMINNUM_IEEE),
        GIM_CheckType, /*MI*/2, /*Op*/1, /*Type*/GILLT_s32,
        GIM_CheckType, /*MI*/2, /*Op*/2, /*Type*/GILLT_s32,
        GIM_RecordInsn, /*DefineMI*/3, /*MI*/0, /*OpIdx*/2, // MIs[3]
        GIM_CheckOpcode, /*MI*/3, GIMT_Encode2(TargetOpcode::G_FMAXNUM),
        // MIs[3] VOP3Mods:src0:src0_mods
        GIM_CheckIsSameOperand, /*MI*/3, /*OpIdx*/1, /*OtherMI*/2, /*OtherOpIdx*/1,
        // MIs[3] VOP3Mods:src1:src1_mods
        GIM_CheckIsSameOperand, /*MI*/3, /*OpIdx*/2, /*OtherMI*/2, /*OtherOpIdx*/2,
        GIM_CheckCxxInsnPredicate, /*MI*/0, /*FnId*/GIMT_Encode2(GICXXPred_MI_Predicate_fminnum_like_nnan),
        GIM_CheckIsSafeToFold, /*InsnID*/1,
        GIM_CheckIsSafeToFold, /*InsnID*/2,
        GIM_CheckIsSafeToFold, /*InsnID*/3,
        GIM_CheckComplexPattern, /*MI*/1, /*Op*/1, /*Renderer*/GIMT_Encode2(0), GIMT_Encode2(GICP_gi_vop3mods),
        GIM_CheckComplexPattern, /*MI*/2, /*Op*/1, /*Renderer*/GIMT_Encode2(1), GIMT_Encode2(GICP_gi_vop3mods),
        GIM_CheckComplexPattern, /*MI*/2, /*Op*/2, /*Renderer*/GIMT_Encode2(2), GIMT_Encode2(GICP_gi_vop3mods),
        // (fminnum_ieee:{ *:[f32] } (fmaxnum:{ *:[f32] } (VOP3Mods:{ *:[f32] } f32:{ *:[f32] }:$src2, i32:{ *:[i32] }:$src2_mods), (fminnum_ieee:{ *:[f32] } (VOP3Mods:{ *:[f32] } f32:{ *:[f32] }:$src0, i32:{ *:[i32] }:$src0_mods), (VOP3Mods:{ *:[f32] } f32:{ *:[f32] }:$src1, i32:{ *:[i32] }:$src1_mods))), (fmaxnum:{ *:[f32] } (VOP3Mods:{ *:[f32] } f32:{ *:[f32] }:$src0, i32:{ *:[i32] }:$src0_mods), (VOP3Mods:{ *:[f32] } f32:{ *:[f32] }:$src1, i32:{ *:[i32] }:$src1_mods)))<<P:Predicate_fminnum_like_nnan>>  =>  (V_MED3_F32_e64:{ *:[f32] } ?:{ *:[i32] }:$src0_mods, ?:{ *:[f32] }:$src0, ?:{ *:[i32] }:$src1_mods, ?:{ *:[f32] }:$src1, ?:{ *:[i32] }:$src2_mods, ?:{ *:[f32] }:$src2, 0:{ *:[i1] }, 0:{ *:[i32] })
        GIR_BuildMI, /*InsnID*/0, /*Opcode*/GIMT_Encode2(AMDGPU::V_MED3_F32_e64),
        GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/0, // DstI[vdst]
        GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(1), /*SubOperand*/1, // src0_mods
        GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(1), /*SubOperand*/0, // src0
        GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(2), /*SubOperand*/1, // src1_mods
        GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(2), /*SubOperand*/0, // src1
        GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/1, // src2_mods
        GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/0, // src2
        GIR_AddImm8, /*InsnID*/0, /*Imm*/0,
        GIR_AddImm8, /*InsnID*/0, /*Imm*/0,
        GIR_ConstrainSelectedInstOperands, /*InsnID*/0,
        GIR_EraseFromParent, /*InsnID*/0,
        // GIR_Coverage, 10341,
        GIR_Done,
      // Label 4811: @333257
      GIM_Try, /*On fail goto*//*Label 4812*/ GIMT_Encode4(333397), // Rule ID 10342 //
        GIM_CheckRegBankForClass, /*MI*/0, /*Op*/0, /*RC*/GIMT_Encode2(AMDGPU::VGPR_32RegClassID),
        GIM_RecordInsn, /*DefineMI*/1, /*MI*/0, /*OpIdx*/1, // MIs[1]
        GIM_CheckOpcode, /*MI*/1, GIMT_Encode2(TargetOpcode::G_FMAXNUM),
        GIM_CheckType, /*MI*/1, /*Op*/1, /*Type*/GILLT_s32,
        GIM_CheckType, /*MI*/1, /*Op*/2, /*Type*/GILLT_s32,
        GIM_RecordInsn, /*DefineMI*/2, /*MI*/1, /*OpIdx*/2, // MIs[2]
        GIM_CheckOpcode, /*MI*/2, GIMT_Encode2(TargetOpcode::G_FMINNUM_IEEE),
        GIM_CheckType, /*MI*/2, /*Op*/1, /*Type*/GILLT_s32,
        GIM_CheckType, /*MI*/2, /*Op*/2, /*Type*/GILLT_s32,
        GIM_RecordInsn, /*DefineMI*/3, /*MI*/0, /*OpIdx*/2, // MIs[3]
        GIM_CheckOpcode, /*MI*/3, GIMT_Encode2(TargetOpcode::G_FMAXNUM),
        // MIs[3] VOP3Mods:src1:src1_mods
        GIM_CheckIsSameOperand, /*MI*/3, /*OpIdx*/1, /*OtherMI*/2, /*OtherOpIdx*/2,
        // MIs[3] VOP3Mods:src0:src0_mods
        GIM_CheckIsSameOperand, /*MI*/3, /*OpIdx*/2, /*OtherMI*/2, /*OtherOpIdx*/1,
        GIM_CheckCxxInsnPredicate, /*MI*/0, /*FnId*/GIMT_Encode2(GICXXPred_MI_Predicate_fminnum_like_nnan),
        GIM_CheckIsSafeToFold, /*InsnID*/1,
        GIM_CheckIsSafeToFold, /*InsnID*/2,
        GIM_CheckIsSafeToFold, /*InsnID*/3,
        GIM_CheckComplexPattern, /*MI*/1, /*Op*/1, /*Renderer*/GIMT_Encode2(0), GIMT_Encode2(GICP_gi_vop3mods),
        GIM_CheckComplexPattern, /*MI*/2, /*Op*/1, /*Renderer*/GIMT_Encode2(1), GIMT_Encode2(GICP_gi_vop3mods),
        GIM_CheckComplexPattern, /*MI*/2, /*Op*/2, /*Renderer*/GIMT_Encode2(2), GIMT_Encode2(GICP_gi_vop3mods),
        // (fminnum_ieee:{ *:[f32] } (fmaxnum:{ *:[f32] } (VOP3Mods:{ *:[f32] } f32:{ *:[f32] }:$src2, i32:{ *:[i32] }:$src2_mods), (fminnum_ieee:{ *:[f32] } (VOP3Mods:{ *:[f32] } f32:{ *:[f32] }:$src0, i32:{ *:[i32] }:$src0_mods), (VOP3Mods:{ *:[f32] } f32:{ *:[f32] }:$src1, i32:{ *:[i32] }:$src1_mods))), (fmaxnum:{ *:[f32] } (VOP3Mods:{ *:[f32] } f32:{ *:[f32] }:$src1, i32:{ *:[i32] }:$src1_mods), (VOP3Mods:{ *:[f32] } f32:{ *:[f32] }:$src0, i32:{ *:[i32] }:$src0_mods)))<<P:Predicate_fminnum_like_nnan>>  =>  (V_MED3_F32_e64:{ *:[f32] } ?:{ *:[i32] }:$src0_mods, ?:{ *:[f32] }:$src0, ?:{ *:[i32] }:$src1_mods, ?:{ *:[f32] }:$src1, ?:{ *:[i32] }:$src2_mods, ?:{ *:[f32] }:$src2, 0:{ *:[i1] }, 0:{ *:[i32] })
        GIR_BuildMI, /*InsnID*/0, /*Opcode*/GIMT_Encode2(AMDGPU::V_MED3_F32_e64),
        GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/0, // DstI[vdst]
        GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(1), /*SubOperand*/1, // src0_mods
        GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(1), /*SubOperand*/0, // src0
        GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(2), /*SubOperand*/1, // src1_mods
        GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(2), /*SubOperand*/0, // src1
        GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/1, // src2_mods
        GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/0, // src2
        GIR_AddImm8, /*InsnID*/0, /*Imm*/0,
        GIR_AddImm8, /*InsnID*/0, /*Imm*/0,
        GIR_ConstrainSelectedInstOperands, /*InsnID*/0,
        GIR_EraseFromParent, /*InsnID*/0,
        // GIR_Coverage, 10342,
        GIR_Done,
      // Label 4812: @333397
      GIM_Try, /*On fail goto*//*Label 4813*/ GIMT_Encode4(333537), // Rule ID 10343 //
        GIM_CheckRegBankForClass, /*MI*/0, /*Op*/0, /*RC*/GIMT_Encode2(AMDGPU::VGPR_32RegClassID),
        GIM_RecordInsn, /*DefineMI*/1, /*MI*/0, /*OpIdx*/1, // MIs[1]
        GIM_CheckOpcode, /*MI*/1, GIMT_Encode2(TargetOpcode::G_FMAXNUM),
        GIM_CheckType, /*MI*/1, /*Op*/1, /*Type*/GILLT_s32,
        GIM_CheckType, /*MI*/1, /*Op*/2, /*Type*/GILLT_s32,
        GIM_RecordInsn, /*DefineMI*/2, /*MI*/1, /*OpIdx*/2, // MIs[2]
        GIM_CheckOpcode, /*MI*/2, GIMT_Encode2(TargetOpcode::G_FMINNUM_IEEE),
        GIM_CheckType, /*MI*/2, /*Op*/1, /*Type*/GILLT_s32,
        GIM_CheckType, /*MI*/2, /*Op*/2, /*Type*/GILLT_s32,
        GIM_RecordInsn, /*DefineMI*/3, /*MI*/0, /*OpIdx*/2, // MIs[3]
        GIM_CheckOpcode, /*MI*/3, GIMT_Encode2(TargetOpcode::G_FMAXNUM),
        // MIs[3] VOP3Mods:src0:src0_mods
        GIM_CheckIsSameOperand, /*MI*/3, /*OpIdx*/1, /*OtherMI*/2, /*OtherOpIdx*/2,
        // MIs[3] VOP3Mods:src1:src1_mods
        GIM_CheckIsSameOperand, /*MI*/3, /*OpIdx*/2, /*OtherMI*/2, /*OtherOpIdx*/1,
        GIM_CheckCxxInsnPredicate, /*MI*/0, /*FnId*/GIMT_Encode2(GICXXPred_MI_Predicate_fminnum_like_nnan),
        GIM_CheckIsSafeToFold, /*InsnID*/1,
        GIM_CheckIsSafeToFold, /*InsnID*/2,
        GIM_CheckIsSafeToFold, /*InsnID*/3,
        GIM_CheckComplexPattern, /*MI*/1, /*Op*/1, /*Renderer*/GIMT_Encode2(0), GIMT_Encode2(GICP_gi_vop3mods),
        GIM_CheckComplexPattern, /*MI*/2, /*Op*/1, /*Renderer*/GIMT_Encode2(1), GIMT_Encode2(GICP_gi_vop3mods),
        GIM_CheckComplexPattern, /*MI*/2, /*Op*/2, /*Renderer*/GIMT_Encode2(2), GIMT_Encode2(GICP_gi_vop3mods),
        // (fminnum_ieee:{ *:[f32] } (fmaxnum:{ *:[f32] } (VOP3Mods:{ *:[f32] } f32:{ *:[f32] }:$src2, i32:{ *:[i32] }:$src2_mods), (fminnum_ieee:{ *:[f32] } (VOP3Mods:{ *:[f32] } f32:{ *:[f32] }:$src1, i32:{ *:[i32] }:$src1_mods), (VOP3Mods:{ *:[f32] } f32:{ *:[f32] }:$src0, i32:{ *:[i32] }:$src0_mods))), (fmaxnum:{ *:[f32] } (VOP3Mods:{ *:[f32] } f32:{ *:[f32] }:$src0, i32:{ *:[i32] }:$src0_mods), (VOP3Mods:{ *:[f32] } f32:{ *:[f32] }:$src1, i32:{ *:[i32] }:$src1_mods)))<<P:Predicate_fminnum_like_nnan>>  =>  (V_MED3_F32_e64:{ *:[f32] } ?:{ *:[i32] }:$src0_mods, ?:{ *:[f32] }:$src0, ?:{ *:[i32] }:$src1_mods, ?:{ *:[f32] }:$src1, ?:{ *:[i32] }:$src2_mods, ?:{ *:[f32] }:$src2, 0:{ *:[i1] }, 0:{ *:[i32] })
        GIR_BuildMI, /*InsnID*/0, /*Opcode*/GIMT_Encode2(AMDGPU::V_MED3_F32_e64),
        GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/0, // DstI[vdst]
        GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(2), /*SubOperand*/1, // src0_mods
        GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(2), /*SubOperand*/0, // src0
        GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(1), /*SubOperand*/1, // src1_mods
        GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(1), /*SubOperand*/0, // src1
        GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/1, // src2_mods
        GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/0, // src2
        GIR_AddImm8, /*InsnID*/0, /*Imm*/0,
        GIR_AddImm8, /*InsnID*/0, /*Imm*/0,
        GIR_ConstrainSelectedInstOperands, /*InsnID*/0,
        GIR_EraseFromParent, /*InsnID*/0,
        // GIR_Coverage, 10343,
        GIR_Done,
      // Label 4813: @333537
      GIM_Try, /*On fail goto*//*Label 4814*/ GIMT_Encode4(333677), // Rule ID 10344 //
        GIM_CheckRegBankForClass, /*MI*/0, /*Op*/0, /*RC*/GIMT_Encode2(AMDGPU::VGPR_32RegClassID),
        GIM_RecordInsn, /*DefineMI*/1, /*MI*/0, /*OpIdx*/1, // MIs[1]
        GIM_CheckOpcode, /*MI*/1, GIMT_Encode2(TargetOpcode::G_FMAXNUM),
        GIM_CheckType, /*MI*/1, /*Op*/1, /*Type*/GILLT_s32,
        GIM_CheckType, /*MI*/1, /*Op*/2, /*Type*/GILLT_s32,
        GIM_RecordInsn, /*DefineMI*/2, /*MI*/1, /*OpIdx*/2, // MIs[2]
        GIM_CheckOpcode, /*MI*/2, GIMT_Encode2(TargetOpcode::G_FMINNUM_IEEE),
        GIM_CheckType, /*MI*/2, /*Op*/1, /*Type*/GILLT_s32,
        GIM_CheckType, /*MI*/2, /*Op*/2, /*Type*/GILLT_s32,
        GIM_RecordInsn, /*DefineMI*/3, /*MI*/0, /*OpIdx*/2, // MIs[3]
        GIM_CheckOpcode, /*MI*/3, GIMT_Encode2(TargetOpcode::G_FMAXNUM),
        // MIs[3] VOP3Mods:src1:src1_mods
        GIM_CheckIsSameOperand, /*MI*/3, /*OpIdx*/1, /*OtherMI*/2, /*OtherOpIdx*/1,
        // MIs[3] VOP3Mods:src0:src0_mods
        GIM_CheckIsSameOperand, /*MI*/3, /*OpIdx*/2, /*OtherMI*/2, /*OtherOpIdx*/2,
        GIM_CheckCxxInsnPredicate, /*MI*/0, /*FnId*/GIMT_Encode2(GICXXPred_MI_Predicate_fminnum_like_nnan),
        GIM_CheckIsSafeToFold, /*InsnID*/1,
        GIM_CheckIsSafeToFold, /*InsnID*/2,
        GIM_CheckIsSafeToFold, /*InsnID*/3,
        GIM_CheckComplexPattern, /*MI*/1, /*Op*/1, /*Renderer*/GIMT_Encode2(0), GIMT_Encode2(GICP_gi_vop3mods),
        GIM_CheckComplexPattern, /*MI*/2, /*Op*/1, /*Renderer*/GIMT_Encode2(1), GIMT_Encode2(GICP_gi_vop3mods),
        GIM_CheckComplexPattern, /*MI*/2, /*Op*/2, /*Renderer*/GIMT_Encode2(2), GIMT_Encode2(GICP_gi_vop3mods),
        // (fminnum_ieee:{ *:[f32] } (fmaxnum:{ *:[f32] } (VOP3Mods:{ *:[f32] } f32:{ *:[f32] }:$src2, i32:{ *:[i32] }:$src2_mods), (fminnum_ieee:{ *:[f32] } (VOP3Mods:{ *:[f32] } f32:{ *:[f32] }:$src1, i32:{ *:[i32] }:$src1_mods), (VOP3Mods:{ *:[f32] } f32:{ *:[f32] }:$src0, i32:{ *:[i32] }:$src0_mods))), (fmaxnum:{ *:[f32] } (VOP3Mods:{ *:[f32] } f32:{ *:[f32] }:$src1, i32:{ *:[i32] }:$src1_mods), (VOP3Mods:{ *:[f32] } f32:{ *:[f32] }:$src0, i32:{ *:[i32] }:$src0_mods)))<<P:Predicate_fminnum_like_nnan>>  =>  (V_MED3_F32_e64:{ *:[f32] } ?:{ *:[i32] }:$src0_mods, ?:{ *:[f32] }:$src0, ?:{ *:[i32] }:$src1_mods, ?:{ *:[f32] }:$src1, ?:{ *:[i32] }:$src2_mods, ?:{ *:[f32] }:$src2, 0:{ *:[i1] }, 0:{ *:[i32] })
        GIR_BuildMI, /*InsnID*/0, /*Opcode*/GIMT_Encode2(AMDGPU::V_MED3_F32_e64),
        GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/0, // DstI[vdst]
        GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(2), /*SubOperand*/1, // src0_mods
        GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(2), /*SubOperand*/0, // src0
        GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(1), /*SubOperand*/1, // src1_mods
        GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(1), /*SubOperand*/0, // src1
        GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/1, // src2_mods
        GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/0, // src2
        GIR_AddImm8, /*InsnID*/0, /*Imm*/0,
        GIR_AddImm8, /*InsnID*/0, /*Imm*/0,
        GIR_ConstrainSelectedInstOperands, /*InsnID*/0,
        GIR_EraseFromParent, /*InsnID*/0,
        // GIR_Coverage, 10344,
        GIR_Done,
      // Label 4814: @333677
      GIM_Try, /*On fail goto*//*Label 4815*/ GIMT_Encode4(333817), // Rule ID 10281 //
        GIM_CheckRegBankForClass, /*MI*/0, /*Op*/0, /*RC*/GIMT_Encode2(AMDGPU::VGPR_32RegClassID),
        GIM_RecordInsn, /*DefineMI*/1, /*MI*/0, /*OpIdx*/1, // MIs[1]
        GIM_CheckOpcode, /*MI*/1, GIMT_Encode2(TargetOpcode::G_FMAXNUM),
        GIM_CheckType, /*MI*/1, /*Op*/1, /*Type*/GILLT_s32,
        GIM_CheckType, /*MI*/1, /*Op*/2, /*Type*/GILLT_s32,
        GIM_RecordInsn, /*DefineMI*/2, /*MI*/1, /*OpIdx*/2, // MIs[2]
        GIM_CheckOpcode, /*MI*/2, GIMT_Encode2(TargetOpcode::G_FMINNUM_IEEE),
        GIM_CheckType, /*MI*/2, /*Op*/1, /*Type*/GILLT_s32,
        GIM_CheckType, /*MI*/2, /*Op*/2, /*Type*/GILLT_s32,
        GIM_RecordInsn, /*DefineMI*/3, /*MI*/0, /*OpIdx*/2, // MIs[3]
        GIM_CheckOpcode, /*MI*/3, GIMT_Encode2(TargetOpcode::G_FMAXNUM_IEEE),
        // MIs[3] VOP3Mods:src0:src0_mods
        GIM_CheckIsSameOperand, /*MI*/3, /*OpIdx*/1, /*OtherMI*/2, /*OtherOpIdx*/1,
        // MIs[3] VOP3Mods:src1:src1_mods
        GIM_CheckIsSameOperand, /*MI*/3, /*OpIdx*/2, /*OtherMI*/2, /*OtherOpIdx*/2,
        GIM_CheckCxxInsnPredicate, /*MI*/0, /*FnId*/GIMT_Encode2(GICXXPred_MI_Predicate_fminnum_like_nnan),
        GIM_CheckIsSafeToFold, /*InsnID*/1,
        GIM_CheckIsSafeToFold, /*InsnID*/2,
        GIM_CheckIsSafeToFold, /*InsnID*/3,
        GIM_CheckComplexPattern, /*MI*/1, /*Op*/1, /*Renderer*/GIMT_Encode2(0), GIMT_Encode2(GICP_gi_vop3mods),
        GIM_CheckComplexPattern, /*MI*/2, /*Op*/1, /*Renderer*/GIMT_Encode2(1), GIMT_Encode2(GICP_gi_vop3mods),
        GIM_CheckComplexPattern, /*MI*/2, /*Op*/2, /*Renderer*/GIMT_Encode2(2), GIMT_Encode2(GICP_gi_vop3mods),
        // (fminnum_ieee:{ *:[f32] } (fmaxnum:{ *:[f32] } (VOP3Mods:{ *:[f32] } f32:{ *:[f32] }:$src2, i32:{ *:[i32] }:$src2_mods), (fminnum_ieee:{ *:[f32] } (VOP3Mods:{ *:[f32] } f32:{ *:[f32] }:$src0, i32:{ *:[i32] }:$src0_mods), (VOP3Mods:{ *:[f32] } f32:{ *:[f32] }:$src1, i32:{ *:[i32] }:$src1_mods))), (fmaxnum_ieee:{ *:[f32] } (VOP3Mods:{ *:[f32] } f32:{ *:[f32] }:$src0, i32:{ *:[i32] }:$src0_mods), (VOP3Mods:{ *:[f32] } f32:{ *:[f32] }:$src1, i32:{ *:[i32] }:$src1_mods)))<<P:Predicate_fminnum_like_nnan>>  =>  (V_MED3_F32_e64:{ *:[f32] } ?:{ *:[i32] }:$src0_mods, ?:{ *:[f32] }:$src0, ?:{ *:[i32] }:$src1_mods, ?:{ *:[f32] }:$src1, ?:{ *:[i32] }:$src2_mods, ?:{ *:[f32] }:$src2, 0:{ *:[i1] }, 0:{ *:[i32] })
        GIR_BuildMI, /*InsnID*/0, /*Opcode*/GIMT_Encode2(AMDGPU::V_MED3_F32_e64),
        GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/0, // DstI[vdst]
        GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(1), /*SubOperand*/1, // src0_mods
        GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(1), /*SubOperand*/0, // src0
        GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(2), /*SubOperand*/1, // src1_mods
        GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(2), /*SubOperand*/0, // src1
        GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/1, // src2_mods
        GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/0, // src2
        GIR_AddImm8, /*InsnID*/0, /*Imm*/0,
        GIR_AddImm8, /*InsnID*/0, /*Imm*/0,
        GIR_ConstrainSelectedInstOperands, /*InsnID*/0,
        GIR_EraseFromParent, /*InsnID*/0,
        // GIR_Coverage, 10281,
        GIR_Done,
      // Label 4815: @333817
      GIM_Try, /*On fail goto*//*Label 4816*/ GIMT_Encode4(333957), // Rule ID 10282 //
        GIM_CheckRegBankForClass, /*MI*/0, /*Op*/0, /*RC*/GIMT_Encode2(AMDGPU::VGPR_32RegClassID),
        GIM_RecordInsn, /*DefineMI*/1, /*MI*/0, /*OpIdx*/1, // MIs[1]
        GIM_CheckOpcode, /*MI*/1, GIMT_Encode2(TargetOpcode::G_FMAXNUM),
        GIM_CheckType, /*MI*/1, /*Op*/1, /*Type*/GILLT_s32,
        GIM_CheckType, /*MI*/1, /*Op*/2, /*Type*/GILLT_s32,
        GIM_RecordInsn, /*DefineMI*/2, /*MI*/1, /*OpIdx*/2, // MIs[2]
        GIM_CheckOpcode, /*MI*/2, GIMT_Encode2(TargetOpcode::G_FMINNUM_IEEE),
        GIM_CheckType, /*MI*/2, /*Op*/1, /*Type*/GILLT_s32,
        GIM_CheckType, /*MI*/2, /*Op*/2, /*Type*/GILLT_s32,
        GIM_RecordInsn, /*DefineMI*/3, /*MI*/0, /*OpIdx*/2, // MIs[3]
        GIM_CheckOpcode, /*MI*/3, GIMT_Encode2(TargetOpcode::G_FMAXNUM_IEEE),
        // MIs[3] VOP3Mods:src1:src1_mods
        GIM_CheckIsSameOperand, /*MI*/3, /*OpIdx*/1, /*OtherMI*/2, /*OtherOpIdx*/2,
        // MIs[3] VOP3Mods:src0:src0_mods
        GIM_CheckIsSameOperand, /*MI*/3, /*OpIdx*/2, /*OtherMI*/2, /*OtherOpIdx*/1,
        GIM_CheckCxxInsnPredicate, /*MI*/0, /*FnId*/GIMT_Encode2(GICXXPred_MI_Predicate_fminnum_like_nnan),
        GIM_CheckIsSafeToFold, /*InsnID*/1,
        GIM_CheckIsSafeToFold, /*InsnID*/2,
        GIM_CheckIsSafeToFold, /*InsnID*/3,
        GIM_CheckComplexPattern, /*MI*/1, /*Op*/1, /*Renderer*/GIMT_Encode2(0), GIMT_Encode2(GICP_gi_vop3mods),
        GIM_CheckComplexPattern, /*MI*/2, /*Op*/1, /*Renderer*/GIMT_Encode2(1), GIMT_Encode2(GICP_gi_vop3mods),
        GIM_CheckComplexPattern, /*MI*/2, /*Op*/2, /*Renderer*/GIMT_Encode2(2), GIMT_Encode2(GICP_gi_vop3mods),
        // (fminnum_ieee:{ *:[f32] } (fmaxnum:{ *:[f32] } (VOP3Mods:{ *:[f32] } f32:{ *:[f32] }:$src2, i32:{ *:[i32] }:$src2_mods), (fminnum_ieee:{ *:[f32] } (VOP3Mods:{ *:[f32] } f32:{ *:[f32] }:$src0, i32:{ *:[i32] }:$src0_mods), (VOP3Mods:{ *:[f32] } f32:{ *:[f32] }:$src1, i32:{ *:[i32] }:$src1_mods))), (fmaxnum_ieee:{ *:[f32] } (VOP3Mods:{ *:[f32] } f32:{ *:[f32] }:$src1, i32:{ *:[i32] }:$src1_mods), (VOP3Mods:{ *:[f32] } f32:{ *:[f32] }:$src0, i32:{ *:[i32] }:$src0_mods)))<<P:Predicate_fminnum_like_nnan>>  =>  (V_MED3_F32_e64:{ *:[f32] } ?:{ *:[i32] }:$src0_mods, ?:{ *:[f32] }:$src0, ?:{ *:[i32] }:$src1_mods, ?:{ *:[f32] }:$src1, ?:{ *:[i32] }:$src2_mods, ?:{ *:[f32] }:$src2, 0:{ *:[i1] }, 0:{ *:[i32] })
        GIR_BuildMI, /*InsnID*/0, /*Opcode*/GIMT_Encode2(AMDGPU::V_MED3_F32_e64),
        GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/0, // DstI[vdst]
        GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(1), /*SubOperand*/1, // src0_mods
        GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(1), /*SubOperand*/0, // src0
        GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(2), /*SubOperand*/1, // src1_mods
        GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(2), /*SubOperand*/0, // src1
        GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/1, // src2_mods
        GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/0, // src2
        GIR_AddImm8, /*InsnID*/0, /*Imm*/0,
        GIR_AddImm8, /*InsnID*/0, /*Imm*/0,
        GIR_ConstrainSelectedInstOperands, /*InsnID*/0,
        GIR_EraseFromParent, /*InsnID*/0,
        // GIR_Coverage, 10282,
        GIR_Done,
      // Label 4816: @333957
      GIM_Try, /*On fail goto*//*Label 4817*/ GIMT_Encode4(334097), // Rule ID 10283 //
        GIM_CheckRegBankForClass, /*MI*/0, /*Op*/0, /*RC*/GIMT_Encode2(AMDGPU::VGPR_32RegClassID),
        GIM_RecordInsn, /*DefineMI*/1, /*MI*/0, /*OpIdx*/1, // MIs[1]
        GIM_CheckOpcode, /*MI*/1, GIMT_Encode2(TargetOpcode::G_FMAXNUM),
        GIM_CheckType, /*MI*/1, /*Op*/1, /*Type*/GILLT_s32,
        GIM_CheckType, /*MI*/1, /*Op*/2, /*Type*/GILLT_s32,
        GIM_RecordInsn, /*DefineMI*/2, /*MI*/1, /*OpIdx*/2, // MIs[2]
        GIM_CheckOpcode, /*MI*/2, GIMT_Encode2(TargetOpcode::G_FMINNUM_IEEE),
        GIM_CheckType, /*MI*/2, /*Op*/1, /*Type*/GILLT_s32,
        GIM_CheckType, /*MI*/2, /*Op*/2, /*Type*/GILLT_s32,
        GIM_RecordInsn, /*DefineMI*/3, /*MI*/0, /*OpIdx*/2, // MIs[3]
        GIM_CheckOpcode, /*MI*/3, GIMT_Encode2(TargetOpcode::G_FMAXNUM_IEEE),
        // MIs[3] VOP3Mods:src0:src0_mods
        GIM_CheckIsSameOperand, /*MI*/3, /*OpIdx*/1, /*OtherMI*/2, /*OtherOpIdx*/2,
        // MIs[3] VOP3Mods:src1:src1_mods
        GIM_CheckIsSameOperand, /*MI*/3, /*OpIdx*/2, /*OtherMI*/2, /*OtherOpIdx*/1,
        GIM_CheckCxxInsnPredicate, /*MI*/0, /*FnId*/GIMT_Encode2(GICXXPred_MI_Predicate_fminnum_like_nnan),
        GIM_CheckIsSafeToFold, /*InsnID*/1,
        GIM_CheckIsSafeToFold, /*InsnID*/2,
        GIM_CheckIsSafeToFold, /*InsnID*/3,
        GIM_CheckComplexPattern, /*MI*/1, /*Op*/1, /*Renderer*/GIMT_Encode2(0), GIMT_Encode2(GICP_gi_vop3mods),
        GIM_CheckComplexPattern, /*MI*/2, /*Op*/1, /*Renderer*/GIMT_Encode2(1), GIMT_Encode2(GICP_gi_vop3mods),
        GIM_CheckComplexPattern, /*MI*/2, /*Op*/2, /*Renderer*/GIMT_Encode2(2), GIMT_Encode2(GICP_gi_vop3mods),
        // (fminnum_ieee:{ *:[f32] } (fmaxnum:{ *:[f32] } (VOP3Mods:{ *:[f32] } f32:{ *:[f32] }:$src2, i32:{ *:[i32] }:$src2_mods), (fminnum_ieee:{ *:[f32] } (VOP3Mods:{ *:[f32] } f32:{ *:[f32] }:$src1, i32:{ *:[i32] }:$src1_mods), (VOP3Mods:{ *:[f32] } f32:{ *:[f32] }:$src0, i32:{ *:[i32] }:$src0_mods))), (fmaxnum_ieee:{ *:[f32] } (VOP3Mods:{ *:[f32] } f32:{ *:[f32] }:$src0, i32:{ *:[i32] }:$src0_mods), (VOP3Mods:{ *:[f32] } f32:{ *:[f32] }:$src1, i32:{ *:[i32] }:$src1_mods)))<<P:Predicate_fminnum_like_nnan>>  =>  (V_MED3_F32_e64:{ *:[f32] } ?:{ *:[i32] }:$src0_mods, ?:{ *:[f32] }:$src0, ?:{ *:[i32] }:$src1_mods, ?:{ *:[f32] }:$src1, ?:{ *:[i32] }:$src2_mods, ?:{ *:[f32] }:$src2, 0:{ *:[i1] }, 0:{ *:[i32] })
        GIR_BuildMI, /*InsnID*/0, /*Opcode*/GIMT_Encode2(AMDGPU::V_MED3_F32_e64),
        GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/0, // DstI[vdst]
        GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(2), /*SubOperand*/1, // src0_mods
        GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(2), /*SubOperand*/0, // src0
        GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(1), /*SubOperand*/1, // src1_mods
        GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(1), /*SubOperand*/0, // src1
        GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/1, // src2_mods
        GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/0, // src2
        GIR_AddImm8, /*InsnID*/0, /*Imm*/0,
        GIR_AddImm8, /*InsnID*/0, /*Imm*/0,
        GIR_ConstrainSelectedInstOperands, /*InsnID*/0,
        GIR_EraseFromParent, /*InsnID*/0,
        // GIR_Coverage, 10283,
        GIR_Done,
      // Label 4817: @334097
      GIM_Try, /*On fail goto*//*Label 4818*/ GIMT_Encode4(334237), // Rule ID 10284 //
        GIM_CheckRegBankForClass, /*MI*/0, /*Op*/0, /*RC*/GIMT_Encode2(AMDGPU::VGPR_32RegClassID),
        GIM_RecordInsn, /*DefineMI*/1, /*MI*/0, /*OpIdx*/1, // MIs[1]
        GIM_CheckOpcode, /*MI*/1, GIMT_Encode2(TargetOpcode::G_FMAXNUM),
        GIM_CheckType, /*MI*/1, /*Op*/1, /*Type*/GILLT_s32,
        GIM_CheckType, /*MI*/1, /*Op*/2, /*Type*/GILLT_s32,
        GIM_RecordInsn, /*DefineMI*/2, /*MI*/1, /*OpIdx*/2, // MIs[2]
        GIM_CheckOpcode, /*MI*/2, GIMT_Encode2(TargetOpcode::G_FMINNUM_IEEE),
        GIM_CheckType, /*MI*/2, /*Op*/1, /*Type*/GILLT_s32,
        GIM_CheckType, /*MI*/2, /*Op*/2, /*Type*/GILLT_s32,
        GIM_RecordInsn, /*DefineMI*/3, /*MI*/0, /*OpIdx*/2, // MIs[3]
        GIM_CheckOpcode, /*MI*/3, GIMT_Encode2(TargetOpcode::G_FMAXNUM_IEEE),
        // MIs[3] VOP3Mods:src1:src1_mods
        GIM_CheckIsSameOperand, /*MI*/3, /*OpIdx*/1, /*OtherMI*/2, /*OtherOpIdx*/1,
        // MIs[3] VOP3Mods:src0:src0_mods
        GIM_CheckIsSameOperand, /*MI*/3, /*OpIdx*/2, /*OtherMI*/2, /*OtherOpIdx*/2,
        GIM_CheckCxxInsnPredicate, /*MI*/0, /*FnId*/GIMT_Encode2(GICXXPred_MI_Predicate_fminnum_like_nnan),
        GIM_CheckIsSafeToFold, /*InsnID*/1,
        GIM_CheckIsSafeToFold, /*InsnID*/2,
        GIM_CheckIsSafeToFold, /*InsnID*/3,
        GIM_CheckComplexPattern, /*MI*/1, /*Op*/1, /*Renderer*/GIMT_Encode2(0), GIMT_Encode2(GICP_gi_vop3mods),
        GIM_CheckComplexPattern, /*MI*/2, /*Op*/1, /*Renderer*/GIMT_Encode2(1), GIMT_Encode2(GICP_gi_vop3mods),
        GIM_CheckComplexPattern, /*MI*/2, /*Op*/2, /*Renderer*/GIMT_Encode2(2), GIMT_Encode2(GICP_gi_vop3mods),
        // (fminnum_ieee:{ *:[f32] } (fmaxnum:{ *:[f32] } (VOP3Mods:{ *:[f32] } f32:{ *:[f32] }:$src2, i32:{ *:[i32] }:$src2_mods), (fminnum_ieee:{ *:[f32] } (VOP3Mods:{ *:[f32] } f32:{ *:[f32] }:$src1, i32:{ *:[i32] }:$src1_mods), (VOP3Mods:{ *:[f32] } f32:{ *:[f32] }:$src0, i32:{ *:[i32] }:$src0_mods))), (fmaxnum_ieee:{ *:[f32] } (VOP3Mods:{ *:[f32] } f32:{ *:[f32] }:$src1, i32:{ *:[i32] }:$src1_mods), (VOP3Mods:{ *:[f32] } f32:{ *:[f32] }:$src0, i32:{ *:[i32] }:$src0_mods)))<<P:Predicate_fminnum_like_nnan>>  =>  (V_MED3_F32_e64:{ *:[f32] } ?:{ *:[i32] }:$src0_mods, ?:{ *:[f32] }:$src0, ?:{ *:[i32] }:$src1_mods, ?:{ *:[f32] }:$src1, ?:{ *:[i32] }:$src2_mods, ?:{ *:[f32] }:$src2, 0:{ *:[i1] }, 0:{ *:[i32] })
        GIR_BuildMI, /*InsnID*/0, /*Opcode*/GIMT_Encode2(AMDGPU::V_MED3_F32_e64),
        GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/0, // DstI[vdst]
        GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(2), /*SubOperand*/1, // src0_mods
        GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(2), /*SubOperand*/0, // src0
        GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(1), /*SubOperand*/1, // src1_mods
        GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(1), /*SubOperand*/0, // src1
        GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/1, // src2_mods
        GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/0, // src2
        GIR_AddImm8, /*InsnID*/0, /*Imm*/0,
        GIR_AddImm8, /*InsnID*/0, /*Imm*/0,
        GIR_ConstrainSelectedInstOperands, /*InsnID*/0,
        GIR_EraseFromParent, /*InsnID*/0,
        // GIR_Coverage, 10284,
        GIR_Done,
      // Label 4818: @334237
      GIM_Try, /*On fail goto*//*Label 4819*/ GIMT_Encode4(334377), // Rule ID 10352 //
        GIM_CheckRegBankForClass, /*MI*/0, /*Op*/0, /*RC*/GIMT_Encode2(AMDGPU::VGPR_32RegClassID),
        GIM_RecordInsn, /*DefineMI*/1, /*MI*/0, /*OpIdx*/1, // MIs[1]
        GIM_CheckOpcode, /*MI*/1, GIMT_Encode2(TargetOpcode::G_FMAXNUM),
        GIM_CheckType, /*MI*/1, /*Op*/1, /*Type*/GILLT_s32,
        GIM_CheckType, /*MI*/1, /*Op*/2, /*Type*/GILLT_s32,
        GIM_RecordInsn, /*DefineMI*/2, /*MI*/1, /*OpIdx*/1, // MIs[2]
        GIM_CheckOpcode, /*MI*/2, GIMT_Encode2(TargetOpcode::G_FMINNUM),
        GIM_CheckType, /*MI*/2, /*Op*/1, /*Type*/GILLT_s32,
        GIM_CheckType, /*MI*/2, /*Op*/2, /*Type*/GILLT_s32,
        GIM_RecordInsn, /*DefineMI*/3, /*MI*/0, /*OpIdx*/2, // MIs[3]
        GIM_CheckOpcode, /*MI*/3, GIMT_Encode2(TargetOpcode::G_FMAXNUM),
        // MIs[3] VOP3Mods:src0:src0_mods
        GIM_CheckIsSameOperand, /*MI*/3, /*OpIdx*/1, /*OtherMI*/2, /*OtherOpIdx*/1,
        // MIs[3] VOP3Mods:src1:src1_mods
        GIM_CheckIsSameOperand, /*MI*/3, /*OpIdx*/2, /*OtherMI*/2, /*OtherOpIdx*/2,
        GIM_CheckCxxInsnPredicate, /*MI*/0, /*FnId*/GIMT_Encode2(GICXXPred_MI_Predicate_fminnum_like_nnan),
        GIM_CheckIsSafeToFold, /*InsnID*/1,
        GIM_CheckIsSafeToFold, /*InsnID*/2,
        GIM_CheckIsSafeToFold, /*InsnID*/3,
        GIM_CheckComplexPattern, /*MI*/1, /*Op*/2, /*Renderer*/GIMT_Encode2(2), GIMT_Encode2(GICP_gi_vop3mods),
        GIM_CheckComplexPattern, /*MI*/2, /*Op*/1, /*Renderer*/GIMT_Encode2(0), GIMT_Encode2(GICP_gi_vop3mods),
        GIM_CheckComplexPattern, /*MI*/2, /*Op*/2, /*Renderer*/GIMT_Encode2(1), GIMT_Encode2(GICP_gi_vop3mods),
        // (fminnum_ieee:{ *:[f32] } (fmaxnum:{ *:[f32] } (fminnum:{ *:[f32] } (VOP3Mods:{ *:[f32] } f32:{ *:[f32] }:$src0, i32:{ *:[i32] }:$src0_mods), (VOP3Mods:{ *:[f32] } f32:{ *:[f32] }:$src1, i32:{ *:[i32] }:$src1_mods)), (VOP3Mods:{ *:[f32] } f32:{ *:[f32] }:$src2, i32:{ *:[i32] }:$src2_mods)), (fmaxnum:{ *:[f32] } (VOP3Mods:{ *:[f32] } f32:{ *:[f32] }:$src0, i32:{ *:[i32] }:$src0_mods), (VOP3Mods:{ *:[f32] } f32:{ *:[f32] }:$src1, i32:{ *:[i32] }:$src1_mods)))<<P:Predicate_fminnum_like_nnan>>  =>  (V_MED3_F32_e64:{ *:[f32] } ?:{ *:[i32] }:$src0_mods, ?:{ *:[f32] }:$src0, ?:{ *:[i32] }:$src1_mods, ?:{ *:[f32] }:$src1, ?:{ *:[i32] }:$src2_mods, ?:{ *:[f32] }:$src2, 0:{ *:[i1] }, 0:{ *:[i32] })
        GIR_BuildMI, /*InsnID*/0, /*Opcode*/GIMT_Encode2(AMDGPU::V_MED3_F32_e64),
        GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/0, // DstI[vdst]
        GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/1, // src0_mods
        GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/0, // src0
        GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(1), /*SubOperand*/1, // src1_mods
        GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(1), /*SubOperand*/0, // src1
        GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(2), /*SubOperand*/1, // src2_mods
        GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(2), /*SubOperand*/0, // src2
        GIR_AddImm8, /*InsnID*/0, /*Imm*/0,
        GIR_AddImm8, /*InsnID*/0, /*Imm*/0,
        GIR_ConstrainSelectedInstOperands, /*InsnID*/0,
        GIR_EraseFromParent, /*InsnID*/0,
        // GIR_Coverage, 10352,
        GIR_Done,
      // Label 4819: @334377
      GIM_Try, /*On fail goto*//*Label 4820*/ GIMT_Encode4(334517), // Rule ID 10353 //
        GIM_CheckRegBankForClass, /*MI*/0, /*Op*/0, /*RC*/GIMT_Encode2(AMDGPU::VGPR_32RegClassID),
        GIM_RecordInsn, /*DefineMI*/1, /*MI*/0, /*OpIdx*/1, // MIs[1]
        GIM_CheckOpcode, /*MI*/1, GIMT_Encode2(TargetOpcode::G_FMAXNUM),
        GIM_CheckType, /*MI*/1, /*Op*/1, /*Type*/GILLT_s32,
        GIM_CheckType, /*MI*/1, /*Op*/2, /*Type*/GILLT_s32,
        GIM_RecordInsn, /*DefineMI*/2, /*MI*/1, /*OpIdx*/1, // MIs[2]
        GIM_CheckOpcode, /*MI*/2, GIMT_Encode2(TargetOpcode::G_FMINNUM),
        GIM_CheckType, /*MI*/2, /*Op*/1, /*Type*/GILLT_s32,
        GIM_CheckType, /*MI*/2, /*Op*/2, /*Type*/GILLT_s32,
        GIM_RecordInsn, /*DefineMI*/3, /*MI*/0, /*OpIdx*/2, // MIs[3]
        GIM_CheckOpcode, /*MI*/3, GIMT_Encode2(TargetOpcode::G_FMAXNUM),
        // MIs[3] VOP3Mods:src1:src1_mods
        GIM_CheckIsSameOperand, /*MI*/3, /*OpIdx*/1, /*OtherMI*/2, /*OtherOpIdx*/2,
        // MIs[3] VOP3Mods:src0:src0_mods
        GIM_CheckIsSameOperand, /*MI*/3, /*OpIdx*/2, /*OtherMI*/2, /*OtherOpIdx*/1,
        GIM_CheckCxxInsnPredicate, /*MI*/0, /*FnId*/GIMT_Encode2(GICXXPred_MI_Predicate_fminnum_like_nnan),
        GIM_CheckIsSafeToFold, /*InsnID*/1,
        GIM_CheckIsSafeToFold, /*InsnID*/2,
        GIM_CheckIsSafeToFold, /*InsnID*/3,
        GIM_CheckComplexPattern, /*MI*/1, /*Op*/2, /*Renderer*/GIMT_Encode2(2), GIMT_Encode2(GICP_gi_vop3mods),
        GIM_CheckComplexPattern, /*MI*/2, /*Op*/1, /*Renderer*/GIMT_Encode2(0), GIMT_Encode2(GICP_gi_vop3mods),
        GIM_CheckComplexPattern, /*MI*/2, /*Op*/2, /*Renderer*/GIMT_Encode2(1), GIMT_Encode2(GICP_gi_vop3mods),
        // (fminnum_ieee:{ *:[f32] } (fmaxnum:{ *:[f32] } (fminnum:{ *:[f32] } (VOP3Mods:{ *:[f32] } f32:{ *:[f32] }:$src0, i32:{ *:[i32] }:$src0_mods), (VOP3Mods:{ *:[f32] } f32:{ *:[f32] }:$src1, i32:{ *:[i32] }:$src1_mods)), (VOP3Mods:{ *:[f32] } f32:{ *:[f32] }:$src2, i32:{ *:[i32] }:$src2_mods)), (fmaxnum:{ *:[f32] } (VOP3Mods:{ *:[f32] } f32:{ *:[f32] }:$src1, i32:{ *:[i32] }:$src1_mods), (VOP3Mods:{ *:[f32] } f32:{ *:[f32] }:$src0, i32:{ *:[i32] }:$src0_mods)))<<P:Predicate_fminnum_like_nnan>>  =>  (V_MED3_F32_e64:{ *:[f32] } ?:{ *:[i32] }:$src0_mods, ?:{ *:[f32] }:$src0, ?:{ *:[i32] }:$src1_mods, ?:{ *:[f32] }:$src1, ?:{ *:[i32] }:$src2_mods, ?:{ *:[f32] }:$src2, 0:{ *:[i1] }, 0:{ *:[i32] })
        GIR_BuildMI, /*InsnID*/0, /*Opcode*/GIMT_Encode2(AMDGPU::V_MED3_F32_e64),
        GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/0, // DstI[vdst]
        GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/1, // src0_mods
        GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/0, // src0
        GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(1), /*SubOperand*/1, // src1_mods
        GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(1), /*SubOperand*/0, // src1
        GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(2), /*SubOperand*/1, // src2_mods
        GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(2), /*SubOperand*/0, // src2
        GIR_AddImm8, /*InsnID*/0, /*Imm*/0,
        GIR_AddImm8, /*InsnID*/0, /*Imm*/0,
        GIR_ConstrainSelectedInstOperands, /*InsnID*/0,
        GIR_EraseFromParent, /*InsnID*/0,
        // GIR_Coverage, 10353,
        GIR_Done,
      // Label 4820: @334517
      GIM_Try, /*On fail goto*//*Label 4821*/ GIMT_Encode4(334657), // Rule ID 10354 //
        GIM_CheckRegBankForClass, /*MI*/0, /*Op*/0, /*RC*/GIMT_Encode2(AMDGPU::VGPR_32RegClassID),
        GIM_RecordInsn, /*DefineMI*/1, /*MI*/0, /*OpIdx*/1, // MIs[1]
        GIM_CheckOpcode, /*MI*/1, GIMT_Encode2(TargetOpcode::G_FMAXNUM),
        GIM_CheckType, /*MI*/1, /*Op*/1, /*Type*/GILLT_s32,
        GIM_CheckType, /*MI*/1, /*Op*/2, /*Type*/GILLT_s32,
        GIM_RecordInsn, /*DefineMI*/2, /*MI*/1, /*OpIdx*/1, // MIs[2]
        GIM_CheckOpcode, /*MI*/2, GIMT_Encode2(TargetOpcode::G_FMINNUM),
        GIM_CheckType, /*MI*/2, /*Op*/1, /*Type*/GILLT_s32,
        GIM_CheckType, /*MI*/2, /*Op*/2, /*Type*/GILLT_s32,
        GIM_RecordInsn, /*DefineMI*/3, /*MI*/0, /*OpIdx*/2, // MIs[3]
        GIM_CheckOpcode, /*MI*/3, GIMT_Encode2(TargetOpcode::G_FMAXNUM),
        // MIs[3] VOP3Mods:src0:src0_mods
        GIM_CheckIsSameOperand, /*MI*/3, /*OpIdx*/1, /*OtherMI*/2, /*OtherOpIdx*/2,
        // MIs[3] VOP3Mods:src1:src1_mods
        GIM_CheckIsSameOperand, /*MI*/3, /*OpIdx*/2, /*OtherMI*/2, /*OtherOpIdx*/1,
        GIM_CheckCxxInsnPredicate, /*MI*/0, /*FnId*/GIMT_Encode2(GICXXPred_MI_Predicate_fminnum_like_nnan),
        GIM_CheckIsSafeToFold, /*InsnID*/1,
        GIM_CheckIsSafeToFold, /*InsnID*/2,
        GIM_CheckIsSafeToFold, /*InsnID*/3,
        GIM_CheckComplexPattern, /*MI*/1, /*Op*/2, /*Renderer*/GIMT_Encode2(2), GIMT_Encode2(GICP_gi_vop3mods),
        GIM_CheckComplexPattern, /*MI*/2, /*Op*/1, /*Renderer*/GIMT_Encode2(0), GIMT_Encode2(GICP_gi_vop3mods),
        GIM_CheckComplexPattern, /*MI*/2, /*Op*/2, /*Renderer*/GIMT_Encode2(1), GIMT_Encode2(GICP_gi_vop3mods),
        // (fminnum_ieee:{ *:[f32] } (fmaxnum:{ *:[f32] } (fminnum:{ *:[f32] } (VOP3Mods:{ *:[f32] } f32:{ *:[f32] }:$src1, i32:{ *:[i32] }:$src1_mods), (VOP3Mods:{ *:[f32] } f32:{ *:[f32] }:$src0, i32:{ *:[i32] }:$src0_mods)), (VOP3Mods:{ *:[f32] } f32:{ *:[f32] }:$src2, i32:{ *:[i32] }:$src2_mods)), (fmaxnum:{ *:[f32] } (VOP3Mods:{ *:[f32] } f32:{ *:[f32] }:$src0, i32:{ *:[i32] }:$src0_mods), (VOP3Mods:{ *:[f32] } f32:{ *:[f32] }:$src1, i32:{ *:[i32] }:$src1_mods)))<<P:Predicate_fminnum_like_nnan>>  =>  (V_MED3_F32_e64:{ *:[f32] } ?:{ *:[i32] }:$src0_mods, ?:{ *:[f32] }:$src0, ?:{ *:[i32] }:$src1_mods, ?:{ *:[f32] }:$src1, ?:{ *:[i32] }:$src2_mods, ?:{ *:[f32] }:$src2, 0:{ *:[i1] }, 0:{ *:[i32] })
        GIR_BuildMI, /*InsnID*/0, /*Opcode*/GIMT_Encode2(AMDGPU::V_MED3_F32_e64),
        GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/0, // DstI[vdst]
        GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(1), /*SubOperand*/1, // src0_mods
        GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(1), /*SubOperand*/0, // src0
        GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/1, // src1_mods
        GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/0, // src1
        GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(2), /*SubOperand*/1, // src2_mods
        GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(2), /*SubOperand*/0, // src2
        GIR_AddImm8, /*InsnID*/0, /*Imm*/0,
        GIR_AddImm8, /*InsnID*/0, /*Imm*/0,
        GIR_ConstrainSelectedInstOperands, /*InsnID*/0,
        GIR_EraseFromParent, /*InsnID*/0,
        // GIR_Coverage, 10354,
        GIR_Done,
      // Label 4821: @334657
      GIM_Try, /*On fail goto*//*Label 4822*/ GIMT_Encode4(334797), // Rule ID 10355 //
        GIM_CheckRegBankForClass, /*MI*/0, /*Op*/0, /*RC*/GIMT_Encode2(AMDGPU::VGPR_32RegClassID),
        GIM_RecordInsn, /*DefineMI*/1, /*MI*/0, /*OpIdx*/1, // MIs[1]
        GIM_CheckOpcode, /*MI*/1, GIMT_Encode2(TargetOpcode::G_FMAXNUM),
        GIM_CheckType, /*MI*/1, /*Op*/1, /*Type*/GILLT_s32,
        GIM_CheckType, /*MI*/1, /*Op*/2, /*Type*/GILLT_s32,
        GIM_RecordInsn, /*DefineMI*/2, /*MI*/1, /*OpIdx*/1, // MIs[2]
        GIM_CheckOpcode, /*MI*/2, GIMT_Encode2(TargetOpcode::G_FMINNUM),
        GIM_CheckType, /*MI*/2, /*Op*/1, /*Type*/GILLT_s32,
        GIM_CheckType, /*MI*/2, /*Op*/2, /*Type*/GILLT_s32,
        GIM_RecordInsn, /*DefineMI*/3, /*MI*/0, /*OpIdx*/2, // MIs[3]
        GIM_CheckOpcode, /*MI*/3, GIMT_Encode2(TargetOpcode::G_FMAXNUM),
        // MIs[3] VOP3Mods:src1:src1_mods
        GIM_CheckIsSameOperand, /*MI*/3, /*OpIdx*/1, /*OtherMI*/2, /*OtherOpIdx*/1,
        // MIs[3] VOP3Mods:src0:src0_mods
        GIM_CheckIsSameOperand, /*MI*/3, /*OpIdx*/2, /*OtherMI*/2, /*OtherOpIdx*/2,
        GIM_CheckCxxInsnPredicate, /*MI*/0, /*FnId*/GIMT_Encode2(GICXXPred_MI_Predicate_fminnum_like_nnan),
        GIM_CheckIsSafeToFold, /*InsnID*/1,
        GIM_CheckIsSafeToFold, /*InsnID*/2,
        GIM_CheckIsSafeToFold, /*InsnID*/3,
        GIM_CheckComplexPattern, /*MI*/1, /*Op*/2, /*Renderer*/GIMT_Encode2(2), GIMT_Encode2(GICP_gi_vop3mods),
        GIM_CheckComplexPattern, /*MI*/2, /*Op*/1, /*Renderer*/GIMT_Encode2(0), GIMT_Encode2(GICP_gi_vop3mods),
        GIM_CheckComplexPattern, /*MI*/2, /*Op*/2, /*Renderer*/GIMT_Encode2(1), GIMT_Encode2(GICP_gi_vop3mods),
        // (fminnum_ieee:{ *:[f32] } (fmaxnum:{ *:[f32] } (fminnum:{ *:[f32] } (VOP3Mods:{ *:[f32] } f32:{ *:[f32] }:$src1, i32:{ *:[i32] }:$src1_mods), (VOP3Mods:{ *:[f32] } f32:{ *:[f32] }:$src0, i32:{ *:[i32] }:$src0_mods)), (VOP3Mods:{ *:[f32] } f32:{ *:[f32] }:$src2, i32:{ *:[i32] }:$src2_mods)), (fmaxnum:{ *:[f32] } (VOP3Mods:{ *:[f32] } f32:{ *:[f32] }:$src1, i32:{ *:[i32] }:$src1_mods), (VOP3Mods:{ *:[f32] } f32:{ *:[f32] }:$src0, i32:{ *:[i32] }:$src0_mods)))<<P:Predicate_fminnum_like_nnan>>  =>  (V_MED3_F32_e64:{ *:[f32] } ?:{ *:[i32] }:$src0_mods, ?:{ *:[f32] }:$src0, ?:{ *:[i32] }:$src1_mods, ?:{ *:[f32] }:$src1, ?:{ *:[i32] }:$src2_mods, ?:{ *:[f32] }:$src2, 0:{ *:[i1] }, 0:{ *:[i32] })
        GIR_BuildMI, /*InsnID*/0, /*Opcode*/GIMT_Encode2(AMDGPU::V_MED3_F32_e64),
        GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/0, // DstI[vdst]
        GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(1), /*SubOperand*/1, // src0_mods
        GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(1), /*SubOperand*/0, // src0
        GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/1, // src1_mods
        GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/0, // src1
        GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(2), /*SubOperand*/1, // src2_mods
        GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(2), /*SubOperand*/0, // src2
        GIR_AddImm8, /*InsnID*/0, /*Imm*/0,
        GIR_AddImm8, /*InsnID*/0, /*Imm*/0,
        GIR_ConstrainSelectedInstOperands, /*InsnID*/0,
        GIR_EraseFromParent, /*InsnID*/0,
        // GIR_Coverage, 10355,
        GIR_Done,
      // Label 4822: @334797
      GIM_Try, /*On fail goto*//*Label 4823*/ GIMT_Encode4(334937), // Rule ID 10292 //
        GIM_CheckRegBankForClass, /*MI*/0, /*Op*/0, /*RC*/GIMT_Encode2(AMDGPU::VGPR_32RegClassID),
        GIM_RecordInsn, /*DefineMI*/1, /*MI*/0, /*OpIdx*/1, // MIs[1]
        GIM_CheckOpcode, /*MI*/1, GIMT_Encode2(TargetOpcode::G_FMAXNUM),
        GIM_CheckType, /*MI*/1, /*Op*/1, /*Type*/GILLT_s32,
        GIM_CheckType, /*MI*/1, /*Op*/2, /*Type*/GILLT_s32,
        GIM_RecordInsn, /*DefineMI*/2, /*MI*/1, /*OpIdx*/1, // MIs[2]
        GIM_CheckOpcode, /*MI*/2, GIMT_Encode2(TargetOpcode::G_FMINNUM),
        GIM_CheckType, /*MI*/2, /*Op*/1, /*Type*/GILLT_s32,
        GIM_CheckType, /*MI*/2, /*Op*/2, /*Type*/GILLT_s32,
        GIM_RecordInsn, /*DefineMI*/3, /*MI*/0, /*OpIdx*/2, // MIs[3]
        GIM_CheckOpcode, /*MI*/3, GIMT_Encode2(TargetOpcode::G_FMAXNUM_IEEE),
        // MIs[3] VOP3Mods:src0:src0_mods
        GIM_CheckIsSameOperand, /*MI*/3, /*OpIdx*/1, /*OtherMI*/2, /*OtherOpIdx*/1,
        // MIs[3] VOP3Mods:src1:src1_mods
        GIM_CheckIsSameOperand, /*MI*/3, /*OpIdx*/2, /*OtherMI*/2, /*OtherOpIdx*/2,
        GIM_CheckCxxInsnPredicate, /*MI*/0, /*FnId*/GIMT_Encode2(GICXXPred_MI_Predicate_fminnum_like_nnan),
        GIM_CheckIsSafeToFold, /*InsnID*/1,
        GIM_CheckIsSafeToFold, /*InsnID*/2,
        GIM_CheckIsSafeToFold, /*InsnID*/3,
        GIM_CheckComplexPattern, /*MI*/1, /*Op*/2, /*Renderer*/GIMT_Encode2(2), GIMT_Encode2(GICP_gi_vop3mods),
        GIM_CheckComplexPattern, /*MI*/2, /*Op*/1, /*Renderer*/GIMT_Encode2(0), GIMT_Encode2(GICP_gi_vop3mods),
        GIM_CheckComplexPattern, /*MI*/2, /*Op*/2, /*Renderer*/GIMT_Encode2(1), GIMT_Encode2(GICP_gi_vop3mods),
        // (fminnum_ieee:{ *:[f32] } (fmaxnum:{ *:[f32] } (fminnum:{ *:[f32] } (VOP3Mods:{ *:[f32] } f32:{ *:[f32] }:$src0, i32:{ *:[i32] }:$src0_mods), (VOP3Mods:{ *:[f32] } f32:{ *:[f32] }:$src1, i32:{ *:[i32] }:$src1_mods)), (VOP3Mods:{ *:[f32] } f32:{ *:[f32] }:$src2, i32:{ *:[i32] }:$src2_mods)), (fmaxnum_ieee:{ *:[f32] } (VOP3Mods:{ *:[f32] } f32:{ *:[f32] }:$src0, i32:{ *:[i32] }:$src0_mods), (VOP3Mods:{ *:[f32] } f32:{ *:[f32] }:$src1, i32:{ *:[i32] }:$src1_mods)))<<P:Predicate_fminnum_like_nnan>>  =>  (V_MED3_F32_e64:{ *:[f32] } ?:{ *:[i32] }:$src0_mods, ?:{ *:[f32] }:$src0, ?:{ *:[i32] }:$src1_mods, ?:{ *:[f32] }:$src1, ?:{ *:[i32] }:$src2_mods, ?:{ *:[f32] }:$src2, 0:{ *:[i1] }, 0:{ *:[i32] })
        GIR_BuildMI, /*InsnID*/0, /*Opcode*/GIMT_Encode2(AMDGPU::V_MED3_F32_e64),
        GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/0, // DstI[vdst]
        GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/1, // src0_mods
        GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/0, // src0
        GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(1), /*SubOperand*/1, // src1_mods
        GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(1), /*SubOperand*/0, // src1
        GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(2), /*SubOperand*/1, // src2_mods
        GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(2), /*SubOperand*/0, // src2
        GIR_AddImm8, /*InsnID*/0, /*Imm*/0,
        GIR_AddImm8, /*InsnID*/0, /*Imm*/0,
        GIR_ConstrainSelectedInstOperands, /*InsnID*/0,
        GIR_EraseFromParent, /*InsnID*/0,
        // GIR_Coverage, 10292,
        GIR_Done,
      // Label 4823: @334937
      GIM_Try, /*On fail goto*//*Label 4824*/ GIMT_Encode4(335077), // Rule ID 10293 //
        GIM_CheckRegBankForClass, /*MI*/0, /*Op*/0, /*RC*/GIMT_Encode2(AMDGPU::VGPR_32RegClassID),
        GIM_RecordInsn, /*DefineMI*/1, /*MI*/0, /*OpIdx*/1, // MIs[1]
        GIM_CheckOpcode, /*MI*/1, GIMT_Encode2(TargetOpcode::G_FMAXNUM),
        GIM_CheckType, /*MI*/1, /*Op*/1, /*Type*/GILLT_s32,
        GIM_CheckType, /*MI*/1, /*Op*/2, /*Type*/GILLT_s32,
        GIM_RecordInsn, /*DefineMI*/2, /*MI*/1, /*OpIdx*/1, // MIs[2]
        GIM_CheckOpcode, /*MI*/2, GIMT_Encode2(TargetOpcode::G_FMINNUM),
        GIM_CheckType, /*MI*/2, /*Op*/1, /*Type*/GILLT_s32,
        GIM_CheckType, /*MI*/2, /*Op*/2, /*Type*/GILLT_s32,
        GIM_RecordInsn, /*DefineMI*/3, /*MI*/0, /*OpIdx*/2, // MIs[3]
        GIM_CheckOpcode, /*MI*/3, GIMT_Encode2(TargetOpcode::G_FMAXNUM_IEEE),
        // MIs[3] VOP3Mods:src1:src1_mods
        GIM_CheckIsSameOperand, /*MI*/3, /*OpIdx*/1, /*OtherMI*/2, /*OtherOpIdx*/2,
        // MIs[3] VOP3Mods:src0:src0_mods
        GIM_CheckIsSameOperand, /*MI*/3, /*OpIdx*/2, /*OtherMI*/2, /*OtherOpIdx*/1,
        GIM_CheckCxxInsnPredicate, /*MI*/0, /*FnId*/GIMT_Encode2(GICXXPred_MI_Predicate_fminnum_like_nnan),
        GIM_CheckIsSafeToFold, /*InsnID*/1,
        GIM_CheckIsSafeToFold, /*InsnID*/2,
        GIM_CheckIsSafeToFold, /*InsnID*/3,
        GIM_CheckComplexPattern, /*MI*/1, /*Op*/2, /*Renderer*/GIMT_Encode2(2), GIMT_Encode2(GICP_gi_vop3mods),
        GIM_CheckComplexPattern, /*MI*/2, /*Op*/1, /*Renderer*/GIMT_Encode2(0), GIMT_Encode2(GICP_gi_vop3mods),
        GIM_CheckComplexPattern, /*MI*/2, /*Op*/2, /*Renderer*/GIMT_Encode2(1), GIMT_Encode2(GICP_gi_vop3mods),
        // (fminnum_ieee:{ *:[f32] } (fmaxnum:{ *:[f32] } (fminnum:{ *:[f32] } (VOP3Mods:{ *:[f32] } f32:{ *:[f32] }:$src0, i32:{ *:[i32] }:$src0_mods), (VOP3Mods:{ *:[f32] } f32:{ *:[f32] }:$src1, i32:{ *:[i32] }:$src1_mods)), (VOP3Mods:{ *:[f32] } f32:{ *:[f32] }:$src2, i32:{ *:[i32] }:$src2_mods)), (fmaxnum_ieee:{ *:[f32] } (VOP3Mods:{ *:[f32] } f32:{ *:[f32] }:$src1, i32:{ *:[i32] }:$src1_mods), (VOP3Mods:{ *:[f32] } f32:{ *:[f32] }:$src0, i32:{ *:[i32] }:$src0_mods)))<<P:Predicate_fminnum_like_nnan>>  =>  (V_MED3_F32_e64:{ *:[f32] } ?:{ *:[i32] }:$src0_mods, ?:{ *:[f32] }:$src0, ?:{ *:[i32] }:$src1_mods, ?:{ *:[f32] }:$src1, ?:{ *:[i32] }:$src2_mods, ?:{ *:[f32] }:$src2, 0:{ *:[i1] }, 0:{ *:[i32] })
        GIR_BuildMI, /*InsnID*/0, /*Opcode*/GIMT_Encode2(AMDGPU::V_MED3_F32_e64),
        GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/0, // DstI[vdst]
        GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/1, // src0_mods
        GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/0, // src0
        GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(1), /*SubOperand*/1, // src1_mods
        GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(1), /*SubOperand*/0, // src1
        GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(2), /*SubOperand*/1, // src2_mods
        GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(2), /*SubOperand*/0, // src2
        GIR_AddImm8, /*InsnID*/0, /*Imm*/0,
        GIR_AddImm8, /*InsnID*/0, /*Imm*/0,
        GIR_ConstrainSelectedInstOperands, /*InsnID*/0,
        GIR_EraseFromParent, /*InsnID*/0,
        // GIR_Coverage, 10293,
        GIR_Done,
      // Label 4824: @335077
      GIM_Try, /*On fail goto*//*Label 4825*/ GIMT_Encode4(335217), // Rule ID 10294 //
        GIM_CheckRegBankForClass, /*MI*/0, /*Op*/0, /*RC*/GIMT_Encode2(AMDGPU::VGPR_32RegClassID),
        GIM_RecordInsn, /*DefineMI*/1, /*MI*/0, /*OpIdx*/1, // MIs[1]
        GIM_CheckOpcode, /*MI*/1, GIMT_Encode2(TargetOpcode::G_FMAXNUM),
        GIM_CheckType, /*MI*/1, /*Op*/1, /*Type*/GILLT_s32,
        GIM_CheckType, /*MI*/1, /*Op*/2, /*Type*/GILLT_s32,
        GIM_RecordInsn, /*DefineMI*/2, /*MI*/1, /*OpIdx*/1, // MIs[2]
        GIM_CheckOpcode, /*MI*/2, GIMT_Encode2(TargetOpcode::G_FMINNUM),
        GIM_CheckType, /*MI*/2, /*Op*/1, /*Type*/GILLT_s32,
        GIM_CheckType, /*MI*/2, /*Op*/2, /*Type*/GILLT_s32,
        GIM_RecordInsn, /*DefineMI*/3, /*MI*/0, /*OpIdx*/2, // MIs[3]
        GIM_CheckOpcode, /*MI*/3, GIMT_Encode2(TargetOpcode::G_FMAXNUM_IEEE),
        // MIs[3] VOP3Mods:src0:src0_mods
        GIM_CheckIsSameOperand, /*MI*/3, /*OpIdx*/1, /*OtherMI*/2, /*OtherOpIdx*/2,
        // MIs[3] VOP3Mods:src1:src1_mods
        GIM_CheckIsSameOperand, /*MI*/3, /*OpIdx*/2, /*OtherMI*/2, /*OtherOpIdx*/1,
        GIM_CheckCxxInsnPredicate, /*MI*/0, /*FnId*/GIMT_Encode2(GICXXPred_MI_Predicate_fminnum_like_nnan),
        GIM_CheckIsSafeToFold, /*InsnID*/1,
        GIM_CheckIsSafeToFold, /*InsnID*/2,
        GIM_CheckIsSafeToFold, /*InsnID*/3,
        GIM_CheckComplexPattern, /*MI*/1, /*Op*/2, /*Renderer*/GIMT_Encode2(2), GIMT_Encode2(GICP_gi_vop3mods),
        GIM_CheckComplexPattern, /*MI*/2, /*Op*/1, /*Renderer*/GIMT_Encode2(0), GIMT_Encode2(GICP_gi_vop3mods),
        GIM_CheckComplexPattern, /*MI*/2, /*Op*/2, /*Renderer*/GIMT_Encode2(1), GIMT_Encode2(GICP_gi_vop3mods),
        // (fminnum_ieee:{ *:[f32] } (fmaxnum:{ *:[f32] } (fminnum:{ *:[f32] } (VOP3Mods:{ *:[f32] } f32:{ *:[f32] }:$src1, i32:{ *:[i32] }:$src1_mods), (VOP3Mods:{ *:[f32] } f32:{ *:[f32] }:$src0, i32:{ *:[i32] }:$src0_mods)), (VOP3Mods:{ *:[f32] } f32:{ *:[f32] }:$src2, i32:{ *:[i32] }:$src2_mods)), (fmaxnum_ieee:{ *:[f32] } (VOP3Mods:{ *:[f32] } f32:{ *:[f32] }:$src0, i32:{ *:[i32] }:$src0_mods), (VOP3Mods:{ *:[f32] } f32:{ *:[f32] }:$src1, i32:{ *:[i32] }:$src1_mods)))<<P:Predicate_fminnum_like_nnan>>  =>  (V_MED3_F32_e64:{ *:[f32] } ?:{ *:[i32] }:$src0_mods, ?:{ *:[f32] }:$src0, ?:{ *:[i32] }:$src1_mods, ?:{ *:[f32] }:$src1, ?:{ *:[i32] }:$src2_mods, ?:{ *:[f32] }:$src2, 0:{ *:[i1] }, 0:{ *:[i32] })
        GIR_BuildMI, /*InsnID*/0, /*Opcode*/GIMT_Encode2(AMDGPU::V_MED3_F32_e64),
        GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/0, // DstI[vdst]
        GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(1), /*SubOperand*/1, // src0_mods
        GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(1), /*SubOperand*/0, // src0
        GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/1, // src1_mods
        GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/0, // src1
        GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(2), /*SubOperand*/1, // src2_mods
        GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(2), /*SubOperand*/0, // src2
        GIR_AddImm8, /*InsnID*/0, /*Imm*/0,
        GIR_AddImm8, /*InsnID*/0, /*Imm*/0,
        GIR_ConstrainSelectedInstOperands, /*InsnID*/0,
        GIR_EraseFromParent, /*InsnID*/0,
        // GIR_Coverage, 10294,
        GIR_Done,
      // Label 4825: @335217
      GIM_Try, /*On fail goto*//*Label 4826*/ GIMT_Encode4(335357), // Rule ID 10295 //
        GIM_CheckRegBankForClass, /*MI*/0, /*Op*/0, /*RC*/GIMT_Encode2(AMDGPU::VGPR_32RegClassID),
        GIM_RecordInsn, /*DefineMI*/1, /*MI*/0, /*OpIdx*/1, // MIs[1]
        GIM_CheckOpcode, /*MI*/1, GIMT_Encode2(TargetOpcode::G_FMAXNUM),
        GIM_CheckType, /*MI*/1, /*Op*/1, /*Type*/GILLT_s32,
        GIM_CheckType, /*MI*/1, /*Op*/2, /*Type*/GILLT_s32,
        GIM_RecordInsn, /*DefineMI*/2, /*MI*/1, /*OpIdx*/1, // MIs[2]
        GIM_CheckOpcode, /*MI*/2, GIMT_Encode2(TargetOpcode::G_FMINNUM),
        GIM_CheckType, /*MI*/2, /*Op*/1, /*Type*/GILLT_s32,
        GIM_CheckType, /*MI*/2, /*Op*/2, /*Type*/GILLT_s32,
        GIM_RecordInsn, /*DefineMI*/3, /*MI*/0, /*OpIdx*/2, // MIs[3]
        GIM_CheckOpcode, /*MI*/3, GIMT_Encode2(TargetOpcode::G_FMAXNUM_IEEE),
        // MIs[3] VOP3Mods:src1:src1_mods
        GIM_CheckIsSameOperand, /*MI*/3, /*OpIdx*/1, /*OtherMI*/2, /*OtherOpIdx*/1,
        // MIs[3] VOP3Mods:src0:src0_mods
        GIM_CheckIsSameOperand, /*MI*/3, /*OpIdx*/2, /*OtherMI*/2, /*OtherOpIdx*/2,
        GIM_CheckCxxInsnPredicate, /*MI*/0, /*FnId*/GIMT_Encode2(GICXXPred_MI_Predicate_fminnum_like_nnan),
        GIM_CheckIsSafeToFold, /*InsnID*/1,
        GIM_CheckIsSafeToFold, /*InsnID*/2,
        GIM_CheckIsSafeToFold, /*InsnID*/3,
        GIM_CheckComplexPattern, /*MI*/1, /*Op*/2, /*Renderer*/GIMT_Encode2(2), GIMT_Encode2(GICP_gi_vop3mods),
        GIM_CheckComplexPattern, /*MI*/2, /*Op*/1, /*Renderer*/GIMT_Encode2(0), GIMT_Encode2(GICP_gi_vop3mods),
        GIM_CheckComplexPattern, /*MI*/2, /*Op*/2, /*Renderer*/GIMT_Encode2(1), GIMT_Encode2(GICP_gi_vop3mods),
        // (fminnum_ieee:{ *:[f32] } (fmaxnum:{ *:[f32] } (fminnum:{ *:[f32] } (VOP3Mods:{ *:[f32] } f32:{ *:[f32] }:$src1, i32:{ *:[i32] }:$src1_mods), (VOP3Mods:{ *:[f32] } f32:{ *:[f32] }:$src0, i32:{ *:[i32] }:$src0_mods)), (VOP3Mods:{ *:[f32] } f32:{ *:[f32] }:$src2, i32:{ *:[i32] }:$src2_mods)), (fmaxnum_ieee:{ *:[f32] } (VOP3Mods:{ *:[f32] } f32:{ *:[f32] }:$src1, i32:{ *:[i32] }:$src1_mods), (VOP3Mods:{ *:[f32] } f32:{ *:[f32] }:$src0, i32:{ *:[i32] }:$src0_mods)))<<P:Predicate_fminnum_like_nnan>>  =>  (V_MED3_F32_e64:{ *:[f32] } ?:{ *:[i32] }:$src0_mods, ?:{ *:[f32] }:$src0, ?:{ *:[i32] }:$src1_mods, ?:{ *:[f32] }:$src1, ?:{ *:[i32] }:$src2_mods, ?:{ *:[f32] }:$src2, 0:{ *:[i1] }, 0:{ *:[i32] })
        GIR_BuildMI, /*InsnID*/0, /*Opcode*/GIMT_Encode2(AMDGPU::V_MED3_F32_e64),
        GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/0, // DstI[vdst]
        GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(1), /*SubOperand*/1, // src0_mods
        GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(1), /*SubOperand*/0, // src0
        GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/1, // src1_mods
        GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/0, // src1
        GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(2), /*SubOperand*/1, // src2_mods
        GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(2), /*SubOperand*/0, // src2
        GIR_AddImm8, /*InsnID*/0, /*Imm*/0,
        GIR_AddImm8, /*InsnID*/0, /*Imm*/0,
        GIR_ConstrainSelectedInstOperands, /*InsnID*/0,
        GIR_EraseFromParent, /*InsnID*/0,
        // GIR_Coverage, 10295,
        GIR_Done,
      // Label 4826: @335357
      GIM_Try, /*On fail goto*//*Label 4827*/ GIMT_Encode4(335497), // Rule ID 10337 //
        GIM_CheckRegBankForClass, /*MI*/0, /*Op*/0, /*RC*/GIMT_Encode2(AMDGPU::VGPR_32RegClassID),
        GIM_RecordInsn, /*DefineMI*/1, /*MI*/0, /*OpIdx*/1, // MIs[1]
        GIM_CheckOpcode, /*MI*/1, GIMT_Encode2(TargetOpcode::G_FMAXNUM),
        GIM_CheckType, /*MI*/1, /*Op*/1, /*Type*/GILLT_s32,
        GIM_CheckType, /*MI*/1, /*Op*/2, /*Type*/GILLT_s32,
        GIM_RecordInsn, /*DefineMI*/2, /*MI*/1, /*OpIdx*/1, // MIs[2]
        GIM_CheckOpcode, /*MI*/2, GIMT_Encode2(TargetOpcode::G_FMINNUM_IEEE),
        GIM_CheckType, /*MI*/2, /*Op*/1, /*Type*/GILLT_s32,
        GIM_CheckType, /*MI*/2, /*Op*/2, /*Type*/GILLT_s32,
        GIM_RecordInsn, /*DefineMI*/3, /*MI*/0, /*OpIdx*/2, // MIs[3]
        GIM_CheckOpcode, /*MI*/3, GIMT_Encode2(TargetOpcode::G_FMAXNUM),
        // MIs[3] VOP3Mods:src0:src0_mods
        GIM_CheckIsSameOperand, /*MI*/3, /*OpIdx*/1, /*OtherMI*/2, /*OtherOpIdx*/1,
        // MIs[3] VOP3Mods:src1:src1_mods
        GIM_CheckIsSameOperand, /*MI*/3, /*OpIdx*/2, /*OtherMI*/2, /*OtherOpIdx*/2,
        GIM_CheckCxxInsnPredicate, /*MI*/0, /*FnId*/GIMT_Encode2(GICXXPred_MI_Predicate_fminnum_like_nnan),
        GIM_CheckIsSafeToFold, /*InsnID*/1,
        GIM_CheckIsSafeToFold, /*InsnID*/2,
        GIM_CheckIsSafeToFold, /*InsnID*/3,
        GIM_CheckComplexPattern, /*MI*/1, /*Op*/2, /*Renderer*/GIMT_Encode2(2), GIMT_Encode2(GICP_gi_vop3mods),
        GIM_CheckComplexPattern, /*MI*/2, /*Op*/1, /*Renderer*/GIMT_Encode2(0), GIMT_Encode2(GICP_gi_vop3mods),
        GIM_CheckComplexPattern, /*MI*/2, /*Op*/2, /*Renderer*/GIMT_Encode2(1), GIMT_Encode2(GICP_gi_vop3mods),
        // (fminnum_ieee:{ *:[f32] } (fmaxnum:{ *:[f32] } (fminnum_ieee:{ *:[f32] } (VOP3Mods:{ *:[f32] } f32:{ *:[f32] }:$src0, i32:{ *:[i32] }:$src0_mods), (VOP3Mods:{ *:[f32] } f32:{ *:[f32] }:$src1, i32:{ *:[i32] }:$src1_mods)), (VOP3Mods:{ *:[f32] } f32:{ *:[f32] }:$src2, i32:{ *:[i32] }:$src2_mods)), (fmaxnum:{ *:[f32] } (VOP3Mods:{ *:[f32] } f32:{ *:[f32] }:$src0, i32:{ *:[i32] }:$src0_mods), (VOP3Mods:{ *:[f32] } f32:{ *:[f32] }:$src1, i32:{ *:[i32] }:$src1_mods)))<<P:Predicate_fminnum_like_nnan>>  =>  (V_MED3_F32_e64:{ *:[f32] } ?:{ *:[i32] }:$src0_mods, ?:{ *:[f32] }:$src0, ?:{ *:[i32] }:$src1_mods, ?:{ *:[f32] }:$src1, ?:{ *:[i32] }:$src2_mods, ?:{ *:[f32] }:$src2, 0:{ *:[i1] }, 0:{ *:[i32] })
        GIR_BuildMI, /*InsnID*/0, /*Opcode*/GIMT_Encode2(AMDGPU::V_MED3_F32_e64),
        GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/0, // DstI[vdst]
        GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/1, // src0_mods
        GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/0, // src0
        GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(1), /*SubOperand*/1, // src1_mods
        GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(1), /*SubOperand*/0, // src1
        GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(2), /*SubOperand*/1, // src2_mods
        GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(2), /*SubOperand*/0, // src2
        GIR_AddImm8, /*InsnID*/0, /*Imm*/0,
        GIR_AddImm8, /*InsnID*/0, /*Imm*/0,
        GIR_ConstrainSelectedInstOperands, /*InsnID*/0,
        GIR_EraseFromParent, /*InsnID*/0,
        // GIR_Coverage, 10337,
        GIR_Done,
      // Label 4827: @335497
      GIM_Try, /*On fail goto*//*Label 4828*/ GIMT_Encode4(335637), // Rule ID 10338 //
        GIM_CheckRegBankForClass, /*MI*/0, /*Op*/0, /*RC*/GIMT_Encode2(AMDGPU::VGPR_32RegClassID),
        GIM_RecordInsn, /*DefineMI*/1, /*MI*/0, /*OpIdx*/1, // MIs[1]
        GIM_CheckOpcode, /*MI*/1, GIMT_Encode2(TargetOpcode::G_FMAXNUM),
        GIM_CheckType, /*MI*/1, /*Op*/1, /*Type*/GILLT_s32,
        GIM_CheckType, /*MI*/1, /*Op*/2, /*Type*/GILLT_s32,
        GIM_RecordInsn, /*DefineMI*/2, /*MI*/1, /*OpIdx*/1, // MIs[2]
        GIM_CheckOpcode, /*MI*/2, GIMT_Encode2(TargetOpcode::G_FMINNUM_IEEE),
        GIM_CheckType, /*MI*/2, /*Op*/1, /*Type*/GILLT_s32,
        GIM_CheckType, /*MI*/2, /*Op*/2, /*Type*/GILLT_s32,
        GIM_RecordInsn, /*DefineMI*/3, /*MI*/0, /*OpIdx*/2, // MIs[3]
        GIM_CheckOpcode, /*MI*/3, GIMT_Encode2(TargetOpcode::G_FMAXNUM),
        // MIs[3] VOP3Mods:src1:src1_mods
        GIM_CheckIsSameOperand, /*MI*/3, /*OpIdx*/1, /*OtherMI*/2, /*OtherOpIdx*/2,
        // MIs[3] VOP3Mods:src0:src0_mods
        GIM_CheckIsSameOperand, /*MI*/3, /*OpIdx*/2, /*OtherMI*/2, /*OtherOpIdx*/1,
        GIM_CheckCxxInsnPredicate, /*MI*/0, /*FnId*/GIMT_Encode2(GICXXPred_MI_Predicate_fminnum_like_nnan),
        GIM_CheckIsSafeToFold, /*InsnID*/1,
        GIM_CheckIsSafeToFold, /*InsnID*/2,
        GIM_CheckIsSafeToFold, /*InsnID*/3,
        GIM_CheckComplexPattern, /*MI*/1, /*Op*/2, /*Renderer*/GIMT_Encode2(2), GIMT_Encode2(GICP_gi_vop3mods),
        GIM_CheckComplexPattern, /*MI*/2, /*Op*/1, /*Renderer*/GIMT_Encode2(0), GIMT_Encode2(GICP_gi_vop3mods),
        GIM_CheckComplexPattern, /*MI*/2, /*Op*/2, /*Renderer*/GIMT_Encode2(1), GIMT_Encode2(GICP_gi_vop3mods),
        // (fminnum_ieee:{ *:[f32] } (fmaxnum:{ *:[f32] } (fminnum_ieee:{ *:[f32] } (VOP3Mods:{ *:[f32] } f32:{ *:[f32] }:$src0, i32:{ *:[i32] }:$src0_mods), (VOP3Mods:{ *:[f32] } f32:{ *:[f32] }:$src1, i32:{ *:[i32] }:$src1_mods)), (VOP3Mods:{ *:[f32] } f32:{ *:[f32] }:$src2, i32:{ *:[i32] }:$src2_mods)), (fmaxnum:{ *:[f32] } (VOP3Mods:{ *:[f32] } f32:{ *:[f32] }:$src1, i32:{ *:[i32] }:$src1_mods), (VOP3Mods:{ *:[f32] } f32:{ *:[f32] }:$src0, i32:{ *:[i32] }:$src0_mods)))<<P:Predicate_fminnum_like_nnan>>  =>  (V_MED3_F32_e64:{ *:[f32] } ?:{ *:[i32] }:$src0_mods, ?:{ *:[f32] }:$src0, ?:{ *:[i32] }:$src1_mods, ?:{ *:[f32] }:$src1, ?:{ *:[i32] }:$src2_mods, ?:{ *:[f32] }:$src2, 0:{ *:[i1] }, 0:{ *:[i32] })
        GIR_BuildMI, /*InsnID*/0, /*Opcode*/GIMT_Encode2(AMDGPU::V_MED3_F32_e64),
        GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/0, // DstI[vdst]
        GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/1, // src0_mods
        GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/0, // src0
        GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(1), /*SubOperand*/1, // src1_mods
        GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(1), /*SubOperand*/0, // src1
        GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(2), /*SubOperand*/1, // src2_mods
        GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(2), /*SubOperand*/0, // src2
        GIR_AddImm8, /*InsnID*/0, /*Imm*/0,
        GIR_AddImm8, /*InsnID*/0, /*Imm*/0,
        GIR_ConstrainSelectedInstOperands, /*InsnID*/0,
        GIR_EraseFromParent, /*InsnID*/0,
        // GIR_Coverage, 10338,
        GIR_Done,
      // Label 4828: @335637
      GIM_Try, /*On fail goto*//*Label 4829*/ GIMT_Encode4(335777), // Rule ID 10339 //
        GIM_CheckRegBankForClass, /*MI*/0, /*Op*/0, /*RC*/GIMT_Encode2(AMDGPU::VGPR_32RegClassID),
        GIM_RecordInsn, /*DefineMI*/1, /*MI*/0, /*OpIdx*/1, // MIs[1]
        GIM_CheckOpcode, /*MI*/1, GIMT_Encode2(TargetOpcode::G_FMAXNUM),
        GIM_CheckType, /*MI*/1, /*Op*/1, /*Type*/GILLT_s32,
        GIM_CheckType, /*MI*/1, /*Op*/2, /*Type*/GILLT_s32,
        GIM_RecordInsn, /*DefineMI*/2, /*MI*/1, /*OpIdx*/1, // MIs[2]
        GIM_CheckOpcode, /*MI*/2, GIMT_Encode2(TargetOpcode::G_FMINNUM_IEEE),
        GIM_CheckType, /*MI*/2, /*Op*/1, /*Type*/GILLT_s32,
        GIM_CheckType, /*MI*/2, /*Op*/2, /*Type*/GILLT_s32,
        GIM_RecordInsn, /*DefineMI*/3, /*MI*/0, /*OpIdx*/2, // MIs[3]
        GIM_CheckOpcode, /*MI*/3, GIMT_Encode2(TargetOpcode::G_FMAXNUM),
        // MIs[3] VOP3Mods:src0:src0_mods
        GIM_CheckIsSameOperand, /*MI*/3, /*OpIdx*/1, /*OtherMI*/2, /*OtherOpIdx*/2,
        // MIs[3] VOP3Mods:src1:src1_mods
        GIM_CheckIsSameOperand, /*MI*/3, /*OpIdx*/2, /*OtherMI*/2, /*OtherOpIdx*/1,
        GIM_CheckCxxInsnPredicate, /*MI*/0, /*FnId*/GIMT_Encode2(GICXXPred_MI_Predicate_fminnum_like_nnan),
        GIM_CheckIsSafeToFold, /*InsnID*/1,
        GIM_CheckIsSafeToFold, /*InsnID*/2,
        GIM_CheckIsSafeToFold, /*InsnID*/3,
        GIM_CheckComplexPattern, /*MI*/1, /*Op*/2, /*Renderer*/GIMT_Encode2(2), GIMT_Encode2(GICP_gi_vop3mods),
        GIM_CheckComplexPattern, /*MI*/2, /*Op*/1, /*Renderer*/GIMT_Encode2(0), GIMT_Encode2(GICP_gi_vop3mods),
        GIM_CheckComplexPattern, /*MI*/2, /*Op*/2, /*Renderer*/GIMT_Encode2(1), GIMT_Encode2(GICP_gi_vop3mods),
        // (fminnum_ieee:{ *:[f32] } (fmaxnum:{ *:[f32] } (fminnum_ieee:{ *:[f32] } (VOP3Mods:{ *:[f32] } f32:{ *:[f32] }:$src1, i32:{ *:[i32] }:$src1_mods), (VOP3Mods:{ *:[f32] } f32:{ *:[f32] }:$src0, i32:{ *:[i32] }:$src0_mods)), (VOP3Mods:{ *:[f32] } f32:{ *:[f32] }:$src2, i32:{ *:[i32] }:$src2_mods)), (fmaxnum:{ *:[f32] } (VOP3Mods:{ *:[f32] } f32:{ *:[f32] }:$src0, i32:{ *:[i32] }:$src0_mods), (VOP3Mods:{ *:[f32] } f32:{ *:[f32] }:$src1, i32:{ *:[i32] }:$src1_mods)))<<P:Predicate_fminnum_like_nnan>>  =>  (V_MED3_F32_e64:{ *:[f32] } ?:{ *:[i32] }:$src0_mods, ?:{ *:[f32] }:$src0, ?:{ *:[i32] }:$src1_mods, ?:{ *:[f32] }:$src1, ?:{ *:[i32] }:$src2_mods, ?:{ *:[f32] }:$src2, 0:{ *:[i1] }, 0:{ *:[i32] })
        GIR_BuildMI, /*InsnID*/0, /*Opcode*/GIMT_Encode2(AMDGPU::V_MED3_F32_e64),
        GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/0, // DstI[vdst]
        GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(1), /*SubOperand*/1, // src0_mods
        GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(1), /*SubOperand*/0, // src0
        GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/1, // src1_mods
        GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/0, // src1
        GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(2), /*SubOperand*/1, // src2_mods
        GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(2), /*SubOperand*/0, // src2
        GIR_AddImm8, /*InsnID*/0, /*Imm*/0,
        GIR_AddImm8, /*InsnID*/0, /*Imm*/0,
        GIR_ConstrainSelectedInstOperands, /*InsnID*/0,
        GIR_EraseFromParent, /*InsnID*/0,
        // GIR_Coverage, 10339,
        GIR_Done,
      // Label 4829: @335777
      GIM_Try, /*On fail goto*//*Label 4830*/ GIMT_Encode4(335917), // Rule ID 10340 //
        GIM_CheckRegBankForClass, /*MI*/0, /*Op*/0, /*RC*/GIMT_Encode2(AMDGPU::VGPR_32RegClassID),
        GIM_RecordInsn, /*DefineMI*/1, /*MI*/0, /*OpIdx*/1, // MIs[1]
        GIM_CheckOpcode, /*MI*/1, GIMT_Encode2(TargetOpcode::G_FMAXNUM),
        GIM_CheckType, /*MI*/1, /*Op*/1, /*Type*/GILLT_s32,
        GIM_CheckType, /*MI*/1, /*Op*/2, /*Type*/GILLT_s32,
        GIM_RecordInsn, /*DefineMI*/2, /*MI*/1, /*OpIdx*/1, // MIs[2]
        GIM_CheckOpcode, /*MI*/2, GIMT_Encode2(TargetOpcode::G_FMINNUM_IEEE),
        GIM_CheckType, /*MI*/2, /*Op*/1, /*Type*/GILLT_s32,
        GIM_CheckType, /*MI*/2, /*Op*/2, /*Type*/GILLT_s32,
        GIM_RecordInsn, /*DefineMI*/3, /*MI*/0, /*OpIdx*/2, // MIs[3]
        GIM_CheckOpcode, /*MI*/3, GIMT_Encode2(TargetOpcode::G_FMAXNUM),
        // MIs[3] VOP3Mods:src1:src1_mods
        GIM_CheckIsSameOperand, /*MI*/3, /*OpIdx*/1, /*OtherMI*/2, /*OtherOpIdx*/1,
        // MIs[3] VOP3Mods:src0:src0_mods
        GIM_CheckIsSameOperand, /*MI*/3, /*OpIdx*/2, /*OtherMI*/2, /*OtherOpIdx*/2,
        GIM_CheckCxxInsnPredicate, /*MI*/0, /*FnId*/GIMT_Encode2(GICXXPred_MI_Predicate_fminnum_like_nnan),
        GIM_CheckIsSafeToFold, /*InsnID*/1,
        GIM_CheckIsSafeToFold, /*InsnID*/2,
        GIM_CheckIsSafeToFold, /*InsnID*/3,
        GIM_CheckComplexPattern, /*MI*/1, /*Op*/2, /*Renderer*/GIMT_Encode2(2), GIMT_Encode2(GICP_gi_vop3mods),
        GIM_CheckComplexPattern, /*MI*/2, /*Op*/1, /*Renderer*/GIMT_Encode2(0), GIMT_Encode2(GICP_gi_vop3mods),
        GIM_CheckComplexPattern, /*MI*/2, /*Op*/2, /*Renderer*/GIMT_Encode2(1), GIMT_Encode2(GICP_gi_vop3mods),
        // (fminnum_ieee:{ *:[f32] } (fmaxnum:{ *:[f32] } (fminnum_ieee:{ *:[f32] } (VOP3Mods:{ *:[f32] } f32:{ *:[f32] }:$src1, i32:{ *:[i32] }:$src1_mods), (VOP3Mods:{ *:[f32] } f32:{ *:[f32] }:$src0, i32:{ *:[i32] }:$src0_mods)), (VOP3Mods:{ *:[f32] } f32:{ *:[f32] }:$src2, i32:{ *:[i32] }:$src2_mods)), (fmaxnum:{ *:[f32] } (VOP3Mods:{ *:[f32] } f32:{ *:[f32] }:$src1, i32:{ *:[i32] }:$src1_mods), (VOP3Mods:{ *:[f32] } f32:{ *:[f32] }:$src0, i32:{ *:[i32] }:$src0_mods)))<<P:Predicate_fminnum_like_nnan>>  =>  (V_MED3_F32_e64:{ *:[f32] } ?:{ *:[i32] }:$src0_mods, ?:{ *:[f32] }:$src0, ?:{ *:[i32] }:$src1_mods, ?:{ *:[f32] }:$src1, ?:{ *:[i32] }:$src2_mods, ?:{ *:[f32] }:$src2, 0:{ *:[i1] }, 0:{ *:[i32] })
        GIR_BuildMI, /*InsnID*/0, /*Opcode*/GIMT_Encode2(AMDGPU::V_MED3_F32_e64),
        GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/0, // DstI[vdst]
        GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(1), /*SubOperand*/1, // src0_mods
        GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(1), /*SubOperand*/0, // src0
        GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/1, // src1_mods
        GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/0, // src1
        GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(2), /*SubOperand*/1, // src2_mods
        GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(2), /*SubOperand*/0, // src2
        GIR_AddImm8, /*InsnID*/0, /*Imm*/0,
        GIR_AddImm8, /*InsnID*/0, /*Imm*/0,
        GIR_ConstrainSelectedInstOperands, /*InsnID*/0,
        GIR_EraseFromParent, /*InsnID*/0,
        // GIR_Coverage, 10340,
        GIR_Done,
      // Label 4830: @335917
      GIM_Try, /*On fail goto*//*Label 4831*/ GIMT_Encode4(336057), // Rule ID 10277 //
        GIM_CheckRegBankForClass, /*MI*/0, /*Op*/0, /*RC*/GIMT_Encode2(AMDGPU::VGPR_32RegClassID),
        GIM_RecordInsn, /*DefineMI*/1, /*MI*/0, /*OpIdx*/1, // MIs[1]
        GIM_CheckOpcode, /*MI*/1, GIMT_Encode2(TargetOpcode::G_FMAXNUM),
        GIM_CheckType, /*MI*/1, /*Op*/1, /*Type*/GILLT_s32,
        GIM_CheckType, /*MI*/1, /*Op*/2, /*Type*/GILLT_s32,
        GIM_RecordInsn, /*DefineMI*/2, /*MI*/1, /*OpIdx*/1, // MIs[2]
        GIM_CheckOpcode, /*MI*/2, GIMT_Encode2(TargetOpcode::G_FMINNUM_IEEE),
        GIM_CheckType, /*MI*/2, /*Op*/1, /*Type*/GILLT_s32,
        GIM_CheckType, /*MI*/2, /*Op*/2, /*Type*/GILLT_s32,
        GIM_RecordInsn, /*DefineMI*/3, /*MI*/0, /*OpIdx*/2, // MIs[3]
        GIM_CheckOpcode, /*MI*/3, GIMT_Encode2(TargetOpcode::G_FMAXNUM_IEEE),
        // MIs[3] VOP3Mods:src0:src0_mods
        GIM_CheckIsSameOperand, /*MI*/3, /*OpIdx*/1, /*OtherMI*/2, /*OtherOpIdx*/1,
        // MIs[3] VOP3Mods:src1:src1_mods
        GIM_CheckIsSameOperand, /*MI*/3, /*OpIdx*/2, /*OtherMI*/2, /*OtherOpIdx*/2,
        GIM_CheckCxxInsnPredicate, /*MI*/0, /*FnId*/GIMT_Encode2(GICXXPred_MI_Predicate_fminnum_like_nnan),
        GIM_CheckIsSafeToFold, /*InsnID*/1,
        GIM_CheckIsSafeToFold, /*InsnID*/2,
        GIM_CheckIsSafeToFold, /*InsnID*/3,
        GIM_CheckComplexPattern, /*MI*/1, /*Op*/2, /*Renderer*/GIMT_Encode2(2), GIMT_Encode2(GICP_gi_vop3mods),
        GIM_CheckComplexPattern, /*MI*/2, /*Op*/1, /*Renderer*/GIMT_Encode2(0), GIMT_Encode2(GICP_gi_vop3mods),
        GIM_CheckComplexPattern, /*MI*/2, /*Op*/2, /*Renderer*/GIMT_Encode2(1), GIMT_Encode2(GICP_gi_vop3mods),
        // (fminnum_ieee:{ *:[f32] } (fmaxnum:{ *:[f32] } (fminnum_ieee:{ *:[f32] } (VOP3Mods:{ *:[f32] } f32:{ *:[f32] }:$src0, i32:{ *:[i32] }:$src0_mods), (VOP3Mods:{ *:[f32] } f32:{ *:[f32] }:$src1, i32:{ *:[i32] }:$src1_mods)), (VOP3Mods:{ *:[f32] } f32:{ *:[f32] }:$src2, i32:{ *:[i32] }:$src2_mods)), (fmaxnum_ieee:{ *:[f32] } (VOP3Mods:{ *:[f32] } f32:{ *:[f32] }:$src0, i32:{ *:[i32] }:$src0_mods), (VOP3Mods:{ *:[f32] } f32:{ *:[f32] }:$src1, i32:{ *:[i32] }:$src1_mods)))<<P:Predicate_fminnum_like_nnan>>  =>  (V_MED3_F32_e64:{ *:[f32] } ?:{ *:[i32] }:$src0_mods, ?:{ *:[f32] }:$src0, ?:{ *:[i32] }:$src1_mods, ?:{ *:[f32] }:$src1, ?:{ *:[i32] }:$src2_mods, ?:{ *:[f32] }:$src2, 0:{ *:[i1] }, 0:{ *:[i32] })
        GIR_BuildMI, /*InsnID*/0, /*Opcode*/GIMT_Encode2(AMDGPU::V_MED3_F32_e64),
        GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/0, // DstI[vdst]
        GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/1, // src0_mods
        GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/0, // src0
        GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(1), /*SubOperand*/1, // src1_mods
        GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(1), /*SubOperand*/0, // src1
        GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(2), /*SubOperand*/1, // src2_mods
        GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(2), /*SubOperand*/0, // src2
        GIR_AddImm8, /*InsnID*/0, /*Imm*/0,
        GIR_AddImm8, /*InsnID*/0, /*Imm*/0,
        GIR_ConstrainSelectedInstOperands, /*InsnID*/0,
        GIR_EraseFromParent, /*InsnID*/0,
        // GIR_Coverage, 10277,
        GIR_Done,
      // Label 4831: @336057
      GIM_Try, /*On fail goto*//*Label 4832*/ GIMT_Encode4(336197), // Rule ID 10278 //
        GIM_CheckRegBankForClass, /*MI*/0, /*Op*/0, /*RC*/GIMT_Encode2(AMDGPU::VGPR_32RegClassID),
        GIM_RecordInsn, /*DefineMI*/1, /*MI*/0, /*OpIdx*/1, // MIs[1]
        GIM_CheckOpcode, /*MI*/1, GIMT_Encode2(TargetOpcode::G_FMAXNUM),
        GIM_CheckType, /*MI*/1, /*Op*/1, /*Type*/GILLT_s32,
        GIM_CheckType, /*MI*/1, /*Op*/2, /*Type*/GILLT_s32,
        GIM_RecordInsn, /*DefineMI*/2, /*MI*/1, /*OpIdx*/1, // MIs[2]
        GIM_CheckOpcode, /*MI*/2, GIMT_Encode2(TargetOpcode::G_FMINNUM_IEEE),
        GIM_CheckType, /*MI*/2, /*Op*/1, /*Type*/GILLT_s32,
        GIM_CheckType, /*MI*/2, /*Op*/2, /*Type*/GILLT_s32,
        GIM_RecordInsn, /*DefineMI*/3, /*MI*/0, /*OpIdx*/2, // MIs[3]
        GIM_CheckOpcode, /*MI*/3, GIMT_Encode2(TargetOpcode::G_FMAXNUM_IEEE),
        // MIs[3] VOP3Mods:src1:src1_mods
        GIM_CheckIsSameOperand, /*MI*/3, /*OpIdx*/1, /*OtherMI*/2, /*OtherOpIdx*/2,
        // MIs[3] VOP3Mods:src0:src0_mods
        GIM_CheckIsSameOperand, /*MI*/3, /*OpIdx*/2, /*OtherMI*/2, /*OtherOpIdx*/1,
        GIM_CheckCxxInsnPredicate, /*MI*/0, /*FnId*/GIMT_Encode2(GICXXPred_MI_Predicate_fminnum_like_nnan),
        GIM_CheckIsSafeToFold, /*InsnID*/1,
        GIM_CheckIsSafeToFold, /*InsnID*/2,
        GIM_CheckIsSafeToFold, /*InsnID*/3,
        GIM_CheckComplexPattern, /*MI*/1, /*Op*/2, /*Renderer*/GIMT_Encode2(2), GIMT_Encode2(GICP_gi_vop3mods),
        GIM_CheckComplexPattern, /*MI*/2, /*Op*/1, /*Renderer*/GIMT_Encode2(0), GIMT_Encode2(GICP_gi_vop3mods),
        GIM_CheckComplexPattern, /*MI*/2, /*Op*/2, /*Renderer*/GIMT_Encode2(1), GIMT_Encode2(GICP_gi_vop3mods),
        // (fminnum_ieee:{ *:[f32] } (fmaxnum:{ *:[f32] } (fminnum_ieee:{ *:[f32] } (VOP3Mods:{ *:[f32] } f32:{ *:[f32] }:$src0, i32:{ *:[i32] }:$src0_mods), (VOP3Mods:{ *:[f32] } f32:{ *:[f32] }:$src1, i32:{ *:[i32] }:$src1_mods)), (VOP3Mods:{ *:[f32] } f32:{ *:[f32] }:$src2, i32:{ *:[i32] }:$src2_mods)), (fmaxnum_ieee:{ *:[f32] } (VOP3Mods:{ *:[f32] } f32:{ *:[f32] }:$src1, i32:{ *:[i32] }:$src1_mods), (VOP3Mods:{ *:[f32] } f32:{ *:[f32] }:$src0, i32:{ *:[i32] }:$src0_mods)))<<P:Predicate_fminnum_like_nnan>>  =>  (V_MED3_F32_e64:{ *:[f32] } ?:{ *:[i32] }:$src0_mods, ?:{ *:[f32] }:$src0, ?:{ *:[i32] }:$src1_mods, ?:{ *:[f32] }:$src1, ?:{ *:[i32] }:$src2_mods, ?:{ *:[f32] }:$src2, 0:{ *:[i1] }, 0:{ *:[i32] })
        GIR_BuildMI, /*InsnID*/0, /*Opcode*/GIMT_Encode2(AMDGPU::V_MED3_F32_e64),
        GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/0, // DstI[vdst]
        GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/1, // src0_mods
        GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/0, // src0
        GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(1), /*SubOperand*/1, // src1_mods
        GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(1), /*SubOperand*/0, // src1
        GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(2), /*SubOperand*/1, // src2_mods
        GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(2), /*SubOperand*/0, // src2
        GIR_AddImm8, /*InsnID*/0, /*Imm*/0,
        GIR_AddImm8, /*InsnID*/0, /*Imm*/0,
        GIR_ConstrainSelectedInstOperands, /*InsnID*/0,
        GIR_EraseFromParent, /*InsnID*/0,
        // GIR_Coverage, 10278,
        GIR_Done,
      // Label 4832: @336197
      GIM_Try, /*On fail goto*//*Label 4833*/ GIMT_Encode4(336337), // Rule ID 10279 //
        GIM_CheckRegBankForClass, /*MI*/0, /*Op*/0, /*RC*/GIMT_Encode2(AMDGPU::VGPR_32RegClassID),
        GIM_RecordInsn, /*DefineMI*/1, /*MI*/0, /*OpIdx*/1, // MIs[1]
        GIM_CheckOpcode, /*MI*/1, GIMT_Encode2(TargetOpcode::G_FMAXNUM),
        GIM_CheckType, /*MI*/1, /*Op*/1, /*Type*/GILLT_s32,
        GIM_CheckType, /*MI*/1, /*Op*/2, /*Type*/GILLT_s32,
        GIM_RecordInsn, /*DefineMI*/2, /*MI*/1, /*OpIdx*/1, // MIs[2]
        GIM_CheckOpcode, /*MI*/2, GIMT_Encode2(TargetOpcode::G_FMINNUM_IEEE),
        GIM_CheckType, /*MI*/2, /*Op*/1, /*Type*/GILLT_s32,
        GIM_CheckType, /*MI*/2, /*Op*/2, /*Type*/GILLT_s32,
        GIM_RecordInsn, /*DefineMI*/3, /*MI*/0, /*OpIdx*/2, // MIs[3]
        GIM_CheckOpcode, /*MI*/3, GIMT_Encode2(TargetOpcode::G_FMAXNUM_IEEE),
        // MIs[3] VOP3Mods:src0:src0_mods
        GIM_CheckIsSameOperand, /*MI*/3, /*OpIdx*/1, /*OtherMI*/2, /*OtherOpIdx*/2,
        // MIs[3] VOP3Mods:src1:src1_mods
        GIM_CheckIsSameOperand, /*MI*/3, /*OpIdx*/2, /*OtherMI*/2, /*OtherOpIdx*/1,
        GIM_CheckCxxInsnPredicate, /*MI*/0, /*FnId*/GIMT_Encode2(GICXXPred_MI_Predicate_fminnum_like_nnan),
        GIM_CheckIsSafeToFold, /*InsnID*/1,
        GIM_CheckIsSafeToFold, /*InsnID*/2,
        GIM_CheckIsSafeToFold, /*InsnID*/3,
        GIM_CheckComplexPattern, /*MI*/1, /*Op*/2, /*Renderer*/GIMT_Encode2(2), GIMT_Encode2(GICP_gi_vop3mods),
        GIM_CheckComplexPattern, /*MI*/2, /*Op*/1, /*Renderer*/GIMT_Encode2(0), GIMT_Encode2(GICP_gi_vop3mods),
        GIM_CheckComplexPattern, /*MI*/2, /*Op*/2, /*Renderer*/GIMT_Encode2(1), GIMT_Encode2(GICP_gi_vop3mods),
        // (fminnum_ieee:{ *:[f32] } (fmaxnum:{ *:[f32] } (fminnum_ieee:{ *:[f32] } (VOP3Mods:{ *:[f32] } f32:{ *:[f32] }:$src1, i32:{ *:[i32] }:$src1_mods), (VOP3Mods:{ *:[f32] } f32:{ *:[f32] }:$src0, i32:{ *:[i32] }:$src0_mods)), (VOP3Mods:{ *:[f32] } f32:{ *:[f32] }:$src2, i32:{ *:[i32] }:$src2_mods)), (fmaxnum_ieee:{ *:[f32] } (VOP3Mods:{ *:[f32] } f32:{ *:[f32] }:$src0, i32:{ *:[i32] }:$src0_mods), (VOP3Mods:{ *:[f32] } f32:{ *:[f32] }:$src1, i32:{ *:[i32] }:$src1_mods)))<<P:Predicate_fminnum_like_nnan>>  =>  (V_MED3_F32_e64:{ *:[f32] } ?:{ *:[i32] }:$src0_mods, ?:{ *:[f32] }:$src0, ?:{ *:[i32] }:$src1_mods, ?:{ *:[f32] }:$src1, ?:{ *:[i32] }:$src2_mods, ?:{ *:[f32] }:$src2, 0:{ *:[i1] }, 0:{ *:[i32] })
        GIR_BuildMI, /*InsnID*/0, /*Opcode*/GIMT_Encode2(AMDGPU::V_MED3_F32_e64),
        GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/0, // DstI[vdst]
        GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(1), /*SubOperand*/1, // src0_mods
        GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(1), /*SubOperand*/0, // src0
        GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/1, // src1_mods
        GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/0, // src1
        GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(2), /*SubOperand*/1, // src2_mods
        GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(2), /*SubOperand*/0, // src2
        GIR_AddImm8, /*InsnID*/0, /*Imm*/0,
        GIR_AddImm8, /*InsnID*/0, /*Imm*/0,
        GIR_ConstrainSelectedInstOperands, /*InsnID*/0,
        GIR_EraseFromParent, /*InsnID*/0,
        // GIR_Coverage, 10279,
        GIR_Done,
      // Label 4833: @336337
      GIM_Try, /*On fail goto*//*Label 4834*/ GIMT_Encode4(336477), // Rule ID 10280 //
        GIM_CheckRegBankForClass, /*MI*/0, /*Op*/0, /*RC*/GIMT_Encode2(AMDGPU::VGPR_32RegClassID),
        GIM_RecordInsn, /*DefineMI*/1, /*MI*/0, /*OpIdx*/1, // MIs[1]
        GIM_CheckOpcode, /*MI*/1, GIMT_Encode2(TargetOpcode::G_FMAXNUM),
        GIM_CheckType, /*MI*/1, /*Op*/1, /*Type*/GILLT_s32,
        GIM_CheckType, /*MI*/1, /*Op*/2, /*Type*/GILLT_s32,
        GIM_RecordInsn, /*DefineMI*/2, /*MI*/1, /*OpIdx*/1, // MIs[2]
        GIM_CheckOpcode, /*MI*/2, GIMT_Encode2(TargetOpcode::G_FMINNUM_IEEE),
        GIM_CheckType, /*MI*/2, /*Op*/1, /*Type*/GILLT_s32,
        GIM_CheckType, /*MI*/2, /*Op*/2, /*Type*/GILLT_s32,
        GIM_RecordInsn, /*DefineMI*/3, /*MI*/0, /*OpIdx*/2, // MIs[3]
        GIM_CheckOpcode, /*MI*/3, GIMT_Encode2(TargetOpcode::G_FMAXNUM_IEEE),
        // MIs[3] VOP3Mods:src1:src1_mods
        GIM_CheckIsSameOperand, /*MI*/3, /*OpIdx*/1, /*OtherMI*/2, /*OtherOpIdx*/1,
        // MIs[3] VOP3Mods:src0:src0_mods
        GIM_CheckIsSameOperand, /*MI*/3, /*OpIdx*/2, /*OtherMI*/2, /*OtherOpIdx*/2,
        GIM_CheckCxxInsnPredicate, /*MI*/0, /*FnId*/GIMT_Encode2(GICXXPred_MI_Predicate_fminnum_like_nnan),
        GIM_CheckIsSafeToFold, /*InsnID*/1,
        GIM_CheckIsSafeToFold, /*InsnID*/2,
        GIM_CheckIsSafeToFold, /*InsnID*/3,
        GIM_CheckComplexPattern, /*MI*/1, /*Op*/2, /*Renderer*/GIMT_Encode2(2), GIMT_Encode2(GICP_gi_vop3mods),
        GIM_CheckComplexPattern, /*MI*/2, /*Op*/1, /*Renderer*/GIMT_Encode2(0), GIMT_Encode2(GICP_gi_vop3mods),
        GIM_CheckComplexPattern, /*MI*/2, /*Op*/2, /*Renderer*/GIMT_Encode2(1), GIMT_Encode2(GICP_gi_vop3mods),
        // (fminnum_ieee:{ *:[f32] } (fmaxnum:{ *:[f32] } (fminnum_ieee:{ *:[f32] } (VOP3Mods:{ *:[f32] } f32:{ *:[f32] }:$src1, i32:{ *:[i32] }:$src1_mods), (VOP3Mods:{ *:[f32] } f32:{ *:[f32] }:$src0, i32:{ *:[i32] }:$src0_mods)), (VOP3Mods:{ *:[f32] } f32:{ *:[f32] }:$src2, i32:{ *:[i32] }:$src2_mods)), (fmaxnum_ieee:{ *:[f32] } (VOP3Mods:{ *:[f32] } f32:{ *:[f32] }:$src1, i32:{ *:[i32] }:$src1_mods), (VOP3Mods:{ *:[f32] } f32:{ *:[f32] }:$src0, i32:{ *:[i32] }:$src0_mods)))<<P:Predicate_fminnum_like_nnan>>  =>  (V_MED3_F32_e64:{ *:[f32] } ?:{ *:[i32] }:$src0_mods, ?:{ *:[f32] }:$src0, ?:{ *:[i32] }:$src1_mods, ?:{ *:[f32] }:$src1, ?:{ *:[i32] }:$src2_mods, ?:{ *:[f32] }:$src2, 0:{ *:[i1] }, 0:{ *:[i32] })
        GIR_BuildMI, /*InsnID*/0, /*Opcode*/GIMT_Encode2(AMDGPU::V_MED3_F32_e64),
        GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/0, // DstI[vdst]
        GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(1), /*SubOperand*/1, // src0_mods
        GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(1), /*SubOperand*/0, // src0
        GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/1, // src1_mods
        GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/0, // src1
        GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(2), /*SubOperand*/1, // src2_mods
        GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(2), /*SubOperand*/0, // src2
        GIR_AddImm8, /*InsnID*/0, /*Imm*/0,
        GIR_AddImm8, /*InsnID*/0, /*Imm*/0,
        GIR_ConstrainSelectedInstOperands, /*InsnID*/0,
        GIR_EraseFromParent, /*InsnID*/0,
        // GIR_Coverage, 10280,
        GIR_Done,
      // Label 4834: @336477
      GIM_Try, /*On fail goto*//*Label 4835*/ GIMT_Encode4(336617), // Rule ID 10286 //
        GIM_CheckRegBankForClass, /*MI*/0, /*Op*/0, /*RC*/GIMT_Encode2(AMDGPU::VGPR_32RegClassID),
        GIM_RecordInsn, /*DefineMI*/1, /*MI*/0, /*OpIdx*/1, // MIs[1]
        GIM_CheckOpcode, /*MI*/1, GIMT_Encode2(TargetOpcode::G_FMAXNUM_IEEE),
        GIM_CheckType, /*MI*/1, /*Op*/1, /*Type*/GILLT_s32,
        GIM_CheckType, /*MI*/1, /*Op*/2, /*Type*/GILLT_s32,
        GIM_RecordInsn, /*DefineMI*/2, /*MI*/0, /*OpIdx*/2, // MIs[2]
        GIM_CheckOpcode, /*MI*/2, GIMT_Encode2(TargetOpcode::G_FMAXNUM),
        GIM_CheckType, /*MI*/2, /*Op*/1, /*Type*/GILLT_s32,
        GIM_CheckType, /*MI*/2, /*Op*/2, /*Type*/GILLT_s32,
        GIM_RecordInsn, /*DefineMI*/3, /*MI*/2, /*OpIdx*/2, // MIs[3]
        GIM_CheckOpcode, /*MI*/3, GIMT_Encode2(TargetOpcode::G_FMINNUM),
        // MIs[3] VOP3Mods:src0:src0_mods
        GIM_CheckIsSameOperand, /*MI*/3, /*OpIdx*/1, /*OtherMI*/1, /*OtherOpIdx*/1,
        // MIs[3] VOP3Mods:src1:src1_mods
        GIM_CheckIsSameOperand, /*MI*/3, /*OpIdx*/2, /*OtherMI*/1, /*OtherOpIdx*/2,
        GIM_CheckCxxInsnPredicate, /*MI*/0, /*FnId*/GIMT_Encode2(GICXXPred_MI_Predicate_fminnum_like_nnan),
        GIM_CheckIsSafeToFold, /*InsnID*/1,
        GIM_CheckIsSafeToFold, /*InsnID*/2,
        GIM_CheckIsSafeToFold, /*InsnID*/3,
        GIM_CheckComplexPattern, /*MI*/1, /*Op*/1, /*Renderer*/GIMT_Encode2(0), GIMT_Encode2(GICP_gi_vop3mods),
        GIM_CheckComplexPattern, /*MI*/1, /*Op*/2, /*Renderer*/GIMT_Encode2(1), GIMT_Encode2(GICP_gi_vop3mods),
        GIM_CheckComplexPattern, /*MI*/2, /*Op*/1, /*Renderer*/GIMT_Encode2(2), GIMT_Encode2(GICP_gi_vop3mods),
        // (fminnum_ieee:{ *:[f32] } (fmaxnum_ieee:{ *:[f32] } (VOP3Mods:{ *:[f32] } f32:{ *:[f32] }:$src0, i32:{ *:[i32] }:$src0_mods), (VOP3Mods:{ *:[f32] } f32:{ *:[f32] }:$src1, i32:{ *:[i32] }:$src1_mods)), (fmaxnum:{ *:[f32] } (VOP3Mods:{ *:[f32] } f32:{ *:[f32] }:$src2, i32:{ *:[i32] }:$src2_mods), (fminnum:{ *:[f32] } (VOP3Mods:{ *:[f32] } f32:{ *:[f32] }:$src0, i32:{ *:[i32] }:$src0_mods), (VOP3Mods:{ *:[f32] } f32:{ *:[f32] }:$src1, i32:{ *:[i32] }:$src1_mods))))<<P:Predicate_fminnum_like_nnan>>  =>  (V_MED3_F32_e64:{ *:[f32] } ?:{ *:[i32] }:$src0_mods, ?:{ *:[f32] }:$src0, ?:{ *:[i32] }:$src1_mods, ?:{ *:[f32] }:$src1, ?:{ *:[i32] }:$src2_mods, ?:{ *:[f32] }:$src2, 0:{ *:[i1] }, 0:{ *:[i32] })
        GIR_BuildMI, /*InsnID*/0, /*Opcode*/GIMT_Encode2(AMDGPU::V_MED3_F32_e64),
        GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/0, // DstI[vdst]
        GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/1, // src0_mods
        GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/0, // src0
        GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(1), /*SubOperand*/1, // src1_mods
        GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(1), /*SubOperand*/0, // src1
        GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(2), /*SubOperand*/1, // src2_mods
        GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(2), /*SubOperand*/0, // src2
        GIR_AddImm8, /*InsnID*/0, /*Imm*/0,
        GIR_AddImm8, /*InsnID*/0, /*Imm*/0,
        GIR_ConstrainSelectedInstOperands, /*InsnID*/0,
        GIR_EraseFromParent, /*InsnID*/0,
        // GIR_Coverage, 10286,
        GIR_Done,
      // Label 4835: @336617
      GIM_Try, /*On fail goto*//*Label 4836*/ GIMT_Encode4(336757), // Rule ID 10287 //
        GIM_CheckRegBankForClass, /*MI*/0, /*Op*/0, /*RC*/GIMT_Encode2(AMDGPU::VGPR_32RegClassID),
        GIM_RecordInsn, /*DefineMI*/1, /*MI*/0, /*OpIdx*/1, // MIs[1]
        GIM_CheckOpcode, /*MI*/1, GIMT_Encode2(TargetOpcode::G_FMAXNUM_IEEE),
        GIM_CheckType, /*MI*/1, /*Op*/1, /*Type*/GILLT_s32,
        GIM_CheckType, /*MI*/1, /*Op*/2, /*Type*/GILLT_s32,
        GIM_RecordInsn, /*DefineMI*/2, /*MI*/0, /*OpIdx*/2, // MIs[2]
        GIM_CheckOpcode, /*MI*/2, GIMT_Encode2(TargetOpcode::G_FMAXNUM),
        GIM_CheckType, /*MI*/2, /*Op*/1, /*Type*/GILLT_s32,
        GIM_CheckType, /*MI*/2, /*Op*/2, /*Type*/GILLT_s32,
        GIM_RecordInsn, /*DefineMI*/3, /*MI*/2, /*OpIdx*/2, // MIs[3]
        GIM_CheckOpcode, /*MI*/3, GIMT_Encode2(TargetOpcode::G_FMINNUM),
        // MIs[3] VOP3Mods:src1:src1_mods
        GIM_CheckIsSameOperand, /*MI*/3, /*OpIdx*/1, /*OtherMI*/1, /*OtherOpIdx*/2,
        // MIs[3] VOP3Mods:src0:src0_mods
        GIM_CheckIsSameOperand, /*MI*/3, /*OpIdx*/2, /*OtherMI*/1, /*OtherOpIdx*/1,
        GIM_CheckCxxInsnPredicate, /*MI*/0, /*FnId*/GIMT_Encode2(GICXXPred_MI_Predicate_fminnum_like_nnan),
        GIM_CheckIsSafeToFold, /*InsnID*/1,
        GIM_CheckIsSafeToFold, /*InsnID*/2,
        GIM_CheckIsSafeToFold, /*InsnID*/3,
        GIM_CheckComplexPattern, /*MI*/1, /*Op*/1, /*Renderer*/GIMT_Encode2(0), GIMT_Encode2(GICP_gi_vop3mods),
        GIM_CheckComplexPattern, /*MI*/1, /*Op*/2, /*Renderer*/GIMT_Encode2(1), GIMT_Encode2(GICP_gi_vop3mods),
        GIM_CheckComplexPattern, /*MI*/2, /*Op*/1, /*Renderer*/GIMT_Encode2(2), GIMT_Encode2(GICP_gi_vop3mods),
        // (fminnum_ieee:{ *:[f32] } (fmaxnum_ieee:{ *:[f32] } (VOP3Mods:{ *:[f32] } f32:{ *:[f32] }:$src0, i32:{ *:[i32] }:$src0_mods), (VOP3Mods:{ *:[f32] } f32:{ *:[f32] }:$src1, i32:{ *:[i32] }:$src1_mods)), (fmaxnum:{ *:[f32] } (VOP3Mods:{ *:[f32] } f32:{ *:[f32] }:$src2, i32:{ *:[i32] }:$src2_mods), (fminnum:{ *:[f32] } (VOP3Mods:{ *:[f32] } f32:{ *:[f32] }:$src1, i32:{ *:[i32] }:$src1_mods), (VOP3Mods:{ *:[f32] } f32:{ *:[f32] }:$src0, i32:{ *:[i32] }:$src0_mods))))<<P:Predicate_fminnum_like_nnan>>  =>  (V_MED3_F32_e64:{ *:[f32] } ?:{ *:[i32] }:$src0_mods, ?:{ *:[f32] }:$src0, ?:{ *:[i32] }:$src1_mods, ?:{ *:[f32] }:$src1, ?:{ *:[i32] }:$src2_mods, ?:{ *:[f32] }:$src2, 0:{ *:[i1] }, 0:{ *:[i32] })
        GIR_BuildMI, /*InsnID*/0, /*Opcode*/GIMT_Encode2(AMDGPU::V_MED3_F32_e64),
        GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/0, // DstI[vdst]
        GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/1, // src0_mods
        GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/0, // src0
        GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(1), /*SubOperand*/1, // src1_mods
        GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(1), /*SubOperand*/0, // src1
        GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(2), /*SubOperand*/1, // src2_mods
        GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(2), /*SubOperand*/0, // src2
        GIR_AddImm8, /*InsnID*/0, /*Imm*/0,
        GIR_AddImm8, /*InsnID*/0, /*Imm*/0,
        GIR_ConstrainSelectedInstOperands, /*InsnID*/0,
        GIR_EraseFromParent, /*InsnID*/0,
        // GIR_Coverage, 10287,
        GIR_Done,
      // Label 4836: @336757
      GIM_Try, /*On fail goto*//*Label 4837*/ GIMT_Encode4(336897), // Rule ID 10290 //
        GIM_CheckRegBankForClass, /*MI*/0, /*Op*/0, /*RC*/GIMT_Encode2(AMDGPU::VGPR_32RegClassID),
        GIM_RecordInsn, /*DefineMI*/1, /*MI*/0, /*OpIdx*/1, // MIs[1]
        GIM_CheckOpcode, /*MI*/1, GIMT_Encode2(TargetOpcode::G_FMAXNUM_IEEE),
        GIM_CheckType, /*MI*/1, /*Op*/1, /*Type*/GILLT_s32,
        GIM_CheckType, /*MI*/1, /*Op*/2, /*Type*/GILLT_s32,
        GIM_RecordInsn, /*DefineMI*/2, /*MI*/0, /*OpIdx*/2, // MIs[2]
        GIM_CheckOpcode, /*MI*/2, GIMT_Encode2(TargetOpcode::G_FMAXNUM),
        GIM_CheckType, /*MI*/2, /*Op*/1, /*Type*/GILLT_s32,
        GIM_CheckType, /*MI*/2, /*Op*/2, /*Type*/GILLT_s32,
        GIM_RecordInsn, /*DefineMI*/3, /*MI*/2, /*OpIdx*/2, // MIs[3]
        GIM_CheckOpcode, /*MI*/3, GIMT_Encode2(TargetOpcode::G_FMINNUM),
        // MIs[3] VOP3Mods:src0:src0_mods
        GIM_CheckIsSameOperand, /*MI*/3, /*OpIdx*/1, /*OtherMI*/1, /*OtherOpIdx*/2,
        // MIs[3] VOP3Mods:src1:src1_mods
        GIM_CheckIsSameOperand, /*MI*/3, /*OpIdx*/2, /*OtherMI*/1, /*OtherOpIdx*/1,
        GIM_CheckCxxInsnPredicate, /*MI*/0, /*FnId*/GIMT_Encode2(GICXXPred_MI_Predicate_fminnum_like_nnan),
        GIM_CheckIsSafeToFold, /*InsnID*/1,
        GIM_CheckIsSafeToFold, /*InsnID*/2,
        GIM_CheckIsSafeToFold, /*InsnID*/3,
        GIM_CheckComplexPattern, /*MI*/1, /*Op*/1, /*Renderer*/GIMT_Encode2(0), GIMT_Encode2(GICP_gi_vop3mods),
        GIM_CheckComplexPattern, /*MI*/1, /*Op*/2, /*Renderer*/GIMT_Encode2(1), GIMT_Encode2(GICP_gi_vop3mods),
        GIM_CheckComplexPattern, /*MI*/2, /*Op*/1, /*Renderer*/GIMT_Encode2(2), GIMT_Encode2(GICP_gi_vop3mods),
        // (fminnum_ieee:{ *:[f32] } (fmaxnum_ieee:{ *:[f32] } (VOP3Mods:{ *:[f32] } f32:{ *:[f32] }:$src1, i32:{ *:[i32] }:$src1_mods), (VOP3Mods:{ *:[f32] } f32:{ *:[f32] }:$src0, i32:{ *:[i32] }:$src0_mods)), (fmaxnum:{ *:[f32] } (VOP3Mods:{ *:[f32] } f32:{ *:[f32] }:$src2, i32:{ *:[i32] }:$src2_mods), (fminnum:{ *:[f32] } (VOP3Mods:{ *:[f32] } f32:{ *:[f32] }:$src0, i32:{ *:[i32] }:$src0_mods), (VOP3Mods:{ *:[f32] } f32:{ *:[f32] }:$src1, i32:{ *:[i32] }:$src1_mods))))<<P:Predicate_fminnum_like_nnan>>  =>  (V_MED3_F32_e64:{ *:[f32] } ?:{ *:[i32] }:$src0_mods, ?:{ *:[f32] }:$src0, ?:{ *:[i32] }:$src1_mods, ?:{ *:[f32] }:$src1, ?:{ *:[i32] }:$src2_mods, ?:{ *:[f32] }:$src2, 0:{ *:[i1] }, 0:{ *:[i32] })
        GIR_BuildMI, /*InsnID*/0, /*Opcode*/GIMT_Encode2(AMDGPU::V_MED3_F32_e64),
        GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/0, // DstI[vdst]
        GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(1), /*SubOperand*/1, // src0_mods
        GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(1), /*SubOperand*/0, // src0
        GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/1, // src1_mods
        GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/0, // src1
        GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(2), /*SubOperand*/1, // src2_mods
        GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(2), /*SubOperand*/0, // src2
        GIR_AddImm8, /*InsnID*/0, /*Imm*/0,
        GIR_AddImm8, /*InsnID*/0, /*Imm*/0,
        GIR_ConstrainSelectedInstOperands, /*InsnID*/0,
        GIR_EraseFromParent, /*InsnID*/0,
        // GIR_Coverage, 10290,
        GIR_Done,
      // Label 4837: @336897
      GIM_Try, /*On fail goto*//*Label 4838*/ GIMT_Encode4(337037), // Rule ID 10291 //
        GIM_CheckRegBankForClass, /*MI*/0, /*Op*/0, /*RC*/GIMT_Encode2(AMDGPU::VGPR_32RegClassID),
        GIM_RecordInsn, /*DefineMI*/1, /*MI*/0, /*OpIdx*/1, // MIs[1]
        GIM_CheckOpcode, /*MI*/1, GIMT_Encode2(TargetOpcode::G_FMAXNUM_IEEE),
        GIM_CheckType, /*MI*/1, /*Op*/1, /*Type*/GILLT_s32,
        GIM_CheckType, /*MI*/1, /*Op*/2, /*Type*/GILLT_s32,
        GIM_RecordInsn, /*DefineMI*/2, /*MI*/0, /*OpIdx*/2, // MIs[2]
        GIM_CheckOpcode, /*MI*/2, GIMT_Encode2(TargetOpcode::G_FMAXNUM),
        GIM_CheckType, /*MI*/2, /*Op*/1, /*Type*/GILLT_s32,
        GIM_CheckType, /*MI*/2, /*Op*/2, /*Type*/GILLT_s32,
        GIM_RecordInsn, /*DefineMI*/3, /*MI*/2, /*OpIdx*/2, // MIs[3]
        GIM_CheckOpcode, /*MI*/3, GIMT_Encode2(TargetOpcode::G_FMINNUM),
        // MIs[3] VOP3Mods:src1:src1_mods
        GIM_CheckIsSameOperand, /*MI*/3, /*OpIdx*/1, /*OtherMI*/1, /*OtherOpIdx*/1,
        // MIs[3] VOP3Mods:src0:src0_mods
        GIM_CheckIsSameOperand, /*MI*/3, /*OpIdx*/2, /*OtherMI*/1, /*OtherOpIdx*/2,
        GIM_CheckCxxInsnPredicate, /*MI*/0, /*FnId*/GIMT_Encode2(GICXXPred_MI_Predicate_fminnum_like_nnan),
        GIM_CheckIsSafeToFold, /*InsnID*/1,
        GIM_CheckIsSafeToFold, /*InsnID*/2,
        GIM_CheckIsSafeToFold, /*InsnID*/3,
        GIM_CheckComplexPattern, /*MI*/1, /*Op*/1, /*Renderer*/GIMT_Encode2(0), GIMT_Encode2(GICP_gi_vop3mods),
        GIM_CheckComplexPattern, /*MI*/1, /*Op*/2, /*Renderer*/GIMT_Encode2(1), GIMT_Encode2(GICP_gi_vop3mods),
        GIM_CheckComplexPattern, /*MI*/2, /*Op*/1, /*Renderer*/GIMT_Encode2(2), GIMT_Encode2(GICP_gi_vop3mods),
        // (fminnum_ieee:{ *:[f32] } (fmaxnum_ieee:{ *:[f32] } (VOP3Mods:{ *:[f32] } f32:{ *:[f32] }:$src1, i32:{ *:[i32] }:$src1_mods), (VOP3Mods:{ *:[f32] } f32:{ *:[f32] }:$src0, i32:{ *:[i32] }:$src0_mods)), (fmaxnum:{ *:[f32] } (VOP3Mods:{ *:[f32] } f32:{ *:[f32] }:$src2, i32:{ *:[i32] }:$src2_mods), (fminnum:{ *:[f32] } (VOP3Mods:{ *:[f32] } f32:{ *:[f32] }:$src1, i32:{ *:[i32] }:$src1_mods), (VOP3Mods:{ *:[f32] } f32:{ *:[f32] }:$src0, i32:{ *:[i32] }:$src0_mods))))<<P:Predicate_fminnum_like_nnan>>  =>  (V_MED3_F32_e64:{ *:[f32] } ?:{ *:[i32] }:$src0_mods, ?:{ *:[f32] }:$src0, ?:{ *:[i32] }:$src1_mods, ?:{ *:[f32] }:$src1, ?:{ *:[i32] }:$src2_mods, ?:{ *:[f32] }:$src2, 0:{ *:[i1] }, 0:{ *:[i32] })
        GIR_BuildMI, /*InsnID*/0, /*Opcode*/GIMT_Encode2(AMDGPU::V_MED3_F32_e64),
        GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/0, // DstI[vdst]
        GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(1), /*SubOperand*/1, // src0_mods
        GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(1), /*SubOperand*/0, // src0
        GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/1, // src1_mods
        GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/0, // src1
        GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(2), /*SubOperand*/1, // src2_mods
        GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(2), /*SubOperand*/0, // src2
        GIR_AddImm8, /*InsnID*/0, /*Imm*/0,
        GIR_AddImm8, /*InsnID*/0, /*Imm*/0,
        GIR_ConstrainSelectedInstOperands, /*InsnID*/0,
        GIR_EraseFromParent, /*InsnID*/0,
        // GIR_Coverage, 10291,
        GIR_Done,
      // Label 4838: @337037
      GIM_Try, /*On fail goto*//*Label 4839*/ GIMT_Encode4(337177), // Rule ID 10271 //
        GIM_CheckRegBankForClass, /*MI*/0, /*Op*/0, /*RC*/GIMT_Encode2(AMDGPU::VGPR_32RegClassID),
        GIM_RecordInsn, /*DefineMI*/1, /*MI*/0, /*OpIdx*/1, // MIs[1]
        GIM_CheckOpcode, /*MI*/1, GIMT_Encode2(TargetOpcode::G_FMAXNUM_IEEE),
        GIM_CheckType, /*MI*/1, /*Op*/1, /*Type*/GILLT_s32,
        GIM_CheckType, /*MI*/1, /*Op*/2, /*Type*/GILLT_s32,
        GIM_RecordInsn, /*DefineMI*/2, /*MI*/0, /*OpIdx*/2, // MIs[2]
        GIM_CheckOpcode, /*MI*/2, GIMT_Encode2(TargetOpcode::G_FMAXNUM),
        GIM_CheckType, /*MI*/2, /*Op*/1, /*Type*/GILLT_s32,
        GIM_CheckType, /*MI*/2, /*Op*/2, /*Type*/GILLT_s32,
        GIM_RecordInsn, /*DefineMI*/3, /*MI*/2, /*OpIdx*/2, // MIs[3]
        GIM_CheckOpcode, /*MI*/3, GIMT_Encode2(TargetOpcode::G_FMINNUM_IEEE),
        // MIs[3] VOP3Mods:src0:src0_mods
        GIM_CheckIsSameOperand, /*MI*/3, /*OpIdx*/1, /*OtherMI*/1, /*OtherOpIdx*/1,
        // MIs[3] VOP3Mods:src1:src1_mods
        GIM_CheckIsSameOperand, /*MI*/3, /*OpIdx*/2, /*OtherMI*/1, /*OtherOpIdx*/2,
        GIM_CheckCxxInsnPredicate, /*MI*/0, /*FnId*/GIMT_Encode2(GICXXPred_MI_Predicate_fminnum_like_nnan),
        GIM_CheckIsSafeToFold, /*InsnID*/1,
        GIM_CheckIsSafeToFold, /*InsnID*/2,
        GIM_CheckIsSafeToFold, /*InsnID*/3,
        GIM_CheckComplexPattern, /*MI*/1, /*Op*/1, /*Renderer*/GIMT_Encode2(0), GIMT_Encode2(GICP_gi_vop3mods),
        GIM_CheckComplexPattern, /*MI*/1, /*Op*/2, /*Renderer*/GIMT_Encode2(1), GIMT_Encode2(GICP_gi_vop3mods),
        GIM_CheckComplexPattern, /*MI*/2, /*Op*/1, /*Renderer*/GIMT_Encode2(2), GIMT_Encode2(GICP_gi_vop3mods),
        // (fminnum_ieee:{ *:[f32] } (fmaxnum_ieee:{ *:[f32] } (VOP3Mods:{ *:[f32] } f32:{ *:[f32] }:$src0, i32:{ *:[i32] }:$src0_mods), (VOP3Mods:{ *:[f32] } f32:{ *:[f32] }:$src1, i32:{ *:[i32] }:$src1_mods)), (fmaxnum:{ *:[f32] } (VOP3Mods:{ *:[f32] } f32:{ *:[f32] }:$src2, i32:{ *:[i32] }:$src2_mods), (fminnum_ieee:{ *:[f32] } (VOP3Mods:{ *:[f32] } f32:{ *:[f32] }:$src0, i32:{ *:[i32] }:$src0_mods), (VOP3Mods:{ *:[f32] } f32:{ *:[f32] }:$src1, i32:{ *:[i32] }:$src1_mods))))<<P:Predicate_fminnum_like_nnan>>  =>  (V_MED3_F32_e64:{ *:[f32] } ?:{ *:[i32] }:$src0_mods, ?:{ *:[f32] }:$src0, ?:{ *:[i32] }:$src1_mods, ?:{ *:[f32] }:$src1, ?:{ *:[i32] }:$src2_mods, ?:{ *:[f32] }:$src2, 0:{ *:[i1] }, 0:{ *:[i32] })
        GIR_BuildMI, /*InsnID*/0, /*Opcode*/GIMT_Encode2(AMDGPU::V_MED3_F32_e64),
        GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/0, // DstI[vdst]
        GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/1, // src0_mods
        GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/0, // src0
        GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(1), /*SubOperand*/1, // src1_mods
        GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(1), /*SubOperand*/0, // src1
        GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(2), /*SubOperand*/1, // src2_mods
        GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(2), /*SubOperand*/0, // src2
        GIR_AddImm8, /*InsnID*/0, /*Imm*/0,
        GIR_AddImm8, /*InsnID*/0, /*Imm*/0,
        GIR_ConstrainSelectedInstOperands, /*InsnID*/0,
        GIR_EraseFromParent, /*InsnID*/0,
        // GIR_Coverage, 10271,
        GIR_Done,
      // Label 4839: @337177
      GIM_Try, /*On fail goto*//*Label 4840*/ GIMT_Encode4(337317), // Rule ID 10272 //
        GIM_CheckRegBankForClass, /*MI*/0, /*Op*/0, /*RC*/GIMT_Encode2(AMDGPU::VGPR_32RegClassID),
        GIM_RecordInsn, /*DefineMI*/1, /*MI*/0, /*OpIdx*/1, // MIs[1]
        GIM_CheckOpcode, /*MI*/1, GIMT_Encode2(TargetOpcode::G_FMAXNUM_IEEE),
        GIM_CheckType, /*MI*/1, /*Op*/1, /*Type*/GILLT_s32,
        GIM_CheckType, /*MI*/1, /*Op*/2, /*Type*/GILLT_s32,
        GIM_RecordInsn, /*DefineMI*/2, /*MI*/0, /*OpIdx*/2, // MIs[2]
        GIM_CheckOpcode, /*MI*/2, GIMT_Encode2(TargetOpcode::G_FMAXNUM),
        GIM_CheckType, /*MI*/2, /*Op*/1, /*Type*/GILLT_s32,
        GIM_CheckType, /*MI*/2, /*Op*/2, /*Type*/GILLT_s32,
        GIM_RecordInsn, /*DefineMI*/3, /*MI*/2, /*OpIdx*/2, // MIs[3]
        GIM_CheckOpcode, /*MI*/3, GIMT_Encode2(TargetOpcode::G_FMINNUM_IEEE),
        // MIs[3] VOP3Mods:src1:src1_mods
        GIM_CheckIsSameOperand, /*MI*/3, /*OpIdx*/1, /*OtherMI*/1, /*OtherOpIdx*/2,
        // MIs[3] VOP3Mods:src0:src0_mods
        GIM_CheckIsSameOperand, /*MI*/3, /*OpIdx*/2, /*OtherMI*/1, /*OtherOpIdx*/1,
        GIM_CheckCxxInsnPredicate, /*MI*/0, /*FnId*/GIMT_Encode2(GICXXPred_MI_Predicate_fminnum_like_nnan),
        GIM_CheckIsSafeToFold, /*InsnID*/1,
        GIM_CheckIsSafeToFold, /*InsnID*/2,
        GIM_CheckIsSafeToFold, /*InsnID*/3,
        GIM_CheckComplexPattern, /*MI*/1, /*Op*/1, /*Renderer*/GIMT_Encode2(0), GIMT_Encode2(GICP_gi_vop3mods),
        GIM_CheckComplexPattern, /*MI*/1, /*Op*/2, /*Renderer*/GIMT_Encode2(1), GIMT_Encode2(GICP_gi_vop3mods),
        GIM_CheckComplexPattern, /*MI*/2, /*Op*/1, /*Renderer*/GIMT_Encode2(2), GIMT_Encode2(GICP_gi_vop3mods),
        // (fminnum_ieee:{ *:[f32] } (fmaxnum_ieee:{ *:[f32] } (VOP3Mods:{ *:[f32] } f32:{ *:[f32] }:$src0, i32:{ *:[i32] }:$src0_mods), (VOP3Mods:{ *:[f32] } f32:{ *:[f32] }:$src1, i32:{ *:[i32] }:$src1_mods)), (fmaxnum:{ *:[f32] } (VOP3Mods:{ *:[f32] } f32:{ *:[f32] }:$src2, i32:{ *:[i32] }:$src2_mods), (fminnum_ieee:{ *:[f32] } (VOP3Mods:{ *:[f32] } f32:{ *:[f32] }:$src1, i32:{ *:[i32] }:$src1_mods), (VOP3Mods:{ *:[f32] } f32:{ *:[f32] }:$src0, i32:{ *:[i32] }:$src0_mods))))<<P:Predicate_fminnum_like_nnan>>  =>  (V_MED3_F32_e64:{ *:[f32] } ?:{ *:[i32] }:$src0_mods, ?:{ *:[f32] }:$src0, ?:{ *:[i32] }:$src1_mods, ?:{ *:[f32] }:$src1, ?:{ *:[i32] }:$src2_mods, ?:{ *:[f32] }:$src2, 0:{ *:[i1] }, 0:{ *:[i32] })
        GIR_BuildMI, /*InsnID*/0, /*Opcode*/GIMT_Encode2(AMDGPU::V_MED3_F32_e64),
        GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/0, // DstI[vdst]
        GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/1, // src0_mods
        GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/0, // src0
        GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(1), /*SubOperand*/1, // src1_mods
        GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(1), /*SubOperand*/0, // src1
        GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(2), /*SubOperand*/1, // src2_mods
        GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(2), /*SubOperand*/0, // src2
        GIR_AddImm8, /*InsnID*/0, /*Imm*/0,
        GIR_AddImm8, /*InsnID*/0, /*Imm*/0,
        GIR_ConstrainSelectedInstOperands, /*InsnID*/0,
        GIR_EraseFromParent, /*InsnID*/0,
        // GIR_Coverage, 10272,
        GIR_Done,
      // Label 4840: @337317
      GIM_Try, /*On fail goto*//*Label 4841*/ GIMT_Encode4(337457), // Rule ID 10275 //
        GIM_CheckRegBankForClass, /*MI*/0, /*Op*/0, /*RC*/GIMT_Encode2(AMDGPU::VGPR_32RegClassID),
        GIM_RecordInsn, /*DefineMI*/1, /*MI*/0, /*OpIdx*/1, // MIs[1]
        GIM_CheckOpcode, /*MI*/1, GIMT_Encode2(TargetOpcode::G_FMAXNUM_IEEE),
        GIM_CheckType, /*MI*/1, /*Op*/1, /*Type*/GILLT_s32,
        GIM_CheckType, /*MI*/1, /*Op*/2, /*Type*/GILLT_s32,
        GIM_RecordInsn, /*DefineMI*/2, /*MI*/0, /*OpIdx*/2, // MIs[2]
        GIM_CheckOpcode, /*MI*/2, GIMT_Encode2(TargetOpcode::G_FMAXNUM),
        GIM_CheckType, /*MI*/2, /*Op*/1, /*Type*/GILLT_s32,
        GIM_CheckType, /*MI*/2, /*Op*/2, /*Type*/GILLT_s32,
        GIM_RecordInsn, /*DefineMI*/3, /*MI*/2, /*OpIdx*/2, // MIs[3]
        GIM_CheckOpcode, /*MI*/3, GIMT_Encode2(TargetOpcode::G_FMINNUM_IEEE),
        // MIs[3] VOP3Mods:src0:src0_mods
        GIM_CheckIsSameOperand, /*MI*/3, /*OpIdx*/1, /*OtherMI*/1, /*OtherOpIdx*/2,
        // MIs[3] VOP3Mods:src1:src1_mods
        GIM_CheckIsSameOperand, /*MI*/3, /*OpIdx*/2, /*OtherMI*/1, /*OtherOpIdx*/1,
        GIM_CheckCxxInsnPredicate, /*MI*/0, /*FnId*/GIMT_Encode2(GICXXPred_MI_Predicate_fminnum_like_nnan),
        GIM_CheckIsSafeToFold, /*InsnID*/1,
        GIM_CheckIsSafeToFold, /*InsnID*/2,
        GIM_CheckIsSafeToFold, /*InsnID*/3,
        GIM_CheckComplexPattern, /*MI*/1, /*Op*/1, /*Renderer*/GIMT_Encode2(0), GIMT_Encode2(GICP_gi_vop3mods),
        GIM_CheckComplexPattern, /*MI*/1, /*Op*/2, /*Renderer*/GIMT_Encode2(1), GIMT_Encode2(GICP_gi_vop3mods),
        GIM_CheckComplexPattern, /*MI*/2, /*Op*/1, /*Renderer*/GIMT_Encode2(2), GIMT_Encode2(GICP_gi_vop3mods),
        // (fminnum_ieee:{ *:[f32] } (fmaxnum_ieee:{ *:[f32] } (VOP3Mods:{ *:[f32] } f32:{ *:[f32] }:$src1, i32:{ *:[i32] }:$src1_mods), (VOP3Mods:{ *:[f32] } f32:{ *:[f32] }:$src0, i32:{ *:[i32] }:$src0_mods)), (fmaxnum:{ *:[f32] } (VOP3Mods:{ *:[f32] } f32:{ *:[f32] }:$src2, i32:{ *:[i32] }:$src2_mods), (fminnum_ieee:{ *:[f32] } (VOP3Mods:{ *:[f32] } f32:{ *:[f32] }:$src0, i32:{ *:[i32] }:$src0_mods), (VOP3Mods:{ *:[f32] } f32:{ *:[f32] }:$src1, i32:{ *:[i32] }:$src1_mods))))<<P:Predicate_fminnum_like_nnan>>  =>  (V_MED3_F32_e64:{ *:[f32] } ?:{ *:[i32] }:$src0_mods, ?:{ *:[f32] }:$src0, ?:{ *:[i32] }:$src1_mods, ?:{ *:[f32] }:$src1, ?:{ *:[i32] }:$src2_mods, ?:{ *:[f32] }:$src2, 0:{ *:[i1] }, 0:{ *:[i32] })
        GIR_BuildMI, /*InsnID*/0, /*Opcode*/GIMT_Encode2(AMDGPU::V_MED3_F32_e64),
        GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/0, // DstI[vdst]
        GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(1), /*SubOperand*/1, // src0_mods
        GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(1), /*SubOperand*/0, // src0
        GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/1, // src1_mods
        GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/0, // src1
        GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(2), /*SubOperand*/1, // src2_mods
        GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(2), /*SubOperand*/0, // src2
        GIR_AddImm8, /*InsnID*/0, /*Imm*/0,
        GIR_AddImm8, /*InsnID*/0, /*Imm*/0,
        GIR_ConstrainSelectedInstOperands, /*InsnID*/0,
        GIR_EraseFromParent, /*InsnID*/0,
        // GIR_Coverage, 10275,
        GIR_Done,
      // Label 4841: @337457
      GIM_Try, /*On fail goto*//*Label 4842*/ GIMT_Encode4(337597), // Rule ID 10276 //
        GIM_CheckRegBankForClass, /*MI*/0, /*Op*/0, /*RC*/GIMT_Encode2(AMDGPU::VGPR_32RegClassID),
        GIM_RecordInsn, /*DefineMI*/1, /*MI*/0, /*OpIdx*/1, // MIs[1]
        GIM_CheckOpcode, /*MI*/1, GIMT_Encode2(TargetOpcode::G_FMAXNUM_IEEE),
        GIM_CheckType, /*MI*/1, /*Op*/1, /*Type*/GILLT_s32,
        GIM_CheckType, /*MI*/1, /*Op*/2, /*Type*/GILLT_s32,
        GIM_RecordInsn, /*DefineMI*/2, /*MI*/0, /*OpIdx*/2, // MIs[2]
        GIM_CheckOpcode, /*MI*/2, GIMT_Encode2(TargetOpcode::G_FMAXNUM),
        GIM_CheckType, /*MI*/2, /*Op*/1, /*Type*/GILLT_s32,
        GIM_CheckType, /*MI*/2, /*Op*/2, /*Type*/GILLT_s32,
        GIM_RecordInsn, /*DefineMI*/3, /*MI*/2, /*OpIdx*/2, // MIs[3]
        GIM_CheckOpcode, /*MI*/3, GIMT_Encode2(TargetOpcode::G_FMINNUM_IEEE),
        // MIs[3] VOP3Mods:src1:src1_mods
        GIM_CheckIsSameOperand, /*MI*/3, /*OpIdx*/1, /*OtherMI*/1, /*OtherOpIdx*/1,
        // MIs[3] VOP3Mods:src0:src0_mods
        GIM_CheckIsSameOperand, /*MI*/3, /*OpIdx*/2, /*OtherMI*/1, /*OtherOpIdx*/2,
        GIM_CheckCxxInsnPredicate, /*MI*/0, /*FnId*/GIMT_Encode2(GICXXPred_MI_Predicate_fminnum_like_nnan),
        GIM_CheckIsSafeToFold, /*InsnID*/1,
        GIM_CheckIsSafeToFold, /*InsnID*/2,
        GIM_CheckIsSafeToFold, /*InsnID*/3,
        GIM_CheckComplexPattern, /*MI*/1, /*Op*/1, /*Renderer*/GIMT_Encode2(0), GIMT_Encode2(GICP_gi_vop3mods),
        GIM_CheckComplexPattern, /*MI*/1, /*Op*/2, /*Renderer*/GIMT_Encode2(1), GIMT_Encode2(GICP_gi_vop3mods),
        GIM_CheckComplexPattern, /*MI*/2, /*Op*/1, /*Renderer*/GIMT_Encode2(2), GIMT_Encode2(GICP_gi_vop3mods),
        // (fminnum_ieee:{ *:[f32] } (fmaxnum_ieee:{ *:[f32] } (VOP3Mods:{ *:[f32] } f32:{ *:[f32] }:$src1, i32:{ *:[i32] }:$src1_mods), (VOP3Mods:{ *:[f32] } f32:{ *:[f32] }:$src0, i32:{ *:[i32] }:$src0_mods)), (fmaxnum:{ *:[f32] } (VOP3Mods:{ *:[f32] } f32:{ *:[f32] }:$src2, i32:{ *:[i32] }:$src2_mods), (fminnum_ieee:{ *:[f32] } (VOP3Mods:{ *:[f32] } f32:{ *:[f32] }:$src1, i32:{ *:[i32] }:$src1_mods), (VOP3Mods:{ *:[f32] } f32:{ *:[f32] }:$src0, i32:{ *:[i32] }:$src0_mods))))<<P:Predicate_fminnum_like_nnan>>  =>  (V_MED3_F32_e64:{ *:[f32] } ?:{ *:[i32] }:$src0_mods, ?:{ *:[f32] }:$src0, ?:{ *:[i32] }:$src1_mods, ?:{ *:[f32] }:$src1, ?:{ *:[i32] }:$src2_mods, ?:{ *:[f32] }:$src2, 0:{ *:[i1] }, 0:{ *:[i32] })
        GIR_BuildMI, /*InsnID*/0, /*Opcode*/GIMT_Encode2(AMDGPU::V_MED3_F32_e64),
        GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/0, // DstI[vdst]
        GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(1), /*SubOperand*/1, // src0_mods
        GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(1), /*SubOperand*/0, // src0
        GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/1, // src1_mods
        GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/0, // src1
        GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(2), /*SubOperand*/1, // src2_mods
        GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(2), /*SubOperand*/0, // src2
        GIR_AddImm8, /*InsnID*/0, /*Imm*/0,
        GIR_AddImm8, /*InsnID*/0, /*Imm*/0,
        GIR_ConstrainSelectedInstOperands, /*InsnID*/0,
        GIR_EraseFromParent, /*InsnID*/0,
        // GIR_Coverage, 10276,
        GIR_Done,
      // Label 4842: @337597
      GIM_Try, /*On fail goto*//*Label 4843*/ GIMT_Encode4(337737), // Rule ID 6501 //
        GIM_CheckRegBankForClass, /*MI*/0, /*Op*/0, /*RC*/GIMT_Encode2(AMDGPU::VGPR_32RegClassID),
        GIM_RecordInsn, /*DefineMI*/1, /*MI*/0, /*OpIdx*/1, // MIs[1]
        GIM_CheckOpcode, /*MI*/1, GIMT_Encode2(TargetOpcode::G_FMAXNUM_IEEE),
        GIM_CheckType, /*MI*/1, /*Op*/1, /*Type*/GILLT_s32,
        GIM_CheckType, /*MI*/1, /*Op*/2, /*Type*/GILLT_s32,
        GIM_RecordInsn, /*DefineMI*/2, /*MI*/0, /*OpIdx*/2, // MIs[2]
        GIM_CheckOpcode, /*MI*/2, GIMT_Encode2(TargetOpcode::G_FMAXNUM),
        GIM_CheckType, /*MI*/2, /*Op*/1, /*Type*/GILLT_s32,
        GIM_CheckType, /*MI*/2, /*Op*/2, /*Type*/GILLT_s32,
        GIM_RecordInsn, /*DefineMI*/3, /*MI*/2, /*OpIdx*/1, // MIs[3]
        GIM_CheckOpcode, /*MI*/3, GIMT_Encode2(TargetOpcode::G_FMINNUM),
        // MIs[3] VOP3Mods:src0:src0_mods
        GIM_CheckIsSameOperand, /*MI*/3, /*OpIdx*/1, /*OtherMI*/1, /*OtherOpIdx*/1,
        // MIs[3] VOP3Mods:src1:src1_mods
        GIM_CheckIsSameOperand, /*MI*/3, /*OpIdx*/2, /*OtherMI*/1, /*OtherOpIdx*/2,
        GIM_CheckCxxInsnPredicate, /*MI*/0, /*FnId*/GIMT_Encode2(GICXXPred_MI_Predicate_fminnum_like_nnan),
        GIM_CheckIsSafeToFold, /*InsnID*/1,
        GIM_CheckIsSafeToFold, /*InsnID*/2,
        GIM_CheckIsSafeToFold, /*InsnID*/3,
        GIM_CheckComplexPattern, /*MI*/1, /*Op*/1, /*Renderer*/GIMT_Encode2(0), GIMT_Encode2(GICP_gi_vop3mods),
        GIM_CheckComplexPattern, /*MI*/1, /*Op*/2, /*Renderer*/GIMT_Encode2(1), GIMT_Encode2(GICP_gi_vop3mods),
        GIM_CheckComplexPattern, /*MI*/2, /*Op*/2, /*Renderer*/GIMT_Encode2(2), GIMT_Encode2(GICP_gi_vop3mods),
        // (fminnum_ieee:{ *:[f32] } (fmaxnum_ieee:{ *:[f32] } (VOP3Mods:{ *:[f32] } f32:{ *:[f32] }:$src0, i32:{ *:[i32] }:$src0_mods), (VOP3Mods:{ *:[f32] } f32:{ *:[f32] }:$src1, i32:{ *:[i32] }:$src1_mods)), (fmaxnum:{ *:[f32] } (fminnum:{ *:[f32] } (VOP3Mods:{ *:[f32] } f32:{ *:[f32] }:$src0, i32:{ *:[i32] }:$src0_mods), (VOP3Mods:{ *:[f32] } f32:{ *:[f32] }:$src1, i32:{ *:[i32] }:$src1_mods)), (VOP3Mods:{ *:[f32] } f32:{ *:[f32] }:$src2, i32:{ *:[i32] }:$src2_mods)))<<P:Predicate_fminnum_like_nnan>>  =>  (V_MED3_F32_e64:{ *:[f32] } ?:{ *:[i32] }:$src0_mods, ?:{ *:[f32] }:$src0, ?:{ *:[i32] }:$src1_mods, ?:{ *:[f32] }:$src1, ?:{ *:[i32] }:$src2_mods, ?:{ *:[f32] }:$src2, 0:{ *:[i1] }, 0:{ *:[i32] })
        GIR_BuildMI, /*InsnID*/0, /*Opcode*/GIMT_Encode2(AMDGPU::V_MED3_F32_e64),
        GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/0, // DstI[vdst]
        GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/1, // src0_mods
        GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/0, // src0
        GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(1), /*SubOperand*/1, // src1_mods
        GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(1), /*SubOperand*/0, // src1
        GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(2), /*SubOperand*/1, // src2_mods
        GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(2), /*SubOperand*/0, // src2
        GIR_AddImm8, /*InsnID*/0, /*Imm*/0,
        GIR_AddImm8, /*InsnID*/0, /*Imm*/0,
        GIR_ConstrainSelectedInstOperands, /*InsnID*/0,
        GIR_EraseFromParent, /*InsnID*/0,
        // GIR_Coverage, 6501,
        GIR_Done,
      // Label 4843: @337737
      GIM_Try, /*On fail goto*//*Label 4844*/ GIMT_Encode4(337877), // Rule ID 10285 //
        GIM_CheckRegBankForClass, /*MI*/0, /*Op*/0, /*RC*/GIMT_Encode2(AMDGPU::VGPR_32RegClassID),
        GIM_RecordInsn, /*DefineMI*/1, /*MI*/0, /*OpIdx*/1, // MIs[1]
        GIM_CheckOpcode, /*MI*/1, GIMT_Encode2(TargetOpcode::G_FMAXNUM_IEEE),
        GIM_CheckType, /*MI*/1, /*Op*/1, /*Type*/GILLT_s32,
        GIM_CheckType, /*MI*/1, /*Op*/2, /*Type*/GILLT_s32,
        GIM_RecordInsn, /*DefineMI*/2, /*MI*/0, /*OpIdx*/2, // MIs[2]
        GIM_CheckOpcode, /*MI*/2, GIMT_Encode2(TargetOpcode::G_FMAXNUM),
        GIM_CheckType, /*MI*/2, /*Op*/1, /*Type*/GILLT_s32,
        GIM_CheckType, /*MI*/2, /*Op*/2, /*Type*/GILLT_s32,
        GIM_RecordInsn, /*DefineMI*/3, /*MI*/2, /*OpIdx*/1, // MIs[3]
        GIM_CheckOpcode, /*MI*/3, GIMT_Encode2(TargetOpcode::G_FMINNUM),
        // MIs[3] VOP3Mods:src1:src1_mods
        GIM_CheckIsSameOperand, /*MI*/3, /*OpIdx*/1, /*OtherMI*/1, /*OtherOpIdx*/2,
        // MIs[3] VOP3Mods:src0:src0_mods
        GIM_CheckIsSameOperand, /*MI*/3, /*OpIdx*/2, /*OtherMI*/1, /*OtherOpIdx*/1,
        GIM_CheckCxxInsnPredicate, /*MI*/0, /*FnId*/GIMT_Encode2(GICXXPred_MI_Predicate_fminnum_like_nnan),
        GIM_CheckIsSafeToFold, /*InsnID*/1,
        GIM_CheckIsSafeToFold, /*InsnID*/2,
        GIM_CheckIsSafeToFold, /*InsnID*/3,
        GIM_CheckComplexPattern, /*MI*/1, /*Op*/1, /*Renderer*/GIMT_Encode2(0), GIMT_Encode2(GICP_gi_vop3mods),
        GIM_CheckComplexPattern, /*MI*/1, /*Op*/2, /*Renderer*/GIMT_Encode2(1), GIMT_Encode2(GICP_gi_vop3mods),
        GIM_CheckComplexPattern, /*MI*/2, /*Op*/2, /*Renderer*/GIMT_Encode2(2), GIMT_Encode2(GICP_gi_vop3mods),
        // (fminnum_ieee:{ *:[f32] } (fmaxnum_ieee:{ *:[f32] } (VOP3Mods:{ *:[f32] } f32:{ *:[f32] }:$src0, i32:{ *:[i32] }:$src0_mods), (VOP3Mods:{ *:[f32] } f32:{ *:[f32] }:$src1, i32:{ *:[i32] }:$src1_mods)), (fmaxnum:{ *:[f32] } (fminnum:{ *:[f32] } (VOP3Mods:{ *:[f32] } f32:{ *:[f32] }:$src1, i32:{ *:[i32] }:$src1_mods), (VOP3Mods:{ *:[f32] } f32:{ *:[f32] }:$src0, i32:{ *:[i32] }:$src0_mods)), (VOP3Mods:{ *:[f32] } f32:{ *:[f32] }:$src2, i32:{ *:[i32] }:$src2_mods)))<<P:Predicate_fminnum_like_nnan>>  =>  (V_MED3_F32_e64:{ *:[f32] } ?:{ *:[i32] }:$src0_mods, ?:{ *:[f32] }:$src0, ?:{ *:[i32] }:$src1_mods, ?:{ *:[f32] }:$src1, ?:{ *:[i32] }:$src2_mods, ?:{ *:[f32] }:$src2, 0:{ *:[i1] }, 0:{ *:[i32] })
        GIR_BuildMI, /*InsnID*/0, /*Opcode*/GIMT_Encode2(AMDGPU::V_MED3_F32_e64),
        GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/0, // DstI[vdst]
        GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/1, // src0_mods
        GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/0, // src0
        GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(1), /*SubOperand*/1, // src1_mods
        GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(1), /*SubOperand*/0, // src1
        GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(2), /*SubOperand*/1, // src2_mods
        GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(2), /*SubOperand*/0, // src2
        GIR_AddImm8, /*InsnID*/0, /*Imm*/0,
        GIR_AddImm8, /*InsnID*/0, /*Imm*/0,
        GIR_ConstrainSelectedInstOperands, /*InsnID*/0,
        GIR_EraseFromParent, /*InsnID*/0,
        // GIR_Coverage, 10285,
        GIR_Done,
      // Label 4844: @337877
      GIM_Try, /*On fail goto*//*Label 4845*/ GIMT_Encode4(338017), // Rule ID 10288 //
        GIM_CheckRegBankForClass, /*MI*/0, /*Op*/0, /*RC*/GIMT_Encode2(AMDGPU::VGPR_32RegClassID),
        GIM_RecordInsn, /*DefineMI*/1, /*MI*/0, /*OpIdx*/1, // MIs[1]
        GIM_CheckOpcode, /*MI*/1, GIMT_Encode2(TargetOpcode::G_FMAXNUM_IEEE),
        GIM_CheckType, /*MI*/1, /*Op*/1, /*Type*/GILLT_s32,
        GIM_CheckType, /*MI*/1, /*Op*/2, /*Type*/GILLT_s32,
        GIM_RecordInsn, /*DefineMI*/2, /*MI*/0, /*OpIdx*/2, // MIs[2]
        GIM_CheckOpcode, /*MI*/2, GIMT_Encode2(TargetOpcode::G_FMAXNUM),
        GIM_CheckType, /*MI*/2, /*Op*/1, /*Type*/GILLT_s32,
        GIM_CheckType, /*MI*/2, /*Op*/2, /*Type*/GILLT_s32,
        GIM_RecordInsn, /*DefineMI*/3, /*MI*/2, /*OpIdx*/1, // MIs[3]
        GIM_CheckOpcode, /*MI*/3, GIMT_Encode2(TargetOpcode::G_FMINNUM),
        // MIs[3] VOP3Mods:src0:src0_mods
        GIM_CheckIsSameOperand, /*MI*/3, /*OpIdx*/1, /*OtherMI*/1, /*OtherOpIdx*/2,
        // MIs[3] VOP3Mods:src1:src1_mods
        GIM_CheckIsSameOperand, /*MI*/3, /*OpIdx*/2, /*OtherMI*/1, /*OtherOpIdx*/1,
        GIM_CheckCxxInsnPredicate, /*MI*/0, /*FnId*/GIMT_Encode2(GICXXPred_MI_Predicate_fminnum_like_nnan),
        GIM_CheckIsSafeToFold, /*InsnID*/1,
        GIM_CheckIsSafeToFold, /*InsnID*/2,
        GIM_CheckIsSafeToFold, /*InsnID*/3,
        GIM_CheckComplexPattern, /*MI*/1, /*Op*/1, /*Renderer*/GIMT_Encode2(0), GIMT_Encode2(GICP_gi_vop3mods),
        GIM_CheckComplexPattern, /*MI*/1, /*Op*/2, /*Renderer*/GIMT_Encode2(1), GIMT_Encode2(GICP_gi_vop3mods),
        GIM_CheckComplexPattern, /*MI*/2, /*Op*/2, /*Renderer*/GIMT_Encode2(2), GIMT_Encode2(GICP_gi_vop3mods),
        // (fminnum_ieee:{ *:[f32] } (fmaxnum_ieee:{ *:[f32] } (VOP3Mods:{ *:[f32] } f32:{ *:[f32] }:$src1, i32:{ *:[i32] }:$src1_mods), (VOP3Mods:{ *:[f32] } f32:{ *:[f32] }:$src0, i32:{ *:[i32] }:$src0_mods)), (fmaxnum:{ *:[f32] } (fminnum:{ *:[f32] } (VOP3Mods:{ *:[f32] } f32:{ *:[f32] }:$src0, i32:{ *:[i32] }:$src0_mods), (VOP3Mods:{ *:[f32] } f32:{ *:[f32] }:$src1, i32:{ *:[i32] }:$src1_mods)), (VOP3Mods:{ *:[f32] } f32:{ *:[f32] }:$src2, i32:{ *:[i32] }:$src2_mods)))<<P:Predicate_fminnum_like_nnan>>  =>  (V_MED3_F32_e64:{ *:[f32] } ?:{ *:[i32] }:$src0_mods, ?:{ *:[f32] }:$src0, ?:{ *:[i32] }:$src1_mods, ?:{ *:[f32] }:$src1, ?:{ *:[i32] }:$src2_mods, ?:{ *:[f32] }:$src2, 0:{ *:[i1] }, 0:{ *:[i32] })
        GIR_BuildMI, /*InsnID*/0, /*Opcode*/GIMT_Encode2(AMDGPU::V_MED3_F32_e64),
        GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/0, // DstI[vdst]
        GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(1), /*SubOperand*/1, // src0_mods
        GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(1), /*SubOperand*/0, // src0
        GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/1, // src1_mods
        GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/0, // src1
        GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(2), /*SubOperand*/1, // src2_mods
        GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(2), /*SubOperand*/0, // src2
        GIR_AddImm8, /*InsnID*/0, /*Imm*/0,
        GIR_AddImm8, /*InsnID*/0, /*Imm*/0,
        GIR_ConstrainSelectedInstOperands, /*InsnID*/0,
        GIR_EraseFromParent, /*InsnID*/0,
        // GIR_Coverage, 10288,
        GIR_Done,
      // Label 4845: @338017
      GIM_Try, /*On fail goto*//*Label 4846*/ GIMT_Encode4(338157), // Rule ID 10289 //
        GIM_CheckRegBankForClass, /*MI*/0, /*Op*/0, /*RC*/GIMT_Encode2(AMDGPU::VGPR_32RegClassID),
        GIM_RecordInsn, /*DefineMI*/1, /*MI*/0, /*OpIdx*/1, // MIs[1]
        GIM_CheckOpcode, /*MI*/1, GIMT_Encode2(TargetOpcode::G_FMAXNUM_IEEE),
        GIM_CheckType, /*MI*/1, /*Op*/1, /*Type*/GILLT_s32,
        GIM_CheckType, /*MI*/1, /*Op*/2, /*Type*/GILLT_s32,
        GIM_RecordInsn, /*DefineMI*/2, /*MI*/0, /*OpIdx*/2, // MIs[2]
        GIM_CheckOpcode, /*MI*/2, GIMT_Encode2(TargetOpcode::G_FMAXNUM),
        GIM_CheckType, /*MI*/2, /*Op*/1, /*Type*/GILLT_s32,
        GIM_CheckType, /*MI*/2, /*Op*/2, /*Type*/GILLT_s32,
        GIM_RecordInsn, /*DefineMI*/3, /*MI*/2, /*OpIdx*/1, // MIs[3]
        GIM_CheckOpcode, /*MI*/3, GIMT_Encode2(TargetOpcode::G_FMINNUM),
        // MIs[3] VOP3Mods:src1:src1_mods
        GIM_CheckIsSameOperand, /*MI*/3, /*OpIdx*/1, /*OtherMI*/1, /*OtherOpIdx*/1,
        // MIs[3] VOP3Mods:src0:src0_mods
        GIM_CheckIsSameOperand, /*MI*/3, /*OpIdx*/2, /*OtherMI*/1, /*OtherOpIdx*/2,
        GIM_CheckCxxInsnPredicate, /*MI*/0, /*FnId*/GIMT_Encode2(GICXXPred_MI_Predicate_fminnum_like_nnan),
        GIM_CheckIsSafeToFold, /*InsnID*/1,
        GIM_CheckIsSafeToFold, /*InsnID*/2,
        GIM_CheckIsSafeToFold, /*InsnID*/3,
        GIM_CheckComplexPattern, /*MI*/1, /*Op*/1, /*Renderer*/GIMT_Encode2(0), GIMT_Encode2(GICP_gi_vop3mods),
        GIM_CheckComplexPattern, /*MI*/1, /*Op*/2, /*Renderer*/GIMT_Encode2(1), GIMT_Encode2(GICP_gi_vop3mods),
        GIM_CheckComplexPattern, /*MI*/2, /*Op*/2, /*Renderer*/GIMT_Encode2(2), GIMT_Encode2(GICP_gi_vop3mods),
        // (fminnum_ieee:{ *:[f32] } (fmaxnum_ieee:{ *:[f32] } (VOP3Mods:{ *:[f32] } f32:{ *:[f32] }:$src1, i32:{ *:[i32] }:$src1_mods), (VOP3Mods:{ *:[f32] } f32:{ *:[f32] }:$src0, i32:{ *:[i32] }:$src0_mods)), (fmaxnum:{ *:[f32] } (fminnum:{ *:[f32] } (VOP3Mods:{ *:[f32] } f32:{ *:[f32] }:$src1, i32:{ *:[i32] }:$src1_mods), (VOP3Mods:{ *:[f32] } f32:{ *:[f32] }:$src0, i32:{ *:[i32] }:$src0_mods)), (VOP3Mods:{ *:[f32] } f32:{ *:[f32] }:$src2, i32:{ *:[i32] }:$src2_mods)))<<P:Predicate_fminnum_like_nnan>>  =>  (V_MED3_F32_e64:{ *:[f32] } ?:{ *:[i32] }:$src0_mods, ?:{ *:[f32] }:$src0, ?:{ *:[i32] }:$src1_mods, ?:{ *:[f32] }:$src1, ?:{ *:[i32] }:$src2_mods, ?:{ *:[f32] }:$src2, 0:{ *:[i1] }, 0:{ *:[i32] })
        GIR_BuildMI, /*InsnID*/0, /*Opcode*/GIMT_Encode2(AMDGPU::V_MED3_F32_e64),
        GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/0, // DstI[vdst]
        GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(1), /*SubOperand*/1, // src0_mods
        GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(1), /*SubOperand*/0, // src0
        GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/1, // src1_mods
        GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/0, // src1
        GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(2), /*SubOperand*/1, // src2_mods
        GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(2), /*SubOperand*/0, // src2
        GIR_AddImm8, /*InsnID*/0, /*Imm*/0,
        GIR_AddImm8, /*InsnID*/0, /*Imm*/0,
        GIR_ConstrainSelectedInstOperands, /*InsnID*/0,
        GIR_EraseFromParent, /*InsnID*/0,
        // GIR_Coverage, 10289,
        GIR_Done,
      // Label 4846: @338157
      GIM_Try, /*On fail goto*//*Label 4847*/ GIMT_Encode4(338297), // Rule ID 6500 //
        GIM_CheckRegBankForClass, /*MI*/0, /*Op*/0, /*RC*/GIMT_Encode2(AMDGPU::VGPR_32RegClassID),
        GIM_RecordInsn, /*DefineMI*/1, /*MI*/0, /*OpIdx*/1, // MIs[1]
        GIM_CheckOpcode, /*MI*/1, GIMT_Encode2(TargetOpcode::G_FMAXNUM_IEEE),
        GIM_CheckType, /*MI*/1, /*Op*/1, /*Type*/GILLT_s32,
        GIM_CheckType, /*MI*/1, /*Op*/2, /*Type*/GILLT_s32,
        GIM_RecordInsn, /*DefineMI*/2, /*MI*/0, /*OpIdx*/2, // MIs[2]
        GIM_CheckOpcode, /*MI*/2, GIMT_Encode2(TargetOpcode::G_FMAXNUM),
        GIM_CheckType, /*MI*/2, /*Op*/1, /*Type*/GILLT_s32,
        GIM_CheckType, /*MI*/2, /*Op*/2, /*Type*/GILLT_s32,
        GIM_RecordInsn, /*DefineMI*/3, /*MI*/2, /*OpIdx*/1, // MIs[3]
        GIM_CheckOpcode, /*MI*/3, GIMT_Encode2(TargetOpcode::G_FMINNUM_IEEE),
        // MIs[3] VOP3Mods:src0:src0_mods
        GIM_CheckIsSameOperand, /*MI*/3, /*OpIdx*/1, /*OtherMI*/1, /*OtherOpIdx*/1,
        // MIs[3] VOP3Mods:src1:src1_mods
        GIM_CheckIsSameOperand, /*MI*/3, /*OpIdx*/2, /*OtherMI*/1, /*OtherOpIdx*/2,
        GIM_CheckCxxInsnPredicate, /*MI*/0, /*FnId*/GIMT_Encode2(GICXXPred_MI_Predicate_fminnum_like_nnan),
        GIM_CheckIsSafeToFold, /*InsnID*/1,
        GIM_CheckIsSafeToFold, /*InsnID*/2,
        GIM_CheckIsSafeToFold, /*InsnID*/3,
        GIM_CheckComplexPattern, /*MI*/1, /*Op*/1, /*Renderer*/GIMT_Encode2(0), GIMT_Encode2(GICP_gi_vop3mods),
        GIM_CheckComplexPattern, /*MI*/1, /*Op*/2, /*Renderer*/GIMT_Encode2(1), GIMT_Encode2(GICP_gi_vop3mods),
        GIM_CheckComplexPattern, /*MI*/2, /*Op*/2, /*Renderer*/GIMT_Encode2(2), GIMT_Encode2(GICP_gi_vop3mods),
        // (fminnum_ieee:{ *:[f32] } (fmaxnum_ieee:{ *:[f32] } (VOP3Mods:{ *:[f32] } f32:{ *:[f32] }:$src0, i32:{ *:[i32] }:$src0_mods), (VOP3Mods:{ *:[f32] } f32:{ *:[f32] }:$src1, i32:{ *:[i32] }:$src1_mods)), (fmaxnum:{ *:[f32] } (fminnum_ieee:{ *:[f32] } (VOP3Mods:{ *:[f32] } f32:{ *:[f32] }:$src0, i32:{ *:[i32] }:$src0_mods), (VOP3Mods:{ *:[f32] } f32:{ *:[f32] }:$src1, i32:{ *:[i32] }:$src1_mods)), (VOP3Mods:{ *:[f32] } f32:{ *:[f32] }:$src2, i32:{ *:[i32] }:$src2_mods)))<<P:Predicate_fminnum_like_nnan>>  =>  (V_MED3_F32_e64:{ *:[f32] } ?:{ *:[i32] }:$src0_mods, ?:{ *:[f32] }:$src0, ?:{ *:[i32] }:$src1_mods, ?:{ *:[f32] }:$src1, ?:{ *:[i32] }:$src2_mods, ?:{ *:[f32] }:$src2, 0:{ *:[i1] }, 0:{ *:[i32] })
        GIR_BuildMI, /*InsnID*/0, /*Opcode*/GIMT_Encode2(AMDGPU::V_MED3_F32_e64),
        GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/0, // DstI[vdst]
        GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/1, // src0_mods
        GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/0, // src0
        GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(1), /*SubOperand*/1, // src1_mods
        GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(1), /*SubOperand*/0, // src1
        GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(2), /*SubOperand*/1, // src2_mods
        GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(2), /*SubOperand*/0, // src2
        GIR_AddImm8, /*InsnID*/0, /*Imm*/0,
        GIR_AddImm8, /*InsnID*/0, /*Imm*/0,
        GIR_ConstrainSelectedInstOperands, /*InsnID*/0,
        GIR_EraseFromParent, /*InsnID*/0,
        // GIR_Coverage, 6500,
        GIR_Done,
      // Label 4847: @338297
      GIM_Try, /*On fail goto*//*Label 4848*/ GIMT_Encode4(338437), // Rule ID 10270 //
        GIM_CheckRegBankForClass, /*MI*/0, /*Op*/0, /*RC*/GIMT_Encode2(AMDGPU::VGPR_32RegClassID),
        GIM_RecordInsn, /*DefineMI*/1, /*MI*/0, /*OpIdx*/1, // MIs[1]
        GIM_CheckOpcode, /*MI*/1, GIMT_Encode2(TargetOpcode::G_FMAXNUM_IEEE),
        GIM_CheckType, /*MI*/1, /*Op*/1, /*Type*/GILLT_s32,
        GIM_CheckType, /*MI*/1, /*Op*/2, /*Type*/GILLT_s32,
        GIM_RecordInsn, /*DefineMI*/2, /*MI*/0, /*OpIdx*/2, // MIs[2]
        GIM_CheckOpcode, /*MI*/2, GIMT_Encode2(TargetOpcode::G_FMAXNUM),
        GIM_CheckType, /*MI*/2, /*Op*/1, /*Type*/GILLT_s32,
        GIM_CheckType, /*MI*/2, /*Op*/2, /*Type*/GILLT_s32,
        GIM_RecordInsn, /*DefineMI*/3, /*MI*/2, /*OpIdx*/1, // MIs[3]
        GIM_CheckOpcode, /*MI*/3, GIMT_Encode2(TargetOpcode::G_FMINNUM_IEEE),
        // MIs[3] VOP3Mods:src1:src1_mods
        GIM_CheckIsSameOperand, /*MI*/3, /*OpIdx*/1, /*OtherMI*/1, /*OtherOpIdx*/2,
        // MIs[3] VOP3Mods:src0:src0_mods
        GIM_CheckIsSameOperand, /*MI*/3, /*OpIdx*/2, /*OtherMI*/1, /*OtherOpIdx*/1,
        GIM_CheckCxxInsnPredicate, /*MI*/0, /*FnId*/GIMT_Encode2(GICXXPred_MI_Predicate_fminnum_like_nnan),
        GIM_CheckIsSafeToFold, /*InsnID*/1,
        GIM_CheckIsSafeToFold, /*InsnID*/2,
        GIM_CheckIsSafeToFold, /*InsnID*/3,
        GIM_CheckComplexPattern, /*MI*/1, /*Op*/1, /*Renderer*/GIMT_Encode2(0), GIMT_Encode2(GICP_gi_vop3mods),
        GIM_CheckComplexPattern, /*MI*/1, /*Op*/2, /*Renderer*/GIMT_Encode2(1), GIMT_Encode2(GICP_gi_vop3mods),
        GIM_CheckComplexPattern, /*MI*/2, /*Op*/2, /*Renderer*/GIMT_Encode2(2), GIMT_Encode2(GICP_gi_vop3mods),
        // (fminnum_ieee:{ *:[f32] } (fmaxnum_ieee:{ *:[f32] } (VOP3Mods:{ *:[f32] } f32:{ *:[f32] }:$src0, i32:{ *:[i32] }:$src0_mods), (VOP3Mods:{ *:[f32] } f32:{ *:[f32] }:$src1, i32:{ *:[i32] }:$src1_mods)), (fmaxnum:{ *:[f32] } (fminnum_ieee:{ *:[f32] } (VOP3Mods:{ *:[f32] } f32:{ *:[f32] }:$src1, i32:{ *:[i32] }:$src1_mods), (VOP3Mods:{ *:[f32] } f32:{ *:[f32] }:$src0, i32:{ *:[i32] }:$src0_mods)), (VOP3Mods:{ *:[f32] } f32:{ *:[f32] }:$src2, i32:{ *:[i32] }:$src2_mods)))<<P:Predicate_fminnum_like_nnan>>  =>  (V_MED3_F32_e64:{ *:[f32] } ?:{ *:[i32] }:$src0_mods, ?:{ *:[f32] }:$src0, ?:{ *:[i32] }:$src1_mods, ?:{ *:[f32] }:$src1, ?:{ *:[i32] }:$src2_mods, ?:{ *:[f32] }:$src2, 0:{ *:[i1] }, 0:{ *:[i32] })
        GIR_BuildMI, /*InsnID*/0, /*Opcode*/GIMT_Encode2(AMDGPU::V_MED3_F32_e64),
        GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/0, // DstI[vdst]
        GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/1, // src0_mods
        GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/0, // src0
        GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(1), /*SubOperand*/1, // src1_mods
        GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(1), /*SubOperand*/0, // src1
        GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(2), /*SubOperand*/1, // src2_mods
        GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(2), /*SubOperand*/0, // src2
        GIR_AddImm8, /*InsnID*/0, /*Imm*/0,
        GIR_AddImm8, /*InsnID*/0, /*Imm*/0,
        GIR_ConstrainSelectedInstOperands, /*InsnID*/0,
        GIR_EraseFromParent, /*InsnID*/0,
        // GIR_Coverage, 10270,
        GIR_Done,
      // Label 4848: @338437
      GIM_Try, /*On fail goto*//*Label 4849*/ GIMT_Encode4(338577), // Rule ID 10273 //
        GIM_CheckRegBankForClass, /*MI*/0, /*Op*/0, /*RC*/GIMT_Encode2(AMDGPU::VGPR_32RegClassID),
        GIM_RecordInsn, /*DefineMI*/1, /*MI*/0, /*OpIdx*/1, // MIs[1]
        GIM_CheckOpcode, /*MI*/1, GIMT_Encode2(TargetOpcode::G_FMAXNUM_IEEE),
        GIM_CheckType, /*MI*/1, /*Op*/1, /*Type*/GILLT_s32,
        GIM_CheckType, /*MI*/1, /*Op*/2, /*Type*/GILLT_s32,
        GIM_RecordInsn, /*DefineMI*/2, /*MI*/0, /*OpIdx*/2, // MIs[2]
        GIM_CheckOpcode, /*MI*/2, GIMT_Encode2(TargetOpcode::G_FMAXNUM),
        GIM_CheckType, /*MI*/2, /*Op*/1, /*Type*/GILLT_s32,
        GIM_CheckType, /*MI*/2, /*Op*/2, /*Type*/GILLT_s32,
        GIM_RecordInsn, /*DefineMI*/3, /*MI*/2, /*OpIdx*/1, // MIs[3]
        GIM_CheckOpcode, /*MI*/3, GIMT_Encode2(TargetOpcode::G_FMINNUM_IEEE),
        // MIs[3] VOP3Mods:src0:src0_mods
        GIM_CheckIsSameOperand, /*MI*/3, /*OpIdx*/1, /*OtherMI*/1, /*OtherOpIdx*/2,
        // MIs[3] VOP3Mods:src1:src1_mods
        GIM_CheckIsSameOperand, /*MI*/3, /*OpIdx*/2, /*OtherMI*/1, /*OtherOpIdx*/1,
        GIM_CheckCxxInsnPredicate, /*MI*/0, /*FnId*/GIMT_Encode2(GICXXPred_MI_Predicate_fminnum_like_nnan),
        GIM_CheckIsSafeToFold, /*InsnID*/1,
        GIM_CheckIsSafeToFold, /*InsnID*/2,
        GIM_CheckIsSafeToFold, /*InsnID*/3,
        GIM_CheckComplexPattern, /*MI*/1, /*Op*/1, /*Renderer*/GIMT_Encode2(0), GIMT_Encode2(GICP_gi_vop3mods),
        GIM_CheckComplexPattern, /*MI*/1, /*Op*/2, /*Renderer*/GIMT_Encode2(1), GIMT_Encode2(GICP_gi_vop3mods),
        GIM_CheckComplexPattern, /*MI*/2, /*Op*/2, /*Renderer*/GIMT_Encode2(2), GIMT_Encode2(GICP_gi_vop3mods),
        // (fminnum_ieee:{ *:[f32] } (fmaxnum_ieee:{ *:[f32] } (VOP3Mods:{ *:[f32] } f32:{ *:[f32] }:$src1, i32:{ *:[i32] }:$src1_mods), (VOP3Mods:{ *:[f32] } f32:{ *:[f32] }:$src0, i32:{ *:[i32] }:$src0_mods)), (fmaxnum:{ *:[f32] } (fminnum_ieee:{ *:[f32] } (VOP3Mods:{ *:[f32] } f32:{ *:[f32] }:$src0, i32:{ *:[i32] }:$src0_mods), (VOP3Mods:{ *:[f32] } f32:{ *:[f32] }:$src1, i32:{ *:[i32] }:$src1_mods)), (VOP3Mods:{ *:[f32] } f32:{ *:[f32] }:$src2, i32:{ *:[i32] }:$src2_mods)))<<P:Predicate_fminnum_like_nnan>>  =>  (V_MED3_F32_e64:{ *:[f32] } ?:{ *:[i32] }:$src0_mods, ?:{ *:[f32] }:$src0, ?:{ *:[i32] }:$src1_mods, ?:{ *:[f32] }:$src1, ?:{ *:[i32] }:$src2_mods, ?:{ *:[f32] }:$src2, 0:{ *:[i1] }, 0:{ *:[i32] })
        GIR_BuildMI, /*InsnID*/0, /*Opcode*/GIMT_Encode2(AMDGPU::V_MED3_F32_e64),
        GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/0, // DstI[vdst]
        GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(1), /*SubOperand*/1, // src0_mods
        GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(1), /*SubOperand*/0, // src0
        GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/1, // src1_mods
        GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/0, // src1
        GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(2), /*SubOperand*/1, // src2_mods
        GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(2), /*SubOperand*/0, // src2
        GIR_AddImm8, /*InsnID*/0, /*Imm*/0,
        GIR_AddImm8, /*InsnID*/0, /*Imm*/0,
        GIR_ConstrainSelectedInstOperands, /*InsnID*/0,
        GIR_EraseFromParent, /*InsnID*/0,
        // GIR_Coverage, 10273,
        GIR_Done,
      // Label 4849: @338577
      GIM_Try, /*On fail goto*//*Label 4850*/ GIMT_Encode4(338717), // Rule ID 10274 //
        GIM_CheckRegBankForClass, /*MI*/0, /*Op*/0, /*RC*/GIMT_Encode2(AMDGPU::VGPR_32RegClassID),
        GIM_RecordInsn, /*DefineMI*/1, /*MI*/0, /*OpIdx*/1, // MIs[1]
        GIM_CheckOpcode, /*MI*/1, GIMT_Encode2(TargetOpcode::G_FMAXNUM_IEEE),
        GIM_CheckType, /*MI*/1, /*Op*/1, /*Type*/GILLT_s32,
        GIM_CheckType, /*MI*/1, /*Op*/2, /*Type*/GILLT_s32,
        GIM_RecordInsn, /*DefineMI*/2, /*MI*/0, /*OpIdx*/2, // MIs[2]
        GIM_CheckOpcode, /*MI*/2, GIMT_Encode2(TargetOpcode::G_FMAXNUM),
        GIM_CheckType, /*MI*/2, /*Op*/1, /*Type*/GILLT_s32,
        GIM_CheckType, /*MI*/2, /*Op*/2, /*Type*/GILLT_s32,
        GIM_RecordInsn, /*DefineMI*/3, /*MI*/2, /*OpIdx*/1, // MIs[3]
        GIM_CheckOpcode, /*MI*/3, GIMT_Encode2(TargetOpcode::G_FMINNUM_IEEE),
        // MIs[3] VOP3Mods:src1:src1_mods
        GIM_CheckIsSameOperand, /*MI*/3, /*OpIdx*/1, /*OtherMI*/1, /*OtherOpIdx*/1,
        // MIs[3] VOP3Mods:src0:src0_mods
        GIM_CheckIsSameOperand, /*MI*/3, /*OpIdx*/2, /*OtherMI*/1, /*OtherOpIdx*/2,
        GIM_CheckCxxInsnPredicate, /*MI*/0, /*FnId*/GIMT_Encode2(GICXXPred_MI_Predicate_fminnum_like_nnan),
        GIM_CheckIsSafeToFold, /*InsnID*/1,
        GIM_CheckIsSafeToFold, /*InsnID*/2,
        GIM_CheckIsSafeToFold, /*InsnID*/3,
        GIM_CheckComplexPattern, /*MI*/1, /*Op*/1, /*Renderer*/GIMT_Encode2(0), GIMT_Encode2(GICP_gi_vop3mods),
        GIM_CheckComplexPattern, /*MI*/1, /*Op*/2, /*Renderer*/GIMT_Encode2(1), GIMT_Encode2(GICP_gi_vop3mods),
        GIM_CheckComplexPattern, /*MI*/2, /*Op*/2, /*Renderer*/GIMT_Encode2(2), GIMT_Encode2(GICP_gi_vop3mods),
        // (fminnum_ieee:{ *:[f32] } (fmaxnum_ieee:{ *:[f32] } (VOP3Mods:{ *:[f32] } f32:{ *:[f32] }:$src1, i32:{ *:[i32] }:$src1_mods), (VOP3Mods:{ *:[f32] } f32:{ *:[f32] }:$src0, i32:{ *:[i32] }:$src0_mods)), (fmaxnum:{ *:[f32] } (fminnum_ieee:{ *:[f32] } (VOP3Mods:{ *:[f32] } f32:{ *:[f32] }:$src1, i32:{ *:[i32] }:$src1_mods), (VOP3Mods:{ *:[f32] } f32:{ *:[f32] }:$src0, i32:{ *:[i32] }:$src0_mods)), (VOP3Mods:{ *:[f32] } f32:{ *:[f32] }:$src2, i32:{ *:[i32] }:$src2_mods)))<<P:Predicate_fminnum_like_nnan>>  =>  (V_MED3_F32_e64:{ *:[f32] } ?:{ *:[i32] }:$src0_mods, ?:{ *:[f32] }:$src0, ?:{ *:[i32] }:$src1_mods, ?:{ *:[f32] }:$src1, ?:{ *:[i32] }:$src2_mods, ?:{ *:[f32] }:$src2, 0:{ *:[i1] }, 0:{ *:[i32] })
        GIR_BuildMI, /*InsnID*/0, /*Opcode*/GIMT_Encode2(AMDGPU::V_MED3_F32_e64),
        GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/0, // DstI[vdst]
        GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(1), /*SubOperand*/1, // src0_mods
        GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(1), /*SubOperand*/0, // src0
        GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/1, // src1_mods
        GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/0, // src1
        GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(2), /*SubOperand*/1, // src2_mods
        GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(2), /*SubOperand*/0, // src2
        GIR_AddImm8, /*InsnID*/0, /*Imm*/0,
        GIR_AddImm8, /*InsnID*/0, /*Imm*/0,
        GIR_ConstrainSelectedInstOperands, /*InsnID*/0,
        GIR_EraseFromParent, /*InsnID*/0,
        // GIR_Coverage, 10274,
        GIR_Done,
      // Label 4850: @338717
      GIM_Try, /*On fail goto*//*Label 4851*/ GIMT_Encode4(338857), // Rule ID 10256 //
        GIM_CheckRegBankForClass, /*MI*/0, /*Op*/0, /*RC*/GIMT_Encode2(AMDGPU::VGPR_32RegClassID),
        GIM_RecordInsn, /*DefineMI*/1, /*MI*/0, /*OpIdx*/1, // MIs[1]
        GIM_CheckOpcode, /*MI*/1, GIMT_Encode2(TargetOpcode::G_FMAXNUM_IEEE),
        GIM_CheckType, /*MI*/1, /*Op*/1, /*Type*/GILLT_s32,
        GIM_CheckType, /*MI*/1, /*Op*/2, /*Type*/GILLT_s32,
        GIM_RecordInsn, /*DefineMI*/2, /*MI*/0, /*OpIdx*/2, // MIs[2]
        GIM_CheckOpcode, /*MI*/2, GIMT_Encode2(TargetOpcode::G_FMAXNUM_IEEE),
        GIM_CheckType, /*MI*/2, /*Op*/1, /*Type*/GILLT_s32,
        GIM_CheckType, /*MI*/2, /*Op*/2, /*Type*/GILLT_s32,
        GIM_RecordInsn, /*DefineMI*/3, /*MI*/2, /*OpIdx*/2, // MIs[3]
        GIM_CheckOpcode, /*MI*/3, GIMT_Encode2(TargetOpcode::G_FMINNUM),
        // MIs[3] VOP3Mods:src0:src0_mods
        GIM_CheckIsSameOperand, /*MI*/3, /*OpIdx*/1, /*OtherMI*/1, /*OtherOpIdx*/1,
        // MIs[3] VOP3Mods:src1:src1_mods
        GIM_CheckIsSameOperand, /*MI*/3, /*OpIdx*/2, /*OtherMI*/1, /*OtherOpIdx*/2,
        GIM_CheckCxxInsnPredicate, /*MI*/0, /*FnId*/GIMT_Encode2(GICXXPred_MI_Predicate_fminnum_like_nnan),
        GIM_CheckIsSafeToFold, /*InsnID*/1,
        GIM_CheckIsSafeToFold, /*InsnID*/2,
        GIM_CheckIsSafeToFold, /*InsnID*/3,
        GIM_CheckComplexPattern, /*MI*/1, /*Op*/1, /*Renderer*/GIMT_Encode2(0), GIMT_Encode2(GICP_gi_vop3mods),
        GIM_CheckComplexPattern, /*MI*/1, /*Op*/2, /*Renderer*/GIMT_Encode2(1), GIMT_Encode2(GICP_gi_vop3mods),
        GIM_CheckComplexPattern, /*MI*/2, /*Op*/1, /*Renderer*/GIMT_Encode2(2), GIMT_Encode2(GICP_gi_vop3mods),
        // (fminnum_ieee:{ *:[f32] } (fmaxnum_ieee:{ *:[f32] } (VOP3Mods:{ *:[f32] } f32:{ *:[f32] }:$src0, i32:{ *:[i32] }:$src0_mods), (VOP3Mods:{ *:[f32] } f32:{ *:[f32] }:$src1, i32:{ *:[i32] }:$src1_mods)), (fmaxnum_ieee:{ *:[f32] } (VOP3Mods:{ *:[f32] } f32:{ *:[f32] }:$src2, i32:{ *:[i32] }:$src2_mods), (fminnum:{ *:[f32] } (VOP3Mods:{ *:[f32] } f32:{ *:[f32] }:$src0, i32:{ *:[i32] }:$src0_mods), (VOP3Mods:{ *:[f32] } f32:{ *:[f32] }:$src1, i32:{ *:[i32] }:$src1_mods))))<<P:Predicate_fminnum_like_nnan>>  =>  (V_MED3_F32_e64:{ *:[f32] } ?:{ *:[i32] }:$src0_mods, ?:{ *:[f32] }:$src0, ?:{ *:[i32] }:$src1_mods, ?:{ *:[f32] }:$src1, ?:{ *:[i32] }:$src2_mods, ?:{ *:[f32] }:$src2, 0:{ *:[i1] }, 0:{ *:[i32] })
        GIR_BuildMI, /*InsnID*/0, /*Opcode*/GIMT_Encode2(AMDGPU::V_MED3_F32_e64),
        GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/0, // DstI[vdst]
        GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/1, // src0_mods
        GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/0, // src0
        GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(1), /*SubOperand*/1, // src1_mods
        GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(1), /*SubOperand*/0, // src1
        GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(2), /*SubOperand*/1, // src2_mods
        GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(2), /*SubOperand*/0, // src2
        GIR_AddImm8, /*InsnID*/0, /*Imm*/0,
        GIR_AddImm8, /*InsnID*/0, /*Imm*/0,
        GIR_ConstrainSelectedInstOperands, /*InsnID*/0,
        GIR_EraseFromParent, /*InsnID*/0,
        // GIR_Coverage, 10256,
        GIR_Done,
      // Label 4851: @338857
      GIM_Try, /*On fail goto*//*Label 4852*/ GIMT_Encode4(338997), // Rule ID 10257 //
        GIM_CheckRegBankForClass, /*MI*/0, /*Op*/0, /*RC*/GIMT_Encode2(AMDGPU::VGPR_32RegClassID),
        GIM_RecordInsn, /*DefineMI*/1, /*MI*/0, /*OpIdx*/1, // MIs[1]
        GIM_CheckOpcode, /*MI*/1, GIMT_Encode2(TargetOpcode::G_FMAXNUM_IEEE),
        GIM_CheckType, /*MI*/1, /*Op*/1, /*Type*/GILLT_s32,
        GIM_CheckType, /*MI*/1, /*Op*/2, /*Type*/GILLT_s32,
        GIM_RecordInsn, /*DefineMI*/2, /*MI*/0, /*OpIdx*/2, // MIs[2]
        GIM_CheckOpcode, /*MI*/2, GIMT_Encode2(TargetOpcode::G_FMAXNUM_IEEE),
        GIM_CheckType, /*MI*/2, /*Op*/1, /*Type*/GILLT_s32,
        GIM_CheckType, /*MI*/2, /*Op*/2, /*Type*/GILLT_s32,
        GIM_RecordInsn, /*DefineMI*/3, /*MI*/2, /*OpIdx*/2, // MIs[3]
        GIM_CheckOpcode, /*MI*/3, GIMT_Encode2(TargetOpcode::G_FMINNUM),
        // MIs[3] VOP3Mods:src1:src1_mods
        GIM_CheckIsSameOperand, /*MI*/3, /*OpIdx*/1, /*OtherMI*/1, /*OtherOpIdx*/2,
        // MIs[3] VOP3Mods:src0:src0_mods
        GIM_CheckIsSameOperand, /*MI*/3, /*OpIdx*/2, /*OtherMI*/1, /*OtherOpIdx*/1,
        GIM_CheckCxxInsnPredicate, /*MI*/0, /*FnId*/GIMT_Encode2(GICXXPred_MI_Predicate_fminnum_like_nnan),
        GIM_CheckIsSafeToFold, /*InsnID*/1,
        GIM_CheckIsSafeToFold, /*InsnID*/2,
        GIM_CheckIsSafeToFold, /*InsnID*/3,
        GIM_CheckComplexPattern, /*MI*/1, /*Op*/1, /*Renderer*/GIMT_Encode2(0), GIMT_Encode2(GICP_gi_vop3mods),
        GIM_CheckComplexPattern, /*MI*/1, /*Op*/2, /*Renderer*/GIMT_Encode2(1), GIMT_Encode2(GICP_gi_vop3mods),
        GIM_CheckComplexPattern, /*MI*/2, /*Op*/1, /*Renderer*/GIMT_Encode2(2), GIMT_Encode2(GICP_gi_vop3mods),
        // (fminnum_ieee:{ *:[f32] } (fmaxnum_ieee:{ *:[f32] } (VOP3Mods:{ *:[f32] } f32:{ *:[f32] }:$src0, i32:{ *:[i32] }:$src0_mods), (VOP3Mods:{ *:[f32] } f32:{ *:[f32] }:$src1, i32:{ *:[i32] }:$src1_mods)), (fmaxnum_ieee:{ *:[f32] } (VOP3Mods:{ *:[f32] } f32:{ *:[f32] }:$src2, i32:{ *:[i32] }:$src2_mods), (fminnum:{ *:[f32] } (VOP3Mods:{ *:[f32] } f32:{ *:[f32] }:$src1, i32:{ *:[i32] }:$src1_mods), (VOP3Mods:{ *:[f32] } f32:{ *:[f32] }:$src0, i32:{ *:[i32] }:$src0_mods))))<<P:Predicate_fminnum_like_nnan>>  =>  (V_MED3_F32_e64:{ *:[f32] } ?:{ *:[i32] }:$src0_mods, ?:{ *:[f32] }:$src0, ?:{ *:[i32] }:$src1_mods, ?:{ *:[f32] }:$src1, ?:{ *:[i32] }:$src2_mods, ?:{ *:[f32] }:$src2, 0:{ *:[i1] }, 0:{ *:[i32] })
        GIR_BuildMI, /*InsnID*/0, /*Opcode*/GIMT_Encode2(AMDGPU::V_MED3_F32_e64),
        GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/0, // DstI[vdst]
        GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/1, // src0_mods
        GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/0, // src0
        GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(1), /*SubOperand*/1, // src1_mods
        GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(1), /*SubOperand*/0, // src1
        GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(2), /*SubOperand*/1, // src2_mods
        GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(2), /*SubOperand*/0, // src2
        GIR_AddImm8, /*InsnID*/0, /*Imm*/0,
        GIR_AddImm8, /*InsnID*/0, /*Imm*/0,
        GIR_ConstrainSelectedInstOperands, /*InsnID*/0,
        GIR_EraseFromParent, /*InsnID*/0,
        // GIR_Coverage, 10257,
        GIR_Done,
      // Label 4852: @338997
      GIM_Try, /*On fail goto*//*Label 4853*/ GIMT_Encode4(339137), // Rule ID 10260 //
        GIM_CheckRegBankForClass, /*MI*/0, /*Op*/0, /*RC*/GIMT_Encode2(AMDGPU::VGPR_32RegClassID),
        GIM_RecordInsn, /*DefineMI*/1, /*MI*/0, /*OpIdx*/1, // MIs[1]
        GIM_CheckOpcode, /*MI*/1, GIMT_Encode2(TargetOpcode::G_FMAXNUM_IEEE),
        GIM_CheckType, /*MI*/1, /*Op*/1, /*Type*/GILLT_s32,
        GIM_CheckType, /*MI*/1, /*Op*/2, /*Type*/GILLT_s32,
        GIM_RecordInsn, /*DefineMI*/2, /*MI*/0, /*OpIdx*/2, // MIs[2]
        GIM_CheckOpcode, /*MI*/2, GIMT_Encode2(TargetOpcode::G_FMAXNUM_IEEE),
        GIM_CheckType, /*MI*/2, /*Op*/1, /*Type*/GILLT_s32,
        GIM_CheckType, /*MI*/2, /*Op*/2, /*Type*/GILLT_s32,
        GIM_RecordInsn, /*DefineMI*/3, /*MI*/2, /*OpIdx*/2, // MIs[3]
        GIM_CheckOpcode, /*MI*/3, GIMT_Encode2(TargetOpcode::G_FMINNUM),
        // MIs[3] VOP3Mods:src0:src0_mods
        GIM_CheckIsSameOperand, /*MI*/3, /*OpIdx*/1, /*OtherMI*/1, /*OtherOpIdx*/2,
        // MIs[3] VOP3Mods:src1:src1_mods
        GIM_CheckIsSameOperand, /*MI*/3, /*OpIdx*/2, /*OtherMI*/1, /*OtherOpIdx*/1,
        GIM_CheckCxxInsnPredicate, /*MI*/0, /*FnId*/GIMT_Encode2(GICXXPred_MI_Predicate_fminnum_like_nnan),
        GIM_CheckIsSafeToFold, /*InsnID*/1,
        GIM_CheckIsSafeToFold, /*InsnID*/2,
        GIM_CheckIsSafeToFold, /*InsnID*/3,
        GIM_CheckComplexPattern, /*MI*/1, /*Op*/1, /*Renderer*/GIMT_Encode2(0), GIMT_Encode2(GICP_gi_vop3mods),
        GIM_CheckComplexPattern, /*MI*/1, /*Op*/2, /*Renderer*/GIMT_Encode2(1), GIMT_Encode2(GICP_gi_vop3mods),
        GIM_CheckComplexPattern, /*MI*/2, /*Op*/1, /*Renderer*/GIMT_Encode2(2), GIMT_Encode2(GICP_gi_vop3mods),
        // (fminnum_ieee:{ *:[f32] } (fmaxnum_ieee:{ *:[f32] } (VOP3Mods:{ *:[f32] } f32:{ *:[f32] }:$src1, i32:{ *:[i32] }:$src1_mods), (VOP3Mods:{ *:[f32] } f32:{ *:[f32] }:$src0, i32:{ *:[i32] }:$src0_mods)), (fmaxnum_ieee:{ *:[f32] } (VOP3Mods:{ *:[f32] } f32:{ *:[f32] }:$src2, i32:{ *:[i32] }:$src2_mods), (fminnum:{ *:[f32] } (VOP3Mods:{ *:[f32] } f32:{ *:[f32] }:$src0, i32:{ *:[i32] }:$src0_mods), (VOP3Mods:{ *:[f32] } f32:{ *:[f32] }:$src1, i32:{ *:[i32] }:$src1_mods))))<<P:Predicate_fminnum_like_nnan>>  =>  (V_MED3_F32_e64:{ *:[f32] } ?:{ *:[i32] }:$src0_mods, ?:{ *:[f32] }:$src0, ?:{ *:[i32] }:$src1_mods, ?:{ *:[f32] }:$src1, ?:{ *:[i32] }:$src2_mods, ?:{ *:[f32] }:$src2, 0:{ *:[i1] }, 0:{ *:[i32] })
        GIR_BuildMI, /*InsnID*/0, /*Opcode*/GIMT_Encode2(AMDGPU::V_MED3_F32_e64),
        GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/0, // DstI[vdst]
        GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(1), /*SubOperand*/1, // src0_mods
        GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(1), /*SubOperand*/0, // src0
        GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/1, // src1_mods
        GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/0, // src1
        GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(2), /*SubOperand*/1, // src2_mods
        GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(2), /*SubOperand*/0, // src2
        GIR_AddImm8, /*InsnID*/0, /*Imm*/0,
        GIR_AddImm8, /*InsnID*/0, /*Imm*/0,
        GIR_ConstrainSelectedInstOperands, /*InsnID*/0,
        GIR_EraseFromParent, /*InsnID*/0,
        // GIR_Coverage, 10260,
        GIR_Done,
      // Label 4853: @339137
      GIM_Try, /*On fail goto*//*Label 4854*/ GIMT_Encode4(339277), // Rule ID 10261 //
        GIM_CheckRegBankForClass, /*MI*/0, /*Op*/0, /*RC*/GIMT_Encode2(AMDGPU::VGPR_32RegClassID),
        GIM_RecordInsn, /*DefineMI*/1, /*MI*/0, /*OpIdx*/1, // MIs[1]
        GIM_CheckOpcode, /*MI*/1, GIMT_Encode2(TargetOpcode::G_FMAXNUM_IEEE),
        GIM_CheckType, /*MI*/1, /*Op*/1, /*Type*/GILLT_s32,
        GIM_CheckType, /*MI*/1, /*Op*/2, /*Type*/GILLT_s32,
        GIM_RecordInsn, /*DefineMI*/2, /*MI*/0, /*OpIdx*/2, // MIs[2]
        GIM_CheckOpcode, /*MI*/2, GIMT_Encode2(TargetOpcode::G_FMAXNUM_IEEE),
        GIM_CheckType, /*MI*/2, /*Op*/1, /*Type*/GILLT_s32,
        GIM_CheckType, /*MI*/2, /*Op*/2, /*Type*/GILLT_s32,
        GIM_RecordInsn, /*DefineMI*/3, /*MI*/2, /*OpIdx*/2, // MIs[3]
        GIM_CheckOpcode, /*MI*/3, GIMT_Encode2(TargetOpcode::G_FMINNUM),
        // MIs[3] VOP3Mods:src1:src1_mods
        GIM_CheckIsSameOperand, /*MI*/3, /*OpIdx*/1, /*OtherMI*/1, /*OtherOpIdx*/1,
        // MIs[3] VOP3Mods:src0:src0_mods
        GIM_CheckIsSameOperand, /*MI*/3, /*OpIdx*/2, /*OtherMI*/1, /*OtherOpIdx*/2,
        GIM_CheckCxxInsnPredicate, /*MI*/0, /*FnId*/GIMT_Encode2(GICXXPred_MI_Predicate_fminnum_like_nnan),
        GIM_CheckIsSafeToFold, /*InsnID*/1,
        GIM_CheckIsSafeToFold, /*InsnID*/2,
        GIM_CheckIsSafeToFold, /*InsnID*/3,
        GIM_CheckComplexPattern, /*MI*/1, /*Op*/1, /*Renderer*/GIMT_Encode2(0), GIMT_Encode2(GICP_gi_vop3mods),
        GIM_CheckComplexPattern, /*MI*/1, /*Op*/2, /*Renderer*/GIMT_Encode2(1), GIMT_Encode2(GICP_gi_vop3mods),
        GIM_CheckComplexPattern, /*MI*/2, /*Op*/1, /*Renderer*/GIMT_Encode2(2), GIMT_Encode2(GICP_gi_vop3mods),
        // (fminnum_ieee:{ *:[f32] } (fmaxnum_ieee:{ *:[f32] } (VOP3Mods:{ *:[f32] } f32:{ *:[f32] }:$src1, i32:{ *:[i32] }:$src1_mods), (VOP3Mods:{ *:[f32] } f32:{ *:[f32] }:$src0, i32:{ *:[i32] }:$src0_mods)), (fmaxnum_ieee:{ *:[f32] } (VOP3Mods:{ *:[f32] } f32:{ *:[f32] }:$src2, i32:{ *:[i32] }:$src2_mods), (fminnum:{ *:[f32] } (VOP3Mods:{ *:[f32] } f32:{ *:[f32] }:$src1, i32:{ *:[i32] }:$src1_mods), (VOP3Mods:{ *:[f32] } f32:{ *:[f32] }:$src0, i32:{ *:[i32] }:$src0_mods))))<<P:Predicate_fminnum_like_nnan>>  =>  (V_MED3_F32_e64:{ *:[f32] } ?:{ *:[i32] }:$src0_mods, ?:{ *:[f32] }:$src0, ?:{ *:[i32] }:$src1_mods, ?:{ *:[f32] }:$src1, ?:{ *:[i32] }:$src2_mods, ?:{ *:[f32] }:$src2, 0:{ *:[i1] }, 0:{ *:[i32] })
        GIR_BuildMI, /*InsnID*/0, /*Opcode*/GIMT_Encode2(AMDGPU::V_MED3_F32_e64),
        GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/0, // DstI[vdst]
        GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(1), /*SubOperand*/1, // src0_mods
        GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(1), /*SubOperand*/0, // src0
        GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/1, // src1_mods
        GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/0, // src1
        GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(2), /*SubOperand*/1, // src2_mods
        GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(2), /*SubOperand*/0, // src2
        GIR_AddImm8, /*InsnID*/0, /*Imm*/0,
        GIR_AddImm8, /*InsnID*/0, /*Imm*/0,
        GIR_ConstrainSelectedInstOperands, /*InsnID*/0,
        GIR_EraseFromParent, /*InsnID*/0,
        // GIR_Coverage, 10261,
        GIR_Done,
      // Label 4854: @339277
      GIM_Try, /*On fail goto*//*Label 4855*/ GIMT_Encode4(339417), // Rule ID 10241 //
        GIM_CheckRegBankForClass, /*MI*/0, /*Op*/0, /*RC*/GIMT_Encode2(AMDGPU::VGPR_32RegClassID),
        GIM_RecordInsn, /*DefineMI*/1, /*MI*/0, /*OpIdx*/1, // MIs[1]
        GIM_CheckOpcode, /*MI*/1, GIMT_Encode2(TargetOpcode::G_FMAXNUM_IEEE),
        GIM_CheckType, /*MI*/1, /*Op*/1, /*Type*/GILLT_s32,
        GIM_CheckType, /*MI*/1, /*Op*/2, /*Type*/GILLT_s32,
        GIM_RecordInsn, /*DefineMI*/2, /*MI*/0, /*OpIdx*/2, // MIs[2]
        GIM_CheckOpcode, /*MI*/2, GIMT_Encode2(TargetOpcode::G_FMAXNUM_IEEE),
        GIM_CheckType, /*MI*/2, /*Op*/1, /*Type*/GILLT_s32,
        GIM_CheckType, /*MI*/2, /*Op*/2, /*Type*/GILLT_s32,
        GIM_RecordInsn, /*DefineMI*/3, /*MI*/2, /*OpIdx*/2, // MIs[3]
        GIM_CheckOpcode, /*MI*/3, GIMT_Encode2(TargetOpcode::G_FMINNUM_IEEE),
        // MIs[3] VOP3Mods:src0:src0_mods
        GIM_CheckIsSameOperand, /*MI*/3, /*OpIdx*/1, /*OtherMI*/1, /*OtherOpIdx*/1,
        // MIs[3] VOP3Mods:src1:src1_mods
        GIM_CheckIsSameOperand, /*MI*/3, /*OpIdx*/2, /*OtherMI*/1, /*OtherOpIdx*/2,
        GIM_CheckCxxInsnPredicate, /*MI*/0, /*FnId*/GIMT_Encode2(GICXXPred_MI_Predicate_fminnum_like_nnan),
        GIM_CheckIsSafeToFold, /*InsnID*/1,
        GIM_CheckIsSafeToFold, /*InsnID*/2,
        GIM_CheckIsSafeToFold, /*InsnID*/3,
        GIM_CheckComplexPattern, /*MI*/1, /*Op*/1, /*Renderer*/GIMT_Encode2(0), GIMT_Encode2(GICP_gi_vop3mods),
        GIM_CheckComplexPattern, /*MI*/1, /*Op*/2, /*Renderer*/GIMT_Encode2(1), GIMT_Encode2(GICP_gi_vop3mods),
        GIM_CheckComplexPattern, /*MI*/2, /*Op*/1, /*Renderer*/GIMT_Encode2(2), GIMT_Encode2(GICP_gi_vop3mods),
        // (fminnum_ieee:{ *:[f32] } (fmaxnum_ieee:{ *:[f32] } (VOP3Mods:{ *:[f32] } f32:{ *:[f32] }:$src0, i32:{ *:[i32] }:$src0_mods), (VOP3Mods:{ *:[f32] } f32:{ *:[f32] }:$src1, i32:{ *:[i32] }:$src1_mods)), (fmaxnum_ieee:{ *:[f32] } (VOP3Mods:{ *:[f32] } f32:{ *:[f32] }:$src2, i32:{ *:[i32] }:$src2_mods), (fminnum_ieee:{ *:[f32] } (VOP3Mods:{ *:[f32] } f32:{ *:[f32] }:$src0, i32:{ *:[i32] }:$src0_mods), (VOP3Mods:{ *:[f32] } f32:{ *:[f32] }:$src1, i32:{ *:[i32] }:$src1_mods))))<<P:Predicate_fminnum_like_nnan>>  =>  (V_MED3_F32_e64:{ *:[f32] } ?:{ *:[i32] }:$src0_mods, ?:{ *:[f32] }:$src0, ?:{ *:[i32] }:$src1_mods, ?:{ *:[f32] }:$src1, ?:{ *:[i32] }:$src2_mods, ?:{ *:[f32] }:$src2, 0:{ *:[i1] }, 0:{ *:[i32] })
        GIR_BuildMI, /*InsnID*/0, /*Opcode*/GIMT_Encode2(AMDGPU::V_MED3_F32_e64),
        GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/0, // DstI[vdst]
        GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/1, // src0_mods
        GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/0, // src0
        GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(1), /*SubOperand*/1, // src1_mods
        GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(1), /*SubOperand*/0, // src1
        GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(2), /*SubOperand*/1, // src2_mods
        GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(2), /*SubOperand*/0, // src2
        GIR_AddImm8, /*InsnID*/0, /*Imm*/0,
        GIR_AddImm8, /*InsnID*/0, /*Imm*/0,
        GIR_ConstrainSelectedInstOperands, /*InsnID*/0,
        GIR_EraseFromParent, /*InsnID*/0,
        // GIR_Coverage, 10241,
        GIR_Done,
      // Label 4855: @339417
      GIM_Try, /*On fail goto*//*Label 4856*/ GIMT_Encode4(339557), // Rule ID 10242 //
        GIM_CheckRegBankForClass, /*MI*/0, /*Op*/0, /*RC*/GIMT_Encode2(AMDGPU::VGPR_32RegClassID),
        GIM_RecordInsn, /*DefineMI*/1, /*MI*/0, /*OpIdx*/1, // MIs[1]
        GIM_CheckOpcode, /*MI*/1, GIMT_Encode2(TargetOpcode::G_FMAXNUM_IEEE),
        GIM_CheckType, /*MI*/1, /*Op*/1, /*Type*/GILLT_s32,
        GIM_CheckType, /*MI*/1, /*Op*/2, /*Type*/GILLT_s32,
        GIM_RecordInsn, /*DefineMI*/2, /*MI*/0, /*OpIdx*/2, // MIs[2]
        GIM_CheckOpcode, /*MI*/2, GIMT_Encode2(TargetOpcode::G_FMAXNUM_IEEE),
        GIM_CheckType, /*MI*/2, /*Op*/1, /*Type*/GILLT_s32,
        GIM_CheckType, /*MI*/2, /*Op*/2, /*Type*/GILLT_s32,
        GIM_RecordInsn, /*DefineMI*/3, /*MI*/2, /*OpIdx*/2, // MIs[3]
        GIM_CheckOpcode, /*MI*/3, GIMT_Encode2(TargetOpcode::G_FMINNUM_IEEE),
        // MIs[3] VOP3Mods:src1:src1_mods
        GIM_CheckIsSameOperand, /*MI*/3, /*OpIdx*/1, /*OtherMI*/1, /*OtherOpIdx*/2,
        // MIs[3] VOP3Mods:src0:src0_mods
        GIM_CheckIsSameOperand, /*MI*/3, /*OpIdx*/2, /*OtherMI*/1, /*OtherOpIdx*/1,
        GIM_CheckCxxInsnPredicate, /*MI*/0, /*FnId*/GIMT_Encode2(GICXXPred_MI_Predicate_fminnum_like_nnan),
        GIM_CheckIsSafeToFold, /*InsnID*/1,
        GIM_CheckIsSafeToFold, /*InsnID*/2,
        GIM_CheckIsSafeToFold, /*InsnID*/3,
        GIM_CheckComplexPattern, /*MI*/1, /*Op*/1, /*Renderer*/GIMT_Encode2(0), GIMT_Encode2(GICP_gi_vop3mods),
        GIM_CheckComplexPattern, /*MI*/1, /*Op*/2, /*Renderer*/GIMT_Encode2(1), GIMT_Encode2(GICP_gi_vop3mods),
        GIM_CheckComplexPattern, /*MI*/2, /*Op*/1, /*Renderer*/GIMT_Encode2(2), GIMT_Encode2(GICP_gi_vop3mods),
        // (fminnum_ieee:{ *:[f32] } (fmaxnum_ieee:{ *:[f32] } (VOP3Mods:{ *:[f32] } f32:{ *:[f32] }:$src0, i32:{ *:[i32] }:$src0_mods), (VOP3Mods:{ *:[f32] } f32:{ *:[f32] }:$src1, i32:{ *:[i32] }:$src1_mods)), (fmaxnum_ieee:{ *:[f32] } (VOP3Mods:{ *:[f32] } f32:{ *:[f32] }:$src2, i32:{ *:[i32] }:$src2_mods), (fminnum_ieee:{ *:[f32] } (VOP3Mods:{ *:[f32] } f32:{ *:[f32] }:$src1, i32:{ *:[i32] }:$src1_mods), (VOP3Mods:{ *:[f32] } f32:{ *:[f32] }:$src0, i32:{ *:[i32] }:$src0_mods))))<<P:Predicate_fminnum_like_nnan>>  =>  (V_MED3_F32_e64:{ *:[f32] } ?:{ *:[i32] }:$src0_mods, ?:{ *:[f32] }:$src0, ?:{ *:[i32] }:$src1_mods, ?:{ *:[f32] }:$src1, ?:{ *:[i32] }:$src2_mods, ?:{ *:[f32] }:$src2, 0:{ *:[i1] }, 0:{ *:[i32] })
        GIR_BuildMI, /*InsnID*/0, /*Opcode*/GIMT_Encode2(AMDGPU::V_MED3_F32_e64),
        GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/0, // DstI[vdst]
        GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/1, // src0_mods
        GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/0, // src0
        GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(1), /*SubOperand*/1, // src1_mods
        GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(1), /*SubOperand*/0, // src1
        GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(2), /*SubOperand*/1, // src2_mods
        GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(2), /*SubOperand*/0, // src2
        GIR_AddImm8, /*InsnID*/0, /*Imm*/0,
        GIR_AddImm8, /*InsnID*/0, /*Imm*/0,
        GIR_ConstrainSelectedInstOperands, /*InsnID*/0,
        GIR_EraseFromParent, /*InsnID*/0,
        // GIR_Coverage, 10242,
        GIR_Done,
      // Label 4856: @339557
      GIM_Try, /*On fail goto*//*Label 4857*/ GIMT_Encode4(339697), // Rule ID 10245 //
        GIM_CheckRegBankForClass, /*MI*/0, /*Op*/0, /*RC*/GIMT_Encode2(AMDGPU::VGPR_32RegClassID),
        GIM_RecordInsn, /*DefineMI*/1, /*MI*/0, /*OpIdx*/1, // MIs[1]
        GIM_CheckOpcode, /*MI*/1, GIMT_Encode2(TargetOpcode::G_FMAXNUM_IEEE),
        GIM_CheckType, /*MI*/1, /*Op*/1, /*Type*/GILLT_s32,
        GIM_CheckType, /*MI*/1, /*Op*/2, /*Type*/GILLT_s32,
        GIM_RecordInsn, /*DefineMI*/2, /*MI*/0, /*OpIdx*/2, // MIs[2]
        GIM_CheckOpcode, /*MI*/2, GIMT_Encode2(TargetOpcode::G_FMAXNUM_IEEE),
        GIM_CheckType, /*MI*/2, /*Op*/1, /*Type*/GILLT_s32,
        GIM_CheckType, /*MI*/2, /*Op*/2, /*Type*/GILLT_s32,
        GIM_RecordInsn, /*DefineMI*/3, /*MI*/2, /*OpIdx*/2, // MIs[3]
        GIM_CheckOpcode, /*MI*/3, GIMT_Encode2(TargetOpcode::G_FMINNUM_IEEE),
        // MIs[3] VOP3Mods:src0:src0_mods
        GIM_CheckIsSameOperand, /*MI*/3, /*OpIdx*/1, /*OtherMI*/1, /*OtherOpIdx*/2,
        // MIs[3] VOP3Mods:src1:src1_mods
        GIM_CheckIsSameOperand, /*MI*/3, /*OpIdx*/2, /*OtherMI*/1, /*OtherOpIdx*/1,
        GIM_CheckCxxInsnPredicate, /*MI*/0, /*FnId*/GIMT_Encode2(GICXXPred_MI_Predicate_fminnum_like_nnan),
        GIM_CheckIsSafeToFold, /*InsnID*/1,
        GIM_CheckIsSafeToFold, /*InsnID*/2,
        GIM_CheckIsSafeToFold, /*InsnID*/3,
        GIM_CheckComplexPattern, /*MI*/1, /*Op*/1, /*Renderer*/GIMT_Encode2(0), GIMT_Encode2(GICP_gi_vop3mods),
        GIM_CheckComplexPattern, /*MI*/1, /*Op*/2, /*Renderer*/GIMT_Encode2(1), GIMT_Encode2(GICP_gi_vop3mods),
        GIM_CheckComplexPattern, /*MI*/2, /*Op*/1, /*Renderer*/GIMT_Encode2(2), GIMT_Encode2(GICP_gi_vop3mods),
        // (fminnum_ieee:{ *:[f32] } (fmaxnum_ieee:{ *:[f32] } (VOP3Mods:{ *:[f32] } f32:{ *:[f32] }:$src1, i32:{ *:[i32] }:$src1_mods), (VOP3Mods:{ *:[f32] } f32:{ *:[f32] }:$src0, i32:{ *:[i32] }:$src0_mods)), (fmaxnum_ieee:{ *:[f32] } (VOP3Mods:{ *:[f32] } f32:{ *:[f32] }:$src2, i32:{ *:[i32] }:$src2_mods), (fminnum_ieee:{ *:[f32] } (VOP3Mods:{ *:[f32] } f32:{ *:[f32] }:$src0, i32:{ *:[i32] }:$src0_mods), (VOP3Mods:{ *:[f32] } f32:{ *:[f32] }:$src1, i32:{ *:[i32] }:$src1_mods))))<<P:Predicate_fminnum_like_nnan>>  =>  (V_MED3_F32_e64:{ *:[f32] } ?:{ *:[i32] }:$src0_mods, ?:{ *:[f32] }:$src0, ?:{ *:[i32] }:$src1_mods, ?:{ *:[f32] }:$src1, ?:{ *:[i32] }:$src2_mods, ?:{ *:[f32] }:$src2, 0:{ *:[i1] }, 0:{ *:[i32] })
        GIR_BuildMI, /*InsnID*/0, /*Opcode*/GIMT_Encode2(AMDGPU::V_MED3_F32_e64),
        GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/0, // DstI[vdst]
        GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(1), /*SubOperand*/1, // src0_mods
        GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(1), /*SubOperand*/0, // src0
        GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/1, // src1_mods
        GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/0, // src1
        GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(2), /*SubOperand*/1, // src2_mods
        GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(2), /*SubOperand*/0, // src2
        GIR_AddImm8, /*InsnID*/0, /*Imm*/0,
        GIR_AddImm8, /*InsnID*/0, /*Imm*/0,
        GIR_ConstrainSelectedInstOperands, /*InsnID*/0,
        GIR_EraseFromParent, /*InsnID*/0,
        // GIR_Coverage, 10245,
        GIR_Done,
      // Label 4857: @339697
      GIM_Try, /*On fail goto*//*Label 4858*/ GIMT_Encode4(339837), // Rule ID 10246 //
        GIM_CheckRegBankForClass, /*MI*/0, /*Op*/0, /*RC*/GIMT_Encode2(AMDGPU::VGPR_32RegClassID),
        GIM_RecordInsn, /*DefineMI*/1, /*MI*/0, /*OpIdx*/1, // MIs[1]
        GIM_CheckOpcode, /*MI*/1, GIMT_Encode2(TargetOpcode::G_FMAXNUM_IEEE),
        GIM_CheckType, /*MI*/1, /*Op*/1, /*Type*/GILLT_s32,
        GIM_CheckType, /*MI*/1, /*Op*/2, /*Type*/GILLT_s32,
        GIM_RecordInsn, /*DefineMI*/2, /*MI*/0, /*OpIdx*/2, // MIs[2]
        GIM_CheckOpcode, /*MI*/2, GIMT_Encode2(TargetOpcode::G_FMAXNUM_IEEE),
        GIM_CheckType, /*MI*/2, /*Op*/1, /*Type*/GILLT_s32,
        GIM_CheckType, /*MI*/2, /*Op*/2, /*Type*/GILLT_s32,
        GIM_RecordInsn, /*DefineMI*/3, /*MI*/2, /*OpIdx*/2, // MIs[3]
        GIM_CheckOpcode, /*MI*/3, GIMT_Encode2(TargetOpcode::G_FMINNUM_IEEE),
        // MIs[3] VOP3Mods:src1:src1_mods
        GIM_CheckIsSameOperand, /*MI*/3, /*OpIdx*/1, /*OtherMI*/1, /*OtherOpIdx*/1,
        // MIs[3] VOP3Mods:src0:src0_mods
        GIM_CheckIsSameOperand, /*MI*/3, /*OpIdx*/2, /*OtherMI*/1, /*OtherOpIdx*/2,
        GIM_CheckCxxInsnPredicate, /*MI*/0, /*FnId*/GIMT_Encode2(GICXXPred_MI_Predicate_fminnum_like_nnan),
        GIM_CheckIsSafeToFold, /*InsnID*/1,
        GIM_CheckIsSafeToFold, /*InsnID*/2,
        GIM_CheckIsSafeToFold, /*InsnID*/3,
        GIM_CheckComplexPattern, /*MI*/1, /*Op*/1, /*Renderer*/GIMT_Encode2(0), GIMT_Encode2(GICP_gi_vop3mods),
        GIM_CheckComplexPattern, /*MI*/1, /*Op*/2, /*Renderer*/GIMT_Encode2(1), GIMT_Encode2(GICP_gi_vop3mods),
        GIM_CheckComplexPattern, /*MI*/2, /*Op*/1, /*Renderer*/GIMT_Encode2(2), GIMT_Encode2(GICP_gi_vop3mods),
        // (fminnum_ieee:{ *:[f32] } (fmaxnum_ieee:{ *:[f32] } (VOP3Mods:{ *:[f32] } f32:{ *:[f32] }:$src1, i32:{ *:[i32] }:$src1_mods), (VOP3Mods:{ *:[f32] } f32:{ *:[f32] }:$src0, i32:{ *:[i32] }:$src0_mods)), (fmaxnum_ieee:{ *:[f32] } (VOP3Mods:{ *:[f32] } f32:{ *:[f32] }:$src2, i32:{ *:[i32] }:$src2_mods), (fminnum_ieee:{ *:[f32] } (VOP3Mods:{ *:[f32] } f32:{ *:[f32] }:$src1, i32:{ *:[i32] }:$src1_mods), (VOP3Mods:{ *:[f32] } f32:{ *:[f32] }:$src0, i32:{ *:[i32] }:$src0_mods))))<<P:Predicate_fminnum_like_nnan>>  =>  (V_MED3_F32_e64:{ *:[f32] } ?:{ *:[i32] }:$src0_mods, ?:{ *:[f32] }:$src0, ?:{ *:[i32] }:$src1_mods, ?:{ *:[f32] }:$src1, ?:{ *:[i32] }:$src2_mods, ?:{ *:[f32] }:$src2, 0:{ *:[i1] }, 0:{ *:[i32] })
        GIR_BuildMI, /*InsnID*/0, /*Opcode*/GIMT_Encode2(AMDGPU::V_MED3_F32_e64),
        GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/0, // DstI[vdst]
        GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(1), /*SubOperand*/1, // src0_mods
        GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(1), /*SubOperand*/0, // src0
        GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/1, // src1_mods
        GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/0, // src1
        GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(2), /*SubOperand*/1, // src2_mods
        GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(2), /*SubOperand*/0, // src2
        GIR_AddImm8, /*InsnID*/0, /*Imm*/0,
        GIR_AddImm8, /*InsnID*/0, /*Imm*/0,
        GIR_ConstrainSelectedInstOperands, /*InsnID*/0,
        GIR_EraseFromParent, /*InsnID*/0,
        // GIR_Coverage, 10246,
        GIR_Done,
      // Label 4858: @339837
      GIM_Try, /*On fail goto*//*Label 4859*/ GIMT_Encode4(339977), // Rule ID 6499 //
        GIM_CheckRegBankForClass, /*MI*/0, /*Op*/0, /*RC*/GIMT_Encode2(AMDGPU::VGPR_32RegClassID),
        GIM_RecordInsn, /*DefineMI*/1, /*MI*/0, /*OpIdx*/1, // MIs[1]
        GIM_CheckOpcode, /*MI*/1, GIMT_Encode2(TargetOpcode::G_FMAXNUM_IEEE),
        GIM_CheckType, /*MI*/1, /*Op*/1, /*Type*/GILLT_s32,
        GIM_CheckType, /*MI*/1, /*Op*/2, /*Type*/GILLT_s32,
        GIM_RecordInsn, /*DefineMI*/2, /*MI*/0, /*OpIdx*/2, // MIs[2]
        GIM_CheckOpcode, /*MI*/2, GIMT_Encode2(TargetOpcode::G_FMAXNUM_IEEE),
        GIM_CheckType, /*MI*/2, /*Op*/1, /*Type*/GILLT_s32,
        GIM_CheckType, /*MI*/2, /*Op*/2, /*Type*/GILLT_s32,
        GIM_RecordInsn, /*DefineMI*/3, /*MI*/2, /*OpIdx*/1, // MIs[3]
        GIM_CheckOpcode, /*MI*/3, GIMT_Encode2(TargetOpcode::G_FMINNUM),
        // MIs[3] VOP3Mods:src0:src0_mods
        GIM_CheckIsSameOperand, /*MI*/3, /*OpIdx*/1, /*OtherMI*/1, /*OtherOpIdx*/1,
        // MIs[3] VOP3Mods:src1:src1_mods
        GIM_CheckIsSameOperand, /*MI*/3, /*OpIdx*/2, /*OtherMI*/1, /*OtherOpIdx*/2,
        GIM_CheckCxxInsnPredicate, /*MI*/0, /*FnId*/GIMT_Encode2(GICXXPred_MI_Predicate_fminnum_like_nnan),
        GIM_CheckIsSafeToFold, /*InsnID*/1,
        GIM_CheckIsSafeToFold, /*InsnID*/2,
        GIM_CheckIsSafeToFold, /*InsnID*/3,
        GIM_CheckComplexPattern, /*MI*/1, /*Op*/1, /*Renderer*/GIMT_Encode2(0), GIMT_Encode2(GICP_gi_vop3mods),
        GIM_CheckComplexPattern, /*MI*/1, /*Op*/2, /*Renderer*/GIMT_Encode2(1), GIMT_Encode2(GICP_gi_vop3mods),
        GIM_CheckComplexPattern, /*MI*/2, /*Op*/2, /*Renderer*/GIMT_Encode2(2), GIMT_Encode2(GICP_gi_vop3mods),
        // (fminnum_ieee:{ *:[f32] } (fmaxnum_ieee:{ *:[f32] } (VOP3Mods:{ *:[f32] } f32:{ *:[f32] }:$src0, i32:{ *:[i32] }:$src0_mods), (VOP3Mods:{ *:[f32] } f32:{ *:[f32] }:$src1, i32:{ *:[i32] }:$src1_mods)), (fmaxnum_ieee:{ *:[f32] } (fminnum:{ *:[f32] } (VOP3Mods:{ *:[f32] } f32:{ *:[f32] }:$src0, i32:{ *:[i32] }:$src0_mods), (VOP3Mods:{ *:[f32] } f32:{ *:[f32] }:$src1, i32:{ *:[i32] }:$src1_mods)), (VOP3Mods:{ *:[f32] } f32:{ *:[f32] }:$src2, i32:{ *:[i32] }:$src2_mods)))<<P:Predicate_fminnum_like_nnan>>  =>  (V_MED3_F32_e64:{ *:[f32] } ?:{ *:[i32] }:$src0_mods, ?:{ *:[f32] }:$src0, ?:{ *:[i32] }:$src1_mods, ?:{ *:[f32] }:$src1, ?:{ *:[i32] }:$src2_mods, ?:{ *:[f32] }:$src2, 0:{ *:[i1] }, 0:{ *:[i32] })
        GIR_BuildMI, /*InsnID*/0, /*Opcode*/GIMT_Encode2(AMDGPU::V_MED3_F32_e64),
        GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/0, // DstI[vdst]
        GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/1, // src0_mods
        GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/0, // src0
        GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(1), /*SubOperand*/1, // src1_mods
        GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(1), /*SubOperand*/0, // src1
        GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(2), /*SubOperand*/1, // src2_mods
        GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(2), /*SubOperand*/0, // src2
        GIR_AddImm8, /*InsnID*/0, /*Imm*/0,
        GIR_AddImm8, /*InsnID*/0, /*Imm*/0,
        GIR_ConstrainSelectedInstOperands, /*InsnID*/0,
        GIR_EraseFromParent, /*InsnID*/0,
        // GIR_Coverage, 6499,
        GIR_Done,
      // Label 4859: @339977
      GIM_Try, /*On fail goto*//*Label 4860*/ GIMT_Encode4(340117), // Rule ID 10255 //
        GIM_CheckRegBankForClass, /*MI*/0, /*Op*/0, /*RC*/GIMT_Encode2(AMDGPU::VGPR_32RegClassID),
        GIM_RecordInsn, /*DefineMI*/1, /*MI*/0, /*OpIdx*/1, // MIs[1]
        GIM_CheckOpcode, /*MI*/1, GIMT_Encode2(TargetOpcode::G_FMAXNUM_IEEE),
        GIM_CheckType, /*MI*/1, /*Op*/1, /*Type*/GILLT_s32,
        GIM_CheckType, /*MI*/1, /*Op*/2, /*Type*/GILLT_s32,
        GIM_RecordInsn, /*DefineMI*/2, /*MI*/0, /*OpIdx*/2, // MIs[2]
        GIM_CheckOpcode, /*MI*/2, GIMT_Encode2(TargetOpcode::G_FMAXNUM_IEEE),
        GIM_CheckType, /*MI*/2, /*Op*/1, /*Type*/GILLT_s32,
        GIM_CheckType, /*MI*/2, /*Op*/2, /*Type*/GILLT_s32,
        GIM_RecordInsn, /*DefineMI*/3, /*MI*/2, /*OpIdx*/1, // MIs[3]
        GIM_CheckOpcode, /*MI*/3, GIMT_Encode2(TargetOpcode::G_FMINNUM),
        // MIs[3] VOP3Mods:src1:src1_mods
        GIM_CheckIsSameOperand, /*MI*/3, /*OpIdx*/1, /*OtherMI*/1, /*OtherOpIdx*/2,
        // MIs[3] VOP3Mods:src0:src0_mods
        GIM_CheckIsSameOperand, /*MI*/3, /*OpIdx*/2, /*OtherMI*/1, /*OtherOpIdx*/1,
        GIM_CheckCxxInsnPredicate, /*MI*/0, /*FnId*/GIMT_Encode2(GICXXPred_MI_Predicate_fminnum_like_nnan),
        GIM_CheckIsSafeToFold, /*InsnID*/1,
        GIM_CheckIsSafeToFold, /*InsnID*/2,
        GIM_CheckIsSafeToFold, /*InsnID*/3,
        GIM_CheckComplexPattern, /*MI*/1, /*Op*/1, /*Renderer*/GIMT_Encode2(0), GIMT_Encode2(GICP_gi_vop3mods),
        GIM_CheckComplexPattern, /*MI*/1, /*Op*/2, /*Renderer*/GIMT_Encode2(1), GIMT_Encode2(GICP_gi_vop3mods),
        GIM_CheckComplexPattern, /*MI*/2, /*Op*/2, /*Renderer*/GIMT_Encode2(2), GIMT_Encode2(GICP_gi_vop3mods),
        // (fminnum_ieee:{ *:[f32] } (fmaxnum_ieee:{ *:[f32] } (VOP3Mods:{ *:[f32] } f32:{ *:[f32] }:$src0, i32:{ *:[i32] }:$src0_mods), (VOP3Mods:{ *:[f32] } f32:{ *:[f32] }:$src1, i32:{ *:[i32] }:$src1_mods)), (fmaxnum_ieee:{ *:[f32] } (fminnum:{ *:[f32] } (VOP3Mods:{ *:[f32] } f32:{ *:[f32] }:$src1, i32:{ *:[i32] }:$src1_mods), (VOP3Mods:{ *:[f32] } f32:{ *:[f32] }:$src0, i32:{ *:[i32] }:$src0_mods)), (VOP3Mods:{ *:[f32] } f32:{ *:[f32] }:$src2, i32:{ *:[i32] }:$src2_mods)))<<P:Predicate_fminnum_like_nnan>>  =>  (V_MED3_F32_e64:{ *:[f32] } ?:{ *:[i32] }:$src0_mods, ?:{ *:[f32] }:$src0, ?:{ *:[i32] }:$src1_mods, ?:{ *:[f32] }:$src1, ?:{ *:[i32] }:$src2_mods, ?:{ *:[f32] }:$src2, 0:{ *:[i1] }, 0:{ *:[i32] })
        GIR_BuildMI, /*InsnID*/0, /*Opcode*/GIMT_Encode2(AMDGPU::V_MED3_F32_e64),
        GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/0, // DstI[vdst]
        GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/1, // src0_mods
        GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/0, // src0
        GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(1), /*SubOperand*/1, // src1_mods
        GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(1), /*SubOperand*/0, // src1
        GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(2), /*SubOperand*/1, // src2_mods
        GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(2), /*SubOperand*/0, // src2
        GIR_AddImm8, /*InsnID*/0, /*Imm*/0,
        GIR_AddImm8, /*InsnID*/0, /*Imm*/0,
        GIR_ConstrainSelectedInstOperands, /*InsnID*/0,
        GIR_EraseFromParent, /*InsnID*/0,
        // GIR_Coverage, 10255,
        GIR_Done,
      // Label 4860: @340117
      GIM_Try, /*On fail goto*//*Label 4861*/ GIMT_Encode4(340257), // Rule ID 10258 //
        GIM_CheckRegBankForClass, /*MI*/0, /*Op*/0, /*RC*/GIMT_Encode2(AMDGPU::VGPR_32RegClassID),
        GIM_RecordInsn, /*DefineMI*/1, /*MI*/0, /*OpIdx*/1, // MIs[1]
        GIM_CheckOpcode, /*MI*/1, GIMT_Encode2(TargetOpcode::G_FMAXNUM_IEEE),
        GIM_CheckType, /*MI*/1, /*Op*/1, /*Type*/GILLT_s32,
        GIM_CheckType, /*MI*/1, /*Op*/2, /*Type*/GILLT_s32,
        GIM_RecordInsn, /*DefineMI*/2, /*MI*/0, /*OpIdx*/2, // MIs[2]
        GIM_CheckOpcode, /*MI*/2, GIMT_Encode2(TargetOpcode::G_FMAXNUM_IEEE),
        GIM_CheckType, /*MI*/2, /*Op*/1, /*Type*/GILLT_s32,
        GIM_CheckType, /*MI*/2, /*Op*/2, /*Type*/GILLT_s32,
        GIM_RecordInsn, /*DefineMI*/3, /*MI*/2, /*OpIdx*/1, // MIs[3]
        GIM_CheckOpcode, /*MI*/3, GIMT_Encode2(TargetOpcode::G_FMINNUM),
        // MIs[3] VOP3Mods:src0:src0_mods
        GIM_CheckIsSameOperand, /*MI*/3, /*OpIdx*/1, /*OtherMI*/1, /*OtherOpIdx*/2,
        // MIs[3] VOP3Mods:src1:src1_mods
        GIM_CheckIsSameOperand, /*MI*/3, /*OpIdx*/2, /*OtherMI*/1, /*OtherOpIdx*/1,
        GIM_CheckCxxInsnPredicate, /*MI*/0, /*FnId*/GIMT_Encode2(GICXXPred_MI_Predicate_fminnum_like_nnan),
        GIM_CheckIsSafeToFold, /*InsnID*/1,
        GIM_CheckIsSafeToFold, /*InsnID*/2,
        GIM_CheckIsSafeToFold, /*InsnID*/3,
        GIM_CheckComplexPattern, /*MI*/1, /*Op*/1, /*Renderer*/GIMT_Encode2(0), GIMT_Encode2(GICP_gi_vop3mods),
        GIM_CheckComplexPattern, /*MI*/1, /*Op*/2, /*Renderer*/GIMT_Encode2(1), GIMT_Encode2(GICP_gi_vop3mods),
        GIM_CheckComplexPattern, /*MI*/2, /*Op*/2, /*Renderer*/GIMT_Encode2(2), GIMT_Encode2(GICP_gi_vop3mods),
        // (fminnum_ieee:{ *:[f32] } (fmaxnum_ieee:{ *:[f32] } (VOP3Mods:{ *:[f32] } f32:{ *:[f32] }:$src1, i32:{ *:[i32] }:$src1_mods), (VOP3Mods:{ *:[f32] } f32:{ *:[f32] }:$src0, i32:{ *:[i32] }:$src0_mods)), (fmaxnum_ieee:{ *:[f32] } (fminnum:{ *:[f32] } (VOP3Mods:{ *:[f32] } f32:{ *:[f32] }:$src0, i32:{ *:[i32] }:$src0_mods), (VOP3Mods:{ *:[f32] } f32:{ *:[f32] }:$src1, i32:{ *:[i32] }:$src1_mods)), (VOP3Mods:{ *:[f32] } f32:{ *:[f32] }:$src2, i32:{ *:[i32] }:$src2_mods)))<<P:Predicate_fminnum_like_nnan>>  =>  (V_MED3_F32_e64:{ *:[f32] } ?:{ *:[i32] }:$src0_mods, ?:{ *:[f32] }:$src0, ?:{ *:[i32] }:$src1_mods, ?:{ *:[f32] }:$src1, ?:{ *:[i32] }:$src2_mods, ?:{ *:[f32] }:$src2, 0:{ *:[i1] }, 0:{ *:[i32] })
        GIR_BuildMI, /*InsnID*/0, /*Opcode*/GIMT_Encode2(AMDGPU::V_MED3_F32_e64),
        GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/0, // DstI[vdst]
        GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(1), /*SubOperand*/1, // src0_mods
        GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(1), /*SubOperand*/0, // src0
        GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/1, // src1_mods
        GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/0, // src1
        GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(2), /*SubOperand*/1, // src2_mods
        GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(2), /*SubOperand*/0, // src2
        GIR_AddImm8, /*InsnID*/0, /*Imm*/0,
        GIR_AddImm8, /*InsnID*/0, /*Imm*/0,
        GIR_ConstrainSelectedInstOperands, /*InsnID*/0,
        GIR_EraseFromParent, /*InsnID*/0,
        // GIR_Coverage, 10258,
        GIR_Done,
      // Label 4861: @340257
      GIM_Try, /*On fail goto*//*Label 4862*/ GIMT_Encode4(340397), // Rule ID 10259 //
        GIM_CheckRegBankForClass, /*MI*/0, /*Op*/0, /*RC*/GIMT_Encode2(AMDGPU::VGPR_32RegClassID),
        GIM_RecordInsn, /*DefineMI*/1, /*MI*/0, /*OpIdx*/1, // MIs[1]
        GIM_CheckOpcode, /*MI*/1, GIMT_Encode2(TargetOpcode::G_FMAXNUM_IEEE),
        GIM_CheckType, /*MI*/1, /*Op*/1, /*Type*/GILLT_s32,
        GIM_CheckType, /*MI*/1, /*Op*/2, /*Type*/GILLT_s32,
        GIM_RecordInsn, /*DefineMI*/2, /*MI*/0, /*OpIdx*/2, // MIs[2]
        GIM_CheckOpcode, /*MI*/2, GIMT_Encode2(TargetOpcode::G_FMAXNUM_IEEE),
        GIM_CheckType, /*MI*/2, /*Op*/1, /*Type*/GILLT_s32,
        GIM_CheckType, /*MI*/2, /*Op*/2, /*Type*/GILLT_s32,
        GIM_RecordInsn, /*DefineMI*/3, /*MI*/2, /*OpIdx*/1, // MIs[3]
        GIM_CheckOpcode, /*MI*/3, GIMT_Encode2(TargetOpcode::G_FMINNUM),
        // MIs[3] VOP3Mods:src1:src1_mods
        GIM_CheckIsSameOperand, /*MI*/3, /*OpIdx*/1, /*OtherMI*/1, /*OtherOpIdx*/1,
        // MIs[3] VOP3Mods:src0:src0_mods
        GIM_CheckIsSameOperand, /*MI*/3, /*OpIdx*/2, /*OtherMI*/1, /*OtherOpIdx*/2,
        GIM_CheckCxxInsnPredicate, /*MI*/0, /*FnId*/GIMT_Encode2(GICXXPred_MI_Predicate_fminnum_like_nnan),
        GIM_CheckIsSafeToFold, /*InsnID*/1,
        GIM_CheckIsSafeToFold, /*InsnID*/2,
        GIM_CheckIsSafeToFold, /*InsnID*/3,
        GIM_CheckComplexPattern, /*MI*/1, /*Op*/1, /*Renderer*/GIMT_Encode2(0), GIMT_Encode2(GICP_gi_vop3mods),
        GIM_CheckComplexPattern, /*MI*/1, /*Op*/2, /*Renderer*/GIMT_Encode2(1), GIMT_Encode2(GICP_gi_vop3mods),
        GIM_CheckComplexPattern, /*MI*/2, /*Op*/2, /*Renderer*/GIMT_Encode2(2), GIMT_Encode2(GICP_gi_vop3mods),
        // (fminnum_ieee:{ *:[f32] } (fmaxnum_ieee:{ *:[f32] } (VOP3Mods:{ *:[f32] } f32:{ *:[f32] }:$src1, i32:{ *:[i32] }:$src1_mods), (VOP3Mods:{ *:[f32] } f32:{ *:[f32] }:$src0, i32:{ *:[i32] }:$src0_mods)), (fmaxnum_ieee:{ *:[f32] } (fminnum:{ *:[f32] } (VOP3Mods:{ *:[f32] } f32:{ *:[f32] }:$src1, i32:{ *:[i32] }:$src1_mods), (VOP3Mods:{ *:[f32] } f32:{ *:[f32] }:$src0, i32:{ *:[i32] }:$src0_mods)), (VOP3Mods:{ *:[f32] } f32:{ *:[f32] }:$src2, i32:{ *:[i32] }:$src2_mods)))<<P:Predicate_fminnum_like_nnan>>  =>  (V_MED3_F32_e64:{ *:[f32] } ?:{ *:[i32] }:$src0_mods, ?:{ *:[f32] }:$src0, ?:{ *:[i32] }:$src1_mods, ?:{ *:[f32] }:$src1, ?:{ *:[i32] }:$src2_mods, ?:{ *:[f32] }:$src2, 0:{ *:[i1] }, 0:{ *:[i32] })
        GIR_BuildMI, /*InsnID*/0, /*Opcode*/GIMT_Encode2(AMDGPU::V_MED3_F32_e64),
        GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/0, // DstI[vdst]
        GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(1), /*SubOperand*/1, // src0_mods
        GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(1), /*SubOperand*/0, // src0
        GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/1, // src1_mods
        GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/0, // src1
        GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(2), /*SubOperand*/1, // src2_mods
        GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(2), /*SubOperand*/0, // src2
        GIR_AddImm8, /*InsnID*/0, /*Imm*/0,
        GIR_AddImm8, /*InsnID*/0, /*Imm*/0,
        GIR_ConstrainSelectedInstOperands, /*InsnID*/0,
        GIR_EraseFromParent, /*InsnID*/0,
        // GIR_Coverage, 10259,
        GIR_Done,
      // Label 4862: @340397
      GIM_Try, /*On fail goto*//*Label 4863*/ GIMT_Encode4(340537), // Rule ID 6498 //
        GIM_CheckRegBankForClass, /*MI*/0, /*Op*/0, /*RC*/GIMT_Encode2(AMDGPU::VGPR_32RegClassID),
        GIM_RecordInsn, /*DefineMI*/1, /*MI*/0, /*OpIdx*/1, // MIs[1]
        GIM_CheckOpcode, /*MI*/1, GIMT_Encode2(TargetOpcode::G_FMAXNUM_IEEE),
        GIM_CheckType, /*MI*/1, /*Op*/1, /*Type*/GILLT_s32,
        GIM_CheckType, /*MI*/1, /*Op*/2, /*Type*/GILLT_s32,
        GIM_RecordInsn, /*DefineMI*/2, /*MI*/0, /*OpIdx*/2, // MIs[2]
        GIM_CheckOpcode, /*MI*/2, GIMT_Encode2(TargetOpcode::G_FMAXNUM_IEEE),
        GIM_CheckType, /*MI*/2, /*Op*/1, /*Type*/GILLT_s32,
        GIM_CheckType, /*MI*/2, /*Op*/2, /*Type*/GILLT_s32,
        GIM_RecordInsn, /*DefineMI*/3, /*MI*/2, /*OpIdx*/1, // MIs[3]
        GIM_CheckOpcode, /*MI*/3, GIMT_Encode2(TargetOpcode::G_FMINNUM_IEEE),
        // MIs[3] VOP3Mods:src0:src0_mods
        GIM_CheckIsSameOperand, /*MI*/3, /*OpIdx*/1, /*OtherMI*/1, /*OtherOpIdx*/1,
        // MIs[3] VOP3Mods:src1:src1_mods
        GIM_CheckIsSameOperand, /*MI*/3, /*OpIdx*/2, /*OtherMI*/1, /*OtherOpIdx*/2,
        GIM_CheckCxxInsnPredicate, /*MI*/0, /*FnId*/GIMT_Encode2(GICXXPred_MI_Predicate_fminnum_like_nnan),
        GIM_CheckIsSafeToFold, /*InsnID*/1,
        GIM_CheckIsSafeToFold, /*InsnID*/2,
        GIM_CheckIsSafeToFold, /*InsnID*/3,
        GIM_CheckComplexPattern, /*MI*/1, /*Op*/1, /*Renderer*/GIMT_Encode2(0), GIMT_Encode2(GICP_gi_vop3mods),
        GIM_CheckComplexPattern, /*MI*/1, /*Op*/2, /*Renderer*/GIMT_Encode2(1), GIMT_Encode2(GICP_gi_vop3mods),
        GIM_CheckComplexPattern, /*MI*/2, /*Op*/2, /*Renderer*/GIMT_Encode2(2), GIMT_Encode2(GICP_gi_vop3mods),
        // (fminnum_ieee:{ *:[f32] } (fmaxnum_ieee:{ *:[f32] } (VOP3Mods:{ *:[f32] } f32:{ *:[f32] }:$src0, i32:{ *:[i32] }:$src0_mods), (VOP3Mods:{ *:[f32] } f32:{ *:[f32] }:$src1, i32:{ *:[i32] }:$src1_mods)), (fmaxnum_ieee:{ *:[f32] } (fminnum_ieee:{ *:[f32] } (VOP3Mods:{ *:[f32] } f32:{ *:[f32] }:$src0, i32:{ *:[i32] }:$src0_mods), (VOP3Mods:{ *:[f32] } f32:{ *:[f32] }:$src1, i32:{ *:[i32] }:$src1_mods)), (VOP3Mods:{ *:[f32] } f32:{ *:[f32] }:$src2, i32:{ *:[i32] }:$src2_mods)))<<P:Predicate_fminnum_like_nnan>>  =>  (V_MED3_F32_e64:{ *:[f32] } ?:{ *:[i32] }:$src0_mods, ?:{ *:[f32] }:$src0, ?:{ *:[i32] }:$src1_mods, ?:{ *:[f32] }:$src1, ?:{ *:[i32] }:$src2_mods, ?:{ *:[f32] }:$src2, 0:{ *:[i1] }, 0:{ *:[i32] })
        GIR_BuildMI, /*InsnID*/0, /*Opcode*/GIMT_Encode2(AMDGPU::V_MED3_F32_e64),
        GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/0, // DstI[vdst]
        GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/1, // src0_mods
        GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/0, // src0
        GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(1), /*SubOperand*/1, // src1_mods
        GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(1), /*SubOperand*/0, // src1
        GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(2), /*SubOperand*/1, // src2_mods
        GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(2), /*SubOperand*/0, // src2
        GIR_AddImm8, /*InsnID*/0, /*Imm*/0,
        GIR_AddImm8, /*InsnID*/0, /*Imm*/0,
        GIR_ConstrainSelectedInstOperands, /*InsnID*/0,
        GIR_EraseFromParent, /*InsnID*/0,
        // GIR_Coverage, 6498,
        GIR_Done,
      // Label 4863: @340537
      GIM_Try, /*On fail goto*//*Label 4864*/ GIMT_Encode4(340677), // Rule ID 10240 //
        GIM_CheckRegBankForClass, /*MI*/0, /*Op*/0, /*RC*/GIMT_Encode2(AMDGPU::VGPR_32RegClassID),
        GIM_RecordInsn, /*DefineMI*/1, /*MI*/0, /*OpIdx*/1, // MIs[1]
        GIM_CheckOpcode, /*MI*/1, GIMT_Encode2(TargetOpcode::G_FMAXNUM_IEEE),
        GIM_CheckType, /*MI*/1, /*Op*/1, /*Type*/GILLT_s32,
        GIM_CheckType, /*MI*/1, /*Op*/2, /*Type*/GILLT_s32,
        GIM_RecordInsn, /*DefineMI*/2, /*MI*/0, /*OpIdx*/2, // MIs[2]
        GIM_CheckOpcode, /*MI*/2, GIMT_Encode2(TargetOpcode::G_FMAXNUM_IEEE),
        GIM_CheckType, /*MI*/2, /*Op*/1, /*Type*/GILLT_s32,
        GIM_CheckType, /*MI*/2, /*Op*/2, /*Type*/GILLT_s32,
        GIM_RecordInsn, /*DefineMI*/3, /*MI*/2, /*OpIdx*/1, // MIs[3]
        GIM_CheckOpcode, /*MI*/3, GIMT_Encode2(TargetOpcode::G_FMINNUM_IEEE),
        // MIs[3] VOP3Mods:src1:src1_mods
        GIM_CheckIsSameOperand, /*MI*/3, /*OpIdx*/1, /*OtherMI*/1, /*OtherOpIdx*/2,
        // MIs[3] VOP3Mods:src0:src0_mods
        GIM_CheckIsSameOperand, /*MI*/3, /*OpIdx*/2, /*OtherMI*/1, /*OtherOpIdx*/1,
        GIM_CheckCxxInsnPredicate, /*MI*/0, /*FnId*/GIMT_Encode2(GICXXPred_MI_Predicate_fminnum_like_nnan),
        GIM_CheckIsSafeToFold, /*InsnID*/1,
        GIM_CheckIsSafeToFold, /*InsnID*/2,
        GIM_CheckIsSafeToFold, /*InsnID*/3,
        GIM_CheckComplexPattern, /*MI*/1, /*Op*/1, /*Renderer*/GIMT_Encode2(0), GIMT_Encode2(GICP_gi_vop3mods),
        GIM_CheckComplexPattern, /*MI*/1, /*Op*/2, /*Renderer*/GIMT_Encode2(1), GIMT_Encode2(GICP_gi_vop3mods),
        GIM_CheckComplexPattern, /*MI*/2, /*Op*/2, /*Renderer*/GIMT_Encode2(2), GIMT_Encode2(GICP_gi_vop3mods),
        // (fminnum_ieee:{ *:[f32] } (fmaxnum_ieee:{ *:[f32] } (VOP3Mods:{ *:[f32] } f32:{ *:[f32] }:$src0, i32:{ *:[i32] }:$src0_mods), (VOP3Mods:{ *:[f32] } f32:{ *:[f32] }:$src1, i32:{ *:[i32] }:$src1_mods)), (fmaxnum_ieee:{ *:[f32] } (fminnum_ieee:{ *:[f32] } (VOP3Mods:{ *:[f32] } f32:{ *:[f32] }:$src1, i32:{ *:[i32] }:$src1_mods), (VOP3Mods:{ *:[f32] } f32:{ *:[f32] }:$src0, i32:{ *:[i32] }:$src0_mods)), (VOP3Mods:{ *:[f32] } f32:{ *:[f32] }:$src2, i32:{ *:[i32] }:$src2_mods)))<<P:Predicate_fminnum_like_nnan>>  =>  (V_MED3_F32_e64:{ *:[f32] } ?:{ *:[i32] }:$src0_mods, ?:{ *:[f32] }:$src0, ?:{ *:[i32] }:$src1_mods, ?:{ *:[f32] }:$src1, ?:{ *:[i32] }:$src2_mods, ?:{ *:[f32] }:$src2, 0:{ *:[i1] }, 0:{ *:[i32] })
        GIR_BuildMI, /*InsnID*/0, /*Opcode*/GIMT_Encode2(AMDGPU::V_MED3_F32_e64),
        GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/0, // DstI[vdst]
        GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/1, // src0_mods
        GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/0, // src0
        GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(1), /*SubOperand*/1, // src1_mods
        GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(1), /*SubOperand*/0, // src1
        GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(2), /*SubOperand*/1, // src2_mods
        GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(2), /*SubOperand*/0, // src2
        GIR_AddImm8, /*InsnID*/0, /*Imm*/0,
        GIR_AddImm8, /*InsnID*/0, /*Imm*/0,
        GIR_ConstrainSelectedInstOperands, /*InsnID*/0,
        GIR_EraseFromParent, /*InsnID*/0,
        // GIR_Coverage, 10240,
        GIR_Done,
      // Label 4864: @340677
      GIM_Try, /*On fail goto*//*Label 4865*/ GIMT_Encode4(340817), // Rule ID 10243 //
        GIM_CheckRegBankForClass, /*MI*/0, /*Op*/0, /*RC*/GIMT_Encode2(AMDGPU::VGPR_32RegClassID),
        GIM_RecordInsn, /*DefineMI*/1, /*MI*/0, /*OpIdx*/1, // MIs[1]
        GIM_CheckOpcode, /*MI*/1, GIMT_Encode2(TargetOpcode::G_FMAXNUM_IEEE),
        GIM_CheckType, /*MI*/1, /*Op*/1, /*Type*/GILLT_s32,
        GIM_CheckType, /*MI*/1, /*Op*/2, /*Type*/GILLT_s32,
        GIM_RecordInsn, /*DefineMI*/2, /*MI*/0, /*OpIdx*/2, // MIs[2]
        GIM_CheckOpcode, /*MI*/2, GIMT_Encode2(TargetOpcode::G_FMAXNUM_IEEE),
        GIM_CheckType, /*MI*/2, /*Op*/1, /*Type*/GILLT_s32,
        GIM_CheckType, /*MI*/2, /*Op*/2, /*Type*/GILLT_s32,
        GIM_RecordInsn, /*DefineMI*/3, /*MI*/2, /*OpIdx*/1, // MIs[3]
        GIM_CheckOpcode, /*MI*/3, GIMT_Encode2(TargetOpcode::G_FMINNUM_IEEE),
        // MIs[3] VOP3Mods:src0:src0_mods
        GIM_CheckIsSameOperand, /*MI*/3, /*OpIdx*/1, /*OtherMI*/1, /*OtherOpIdx*/2,
        // MIs[3] VOP3Mods:src1:src1_mods
        GIM_CheckIsSameOperand, /*MI*/3, /*OpIdx*/2, /*OtherMI*/1, /*OtherOpIdx*/1,
        GIM_CheckCxxInsnPredicate, /*MI*/0, /*FnId*/GIMT_Encode2(GICXXPred_MI_Predicate_fminnum_like_nnan),
        GIM_CheckIsSafeToFold, /*InsnID*/1,
        GIM_CheckIsSafeToFold, /*InsnID*/2,
        GIM_CheckIsSafeToFold, /*InsnID*/3,
        GIM_CheckComplexPattern, /*MI*/1, /*Op*/1, /*Renderer*/GIMT_Encode2(0), GIMT_Encode2(GICP_gi_vop3mods),
        GIM_CheckComplexPattern, /*MI*/1, /*Op*/2, /*Renderer*/GIMT_Encode2(1), GIMT_Encode2(GICP_gi_vop3mods),
        GIM_CheckComplexPattern, /*MI*/2, /*Op*/2, /*Renderer*/GIMT_Encode2(2), GIMT_Encode2(GICP_gi_vop3mods),
        // (fminnum_ieee:{ *:[f32] } (fmaxnum_ieee:{ *:[f32] } (VOP3Mods:{ *:[f32] } f32:{ *:[f32] }:$src1, i32:{ *:[i32] }:$src1_mods), (VOP3Mods:{ *:[f32] } f32:{ *:[f32] }:$src0, i32:{ *:[i32] }:$src0_mods)), (fmaxnum_ieee:{ *:[f32] } (fminnum_ieee:{ *:[f32] } (VOP3Mods:{ *:[f32] } f32:{ *:[f32] }:$src0, i32:{ *:[i32] }:$src0_mods), (VOP3Mods:{ *:[f32] } f32:{ *:[f32] }:$src1, i32:{ *:[i32] }:$src1_mods)), (VOP3Mods:{ *:[f32] } f32:{ *:[f32] }:$src2, i32:{ *:[i32] }:$src2_mods)))<<P:Predicate_fminnum_like_nnan>>  =>  (V_MED3_F32_e64:{ *:[f32] } ?:{ *:[i32] }:$src0_mods, ?:{ *:[f32] }:$src0, ?:{ *:[i32] }:$src1_mods, ?:{ *:[f32] }:$src1, ?:{ *:[i32] }:$src2_mods, ?:{ *:[f32] }:$src2, 0:{ *:[i1] }, 0:{ *:[i32] })
        GIR_BuildMI, /*InsnID*/0, /*Opcode*/GIMT_Encode2(AMDGPU::V_MED3_F32_e64),
        GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/0, // DstI[vdst]
        GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(1), /*SubOperand*/1, // src0_mods
        GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(1), /*SubOperand*/0, // src0
        GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/1, // src1_mods
        GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/0, // src1
        GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(2), /*SubOperand*/1, // src2_mods
        GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(2), /*SubOperand*/0, // src2
        GIR_AddImm8, /*InsnID*/0, /*Imm*/0,
        GIR_AddImm8, /*InsnID*/0, /*Imm*/0,
        GIR_ConstrainSelectedInstOperands, /*InsnID*/0,
        GIR_EraseFromParent, /*InsnID*/0,
        // GIR_Coverage, 10243,
        GIR_Done,
      // Label 4865: @340817
      GIM_Try, /*On fail goto*//*Label 4866*/ GIMT_Encode4(340957), // Rule ID 10244 //
        GIM_CheckRegBankForClass, /*MI*/0, /*Op*/0, /*RC*/GIMT_Encode2(AMDGPU::VGPR_32RegClassID),
        GIM_RecordInsn, /*DefineMI*/1, /*MI*/0, /*OpIdx*/1, // MIs[1]
        GIM_CheckOpcode, /*MI*/1, GIMT_Encode2(TargetOpcode::G_FMAXNUM_IEEE),
        GIM_CheckType, /*MI*/1, /*Op*/1, /*Type*/GILLT_s32,
        GIM_CheckType, /*MI*/1, /*Op*/2, /*Type*/GILLT_s32,
        GIM_RecordInsn, /*DefineMI*/2, /*MI*/0, /*OpIdx*/2, // MIs[2]
        GIM_CheckOpcode, /*MI*/2, GIMT_Encode2(TargetOpcode::G_FMAXNUM_IEEE),
        GIM_CheckType, /*MI*/2, /*Op*/1, /*Type*/GILLT_s32,
        GIM_CheckType, /*MI*/2, /*Op*/2, /*Type*/GILLT_s32,
        GIM_RecordInsn, /*DefineMI*/3, /*MI*/2, /*OpIdx*/1, // MIs[3]
        GIM_CheckOpcode, /*MI*/3, GIMT_Encode2(TargetOpcode::G_FMINNUM_IEEE),
        // MIs[3] VOP3Mods:src1:src1_mods
        GIM_CheckIsSameOperand, /*MI*/3, /*OpIdx*/1, /*OtherMI*/1, /*OtherOpIdx*/1,
        // MIs[3] VOP3Mods:src0:src0_mods
        GIM_CheckIsSameOperand, /*MI*/3, /*OpIdx*/2, /*OtherMI*/1, /*OtherOpIdx*/2,
        GIM_CheckCxxInsnPredicate, /*MI*/0, /*FnId*/GIMT_Encode2(GICXXPred_MI_Predicate_fminnum_like_nnan),
        GIM_CheckIsSafeToFold, /*InsnID*/1,
        GIM_CheckIsSafeToFold, /*InsnID*/2,
        GIM_CheckIsSafeToFold, /*InsnID*/3,
        GIM_CheckComplexPattern, /*MI*/1, /*Op*/1, /*Renderer*/GIMT_Encode2(0), GIMT_Encode2(GICP_gi_vop3mods),
        GIM_CheckComplexPattern, /*MI*/1, /*Op*/2, /*Renderer*/GIMT_Encode2(1), GIMT_Encode2(GICP_gi_vop3mods),
        GIM_CheckComplexPattern, /*MI*/2, /*Op*/2, /*Renderer*/GIMT_Encode2(2), GIMT_Encode2(GICP_gi_vop3mods),
        // (fminnum_ieee:{ *:[f32] } (fmaxnum_ieee:{ *:[f32] } (VOP3Mods:{ *:[f32] } f32:{ *:[f32] }:$src1, i32:{ *:[i32] }:$src1_mods), (VOP3Mods:{ *:[f32] } f32:{ *:[f32] }:$src0, i32:{ *:[i32] }:$src0_mods)), (fmaxnum_ieee:{ *:[f32] } (fminnum_ieee:{ *:[f32] } (VOP3Mods:{ *:[f32] } f32:{ *:[f32] }:$src1, i32:{ *:[i32] }:$src1_mods), (VOP3Mods:{ *:[f32] } f32:{ *:[f32] }:$src0, i32:{ *:[i32] }:$src0_mods)), (VOP3Mods:{ *:[f32] } f32:{ *:[f32] }:$src2, i32:{ *:[i32] }:$src2_mods)))<<P:Predicate_fminnum_like_nnan>>  =>  (V_MED3_F32_e64:{ *:[f32] } ?:{ *:[i32] }:$src0_mods, ?:{ *:[f32] }:$src0, ?:{ *:[i32] }:$src1_mods, ?:{ *:[f32] }:$src1, ?:{ *:[i32] }:$src2_mods, ?:{ *:[f32] }:$src2, 0:{ *:[i1] }, 0:{ *:[i32] })
        GIR_BuildMI, /*InsnID*/0, /*Opcode*/GIMT_Encode2(AMDGPU::V_MED3_F32_e64),
        GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/0, // DstI[vdst]
        GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(1), /*SubOperand*/1, // src0_mods
        GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(1), /*SubOperand*/0, // src0
        GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/1, // src1_mods
        GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/0, // src1
        GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(2), /*SubOperand*/1, // src2_mods
        GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(2), /*SubOperand*/0, // src2
        GIR_AddImm8, /*InsnID*/0, /*Imm*/0,
        GIR_AddImm8, /*InsnID*/0, /*Imm*/0,
        GIR_ConstrainSelectedInstOperands, /*InsnID*/0,
        GIR_EraseFromParent, /*InsnID*/0,
        // GIR_Coverage, 10244,
        GIR_Done,
      // Label 4866: @340957
      GIM_Try, /*On fail goto*//*Label 4867*/ GIMT_Encode4(341097), // Rule ID 10326 //
        GIM_CheckRegBankForClass, /*MI*/0, /*Op*/0, /*RC*/GIMT_Encode2(AMDGPU::VGPR_32RegClassID),
        GIM_RecordInsn, /*DefineMI*/1, /*MI*/0, /*OpIdx*/1, // MIs[1]
        GIM_CheckOpcode, /*MI*/1, GIMT_Encode2(TargetOpcode::G_FMAXNUM_IEEE),
        GIM_CheckType, /*MI*/1, /*Op*/1, /*Type*/GILLT_s32,
        GIM_CheckType, /*MI*/1, /*Op*/2, /*Type*/GILLT_s32,
        GIM_RecordInsn, /*DefineMI*/2, /*MI*/1, /*OpIdx*/2, // MIs[2]
        GIM_CheckOpcode, /*MI*/2, GIMT_Encode2(TargetOpcode::G_FMINNUM),
        GIM_CheckType, /*MI*/2, /*Op*/1, /*Type*/GILLT_s32,
        GIM_CheckType, /*MI*/2, /*Op*/2, /*Type*/GILLT_s32,
        GIM_RecordInsn, /*DefineMI*/3, /*MI*/0, /*OpIdx*/2, // MIs[3]
        GIM_CheckOpcode, /*MI*/3, GIMT_Encode2(TargetOpcode::G_FMAXNUM),
        // MIs[3] VOP3Mods:src0:src0_mods
        GIM_CheckIsSameOperand, /*MI*/3, /*OpIdx*/1, /*OtherMI*/2, /*OtherOpIdx*/1,
        // MIs[3] VOP3Mods:src1:src1_mods
        GIM_CheckIsSameOperand, /*MI*/3, /*OpIdx*/2, /*OtherMI*/2, /*OtherOpIdx*/2,
        GIM_CheckCxxInsnPredicate, /*MI*/0, /*FnId*/GIMT_Encode2(GICXXPred_MI_Predicate_fminnum_like_nnan),
        GIM_CheckIsSafeToFold, /*InsnID*/1,
        GIM_CheckIsSafeToFold, /*InsnID*/2,
        GIM_CheckIsSafeToFold, /*InsnID*/3,
        GIM_CheckComplexPattern, /*MI*/1, /*Op*/1, /*Renderer*/GIMT_Encode2(0), GIMT_Encode2(GICP_gi_vop3mods),
        GIM_CheckComplexPattern, /*MI*/2, /*Op*/1, /*Renderer*/GIMT_Encode2(1), GIMT_Encode2(GICP_gi_vop3mods),
        GIM_CheckComplexPattern, /*MI*/2, /*Op*/2, /*Renderer*/GIMT_Encode2(2), GIMT_Encode2(GICP_gi_vop3mods),
        // (fminnum_ieee:{ *:[f32] } (fmaxnum_ieee:{ *:[f32] } (VOP3Mods:{ *:[f32] } f32:{ *:[f32] }:$src2, i32:{ *:[i32] }:$src2_mods), (fminnum:{ *:[f32] } (VOP3Mods:{ *:[f32] } f32:{ *:[f32] }:$src0, i32:{ *:[i32] }:$src0_mods), (VOP3Mods:{ *:[f32] } f32:{ *:[f32] }:$src1, i32:{ *:[i32] }:$src1_mods))), (fmaxnum:{ *:[f32] } (VOP3Mods:{ *:[f32] } f32:{ *:[f32] }:$src0, i32:{ *:[i32] }:$src0_mods), (VOP3Mods:{ *:[f32] } f32:{ *:[f32] }:$src1, i32:{ *:[i32] }:$src1_mods)))<<P:Predicate_fminnum_like_nnan>>  =>  (V_MED3_F32_e64:{ *:[f32] } ?:{ *:[i32] }:$src0_mods, ?:{ *:[f32] }:$src0, ?:{ *:[i32] }:$src1_mods, ?:{ *:[f32] }:$src1, ?:{ *:[i32] }:$src2_mods, ?:{ *:[f32] }:$src2, 0:{ *:[i1] }, 0:{ *:[i32] })
        GIR_BuildMI, /*InsnID*/0, /*Opcode*/GIMT_Encode2(AMDGPU::V_MED3_F32_e64),
        GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/0, // DstI[vdst]
        GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(1), /*SubOperand*/1, // src0_mods
        GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(1), /*SubOperand*/0, // src0
        GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(2), /*SubOperand*/1, // src1_mods
        GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(2), /*SubOperand*/0, // src1
        GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/1, // src2_mods
        GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/0, // src2
        GIR_AddImm8, /*InsnID*/0, /*Imm*/0,
        GIR_AddImm8, /*InsnID*/0, /*Imm*/0,
        GIR_ConstrainSelectedInstOperands, /*InsnID*/0,
        GIR_EraseFromParent, /*InsnID*/0,
        // GIR_Coverage, 10326,
        GIR_Done,
      // Label 4867: @341097
      GIM_Try, /*On fail goto*//*Label 4868*/ GIMT_Encode4(341237), // Rule ID 10327 //
        GIM_CheckRegBankForClass, /*MI*/0, /*Op*/0, /*RC*/GIMT_Encode2(AMDGPU::VGPR_32RegClassID),
        GIM_RecordInsn, /*DefineMI*/1, /*MI*/0, /*OpIdx*/1, // MIs[1]
        GIM_CheckOpcode, /*MI*/1, GIMT_Encode2(TargetOpcode::G_FMAXNUM_IEEE),
        GIM_CheckType, /*MI*/1, /*Op*/1, /*Type*/GILLT_s32,
        GIM_CheckType, /*MI*/1, /*Op*/2, /*Type*/GILLT_s32,
        GIM_RecordInsn, /*DefineMI*/2, /*MI*/1, /*OpIdx*/2, // MIs[2]
        GIM_CheckOpcode, /*MI*/2, GIMT_Encode2(TargetOpcode::G_FMINNUM),
        GIM_CheckType, /*MI*/2, /*Op*/1, /*Type*/GILLT_s32,
        GIM_CheckType, /*MI*/2, /*Op*/2, /*Type*/GILLT_s32,
        GIM_RecordInsn, /*DefineMI*/3, /*MI*/0, /*OpIdx*/2, // MIs[3]
        GIM_CheckOpcode, /*MI*/3, GIMT_Encode2(TargetOpcode::G_FMAXNUM),
        // MIs[3] VOP3Mods:src1:src1_mods
        GIM_CheckIsSameOperand, /*MI*/3, /*OpIdx*/1, /*OtherMI*/2, /*OtherOpIdx*/2,
        // MIs[3] VOP3Mods:src0:src0_mods
        GIM_CheckIsSameOperand, /*MI*/3, /*OpIdx*/2, /*OtherMI*/2, /*OtherOpIdx*/1,
        GIM_CheckCxxInsnPredicate, /*MI*/0, /*FnId*/GIMT_Encode2(GICXXPred_MI_Predicate_fminnum_like_nnan),
        GIM_CheckIsSafeToFold, /*InsnID*/1,
        GIM_CheckIsSafeToFold, /*InsnID*/2,
        GIM_CheckIsSafeToFold, /*InsnID*/3,
        GIM_CheckComplexPattern, /*MI*/1, /*Op*/1, /*Renderer*/GIMT_Encode2(0), GIMT_Encode2(GICP_gi_vop3mods),
        GIM_CheckComplexPattern, /*MI*/2, /*Op*/1, /*Renderer*/GIMT_Encode2(1), GIMT_Encode2(GICP_gi_vop3mods),
        GIM_CheckComplexPattern, /*MI*/2, /*Op*/2, /*Renderer*/GIMT_Encode2(2), GIMT_Encode2(GICP_gi_vop3mods),
        // (fminnum_ieee:{ *:[f32] } (fmaxnum_ieee:{ *:[f32] } (VOP3Mods:{ *:[f32] } f32:{ *:[f32] }:$src2, i32:{ *:[i32] }:$src2_mods), (fminnum:{ *:[f32] } (VOP3Mods:{ *:[f32] } f32:{ *:[f32] }:$src0, i32:{ *:[i32] }:$src0_mods), (VOP3Mods:{ *:[f32] } f32:{ *:[f32] }:$src1, i32:{ *:[i32] }:$src1_mods))), (fmaxnum:{ *:[f32] } (VOP3Mods:{ *:[f32] } f32:{ *:[f32] }:$src1, i32:{ *:[i32] }:$src1_mods), (VOP3Mods:{ *:[f32] } f32:{ *:[f32] }:$src0, i32:{ *:[i32] }:$src0_mods)))<<P:Predicate_fminnum_like_nnan>>  =>  (V_MED3_F32_e64:{ *:[f32] } ?:{ *:[i32] }:$src0_mods, ?:{ *:[f32] }:$src0, ?:{ *:[i32] }:$src1_mods, ?:{ *:[f32] }:$src1, ?:{ *:[i32] }:$src2_mods, ?:{ *:[f32] }:$src2, 0:{ *:[i1] }, 0:{ *:[i32] })
        GIR_BuildMI, /*InsnID*/0, /*Opcode*/GIMT_Encode2(AMDGPU::V_MED3_F32_e64),
        GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/0, // DstI[vdst]
        GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(1), /*SubOperand*/1, // src0_mods
        GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(1), /*SubOperand*/0, // src0
        GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(2), /*SubOperand*/1, // src1_mods
        GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(2), /*SubOperand*/0, // src1
        GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/1, // src2_mods
        GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/0, // src2
        GIR_AddImm8, /*InsnID*/0, /*Imm*/0,
        GIR_AddImm8, /*InsnID*/0, /*Imm*/0,
        GIR_ConstrainSelectedInstOperands, /*InsnID*/0,
        GIR_EraseFromParent, /*InsnID*/0,
        // GIR_Coverage, 10327,
        GIR_Done,
      // Label 4868: @341237
      GIM_Try, /*On fail goto*//*Label 4869*/ GIMT_Encode4(341377), // Rule ID 10328 //
        GIM_CheckRegBankForClass, /*MI*/0, /*Op*/0, /*RC*/GIMT_Encode2(AMDGPU::VGPR_32RegClassID),
        GIM_RecordInsn, /*DefineMI*/1, /*MI*/0, /*OpIdx*/1, // MIs[1]
        GIM_CheckOpcode, /*MI*/1, GIMT_Encode2(TargetOpcode::G_FMAXNUM_IEEE),
        GIM_CheckType, /*MI*/1, /*Op*/1, /*Type*/GILLT_s32,
        GIM_CheckType, /*MI*/1, /*Op*/2, /*Type*/GILLT_s32,
        GIM_RecordInsn, /*DefineMI*/2, /*MI*/1, /*OpIdx*/2, // MIs[2]
        GIM_CheckOpcode, /*MI*/2, GIMT_Encode2(TargetOpcode::G_FMINNUM),
        GIM_CheckType, /*MI*/2, /*Op*/1, /*Type*/GILLT_s32,
        GIM_CheckType, /*MI*/2, /*Op*/2, /*Type*/GILLT_s32,
        GIM_RecordInsn, /*DefineMI*/3, /*MI*/0, /*OpIdx*/2, // MIs[3]
        GIM_CheckOpcode, /*MI*/3, GIMT_Encode2(TargetOpcode::G_FMAXNUM),
        // MIs[3] VOP3Mods:src0:src0_mods
        GIM_CheckIsSameOperand, /*MI*/3, /*OpIdx*/1, /*OtherMI*/2, /*OtherOpIdx*/2,
        // MIs[3] VOP3Mods:src1:src1_mods
        GIM_CheckIsSameOperand, /*MI*/3, /*OpIdx*/2, /*OtherMI*/2, /*OtherOpIdx*/1,
        GIM_CheckCxxInsnPredicate, /*MI*/0, /*FnId*/GIMT_Encode2(GICXXPred_MI_Predicate_fminnum_like_nnan),
        GIM_CheckIsSafeToFold, /*InsnID*/1,
        GIM_CheckIsSafeToFold, /*InsnID*/2,
        GIM_CheckIsSafeToFold, /*InsnID*/3,
        GIM_CheckComplexPattern, /*MI*/1, /*Op*/1, /*Renderer*/GIMT_Encode2(0), GIMT_Encode2(GICP_gi_vop3mods),
        GIM_CheckComplexPattern, /*MI*/2, /*Op*/1, /*Renderer*/GIMT_Encode2(1), GIMT_Encode2(GICP_gi_vop3mods),
        GIM_CheckComplexPattern, /*MI*/2, /*Op*/2, /*Renderer*/GIMT_Encode2(2), GIMT_Encode2(GICP_gi_vop3mods),
        // (fminnum_ieee:{ *:[f32] } (fmaxnum_ieee:{ *:[f32] } (VOP3Mods:{ *:[f32] } f32:{ *:[f32] }:$src2, i32:{ *:[i32] }:$src2_mods), (fminnum:{ *:[f32] } (VOP3Mods:{ *:[f32] } f32:{ *:[f32] }:$src1, i32:{ *:[i32] }:$src1_mods), (VOP3Mods:{ *:[f32] } f32:{ *:[f32] }:$src0, i32:{ *:[i32] }:$src0_mods))), (fmaxnum:{ *:[f32] } (VOP3Mods:{ *:[f32] } f32:{ *:[f32] }:$src0, i32:{ *:[i32] }:$src0_mods), (VOP3Mods:{ *:[f32] } f32:{ *:[f32] }:$src1, i32:{ *:[i32] }:$src1_mods)))<<P:Predicate_fminnum_like_nnan>>  =>  (V_MED3_F32_e64:{ *:[f32] } ?:{ *:[i32] }:$src0_mods, ?:{ *:[f32] }:$src0, ?:{ *:[i32] }:$src1_mods, ?:{ *:[f32] }:$src1, ?:{ *:[i32] }:$src2_mods, ?:{ *:[f32] }:$src2, 0:{ *:[i1] }, 0:{ *:[i32] })
        GIR_BuildMI, /*InsnID*/0, /*Opcode*/GIMT_Encode2(AMDGPU::V_MED3_F32_e64),
        GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/0, // DstI[vdst]
        GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(2), /*SubOperand*/1, // src0_mods
        GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(2), /*SubOperand*/0, // src0
        GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(1), /*SubOperand*/1, // src1_mods
        GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(1), /*SubOperand*/0, // src1
        GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/1, // src2_mods
        GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/0, // src2
        GIR_AddImm8, /*InsnID*/0, /*Imm*/0,
        GIR_AddImm8, /*InsnID*/0, /*Imm*/0,
        GIR_ConstrainSelectedInstOperands, /*InsnID*/0,
        GIR_EraseFromParent, /*InsnID*/0,
        // GIR_Coverage, 10328,
        GIR_Done,
      // Label 4869: @341377
      GIM_Try, /*On fail goto*//*Label 4870*/ GIMT_Encode4(341517), // Rule ID 10329 //
        GIM_CheckRegBankForClass, /*MI*/0, /*Op*/0, /*RC*/GIMT_Encode2(AMDGPU::VGPR_32RegClassID),
        GIM_RecordInsn, /*DefineMI*/1, /*MI*/0, /*OpIdx*/1, // MIs[1]
        GIM_CheckOpcode, /*MI*/1, GIMT_Encode2(TargetOpcode::G_FMAXNUM_IEEE),
        GIM_CheckType, /*MI*/1, /*Op*/1, /*Type*/GILLT_s32,
        GIM_CheckType, /*MI*/1, /*Op*/2, /*Type*/GILLT_s32,
        GIM_RecordInsn, /*DefineMI*/2, /*MI*/1, /*OpIdx*/2, // MIs[2]
        GIM_CheckOpcode, /*MI*/2, GIMT_Encode2(TargetOpcode::G_FMINNUM),
        GIM_CheckType, /*MI*/2, /*Op*/1, /*Type*/GILLT_s32,
        GIM_CheckType, /*MI*/2, /*Op*/2, /*Type*/GILLT_s32,
        GIM_RecordInsn, /*DefineMI*/3, /*MI*/0, /*OpIdx*/2, // MIs[3]
        GIM_CheckOpcode, /*MI*/3, GIMT_Encode2(TargetOpcode::G_FMAXNUM),
        // MIs[3] VOP3Mods:src1:src1_mods
        GIM_CheckIsSameOperand, /*MI*/3, /*OpIdx*/1, /*OtherMI*/2, /*OtherOpIdx*/1,
        // MIs[3] VOP3Mods:src0:src0_mods
        GIM_CheckIsSameOperand, /*MI*/3, /*OpIdx*/2, /*OtherMI*/2, /*OtherOpIdx*/2,
        GIM_CheckCxxInsnPredicate, /*MI*/0, /*FnId*/GIMT_Encode2(GICXXPred_MI_Predicate_fminnum_like_nnan),
        GIM_CheckIsSafeToFold, /*InsnID*/1,
        GIM_CheckIsSafeToFold, /*InsnID*/2,
        GIM_CheckIsSafeToFold, /*InsnID*/3,
        GIM_CheckComplexPattern, /*MI*/1, /*Op*/1, /*Renderer*/GIMT_Encode2(0), GIMT_Encode2(GICP_gi_vop3mods),
        GIM_CheckComplexPattern, /*MI*/2, /*Op*/1, /*Renderer*/GIMT_Encode2(1), GIMT_Encode2(GICP_gi_vop3mods),
        GIM_CheckComplexPattern, /*MI*/2, /*Op*/2, /*Renderer*/GIMT_Encode2(2), GIMT_Encode2(GICP_gi_vop3mods),
        // (fminnum_ieee:{ *:[f32] } (fmaxnum_ieee:{ *:[f32] } (VOP3Mods:{ *:[f32] } f32:{ *:[f32] }:$src2, i32:{ *:[i32] }:$src2_mods), (fminnum:{ *:[f32] } (VOP3Mods:{ *:[f32] } f32:{ *:[f32] }:$src1, i32:{ *:[i32] }:$src1_mods), (VOP3Mods:{ *:[f32] } f32:{ *:[f32] }:$src0, i32:{ *:[i32] }:$src0_mods))), (fmaxnum:{ *:[f32] } (VOP3Mods:{ *:[f32] } f32:{ *:[f32] }:$src1, i32:{ *:[i32] }:$src1_mods), (VOP3Mods:{ *:[f32] } f32:{ *:[f32] }:$src0, i32:{ *:[i32] }:$src0_mods)))<<P:Predicate_fminnum_like_nnan>>  =>  (V_MED3_F32_e64:{ *:[f32] } ?:{ *:[i32] }:$src0_mods, ?:{ *:[f32] }:$src0, ?:{ *:[i32] }:$src1_mods, ?:{ *:[f32] }:$src1, ?:{ *:[i32] }:$src2_mods, ?:{ *:[f32] }:$src2, 0:{ *:[i1] }, 0:{ *:[i32] })
        GIR_BuildMI, /*InsnID*/0, /*Opcode*/GIMT_Encode2(AMDGPU::V_MED3_F32_e64),
        GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/0, // DstI[vdst]
        GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(2), /*SubOperand*/1, // src0_mods
        GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(2), /*SubOperand*/0, // src0
        GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(1), /*SubOperand*/1, // src1_mods
        GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(1), /*SubOperand*/0, // src1
        GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/1, // src2_mods
        GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/0, // src2
        GIR_AddImm8, /*InsnID*/0, /*Imm*/0,
        GIR_AddImm8, /*InsnID*/0, /*Imm*/0,
        GIR_ConstrainSelectedInstOperands, /*InsnID*/0,
        GIR_EraseFromParent, /*InsnID*/0,
        // GIR_Coverage, 10329,
        GIR_Done,
      // Label 4870: @341517
      GIM_Try, /*On fail goto*//*Label 4871*/ GIMT_Encode4(341657), // Rule ID 10266 //
        GIM_CheckRegBankForClass, /*MI*/0, /*Op*/0, /*RC*/GIMT_Encode2(AMDGPU::VGPR_32RegClassID),
        GIM_RecordInsn, /*DefineMI*/1, /*MI*/0, /*OpIdx*/1, // MIs[1]
        GIM_CheckOpcode, /*MI*/1, GIMT_Encode2(TargetOpcode::G_FMAXNUM_IEEE),
        GIM_CheckType, /*MI*/1, /*Op*/1, /*Type*/GILLT_s32,
        GIM_CheckType, /*MI*/1, /*Op*/2, /*Type*/GILLT_s32,
        GIM_RecordInsn, /*DefineMI*/2, /*MI*/1, /*OpIdx*/2, // MIs[2]
        GIM_CheckOpcode, /*MI*/2, GIMT_Encode2(TargetOpcode::G_FMINNUM),
        GIM_CheckType, /*MI*/2, /*Op*/1, /*Type*/GILLT_s32,
        GIM_CheckType, /*MI*/2, /*Op*/2, /*Type*/GILLT_s32,
        GIM_RecordInsn, /*DefineMI*/3, /*MI*/0, /*OpIdx*/2, // MIs[3]
        GIM_CheckOpcode, /*MI*/3, GIMT_Encode2(TargetOpcode::G_FMAXNUM_IEEE),
        // MIs[3] VOP3Mods:src0:src0_mods
        GIM_CheckIsSameOperand, /*MI*/3, /*OpIdx*/1, /*OtherMI*/2, /*OtherOpIdx*/1,
        // MIs[3] VOP3Mods:src1:src1_mods
        GIM_CheckIsSameOperand, /*MI*/3, /*OpIdx*/2, /*OtherMI*/2, /*OtherOpIdx*/2,
        GIM_CheckCxxInsnPredicate, /*MI*/0, /*FnId*/GIMT_Encode2(GICXXPred_MI_Predicate_fminnum_like_nnan),
        GIM_CheckIsSafeToFold, /*InsnID*/1,
        GIM_CheckIsSafeToFold, /*InsnID*/2,
        GIM_CheckIsSafeToFold, /*InsnID*/3,
        GIM_CheckComplexPattern, /*MI*/1, /*Op*/1, /*Renderer*/GIMT_Encode2(0), GIMT_Encode2(GICP_gi_vop3mods),
        GIM_CheckComplexPattern, /*MI*/2, /*Op*/1, /*Renderer*/GIMT_Encode2(1), GIMT_Encode2(GICP_gi_vop3mods),
        GIM_CheckComplexPattern, /*MI*/2, /*Op*/2, /*Renderer*/GIMT_Encode2(2), GIMT_Encode2(GICP_gi_vop3mods),
        // (fminnum_ieee:{ *:[f32] } (fmaxnum_ieee:{ *:[f32] } (VOP3Mods:{ *:[f32] } f32:{ *:[f32] }:$src2, i32:{ *:[i32] }:$src2_mods), (fminnum:{ *:[f32] } (VOP3Mods:{ *:[f32] } f32:{ *:[f32] }:$src0, i32:{ *:[i32] }:$src0_mods), (VOP3Mods:{ *:[f32] } f32:{ *:[f32] }:$src1, i32:{ *:[i32] }:$src1_mods))), (fmaxnum_ieee:{ *:[f32] } (VOP3Mods:{ *:[f32] } f32:{ *:[f32] }:$src0, i32:{ *:[i32] }:$src0_mods), (VOP3Mods:{ *:[f32] } f32:{ *:[f32] }:$src1, i32:{ *:[i32] }:$src1_mods)))<<P:Predicate_fminnum_like_nnan>>  =>  (V_MED3_F32_e64:{ *:[f32] } ?:{ *:[i32] }:$src0_mods, ?:{ *:[f32] }:$src0, ?:{ *:[i32] }:$src1_mods, ?:{ *:[f32] }:$src1, ?:{ *:[i32] }:$src2_mods, ?:{ *:[f32] }:$src2, 0:{ *:[i1] }, 0:{ *:[i32] })
        GIR_BuildMI, /*InsnID*/0, /*Opcode*/GIMT_Encode2(AMDGPU::V_MED3_F32_e64),
        GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/0, // DstI[vdst]
        GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(1), /*SubOperand*/1, // src0_mods
        GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(1), /*SubOperand*/0, // src0
        GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(2), /*SubOperand*/1, // src1_mods
        GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(2), /*SubOperand*/0, // src1
        GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/1, // src2_mods
        GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/0, // src2
        GIR_AddImm8, /*InsnID*/0, /*Imm*/0,
        GIR_AddImm8, /*InsnID*/0, /*Imm*/0,
        GIR_ConstrainSelectedInstOperands, /*InsnID*/0,
        GIR_EraseFromParent, /*InsnID*/0,
        // GIR_Coverage, 10266,
        GIR_Done,
      // Label 4871: @341657
      GIM_Try, /*On fail goto*//*Label 4872*/ GIMT_Encode4(341797), // Rule ID 10267 //
        GIM_CheckRegBankForClass, /*MI*/0, /*Op*/0, /*RC*/GIMT_Encode2(AMDGPU::VGPR_32RegClassID),
        GIM_RecordInsn, /*DefineMI*/1, /*MI*/0, /*OpIdx*/1, // MIs[1]
        GIM_CheckOpcode, /*MI*/1, GIMT_Encode2(TargetOpcode::G_FMAXNUM_IEEE),
        GIM_CheckType, /*MI*/1, /*Op*/1, /*Type*/GILLT_s32,
        GIM_CheckType, /*MI*/1, /*Op*/2, /*Type*/GILLT_s32,
        GIM_RecordInsn, /*DefineMI*/2, /*MI*/1, /*OpIdx*/2, // MIs[2]
        GIM_CheckOpcode, /*MI*/2, GIMT_Encode2(TargetOpcode::G_FMINNUM),
        GIM_CheckType, /*MI*/2, /*Op*/1, /*Type*/GILLT_s32,
        GIM_CheckType, /*MI*/2, /*Op*/2, /*Type*/GILLT_s32,
        GIM_RecordInsn, /*DefineMI*/3, /*MI*/0, /*OpIdx*/2, // MIs[3]
        GIM_CheckOpcode, /*MI*/3, GIMT_Encode2(TargetOpcode::G_FMAXNUM_IEEE),
        // MIs[3] VOP3Mods:src1:src1_mods
        GIM_CheckIsSameOperand, /*MI*/3, /*OpIdx*/1, /*OtherMI*/2, /*OtherOpIdx*/2,
        // MIs[3] VOP3Mods:src0:src0_mods
        GIM_CheckIsSameOperand, /*MI*/3, /*OpIdx*/2, /*OtherMI*/2, /*OtherOpIdx*/1,
        GIM_CheckCxxInsnPredicate, /*MI*/0, /*FnId*/GIMT_Encode2(GICXXPred_MI_Predicate_fminnum_like_nnan),
        GIM_CheckIsSafeToFold, /*InsnID*/1,
        GIM_CheckIsSafeToFold, /*InsnID*/2,
        GIM_CheckIsSafeToFold, /*InsnID*/3,
        GIM_CheckComplexPattern, /*MI*/1, /*Op*/1, /*Renderer*/GIMT_Encode2(0), GIMT_Encode2(GICP_gi_vop3mods),
        GIM_CheckComplexPattern, /*MI*/2, /*Op*/1, /*Renderer*/GIMT_Encode2(1), GIMT_Encode2(GICP_gi_vop3mods),
        GIM_CheckComplexPattern, /*MI*/2, /*Op*/2, /*Renderer*/GIMT_Encode2(2), GIMT_Encode2(GICP_gi_vop3mods),
        // (fminnum_ieee:{ *:[f32] } (fmaxnum_ieee:{ *:[f32] } (VOP3Mods:{ *:[f32] } f32:{ *:[f32] }:$src2, i32:{ *:[i32] }:$src2_mods), (fminnum:{ *:[f32] } (VOP3Mods:{ *:[f32] } f32:{ *:[f32] }:$src0, i32:{ *:[i32] }:$src0_mods), (VOP3Mods:{ *:[f32] } f32:{ *:[f32] }:$src1, i32:{ *:[i32] }:$src1_mods))), (fmaxnum_ieee:{ *:[f32] } (VOP3Mods:{ *:[f32] } f32:{ *:[f32] }:$src1, i32:{ *:[i32] }:$src1_mods), (VOP3Mods:{ *:[f32] } f32:{ *:[f32] }:$src0, i32:{ *:[i32] }:$src0_mods)))<<P:Predicate_fminnum_like_nnan>>  =>  (V_MED3_F32_e64:{ *:[f32] } ?:{ *:[i32] }:$src0_mods, ?:{ *:[f32] }:$src0, ?:{ *:[i32] }:$src1_mods, ?:{ *:[f32] }:$src1, ?:{ *:[i32] }:$src2_mods, ?:{ *:[f32] }:$src2, 0:{ *:[i1] }, 0:{ *:[i32] })
        GIR_BuildMI, /*InsnID*/0, /*Opcode*/GIMT_Encode2(AMDGPU::V_MED3_F32_e64),
        GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/0, // DstI[vdst]
        GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(1), /*SubOperand*/1, // src0_mods
        GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(1), /*SubOperand*/0, // src0
        GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(2), /*SubOperand*/1, // src1_mods
        GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(2), /*SubOperand*/0, // src1
        GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/1, // src2_mods
        GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/0, // src2
        GIR_AddImm8, /*InsnID*/0, /*Imm*/0,
        GIR_AddImm8, /*InsnID*/0, /*Imm*/0,
        GIR_ConstrainSelectedInstOperands, /*InsnID*/0,
        GIR_EraseFromParent, /*InsnID*/0,
        // GIR_Coverage, 10267,
        GIR_Done,
      // Label 4872: @341797
      GIM_Try, /*On fail goto*//*Label 4873*/ GIMT_Encode4(341937), // Rule ID 10268 //
        GIM_CheckRegBankForClass, /*MI*/0, /*Op*/0, /*RC*/GIMT_Encode2(AMDGPU::VGPR_32RegClassID),
        GIM_RecordInsn, /*DefineMI*/1, /*MI*/0, /*OpIdx*/1, // MIs[1]
        GIM_CheckOpcode, /*MI*/1, GIMT_Encode2(TargetOpcode::G_FMAXNUM_IEEE),
        GIM_CheckType, /*MI*/1, /*Op*/1, /*Type*/GILLT_s32,
        GIM_CheckType, /*MI*/1, /*Op*/2, /*Type*/GILLT_s32,
        GIM_RecordInsn, /*DefineMI*/2, /*MI*/1, /*OpIdx*/2, // MIs[2]
        GIM_CheckOpcode, /*MI*/2, GIMT_Encode2(TargetOpcode::G_FMINNUM),
        GIM_CheckType, /*MI*/2, /*Op*/1, /*Type*/GILLT_s32,
        GIM_CheckType, /*MI*/2, /*Op*/2, /*Type*/GILLT_s32,
        GIM_RecordInsn, /*DefineMI*/3, /*MI*/0, /*OpIdx*/2, // MIs[3]
        GIM_CheckOpcode, /*MI*/3, GIMT_Encode2(TargetOpcode::G_FMAXNUM_IEEE),
        // MIs[3] VOP3Mods:src0:src0_mods
        GIM_CheckIsSameOperand, /*MI*/3, /*OpIdx*/1, /*OtherMI*/2, /*OtherOpIdx*/2,
        // MIs[3] VOP3Mods:src1:src1_mods
        GIM_CheckIsSameOperand, /*MI*/3, /*OpIdx*/2, /*OtherMI*/2, /*OtherOpIdx*/1,
        GIM_CheckCxxInsnPredicate, /*MI*/0, /*FnId*/GIMT_Encode2(GICXXPred_MI_Predicate_fminnum_like_nnan),
        GIM_CheckIsSafeToFold, /*InsnID*/1,
        GIM_CheckIsSafeToFold, /*InsnID*/2,
        GIM_CheckIsSafeToFold, /*InsnID*/3,
        GIM_CheckComplexPattern, /*MI*/1, /*Op*/1, /*Renderer*/GIMT_Encode2(0), GIMT_Encode2(GICP_gi_vop3mods),
        GIM_CheckComplexPattern, /*MI*/2, /*Op*/1, /*Renderer*/GIMT_Encode2(1), GIMT_Encode2(GICP_gi_vop3mods),
        GIM_CheckComplexPattern, /*MI*/2, /*Op*/2, /*Renderer*/GIMT_Encode2(2), GIMT_Encode2(GICP_gi_vop3mods),
        // (fminnum_ieee:{ *:[f32] } (fmaxnum_ieee:{ *:[f32] } (VOP3Mods:{ *:[f32] } f32:{ *:[f32] }:$src2, i32:{ *:[i32] }:$src2_mods), (fminnum:{ *:[f32] } (VOP3Mods:{ *:[f32] } f32:{ *:[f32] }:$src1, i32:{ *:[i32] }:$src1_mods), (VOP3Mods:{ *:[f32] } f32:{ *:[f32] }:$src0, i32:{ *:[i32] }:$src0_mods))), (fmaxnum_ieee:{ *:[f32] } (VOP3Mods:{ *:[f32] } f32:{ *:[f32] }:$src0, i32:{ *:[i32] }:$src0_mods), (VOP3Mods:{ *:[f32] } f32:{ *:[f32] }:$src1, i32:{ *:[i32] }:$src1_mods)))<<P:Predicate_fminnum_like_nnan>>  =>  (V_MED3_F32_e64:{ *:[f32] } ?:{ *:[i32] }:$src0_mods, ?:{ *:[f32] }:$src0, ?:{ *:[i32] }:$src1_mods, ?:{ *:[f32] }:$src1, ?:{ *:[i32] }:$src2_mods, ?:{ *:[f32] }:$src2, 0:{ *:[i1] }, 0:{ *:[i32] })
        GIR_BuildMI, /*InsnID*/0, /*Opcode*/GIMT_Encode2(AMDGPU::V_MED3_F32_e64),
        GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/0, // DstI[vdst]
        GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(2), /*SubOperand*/1, // src0_mods
        GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(2), /*SubOperand*/0, // src0
        GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(1), /*SubOperand*/1, // src1_mods
        GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(1), /*SubOperand*/0, // src1
        GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/1, // src2_mods
        GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/0, // src2
        GIR_AddImm8, /*InsnID*/0, /*Imm*/0,
        GIR_AddImm8, /*InsnID*/0, /*Imm*/0,
        GIR_ConstrainSelectedInstOperands, /*InsnID*/0,
        GIR_EraseFromParent, /*InsnID*/0,
        // GIR_Coverage, 10268,
        GIR_Done,
      // Label 4873: @341937
      GIM_Try, /*On fail goto*//*Label 4874*/ GIMT_Encode4(342077), // Rule ID 10269 //
        GIM_CheckRegBankForClass, /*MI*/0, /*Op*/0, /*RC*/GIMT_Encode2(AMDGPU::VGPR_32RegClassID),
        GIM_RecordInsn, /*DefineMI*/1, /*MI*/0, /*OpIdx*/1, // MIs[1]
        GIM_CheckOpcode, /*MI*/1, GIMT_Encode2(TargetOpcode::G_FMAXNUM_IEEE),
        GIM_CheckType, /*MI*/1, /*Op*/1, /*Type*/GILLT_s32,
        GIM_CheckType, /*MI*/1, /*Op*/2, /*Type*/GILLT_s32,
        GIM_RecordInsn, /*DefineMI*/2, /*MI*/1, /*OpIdx*/2, // MIs[2]
        GIM_CheckOpcode, /*MI*/2, GIMT_Encode2(TargetOpcode::G_FMINNUM),
        GIM_CheckType, /*MI*/2, /*Op*/1, /*Type*/GILLT_s32,
        GIM_CheckType, /*MI*/2, /*Op*/2, /*Type*/GILLT_s32,
        GIM_RecordInsn, /*DefineMI*/3, /*MI*/0, /*OpIdx*/2, // MIs[3]
        GIM_CheckOpcode, /*MI*/3, GIMT_Encode2(TargetOpcode::G_FMAXNUM_IEEE),
        // MIs[3] VOP3Mods:src1:src1_mods
        GIM_CheckIsSameOperand, /*MI*/3, /*OpIdx*/1, /*OtherMI*/2, /*OtherOpIdx*/1,
        // MIs[3] VOP3Mods:src0:src0_mods
        GIM_CheckIsSameOperand, /*MI*/3, /*OpIdx*/2, /*OtherMI*/2, /*OtherOpIdx*/2,
        GIM_CheckCxxInsnPredicate, /*MI*/0, /*FnId*/GIMT_Encode2(GICXXPred_MI_Predicate_fminnum_like_nnan),
        GIM_CheckIsSafeToFold, /*InsnID*/1,
        GIM_CheckIsSafeToFold, /*InsnID*/2,
        GIM_CheckIsSafeToFold, /*InsnID*/3,
        GIM_CheckComplexPattern, /*MI*/1, /*Op*/1, /*Renderer*/GIMT_Encode2(0), GIMT_Encode2(GICP_gi_vop3mods),
        GIM_CheckComplexPattern, /*MI*/2, /*Op*/1, /*Renderer*/GIMT_Encode2(1), GIMT_Encode2(GICP_gi_vop3mods),
        GIM_CheckComplexPattern, /*MI*/2, /*Op*/2, /*Renderer*/GIMT_Encode2(2), GIMT_Encode2(GICP_gi_vop3mods),
        // (fminnum_ieee:{ *:[f32] } (fmaxnum_ieee:{ *:[f32] } (VOP3Mods:{ *:[f32] } f32:{ *:[f32] }:$src2, i32:{ *:[i32] }:$src2_mods), (fminnum:{ *:[f32] } (VOP3Mods:{ *:[f32] } f32:{ *:[f32] }:$src1, i32:{ *:[i32] }:$src1_mods), (VOP3Mods:{ *:[f32] } f32:{ *:[f32] }:$src0, i32:{ *:[i32] }:$src0_mods))), (fmaxnum_ieee:{ *:[f32] } (VOP3Mods:{ *:[f32] } f32:{ *:[f32] }:$src1, i32:{ *:[i32] }:$src1_mods), (VOP3Mods:{ *:[f32] } f32:{ *:[f32] }:$src0, i32:{ *:[i32] }:$src0_mods)))<<P:Predicate_fminnum_like_nnan>>  =>  (V_MED3_F32_e64:{ *:[f32] } ?:{ *:[i32] }:$src0_mods, ?:{ *:[f32] }:$src0, ?:{ *:[i32] }:$src1_mods, ?:{ *:[f32] }:$src1, ?:{ *:[i32] }:$src2_mods, ?:{ *:[f32] }:$src2, 0:{ *:[i1] }, 0:{ *:[i32] })
        GIR_BuildMI, /*InsnID*/0, /*Opcode*/GIMT_Encode2(AMDGPU::V_MED3_F32_e64),
        GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/0, // DstI[vdst]
        GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(2), /*SubOperand*/1, // src0_mods
        GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(2), /*SubOperand*/0, // src0
        GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(1), /*SubOperand*/1, // src1_mods
        GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(1), /*SubOperand*/0, // src1
        GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/1, // src2_mods
        GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/0, // src2
        GIR_AddImm8, /*InsnID*/0, /*Imm*/0,
        GIR_AddImm8, /*InsnID*/0, /*Imm*/0,
        GIR_ConstrainSelectedInstOperands, /*InsnID*/0,
        GIR_EraseFromParent, /*InsnID*/0,
        // GIR_Coverage, 10269,
        GIR_Done,
      // Label 4874: @342077
      GIM_Try, /*On fail goto*//*Label 4875*/ GIMT_Encode4(342217), // Rule ID 10311 //
        GIM_CheckRegBankForClass, /*MI*/0, /*Op*/0, /*RC*/GIMT_Encode2(AMDGPU::VGPR_32RegClassID),
        GIM_RecordInsn, /*DefineMI*/1, /*MI*/0, /*OpIdx*/1, // MIs[1]
        GIM_CheckOpcode, /*MI*/1, GIMT_Encode2(TargetOpcode::G_FMAXNUM_IEEE),
        GIM_CheckType, /*MI*/1, /*Op*/1, /*Type*/GILLT_s32,
        GIM_CheckType, /*MI*/1, /*Op*/2, /*Type*/GILLT_s32,
        GIM_RecordInsn, /*DefineMI*/2, /*MI*/1, /*OpIdx*/2, // MIs[2]
        GIM_CheckOpcode, /*MI*/2, GIMT_Encode2(TargetOpcode::G_FMINNUM_IEEE),
        GIM_CheckType, /*MI*/2, /*Op*/1, /*Type*/GILLT_s32,
        GIM_CheckType, /*MI*/2, /*Op*/2, /*Type*/GILLT_s32,
        GIM_RecordInsn, /*DefineMI*/3, /*MI*/0, /*OpIdx*/2, // MIs[3]
        GIM_CheckOpcode, /*MI*/3, GIMT_Encode2(TargetOpcode::G_FMAXNUM),
        // MIs[3] VOP3Mods:src0:src0_mods
        GIM_CheckIsSameOperand, /*MI*/3, /*OpIdx*/1, /*OtherMI*/2, /*OtherOpIdx*/1,
        // MIs[3] VOP3Mods:src1:src1_mods
        GIM_CheckIsSameOperand, /*MI*/3, /*OpIdx*/2, /*OtherMI*/2, /*OtherOpIdx*/2,
        GIM_CheckCxxInsnPredicate, /*MI*/0, /*FnId*/GIMT_Encode2(GICXXPred_MI_Predicate_fminnum_like_nnan),
        GIM_CheckIsSafeToFold, /*InsnID*/1,
        GIM_CheckIsSafeToFold, /*InsnID*/2,
        GIM_CheckIsSafeToFold, /*InsnID*/3,
        GIM_CheckComplexPattern, /*MI*/1, /*Op*/1, /*Renderer*/GIMT_Encode2(0), GIMT_Encode2(GICP_gi_vop3mods),
        GIM_CheckComplexPattern, /*MI*/2, /*Op*/1, /*Renderer*/GIMT_Encode2(1), GIMT_Encode2(GICP_gi_vop3mods),
        GIM_CheckComplexPattern, /*MI*/2, /*Op*/2, /*Renderer*/GIMT_Encode2(2), GIMT_Encode2(GICP_gi_vop3mods),
        // (fminnum_ieee:{ *:[f32] } (fmaxnum_ieee:{ *:[f32] } (VOP3Mods:{ *:[f32] } f32:{ *:[f32] }:$src2, i32:{ *:[i32] }:$src2_mods), (fminnum_ieee:{ *:[f32] } (VOP3Mods:{ *:[f32] } f32:{ *:[f32] }:$src0, i32:{ *:[i32] }:$src0_mods), (VOP3Mods:{ *:[f32] } f32:{ *:[f32] }:$src1, i32:{ *:[i32] }:$src1_mods))), (fmaxnum:{ *:[f32] } (VOP3Mods:{ *:[f32] } f32:{ *:[f32] }:$src0, i32:{ *:[i32] }:$src0_mods), (VOP3Mods:{ *:[f32] } f32:{ *:[f32] }:$src1, i32:{ *:[i32] }:$src1_mods)))<<P:Predicate_fminnum_like_nnan>>  =>  (V_MED3_F32_e64:{ *:[f32] } ?:{ *:[i32] }:$src0_mods, ?:{ *:[f32] }:$src0, ?:{ *:[i32] }:$src1_mods, ?:{ *:[f32] }:$src1, ?:{ *:[i32] }:$src2_mods, ?:{ *:[f32] }:$src2, 0:{ *:[i1] }, 0:{ *:[i32] })
        GIR_BuildMI, /*InsnID*/0, /*Opcode*/GIMT_Encode2(AMDGPU::V_MED3_F32_e64),
        GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/0, // DstI[vdst]
        GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(1), /*SubOperand*/1, // src0_mods
        GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(1), /*SubOperand*/0, // src0
        GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(2), /*SubOperand*/1, // src1_mods
        GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(2), /*SubOperand*/0, // src1
        GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/1, // src2_mods
        GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/0, // src2
        GIR_AddImm8, /*InsnID*/0, /*Imm*/0,
        GIR_AddImm8, /*InsnID*/0, /*Imm*/0,
        GIR_ConstrainSelectedInstOperands, /*InsnID*/0,
        GIR_EraseFromParent, /*InsnID*/0,
        // GIR_Coverage, 10311,
        GIR_Done,
      // Label 4875: @342217
      GIM_Try, /*On fail goto*//*Label 4876*/ GIMT_Encode4(342357), // Rule ID 10312 //
        GIM_CheckRegBankForClass, /*MI*/0, /*Op*/0, /*RC*/GIMT_Encode2(AMDGPU::VGPR_32RegClassID),
        GIM_RecordInsn, /*DefineMI*/1, /*MI*/0, /*OpIdx*/1, // MIs[1]
        GIM_CheckOpcode, /*MI*/1, GIMT_Encode2(TargetOpcode::G_FMAXNUM_IEEE),
        GIM_CheckType, /*MI*/1, /*Op*/1, /*Type*/GILLT_s32,
        GIM_CheckType, /*MI*/1, /*Op*/2, /*Type*/GILLT_s32,
        GIM_RecordInsn, /*DefineMI*/2, /*MI*/1, /*OpIdx*/2, // MIs[2]
        GIM_CheckOpcode, /*MI*/2, GIMT_Encode2(TargetOpcode::G_FMINNUM_IEEE),
        GIM_CheckType, /*MI*/2, /*Op*/1, /*Type*/GILLT_s32,
        GIM_CheckType, /*MI*/2, /*Op*/2, /*Type*/GILLT_s32,
        GIM_RecordInsn, /*DefineMI*/3, /*MI*/0, /*OpIdx*/2, // MIs[3]
        GIM_CheckOpcode, /*MI*/3, GIMT_Encode2(TargetOpcode::G_FMAXNUM),
        // MIs[3] VOP3Mods:src1:src1_mods
        GIM_CheckIsSameOperand, /*MI*/3, /*OpIdx*/1, /*OtherMI*/2, /*OtherOpIdx*/2,
        // MIs[3] VOP3Mods:src0:src0_mods
        GIM_CheckIsSameOperand, /*MI*/3, /*OpIdx*/2, /*OtherMI*/2, /*OtherOpIdx*/1,
        GIM_CheckCxxInsnPredicate, /*MI*/0, /*FnId*/GIMT_Encode2(GICXXPred_MI_Predicate_fminnum_like_nnan),
        GIM_CheckIsSafeToFold, /*InsnID*/1,
        GIM_CheckIsSafeToFold, /*InsnID*/2,
        GIM_CheckIsSafeToFold, /*InsnID*/3,
        GIM_CheckComplexPattern, /*MI*/1, /*Op*/1, /*Renderer*/GIMT_Encode2(0), GIMT_Encode2(GICP_gi_vop3mods),
        GIM_CheckComplexPattern, /*MI*/2, /*Op*/1, /*Renderer*/GIMT_Encode2(1), GIMT_Encode2(GICP_gi_vop3mods),
        GIM_CheckComplexPattern, /*MI*/2, /*Op*/2, /*Renderer*/GIMT_Encode2(2), GIMT_Encode2(GICP_gi_vop3mods),
        // (fminnum_ieee:{ *:[f32] } (fmaxnum_ieee:{ *:[f32] } (VOP3Mods:{ *:[f32] } f32:{ *:[f32] }:$src2, i32:{ *:[i32] }:$src2_mods), (fminnum_ieee:{ *:[f32] } (VOP3Mods:{ *:[f32] } f32:{ *:[f32] }:$src0, i32:{ *:[i32] }:$src0_mods), (VOP3Mods:{ *:[f32] } f32:{ *:[f32] }:$src1, i32:{ *:[i32] }:$src1_mods))), (fmaxnum:{ *:[f32] } (VOP3Mods:{ *:[f32] } f32:{ *:[f32] }:$src1, i32:{ *:[i32] }:$src1_mods), (VOP3Mods:{ *:[f32] } f32:{ *:[f32] }:$src0, i32:{ *:[i32] }:$src0_mods)))<<P:Predicate_fminnum_like_nnan>>  =>  (V_MED3_F32_e64:{ *:[f32] } ?:{ *:[i32] }:$src0_mods, ?:{ *:[f32] }:$src0, ?:{ *:[i32] }:$src1_mods, ?:{ *:[f32] }:$src1, ?:{ *:[i32] }:$src2_mods, ?:{ *:[f32] }:$src2, 0:{ *:[i1] }, 0:{ *:[i32] })
        GIR_BuildMI, /*InsnID*/0, /*Opcode*/GIMT_Encode2(AMDGPU::V_MED3_F32_e64),
        GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/0, // DstI[vdst]
        GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(1), /*SubOperand*/1, // src0_mods
        GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(1), /*SubOperand*/0, // src0
        GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(2), /*SubOperand*/1, // src1_mods
        GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(2), /*SubOperand*/0, // src1
        GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/1, // src2_mods
        GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/0, // src2
        GIR_AddImm8, /*InsnID*/0, /*Imm*/0,
        GIR_AddImm8, /*InsnID*/0, /*Imm*/0,
        GIR_ConstrainSelectedInstOperands, /*InsnID*/0,
        GIR_EraseFromParent, /*InsnID*/0,
        // GIR_Coverage, 10312,
        GIR_Done,
      // Label 4876: @342357
      GIM_Try, /*On fail goto*//*Label 4877*/ GIMT_Encode4(342497), // Rule ID 10313 //
        GIM_CheckRegBankForClass, /*MI*/0, /*Op*/0, /*RC*/GIMT_Encode2(AMDGPU::VGPR_32RegClassID),
        GIM_RecordInsn, /*DefineMI*/1, /*MI*/0, /*OpIdx*/1, // MIs[1]
        GIM_CheckOpcode, /*MI*/1, GIMT_Encode2(TargetOpcode::G_FMAXNUM_IEEE),
        GIM_CheckType, /*MI*/1, /*Op*/1, /*Type*/GILLT_s32,
        GIM_CheckType, /*MI*/1, /*Op*/2, /*Type*/GILLT_s32,
        GIM_RecordInsn, /*DefineMI*/2, /*MI*/1, /*OpIdx*/2, // MIs[2]
        GIM_CheckOpcode, /*MI*/2, GIMT_Encode2(TargetOpcode::G_FMINNUM_IEEE),
        GIM_CheckType, /*MI*/2, /*Op*/1, /*Type*/GILLT_s32,
        GIM_CheckType, /*MI*/2, /*Op*/2, /*Type*/GILLT_s32,
        GIM_RecordInsn, /*DefineMI*/3, /*MI*/0, /*OpIdx*/2, // MIs[3]
        GIM_CheckOpcode, /*MI*/3, GIMT_Encode2(TargetOpcode::G_FMAXNUM),
        // MIs[3] VOP3Mods:src0:src0_mods
        GIM_CheckIsSameOperand, /*MI*/3, /*OpIdx*/1, /*OtherMI*/2, /*OtherOpIdx*/2,
        // MIs[3] VOP3Mods:src1:src1_mods
        GIM_CheckIsSameOperand, /*MI*/3, /*OpIdx*/2, /*OtherMI*/2, /*OtherOpIdx*/1,
        GIM_CheckCxxInsnPredicate, /*MI*/0, /*FnId*/GIMT_Encode2(GICXXPred_MI_Predicate_fminnum_like_nnan),
        GIM_CheckIsSafeToFold, /*InsnID*/1,
        GIM_CheckIsSafeToFold, /*InsnID*/2,
        GIM_CheckIsSafeToFold, /*InsnID*/3,
        GIM_CheckComplexPattern, /*MI*/1, /*Op*/1, /*Renderer*/GIMT_Encode2(0), GIMT_Encode2(GICP_gi_vop3mods),
        GIM_CheckComplexPattern, /*MI*/2, /*Op*/1, /*Renderer*/GIMT_Encode2(1), GIMT_Encode2(GICP_gi_vop3mods),
        GIM_CheckComplexPattern, /*MI*/2, /*Op*/2, /*Renderer*/GIMT_Encode2(2), GIMT_Encode2(GICP_gi_vop3mods),
        // (fminnum_ieee:{ *:[f32] } (fmaxnum_ieee:{ *:[f32] } (VOP3Mods:{ *:[f32] } f32:{ *:[f32] }:$src2, i32:{ *:[i32] }:$src2_mods), (fminnum_ieee:{ *:[f32] } (VOP3Mods:{ *:[f32] } f32:{ *:[f32] }:$src1, i32:{ *:[i32] }:$src1_mods), (VOP3Mods:{ *:[f32] } f32:{ *:[f32] }:$src0, i32:{ *:[i32] }:$src0_mods))), (fmaxnum:{ *:[f32] } (VOP3Mods:{ *:[f32] } f32:{ *:[f32] }:$src0, i32:{ *:[i32] }:$src0_mods), (VOP3Mods:{ *:[f32] } f32:{ *:[f32] }:$src1, i32:{ *:[i32] }:$src1_mods)))<<P:Predicate_fminnum_like_nnan>>  =>  (V_MED3_F32_e64:{ *:[f32] } ?:{ *:[i32] }:$src0_mods, ?:{ *:[f32] }:$src0, ?:{ *:[i32] }:$src1_mods, ?:{ *:[f32] }:$src1, ?:{ *:[i32] }:$src2_mods, ?:{ *:[f32] }:$src2, 0:{ *:[i1] }, 0:{ *:[i32] })
        GIR_BuildMI, /*InsnID*/0, /*Opcode*/GIMT_Encode2(AMDGPU::V_MED3_F32_e64),
        GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/0, // DstI[vdst]
        GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(2), /*SubOperand*/1, // src0_mods
        GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(2), /*SubOperand*/0, // src0
        GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(1), /*SubOperand*/1, // src1_mods
        GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(1), /*SubOperand*/0, // src1
        GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/1, // src2_mods
        GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/0, // src2
        GIR_AddImm8, /*InsnID*/0, /*Imm*/0,
        GIR_AddImm8, /*InsnID*/0, /*Imm*/0,
        GIR_ConstrainSelectedInstOperands, /*InsnID*/0,
        GIR_EraseFromParent, /*InsnID*/0,
        // GIR_Coverage, 10313,
        GIR_Done,
      // Label 4877: @342497
      GIM_Try, /*On fail goto*//*Label 4878*/ GIMT_Encode4(342637), // Rule ID 10314 //
        GIM_CheckRegBankForClass, /*MI*/0, /*Op*/0, /*RC*/GIMT_Encode2(AMDGPU::VGPR_32RegClassID),
        GIM_RecordInsn, /*DefineMI*/1, /*MI*/0, /*OpIdx*/1, // MIs[1]
        GIM_CheckOpcode, /*MI*/1, GIMT_Encode2(TargetOpcode::G_FMAXNUM_IEEE),
        GIM_CheckType, /*MI*/1, /*Op*/1, /*Type*/GILLT_s32,
        GIM_CheckType, /*MI*/1, /*Op*/2, /*Type*/GILLT_s32,
        GIM_RecordInsn, /*DefineMI*/2, /*MI*/1, /*OpIdx*/2, // MIs[2]
        GIM_CheckOpcode, /*MI*/2, GIMT_Encode2(TargetOpcode::G_FMINNUM_IEEE),
        GIM_CheckType, /*MI*/2, /*Op*/1, /*Type*/GILLT_s32,
        GIM_CheckType, /*MI*/2, /*Op*/2, /*Type*/GILLT_s32,
        GIM_RecordInsn, /*DefineMI*/3, /*MI*/0, /*OpIdx*/2, // MIs[3]
        GIM_CheckOpcode, /*MI*/3, GIMT_Encode2(TargetOpcode::G_FMAXNUM),
        // MIs[3] VOP3Mods:src1:src1_mods
        GIM_CheckIsSameOperand, /*MI*/3, /*OpIdx*/1, /*OtherMI*/2, /*OtherOpIdx*/1,
        // MIs[3] VOP3Mods:src0:src0_mods
        GIM_CheckIsSameOperand, /*MI*/3, /*OpIdx*/2, /*OtherMI*/2, /*OtherOpIdx*/2,
        GIM_CheckCxxInsnPredicate, /*MI*/0, /*FnId*/GIMT_Encode2(GICXXPred_MI_Predicate_fminnum_like_nnan),
        GIM_CheckIsSafeToFold, /*InsnID*/1,
        GIM_CheckIsSafeToFold, /*InsnID*/2,
        GIM_CheckIsSafeToFold, /*InsnID*/3,
        GIM_CheckComplexPattern, /*MI*/1, /*Op*/1, /*Renderer*/GIMT_Encode2(0), GIMT_Encode2(GICP_gi_vop3mods),
        GIM_CheckComplexPattern, /*MI*/2, /*Op*/1, /*Renderer*/GIMT_Encode2(1), GIMT_Encode2(GICP_gi_vop3mods),
        GIM_CheckComplexPattern, /*MI*/2, /*Op*/2, /*Renderer*/GIMT_Encode2(2), GIMT_Encode2(GICP_gi_vop3mods),
        // (fminnum_ieee:{ *:[f32] } (fmaxnum_ieee:{ *:[f32] } (VOP3Mods:{ *:[f32] } f32:{ *:[f32] }:$src2, i32:{ *:[i32] }:$src2_mods), (fminnum_ieee:{ *:[f32] } (VOP3Mods:{ *:[f32] } f32:{ *:[f32] }:$src1, i32:{ *:[i32] }:$src1_mods), (VOP3Mods:{ *:[f32] } f32:{ *:[f32] }:$src0, i32:{ *:[i32] }:$src0_mods))), (fmaxnum:{ *:[f32] } (VOP3Mods:{ *:[f32] } f32:{ *:[f32] }:$src1, i32:{ *:[i32] }:$src1_mods), (VOP3Mods:{ *:[f32] } f32:{ *:[f32] }:$src0, i32:{ *:[i32] }:$src0_mods)))<<P:Predicate_fminnum_like_nnan>>  =>  (V_MED3_F32_e64:{ *:[f32] } ?:{ *:[i32] }:$src0_mods, ?:{ *:[f32] }:$src0, ?:{ *:[i32] }:$src1_mods, ?:{ *:[f32] }:$src1, ?:{ *:[i32] }:$src2_mods, ?:{ *:[f32] }:$src2, 0:{ *:[i1] }, 0:{ *:[i32] })
        GIR_BuildMI, /*InsnID*/0, /*Opcode*/GIMT_Encode2(AMDGPU::V_MED3_F32_e64),
        GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/0, // DstI[vdst]
        GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(2), /*SubOperand*/1, // src0_mods
        GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(2), /*SubOperand*/0, // src0
        GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(1), /*SubOperand*/1, // src1_mods
        GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(1), /*SubOperand*/0, // src1
        GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/1, // src2_mods
        GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/0, // src2
        GIR_AddImm8, /*InsnID*/0, /*Imm*/0,
        GIR_AddImm8, /*InsnID*/0, /*Imm*/0,
        GIR_ConstrainSelectedInstOperands, /*InsnID*/0,
        GIR_EraseFromParent, /*InsnID*/0,
        // GIR_Coverage, 10314,
        GIR_Done,
      // Label 4878: @342637
      GIM_Try, /*On fail goto*//*Label 4879*/ GIMT_Encode4(342777), // Rule ID 10251 //
        GIM_CheckRegBankForClass, /*MI*/0, /*Op*/0, /*RC*/GIMT_Encode2(AMDGPU::VGPR_32RegClassID),
        GIM_RecordInsn, /*DefineMI*/1, /*MI*/0, /*OpIdx*/1, // MIs[1]
        GIM_CheckOpcode, /*MI*/1, GIMT_Encode2(TargetOpcode::G_FMAXNUM_IEEE),
        GIM_CheckType, /*MI*/1, /*Op*/1, /*Type*/GILLT_s32,
        GIM_CheckType, /*MI*/1, /*Op*/2, /*Type*/GILLT_s32,
        GIM_RecordInsn, /*DefineMI*/2, /*MI*/1, /*OpIdx*/2, // MIs[2]
        GIM_CheckOpcode, /*MI*/2, GIMT_Encode2(TargetOpcode::G_FMINNUM_IEEE),
        GIM_CheckType, /*MI*/2, /*Op*/1, /*Type*/GILLT_s32,
        GIM_CheckType, /*MI*/2, /*Op*/2, /*Type*/GILLT_s32,
        GIM_RecordInsn, /*DefineMI*/3, /*MI*/0, /*OpIdx*/2, // MIs[3]
        GIM_CheckOpcode, /*MI*/3, GIMT_Encode2(TargetOpcode::G_FMAXNUM_IEEE),
        // MIs[3] VOP3Mods:src0:src0_mods
        GIM_CheckIsSameOperand, /*MI*/3, /*OpIdx*/1, /*OtherMI*/2, /*OtherOpIdx*/1,
        // MIs[3] VOP3Mods:src1:src1_mods
        GIM_CheckIsSameOperand, /*MI*/3, /*OpIdx*/2, /*OtherMI*/2, /*OtherOpIdx*/2,
        GIM_CheckCxxInsnPredicate, /*MI*/0, /*FnId*/GIMT_Encode2(GICXXPred_MI_Predicate_fminnum_like_nnan),
        GIM_CheckIsSafeToFold, /*InsnID*/1,
        GIM_CheckIsSafeToFold, /*InsnID*/2,
        GIM_CheckIsSafeToFold, /*InsnID*/3,
        GIM_CheckComplexPattern, /*MI*/1, /*Op*/1, /*Renderer*/GIMT_Encode2(0), GIMT_Encode2(GICP_gi_vop3mods),
        GIM_CheckComplexPattern, /*MI*/2, /*Op*/1, /*Renderer*/GIMT_Encode2(1), GIMT_Encode2(GICP_gi_vop3mods),
        GIM_CheckComplexPattern, /*MI*/2, /*Op*/2, /*Renderer*/GIMT_Encode2(2), GIMT_Encode2(GICP_gi_vop3mods),
        // (fminnum_ieee:{ *:[f32] } (fmaxnum_ieee:{ *:[f32] } (VOP3Mods:{ *:[f32] } f32:{ *:[f32] }:$src2, i32:{ *:[i32] }:$src2_mods), (fminnum_ieee:{ *:[f32] } (VOP3Mods:{ *:[f32] } f32:{ *:[f32] }:$src0, i32:{ *:[i32] }:$src0_mods), (VOP3Mods:{ *:[f32] } f32:{ *:[f32] }:$src1, i32:{ *:[i32] }:$src1_mods))), (fmaxnum_ieee:{ *:[f32] } (VOP3Mods:{ *:[f32] } f32:{ *:[f32] }:$src0, i32:{ *:[i32] }:$src0_mods), (VOP3Mods:{ *:[f32] } f32:{ *:[f32] }:$src1, i32:{ *:[i32] }:$src1_mods)))<<P:Predicate_fminnum_like_nnan>>  =>  (V_MED3_F32_e64:{ *:[f32] } ?:{ *:[i32] }:$src0_mods, ?:{ *:[f32] }:$src0, ?:{ *:[i32] }:$src1_mods, ?:{ *:[f32] }:$src1, ?:{ *:[i32] }:$src2_mods, ?:{ *:[f32] }:$src2, 0:{ *:[i1] }, 0:{ *:[i32] })
        GIR_BuildMI, /*InsnID*/0, /*Opcode*/GIMT_Encode2(AMDGPU::V_MED3_F32_e64),
        GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/0, // DstI[vdst]
        GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(1), /*SubOperand*/1, // src0_mods
        GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(1), /*SubOperand*/0, // src0
        GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(2), /*SubOperand*/1, // src1_mods
        GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(2), /*SubOperand*/0, // src1
        GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/1, // src2_mods
        GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/0, // src2
        GIR_AddImm8, /*InsnID*/0, /*Imm*/0,
        GIR_AddImm8, /*InsnID*/0, /*Imm*/0,
        GIR_ConstrainSelectedInstOperands, /*InsnID*/0,
        GIR_EraseFromParent, /*InsnID*/0,
        // GIR_Coverage, 10251,
        GIR_Done,
      // Label 4879: @342777
      GIM_Try, /*On fail goto*//*Label 4880*/ GIMT_Encode4(342917), // Rule ID 10252 //
        GIM_CheckRegBankForClass, /*MI*/0, /*Op*/0, /*RC*/GIMT_Encode2(AMDGPU::VGPR_32RegClassID),
        GIM_RecordInsn, /*DefineMI*/1, /*MI*/0, /*OpIdx*/1, // MIs[1]
        GIM_CheckOpcode, /*MI*/1, GIMT_Encode2(TargetOpcode::G_FMAXNUM_IEEE),
        GIM_CheckType, /*MI*/1, /*Op*/1, /*Type*/GILLT_s32,
        GIM_CheckType, /*MI*/1, /*Op*/2, /*Type*/GILLT_s32,
        GIM_RecordInsn, /*DefineMI*/2, /*MI*/1, /*OpIdx*/2, // MIs[2]
        GIM_CheckOpcode, /*MI*/2, GIMT_Encode2(TargetOpcode::G_FMINNUM_IEEE),
        GIM_CheckType, /*MI*/2, /*Op*/1, /*Type*/GILLT_s32,
        GIM_CheckType, /*MI*/2, /*Op*/2, /*Type*/GILLT_s32,
        GIM_RecordInsn, /*DefineMI*/3, /*MI*/0, /*OpIdx*/2, // MIs[3]
        GIM_CheckOpcode, /*MI*/3, GIMT_Encode2(TargetOpcode::G_FMAXNUM_IEEE),
        // MIs[3] VOP3Mods:src1:src1_mods
        GIM_CheckIsSameOperand, /*MI*/3, /*OpIdx*/1, /*OtherMI*/2, /*OtherOpIdx*/2,
        // MIs[3] VOP3Mods:src0:src0_mods
        GIM_CheckIsSameOperand, /*MI*/3, /*OpIdx*/2, /*OtherMI*/2, /*OtherOpIdx*/1,
        GIM_CheckCxxInsnPredicate, /*MI*/0, /*FnId*/GIMT_Encode2(GICXXPred_MI_Predicate_fminnum_like_nnan),
        GIM_CheckIsSafeToFold, /*InsnID*/1,
        GIM_CheckIsSafeToFold, /*InsnID*/2,
        GIM_CheckIsSafeToFold, /*InsnID*/3,
        GIM_CheckComplexPattern, /*MI*/1, /*Op*/1, /*Renderer*/GIMT_Encode2(0), GIMT_Encode2(GICP_gi_vop3mods),
        GIM_CheckComplexPattern, /*MI*/2, /*Op*/1, /*Renderer*/GIMT_Encode2(1), GIMT_Encode2(GICP_gi_vop3mods),
        GIM_CheckComplexPattern, /*MI*/2, /*Op*/2, /*Renderer*/GIMT_Encode2(2), GIMT_Encode2(GICP_gi_vop3mods),
        // (fminnum_ieee:{ *:[f32] } (fmaxnum_ieee:{ *:[f32] } (VOP3Mods:{ *:[f32] } f32:{ *:[f32] }:$src2, i32:{ *:[i32] }:$src2_mods), (fminnum_ieee:{ *:[f32] } (VOP3Mods:{ *:[f32] } f32:{ *:[f32] }:$src0, i32:{ *:[i32] }:$src0_mods), (VOP3Mods:{ *:[f32] } f32:{ *:[f32] }:$src1, i32:{ *:[i32] }:$src1_mods))), (fmaxnum_ieee:{ *:[f32] } (VOP3Mods:{ *:[f32] } f32:{ *:[f32] }:$src1, i32:{ *:[i32] }:$src1_mods), (VOP3Mods:{ *:[f32] } f32:{ *:[f32] }:$src0, i32:{ *:[i32] }:$src0_mods)))<<P:Predicate_fminnum_like_nnan>>  =>  (V_MED3_F32_e64:{ *:[f32] } ?:{ *:[i32] }:$src0_mods, ?:{ *:[f32] }:$src0, ?:{ *:[i32] }:$src1_mods, ?:{ *:[f32] }:$src1, ?:{ *:[i32] }:$src2_mods, ?:{ *:[f32] }:$src2, 0:{ *:[i1] }, 0:{ *:[i32] })
        GIR_BuildMI, /*InsnID*/0, /*Opcode*/GIMT_Encode2(AMDGPU::V_MED3_F32_e64),
        GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/0, // DstI[vdst]
        GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(1), /*SubOperand*/1, // src0_mods
        GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(1), /*SubOperand*/0, // src0
        GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(2), /*SubOperand*/1, // src1_mods
        GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(2), /*SubOperand*/0, // src1
        GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/1, // src2_mods
        GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/0, // src2
        GIR_AddImm8, /*InsnID*/0, /*Imm*/0,
        GIR_AddImm8, /*InsnID*/0, /*Imm*/0,
        GIR_ConstrainSelectedInstOperands, /*InsnID*/0,
        GIR_EraseFromParent, /*InsnID*/0,
        // GIR_Coverage, 10252,
        GIR_Done,
      // Label 4880: @342917
      GIM_Try, /*On fail goto*//*Label 4881*/ GIMT_Encode4(343057), // Rule ID 10253 //
        GIM_CheckRegBankForClass, /*MI*/0, /*Op*/0, /*RC*/GIMT_Encode2(AMDGPU::VGPR_32RegClassID),
        GIM_RecordInsn, /*DefineMI*/1, /*MI*/0, /*OpIdx*/1, // MIs[1]
        GIM_CheckOpcode, /*MI*/1, GIMT_Encode2(TargetOpcode::G_FMAXNUM_IEEE),
        GIM_CheckType, /*MI*/1, /*Op*/1, /*Type*/GILLT_s32,
        GIM_CheckType, /*MI*/1, /*Op*/2, /*Type*/GILLT_s32,
        GIM_RecordInsn, /*DefineMI*/2, /*MI*/1, /*OpIdx*/2, // MIs[2]
        GIM_CheckOpcode, /*MI*/2, GIMT_Encode2(TargetOpcode::G_FMINNUM_IEEE),
        GIM_CheckType, /*MI*/2, /*Op*/1, /*Type*/GILLT_s32,
        GIM_CheckType, /*MI*/2, /*Op*/2, /*Type*/GILLT_s32,
        GIM_RecordInsn, /*DefineMI*/3, /*MI*/0, /*OpIdx*/2, // MIs[3]
        GIM_CheckOpcode, /*MI*/3, GIMT_Encode2(TargetOpcode::G_FMAXNUM_IEEE),
        // MIs[3] VOP3Mods:src0:src0_mods
        GIM_CheckIsSameOperand, /*MI*/3, /*OpIdx*/1, /*OtherMI*/2, /*OtherOpIdx*/2,
        // MIs[3] VOP3Mods:src1:src1_mods
        GIM_CheckIsSameOperand, /*MI*/3, /*OpIdx*/2, /*OtherMI*/2, /*OtherOpIdx*/1,
        GIM_CheckCxxInsnPredicate, /*MI*/0, /*FnId*/GIMT_Encode2(GICXXPred_MI_Predicate_fminnum_like_nnan),
        GIM_CheckIsSafeToFold, /*InsnID*/1,
        GIM_CheckIsSafeToFold, /*InsnID*/2,
        GIM_CheckIsSafeToFold, /*InsnID*/3,
        GIM_CheckComplexPattern, /*MI*/1, /*Op*/1, /*Renderer*/GIMT_Encode2(0), GIMT_Encode2(GICP_gi_vop3mods),
        GIM_CheckComplexPattern, /*MI*/2, /*Op*/1, /*Renderer*/GIMT_Encode2(1), GIMT_Encode2(GICP_gi_vop3mods),
        GIM_CheckComplexPattern, /*MI*/2, /*Op*/2, /*Renderer*/GIMT_Encode2(2), GIMT_Encode2(GICP_gi_vop3mods),
        // (fminnum_ieee:{ *:[f32] } (fmaxnum_ieee:{ *:[f32] } (VOP3Mods:{ *:[f32] } f32:{ *:[f32] }:$src2, i32:{ *:[i32] }:$src2_mods), (fminnum_ieee:{ *:[f32] } (VOP3Mods:{ *:[f32] } f32:{ *:[f32] }:$src1, i32:{ *:[i32] }:$src1_mods), (VOP3Mods:{ *:[f32] } f32:{ *:[f32] }:$src0, i32:{ *:[i32] }:$src0_mods))), (fmaxnum_ieee:{ *:[f32] } (VOP3Mods:{ *:[f32] } f32:{ *:[f32] }:$src0, i32:{ *:[i32] }:$src0_mods), (VOP3Mods:{ *:[f32] } f32:{ *:[f32] }:$src1, i32:{ *:[i32] }:$src1_mods)))<<P:Predicate_fminnum_like_nnan>>  =>  (V_MED3_F32_e64:{ *:[f32] } ?:{ *:[i32] }:$src0_mods, ?:{ *:[f32] }:$src0, ?:{ *:[i32] }:$src1_mods, ?:{ *:[f32] }:$src1, ?:{ *:[i32] }:$src2_mods, ?:{ *:[f32] }:$src2, 0:{ *:[i1] }, 0:{ *:[i32] })
        GIR_BuildMI, /*InsnID*/0, /*Opcode*/GIMT_Encode2(AMDGPU::V_MED3_F32_e64),
        GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/0, // DstI[vdst]
        GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(2), /*SubOperand*/1, // src0_mods
        GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(2), /*SubOperand*/0, // src0
        GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(1), /*SubOperand*/1, // src1_mods
        GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(1), /*SubOperand*/0, // src1
        GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/1, // src2_mods
        GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/0, // src2
        GIR_AddImm8, /*InsnID*/0, /*Imm*/0,
        GIR_AddImm8, /*InsnID*/0, /*Imm*/0,
        GIR_ConstrainSelectedInstOperands, /*InsnID*/0,
        GIR_EraseFromParent, /*InsnID*/0,
        // GIR_Coverage, 10253,
        GIR_Done,
      // Label 4881: @343057
      GIM_Try, /*On fail goto*//*Label 4882*/ GIMT_Encode4(343197), // Rule ID 10254 //
        GIM_CheckRegBankForClass, /*MI*/0, /*Op*/0, /*RC*/GIMT_Encode2(AMDGPU::VGPR_32RegClassID),
        GIM_RecordInsn, /*DefineMI*/1, /*MI*/0, /*OpIdx*/1, // MIs[1]
        GIM_CheckOpcode, /*MI*/1, GIMT_Encode2(TargetOpcode::G_FMAXNUM_IEEE),
        GIM_CheckType, /*MI*/1, /*Op*/1, /*Type*/GILLT_s32,
        GIM_CheckType, /*MI*/1, /*Op*/2, /*Type*/GILLT_s32,
        GIM_RecordInsn, /*DefineMI*/2, /*MI*/1, /*OpIdx*/2, // MIs[2]
        GIM_CheckOpcode, /*MI*/2, GIMT_Encode2(TargetOpcode::G_FMINNUM_IEEE),
        GIM_CheckType, /*MI*/2, /*Op*/1, /*Type*/GILLT_s32,
        GIM_CheckType, /*MI*/2, /*Op*/2, /*Type*/GILLT_s32,
        GIM_RecordInsn, /*DefineMI*/3, /*MI*/0, /*OpIdx*/2, // MIs[3]
        GIM_CheckOpcode, /*MI*/3, GIMT_Encode2(TargetOpcode::G_FMAXNUM_IEEE),
        // MIs[3] VOP3Mods:src1:src1_mods
        GIM_CheckIsSameOperand, /*MI*/3, /*OpIdx*/1, /*OtherMI*/2, /*OtherOpIdx*/1,
        // MIs[3] VOP3Mods:src0:src0_mods
        GIM_CheckIsSameOperand, /*MI*/3, /*OpIdx*/2, /*OtherMI*/2, /*OtherOpIdx*/2,
        GIM_CheckCxxInsnPredicate, /*MI*/0, /*FnId*/GIMT_Encode2(GICXXPred_MI_Predicate_fminnum_like_nnan),
        GIM_CheckIsSafeToFold, /*InsnID*/1,
        GIM_CheckIsSafeToFold, /*InsnID*/2,
        GIM_CheckIsSafeToFold, /*InsnID*/3,
        GIM_CheckComplexPattern, /*MI*/1, /*Op*/1, /*Renderer*/GIMT_Encode2(0), GIMT_Encode2(GICP_gi_vop3mods),
        GIM_CheckComplexPattern, /*MI*/2, /*Op*/1, /*Renderer*/GIMT_Encode2(1), GIMT_Encode2(GICP_gi_vop3mods),
        GIM_CheckComplexPattern, /*MI*/2, /*Op*/2, /*Renderer*/GIMT_Encode2(2), GIMT_Encode2(GICP_gi_vop3mods),
        // (fminnum_ieee:{ *:[f32] } (fmaxnum_ieee:{ *:[f32] } (VOP3Mods:{ *:[f32] } f32:{ *:[f32] }:$src2, i32:{ *:[i32] }:$src2_mods), (fminnum_ieee:{ *:[f32] } (VOP3Mods:{ *:[f32] } f32:{ *:[f32] }:$src1, i32:{ *:[i32] }:$src1_mods), (VOP3Mods:{ *:[f32] } f32:{ *:[f32] }:$src0, i32:{ *:[i32] }:$src0_mods))), (fmaxnum_ieee:{ *:[f32] } (VOP3Mods:{ *:[f32] } f32:{ *:[f32] }:$src1, i32:{ *:[i32] }:$src1_mods), (VOP3Mods:{ *:[f32] } f32:{ *:[f32] }:$src0, i32:{ *:[i32] }:$src0_mods)))<<P:Predicate_fminnum_like_nnan>>  =>  (V_MED3_F32_e64:{ *:[f32] } ?:{ *:[i32] }:$src0_mods, ?:{ *:[f32] }:$src0, ?:{ *:[i32] }:$src1_mods, ?:{ *:[f32] }:$src1, ?:{ *:[i32] }:$src2_mods, ?:{ *:[f32] }:$src2, 0:{ *:[i1] }, 0:{ *:[i32] })
        GIR_BuildMI, /*InsnID*/0, /*Opcode*/GIMT_Encode2(AMDGPU::V_MED3_F32_e64),
        GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/0, // DstI[vdst]
        GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(2), /*SubOperand*/1, // src0_mods
        GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(2), /*SubOperand*/0, // src0
        GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(1), /*SubOperand*/1, // src1_mods
        GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(1), /*SubOperand*/0, // src1
        GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/1, // src2_mods
        GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/0, // src2
        GIR_AddImm8, /*InsnID*/0, /*Imm*/0,
        GIR_AddImm8, /*InsnID*/0, /*Imm*/0,
        GIR_ConstrainSelectedInstOperands, /*InsnID*/0,
        GIR_EraseFromParent, /*InsnID*/0,
        // GIR_Coverage, 10254,
        GIR_Done,
      // Label 4882: @343197
      GIM_Try, /*On fail goto*//*Label 4883*/ GIMT_Encode4(343337), // Rule ID 10322 //
        GIM_CheckRegBankForClass, /*MI*/0, /*Op*/0, /*RC*/GIMT_Encode2(AMDGPU::VGPR_32RegClassID),
        GIM_RecordInsn, /*DefineMI*/1, /*MI*/0, /*OpIdx*/1, // MIs[1]
        GIM_CheckOpcode, /*MI*/1, GIMT_Encode2(TargetOpcode::G_FMAXNUM_IEEE),
        GIM_CheckType, /*MI*/1, /*Op*/1, /*Type*/GILLT_s32,
        GIM_CheckType, /*MI*/1, /*Op*/2, /*Type*/GILLT_s32,
        GIM_RecordInsn, /*DefineMI*/2, /*MI*/1, /*OpIdx*/1, // MIs[2]
        GIM_CheckOpcode, /*MI*/2, GIMT_Encode2(TargetOpcode::G_FMINNUM),
        GIM_CheckType, /*MI*/2, /*Op*/1, /*Type*/GILLT_s32,
        GIM_CheckType, /*MI*/2, /*Op*/2, /*Type*/GILLT_s32,
        GIM_RecordInsn, /*DefineMI*/3, /*MI*/0, /*OpIdx*/2, // MIs[3]
        GIM_CheckOpcode, /*MI*/3, GIMT_Encode2(TargetOpcode::G_FMAXNUM),
        // MIs[3] VOP3Mods:src0:src0_mods
        GIM_CheckIsSameOperand, /*MI*/3, /*OpIdx*/1, /*OtherMI*/2, /*OtherOpIdx*/1,
        // MIs[3] VOP3Mods:src1:src1_mods
        GIM_CheckIsSameOperand, /*MI*/3, /*OpIdx*/2, /*OtherMI*/2, /*OtherOpIdx*/2,
        GIM_CheckCxxInsnPredicate, /*MI*/0, /*FnId*/GIMT_Encode2(GICXXPred_MI_Predicate_fminnum_like_nnan),
        GIM_CheckIsSafeToFold, /*InsnID*/1,
        GIM_CheckIsSafeToFold, /*InsnID*/2,
        GIM_CheckIsSafeToFold, /*InsnID*/3,
        GIM_CheckComplexPattern, /*MI*/1, /*Op*/2, /*Renderer*/GIMT_Encode2(2), GIMT_Encode2(GICP_gi_vop3mods),
        GIM_CheckComplexPattern, /*MI*/2, /*Op*/1, /*Renderer*/GIMT_Encode2(0), GIMT_Encode2(GICP_gi_vop3mods),
        GIM_CheckComplexPattern, /*MI*/2, /*Op*/2, /*Renderer*/GIMT_Encode2(1), GIMT_Encode2(GICP_gi_vop3mods),
        // (fminnum_ieee:{ *:[f32] } (fmaxnum_ieee:{ *:[f32] } (fminnum:{ *:[f32] } (VOP3Mods:{ *:[f32] } f32:{ *:[f32] }:$src0, i32:{ *:[i32] }:$src0_mods), (VOP3Mods:{ *:[f32] } f32:{ *:[f32] }:$src1, i32:{ *:[i32] }:$src1_mods)), (VOP3Mods:{ *:[f32] } f32:{ *:[f32] }:$src2, i32:{ *:[i32] }:$src2_mods)), (fmaxnum:{ *:[f32] } (VOP3Mods:{ *:[f32] } f32:{ *:[f32] }:$src0, i32:{ *:[i32] }:$src0_mods), (VOP3Mods:{ *:[f32] } f32:{ *:[f32] }:$src1, i32:{ *:[i32] }:$src1_mods)))<<P:Predicate_fminnum_like_nnan>>  =>  (V_MED3_F32_e64:{ *:[f32] } ?:{ *:[i32] }:$src0_mods, ?:{ *:[f32] }:$src0, ?:{ *:[i32] }:$src1_mods, ?:{ *:[f32] }:$src1, ?:{ *:[i32] }:$src2_mods, ?:{ *:[f32] }:$src2, 0:{ *:[i1] }, 0:{ *:[i32] })
        GIR_BuildMI, /*InsnID*/0, /*Opcode*/GIMT_Encode2(AMDGPU::V_MED3_F32_e64),
        GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/0, // DstI[vdst]
        GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/1, // src0_mods
        GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/0, // src0
        GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(1), /*SubOperand*/1, // src1_mods
        GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(1), /*SubOperand*/0, // src1
        GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(2), /*SubOperand*/1, // src2_mods
        GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(2), /*SubOperand*/0, // src2
        GIR_AddImm8, /*InsnID*/0, /*Imm*/0,
        GIR_AddImm8, /*InsnID*/0, /*Imm*/0,
        GIR_ConstrainSelectedInstOperands, /*InsnID*/0,
        GIR_EraseFromParent, /*InsnID*/0,
        // GIR_Coverage, 10322,
        GIR_Done,
      // Label 4883: @343337
      GIM_Try, /*On fail goto*//*Label 4884*/ GIMT_Encode4(343477), // Rule ID 10323 //
        GIM_CheckRegBankForClass, /*MI*/0, /*Op*/0, /*RC*/GIMT_Encode2(AMDGPU::VGPR_32RegClassID),
        GIM_RecordInsn, /*DefineMI*/1, /*MI*/0, /*OpIdx*/1, // MIs[1]
        GIM_CheckOpcode, /*MI*/1, GIMT_Encode2(TargetOpcode::G_FMAXNUM_IEEE),
        GIM_CheckType, /*MI*/1, /*Op*/1, /*Type*/GILLT_s32,
        GIM_CheckType, /*MI*/1, /*Op*/2, /*Type*/GILLT_s32,
        GIM_RecordInsn, /*DefineMI*/2, /*MI*/1, /*OpIdx*/1, // MIs[2]
        GIM_CheckOpcode, /*MI*/2, GIMT_Encode2(TargetOpcode::G_FMINNUM),
        GIM_CheckType, /*MI*/2, /*Op*/1, /*Type*/GILLT_s32,
        GIM_CheckType, /*MI*/2, /*Op*/2, /*Type*/GILLT_s32,
        GIM_RecordInsn, /*DefineMI*/3, /*MI*/0, /*OpIdx*/2, // MIs[3]
        GIM_CheckOpcode, /*MI*/3, GIMT_Encode2(TargetOpcode::G_FMAXNUM),
        // MIs[3] VOP3Mods:src1:src1_mods
        GIM_CheckIsSameOperand, /*MI*/3, /*OpIdx*/1, /*OtherMI*/2, /*OtherOpIdx*/2,
        // MIs[3] VOP3Mods:src0:src0_mods
        GIM_CheckIsSameOperand, /*MI*/3, /*OpIdx*/2, /*OtherMI*/2, /*OtherOpIdx*/1,
        GIM_CheckCxxInsnPredicate, /*MI*/0, /*FnId*/GIMT_Encode2(GICXXPred_MI_Predicate_fminnum_like_nnan),
        GIM_CheckIsSafeToFold, /*InsnID*/1,
        GIM_CheckIsSafeToFold, /*InsnID*/2,
        GIM_CheckIsSafeToFold, /*InsnID*/3,
        GIM_CheckComplexPattern, /*MI*/1, /*Op*/2, /*Renderer*/GIMT_Encode2(2), GIMT_Encode2(GICP_gi_vop3mods),
        GIM_CheckComplexPattern, /*MI*/2, /*Op*/1, /*Renderer*/GIMT_Encode2(0), GIMT_Encode2(GICP_gi_vop3mods),
        GIM_CheckComplexPattern, /*MI*/2, /*Op*/2, /*Renderer*/GIMT_Encode2(1), GIMT_Encode2(GICP_gi_vop3mods),
        // (fminnum_ieee:{ *:[f32] } (fmaxnum_ieee:{ *:[f32] } (fminnum:{ *:[f32] } (VOP3Mods:{ *:[f32] } f32:{ *:[f32] }:$src0, i32:{ *:[i32] }:$src0_mods), (VOP3Mods:{ *:[f32] } f32:{ *:[f32] }:$src1, i32:{ *:[i32] }:$src1_mods)), (VOP3Mods:{ *:[f32] } f32:{ *:[f32] }:$src2, i32:{ *:[i32] }:$src2_mods)), (fmaxnum:{ *:[f32] } (VOP3Mods:{ *:[f32] } f32:{ *:[f32] }:$src1, i32:{ *:[i32] }:$src1_mods), (VOP3Mods:{ *:[f32] } f32:{ *:[f32] }:$src0, i32:{ *:[i32] }:$src0_mods)))<<P:Predicate_fminnum_like_nnan>>  =>  (V_MED3_F32_e64:{ *:[f32] } ?:{ *:[i32] }:$src0_mods, ?:{ *:[f32] }:$src0, ?:{ *:[i32] }:$src1_mods, ?:{ *:[f32] }:$src1, ?:{ *:[i32] }:$src2_mods, ?:{ *:[f32] }:$src2, 0:{ *:[i1] }, 0:{ *:[i32] })
        GIR_BuildMI, /*InsnID*/0, /*Opcode*/GIMT_Encode2(AMDGPU::V_MED3_F32_e64),
        GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/0, // DstI[vdst]
        GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/1, // src0_mods
        GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/0, // src0
        GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(1), /*SubOperand*/1, // src1_mods
        GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(1), /*SubOperand*/0, // src1
        GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(2), /*SubOperand*/1, // src2_mods
        GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(2), /*SubOperand*/0, // src2
        GIR_AddImm8, /*InsnID*/0, /*Imm*/0,
        GIR_AddImm8, /*InsnID*/0, /*Imm*/0,
        GIR_ConstrainSelectedInstOperands, /*InsnID*/0,
        GIR_EraseFromParent, /*InsnID*/0,
        // GIR_Coverage, 10323,
        GIR_Done,
      // Label 4884: @343477
      GIM_Try, /*On fail goto*//*Label 4885*/ GIMT_Encode4(343617), // Rule ID 10324 //
        GIM_CheckRegBankForClass, /*MI*/0, /*Op*/0, /*RC*/GIMT_Encode2(AMDGPU::VGPR_32RegClassID),
        GIM_RecordInsn, /*DefineMI*/1, /*MI*/0, /*OpIdx*/1, // MIs[1]
        GIM_CheckOpcode, /*MI*/1, GIMT_Encode2(TargetOpcode::G_FMAXNUM_IEEE),
        GIM_CheckType, /*MI*/1, /*Op*/1, /*Type*/GILLT_s32,
        GIM_CheckType, /*MI*/1, /*Op*/2, /*Type*/GILLT_s32,
        GIM_RecordInsn, /*DefineMI*/2, /*MI*/1, /*OpIdx*/1, // MIs[2]
        GIM_CheckOpcode, /*MI*/2, GIMT_Encode2(TargetOpcode::G_FMINNUM),
        GIM_CheckType, /*MI*/2, /*Op*/1, /*Type*/GILLT_s32,
        GIM_CheckType, /*MI*/2, /*Op*/2, /*Type*/GILLT_s32,
        GIM_RecordInsn, /*DefineMI*/3, /*MI*/0, /*OpIdx*/2, // MIs[3]
        GIM_CheckOpcode, /*MI*/3, GIMT_Encode2(TargetOpcode::G_FMAXNUM),
        // MIs[3] VOP3Mods:src0:src0_mods
        GIM_CheckIsSameOperand, /*MI*/3, /*OpIdx*/1, /*OtherMI*/2, /*OtherOpIdx*/2,
        // MIs[3] VOP3Mods:src1:src1_mods
        GIM_CheckIsSameOperand, /*MI*/3, /*OpIdx*/2, /*OtherMI*/2, /*OtherOpIdx*/1,
        GIM_CheckCxxInsnPredicate, /*MI*/0, /*FnId*/GIMT_Encode2(GICXXPred_MI_Predicate_fminnum_like_nnan),
        GIM_CheckIsSafeToFold, /*InsnID*/1,
        GIM_CheckIsSafeToFold, /*InsnID*/2,
        GIM_CheckIsSafeToFold, /*InsnID*/3,
        GIM_CheckComplexPattern, /*MI*/1, /*Op*/2, /*Renderer*/GIMT_Encode2(2), GIMT_Encode2(GICP_gi_vop3mods),
        GIM_CheckComplexPattern, /*MI*/2, /*Op*/1, /*Renderer*/GIMT_Encode2(0), GIMT_Encode2(GICP_gi_vop3mods),
        GIM_CheckComplexPattern, /*MI*/2, /*Op*/2, /*Renderer*/GIMT_Encode2(1), GIMT_Encode2(GICP_gi_vop3mods),
        // (fminnum_ieee:{ *:[f32] } (fmaxnum_ieee:{ *:[f32] } (fminnum:{ *:[f32] } (VOP3Mods:{ *:[f32] } f32:{ *:[f32] }:$src1, i32:{ *:[i32] }:$src1_mods), (VOP3Mods:{ *:[f32] } f32:{ *:[f32] }:$src0, i32:{ *:[i32] }:$src0_mods)), (VOP3Mods:{ *:[f32] } f32:{ *:[f32] }:$src2, i32:{ *:[i32] }:$src2_mods)), (fmaxnum:{ *:[f32] } (VOP3Mods:{ *:[f32] } f32:{ *:[f32] }:$src0, i32:{ *:[i32] }:$src0_mods), (VOP3Mods:{ *:[f32] } f32:{ *:[f32] }:$src1, i32:{ *:[i32] }:$src1_mods)))<<P:Predicate_fminnum_like_nnan>>  =>  (V_MED3_F32_e64:{ *:[f32] } ?:{ *:[i32] }:$src0_mods, ?:{ *:[f32] }:$src0, ?:{ *:[i32] }:$src1_mods, ?:{ *:[f32] }:$src1, ?:{ *:[i32] }:$src2_mods, ?:{ *:[f32] }:$src2, 0:{ *:[i1] }, 0:{ *:[i32] })
        GIR_BuildMI, /*InsnID*/0, /*Opcode*/GIMT_Encode2(AMDGPU::V_MED3_F32_e64),
        GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/0, // DstI[vdst]
        GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(1), /*SubOperand*/1, // src0_mods
        GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(1), /*SubOperand*/0, // src0
        GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/1, // src1_mods
        GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/0, // src1
        GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(2), /*SubOperand*/1, // src2_mods
        GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(2), /*SubOperand*/0, // src2
        GIR_AddImm8, /*InsnID*/0, /*Imm*/0,
        GIR_AddImm8, /*InsnID*/0, /*Imm*/0,
        GIR_ConstrainSelectedInstOperands, /*InsnID*/0,
        GIR_EraseFromParent, /*InsnID*/0,
        // GIR_Coverage, 10324,
        GIR_Done,
      // Label 4885: @343617
      GIM_Try, /*On fail goto*//*Label 4886*/ GIMT_Encode4(343757), // Rule ID 10325 //
        GIM_CheckRegBankForClass, /*MI*/0, /*Op*/0, /*RC*/GIMT_Encode2(AMDGPU::VGPR_32RegClassID),
        GIM_RecordInsn, /*DefineMI*/1, /*MI*/0, /*OpIdx*/1, // MIs[1]
        GIM_CheckOpcode, /*MI*/1, GIMT_Encode2(TargetOpcode::G_FMAXNUM_IEEE),
        GIM_CheckType, /*MI*/1, /*Op*/1, /*Type*/GILLT_s32,
        GIM_CheckType, /*MI*/1, /*Op*/2, /*Type*/GILLT_s32,
        GIM_RecordInsn, /*DefineMI*/2, /*MI*/1, /*OpIdx*/1, // MIs[2]
        GIM_CheckOpcode, /*MI*/2, GIMT_Encode2(TargetOpcode::G_FMINNUM),
        GIM_CheckType, /*MI*/2, /*Op*/1, /*Type*/GILLT_s32,
        GIM_CheckType, /*MI*/2, /*Op*/2, /*Type*/GILLT_s32,
        GIM_RecordInsn, /*DefineMI*/3, /*MI*/0, /*OpIdx*/2, // MIs[3]
        GIM_CheckOpcode, /*MI*/3, GIMT_Encode2(TargetOpcode::G_FMAXNUM),
        // MIs[3] VOP3Mods:src1:src1_mods
        GIM_CheckIsSameOperand, /*MI*/3, /*OpIdx*/1, /*OtherMI*/2, /*OtherOpIdx*/1,
        // MIs[3] VOP3Mods:src0:src0_mods
        GIM_CheckIsSameOperand, /*MI*/3, /*OpIdx*/2, /*OtherMI*/2, /*OtherOpIdx*/2,
        GIM_CheckCxxInsnPredicate, /*MI*/0, /*FnId*/GIMT_Encode2(GICXXPred_MI_Predicate_fminnum_like_nnan),
        GIM_CheckIsSafeToFold, /*InsnID*/1,
        GIM_CheckIsSafeToFold, /*InsnID*/2,
        GIM_CheckIsSafeToFold, /*InsnID*/3,
        GIM_CheckComplexPattern, /*MI*/1, /*Op*/2, /*Renderer*/GIMT_Encode2(2), GIMT_Encode2(GICP_gi_vop3mods),
        GIM_CheckComplexPattern, /*MI*/2, /*Op*/1, /*Renderer*/GIMT_Encode2(0), GIMT_Encode2(GICP_gi_vop3mods),
        GIM_CheckComplexPattern, /*MI*/2, /*Op*/2, /*Renderer*/GIMT_Encode2(1), GIMT_Encode2(GICP_gi_vop3mods),
        // (fminnum_ieee:{ *:[f32] } (fmaxnum_ieee:{ *:[f32] } (fminnum:{ *:[f32] } (VOP3Mods:{ *:[f32] } f32:{ *:[f32] }:$src1, i32:{ *:[i32] }:$src1_mods), (VOP3Mods:{ *:[f32] } f32:{ *:[f32] }:$src0, i32:{ *:[i32] }:$src0_mods)), (VOP3Mods:{ *:[f32] } f32:{ *:[f32] }:$src2, i32:{ *:[i32] }:$src2_mods)), (fmaxnum:{ *:[f32] } (VOP3Mods:{ *:[f32] } f32:{ *:[f32] }:$src1, i32:{ *:[i32] }:$src1_mods), (VOP3Mods:{ *:[f32] } f32:{ *:[f32] }:$src0, i32:{ *:[i32] }:$src0_mods)))<<P:Predicate_fminnum_like_nnan>>  =>  (V_MED3_F32_e64:{ *:[f32] } ?:{ *:[i32] }:$src0_mods, ?:{ *:[f32] }:$src0, ?:{ *:[i32] }:$src1_mods, ?:{ *:[f32] }:$src1, ?:{ *:[i32] }:$src2_mods, ?:{ *:[f32] }:$src2, 0:{ *:[i1] }, 0:{ *:[i32] })
        GIR_BuildMI, /*InsnID*/0, /*Opcode*/GIMT_Encode2(AMDGPU::V_MED3_F32_e64),
        GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/0, // DstI[vdst]
        GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(1), /*SubOperand*/1, // src0_mods
        GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(1), /*SubOperand*/0, // src0
        GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/1, // src1_mods
        GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/0, // src1
        GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(2), /*SubOperand*/1, // src2_mods
        GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(2), /*SubOperand*/0, // src2
        GIR_AddImm8, /*InsnID*/0, /*Imm*/0,
        GIR_AddImm8, /*InsnID*/0, /*Imm*/0,
        GIR_ConstrainSelectedInstOperands, /*InsnID*/0,
        GIR_EraseFromParent, /*InsnID*/0,
        // GIR_Coverage, 10325,
        GIR_Done,
      // Label 4886: @343757
      GIM_Try, /*On fail goto*//*Label 4887*/ GIMT_Encode4(343897), // Rule ID 10262 //
        GIM_CheckRegBankForClass, /*MI*/0, /*Op*/0, /*RC*/GIMT_Encode2(AMDGPU::VGPR_32RegClassID),
        GIM_RecordInsn, /*DefineMI*/1, /*MI*/0, /*OpIdx*/1, // MIs[1]
        GIM_CheckOpcode, /*MI*/1, GIMT_Encode2(TargetOpcode::G_FMAXNUM_IEEE),
        GIM_CheckType, /*MI*/1, /*Op*/1, /*Type*/GILLT_s32,
        GIM_CheckType, /*MI*/1, /*Op*/2, /*Type*/GILLT_s32,
        GIM_RecordInsn, /*DefineMI*/2, /*MI*/1, /*OpIdx*/1, // MIs[2]
        GIM_CheckOpcode, /*MI*/2, GIMT_Encode2(TargetOpcode::G_FMINNUM),
        GIM_CheckType, /*MI*/2, /*Op*/1, /*Type*/GILLT_s32,
        GIM_CheckType, /*MI*/2, /*Op*/2, /*Type*/GILLT_s32,
        GIM_RecordInsn, /*DefineMI*/3, /*MI*/0, /*OpIdx*/2, // MIs[3]
        GIM_CheckOpcode, /*MI*/3, GIMT_Encode2(TargetOpcode::G_FMAXNUM_IEEE),
        // MIs[3] VOP3Mods:src0:src0_mods
        GIM_CheckIsSameOperand, /*MI*/3, /*OpIdx*/1, /*OtherMI*/2, /*OtherOpIdx*/1,
        // MIs[3] VOP3Mods:src1:src1_mods
        GIM_CheckIsSameOperand, /*MI*/3, /*OpIdx*/2, /*OtherMI*/2, /*OtherOpIdx*/2,
        GIM_CheckCxxInsnPredicate, /*MI*/0, /*FnId*/GIMT_Encode2(GICXXPred_MI_Predicate_fminnum_like_nnan),
        GIM_CheckIsSafeToFold, /*InsnID*/1,
        GIM_CheckIsSafeToFold, /*InsnID*/2,
        GIM_CheckIsSafeToFold, /*InsnID*/3,
        GIM_CheckComplexPattern, /*MI*/1, /*Op*/2, /*Renderer*/GIMT_Encode2(2), GIMT_Encode2(GICP_gi_vop3mods),
        GIM_CheckComplexPattern, /*MI*/2, /*Op*/1, /*Renderer*/GIMT_Encode2(0), GIMT_Encode2(GICP_gi_vop3mods),
        GIM_CheckComplexPattern, /*MI*/2, /*Op*/2, /*Renderer*/GIMT_Encode2(1), GIMT_Encode2(GICP_gi_vop3mods),
        // (fminnum_ieee:{ *:[f32] } (fmaxnum_ieee:{ *:[f32] } (fminnum:{ *:[f32] } (VOP3Mods:{ *:[f32] } f32:{ *:[f32] }:$src0, i32:{ *:[i32] }:$src0_mods), (VOP3Mods:{ *:[f32] } f32:{ *:[f32] }:$src1, i32:{ *:[i32] }:$src1_mods)), (VOP3Mods:{ *:[f32] } f32:{ *:[f32] }:$src2, i32:{ *:[i32] }:$src2_mods)), (fmaxnum_ieee:{ *:[f32] } (VOP3Mods:{ *:[f32] } f32:{ *:[f32] }:$src0, i32:{ *:[i32] }:$src0_mods), (VOP3Mods:{ *:[f32] } f32:{ *:[f32] }:$src1, i32:{ *:[i32] }:$src1_mods)))<<P:Predicate_fminnum_like_nnan>>  =>  (V_MED3_F32_e64:{ *:[f32] } ?:{ *:[i32] }:$src0_mods, ?:{ *:[f32] }:$src0, ?:{ *:[i32] }:$src1_mods, ?:{ *:[f32] }:$src1, ?:{ *:[i32] }:$src2_mods, ?:{ *:[f32] }:$src2, 0:{ *:[i1] }, 0:{ *:[i32] })
        GIR_BuildMI, /*InsnID*/0, /*Opcode*/GIMT_Encode2(AMDGPU::V_MED3_F32_e64),
        GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/0, // DstI[vdst]
        GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/1, // src0_mods
        GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/0, // src0
        GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(1), /*SubOperand*/1, // src1_mods
        GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(1), /*SubOperand*/0, // src1
        GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(2), /*SubOperand*/1, // src2_mods
        GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(2), /*SubOperand*/0, // src2
        GIR_AddImm8, /*InsnID*/0, /*Imm*/0,
        GIR_AddImm8, /*InsnID*/0, /*Imm*/0,
        GIR_ConstrainSelectedInstOperands, /*InsnID*/0,
        GIR_EraseFromParent, /*InsnID*/0,
        // GIR_Coverage, 10262,
        GIR_Done,
      // Label 4887: @343897
      GIM_Try, /*On fail goto*//*Label 4888*/ GIMT_Encode4(344037), // Rule ID 10263 //
        GIM_CheckRegBankForClass, /*MI*/0, /*Op*/0, /*RC*/GIMT_Encode2(AMDGPU::VGPR_32RegClassID),
        GIM_RecordInsn, /*DefineMI*/1, /*MI*/0, /*OpIdx*/1, // MIs[1]
        GIM_CheckOpcode, /*MI*/1, GIMT_Encode2(TargetOpcode::G_FMAXNUM_IEEE),
        GIM_CheckType, /*MI*/1, /*Op*/1, /*Type*/GILLT_s32,
        GIM_CheckType, /*MI*/1, /*Op*/2, /*Type*/GILLT_s32,
        GIM_RecordInsn, /*DefineMI*/2, /*MI*/1, /*OpIdx*/1, // MIs[2]
        GIM_CheckOpcode, /*MI*/2, GIMT_Encode2(TargetOpcode::G_FMINNUM),
        GIM_CheckType, /*MI*/2, /*Op*/1, /*Type*/GILLT_s32,
        GIM_CheckType, /*MI*/2, /*Op*/2, /*Type*/GILLT_s32,
        GIM_RecordInsn, /*DefineMI*/3, /*MI*/0, /*OpIdx*/2, // MIs[3]
        GIM_CheckOpcode, /*MI*/3, GIMT_Encode2(TargetOpcode::G_FMAXNUM_IEEE),
        // MIs[3] VOP3Mods:src1:src1_mods
        GIM_CheckIsSameOperand, /*MI*/3, /*OpIdx*/1, /*OtherMI*/2, /*OtherOpIdx*/2,
        // MIs[3] VOP3Mods:src0:src0_mods
        GIM_CheckIsSameOperand, /*MI*/3, /*OpIdx*/2, /*OtherMI*/2, /*OtherOpIdx*/1,
        GIM_CheckCxxInsnPredicate, /*MI*/0, /*FnId*/GIMT_Encode2(GICXXPred_MI_Predicate_fminnum_like_nnan),
        GIM_CheckIsSafeToFold, /*InsnID*/1,
        GIM_CheckIsSafeToFold, /*InsnID*/2,
        GIM_CheckIsSafeToFold, /*InsnID*/3,
        GIM_CheckComplexPattern, /*MI*/1, /*Op*/2, /*Renderer*/GIMT_Encode2(2), GIMT_Encode2(GICP_gi_vop3mods),
        GIM_CheckComplexPattern, /*MI*/2, /*Op*/1, /*Renderer*/GIMT_Encode2(0), GIMT_Encode2(GICP_gi_vop3mods),
        GIM_CheckComplexPattern, /*MI*/2, /*Op*/2, /*Renderer*/GIMT_Encode2(1), GIMT_Encode2(GICP_gi_vop3mods),
        // (fminnum_ieee:{ *:[f32] } (fmaxnum_ieee:{ *:[f32] } (fminnum:{ *:[f32] } (VOP3Mods:{ *:[f32] } f32:{ *:[f32] }:$src0, i32:{ *:[i32] }:$src0_mods), (VOP3Mods:{ *:[f32] } f32:{ *:[f32] }:$src1, i32:{ *:[i32] }:$src1_mods)), (VOP3Mods:{ *:[f32] } f32:{ *:[f32] }:$src2, i32:{ *:[i32] }:$src2_mods)), (fmaxnum_ieee:{ *:[f32] } (VOP3Mods:{ *:[f32] } f32:{ *:[f32] }:$src1, i32:{ *:[i32] }:$src1_mods), (VOP3Mods:{ *:[f32] } f32:{ *:[f32] }:$src0, i32:{ *:[i32] }:$src0_mods)))<<P:Predicate_fminnum_like_nnan>>  =>  (V_MED3_F32_e64:{ *:[f32] } ?:{ *:[i32] }:$src0_mods, ?:{ *:[f32] }:$src0, ?:{ *:[i32] }:$src1_mods, ?:{ *:[f32] }:$src1, ?:{ *:[i32] }:$src2_mods, ?:{ *:[f32] }:$src2, 0:{ *:[i1] }, 0:{ *:[i32] })
        GIR_BuildMI, /*InsnID*/0, /*Opcode*/GIMT_Encode2(AMDGPU::V_MED3_F32_e64),
        GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/0, // DstI[vdst]
        GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/1, // src0_mods
        GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/0, // src0
        GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(1), /*SubOperand*/1, // src1_mods
        GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(1), /*SubOperand*/0, // src1
        GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(2), /*SubOperand*/1, // src2_mods
        GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(2), /*SubOperand*/0, // src2
        GIR_AddImm8, /*InsnID*/0, /*Imm*/0,
        GIR_AddImm8, /*InsnID*/0, /*Imm*/0,
        GIR_ConstrainSelectedInstOperands, /*InsnID*/0,
        GIR_EraseFromParent, /*InsnID*/0,
        // GIR_Coverage, 10263,
        GIR_Done,
      // Label 4888: @344037
      GIM_Try, /*On fail goto*//*Label 4889*/ GIMT_Encode4(344177), // Rule ID 10264 //
        GIM_CheckRegBankForClass, /*MI*/0, /*Op*/0, /*RC*/GIMT_Encode2(AMDGPU::VGPR_32RegClassID),
        GIM_RecordInsn, /*DefineMI*/1, /*MI*/0, /*OpIdx*/1, // MIs[1]
        GIM_CheckOpcode, /*MI*/1, GIMT_Encode2(TargetOpcode::G_FMAXNUM_IEEE),
        GIM_CheckType, /*MI*/1, /*Op*/1, /*Type*/GILLT_s32,
        GIM_CheckType, /*MI*/1, /*Op*/2, /*Type*/GILLT_s32,
        GIM_RecordInsn, /*DefineMI*/2, /*MI*/1, /*OpIdx*/1, // MIs[2]
        GIM_CheckOpcode, /*MI*/2, GIMT_Encode2(TargetOpcode::G_FMINNUM),
        GIM_CheckType, /*MI*/2, /*Op*/1, /*Type*/GILLT_s32,
        GIM_CheckType, /*MI*/2, /*Op*/2, /*Type*/GILLT_s32,
        GIM_RecordInsn, /*DefineMI*/3, /*MI*/0, /*OpIdx*/2, // MIs[3]
        GIM_CheckOpcode, /*MI*/3, GIMT_Encode2(TargetOpcode::G_FMAXNUM_IEEE),
        // MIs[3] VOP3Mods:src0:src0_mods
        GIM_CheckIsSameOperand, /*MI*/3, /*OpIdx*/1, /*OtherMI*/2, /*OtherOpIdx*/2,
        // MIs[3] VOP3Mods:src1:src1_mods
        GIM_CheckIsSameOperand, /*MI*/3, /*OpIdx*/2, /*OtherMI*/2, /*OtherOpIdx*/1,
        GIM_CheckCxxInsnPredicate, /*MI*/0, /*FnId*/GIMT_Encode2(GICXXPred_MI_Predicate_fminnum_like_nnan),
        GIM_CheckIsSafeToFold, /*InsnID*/1,
        GIM_CheckIsSafeToFold, /*InsnID*/2,
        GIM_CheckIsSafeToFold, /*InsnID*/3,
        GIM_CheckComplexPattern, /*MI*/1, /*Op*/2, /*Renderer*/GIMT_Encode2(2), GIMT_Encode2(GICP_gi_vop3mods),
        GIM_CheckComplexPattern, /*MI*/2, /*Op*/1, /*Renderer*/GIMT_Encode2(0), GIMT_Encode2(GICP_gi_vop3mods),
        GIM_CheckComplexPattern, /*MI*/2, /*Op*/2, /*Renderer*/GIMT_Encode2(1), GIMT_Encode2(GICP_gi_vop3mods),
        // (fminnum_ieee:{ *:[f32] } (fmaxnum_ieee:{ *:[f32] } (fminnum:{ *:[f32] } (VOP3Mods:{ *:[f32] } f32:{ *:[f32] }:$src1, i32:{ *:[i32] }:$src1_mods), (VOP3Mods:{ *:[f32] } f32:{ *:[f32] }:$src0, i32:{ *:[i32] }:$src0_mods)), (VOP3Mods:{ *:[f32] } f32:{ *:[f32] }:$src2, i32:{ *:[i32] }:$src2_mods)), (fmaxnum_ieee:{ *:[f32] } (VOP3Mods:{ *:[f32] } f32:{ *:[f32] }:$src0, i32:{ *:[i32] }:$src0_mods), (VOP3Mods:{ *:[f32] } f32:{ *:[f32] }:$src1, i32:{ *:[i32] }:$src1_mods)))<<P:Predicate_fminnum_like_nnan>>  =>  (V_MED3_F32_e64:{ *:[f32] } ?:{ *:[i32] }:$src0_mods, ?:{ *:[f32] }:$src0, ?:{ *:[i32] }:$src1_mods, ?:{ *:[f32] }:$src1, ?:{ *:[i32] }:$src2_mods, ?:{ *:[f32] }:$src2, 0:{ *:[i1] }, 0:{ *:[i32] })
        GIR_BuildMI, /*InsnID*/0, /*Opcode*/GIMT_Encode2(AMDGPU::V_MED3_F32_e64),
        GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/0, // DstI[vdst]
        GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(1), /*SubOperand*/1, // src0_mods
        GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(1), /*SubOperand*/0, // src0
        GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/1, // src1_mods
        GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/0, // src1
        GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(2), /*SubOperand*/1, // src2_mods
        GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(2), /*SubOperand*/0, // src2
        GIR_AddImm8, /*InsnID*/0, /*Imm*/0,
        GIR_AddImm8, /*InsnID*/0, /*Imm*/0,
        GIR_ConstrainSelectedInstOperands, /*InsnID*/0,
        GIR_EraseFromParent, /*InsnID*/0,
        // GIR_Coverage, 10264,
        GIR_Done,
      // Label 4889: @344177
      GIM_Try, /*On fail goto*//*Label 4890*/ GIMT_Encode4(344317), // Rule ID 10265 //
        GIM_CheckRegBankForClass, /*MI*/0, /*Op*/0, /*RC*/GIMT_Encode2(AMDGPU::VGPR_32RegClassID),
        GIM_RecordInsn, /*DefineMI*/1, /*MI*/0, /*OpIdx*/1, // MIs[1]
        GIM_CheckOpcode, /*MI*/1, GIMT_Encode2(TargetOpcode::G_FMAXNUM_IEEE),
        GIM_CheckType, /*MI*/1, /*Op*/1, /*Type*/GILLT_s32,
        GIM_CheckType, /*MI*/1, /*Op*/2, /*Type*/GILLT_s32,
        GIM_RecordInsn, /*DefineMI*/2, /*MI*/1, /*OpIdx*/1, // MIs[2]
        GIM_CheckOpcode, /*MI*/2, GIMT_Encode2(TargetOpcode::G_FMINNUM),
        GIM_CheckType, /*MI*/2, /*Op*/1, /*Type*/GILLT_s32,
        GIM_CheckType, /*MI*/2, /*Op*/2, /*Type*/GILLT_s32,
        GIM_RecordInsn, /*DefineMI*/3, /*MI*/0, /*OpIdx*/2, // MIs[3]
        GIM_CheckOpcode, /*MI*/3, GIMT_Encode2(TargetOpcode::G_FMAXNUM_IEEE),
        // MIs[3] VOP3Mods:src1:src1_mods
        GIM_CheckIsSameOperand, /*MI*/3, /*OpIdx*/1, /*OtherMI*/2, /*OtherOpIdx*/1,
        // MIs[3] VOP3Mods:src0:src0_mods
        GIM_CheckIsSameOperand, /*MI*/3, /*OpIdx*/2, /*OtherMI*/2, /*OtherOpIdx*/2,
        GIM_CheckCxxInsnPredicate, /*MI*/0, /*FnId*/GIMT_Encode2(GICXXPred_MI_Predicate_fminnum_like_nnan),
        GIM_CheckIsSafeToFold, /*InsnID*/1,
        GIM_CheckIsSafeToFold, /*InsnID*/2,
        GIM_CheckIsSafeToFold, /*InsnID*/3,
        GIM_CheckComplexPattern, /*MI*/1, /*Op*/2, /*Renderer*/GIMT_Encode2(2), GIMT_Encode2(GICP_gi_vop3mods),
        GIM_CheckComplexPattern, /*MI*/2, /*Op*/1, /*Renderer*/GIMT_Encode2(0), GIMT_Encode2(GICP_gi_vop3mods),
        GIM_CheckComplexPattern, /*MI*/2, /*Op*/2, /*Renderer*/GIMT_Encode2(1), GIMT_Encode2(GICP_gi_vop3mods),
        // (fminnum_ieee:{ *:[f32] } (fmaxnum_ieee:{ *:[f32] } (fminnum:{ *:[f32] } (VOP3Mods:{ *:[f32] } f32:{ *:[f32] }:$src1, i32:{ *:[i32] }:$src1_mods), (VOP3Mods:{ *:[f32] } f32:{ *:[f32] }:$src0, i32:{ *:[i32] }:$src0_mods)), (VOP3Mods:{ *:[f32] } f32:{ *:[f32] }:$src2, i32:{ *:[i32] }:$src2_mods)), (fmaxnum_ieee:{ *:[f32] } (VOP3Mods:{ *:[f32] } f32:{ *:[f32] }:$src1, i32:{ *:[i32] }:$src1_mods), (VOP3Mods:{ *:[f32] } f32:{ *:[f32] }:$src0, i32:{ *:[i32] }:$src0_mods)))<<P:Predicate_fminnum_like_nnan>>  =>  (V_MED3_F32_e64:{ *:[f32] } ?:{ *:[i32] }:$src0_mods, ?:{ *:[f32] }:$src0, ?:{ *:[i32] }:$src1_mods, ?:{ *:[f32] }:$src1, ?:{ *:[i32] }:$src2_mods, ?:{ *:[f32] }:$src2, 0:{ *:[i1] }, 0:{ *:[i32] })
        GIR_BuildMI, /*InsnID*/0, /*Opcode*/GIMT_Encode2(AMDGPU::V_MED3_F32_e64),
        GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/0, // DstI[vdst]
        GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(1), /*SubOperand*/1, // src0_mods
        GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(1), /*SubOperand*/0, // src0
        GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/1, // src1_mods
        GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/0, // src1
        GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(2), /*SubOperand*/1, // src2_mods
        GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(2), /*SubOperand*/0, // src2
        GIR_AddImm8, /*InsnID*/0, /*Imm*/0,
        GIR_AddImm8, /*InsnID*/0, /*Imm*/0,
        GIR_ConstrainSelectedInstOperands, /*InsnID*/0,
        GIR_EraseFromParent, /*InsnID*/0,
        // GIR_Coverage, 10265,
        GIR_Done,
      // Label 4890: @344317
      GIM_Try, /*On fail goto*//*Label 4891*/ GIMT_Encode4(344457), // Rule ID 10307 //
        GIM_CheckRegBankForClass, /*MI*/0, /*Op*/0, /*RC*/GIMT_Encode2(AMDGPU::VGPR_32RegClassID),
        GIM_RecordInsn, /*DefineMI*/1, /*MI*/0, /*OpIdx*/1, // MIs[1]
        GIM_CheckOpcode, /*MI*/1, GIMT_Encode2(TargetOpcode::G_FMAXNUM_IEEE),
        GIM_CheckType, /*MI*/1, /*Op*/1, /*Type*/GILLT_s32,
        GIM_CheckType, /*MI*/1, /*Op*/2, /*Type*/GILLT_s32,
        GIM_RecordInsn, /*DefineMI*/2, /*MI*/1, /*OpIdx*/1, // MIs[2]
        GIM_CheckOpcode, /*MI*/2, GIMT_Encode2(TargetOpcode::G_FMINNUM_IEEE),
        GIM_CheckType, /*MI*/2, /*Op*/1, /*Type*/GILLT_s32,
        GIM_CheckType, /*MI*/2, /*Op*/2, /*Type*/GILLT_s32,
        GIM_RecordInsn, /*DefineMI*/3, /*MI*/0, /*OpIdx*/2, // MIs[3]
        GIM_CheckOpcode, /*MI*/3, GIMT_Encode2(TargetOpcode::G_FMAXNUM),
        // MIs[3] VOP3Mods:src0:src0_mods
        GIM_CheckIsSameOperand, /*MI*/3, /*OpIdx*/1, /*OtherMI*/2, /*OtherOpIdx*/1,
        // MIs[3] VOP3Mods:src1:src1_mods
        GIM_CheckIsSameOperand, /*MI*/3, /*OpIdx*/2, /*OtherMI*/2, /*OtherOpIdx*/2,
        GIM_CheckCxxInsnPredicate, /*MI*/0, /*FnId*/GIMT_Encode2(GICXXPred_MI_Predicate_fminnum_like_nnan),
        GIM_CheckIsSafeToFold, /*InsnID*/1,
        GIM_CheckIsSafeToFold, /*InsnID*/2,
        GIM_CheckIsSafeToFold, /*InsnID*/3,
        GIM_CheckComplexPattern, /*MI*/1, /*Op*/2, /*Renderer*/GIMT_Encode2(2), GIMT_Encode2(GICP_gi_vop3mods),
        GIM_CheckComplexPattern, /*MI*/2, /*Op*/1, /*Renderer*/GIMT_Encode2(0), GIMT_Encode2(GICP_gi_vop3mods),
        GIM_CheckComplexPattern, /*MI*/2, /*Op*/2, /*Renderer*/GIMT_Encode2(1), GIMT_Encode2(GICP_gi_vop3mods),
        // (fminnum_ieee:{ *:[f32] } (fmaxnum_ieee:{ *:[f32] } (fminnum_ieee:{ *:[f32] } (VOP3Mods:{ *:[f32] } f32:{ *:[f32] }:$src0, i32:{ *:[i32] }:$src0_mods), (VOP3Mods:{ *:[f32] } f32:{ *:[f32] }:$src1, i32:{ *:[i32] }:$src1_mods)), (VOP3Mods:{ *:[f32] } f32:{ *:[f32] }:$src2, i32:{ *:[i32] }:$src2_mods)), (fmaxnum:{ *:[f32] } (VOP3Mods:{ *:[f32] } f32:{ *:[f32] }:$src0, i32:{ *:[i32] }:$src0_mods), (VOP3Mods:{ *:[f32] } f32:{ *:[f32] }:$src1, i32:{ *:[i32] }:$src1_mods)))<<P:Predicate_fminnum_like_nnan>>  =>  (V_MED3_F32_e64:{ *:[f32] } ?:{ *:[i32] }:$src0_mods, ?:{ *:[f32] }:$src0, ?:{ *:[i32] }:$src1_mods, ?:{ *:[f32] }:$src1, ?:{ *:[i32] }:$src2_mods, ?:{ *:[f32] }:$src2, 0:{ *:[i1] }, 0:{ *:[i32] })
        GIR_BuildMI, /*InsnID*/0, /*Opcode*/GIMT_Encode2(AMDGPU::V_MED3_F32_e64),
        GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/0, // DstI[vdst]
        GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/1, // src0_mods
        GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/0, // src0
        GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(1), /*SubOperand*/1, // src1_mods
        GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(1), /*SubOperand*/0, // src1
        GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(2), /*SubOperand*/1, // src2_mods
        GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(2), /*SubOperand*/0, // src2
        GIR_AddImm8, /*InsnID*/0, /*Imm*/0,
        GIR_AddImm8, /*InsnID*/0, /*Imm*/0,
        GIR_ConstrainSelectedInstOperands, /*InsnID*/0,
        GIR_EraseFromParent, /*InsnID*/0,
        // GIR_Coverage, 10307,
        GIR_Done,
      // Label 4891: @344457
      GIM_Try, /*On fail goto*//*Label 4892*/ GIMT_Encode4(344597), // Rule ID 10308 //
        GIM_CheckRegBankForClass, /*MI*/0, /*Op*/0, /*RC*/GIMT_Encode2(AMDGPU::VGPR_32RegClassID),
        GIM_RecordInsn, /*DefineMI*/1, /*MI*/0, /*OpIdx*/1, // MIs[1]
        GIM_CheckOpcode, /*MI*/1, GIMT_Encode2(TargetOpcode::G_FMAXNUM_IEEE),
        GIM_CheckType, /*MI*/1, /*Op*/1, /*Type*/GILLT_s32,
        GIM_CheckType, /*MI*/1, /*Op*/2, /*Type*/GILLT_s32,
        GIM_RecordInsn, /*DefineMI*/2, /*MI*/1, /*OpIdx*/1, // MIs[2]
        GIM_CheckOpcode, /*MI*/2, GIMT_Encode2(TargetOpcode::G_FMINNUM_IEEE),
        GIM_CheckType, /*MI*/2, /*Op*/1, /*Type*/GILLT_s32,
        GIM_CheckType, /*MI*/2, /*Op*/2, /*Type*/GILLT_s32,
        GIM_RecordInsn, /*DefineMI*/3, /*MI*/0, /*OpIdx*/2, // MIs[3]
        GIM_CheckOpcode, /*MI*/3, GIMT_Encode2(TargetOpcode::G_FMAXNUM),
        // MIs[3] VOP3Mods:src1:src1_mods
        GIM_CheckIsSameOperand, /*MI*/3, /*OpIdx*/1, /*OtherMI*/2, /*OtherOpIdx*/2,
        // MIs[3] VOP3Mods:src0:src0_mods
        GIM_CheckIsSameOperand, /*MI*/3, /*OpIdx*/2, /*OtherMI*/2, /*OtherOpIdx*/1,
        GIM_CheckCxxInsnPredicate, /*MI*/0, /*FnId*/GIMT_Encode2(GICXXPred_MI_Predicate_fminnum_like_nnan),
        GIM_CheckIsSafeToFold, /*InsnID*/1,
        GIM_CheckIsSafeToFold, /*InsnID*/2,
        GIM_CheckIsSafeToFold, /*InsnID*/3,
        GIM_CheckComplexPattern, /*MI*/1, /*Op*/2, /*Renderer*/GIMT_Encode2(2), GIMT_Encode2(GICP_gi_vop3mods),
        GIM_CheckComplexPattern, /*MI*/2, /*Op*/1, /*Renderer*/GIMT_Encode2(0), GIMT_Encode2(GICP_gi_vop3mods),
        GIM_CheckComplexPattern, /*MI*/2, /*Op*/2, /*Renderer*/GIMT_Encode2(1), GIMT_Encode2(GICP_gi_vop3mods),
        // (fminnum_ieee:{ *:[f32] } (fmaxnum_ieee:{ *:[f32] } (fminnum_ieee:{ *:[f32] } (VOP3Mods:{ *:[f32] } f32:{ *:[f32] }:$src0, i32:{ *:[i32] }:$src0_mods), (VOP3Mods:{ *:[f32] } f32:{ *:[f32] }:$src1, i32:{ *:[i32] }:$src1_mods)), (VOP3Mods:{ *:[f32] } f32:{ *:[f32] }:$src2, i32:{ *:[i32] }:$src2_mods)), (fmaxnum:{ *:[f32] } (VOP3Mods:{ *:[f32] } f32:{ *:[f32] }:$src1, i32:{ *:[i32] }:$src1_mods), (VOP3Mods:{ *:[f32] } f32:{ *:[f32] }:$src0, i32:{ *:[i32] }:$src0_mods)))<<P:Predicate_fminnum_like_nnan>>  =>  (V_MED3_F32_e64:{ *:[f32] } ?:{ *:[i32] }:$src0_mods, ?:{ *:[f32] }:$src0, ?:{ *:[i32] }:$src1_mods, ?:{ *:[f32] }:$src1, ?:{ *:[i32] }:$src2_mods, ?:{ *:[f32] }:$src2, 0:{ *:[i1] }, 0:{ *:[i32] })
        GIR_BuildMI, /*InsnID*/0, /*Opcode*/GIMT_Encode2(AMDGPU::V_MED3_F32_e64),
        GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/0, // DstI[vdst]
        GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/1, // src0_mods
        GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/0, // src0
        GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(1), /*SubOperand*/1, // src1_mods
        GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(1), /*SubOperand*/0, // src1
        GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(2), /*SubOperand*/1, // src2_mods
        GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(2), /*SubOperand*/0, // src2
        GIR_AddImm8, /*InsnID*/0, /*Imm*/0,
        GIR_AddImm8, /*InsnID*/0, /*Imm*/0,
        GIR_ConstrainSelectedInstOperands, /*InsnID*/0,
        GIR_EraseFromParent, /*InsnID*/0,
        // GIR_Coverage, 10308,
        GIR_Done,
      // Label 4892: @344597
      GIM_Try, /*On fail goto*//*Label 4893*/ GIMT_Encode4(344737), // Rule ID 10309 //
        GIM_CheckRegBankForClass, /*MI*/0, /*Op*/0, /*RC*/GIMT_Encode2(AMDGPU::VGPR_32RegClassID),
        GIM_RecordInsn, /*DefineMI*/1, /*MI*/0, /*OpIdx*/1, // MIs[1]
        GIM_CheckOpcode, /*MI*/1, GIMT_Encode2(TargetOpcode::G_FMAXNUM_IEEE),
        GIM_CheckType, /*MI*/1, /*Op*/1, /*Type*/GILLT_s32,
        GIM_CheckType, /*MI*/1, /*Op*/2, /*Type*/GILLT_s32,
        GIM_RecordInsn, /*DefineMI*/2, /*MI*/1, /*OpIdx*/1, // MIs[2]
        GIM_CheckOpcode, /*MI*/2, GIMT_Encode2(TargetOpcode::G_FMINNUM_IEEE),
        GIM_CheckType, /*MI*/2, /*Op*/1, /*Type*/GILLT_s32,
        GIM_CheckType, /*MI*/2, /*Op*/2, /*Type*/GILLT_s32,
        GIM_RecordInsn, /*DefineMI*/3, /*MI*/0, /*OpIdx*/2, // MIs[3]
        GIM_CheckOpcode, /*MI*/3, GIMT_Encode2(TargetOpcode::G_FMAXNUM),
        // MIs[3] VOP3Mods:src0:src0_mods
        GIM_CheckIsSameOperand, /*MI*/3, /*OpIdx*/1, /*OtherMI*/2, /*OtherOpIdx*/2,
        // MIs[3] VOP3Mods:src1:src1_mods
        GIM_CheckIsSameOperand, /*MI*/3, /*OpIdx*/2, /*OtherMI*/2, /*OtherOpIdx*/1,
        GIM_CheckCxxInsnPredicate, /*MI*/0, /*FnId*/GIMT_Encode2(GICXXPred_MI_Predicate_fminnum_like_nnan),
        GIM_CheckIsSafeToFold, /*InsnID*/1,
        GIM_CheckIsSafeToFold, /*InsnID*/2,
        GIM_CheckIsSafeToFold, /*InsnID*/3,
        GIM_CheckComplexPattern, /*MI*/1, /*Op*/2, /*Renderer*/GIMT_Encode2(2), GIMT_Encode2(GICP_gi_vop3mods),
        GIM_CheckComplexPattern, /*MI*/2, /*Op*/1, /*Renderer*/GIMT_Encode2(0), GIMT_Encode2(GICP_gi_vop3mods),
        GIM_CheckComplexPattern, /*MI*/2, /*Op*/2, /*Renderer*/GIMT_Encode2(1), GIMT_Encode2(GICP_gi_vop3mods),
        // (fminnum_ieee:{ *:[f32] } (fmaxnum_ieee:{ *:[f32] } (fminnum_ieee:{ *:[f32] } (VOP3Mods:{ *:[f32] } f32:{ *:[f32] }:$src1, i32:{ *:[i32] }:$src1_mods), (VOP3Mods:{ *:[f32] } f32:{ *:[f32] }:$src0, i32:{ *:[i32] }:$src0_mods)), (VOP3Mods:{ *:[f32] } f32:{ *:[f32] }:$src2, i32:{ *:[i32] }:$src2_mods)), (fmaxnum:{ *:[f32] } (VOP3Mods:{ *:[f32] } f32:{ *:[f32] }:$src0, i32:{ *:[i32] }:$src0_mods), (VOP3Mods:{ *:[f32] } f32:{ *:[f32] }:$src1, i32:{ *:[i32] }:$src1_mods)))<<P:Predicate_fminnum_like_nnan>>  =>  (V_MED3_F32_e64:{ *:[f32] } ?:{ *:[i32] }:$src0_mods, ?:{ *:[f32] }:$src0, ?:{ *:[i32] }:$src1_mods, ?:{ *:[f32] }:$src1, ?:{ *:[i32] }:$src2_mods, ?:{ *:[f32] }:$src2, 0:{ *:[i1] }, 0:{ *:[i32] })
        GIR_BuildMI, /*InsnID*/0, /*Opcode*/GIMT_Encode2(AMDGPU::V_MED3_F32_e64),
        GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/0, // DstI[vdst]
        GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(1), /*SubOperand*/1, // src0_mods
        GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(1), /*SubOperand*/0, // src0
        GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/1, // src1_mods
        GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/0, // src1
        GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(2), /*SubOperand*/1, // src2_mods
        GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(2), /*SubOperand*/0, // src2
        GIR_AddImm8, /*InsnID*/0, /*Imm*/0,
        GIR_AddImm8, /*InsnID*/0, /*Imm*/0,
        GIR_ConstrainSelectedInstOperands, /*InsnID*/0,
        GIR_EraseFromParent, /*InsnID*/0,
        // GIR_Coverage, 10309,
        GIR_Done,
      // Label 4893: @344737
      GIM_Try, /*On fail goto*//*Label 4894*/ GIMT_Encode4(344877), // Rule ID 10310 //
        GIM_CheckRegBankForClass, /*MI*/0, /*Op*/0, /*RC*/GIMT_Encode2(AMDGPU::VGPR_32RegClassID),
        GIM_RecordInsn, /*DefineMI*/1, /*MI*/0, /*OpIdx*/1, // MIs[1]
        GIM_CheckOpcode, /*MI*/1, GIMT_Encode2(TargetOpcode::G_FMAXNUM_IEEE),
        GIM_CheckType, /*MI*/1, /*Op*/1, /*Type*/GILLT_s32,
        GIM_CheckType, /*MI*/1, /*Op*/2, /*Type*/GILLT_s32,
        GIM_RecordInsn, /*DefineMI*/2, /*MI*/1, /*OpIdx*/1, // MIs[2]
        GIM_CheckOpcode, /*MI*/2, GIMT_Encode2(TargetOpcode::G_FMINNUM_IEEE),
        GIM_CheckType, /*MI*/2, /*Op*/1, /*Type*/GILLT_s32,
        GIM_CheckType, /*MI*/2, /*Op*/2, /*Type*/GILLT_s32,
        GIM_RecordInsn, /*DefineMI*/3, /*MI*/0, /*OpIdx*/2, // MIs[3]
        GIM_CheckOpcode, /*MI*/3, GIMT_Encode2(TargetOpcode::G_FMAXNUM),
        // MIs[3] VOP3Mods:src1:src1_mods
        GIM_CheckIsSameOperand, /*MI*/3, /*OpIdx*/1, /*OtherMI*/2, /*OtherOpIdx*/1,
        // MIs[3] VOP3Mods:src0:src0_mods
        GIM_CheckIsSameOperand, /*MI*/3, /*OpIdx*/2, /*OtherMI*/2, /*OtherOpIdx*/2,
        GIM_CheckCxxInsnPredicate, /*MI*/0, /*FnId*/GIMT_Encode2(GICXXPred_MI_Predicate_fminnum_like_nnan),
        GIM_CheckIsSafeToFold, /*InsnID*/1,
        GIM_CheckIsSafeToFold, /*InsnID*/2,
        GIM_CheckIsSafeToFold, /*InsnID*/3,
        GIM_CheckComplexPattern, /*MI*/1, /*Op*/2, /*Renderer*/GIMT_Encode2(2), GIMT_Encode2(GICP_gi_vop3mods),
        GIM_CheckComplexPattern, /*MI*/2, /*Op*/1, /*Renderer*/GIMT_Encode2(0), GIMT_Encode2(GICP_gi_vop3mods),
        GIM_CheckComplexPattern, /*MI*/2, /*Op*/2, /*Renderer*/GIMT_Encode2(1), GIMT_Encode2(GICP_gi_vop3mods),
        // (fminnum_ieee:{ *:[f32] } (fmaxnum_ieee:{ *:[f32] } (fminnum_ieee:{ *:[f32] } (VOP3Mods:{ *:[f32] } f32:{ *:[f32] }:$src1, i32:{ *:[i32] }:$src1_mods), (VOP3Mods:{ *:[f32] } f32:{ *:[f32] }:$src0, i32:{ *:[i32] }:$src0_mods)), (VOP3Mods:{ *:[f32] } f32:{ *:[f32] }:$src2, i32:{ *:[i32] }:$src2_mods)), (fmaxnum:{ *:[f32] } (VOP3Mods:{ *:[f32] } f32:{ *:[f32] }:$src1, i32:{ *:[i32] }:$src1_mods), (VOP3Mods:{ *:[f32] } f32:{ *:[f32] }:$src0, i32:{ *:[i32] }:$src0_mods)))<<P:Predicate_fminnum_like_nnan>>  =>  (V_MED3_F32_e64:{ *:[f32] } ?:{ *:[i32] }:$src0_mods, ?:{ *:[f32] }:$src0, ?:{ *:[i32] }:$src1_mods, ?:{ *:[f32] }:$src1, ?:{ *:[i32] }:$src2_mods, ?:{ *:[f32] }:$src2, 0:{ *:[i1] }, 0:{ *:[i32] })
        GIR_BuildMI, /*InsnID*/0, /*Opcode*/GIMT_Encode2(AMDGPU::V_MED3_F32_e64),
        GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/0, // DstI[vdst]
        GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(1), /*SubOperand*/1, // src0_mods
        GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(1), /*SubOperand*/0, // src0
        GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/1, // src1_mods
        GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/0, // src1
        GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(2), /*SubOperand*/1, // src2_mods
        GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(2), /*SubOperand*/0, // src2
        GIR_AddImm8, /*InsnID*/0, /*Imm*/0,
        GIR_AddImm8, /*InsnID*/0, /*Imm*/0,
        GIR_ConstrainSelectedInstOperands, /*InsnID*/0,
        GIR_EraseFromParent, /*InsnID*/0,
        // GIR_Coverage, 10310,
        GIR_Done,
      // Label 4894: @344877
      GIM_Try, /*On fail goto*//*Label 4895*/ GIMT_Encode4(345017), // Rule ID 10247 //
        GIM_CheckRegBankForClass, /*MI*/0, /*Op*/0, /*RC*/GIMT_Encode2(AMDGPU::VGPR_32RegClassID),
        GIM_RecordInsn, /*DefineMI*/1, /*MI*/0, /*OpIdx*/1, // MIs[1]
        GIM_CheckOpcode, /*MI*/1, GIMT_Encode2(TargetOpcode::G_FMAXNUM_IEEE),
        GIM_CheckType, /*MI*/1, /*Op*/1, /*Type*/GILLT_s32,
        GIM_CheckType, /*MI*/1, /*Op*/2, /*Type*/GILLT_s32,
        GIM_RecordInsn, /*DefineMI*/2, /*MI*/1, /*OpIdx*/1, // MIs[2]
        GIM_CheckOpcode, /*MI*/2, GIMT_Encode2(TargetOpcode::G_FMINNUM_IEEE),
        GIM_CheckType, /*MI*/2, /*Op*/1, /*Type*/GILLT_s32,
        GIM_CheckType, /*MI*/2, /*Op*/2, /*Type*/GILLT_s32,
        GIM_RecordInsn, /*DefineMI*/3, /*MI*/0, /*OpIdx*/2, // MIs[3]
        GIM_CheckOpcode, /*MI*/3, GIMT_Encode2(TargetOpcode::G_FMAXNUM_IEEE),
        // MIs[3] VOP3Mods:src0:src0_mods
        GIM_CheckIsSameOperand, /*MI*/3, /*OpIdx*/1, /*OtherMI*/2, /*OtherOpIdx*/1,
        // MIs[3] VOP3Mods:src1:src1_mods
        GIM_CheckIsSameOperand, /*MI*/3, /*OpIdx*/2, /*OtherMI*/2, /*OtherOpIdx*/2,
        GIM_CheckCxxInsnPredicate, /*MI*/0, /*FnId*/GIMT_Encode2(GICXXPred_MI_Predicate_fminnum_like_nnan),
        GIM_CheckIsSafeToFold, /*InsnID*/1,
        GIM_CheckIsSafeToFold, /*InsnID*/2,
        GIM_CheckIsSafeToFold, /*InsnID*/3,
        GIM_CheckComplexPattern, /*MI*/1, /*Op*/2, /*Renderer*/GIMT_Encode2(2), GIMT_Encode2(GICP_gi_vop3mods),
        GIM_CheckComplexPattern, /*MI*/2, /*Op*/1, /*Renderer*/GIMT_Encode2(0), GIMT_Encode2(GICP_gi_vop3mods),
        GIM_CheckComplexPattern, /*MI*/2, /*Op*/2, /*Renderer*/GIMT_Encode2(1), GIMT_Encode2(GICP_gi_vop3mods),
        // (fminnum_ieee:{ *:[f32] } (fmaxnum_ieee:{ *:[f32] } (fminnum_ieee:{ *:[f32] } (VOP3Mods:{ *:[f32] } f32:{ *:[f32] }:$src0, i32:{ *:[i32] }:$src0_mods), (VOP3Mods:{ *:[f32] } f32:{ *:[f32] }:$src1, i32:{ *:[i32] }:$src1_mods)), (VOP3Mods:{ *:[f32] } f32:{ *:[f32] }:$src2, i32:{ *:[i32] }:$src2_mods)), (fmaxnum_ieee:{ *:[f32] } (VOP3Mods:{ *:[f32] } f32:{ *:[f32] }:$src0, i32:{ *:[i32] }:$src0_mods), (VOP3Mods:{ *:[f32] } f32:{ *:[f32] }:$src1, i32:{ *:[i32] }:$src1_mods)))<<P:Predicate_fminnum_like_nnan>>  =>  (V_MED3_F32_e64:{ *:[f32] } ?:{ *:[i32] }:$src0_mods, ?:{ *:[f32] }:$src0, ?:{ *:[i32] }:$src1_mods, ?:{ *:[f32] }:$src1, ?:{ *:[i32] }:$src2_mods, ?:{ *:[f32] }:$src2, 0:{ *:[i1] }, 0:{ *:[i32] })
        GIR_BuildMI, /*InsnID*/0, /*Opcode*/GIMT_Encode2(AMDGPU::V_MED3_F32_e64),
        GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/0, // DstI[vdst]
        GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/1, // src0_mods
        GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/0, // src0
        GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(1), /*SubOperand*/1, // src1_mods
        GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(1), /*SubOperand*/0, // src1
        GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(2), /*SubOperand*/1, // src2_mods
        GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(2), /*SubOperand*/0, // src2
        GIR_AddImm8, /*InsnID*/0, /*Imm*/0,
        GIR_AddImm8, /*InsnID*/0, /*Imm*/0,
        GIR_ConstrainSelectedInstOperands, /*InsnID*/0,
        GIR_EraseFromParent, /*InsnID*/0,
        // GIR_Coverage, 10247,
        GIR_Done,
      // Label 4895: @345017
      GIM_Try, /*On fail goto*//*Label 4896*/ GIMT_Encode4(345157), // Rule ID 10248 //
        GIM_CheckRegBankForClass, /*MI*/0, /*Op*/0, /*RC*/GIMT_Encode2(AMDGPU::VGPR_32RegClassID),
        GIM_RecordInsn, /*DefineMI*/1, /*MI*/0, /*OpIdx*/1, // MIs[1]
        GIM_CheckOpcode, /*MI*/1, GIMT_Encode2(TargetOpcode::G_FMAXNUM_IEEE),
        GIM_CheckType, /*MI*/1, /*Op*/1, /*Type*/GILLT_s32,
        GIM_CheckType, /*MI*/1, /*Op*/2, /*Type*/GILLT_s32,
        GIM_RecordInsn, /*DefineMI*/2, /*MI*/1, /*OpIdx*/1, // MIs[2]
        GIM_CheckOpcode, /*MI*/2, GIMT_Encode2(TargetOpcode::G_FMINNUM_IEEE),
        GIM_CheckType, /*MI*/2, /*Op*/1, /*Type*/GILLT_s32,
        GIM_CheckType, /*MI*/2, /*Op*/2, /*Type*/GILLT_s32,
        GIM_RecordInsn, /*DefineMI*/3, /*MI*/0, /*OpIdx*/2, // MIs[3]
        GIM_CheckOpcode, /*MI*/3, GIMT_Encode2(TargetOpcode::G_FMAXNUM_IEEE),
        // MIs[3] VOP3Mods:src1:src1_mods
        GIM_CheckIsSameOperand, /*MI*/3, /*OpIdx*/1, /*OtherMI*/2, /*OtherOpIdx*/2,
        // MIs[3] VOP3Mods:src0:src0_mods
        GIM_CheckIsSameOperand, /*MI*/3, /*OpIdx*/2, /*OtherMI*/2, /*OtherOpIdx*/1,
        GIM_CheckCxxInsnPredicate, /*MI*/0, /*FnId*/GIMT_Encode2(GICXXPred_MI_Predicate_fminnum_like_nnan),
        GIM_CheckIsSafeToFold, /*InsnID*/1,
        GIM_CheckIsSafeToFold, /*InsnID*/2,
        GIM_CheckIsSafeToFold, /*InsnID*/3,
        GIM_CheckComplexPattern, /*MI*/1, /*Op*/2, /*Renderer*/GIMT_Encode2(2), GIMT_Encode2(GICP_gi_vop3mods),
        GIM_CheckComplexPattern, /*MI*/2, /*Op*/1, /*Renderer*/GIMT_Encode2(0), GIMT_Encode2(GICP_gi_vop3mods),
        GIM_CheckComplexPattern, /*MI*/2, /*Op*/2, /*Renderer*/GIMT_Encode2(1), GIMT_Encode2(GICP_gi_vop3mods),
        // (fminnum_ieee:{ *:[f32] } (fmaxnum_ieee:{ *:[f32] } (fminnum_ieee:{ *:[f32] } (VOP3Mods:{ *:[f32] } f32:{ *:[f32] }:$src0, i32:{ *:[i32] }:$src0_mods), (VOP3Mods:{ *:[f32] } f32:{ *:[f32] }:$src1, i32:{ *:[i32] }:$src1_mods)), (VOP3Mods:{ *:[f32] } f32:{ *:[f32] }:$src2, i32:{ *:[i32] }:$src2_mods)), (fmaxnum_ieee:{ *:[f32] } (VOP3Mods:{ *:[f32] } f32:{ *:[f32] }:$src1, i32:{ *:[i32] }:$src1_mods), (VOP3Mods:{ *:[f32] } f32:{ *:[f32] }:$src0, i32:{ *:[i32] }:$src0_mods)))<<P:Predicate_fminnum_like_nnan>>  =>  (V_MED3_F32_e64:{ *:[f32] } ?:{ *:[i32] }:$src0_mods, ?:{ *:[f32] }:$src0, ?:{ *:[i32] }:$src1_mods, ?:{ *:[f32] }:$src1, ?:{ *:[i32] }:$src2_mods, ?:{ *:[f32] }:$src2, 0:{ *:[i1] }, 0:{ *:[i32] })
        GIR_BuildMI, /*InsnID*/0, /*Opcode*/GIMT_Encode2(AMDGPU::V_MED3_F32_e64),
        GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/0, // DstI[vdst]
        GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/1, // src0_mods
        GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/0, // src0
        GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(1), /*SubOperand*/1, // src1_mods
        GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(1), /*SubOperand*/0, // src1
        GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(2), /*SubOperand*/1, // src2_mods
        GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(2), /*SubOperand*/0, // src2
        GIR_AddImm8, /*InsnID*/0, /*Imm*/0,
        GIR_AddImm8, /*InsnID*/0, /*Imm*/0,
        GIR_ConstrainSelectedInstOperands, /*InsnID*/0,
        GIR_EraseFromParent, /*InsnID*/0,
        // GIR_Coverage, 10248,
        GIR_Done,
      // Label 4896: @345157
      GIM_Try, /*On fail goto*//*Label 4897*/ GIMT_Encode4(345297), // Rule ID 10249 //
        GIM_CheckRegBankForClass, /*MI*/0, /*Op*/0, /*RC*/GIMT_Encode2(AMDGPU::VGPR_32RegClassID),
        GIM_RecordInsn, /*DefineMI*/1, /*MI*/0, /*OpIdx*/1, // MIs[1]
        GIM_CheckOpcode, /*MI*/1, GIMT_Encode2(TargetOpcode::G_FMAXNUM_IEEE),
        GIM_CheckType, /*MI*/1, /*Op*/1, /*Type*/GILLT_s32,
        GIM_CheckType, /*MI*/1, /*Op*/2, /*Type*/GILLT_s32,
        GIM_RecordInsn, /*DefineMI*/2, /*MI*/1, /*OpIdx*/1, // MIs[2]
        GIM_CheckOpcode, /*MI*/2, GIMT_Encode2(TargetOpcode::G_FMINNUM_IEEE),
        GIM_CheckType, /*MI*/2, /*Op*/1, /*Type*/GILLT_s32,
        GIM_CheckType, /*MI*/2, /*Op*/2, /*Type*/GILLT_s32,
        GIM_RecordInsn, /*DefineMI*/3, /*MI*/0, /*OpIdx*/2, // MIs[3]
        GIM_CheckOpcode, /*MI*/3, GIMT_Encode2(TargetOpcode::G_FMAXNUM_IEEE),
        // MIs[3] VOP3Mods:src0:src0_mods
        GIM_CheckIsSameOperand, /*MI*/3, /*OpIdx*/1, /*OtherMI*/2, /*OtherOpIdx*/2,
        // MIs[3] VOP3Mods:src1:src1_mods
        GIM_CheckIsSameOperand, /*MI*/3, /*OpIdx*/2, /*OtherMI*/2, /*OtherOpIdx*/1,
        GIM_CheckCxxInsnPredicate, /*MI*/0, /*FnId*/GIMT_Encode2(GICXXPred_MI_Predicate_fminnum_like_nnan),
        GIM_CheckIsSafeToFold, /*InsnID*/1,
        GIM_CheckIsSafeToFold, /*InsnID*/2,
        GIM_CheckIsSafeToFold, /*InsnID*/3,
        GIM_CheckComplexPattern, /*MI*/1, /*Op*/2, /*Renderer*/GIMT_Encode2(2), GIMT_Encode2(GICP_gi_vop3mods),
        GIM_CheckComplexPattern, /*MI*/2, /*Op*/1, /*Renderer*/GIMT_Encode2(0), GIMT_Encode2(GICP_gi_vop3mods),
        GIM_CheckComplexPattern, /*MI*/2, /*Op*/2, /*Renderer*/GIMT_Encode2(1), GIMT_Encode2(GICP_gi_vop3mods),
        // (fminnum_ieee:{ *:[f32] } (fmaxnum_ieee:{ *:[f32] } (fminnum_ieee:{ *:[f32] } (VOP3Mods:{ *:[f32] } f32:{ *:[f32] }:$src1, i32:{ *:[i32] }:$src1_mods), (VOP3Mods:{ *:[f32] } f32:{ *:[f32] }:$src0, i32:{ *:[i32] }:$src0_mods)), (VOP3Mods:{ *:[f32] } f32:{ *:[f32] }:$src2, i32:{ *:[i32] }:$src2_mods)), (fmaxnum_ieee:{ *:[f32] } (VOP3Mods:{ *:[f32] } f32:{ *:[f32] }:$src0, i32:{ *:[i32] }:$src0_mods), (VOP3Mods:{ *:[f32] } f32:{ *:[f32] }:$src1, i32:{ *:[i32] }:$src1_mods)))<<P:Predicate_fminnum_like_nnan>>  =>  (V_MED3_F32_e64:{ *:[f32] } ?:{ *:[i32] }:$src0_mods, ?:{ *:[f32] }:$src0, ?:{ *:[i32] }:$src1_mods, ?:{ *:[f32] }:$src1, ?:{ *:[i32] }:$src2_mods, ?:{ *:[f32] }:$src2, 0:{ *:[i1] }, 0:{ *:[i32] })
        GIR_BuildMI, /*InsnID*/0, /*Opcode*/GIMT_Encode2(AMDGPU::V_MED3_F32_e64),
        GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/0, // DstI[vdst]
        GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(1), /*SubOperand*/1, // src0_mods
        GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(1), /*SubOperand*/0, // src0
        GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/1, // src1_mods
        GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/0, // src1
        GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(2), /*SubOperand*/1, // src2_mods
        GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(2), /*SubOperand*/0, // src2
        GIR_AddImm8, /*InsnID*/0, /*Imm*/0,
        GIR_AddImm8, /*InsnID*/0, /*Imm*/0,
        GIR_ConstrainSelectedInstOperands, /*InsnID*/0,
        GIR_EraseFromParent, /*InsnID*/0,
        // GIR_Coverage, 10249,
        GIR_Done,
      // Label 4897: @345297
      GIM_Try, /*On fail goto*//*Label 4898*/ GIMT_Encode4(345437), // Rule ID 10250 //
        GIM_CheckRegBankForClass, /*MI*/0, /*Op*/0, /*RC*/GIMT_Encode2(AMDGPU::VGPR_32RegClassID),
        GIM_RecordInsn, /*DefineMI*/1, /*MI*/0, /*OpIdx*/1, // MIs[1]
        GIM_CheckOpcode, /*MI*/1, GIMT_Encode2(TargetOpcode::G_FMAXNUM_IEEE),
        GIM_CheckType, /*MI*/1, /*Op*/1, /*Type*/GILLT_s32,
        GIM_CheckType, /*MI*/1, /*Op*/2, /*Type*/GILLT_s32,
        GIM_RecordInsn, /*DefineMI*/2, /*MI*/1, /*OpIdx*/1, // MIs[2]
        GIM_CheckOpcode, /*MI*/2, GIMT_Encode2(TargetOpcode::G_FMINNUM_IEEE),
        GIM_CheckType, /*MI*/2, /*Op*/1, /*Type*/GILLT_s32,
        GIM_CheckType, /*MI*/2, /*Op*/2, /*Type*/GILLT_s32,
        GIM_RecordInsn, /*DefineMI*/3, /*MI*/0, /*OpIdx*/2, // MIs[3]
        GIM_CheckOpcode, /*MI*/3, GIMT_Encode2(TargetOpcode::G_FMAXNUM_IEEE),
        // MIs[3] VOP3Mods:src1:src1_mods
        GIM_CheckIsSameOperand, /*MI*/3, /*OpIdx*/1, /*OtherMI*/2, /*OtherOpIdx*/1,
        // MIs[3] VOP3Mods:src0:src0_mods
        GIM_CheckIsSameOperand, /*MI*/3, /*OpIdx*/2, /*OtherMI*/2, /*OtherOpIdx*/2,
        GIM_CheckCxxInsnPredicate, /*MI*/0, /*FnId*/GIMT_Encode2(GICXXPred_MI_Predicate_fminnum_like_nnan),
        GIM_CheckIsSafeToFold, /*InsnID*/1,
        GIM_CheckIsSafeToFold, /*InsnID*/2,
        GIM_CheckIsSafeToFold, /*InsnID*/3,
        GIM_CheckComplexPattern, /*MI*/1, /*Op*/2, /*Renderer*/GIMT_Encode2(2), GIMT_Encode2(GICP_gi_vop3mods),
        GIM_CheckComplexPattern, /*MI*/2, /*Op*/1, /*Renderer*/GIMT_Encode2(0), GIMT_Encode2(GICP_gi_vop3mods),
        GIM_CheckComplexPattern, /*MI*/2, /*Op*/2, /*Renderer*/GIMT_Encode2(1), GIMT_Encode2(GICP_gi_vop3mods),
        // (fminnum_ieee:{ *:[f32] } (fmaxnum_ieee:{ *:[f32] } (fminnum_ieee:{ *:[f32] } (VOP3Mods:{ *:[f32] } f32:{ *:[f32] }:$src1, i32:{ *:[i32] }:$src1_mods), (VOP3Mods:{ *:[f32] } f32:{ *:[f32] }:$src0, i32:{ *:[i32] }:$src0_mods)), (VOP3Mods:{ *:[f32] } f32:{ *:[f32] }:$src2, i32:{ *:[i32] }:$src2_mods)), (fmaxnum_ieee:{ *:[f32] } (VOP3Mods:{ *:[f32] } f32:{ *:[f32] }:$src1, i32:{ *:[i32] }:$src1_mods), (VOP3Mods:{ *:[f32] } f32:{ *:[f32] }:$src0, i32:{ *:[i32] }:$src0_mods)))<<P:Predicate_fminnum_like_nnan>>  =>  (V_MED3_F32_e64:{ *:[f32] } ?:{ *:[i32] }:$src0_mods, ?:{ *:[f32] }:$src0, ?:{ *:[i32] }:$src1_mods, ?:{ *:[f32] }:$src1, ?:{ *:[i32] }:$src2_mods, ?:{ *:[f32] }:$src2, 0:{ *:[i1] }, 0:{ *:[i32] })
        GIR_BuildMI, /*InsnID*/0, /*Opcode*/GIMT_Encode2(AMDGPU::V_MED3_F32_e64),
        GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/0, // DstI[vdst]
        GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(1), /*SubOperand*/1, // src0_mods
        GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(1), /*SubOperand*/0, // src0
        GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/1, // src1_mods
        GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/0, // src1
        GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(2), /*SubOperand*/1, // src2_mods
        GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(2), /*SubOperand*/0, // src2
        GIR_AddImm8, /*InsnID*/0, /*Imm*/0,
        GIR_AddImm8, /*InsnID*/0, /*Imm*/0,
        GIR_ConstrainSelectedInstOperands, /*InsnID*/0,
        GIR_EraseFromParent, /*InsnID*/0,
        // GIR_Coverage, 10250,
        GIR_Done,
      // Label 4898: @345437
      GIM_Try, /*On fail goto*//*Label 4899*/ GIMT_Encode4(345542), // Rule ID 10519 //
        GIM_CheckFeatures, GIMT_Encode2(GIFBS_isGFX11Plus),
        GIM_CheckRegBankForClass, /*MI*/0, /*Op*/0, /*RC*/GIMT_Encode2(AMDGPU::VGPR_32RegClassID),
        GIM_RecordInsn, /*DefineMI*/1, /*MI*/0, /*OpIdx*/2, // MIs[1]
        GIM_CheckOpcode, /*MI*/1, GIMT_Encode2(TargetOpcode::G_FMAXNUM),
        GIM_CheckType, /*MI*/1, /*Op*/1, /*Type*/GILLT_s32,
        GIM_CheckType, /*MI*/1, /*Op*/2, /*Type*/GILLT_s32,
        GIM_CheckCxxInsnPredicate, /*MI*/1, /*FnId*/GIMT_Encode2(GICXXPred_MI_Predicate_fmaxnum_oneuse),
        GIM_CheckIsSafeToFold, /*InsnID*/1,
        GIM_CheckComplexPattern, /*MI*/0, /*Op*/1, /*Renderer*/GIMT_Encode2(0), GIMT_Encode2(GICP_gi_vop3mods),
        GIM_CheckComplexPattern, /*MI*/1, /*Op*/1, /*Renderer*/GIMT_Encode2(1), GIMT_Encode2(GICP_gi_vop3mods),
        GIM_CheckComplexPattern, /*MI*/1, /*Op*/2, /*Renderer*/GIMT_Encode2(2), GIMT_Encode2(GICP_gi_vop3mods),
        // (fminnum_ieee:{ *:[f32] } (VOP3Mods:{ *:[f32] } f32:{ *:[f32] }:$src2, i32:{ *:[i32] }:$src2_mods), (fmaxnum:{ *:[f32] } (VOP3Mods:{ *:[f32] } f32:{ *:[f32] }:$src0, i32:{ *:[i32] }:$src0_mods), (VOP3Mods:{ *:[f32] } f32:{ *:[f32] }:$src1, i32:{ *:[i32] }:$src1_mods))<<P:Predicate_fmaxnum_oneuse>>)  =>  (V_MAXMIN_F32_e64:{ *:[f32] } ?:{ *:[i32] }:$src0_mods, ?:{ *:[f32] }:$src0, ?:{ *:[i32] }:$src1_mods, ?:{ *:[f32] }:$src1, ?:{ *:[i32] }:$src2_mods, ?:{ *:[f32] }:$src2, 0:{ *:[i1] }, 0:{ *:[i32] })
        GIR_BuildMI, /*InsnID*/0, /*Opcode*/GIMT_Encode2(AMDGPU::V_MAXMIN_F32_e64),
        GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/0, // DstI[vdst]
        GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(1), /*SubOperand*/1, // src0_mods
        GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(1), /*SubOperand*/0, // src0
        GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(2), /*SubOperand*/1, // src1_mods
        GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(2), /*SubOperand*/0, // src1
        GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/1, // src2_mods
        GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/0, // src2
        GIR_AddImm8, /*InsnID*/0, /*Imm*/0,
        GIR_AddImm8, /*InsnID*/0, /*Imm*/0,
        GIR_ConstrainSelectedInstOperands, /*InsnID*/0,
        GIR_EraseFromParent, /*InsnID*/0,
        // GIR_Coverage, 10519,
        GIR_Done,
      // Label 4899: @345542
      GIM_Try, /*On fail goto*//*Label 4900*/ GIMT_Encode4(345647), // Rule ID 10518 //
        GIM_CheckFeatures, GIMT_Encode2(GIFBS_isGFX11Plus),
        GIM_CheckRegBankForClass, /*MI*/0, /*Op*/0, /*RC*/GIMT_Encode2(AMDGPU::VGPR_32RegClassID),
        GIM_RecordInsn, /*DefineMI*/1, /*MI*/0, /*OpIdx*/2, // MIs[1]
        GIM_CheckOpcode, /*MI*/1, GIMT_Encode2(TargetOpcode::G_FMAXNUM_IEEE),
        GIM_CheckType, /*MI*/1, /*Op*/1, /*Type*/GILLT_s32,
        GIM_CheckType, /*MI*/1, /*Op*/2, /*Type*/GILLT_s32,
        GIM_CheckCxxInsnPredicate, /*MI*/1, /*FnId*/GIMT_Encode2(GICXXPred_MI_Predicate_fmaxnum_ieee_oneuse),
        GIM_CheckIsSafeToFold, /*InsnID*/1,
        GIM_CheckComplexPattern, /*MI*/0, /*Op*/1, /*Renderer*/GIMT_Encode2(0), GIMT_Encode2(GICP_gi_vop3mods),
        GIM_CheckComplexPattern, /*MI*/1, /*Op*/1, /*Renderer*/GIMT_Encode2(1), GIMT_Encode2(GICP_gi_vop3mods),
        GIM_CheckComplexPattern, /*MI*/1, /*Op*/2, /*Renderer*/GIMT_Encode2(2), GIMT_Encode2(GICP_gi_vop3mods),
        // (fminnum_ieee:{ *:[f32] } (VOP3Mods:{ *:[f32] } f32:{ *:[f32] }:$src2, i32:{ *:[i32] }:$src2_mods), (fmaxnum_ieee:{ *:[f32] } (VOP3Mods:{ *:[f32] } f32:{ *:[f32] }:$src0, i32:{ *:[i32] }:$src0_mods), (VOP3Mods:{ *:[f32] } f32:{ *:[f32] }:$src1, i32:{ *:[i32] }:$src1_mods))<<P:Predicate_fmaxnum_ieee_oneuse>>)  =>  (V_MAXMIN_F32_e64:{ *:[f32] } ?:{ *:[i32] }:$src0_mods, ?:{ *:[f32] }:$src0, ?:{ *:[i32] }:$src1_mods, ?:{ *:[f32] }:$src1, ?:{ *:[i32] }:$src2_mods, ?:{ *:[f32] }:$src2, 0:{ *:[i1] }, 0:{ *:[i32] })
        GIR_BuildMI, /*InsnID*/0, /*Opcode*/GIMT_Encode2(AMDGPU::V_MAXMIN_F32_e64),
        GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/0, // DstI[vdst]
        GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(1), /*SubOperand*/1, // src0_mods
        GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(1), /*SubOperand*/0, // src0
        GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(2), /*SubOperand*/1, // src1_mods
        GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(2), /*SubOperand*/0, // src1
        GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/1, // src2_mods
        GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/0, // src2
        GIR_AddImm8, /*InsnID*/0, /*Imm*/0,
        GIR_AddImm8, /*InsnID*/0, /*Imm*/0,
        GIR_ConstrainSelectedInstOperands, /*InsnID*/0,
        GIR_EraseFromParent, /*InsnID*/0,
        // GIR_Coverage, 10518,
        GIR_Done,
      // Label 4900: @345647
      GIM_Try, /*On fail goto*//*Label 4901*/ GIMT_Encode4(345752), // Rule ID 6525 //
        GIM_CheckFeatures, GIMT_Encode2(GIFBS_isGFX11Plus),
        GIM_CheckRegBankForClass, /*MI*/0, /*Op*/0, /*RC*/GIMT_Encode2(AMDGPU::VGPR_32RegClassID),
        GIM_RecordInsn, /*DefineMI*/1, /*MI*/0, /*OpIdx*/1, // MIs[1]
        GIM_CheckOpcode, /*MI*/1, GIMT_Encode2(TargetOpcode::G_FMAXNUM),
        GIM_CheckType, /*MI*/1, /*Op*/1, /*Type*/GILLT_s32,
        GIM_CheckType, /*MI*/1, /*Op*/2, /*Type*/GILLT_s32,
        GIM_CheckCxxInsnPredicate, /*MI*/1, /*FnId*/GIMT_Encode2(GICXXPred_MI_Predicate_fmaxnum_oneuse),
        GIM_CheckIsSafeToFold, /*InsnID*/1,
        GIM_CheckComplexPattern, /*MI*/0, /*Op*/2, /*Renderer*/GIMT_Encode2(2), GIMT_Encode2(GICP_gi_vop3mods),
        GIM_CheckComplexPattern, /*MI*/1, /*Op*/1, /*Renderer*/GIMT_Encode2(0), GIMT_Encode2(GICP_gi_vop3mods),
        GIM_CheckComplexPattern, /*MI*/1, /*Op*/2, /*Renderer*/GIMT_Encode2(1), GIMT_Encode2(GICP_gi_vop3mods),
        // (fminnum_ieee:{ *:[f32] } (fmaxnum:{ *:[f32] } (VOP3Mods:{ *:[f32] } f32:{ *:[f32] }:$src0, i32:{ *:[i32] }:$src0_mods), (VOP3Mods:{ *:[f32] } f32:{ *:[f32] }:$src1, i32:{ *:[i32] }:$src1_mods))<<P:Predicate_fmaxnum_oneuse>>, (VOP3Mods:{ *:[f32] } f32:{ *:[f32] }:$src2, i32:{ *:[i32] }:$src2_mods))  =>  (V_MAXMIN_F32_e64:{ *:[f32] } ?:{ *:[i32] }:$src0_mods, ?:{ *:[f32] }:$src0, ?:{ *:[i32] }:$src1_mods, ?:{ *:[f32] }:$src1, ?:{ *:[i32] }:$src2_mods, ?:{ *:[f32] }:$src2, 0:{ *:[i1] }, 0:{ *:[i32] })
        GIR_BuildMI, /*InsnID*/0, /*Opcode*/GIMT_Encode2(AMDGPU::V_MAXMIN_F32_e64),
        GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/0, // DstI[vdst]
        GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/1, // src0_mods
        GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/0, // src0
        GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(1), /*SubOperand*/1, // src1_mods
        GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(1), /*SubOperand*/0, // src1
        GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(2), /*SubOperand*/1, // src2_mods
        GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(2), /*SubOperand*/0, // src2
        GIR_AddImm8, /*InsnID*/0, /*Imm*/0,
        GIR_AddImm8, /*InsnID*/0, /*Imm*/0,
        GIR_ConstrainSelectedInstOperands, /*InsnID*/0,
        GIR_EraseFromParent, /*InsnID*/0,
        // GIR_Coverage, 6525,
        GIR_Done,
      // Label 4901: @345752
      GIM_Try, /*On fail goto*//*Label 4902*/ GIMT_Encode4(345857), // Rule ID 6524 //
        GIM_CheckFeatures, GIMT_Encode2(GIFBS_isGFX11Plus),
        GIM_CheckRegBankForClass, /*MI*/0, /*Op*/0, /*RC*/GIMT_Encode2(AMDGPU::VGPR_32RegClassID),
        GIM_RecordInsn, /*DefineMI*/1, /*MI*/0, /*OpIdx*/1, // MIs[1]
        GIM_CheckOpcode, /*MI*/1, GIMT_Encode2(TargetOpcode::G_FMAXNUM_IEEE),
        GIM_CheckType, /*MI*/1, /*Op*/1, /*Type*/GILLT_s32,
        GIM_CheckType, /*MI*/1, /*Op*/2, /*Type*/GILLT_s32,
        GIM_CheckCxxInsnPredicate, /*MI*/1, /*FnId*/GIMT_Encode2(GICXXPred_MI_Predicate_fmaxnum_ieee_oneuse),
        GIM_CheckIsSafeToFold, /*InsnID*/1,
        GIM_CheckComplexPattern, /*MI*/0, /*Op*/2, /*Renderer*/GIMT_Encode2(2), GIMT_Encode2(GICP_gi_vop3mods),
        GIM_CheckComplexPattern, /*MI*/1, /*Op*/1, /*Renderer*/GIMT_Encode2(0), GIMT_Encode2(GICP_gi_vop3mods),
        GIM_CheckComplexPattern, /*MI*/1, /*Op*/2, /*Renderer*/GIMT_Encode2(1), GIMT_Encode2(GICP_gi_vop3mods),
        // (fminnum_ieee:{ *:[f32] } (fmaxnum_ieee:{ *:[f32] } (VOP3Mods:{ *:[f32] } f32:{ *:[f32] }:$src0, i32:{ *:[i32] }:$src0_mods), (VOP3Mods:{ *:[f32] } f32:{ *:[f32] }:$src1, i32:{ *:[i32] }:$src1_mods))<<P:Predicate_fmaxnum_ieee_oneuse>>, (VOP3Mods:{ *:[f32] } f32:{ *:[f32] }:$src2, i32:{ *:[i32] }:$src2_mods))  =>  (V_MAXMIN_F32_e64:{ *:[f32] } ?:{ *:[i32] }:$src0_mods, ?:{ *:[f32] }:$src0, ?:{ *:[i32] }:$src1_mods, ?:{ *:[f32] }:$src1, ?:{ *:[i32] }:$src2_mods, ?:{ *:[f32] }:$src2, 0:{ *:[i1] }, 0:{ *:[i32] })
        GIR_BuildMI, /*InsnID*/0, /*Opcode*/GIMT_Encode2(AMDGPU::V_MAXMIN_F32_e64),
        GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/0, // DstI[vdst]
        GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/1, // src0_mods
        GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/0, // src0
        GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(1), /*SubOperand*/1, // src1_mods
        GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(1), /*SubOperand*/0, // src1
        GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(2), /*SubOperand*/1, // src2_mods
        GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(2), /*SubOperand*/0, // src2
        GIR_AddImm8, /*InsnID*/0, /*Imm*/0,
        GIR_AddImm8, /*InsnID*/0, /*Imm*/0,
        GIR_ConstrainSelectedInstOperands, /*InsnID*/0,
        GIR_EraseFromParent, /*InsnID*/0,
        // GIR_Coverage, 6524,
        GIR_Done,
      // Label 4902: @345857
      GIM_Try, /*On fail goto*//*Label 4903*/ GIMT_Encode4(345896), // Rule ID 92 //
        GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasSALUFloatInsts),
        GIM_CheckRegBankForClass, /*MI*/0, /*Op*/0, /*RC*/GIMT_Encode2(AMDGPU::SReg_32RegClassID),
        GIM_CheckRegBankForClass, /*MI*/0, /*Op*/1, /*RC*/GIMT_Encode2(AMDGPU::SReg_32RegClassID),
        GIM_CheckRegBankForClass, /*MI*/0, /*Op*/2, /*RC*/GIMT_Encode2(AMDGPU::SReg_32RegClassID),
        GIM_CheckCxxInsnPredicate, /*MI*/0, /*FnId*/GIMT_Encode2(GICXXPred_MI_Predicate_anonymous_17631),
        // (fminnum_ieee:{ *:[f32] } SSrc_f32:{ *:[f32] }:$src0, SSrc_f32:{ *:[f32] }:$src1)<<P:Predicate_anonymous_17631>>  =>  (S_MIN_F32:{ *:[f32] } SSrc_f32:{ *:[f32] }:$src0, SSrc_f32:{ *:[f32] }:$src1)
        GIR_MutateOpcode, /*InsnID*/0, /*RecycleInsnID*/0, /*Opcode*/GIMT_Encode2(AMDGPU::S_MIN_F32),
        GIR_AddImplicitUse, /*InsnID*/0, GIMT_Encode2(AMDGPU::MODE),
        GIR_ConstrainSelectedInstOperands, /*InsnID*/0,
        // GIR_Coverage, 92,
        GIR_Done,
      // Label 4903: @345896
      GIM_Try, /*On fail goto*//*Label 4904*/ GIMT_Encode4(345963), // Rule ID 739 //
        GIM_CheckRegBankForClass, /*MI*/0, /*Op*/0, /*RC*/GIMT_Encode2(AMDGPU::VGPR_32RegClassID),
        GIM_CheckComplexPattern, /*MI*/0, /*Op*/1, /*Renderer*/GIMT_Encode2(0), GIMT_Encode2(GICP_gi_vop3mods0),
        GIM_CheckComplexPattern, /*MI*/0, /*Op*/2, /*Renderer*/GIMT_Encode2(1), GIMT_Encode2(GICP_gi_vop3mods),
        // (fminnum_ieee:{ *:[f32] } (VOP3Mods0:{ *:[f32] } f32:{ *:[f32] }:$src0, i32:{ *:[i32] }:$src0_modifiers, i1:{ *:[i1] }:$clamp, i32:{ *:[i32] }:$omod), (VOP3Mods:{ *:[f32] } f32:{ *:[f32] }:$src1, i32:{ *:[i32] }:$src1_modifiers))  =>  (V_MIN_F32_e64:{ *:[f32] } i32:{ *:[i32] }:$src0_modifiers, f32:{ *:[f32] }:$src0, i32:{ *:[i32] }:$src1_modifiers, f32:{ *:[f32] }:$src1, i1:{ *:[i1] }:$clamp, i32:{ *:[i32] }:$omod)
        GIR_BuildMI, /*InsnID*/0, /*Opcode*/GIMT_Encode2(AMDGPU::V_MIN_F32_e64),
        GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/0, // DstI[vdst]
        GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/1, // src0_modifiers
        GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/0, // src0
        GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(1), /*SubOperand*/1, // src1_modifiers
        GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(1), /*SubOperand*/0, // src1
        GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/2, // clamp
        GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/3, // omod
        GIR_ConstrainSelectedInstOperands, /*InsnID*/0,
        GIR_EraseFromParent, /*InsnID*/0,
        // GIR_Coverage, 739,
        GIR_Done,
      // Label 4904: @345963
      GIM_Try, /*On fail goto*//*Label 4905*/ GIMT_Encode4(346030), // Rule ID 7131 //
        GIM_CheckRegBankForClass, /*MI*/0, /*Op*/0, /*RC*/GIMT_Encode2(AMDGPU::VGPR_32RegClassID),
        GIM_CheckComplexPattern, /*MI*/0, /*Op*/1, /*Renderer*/GIMT_Encode2(0), GIMT_Encode2(GICP_gi_vop3mods),
        GIM_CheckComplexPattern, /*MI*/0, /*Op*/2, /*Renderer*/GIMT_Encode2(1), GIMT_Encode2(GICP_gi_vop3mods0),
        // (fminnum_ieee:{ *:[f32] } (VOP3Mods:{ *:[f32] } f32:{ *:[f32] }:$src1, i32:{ *:[i32] }:$src1_modifiers), (VOP3Mods0:{ *:[f32] } f32:{ *:[f32] }:$src0, i32:{ *:[i32] }:$src0_modifiers, i1:{ *:[i1] }:$clamp, i32:{ *:[i32] }:$omod))  =>  (V_MIN_F32_e64:{ *:[f32] } i32:{ *:[i32] }:$src0_modifiers, f32:{ *:[f32] }:$src0, i32:{ *:[i32] }:$src1_modifiers, f32:{ *:[f32] }:$src1, i1:{ *:[i1] }:$clamp, i32:{ *:[i32] }:$omod)
        GIR_BuildMI, /*InsnID*/0, /*Opcode*/GIMT_Encode2(AMDGPU::V_MIN_F32_e64),
        GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/0, // DstI[vdst]
        GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(1), /*SubOperand*/1, // src0_modifiers
        GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(1), /*SubOperand*/0, // src0
        GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/1, // src1_modifiers
        GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/0, // src1
        GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(1), /*SubOperand*/2, // clamp
        GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(1), /*SubOperand*/3, // omod
        GIR_ConstrainSelectedInstOperands, /*InsnID*/0,
        GIR_EraseFromParent, /*InsnID*/0,
        // GIR_Coverage, 7131,
        GIR_Done,
      // Label 4905: @346030
      GIM_Reject,
    // Label 4770: @346031
    GIM_Reject,
    // Label 4755: @346032
    GIM_Try, /*On fail goto*//*Label 4906*/ GIMT_Encode4(346311),
      GIM_CheckType, /*MI*/0, /*Op*/1, /*Type*/GILLT_s64,
      GIM_CheckType, /*MI*/0, /*Op*/2, /*Type*/GILLT_s64,
      GIM_CheckRegBankForClass, /*MI*/0, /*Op*/0, /*RC*/GIMT_Encode2(AMDGPU::VReg_64RegClassID),
      GIM_Try, /*On fail goto*//*Label 4907*/ GIMT_Encode4(346115), // Rule ID 842 //
        GIM_CheckFeatures, GIMT_Encode2(GIFBS_isGFX12Plus),
        GIM_CheckComplexPattern, /*MI*/0, /*Op*/1, /*Renderer*/GIMT_Encode2(0), GIMT_Encode2(GICP_gi_vop3mods0),
        GIM_CheckComplexPattern, /*MI*/0, /*Op*/2, /*Renderer*/GIMT_Encode2(1), GIMT_Encode2(GICP_gi_vop3mods),
        // (fminnum_ieee:{ *:[f64] } (VOP3Mods0:{ *:[f64] } f64:{ *:[f64] }:$src0, i32:{ *:[i32] }:$src0_modifiers, i1:{ *:[i1] }:$clamp, i32:{ *:[i32] }:$omod), (VOP3Mods:{ *:[f64] } f64:{ *:[f64] }:$src1, i32:{ *:[i32] }:$src1_modifiers))  =>  (V_MIN_NUM_F64_e64:{ *:[f64] } i32:{ *:[i32] }:$src0_modifiers, f64:{ *:[f64] }:$src0, i32:{ *:[i32] }:$src1_modifiers, f64:{ *:[f64] }:$src1, i1:{ *:[i1] }:$clamp, i32:{ *:[i32] }:$omod)
        GIR_BuildMI, /*InsnID*/0, /*Opcode*/GIMT_Encode2(AMDGPU::V_MIN_NUM_F64_e64),
        GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/0, // DstI[vdst]
        GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/1, // src0_modifiers
        GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/0, // src0
        GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(1), /*SubOperand*/1, // src1_modifiers
        GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(1), /*SubOperand*/0, // src1
        GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/2, // clamp
        GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/3, // omod
        GIR_ConstrainSelectedInstOperands, /*InsnID*/0,
        GIR_EraseFromParent, /*InsnID*/0,
        // GIR_Coverage, 842,
        GIR_Done,
      // Label 4907: @346115
      GIM_Try, /*On fail goto*//*Label 4908*/ GIMT_Encode4(346180), // Rule ID 861 //
        GIM_CheckFeatures, GIMT_Encode2(GIFBS_isNotGFX12Plus),
        GIM_CheckComplexPattern, /*MI*/0, /*Op*/1, /*Renderer*/GIMT_Encode2(0), GIMT_Encode2(GICP_gi_vop3mods0),
        GIM_CheckComplexPattern, /*MI*/0, /*Op*/2, /*Renderer*/GIMT_Encode2(1), GIMT_Encode2(GICP_gi_vop3mods),
        // (fminnum_ieee:{ *:[f64] } (VOP3Mods0:{ *:[f64] } f64:{ *:[f64] }:$src0, i32:{ *:[i32] }:$src0_modifiers, i1:{ *:[i1] }:$clamp, i32:{ *:[i32] }:$omod), (VOP3Mods:{ *:[f64] } f64:{ *:[f64] }:$src1, i32:{ *:[i32] }:$src1_modifiers))  =>  (V_MIN_F64_e64:{ *:[f64] } i32:{ *:[i32] }:$src0_modifiers, f64:{ *:[f64] }:$src0, i32:{ *:[i32] }:$src1_modifiers, f64:{ *:[f64] }:$src1, i1:{ *:[i1] }:$clamp, i32:{ *:[i32] }:$omod)
        GIR_BuildMI, /*InsnID*/0, /*Opcode*/GIMT_Encode2(AMDGPU::V_MIN_F64_e64),
        GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/0, // DstI[vdst]
        GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/1, // src0_modifiers
        GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/0, // src0
        GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(1), /*SubOperand*/1, // src1_modifiers
        GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(1), /*SubOperand*/0, // src1
        GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/2, // clamp
        GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/3, // omod
        GIR_ConstrainSelectedInstOperands, /*InsnID*/0,
        GIR_EraseFromParent, /*InsnID*/0,
        // GIR_Coverage, 861,
        GIR_Done,
      // Label 4908: @346180
      GIM_Try, /*On fail goto*//*Label 4909*/ GIMT_Encode4(346245), // Rule ID 7165 //
        GIM_CheckFeatures, GIMT_Encode2(GIFBS_isGFX12Plus),
        GIM_CheckComplexPattern, /*MI*/0, /*Op*/1, /*Renderer*/GIMT_Encode2(0), GIMT_Encode2(GICP_gi_vop3mods),
        GIM_CheckComplexPattern, /*MI*/0, /*Op*/2, /*Renderer*/GIMT_Encode2(1), GIMT_Encode2(GICP_gi_vop3mods0),
        // (fminnum_ieee:{ *:[f64] } (VOP3Mods:{ *:[f64] } f64:{ *:[f64] }:$src1, i32:{ *:[i32] }:$src1_modifiers), (VOP3Mods0:{ *:[f64] } f64:{ *:[f64] }:$src0, i32:{ *:[i32] }:$src0_modifiers, i1:{ *:[i1] }:$clamp, i32:{ *:[i32] }:$omod))  =>  (V_MIN_NUM_F64_e64:{ *:[f64] } i32:{ *:[i32] }:$src0_modifiers, f64:{ *:[f64] }:$src0, i32:{ *:[i32] }:$src1_modifiers, f64:{ *:[f64] }:$src1, i1:{ *:[i1] }:$clamp, i32:{ *:[i32] }:$omod)
        GIR_BuildMI, /*InsnID*/0, /*Opcode*/GIMT_Encode2(AMDGPU::V_MIN_NUM_F64_e64),
        GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/0, // DstI[vdst]
        GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(1), /*SubOperand*/1, // src0_modifiers
        GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(1), /*SubOperand*/0, // src0
        GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/1, // src1_modifiers
        GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/0, // src1
        GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(1), /*SubOperand*/2, // clamp
        GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(1), /*SubOperand*/3, // omod
        GIR_ConstrainSelectedInstOperands, /*InsnID*/0,
        GIR_EraseFromParent, /*InsnID*/0,
        // GIR_Coverage, 7165,
        GIR_Done,
      // Label 4909: @346245
      GIM_Try, /*On fail goto*//*Label 4910*/ GIMT_Encode4(346310), // Rule ID 7179 //
        GIM_CheckFeatures, GIMT_Encode2(GIFBS_isNotGFX12Plus),
        GIM_CheckComplexPattern, /*MI*/0, /*Op*/1, /*Renderer*/GIMT_Encode2(0), GIMT_Encode2(GICP_gi_vop3mods),
        GIM_CheckComplexPattern, /*MI*/0, /*Op*/2, /*Renderer*/GIMT_Encode2(1), GIMT_Encode2(GICP_gi_vop3mods0),
        // (fminnum_ieee:{ *:[f64] } (VOP3Mods:{ *:[f64] } f64:{ *:[f64] }:$src1, i32:{ *:[i32] }:$src1_modifiers), (VOP3Mods0:{ *:[f64] } f64:{ *:[f64] }:$src0, i32:{ *:[i32] }:$src0_modifiers, i1:{ *:[i1] }:$clamp, i32:{ *:[i32] }:$omod))  =>  (V_MIN_F64_e64:{ *:[f64] } i32:{ *:[i32] }:$src0_modifiers, f64:{ *:[f64] }:$src0, i32:{ *:[i32] }:$src1_modifiers, f64:{ *:[f64] }:$src1, i1:{ *:[i1] }:$clamp, i32:{ *:[i32] }:$omod)
        GIR_BuildMI, /*InsnID*/0, /*Opcode*/GIMT_Encode2(AMDGPU::V_MIN_F64_e64),
        GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/0, // DstI[vdst]
        GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(1), /*SubOperand*/1, // src0_modifiers
        GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(1), /*SubOperand*/0, // src0
        GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/1, // src1_modifiers
        GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/0, // src1
        GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(1), /*SubOperand*/2, // clamp
        GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(1), /*SubOperand*/3, // omod
        GIR_ConstrainSelectedInstOperands, /*InsnID*/0,
        GIR_EraseFromParent, /*InsnID*/0,
        // GIR_Coverage, 7179,
        GIR_Done,
      // Label 4910: @346310
      GIM_Reject,
    // Label 4906: @346311
    GIM_Reject,
    // Label 4756: @346312
    GIM_Try, /*On fail goto*//*Label 4911*/ GIMT_Encode4(346392), // Rule ID 966 //
      GIM_CheckType, /*MI*/0, /*Op*/1, /*Type*/GILLT_v2s16,
      GIM_CheckType, /*MI*/0, /*Op*/2, /*Type*/GILLT_v2s16,
      GIM_CheckRegBankForClass, /*MI*/0, /*Op*/0, /*RC*/GIMT_Encode2(AMDGPU::VGPR_32RegClassID),
      GIM_CheckComplexPattern, /*MI*/0, /*Op*/1, /*Renderer*/GIMT_Encode2(0), GIMT_Encode2(GICP_gi_vop3pmods),
      GIM_CheckComplexPattern, /*MI*/0, /*Op*/2, /*Renderer*/GIMT_Encode2(1), GIMT_Encode2(GICP_gi_vop3pmods),
      // (fminnum_ieee:{ *:[v2f16] } (VOP3PMods:{ *:[v2f16] } v2f16:{ *:[v2f16] }:$src0, i32:{ *:[i32] }:$src0_modifiers), (VOP3PMods:{ *:[v2f16] } v2f16:{ *:[v2f16] }:$src1, i32:{ *:[i32] }:$src1_modifiers))  =>  (V_PK_MIN_F16:{ *:[v2f16] } i32:{ *:[i32] }:$src0_modifiers, v2f16:{ *:[v2f16] }:$src0, i32:{ *:[i32] }:$src1_modifiers, v2f16:{ *:[v2f16] }:$src1)
      GIR_BuildMI, /*InsnID*/0, /*Opcode*/GIMT_Encode2(AMDGPU::V_PK_MIN_F16),
      GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/0, // DstI[vdst]
      GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/1, // src0_modifiers
      GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/0, // src0
      GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(1), /*SubOperand*/1, // src1_modifiers
      GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(1), /*SubOperand*/0, // src1
      GIR_AddImm8, /*InsnID*/0, /*Imm*/0,
      GIR_AddImm8, /*InsnID*/0, /*Imm*/0,
      GIR_AddImm8, /*InsnID*/0, /*Imm*/0,
      GIR_AddImm8, /*InsnID*/0, /*Imm*/0,
      GIR_AddImm8, /*InsnID*/0, /*Imm*/0,
      GIR_ConstrainSelectedInstOperands, /*InsnID*/0,
      GIR_EraseFromParent, /*InsnID*/0,
      // GIR_Coverage, 966,
      GIR_Done,
    // Label 4911: @346392
    GIM_Reject,
    // Label 4757: @346393
    GIM_Reject,
    // Label 79: @346394
    GIM_SwitchType, /*MI*/0, /*Op*/0, /*[*/GIMT_Encode2(8), GIMT_Encode2(12), /*)*//*default:*//*Label 4916*/ GIMT_Encode4(384892),
    /*GILLT_s16*//*Label 4912*/ GIMT_Encode4(346421),
    /*GILLT_s32*//*Label 4913*/ GIMT_Encode4(366003),
    /*GILLT_s64*//*Label 4914*/ GIMT_Encode4(384531),
    /*GILLT_v2s16*//*Label 4915*/ GIMT_Encode4(384811),
    // Label 4912: @346421
    GIM_Try, /*On fail goto*//*Label 4917*/ GIMT_Encode4(366002),
      GIM_CheckType, /*MI*/0, /*Op*/1, /*Type*/GILLT_s16,
      GIM_CheckType, /*MI*/0, /*Op*/2, /*Type*/GILLT_s16,
      GIM_Try, /*On fail goto*//*Label 4918*/ GIMT_Encode4(346580), // Rule ID 10636 //
        GIM_CheckFeatures, GIMT_Encode2(GIFBS_isGFX9Plus),
        GIM_CheckRegBankForClass, /*MI*/0, /*Op*/0, /*RC*/GIMT_Encode2(AMDGPU::VGPR_32RegClassID),
        GIM_RecordInsn, /*DefineMI*/1, /*MI*/0, /*OpIdx*/1, // MIs[1]
        GIM_CheckOpcode, /*MI*/1, GIMT_Encode2(TargetOpcode::G_FMINNUM),
        GIM_CheckType, /*MI*/1, /*Op*/1, /*Type*/GILLT_s16,
        GIM_CheckType, /*MI*/1, /*Op*/2, /*Type*/GILLT_s16,
        GIM_RecordInsn, /*DefineMI*/2, /*MI*/0, /*OpIdx*/2, // MIs[2]
        GIM_CheckOpcode, /*MI*/2, GIMT_Encode2(TargetOpcode::G_FMINNUM),
        GIM_CheckType, /*MI*/2, /*Op*/1, /*Type*/GILLT_s16,
        GIM_CheckType, /*MI*/2, /*Op*/2, /*Type*/GILLT_s16,
        GIM_RecordInsn, /*DefineMI*/3, /*MI*/2, /*OpIdx*/2, // MIs[3]
        GIM_CheckOpcode, /*MI*/3, GIMT_Encode2(TargetOpcode::G_FMAXNUM),
        // MIs[3] VOP3Mods:src0:src0_mods
        GIM_CheckIsSameOperand, /*MI*/3, /*OpIdx*/1, /*OtherMI*/1, /*OtherOpIdx*/1,
        // MIs[3] VOP3Mods:src1:src1_mods
        GIM_CheckIsSameOperand, /*MI*/3, /*OpIdx*/2, /*OtherMI*/1, /*OtherOpIdx*/2,
        GIM_CheckCxxInsnPredicate, /*MI*/0, /*FnId*/GIMT_Encode2(GICXXPred_MI_Predicate_fmaxnum_like_nnan),
        GIM_CheckIsSafeToFold, /*InsnID*/1,
        GIM_CheckIsSafeToFold, /*InsnID*/2,
        GIM_CheckIsSafeToFold, /*InsnID*/3,
        GIM_CheckComplexPattern, /*MI*/1, /*Op*/1, /*Renderer*/GIMT_Encode2(0), GIMT_Encode2(GICP_gi_vop3mods),
        GIM_CheckComplexPattern, /*MI*/1, /*Op*/2, /*Renderer*/GIMT_Encode2(1), GIMT_Encode2(GICP_gi_vop3mods),
        GIM_CheckComplexPattern, /*MI*/2, /*Op*/1, /*Renderer*/GIMT_Encode2(2), GIMT_Encode2(GICP_gi_vop3mods),
        // (fmaxnum_ieee:{ *:[f16] } (fminnum:{ *:[f16] } (VOP3Mods:{ *:[f16] } f16:{ *:[f16] }:$src0, i32:{ *:[i32] }:$src0_mods), (VOP3Mods:{ *:[f16] } f16:{ *:[f16] }:$src1, i32:{ *:[i32] }:$src1_mods)), (fminnum:{ *:[f16] } (VOP3Mods:{ *:[f16] } f16:{ *:[f16] }:$src2, i32:{ *:[i32] }:$src2_mods), (fmaxnum:{ *:[f16] } (VOP3Mods:{ *:[f16] } f16:{ *:[f16] }:$src0, i32:{ *:[i32] }:$src0_mods), (VOP3Mods:{ *:[f16] } f16:{ *:[f16] }:$src1, i32:{ *:[i32] }:$src1_mods))))<<P:Predicate_fmaxnum_like_nnan>>  =>  (V_MED3_F16_e64:{ *:[f16] } ?:{ *:[i32] }:$src0_mods, ?:{ *:[f16] }:$src0, ?:{ *:[i32] }:$src1_mods, ?:{ *:[f16] }:$src1, ?:{ *:[i32] }:$src2_mods, ?:{ *:[f16] }:$src2, 0:{ *:[i1] })
        GIR_BuildMI, /*InsnID*/0, /*Opcode*/GIMT_Encode2(AMDGPU::V_MED3_F16_e64),
        GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/0, // DstI[vdst]
        GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/1, // src0_mods
        GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/0, // src0
        GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(1), /*SubOperand*/1, // src1_mods
        GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(1), /*SubOperand*/0, // src1
        GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(2), /*SubOperand*/1, // src2_mods
        GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(2), /*SubOperand*/0, // src2
        GIR_AddImm8, /*InsnID*/0, /*Imm*/0,
        GIR_AddImm8, /*InsnID*/0, /*Imm*/0,
        GIR_AddImm8, /*InsnID*/0, /*Imm*/0,
        GIR_ConstrainSelectedInstOperands, /*InsnID*/0,
        GIR_EraseFromParent, /*InsnID*/0,
        // GIR_Coverage, 10636,
        GIR_Done,
      // Label 4918: @346580
      GIM_Try, /*On fail goto*//*Label 4919*/ GIMT_Encode4(346726), // Rule ID 10637 //
        GIM_CheckFeatures, GIMT_Encode2(GIFBS_isGFX9Plus),
        GIM_CheckRegBankForClass, /*MI*/0, /*Op*/0, /*RC*/GIMT_Encode2(AMDGPU::VGPR_32RegClassID),
        GIM_RecordInsn, /*DefineMI*/1, /*MI*/0, /*OpIdx*/1, // MIs[1]
        GIM_CheckOpcode, /*MI*/1, GIMT_Encode2(TargetOpcode::G_FMINNUM),
        GIM_CheckType, /*MI*/1, /*Op*/1, /*Type*/GILLT_s16,
        GIM_CheckType, /*MI*/1, /*Op*/2, /*Type*/GILLT_s16,
        GIM_RecordInsn, /*DefineMI*/2, /*MI*/0, /*OpIdx*/2, // MIs[2]
        GIM_CheckOpcode, /*MI*/2, GIMT_Encode2(TargetOpcode::G_FMINNUM),
        GIM_CheckType, /*MI*/2, /*Op*/1, /*Type*/GILLT_s16,
        GIM_CheckType, /*MI*/2, /*Op*/2, /*Type*/GILLT_s16,
        GIM_RecordInsn, /*DefineMI*/3, /*MI*/2, /*OpIdx*/2, // MIs[3]
        GIM_CheckOpcode, /*MI*/3, GIMT_Encode2(TargetOpcode::G_FMAXNUM),
        // MIs[3] VOP3Mods:src1:src1_mods
        GIM_CheckIsSameOperand, /*MI*/3, /*OpIdx*/1, /*OtherMI*/1, /*OtherOpIdx*/2,
        // MIs[3] VOP3Mods:src0:src0_mods
        GIM_CheckIsSameOperand, /*MI*/3, /*OpIdx*/2, /*OtherMI*/1, /*OtherOpIdx*/1,
        GIM_CheckCxxInsnPredicate, /*MI*/0, /*FnId*/GIMT_Encode2(GICXXPred_MI_Predicate_fmaxnum_like_nnan),
        GIM_CheckIsSafeToFold, /*InsnID*/1,
        GIM_CheckIsSafeToFold, /*InsnID*/2,
        GIM_CheckIsSafeToFold, /*InsnID*/3,
        GIM_CheckComplexPattern, /*MI*/1, /*Op*/1, /*Renderer*/GIMT_Encode2(0), GIMT_Encode2(GICP_gi_vop3mods),
        GIM_CheckComplexPattern, /*MI*/1, /*Op*/2, /*Renderer*/GIMT_Encode2(1), GIMT_Encode2(GICP_gi_vop3mods),
        GIM_CheckComplexPattern, /*MI*/2, /*Op*/1, /*Renderer*/GIMT_Encode2(2), GIMT_Encode2(GICP_gi_vop3mods),
        // (fmaxnum_ieee:{ *:[f16] } (fminnum:{ *:[f16] } (VOP3Mods:{ *:[f16] } f16:{ *:[f16] }:$src0, i32:{ *:[i32] }:$src0_mods), (VOP3Mods:{ *:[f16] } f16:{ *:[f16] }:$src1, i32:{ *:[i32] }:$src1_mods)), (fminnum:{ *:[f16] } (VOP3Mods:{ *:[f16] } f16:{ *:[f16] }:$src2, i32:{ *:[i32] }:$src2_mods), (fmaxnum:{ *:[f16] } (VOP3Mods:{ *:[f16] } f16:{ *:[f16] }:$src1, i32:{ *:[i32] }:$src1_mods), (VOP3Mods:{ *:[f16] } f16:{ *:[f16] }:$src0, i32:{ *:[i32] }:$src0_mods))))<<P:Predicate_fmaxnum_like_nnan>>  =>  (V_MED3_F16_e64:{ *:[f16] } ?:{ *:[i32] }:$src0_mods, ?:{ *:[f16] }:$src0, ?:{ *:[i32] }:$src1_mods, ?:{ *:[f16] }:$src1, ?:{ *:[i32] }:$src2_mods, ?:{ *:[f16] }:$src2, 0:{ *:[i1] })
        GIR_BuildMI, /*InsnID*/0, /*Opcode*/GIMT_Encode2(AMDGPU::V_MED3_F16_e64),
        GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/0, // DstI[vdst]
        GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/1, // src0_mods
        GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/0, // src0
        GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(1), /*SubOperand*/1, // src1_mods
        GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(1), /*SubOperand*/0, // src1
        GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(2), /*SubOperand*/1, // src2_mods
        GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(2), /*SubOperand*/0, // src2
        GIR_AddImm8, /*InsnID*/0, /*Imm*/0,
        GIR_AddImm8, /*InsnID*/0, /*Imm*/0,
        GIR_AddImm8, /*InsnID*/0, /*Imm*/0,
        GIR_ConstrainSelectedInstOperands, /*InsnID*/0,
        GIR_EraseFromParent, /*InsnID*/0,
        // GIR_Coverage, 10637,
        GIR_Done,
      // Label 4919: @346726
      GIM_Try, /*On fail goto*//*Label 4920*/ GIMT_Encode4(346872), // Rule ID 10640 //
        GIM_CheckFeatures, GIMT_Encode2(GIFBS_isGFX9Plus),
        GIM_CheckRegBankForClass, /*MI*/0, /*Op*/0, /*RC*/GIMT_Encode2(AMDGPU::VGPR_32RegClassID),
        GIM_RecordInsn, /*DefineMI*/1, /*MI*/0, /*OpIdx*/1, // MIs[1]
        GIM_CheckOpcode, /*MI*/1, GIMT_Encode2(TargetOpcode::G_FMINNUM),
        GIM_CheckType, /*MI*/1, /*Op*/1, /*Type*/GILLT_s16,
        GIM_CheckType, /*MI*/1, /*Op*/2, /*Type*/GILLT_s16,
        GIM_RecordInsn, /*DefineMI*/2, /*MI*/0, /*OpIdx*/2, // MIs[2]
        GIM_CheckOpcode, /*MI*/2, GIMT_Encode2(TargetOpcode::G_FMINNUM),
        GIM_CheckType, /*MI*/2, /*Op*/1, /*Type*/GILLT_s16,
        GIM_CheckType, /*MI*/2, /*Op*/2, /*Type*/GILLT_s16,
        GIM_RecordInsn, /*DefineMI*/3, /*MI*/2, /*OpIdx*/2, // MIs[3]
        GIM_CheckOpcode, /*MI*/3, GIMT_Encode2(TargetOpcode::G_FMAXNUM),
        // MIs[3] VOP3Mods:src0:src0_mods
        GIM_CheckIsSameOperand, /*MI*/3, /*OpIdx*/1, /*OtherMI*/1, /*OtherOpIdx*/2,
        // MIs[3] VOP3Mods:src1:src1_mods
        GIM_CheckIsSameOperand, /*MI*/3, /*OpIdx*/2, /*OtherMI*/1, /*OtherOpIdx*/1,
        GIM_CheckCxxInsnPredicate, /*MI*/0, /*FnId*/GIMT_Encode2(GICXXPred_MI_Predicate_fmaxnum_like_nnan),
        GIM_CheckIsSafeToFold, /*InsnID*/1,
        GIM_CheckIsSafeToFold, /*InsnID*/2,
        GIM_CheckIsSafeToFold, /*InsnID*/3,
        GIM_CheckComplexPattern, /*MI*/1, /*Op*/1, /*Renderer*/GIMT_Encode2(0), GIMT_Encode2(GICP_gi_vop3mods),
        GIM_CheckComplexPattern, /*MI*/1, /*Op*/2, /*Renderer*/GIMT_Encode2(1), GIMT_Encode2(GICP_gi_vop3mods),
        GIM_CheckComplexPattern, /*MI*/2, /*Op*/1, /*Renderer*/GIMT_Encode2(2), GIMT_Encode2(GICP_gi_vop3mods),
        // (fmaxnum_ieee:{ *:[f16] } (fminnum:{ *:[f16] } (VOP3Mods:{ *:[f16] } f16:{ *:[f16] }:$src1, i32:{ *:[i32] }:$src1_mods), (VOP3Mods:{ *:[f16] } f16:{ *:[f16] }:$src0, i32:{ *:[i32] }:$src0_mods)), (fminnum:{ *:[f16] } (VOP3Mods:{ *:[f16] } f16:{ *:[f16] }:$src2, i32:{ *:[i32] }:$src2_mods), (fmaxnum:{ *:[f16] } (VOP3Mods:{ *:[f16] } f16:{ *:[f16] }:$src0, i32:{ *:[i32] }:$src0_mods), (VOP3Mods:{ *:[f16] } f16:{ *:[f16] }:$src1, i32:{ *:[i32] }:$src1_mods))))<<P:Predicate_fmaxnum_like_nnan>>  =>  (V_MED3_F16_e64:{ *:[f16] } ?:{ *:[i32] }:$src0_mods, ?:{ *:[f16] }:$src0, ?:{ *:[i32] }:$src1_mods, ?:{ *:[f16] }:$src1, ?:{ *:[i32] }:$src2_mods, ?:{ *:[f16] }:$src2, 0:{ *:[i1] })
        GIR_BuildMI, /*InsnID*/0, /*Opcode*/GIMT_Encode2(AMDGPU::V_MED3_F16_e64),
        GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/0, // DstI[vdst]
        GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(1), /*SubOperand*/1, // src0_mods
        GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(1), /*SubOperand*/0, // src0
        GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/1, // src1_mods
        GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/0, // src1
        GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(2), /*SubOperand*/1, // src2_mods
        GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(2), /*SubOperand*/0, // src2
        GIR_AddImm8, /*InsnID*/0, /*Imm*/0,
        GIR_AddImm8, /*InsnID*/0, /*Imm*/0,
        GIR_AddImm8, /*InsnID*/0, /*Imm*/0,
        GIR_ConstrainSelectedInstOperands, /*InsnID*/0,
        GIR_EraseFromParent, /*InsnID*/0,
        // GIR_Coverage, 10640,
        GIR_Done,
      // Label 4920: @346872
      GIM_Try, /*On fail goto*//*Label 4921*/ GIMT_Encode4(347018), // Rule ID 10641 //
        GIM_CheckFeatures, GIMT_Encode2(GIFBS_isGFX9Plus),
        GIM_CheckRegBankForClass, /*MI*/0, /*Op*/0, /*RC*/GIMT_Encode2(AMDGPU::VGPR_32RegClassID),
        GIM_RecordInsn, /*DefineMI*/1, /*MI*/0, /*OpIdx*/1, // MIs[1]
        GIM_CheckOpcode, /*MI*/1, GIMT_Encode2(TargetOpcode::G_FMINNUM),
        GIM_CheckType, /*MI*/1, /*Op*/1, /*Type*/GILLT_s16,
        GIM_CheckType, /*MI*/1, /*Op*/2, /*Type*/GILLT_s16,
        GIM_RecordInsn, /*DefineMI*/2, /*MI*/0, /*OpIdx*/2, // MIs[2]
        GIM_CheckOpcode, /*MI*/2, GIMT_Encode2(TargetOpcode::G_FMINNUM),
        GIM_CheckType, /*MI*/2, /*Op*/1, /*Type*/GILLT_s16,
        GIM_CheckType, /*MI*/2, /*Op*/2, /*Type*/GILLT_s16,
        GIM_RecordInsn, /*DefineMI*/3, /*MI*/2, /*OpIdx*/2, // MIs[3]
        GIM_CheckOpcode, /*MI*/3, GIMT_Encode2(TargetOpcode::G_FMAXNUM),
        // MIs[3] VOP3Mods:src1:src1_mods
        GIM_CheckIsSameOperand, /*MI*/3, /*OpIdx*/1, /*OtherMI*/1, /*OtherOpIdx*/1,
        // MIs[3] VOP3Mods:src0:src0_mods
        GIM_CheckIsSameOperand, /*MI*/3, /*OpIdx*/2, /*OtherMI*/1, /*OtherOpIdx*/2,
        GIM_CheckCxxInsnPredicate, /*MI*/0, /*FnId*/GIMT_Encode2(GICXXPred_MI_Predicate_fmaxnum_like_nnan),
        GIM_CheckIsSafeToFold, /*InsnID*/1,
        GIM_CheckIsSafeToFold, /*InsnID*/2,
        GIM_CheckIsSafeToFold, /*InsnID*/3,
        GIM_CheckComplexPattern, /*MI*/1, /*Op*/1, /*Renderer*/GIMT_Encode2(0), GIMT_Encode2(GICP_gi_vop3mods),
        GIM_CheckComplexPattern, /*MI*/1, /*Op*/2, /*Renderer*/GIMT_Encode2(1), GIMT_Encode2(GICP_gi_vop3mods),
        GIM_CheckComplexPattern, /*MI*/2, /*Op*/1, /*Renderer*/GIMT_Encode2(2), GIMT_Encode2(GICP_gi_vop3mods),
        // (fmaxnum_ieee:{ *:[f16] } (fminnum:{ *:[f16] } (VOP3Mods:{ *:[f16] } f16:{ *:[f16] }:$src1, i32:{ *:[i32] }:$src1_mods), (VOP3Mods:{ *:[f16] } f16:{ *:[f16] }:$src0, i32:{ *:[i32] }:$src0_mods)), (fminnum:{ *:[f16] } (VOP3Mods:{ *:[f16] } f16:{ *:[f16] }:$src2, i32:{ *:[i32] }:$src2_mods), (fmaxnum:{ *:[f16] } (VOP3Mods:{ *:[f16] } f16:{ *:[f16] }:$src1, i32:{ *:[i32] }:$src1_mods), (VOP3Mods:{ *:[f16] } f16:{ *:[f16] }:$src0, i32:{ *:[i32] }:$src0_mods))))<<P:Predicate_fmaxnum_like_nnan>>  =>  (V_MED3_F16_e64:{ *:[f16] } ?:{ *:[i32] }:$src0_mods, ?:{ *:[f16] }:$src0, ?:{ *:[i32] }:$src1_mods, ?:{ *:[f16] }:$src1, ?:{ *:[i32] }:$src2_mods, ?:{ *:[f16] }:$src2, 0:{ *:[i1] })
        GIR_BuildMI, /*InsnID*/0, /*Opcode*/GIMT_Encode2(AMDGPU::V_MED3_F16_e64),
        GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/0, // DstI[vdst]
        GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(1), /*SubOperand*/1, // src0_mods
        GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(1), /*SubOperand*/0, // src0
        GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/1, // src1_mods
        GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/0, // src1
        GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(2), /*SubOperand*/1, // src2_mods
        GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(2), /*SubOperand*/0, // src2
        GIR_AddImm8, /*InsnID*/0, /*Imm*/0,
        GIR_AddImm8, /*InsnID*/0, /*Imm*/0,
        GIR_AddImm8, /*InsnID*/0, /*Imm*/0,
        GIR_ConstrainSelectedInstOperands, /*InsnID*/0,
        GIR_EraseFromParent, /*InsnID*/0,
        // GIR_Coverage, 10641,
        GIR_Done,
      // Label 4921: @347018
      GIM_Try, /*On fail goto*//*Label 4922*/ GIMT_Encode4(347164), // Rule ID 10621 //
        GIM_CheckFeatures, GIMT_Encode2(GIFBS_isGFX9Plus),
        GIM_CheckRegBankForClass, /*MI*/0, /*Op*/0, /*RC*/GIMT_Encode2(AMDGPU::VGPR_32RegClassID),
        GIM_RecordInsn, /*DefineMI*/1, /*MI*/0, /*OpIdx*/1, // MIs[1]
        GIM_CheckOpcode, /*MI*/1, GIMT_Encode2(TargetOpcode::G_FMINNUM),
        GIM_CheckType, /*MI*/1, /*Op*/1, /*Type*/GILLT_s16,
        GIM_CheckType, /*MI*/1, /*Op*/2, /*Type*/GILLT_s16,
        GIM_RecordInsn, /*DefineMI*/2, /*MI*/0, /*OpIdx*/2, // MIs[2]
        GIM_CheckOpcode, /*MI*/2, GIMT_Encode2(TargetOpcode::G_FMINNUM),
        GIM_CheckType, /*MI*/2, /*Op*/1, /*Type*/GILLT_s16,
        GIM_CheckType, /*MI*/2, /*Op*/2, /*Type*/GILLT_s16,
        GIM_RecordInsn, /*DefineMI*/3, /*MI*/2, /*OpIdx*/2, // MIs[3]
        GIM_CheckOpcode, /*MI*/3, GIMT_Encode2(TargetOpcode::G_FMAXNUM_IEEE),
        // MIs[3] VOP3Mods:src0:src0_mods
        GIM_CheckIsSameOperand, /*MI*/3, /*OpIdx*/1, /*OtherMI*/1, /*OtherOpIdx*/1,
        // MIs[3] VOP3Mods:src1:src1_mods
        GIM_CheckIsSameOperand, /*MI*/3, /*OpIdx*/2, /*OtherMI*/1, /*OtherOpIdx*/2,
        GIM_CheckCxxInsnPredicate, /*MI*/0, /*FnId*/GIMT_Encode2(GICXXPred_MI_Predicate_fmaxnum_like_nnan),
        GIM_CheckIsSafeToFold, /*InsnID*/1,
        GIM_CheckIsSafeToFold, /*InsnID*/2,
        GIM_CheckIsSafeToFold, /*InsnID*/3,
        GIM_CheckComplexPattern, /*MI*/1, /*Op*/1, /*Renderer*/GIMT_Encode2(0), GIMT_Encode2(GICP_gi_vop3mods),
        GIM_CheckComplexPattern, /*MI*/1, /*Op*/2, /*Renderer*/GIMT_Encode2(1), GIMT_Encode2(GICP_gi_vop3mods),
        GIM_CheckComplexPattern, /*MI*/2, /*Op*/1, /*Renderer*/GIMT_Encode2(2), GIMT_Encode2(GICP_gi_vop3mods),
        // (fmaxnum_ieee:{ *:[f16] } (fminnum:{ *:[f16] } (VOP3Mods:{ *:[f16] } f16:{ *:[f16] }:$src0, i32:{ *:[i32] }:$src0_mods), (VOP3Mods:{ *:[f16] } f16:{ *:[f16] }:$src1, i32:{ *:[i32] }:$src1_mods)), (fminnum:{ *:[f16] } (VOP3Mods:{ *:[f16] } f16:{ *:[f16] }:$src2, i32:{ *:[i32] }:$src2_mods), (fmaxnum_ieee:{ *:[f16] } (VOP3Mods:{ *:[f16] } f16:{ *:[f16] }:$src0, i32:{ *:[i32] }:$src0_mods), (VOP3Mods:{ *:[f16] } f16:{ *:[f16] }:$src1, i32:{ *:[i32] }:$src1_mods))))<<P:Predicate_fmaxnum_like_nnan>>  =>  (V_MED3_F16_e64:{ *:[f16] } ?:{ *:[i32] }:$src0_mods, ?:{ *:[f16] }:$src0, ?:{ *:[i32] }:$src1_mods, ?:{ *:[f16] }:$src1, ?:{ *:[i32] }:$src2_mods, ?:{ *:[f16] }:$src2, 0:{ *:[i1] })
        GIR_BuildMI, /*InsnID*/0, /*Opcode*/GIMT_Encode2(AMDGPU::V_MED3_F16_e64),
        GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/0, // DstI[vdst]
        GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/1, // src0_mods
        GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/0, // src0
        GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(1), /*SubOperand*/1, // src1_mods
        GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(1), /*SubOperand*/0, // src1
        GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(2), /*SubOperand*/1, // src2_mods
        GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(2), /*SubOperand*/0, // src2
        GIR_AddImm8, /*InsnID*/0, /*Imm*/0,
        GIR_AddImm8, /*InsnID*/0, /*Imm*/0,
        GIR_AddImm8, /*InsnID*/0, /*Imm*/0,
        GIR_ConstrainSelectedInstOperands, /*InsnID*/0,
        GIR_EraseFromParent, /*InsnID*/0,
        // GIR_Coverage, 10621,
        GIR_Done,
      // Label 4922: @347164
      GIM_Try, /*On fail goto*//*Label 4923*/ GIMT_Encode4(347310), // Rule ID 10622 //
        GIM_CheckFeatures, GIMT_Encode2(GIFBS_isGFX9Plus),
        GIM_CheckRegBankForClass, /*MI*/0, /*Op*/0, /*RC*/GIMT_Encode2(AMDGPU::VGPR_32RegClassID),
        GIM_RecordInsn, /*DefineMI*/1, /*MI*/0, /*OpIdx*/1, // MIs[1]
        GIM_CheckOpcode, /*MI*/1, GIMT_Encode2(TargetOpcode::G_FMINNUM),
        GIM_CheckType, /*MI*/1, /*Op*/1, /*Type*/GILLT_s16,
        GIM_CheckType, /*MI*/1, /*Op*/2, /*Type*/GILLT_s16,
        GIM_RecordInsn, /*DefineMI*/2, /*MI*/0, /*OpIdx*/2, // MIs[2]
        GIM_CheckOpcode, /*MI*/2, GIMT_Encode2(TargetOpcode::G_FMINNUM),
        GIM_CheckType, /*MI*/2, /*Op*/1, /*Type*/GILLT_s16,
        GIM_CheckType, /*MI*/2, /*Op*/2, /*Type*/GILLT_s16,
        GIM_RecordInsn, /*DefineMI*/3, /*MI*/2, /*OpIdx*/2, // MIs[3]
        GIM_CheckOpcode, /*MI*/3, GIMT_Encode2(TargetOpcode::G_FMAXNUM_IEEE),
        // MIs[3] VOP3Mods:src1:src1_mods
        GIM_CheckIsSameOperand, /*MI*/3, /*OpIdx*/1, /*OtherMI*/1, /*OtherOpIdx*/2,
        // MIs[3] VOP3Mods:src0:src0_mods
        GIM_CheckIsSameOperand, /*MI*/3, /*OpIdx*/2, /*OtherMI*/1, /*OtherOpIdx*/1,
        GIM_CheckCxxInsnPredicate, /*MI*/0, /*FnId*/GIMT_Encode2(GICXXPred_MI_Predicate_fmaxnum_like_nnan),
        GIM_CheckIsSafeToFold, /*InsnID*/1,
        GIM_CheckIsSafeToFold, /*InsnID*/2,
        GIM_CheckIsSafeToFold, /*InsnID*/3,
        GIM_CheckComplexPattern, /*MI*/1, /*Op*/1, /*Renderer*/GIMT_Encode2(0), GIMT_Encode2(GICP_gi_vop3mods),
        GIM_CheckComplexPattern, /*MI*/1, /*Op*/2, /*Renderer*/GIMT_Encode2(1), GIMT_Encode2(GICP_gi_vop3mods),
        GIM_CheckComplexPattern, /*MI*/2, /*Op*/1, /*Renderer*/GIMT_Encode2(2), GIMT_Encode2(GICP_gi_vop3mods),
        // (fmaxnum_ieee:{ *:[f16] } (fminnum:{ *:[f16] } (VOP3Mods:{ *:[f16] } f16:{ *:[f16] }:$src0, i32:{ *:[i32] }:$src0_mods), (VOP3Mods:{ *:[f16] } f16:{ *:[f16] }:$src1, i32:{ *:[i32] }:$src1_mods)), (fminnum:{ *:[f16] } (VOP3Mods:{ *:[f16] } f16:{ *:[f16] }:$src2, i32:{ *:[i32] }:$src2_mods), (fmaxnum_ieee:{ *:[f16] } (VOP3Mods:{ *:[f16] } f16:{ *:[f16] }:$src1, i32:{ *:[i32] }:$src1_mods), (VOP3Mods:{ *:[f16] } f16:{ *:[f16] }:$src0, i32:{ *:[i32] }:$src0_mods))))<<P:Predicate_fmaxnum_like_nnan>>  =>  (V_MED3_F16_e64:{ *:[f16] } ?:{ *:[i32] }:$src0_mods, ?:{ *:[f16] }:$src0, ?:{ *:[i32] }:$src1_mods, ?:{ *:[f16] }:$src1, ?:{ *:[i32] }:$src2_mods, ?:{ *:[f16] }:$src2, 0:{ *:[i1] })
        GIR_BuildMI, /*InsnID*/0, /*Opcode*/GIMT_Encode2(AMDGPU::V_MED3_F16_e64),
        GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/0, // DstI[vdst]
        GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/1, // src0_mods
        GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/0, // src0
        GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(1), /*SubOperand*/1, // src1_mods
        GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(1), /*SubOperand*/0, // src1
        GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(2), /*SubOperand*/1, // src2_mods
        GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(2), /*SubOperand*/0, // src2
        GIR_AddImm8, /*InsnID*/0, /*Imm*/0,
        GIR_AddImm8, /*InsnID*/0, /*Imm*/0,
        GIR_AddImm8, /*InsnID*/0, /*Imm*/0,
        GIR_ConstrainSelectedInstOperands, /*InsnID*/0,
        GIR_EraseFromParent, /*InsnID*/0,
        // GIR_Coverage, 10622,
        GIR_Done,
      // Label 4923: @347310
      GIM_Try, /*On fail goto*//*Label 4924*/ GIMT_Encode4(347456), // Rule ID 10625 //
        GIM_CheckFeatures, GIMT_Encode2(GIFBS_isGFX9Plus),
        GIM_CheckRegBankForClass, /*MI*/0, /*Op*/0, /*RC*/GIMT_Encode2(AMDGPU::VGPR_32RegClassID),
        GIM_RecordInsn, /*DefineMI*/1, /*MI*/0, /*OpIdx*/1, // MIs[1]
        GIM_CheckOpcode, /*MI*/1, GIMT_Encode2(TargetOpcode::G_FMINNUM),
        GIM_CheckType, /*MI*/1, /*Op*/1, /*Type*/GILLT_s16,
        GIM_CheckType, /*MI*/1, /*Op*/2, /*Type*/GILLT_s16,
        GIM_RecordInsn, /*DefineMI*/2, /*MI*/0, /*OpIdx*/2, // MIs[2]
        GIM_CheckOpcode, /*MI*/2, GIMT_Encode2(TargetOpcode::G_FMINNUM),
        GIM_CheckType, /*MI*/2, /*Op*/1, /*Type*/GILLT_s16,
        GIM_CheckType, /*MI*/2, /*Op*/2, /*Type*/GILLT_s16,
        GIM_RecordInsn, /*DefineMI*/3, /*MI*/2, /*OpIdx*/2, // MIs[3]
        GIM_CheckOpcode, /*MI*/3, GIMT_Encode2(TargetOpcode::G_FMAXNUM_IEEE),
        // MIs[3] VOP3Mods:src0:src0_mods
        GIM_CheckIsSameOperand, /*MI*/3, /*OpIdx*/1, /*OtherMI*/1, /*OtherOpIdx*/2,
        // MIs[3] VOP3Mods:src1:src1_mods
        GIM_CheckIsSameOperand, /*MI*/3, /*OpIdx*/2, /*OtherMI*/1, /*OtherOpIdx*/1,
        GIM_CheckCxxInsnPredicate, /*MI*/0, /*FnId*/GIMT_Encode2(GICXXPred_MI_Predicate_fmaxnum_like_nnan),
        GIM_CheckIsSafeToFold, /*InsnID*/1,
        GIM_CheckIsSafeToFold, /*InsnID*/2,
        GIM_CheckIsSafeToFold, /*InsnID*/3,
        GIM_CheckComplexPattern, /*MI*/1, /*Op*/1, /*Renderer*/GIMT_Encode2(0), GIMT_Encode2(GICP_gi_vop3mods),
        GIM_CheckComplexPattern, /*MI*/1, /*Op*/2, /*Renderer*/GIMT_Encode2(1), GIMT_Encode2(GICP_gi_vop3mods),
        GIM_CheckComplexPattern, /*MI*/2, /*Op*/1, /*Renderer*/GIMT_Encode2(2), GIMT_Encode2(GICP_gi_vop3mods),
        // (fmaxnum_ieee:{ *:[f16] } (fminnum:{ *:[f16] } (VOP3Mods:{ *:[f16] } f16:{ *:[f16] }:$src1, i32:{ *:[i32] }:$src1_mods), (VOP3Mods:{ *:[f16] } f16:{ *:[f16] }:$src0, i32:{ *:[i32] }:$src0_mods)), (fminnum:{ *:[f16] } (VOP3Mods:{ *:[f16] } f16:{ *:[f16] }:$src2, i32:{ *:[i32] }:$src2_mods), (fmaxnum_ieee:{ *:[f16] } (VOP3Mods:{ *:[f16] } f16:{ *:[f16] }:$src0, i32:{ *:[i32] }:$src0_mods), (VOP3Mods:{ *:[f16] } f16:{ *:[f16] }:$src1, i32:{ *:[i32] }:$src1_mods))))<<P:Predicate_fmaxnum_like_nnan>>  =>  (V_MED3_F16_e64:{ *:[f16] } ?:{ *:[i32] }:$src0_mods, ?:{ *:[f16] }:$src0, ?:{ *:[i32] }:$src1_mods, ?:{ *:[f16] }:$src1, ?:{ *:[i32] }:$src2_mods, ?:{ *:[f16] }:$src2, 0:{ *:[i1] })
        GIR_BuildMI, /*InsnID*/0, /*Opcode*/GIMT_Encode2(AMDGPU::V_MED3_F16_e64),
        GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/0, // DstI[vdst]
        GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(1), /*SubOperand*/1, // src0_mods
        GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(1), /*SubOperand*/0, // src0
        GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/1, // src1_mods
        GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/0, // src1
        GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(2), /*SubOperand*/1, // src2_mods
        GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(2), /*SubOperand*/0, // src2
        GIR_AddImm8, /*InsnID*/0, /*Imm*/0,
        GIR_AddImm8, /*InsnID*/0, /*Imm*/0,
        GIR_AddImm8, /*InsnID*/0, /*Imm*/0,
        GIR_ConstrainSelectedInstOperands, /*InsnID*/0,
        GIR_EraseFromParent, /*InsnID*/0,
        // GIR_Coverage, 10625,
        GIR_Done,
      // Label 4924: @347456
      GIM_Try, /*On fail goto*//*Label 4925*/ GIMT_Encode4(347602), // Rule ID 10626 //
        GIM_CheckFeatures, GIMT_Encode2(GIFBS_isGFX9Plus),
        GIM_CheckRegBankForClass, /*MI*/0, /*Op*/0, /*RC*/GIMT_Encode2(AMDGPU::VGPR_32RegClassID),
        GIM_RecordInsn, /*DefineMI*/1, /*MI*/0, /*OpIdx*/1, // MIs[1]
        GIM_CheckOpcode, /*MI*/1, GIMT_Encode2(TargetOpcode::G_FMINNUM),
        GIM_CheckType, /*MI*/1, /*Op*/1, /*Type*/GILLT_s16,
        GIM_CheckType, /*MI*/1, /*Op*/2, /*Type*/GILLT_s16,
        GIM_RecordInsn, /*DefineMI*/2, /*MI*/0, /*OpIdx*/2, // MIs[2]
        GIM_CheckOpcode, /*MI*/2, GIMT_Encode2(TargetOpcode::G_FMINNUM),
        GIM_CheckType, /*MI*/2, /*Op*/1, /*Type*/GILLT_s16,
        GIM_CheckType, /*MI*/2, /*Op*/2, /*Type*/GILLT_s16,
        GIM_RecordInsn, /*DefineMI*/3, /*MI*/2, /*OpIdx*/2, // MIs[3]
        GIM_CheckOpcode, /*MI*/3, GIMT_Encode2(TargetOpcode::G_FMAXNUM_IEEE),
        // MIs[3] VOP3Mods:src1:src1_mods
        GIM_CheckIsSameOperand, /*MI*/3, /*OpIdx*/1, /*OtherMI*/1, /*OtherOpIdx*/1,
        // MIs[3] VOP3Mods:src0:src0_mods
        GIM_CheckIsSameOperand, /*MI*/3, /*OpIdx*/2, /*OtherMI*/1, /*OtherOpIdx*/2,
        GIM_CheckCxxInsnPredicate, /*MI*/0, /*FnId*/GIMT_Encode2(GICXXPred_MI_Predicate_fmaxnum_like_nnan),
        GIM_CheckIsSafeToFold, /*InsnID*/1,
        GIM_CheckIsSafeToFold, /*InsnID*/2,
        GIM_CheckIsSafeToFold, /*InsnID*/3,
        GIM_CheckComplexPattern, /*MI*/1, /*Op*/1, /*Renderer*/GIMT_Encode2(0), GIMT_Encode2(GICP_gi_vop3mods),
        GIM_CheckComplexPattern, /*MI*/1, /*Op*/2, /*Renderer*/GIMT_Encode2(1), GIMT_Encode2(GICP_gi_vop3mods),
        GIM_CheckComplexPattern, /*MI*/2, /*Op*/1, /*Renderer*/GIMT_Encode2(2), GIMT_Encode2(GICP_gi_vop3mods),
        // (fmaxnum_ieee:{ *:[f16] } (fminnum:{ *:[f16] } (VOP3Mods:{ *:[f16] } f16:{ *:[f16] }:$src1, i32:{ *:[i32] }:$src1_mods), (VOP3Mods:{ *:[f16] } f16:{ *:[f16] }:$src0, i32:{ *:[i32] }:$src0_mods)), (fminnum:{ *:[f16] } (VOP3Mods:{ *:[f16] } f16:{ *:[f16] }:$src2, i32:{ *:[i32] }:$src2_mods), (fmaxnum_ieee:{ *:[f16] } (VOP3Mods:{ *:[f16] } f16:{ *:[f16] }:$src1, i32:{ *:[i32] }:$src1_mods), (VOP3Mods:{ *:[f16] } f16:{ *:[f16] }:$src0, i32:{ *:[i32] }:$src0_mods))))<<P:Predicate_fmaxnum_like_nnan>>  =>  (V_MED3_F16_e64:{ *:[f16] } ?:{ *:[i32] }:$src0_mods, ?:{ *:[f16] }:$src0, ?:{ *:[i32] }:$src1_mods, ?:{ *:[f16] }:$src1, ?:{ *:[i32] }:$src2_mods, ?:{ *:[f16] }:$src2, 0:{ *:[i1] })
        GIR_BuildMI, /*InsnID*/0, /*Opcode*/GIMT_Encode2(AMDGPU::V_MED3_F16_e64),
        GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/0, // DstI[vdst]
        GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(1), /*SubOperand*/1, // src0_mods
        GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(1), /*SubOperand*/0, // src0
        GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/1, // src1_mods
        GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/0, // src1
        GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(2), /*SubOperand*/1, // src2_mods
        GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(2), /*SubOperand*/0, // src2
        GIR_AddImm8, /*InsnID*/0, /*Imm*/0,
        GIR_AddImm8, /*InsnID*/0, /*Imm*/0,
        GIR_AddImm8, /*InsnID*/0, /*Imm*/0,
        GIR_ConstrainSelectedInstOperands, /*InsnID*/0,
        GIR_EraseFromParent, /*InsnID*/0,
        // GIR_Coverage, 10626,
        GIR_Done,
      // Label 4925: @347602
      GIM_Try, /*On fail goto*//*Label 4926*/ GIMT_Encode4(347748), // Rule ID 6543 //
        GIM_CheckFeatures, GIMT_Encode2(GIFBS_isGFX9Plus),
        GIM_CheckRegBankForClass, /*MI*/0, /*Op*/0, /*RC*/GIMT_Encode2(AMDGPU::VGPR_32RegClassID),
        GIM_RecordInsn, /*DefineMI*/1, /*MI*/0, /*OpIdx*/1, // MIs[1]
        GIM_CheckOpcode, /*MI*/1, GIMT_Encode2(TargetOpcode::G_FMINNUM),
        GIM_CheckType, /*MI*/1, /*Op*/1, /*Type*/GILLT_s16,
        GIM_CheckType, /*MI*/1, /*Op*/2, /*Type*/GILLT_s16,
        GIM_RecordInsn, /*DefineMI*/2, /*MI*/0, /*OpIdx*/2, // MIs[2]
        GIM_CheckOpcode, /*MI*/2, GIMT_Encode2(TargetOpcode::G_FMINNUM),
        GIM_CheckType, /*MI*/2, /*Op*/1, /*Type*/GILLT_s16,
        GIM_CheckType, /*MI*/2, /*Op*/2, /*Type*/GILLT_s16,
        GIM_RecordInsn, /*DefineMI*/3, /*MI*/2, /*OpIdx*/1, // MIs[3]
        GIM_CheckOpcode, /*MI*/3, GIMT_Encode2(TargetOpcode::G_FMAXNUM),
        // MIs[3] VOP3Mods:src0:src0_mods
        GIM_CheckIsSameOperand, /*MI*/3, /*OpIdx*/1, /*OtherMI*/1, /*OtherOpIdx*/1,
        // MIs[3] VOP3Mods:src1:src1_mods
        GIM_CheckIsSameOperand, /*MI*/3, /*OpIdx*/2, /*OtherMI*/1, /*OtherOpIdx*/2,
        GIM_CheckCxxInsnPredicate, /*MI*/0, /*FnId*/GIMT_Encode2(GICXXPred_MI_Predicate_fmaxnum_like_nnan),
        GIM_CheckIsSafeToFold, /*InsnID*/1,
        GIM_CheckIsSafeToFold, /*InsnID*/2,
        GIM_CheckIsSafeToFold, /*InsnID*/3,
        GIM_CheckComplexPattern, /*MI*/1, /*Op*/1, /*Renderer*/GIMT_Encode2(0), GIMT_Encode2(GICP_gi_vop3mods),
        GIM_CheckComplexPattern, /*MI*/1, /*Op*/2, /*Renderer*/GIMT_Encode2(1), GIMT_Encode2(GICP_gi_vop3mods),
        GIM_CheckComplexPattern, /*MI*/2, /*Op*/2, /*Renderer*/GIMT_Encode2(2), GIMT_Encode2(GICP_gi_vop3mods),
        // (fmaxnum_ieee:{ *:[f16] } (fminnum:{ *:[f16] } (VOP3Mods:{ *:[f16] } f16:{ *:[f16] }:$src0, i32:{ *:[i32] }:$src0_mods), (VOP3Mods:{ *:[f16] } f16:{ *:[f16] }:$src1, i32:{ *:[i32] }:$src1_mods)), (fminnum:{ *:[f16] } (fmaxnum:{ *:[f16] } (VOP3Mods:{ *:[f16] } f16:{ *:[f16] }:$src0, i32:{ *:[i32] }:$src0_mods), (VOP3Mods:{ *:[f16] } f16:{ *:[f16] }:$src1, i32:{ *:[i32] }:$src1_mods)), (VOP3Mods:{ *:[f16] } f16:{ *:[f16] }:$src2, i32:{ *:[i32] }:$src2_mods)))<<P:Predicate_fmaxnum_like_nnan>>  =>  (V_MED3_F16_e64:{ *:[f16] } ?:{ *:[i32] }:$src0_mods, ?:{ *:[f16] }:$src0, ?:{ *:[i32] }:$src1_mods, ?:{ *:[f16] }:$src1, ?:{ *:[i32] }:$src2_mods, ?:{ *:[f16] }:$src2, 0:{ *:[i1] })
        GIR_BuildMI, /*InsnID*/0, /*Opcode*/GIMT_Encode2(AMDGPU::V_MED3_F16_e64),
        GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/0, // DstI[vdst]
        GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/1, // src0_mods
        GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/0, // src0
        GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(1), /*SubOperand*/1, // src1_mods
        GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(1), /*SubOperand*/0, // src1
        GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(2), /*SubOperand*/1, // src2_mods
        GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(2), /*SubOperand*/0, // src2
        GIR_AddImm8, /*InsnID*/0, /*Imm*/0,
        GIR_AddImm8, /*InsnID*/0, /*Imm*/0,
        GIR_AddImm8, /*InsnID*/0, /*Imm*/0,
        GIR_ConstrainSelectedInstOperands, /*InsnID*/0,
        GIR_EraseFromParent, /*InsnID*/0,
        // GIR_Coverage, 6543,
        GIR_Done,
      // Label 4926: @347748
      GIM_Try, /*On fail goto*//*Label 4927*/ GIMT_Encode4(347894), // Rule ID 10635 //
        GIM_CheckFeatures, GIMT_Encode2(GIFBS_isGFX9Plus),
        GIM_CheckRegBankForClass, /*MI*/0, /*Op*/0, /*RC*/GIMT_Encode2(AMDGPU::VGPR_32RegClassID),
        GIM_RecordInsn, /*DefineMI*/1, /*MI*/0, /*OpIdx*/1, // MIs[1]
        GIM_CheckOpcode, /*MI*/1, GIMT_Encode2(TargetOpcode::G_FMINNUM),
        GIM_CheckType, /*MI*/1, /*Op*/1, /*Type*/GILLT_s16,
        GIM_CheckType, /*MI*/1, /*Op*/2, /*Type*/GILLT_s16,
        GIM_RecordInsn, /*DefineMI*/2, /*MI*/0, /*OpIdx*/2, // MIs[2]
        GIM_CheckOpcode, /*MI*/2, GIMT_Encode2(TargetOpcode::G_FMINNUM),
        GIM_CheckType, /*MI*/2, /*Op*/1, /*Type*/GILLT_s16,
        GIM_CheckType, /*MI*/2, /*Op*/2, /*Type*/GILLT_s16,
        GIM_RecordInsn, /*DefineMI*/3, /*MI*/2, /*OpIdx*/1, // MIs[3]
        GIM_CheckOpcode, /*MI*/3, GIMT_Encode2(TargetOpcode::G_FMAXNUM),
        // MIs[3] VOP3Mods:src1:src1_mods
        GIM_CheckIsSameOperand, /*MI*/3, /*OpIdx*/1, /*OtherMI*/1, /*OtherOpIdx*/2,
        // MIs[3] VOP3Mods:src0:src0_mods
        GIM_CheckIsSameOperand, /*MI*/3, /*OpIdx*/2, /*OtherMI*/1, /*OtherOpIdx*/1,
        GIM_CheckCxxInsnPredicate, /*MI*/0, /*FnId*/GIMT_Encode2(GICXXPred_MI_Predicate_fmaxnum_like_nnan),
        GIM_CheckIsSafeToFold, /*InsnID*/1,
        GIM_CheckIsSafeToFold, /*InsnID*/2,
        GIM_CheckIsSafeToFold, /*InsnID*/3,
        GIM_CheckComplexPattern, /*MI*/1, /*Op*/1, /*Renderer*/GIMT_Encode2(0), GIMT_Encode2(GICP_gi_vop3mods),
        GIM_CheckComplexPattern, /*MI*/1, /*Op*/2, /*Renderer*/GIMT_Encode2(1), GIMT_Encode2(GICP_gi_vop3mods),
        GIM_CheckComplexPattern, /*MI*/2, /*Op*/2, /*Renderer*/GIMT_Encode2(2), GIMT_Encode2(GICP_gi_vop3mods),
        // (fmaxnum_ieee:{ *:[f16] } (fminnum:{ *:[f16] } (VOP3Mods:{ *:[f16] } f16:{ *:[f16] }:$src0, i32:{ *:[i32] }:$src0_mods), (VOP3Mods:{ *:[f16] } f16:{ *:[f16] }:$src1, i32:{ *:[i32] }:$src1_mods)), (fminnum:{ *:[f16] } (fmaxnum:{ *:[f16] } (VOP3Mods:{ *:[f16] } f16:{ *:[f16] }:$src1, i32:{ *:[i32] }:$src1_mods), (VOP3Mods:{ *:[f16] } f16:{ *:[f16] }:$src0, i32:{ *:[i32] }:$src0_mods)), (VOP3Mods:{ *:[f16] } f16:{ *:[f16] }:$src2, i32:{ *:[i32] }:$src2_mods)))<<P:Predicate_fmaxnum_like_nnan>>  =>  (V_MED3_F16_e64:{ *:[f16] } ?:{ *:[i32] }:$src0_mods, ?:{ *:[f16] }:$src0, ?:{ *:[i32] }:$src1_mods, ?:{ *:[f16] }:$src1, ?:{ *:[i32] }:$src2_mods, ?:{ *:[f16] }:$src2, 0:{ *:[i1] })
        GIR_BuildMI, /*InsnID*/0, /*Opcode*/GIMT_Encode2(AMDGPU::V_MED3_F16_e64),
        GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/0, // DstI[vdst]
        GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/1, // src0_mods
        GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/0, // src0
        GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(1), /*SubOperand*/1, // src1_mods
        GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(1), /*SubOperand*/0, // src1
        GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(2), /*SubOperand*/1, // src2_mods
        GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(2), /*SubOperand*/0, // src2
        GIR_AddImm8, /*InsnID*/0, /*Imm*/0,
        GIR_AddImm8, /*InsnID*/0, /*Imm*/0,
        GIR_AddImm8, /*InsnID*/0, /*Imm*/0,
        GIR_ConstrainSelectedInstOperands, /*InsnID*/0,
        GIR_EraseFromParent, /*InsnID*/0,
        // GIR_Coverage, 10635,
        GIR_Done,
      // Label 4927: @347894
      GIM_Try, /*On fail goto*//*Label 4928*/ GIMT_Encode4(348040), // Rule ID 10638 //
        GIM_CheckFeatures, GIMT_Encode2(GIFBS_isGFX9Plus),
        GIM_CheckRegBankForClass, /*MI*/0, /*Op*/0, /*RC*/GIMT_Encode2(AMDGPU::VGPR_32RegClassID),
        GIM_RecordInsn, /*DefineMI*/1, /*MI*/0, /*OpIdx*/1, // MIs[1]
        GIM_CheckOpcode, /*MI*/1, GIMT_Encode2(TargetOpcode::G_FMINNUM),
        GIM_CheckType, /*MI*/1, /*Op*/1, /*Type*/GILLT_s16,
        GIM_CheckType, /*MI*/1, /*Op*/2, /*Type*/GILLT_s16,
        GIM_RecordInsn, /*DefineMI*/2, /*MI*/0, /*OpIdx*/2, // MIs[2]
        GIM_CheckOpcode, /*MI*/2, GIMT_Encode2(TargetOpcode::G_FMINNUM),
        GIM_CheckType, /*MI*/2, /*Op*/1, /*Type*/GILLT_s16,
        GIM_CheckType, /*MI*/2, /*Op*/2, /*Type*/GILLT_s16,
        GIM_RecordInsn, /*DefineMI*/3, /*MI*/2, /*OpIdx*/1, // MIs[3]
        GIM_CheckOpcode, /*MI*/3, GIMT_Encode2(TargetOpcode::G_FMAXNUM),
        // MIs[3] VOP3Mods:src0:src0_mods
        GIM_CheckIsSameOperand, /*MI*/3, /*OpIdx*/1, /*OtherMI*/1, /*OtherOpIdx*/2,
        // MIs[3] VOP3Mods:src1:src1_mods
        GIM_CheckIsSameOperand, /*MI*/3, /*OpIdx*/2, /*OtherMI*/1, /*OtherOpIdx*/1,
        GIM_CheckCxxInsnPredicate, /*MI*/0, /*FnId*/GIMT_Encode2(GICXXPred_MI_Predicate_fmaxnum_like_nnan),
        GIM_CheckIsSafeToFold, /*InsnID*/1,
        GIM_CheckIsSafeToFold, /*InsnID*/2,
        GIM_CheckIsSafeToFold, /*InsnID*/3,
        GIM_CheckComplexPattern, /*MI*/1, /*Op*/1, /*Renderer*/GIMT_Encode2(0), GIMT_Encode2(GICP_gi_vop3mods),
        GIM_CheckComplexPattern, /*MI*/1, /*Op*/2, /*Renderer*/GIMT_Encode2(1), GIMT_Encode2(GICP_gi_vop3mods),
        GIM_CheckComplexPattern, /*MI*/2, /*Op*/2, /*Renderer*/GIMT_Encode2(2), GIMT_Encode2(GICP_gi_vop3mods),
        // (fmaxnum_ieee:{ *:[f16] } (fminnum:{ *:[f16] } (VOP3Mods:{ *:[f16] } f16:{ *:[f16] }:$src1, i32:{ *:[i32] }:$src1_mods), (VOP3Mods:{ *:[f16] } f16:{ *:[f16] }:$src0, i32:{ *:[i32] }:$src0_mods)), (fminnum:{ *:[f16] } (fmaxnum:{ *:[f16] } (VOP3Mods:{ *:[f16] } f16:{ *:[f16] }:$src0, i32:{ *:[i32] }:$src0_mods), (VOP3Mods:{ *:[f16] } f16:{ *:[f16] }:$src1, i32:{ *:[i32] }:$src1_mods)), (VOP3Mods:{ *:[f16] } f16:{ *:[f16] }:$src2, i32:{ *:[i32] }:$src2_mods)))<<P:Predicate_fmaxnum_like_nnan>>  =>  (V_MED3_F16_e64:{ *:[f16] } ?:{ *:[i32] }:$src0_mods, ?:{ *:[f16] }:$src0, ?:{ *:[i32] }:$src1_mods, ?:{ *:[f16] }:$src1, ?:{ *:[i32] }:$src2_mods, ?:{ *:[f16] }:$src2, 0:{ *:[i1] })
        GIR_BuildMI, /*InsnID*/0, /*Opcode*/GIMT_Encode2(AMDGPU::V_MED3_F16_e64),
        GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/0, // DstI[vdst]
        GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(1), /*SubOperand*/1, // src0_mods
        GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(1), /*SubOperand*/0, // src0
        GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/1, // src1_mods
        GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/0, // src1
        GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(2), /*SubOperand*/1, // src2_mods
        GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(2), /*SubOperand*/0, // src2
        GIR_AddImm8, /*InsnID*/0, /*Imm*/0,
        GIR_AddImm8, /*InsnID*/0, /*Imm*/0,
        GIR_AddImm8, /*InsnID*/0, /*Imm*/0,
        GIR_ConstrainSelectedInstOperands, /*InsnID*/0,
        GIR_EraseFromParent, /*InsnID*/0,
        // GIR_Coverage, 10638,
        GIR_Done,
      // Label 4928: @348040
      GIM_Try, /*On fail goto*//*Label 4929*/ GIMT_Encode4(348186), // Rule ID 10639 //
        GIM_CheckFeatures, GIMT_Encode2(GIFBS_isGFX9Plus),
        GIM_CheckRegBankForClass, /*MI*/0, /*Op*/0, /*RC*/GIMT_Encode2(AMDGPU::VGPR_32RegClassID),
        GIM_RecordInsn, /*DefineMI*/1, /*MI*/0, /*OpIdx*/1, // MIs[1]
        GIM_CheckOpcode, /*MI*/1, GIMT_Encode2(TargetOpcode::G_FMINNUM),
        GIM_CheckType, /*MI*/1, /*Op*/1, /*Type*/GILLT_s16,
        GIM_CheckType, /*MI*/1, /*Op*/2, /*Type*/GILLT_s16,
        GIM_RecordInsn, /*DefineMI*/2, /*MI*/0, /*OpIdx*/2, // MIs[2]
        GIM_CheckOpcode, /*MI*/2, GIMT_Encode2(TargetOpcode::G_FMINNUM),
        GIM_CheckType, /*MI*/2, /*Op*/1, /*Type*/GILLT_s16,
        GIM_CheckType, /*MI*/2, /*Op*/2, /*Type*/GILLT_s16,
        GIM_RecordInsn, /*DefineMI*/3, /*MI*/2, /*OpIdx*/1, // MIs[3]
        GIM_CheckOpcode, /*MI*/3, GIMT_Encode2(TargetOpcode::G_FMAXNUM),
        // MIs[3] VOP3Mods:src1:src1_mods
        GIM_CheckIsSameOperand, /*MI*/3, /*OpIdx*/1, /*OtherMI*/1, /*OtherOpIdx*/1,
        // MIs[3] VOP3Mods:src0:src0_mods
        GIM_CheckIsSameOperand, /*MI*/3, /*OpIdx*/2, /*OtherMI*/1, /*OtherOpIdx*/2,
        GIM_CheckCxxInsnPredicate, /*MI*/0, /*FnId*/GIMT_Encode2(GICXXPred_MI_Predicate_fmaxnum_like_nnan),
        GIM_CheckIsSafeToFold, /*InsnID*/1,
        GIM_CheckIsSafeToFold, /*InsnID*/2,
        GIM_CheckIsSafeToFold, /*InsnID*/3,
        GIM_CheckComplexPattern, /*MI*/1, /*Op*/1, /*Renderer*/GIMT_Encode2(0), GIMT_Encode2(GICP_gi_vop3mods),
        GIM_CheckComplexPattern, /*MI*/1, /*Op*/2, /*Renderer*/GIMT_Encode2(1), GIMT_Encode2(GICP_gi_vop3mods),
        GIM_CheckComplexPattern, /*MI*/2, /*Op*/2, /*Renderer*/GIMT_Encode2(2), GIMT_Encode2(GICP_gi_vop3mods),
        // (fmaxnum_ieee:{ *:[f16] } (fminnum:{ *:[f16] } (VOP3Mods:{ *:[f16] } f16:{ *:[f16] }:$src1, i32:{ *:[i32] }:$src1_mods), (VOP3Mods:{ *:[f16] } f16:{ *:[f16] }:$src0, i32:{ *:[i32] }:$src0_mods)), (fminnum:{ *:[f16] } (fmaxnum:{ *:[f16] } (VOP3Mods:{ *:[f16] } f16:{ *:[f16] }:$src1, i32:{ *:[i32] }:$src1_mods), (VOP3Mods:{ *:[f16] } f16:{ *:[f16] }:$src0, i32:{ *:[i32] }:$src0_mods)), (VOP3Mods:{ *:[f16] } f16:{ *:[f16] }:$src2, i32:{ *:[i32] }:$src2_mods)))<<P:Predicate_fmaxnum_like_nnan>>  =>  (V_MED3_F16_e64:{ *:[f16] } ?:{ *:[i32] }:$src0_mods, ?:{ *:[f16] }:$src0, ?:{ *:[i32] }:$src1_mods, ?:{ *:[f16] }:$src1, ?:{ *:[i32] }:$src2_mods, ?:{ *:[f16] }:$src2, 0:{ *:[i1] })
        GIR_BuildMI, /*InsnID*/0, /*Opcode*/GIMT_Encode2(AMDGPU::V_MED3_F16_e64),
        GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/0, // DstI[vdst]
        GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(1), /*SubOperand*/1, // src0_mods
        GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(1), /*SubOperand*/0, // src0
        GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/1, // src1_mods
        GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/0, // src1
        GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(2), /*SubOperand*/1, // src2_mods
        GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(2), /*SubOperand*/0, // src2
        GIR_AddImm8, /*InsnID*/0, /*Imm*/0,
        GIR_AddImm8, /*InsnID*/0, /*Imm*/0,
        GIR_AddImm8, /*InsnID*/0, /*Imm*/0,
        GIR_ConstrainSelectedInstOperands, /*InsnID*/0,
        GIR_EraseFromParent, /*InsnID*/0,
        // GIR_Coverage, 10639,
        GIR_Done,
      // Label 4929: @348186
      GIM_Try, /*On fail goto*//*Label 4930*/ GIMT_Encode4(348332), // Rule ID 6542 //
        GIM_CheckFeatures, GIMT_Encode2(GIFBS_isGFX9Plus),
        GIM_CheckRegBankForClass, /*MI*/0, /*Op*/0, /*RC*/GIMT_Encode2(AMDGPU::VGPR_32RegClassID),
        GIM_RecordInsn, /*DefineMI*/1, /*MI*/0, /*OpIdx*/1, // MIs[1]
        GIM_CheckOpcode, /*MI*/1, GIMT_Encode2(TargetOpcode::G_FMINNUM),
        GIM_CheckType, /*MI*/1, /*Op*/1, /*Type*/GILLT_s16,
        GIM_CheckType, /*MI*/1, /*Op*/2, /*Type*/GILLT_s16,
        GIM_RecordInsn, /*DefineMI*/2, /*MI*/0, /*OpIdx*/2, // MIs[2]
        GIM_CheckOpcode, /*MI*/2, GIMT_Encode2(TargetOpcode::G_FMINNUM),
        GIM_CheckType, /*MI*/2, /*Op*/1, /*Type*/GILLT_s16,
        GIM_CheckType, /*MI*/2, /*Op*/2, /*Type*/GILLT_s16,
        GIM_RecordInsn, /*DefineMI*/3, /*MI*/2, /*OpIdx*/1, // MIs[3]
        GIM_CheckOpcode, /*MI*/3, GIMT_Encode2(TargetOpcode::G_FMAXNUM_IEEE),
        // MIs[3] VOP3Mods:src0:src0_mods
        GIM_CheckIsSameOperand, /*MI*/3, /*OpIdx*/1, /*OtherMI*/1, /*OtherOpIdx*/1,
        // MIs[3] VOP3Mods:src1:src1_mods
        GIM_CheckIsSameOperand, /*MI*/3, /*OpIdx*/2, /*OtherMI*/1, /*OtherOpIdx*/2,
        GIM_CheckCxxInsnPredicate, /*MI*/0, /*FnId*/GIMT_Encode2(GICXXPred_MI_Predicate_fmaxnum_like_nnan),
        GIM_CheckIsSafeToFold, /*InsnID*/1,
        GIM_CheckIsSafeToFold, /*InsnID*/2,
        GIM_CheckIsSafeToFold, /*InsnID*/3,
        GIM_CheckComplexPattern, /*MI*/1, /*Op*/1, /*Renderer*/GIMT_Encode2(0), GIMT_Encode2(GICP_gi_vop3mods),
        GIM_CheckComplexPattern, /*MI*/1, /*Op*/2, /*Renderer*/GIMT_Encode2(1), GIMT_Encode2(GICP_gi_vop3mods),
        GIM_CheckComplexPattern, /*MI*/2, /*Op*/2, /*Renderer*/GIMT_Encode2(2), GIMT_Encode2(GICP_gi_vop3mods),
        // (fmaxnum_ieee:{ *:[f16] } (fminnum:{ *:[f16] } (VOP3Mods:{ *:[f16] } f16:{ *:[f16] }:$src0, i32:{ *:[i32] }:$src0_mods), (VOP3Mods:{ *:[f16] } f16:{ *:[f16] }:$src1, i32:{ *:[i32] }:$src1_mods)), (fminnum:{ *:[f16] } (fmaxnum_ieee:{ *:[f16] } (VOP3Mods:{ *:[f16] } f16:{ *:[f16] }:$src0, i32:{ *:[i32] }:$src0_mods), (VOP3Mods:{ *:[f16] } f16:{ *:[f16] }:$src1, i32:{ *:[i32] }:$src1_mods)), (VOP3Mods:{ *:[f16] } f16:{ *:[f16] }:$src2, i32:{ *:[i32] }:$src2_mods)))<<P:Predicate_fmaxnum_like_nnan>>  =>  (V_MED3_F16_e64:{ *:[f16] } ?:{ *:[i32] }:$src0_mods, ?:{ *:[f16] }:$src0, ?:{ *:[i32] }:$src1_mods, ?:{ *:[f16] }:$src1, ?:{ *:[i32] }:$src2_mods, ?:{ *:[f16] }:$src2, 0:{ *:[i1] })
        GIR_BuildMI, /*InsnID*/0, /*Opcode*/GIMT_Encode2(AMDGPU::V_MED3_F16_e64),
        GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/0, // DstI[vdst]
        GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/1, // src0_mods
        GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/0, // src0
        GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(1), /*SubOperand*/1, // src1_mods
        GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(1), /*SubOperand*/0, // src1
        GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(2), /*SubOperand*/1, // src2_mods
        GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(2), /*SubOperand*/0, // src2
        GIR_AddImm8, /*InsnID*/0, /*Imm*/0,
        GIR_AddImm8, /*InsnID*/0, /*Imm*/0,
        GIR_AddImm8, /*InsnID*/0, /*Imm*/0,
        GIR_ConstrainSelectedInstOperands, /*InsnID*/0,
        GIR_EraseFromParent, /*InsnID*/0,
        // GIR_Coverage, 6542,
        GIR_Done,
      // Label 4930: @348332
      GIM_Try, /*On fail goto*//*Label 4931*/ GIMT_Encode4(348478), // Rule ID 10620 //
        GIM_CheckFeatures, GIMT_Encode2(GIFBS_isGFX9Plus),
        GIM_CheckRegBankForClass, /*MI*/0, /*Op*/0, /*RC*/GIMT_Encode2(AMDGPU::VGPR_32RegClassID),
        GIM_RecordInsn, /*DefineMI*/1, /*MI*/0, /*OpIdx*/1, // MIs[1]
        GIM_CheckOpcode, /*MI*/1, GIMT_Encode2(TargetOpcode::G_FMINNUM),
        GIM_CheckType, /*MI*/1, /*Op*/1, /*Type*/GILLT_s16,
        GIM_CheckType, /*MI*/1, /*Op*/2, /*Type*/GILLT_s16,
        GIM_RecordInsn, /*DefineMI*/2, /*MI*/0, /*OpIdx*/2, // MIs[2]
        GIM_CheckOpcode, /*MI*/2, GIMT_Encode2(TargetOpcode::G_FMINNUM),
        GIM_CheckType, /*MI*/2, /*Op*/1, /*Type*/GILLT_s16,
        GIM_CheckType, /*MI*/2, /*Op*/2, /*Type*/GILLT_s16,
        GIM_RecordInsn, /*DefineMI*/3, /*MI*/2, /*OpIdx*/1, // MIs[3]
        GIM_CheckOpcode, /*MI*/3, GIMT_Encode2(TargetOpcode::G_FMAXNUM_IEEE),
        // MIs[3] VOP3Mods:src1:src1_mods
        GIM_CheckIsSameOperand, /*MI*/3, /*OpIdx*/1, /*OtherMI*/1, /*OtherOpIdx*/2,
        // MIs[3] VOP3Mods:src0:src0_mods
        GIM_CheckIsSameOperand, /*MI*/3, /*OpIdx*/2, /*OtherMI*/1, /*OtherOpIdx*/1,
        GIM_CheckCxxInsnPredicate, /*MI*/0, /*FnId*/GIMT_Encode2(GICXXPred_MI_Predicate_fmaxnum_like_nnan),
        GIM_CheckIsSafeToFold, /*InsnID*/1,
        GIM_CheckIsSafeToFold, /*InsnID*/2,
        GIM_CheckIsSafeToFold, /*InsnID*/3,
        GIM_CheckComplexPattern, /*MI*/1, /*Op*/1, /*Renderer*/GIMT_Encode2(0), GIMT_Encode2(GICP_gi_vop3mods),
        GIM_CheckComplexPattern, /*MI*/1, /*Op*/2, /*Renderer*/GIMT_Encode2(1), GIMT_Encode2(GICP_gi_vop3mods),
        GIM_CheckComplexPattern, /*MI*/2, /*Op*/2, /*Renderer*/GIMT_Encode2(2), GIMT_Encode2(GICP_gi_vop3mods),
        // (fmaxnum_ieee:{ *:[f16] } (fminnum:{ *:[f16] } (VOP3Mods:{ *:[f16] } f16:{ *:[f16] }:$src0, i32:{ *:[i32] }:$src0_mods), (VOP3Mods:{ *:[f16] } f16:{ *:[f16] }:$src1, i32:{ *:[i32] }:$src1_mods)), (fminnum:{ *:[f16] } (fmaxnum_ieee:{ *:[f16] } (VOP3Mods:{ *:[f16] } f16:{ *:[f16] }:$src1, i32:{ *:[i32] }:$src1_mods), (VOP3Mods:{ *:[f16] } f16:{ *:[f16] }:$src0, i32:{ *:[i32] }:$src0_mods)), (VOP3Mods:{ *:[f16] } f16:{ *:[f16] }:$src2, i32:{ *:[i32] }:$src2_mods)))<<P:Predicate_fmaxnum_like_nnan>>  =>  (V_MED3_F16_e64:{ *:[f16] } ?:{ *:[i32] }:$src0_mods, ?:{ *:[f16] }:$src0, ?:{ *:[i32] }:$src1_mods, ?:{ *:[f16] }:$src1, ?:{ *:[i32] }:$src2_mods, ?:{ *:[f16] }:$src2, 0:{ *:[i1] })
        GIR_BuildMI, /*InsnID*/0, /*Opcode*/GIMT_Encode2(AMDGPU::V_MED3_F16_e64),
        GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/0, // DstI[vdst]
        GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/1, // src0_mods
        GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/0, // src0
        GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(1), /*SubOperand*/1, // src1_mods
        GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(1), /*SubOperand*/0, // src1
        GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(2), /*SubOperand*/1, // src2_mods
        GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(2), /*SubOperand*/0, // src2
        GIR_AddImm8, /*InsnID*/0, /*Imm*/0,
        GIR_AddImm8, /*InsnID*/0, /*Imm*/0,
        GIR_AddImm8, /*InsnID*/0, /*Imm*/0,
        GIR_ConstrainSelectedInstOperands, /*InsnID*/0,
        GIR_EraseFromParent, /*InsnID*/0,
        // GIR_Coverage, 10620,
        GIR_Done,
      // Label 4931: @348478
      GIM_Try, /*On fail goto*//*Label 4932*/ GIMT_Encode4(348624), // Rule ID 10623 //
        GIM_CheckFeatures, GIMT_Encode2(GIFBS_isGFX9Plus),
        GIM_CheckRegBankForClass, /*MI*/0, /*Op*/0, /*RC*/GIMT_Encode2(AMDGPU::VGPR_32RegClassID),
        GIM_RecordInsn, /*DefineMI*/1, /*MI*/0, /*OpIdx*/1, // MIs[1]
        GIM_CheckOpcode, /*MI*/1, GIMT_Encode2(TargetOpcode::G_FMINNUM),
        GIM_CheckType, /*MI*/1, /*Op*/1, /*Type*/GILLT_s16,
        GIM_CheckType, /*MI*/1, /*Op*/2, /*Type*/GILLT_s16,
        GIM_RecordInsn, /*DefineMI*/2, /*MI*/0, /*OpIdx*/2, // MIs[2]
        GIM_CheckOpcode, /*MI*/2, GIMT_Encode2(TargetOpcode::G_FMINNUM),
        GIM_CheckType, /*MI*/2, /*Op*/1, /*Type*/GILLT_s16,
        GIM_CheckType, /*MI*/2, /*Op*/2, /*Type*/GILLT_s16,
        GIM_RecordInsn, /*DefineMI*/3, /*MI*/2, /*OpIdx*/1, // MIs[3]
        GIM_CheckOpcode, /*MI*/3, GIMT_Encode2(TargetOpcode::G_FMAXNUM_IEEE),
        // MIs[3] VOP3Mods:src0:src0_mods
        GIM_CheckIsSameOperand, /*MI*/3, /*OpIdx*/1, /*OtherMI*/1, /*OtherOpIdx*/2,
        // MIs[3] VOP3Mods:src1:src1_mods
        GIM_CheckIsSameOperand, /*MI*/3, /*OpIdx*/2, /*OtherMI*/1, /*OtherOpIdx*/1,
        GIM_CheckCxxInsnPredicate, /*MI*/0, /*FnId*/GIMT_Encode2(GICXXPred_MI_Predicate_fmaxnum_like_nnan),
        GIM_CheckIsSafeToFold, /*InsnID*/1,
        GIM_CheckIsSafeToFold, /*InsnID*/2,
        GIM_CheckIsSafeToFold, /*InsnID*/3,
        GIM_CheckComplexPattern, /*MI*/1, /*Op*/1, /*Renderer*/GIMT_Encode2(0), GIMT_Encode2(GICP_gi_vop3mods),
        GIM_CheckComplexPattern, /*MI*/1, /*Op*/2, /*Renderer*/GIMT_Encode2(1), GIMT_Encode2(GICP_gi_vop3mods),
        GIM_CheckComplexPattern, /*MI*/2, /*Op*/2, /*Renderer*/GIMT_Encode2(2), GIMT_Encode2(GICP_gi_vop3mods),
        // (fmaxnum_ieee:{ *:[f16] } (fminnum:{ *:[f16] } (VOP3Mods:{ *:[f16] } f16:{ *:[f16] }:$src1, i32:{ *:[i32] }:$src1_mods), (VOP3Mods:{ *:[f16] } f16:{ *:[f16] }:$src0, i32:{ *:[i32] }:$src0_mods)), (fminnum:{ *:[f16] } (fmaxnum_ieee:{ *:[f16] } (VOP3Mods:{ *:[f16] } f16:{ *:[f16] }:$src0, i32:{ *:[i32] }:$src0_mods), (VOP3Mods:{ *:[f16] } f16:{ *:[f16] }:$src1, i32:{ *:[i32] }:$src1_mods)), (VOP3Mods:{ *:[f16] } f16:{ *:[f16] }:$src2, i32:{ *:[i32] }:$src2_mods)))<<P:Predicate_fmaxnum_like_nnan>>  =>  (V_MED3_F16_e64:{ *:[f16] } ?:{ *:[i32] }:$src0_mods, ?:{ *:[f16] }:$src0, ?:{ *:[i32] }:$src1_mods, ?:{ *:[f16] }:$src1, ?:{ *:[i32] }:$src2_mods, ?:{ *:[f16] }:$src2, 0:{ *:[i1] })
        GIR_BuildMI, /*InsnID*/0, /*Opcode*/GIMT_Encode2(AMDGPU::V_MED3_F16_e64),
        GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/0, // DstI[vdst]
        GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(1), /*SubOperand*/1, // src0_mods
        GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(1), /*SubOperand*/0, // src0
        GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/1, // src1_mods
        GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/0, // src1
        GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(2), /*SubOperand*/1, // src2_mods
        GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(2), /*SubOperand*/0, // src2
        GIR_AddImm8, /*InsnID*/0, /*Imm*/0,
        GIR_AddImm8, /*InsnID*/0, /*Imm*/0,
        GIR_AddImm8, /*InsnID*/0, /*Imm*/0,
        GIR_ConstrainSelectedInstOperands, /*InsnID*/0,
        GIR_EraseFromParent, /*InsnID*/0,
        // GIR_Coverage, 10623,
        GIR_Done,
      // Label 4932: @348624
      GIM_Try, /*On fail goto*//*Label 4933*/ GIMT_Encode4(348770), // Rule ID 10624 //
        GIM_CheckFeatures, GIMT_Encode2(GIFBS_isGFX9Plus),
        GIM_CheckRegBankForClass, /*MI*/0, /*Op*/0, /*RC*/GIMT_Encode2(AMDGPU::VGPR_32RegClassID),
        GIM_RecordInsn, /*DefineMI*/1, /*MI*/0, /*OpIdx*/1, // MIs[1]
        GIM_CheckOpcode, /*MI*/1, GIMT_Encode2(TargetOpcode::G_FMINNUM),
        GIM_CheckType, /*MI*/1, /*Op*/1, /*Type*/GILLT_s16,
        GIM_CheckType, /*MI*/1, /*Op*/2, /*Type*/GILLT_s16,
        GIM_RecordInsn, /*DefineMI*/2, /*MI*/0, /*OpIdx*/2, // MIs[2]
        GIM_CheckOpcode, /*MI*/2, GIMT_Encode2(TargetOpcode::G_FMINNUM),
        GIM_CheckType, /*MI*/2, /*Op*/1, /*Type*/GILLT_s16,
        GIM_CheckType, /*MI*/2, /*Op*/2, /*Type*/GILLT_s16,
        GIM_RecordInsn, /*DefineMI*/3, /*MI*/2, /*OpIdx*/1, // MIs[3]
        GIM_CheckOpcode, /*MI*/3, GIMT_Encode2(TargetOpcode::G_FMAXNUM_IEEE),
        // MIs[3] VOP3Mods:src1:src1_mods
        GIM_CheckIsSameOperand, /*MI*/3, /*OpIdx*/1, /*OtherMI*/1, /*OtherOpIdx*/1,
        // MIs[3] VOP3Mods:src0:src0_mods
        GIM_CheckIsSameOperand, /*MI*/3, /*OpIdx*/2, /*OtherMI*/1, /*OtherOpIdx*/2,
        GIM_CheckCxxInsnPredicate, /*MI*/0, /*FnId*/GIMT_Encode2(GICXXPred_MI_Predicate_fmaxnum_like_nnan),
        GIM_CheckIsSafeToFold, /*InsnID*/1,
        GIM_CheckIsSafeToFold, /*InsnID*/2,
        GIM_CheckIsSafeToFold, /*InsnID*/3,
        GIM_CheckComplexPattern, /*MI*/1, /*Op*/1, /*Renderer*/GIMT_Encode2(0), GIMT_Encode2(GICP_gi_vop3mods),
        GIM_CheckComplexPattern, /*MI*/1, /*Op*/2, /*Renderer*/GIMT_Encode2(1), GIMT_Encode2(GICP_gi_vop3mods),
        GIM_CheckComplexPattern, /*MI*/2, /*Op*/2, /*Renderer*/GIMT_Encode2(2), GIMT_Encode2(GICP_gi_vop3mods),
        // (fmaxnum_ieee:{ *:[f16] } (fminnum:{ *:[f16] } (VOP3Mods:{ *:[f16] } f16:{ *:[f16] }:$src1, i32:{ *:[i32] }:$src1_mods), (VOP3Mods:{ *:[f16] } f16:{ *:[f16] }:$src0, i32:{ *:[i32] }:$src0_mods)), (fminnum:{ *:[f16] } (fmaxnum_ieee:{ *:[f16] } (VOP3Mods:{ *:[f16] } f16:{ *:[f16] }:$src1, i32:{ *:[i32] }:$src1_mods), (VOP3Mods:{ *:[f16] } f16:{ *:[f16] }:$src0, i32:{ *:[i32] }:$src0_mods)), (VOP3Mods:{ *:[f16] } f16:{ *:[f16] }:$src2, i32:{ *:[i32] }:$src2_mods)))<<P:Predicate_fmaxnum_like_nnan>>  =>  (V_MED3_F16_e64:{ *:[f16] } ?:{ *:[i32] }:$src0_mods, ?:{ *:[f16] }:$src0, ?:{ *:[i32] }:$src1_mods, ?:{ *:[f16] }:$src1, ?:{ *:[i32] }:$src2_mods, ?:{ *:[f16] }:$src2, 0:{ *:[i1] })
        GIR_BuildMI, /*InsnID*/0, /*Opcode*/GIMT_Encode2(AMDGPU::V_MED3_F16_e64),
        GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/0, // DstI[vdst]
        GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(1), /*SubOperand*/1, // src0_mods
        GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(1), /*SubOperand*/0, // src0
        GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/1, // src1_mods
        GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/0, // src1
        GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(2), /*SubOperand*/1, // src2_mods
        GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(2), /*SubOperand*/0, // src2
        GIR_AddImm8, /*InsnID*/0, /*Imm*/0,
        GIR_AddImm8, /*InsnID*/0, /*Imm*/0,
        GIR_AddImm8, /*InsnID*/0, /*Imm*/0,
        GIR_ConstrainSelectedInstOperands, /*InsnID*/0,
        GIR_EraseFromParent, /*InsnID*/0,
        // GIR_Coverage, 10624,
        GIR_Done,
      // Label 4933: @348770
      GIM_Try, /*On fail goto*//*Label 4934*/ GIMT_Encode4(348916), // Rule ID 10606 //
        GIM_CheckFeatures, GIMT_Encode2(GIFBS_isGFX9Plus),
        GIM_CheckRegBankForClass, /*MI*/0, /*Op*/0, /*RC*/GIMT_Encode2(AMDGPU::VGPR_32RegClassID),
        GIM_RecordInsn, /*DefineMI*/1, /*MI*/0, /*OpIdx*/1, // MIs[1]
        GIM_CheckOpcode, /*MI*/1, GIMT_Encode2(TargetOpcode::G_FMINNUM),
        GIM_CheckType, /*MI*/1, /*Op*/1, /*Type*/GILLT_s16,
        GIM_CheckType, /*MI*/1, /*Op*/2, /*Type*/GILLT_s16,
        GIM_RecordInsn, /*DefineMI*/2, /*MI*/0, /*OpIdx*/2, // MIs[2]
        GIM_CheckOpcode, /*MI*/2, GIMT_Encode2(TargetOpcode::G_FMINNUM_IEEE),
        GIM_CheckType, /*MI*/2, /*Op*/1, /*Type*/GILLT_s16,
        GIM_CheckType, /*MI*/2, /*Op*/2, /*Type*/GILLT_s16,
        GIM_RecordInsn, /*DefineMI*/3, /*MI*/2, /*OpIdx*/2, // MIs[3]
        GIM_CheckOpcode, /*MI*/3, GIMT_Encode2(TargetOpcode::G_FMAXNUM),
        // MIs[3] VOP3Mods:src0:src0_mods
        GIM_CheckIsSameOperand, /*MI*/3, /*OpIdx*/1, /*OtherMI*/1, /*OtherOpIdx*/1,
        // MIs[3] VOP3Mods:src1:src1_mods
        GIM_CheckIsSameOperand, /*MI*/3, /*OpIdx*/2, /*OtherMI*/1, /*OtherOpIdx*/2,
        GIM_CheckCxxInsnPredicate, /*MI*/0, /*FnId*/GIMT_Encode2(GICXXPred_MI_Predicate_fmaxnum_like_nnan),
        GIM_CheckIsSafeToFold, /*InsnID*/1,
        GIM_CheckIsSafeToFold, /*InsnID*/2,
        GIM_CheckIsSafeToFold, /*InsnID*/3,
        GIM_CheckComplexPattern, /*MI*/1, /*Op*/1, /*Renderer*/GIMT_Encode2(0), GIMT_Encode2(GICP_gi_vop3mods),
        GIM_CheckComplexPattern, /*MI*/1, /*Op*/2, /*Renderer*/GIMT_Encode2(1), GIMT_Encode2(GICP_gi_vop3mods),
        GIM_CheckComplexPattern, /*MI*/2, /*Op*/1, /*Renderer*/GIMT_Encode2(2), GIMT_Encode2(GICP_gi_vop3mods),
        // (fmaxnum_ieee:{ *:[f16] } (fminnum:{ *:[f16] } (VOP3Mods:{ *:[f16] } f16:{ *:[f16] }:$src0, i32:{ *:[i32] }:$src0_mods), (VOP3Mods:{ *:[f16] } f16:{ *:[f16] }:$src1, i32:{ *:[i32] }:$src1_mods)), (fminnum_ieee:{ *:[f16] } (VOP3Mods:{ *:[f16] } f16:{ *:[f16] }:$src2, i32:{ *:[i32] }:$src2_mods), (fmaxnum:{ *:[f16] } (VOP3Mods:{ *:[f16] } f16:{ *:[f16] }:$src0, i32:{ *:[i32] }:$src0_mods), (VOP3Mods:{ *:[f16] } f16:{ *:[f16] }:$src1, i32:{ *:[i32] }:$src1_mods))))<<P:Predicate_fmaxnum_like_nnan>>  =>  (V_MED3_F16_e64:{ *:[f16] } ?:{ *:[i32] }:$src0_mods, ?:{ *:[f16] }:$src0, ?:{ *:[i32] }:$src1_mods, ?:{ *:[f16] }:$src1, ?:{ *:[i32] }:$src2_mods, ?:{ *:[f16] }:$src2, 0:{ *:[i1] })
        GIR_BuildMI, /*InsnID*/0, /*Opcode*/GIMT_Encode2(AMDGPU::V_MED3_F16_e64),
        GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/0, // DstI[vdst]
        GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/1, // src0_mods
        GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/0, // src0
        GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(1), /*SubOperand*/1, // src1_mods
        GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(1), /*SubOperand*/0, // src1
        GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(2), /*SubOperand*/1, // src2_mods
        GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(2), /*SubOperand*/0, // src2
        GIR_AddImm8, /*InsnID*/0, /*Imm*/0,
        GIR_AddImm8, /*InsnID*/0, /*Imm*/0,
        GIR_AddImm8, /*InsnID*/0, /*Imm*/0,
        GIR_ConstrainSelectedInstOperands, /*InsnID*/0,
        GIR_EraseFromParent, /*InsnID*/0,
        // GIR_Coverage, 10606,
        GIR_Done,
      // Label 4934: @348916
      GIM_Try, /*On fail goto*//*Label 4935*/ GIMT_Encode4(349062), // Rule ID 10607 //
        GIM_CheckFeatures, GIMT_Encode2(GIFBS_isGFX9Plus),
        GIM_CheckRegBankForClass, /*MI*/0, /*Op*/0, /*RC*/GIMT_Encode2(AMDGPU::VGPR_32RegClassID),
        GIM_RecordInsn, /*DefineMI*/1, /*MI*/0, /*OpIdx*/1, // MIs[1]
        GIM_CheckOpcode, /*MI*/1, GIMT_Encode2(TargetOpcode::G_FMINNUM),
        GIM_CheckType, /*MI*/1, /*Op*/1, /*Type*/GILLT_s16,
        GIM_CheckType, /*MI*/1, /*Op*/2, /*Type*/GILLT_s16,
        GIM_RecordInsn, /*DefineMI*/2, /*MI*/0, /*OpIdx*/2, // MIs[2]
        GIM_CheckOpcode, /*MI*/2, GIMT_Encode2(TargetOpcode::G_FMINNUM_IEEE),
        GIM_CheckType, /*MI*/2, /*Op*/1, /*Type*/GILLT_s16,
        GIM_CheckType, /*MI*/2, /*Op*/2, /*Type*/GILLT_s16,
        GIM_RecordInsn, /*DefineMI*/3, /*MI*/2, /*OpIdx*/2, // MIs[3]
        GIM_CheckOpcode, /*MI*/3, GIMT_Encode2(TargetOpcode::G_FMAXNUM),
        // MIs[3] VOP3Mods:src1:src1_mods
        GIM_CheckIsSameOperand, /*MI*/3, /*OpIdx*/1, /*OtherMI*/1, /*OtherOpIdx*/2,
        // MIs[3] VOP3Mods:src0:src0_mods
        GIM_CheckIsSameOperand, /*MI*/3, /*OpIdx*/2, /*OtherMI*/1, /*OtherOpIdx*/1,
        GIM_CheckCxxInsnPredicate, /*MI*/0, /*FnId*/GIMT_Encode2(GICXXPred_MI_Predicate_fmaxnum_like_nnan),
        GIM_CheckIsSafeToFold, /*InsnID*/1,
        GIM_CheckIsSafeToFold, /*InsnID*/2,
        GIM_CheckIsSafeToFold, /*InsnID*/3,
        GIM_CheckComplexPattern, /*MI*/1, /*Op*/1, /*Renderer*/GIMT_Encode2(0), GIMT_Encode2(GICP_gi_vop3mods),
        GIM_CheckComplexPattern, /*MI*/1, /*Op*/2, /*Renderer*/GIMT_Encode2(1), GIMT_Encode2(GICP_gi_vop3mods),
        GIM_CheckComplexPattern, /*MI*/2, /*Op*/1, /*Renderer*/GIMT_Encode2(2), GIMT_Encode2(GICP_gi_vop3mods),
        // (fmaxnum_ieee:{ *:[f16] } (fminnum:{ *:[f16] } (VOP3Mods:{ *:[f16] } f16:{ *:[f16] }:$src0, i32:{ *:[i32] }:$src0_mods), (VOP3Mods:{ *:[f16] } f16:{ *:[f16] }:$src1, i32:{ *:[i32] }:$src1_mods)), (fminnum_ieee:{ *:[f16] } (VOP3Mods:{ *:[f16] } f16:{ *:[f16] }:$src2, i32:{ *:[i32] }:$src2_mods), (fmaxnum:{ *:[f16] } (VOP3Mods:{ *:[f16] } f16:{ *:[f16] }:$src1, i32:{ *:[i32] }:$src1_mods), (VOP3Mods:{ *:[f16] } f16:{ *:[f16] }:$src0, i32:{ *:[i32] }:$src0_mods))))<<P:Predicate_fmaxnum_like_nnan>>  =>  (V_MED3_F16_e64:{ *:[f16] } ?:{ *:[i32] }:$src0_mods, ?:{ *:[f16] }:$src0, ?:{ *:[i32] }:$src1_mods, ?:{ *:[f16] }:$src1, ?:{ *:[i32] }:$src2_mods, ?:{ *:[f16] }:$src2, 0:{ *:[i1] })
        GIR_BuildMI, /*InsnID*/0, /*Opcode*/GIMT_Encode2(AMDGPU::V_MED3_F16_e64),
        GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/0, // DstI[vdst]
        GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/1, // src0_mods
        GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/0, // src0
        GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(1), /*SubOperand*/1, // src1_mods
        GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(1), /*SubOperand*/0, // src1
        GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(2), /*SubOperand*/1, // src2_mods
        GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(2), /*SubOperand*/0, // src2
        GIR_AddImm8, /*InsnID*/0, /*Imm*/0,
        GIR_AddImm8, /*InsnID*/0, /*Imm*/0,
        GIR_AddImm8, /*InsnID*/0, /*Imm*/0,
        GIR_ConstrainSelectedInstOperands, /*InsnID*/0,
        GIR_EraseFromParent, /*InsnID*/0,
        // GIR_Coverage, 10607,
        GIR_Done,
      // Label 4935: @349062
      GIM_Try, /*On fail goto*//*Label 4936*/ GIMT_Encode4(349208), // Rule ID 10610 //
        GIM_CheckFeatures, GIMT_Encode2(GIFBS_isGFX9Plus),
        GIM_CheckRegBankForClass, /*MI*/0, /*Op*/0, /*RC*/GIMT_Encode2(AMDGPU::VGPR_32RegClassID),
        GIM_RecordInsn, /*DefineMI*/1, /*MI*/0, /*OpIdx*/1, // MIs[1]
        GIM_CheckOpcode, /*MI*/1, GIMT_Encode2(TargetOpcode::G_FMINNUM),
        GIM_CheckType, /*MI*/1, /*Op*/1, /*Type*/GILLT_s16,
        GIM_CheckType, /*MI*/1, /*Op*/2, /*Type*/GILLT_s16,
        GIM_RecordInsn, /*DefineMI*/2, /*MI*/0, /*OpIdx*/2, // MIs[2]
        GIM_CheckOpcode, /*MI*/2, GIMT_Encode2(TargetOpcode::G_FMINNUM_IEEE),
        GIM_CheckType, /*MI*/2, /*Op*/1, /*Type*/GILLT_s16,
        GIM_CheckType, /*MI*/2, /*Op*/2, /*Type*/GILLT_s16,
        GIM_RecordInsn, /*DefineMI*/3, /*MI*/2, /*OpIdx*/2, // MIs[3]
        GIM_CheckOpcode, /*MI*/3, GIMT_Encode2(TargetOpcode::G_FMAXNUM),
        // MIs[3] VOP3Mods:src0:src0_mods
        GIM_CheckIsSameOperand, /*MI*/3, /*OpIdx*/1, /*OtherMI*/1, /*OtherOpIdx*/2,
        // MIs[3] VOP3Mods:src1:src1_mods
        GIM_CheckIsSameOperand, /*MI*/3, /*OpIdx*/2, /*OtherMI*/1, /*OtherOpIdx*/1,
        GIM_CheckCxxInsnPredicate, /*MI*/0, /*FnId*/GIMT_Encode2(GICXXPred_MI_Predicate_fmaxnum_like_nnan),
        GIM_CheckIsSafeToFold, /*InsnID*/1,
        GIM_CheckIsSafeToFold, /*InsnID*/2,
        GIM_CheckIsSafeToFold, /*InsnID*/3,
        GIM_CheckComplexPattern, /*MI*/1, /*Op*/1, /*Renderer*/GIMT_Encode2(0), GIMT_Encode2(GICP_gi_vop3mods),
        GIM_CheckComplexPattern, /*MI*/1, /*Op*/2, /*Renderer*/GIMT_Encode2(1), GIMT_Encode2(GICP_gi_vop3mods),
        GIM_CheckComplexPattern, /*MI*/2, /*Op*/1, /*Renderer*/GIMT_Encode2(2), GIMT_Encode2(GICP_gi_vop3mods),
        // (fmaxnum_ieee:{ *:[f16] } (fminnum:{ *:[f16] } (VOP3Mods:{ *:[f16] } f16:{ *:[f16] }:$src1, i32:{ *:[i32] }:$src1_mods), (VOP3Mods:{ *:[f16] } f16:{ *:[f16] }:$src0, i32:{ *:[i32] }:$src0_mods)), (fminnum_ieee:{ *:[f16] } (VOP3Mods:{ *:[f16] } f16:{ *:[f16] }:$src2, i32:{ *:[i32] }:$src2_mods), (fmaxnum:{ *:[f16] } (VOP3Mods:{ *:[f16] } f16:{ *:[f16] }:$src0, i32:{ *:[i32] }:$src0_mods), (VOP3Mods:{ *:[f16] } f16:{ *:[f16] }:$src1, i32:{ *:[i32] }:$src1_mods))))<<P:Predicate_fmaxnum_like_nnan>>  =>  (V_MED3_F16_e64:{ *:[f16] } ?:{ *:[i32] }:$src0_mods, ?:{ *:[f16] }:$src0, ?:{ *:[i32] }:$src1_mods, ?:{ *:[f16] }:$src1, ?:{ *:[i32] }:$src2_mods, ?:{ *:[f16] }:$src2, 0:{ *:[i1] })
        GIR_BuildMI, /*InsnID*/0, /*Opcode*/GIMT_Encode2(AMDGPU::V_MED3_F16_e64),
        GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/0, // DstI[vdst]
        GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(1), /*SubOperand*/1, // src0_mods
        GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(1), /*SubOperand*/0, // src0
        GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/1, // src1_mods
        GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/0, // src1
        GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(2), /*SubOperand*/1, // src2_mods
        GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(2), /*SubOperand*/0, // src2
        GIR_AddImm8, /*InsnID*/0, /*Imm*/0,
        GIR_AddImm8, /*InsnID*/0, /*Imm*/0,
        GIR_AddImm8, /*InsnID*/0, /*Imm*/0,
        GIR_ConstrainSelectedInstOperands, /*InsnID*/0,
        GIR_EraseFromParent, /*InsnID*/0,
        // GIR_Coverage, 10610,
        GIR_Done,
      // Label 4936: @349208
      GIM_Try, /*On fail goto*//*Label 4937*/ GIMT_Encode4(349354), // Rule ID 10611 //
        GIM_CheckFeatures, GIMT_Encode2(GIFBS_isGFX9Plus),
        GIM_CheckRegBankForClass, /*MI*/0, /*Op*/0, /*RC*/GIMT_Encode2(AMDGPU::VGPR_32RegClassID),
        GIM_RecordInsn, /*DefineMI*/1, /*MI*/0, /*OpIdx*/1, // MIs[1]
        GIM_CheckOpcode, /*MI*/1, GIMT_Encode2(TargetOpcode::G_FMINNUM),
        GIM_CheckType, /*MI*/1, /*Op*/1, /*Type*/GILLT_s16,
        GIM_CheckType, /*MI*/1, /*Op*/2, /*Type*/GILLT_s16,
        GIM_RecordInsn, /*DefineMI*/2, /*MI*/0, /*OpIdx*/2, // MIs[2]
        GIM_CheckOpcode, /*MI*/2, GIMT_Encode2(TargetOpcode::G_FMINNUM_IEEE),
        GIM_CheckType, /*MI*/2, /*Op*/1, /*Type*/GILLT_s16,
        GIM_CheckType, /*MI*/2, /*Op*/2, /*Type*/GILLT_s16,
        GIM_RecordInsn, /*DefineMI*/3, /*MI*/2, /*OpIdx*/2, // MIs[3]
        GIM_CheckOpcode, /*MI*/3, GIMT_Encode2(TargetOpcode::G_FMAXNUM),
        // MIs[3] VOP3Mods:src1:src1_mods
        GIM_CheckIsSameOperand, /*MI*/3, /*OpIdx*/1, /*OtherMI*/1, /*OtherOpIdx*/1,
        // MIs[3] VOP3Mods:src0:src0_mods
        GIM_CheckIsSameOperand, /*MI*/3, /*OpIdx*/2, /*OtherMI*/1, /*OtherOpIdx*/2,
        GIM_CheckCxxInsnPredicate, /*MI*/0, /*FnId*/GIMT_Encode2(GICXXPred_MI_Predicate_fmaxnum_like_nnan),
        GIM_CheckIsSafeToFold, /*InsnID*/1,
        GIM_CheckIsSafeToFold, /*InsnID*/2,
        GIM_CheckIsSafeToFold, /*InsnID*/3,
        GIM_CheckComplexPattern, /*MI*/1, /*Op*/1, /*Renderer*/GIMT_Encode2(0), GIMT_Encode2(GICP_gi_vop3mods),
        GIM_CheckComplexPattern, /*MI*/1, /*Op*/2, /*Renderer*/GIMT_Encode2(1), GIMT_Encode2(GICP_gi_vop3mods),
        GIM_CheckComplexPattern, /*MI*/2, /*Op*/1, /*Renderer*/GIMT_Encode2(2), GIMT_Encode2(GICP_gi_vop3mods),
        // (fmaxnum_ieee:{ *:[f16] } (fminnum:{ *:[f16] } (VOP3Mods:{ *:[f16] } f16:{ *:[f16] }:$src1, i32:{ *:[i32] }:$src1_mods), (VOP3Mods:{ *:[f16] } f16:{ *:[f16] }:$src0, i32:{ *:[i32] }:$src0_mods)), (fminnum_ieee:{ *:[f16] } (VOP3Mods:{ *:[f16] } f16:{ *:[f16] }:$src2, i32:{ *:[i32] }:$src2_mods), (fmaxnum:{ *:[f16] } (VOP3Mods:{ *:[f16] } f16:{ *:[f16] }:$src1, i32:{ *:[i32] }:$src1_mods), (VOP3Mods:{ *:[f16] } f16:{ *:[f16] }:$src0, i32:{ *:[i32] }:$src0_mods))))<<P:Predicate_fmaxnum_like_nnan>>  =>  (V_MED3_F16_e64:{ *:[f16] } ?:{ *:[i32] }:$src0_mods, ?:{ *:[f16] }:$src0, ?:{ *:[i32] }:$src1_mods, ?:{ *:[f16] }:$src1, ?:{ *:[i32] }:$src2_mods, ?:{ *:[f16] }:$src2, 0:{ *:[i1] })
        GIR_BuildMI, /*InsnID*/0, /*Opcode*/GIMT_Encode2(AMDGPU::V_MED3_F16_e64),
        GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/0, // DstI[vdst]
        GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(1), /*SubOperand*/1, // src0_mods
        GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(1), /*SubOperand*/0, // src0
        GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/1, // src1_mods
        GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/0, // src1
        GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(2), /*SubOperand*/1, // src2_mods
        GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(2), /*SubOperand*/0, // src2
        GIR_AddImm8, /*InsnID*/0, /*Imm*/0,
        GIR_AddImm8, /*InsnID*/0, /*Imm*/0,
        GIR_AddImm8, /*InsnID*/0, /*Imm*/0,
        GIR_ConstrainSelectedInstOperands, /*InsnID*/0,
        GIR_EraseFromParent, /*InsnID*/0,
        // GIR_Coverage, 10611,
        GIR_Done,
      // Label 4937: @349354
      GIM_Try, /*On fail goto*//*Label 4938*/ GIMT_Encode4(349500), // Rule ID 10591 //
        GIM_CheckFeatures, GIMT_Encode2(GIFBS_isGFX9Plus),
        GIM_CheckRegBankForClass, /*MI*/0, /*Op*/0, /*RC*/GIMT_Encode2(AMDGPU::VGPR_32RegClassID),
        GIM_RecordInsn, /*DefineMI*/1, /*MI*/0, /*OpIdx*/1, // MIs[1]
        GIM_CheckOpcode, /*MI*/1, GIMT_Encode2(TargetOpcode::G_FMINNUM),
        GIM_CheckType, /*MI*/1, /*Op*/1, /*Type*/GILLT_s16,
        GIM_CheckType, /*MI*/1, /*Op*/2, /*Type*/GILLT_s16,
        GIM_RecordInsn, /*DefineMI*/2, /*MI*/0, /*OpIdx*/2, // MIs[2]
        GIM_CheckOpcode, /*MI*/2, GIMT_Encode2(TargetOpcode::G_FMINNUM_IEEE),
        GIM_CheckType, /*MI*/2, /*Op*/1, /*Type*/GILLT_s16,
        GIM_CheckType, /*MI*/2, /*Op*/2, /*Type*/GILLT_s16,
        GIM_RecordInsn, /*DefineMI*/3, /*MI*/2, /*OpIdx*/2, // MIs[3]
        GIM_CheckOpcode, /*MI*/3, GIMT_Encode2(TargetOpcode::G_FMAXNUM_IEEE),
        // MIs[3] VOP3Mods:src0:src0_mods
        GIM_CheckIsSameOperand, /*MI*/3, /*OpIdx*/1, /*OtherMI*/1, /*OtherOpIdx*/1,
        // MIs[3] VOP3Mods:src1:src1_mods
        GIM_CheckIsSameOperand, /*MI*/3, /*OpIdx*/2, /*OtherMI*/1, /*OtherOpIdx*/2,
        GIM_CheckCxxInsnPredicate, /*MI*/0, /*FnId*/GIMT_Encode2(GICXXPred_MI_Predicate_fmaxnum_like_nnan),
        GIM_CheckIsSafeToFold, /*InsnID*/1,
        GIM_CheckIsSafeToFold, /*InsnID*/2,
        GIM_CheckIsSafeToFold, /*InsnID*/3,
        GIM_CheckComplexPattern, /*MI*/1, /*Op*/1, /*Renderer*/GIMT_Encode2(0), GIMT_Encode2(GICP_gi_vop3mods),
        GIM_CheckComplexPattern, /*MI*/1, /*Op*/2, /*Renderer*/GIMT_Encode2(1), GIMT_Encode2(GICP_gi_vop3mods),
        GIM_CheckComplexPattern, /*MI*/2, /*Op*/1, /*Renderer*/GIMT_Encode2(2), GIMT_Encode2(GICP_gi_vop3mods),
        // (fmaxnum_ieee:{ *:[f16] } (fminnum:{ *:[f16] } (VOP3Mods:{ *:[f16] } f16:{ *:[f16] }:$src0, i32:{ *:[i32] }:$src0_mods), (VOP3Mods:{ *:[f16] } f16:{ *:[f16] }:$src1, i32:{ *:[i32] }:$src1_mods)), (fminnum_ieee:{ *:[f16] } (VOP3Mods:{ *:[f16] } f16:{ *:[f16] }:$src2, i32:{ *:[i32] }:$src2_mods), (fmaxnum_ieee:{ *:[f16] } (VOP3Mods:{ *:[f16] } f16:{ *:[f16] }:$src0, i32:{ *:[i32] }:$src0_mods), (VOP3Mods:{ *:[f16] } f16:{ *:[f16] }:$src1, i32:{ *:[i32] }:$src1_mods))))<<P:Predicate_fmaxnum_like_nnan>>  =>  (V_MED3_F16_e64:{ *:[f16] } ?:{ *:[i32] }:$src0_mods, ?:{ *:[f16] }:$src0, ?:{ *:[i32] }:$src1_mods, ?:{ *:[f16] }:$src1, ?:{ *:[i32] }:$src2_mods, ?:{ *:[f16] }:$src2, 0:{ *:[i1] })
        GIR_BuildMI, /*InsnID*/0, /*Opcode*/GIMT_Encode2(AMDGPU::V_MED3_F16_e64),
        GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/0, // DstI[vdst]
        GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/1, // src0_mods
        GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/0, // src0
        GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(1), /*SubOperand*/1, // src1_mods
        GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(1), /*SubOperand*/0, // src1
        GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(2), /*SubOperand*/1, // src2_mods
        GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(2), /*SubOperand*/0, // src2
        GIR_AddImm8, /*InsnID*/0, /*Imm*/0,
        GIR_AddImm8, /*InsnID*/0, /*Imm*/0,
        GIR_AddImm8, /*InsnID*/0, /*Imm*/0,
        GIR_ConstrainSelectedInstOperands, /*InsnID*/0,
        GIR_EraseFromParent, /*InsnID*/0,
        // GIR_Coverage, 10591,
        GIR_Done,
      // Label 4938: @349500
      GIM_Try, /*On fail goto*//*Label 4939*/ GIMT_Encode4(349646), // Rule ID 10592 //
        GIM_CheckFeatures, GIMT_Encode2(GIFBS_isGFX9Plus),
        GIM_CheckRegBankForClass, /*MI*/0, /*Op*/0, /*RC*/GIMT_Encode2(AMDGPU::VGPR_32RegClassID),
        GIM_RecordInsn, /*DefineMI*/1, /*MI*/0, /*OpIdx*/1, // MIs[1]
        GIM_CheckOpcode, /*MI*/1, GIMT_Encode2(TargetOpcode::G_FMINNUM),
        GIM_CheckType, /*MI*/1, /*Op*/1, /*Type*/GILLT_s16,
        GIM_CheckType, /*MI*/1, /*Op*/2, /*Type*/GILLT_s16,
        GIM_RecordInsn, /*DefineMI*/2, /*MI*/0, /*OpIdx*/2, // MIs[2]
        GIM_CheckOpcode, /*MI*/2, GIMT_Encode2(TargetOpcode::G_FMINNUM_IEEE),
        GIM_CheckType, /*MI*/2, /*Op*/1, /*Type*/GILLT_s16,
        GIM_CheckType, /*MI*/2, /*Op*/2, /*Type*/GILLT_s16,
        GIM_RecordInsn, /*DefineMI*/3, /*MI*/2, /*OpIdx*/2, // MIs[3]
        GIM_CheckOpcode, /*MI*/3, GIMT_Encode2(TargetOpcode::G_FMAXNUM_IEEE),
        // MIs[3] VOP3Mods:src1:src1_mods
        GIM_CheckIsSameOperand, /*MI*/3, /*OpIdx*/1, /*OtherMI*/1, /*OtherOpIdx*/2,
        // MIs[3] VOP3Mods:src0:src0_mods
        GIM_CheckIsSameOperand, /*MI*/3, /*OpIdx*/2, /*OtherMI*/1, /*OtherOpIdx*/1,
        GIM_CheckCxxInsnPredicate, /*MI*/0, /*FnId*/GIMT_Encode2(GICXXPred_MI_Predicate_fmaxnum_like_nnan),
        GIM_CheckIsSafeToFold, /*InsnID*/1,
        GIM_CheckIsSafeToFold, /*InsnID*/2,
        GIM_CheckIsSafeToFold, /*InsnID*/3,
        GIM_CheckComplexPattern, /*MI*/1, /*Op*/1, /*Renderer*/GIMT_Encode2(0), GIMT_Encode2(GICP_gi_vop3mods),
        GIM_CheckComplexPattern, /*MI*/1, /*Op*/2, /*Renderer*/GIMT_Encode2(1), GIMT_Encode2(GICP_gi_vop3mods),
        GIM_CheckComplexPattern, /*MI*/2, /*Op*/1, /*Renderer*/GIMT_Encode2(2), GIMT_Encode2(GICP_gi_vop3mods),
        // (fmaxnum_ieee:{ *:[f16] } (fminnum:{ *:[f16] } (VOP3Mods:{ *:[f16] } f16:{ *:[f16] }:$src0, i32:{ *:[i32] }:$src0_mods), (VOP3Mods:{ *:[f16] } f16:{ *:[f16] }:$src1, i32:{ *:[i32] }:$src1_mods)), (fminnum_ieee:{ *:[f16] } (VOP3Mods:{ *:[f16] } f16:{ *:[f16] }:$src2, i32:{ *:[i32] }:$src2_mods), (fmaxnum_ieee:{ *:[f16] } (VOP3Mods:{ *:[f16] } f16:{ *:[f16] }:$src1, i32:{ *:[i32] }:$src1_mods), (VOP3Mods:{ *:[f16] } f16:{ *:[f16] }:$src0, i32:{ *:[i32] }:$src0_mods))))<<P:Predicate_fmaxnum_like_nnan>>  =>  (V_MED3_F16_e64:{ *:[f16] } ?:{ *:[i32] }:$src0_mods, ?:{ *:[f16] }:$src0, ?:{ *:[i32] }:$src1_mods, ?:{ *:[f16] }:$src1, ?:{ *:[i32] }:$src2_mods, ?:{ *:[f16] }:$src2, 0:{ *:[i1] })
        GIR_BuildMI, /*InsnID*/0, /*Opcode*/GIMT_Encode2(AMDGPU::V_MED3_F16_e64),
        GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/0, // DstI[vdst]
        GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/1, // src0_mods
        GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/0, // src0
        GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(1), /*SubOperand*/1, // src1_mods
        GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(1), /*SubOperand*/0, // src1
        GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(2), /*SubOperand*/1, // src2_mods
        GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(2), /*SubOperand*/0, // src2
        GIR_AddImm8, /*InsnID*/0, /*Imm*/0,
        GIR_AddImm8, /*InsnID*/0, /*Imm*/0,
        GIR_AddImm8, /*InsnID*/0, /*Imm*/0,
        GIR_ConstrainSelectedInstOperands, /*InsnID*/0,
        GIR_EraseFromParent, /*InsnID*/0,
        // GIR_Coverage, 10592,
        GIR_Done,
      // Label 4939: @349646
      GIM_Try, /*On fail goto*//*Label 4940*/ GIMT_Encode4(349792), // Rule ID 10595 //
        GIM_CheckFeatures, GIMT_Encode2(GIFBS_isGFX9Plus),
        GIM_CheckRegBankForClass, /*MI*/0, /*Op*/0, /*RC*/GIMT_Encode2(AMDGPU::VGPR_32RegClassID),
        GIM_RecordInsn, /*DefineMI*/1, /*MI*/0, /*OpIdx*/1, // MIs[1]
        GIM_CheckOpcode, /*MI*/1, GIMT_Encode2(TargetOpcode::G_FMINNUM),
        GIM_CheckType, /*MI*/1, /*Op*/1, /*Type*/GILLT_s16,
        GIM_CheckType, /*MI*/1, /*Op*/2, /*Type*/GILLT_s16,
        GIM_RecordInsn, /*DefineMI*/2, /*MI*/0, /*OpIdx*/2, // MIs[2]
        GIM_CheckOpcode, /*MI*/2, GIMT_Encode2(TargetOpcode::G_FMINNUM_IEEE),
        GIM_CheckType, /*MI*/2, /*Op*/1, /*Type*/GILLT_s16,
        GIM_CheckType, /*MI*/2, /*Op*/2, /*Type*/GILLT_s16,
        GIM_RecordInsn, /*DefineMI*/3, /*MI*/2, /*OpIdx*/2, // MIs[3]
        GIM_CheckOpcode, /*MI*/3, GIMT_Encode2(TargetOpcode::G_FMAXNUM_IEEE),
        // MIs[3] VOP3Mods:src0:src0_mods
        GIM_CheckIsSameOperand, /*MI*/3, /*OpIdx*/1, /*OtherMI*/1, /*OtherOpIdx*/2,
        // MIs[3] VOP3Mods:src1:src1_mods
        GIM_CheckIsSameOperand, /*MI*/3, /*OpIdx*/2, /*OtherMI*/1, /*OtherOpIdx*/1,
        GIM_CheckCxxInsnPredicate, /*MI*/0, /*FnId*/GIMT_Encode2(GICXXPred_MI_Predicate_fmaxnum_like_nnan),
        GIM_CheckIsSafeToFold, /*InsnID*/1,
        GIM_CheckIsSafeToFold, /*InsnID*/2,
        GIM_CheckIsSafeToFold, /*InsnID*/3,
        GIM_CheckComplexPattern, /*MI*/1, /*Op*/1, /*Renderer*/GIMT_Encode2(0), GIMT_Encode2(GICP_gi_vop3mods),
        GIM_CheckComplexPattern, /*MI*/1, /*Op*/2, /*Renderer*/GIMT_Encode2(1), GIMT_Encode2(GICP_gi_vop3mods),
        GIM_CheckComplexPattern, /*MI*/2, /*Op*/1, /*Renderer*/GIMT_Encode2(2), GIMT_Encode2(GICP_gi_vop3mods),
        // (fmaxnum_ieee:{ *:[f16] } (fminnum:{ *:[f16] } (VOP3Mods:{ *:[f16] } f16:{ *:[f16] }:$src1, i32:{ *:[i32] }:$src1_mods), (VOP3Mods:{ *:[f16] } f16:{ *:[f16] }:$src0, i32:{ *:[i32] }:$src0_mods)), (fminnum_ieee:{ *:[f16] } (VOP3Mods:{ *:[f16] } f16:{ *:[f16] }:$src2, i32:{ *:[i32] }:$src2_mods), (fmaxnum_ieee:{ *:[f16] } (VOP3Mods:{ *:[f16] } f16:{ *:[f16] }:$src0, i32:{ *:[i32] }:$src0_mods), (VOP3Mods:{ *:[f16] } f16:{ *:[f16] }:$src1, i32:{ *:[i32] }:$src1_mods))))<<P:Predicate_fmaxnum_like_nnan>>  =>  (V_MED3_F16_e64:{ *:[f16] } ?:{ *:[i32] }:$src0_mods, ?:{ *:[f16] }:$src0, ?:{ *:[i32] }:$src1_mods, ?:{ *:[f16] }:$src1, ?:{ *:[i32] }:$src2_mods, ?:{ *:[f16] }:$src2, 0:{ *:[i1] })
        GIR_BuildMI, /*InsnID*/0, /*Opcode*/GIMT_Encode2(AMDGPU::V_MED3_F16_e64),
        GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/0, // DstI[vdst]
        GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(1), /*SubOperand*/1, // src0_mods
        GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(1), /*SubOperand*/0, // src0
        GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/1, // src1_mods
        GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/0, // src1
        GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(2), /*SubOperand*/1, // src2_mods
        GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(2), /*SubOperand*/0, // src2
        GIR_AddImm8, /*InsnID*/0, /*Imm*/0,
        GIR_AddImm8, /*InsnID*/0, /*Imm*/0,
        GIR_AddImm8, /*InsnID*/0, /*Imm*/0,
        GIR_ConstrainSelectedInstOperands, /*InsnID*/0,
        GIR_EraseFromParent, /*InsnID*/0,
        // GIR_Coverage, 10595,
        GIR_Done,
      // Label 4940: @349792
      GIM_Try, /*On fail goto*//*Label 4941*/ GIMT_Encode4(349938), // Rule ID 10596 //
        GIM_CheckFeatures, GIMT_Encode2(GIFBS_isGFX9Plus),
        GIM_CheckRegBankForClass, /*MI*/0, /*Op*/0, /*RC*/GIMT_Encode2(AMDGPU::VGPR_32RegClassID),
        GIM_RecordInsn, /*DefineMI*/1, /*MI*/0, /*OpIdx*/1, // MIs[1]
        GIM_CheckOpcode, /*MI*/1, GIMT_Encode2(TargetOpcode::G_FMINNUM),
        GIM_CheckType, /*MI*/1, /*Op*/1, /*Type*/GILLT_s16,
        GIM_CheckType, /*MI*/1, /*Op*/2, /*Type*/GILLT_s16,
        GIM_RecordInsn, /*DefineMI*/2, /*MI*/0, /*OpIdx*/2, // MIs[2]
        GIM_CheckOpcode, /*MI*/2, GIMT_Encode2(TargetOpcode::G_FMINNUM_IEEE),
        GIM_CheckType, /*MI*/2, /*Op*/1, /*Type*/GILLT_s16,
        GIM_CheckType, /*MI*/2, /*Op*/2, /*Type*/GILLT_s16,
        GIM_RecordInsn, /*DefineMI*/3, /*MI*/2, /*OpIdx*/2, // MIs[3]
        GIM_CheckOpcode, /*MI*/3, GIMT_Encode2(TargetOpcode::G_FMAXNUM_IEEE),
        // MIs[3] VOP3Mods:src1:src1_mods
        GIM_CheckIsSameOperand, /*MI*/3, /*OpIdx*/1, /*OtherMI*/1, /*OtherOpIdx*/1,
        // MIs[3] VOP3Mods:src0:src0_mods
        GIM_CheckIsSameOperand, /*MI*/3, /*OpIdx*/2, /*OtherMI*/1, /*OtherOpIdx*/2,
        GIM_CheckCxxInsnPredicate, /*MI*/0, /*FnId*/GIMT_Encode2(GICXXPred_MI_Predicate_fmaxnum_like_nnan),
        GIM_CheckIsSafeToFold, /*InsnID*/1,
        GIM_CheckIsSafeToFold, /*InsnID*/2,
        GIM_CheckIsSafeToFold, /*InsnID*/3,
        GIM_CheckComplexPattern, /*MI*/1, /*Op*/1, /*Renderer*/GIMT_Encode2(0), GIMT_Encode2(GICP_gi_vop3mods),
        GIM_CheckComplexPattern, /*MI*/1, /*Op*/2, /*Renderer*/GIMT_Encode2(1), GIMT_Encode2(GICP_gi_vop3mods),
        GIM_CheckComplexPattern, /*MI*/2, /*Op*/1, /*Renderer*/GIMT_Encode2(2), GIMT_Encode2(GICP_gi_vop3mods),
        // (fmaxnum_ieee:{ *:[f16] } (fminnum:{ *:[f16] } (VOP3Mods:{ *:[f16] } f16:{ *:[f16] }:$src1, i32:{ *:[i32] }:$src1_mods), (VOP3Mods:{ *:[f16] } f16:{ *:[f16] }:$src0, i32:{ *:[i32] }:$src0_mods)), (fminnum_ieee:{ *:[f16] } (VOP3Mods:{ *:[f16] } f16:{ *:[f16] }:$src2, i32:{ *:[i32] }:$src2_mods), (fmaxnum_ieee:{ *:[f16] } (VOP3Mods:{ *:[f16] } f16:{ *:[f16] }:$src1, i32:{ *:[i32] }:$src1_mods), (VOP3Mods:{ *:[f16] } f16:{ *:[f16] }:$src0, i32:{ *:[i32] }:$src0_mods))))<<P:Predicate_fmaxnum_like_nnan>>  =>  (V_MED3_F16_e64:{ *:[f16] } ?:{ *:[i32] }:$src0_mods, ?:{ *:[f16] }:$src0, ?:{ *:[i32] }:$src1_mods, ?:{ *:[f16] }:$src1, ?:{ *:[i32] }:$src2_mods, ?:{ *:[f16] }:$src2, 0:{ *:[i1] })
        GIR_BuildMI, /*InsnID*/0, /*Opcode*/GIMT_Encode2(AMDGPU::V_MED3_F16_e64),
        GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/0, // DstI[vdst]
        GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(1), /*SubOperand*/1, // src0_mods
        GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(1), /*SubOperand*/0, // src0
        GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/1, // src1_mods
        GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/0, // src1
        GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(2), /*SubOperand*/1, // src2_mods
        GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(2), /*SubOperand*/0, // src2
        GIR_AddImm8, /*InsnID*/0, /*Imm*/0,
        GIR_AddImm8, /*InsnID*/0, /*Imm*/0,
        GIR_AddImm8, /*InsnID*/0, /*Imm*/0,
        GIR_ConstrainSelectedInstOperands, /*InsnID*/0,
        GIR_EraseFromParent, /*InsnID*/0,
        // GIR_Coverage, 10596,
        GIR_Done,
      // Label 4941: @349938
      GIM_Try, /*On fail goto*//*Label 4942*/ GIMT_Encode4(350084), // Rule ID 6541 //
        GIM_CheckFeatures, GIMT_Encode2(GIFBS_isGFX9Plus),
        GIM_CheckRegBankForClass, /*MI*/0, /*Op*/0, /*RC*/GIMT_Encode2(AMDGPU::VGPR_32RegClassID),
        GIM_RecordInsn, /*DefineMI*/1, /*MI*/0, /*OpIdx*/1, // MIs[1]
        GIM_CheckOpcode, /*MI*/1, GIMT_Encode2(TargetOpcode::G_FMINNUM),
        GIM_CheckType, /*MI*/1, /*Op*/1, /*Type*/GILLT_s16,
        GIM_CheckType, /*MI*/1, /*Op*/2, /*Type*/GILLT_s16,
        GIM_RecordInsn, /*DefineMI*/2, /*MI*/0, /*OpIdx*/2, // MIs[2]
        GIM_CheckOpcode, /*MI*/2, GIMT_Encode2(TargetOpcode::G_FMINNUM_IEEE),
        GIM_CheckType, /*MI*/2, /*Op*/1, /*Type*/GILLT_s16,
        GIM_CheckType, /*MI*/2, /*Op*/2, /*Type*/GILLT_s16,
        GIM_RecordInsn, /*DefineMI*/3, /*MI*/2, /*OpIdx*/1, // MIs[3]
        GIM_CheckOpcode, /*MI*/3, GIMT_Encode2(TargetOpcode::G_FMAXNUM),
        // MIs[3] VOP3Mods:src0:src0_mods
        GIM_CheckIsSameOperand, /*MI*/3, /*OpIdx*/1, /*OtherMI*/1, /*OtherOpIdx*/1,
        // MIs[3] VOP3Mods:src1:src1_mods
        GIM_CheckIsSameOperand, /*MI*/3, /*OpIdx*/2, /*OtherMI*/1, /*OtherOpIdx*/2,
        GIM_CheckCxxInsnPredicate, /*MI*/0, /*FnId*/GIMT_Encode2(GICXXPred_MI_Predicate_fmaxnum_like_nnan),
        GIM_CheckIsSafeToFold, /*InsnID*/1,
        GIM_CheckIsSafeToFold, /*InsnID*/2,
        GIM_CheckIsSafeToFold, /*InsnID*/3,
        GIM_CheckComplexPattern, /*MI*/1, /*Op*/1, /*Renderer*/GIMT_Encode2(0), GIMT_Encode2(GICP_gi_vop3mods),
        GIM_CheckComplexPattern, /*MI*/1, /*Op*/2, /*Renderer*/GIMT_Encode2(1), GIMT_Encode2(GICP_gi_vop3mods),
        GIM_CheckComplexPattern, /*MI*/2, /*Op*/2, /*Renderer*/GIMT_Encode2(2), GIMT_Encode2(GICP_gi_vop3mods),
        // (fmaxnum_ieee:{ *:[f16] } (fminnum:{ *:[f16] } (VOP3Mods:{ *:[f16] } f16:{ *:[f16] }:$src0, i32:{ *:[i32] }:$src0_mods), (VOP3Mods:{ *:[f16] } f16:{ *:[f16] }:$src1, i32:{ *:[i32] }:$src1_mods)), (fminnum_ieee:{ *:[f16] } (fmaxnum:{ *:[f16] } (VOP3Mods:{ *:[f16] } f16:{ *:[f16] }:$src0, i32:{ *:[i32] }:$src0_mods), (VOP3Mods:{ *:[f16] } f16:{ *:[f16] }:$src1, i32:{ *:[i32] }:$src1_mods)), (VOP3Mods:{ *:[f16] } f16:{ *:[f16] }:$src2, i32:{ *:[i32] }:$src2_mods)))<<P:Predicate_fmaxnum_like_nnan>>  =>  (V_MED3_F16_e64:{ *:[f16] } ?:{ *:[i32] }:$src0_mods, ?:{ *:[f16] }:$src0, ?:{ *:[i32] }:$src1_mods, ?:{ *:[f16] }:$src1, ?:{ *:[i32] }:$src2_mods, ?:{ *:[f16] }:$src2, 0:{ *:[i1] })
        GIR_BuildMI, /*InsnID*/0, /*Opcode*/GIMT_Encode2(AMDGPU::V_MED3_F16_e64),
        GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/0, // DstI[vdst]
        GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/1, // src0_mods
        GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/0, // src0
        GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(1), /*SubOperand*/1, // src1_mods
        GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(1), /*SubOperand*/0, // src1
        GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(2), /*SubOperand*/1, // src2_mods
        GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(2), /*SubOperand*/0, // src2
        GIR_AddImm8, /*InsnID*/0, /*Imm*/0,
        GIR_AddImm8, /*InsnID*/0, /*Imm*/0,
        GIR_AddImm8, /*InsnID*/0, /*Imm*/0,
        GIR_ConstrainSelectedInstOperands, /*InsnID*/0,
        GIR_EraseFromParent, /*InsnID*/0,
        // GIR_Coverage, 6541,
        GIR_Done,
      // Label 4942: @350084
      GIM_Try, /*On fail goto*//*Label 4943*/ GIMT_Encode4(350230), // Rule ID 10605 //
        GIM_CheckFeatures, GIMT_Encode2(GIFBS_isGFX9Plus),
        GIM_CheckRegBankForClass, /*MI*/0, /*Op*/0, /*RC*/GIMT_Encode2(AMDGPU::VGPR_32RegClassID),
        GIM_RecordInsn, /*DefineMI*/1, /*MI*/0, /*OpIdx*/1, // MIs[1]
        GIM_CheckOpcode, /*MI*/1, GIMT_Encode2(TargetOpcode::G_FMINNUM),
        GIM_CheckType, /*MI*/1, /*Op*/1, /*Type*/GILLT_s16,
        GIM_CheckType, /*MI*/1, /*Op*/2, /*Type*/GILLT_s16,
        GIM_RecordInsn, /*DefineMI*/2, /*MI*/0, /*OpIdx*/2, // MIs[2]
        GIM_CheckOpcode, /*MI*/2, GIMT_Encode2(TargetOpcode::G_FMINNUM_IEEE),
        GIM_CheckType, /*MI*/2, /*Op*/1, /*Type*/GILLT_s16,
        GIM_CheckType, /*MI*/2, /*Op*/2, /*Type*/GILLT_s16,
        GIM_RecordInsn, /*DefineMI*/3, /*MI*/2, /*OpIdx*/1, // MIs[3]
        GIM_CheckOpcode, /*MI*/3, GIMT_Encode2(TargetOpcode::G_FMAXNUM),
        // MIs[3] VOP3Mods:src1:src1_mods
        GIM_CheckIsSameOperand, /*MI*/3, /*OpIdx*/1, /*OtherMI*/1, /*OtherOpIdx*/2,
        // MIs[3] VOP3Mods:src0:src0_mods
        GIM_CheckIsSameOperand, /*MI*/3, /*OpIdx*/2, /*OtherMI*/1, /*OtherOpIdx*/1,
        GIM_CheckCxxInsnPredicate, /*MI*/0, /*FnId*/GIMT_Encode2(GICXXPred_MI_Predicate_fmaxnum_like_nnan),
        GIM_CheckIsSafeToFold, /*InsnID*/1,
        GIM_CheckIsSafeToFold, /*InsnID*/2,
        GIM_CheckIsSafeToFold, /*InsnID*/3,
        GIM_CheckComplexPattern, /*MI*/1, /*Op*/1, /*Renderer*/GIMT_Encode2(0), GIMT_Encode2(GICP_gi_vop3mods),
        GIM_CheckComplexPattern, /*MI*/1, /*Op*/2, /*Renderer*/GIMT_Encode2(1), GIMT_Encode2(GICP_gi_vop3mods),
        GIM_CheckComplexPattern, /*MI*/2, /*Op*/2, /*Renderer*/GIMT_Encode2(2), GIMT_Encode2(GICP_gi_vop3mods),
        // (fmaxnum_ieee:{ *:[f16] } (fminnum:{ *:[f16] } (VOP3Mods:{ *:[f16] } f16:{ *:[f16] }:$src0, i32:{ *:[i32] }:$src0_mods), (VOP3Mods:{ *:[f16] } f16:{ *:[f16] }:$src1, i32:{ *:[i32] }:$src1_mods)), (fminnum_ieee:{ *:[f16] } (fmaxnum:{ *:[f16] } (VOP3Mods:{ *:[f16] } f16:{ *:[f16] }:$src1, i32:{ *:[i32] }:$src1_mods), (VOP3Mods:{ *:[f16] } f16:{ *:[f16] }:$src0, i32:{ *:[i32] }:$src0_mods)), (VOP3Mods:{ *:[f16] } f16:{ *:[f16] }:$src2, i32:{ *:[i32] }:$src2_mods)))<<P:Predicate_fmaxnum_like_nnan>>  =>  (V_MED3_F16_e64:{ *:[f16] } ?:{ *:[i32] }:$src0_mods, ?:{ *:[f16] }:$src0, ?:{ *:[i32] }:$src1_mods, ?:{ *:[f16] }:$src1, ?:{ *:[i32] }:$src2_mods, ?:{ *:[f16] }:$src2, 0:{ *:[i1] })
        GIR_BuildMI, /*InsnID*/0, /*Opcode*/GIMT_Encode2(AMDGPU::V_MED3_F16_e64),
        GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/0, // DstI[vdst]
        GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/1, // src0_mods
        GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/0, // src0
        GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(1), /*SubOperand*/1, // src1_mods
        GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(1), /*SubOperand*/0, // src1
        GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(2), /*SubOperand*/1, // src2_mods
        GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(2), /*SubOperand*/0, // src2
        GIR_AddImm8, /*InsnID*/0, /*Imm*/0,
        GIR_AddImm8, /*InsnID*/0, /*Imm*/0,
        GIR_AddImm8, /*InsnID*/0, /*Imm*/0,
        GIR_ConstrainSelectedInstOperands, /*InsnID*/0,
        GIR_EraseFromParent, /*InsnID*/0,
        // GIR_Coverage, 10605,
        GIR_Done,
      // Label 4943: @350230
      GIM_Try, /*On fail goto*//*Label 4944*/ GIMT_Encode4(350376), // Rule ID 10608 //
        GIM_CheckFeatures, GIMT_Encode2(GIFBS_isGFX9Plus),
        GIM_CheckRegBankForClass, /*MI*/0, /*Op*/0, /*RC*/GIMT_Encode2(AMDGPU::VGPR_32RegClassID),
        GIM_RecordInsn, /*DefineMI*/1, /*MI*/0, /*OpIdx*/1, // MIs[1]
        GIM_CheckOpcode, /*MI*/1, GIMT_Encode2(TargetOpcode::G_FMINNUM),
        GIM_CheckType, /*MI*/1, /*Op*/1, /*Type*/GILLT_s16,
        GIM_CheckType, /*MI*/1, /*Op*/2, /*Type*/GILLT_s16,
        GIM_RecordInsn, /*DefineMI*/2, /*MI*/0, /*OpIdx*/2, // MIs[2]
        GIM_CheckOpcode, /*MI*/2, GIMT_Encode2(TargetOpcode::G_FMINNUM_IEEE),
        GIM_CheckType, /*MI*/2, /*Op*/1, /*Type*/GILLT_s16,
        GIM_CheckType, /*MI*/2, /*Op*/2, /*Type*/GILLT_s16,
        GIM_RecordInsn, /*DefineMI*/3, /*MI*/2, /*OpIdx*/1, // MIs[3]
        GIM_CheckOpcode, /*MI*/3, GIMT_Encode2(TargetOpcode::G_FMAXNUM),
        // MIs[3] VOP3Mods:src0:src0_mods
        GIM_CheckIsSameOperand, /*MI*/3, /*OpIdx*/1, /*OtherMI*/1, /*OtherOpIdx*/2,
        // MIs[3] VOP3Mods:src1:src1_mods
        GIM_CheckIsSameOperand, /*MI*/3, /*OpIdx*/2, /*OtherMI*/1, /*OtherOpIdx*/1,
        GIM_CheckCxxInsnPredicate, /*MI*/0, /*FnId*/GIMT_Encode2(GICXXPred_MI_Predicate_fmaxnum_like_nnan),
        GIM_CheckIsSafeToFold, /*InsnID*/1,
        GIM_CheckIsSafeToFold, /*InsnID*/2,
        GIM_CheckIsSafeToFold, /*InsnID*/3,
        GIM_CheckComplexPattern, /*MI*/1, /*Op*/1, /*Renderer*/GIMT_Encode2(0), GIMT_Encode2(GICP_gi_vop3mods),
        GIM_CheckComplexPattern, /*MI*/1, /*Op*/2, /*Renderer*/GIMT_Encode2(1), GIMT_Encode2(GICP_gi_vop3mods),
        GIM_CheckComplexPattern, /*MI*/2, /*Op*/2, /*Renderer*/GIMT_Encode2(2), GIMT_Encode2(GICP_gi_vop3mods),
        // (fmaxnum_ieee:{ *:[f16] } (fminnum:{ *:[f16] } (VOP3Mods:{ *:[f16] } f16:{ *:[f16] }:$src1, i32:{ *:[i32] }:$src1_mods), (VOP3Mods:{ *:[f16] } f16:{ *:[f16] }:$src0, i32:{ *:[i32] }:$src0_mods)), (fminnum_ieee:{ *:[f16] } (fmaxnum:{ *:[f16] } (VOP3Mods:{ *:[f16] } f16:{ *:[f16] }:$src0, i32:{ *:[i32] }:$src0_mods), (VOP3Mods:{ *:[f16] } f16:{ *:[f16] }:$src1, i32:{ *:[i32] }:$src1_mods)), (VOP3Mods:{ *:[f16] } f16:{ *:[f16] }:$src2, i32:{ *:[i32] }:$src2_mods)))<<P:Predicate_fmaxnum_like_nnan>>  =>  (V_MED3_F16_e64:{ *:[f16] } ?:{ *:[i32] }:$src0_mods, ?:{ *:[f16] }:$src0, ?:{ *:[i32] }:$src1_mods, ?:{ *:[f16] }:$src1, ?:{ *:[i32] }:$src2_mods, ?:{ *:[f16] }:$src2, 0:{ *:[i1] })
        GIR_BuildMI, /*InsnID*/0, /*Opcode*/GIMT_Encode2(AMDGPU::V_MED3_F16_e64),
        GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/0, // DstI[vdst]
        GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(1), /*SubOperand*/1, // src0_mods
        GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(1), /*SubOperand*/0, // src0
        GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/1, // src1_mods
        GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/0, // src1
        GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(2), /*SubOperand*/1, // src2_mods
        GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(2), /*SubOperand*/0, // src2
        GIR_AddImm8, /*InsnID*/0, /*Imm*/0,
        GIR_AddImm8, /*InsnID*/0, /*Imm*/0,
        GIR_AddImm8, /*InsnID*/0, /*Imm*/0,
        GIR_ConstrainSelectedInstOperands, /*InsnID*/0,
        GIR_EraseFromParent, /*InsnID*/0,
        // GIR_Coverage, 10608,
        GIR_Done,
      // Label 4944: @350376
      GIM_Try, /*On fail goto*//*Label 4945*/ GIMT_Encode4(350522), // Rule ID 10609 //
        GIM_CheckFeatures, GIMT_Encode2(GIFBS_isGFX9Plus),
        GIM_CheckRegBankForClass, /*MI*/0, /*Op*/0, /*RC*/GIMT_Encode2(AMDGPU::VGPR_32RegClassID),
        GIM_RecordInsn, /*DefineMI*/1, /*MI*/0, /*OpIdx*/1, // MIs[1]
        GIM_CheckOpcode, /*MI*/1, GIMT_Encode2(TargetOpcode::G_FMINNUM),
        GIM_CheckType, /*MI*/1, /*Op*/1, /*Type*/GILLT_s16,
        GIM_CheckType, /*MI*/1, /*Op*/2, /*Type*/GILLT_s16,
        GIM_RecordInsn, /*DefineMI*/2, /*MI*/0, /*OpIdx*/2, // MIs[2]
        GIM_CheckOpcode, /*MI*/2, GIMT_Encode2(TargetOpcode::G_FMINNUM_IEEE),
        GIM_CheckType, /*MI*/2, /*Op*/1, /*Type*/GILLT_s16,
        GIM_CheckType, /*MI*/2, /*Op*/2, /*Type*/GILLT_s16,
        GIM_RecordInsn, /*DefineMI*/3, /*MI*/2, /*OpIdx*/1, // MIs[3]
        GIM_CheckOpcode, /*MI*/3, GIMT_Encode2(TargetOpcode::G_FMAXNUM),
        // MIs[3] VOP3Mods:src1:src1_mods
        GIM_CheckIsSameOperand, /*MI*/3, /*OpIdx*/1, /*OtherMI*/1, /*OtherOpIdx*/1,
        // MIs[3] VOP3Mods:src0:src0_mods
        GIM_CheckIsSameOperand, /*MI*/3, /*OpIdx*/2, /*OtherMI*/1, /*OtherOpIdx*/2,
        GIM_CheckCxxInsnPredicate, /*MI*/0, /*FnId*/GIMT_Encode2(GICXXPred_MI_Predicate_fmaxnum_like_nnan),
        GIM_CheckIsSafeToFold, /*InsnID*/1,
        GIM_CheckIsSafeToFold, /*InsnID*/2,
        GIM_CheckIsSafeToFold, /*InsnID*/3,
        GIM_CheckComplexPattern, /*MI*/1, /*Op*/1, /*Renderer*/GIMT_Encode2(0), GIMT_Encode2(GICP_gi_vop3mods),
        GIM_CheckComplexPattern, /*MI*/1, /*Op*/2, /*Renderer*/GIMT_Encode2(1), GIMT_Encode2(GICP_gi_vop3mods),
        GIM_CheckComplexPattern, /*MI*/2, /*Op*/2, /*Renderer*/GIMT_Encode2(2), GIMT_Encode2(GICP_gi_vop3mods),
        // (fmaxnum_ieee:{ *:[f16] } (fminnum:{ *:[f16] } (VOP3Mods:{ *:[f16] } f16:{ *:[f16] }:$src1, i32:{ *:[i32] }:$src1_mods), (VOP3Mods:{ *:[f16] } f16:{ *:[f16] }:$src0, i32:{ *:[i32] }:$src0_mods)), (fminnum_ieee:{ *:[f16] } (fmaxnum:{ *:[f16] } (VOP3Mods:{ *:[f16] } f16:{ *:[f16] }:$src1, i32:{ *:[i32] }:$src1_mods), (VOP3Mods:{ *:[f16] } f16:{ *:[f16] }:$src0, i32:{ *:[i32] }:$src0_mods)), (VOP3Mods:{ *:[f16] } f16:{ *:[f16] }:$src2, i32:{ *:[i32] }:$src2_mods)))<<P:Predicate_fmaxnum_like_nnan>>  =>  (V_MED3_F16_e64:{ *:[f16] } ?:{ *:[i32] }:$src0_mods, ?:{ *:[f16] }:$src0, ?:{ *:[i32] }:$src1_mods, ?:{ *:[f16] }:$src1, ?:{ *:[i32] }:$src2_mods, ?:{ *:[f16] }:$src2, 0:{ *:[i1] })
        GIR_BuildMI, /*InsnID*/0, /*Opcode*/GIMT_Encode2(AMDGPU::V_MED3_F16_e64),
        GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/0, // DstI[vdst]
        GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(1), /*SubOperand*/1, // src0_mods
        GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(1), /*SubOperand*/0, // src0
        GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/1, // src1_mods
        GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/0, // src1
        GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(2), /*SubOperand*/1, // src2_mods
        GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(2), /*SubOperand*/0, // src2
        GIR_AddImm8, /*InsnID*/0, /*Imm*/0,
        GIR_AddImm8, /*InsnID*/0, /*Imm*/0,
        GIR_AddImm8, /*InsnID*/0, /*Imm*/0,
        GIR_ConstrainSelectedInstOperands, /*InsnID*/0,
        GIR_EraseFromParent, /*InsnID*/0,
        // GIR_Coverage, 10609,
        GIR_Done,
      // Label 4945: @350522
      GIM_Try, /*On fail goto*//*Label 4946*/ GIMT_Encode4(350668), // Rule ID 6540 //
        GIM_CheckFeatures, GIMT_Encode2(GIFBS_isGFX9Plus),
        GIM_CheckRegBankForClass, /*MI*/0, /*Op*/0, /*RC*/GIMT_Encode2(AMDGPU::VGPR_32RegClassID),
        GIM_RecordInsn, /*DefineMI*/1, /*MI*/0, /*OpIdx*/1, // MIs[1]
        GIM_CheckOpcode, /*MI*/1, GIMT_Encode2(TargetOpcode::G_FMINNUM),
        GIM_CheckType, /*MI*/1, /*Op*/1, /*Type*/GILLT_s16,
        GIM_CheckType, /*MI*/1, /*Op*/2, /*Type*/GILLT_s16,
        GIM_RecordInsn, /*DefineMI*/2, /*MI*/0, /*OpIdx*/2, // MIs[2]
        GIM_CheckOpcode, /*MI*/2, GIMT_Encode2(TargetOpcode::G_FMINNUM_IEEE),
        GIM_CheckType, /*MI*/2, /*Op*/1, /*Type*/GILLT_s16,
        GIM_CheckType, /*MI*/2, /*Op*/2, /*Type*/GILLT_s16,
        GIM_RecordInsn, /*DefineMI*/3, /*MI*/2, /*OpIdx*/1, // MIs[3]
        GIM_CheckOpcode, /*MI*/3, GIMT_Encode2(TargetOpcode::G_FMAXNUM_IEEE),
        // MIs[3] VOP3Mods:src0:src0_mods
        GIM_CheckIsSameOperand, /*MI*/3, /*OpIdx*/1, /*OtherMI*/1, /*OtherOpIdx*/1,
        // MIs[3] VOP3Mods:src1:src1_mods
        GIM_CheckIsSameOperand, /*MI*/3, /*OpIdx*/2, /*OtherMI*/1, /*OtherOpIdx*/2,
        GIM_CheckCxxInsnPredicate, /*MI*/0, /*FnId*/GIMT_Encode2(GICXXPred_MI_Predicate_fmaxnum_like_nnan),
        GIM_CheckIsSafeToFold, /*InsnID*/1,
        GIM_CheckIsSafeToFold, /*InsnID*/2,
        GIM_CheckIsSafeToFold, /*InsnID*/3,
        GIM_CheckComplexPattern, /*MI*/1, /*Op*/1, /*Renderer*/GIMT_Encode2(0), GIMT_Encode2(GICP_gi_vop3mods),
        GIM_CheckComplexPattern, /*MI*/1, /*Op*/2, /*Renderer*/GIMT_Encode2(1), GIMT_Encode2(GICP_gi_vop3mods),
        GIM_CheckComplexPattern, /*MI*/2, /*Op*/2, /*Renderer*/GIMT_Encode2(2), GIMT_Encode2(GICP_gi_vop3mods),
        // (fmaxnum_ieee:{ *:[f16] } (fminnum:{ *:[f16] } (VOP3Mods:{ *:[f16] } f16:{ *:[f16] }:$src0, i32:{ *:[i32] }:$src0_mods), (VOP3Mods:{ *:[f16] } f16:{ *:[f16] }:$src1, i32:{ *:[i32] }:$src1_mods)), (fminnum_ieee:{ *:[f16] } (fmaxnum_ieee:{ *:[f16] } (VOP3Mods:{ *:[f16] } f16:{ *:[f16] }:$src0, i32:{ *:[i32] }:$src0_mods), (VOP3Mods:{ *:[f16] } f16:{ *:[f16] }:$src1, i32:{ *:[i32] }:$src1_mods)), (VOP3Mods:{ *:[f16] } f16:{ *:[f16] }:$src2, i32:{ *:[i32] }:$src2_mods)))<<P:Predicate_fmaxnum_like_nnan>>  =>  (V_MED3_F16_e64:{ *:[f16] } ?:{ *:[i32] }:$src0_mods, ?:{ *:[f16] }:$src0, ?:{ *:[i32] }:$src1_mods, ?:{ *:[f16] }:$src1, ?:{ *:[i32] }:$src2_mods, ?:{ *:[f16] }:$src2, 0:{ *:[i1] })
        GIR_BuildMI, /*InsnID*/0, /*Opcode*/GIMT_Encode2(AMDGPU::V_MED3_F16_e64),
        GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/0, // DstI[vdst]
        GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/1, // src0_mods
        GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/0, // src0
        GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(1), /*SubOperand*/1, // src1_mods
        GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(1), /*SubOperand*/0, // src1
        GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(2), /*SubOperand*/1, // src2_mods
        GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(2), /*SubOperand*/0, // src2
        GIR_AddImm8, /*InsnID*/0, /*Imm*/0,
        GIR_AddImm8, /*InsnID*/0, /*Imm*/0,
        GIR_AddImm8, /*InsnID*/0, /*Imm*/0,
        GIR_ConstrainSelectedInstOperands, /*InsnID*/0,
        GIR_EraseFromParent, /*InsnID*/0,
        // GIR_Coverage, 6540,
        GIR_Done,
      // Label 4946: @350668
      GIM_Try, /*On fail goto*//*Label 4947*/ GIMT_Encode4(350814), // Rule ID 10590 //
        GIM_CheckFeatures, GIMT_Encode2(GIFBS_isGFX9Plus),
        GIM_CheckRegBankForClass, /*MI*/0, /*Op*/0, /*RC*/GIMT_Encode2(AMDGPU::VGPR_32RegClassID),
        GIM_RecordInsn, /*DefineMI*/1, /*MI*/0, /*OpIdx*/1, // MIs[1]
        GIM_CheckOpcode, /*MI*/1, GIMT_Encode2(TargetOpcode::G_FMINNUM),
        GIM_CheckType, /*MI*/1, /*Op*/1, /*Type*/GILLT_s16,
        GIM_CheckType, /*MI*/1, /*Op*/2, /*Type*/GILLT_s16,
        GIM_RecordInsn, /*DefineMI*/2, /*MI*/0, /*OpIdx*/2, // MIs[2]
        GIM_CheckOpcode, /*MI*/2, GIMT_Encode2(TargetOpcode::G_FMINNUM_IEEE),
        GIM_CheckType, /*MI*/2, /*Op*/1, /*Type*/GILLT_s16,
        GIM_CheckType, /*MI*/2, /*Op*/2, /*Type*/GILLT_s16,
        GIM_RecordInsn, /*DefineMI*/3, /*MI*/2, /*OpIdx*/1, // MIs[3]
        GIM_CheckOpcode, /*MI*/3, GIMT_Encode2(TargetOpcode::G_FMAXNUM_IEEE),
        // MIs[3] VOP3Mods:src1:src1_mods
        GIM_CheckIsSameOperand, /*MI*/3, /*OpIdx*/1, /*OtherMI*/1, /*OtherOpIdx*/2,
        // MIs[3] VOP3Mods:src0:src0_mods
        GIM_CheckIsSameOperand, /*MI*/3, /*OpIdx*/2, /*OtherMI*/1, /*OtherOpIdx*/1,
        GIM_CheckCxxInsnPredicate, /*MI*/0, /*FnId*/GIMT_Encode2(GICXXPred_MI_Predicate_fmaxnum_like_nnan),
        GIM_CheckIsSafeToFold, /*InsnID*/1,
        GIM_CheckIsSafeToFold, /*InsnID*/2,
        GIM_CheckIsSafeToFold, /*InsnID*/3,
        GIM_CheckComplexPattern, /*MI*/1, /*Op*/1, /*Renderer*/GIMT_Encode2(0), GIMT_Encode2(GICP_gi_vop3mods),
        GIM_CheckComplexPattern, /*MI*/1, /*Op*/2, /*Renderer*/GIMT_Encode2(1), GIMT_Encode2(GICP_gi_vop3mods),
        GIM_CheckComplexPattern, /*MI*/2, /*Op*/2, /*Renderer*/GIMT_Encode2(2), GIMT_Encode2(GICP_gi_vop3mods),
        // (fmaxnum_ieee:{ *:[f16] } (fminnum:{ *:[f16] } (VOP3Mods:{ *:[f16] } f16:{ *:[f16] }:$src0, i32:{ *:[i32] }:$src0_mods), (VOP3Mods:{ *:[f16] } f16:{ *:[f16] }:$src1, i32:{ *:[i32] }:$src1_mods)), (fminnum_ieee:{ *:[f16] } (fmaxnum_ieee:{ *:[f16] } (VOP3Mods:{ *:[f16] } f16:{ *:[f16] }:$src1, i32:{ *:[i32] }:$src1_mods), (VOP3Mods:{ *:[f16] } f16:{ *:[f16] }:$src0, i32:{ *:[i32] }:$src0_mods)), (VOP3Mods:{ *:[f16] } f16:{ *:[f16] }:$src2, i32:{ *:[i32] }:$src2_mods)))<<P:Predicate_fmaxnum_like_nnan>>  =>  (V_MED3_F16_e64:{ *:[f16] } ?:{ *:[i32] }:$src0_mods, ?:{ *:[f16] }:$src0, ?:{ *:[i32] }:$src1_mods, ?:{ *:[f16] }:$src1, ?:{ *:[i32] }:$src2_mods, ?:{ *:[f16] }:$src2, 0:{ *:[i1] })
        GIR_BuildMI, /*InsnID*/0, /*Opcode*/GIMT_Encode2(AMDGPU::V_MED3_F16_e64),
        GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/0, // DstI[vdst]
        GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/1, // src0_mods
        GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/0, // src0
        GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(1), /*SubOperand*/1, // src1_mods
        GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(1), /*SubOperand*/0, // src1
        GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(2), /*SubOperand*/1, // src2_mods
        GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(2), /*SubOperand*/0, // src2
        GIR_AddImm8, /*InsnID*/0, /*Imm*/0,
        GIR_AddImm8, /*InsnID*/0, /*Imm*/0,
        GIR_AddImm8, /*InsnID*/0, /*Imm*/0,
        GIR_ConstrainSelectedInstOperands, /*InsnID*/0,
        GIR_EraseFromParent, /*InsnID*/0,
        // GIR_Coverage, 10590,
        GIR_Done,
      // Label 4947: @350814
      GIM_Try, /*On fail goto*//*Label 4948*/ GIMT_Encode4(350960), // Rule ID 10593 //
        GIM_CheckFeatures, GIMT_Encode2(GIFBS_isGFX9Plus),
        GIM_CheckRegBankForClass, /*MI*/0, /*Op*/0, /*RC*/GIMT_Encode2(AMDGPU::VGPR_32RegClassID),
        GIM_RecordInsn, /*DefineMI*/1, /*MI*/0, /*OpIdx*/1, // MIs[1]
        GIM_CheckOpcode, /*MI*/1, GIMT_Encode2(TargetOpcode::G_FMINNUM),
        GIM_CheckType, /*MI*/1, /*Op*/1, /*Type*/GILLT_s16,
        GIM_CheckType, /*MI*/1, /*Op*/2, /*Type*/GILLT_s16,
        GIM_RecordInsn, /*DefineMI*/2, /*MI*/0, /*OpIdx*/2, // MIs[2]
        GIM_CheckOpcode, /*MI*/2, GIMT_Encode2(TargetOpcode::G_FMINNUM_IEEE),
        GIM_CheckType, /*MI*/2, /*Op*/1, /*Type*/GILLT_s16,
        GIM_CheckType, /*MI*/2, /*Op*/2, /*Type*/GILLT_s16,
        GIM_RecordInsn, /*DefineMI*/3, /*MI*/2, /*OpIdx*/1, // MIs[3]
        GIM_CheckOpcode, /*MI*/3, GIMT_Encode2(TargetOpcode::G_FMAXNUM_IEEE),
        // MIs[3] VOP3Mods:src0:src0_mods
        GIM_CheckIsSameOperand, /*MI*/3, /*OpIdx*/1, /*OtherMI*/1, /*OtherOpIdx*/2,
        // MIs[3] VOP3Mods:src1:src1_mods
        GIM_CheckIsSameOperand, /*MI*/3, /*OpIdx*/2, /*OtherMI*/1, /*OtherOpIdx*/1,
        GIM_CheckCxxInsnPredicate, /*MI*/0, /*FnId*/GIMT_Encode2(GICXXPred_MI_Predicate_fmaxnum_like_nnan),
        GIM_CheckIsSafeToFold, /*InsnID*/1,
        GIM_CheckIsSafeToFold, /*InsnID*/2,
        GIM_CheckIsSafeToFold, /*InsnID*/3,
        GIM_CheckComplexPattern, /*MI*/1, /*Op*/1, /*Renderer*/GIMT_Encode2(0), GIMT_Encode2(GICP_gi_vop3mods),
        GIM_CheckComplexPattern, /*MI*/1, /*Op*/2, /*Renderer*/GIMT_Encode2(1), GIMT_Encode2(GICP_gi_vop3mods),
        GIM_CheckComplexPattern, /*MI*/2, /*Op*/2, /*Renderer*/GIMT_Encode2(2), GIMT_Encode2(GICP_gi_vop3mods),
        // (fmaxnum_ieee:{ *:[f16] } (fminnum:{ *:[f16] } (VOP3Mods:{ *:[f16] } f16:{ *:[f16] }:$src1, i32:{ *:[i32] }:$src1_mods), (VOP3Mods:{ *:[f16] } f16:{ *:[f16] }:$src0, i32:{ *:[i32] }:$src0_mods)), (fminnum_ieee:{ *:[f16] } (fmaxnum_ieee:{ *:[f16] } (VOP3Mods:{ *:[f16] } f16:{ *:[f16] }:$src0, i32:{ *:[i32] }:$src0_mods), (VOP3Mods:{ *:[f16] } f16:{ *:[f16] }:$src1, i32:{ *:[i32] }:$src1_mods)), (VOP3Mods:{ *:[f16] } f16:{ *:[f16] }:$src2, i32:{ *:[i32] }:$src2_mods)))<<P:Predicate_fmaxnum_like_nnan>>  =>  (V_MED3_F16_e64:{ *:[f16] } ?:{ *:[i32] }:$src0_mods, ?:{ *:[f16] }:$src0, ?:{ *:[i32] }:$src1_mods, ?:{ *:[f16] }:$src1, ?:{ *:[i32] }:$src2_mods, ?:{ *:[f16] }:$src2, 0:{ *:[i1] })
        GIR_BuildMI, /*InsnID*/0, /*Opcode*/GIMT_Encode2(AMDGPU::V_MED3_F16_e64),
        GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/0, // DstI[vdst]
        GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(1), /*SubOperand*/1, // src0_mods
        GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(1), /*SubOperand*/0, // src0
        GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/1, // src1_mods
        GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/0, // src1
        GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(2), /*SubOperand*/1, // src2_mods
        GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(2), /*SubOperand*/0, // src2
        GIR_AddImm8, /*InsnID*/0, /*Imm*/0,
        GIR_AddImm8, /*InsnID*/0, /*Imm*/0,
        GIR_AddImm8, /*InsnID*/0, /*Imm*/0,
        GIR_ConstrainSelectedInstOperands, /*InsnID*/0,
        GIR_EraseFromParent, /*InsnID*/0,
        // GIR_Coverage, 10593,
        GIR_Done,
      // Label 4948: @350960
      GIM_Try, /*On fail goto*//*Label 4949*/ GIMT_Encode4(351106), // Rule ID 10594 //
        GIM_CheckFeatures, GIMT_Encode2(GIFBS_isGFX9Plus),
        GIM_CheckRegBankForClass, /*MI*/0, /*Op*/0, /*RC*/GIMT_Encode2(AMDGPU::VGPR_32RegClassID),
        GIM_RecordInsn, /*DefineMI*/1, /*MI*/0, /*OpIdx*/1, // MIs[1]
        GIM_CheckOpcode, /*MI*/1, GIMT_Encode2(TargetOpcode::G_FMINNUM),
        GIM_CheckType, /*MI*/1, /*Op*/1, /*Type*/GILLT_s16,
        GIM_CheckType, /*MI*/1, /*Op*/2, /*Type*/GILLT_s16,
        GIM_RecordInsn, /*DefineMI*/2, /*MI*/0, /*OpIdx*/2, // MIs[2]
        GIM_CheckOpcode, /*MI*/2, GIMT_Encode2(TargetOpcode::G_FMINNUM_IEEE),
        GIM_CheckType, /*MI*/2, /*Op*/1, /*Type*/GILLT_s16,
        GIM_CheckType, /*MI*/2, /*Op*/2, /*Type*/GILLT_s16,
        GIM_RecordInsn, /*DefineMI*/3, /*MI*/2, /*OpIdx*/1, // MIs[3]
        GIM_CheckOpcode, /*MI*/3, GIMT_Encode2(TargetOpcode::G_FMAXNUM_IEEE),
        // MIs[3] VOP3Mods:src1:src1_mods
        GIM_CheckIsSameOperand, /*MI*/3, /*OpIdx*/1, /*OtherMI*/1, /*OtherOpIdx*/1,
        // MIs[3] VOP3Mods:src0:src0_mods
        GIM_CheckIsSameOperand, /*MI*/3, /*OpIdx*/2, /*OtherMI*/1, /*OtherOpIdx*/2,
        GIM_CheckCxxInsnPredicate, /*MI*/0, /*FnId*/GIMT_Encode2(GICXXPred_MI_Predicate_fmaxnum_like_nnan),
        GIM_CheckIsSafeToFold, /*InsnID*/1,
        GIM_CheckIsSafeToFold, /*InsnID*/2,
        GIM_CheckIsSafeToFold, /*InsnID*/3,
        GIM_CheckComplexPattern, /*MI*/1, /*Op*/1, /*Renderer*/GIMT_Encode2(0), GIMT_Encode2(GICP_gi_vop3mods),
        GIM_CheckComplexPattern, /*MI*/1, /*Op*/2, /*Renderer*/GIMT_Encode2(1), GIMT_Encode2(GICP_gi_vop3mods),
        GIM_CheckComplexPattern, /*MI*/2, /*Op*/2, /*Renderer*/GIMT_Encode2(2), GIMT_Encode2(GICP_gi_vop3mods),
        // (fmaxnum_ieee:{ *:[f16] } (fminnum:{ *:[f16] } (VOP3Mods:{ *:[f16] } f16:{ *:[f16] }:$src1, i32:{ *:[i32] }:$src1_mods), (VOP3Mods:{ *:[f16] } f16:{ *:[f16] }:$src0, i32:{ *:[i32] }:$src0_mods)), (fminnum_ieee:{ *:[f16] } (fmaxnum_ieee:{ *:[f16] } (VOP3Mods:{ *:[f16] } f16:{ *:[f16] }:$src1, i32:{ *:[i32] }:$src1_mods), (VOP3Mods:{ *:[f16] } f16:{ *:[f16] }:$src0, i32:{ *:[i32] }:$src0_mods)), (VOP3Mods:{ *:[f16] } f16:{ *:[f16] }:$src2, i32:{ *:[i32] }:$src2_mods)))<<P:Predicate_fmaxnum_like_nnan>>  =>  (V_MED3_F16_e64:{ *:[f16] } ?:{ *:[i32] }:$src0_mods, ?:{ *:[f16] }:$src0, ?:{ *:[i32] }:$src1_mods, ?:{ *:[f16] }:$src1, ?:{ *:[i32] }:$src2_mods, ?:{ *:[f16] }:$src2, 0:{ *:[i1] })
        GIR_BuildMI, /*InsnID*/0, /*Opcode*/GIMT_Encode2(AMDGPU::V_MED3_F16_e64),
        GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/0, // DstI[vdst]
        GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(1), /*SubOperand*/1, // src0_mods
        GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(1), /*SubOperand*/0, // src0
        GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/1, // src1_mods
        GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/0, // src1
        GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(2), /*SubOperand*/1, // src2_mods
        GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(2), /*SubOperand*/0, // src2
        GIR_AddImm8, /*InsnID*/0, /*Imm*/0,
        GIR_AddImm8, /*InsnID*/0, /*Imm*/0,
        GIR_AddImm8, /*InsnID*/0, /*Imm*/0,
        GIR_ConstrainSelectedInstOperands, /*InsnID*/0,
        GIR_EraseFromParent, /*InsnID*/0,
        // GIR_Coverage, 10594,
        GIR_Done,
      // Label 4949: @351106
      GIM_Try, /*On fail goto*//*Label 4950*/ GIMT_Encode4(351252), // Rule ID 10646 //
        GIM_CheckFeatures, GIMT_Encode2(GIFBS_isGFX9Plus),
        GIM_CheckRegBankForClass, /*MI*/0, /*Op*/0, /*RC*/GIMT_Encode2(AMDGPU::VGPR_32RegClassID),
        GIM_RecordInsn, /*DefineMI*/1, /*MI*/0, /*OpIdx*/1, // MIs[1]
        GIM_CheckOpcode, /*MI*/1, GIMT_Encode2(TargetOpcode::G_FMINNUM),
        GIM_CheckType, /*MI*/1, /*Op*/1, /*Type*/GILLT_s16,
        GIM_CheckType, /*MI*/1, /*Op*/2, /*Type*/GILLT_s16,
        GIM_RecordInsn, /*DefineMI*/2, /*MI*/1, /*OpIdx*/2, // MIs[2]
        GIM_CheckOpcode, /*MI*/2, GIMT_Encode2(TargetOpcode::G_FMAXNUM),
        GIM_CheckType, /*MI*/2, /*Op*/1, /*Type*/GILLT_s16,
        GIM_CheckType, /*MI*/2, /*Op*/2, /*Type*/GILLT_s16,
        GIM_RecordInsn, /*DefineMI*/3, /*MI*/0, /*OpIdx*/2, // MIs[3]
        GIM_CheckOpcode, /*MI*/3, GIMT_Encode2(TargetOpcode::G_FMINNUM),
        // MIs[3] VOP3Mods:src0:src0_mods
        GIM_CheckIsSameOperand, /*MI*/3, /*OpIdx*/1, /*OtherMI*/2, /*OtherOpIdx*/1,
        // MIs[3] VOP3Mods:src1:src1_mods
        GIM_CheckIsSameOperand, /*MI*/3, /*OpIdx*/2, /*OtherMI*/2, /*OtherOpIdx*/2,
        GIM_CheckCxxInsnPredicate, /*MI*/0, /*FnId*/GIMT_Encode2(GICXXPred_MI_Predicate_fmaxnum_like_nnan),
        GIM_CheckIsSafeToFold, /*InsnID*/1,
        GIM_CheckIsSafeToFold, /*InsnID*/2,
        GIM_CheckIsSafeToFold, /*InsnID*/3,
        GIM_CheckComplexPattern, /*MI*/1, /*Op*/1, /*Renderer*/GIMT_Encode2(0), GIMT_Encode2(GICP_gi_vop3mods),
        GIM_CheckComplexPattern, /*MI*/2, /*Op*/1, /*Renderer*/GIMT_Encode2(1), GIMT_Encode2(GICP_gi_vop3mods),
        GIM_CheckComplexPattern, /*MI*/2, /*Op*/2, /*Renderer*/GIMT_Encode2(2), GIMT_Encode2(GICP_gi_vop3mods),
        // (fmaxnum_ieee:{ *:[f16] } (fminnum:{ *:[f16] } (VOP3Mods:{ *:[f16] } f16:{ *:[f16] }:$src2, i32:{ *:[i32] }:$src2_mods), (fmaxnum:{ *:[f16] } (VOP3Mods:{ *:[f16] } f16:{ *:[f16] }:$src0, i32:{ *:[i32] }:$src0_mods), (VOP3Mods:{ *:[f16] } f16:{ *:[f16] }:$src1, i32:{ *:[i32] }:$src1_mods))), (fminnum:{ *:[f16] } (VOP3Mods:{ *:[f16] } f16:{ *:[f16] }:$src0, i32:{ *:[i32] }:$src0_mods), (VOP3Mods:{ *:[f16] } f16:{ *:[f16] }:$src1, i32:{ *:[i32] }:$src1_mods)))<<P:Predicate_fmaxnum_like_nnan>>  =>  (V_MED3_F16_e64:{ *:[f16] } ?:{ *:[i32] }:$src0_mods, ?:{ *:[f16] }:$src0, ?:{ *:[i32] }:$src1_mods, ?:{ *:[f16] }:$src1, ?:{ *:[i32] }:$src2_mods, ?:{ *:[f16] }:$src2, 0:{ *:[i1] })
        GIR_BuildMI, /*InsnID*/0, /*Opcode*/GIMT_Encode2(AMDGPU::V_MED3_F16_e64),
        GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/0, // DstI[vdst]
        GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(1), /*SubOperand*/1, // src0_mods
        GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(1), /*SubOperand*/0, // src0
        GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(2), /*SubOperand*/1, // src1_mods
        GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(2), /*SubOperand*/0, // src1
        GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/1, // src2_mods
        GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/0, // src2
        GIR_AddImm8, /*InsnID*/0, /*Imm*/0,
        GIR_AddImm8, /*InsnID*/0, /*Imm*/0,
        GIR_AddImm8, /*InsnID*/0, /*Imm*/0,
        GIR_ConstrainSelectedInstOperands, /*InsnID*/0,
        GIR_EraseFromParent, /*InsnID*/0,
        // GIR_Coverage, 10646,
        GIR_Done,
      // Label 4950: @351252
      GIM_Try, /*On fail goto*//*Label 4951*/ GIMT_Encode4(351398), // Rule ID 10647 //
        GIM_CheckFeatures, GIMT_Encode2(GIFBS_isGFX9Plus),
        GIM_CheckRegBankForClass, /*MI*/0, /*Op*/0, /*RC*/GIMT_Encode2(AMDGPU::VGPR_32RegClassID),
        GIM_RecordInsn, /*DefineMI*/1, /*MI*/0, /*OpIdx*/1, // MIs[1]
        GIM_CheckOpcode, /*MI*/1, GIMT_Encode2(TargetOpcode::G_FMINNUM),
        GIM_CheckType, /*MI*/1, /*Op*/1, /*Type*/GILLT_s16,
        GIM_CheckType, /*MI*/1, /*Op*/2, /*Type*/GILLT_s16,
        GIM_RecordInsn, /*DefineMI*/2, /*MI*/1, /*OpIdx*/2, // MIs[2]
        GIM_CheckOpcode, /*MI*/2, GIMT_Encode2(TargetOpcode::G_FMAXNUM),
        GIM_CheckType, /*MI*/2, /*Op*/1, /*Type*/GILLT_s16,
        GIM_CheckType, /*MI*/2, /*Op*/2, /*Type*/GILLT_s16,
        GIM_RecordInsn, /*DefineMI*/3, /*MI*/0, /*OpIdx*/2, // MIs[3]
        GIM_CheckOpcode, /*MI*/3, GIMT_Encode2(TargetOpcode::G_FMINNUM),
        // MIs[3] VOP3Mods:src1:src1_mods
        GIM_CheckIsSameOperand, /*MI*/3, /*OpIdx*/1, /*OtherMI*/2, /*OtherOpIdx*/2,
        // MIs[3] VOP3Mods:src0:src0_mods
        GIM_CheckIsSameOperand, /*MI*/3, /*OpIdx*/2, /*OtherMI*/2, /*OtherOpIdx*/1,
        GIM_CheckCxxInsnPredicate, /*MI*/0, /*FnId*/GIMT_Encode2(GICXXPred_MI_Predicate_fmaxnum_like_nnan),
        GIM_CheckIsSafeToFold, /*InsnID*/1,
        GIM_CheckIsSafeToFold, /*InsnID*/2,
        GIM_CheckIsSafeToFold, /*InsnID*/3,
        GIM_CheckComplexPattern, /*MI*/1, /*Op*/1, /*Renderer*/GIMT_Encode2(0), GIMT_Encode2(GICP_gi_vop3mods),
        GIM_CheckComplexPattern, /*MI*/2, /*Op*/1, /*Renderer*/GIMT_Encode2(1), GIMT_Encode2(GICP_gi_vop3mods),
        GIM_CheckComplexPattern, /*MI*/2, /*Op*/2, /*Renderer*/GIMT_Encode2(2), GIMT_Encode2(GICP_gi_vop3mods),
        // (fmaxnum_ieee:{ *:[f16] } (fminnum:{ *:[f16] } (VOP3Mods:{ *:[f16] } f16:{ *:[f16] }:$src2, i32:{ *:[i32] }:$src2_mods), (fmaxnum:{ *:[f16] } (VOP3Mods:{ *:[f16] } f16:{ *:[f16] }:$src0, i32:{ *:[i32] }:$src0_mods), (VOP3Mods:{ *:[f16] } f16:{ *:[f16] }:$src1, i32:{ *:[i32] }:$src1_mods))), (fminnum:{ *:[f16] } (VOP3Mods:{ *:[f16] } f16:{ *:[f16] }:$src1, i32:{ *:[i32] }:$src1_mods), (VOP3Mods:{ *:[f16] } f16:{ *:[f16] }:$src0, i32:{ *:[i32] }:$src0_mods)))<<P:Predicate_fmaxnum_like_nnan>>  =>  (V_MED3_F16_e64:{ *:[f16] } ?:{ *:[i32] }:$src0_mods, ?:{ *:[f16] }:$src0, ?:{ *:[i32] }:$src1_mods, ?:{ *:[f16] }:$src1, ?:{ *:[i32] }:$src2_mods, ?:{ *:[f16] }:$src2, 0:{ *:[i1] })
        GIR_BuildMI, /*InsnID*/0, /*Opcode*/GIMT_Encode2(AMDGPU::V_MED3_F16_e64),
        GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/0, // DstI[vdst]
        GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(1), /*SubOperand*/1, // src0_mods
        GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(1), /*SubOperand*/0, // src0
        GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(2), /*SubOperand*/1, // src1_mods
        GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(2), /*SubOperand*/0, // src1
        GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/1, // src2_mods
        GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/0, // src2
        GIR_AddImm8, /*InsnID*/0, /*Imm*/0,
        GIR_AddImm8, /*InsnID*/0, /*Imm*/0,
        GIR_AddImm8, /*InsnID*/0, /*Imm*/0,
        GIR_ConstrainSelectedInstOperands, /*InsnID*/0,
        GIR_EraseFromParent, /*InsnID*/0,
        // GIR_Coverage, 10647,
        GIR_Done,
      // Label 4951: @351398
      GIM_Try, /*On fail goto*//*Label 4952*/ GIMT_Encode4(351544), // Rule ID 10648 //
        GIM_CheckFeatures, GIMT_Encode2(GIFBS_isGFX9Plus),
        GIM_CheckRegBankForClass, /*MI*/0, /*Op*/0, /*RC*/GIMT_Encode2(AMDGPU::VGPR_32RegClassID),
        GIM_RecordInsn, /*DefineMI*/1, /*MI*/0, /*OpIdx*/1, // MIs[1]
        GIM_CheckOpcode, /*MI*/1, GIMT_Encode2(TargetOpcode::G_FMINNUM),
        GIM_CheckType, /*MI*/1, /*Op*/1, /*Type*/GILLT_s16,
        GIM_CheckType, /*MI*/1, /*Op*/2, /*Type*/GILLT_s16,
        GIM_RecordInsn, /*DefineMI*/2, /*MI*/1, /*OpIdx*/2, // MIs[2]
        GIM_CheckOpcode, /*MI*/2, GIMT_Encode2(TargetOpcode::G_FMAXNUM),
        GIM_CheckType, /*MI*/2, /*Op*/1, /*Type*/GILLT_s16,
        GIM_CheckType, /*MI*/2, /*Op*/2, /*Type*/GILLT_s16,
        GIM_RecordInsn, /*DefineMI*/3, /*MI*/0, /*OpIdx*/2, // MIs[3]
        GIM_CheckOpcode, /*MI*/3, GIMT_Encode2(TargetOpcode::G_FMINNUM),
        // MIs[3] VOP3Mods:src0:src0_mods
        GIM_CheckIsSameOperand, /*MI*/3, /*OpIdx*/1, /*OtherMI*/2, /*OtherOpIdx*/2,
        // MIs[3] VOP3Mods:src1:src1_mods
        GIM_CheckIsSameOperand, /*MI*/3, /*OpIdx*/2, /*OtherMI*/2, /*OtherOpIdx*/1,
        GIM_CheckCxxInsnPredicate, /*MI*/0, /*FnId*/GIMT_Encode2(GICXXPred_MI_Predicate_fmaxnum_like_nnan),
        GIM_CheckIsSafeToFold, /*InsnID*/1,
        GIM_CheckIsSafeToFold, /*InsnID*/2,
        GIM_CheckIsSafeToFold, /*InsnID*/3,
        GIM_CheckComplexPattern, /*MI*/1, /*Op*/1, /*Renderer*/GIMT_Encode2(0), GIMT_Encode2(GICP_gi_vop3mods),
        GIM_CheckComplexPattern, /*MI*/2, /*Op*/1, /*Renderer*/GIMT_Encode2(1), GIMT_Encode2(GICP_gi_vop3mods),
        GIM_CheckComplexPattern, /*MI*/2, /*Op*/2, /*Renderer*/GIMT_Encode2(2), GIMT_Encode2(GICP_gi_vop3mods),
        // (fmaxnum_ieee:{ *:[f16] } (fminnum:{ *:[f16] } (VOP3Mods:{ *:[f16] } f16:{ *:[f16] }:$src2, i32:{ *:[i32] }:$src2_mods), (fmaxnum:{ *:[f16] } (VOP3Mods:{ *:[f16] } f16:{ *:[f16] }:$src1, i32:{ *:[i32] }:$src1_mods), (VOP3Mods:{ *:[f16] } f16:{ *:[f16] }:$src0, i32:{ *:[i32] }:$src0_mods))), (fminnum:{ *:[f16] } (VOP3Mods:{ *:[f16] } f16:{ *:[f16] }:$src0, i32:{ *:[i32] }:$src0_mods), (VOP3Mods:{ *:[f16] } f16:{ *:[f16] }:$src1, i32:{ *:[i32] }:$src1_mods)))<<P:Predicate_fmaxnum_like_nnan>>  =>  (V_MED3_F16_e64:{ *:[f16] } ?:{ *:[i32] }:$src0_mods, ?:{ *:[f16] }:$src0, ?:{ *:[i32] }:$src1_mods, ?:{ *:[f16] }:$src1, ?:{ *:[i32] }:$src2_mods, ?:{ *:[f16] }:$src2, 0:{ *:[i1] })
        GIR_BuildMI, /*InsnID*/0, /*Opcode*/GIMT_Encode2(AMDGPU::V_MED3_F16_e64),
        GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/0, // DstI[vdst]
        GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(2), /*SubOperand*/1, // src0_mods
        GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(2), /*SubOperand*/0, // src0
        GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(1), /*SubOperand*/1, // src1_mods
        GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(1), /*SubOperand*/0, // src1
        GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/1, // src2_mods
        GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/0, // src2
        GIR_AddImm8, /*InsnID*/0, /*Imm*/0,
        GIR_AddImm8, /*InsnID*/0, /*Imm*/0,
        GIR_AddImm8, /*InsnID*/0, /*Imm*/0,
        GIR_ConstrainSelectedInstOperands, /*InsnID*/0,
        GIR_EraseFromParent, /*InsnID*/0,
        // GIR_Coverage, 10648,
        GIR_Done,
      // Label 4952: @351544
      GIM_Try, /*On fail goto*//*Label 4953*/ GIMT_Encode4(351690), // Rule ID 10649 //
        GIM_CheckFeatures, GIMT_Encode2(GIFBS_isGFX9Plus),
        GIM_CheckRegBankForClass, /*MI*/0, /*Op*/0, /*RC*/GIMT_Encode2(AMDGPU::VGPR_32RegClassID),
        GIM_RecordInsn, /*DefineMI*/1, /*MI*/0, /*OpIdx*/1, // MIs[1]
        GIM_CheckOpcode, /*MI*/1, GIMT_Encode2(TargetOpcode::G_FMINNUM),
        GIM_CheckType, /*MI*/1, /*Op*/1, /*Type*/GILLT_s16,
        GIM_CheckType, /*MI*/1, /*Op*/2, /*Type*/GILLT_s16,
        GIM_RecordInsn, /*DefineMI*/2, /*MI*/1, /*OpIdx*/2, // MIs[2]
        GIM_CheckOpcode, /*MI*/2, GIMT_Encode2(TargetOpcode::G_FMAXNUM),
        GIM_CheckType, /*MI*/2, /*Op*/1, /*Type*/GILLT_s16,
        GIM_CheckType, /*MI*/2, /*Op*/2, /*Type*/GILLT_s16,
        GIM_RecordInsn, /*DefineMI*/3, /*MI*/0, /*OpIdx*/2, // MIs[3]
        GIM_CheckOpcode, /*MI*/3, GIMT_Encode2(TargetOpcode::G_FMINNUM),
        // MIs[3] VOP3Mods:src1:src1_mods
        GIM_CheckIsSameOperand, /*MI*/3, /*OpIdx*/1, /*OtherMI*/2, /*OtherOpIdx*/1,
        // MIs[3] VOP3Mods:src0:src0_mods
        GIM_CheckIsSameOperand, /*MI*/3, /*OpIdx*/2, /*OtherMI*/2, /*OtherOpIdx*/2,
        GIM_CheckCxxInsnPredicate, /*MI*/0, /*FnId*/GIMT_Encode2(GICXXPred_MI_Predicate_fmaxnum_like_nnan),
        GIM_CheckIsSafeToFold, /*InsnID*/1,
        GIM_CheckIsSafeToFold, /*InsnID*/2,
        GIM_CheckIsSafeToFold, /*InsnID*/3,
        GIM_CheckComplexPattern, /*MI*/1, /*Op*/1, /*Renderer*/GIMT_Encode2(0), GIMT_Encode2(GICP_gi_vop3mods),
        GIM_CheckComplexPattern, /*MI*/2, /*Op*/1, /*Renderer*/GIMT_Encode2(1), GIMT_Encode2(GICP_gi_vop3mods),
        GIM_CheckComplexPattern, /*MI*/2, /*Op*/2, /*Renderer*/GIMT_Encode2(2), GIMT_Encode2(GICP_gi_vop3mods),
        // (fmaxnum_ieee:{ *:[f16] } (fminnum:{ *:[f16] } (VOP3Mods:{ *:[f16] } f16:{ *:[f16] }:$src2, i32:{ *:[i32] }:$src2_mods), (fmaxnum:{ *:[f16] } (VOP3Mods:{ *:[f16] } f16:{ *:[f16] }:$src1, i32:{ *:[i32] }:$src1_mods), (VOP3Mods:{ *:[f16] } f16:{ *:[f16] }:$src0, i32:{ *:[i32] }:$src0_mods))), (fminnum:{ *:[f16] } (VOP3Mods:{ *:[f16] } f16:{ *:[f16] }:$src1, i32:{ *:[i32] }:$src1_mods), (VOP3Mods:{ *:[f16] } f16:{ *:[f16] }:$src0, i32:{ *:[i32] }:$src0_mods)))<<P:Predicate_fmaxnum_like_nnan>>  =>  (V_MED3_F16_e64:{ *:[f16] } ?:{ *:[i32] }:$src0_mods, ?:{ *:[f16] }:$src0, ?:{ *:[i32] }:$src1_mods, ?:{ *:[f16] }:$src1, ?:{ *:[i32] }:$src2_mods, ?:{ *:[f16] }:$src2, 0:{ *:[i1] })
        GIR_BuildMI, /*InsnID*/0, /*Opcode*/GIMT_Encode2(AMDGPU::V_MED3_F16_e64),
        GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/0, // DstI[vdst]
        GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(2), /*SubOperand*/1, // src0_mods
        GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(2), /*SubOperand*/0, // src0
        GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(1), /*SubOperand*/1, // src1_mods
        GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(1), /*SubOperand*/0, // src1
        GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/1, // src2_mods
        GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/0, // src2
        GIR_AddImm8, /*InsnID*/0, /*Imm*/0,
        GIR_AddImm8, /*InsnID*/0, /*Imm*/0,
        GIR_AddImm8, /*InsnID*/0, /*Imm*/0,
        GIR_ConstrainSelectedInstOperands, /*InsnID*/0,
        GIR_EraseFromParent, /*InsnID*/0,
        // GIR_Coverage, 10649,
        GIR_Done,
      // Label 4953: @351690
      GIM_Try, /*On fail goto*//*Label 4954*/ GIMT_Encode4(351836), // Rule ID 10586 //
        GIM_CheckFeatures, GIMT_Encode2(GIFBS_isGFX9Plus),
        GIM_CheckRegBankForClass, /*MI*/0, /*Op*/0, /*RC*/GIMT_Encode2(AMDGPU::VGPR_32RegClassID),
        GIM_RecordInsn, /*DefineMI*/1, /*MI*/0, /*OpIdx*/1, // MIs[1]
        GIM_CheckOpcode, /*MI*/1, GIMT_Encode2(TargetOpcode::G_FMINNUM),
        GIM_CheckType, /*MI*/1, /*Op*/1, /*Type*/GILLT_s16,
        GIM_CheckType, /*MI*/1, /*Op*/2, /*Type*/GILLT_s16,
        GIM_RecordInsn, /*DefineMI*/2, /*MI*/1, /*OpIdx*/2, // MIs[2]
        GIM_CheckOpcode, /*MI*/2, GIMT_Encode2(TargetOpcode::G_FMAXNUM),
        GIM_CheckType, /*MI*/2, /*Op*/1, /*Type*/GILLT_s16,
        GIM_CheckType, /*MI*/2, /*Op*/2, /*Type*/GILLT_s16,
        GIM_RecordInsn, /*DefineMI*/3, /*MI*/0, /*OpIdx*/2, // MIs[3]
        GIM_CheckOpcode, /*MI*/3, GIMT_Encode2(TargetOpcode::G_FMINNUM_IEEE),
        // MIs[3] VOP3Mods:src0:src0_mods
        GIM_CheckIsSameOperand, /*MI*/3, /*OpIdx*/1, /*OtherMI*/2, /*OtherOpIdx*/1,
        // MIs[3] VOP3Mods:src1:src1_mods
        GIM_CheckIsSameOperand, /*MI*/3, /*OpIdx*/2, /*OtherMI*/2, /*OtherOpIdx*/2,
        GIM_CheckCxxInsnPredicate, /*MI*/0, /*FnId*/GIMT_Encode2(GICXXPred_MI_Predicate_fmaxnum_like_nnan),
        GIM_CheckIsSafeToFold, /*InsnID*/1,
        GIM_CheckIsSafeToFold, /*InsnID*/2,
        GIM_CheckIsSafeToFold, /*InsnID*/3,
        GIM_CheckComplexPattern, /*MI*/1, /*Op*/1, /*Renderer*/GIMT_Encode2(0), GIMT_Encode2(GICP_gi_vop3mods),
        GIM_CheckComplexPattern, /*MI*/2, /*Op*/1, /*Renderer*/GIMT_Encode2(1), GIMT_Encode2(GICP_gi_vop3mods),
        GIM_CheckComplexPattern, /*MI*/2, /*Op*/2, /*Renderer*/GIMT_Encode2(2), GIMT_Encode2(GICP_gi_vop3mods),
        // (fmaxnum_ieee:{ *:[f16] } (fminnum:{ *:[f16] } (VOP3Mods:{ *:[f16] } f16:{ *:[f16] }:$src2, i32:{ *:[i32] }:$src2_mods), (fmaxnum:{ *:[f16] } (VOP3Mods:{ *:[f16] } f16:{ *:[f16] }:$src0, i32:{ *:[i32] }:$src0_mods), (VOP3Mods:{ *:[f16] } f16:{ *:[f16] }:$src1, i32:{ *:[i32] }:$src1_mods))), (fminnum_ieee:{ *:[f16] } (VOP3Mods:{ *:[f16] } f16:{ *:[f16] }:$src0, i32:{ *:[i32] }:$src0_mods), (VOP3Mods:{ *:[f16] } f16:{ *:[f16] }:$src1, i32:{ *:[i32] }:$src1_mods)))<<P:Predicate_fmaxnum_like_nnan>>  =>  (V_MED3_F16_e64:{ *:[f16] } ?:{ *:[i32] }:$src0_mods, ?:{ *:[f16] }:$src0, ?:{ *:[i32] }:$src1_mods, ?:{ *:[f16] }:$src1, ?:{ *:[i32] }:$src2_mods, ?:{ *:[f16] }:$src2, 0:{ *:[i1] })
        GIR_BuildMI, /*InsnID*/0, /*Opcode*/GIMT_Encode2(AMDGPU::V_MED3_F16_e64),
        GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/0, // DstI[vdst]
        GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(1), /*SubOperand*/1, // src0_mods
        GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(1), /*SubOperand*/0, // src0
        GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(2), /*SubOperand*/1, // src1_mods
        GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(2), /*SubOperand*/0, // src1
        GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/1, // src2_mods
        GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/0, // src2
        GIR_AddImm8, /*InsnID*/0, /*Imm*/0,
        GIR_AddImm8, /*InsnID*/0, /*Imm*/0,
        GIR_AddImm8, /*InsnID*/0, /*Imm*/0,
        GIR_ConstrainSelectedInstOperands, /*InsnID*/0,
        GIR_EraseFromParent, /*InsnID*/0,
        // GIR_Coverage, 10586,
        GIR_Done,
      // Label 4954: @351836
      GIM_Try, /*On fail goto*//*Label 4955*/ GIMT_Encode4(351982), // Rule ID 10587 //
        GIM_CheckFeatures, GIMT_Encode2(GIFBS_isGFX9Plus),
        GIM_CheckRegBankForClass, /*MI*/0, /*Op*/0, /*RC*/GIMT_Encode2(AMDGPU::VGPR_32RegClassID),
        GIM_RecordInsn, /*DefineMI*/1, /*MI*/0, /*OpIdx*/1, // MIs[1]
        GIM_CheckOpcode, /*MI*/1, GIMT_Encode2(TargetOpcode::G_FMINNUM),
        GIM_CheckType, /*MI*/1, /*Op*/1, /*Type*/GILLT_s16,
        GIM_CheckType, /*MI*/1, /*Op*/2, /*Type*/GILLT_s16,
        GIM_RecordInsn, /*DefineMI*/2, /*MI*/1, /*OpIdx*/2, // MIs[2]
        GIM_CheckOpcode, /*MI*/2, GIMT_Encode2(TargetOpcode::G_FMAXNUM),
        GIM_CheckType, /*MI*/2, /*Op*/1, /*Type*/GILLT_s16,
        GIM_CheckType, /*MI*/2, /*Op*/2, /*Type*/GILLT_s16,
        GIM_RecordInsn, /*DefineMI*/3, /*MI*/0, /*OpIdx*/2, // MIs[3]
        GIM_CheckOpcode, /*MI*/3, GIMT_Encode2(TargetOpcode::G_FMINNUM_IEEE),
        // MIs[3] VOP3Mods:src1:src1_mods
        GIM_CheckIsSameOperand, /*MI*/3, /*OpIdx*/1, /*OtherMI*/2, /*OtherOpIdx*/2,
        // MIs[3] VOP3Mods:src0:src0_mods
        GIM_CheckIsSameOperand, /*MI*/3, /*OpIdx*/2, /*OtherMI*/2, /*OtherOpIdx*/1,
        GIM_CheckCxxInsnPredicate, /*MI*/0, /*FnId*/GIMT_Encode2(GICXXPred_MI_Predicate_fmaxnum_like_nnan),
        GIM_CheckIsSafeToFold, /*InsnID*/1,
        GIM_CheckIsSafeToFold, /*InsnID*/2,
        GIM_CheckIsSafeToFold, /*InsnID*/3,
        GIM_CheckComplexPattern, /*MI*/1, /*Op*/1, /*Renderer*/GIMT_Encode2(0), GIMT_Encode2(GICP_gi_vop3mods),
        GIM_CheckComplexPattern, /*MI*/2, /*Op*/1, /*Renderer*/GIMT_Encode2(1), GIMT_Encode2(GICP_gi_vop3mods),
        GIM_CheckComplexPattern, /*MI*/2, /*Op*/2, /*Renderer*/GIMT_Encode2(2), GIMT_Encode2(GICP_gi_vop3mods),
        // (fmaxnum_ieee:{ *:[f16] } (fminnum:{ *:[f16] } (VOP3Mods:{ *:[f16] } f16:{ *:[f16] }:$src2, i32:{ *:[i32] }:$src2_mods), (fmaxnum:{ *:[f16] } (VOP3Mods:{ *:[f16] } f16:{ *:[f16] }:$src0, i32:{ *:[i32] }:$src0_mods), (VOP3Mods:{ *:[f16] } f16:{ *:[f16] }:$src1, i32:{ *:[i32] }:$src1_mods))), (fminnum_ieee:{ *:[f16] } (VOP3Mods:{ *:[f16] } f16:{ *:[f16] }:$src1, i32:{ *:[i32] }:$src1_mods), (VOP3Mods:{ *:[f16] } f16:{ *:[f16] }:$src0, i32:{ *:[i32] }:$src0_mods)))<<P:Predicate_fmaxnum_like_nnan>>  =>  (V_MED3_F16_e64:{ *:[f16] } ?:{ *:[i32] }:$src0_mods, ?:{ *:[f16] }:$src0, ?:{ *:[i32] }:$src1_mods, ?:{ *:[f16] }:$src1, ?:{ *:[i32] }:$src2_mods, ?:{ *:[f16] }:$src2, 0:{ *:[i1] })
        GIR_BuildMI, /*InsnID*/0, /*Opcode*/GIMT_Encode2(AMDGPU::V_MED3_F16_e64),
        GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/0, // DstI[vdst]
        GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(1), /*SubOperand*/1, // src0_mods
        GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(1), /*SubOperand*/0, // src0
        GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(2), /*SubOperand*/1, // src1_mods
        GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(2), /*SubOperand*/0, // src1
        GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/1, // src2_mods
        GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/0, // src2
        GIR_AddImm8, /*InsnID*/0, /*Imm*/0,
        GIR_AddImm8, /*InsnID*/0, /*Imm*/0,
        GIR_AddImm8, /*InsnID*/0, /*Imm*/0,
        GIR_ConstrainSelectedInstOperands, /*InsnID*/0,
        GIR_EraseFromParent, /*InsnID*/0,
        // GIR_Coverage, 10587,
        GIR_Done,
      // Label 4955: @351982
      GIM_Try, /*On fail goto*//*Label 4956*/ GIMT_Encode4(352128), // Rule ID 10588 //
        GIM_CheckFeatures, GIMT_Encode2(GIFBS_isGFX9Plus),
        GIM_CheckRegBankForClass, /*MI*/0, /*Op*/0, /*RC*/GIMT_Encode2(AMDGPU::VGPR_32RegClassID),
        GIM_RecordInsn, /*DefineMI*/1, /*MI*/0, /*OpIdx*/1, // MIs[1]
        GIM_CheckOpcode, /*MI*/1, GIMT_Encode2(TargetOpcode::G_FMINNUM),
        GIM_CheckType, /*MI*/1, /*Op*/1, /*Type*/GILLT_s16,
        GIM_CheckType, /*MI*/1, /*Op*/2, /*Type*/GILLT_s16,
        GIM_RecordInsn, /*DefineMI*/2, /*MI*/1, /*OpIdx*/2, // MIs[2]
        GIM_CheckOpcode, /*MI*/2, GIMT_Encode2(TargetOpcode::G_FMAXNUM),
        GIM_CheckType, /*MI*/2, /*Op*/1, /*Type*/GILLT_s16,
        GIM_CheckType, /*MI*/2, /*Op*/2, /*Type*/GILLT_s16,
        GIM_RecordInsn, /*DefineMI*/3, /*MI*/0, /*OpIdx*/2, // MIs[3]
        GIM_CheckOpcode, /*MI*/3, GIMT_Encode2(TargetOpcode::G_FMINNUM_IEEE),
        // MIs[3] VOP3Mods:src0:src0_mods
        GIM_CheckIsSameOperand, /*MI*/3, /*OpIdx*/1, /*OtherMI*/2, /*OtherOpIdx*/2,
        // MIs[3] VOP3Mods:src1:src1_mods
        GIM_CheckIsSameOperand, /*MI*/3, /*OpIdx*/2, /*OtherMI*/2, /*OtherOpIdx*/1,
        GIM_CheckCxxInsnPredicate, /*MI*/0, /*FnId*/GIMT_Encode2(GICXXPred_MI_Predicate_fmaxnum_like_nnan),
        GIM_CheckIsSafeToFold, /*InsnID*/1,
        GIM_CheckIsSafeToFold, /*InsnID*/2,
        GIM_CheckIsSafeToFold, /*InsnID*/3,
        GIM_CheckComplexPattern, /*MI*/1, /*Op*/1, /*Renderer*/GIMT_Encode2(0), GIMT_Encode2(GICP_gi_vop3mods),
        GIM_CheckComplexPattern, /*MI*/2, /*Op*/1, /*Renderer*/GIMT_Encode2(1), GIMT_Encode2(GICP_gi_vop3mods),
        GIM_CheckComplexPattern, /*MI*/2, /*Op*/2, /*Renderer*/GIMT_Encode2(2), GIMT_Encode2(GICP_gi_vop3mods),
        // (fmaxnum_ieee:{ *:[f16] } (fminnum:{ *:[f16] } (VOP3Mods:{ *:[f16] } f16:{ *:[f16] }:$src2, i32:{ *:[i32] }:$src2_mods), (fmaxnum:{ *:[f16] } (VOP3Mods:{ *:[f16] } f16:{ *:[f16] }:$src1, i32:{ *:[i32] }:$src1_mods), (VOP3Mods:{ *:[f16] } f16:{ *:[f16] }:$src0, i32:{ *:[i32] }:$src0_mods))), (fminnum_ieee:{ *:[f16] } (VOP3Mods:{ *:[f16] } f16:{ *:[f16] }:$src0, i32:{ *:[i32] }:$src0_mods), (VOP3Mods:{ *:[f16] } f16:{ *:[f16] }:$src1, i32:{ *:[i32] }:$src1_mods)))<<P:Predicate_fmaxnum_like_nnan>>  =>  (V_MED3_F16_e64:{ *:[f16] } ?:{ *:[i32] }:$src0_mods, ?:{ *:[f16] }:$src0, ?:{ *:[i32] }:$src1_mods, ?:{ *:[f16] }:$src1, ?:{ *:[i32] }:$src2_mods, ?:{ *:[f16] }:$src2, 0:{ *:[i1] })
        GIR_BuildMI, /*InsnID*/0, /*Opcode*/GIMT_Encode2(AMDGPU::V_MED3_F16_e64),
        GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/0, // DstI[vdst]
        GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(2), /*SubOperand*/1, // src0_mods
        GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(2), /*SubOperand*/0, // src0
        GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(1), /*SubOperand*/1, // src1_mods
        GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(1), /*SubOperand*/0, // src1
        GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/1, // src2_mods
        GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/0, // src2
        GIR_AddImm8, /*InsnID*/0, /*Imm*/0,
        GIR_AddImm8, /*InsnID*/0, /*Imm*/0,
        GIR_AddImm8, /*InsnID*/0, /*Imm*/0,
        GIR_ConstrainSelectedInstOperands, /*InsnID*/0,
        GIR_EraseFromParent, /*InsnID*/0,
        // GIR_Coverage, 10588,
        GIR_Done,
      // Label 4956: @352128
      GIM_Try, /*On fail goto*//*Label 4957*/ GIMT_Encode4(352274), // Rule ID 10589 //
        GIM_CheckFeatures, GIMT_Encode2(GIFBS_isGFX9Plus),
        GIM_CheckRegBankForClass, /*MI*/0, /*Op*/0, /*RC*/GIMT_Encode2(AMDGPU::VGPR_32RegClassID),
        GIM_RecordInsn, /*DefineMI*/1, /*MI*/0, /*OpIdx*/1, // MIs[1]
        GIM_CheckOpcode, /*MI*/1, GIMT_Encode2(TargetOpcode::G_FMINNUM),
        GIM_CheckType, /*MI*/1, /*Op*/1, /*Type*/GILLT_s16,
        GIM_CheckType, /*MI*/1, /*Op*/2, /*Type*/GILLT_s16,
        GIM_RecordInsn, /*DefineMI*/2, /*MI*/1, /*OpIdx*/2, // MIs[2]
        GIM_CheckOpcode, /*MI*/2, GIMT_Encode2(TargetOpcode::G_FMAXNUM),
        GIM_CheckType, /*MI*/2, /*Op*/1, /*Type*/GILLT_s16,
        GIM_CheckType, /*MI*/2, /*Op*/2, /*Type*/GILLT_s16,
        GIM_RecordInsn, /*DefineMI*/3, /*MI*/0, /*OpIdx*/2, // MIs[3]
        GIM_CheckOpcode, /*MI*/3, GIMT_Encode2(TargetOpcode::G_FMINNUM_IEEE),
        // MIs[3] VOP3Mods:src1:src1_mods
        GIM_CheckIsSameOperand, /*MI*/3, /*OpIdx*/1, /*OtherMI*/2, /*OtherOpIdx*/1,
        // MIs[3] VOP3Mods:src0:src0_mods
        GIM_CheckIsSameOperand, /*MI*/3, /*OpIdx*/2, /*OtherMI*/2, /*OtherOpIdx*/2,
        GIM_CheckCxxInsnPredicate, /*MI*/0, /*FnId*/GIMT_Encode2(GICXXPred_MI_Predicate_fmaxnum_like_nnan),
        GIM_CheckIsSafeToFold, /*InsnID*/1,
        GIM_CheckIsSafeToFold, /*InsnID*/2,
        GIM_CheckIsSafeToFold, /*InsnID*/3,
        GIM_CheckComplexPattern, /*MI*/1, /*Op*/1, /*Renderer*/GIMT_Encode2(0), GIMT_Encode2(GICP_gi_vop3mods),
        GIM_CheckComplexPattern, /*MI*/2, /*Op*/1, /*Renderer*/GIMT_Encode2(1), GIMT_Encode2(GICP_gi_vop3mods),
        GIM_CheckComplexPattern, /*MI*/2, /*Op*/2, /*Renderer*/GIMT_Encode2(2), GIMT_Encode2(GICP_gi_vop3mods),
        // (fmaxnum_ieee:{ *:[f16] } (fminnum:{ *:[f16] } (VOP3Mods:{ *:[f16] } f16:{ *:[f16] }:$src2, i32:{ *:[i32] }:$src2_mods), (fmaxnum:{ *:[f16] } (VOP3Mods:{ *:[f16] } f16:{ *:[f16] }:$src1, i32:{ *:[i32] }:$src1_mods), (VOP3Mods:{ *:[f16] } f16:{ *:[f16] }:$src0, i32:{ *:[i32] }:$src0_mods))), (fminnum_ieee:{ *:[f16] } (VOP3Mods:{ *:[f16] } f16:{ *:[f16] }:$src1, i32:{ *:[i32] }:$src1_mods), (VOP3Mods:{ *:[f16] } f16:{ *:[f16] }:$src0, i32:{ *:[i32] }:$src0_mods)))<<P:Predicate_fmaxnum_like_nnan>>  =>  (V_MED3_F16_e64:{ *:[f16] } ?:{ *:[i32] }:$src0_mods, ?:{ *:[f16] }:$src0, ?:{ *:[i32] }:$src1_mods, ?:{ *:[f16] }:$src1, ?:{ *:[i32] }:$src2_mods, ?:{ *:[f16] }:$src2, 0:{ *:[i1] })
        GIR_BuildMI, /*InsnID*/0, /*Opcode*/GIMT_Encode2(AMDGPU::V_MED3_F16_e64),
        GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/0, // DstI[vdst]
        GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(2), /*SubOperand*/1, // src0_mods
        GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(2), /*SubOperand*/0, // src0
        GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(1), /*SubOperand*/1, // src1_mods
        GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(1), /*SubOperand*/0, // src1
        GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/1, // src2_mods
        GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/0, // src2
        GIR_AddImm8, /*InsnID*/0, /*Imm*/0,
        GIR_AddImm8, /*InsnID*/0, /*Imm*/0,
        GIR_AddImm8, /*InsnID*/0, /*Imm*/0,
        GIR_ConstrainSelectedInstOperands, /*InsnID*/0,
        GIR_EraseFromParent, /*InsnID*/0,
        // GIR_Coverage, 10589,
        GIR_Done,
      // Label 4957: @352274
      GIM_Try, /*On fail goto*//*Label 4958*/ GIMT_Encode4(352420), // Rule ID 10631 //
        GIM_CheckFeatures, GIMT_Encode2(GIFBS_isGFX9Plus),
        GIM_CheckRegBankForClass, /*MI*/0, /*Op*/0, /*RC*/GIMT_Encode2(AMDGPU::VGPR_32RegClassID),
        GIM_RecordInsn, /*DefineMI*/1, /*MI*/0, /*OpIdx*/1, // MIs[1]
        GIM_CheckOpcode, /*MI*/1, GIMT_Encode2(TargetOpcode::G_FMINNUM),
        GIM_CheckType, /*MI*/1, /*Op*/1, /*Type*/GILLT_s16,
        GIM_CheckType, /*MI*/1, /*Op*/2, /*Type*/GILLT_s16,
        GIM_RecordInsn, /*DefineMI*/2, /*MI*/1, /*OpIdx*/2, // MIs[2]
        GIM_CheckOpcode, /*MI*/2, GIMT_Encode2(TargetOpcode::G_FMAXNUM_IEEE),
        GIM_CheckType, /*MI*/2, /*Op*/1, /*Type*/GILLT_s16,
        GIM_CheckType, /*MI*/2, /*Op*/2, /*Type*/GILLT_s16,
        GIM_RecordInsn, /*DefineMI*/3, /*MI*/0, /*OpIdx*/2, // MIs[3]
        GIM_CheckOpcode, /*MI*/3, GIMT_Encode2(TargetOpcode::G_FMINNUM),
        // MIs[3] VOP3Mods:src0:src0_mods
        GIM_CheckIsSameOperand, /*MI*/3, /*OpIdx*/1, /*OtherMI*/2, /*OtherOpIdx*/1,
        // MIs[3] VOP3Mods:src1:src1_mods
        GIM_CheckIsSameOperand, /*MI*/3, /*OpIdx*/2, /*OtherMI*/2, /*OtherOpIdx*/2,
        GIM_CheckCxxInsnPredicate, /*MI*/0, /*FnId*/GIMT_Encode2(GICXXPred_MI_Predicate_fmaxnum_like_nnan),
        GIM_CheckIsSafeToFold, /*InsnID*/1,
        GIM_CheckIsSafeToFold, /*InsnID*/2,
        GIM_CheckIsSafeToFold, /*InsnID*/3,
        GIM_CheckComplexPattern, /*MI*/1, /*Op*/1, /*Renderer*/GIMT_Encode2(0), GIMT_Encode2(GICP_gi_vop3mods),
        GIM_CheckComplexPattern, /*MI*/2, /*Op*/1, /*Renderer*/GIMT_Encode2(1), GIMT_Encode2(GICP_gi_vop3mods),
        GIM_CheckComplexPattern, /*MI*/2, /*Op*/2, /*Renderer*/GIMT_Encode2(2), GIMT_Encode2(GICP_gi_vop3mods),
        // (fmaxnum_ieee:{ *:[f16] } (fminnum:{ *:[f16] } (VOP3Mods:{ *:[f16] } f16:{ *:[f16] }:$src2, i32:{ *:[i32] }:$src2_mods), (fmaxnum_ieee:{ *:[f16] } (VOP3Mods:{ *:[f16] } f16:{ *:[f16] }:$src0, i32:{ *:[i32] }:$src0_mods), (VOP3Mods:{ *:[f16] } f16:{ *:[f16] }:$src1, i32:{ *:[i32] }:$src1_mods))), (fminnum:{ *:[f16] } (VOP3Mods:{ *:[f16] } f16:{ *:[f16] }:$src0, i32:{ *:[i32] }:$src0_mods), (VOP3Mods:{ *:[f16] } f16:{ *:[f16] }:$src1, i32:{ *:[i32] }:$src1_mods)))<<P:Predicate_fmaxnum_like_nnan>>  =>  (V_MED3_F16_e64:{ *:[f16] } ?:{ *:[i32] }:$src0_mods, ?:{ *:[f16] }:$src0, ?:{ *:[i32] }:$src1_mods, ?:{ *:[f16] }:$src1, ?:{ *:[i32] }:$src2_mods, ?:{ *:[f16] }:$src2, 0:{ *:[i1] })
        GIR_BuildMI, /*InsnID*/0, /*Opcode*/GIMT_Encode2(AMDGPU::V_MED3_F16_e64),
        GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/0, // DstI[vdst]
        GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(1), /*SubOperand*/1, // src0_mods
        GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(1), /*SubOperand*/0, // src0
        GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(2), /*SubOperand*/1, // src1_mods
        GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(2), /*SubOperand*/0, // src1
        GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/1, // src2_mods
        GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/0, // src2
        GIR_AddImm8, /*InsnID*/0, /*Imm*/0,
        GIR_AddImm8, /*InsnID*/0, /*Imm*/0,
        GIR_AddImm8, /*InsnID*/0, /*Imm*/0,
        GIR_ConstrainSelectedInstOperands, /*InsnID*/0,
        GIR_EraseFromParent, /*InsnID*/0,
        // GIR_Coverage, 10631,
        GIR_Done,
      // Label 4958: @352420
      GIM_Try, /*On fail goto*//*Label 4959*/ GIMT_Encode4(352566), // Rule ID 10632 //
        GIM_CheckFeatures, GIMT_Encode2(GIFBS_isGFX9Plus),
        GIM_CheckRegBankForClass, /*MI*/0, /*Op*/0, /*RC*/GIMT_Encode2(AMDGPU::VGPR_32RegClassID),
        GIM_RecordInsn, /*DefineMI*/1, /*MI*/0, /*OpIdx*/1, // MIs[1]
        GIM_CheckOpcode, /*MI*/1, GIMT_Encode2(TargetOpcode::G_FMINNUM),
        GIM_CheckType, /*MI*/1, /*Op*/1, /*Type*/GILLT_s16,
        GIM_CheckType, /*MI*/1, /*Op*/2, /*Type*/GILLT_s16,
        GIM_RecordInsn, /*DefineMI*/2, /*MI*/1, /*OpIdx*/2, // MIs[2]
        GIM_CheckOpcode, /*MI*/2, GIMT_Encode2(TargetOpcode::G_FMAXNUM_IEEE),
        GIM_CheckType, /*MI*/2, /*Op*/1, /*Type*/GILLT_s16,
        GIM_CheckType, /*MI*/2, /*Op*/2, /*Type*/GILLT_s16,
        GIM_RecordInsn, /*DefineMI*/3, /*MI*/0, /*OpIdx*/2, // MIs[3]
        GIM_CheckOpcode, /*MI*/3, GIMT_Encode2(TargetOpcode::G_FMINNUM),
        // MIs[3] VOP3Mods:src1:src1_mods
        GIM_CheckIsSameOperand, /*MI*/3, /*OpIdx*/1, /*OtherMI*/2, /*OtherOpIdx*/2,
        // MIs[3] VOP3Mods:src0:src0_mods
        GIM_CheckIsSameOperand, /*MI*/3, /*OpIdx*/2, /*OtherMI*/2, /*OtherOpIdx*/1,
        GIM_CheckCxxInsnPredicate, /*MI*/0, /*FnId*/GIMT_Encode2(GICXXPred_MI_Predicate_fmaxnum_like_nnan),
        GIM_CheckIsSafeToFold, /*InsnID*/1,
        GIM_CheckIsSafeToFold, /*InsnID*/2,
        GIM_CheckIsSafeToFold, /*InsnID*/3,
        GIM_CheckComplexPattern, /*MI*/1, /*Op*/1, /*Renderer*/GIMT_Encode2(0), GIMT_Encode2(GICP_gi_vop3mods),
        GIM_CheckComplexPattern, /*MI*/2, /*Op*/1, /*Renderer*/GIMT_Encode2(1), GIMT_Encode2(GICP_gi_vop3mods),
        GIM_CheckComplexPattern, /*MI*/2, /*Op*/2, /*Renderer*/GIMT_Encode2(2), GIMT_Encode2(GICP_gi_vop3mods),
        // (fmaxnum_ieee:{ *:[f16] } (fminnum:{ *:[f16] } (VOP3Mods:{ *:[f16] } f16:{ *:[f16] }:$src2, i32:{ *:[i32] }:$src2_mods), (fmaxnum_ieee:{ *:[f16] } (VOP3Mods:{ *:[f16] } f16:{ *:[f16] }:$src0, i32:{ *:[i32] }:$src0_mods), (VOP3Mods:{ *:[f16] } f16:{ *:[f16] }:$src1, i32:{ *:[i32] }:$src1_mods))), (fminnum:{ *:[f16] } (VOP3Mods:{ *:[f16] } f16:{ *:[f16] }:$src1, i32:{ *:[i32] }:$src1_mods), (VOP3Mods:{ *:[f16] } f16:{ *:[f16] }:$src0, i32:{ *:[i32] }:$src0_mods)))<<P:Predicate_fmaxnum_like_nnan>>  =>  (V_MED3_F16_e64:{ *:[f16] } ?:{ *:[i32] }:$src0_mods, ?:{ *:[f16] }:$src0, ?:{ *:[i32] }:$src1_mods, ?:{ *:[f16] }:$src1, ?:{ *:[i32] }:$src2_mods, ?:{ *:[f16] }:$src2, 0:{ *:[i1] })
        GIR_BuildMI, /*InsnID*/0, /*Opcode*/GIMT_Encode2(AMDGPU::V_MED3_F16_e64),
        GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/0, // DstI[vdst]
        GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(1), /*SubOperand*/1, // src0_mods
        GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(1), /*SubOperand*/0, // src0
        GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(2), /*SubOperand*/1, // src1_mods
        GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(2), /*SubOperand*/0, // src1
        GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/1, // src2_mods
        GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/0, // src2
        GIR_AddImm8, /*InsnID*/0, /*Imm*/0,
        GIR_AddImm8, /*InsnID*/0, /*Imm*/0,
        GIR_AddImm8, /*InsnID*/0, /*Imm*/0,
        GIR_ConstrainSelectedInstOperands, /*InsnID*/0,
        GIR_EraseFromParent, /*InsnID*/0,
        // GIR_Coverage, 10632,
        GIR_Done,
      // Label 4959: @352566
      GIM_Try, /*On fail goto*//*Label 4960*/ GIMT_Encode4(352712), // Rule ID 10633 //
        GIM_CheckFeatures, GIMT_Encode2(GIFBS_isGFX9Plus),
        GIM_CheckRegBankForClass, /*MI*/0, /*Op*/0, /*RC*/GIMT_Encode2(AMDGPU::VGPR_32RegClassID),
        GIM_RecordInsn, /*DefineMI*/1, /*MI*/0, /*OpIdx*/1, // MIs[1]
        GIM_CheckOpcode, /*MI*/1, GIMT_Encode2(TargetOpcode::G_FMINNUM),
        GIM_CheckType, /*MI*/1, /*Op*/1, /*Type*/GILLT_s16,
        GIM_CheckType, /*MI*/1, /*Op*/2, /*Type*/GILLT_s16,
        GIM_RecordInsn, /*DefineMI*/2, /*MI*/1, /*OpIdx*/2, // MIs[2]
        GIM_CheckOpcode, /*MI*/2, GIMT_Encode2(TargetOpcode::G_FMAXNUM_IEEE),
        GIM_CheckType, /*MI*/2, /*Op*/1, /*Type*/GILLT_s16,
        GIM_CheckType, /*MI*/2, /*Op*/2, /*Type*/GILLT_s16,
        GIM_RecordInsn, /*DefineMI*/3, /*MI*/0, /*OpIdx*/2, // MIs[3]
        GIM_CheckOpcode, /*MI*/3, GIMT_Encode2(TargetOpcode::G_FMINNUM),
        // MIs[3] VOP3Mods:src0:src0_mods
        GIM_CheckIsSameOperand, /*MI*/3, /*OpIdx*/1, /*OtherMI*/2, /*OtherOpIdx*/2,
        // MIs[3] VOP3Mods:src1:src1_mods
        GIM_CheckIsSameOperand, /*MI*/3, /*OpIdx*/2, /*OtherMI*/2, /*OtherOpIdx*/1,
        GIM_CheckCxxInsnPredicate, /*MI*/0, /*FnId*/GIMT_Encode2(GICXXPred_MI_Predicate_fmaxnum_like_nnan),
        GIM_CheckIsSafeToFold, /*InsnID*/1,
        GIM_CheckIsSafeToFold, /*InsnID*/2,
        GIM_CheckIsSafeToFold, /*InsnID*/3,
        GIM_CheckComplexPattern, /*MI*/1, /*Op*/1, /*Renderer*/GIMT_Encode2(0), GIMT_Encode2(GICP_gi_vop3mods),
        GIM_CheckComplexPattern, /*MI*/2, /*Op*/1, /*Renderer*/GIMT_Encode2(1), GIMT_Encode2(GICP_gi_vop3mods),
        GIM_CheckComplexPattern, /*MI*/2, /*Op*/2, /*Renderer*/GIMT_Encode2(2), GIMT_Encode2(GICP_gi_vop3mods),
        // (fmaxnum_ieee:{ *:[f16] } (fminnum:{ *:[f16] } (VOP3Mods:{ *:[f16] } f16:{ *:[f16] }:$src2, i32:{ *:[i32] }:$src2_mods), (fmaxnum_ieee:{ *:[f16] } (VOP3Mods:{ *:[f16] } f16:{ *:[f16] }:$src1, i32:{ *:[i32] }:$src1_mods), (VOP3Mods:{ *:[f16] } f16:{ *:[f16] }:$src0, i32:{ *:[i32] }:$src0_mods))), (fminnum:{ *:[f16] } (VOP3Mods:{ *:[f16] } f16:{ *:[f16] }:$src0, i32:{ *:[i32] }:$src0_mods), (VOP3Mods:{ *:[f16] } f16:{ *:[f16] }:$src1, i32:{ *:[i32] }:$src1_mods)))<<P:Predicate_fmaxnum_like_nnan>>  =>  (V_MED3_F16_e64:{ *:[f16] } ?:{ *:[i32] }:$src0_mods, ?:{ *:[f16] }:$src0, ?:{ *:[i32] }:$src1_mods, ?:{ *:[f16] }:$src1, ?:{ *:[i32] }:$src2_mods, ?:{ *:[f16] }:$src2, 0:{ *:[i1] })
        GIR_BuildMI, /*InsnID*/0, /*Opcode*/GIMT_Encode2(AMDGPU::V_MED3_F16_e64),
        GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/0, // DstI[vdst]
        GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(2), /*SubOperand*/1, // src0_mods
        GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(2), /*SubOperand*/0, // src0
        GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(1), /*SubOperand*/1, // src1_mods
        GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(1), /*SubOperand*/0, // src1
        GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/1, // src2_mods
        GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/0, // src2
        GIR_AddImm8, /*InsnID*/0, /*Imm*/0,
        GIR_AddImm8, /*InsnID*/0, /*Imm*/0,
        GIR_AddImm8, /*InsnID*/0, /*Imm*/0,
        GIR_ConstrainSelectedInstOperands, /*InsnID*/0,
        GIR_EraseFromParent, /*InsnID*/0,
        // GIR_Coverage, 10633,
        GIR_Done,
      // Label 4960: @352712
      GIM_Try, /*On fail goto*//*Label 4961*/ GIMT_Encode4(352858), // Rule ID 10634 //
        GIM_CheckFeatures, GIMT_Encode2(GIFBS_isGFX9Plus),
        GIM_CheckRegBankForClass, /*MI*/0, /*Op*/0, /*RC*/GIMT_Encode2(AMDGPU::VGPR_32RegClassID),
        GIM_RecordInsn, /*DefineMI*/1, /*MI*/0, /*OpIdx*/1, // MIs[1]
        GIM_CheckOpcode, /*MI*/1, GIMT_Encode2(TargetOpcode::G_FMINNUM),
        GIM_CheckType, /*MI*/1, /*Op*/1, /*Type*/GILLT_s16,
        GIM_CheckType, /*MI*/1, /*Op*/2, /*Type*/GILLT_s16,
        GIM_RecordInsn, /*DefineMI*/2, /*MI*/1, /*OpIdx*/2, // MIs[2]
        GIM_CheckOpcode, /*MI*/2, GIMT_Encode2(TargetOpcode::G_FMAXNUM_IEEE),
        GIM_CheckType, /*MI*/2, /*Op*/1, /*Type*/GILLT_s16,
        GIM_CheckType, /*MI*/2, /*Op*/2, /*Type*/GILLT_s16,
        GIM_RecordInsn, /*DefineMI*/3, /*MI*/0, /*OpIdx*/2, // MIs[3]
        GIM_CheckOpcode, /*MI*/3, GIMT_Encode2(TargetOpcode::G_FMINNUM),
        // MIs[3] VOP3Mods:src1:src1_mods
        GIM_CheckIsSameOperand, /*MI*/3, /*OpIdx*/1, /*OtherMI*/2, /*OtherOpIdx*/1,
        // MIs[3] VOP3Mods:src0:src0_mods
        GIM_CheckIsSameOperand, /*MI*/3, /*OpIdx*/2, /*OtherMI*/2, /*OtherOpIdx*/2,
        GIM_CheckCxxInsnPredicate, /*MI*/0, /*FnId*/GIMT_Encode2(GICXXPred_MI_Predicate_fmaxnum_like_nnan),
        GIM_CheckIsSafeToFold, /*InsnID*/1,
        GIM_CheckIsSafeToFold, /*InsnID*/2,
        GIM_CheckIsSafeToFold, /*InsnID*/3,
        GIM_CheckComplexPattern, /*MI*/1, /*Op*/1, /*Renderer*/GIMT_Encode2(0), GIMT_Encode2(GICP_gi_vop3mods),
        GIM_CheckComplexPattern, /*MI*/2, /*Op*/1, /*Renderer*/GIMT_Encode2(1), GIMT_Encode2(GICP_gi_vop3mods),
        GIM_CheckComplexPattern, /*MI*/2, /*Op*/2, /*Renderer*/GIMT_Encode2(2), GIMT_Encode2(GICP_gi_vop3mods),
        // (fmaxnum_ieee:{ *:[f16] } (fminnum:{ *:[f16] } (VOP3Mods:{ *:[f16] } f16:{ *:[f16] }:$src2, i32:{ *:[i32] }:$src2_mods), (fmaxnum_ieee:{ *:[f16] } (VOP3Mods:{ *:[f16] } f16:{ *:[f16] }:$src1, i32:{ *:[i32] }:$src1_mods), (VOP3Mods:{ *:[f16] } f16:{ *:[f16] }:$src0, i32:{ *:[i32] }:$src0_mods))), (fminnum:{ *:[f16] } (VOP3Mods:{ *:[f16] } f16:{ *:[f16] }:$src1, i32:{ *:[i32] }:$src1_mods), (VOP3Mods:{ *:[f16] } f16:{ *:[f16] }:$src0, i32:{ *:[i32] }:$src0_mods)))<<P:Predicate_fmaxnum_like_nnan>>  =>  (V_MED3_F16_e64:{ *:[f16] } ?:{ *:[i32] }:$src0_mods, ?:{ *:[f16] }:$src0, ?:{ *:[i32] }:$src1_mods, ?:{ *:[f16] }:$src1, ?:{ *:[i32] }:$src2_mods, ?:{ *:[f16] }:$src2, 0:{ *:[i1] })
        GIR_BuildMI, /*InsnID*/0, /*Opcode*/GIMT_Encode2(AMDGPU::V_MED3_F16_e64),
        GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/0, // DstI[vdst]
        GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(2), /*SubOperand*/1, // src0_mods
        GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(2), /*SubOperand*/0, // src0
        GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(1), /*SubOperand*/1, // src1_mods
        GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(1), /*SubOperand*/0, // src1
        GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/1, // src2_mods
        GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/0, // src2
        GIR_AddImm8, /*InsnID*/0, /*Imm*/0,
        GIR_AddImm8, /*InsnID*/0, /*Imm*/0,
        GIR_AddImm8, /*InsnID*/0, /*Imm*/0,
        GIR_ConstrainSelectedInstOperands, /*InsnID*/0,
        GIR_EraseFromParent, /*InsnID*/0,
        // GIR_Coverage, 10634,
        GIR_Done,
      // Label 4961: @352858
      GIM_Try, /*On fail goto*//*Label 4962*/ GIMT_Encode4(353004), // Rule ID 10571 //
        GIM_CheckFeatures, GIMT_Encode2(GIFBS_isGFX9Plus),
        GIM_CheckRegBankForClass, /*MI*/0, /*Op*/0, /*RC*/GIMT_Encode2(AMDGPU::VGPR_32RegClassID),
        GIM_RecordInsn, /*DefineMI*/1, /*MI*/0, /*OpIdx*/1, // MIs[1]
        GIM_CheckOpcode, /*MI*/1, GIMT_Encode2(TargetOpcode::G_FMINNUM),
        GIM_CheckType, /*MI*/1, /*Op*/1, /*Type*/GILLT_s16,
        GIM_CheckType, /*MI*/1, /*Op*/2, /*Type*/GILLT_s16,
        GIM_RecordInsn, /*DefineMI*/2, /*MI*/1, /*OpIdx*/2, // MIs[2]
        GIM_CheckOpcode, /*MI*/2, GIMT_Encode2(TargetOpcode::G_FMAXNUM_IEEE),
        GIM_CheckType, /*MI*/2, /*Op*/1, /*Type*/GILLT_s16,
        GIM_CheckType, /*MI*/2, /*Op*/2, /*Type*/GILLT_s16,
        GIM_RecordInsn, /*DefineMI*/3, /*MI*/0, /*OpIdx*/2, // MIs[3]
        GIM_CheckOpcode, /*MI*/3, GIMT_Encode2(TargetOpcode::G_FMINNUM_IEEE),
        // MIs[3] VOP3Mods:src0:src0_mods
        GIM_CheckIsSameOperand, /*MI*/3, /*OpIdx*/1, /*OtherMI*/2, /*OtherOpIdx*/1,
        // MIs[3] VOP3Mods:src1:src1_mods
        GIM_CheckIsSameOperand, /*MI*/3, /*OpIdx*/2, /*OtherMI*/2, /*OtherOpIdx*/2,
        GIM_CheckCxxInsnPredicate, /*MI*/0, /*FnId*/GIMT_Encode2(GICXXPred_MI_Predicate_fmaxnum_like_nnan),
        GIM_CheckIsSafeToFold, /*InsnID*/1,
        GIM_CheckIsSafeToFold, /*InsnID*/2,
        GIM_CheckIsSafeToFold, /*InsnID*/3,
        GIM_CheckComplexPattern, /*MI*/1, /*Op*/1, /*Renderer*/GIMT_Encode2(0), GIMT_Encode2(GICP_gi_vop3mods),
        GIM_CheckComplexPattern, /*MI*/2, /*Op*/1, /*Renderer*/GIMT_Encode2(1), GIMT_Encode2(GICP_gi_vop3mods),
        GIM_CheckComplexPattern, /*MI*/2, /*Op*/2, /*Renderer*/GIMT_Encode2(2), GIMT_Encode2(GICP_gi_vop3mods),
        // (fmaxnum_ieee:{ *:[f16] } (fminnum:{ *:[f16] } (VOP3Mods:{ *:[f16] } f16:{ *:[f16] }:$src2, i32:{ *:[i32] }:$src2_mods), (fmaxnum_ieee:{ *:[f16] } (VOP3Mods:{ *:[f16] } f16:{ *:[f16] }:$src0, i32:{ *:[i32] }:$src0_mods), (VOP3Mods:{ *:[f16] } f16:{ *:[f16] }:$src1, i32:{ *:[i32] }:$src1_mods))), (fminnum_ieee:{ *:[f16] } (VOP3Mods:{ *:[f16] } f16:{ *:[f16] }:$src0, i32:{ *:[i32] }:$src0_mods), (VOP3Mods:{ *:[f16] } f16:{ *:[f16] }:$src1, i32:{ *:[i32] }:$src1_mods)))<<P:Predicate_fmaxnum_like_nnan>>  =>  (V_MED3_F16_e64:{ *:[f16] } ?:{ *:[i32] }:$src0_mods, ?:{ *:[f16] }:$src0, ?:{ *:[i32] }:$src1_mods, ?:{ *:[f16] }:$src1, ?:{ *:[i32] }:$src2_mods, ?:{ *:[f16] }:$src2, 0:{ *:[i1] })
        GIR_BuildMI, /*InsnID*/0, /*Opcode*/GIMT_Encode2(AMDGPU::V_MED3_F16_e64),
        GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/0, // DstI[vdst]
        GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(1), /*SubOperand*/1, // src0_mods
        GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(1), /*SubOperand*/0, // src0
        GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(2), /*SubOperand*/1, // src1_mods
        GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(2), /*SubOperand*/0, // src1
        GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/1, // src2_mods
        GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/0, // src2
        GIR_AddImm8, /*InsnID*/0, /*Imm*/0,
        GIR_AddImm8, /*InsnID*/0, /*Imm*/0,
        GIR_AddImm8, /*InsnID*/0, /*Imm*/0,
        GIR_ConstrainSelectedInstOperands, /*InsnID*/0,
        GIR_EraseFromParent, /*InsnID*/0,
        // GIR_Coverage, 10571,
        GIR_Done,
      // Label 4962: @353004
      GIM_Try, /*On fail goto*//*Label 4963*/ GIMT_Encode4(353150), // Rule ID 10572 //
        GIM_CheckFeatures, GIMT_Encode2(GIFBS_isGFX9Plus),
        GIM_CheckRegBankForClass, /*MI*/0, /*Op*/0, /*RC*/GIMT_Encode2(AMDGPU::VGPR_32RegClassID),
        GIM_RecordInsn, /*DefineMI*/1, /*MI*/0, /*OpIdx*/1, // MIs[1]
        GIM_CheckOpcode, /*MI*/1, GIMT_Encode2(TargetOpcode::G_FMINNUM),
        GIM_CheckType, /*MI*/1, /*Op*/1, /*Type*/GILLT_s16,
        GIM_CheckType, /*MI*/1, /*Op*/2, /*Type*/GILLT_s16,
        GIM_RecordInsn, /*DefineMI*/2, /*MI*/1, /*OpIdx*/2, // MIs[2]
        GIM_CheckOpcode, /*MI*/2, GIMT_Encode2(TargetOpcode::G_FMAXNUM_IEEE),
        GIM_CheckType, /*MI*/2, /*Op*/1, /*Type*/GILLT_s16,
        GIM_CheckType, /*MI*/2, /*Op*/2, /*Type*/GILLT_s16,
        GIM_RecordInsn, /*DefineMI*/3, /*MI*/0, /*OpIdx*/2, // MIs[3]
        GIM_CheckOpcode, /*MI*/3, GIMT_Encode2(TargetOpcode::G_FMINNUM_IEEE),
        // MIs[3] VOP3Mods:src1:src1_mods
        GIM_CheckIsSameOperand, /*MI*/3, /*OpIdx*/1, /*OtherMI*/2, /*OtherOpIdx*/2,
        // MIs[3] VOP3Mods:src0:src0_mods
        GIM_CheckIsSameOperand, /*MI*/3, /*OpIdx*/2, /*OtherMI*/2, /*OtherOpIdx*/1,
        GIM_CheckCxxInsnPredicate, /*MI*/0, /*FnId*/GIMT_Encode2(GICXXPred_MI_Predicate_fmaxnum_like_nnan),
        GIM_CheckIsSafeToFold, /*InsnID*/1,
        GIM_CheckIsSafeToFold, /*InsnID*/2,
        GIM_CheckIsSafeToFold, /*InsnID*/3,
        GIM_CheckComplexPattern, /*MI*/1, /*Op*/1, /*Renderer*/GIMT_Encode2(0), GIMT_Encode2(GICP_gi_vop3mods),
        GIM_CheckComplexPattern, /*MI*/2, /*Op*/1, /*Renderer*/GIMT_Encode2(1), GIMT_Encode2(GICP_gi_vop3mods),
        GIM_CheckComplexPattern, /*MI*/2, /*Op*/2, /*Renderer*/GIMT_Encode2(2), GIMT_Encode2(GICP_gi_vop3mods),
        // (fmaxnum_ieee:{ *:[f16] } (fminnum:{ *:[f16] } (VOP3Mods:{ *:[f16] } f16:{ *:[f16] }:$src2, i32:{ *:[i32] }:$src2_mods), (fmaxnum_ieee:{ *:[f16] } (VOP3Mods:{ *:[f16] } f16:{ *:[f16] }:$src0, i32:{ *:[i32] }:$src0_mods), (VOP3Mods:{ *:[f16] } f16:{ *:[f16] }:$src1, i32:{ *:[i32] }:$src1_mods))), (fminnum_ieee:{ *:[f16] } (VOP3Mods:{ *:[f16] } f16:{ *:[f16] }:$src1, i32:{ *:[i32] }:$src1_mods), (VOP3Mods:{ *:[f16] } f16:{ *:[f16] }:$src0, i32:{ *:[i32] }:$src0_mods)))<<P:Predicate_fmaxnum_like_nnan>>  =>  (V_MED3_F16_e64:{ *:[f16] } ?:{ *:[i32] }:$src0_mods, ?:{ *:[f16] }:$src0, ?:{ *:[i32] }:$src1_mods, ?:{ *:[f16] }:$src1, ?:{ *:[i32] }:$src2_mods, ?:{ *:[f16] }:$src2, 0:{ *:[i1] })
        GIR_BuildMI, /*InsnID*/0, /*Opcode*/GIMT_Encode2(AMDGPU::V_MED3_F16_e64),
        GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/0, // DstI[vdst]
        GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(1), /*SubOperand*/1, // src0_mods
        GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(1), /*SubOperand*/0, // src0
        GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(2), /*SubOperand*/1, // src1_mods
        GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(2), /*SubOperand*/0, // src1
        GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/1, // src2_mods
        GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/0, // src2
        GIR_AddImm8, /*InsnID*/0, /*Imm*/0,
        GIR_AddImm8, /*InsnID*/0, /*Imm*/0,
        GIR_AddImm8, /*InsnID*/0, /*Imm*/0,
        GIR_ConstrainSelectedInstOperands, /*InsnID*/0,
        GIR_EraseFromParent, /*InsnID*/0,
        // GIR_Coverage, 10572,
        GIR_Done,
      // Label 4963: @353150
      GIM_Try, /*On fail goto*//*Label 4964*/ GIMT_Encode4(353296), // Rule ID 10573 //
        GIM_CheckFeatures, GIMT_Encode2(GIFBS_isGFX9Plus),
        GIM_CheckRegBankForClass, /*MI*/0, /*Op*/0, /*RC*/GIMT_Encode2(AMDGPU::VGPR_32RegClassID),
        GIM_RecordInsn, /*DefineMI*/1, /*MI*/0, /*OpIdx*/1, // MIs[1]
        GIM_CheckOpcode, /*MI*/1, GIMT_Encode2(TargetOpcode::G_FMINNUM),
        GIM_CheckType, /*MI*/1, /*Op*/1, /*Type*/GILLT_s16,
        GIM_CheckType, /*MI*/1, /*Op*/2, /*Type*/GILLT_s16,
        GIM_RecordInsn, /*DefineMI*/2, /*MI*/1, /*OpIdx*/2, // MIs[2]
        GIM_CheckOpcode, /*MI*/2, GIMT_Encode2(TargetOpcode::G_FMAXNUM_IEEE),
        GIM_CheckType, /*MI*/2, /*Op*/1, /*Type*/GILLT_s16,
        GIM_CheckType, /*MI*/2, /*Op*/2, /*Type*/GILLT_s16,
        GIM_RecordInsn, /*DefineMI*/3, /*MI*/0, /*OpIdx*/2, // MIs[3]
        GIM_CheckOpcode, /*MI*/3, GIMT_Encode2(TargetOpcode::G_FMINNUM_IEEE),
        // MIs[3] VOP3Mods:src0:src0_mods
        GIM_CheckIsSameOperand, /*MI*/3, /*OpIdx*/1, /*OtherMI*/2, /*OtherOpIdx*/2,
        // MIs[3] VOP3Mods:src1:src1_mods
        GIM_CheckIsSameOperand, /*MI*/3, /*OpIdx*/2, /*OtherMI*/2, /*OtherOpIdx*/1,
        GIM_CheckCxxInsnPredicate, /*MI*/0, /*FnId*/GIMT_Encode2(GICXXPred_MI_Predicate_fmaxnum_like_nnan),
        GIM_CheckIsSafeToFold, /*InsnID*/1,
        GIM_CheckIsSafeToFold, /*InsnID*/2,
        GIM_CheckIsSafeToFold, /*InsnID*/3,
        GIM_CheckComplexPattern, /*MI*/1, /*Op*/1, /*Renderer*/GIMT_Encode2(0), GIMT_Encode2(GICP_gi_vop3mods),
        GIM_CheckComplexPattern, /*MI*/2, /*Op*/1, /*Renderer*/GIMT_Encode2(1), GIMT_Encode2(GICP_gi_vop3mods),
        GIM_CheckComplexPattern, /*MI*/2, /*Op*/2, /*Renderer*/GIMT_Encode2(2), GIMT_Encode2(GICP_gi_vop3mods),
        // (fmaxnum_ieee:{ *:[f16] } (fminnum:{ *:[f16] } (VOP3Mods:{ *:[f16] } f16:{ *:[f16] }:$src2, i32:{ *:[i32] }:$src2_mods), (fmaxnum_ieee:{ *:[f16] } (VOP3Mods:{ *:[f16] } f16:{ *:[f16] }:$src1, i32:{ *:[i32] }:$src1_mods), (VOP3Mods:{ *:[f16] } f16:{ *:[f16] }:$src0, i32:{ *:[i32] }:$src0_mods))), (fminnum_ieee:{ *:[f16] } (VOP3Mods:{ *:[f16] } f16:{ *:[f16] }:$src0, i32:{ *:[i32] }:$src0_mods), (VOP3Mods:{ *:[f16] } f16:{ *:[f16] }:$src1, i32:{ *:[i32] }:$src1_mods)))<<P:Predicate_fmaxnum_like_nnan>>  =>  (V_MED3_F16_e64:{ *:[f16] } ?:{ *:[i32] }:$src0_mods, ?:{ *:[f16] }:$src0, ?:{ *:[i32] }:$src1_mods, ?:{ *:[f16] }:$src1, ?:{ *:[i32] }:$src2_mods, ?:{ *:[f16] }:$src2, 0:{ *:[i1] })
        GIR_BuildMI, /*InsnID*/0, /*Opcode*/GIMT_Encode2(AMDGPU::V_MED3_F16_e64),
        GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/0, // DstI[vdst]
        GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(2), /*SubOperand*/1, // src0_mods
        GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(2), /*SubOperand*/0, // src0
        GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(1), /*SubOperand*/1, // src1_mods
        GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(1), /*SubOperand*/0, // src1
        GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/1, // src2_mods
        GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/0, // src2
        GIR_AddImm8, /*InsnID*/0, /*Imm*/0,
        GIR_AddImm8, /*InsnID*/0, /*Imm*/0,
        GIR_AddImm8, /*InsnID*/0, /*Imm*/0,
        GIR_ConstrainSelectedInstOperands, /*InsnID*/0,
        GIR_EraseFromParent, /*InsnID*/0,
        // GIR_Coverage, 10573,
        GIR_Done,
      // Label 4964: @353296
      GIM_Try, /*On fail goto*//*Label 4965*/ GIMT_Encode4(353442), // Rule ID 10574 //
        GIM_CheckFeatures, GIMT_Encode2(GIFBS_isGFX9Plus),
        GIM_CheckRegBankForClass, /*MI*/0, /*Op*/0, /*RC*/GIMT_Encode2(AMDGPU::VGPR_32RegClassID),
        GIM_RecordInsn, /*DefineMI*/1, /*MI*/0, /*OpIdx*/1, // MIs[1]
        GIM_CheckOpcode, /*MI*/1, GIMT_Encode2(TargetOpcode::G_FMINNUM),
        GIM_CheckType, /*MI*/1, /*Op*/1, /*Type*/GILLT_s16,
        GIM_CheckType, /*MI*/1, /*Op*/2, /*Type*/GILLT_s16,
        GIM_RecordInsn, /*DefineMI*/2, /*MI*/1, /*OpIdx*/2, // MIs[2]
        GIM_CheckOpcode, /*MI*/2, GIMT_Encode2(TargetOpcode::G_FMAXNUM_IEEE),
        GIM_CheckType, /*MI*/2, /*Op*/1, /*Type*/GILLT_s16,
        GIM_CheckType, /*MI*/2, /*Op*/2, /*Type*/GILLT_s16,
        GIM_RecordInsn, /*DefineMI*/3, /*MI*/0, /*OpIdx*/2, // MIs[3]
        GIM_CheckOpcode, /*MI*/3, GIMT_Encode2(TargetOpcode::G_FMINNUM_IEEE),
        // MIs[3] VOP3Mods:src1:src1_mods
        GIM_CheckIsSameOperand, /*MI*/3, /*OpIdx*/1, /*OtherMI*/2, /*OtherOpIdx*/1,
        // MIs[3] VOP3Mods:src0:src0_mods
        GIM_CheckIsSameOperand, /*MI*/3, /*OpIdx*/2, /*OtherMI*/2, /*OtherOpIdx*/2,
        GIM_CheckCxxInsnPredicate, /*MI*/0, /*FnId*/GIMT_Encode2(GICXXPred_MI_Predicate_fmaxnum_like_nnan),
        GIM_CheckIsSafeToFold, /*InsnID*/1,
        GIM_CheckIsSafeToFold, /*InsnID*/2,
        GIM_CheckIsSafeToFold, /*InsnID*/3,
        GIM_CheckComplexPattern, /*MI*/1, /*Op*/1, /*Renderer*/GIMT_Encode2(0), GIMT_Encode2(GICP_gi_vop3mods),
        GIM_CheckComplexPattern, /*MI*/2, /*Op*/1, /*Renderer*/GIMT_Encode2(1), GIMT_Encode2(GICP_gi_vop3mods),
        GIM_CheckComplexPattern, /*MI*/2, /*Op*/2, /*Renderer*/GIMT_Encode2(2), GIMT_Encode2(GICP_gi_vop3mods),
        // (fmaxnum_ieee:{ *:[f16] } (fminnum:{ *:[f16] } (VOP3Mods:{ *:[f16] } f16:{ *:[f16] }:$src2, i32:{ *:[i32] }:$src2_mods), (fmaxnum_ieee:{ *:[f16] } (VOP3Mods:{ *:[f16] } f16:{ *:[f16] }:$src1, i32:{ *:[i32] }:$src1_mods), (VOP3Mods:{ *:[f16] } f16:{ *:[f16] }:$src0, i32:{ *:[i32] }:$src0_mods))), (fminnum_ieee:{ *:[f16] } (VOP3Mods:{ *:[f16] } f16:{ *:[f16] }:$src1, i32:{ *:[i32] }:$src1_mods), (VOP3Mods:{ *:[f16] } f16:{ *:[f16] }:$src0, i32:{ *:[i32] }:$src0_mods)))<<P:Predicate_fmaxnum_like_nnan>>  =>  (V_MED3_F16_e64:{ *:[f16] } ?:{ *:[i32] }:$src0_mods, ?:{ *:[f16] }:$src0, ?:{ *:[i32] }:$src1_mods, ?:{ *:[f16] }:$src1, ?:{ *:[i32] }:$src2_mods, ?:{ *:[f16] }:$src2, 0:{ *:[i1] })
        GIR_BuildMI, /*InsnID*/0, /*Opcode*/GIMT_Encode2(AMDGPU::V_MED3_F16_e64),
        GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/0, // DstI[vdst]
        GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(2), /*SubOperand*/1, // src0_mods
        GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(2), /*SubOperand*/0, // src0
        GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(1), /*SubOperand*/1, // src1_mods
        GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(1), /*SubOperand*/0, // src1
        GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/1, // src2_mods
        GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/0, // src2
        GIR_AddImm8, /*InsnID*/0, /*Imm*/0,
        GIR_AddImm8, /*InsnID*/0, /*Imm*/0,
        GIR_AddImm8, /*InsnID*/0, /*Imm*/0,
        GIR_ConstrainSelectedInstOperands, /*InsnID*/0,
        GIR_EraseFromParent, /*InsnID*/0,
        // GIR_Coverage, 10574,
        GIR_Done,
      // Label 4965: @353442
      GIM_Try, /*On fail goto*//*Label 4966*/ GIMT_Encode4(353588), // Rule ID 10642 //
        GIM_CheckFeatures, GIMT_Encode2(GIFBS_isGFX9Plus),
        GIM_CheckRegBankForClass, /*MI*/0, /*Op*/0, /*RC*/GIMT_Encode2(AMDGPU::VGPR_32RegClassID),
        GIM_RecordInsn, /*DefineMI*/1, /*MI*/0, /*OpIdx*/1, // MIs[1]
        GIM_CheckOpcode, /*MI*/1, GIMT_Encode2(TargetOpcode::G_FMINNUM),
        GIM_CheckType, /*MI*/1, /*Op*/1, /*Type*/GILLT_s16,
        GIM_CheckType, /*MI*/1, /*Op*/2, /*Type*/GILLT_s16,
        GIM_RecordInsn, /*DefineMI*/2, /*MI*/1, /*OpIdx*/1, // MIs[2]
        GIM_CheckOpcode, /*MI*/2, GIMT_Encode2(TargetOpcode::G_FMAXNUM),
        GIM_CheckType, /*MI*/2, /*Op*/1, /*Type*/GILLT_s16,
        GIM_CheckType, /*MI*/2, /*Op*/2, /*Type*/GILLT_s16,
        GIM_RecordInsn, /*DefineMI*/3, /*MI*/0, /*OpIdx*/2, // MIs[3]
        GIM_CheckOpcode, /*MI*/3, GIMT_Encode2(TargetOpcode::G_FMINNUM),
        // MIs[3] VOP3Mods:src0:src0_mods
        GIM_CheckIsSameOperand, /*MI*/3, /*OpIdx*/1, /*OtherMI*/2, /*OtherOpIdx*/1,
        // MIs[3] VOP3Mods:src1:src1_mods
        GIM_CheckIsSameOperand, /*MI*/3, /*OpIdx*/2, /*OtherMI*/2, /*OtherOpIdx*/2,
        GIM_CheckCxxInsnPredicate, /*MI*/0, /*FnId*/GIMT_Encode2(GICXXPred_MI_Predicate_fmaxnum_like_nnan),
        GIM_CheckIsSafeToFold, /*InsnID*/1,
        GIM_CheckIsSafeToFold, /*InsnID*/2,
        GIM_CheckIsSafeToFold, /*InsnID*/3,
        GIM_CheckComplexPattern, /*MI*/1, /*Op*/2, /*Renderer*/GIMT_Encode2(2), GIMT_Encode2(GICP_gi_vop3mods),
        GIM_CheckComplexPattern, /*MI*/2, /*Op*/1, /*Renderer*/GIMT_Encode2(0), GIMT_Encode2(GICP_gi_vop3mods),
        GIM_CheckComplexPattern, /*MI*/2, /*Op*/2, /*Renderer*/GIMT_Encode2(1), GIMT_Encode2(GICP_gi_vop3mods),
        // (fmaxnum_ieee:{ *:[f16] } (fminnum:{ *:[f16] } (fmaxnum:{ *:[f16] } (VOP3Mods:{ *:[f16] } f16:{ *:[f16] }:$src0, i32:{ *:[i32] }:$src0_mods), (VOP3Mods:{ *:[f16] } f16:{ *:[f16] }:$src1, i32:{ *:[i32] }:$src1_mods)), (VOP3Mods:{ *:[f16] } f16:{ *:[f16] }:$src2, i32:{ *:[i32] }:$src2_mods)), (fminnum:{ *:[f16] } (VOP3Mods:{ *:[f16] } f16:{ *:[f16] }:$src0, i32:{ *:[i32] }:$src0_mods), (VOP3Mods:{ *:[f16] } f16:{ *:[f16] }:$src1, i32:{ *:[i32] }:$src1_mods)))<<P:Predicate_fmaxnum_like_nnan>>  =>  (V_MED3_F16_e64:{ *:[f16] } ?:{ *:[i32] }:$src0_mods, ?:{ *:[f16] }:$src0, ?:{ *:[i32] }:$src1_mods, ?:{ *:[f16] }:$src1, ?:{ *:[i32] }:$src2_mods, ?:{ *:[f16] }:$src2, 0:{ *:[i1] })
        GIR_BuildMI, /*InsnID*/0, /*Opcode*/GIMT_Encode2(AMDGPU::V_MED3_F16_e64),
        GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/0, // DstI[vdst]
        GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/1, // src0_mods
        GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/0, // src0
        GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(1), /*SubOperand*/1, // src1_mods
        GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(1), /*SubOperand*/0, // src1
        GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(2), /*SubOperand*/1, // src2_mods
        GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(2), /*SubOperand*/0, // src2
        GIR_AddImm8, /*InsnID*/0, /*Imm*/0,
        GIR_AddImm8, /*InsnID*/0, /*Imm*/0,
        GIR_AddImm8, /*InsnID*/0, /*Imm*/0,
        GIR_ConstrainSelectedInstOperands, /*InsnID*/0,
        GIR_EraseFromParent, /*InsnID*/0,
        // GIR_Coverage, 10642,
        GIR_Done,
      // Label 4966: @353588
      GIM_Try, /*On fail goto*//*Label 4967*/ GIMT_Encode4(353734), // Rule ID 10643 //
        GIM_CheckFeatures, GIMT_Encode2(GIFBS_isGFX9Plus),
        GIM_CheckRegBankForClass, /*MI*/0, /*Op*/0, /*RC*/GIMT_Encode2(AMDGPU::VGPR_32RegClassID),
        GIM_RecordInsn, /*DefineMI*/1, /*MI*/0, /*OpIdx*/1, // MIs[1]
        GIM_CheckOpcode, /*MI*/1, GIMT_Encode2(TargetOpcode::G_FMINNUM),
        GIM_CheckType, /*MI*/1, /*Op*/1, /*Type*/GILLT_s16,
        GIM_CheckType, /*MI*/1, /*Op*/2, /*Type*/GILLT_s16,
        GIM_RecordInsn, /*DefineMI*/2, /*MI*/1, /*OpIdx*/1, // MIs[2]
        GIM_CheckOpcode, /*MI*/2, GIMT_Encode2(TargetOpcode::G_FMAXNUM),
        GIM_CheckType, /*MI*/2, /*Op*/1, /*Type*/GILLT_s16,
        GIM_CheckType, /*MI*/2, /*Op*/2, /*Type*/GILLT_s16,
        GIM_RecordInsn, /*DefineMI*/3, /*MI*/0, /*OpIdx*/2, // MIs[3]
        GIM_CheckOpcode, /*MI*/3, GIMT_Encode2(TargetOpcode::G_FMINNUM),
        // MIs[3] VOP3Mods:src1:src1_mods
        GIM_CheckIsSameOperand, /*MI*/3, /*OpIdx*/1, /*OtherMI*/2, /*OtherOpIdx*/2,
        // MIs[3] VOP3Mods:src0:src0_mods
        GIM_CheckIsSameOperand, /*MI*/3, /*OpIdx*/2, /*OtherMI*/2, /*OtherOpIdx*/1,
        GIM_CheckCxxInsnPredicate, /*MI*/0, /*FnId*/GIMT_Encode2(GICXXPred_MI_Predicate_fmaxnum_like_nnan),
        GIM_CheckIsSafeToFold, /*InsnID*/1,
        GIM_CheckIsSafeToFold, /*InsnID*/2,
        GIM_CheckIsSafeToFold, /*InsnID*/3,
        GIM_CheckComplexPattern, /*MI*/1, /*Op*/2, /*Renderer*/GIMT_Encode2(2), GIMT_Encode2(GICP_gi_vop3mods),
        GIM_CheckComplexPattern, /*MI*/2, /*Op*/1, /*Renderer*/GIMT_Encode2(0), GIMT_Encode2(GICP_gi_vop3mods),
        GIM_CheckComplexPattern, /*MI*/2, /*Op*/2, /*Renderer*/GIMT_Encode2(1), GIMT_Encode2(GICP_gi_vop3mods),
        // (fmaxnum_ieee:{ *:[f16] } (fminnum:{ *:[f16] } (fmaxnum:{ *:[f16] } (VOP3Mods:{ *:[f16] } f16:{ *:[f16] }:$src0, i32:{ *:[i32] }:$src0_mods), (VOP3Mods:{ *:[f16] } f16:{ *:[f16] }:$src1, i32:{ *:[i32] }:$src1_mods)), (VOP3Mods:{ *:[f16] } f16:{ *:[f16] }:$src2, i32:{ *:[i32] }:$src2_mods)), (fminnum:{ *:[f16] } (VOP3Mods:{ *:[f16] } f16:{ *:[f16] }:$src1, i32:{ *:[i32] }:$src1_mods), (VOP3Mods:{ *:[f16] } f16:{ *:[f16] }:$src0, i32:{ *:[i32] }:$src0_mods)))<<P:Predicate_fmaxnum_like_nnan>>  =>  (V_MED3_F16_e64:{ *:[f16] } ?:{ *:[i32] }:$src0_mods, ?:{ *:[f16] }:$src0, ?:{ *:[i32] }:$src1_mods, ?:{ *:[f16] }:$src1, ?:{ *:[i32] }:$src2_mods, ?:{ *:[f16] }:$src2, 0:{ *:[i1] })
        GIR_BuildMI, /*InsnID*/0, /*Opcode*/GIMT_Encode2(AMDGPU::V_MED3_F16_e64),
        GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/0, // DstI[vdst]
        GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/1, // src0_mods
        GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/0, // src0
        GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(1), /*SubOperand*/1, // src1_mods
        GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(1), /*SubOperand*/0, // src1
        GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(2), /*SubOperand*/1, // src2_mods
        GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(2), /*SubOperand*/0, // src2
        GIR_AddImm8, /*InsnID*/0, /*Imm*/0,
        GIR_AddImm8, /*InsnID*/0, /*Imm*/0,
        GIR_AddImm8, /*InsnID*/0, /*Imm*/0,
        GIR_ConstrainSelectedInstOperands, /*InsnID*/0,
        GIR_EraseFromParent, /*InsnID*/0,
        // GIR_Coverage, 10643,
        GIR_Done,
      // Label 4967: @353734
      GIM_Try, /*On fail goto*//*Label 4968*/ GIMT_Encode4(353880), // Rule ID 10644 //
        GIM_CheckFeatures, GIMT_Encode2(GIFBS_isGFX9Plus),
        GIM_CheckRegBankForClass, /*MI*/0, /*Op*/0, /*RC*/GIMT_Encode2(AMDGPU::VGPR_32RegClassID),
        GIM_RecordInsn, /*DefineMI*/1, /*MI*/0, /*OpIdx*/1, // MIs[1]
        GIM_CheckOpcode, /*MI*/1, GIMT_Encode2(TargetOpcode::G_FMINNUM),
        GIM_CheckType, /*MI*/1, /*Op*/1, /*Type*/GILLT_s16,
        GIM_CheckType, /*MI*/1, /*Op*/2, /*Type*/GILLT_s16,
        GIM_RecordInsn, /*DefineMI*/2, /*MI*/1, /*OpIdx*/1, // MIs[2]
        GIM_CheckOpcode, /*MI*/2, GIMT_Encode2(TargetOpcode::G_FMAXNUM),
        GIM_CheckType, /*MI*/2, /*Op*/1, /*Type*/GILLT_s16,
        GIM_CheckType, /*MI*/2, /*Op*/2, /*Type*/GILLT_s16,
        GIM_RecordInsn, /*DefineMI*/3, /*MI*/0, /*OpIdx*/2, // MIs[3]
        GIM_CheckOpcode, /*MI*/3, GIMT_Encode2(TargetOpcode::G_FMINNUM),
        // MIs[3] VOP3Mods:src0:src0_mods
        GIM_CheckIsSameOperand, /*MI*/3, /*OpIdx*/1, /*OtherMI*/2, /*OtherOpIdx*/2,
        // MIs[3] VOP3Mods:src1:src1_mods
        GIM_CheckIsSameOperand, /*MI*/3, /*OpIdx*/2, /*OtherMI*/2, /*OtherOpIdx*/1,
        GIM_CheckCxxInsnPredicate, /*MI*/0, /*FnId*/GIMT_Encode2(GICXXPred_MI_Predicate_fmaxnum_like_nnan),
        GIM_CheckIsSafeToFold, /*InsnID*/1,
        GIM_CheckIsSafeToFold, /*InsnID*/2,
        GIM_CheckIsSafeToFold, /*InsnID*/3,
        GIM_CheckComplexPattern, /*MI*/1, /*Op*/2, /*Renderer*/GIMT_Encode2(2), GIMT_Encode2(GICP_gi_vop3mods),
        GIM_CheckComplexPattern, /*MI*/2, /*Op*/1, /*Renderer*/GIMT_Encode2(0), GIMT_Encode2(GICP_gi_vop3mods),
        GIM_CheckComplexPattern, /*MI*/2, /*Op*/2, /*Renderer*/GIMT_Encode2(1), GIMT_Encode2(GICP_gi_vop3mods),
        // (fmaxnum_ieee:{ *:[f16] } (fminnum:{ *:[f16] } (fmaxnum:{ *:[f16] } (VOP3Mods:{ *:[f16] } f16:{ *:[f16] }:$src1, i32:{ *:[i32] }:$src1_mods), (VOP3Mods:{ *:[f16] } f16:{ *:[f16] }:$src0, i32:{ *:[i32] }:$src0_mods)), (VOP3Mods:{ *:[f16] } f16:{ *:[f16] }:$src2, i32:{ *:[i32] }:$src2_mods)), (fminnum:{ *:[f16] } (VOP3Mods:{ *:[f16] } f16:{ *:[f16] }:$src0, i32:{ *:[i32] }:$src0_mods), (VOP3Mods:{ *:[f16] } f16:{ *:[f16] }:$src1, i32:{ *:[i32] }:$src1_mods)))<<P:Predicate_fmaxnum_like_nnan>>  =>  (V_MED3_F16_e64:{ *:[f16] } ?:{ *:[i32] }:$src0_mods, ?:{ *:[f16] }:$src0, ?:{ *:[i32] }:$src1_mods, ?:{ *:[f16] }:$src1, ?:{ *:[i32] }:$src2_mods, ?:{ *:[f16] }:$src2, 0:{ *:[i1] })
        GIR_BuildMI, /*InsnID*/0, /*Opcode*/GIMT_Encode2(AMDGPU::V_MED3_F16_e64),
        GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/0, // DstI[vdst]
        GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(1), /*SubOperand*/1, // src0_mods
        GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(1), /*SubOperand*/0, // src0
        GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/1, // src1_mods
        GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/0, // src1
        GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(2), /*SubOperand*/1, // src2_mods
        GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(2), /*SubOperand*/0, // src2
        GIR_AddImm8, /*InsnID*/0, /*Imm*/0,
        GIR_AddImm8, /*InsnID*/0, /*Imm*/0,
        GIR_AddImm8, /*InsnID*/0, /*Imm*/0,
        GIR_ConstrainSelectedInstOperands, /*InsnID*/0,
        GIR_EraseFromParent, /*InsnID*/0,
        // GIR_Coverage, 10644,
        GIR_Done,
      // Label 4968: @353880
      GIM_Try, /*On fail goto*//*Label 4969*/ GIMT_Encode4(354026), // Rule ID 10645 //
        GIM_CheckFeatures, GIMT_Encode2(GIFBS_isGFX9Plus),
        GIM_CheckRegBankForClass, /*MI*/0, /*Op*/0, /*RC*/GIMT_Encode2(AMDGPU::VGPR_32RegClassID),
        GIM_RecordInsn, /*DefineMI*/1, /*MI*/0, /*OpIdx*/1, // MIs[1]
        GIM_CheckOpcode, /*MI*/1, GIMT_Encode2(TargetOpcode::G_FMINNUM),
        GIM_CheckType, /*MI*/1, /*Op*/1, /*Type*/GILLT_s16,
        GIM_CheckType, /*MI*/1, /*Op*/2, /*Type*/GILLT_s16,
        GIM_RecordInsn, /*DefineMI*/2, /*MI*/1, /*OpIdx*/1, // MIs[2]
        GIM_CheckOpcode, /*MI*/2, GIMT_Encode2(TargetOpcode::G_FMAXNUM),
        GIM_CheckType, /*MI*/2, /*Op*/1, /*Type*/GILLT_s16,
        GIM_CheckType, /*MI*/2, /*Op*/2, /*Type*/GILLT_s16,
        GIM_RecordInsn, /*DefineMI*/3, /*MI*/0, /*OpIdx*/2, // MIs[3]
        GIM_CheckOpcode, /*MI*/3, GIMT_Encode2(TargetOpcode::G_FMINNUM),
        // MIs[3] VOP3Mods:src1:src1_mods
        GIM_CheckIsSameOperand, /*MI*/3, /*OpIdx*/1, /*OtherMI*/2, /*OtherOpIdx*/1,
        // MIs[3] VOP3Mods:src0:src0_mods
        GIM_CheckIsSameOperand, /*MI*/3, /*OpIdx*/2, /*OtherMI*/2, /*OtherOpIdx*/2,
        GIM_CheckCxxInsnPredicate, /*MI*/0, /*FnId*/GIMT_Encode2(GICXXPred_MI_Predicate_fmaxnum_like_nnan),
        GIM_CheckIsSafeToFold, /*InsnID*/1,
        GIM_CheckIsSafeToFold, /*InsnID*/2,
        GIM_CheckIsSafeToFold, /*InsnID*/3,
        GIM_CheckComplexPattern, /*MI*/1, /*Op*/2, /*Renderer*/GIMT_Encode2(2), GIMT_Encode2(GICP_gi_vop3mods),
        GIM_CheckComplexPattern, /*MI*/2, /*Op*/1, /*Renderer*/GIMT_Encode2(0), GIMT_Encode2(GICP_gi_vop3mods),
        GIM_CheckComplexPattern, /*MI*/2, /*Op*/2, /*Renderer*/GIMT_Encode2(1), GIMT_Encode2(GICP_gi_vop3mods),
        // (fmaxnum_ieee:{ *:[f16] } (fminnum:{ *:[f16] } (fmaxnum:{ *:[f16] } (VOP3Mods:{ *:[f16] } f16:{ *:[f16] }:$src1, i32:{ *:[i32] }:$src1_mods), (VOP3Mods:{ *:[f16] } f16:{ *:[f16] }:$src0, i32:{ *:[i32] }:$src0_mods)), (VOP3Mods:{ *:[f16] } f16:{ *:[f16] }:$src2, i32:{ *:[i32] }:$src2_mods)), (fminnum:{ *:[f16] } (VOP3Mods:{ *:[f16] } f16:{ *:[f16] }:$src1, i32:{ *:[i32] }:$src1_mods), (VOP3Mods:{ *:[f16] } f16:{ *:[f16] }:$src0, i32:{ *:[i32] }:$src0_mods)))<<P:Predicate_fmaxnum_like_nnan>>  =>  (V_MED3_F16_e64:{ *:[f16] } ?:{ *:[i32] }:$src0_mods, ?:{ *:[f16] }:$src0, ?:{ *:[i32] }:$src1_mods, ?:{ *:[f16] }:$src1, ?:{ *:[i32] }:$src2_mods, ?:{ *:[f16] }:$src2, 0:{ *:[i1] })
        GIR_BuildMI, /*InsnID*/0, /*Opcode*/GIMT_Encode2(AMDGPU::V_MED3_F16_e64),
        GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/0, // DstI[vdst]
        GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(1), /*SubOperand*/1, // src0_mods
        GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(1), /*SubOperand*/0, // src0
        GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/1, // src1_mods
        GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/0, // src1
        GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(2), /*SubOperand*/1, // src2_mods
        GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(2), /*SubOperand*/0, // src2
        GIR_AddImm8, /*InsnID*/0, /*Imm*/0,
        GIR_AddImm8, /*InsnID*/0, /*Imm*/0,
        GIR_AddImm8, /*InsnID*/0, /*Imm*/0,
        GIR_ConstrainSelectedInstOperands, /*InsnID*/0,
        GIR_EraseFromParent, /*InsnID*/0,
        // GIR_Coverage, 10645,
        GIR_Done,
      // Label 4969: @354026
      GIM_Try, /*On fail goto*//*Label 4970*/ GIMT_Encode4(354172), // Rule ID 10582 //
        GIM_CheckFeatures, GIMT_Encode2(GIFBS_isGFX9Plus),
        GIM_CheckRegBankForClass, /*MI*/0, /*Op*/0, /*RC*/GIMT_Encode2(AMDGPU::VGPR_32RegClassID),
        GIM_RecordInsn, /*DefineMI*/1, /*MI*/0, /*OpIdx*/1, // MIs[1]
        GIM_CheckOpcode, /*MI*/1, GIMT_Encode2(TargetOpcode::G_FMINNUM),
        GIM_CheckType, /*MI*/1, /*Op*/1, /*Type*/GILLT_s16,
        GIM_CheckType, /*MI*/1, /*Op*/2, /*Type*/GILLT_s16,
        GIM_RecordInsn, /*DefineMI*/2, /*MI*/1, /*OpIdx*/1, // MIs[2]
        GIM_CheckOpcode, /*MI*/2, GIMT_Encode2(TargetOpcode::G_FMAXNUM),
        GIM_CheckType, /*MI*/2, /*Op*/1, /*Type*/GILLT_s16,
        GIM_CheckType, /*MI*/2, /*Op*/2, /*Type*/GILLT_s16,
        GIM_RecordInsn, /*DefineMI*/3, /*MI*/0, /*OpIdx*/2, // MIs[3]
        GIM_CheckOpcode, /*MI*/3, GIMT_Encode2(TargetOpcode::G_FMINNUM_IEEE),
        // MIs[3] VOP3Mods:src0:src0_mods
        GIM_CheckIsSameOperand, /*MI*/3, /*OpIdx*/1, /*OtherMI*/2, /*OtherOpIdx*/1,
        // MIs[3] VOP3Mods:src1:src1_mods
        GIM_CheckIsSameOperand, /*MI*/3, /*OpIdx*/2, /*OtherMI*/2, /*OtherOpIdx*/2,
        GIM_CheckCxxInsnPredicate, /*MI*/0, /*FnId*/GIMT_Encode2(GICXXPred_MI_Predicate_fmaxnum_like_nnan),
        GIM_CheckIsSafeToFold, /*InsnID*/1,
        GIM_CheckIsSafeToFold, /*InsnID*/2,
        GIM_CheckIsSafeToFold, /*InsnID*/3,
        GIM_CheckComplexPattern, /*MI*/1, /*Op*/2, /*Renderer*/GIMT_Encode2(2), GIMT_Encode2(GICP_gi_vop3mods),
        GIM_CheckComplexPattern, /*MI*/2, /*Op*/1, /*Renderer*/GIMT_Encode2(0), GIMT_Encode2(GICP_gi_vop3mods),
        GIM_CheckComplexPattern, /*MI*/2, /*Op*/2, /*Renderer*/GIMT_Encode2(1), GIMT_Encode2(GICP_gi_vop3mods),
        // (fmaxnum_ieee:{ *:[f16] } (fminnum:{ *:[f16] } (fmaxnum:{ *:[f16] } (VOP3Mods:{ *:[f16] } f16:{ *:[f16] }:$src0, i32:{ *:[i32] }:$src0_mods), (VOP3Mods:{ *:[f16] } f16:{ *:[f16] }:$src1, i32:{ *:[i32] }:$src1_mods)), (VOP3Mods:{ *:[f16] } f16:{ *:[f16] }:$src2, i32:{ *:[i32] }:$src2_mods)), (fminnum_ieee:{ *:[f16] } (VOP3Mods:{ *:[f16] } f16:{ *:[f16] }:$src0, i32:{ *:[i32] }:$src0_mods), (VOP3Mods:{ *:[f16] } f16:{ *:[f16] }:$src1, i32:{ *:[i32] }:$src1_mods)))<<P:Predicate_fmaxnum_like_nnan>>  =>  (V_MED3_F16_e64:{ *:[f16] } ?:{ *:[i32] }:$src0_mods, ?:{ *:[f16] }:$src0, ?:{ *:[i32] }:$src1_mods, ?:{ *:[f16] }:$src1, ?:{ *:[i32] }:$src2_mods, ?:{ *:[f16] }:$src2, 0:{ *:[i1] })
        GIR_BuildMI, /*InsnID*/0, /*Opcode*/GIMT_Encode2(AMDGPU::V_MED3_F16_e64),
        GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/0, // DstI[vdst]
        GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/1, // src0_mods
        GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/0, // src0
        GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(1), /*SubOperand*/1, // src1_mods
        GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(1), /*SubOperand*/0, // src1
        GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(2), /*SubOperand*/1, // src2_mods
        GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(2), /*SubOperand*/0, // src2
        GIR_AddImm8, /*InsnID*/0, /*Imm*/0,
        GIR_AddImm8, /*InsnID*/0, /*Imm*/0,
        GIR_AddImm8, /*InsnID*/0, /*Imm*/0,
        GIR_ConstrainSelectedInstOperands, /*InsnID*/0,
        GIR_EraseFromParent, /*InsnID*/0,
        // GIR_Coverage, 10582,
        GIR_Done,
      // Label 4970: @354172
      GIM_Try, /*On fail goto*//*Label 4971*/ GIMT_Encode4(354318), // Rule ID 10583 //
        GIM_CheckFeatures, GIMT_Encode2(GIFBS_isGFX9Plus),
        GIM_CheckRegBankForClass, /*MI*/0, /*Op*/0, /*RC*/GIMT_Encode2(AMDGPU::VGPR_32RegClassID),
        GIM_RecordInsn, /*DefineMI*/1, /*MI*/0, /*OpIdx*/1, // MIs[1]
        GIM_CheckOpcode, /*MI*/1, GIMT_Encode2(TargetOpcode::G_FMINNUM),
        GIM_CheckType, /*MI*/1, /*Op*/1, /*Type*/GILLT_s16,
        GIM_CheckType, /*MI*/1, /*Op*/2, /*Type*/GILLT_s16,
        GIM_RecordInsn, /*DefineMI*/2, /*MI*/1, /*OpIdx*/1, // MIs[2]
        GIM_CheckOpcode, /*MI*/2, GIMT_Encode2(TargetOpcode::G_FMAXNUM),
        GIM_CheckType, /*MI*/2, /*Op*/1, /*Type*/GILLT_s16,
        GIM_CheckType, /*MI*/2, /*Op*/2, /*Type*/GILLT_s16,
        GIM_RecordInsn, /*DefineMI*/3, /*MI*/0, /*OpIdx*/2, // MIs[3]
        GIM_CheckOpcode, /*MI*/3, GIMT_Encode2(TargetOpcode::G_FMINNUM_IEEE),
        // MIs[3] VOP3Mods:src1:src1_mods
        GIM_CheckIsSameOperand, /*MI*/3, /*OpIdx*/1, /*OtherMI*/2, /*OtherOpIdx*/2,
        // MIs[3] VOP3Mods:src0:src0_mods
        GIM_CheckIsSameOperand, /*MI*/3, /*OpIdx*/2, /*OtherMI*/2, /*OtherOpIdx*/1,
        GIM_CheckCxxInsnPredicate, /*MI*/0, /*FnId*/GIMT_Encode2(GICXXPred_MI_Predicate_fmaxnum_like_nnan),
        GIM_CheckIsSafeToFold, /*InsnID*/1,
        GIM_CheckIsSafeToFold, /*InsnID*/2,
        GIM_CheckIsSafeToFold, /*InsnID*/3,
        GIM_CheckComplexPattern, /*MI*/1, /*Op*/2, /*Renderer*/GIMT_Encode2(2), GIMT_Encode2(GICP_gi_vop3mods),
        GIM_CheckComplexPattern, /*MI*/2, /*Op*/1, /*Renderer*/GIMT_Encode2(0), GIMT_Encode2(GICP_gi_vop3mods),
        GIM_CheckComplexPattern, /*MI*/2, /*Op*/2, /*Renderer*/GIMT_Encode2(1), GIMT_Encode2(GICP_gi_vop3mods),
        // (fmaxnum_ieee:{ *:[f16] } (fminnum:{ *:[f16] } (fmaxnum:{ *:[f16] } (VOP3Mods:{ *:[f16] } f16:{ *:[f16] }:$src0, i32:{ *:[i32] }:$src0_mods), (VOP3Mods:{ *:[f16] } f16:{ *:[f16] }:$src1, i32:{ *:[i32] }:$src1_mods)), (VOP3Mods:{ *:[f16] } f16:{ *:[f16] }:$src2, i32:{ *:[i32] }:$src2_mods)), (fminnum_ieee:{ *:[f16] } (VOP3Mods:{ *:[f16] } f16:{ *:[f16] }:$src1, i32:{ *:[i32] }:$src1_mods), (VOP3Mods:{ *:[f16] } f16:{ *:[f16] }:$src0, i32:{ *:[i32] }:$src0_mods)))<<P:Predicate_fmaxnum_like_nnan>>  =>  (V_MED3_F16_e64:{ *:[f16] } ?:{ *:[i32] }:$src0_mods, ?:{ *:[f16] }:$src0, ?:{ *:[i32] }:$src1_mods, ?:{ *:[f16] }:$src1, ?:{ *:[i32] }:$src2_mods, ?:{ *:[f16] }:$src2, 0:{ *:[i1] })
        GIR_BuildMI, /*InsnID*/0, /*Opcode*/GIMT_Encode2(AMDGPU::V_MED3_F16_e64),
        GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/0, // DstI[vdst]
        GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/1, // src0_mods
        GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/0, // src0
        GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(1), /*SubOperand*/1, // src1_mods
        GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(1), /*SubOperand*/0, // src1
        GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(2), /*SubOperand*/1, // src2_mods
        GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(2), /*SubOperand*/0, // src2
        GIR_AddImm8, /*InsnID*/0, /*Imm*/0,
        GIR_AddImm8, /*InsnID*/0, /*Imm*/0,
        GIR_AddImm8, /*InsnID*/0, /*Imm*/0,
        GIR_ConstrainSelectedInstOperands, /*InsnID*/0,
        GIR_EraseFromParent, /*InsnID*/0,
        // GIR_Coverage, 10583,
        GIR_Done,
      // Label 4971: @354318
      GIM_Try, /*On fail goto*//*Label 4972*/ GIMT_Encode4(354464), // Rule ID 10584 //
        GIM_CheckFeatures, GIMT_Encode2(GIFBS_isGFX9Plus),
        GIM_CheckRegBankForClass, /*MI*/0, /*Op*/0, /*RC*/GIMT_Encode2(AMDGPU::VGPR_32RegClassID),
        GIM_RecordInsn, /*DefineMI*/1, /*MI*/0, /*OpIdx*/1, // MIs[1]
        GIM_CheckOpcode, /*MI*/1, GIMT_Encode2(TargetOpcode::G_FMINNUM),
        GIM_CheckType, /*MI*/1, /*Op*/1, /*Type*/GILLT_s16,
        GIM_CheckType, /*MI*/1, /*Op*/2, /*Type*/GILLT_s16,
        GIM_RecordInsn, /*DefineMI*/2, /*MI*/1, /*OpIdx*/1, // MIs[2]
        GIM_CheckOpcode, /*MI*/2, GIMT_Encode2(TargetOpcode::G_FMAXNUM),
        GIM_CheckType, /*MI*/2, /*Op*/1, /*Type*/GILLT_s16,
        GIM_CheckType, /*MI*/2, /*Op*/2, /*Type*/GILLT_s16,
        GIM_RecordInsn, /*DefineMI*/3, /*MI*/0, /*OpIdx*/2, // MIs[3]
        GIM_CheckOpcode, /*MI*/3, GIMT_Encode2(TargetOpcode::G_FMINNUM_IEEE),
        // MIs[3] VOP3Mods:src0:src0_mods
        GIM_CheckIsSameOperand, /*MI*/3, /*OpIdx*/1, /*OtherMI*/2, /*OtherOpIdx*/2,
        // MIs[3] VOP3Mods:src1:src1_mods
        GIM_CheckIsSameOperand, /*MI*/3, /*OpIdx*/2, /*OtherMI*/2, /*OtherOpIdx*/1,
        GIM_CheckCxxInsnPredicate, /*MI*/0, /*FnId*/GIMT_Encode2(GICXXPred_MI_Predicate_fmaxnum_like_nnan),
        GIM_CheckIsSafeToFold, /*InsnID*/1,
        GIM_CheckIsSafeToFold, /*InsnID*/2,
        GIM_CheckIsSafeToFold, /*InsnID*/3,
        GIM_CheckComplexPattern, /*MI*/1, /*Op*/2, /*Renderer*/GIMT_Encode2(2), GIMT_Encode2(GICP_gi_vop3mods),
        GIM_CheckComplexPattern, /*MI*/2, /*Op*/1, /*Renderer*/GIMT_Encode2(0), GIMT_Encode2(GICP_gi_vop3mods),
        GIM_CheckComplexPattern, /*MI*/2, /*Op*/2, /*Renderer*/GIMT_Encode2(1), GIMT_Encode2(GICP_gi_vop3mods),
        // (fmaxnum_ieee:{ *:[f16] } (fminnum:{ *:[f16] } (fmaxnum:{ *:[f16] } (VOP3Mods:{ *:[f16] } f16:{ *:[f16] }:$src1, i32:{ *:[i32] }:$src1_mods), (VOP3Mods:{ *:[f16] } f16:{ *:[f16] }:$src0, i32:{ *:[i32] }:$src0_mods)), (VOP3Mods:{ *:[f16] } f16:{ *:[f16] }:$src2, i32:{ *:[i32] }:$src2_mods)), (fminnum_ieee:{ *:[f16] } (VOP3Mods:{ *:[f16] } f16:{ *:[f16] }:$src0, i32:{ *:[i32] }:$src0_mods), (VOP3Mods:{ *:[f16] } f16:{ *:[f16] }:$src1, i32:{ *:[i32] }:$src1_mods)))<<P:Predicate_fmaxnum_like_nnan>>  =>  (V_MED3_F16_e64:{ *:[f16] } ?:{ *:[i32] }:$src0_mods, ?:{ *:[f16] }:$src0, ?:{ *:[i32] }:$src1_mods, ?:{ *:[f16] }:$src1, ?:{ *:[i32] }:$src2_mods, ?:{ *:[f16] }:$src2, 0:{ *:[i1] })
        GIR_BuildMI, /*InsnID*/0, /*Opcode*/GIMT_Encode2(AMDGPU::V_MED3_F16_e64),
        GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/0, // DstI[vdst]
        GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(1), /*SubOperand*/1, // src0_mods
        GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(1), /*SubOperand*/0, // src0
        GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/1, // src1_mods
        GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/0, // src1
        GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(2), /*SubOperand*/1, // src2_mods
        GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(2), /*SubOperand*/0, // src2
        GIR_AddImm8, /*InsnID*/0, /*Imm*/0,
        GIR_AddImm8, /*InsnID*/0, /*Imm*/0,
        GIR_AddImm8, /*InsnID*/0, /*Imm*/0,
        GIR_ConstrainSelectedInstOperands, /*InsnID*/0,
        GIR_EraseFromParent, /*InsnID*/0,
        // GIR_Coverage, 10584,
        GIR_Done,
      // Label 4972: @354464
      GIM_Try, /*On fail goto*//*Label 4973*/ GIMT_Encode4(354610), // Rule ID 10585 //
        GIM_CheckFeatures, GIMT_Encode2(GIFBS_isGFX9Plus),
        GIM_CheckRegBankForClass, /*MI*/0, /*Op*/0, /*RC*/GIMT_Encode2(AMDGPU::VGPR_32RegClassID),
        GIM_RecordInsn, /*DefineMI*/1, /*MI*/0, /*OpIdx*/1, // MIs[1]
        GIM_CheckOpcode, /*MI*/1, GIMT_Encode2(TargetOpcode::G_FMINNUM),
        GIM_CheckType, /*MI*/1, /*Op*/1, /*Type*/GILLT_s16,
        GIM_CheckType, /*MI*/1, /*Op*/2, /*Type*/GILLT_s16,
        GIM_RecordInsn, /*DefineMI*/2, /*MI*/1, /*OpIdx*/1, // MIs[2]
        GIM_CheckOpcode, /*MI*/2, GIMT_Encode2(TargetOpcode::G_FMAXNUM),
        GIM_CheckType, /*MI*/2, /*Op*/1, /*Type*/GILLT_s16,
        GIM_CheckType, /*MI*/2, /*Op*/2, /*Type*/GILLT_s16,
        GIM_RecordInsn, /*DefineMI*/3, /*MI*/0, /*OpIdx*/2, // MIs[3]
        GIM_CheckOpcode, /*MI*/3, GIMT_Encode2(TargetOpcode::G_FMINNUM_IEEE),
        // MIs[3] VOP3Mods:src1:src1_mods
        GIM_CheckIsSameOperand, /*MI*/3, /*OpIdx*/1, /*OtherMI*/2, /*OtherOpIdx*/1,
        // MIs[3] VOP3Mods:src0:src0_mods
        GIM_CheckIsSameOperand, /*MI*/3, /*OpIdx*/2, /*OtherMI*/2, /*OtherOpIdx*/2,
        GIM_CheckCxxInsnPredicate, /*MI*/0, /*FnId*/GIMT_Encode2(GICXXPred_MI_Predicate_fmaxnum_like_nnan),
        GIM_CheckIsSafeToFold, /*InsnID*/1,
        GIM_CheckIsSafeToFold, /*InsnID*/2,
        GIM_CheckIsSafeToFold, /*InsnID*/3,
        GIM_CheckComplexPattern, /*MI*/1, /*Op*/2, /*Renderer*/GIMT_Encode2(2), GIMT_Encode2(GICP_gi_vop3mods),
        GIM_CheckComplexPattern, /*MI*/2, /*Op*/1, /*Renderer*/GIMT_Encode2(0), GIMT_Encode2(GICP_gi_vop3mods),
        GIM_CheckComplexPattern, /*MI*/2, /*Op*/2, /*Renderer*/GIMT_Encode2(1), GIMT_Encode2(GICP_gi_vop3mods),
        // (fmaxnum_ieee:{ *:[f16] } (fminnum:{ *:[f16] } (fmaxnum:{ *:[f16] } (VOP3Mods:{ *:[f16] } f16:{ *:[f16] }:$src1, i32:{ *:[i32] }:$src1_mods), (VOP3Mods:{ *:[f16] } f16:{ *:[f16] }:$src0, i32:{ *:[i32] }:$src0_mods)), (VOP3Mods:{ *:[f16] } f16:{ *:[f16] }:$src2, i32:{ *:[i32] }:$src2_mods)), (fminnum_ieee:{ *:[f16] } (VOP3Mods:{ *:[f16] } f16:{ *:[f16] }:$src1, i32:{ *:[i32] }:$src1_mods), (VOP3Mods:{ *:[f16] } f16:{ *:[f16] }:$src0, i32:{ *:[i32] }:$src0_mods)))<<P:Predicate_fmaxnum_like_nnan>>  =>  (V_MED3_F16_e64:{ *:[f16] } ?:{ *:[i32] }:$src0_mods, ?:{ *:[f16] }:$src0, ?:{ *:[i32] }:$src1_mods, ?:{ *:[f16] }:$src1, ?:{ *:[i32] }:$src2_mods, ?:{ *:[f16] }:$src2, 0:{ *:[i1] })
        GIR_BuildMI, /*InsnID*/0, /*Opcode*/GIMT_Encode2(AMDGPU::V_MED3_F16_e64),
        GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/0, // DstI[vdst]
        GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(1), /*SubOperand*/1, // src0_mods
        GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(1), /*SubOperand*/0, // src0
        GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/1, // src1_mods
        GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/0, // src1
        GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(2), /*SubOperand*/1, // src2_mods
        GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(2), /*SubOperand*/0, // src2
        GIR_AddImm8, /*InsnID*/0, /*Imm*/0,
        GIR_AddImm8, /*InsnID*/0, /*Imm*/0,
        GIR_AddImm8, /*InsnID*/0, /*Imm*/0,
        GIR_ConstrainSelectedInstOperands, /*InsnID*/0,
        GIR_EraseFromParent, /*InsnID*/0,
        // GIR_Coverage, 10585,
        GIR_Done,
      // Label 4973: @354610
      GIM_Try, /*On fail goto*//*Label 4974*/ GIMT_Encode4(354756), // Rule ID 10627 //
        GIM_CheckFeatures, GIMT_Encode2(GIFBS_isGFX9Plus),
        GIM_CheckRegBankForClass, /*MI*/0, /*Op*/0, /*RC*/GIMT_Encode2(AMDGPU::VGPR_32RegClassID),
        GIM_RecordInsn, /*DefineMI*/1, /*MI*/0, /*OpIdx*/1, // MIs[1]
        GIM_CheckOpcode, /*MI*/1, GIMT_Encode2(TargetOpcode::G_FMINNUM),
        GIM_CheckType, /*MI*/1, /*Op*/1, /*Type*/GILLT_s16,
        GIM_CheckType, /*MI*/1, /*Op*/2, /*Type*/GILLT_s16,
        GIM_RecordInsn, /*DefineMI*/2, /*MI*/1, /*OpIdx*/1, // MIs[2]
        GIM_CheckOpcode, /*MI*/2, GIMT_Encode2(TargetOpcode::G_FMAXNUM_IEEE),
        GIM_CheckType, /*MI*/2, /*Op*/1, /*Type*/GILLT_s16,
        GIM_CheckType, /*MI*/2, /*Op*/2, /*Type*/GILLT_s16,
        GIM_RecordInsn, /*DefineMI*/3, /*MI*/0, /*OpIdx*/2, // MIs[3]
        GIM_CheckOpcode, /*MI*/3, GIMT_Encode2(TargetOpcode::G_FMINNUM),
        // MIs[3] VOP3Mods:src0:src0_mods
        GIM_CheckIsSameOperand, /*MI*/3, /*OpIdx*/1, /*OtherMI*/2, /*OtherOpIdx*/1,
        // MIs[3] VOP3Mods:src1:src1_mods
        GIM_CheckIsSameOperand, /*MI*/3, /*OpIdx*/2, /*OtherMI*/2, /*OtherOpIdx*/2,
        GIM_CheckCxxInsnPredicate, /*MI*/0, /*FnId*/GIMT_Encode2(GICXXPred_MI_Predicate_fmaxnum_like_nnan),
        GIM_CheckIsSafeToFold, /*InsnID*/1,
        GIM_CheckIsSafeToFold, /*InsnID*/2,
        GIM_CheckIsSafeToFold, /*InsnID*/3,
        GIM_CheckComplexPattern, /*MI*/1, /*Op*/2, /*Renderer*/GIMT_Encode2(2), GIMT_Encode2(GICP_gi_vop3mods),
        GIM_CheckComplexPattern, /*MI*/2, /*Op*/1, /*Renderer*/GIMT_Encode2(0), GIMT_Encode2(GICP_gi_vop3mods),
        GIM_CheckComplexPattern, /*MI*/2, /*Op*/2, /*Renderer*/GIMT_Encode2(1), GIMT_Encode2(GICP_gi_vop3mods),
        // (fmaxnum_ieee:{ *:[f16] } (fminnum:{ *:[f16] } (fmaxnum_ieee:{ *:[f16] } (VOP3Mods:{ *:[f16] } f16:{ *:[f16] }:$src0, i32:{ *:[i32] }:$src0_mods), (VOP3Mods:{ *:[f16] } f16:{ *:[f16] }:$src1, i32:{ *:[i32] }:$src1_mods)), (VOP3Mods:{ *:[f16] } f16:{ *:[f16] }:$src2, i32:{ *:[i32] }:$src2_mods)), (fminnum:{ *:[f16] } (VOP3Mods:{ *:[f16] } f16:{ *:[f16] }:$src0, i32:{ *:[i32] }:$src0_mods), (VOP3Mods:{ *:[f16] } f16:{ *:[f16] }:$src1, i32:{ *:[i32] }:$src1_mods)))<<P:Predicate_fmaxnum_like_nnan>>  =>  (V_MED3_F16_e64:{ *:[f16] } ?:{ *:[i32] }:$src0_mods, ?:{ *:[f16] }:$src0, ?:{ *:[i32] }:$src1_mods, ?:{ *:[f16] }:$src1, ?:{ *:[i32] }:$src2_mods, ?:{ *:[f16] }:$src2, 0:{ *:[i1] })
        GIR_BuildMI, /*InsnID*/0, /*Opcode*/GIMT_Encode2(AMDGPU::V_MED3_F16_e64),
        GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/0, // DstI[vdst]
        GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/1, // src0_mods
        GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/0, // src0
        GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(1), /*SubOperand*/1, // src1_mods
        GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(1), /*SubOperand*/0, // src1
        GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(2), /*SubOperand*/1, // src2_mods
        GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(2), /*SubOperand*/0, // src2
        GIR_AddImm8, /*InsnID*/0, /*Imm*/0,
        GIR_AddImm8, /*InsnID*/0, /*Imm*/0,
        GIR_AddImm8, /*InsnID*/0, /*Imm*/0,
        GIR_ConstrainSelectedInstOperands, /*InsnID*/0,
        GIR_EraseFromParent, /*InsnID*/0,
        // GIR_Coverage, 10627,
        GIR_Done,
      // Label 4974: @354756
      GIM_Try, /*On fail goto*//*Label 4975*/ GIMT_Encode4(354902), // Rule ID 10628 //
        GIM_CheckFeatures, GIMT_Encode2(GIFBS_isGFX9Plus),
        GIM_CheckRegBankForClass, /*MI*/0, /*Op*/0, /*RC*/GIMT_Encode2(AMDGPU::VGPR_32RegClassID),
        GIM_RecordInsn, /*DefineMI*/1, /*MI*/0, /*OpIdx*/1, // MIs[1]
        GIM_CheckOpcode, /*MI*/1, GIMT_Encode2(TargetOpcode::G_FMINNUM),
        GIM_CheckType, /*MI*/1, /*Op*/1, /*Type*/GILLT_s16,
        GIM_CheckType, /*MI*/1, /*Op*/2, /*Type*/GILLT_s16,
        GIM_RecordInsn, /*DefineMI*/2, /*MI*/1, /*OpIdx*/1, // MIs[2]
        GIM_CheckOpcode, /*MI*/2, GIMT_Encode2(TargetOpcode::G_FMAXNUM_IEEE),
        GIM_CheckType, /*MI*/2, /*Op*/1, /*Type*/GILLT_s16,
        GIM_CheckType, /*MI*/2, /*Op*/2, /*Type*/GILLT_s16,
        GIM_RecordInsn, /*DefineMI*/3, /*MI*/0, /*OpIdx*/2, // MIs[3]
        GIM_CheckOpcode, /*MI*/3, GIMT_Encode2(TargetOpcode::G_FMINNUM),
        // MIs[3] VOP3Mods:src1:src1_mods
        GIM_CheckIsSameOperand, /*MI*/3, /*OpIdx*/1, /*OtherMI*/2, /*OtherOpIdx*/2,
        // MIs[3] VOP3Mods:src0:src0_mods
        GIM_CheckIsSameOperand, /*MI*/3, /*OpIdx*/2, /*OtherMI*/2, /*OtherOpIdx*/1,
        GIM_CheckCxxInsnPredicate, /*MI*/0, /*FnId*/GIMT_Encode2(GICXXPred_MI_Predicate_fmaxnum_like_nnan),
        GIM_CheckIsSafeToFold, /*InsnID*/1,
        GIM_CheckIsSafeToFold, /*InsnID*/2,
        GIM_CheckIsSafeToFold, /*InsnID*/3,
        GIM_CheckComplexPattern, /*MI*/1, /*Op*/2, /*Renderer*/GIMT_Encode2(2), GIMT_Encode2(GICP_gi_vop3mods),
        GIM_CheckComplexPattern, /*MI*/2, /*Op*/1, /*Renderer*/GIMT_Encode2(0), GIMT_Encode2(GICP_gi_vop3mods),
        GIM_CheckComplexPattern, /*MI*/2, /*Op*/2, /*Renderer*/GIMT_Encode2(1), GIMT_Encode2(GICP_gi_vop3mods),
        // (fmaxnum_ieee:{ *:[f16] } (fminnum:{ *:[f16] } (fmaxnum_ieee:{ *:[f16] } (VOP3Mods:{ *:[f16] } f16:{ *:[f16] }:$src0, i32:{ *:[i32] }:$src0_mods), (VOP3Mods:{ *:[f16] } f16:{ *:[f16] }:$src1, i32:{ *:[i32] }:$src1_mods)), (VOP3Mods:{ *:[f16] } f16:{ *:[f16] }:$src2, i32:{ *:[i32] }:$src2_mods)), (fminnum:{ *:[f16] } (VOP3Mods:{ *:[f16] } f16:{ *:[f16] }:$src1, i32:{ *:[i32] }:$src1_mods), (VOP3Mods:{ *:[f16] } f16:{ *:[f16] }:$src0, i32:{ *:[i32] }:$src0_mods)))<<P:Predicate_fmaxnum_like_nnan>>  =>  (V_MED3_F16_e64:{ *:[f16] } ?:{ *:[i32] }:$src0_mods, ?:{ *:[f16] }:$src0, ?:{ *:[i32] }:$src1_mods, ?:{ *:[f16] }:$src1, ?:{ *:[i32] }:$src2_mods, ?:{ *:[f16] }:$src2, 0:{ *:[i1] })
        GIR_BuildMI, /*InsnID*/0, /*Opcode*/GIMT_Encode2(AMDGPU::V_MED3_F16_e64),
        GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/0, // DstI[vdst]
        GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/1, // src0_mods
        GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/0, // src0
        GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(1), /*SubOperand*/1, // src1_mods
        GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(1), /*SubOperand*/0, // src1
        GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(2), /*SubOperand*/1, // src2_mods
        GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(2), /*SubOperand*/0, // src2
        GIR_AddImm8, /*InsnID*/0, /*Imm*/0,
        GIR_AddImm8, /*InsnID*/0, /*Imm*/0,
        GIR_AddImm8, /*InsnID*/0, /*Imm*/0,
        GIR_ConstrainSelectedInstOperands, /*InsnID*/0,
        GIR_EraseFromParent, /*InsnID*/0,
        // GIR_Coverage, 10628,
        GIR_Done,
      // Label 4975: @354902
      GIM_Try, /*On fail goto*//*Label 4976*/ GIMT_Encode4(355048), // Rule ID 10629 //
        GIM_CheckFeatures, GIMT_Encode2(GIFBS_isGFX9Plus),
        GIM_CheckRegBankForClass, /*MI*/0, /*Op*/0, /*RC*/GIMT_Encode2(AMDGPU::VGPR_32RegClassID),
        GIM_RecordInsn, /*DefineMI*/1, /*MI*/0, /*OpIdx*/1, // MIs[1]
        GIM_CheckOpcode, /*MI*/1, GIMT_Encode2(TargetOpcode::G_FMINNUM),
        GIM_CheckType, /*MI*/1, /*Op*/1, /*Type*/GILLT_s16,
        GIM_CheckType, /*MI*/1, /*Op*/2, /*Type*/GILLT_s16,
        GIM_RecordInsn, /*DefineMI*/2, /*MI*/1, /*OpIdx*/1, // MIs[2]
        GIM_CheckOpcode, /*MI*/2, GIMT_Encode2(TargetOpcode::G_FMAXNUM_IEEE),
        GIM_CheckType, /*MI*/2, /*Op*/1, /*Type*/GILLT_s16,
        GIM_CheckType, /*MI*/2, /*Op*/2, /*Type*/GILLT_s16,
        GIM_RecordInsn, /*DefineMI*/3, /*MI*/0, /*OpIdx*/2, // MIs[3]
        GIM_CheckOpcode, /*MI*/3, GIMT_Encode2(TargetOpcode::G_FMINNUM),
        // MIs[3] VOP3Mods:src0:src0_mods
        GIM_CheckIsSameOperand, /*MI*/3, /*OpIdx*/1, /*OtherMI*/2, /*OtherOpIdx*/2,
        // MIs[3] VOP3Mods:src1:src1_mods
        GIM_CheckIsSameOperand, /*MI*/3, /*OpIdx*/2, /*OtherMI*/2, /*OtherOpIdx*/1,
        GIM_CheckCxxInsnPredicate, /*MI*/0, /*FnId*/GIMT_Encode2(GICXXPred_MI_Predicate_fmaxnum_like_nnan),
        GIM_CheckIsSafeToFold, /*InsnID*/1,
        GIM_CheckIsSafeToFold, /*InsnID*/2,
        GIM_CheckIsSafeToFold, /*InsnID*/3,
        GIM_CheckComplexPattern, /*MI*/1, /*Op*/2, /*Renderer*/GIMT_Encode2(2), GIMT_Encode2(GICP_gi_vop3mods),
        GIM_CheckComplexPattern, /*MI*/2, /*Op*/1, /*Renderer*/GIMT_Encode2(0), GIMT_Encode2(GICP_gi_vop3mods),
        GIM_CheckComplexPattern, /*MI*/2, /*Op*/2, /*Renderer*/GIMT_Encode2(1), GIMT_Encode2(GICP_gi_vop3mods),
        // (fmaxnum_ieee:{ *:[f16] } (fminnum:{ *:[f16] } (fmaxnum_ieee:{ *:[f16] } (VOP3Mods:{ *:[f16] } f16:{ *:[f16] }:$src1, i32:{ *:[i32] }:$src1_mods), (VOP3Mods:{ *:[f16] } f16:{ *:[f16] }:$src0, i32:{ *:[i32] }:$src0_mods)), (VOP3Mods:{ *:[f16] } f16:{ *:[f16] }:$src2, i32:{ *:[i32] }:$src2_mods)), (fminnum:{ *:[f16] } (VOP3Mods:{ *:[f16] } f16:{ *:[f16] }:$src0, i32:{ *:[i32] }:$src0_mods), (VOP3Mods:{ *:[f16] } f16:{ *:[f16] }:$src1, i32:{ *:[i32] }:$src1_mods)))<<P:Predicate_fmaxnum_like_nnan>>  =>  (V_MED3_F16_e64:{ *:[f16] } ?:{ *:[i32] }:$src0_mods, ?:{ *:[f16] }:$src0, ?:{ *:[i32] }:$src1_mods, ?:{ *:[f16] }:$src1, ?:{ *:[i32] }:$src2_mods, ?:{ *:[f16] }:$src2, 0:{ *:[i1] })
        GIR_BuildMI, /*InsnID*/0, /*Opcode*/GIMT_Encode2(AMDGPU::V_MED3_F16_e64),
        GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/0, // DstI[vdst]
        GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(1), /*SubOperand*/1, // src0_mods
        GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(1), /*SubOperand*/0, // src0
        GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/1, // src1_mods
        GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/0, // src1
        GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(2), /*SubOperand*/1, // src2_mods
        GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(2), /*SubOperand*/0, // src2
        GIR_AddImm8, /*InsnID*/0, /*Imm*/0,
        GIR_AddImm8, /*InsnID*/0, /*Imm*/0,
        GIR_AddImm8, /*InsnID*/0, /*Imm*/0,
        GIR_ConstrainSelectedInstOperands, /*InsnID*/0,
        GIR_EraseFromParent, /*InsnID*/0,
        // GIR_Coverage, 10629,
        GIR_Done,
      // Label 4976: @355048
      GIM_Try, /*On fail goto*//*Label 4977*/ GIMT_Encode4(355194), // Rule ID 10630 //
        GIM_CheckFeatures, GIMT_Encode2(GIFBS_isGFX9Plus),
        GIM_CheckRegBankForClass, /*MI*/0, /*Op*/0, /*RC*/GIMT_Encode2(AMDGPU::VGPR_32RegClassID),
        GIM_RecordInsn, /*DefineMI*/1, /*MI*/0, /*OpIdx*/1, // MIs[1]
        GIM_CheckOpcode, /*MI*/1, GIMT_Encode2(TargetOpcode::G_FMINNUM),
        GIM_CheckType, /*MI*/1, /*Op*/1, /*Type*/GILLT_s16,
        GIM_CheckType, /*MI*/1, /*Op*/2, /*Type*/GILLT_s16,
        GIM_RecordInsn, /*DefineMI*/2, /*MI*/1, /*OpIdx*/1, // MIs[2]
        GIM_CheckOpcode, /*MI*/2, GIMT_Encode2(TargetOpcode::G_FMAXNUM_IEEE),
        GIM_CheckType, /*MI*/2, /*Op*/1, /*Type*/GILLT_s16,
        GIM_CheckType, /*MI*/2, /*Op*/2, /*Type*/GILLT_s16,
        GIM_RecordInsn, /*DefineMI*/3, /*MI*/0, /*OpIdx*/2, // MIs[3]
        GIM_CheckOpcode, /*MI*/3, GIMT_Encode2(TargetOpcode::G_FMINNUM),
        // MIs[3] VOP3Mods:src1:src1_mods
        GIM_CheckIsSameOperand, /*MI*/3, /*OpIdx*/1, /*OtherMI*/2, /*OtherOpIdx*/1,
        // MIs[3] VOP3Mods:src0:src0_mods
        GIM_CheckIsSameOperand, /*MI*/3, /*OpIdx*/2, /*OtherMI*/2, /*OtherOpIdx*/2,
        GIM_CheckCxxInsnPredicate, /*MI*/0, /*FnId*/GIMT_Encode2(GICXXPred_MI_Predicate_fmaxnum_like_nnan),
        GIM_CheckIsSafeToFold, /*InsnID*/1,
        GIM_CheckIsSafeToFold, /*InsnID*/2,
        GIM_CheckIsSafeToFold, /*InsnID*/3,
        GIM_CheckComplexPattern, /*MI*/1, /*Op*/2, /*Renderer*/GIMT_Encode2(2), GIMT_Encode2(GICP_gi_vop3mods),
        GIM_CheckComplexPattern, /*MI*/2, /*Op*/1, /*Renderer*/GIMT_Encode2(0), GIMT_Encode2(GICP_gi_vop3mods),
        GIM_CheckComplexPattern, /*MI*/2, /*Op*/2, /*Renderer*/GIMT_Encode2(1), GIMT_Encode2(GICP_gi_vop3mods),
        // (fmaxnum_ieee:{ *:[f16] } (fminnum:{ *:[f16] } (fmaxnum_ieee:{ *:[f16] } (VOP3Mods:{ *:[f16] } f16:{ *:[f16] }:$src1, i32:{ *:[i32] }:$src1_mods), (VOP3Mods:{ *:[f16] } f16:{ *:[f16] }:$src0, i32:{ *:[i32] }:$src0_mods)), (VOP3Mods:{ *:[f16] } f16:{ *:[f16] }:$src2, i32:{ *:[i32] }:$src2_mods)), (fminnum:{ *:[f16] } (VOP3Mods:{ *:[f16] } f16:{ *:[f16] }:$src1, i32:{ *:[i32] }:$src1_mods), (VOP3Mods:{ *:[f16] } f16:{ *:[f16] }:$src0, i32:{ *:[i32] }:$src0_mods)))<<P:Predicate_fmaxnum_like_nnan>>  =>  (V_MED3_F16_e64:{ *:[f16] } ?:{ *:[i32] }:$src0_mods, ?:{ *:[f16] }:$src0, ?:{ *:[i32] }:$src1_mods, ?:{ *:[f16] }:$src1, ?:{ *:[i32] }:$src2_mods, ?:{ *:[f16] }:$src2, 0:{ *:[i1] })
        GIR_BuildMI, /*InsnID*/0, /*Opcode*/GIMT_Encode2(AMDGPU::V_MED3_F16_e64),
        GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/0, // DstI[vdst]
        GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(1), /*SubOperand*/1, // src0_mods
        GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(1), /*SubOperand*/0, // src0
        GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/1, // src1_mods
        GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/0, // src1
        GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(2), /*SubOperand*/1, // src2_mods
        GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(2), /*SubOperand*/0, // src2
        GIR_AddImm8, /*InsnID*/0, /*Imm*/0,
        GIR_AddImm8, /*InsnID*/0, /*Imm*/0,
        GIR_AddImm8, /*InsnID*/0, /*Imm*/0,
        GIR_ConstrainSelectedInstOperands, /*InsnID*/0,
        GIR_EraseFromParent, /*InsnID*/0,
        // GIR_Coverage, 10630,
        GIR_Done,
      // Label 4977: @355194
      GIM_Try, /*On fail goto*//*Label 4978*/ GIMT_Encode4(355340), // Rule ID 10567 //
        GIM_CheckFeatures, GIMT_Encode2(GIFBS_isGFX9Plus),
        GIM_CheckRegBankForClass, /*MI*/0, /*Op*/0, /*RC*/GIMT_Encode2(AMDGPU::VGPR_32RegClassID),
        GIM_RecordInsn, /*DefineMI*/1, /*MI*/0, /*OpIdx*/1, // MIs[1]
        GIM_CheckOpcode, /*MI*/1, GIMT_Encode2(TargetOpcode::G_FMINNUM),
        GIM_CheckType, /*MI*/1, /*Op*/1, /*Type*/GILLT_s16,
        GIM_CheckType, /*MI*/1, /*Op*/2, /*Type*/GILLT_s16,
        GIM_RecordInsn, /*DefineMI*/2, /*MI*/1, /*OpIdx*/1, // MIs[2]
        GIM_CheckOpcode, /*MI*/2, GIMT_Encode2(TargetOpcode::G_FMAXNUM_IEEE),
        GIM_CheckType, /*MI*/2, /*Op*/1, /*Type*/GILLT_s16,
        GIM_CheckType, /*MI*/2, /*Op*/2, /*Type*/GILLT_s16,
        GIM_RecordInsn, /*DefineMI*/3, /*MI*/0, /*OpIdx*/2, // MIs[3]
        GIM_CheckOpcode, /*MI*/3, GIMT_Encode2(TargetOpcode::G_FMINNUM_IEEE),
        // MIs[3] VOP3Mods:src0:src0_mods
        GIM_CheckIsSameOperand, /*MI*/3, /*OpIdx*/1, /*OtherMI*/2, /*OtherOpIdx*/1,
        // MIs[3] VOP3Mods:src1:src1_mods
        GIM_CheckIsSameOperand, /*MI*/3, /*OpIdx*/2, /*OtherMI*/2, /*OtherOpIdx*/2,
        GIM_CheckCxxInsnPredicate, /*MI*/0, /*FnId*/GIMT_Encode2(GICXXPred_MI_Predicate_fmaxnum_like_nnan),
        GIM_CheckIsSafeToFold, /*InsnID*/1,
        GIM_CheckIsSafeToFold, /*InsnID*/2,
        GIM_CheckIsSafeToFold, /*InsnID*/3,
        GIM_CheckComplexPattern, /*MI*/1, /*Op*/2, /*Renderer*/GIMT_Encode2(2), GIMT_Encode2(GICP_gi_vop3mods),
        GIM_CheckComplexPattern, /*MI*/2, /*Op*/1, /*Renderer*/GIMT_Encode2(0), GIMT_Encode2(GICP_gi_vop3mods),
        GIM_CheckComplexPattern, /*MI*/2, /*Op*/2, /*Renderer*/GIMT_Encode2(1), GIMT_Encode2(GICP_gi_vop3mods),
        // (fmaxnum_ieee:{ *:[f16] } (fminnum:{ *:[f16] } (fmaxnum_ieee:{ *:[f16] } (VOP3Mods:{ *:[f16] } f16:{ *:[f16] }:$src0, i32:{ *:[i32] }:$src0_mods), (VOP3Mods:{ *:[f16] } f16:{ *:[f16] }:$src1, i32:{ *:[i32] }:$src1_mods)), (VOP3Mods:{ *:[f16] } f16:{ *:[f16] }:$src2, i32:{ *:[i32] }:$src2_mods)), (fminnum_ieee:{ *:[f16] } (VOP3Mods:{ *:[f16] } f16:{ *:[f16] }:$src0, i32:{ *:[i32] }:$src0_mods), (VOP3Mods:{ *:[f16] } f16:{ *:[f16] }:$src1, i32:{ *:[i32] }:$src1_mods)))<<P:Predicate_fmaxnum_like_nnan>>  =>  (V_MED3_F16_e64:{ *:[f16] } ?:{ *:[i32] }:$src0_mods, ?:{ *:[f16] }:$src0, ?:{ *:[i32] }:$src1_mods, ?:{ *:[f16] }:$src1, ?:{ *:[i32] }:$src2_mods, ?:{ *:[f16] }:$src2, 0:{ *:[i1] })
        GIR_BuildMI, /*InsnID*/0, /*Opcode*/GIMT_Encode2(AMDGPU::V_MED3_F16_e64),
        GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/0, // DstI[vdst]
        GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/1, // src0_mods
        GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/0, // src0
        GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(1), /*SubOperand*/1, // src1_mods
        GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(1), /*SubOperand*/0, // src1
        GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(2), /*SubOperand*/1, // src2_mods
        GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(2), /*SubOperand*/0, // src2
        GIR_AddImm8, /*InsnID*/0, /*Imm*/0,
        GIR_AddImm8, /*InsnID*/0, /*Imm*/0,
        GIR_AddImm8, /*InsnID*/0, /*Imm*/0,
        GIR_ConstrainSelectedInstOperands, /*InsnID*/0,
        GIR_EraseFromParent, /*InsnID*/0,
        // GIR_Coverage, 10567,
        GIR_Done,
      // Label 4978: @355340
      GIM_Try, /*On fail goto*//*Label 4979*/ GIMT_Encode4(355486), // Rule ID 10568 //
        GIM_CheckFeatures, GIMT_Encode2(GIFBS_isGFX9Plus),
        GIM_CheckRegBankForClass, /*MI*/0, /*Op*/0, /*RC*/GIMT_Encode2(AMDGPU::VGPR_32RegClassID),
        GIM_RecordInsn, /*DefineMI*/1, /*MI*/0, /*OpIdx*/1, // MIs[1]
        GIM_CheckOpcode, /*MI*/1, GIMT_Encode2(TargetOpcode::G_FMINNUM),
        GIM_CheckType, /*MI*/1, /*Op*/1, /*Type*/GILLT_s16,
        GIM_CheckType, /*MI*/1, /*Op*/2, /*Type*/GILLT_s16,
        GIM_RecordInsn, /*DefineMI*/2, /*MI*/1, /*OpIdx*/1, // MIs[2]
        GIM_CheckOpcode, /*MI*/2, GIMT_Encode2(TargetOpcode::G_FMAXNUM_IEEE),
        GIM_CheckType, /*MI*/2, /*Op*/1, /*Type*/GILLT_s16,
        GIM_CheckType, /*MI*/2, /*Op*/2, /*Type*/GILLT_s16,
        GIM_RecordInsn, /*DefineMI*/3, /*MI*/0, /*OpIdx*/2, // MIs[3]
        GIM_CheckOpcode, /*MI*/3, GIMT_Encode2(TargetOpcode::G_FMINNUM_IEEE),
        // MIs[3] VOP3Mods:src1:src1_mods
        GIM_CheckIsSameOperand, /*MI*/3, /*OpIdx*/1, /*OtherMI*/2, /*OtherOpIdx*/2,
        // MIs[3] VOP3Mods:src0:src0_mods
        GIM_CheckIsSameOperand, /*MI*/3, /*OpIdx*/2, /*OtherMI*/2, /*OtherOpIdx*/1,
        GIM_CheckCxxInsnPredicate, /*MI*/0, /*FnId*/GIMT_Encode2(GICXXPred_MI_Predicate_fmaxnum_like_nnan),
        GIM_CheckIsSafeToFold, /*InsnID*/1,
        GIM_CheckIsSafeToFold, /*InsnID*/2,
        GIM_CheckIsSafeToFold, /*InsnID*/3,
        GIM_CheckComplexPattern, /*MI*/1, /*Op*/2, /*Renderer*/GIMT_Encode2(2), GIMT_Encode2(GICP_gi_vop3mods),
        GIM_CheckComplexPattern, /*MI*/2, /*Op*/1, /*Renderer*/GIMT_Encode2(0), GIMT_Encode2(GICP_gi_vop3mods),
        GIM_CheckComplexPattern, /*MI*/2, /*Op*/2, /*Renderer*/GIMT_Encode2(1), GIMT_Encode2(GICP_gi_vop3mods),
        // (fmaxnum_ieee:{ *:[f16] } (fminnum:{ *:[f16] } (fmaxnum_ieee:{ *:[f16] } (VOP3Mods:{ *:[f16] } f16:{ *:[f16] }:$src0, i32:{ *:[i32] }:$src0_mods), (VOP3Mods:{ *:[f16] } f16:{ *:[f16] }:$src1, i32:{ *:[i32] }:$src1_mods)), (VOP3Mods:{ *:[f16] } f16:{ *:[f16] }:$src2, i32:{ *:[i32] }:$src2_mods)), (fminnum_ieee:{ *:[f16] } (VOP3Mods:{ *:[f16] } f16:{ *:[f16] }:$src1, i32:{ *:[i32] }:$src1_mods), (VOP3Mods:{ *:[f16] } f16:{ *:[f16] }:$src0, i32:{ *:[i32] }:$src0_mods)))<<P:Predicate_fmaxnum_like_nnan>>  =>  (V_MED3_F16_e64:{ *:[f16] } ?:{ *:[i32] }:$src0_mods, ?:{ *:[f16] }:$src0, ?:{ *:[i32] }:$src1_mods, ?:{ *:[f16] }:$src1, ?:{ *:[i32] }:$src2_mods, ?:{ *:[f16] }:$src2, 0:{ *:[i1] })
        GIR_BuildMI, /*InsnID*/0, /*Opcode*/GIMT_Encode2(AMDGPU::V_MED3_F16_e64),
        GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/0, // DstI[vdst]
        GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/1, // src0_mods
        GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/0, // src0
        GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(1), /*SubOperand*/1, // src1_mods
        GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(1), /*SubOperand*/0, // src1
        GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(2), /*SubOperand*/1, // src2_mods
        GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(2), /*SubOperand*/0, // src2
        GIR_AddImm8, /*InsnID*/0, /*Imm*/0,
        GIR_AddImm8, /*InsnID*/0, /*Imm*/0,
        GIR_AddImm8, /*InsnID*/0, /*Imm*/0,
        GIR_ConstrainSelectedInstOperands, /*InsnID*/0,
        GIR_EraseFromParent, /*InsnID*/0,
        // GIR_Coverage, 10568,
        GIR_Done,
      // Label 4979: @355486
      GIM_Try, /*On fail goto*//*Label 4980*/ GIMT_Encode4(355632), // Rule ID 10569 //
        GIM_CheckFeatures, GIMT_Encode2(GIFBS_isGFX9Plus),
        GIM_CheckRegBankForClass, /*MI*/0, /*Op*/0, /*RC*/GIMT_Encode2(AMDGPU::VGPR_32RegClassID),
        GIM_RecordInsn, /*DefineMI*/1, /*MI*/0, /*OpIdx*/1, // MIs[1]
        GIM_CheckOpcode, /*MI*/1, GIMT_Encode2(TargetOpcode::G_FMINNUM),
        GIM_CheckType, /*MI*/1, /*Op*/1, /*Type*/GILLT_s16,
        GIM_CheckType, /*MI*/1, /*Op*/2, /*Type*/GILLT_s16,
        GIM_RecordInsn, /*DefineMI*/2, /*MI*/1, /*OpIdx*/1, // MIs[2]
        GIM_CheckOpcode, /*MI*/2, GIMT_Encode2(TargetOpcode::G_FMAXNUM_IEEE),
        GIM_CheckType, /*MI*/2, /*Op*/1, /*Type*/GILLT_s16,
        GIM_CheckType, /*MI*/2, /*Op*/2, /*Type*/GILLT_s16,
        GIM_RecordInsn, /*DefineMI*/3, /*MI*/0, /*OpIdx*/2, // MIs[3]
        GIM_CheckOpcode, /*MI*/3, GIMT_Encode2(TargetOpcode::G_FMINNUM_IEEE),
        // MIs[3] VOP3Mods:src0:src0_mods
        GIM_CheckIsSameOperand, /*MI*/3, /*OpIdx*/1, /*OtherMI*/2, /*OtherOpIdx*/2,
        // MIs[3] VOP3Mods:src1:src1_mods
        GIM_CheckIsSameOperand, /*MI*/3, /*OpIdx*/2, /*OtherMI*/2, /*OtherOpIdx*/1,
        GIM_CheckCxxInsnPredicate, /*MI*/0, /*FnId*/GIMT_Encode2(GICXXPred_MI_Predicate_fmaxnum_like_nnan),
        GIM_CheckIsSafeToFold, /*InsnID*/1,
        GIM_CheckIsSafeToFold, /*InsnID*/2,
        GIM_CheckIsSafeToFold, /*InsnID*/3,
        GIM_CheckComplexPattern, /*MI*/1, /*Op*/2, /*Renderer*/GIMT_Encode2(2), GIMT_Encode2(GICP_gi_vop3mods),
        GIM_CheckComplexPattern, /*MI*/2, /*Op*/1, /*Renderer*/GIMT_Encode2(0), GIMT_Encode2(GICP_gi_vop3mods),
        GIM_CheckComplexPattern, /*MI*/2, /*Op*/2, /*Renderer*/GIMT_Encode2(1), GIMT_Encode2(GICP_gi_vop3mods),
        // (fmaxnum_ieee:{ *:[f16] } (fminnum:{ *:[f16] } (fmaxnum_ieee:{ *:[f16] } (VOP3Mods:{ *:[f16] } f16:{ *:[f16] }:$src1, i32:{ *:[i32] }:$src1_mods), (VOP3Mods:{ *:[f16] } f16:{ *:[f16] }:$src0, i32:{ *:[i32] }:$src0_mods)), (VOP3Mods:{ *:[f16] } f16:{ *:[f16] }:$src2, i32:{ *:[i32] }:$src2_mods)), (fminnum_ieee:{ *:[f16] } (VOP3Mods:{ *:[f16] } f16:{ *:[f16] }:$src0, i32:{ *:[i32] }:$src0_mods), (VOP3Mods:{ *:[f16] } f16:{ *:[f16] }:$src1, i32:{ *:[i32] }:$src1_mods)))<<P:Predicate_fmaxnum_like_nnan>>  =>  (V_MED3_F16_e64:{ *:[f16] } ?:{ *:[i32] }:$src0_mods, ?:{ *:[f16] }:$src0, ?:{ *:[i32] }:$src1_mods, ?:{ *:[f16] }:$src1, ?:{ *:[i32] }:$src2_mods, ?:{ *:[f16] }:$src2, 0:{ *:[i1] })
        GIR_BuildMI, /*InsnID*/0, /*Opcode*/GIMT_Encode2(AMDGPU::V_MED3_F16_e64),
        GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/0, // DstI[vdst]
        GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(1), /*SubOperand*/1, // src0_mods
        GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(1), /*SubOperand*/0, // src0
        GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/1, // src1_mods
        GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/0, // src1
        GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(2), /*SubOperand*/1, // src2_mods
        GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(2), /*SubOperand*/0, // src2
        GIR_AddImm8, /*InsnID*/0, /*Imm*/0,
        GIR_AddImm8, /*InsnID*/0, /*Imm*/0,
        GIR_AddImm8, /*InsnID*/0, /*Imm*/0,
        GIR_ConstrainSelectedInstOperands, /*InsnID*/0,
        GIR_EraseFromParent, /*InsnID*/0,
        // GIR_Coverage, 10569,
        GIR_Done,
      // Label 4980: @355632
      GIM_Try, /*On fail goto*//*Label 4981*/ GIMT_Encode4(355778), // Rule ID 10570 //
        GIM_CheckFeatures, GIMT_Encode2(GIFBS_isGFX9Plus),
        GIM_CheckRegBankForClass, /*MI*/0, /*Op*/0, /*RC*/GIMT_Encode2(AMDGPU::VGPR_32RegClassID),
        GIM_RecordInsn, /*DefineMI*/1, /*MI*/0, /*OpIdx*/1, // MIs[1]
        GIM_CheckOpcode, /*MI*/1, GIMT_Encode2(TargetOpcode::G_FMINNUM),
        GIM_CheckType, /*MI*/1, /*Op*/1, /*Type*/GILLT_s16,
        GIM_CheckType, /*MI*/1, /*Op*/2, /*Type*/GILLT_s16,
        GIM_RecordInsn, /*DefineMI*/2, /*MI*/1, /*OpIdx*/1, // MIs[2]
        GIM_CheckOpcode, /*MI*/2, GIMT_Encode2(TargetOpcode::G_FMAXNUM_IEEE),
        GIM_CheckType, /*MI*/2, /*Op*/1, /*Type*/GILLT_s16,
        GIM_CheckType, /*MI*/2, /*Op*/2, /*Type*/GILLT_s16,
        GIM_RecordInsn, /*DefineMI*/3, /*MI*/0, /*OpIdx*/2, // MIs[3]
        GIM_CheckOpcode, /*MI*/3, GIMT_Encode2(TargetOpcode::G_FMINNUM_IEEE),
        // MIs[3] VOP3Mods:src1:src1_mods
        GIM_CheckIsSameOperand, /*MI*/3, /*OpIdx*/1, /*OtherMI*/2, /*OtherOpIdx*/1,
        // MIs[3] VOP3Mods:src0:src0_mods
        GIM_CheckIsSameOperand, /*MI*/3, /*OpIdx*/2, /*OtherMI*/2, /*OtherOpIdx*/2,
        GIM_CheckCxxInsnPredicate, /*MI*/0, /*FnId*/GIMT_Encode2(GICXXPred_MI_Predicate_fmaxnum_like_nnan),
        GIM_CheckIsSafeToFold, /*InsnID*/1,
        GIM_CheckIsSafeToFold, /*InsnID*/2,
        GIM_CheckIsSafeToFold, /*InsnID*/3,
        GIM_CheckComplexPattern, /*MI*/1, /*Op*/2, /*Renderer*/GIMT_Encode2(2), GIMT_Encode2(GICP_gi_vop3mods),
        GIM_CheckComplexPattern, /*MI*/2, /*Op*/1, /*Renderer*/GIMT_Encode2(0), GIMT_Encode2(GICP_gi_vop3mods),
        GIM_CheckComplexPattern, /*MI*/2, /*Op*/2, /*Renderer*/GIMT_Encode2(1), GIMT_Encode2(GICP_gi_vop3mods),
        // (fmaxnum_ieee:{ *:[f16] } (fminnum:{ *:[f16] } (fmaxnum_ieee:{ *:[f16] } (VOP3Mods:{ *:[f16] } f16:{ *:[f16] }:$src1, i32:{ *:[i32] }:$src1_mods), (VOP3Mods:{ *:[f16] } f16:{ *:[f16] }:$src0, i32:{ *:[i32] }:$src0_mods)), (VOP3Mods:{ *:[f16] } f16:{ *:[f16] }:$src2, i32:{ *:[i32] }:$src2_mods)), (fminnum_ieee:{ *:[f16] } (VOP3Mods:{ *:[f16] } f16:{ *:[f16] }:$src1, i32:{ *:[i32] }:$src1_mods), (VOP3Mods:{ *:[f16] } f16:{ *:[f16] }:$src0, i32:{ *:[i32] }:$src0_mods)))<<P:Predicate_fmaxnum_like_nnan>>  =>  (V_MED3_F16_e64:{ *:[f16] } ?:{ *:[i32] }:$src0_mods, ?:{ *:[f16] }:$src0, ?:{ *:[i32] }:$src1_mods, ?:{ *:[f16] }:$src1, ?:{ *:[i32] }:$src2_mods, ?:{ *:[f16] }:$src2, 0:{ *:[i1] })
        GIR_BuildMI, /*InsnID*/0, /*Opcode*/GIMT_Encode2(AMDGPU::V_MED3_F16_e64),
        GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/0, // DstI[vdst]
        GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(1), /*SubOperand*/1, // src0_mods
        GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(1), /*SubOperand*/0, // src0
        GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/1, // src1_mods
        GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/0, // src1
        GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(2), /*SubOperand*/1, // src2_mods
        GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(2), /*SubOperand*/0, // src2
        GIR_AddImm8, /*InsnID*/0, /*Imm*/0,
        GIR_AddImm8, /*InsnID*/0, /*Imm*/0,
        GIR_AddImm8, /*InsnID*/0, /*Imm*/0,
        GIR_ConstrainSelectedInstOperands, /*InsnID*/0,
        GIR_EraseFromParent, /*InsnID*/0,
        // GIR_Coverage, 10570,
        GIR_Done,
      // Label 4981: @355778
      GIM_Try, /*On fail goto*//*Label 4982*/ GIMT_Encode4(355924), // Rule ID 10576 //
        GIM_CheckFeatures, GIMT_Encode2(GIFBS_isGFX9Plus),
        GIM_CheckRegBankForClass, /*MI*/0, /*Op*/0, /*RC*/GIMT_Encode2(AMDGPU::VGPR_32RegClassID),
        GIM_RecordInsn, /*DefineMI*/1, /*MI*/0, /*OpIdx*/1, // MIs[1]
        GIM_CheckOpcode, /*MI*/1, GIMT_Encode2(TargetOpcode::G_FMINNUM_IEEE),
        GIM_CheckType, /*MI*/1, /*Op*/1, /*Type*/GILLT_s16,
        GIM_CheckType, /*MI*/1, /*Op*/2, /*Type*/GILLT_s16,
        GIM_RecordInsn, /*DefineMI*/2, /*MI*/0, /*OpIdx*/2, // MIs[2]
        GIM_CheckOpcode, /*MI*/2, GIMT_Encode2(TargetOpcode::G_FMINNUM),
        GIM_CheckType, /*MI*/2, /*Op*/1, /*Type*/GILLT_s16,
        GIM_CheckType, /*MI*/2, /*Op*/2, /*Type*/GILLT_s16,
        GIM_RecordInsn, /*DefineMI*/3, /*MI*/2, /*OpIdx*/2, // MIs[3]
        GIM_CheckOpcode, /*MI*/3, GIMT_Encode2(TargetOpcode::G_FMAXNUM),
        // MIs[3] VOP3Mods:src0:src0_mods
        GIM_CheckIsSameOperand, /*MI*/3, /*OpIdx*/1, /*OtherMI*/1, /*OtherOpIdx*/1,
        // MIs[3] VOP3Mods:src1:src1_mods
        GIM_CheckIsSameOperand, /*MI*/3, /*OpIdx*/2, /*OtherMI*/1, /*OtherOpIdx*/2,
        GIM_CheckCxxInsnPredicate, /*MI*/0, /*FnId*/GIMT_Encode2(GICXXPred_MI_Predicate_fmaxnum_like_nnan),
        GIM_CheckIsSafeToFold, /*InsnID*/1,
        GIM_CheckIsSafeToFold, /*InsnID*/2,
        GIM_CheckIsSafeToFold, /*InsnID*/3,
        GIM_CheckComplexPattern, /*MI*/1, /*Op*/1, /*Renderer*/GIMT_Encode2(0), GIMT_Encode2(GICP_gi_vop3mods),
        GIM_CheckComplexPattern, /*MI*/1, /*Op*/2, /*Renderer*/GIMT_Encode2(1), GIMT_Encode2(GICP_gi_vop3mods),
        GIM_CheckComplexPattern, /*MI*/2, /*Op*/1, /*Renderer*/GIMT_Encode2(2), GIMT_Encode2(GICP_gi_vop3mods),
        // (fmaxnum_ieee:{ *:[f16] } (fminnum_ieee:{ *:[f16] } (VOP3Mods:{ *:[f16] } f16:{ *:[f16] }:$src0, i32:{ *:[i32] }:$src0_mods), (VOP3Mods:{ *:[f16] } f16:{ *:[f16] }:$src1, i32:{ *:[i32] }:$src1_mods)), (fminnum:{ *:[f16] } (VOP3Mods:{ *:[f16] } f16:{ *:[f16] }:$src2, i32:{ *:[i32] }:$src2_mods), (fmaxnum:{ *:[f16] } (VOP3Mods:{ *:[f16] } f16:{ *:[f16] }:$src0, i32:{ *:[i32] }:$src0_mods), (VOP3Mods:{ *:[f16] } f16:{ *:[f16] }:$src1, i32:{ *:[i32] }:$src1_mods))))<<P:Predicate_fmaxnum_like_nnan>>  =>  (V_MED3_F16_e64:{ *:[f16] } ?:{ *:[i32] }:$src0_mods, ?:{ *:[f16] }:$src0, ?:{ *:[i32] }:$src1_mods, ?:{ *:[f16] }:$src1, ?:{ *:[i32] }:$src2_mods, ?:{ *:[f16] }:$src2, 0:{ *:[i1] })
        GIR_BuildMI, /*InsnID*/0, /*Opcode*/GIMT_Encode2(AMDGPU::V_MED3_F16_e64),
        GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/0, // DstI[vdst]
        GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/1, // src0_mods
        GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/0, // src0
        GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(1), /*SubOperand*/1, // src1_mods
        GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(1), /*SubOperand*/0, // src1
        GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(2), /*SubOperand*/1, // src2_mods
        GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(2), /*SubOperand*/0, // src2
        GIR_AddImm8, /*InsnID*/0, /*Imm*/0,
        GIR_AddImm8, /*InsnID*/0, /*Imm*/0,
        GIR_AddImm8, /*InsnID*/0, /*Imm*/0,
        GIR_ConstrainSelectedInstOperands, /*InsnID*/0,
        GIR_EraseFromParent, /*InsnID*/0,
        // GIR_Coverage, 10576,
        GIR_Done,
      // Label 4982: @355924
      GIM_Try, /*On fail goto*//*Label 4983*/ GIMT_Encode4(356070), // Rule ID 10577 //
        GIM_CheckFeatures, GIMT_Encode2(GIFBS_isGFX9Plus),
        GIM_CheckRegBankForClass, /*MI*/0, /*Op*/0, /*RC*/GIMT_Encode2(AMDGPU::VGPR_32RegClassID),
        GIM_RecordInsn, /*DefineMI*/1, /*MI*/0, /*OpIdx*/1, // MIs[1]
        GIM_CheckOpcode, /*MI*/1, GIMT_Encode2(TargetOpcode::G_FMINNUM_IEEE),
        GIM_CheckType, /*MI*/1, /*Op*/1, /*Type*/GILLT_s16,
        GIM_CheckType, /*MI*/1, /*Op*/2, /*Type*/GILLT_s16,
        GIM_RecordInsn, /*DefineMI*/2, /*MI*/0, /*OpIdx*/2, // MIs[2]
        GIM_CheckOpcode, /*MI*/2, GIMT_Encode2(TargetOpcode::G_FMINNUM),
        GIM_CheckType, /*MI*/2, /*Op*/1, /*Type*/GILLT_s16,
        GIM_CheckType, /*MI*/2, /*Op*/2, /*Type*/GILLT_s16,
        GIM_RecordInsn, /*DefineMI*/3, /*MI*/2, /*OpIdx*/2, // MIs[3]
        GIM_CheckOpcode, /*MI*/3, GIMT_Encode2(TargetOpcode::G_FMAXNUM),
        // MIs[3] VOP3Mods:src1:src1_mods
        GIM_CheckIsSameOperand, /*MI*/3, /*OpIdx*/1, /*OtherMI*/1, /*OtherOpIdx*/2,
        // MIs[3] VOP3Mods:src0:src0_mods
        GIM_CheckIsSameOperand, /*MI*/3, /*OpIdx*/2, /*OtherMI*/1, /*OtherOpIdx*/1,
        GIM_CheckCxxInsnPredicate, /*MI*/0, /*FnId*/GIMT_Encode2(GICXXPred_MI_Predicate_fmaxnum_like_nnan),
        GIM_CheckIsSafeToFold, /*InsnID*/1,
        GIM_CheckIsSafeToFold, /*InsnID*/2,
        GIM_CheckIsSafeToFold, /*InsnID*/3,
        GIM_CheckComplexPattern, /*MI*/1, /*Op*/1, /*Renderer*/GIMT_Encode2(0), GIMT_Encode2(GICP_gi_vop3mods),
        GIM_CheckComplexPattern, /*MI*/1, /*Op*/2, /*Renderer*/GIMT_Encode2(1), GIMT_Encode2(GICP_gi_vop3mods),
        GIM_CheckComplexPattern, /*MI*/2, /*Op*/1, /*Renderer*/GIMT_Encode2(2), GIMT_Encode2(GICP_gi_vop3mods),
        // (fmaxnum_ieee:{ *:[f16] } (fminnum_ieee:{ *:[f16] } (VOP3Mods:{ *:[f16] } f16:{ *:[f16] }:$src0, i32:{ *:[i32] }:$src0_mods), (VOP3Mods:{ *:[f16] } f16:{ *:[f16] }:$src1, i32:{ *:[i32] }:$src1_mods)), (fminnum:{ *:[f16] } (VOP3Mods:{ *:[f16] } f16:{ *:[f16] }:$src2, i32:{ *:[i32] }:$src2_mods), (fmaxnum:{ *:[f16] } (VOP3Mods:{ *:[f16] } f16:{ *:[f16] }:$src1, i32:{ *:[i32] }:$src1_mods), (VOP3Mods:{ *:[f16] } f16:{ *:[f16] }:$src0, i32:{ *:[i32] }:$src0_mods))))<<P:Predicate_fmaxnum_like_nnan>>  =>  (V_MED3_F16_e64:{ *:[f16] } ?:{ *:[i32] }:$src0_mods, ?:{ *:[f16] }:$src0, ?:{ *:[i32] }:$src1_mods, ?:{ *:[f16] }:$src1, ?:{ *:[i32] }:$src2_mods, ?:{ *:[f16] }:$src2, 0:{ *:[i1] })
        GIR_BuildMI, /*InsnID*/0, /*Opcode*/GIMT_Encode2(AMDGPU::V_MED3_F16_e64),
        GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/0, // DstI[vdst]
        GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/1, // src0_mods
        GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/0, // src0
        GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(1), /*SubOperand*/1, // src1_mods
        GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(1), /*SubOperand*/0, // src1
        GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(2), /*SubOperand*/1, // src2_mods
        GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(2), /*SubOperand*/0, // src2
        GIR_AddImm8, /*InsnID*/0, /*Imm*/0,
        GIR_AddImm8, /*InsnID*/0, /*Imm*/0,
        GIR_AddImm8, /*InsnID*/0, /*Imm*/0,
        GIR_ConstrainSelectedInstOperands, /*InsnID*/0,
        GIR_EraseFromParent, /*InsnID*/0,
        // GIR_Coverage, 10577,
        GIR_Done,
      // Label 4983: @356070
      GIM_Try, /*On fail goto*//*Label 4984*/ GIMT_Encode4(356216), // Rule ID 10580 //
        GIM_CheckFeatures, GIMT_Encode2(GIFBS_isGFX9Plus),
        GIM_CheckRegBankForClass, /*MI*/0, /*Op*/0, /*RC*/GIMT_Encode2(AMDGPU::VGPR_32RegClassID),
        GIM_RecordInsn, /*DefineMI*/1, /*MI*/0, /*OpIdx*/1, // MIs[1]
        GIM_CheckOpcode, /*MI*/1, GIMT_Encode2(TargetOpcode::G_FMINNUM_IEEE),
        GIM_CheckType, /*MI*/1, /*Op*/1, /*Type*/GILLT_s16,
        GIM_CheckType, /*MI*/1, /*Op*/2, /*Type*/GILLT_s16,
        GIM_RecordInsn, /*DefineMI*/2, /*MI*/0, /*OpIdx*/2, // MIs[2]
        GIM_CheckOpcode, /*MI*/2, GIMT_Encode2(TargetOpcode::G_FMINNUM),
        GIM_CheckType, /*MI*/2, /*Op*/1, /*Type*/GILLT_s16,
        GIM_CheckType, /*MI*/2, /*Op*/2, /*Type*/GILLT_s16,
        GIM_RecordInsn, /*DefineMI*/3, /*MI*/2, /*OpIdx*/2, // MIs[3]
        GIM_CheckOpcode, /*MI*/3, GIMT_Encode2(TargetOpcode::G_FMAXNUM),
        // MIs[3] VOP3Mods:src0:src0_mods
        GIM_CheckIsSameOperand, /*MI*/3, /*OpIdx*/1, /*OtherMI*/1, /*OtherOpIdx*/2,
        // MIs[3] VOP3Mods:src1:src1_mods
        GIM_CheckIsSameOperand, /*MI*/3, /*OpIdx*/2, /*OtherMI*/1, /*OtherOpIdx*/1,
        GIM_CheckCxxInsnPredicate, /*MI*/0, /*FnId*/GIMT_Encode2(GICXXPred_MI_Predicate_fmaxnum_like_nnan),
        GIM_CheckIsSafeToFold, /*InsnID*/1,
        GIM_CheckIsSafeToFold, /*InsnID*/2,
        GIM_CheckIsSafeToFold, /*InsnID*/3,
        GIM_CheckComplexPattern, /*MI*/1, /*Op*/1, /*Renderer*/GIMT_Encode2(0), GIMT_Encode2(GICP_gi_vop3mods),
        GIM_CheckComplexPattern, /*MI*/1, /*Op*/2, /*Renderer*/GIMT_Encode2(1), GIMT_Encode2(GICP_gi_vop3mods),
        GIM_CheckComplexPattern, /*MI*/2, /*Op*/1, /*Renderer*/GIMT_Encode2(2), GIMT_Encode2(GICP_gi_vop3mods),
        // (fmaxnum_ieee:{ *:[f16] } (fminnum_ieee:{ *:[f16] } (VOP3Mods:{ *:[f16] } f16:{ *:[f16] }:$src1, i32:{ *:[i32] }:$src1_mods), (VOP3Mods:{ *:[f16] } f16:{ *:[f16] }:$src0, i32:{ *:[i32] }:$src0_mods)), (fminnum:{ *:[f16] } (VOP3Mods:{ *:[f16] } f16:{ *:[f16] }:$src2, i32:{ *:[i32] }:$src2_mods), (fmaxnum:{ *:[f16] } (VOP3Mods:{ *:[f16] } f16:{ *:[f16] }:$src0, i32:{ *:[i32] }:$src0_mods), (VOP3Mods:{ *:[f16] } f16:{ *:[f16] }:$src1, i32:{ *:[i32] }:$src1_mods))))<<P:Predicate_fmaxnum_like_nnan>>  =>  (V_MED3_F16_e64:{ *:[f16] } ?:{ *:[i32] }:$src0_mods, ?:{ *:[f16] }:$src0, ?:{ *:[i32] }:$src1_mods, ?:{ *:[f16] }:$src1, ?:{ *:[i32] }:$src2_mods, ?:{ *:[f16] }:$src2, 0:{ *:[i1] })
        GIR_BuildMI, /*InsnID*/0, /*Opcode*/GIMT_Encode2(AMDGPU::V_MED3_F16_e64),
        GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/0, // DstI[vdst]
        GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(1), /*SubOperand*/1, // src0_mods
        GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(1), /*SubOperand*/0, // src0
        GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/1, // src1_mods
        GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/0, // src1
        GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(2), /*SubOperand*/1, // src2_mods
        GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(2), /*SubOperand*/0, // src2
        GIR_AddImm8, /*InsnID*/0, /*Imm*/0,
        GIR_AddImm8, /*InsnID*/0, /*Imm*/0,
        GIR_AddImm8, /*InsnID*/0, /*Imm*/0,
        GIR_ConstrainSelectedInstOperands, /*InsnID*/0,
        GIR_EraseFromParent, /*InsnID*/0,
        // GIR_Coverage, 10580,
        GIR_Done,
      // Label 4984: @356216
      GIM_Try, /*On fail goto*//*Label 4985*/ GIMT_Encode4(356362), // Rule ID 10581 //
        GIM_CheckFeatures, GIMT_Encode2(GIFBS_isGFX9Plus),
        GIM_CheckRegBankForClass, /*MI*/0, /*Op*/0, /*RC*/GIMT_Encode2(AMDGPU::VGPR_32RegClassID),
        GIM_RecordInsn, /*DefineMI*/1, /*MI*/0, /*OpIdx*/1, // MIs[1]
        GIM_CheckOpcode, /*MI*/1, GIMT_Encode2(TargetOpcode::G_FMINNUM_IEEE),
        GIM_CheckType, /*MI*/1, /*Op*/1, /*Type*/GILLT_s16,
        GIM_CheckType, /*MI*/1, /*Op*/2, /*Type*/GILLT_s16,
        GIM_RecordInsn, /*DefineMI*/2, /*MI*/0, /*OpIdx*/2, // MIs[2]
        GIM_CheckOpcode, /*MI*/2, GIMT_Encode2(TargetOpcode::G_FMINNUM),
        GIM_CheckType, /*MI*/2, /*Op*/1, /*Type*/GILLT_s16,
        GIM_CheckType, /*MI*/2, /*Op*/2, /*Type*/GILLT_s16,
        GIM_RecordInsn, /*DefineMI*/3, /*MI*/2, /*OpIdx*/2, // MIs[3]
        GIM_CheckOpcode, /*MI*/3, GIMT_Encode2(TargetOpcode::G_FMAXNUM),
        // MIs[3] VOP3Mods:src1:src1_mods
        GIM_CheckIsSameOperand, /*MI*/3, /*OpIdx*/1, /*OtherMI*/1, /*OtherOpIdx*/1,
        // MIs[3] VOP3Mods:src0:src0_mods
        GIM_CheckIsSameOperand, /*MI*/3, /*OpIdx*/2, /*OtherMI*/1, /*OtherOpIdx*/2,
        GIM_CheckCxxInsnPredicate, /*MI*/0, /*FnId*/GIMT_Encode2(GICXXPred_MI_Predicate_fmaxnum_like_nnan),
        GIM_CheckIsSafeToFold, /*InsnID*/1,
        GIM_CheckIsSafeToFold, /*InsnID*/2,
        GIM_CheckIsSafeToFold, /*InsnID*/3,
        GIM_CheckComplexPattern, /*MI*/1, /*Op*/1, /*Renderer*/GIMT_Encode2(0), GIMT_Encode2(GICP_gi_vop3mods),
        GIM_CheckComplexPattern, /*MI*/1, /*Op*/2, /*Renderer*/GIMT_Encode2(1), GIMT_Encode2(GICP_gi_vop3mods),
        GIM_CheckComplexPattern, /*MI*/2, /*Op*/1, /*Renderer*/GIMT_Encode2(2), GIMT_Encode2(GICP_gi_vop3mods),
        // (fmaxnum_ieee:{ *:[f16] } (fminnum_ieee:{ *:[f16] } (VOP3Mods:{ *:[f16] } f16:{ *:[f16] }:$src1, i32:{ *:[i32] }:$src1_mods), (VOP3Mods:{ *:[f16] } f16:{ *:[f16] }:$src0, i32:{ *:[i32] }:$src0_mods)), (fminnum:{ *:[f16] } (VOP3Mods:{ *:[f16] } f16:{ *:[f16] }:$src2, i32:{ *:[i32] }:$src2_mods), (fmaxnum:{ *:[f16] } (VOP3Mods:{ *:[f16] } f16:{ *:[f16] }:$src1, i32:{ *:[i32] }:$src1_mods), (VOP3Mods:{ *:[f16] } f16:{ *:[f16] }:$src0, i32:{ *:[i32] }:$src0_mods))))<<P:Predicate_fmaxnum_like_nnan>>  =>  (V_MED3_F16_e64:{ *:[f16] } ?:{ *:[i32] }:$src0_mods, ?:{ *:[f16] }:$src0, ?:{ *:[i32] }:$src1_mods, ?:{ *:[f16] }:$src1, ?:{ *:[i32] }:$src2_mods, ?:{ *:[f16] }:$src2, 0:{ *:[i1] })
        GIR_BuildMI, /*InsnID*/0, /*Opcode*/GIMT_Encode2(AMDGPU::V_MED3_F16_e64),
        GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/0, // DstI[vdst]
        GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(1), /*SubOperand*/1, // src0_mods
        GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(1), /*SubOperand*/0, // src0
        GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/1, // src1_mods
        GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/0, // src1
        GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(2), /*SubOperand*/1, // src2_mods
        GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(2), /*SubOperand*/0, // src2
        GIR_AddImm8, /*InsnID*/0, /*Imm*/0,
        GIR_AddImm8, /*InsnID*/0, /*Imm*/0,
        GIR_AddImm8, /*InsnID*/0, /*Imm*/0,
        GIR_ConstrainSelectedInstOperands, /*InsnID*/0,
        GIR_EraseFromParent, /*InsnID*/0,
        // GIR_Coverage, 10581,
        GIR_Done,
      // Label 4985: @356362
      GIM_Try, /*On fail goto*//*Label 4986*/ GIMT_Encode4(356508), // Rule ID 10561 //
        GIM_CheckFeatures, GIMT_Encode2(GIFBS_isGFX9Plus),
        GIM_CheckRegBankForClass, /*MI*/0, /*Op*/0, /*RC*/GIMT_Encode2(AMDGPU::VGPR_32RegClassID),
        GIM_RecordInsn, /*DefineMI*/1, /*MI*/0, /*OpIdx*/1, // MIs[1]
        GIM_CheckOpcode, /*MI*/1, GIMT_Encode2(TargetOpcode::G_FMINNUM_IEEE),
        GIM_CheckType, /*MI*/1, /*Op*/1, /*Type*/GILLT_s16,
        GIM_CheckType, /*MI*/1, /*Op*/2, /*Type*/GILLT_s16,
        GIM_RecordInsn, /*DefineMI*/2, /*MI*/0, /*OpIdx*/2, // MIs[2]
        GIM_CheckOpcode, /*MI*/2, GIMT_Encode2(TargetOpcode::G_FMINNUM),
        GIM_CheckType, /*MI*/2, /*Op*/1, /*Type*/GILLT_s16,
        GIM_CheckType, /*MI*/2, /*Op*/2, /*Type*/GILLT_s16,
        GIM_RecordInsn, /*DefineMI*/3, /*MI*/2, /*OpIdx*/2, // MIs[3]
        GIM_CheckOpcode, /*MI*/3, GIMT_Encode2(TargetOpcode::G_FMAXNUM_IEEE),
        // MIs[3] VOP3Mods:src0:src0_mods
        GIM_CheckIsSameOperand, /*MI*/3, /*OpIdx*/1, /*OtherMI*/1, /*OtherOpIdx*/1,
        // MIs[3] VOP3Mods:src1:src1_mods
        GIM_CheckIsSameOperand, /*MI*/3, /*OpIdx*/2, /*OtherMI*/1, /*OtherOpIdx*/2,
        GIM_CheckCxxInsnPredicate, /*MI*/0, /*FnId*/GIMT_Encode2(GICXXPred_MI_Predicate_fmaxnum_like_nnan),
        GIM_CheckIsSafeToFold, /*InsnID*/1,
        GIM_CheckIsSafeToFold, /*InsnID*/2,
        GIM_CheckIsSafeToFold, /*InsnID*/3,
        GIM_CheckComplexPattern, /*MI*/1, /*Op*/1, /*Renderer*/GIMT_Encode2(0), GIMT_Encode2(GICP_gi_vop3mods),
        GIM_CheckComplexPattern, /*MI*/1, /*Op*/2, /*Renderer*/GIMT_Encode2(1), GIMT_Encode2(GICP_gi_vop3mods),
        GIM_CheckComplexPattern, /*MI*/2, /*Op*/1, /*Renderer*/GIMT_Encode2(2), GIMT_Encode2(GICP_gi_vop3mods),
        // (fmaxnum_ieee:{ *:[f16] } (fminnum_ieee:{ *:[f16] } (VOP3Mods:{ *:[f16] } f16:{ *:[f16] }:$src0, i32:{ *:[i32] }:$src0_mods), (VOP3Mods:{ *:[f16] } f16:{ *:[f16] }:$src1, i32:{ *:[i32] }:$src1_mods)), (fminnum:{ *:[f16] } (VOP3Mods:{ *:[f16] } f16:{ *:[f16] }:$src2, i32:{ *:[i32] }:$src2_mods), (fmaxnum_ieee:{ *:[f16] } (VOP3Mods:{ *:[f16] } f16:{ *:[f16] }:$src0, i32:{ *:[i32] }:$src0_mods), (VOP3Mods:{ *:[f16] } f16:{ *:[f16] }:$src1, i32:{ *:[i32] }:$src1_mods))))<<P:Predicate_fmaxnum_like_nnan>>  =>  (V_MED3_F16_e64:{ *:[f16] } ?:{ *:[i32] }:$src0_mods, ?:{ *:[f16] }:$src0, ?:{ *:[i32] }:$src1_mods, ?:{ *:[f16] }:$src1, ?:{ *:[i32] }:$src2_mods, ?:{ *:[f16] }:$src2, 0:{ *:[i1] })
        GIR_BuildMI, /*InsnID*/0, /*Opcode*/GIMT_Encode2(AMDGPU::V_MED3_F16_e64),
        GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/0, // DstI[vdst]
        GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/1, // src0_mods
        GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/0, // src0
        GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(1), /*SubOperand*/1, // src1_mods
        GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(1), /*SubOperand*/0, // src1
        GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(2), /*SubOperand*/1, // src2_mods
        GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(2), /*SubOperand*/0, // src2
        GIR_AddImm8, /*InsnID*/0, /*Imm*/0,
        GIR_AddImm8, /*InsnID*/0, /*Imm*/0,
        GIR_AddImm8, /*InsnID*/0, /*Imm*/0,
        GIR_ConstrainSelectedInstOperands, /*InsnID*/0,
        GIR_EraseFromParent, /*InsnID*/0,
        // GIR_Coverage, 10561,
        GIR_Done,
      // Label 4986: @356508
      GIM_Try, /*On fail goto*//*Label 4987*/ GIMT_Encode4(356654), // Rule ID 10562 //
        GIM_CheckFeatures, GIMT_Encode2(GIFBS_isGFX9Plus),
        GIM_CheckRegBankForClass, /*MI*/0, /*Op*/0, /*RC*/GIMT_Encode2(AMDGPU::VGPR_32RegClassID),
        GIM_RecordInsn, /*DefineMI*/1, /*MI*/0, /*OpIdx*/1, // MIs[1]
        GIM_CheckOpcode, /*MI*/1, GIMT_Encode2(TargetOpcode::G_FMINNUM_IEEE),
        GIM_CheckType, /*MI*/1, /*Op*/1, /*Type*/GILLT_s16,
        GIM_CheckType, /*MI*/1, /*Op*/2, /*Type*/GILLT_s16,
        GIM_RecordInsn, /*DefineMI*/2, /*MI*/0, /*OpIdx*/2, // MIs[2]
        GIM_CheckOpcode, /*MI*/2, GIMT_Encode2(TargetOpcode::G_FMINNUM),
        GIM_CheckType, /*MI*/2, /*Op*/1, /*Type*/GILLT_s16,
        GIM_CheckType, /*MI*/2, /*Op*/2, /*Type*/GILLT_s16,
        GIM_RecordInsn, /*DefineMI*/3, /*MI*/2, /*OpIdx*/2, // MIs[3]
        GIM_CheckOpcode, /*MI*/3, GIMT_Encode2(TargetOpcode::G_FMAXNUM_IEEE),
        // MIs[3] VOP3Mods:src1:src1_mods
        GIM_CheckIsSameOperand, /*MI*/3, /*OpIdx*/1, /*OtherMI*/1, /*OtherOpIdx*/2,
        // MIs[3] VOP3Mods:src0:src0_mods
        GIM_CheckIsSameOperand, /*MI*/3, /*OpIdx*/2, /*OtherMI*/1, /*OtherOpIdx*/1,
        GIM_CheckCxxInsnPredicate, /*MI*/0, /*FnId*/GIMT_Encode2(GICXXPred_MI_Predicate_fmaxnum_like_nnan),
        GIM_CheckIsSafeToFold, /*InsnID*/1,
        GIM_CheckIsSafeToFold, /*InsnID*/2,
        GIM_CheckIsSafeToFold, /*InsnID*/3,
        GIM_CheckComplexPattern, /*MI*/1, /*Op*/1, /*Renderer*/GIMT_Encode2(0), GIMT_Encode2(GICP_gi_vop3mods),
        GIM_CheckComplexPattern, /*MI*/1, /*Op*/2, /*Renderer*/GIMT_Encode2(1), GIMT_Encode2(GICP_gi_vop3mods),
        GIM_CheckComplexPattern, /*MI*/2, /*Op*/1, /*Renderer*/GIMT_Encode2(2), GIMT_Encode2(GICP_gi_vop3mods),
        // (fmaxnum_ieee:{ *:[f16] } (fminnum_ieee:{ *:[f16] } (VOP3Mods:{ *:[f16] } f16:{ *:[f16] }:$src0, i32:{ *:[i32] }:$src0_mods), (VOP3Mods:{ *:[f16] } f16:{ *:[f16] }:$src1, i32:{ *:[i32] }:$src1_mods)), (fminnum:{ *:[f16] } (VOP3Mods:{ *:[f16] } f16:{ *:[f16] }:$src2, i32:{ *:[i32] }:$src2_mods), (fmaxnum_ieee:{ *:[f16] } (VOP3Mods:{ *:[f16] } f16:{ *:[f16] }:$src1, i32:{ *:[i32] }:$src1_mods), (VOP3Mods:{ *:[f16] } f16:{ *:[f16] }:$src0, i32:{ *:[i32] }:$src0_mods))))<<P:Predicate_fmaxnum_like_nnan>>  =>  (V_MED3_F16_e64:{ *:[f16] } ?:{ *:[i32] }:$src0_mods, ?:{ *:[f16] }:$src0, ?:{ *:[i32] }:$src1_mods, ?:{ *:[f16] }:$src1, ?:{ *:[i32] }:$src2_mods, ?:{ *:[f16] }:$src2, 0:{ *:[i1] })
        GIR_BuildMI, /*InsnID*/0, /*Opcode*/GIMT_Encode2(AMDGPU::V_MED3_F16_e64),
        GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/0, // DstI[vdst]
        GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/1, // src0_mods
        GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/0, // src0
        GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(1), /*SubOperand*/1, // src1_mods
        GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(1), /*SubOperand*/0, // src1
        GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(2), /*SubOperand*/1, // src2_mods
        GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(2), /*SubOperand*/0, // src2
        GIR_AddImm8, /*InsnID*/0, /*Imm*/0,
        GIR_AddImm8, /*InsnID*/0, /*Imm*/0,
        GIR_AddImm8, /*InsnID*/0, /*Imm*/0,
        GIR_ConstrainSelectedInstOperands, /*InsnID*/0,
        GIR_EraseFromParent, /*InsnID*/0,
        // GIR_Coverage, 10562,
        GIR_Done,
      // Label 4987: @356654
      GIM_Try, /*On fail goto*//*Label 4988*/ GIMT_Encode4(356800), // Rule ID 10565 //
        GIM_CheckFeatures, GIMT_Encode2(GIFBS_isGFX9Plus),
        GIM_CheckRegBankForClass, /*MI*/0, /*Op*/0, /*RC*/GIMT_Encode2(AMDGPU::VGPR_32RegClassID),
        GIM_RecordInsn, /*DefineMI*/1, /*MI*/0, /*OpIdx*/1, // MIs[1]
        GIM_CheckOpcode, /*MI*/1, GIMT_Encode2(TargetOpcode::G_FMINNUM_IEEE),
        GIM_CheckType, /*MI*/1, /*Op*/1, /*Type*/GILLT_s16,
        GIM_CheckType, /*MI*/1, /*Op*/2, /*Type*/GILLT_s16,
        GIM_RecordInsn, /*DefineMI*/2, /*MI*/0, /*OpIdx*/2, // MIs[2]
        GIM_CheckOpcode, /*MI*/2, GIMT_Encode2(TargetOpcode::G_FMINNUM),
        GIM_CheckType, /*MI*/2, /*Op*/1, /*Type*/GILLT_s16,
        GIM_CheckType, /*MI*/2, /*Op*/2, /*Type*/GILLT_s16,
        GIM_RecordInsn, /*DefineMI*/3, /*MI*/2, /*OpIdx*/2, // MIs[3]
        GIM_CheckOpcode, /*MI*/3, GIMT_Encode2(TargetOpcode::G_FMAXNUM_IEEE),
        // MIs[3] VOP3Mods:src0:src0_mods
        GIM_CheckIsSameOperand, /*MI*/3, /*OpIdx*/1, /*OtherMI*/1, /*OtherOpIdx*/2,
        // MIs[3] VOP3Mods:src1:src1_mods
        GIM_CheckIsSameOperand, /*MI*/3, /*OpIdx*/2, /*OtherMI*/1, /*OtherOpIdx*/1,
        GIM_CheckCxxInsnPredicate, /*MI*/0, /*FnId*/GIMT_Encode2(GICXXPred_MI_Predicate_fmaxnum_like_nnan),
        GIM_CheckIsSafeToFold, /*InsnID*/1,
        GIM_CheckIsSafeToFold, /*InsnID*/2,
        GIM_CheckIsSafeToFold, /*InsnID*/3,
        GIM_CheckComplexPattern, /*MI*/1, /*Op*/1, /*Renderer*/GIMT_Encode2(0), GIMT_Encode2(GICP_gi_vop3mods),
        GIM_CheckComplexPattern, /*MI*/1, /*Op*/2, /*Renderer*/GIMT_Encode2(1), GIMT_Encode2(GICP_gi_vop3mods),
        GIM_CheckComplexPattern, /*MI*/2, /*Op*/1, /*Renderer*/GIMT_Encode2(2), GIMT_Encode2(GICP_gi_vop3mods),
        // (fmaxnum_ieee:{ *:[f16] } (fminnum_ieee:{ *:[f16] } (VOP3Mods:{ *:[f16] } f16:{ *:[f16] }:$src1, i32:{ *:[i32] }:$src1_mods), (VOP3Mods:{ *:[f16] } f16:{ *:[f16] }:$src0, i32:{ *:[i32] }:$src0_mods)), (fminnum:{ *:[f16] } (VOP3Mods:{ *:[f16] } f16:{ *:[f16] }:$src2, i32:{ *:[i32] }:$src2_mods), (fmaxnum_ieee:{ *:[f16] } (VOP3Mods:{ *:[f16] } f16:{ *:[f16] }:$src0, i32:{ *:[i32] }:$src0_mods), (VOP3Mods:{ *:[f16] } f16:{ *:[f16] }:$src1, i32:{ *:[i32] }:$src1_mods))))<<P:Predicate_fmaxnum_like_nnan>>  =>  (V_MED3_F16_e64:{ *:[f16] } ?:{ *:[i32] }:$src0_mods, ?:{ *:[f16] }:$src0, ?:{ *:[i32] }:$src1_mods, ?:{ *:[f16] }:$src1, ?:{ *:[i32] }:$src2_mods, ?:{ *:[f16] }:$src2, 0:{ *:[i1] })
        GIR_BuildMI, /*InsnID*/0, /*Opcode*/GIMT_Encode2(AMDGPU::V_MED3_F16_e64),
        GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/0, // DstI[vdst]
        GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(1), /*SubOperand*/1, // src0_mods
        GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(1), /*SubOperand*/0, // src0
        GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/1, // src1_mods
        GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/0, // src1
        GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(2), /*SubOperand*/1, // src2_mods
        GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(2), /*SubOperand*/0, // src2
        GIR_AddImm8, /*InsnID*/0, /*Imm*/0,
        GIR_AddImm8, /*InsnID*/0, /*Imm*/0,
        GIR_AddImm8, /*InsnID*/0, /*Imm*/0,
        GIR_ConstrainSelectedInstOperands, /*InsnID*/0,
        GIR_EraseFromParent, /*InsnID*/0,
        // GIR_Coverage, 10565,
        GIR_Done,
      // Label 4988: @356800
      GIM_Try, /*On fail goto*//*Label 4989*/ GIMT_Encode4(356946), // Rule ID 10566 //
        GIM_CheckFeatures, GIMT_Encode2(GIFBS_isGFX9Plus),
        GIM_CheckRegBankForClass, /*MI*/0, /*Op*/0, /*RC*/GIMT_Encode2(AMDGPU::VGPR_32RegClassID),
        GIM_RecordInsn, /*DefineMI*/1, /*MI*/0, /*OpIdx*/1, // MIs[1]
        GIM_CheckOpcode, /*MI*/1, GIMT_Encode2(TargetOpcode::G_FMINNUM_IEEE),
        GIM_CheckType, /*MI*/1, /*Op*/1, /*Type*/GILLT_s16,
        GIM_CheckType, /*MI*/1, /*Op*/2, /*Type*/GILLT_s16,
        GIM_RecordInsn, /*DefineMI*/2, /*MI*/0, /*OpIdx*/2, // MIs[2]
        GIM_CheckOpcode, /*MI*/2, GIMT_Encode2(TargetOpcode::G_FMINNUM),
        GIM_CheckType, /*MI*/2, /*Op*/1, /*Type*/GILLT_s16,
        GIM_CheckType, /*MI*/2, /*Op*/2, /*Type*/GILLT_s16,
        GIM_RecordInsn, /*DefineMI*/3, /*MI*/2, /*OpIdx*/2, // MIs[3]
        GIM_CheckOpcode, /*MI*/3, GIMT_Encode2(TargetOpcode::G_FMAXNUM_IEEE),
        // MIs[3] VOP3Mods:src1:src1_mods
        GIM_CheckIsSameOperand, /*MI*/3, /*OpIdx*/1, /*OtherMI*/1, /*OtherOpIdx*/1,
        // MIs[3] VOP3Mods:src0:src0_mods
        GIM_CheckIsSameOperand, /*MI*/3, /*OpIdx*/2, /*OtherMI*/1, /*OtherOpIdx*/2,
        GIM_CheckCxxInsnPredicate, /*MI*/0, /*FnId*/GIMT_Encode2(GICXXPred_MI_Predicate_fmaxnum_like_nnan),
        GIM_CheckIsSafeToFold, /*InsnID*/1,
        GIM_CheckIsSafeToFold, /*InsnID*/2,
        GIM_CheckIsSafeToFold, /*InsnID*/3,
        GIM_CheckComplexPattern, /*MI*/1, /*Op*/1, /*Renderer*/GIMT_Encode2(0), GIMT_Encode2(GICP_gi_vop3mods),
        GIM_CheckComplexPattern, /*MI*/1, /*Op*/2, /*Renderer*/GIMT_Encode2(1), GIMT_Encode2(GICP_gi_vop3mods),
        GIM_CheckComplexPattern, /*MI*/2, /*Op*/1, /*Renderer*/GIMT_Encode2(2), GIMT_Encode2(GICP_gi_vop3mods),
        // (fmaxnum_ieee:{ *:[f16] } (fminnum_ieee:{ *:[f16] } (VOP3Mods:{ *:[f16] } f16:{ *:[f16] }:$src1, i32:{ *:[i32] }:$src1_mods), (VOP3Mods:{ *:[f16] } f16:{ *:[f16] }:$src0, i32:{ *:[i32] }:$src0_mods)), (fminnum:{ *:[f16] } (VOP3Mods:{ *:[f16] } f16:{ *:[f16] }:$src2, i32:{ *:[i32] }:$src2_mods), (fmaxnum_ieee:{ *:[f16] } (VOP3Mods:{ *:[f16] } f16:{ *:[f16] }:$src1, i32:{ *:[i32] }:$src1_mods), (VOP3Mods:{ *:[f16] } f16:{ *:[f16] }:$src0, i32:{ *:[i32] }:$src0_mods))))<<P:Predicate_fmaxnum_like_nnan>>  =>  (V_MED3_F16_e64:{ *:[f16] } ?:{ *:[i32] }:$src0_mods, ?:{ *:[f16] }:$src0, ?:{ *:[i32] }:$src1_mods, ?:{ *:[f16] }:$src1, ?:{ *:[i32] }:$src2_mods, ?:{ *:[f16] }:$src2, 0:{ *:[i1] })
        GIR_BuildMI, /*InsnID*/0, /*Opcode*/GIMT_Encode2(AMDGPU::V_MED3_F16_e64),
        GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/0, // DstI[vdst]
        GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(1), /*SubOperand*/1, // src0_mods
        GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(1), /*SubOperand*/0, // src0
        GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/1, // src1_mods
        GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/0, // src1
        GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(2), /*SubOperand*/1, // src2_mods
        GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(2), /*SubOperand*/0, // src2
        GIR_AddImm8, /*InsnID*/0, /*Imm*/0,
        GIR_AddImm8, /*InsnID*/0, /*Imm*/0,
        GIR_AddImm8, /*InsnID*/0, /*Imm*/0,
        GIR_ConstrainSelectedInstOperands, /*InsnID*/0,
        GIR_EraseFromParent, /*InsnID*/0,
        // GIR_Coverage, 10566,
        GIR_Done,
      // Label 4989: @356946
      GIM_Try, /*On fail goto*//*Label 4990*/ GIMT_Encode4(357092), // Rule ID 6539 //
        GIM_CheckFeatures, GIMT_Encode2(GIFBS_isGFX9Plus),
        GIM_CheckRegBankForClass, /*MI*/0, /*Op*/0, /*RC*/GIMT_Encode2(AMDGPU::VGPR_32RegClassID),
        GIM_RecordInsn, /*DefineMI*/1, /*MI*/0, /*OpIdx*/1, // MIs[1]
        GIM_CheckOpcode, /*MI*/1, GIMT_Encode2(TargetOpcode::G_FMINNUM_IEEE),
        GIM_CheckType, /*MI*/1, /*Op*/1, /*Type*/GILLT_s16,
        GIM_CheckType, /*MI*/1, /*Op*/2, /*Type*/GILLT_s16,
        GIM_RecordInsn, /*DefineMI*/2, /*MI*/0, /*OpIdx*/2, // MIs[2]
        GIM_CheckOpcode, /*MI*/2, GIMT_Encode2(TargetOpcode::G_FMINNUM),
        GIM_CheckType, /*MI*/2, /*Op*/1, /*Type*/GILLT_s16,
        GIM_CheckType, /*MI*/2, /*Op*/2, /*Type*/GILLT_s16,
        GIM_RecordInsn, /*DefineMI*/3, /*MI*/2, /*OpIdx*/1, // MIs[3]
        GIM_CheckOpcode, /*MI*/3, GIMT_Encode2(TargetOpcode::G_FMAXNUM),
        // MIs[3] VOP3Mods:src0:src0_mods
        GIM_CheckIsSameOperand, /*MI*/3, /*OpIdx*/1, /*OtherMI*/1, /*OtherOpIdx*/1,
        // MIs[3] VOP3Mods:src1:src1_mods
        GIM_CheckIsSameOperand, /*MI*/3, /*OpIdx*/2, /*OtherMI*/1, /*OtherOpIdx*/2,
        GIM_CheckCxxInsnPredicate, /*MI*/0, /*FnId*/GIMT_Encode2(GICXXPred_MI_Predicate_fmaxnum_like_nnan),
        GIM_CheckIsSafeToFold, /*InsnID*/1,
        GIM_CheckIsSafeToFold, /*InsnID*/2,
        GIM_CheckIsSafeToFold, /*InsnID*/3,
        GIM_CheckComplexPattern, /*MI*/1, /*Op*/1, /*Renderer*/GIMT_Encode2(0), GIMT_Encode2(GICP_gi_vop3mods),
        GIM_CheckComplexPattern, /*MI*/1, /*Op*/2, /*Renderer*/GIMT_Encode2(1), GIMT_Encode2(GICP_gi_vop3mods),
        GIM_CheckComplexPattern, /*MI*/2, /*Op*/2, /*Renderer*/GIMT_Encode2(2), GIMT_Encode2(GICP_gi_vop3mods),
        // (fmaxnum_ieee:{ *:[f16] } (fminnum_ieee:{ *:[f16] } (VOP3Mods:{ *:[f16] } f16:{ *:[f16] }:$src0, i32:{ *:[i32] }:$src0_mods), (VOP3Mods:{ *:[f16] } f16:{ *:[f16] }:$src1, i32:{ *:[i32] }:$src1_mods)), (fminnum:{ *:[f16] } (fmaxnum:{ *:[f16] } (VOP3Mods:{ *:[f16] } f16:{ *:[f16] }:$src0, i32:{ *:[i32] }:$src0_mods), (VOP3Mods:{ *:[f16] } f16:{ *:[f16] }:$src1, i32:{ *:[i32] }:$src1_mods)), (VOP3Mods:{ *:[f16] } f16:{ *:[f16] }:$src2, i32:{ *:[i32] }:$src2_mods)))<<P:Predicate_fmaxnum_like_nnan>>  =>  (V_MED3_F16_e64:{ *:[f16] } ?:{ *:[i32] }:$src0_mods, ?:{ *:[f16] }:$src0, ?:{ *:[i32] }:$src1_mods, ?:{ *:[f16] }:$src1, ?:{ *:[i32] }:$src2_mods, ?:{ *:[f16] }:$src2, 0:{ *:[i1] })
        GIR_BuildMI, /*InsnID*/0, /*Opcode*/GIMT_Encode2(AMDGPU::V_MED3_F16_e64),
        GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/0, // DstI[vdst]
        GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/1, // src0_mods
        GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/0, // src0
        GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(1), /*SubOperand*/1, // src1_mods
        GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(1), /*SubOperand*/0, // src1
        GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(2), /*SubOperand*/1, // src2_mods
        GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(2), /*SubOperand*/0, // src2
        GIR_AddImm8, /*InsnID*/0, /*Imm*/0,
        GIR_AddImm8, /*InsnID*/0, /*Imm*/0,
        GIR_AddImm8, /*InsnID*/0, /*Imm*/0,
        GIR_ConstrainSelectedInstOperands, /*InsnID*/0,
        GIR_EraseFromParent, /*InsnID*/0,
        // GIR_Coverage, 6539,
        GIR_Done,
      // Label 4990: @357092
      GIM_Try, /*On fail goto*//*Label 4991*/ GIMT_Encode4(357238), // Rule ID 10575 //
        GIM_CheckFeatures, GIMT_Encode2(GIFBS_isGFX9Plus),
        GIM_CheckRegBankForClass, /*MI*/0, /*Op*/0, /*RC*/GIMT_Encode2(AMDGPU::VGPR_32RegClassID),
        GIM_RecordInsn, /*DefineMI*/1, /*MI*/0, /*OpIdx*/1, // MIs[1]
        GIM_CheckOpcode, /*MI*/1, GIMT_Encode2(TargetOpcode::G_FMINNUM_IEEE),
        GIM_CheckType, /*MI*/1, /*Op*/1, /*Type*/GILLT_s16,
        GIM_CheckType, /*MI*/1, /*Op*/2, /*Type*/GILLT_s16,
        GIM_RecordInsn, /*DefineMI*/2, /*MI*/0, /*OpIdx*/2, // MIs[2]
        GIM_CheckOpcode, /*MI*/2, GIMT_Encode2(TargetOpcode::G_FMINNUM),
        GIM_CheckType, /*MI*/2, /*Op*/1, /*Type*/GILLT_s16,
        GIM_CheckType, /*MI*/2, /*Op*/2, /*Type*/GILLT_s16,
        GIM_RecordInsn, /*DefineMI*/3, /*MI*/2, /*OpIdx*/1, // MIs[3]
        GIM_CheckOpcode, /*MI*/3, GIMT_Encode2(TargetOpcode::G_FMAXNUM),
        // MIs[3] VOP3Mods:src1:src1_mods
        GIM_CheckIsSameOperand, /*MI*/3, /*OpIdx*/1, /*OtherMI*/1, /*OtherOpIdx*/2,
        // MIs[3] VOP3Mods:src0:src0_mods
        GIM_CheckIsSameOperand, /*MI*/3, /*OpIdx*/2, /*OtherMI*/1, /*OtherOpIdx*/1,
        GIM_CheckCxxInsnPredicate, /*MI*/0, /*FnId*/GIMT_Encode2(GICXXPred_MI_Predicate_fmaxnum_like_nnan),
        GIM_CheckIsSafeToFold, /*InsnID*/1,
        GIM_CheckIsSafeToFold, /*InsnID*/2,
        GIM_CheckIsSafeToFold, /*InsnID*/3,
        GIM_CheckComplexPattern, /*MI*/1, /*Op*/1, /*Renderer*/GIMT_Encode2(0), GIMT_Encode2(GICP_gi_vop3mods),
        GIM_CheckComplexPattern, /*MI*/1, /*Op*/2, /*Renderer*/GIMT_Encode2(1), GIMT_Encode2(GICP_gi_vop3mods),
        GIM_CheckComplexPattern, /*MI*/2, /*Op*/2, /*Renderer*/GIMT_Encode2(2), GIMT_Encode2(GICP_gi_vop3mods),
        // (fmaxnum_ieee:{ *:[f16] } (fminnum_ieee:{ *:[f16] } (VOP3Mods:{ *:[f16] } f16:{ *:[f16] }:$src0, i32:{ *:[i32] }:$src0_mods), (VOP3Mods:{ *:[f16] } f16:{ *:[f16] }:$src1, i32:{ *:[i32] }:$src1_mods)), (fminnum:{ *:[f16] } (fmaxnum:{ *:[f16] } (VOP3Mods:{ *:[f16] } f16:{ *:[f16] }:$src1, i32:{ *:[i32] }:$src1_mods), (VOP3Mods:{ *:[f16] } f16:{ *:[f16] }:$src0, i32:{ *:[i32] }:$src0_mods)), (VOP3Mods:{ *:[f16] } f16:{ *:[f16] }:$src2, i32:{ *:[i32] }:$src2_mods)))<<P:Predicate_fmaxnum_like_nnan>>  =>  (V_MED3_F16_e64:{ *:[f16] } ?:{ *:[i32] }:$src0_mods, ?:{ *:[f16] }:$src0, ?:{ *:[i32] }:$src1_mods, ?:{ *:[f16] }:$src1, ?:{ *:[i32] }:$src2_mods, ?:{ *:[f16] }:$src2, 0:{ *:[i1] })
        GIR_BuildMI, /*InsnID*/0, /*Opcode*/GIMT_Encode2(AMDGPU::V_MED3_F16_e64),
        GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/0, // DstI[vdst]
        GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/1, // src0_mods
        GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/0, // src0
        GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(1), /*SubOperand*/1, // src1_mods
        GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(1), /*SubOperand*/0, // src1
        GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(2), /*SubOperand*/1, // src2_mods
        GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(2), /*SubOperand*/0, // src2
        GIR_AddImm8, /*InsnID*/0, /*Imm*/0,
        GIR_AddImm8, /*InsnID*/0, /*Imm*/0,
        GIR_AddImm8, /*InsnID*/0, /*Imm*/0,
        GIR_ConstrainSelectedInstOperands, /*InsnID*/0,
        GIR_EraseFromParent, /*InsnID*/0,
        // GIR_Coverage, 10575,
        GIR_Done,
      // Label 4991: @357238
      GIM_Try, /*On fail goto*//*Label 4992*/ GIMT_Encode4(357384), // Rule ID 10578 //
        GIM_CheckFeatures, GIMT_Encode2(GIFBS_isGFX9Plus),
        GIM_CheckRegBankForClass, /*MI*/0, /*Op*/0, /*RC*/GIMT_Encode2(AMDGPU::VGPR_32RegClassID),
        GIM_RecordInsn, /*DefineMI*/1, /*MI*/0, /*OpIdx*/1, // MIs[1]
        GIM_CheckOpcode, /*MI*/1, GIMT_Encode2(TargetOpcode::G_FMINNUM_IEEE),
        GIM_CheckType, /*MI*/1, /*Op*/1, /*Type*/GILLT_s16,
        GIM_CheckType, /*MI*/1, /*Op*/2, /*Type*/GILLT_s16,
        GIM_RecordInsn, /*DefineMI*/2, /*MI*/0, /*OpIdx*/2, // MIs[2]
        GIM_CheckOpcode, /*MI*/2, GIMT_Encode2(TargetOpcode::G_FMINNUM),
        GIM_CheckType, /*MI*/2, /*Op*/1, /*Type*/GILLT_s16,
        GIM_CheckType, /*MI*/2, /*Op*/2, /*Type*/GILLT_s16,
        GIM_RecordInsn, /*DefineMI*/3, /*MI*/2, /*OpIdx*/1, // MIs[3]
        GIM_CheckOpcode, /*MI*/3, GIMT_Encode2(TargetOpcode::G_FMAXNUM),
        // MIs[3] VOP3Mods:src0:src0_mods
        GIM_CheckIsSameOperand, /*MI*/3, /*OpIdx*/1, /*OtherMI*/1, /*OtherOpIdx*/2,
        // MIs[3] VOP3Mods:src1:src1_mods
        GIM_CheckIsSameOperand, /*MI*/3, /*OpIdx*/2, /*OtherMI*/1, /*OtherOpIdx*/1,
        GIM_CheckCxxInsnPredicate, /*MI*/0, /*FnId*/GIMT_Encode2(GICXXPred_MI_Predicate_fmaxnum_like_nnan),
        GIM_CheckIsSafeToFold, /*InsnID*/1,
        GIM_CheckIsSafeToFold, /*InsnID*/2,
        GIM_CheckIsSafeToFold, /*InsnID*/3,
        GIM_CheckComplexPattern, /*MI*/1, /*Op*/1, /*Renderer*/GIMT_Encode2(0), GIMT_Encode2(GICP_gi_vop3mods),
        GIM_CheckComplexPattern, /*MI*/1, /*Op*/2, /*Renderer*/GIMT_Encode2(1), GIMT_Encode2(GICP_gi_vop3mods),
        GIM_CheckComplexPattern, /*MI*/2, /*Op*/2, /*Renderer*/GIMT_Encode2(2), GIMT_Encode2(GICP_gi_vop3mods),
        // (fmaxnum_ieee:{ *:[f16] } (fminnum_ieee:{ *:[f16] } (VOP3Mods:{ *:[f16] } f16:{ *:[f16] }:$src1, i32:{ *:[i32] }:$src1_mods), (VOP3Mods:{ *:[f16] } f16:{ *:[f16] }:$src0, i32:{ *:[i32] }:$src0_mods)), (fminnum:{ *:[f16] } (fmaxnum:{ *:[f16] } (VOP3Mods:{ *:[f16] } f16:{ *:[f16] }:$src0, i32:{ *:[i32] }:$src0_mods), (VOP3Mods:{ *:[f16] } f16:{ *:[f16] }:$src1, i32:{ *:[i32] }:$src1_mods)), (VOP3Mods:{ *:[f16] } f16:{ *:[f16] }:$src2, i32:{ *:[i32] }:$src2_mods)))<<P:Predicate_fmaxnum_like_nnan>>  =>  (V_MED3_F16_e64:{ *:[f16] } ?:{ *:[i32] }:$src0_mods, ?:{ *:[f16] }:$src0, ?:{ *:[i32] }:$src1_mods, ?:{ *:[f16] }:$src1, ?:{ *:[i32] }:$src2_mods, ?:{ *:[f16] }:$src2, 0:{ *:[i1] })
        GIR_BuildMI, /*InsnID*/0, /*Opcode*/GIMT_Encode2(AMDGPU::V_MED3_F16_e64),
        GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/0, // DstI[vdst]
        GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(1), /*SubOperand*/1, // src0_mods
        GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(1), /*SubOperand*/0, // src0
        GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/1, // src1_mods
        GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/0, // src1
        GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(2), /*SubOperand*/1, // src2_mods
        GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(2), /*SubOperand*/0, // src2
        GIR_AddImm8, /*InsnID*/0, /*Imm*/0,
        GIR_AddImm8, /*InsnID*/0, /*Imm*/0,
        GIR_AddImm8, /*InsnID*/0, /*Imm*/0,
        GIR_ConstrainSelectedInstOperands, /*InsnID*/0,
        GIR_EraseFromParent, /*InsnID*/0,
        // GIR_Coverage, 10578,
        GIR_Done,
      // Label 4992: @357384
      GIM_Try, /*On fail goto*//*Label 4993*/ GIMT_Encode4(357530), // Rule ID 10579 //
        GIM_CheckFeatures, GIMT_Encode2(GIFBS_isGFX9Plus),
        GIM_CheckRegBankForClass, /*MI*/0, /*Op*/0, /*RC*/GIMT_Encode2(AMDGPU::VGPR_32RegClassID),
        GIM_RecordInsn, /*DefineMI*/1, /*MI*/0, /*OpIdx*/1, // MIs[1]
        GIM_CheckOpcode, /*MI*/1, GIMT_Encode2(TargetOpcode::G_FMINNUM_IEEE),
        GIM_CheckType, /*MI*/1, /*Op*/1, /*Type*/GILLT_s16,
        GIM_CheckType, /*MI*/1, /*Op*/2, /*Type*/GILLT_s16,
        GIM_RecordInsn, /*DefineMI*/2, /*MI*/0, /*OpIdx*/2, // MIs[2]
        GIM_CheckOpcode, /*MI*/2, GIMT_Encode2(TargetOpcode::G_FMINNUM),
        GIM_CheckType, /*MI*/2, /*Op*/1, /*Type*/GILLT_s16,
        GIM_CheckType, /*MI*/2, /*Op*/2, /*Type*/GILLT_s16,
        GIM_RecordInsn, /*DefineMI*/3, /*MI*/2, /*OpIdx*/1, // MIs[3]
        GIM_CheckOpcode, /*MI*/3, GIMT_Encode2(TargetOpcode::G_FMAXNUM),
        // MIs[3] VOP3Mods:src1:src1_mods
        GIM_CheckIsSameOperand, /*MI*/3, /*OpIdx*/1, /*OtherMI*/1, /*OtherOpIdx*/1,
        // MIs[3] VOP3Mods:src0:src0_mods
        GIM_CheckIsSameOperand, /*MI*/3, /*OpIdx*/2, /*OtherMI*/1, /*OtherOpIdx*/2,
        GIM_CheckCxxInsnPredicate, /*MI*/0, /*FnId*/GIMT_Encode2(GICXXPred_MI_Predicate_fmaxnum_like_nnan),
        GIM_CheckIsSafeToFold, /*InsnID*/1,
        GIM_CheckIsSafeToFold, /*InsnID*/2,
        GIM_CheckIsSafeToFold, /*InsnID*/3,
        GIM_CheckComplexPattern, /*MI*/1, /*Op*/1, /*Renderer*/GIMT_Encode2(0), GIMT_Encode2(GICP_gi_vop3mods),
        GIM_CheckComplexPattern, /*MI*/1, /*Op*/2, /*Renderer*/GIMT_Encode2(1), GIMT_Encode2(GICP_gi_vop3mods),
        GIM_CheckComplexPattern, /*MI*/2, /*Op*/2, /*Renderer*/GIMT_Encode2(2), GIMT_Encode2(GICP_gi_vop3mods),
        // (fmaxnum_ieee:{ *:[f16] } (fminnum_ieee:{ *:[f16] } (VOP3Mods:{ *:[f16] } f16:{ *:[f16] }:$src1, i32:{ *:[i32] }:$src1_mods), (VOP3Mods:{ *:[f16] } f16:{ *:[f16] }:$src0, i32:{ *:[i32] }:$src0_mods)), (fminnum:{ *:[f16] } (fmaxnum:{ *:[f16] } (VOP3Mods:{ *:[f16] } f16:{ *:[f16] }:$src1, i32:{ *:[i32] }:$src1_mods), (VOP3Mods:{ *:[f16] } f16:{ *:[f16] }:$src0, i32:{ *:[i32] }:$src0_mods)), (VOP3Mods:{ *:[f16] } f16:{ *:[f16] }:$src2, i32:{ *:[i32] }:$src2_mods)))<<P:Predicate_fmaxnum_like_nnan>>  =>  (V_MED3_F16_e64:{ *:[f16] } ?:{ *:[i32] }:$src0_mods, ?:{ *:[f16] }:$src0, ?:{ *:[i32] }:$src1_mods, ?:{ *:[f16] }:$src1, ?:{ *:[i32] }:$src2_mods, ?:{ *:[f16] }:$src2, 0:{ *:[i1] })
        GIR_BuildMI, /*InsnID*/0, /*Opcode*/GIMT_Encode2(AMDGPU::V_MED3_F16_e64),
        GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/0, // DstI[vdst]
        GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(1), /*SubOperand*/1, // src0_mods
        GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(1), /*SubOperand*/0, // src0
        GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/1, // src1_mods
        GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/0, // src1
        GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(2), /*SubOperand*/1, // src2_mods
        GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(2), /*SubOperand*/0, // src2
        GIR_AddImm8, /*InsnID*/0, /*Imm*/0,
        GIR_AddImm8, /*InsnID*/0, /*Imm*/0,
        GIR_AddImm8, /*InsnID*/0, /*Imm*/0,
        GIR_ConstrainSelectedInstOperands, /*InsnID*/0,
        GIR_EraseFromParent, /*InsnID*/0,
        // GIR_Coverage, 10579,
        GIR_Done,
      // Label 4993: @357530
      GIM_Try, /*On fail goto*//*Label 4994*/ GIMT_Encode4(357676), // Rule ID 6538 //
        GIM_CheckFeatures, GIMT_Encode2(GIFBS_isGFX9Plus),
        GIM_CheckRegBankForClass, /*MI*/0, /*Op*/0, /*RC*/GIMT_Encode2(AMDGPU::VGPR_32RegClassID),
        GIM_RecordInsn, /*DefineMI*/1, /*MI*/0, /*OpIdx*/1, // MIs[1]
        GIM_CheckOpcode, /*MI*/1, GIMT_Encode2(TargetOpcode::G_FMINNUM_IEEE),
        GIM_CheckType, /*MI*/1, /*Op*/1, /*Type*/GILLT_s16,
        GIM_CheckType, /*MI*/1, /*Op*/2, /*Type*/GILLT_s16,
        GIM_RecordInsn, /*DefineMI*/2, /*MI*/0, /*OpIdx*/2, // MIs[2]
        GIM_CheckOpcode, /*MI*/2, GIMT_Encode2(TargetOpcode::G_FMINNUM),
        GIM_CheckType, /*MI*/2, /*Op*/1, /*Type*/GILLT_s16,
        GIM_CheckType, /*MI*/2, /*Op*/2, /*Type*/GILLT_s16,
        GIM_RecordInsn, /*DefineMI*/3, /*MI*/2, /*OpIdx*/1, // MIs[3]
        GIM_CheckOpcode, /*MI*/3, GIMT_Encode2(TargetOpcode::G_FMAXNUM_IEEE),
        // MIs[3] VOP3Mods:src0:src0_mods
        GIM_CheckIsSameOperand, /*MI*/3, /*OpIdx*/1, /*OtherMI*/1, /*OtherOpIdx*/1,
        // MIs[3] VOP3Mods:src1:src1_mods
        GIM_CheckIsSameOperand, /*MI*/3, /*OpIdx*/2, /*OtherMI*/1, /*OtherOpIdx*/2,
        GIM_CheckCxxInsnPredicate, /*MI*/0, /*FnId*/GIMT_Encode2(GICXXPred_MI_Predicate_fmaxnum_like_nnan),
        GIM_CheckIsSafeToFold, /*InsnID*/1,
        GIM_CheckIsSafeToFold, /*InsnID*/2,
        GIM_CheckIsSafeToFold, /*InsnID*/3,
        GIM_CheckComplexPattern, /*MI*/1, /*Op*/1, /*Renderer*/GIMT_Encode2(0), GIMT_Encode2(GICP_gi_vop3mods),
        GIM_CheckComplexPattern, /*MI*/1, /*Op*/2, /*Renderer*/GIMT_Encode2(1), GIMT_Encode2(GICP_gi_vop3mods),
        GIM_CheckComplexPattern, /*MI*/2, /*Op*/2, /*Renderer*/GIMT_Encode2(2), GIMT_Encode2(GICP_gi_vop3mods),
        // (fmaxnum_ieee:{ *:[f16] } (fminnum_ieee:{ *:[f16] } (VOP3Mods:{ *:[f16] } f16:{ *:[f16] }:$src0, i32:{ *:[i32] }:$src0_mods), (VOP3Mods:{ *:[f16] } f16:{ *:[f16] }:$src1, i32:{ *:[i32] }:$src1_mods)), (fminnum:{ *:[f16] } (fmaxnum_ieee:{ *:[f16] } (VOP3Mods:{ *:[f16] } f16:{ *:[f16] }:$src0, i32:{ *:[i32] }:$src0_mods), (VOP3Mods:{ *:[f16] } f16:{ *:[f16] }:$src1, i32:{ *:[i32] }:$src1_mods)), (VOP3Mods:{ *:[f16] } f16:{ *:[f16] }:$src2, i32:{ *:[i32] }:$src2_mods)))<<P:Predicate_fmaxnum_like_nnan>>  =>  (V_MED3_F16_e64:{ *:[f16] } ?:{ *:[i32] }:$src0_mods, ?:{ *:[f16] }:$src0, ?:{ *:[i32] }:$src1_mods, ?:{ *:[f16] }:$src1, ?:{ *:[i32] }:$src2_mods, ?:{ *:[f16] }:$src2, 0:{ *:[i1] })
        GIR_BuildMI, /*InsnID*/0, /*Opcode*/GIMT_Encode2(AMDGPU::V_MED3_F16_e64),
        GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/0, // DstI[vdst]
        GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/1, // src0_mods
        GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/0, // src0
        GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(1), /*SubOperand*/1, // src1_mods
        GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(1), /*SubOperand*/0, // src1
        GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(2), /*SubOperand*/1, // src2_mods
        GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(2), /*SubOperand*/0, // src2
        GIR_AddImm8, /*InsnID*/0, /*Imm*/0,
        GIR_AddImm8, /*InsnID*/0, /*Imm*/0,
        GIR_AddImm8, /*InsnID*/0, /*Imm*/0,
        GIR_ConstrainSelectedInstOperands, /*InsnID*/0,
        GIR_EraseFromParent, /*InsnID*/0,
        // GIR_Coverage, 6538,
        GIR_Done,
      // Label 4994: @357676
      GIM_Try, /*On fail goto*//*Label 4995*/ GIMT_Encode4(357822), // Rule ID 10560 //
        GIM_CheckFeatures, GIMT_Encode2(GIFBS_isGFX9Plus),
        GIM_CheckRegBankForClass, /*MI*/0, /*Op*/0, /*RC*/GIMT_Encode2(AMDGPU::VGPR_32RegClassID),
        GIM_RecordInsn, /*DefineMI*/1, /*MI*/0, /*OpIdx*/1, // MIs[1]
        GIM_CheckOpcode, /*MI*/1, GIMT_Encode2(TargetOpcode::G_FMINNUM_IEEE),
        GIM_CheckType, /*MI*/1, /*Op*/1, /*Type*/GILLT_s16,
        GIM_CheckType, /*MI*/1, /*Op*/2, /*Type*/GILLT_s16,
        GIM_RecordInsn, /*DefineMI*/2, /*MI*/0, /*OpIdx*/2, // MIs[2]
        GIM_CheckOpcode, /*MI*/2, GIMT_Encode2(TargetOpcode::G_FMINNUM),
        GIM_CheckType, /*MI*/2, /*Op*/1, /*Type*/GILLT_s16,
        GIM_CheckType, /*MI*/2, /*Op*/2, /*Type*/GILLT_s16,
        GIM_RecordInsn, /*DefineMI*/3, /*MI*/2, /*OpIdx*/1, // MIs[3]
        GIM_CheckOpcode, /*MI*/3, GIMT_Encode2(TargetOpcode::G_FMAXNUM_IEEE),
        // MIs[3] VOP3Mods:src1:src1_mods
        GIM_CheckIsSameOperand, /*MI*/3, /*OpIdx*/1, /*OtherMI*/1, /*OtherOpIdx*/2,
        // MIs[3] VOP3Mods:src0:src0_mods
        GIM_CheckIsSameOperand, /*MI*/3, /*OpIdx*/2, /*OtherMI*/1, /*OtherOpIdx*/1,
        GIM_CheckCxxInsnPredicate, /*MI*/0, /*FnId*/GIMT_Encode2(GICXXPred_MI_Predicate_fmaxnum_like_nnan),
        GIM_CheckIsSafeToFold, /*InsnID*/1,
        GIM_CheckIsSafeToFold, /*InsnID*/2,
        GIM_CheckIsSafeToFold, /*InsnID*/3,
        GIM_CheckComplexPattern, /*MI*/1, /*Op*/1, /*Renderer*/GIMT_Encode2(0), GIMT_Encode2(GICP_gi_vop3mods),
        GIM_CheckComplexPattern, /*MI*/1, /*Op*/2, /*Renderer*/GIMT_Encode2(1), GIMT_Encode2(GICP_gi_vop3mods),
        GIM_CheckComplexPattern, /*MI*/2, /*Op*/2, /*Renderer*/GIMT_Encode2(2), GIMT_Encode2(GICP_gi_vop3mods),
        // (fmaxnum_ieee:{ *:[f16] } (fminnum_ieee:{ *:[f16] } (VOP3Mods:{ *:[f16] } f16:{ *:[f16] }:$src0, i32:{ *:[i32] }:$src0_mods), (VOP3Mods:{ *:[f16] } f16:{ *:[f16] }:$src1, i32:{ *:[i32] }:$src1_mods)), (fminnum:{ *:[f16] } (fmaxnum_ieee:{ *:[f16] } (VOP3Mods:{ *:[f16] } f16:{ *:[f16] }:$src1, i32:{ *:[i32] }:$src1_mods), (VOP3Mods:{ *:[f16] } f16:{ *:[f16] }:$src0, i32:{ *:[i32] }:$src0_mods)), (VOP3Mods:{ *:[f16] } f16:{ *:[f16] }:$src2, i32:{ *:[i32] }:$src2_mods)))<<P:Predicate_fmaxnum_like_nnan>>  =>  (V_MED3_F16_e64:{ *:[f16] } ?:{ *:[i32] }:$src0_mods, ?:{ *:[f16] }:$src0, ?:{ *:[i32] }:$src1_mods, ?:{ *:[f16] }:$src1, ?:{ *:[i32] }:$src2_mods, ?:{ *:[f16] }:$src2, 0:{ *:[i1] })
        GIR_BuildMI, /*InsnID*/0, /*Opcode*/GIMT_Encode2(AMDGPU::V_MED3_F16_e64),
        GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/0, // DstI[vdst]
        GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/1, // src0_mods
        GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/0, // src0
        GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(1), /*SubOperand*/1, // src1_mods
        GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(1), /*SubOperand*/0, // src1
        GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(2), /*SubOperand*/1, // src2_mods
        GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(2), /*SubOperand*/0, // src2
        GIR_AddImm8, /*InsnID*/0, /*Imm*/0,
        GIR_AddImm8, /*InsnID*/0, /*Imm*/0,
        GIR_AddImm8, /*InsnID*/0, /*Imm*/0,
        GIR_ConstrainSelectedInstOperands, /*InsnID*/0,
        GIR_EraseFromParent, /*InsnID*/0,
        // GIR_Coverage, 10560,
        GIR_Done,
      // Label 4995: @357822
      GIM_Try, /*On fail goto*//*Label 4996*/ GIMT_Encode4(357968), // Rule ID 10563 //
        GIM_CheckFeatures, GIMT_Encode2(GIFBS_isGFX9Plus),
        GIM_CheckRegBankForClass, /*MI*/0, /*Op*/0, /*RC*/GIMT_Encode2(AMDGPU::VGPR_32RegClassID),
        GIM_RecordInsn, /*DefineMI*/1, /*MI*/0, /*OpIdx*/1, // MIs[1]
        GIM_CheckOpcode, /*MI*/1, GIMT_Encode2(TargetOpcode::G_FMINNUM_IEEE),
        GIM_CheckType, /*MI*/1, /*Op*/1, /*Type*/GILLT_s16,
        GIM_CheckType, /*MI*/1, /*Op*/2, /*Type*/GILLT_s16,
        GIM_RecordInsn, /*DefineMI*/2, /*MI*/0, /*OpIdx*/2, // MIs[2]
        GIM_CheckOpcode, /*MI*/2, GIMT_Encode2(TargetOpcode::G_FMINNUM),
        GIM_CheckType, /*MI*/2, /*Op*/1, /*Type*/GILLT_s16,
        GIM_CheckType, /*MI*/2, /*Op*/2, /*Type*/GILLT_s16,
        GIM_RecordInsn, /*DefineMI*/3, /*MI*/2, /*OpIdx*/1, // MIs[3]
        GIM_CheckOpcode, /*MI*/3, GIMT_Encode2(TargetOpcode::G_FMAXNUM_IEEE),
        // MIs[3] VOP3Mods:src0:src0_mods
        GIM_CheckIsSameOperand, /*MI*/3, /*OpIdx*/1, /*OtherMI*/1, /*OtherOpIdx*/2,
        // MIs[3] VOP3Mods:src1:src1_mods
        GIM_CheckIsSameOperand, /*MI*/3, /*OpIdx*/2, /*OtherMI*/1, /*OtherOpIdx*/1,
        GIM_CheckCxxInsnPredicate, /*MI*/0, /*FnId*/GIMT_Encode2(GICXXPred_MI_Predicate_fmaxnum_like_nnan),
        GIM_CheckIsSafeToFold, /*InsnID*/1,
        GIM_CheckIsSafeToFold, /*InsnID*/2,
        GIM_CheckIsSafeToFold, /*InsnID*/3,
        GIM_CheckComplexPattern, /*MI*/1, /*Op*/1, /*Renderer*/GIMT_Encode2(0), GIMT_Encode2(GICP_gi_vop3mods),
        GIM_CheckComplexPattern, /*MI*/1, /*Op*/2, /*Renderer*/GIMT_Encode2(1), GIMT_Encode2(GICP_gi_vop3mods),
        GIM_CheckComplexPattern, /*MI*/2, /*Op*/2, /*Renderer*/GIMT_Encode2(2), GIMT_Encode2(GICP_gi_vop3mods),
        // (fmaxnum_ieee:{ *:[f16] } (fminnum_ieee:{ *:[f16] } (VOP3Mods:{ *:[f16] } f16:{ *:[f16] }:$src1, i32:{ *:[i32] }:$src1_mods), (VOP3Mods:{ *:[f16] } f16:{ *:[f16] }:$src0, i32:{ *:[i32] }:$src0_mods)), (fminnum:{ *:[f16] } (fmaxnum_ieee:{ *:[f16] } (VOP3Mods:{ *:[f16] } f16:{ *:[f16] }:$src0, i32:{ *:[i32] }:$src0_mods), (VOP3Mods:{ *:[f16] } f16:{ *:[f16] }:$src1, i32:{ *:[i32] }:$src1_mods)), (VOP3Mods:{ *:[f16] } f16:{ *:[f16] }:$src2, i32:{ *:[i32] }:$src2_mods)))<<P:Predicate_fmaxnum_like_nnan>>  =>  (V_MED3_F16_e64:{ *:[f16] } ?:{ *:[i32] }:$src0_mods, ?:{ *:[f16] }:$src0, ?:{ *:[i32] }:$src1_mods, ?:{ *:[f16] }:$src1, ?:{ *:[i32] }:$src2_mods, ?:{ *:[f16] }:$src2, 0:{ *:[i1] })
        GIR_BuildMI, /*InsnID*/0, /*Opcode*/GIMT_Encode2(AMDGPU::V_MED3_F16_e64),
        GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/0, // DstI[vdst]
        GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(1), /*SubOperand*/1, // src0_mods
        GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(1), /*SubOperand*/0, // src0
        GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/1, // src1_mods
        GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/0, // src1
        GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(2), /*SubOperand*/1, // src2_mods
        GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(2), /*SubOperand*/0, // src2
        GIR_AddImm8, /*InsnID*/0, /*Imm*/0,
        GIR_AddImm8, /*InsnID*/0, /*Imm*/0,
        GIR_AddImm8, /*InsnID*/0, /*Imm*/0,
        GIR_ConstrainSelectedInstOperands, /*InsnID*/0,
        GIR_EraseFromParent, /*InsnID*/0,
        // GIR_Coverage, 10563,
        GIR_Done,
      // Label 4996: @357968
      GIM_Try, /*On fail goto*//*Label 4997*/ GIMT_Encode4(358114), // Rule ID 10564 //
        GIM_CheckFeatures, GIMT_Encode2(GIFBS_isGFX9Plus),
        GIM_CheckRegBankForClass, /*MI*/0, /*Op*/0, /*RC*/GIMT_Encode2(AMDGPU::VGPR_32RegClassID),
        GIM_RecordInsn, /*DefineMI*/1, /*MI*/0, /*OpIdx*/1, // MIs[1]
        GIM_CheckOpcode, /*MI*/1, GIMT_Encode2(TargetOpcode::G_FMINNUM_IEEE),
        GIM_CheckType, /*MI*/1, /*Op*/1, /*Type*/GILLT_s16,
        GIM_CheckType, /*MI*/1, /*Op*/2, /*Type*/GILLT_s16,
        GIM_RecordInsn, /*DefineMI*/2, /*MI*/0, /*OpIdx*/2, // MIs[2]
        GIM_CheckOpcode, /*MI*/2, GIMT_Encode2(TargetOpcode::G_FMINNUM),
        GIM_CheckType, /*MI*/2, /*Op*/1, /*Type*/GILLT_s16,
        GIM_CheckType, /*MI*/2, /*Op*/2, /*Type*/GILLT_s16,
        GIM_RecordInsn, /*DefineMI*/3, /*MI*/2, /*OpIdx*/1, // MIs[3]
        GIM_CheckOpcode, /*MI*/3, GIMT_Encode2(TargetOpcode::G_FMAXNUM_IEEE),
        // MIs[3] VOP3Mods:src1:src1_mods
        GIM_CheckIsSameOperand, /*MI*/3, /*OpIdx*/1, /*OtherMI*/1, /*OtherOpIdx*/1,
        // MIs[3] VOP3Mods:src0:src0_mods
        GIM_CheckIsSameOperand, /*MI*/3, /*OpIdx*/2, /*OtherMI*/1, /*OtherOpIdx*/2,
        GIM_CheckCxxInsnPredicate, /*MI*/0, /*FnId*/GIMT_Encode2(GICXXPred_MI_Predicate_fmaxnum_like_nnan),
        GIM_CheckIsSafeToFold, /*InsnID*/1,
        GIM_CheckIsSafeToFold, /*InsnID*/2,
        GIM_CheckIsSafeToFold, /*InsnID*/3,
        GIM_CheckComplexPattern, /*MI*/1, /*Op*/1, /*Renderer*/GIMT_Encode2(0), GIMT_Encode2(GICP_gi_vop3mods),
        GIM_CheckComplexPattern, /*MI*/1, /*Op*/2, /*Renderer*/GIMT_Encode2(1), GIMT_Encode2(GICP_gi_vop3mods),
        GIM_CheckComplexPattern, /*MI*/2, /*Op*/2, /*Renderer*/GIMT_Encode2(2), GIMT_Encode2(GICP_gi_vop3mods),
        // (fmaxnum_ieee:{ *:[f16] } (fminnum_ieee:{ *:[f16] } (VOP3Mods:{ *:[f16] } f16:{ *:[f16] }:$src1, i32:{ *:[i32] }:$src1_mods), (VOP3Mods:{ *:[f16] } f16:{ *:[f16] }:$src0, i32:{ *:[i32] }:$src0_mods)), (fminnum:{ *:[f16] } (fmaxnum_ieee:{ *:[f16] } (VOP3Mods:{ *:[f16] } f16:{ *:[f16] }:$src1, i32:{ *:[i32] }:$src1_mods), (VOP3Mods:{ *:[f16] } f16:{ *:[f16] }:$src0, i32:{ *:[i32] }:$src0_mods)), (VOP3Mods:{ *:[f16] } f16:{ *:[f16] }:$src2, i32:{ *:[i32] }:$src2_mods)))<<P:Predicate_fmaxnum_like_nnan>>  =>  (V_MED3_F16_e64:{ *:[f16] } ?:{ *:[i32] }:$src0_mods, ?:{ *:[f16] }:$src0, ?:{ *:[i32] }:$src1_mods, ?:{ *:[f16] }:$src1, ?:{ *:[i32] }:$src2_mods, ?:{ *:[f16] }:$src2, 0:{ *:[i1] })
        GIR_BuildMI, /*InsnID*/0, /*Opcode*/GIMT_Encode2(AMDGPU::V_MED3_F16_e64),
        GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/0, // DstI[vdst]
        GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(1), /*SubOperand*/1, // src0_mods
        GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(1), /*SubOperand*/0, // src0
        GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/1, // src1_mods
        GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/0, // src1
        GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(2), /*SubOperand*/1, // src2_mods
        GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(2), /*SubOperand*/0, // src2
        GIR_AddImm8, /*InsnID*/0, /*Imm*/0,
        GIR_AddImm8, /*InsnID*/0, /*Imm*/0,
        GIR_AddImm8, /*InsnID*/0, /*Imm*/0,
        GIR_ConstrainSelectedInstOperands, /*InsnID*/0,
        GIR_EraseFromParent, /*InsnID*/0,
        // GIR_Coverage, 10564,
        GIR_Done,
      // Label 4997: @358114
      GIM_Try, /*On fail goto*//*Label 4998*/ GIMT_Encode4(358260), // Rule ID 10546 //
        GIM_CheckFeatures, GIMT_Encode2(GIFBS_isGFX9Plus),
        GIM_CheckRegBankForClass, /*MI*/0, /*Op*/0, /*RC*/GIMT_Encode2(AMDGPU::VGPR_32RegClassID),
        GIM_RecordInsn, /*DefineMI*/1, /*MI*/0, /*OpIdx*/1, // MIs[1]
        GIM_CheckOpcode, /*MI*/1, GIMT_Encode2(TargetOpcode::G_FMINNUM_IEEE),
        GIM_CheckType, /*MI*/1, /*Op*/1, /*Type*/GILLT_s16,
        GIM_CheckType, /*MI*/1, /*Op*/2, /*Type*/GILLT_s16,
        GIM_RecordInsn, /*DefineMI*/2, /*MI*/0, /*OpIdx*/2, // MIs[2]
        GIM_CheckOpcode, /*MI*/2, GIMT_Encode2(TargetOpcode::G_FMINNUM_IEEE),
        GIM_CheckType, /*MI*/2, /*Op*/1, /*Type*/GILLT_s16,
        GIM_CheckType, /*MI*/2, /*Op*/2, /*Type*/GILLT_s16,
        GIM_RecordInsn, /*DefineMI*/3, /*MI*/2, /*OpIdx*/2, // MIs[3]
        GIM_CheckOpcode, /*MI*/3, GIMT_Encode2(TargetOpcode::G_FMAXNUM),
        // MIs[3] VOP3Mods:src0:src0_mods
        GIM_CheckIsSameOperand, /*MI*/3, /*OpIdx*/1, /*OtherMI*/1, /*OtherOpIdx*/1,
        // MIs[3] VOP3Mods:src1:src1_mods
        GIM_CheckIsSameOperand, /*MI*/3, /*OpIdx*/2, /*OtherMI*/1, /*OtherOpIdx*/2,
        GIM_CheckCxxInsnPredicate, /*MI*/0, /*FnId*/GIMT_Encode2(GICXXPred_MI_Predicate_fmaxnum_like_nnan),
        GIM_CheckIsSafeToFold, /*InsnID*/1,
        GIM_CheckIsSafeToFold, /*InsnID*/2,
        GIM_CheckIsSafeToFold, /*InsnID*/3,
        GIM_CheckComplexPattern, /*MI*/1, /*Op*/1, /*Renderer*/GIMT_Encode2(0), GIMT_Encode2(GICP_gi_vop3mods),
        GIM_CheckComplexPattern, /*MI*/1, /*Op*/2, /*Renderer*/GIMT_Encode2(1), GIMT_Encode2(GICP_gi_vop3mods),
        GIM_CheckComplexPattern, /*MI*/2, /*Op*/1, /*Renderer*/GIMT_Encode2(2), GIMT_Encode2(GICP_gi_vop3mods),
        // (fmaxnum_ieee:{ *:[f16] } (fminnum_ieee:{ *:[f16] } (VOP3Mods:{ *:[f16] } f16:{ *:[f16] }:$src0, i32:{ *:[i32] }:$src0_mods), (VOP3Mods:{ *:[f16] } f16:{ *:[f16] }:$src1, i32:{ *:[i32] }:$src1_mods)), (fminnum_ieee:{ *:[f16] } (VOP3Mods:{ *:[f16] } f16:{ *:[f16] }:$src2, i32:{ *:[i32] }:$src2_mods), (fmaxnum:{ *:[f16] } (VOP3Mods:{ *:[f16] } f16:{ *:[f16] }:$src0, i32:{ *:[i32] }:$src0_mods), (VOP3Mods:{ *:[f16] } f16:{ *:[f16] }:$src1, i32:{ *:[i32] }:$src1_mods))))<<P:Predicate_fmaxnum_like_nnan>>  =>  (V_MED3_F16_e64:{ *:[f16] } ?:{ *:[i32] }:$src0_mods, ?:{ *:[f16] }:$src0, ?:{ *:[i32] }:$src1_mods, ?:{ *:[f16] }:$src1, ?:{ *:[i32] }:$src2_mods, ?:{ *:[f16] }:$src2, 0:{ *:[i1] })
        GIR_BuildMI, /*InsnID*/0, /*Opcode*/GIMT_Encode2(AMDGPU::V_MED3_F16_e64),
        GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/0, // DstI[vdst]
        GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/1, // src0_mods
        GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/0, // src0
        GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(1), /*SubOperand*/1, // src1_mods
        GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(1), /*SubOperand*/0, // src1
        GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(2), /*SubOperand*/1, // src2_mods
        GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(2), /*SubOperand*/0, // src2
        GIR_AddImm8, /*InsnID*/0, /*Imm*/0,
        GIR_AddImm8, /*InsnID*/0, /*Imm*/0,
        GIR_AddImm8, /*InsnID*/0, /*Imm*/0,
        GIR_ConstrainSelectedInstOperands, /*InsnID*/0,
        GIR_EraseFromParent, /*InsnID*/0,
        // GIR_Coverage, 10546,
        GIR_Done,
      // Label 4998: @358260
      GIM_Try, /*On fail goto*//*Label 4999*/ GIMT_Encode4(358406), // Rule ID 10547 //
        GIM_CheckFeatures, GIMT_Encode2(GIFBS_isGFX9Plus),
        GIM_CheckRegBankForClass, /*MI*/0, /*Op*/0, /*RC*/GIMT_Encode2(AMDGPU::VGPR_32RegClassID),
        GIM_RecordInsn, /*DefineMI*/1, /*MI*/0, /*OpIdx*/1, // MIs[1]
        GIM_CheckOpcode, /*MI*/1, GIMT_Encode2(TargetOpcode::G_FMINNUM_IEEE),
        GIM_CheckType, /*MI*/1, /*Op*/1, /*Type*/GILLT_s16,
        GIM_CheckType, /*MI*/1, /*Op*/2, /*Type*/GILLT_s16,
        GIM_RecordInsn, /*DefineMI*/2, /*MI*/0, /*OpIdx*/2, // MIs[2]
        GIM_CheckOpcode, /*MI*/2, GIMT_Encode2(TargetOpcode::G_FMINNUM_IEEE),
        GIM_CheckType, /*MI*/2, /*Op*/1, /*Type*/GILLT_s16,
        GIM_CheckType, /*MI*/2, /*Op*/2, /*Type*/GILLT_s16,
        GIM_RecordInsn, /*DefineMI*/3, /*MI*/2, /*OpIdx*/2, // MIs[3]
        GIM_CheckOpcode, /*MI*/3, GIMT_Encode2(TargetOpcode::G_FMAXNUM),
        // MIs[3] VOP3Mods:src1:src1_mods
        GIM_CheckIsSameOperand, /*MI*/3, /*OpIdx*/1, /*OtherMI*/1, /*OtherOpIdx*/2,
        // MIs[3] VOP3Mods:src0:src0_mods
        GIM_CheckIsSameOperand, /*MI*/3, /*OpIdx*/2, /*OtherMI*/1, /*OtherOpIdx*/1,
        GIM_CheckCxxInsnPredicate, /*MI*/0, /*FnId*/GIMT_Encode2(GICXXPred_MI_Predicate_fmaxnum_like_nnan),
        GIM_CheckIsSafeToFold, /*InsnID*/1,
        GIM_CheckIsSafeToFold, /*InsnID*/2,
        GIM_CheckIsSafeToFold, /*InsnID*/3,
        GIM_CheckComplexPattern, /*MI*/1, /*Op*/1, /*Renderer*/GIMT_Encode2(0), GIMT_Encode2(GICP_gi_vop3mods),
        GIM_CheckComplexPattern, /*MI*/1, /*Op*/2, /*Renderer*/GIMT_Encode2(1), GIMT_Encode2(GICP_gi_vop3mods),
        GIM_CheckComplexPattern, /*MI*/2, /*Op*/1, /*Renderer*/GIMT_Encode2(2), GIMT_Encode2(GICP_gi_vop3mods),
        // (fmaxnum_ieee:{ *:[f16] } (fminnum_ieee:{ *:[f16] } (VOP3Mods:{ *:[f16] } f16:{ *:[f16] }:$src0, i32:{ *:[i32] }:$src0_mods), (VOP3Mods:{ *:[f16] } f16:{ *:[f16] }:$src1, i32:{ *:[i32] }:$src1_mods)), (fminnum_ieee:{ *:[f16] } (VOP3Mods:{ *:[f16] } f16:{ *:[f16] }:$src2, i32:{ *:[i32] }:$src2_mods), (fmaxnum:{ *:[f16] } (VOP3Mods:{ *:[f16] } f16:{ *:[f16] }:$src1, i32:{ *:[i32] }:$src1_mods), (VOP3Mods:{ *:[f16] } f16:{ *:[f16] }:$src0, i32:{ *:[i32] }:$src0_mods))))<<P:Predicate_fmaxnum_like_nnan>>  =>  (V_MED3_F16_e64:{ *:[f16] } ?:{ *:[i32] }:$src0_mods, ?:{ *:[f16] }:$src0, ?:{ *:[i32] }:$src1_mods, ?:{ *:[f16] }:$src1, ?:{ *:[i32] }:$src2_mods, ?:{ *:[f16] }:$src2, 0:{ *:[i1] })
        GIR_BuildMI, /*InsnID*/0, /*Opcode*/GIMT_Encode2(AMDGPU::V_MED3_F16_e64),
        GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/0, // DstI[vdst]
        GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/1, // src0_mods
        GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/0, // src0
        GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(1), /*SubOperand*/1, // src1_mods
        GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(1), /*SubOperand*/0, // src1
        GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(2), /*SubOperand*/1, // src2_mods
        GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(2), /*SubOperand*/0, // src2
        GIR_AddImm8, /*InsnID*/0, /*Imm*/0,
        GIR_AddImm8, /*InsnID*/0, /*Imm*/0,
        GIR_AddImm8, /*InsnID*/0, /*Imm*/0,
        GIR_ConstrainSelectedInstOperands, /*InsnID*/0,
        GIR_EraseFromParent, /*InsnID*/0,
        // GIR_Coverage, 10547,
        GIR_Done,
      // Label 4999: @358406
      GIM_Try, /*On fail goto*//*Label 5000*/ GIMT_Encode4(358552), // Rule ID 10550 //
        GIM_CheckFeatures, GIMT_Encode2(GIFBS_isGFX9Plus),
        GIM_CheckRegBankForClass, /*MI*/0, /*Op*/0, /*RC*/GIMT_Encode2(AMDGPU::VGPR_32RegClassID),
        GIM_RecordInsn, /*DefineMI*/1, /*MI*/0, /*OpIdx*/1, // MIs[1]
        GIM_CheckOpcode, /*MI*/1, GIMT_Encode2(TargetOpcode::G_FMINNUM_IEEE),
        GIM_CheckType, /*MI*/1, /*Op*/1, /*Type*/GILLT_s16,
        GIM_CheckType, /*MI*/1, /*Op*/2, /*Type*/GILLT_s16,
        GIM_RecordInsn, /*DefineMI*/2, /*MI*/0, /*OpIdx*/2, // MIs[2]
        GIM_CheckOpcode, /*MI*/2, GIMT_Encode2(TargetOpcode::G_FMINNUM_IEEE),
        GIM_CheckType, /*MI*/2, /*Op*/1, /*Type*/GILLT_s16,
        GIM_CheckType, /*MI*/2, /*Op*/2, /*Type*/GILLT_s16,
        GIM_RecordInsn, /*DefineMI*/3, /*MI*/2, /*OpIdx*/2, // MIs[3]
        GIM_CheckOpcode, /*MI*/3, GIMT_Encode2(TargetOpcode::G_FMAXNUM),
        // MIs[3] VOP3Mods:src0:src0_mods
        GIM_CheckIsSameOperand, /*MI*/3, /*OpIdx*/1, /*OtherMI*/1, /*OtherOpIdx*/2,
        // MIs[3] VOP3Mods:src1:src1_mods
        GIM_CheckIsSameOperand, /*MI*/3, /*OpIdx*/2, /*OtherMI*/1, /*OtherOpIdx*/1,
        GIM_CheckCxxInsnPredicate, /*MI*/0, /*FnId*/GIMT_Encode2(GICXXPred_MI_Predicate_fmaxnum_like_nnan),
        GIM_CheckIsSafeToFold, /*InsnID*/1,
        GIM_CheckIsSafeToFold, /*InsnID*/2,
        GIM_CheckIsSafeToFold, /*InsnID*/3,
        GIM_CheckComplexPattern, /*MI*/1, /*Op*/1, /*Renderer*/GIMT_Encode2(0), GIMT_Encode2(GICP_gi_vop3mods),
        GIM_CheckComplexPattern, /*MI*/1, /*Op*/2, /*Renderer*/GIMT_Encode2(1), GIMT_Encode2(GICP_gi_vop3mods),
        GIM_CheckComplexPattern, /*MI*/2, /*Op*/1, /*Renderer*/GIMT_Encode2(2), GIMT_Encode2(GICP_gi_vop3mods),
        // (fmaxnum_ieee:{ *:[f16] } (fminnum_ieee:{ *:[f16] } (VOP3Mods:{ *:[f16] } f16:{ *:[f16] }:$src1, i32:{ *:[i32] }:$src1_mods), (VOP3Mods:{ *:[f16] } f16:{ *:[f16] }:$src0, i32:{ *:[i32] }:$src0_mods)), (fminnum_ieee:{ *:[f16] } (VOP3Mods:{ *:[f16] } f16:{ *:[f16] }:$src2, i32:{ *:[i32] }:$src2_mods), (fmaxnum:{ *:[f16] } (VOP3Mods:{ *:[f16] } f16:{ *:[f16] }:$src0, i32:{ *:[i32] }:$src0_mods), (VOP3Mods:{ *:[f16] } f16:{ *:[f16] }:$src1, i32:{ *:[i32] }:$src1_mods))))<<P:Predicate_fmaxnum_like_nnan>>  =>  (V_MED3_F16_e64:{ *:[f16] } ?:{ *:[i32] }:$src0_mods, ?:{ *:[f16] }:$src0, ?:{ *:[i32] }:$src1_mods, ?:{ *:[f16] }:$src1, ?:{ *:[i32] }:$src2_mods, ?:{ *:[f16] }:$src2, 0:{ *:[i1] })
        GIR_BuildMI, /*InsnID*/0, /*Opcode*/GIMT_Encode2(AMDGPU::V_MED3_F16_e64),
        GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/0, // DstI[vdst]
        GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(1), /*SubOperand*/1, // src0_mods
        GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(1), /*SubOperand*/0, // src0
        GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/1, // src1_mods
        GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/0, // src1
        GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(2), /*SubOperand*/1, // src2_mods
        GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(2), /*SubOperand*/0, // src2
        GIR_AddImm8, /*InsnID*/0, /*Imm*/0,
        GIR_AddImm8, /*InsnID*/0, /*Imm*/0,
        GIR_AddImm8, /*InsnID*/0, /*Imm*/0,
        GIR_ConstrainSelectedInstOperands, /*InsnID*/0,
        GIR_EraseFromParent, /*InsnID*/0,
        // GIR_Coverage, 10550,
        GIR_Done,
      // Label 5000: @358552
      GIM_Try, /*On fail goto*//*Label 5001*/ GIMT_Encode4(358698), // Rule ID 10551 //
        GIM_CheckFeatures, GIMT_Encode2(GIFBS_isGFX9Plus),
        GIM_CheckRegBankForClass, /*MI*/0, /*Op*/0, /*RC*/GIMT_Encode2(AMDGPU::VGPR_32RegClassID),
        GIM_RecordInsn, /*DefineMI*/1, /*MI*/0, /*OpIdx*/1, // MIs[1]
        GIM_CheckOpcode, /*MI*/1, GIMT_Encode2(TargetOpcode::G_FMINNUM_IEEE),
        GIM_CheckType, /*MI*/1, /*Op*/1, /*Type*/GILLT_s16,
        GIM_CheckType, /*MI*/1, /*Op*/2, /*Type*/GILLT_s16,
        GIM_RecordInsn, /*DefineMI*/2, /*MI*/0, /*OpIdx*/2, // MIs[2]
        GIM_CheckOpcode, /*MI*/2, GIMT_Encode2(TargetOpcode::G_FMINNUM_IEEE),
        GIM_CheckType, /*MI*/2, /*Op*/1, /*Type*/GILLT_s16,
        GIM_CheckType, /*MI*/2, /*Op*/2, /*Type*/GILLT_s16,
        GIM_RecordInsn, /*DefineMI*/3, /*MI*/2, /*OpIdx*/2, // MIs[3]
        GIM_CheckOpcode, /*MI*/3, GIMT_Encode2(TargetOpcode::G_FMAXNUM),
        // MIs[3] VOP3Mods:src1:src1_mods
        GIM_CheckIsSameOperand, /*MI*/3, /*OpIdx*/1, /*OtherMI*/1, /*OtherOpIdx*/1,
        // MIs[3] VOP3Mods:src0:src0_mods
        GIM_CheckIsSameOperand, /*MI*/3, /*OpIdx*/2, /*OtherMI*/1, /*OtherOpIdx*/2,
        GIM_CheckCxxInsnPredicate, /*MI*/0, /*FnId*/GIMT_Encode2(GICXXPred_MI_Predicate_fmaxnum_like_nnan),
        GIM_CheckIsSafeToFold, /*InsnID*/1,
        GIM_CheckIsSafeToFold, /*InsnID*/2,
        GIM_CheckIsSafeToFold, /*InsnID*/3,
        GIM_CheckComplexPattern, /*MI*/1, /*Op*/1, /*Renderer*/GIMT_Encode2(0), GIMT_Encode2(GICP_gi_vop3mods),
        GIM_CheckComplexPattern, /*MI*/1, /*Op*/2, /*Renderer*/GIMT_Encode2(1), GIMT_Encode2(GICP_gi_vop3mods),
        GIM_CheckComplexPattern, /*MI*/2, /*Op*/1, /*Renderer*/GIMT_Encode2(2), GIMT_Encode2(GICP_gi_vop3mods),
        // (fmaxnum_ieee:{ *:[f16] } (fminnum_ieee:{ *:[f16] } (VOP3Mods:{ *:[f16] } f16:{ *:[f16] }:$src1, i32:{ *:[i32] }:$src1_mods), (VOP3Mods:{ *:[f16] } f16:{ *:[f16] }:$src0, i32:{ *:[i32] }:$src0_mods)), (fminnum_ieee:{ *:[f16] } (VOP3Mods:{ *:[f16] } f16:{ *:[f16] }:$src2, i32:{ *:[i32] }:$src2_mods), (fmaxnum:{ *:[f16] } (VOP3Mods:{ *:[f16] } f16:{ *:[f16] }:$src1, i32:{ *:[i32] }:$src1_mods), (VOP3Mods:{ *:[f16] } f16:{ *:[f16] }:$src0, i32:{ *:[i32] }:$src0_mods))))<<P:Predicate_fmaxnum_like_nnan>>  =>  (V_MED3_F16_e64:{ *:[f16] } ?:{ *:[i32] }:$src0_mods, ?:{ *:[f16] }:$src0, ?:{ *:[i32] }:$src1_mods, ?:{ *:[f16] }:$src1, ?:{ *:[i32] }:$src2_mods, ?:{ *:[f16] }:$src2, 0:{ *:[i1] })
        GIR_BuildMI, /*InsnID*/0, /*Opcode*/GIMT_Encode2(AMDGPU::V_MED3_F16_e64),
        GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/0, // DstI[vdst]
        GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(1), /*SubOperand*/1, // src0_mods
        GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(1), /*SubOperand*/0, // src0
        GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/1, // src1_mods
        GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/0, // src1
        GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(2), /*SubOperand*/1, // src2_mods
        GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(2), /*SubOperand*/0, // src2
        GIR_AddImm8, /*InsnID*/0, /*Imm*/0,
        GIR_AddImm8, /*InsnID*/0, /*Imm*/0,
        GIR_AddImm8, /*InsnID*/0, /*Imm*/0,
        GIR_ConstrainSelectedInstOperands, /*InsnID*/0,
        GIR_EraseFromParent, /*InsnID*/0,
        // GIR_Coverage, 10551,
        GIR_Done,
      // Label 5001: @358698
      GIM_Try, /*On fail goto*//*Label 5002*/ GIMT_Encode4(358844), // Rule ID 10531 //
        GIM_CheckFeatures, GIMT_Encode2(GIFBS_isGFX9Plus),
        GIM_CheckRegBankForClass, /*MI*/0, /*Op*/0, /*RC*/GIMT_Encode2(AMDGPU::VGPR_32RegClassID),
        GIM_RecordInsn, /*DefineMI*/1, /*MI*/0, /*OpIdx*/1, // MIs[1]
        GIM_CheckOpcode, /*MI*/1, GIMT_Encode2(TargetOpcode::G_FMINNUM_IEEE),
        GIM_CheckType, /*MI*/1, /*Op*/1, /*Type*/GILLT_s16,
        GIM_CheckType, /*MI*/1, /*Op*/2, /*Type*/GILLT_s16,
        GIM_RecordInsn, /*DefineMI*/2, /*MI*/0, /*OpIdx*/2, // MIs[2]
        GIM_CheckOpcode, /*MI*/2, GIMT_Encode2(TargetOpcode::G_FMINNUM_IEEE),
        GIM_CheckType, /*MI*/2, /*Op*/1, /*Type*/GILLT_s16,
        GIM_CheckType, /*MI*/2, /*Op*/2, /*Type*/GILLT_s16,
        GIM_RecordInsn, /*DefineMI*/3, /*MI*/2, /*OpIdx*/2, // MIs[3]
        GIM_CheckOpcode, /*MI*/3, GIMT_Encode2(TargetOpcode::G_FMAXNUM_IEEE),
        // MIs[3] VOP3Mods:src0:src0_mods
        GIM_CheckIsSameOperand, /*MI*/3, /*OpIdx*/1, /*OtherMI*/1, /*OtherOpIdx*/1,
        // MIs[3] VOP3Mods:src1:src1_mods
        GIM_CheckIsSameOperand, /*MI*/3, /*OpIdx*/2, /*OtherMI*/1, /*OtherOpIdx*/2,
        GIM_CheckCxxInsnPredicate, /*MI*/0, /*FnId*/GIMT_Encode2(GICXXPred_MI_Predicate_fmaxnum_like_nnan),
        GIM_CheckIsSafeToFold, /*InsnID*/1,
        GIM_CheckIsSafeToFold, /*InsnID*/2,
        GIM_CheckIsSafeToFold, /*InsnID*/3,
        GIM_CheckComplexPattern, /*MI*/1, /*Op*/1, /*Renderer*/GIMT_Encode2(0), GIMT_Encode2(GICP_gi_vop3mods),
        GIM_CheckComplexPattern, /*MI*/1, /*Op*/2, /*Renderer*/GIMT_Encode2(1), GIMT_Encode2(GICP_gi_vop3mods),
        GIM_CheckComplexPattern, /*MI*/2, /*Op*/1, /*Renderer*/GIMT_Encode2(2), GIMT_Encode2(GICP_gi_vop3mods),
        // (fmaxnum_ieee:{ *:[f16] } (fminnum_ieee:{ *:[f16] } (VOP3Mods:{ *:[f16] } f16:{ *:[f16] }:$src0, i32:{ *:[i32] }:$src0_mods), (VOP3Mods:{ *:[f16] } f16:{ *:[f16] }:$src1, i32:{ *:[i32] }:$src1_mods)), (fminnum_ieee:{ *:[f16] } (VOP3Mods:{ *:[f16] } f16:{ *:[f16] }:$src2, i32:{ *:[i32] }:$src2_mods), (fmaxnum_ieee:{ *:[f16] } (VOP3Mods:{ *:[f16] } f16:{ *:[f16] }:$src0, i32:{ *:[i32] }:$src0_mods), (VOP3Mods:{ *:[f16] } f16:{ *:[f16] }:$src1, i32:{ *:[i32] }:$src1_mods))))<<P:Predicate_fmaxnum_like_nnan>>  =>  (V_MED3_F16_e64:{ *:[f16] } ?:{ *:[i32] }:$src0_mods, ?:{ *:[f16] }:$src0, ?:{ *:[i32] }:$src1_mods, ?:{ *:[f16] }:$src1, ?:{ *:[i32] }:$src2_mods, ?:{ *:[f16] }:$src2, 0:{ *:[i1] })
        GIR_BuildMI, /*InsnID*/0, /*Opcode*/GIMT_Encode2(AMDGPU::V_MED3_F16_e64),
        GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/0, // DstI[vdst]
        GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/1, // src0_mods
        GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/0, // src0
        GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(1), /*SubOperand*/1, // src1_mods
        GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(1), /*SubOperand*/0, // src1
        GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(2), /*SubOperand*/1, // src2_mods
        GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(2), /*SubOperand*/0, // src2
        GIR_AddImm8, /*InsnID*/0, /*Imm*/0,
        GIR_AddImm8, /*InsnID*/0, /*Imm*/0,
        GIR_AddImm8, /*InsnID*/0, /*Imm*/0,
        GIR_ConstrainSelectedInstOperands, /*InsnID*/0,
        GIR_EraseFromParent, /*InsnID*/0,
        // GIR_Coverage, 10531,
        GIR_Done,
      // Label 5002: @358844
      GIM_Try, /*On fail goto*//*Label 5003*/ GIMT_Encode4(358990), // Rule ID 10532 //
        GIM_CheckFeatures, GIMT_Encode2(GIFBS_isGFX9Plus),
        GIM_CheckRegBankForClass, /*MI*/0, /*Op*/0, /*RC*/GIMT_Encode2(AMDGPU::VGPR_32RegClassID),
        GIM_RecordInsn, /*DefineMI*/1, /*MI*/0, /*OpIdx*/1, // MIs[1]
        GIM_CheckOpcode, /*MI*/1, GIMT_Encode2(TargetOpcode::G_FMINNUM_IEEE),
        GIM_CheckType, /*MI*/1, /*Op*/1, /*Type*/GILLT_s16,
        GIM_CheckType, /*MI*/1, /*Op*/2, /*Type*/GILLT_s16,
        GIM_RecordInsn, /*DefineMI*/2, /*MI*/0, /*OpIdx*/2, // MIs[2]
        GIM_CheckOpcode, /*MI*/2, GIMT_Encode2(TargetOpcode::G_FMINNUM_IEEE),
        GIM_CheckType, /*MI*/2, /*Op*/1, /*Type*/GILLT_s16,
        GIM_CheckType, /*MI*/2, /*Op*/2, /*Type*/GILLT_s16,
        GIM_RecordInsn, /*DefineMI*/3, /*MI*/2, /*OpIdx*/2, // MIs[3]
        GIM_CheckOpcode, /*MI*/3, GIMT_Encode2(TargetOpcode::G_FMAXNUM_IEEE),
        // MIs[3] VOP3Mods:src1:src1_mods
        GIM_CheckIsSameOperand, /*MI*/3, /*OpIdx*/1, /*OtherMI*/1, /*OtherOpIdx*/2,
        // MIs[3] VOP3Mods:src0:src0_mods
        GIM_CheckIsSameOperand, /*MI*/3, /*OpIdx*/2, /*OtherMI*/1, /*OtherOpIdx*/1,
        GIM_CheckCxxInsnPredicate, /*MI*/0, /*FnId*/GIMT_Encode2(GICXXPred_MI_Predicate_fmaxnum_like_nnan),
        GIM_CheckIsSafeToFold, /*InsnID*/1,
        GIM_CheckIsSafeToFold, /*InsnID*/2,
        GIM_CheckIsSafeToFold, /*InsnID*/3,
        GIM_CheckComplexPattern, /*MI*/1, /*Op*/1, /*Renderer*/GIMT_Encode2(0), GIMT_Encode2(GICP_gi_vop3mods),
        GIM_CheckComplexPattern, /*MI*/1, /*Op*/2, /*Renderer*/GIMT_Encode2(1), GIMT_Encode2(GICP_gi_vop3mods),
        GIM_CheckComplexPattern, /*MI*/2, /*Op*/1, /*Renderer*/GIMT_Encode2(2), GIMT_Encode2(GICP_gi_vop3mods),
        // (fmaxnum_ieee:{ *:[f16] } (fminnum_ieee:{ *:[f16] } (VOP3Mods:{ *:[f16] } f16:{ *:[f16] }:$src0, i32:{ *:[i32] }:$src0_mods), (VOP3Mods:{ *:[f16] } f16:{ *:[f16] }:$src1, i32:{ *:[i32] }:$src1_mods)), (fminnum_ieee:{ *:[f16] } (VOP3Mods:{ *:[f16] } f16:{ *:[f16] }:$src2, i32:{ *:[i32] }:$src2_mods), (fmaxnum_ieee:{ *:[f16] } (VOP3Mods:{ *:[f16] } f16:{ *:[f16] }:$src1, i32:{ *:[i32] }:$src1_mods), (VOP3Mods:{ *:[f16] } f16:{ *:[f16] }:$src0, i32:{ *:[i32] }:$src0_mods))))<<P:Predicate_fmaxnum_like_nnan>>  =>  (V_MED3_F16_e64:{ *:[f16] } ?:{ *:[i32] }:$src0_mods, ?:{ *:[f16] }:$src0, ?:{ *:[i32] }:$src1_mods, ?:{ *:[f16] }:$src1, ?:{ *:[i32] }:$src2_mods, ?:{ *:[f16] }:$src2, 0:{ *:[i1] })
        GIR_BuildMI, /*InsnID*/0, /*Opcode*/GIMT_Encode2(AMDGPU::V_MED3_F16_e64),
        GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/0, // DstI[vdst]
        GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/1, // src0_mods
        GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/0, // src0
        GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(1), /*SubOperand*/1, // src1_mods
        GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(1), /*SubOperand*/0, // src1
        GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(2), /*SubOperand*/1, // src2_mods
        GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(2), /*SubOperand*/0, // src2
        GIR_AddImm8, /*InsnID*/0, /*Imm*/0,
        GIR_AddImm8, /*InsnID*/0, /*Imm*/0,
        GIR_AddImm8, /*InsnID*/0, /*Imm*/0,
        GIR_ConstrainSelectedInstOperands, /*InsnID*/0,
        GIR_EraseFromParent, /*InsnID*/0,
        // GIR_Coverage, 10532,
        GIR_Done,
      // Label 5003: @358990
      GIM_Try, /*On fail goto*//*Label 5004*/ GIMT_Encode4(359136), // Rule ID 10535 //
        GIM_CheckFeatures, GIMT_Encode2(GIFBS_isGFX9Plus),
        GIM_CheckRegBankForClass, /*MI*/0, /*Op*/0, /*RC*/GIMT_Encode2(AMDGPU::VGPR_32RegClassID),
        GIM_RecordInsn, /*DefineMI*/1, /*MI*/0, /*OpIdx*/1, // MIs[1]
        GIM_CheckOpcode, /*MI*/1, GIMT_Encode2(TargetOpcode::G_FMINNUM_IEEE),
        GIM_CheckType, /*MI*/1, /*Op*/1, /*Type*/GILLT_s16,
        GIM_CheckType, /*MI*/1, /*Op*/2, /*Type*/GILLT_s16,
        GIM_RecordInsn, /*DefineMI*/2, /*MI*/0, /*OpIdx*/2, // MIs[2]
        GIM_CheckOpcode, /*MI*/2, GIMT_Encode2(TargetOpcode::G_FMINNUM_IEEE),
        GIM_CheckType, /*MI*/2, /*Op*/1, /*Type*/GILLT_s16,
        GIM_CheckType, /*MI*/2, /*Op*/2, /*Type*/GILLT_s16,
        GIM_RecordInsn, /*DefineMI*/3, /*MI*/2, /*OpIdx*/2, // MIs[3]
        GIM_CheckOpcode, /*MI*/3, GIMT_Encode2(TargetOpcode::G_FMAXNUM_IEEE),
        // MIs[3] VOP3Mods:src0:src0_mods
        GIM_CheckIsSameOperand, /*MI*/3, /*OpIdx*/1, /*OtherMI*/1, /*OtherOpIdx*/2,
        // MIs[3] VOP3Mods:src1:src1_mods
        GIM_CheckIsSameOperand, /*MI*/3, /*OpIdx*/2, /*OtherMI*/1, /*OtherOpIdx*/1,
        GIM_CheckCxxInsnPredicate, /*MI*/0, /*FnId*/GIMT_Encode2(GICXXPred_MI_Predicate_fmaxnum_like_nnan),
        GIM_CheckIsSafeToFold, /*InsnID*/1,
        GIM_CheckIsSafeToFold, /*InsnID*/2,
        GIM_CheckIsSafeToFold, /*InsnID*/3,
        GIM_CheckComplexPattern, /*MI*/1, /*Op*/1, /*Renderer*/GIMT_Encode2(0), GIMT_Encode2(GICP_gi_vop3mods),
        GIM_CheckComplexPattern, /*MI*/1, /*Op*/2, /*Renderer*/GIMT_Encode2(1), GIMT_Encode2(GICP_gi_vop3mods),
        GIM_CheckComplexPattern, /*MI*/2, /*Op*/1, /*Renderer*/GIMT_Encode2(2), GIMT_Encode2(GICP_gi_vop3mods),
        // (fmaxnum_ieee:{ *:[f16] } (fminnum_ieee:{ *:[f16] } (VOP3Mods:{ *:[f16] } f16:{ *:[f16] }:$src1, i32:{ *:[i32] }:$src1_mods), (VOP3Mods:{ *:[f16] } f16:{ *:[f16] }:$src0, i32:{ *:[i32] }:$src0_mods)), (fminnum_ieee:{ *:[f16] } (VOP3Mods:{ *:[f16] } f16:{ *:[f16] }:$src2, i32:{ *:[i32] }:$src2_mods), (fmaxnum_ieee:{ *:[f16] } (VOP3Mods:{ *:[f16] } f16:{ *:[f16] }:$src0, i32:{ *:[i32] }:$src0_mods), (VOP3Mods:{ *:[f16] } f16:{ *:[f16] }:$src1, i32:{ *:[i32] }:$src1_mods))))<<P:Predicate_fmaxnum_like_nnan>>  =>  (V_MED3_F16_e64:{ *:[f16] } ?:{ *:[i32] }:$src0_mods, ?:{ *:[f16] }:$src0, ?:{ *:[i32] }:$src1_mods, ?:{ *:[f16] }:$src1, ?:{ *:[i32] }:$src2_mods, ?:{ *:[f16] }:$src2, 0:{ *:[i1] })
        GIR_BuildMI, /*InsnID*/0, /*Opcode*/GIMT_Encode2(AMDGPU::V_MED3_F16_e64),
        GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/0, // DstI[vdst]
        GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(1), /*SubOperand*/1, // src0_mods
        GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(1), /*SubOperand*/0, // src0
        GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/1, // src1_mods
        GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/0, // src1
        GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(2), /*SubOperand*/1, // src2_mods
        GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(2), /*SubOperand*/0, // src2
        GIR_AddImm8, /*InsnID*/0, /*Imm*/0,
        GIR_AddImm8, /*InsnID*/0, /*Imm*/0,
        GIR_AddImm8, /*InsnID*/0, /*Imm*/0,
        GIR_ConstrainSelectedInstOperands, /*InsnID*/0,
        GIR_EraseFromParent, /*InsnID*/0,
        // GIR_Coverage, 10535,
        GIR_Done,
      // Label 5004: @359136
      GIM_Try, /*On fail goto*//*Label 5005*/ GIMT_Encode4(359282), // Rule ID 10536 //
        GIM_CheckFeatures, GIMT_Encode2(GIFBS_isGFX9Plus),
        GIM_CheckRegBankForClass, /*MI*/0, /*Op*/0, /*RC*/GIMT_Encode2(AMDGPU::VGPR_32RegClassID),
        GIM_RecordInsn, /*DefineMI*/1, /*MI*/0, /*OpIdx*/1, // MIs[1]
        GIM_CheckOpcode, /*MI*/1, GIMT_Encode2(TargetOpcode::G_FMINNUM_IEEE),
        GIM_CheckType, /*MI*/1, /*Op*/1, /*Type*/GILLT_s16,
        GIM_CheckType, /*MI*/1, /*Op*/2, /*Type*/GILLT_s16,
        GIM_RecordInsn, /*DefineMI*/2, /*MI*/0, /*OpIdx*/2, // MIs[2]
        GIM_CheckOpcode, /*MI*/2, GIMT_Encode2(TargetOpcode::G_FMINNUM_IEEE),
        GIM_CheckType, /*MI*/2, /*Op*/1, /*Type*/GILLT_s16,
        GIM_CheckType, /*MI*/2, /*Op*/2, /*Type*/GILLT_s16,
        GIM_RecordInsn, /*DefineMI*/3, /*MI*/2, /*OpIdx*/2, // MIs[3]
        GIM_CheckOpcode, /*MI*/3, GIMT_Encode2(TargetOpcode::G_FMAXNUM_IEEE),
        // MIs[3] VOP3Mods:src1:src1_mods
        GIM_CheckIsSameOperand, /*MI*/3, /*OpIdx*/1, /*OtherMI*/1, /*OtherOpIdx*/1,
        // MIs[3] VOP3Mods:src0:src0_mods
        GIM_CheckIsSameOperand, /*MI*/3, /*OpIdx*/2, /*OtherMI*/1, /*OtherOpIdx*/2,
        GIM_CheckCxxInsnPredicate, /*MI*/0, /*FnId*/GIMT_Encode2(GICXXPred_MI_Predicate_fmaxnum_like_nnan),
        GIM_CheckIsSafeToFold, /*InsnID*/1,
        GIM_CheckIsSafeToFold, /*InsnID*/2,
        GIM_CheckIsSafeToFold, /*InsnID*/3,
        GIM_CheckComplexPattern, /*MI*/1, /*Op*/1, /*Renderer*/GIMT_Encode2(0), GIMT_Encode2(GICP_gi_vop3mods),
        GIM_CheckComplexPattern, /*MI*/1, /*Op*/2, /*Renderer*/GIMT_Encode2(1), GIMT_Encode2(GICP_gi_vop3mods),
        GIM_CheckComplexPattern, /*MI*/2, /*Op*/1, /*Renderer*/GIMT_Encode2(2), GIMT_Encode2(GICP_gi_vop3mods),
        // (fmaxnum_ieee:{ *:[f16] } (fminnum_ieee:{ *:[f16] } (VOP3Mods:{ *:[f16] } f16:{ *:[f16] }:$src1, i32:{ *:[i32] }:$src1_mods), (VOP3Mods:{ *:[f16] } f16:{ *:[f16] }:$src0, i32:{ *:[i32] }:$src0_mods)), (fminnum_ieee:{ *:[f16] } (VOP3Mods:{ *:[f16] } f16:{ *:[f16] }:$src2, i32:{ *:[i32] }:$src2_mods), (fmaxnum_ieee:{ *:[f16] } (VOP3Mods:{ *:[f16] } f16:{ *:[f16] }:$src1, i32:{ *:[i32] }:$src1_mods), (VOP3Mods:{ *:[f16] } f16:{ *:[f16] }:$src0, i32:{ *:[i32] }:$src0_mods))))<<P:Predicate_fmaxnum_like_nnan>>  =>  (V_MED3_F16_e64:{ *:[f16] } ?:{ *:[i32] }:$src0_mods, ?:{ *:[f16] }:$src0, ?:{ *:[i32] }:$src1_mods, ?:{ *:[f16] }:$src1, ?:{ *:[i32] }:$src2_mods, ?:{ *:[f16] }:$src2, 0:{ *:[i1] })
        GIR_BuildMI, /*InsnID*/0, /*Opcode*/GIMT_Encode2(AMDGPU::V_MED3_F16_e64),
        GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/0, // DstI[vdst]
        GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(1), /*SubOperand*/1, // src0_mods
        GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(1), /*SubOperand*/0, // src0
        GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/1, // src1_mods
        GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/0, // src1
        GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(2), /*SubOperand*/1, // src2_mods
        GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(2), /*SubOperand*/0, // src2
        GIR_AddImm8, /*InsnID*/0, /*Imm*/0,
        GIR_AddImm8, /*InsnID*/0, /*Imm*/0,
        GIR_AddImm8, /*InsnID*/0, /*Imm*/0,
        GIR_ConstrainSelectedInstOperands, /*InsnID*/0,
        GIR_EraseFromParent, /*InsnID*/0,
        // GIR_Coverage, 10536,
        GIR_Done,
      // Label 5005: @359282
      GIM_Try, /*On fail goto*//*Label 5006*/ GIMT_Encode4(359428), // Rule ID 6537 //
        GIM_CheckFeatures, GIMT_Encode2(GIFBS_isGFX9Plus),
        GIM_CheckRegBankForClass, /*MI*/0, /*Op*/0, /*RC*/GIMT_Encode2(AMDGPU::VGPR_32RegClassID),
        GIM_RecordInsn, /*DefineMI*/1, /*MI*/0, /*OpIdx*/1, // MIs[1]
        GIM_CheckOpcode, /*MI*/1, GIMT_Encode2(TargetOpcode::G_FMINNUM_IEEE),
        GIM_CheckType, /*MI*/1, /*Op*/1, /*Type*/GILLT_s16,
        GIM_CheckType, /*MI*/1, /*Op*/2, /*Type*/GILLT_s16,
        GIM_RecordInsn, /*DefineMI*/2, /*MI*/0, /*OpIdx*/2, // MIs[2]
        GIM_CheckOpcode, /*MI*/2, GIMT_Encode2(TargetOpcode::G_FMINNUM_IEEE),
        GIM_CheckType, /*MI*/2, /*Op*/1, /*Type*/GILLT_s16,
        GIM_CheckType, /*MI*/2, /*Op*/2, /*Type*/GILLT_s16,
        GIM_RecordInsn, /*DefineMI*/3, /*MI*/2, /*OpIdx*/1, // MIs[3]
        GIM_CheckOpcode, /*MI*/3, GIMT_Encode2(TargetOpcode::G_FMAXNUM),
        // MIs[3] VOP3Mods:src0:src0_mods
        GIM_CheckIsSameOperand, /*MI*/3, /*OpIdx*/1, /*OtherMI*/1, /*OtherOpIdx*/1,
        // MIs[3] VOP3Mods:src1:src1_mods
        GIM_CheckIsSameOperand, /*MI*/3, /*OpIdx*/2, /*OtherMI*/1, /*OtherOpIdx*/2,
        GIM_CheckCxxInsnPredicate, /*MI*/0, /*FnId*/GIMT_Encode2(GICXXPred_MI_Predicate_fmaxnum_like_nnan),
        GIM_CheckIsSafeToFold, /*InsnID*/1,
        GIM_CheckIsSafeToFold, /*InsnID*/2,
        GIM_CheckIsSafeToFold, /*InsnID*/3,
        GIM_CheckComplexPattern, /*MI*/1, /*Op*/1, /*Renderer*/GIMT_Encode2(0), GIMT_Encode2(GICP_gi_vop3mods),
        GIM_CheckComplexPattern, /*MI*/1, /*Op*/2, /*Renderer*/GIMT_Encode2(1), GIMT_Encode2(GICP_gi_vop3mods),
        GIM_CheckComplexPattern, /*MI*/2, /*Op*/2, /*Renderer*/GIMT_Encode2(2), GIMT_Encode2(GICP_gi_vop3mods),
        // (fmaxnum_ieee:{ *:[f16] } (fminnum_ieee:{ *:[f16] } (VOP3Mods:{ *:[f16] } f16:{ *:[f16] }:$src0, i32:{ *:[i32] }:$src0_mods), (VOP3Mods:{ *:[f16] } f16:{ *:[f16] }:$src1, i32:{ *:[i32] }:$src1_mods)), (fminnum_ieee:{ *:[f16] } (fmaxnum:{ *:[f16] } (VOP3Mods:{ *:[f16] } f16:{ *:[f16] }:$src0, i32:{ *:[i32] }:$src0_mods), (VOP3Mods:{ *:[f16] } f16:{ *:[f16] }:$src1, i32:{ *:[i32] }:$src1_mods)), (VOP3Mods:{ *:[f16] } f16:{ *:[f16] }:$src2, i32:{ *:[i32] }:$src2_mods)))<<P:Predicate_fmaxnum_like_nnan>>  =>  (V_MED3_F16_e64:{ *:[f16] } ?:{ *:[i32] }:$src0_mods, ?:{ *:[f16] }:$src0, ?:{ *:[i32] }:$src1_mods, ?:{ *:[f16] }:$src1, ?:{ *:[i32] }:$src2_mods, ?:{ *:[f16] }:$src2, 0:{ *:[i1] })
        GIR_BuildMI, /*InsnID*/0, /*Opcode*/GIMT_Encode2(AMDGPU::V_MED3_F16_e64),
        GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/0, // DstI[vdst]
        GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/1, // src0_mods
        GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/0, // src0
        GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(1), /*SubOperand*/1, // src1_mods
        GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(1), /*SubOperand*/0, // src1
        GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(2), /*SubOperand*/1, // src2_mods
        GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(2), /*SubOperand*/0, // src2
        GIR_AddImm8, /*InsnID*/0, /*Imm*/0,
        GIR_AddImm8, /*InsnID*/0, /*Imm*/0,
        GIR_AddImm8, /*InsnID*/0, /*Imm*/0,
        GIR_ConstrainSelectedInstOperands, /*InsnID*/0,
        GIR_EraseFromParent, /*InsnID*/0,
        // GIR_Coverage, 6537,
        GIR_Done,
      // Label 5006: @359428
      GIM_Try, /*On fail goto*//*Label 5007*/ GIMT_Encode4(359574), // Rule ID 10545 //
        GIM_CheckFeatures, GIMT_Encode2(GIFBS_isGFX9Plus),
        GIM_CheckRegBankForClass, /*MI*/0, /*Op*/0, /*RC*/GIMT_Encode2(AMDGPU::VGPR_32RegClassID),
        GIM_RecordInsn, /*DefineMI*/1, /*MI*/0, /*OpIdx*/1, // MIs[1]
        GIM_CheckOpcode, /*MI*/1, GIMT_Encode2(TargetOpcode::G_FMINNUM_IEEE),
        GIM_CheckType, /*MI*/1, /*Op*/1, /*Type*/GILLT_s16,
        GIM_CheckType, /*MI*/1, /*Op*/2, /*Type*/GILLT_s16,
        GIM_RecordInsn, /*DefineMI*/2, /*MI*/0, /*OpIdx*/2, // MIs[2]
        GIM_CheckOpcode, /*MI*/2, GIMT_Encode2(TargetOpcode::G_FMINNUM_IEEE),
        GIM_CheckType, /*MI*/2, /*Op*/1, /*Type*/GILLT_s16,
        GIM_CheckType, /*MI*/2, /*Op*/2, /*Type*/GILLT_s16,
        GIM_RecordInsn, /*DefineMI*/3, /*MI*/2, /*OpIdx*/1, // MIs[3]
        GIM_CheckOpcode, /*MI*/3, GIMT_Encode2(TargetOpcode::G_FMAXNUM),
        // MIs[3] VOP3Mods:src1:src1_mods
        GIM_CheckIsSameOperand, /*MI*/3, /*OpIdx*/1, /*OtherMI*/1, /*OtherOpIdx*/2,
        // MIs[3] VOP3Mods:src0:src0_mods
        GIM_CheckIsSameOperand, /*MI*/3, /*OpIdx*/2, /*OtherMI*/1, /*OtherOpIdx*/1,
        GIM_CheckCxxInsnPredicate, /*MI*/0, /*FnId*/GIMT_Encode2(GICXXPred_MI_Predicate_fmaxnum_like_nnan),
        GIM_CheckIsSafeToFold, /*InsnID*/1,
        GIM_CheckIsSafeToFold, /*InsnID*/2,
        GIM_CheckIsSafeToFold, /*InsnID*/3,
        GIM_CheckComplexPattern, /*MI*/1, /*Op*/1, /*Renderer*/GIMT_Encode2(0), GIMT_Encode2(GICP_gi_vop3mods),
        GIM_CheckComplexPattern, /*MI*/1, /*Op*/2, /*Renderer*/GIMT_Encode2(1), GIMT_Encode2(GICP_gi_vop3mods),
        GIM_CheckComplexPattern, /*MI*/2, /*Op*/2, /*Renderer*/GIMT_Encode2(2), GIMT_Encode2(GICP_gi_vop3mods),
        // (fmaxnum_ieee:{ *:[f16] } (fminnum_ieee:{ *:[f16] } (VOP3Mods:{ *:[f16] } f16:{ *:[f16] }:$src0, i32:{ *:[i32] }:$src0_mods), (VOP3Mods:{ *:[f16] } f16:{ *:[f16] }:$src1, i32:{ *:[i32] }:$src1_mods)), (fminnum_ieee:{ *:[f16] } (fmaxnum:{ *:[f16] } (VOP3Mods:{ *:[f16] } f16:{ *:[f16] }:$src1, i32:{ *:[i32] }:$src1_mods), (VOP3Mods:{ *:[f16] } f16:{ *:[f16] }:$src0, i32:{ *:[i32] }:$src0_mods)), (VOP3Mods:{ *:[f16] } f16:{ *:[f16] }:$src2, i32:{ *:[i32] }:$src2_mods)))<<P:Predicate_fmaxnum_like_nnan>>  =>  (V_MED3_F16_e64:{ *:[f16] } ?:{ *:[i32] }:$src0_mods, ?:{ *:[f16] }:$src0, ?:{ *:[i32] }:$src1_mods, ?:{ *:[f16] }:$src1, ?:{ *:[i32] }:$src2_mods, ?:{ *:[f16] }:$src2, 0:{ *:[i1] })
        GIR_BuildMI, /*InsnID*/0, /*Opcode*/GIMT_Encode2(AMDGPU::V_MED3_F16_e64),
        GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/0, // DstI[vdst]
        GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/1, // src0_mods
        GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/0, // src0
        GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(1), /*SubOperand*/1, // src1_mods
        GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(1), /*SubOperand*/0, // src1
        GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(2), /*SubOperand*/1, // src2_mods
        GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(2), /*SubOperand*/0, // src2
        GIR_AddImm8, /*InsnID*/0, /*Imm*/0,
        GIR_AddImm8, /*InsnID*/0, /*Imm*/0,
        GIR_AddImm8, /*InsnID*/0, /*Imm*/0,
        GIR_ConstrainSelectedInstOperands, /*InsnID*/0,
        GIR_EraseFromParent, /*InsnID*/0,
        // GIR_Coverage, 10545,
        GIR_Done,
      // Label 5007: @359574
      GIM_Try, /*On fail goto*//*Label 5008*/ GIMT_Encode4(359720), // Rule ID 10548 //
        GIM_CheckFeatures, GIMT_Encode2(GIFBS_isGFX9Plus),
        GIM_CheckRegBankForClass, /*MI*/0, /*Op*/0, /*RC*/GIMT_Encode2(AMDGPU::VGPR_32RegClassID),
        GIM_RecordInsn, /*DefineMI*/1, /*MI*/0, /*OpIdx*/1, // MIs[1]
        GIM_CheckOpcode, /*MI*/1, GIMT_Encode2(TargetOpcode::G_FMINNUM_IEEE),
        GIM_CheckType, /*MI*/1, /*Op*/1, /*Type*/GILLT_s16,
        GIM_CheckType, /*MI*/1, /*Op*/2, /*Type*/GILLT_s16,
        GIM_RecordInsn, /*DefineMI*/2, /*MI*/0, /*OpIdx*/2, // MIs[2]
        GIM_CheckOpcode, /*MI*/2, GIMT_Encode2(TargetOpcode::G_FMINNUM_IEEE),
        GIM_CheckType, /*MI*/2, /*Op*/1, /*Type*/GILLT_s16,
        GIM_CheckType, /*MI*/2, /*Op*/2, /*Type*/GILLT_s16,
        GIM_RecordInsn, /*DefineMI*/3, /*MI*/2, /*OpIdx*/1, // MIs[3]
        GIM_CheckOpcode, /*MI*/3, GIMT_Encode2(TargetOpcode::G_FMAXNUM),
        // MIs[3] VOP3Mods:src0:src0_mods
        GIM_CheckIsSameOperand, /*MI*/3, /*OpIdx*/1, /*OtherMI*/1, /*OtherOpIdx*/2,
        // MIs[3] VOP3Mods:src1:src1_mods
        GIM_CheckIsSameOperand, /*MI*/3, /*OpIdx*/2, /*OtherMI*/1, /*OtherOpIdx*/1,
        GIM_CheckCxxInsnPredicate, /*MI*/0, /*FnId*/GIMT_Encode2(GICXXPred_MI_Predicate_fmaxnum_like_nnan),
        GIM_CheckIsSafeToFold, /*InsnID*/1,
        GIM_CheckIsSafeToFold, /*InsnID*/2,
        GIM_CheckIsSafeToFold, /*InsnID*/3,
        GIM_CheckComplexPattern, /*MI*/1, /*Op*/1, /*Renderer*/GIMT_Encode2(0), GIMT_Encode2(GICP_gi_vop3mods),
        GIM_CheckComplexPattern, /*MI*/1, /*Op*/2, /*Renderer*/GIMT_Encode2(1), GIMT_Encode2(GICP_gi_vop3mods),
        GIM_CheckComplexPattern, /*MI*/2, /*Op*/2, /*Renderer*/GIMT_Encode2(2), GIMT_Encode2(GICP_gi_vop3mods),
        // (fmaxnum_ieee:{ *:[f16] } (fminnum_ieee:{ *:[f16] } (VOP3Mods:{ *:[f16] } f16:{ *:[f16] }:$src1, i32:{ *:[i32] }:$src1_mods), (VOP3Mods:{ *:[f16] } f16:{ *:[f16] }:$src0, i32:{ *:[i32] }:$src0_mods)), (fminnum_ieee:{ *:[f16] } (fmaxnum:{ *:[f16] } (VOP3Mods:{ *:[f16] } f16:{ *:[f16] }:$src0, i32:{ *:[i32] }:$src0_mods), (VOP3Mods:{ *:[f16] } f16:{ *:[f16] }:$src1, i32:{ *:[i32] }:$src1_mods)), (VOP3Mods:{ *:[f16] } f16:{ *:[f16] }:$src2, i32:{ *:[i32] }:$src2_mods)))<<P:Predicate_fmaxnum_like_nnan>>  =>  (V_MED3_F16_e64:{ *:[f16] } ?:{ *:[i32] }:$src0_mods, ?:{ *:[f16] }:$src0, ?:{ *:[i32] }:$src1_mods, ?:{ *:[f16] }:$src1, ?:{ *:[i32] }:$src2_mods, ?:{ *:[f16] }:$src2, 0:{ *:[i1] })
        GIR_BuildMI, /*InsnID*/0, /*Opcode*/GIMT_Encode2(AMDGPU::V_MED3_F16_e64),
        GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/0, // DstI[vdst]
        GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(1), /*SubOperand*/1, // src0_mods
        GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(1), /*SubOperand*/0, // src0
        GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/1, // src1_mods
        GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/0, // src1
        GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(2), /*SubOperand*/1, // src2_mods
        GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(2), /*SubOperand*/0, // src2
        GIR_AddImm8, /*InsnID*/0, /*Imm*/0,
        GIR_AddImm8, /*InsnID*/0, /*Imm*/0,
        GIR_AddImm8, /*InsnID*/0, /*Imm*/0,
        GIR_ConstrainSelectedInstOperands, /*InsnID*/0,
        GIR_EraseFromParent, /*InsnID*/0,
        // GIR_Coverage, 10548,
        GIR_Done,
      // Label 5008: @359720
      GIM_Try, /*On fail goto*//*Label 5009*/ GIMT_Encode4(359866), // Rule ID 10549 //
        GIM_CheckFeatures, GIMT_Encode2(GIFBS_isGFX9Plus),
        GIM_CheckRegBankForClass, /*MI*/0, /*Op*/0, /*RC*/GIMT_Encode2(AMDGPU::VGPR_32RegClassID),
        GIM_RecordInsn, /*DefineMI*/1, /*MI*/0, /*OpIdx*/1, // MIs[1]
        GIM_CheckOpcode, /*MI*/1, GIMT_Encode2(TargetOpcode::G_FMINNUM_IEEE),
        GIM_CheckType, /*MI*/1, /*Op*/1, /*Type*/GILLT_s16,
        GIM_CheckType, /*MI*/1, /*Op*/2, /*Type*/GILLT_s16,
        GIM_RecordInsn, /*DefineMI*/2, /*MI*/0, /*OpIdx*/2, // MIs[2]
        GIM_CheckOpcode, /*MI*/2, GIMT_Encode2(TargetOpcode::G_FMINNUM_IEEE),
        GIM_CheckType, /*MI*/2, /*Op*/1, /*Type*/GILLT_s16,
        GIM_CheckType, /*MI*/2, /*Op*/2, /*Type*/GILLT_s16,
        GIM_RecordInsn, /*DefineMI*/3, /*MI*/2, /*OpIdx*/1, // MIs[3]
        GIM_CheckOpcode, /*MI*/3, GIMT_Encode2(TargetOpcode::G_FMAXNUM),
        // MIs[3] VOP3Mods:src1:src1_mods
        GIM_CheckIsSameOperand, /*MI*/3, /*OpIdx*/1, /*OtherMI*/1, /*OtherOpIdx*/1,
        // MIs[3] VOP3Mods:src0:src0_mods
        GIM_CheckIsSameOperand, /*MI*/3, /*OpIdx*/2, /*OtherMI*/1, /*OtherOpIdx*/2,
        GIM_CheckCxxInsnPredicate, /*MI*/0, /*FnId*/GIMT_Encode2(GICXXPred_MI_Predicate_fmaxnum_like_nnan),
        GIM_CheckIsSafeToFold, /*InsnID*/1,
        GIM_CheckIsSafeToFold, /*InsnID*/2,
        GIM_CheckIsSafeToFold, /*InsnID*/3,
        GIM_CheckComplexPattern, /*MI*/1, /*Op*/1, /*Renderer*/GIMT_Encode2(0), GIMT_Encode2(GICP_gi_vop3mods),
        GIM_CheckComplexPattern, /*MI*/1, /*Op*/2, /*Renderer*/GIMT_Encode2(1), GIMT_Encode2(GICP_gi_vop3mods),
        GIM_CheckComplexPattern, /*MI*/2, /*Op*/2, /*Renderer*/GIMT_Encode2(2), GIMT_Encode2(GICP_gi_vop3mods),
        // (fmaxnum_ieee:{ *:[f16] } (fminnum_ieee:{ *:[f16] } (VOP3Mods:{ *:[f16] } f16:{ *:[f16] }:$src1, i32:{ *:[i32] }:$src1_mods), (VOP3Mods:{ *:[f16] } f16:{ *:[f16] }:$src0, i32:{ *:[i32] }:$src0_mods)), (fminnum_ieee:{ *:[f16] } (fmaxnum:{ *:[f16] } (VOP3Mods:{ *:[f16] } f16:{ *:[f16] }:$src1, i32:{ *:[i32] }:$src1_mods), (VOP3Mods:{ *:[f16] } f16:{ *:[f16] }:$src0, i32:{ *:[i32] }:$src0_mods)), (VOP3Mods:{ *:[f16] } f16:{ *:[f16] }:$src2, i32:{ *:[i32] }:$src2_mods)))<<P:Predicate_fmaxnum_like_nnan>>  =>  (V_MED3_F16_e64:{ *:[f16] } ?:{ *:[i32] }:$src0_mods, ?:{ *:[f16] }:$src0, ?:{ *:[i32] }:$src1_mods, ?:{ *:[f16] }:$src1, ?:{ *:[i32] }:$src2_mods, ?:{ *:[f16] }:$src2, 0:{ *:[i1] })
        GIR_BuildMI, /*InsnID*/0, /*Opcode*/GIMT_Encode2(AMDGPU::V_MED3_F16_e64),
        GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/0, // DstI[vdst]
        GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(1), /*SubOperand*/1, // src0_mods
        GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(1), /*SubOperand*/0, // src0
        GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/1, // src1_mods
        GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/0, // src1
        GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(2), /*SubOperand*/1, // src2_mods
        GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(2), /*SubOperand*/0, // src2
        GIR_AddImm8, /*InsnID*/0, /*Imm*/0,
        GIR_AddImm8, /*InsnID*/0, /*Imm*/0,
        GIR_AddImm8, /*InsnID*/0, /*Imm*/0,
        GIR_ConstrainSelectedInstOperands, /*InsnID*/0,
        GIR_EraseFromParent, /*InsnID*/0,
        // GIR_Coverage, 10549,
        GIR_Done,
      // Label 5009: @359866
      GIM_Try, /*On fail goto*//*Label 5010*/ GIMT_Encode4(360012), // Rule ID 6536 //
        GIM_CheckFeatures, GIMT_Encode2(GIFBS_isGFX9Plus),
        GIM_CheckRegBankForClass, /*MI*/0, /*Op*/0, /*RC*/GIMT_Encode2(AMDGPU::VGPR_32RegClassID),
        GIM_RecordInsn, /*DefineMI*/1, /*MI*/0, /*OpIdx*/1, // MIs[1]
        GIM_CheckOpcode, /*MI*/1, GIMT_Encode2(TargetOpcode::G_FMINNUM_IEEE),
        GIM_CheckType, /*MI*/1, /*Op*/1, /*Type*/GILLT_s16,
        GIM_CheckType, /*MI*/1, /*Op*/2, /*Type*/GILLT_s16,
        GIM_RecordInsn, /*DefineMI*/2, /*MI*/0, /*OpIdx*/2, // MIs[2]
        GIM_CheckOpcode, /*MI*/2, GIMT_Encode2(TargetOpcode::G_FMINNUM_IEEE),
        GIM_CheckType, /*MI*/2, /*Op*/1, /*Type*/GILLT_s16,
        GIM_CheckType, /*MI*/2, /*Op*/2, /*Type*/GILLT_s16,
        GIM_RecordInsn, /*DefineMI*/3, /*MI*/2, /*OpIdx*/1, // MIs[3]
        GIM_CheckOpcode, /*MI*/3, GIMT_Encode2(TargetOpcode::G_FMAXNUM_IEEE),
        // MIs[3] VOP3Mods:src0:src0_mods
        GIM_CheckIsSameOperand, /*MI*/3, /*OpIdx*/1, /*OtherMI*/1, /*OtherOpIdx*/1,
        // MIs[3] VOP3Mods:src1:src1_mods
        GIM_CheckIsSameOperand, /*MI*/3, /*OpIdx*/2, /*OtherMI*/1, /*OtherOpIdx*/2,
        GIM_CheckCxxInsnPredicate, /*MI*/0, /*FnId*/GIMT_Encode2(GICXXPred_MI_Predicate_fmaxnum_like_nnan),
        GIM_CheckIsSafeToFold, /*InsnID*/1,
        GIM_CheckIsSafeToFold, /*InsnID*/2,
        GIM_CheckIsSafeToFold, /*InsnID*/3,
        GIM_CheckComplexPattern, /*MI*/1, /*Op*/1, /*Renderer*/GIMT_Encode2(0), GIMT_Encode2(GICP_gi_vop3mods),
        GIM_CheckComplexPattern, /*MI*/1, /*Op*/2, /*Renderer*/GIMT_Encode2(1), GIMT_Encode2(GICP_gi_vop3mods),
        GIM_CheckComplexPattern, /*MI*/2, /*Op*/2, /*Renderer*/GIMT_Encode2(2), GIMT_Encode2(GICP_gi_vop3mods),
        // (fmaxnum_ieee:{ *:[f16] } (fminnum_ieee:{ *:[f16] } (VOP3Mods:{ *:[f16] } f16:{ *:[f16] }:$src0, i32:{ *:[i32] }:$src0_mods), (VOP3Mods:{ *:[f16] } f16:{ *:[f16] }:$src1, i32:{ *:[i32] }:$src1_mods)), (fminnum_ieee:{ *:[f16] } (fmaxnum_ieee:{ *:[f16] } (VOP3Mods:{ *:[f16] } f16:{ *:[f16] }:$src0, i32:{ *:[i32] }:$src0_mods), (VOP3Mods:{ *:[f16] } f16:{ *:[f16] }:$src1, i32:{ *:[i32] }:$src1_mods)), (VOP3Mods:{ *:[f16] } f16:{ *:[f16] }:$src2, i32:{ *:[i32] }:$src2_mods)))<<P:Predicate_fmaxnum_like_nnan>>  =>  (V_MED3_F16_e64:{ *:[f16] } ?:{ *:[i32] }:$src0_mods, ?:{ *:[f16] }:$src0, ?:{ *:[i32] }:$src1_mods, ?:{ *:[f16] }:$src1, ?:{ *:[i32] }:$src2_mods, ?:{ *:[f16] }:$src2, 0:{ *:[i1] })
        GIR_BuildMI, /*InsnID*/0, /*Opcode*/GIMT_Encode2(AMDGPU::V_MED3_F16_e64),
        GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/0, // DstI[vdst]
        GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/1, // src0_mods
        GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/0, // src0
        GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(1), /*SubOperand*/1, // src1_mods
        GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(1), /*SubOperand*/0, // src1
        GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(2), /*SubOperand*/1, // src2_mods
        GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(2), /*SubOperand*/0, // src2
        GIR_AddImm8, /*InsnID*/0, /*Imm*/0,
        GIR_AddImm8, /*InsnID*/0, /*Imm*/0,
        GIR_AddImm8, /*InsnID*/0, /*Imm*/0,
        GIR_ConstrainSelectedInstOperands, /*InsnID*/0,
        GIR_EraseFromParent, /*InsnID*/0,
        // GIR_Coverage, 6536,
        GIR_Done,
      // Label 5010: @360012
      GIM_Try, /*On fail goto*//*Label 5011*/ GIMT_Encode4(360158), // Rule ID 10530 //
        GIM_CheckFeatures, GIMT_Encode2(GIFBS_isGFX9Plus),
        GIM_CheckRegBankForClass, /*MI*/0, /*Op*/0, /*RC*/GIMT_Encode2(AMDGPU::VGPR_32RegClassID),
        GIM_RecordInsn, /*DefineMI*/1, /*MI*/0, /*OpIdx*/1, // MIs[1]
        GIM_CheckOpcode, /*MI*/1, GIMT_Encode2(TargetOpcode::G_FMINNUM_IEEE),
        GIM_CheckType, /*MI*/1, /*Op*/1, /*Type*/GILLT_s16,
        GIM_CheckType, /*MI*/1, /*Op*/2, /*Type*/GILLT_s16,
        GIM_RecordInsn, /*DefineMI*/2, /*MI*/0, /*OpIdx*/2, // MIs[2]
        GIM_CheckOpcode, /*MI*/2, GIMT_Encode2(TargetOpcode::G_FMINNUM_IEEE),
        GIM_CheckType, /*MI*/2, /*Op*/1, /*Type*/GILLT_s16,
        GIM_CheckType, /*MI*/2, /*Op*/2, /*Type*/GILLT_s16,
        GIM_RecordInsn, /*DefineMI*/3, /*MI*/2, /*OpIdx*/1, // MIs[3]
        GIM_CheckOpcode, /*MI*/3, GIMT_Encode2(TargetOpcode::G_FMAXNUM_IEEE),
        // MIs[3] VOP3Mods:src1:src1_mods
        GIM_CheckIsSameOperand, /*MI*/3, /*OpIdx*/1, /*OtherMI*/1, /*OtherOpIdx*/2,
        // MIs[3] VOP3Mods:src0:src0_mods
        GIM_CheckIsSameOperand, /*MI*/3, /*OpIdx*/2, /*OtherMI*/1, /*OtherOpIdx*/1,
        GIM_CheckCxxInsnPredicate, /*MI*/0, /*FnId*/GIMT_Encode2(GICXXPred_MI_Predicate_fmaxnum_like_nnan),
        GIM_CheckIsSafeToFold, /*InsnID*/1,
        GIM_CheckIsSafeToFold, /*InsnID*/2,
        GIM_CheckIsSafeToFold, /*InsnID*/3,
        GIM_CheckComplexPattern, /*MI*/1, /*Op*/1, /*Renderer*/GIMT_Encode2(0), GIMT_Encode2(GICP_gi_vop3mods),
        GIM_CheckComplexPattern, /*MI*/1, /*Op*/2, /*Renderer*/GIMT_Encode2(1), GIMT_Encode2(GICP_gi_vop3mods),
        GIM_CheckComplexPattern, /*MI*/2, /*Op*/2, /*Renderer*/GIMT_Encode2(2), GIMT_Encode2(GICP_gi_vop3mods),
        // (fmaxnum_ieee:{ *:[f16] } (fminnum_ieee:{ *:[f16] } (VOP3Mods:{ *:[f16] } f16:{ *:[f16] }:$src0, i32:{ *:[i32] }:$src0_mods), (VOP3Mods:{ *:[f16] } f16:{ *:[f16] }:$src1, i32:{ *:[i32] }:$src1_mods)), (fminnum_ieee:{ *:[f16] } (fmaxnum_ieee:{ *:[f16] } (VOP3Mods:{ *:[f16] } f16:{ *:[f16] }:$src1, i32:{ *:[i32] }:$src1_mods), (VOP3Mods:{ *:[f16] } f16:{ *:[f16] }:$src0, i32:{ *:[i32] }:$src0_mods)), (VOP3Mods:{ *:[f16] } f16:{ *:[f16] }:$src2, i32:{ *:[i32] }:$src2_mods)))<<P:Predicate_fmaxnum_like_nnan>>  =>  (V_MED3_F16_e64:{ *:[f16] } ?:{ *:[i32] }:$src0_mods, ?:{ *:[f16] }:$src0, ?:{ *:[i32] }:$src1_mods, ?:{ *:[f16] }:$src1, ?:{ *:[i32] }:$src2_mods, ?:{ *:[f16] }:$src2, 0:{ *:[i1] })
        GIR_BuildMI, /*InsnID*/0, /*Opcode*/GIMT_Encode2(AMDGPU::V_MED3_F16_e64),
        GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/0, // DstI[vdst]
        GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/1, // src0_mods
        GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/0, // src0
        GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(1), /*SubOperand*/1, // src1_mods
        GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(1), /*SubOperand*/0, // src1
        GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(2), /*SubOperand*/1, // src2_mods
        GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(2), /*SubOperand*/0, // src2
        GIR_AddImm8, /*InsnID*/0, /*Imm*/0,
        GIR_AddImm8, /*InsnID*/0, /*Imm*/0,
        GIR_AddImm8, /*InsnID*/0, /*Imm*/0,
        GIR_ConstrainSelectedInstOperands, /*InsnID*/0,
        GIR_EraseFromParent, /*InsnID*/0,
        // GIR_Coverage, 10530,
        GIR_Done,
      // Label 5011: @360158
      GIM_Try, /*On fail goto*//*Label 5012*/ GIMT_Encode4(360304), // Rule ID 10533 //
        GIM_CheckFeatures, GIMT_Encode2(GIFBS_isGFX9Plus),
        GIM_CheckRegBankForClass, /*MI*/0, /*Op*/0, /*RC*/GIMT_Encode2(AMDGPU::VGPR_32RegClassID),
        GIM_RecordInsn, /*DefineMI*/1, /*MI*/0, /*OpIdx*/1, // MIs[1]
        GIM_CheckOpcode, /*MI*/1, GIMT_Encode2(TargetOpcode::G_FMINNUM_IEEE),
        GIM_CheckType, /*MI*/1, /*Op*/1, /*Type*/GILLT_s16,
        GIM_CheckType, /*MI*/1, /*Op*/2, /*Type*/GILLT_s16,
        GIM_RecordInsn, /*DefineMI*/2, /*MI*/0, /*OpIdx*/2, // MIs[2]
        GIM_CheckOpcode, /*MI*/2, GIMT_Encode2(TargetOpcode::G_FMINNUM_IEEE),
        GIM_CheckType, /*MI*/2, /*Op*/1, /*Type*/GILLT_s16,
        GIM_CheckType, /*MI*/2, /*Op*/2, /*Type*/GILLT_s16,
        GIM_RecordInsn, /*DefineMI*/3, /*MI*/2, /*OpIdx*/1, // MIs[3]
        GIM_CheckOpcode, /*MI*/3, GIMT_Encode2(TargetOpcode::G_FMAXNUM_IEEE),
        // MIs[3] VOP3Mods:src0:src0_mods
        GIM_CheckIsSameOperand, /*MI*/3, /*OpIdx*/1, /*OtherMI*/1, /*OtherOpIdx*/2,
        // MIs[3] VOP3Mods:src1:src1_mods
        GIM_CheckIsSameOperand, /*MI*/3, /*OpIdx*/2, /*OtherMI*/1, /*OtherOpIdx*/1,
        GIM_CheckCxxInsnPredicate, /*MI*/0, /*FnId*/GIMT_Encode2(GICXXPred_MI_Predicate_fmaxnum_like_nnan),
        GIM_CheckIsSafeToFold, /*InsnID*/1,
        GIM_CheckIsSafeToFold, /*InsnID*/2,
        GIM_CheckIsSafeToFold, /*InsnID*/3,
        GIM_CheckComplexPattern, /*MI*/1, /*Op*/1, /*Renderer*/GIMT_Encode2(0), GIMT_Encode2(GICP_gi_vop3mods),
        GIM_CheckComplexPattern, /*MI*/1, /*Op*/2, /*Renderer*/GIMT_Encode2(1), GIMT_Encode2(GICP_gi_vop3mods),
        GIM_CheckComplexPattern, /*MI*/2, /*Op*/2, /*Renderer*/GIMT_Encode2(2), GIMT_Encode2(GICP_gi_vop3mods),
        // (fmaxnum_ieee:{ *:[f16] } (fminnum_ieee:{ *:[f16] } (VOP3Mods:{ *:[f16] } f16:{ *:[f16] }:$src1, i32:{ *:[i32] }:$src1_mods), (VOP3Mods:{ *:[f16] } f16:{ *:[f16] }:$src0, i32:{ *:[i32] }:$src0_mods)), (fminnum_ieee:{ *:[f16] } (fmaxnum_ieee:{ *:[f16] } (VOP3Mods:{ *:[f16] } f16:{ *:[f16] }:$src0, i32:{ *:[i32] }:$src0_mods), (VOP3Mods:{ *:[f16] } f16:{ *:[f16] }:$src1, i32:{ *:[i32] }:$src1_mods)), (VOP3Mods:{ *:[f16] } f16:{ *:[f16] }:$src2, i32:{ *:[i32] }:$src2_mods)))<<P:Predicate_fmaxnum_like_nnan>>  =>  (V_MED3_F16_e64:{ *:[f16] } ?:{ *:[i32] }:$src0_mods, ?:{ *:[f16] }:$src0, ?:{ *:[i32] }:$src1_mods, ?:{ *:[f16] }:$src1, ?:{ *:[i32] }:$src2_mods, ?:{ *:[f16] }:$src2, 0:{ *:[i1] })
        GIR_BuildMI, /*InsnID*/0, /*Opcode*/GIMT_Encode2(AMDGPU::V_MED3_F16_e64),
        GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/0, // DstI[vdst]
        GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(1), /*SubOperand*/1, // src0_mods
        GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(1), /*SubOperand*/0, // src0
        GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/1, // src1_mods
        GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/0, // src1
        GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(2), /*SubOperand*/1, // src2_mods
        GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(2), /*SubOperand*/0, // src2
        GIR_AddImm8, /*InsnID*/0, /*Imm*/0,
        GIR_AddImm8, /*InsnID*/0, /*Imm*/0,
        GIR_AddImm8, /*InsnID*/0, /*Imm*/0,
        GIR_ConstrainSelectedInstOperands, /*InsnID*/0,
        GIR_EraseFromParent, /*InsnID*/0,
        // GIR_Coverage, 10533,
        GIR_Done,
      // Label 5012: @360304
      GIM_Try, /*On fail goto*//*Label 5013*/ GIMT_Encode4(360450), // Rule ID 10534 //
        GIM_CheckFeatures, GIMT_Encode2(GIFBS_isGFX9Plus),
        GIM_CheckRegBankForClass, /*MI*/0, /*Op*/0, /*RC*/GIMT_Encode2(AMDGPU::VGPR_32RegClassID),
        GIM_RecordInsn, /*DefineMI*/1, /*MI*/0, /*OpIdx*/1, // MIs[1]
        GIM_CheckOpcode, /*MI*/1, GIMT_Encode2(TargetOpcode::G_FMINNUM_IEEE),
        GIM_CheckType, /*MI*/1, /*Op*/1, /*Type*/GILLT_s16,
        GIM_CheckType, /*MI*/1, /*Op*/2, /*Type*/GILLT_s16,
        GIM_RecordInsn, /*DefineMI*/2, /*MI*/0, /*OpIdx*/2, // MIs[2]
        GIM_CheckOpcode, /*MI*/2, GIMT_Encode2(TargetOpcode::G_FMINNUM_IEEE),
        GIM_CheckType, /*MI*/2, /*Op*/1, /*Type*/GILLT_s16,
        GIM_CheckType, /*MI*/2, /*Op*/2, /*Type*/GILLT_s16,
        GIM_RecordInsn, /*DefineMI*/3, /*MI*/2, /*OpIdx*/1, // MIs[3]
        GIM_CheckOpcode, /*MI*/3, GIMT_Encode2(TargetOpcode::G_FMAXNUM_IEEE),
        // MIs[3] VOP3Mods:src1:src1_mods
        GIM_CheckIsSameOperand, /*MI*/3, /*OpIdx*/1, /*OtherMI*/1, /*OtherOpIdx*/1,
        // MIs[3] VOP3Mods:src0:src0_mods
        GIM_CheckIsSameOperand, /*MI*/3, /*OpIdx*/2, /*OtherMI*/1, /*OtherOpIdx*/2,
        GIM_CheckCxxInsnPredicate, /*MI*/0, /*FnId*/GIMT_Encode2(GICXXPred_MI_Predicate_fmaxnum_like_nnan),
        GIM_CheckIsSafeToFold, /*InsnID*/1,
        GIM_CheckIsSafeToFold, /*InsnID*/2,
        GIM_CheckIsSafeToFold, /*InsnID*/3,
        GIM_CheckComplexPattern, /*MI*/1, /*Op*/1, /*Renderer*/GIMT_Encode2(0), GIMT_Encode2(GICP_gi_vop3mods),
        GIM_CheckComplexPattern, /*MI*/1, /*Op*/2, /*Renderer*/GIMT_Encode2(1), GIMT_Encode2(GICP_gi_vop3mods),
        GIM_CheckComplexPattern, /*MI*/2, /*Op*/2, /*Renderer*/GIMT_Encode2(2), GIMT_Encode2(GICP_gi_vop3mods),
        // (fmaxnum_ieee:{ *:[f16] } (fminnum_ieee:{ *:[f16] } (VOP3Mods:{ *:[f16] } f16:{ *:[f16] }:$src1, i32:{ *:[i32] }:$src1_mods), (VOP3Mods:{ *:[f16] } f16:{ *:[f16] }:$src0, i32:{ *:[i32] }:$src0_mods)), (fminnum_ieee:{ *:[f16] } (fmaxnum_ieee:{ *:[f16] } (VOP3Mods:{ *:[f16] } f16:{ *:[f16] }:$src1, i32:{ *:[i32] }:$src1_mods), (VOP3Mods:{ *:[f16] } f16:{ *:[f16] }:$src0, i32:{ *:[i32] }:$src0_mods)), (VOP3Mods:{ *:[f16] } f16:{ *:[f16] }:$src2, i32:{ *:[i32] }:$src2_mods)))<<P:Predicate_fmaxnum_like_nnan>>  =>  (V_MED3_F16_e64:{ *:[f16] } ?:{ *:[i32] }:$src0_mods, ?:{ *:[f16] }:$src0, ?:{ *:[i32] }:$src1_mods, ?:{ *:[f16] }:$src1, ?:{ *:[i32] }:$src2_mods, ?:{ *:[f16] }:$src2, 0:{ *:[i1] })
        GIR_BuildMI, /*InsnID*/0, /*Opcode*/GIMT_Encode2(AMDGPU::V_MED3_F16_e64),
        GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/0, // DstI[vdst]
        GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(1), /*SubOperand*/1, // src0_mods
        GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(1), /*SubOperand*/0, // src0
        GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/1, // src1_mods
        GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/0, // src1
        GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(2), /*SubOperand*/1, // src2_mods
        GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(2), /*SubOperand*/0, // src2
        GIR_AddImm8, /*InsnID*/0, /*Imm*/0,
        GIR_AddImm8, /*InsnID*/0, /*Imm*/0,
        GIR_AddImm8, /*InsnID*/0, /*Imm*/0,
        GIR_ConstrainSelectedInstOperands, /*InsnID*/0,
        GIR_EraseFromParent, /*InsnID*/0,
        // GIR_Coverage, 10534,
        GIR_Done,
      // Label 5013: @360450
      GIM_Try, /*On fail goto*//*Label 5014*/ GIMT_Encode4(360596), // Rule ID 10616 //
        GIM_CheckFeatures, GIMT_Encode2(GIFBS_isGFX9Plus),
        GIM_CheckRegBankForClass, /*MI*/0, /*Op*/0, /*RC*/GIMT_Encode2(AMDGPU::VGPR_32RegClassID),
        GIM_RecordInsn, /*DefineMI*/1, /*MI*/0, /*OpIdx*/1, // MIs[1]
        GIM_CheckOpcode, /*MI*/1, GIMT_Encode2(TargetOpcode::G_FMINNUM_IEEE),
        GIM_CheckType, /*MI*/1, /*Op*/1, /*Type*/GILLT_s16,
        GIM_CheckType, /*MI*/1, /*Op*/2, /*Type*/GILLT_s16,
        GIM_RecordInsn, /*DefineMI*/2, /*MI*/1, /*OpIdx*/2, // MIs[2]
        GIM_CheckOpcode, /*MI*/2, GIMT_Encode2(TargetOpcode::G_FMAXNUM),
        GIM_CheckType, /*MI*/2, /*Op*/1, /*Type*/GILLT_s16,
        GIM_CheckType, /*MI*/2, /*Op*/2, /*Type*/GILLT_s16,
        GIM_RecordInsn, /*DefineMI*/3, /*MI*/0, /*OpIdx*/2, // MIs[3]
        GIM_CheckOpcode, /*MI*/3, GIMT_Encode2(TargetOpcode::G_FMINNUM),
        // MIs[3] VOP3Mods:src0:src0_mods
        GIM_CheckIsSameOperand, /*MI*/3, /*OpIdx*/1, /*OtherMI*/2, /*OtherOpIdx*/1,
        // MIs[3] VOP3Mods:src1:src1_mods
        GIM_CheckIsSameOperand, /*MI*/3, /*OpIdx*/2, /*OtherMI*/2, /*OtherOpIdx*/2,
        GIM_CheckCxxInsnPredicate, /*MI*/0, /*FnId*/GIMT_Encode2(GICXXPred_MI_Predicate_fmaxnum_like_nnan),
        GIM_CheckIsSafeToFold, /*InsnID*/1,
        GIM_CheckIsSafeToFold, /*InsnID*/2,
        GIM_CheckIsSafeToFold, /*InsnID*/3,
        GIM_CheckComplexPattern, /*MI*/1, /*Op*/1, /*Renderer*/GIMT_Encode2(0), GIMT_Encode2(GICP_gi_vop3mods),
        GIM_CheckComplexPattern, /*MI*/2, /*Op*/1, /*Renderer*/GIMT_Encode2(1), GIMT_Encode2(GICP_gi_vop3mods),
        GIM_CheckComplexPattern, /*MI*/2, /*Op*/2, /*Renderer*/GIMT_Encode2(2), GIMT_Encode2(GICP_gi_vop3mods),
        // (fmaxnum_ieee:{ *:[f16] } (fminnum_ieee:{ *:[f16] } (VOP3Mods:{ *:[f16] } f16:{ *:[f16] }:$src2, i32:{ *:[i32] }:$src2_mods), (fmaxnum:{ *:[f16] } (VOP3Mods:{ *:[f16] } f16:{ *:[f16] }:$src0, i32:{ *:[i32] }:$src0_mods), (VOP3Mods:{ *:[f16] } f16:{ *:[f16] }:$src1, i32:{ *:[i32] }:$src1_mods))), (fminnum:{ *:[f16] } (VOP3Mods:{ *:[f16] } f16:{ *:[f16] }:$src0, i32:{ *:[i32] }:$src0_mods), (VOP3Mods:{ *:[f16] } f16:{ *:[f16] }:$src1, i32:{ *:[i32] }:$src1_mods)))<<P:Predicate_fmaxnum_like_nnan>>  =>  (V_MED3_F16_e64:{ *:[f16] } ?:{ *:[i32] }:$src0_mods, ?:{ *:[f16] }:$src0, ?:{ *:[i32] }:$src1_mods, ?:{ *:[f16] }:$src1, ?:{ *:[i32] }:$src2_mods, ?:{ *:[f16] }:$src2, 0:{ *:[i1] })
        GIR_BuildMI, /*InsnID*/0, /*Opcode*/GIMT_Encode2(AMDGPU::V_MED3_F16_e64),
        GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/0, // DstI[vdst]
        GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(1), /*SubOperand*/1, // src0_mods
        GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(1), /*SubOperand*/0, // src0
        GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(2), /*SubOperand*/1, // src1_mods
        GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(2), /*SubOperand*/0, // src1
        GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/1, // src2_mods
        GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/0, // src2
        GIR_AddImm8, /*InsnID*/0, /*Imm*/0,
        GIR_AddImm8, /*InsnID*/0, /*Imm*/0,
        GIR_AddImm8, /*InsnID*/0, /*Imm*/0,
        GIR_ConstrainSelectedInstOperands, /*InsnID*/0,
        GIR_EraseFromParent, /*InsnID*/0,
        // GIR_Coverage, 10616,
        GIR_Done,
      // Label 5014: @360596
      GIM_Try, /*On fail goto*//*Label 5015*/ GIMT_Encode4(360742), // Rule ID 10617 //
        GIM_CheckFeatures, GIMT_Encode2(GIFBS_isGFX9Plus),
        GIM_CheckRegBankForClass, /*MI*/0, /*Op*/0, /*RC*/GIMT_Encode2(AMDGPU::VGPR_32RegClassID),
        GIM_RecordInsn, /*DefineMI*/1, /*MI*/0, /*OpIdx*/1, // MIs[1]
        GIM_CheckOpcode, /*MI*/1, GIMT_Encode2(TargetOpcode::G_FMINNUM_IEEE),
        GIM_CheckType, /*MI*/1, /*Op*/1, /*Type*/GILLT_s16,
        GIM_CheckType, /*MI*/1, /*Op*/2, /*Type*/GILLT_s16,
        GIM_RecordInsn, /*DefineMI*/2, /*MI*/1, /*OpIdx*/2, // MIs[2]
        GIM_CheckOpcode, /*MI*/2, GIMT_Encode2(TargetOpcode::G_FMAXNUM),
        GIM_CheckType, /*MI*/2, /*Op*/1, /*Type*/GILLT_s16,
        GIM_CheckType, /*MI*/2, /*Op*/2, /*Type*/GILLT_s16,
        GIM_RecordInsn, /*DefineMI*/3, /*MI*/0, /*OpIdx*/2, // MIs[3]
        GIM_CheckOpcode, /*MI*/3, GIMT_Encode2(TargetOpcode::G_FMINNUM),
        // MIs[3] VOP3Mods:src1:src1_mods
        GIM_CheckIsSameOperand, /*MI*/3, /*OpIdx*/1, /*OtherMI*/2, /*OtherOpIdx*/2,
        // MIs[3] VOP3Mods:src0:src0_mods
        GIM_CheckIsSameOperand, /*MI*/3, /*OpIdx*/2, /*OtherMI*/2, /*OtherOpIdx*/1,
        GIM_CheckCxxInsnPredicate, /*MI*/0, /*FnId*/GIMT_Encode2(GICXXPred_MI_Predicate_fmaxnum_like_nnan),
        GIM_CheckIsSafeToFold, /*InsnID*/1,
        GIM_CheckIsSafeToFold, /*InsnID*/2,
        GIM_CheckIsSafeToFold, /*InsnID*/3,
        GIM_CheckComplexPattern, /*MI*/1, /*Op*/1, /*Renderer*/GIMT_Encode2(0), GIMT_Encode2(GICP_gi_vop3mods),
        GIM_CheckComplexPattern, /*MI*/2, /*Op*/1, /*Renderer*/GIMT_Encode2(1), GIMT_Encode2(GICP_gi_vop3mods),
        GIM_CheckComplexPattern, /*MI*/2, /*Op*/2, /*Renderer*/GIMT_Encode2(2), GIMT_Encode2(GICP_gi_vop3mods),
        // (fmaxnum_ieee:{ *:[f16] } (fminnum_ieee:{ *:[f16] } (VOP3Mods:{ *:[f16] } f16:{ *:[f16] }:$src2, i32:{ *:[i32] }:$src2_mods), (fmaxnum:{ *:[f16] } (VOP3Mods:{ *:[f16] } f16:{ *:[f16] }:$src0, i32:{ *:[i32] }:$src0_mods), (VOP3Mods:{ *:[f16] } f16:{ *:[f16] }:$src1, i32:{ *:[i32] }:$src1_mods))), (fminnum:{ *:[f16] } (VOP3Mods:{ *:[f16] } f16:{ *:[f16] }:$src1, i32:{ *:[i32] }:$src1_mods), (VOP3Mods:{ *:[f16] } f16:{ *:[f16] }:$src0, i32:{ *:[i32] }:$src0_mods)))<<P:Predicate_fmaxnum_like_nnan>>  =>  (V_MED3_F16_e64:{ *:[f16] } ?:{ *:[i32] }:$src0_mods, ?:{ *:[f16] }:$src0, ?:{ *:[i32] }:$src1_mods, ?:{ *:[f16] }:$src1, ?:{ *:[i32] }:$src2_mods, ?:{ *:[f16] }:$src2, 0:{ *:[i1] })
        GIR_BuildMI, /*InsnID*/0, /*Opcode*/GIMT_Encode2(AMDGPU::V_MED3_F16_e64),
        GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/0, // DstI[vdst]
        GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(1), /*SubOperand*/1, // src0_mods
        GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(1), /*SubOperand*/0, // src0
        GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(2), /*SubOperand*/1, // src1_mods
        GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(2), /*SubOperand*/0, // src1
        GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/1, // src2_mods
        GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/0, // src2
        GIR_AddImm8, /*InsnID*/0, /*Imm*/0,
        GIR_AddImm8, /*InsnID*/0, /*Imm*/0,
        GIR_AddImm8, /*InsnID*/0, /*Imm*/0,
        GIR_ConstrainSelectedInstOperands, /*InsnID*/0,
        GIR_EraseFromParent, /*InsnID*/0,
        // GIR_Coverage, 10617,
        GIR_Done,
      // Label 5015: @360742
      GIM_Try, /*On fail goto*//*Label 5016*/ GIMT_Encode4(360888), // Rule ID 10618 //
        GIM_CheckFeatures, GIMT_Encode2(GIFBS_isGFX9Plus),
        GIM_CheckRegBankForClass, /*MI*/0, /*Op*/0, /*RC*/GIMT_Encode2(AMDGPU::VGPR_32RegClassID),
        GIM_RecordInsn, /*DefineMI*/1, /*MI*/0, /*OpIdx*/1, // MIs[1]
        GIM_CheckOpcode, /*MI*/1, GIMT_Encode2(TargetOpcode::G_FMINNUM_IEEE),
        GIM_CheckType, /*MI*/1, /*Op*/1, /*Type*/GILLT_s16,
        GIM_CheckType, /*MI*/1, /*Op*/2, /*Type*/GILLT_s16,
        GIM_RecordInsn, /*DefineMI*/2, /*MI*/1, /*OpIdx*/2, // MIs[2]
        GIM_CheckOpcode, /*MI*/2, GIMT_Encode2(TargetOpcode::G_FMAXNUM),
        GIM_CheckType, /*MI*/2, /*Op*/1, /*Type*/GILLT_s16,
        GIM_CheckType, /*MI*/2, /*Op*/2, /*Type*/GILLT_s16,
        GIM_RecordInsn, /*DefineMI*/3, /*MI*/0, /*OpIdx*/2, // MIs[3]
        GIM_CheckOpcode, /*MI*/3, GIMT_Encode2(TargetOpcode::G_FMINNUM),
        // MIs[3] VOP3Mods:src0:src0_mods
        GIM_CheckIsSameOperand, /*MI*/3, /*OpIdx*/1, /*OtherMI*/2, /*OtherOpIdx*/2,
        // MIs[3] VOP3Mods:src1:src1_mods
        GIM_CheckIsSameOperand, /*MI*/3, /*OpIdx*/2, /*OtherMI*/2, /*OtherOpIdx*/1,
        GIM_CheckCxxInsnPredicate, /*MI*/0, /*FnId*/GIMT_Encode2(GICXXPred_MI_Predicate_fmaxnum_like_nnan),
        GIM_CheckIsSafeToFold, /*InsnID*/1,
        GIM_CheckIsSafeToFold, /*InsnID*/2,
        GIM_CheckIsSafeToFold, /*InsnID*/3,
        GIM_CheckComplexPattern, /*MI*/1, /*Op*/1, /*Renderer*/GIMT_Encode2(0), GIMT_Encode2(GICP_gi_vop3mods),
        GIM_CheckComplexPattern, /*MI*/2, /*Op*/1, /*Renderer*/GIMT_Encode2(1), GIMT_Encode2(GICP_gi_vop3mods),
        GIM_CheckComplexPattern, /*MI*/2, /*Op*/2, /*Renderer*/GIMT_Encode2(2), GIMT_Encode2(GICP_gi_vop3mods),
        // (fmaxnum_ieee:{ *:[f16] } (fminnum_ieee:{ *:[f16] } (VOP3Mods:{ *:[f16] } f16:{ *:[f16] }:$src2, i32:{ *:[i32] }:$src2_mods), (fmaxnum:{ *:[f16] } (VOP3Mods:{ *:[f16] } f16:{ *:[f16] }:$src1, i32:{ *:[i32] }:$src1_mods), (VOP3Mods:{ *:[f16] } f16:{ *:[f16] }:$src0, i32:{ *:[i32] }:$src0_mods))), (fminnum:{ *:[f16] } (VOP3Mods:{ *:[f16] } f16:{ *:[f16] }:$src0, i32:{ *:[i32] }:$src0_mods), (VOP3Mods:{ *:[f16] } f16:{ *:[f16] }:$src1, i32:{ *:[i32] }:$src1_mods)))<<P:Predicate_fmaxnum_like_nnan>>  =>  (V_MED3_F16_e64:{ *:[f16] } ?:{ *:[i32] }:$src0_mods, ?:{ *:[f16] }:$src0, ?:{ *:[i32] }:$src1_mods, ?:{ *:[f16] }:$src1, ?:{ *:[i32] }:$src2_mods, ?:{ *:[f16] }:$src2, 0:{ *:[i1] })
        GIR_BuildMI, /*InsnID*/0, /*Opcode*/GIMT_Encode2(AMDGPU::V_MED3_F16_e64),
        GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/0, // DstI[vdst]
        GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(2), /*SubOperand*/1, // src0_mods
        GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(2), /*SubOperand*/0, // src0
        GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(1), /*SubOperand*/1, // src1_mods
        GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(1), /*SubOperand*/0, // src1
        GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/1, // src2_mods
        GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/0, // src2
        GIR_AddImm8, /*InsnID*/0, /*Imm*/0,
        GIR_AddImm8, /*InsnID*/0, /*Imm*/0,
        GIR_AddImm8, /*InsnID*/0, /*Imm*/0,
        GIR_ConstrainSelectedInstOperands, /*InsnID*/0,
        GIR_EraseFromParent, /*InsnID*/0,
        // GIR_Coverage, 10618,
        GIR_Done,
      // Label 5016: @360888
      GIM_Try, /*On fail goto*//*Label 5017*/ GIMT_Encode4(361034), // Rule ID 10619 //
        GIM_CheckFeatures, GIMT_Encode2(GIFBS_isGFX9Plus),
        GIM_CheckRegBankForClass, /*MI*/0, /*Op*/0, /*RC*/GIMT_Encode2(AMDGPU::VGPR_32RegClassID),
        GIM_RecordInsn, /*DefineMI*/1, /*MI*/0, /*OpIdx*/1, // MIs[1]
        GIM_CheckOpcode, /*MI*/1, GIMT_Encode2(TargetOpcode::G_FMINNUM_IEEE),
        GIM_CheckType, /*MI*/1, /*Op*/1, /*Type*/GILLT_s16,
        GIM_CheckType, /*MI*/1, /*Op*/2, /*Type*/GILLT_s16,
        GIM_RecordInsn, /*DefineMI*/2, /*MI*/1, /*OpIdx*/2, // MIs[2]
        GIM_CheckOpcode, /*MI*/2, GIMT_Encode2(TargetOpcode::G_FMAXNUM),
        GIM_CheckType, /*MI*/2, /*Op*/1, /*Type*/GILLT_s16,
        GIM_CheckType, /*MI*/2, /*Op*/2, /*Type*/GILLT_s16,
        GIM_RecordInsn, /*DefineMI*/3, /*MI*/0, /*OpIdx*/2, // MIs[3]
        GIM_CheckOpcode, /*MI*/3, GIMT_Encode2(TargetOpcode::G_FMINNUM),
        // MIs[3] VOP3Mods:src1:src1_mods
        GIM_CheckIsSameOperand, /*MI*/3, /*OpIdx*/1, /*OtherMI*/2, /*OtherOpIdx*/1,
        // MIs[3] VOP3Mods:src0:src0_mods
        GIM_CheckIsSameOperand, /*MI*/3, /*OpIdx*/2, /*OtherMI*/2, /*OtherOpIdx*/2,
        GIM_CheckCxxInsnPredicate, /*MI*/0, /*FnId*/GIMT_Encode2(GICXXPred_MI_Predicate_fmaxnum_like_nnan),
        GIM_CheckIsSafeToFold, /*InsnID*/1,
        GIM_CheckIsSafeToFold, /*InsnID*/2,
        GIM_CheckIsSafeToFold, /*InsnID*/3,
        GIM_CheckComplexPattern, /*MI*/1, /*Op*/1, /*Renderer*/GIMT_Encode2(0), GIMT_Encode2(GICP_gi_vop3mods),
        GIM_CheckComplexPattern, /*MI*/2, /*Op*/1, /*Renderer*/GIMT_Encode2(1), GIMT_Encode2(GICP_gi_vop3mods),
        GIM_CheckComplexPattern, /*MI*/2, /*Op*/2, /*Renderer*/GIMT_Encode2(2), GIMT_Encode2(GICP_gi_vop3mods),
        // (fmaxnum_ieee:{ *:[f16] } (fminnum_ieee:{ *:[f16] } (VOP3Mods:{ *:[f16] } f16:{ *:[f16] }:$src2, i32:{ *:[i32] }:$src2_mods), (fmaxnum:{ *:[f16] } (VOP3Mods:{ *:[f16] } f16:{ *:[f16] }:$src1, i32:{ *:[i32] }:$src1_mods), (VOP3Mods:{ *:[f16] } f16:{ *:[f16] }:$src0, i32:{ *:[i32] }:$src0_mods))), (fminnum:{ *:[f16] } (VOP3Mods:{ *:[f16] } f16:{ *:[f16] }:$src1, i32:{ *:[i32] }:$src1_mods), (VOP3Mods:{ *:[f16] } f16:{ *:[f16] }:$src0, i32:{ *:[i32] }:$src0_mods)))<<P:Predicate_fmaxnum_like_nnan>>  =>  (V_MED3_F16_e64:{ *:[f16] } ?:{ *:[i32] }:$src0_mods, ?:{ *:[f16] }:$src0, ?:{ *:[i32] }:$src1_mods, ?:{ *:[f16] }:$src1, ?:{ *:[i32] }:$src2_mods, ?:{ *:[f16] }:$src2, 0:{ *:[i1] })
        GIR_BuildMI, /*InsnID*/0, /*Opcode*/GIMT_Encode2(AMDGPU::V_MED3_F16_e64),
        GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/0, // DstI[vdst]
        GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(2), /*SubOperand*/1, // src0_mods
        GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(2), /*SubOperand*/0, // src0
        GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(1), /*SubOperand*/1, // src1_mods
        GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(1), /*SubOperand*/0, // src1
        GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/1, // src2_mods
        GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/0, // src2
        GIR_AddImm8, /*InsnID*/0, /*Imm*/0,
        GIR_AddImm8, /*InsnID*/0, /*Imm*/0,
        GIR_AddImm8, /*InsnID*/0, /*Imm*/0,
        GIR_ConstrainSelectedInstOperands, /*InsnID*/0,
        GIR_EraseFromParent, /*InsnID*/0,
        // GIR_Coverage, 10619,
        GIR_Done,
      // Label 5017: @361034
      GIM_Try, /*On fail goto*//*Label 5018*/ GIMT_Encode4(361180), // Rule ID 10556 //
        GIM_CheckFeatures, GIMT_Encode2(GIFBS_isGFX9Plus),
        GIM_CheckRegBankForClass, /*MI*/0, /*Op*/0, /*RC*/GIMT_Encode2(AMDGPU::VGPR_32RegClassID),
        GIM_RecordInsn, /*DefineMI*/1, /*MI*/0, /*OpIdx*/1, // MIs[1]
        GIM_CheckOpcode, /*MI*/1, GIMT_Encode2(TargetOpcode::G_FMINNUM_IEEE),
        GIM_CheckType, /*MI*/1, /*Op*/1, /*Type*/GILLT_s16,
        GIM_CheckType, /*MI*/1, /*Op*/2, /*Type*/GILLT_s16,
        GIM_RecordInsn, /*DefineMI*/2, /*MI*/1, /*OpIdx*/2, // MIs[2]
        GIM_CheckOpcode, /*MI*/2, GIMT_Encode2(TargetOpcode::G_FMAXNUM),
        GIM_CheckType, /*MI*/2, /*Op*/1, /*Type*/GILLT_s16,
        GIM_CheckType, /*MI*/2, /*Op*/2, /*Type*/GILLT_s16,
        GIM_RecordInsn, /*DefineMI*/3, /*MI*/0, /*OpIdx*/2, // MIs[3]
        GIM_CheckOpcode, /*MI*/3, GIMT_Encode2(TargetOpcode::G_FMINNUM_IEEE),
        // MIs[3] VOP3Mods:src0:src0_mods
        GIM_CheckIsSameOperand, /*MI*/3, /*OpIdx*/1, /*OtherMI*/2, /*OtherOpIdx*/1,
        // MIs[3] VOP3Mods:src1:src1_mods
        GIM_CheckIsSameOperand, /*MI*/3, /*OpIdx*/2, /*OtherMI*/2, /*OtherOpIdx*/2,
        GIM_CheckCxxInsnPredicate, /*MI*/0, /*FnId*/GIMT_Encode2(GICXXPred_MI_Predicate_fmaxnum_like_nnan),
        GIM_CheckIsSafeToFold, /*InsnID*/1,
        GIM_CheckIsSafeToFold, /*InsnID*/2,
        GIM_CheckIsSafeToFold, /*InsnID*/3,
        GIM_CheckComplexPattern, /*MI*/1, /*Op*/1, /*Renderer*/GIMT_Encode2(0), GIMT_Encode2(GICP_gi_vop3mods),
        GIM_CheckComplexPattern, /*MI*/2, /*Op*/1, /*Renderer*/GIMT_Encode2(1), GIMT_Encode2(GICP_gi_vop3mods),
        GIM_CheckComplexPattern, /*MI*/2, /*Op*/2, /*Renderer*/GIMT_Encode2(2), GIMT_Encode2(GICP_gi_vop3mods),
        // (fmaxnum_ieee:{ *:[f16] } (fminnum_ieee:{ *:[f16] } (VOP3Mods:{ *:[f16] } f16:{ *:[f16] }:$src2, i32:{ *:[i32] }:$src2_mods), (fmaxnum:{ *:[f16] } (VOP3Mods:{ *:[f16] } f16:{ *:[f16] }:$src0, i32:{ *:[i32] }:$src0_mods), (VOP3Mods:{ *:[f16] } f16:{ *:[f16] }:$src1, i32:{ *:[i32] }:$src1_mods))), (fminnum_ieee:{ *:[f16] } (VOP3Mods:{ *:[f16] } f16:{ *:[f16] }:$src0, i32:{ *:[i32] }:$src0_mods), (VOP3Mods:{ *:[f16] } f16:{ *:[f16] }:$src1, i32:{ *:[i32] }:$src1_mods)))<<P:Predicate_fmaxnum_like_nnan>>  =>  (V_MED3_F16_e64:{ *:[f16] } ?:{ *:[i32] }:$src0_mods, ?:{ *:[f16] }:$src0, ?:{ *:[i32] }:$src1_mods, ?:{ *:[f16] }:$src1, ?:{ *:[i32] }:$src2_mods, ?:{ *:[f16] }:$src2, 0:{ *:[i1] })
        GIR_BuildMI, /*InsnID*/0, /*Opcode*/GIMT_Encode2(AMDGPU::V_MED3_F16_e64),
        GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/0, // DstI[vdst]
        GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(1), /*SubOperand*/1, // src0_mods
        GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(1), /*SubOperand*/0, // src0
        GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(2), /*SubOperand*/1, // src1_mods
        GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(2), /*SubOperand*/0, // src1
        GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/1, // src2_mods
        GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/0, // src2
        GIR_AddImm8, /*InsnID*/0, /*Imm*/0,
        GIR_AddImm8, /*InsnID*/0, /*Imm*/0,
        GIR_AddImm8, /*InsnID*/0, /*Imm*/0,
        GIR_ConstrainSelectedInstOperands, /*InsnID*/0,
        GIR_EraseFromParent, /*InsnID*/0,
        // GIR_Coverage, 10556,
        GIR_Done,
      // Label 5018: @361180
      GIM_Try, /*On fail goto*//*Label 5019*/ GIMT_Encode4(361326), // Rule ID 10557 //
        GIM_CheckFeatures, GIMT_Encode2(GIFBS_isGFX9Plus),
        GIM_CheckRegBankForClass, /*MI*/0, /*Op*/0, /*RC*/GIMT_Encode2(AMDGPU::VGPR_32RegClassID),
        GIM_RecordInsn, /*DefineMI*/1, /*MI*/0, /*OpIdx*/1, // MIs[1]
        GIM_CheckOpcode, /*MI*/1, GIMT_Encode2(TargetOpcode::G_FMINNUM_IEEE),
        GIM_CheckType, /*MI*/1, /*Op*/1, /*Type*/GILLT_s16,
        GIM_CheckType, /*MI*/1, /*Op*/2, /*Type*/GILLT_s16,
        GIM_RecordInsn, /*DefineMI*/2, /*MI*/1, /*OpIdx*/2, // MIs[2]
        GIM_CheckOpcode, /*MI*/2, GIMT_Encode2(TargetOpcode::G_FMAXNUM),
        GIM_CheckType, /*MI*/2, /*Op*/1, /*Type*/GILLT_s16,
        GIM_CheckType, /*MI*/2, /*Op*/2, /*Type*/GILLT_s16,
        GIM_RecordInsn, /*DefineMI*/3, /*MI*/0, /*OpIdx*/2, // MIs[3]
        GIM_CheckOpcode, /*MI*/3, GIMT_Encode2(TargetOpcode::G_FMINNUM_IEEE),
        // MIs[3] VOP3Mods:src1:src1_mods
        GIM_CheckIsSameOperand, /*MI*/3, /*OpIdx*/1, /*OtherMI*/2, /*OtherOpIdx*/2,
        // MIs[3] VOP3Mods:src0:src0_mods
        GIM_CheckIsSameOperand, /*MI*/3, /*OpIdx*/2, /*OtherMI*/2, /*OtherOpIdx*/1,
        GIM_CheckCxxInsnPredicate, /*MI*/0, /*FnId*/GIMT_Encode2(GICXXPred_MI_Predicate_fmaxnum_like_nnan),
        GIM_CheckIsSafeToFold, /*InsnID*/1,
        GIM_CheckIsSafeToFold, /*InsnID*/2,
        GIM_CheckIsSafeToFold, /*InsnID*/3,
        GIM_CheckComplexPattern, /*MI*/1, /*Op*/1, /*Renderer*/GIMT_Encode2(0), GIMT_Encode2(GICP_gi_vop3mods),
        GIM_CheckComplexPattern, /*MI*/2, /*Op*/1, /*Renderer*/GIMT_Encode2(1), GIMT_Encode2(GICP_gi_vop3mods),
        GIM_CheckComplexPattern, /*MI*/2, /*Op*/2, /*Renderer*/GIMT_Encode2(2), GIMT_Encode2(GICP_gi_vop3mods),
        // (fmaxnum_ieee:{ *:[f16] } (fminnum_ieee:{ *:[f16] } (VOP3Mods:{ *:[f16] } f16:{ *:[f16] }:$src2, i32:{ *:[i32] }:$src2_mods), (fmaxnum:{ *:[f16] } (VOP3Mods:{ *:[f16] } f16:{ *:[f16] }:$src0, i32:{ *:[i32] }:$src0_mods), (VOP3Mods:{ *:[f16] } f16:{ *:[f16] }:$src1, i32:{ *:[i32] }:$src1_mods))), (fminnum_ieee:{ *:[f16] } (VOP3Mods:{ *:[f16] } f16:{ *:[f16] }:$src1, i32:{ *:[i32] }:$src1_mods), (VOP3Mods:{ *:[f16] } f16:{ *:[f16] }:$src0, i32:{ *:[i32] }:$src0_mods)))<<P:Predicate_fmaxnum_like_nnan>>  =>  (V_MED3_F16_e64:{ *:[f16] } ?:{ *:[i32] }:$src0_mods, ?:{ *:[f16] }:$src0, ?:{ *:[i32] }:$src1_mods, ?:{ *:[f16] }:$src1, ?:{ *:[i32] }:$src2_mods, ?:{ *:[f16] }:$src2, 0:{ *:[i1] })
        GIR_BuildMI, /*InsnID*/0, /*Opcode*/GIMT_Encode2(AMDGPU::V_MED3_F16_e64),
        GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/0, // DstI[vdst]
        GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(1), /*SubOperand*/1, // src0_mods
        GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(1), /*SubOperand*/0, // src0
        GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(2), /*SubOperand*/1, // src1_mods
        GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(2), /*SubOperand*/0, // src1
        GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/1, // src2_mods
        GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/0, // src2
        GIR_AddImm8, /*InsnID*/0, /*Imm*/0,
        GIR_AddImm8, /*InsnID*/0, /*Imm*/0,
        GIR_AddImm8, /*InsnID*/0, /*Imm*/0,
        GIR_ConstrainSelectedInstOperands, /*InsnID*/0,
        GIR_EraseFromParent, /*InsnID*/0,
        // GIR_Coverage, 10557,
        GIR_Done,
      // Label 5019: @361326
      GIM_Try, /*On fail goto*//*Label 5020*/ GIMT_Encode4(361472), // Rule ID 10558 //
        GIM_CheckFeatures, GIMT_Encode2(GIFBS_isGFX9Plus),
        GIM_CheckRegBankForClass, /*MI*/0, /*Op*/0, /*RC*/GIMT_Encode2(AMDGPU::VGPR_32RegClassID),
        GIM_RecordInsn, /*DefineMI*/1, /*MI*/0, /*OpIdx*/1, // MIs[1]
        GIM_CheckOpcode, /*MI*/1, GIMT_Encode2(TargetOpcode::G_FMINNUM_IEEE),
        GIM_CheckType, /*MI*/1, /*Op*/1, /*Type*/GILLT_s16,
        GIM_CheckType, /*MI*/1, /*Op*/2, /*Type*/GILLT_s16,
        GIM_RecordInsn, /*DefineMI*/2, /*MI*/1, /*OpIdx*/2, // MIs[2]
        GIM_CheckOpcode, /*MI*/2, GIMT_Encode2(TargetOpcode::G_FMAXNUM),
        GIM_CheckType, /*MI*/2, /*Op*/1, /*Type*/GILLT_s16,
        GIM_CheckType, /*MI*/2, /*Op*/2, /*Type*/GILLT_s16,
        GIM_RecordInsn, /*DefineMI*/3, /*MI*/0, /*OpIdx*/2, // MIs[3]
        GIM_CheckOpcode, /*MI*/3, GIMT_Encode2(TargetOpcode::G_FMINNUM_IEEE),
        // MIs[3] VOP3Mods:src0:src0_mods
        GIM_CheckIsSameOperand, /*MI*/3, /*OpIdx*/1, /*OtherMI*/2, /*OtherOpIdx*/2,
        // MIs[3] VOP3Mods:src1:src1_mods
        GIM_CheckIsSameOperand, /*MI*/3, /*OpIdx*/2, /*OtherMI*/2, /*OtherOpIdx*/1,
        GIM_CheckCxxInsnPredicate, /*MI*/0, /*FnId*/GIMT_Encode2(GICXXPred_MI_Predicate_fmaxnum_like_nnan),
        GIM_CheckIsSafeToFold, /*InsnID*/1,
        GIM_CheckIsSafeToFold, /*InsnID*/2,
        GIM_CheckIsSafeToFold, /*InsnID*/3,
        GIM_CheckComplexPattern, /*MI*/1, /*Op*/1, /*Renderer*/GIMT_Encode2(0), GIMT_Encode2(GICP_gi_vop3mods),
        GIM_CheckComplexPattern, /*MI*/2, /*Op*/1, /*Renderer*/GIMT_Encode2(1), GIMT_Encode2(GICP_gi_vop3mods),
        GIM_CheckComplexPattern, /*MI*/2, /*Op*/2, /*Renderer*/GIMT_Encode2(2), GIMT_Encode2(GICP_gi_vop3mods),
        // (fmaxnum_ieee:{ *:[f16] } (fminnum_ieee:{ *:[f16] } (VOP3Mods:{ *:[f16] } f16:{ *:[f16] }:$src2, i32:{ *:[i32] }:$src2_mods), (fmaxnum:{ *:[f16] } (VOP3Mods:{ *:[f16] } f16:{ *:[f16] }:$src1, i32:{ *:[i32] }:$src1_mods), (VOP3Mods:{ *:[f16] } f16:{ *:[f16] }:$src0, i32:{ *:[i32] }:$src0_mods))), (fminnum_ieee:{ *:[f16] } (VOP3Mods:{ *:[f16] } f16:{ *:[f16] }:$src0, i32:{ *:[i32] }:$src0_mods), (VOP3Mods:{ *:[f16] } f16:{ *:[f16] }:$src1, i32:{ *:[i32] }:$src1_mods)))<<P:Predicate_fmaxnum_like_nnan>>  =>  (V_MED3_F16_e64:{ *:[f16] } ?:{ *:[i32] }:$src0_mods, ?:{ *:[f16] }:$src0, ?:{ *:[i32] }:$src1_mods, ?:{ *:[f16] }:$src1, ?:{ *:[i32] }:$src2_mods, ?:{ *:[f16] }:$src2, 0:{ *:[i1] })
        GIR_BuildMI, /*InsnID*/0, /*Opcode*/GIMT_Encode2(AMDGPU::V_MED3_F16_e64),
        GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/0, // DstI[vdst]
        GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(2), /*SubOperand*/1, // src0_mods
        GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(2), /*SubOperand*/0, // src0
        GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(1), /*SubOperand*/1, // src1_mods
        GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(1), /*SubOperand*/0, // src1
        GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/1, // src2_mods
        GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/0, // src2
        GIR_AddImm8, /*InsnID*/0, /*Imm*/0,
        GIR_AddImm8, /*InsnID*/0, /*Imm*/0,
        GIR_AddImm8, /*InsnID*/0, /*Imm*/0,
        GIR_ConstrainSelectedInstOperands, /*InsnID*/0,
        GIR_EraseFromParent, /*InsnID*/0,
        // GIR_Coverage, 10558,
        GIR_Done,
      // Label 5020: @361472
      GIM_Try, /*On fail goto*//*Label 5021*/ GIMT_Encode4(361618), // Rule ID 10559 //
        GIM_CheckFeatures, GIMT_Encode2(GIFBS_isGFX9Plus),
        GIM_CheckRegBankForClass, /*MI*/0, /*Op*/0, /*RC*/GIMT_Encode2(AMDGPU::VGPR_32RegClassID),
        GIM_RecordInsn, /*DefineMI*/1, /*MI*/0, /*OpIdx*/1, // MIs[1]
        GIM_CheckOpcode, /*MI*/1, GIMT_Encode2(TargetOpcode::G_FMINNUM_IEEE),
        GIM_CheckType, /*MI*/1, /*Op*/1, /*Type*/GILLT_s16,
        GIM_CheckType, /*MI*/1, /*Op*/2, /*Type*/GILLT_s16,
        GIM_RecordInsn, /*DefineMI*/2, /*MI*/1, /*OpIdx*/2, // MIs[2]
        GIM_CheckOpcode, /*MI*/2, GIMT_Encode2(TargetOpcode::G_FMAXNUM),
        GIM_CheckType, /*MI*/2, /*Op*/1, /*Type*/GILLT_s16,
        GIM_CheckType, /*MI*/2, /*Op*/2, /*Type*/GILLT_s16,
        GIM_RecordInsn, /*DefineMI*/3, /*MI*/0, /*OpIdx*/2, // MIs[3]
        GIM_CheckOpcode, /*MI*/3, GIMT_Encode2(TargetOpcode::G_FMINNUM_IEEE),
        // MIs[3] VOP3Mods:src1:src1_mods
        GIM_CheckIsSameOperand, /*MI*/3, /*OpIdx*/1, /*OtherMI*/2, /*OtherOpIdx*/1,
        // MIs[3] VOP3Mods:src0:src0_mods
        GIM_CheckIsSameOperand, /*MI*/3, /*OpIdx*/2, /*OtherMI*/2, /*OtherOpIdx*/2,
        GIM_CheckCxxInsnPredicate, /*MI*/0, /*FnId*/GIMT_Encode2(GICXXPred_MI_Predicate_fmaxnum_like_nnan),
        GIM_CheckIsSafeToFold, /*InsnID*/1,
        GIM_CheckIsSafeToFold, /*InsnID*/2,
        GIM_CheckIsSafeToFold, /*InsnID*/3,
        GIM_CheckComplexPattern, /*MI*/1, /*Op*/1, /*Renderer*/GIMT_Encode2(0), GIMT_Encode2(GICP_gi_vop3mods),
        GIM_CheckComplexPattern, /*MI*/2, /*Op*/1, /*Renderer*/GIMT_Encode2(1), GIMT_Encode2(GICP_gi_vop3mods),
        GIM_CheckComplexPattern, /*MI*/2, /*Op*/2, /*Renderer*/GIMT_Encode2(2), GIMT_Encode2(GICP_gi_vop3mods),
        // (fmaxnum_ieee:{ *:[f16] } (fminnum_ieee:{ *:[f16] } (VOP3Mods:{ *:[f16] } f16:{ *:[f16] }:$src2, i32:{ *:[i32] }:$src2_mods), (fmaxnum:{ *:[f16] } (VOP3Mods:{ *:[f16] } f16:{ *:[f16] }:$src1, i32:{ *:[i32] }:$src1_mods), (VOP3Mods:{ *:[f16] } f16:{ *:[f16] }:$src0, i32:{ *:[i32] }:$src0_mods))), (fminnum_ieee:{ *:[f16] } (VOP3Mods:{ *:[f16] } f16:{ *:[f16] }:$src1, i32:{ *:[i32] }:$src1_mods), (VOP3Mods:{ *:[f16] } f16:{ *:[f16] }:$src0, i32:{ *:[i32] }:$src0_mods)))<<P:Predicate_fmaxnum_like_nnan>>  =>  (V_MED3_F16_e64:{ *:[f16] } ?:{ *:[i32] }:$src0_mods, ?:{ *:[f16] }:$src0, ?:{ *:[i32] }:$src1_mods, ?:{ *:[f16] }:$src1, ?:{ *:[i32] }:$src2_mods, ?:{ *:[f16] }:$src2, 0:{ *:[i1] })
        GIR_BuildMI, /*InsnID*/0, /*Opcode*/GIMT_Encode2(AMDGPU::V_MED3_F16_e64),
        GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/0, // DstI[vdst]
        GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(2), /*SubOperand*/1, // src0_mods
        GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(2), /*SubOperand*/0, // src0
        GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(1), /*SubOperand*/1, // src1_mods
        GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(1), /*SubOperand*/0, // src1
        GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/1, // src2_mods
        GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/0, // src2
        GIR_AddImm8, /*InsnID*/0, /*Imm*/0,
        GIR_AddImm8, /*InsnID*/0, /*Imm*/0,
        GIR_AddImm8, /*InsnID*/0, /*Imm*/0,
        GIR_ConstrainSelectedInstOperands, /*InsnID*/0,
        GIR_EraseFromParent, /*InsnID*/0,
        // GIR_Coverage, 10559,
        GIR_Done,
      // Label 5021: @361618
      GIM_Try, /*On fail goto*//*Label 5022*/ GIMT_Encode4(361764), // Rule ID 10601 //
        GIM_CheckFeatures, GIMT_Encode2(GIFBS_isGFX9Plus),
        GIM_CheckRegBankForClass, /*MI*/0, /*Op*/0, /*RC*/GIMT_Encode2(AMDGPU::VGPR_32RegClassID),
        GIM_RecordInsn, /*DefineMI*/1, /*MI*/0, /*OpIdx*/1, // MIs[1]
        GIM_CheckOpcode, /*MI*/1, GIMT_Encode2(TargetOpcode::G_FMINNUM_IEEE),
        GIM_CheckType, /*MI*/1, /*Op*/1, /*Type*/GILLT_s16,
        GIM_CheckType, /*MI*/1, /*Op*/2, /*Type*/GILLT_s16,
        GIM_RecordInsn, /*DefineMI*/2, /*MI*/1, /*OpIdx*/2, // MIs[2]
        GIM_CheckOpcode, /*MI*/2, GIMT_Encode2(TargetOpcode::G_FMAXNUM_IEEE),
        GIM_CheckType, /*MI*/2, /*Op*/1, /*Type*/GILLT_s16,
        GIM_CheckType, /*MI*/2, /*Op*/2, /*Type*/GILLT_s16,
        GIM_RecordInsn, /*DefineMI*/3, /*MI*/0, /*OpIdx*/2, // MIs[3]
        GIM_CheckOpcode, /*MI*/3, GIMT_Encode2(TargetOpcode::G_FMINNUM),
        // MIs[3] VOP3Mods:src0:src0_mods
        GIM_CheckIsSameOperand, /*MI*/3, /*OpIdx*/1, /*OtherMI*/2, /*OtherOpIdx*/1,
        // MIs[3] VOP3Mods:src1:src1_mods
        GIM_CheckIsSameOperand, /*MI*/3, /*OpIdx*/2, /*OtherMI*/2, /*OtherOpIdx*/2,
        GIM_CheckCxxInsnPredicate, /*MI*/0, /*FnId*/GIMT_Encode2(GICXXPred_MI_Predicate_fmaxnum_like_nnan),
        GIM_CheckIsSafeToFold, /*InsnID*/1,
        GIM_CheckIsSafeToFold, /*InsnID*/2,
        GIM_CheckIsSafeToFold, /*InsnID*/3,
        GIM_CheckComplexPattern, /*MI*/1, /*Op*/1, /*Renderer*/GIMT_Encode2(0), GIMT_Encode2(GICP_gi_vop3mods),
        GIM_CheckComplexPattern, /*MI*/2, /*Op*/1, /*Renderer*/GIMT_Encode2(1), GIMT_Encode2(GICP_gi_vop3mods),
        GIM_CheckComplexPattern, /*MI*/2, /*Op*/2, /*Renderer*/GIMT_Encode2(2), GIMT_Encode2(GICP_gi_vop3mods),
        // (fmaxnum_ieee:{ *:[f16] } (fminnum_ieee:{ *:[f16] } (VOP3Mods:{ *:[f16] } f16:{ *:[f16] }:$src2, i32:{ *:[i32] }:$src2_mods), (fmaxnum_ieee:{ *:[f16] } (VOP3Mods:{ *:[f16] } f16:{ *:[f16] }:$src0, i32:{ *:[i32] }:$src0_mods), (VOP3Mods:{ *:[f16] } f16:{ *:[f16] }:$src1, i32:{ *:[i32] }:$src1_mods))), (fminnum:{ *:[f16] } (VOP3Mods:{ *:[f16] } f16:{ *:[f16] }:$src0, i32:{ *:[i32] }:$src0_mods), (VOP3Mods:{ *:[f16] } f16:{ *:[f16] }:$src1, i32:{ *:[i32] }:$src1_mods)))<<P:Predicate_fmaxnum_like_nnan>>  =>  (V_MED3_F16_e64:{ *:[f16] } ?:{ *:[i32] }:$src0_mods, ?:{ *:[f16] }:$src0, ?:{ *:[i32] }:$src1_mods, ?:{ *:[f16] }:$src1, ?:{ *:[i32] }:$src2_mods, ?:{ *:[f16] }:$src2, 0:{ *:[i1] })
        GIR_BuildMI, /*InsnID*/0, /*Opcode*/GIMT_Encode2(AMDGPU::V_MED3_F16_e64),
        GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/0, // DstI[vdst]
        GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(1), /*SubOperand*/1, // src0_mods
        GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(1), /*SubOperand*/0, // src0
        GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(2), /*SubOperand*/1, // src1_mods
        GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(2), /*SubOperand*/0, // src1
        GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/1, // src2_mods
        GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/0, // src2
        GIR_AddImm8, /*InsnID*/0, /*Imm*/0,
        GIR_AddImm8, /*InsnID*/0, /*Imm*/0,
        GIR_AddImm8, /*InsnID*/0, /*Imm*/0,
        GIR_ConstrainSelectedInstOperands, /*InsnID*/0,
        GIR_EraseFromParent, /*InsnID*/0,
        // GIR_Coverage, 10601,
        GIR_Done,
      // Label 5022: @361764
      GIM_Try, /*On fail goto*//*Label 5023*/ GIMT_Encode4(361910), // Rule ID 10602 //
        GIM_CheckFeatures, GIMT_Encode2(GIFBS_isGFX9Plus),
        GIM_CheckRegBankForClass, /*MI*/0, /*Op*/0, /*RC*/GIMT_Encode2(AMDGPU::VGPR_32RegClassID),
        GIM_RecordInsn, /*DefineMI*/1, /*MI*/0, /*OpIdx*/1, // MIs[1]
        GIM_CheckOpcode, /*MI*/1, GIMT_Encode2(TargetOpcode::G_FMINNUM_IEEE),
        GIM_CheckType, /*MI*/1, /*Op*/1, /*Type*/GILLT_s16,
        GIM_CheckType, /*MI*/1, /*Op*/2, /*Type*/GILLT_s16,
        GIM_RecordInsn, /*DefineMI*/2, /*MI*/1, /*OpIdx*/2, // MIs[2]
        GIM_CheckOpcode, /*MI*/2, GIMT_Encode2(TargetOpcode::G_FMAXNUM_IEEE),
        GIM_CheckType, /*MI*/2, /*Op*/1, /*Type*/GILLT_s16,
        GIM_CheckType, /*MI*/2, /*Op*/2, /*Type*/GILLT_s16,
        GIM_RecordInsn, /*DefineMI*/3, /*MI*/0, /*OpIdx*/2, // MIs[3]
        GIM_CheckOpcode, /*MI*/3, GIMT_Encode2(TargetOpcode::G_FMINNUM),
        // MIs[3] VOP3Mods:src1:src1_mods
        GIM_CheckIsSameOperand, /*MI*/3, /*OpIdx*/1, /*OtherMI*/2, /*OtherOpIdx*/2,
        // MIs[3] VOP3Mods:src0:src0_mods
        GIM_CheckIsSameOperand, /*MI*/3, /*OpIdx*/2, /*OtherMI*/2, /*OtherOpIdx*/1,
        GIM_CheckCxxInsnPredicate, /*MI*/0, /*FnId*/GIMT_Encode2(GICXXPred_MI_Predicate_fmaxnum_like_nnan),
        GIM_CheckIsSafeToFold, /*InsnID*/1,
        GIM_CheckIsSafeToFold, /*InsnID*/2,
        GIM_CheckIsSafeToFold, /*InsnID*/3,
        GIM_CheckComplexPattern, /*MI*/1, /*Op*/1, /*Renderer*/GIMT_Encode2(0), GIMT_Encode2(GICP_gi_vop3mods),
        GIM_CheckComplexPattern, /*MI*/2, /*Op*/1, /*Renderer*/GIMT_Encode2(1), GIMT_Encode2(GICP_gi_vop3mods),
        GIM_CheckComplexPattern, /*MI*/2, /*Op*/2, /*Renderer*/GIMT_Encode2(2), GIMT_Encode2(GICP_gi_vop3mods),
        // (fmaxnum_ieee:{ *:[f16] } (fminnum_ieee:{ *:[f16] } (VOP3Mods:{ *:[f16] } f16:{ *:[f16] }:$src2, i32:{ *:[i32] }:$src2_mods), (fmaxnum_ieee:{ *:[f16] } (VOP3Mods:{ *:[f16] } f16:{ *:[f16] }:$src0, i32:{ *:[i32] }:$src0_mods), (VOP3Mods:{ *:[f16] } f16:{ *:[f16] }:$src1, i32:{ *:[i32] }:$src1_mods))), (fminnum:{ *:[f16] } (VOP3Mods:{ *:[f16] } f16:{ *:[f16] }:$src1, i32:{ *:[i32] }:$src1_mods), (VOP3Mods:{ *:[f16] } f16:{ *:[f16] }:$src0, i32:{ *:[i32] }:$src0_mods)))<<P:Predicate_fmaxnum_like_nnan>>  =>  (V_MED3_F16_e64:{ *:[f16] } ?:{ *:[i32] }:$src0_mods, ?:{ *:[f16] }:$src0, ?:{ *:[i32] }:$src1_mods, ?:{ *:[f16] }:$src1, ?:{ *:[i32] }:$src2_mods, ?:{ *:[f16] }:$src2, 0:{ *:[i1] })
        GIR_BuildMI, /*InsnID*/0, /*Opcode*/GIMT_Encode2(AMDGPU::V_MED3_F16_e64),
        GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/0, // DstI[vdst]
        GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(1), /*SubOperand*/1, // src0_mods
        GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(1), /*SubOperand*/0, // src0
        GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(2), /*SubOperand*/1, // src1_mods
        GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(2), /*SubOperand*/0, // src1
        GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/1, // src2_mods
        GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/0, // src2
        GIR_AddImm8, /*InsnID*/0, /*Imm*/0,
        GIR_AddImm8, /*InsnID*/0, /*Imm*/0,
        GIR_AddImm8, /*InsnID*/0, /*Imm*/0,
        GIR_ConstrainSelectedInstOperands, /*InsnID*/0,
        GIR_EraseFromParent, /*InsnID*/0,
        // GIR_Coverage, 10602,
        GIR_Done,
      // Label 5023: @361910
      GIM_Try, /*On fail goto*//*Label 5024*/ GIMT_Encode4(362056), // Rule ID 10603 //
        GIM_CheckFeatures, GIMT_Encode2(GIFBS_isGFX9Plus),
        GIM_CheckRegBankForClass, /*MI*/0, /*Op*/0, /*RC*/GIMT_Encode2(AMDGPU::VGPR_32RegClassID),
        GIM_RecordInsn, /*DefineMI*/1, /*MI*/0, /*OpIdx*/1, // MIs[1]
        GIM_CheckOpcode, /*MI*/1, GIMT_Encode2(TargetOpcode::G_FMINNUM_IEEE),
        GIM_CheckType, /*MI*/1, /*Op*/1, /*Type*/GILLT_s16,
        GIM_CheckType, /*MI*/1, /*Op*/2, /*Type*/GILLT_s16,
        GIM_RecordInsn, /*DefineMI*/2, /*MI*/1, /*OpIdx*/2, // MIs[2]
        GIM_CheckOpcode, /*MI*/2, GIMT_Encode2(TargetOpcode::G_FMAXNUM_IEEE),
        GIM_CheckType, /*MI*/2, /*Op*/1, /*Type*/GILLT_s16,
        GIM_CheckType, /*MI*/2, /*Op*/2, /*Type*/GILLT_s16,
        GIM_RecordInsn, /*DefineMI*/3, /*MI*/0, /*OpIdx*/2, // MIs[3]
        GIM_CheckOpcode, /*MI*/3, GIMT_Encode2(TargetOpcode::G_FMINNUM),
        // MIs[3] VOP3Mods:src0:src0_mods
        GIM_CheckIsSameOperand, /*MI*/3, /*OpIdx*/1, /*OtherMI*/2, /*OtherOpIdx*/2,
        // MIs[3] VOP3Mods:src1:src1_mods
        GIM_CheckIsSameOperand, /*MI*/3, /*OpIdx*/2, /*OtherMI*/2, /*OtherOpIdx*/1,
        GIM_CheckCxxInsnPredicate, /*MI*/0, /*FnId*/GIMT_Encode2(GICXXPred_MI_Predicate_fmaxnum_like_nnan),
        GIM_CheckIsSafeToFold, /*InsnID*/1,
        GIM_CheckIsSafeToFold, /*InsnID*/2,
        GIM_CheckIsSafeToFold, /*InsnID*/3,
        GIM_CheckComplexPattern, /*MI*/1, /*Op*/1, /*Renderer*/GIMT_Encode2(0), GIMT_Encode2(GICP_gi_vop3mods),
        GIM_CheckComplexPattern, /*MI*/2, /*Op*/1, /*Renderer*/GIMT_Encode2(1), GIMT_Encode2(GICP_gi_vop3mods),
        GIM_CheckComplexPattern, /*MI*/2, /*Op*/2, /*Renderer*/GIMT_Encode2(2), GIMT_Encode2(GICP_gi_vop3mods),
        // (fmaxnum_ieee:{ *:[f16] } (fminnum_ieee:{ *:[f16] } (VOP3Mods:{ *:[f16] } f16:{ *:[f16] }:$src2, i32:{ *:[i32] }:$src2_mods), (fmaxnum_ieee:{ *:[f16] } (VOP3Mods:{ *:[f16] } f16:{ *:[f16] }:$src1, i32:{ *:[i32] }:$src1_mods), (VOP3Mods:{ *:[f16] } f16:{ *:[f16] }:$src0, i32:{ *:[i32] }:$src0_mods))), (fminnum:{ *:[f16] } (VOP3Mods:{ *:[f16] } f16:{ *:[f16] }:$src0, i32:{ *:[i32] }:$src0_mods), (VOP3Mods:{ *:[f16] } f16:{ *:[f16] }:$src1, i32:{ *:[i32] }:$src1_mods)))<<P:Predicate_fmaxnum_like_nnan>>  =>  (V_MED3_F16_e64:{ *:[f16] } ?:{ *:[i32] }:$src0_mods, ?:{ *:[f16] }:$src0, ?:{ *:[i32] }:$src1_mods, ?:{ *:[f16] }:$src1, ?:{ *:[i32] }:$src2_mods, ?:{ *:[f16] }:$src2, 0:{ *:[i1] })
        GIR_BuildMI, /*InsnID*/0, /*Opcode*/GIMT_Encode2(AMDGPU::V_MED3_F16_e64),
        GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/0, // DstI[vdst]
        GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(2), /*SubOperand*/1, // src0_mods
        GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(2), /*SubOperand*/0, // src0
        GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(1), /*SubOperand*/1, // src1_mods
        GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(1), /*SubOperand*/0, // src1
        GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/1, // src2_mods
        GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/0, // src2
        GIR_AddImm8, /*InsnID*/0, /*Imm*/0,
        GIR_AddImm8, /*InsnID*/0, /*Imm*/0,
        GIR_AddImm8, /*InsnID*/0, /*Imm*/0,
        GIR_ConstrainSelectedInstOperands, /*InsnID*/0,
        GIR_EraseFromParent, /*InsnID*/0,
        // GIR_Coverage, 10603,
        GIR_Done,
      // Label 5024: @362056
      GIM_Try, /*On fail goto*//*Label 5025*/ GIMT_Encode4(362202), // Rule ID 10604 //
        GIM_CheckFeatures, GIMT_Encode2(GIFBS_isGFX9Plus),
        GIM_CheckRegBankForClass, /*MI*/0, /*Op*/0, /*RC*/GIMT_Encode2(AMDGPU::VGPR_32RegClassID),
        GIM_RecordInsn, /*DefineMI*/1, /*MI*/0, /*OpIdx*/1, // MIs[1]
        GIM_CheckOpcode, /*MI*/1, GIMT_Encode2(TargetOpcode::G_FMINNUM_IEEE),
        GIM_CheckType, /*MI*/1, /*Op*/1, /*Type*/GILLT_s16,
        GIM_CheckType, /*MI*/1, /*Op*/2, /*Type*/GILLT_s16,
        GIM_RecordInsn, /*DefineMI*/2, /*MI*/1, /*OpIdx*/2, // MIs[2]
        GIM_CheckOpcode, /*MI*/2, GIMT_Encode2(TargetOpcode::G_FMAXNUM_IEEE),
        GIM_CheckType, /*MI*/2, /*Op*/1, /*Type*/GILLT_s16,
        GIM_CheckType, /*MI*/2, /*Op*/2, /*Type*/GILLT_s16,
        GIM_RecordInsn, /*DefineMI*/3, /*MI*/0, /*OpIdx*/2, // MIs[3]
        GIM_CheckOpcode, /*MI*/3, GIMT_Encode2(TargetOpcode::G_FMINNUM),
        // MIs[3] VOP3Mods:src1:src1_mods
        GIM_CheckIsSameOperand, /*MI*/3, /*OpIdx*/1, /*OtherMI*/2, /*OtherOpIdx*/1,
        // MIs[3] VOP3Mods:src0:src0_mods
        GIM_CheckIsSameOperand, /*MI*/3, /*OpIdx*/2, /*OtherMI*/2, /*OtherOpIdx*/2,
        GIM_CheckCxxInsnPredicate, /*MI*/0, /*FnId*/GIMT_Encode2(GICXXPred_MI_Predicate_fmaxnum_like_nnan),
        GIM_CheckIsSafeToFold, /*InsnID*/1,
        GIM_CheckIsSafeToFold, /*InsnID*/2,
        GIM_CheckIsSafeToFold, /*InsnID*/3,
        GIM_CheckComplexPattern, /*MI*/1, /*Op*/1, /*Renderer*/GIMT_Encode2(0), GIMT_Encode2(GICP_gi_vop3mods),
        GIM_CheckComplexPattern, /*MI*/2, /*Op*/1, /*Renderer*/GIMT_Encode2(1), GIMT_Encode2(GICP_gi_vop3mods),
        GIM_CheckComplexPattern, /*MI*/2, /*Op*/2, /*Renderer*/GIMT_Encode2(2), GIMT_Encode2(GICP_gi_vop3mods),
        // (fmaxnum_ieee:{ *:[f16] } (fminnum_ieee:{ *:[f16] } (VOP3Mods:{ *:[f16] } f16:{ *:[f16] }:$src2, i32:{ *:[i32] }:$src2_mods), (fmaxnum_ieee:{ *:[f16] } (VOP3Mods:{ *:[f16] } f16:{ *:[f16] }:$src1, i32:{ *:[i32] }:$src1_mods), (VOP3Mods:{ *:[f16] } f16:{ *:[f16] }:$src0, i32:{ *:[i32] }:$src0_mods))), (fminnum:{ *:[f16] } (VOP3Mods:{ *:[f16] } f16:{ *:[f16] }:$src1, i32:{ *:[i32] }:$src1_mods), (VOP3Mods:{ *:[f16] } f16:{ *:[f16] }:$src0, i32:{ *:[i32] }:$src0_mods)))<<P:Predicate_fmaxnum_like_nnan>>  =>  (V_MED3_F16_e64:{ *:[f16] } ?:{ *:[i32] }:$src0_mods, ?:{ *:[f16] }:$src0, ?:{ *:[i32] }:$src1_mods, ?:{ *:[f16] }:$src1, ?:{ *:[i32] }:$src2_mods, ?:{ *:[f16] }:$src2, 0:{ *:[i1] })
        GIR_BuildMI, /*InsnID*/0, /*Opcode*/GIMT_Encode2(AMDGPU::V_MED3_F16_e64),
        GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/0, // DstI[vdst]
        GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(2), /*SubOperand*/1, // src0_mods
        GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(2), /*SubOperand*/0, // src0
        GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(1), /*SubOperand*/1, // src1_mods
        GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(1), /*SubOperand*/0, // src1
        GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/1, // src2_mods
        GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/0, // src2
        GIR_AddImm8, /*InsnID*/0, /*Imm*/0,
        GIR_AddImm8, /*InsnID*/0, /*Imm*/0,
        GIR_AddImm8, /*InsnID*/0, /*Imm*/0,
        GIR_ConstrainSelectedInstOperands, /*InsnID*/0,
        GIR_EraseFromParent, /*InsnID*/0,
        // GIR_Coverage, 10604,
        GIR_Done,
      // Label 5025: @362202
      GIM_Try, /*On fail goto*//*Label 5026*/ GIMT_Encode4(362348), // Rule ID 10541 //
        GIM_CheckFeatures, GIMT_Encode2(GIFBS_isGFX9Plus),
        GIM_CheckRegBankForClass, /*MI*/0, /*Op*/0, /*RC*/GIMT_Encode2(AMDGPU::VGPR_32RegClassID),
        GIM_RecordInsn, /*DefineMI*/1, /*MI*/0, /*OpIdx*/1, // MIs[1]
        GIM_CheckOpcode, /*MI*/1, GIMT_Encode2(TargetOpcode::G_FMINNUM_IEEE),
        GIM_CheckType, /*MI*/1, /*Op*/1, /*Type*/GILLT_s16,
        GIM_CheckType, /*MI*/1, /*Op*/2, /*Type*/GILLT_s16,
        GIM_RecordInsn, /*DefineMI*/2, /*MI*/1, /*OpIdx*/2, // MIs[2]
        GIM_CheckOpcode, /*MI*/2, GIMT_Encode2(TargetOpcode::G_FMAXNUM_IEEE),
        GIM_CheckType, /*MI*/2, /*Op*/1, /*Type*/GILLT_s16,
        GIM_CheckType, /*MI*/2, /*Op*/2, /*Type*/GILLT_s16,
        GIM_RecordInsn, /*DefineMI*/3, /*MI*/0, /*OpIdx*/2, // MIs[3]
        GIM_CheckOpcode, /*MI*/3, GIMT_Encode2(TargetOpcode::G_FMINNUM_IEEE),
        // MIs[3] VOP3Mods:src0:src0_mods
        GIM_CheckIsSameOperand, /*MI*/3, /*OpIdx*/1, /*OtherMI*/2, /*OtherOpIdx*/1,
        // MIs[3] VOP3Mods:src1:src1_mods
        GIM_CheckIsSameOperand, /*MI*/3, /*OpIdx*/2, /*OtherMI*/2, /*OtherOpIdx*/2,
        GIM_CheckCxxInsnPredicate, /*MI*/0, /*FnId*/GIMT_Encode2(GICXXPred_MI_Predicate_fmaxnum_like_nnan),
        GIM_CheckIsSafeToFold, /*InsnID*/1,
        GIM_CheckIsSafeToFold, /*InsnID*/2,
        GIM_CheckIsSafeToFold, /*InsnID*/3,
        GIM_CheckComplexPattern, /*MI*/1, /*Op*/1, /*Renderer*/GIMT_Encode2(0), GIMT_Encode2(GICP_gi_vop3mods),
        GIM_CheckComplexPattern, /*MI*/2, /*Op*/1, /*Renderer*/GIMT_Encode2(1), GIMT_Encode2(GICP_gi_vop3mods),
        GIM_CheckComplexPattern, /*MI*/2, /*Op*/2, /*Renderer*/GIMT_Encode2(2), GIMT_Encode2(GICP_gi_vop3mods),
        // (fmaxnum_ieee:{ *:[f16] } (fminnum_ieee:{ *:[f16] } (VOP3Mods:{ *:[f16] } f16:{ *:[f16] }:$src2, i32:{ *:[i32] }:$src2_mods), (fmaxnum_ieee:{ *:[f16] } (VOP3Mods:{ *:[f16] } f16:{ *:[f16] }:$src0, i32:{ *:[i32] }:$src0_mods), (VOP3Mods:{ *:[f16] } f16:{ *:[f16] }:$src1, i32:{ *:[i32] }:$src1_mods))), (fminnum_ieee:{ *:[f16] } (VOP3Mods:{ *:[f16] } f16:{ *:[f16] }:$src0, i32:{ *:[i32] }:$src0_mods), (VOP3Mods:{ *:[f16] } f16:{ *:[f16] }:$src1, i32:{ *:[i32] }:$src1_mods)))<<P:Predicate_fmaxnum_like_nnan>>  =>  (V_MED3_F16_e64:{ *:[f16] } ?:{ *:[i32] }:$src0_mods, ?:{ *:[f16] }:$src0, ?:{ *:[i32] }:$src1_mods, ?:{ *:[f16] }:$src1, ?:{ *:[i32] }:$src2_mods, ?:{ *:[f16] }:$src2, 0:{ *:[i1] })
        GIR_BuildMI, /*InsnID*/0, /*Opcode*/GIMT_Encode2(AMDGPU::V_MED3_F16_e64),
        GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/0, // DstI[vdst]
        GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(1), /*SubOperand*/1, // src0_mods
        GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(1), /*SubOperand*/0, // src0
        GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(2), /*SubOperand*/1, // src1_mods
        GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(2), /*SubOperand*/0, // src1
        GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/1, // src2_mods
        GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/0, // src2
        GIR_AddImm8, /*InsnID*/0, /*Imm*/0,
        GIR_AddImm8, /*InsnID*/0, /*Imm*/0,
        GIR_AddImm8, /*InsnID*/0, /*Imm*/0,
        GIR_ConstrainSelectedInstOperands, /*InsnID*/0,
        GIR_EraseFromParent, /*InsnID*/0,
        // GIR_Coverage, 10541,
        GIR_Done,
      // Label 5026: @362348
      GIM_Try, /*On fail goto*//*Label 5027*/ GIMT_Encode4(362494), // Rule ID 10542 //
        GIM_CheckFeatures, GIMT_Encode2(GIFBS_isGFX9Plus),
        GIM_CheckRegBankForClass, /*MI*/0, /*Op*/0, /*RC*/GIMT_Encode2(AMDGPU::VGPR_32RegClassID),
        GIM_RecordInsn, /*DefineMI*/1, /*MI*/0, /*OpIdx*/1, // MIs[1]
        GIM_CheckOpcode, /*MI*/1, GIMT_Encode2(TargetOpcode::G_FMINNUM_IEEE),
        GIM_CheckType, /*MI*/1, /*Op*/1, /*Type*/GILLT_s16,
        GIM_CheckType, /*MI*/1, /*Op*/2, /*Type*/GILLT_s16,
        GIM_RecordInsn, /*DefineMI*/2, /*MI*/1, /*OpIdx*/2, // MIs[2]
        GIM_CheckOpcode, /*MI*/2, GIMT_Encode2(TargetOpcode::G_FMAXNUM_IEEE),
        GIM_CheckType, /*MI*/2, /*Op*/1, /*Type*/GILLT_s16,
        GIM_CheckType, /*MI*/2, /*Op*/2, /*Type*/GILLT_s16,
        GIM_RecordInsn, /*DefineMI*/3, /*MI*/0, /*OpIdx*/2, // MIs[3]
        GIM_CheckOpcode, /*MI*/3, GIMT_Encode2(TargetOpcode::G_FMINNUM_IEEE),
        // MIs[3] VOP3Mods:src1:src1_mods
        GIM_CheckIsSameOperand, /*MI*/3, /*OpIdx*/1, /*OtherMI*/2, /*OtherOpIdx*/2,
        // MIs[3] VOP3Mods:src0:src0_mods
        GIM_CheckIsSameOperand, /*MI*/3, /*OpIdx*/2, /*OtherMI*/2, /*OtherOpIdx*/1,
        GIM_CheckCxxInsnPredicate, /*MI*/0, /*FnId*/GIMT_Encode2(GICXXPred_MI_Predicate_fmaxnum_like_nnan),
        GIM_CheckIsSafeToFold, /*InsnID*/1,
        GIM_CheckIsSafeToFold, /*InsnID*/2,
        GIM_CheckIsSafeToFold, /*InsnID*/3,
        GIM_CheckComplexPattern, /*MI*/1, /*Op*/1, /*Renderer*/GIMT_Encode2(0), GIMT_Encode2(GICP_gi_vop3mods),
        GIM_CheckComplexPattern, /*MI*/2, /*Op*/1, /*Renderer*/GIMT_Encode2(1), GIMT_Encode2(GICP_gi_vop3mods),
        GIM_CheckComplexPattern, /*MI*/2, /*Op*/2, /*Renderer*/GIMT_Encode2(2), GIMT_Encode2(GICP_gi_vop3mods),
        // (fmaxnum_ieee:{ *:[f16] } (fminnum_ieee:{ *:[f16] } (VOP3Mods:{ *:[f16] } f16:{ *:[f16] }:$src2, i32:{ *:[i32] }:$src2_mods), (fmaxnum_ieee:{ *:[f16] } (VOP3Mods:{ *:[f16] } f16:{ *:[f16] }:$src0, i32:{ *:[i32] }:$src0_mods), (VOP3Mods:{ *:[f16] } f16:{ *:[f16] }:$src1, i32:{ *:[i32] }:$src1_mods))), (fminnum_ieee:{ *:[f16] } (VOP3Mods:{ *:[f16] } f16:{ *:[f16] }:$src1, i32:{ *:[i32] }:$src1_mods), (VOP3Mods:{ *:[f16] } f16:{ *:[f16] }:$src0, i32:{ *:[i32] }:$src0_mods)))<<P:Predicate_fmaxnum_like_nnan>>  =>  (V_MED3_F16_e64:{ *:[f16] } ?:{ *:[i32] }:$src0_mods, ?:{ *:[f16] }:$src0, ?:{ *:[i32] }:$src1_mods, ?:{ *:[f16] }:$src1, ?:{ *:[i32] }:$src2_mods, ?:{ *:[f16] }:$src2, 0:{ *:[i1] })
        GIR_BuildMI, /*InsnID*/0, /*Opcode*/GIMT_Encode2(AMDGPU::V_MED3_F16_e64),
        GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/0, // DstI[vdst]
        GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(1), /*SubOperand*/1, // src0_mods
        GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(1), /*SubOperand*/0, // src0
        GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(2), /*SubOperand*/1, // src1_mods
        GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(2), /*SubOperand*/0, // src1
        GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/1, // src2_mods
        GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/0, // src2
        GIR_AddImm8, /*InsnID*/0, /*Imm*/0,
        GIR_AddImm8, /*InsnID*/0, /*Imm*/0,
        GIR_AddImm8, /*InsnID*/0, /*Imm*/0,
        GIR_ConstrainSelectedInstOperands, /*InsnID*/0,
        GIR_EraseFromParent, /*InsnID*/0,
        // GIR_Coverage, 10542,
        GIR_Done,
      // Label 5027: @362494
      GIM_Try, /*On fail goto*//*Label 5028*/ GIMT_Encode4(362640), // Rule ID 10543 //
        GIM_CheckFeatures, GIMT_Encode2(GIFBS_isGFX9Plus),
        GIM_CheckRegBankForClass, /*MI*/0, /*Op*/0, /*RC*/GIMT_Encode2(AMDGPU::VGPR_32RegClassID),
        GIM_RecordInsn, /*DefineMI*/1, /*MI*/0, /*OpIdx*/1, // MIs[1]
        GIM_CheckOpcode, /*MI*/1, GIMT_Encode2(TargetOpcode::G_FMINNUM_IEEE),
        GIM_CheckType, /*MI*/1, /*Op*/1, /*Type*/GILLT_s16,
        GIM_CheckType, /*MI*/1, /*Op*/2, /*Type*/GILLT_s16,
        GIM_RecordInsn, /*DefineMI*/2, /*MI*/1, /*OpIdx*/2, // MIs[2]
        GIM_CheckOpcode, /*MI*/2, GIMT_Encode2(TargetOpcode::G_FMAXNUM_IEEE),
        GIM_CheckType, /*MI*/2, /*Op*/1, /*Type*/GILLT_s16,
        GIM_CheckType, /*MI*/2, /*Op*/2, /*Type*/GILLT_s16,
        GIM_RecordInsn, /*DefineMI*/3, /*MI*/0, /*OpIdx*/2, // MIs[3]
        GIM_CheckOpcode, /*MI*/3, GIMT_Encode2(TargetOpcode::G_FMINNUM_IEEE),
        // MIs[3] VOP3Mods:src0:src0_mods
        GIM_CheckIsSameOperand, /*MI*/3, /*OpIdx*/1, /*OtherMI*/2, /*OtherOpIdx*/2,
        // MIs[3] VOP3Mods:src1:src1_mods
        GIM_CheckIsSameOperand, /*MI*/3, /*OpIdx*/2, /*OtherMI*/2, /*OtherOpIdx*/1,
        GIM_CheckCxxInsnPredicate, /*MI*/0, /*FnId*/GIMT_Encode2(GICXXPred_MI_Predicate_fmaxnum_like_nnan),
        GIM_CheckIsSafeToFold, /*InsnID*/1,
        GIM_CheckIsSafeToFold, /*InsnID*/2,
        GIM_CheckIsSafeToFold, /*InsnID*/3,
        GIM_CheckComplexPattern, /*MI*/1, /*Op*/1, /*Renderer*/GIMT_Encode2(0), GIMT_Encode2(GICP_gi_vop3mods),
        GIM_CheckComplexPattern, /*MI*/2, /*Op*/1, /*Renderer*/GIMT_Encode2(1), GIMT_Encode2(GICP_gi_vop3mods),
        GIM_CheckComplexPattern, /*MI*/2, /*Op*/2, /*Renderer*/GIMT_Encode2(2), GIMT_Encode2(GICP_gi_vop3mods),
        // (fmaxnum_ieee:{ *:[f16] } (fminnum_ieee:{ *:[f16] } (VOP3Mods:{ *:[f16] } f16:{ *:[f16] }:$src2, i32:{ *:[i32] }:$src2_mods), (fmaxnum_ieee:{ *:[f16] } (VOP3Mods:{ *:[f16] } f16:{ *:[f16] }:$src1, i32:{ *:[i32] }:$src1_mods), (VOP3Mods:{ *:[f16] } f16:{ *:[f16] }:$src0, i32:{ *:[i32] }:$src0_mods))), (fminnum_ieee:{ *:[f16] } (VOP3Mods:{ *:[f16] } f16:{ *:[f16] }:$src0, i32:{ *:[i32] }:$src0_mods), (VOP3Mods:{ *:[f16] } f16:{ *:[f16] }:$src1, i32:{ *:[i32] }:$src1_mods)))<<P:Predicate_fmaxnum_like_nnan>>  =>  (V_MED3_F16_e64:{ *:[f16] } ?:{ *:[i32] }:$src0_mods, ?:{ *:[f16] }:$src0, ?:{ *:[i32] }:$src1_mods, ?:{ *:[f16] }:$src1, ?:{ *:[i32] }:$src2_mods, ?:{ *:[f16] }:$src2, 0:{ *:[i1] })
        GIR_BuildMI, /*InsnID*/0, /*Opcode*/GIMT_Encode2(AMDGPU::V_MED3_F16_e64),
        GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/0, // DstI[vdst]
        GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(2), /*SubOperand*/1, // src0_mods
        GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(2), /*SubOperand*/0, // src0
        GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(1), /*SubOperand*/1, // src1_mods
        GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(1), /*SubOperand*/0, // src1
        GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/1, // src2_mods
        GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/0, // src2
        GIR_AddImm8, /*InsnID*/0, /*Imm*/0,
        GIR_AddImm8, /*InsnID*/0, /*Imm*/0,
        GIR_AddImm8, /*InsnID*/0, /*Imm*/0,
        GIR_ConstrainSelectedInstOperands, /*InsnID*/0,
        GIR_EraseFromParent, /*InsnID*/0,
        // GIR_Coverage, 10543,
        GIR_Done,
      // Label 5028: @362640
      GIM_Try, /*On fail goto*//*Label 5029*/ GIMT_Encode4(362786), // Rule ID 10544 //
        GIM_CheckFeatures, GIMT_Encode2(GIFBS_isGFX9Plus),
        GIM_CheckRegBankForClass, /*MI*/0, /*Op*/0, /*RC*/GIMT_Encode2(AMDGPU::VGPR_32RegClassID),
        GIM_RecordInsn, /*DefineMI*/1, /*MI*/0, /*OpIdx*/1, // MIs[1]
        GIM_CheckOpcode, /*MI*/1, GIMT_Encode2(TargetOpcode::G_FMINNUM_IEEE),
        GIM_CheckType, /*MI*/1, /*Op*/1, /*Type*/GILLT_s16,
        GIM_CheckType, /*MI*/1, /*Op*/2, /*Type*/GILLT_s16,
        GIM_RecordInsn, /*DefineMI*/2, /*MI*/1, /*OpIdx*/2, // MIs[2]
        GIM_CheckOpcode, /*MI*/2, GIMT_Encode2(TargetOpcode::G_FMAXNUM_IEEE),
        GIM_CheckType, /*MI*/2, /*Op*/1, /*Type*/GILLT_s16,
        GIM_CheckType, /*MI*/2, /*Op*/2, /*Type*/GILLT_s16,
        GIM_RecordInsn, /*DefineMI*/3, /*MI*/0, /*OpIdx*/2, // MIs[3]
        GIM_CheckOpcode, /*MI*/3, GIMT_Encode2(TargetOpcode::G_FMINNUM_IEEE),
        // MIs[3] VOP3Mods:src1:src1_mods
        GIM_CheckIsSameOperand, /*MI*/3, /*OpIdx*/1, /*OtherMI*/2, /*OtherOpIdx*/1,
        // MIs[3] VOP3Mods:src0:src0_mods
        GIM_CheckIsSameOperand, /*MI*/3, /*OpIdx*/2, /*OtherMI*/2, /*OtherOpIdx*/2,
        GIM_CheckCxxInsnPredicate, /*MI*/0, /*FnId*/GIMT_Encode2(GICXXPred_MI_Predicate_fmaxnum_like_nnan),
        GIM_CheckIsSafeToFold, /*InsnID*/1,
        GIM_CheckIsSafeToFold, /*InsnID*/2,
        GIM_CheckIsSafeToFold, /*InsnID*/3,
        GIM_CheckComplexPattern, /*MI*/1, /*Op*/1, /*Renderer*/GIMT_Encode2(0), GIMT_Encode2(GICP_gi_vop3mods),
        GIM_CheckComplexPattern, /*MI*/2, /*Op*/1, /*Renderer*/GIMT_Encode2(1), GIMT_Encode2(GICP_gi_vop3mods),
        GIM_CheckComplexPattern, /*MI*/2, /*Op*/2, /*Renderer*/GIMT_Encode2(2), GIMT_Encode2(GICP_gi_vop3mods),
        // (fmaxnum_ieee:{ *:[f16] } (fminnum_ieee:{ *:[f16] } (VOP3Mods:{ *:[f16] } f16:{ *:[f16] }:$src2, i32:{ *:[i32] }:$src2_mods), (fmaxnum_ieee:{ *:[f16] } (VOP3Mods:{ *:[f16] } f16:{ *:[f16] }:$src1, i32:{ *:[i32] }:$src1_mods), (VOP3Mods:{ *:[f16] } f16:{ *:[f16] }:$src0, i32:{ *:[i32] }:$src0_mods))), (fminnum_ieee:{ *:[f16] } (VOP3Mods:{ *:[f16] } f16:{ *:[f16] }:$src1, i32:{ *:[i32] }:$src1_mods), (VOP3Mods:{ *:[f16] } f16:{ *:[f16] }:$src0, i32:{ *:[i32] }:$src0_mods)))<<P:Predicate_fmaxnum_like_nnan>>  =>  (V_MED3_F16_e64:{ *:[f16] } ?:{ *:[i32] }:$src0_mods, ?:{ *:[f16] }:$src0, ?:{ *:[i32] }:$src1_mods, ?:{ *:[f16] }:$src1, ?:{ *:[i32] }:$src2_mods, ?:{ *:[f16] }:$src2, 0:{ *:[i1] })
        GIR_BuildMI, /*InsnID*/0, /*Opcode*/GIMT_Encode2(AMDGPU::V_MED3_F16_e64),
        GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/0, // DstI[vdst]
        GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(2), /*SubOperand*/1, // src0_mods
        GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(2), /*SubOperand*/0, // src0
        GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(1), /*SubOperand*/1, // src1_mods
        GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(1), /*SubOperand*/0, // src1
        GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/1, // src2_mods
        GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/0, // src2
        GIR_AddImm8, /*InsnID*/0, /*Imm*/0,
        GIR_AddImm8, /*InsnID*/0, /*Imm*/0,
        GIR_AddImm8, /*InsnID*/0, /*Imm*/0,
        GIR_ConstrainSelectedInstOperands, /*InsnID*/0,
        GIR_EraseFromParent, /*InsnID*/0,
        // GIR_Coverage, 10544,
        GIR_Done,
      // Label 5029: @362786
      GIM_Try, /*On fail goto*//*Label 5030*/ GIMT_Encode4(362932), // Rule ID 10612 //
        GIM_CheckFeatures, GIMT_Encode2(GIFBS_isGFX9Plus),
        GIM_CheckRegBankForClass, /*MI*/0, /*Op*/0, /*RC*/GIMT_Encode2(AMDGPU::VGPR_32RegClassID),
        GIM_RecordInsn, /*DefineMI*/1, /*MI*/0, /*OpIdx*/1, // MIs[1]
        GIM_CheckOpcode, /*MI*/1, GIMT_Encode2(TargetOpcode::G_FMINNUM_IEEE),
        GIM_CheckType, /*MI*/1, /*Op*/1, /*Type*/GILLT_s16,
        GIM_CheckType, /*MI*/1, /*Op*/2, /*Type*/GILLT_s16,
        GIM_RecordInsn, /*DefineMI*/2, /*MI*/1, /*OpIdx*/1, // MIs[2]
        GIM_CheckOpcode, /*MI*/2, GIMT_Encode2(TargetOpcode::G_FMAXNUM),
        GIM_CheckType, /*MI*/2, /*Op*/1, /*Type*/GILLT_s16,
        GIM_CheckType, /*MI*/2, /*Op*/2, /*Type*/GILLT_s16,
        GIM_RecordInsn, /*DefineMI*/3, /*MI*/0, /*OpIdx*/2, // MIs[3]
        GIM_CheckOpcode, /*MI*/3, GIMT_Encode2(TargetOpcode::G_FMINNUM),
        // MIs[3] VOP3Mods:src0:src0_mods
        GIM_CheckIsSameOperand, /*MI*/3, /*OpIdx*/1, /*OtherMI*/2, /*OtherOpIdx*/1,
        // MIs[3] VOP3Mods:src1:src1_mods
        GIM_CheckIsSameOperand, /*MI*/3, /*OpIdx*/2, /*OtherMI*/2, /*OtherOpIdx*/2,
        GIM_CheckCxxInsnPredicate, /*MI*/0, /*FnId*/GIMT_Encode2(GICXXPred_MI_Predicate_fmaxnum_like_nnan),
        GIM_CheckIsSafeToFold, /*InsnID*/1,
        GIM_CheckIsSafeToFold, /*InsnID*/2,
        GIM_CheckIsSafeToFold, /*InsnID*/3,
        GIM_CheckComplexPattern, /*MI*/1, /*Op*/2, /*Renderer*/GIMT_Encode2(2), GIMT_Encode2(GICP_gi_vop3mods),
        GIM_CheckComplexPattern, /*MI*/2, /*Op*/1, /*Renderer*/GIMT_Encode2(0), GIMT_Encode2(GICP_gi_vop3mods),
        GIM_CheckComplexPattern, /*MI*/2, /*Op*/2, /*Renderer*/GIMT_Encode2(1), GIMT_Encode2(GICP_gi_vop3mods),
        // (fmaxnum_ieee:{ *:[f16] } (fminnum_ieee:{ *:[f16] } (fmaxnum:{ *:[f16] } (VOP3Mods:{ *:[f16] } f16:{ *:[f16] }:$src0, i32:{ *:[i32] }:$src0_mods), (VOP3Mods:{ *:[f16] } f16:{ *:[f16] }:$src1, i32:{ *:[i32] }:$src1_mods)), (VOP3Mods:{ *:[f16] } f16:{ *:[f16] }:$src2, i32:{ *:[i32] }:$src2_mods)), (fminnum:{ *:[f16] } (VOP3Mods:{ *:[f16] } f16:{ *:[f16] }:$src0, i32:{ *:[i32] }:$src0_mods), (VOP3Mods:{ *:[f16] } f16:{ *:[f16] }:$src1, i32:{ *:[i32] }:$src1_mods)))<<P:Predicate_fmaxnum_like_nnan>>  =>  (V_MED3_F16_e64:{ *:[f16] } ?:{ *:[i32] }:$src0_mods, ?:{ *:[f16] }:$src0, ?:{ *:[i32] }:$src1_mods, ?:{ *:[f16] }:$src1, ?:{ *:[i32] }:$src2_mods, ?:{ *:[f16] }:$src2, 0:{ *:[i1] })
        GIR_BuildMI, /*InsnID*/0, /*Opcode*/GIMT_Encode2(AMDGPU::V_MED3_F16_e64),
        GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/0, // DstI[vdst]
        GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/1, // src0_mods
        GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/0, // src0
        GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(1), /*SubOperand*/1, // src1_mods
        GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(1), /*SubOperand*/0, // src1
        GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(2), /*SubOperand*/1, // src2_mods
        GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(2), /*SubOperand*/0, // src2
        GIR_AddImm8, /*InsnID*/0, /*Imm*/0,
        GIR_AddImm8, /*InsnID*/0, /*Imm*/0,
        GIR_AddImm8, /*InsnID*/0, /*Imm*/0,
        GIR_ConstrainSelectedInstOperands, /*InsnID*/0,
        GIR_EraseFromParent, /*InsnID*/0,
        // GIR_Coverage, 10612,
        GIR_Done,
      // Label 5030: @362932
      GIM_Try, /*On fail goto*//*Label 5031*/ GIMT_Encode4(363078), // Rule ID 10613 //
        GIM_CheckFeatures, GIMT_Encode2(GIFBS_isGFX9Plus),
        GIM_CheckRegBankForClass, /*MI*/0, /*Op*/0, /*RC*/GIMT_Encode2(AMDGPU::VGPR_32RegClassID),
        GIM_RecordInsn, /*DefineMI*/1, /*MI*/0, /*OpIdx*/1, // MIs[1]
        GIM_CheckOpcode, /*MI*/1, GIMT_Encode2(TargetOpcode::G_FMINNUM_IEEE),
        GIM_CheckType, /*MI*/1, /*Op*/1, /*Type*/GILLT_s16,
        GIM_CheckType, /*MI*/1, /*Op*/2, /*Type*/GILLT_s16,
        GIM_RecordInsn, /*DefineMI*/2, /*MI*/1, /*OpIdx*/1, // MIs[2]
        GIM_CheckOpcode, /*MI*/2, GIMT_Encode2(TargetOpcode::G_FMAXNUM),
        GIM_CheckType, /*MI*/2, /*Op*/1, /*Type*/GILLT_s16,
        GIM_CheckType, /*MI*/2, /*Op*/2, /*Type*/GILLT_s16,
        GIM_RecordInsn, /*DefineMI*/3, /*MI*/0, /*OpIdx*/2, // MIs[3]
        GIM_CheckOpcode, /*MI*/3, GIMT_Encode2(TargetOpcode::G_FMINNUM),
        // MIs[3] VOP3Mods:src1:src1_mods
        GIM_CheckIsSameOperand, /*MI*/3, /*OpIdx*/1, /*OtherMI*/2, /*OtherOpIdx*/2,
        // MIs[3] VOP3Mods:src0:src0_mods
        GIM_CheckIsSameOperand, /*MI*/3, /*OpIdx*/2, /*OtherMI*/2, /*OtherOpIdx*/1,
        GIM_CheckCxxInsnPredicate, /*MI*/0, /*FnId*/GIMT_Encode2(GICXXPred_MI_Predicate_fmaxnum_like_nnan),
        GIM_CheckIsSafeToFold, /*InsnID*/1,
        GIM_CheckIsSafeToFold, /*InsnID*/2,
        GIM_CheckIsSafeToFold, /*InsnID*/3,
        GIM_CheckComplexPattern, /*MI*/1, /*Op*/2, /*Renderer*/GIMT_Encode2(2), GIMT_Encode2(GICP_gi_vop3mods),
        GIM_CheckComplexPattern, /*MI*/2, /*Op*/1, /*Renderer*/GIMT_Encode2(0), GIMT_Encode2(GICP_gi_vop3mods),
        GIM_CheckComplexPattern, /*MI*/2, /*Op*/2, /*Renderer*/GIMT_Encode2(1), GIMT_Encode2(GICP_gi_vop3mods),
        // (fmaxnum_ieee:{ *:[f16] } (fminnum_ieee:{ *:[f16] } (fmaxnum:{ *:[f16] } (VOP3Mods:{ *:[f16] } f16:{ *:[f16] }:$src0, i32:{ *:[i32] }:$src0_mods), (VOP3Mods:{ *:[f16] } f16:{ *:[f16] }:$src1, i32:{ *:[i32] }:$src1_mods)), (VOP3Mods:{ *:[f16] } f16:{ *:[f16] }:$src2, i32:{ *:[i32] }:$src2_mods)), (fminnum:{ *:[f16] } (VOP3Mods:{ *:[f16] } f16:{ *:[f16] }:$src1, i32:{ *:[i32] }:$src1_mods), (VOP3Mods:{ *:[f16] } f16:{ *:[f16] }:$src0, i32:{ *:[i32] }:$src0_mods)))<<P:Predicate_fmaxnum_like_nnan>>  =>  (V_MED3_F16_e64:{ *:[f16] } ?:{ *:[i32] }:$src0_mods, ?:{ *:[f16] }:$src0, ?:{ *:[i32] }:$src1_mods, ?:{ *:[f16] }:$src1, ?:{ *:[i32] }:$src2_mods, ?:{ *:[f16] }:$src2, 0:{ *:[i1] })
        GIR_BuildMI, /*InsnID*/0, /*Opcode*/GIMT_Encode2(AMDGPU::V_MED3_F16_e64),
        GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/0, // DstI[vdst]
        GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/1, // src0_mods
        GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/0, // src0
        GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(1), /*SubOperand*/1, // src1_mods
        GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(1), /*SubOperand*/0, // src1
        GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(2), /*SubOperand*/1, // src2_mods
        GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(2), /*SubOperand*/0, // src2
        GIR_AddImm8, /*InsnID*/0, /*Imm*/0,
        GIR_AddImm8, /*InsnID*/0, /*Imm*/0,
        GIR_AddImm8, /*InsnID*/0, /*Imm*/0,
        GIR_ConstrainSelectedInstOperands, /*InsnID*/0,
        GIR_EraseFromParent, /*InsnID*/0,
        // GIR_Coverage, 10613,
        GIR_Done,
      // Label 5031: @363078
      GIM_Try, /*On fail goto*//*Label 5032*/ GIMT_Encode4(363224), // Rule ID 10614 //
        GIM_CheckFeatures, GIMT_Encode2(GIFBS_isGFX9Plus),
        GIM_CheckRegBankForClass, /*MI*/0, /*Op*/0, /*RC*/GIMT_Encode2(AMDGPU::VGPR_32RegClassID),
        GIM_RecordInsn, /*DefineMI*/1, /*MI*/0, /*OpIdx*/1, // MIs[1]
        GIM_CheckOpcode, /*MI*/1, GIMT_Encode2(TargetOpcode::G_FMINNUM_IEEE),
        GIM_CheckType, /*MI*/1, /*Op*/1, /*Type*/GILLT_s16,
        GIM_CheckType, /*MI*/1, /*Op*/2, /*Type*/GILLT_s16,
        GIM_RecordInsn, /*DefineMI*/2, /*MI*/1, /*OpIdx*/1, // MIs[2]
        GIM_CheckOpcode, /*MI*/2, GIMT_Encode2(TargetOpcode::G_FMAXNUM),
        GIM_CheckType, /*MI*/2, /*Op*/1, /*Type*/GILLT_s16,
        GIM_CheckType, /*MI*/2, /*Op*/2, /*Type*/GILLT_s16,
        GIM_RecordInsn, /*DefineMI*/3, /*MI*/0, /*OpIdx*/2, // MIs[3]
        GIM_CheckOpcode, /*MI*/3, GIMT_Encode2(TargetOpcode::G_FMINNUM),
        // MIs[3] VOP3Mods:src0:src0_mods
        GIM_CheckIsSameOperand, /*MI*/3, /*OpIdx*/1, /*OtherMI*/2, /*OtherOpIdx*/2,
        // MIs[3] VOP3Mods:src1:src1_mods
        GIM_CheckIsSameOperand, /*MI*/3, /*OpIdx*/2, /*OtherMI*/2, /*OtherOpIdx*/1,
        GIM_CheckCxxInsnPredicate, /*MI*/0, /*FnId*/GIMT_Encode2(GICXXPred_MI_Predicate_fmaxnum_like_nnan),
        GIM_CheckIsSafeToFold, /*InsnID*/1,
        GIM_CheckIsSafeToFold, /*InsnID*/2,
        GIM_CheckIsSafeToFold, /*InsnID*/3,
        GIM_CheckComplexPattern, /*MI*/1, /*Op*/2, /*Renderer*/GIMT_Encode2(2), GIMT_Encode2(GICP_gi_vop3mods),
        GIM_CheckComplexPattern, /*MI*/2, /*Op*/1, /*Renderer*/GIMT_Encode2(0), GIMT_Encode2(GICP_gi_vop3mods),
        GIM_CheckComplexPattern, /*MI*/2, /*Op*/2, /*Renderer*/GIMT_Encode2(1), GIMT_Encode2(GICP_gi_vop3mods),
        // (fmaxnum_ieee:{ *:[f16] } (fminnum_ieee:{ *:[f16] } (fmaxnum:{ *:[f16] } (VOP3Mods:{ *:[f16] } f16:{ *:[f16] }:$src1, i32:{ *:[i32] }:$src1_mods), (VOP3Mods:{ *:[f16] } f16:{ *:[f16] }:$src0, i32:{ *:[i32] }:$src0_mods)), (VOP3Mods:{ *:[f16] } f16:{ *:[f16] }:$src2, i32:{ *:[i32] }:$src2_mods)), (fminnum:{ *:[f16] } (VOP3Mods:{ *:[f16] } f16:{ *:[f16] }:$src0, i32:{ *:[i32] }:$src0_mods), (VOP3Mods:{ *:[f16] } f16:{ *:[f16] }:$src1, i32:{ *:[i32] }:$src1_mods)))<<P:Predicate_fmaxnum_like_nnan>>  =>  (V_MED3_F16_e64:{ *:[f16] } ?:{ *:[i32] }:$src0_mods, ?:{ *:[f16] }:$src0, ?:{ *:[i32] }:$src1_mods, ?:{ *:[f16] }:$src1, ?:{ *:[i32] }:$src2_mods, ?:{ *:[f16] }:$src2, 0:{ *:[i1] })
        GIR_BuildMI, /*InsnID*/0, /*Opcode*/GIMT_Encode2(AMDGPU::V_MED3_F16_e64),
        GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/0, // DstI[vdst]
        GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(1), /*SubOperand*/1, // src0_mods
        GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(1), /*SubOperand*/0, // src0
        GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/1, // src1_mods
        GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/0, // src1
        GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(2), /*SubOperand*/1, // src2_mods
        GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(2), /*SubOperand*/0, // src2
        GIR_AddImm8, /*InsnID*/0, /*Imm*/0,
        GIR_AddImm8, /*InsnID*/0, /*Imm*/0,
        GIR_AddImm8, /*InsnID*/0, /*Imm*/0,
        GIR_ConstrainSelectedInstOperands, /*InsnID*/0,
        GIR_EraseFromParent, /*InsnID*/0,
        // GIR_Coverage, 10614,
        GIR_Done,
      // Label 5032: @363224
      GIM_Try, /*On fail goto*//*Label 5033*/ GIMT_Encode4(363370), // Rule ID 10615 //
        GIM_CheckFeatures, GIMT_Encode2(GIFBS_isGFX9Plus),
        GIM_CheckRegBankForClass, /*MI*/0, /*Op*/0, /*RC*/GIMT_Encode2(AMDGPU::VGPR_32RegClassID),
        GIM_RecordInsn, /*DefineMI*/1, /*MI*/0, /*OpIdx*/1, // MIs[1]
        GIM_CheckOpcode, /*MI*/1, GIMT_Encode2(TargetOpcode::G_FMINNUM_IEEE),
        GIM_CheckType, /*MI*/1, /*Op*/1, /*Type*/GILLT_s16,
        GIM_CheckType, /*MI*/1, /*Op*/2, /*Type*/GILLT_s16,
        GIM_RecordInsn, /*DefineMI*/2, /*MI*/1, /*OpIdx*/1, // MIs[2]
        GIM_CheckOpcode, /*MI*/2, GIMT_Encode2(TargetOpcode::G_FMAXNUM),
        GIM_CheckType, /*MI*/2, /*Op*/1, /*Type*/GILLT_s16,
        GIM_CheckType, /*MI*/2, /*Op*/2, /*Type*/GILLT_s16,
        GIM_RecordInsn, /*DefineMI*/3, /*MI*/0, /*OpIdx*/2, // MIs[3]
        GIM_CheckOpcode, /*MI*/3, GIMT_Encode2(TargetOpcode::G_FMINNUM),
        // MIs[3] VOP3Mods:src1:src1_mods
        GIM_CheckIsSameOperand, /*MI*/3, /*OpIdx*/1, /*OtherMI*/2, /*OtherOpIdx*/1,
        // MIs[3] VOP3Mods:src0:src0_mods
        GIM_CheckIsSameOperand, /*MI*/3, /*OpIdx*/2, /*OtherMI*/2, /*OtherOpIdx*/2,
        GIM_CheckCxxInsnPredicate, /*MI*/0, /*FnId*/GIMT_Encode2(GICXXPred_MI_Predicate_fmaxnum_like_nnan),
        GIM_CheckIsSafeToFold, /*InsnID*/1,
        GIM_CheckIsSafeToFold, /*InsnID*/2,
        GIM_CheckIsSafeToFold, /*InsnID*/3,
        GIM_CheckComplexPattern, /*MI*/1, /*Op*/2, /*Renderer*/GIMT_Encode2(2), GIMT_Encode2(GICP_gi_vop3mods),
        GIM_CheckComplexPattern, /*MI*/2, /*Op*/1, /*Renderer*/GIMT_Encode2(0), GIMT_Encode2(GICP_gi_vop3mods),
        GIM_CheckComplexPattern, /*MI*/2, /*Op*/2, /*Renderer*/GIMT_Encode2(1), GIMT_Encode2(GICP_gi_vop3mods),
        // (fmaxnum_ieee:{ *:[f16] } (fminnum_ieee:{ *:[f16] } (fmaxnum:{ *:[f16] } (VOP3Mods:{ *:[f16] } f16:{ *:[f16] }:$src1, i32:{ *:[i32] }:$src1_mods), (VOP3Mods:{ *:[f16] } f16:{ *:[f16] }:$src0, i32:{ *:[i32] }:$src0_mods)), (VOP3Mods:{ *:[f16] } f16:{ *:[f16] }:$src2, i32:{ *:[i32] }:$src2_mods)), (fminnum:{ *:[f16] } (VOP3Mods:{ *:[f16] } f16:{ *:[f16] }:$src1, i32:{ *:[i32] }:$src1_mods), (VOP3Mods:{ *:[f16] } f16:{ *:[f16] }:$src0, i32:{ *:[i32] }:$src0_mods)))<<P:Predicate_fmaxnum_like_nnan>>  =>  (V_MED3_F16_e64:{ *:[f16] } ?:{ *:[i32] }:$src0_mods, ?:{ *:[f16] }:$src0, ?:{ *:[i32] }:$src1_mods, ?:{ *:[f16] }:$src1, ?:{ *:[i32] }:$src2_mods, ?:{ *:[f16] }:$src2, 0:{ *:[i1] })
        GIR_BuildMI, /*InsnID*/0, /*Opcode*/GIMT_Encode2(AMDGPU::V_MED3_F16_e64),
        GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/0, // DstI[vdst]
        GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(1), /*SubOperand*/1, // src0_mods
        GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(1), /*SubOperand*/0, // src0
        GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/1, // src1_mods
        GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/0, // src1
        GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(2), /*SubOperand*/1, // src2_mods
        GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(2), /*SubOperand*/0, // src2
        GIR_AddImm8, /*InsnID*/0, /*Imm*/0,
        GIR_AddImm8, /*InsnID*/0, /*Imm*/0,
        GIR_AddImm8, /*InsnID*/0, /*Imm*/0,
        GIR_ConstrainSelectedInstOperands, /*InsnID*/0,
        GIR_EraseFromParent, /*InsnID*/0,
        // GIR_Coverage, 10615,
        GIR_Done,
      // Label 5033: @363370
      GIM_Try, /*On fail goto*//*Label 5034*/ GIMT_Encode4(363516), // Rule ID 10552 //
        GIM_CheckFeatures, GIMT_Encode2(GIFBS_isGFX9Plus),
        GIM_CheckRegBankForClass, /*MI*/0, /*Op*/0, /*RC*/GIMT_Encode2(AMDGPU::VGPR_32RegClassID),
        GIM_RecordInsn, /*DefineMI*/1, /*MI*/0, /*OpIdx*/1, // MIs[1]
        GIM_CheckOpcode, /*MI*/1, GIMT_Encode2(TargetOpcode::G_FMINNUM_IEEE),
        GIM_CheckType, /*MI*/1, /*Op*/1, /*Type*/GILLT_s16,
        GIM_CheckType, /*MI*/1, /*Op*/2, /*Type*/GILLT_s16,
        GIM_RecordInsn, /*DefineMI*/2, /*MI*/1, /*OpIdx*/1, // MIs[2]
        GIM_CheckOpcode, /*MI*/2, GIMT_Encode2(TargetOpcode::G_FMAXNUM),
        GIM_CheckType, /*MI*/2, /*Op*/1, /*Type*/GILLT_s16,
        GIM_CheckType, /*MI*/2, /*Op*/2, /*Type*/GILLT_s16,
        GIM_RecordInsn, /*DefineMI*/3, /*MI*/0, /*OpIdx*/2, // MIs[3]
        GIM_CheckOpcode, /*MI*/3, GIMT_Encode2(TargetOpcode::G_FMINNUM_IEEE),
        // MIs[3] VOP3Mods:src0:src0_mods
        GIM_CheckIsSameOperand, /*MI*/3, /*OpIdx*/1, /*OtherMI*/2, /*OtherOpIdx*/1,
        // MIs[3] VOP3Mods:src1:src1_mods
        GIM_CheckIsSameOperand, /*MI*/3, /*OpIdx*/2, /*OtherMI*/2, /*OtherOpIdx*/2,
        GIM_CheckCxxInsnPredicate, /*MI*/0, /*FnId*/GIMT_Encode2(GICXXPred_MI_Predicate_fmaxnum_like_nnan),
        GIM_CheckIsSafeToFold, /*InsnID*/1,
        GIM_CheckIsSafeToFold, /*InsnID*/2,
        GIM_CheckIsSafeToFold, /*InsnID*/3,
        GIM_CheckComplexPattern, /*MI*/1, /*Op*/2, /*Renderer*/GIMT_Encode2(2), GIMT_Encode2(GICP_gi_vop3mods),
        GIM_CheckComplexPattern, /*MI*/2, /*Op*/1, /*Renderer*/GIMT_Encode2(0), GIMT_Encode2(GICP_gi_vop3mods),
        GIM_CheckComplexPattern, /*MI*/2, /*Op*/2, /*Renderer*/GIMT_Encode2(1), GIMT_Encode2(GICP_gi_vop3mods),
        // (fmaxnum_ieee:{ *:[f16] } (fminnum_ieee:{ *:[f16] } (fmaxnum:{ *:[f16] } (VOP3Mods:{ *:[f16] } f16:{ *:[f16] }:$src0, i32:{ *:[i32] }:$src0_mods), (VOP3Mods:{ *:[f16] } f16:{ *:[f16] }:$src1, i32:{ *:[i32] }:$src1_mods)), (VOP3Mods:{ *:[f16] } f16:{ *:[f16] }:$src2, i32:{ *:[i32] }:$src2_mods)), (fminnum_ieee:{ *:[f16] } (VOP3Mods:{ *:[f16] } f16:{ *:[f16] }:$src0, i32:{ *:[i32] }:$src0_mods), (VOP3Mods:{ *:[f16] } f16:{ *:[f16] }:$src1, i32:{ *:[i32] }:$src1_mods)))<<P:Predicate_fmaxnum_like_nnan>>  =>  (V_MED3_F16_e64:{ *:[f16] } ?:{ *:[i32] }:$src0_mods, ?:{ *:[f16] }:$src0, ?:{ *:[i32] }:$src1_mods, ?:{ *:[f16] }:$src1, ?:{ *:[i32] }:$src2_mods, ?:{ *:[f16] }:$src2, 0:{ *:[i1] })
        GIR_BuildMI, /*InsnID*/0, /*Opcode*/GIMT_Encode2(AMDGPU::V_MED3_F16_e64),
        GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/0, // DstI[vdst]
        GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/1, // src0_mods
        GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/0, // src0
        GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(1), /*SubOperand*/1, // src1_mods
        GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(1), /*SubOperand*/0, // src1
        GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(2), /*SubOperand*/1, // src2_mods
        GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(2), /*SubOperand*/0, // src2
        GIR_AddImm8, /*InsnID*/0, /*Imm*/0,
        GIR_AddImm8, /*InsnID*/0, /*Imm*/0,
        GIR_AddImm8, /*InsnID*/0, /*Imm*/0,
        GIR_ConstrainSelectedInstOperands, /*InsnID*/0,
        GIR_EraseFromParent, /*InsnID*/0,
        // GIR_Coverage, 10552,
        GIR_Done,
      // Label 5034: @363516
      GIM_Try, /*On fail goto*//*Label 5035*/ GIMT_Encode4(363662), // Rule ID 10553 //
        GIM_CheckFeatures, GIMT_Encode2(GIFBS_isGFX9Plus),
        GIM_CheckRegBankForClass, /*MI*/0, /*Op*/0, /*RC*/GIMT_Encode2(AMDGPU::VGPR_32RegClassID),
        GIM_RecordInsn, /*DefineMI*/1, /*MI*/0, /*OpIdx*/1, // MIs[1]
        GIM_CheckOpcode, /*MI*/1, GIMT_Encode2(TargetOpcode::G_FMINNUM_IEEE),
        GIM_CheckType, /*MI*/1, /*Op*/1, /*Type*/GILLT_s16,
        GIM_CheckType, /*MI*/1, /*Op*/2, /*Type*/GILLT_s16,
        GIM_RecordInsn, /*DefineMI*/2, /*MI*/1, /*OpIdx*/1, // MIs[2]
        GIM_CheckOpcode, /*MI*/2, GIMT_Encode2(TargetOpcode::G_FMAXNUM),
        GIM_CheckType, /*MI*/2, /*Op*/1, /*Type*/GILLT_s16,
        GIM_CheckType, /*MI*/2, /*Op*/2, /*Type*/GILLT_s16,
        GIM_RecordInsn, /*DefineMI*/3, /*MI*/0, /*OpIdx*/2, // MIs[3]
        GIM_CheckOpcode, /*MI*/3, GIMT_Encode2(TargetOpcode::G_FMINNUM_IEEE),
        // MIs[3] VOP3Mods:src1:src1_mods
        GIM_CheckIsSameOperand, /*MI*/3, /*OpIdx*/1, /*OtherMI*/2, /*OtherOpIdx*/2,
        // MIs[3] VOP3Mods:src0:src0_mods
        GIM_CheckIsSameOperand, /*MI*/3, /*OpIdx*/2, /*OtherMI*/2, /*OtherOpIdx*/1,
        GIM_CheckCxxInsnPredicate, /*MI*/0, /*FnId*/GIMT_Encode2(GICXXPred_MI_Predicate_fmaxnum_like_nnan),
        GIM_CheckIsSafeToFold, /*InsnID*/1,
        GIM_CheckIsSafeToFold, /*InsnID*/2,
        GIM_CheckIsSafeToFold, /*InsnID*/3,
        GIM_CheckComplexPattern, /*MI*/1, /*Op*/2, /*Renderer*/GIMT_Encode2(2), GIMT_Encode2(GICP_gi_vop3mods),
        GIM_CheckComplexPattern, /*MI*/2, /*Op*/1, /*Renderer*/GIMT_Encode2(0), GIMT_Encode2(GICP_gi_vop3mods),
        GIM_CheckComplexPattern, /*MI*/2, /*Op*/2, /*Renderer*/GIMT_Encode2(1), GIMT_Encode2(GICP_gi_vop3mods),
        // (fmaxnum_ieee:{ *:[f16] } (fminnum_ieee:{ *:[f16] } (fmaxnum:{ *:[f16] } (VOP3Mods:{ *:[f16] } f16:{ *:[f16] }:$src0, i32:{ *:[i32] }:$src0_mods), (VOP3Mods:{ *:[f16] } f16:{ *:[f16] }:$src1, i32:{ *:[i32] }:$src1_mods)), (VOP3Mods:{ *:[f16] } f16:{ *:[f16] }:$src2, i32:{ *:[i32] }:$src2_mods)), (fminnum_ieee:{ *:[f16] } (VOP3Mods:{ *:[f16] } f16:{ *:[f16] }:$src1, i32:{ *:[i32] }:$src1_mods), (VOP3Mods:{ *:[f16] } f16:{ *:[f16] }:$src0, i32:{ *:[i32] }:$src0_mods)))<<P:Predicate_fmaxnum_like_nnan>>  =>  (V_MED3_F16_e64:{ *:[f16] } ?:{ *:[i32] }:$src0_mods, ?:{ *:[f16] }:$src0, ?:{ *:[i32] }:$src1_mods, ?:{ *:[f16] }:$src1, ?:{ *:[i32] }:$src2_mods, ?:{ *:[f16] }:$src2, 0:{ *:[i1] })
        GIR_BuildMI, /*InsnID*/0, /*Opcode*/GIMT_Encode2(AMDGPU::V_MED3_F16_e64),
        GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/0, // DstI[vdst]
        GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/1, // src0_mods
        GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/0, // src0
        GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(1), /*SubOperand*/1, // src1_mods
        GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(1), /*SubOperand*/0, // src1
        GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(2), /*SubOperand*/1, // src2_mods
        GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(2), /*SubOperand*/0, // src2
        GIR_AddImm8, /*InsnID*/0, /*Imm*/0,
        GIR_AddImm8, /*InsnID*/0, /*Imm*/0,
        GIR_AddImm8, /*InsnID*/0, /*Imm*/0,
        GIR_ConstrainSelectedInstOperands, /*InsnID*/0,
        GIR_EraseFromParent, /*InsnID*/0,
        // GIR_Coverage, 10553,
        GIR_Done,
      // Label 5035: @363662
      GIM_Try, /*On fail goto*//*Label 5036*/ GIMT_Encode4(363808), // Rule ID 10554 //
        GIM_CheckFeatures, GIMT_Encode2(GIFBS_isGFX9Plus),
        GIM_CheckRegBankForClass, /*MI*/0, /*Op*/0, /*RC*/GIMT_Encode2(AMDGPU::VGPR_32RegClassID),
        GIM_RecordInsn, /*DefineMI*/1, /*MI*/0, /*OpIdx*/1, // MIs[1]
        GIM_CheckOpcode, /*MI*/1, GIMT_Encode2(TargetOpcode::G_FMINNUM_IEEE),
        GIM_CheckType, /*MI*/1, /*Op*/1, /*Type*/GILLT_s16,
        GIM_CheckType, /*MI*/1, /*Op*/2, /*Type*/GILLT_s16,
        GIM_RecordInsn, /*DefineMI*/2, /*MI*/1, /*OpIdx*/1, // MIs[2]
        GIM_CheckOpcode, /*MI*/2, GIMT_Encode2(TargetOpcode::G_FMAXNUM),
        GIM_CheckType, /*MI*/2, /*Op*/1, /*Type*/GILLT_s16,
        GIM_CheckType, /*MI*/2, /*Op*/2, /*Type*/GILLT_s16,
        GIM_RecordInsn, /*DefineMI*/3, /*MI*/0, /*OpIdx*/2, // MIs[3]
        GIM_CheckOpcode, /*MI*/3, GIMT_Encode2(TargetOpcode::G_FMINNUM_IEEE),
        // MIs[3] VOP3Mods:src0:src0_mods
        GIM_CheckIsSameOperand, /*MI*/3, /*OpIdx*/1, /*OtherMI*/2, /*OtherOpIdx*/2,
        // MIs[3] VOP3Mods:src1:src1_mods
        GIM_CheckIsSameOperand, /*MI*/3, /*OpIdx*/2, /*OtherMI*/2, /*OtherOpIdx*/1,
        GIM_CheckCxxInsnPredicate, /*MI*/0, /*FnId*/GIMT_Encode2(GICXXPred_MI_Predicate_fmaxnum_like_nnan),
        GIM_CheckIsSafeToFold, /*InsnID*/1,
        GIM_CheckIsSafeToFold, /*InsnID*/2,
        GIM_CheckIsSafeToFold, /*InsnID*/3,
        GIM_CheckComplexPattern, /*MI*/1, /*Op*/2, /*Renderer*/GIMT_Encode2(2), GIMT_Encode2(GICP_gi_vop3mods),
        GIM_CheckComplexPattern, /*MI*/2, /*Op*/1, /*Renderer*/GIMT_Encode2(0), GIMT_Encode2(GICP_gi_vop3mods),
        GIM_CheckComplexPattern, /*MI*/2, /*Op*/2, /*Renderer*/GIMT_Encode2(1), GIMT_Encode2(GICP_gi_vop3mods),
        // (fmaxnum_ieee:{ *:[f16] } (fminnum_ieee:{ *:[f16] } (fmaxnum:{ *:[f16] } (VOP3Mods:{ *:[f16] } f16:{ *:[f16] }:$src1, i32:{ *:[i32] }:$src1_mods), (VOP3Mods:{ *:[f16] } f16:{ *:[f16] }:$src0, i32:{ *:[i32] }:$src0_mods)), (VOP3Mods:{ *:[f16] } f16:{ *:[f16] }:$src2, i32:{ *:[i32] }:$src2_mods)), (fminnum_ieee:{ *:[f16] } (VOP3Mods:{ *:[f16] } f16:{ *:[f16] }:$src0, i32:{ *:[i32] }:$src0_mods), (VOP3Mods:{ *:[f16] } f16:{ *:[f16] }:$src1, i32:{ *:[i32] }:$src1_mods)))<<P:Predicate_fmaxnum_like_nnan>>  =>  (V_MED3_F16_e64:{ *:[f16] } ?:{ *:[i32] }:$src0_mods, ?:{ *:[f16] }:$src0, ?:{ *:[i32] }:$src1_mods, ?:{ *:[f16] }:$src1, ?:{ *:[i32] }:$src2_mods, ?:{ *:[f16] }:$src2, 0:{ *:[i1] })
        GIR_BuildMI, /*InsnID*/0, /*Opcode*/GIMT_Encode2(AMDGPU::V_MED3_F16_e64),
        GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/0, // DstI[vdst]
        GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(1), /*SubOperand*/1, // src0_mods
        GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(1), /*SubOperand*/0, // src0
        GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/1, // src1_mods
        GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/0, // src1
        GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(2), /*SubOperand*/1, // src2_mods
        GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(2), /*SubOperand*/0, // src2
        GIR_AddImm8, /*InsnID*/0, /*Imm*/0,
        GIR_AddImm8, /*InsnID*/0, /*Imm*/0,
        GIR_AddImm8, /*InsnID*/0, /*Imm*/0,
        GIR_ConstrainSelectedInstOperands, /*InsnID*/0,
        GIR_EraseFromParent, /*InsnID*/0,
        // GIR_Coverage, 10554,
        GIR_Done,
      // Label 5036: @363808
      GIM_Try, /*On fail goto*//*Label 5037*/ GIMT_Encode4(363954), // Rule ID 10555 //
        GIM_CheckFeatures, GIMT_Encode2(GIFBS_isGFX9Plus),
        GIM_CheckRegBankForClass, /*MI*/0, /*Op*/0, /*RC*/GIMT_Encode2(AMDGPU::VGPR_32RegClassID),
        GIM_RecordInsn, /*DefineMI*/1, /*MI*/0, /*OpIdx*/1, // MIs[1]
        GIM_CheckOpcode, /*MI*/1, GIMT_Encode2(TargetOpcode::G_FMINNUM_IEEE),
        GIM_CheckType, /*MI*/1, /*Op*/1, /*Type*/GILLT_s16,
        GIM_CheckType, /*MI*/1, /*Op*/2, /*Type*/GILLT_s16,
        GIM_RecordInsn, /*DefineMI*/2, /*MI*/1, /*OpIdx*/1, // MIs[2]
        GIM_CheckOpcode, /*MI*/2, GIMT_Encode2(TargetOpcode::G_FMAXNUM),
        GIM_CheckType, /*MI*/2, /*Op*/1, /*Type*/GILLT_s16,
        GIM_CheckType, /*MI*/2, /*Op*/2, /*Type*/GILLT_s16,
        GIM_RecordInsn, /*DefineMI*/3, /*MI*/0, /*OpIdx*/2, // MIs[3]
        GIM_CheckOpcode, /*MI*/3, GIMT_Encode2(TargetOpcode::G_FMINNUM_IEEE),
        // MIs[3] VOP3Mods:src1:src1_mods
        GIM_CheckIsSameOperand, /*MI*/3, /*OpIdx*/1, /*OtherMI*/2, /*OtherOpIdx*/1,
        // MIs[3] VOP3Mods:src0:src0_mods
        GIM_CheckIsSameOperand, /*MI*/3, /*OpIdx*/2, /*OtherMI*/2, /*OtherOpIdx*/2,
        GIM_CheckCxxInsnPredicate, /*MI*/0, /*FnId*/GIMT_Encode2(GICXXPred_MI_Predicate_fmaxnum_like_nnan),
        GIM_CheckIsSafeToFold, /*InsnID*/1,
        GIM_CheckIsSafeToFold, /*InsnID*/2,
        GIM_CheckIsSafeToFold, /*InsnID*/3,
        GIM_CheckComplexPattern, /*MI*/1, /*Op*/2, /*Renderer*/GIMT_Encode2(2), GIMT_Encode2(GICP_gi_vop3mods),
        GIM_CheckComplexPattern, /*MI*/2, /*Op*/1, /*Renderer*/GIMT_Encode2(0), GIMT_Encode2(GICP_gi_vop3mods),
        GIM_CheckComplexPattern, /*MI*/2, /*Op*/2, /*Renderer*/GIMT_Encode2(1), GIMT_Encode2(GICP_gi_vop3mods),
        // (fmaxnum_ieee:{ *:[f16] } (fminnum_ieee:{ *:[f16] } (fmaxnum:{ *:[f16] } (VOP3Mods:{ *:[f16] } f16:{ *:[f16] }:$src1, i32:{ *:[i32] }:$src1_mods), (VOP3Mods:{ *:[f16] } f16:{ *:[f16] }:$src0, i32:{ *:[i32] }:$src0_mods)), (VOP3Mods:{ *:[f16] } f16:{ *:[f16] }:$src2, i32:{ *:[i32] }:$src2_mods)), (fminnum_ieee:{ *:[f16] } (VOP3Mods:{ *:[f16] } f16:{ *:[f16] }:$src1, i32:{ *:[i32] }:$src1_mods), (VOP3Mods:{ *:[f16] } f16:{ *:[f16] }:$src0, i32:{ *:[i32] }:$src0_mods)))<<P:Predicate_fmaxnum_like_nnan>>  =>  (V_MED3_F16_e64:{ *:[f16] } ?:{ *:[i32] }:$src0_mods, ?:{ *:[f16] }:$src0, ?:{ *:[i32] }:$src1_mods, ?:{ *:[f16] }:$src1, ?:{ *:[i32] }:$src2_mods, ?:{ *:[f16] }:$src2, 0:{ *:[i1] })
        GIR_BuildMI, /*InsnID*/0, /*Opcode*/GIMT_Encode2(AMDGPU::V_MED3_F16_e64),
        GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/0, // DstI[vdst]
        GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(1), /*SubOperand*/1, // src0_mods
        GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(1), /*SubOperand*/0, // src0
        GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/1, // src1_mods
        GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/0, // src1
        GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(2), /*SubOperand*/1, // src2_mods
        GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(2), /*SubOperand*/0, // src2
        GIR_AddImm8, /*InsnID*/0, /*Imm*/0,
        GIR_AddImm8, /*InsnID*/0, /*Imm*/0,
        GIR_AddImm8, /*InsnID*/0, /*Imm*/0,
        GIR_ConstrainSelectedInstOperands, /*InsnID*/0,
        GIR_EraseFromParent, /*InsnID*/0,
        // GIR_Coverage, 10555,
        GIR_Done,
      // Label 5037: @363954
      GIM_Try, /*On fail goto*//*Label 5038*/ GIMT_Encode4(364100), // Rule ID 10597 //
        GIM_CheckFeatures, GIMT_Encode2(GIFBS_isGFX9Plus),
        GIM_CheckRegBankForClass, /*MI*/0, /*Op*/0, /*RC*/GIMT_Encode2(AMDGPU::VGPR_32RegClassID),
        GIM_RecordInsn, /*DefineMI*/1, /*MI*/0, /*OpIdx*/1, // MIs[1]
        GIM_CheckOpcode, /*MI*/1, GIMT_Encode2(TargetOpcode::G_FMINNUM_IEEE),
        GIM_CheckType, /*MI*/1, /*Op*/1, /*Type*/GILLT_s16,
        GIM_CheckType, /*MI*/1, /*Op*/2, /*Type*/GILLT_s16,
        GIM_RecordInsn, /*DefineMI*/2, /*MI*/1, /*OpIdx*/1, // MIs[2]
        GIM_CheckOpcode, /*MI*/2, GIMT_Encode2(TargetOpcode::G_FMAXNUM_IEEE),
        GIM_CheckType, /*MI*/2, /*Op*/1, /*Type*/GILLT_s16,
        GIM_CheckType, /*MI*/2, /*Op*/2, /*Type*/GILLT_s16,
        GIM_RecordInsn, /*DefineMI*/3, /*MI*/0, /*OpIdx*/2, // MIs[3]
        GIM_CheckOpcode, /*MI*/3, GIMT_Encode2(TargetOpcode::G_FMINNUM),
        // MIs[3] VOP3Mods:src0:src0_mods
        GIM_CheckIsSameOperand, /*MI*/3, /*OpIdx*/1, /*OtherMI*/2, /*OtherOpIdx*/1,
        // MIs[3] VOP3Mods:src1:src1_mods
        GIM_CheckIsSameOperand, /*MI*/3, /*OpIdx*/2, /*OtherMI*/2, /*OtherOpIdx*/2,
        GIM_CheckCxxInsnPredicate, /*MI*/0, /*FnId*/GIMT_Encode2(GICXXPred_MI_Predicate_fmaxnum_like_nnan),
        GIM_CheckIsSafeToFold, /*InsnID*/1,
        GIM_CheckIsSafeToFold, /*InsnID*/2,
        GIM_CheckIsSafeToFold, /*InsnID*/3,
        GIM_CheckComplexPattern, /*MI*/1, /*Op*/2, /*Renderer*/GIMT_Encode2(2), GIMT_Encode2(GICP_gi_vop3mods),
        GIM_CheckComplexPattern, /*MI*/2, /*Op*/1, /*Renderer*/GIMT_Encode2(0), GIMT_Encode2(GICP_gi_vop3mods),
        GIM_CheckComplexPattern, /*MI*/2, /*Op*/2, /*Renderer*/GIMT_Encode2(1), GIMT_Encode2(GICP_gi_vop3mods),
        // (fmaxnum_ieee:{ *:[f16] } (fminnum_ieee:{ *:[f16] } (fmaxnum_ieee:{ *:[f16] } (VOP3Mods:{ *:[f16] } f16:{ *:[f16] }:$src0, i32:{ *:[i32] }:$src0_mods), (VOP3Mods:{ *:[f16] } f16:{ *:[f16] }:$src1, i32:{ *:[i32] }:$src1_mods)), (VOP3Mods:{ *:[f16] } f16:{ *:[f16] }:$src2, i32:{ *:[i32] }:$src2_mods)), (fminnum:{ *:[f16] } (VOP3Mods:{ *:[f16] } f16:{ *:[f16] }:$src0, i32:{ *:[i32] }:$src0_mods), (VOP3Mods:{ *:[f16] } f16:{ *:[f16] }:$src1, i32:{ *:[i32] }:$src1_mods)))<<P:Predicate_fmaxnum_like_nnan>>  =>  (V_MED3_F16_e64:{ *:[f16] } ?:{ *:[i32] }:$src0_mods, ?:{ *:[f16] }:$src0, ?:{ *:[i32] }:$src1_mods, ?:{ *:[f16] }:$src1, ?:{ *:[i32] }:$src2_mods, ?:{ *:[f16] }:$src2, 0:{ *:[i1] })
        GIR_BuildMI, /*InsnID*/0, /*Opcode*/GIMT_Encode2(AMDGPU::V_MED3_F16_e64),
        GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/0, // DstI[vdst]
        GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/1, // src0_mods
        GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/0, // src0
        GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(1), /*SubOperand*/1, // src1_mods
        GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(1), /*SubOperand*/0, // src1
        GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(2), /*SubOperand*/1, // src2_mods
        GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(2), /*SubOperand*/0, // src2
        GIR_AddImm8, /*InsnID*/0, /*Imm*/0,
        GIR_AddImm8, /*InsnID*/0, /*Imm*/0,
        GIR_AddImm8, /*InsnID*/0, /*Imm*/0,
        GIR_ConstrainSelectedInstOperands, /*InsnID*/0,
        GIR_EraseFromParent, /*InsnID*/0,
        // GIR_Coverage, 10597,
        GIR_Done,
      // Label 5038: @364100
      GIM_Try, /*On fail goto*//*Label 5039*/ GIMT_Encode4(364246), // Rule ID 10598 //
        GIM_CheckFeatures, GIMT_Encode2(GIFBS_isGFX9Plus),
        GIM_CheckRegBankForClass, /*MI*/0, /*Op*/0, /*RC*/GIMT_Encode2(AMDGPU::VGPR_32RegClassID),
        GIM_RecordInsn, /*DefineMI*/1, /*MI*/0, /*OpIdx*/1, // MIs[1]
        GIM_CheckOpcode, /*MI*/1, GIMT_Encode2(TargetOpcode::G_FMINNUM_IEEE),
        GIM_CheckType, /*MI*/1, /*Op*/1, /*Type*/GILLT_s16,
        GIM_CheckType, /*MI*/1, /*Op*/2, /*Type*/GILLT_s16,
        GIM_RecordInsn, /*DefineMI*/2, /*MI*/1, /*OpIdx*/1, // MIs[2]
        GIM_CheckOpcode, /*MI*/2, GIMT_Encode2(TargetOpcode::G_FMAXNUM_IEEE),
        GIM_CheckType, /*MI*/2, /*Op*/1, /*Type*/GILLT_s16,
        GIM_CheckType, /*MI*/2, /*Op*/2, /*Type*/GILLT_s16,
        GIM_RecordInsn, /*DefineMI*/3, /*MI*/0, /*OpIdx*/2, // MIs[3]
        GIM_CheckOpcode, /*MI*/3, GIMT_Encode2(TargetOpcode::G_FMINNUM),
        // MIs[3] VOP3Mods:src1:src1_mods
        GIM_CheckIsSameOperand, /*MI*/3, /*OpIdx*/1, /*OtherMI*/2, /*OtherOpIdx*/2,
        // MIs[3] VOP3Mods:src0:src0_mods
        GIM_CheckIsSameOperand, /*MI*/3, /*OpIdx*/2, /*OtherMI*/2, /*OtherOpIdx*/1,
        GIM_CheckCxxInsnPredicate, /*MI*/0, /*FnId*/GIMT_Encode2(GICXXPred_MI_Predicate_fmaxnum_like_nnan),
        GIM_CheckIsSafeToFold, /*InsnID*/1,
        GIM_CheckIsSafeToFold, /*InsnID*/2,
        GIM_CheckIsSafeToFold, /*InsnID*/3,
        GIM_CheckComplexPattern, /*MI*/1, /*Op*/2, /*Renderer*/GIMT_Encode2(2), GIMT_Encode2(GICP_gi_vop3mods),
        GIM_CheckComplexPattern, /*MI*/2, /*Op*/1, /*Renderer*/GIMT_Encode2(0), GIMT_Encode2(GICP_gi_vop3mods),
        GIM_CheckComplexPattern, /*MI*/2, /*Op*/2, /*Renderer*/GIMT_Encode2(1), GIMT_Encode2(GICP_gi_vop3mods),
        // (fmaxnum_ieee:{ *:[f16] } (fminnum_ieee:{ *:[f16] } (fmaxnum_ieee:{ *:[f16] } (VOP3Mods:{ *:[f16] } f16:{ *:[f16] }:$src0, i32:{ *:[i32] }:$src0_mods), (VOP3Mods:{ *:[f16] } f16:{ *:[f16] }:$src1, i32:{ *:[i32] }:$src1_mods)), (VOP3Mods:{ *:[f16] } f16:{ *:[f16] }:$src2, i32:{ *:[i32] }:$src2_mods)), (fminnum:{ *:[f16] } (VOP3Mods:{ *:[f16] } f16:{ *:[f16] }:$src1, i32:{ *:[i32] }:$src1_mods), (VOP3Mods:{ *:[f16] } f16:{ *:[f16] }:$src0, i32:{ *:[i32] }:$src0_mods)))<<P:Predicate_fmaxnum_like_nnan>>  =>  (V_MED3_F16_e64:{ *:[f16] } ?:{ *:[i32] }:$src0_mods, ?:{ *:[f16] }:$src0, ?:{ *:[i32] }:$src1_mods, ?:{ *:[f16] }:$src1, ?:{ *:[i32] }:$src2_mods, ?:{ *:[f16] }:$src2, 0:{ *:[i1] })
        GIR_BuildMI, /*InsnID*/0, /*Opcode*/GIMT_Encode2(AMDGPU::V_MED3_F16_e64),
        GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/0, // DstI[vdst]
        GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/1, // src0_mods
        GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/0, // src0
        GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(1), /*SubOperand*/1, // src1_mods
        GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(1), /*SubOperand*/0, // src1
        GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(2), /*SubOperand*/1, // src2_mods
        GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(2), /*SubOperand*/0, // src2
        GIR_AddImm8, /*InsnID*/0, /*Imm*/0,
        GIR_AddImm8, /*InsnID*/0, /*Imm*/0,
        GIR_AddImm8, /*InsnID*/0, /*Imm*/0,
        GIR_ConstrainSelectedInstOperands, /*InsnID*/0,
        GIR_EraseFromParent, /*InsnID*/0,
        // GIR_Coverage, 10598,
        GIR_Done,
      // Label 5039: @364246
      GIM_Try, /*On fail goto*//*Label 5040*/ GIMT_Encode4(364392), // Rule ID 10599 //
        GIM_CheckFeatures, GIMT_Encode2(GIFBS_isGFX9Plus),
        GIM_CheckRegBankForClass, /*MI*/0, /*Op*/0, /*RC*/GIMT_Encode2(AMDGPU::VGPR_32RegClassID),
        GIM_RecordInsn, /*DefineMI*/1, /*MI*/0, /*OpIdx*/1, // MIs[1]
        GIM_CheckOpcode, /*MI*/1, GIMT_Encode2(TargetOpcode::G_FMINNUM_IEEE),
        GIM_CheckType, /*MI*/1, /*Op*/1, /*Type*/GILLT_s16,
        GIM_CheckType, /*MI*/1, /*Op*/2, /*Type*/GILLT_s16,
        GIM_RecordInsn, /*DefineMI*/2, /*MI*/1, /*OpIdx*/1, // MIs[2]
        GIM_CheckOpcode, /*MI*/2, GIMT_Encode2(TargetOpcode::G_FMAXNUM_IEEE),
        GIM_CheckType, /*MI*/2, /*Op*/1, /*Type*/GILLT_s16,
        GIM_CheckType, /*MI*/2, /*Op*/2, /*Type*/GILLT_s16,
        GIM_RecordInsn, /*DefineMI*/3, /*MI*/0, /*OpIdx*/2, // MIs[3]
        GIM_CheckOpcode, /*MI*/3, GIMT_Encode2(TargetOpcode::G_FMINNUM),
        // MIs[3] VOP3Mods:src0:src0_mods
        GIM_CheckIsSameOperand, /*MI*/3, /*OpIdx*/1, /*OtherMI*/2, /*OtherOpIdx*/2,
        // MIs[3] VOP3Mods:src1:src1_mods
        GIM_CheckIsSameOperand, /*MI*/3, /*OpIdx*/2, /*OtherMI*/2, /*OtherOpIdx*/1,
        GIM_CheckCxxInsnPredicate, /*MI*/0, /*FnId*/GIMT_Encode2(GICXXPred_MI_Predicate_fmaxnum_like_nnan),
        GIM_CheckIsSafeToFold, /*InsnID*/1,
        GIM_CheckIsSafeToFold, /*InsnID*/2,
        GIM_CheckIsSafeToFold, /*InsnID*/3,
        GIM_CheckComplexPattern, /*MI*/1, /*Op*/2, /*Renderer*/GIMT_Encode2(2), GIMT_Encode2(GICP_gi_vop3mods),
        GIM_CheckComplexPattern, /*MI*/2, /*Op*/1, /*Renderer*/GIMT_Encode2(0), GIMT_Encode2(GICP_gi_vop3mods),
        GIM_CheckComplexPattern, /*MI*/2, /*Op*/2, /*Renderer*/GIMT_Encode2(1), GIMT_Encode2(GICP_gi_vop3mods),
        // (fmaxnum_ieee:{ *:[f16] } (fminnum_ieee:{ *:[f16] } (fmaxnum_ieee:{ *:[f16] } (VOP3Mods:{ *:[f16] } f16:{ *:[f16] }:$src1, i32:{ *:[i32] }:$src1_mods), (VOP3Mods:{ *:[f16] } f16:{ *:[f16] }:$src0, i32:{ *:[i32] }:$src0_mods)), (VOP3Mods:{ *:[f16] } f16:{ *:[f16] }:$src2, i32:{ *:[i32] }:$src2_mods)), (fminnum:{ *:[f16] } (VOP3Mods:{ *:[f16] } f16:{ *:[f16] }:$src0, i32:{ *:[i32] }:$src0_mods), (VOP3Mods:{ *:[f16] } f16:{ *:[f16] }:$src1, i32:{ *:[i32] }:$src1_mods)))<<P:Predicate_fmaxnum_like_nnan>>  =>  (V_MED3_F16_e64:{ *:[f16] } ?:{ *:[i32] }:$src0_mods, ?:{ *:[f16] }:$src0, ?:{ *:[i32] }:$src1_mods, ?:{ *:[f16] }:$src1, ?:{ *:[i32] }:$src2_mods, ?:{ *:[f16] }:$src2, 0:{ *:[i1] })
        GIR_BuildMI, /*InsnID*/0, /*Opcode*/GIMT_Encode2(AMDGPU::V_MED3_F16_e64),
        GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/0, // DstI[vdst]
        GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(1), /*SubOperand*/1, // src0_mods
        GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(1), /*SubOperand*/0, // src0
        GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/1, // src1_mods
        GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/0, // src1
        GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(2), /*SubOperand*/1, // src2_mods
        GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(2), /*SubOperand*/0, // src2
        GIR_AddImm8, /*InsnID*/0, /*Imm*/0,
        GIR_AddImm8, /*InsnID*/0, /*Imm*/0,
        GIR_AddImm8, /*InsnID*/0, /*Imm*/0,
        GIR_ConstrainSelectedInstOperands, /*InsnID*/0,
        GIR_EraseFromParent, /*InsnID*/0,
        // GIR_Coverage, 10599,
        GIR_Done,
      // Label 5040: @364392
      GIM_Try, /*On fail goto*//*Label 5041*/ GIMT_Encode4(364538), // Rule ID 10600 //
        GIM_CheckFeatures, GIMT_Encode2(GIFBS_isGFX9Plus),
        GIM_CheckRegBankForClass, /*MI*/0, /*Op*/0, /*RC*/GIMT_Encode2(AMDGPU::VGPR_32RegClassID),
        GIM_RecordInsn, /*DefineMI*/1, /*MI*/0, /*OpIdx*/1, // MIs[1]
        GIM_CheckOpcode, /*MI*/1, GIMT_Encode2(TargetOpcode::G_FMINNUM_IEEE),
        GIM_CheckType, /*MI*/1, /*Op*/1, /*Type*/GILLT_s16,
        GIM_CheckType, /*MI*/1, /*Op*/2, /*Type*/GILLT_s16,
        GIM_RecordInsn, /*DefineMI*/2, /*MI*/1, /*OpIdx*/1, // MIs[2]
        GIM_CheckOpcode, /*MI*/2, GIMT_Encode2(TargetOpcode::G_FMAXNUM_IEEE),
        GIM_CheckType, /*MI*/2, /*Op*/1, /*Type*/GILLT_s16,
        GIM_CheckType, /*MI*/2, /*Op*/2, /*Type*/GILLT_s16,
        GIM_RecordInsn, /*DefineMI*/3, /*MI*/0, /*OpIdx*/2, // MIs[3]
        GIM_CheckOpcode, /*MI*/3, GIMT_Encode2(TargetOpcode::G_FMINNUM),
        // MIs[3] VOP3Mods:src1:src1_mods
        GIM_CheckIsSameOperand, /*MI*/3, /*OpIdx*/1, /*OtherMI*/2, /*OtherOpIdx*/1,
        // MIs[3] VOP3Mods:src0:src0_mods
        GIM_CheckIsSameOperand, /*MI*/3, /*OpIdx*/2, /*OtherMI*/2, /*OtherOpIdx*/2,
        GIM_CheckCxxInsnPredicate, /*MI*/0, /*FnId*/GIMT_Encode2(GICXXPred_MI_Predicate_fmaxnum_like_nnan),
        GIM_CheckIsSafeToFold, /*InsnID*/1,
        GIM_CheckIsSafeToFold, /*InsnID*/2,
        GIM_CheckIsSafeToFold, /*InsnID*/3,
        GIM_CheckComplexPattern, /*MI*/1, /*Op*/2, /*Renderer*/GIMT_Encode2(2), GIMT_Encode2(GICP_gi_vop3mods),
        GIM_CheckComplexPattern, /*MI*/2, /*Op*/1, /*Renderer*/GIMT_Encode2(0), GIMT_Encode2(GICP_gi_vop3mods),
        GIM_CheckComplexPattern, /*MI*/2, /*Op*/2, /*Renderer*/GIMT_Encode2(1), GIMT_Encode2(GICP_gi_vop3mods),
        // (fmaxnum_ieee:{ *:[f16] } (fminnum_ieee:{ *:[f16] } (fmaxnum_ieee:{ *:[f16] } (VOP3Mods:{ *:[f16] } f16:{ *:[f16] }:$src1, i32:{ *:[i32] }:$src1_mods), (VOP3Mods:{ *:[f16] } f16:{ *:[f16] }:$src0, i32:{ *:[i32] }:$src0_mods)), (VOP3Mods:{ *:[f16] } f16:{ *:[f16] }:$src2, i32:{ *:[i32] }:$src2_mods)), (fminnum:{ *:[f16] } (VOP3Mods:{ *:[f16] } f16:{ *:[f16] }:$src1, i32:{ *:[i32] }:$src1_mods), (VOP3Mods:{ *:[f16] } f16:{ *:[f16] }:$src0, i32:{ *:[i32] }:$src0_mods)))<<P:Predicate_fmaxnum_like_nnan>>  =>  (V_MED3_F16_e64:{ *:[f16] } ?:{ *:[i32] }:$src0_mods, ?:{ *:[f16] }:$src0, ?:{ *:[i32] }:$src1_mods, ?:{ *:[f16] }:$src1, ?:{ *:[i32] }:$src2_mods, ?:{ *:[f16] }:$src2, 0:{ *:[i1] })
        GIR_BuildMI, /*InsnID*/0, /*Opcode*/GIMT_Encode2(AMDGPU::V_MED3_F16_e64),
        GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/0, // DstI[vdst]
        GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(1), /*SubOperand*/1, // src0_mods
        GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(1), /*SubOperand*/0, // src0
        GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/1, // src1_mods
        GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/0, // src1
        GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(2), /*SubOperand*/1, // src2_mods
        GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(2), /*SubOperand*/0, // src2
        GIR_AddImm8, /*InsnID*/0, /*Imm*/0,
        GIR_AddImm8, /*InsnID*/0, /*Imm*/0,
        GIR_AddImm8, /*InsnID*/0, /*Imm*/0,
        GIR_ConstrainSelectedInstOperands, /*InsnID*/0,
        GIR_EraseFromParent, /*InsnID*/0,
        // GIR_Coverage, 10600,
        GIR_Done,
      // Label 5041: @364538
      GIM_Try, /*On fail goto*//*Label 5042*/ GIMT_Encode4(364684), // Rule ID 10537 //
        GIM_CheckFeatures, GIMT_Encode2(GIFBS_isGFX9Plus),
        GIM_CheckRegBankForClass, /*MI*/0, /*Op*/0, /*RC*/GIMT_Encode2(AMDGPU::VGPR_32RegClassID),
        GIM_RecordInsn, /*DefineMI*/1, /*MI*/0, /*OpIdx*/1, // MIs[1]
        GIM_CheckOpcode, /*MI*/1, GIMT_Encode2(TargetOpcode::G_FMINNUM_IEEE),
        GIM_CheckType, /*MI*/1, /*Op*/1, /*Type*/GILLT_s16,
        GIM_CheckType, /*MI*/1, /*Op*/2, /*Type*/GILLT_s16,
        GIM_RecordInsn, /*DefineMI*/2, /*MI*/1, /*OpIdx*/1, // MIs[2]
        GIM_CheckOpcode, /*MI*/2, GIMT_Encode2(TargetOpcode::G_FMAXNUM_IEEE),
        GIM_CheckType, /*MI*/2, /*Op*/1, /*Type*/GILLT_s16,
        GIM_CheckType, /*MI*/2, /*Op*/2, /*Type*/GILLT_s16,
        GIM_RecordInsn, /*DefineMI*/3, /*MI*/0, /*OpIdx*/2, // MIs[3]
        GIM_CheckOpcode, /*MI*/3, GIMT_Encode2(TargetOpcode::G_FMINNUM_IEEE),
        // MIs[3] VOP3Mods:src0:src0_mods
        GIM_CheckIsSameOperand, /*MI*/3, /*OpIdx*/1, /*OtherMI*/2, /*OtherOpIdx*/1,
        // MIs[3] VOP3Mods:src1:src1_mods
        GIM_CheckIsSameOperand, /*MI*/3, /*OpIdx*/2, /*OtherMI*/2, /*OtherOpIdx*/2,
        GIM_CheckCxxInsnPredicate, /*MI*/0, /*FnId*/GIMT_Encode2(GICXXPred_MI_Predicate_fmaxnum_like_nnan),
        GIM_CheckIsSafeToFold, /*InsnID*/1,
        GIM_CheckIsSafeToFold, /*InsnID*/2,
        GIM_CheckIsSafeToFold, /*InsnID*/3,
        GIM_CheckComplexPattern, /*MI*/1, /*Op*/2, /*Renderer*/GIMT_Encode2(2), GIMT_Encode2(GICP_gi_vop3mods),
        GIM_CheckComplexPattern, /*MI*/2, /*Op*/1, /*Renderer*/GIMT_Encode2(0), GIMT_Encode2(GICP_gi_vop3mods),
        GIM_CheckComplexPattern, /*MI*/2, /*Op*/2, /*Renderer*/GIMT_Encode2(1), GIMT_Encode2(GICP_gi_vop3mods),
        // (fmaxnum_ieee:{ *:[f16] } (fminnum_ieee:{ *:[f16] } (fmaxnum_ieee:{ *:[f16] } (VOP3Mods:{ *:[f16] } f16:{ *:[f16] }:$src0, i32:{ *:[i32] }:$src0_mods), (VOP3Mods:{ *:[f16] } f16:{ *:[f16] }:$src1, i32:{ *:[i32] }:$src1_mods)), (VOP3Mods:{ *:[f16] } f16:{ *:[f16] }:$src2, i32:{ *:[i32] }:$src2_mods)), (fminnum_ieee:{ *:[f16] } (VOP3Mods:{ *:[f16] } f16:{ *:[f16] }:$src0, i32:{ *:[i32] }:$src0_mods), (VOP3Mods:{ *:[f16] } f16:{ *:[f16] }:$src1, i32:{ *:[i32] }:$src1_mods)))<<P:Predicate_fmaxnum_like_nnan>>  =>  (V_MED3_F16_e64:{ *:[f16] } ?:{ *:[i32] }:$src0_mods, ?:{ *:[f16] }:$src0, ?:{ *:[i32] }:$src1_mods, ?:{ *:[f16] }:$src1, ?:{ *:[i32] }:$src2_mods, ?:{ *:[f16] }:$src2, 0:{ *:[i1] })
        GIR_BuildMI, /*InsnID*/0, /*Opcode*/GIMT_Encode2(AMDGPU::V_MED3_F16_e64),
        GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/0, // DstI[vdst]
        GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/1, // src0_mods
        GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/0, // src0
        GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(1), /*SubOperand*/1, // src1_mods
        GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(1), /*SubOperand*/0, // src1
        GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(2), /*SubOperand*/1, // src2_mods
        GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(2), /*SubOperand*/0, // src2
        GIR_AddImm8, /*InsnID*/0, /*Imm*/0,
        GIR_AddImm8, /*InsnID*/0, /*Imm*/0,
        GIR_AddImm8, /*InsnID*/0, /*Imm*/0,
        GIR_ConstrainSelectedInstOperands, /*InsnID*/0,
        GIR_EraseFromParent, /*InsnID*/0,
        // GIR_Coverage, 10537,
        GIR_Done,
      // Label 5042: @364684
      GIM_Try, /*On fail goto*//*Label 5043*/ GIMT_Encode4(364830), // Rule ID 10538 //
        GIM_CheckFeatures, GIMT_Encode2(GIFBS_isGFX9Plus),
        GIM_CheckRegBankForClass, /*MI*/0, /*Op*/0, /*RC*/GIMT_Encode2(AMDGPU::VGPR_32RegClassID),
        GIM_RecordInsn, /*DefineMI*/1, /*MI*/0, /*OpIdx*/1, // MIs[1]
        GIM_CheckOpcode, /*MI*/1, GIMT_Encode2(TargetOpcode::G_FMINNUM_IEEE),
        GIM_CheckType, /*MI*/1, /*Op*/1, /*Type*/GILLT_s16,
        GIM_CheckType, /*MI*/1, /*Op*/2, /*Type*/GILLT_s16,
        GIM_RecordInsn, /*DefineMI*/2, /*MI*/1, /*OpIdx*/1, // MIs[2]
        GIM_CheckOpcode, /*MI*/2, GIMT_Encode2(TargetOpcode::G_FMAXNUM_IEEE),
        GIM_CheckType, /*MI*/2, /*Op*/1, /*Type*/GILLT_s16,
        GIM_CheckType, /*MI*/2, /*Op*/2, /*Type*/GILLT_s16,
        GIM_RecordInsn, /*DefineMI*/3, /*MI*/0, /*OpIdx*/2, // MIs[3]
        GIM_CheckOpcode, /*MI*/3, GIMT_Encode2(TargetOpcode::G_FMINNUM_IEEE),
        // MIs[3] VOP3Mods:src1:src1_mods
        GIM_CheckIsSameOperand, /*MI*/3, /*OpIdx*/1, /*OtherMI*/2, /*OtherOpIdx*/2,
        // MIs[3] VOP3Mods:src0:src0_mods
        GIM_CheckIsSameOperand, /*MI*/3, /*OpIdx*/2, /*OtherMI*/2, /*OtherOpIdx*/1,
        GIM_CheckCxxInsnPredicate, /*MI*/0, /*FnId*/GIMT_Encode2(GICXXPred_MI_Predicate_fmaxnum_like_nnan),
        GIM_CheckIsSafeToFold, /*InsnID*/1,
        GIM_CheckIsSafeToFold, /*InsnID*/2,
        GIM_CheckIsSafeToFold, /*InsnID*/3,
        GIM_CheckComplexPattern, /*MI*/1, /*Op*/2, /*Renderer*/GIMT_Encode2(2), GIMT_Encode2(GICP_gi_vop3mods),
        GIM_CheckComplexPattern, /*MI*/2, /*Op*/1, /*Renderer*/GIMT_Encode2(0), GIMT_Encode2(GICP_gi_vop3mods),
        GIM_CheckComplexPattern, /*MI*/2, /*Op*/2, /*Renderer*/GIMT_Encode2(1), GIMT_Encode2(GICP_gi_vop3mods),
        // (fmaxnum_ieee:{ *:[f16] } (fminnum_ieee:{ *:[f16] } (fmaxnum_ieee:{ *:[f16] } (VOP3Mods:{ *:[f16] } f16:{ *:[f16] }:$src0, i32:{ *:[i32] }:$src0_mods), (VOP3Mods:{ *:[f16] } f16:{ *:[f16] }:$src1, i32:{ *:[i32] }:$src1_mods)), (VOP3Mods:{ *:[f16] } f16:{ *:[f16] }:$src2, i32:{ *:[i32] }:$src2_mods)), (fminnum_ieee:{ *:[f16] } (VOP3Mods:{ *:[f16] } f16:{ *:[f16] }:$src1, i32:{ *:[i32] }:$src1_mods), (VOP3Mods:{ *:[f16] } f16:{ *:[f16] }:$src0, i32:{ *:[i32] }:$src0_mods)))<<P:Predicate_fmaxnum_like_nnan>>  =>  (V_MED3_F16_e64:{ *:[f16] } ?:{ *:[i32] }:$src0_mods, ?:{ *:[f16] }:$src0, ?:{ *:[i32] }:$src1_mods, ?:{ *:[f16] }:$src1, ?:{ *:[i32] }:$src2_mods, ?:{ *:[f16] }:$src2, 0:{ *:[i1] })
        GIR_BuildMI, /*InsnID*/0, /*Opcode*/GIMT_Encode2(AMDGPU::V_MED3_F16_e64),
        GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/0, // DstI[vdst]
        GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/1, // src0_mods
        GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/0, // src0
        GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(1), /*SubOperand*/1, // src1_mods
        GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(1), /*SubOperand*/0, // src1
        GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(2), /*SubOperand*/1, // src2_mods
        GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(2), /*SubOperand*/0, // src2
        GIR_AddImm8, /*InsnID*/0, /*Imm*/0,
        GIR_AddImm8, /*InsnID*/0, /*Imm*/0,
        GIR_AddImm8, /*InsnID*/0, /*Imm*/0,
        GIR_ConstrainSelectedInstOperands, /*InsnID*/0,
        GIR_EraseFromParent, /*InsnID*/0,
        // GIR_Coverage, 10538,
        GIR_Done,
      // Label 5043: @364830
      GIM_Try, /*On fail goto*//*Label 5044*/ GIMT_Encode4(364976), // Rule ID 10539 //
        GIM_CheckFeatures, GIMT_Encode2(GIFBS_isGFX9Plus),
        GIM_CheckRegBankForClass, /*MI*/0, /*Op*/0, /*RC*/GIMT_Encode2(AMDGPU::VGPR_32RegClassID),
        GIM_RecordInsn, /*DefineMI*/1, /*MI*/0, /*OpIdx*/1, // MIs[1]
        GIM_CheckOpcode, /*MI*/1, GIMT_Encode2(TargetOpcode::G_FMINNUM_IEEE),
        GIM_CheckType, /*MI*/1, /*Op*/1, /*Type*/GILLT_s16,
        GIM_CheckType, /*MI*/1, /*Op*/2, /*Type*/GILLT_s16,
        GIM_RecordInsn, /*DefineMI*/2, /*MI*/1, /*OpIdx*/1, // MIs[2]
        GIM_CheckOpcode, /*MI*/2, GIMT_Encode2(TargetOpcode::G_FMAXNUM_IEEE),
        GIM_CheckType, /*MI*/2, /*Op*/1, /*Type*/GILLT_s16,
        GIM_CheckType, /*MI*/2, /*Op*/2, /*Type*/GILLT_s16,
        GIM_RecordInsn, /*DefineMI*/3, /*MI*/0, /*OpIdx*/2, // MIs[3]
        GIM_CheckOpcode, /*MI*/3, GIMT_Encode2(TargetOpcode::G_FMINNUM_IEEE),
        // MIs[3] VOP3Mods:src0:src0_mods
        GIM_CheckIsSameOperand, /*MI*/3, /*OpIdx*/1, /*OtherMI*/2, /*OtherOpIdx*/2,
        // MIs[3] VOP3Mods:src1:src1_mods
        GIM_CheckIsSameOperand, /*MI*/3, /*OpIdx*/2, /*OtherMI*/2, /*OtherOpIdx*/1,
        GIM_CheckCxxInsnPredicate, /*MI*/0, /*FnId*/GIMT_Encode2(GICXXPred_MI_Predicate_fmaxnum_like_nnan),
        GIM_CheckIsSafeToFold, /*InsnID*/1,
        GIM_CheckIsSafeToFold, /*InsnID*/2,
        GIM_CheckIsSafeToFold, /*InsnID*/3,
        GIM_CheckComplexPattern, /*MI*/1, /*Op*/2, /*Renderer*/GIMT_Encode2(2), GIMT_Encode2(GICP_gi_vop3mods),
        GIM_CheckComplexPattern, /*MI*/2, /*Op*/1, /*Renderer*/GIMT_Encode2(0), GIMT_Encode2(GICP_gi_vop3mods),
        GIM_CheckComplexPattern, /*MI*/2, /*Op*/2, /*Renderer*/GIMT_Encode2(1), GIMT_Encode2(GICP_gi_vop3mods),
        // (fmaxnum_ieee:{ *:[f16] } (fminnum_ieee:{ *:[f16] } (fmaxnum_ieee:{ *:[f16] } (VOP3Mods:{ *:[f16] } f16:{ *:[f16] }:$src1, i32:{ *:[i32] }:$src1_mods), (VOP3Mods:{ *:[f16] } f16:{ *:[f16] }:$src0, i32:{ *:[i32] }:$src0_mods)), (VOP3Mods:{ *:[f16] } f16:{ *:[f16] }:$src2, i32:{ *:[i32] }:$src2_mods)), (fminnum_ieee:{ *:[f16] } (VOP3Mods:{ *:[f16] } f16:{ *:[f16] }:$src0, i32:{ *:[i32] }:$src0_mods), (VOP3Mods:{ *:[f16] } f16:{ *:[f16] }:$src1, i32:{ *:[i32] }:$src1_mods)))<<P:Predicate_fmaxnum_like_nnan>>  =>  (V_MED3_F16_e64:{ *:[f16] } ?:{ *:[i32] }:$src0_mods, ?:{ *:[f16] }:$src0, ?:{ *:[i32] }:$src1_mods, ?:{ *:[f16] }:$src1, ?:{ *:[i32] }:$src2_mods, ?:{ *:[f16] }:$src2, 0:{ *:[i1] })
        GIR_BuildMI, /*InsnID*/0, /*Opcode*/GIMT_Encode2(AMDGPU::V_MED3_F16_e64),
        GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/0, // DstI[vdst]
        GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(1), /*SubOperand*/1, // src0_mods
        GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(1), /*SubOperand*/0, // src0
        GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/1, // src1_mods
        GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/0, // src1
        GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(2), /*SubOperand*/1, // src2_mods
        GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(2), /*SubOperand*/0, // src2
        GIR_AddImm8, /*InsnID*/0, /*Imm*/0,
        GIR_AddImm8, /*InsnID*/0, /*Imm*/0,
        GIR_AddImm8, /*InsnID*/0, /*Imm*/0,
        GIR_ConstrainSelectedInstOperands, /*InsnID*/0,
        GIR_EraseFromParent, /*InsnID*/0,
        // GIR_Coverage, 10539,
        GIR_Done,
      // Label 5044: @364976
      GIM_Try, /*On fail goto*//*Label 5045*/ GIMT_Encode4(365122), // Rule ID 10540 //
        GIM_CheckFeatures, GIMT_Encode2(GIFBS_isGFX9Plus),
        GIM_CheckRegBankForClass, /*MI*/0, /*Op*/0, /*RC*/GIMT_Encode2(AMDGPU::VGPR_32RegClassID),
        GIM_RecordInsn, /*DefineMI*/1, /*MI*/0, /*OpIdx*/1, // MIs[1]
        GIM_CheckOpcode, /*MI*/1, GIMT_Encode2(TargetOpcode::G_FMINNUM_IEEE),
        GIM_CheckType, /*MI*/1, /*Op*/1, /*Type*/GILLT_s16,
        GIM_CheckType, /*MI*/1, /*Op*/2, /*Type*/GILLT_s16,
        GIM_RecordInsn, /*DefineMI*/2, /*MI*/1, /*OpIdx*/1, // MIs[2]
        GIM_CheckOpcode, /*MI*/2, GIMT_Encode2(TargetOpcode::G_FMAXNUM_IEEE),
        GIM_CheckType, /*MI*/2, /*Op*/1, /*Type*/GILLT_s16,
        GIM_CheckType, /*MI*/2, /*Op*/2, /*Type*/GILLT_s16,
        GIM_RecordInsn, /*DefineMI*/3, /*MI*/0, /*OpIdx*/2, // MIs[3]
        GIM_CheckOpcode, /*MI*/3, GIMT_Encode2(TargetOpcode::G_FMINNUM_IEEE),
        // MIs[3] VOP3Mods:src1:src1_mods
        GIM_CheckIsSameOperand, /*MI*/3, /*OpIdx*/1, /*OtherMI*/2, /*OtherOpIdx*/1,
        // MIs[3] VOP3Mods:src0:src0_mods
        GIM_CheckIsSameOperand, /*MI*/3, /*OpIdx*/2, /*OtherMI*/2, /*OtherOpIdx*/2,
        GIM_CheckCxxInsnPredicate, /*MI*/0, /*FnId*/GIMT_Encode2(GICXXPred_MI_Predicate_fmaxnum_like_nnan),
        GIM_CheckIsSafeToFold, /*InsnID*/1,
        GIM_CheckIsSafeToFold, /*InsnID*/2,
        GIM_CheckIsSafeToFold, /*InsnID*/3,
        GIM_CheckComplexPattern, /*MI*/1, /*Op*/2, /*Renderer*/GIMT_Encode2(2), GIMT_Encode2(GICP_gi_vop3mods),
        GIM_CheckComplexPattern, /*MI*/2, /*Op*/1, /*Renderer*/GIMT_Encode2(0), GIMT_Encode2(GICP_gi_vop3mods),
        GIM_CheckComplexPattern, /*MI*/2, /*Op*/2, /*Renderer*/GIMT_Encode2(1), GIMT_Encode2(GICP_gi_vop3mods),
        // (fmaxnum_ieee:{ *:[f16] } (fminnum_ieee:{ *:[f16] } (fmaxnum_ieee:{ *:[f16] } (VOP3Mods:{ *:[f16] } f16:{ *:[f16] }:$src1, i32:{ *:[i32] }:$src1_mods), (VOP3Mods:{ *:[f16] } f16:{ *:[f16] }:$src0, i32:{ *:[i32] }:$src0_mods)), (VOP3Mods:{ *:[f16] } f16:{ *:[f16] }:$src2, i32:{ *:[i32] }:$src2_mods)), (fminnum_ieee:{ *:[f16] } (VOP3Mods:{ *:[f16] } f16:{ *:[f16] }:$src1, i32:{ *:[i32] }:$src1_mods), (VOP3Mods:{ *:[f16] } f16:{ *:[f16] }:$src0, i32:{ *:[i32] }:$src0_mods)))<<P:Predicate_fmaxnum_like_nnan>>  =>  (V_MED3_F16_e64:{ *:[f16] } ?:{ *:[i32] }:$src0_mods, ?:{ *:[f16] }:$src0, ?:{ *:[i32] }:$src1_mods, ?:{ *:[f16] }:$src1, ?:{ *:[i32] }:$src2_mods, ?:{ *:[f16] }:$src2, 0:{ *:[i1] })
        GIR_BuildMI, /*InsnID*/0, /*Opcode*/GIMT_Encode2(AMDGPU::V_MED3_F16_e64),
        GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/0, // DstI[vdst]
        GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(1), /*SubOperand*/1, // src0_mods
        GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(1), /*SubOperand*/0, // src0
        GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/1, // src1_mods
        GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/0, // src1
        GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(2), /*SubOperand*/1, // src2_mods
        GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(2), /*SubOperand*/0, // src2
        GIR_AddImm8, /*InsnID*/0, /*Imm*/0,
        GIR_AddImm8, /*InsnID*/0, /*Imm*/0,
        GIR_AddImm8, /*InsnID*/0, /*Imm*/0,
        GIR_ConstrainSelectedInstOperands, /*InsnID*/0,
        GIR_EraseFromParent, /*InsnID*/0,
        // GIR_Coverage, 10540,
        GIR_Done,
      // Label 5045: @365122
      GIM_Try, /*On fail goto*//*Label 5046*/ GIMT_Encode4(365227), // Rule ID 10523 //
        GIM_CheckFeatures, GIMT_Encode2(GIFBS_isGFX11Plus),
        GIM_CheckRegBankForClass, /*MI*/0, /*Op*/0, /*RC*/GIMT_Encode2(AMDGPU::VGPR_32RegClassID),
        GIM_RecordInsn, /*DefineMI*/1, /*MI*/0, /*OpIdx*/2, // MIs[1]
        GIM_CheckOpcode, /*MI*/1, GIMT_Encode2(TargetOpcode::G_FMINNUM),
        GIM_CheckType, /*MI*/1, /*Op*/1, /*Type*/GILLT_s16,
        GIM_CheckType, /*MI*/1, /*Op*/2, /*Type*/GILLT_s16,
        GIM_CheckCxxInsnPredicate, /*MI*/1, /*FnId*/GIMT_Encode2(GICXXPred_MI_Predicate_fminnum_oneuse),
        GIM_CheckIsSafeToFold, /*InsnID*/1,
        GIM_CheckComplexPattern, /*MI*/0, /*Op*/1, /*Renderer*/GIMT_Encode2(0), GIMT_Encode2(GICP_gi_vop3mods),
        GIM_CheckComplexPattern, /*MI*/1, /*Op*/1, /*Renderer*/GIMT_Encode2(1), GIMT_Encode2(GICP_gi_vop3mods),
        GIM_CheckComplexPattern, /*MI*/1, /*Op*/2, /*Renderer*/GIMT_Encode2(2), GIMT_Encode2(GICP_gi_vop3mods),
        // (fmaxnum_ieee:{ *:[f16] } (VOP3Mods:{ *:[f16] } f16:{ *:[f16] }:$src2, i32:{ *:[i32] }:$src2_mods), (fminnum:{ *:[f16] } (VOP3Mods:{ *:[f16] } f16:{ *:[f16] }:$src0, i32:{ *:[i32] }:$src0_mods), (VOP3Mods:{ *:[f16] } f16:{ *:[f16] }:$src1, i32:{ *:[i32] }:$src1_mods))<<P:Predicate_fminnum_oneuse>>)  =>  (V_MINMAX_F16_e64:{ *:[f16] } ?:{ *:[i32] }:$src0_mods, ?:{ *:[f16] }:$src0, ?:{ *:[i32] }:$src1_mods, ?:{ *:[f16] }:$src1, ?:{ *:[i32] }:$src2_mods, ?:{ *:[f16] }:$src2, 0:{ *:[i1] }, 0:{ *:[i32] })
        GIR_BuildMI, /*InsnID*/0, /*Opcode*/GIMT_Encode2(AMDGPU::V_MINMAX_F16_e64),
        GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/0, // DstI[vdst]
        GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(1), /*SubOperand*/1, // src0_mods
        GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(1), /*SubOperand*/0, // src0
        GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(2), /*SubOperand*/1, // src1_mods
        GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(2), /*SubOperand*/0, // src1
        GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/1, // src2_mods
        GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/0, // src2
        GIR_AddImm8, /*InsnID*/0, /*Imm*/0,
        GIR_AddImm8, /*InsnID*/0, /*Imm*/0,
        GIR_ConstrainSelectedInstOperands, /*InsnID*/0,
        GIR_EraseFromParent, /*InsnID*/0,
        // GIR_Coverage, 10523,
        GIR_Done,
      // Label 5046: @365227
      GIM_Try, /*On fail goto*//*Label 5047*/ GIMT_Encode4(365332), // Rule ID 10522 //
        GIM_CheckFeatures, GIMT_Encode2(GIFBS_isGFX11Plus),
        GIM_CheckRegBankForClass, /*MI*/0, /*Op*/0, /*RC*/GIMT_Encode2(AMDGPU::VGPR_32RegClassID),
        GIM_RecordInsn, /*DefineMI*/1, /*MI*/0, /*OpIdx*/2, // MIs[1]
        GIM_CheckOpcode, /*MI*/1, GIMT_Encode2(TargetOpcode::G_FMINNUM_IEEE),
        GIM_CheckType, /*MI*/1, /*Op*/1, /*Type*/GILLT_s16,
        GIM_CheckType, /*MI*/1, /*Op*/2, /*Type*/GILLT_s16,
        GIM_CheckCxxInsnPredicate, /*MI*/1, /*FnId*/GIMT_Encode2(GICXXPred_MI_Predicate_fminnum_ieee_oneuse),
        GIM_CheckIsSafeToFold, /*InsnID*/1,
        GIM_CheckComplexPattern, /*MI*/0, /*Op*/1, /*Renderer*/GIMT_Encode2(0), GIMT_Encode2(GICP_gi_vop3mods),
        GIM_CheckComplexPattern, /*MI*/1, /*Op*/1, /*Renderer*/GIMT_Encode2(1), GIMT_Encode2(GICP_gi_vop3mods),
        GIM_CheckComplexPattern, /*MI*/1, /*Op*/2, /*Renderer*/GIMT_Encode2(2), GIMT_Encode2(GICP_gi_vop3mods),
        // (fmaxnum_ieee:{ *:[f16] } (VOP3Mods:{ *:[f16] } f16:{ *:[f16] }:$src2, i32:{ *:[i32] }:$src2_mods), (fminnum_ieee:{ *:[f16] } (VOP3Mods:{ *:[f16] } f16:{ *:[f16] }:$src0, i32:{ *:[i32] }:$src0_mods), (VOP3Mods:{ *:[f16] } f16:{ *:[f16] }:$src1, i32:{ *:[i32] }:$src1_mods))<<P:Predicate_fminnum_ieee_oneuse>>)  =>  (V_MINMAX_F16_e64:{ *:[f16] } ?:{ *:[i32] }:$src0_mods, ?:{ *:[f16] }:$src0, ?:{ *:[i32] }:$src1_mods, ?:{ *:[f16] }:$src1, ?:{ *:[i32] }:$src2_mods, ?:{ *:[f16] }:$src2, 0:{ *:[i1] }, 0:{ *:[i32] })
        GIR_BuildMI, /*InsnID*/0, /*Opcode*/GIMT_Encode2(AMDGPU::V_MINMAX_F16_e64),
        GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/0, // DstI[vdst]
        GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(1), /*SubOperand*/1, // src0_mods
        GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(1), /*SubOperand*/0, // src0
        GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(2), /*SubOperand*/1, // src1_mods
        GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(2), /*SubOperand*/0, // src1
        GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/1, // src2_mods
        GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/0, // src2
        GIR_AddImm8, /*InsnID*/0, /*Imm*/0,
        GIR_AddImm8, /*InsnID*/0, /*Imm*/0,
        GIR_ConstrainSelectedInstOperands, /*InsnID*/0,
        GIR_EraseFromParent, /*InsnID*/0,
        // GIR_Coverage, 10522,
        GIR_Done,
      // Label 5047: @365332
      GIM_Try, /*On fail goto*//*Label 5048*/ GIMT_Encode4(365437), // Rule ID 6529 //
        GIM_CheckFeatures, GIMT_Encode2(GIFBS_isGFX11Plus),
        GIM_CheckRegBankForClass, /*MI*/0, /*Op*/0, /*RC*/GIMT_Encode2(AMDGPU::VGPR_32RegClassID),
        GIM_RecordInsn, /*DefineMI*/1, /*MI*/0, /*OpIdx*/1, // MIs[1]
        GIM_CheckOpcode, /*MI*/1, GIMT_Encode2(TargetOpcode::G_FMINNUM),
        GIM_CheckType, /*MI*/1, /*Op*/1, /*Type*/GILLT_s16,
        GIM_CheckType, /*MI*/1, /*Op*/2, /*Type*/GILLT_s16,
        GIM_CheckCxxInsnPredicate, /*MI*/1, /*FnId*/GIMT_Encode2(GICXXPred_MI_Predicate_fminnum_oneuse),
        GIM_CheckIsSafeToFold, /*InsnID*/1,
        GIM_CheckComplexPattern, /*MI*/0, /*Op*/2, /*Renderer*/GIMT_Encode2(2), GIMT_Encode2(GICP_gi_vop3mods),
        GIM_CheckComplexPattern, /*MI*/1, /*Op*/1, /*Renderer*/GIMT_Encode2(0), GIMT_Encode2(GICP_gi_vop3mods),
        GIM_CheckComplexPattern, /*MI*/1, /*Op*/2, /*Renderer*/GIMT_Encode2(1), GIMT_Encode2(GICP_gi_vop3mods),
        // (fmaxnum_ieee:{ *:[f16] } (fminnum:{ *:[f16] } (VOP3Mods:{ *:[f16] } f16:{ *:[f16] }:$src0, i32:{ *:[i32] }:$src0_mods), (VOP3Mods:{ *:[f16] } f16:{ *:[f16] }:$src1, i32:{ *:[i32] }:$src1_mods))<<P:Predicate_fminnum_oneuse>>, (VOP3Mods:{ *:[f16] } f16:{ *:[f16] }:$src2, i32:{ *:[i32] }:$src2_mods))  =>  (V_MINMAX_F16_e64:{ *:[f16] } ?:{ *:[i32] }:$src0_mods, ?:{ *:[f16] }:$src0, ?:{ *:[i32] }:$src1_mods, ?:{ *:[f16] }:$src1, ?:{ *:[i32] }:$src2_mods, ?:{ *:[f16] }:$src2, 0:{ *:[i1] }, 0:{ *:[i32] })
        GIR_BuildMI, /*InsnID*/0, /*Opcode*/GIMT_Encode2(AMDGPU::V_MINMAX_F16_e64),
        GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/0, // DstI[vdst]
        GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/1, // src0_mods
        GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/0, // src0
        GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(1), /*SubOperand*/1, // src1_mods
        GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(1), /*SubOperand*/0, // src1
        GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(2), /*SubOperand*/1, // src2_mods
        GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(2), /*SubOperand*/0, // src2
        GIR_AddImm8, /*InsnID*/0, /*Imm*/0,
        GIR_AddImm8, /*InsnID*/0, /*Imm*/0,
        GIR_ConstrainSelectedInstOperands, /*InsnID*/0,
        GIR_EraseFromParent, /*InsnID*/0,
        // GIR_Coverage, 6529,
        GIR_Done,
      // Label 5048: @365437
      GIM_Try, /*On fail goto*//*Label 5049*/ GIMT_Encode4(365542), // Rule ID 6528 //
        GIM_CheckFeatures, GIMT_Encode2(GIFBS_isGFX11Plus),
        GIM_CheckRegBankForClass, /*MI*/0, /*Op*/0, /*RC*/GIMT_Encode2(AMDGPU::VGPR_32RegClassID),
        GIM_RecordInsn, /*DefineMI*/1, /*MI*/0, /*OpIdx*/1, // MIs[1]
        GIM_CheckOpcode, /*MI*/1, GIMT_Encode2(TargetOpcode::G_FMINNUM_IEEE),
        GIM_CheckType, /*MI*/1, /*Op*/1, /*Type*/GILLT_s16,
        GIM_CheckType, /*MI*/1, /*Op*/2, /*Type*/GILLT_s16,
        GIM_CheckCxxInsnPredicate, /*MI*/1, /*FnId*/GIMT_Encode2(GICXXPred_MI_Predicate_fminnum_ieee_oneuse),
        GIM_CheckIsSafeToFold, /*InsnID*/1,
        GIM_CheckComplexPattern, /*MI*/0, /*Op*/2, /*Renderer*/GIMT_Encode2(2), GIMT_Encode2(GICP_gi_vop3mods),
        GIM_CheckComplexPattern, /*MI*/1, /*Op*/1, /*Renderer*/GIMT_Encode2(0), GIMT_Encode2(GICP_gi_vop3mods),
        GIM_CheckComplexPattern, /*MI*/1, /*Op*/2, /*Renderer*/GIMT_Encode2(1), GIMT_Encode2(GICP_gi_vop3mods),
        // (fmaxnum_ieee:{ *:[f16] } (fminnum_ieee:{ *:[f16] } (VOP3Mods:{ *:[f16] } f16:{ *:[f16] }:$src0, i32:{ *:[i32] }:$src0_mods), (VOP3Mods:{ *:[f16] } f16:{ *:[f16] }:$src1, i32:{ *:[i32] }:$src1_mods))<<P:Predicate_fminnum_ieee_oneuse>>, (VOP3Mods:{ *:[f16] } f16:{ *:[f16] }:$src2, i32:{ *:[i32] }:$src2_mods))  =>  (V_MINMAX_F16_e64:{ *:[f16] } ?:{ *:[i32] }:$src0_mods, ?:{ *:[f16] }:$src0, ?:{ *:[i32] }:$src1_mods, ?:{ *:[f16] }:$src1, ?:{ *:[i32] }:$src2_mods, ?:{ *:[f16] }:$src2, 0:{ *:[i1] }, 0:{ *:[i32] })
        GIR_BuildMI, /*InsnID*/0, /*Opcode*/GIMT_Encode2(AMDGPU::V_MINMAX_F16_e64),
        GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/0, // DstI[vdst]
        GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/1, // src0_mods
        GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/0, // src0
        GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(1), /*SubOperand*/1, // src1_mods
        GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(1), /*SubOperand*/0, // src1
        GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(2), /*SubOperand*/1, // src2_mods
        GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(2), /*SubOperand*/0, // src2
        GIR_AddImm8, /*InsnID*/0, /*Imm*/0,
        GIR_AddImm8, /*InsnID*/0, /*Imm*/0,
        GIR_ConstrainSelectedInstOperands, /*InsnID*/0,
        GIR_EraseFromParent, /*InsnID*/0,
        // GIR_Coverage, 6528,
        GIR_Done,
      // Label 5049: @365542
      GIM_Try, /*On fail goto*//*Label 5050*/ GIMT_Encode4(365581), // Rule ID 104 //
        GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasSALUFloatInsts),
        GIM_CheckRegBankForClass, /*MI*/0, /*Op*/0, /*RC*/GIMT_Encode2(AMDGPU::SReg_32RegClassID),
        GIM_CheckRegBankForClass, /*MI*/0, /*Op*/1, /*RC*/GIMT_Encode2(AMDGPU::SReg_32RegClassID),
        GIM_CheckRegBankForClass, /*MI*/0, /*Op*/2, /*RC*/GIMT_Encode2(AMDGPU::SReg_32RegClassID),
        GIM_CheckCxxInsnPredicate, /*MI*/0, /*FnId*/GIMT_Encode2(GICXXPred_MI_Predicate_anonymous_17632),
        // (fmaxnum_ieee:{ *:[f16] } SSrc_f16:{ *:[f16] }:$src0, SSrc_f16:{ *:[f16] }:$src1)<<P:Predicate_anonymous_17632>>  =>  (S_MAX_F16:{ *:[f16] } SSrc_f16:{ *:[f16] }:$src0, SSrc_f16:{ *:[f16] }:$src1)
        GIR_MutateOpcode, /*InsnID*/0, /*RecycleInsnID*/0, /*Opcode*/GIMT_Encode2(AMDGPU::S_MAX_F16),
        GIR_AddImplicitUse, /*InsnID*/0, GIMT_Encode2(AMDGPU::MODE),
        GIR_ConstrainSelectedInstOperands, /*InsnID*/0,
        // GIR_Coverage, 104,
        GIR_Done,
      // Label 5050: @365581
      GIM_Try, /*On fail goto*//*Label 5051*/ GIMT_Encode4(365651), // Rule ID 813 //
        GIM_CheckFeatures, GIMT_Encode2(GIFBS_Has16BitInsts_NotHasTrue16BitInsts),
        GIM_CheckRegBankForClass, /*MI*/0, /*Op*/0, /*RC*/GIMT_Encode2(AMDGPU::VGPR_32RegClassID),
        GIM_CheckComplexPattern, /*MI*/0, /*Op*/1, /*Renderer*/GIMT_Encode2(0), GIMT_Encode2(GICP_gi_vop3mods0),
        GIM_CheckComplexPattern, /*MI*/0, /*Op*/2, /*Renderer*/GIMT_Encode2(1), GIMT_Encode2(GICP_gi_vop3mods),
        // (fmaxnum_ieee:{ *:[f16] } (VOP3Mods0:{ *:[f16] } f16:{ *:[f16] }:$src0, i32:{ *:[i32] }:$src0_modifiers, i1:{ *:[i1] }:$clamp, i32:{ *:[i32] }:$omod), (VOP3Mods:{ *:[f16] } f16:{ *:[f16] }:$src1, i32:{ *:[i32] }:$src1_modifiers))  =>  (V_MAX_F16_e64:{ *:[f16] } i32:{ *:[i32] }:$src0_modifiers, f16:{ *:[f16] }:$src0, i32:{ *:[i32] }:$src1_modifiers, f16:{ *:[f16] }:$src1, i1:{ *:[i1] }:$clamp, i32:{ *:[i32] }:$omod)
        GIR_BuildMI, /*InsnID*/0, /*Opcode*/GIMT_Encode2(AMDGPU::V_MAX_F16_e64),
        GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/0, // DstI[vdst]
        GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/1, // src0_modifiers
        GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/0, // src0
        GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(1), /*SubOperand*/1, // src1_modifiers
        GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(1), /*SubOperand*/0, // src1
        GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/2, // clamp
        GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/3, // omod
        GIR_ConstrainSelectedInstOperands, /*InsnID*/0,
        GIR_EraseFromParent, /*InsnID*/0,
        // GIR_Coverage, 813,
        GIR_Done,
      // Label 5051: @365651
      GIM_Try, /*On fail goto*//*Label 5052*/ GIMT_Encode4(365721), // Rule ID 815 //
        GIM_CheckFeatures, GIMT_Encode2(GIFBS_UseRealTrue16Insts),
        GIM_CheckRegBankForClass, /*MI*/0, /*Op*/0, /*RC*/GIMT_Encode2(AMDGPU::VGPR_16RegClassID),
        GIM_CheckComplexPattern, /*MI*/0, /*Op*/1, /*Renderer*/GIMT_Encode2(0), GIMT_Encode2(GICP_gi_vop3mods0),
        GIM_CheckComplexPattern, /*MI*/0, /*Op*/2, /*Renderer*/GIMT_Encode2(1), GIMT_Encode2(GICP_gi_vop3mods),
        // (fmaxnum_ieee:{ *:[f16] } (VOP3Mods0:{ *:[f16] } f16:{ *:[f16] }:$src0, i32:{ *:[i32] }:$src0_modifiers, i1:{ *:[i1] }:$clamp, i32:{ *:[i32] }:$omod), (VOP3Mods:{ *:[f16] } f16:{ *:[f16] }:$src1, i32:{ *:[i32] }:$src1_modifiers))  =>  (V_MAX_F16_t16_e64:{ *:[f16] } i32:{ *:[i32] }:$src0_modifiers, f16:{ *:[f16] }:$src0, i32:{ *:[i32] }:$src1_modifiers, f16:{ *:[f16] }:$src1, i1:{ *:[i1] }:$clamp, i32:{ *:[i32] }:$omod)
        GIR_BuildMI, /*InsnID*/0, /*Opcode*/GIMT_Encode2(AMDGPU::V_MAX_F16_t16_e64),
        GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/0, // DstI[vdst]
        GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/1, // src0_modifiers
        GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/0, // src0
        GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(1), /*SubOperand*/1, // src1_modifiers
        GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(1), /*SubOperand*/0, // src1
        GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/2, // clamp
        GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/3, // omod
        GIR_ConstrainSelectedInstOperands, /*InsnID*/0,
        GIR_EraseFromParent, /*InsnID*/0,
        // GIR_Coverage, 815,
        GIR_Done,
      // Label 5052: @365721
      GIM_Try, /*On fail goto*//*Label 5053*/ GIMT_Encode4(365791), // Rule ID 817 //
        GIM_CheckFeatures, GIMT_Encode2(GIFBS_UseFakeTrue16Insts),
        GIM_CheckRegBankForClass, /*MI*/0, /*Op*/0, /*RC*/GIMT_Encode2(AMDGPU::VGPR_32RegClassID),
        GIM_CheckComplexPattern, /*MI*/0, /*Op*/1, /*Renderer*/GIMT_Encode2(0), GIMT_Encode2(GICP_gi_vop3mods0),
        GIM_CheckComplexPattern, /*MI*/0, /*Op*/2, /*Renderer*/GIMT_Encode2(1), GIMT_Encode2(GICP_gi_vop3mods),
        // (fmaxnum_ieee:{ *:[f16] } (VOP3Mods0:{ *:[f16] } f16:{ *:[f16] }:$src0, i32:{ *:[i32] }:$src0_modifiers, i1:{ *:[i1] }:$clamp, i32:{ *:[i32] }:$omod), (VOP3Mods:{ *:[f16] } f16:{ *:[f16] }:$src1, i32:{ *:[i32] }:$src1_modifiers))  =>  (V_MAX_F16_fake16_e64:{ *:[f16] } i32:{ *:[i32] }:$src0_modifiers, f16:{ *:[f16] }:$src0, i32:{ *:[i32] }:$src1_modifiers, f16:{ *:[f16] }:$src1, i1:{ *:[i1] }:$clamp, i32:{ *:[i32] }:$omod)
        GIR_BuildMI, /*InsnID*/0, /*Opcode*/GIMT_Encode2(AMDGPU::V_MAX_F16_fake16_e64),
        GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/0, // DstI[vdst]
        GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/1, // src0_modifiers
        GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/0, // src0
        GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(1), /*SubOperand*/1, // src1_modifiers
        GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(1), /*SubOperand*/0, // src1
        GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/2, // clamp
        GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/3, // omod
        GIR_ConstrainSelectedInstOperands, /*InsnID*/0,
        GIR_EraseFromParent, /*InsnID*/0,
        // GIR_Coverage, 817,
        GIR_Done,
      // Label 5053: @365791
      GIM_Try, /*On fail goto*//*Label 5054*/ GIMT_Encode4(365861), // Rule ID 7148 //
        GIM_CheckFeatures, GIMT_Encode2(GIFBS_Has16BitInsts_NotHasTrue16BitInsts),
        GIM_CheckRegBankForClass, /*MI*/0, /*Op*/0, /*RC*/GIMT_Encode2(AMDGPU::VGPR_32RegClassID),
        GIM_CheckComplexPattern, /*MI*/0, /*Op*/1, /*Renderer*/GIMT_Encode2(0), GIMT_Encode2(GICP_gi_vop3mods),
        GIM_CheckComplexPattern, /*MI*/0, /*Op*/2, /*Renderer*/GIMT_Encode2(1), GIMT_Encode2(GICP_gi_vop3mods0),
        // (fmaxnum_ieee:{ *:[f16] } (VOP3Mods:{ *:[f16] } f16:{ *:[f16] }:$src1, i32:{ *:[i32] }:$src1_modifiers), (VOP3Mods0:{ *:[f16] } f16:{ *:[f16] }:$src0, i32:{ *:[i32] }:$src0_modifiers, i1:{ *:[i1] }:$clamp, i32:{ *:[i32] }:$omod))  =>  (V_MAX_F16_e64:{ *:[f16] } i32:{ *:[i32] }:$src0_modifiers, f16:{ *:[f16] }:$src0, i32:{ *:[i32] }:$src1_modifiers, f16:{ *:[f16] }:$src1, i1:{ *:[i1] }:$clamp, i32:{ *:[i32] }:$omod)
        GIR_BuildMI, /*InsnID*/0, /*Opcode*/GIMT_Encode2(AMDGPU::V_MAX_F16_e64),
        GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/0, // DstI[vdst]
        GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(1), /*SubOperand*/1, // src0_modifiers
        GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(1), /*SubOperand*/0, // src0
        GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/1, // src1_modifiers
        GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/0, // src1
        GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(1), /*SubOperand*/2, // clamp
        GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(1), /*SubOperand*/3, // omod
        GIR_ConstrainSelectedInstOperands, /*InsnID*/0,
        GIR_EraseFromParent, /*InsnID*/0,
        // GIR_Coverage, 7148,
        GIR_Done,
      // Label 5054: @365861
      GIM_Try, /*On fail goto*//*Label 5055*/ GIMT_Encode4(365931), // Rule ID 7150 //
        GIM_CheckFeatures, GIMT_Encode2(GIFBS_UseRealTrue16Insts),
        GIM_CheckRegBankForClass, /*MI*/0, /*Op*/0, /*RC*/GIMT_Encode2(AMDGPU::VGPR_16RegClassID),
        GIM_CheckComplexPattern, /*MI*/0, /*Op*/1, /*Renderer*/GIMT_Encode2(0), GIMT_Encode2(GICP_gi_vop3mods),
        GIM_CheckComplexPattern, /*MI*/0, /*Op*/2, /*Renderer*/GIMT_Encode2(1), GIMT_Encode2(GICP_gi_vop3mods0),
        // (fmaxnum_ieee:{ *:[f16] } (VOP3Mods:{ *:[f16] } f16:{ *:[f16] }:$src1, i32:{ *:[i32] }:$src1_modifiers), (VOP3Mods0:{ *:[f16] } f16:{ *:[f16] }:$src0, i32:{ *:[i32] }:$src0_modifiers, i1:{ *:[i1] }:$clamp, i32:{ *:[i32] }:$omod))  =>  (V_MAX_F16_t16_e64:{ *:[f16] } i32:{ *:[i32] }:$src0_modifiers, f16:{ *:[f16] }:$src0, i32:{ *:[i32] }:$src1_modifiers, f16:{ *:[f16] }:$src1, i1:{ *:[i1] }:$clamp, i32:{ *:[i32] }:$omod)
        GIR_BuildMI, /*InsnID*/0, /*Opcode*/GIMT_Encode2(AMDGPU::V_MAX_F16_t16_e64),
        GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/0, // DstI[vdst]
        GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(1), /*SubOperand*/1, // src0_modifiers
        GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(1), /*SubOperand*/0, // src0
        GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/1, // src1_modifiers
        GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/0, // src1
        GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(1), /*SubOperand*/2, // clamp
        GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(1), /*SubOperand*/3, // omod
        GIR_ConstrainSelectedInstOperands, /*InsnID*/0,
        GIR_EraseFromParent, /*InsnID*/0,
        // GIR_Coverage, 7150,
        GIR_Done,
      // Label 5055: @365931
      GIM_Try, /*On fail goto*//*Label 5056*/ GIMT_Encode4(366001), // Rule ID 7152 //
        GIM_CheckFeatures, GIMT_Encode2(GIFBS_UseFakeTrue16Insts),
        GIM_CheckRegBankForClass, /*MI*/0, /*Op*/0, /*RC*/GIMT_Encode2(AMDGPU::VGPR_32RegClassID),
        GIM_CheckComplexPattern, /*MI*/0, /*Op*/1, /*Renderer*/GIMT_Encode2(0), GIMT_Encode2(GICP_gi_vop3mods),
        GIM_CheckComplexPattern, /*MI*/0, /*Op*/2, /*Renderer*/GIMT_Encode2(1), GIMT_Encode2(GICP_gi_vop3mods0),
        // (fmaxnum_ieee:{ *:[f16] } (VOP3Mods:{ *:[f16] } f16:{ *:[f16] }:$src1, i32:{ *:[i32] }:$src1_modifiers), (VOP3Mods0:{ *:[f16] } f16:{ *:[f16] }:$src0, i32:{ *:[i32] }:$src0_modifiers, i1:{ *:[i1] }:$clamp, i32:{ *:[i32] }:$omod))  =>  (V_MAX_F16_fake16_e64:{ *:[f16] } i32:{ *:[i32] }:$src0_modifiers, f16:{ *:[f16] }:$src0, i32:{ *:[i32] }:$src1_modifiers, f16:{ *:[f16] }:$src1, i1:{ *:[i1] }:$clamp, i32:{ *:[i32] }:$omod)
        GIR_BuildMI, /*InsnID*/0, /*Opcode*/GIMT_Encode2(AMDGPU::V_MAX_F16_fake16_e64),
        GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/0, // DstI[vdst]
        GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(1), /*SubOperand*/1, // src0_modifiers
        GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(1), /*SubOperand*/0, // src0
        GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/1, // src1_modifiers
        GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/0, // src1
        GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(1), /*SubOperand*/2, // clamp
        GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(1), /*SubOperand*/3, // omod
        GIR_ConstrainSelectedInstOperands, /*InsnID*/0,
        GIR_EraseFromParent, /*InsnID*/0,
        // GIR_Coverage, 7152,
        GIR_Done,
      // Label 5056: @366001
      GIM_Reject,
    // Label 4917: @366002
    GIM_Reject,
    // Label 4913: @366003
    GIM_Try, /*On fail goto*//*Label 5057*/ GIMT_Encode4(384530),
      GIM_CheckType, /*MI*/0, /*Op*/1, /*Type*/GILLT_s32,
      GIM_CheckType, /*MI*/0, /*Op*/2, /*Type*/GILLT_s32,
      GIM_Try, /*On fail goto*//*Label 5058*/ GIMT_Encode4(366156), // Rule ID 10106 //
        GIM_CheckRegBankForClass, /*MI*/0, /*Op*/0, /*RC*/GIMT_Encode2(AMDGPU::VGPR_32RegClassID),
        GIM_RecordInsn, /*DefineMI*/1, /*MI*/0, /*OpIdx*/1, // MIs[1]
        GIM_CheckOpcode, /*MI*/1, GIMT_Encode2(TargetOpcode::G_FMINNUM),
        GIM_CheckType, /*MI*/1, /*Op*/1, /*Type*/GILLT_s32,
        GIM_CheckType, /*MI*/1, /*Op*/2, /*Type*/GILLT_s32,
        GIM_RecordInsn, /*DefineMI*/2, /*MI*/0, /*OpIdx*/2, // MIs[2]
        GIM_CheckOpcode, /*MI*/2, GIMT_Encode2(TargetOpcode::G_FMINNUM),
        GIM_CheckType, /*MI*/2, /*Op*/1, /*Type*/GILLT_s32,
        GIM_CheckType, /*MI*/2, /*Op*/2, /*Type*/GILLT_s32,
        GIM_RecordInsn, /*DefineMI*/3, /*MI*/2, /*OpIdx*/2, // MIs[3]
        GIM_CheckOpcode, /*MI*/3, GIMT_Encode2(TargetOpcode::G_FMAXNUM),
        // MIs[3] VOP3Mods:src0:src0_mods
        GIM_CheckIsSameOperand, /*MI*/3, /*OpIdx*/1, /*OtherMI*/1, /*OtherOpIdx*/1,
        // MIs[3] VOP3Mods:src1:src1_mods
        GIM_CheckIsSameOperand, /*MI*/3, /*OpIdx*/2, /*OtherMI*/1, /*OtherOpIdx*/2,
        GIM_CheckCxxInsnPredicate, /*MI*/0, /*FnId*/GIMT_Encode2(GICXXPred_MI_Predicate_fmaxnum_like_nnan),
        GIM_CheckIsSafeToFold, /*InsnID*/1,
        GIM_CheckIsSafeToFold, /*InsnID*/2,
        GIM_CheckIsSafeToFold, /*InsnID*/3,
        GIM_CheckComplexPattern, /*MI*/1, /*Op*/1, /*Renderer*/GIMT_Encode2(0), GIMT_Encode2(GICP_gi_vop3mods),
        GIM_CheckComplexPattern, /*MI*/1, /*Op*/2, /*Renderer*/GIMT_Encode2(1), GIMT_Encode2(GICP_gi_vop3mods),
        GIM_CheckComplexPattern, /*MI*/2, /*Op*/1, /*Renderer*/GIMT_Encode2(2), GIMT_Encode2(GICP_gi_vop3mods),
        // (fmaxnum_ieee:{ *:[f32] } (fminnum:{ *:[f32] } (VOP3Mods:{ *:[f32] } f32:{ *:[f32] }:$src0, i32:{ *:[i32] }:$src0_mods), (VOP3Mods:{ *:[f32] } f32:{ *:[f32] }:$src1, i32:{ *:[i32] }:$src1_mods)), (fminnum:{ *:[f32] } (VOP3Mods:{ *:[f32] } f32:{ *:[f32] }:$src2, i32:{ *:[i32] }:$src2_mods), (fmaxnum:{ *:[f32] } (VOP3Mods:{ *:[f32] } f32:{ *:[f32] }:$src0, i32:{ *:[i32] }:$src0_mods), (VOP3Mods:{ *:[f32] } f32:{ *:[f32] }:$src1, i32:{ *:[i32] }:$src1_mods))))<<P:Predicate_fmaxnum_like_nnan>>  =>  (V_MED3_F32_e64:{ *:[f32] } ?:{ *:[i32] }:$src0_mods, ?:{ *:[f32] }:$src0, ?:{ *:[i32] }:$src1_mods, ?:{ *:[f32] }:$src1, ?:{ *:[i32] }:$src2_mods, ?:{ *:[f32] }:$src2, 0:{ *:[i1] }, 0:{ *:[i32] })
        GIR_BuildMI, /*InsnID*/0, /*Opcode*/GIMT_Encode2(AMDGPU::V_MED3_F32_e64),
        GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/0, // DstI[vdst]
        GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/1, // src0_mods
        GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/0, // src0
        GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(1), /*SubOperand*/1, // src1_mods
        GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(1), /*SubOperand*/0, // src1
        GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(2), /*SubOperand*/1, // src2_mods
        GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(2), /*SubOperand*/0, // src2
        GIR_AddImm8, /*InsnID*/0, /*Imm*/0,
        GIR_AddImm8, /*InsnID*/0, /*Imm*/0,
        GIR_ConstrainSelectedInstOperands, /*InsnID*/0,
        GIR_EraseFromParent, /*InsnID*/0,
        // GIR_Coverage, 10106,
        GIR_Done,
      // Label 5058: @366156
      GIM_Try, /*On fail goto*//*Label 5059*/ GIMT_Encode4(366296), // Rule ID 10107 //
        GIM_CheckRegBankForClass, /*MI*/0, /*Op*/0, /*RC*/GIMT_Encode2(AMDGPU::VGPR_32RegClassID),
        GIM_RecordInsn, /*DefineMI*/1, /*MI*/0, /*OpIdx*/1, // MIs[1]
        GIM_CheckOpcode, /*MI*/1, GIMT_Encode2(TargetOpcode::G_FMINNUM),
        GIM_CheckType, /*MI*/1, /*Op*/1, /*Type*/GILLT_s32,
        GIM_CheckType, /*MI*/1, /*Op*/2, /*Type*/GILLT_s32,
        GIM_RecordInsn, /*DefineMI*/2, /*MI*/0, /*OpIdx*/2, // MIs[2]
        GIM_CheckOpcode, /*MI*/2, GIMT_Encode2(TargetOpcode::G_FMINNUM),
        GIM_CheckType, /*MI*/2, /*Op*/1, /*Type*/GILLT_s32,
        GIM_CheckType, /*MI*/2, /*Op*/2, /*Type*/GILLT_s32,
        GIM_RecordInsn, /*DefineMI*/3, /*MI*/2, /*OpIdx*/2, // MIs[3]
        GIM_CheckOpcode, /*MI*/3, GIMT_Encode2(TargetOpcode::G_FMAXNUM),
        // MIs[3] VOP3Mods:src1:src1_mods
        GIM_CheckIsSameOperand, /*MI*/3, /*OpIdx*/1, /*OtherMI*/1, /*OtherOpIdx*/2,
        // MIs[3] VOP3Mods:src0:src0_mods
        GIM_CheckIsSameOperand, /*MI*/3, /*OpIdx*/2, /*OtherMI*/1, /*OtherOpIdx*/1,
        GIM_CheckCxxInsnPredicate, /*MI*/0, /*FnId*/GIMT_Encode2(GICXXPred_MI_Predicate_fmaxnum_like_nnan),
        GIM_CheckIsSafeToFold, /*InsnID*/1,
        GIM_CheckIsSafeToFold, /*InsnID*/2,
        GIM_CheckIsSafeToFold, /*InsnID*/3,
        GIM_CheckComplexPattern, /*MI*/1, /*Op*/1, /*Renderer*/GIMT_Encode2(0), GIMT_Encode2(GICP_gi_vop3mods),
        GIM_CheckComplexPattern, /*MI*/1, /*Op*/2, /*Renderer*/GIMT_Encode2(1), GIMT_Encode2(GICP_gi_vop3mods),
        GIM_CheckComplexPattern, /*MI*/2, /*Op*/1, /*Renderer*/GIMT_Encode2(2), GIMT_Encode2(GICP_gi_vop3mods),
        // (fmaxnum_ieee:{ *:[f32] } (fminnum:{ *:[f32] } (VOP3Mods:{ *:[f32] } f32:{ *:[f32] }:$src0, i32:{ *:[i32] }:$src0_mods), (VOP3Mods:{ *:[f32] } f32:{ *:[f32] }:$src1, i32:{ *:[i32] }:$src1_mods)), (fminnum:{ *:[f32] } (VOP3Mods:{ *:[f32] } f32:{ *:[f32] }:$src2, i32:{ *:[i32] }:$src2_mods), (fmaxnum:{ *:[f32] } (VOP3Mods:{ *:[f32] } f32:{ *:[f32] }:$src1, i32:{ *:[i32] }:$src1_mods), (VOP3Mods:{ *:[f32] } f32:{ *:[f32] }:$src0, i32:{ *:[i32] }:$src0_mods))))<<P:Predicate_fmaxnum_like_nnan>>  =>  (V_MED3_F32_e64:{ *:[f32] } ?:{ *:[i32] }:$src0_mods, ?:{ *:[f32] }:$src0, ?:{ *:[i32] }:$src1_mods, ?:{ *:[f32] }:$src1, ?:{ *:[i32] }:$src2_mods, ?:{ *:[f32] }:$src2, 0:{ *:[i1] }, 0:{ *:[i32] })
        GIR_BuildMI, /*InsnID*/0, /*Opcode*/GIMT_Encode2(AMDGPU::V_MED3_F32_e64),
        GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/0, // DstI[vdst]
        GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/1, // src0_mods
        GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/0, // src0
        GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(1), /*SubOperand*/1, // src1_mods
        GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(1), /*SubOperand*/0, // src1
        GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(2), /*SubOperand*/1, // src2_mods
        GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(2), /*SubOperand*/0, // src2
        GIR_AddImm8, /*InsnID*/0, /*Imm*/0,
        GIR_AddImm8, /*InsnID*/0, /*Imm*/0,
        GIR_ConstrainSelectedInstOperands, /*InsnID*/0,
        GIR_EraseFromParent, /*InsnID*/0,
        // GIR_Coverage, 10107,
        GIR_Done,
      // Label 5059: @366296
      GIM_Try, /*On fail goto*//*Label 5060*/ GIMT_Encode4(366436), // Rule ID 10110 //
        GIM_CheckRegBankForClass, /*MI*/0, /*Op*/0, /*RC*/GIMT_Encode2(AMDGPU::VGPR_32RegClassID),
        GIM_RecordInsn, /*DefineMI*/1, /*MI*/0, /*OpIdx*/1, // MIs[1]
        GIM_CheckOpcode, /*MI*/1, GIMT_Encode2(TargetOpcode::G_FMINNUM),
        GIM_CheckType, /*MI*/1, /*Op*/1, /*Type*/GILLT_s32,
        GIM_CheckType, /*MI*/1, /*Op*/2, /*Type*/GILLT_s32,
        GIM_RecordInsn, /*DefineMI*/2, /*MI*/0, /*OpIdx*/2, // MIs[2]
        GIM_CheckOpcode, /*MI*/2, GIMT_Encode2(TargetOpcode::G_FMINNUM),
        GIM_CheckType, /*MI*/2, /*Op*/1, /*Type*/GILLT_s32,
        GIM_CheckType, /*MI*/2, /*Op*/2, /*Type*/GILLT_s32,
        GIM_RecordInsn, /*DefineMI*/3, /*MI*/2, /*OpIdx*/2, // MIs[3]
        GIM_CheckOpcode, /*MI*/3, GIMT_Encode2(TargetOpcode::G_FMAXNUM),
        // MIs[3] VOP3Mods:src0:src0_mods
        GIM_CheckIsSameOperand, /*MI*/3, /*OpIdx*/1, /*OtherMI*/1, /*OtherOpIdx*/2,
        // MIs[3] VOP3Mods:src1:src1_mods
        GIM_CheckIsSameOperand, /*MI*/3, /*OpIdx*/2, /*OtherMI*/1, /*OtherOpIdx*/1,
        GIM_CheckCxxInsnPredicate, /*MI*/0, /*FnId*/GIMT_Encode2(GICXXPred_MI_Predicate_fmaxnum_like_nnan),
        GIM_CheckIsSafeToFold, /*InsnID*/1,
        GIM_CheckIsSafeToFold, /*InsnID*/2,
        GIM_CheckIsSafeToFold, /*InsnID*/3,
        GIM_CheckComplexPattern, /*MI*/1, /*Op*/1, /*Renderer*/GIMT_Encode2(0), GIMT_Encode2(GICP_gi_vop3mods),
        GIM_CheckComplexPattern, /*MI*/1, /*Op*/2, /*Renderer*/GIMT_Encode2(1), GIMT_Encode2(GICP_gi_vop3mods),
        GIM_CheckComplexPattern, /*MI*/2, /*Op*/1, /*Renderer*/GIMT_Encode2(2), GIMT_Encode2(GICP_gi_vop3mods),
        // (fmaxnum_ieee:{ *:[f32] } (fminnum:{ *:[f32] } (VOP3Mods:{ *:[f32] } f32:{ *:[f32] }:$src1, i32:{ *:[i32] }:$src1_mods), (VOP3Mods:{ *:[f32] } f32:{ *:[f32] }:$src0, i32:{ *:[i32] }:$src0_mods)), (fminnum:{ *:[f32] } (VOP3Mods:{ *:[f32] } f32:{ *:[f32] }:$src2, i32:{ *:[i32] }:$src2_mods), (fmaxnum:{ *:[f32] } (VOP3Mods:{ *:[f32] } f32:{ *:[f32] }:$src0, i32:{ *:[i32] }:$src0_mods), (VOP3Mods:{ *:[f32] } f32:{ *:[f32] }:$src1, i32:{ *:[i32] }:$src1_mods))))<<P:Predicate_fmaxnum_like_nnan>>  =>  (V_MED3_F32_e64:{ *:[f32] } ?:{ *:[i32] }:$src0_mods, ?:{ *:[f32] }:$src0, ?:{ *:[i32] }:$src1_mods, ?:{ *:[f32] }:$src1, ?:{ *:[i32] }:$src2_mods, ?:{ *:[f32] }:$src2, 0:{ *:[i1] }, 0:{ *:[i32] })
        GIR_BuildMI, /*InsnID*/0, /*Opcode*/GIMT_Encode2(AMDGPU::V_MED3_F32_e64),
        GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/0, // DstI[vdst]
        GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(1), /*SubOperand*/1, // src0_mods
        GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(1), /*SubOperand*/0, // src0
        GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/1, // src1_mods
        GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/0, // src1
        GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(2), /*SubOperand*/1, // src2_mods
        GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(2), /*SubOperand*/0, // src2
        GIR_AddImm8, /*InsnID*/0, /*Imm*/0,
        GIR_AddImm8, /*InsnID*/0, /*Imm*/0,
        GIR_ConstrainSelectedInstOperands, /*InsnID*/0,
        GIR_EraseFromParent, /*InsnID*/0,
        // GIR_Coverage, 10110,
        GIR_Done,
      // Label 5060: @366436
      GIM_Try, /*On fail goto*//*Label 5061*/ GIMT_Encode4(366576), // Rule ID 10111 //
        GIM_CheckRegBankForClass, /*MI*/0, /*Op*/0, /*RC*/GIMT_Encode2(AMDGPU::VGPR_32RegClassID),
        GIM_RecordInsn, /*DefineMI*/1, /*MI*/0, /*OpIdx*/1, // MIs[1]
        GIM_CheckOpcode, /*MI*/1, GIMT_Encode2(TargetOpcode::G_FMINNUM),
        GIM_CheckType, /*MI*/1, /*Op*/1, /*Type*/GILLT_s32,
        GIM_CheckType, /*MI*/1, /*Op*/2, /*Type*/GILLT_s32,
        GIM_RecordInsn, /*DefineMI*/2, /*MI*/0, /*OpIdx*/2, // MIs[2]
        GIM_CheckOpcode, /*MI*/2, GIMT_Encode2(TargetOpcode::G_FMINNUM),
        GIM_CheckType, /*MI*/2, /*Op*/1, /*Type*/GILLT_s32,
        GIM_CheckType, /*MI*/2, /*Op*/2, /*Type*/GILLT_s32,
        GIM_RecordInsn, /*DefineMI*/3, /*MI*/2, /*OpIdx*/2, // MIs[3]
        GIM_CheckOpcode, /*MI*/3, GIMT_Encode2(TargetOpcode::G_FMAXNUM),
        // MIs[3] VOP3Mods:src1:src1_mods
        GIM_CheckIsSameOperand, /*MI*/3, /*OpIdx*/1, /*OtherMI*/1, /*OtherOpIdx*/1,
        // MIs[3] VOP3Mods:src0:src0_mods
        GIM_CheckIsSameOperand, /*MI*/3, /*OpIdx*/2, /*OtherMI*/1, /*OtherOpIdx*/2,
        GIM_CheckCxxInsnPredicate, /*MI*/0, /*FnId*/GIMT_Encode2(GICXXPred_MI_Predicate_fmaxnum_like_nnan),
        GIM_CheckIsSafeToFold, /*InsnID*/1,
        GIM_CheckIsSafeToFold, /*InsnID*/2,
        GIM_CheckIsSafeToFold, /*InsnID*/3,
        GIM_CheckComplexPattern, /*MI*/1, /*Op*/1, /*Renderer*/GIMT_Encode2(0), GIMT_Encode2(GICP_gi_vop3mods),
        GIM_CheckComplexPattern, /*MI*/1, /*Op*/2, /*Renderer*/GIMT_Encode2(1), GIMT_Encode2(GICP_gi_vop3mods),
        GIM_CheckComplexPattern, /*MI*/2, /*Op*/1, /*Renderer*/GIMT_Encode2(2), GIMT_Encode2(GICP_gi_vop3mods),
        // (fmaxnum_ieee:{ *:[f32] } (fminnum:{ *:[f32] } (VOP3Mods:{ *:[f32] } f32:{ *:[f32] }:$src1, i32:{ *:[i32] }:$src1_mods), (VOP3Mods:{ *:[f32] } f32:{ *:[f32] }:$src0, i32:{ *:[i32] }:$src0_mods)), (fminnum:{ *:[f32] } (VOP3Mods:{ *:[f32] } f32:{ *:[f32] }:$src2, i32:{ *:[i32] }:$src2_mods), (fmaxnum:{ *:[f32] } (VOP3Mods:{ *:[f32] } f32:{ *:[f32] }:$src1, i32:{ *:[i32] }:$src1_mods), (VOP3Mods:{ *:[f32] } f32:{ *:[f32] }:$src0, i32:{ *:[i32] }:$src0_mods))))<<P:Predicate_fmaxnum_like_nnan>>  =>  (V_MED3_F32_e64:{ *:[f32] } ?:{ *:[i32] }:$src0_mods, ?:{ *:[f32] }:$src0, ?:{ *:[i32] }:$src1_mods, ?:{ *:[f32] }:$src1, ?:{ *:[i32] }:$src2_mods, ?:{ *:[f32] }:$src2, 0:{ *:[i1] }, 0:{ *:[i32] })
        GIR_BuildMI, /*InsnID*/0, /*Opcode*/GIMT_Encode2(AMDGPU::V_MED3_F32_e64),
        GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/0, // DstI[vdst]
        GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(1), /*SubOperand*/1, // src0_mods
        GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(1), /*SubOperand*/0, // src0
        GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/1, // src1_mods
        GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/0, // src1
        GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(2), /*SubOperand*/1, // src2_mods
        GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(2), /*SubOperand*/0, // src2
        GIR_AddImm8, /*InsnID*/0, /*Imm*/0,
        GIR_AddImm8, /*InsnID*/0, /*Imm*/0,
        GIR_ConstrainSelectedInstOperands, /*InsnID*/0,
        GIR_EraseFromParent, /*InsnID*/0,
        // GIR_Coverage, 10111,
        GIR_Done,
      // Label 5061: @366576
      GIM_Try, /*On fail goto*//*Label 5062*/ GIMT_Encode4(366716), // Rule ID 10091 //
        GIM_CheckRegBankForClass, /*MI*/0, /*Op*/0, /*RC*/GIMT_Encode2(AMDGPU::VGPR_32RegClassID),
        GIM_RecordInsn, /*DefineMI*/1, /*MI*/0, /*OpIdx*/1, // MIs[1]
        GIM_CheckOpcode, /*MI*/1, GIMT_Encode2(TargetOpcode::G_FMINNUM),
        GIM_CheckType, /*MI*/1, /*Op*/1, /*Type*/GILLT_s32,
        GIM_CheckType, /*MI*/1, /*Op*/2, /*Type*/GILLT_s32,
        GIM_RecordInsn, /*DefineMI*/2, /*MI*/0, /*OpIdx*/2, // MIs[2]
        GIM_CheckOpcode, /*MI*/2, GIMT_Encode2(TargetOpcode::G_FMINNUM),
        GIM_CheckType, /*MI*/2, /*Op*/1, /*Type*/GILLT_s32,
        GIM_CheckType, /*MI*/2, /*Op*/2, /*Type*/GILLT_s32,
        GIM_RecordInsn, /*DefineMI*/3, /*MI*/2, /*OpIdx*/2, // MIs[3]
        GIM_CheckOpcode, /*MI*/3, GIMT_Encode2(TargetOpcode::G_FMAXNUM_IEEE),
        // MIs[3] VOP3Mods:src0:src0_mods
        GIM_CheckIsSameOperand, /*MI*/3, /*OpIdx*/1, /*OtherMI*/1, /*OtherOpIdx*/1,
        // MIs[3] VOP3Mods:src1:src1_mods
        GIM_CheckIsSameOperand, /*MI*/3, /*OpIdx*/2, /*OtherMI*/1, /*OtherOpIdx*/2,
        GIM_CheckCxxInsnPredicate, /*MI*/0, /*FnId*/GIMT_Encode2(GICXXPred_MI_Predicate_fmaxnum_like_nnan),
        GIM_CheckIsSafeToFold, /*InsnID*/1,
        GIM_CheckIsSafeToFold, /*InsnID*/2,
        GIM_CheckIsSafeToFold, /*InsnID*/3,
        GIM_CheckComplexPattern, /*MI*/1, /*Op*/1, /*Renderer*/GIMT_Encode2(0), GIMT_Encode2(GICP_gi_vop3mods),
        GIM_CheckComplexPattern, /*MI*/1, /*Op*/2, /*Renderer*/GIMT_Encode2(1), GIMT_Encode2(GICP_gi_vop3mods),
        GIM_CheckComplexPattern, /*MI*/2, /*Op*/1, /*Renderer*/GIMT_Encode2(2), GIMT_Encode2(GICP_gi_vop3mods),
        // (fmaxnum_ieee:{ *:[f32] } (fminnum:{ *:[f32] } (VOP3Mods:{ *:[f32] } f32:{ *:[f32] }:$src0, i32:{ *:[i32] }:$src0_mods), (VOP3Mods:{ *:[f32] } f32:{ *:[f32] }:$src1, i32:{ *:[i32] }:$src1_mods)), (fminnum:{ *:[f32] } (VOP3Mods:{ *:[f32] } f32:{ *:[f32] }:$src2, i32:{ *:[i32] }:$src2_mods), (fmaxnum_ieee:{ *:[f32] } (VOP3Mods:{ *:[f32] } f32:{ *:[f32] }:$src0, i32:{ *:[i32] }:$src0_mods), (VOP3Mods:{ *:[f32] } f32:{ *:[f32] }:$src1, i32:{ *:[i32] }:$src1_mods))))<<P:Predicate_fmaxnum_like_nnan>>  =>  (V_MED3_F32_e64:{ *:[f32] } ?:{ *:[i32] }:$src0_mods, ?:{ *:[f32] }:$src0, ?:{ *:[i32] }:$src1_mods, ?:{ *:[f32] }:$src1, ?:{ *:[i32] }:$src2_mods, ?:{ *:[f32] }:$src2, 0:{ *:[i1] }, 0:{ *:[i32] })
        GIR_BuildMI, /*InsnID*/0, /*Opcode*/GIMT_Encode2(AMDGPU::V_MED3_F32_e64),
        GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/0, // DstI[vdst]
        GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/1, // src0_mods
        GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/0, // src0
        GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(1), /*SubOperand*/1, // src1_mods
        GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(1), /*SubOperand*/0, // src1
        GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(2), /*SubOperand*/1, // src2_mods
        GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(2), /*SubOperand*/0, // src2
        GIR_AddImm8, /*InsnID*/0, /*Imm*/0,
        GIR_AddImm8, /*InsnID*/0, /*Imm*/0,
        GIR_ConstrainSelectedInstOperands, /*InsnID*/0,
        GIR_EraseFromParent, /*InsnID*/0,
        // GIR_Coverage, 10091,
        GIR_Done,
      // Label 5062: @366716
      GIM_Try, /*On fail goto*//*Label 5063*/ GIMT_Encode4(366856), // Rule ID 10092 //
        GIM_CheckRegBankForClass, /*MI*/0, /*Op*/0, /*RC*/GIMT_Encode2(AMDGPU::VGPR_32RegClassID),
        GIM_RecordInsn, /*DefineMI*/1, /*MI*/0, /*OpIdx*/1, // MIs[1]
        GIM_CheckOpcode, /*MI*/1, GIMT_Encode2(TargetOpcode::G_FMINNUM),
        GIM_CheckType, /*MI*/1, /*Op*/1, /*Type*/GILLT_s32,
        GIM_CheckType, /*MI*/1, /*Op*/2, /*Type*/GILLT_s32,
        GIM_RecordInsn, /*DefineMI*/2, /*MI*/0, /*OpIdx*/2, // MIs[2]
        GIM_CheckOpcode, /*MI*/2, GIMT_Encode2(TargetOpcode::G_FMINNUM),
        GIM_CheckType, /*MI*/2, /*Op*/1, /*Type*/GILLT_s32,
        GIM_CheckType, /*MI*/2, /*Op*/2, /*Type*/GILLT_s32,
        GIM_RecordInsn, /*DefineMI*/3, /*MI*/2, /*OpIdx*/2, // MIs[3]
        GIM_CheckOpcode, /*MI*/3, GIMT_Encode2(TargetOpcode::G_FMAXNUM_IEEE),
        // MIs[3] VOP3Mods:src1:src1_mods
        GIM_CheckIsSameOperand, /*MI*/3, /*OpIdx*/1, /*OtherMI*/1, /*OtherOpIdx*/2,
        // MIs[3] VOP3Mods:src0:src0_mods
        GIM_CheckIsSameOperand, /*MI*/3, /*OpIdx*/2, /*OtherMI*/1, /*OtherOpIdx*/1,
        GIM_CheckCxxInsnPredicate, /*MI*/0, /*FnId*/GIMT_Encode2(GICXXPred_MI_Predicate_fmaxnum_like_nnan),
        GIM_CheckIsSafeToFold, /*InsnID*/1,
        GIM_CheckIsSafeToFold, /*InsnID*/2,
        GIM_CheckIsSafeToFold, /*InsnID*/3,
        GIM_CheckComplexPattern, /*MI*/1, /*Op*/1, /*Renderer*/GIMT_Encode2(0), GIMT_Encode2(GICP_gi_vop3mods),
        GIM_CheckComplexPattern, /*MI*/1, /*Op*/2, /*Renderer*/GIMT_Encode2(1), GIMT_Encode2(GICP_gi_vop3mods),
        GIM_CheckComplexPattern, /*MI*/2, /*Op*/1, /*Renderer*/GIMT_Encode2(2), GIMT_Encode2(GICP_gi_vop3mods),
        // (fmaxnum_ieee:{ *:[f32] } (fminnum:{ *:[f32] } (VOP3Mods:{ *:[f32] } f32:{ *:[f32] }:$src0, i32:{ *:[i32] }:$src0_mods), (VOP3Mods:{ *:[f32] } f32:{ *:[f32] }:$src1, i32:{ *:[i32] }:$src1_mods)), (fminnum:{ *:[f32] } (VOP3Mods:{ *:[f32] } f32:{ *:[f32] }:$src2, i32:{ *:[i32] }:$src2_mods), (fmaxnum_ieee:{ *:[f32] } (VOP3Mods:{ *:[f32] } f32:{ *:[f32] }:$src1, i32:{ *:[i32] }:$src1_mods), (VOP3Mods:{ *:[f32] } f32:{ *:[f32] }:$src0, i32:{ *:[i32] }:$src0_mods))))<<P:Predicate_fmaxnum_like_nnan>>  =>  (V_MED3_F32_e64:{ *:[f32] } ?:{ *:[i32] }:$src0_mods, ?:{ *:[f32] }:$src0, ?:{ *:[i32] }:$src1_mods, ?:{ *:[f32] }:$src1, ?:{ *:[i32] }:$src2_mods, ?:{ *:[f32] }:$src2, 0:{ *:[i1] }, 0:{ *:[i32] })
        GIR_BuildMI, /*InsnID*/0, /*Opcode*/GIMT_Encode2(AMDGPU::V_MED3_F32_e64),
        GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/0, // DstI[vdst]
        GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/1, // src0_mods
        GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/0, // src0
        GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(1), /*SubOperand*/1, // src1_mods
        GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(1), /*SubOperand*/0, // src1
        GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(2), /*SubOperand*/1, // src2_mods
        GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(2), /*SubOperand*/0, // src2
        GIR_AddImm8, /*InsnID*/0, /*Imm*/0,
        GIR_AddImm8, /*InsnID*/0, /*Imm*/0,
        GIR_ConstrainSelectedInstOperands, /*InsnID*/0,
        GIR_EraseFromParent, /*InsnID*/0,
        // GIR_Coverage, 10092,
        GIR_Done,
      // Label 5063: @366856
      GIM_Try, /*On fail goto*//*Label 5064*/ GIMT_Encode4(366996), // Rule ID 10095 //
        GIM_CheckRegBankForClass, /*MI*/0, /*Op*/0, /*RC*/GIMT_Encode2(AMDGPU::VGPR_32RegClassID),
        GIM_RecordInsn, /*DefineMI*/1, /*MI*/0, /*OpIdx*/1, // MIs[1]
        GIM_CheckOpcode, /*MI*/1, GIMT_Encode2(TargetOpcode::G_FMINNUM),
        GIM_CheckType, /*MI*/1, /*Op*/1, /*Type*/GILLT_s32,
        GIM_CheckType, /*MI*/1, /*Op*/2, /*Type*/GILLT_s32,
        GIM_RecordInsn, /*DefineMI*/2, /*MI*/0, /*OpIdx*/2, // MIs[2]
        GIM_CheckOpcode, /*MI*/2, GIMT_Encode2(TargetOpcode::G_FMINNUM),
        GIM_CheckType, /*MI*/2, /*Op*/1, /*Type*/GILLT_s32,
        GIM_CheckType, /*MI*/2, /*Op*/2, /*Type*/GILLT_s32,
        GIM_RecordInsn, /*DefineMI*/3, /*MI*/2, /*OpIdx*/2, // MIs[3]
        GIM_CheckOpcode, /*MI*/3, GIMT_Encode2(TargetOpcode::G_FMAXNUM_IEEE),
        // MIs[3] VOP3Mods:src0:src0_mods
        GIM_CheckIsSameOperand, /*MI*/3, /*OpIdx*/1, /*OtherMI*/1, /*OtherOpIdx*/2,
        // MIs[3] VOP3Mods:src1:src1_mods
        GIM_CheckIsSameOperand, /*MI*/3, /*OpIdx*/2, /*OtherMI*/1, /*OtherOpIdx*/1,
        GIM_CheckCxxInsnPredicate, /*MI*/0, /*FnId*/GIMT_Encode2(GICXXPred_MI_Predicate_fmaxnum_like_nnan),
        GIM_CheckIsSafeToFold, /*InsnID*/1,
        GIM_CheckIsSafeToFold, /*InsnID*/2,
        GIM_CheckIsSafeToFold, /*InsnID*/3,
        GIM_CheckComplexPattern, /*MI*/1, /*Op*/1, /*Renderer*/GIMT_Encode2(0), GIMT_Encode2(GICP_gi_vop3mods),
        GIM_CheckComplexPattern, /*MI*/1, /*Op*/2, /*Renderer*/GIMT_Encode2(1), GIMT_Encode2(GICP_gi_vop3mods),
        GIM_CheckComplexPattern, /*MI*/2, /*Op*/1, /*Renderer*/GIMT_Encode2(2), GIMT_Encode2(GICP_gi_vop3mods),
        // (fmaxnum_ieee:{ *:[f32] } (fminnum:{ *:[f32] } (VOP3Mods:{ *:[f32] } f32:{ *:[f32] }:$src1, i32:{ *:[i32] }:$src1_mods), (VOP3Mods:{ *:[f32] } f32:{ *:[f32] }:$src0, i32:{ *:[i32] }:$src0_mods)), (fminnum:{ *:[f32] } (VOP3Mods:{ *:[f32] } f32:{ *:[f32] }:$src2, i32:{ *:[i32] }:$src2_mods), (fmaxnum_ieee:{ *:[f32] } (VOP3Mods:{ *:[f32] } f32:{ *:[f32] }:$src0, i32:{ *:[i32] }:$src0_mods), (VOP3Mods:{ *:[f32] } f32:{ *:[f32] }:$src1, i32:{ *:[i32] }:$src1_mods))))<<P:Predicate_fmaxnum_like_nnan>>  =>  (V_MED3_F32_e64:{ *:[f32] } ?:{ *:[i32] }:$src0_mods, ?:{ *:[f32] }:$src0, ?:{ *:[i32] }:$src1_mods, ?:{ *:[f32] }:$src1, ?:{ *:[i32] }:$src2_mods, ?:{ *:[f32] }:$src2, 0:{ *:[i1] }, 0:{ *:[i32] })
        GIR_BuildMI, /*InsnID*/0, /*Opcode*/GIMT_Encode2(AMDGPU::V_MED3_F32_e64),
        GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/0, // DstI[vdst]
        GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(1), /*SubOperand*/1, // src0_mods
        GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(1), /*SubOperand*/0, // src0
        GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/1, // src1_mods
        GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/0, // src1
        GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(2), /*SubOperand*/1, // src2_mods
        GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(2), /*SubOperand*/0, // src2
        GIR_AddImm8, /*InsnID*/0, /*Imm*/0,
        GIR_AddImm8, /*InsnID*/0, /*Imm*/0,
        GIR_ConstrainSelectedInstOperands, /*InsnID*/0,
        GIR_EraseFromParent, /*InsnID*/0,
        // GIR_Coverage, 10095,
        GIR_Done,
      // Label 5064: @366996
      GIM_Try, /*On fail goto*//*Label 5065*/ GIMT_Encode4(367136), // Rule ID 10096 //
        GIM_CheckRegBankForClass, /*MI*/0, /*Op*/0, /*RC*/GIMT_Encode2(AMDGPU::VGPR_32RegClassID),
        GIM_RecordInsn, /*DefineMI*/1, /*MI*/0, /*OpIdx*/1, // MIs[1]
        GIM_CheckOpcode, /*MI*/1, GIMT_Encode2(TargetOpcode::G_FMINNUM),
        GIM_CheckType, /*MI*/1, /*Op*/1, /*Type*/GILLT_s32,
        GIM_CheckType, /*MI*/1, /*Op*/2, /*Type*/GILLT_s32,
        GIM_RecordInsn, /*DefineMI*/2, /*MI*/0, /*OpIdx*/2, // MIs[2]
        GIM_CheckOpcode, /*MI*/2, GIMT_Encode2(TargetOpcode::G_FMINNUM),
        GIM_CheckType, /*MI*/2, /*Op*/1, /*Type*/GILLT_s32,
        GIM_CheckType, /*MI*/2, /*Op*/2, /*Type*/GILLT_s32,
        GIM_RecordInsn, /*DefineMI*/3, /*MI*/2, /*OpIdx*/2, // MIs[3]
        GIM_CheckOpcode, /*MI*/3, GIMT_Encode2(TargetOpcode::G_FMAXNUM_IEEE),
        // MIs[3] VOP3Mods:src1:src1_mods
        GIM_CheckIsSameOperand, /*MI*/3, /*OpIdx*/1, /*OtherMI*/1, /*OtherOpIdx*/1,
        // MIs[3] VOP3Mods:src0:src0_mods
        GIM_CheckIsSameOperand, /*MI*/3, /*OpIdx*/2, /*OtherMI*/1, /*OtherOpIdx*/2,
        GIM_CheckCxxInsnPredicate, /*MI*/0, /*FnId*/GIMT_Encode2(GICXXPred_MI_Predicate_fmaxnum_like_nnan),
        GIM_CheckIsSafeToFold, /*InsnID*/1,
        GIM_CheckIsSafeToFold, /*InsnID*/2,
        GIM_CheckIsSafeToFold, /*InsnID*/3,
        GIM_CheckComplexPattern, /*MI*/1, /*Op*/1, /*Renderer*/GIMT_Encode2(0), GIMT_Encode2(GICP_gi_vop3mods),
        GIM_CheckComplexPattern, /*MI*/1, /*Op*/2, /*Renderer*/GIMT_Encode2(1), GIMT_Encode2(GICP_gi_vop3mods),
        GIM_CheckComplexPattern, /*MI*/2, /*Op*/1, /*Renderer*/GIMT_Encode2(2), GIMT_Encode2(GICP_gi_vop3mods),
        // (fmaxnum_ieee:{ *:[f32] } (fminnum:{ *:[f32] } (VOP3Mods:{ *:[f32] } f32:{ *:[f32] }:$src1, i32:{ *:[i32] }:$src1_mods), (VOP3Mods:{ *:[f32] } f32:{ *:[f32] }:$src0, i32:{ *:[i32] }:$src0_mods)), (fminnum:{ *:[f32] } (VOP3Mods:{ *:[f32] } f32:{ *:[f32] }:$src2, i32:{ *:[i32] }:$src2_mods), (fmaxnum_ieee:{ *:[f32] } (VOP3Mods:{ *:[f32] } f32:{ *:[f32] }:$src1, i32:{ *:[i32] }:$src1_mods), (VOP3Mods:{ *:[f32] } f32:{ *:[f32] }:$src0, i32:{ *:[i32] }:$src0_mods))))<<P:Predicate_fmaxnum_like_nnan>>  =>  (V_MED3_F32_e64:{ *:[f32] } ?:{ *:[i32] }:$src0_mods, ?:{ *:[f32] }:$src0, ?:{ *:[i32] }:$src1_mods, ?:{ *:[f32] }:$src1, ?:{ *:[i32] }:$src2_mods, ?:{ *:[f32] }:$src2, 0:{ *:[i1] }, 0:{ *:[i32] })
        GIR_BuildMI, /*InsnID*/0, /*Opcode*/GIMT_Encode2(AMDGPU::V_MED3_F32_e64),
        GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/0, // DstI[vdst]
        GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(1), /*SubOperand*/1, // src0_mods
        GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(1), /*SubOperand*/0, // src0
        GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/1, // src1_mods
        GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/0, // src1
        GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(2), /*SubOperand*/1, // src2_mods
        GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(2), /*SubOperand*/0, // src2
        GIR_AddImm8, /*InsnID*/0, /*Imm*/0,
        GIR_AddImm8, /*InsnID*/0, /*Imm*/0,
        GIR_ConstrainSelectedInstOperands, /*InsnID*/0,
        GIR_EraseFromParent, /*InsnID*/0,
        // GIR_Coverage, 10096,
        GIR_Done,
      // Label 5065: @367136
      GIM_Try, /*On fail goto*//*Label 5066*/ GIMT_Encode4(367276), // Rule ID 6489 //
        GIM_CheckRegBankForClass, /*MI*/0, /*Op*/0, /*RC*/GIMT_Encode2(AMDGPU::VGPR_32RegClassID),
        GIM_RecordInsn, /*DefineMI*/1, /*MI*/0, /*OpIdx*/1, // MIs[1]
        GIM_CheckOpcode, /*MI*/1, GIMT_Encode2(TargetOpcode::G_FMINNUM),
        GIM_CheckType, /*MI*/1, /*Op*/1, /*Type*/GILLT_s32,
        GIM_CheckType, /*MI*/1, /*Op*/2, /*Type*/GILLT_s32,
        GIM_RecordInsn, /*DefineMI*/2, /*MI*/0, /*OpIdx*/2, // MIs[2]
        GIM_CheckOpcode, /*MI*/2, GIMT_Encode2(TargetOpcode::G_FMINNUM),
        GIM_CheckType, /*MI*/2, /*Op*/1, /*Type*/GILLT_s32,
        GIM_CheckType, /*MI*/2, /*Op*/2, /*Type*/GILLT_s32,
        GIM_RecordInsn, /*DefineMI*/3, /*MI*/2, /*OpIdx*/1, // MIs[3]
        GIM_CheckOpcode, /*MI*/3, GIMT_Encode2(TargetOpcode::G_FMAXNUM),
        // MIs[3] VOP3Mods:src0:src0_mods
        GIM_CheckIsSameOperand, /*MI*/3, /*OpIdx*/1, /*OtherMI*/1, /*OtherOpIdx*/1,
        // MIs[3] VOP3Mods:src1:src1_mods
        GIM_CheckIsSameOperand, /*MI*/3, /*OpIdx*/2, /*OtherMI*/1, /*OtherOpIdx*/2,
        GIM_CheckCxxInsnPredicate, /*MI*/0, /*FnId*/GIMT_Encode2(GICXXPred_MI_Predicate_fmaxnum_like_nnan),
        GIM_CheckIsSafeToFold, /*InsnID*/1,
        GIM_CheckIsSafeToFold, /*InsnID*/2,
        GIM_CheckIsSafeToFold, /*InsnID*/3,
        GIM_CheckComplexPattern, /*MI*/1, /*Op*/1, /*Renderer*/GIMT_Encode2(0), GIMT_Encode2(GICP_gi_vop3mods),
        GIM_CheckComplexPattern, /*MI*/1, /*Op*/2, /*Renderer*/GIMT_Encode2(1), GIMT_Encode2(GICP_gi_vop3mods),
        GIM_CheckComplexPattern, /*MI*/2, /*Op*/2, /*Renderer*/GIMT_Encode2(2), GIMT_Encode2(GICP_gi_vop3mods),
        // (fmaxnum_ieee:{ *:[f32] } (fminnum:{ *:[f32] } (VOP3Mods:{ *:[f32] } f32:{ *:[f32] }:$src0, i32:{ *:[i32] }:$src0_mods), (VOP3Mods:{ *:[f32] } f32:{ *:[f32] }:$src1, i32:{ *:[i32] }:$src1_mods)), (fminnum:{ *:[f32] } (fmaxnum:{ *:[f32] } (VOP3Mods:{ *:[f32] } f32:{ *:[f32] }:$src0, i32:{ *:[i32] }:$src0_mods), (VOP3Mods:{ *:[f32] } f32:{ *:[f32] }:$src1, i32:{ *:[i32] }:$src1_mods)), (VOP3Mods:{ *:[f32] } f32:{ *:[f32] }:$src2, i32:{ *:[i32] }:$src2_mods)))<<P:Predicate_fmaxnum_like_nnan>>  =>  (V_MED3_F32_e64:{ *:[f32] } ?:{ *:[i32] }:$src0_mods, ?:{ *:[f32] }:$src0, ?:{ *:[i32] }:$src1_mods, ?:{ *:[f32] }:$src1, ?:{ *:[i32] }:$src2_mods, ?:{ *:[f32] }:$src2, 0:{ *:[i1] }, 0:{ *:[i32] })
        GIR_BuildMI, /*InsnID*/0, /*Opcode*/GIMT_Encode2(AMDGPU::V_MED3_F32_e64),
        GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/0, // DstI[vdst]
        GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/1, // src0_mods
        GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/0, // src0
        GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(1), /*SubOperand*/1, // src1_mods
        GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(1), /*SubOperand*/0, // src1
        GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(2), /*SubOperand*/1, // src2_mods
        GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(2), /*SubOperand*/0, // src2
        GIR_AddImm8, /*InsnID*/0, /*Imm*/0,
        GIR_AddImm8, /*InsnID*/0, /*Imm*/0,
        GIR_ConstrainSelectedInstOperands, /*InsnID*/0,
        GIR_EraseFromParent, /*InsnID*/0,
        // GIR_Coverage, 6489,
        GIR_Done,
      // Label 5066: @367276
      GIM_Try, /*On fail goto*//*Label 5067*/ GIMT_Encode4(367416), // Rule ID 10105 //
        GIM_CheckRegBankForClass, /*MI*/0, /*Op*/0, /*RC*/GIMT_Encode2(AMDGPU::VGPR_32RegClassID),
        GIM_RecordInsn, /*DefineMI*/1, /*MI*/0, /*OpIdx*/1, // MIs[1]
        GIM_CheckOpcode, /*MI*/1, GIMT_Encode2(TargetOpcode::G_FMINNUM),
        GIM_CheckType, /*MI*/1, /*Op*/1, /*Type*/GILLT_s32,
        GIM_CheckType, /*MI*/1, /*Op*/2, /*Type*/GILLT_s32,
        GIM_RecordInsn, /*DefineMI*/2, /*MI*/0, /*OpIdx*/2, // MIs[2]
        GIM_CheckOpcode, /*MI*/2, GIMT_Encode2(TargetOpcode::G_FMINNUM),
        GIM_CheckType, /*MI*/2, /*Op*/1, /*Type*/GILLT_s32,
        GIM_CheckType, /*MI*/2, /*Op*/2, /*Type*/GILLT_s32,
        GIM_RecordInsn, /*DefineMI*/3, /*MI*/2, /*OpIdx*/1, // MIs[3]
        GIM_CheckOpcode, /*MI*/3, GIMT_Encode2(TargetOpcode::G_FMAXNUM),
        // MIs[3] VOP3Mods:src1:src1_mods
        GIM_CheckIsSameOperand, /*MI*/3, /*OpIdx*/1, /*OtherMI*/1, /*OtherOpIdx*/2,
        // MIs[3] VOP3Mods:src0:src0_mods
        GIM_CheckIsSameOperand, /*MI*/3, /*OpIdx*/2, /*OtherMI*/1, /*OtherOpIdx*/1,
        GIM_CheckCxxInsnPredicate, /*MI*/0, /*FnId*/GIMT_Encode2(GICXXPred_MI_Predicate_fmaxnum_like_nnan),
        GIM_CheckIsSafeToFold, /*InsnID*/1,
        GIM_CheckIsSafeToFold, /*InsnID*/2,
        GIM_CheckIsSafeToFold, /*InsnID*/3,
        GIM_CheckComplexPattern, /*MI*/1, /*Op*/1, /*Renderer*/GIMT_Encode2(0), GIMT_Encode2(GICP_gi_vop3mods),
        GIM_CheckComplexPattern, /*MI*/1, /*Op*/2, /*Renderer*/GIMT_Encode2(1), GIMT_Encode2(GICP_gi_vop3mods),
        GIM_CheckComplexPattern, /*MI*/2, /*Op*/2, /*Renderer*/GIMT_Encode2(2), GIMT_Encode2(GICP_gi_vop3mods),
        // (fmaxnum_ieee:{ *:[f32] } (fminnum:{ *:[f32] } (VOP3Mods:{ *:[f32] } f32:{ *:[f32] }:$src0, i32:{ *:[i32] }:$src0_mods), (VOP3Mods:{ *:[f32] } f32:{ *:[f32] }:$src1, i32:{ *:[i32] }:$src1_mods)), (fminnum:{ *:[f32] } (fmaxnum:{ *:[f32] } (VOP3Mods:{ *:[f32] } f32:{ *:[f32] }:$src1, i32:{ *:[i32] }:$src1_mods), (VOP3Mods:{ *:[f32] } f32:{ *:[f32] }:$src0, i32:{ *:[i32] }:$src0_mods)), (VOP3Mods:{ *:[f32] } f32:{ *:[f32] }:$src2, i32:{ *:[i32] }:$src2_mods)))<<P:Predicate_fmaxnum_like_nnan>>  =>  (V_MED3_F32_e64:{ *:[f32] } ?:{ *:[i32] }:$src0_mods, ?:{ *:[f32] }:$src0, ?:{ *:[i32] }:$src1_mods, ?:{ *:[f32] }:$src1, ?:{ *:[i32] }:$src2_mods, ?:{ *:[f32] }:$src2, 0:{ *:[i1] }, 0:{ *:[i32] })
        GIR_BuildMI, /*InsnID*/0, /*Opcode*/GIMT_Encode2(AMDGPU::V_MED3_F32_e64),
        GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/0, // DstI[vdst]
        GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/1, // src0_mods
        GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/0, // src0
        GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(1), /*SubOperand*/1, // src1_mods
        GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(1), /*SubOperand*/0, // src1
        GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(2), /*SubOperand*/1, // src2_mods
        GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(2), /*SubOperand*/0, // src2
        GIR_AddImm8, /*InsnID*/0, /*Imm*/0,
        GIR_AddImm8, /*InsnID*/0, /*Imm*/0,
        GIR_ConstrainSelectedInstOperands, /*InsnID*/0,
        GIR_EraseFromParent, /*InsnID*/0,
        // GIR_Coverage, 10105,
        GIR_Done,
      // Label 5067: @367416
      GIM_Try, /*On fail goto*//*Label 5068*/ GIMT_Encode4(367556), // Rule ID 10108 //
        GIM_CheckRegBankForClass, /*MI*/0, /*Op*/0, /*RC*/GIMT_Encode2(AMDGPU::VGPR_32RegClassID),
        GIM_RecordInsn, /*DefineMI*/1, /*MI*/0, /*OpIdx*/1, // MIs[1]
        GIM_CheckOpcode, /*MI*/1, GIMT_Encode2(TargetOpcode::G_FMINNUM),
        GIM_CheckType, /*MI*/1, /*Op*/1, /*Type*/GILLT_s32,
        GIM_CheckType, /*MI*/1, /*Op*/2, /*Type*/GILLT_s32,
        GIM_RecordInsn, /*DefineMI*/2, /*MI*/0, /*OpIdx*/2, // MIs[2]
        GIM_CheckOpcode, /*MI*/2, GIMT_Encode2(TargetOpcode::G_FMINNUM),
        GIM_CheckType, /*MI*/2, /*Op*/1, /*Type*/GILLT_s32,
        GIM_CheckType, /*MI*/2, /*Op*/2, /*Type*/GILLT_s32,
        GIM_RecordInsn, /*DefineMI*/3, /*MI*/2, /*OpIdx*/1, // MIs[3]
        GIM_CheckOpcode, /*MI*/3, GIMT_Encode2(TargetOpcode::G_FMAXNUM),
        // MIs[3] VOP3Mods:src0:src0_mods
        GIM_CheckIsSameOperand, /*MI*/3, /*OpIdx*/1, /*OtherMI*/1, /*OtherOpIdx*/2,
        // MIs[3] VOP3Mods:src1:src1_mods
        GIM_CheckIsSameOperand, /*MI*/3, /*OpIdx*/2, /*OtherMI*/1, /*OtherOpIdx*/1,
        GIM_CheckCxxInsnPredicate, /*MI*/0, /*FnId*/GIMT_Encode2(GICXXPred_MI_Predicate_fmaxnum_like_nnan),
        GIM_CheckIsSafeToFold, /*InsnID*/1,
        GIM_CheckIsSafeToFold, /*InsnID*/2,
        GIM_CheckIsSafeToFold, /*InsnID*/3,
        GIM_CheckComplexPattern, /*MI*/1, /*Op*/1, /*Renderer*/GIMT_Encode2(0), GIMT_Encode2(GICP_gi_vop3mods),
        GIM_CheckComplexPattern, /*MI*/1, /*Op*/2, /*Renderer*/GIMT_Encode2(1), GIMT_Encode2(GICP_gi_vop3mods),
        GIM_CheckComplexPattern, /*MI*/2, /*Op*/2, /*Renderer*/GIMT_Encode2(2), GIMT_Encode2(GICP_gi_vop3mods),
        // (fmaxnum_ieee:{ *:[f32] } (fminnum:{ *:[f32] } (VOP3Mods:{ *:[f32] } f32:{ *:[f32] }:$src1, i32:{ *:[i32] }:$src1_mods), (VOP3Mods:{ *:[f32] } f32:{ *:[f32] }:$src0, i32:{ *:[i32] }:$src0_mods)), (fminnum:{ *:[f32] } (fmaxnum:{ *:[f32] } (VOP3Mods:{ *:[f32] } f32:{ *:[f32] }:$src0, i32:{ *:[i32] }:$src0_mods), (VOP3Mods:{ *:[f32] } f32:{ *:[f32] }:$src1, i32:{ *:[i32] }:$src1_mods)), (VOP3Mods:{ *:[f32] } f32:{ *:[f32] }:$src2, i32:{ *:[i32] }:$src2_mods)))<<P:Predicate_fmaxnum_like_nnan>>  =>  (V_MED3_F32_e64:{ *:[f32] } ?:{ *:[i32] }:$src0_mods, ?:{ *:[f32] }:$src0, ?:{ *:[i32] }:$src1_mods, ?:{ *:[f32] }:$src1, ?:{ *:[i32] }:$src2_mods, ?:{ *:[f32] }:$src2, 0:{ *:[i1] }, 0:{ *:[i32] })
        GIR_BuildMI, /*InsnID*/0, /*Opcode*/GIMT_Encode2(AMDGPU::V_MED3_F32_e64),
        GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/0, // DstI[vdst]
        GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(1), /*SubOperand*/1, // src0_mods
        GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(1), /*SubOperand*/0, // src0
        GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/1, // src1_mods
        GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/0, // src1
        GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(2), /*SubOperand*/1, // src2_mods
        GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(2), /*SubOperand*/0, // src2
        GIR_AddImm8, /*InsnID*/0, /*Imm*/0,
        GIR_AddImm8, /*InsnID*/0, /*Imm*/0,
        GIR_ConstrainSelectedInstOperands, /*InsnID*/0,
        GIR_EraseFromParent, /*InsnID*/0,
        // GIR_Coverage, 10108,
        GIR_Done,
      // Label 5068: @367556
      GIM_Try, /*On fail goto*//*Label 5069*/ GIMT_Encode4(367696), // Rule ID 10109 //
        GIM_CheckRegBankForClass, /*MI*/0, /*Op*/0, /*RC*/GIMT_Encode2(AMDGPU::VGPR_32RegClassID),
        GIM_RecordInsn, /*DefineMI*/1, /*MI*/0, /*OpIdx*/1, // MIs[1]
        GIM_CheckOpcode, /*MI*/1, GIMT_Encode2(TargetOpcode::G_FMINNUM),
        GIM_CheckType, /*MI*/1, /*Op*/1, /*Type*/GILLT_s32,
        GIM_CheckType, /*MI*/1, /*Op*/2, /*Type*/GILLT_s32,
        GIM_RecordInsn, /*DefineMI*/2, /*MI*/0, /*OpIdx*/2, // MIs[2]
        GIM_CheckOpcode, /*MI*/2, GIMT_Encode2(TargetOpcode::G_FMINNUM),
        GIM_CheckType, /*MI*/2, /*Op*/1, /*Type*/GILLT_s32,
        GIM_CheckType, /*MI*/2, /*Op*/2, /*Type*/GILLT_s32,
        GIM_RecordInsn, /*DefineMI*/3, /*MI*/2, /*OpIdx*/1, // MIs[3]
        GIM_CheckOpcode, /*MI*/3, GIMT_Encode2(TargetOpcode::G_FMAXNUM),
        // MIs[3] VOP3Mods:src1:src1_mods
        GIM_CheckIsSameOperand, /*MI*/3, /*OpIdx*/1, /*OtherMI*/1, /*OtherOpIdx*/1,
        // MIs[3] VOP3Mods:src0:src0_mods
        GIM_CheckIsSameOperand, /*MI*/3, /*OpIdx*/2, /*OtherMI*/1, /*OtherOpIdx*/2,
        GIM_CheckCxxInsnPredicate, /*MI*/0, /*FnId*/GIMT_Encode2(GICXXPred_MI_Predicate_fmaxnum_like_nnan),
        GIM_CheckIsSafeToFold, /*InsnID*/1,
        GIM_CheckIsSafeToFold, /*InsnID*/2,
        GIM_CheckIsSafeToFold, /*InsnID*/3,
        GIM_CheckComplexPattern, /*MI*/1, /*Op*/1, /*Renderer*/GIMT_Encode2(0), GIMT_Encode2(GICP_gi_vop3mods),
        GIM_CheckComplexPattern, /*MI*/1, /*Op*/2, /*Renderer*/GIMT_Encode2(1), GIMT_Encode2(GICP_gi_vop3mods),
        GIM_CheckComplexPattern, /*MI*/2, /*Op*/2, /*Renderer*/GIMT_Encode2(2), GIMT_Encode2(GICP_gi_vop3mods),
        // (fmaxnum_ieee:{ *:[f32] } (fminnum:{ *:[f32] } (VOP3Mods:{ *:[f32] } f32:{ *:[f32] }:$src1, i32:{ *:[i32] }:$src1_mods), (VOP3Mods:{ *:[f32] } f32:{ *:[f32] }:$src0, i32:{ *:[i32] }:$src0_mods)), (fminnum:{ *:[f32] } (fmaxnum:{ *:[f32] } (VOP3Mods:{ *:[f32] } f32:{ *:[f32] }:$src1, i32:{ *:[i32] }:$src1_mods), (VOP3Mods:{ *:[f32] } f32:{ *:[f32] }:$src0, i32:{ *:[i32] }:$src0_mods)), (VOP3Mods:{ *:[f32] } f32:{ *:[f32] }:$src2, i32:{ *:[i32] }:$src2_mods)))<<P:Predicate_fmaxnum_like_nnan>>  =>  (V_MED3_F32_e64:{ *:[f32] } ?:{ *:[i32] }:$src0_mods, ?:{ *:[f32] }:$src0, ?:{ *:[i32] }:$src1_mods, ?:{ *:[f32] }:$src1, ?:{ *:[i32] }:$src2_mods, ?:{ *:[f32] }:$src2, 0:{ *:[i1] }, 0:{ *:[i32] })
        GIR_BuildMI, /*InsnID*/0, /*Opcode*/GIMT_Encode2(AMDGPU::V_MED3_F32_e64),
        GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/0, // DstI[vdst]
        GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(1), /*SubOperand*/1, // src0_mods
        GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(1), /*SubOperand*/0, // src0
        GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/1, // src1_mods
        GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/0, // src1
        GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(2), /*SubOperand*/1, // src2_mods
        GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(2), /*SubOperand*/0, // src2
        GIR_AddImm8, /*InsnID*/0, /*Imm*/0,
        GIR_AddImm8, /*InsnID*/0, /*Imm*/0,
        GIR_ConstrainSelectedInstOperands, /*InsnID*/0,
        GIR_EraseFromParent, /*InsnID*/0,
        // GIR_Coverage, 10109,
        GIR_Done,
      // Label 5069: @367696
      GIM_Try, /*On fail goto*//*Label 5070*/ GIMT_Encode4(367836), // Rule ID 6488 //
        GIM_CheckRegBankForClass, /*MI*/0, /*Op*/0, /*RC*/GIMT_Encode2(AMDGPU::VGPR_32RegClassID),
        GIM_RecordInsn, /*DefineMI*/1, /*MI*/0, /*OpIdx*/1, // MIs[1]
        GIM_CheckOpcode, /*MI*/1, GIMT_Encode2(TargetOpcode::G_FMINNUM),
        GIM_CheckType, /*MI*/1, /*Op*/1, /*Type*/GILLT_s32,
        GIM_CheckType, /*MI*/1, /*Op*/2, /*Type*/GILLT_s32,
        GIM_RecordInsn, /*DefineMI*/2, /*MI*/0, /*OpIdx*/2, // MIs[2]
        GIM_CheckOpcode, /*MI*/2, GIMT_Encode2(TargetOpcode::G_FMINNUM),
        GIM_CheckType, /*MI*/2, /*Op*/1, /*Type*/GILLT_s32,
        GIM_CheckType, /*MI*/2, /*Op*/2, /*Type*/GILLT_s32,
        GIM_RecordInsn, /*DefineMI*/3, /*MI*/2, /*OpIdx*/1, // MIs[3]
        GIM_CheckOpcode, /*MI*/3, GIMT_Encode2(TargetOpcode::G_FMAXNUM_IEEE),
        // MIs[3] VOP3Mods:src0:src0_mods
        GIM_CheckIsSameOperand, /*MI*/3, /*OpIdx*/1, /*OtherMI*/1, /*OtherOpIdx*/1,
        // MIs[3] VOP3Mods:src1:src1_mods
        GIM_CheckIsSameOperand, /*MI*/3, /*OpIdx*/2, /*OtherMI*/1, /*OtherOpIdx*/2,
        GIM_CheckCxxInsnPredicate, /*MI*/0, /*FnId*/GIMT_Encode2(GICXXPred_MI_Predicate_fmaxnum_like_nnan),
        GIM_CheckIsSafeToFold, /*InsnID*/1,
        GIM_CheckIsSafeToFold, /*InsnID*/2,
        GIM_CheckIsSafeToFold, /*InsnID*/3,
        GIM_CheckComplexPattern, /*MI*/1, /*Op*/1, /*Renderer*/GIMT_Encode2(0), GIMT_Encode2(GICP_gi_vop3mods),
        GIM_CheckComplexPattern, /*MI*/1, /*Op*/2, /*Renderer*/GIMT_Encode2(1), GIMT_Encode2(GICP_gi_vop3mods),
        GIM_CheckComplexPattern, /*MI*/2, /*Op*/2, /*Renderer*/GIMT_Encode2(2), GIMT_Encode2(GICP_gi_vop3mods),
        // (fmaxnum_ieee:{ *:[f32] } (fminnum:{ *:[f32] } (VOP3Mods:{ *:[f32] } f32:{ *:[f32] }:$src0, i32:{ *:[i32] }:$src0_mods), (VOP3Mods:{ *:[f32] } f32:{ *:[f32] }:$src1, i32:{ *:[i32] }:$src1_mods)), (fminnum:{ *:[f32] } (fmaxnum_ieee:{ *:[f32] } (VOP3Mods:{ *:[f32] } f32:{ *:[f32] }:$src0, i32:{ *:[i32] }:$src0_mods), (VOP3Mods:{ *:[f32] } f32:{ *:[f32] }:$src1, i32:{ *:[i32] }:$src1_mods)), (VOP3Mods:{ *:[f32] } f32:{ *:[f32] }:$src2, i32:{ *:[i32] }:$src2_mods)))<<P:Predicate_fmaxnum_like_nnan>>  =>  (V_MED3_F32_e64:{ *:[f32] } ?:{ *:[i32] }:$src0_mods, ?:{ *:[f32] }:$src0, ?:{ *:[i32] }:$src1_mods, ?:{ *:[f32] }:$src1, ?:{ *:[i32] }:$src2_mods, ?:{ *:[f32] }:$src2, 0:{ *:[i1] }, 0:{ *:[i32] })
        GIR_BuildMI, /*InsnID*/0, /*Opcode*/GIMT_Encode2(AMDGPU::V_MED3_F32_e64),
        GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/0, // DstI[vdst]
        GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/1, // src0_mods
        GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/0, // src0
        GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(1), /*SubOperand*/1, // src1_mods
        GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(1), /*SubOperand*/0, // src1
        GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(2), /*SubOperand*/1, // src2_mods
        GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(2), /*SubOperand*/0, // src2
        GIR_AddImm8, /*InsnID*/0, /*Imm*/0,
        GIR_AddImm8, /*InsnID*/0, /*Imm*/0,
        GIR_ConstrainSelectedInstOperands, /*InsnID*/0,
        GIR_EraseFromParent, /*InsnID*/0,
        // GIR_Coverage, 6488,
        GIR_Done,
      // Label 5070: @367836
      GIM_Try, /*On fail goto*//*Label 5071*/ GIMT_Encode4(367976), // Rule ID 10090 //
        GIM_CheckRegBankForClass, /*MI*/0, /*Op*/0, /*RC*/GIMT_Encode2(AMDGPU::VGPR_32RegClassID),
        GIM_RecordInsn, /*DefineMI*/1, /*MI*/0, /*OpIdx*/1, // MIs[1]
        GIM_CheckOpcode, /*MI*/1, GIMT_Encode2(TargetOpcode::G_FMINNUM),
        GIM_CheckType, /*MI*/1, /*Op*/1, /*Type*/GILLT_s32,
        GIM_CheckType, /*MI*/1, /*Op*/2, /*Type*/GILLT_s32,
        GIM_RecordInsn, /*DefineMI*/2, /*MI*/0, /*OpIdx*/2, // MIs[2]
        GIM_CheckOpcode, /*MI*/2, GIMT_Encode2(TargetOpcode::G_FMINNUM),
        GIM_CheckType, /*MI*/2, /*Op*/1, /*Type*/GILLT_s32,
        GIM_CheckType, /*MI*/2, /*Op*/2, /*Type*/GILLT_s32,
        GIM_RecordInsn, /*DefineMI*/3, /*MI*/2, /*OpIdx*/1, // MIs[3]
        GIM_CheckOpcode, /*MI*/3, GIMT_Encode2(TargetOpcode::G_FMAXNUM_IEEE),
        // MIs[3] VOP3Mods:src1:src1_mods
        GIM_CheckIsSameOperand, /*MI*/3, /*OpIdx*/1, /*OtherMI*/1, /*OtherOpIdx*/2,
        // MIs[3] VOP3Mods:src0:src0_mods
        GIM_CheckIsSameOperand, /*MI*/3, /*OpIdx*/2, /*OtherMI*/1, /*OtherOpIdx*/1,
        GIM_CheckCxxInsnPredicate, /*MI*/0, /*FnId*/GIMT_Encode2(GICXXPred_MI_Predicate_fmaxnum_like_nnan),
        GIM_CheckIsSafeToFold, /*InsnID*/1,
        GIM_CheckIsSafeToFold, /*InsnID*/2,
        GIM_CheckIsSafeToFold, /*InsnID*/3,
        GIM_CheckComplexPattern, /*MI*/1, /*Op*/1, /*Renderer*/GIMT_Encode2(0), GIMT_Encode2(GICP_gi_vop3mods),
        GIM_CheckComplexPattern, /*MI*/1, /*Op*/2, /*Renderer*/GIMT_Encode2(1), GIMT_Encode2(GICP_gi_vop3mods),
        GIM_CheckComplexPattern, /*MI*/2, /*Op*/2, /*Renderer*/GIMT_Encode2(2), GIMT_Encode2(GICP_gi_vop3mods),
        // (fmaxnum_ieee:{ *:[f32] } (fminnum:{ *:[f32] } (VOP3Mods:{ *:[f32] } f32:{ *:[f32] }:$src0, i32:{ *:[i32] }:$src0_mods), (VOP3Mods:{ *:[f32] } f32:{ *:[f32] }:$src1, i32:{ *:[i32] }:$src1_mods)), (fminnum:{ *:[f32] } (fmaxnum_ieee:{ *:[f32] } (VOP3Mods:{ *:[f32] } f32:{ *:[f32] }:$src1, i32:{ *:[i32] }:$src1_mods), (VOP3Mods:{ *:[f32] } f32:{ *:[f32] }:$src0, i32:{ *:[i32] }:$src0_mods)), (VOP3Mods:{ *:[f32] } f32:{ *:[f32] }:$src2, i32:{ *:[i32] }:$src2_mods)))<<P:Predicate_fmaxnum_like_nnan>>  =>  (V_MED3_F32_e64:{ *:[f32] } ?:{ *:[i32] }:$src0_mods, ?:{ *:[f32] }:$src0, ?:{ *:[i32] }:$src1_mods, ?:{ *:[f32] }:$src1, ?:{ *:[i32] }:$src2_mods, ?:{ *:[f32] }:$src2, 0:{ *:[i1] }, 0:{ *:[i32] })
        GIR_BuildMI, /*InsnID*/0, /*Opcode*/GIMT_Encode2(AMDGPU::V_MED3_F32_e64),
        GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/0, // DstI[vdst]
        GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/1, // src0_mods
        GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/0, // src0
        GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(1), /*SubOperand*/1, // src1_mods
        GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(1), /*SubOperand*/0, // src1
        GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(2), /*SubOperand*/1, // src2_mods
        GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(2), /*SubOperand*/0, // src2
        GIR_AddImm8, /*InsnID*/0, /*Imm*/0,
        GIR_AddImm8, /*InsnID*/0, /*Imm*/0,
        GIR_ConstrainSelectedInstOperands, /*InsnID*/0,
        GIR_EraseFromParent, /*InsnID*/0,
        // GIR_Coverage, 10090,
        GIR_Done,
      // Label 5071: @367976
      GIM_Try, /*On fail goto*//*Label 5072*/ GIMT_Encode4(368116), // Rule ID 10093 //
        GIM_CheckRegBankForClass, /*MI*/0, /*Op*/0, /*RC*/GIMT_Encode2(AMDGPU::VGPR_32RegClassID),
        GIM_RecordInsn, /*DefineMI*/1, /*MI*/0, /*OpIdx*/1, // MIs[1]
        GIM_CheckOpcode, /*MI*/1, GIMT_Encode2(TargetOpcode::G_FMINNUM),
        GIM_CheckType, /*MI*/1, /*Op*/1, /*Type*/GILLT_s32,
        GIM_CheckType, /*MI*/1, /*Op*/2, /*Type*/GILLT_s32,
        GIM_RecordInsn, /*DefineMI*/2, /*MI*/0, /*OpIdx*/2, // MIs[2]
        GIM_CheckOpcode, /*MI*/2, GIMT_Encode2(TargetOpcode::G_FMINNUM),
        GIM_CheckType, /*MI*/2, /*Op*/1, /*Type*/GILLT_s32,
        GIM_CheckType, /*MI*/2, /*Op*/2, /*Type*/GILLT_s32,
        GIM_RecordInsn, /*DefineMI*/3, /*MI*/2, /*OpIdx*/1, // MIs[3]
        GIM_CheckOpcode, /*MI*/3, GIMT_Encode2(TargetOpcode::G_FMAXNUM_IEEE),
        // MIs[3] VOP3Mods:src0:src0_mods
        GIM_CheckIsSameOperand, /*MI*/3, /*OpIdx*/1, /*OtherMI*/1, /*OtherOpIdx*/2,
        // MIs[3] VOP3Mods:src1:src1_mods
        GIM_CheckIsSameOperand, /*MI*/3, /*OpIdx*/2, /*OtherMI*/1, /*OtherOpIdx*/1,
        GIM_CheckCxxInsnPredicate, /*MI*/0, /*FnId*/GIMT_Encode2(GICXXPred_MI_Predicate_fmaxnum_like_nnan),
        GIM_CheckIsSafeToFold, /*InsnID*/1,
        GIM_CheckIsSafeToFold, /*InsnID*/2,
        GIM_CheckIsSafeToFold, /*InsnID*/3,
        GIM_CheckComplexPattern, /*MI*/1, /*Op*/1, /*Renderer*/GIMT_Encode2(0), GIMT_Encode2(GICP_gi_vop3mods),
        GIM_CheckComplexPattern, /*MI*/1, /*Op*/2, /*Renderer*/GIMT_Encode2(1), GIMT_Encode2(GICP_gi_vop3mods),
        GIM_CheckComplexPattern, /*MI*/2, /*Op*/2, /*Renderer*/GIMT_Encode2(2), GIMT_Encode2(GICP_gi_vop3mods),
        // (fmaxnum_ieee:{ *:[f32] } (fminnum:{ *:[f32] } (VOP3Mods:{ *:[f32] } f32:{ *:[f32] }:$src1, i32:{ *:[i32] }:$src1_mods), (VOP3Mods:{ *:[f32] } f32:{ *:[f32] }:$src0, i32:{ *:[i32] }:$src0_mods)), (fminnum:{ *:[f32] } (fmaxnum_ieee:{ *:[f32] } (VOP3Mods:{ *:[f32] } f32:{ *:[f32] }:$src0, i32:{ *:[i32] }:$src0_mods), (VOP3Mods:{ *:[f32] } f32:{ *:[f32] }:$src1, i32:{ *:[i32] }:$src1_mods)), (VOP3Mods:{ *:[f32] } f32:{ *:[f32] }:$src2, i32:{ *:[i32] }:$src2_mods)))<<P:Predicate_fmaxnum_like_nnan>>  =>  (V_MED3_F32_e64:{ *:[f32] } ?:{ *:[i32] }:$src0_mods, ?:{ *:[f32] }:$src0, ?:{ *:[i32] }:$src1_mods, ?:{ *:[f32] }:$src1, ?:{ *:[i32] }:$src2_mods, ?:{ *:[f32] }:$src2, 0:{ *:[i1] }, 0:{ *:[i32] })
        GIR_BuildMI, /*InsnID*/0, /*Opcode*/GIMT_Encode2(AMDGPU::V_MED3_F32_e64),
        GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/0, // DstI[vdst]
        GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(1), /*SubOperand*/1, // src0_mods
        GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(1), /*SubOperand*/0, // src0
        GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/1, // src1_mods
        GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/0, // src1
        GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(2), /*SubOperand*/1, // src2_mods
        GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(2), /*SubOperand*/0, // src2
        GIR_AddImm8, /*InsnID*/0, /*Imm*/0,
        GIR_AddImm8, /*InsnID*/0, /*Imm*/0,
        GIR_ConstrainSelectedInstOperands, /*InsnID*/0,
        GIR_EraseFromParent, /*InsnID*/0,
        // GIR_Coverage, 10093,
        GIR_Done,
      // Label 5072: @368116
      GIM_Try, /*On fail goto*//*Label 5073*/ GIMT_Encode4(368256), // Rule ID 10094 //
        GIM_CheckRegBankForClass, /*MI*/0, /*Op*/0, /*RC*/GIMT_Encode2(AMDGPU::VGPR_32RegClassID),
        GIM_RecordInsn, /*DefineMI*/1, /*MI*/0, /*OpIdx*/1, // MIs[1]
        GIM_CheckOpcode, /*MI*/1, GIMT_Encode2(TargetOpcode::G_FMINNUM),
        GIM_CheckType, /*MI*/1, /*Op*/1, /*Type*/GILLT_s32,
        GIM_CheckType, /*MI*/1, /*Op*/2, /*Type*/GILLT_s32,
        GIM_RecordInsn, /*DefineMI*/2, /*MI*/0, /*OpIdx*/2, // MIs[2]
        GIM_CheckOpcode, /*MI*/2, GIMT_Encode2(TargetOpcode::G_FMINNUM),
        GIM_CheckType, /*MI*/2, /*Op*/1, /*Type*/GILLT_s32,
        GIM_CheckType, /*MI*/2, /*Op*/2, /*Type*/GILLT_s32,
        GIM_RecordInsn, /*DefineMI*/3, /*MI*/2, /*OpIdx*/1, // MIs[3]
        GIM_CheckOpcode, /*MI*/3, GIMT_Encode2(TargetOpcode::G_FMAXNUM_IEEE),
        // MIs[3] VOP3Mods:src1:src1_mods
        GIM_CheckIsSameOperand, /*MI*/3, /*OpIdx*/1, /*OtherMI*/1, /*OtherOpIdx*/1,
        // MIs[3] VOP3Mods:src0:src0_mods
        GIM_CheckIsSameOperand, /*MI*/3, /*OpIdx*/2, /*OtherMI*/1, /*OtherOpIdx*/2,
        GIM_CheckCxxInsnPredicate, /*MI*/0, /*FnId*/GIMT_Encode2(GICXXPred_MI_Predicate_fmaxnum_like_nnan),
        GIM_CheckIsSafeToFold, /*InsnID*/1,
        GIM_CheckIsSafeToFold, /*InsnID*/2,
        GIM_CheckIsSafeToFold, /*InsnID*/3,
        GIM_CheckComplexPattern, /*MI*/1, /*Op*/1, /*Renderer*/GIMT_Encode2(0), GIMT_Encode2(GICP_gi_vop3mods),
        GIM_CheckComplexPattern, /*MI*/1, /*Op*/2, /*Renderer*/GIMT_Encode2(1), GIMT_Encode2(GICP_gi_vop3mods),
        GIM_CheckComplexPattern, /*MI*/2, /*Op*/2, /*Renderer*/GIMT_Encode2(2), GIMT_Encode2(GICP_gi_vop3mods),
        // (fmaxnum_ieee:{ *:[f32] } (fminnum:{ *:[f32] } (VOP3Mods:{ *:[f32] } f32:{ *:[f32] }:$src1, i32:{ *:[i32] }:$src1_mods), (VOP3Mods:{ *:[f32] } f32:{ *:[f32] }:$src0, i32:{ *:[i32] }:$src0_mods)), (fminnum:{ *:[f32] } (fmaxnum_ieee:{ *:[f32] } (VOP3Mods:{ *:[f32] } f32:{ *:[f32] }:$src1, i32:{ *:[i32] }:$src1_mods), (VOP3Mods:{ *:[f32] } f32:{ *:[f32] }:$src0, i32:{ *:[i32] }:$src0_mods)), (VOP3Mods:{ *:[f32] } f32:{ *:[f32] }:$src2, i32:{ *:[i32] }:$src2_mods)))<<P:Predicate_fmaxnum_like_nnan>>  =>  (V_MED3_F32_e64:{ *:[f32] } ?:{ *:[i32] }:$src0_mods, ?:{ *:[f32] }:$src0, ?:{ *:[i32] }:$src1_mods, ?:{ *:[f32] }:$src1, ?:{ *:[i32] }:$src2_mods, ?:{ *:[f32] }:$src2, 0:{ *:[i1] }, 0:{ *:[i32] })
        GIR_BuildMI, /*InsnID*/0, /*Opcode*/GIMT_Encode2(AMDGPU::V_MED3_F32_e64),
        GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/0, // DstI[vdst]
        GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(1), /*SubOperand*/1, // src0_mods
        GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(1), /*SubOperand*/0, // src0
        GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/1, // src1_mods
        GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/0, // src1
        GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(2), /*SubOperand*/1, // src2_mods
        GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(2), /*SubOperand*/0, // src2
        GIR_AddImm8, /*InsnID*/0, /*Imm*/0,
        GIR_AddImm8, /*InsnID*/0, /*Imm*/0,
        GIR_ConstrainSelectedInstOperands, /*InsnID*/0,
        GIR_EraseFromParent, /*InsnID*/0,
        // GIR_Coverage, 10094,
        GIR_Done,
      // Label 5073: @368256
      GIM_Try, /*On fail goto*//*Label 5074*/ GIMT_Encode4(368396), // Rule ID 10076 //
        GIM_CheckRegBankForClass, /*MI*/0, /*Op*/0, /*RC*/GIMT_Encode2(AMDGPU::VGPR_32RegClassID),
        GIM_RecordInsn, /*DefineMI*/1, /*MI*/0, /*OpIdx*/1, // MIs[1]
        GIM_CheckOpcode, /*MI*/1, GIMT_Encode2(TargetOpcode::G_FMINNUM),
        GIM_CheckType, /*MI*/1, /*Op*/1, /*Type*/GILLT_s32,
        GIM_CheckType, /*MI*/1, /*Op*/2, /*Type*/GILLT_s32,
        GIM_RecordInsn, /*DefineMI*/2, /*MI*/0, /*OpIdx*/2, // MIs[2]
        GIM_CheckOpcode, /*MI*/2, GIMT_Encode2(TargetOpcode::G_FMINNUM_IEEE),
        GIM_CheckType, /*MI*/2, /*Op*/1, /*Type*/GILLT_s32,
        GIM_CheckType, /*MI*/2, /*Op*/2, /*Type*/GILLT_s32,
        GIM_RecordInsn, /*DefineMI*/3, /*MI*/2, /*OpIdx*/2, // MIs[3]
        GIM_CheckOpcode, /*MI*/3, GIMT_Encode2(TargetOpcode::G_FMAXNUM),
        // MIs[3] VOP3Mods:src0:src0_mods
        GIM_CheckIsSameOperand, /*MI*/3, /*OpIdx*/1, /*OtherMI*/1, /*OtherOpIdx*/1,
        // MIs[3] VOP3Mods:src1:src1_mods
        GIM_CheckIsSameOperand, /*MI*/3, /*OpIdx*/2, /*OtherMI*/1, /*OtherOpIdx*/2,
        GIM_CheckCxxInsnPredicate, /*MI*/0, /*FnId*/GIMT_Encode2(GICXXPred_MI_Predicate_fmaxnum_like_nnan),
        GIM_CheckIsSafeToFold, /*InsnID*/1,
        GIM_CheckIsSafeToFold, /*InsnID*/2,
        GIM_CheckIsSafeToFold, /*InsnID*/3,
        GIM_CheckComplexPattern, /*MI*/1, /*Op*/1, /*Renderer*/GIMT_Encode2(0), GIMT_Encode2(GICP_gi_vop3mods),
        GIM_CheckComplexPattern, /*MI*/1, /*Op*/2, /*Renderer*/GIMT_Encode2(1), GIMT_Encode2(GICP_gi_vop3mods),
        GIM_CheckComplexPattern, /*MI*/2, /*Op*/1, /*Renderer*/GIMT_Encode2(2), GIMT_Encode2(GICP_gi_vop3mods),
        // (fmaxnum_ieee:{ *:[f32] } (fminnum:{ *:[f32] } (VOP3Mods:{ *:[f32] } f32:{ *:[f32] }:$src0, i32:{ *:[i32] }:$src0_mods), (VOP3Mods:{ *:[f32] } f32:{ *:[f32] }:$src1, i32:{ *:[i32] }:$src1_mods)), (fminnum_ieee:{ *:[f32] } (VOP3Mods:{ *:[f32] } f32:{ *:[f32] }:$src2, i32:{ *:[i32] }:$src2_mods), (fmaxnum:{ *:[f32] } (VOP3Mods:{ *:[f32] } f32:{ *:[f32] }:$src0, i32:{ *:[i32] }:$src0_mods), (VOP3Mods:{ *:[f32] } f32:{ *:[f32] }:$src1, i32:{ *:[i32] }:$src1_mods))))<<P:Predicate_fmaxnum_like_nnan>>  =>  (V_MED3_F32_e64:{ *:[f32] } ?:{ *:[i32] }:$src0_mods, ?:{ *:[f32] }:$src0, ?:{ *:[i32] }:$src1_mods, ?:{ *:[f32] }:$src1, ?:{ *:[i32] }:$src2_mods, ?:{ *:[f32] }:$src2, 0:{ *:[i1] }, 0:{ *:[i32] })
        GIR_BuildMI, /*InsnID*/0, /*Opcode*/GIMT_Encode2(AMDGPU::V_MED3_F32_e64),
        GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/0, // DstI[vdst]
        GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/1, // src0_mods
        GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/0, // src0
        GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(1), /*SubOperand*/1, // src1_mods
        GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(1), /*SubOperand*/0, // src1
        GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(2), /*SubOperand*/1, // src2_mods
        GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(2), /*SubOperand*/0, // src2
        GIR_AddImm8, /*InsnID*/0, /*Imm*/0,
        GIR_AddImm8, /*InsnID*/0, /*Imm*/0,
        GIR_ConstrainSelectedInstOperands, /*InsnID*/0,
        GIR_EraseFromParent, /*InsnID*/0,
        // GIR_Coverage, 10076,
        GIR_Done,
      // Label 5074: @368396
      GIM_Try, /*On fail goto*//*Label 5075*/ GIMT_Encode4(368536), // Rule ID 10077 //
        GIM_CheckRegBankForClass, /*MI*/0, /*Op*/0, /*RC*/GIMT_Encode2(AMDGPU::VGPR_32RegClassID),
        GIM_RecordInsn, /*DefineMI*/1, /*MI*/0, /*OpIdx*/1, // MIs[1]
        GIM_CheckOpcode, /*MI*/1, GIMT_Encode2(TargetOpcode::G_FMINNUM),
        GIM_CheckType, /*MI*/1, /*Op*/1, /*Type*/GILLT_s32,
        GIM_CheckType, /*MI*/1, /*Op*/2, /*Type*/GILLT_s32,
        GIM_RecordInsn, /*DefineMI*/2, /*MI*/0, /*OpIdx*/2, // MIs[2]
        GIM_CheckOpcode, /*MI*/2, GIMT_Encode2(TargetOpcode::G_FMINNUM_IEEE),
        GIM_CheckType, /*MI*/2, /*Op*/1, /*Type*/GILLT_s32,
        GIM_CheckType, /*MI*/2, /*Op*/2, /*Type*/GILLT_s32,
        GIM_RecordInsn, /*DefineMI*/3, /*MI*/2, /*OpIdx*/2, // MIs[3]
        GIM_CheckOpcode, /*MI*/3, GIMT_Encode2(TargetOpcode::G_FMAXNUM),
        // MIs[3] VOP3Mods:src1:src1_mods
        GIM_CheckIsSameOperand, /*MI*/3, /*OpIdx*/1, /*OtherMI*/1, /*OtherOpIdx*/2,
        // MIs[3] VOP3Mods:src0:src0_mods
        GIM_CheckIsSameOperand, /*MI*/3, /*OpIdx*/2, /*OtherMI*/1, /*OtherOpIdx*/1,
        GIM_CheckCxxInsnPredicate, /*MI*/0, /*FnId*/GIMT_Encode2(GICXXPred_MI_Predicate_fmaxnum_like_nnan),
        GIM_CheckIsSafeToFold, /*InsnID*/1,
        GIM_CheckIsSafeToFold, /*InsnID*/2,
        GIM_CheckIsSafeToFold, /*InsnID*/3,
        GIM_CheckComplexPattern, /*MI*/1, /*Op*/1, /*Renderer*/GIMT_Encode2(0), GIMT_Encode2(GICP_gi_vop3mods),
        GIM_CheckComplexPattern, /*MI*/1, /*Op*/2, /*Renderer*/GIMT_Encode2(1), GIMT_Encode2(GICP_gi_vop3mods),
        GIM_CheckComplexPattern, /*MI*/2, /*Op*/1, /*Renderer*/GIMT_Encode2(2), GIMT_Encode2(GICP_gi_vop3mods),
        // (fmaxnum_ieee:{ *:[f32] } (fminnum:{ *:[f32] } (VOP3Mods:{ *:[f32] } f32:{ *:[f32] }:$src0, i32:{ *:[i32] }:$src0_mods), (VOP3Mods:{ *:[f32] } f32:{ *:[f32] }:$src1, i32:{ *:[i32] }:$src1_mods)), (fminnum_ieee:{ *:[f32] } (VOP3Mods:{ *:[f32] } f32:{ *:[f32] }:$src2, i32:{ *:[i32] }:$src2_mods), (fmaxnum:{ *:[f32] } (VOP3Mods:{ *:[f32] } f32:{ *:[f32] }:$src1, i32:{ *:[i32] }:$src1_mods), (VOP3Mods:{ *:[f32] } f32:{ *:[f32] }:$src0, i32:{ *:[i32] }:$src0_mods))))<<P:Predicate_fmaxnum_like_nnan>>  =>  (V_MED3_F32_e64:{ *:[f32] } ?:{ *:[i32] }:$src0_mods, ?:{ *:[f32] }:$src0, ?:{ *:[i32] }:$src1_mods, ?:{ *:[f32] }:$src1, ?:{ *:[i32] }:$src2_mods, ?:{ *:[f32] }:$src2, 0:{ *:[i1] }, 0:{ *:[i32] })
        GIR_BuildMI, /*InsnID*/0, /*Opcode*/GIMT_Encode2(AMDGPU::V_MED3_F32_e64),
        GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/0, // DstI[vdst]
        GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/1, // src0_mods
        GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/0, // src0
        GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(1), /*SubOperand*/1, // src1_mods
        GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(1), /*SubOperand*/0, // src1
        GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(2), /*SubOperand*/1, // src2_mods
        GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(2), /*SubOperand*/0, // src2
        GIR_AddImm8, /*InsnID*/0, /*Imm*/0,
        GIR_AddImm8, /*InsnID*/0, /*Imm*/0,
        GIR_ConstrainSelectedInstOperands, /*InsnID*/0,
        GIR_EraseFromParent, /*InsnID*/0,
        // GIR_Coverage, 10077,
        GIR_Done,
      // Label 5075: @368536
      GIM_Try, /*On fail goto*//*Label 5076*/ GIMT_Encode4(368676), // Rule ID 10080 //
        GIM_CheckRegBankForClass, /*MI*/0, /*Op*/0, /*RC*/GIMT_Encode2(AMDGPU::VGPR_32RegClassID),
        GIM_RecordInsn, /*DefineMI*/1, /*MI*/0, /*OpIdx*/1, // MIs[1]
        GIM_CheckOpcode, /*MI*/1, GIMT_Encode2(TargetOpcode::G_FMINNUM),
        GIM_CheckType, /*MI*/1, /*Op*/1, /*Type*/GILLT_s32,
        GIM_CheckType, /*MI*/1, /*Op*/2, /*Type*/GILLT_s32,
        GIM_RecordInsn, /*DefineMI*/2, /*MI*/0, /*OpIdx*/2, // MIs[2]
        GIM_CheckOpcode, /*MI*/2, GIMT_Encode2(TargetOpcode::G_FMINNUM_IEEE),
        GIM_CheckType, /*MI*/2, /*Op*/1, /*Type*/GILLT_s32,
        GIM_CheckType, /*MI*/2, /*Op*/2, /*Type*/GILLT_s32,
        GIM_RecordInsn, /*DefineMI*/3, /*MI*/2, /*OpIdx*/2, // MIs[3]
        GIM_CheckOpcode, /*MI*/3, GIMT_Encode2(TargetOpcode::G_FMAXNUM),
        // MIs[3] VOP3Mods:src0:src0_mods
        GIM_CheckIsSameOperand, /*MI*/3, /*OpIdx*/1, /*OtherMI*/1, /*OtherOpIdx*/2,
        // MIs[3] VOP3Mods:src1:src1_mods
        GIM_CheckIsSameOperand, /*MI*/3, /*OpIdx*/2, /*OtherMI*/1, /*OtherOpIdx*/1,
        GIM_CheckCxxInsnPredicate, /*MI*/0, /*FnId*/GIMT_Encode2(GICXXPred_MI_Predicate_fmaxnum_like_nnan),
        GIM_CheckIsSafeToFold, /*InsnID*/1,
        GIM_CheckIsSafeToFold, /*InsnID*/2,
        GIM_CheckIsSafeToFold, /*InsnID*/3,
        GIM_CheckComplexPattern, /*MI*/1, /*Op*/1, /*Renderer*/GIMT_Encode2(0), GIMT_Encode2(GICP_gi_vop3mods),
        GIM_CheckComplexPattern, /*MI*/1, /*Op*/2, /*Renderer*/GIMT_Encode2(1), GIMT_Encode2(GICP_gi_vop3mods),
        GIM_CheckComplexPattern, /*MI*/2, /*Op*/1, /*Renderer*/GIMT_Encode2(2), GIMT_Encode2(GICP_gi_vop3mods),
        // (fmaxnum_ieee:{ *:[f32] } (fminnum:{ *:[f32] } (VOP3Mods:{ *:[f32] } f32:{ *:[f32] }:$src1, i32:{ *:[i32] }:$src1_mods), (VOP3Mods:{ *:[f32] } f32:{ *:[f32] }:$src0, i32:{ *:[i32] }:$src0_mods)), (fminnum_ieee:{ *:[f32] } (VOP3Mods:{ *:[f32] } f32:{ *:[f32] }:$src2, i32:{ *:[i32] }:$src2_mods), (fmaxnum:{ *:[f32] } (VOP3Mods:{ *:[f32] } f32:{ *:[f32] }:$src0, i32:{ *:[i32] }:$src0_mods), (VOP3Mods:{ *:[f32] } f32:{ *:[f32] }:$src1, i32:{ *:[i32] }:$src1_mods))))<<P:Predicate_fmaxnum_like_nnan>>  =>  (V_MED3_F32_e64:{ *:[f32] } ?:{ *:[i32] }:$src0_mods, ?:{ *:[f32] }:$src0, ?:{ *:[i32] }:$src1_mods, ?:{ *:[f32] }:$src1, ?:{ *:[i32] }:$src2_mods, ?:{ *:[f32] }:$src2, 0:{ *:[i1] }, 0:{ *:[i32] })
        GIR_BuildMI, /*InsnID*/0, /*Opcode*/GIMT_Encode2(AMDGPU::V_MED3_F32_e64),
        GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/0, // DstI[vdst]
        GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(1), /*SubOperand*/1, // src0_mods
        GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(1), /*SubOperand*/0, // src0
        GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/1, // src1_mods
        GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/0, // src1
        GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(2), /*SubOperand*/1, // src2_mods
        GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(2), /*SubOperand*/0, // src2
        GIR_AddImm8, /*InsnID*/0, /*Imm*/0,
        GIR_AddImm8, /*InsnID*/0, /*Imm*/0,
        GIR_ConstrainSelectedInstOperands, /*InsnID*/0,
        GIR_EraseFromParent, /*InsnID*/0,
        // GIR_Coverage, 10080,
        GIR_Done,
      // Label 5076: @368676
      GIM_Try, /*On fail goto*//*Label 5077*/ GIMT_Encode4(368816), // Rule ID 10081 //
        GIM_CheckRegBankForClass, /*MI*/0, /*Op*/0, /*RC*/GIMT_Encode2(AMDGPU::VGPR_32RegClassID),
        GIM_RecordInsn, /*DefineMI*/1, /*MI*/0, /*OpIdx*/1, // MIs[1]
        GIM_CheckOpcode, /*MI*/1, GIMT_Encode2(TargetOpcode::G_FMINNUM),
        GIM_CheckType, /*MI*/1, /*Op*/1, /*Type*/GILLT_s32,
        GIM_CheckType, /*MI*/1, /*Op*/2, /*Type*/GILLT_s32,
        GIM_RecordInsn, /*DefineMI*/2, /*MI*/0, /*OpIdx*/2, // MIs[2]
        GIM_CheckOpcode, /*MI*/2, GIMT_Encode2(TargetOpcode::G_FMINNUM_IEEE),
        GIM_CheckType, /*MI*/2, /*Op*/1, /*Type*/GILLT_s32,
        GIM_CheckType, /*MI*/2, /*Op*/2, /*Type*/GILLT_s32,
        GIM_RecordInsn, /*DefineMI*/3, /*MI*/2, /*OpIdx*/2, // MIs[3]
        GIM_CheckOpcode, /*MI*/3, GIMT_Encode2(TargetOpcode::G_FMAXNUM),
        // MIs[3] VOP3Mods:src1:src1_mods
        GIM_CheckIsSameOperand, /*MI*/3, /*OpIdx*/1, /*OtherMI*/1, /*OtherOpIdx*/1,
        // MIs[3] VOP3Mods:src0:src0_mods
        GIM_CheckIsSameOperand, /*MI*/3, /*OpIdx*/2, /*OtherMI*/1, /*OtherOpIdx*/2,
        GIM_CheckCxxInsnPredicate, /*MI*/0, /*FnId*/GIMT_Encode2(GICXXPred_MI_Predicate_fmaxnum_like_nnan),
        GIM_CheckIsSafeToFold, /*InsnID*/1,
        GIM_CheckIsSafeToFold, /*InsnID*/2,
        GIM_CheckIsSafeToFold, /*InsnID*/3,
        GIM_CheckComplexPattern, /*MI*/1, /*Op*/1, /*Renderer*/GIMT_Encode2(0), GIMT_Encode2(GICP_gi_vop3mods),
        GIM_CheckComplexPattern, /*MI*/1, /*Op*/2, /*Renderer*/GIMT_Encode2(1), GIMT_Encode2(GICP_gi_vop3mods),
        GIM_CheckComplexPattern, /*MI*/2, /*Op*/1, /*Renderer*/GIMT_Encode2(2), GIMT_Encode2(GICP_gi_vop3mods),
        // (fmaxnum_ieee:{ *:[f32] } (fminnum:{ *:[f32] } (VOP3Mods:{ *:[f32] } f32:{ *:[f32] }:$src1, i32:{ *:[i32] }:$src1_mods), (VOP3Mods:{ *:[f32] } f32:{ *:[f32] }:$src0, i32:{ *:[i32] }:$src0_mods)), (fminnum_ieee:{ *:[f32] } (VOP3Mods:{ *:[f32] } f32:{ *:[f32] }:$src2, i32:{ *:[i32] }:$src2_mods), (fmaxnum:{ *:[f32] } (VOP3Mods:{ *:[f32] } f32:{ *:[f32] }:$src1, i32:{ *:[i32] }:$src1_mods), (VOP3Mods:{ *:[f32] } f32:{ *:[f32] }:$src0, i32:{ *:[i32] }:$src0_mods))))<<P:Predicate_fmaxnum_like_nnan>>  =>  (V_MED3_F32_e64:{ *:[f32] } ?:{ *:[i32] }:$src0_mods, ?:{ *:[f32] }:$src0, ?:{ *:[i32] }:$src1_mods, ?:{ *:[f32] }:$src1, ?:{ *:[i32] }:$src2_mods, ?:{ *:[f32] }:$src2, 0:{ *:[i1] }, 0:{ *:[i32] })
        GIR_BuildMI, /*InsnID*/0, /*Opcode*/GIMT_Encode2(AMDGPU::V_MED3_F32_e64),
        GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/0, // DstI[vdst]
        GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(1), /*SubOperand*/1, // src0_mods
        GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(1), /*SubOperand*/0, // src0
        GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/1, // src1_mods
        GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/0, // src1
        GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(2), /*SubOperand*/1, // src2_mods
        GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(2), /*SubOperand*/0, // src2
        GIR_AddImm8, /*InsnID*/0, /*Imm*/0,
        GIR_AddImm8, /*InsnID*/0, /*Imm*/0,
        GIR_ConstrainSelectedInstOperands, /*InsnID*/0,
        GIR_EraseFromParent, /*InsnID*/0,
        // GIR_Coverage, 10081,
        GIR_Done,
      // Label 5077: @368816
      GIM_Try, /*On fail goto*//*Label 5078*/ GIMT_Encode4(368956), // Rule ID 10061 //
        GIM_CheckRegBankForClass, /*MI*/0, /*Op*/0, /*RC*/GIMT_Encode2(AMDGPU::VGPR_32RegClassID),
        GIM_RecordInsn, /*DefineMI*/1, /*MI*/0, /*OpIdx*/1, // MIs[1]
        GIM_CheckOpcode, /*MI*/1, GIMT_Encode2(TargetOpcode::G_FMINNUM),
        GIM_CheckType, /*MI*/1, /*Op*/1, /*Type*/GILLT_s32,
        GIM_CheckType, /*MI*/1, /*Op*/2, /*Type*/GILLT_s32,
        GIM_RecordInsn, /*DefineMI*/2, /*MI*/0, /*OpIdx*/2, // MIs[2]
        GIM_CheckOpcode, /*MI*/2, GIMT_Encode2(TargetOpcode::G_FMINNUM_IEEE),
        GIM_CheckType, /*MI*/2, /*Op*/1, /*Type*/GILLT_s32,
        GIM_CheckType, /*MI*/2, /*Op*/2, /*Type*/GILLT_s32,
        GIM_RecordInsn, /*DefineMI*/3, /*MI*/2, /*OpIdx*/2, // MIs[3]
        GIM_CheckOpcode, /*MI*/3, GIMT_Encode2(TargetOpcode::G_FMAXNUM_IEEE),
        // MIs[3] VOP3Mods:src0:src0_mods
        GIM_CheckIsSameOperand, /*MI*/3, /*OpIdx*/1, /*OtherMI*/1, /*OtherOpIdx*/1,
        // MIs[3] VOP3Mods:src1:src1_mods
        GIM_CheckIsSameOperand, /*MI*/3, /*OpIdx*/2, /*OtherMI*/1, /*OtherOpIdx*/2,
        GIM_CheckCxxInsnPredicate, /*MI*/0, /*FnId*/GIMT_Encode2(GICXXPred_MI_Predicate_fmaxnum_like_nnan),
        GIM_CheckIsSafeToFold, /*InsnID*/1,
        GIM_CheckIsSafeToFold, /*InsnID*/2,
        GIM_CheckIsSafeToFold, /*InsnID*/3,
        GIM_CheckComplexPattern, /*MI*/1, /*Op*/1, /*Renderer*/GIMT_Encode2(0), GIMT_Encode2(GICP_gi_vop3mods),
        GIM_CheckComplexPattern, /*MI*/1, /*Op*/2, /*Renderer*/GIMT_Encode2(1), GIMT_Encode2(GICP_gi_vop3mods),
        GIM_CheckComplexPattern, /*MI*/2, /*Op*/1, /*Renderer*/GIMT_Encode2(2), GIMT_Encode2(GICP_gi_vop3mods),
        // (fmaxnum_ieee:{ *:[f32] } (fminnum:{ *:[f32] } (VOP3Mods:{ *:[f32] } f32:{ *:[f32] }:$src0, i32:{ *:[i32] }:$src0_mods), (VOP3Mods:{ *:[f32] } f32:{ *:[f32] }:$src1, i32:{ *:[i32] }:$src1_mods)), (fminnum_ieee:{ *:[f32] } (VOP3Mods:{ *:[f32] } f32:{ *:[f32] }:$src2, i32:{ *:[i32] }:$src2_mods), (fmaxnum_ieee:{ *:[f32] } (VOP3Mods:{ *:[f32] } f32:{ *:[f32] }:$src0, i32:{ *:[i32] }:$src0_mods), (VOP3Mods:{ *:[f32] } f32:{ *:[f32] }:$src1, i32:{ *:[i32] }:$src1_mods))))<<P:Predicate_fmaxnum_like_nnan>>  =>  (V_MED3_F32_e64:{ *:[f32] } ?:{ *:[i32] }:$src0_mods, ?:{ *:[f32] }:$src0, ?:{ *:[i32] }:$src1_mods, ?:{ *:[f32] }:$src1, ?:{ *:[i32] }:$src2_mods, ?:{ *:[f32] }:$src2, 0:{ *:[i1] }, 0:{ *:[i32] })
        GIR_BuildMI, /*InsnID*/0, /*Opcode*/GIMT_Encode2(AMDGPU::V_MED3_F32_e64),
        GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/0, // DstI[vdst]
        GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/1, // src0_mods
        GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/0, // src0
        GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(1), /*SubOperand*/1, // src1_mods
        GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(1), /*SubOperand*/0, // src1
        GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(2), /*SubOperand*/1, // src2_mods
        GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(2), /*SubOperand*/0, // src2
        GIR_AddImm8, /*InsnID*/0, /*Imm*/0,
        GIR_AddImm8, /*InsnID*/0, /*Imm*/0,
        GIR_ConstrainSelectedInstOperands, /*InsnID*/0,
        GIR_EraseFromParent, /*InsnID*/0,
        // GIR_Coverage, 10061,
        GIR_Done,
      // Label 5078: @368956
      GIM_Try, /*On fail goto*//*Label 5079*/ GIMT_Encode4(369096), // Rule ID 10062 //
        GIM_CheckRegBankForClass, /*MI*/0, /*Op*/0, /*RC*/GIMT_Encode2(AMDGPU::VGPR_32RegClassID),
        GIM_RecordInsn, /*DefineMI*/1, /*MI*/0, /*OpIdx*/1, // MIs[1]
        GIM_CheckOpcode, /*MI*/1, GIMT_Encode2(TargetOpcode::G_FMINNUM),
        GIM_CheckType, /*MI*/1, /*Op*/1, /*Type*/GILLT_s32,
        GIM_CheckType, /*MI*/1, /*Op*/2, /*Type*/GILLT_s32,
        GIM_RecordInsn, /*DefineMI*/2, /*MI*/0, /*OpIdx*/2, // MIs[2]
        GIM_CheckOpcode, /*MI*/2, GIMT_Encode2(TargetOpcode::G_FMINNUM_IEEE),
        GIM_CheckType, /*MI*/2, /*Op*/1, /*Type*/GILLT_s32,
        GIM_CheckType, /*MI*/2, /*Op*/2, /*Type*/GILLT_s32,
        GIM_RecordInsn, /*DefineMI*/3, /*MI*/2, /*OpIdx*/2, // MIs[3]
        GIM_CheckOpcode, /*MI*/3, GIMT_Encode2(TargetOpcode::G_FMAXNUM_IEEE),
        // MIs[3] VOP3Mods:src1:src1_mods
        GIM_CheckIsSameOperand, /*MI*/3, /*OpIdx*/1, /*OtherMI*/1, /*OtherOpIdx*/2,
        // MIs[3] VOP3Mods:src0:src0_mods
        GIM_CheckIsSameOperand, /*MI*/3, /*OpIdx*/2, /*OtherMI*/1, /*OtherOpIdx*/1,
        GIM_CheckCxxInsnPredicate, /*MI*/0, /*FnId*/GIMT_Encode2(GICXXPred_MI_Predicate_fmaxnum_like_nnan),
        GIM_CheckIsSafeToFold, /*InsnID*/1,
        GIM_CheckIsSafeToFold, /*InsnID*/2,
        GIM_CheckIsSafeToFold, /*InsnID*/3,
        GIM_CheckComplexPattern, /*MI*/1, /*Op*/1, /*Renderer*/GIMT_Encode2(0), GIMT_Encode2(GICP_gi_vop3mods),
        GIM_CheckComplexPattern, /*MI*/1, /*Op*/2, /*Renderer*/GIMT_Encode2(1), GIMT_Encode2(GICP_gi_vop3mods),
        GIM_CheckComplexPattern, /*MI*/2, /*Op*/1, /*Renderer*/GIMT_Encode2(2), GIMT_Encode2(GICP_gi_vop3mods),
        // (fmaxnum_ieee:{ *:[f32] } (fminnum:{ *:[f32] } (VOP3Mods:{ *:[f32] } f32:{ *:[f32] }:$src0, i32:{ *:[i32] }:$src0_mods), (VOP3Mods:{ *:[f32] } f32:{ *:[f32] }:$src1, i32:{ *:[i32] }:$src1_mods)), (fminnum_ieee:{ *:[f32] } (VOP3Mods:{ *:[f32] } f32:{ *:[f32] }:$src2, i32:{ *:[i32] }:$src2_mods), (fmaxnum_ieee:{ *:[f32] } (VOP3Mods:{ *:[f32] } f32:{ *:[f32] }:$src1, i32:{ *:[i32] }:$src1_mods), (VOP3Mods:{ *:[f32] } f32:{ *:[f32] }:$src0, i32:{ *:[i32] }:$src0_mods))))<<P:Predicate_fmaxnum_like_nnan>>  =>  (V_MED3_F32_e64:{ *:[f32] } ?:{ *:[i32] }:$src0_mods, ?:{ *:[f32] }:$src0, ?:{ *:[i32] }:$src1_mods, ?:{ *:[f32] }:$src1, ?:{ *:[i32] }:$src2_mods, ?:{ *:[f32] }:$src2, 0:{ *:[i1] }, 0:{ *:[i32] })
        GIR_BuildMI, /*InsnID*/0, /*Opcode*/GIMT_Encode2(AMDGPU::V_MED3_F32_e64),
        GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/0, // DstI[vdst]
        GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/1, // src0_mods
        GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/0, // src0
        GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(1), /*SubOperand*/1, // src1_mods
        GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(1), /*SubOperand*/0, // src1
        GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(2), /*SubOperand*/1, // src2_mods
        GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(2), /*SubOperand*/0, // src2
        GIR_AddImm8, /*InsnID*/0, /*Imm*/0,
        GIR_AddImm8, /*InsnID*/0, /*Imm*/0,
        GIR_ConstrainSelectedInstOperands, /*InsnID*/0,
        GIR_EraseFromParent, /*InsnID*/0,
        // GIR_Coverage, 10062,
        GIR_Done,
      // Label 5079: @369096
      GIM_Try, /*On fail goto*//*Label 5080*/ GIMT_Encode4(369236), // Rule ID 10065 //
        GIM_CheckRegBankForClass, /*MI*/0, /*Op*/0, /*RC*/GIMT_Encode2(AMDGPU::VGPR_32RegClassID),
        GIM_RecordInsn, /*DefineMI*/1, /*MI*/0, /*OpIdx*/1, // MIs[1]
        GIM_CheckOpcode, /*MI*/1, GIMT_Encode2(TargetOpcode::G_FMINNUM),
        GIM_CheckType, /*MI*/1, /*Op*/1, /*Type*/GILLT_s32,
        GIM_CheckType, /*MI*/1, /*Op*/2, /*Type*/GILLT_s32,
        GIM_RecordInsn, /*DefineMI*/2, /*MI*/0, /*OpIdx*/2, // MIs[2]
        GIM_CheckOpcode, /*MI*/2, GIMT_Encode2(TargetOpcode::G_FMINNUM_IEEE),
        GIM_CheckType, /*MI*/2, /*Op*/1, /*Type*/GILLT_s32,
        GIM_CheckType, /*MI*/2, /*Op*/2, /*Type*/GILLT_s32,
        GIM_RecordInsn, /*DefineMI*/3, /*MI*/2, /*OpIdx*/2, // MIs[3]
        GIM_CheckOpcode, /*MI*/3, GIMT_Encode2(TargetOpcode::G_FMAXNUM_IEEE),
        // MIs[3] VOP3Mods:src0:src0_mods
        GIM_CheckIsSameOperand, /*MI*/3, /*OpIdx*/1, /*OtherMI*/1, /*OtherOpIdx*/2,
        // MIs[3] VOP3Mods:src1:src1_mods
        GIM_CheckIsSameOperand, /*MI*/3, /*OpIdx*/2, /*OtherMI*/1, /*OtherOpIdx*/1,
        GIM_CheckCxxInsnPredicate, /*MI*/0, /*FnId*/GIMT_Encode2(GICXXPred_MI_Predicate_fmaxnum_like_nnan),
        GIM_CheckIsSafeToFold, /*InsnID*/1,
        GIM_CheckIsSafeToFold, /*InsnID*/2,
        GIM_CheckIsSafeToFold, /*InsnID*/3,
        GIM_CheckComplexPattern, /*MI*/1, /*Op*/1, /*Renderer*/GIMT_Encode2(0), GIMT_Encode2(GICP_gi_vop3mods),
        GIM_CheckComplexPattern, /*MI*/1, /*Op*/2, /*Renderer*/GIMT_Encode2(1), GIMT_Encode2(GICP_gi_vop3mods),
        GIM_CheckComplexPattern, /*MI*/2, /*Op*/1, /*Renderer*/GIMT_Encode2(2), GIMT_Encode2(GICP_gi_vop3mods),
        // (fmaxnum_ieee:{ *:[f32] } (fminnum:{ *:[f32] } (VOP3Mods:{ *:[f32] } f32:{ *:[f32] }:$src1, i32:{ *:[i32] }:$src1_mods), (VOP3Mods:{ *:[f32] } f32:{ *:[f32] }:$src0, i32:{ *:[i32] }:$src0_mods)), (fminnum_ieee:{ *:[f32] } (VOP3Mods:{ *:[f32] } f32:{ *:[f32] }:$src2, i32:{ *:[i32] }:$src2_mods), (fmaxnum_ieee:{ *:[f32] } (VOP3Mods:{ *:[f32] } f32:{ *:[f32] }:$src0, i32:{ *:[i32] }:$src0_mods), (VOP3Mods:{ *:[f32] } f32:{ *:[f32] }:$src1, i32:{ *:[i32] }:$src1_mods))))<<P:Predicate_fmaxnum_like_nnan>>  =>  (V_MED3_F32_e64:{ *:[f32] } ?:{ *:[i32] }:$src0_mods, ?:{ *:[f32] }:$src0, ?:{ *:[i32] }:$src1_mods, ?:{ *:[f32] }:$src1, ?:{ *:[i32] }:$src2_mods, ?:{ *:[f32] }:$src2, 0:{ *:[i1] }, 0:{ *:[i32] })
        GIR_BuildMI, /*InsnID*/0, /*Opcode*/GIMT_Encode2(AMDGPU::V_MED3_F32_e64),
        GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/0, // DstI[vdst]
        GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(1), /*SubOperand*/1, // src0_mods
        GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(1), /*SubOperand*/0, // src0
        GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/1, // src1_mods
        GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/0, // src1
        GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(2), /*SubOperand*/1, // src2_mods
        GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(2), /*SubOperand*/0, // src2
        GIR_AddImm8, /*InsnID*/0, /*Imm*/0,
        GIR_AddImm8, /*InsnID*/0, /*Imm*/0,
        GIR_ConstrainSelectedInstOperands, /*InsnID*/0,
        GIR_EraseFromParent, /*InsnID*/0,
        // GIR_Coverage, 10065,
        GIR_Done,
      // Label 5080: @369236
      GIM_Try, /*On fail goto*//*Label 5081*/ GIMT_Encode4(369376), // Rule ID 10066 //
        GIM_CheckRegBankForClass, /*MI*/0, /*Op*/0, /*RC*/GIMT_Encode2(AMDGPU::VGPR_32RegClassID),
        GIM_RecordInsn, /*DefineMI*/1, /*MI*/0, /*OpIdx*/1, // MIs[1]
        GIM_CheckOpcode, /*MI*/1, GIMT_Encode2(TargetOpcode::G_FMINNUM),
        GIM_CheckType, /*MI*/1, /*Op*/1, /*Type*/GILLT_s32,
        GIM_CheckType, /*MI*/1, /*Op*/2, /*Type*/GILLT_s32,
        GIM_RecordInsn, /*DefineMI*/2, /*MI*/0, /*OpIdx*/2, // MIs[2]
        GIM_CheckOpcode, /*MI*/2, GIMT_Encode2(TargetOpcode::G_FMINNUM_IEEE),
        GIM_CheckType, /*MI*/2, /*Op*/1, /*Type*/GILLT_s32,
        GIM_CheckType, /*MI*/2, /*Op*/2, /*Type*/GILLT_s32,
        GIM_RecordInsn, /*DefineMI*/3, /*MI*/2, /*OpIdx*/2, // MIs[3]
        GIM_CheckOpcode, /*MI*/3, GIMT_Encode2(TargetOpcode::G_FMAXNUM_IEEE),
        // MIs[3] VOP3Mods:src1:src1_mods
        GIM_CheckIsSameOperand, /*MI*/3, /*OpIdx*/1, /*OtherMI*/1, /*OtherOpIdx*/1,
        // MIs[3] VOP3Mods:src0:src0_mods
        GIM_CheckIsSameOperand, /*MI*/3, /*OpIdx*/2, /*OtherMI*/1, /*OtherOpIdx*/2,
        GIM_CheckCxxInsnPredicate, /*MI*/0, /*FnId*/GIMT_Encode2(GICXXPred_MI_Predicate_fmaxnum_like_nnan),
        GIM_CheckIsSafeToFold, /*InsnID*/1,
        GIM_CheckIsSafeToFold, /*InsnID*/2,
        GIM_CheckIsSafeToFold, /*InsnID*/3,
        GIM_CheckComplexPattern, /*MI*/1, /*Op*/1, /*Renderer*/GIMT_Encode2(0), GIMT_Encode2(GICP_gi_vop3mods),
        GIM_CheckComplexPattern, /*MI*/1, /*Op*/2, /*Renderer*/GIMT_Encode2(1), GIMT_Encode2(GICP_gi_vop3mods),
        GIM_CheckComplexPattern, /*MI*/2, /*Op*/1, /*Renderer*/GIMT_Encode2(2), GIMT_Encode2(GICP_gi_vop3mods),
        // (fmaxnum_ieee:{ *:[f32] } (fminnum:{ *:[f32] } (VOP3Mods:{ *:[f32] } f32:{ *:[f32] }:$src1, i32:{ *:[i32] }:$src1_mods), (VOP3Mods:{ *:[f32] } f32:{ *:[f32] }:$src0, i32:{ *:[i32] }:$src0_mods)), (fminnum_ieee:{ *:[f32] } (VOP3Mods:{ *:[f32] } f32:{ *:[f32] }:$src2, i32:{ *:[i32] }:$src2_mods), (fmaxnum_ieee:{ *:[f32] } (VOP3Mods:{ *:[f32] } f32:{ *:[f32] }:$src1, i32:{ *:[i32] }:$src1_mods), (VOP3Mods:{ *:[f32] } f32:{ *:[f32] }:$src0, i32:{ *:[i32] }:$src0_mods))))<<P:Predicate_fmaxnum_like_nnan>>  =>  (V_MED3_F32_e64:{ *:[f32] } ?:{ *:[i32] }:$src0_mods, ?:{ *:[f32] }:$src0, ?:{ *:[i32] }:$src1_mods, ?:{ *:[f32] }:$src1, ?:{ *:[i32] }:$src2_mods, ?:{ *:[f32] }:$src2, 0:{ *:[i1] }, 0:{ *:[i32] })
        GIR_BuildMI, /*InsnID*/0, /*Opcode*/GIMT_Encode2(AMDGPU::V_MED3_F32_e64),
        GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/0, // DstI[vdst]
        GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(1), /*SubOperand*/1, // src0_mods
        GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(1), /*SubOperand*/0, // src0
        GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/1, // src1_mods
        GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/0, // src1
        GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(2), /*SubOperand*/1, // src2_mods
        GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(2), /*SubOperand*/0, // src2
        GIR_AddImm8, /*InsnID*/0, /*Imm*/0,
        GIR_AddImm8, /*InsnID*/0, /*Imm*/0,
        GIR_ConstrainSelectedInstOperands, /*InsnID*/0,
        GIR_EraseFromParent, /*InsnID*/0,
        // GIR_Coverage, 10066,
        GIR_Done,
      // Label 5081: @369376
      GIM_Try, /*On fail goto*//*Label 5082*/ GIMT_Encode4(369516), // Rule ID 6487 //
        GIM_CheckRegBankForClass, /*MI*/0, /*Op*/0, /*RC*/GIMT_Encode2(AMDGPU::VGPR_32RegClassID),
        GIM_RecordInsn, /*DefineMI*/1, /*MI*/0, /*OpIdx*/1, // MIs[1]
        GIM_CheckOpcode, /*MI*/1, GIMT_Encode2(TargetOpcode::G_FMINNUM),
        GIM_CheckType, /*MI*/1, /*Op*/1, /*Type*/GILLT_s32,
        GIM_CheckType, /*MI*/1, /*Op*/2, /*Type*/GILLT_s32,
        GIM_RecordInsn, /*DefineMI*/2, /*MI*/0, /*OpIdx*/2, // MIs[2]
        GIM_CheckOpcode, /*MI*/2, GIMT_Encode2(TargetOpcode::G_FMINNUM_IEEE),
        GIM_CheckType, /*MI*/2, /*Op*/1, /*Type*/GILLT_s32,
        GIM_CheckType, /*MI*/2, /*Op*/2, /*Type*/GILLT_s32,
        GIM_RecordInsn, /*DefineMI*/3, /*MI*/2, /*OpIdx*/1, // MIs[3]
        GIM_CheckOpcode, /*MI*/3, GIMT_Encode2(TargetOpcode::G_FMAXNUM),
        // MIs[3] VOP3Mods:src0:src0_mods
        GIM_CheckIsSameOperand, /*MI*/3, /*OpIdx*/1, /*OtherMI*/1, /*OtherOpIdx*/1,
        // MIs[3] VOP3Mods:src1:src1_mods
        GIM_CheckIsSameOperand, /*MI*/3, /*OpIdx*/2, /*OtherMI*/1, /*OtherOpIdx*/2,
        GIM_CheckCxxInsnPredicate, /*MI*/0, /*FnId*/GIMT_Encode2(GICXXPred_MI_Predicate_fmaxnum_like_nnan),
        GIM_CheckIsSafeToFold, /*InsnID*/1,
        GIM_CheckIsSafeToFold, /*InsnID*/2,
        GIM_CheckIsSafeToFold, /*InsnID*/3,
        GIM_CheckComplexPattern, /*MI*/1, /*Op*/1, /*Renderer*/GIMT_Encode2(0), GIMT_Encode2(GICP_gi_vop3mods),
        GIM_CheckComplexPattern, /*MI*/1, /*Op*/2, /*Renderer*/GIMT_Encode2(1), GIMT_Encode2(GICP_gi_vop3mods),
        GIM_CheckComplexPattern, /*MI*/2, /*Op*/2, /*Renderer*/GIMT_Encode2(2), GIMT_Encode2(GICP_gi_vop3mods),
        // (fmaxnum_ieee:{ *:[f32] } (fminnum:{ *:[f32] } (VOP3Mods:{ *:[f32] } f32:{ *:[f32] }:$src0, i32:{ *:[i32] }:$src0_mods), (VOP3Mods:{ *:[f32] } f32:{ *:[f32] }:$src1, i32:{ *:[i32] }:$src1_mods)), (fminnum_ieee:{ *:[f32] } (fmaxnum:{ *:[f32] } (VOP3Mods:{ *:[f32] } f32:{ *:[f32] }:$src0, i32:{ *:[i32] }:$src0_mods), (VOP3Mods:{ *:[f32] } f32:{ *:[f32] }:$src1, i32:{ *:[i32] }:$src1_mods)), (VOP3Mods:{ *:[f32] } f32:{ *:[f32] }:$src2, i32:{ *:[i32] }:$src2_mods)))<<P:Predicate_fmaxnum_like_nnan>>  =>  (V_MED3_F32_e64:{ *:[f32] } ?:{ *:[i32] }:$src0_mods, ?:{ *:[f32] }:$src0, ?:{ *:[i32] }:$src1_mods, ?:{ *:[f32] }:$src1, ?:{ *:[i32] }:$src2_mods, ?:{ *:[f32] }:$src2, 0:{ *:[i1] }, 0:{ *:[i32] })
        GIR_BuildMI, /*InsnID*/0, /*Opcode*/GIMT_Encode2(AMDGPU::V_MED3_F32_e64),
        GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/0, // DstI[vdst]
        GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/1, // src0_mods
        GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/0, // src0
        GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(1), /*SubOperand*/1, // src1_mods
        GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(1), /*SubOperand*/0, // src1
        GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(2), /*SubOperand*/1, // src2_mods
        GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(2), /*SubOperand*/0, // src2
        GIR_AddImm8, /*InsnID*/0, /*Imm*/0,
        GIR_AddImm8, /*InsnID*/0, /*Imm*/0,
        GIR_ConstrainSelectedInstOperands, /*InsnID*/0,
        GIR_EraseFromParent, /*InsnID*/0,
        // GIR_Coverage, 6487,
        GIR_Done,
      // Label 5082: @369516
      GIM_Try, /*On fail goto*//*Label 5083*/ GIMT_Encode4(369656), // Rule ID 10075 //
        GIM_CheckRegBankForClass, /*MI*/0, /*Op*/0, /*RC*/GIMT_Encode2(AMDGPU::VGPR_32RegClassID),
        GIM_RecordInsn, /*DefineMI*/1, /*MI*/0, /*OpIdx*/1, // MIs[1]
        GIM_CheckOpcode, /*MI*/1, GIMT_Encode2(TargetOpcode::G_FMINNUM),
        GIM_CheckType, /*MI*/1, /*Op*/1, /*Type*/GILLT_s32,
        GIM_CheckType, /*MI*/1, /*Op*/2, /*Type*/GILLT_s32,
        GIM_RecordInsn, /*DefineMI*/2, /*MI*/0, /*OpIdx*/2, // MIs[2]
        GIM_CheckOpcode, /*MI*/2, GIMT_Encode2(TargetOpcode::G_FMINNUM_IEEE),
        GIM_CheckType, /*MI*/2, /*Op*/1, /*Type*/GILLT_s32,
        GIM_CheckType, /*MI*/2, /*Op*/2, /*Type*/GILLT_s32,
        GIM_RecordInsn, /*DefineMI*/3, /*MI*/2, /*OpIdx*/1, // MIs[3]
        GIM_CheckOpcode, /*MI*/3, GIMT_Encode2(TargetOpcode::G_FMAXNUM),
        // MIs[3] VOP3Mods:src1:src1_mods
        GIM_CheckIsSameOperand, /*MI*/3, /*OpIdx*/1, /*OtherMI*/1, /*OtherOpIdx*/2,
        // MIs[3] VOP3Mods:src0:src0_mods
        GIM_CheckIsSameOperand, /*MI*/3, /*OpIdx*/2, /*OtherMI*/1, /*OtherOpIdx*/1,
        GIM_CheckCxxInsnPredicate, /*MI*/0, /*FnId*/GIMT_Encode2(GICXXPred_MI_Predicate_fmaxnum_like_nnan),
        GIM_CheckIsSafeToFold, /*InsnID*/1,
        GIM_CheckIsSafeToFold, /*InsnID*/2,
        GIM_CheckIsSafeToFold, /*InsnID*/3,
        GIM_CheckComplexPattern, /*MI*/1, /*Op*/1, /*Renderer*/GIMT_Encode2(0), GIMT_Encode2(GICP_gi_vop3mods),
        GIM_CheckComplexPattern, /*MI*/1, /*Op*/2, /*Renderer*/GIMT_Encode2(1), GIMT_Encode2(GICP_gi_vop3mods),
        GIM_CheckComplexPattern, /*MI*/2, /*Op*/2, /*Renderer*/GIMT_Encode2(2), GIMT_Encode2(GICP_gi_vop3mods),
        // (fmaxnum_ieee:{ *:[f32] } (fminnum:{ *:[f32] } (VOP3Mods:{ *:[f32] } f32:{ *:[f32] }:$src0, i32:{ *:[i32] }:$src0_mods), (VOP3Mods:{ *:[f32] } f32:{ *:[f32] }:$src1, i32:{ *:[i32] }:$src1_mods)), (fminnum_ieee:{ *:[f32] } (fmaxnum:{ *:[f32] } (VOP3Mods:{ *:[f32] } f32:{ *:[f32] }:$src1, i32:{ *:[i32] }:$src1_mods), (VOP3Mods:{ *:[f32] } f32:{ *:[f32] }:$src0, i32:{ *:[i32] }:$src0_mods)), (VOP3Mods:{ *:[f32] } f32:{ *:[f32] }:$src2, i32:{ *:[i32] }:$src2_mods)))<<P:Predicate_fmaxnum_like_nnan>>  =>  (V_MED3_F32_e64:{ *:[f32] } ?:{ *:[i32] }:$src0_mods, ?:{ *:[f32] }:$src0, ?:{ *:[i32] }:$src1_mods, ?:{ *:[f32] }:$src1, ?:{ *:[i32] }:$src2_mods, ?:{ *:[f32] }:$src2, 0:{ *:[i1] }, 0:{ *:[i32] })
        GIR_BuildMI, /*InsnID*/0, /*Opcode*/GIMT_Encode2(AMDGPU::V_MED3_F32_e64),
        GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/0, // DstI[vdst]
        GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/1, // src0_mods
        GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/0, // src0
        GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(1), /*SubOperand*/1, // src1_mods
        GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(1), /*SubOperand*/0, // src1
        GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(2), /*SubOperand*/1, // src2_mods
        GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(2), /*SubOperand*/0, // src2
        GIR_AddImm8, /*InsnID*/0, /*Imm*/0,
        GIR_AddImm8, /*InsnID*/0, /*Imm*/0,
        GIR_ConstrainSelectedInstOperands, /*InsnID*/0,
        GIR_EraseFromParent, /*InsnID*/0,
        // GIR_Coverage, 10075,
        GIR_Done,
      // Label 5083: @369656
      GIM_Try, /*On fail goto*//*Label 5084*/ GIMT_Encode4(369796), // Rule ID 10078 //
        GIM_CheckRegBankForClass, /*MI*/0, /*Op*/0, /*RC*/GIMT_Encode2(AMDGPU::VGPR_32RegClassID),
        GIM_RecordInsn, /*DefineMI*/1, /*MI*/0, /*OpIdx*/1, // MIs[1]
        GIM_CheckOpcode, /*MI*/1, GIMT_Encode2(TargetOpcode::G_FMINNUM),
        GIM_CheckType, /*MI*/1, /*Op*/1, /*Type*/GILLT_s32,
        GIM_CheckType, /*MI*/1, /*Op*/2, /*Type*/GILLT_s32,
        GIM_RecordInsn, /*DefineMI*/2, /*MI*/0, /*OpIdx*/2, // MIs[2]
        GIM_CheckOpcode, /*MI*/2, GIMT_Encode2(TargetOpcode::G_FMINNUM_IEEE),
        GIM_CheckType, /*MI*/2, /*Op*/1, /*Type*/GILLT_s32,
        GIM_CheckType, /*MI*/2, /*Op*/2, /*Type*/GILLT_s32,
        GIM_RecordInsn, /*DefineMI*/3, /*MI*/2, /*OpIdx*/1, // MIs[3]
        GIM_CheckOpcode, /*MI*/3, GIMT_Encode2(TargetOpcode::G_FMAXNUM),
        // MIs[3] VOP3Mods:src0:src0_mods
        GIM_CheckIsSameOperand, /*MI*/3, /*OpIdx*/1, /*OtherMI*/1, /*OtherOpIdx*/2,
        // MIs[3] VOP3Mods:src1:src1_mods
        GIM_CheckIsSameOperand, /*MI*/3, /*OpIdx*/2, /*OtherMI*/1, /*OtherOpIdx*/1,
        GIM_CheckCxxInsnPredicate, /*MI*/0, /*FnId*/GIMT_Encode2(GICXXPred_MI_Predicate_fmaxnum_like_nnan),
        GIM_CheckIsSafeToFold, /*InsnID*/1,
        GIM_CheckIsSafeToFold, /*InsnID*/2,
        GIM_CheckIsSafeToFold, /*InsnID*/3,
        GIM_CheckComplexPattern, /*MI*/1, /*Op*/1, /*Renderer*/GIMT_Encode2(0), GIMT_Encode2(GICP_gi_vop3mods),
        GIM_CheckComplexPattern, /*MI*/1, /*Op*/2, /*Renderer*/GIMT_Encode2(1), GIMT_Encode2(GICP_gi_vop3mods),
        GIM_CheckComplexPattern, /*MI*/2, /*Op*/2, /*Renderer*/GIMT_Encode2(2), GIMT_Encode2(GICP_gi_vop3mods),
        // (fmaxnum_ieee:{ *:[f32] } (fminnum:{ *:[f32] } (VOP3Mods:{ *:[f32] } f32:{ *:[f32] }:$src1, i32:{ *:[i32] }:$src1_mods), (VOP3Mods:{ *:[f32] } f32:{ *:[f32] }:$src0, i32:{ *:[i32] }:$src0_mods)), (fminnum_ieee:{ *:[f32] } (fmaxnum:{ *:[f32] } (VOP3Mods:{ *:[f32] } f32:{ *:[f32] }:$src0, i32:{ *:[i32] }:$src0_mods), (VOP3Mods:{ *:[f32] } f32:{ *:[f32] }:$src1, i32:{ *:[i32] }:$src1_mods)), (VOP3Mods:{ *:[f32] } f32:{ *:[f32] }:$src2, i32:{ *:[i32] }:$src2_mods)))<<P:Predicate_fmaxnum_like_nnan>>  =>  (V_MED3_F32_e64:{ *:[f32] } ?:{ *:[i32] }:$src0_mods, ?:{ *:[f32] }:$src0, ?:{ *:[i32] }:$src1_mods, ?:{ *:[f32] }:$src1, ?:{ *:[i32] }:$src2_mods, ?:{ *:[f32] }:$src2, 0:{ *:[i1] }, 0:{ *:[i32] })
        GIR_BuildMI, /*InsnID*/0, /*Opcode*/GIMT_Encode2(AMDGPU::V_MED3_F32_e64),
        GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/0, // DstI[vdst]
        GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(1), /*SubOperand*/1, // src0_mods
        GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(1), /*SubOperand*/0, // src0
        GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/1, // src1_mods
        GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/0, // src1
        GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(2), /*SubOperand*/1, // src2_mods
        GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(2), /*SubOperand*/0, // src2
        GIR_AddImm8, /*InsnID*/0, /*Imm*/0,
        GIR_AddImm8, /*InsnID*/0, /*Imm*/0,
        GIR_ConstrainSelectedInstOperands, /*InsnID*/0,
        GIR_EraseFromParent, /*InsnID*/0,
        // GIR_Coverage, 10078,
        GIR_Done,
      // Label 5084: @369796
      GIM_Try, /*On fail goto*//*Label 5085*/ GIMT_Encode4(369936), // Rule ID 10079 //
        GIM_CheckRegBankForClass, /*MI*/0, /*Op*/0, /*RC*/GIMT_Encode2(AMDGPU::VGPR_32RegClassID),
        GIM_RecordInsn, /*DefineMI*/1, /*MI*/0, /*OpIdx*/1, // MIs[1]
        GIM_CheckOpcode, /*MI*/1, GIMT_Encode2(TargetOpcode::G_FMINNUM),
        GIM_CheckType, /*MI*/1, /*Op*/1, /*Type*/GILLT_s32,
        GIM_CheckType, /*MI*/1, /*Op*/2, /*Type*/GILLT_s32,
        GIM_RecordInsn, /*DefineMI*/2, /*MI*/0, /*OpIdx*/2, // MIs[2]
        GIM_CheckOpcode, /*MI*/2, GIMT_Encode2(TargetOpcode::G_FMINNUM_IEEE),
        GIM_CheckType, /*MI*/2, /*Op*/1, /*Type*/GILLT_s32,
        GIM_CheckType, /*MI*/2, /*Op*/2, /*Type*/GILLT_s32,
        GIM_RecordInsn, /*DefineMI*/3, /*MI*/2, /*OpIdx*/1, // MIs[3]
        GIM_CheckOpcode, /*MI*/3, GIMT_Encode2(TargetOpcode::G_FMAXNUM),
        // MIs[3] VOP3Mods:src1:src1_mods
        GIM_CheckIsSameOperand, /*MI*/3, /*OpIdx*/1, /*OtherMI*/1, /*OtherOpIdx*/1,
        // MIs[3] VOP3Mods:src0:src0_mods
        GIM_CheckIsSameOperand, /*MI*/3, /*OpIdx*/2, /*OtherMI*/1, /*OtherOpIdx*/2,
        GIM_CheckCxxInsnPredicate, /*MI*/0, /*FnId*/GIMT_Encode2(GICXXPred_MI_Predicate_fmaxnum_like_nnan),
        GIM_CheckIsSafeToFold, /*InsnID*/1,
        GIM_CheckIsSafeToFold, /*InsnID*/2,
        GIM_CheckIsSafeToFold, /*InsnID*/3,
        GIM_CheckComplexPattern, /*MI*/1, /*Op*/1, /*Renderer*/GIMT_Encode2(0), GIMT_Encode2(GICP_gi_vop3mods),
        GIM_CheckComplexPattern, /*MI*/1, /*Op*/2, /*Renderer*/GIMT_Encode2(1), GIMT_Encode2(GICP_gi_vop3mods),
        GIM_CheckComplexPattern, /*MI*/2, /*Op*/2, /*Renderer*/GIMT_Encode2(2), GIMT_Encode2(GICP_gi_vop3mods),
        // (fmaxnum_ieee:{ *:[f32] } (fminnum:{ *:[f32] } (VOP3Mods:{ *:[f32] } f32:{ *:[f32] }:$src1, i32:{ *:[i32] }:$src1_mods), (VOP3Mods:{ *:[f32] } f32:{ *:[f32] }:$src0, i32:{ *:[i32] }:$src0_mods)), (fminnum_ieee:{ *:[f32] } (fmaxnum:{ *:[f32] } (VOP3Mods:{ *:[f32] } f32:{ *:[f32] }:$src1, i32:{ *:[i32] }:$src1_mods), (VOP3Mods:{ *:[f32] } f32:{ *:[f32] }:$src0, i32:{ *:[i32] }:$src0_mods)), (VOP3Mods:{ *:[f32] } f32:{ *:[f32] }:$src2, i32:{ *:[i32] }:$src2_mods)))<<P:Predicate_fmaxnum_like_nnan>>  =>  (V_MED3_F32_e64:{ *:[f32] } ?:{ *:[i32] }:$src0_mods, ?:{ *:[f32] }:$src0, ?:{ *:[i32] }:$src1_mods, ?:{ *:[f32] }:$src1, ?:{ *:[i32] }:$src2_mods, ?:{ *:[f32] }:$src2, 0:{ *:[i1] }, 0:{ *:[i32] })
        GIR_BuildMI, /*InsnID*/0, /*Opcode*/GIMT_Encode2(AMDGPU::V_MED3_F32_e64),
        GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/0, // DstI[vdst]
        GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(1), /*SubOperand*/1, // src0_mods
        GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(1), /*SubOperand*/0, // src0
        GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/1, // src1_mods
        GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/0, // src1
        GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(2), /*SubOperand*/1, // src2_mods
        GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(2), /*SubOperand*/0, // src2
        GIR_AddImm8, /*InsnID*/0, /*Imm*/0,
        GIR_AddImm8, /*InsnID*/0, /*Imm*/0,
        GIR_ConstrainSelectedInstOperands, /*InsnID*/0,
        GIR_EraseFromParent, /*InsnID*/0,
        // GIR_Coverage, 10079,
        GIR_Done,
      // Label 5085: @369936
      GIM_Try, /*On fail goto*//*Label 5086*/ GIMT_Encode4(370076), // Rule ID 6486 //
        GIM_CheckRegBankForClass, /*MI*/0, /*Op*/0, /*RC*/GIMT_Encode2(AMDGPU::VGPR_32RegClassID),
        GIM_RecordInsn, /*DefineMI*/1, /*MI*/0, /*OpIdx*/1, // MIs[1]
        GIM_CheckOpcode, /*MI*/1, GIMT_Encode2(TargetOpcode::G_FMINNUM),
        GIM_CheckType, /*MI*/1, /*Op*/1, /*Type*/GILLT_s32,
        GIM_CheckType, /*MI*/1, /*Op*/2, /*Type*/GILLT_s32,
        GIM_RecordInsn, /*DefineMI*/2, /*MI*/0, /*OpIdx*/2, // MIs[2]
        GIM_CheckOpcode, /*MI*/2, GIMT_Encode2(TargetOpcode::G_FMINNUM_IEEE),
        GIM_CheckType, /*MI*/2, /*Op*/1, /*Type*/GILLT_s32,
        GIM_CheckType, /*MI*/2, /*Op*/2, /*Type*/GILLT_s32,
        GIM_RecordInsn, /*DefineMI*/3, /*MI*/2, /*OpIdx*/1, // MIs[3]
        GIM_CheckOpcode, /*MI*/3, GIMT_Encode2(TargetOpcode::G_FMAXNUM_IEEE),
        // MIs[3] VOP3Mods:src0:src0_mods
        GIM_CheckIsSameOperand, /*MI*/3, /*OpIdx*/1, /*OtherMI*/1, /*OtherOpIdx*/1,
        // MIs[3] VOP3Mods:src1:src1_mods
        GIM_CheckIsSameOperand, /*MI*/3, /*OpIdx*/2, /*OtherMI*/1, /*OtherOpIdx*/2,
        GIM_CheckCxxInsnPredicate, /*MI*/0, /*FnId*/GIMT_Encode2(GICXXPred_MI_Predicate_fmaxnum_like_nnan),
        GIM_CheckIsSafeToFold, /*InsnID*/1,
        GIM_CheckIsSafeToFold, /*InsnID*/2,
        GIM_CheckIsSafeToFold, /*InsnID*/3,
        GIM_CheckComplexPattern, /*MI*/1, /*Op*/1, /*Renderer*/GIMT_Encode2(0), GIMT_Encode2(GICP_gi_vop3mods),
        GIM_CheckComplexPattern, /*MI*/1, /*Op*/2, /*Renderer*/GIMT_Encode2(1), GIMT_Encode2(GICP_gi_vop3mods),
        GIM_CheckComplexPattern, /*MI*/2, /*Op*/2, /*Renderer*/GIMT_Encode2(2), GIMT_Encode2(GICP_gi_vop3mods),
        // (fmaxnum_ieee:{ *:[f32] } (fminnum:{ *:[f32] } (VOP3Mods:{ *:[f32] } f32:{ *:[f32] }:$src0, i32:{ *:[i32] }:$src0_mods), (VOP3Mods:{ *:[f32] } f32:{ *:[f32] }:$src1, i32:{ *:[i32] }:$src1_mods)), (fminnum_ieee:{ *:[f32] } (fmaxnum_ieee:{ *:[f32] } (VOP3Mods:{ *:[f32] } f32:{ *:[f32] }:$src0, i32:{ *:[i32] }:$src0_mods), (VOP3Mods:{ *:[f32] } f32:{ *:[f32] }:$src1, i32:{ *:[i32] }:$src1_mods)), (VOP3Mods:{ *:[f32] } f32:{ *:[f32] }:$src2, i32:{ *:[i32] }:$src2_mods)))<<P:Predicate_fmaxnum_like_nnan>>  =>  (V_MED3_F32_e64:{ *:[f32] } ?:{ *:[i32] }:$src0_mods, ?:{ *:[f32] }:$src0, ?:{ *:[i32] }:$src1_mods, ?:{ *:[f32] }:$src1, ?:{ *:[i32] }:$src2_mods, ?:{ *:[f32] }:$src2, 0:{ *:[i1] }, 0:{ *:[i32] })
        GIR_BuildMI, /*InsnID*/0, /*Opcode*/GIMT_Encode2(AMDGPU::V_MED3_F32_e64),
        GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/0, // DstI[vdst]
        GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/1, // src0_mods
        GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/0, // src0
        GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(1), /*SubOperand*/1, // src1_mods
        GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(1), /*SubOperand*/0, // src1
        GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(2), /*SubOperand*/1, // src2_mods
        GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(2), /*SubOperand*/0, // src2
        GIR_AddImm8, /*InsnID*/0, /*Imm*/0,
        GIR_AddImm8, /*InsnID*/0, /*Imm*/0,
        GIR_ConstrainSelectedInstOperands, /*InsnID*/0,
        GIR_EraseFromParent, /*InsnID*/0,
        // GIR_Coverage, 6486,
        GIR_Done,
      // Label 5086: @370076
      GIM_Try, /*On fail goto*//*Label 5087*/ GIMT_Encode4(370216), // Rule ID 10060 //
        GIM_CheckRegBankForClass, /*MI*/0, /*Op*/0, /*RC*/GIMT_Encode2(AMDGPU::VGPR_32RegClassID),
        GIM_RecordInsn, /*DefineMI*/1, /*MI*/0, /*OpIdx*/1, // MIs[1]
        GIM_CheckOpcode, /*MI*/1, GIMT_Encode2(TargetOpcode::G_FMINNUM),
        GIM_CheckType, /*MI*/1, /*Op*/1, /*Type*/GILLT_s32,
        GIM_CheckType, /*MI*/1, /*Op*/2, /*Type*/GILLT_s32,
        GIM_RecordInsn, /*DefineMI*/2, /*MI*/0, /*OpIdx*/2, // MIs[2]
        GIM_CheckOpcode, /*MI*/2, GIMT_Encode2(TargetOpcode::G_FMINNUM_IEEE),
        GIM_CheckType, /*MI*/2, /*Op*/1, /*Type*/GILLT_s32,
        GIM_CheckType, /*MI*/2, /*Op*/2, /*Type*/GILLT_s32,
        GIM_RecordInsn, /*DefineMI*/3, /*MI*/2, /*OpIdx*/1, // MIs[3]
        GIM_CheckOpcode, /*MI*/3, GIMT_Encode2(TargetOpcode::G_FMAXNUM_IEEE),
        // MIs[3] VOP3Mods:src1:src1_mods
        GIM_CheckIsSameOperand, /*MI*/3, /*OpIdx*/1, /*OtherMI*/1, /*OtherOpIdx*/2,
        // MIs[3] VOP3Mods:src0:src0_mods
        GIM_CheckIsSameOperand, /*MI*/3, /*OpIdx*/2, /*OtherMI*/1, /*OtherOpIdx*/1,
        GIM_CheckCxxInsnPredicate, /*MI*/0, /*FnId*/GIMT_Encode2(GICXXPred_MI_Predicate_fmaxnum_like_nnan),
        GIM_CheckIsSafeToFold, /*InsnID*/1,
        GIM_CheckIsSafeToFold, /*InsnID*/2,
        GIM_CheckIsSafeToFold, /*InsnID*/3,
        GIM_CheckComplexPattern, /*MI*/1, /*Op*/1, /*Renderer*/GIMT_Encode2(0), GIMT_Encode2(GICP_gi_vop3mods),
        GIM_CheckComplexPattern, /*MI*/1, /*Op*/2, /*Renderer*/GIMT_Encode2(1), GIMT_Encode2(GICP_gi_vop3mods),
        GIM_CheckComplexPattern, /*MI*/2, /*Op*/2, /*Renderer*/GIMT_Encode2(2), GIMT_Encode2(GICP_gi_vop3mods),
        // (fmaxnum_ieee:{ *:[f32] } (fminnum:{ *:[f32] } (VOP3Mods:{ *:[f32] } f32:{ *:[f32] }:$src0, i32:{ *:[i32] }:$src0_mods), (VOP3Mods:{ *:[f32] } f32:{ *:[f32] }:$src1, i32:{ *:[i32] }:$src1_mods)), (fminnum_ieee:{ *:[f32] } (fmaxnum_ieee:{ *:[f32] } (VOP3Mods:{ *:[f32] } f32:{ *:[f32] }:$src1, i32:{ *:[i32] }:$src1_mods), (VOP3Mods:{ *:[f32] } f32:{ *:[f32] }:$src0, i32:{ *:[i32] }:$src0_mods)), (VOP3Mods:{ *:[f32] } f32:{ *:[f32] }:$src2, i32:{ *:[i32] }:$src2_mods)))<<P:Predicate_fmaxnum_like_nnan>>  =>  (V_MED3_F32_e64:{ *:[f32] } ?:{ *:[i32] }:$src0_mods, ?:{ *:[f32] }:$src0, ?:{ *:[i32] }:$src1_mods, ?:{ *:[f32] }:$src1, ?:{ *:[i32] }:$src2_mods, ?:{ *:[f32] }:$src2, 0:{ *:[i1] }, 0:{ *:[i32] })
        GIR_BuildMI, /*InsnID*/0, /*Opcode*/GIMT_Encode2(AMDGPU::V_MED3_F32_e64),
        GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/0, // DstI[vdst]
        GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/1, // src0_mods
        GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/0, // src0
        GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(1), /*SubOperand*/1, // src1_mods
        GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(1), /*SubOperand*/0, // src1
        GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(2), /*SubOperand*/1, // src2_mods
        GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(2), /*SubOperand*/0, // src2
        GIR_AddImm8, /*InsnID*/0, /*Imm*/0,
        GIR_AddImm8, /*InsnID*/0, /*Imm*/0,
        GIR_ConstrainSelectedInstOperands, /*InsnID*/0,
        GIR_EraseFromParent, /*InsnID*/0,
        // GIR_Coverage, 10060,
        GIR_Done,
      // Label 5087: @370216
      GIM_Try, /*On fail goto*//*Label 5088*/ GIMT_Encode4(370356), // Rule ID 10063 //
        GIM_CheckRegBankForClass, /*MI*/0, /*Op*/0, /*RC*/GIMT_Encode2(AMDGPU::VGPR_32RegClassID),
        GIM_RecordInsn, /*DefineMI*/1, /*MI*/0, /*OpIdx*/1, // MIs[1]
        GIM_CheckOpcode, /*MI*/1, GIMT_Encode2(TargetOpcode::G_FMINNUM),
        GIM_CheckType, /*MI*/1, /*Op*/1, /*Type*/GILLT_s32,
        GIM_CheckType, /*MI*/1, /*Op*/2, /*Type*/GILLT_s32,
        GIM_RecordInsn, /*DefineMI*/2, /*MI*/0, /*OpIdx*/2, // MIs[2]
        GIM_CheckOpcode, /*MI*/2, GIMT_Encode2(TargetOpcode::G_FMINNUM_IEEE),
        GIM_CheckType, /*MI*/2, /*Op*/1, /*Type*/GILLT_s32,
        GIM_CheckType, /*MI*/2, /*Op*/2, /*Type*/GILLT_s32,
        GIM_RecordInsn, /*DefineMI*/3, /*MI*/2, /*OpIdx*/1, // MIs[3]
        GIM_CheckOpcode, /*MI*/3, GIMT_Encode2(TargetOpcode::G_FMAXNUM_IEEE),
        // MIs[3] VOP3Mods:src0:src0_mods
        GIM_CheckIsSameOperand, /*MI*/3, /*OpIdx*/1, /*OtherMI*/1, /*OtherOpIdx*/2,
        // MIs[3] VOP3Mods:src1:src1_mods
        GIM_CheckIsSameOperand, /*MI*/3, /*OpIdx*/2, /*OtherMI*/1, /*OtherOpIdx*/1,
        GIM_CheckCxxInsnPredicate, /*MI*/0, /*FnId*/GIMT_Encode2(GICXXPred_MI_Predicate_fmaxnum_like_nnan),
        GIM_CheckIsSafeToFold, /*InsnID*/1,
        GIM_CheckIsSafeToFold, /*InsnID*/2,
        GIM_CheckIsSafeToFold, /*InsnID*/3,
        GIM_CheckComplexPattern, /*MI*/1, /*Op*/1, /*Renderer*/GIMT_Encode2(0), GIMT_Encode2(GICP_gi_vop3mods),
        GIM_CheckComplexPattern, /*MI*/1, /*Op*/2, /*Renderer*/GIMT_Encode2(1), GIMT_Encode2(GICP_gi_vop3mods),
        GIM_CheckComplexPattern, /*MI*/2, /*Op*/2, /*Renderer*/GIMT_Encode2(2), GIMT_Encode2(GICP_gi_vop3mods),
        // (fmaxnum_ieee:{ *:[f32] } (fminnum:{ *:[f32] } (VOP3Mods:{ *:[f32] } f32:{ *:[f32] }:$src1, i32:{ *:[i32] }:$src1_mods), (VOP3Mods:{ *:[f32] } f32:{ *:[f32] }:$src0, i32:{ *:[i32] }:$src0_mods)), (fminnum_ieee:{ *:[f32] } (fmaxnum_ieee:{ *:[f32] } (VOP3Mods:{ *:[f32] } f32:{ *:[f32] }:$src0, i32:{ *:[i32] }:$src0_mods), (VOP3Mods:{ *:[f32] } f32:{ *:[f32] }:$src1, i32:{ *:[i32] }:$src1_mods)), (VOP3Mods:{ *:[f32] } f32:{ *:[f32] }:$src2, i32:{ *:[i32] }:$src2_mods)))<<P:Predicate_fmaxnum_like_nnan>>  =>  (V_MED3_F32_e64:{ *:[f32] } ?:{ *:[i32] }:$src0_mods, ?:{ *:[f32] }:$src0, ?:{ *:[i32] }:$src1_mods, ?:{ *:[f32] }:$src1, ?:{ *:[i32] }:$src2_mods, ?:{ *:[f32] }:$src2, 0:{ *:[i1] }, 0:{ *:[i32] })
        GIR_BuildMI, /*InsnID*/0, /*Opcode*/GIMT_Encode2(AMDGPU::V_MED3_F32_e64),
        GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/0, // DstI[vdst]
        GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(1), /*SubOperand*/1, // src0_mods
        GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(1), /*SubOperand*/0, // src0
        GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/1, // src1_mods
        GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/0, // src1
        GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(2), /*SubOperand*/1, // src2_mods
        GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(2), /*SubOperand*/0, // src2
        GIR_AddImm8, /*InsnID*/0, /*Imm*/0,
        GIR_AddImm8, /*InsnID*/0, /*Imm*/0,
        GIR_ConstrainSelectedInstOperands, /*InsnID*/0,
        GIR_EraseFromParent, /*InsnID*/0,
        // GIR_Coverage, 10063,
        GIR_Done,
      // Label 5088: @370356
      GIM_Try, /*On fail goto*//*Label 5089*/ GIMT_Encode4(370496), // Rule ID 10064 //
        GIM_CheckRegBankForClass, /*MI*/0, /*Op*/0, /*RC*/GIMT_Encode2(AMDGPU::VGPR_32RegClassID),
        GIM_RecordInsn, /*DefineMI*/1, /*MI*/0, /*OpIdx*/1, // MIs[1]
        GIM_CheckOpcode, /*MI*/1, GIMT_Encode2(TargetOpcode::G_FMINNUM),
        GIM_CheckType, /*MI*/1, /*Op*/1, /*Type*/GILLT_s32,
        GIM_CheckType, /*MI*/1, /*Op*/2, /*Type*/GILLT_s32,
        GIM_RecordInsn, /*DefineMI*/2, /*MI*/0, /*OpIdx*/2, // MIs[2]
        GIM_CheckOpcode, /*MI*/2, GIMT_Encode2(TargetOpcode::G_FMINNUM_IEEE),
        GIM_CheckType, /*MI*/2, /*Op*/1, /*Type*/GILLT_s32,
        GIM_CheckType, /*MI*/2, /*Op*/2, /*Type*/GILLT_s32,
        GIM_RecordInsn, /*DefineMI*/3, /*MI*/2, /*OpIdx*/1, // MIs[3]
        GIM_CheckOpcode, /*MI*/3, GIMT_Encode2(TargetOpcode::G_FMAXNUM_IEEE),
        // MIs[3] VOP3Mods:src1:src1_mods
        GIM_CheckIsSameOperand, /*MI*/3, /*OpIdx*/1, /*OtherMI*/1, /*OtherOpIdx*/1,
        // MIs[3] VOP3Mods:src0:src0_mods
        GIM_CheckIsSameOperand, /*MI*/3, /*OpIdx*/2, /*OtherMI*/1, /*OtherOpIdx*/2,
        GIM_CheckCxxInsnPredicate, /*MI*/0, /*FnId*/GIMT_Encode2(GICXXPred_MI_Predicate_fmaxnum_like_nnan),
        GIM_CheckIsSafeToFold, /*InsnID*/1,
        GIM_CheckIsSafeToFold, /*InsnID*/2,
        GIM_CheckIsSafeToFold, /*InsnID*/3,
        GIM_CheckComplexPattern, /*MI*/1, /*Op*/1, /*Renderer*/GIMT_Encode2(0), GIMT_Encode2(GICP_gi_vop3mods),
        GIM_CheckComplexPattern, /*MI*/1, /*Op*/2, /*Renderer*/GIMT_Encode2(1), GIMT_Encode2(GICP_gi_vop3mods),
        GIM_CheckComplexPattern, /*MI*/2, /*Op*/2, /*Renderer*/GIMT_Encode2(2), GIMT_Encode2(GICP_gi_vop3mods),
        // (fmaxnum_ieee:{ *:[f32] } (fminnum:{ *:[f32] } (VOP3Mods:{ *:[f32] } f32:{ *:[f32] }:$src1, i32:{ *:[i32] }:$src1_mods), (VOP3Mods:{ *:[f32] } f32:{ *:[f32] }:$src0, i32:{ *:[i32] }:$src0_mods)), (fminnum_ieee:{ *:[f32] } (fmaxnum_ieee:{ *:[f32] } (VOP3Mods:{ *:[f32] } f32:{ *:[f32] }:$src1, i32:{ *:[i32] }:$src1_mods), (VOP3Mods:{ *:[f32] } f32:{ *:[f32] }:$src0, i32:{ *:[i32] }:$src0_mods)), (VOP3Mods:{ *:[f32] } f32:{ *:[f32] }:$src2, i32:{ *:[i32] }:$src2_mods)))<<P:Predicate_fmaxnum_like_nnan>>  =>  (V_MED3_F32_e64:{ *:[f32] } ?:{ *:[i32] }:$src0_mods, ?:{ *:[f32] }:$src0, ?:{ *:[i32] }:$src1_mods, ?:{ *:[f32] }:$src1, ?:{ *:[i32] }:$src2_mods, ?:{ *:[f32] }:$src2, 0:{ *:[i1] }, 0:{ *:[i32] })
        GIR_BuildMI, /*InsnID*/0, /*Opcode*/GIMT_Encode2(AMDGPU::V_MED3_F32_e64),
        GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/0, // DstI[vdst]
        GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(1), /*SubOperand*/1, // src0_mods
        GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(1), /*SubOperand*/0, // src0
        GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/1, // src1_mods
        GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/0, // src1
        GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(2), /*SubOperand*/1, // src2_mods
        GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(2), /*SubOperand*/0, // src2
        GIR_AddImm8, /*InsnID*/0, /*Imm*/0,
        GIR_AddImm8, /*InsnID*/0, /*Imm*/0,
        GIR_ConstrainSelectedInstOperands, /*InsnID*/0,
        GIR_EraseFromParent, /*InsnID*/0,
        // GIR_Coverage, 10064,
        GIR_Done,
      // Label 5089: @370496
      GIM_Try, /*On fail goto*//*Label 5090*/ GIMT_Encode4(370636), // Rule ID 10116 //
        GIM_CheckRegBankForClass, /*MI*/0, /*Op*/0, /*RC*/GIMT_Encode2(AMDGPU::VGPR_32RegClassID),
        GIM_RecordInsn, /*DefineMI*/1, /*MI*/0, /*OpIdx*/1, // MIs[1]
        GIM_CheckOpcode, /*MI*/1, GIMT_Encode2(TargetOpcode::G_FMINNUM),
        GIM_CheckType, /*MI*/1, /*Op*/1, /*Type*/GILLT_s32,
        GIM_CheckType, /*MI*/1, /*Op*/2, /*Type*/GILLT_s32,
        GIM_RecordInsn, /*DefineMI*/2, /*MI*/1, /*OpIdx*/2, // MIs[2]
        GIM_CheckOpcode, /*MI*/2, GIMT_Encode2(TargetOpcode::G_FMAXNUM),
        GIM_CheckType, /*MI*/2, /*Op*/1, /*Type*/GILLT_s32,
        GIM_CheckType, /*MI*/2, /*Op*/2, /*Type*/GILLT_s32,
        GIM_RecordInsn, /*DefineMI*/3, /*MI*/0, /*OpIdx*/2, // MIs[3]
        GIM_CheckOpcode, /*MI*/3, GIMT_Encode2(TargetOpcode::G_FMINNUM),
        // MIs[3] VOP3Mods:src0:src0_mods
        GIM_CheckIsSameOperand, /*MI*/3, /*OpIdx*/1, /*OtherMI*/2, /*OtherOpIdx*/1,
        // MIs[3] VOP3Mods:src1:src1_mods
        GIM_CheckIsSameOperand, /*MI*/3, /*OpIdx*/2, /*OtherMI*/2, /*OtherOpIdx*/2,
        GIM_CheckCxxInsnPredicate, /*MI*/0, /*FnId*/GIMT_Encode2(GICXXPred_MI_Predicate_fmaxnum_like_nnan),
        GIM_CheckIsSafeToFold, /*InsnID*/1,
        GIM_CheckIsSafeToFold, /*InsnID*/2,
        GIM_CheckIsSafeToFold, /*InsnID*/3,
        GIM_CheckComplexPattern, /*MI*/1, /*Op*/1, /*Renderer*/GIMT_Encode2(0), GIMT_Encode2(GICP_gi_vop3mods),
        GIM_CheckComplexPattern, /*MI*/2, /*Op*/1, /*Renderer*/GIMT_Encode2(1), GIMT_Encode2(GICP_gi_vop3mods),
        GIM_CheckComplexPattern, /*MI*/2, /*Op*/2, /*Renderer*/GIMT_Encode2(2), GIMT_Encode2(GICP_gi_vop3mods),
        // (fmaxnum_ieee:{ *:[f32] } (fminnum:{ *:[f32] } (VOP3Mods:{ *:[f32] } f32:{ *:[f32] }:$src2, i32:{ *:[i32] }:$src2_mods), (fmaxnum:{ *:[f32] } (VOP3Mods:{ *:[f32] } f32:{ *:[f32] }:$src0, i32:{ *:[i32] }:$src0_mods), (VOP3Mods:{ *:[f32] } f32:{ *:[f32] }:$src1, i32:{ *:[i32] }:$src1_mods))), (fminnum:{ *:[f32] } (VOP3Mods:{ *:[f32] } f32:{ *:[f32] }:$src0, i32:{ *:[i32] }:$src0_mods), (VOP3Mods:{ *:[f32] } f32:{ *:[f32] }:$src1, i32:{ *:[i32] }:$src1_mods)))<<P:Predicate_fmaxnum_like_nnan>>  =>  (V_MED3_F32_e64:{ *:[f32] } ?:{ *:[i32] }:$src0_mods, ?:{ *:[f32] }:$src0, ?:{ *:[i32] }:$src1_mods, ?:{ *:[f32] }:$src1, ?:{ *:[i32] }:$src2_mods, ?:{ *:[f32] }:$src2, 0:{ *:[i1] }, 0:{ *:[i32] })
        GIR_BuildMI, /*InsnID*/0, /*Opcode*/GIMT_Encode2(AMDGPU::V_MED3_F32_e64),
        GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/0, // DstI[vdst]
        GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(1), /*SubOperand*/1, // src0_mods
        GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(1), /*SubOperand*/0, // src0
        GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(2), /*SubOperand*/1, // src1_mods
        GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(2), /*SubOperand*/0, // src1
        GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/1, // src2_mods
        GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/0, // src2
        GIR_AddImm8, /*InsnID*/0, /*Imm*/0,
        GIR_AddImm8, /*InsnID*/0, /*Imm*/0,
        GIR_ConstrainSelectedInstOperands, /*InsnID*/0,
        GIR_EraseFromParent, /*InsnID*/0,
        // GIR_Coverage, 10116,
        GIR_Done,
      // Label 5090: @370636
      GIM_Try, /*On fail goto*//*Label 5091*/ GIMT_Encode4(370776), // Rule ID 10117 //
        GIM_CheckRegBankForClass, /*MI*/0, /*Op*/0, /*RC*/GIMT_Encode2(AMDGPU::VGPR_32RegClassID),
        GIM_RecordInsn, /*DefineMI*/1, /*MI*/0, /*OpIdx*/1, // MIs[1]
        GIM_CheckOpcode, /*MI*/1, GIMT_Encode2(TargetOpcode::G_FMINNUM),
        GIM_CheckType, /*MI*/1, /*Op*/1, /*Type*/GILLT_s32,
        GIM_CheckType, /*MI*/1, /*Op*/2, /*Type*/GILLT_s32,
        GIM_RecordInsn, /*DefineMI*/2, /*MI*/1, /*OpIdx*/2, // MIs[2]
        GIM_CheckOpcode, /*MI*/2, GIMT_Encode2(TargetOpcode::G_FMAXNUM),
        GIM_CheckType, /*MI*/2, /*Op*/1, /*Type*/GILLT_s32,
        GIM_CheckType, /*MI*/2, /*Op*/2, /*Type*/GILLT_s32,
        GIM_RecordInsn, /*DefineMI*/3, /*MI*/0, /*OpIdx*/2, // MIs[3]
        GIM_CheckOpcode, /*MI*/3, GIMT_Encode2(TargetOpcode::G_FMINNUM),
        // MIs[3] VOP3Mods:src1:src1_mods
        GIM_CheckIsSameOperand, /*MI*/3, /*OpIdx*/1, /*OtherMI*/2, /*OtherOpIdx*/2,
        // MIs[3] VOP3Mods:src0:src0_mods
        GIM_CheckIsSameOperand, /*MI*/3, /*OpIdx*/2, /*OtherMI*/2, /*OtherOpIdx*/1,
        GIM_CheckCxxInsnPredicate, /*MI*/0, /*FnId*/GIMT_Encode2(GICXXPred_MI_Predicate_fmaxnum_like_nnan),
        GIM_CheckIsSafeToFold, /*InsnID*/1,
        GIM_CheckIsSafeToFold, /*InsnID*/2,
        GIM_CheckIsSafeToFold, /*InsnID*/3,
        GIM_CheckComplexPattern, /*MI*/1, /*Op*/1, /*Renderer*/GIMT_Encode2(0), GIMT_Encode2(GICP_gi_vop3mods),
        GIM_CheckComplexPattern, /*MI*/2, /*Op*/1, /*Renderer*/GIMT_Encode2(1), GIMT_Encode2(GICP_gi_vop3mods),
        GIM_CheckComplexPattern, /*MI*/2, /*Op*/2, /*Renderer*/GIMT_Encode2(2), GIMT_Encode2(GICP_gi_vop3mods),
        // (fmaxnum_ieee:{ *:[f32] } (fminnum:{ *:[f32] } (VOP3Mods:{ *:[f32] } f32:{ *:[f32] }:$src2, i32:{ *:[i32] }:$src2_mods), (fmaxnum:{ *:[f32] } (VOP3Mods:{ *:[f32] } f32:{ *:[f32] }:$src0, i32:{ *:[i32] }:$src0_mods), (VOP3Mods:{ *:[f32] } f32:{ *:[f32] }:$src1, i32:{ *:[i32] }:$src1_mods))), (fminnum:{ *:[f32] } (VOP3Mods:{ *:[f32] } f32:{ *:[f32] }:$src1, i32:{ *:[i32] }:$src1_mods), (VOP3Mods:{ *:[f32] } f32:{ *:[f32] }:$src0, i32:{ *:[i32] }:$src0_mods)))<<P:Predicate_fmaxnum_like_nnan>>  =>  (V_MED3_F32_e64:{ *:[f32] } ?:{ *:[i32] }:$src0_mods, ?:{ *:[f32] }:$src0, ?:{ *:[i32] }:$src1_mods, ?:{ *:[f32] }:$src1, ?:{ *:[i32] }:$src2_mods, ?:{ *:[f32] }:$src2, 0:{ *:[i1] }, 0:{ *:[i32] })
        GIR_BuildMI, /*InsnID*/0, /*Opcode*/GIMT_Encode2(AMDGPU::V_MED3_F32_e64),
        GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/0, // DstI[vdst]
        GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(1), /*SubOperand*/1, // src0_mods
        GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(1), /*SubOperand*/0, // src0
        GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(2), /*SubOperand*/1, // src1_mods
        GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(2), /*SubOperand*/0, // src1
        GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/1, // src2_mods
        GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/0, // src2
        GIR_AddImm8, /*InsnID*/0, /*Imm*/0,
        GIR_AddImm8, /*InsnID*/0, /*Imm*/0,
        GIR_ConstrainSelectedInstOperands, /*InsnID*/0,
        GIR_EraseFromParent, /*InsnID*/0,
        // GIR_Coverage, 10117,
        GIR_Done,
      // Label 5091: @370776
      GIM_Try, /*On fail goto*//*Label 5092*/ GIMT_Encode4(370916), // Rule ID 10118 //
        GIM_CheckRegBankForClass, /*MI*/0, /*Op*/0, /*RC*/GIMT_Encode2(AMDGPU::VGPR_32RegClassID),
        GIM_RecordInsn, /*DefineMI*/1, /*MI*/0, /*OpIdx*/1, // MIs[1]
        GIM_CheckOpcode, /*MI*/1, GIMT_Encode2(TargetOpcode::G_FMINNUM),
        GIM_CheckType, /*MI*/1, /*Op*/1, /*Type*/GILLT_s32,
        GIM_CheckType, /*MI*/1, /*Op*/2, /*Type*/GILLT_s32,
        GIM_RecordInsn, /*DefineMI*/2, /*MI*/1, /*OpIdx*/2, // MIs[2]
        GIM_CheckOpcode, /*MI*/2, GIMT_Encode2(TargetOpcode::G_FMAXNUM),
        GIM_CheckType, /*MI*/2, /*Op*/1, /*Type*/GILLT_s32,
        GIM_CheckType, /*MI*/2, /*Op*/2, /*Type*/GILLT_s32,
        GIM_RecordInsn, /*DefineMI*/3, /*MI*/0, /*OpIdx*/2, // MIs[3]
        GIM_CheckOpcode, /*MI*/3, GIMT_Encode2(TargetOpcode::G_FMINNUM),
        // MIs[3] VOP3Mods:src0:src0_mods
        GIM_CheckIsSameOperand, /*MI*/3, /*OpIdx*/1, /*OtherMI*/2, /*OtherOpIdx*/2,
        // MIs[3] VOP3Mods:src1:src1_mods
        GIM_CheckIsSameOperand, /*MI*/3, /*OpIdx*/2, /*OtherMI*/2, /*OtherOpIdx*/1,
        GIM_CheckCxxInsnPredicate, /*MI*/0, /*FnId*/GIMT_Encode2(GICXXPred_MI_Predicate_fmaxnum_like_nnan),
        GIM_CheckIsSafeToFold, /*InsnID*/1,
        GIM_CheckIsSafeToFold, /*InsnID*/2,
        GIM_CheckIsSafeToFold, /*InsnID*/3,
        GIM_CheckComplexPattern, /*MI*/1, /*Op*/1, /*Renderer*/GIMT_Encode2(0), GIMT_Encode2(GICP_gi_vop3mods),
        GIM_CheckComplexPattern, /*MI*/2, /*Op*/1, /*Renderer*/GIMT_Encode2(1), GIMT_Encode2(GICP_gi_vop3mods),
        GIM_CheckComplexPattern, /*MI*/2, /*Op*/2, /*Renderer*/GIMT_Encode2(2), GIMT_Encode2(GICP_gi_vop3mods),
        // (fmaxnum_ieee:{ *:[f32] } (fminnum:{ *:[f32] } (VOP3Mods:{ *:[f32] } f32:{ *:[f32] }:$src2, i32:{ *:[i32] }:$src2_mods), (fmaxnum:{ *:[f32] } (VOP3Mods:{ *:[f32] } f32:{ *:[f32] }:$src1, i32:{ *:[i32] }:$src1_mods), (VOP3Mods:{ *:[f32] } f32:{ *:[f32] }:$src0, i32:{ *:[i32] }:$src0_mods))), (fminnum:{ *:[f32] } (VOP3Mods:{ *:[f32] } f32:{ *:[f32] }:$src0, i32:{ *:[i32] }:$src0_mods), (VOP3Mods:{ *:[f32] } f32:{ *:[f32] }:$src1, i32:{ *:[i32] }:$src1_mods)))<<P:Predicate_fmaxnum_like_nnan>>  =>  (V_MED3_F32_e64:{ *:[f32] } ?:{ *:[i32] }:$src0_mods, ?:{ *:[f32] }:$src0, ?:{ *:[i32] }:$src1_mods, ?:{ *:[f32] }:$src1, ?:{ *:[i32] }:$src2_mods, ?:{ *:[f32] }:$src2, 0:{ *:[i1] }, 0:{ *:[i32] })
        GIR_BuildMI, /*InsnID*/0, /*Opcode*/GIMT_Encode2(AMDGPU::V_MED3_F32_e64),
        GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/0, // DstI[vdst]
        GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(2), /*SubOperand*/1, // src0_mods
        GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(2), /*SubOperand*/0, // src0
        GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(1), /*SubOperand*/1, // src1_mods
        GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(1), /*SubOperand*/0, // src1
        GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/1, // src2_mods
        GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/0, // src2
        GIR_AddImm8, /*InsnID*/0, /*Imm*/0,
        GIR_AddImm8, /*InsnID*/0, /*Imm*/0,
        GIR_ConstrainSelectedInstOperands, /*InsnID*/0,
        GIR_EraseFromParent, /*InsnID*/0,
        // GIR_Coverage, 10118,
        GIR_Done,
      // Label 5092: @370916
      GIM_Try, /*On fail goto*//*Label 5093*/ GIMT_Encode4(371056), // Rule ID 10119 //
        GIM_CheckRegBankForClass, /*MI*/0, /*Op*/0, /*RC*/GIMT_Encode2(AMDGPU::VGPR_32RegClassID),
        GIM_RecordInsn, /*DefineMI*/1, /*MI*/0, /*OpIdx*/1, // MIs[1]
        GIM_CheckOpcode, /*MI*/1, GIMT_Encode2(TargetOpcode::G_FMINNUM),
        GIM_CheckType, /*MI*/1, /*Op*/1, /*Type*/GILLT_s32,
        GIM_CheckType, /*MI*/1, /*Op*/2, /*Type*/GILLT_s32,
        GIM_RecordInsn, /*DefineMI*/2, /*MI*/1, /*OpIdx*/2, // MIs[2]
        GIM_CheckOpcode, /*MI*/2, GIMT_Encode2(TargetOpcode::G_FMAXNUM),
        GIM_CheckType, /*MI*/2, /*Op*/1, /*Type*/GILLT_s32,
        GIM_CheckType, /*MI*/2, /*Op*/2, /*Type*/GILLT_s32,
        GIM_RecordInsn, /*DefineMI*/3, /*MI*/0, /*OpIdx*/2, // MIs[3]
        GIM_CheckOpcode, /*MI*/3, GIMT_Encode2(TargetOpcode::G_FMINNUM),
        // MIs[3] VOP3Mods:src1:src1_mods
        GIM_CheckIsSameOperand, /*MI*/3, /*OpIdx*/1, /*OtherMI*/2, /*OtherOpIdx*/1,
        // MIs[3] VOP3Mods:src0:src0_mods
        GIM_CheckIsSameOperand, /*MI*/3, /*OpIdx*/2, /*OtherMI*/2, /*OtherOpIdx*/2,
        GIM_CheckCxxInsnPredicate, /*MI*/0, /*FnId*/GIMT_Encode2(GICXXPred_MI_Predicate_fmaxnum_like_nnan),
        GIM_CheckIsSafeToFold, /*InsnID*/1,
        GIM_CheckIsSafeToFold, /*InsnID*/2,
        GIM_CheckIsSafeToFold, /*InsnID*/3,
        GIM_CheckComplexPattern, /*MI*/1, /*Op*/1, /*Renderer*/GIMT_Encode2(0), GIMT_Encode2(GICP_gi_vop3mods),
        GIM_CheckComplexPattern, /*MI*/2, /*Op*/1, /*Renderer*/GIMT_Encode2(1), GIMT_Encode2(GICP_gi_vop3mods),
        GIM_CheckComplexPattern, /*MI*/2, /*Op*/2, /*Renderer*/GIMT_Encode2(2), GIMT_Encode2(GICP_gi_vop3mods),
        // (fmaxnum_ieee:{ *:[f32] } (fminnum:{ *:[f32] } (VOP3Mods:{ *:[f32] } f32:{ *:[f32] }:$src2, i32:{ *:[i32] }:$src2_mods), (fmaxnum:{ *:[f32] } (VOP3Mods:{ *:[f32] } f32:{ *:[f32] }:$src1, i32:{ *:[i32] }:$src1_mods), (VOP3Mods:{ *:[f32] } f32:{ *:[f32] }:$src0, i32:{ *:[i32] }:$src0_mods))), (fminnum:{ *:[f32] } (VOP3Mods:{ *:[f32] } f32:{ *:[f32] }:$src1, i32:{ *:[i32] }:$src1_mods), (VOP3Mods:{ *:[f32] } f32:{ *:[f32] }:$src0, i32:{ *:[i32] }:$src0_mods)))<<P:Predicate_fmaxnum_like_nnan>>  =>  (V_MED3_F32_e64:{ *:[f32] } ?:{ *:[i32] }:$src0_mods, ?:{ *:[f32] }:$src0, ?:{ *:[i32] }:$src1_mods, ?:{ *:[f32] }:$src1, ?:{ *:[i32] }:$src2_mods, ?:{ *:[f32] }:$src2, 0:{ *:[i1] }, 0:{ *:[i32] })
        GIR_BuildMI, /*InsnID*/0, /*Opcode*/GIMT_Encode2(AMDGPU::V_MED3_F32_e64),
        GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/0, // DstI[vdst]
        GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(2), /*SubOperand*/1, // src0_mods
        GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(2), /*SubOperand*/0, // src0
        GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(1), /*SubOperand*/1, // src1_mods
        GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(1), /*SubOperand*/0, // src1
        GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/1, // src2_mods
        GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/0, // src2
        GIR_AddImm8, /*InsnID*/0, /*Imm*/0,
        GIR_AddImm8, /*InsnID*/0, /*Imm*/0,
        GIR_ConstrainSelectedInstOperands, /*InsnID*/0,
        GIR_EraseFromParent, /*InsnID*/0,
        // GIR_Coverage, 10119,
        GIR_Done,
      // Label 5093: @371056
      GIM_Try, /*On fail goto*//*Label 5094*/ GIMT_Encode4(371196), // Rule ID 10056 //
        GIM_CheckRegBankForClass, /*MI*/0, /*Op*/0, /*RC*/GIMT_Encode2(AMDGPU::VGPR_32RegClassID),
        GIM_RecordInsn, /*DefineMI*/1, /*MI*/0, /*OpIdx*/1, // MIs[1]
        GIM_CheckOpcode, /*MI*/1, GIMT_Encode2(TargetOpcode::G_FMINNUM),
        GIM_CheckType, /*MI*/1, /*Op*/1, /*Type*/GILLT_s32,
        GIM_CheckType, /*MI*/1, /*Op*/2, /*Type*/GILLT_s32,
        GIM_RecordInsn, /*DefineMI*/2, /*MI*/1, /*OpIdx*/2, // MIs[2]
        GIM_CheckOpcode, /*MI*/2, GIMT_Encode2(TargetOpcode::G_FMAXNUM),
        GIM_CheckType, /*MI*/2, /*Op*/1, /*Type*/GILLT_s32,
        GIM_CheckType, /*MI*/2, /*Op*/2, /*Type*/GILLT_s32,
        GIM_RecordInsn, /*DefineMI*/3, /*MI*/0, /*OpIdx*/2, // MIs[3]
        GIM_CheckOpcode, /*MI*/3, GIMT_Encode2(TargetOpcode::G_FMINNUM_IEEE),
        // MIs[3] VOP3Mods:src0:src0_mods
        GIM_CheckIsSameOperand, /*MI*/3, /*OpIdx*/1, /*OtherMI*/2, /*OtherOpIdx*/1,
        // MIs[3] VOP3Mods:src1:src1_mods
        GIM_CheckIsSameOperand, /*MI*/3, /*OpIdx*/2, /*OtherMI*/2, /*OtherOpIdx*/2,
        GIM_CheckCxxInsnPredicate, /*MI*/0, /*FnId*/GIMT_Encode2(GICXXPred_MI_Predicate_fmaxnum_like_nnan),
        GIM_CheckIsSafeToFold, /*InsnID*/1,
        GIM_CheckIsSafeToFold, /*InsnID*/2,
        GIM_CheckIsSafeToFold, /*InsnID*/3,
        GIM_CheckComplexPattern, /*MI*/1, /*Op*/1, /*Renderer*/GIMT_Encode2(0), GIMT_Encode2(GICP_gi_vop3mods),
        GIM_CheckComplexPattern, /*MI*/2, /*Op*/1, /*Renderer*/GIMT_Encode2(1), GIMT_Encode2(GICP_gi_vop3mods),
        GIM_CheckComplexPattern, /*MI*/2, /*Op*/2, /*Renderer*/GIMT_Encode2(2), GIMT_Encode2(GICP_gi_vop3mods),
        // (fmaxnum_ieee:{ *:[f32] } (fminnum:{ *:[f32] } (VOP3Mods:{ *:[f32] } f32:{ *:[f32] }:$src2, i32:{ *:[i32] }:$src2_mods), (fmaxnum:{ *:[f32] } (VOP3Mods:{ *:[f32] } f32:{ *:[f32] }:$src0, i32:{ *:[i32] }:$src0_mods), (VOP3Mods:{ *:[f32] } f32:{ *:[f32] }:$src1, i32:{ *:[i32] }:$src1_mods))), (fminnum_ieee:{ *:[f32] } (VOP3Mods:{ *:[f32] } f32:{ *:[f32] }:$src0, i32:{ *:[i32] }:$src0_mods), (VOP3Mods:{ *:[f32] } f32:{ *:[f32] }:$src1, i32:{ *:[i32] }:$src1_mods)))<<P:Predicate_fmaxnum_like_nnan>>  =>  (V_MED3_F32_e64:{ *:[f32] } ?:{ *:[i32] }:$src0_mods, ?:{ *:[f32] }:$src0, ?:{ *:[i32] }:$src1_mods, ?:{ *:[f32] }:$src1, ?:{ *:[i32] }:$src2_mods, ?:{ *:[f32] }:$src2, 0:{ *:[i1] }, 0:{ *:[i32] })
        GIR_BuildMI, /*InsnID*/0, /*Opcode*/GIMT_Encode2(AMDGPU::V_MED3_F32_e64),
        GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/0, // DstI[vdst]
        GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(1), /*SubOperand*/1, // src0_mods
        GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(1), /*SubOperand*/0, // src0
        GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(2), /*SubOperand*/1, // src1_mods
        GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(2), /*SubOperand*/0, // src1
        GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/1, // src2_mods
        GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/0, // src2
        GIR_AddImm8, /*InsnID*/0, /*Imm*/0,
        GIR_AddImm8, /*InsnID*/0, /*Imm*/0,
        GIR_ConstrainSelectedInstOperands, /*InsnID*/0,
        GIR_EraseFromParent, /*InsnID*/0,
        // GIR_Coverage, 10056,
        GIR_Done,
      // Label 5094: @371196
      GIM_Try, /*On fail goto*//*Label 5095*/ GIMT_Encode4(371336), // Rule ID 10057 //
        GIM_CheckRegBankForClass, /*MI*/0, /*Op*/0, /*RC*/GIMT_Encode2(AMDGPU::VGPR_32RegClassID),
        GIM_RecordInsn, /*DefineMI*/1, /*MI*/0, /*OpIdx*/1, // MIs[1]
        GIM_CheckOpcode, /*MI*/1, GIMT_Encode2(TargetOpcode::G_FMINNUM),
        GIM_CheckType, /*MI*/1, /*Op*/1, /*Type*/GILLT_s32,
        GIM_CheckType, /*MI*/1, /*Op*/2, /*Type*/GILLT_s32,
        GIM_RecordInsn, /*DefineMI*/2, /*MI*/1, /*OpIdx*/2, // MIs[2]
        GIM_CheckOpcode, /*MI*/2, GIMT_Encode2(TargetOpcode::G_FMAXNUM),
        GIM_CheckType, /*MI*/2, /*Op*/1, /*Type*/GILLT_s32,
        GIM_CheckType, /*MI*/2, /*Op*/2, /*Type*/GILLT_s32,
        GIM_RecordInsn, /*DefineMI*/3, /*MI*/0, /*OpIdx*/2, // MIs[3]
        GIM_CheckOpcode, /*MI*/3, GIMT_Encode2(TargetOpcode::G_FMINNUM_IEEE),
        // MIs[3] VOP3Mods:src1:src1_mods
        GIM_CheckIsSameOperand, /*MI*/3, /*OpIdx*/1, /*OtherMI*/2, /*OtherOpIdx*/2,
        // MIs[3] VOP3Mods:src0:src0_mods
        GIM_CheckIsSameOperand, /*MI*/3, /*OpIdx*/2, /*OtherMI*/2, /*OtherOpIdx*/1,
        GIM_CheckCxxInsnPredicate, /*MI*/0, /*FnId*/GIMT_Encode2(GICXXPred_MI_Predicate_fmaxnum_like_nnan),
        GIM_CheckIsSafeToFold, /*InsnID*/1,
        GIM_CheckIsSafeToFold, /*InsnID*/2,
        GIM_CheckIsSafeToFold, /*InsnID*/3,
        GIM_CheckComplexPattern, /*MI*/1, /*Op*/1, /*Renderer*/GIMT_Encode2(0), GIMT_Encode2(GICP_gi_vop3mods),
        GIM_CheckComplexPattern, /*MI*/2, /*Op*/1, /*Renderer*/GIMT_Encode2(1), GIMT_Encode2(GICP_gi_vop3mods),
        GIM_CheckComplexPattern, /*MI*/2, /*Op*/2, /*Renderer*/GIMT_Encode2(2), GIMT_Encode2(GICP_gi_vop3mods),
        // (fmaxnum_ieee:{ *:[f32] } (fminnum:{ *:[f32] } (VOP3Mods:{ *:[f32] } f32:{ *:[f32] }:$src2, i32:{ *:[i32] }:$src2_mods), (fmaxnum:{ *:[f32] } (VOP3Mods:{ *:[f32] } f32:{ *:[f32] }:$src0, i32:{ *:[i32] }:$src0_mods), (VOP3Mods:{ *:[f32] } f32:{ *:[f32] }:$src1, i32:{ *:[i32] }:$src1_mods))), (fminnum_ieee:{ *:[f32] } (VOP3Mods:{ *:[f32] } f32:{ *:[f32] }:$src1, i32:{ *:[i32] }:$src1_mods), (VOP3Mods:{ *:[f32] } f32:{ *:[f32] }:$src0, i32:{ *:[i32] }:$src0_mods)))<<P:Predicate_fmaxnum_like_nnan>>  =>  (V_MED3_F32_e64:{ *:[f32] } ?:{ *:[i32] }:$src0_mods, ?:{ *:[f32] }:$src0, ?:{ *:[i32] }:$src1_mods, ?:{ *:[f32] }:$src1, ?:{ *:[i32] }:$src2_mods, ?:{ *:[f32] }:$src2, 0:{ *:[i1] }, 0:{ *:[i32] })
        GIR_BuildMI, /*InsnID*/0, /*Opcode*/GIMT_Encode2(AMDGPU::V_MED3_F32_e64),
        GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/0, // DstI[vdst]
        GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(1), /*SubOperand*/1, // src0_mods
        GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(1), /*SubOperand*/0, // src0
        GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(2), /*SubOperand*/1, // src1_mods
        GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(2), /*SubOperand*/0, // src1
        GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/1, // src2_mods
        GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/0, // src2
        GIR_AddImm8, /*InsnID*/0, /*Imm*/0,
        GIR_AddImm8, /*InsnID*/0, /*Imm*/0,
        GIR_ConstrainSelectedInstOperands, /*InsnID*/0,
        GIR_EraseFromParent, /*InsnID*/0,
        // GIR_Coverage, 10057,
        GIR_Done,
      // Label 5095: @371336
      GIM_Try, /*On fail goto*//*Label 5096*/ GIMT_Encode4(371476), // Rule ID 10058 //
        GIM_CheckRegBankForClass, /*MI*/0, /*Op*/0, /*RC*/GIMT_Encode2(AMDGPU::VGPR_32RegClassID),
        GIM_RecordInsn, /*DefineMI*/1, /*MI*/0, /*OpIdx*/1, // MIs[1]
        GIM_CheckOpcode, /*MI*/1, GIMT_Encode2(TargetOpcode::G_FMINNUM),
        GIM_CheckType, /*MI*/1, /*Op*/1, /*Type*/GILLT_s32,
        GIM_CheckType, /*MI*/1, /*Op*/2, /*Type*/GILLT_s32,
        GIM_RecordInsn, /*DefineMI*/2, /*MI*/1, /*OpIdx*/2, // MIs[2]
        GIM_CheckOpcode, /*MI*/2, GIMT_Encode2(TargetOpcode::G_FMAXNUM),
        GIM_CheckType, /*MI*/2, /*Op*/1, /*Type*/GILLT_s32,
        GIM_CheckType, /*MI*/2, /*Op*/2, /*Type*/GILLT_s32,
        GIM_RecordInsn, /*DefineMI*/3, /*MI*/0, /*OpIdx*/2, // MIs[3]
        GIM_CheckOpcode, /*MI*/3, GIMT_Encode2(TargetOpcode::G_FMINNUM_IEEE),
        // MIs[3] VOP3Mods:src0:src0_mods
        GIM_CheckIsSameOperand, /*MI*/3, /*OpIdx*/1, /*OtherMI*/2, /*OtherOpIdx*/2,
        // MIs[3] VOP3Mods:src1:src1_mods
        GIM_CheckIsSameOperand, /*MI*/3, /*OpIdx*/2, /*OtherMI*/2, /*OtherOpIdx*/1,
        GIM_CheckCxxInsnPredicate, /*MI*/0, /*FnId*/GIMT_Encode2(GICXXPred_MI_Predicate_fmaxnum_like_nnan),
        GIM_CheckIsSafeToFold, /*InsnID*/1,
        GIM_CheckIsSafeToFold, /*InsnID*/2,
        GIM_CheckIsSafeToFold, /*InsnID*/3,
        GIM_CheckComplexPattern, /*MI*/1, /*Op*/1, /*Renderer*/GIMT_Encode2(0), GIMT_Encode2(GICP_gi_vop3mods),
        GIM_CheckComplexPattern, /*MI*/2, /*Op*/1, /*Renderer*/GIMT_Encode2(1), GIMT_Encode2(GICP_gi_vop3mods),
        GIM_CheckComplexPattern, /*MI*/2, /*Op*/2, /*Renderer*/GIMT_Encode2(2), GIMT_Encode2(GICP_gi_vop3mods),
        // (fmaxnum_ieee:{ *:[f32] } (fminnum:{ *:[f32] } (VOP3Mods:{ *:[f32] } f32:{ *:[f32] }:$src2, i32:{ *:[i32] }:$src2_mods), (fmaxnum:{ *:[f32] } (VOP3Mods:{ *:[f32] } f32:{ *:[f32] }:$src1, i32:{ *:[i32] }:$src1_mods), (VOP3Mods:{ *:[f32] } f32:{ *:[f32] }:$src0, i32:{ *:[i32] }:$src0_mods))), (fminnum_ieee:{ *:[f32] } (VOP3Mods:{ *:[f32] } f32:{ *:[f32] }:$src0, i32:{ *:[i32] }:$src0_mods), (VOP3Mods:{ *:[f32] } f32:{ *:[f32] }:$src1, i32:{ *:[i32] }:$src1_mods)))<<P:Predicate_fmaxnum_like_nnan>>  =>  (V_MED3_F32_e64:{ *:[f32] } ?:{ *:[i32] }:$src0_mods, ?:{ *:[f32] }:$src0, ?:{ *:[i32] }:$src1_mods, ?:{ *:[f32] }:$src1, ?:{ *:[i32] }:$src2_mods, ?:{ *:[f32] }:$src2, 0:{ *:[i1] }, 0:{ *:[i32] })
        GIR_BuildMI, /*InsnID*/0, /*Opcode*/GIMT_Encode2(AMDGPU::V_MED3_F32_e64),
        GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/0, // DstI[vdst]
        GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(2), /*SubOperand*/1, // src0_mods
        GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(2), /*SubOperand*/0, // src0
        GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(1), /*SubOperand*/1, // src1_mods
        GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(1), /*SubOperand*/0, // src1
        GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/1, // src2_mods
        GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/0, // src2
        GIR_AddImm8, /*InsnID*/0, /*Imm*/0,
        GIR_AddImm8, /*InsnID*/0, /*Imm*/0,
        GIR_ConstrainSelectedInstOperands, /*InsnID*/0,
        GIR_EraseFromParent, /*InsnID*/0,
        // GIR_Coverage, 10058,
        GIR_Done,
      // Label 5096: @371476
      GIM_Try, /*On fail goto*//*Label 5097*/ GIMT_Encode4(371616), // Rule ID 10059 //
        GIM_CheckRegBankForClass, /*MI*/0, /*Op*/0, /*RC*/GIMT_Encode2(AMDGPU::VGPR_32RegClassID),
        GIM_RecordInsn, /*DefineMI*/1, /*MI*/0, /*OpIdx*/1, // MIs[1]
        GIM_CheckOpcode, /*MI*/1, GIMT_Encode2(TargetOpcode::G_FMINNUM),
        GIM_CheckType, /*MI*/1, /*Op*/1, /*Type*/GILLT_s32,
        GIM_CheckType, /*MI*/1, /*Op*/2, /*Type*/GILLT_s32,
        GIM_RecordInsn, /*DefineMI*/2, /*MI*/1, /*OpIdx*/2, // MIs[2]
        GIM_CheckOpcode, /*MI*/2, GIMT_Encode2(TargetOpcode::G_FMAXNUM),
        GIM_CheckType, /*MI*/2, /*Op*/1, /*Type*/GILLT_s32,
        GIM_CheckType, /*MI*/2, /*Op*/2, /*Type*/GILLT_s32,
        GIM_RecordInsn, /*DefineMI*/3, /*MI*/0, /*OpIdx*/2, // MIs[3]
        GIM_CheckOpcode, /*MI*/3, GIMT_Encode2(TargetOpcode::G_FMINNUM_IEEE),
        // MIs[3] VOP3Mods:src1:src1_mods
        GIM_CheckIsSameOperand, /*MI*/3, /*OpIdx*/1, /*OtherMI*/2, /*OtherOpIdx*/1,
        // MIs[3] VOP3Mods:src0:src0_mods
        GIM_CheckIsSameOperand, /*MI*/3, /*OpIdx*/2, /*OtherMI*/2, /*OtherOpIdx*/2,
        GIM_CheckCxxInsnPredicate, /*MI*/0, /*FnId*/GIMT_Encode2(GICXXPred_MI_Predicate_fmaxnum_like_nnan),
        GIM_CheckIsSafeToFold, /*InsnID*/1,
        GIM_CheckIsSafeToFold, /*InsnID*/2,
        GIM_CheckIsSafeToFold, /*InsnID*/3,
        GIM_CheckComplexPattern, /*MI*/1, /*Op*/1, /*Renderer*/GIMT_Encode2(0), GIMT_Encode2(GICP_gi_vop3mods),
        GIM_CheckComplexPattern, /*MI*/2, /*Op*/1, /*Renderer*/GIMT_Encode2(1), GIMT_Encode2(GICP_gi_vop3mods),
        GIM_CheckComplexPattern, /*MI*/2, /*Op*/2, /*Renderer*/GIMT_Encode2(2), GIMT_Encode2(GICP_gi_vop3mods),
        // (fmaxnum_ieee:{ *:[f32] } (fminnum:{ *:[f32] } (VOP3Mods:{ *:[f32] } f32:{ *:[f32] }:$src2, i32:{ *:[i32] }:$src2_mods), (fmaxnum:{ *:[f32] } (VOP3Mods:{ *:[f32] } f32:{ *:[f32] }:$src1, i32:{ *:[i32] }:$src1_mods), (VOP3Mods:{ *:[f32] } f32:{ *:[f32] }:$src0, i32:{ *:[i32] }:$src0_mods))), (fminnum_ieee:{ *:[f32] } (VOP3Mods:{ *:[f32] } f32:{ *:[f32] }:$src1, i32:{ *:[i32] }:$src1_mods), (VOP3Mods:{ *:[f32] } f32:{ *:[f32] }:$src0, i32:{ *:[i32] }:$src0_mods)))<<P:Predicate_fmaxnum_like_nnan>>  =>  (V_MED3_F32_e64:{ *:[f32] } ?:{ *:[i32] }:$src0_mods, ?:{ *:[f32] }:$src0, ?:{ *:[i32] }:$src1_mods, ?:{ *:[f32] }:$src1, ?:{ *:[i32] }:$src2_mods, ?:{ *:[f32] }:$src2, 0:{ *:[i1] }, 0:{ *:[i32] })
        GIR_BuildMI, /*InsnID*/0, /*Opcode*/GIMT_Encode2(AMDGPU::V_MED3_F32_e64),
        GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/0, // DstI[vdst]
        GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(2), /*SubOperand*/1, // src0_mods
        GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(2), /*SubOperand*/0, // src0
        GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(1), /*SubOperand*/1, // src1_mods
        GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(1), /*SubOperand*/0, // src1
        GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/1, // src2_mods
        GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/0, // src2
        GIR_AddImm8, /*InsnID*/0, /*Imm*/0,
        GIR_AddImm8, /*InsnID*/0, /*Imm*/0,
        GIR_ConstrainSelectedInstOperands, /*InsnID*/0,
        GIR_EraseFromParent, /*InsnID*/0,
        // GIR_Coverage, 10059,
        GIR_Done,
      // Label 5097: @371616
      GIM_Try, /*On fail goto*//*Label 5098*/ GIMT_Encode4(371756), // Rule ID 10101 //
        GIM_CheckRegBankForClass, /*MI*/0, /*Op*/0, /*RC*/GIMT_Encode2(AMDGPU::VGPR_32RegClassID),
        GIM_RecordInsn, /*DefineMI*/1, /*MI*/0, /*OpIdx*/1, // MIs[1]
        GIM_CheckOpcode, /*MI*/1, GIMT_Encode2(TargetOpcode::G_FMINNUM),
        GIM_CheckType, /*MI*/1, /*Op*/1, /*Type*/GILLT_s32,
        GIM_CheckType, /*MI*/1, /*Op*/2, /*Type*/GILLT_s32,
        GIM_RecordInsn, /*DefineMI*/2, /*MI*/1, /*OpIdx*/2, // MIs[2]
        GIM_CheckOpcode, /*MI*/2, GIMT_Encode2(TargetOpcode::G_FMAXNUM_IEEE),
        GIM_CheckType, /*MI*/2, /*Op*/1, /*Type*/GILLT_s32,
        GIM_CheckType, /*MI*/2, /*Op*/2, /*Type*/GILLT_s32,
        GIM_RecordInsn, /*DefineMI*/3, /*MI*/0, /*OpIdx*/2, // MIs[3]
        GIM_CheckOpcode, /*MI*/3, GIMT_Encode2(TargetOpcode::G_FMINNUM),
        // MIs[3] VOP3Mods:src0:src0_mods
        GIM_CheckIsSameOperand, /*MI*/3, /*OpIdx*/1, /*OtherMI*/2, /*OtherOpIdx*/1,
        // MIs[3] VOP3Mods:src1:src1_mods
        GIM_CheckIsSameOperand, /*MI*/3, /*OpIdx*/2, /*OtherMI*/2, /*OtherOpIdx*/2,
        GIM_CheckCxxInsnPredicate, /*MI*/0, /*FnId*/GIMT_Encode2(GICXXPred_MI_Predicate_fmaxnum_like_nnan),
        GIM_CheckIsSafeToFold, /*InsnID*/1,
        GIM_CheckIsSafeToFold, /*InsnID*/2,
        GIM_CheckIsSafeToFold, /*InsnID*/3,
        GIM_CheckComplexPattern, /*MI*/1, /*Op*/1, /*Renderer*/GIMT_Encode2(0), GIMT_Encode2(GICP_gi_vop3mods),
        GIM_CheckComplexPattern, /*MI*/2, /*Op*/1, /*Renderer*/GIMT_Encode2(1), GIMT_Encode2(GICP_gi_vop3mods),
        GIM_CheckComplexPattern, /*MI*/2, /*Op*/2, /*Renderer*/GIMT_Encode2(2), GIMT_Encode2(GICP_gi_vop3mods),
        // (fmaxnum_ieee:{ *:[f32] } (fminnum:{ *:[f32] } (VOP3Mods:{ *:[f32] } f32:{ *:[f32] }:$src2, i32:{ *:[i32] }:$src2_mods), (fmaxnum_ieee:{ *:[f32] } (VOP3Mods:{ *:[f32] } f32:{ *:[f32] }:$src0, i32:{ *:[i32] }:$src0_mods), (VOP3Mods:{ *:[f32] } f32:{ *:[f32] }:$src1, i32:{ *:[i32] }:$src1_mods))), (fminnum:{ *:[f32] } (VOP3Mods:{ *:[f32] } f32:{ *:[f32] }:$src0, i32:{ *:[i32] }:$src0_mods), (VOP3Mods:{ *:[f32] } f32:{ *:[f32] }:$src1, i32:{ *:[i32] }:$src1_mods)))<<P:Predicate_fmaxnum_like_nnan>>  =>  (V_MED3_F32_e64:{ *:[f32] } ?:{ *:[i32] }:$src0_mods, ?:{ *:[f32] }:$src0, ?:{ *:[i32] }:$src1_mods, ?:{ *:[f32] }:$src1, ?:{ *:[i32] }:$src2_mods, ?:{ *:[f32] }:$src2, 0:{ *:[i1] }, 0:{ *:[i32] })
        GIR_BuildMI, /*InsnID*/0, /*Opcode*/GIMT_Encode2(AMDGPU::V_MED3_F32_e64),
        GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/0, // DstI[vdst]
        GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(1), /*SubOperand*/1, // src0_mods
        GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(1), /*SubOperand*/0, // src0
        GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(2), /*SubOperand*/1, // src1_mods
        GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(2), /*SubOperand*/0, // src1
        GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/1, // src2_mods
        GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/0, // src2
        GIR_AddImm8, /*InsnID*/0, /*Imm*/0,
        GIR_AddImm8, /*InsnID*/0, /*Imm*/0,
        GIR_ConstrainSelectedInstOperands, /*InsnID*/0,
        GIR_EraseFromParent, /*InsnID*/0,
        // GIR_Coverage, 10101,
        GIR_Done,
      // Label 5098: @371756
      GIM_Try, /*On fail goto*//*Label 5099*/ GIMT_Encode4(371896), // Rule ID 10102 //
        GIM_CheckRegBankForClass, /*MI*/0, /*Op*/0, /*RC*/GIMT_Encode2(AMDGPU::VGPR_32RegClassID),
        GIM_RecordInsn, /*DefineMI*/1, /*MI*/0, /*OpIdx*/1, // MIs[1]
        GIM_CheckOpcode, /*MI*/1, GIMT_Encode2(TargetOpcode::G_FMINNUM),
        GIM_CheckType, /*MI*/1, /*Op*/1, /*Type*/GILLT_s32,
        GIM_CheckType, /*MI*/1, /*Op*/2, /*Type*/GILLT_s32,
        GIM_RecordInsn, /*DefineMI*/2, /*MI*/1, /*OpIdx*/2, // MIs[2]
        GIM_CheckOpcode, /*MI*/2, GIMT_Encode2(TargetOpcode::G_FMAXNUM_IEEE),
        GIM_CheckType, /*MI*/2, /*Op*/1, /*Type*/GILLT_s32,
        GIM_CheckType, /*MI*/2, /*Op*/2, /*Type*/GILLT_s32,
        GIM_RecordInsn, /*DefineMI*/3, /*MI*/0, /*OpIdx*/2, // MIs[3]
        GIM_CheckOpcode, /*MI*/3, GIMT_Encode2(TargetOpcode::G_FMINNUM),
        // MIs[3] VOP3Mods:src1:src1_mods
        GIM_CheckIsSameOperand, /*MI*/3, /*OpIdx*/1, /*OtherMI*/2, /*OtherOpIdx*/2,
        // MIs[3] VOP3Mods:src0:src0_mods
        GIM_CheckIsSameOperand, /*MI*/3, /*OpIdx*/2, /*OtherMI*/2, /*OtherOpIdx*/1,
        GIM_CheckCxxInsnPredicate, /*MI*/0, /*FnId*/GIMT_Encode2(GICXXPred_MI_Predicate_fmaxnum_like_nnan),
        GIM_CheckIsSafeToFold, /*InsnID*/1,
        GIM_CheckIsSafeToFold, /*InsnID*/2,
        GIM_CheckIsSafeToFold, /*InsnID*/3,
        GIM_CheckComplexPattern, /*MI*/1, /*Op*/1, /*Renderer*/GIMT_Encode2(0), GIMT_Encode2(GICP_gi_vop3mods),
        GIM_CheckComplexPattern, /*MI*/2, /*Op*/1, /*Renderer*/GIMT_Encode2(1), GIMT_Encode2(GICP_gi_vop3mods),
        GIM_CheckComplexPattern, /*MI*/2, /*Op*/2, /*Renderer*/GIMT_Encode2(2), GIMT_Encode2(GICP_gi_vop3mods),
        // (fmaxnum_ieee:{ *:[f32] } (fminnum:{ *:[f32] } (VOP3Mods:{ *:[f32] } f32:{ *:[f32] }:$src2, i32:{ *:[i32] }:$src2_mods), (fmaxnum_ieee:{ *:[f32] } (VOP3Mods:{ *:[f32] } f32:{ *:[f32] }:$src0, i32:{ *:[i32] }:$src0_mods), (VOP3Mods:{ *:[f32] } f32:{ *:[f32] }:$src1, i32:{ *:[i32] }:$src1_mods))), (fminnum:{ *:[f32] } (VOP3Mods:{ *:[f32] } f32:{ *:[f32] }:$src1, i32:{ *:[i32] }:$src1_mods), (VOP3Mods:{ *:[f32] } f32:{ *:[f32] }:$src0, i32:{ *:[i32] }:$src0_mods)))<<P:Predicate_fmaxnum_like_nnan>>  =>  (V_MED3_F32_e64:{ *:[f32] } ?:{ *:[i32] }:$src0_mods, ?:{ *:[f32] }:$src0, ?:{ *:[i32] }:$src1_mods, ?:{ *:[f32] }:$src1, ?:{ *:[i32] }:$src2_mods, ?:{ *:[f32] }:$src2, 0:{ *:[i1] }, 0:{ *:[i32] })
        GIR_BuildMI, /*InsnID*/0, /*Opcode*/GIMT_Encode2(AMDGPU::V_MED3_F32_e64),
        GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/0, // DstI[vdst]
        GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(1), /*SubOperand*/1, // src0_mods
        GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(1), /*SubOperand*/0, // src0
        GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(2), /*SubOperand*/1, // src1_mods
        GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(2), /*SubOperand*/0, // src1
        GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/1, // src2_mods
        GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/0, // src2
        GIR_AddImm8, /*InsnID*/0, /*Imm*/0,
        GIR_AddImm8, /*InsnID*/0, /*Imm*/0,
        GIR_ConstrainSelectedInstOperands, /*InsnID*/0,
        GIR_EraseFromParent, /*InsnID*/0,
        // GIR_Coverage, 10102,
        GIR_Done,
      // Label 5099: @371896
      GIM_Try, /*On fail goto*//*Label 5100*/ GIMT_Encode4(372036), // Rule ID 10103 //
        GIM_CheckRegBankForClass, /*MI*/0, /*Op*/0, /*RC*/GIMT_Encode2(AMDGPU::VGPR_32RegClassID),
        GIM_RecordInsn, /*DefineMI*/1, /*MI*/0, /*OpIdx*/1, // MIs[1]
        GIM_CheckOpcode, /*MI*/1, GIMT_Encode2(TargetOpcode::G_FMINNUM),
        GIM_CheckType, /*MI*/1, /*Op*/1, /*Type*/GILLT_s32,
        GIM_CheckType, /*MI*/1, /*Op*/2, /*Type*/GILLT_s32,
        GIM_RecordInsn, /*DefineMI*/2, /*MI*/1, /*OpIdx*/2, // MIs[2]
        GIM_CheckOpcode, /*MI*/2, GIMT_Encode2(TargetOpcode::G_FMAXNUM_IEEE),
        GIM_CheckType, /*MI*/2, /*Op*/1, /*Type*/GILLT_s32,
        GIM_CheckType, /*MI*/2, /*Op*/2, /*Type*/GILLT_s32,
        GIM_RecordInsn, /*DefineMI*/3, /*MI*/0, /*OpIdx*/2, // MIs[3]
        GIM_CheckOpcode, /*MI*/3, GIMT_Encode2(TargetOpcode::G_FMINNUM),
        // MIs[3] VOP3Mods:src0:src0_mods
        GIM_CheckIsSameOperand, /*MI*/3, /*OpIdx*/1, /*OtherMI*/2, /*OtherOpIdx*/2,
        // MIs[3] VOP3Mods:src1:src1_mods
        GIM_CheckIsSameOperand, /*MI*/3, /*OpIdx*/2, /*OtherMI*/2, /*OtherOpIdx*/1,
        GIM_CheckCxxInsnPredicate, /*MI*/0, /*FnId*/GIMT_Encode2(GICXXPred_MI_Predicate_fmaxnum_like_nnan),
        GIM_CheckIsSafeToFold, /*InsnID*/1,
        GIM_CheckIsSafeToFold, /*InsnID*/2,
        GIM_CheckIsSafeToFold, /*InsnID*/3,
        GIM_CheckComplexPattern, /*MI*/1, /*Op*/1, /*Renderer*/GIMT_Encode2(0), GIMT_Encode2(GICP_gi_vop3mods),
        GIM_CheckComplexPattern, /*MI*/2, /*Op*/1, /*Renderer*/GIMT_Encode2(1), GIMT_Encode2(GICP_gi_vop3mods),
        GIM_CheckComplexPattern, /*MI*/2, /*Op*/2, /*Renderer*/GIMT_Encode2(2), GIMT_Encode2(GICP_gi_vop3mods),
        // (fmaxnum_ieee:{ *:[f32] } (fminnum:{ *:[f32] } (VOP3Mods:{ *:[f32] } f32:{ *:[f32] }:$src2, i32:{ *:[i32] }:$src2_mods), (fmaxnum_ieee:{ *:[f32] } (VOP3Mods:{ *:[f32] } f32:{ *:[f32] }:$src1, i32:{ *:[i32] }:$src1_mods), (VOP3Mods:{ *:[f32] } f32:{ *:[f32] }:$src0, i32:{ *:[i32] }:$src0_mods))), (fminnum:{ *:[f32] } (VOP3Mods:{ *:[f32] } f32:{ *:[f32] }:$src0, i32:{ *:[i32] }:$src0_mods), (VOP3Mods:{ *:[f32] } f32:{ *:[f32] }:$src1, i32:{ *:[i32] }:$src1_mods)))<<P:Predicate_fmaxnum_like_nnan>>  =>  (V_MED3_F32_e64:{ *:[f32] } ?:{ *:[i32] }:$src0_mods, ?:{ *:[f32] }:$src0, ?:{ *:[i32] }:$src1_mods, ?:{ *:[f32] }:$src1, ?:{ *:[i32] }:$src2_mods, ?:{ *:[f32] }:$src2, 0:{ *:[i1] }, 0:{ *:[i32] })
        GIR_BuildMI, /*InsnID*/0, /*Opcode*/GIMT_Encode2(AMDGPU::V_MED3_F32_e64),
        GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/0, // DstI[vdst]
        GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(2), /*SubOperand*/1, // src0_mods
        GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(2), /*SubOperand*/0, // src0
        GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(1), /*SubOperand*/1, // src1_mods
        GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(1), /*SubOperand*/0, // src1
        GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/1, // src2_mods
        GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/0, // src2
        GIR_AddImm8, /*InsnID*/0, /*Imm*/0,
        GIR_AddImm8, /*InsnID*/0, /*Imm*/0,
        GIR_ConstrainSelectedInstOperands, /*InsnID*/0,
        GIR_EraseFromParent, /*InsnID*/0,
        // GIR_Coverage, 10103,
        GIR_Done,
      // Label 5100: @372036
      GIM_Try, /*On fail goto*//*Label 5101*/ GIMT_Encode4(372176), // Rule ID 10104 //
        GIM_CheckRegBankForClass, /*MI*/0, /*Op*/0, /*RC*/GIMT_Encode2(AMDGPU::VGPR_32RegClassID),
        GIM_RecordInsn, /*DefineMI*/1, /*MI*/0, /*OpIdx*/1, // MIs[1]
        GIM_CheckOpcode, /*MI*/1, GIMT_Encode2(TargetOpcode::G_FMINNUM),
        GIM_CheckType, /*MI*/1, /*Op*/1, /*Type*/GILLT_s32,
        GIM_CheckType, /*MI*/1, /*Op*/2, /*Type*/GILLT_s32,
        GIM_RecordInsn, /*DefineMI*/2, /*MI*/1, /*OpIdx*/2, // MIs[2]
        GIM_CheckOpcode, /*MI*/2, GIMT_Encode2(TargetOpcode::G_FMAXNUM_IEEE),
        GIM_CheckType, /*MI*/2, /*Op*/1, /*Type*/GILLT_s32,
        GIM_CheckType, /*MI*/2, /*Op*/2, /*Type*/GILLT_s32,
        GIM_RecordInsn, /*DefineMI*/3, /*MI*/0, /*OpIdx*/2, // MIs[3]
        GIM_CheckOpcode, /*MI*/3, GIMT_Encode2(TargetOpcode::G_FMINNUM),
        // MIs[3] VOP3Mods:src1:src1_mods
        GIM_CheckIsSameOperand, /*MI*/3, /*OpIdx*/1, /*OtherMI*/2, /*OtherOpIdx*/1,
        // MIs[3] VOP3Mods:src0:src0_mods
        GIM_CheckIsSameOperand, /*MI*/3, /*OpIdx*/2, /*OtherMI*/2, /*OtherOpIdx*/2,
        GIM_CheckCxxInsnPredicate, /*MI*/0, /*FnId*/GIMT_Encode2(GICXXPred_MI_Predicate_fmaxnum_like_nnan),
        GIM_CheckIsSafeToFold, /*InsnID*/1,
        GIM_CheckIsSafeToFold, /*InsnID*/2,
        GIM_CheckIsSafeToFold, /*InsnID*/3,
        GIM_CheckComplexPattern, /*MI*/1, /*Op*/1, /*Renderer*/GIMT_Encode2(0), GIMT_Encode2(GICP_gi_vop3mods),
        GIM_CheckComplexPattern, /*MI*/2, /*Op*/1, /*Renderer*/GIMT_Encode2(1), GIMT_Encode2(GICP_gi_vop3mods),
        GIM_CheckComplexPattern, /*MI*/2, /*Op*/2, /*Renderer*/GIMT_Encode2(2), GIMT_Encode2(GICP_gi_vop3mods),
        // (fmaxnum_ieee:{ *:[f32] } (fminnum:{ *:[f32] } (VOP3Mods:{ *:[f32] } f32:{ *:[f32] }:$src2, i32:{ *:[i32] }:$src2_mods), (fmaxnum_ieee:{ *:[f32] } (VOP3Mods:{ *:[f32] } f32:{ *:[f32] }:$src1, i32:{ *:[i32] }:$src1_mods), (VOP3Mods:{ *:[f32] } f32:{ *:[f32] }:$src0, i32:{ *:[i32] }:$src0_mods))), (fminnum:{ *:[f32] } (VOP3Mods:{ *:[f32] } f32:{ *:[f32] }:$src1, i32:{ *:[i32] }:$src1_mods), (VOP3Mods:{ *:[f32] } f32:{ *:[f32] }:$src0, i32:{ *:[i32] }:$src0_mods)))<<P:Predicate_fmaxnum_like_nnan>>  =>  (V_MED3_F32_e64:{ *:[f32] } ?:{ *:[i32] }:$src0_mods, ?:{ *:[f32] }:$src0, ?:{ *:[i32] }:$src1_mods, ?:{ *:[f32] }:$src1, ?:{ *:[i32] }:$src2_mods, ?:{ *:[f32] }:$src2, 0:{ *:[i1] }, 0:{ *:[i32] })
        GIR_BuildMI, /*InsnID*/0, /*Opcode*/GIMT_Encode2(AMDGPU::V_MED3_F32_e64),
        GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/0, // DstI[vdst]
        GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(2), /*SubOperand*/1, // src0_mods
        GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(2), /*SubOperand*/0, // src0
        GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(1), /*SubOperand*/1, // src1_mods
        GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(1), /*SubOperand*/0, // src1
        GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/1, // src2_mods
        GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/0, // src2
        GIR_AddImm8, /*InsnID*/0, /*Imm*/0,
        GIR_AddImm8, /*InsnID*/0, /*Imm*/0,
        GIR_ConstrainSelectedInstOperands, /*InsnID*/0,
        GIR_EraseFromParent, /*InsnID*/0,
        // GIR_Coverage, 10104,
        GIR_Done,
      // Label 5101: @372176
      GIM_Try, /*On fail goto*//*Label 5102*/ GIMT_Encode4(372316), // Rule ID 10041 //
        GIM_CheckRegBankForClass, /*MI*/0, /*Op*/0, /*RC*/GIMT_Encode2(AMDGPU::VGPR_32RegClassID),
        GIM_RecordInsn, /*DefineMI*/1, /*MI*/0, /*OpIdx*/1, // MIs[1]
        GIM_CheckOpcode, /*MI*/1, GIMT_Encode2(TargetOpcode::G_FMINNUM),
        GIM_CheckType, /*MI*/1, /*Op*/1, /*Type*/GILLT_s32,
        GIM_CheckType, /*MI*/1, /*Op*/2, /*Type*/GILLT_s32,
        GIM_RecordInsn, /*DefineMI*/2, /*MI*/1, /*OpIdx*/2, // MIs[2]
        GIM_CheckOpcode, /*MI*/2, GIMT_Encode2(TargetOpcode::G_FMAXNUM_IEEE),
        GIM_CheckType, /*MI*/2, /*Op*/1, /*Type*/GILLT_s32,
        GIM_CheckType, /*MI*/2, /*Op*/2, /*Type*/GILLT_s32,
        GIM_RecordInsn, /*DefineMI*/3, /*MI*/0, /*OpIdx*/2, // MIs[3]
        GIM_CheckOpcode, /*MI*/3, GIMT_Encode2(TargetOpcode::G_FMINNUM_IEEE),
        // MIs[3] VOP3Mods:src0:src0_mods
        GIM_CheckIsSameOperand, /*MI*/3, /*OpIdx*/1, /*OtherMI*/2, /*OtherOpIdx*/1,
        // MIs[3] VOP3Mods:src1:src1_mods
        GIM_CheckIsSameOperand, /*MI*/3, /*OpIdx*/2, /*OtherMI*/2, /*OtherOpIdx*/2,
        GIM_CheckCxxInsnPredicate, /*MI*/0, /*FnId*/GIMT_Encode2(GICXXPred_MI_Predicate_fmaxnum_like_nnan),
        GIM_CheckIsSafeToFold, /*InsnID*/1,
        GIM_CheckIsSafeToFold, /*InsnID*/2,
        GIM_CheckIsSafeToFold, /*InsnID*/3,
        GIM_CheckComplexPattern, /*MI*/1, /*Op*/1, /*Renderer*/GIMT_Encode2(0), GIMT_Encode2(GICP_gi_vop3mods),
        GIM_CheckComplexPattern, /*MI*/2, /*Op*/1, /*Renderer*/GIMT_Encode2(1), GIMT_Encode2(GICP_gi_vop3mods),
        GIM_CheckComplexPattern, /*MI*/2, /*Op*/2, /*Renderer*/GIMT_Encode2(2), GIMT_Encode2(GICP_gi_vop3mods),
        // (fmaxnum_ieee:{ *:[f32] } (fminnum:{ *:[f32] } (VOP3Mods:{ *:[f32] } f32:{ *:[f32] }:$src2, i32:{ *:[i32] }:$src2_mods), (fmaxnum_ieee:{ *:[f32] } (VOP3Mods:{ *:[f32] } f32:{ *:[f32] }:$src0, i32:{ *:[i32] }:$src0_mods), (VOP3Mods:{ *:[f32] } f32:{ *:[f32] }:$src1, i32:{ *:[i32] }:$src1_mods))), (fminnum_ieee:{ *:[f32] } (VOP3Mods:{ *:[f32] } f32:{ *:[f32] }:$src0, i32:{ *:[i32] }:$src0_mods), (VOP3Mods:{ *:[f32] } f32:{ *:[f32] }:$src1, i32:{ *:[i32] }:$src1_mods)))<<P:Predicate_fmaxnum_like_nnan>>  =>  (V_MED3_F32_e64:{ *:[f32] } ?:{ *:[i32] }:$src0_mods, ?:{ *:[f32] }:$src0, ?:{ *:[i32] }:$src1_mods, ?:{ *:[f32] }:$src1, ?:{ *:[i32] }:$src2_mods, ?:{ *:[f32] }:$src2, 0:{ *:[i1] }, 0:{ *:[i32] })
        GIR_BuildMI, /*InsnID*/0, /*Opcode*/GIMT_Encode2(AMDGPU::V_MED3_F32_e64),
        GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/0, // DstI[vdst]
        GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(1), /*SubOperand*/1, // src0_mods
        GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(1), /*SubOperand*/0, // src0
        GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(2), /*SubOperand*/1, // src1_mods
        GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(2), /*SubOperand*/0, // src1
        GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/1, // src2_mods
        GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/0, // src2
        GIR_AddImm8, /*InsnID*/0, /*Imm*/0,
        GIR_AddImm8, /*InsnID*/0, /*Imm*/0,
        GIR_ConstrainSelectedInstOperands, /*InsnID*/0,
        GIR_EraseFromParent, /*InsnID*/0,
        // GIR_Coverage, 10041,
        GIR_Done,
      // Label 5102: @372316
      GIM_Try, /*On fail goto*//*Label 5103*/ GIMT_Encode4(372456), // Rule ID 10042 //
        GIM_CheckRegBankForClass, /*MI*/0, /*Op*/0, /*RC*/GIMT_Encode2(AMDGPU::VGPR_32RegClassID),
        GIM_RecordInsn, /*DefineMI*/1, /*MI*/0, /*OpIdx*/1, // MIs[1]
        GIM_CheckOpcode, /*MI*/1, GIMT_Encode2(TargetOpcode::G_FMINNUM),
        GIM_CheckType, /*MI*/1, /*Op*/1, /*Type*/GILLT_s32,
        GIM_CheckType, /*MI*/1, /*Op*/2, /*Type*/GILLT_s32,
        GIM_RecordInsn, /*DefineMI*/2, /*MI*/1, /*OpIdx*/2, // MIs[2]
        GIM_CheckOpcode, /*MI*/2, GIMT_Encode2(TargetOpcode::G_FMAXNUM_IEEE),
        GIM_CheckType, /*MI*/2, /*Op*/1, /*Type*/GILLT_s32,
        GIM_CheckType, /*MI*/2, /*Op*/2, /*Type*/GILLT_s32,
        GIM_RecordInsn, /*DefineMI*/3, /*MI*/0, /*OpIdx*/2, // MIs[3]
        GIM_CheckOpcode, /*MI*/3, GIMT_Encode2(TargetOpcode::G_FMINNUM_IEEE),
        // MIs[3] VOP3Mods:src1:src1_mods
        GIM_CheckIsSameOperand, /*MI*/3, /*OpIdx*/1, /*OtherMI*/2, /*OtherOpIdx*/2,
        // MIs[3] VOP3Mods:src0:src0_mods
        GIM_CheckIsSameOperand, /*MI*/3, /*OpIdx*/2, /*OtherMI*/2, /*OtherOpIdx*/1,
        GIM_CheckCxxInsnPredicate, /*MI*/0, /*FnId*/GIMT_Encode2(GICXXPred_MI_Predicate_fmaxnum_like_nnan),
        GIM_CheckIsSafeToFold, /*InsnID*/1,
        GIM_CheckIsSafeToFold, /*InsnID*/2,
        GIM_CheckIsSafeToFold, /*InsnID*/3,
        GIM_CheckComplexPattern, /*MI*/1, /*Op*/1, /*Renderer*/GIMT_Encode2(0), GIMT_Encode2(GICP_gi_vop3mods),
        GIM_CheckComplexPattern, /*MI*/2, /*Op*/1, /*Renderer*/GIMT_Encode2(1), GIMT_Encode2(GICP_gi_vop3mods),
        GIM_CheckComplexPattern, /*MI*/2, /*Op*/2, /*Renderer*/GIMT_Encode2(2), GIMT_Encode2(GICP_gi_vop3mods),
        // (fmaxnum_ieee:{ *:[f32] } (fminnum:{ *:[f32] } (VOP3Mods:{ *:[f32] } f32:{ *:[f32] }:$src2, i32:{ *:[i32] }:$src2_mods), (fmaxnum_ieee:{ *:[f32] } (VOP3Mods:{ *:[f32] } f32:{ *:[f32] }:$src0, i32:{ *:[i32] }:$src0_mods), (VOP3Mods:{ *:[f32] } f32:{ *:[f32] }:$src1, i32:{ *:[i32] }:$src1_mods))), (fminnum_ieee:{ *:[f32] } (VOP3Mods:{ *:[f32] } f32:{ *:[f32] }:$src1, i32:{ *:[i32] }:$src1_mods), (VOP3Mods:{ *:[f32] } f32:{ *:[f32] }:$src0, i32:{ *:[i32] }:$src0_mods)))<<P:Predicate_fmaxnum_like_nnan>>  =>  (V_MED3_F32_e64:{ *:[f32] } ?:{ *:[i32] }:$src0_mods, ?:{ *:[f32] }:$src0, ?:{ *:[i32] }:$src1_mods, ?:{ *:[f32] }:$src1, ?:{ *:[i32] }:$src2_mods, ?:{ *:[f32] }:$src2, 0:{ *:[i1] }, 0:{ *:[i32] })
        GIR_BuildMI, /*InsnID*/0, /*Opcode*/GIMT_Encode2(AMDGPU::V_MED3_F32_e64),
        GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/0, // DstI[vdst]
        GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(1), /*SubOperand*/1, // src0_mods
        GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(1), /*SubOperand*/0, // src0
        GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(2), /*SubOperand*/1, // src1_mods
        GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(2), /*SubOperand*/0, // src1
        GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/1, // src2_mods
        GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/0, // src2
        GIR_AddImm8, /*InsnID*/0, /*Imm*/0,
        GIR_AddImm8, /*InsnID*/0, /*Imm*/0,
        GIR_ConstrainSelectedInstOperands, /*InsnID*/0,
        GIR_EraseFromParent, /*InsnID*/0,
        // GIR_Coverage, 10042,
        GIR_Done,
      // Label 5103: @372456
      GIM_Try, /*On fail goto*//*Label 5104*/ GIMT_Encode4(372596), // Rule ID 10043 //
        GIM_CheckRegBankForClass, /*MI*/0, /*Op*/0, /*RC*/GIMT_Encode2(AMDGPU::VGPR_32RegClassID),
        GIM_RecordInsn, /*DefineMI*/1, /*MI*/0, /*OpIdx*/1, // MIs[1]
        GIM_CheckOpcode, /*MI*/1, GIMT_Encode2(TargetOpcode::G_FMINNUM),
        GIM_CheckType, /*MI*/1, /*Op*/1, /*Type*/GILLT_s32,
        GIM_CheckType, /*MI*/1, /*Op*/2, /*Type*/GILLT_s32,
        GIM_RecordInsn, /*DefineMI*/2, /*MI*/1, /*OpIdx*/2, // MIs[2]
        GIM_CheckOpcode, /*MI*/2, GIMT_Encode2(TargetOpcode::G_FMAXNUM_IEEE),
        GIM_CheckType, /*MI*/2, /*Op*/1, /*Type*/GILLT_s32,
        GIM_CheckType, /*MI*/2, /*Op*/2, /*Type*/GILLT_s32,
        GIM_RecordInsn, /*DefineMI*/3, /*MI*/0, /*OpIdx*/2, // MIs[3]
        GIM_CheckOpcode, /*MI*/3, GIMT_Encode2(TargetOpcode::G_FMINNUM_IEEE),
        // MIs[3] VOP3Mods:src0:src0_mods
        GIM_CheckIsSameOperand, /*MI*/3, /*OpIdx*/1, /*OtherMI*/2, /*OtherOpIdx*/2,
        // MIs[3] VOP3Mods:src1:src1_mods
        GIM_CheckIsSameOperand, /*MI*/3, /*OpIdx*/2, /*OtherMI*/2, /*OtherOpIdx*/1,
        GIM_CheckCxxInsnPredicate, /*MI*/0, /*FnId*/GIMT_Encode2(GICXXPred_MI_Predicate_fmaxnum_like_nnan),
        GIM_CheckIsSafeToFold, /*InsnID*/1,
        GIM_CheckIsSafeToFold, /*InsnID*/2,
        GIM_CheckIsSafeToFold, /*InsnID*/3,
        GIM_CheckComplexPattern, /*MI*/1, /*Op*/1, /*Renderer*/GIMT_Encode2(0), GIMT_Encode2(GICP_gi_vop3mods),
        GIM_CheckComplexPattern, /*MI*/2, /*Op*/1, /*Renderer*/GIMT_Encode2(1), GIMT_Encode2(GICP_gi_vop3mods),
        GIM_CheckComplexPattern, /*MI*/2, /*Op*/2, /*Renderer*/GIMT_Encode2(2), GIMT_Encode2(GICP_gi_vop3mods),
        // (fmaxnum_ieee:{ *:[f32] } (fminnum:{ *:[f32] } (VOP3Mods:{ *:[f32] } f32:{ *:[f32] }:$src2, i32:{ *:[i32] }:$src2_mods), (fmaxnum_ieee:{ *:[f32] } (VOP3Mods:{ *:[f32] } f32:{ *:[f32] }:$src1, i32:{ *:[i32] }:$src1_mods), (VOP3Mods:{ *:[f32] } f32:{ *:[f32] }:$src0, i32:{ *:[i32] }:$src0_mods))), (fminnum_ieee:{ *:[f32] } (VOP3Mods:{ *:[f32] } f32:{ *:[f32] }:$src0, i32:{ *:[i32] }:$src0_mods), (VOP3Mods:{ *:[f32] } f32:{ *:[f32] }:$src1, i32:{ *:[i32] }:$src1_mods)))<<P:Predicate_fmaxnum_like_nnan>>  =>  (V_MED3_F32_e64:{ *:[f32] } ?:{ *:[i32] }:$src0_mods, ?:{ *:[f32] }:$src0, ?:{ *:[i32] }:$src1_mods, ?:{ *:[f32] }:$src1, ?:{ *:[i32] }:$src2_mods, ?:{ *:[f32] }:$src2, 0:{ *:[i1] }, 0:{ *:[i32] })
        GIR_BuildMI, /*InsnID*/0, /*Opcode*/GIMT_Encode2(AMDGPU::V_MED3_F32_e64),
        GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/0, // DstI[vdst]
        GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(2), /*SubOperand*/1, // src0_mods
        GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(2), /*SubOperand*/0, // src0
        GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(1), /*SubOperand*/1, // src1_mods
        GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(1), /*SubOperand*/0, // src1
        GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/1, // src2_mods
        GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/0, // src2
        GIR_AddImm8, /*InsnID*/0, /*Imm*/0,
        GIR_AddImm8, /*InsnID*/0, /*Imm*/0,
        GIR_ConstrainSelectedInstOperands, /*InsnID*/0,
        GIR_EraseFromParent, /*InsnID*/0,
        // GIR_Coverage, 10043,
        GIR_Done,
      // Label 5104: @372596
      GIM_Try, /*On fail goto*//*Label 5105*/ GIMT_Encode4(372736), // Rule ID 10044 //
        GIM_CheckRegBankForClass, /*MI*/0, /*Op*/0, /*RC*/GIMT_Encode2(AMDGPU::VGPR_32RegClassID),
        GIM_RecordInsn, /*DefineMI*/1, /*MI*/0, /*OpIdx*/1, // MIs[1]
        GIM_CheckOpcode, /*MI*/1, GIMT_Encode2(TargetOpcode::G_FMINNUM),
        GIM_CheckType, /*MI*/1, /*Op*/1, /*Type*/GILLT_s32,
        GIM_CheckType, /*MI*/1, /*Op*/2, /*Type*/GILLT_s32,
        GIM_RecordInsn, /*DefineMI*/2, /*MI*/1, /*OpIdx*/2, // MIs[2]
        GIM_CheckOpcode, /*MI*/2, GIMT_Encode2(TargetOpcode::G_FMAXNUM_IEEE),
        GIM_CheckType, /*MI*/2, /*Op*/1, /*Type*/GILLT_s32,
        GIM_CheckType, /*MI*/2, /*Op*/2, /*Type*/GILLT_s32,
        GIM_RecordInsn, /*DefineMI*/3, /*MI*/0, /*OpIdx*/2, // MIs[3]
        GIM_CheckOpcode, /*MI*/3, GIMT_Encode2(TargetOpcode::G_FMINNUM_IEEE),
        // MIs[3] VOP3Mods:src1:src1_mods
        GIM_CheckIsSameOperand, /*MI*/3, /*OpIdx*/1, /*OtherMI*/2, /*OtherOpIdx*/1,
        // MIs[3] VOP3Mods:src0:src0_mods
        GIM_CheckIsSameOperand, /*MI*/3, /*OpIdx*/2, /*OtherMI*/2, /*OtherOpIdx*/2,
        GIM_CheckCxxInsnPredicate, /*MI*/0, /*FnId*/GIMT_Encode2(GICXXPred_MI_Predicate_fmaxnum_like_nnan),
        GIM_CheckIsSafeToFold, /*InsnID*/1,
        GIM_CheckIsSafeToFold, /*InsnID*/2,
        GIM_CheckIsSafeToFold, /*InsnID*/3,
        GIM_CheckComplexPattern, /*MI*/1, /*Op*/1, /*Renderer*/GIMT_Encode2(0), GIMT_Encode2(GICP_gi_vop3mods),
        GIM_CheckComplexPattern, /*MI*/2, /*Op*/1, /*Renderer*/GIMT_Encode2(1), GIMT_Encode2(GICP_gi_vop3mods),
        GIM_CheckComplexPattern, /*MI*/2, /*Op*/2, /*Renderer*/GIMT_Encode2(2), GIMT_Encode2(GICP_gi_vop3mods),
        // (fmaxnum_ieee:{ *:[f32] } (fminnum:{ *:[f32] } (VOP3Mods:{ *:[f32] } f32:{ *:[f32] }:$src2, i32:{ *:[i32] }:$src2_mods), (fmaxnum_ieee:{ *:[f32] } (VOP3Mods:{ *:[f32] } f32:{ *:[f32] }:$src1, i32:{ *:[i32] }:$src1_mods), (VOP3Mods:{ *:[f32] } f32:{ *:[f32] }:$src0, i32:{ *:[i32] }:$src0_mods))), (fminnum_ieee:{ *:[f32] } (VOP3Mods:{ *:[f32] } f32:{ *:[f32] }:$src1, i32:{ *:[i32] }:$src1_mods), (VOP3Mods:{ *:[f32] } f32:{ *:[f32] }:$src0, i32:{ *:[i32] }:$src0_mods)))<<P:Predicate_fmaxnum_like_nnan>>  =>  (V_MED3_F32_e64:{ *:[f32] } ?:{ *:[i32] }:$src0_mods, ?:{ *:[f32] }:$src0, ?:{ *:[i32] }:$src1_mods, ?:{ *:[f32] }:$src1, ?:{ *:[i32] }:$src2_mods, ?:{ *:[f32] }:$src2, 0:{ *:[i1] }, 0:{ *:[i32] })
        GIR_BuildMI, /*InsnID*/0, /*Opcode*/GIMT_Encode2(AMDGPU::V_MED3_F32_e64),
        GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/0, // DstI[vdst]
        GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(2), /*SubOperand*/1, // src0_mods
        GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(2), /*SubOperand*/0, // src0
        GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(1), /*SubOperand*/1, // src1_mods
        GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(1), /*SubOperand*/0, // src1
        GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/1, // src2_mods
        GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/0, // src2
        GIR_AddImm8, /*InsnID*/0, /*Imm*/0,
        GIR_AddImm8, /*InsnID*/0, /*Imm*/0,
        GIR_ConstrainSelectedInstOperands, /*InsnID*/0,
        GIR_EraseFromParent, /*InsnID*/0,
        // GIR_Coverage, 10044,
        GIR_Done,
      // Label 5105: @372736
      GIM_Try, /*On fail goto*//*Label 5106*/ GIMT_Encode4(372876), // Rule ID 10112 //
        GIM_CheckRegBankForClass, /*MI*/0, /*Op*/0, /*RC*/GIMT_Encode2(AMDGPU::VGPR_32RegClassID),
        GIM_RecordInsn, /*DefineMI*/1, /*MI*/0, /*OpIdx*/1, // MIs[1]
        GIM_CheckOpcode, /*MI*/1, GIMT_Encode2(TargetOpcode::G_FMINNUM),
        GIM_CheckType, /*MI*/1, /*Op*/1, /*Type*/GILLT_s32,
        GIM_CheckType, /*MI*/1, /*Op*/2, /*Type*/GILLT_s32,
        GIM_RecordInsn, /*DefineMI*/2, /*MI*/1, /*OpIdx*/1, // MIs[2]
        GIM_CheckOpcode, /*MI*/2, GIMT_Encode2(TargetOpcode::G_FMAXNUM),
        GIM_CheckType, /*MI*/2, /*Op*/1, /*Type*/GILLT_s32,
        GIM_CheckType, /*MI*/2, /*Op*/2, /*Type*/GILLT_s32,
        GIM_RecordInsn, /*DefineMI*/3, /*MI*/0, /*OpIdx*/2, // MIs[3]
        GIM_CheckOpcode, /*MI*/3, GIMT_Encode2(TargetOpcode::G_FMINNUM),
        // MIs[3] VOP3Mods:src0:src0_mods
        GIM_CheckIsSameOperand, /*MI*/3, /*OpIdx*/1, /*OtherMI*/2, /*OtherOpIdx*/1,
        // MIs[3] VOP3Mods:src1:src1_mods
        GIM_CheckIsSameOperand, /*MI*/3, /*OpIdx*/2, /*OtherMI*/2, /*OtherOpIdx*/2,
        GIM_CheckCxxInsnPredicate, /*MI*/0, /*FnId*/GIMT_Encode2(GICXXPred_MI_Predicate_fmaxnum_like_nnan),
        GIM_CheckIsSafeToFold, /*InsnID*/1,
        GIM_CheckIsSafeToFold, /*InsnID*/2,
        GIM_CheckIsSafeToFold, /*InsnID*/3,
        GIM_CheckComplexPattern, /*MI*/1, /*Op*/2, /*Renderer*/GIMT_Encode2(2), GIMT_Encode2(GICP_gi_vop3mods),
        GIM_CheckComplexPattern, /*MI*/2, /*Op*/1, /*Renderer*/GIMT_Encode2(0), GIMT_Encode2(GICP_gi_vop3mods),
        GIM_CheckComplexPattern, /*MI*/2, /*Op*/2, /*Renderer*/GIMT_Encode2(1), GIMT_Encode2(GICP_gi_vop3mods),
        // (fmaxnum_ieee:{ *:[f32] } (fminnum:{ *:[f32] } (fmaxnum:{ *:[f32] } (VOP3Mods:{ *:[f32] } f32:{ *:[f32] }:$src0, i32:{ *:[i32] }:$src0_mods), (VOP3Mods:{ *:[f32] } f32:{ *:[f32] }:$src1, i32:{ *:[i32] }:$src1_mods)), (VOP3Mods:{ *:[f32] } f32:{ *:[f32] }:$src2, i32:{ *:[i32] }:$src2_mods)), (fminnum:{ *:[f32] } (VOP3Mods:{ *:[f32] } f32:{ *:[f32] }:$src0, i32:{ *:[i32] }:$src0_mods), (VOP3Mods:{ *:[f32] } f32:{ *:[f32] }:$src1, i32:{ *:[i32] }:$src1_mods)))<<P:Predicate_fmaxnum_like_nnan>>  =>  (V_MED3_F32_e64:{ *:[f32] } ?:{ *:[i32] }:$src0_mods, ?:{ *:[f32] }:$src0, ?:{ *:[i32] }:$src1_mods, ?:{ *:[f32] }:$src1, ?:{ *:[i32] }:$src2_mods, ?:{ *:[f32] }:$src2, 0:{ *:[i1] }, 0:{ *:[i32] })
        GIR_BuildMI, /*InsnID*/0, /*Opcode*/GIMT_Encode2(AMDGPU::V_MED3_F32_e64),
        GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/0, // DstI[vdst]
        GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/1, // src0_mods
        GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/0, // src0
        GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(1), /*SubOperand*/1, // src1_mods
        GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(1), /*SubOperand*/0, // src1
        GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(2), /*SubOperand*/1, // src2_mods
        GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(2), /*SubOperand*/0, // src2
        GIR_AddImm8, /*InsnID*/0, /*Imm*/0,
        GIR_AddImm8, /*InsnID*/0, /*Imm*/0,
        GIR_ConstrainSelectedInstOperands, /*InsnID*/0,
        GIR_EraseFromParent, /*InsnID*/0,
        // GIR_Coverage, 10112,
        GIR_Done,
      // Label 5106: @372876
      GIM_Try, /*On fail goto*//*Label 5107*/ GIMT_Encode4(373016), // Rule ID 10113 //
        GIM_CheckRegBankForClass, /*MI*/0, /*Op*/0, /*RC*/GIMT_Encode2(AMDGPU::VGPR_32RegClassID),
        GIM_RecordInsn, /*DefineMI*/1, /*MI*/0, /*OpIdx*/1, // MIs[1]
        GIM_CheckOpcode, /*MI*/1, GIMT_Encode2(TargetOpcode::G_FMINNUM),
        GIM_CheckType, /*MI*/1, /*Op*/1, /*Type*/GILLT_s32,
        GIM_CheckType, /*MI*/1, /*Op*/2, /*Type*/GILLT_s32,
        GIM_RecordInsn, /*DefineMI*/2, /*MI*/1, /*OpIdx*/1, // MIs[2]
        GIM_CheckOpcode, /*MI*/2, GIMT_Encode2(TargetOpcode::G_FMAXNUM),
        GIM_CheckType, /*MI*/2, /*Op*/1, /*Type*/GILLT_s32,
        GIM_CheckType, /*MI*/2, /*Op*/2, /*Type*/GILLT_s32,
        GIM_RecordInsn, /*DefineMI*/3, /*MI*/0, /*OpIdx*/2, // MIs[3]
        GIM_CheckOpcode, /*MI*/3, GIMT_Encode2(TargetOpcode::G_FMINNUM),
        // MIs[3] VOP3Mods:src1:src1_mods
        GIM_CheckIsSameOperand, /*MI*/3, /*OpIdx*/1, /*OtherMI*/2, /*OtherOpIdx*/2,
        // MIs[3] VOP3Mods:src0:src0_mods
        GIM_CheckIsSameOperand, /*MI*/3, /*OpIdx*/2, /*OtherMI*/2, /*OtherOpIdx*/1,
        GIM_CheckCxxInsnPredicate, /*MI*/0, /*FnId*/GIMT_Encode2(GICXXPred_MI_Predicate_fmaxnum_like_nnan),
        GIM_CheckIsSafeToFold, /*InsnID*/1,
        GIM_CheckIsSafeToFold, /*InsnID*/2,
        GIM_CheckIsSafeToFold, /*InsnID*/3,
        GIM_CheckComplexPattern, /*MI*/1, /*Op*/2, /*Renderer*/GIMT_Encode2(2), GIMT_Encode2(GICP_gi_vop3mods),
        GIM_CheckComplexPattern, /*MI*/2, /*Op*/1, /*Renderer*/GIMT_Encode2(0), GIMT_Encode2(GICP_gi_vop3mods),
        GIM_CheckComplexPattern, /*MI*/2, /*Op*/2, /*Renderer*/GIMT_Encode2(1), GIMT_Encode2(GICP_gi_vop3mods),
        // (fmaxnum_ieee:{ *:[f32] } (fminnum:{ *:[f32] } (fmaxnum:{ *:[f32] } (VOP3Mods:{ *:[f32] } f32:{ *:[f32] }:$src0, i32:{ *:[i32] }:$src0_mods), (VOP3Mods:{ *:[f32] } f32:{ *:[f32] }:$src1, i32:{ *:[i32] }:$src1_mods)), (VOP3Mods:{ *:[f32] } f32:{ *:[f32] }:$src2, i32:{ *:[i32] }:$src2_mods)), (fminnum:{ *:[f32] } (VOP3Mods:{ *:[f32] } f32:{ *:[f32] }:$src1, i32:{ *:[i32] }:$src1_mods), (VOP3Mods:{ *:[f32] } f32:{ *:[f32] }:$src0, i32:{ *:[i32] }:$src0_mods)))<<P:Predicate_fmaxnum_like_nnan>>  =>  (V_MED3_F32_e64:{ *:[f32] } ?:{ *:[i32] }:$src0_mods, ?:{ *:[f32] }:$src0, ?:{ *:[i32] }:$src1_mods, ?:{ *:[f32] }:$src1, ?:{ *:[i32] }:$src2_mods, ?:{ *:[f32] }:$src2, 0:{ *:[i1] }, 0:{ *:[i32] })
        GIR_BuildMI, /*InsnID*/0, /*Opcode*/GIMT_Encode2(AMDGPU::V_MED3_F32_e64),
        GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/0, // DstI[vdst]
        GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/1, // src0_mods
        GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/0, // src0
        GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(1), /*SubOperand*/1, // src1_mods
        GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(1), /*SubOperand*/0, // src1
        GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(2), /*SubOperand*/1, // src2_mods
        GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(2), /*SubOperand*/0, // src2
        GIR_AddImm8, /*InsnID*/0, /*Imm*/0,
        GIR_AddImm8, /*InsnID*/0, /*Imm*/0,
        GIR_ConstrainSelectedInstOperands, /*InsnID*/0,
        GIR_EraseFromParent, /*InsnID*/0,
        // GIR_Coverage, 10113,
        GIR_Done,
      // Label 5107: @373016
      GIM_Try, /*On fail goto*//*Label 5108*/ GIMT_Encode4(373156), // Rule ID 10114 //
        GIM_CheckRegBankForClass, /*MI*/0, /*Op*/0, /*RC*/GIMT_Encode2(AMDGPU::VGPR_32RegClassID),
        GIM_RecordInsn, /*DefineMI*/1, /*MI*/0, /*OpIdx*/1, // MIs[1]
        GIM_CheckOpcode, /*MI*/1, GIMT_Encode2(TargetOpcode::G_FMINNUM),
        GIM_CheckType, /*MI*/1, /*Op*/1, /*Type*/GILLT_s32,
        GIM_CheckType, /*MI*/1, /*Op*/2, /*Type*/GILLT_s32,
        GIM_RecordInsn, /*DefineMI*/2, /*MI*/1, /*OpIdx*/1, // MIs[2]
        GIM_CheckOpcode, /*MI*/2, GIMT_Encode2(TargetOpcode::G_FMAXNUM),
        GIM_CheckType, /*MI*/2, /*Op*/1, /*Type*/GILLT_s32,
        GIM_CheckType, /*MI*/2, /*Op*/2, /*Type*/GILLT_s32,
        GIM_RecordInsn, /*DefineMI*/3, /*MI*/0, /*OpIdx*/2, // MIs[3]
        GIM_CheckOpcode, /*MI*/3, GIMT_Encode2(TargetOpcode::G_FMINNUM),
        // MIs[3] VOP3Mods:src0:src0_mods
        GIM_CheckIsSameOperand, /*MI*/3, /*OpIdx*/1, /*OtherMI*/2, /*OtherOpIdx*/2,
        // MIs[3] VOP3Mods:src1:src1_mods
        GIM_CheckIsSameOperand, /*MI*/3, /*OpIdx*/2, /*OtherMI*/2, /*OtherOpIdx*/1,
        GIM_CheckCxxInsnPredicate, /*MI*/0, /*FnId*/GIMT_Encode2(GICXXPred_MI_Predicate_fmaxnum_like_nnan),
        GIM_CheckIsSafeToFold, /*InsnID*/1,
        GIM_CheckIsSafeToFold, /*InsnID*/2,
        GIM_CheckIsSafeToFold, /*InsnID*/3,
        GIM_CheckComplexPattern, /*MI*/1, /*Op*/2, /*Renderer*/GIMT_Encode2(2), GIMT_Encode2(GICP_gi_vop3mods),
        GIM_CheckComplexPattern, /*MI*/2, /*Op*/1, /*Renderer*/GIMT_Encode2(0), GIMT_Encode2(GICP_gi_vop3mods),
        GIM_CheckComplexPattern, /*MI*/2, /*Op*/2, /*Renderer*/GIMT_Encode2(1), GIMT_Encode2(GICP_gi_vop3mods),
        // (fmaxnum_ieee:{ *:[f32] } (fminnum:{ *:[f32] } (fmaxnum:{ *:[f32] } (VOP3Mods:{ *:[f32] } f32:{ *:[f32] }:$src1, i32:{ *:[i32] }:$src1_mods), (VOP3Mods:{ *:[f32] } f32:{ *:[f32] }:$src0, i32:{ *:[i32] }:$src0_mods)), (VOP3Mods:{ *:[f32] } f32:{ *:[f32] }:$src2, i32:{ *:[i32] }:$src2_mods)), (fminnum:{ *:[f32] } (VOP3Mods:{ *:[f32] } f32:{ *:[f32] }:$src0, i32:{ *:[i32] }:$src0_mods), (VOP3Mods:{ *:[f32] } f32:{ *:[f32] }:$src1, i32:{ *:[i32] }:$src1_mods)))<<P:Predicate_fmaxnum_like_nnan>>  =>  (V_MED3_F32_e64:{ *:[f32] } ?:{ *:[i32] }:$src0_mods, ?:{ *:[f32] }:$src0, ?:{ *:[i32] }:$src1_mods, ?:{ *:[f32] }:$src1, ?:{ *:[i32] }:$src2_mods, ?:{ *:[f32] }:$src2, 0:{ *:[i1] }, 0:{ *:[i32] })
        GIR_BuildMI, /*InsnID*/0, /*Opcode*/GIMT_Encode2(AMDGPU::V_MED3_F32_e64),
        GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/0, // DstI[vdst]
        GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(1), /*SubOperand*/1, // src0_mods
        GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(1), /*SubOperand*/0, // src0
        GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/1, // src1_mods
        GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/0, // src1
        GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(2), /*SubOperand*/1, // src2_mods
        GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(2), /*SubOperand*/0, // src2
        GIR_AddImm8, /*InsnID*/0, /*Imm*/0,
        GIR_AddImm8, /*InsnID*/0, /*Imm*/0,
        GIR_ConstrainSelectedInstOperands, /*InsnID*/0,
        GIR_EraseFromParent, /*InsnID*/0,
        // GIR_Coverage, 10114,
        GIR_Done,
      // Label 5108: @373156
      GIM_Try, /*On fail goto*//*Label 5109*/ GIMT_Encode4(373296), // Rule ID 10115 //
        GIM_CheckRegBankForClass, /*MI*/0, /*Op*/0, /*RC*/GIMT_Encode2(AMDGPU::VGPR_32RegClassID),
        GIM_RecordInsn, /*DefineMI*/1, /*MI*/0, /*OpIdx*/1, // MIs[1]
        GIM_CheckOpcode, /*MI*/1, GIMT_Encode2(TargetOpcode::G_FMINNUM),
        GIM_CheckType, /*MI*/1, /*Op*/1, /*Type*/GILLT_s32,
        GIM_CheckType, /*MI*/1, /*Op*/2, /*Type*/GILLT_s32,
        GIM_RecordInsn, /*DefineMI*/2, /*MI*/1, /*OpIdx*/1, // MIs[2]
        GIM_CheckOpcode, /*MI*/2, GIMT_Encode2(TargetOpcode::G_FMAXNUM),
        GIM_CheckType, /*MI*/2, /*Op*/1, /*Type*/GILLT_s32,
        GIM_CheckType, /*MI*/2, /*Op*/2, /*Type*/GILLT_s32,
        GIM_RecordInsn, /*DefineMI*/3, /*MI*/0, /*OpIdx*/2, // MIs[3]
        GIM_CheckOpcode, /*MI*/3, GIMT_Encode2(TargetOpcode::G_FMINNUM),
        // MIs[3] VOP3Mods:src1:src1_mods
        GIM_CheckIsSameOperand, /*MI*/3, /*OpIdx*/1, /*OtherMI*/2, /*OtherOpIdx*/1,
        // MIs[3] VOP3Mods:src0:src0_mods
        GIM_CheckIsSameOperand, /*MI*/3, /*OpIdx*/2, /*OtherMI*/2, /*OtherOpIdx*/2,
        GIM_CheckCxxInsnPredicate, /*MI*/0, /*FnId*/GIMT_Encode2(GICXXPred_MI_Predicate_fmaxnum_like_nnan),
        GIM_CheckIsSafeToFold, /*InsnID*/1,
        GIM_CheckIsSafeToFold, /*InsnID*/2,
        GIM_CheckIsSafeToFold, /*InsnID*/3,
        GIM_CheckComplexPattern, /*MI*/1, /*Op*/2, /*Renderer*/GIMT_Encode2(2), GIMT_Encode2(GICP_gi_vop3mods),
        GIM_CheckComplexPattern, /*MI*/2, /*Op*/1, /*Renderer*/GIMT_Encode2(0), GIMT_Encode2(GICP_gi_vop3mods),
        GIM_CheckComplexPattern, /*MI*/2, /*Op*/2, /*Renderer*/GIMT_Encode2(1), GIMT_Encode2(GICP_gi_vop3mods),
        // (fmaxnum_ieee:{ *:[f32] } (fminnum:{ *:[f32] } (fmaxnum:{ *:[f32] } (VOP3Mods:{ *:[f32] } f32:{ *:[f32] }:$src1, i32:{ *:[i32] }:$src1_mods), (VOP3Mods:{ *:[f32] } f32:{ *:[f32] }:$src0, i32:{ *:[i32] }:$src0_mods)), (VOP3Mods:{ *:[f32] } f32:{ *:[f32] }:$src2, i32:{ *:[i32] }:$src2_mods)), (fminnum:{ *:[f32] } (VOP3Mods:{ *:[f32] } f32:{ *:[f32] }:$src1, i32:{ *:[i32] }:$src1_mods), (VOP3Mods:{ *:[f32] } f32:{ *:[f32] }:$src0, i32:{ *:[i32] }:$src0_mods)))<<P:Predicate_fmaxnum_like_nnan>>  =>  (V_MED3_F32_e64:{ *:[f32] } ?:{ *:[i32] }:$src0_mods, ?:{ *:[f32] }:$src0, ?:{ *:[i32] }:$src1_mods, ?:{ *:[f32] }:$src1, ?:{ *:[i32] }:$src2_mods, ?:{ *:[f32] }:$src2, 0:{ *:[i1] }, 0:{ *:[i32] })
        GIR_BuildMI, /*InsnID*/0, /*Opcode*/GIMT_Encode2(AMDGPU::V_MED3_F32_e64),
        GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/0, // DstI[vdst]
        GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(1), /*SubOperand*/1, // src0_mods
        GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(1), /*SubOperand*/0, // src0
        GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/1, // src1_mods
        GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/0, // src1
        GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(2), /*SubOperand*/1, // src2_mods
        GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(2), /*SubOperand*/0, // src2
        GIR_AddImm8, /*InsnID*/0, /*Imm*/0,
        GIR_AddImm8, /*InsnID*/0, /*Imm*/0,
        GIR_ConstrainSelectedInstOperands, /*InsnID*/0,
        GIR_EraseFromParent, /*InsnID*/0,
        // GIR_Coverage, 10115,
        GIR_Done,
      // Label 5109: @373296
      GIM_Try, /*On fail goto*//*Label 5110*/ GIMT_Encode4(373436), // Rule ID 10052 //
        GIM_CheckRegBankForClass, /*MI*/0, /*Op*/0, /*RC*/GIMT_Encode2(AMDGPU::VGPR_32RegClassID),
        GIM_RecordInsn, /*DefineMI*/1, /*MI*/0, /*OpIdx*/1, // MIs[1]
        GIM_CheckOpcode, /*MI*/1, GIMT_Encode2(TargetOpcode::G_FMINNUM),
        GIM_CheckType, /*MI*/1, /*Op*/1, /*Type*/GILLT_s32,
        GIM_CheckType, /*MI*/1, /*Op*/2, /*Type*/GILLT_s32,
        GIM_RecordInsn, /*DefineMI*/2, /*MI*/1, /*OpIdx*/1, // MIs[2]
        GIM_CheckOpcode, /*MI*/2, GIMT_Encode2(TargetOpcode::G_FMAXNUM),
        GIM_CheckType, /*MI*/2, /*Op*/1, /*Type*/GILLT_s32,
        GIM_CheckType, /*MI*/2, /*Op*/2, /*Type*/GILLT_s32,
        GIM_RecordInsn, /*DefineMI*/3, /*MI*/0, /*OpIdx*/2, // MIs[3]
        GIM_CheckOpcode, /*MI*/3, GIMT_Encode2(TargetOpcode::G_FMINNUM_IEEE),
        // MIs[3] VOP3Mods:src0:src0_mods
        GIM_CheckIsSameOperand, /*MI*/3, /*OpIdx*/1, /*OtherMI*/2, /*OtherOpIdx*/1,
        // MIs[3] VOP3Mods:src1:src1_mods
        GIM_CheckIsSameOperand, /*MI*/3, /*OpIdx*/2, /*OtherMI*/2, /*OtherOpIdx*/2,
        GIM_CheckCxxInsnPredicate, /*MI*/0, /*FnId*/GIMT_Encode2(GICXXPred_MI_Predicate_fmaxnum_like_nnan),
        GIM_CheckIsSafeToFold, /*InsnID*/1,
        GIM_CheckIsSafeToFold, /*InsnID*/2,
        GIM_CheckIsSafeToFold, /*InsnID*/3,
        GIM_CheckComplexPattern, /*MI*/1, /*Op*/2, /*Renderer*/GIMT_Encode2(2), GIMT_Encode2(GICP_gi_vop3mods),
        GIM_CheckComplexPattern, /*MI*/2, /*Op*/1, /*Renderer*/GIMT_Encode2(0), GIMT_Encode2(GICP_gi_vop3mods),
        GIM_CheckComplexPattern, /*MI*/2, /*Op*/2, /*Renderer*/GIMT_Encode2(1), GIMT_Encode2(GICP_gi_vop3mods),
        // (fmaxnum_ieee:{ *:[f32] } (fminnum:{ *:[f32] } (fmaxnum:{ *:[f32] } (VOP3Mods:{ *:[f32] } f32:{ *:[f32] }:$src0, i32:{ *:[i32] }:$src0_mods), (VOP3Mods:{ *:[f32] } f32:{ *:[f32] }:$src1, i32:{ *:[i32] }:$src1_mods)), (VOP3Mods:{ *:[f32] } f32:{ *:[f32] }:$src2, i32:{ *:[i32] }:$src2_mods)), (fminnum_ieee:{ *:[f32] } (VOP3Mods:{ *:[f32] } f32:{ *:[f32] }:$src0, i32:{ *:[i32] }:$src0_mods), (VOP3Mods:{ *:[f32] } f32:{ *:[f32] }:$src1, i32:{ *:[i32] }:$src1_mods)))<<P:Predicate_fmaxnum_like_nnan>>  =>  (V_MED3_F32_e64:{ *:[f32] } ?:{ *:[i32] }:$src0_mods, ?:{ *:[f32] }:$src0, ?:{ *:[i32] }:$src1_mods, ?:{ *:[f32] }:$src1, ?:{ *:[i32] }:$src2_mods, ?:{ *:[f32] }:$src2, 0:{ *:[i1] }, 0:{ *:[i32] })
        GIR_BuildMI, /*InsnID*/0, /*Opcode*/GIMT_Encode2(AMDGPU::V_MED3_F32_e64),
        GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/0, // DstI[vdst]
        GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/1, // src0_mods
        GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/0, // src0
        GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(1), /*SubOperand*/1, // src1_mods
        GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(1), /*SubOperand*/0, // src1
        GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(2), /*SubOperand*/1, // src2_mods
        GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(2), /*SubOperand*/0, // src2
        GIR_AddImm8, /*InsnID*/0, /*Imm*/0,
        GIR_AddImm8, /*InsnID*/0, /*Imm*/0,
        GIR_ConstrainSelectedInstOperands, /*InsnID*/0,
        GIR_EraseFromParent, /*InsnID*/0,
        // GIR_Coverage, 10052,
        GIR_Done,
      // Label 5110: @373436
      GIM_Try, /*On fail goto*//*Label 5111*/ GIMT_Encode4(373576), // Rule ID 10053 //
        GIM_CheckRegBankForClass, /*MI*/0, /*Op*/0, /*RC*/GIMT_Encode2(AMDGPU::VGPR_32RegClassID),
        GIM_RecordInsn, /*DefineMI*/1, /*MI*/0, /*OpIdx*/1, // MIs[1]
        GIM_CheckOpcode, /*MI*/1, GIMT_Encode2(TargetOpcode::G_FMINNUM),
        GIM_CheckType, /*MI*/1, /*Op*/1, /*Type*/GILLT_s32,
        GIM_CheckType, /*MI*/1, /*Op*/2, /*Type*/GILLT_s32,
        GIM_RecordInsn, /*DefineMI*/2, /*MI*/1, /*OpIdx*/1, // MIs[2]
        GIM_CheckOpcode, /*MI*/2, GIMT_Encode2(TargetOpcode::G_FMAXNUM),
        GIM_CheckType, /*MI*/2, /*Op*/1, /*Type*/GILLT_s32,
        GIM_CheckType, /*MI*/2, /*Op*/2, /*Type*/GILLT_s32,
        GIM_RecordInsn, /*DefineMI*/3, /*MI*/0, /*OpIdx*/2, // MIs[3]
        GIM_CheckOpcode, /*MI*/3, GIMT_Encode2(TargetOpcode::G_FMINNUM_IEEE),
        // MIs[3] VOP3Mods:src1:src1_mods
        GIM_CheckIsSameOperand, /*MI*/3, /*OpIdx*/1, /*OtherMI*/2, /*OtherOpIdx*/2,
        // MIs[3] VOP3Mods:src0:src0_mods
        GIM_CheckIsSameOperand, /*MI*/3, /*OpIdx*/2, /*OtherMI*/2, /*OtherOpIdx*/1,
        GIM_CheckCxxInsnPredicate, /*MI*/0, /*FnId*/GIMT_Encode2(GICXXPred_MI_Predicate_fmaxnum_like_nnan),
        GIM_CheckIsSafeToFold, /*InsnID*/1,
        GIM_CheckIsSafeToFold, /*InsnID*/2,
        GIM_CheckIsSafeToFold, /*InsnID*/3,
        GIM_CheckComplexPattern, /*MI*/1, /*Op*/2, /*Renderer*/GIMT_Encode2(2), GIMT_Encode2(GICP_gi_vop3mods),
        GIM_CheckComplexPattern, /*MI*/2, /*Op*/1, /*Renderer*/GIMT_Encode2(0), GIMT_Encode2(GICP_gi_vop3mods),
        GIM_CheckComplexPattern, /*MI*/2, /*Op*/2, /*Renderer*/GIMT_Encode2(1), GIMT_Encode2(GICP_gi_vop3mods),
        // (fmaxnum_ieee:{ *:[f32] } (fminnum:{ *:[f32] } (fmaxnum:{ *:[f32] } (VOP3Mods:{ *:[f32] } f32:{ *:[f32] }:$src0, i32:{ *:[i32] }:$src0_mods), (VOP3Mods:{ *:[f32] } f32:{ *:[f32] }:$src1, i32:{ *:[i32] }:$src1_mods)), (VOP3Mods:{ *:[f32] } f32:{ *:[f32] }:$src2, i32:{ *:[i32] }:$src2_mods)), (fminnum_ieee:{ *:[f32] } (VOP3Mods:{ *:[f32] } f32:{ *:[f32] }:$src1, i32:{ *:[i32] }:$src1_mods), (VOP3Mods:{ *:[f32] } f32:{ *:[f32] }:$src0, i32:{ *:[i32] }:$src0_mods)))<<P:Predicate_fmaxnum_like_nnan>>  =>  (V_MED3_F32_e64:{ *:[f32] } ?:{ *:[i32] }:$src0_mods, ?:{ *:[f32] }:$src0, ?:{ *:[i32] }:$src1_mods, ?:{ *:[f32] }:$src1, ?:{ *:[i32] }:$src2_mods, ?:{ *:[f32] }:$src2, 0:{ *:[i1] }, 0:{ *:[i32] })
        GIR_BuildMI, /*InsnID*/0, /*Opcode*/GIMT_Encode2(AMDGPU::V_MED3_F32_e64),
        GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/0, // DstI[vdst]
        GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/1, // src0_mods
        GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/0, // src0
        GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(1), /*SubOperand*/1, // src1_mods
        GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(1), /*SubOperand*/0, // src1
        GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(2), /*SubOperand*/1, // src2_mods
        GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(2), /*SubOperand*/0, // src2
        GIR_AddImm8, /*InsnID*/0, /*Imm*/0,
        GIR_AddImm8, /*InsnID*/0, /*Imm*/0,
        GIR_ConstrainSelectedInstOperands, /*InsnID*/0,
        GIR_EraseFromParent, /*InsnID*/0,
        // GIR_Coverage, 10053,
        GIR_Done,
      // Label 5111: @373576
      GIM_Try, /*On fail goto*//*Label 5112*/ GIMT_Encode4(373716), // Rule ID 10054 //
        GIM_CheckRegBankForClass, /*MI*/0, /*Op*/0, /*RC*/GIMT_Encode2(AMDGPU::VGPR_32RegClassID),
        GIM_RecordInsn, /*DefineMI*/1, /*MI*/0, /*OpIdx*/1, // MIs[1]
        GIM_CheckOpcode, /*MI*/1, GIMT_Encode2(TargetOpcode::G_FMINNUM),
        GIM_CheckType, /*MI*/1, /*Op*/1, /*Type*/GILLT_s32,
        GIM_CheckType, /*MI*/1, /*Op*/2, /*Type*/GILLT_s32,
        GIM_RecordInsn, /*DefineMI*/2, /*MI*/1, /*OpIdx*/1, // MIs[2]
        GIM_CheckOpcode, /*MI*/2, GIMT_Encode2(TargetOpcode::G_FMAXNUM),
        GIM_CheckType, /*MI*/2, /*Op*/1, /*Type*/GILLT_s32,
        GIM_CheckType, /*MI*/2, /*Op*/2, /*Type*/GILLT_s32,
        GIM_RecordInsn, /*DefineMI*/3, /*MI*/0, /*OpIdx*/2, // MIs[3]
        GIM_CheckOpcode, /*MI*/3, GIMT_Encode2(TargetOpcode::G_FMINNUM_IEEE),
        // MIs[3] VOP3Mods:src0:src0_mods
        GIM_CheckIsSameOperand, /*MI*/3, /*OpIdx*/1, /*OtherMI*/2, /*OtherOpIdx*/2,
        // MIs[3] VOP3Mods:src1:src1_mods
        GIM_CheckIsSameOperand, /*MI*/3, /*OpIdx*/2, /*OtherMI*/2, /*OtherOpIdx*/1,
        GIM_CheckCxxInsnPredicate, /*MI*/0, /*FnId*/GIMT_Encode2(GICXXPred_MI_Predicate_fmaxnum_like_nnan),
        GIM_CheckIsSafeToFold, /*InsnID*/1,
        GIM_CheckIsSafeToFold, /*InsnID*/2,
        GIM_CheckIsSafeToFold, /*InsnID*/3,
        GIM_CheckComplexPattern, /*MI*/1, /*Op*/2, /*Renderer*/GIMT_Encode2(2), GIMT_Encode2(GICP_gi_vop3mods),
        GIM_CheckComplexPattern, /*MI*/2, /*Op*/1, /*Renderer*/GIMT_Encode2(0), GIMT_Encode2(GICP_gi_vop3mods),
        GIM_CheckComplexPattern, /*MI*/2, /*Op*/2, /*Renderer*/GIMT_Encode2(1), GIMT_Encode2(GICP_gi_vop3mods),
        // (fmaxnum_ieee:{ *:[f32] } (fminnum:{ *:[f32] } (fmaxnum:{ *:[f32] } (VOP3Mods:{ *:[f32] } f32:{ *:[f32] }:$src1, i32:{ *:[i32] }:$src1_mods), (VOP3Mods:{ *:[f32] } f32:{ *:[f32] }:$src0, i32:{ *:[i32] }:$src0_mods)), (VOP3Mods:{ *:[f32] } f32:{ *:[f32] }:$src2, i32:{ *:[i32] }:$src2_mods)), (fminnum_ieee:{ *:[f32] } (VOP3Mods:{ *:[f32] } f32:{ *:[f32] }:$src0, i32:{ *:[i32] }:$src0_mods), (VOP3Mods:{ *:[f32] } f32:{ *:[f32] }:$src1, i32:{ *:[i32] }:$src1_mods)))<<P:Predicate_fmaxnum_like_nnan>>  =>  (V_MED3_F32_e64:{ *:[f32] } ?:{ *:[i32] }:$src0_mods, ?:{ *:[f32] }:$src0, ?:{ *:[i32] }:$src1_mods, ?:{ *:[f32] }:$src1, ?:{ *:[i32] }:$src2_mods, ?:{ *:[f32] }:$src2, 0:{ *:[i1] }, 0:{ *:[i32] })
        GIR_BuildMI, /*InsnID*/0, /*Opcode*/GIMT_Encode2(AMDGPU::V_MED3_F32_e64),
        GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/0, // DstI[vdst]
        GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(1), /*SubOperand*/1, // src0_mods
        GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(1), /*SubOperand*/0, // src0
        GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/1, // src1_mods
        GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/0, // src1
        GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(2), /*SubOperand*/1, // src2_mods
        GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(2), /*SubOperand*/0, // src2
        GIR_AddImm8, /*InsnID*/0, /*Imm*/0,
        GIR_AddImm8, /*InsnID*/0, /*Imm*/0,
        GIR_ConstrainSelectedInstOperands, /*InsnID*/0,
        GIR_EraseFromParent, /*InsnID*/0,
        // GIR_Coverage, 10054,
        GIR_Done,
      // Label 5112: @373716
      GIM_Try, /*On fail goto*//*Label 5113*/ GIMT_Encode4(373856), // Rule ID 10055 //
        GIM_CheckRegBankForClass, /*MI*/0, /*Op*/0, /*RC*/GIMT_Encode2(AMDGPU::VGPR_32RegClassID),
        GIM_RecordInsn, /*DefineMI*/1, /*MI*/0, /*OpIdx*/1, // MIs[1]
        GIM_CheckOpcode, /*MI*/1, GIMT_Encode2(TargetOpcode::G_FMINNUM),
        GIM_CheckType, /*MI*/1, /*Op*/1, /*Type*/GILLT_s32,
        GIM_CheckType, /*MI*/1, /*Op*/2, /*Type*/GILLT_s32,
        GIM_RecordInsn, /*DefineMI*/2, /*MI*/1, /*OpIdx*/1, // MIs[2]
        GIM_CheckOpcode, /*MI*/2, GIMT_Encode2(TargetOpcode::G_FMAXNUM),
        GIM_CheckType, /*MI*/2, /*Op*/1, /*Type*/GILLT_s32,
        GIM_CheckType, /*MI*/2, /*Op*/2, /*Type*/GILLT_s32,
        GIM_RecordInsn, /*DefineMI*/3, /*MI*/0, /*OpIdx*/2, // MIs[3]
        GIM_CheckOpcode, /*MI*/3, GIMT_Encode2(TargetOpcode::G_FMINNUM_IEEE),
        // MIs[3] VOP3Mods:src1:src1_mods
        GIM_CheckIsSameOperand, /*MI*/3, /*OpIdx*/1, /*OtherMI*/2, /*OtherOpIdx*/1,
        // MIs[3] VOP3Mods:src0:src0_mods
        GIM_CheckIsSameOperand, /*MI*/3, /*OpIdx*/2, /*OtherMI*/2, /*OtherOpIdx*/2,
        GIM_CheckCxxInsnPredicate, /*MI*/0, /*FnId*/GIMT_Encode2(GICXXPred_MI_Predicate_fmaxnum_like_nnan),
        GIM_CheckIsSafeToFold, /*InsnID*/1,
        GIM_CheckIsSafeToFold, /*InsnID*/2,
        GIM_CheckIsSafeToFold, /*InsnID*/3,
        GIM_CheckComplexPattern, /*MI*/1, /*Op*/2, /*Renderer*/GIMT_Encode2(2), GIMT_Encode2(GICP_gi_vop3mods),
        GIM_CheckComplexPattern, /*MI*/2, /*Op*/1, /*Renderer*/GIMT_Encode2(0), GIMT_Encode2(GICP_gi_vop3mods),
        GIM_CheckComplexPattern, /*MI*/2, /*Op*/2, /*Renderer*/GIMT_Encode2(1), GIMT_Encode2(GICP_gi_vop3mods),
        // (fmaxnum_ieee:{ *:[f32] } (fminnum:{ *:[f32] } (fmaxnum:{ *:[f32] } (VOP3Mods:{ *:[f32] } f32:{ *:[f32] }:$src1, i32:{ *:[i32] }:$src1_mods), (VOP3Mods:{ *:[f32] } f32:{ *:[f32] }:$src0, i32:{ *:[i32] }:$src0_mods)), (VOP3Mods:{ *:[f32] } f32:{ *:[f32] }:$src2, i32:{ *:[i32] }:$src2_mods)), (fminnum_ieee:{ *:[f32] } (VOP3Mods:{ *:[f32] } f32:{ *:[f32] }:$src1, i32:{ *:[i32] }:$src1_mods), (VOP3Mods:{ *:[f32] } f32:{ *:[f32] }:$src0, i32:{ *:[i32] }:$src0_mods)))<<P:Predicate_fmaxnum_like_nnan>>  =>  (V_MED3_F32_e64:{ *:[f32] } ?:{ *:[i32] }:$src0_mods, ?:{ *:[f32] }:$src0, ?:{ *:[i32] }:$src1_mods, ?:{ *:[f32] }:$src1, ?:{ *:[i32] }:$src2_mods, ?:{ *:[f32] }:$src2, 0:{ *:[i1] }, 0:{ *:[i32] })
        GIR_BuildMI, /*InsnID*/0, /*Opcode*/GIMT_Encode2(AMDGPU::V_MED3_F32_e64),
        GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/0, // DstI[vdst]
        GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(1), /*SubOperand*/1, // src0_mods
        GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(1), /*SubOperand*/0, // src0
        GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/1, // src1_mods
        GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/0, // src1
        GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(2), /*SubOperand*/1, // src2_mods
        GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(2), /*SubOperand*/0, // src2
        GIR_AddImm8, /*InsnID*/0, /*Imm*/0,
        GIR_AddImm8, /*InsnID*/0, /*Imm*/0,
        GIR_ConstrainSelectedInstOperands, /*InsnID*/0,
        GIR_EraseFromParent, /*InsnID*/0,
        // GIR_Coverage, 10055,
        GIR_Done,
      // Label 5113: @373856
      GIM_Try, /*On fail goto*//*Label 5114*/ GIMT_Encode4(373996), // Rule ID 10097 //
        GIM_CheckRegBankForClass, /*MI*/0, /*Op*/0, /*RC*/GIMT_Encode2(AMDGPU::VGPR_32RegClassID),
        GIM_RecordInsn, /*DefineMI*/1, /*MI*/0, /*OpIdx*/1, // MIs[1]
        GIM_CheckOpcode, /*MI*/1, GIMT_Encode2(TargetOpcode::G_FMINNUM),
        GIM_CheckType, /*MI*/1, /*Op*/1, /*Type*/GILLT_s32,
        GIM_CheckType, /*MI*/1, /*Op*/2, /*Type*/GILLT_s32,
        GIM_RecordInsn, /*DefineMI*/2, /*MI*/1, /*OpIdx*/1, // MIs[2]
        GIM_CheckOpcode, /*MI*/2, GIMT_Encode2(TargetOpcode::G_FMAXNUM_IEEE),
        GIM_CheckType, /*MI*/2, /*Op*/1, /*Type*/GILLT_s32,
        GIM_CheckType, /*MI*/2, /*Op*/2, /*Type*/GILLT_s32,
        GIM_RecordInsn, /*DefineMI*/3, /*MI*/0, /*OpIdx*/2, // MIs[3]
        GIM_CheckOpcode, /*MI*/3, GIMT_Encode2(TargetOpcode::G_FMINNUM),
        // MIs[3] VOP3Mods:src0:src0_mods
        GIM_CheckIsSameOperand, /*MI*/3, /*OpIdx*/1, /*OtherMI*/2, /*OtherOpIdx*/1,
        // MIs[3] VOP3Mods:src1:src1_mods
        GIM_CheckIsSameOperand, /*MI*/3, /*OpIdx*/2, /*OtherMI*/2, /*OtherOpIdx*/2,
        GIM_CheckCxxInsnPredicate, /*MI*/0, /*FnId*/GIMT_Encode2(GICXXPred_MI_Predicate_fmaxnum_like_nnan),
        GIM_CheckIsSafeToFold, /*InsnID*/1,
        GIM_CheckIsSafeToFold, /*InsnID*/2,
        GIM_CheckIsSafeToFold, /*InsnID*/3,
        GIM_CheckComplexPattern, /*MI*/1, /*Op*/2, /*Renderer*/GIMT_Encode2(2), GIMT_Encode2(GICP_gi_vop3mods),
        GIM_CheckComplexPattern, /*MI*/2, /*Op*/1, /*Renderer*/GIMT_Encode2(0), GIMT_Encode2(GICP_gi_vop3mods),
        GIM_CheckComplexPattern, /*MI*/2, /*Op*/2, /*Renderer*/GIMT_Encode2(1), GIMT_Encode2(GICP_gi_vop3mods),
        // (fmaxnum_ieee:{ *:[f32] } (fminnum:{ *:[f32] } (fmaxnum_ieee:{ *:[f32] } (VOP3Mods:{ *:[f32] } f32:{ *:[f32] }:$src0, i32:{ *:[i32] }:$src0_mods), (VOP3Mods:{ *:[f32] } f32:{ *:[f32] }:$src1, i32:{ *:[i32] }:$src1_mods)), (VOP3Mods:{ *:[f32] } f32:{ *:[f32] }:$src2, i32:{ *:[i32] }:$src2_mods)), (fminnum:{ *:[f32] } (VOP3Mods:{ *:[f32] } f32:{ *:[f32] }:$src0, i32:{ *:[i32] }:$src0_mods), (VOP3Mods:{ *:[f32] } f32:{ *:[f32] }:$src1, i32:{ *:[i32] }:$src1_mods)))<<P:Predicate_fmaxnum_like_nnan>>  =>  (V_MED3_F32_e64:{ *:[f32] } ?:{ *:[i32] }:$src0_mods, ?:{ *:[f32] }:$src0, ?:{ *:[i32] }:$src1_mods, ?:{ *:[f32] }:$src1, ?:{ *:[i32] }:$src2_mods, ?:{ *:[f32] }:$src2, 0:{ *:[i1] }, 0:{ *:[i32] })
        GIR_BuildMI, /*InsnID*/0, /*Opcode*/GIMT_Encode2(AMDGPU::V_MED3_F32_e64),
        GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/0, // DstI[vdst]
        GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/1, // src0_mods
        GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/0, // src0
        GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(1), /*SubOperand*/1, // src1_mods
        GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(1), /*SubOperand*/0, // src1
        GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(2), /*SubOperand*/1, // src2_mods
        GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(2), /*SubOperand*/0, // src2
        GIR_AddImm8, /*InsnID*/0, /*Imm*/0,
        GIR_AddImm8, /*InsnID*/0, /*Imm*/0,
        GIR_ConstrainSelectedInstOperands, /*InsnID*/0,
        GIR_EraseFromParent, /*InsnID*/0,
        // GIR_Coverage, 10097,
        GIR_Done,
      // Label 5114: @373996
      GIM_Try, /*On fail goto*//*Label 5115*/ GIMT_Encode4(374136), // Rule ID 10098 //
        GIM_CheckRegBankForClass, /*MI*/0, /*Op*/0, /*RC*/GIMT_Encode2(AMDGPU::VGPR_32RegClassID),
        GIM_RecordInsn, /*DefineMI*/1, /*MI*/0, /*OpIdx*/1, // MIs[1]
        GIM_CheckOpcode, /*MI*/1, GIMT_Encode2(TargetOpcode::G_FMINNUM),
        GIM_CheckType, /*MI*/1, /*Op*/1, /*Type*/GILLT_s32,
        GIM_CheckType, /*MI*/1, /*Op*/2, /*Type*/GILLT_s32,
        GIM_RecordInsn, /*DefineMI*/2, /*MI*/1, /*OpIdx*/1, // MIs[2]
        GIM_CheckOpcode, /*MI*/2, GIMT_Encode2(TargetOpcode::G_FMAXNUM_IEEE),
        GIM_CheckType, /*MI*/2, /*Op*/1, /*Type*/GILLT_s32,
        GIM_CheckType, /*MI*/2, /*Op*/2, /*Type*/GILLT_s32,
        GIM_RecordInsn, /*DefineMI*/3, /*MI*/0, /*OpIdx*/2, // MIs[3]
        GIM_CheckOpcode, /*MI*/3, GIMT_Encode2(TargetOpcode::G_FMINNUM),
        // MIs[3] VOP3Mods:src1:src1_mods
        GIM_CheckIsSameOperand, /*MI*/3, /*OpIdx*/1, /*OtherMI*/2, /*OtherOpIdx*/2,
        // MIs[3] VOP3Mods:src0:src0_mods
        GIM_CheckIsSameOperand, /*MI*/3, /*OpIdx*/2, /*OtherMI*/2, /*OtherOpIdx*/1,
        GIM_CheckCxxInsnPredicate, /*MI*/0, /*FnId*/GIMT_Encode2(GICXXPred_MI_Predicate_fmaxnum_like_nnan),
        GIM_CheckIsSafeToFold, /*InsnID*/1,
        GIM_CheckIsSafeToFold, /*InsnID*/2,
        GIM_CheckIsSafeToFold, /*InsnID*/3,
        GIM_CheckComplexPattern, /*MI*/1, /*Op*/2, /*Renderer*/GIMT_Encode2(2), GIMT_Encode2(GICP_gi_vop3mods),
        GIM_CheckComplexPattern, /*MI*/2, /*Op*/1, /*Renderer*/GIMT_Encode2(0), GIMT_Encode2(GICP_gi_vop3mods),
        GIM_CheckComplexPattern, /*MI*/2, /*Op*/2, /*Renderer*/GIMT_Encode2(1), GIMT_Encode2(GICP_gi_vop3mods),
        // (fmaxnum_ieee:{ *:[f32] } (fminnum:{ *:[f32] } (fmaxnum_ieee:{ *:[f32] } (VOP3Mods:{ *:[f32] } f32:{ *:[f32] }:$src0, i32:{ *:[i32] }:$src0_mods), (VOP3Mods:{ *:[f32] } f32:{ *:[f32] }:$src1, i32:{ *:[i32] }:$src1_mods)), (VOP3Mods:{ *:[f32] } f32:{ *:[f32] }:$src2, i32:{ *:[i32] }:$src2_mods)), (fminnum:{ *:[f32] } (VOP3Mods:{ *:[f32] } f32:{ *:[f32] }:$src1, i32:{ *:[i32] }:$src1_mods), (VOP3Mods:{ *:[f32] } f32:{ *:[f32] }:$src0, i32:{ *:[i32] }:$src0_mods)))<<P:Predicate_fmaxnum_like_nnan>>  =>  (V_MED3_F32_e64:{ *:[f32] } ?:{ *:[i32] }:$src0_mods, ?:{ *:[f32] }:$src0, ?:{ *:[i32] }:$src1_mods, ?:{ *:[f32] }:$src1, ?:{ *:[i32] }:$src2_mods, ?:{ *:[f32] }:$src2, 0:{ *:[i1] }, 0:{ *:[i32] })
        GIR_BuildMI, /*InsnID*/0, /*Opcode*/GIMT_Encode2(AMDGPU::V_MED3_F32_e64),
        GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/0, // DstI[vdst]
        GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/1, // src0_mods
        GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/0, // src0
        GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(1), /*SubOperand*/1, // src1_mods
        GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(1), /*SubOperand*/0, // src1
        GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(2), /*SubOperand*/1, // src2_mods
        GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(2), /*SubOperand*/0, // src2
        GIR_AddImm8, /*InsnID*/0, /*Imm*/0,
        GIR_AddImm8, /*InsnID*/0, /*Imm*/0,
        GIR_ConstrainSelectedInstOperands, /*InsnID*/0,
        GIR_EraseFromParent, /*InsnID*/0,
        // GIR_Coverage, 10098,
        GIR_Done,
      // Label 5115: @374136
      GIM_Try, /*On fail goto*//*Label 5116*/ GIMT_Encode4(374276), // Rule ID 10099 //
        GIM_CheckRegBankForClass, /*MI*/0, /*Op*/0, /*RC*/GIMT_Encode2(AMDGPU::VGPR_32RegClassID),
        GIM_RecordInsn, /*DefineMI*/1, /*MI*/0, /*OpIdx*/1, // MIs[1]
        GIM_CheckOpcode, /*MI*/1, GIMT_Encode2(TargetOpcode::G_FMINNUM),
        GIM_CheckType, /*MI*/1, /*Op*/1, /*Type*/GILLT_s32,
        GIM_CheckType, /*MI*/1, /*Op*/2, /*Type*/GILLT_s32,
        GIM_RecordInsn, /*DefineMI*/2, /*MI*/1, /*OpIdx*/1, // MIs[2]
        GIM_CheckOpcode, /*MI*/2, GIMT_Encode2(TargetOpcode::G_FMAXNUM_IEEE),
        GIM_CheckType, /*MI*/2, /*Op*/1, /*Type*/GILLT_s32,
        GIM_CheckType, /*MI*/2, /*Op*/2, /*Type*/GILLT_s32,
        GIM_RecordInsn, /*DefineMI*/3, /*MI*/0, /*OpIdx*/2, // MIs[3]
        GIM_CheckOpcode, /*MI*/3, GIMT_Encode2(TargetOpcode::G_FMINNUM),
        // MIs[3] VOP3Mods:src0:src0_mods
        GIM_CheckIsSameOperand, /*MI*/3, /*OpIdx*/1, /*OtherMI*/2, /*OtherOpIdx*/2,
        // MIs[3] VOP3Mods:src1:src1_mods
        GIM_CheckIsSameOperand, /*MI*/3, /*OpIdx*/2, /*OtherMI*/2, /*OtherOpIdx*/1,
        GIM_CheckCxxInsnPredicate, /*MI*/0, /*FnId*/GIMT_Encode2(GICXXPred_MI_Predicate_fmaxnum_like_nnan),
        GIM_CheckIsSafeToFold, /*InsnID*/1,
        GIM_CheckIsSafeToFold, /*InsnID*/2,
        GIM_CheckIsSafeToFold, /*InsnID*/3,
        GIM_CheckComplexPattern, /*MI*/1, /*Op*/2, /*Renderer*/GIMT_Encode2(2), GIMT_Encode2(GICP_gi_vop3mods),
        GIM_CheckComplexPattern, /*MI*/2, /*Op*/1, /*Renderer*/GIMT_Encode2(0), GIMT_Encode2(GICP_gi_vop3mods),
        GIM_CheckComplexPattern, /*MI*/2, /*Op*/2, /*Renderer*/GIMT_Encode2(1), GIMT_Encode2(GICP_gi_vop3mods),
        // (fmaxnum_ieee:{ *:[f32] } (fminnum:{ *:[f32] } (fmaxnum_ieee:{ *:[f32] } (VOP3Mods:{ *:[f32] } f32:{ *:[f32] }:$src1, i32:{ *:[i32] }:$src1_mods), (VOP3Mods:{ *:[f32] } f32:{ *:[f32] }:$src0, i32:{ *:[i32] }:$src0_mods)), (VOP3Mods:{ *:[f32] } f32:{ *:[f32] }:$src2, i32:{ *:[i32] }:$src2_mods)), (fminnum:{ *:[f32] } (VOP3Mods:{ *:[f32] } f32:{ *:[f32] }:$src0, i32:{ *:[i32] }:$src0_mods), (VOP3Mods:{ *:[f32] } f32:{ *:[f32] }:$src1, i32:{ *:[i32] }:$src1_mods)))<<P:Predicate_fmaxnum_like_nnan>>  =>  (V_MED3_F32_e64:{ *:[f32] } ?:{ *:[i32] }:$src0_mods, ?:{ *:[f32] }:$src0, ?:{ *:[i32] }:$src1_mods, ?:{ *:[f32] }:$src1, ?:{ *:[i32] }:$src2_mods, ?:{ *:[f32] }:$src2, 0:{ *:[i1] }, 0:{ *:[i32] })
        GIR_BuildMI, /*InsnID*/0, /*Opcode*/GIMT_Encode2(AMDGPU::V_MED3_F32_e64),
        GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/0, // DstI[vdst]
        GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(1), /*SubOperand*/1, // src0_mods
        GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(1), /*SubOperand*/0, // src0
        GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/1, // src1_mods
        GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/0, // src1
        GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(2), /*SubOperand*/1, // src2_mods
        GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(2), /*SubOperand*/0, // src2
        GIR_AddImm8, /*InsnID*/0, /*Imm*/0,
        GIR_AddImm8, /*InsnID*/0, /*Imm*/0,
        GIR_ConstrainSelectedInstOperands, /*InsnID*/0,
        GIR_EraseFromParent, /*InsnID*/0,
        // GIR_Coverage, 10099,
        GIR_Done,
      // Label 5116: @374276
      GIM_Try, /*On fail goto*//*Label 5117*/ GIMT_Encode4(374416), // Rule ID 10100 //
        GIM_CheckRegBankForClass, /*MI*/0, /*Op*/0, /*RC*/GIMT_Encode2(AMDGPU::VGPR_32RegClassID),
        GIM_RecordInsn, /*DefineMI*/1, /*MI*/0, /*OpIdx*/1, // MIs[1]
        GIM_CheckOpcode, /*MI*/1, GIMT_Encode2(TargetOpcode::G_FMINNUM),
        GIM_CheckType, /*MI*/1, /*Op*/1, /*Type*/GILLT_s32,
        GIM_CheckType, /*MI*/1, /*Op*/2, /*Type*/GILLT_s32,
        GIM_RecordInsn, /*DefineMI*/2, /*MI*/1, /*OpIdx*/1, // MIs[2]
        GIM_CheckOpcode, /*MI*/2, GIMT_Encode2(TargetOpcode::G_FMAXNUM_IEEE),
        GIM_CheckType, /*MI*/2, /*Op*/1, /*Type*/GILLT_s32,
        GIM_CheckType, /*MI*/2, /*Op*/2, /*Type*/GILLT_s32,
        GIM_RecordInsn, /*DefineMI*/3, /*MI*/0, /*OpIdx*/2, // MIs[3]
        GIM_CheckOpcode, /*MI*/3, GIMT_Encode2(TargetOpcode::G_FMINNUM),
        // MIs[3] VOP3Mods:src1:src1_mods
        GIM_CheckIsSameOperand, /*MI*/3, /*OpIdx*/1, /*OtherMI*/2, /*OtherOpIdx*/1,
        // MIs[3] VOP3Mods:src0:src0_mods
        GIM_CheckIsSameOperand, /*MI*/3, /*OpIdx*/2, /*OtherMI*/2, /*OtherOpIdx*/2,
        GIM_CheckCxxInsnPredicate, /*MI*/0, /*FnId*/GIMT_Encode2(GICXXPred_MI_Predicate_fmaxnum_like_nnan),
        GIM_CheckIsSafeToFold, /*InsnID*/1,
        GIM_CheckIsSafeToFold, /*InsnID*/2,
        GIM_CheckIsSafeToFold, /*InsnID*/3,
        GIM_CheckComplexPattern, /*MI*/1, /*Op*/2, /*Renderer*/GIMT_Encode2(2), GIMT_Encode2(GICP_gi_vop3mods),
        GIM_CheckComplexPattern, /*MI*/2, /*Op*/1, /*Renderer*/GIMT_Encode2(0), GIMT_Encode2(GICP_gi_vop3mods),
        GIM_CheckComplexPattern, /*MI*/2, /*Op*/2, /*Renderer*/GIMT_Encode2(1), GIMT_Encode2(GICP_gi_vop3mods),
        // (fmaxnum_ieee:{ *:[f32] } (fminnum:{ *:[f32] } (fmaxnum_ieee:{ *:[f32] } (VOP3Mods:{ *:[f32] } f32:{ *:[f32] }:$src1, i32:{ *:[i32] }:$src1_mods), (VOP3Mods:{ *:[f32] } f32:{ *:[f32] }:$src0, i32:{ *:[i32] }:$src0_mods)), (VOP3Mods:{ *:[f32] } f32:{ *:[f32] }:$src2, i32:{ *:[i32] }:$src2_mods)), (fminnum:{ *:[f32] } (VOP3Mods:{ *:[f32] } f32:{ *:[f32] }:$src1, i32:{ *:[i32] }:$src1_mods), (VOP3Mods:{ *:[f32] } f32:{ *:[f32] }:$src0, i32:{ *:[i32] }:$src0_mods)))<<P:Predicate_fmaxnum_like_nnan>>  =>  (V_MED3_F32_e64:{ *:[f32] } ?:{ *:[i32] }:$src0_mods, ?:{ *:[f32] }:$src0, ?:{ *:[i32] }:$src1_mods, ?:{ *:[f32] }:$src1, ?:{ *:[i32] }:$src2_mods, ?:{ *:[f32] }:$src2, 0:{ *:[i1] }, 0:{ *:[i32] })
        GIR_BuildMI, /*InsnID*/0, /*Opcode*/GIMT_Encode2(AMDGPU::V_MED3_F32_e64),
        GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/0, // DstI[vdst]
        GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(1), /*SubOperand*/1, // src0_mods
        GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(1), /*SubOperand*/0, // src0
        GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/1, // src1_mods
        GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/0, // src1
        GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(2), /*SubOperand*/1, // src2_mods
        GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(2), /*SubOperand*/0, // src2
        GIR_AddImm8, /*InsnID*/0, /*Imm*/0,
        GIR_AddImm8, /*InsnID*/0, /*Imm*/0,
        GIR_ConstrainSelectedInstOperands, /*InsnID*/0,
        GIR_EraseFromParent, /*InsnID*/0,
        // GIR_Coverage, 10100,
        GIR_Done,
      // Label 5117: @374416
      GIM_Try, /*On fail goto*//*Label 5118*/ GIMT_Encode4(374556), // Rule ID 10037 //
        GIM_CheckRegBankForClass, /*MI*/0, /*Op*/0, /*RC*/GIMT_Encode2(AMDGPU::VGPR_32RegClassID),
        GIM_RecordInsn, /*DefineMI*/1, /*MI*/0, /*OpIdx*/1, // MIs[1]
        GIM_CheckOpcode, /*MI*/1, GIMT_Encode2(TargetOpcode::G_FMINNUM),
        GIM_CheckType, /*MI*/1, /*Op*/1, /*Type*/GILLT_s32,
        GIM_CheckType, /*MI*/1, /*Op*/2, /*Type*/GILLT_s32,
        GIM_RecordInsn, /*DefineMI*/2, /*MI*/1, /*OpIdx*/1, // MIs[2]
        GIM_CheckOpcode, /*MI*/2, GIMT_Encode2(TargetOpcode::G_FMAXNUM_IEEE),
        GIM_CheckType, /*MI*/2, /*Op*/1, /*Type*/GILLT_s32,
        GIM_CheckType, /*MI*/2, /*Op*/2, /*Type*/GILLT_s32,
        GIM_RecordInsn, /*DefineMI*/3, /*MI*/0, /*OpIdx*/2, // MIs[3]
        GIM_CheckOpcode, /*MI*/3, GIMT_Encode2(TargetOpcode::G_FMINNUM_IEEE),
        // MIs[3] VOP3Mods:src0:src0_mods
        GIM_CheckIsSameOperand, /*MI*/3, /*OpIdx*/1, /*OtherMI*/2, /*OtherOpIdx*/1,
        // MIs[3] VOP3Mods:src1:src1_mods
        GIM_CheckIsSameOperand, /*MI*/3, /*OpIdx*/2, /*OtherMI*/2, /*OtherOpIdx*/2,
        GIM_CheckCxxInsnPredicate, /*MI*/0, /*FnId*/GIMT_Encode2(GICXXPred_MI_Predicate_fmaxnum_like_nnan),
        GIM_CheckIsSafeToFold, /*InsnID*/1,
        GIM_CheckIsSafeToFold, /*InsnID*/2,
        GIM_CheckIsSafeToFold, /*InsnID*/3,
        GIM_CheckComplexPattern, /*MI*/1, /*Op*/2, /*Renderer*/GIMT_Encode2(2), GIMT_Encode2(GICP_gi_vop3mods),
        GIM_CheckComplexPattern, /*MI*/2, /*Op*/1, /*Renderer*/GIMT_Encode2(0), GIMT_Encode2(GICP_gi_vop3mods),
        GIM_CheckComplexPattern, /*MI*/2, /*Op*/2, /*Renderer*/GIMT_Encode2(1), GIMT_Encode2(GICP_gi_vop3mods),
        // (fmaxnum_ieee:{ *:[f32] } (fminnum:{ *:[f32] } (fmaxnum_ieee:{ *:[f32] } (VOP3Mods:{ *:[f32] } f32:{ *:[f32] }:$src0, i32:{ *:[i32] }:$src0_mods), (VOP3Mods:{ *:[f32] } f32:{ *:[f32] }:$src1, i32:{ *:[i32] }:$src1_mods)), (VOP3Mods:{ *:[f32] } f32:{ *:[f32] }:$src2, i32:{ *:[i32] }:$src2_mods)), (fminnum_ieee:{ *:[f32] } (VOP3Mods:{ *:[f32] } f32:{ *:[f32] }:$src0, i32:{ *:[i32] }:$src0_mods), (VOP3Mods:{ *:[f32] } f32:{ *:[f32] }:$src1, i32:{ *:[i32] }:$src1_mods)))<<P:Predicate_fmaxnum_like_nnan>>  =>  (V_MED3_F32_e64:{ *:[f32] } ?:{ *:[i32] }:$src0_mods, ?:{ *:[f32] }:$src0, ?:{ *:[i32] }:$src1_mods, ?:{ *:[f32] }:$src1, ?:{ *:[i32] }:$src2_mods, ?:{ *:[f32] }:$src2, 0:{ *:[i1] }, 0:{ *:[i32] })
        GIR_BuildMI, /*InsnID*/0, /*Opcode*/GIMT_Encode2(AMDGPU::V_MED3_F32_e64),
        GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/0, // DstI[vdst]
        GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/1, // src0_mods
        GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/0, // src0
        GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(1), /*SubOperand*/1, // src1_mods
        GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(1), /*SubOperand*/0, // src1
        GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(2), /*SubOperand*/1, // src2_mods
        GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(2), /*SubOperand*/0, // src2
        GIR_AddImm8, /*InsnID*/0, /*Imm*/0,
        GIR_AddImm8, /*InsnID*/0, /*Imm*/0,
        GIR_ConstrainSelectedInstOperands, /*InsnID*/0,
        GIR_EraseFromParent, /*InsnID*/0,
        // GIR_Coverage, 10037,
        GIR_Done,
      // Label 5118: @374556
      GIM_Try, /*On fail goto*//*Label 5119*/ GIMT_Encode4(374696), // Rule ID 10038 //
        GIM_CheckRegBankForClass, /*MI*/0, /*Op*/0, /*RC*/GIMT_Encode2(AMDGPU::VGPR_32RegClassID),
        GIM_RecordInsn, /*DefineMI*/1, /*MI*/0, /*OpIdx*/1, // MIs[1]
        GIM_CheckOpcode, /*MI*/1, GIMT_Encode2(TargetOpcode::G_FMINNUM),
        GIM_CheckType, /*MI*/1, /*Op*/1, /*Type*/GILLT_s32,
        GIM_CheckType, /*MI*/1, /*Op*/2, /*Type*/GILLT_s32,
        GIM_RecordInsn, /*DefineMI*/2, /*MI*/1, /*OpIdx*/1, // MIs[2]
        GIM_CheckOpcode, /*MI*/2, GIMT_Encode2(TargetOpcode::G_FMAXNUM_IEEE),
        GIM_CheckType, /*MI*/2, /*Op*/1, /*Type*/GILLT_s32,
        GIM_CheckType, /*MI*/2, /*Op*/2, /*Type*/GILLT_s32,
        GIM_RecordInsn, /*DefineMI*/3, /*MI*/0, /*OpIdx*/2, // MIs[3]
        GIM_CheckOpcode, /*MI*/3, GIMT_Encode2(TargetOpcode::G_FMINNUM_IEEE),
        // MIs[3] VOP3Mods:src1:src1_mods
        GIM_CheckIsSameOperand, /*MI*/3, /*OpIdx*/1, /*OtherMI*/2, /*OtherOpIdx*/2,
        // MIs[3] VOP3Mods:src0:src0_mods
        GIM_CheckIsSameOperand, /*MI*/3, /*OpIdx*/2, /*OtherMI*/2, /*OtherOpIdx*/1,
        GIM_CheckCxxInsnPredicate, /*MI*/0, /*FnId*/GIMT_Encode2(GICXXPred_MI_Predicate_fmaxnum_like_nnan),
        GIM_CheckIsSafeToFold, /*InsnID*/1,
        GIM_CheckIsSafeToFold, /*InsnID*/2,
        GIM_CheckIsSafeToFold, /*InsnID*/3,
        GIM_CheckComplexPattern, /*MI*/1, /*Op*/2, /*Renderer*/GIMT_Encode2(2), GIMT_Encode2(GICP_gi_vop3mods),
        GIM_CheckComplexPattern, /*MI*/2, /*Op*/1, /*Renderer*/GIMT_Encode2(0), GIMT_Encode2(GICP_gi_vop3mods),
        GIM_CheckComplexPattern, /*MI*/2, /*Op*/2, /*Renderer*/GIMT_Encode2(1), GIMT_Encode2(GICP_gi_vop3mods),
        // (fmaxnum_ieee:{ *:[f32] } (fminnum:{ *:[f32] } (fmaxnum_ieee:{ *:[f32] } (VOP3Mods:{ *:[f32] } f32:{ *:[f32] }:$src0, i32:{ *:[i32] }:$src0_mods), (VOP3Mods:{ *:[f32] } f32:{ *:[f32] }:$src1, i32:{ *:[i32] }:$src1_mods)), (VOP3Mods:{ *:[f32] } f32:{ *:[f32] }:$src2, i32:{ *:[i32] }:$src2_mods)), (fminnum_ieee:{ *:[f32] } (VOP3Mods:{ *:[f32] } f32:{ *:[f32] }:$src1, i32:{ *:[i32] }:$src1_mods), (VOP3Mods:{ *:[f32] } f32:{ *:[f32] }:$src0, i32:{ *:[i32] }:$src0_mods)))<<P:Predicate_fmaxnum_like_nnan>>  =>  (V_MED3_F32_e64:{ *:[f32] } ?:{ *:[i32] }:$src0_mods, ?:{ *:[f32] }:$src0, ?:{ *:[i32] }:$src1_mods, ?:{ *:[f32] }:$src1, ?:{ *:[i32] }:$src2_mods, ?:{ *:[f32] }:$src2, 0:{ *:[i1] }, 0:{ *:[i32] })
        GIR_BuildMI, /*InsnID*/0, /*Opcode*/GIMT_Encode2(AMDGPU::V_MED3_F32_e64),
        GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/0, // DstI[vdst]
        GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/1, // src0_mods
        GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/0, // src0
        GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(1), /*SubOperand*/1, // src1_mods
        GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(1), /*SubOperand*/0, // src1
        GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(2), /*SubOperand*/1, // src2_mods
        GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(2), /*SubOperand*/0, // src2
        GIR_AddImm8, /*InsnID*/0, /*Imm*/0,
        GIR_AddImm8, /*InsnID*/0, /*Imm*/0,
        GIR_ConstrainSelectedInstOperands, /*InsnID*/0,
        GIR_EraseFromParent, /*InsnID*/0,
        // GIR_Coverage, 10038,
        GIR_Done,
      // Label 5119: @374696
      GIM_Try, /*On fail goto*//*Label 5120*/ GIMT_Encode4(374836), // Rule ID 10039 //
        GIM_CheckRegBankForClass, /*MI*/0, /*Op*/0, /*RC*/GIMT_Encode2(AMDGPU::VGPR_32RegClassID),
        GIM_RecordInsn, /*DefineMI*/1, /*MI*/0, /*OpIdx*/1, // MIs[1]
        GIM_CheckOpcode, /*MI*/1, GIMT_Encode2(TargetOpcode::G_FMINNUM),
        GIM_CheckType, /*MI*/1, /*Op*/1, /*Type*/GILLT_s32,
        GIM_CheckType, /*MI*/1, /*Op*/2, /*Type*/GILLT_s32,
        GIM_RecordInsn, /*DefineMI*/2, /*MI*/1, /*OpIdx*/1, // MIs[2]
        GIM_CheckOpcode, /*MI*/2, GIMT_Encode2(TargetOpcode::G_FMAXNUM_IEEE),
        GIM_CheckType, /*MI*/2, /*Op*/1, /*Type*/GILLT_s32,
        GIM_CheckType, /*MI*/2, /*Op*/2, /*Type*/GILLT_s32,
        GIM_RecordInsn, /*DefineMI*/3, /*MI*/0, /*OpIdx*/2, // MIs[3]
        GIM_CheckOpcode, /*MI*/3, GIMT_Encode2(TargetOpcode::G_FMINNUM_IEEE),
        // MIs[3] VOP3Mods:src0:src0_mods
        GIM_CheckIsSameOperand, /*MI*/3, /*OpIdx*/1, /*OtherMI*/2, /*OtherOpIdx*/2,
        // MIs[3] VOP3Mods:src1:src1_mods
        GIM_CheckIsSameOperand, /*MI*/3, /*OpIdx*/2, /*OtherMI*/2, /*OtherOpIdx*/1,
        GIM_CheckCxxInsnPredicate, /*MI*/0, /*FnId*/GIMT_Encode2(GICXXPred_MI_Predicate_fmaxnum_like_nnan),
        GIM_CheckIsSafeToFold, /*InsnID*/1,
        GIM_CheckIsSafeToFold, /*InsnID*/2,
        GIM_CheckIsSafeToFold, /*InsnID*/3,
        GIM_CheckComplexPattern, /*MI*/1, /*Op*/2, /*Renderer*/GIMT_Encode2(2), GIMT_Encode2(GICP_gi_vop3mods),
        GIM_CheckComplexPattern, /*MI*/2, /*Op*/1, /*Renderer*/GIMT_Encode2(0), GIMT_Encode2(GICP_gi_vop3mods),
        GIM_CheckComplexPattern, /*MI*/2, /*Op*/2, /*Renderer*/GIMT_Encode2(1), GIMT_Encode2(GICP_gi_vop3mods),
        // (fmaxnum_ieee:{ *:[f32] } (fminnum:{ *:[f32] } (fmaxnum_ieee:{ *:[f32] } (VOP3Mods:{ *:[f32] } f32:{ *:[f32] }:$src1, i32:{ *:[i32] }:$src1_mods), (VOP3Mods:{ *:[f32] } f32:{ *:[f32] }:$src0, i32:{ *:[i32] }:$src0_mods)), (VOP3Mods:{ *:[f32] } f32:{ *:[f32] }:$src2, i32:{ *:[i32] }:$src2_mods)), (fminnum_ieee:{ *:[f32] } (VOP3Mods:{ *:[f32] } f32:{ *:[f32] }:$src0, i32:{ *:[i32] }:$src0_mods), (VOP3Mods:{ *:[f32] } f32:{ *:[f32] }:$src1, i32:{ *:[i32] }:$src1_mods)))<<P:Predicate_fmaxnum_like_nnan>>  =>  (V_MED3_F32_e64:{ *:[f32] } ?:{ *:[i32] }:$src0_mods, ?:{ *:[f32] }:$src0, ?:{ *:[i32] }:$src1_mods, ?:{ *:[f32] }:$src1, ?:{ *:[i32] }:$src2_mods, ?:{ *:[f32] }:$src2, 0:{ *:[i1] }, 0:{ *:[i32] })
        GIR_BuildMI, /*InsnID*/0, /*Opcode*/GIMT_Encode2(AMDGPU::V_MED3_F32_e64),
        GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/0, // DstI[vdst]
        GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(1), /*SubOperand*/1, // src0_mods
        GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(1), /*SubOperand*/0, // src0
        GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/1, // src1_mods
        GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/0, // src1
        GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(2), /*SubOperand*/1, // src2_mods
        GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(2), /*SubOperand*/0, // src2
        GIR_AddImm8, /*InsnID*/0, /*Imm*/0,
        GIR_AddImm8, /*InsnID*/0, /*Imm*/0,
        GIR_ConstrainSelectedInstOperands, /*InsnID*/0,
        GIR_EraseFromParent, /*InsnID*/0,
        // GIR_Coverage, 10039,
        GIR_Done,
      // Label 5120: @374836
      GIM_Try, /*On fail goto*//*Label 5121*/ GIMT_Encode4(374976), // Rule ID 10040 //
        GIM_CheckRegBankForClass, /*MI*/0, /*Op*/0, /*RC*/GIMT_Encode2(AMDGPU::VGPR_32RegClassID),
        GIM_RecordInsn, /*DefineMI*/1, /*MI*/0, /*OpIdx*/1, // MIs[1]
        GIM_CheckOpcode, /*MI*/1, GIMT_Encode2(TargetOpcode::G_FMINNUM),
        GIM_CheckType, /*MI*/1, /*Op*/1, /*Type*/GILLT_s32,
        GIM_CheckType, /*MI*/1, /*Op*/2, /*Type*/GILLT_s32,
        GIM_RecordInsn, /*DefineMI*/2, /*MI*/1, /*OpIdx*/1, // MIs[2]
        GIM_CheckOpcode, /*MI*/2, GIMT_Encode2(TargetOpcode::G_FMAXNUM_IEEE),
        GIM_CheckType, /*MI*/2, /*Op*/1, /*Type*/GILLT_s32,
        GIM_CheckType, /*MI*/2, /*Op*/2, /*Type*/GILLT_s32,
        GIM_RecordInsn, /*DefineMI*/3, /*MI*/0, /*OpIdx*/2, // MIs[3]
        GIM_CheckOpcode, /*MI*/3, GIMT_Encode2(TargetOpcode::G_FMINNUM_IEEE),
        // MIs[3] VOP3Mods:src1:src1_mods
        GIM_CheckIsSameOperand, /*MI*/3, /*OpIdx*/1, /*OtherMI*/2, /*OtherOpIdx*/1,
        // MIs[3] VOP3Mods:src0:src0_mods
        GIM_CheckIsSameOperand, /*MI*/3, /*OpIdx*/2, /*OtherMI*/2, /*OtherOpIdx*/2,
        GIM_CheckCxxInsnPredicate, /*MI*/0, /*FnId*/GIMT_Encode2(GICXXPred_MI_Predicate_fmaxnum_like_nnan),
        GIM_CheckIsSafeToFold, /*InsnID*/1,
        GIM_CheckIsSafeToFold, /*InsnID*/2,
        GIM_CheckIsSafeToFold, /*InsnID*/3,
        GIM_CheckComplexPattern, /*MI*/1, /*Op*/2, /*Renderer*/GIMT_Encode2(2), GIMT_Encode2(GICP_gi_vop3mods),
        GIM_CheckComplexPattern, /*MI*/2, /*Op*/1, /*Renderer*/GIMT_Encode2(0), GIMT_Encode2(GICP_gi_vop3mods),
        GIM_CheckComplexPattern, /*MI*/2, /*Op*/2, /*Renderer*/GIMT_Encode2(1), GIMT_Encode2(GICP_gi_vop3mods),
        // (fmaxnum_ieee:{ *:[f32] } (fminnum:{ *:[f32] } (fmaxnum_ieee:{ *:[f32] } (VOP3Mods:{ *:[f32] } f32:{ *:[f32] }:$src1, i32:{ *:[i32] }:$src1_mods), (VOP3Mods:{ *:[f32] } f32:{ *:[f32] }:$src0, i32:{ *:[i32] }:$src0_mods)), (VOP3Mods:{ *:[f32] } f32:{ *:[f32] }:$src2, i32:{ *:[i32] }:$src2_mods)), (fminnum_ieee:{ *:[f32] } (VOP3Mods:{ *:[f32] } f32:{ *:[f32] }:$src1, i32:{ *:[i32] }:$src1_mods), (VOP3Mods:{ *:[f32] } f32:{ *:[f32] }:$src0, i32:{ *:[i32] }:$src0_mods)))<<P:Predicate_fmaxnum_like_nnan>>  =>  (V_MED3_F32_e64:{ *:[f32] } ?:{ *:[i32] }:$src0_mods, ?:{ *:[f32] }:$src0, ?:{ *:[i32] }:$src1_mods, ?:{ *:[f32] }:$src1, ?:{ *:[i32] }:$src2_mods, ?:{ *:[f32] }:$src2, 0:{ *:[i1] }, 0:{ *:[i32] })
        GIR_BuildMI, /*InsnID*/0, /*Opcode*/GIMT_Encode2(AMDGPU::V_MED3_F32_e64),
        GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/0, // DstI[vdst]
        GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(1), /*SubOperand*/1, // src0_mods
        GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(1), /*SubOperand*/0, // src0
        GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/1, // src1_mods
        GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/0, // src1
        GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(2), /*SubOperand*/1, // src2_mods
        GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(2), /*SubOperand*/0, // src2
        GIR_AddImm8, /*InsnID*/0, /*Imm*/0,
        GIR_AddImm8, /*InsnID*/0, /*Imm*/0,
        GIR_ConstrainSelectedInstOperands, /*InsnID*/0,
        GIR_EraseFromParent, /*InsnID*/0,
        // GIR_Coverage, 10040,
        GIR_Done,
      // Label 5121: @374976
      GIM_Try, /*On fail goto*//*Label 5122*/ GIMT_Encode4(375116), // Rule ID 10046 //
        GIM_CheckRegBankForClass, /*MI*/0, /*Op*/0, /*RC*/GIMT_Encode2(AMDGPU::VGPR_32RegClassID),
        GIM_RecordInsn, /*DefineMI*/1, /*MI*/0, /*OpIdx*/1, // MIs[1]
        GIM_CheckOpcode, /*MI*/1, GIMT_Encode2(TargetOpcode::G_FMINNUM_IEEE),
        GIM_CheckType, /*MI*/1, /*Op*/1, /*Type*/GILLT_s32,
        GIM_CheckType, /*MI*/1, /*Op*/2, /*Type*/GILLT_s32,
        GIM_RecordInsn, /*DefineMI*/2, /*MI*/0, /*OpIdx*/2, // MIs[2]
        GIM_CheckOpcode, /*MI*/2, GIMT_Encode2(TargetOpcode::G_FMINNUM),
        GIM_CheckType, /*MI*/2, /*Op*/1, /*Type*/GILLT_s32,
        GIM_CheckType, /*MI*/2, /*Op*/2, /*Type*/GILLT_s32,
        GIM_RecordInsn, /*DefineMI*/3, /*MI*/2, /*OpIdx*/2, // MIs[3]
        GIM_CheckOpcode, /*MI*/3, GIMT_Encode2(TargetOpcode::G_FMAXNUM),
        // MIs[3] VOP3Mods:src0:src0_mods
        GIM_CheckIsSameOperand, /*MI*/3, /*OpIdx*/1, /*OtherMI*/1, /*OtherOpIdx*/1,
        // MIs[3] VOP3Mods:src1:src1_mods
        GIM_CheckIsSameOperand, /*MI*/3, /*OpIdx*/2, /*OtherMI*/1, /*OtherOpIdx*/2,
        GIM_CheckCxxInsnPredicate, /*MI*/0, /*FnId*/GIMT_Encode2(GICXXPred_MI_Predicate_fmaxnum_like_nnan),
        GIM_CheckIsSafeToFold, /*InsnID*/1,
        GIM_CheckIsSafeToFold, /*InsnID*/2,
        GIM_CheckIsSafeToFold, /*InsnID*/3,
        GIM_CheckComplexPattern, /*MI*/1, /*Op*/1, /*Renderer*/GIMT_Encode2(0), GIMT_Encode2(GICP_gi_vop3mods),
        GIM_CheckComplexPattern, /*MI*/1, /*Op*/2, /*Renderer*/GIMT_Encode2(1), GIMT_Encode2(GICP_gi_vop3mods),
        GIM_CheckComplexPattern, /*MI*/2, /*Op*/1, /*Renderer*/GIMT_Encode2(2), GIMT_Encode2(GICP_gi_vop3mods),
        // (fmaxnum_ieee:{ *:[f32] } (fminnum_ieee:{ *:[f32] } (VOP3Mods:{ *:[f32] } f32:{ *:[f32] }:$src0, i32:{ *:[i32] }:$src0_mods), (VOP3Mods:{ *:[f32] } f32:{ *:[f32] }:$src1, i32:{ *:[i32] }:$src1_mods)), (fminnum:{ *:[f32] } (VOP3Mods:{ *:[f32] } f32:{ *:[f32] }:$src2, i32:{ *:[i32] }:$src2_mods), (fmaxnum:{ *:[f32] } (VOP3Mods:{ *:[f32] } f32:{ *:[f32] }:$src0, i32:{ *:[i32] }:$src0_mods), (VOP3Mods:{ *:[f32] } f32:{ *:[f32] }:$src1, i32:{ *:[i32] }:$src1_mods))))<<P:Predicate_fmaxnum_like_nnan>>  =>  (V_MED3_F32_e64:{ *:[f32] } ?:{ *:[i32] }:$src0_mods, ?:{ *:[f32] }:$src0, ?:{ *:[i32] }:$src1_mods, ?:{ *:[f32] }:$src1, ?:{ *:[i32] }:$src2_mods, ?:{ *:[f32] }:$src2, 0:{ *:[i1] }, 0:{ *:[i32] })
        GIR_BuildMI, /*InsnID*/0, /*Opcode*/GIMT_Encode2(AMDGPU::V_MED3_F32_e64),
        GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/0, // DstI[vdst]
        GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/1, // src0_mods
        GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/0, // src0
        GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(1), /*SubOperand*/1, // src1_mods
        GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(1), /*SubOperand*/0, // src1
        GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(2), /*SubOperand*/1, // src2_mods
        GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(2), /*SubOperand*/0, // src2
        GIR_AddImm8, /*InsnID*/0, /*Imm*/0,
        GIR_AddImm8, /*InsnID*/0, /*Imm*/0,
        GIR_ConstrainSelectedInstOperands, /*InsnID*/0,
        GIR_EraseFromParent, /*InsnID*/0,
        // GIR_Coverage, 10046,
        GIR_Done,
      // Label 5122: @375116
      GIM_Try, /*On fail goto*//*Label 5123*/ GIMT_Encode4(375256), // Rule ID 10047 //
        GIM_CheckRegBankForClass, /*MI*/0, /*Op*/0, /*RC*/GIMT_Encode2(AMDGPU::VGPR_32RegClassID),
        GIM_RecordInsn, /*DefineMI*/1, /*MI*/0, /*OpIdx*/1, // MIs[1]
        GIM_CheckOpcode, /*MI*/1, GIMT_Encode2(TargetOpcode::G_FMINNUM_IEEE),
        GIM_CheckType, /*MI*/1, /*Op*/1, /*Type*/GILLT_s32,
        GIM_CheckType, /*MI*/1, /*Op*/2, /*Type*/GILLT_s32,
        GIM_RecordInsn, /*DefineMI*/2, /*MI*/0, /*OpIdx*/2, // MIs[2]
        GIM_CheckOpcode, /*MI*/2, GIMT_Encode2(TargetOpcode::G_FMINNUM),
        GIM_CheckType, /*MI*/2, /*Op*/1, /*Type*/GILLT_s32,
        GIM_CheckType, /*MI*/2, /*Op*/2, /*Type*/GILLT_s32,
        GIM_RecordInsn, /*DefineMI*/3, /*MI*/2, /*OpIdx*/2, // MIs[3]
        GIM_CheckOpcode, /*MI*/3, GIMT_Encode2(TargetOpcode::G_FMAXNUM),
        // MIs[3] VOP3Mods:src1:src1_mods
        GIM_CheckIsSameOperand, /*MI*/3, /*OpIdx*/1, /*OtherMI*/1, /*OtherOpIdx*/2,
        // MIs[3] VOP3Mods:src0:src0_mods
        GIM_CheckIsSameOperand, /*MI*/3, /*OpIdx*/2, /*OtherMI*/1, /*OtherOpIdx*/1,
        GIM_CheckCxxInsnPredicate, /*MI*/0, /*FnId*/GIMT_Encode2(GICXXPred_MI_Predicate_fmaxnum_like_nnan),
        GIM_CheckIsSafeToFold, /*InsnID*/1,
        GIM_CheckIsSafeToFold, /*InsnID*/2,
        GIM_CheckIsSafeToFold, /*InsnID*/3,
        GIM_CheckComplexPattern, /*MI*/1, /*Op*/1, /*Renderer*/GIMT_Encode2(0), GIMT_Encode2(GICP_gi_vop3mods),
        GIM_CheckComplexPattern, /*MI*/1, /*Op*/2, /*Renderer*/GIMT_Encode2(1), GIMT_Encode2(GICP_gi_vop3mods),
        GIM_CheckComplexPattern, /*MI*/2, /*Op*/1, /*Renderer*/GIMT_Encode2(2), GIMT_Encode2(GICP_gi_vop3mods),
        // (fmaxnum_ieee:{ *:[f32] } (fminnum_ieee:{ *:[f32] } (VOP3Mods:{ *:[f32] } f32:{ *:[f32] }:$src0, i32:{ *:[i32] }:$src0_mods), (VOP3Mods:{ *:[f32] } f32:{ *:[f32] }:$src1, i32:{ *:[i32] }:$src1_mods)), (fminnum:{ *:[f32] } (VOP3Mods:{ *:[f32] } f32:{ *:[f32] }:$src2, i32:{ *:[i32] }:$src2_mods), (fmaxnum:{ *:[f32] } (VOP3Mods:{ *:[f32] } f32:{ *:[f32] }:$src1, i32:{ *:[i32] }:$src1_mods), (VOP3Mods:{ *:[f32] } f32:{ *:[f32] }:$src0, i32:{ *:[i32] }:$src0_mods))))<<P:Predicate_fmaxnum_like_nnan>>  =>  (V_MED3_F32_e64:{ *:[f32] } ?:{ *:[i32] }:$src0_mods, ?:{ *:[f32] }:$src0, ?:{ *:[i32] }:$src1_mods, ?:{ *:[f32] }:$src1, ?:{ *:[i32] }:$src2_mods, ?:{ *:[f32] }:$src2, 0:{ *:[i1] }, 0:{ *:[i32] })
        GIR_BuildMI, /*InsnID*/0, /*Opcode*/GIMT_Encode2(AMDGPU::V_MED3_F32_e64),
        GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/0, // DstI[vdst]
        GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/1, // src0_mods
        GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/0, // src0
        GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(1), /*SubOperand*/1, // src1_mods
        GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(1), /*SubOperand*/0, // src1
        GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(2), /*SubOperand*/1, // src2_mods
        GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(2), /*SubOperand*/0, // src2
        GIR_AddImm8, /*InsnID*/0, /*Imm*/0,
        GIR_AddImm8, /*InsnID*/0, /*Imm*/0,
        GIR_ConstrainSelectedInstOperands, /*InsnID*/0,
        GIR_EraseFromParent, /*InsnID*/0,
        // GIR_Coverage, 10047,
        GIR_Done,
      // Label 5123: @375256
      GIM_Try, /*On fail goto*//*Label 5124*/ GIMT_Encode4(375396), // Rule ID 10050 //
        GIM_CheckRegBankForClass, /*MI*/0, /*Op*/0, /*RC*/GIMT_Encode2(AMDGPU::VGPR_32RegClassID),
        GIM_RecordInsn, /*DefineMI*/1, /*MI*/0, /*OpIdx*/1, // MIs[1]
        GIM_CheckOpcode, /*MI*/1, GIMT_Encode2(TargetOpcode::G_FMINNUM_IEEE),
        GIM_CheckType, /*MI*/1, /*Op*/1, /*Type*/GILLT_s32,
        GIM_CheckType, /*MI*/1, /*Op*/2, /*Type*/GILLT_s32,
        GIM_RecordInsn, /*DefineMI*/2, /*MI*/0, /*OpIdx*/2, // MIs[2]
        GIM_CheckOpcode, /*MI*/2, GIMT_Encode2(TargetOpcode::G_FMINNUM),
        GIM_CheckType, /*MI*/2, /*Op*/1, /*Type*/GILLT_s32,
        GIM_CheckType, /*MI*/2, /*Op*/2, /*Type*/GILLT_s32,
        GIM_RecordInsn, /*DefineMI*/3, /*MI*/2, /*OpIdx*/2, // MIs[3]
        GIM_CheckOpcode, /*MI*/3, GIMT_Encode2(TargetOpcode::G_FMAXNUM),
        // MIs[3] VOP3Mods:src0:src0_mods
        GIM_CheckIsSameOperand, /*MI*/3, /*OpIdx*/1, /*OtherMI*/1, /*OtherOpIdx*/2,
        // MIs[3] VOP3Mods:src1:src1_mods
        GIM_CheckIsSameOperand, /*MI*/3, /*OpIdx*/2, /*OtherMI*/1, /*OtherOpIdx*/1,
        GIM_CheckCxxInsnPredicate, /*MI*/0, /*FnId*/GIMT_Encode2(GICXXPred_MI_Predicate_fmaxnum_like_nnan),
        GIM_CheckIsSafeToFold, /*InsnID*/1,
        GIM_CheckIsSafeToFold, /*InsnID*/2,
        GIM_CheckIsSafeToFold, /*InsnID*/3,
        GIM_CheckComplexPattern, /*MI*/1, /*Op*/1, /*Renderer*/GIMT_Encode2(0), GIMT_Encode2(GICP_gi_vop3mods),
        GIM_CheckComplexPattern, /*MI*/1, /*Op*/2, /*Renderer*/GIMT_Encode2(1), GIMT_Encode2(GICP_gi_vop3mods),
        GIM_CheckComplexPattern, /*MI*/2, /*Op*/1, /*Renderer*/GIMT_Encode2(2), GIMT_Encode2(GICP_gi_vop3mods),
        // (fmaxnum_ieee:{ *:[f32] } (fminnum_ieee:{ *:[f32] } (VOP3Mods:{ *:[f32] } f32:{ *:[f32] }:$src1, i32:{ *:[i32] }:$src1_mods), (VOP3Mods:{ *:[f32] } f32:{ *:[f32] }:$src0, i32:{ *:[i32] }:$src0_mods)), (fminnum:{ *:[f32] } (VOP3Mods:{ *:[f32] } f32:{ *:[f32] }:$src2, i32:{ *:[i32] }:$src2_mods), (fmaxnum:{ *:[f32] } (VOP3Mods:{ *:[f32] } f32:{ *:[f32] }:$src0, i32:{ *:[i32] }:$src0_mods), (VOP3Mods:{ *:[f32] } f32:{ *:[f32] }:$src1, i32:{ *:[i32] }:$src1_mods))))<<P:Predicate_fmaxnum_like_nnan>>  =>  (V_MED3_F32_e64:{ *:[f32] } ?:{ *:[i32] }:$src0_mods, ?:{ *:[f32] }:$src0, ?:{ *:[i32] }:$src1_mods, ?:{ *:[f32] }:$src1, ?:{ *:[i32] }:$src2_mods, ?:{ *:[f32] }:$src2, 0:{ *:[i1] }, 0:{ *:[i32] })
        GIR_BuildMI, /*InsnID*/0, /*Opcode*/GIMT_Encode2(AMDGPU::V_MED3_F32_e64),
        GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/0, // DstI[vdst]
        GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(1), /*SubOperand*/1, // src0_mods
        GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(1), /*SubOperand*/0, // src0
        GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/1, // src1_mods
        GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/0, // src1
        GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(2), /*SubOperand*/1, // src2_mods
        GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(2), /*SubOperand*/0, // src2
        GIR_AddImm8, /*InsnID*/0, /*Imm*/0,
        GIR_AddImm8, /*InsnID*/0, /*Imm*/0,
        GIR_ConstrainSelectedInstOperands, /*InsnID*/0,
        GIR_EraseFromParent, /*InsnID*/0,
        // GIR_Coverage, 10050,
        GIR_Done,
      // Label 5124: @375396
      GIM_Try, /*On fail goto*//*Label 5125*/ GIMT_Encode4(375536), // Rule ID 10051 //
        GIM_CheckRegBankForClass, /*MI*/0, /*Op*/0, /*RC*/GIMT_Encode2(AMDGPU::VGPR_32RegClassID),
        GIM_RecordInsn, /*DefineMI*/1, /*MI*/0, /*OpIdx*/1, // MIs[1]
        GIM_CheckOpcode, /*MI*/1, GIMT_Encode2(TargetOpcode::G_FMINNUM_IEEE),
        GIM_CheckType, /*MI*/1, /*Op*/1, /*Type*/GILLT_s32,
        GIM_CheckType, /*MI*/1, /*Op*/2, /*Type*/GILLT_s32,
        GIM_RecordInsn, /*DefineMI*/2, /*MI*/0, /*OpIdx*/2, // MIs[2]
        GIM_CheckOpcode, /*MI*/2, GIMT_Encode2(TargetOpcode::G_FMINNUM),
        GIM_CheckType, /*MI*/2, /*Op*/1, /*Type*/GILLT_s32,
        GIM_CheckType, /*MI*/2, /*Op*/2, /*Type*/GILLT_s32,
        GIM_RecordInsn, /*DefineMI*/3, /*MI*/2, /*OpIdx*/2, // MIs[3]
        GIM_CheckOpcode, /*MI*/3, GIMT_Encode2(TargetOpcode::G_FMAXNUM),
        // MIs[3] VOP3Mods:src1:src1_mods
        GIM_CheckIsSameOperand, /*MI*/3, /*OpIdx*/1, /*OtherMI*/1, /*OtherOpIdx*/1,
        // MIs[3] VOP3Mods:src0:src0_mods
        GIM_CheckIsSameOperand, /*MI*/3, /*OpIdx*/2, /*OtherMI*/1, /*OtherOpIdx*/2,
        GIM_CheckCxxInsnPredicate, /*MI*/0, /*FnId*/GIMT_Encode2(GICXXPred_MI_Predicate_fmaxnum_like_nnan),
        GIM_CheckIsSafeToFold, /*InsnID*/1,
        GIM_CheckIsSafeToFold, /*InsnID*/2,
        GIM_CheckIsSafeToFold, /*InsnID*/3,
        GIM_CheckComplexPattern, /*MI*/1, /*Op*/1, /*Renderer*/GIMT_Encode2(0), GIMT_Encode2(GICP_gi_vop3mods),
        GIM_CheckComplexPattern, /*MI*/1, /*Op*/2, /*Renderer*/GIMT_Encode2(1), GIMT_Encode2(GICP_gi_vop3mods),
        GIM_CheckComplexPattern, /*MI*/2, /*Op*/1, /*Renderer*/GIMT_Encode2(2), GIMT_Encode2(GICP_gi_vop3mods),
        // (fmaxnum_ieee:{ *:[f32] } (fminnum_ieee:{ *:[f32] } (VOP3Mods:{ *:[f32] } f32:{ *:[f32] }:$src1, i32:{ *:[i32] }:$src1_mods), (VOP3Mods:{ *:[f32] } f32:{ *:[f32] }:$src0, i32:{ *:[i32] }:$src0_mods)), (fminnum:{ *:[f32] } (VOP3Mods:{ *:[f32] } f32:{ *:[f32] }:$src2, i32:{ *:[i32] }:$src2_mods), (fmaxnum:{ *:[f32] } (VOP3Mods:{ *:[f32] } f32:{ *:[f32] }:$src1, i32:{ *:[i32] }:$src1_mods), (VOP3Mods:{ *:[f32] } f32:{ *:[f32] }:$src0, i32:{ *:[i32] }:$src0_mods))))<<P:Predicate_fmaxnum_like_nnan>>  =>  (V_MED3_F32_e64:{ *:[f32] } ?:{ *:[i32] }:$src0_mods, ?:{ *:[f32] }:$src0, ?:{ *:[i32] }:$src1_mods, ?:{ *:[f32] }:$src1, ?:{ *:[i32] }:$src2_mods, ?:{ *:[f32] }:$src2, 0:{ *:[i1] }, 0:{ *:[i32] })
        GIR_BuildMI, /*InsnID*/0, /*Opcode*/GIMT_Encode2(AMDGPU::V_MED3_F32_e64),
        GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/0, // DstI[vdst]
        GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(1), /*SubOperand*/1, // src0_mods
        GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(1), /*SubOperand*/0, // src0
        GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/1, // src1_mods
        GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/0, // src1
        GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(2), /*SubOperand*/1, // src2_mods
        GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(2), /*SubOperand*/0, // src2
        GIR_AddImm8, /*InsnID*/0, /*Imm*/0,
        GIR_AddImm8, /*InsnID*/0, /*Imm*/0,
        GIR_ConstrainSelectedInstOperands, /*InsnID*/0,
        GIR_EraseFromParent, /*InsnID*/0,
        // GIR_Coverage, 10051,
        GIR_Done,
      // Label 5125: @375536
      GIM_Try, /*On fail goto*//*Label 5126*/ GIMT_Encode4(375676), // Rule ID 10031 //
        GIM_CheckRegBankForClass, /*MI*/0, /*Op*/0, /*RC*/GIMT_Encode2(AMDGPU::VGPR_32RegClassID),
        GIM_RecordInsn, /*DefineMI*/1, /*MI*/0, /*OpIdx*/1, // MIs[1]
        GIM_CheckOpcode, /*MI*/1, GIMT_Encode2(TargetOpcode::G_FMINNUM_IEEE),
        GIM_CheckType, /*MI*/1, /*Op*/1, /*Type*/GILLT_s32,
        GIM_CheckType, /*MI*/1, /*Op*/2, /*Type*/GILLT_s32,
        GIM_RecordInsn, /*DefineMI*/2, /*MI*/0, /*OpIdx*/2, // MIs[2]
        GIM_CheckOpcode, /*MI*/2, GIMT_Encode2(TargetOpcode::G_FMINNUM),
        GIM_CheckType, /*MI*/2, /*Op*/1, /*Type*/GILLT_s32,
        GIM_CheckType, /*MI*/2, /*Op*/2, /*Type*/GILLT_s32,
        GIM_RecordInsn, /*DefineMI*/3, /*MI*/2, /*OpIdx*/2, // MIs[3]
        GIM_CheckOpcode, /*MI*/3, GIMT_Encode2(TargetOpcode::G_FMAXNUM_IEEE),
        // MIs[3] VOP3Mods:src0:src0_mods
        GIM_CheckIsSameOperand, /*MI*/3, /*OpIdx*/1, /*OtherMI*/1, /*OtherOpIdx*/1,
        // MIs[3] VOP3Mods:src1:src1_mods
        GIM_CheckIsSameOperand, /*MI*/3, /*OpIdx*/2, /*OtherMI*/1, /*OtherOpIdx*/2,
        GIM_CheckCxxInsnPredicate, /*MI*/0, /*FnId*/GIMT_Encode2(GICXXPred_MI_Predicate_fmaxnum_like_nnan),
        GIM_CheckIsSafeToFold, /*InsnID*/1,
        GIM_CheckIsSafeToFold, /*InsnID*/2,
        GIM_CheckIsSafeToFold, /*InsnID*/3,
        GIM_CheckComplexPattern, /*MI*/1, /*Op*/1, /*Renderer*/GIMT_Encode2(0), GIMT_Encode2(GICP_gi_vop3mods),
        GIM_CheckComplexPattern, /*MI*/1, /*Op*/2, /*Renderer*/GIMT_Encode2(1), GIMT_Encode2(GICP_gi_vop3mods),
        GIM_CheckComplexPattern, /*MI*/2, /*Op*/1, /*Renderer*/GIMT_Encode2(2), GIMT_Encode2(GICP_gi_vop3mods),
        // (fmaxnum_ieee:{ *:[f32] } (fminnum_ieee:{ *:[f32] } (VOP3Mods:{ *:[f32] } f32:{ *:[f32] }:$src0, i32:{ *:[i32] }:$src0_mods), (VOP3Mods:{ *:[f32] } f32:{ *:[f32] }:$src1, i32:{ *:[i32] }:$src1_mods)), (fminnum:{ *:[f32] } (VOP3Mods:{ *:[f32] } f32:{ *:[f32] }:$src2, i32:{ *:[i32] }:$src2_mods), (fmaxnum_ieee:{ *:[f32] } (VOP3Mods:{ *:[f32] } f32:{ *:[f32] }:$src0, i32:{ *:[i32] }:$src0_mods), (VOP3Mods:{ *:[f32] } f32:{ *:[f32] }:$src1, i32:{ *:[i32] }:$src1_mods))))<<P:Predicate_fmaxnum_like_nnan>>  =>  (V_MED3_F32_e64:{ *:[f32] } ?:{ *:[i32] }:$src0_mods, ?:{ *:[f32] }:$src0, ?:{ *:[i32] }:$src1_mods, ?:{ *:[f32] }:$src1, ?:{ *:[i32] }:$src2_mods, ?:{ *:[f32] }:$src2, 0:{ *:[i1] }, 0:{ *:[i32] })
        GIR_BuildMI, /*InsnID*/0, /*Opcode*/GIMT_Encode2(AMDGPU::V_MED3_F32_e64),
        GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/0, // DstI[vdst]
        GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/1, // src0_mods
        GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/0, // src0
        GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(1), /*SubOperand*/1, // src1_mods
        GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(1), /*SubOperand*/0, // src1
        GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(2), /*SubOperand*/1, // src2_mods
        GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(2), /*SubOperand*/0, // src2
        GIR_AddImm8, /*InsnID*/0, /*Imm*/0,
        GIR_AddImm8, /*InsnID*/0, /*Imm*/0,
        GIR_ConstrainSelectedInstOperands, /*InsnID*/0,
        GIR_EraseFromParent, /*InsnID*/0,
        // GIR_Coverage, 10031,
        GIR_Done,
      // Label 5126: @375676
      GIM_Try, /*On fail goto*//*Label 5127*/ GIMT_Encode4(375816), // Rule ID 10032 //
        GIM_CheckRegBankForClass, /*MI*/0, /*Op*/0, /*RC*/GIMT_Encode2(AMDGPU::VGPR_32RegClassID),
        GIM_RecordInsn, /*DefineMI*/1, /*MI*/0, /*OpIdx*/1, // MIs[1]
        GIM_CheckOpcode, /*MI*/1, GIMT_Encode2(TargetOpcode::G_FMINNUM_IEEE),
        GIM_CheckType, /*MI*/1, /*Op*/1, /*Type*/GILLT_s32,
        GIM_CheckType, /*MI*/1, /*Op*/2, /*Type*/GILLT_s32,
        GIM_RecordInsn, /*DefineMI*/2, /*MI*/0, /*OpIdx*/2, // MIs[2]
        GIM_CheckOpcode, /*MI*/2, GIMT_Encode2(TargetOpcode::G_FMINNUM),
        GIM_CheckType, /*MI*/2, /*Op*/1, /*Type*/GILLT_s32,
        GIM_CheckType, /*MI*/2, /*Op*/2, /*Type*/GILLT_s32,
        GIM_RecordInsn, /*DefineMI*/3, /*MI*/2, /*OpIdx*/2, // MIs[3]
        GIM_CheckOpcode, /*MI*/3, GIMT_Encode2(TargetOpcode::G_FMAXNUM_IEEE),
        // MIs[3] VOP3Mods:src1:src1_mods
        GIM_CheckIsSameOperand, /*MI*/3, /*OpIdx*/1, /*OtherMI*/1, /*OtherOpIdx*/2,
        // MIs[3] VOP3Mods:src0:src0_mods
        GIM_CheckIsSameOperand, /*MI*/3, /*OpIdx*/2, /*OtherMI*/1, /*OtherOpIdx*/1,
        GIM_CheckCxxInsnPredicate, /*MI*/0, /*FnId*/GIMT_Encode2(GICXXPred_MI_Predicate_fmaxnum_like_nnan),
        GIM_CheckIsSafeToFold, /*InsnID*/1,
        GIM_CheckIsSafeToFold, /*InsnID*/2,
        GIM_CheckIsSafeToFold, /*InsnID*/3,
        GIM_CheckComplexPattern, /*MI*/1, /*Op*/1, /*Renderer*/GIMT_Encode2(0), GIMT_Encode2(GICP_gi_vop3mods),
        GIM_CheckComplexPattern, /*MI*/1, /*Op*/2, /*Renderer*/GIMT_Encode2(1), GIMT_Encode2(GICP_gi_vop3mods),
        GIM_CheckComplexPattern, /*MI*/2, /*Op*/1, /*Renderer*/GIMT_Encode2(2), GIMT_Encode2(GICP_gi_vop3mods),
        // (fmaxnum_ieee:{ *:[f32] } (fminnum_ieee:{ *:[f32] } (VOP3Mods:{ *:[f32] } f32:{ *:[f32] }:$src0, i32:{ *:[i32] }:$src0_mods), (VOP3Mods:{ *:[f32] } f32:{ *:[f32] }:$src1, i32:{ *:[i32] }:$src1_mods)), (fminnum:{ *:[f32] } (VOP3Mods:{ *:[f32] } f32:{ *:[f32] }:$src2, i32:{ *:[i32] }:$src2_mods), (fmaxnum_ieee:{ *:[f32] } (VOP3Mods:{ *:[f32] } f32:{ *:[f32] }:$src1, i32:{ *:[i32] }:$src1_mods), (VOP3Mods:{ *:[f32] } f32:{ *:[f32] }:$src0, i32:{ *:[i32] }:$src0_mods))))<<P:Predicate_fmaxnum_like_nnan>>  =>  (V_MED3_F32_e64:{ *:[f32] } ?:{ *:[i32] }:$src0_mods, ?:{ *:[f32] }:$src0, ?:{ *:[i32] }:$src1_mods, ?:{ *:[f32] }:$src1, ?:{ *:[i32] }:$src2_mods, ?:{ *:[f32] }:$src2, 0:{ *:[i1] }, 0:{ *:[i32] })
        GIR_BuildMI, /*InsnID*/0, /*Opcode*/GIMT_Encode2(AMDGPU::V_MED3_F32_e64),
        GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/0, // DstI[vdst]
        GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/1, // src0_mods
        GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/0, // src0
        GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(1), /*SubOperand*/1, // src1_mods
        GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(1), /*SubOperand*/0, // src1
        GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(2), /*SubOperand*/1, // src2_mods
        GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(2), /*SubOperand*/0, // src2
        GIR_AddImm8, /*InsnID*/0, /*Imm*/0,
        GIR_AddImm8, /*InsnID*/0, /*Imm*/0,
        GIR_ConstrainSelectedInstOperands, /*InsnID*/0,
        GIR_EraseFromParent, /*InsnID*/0,
        // GIR_Coverage, 10032,
        GIR_Done,
      // Label 5127: @375816
      GIM_Try, /*On fail goto*//*Label 5128*/ GIMT_Encode4(375956), // Rule ID 10035 //
        GIM_CheckRegBankForClass, /*MI*/0, /*Op*/0, /*RC*/GIMT_Encode2(AMDGPU::VGPR_32RegClassID),
        GIM_RecordInsn, /*DefineMI*/1, /*MI*/0, /*OpIdx*/1, // MIs[1]
        GIM_CheckOpcode, /*MI*/1, GIMT_Encode2(TargetOpcode::G_FMINNUM_IEEE),
        GIM_CheckType, /*MI*/1, /*Op*/1, /*Type*/GILLT_s32,
        GIM_CheckType, /*MI*/1, /*Op*/2, /*Type*/GILLT_s32,
        GIM_RecordInsn, /*DefineMI*/2, /*MI*/0, /*OpIdx*/2, // MIs[2]
        GIM_CheckOpcode, /*MI*/2, GIMT_Encode2(TargetOpcode::G_FMINNUM),
        GIM_CheckType, /*MI*/2, /*Op*/1, /*Type*/GILLT_s32,
        GIM_CheckType, /*MI*/2, /*Op*/2, /*Type*/GILLT_s32,
        GIM_RecordInsn, /*DefineMI*/3, /*MI*/2, /*OpIdx*/2, // MIs[3]
        GIM_CheckOpcode, /*MI*/3, GIMT_Encode2(TargetOpcode::G_FMAXNUM_IEEE),
        // MIs[3] VOP3Mods:src0:src0_mods
        GIM_CheckIsSameOperand, /*MI*/3, /*OpIdx*/1, /*OtherMI*/1, /*OtherOpIdx*/2,
        // MIs[3] VOP3Mods:src1:src1_mods
        GIM_CheckIsSameOperand, /*MI*/3, /*OpIdx*/2, /*OtherMI*/1, /*OtherOpIdx*/1,
        GIM_CheckCxxInsnPredicate, /*MI*/0, /*FnId*/GIMT_Encode2(GICXXPred_MI_Predicate_fmaxnum_like_nnan),
        GIM_CheckIsSafeToFold, /*InsnID*/1,
        GIM_CheckIsSafeToFold, /*InsnID*/2,
        GIM_CheckIsSafeToFold, /*InsnID*/3,
        GIM_CheckComplexPattern, /*MI*/1, /*Op*/1, /*Renderer*/GIMT_Encode2(0), GIMT_Encode2(GICP_gi_vop3mods),
        GIM_CheckComplexPattern, /*MI*/1, /*Op*/2, /*Renderer*/GIMT_Encode2(1), GIMT_Encode2(GICP_gi_vop3mods),
        GIM_CheckComplexPattern, /*MI*/2, /*Op*/1, /*Renderer*/GIMT_Encode2(2), GIMT_Encode2(GICP_gi_vop3mods),
        // (fmaxnum_ieee:{ *:[f32] } (fminnum_ieee:{ *:[f32] } (VOP3Mods:{ *:[f32] } f32:{ *:[f32] }:$src1, i32:{ *:[i32] }:$src1_mods), (VOP3Mods:{ *:[f32] } f32:{ *:[f32] }:$src0, i32:{ *:[i32] }:$src0_mods)), (fminnum:{ *:[f32] } (VOP3Mods:{ *:[f32] } f32:{ *:[f32] }:$src2, i32:{ *:[i32] }:$src2_mods), (fmaxnum_ieee:{ *:[f32] } (VOP3Mods:{ *:[f32] } f32:{ *:[f32] }:$src0, i32:{ *:[i32] }:$src0_mods), (VOP3Mods:{ *:[f32] } f32:{ *:[f32] }:$src1, i32:{ *:[i32] }:$src1_mods))))<<P:Predicate_fmaxnum_like_nnan>>  =>  (V_MED3_F32_e64:{ *:[f32] } ?:{ *:[i32] }:$src0_mods, ?:{ *:[f32] }:$src0, ?:{ *:[i32] }:$src1_mods, ?:{ *:[f32] }:$src1, ?:{ *:[i32] }:$src2_mods, ?:{ *:[f32] }:$src2, 0:{ *:[i1] }, 0:{ *:[i32] })
        GIR_BuildMI, /*InsnID*/0, /*Opcode*/GIMT_Encode2(AMDGPU::V_MED3_F32_e64),
        GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/0, // DstI[vdst]
        GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(1), /*SubOperand*/1, // src0_mods
        GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(1), /*SubOperand*/0, // src0
        GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/1, // src1_mods
        GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/0, // src1
        GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(2), /*SubOperand*/1, // src2_mods
        GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(2), /*SubOperand*/0, // src2
        GIR_AddImm8, /*InsnID*/0, /*Imm*/0,
        GIR_AddImm8, /*InsnID*/0, /*Imm*/0,
        GIR_ConstrainSelectedInstOperands, /*InsnID*/0,
        GIR_EraseFromParent, /*InsnID*/0,
        // GIR_Coverage, 10035,
        GIR_Done,
      // Label 5128: @375956
      GIM_Try, /*On fail goto*//*Label 5129*/ GIMT_Encode4(376096), // Rule ID 10036 //
        GIM_CheckRegBankForClass, /*MI*/0, /*Op*/0, /*RC*/GIMT_Encode2(AMDGPU::VGPR_32RegClassID),
        GIM_RecordInsn, /*DefineMI*/1, /*MI*/0, /*OpIdx*/1, // MIs[1]
        GIM_CheckOpcode, /*MI*/1, GIMT_Encode2(TargetOpcode::G_FMINNUM_IEEE),
        GIM_CheckType, /*MI*/1, /*Op*/1, /*Type*/GILLT_s32,
        GIM_CheckType, /*MI*/1, /*Op*/2, /*Type*/GILLT_s32,
        GIM_RecordInsn, /*DefineMI*/2, /*MI*/0, /*OpIdx*/2, // MIs[2]
        GIM_CheckOpcode, /*MI*/2, GIMT_Encode2(TargetOpcode::G_FMINNUM),
        GIM_CheckType, /*MI*/2, /*Op*/1, /*Type*/GILLT_s32,
        GIM_CheckType, /*MI*/2, /*Op*/2, /*Type*/GILLT_s32,
        GIM_RecordInsn, /*DefineMI*/3, /*MI*/2, /*OpIdx*/2, // MIs[3]
        GIM_CheckOpcode, /*MI*/3, GIMT_Encode2(TargetOpcode::G_FMAXNUM_IEEE),
        // MIs[3] VOP3Mods:src1:src1_mods
        GIM_CheckIsSameOperand, /*MI*/3, /*OpIdx*/1, /*OtherMI*/1, /*OtherOpIdx*/1,
        // MIs[3] VOP3Mods:src0:src0_mods
        GIM_CheckIsSameOperand, /*MI*/3, /*OpIdx*/2, /*OtherMI*/1, /*OtherOpIdx*/2,
        GIM_CheckCxxInsnPredicate, /*MI*/0, /*FnId*/GIMT_Encode2(GICXXPred_MI_Predicate_fmaxnum_like_nnan),
        GIM_CheckIsSafeToFold, /*InsnID*/1,
        GIM_CheckIsSafeToFold, /*InsnID*/2,
        GIM_CheckIsSafeToFold, /*InsnID*/3,
        GIM_CheckComplexPattern, /*MI*/1, /*Op*/1, /*Renderer*/GIMT_Encode2(0), GIMT_Encode2(GICP_gi_vop3mods),
        GIM_CheckComplexPattern, /*MI*/1, /*Op*/2, /*Renderer*/GIMT_Encode2(1), GIMT_Encode2(GICP_gi_vop3mods),
        GIM_CheckComplexPattern, /*MI*/2, /*Op*/1, /*Renderer*/GIMT_Encode2(2), GIMT_Encode2(GICP_gi_vop3mods),
        // (fmaxnum_ieee:{ *:[f32] } (fminnum_ieee:{ *:[f32] } (VOP3Mods:{ *:[f32] } f32:{ *:[f32] }:$src1, i32:{ *:[i32] }:$src1_mods), (VOP3Mods:{ *:[f32] } f32:{ *:[f32] }:$src0, i32:{ *:[i32] }:$src0_mods)), (fminnum:{ *:[f32] } (VOP3Mods:{ *:[f32] } f32:{ *:[f32] }:$src2, i32:{ *:[i32] }:$src2_mods), (fmaxnum_ieee:{ *:[f32] } (VOP3Mods:{ *:[f32] } f32:{ *:[f32] }:$src1, i32:{ *:[i32] }:$src1_mods), (VOP3Mods:{ *:[f32] } f32:{ *:[f32] }:$src0, i32:{ *:[i32] }:$src0_mods))))<<P:Predicate_fmaxnum_like_nnan>>  =>  (V_MED3_F32_e64:{ *:[f32] } ?:{ *:[i32] }:$src0_mods, ?:{ *:[f32] }:$src0, ?:{ *:[i32] }:$src1_mods, ?:{ *:[f32] }:$src1, ?:{ *:[i32] }:$src2_mods, ?:{ *:[f32] }:$src2, 0:{ *:[i1] }, 0:{ *:[i32] })
        GIR_BuildMI, /*InsnID*/0, /*Opcode*/GIMT_Encode2(AMDGPU::V_MED3_F32_e64),
        GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/0, // DstI[vdst]
        GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(1), /*SubOperand*/1, // src0_mods
        GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(1), /*SubOperand*/0, // src0
        GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/1, // src1_mods
        GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/0, // src1
        GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(2), /*SubOperand*/1, // src2_mods
        GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(2), /*SubOperand*/0, // src2
        GIR_AddImm8, /*InsnID*/0, /*Imm*/0,
        GIR_AddImm8, /*InsnID*/0, /*Imm*/0,
        GIR_ConstrainSelectedInstOperands, /*InsnID*/0,
        GIR_EraseFromParent, /*InsnID*/0,
        // GIR_Coverage, 10036,
        GIR_Done,
      // Label 5129: @376096
      GIM_Try, /*On fail goto*//*Label 5130*/ GIMT_Encode4(376236), // Rule ID 6485 //
        GIM_CheckRegBankForClass, /*MI*/0, /*Op*/0, /*RC*/GIMT_Encode2(AMDGPU::VGPR_32RegClassID),
        GIM_RecordInsn, /*DefineMI*/1, /*MI*/0, /*OpIdx*/1, // MIs[1]
        GIM_CheckOpcode, /*MI*/1, GIMT_Encode2(TargetOpcode::G_FMINNUM_IEEE),
        GIM_CheckType, /*MI*/1, /*Op*/1, /*Type*/GILLT_s32,
        GIM_CheckType, /*MI*/1, /*Op*/2, /*Type*/GILLT_s32,
        GIM_RecordInsn, /*DefineMI*/2, /*MI*/0, /*OpIdx*/2, // MIs[2]
        GIM_CheckOpcode, /*MI*/2, GIMT_Encode2(TargetOpcode::G_FMINNUM),
        GIM_CheckType, /*MI*/2, /*Op*/1, /*Type*/GILLT_s32,
        GIM_CheckType, /*MI*/2, /*Op*/2, /*Type*/GILLT_s32,
        GIM_RecordInsn, /*DefineMI*/3, /*MI*/2, /*OpIdx*/1, // MIs[3]
        GIM_CheckOpcode, /*MI*/3, GIMT_Encode2(TargetOpcode::G_FMAXNUM),
        // MIs[3] VOP3Mods:src0:src0_mods
        GIM_CheckIsSameOperand, /*MI*/3, /*OpIdx*/1, /*OtherMI*/1, /*OtherOpIdx*/1,
        // MIs[3] VOP3Mods:src1:src1_mods
        GIM_CheckIsSameOperand, /*MI*/3, /*OpIdx*/2, /*OtherMI*/1, /*OtherOpIdx*/2,
        GIM_CheckCxxInsnPredicate, /*MI*/0, /*FnId*/GIMT_Encode2(GICXXPred_MI_Predicate_fmaxnum_like_nnan),
        GIM_CheckIsSafeToFold, /*InsnID*/1,
        GIM_CheckIsSafeToFold, /*InsnID*/2,
        GIM_CheckIsSafeToFold, /*InsnID*/3,
        GIM_CheckComplexPattern, /*MI*/1, /*Op*/1, /*Renderer*/GIMT_Encode2(0), GIMT_Encode2(GICP_gi_vop3mods),
        GIM_CheckComplexPattern, /*MI*/1, /*Op*/2, /*Renderer*/GIMT_Encode2(1), GIMT_Encode2(GICP_gi_vop3mods),
        GIM_CheckComplexPattern, /*MI*/2, /*Op*/2, /*Renderer*/GIMT_Encode2(2), GIMT_Encode2(GICP_gi_vop3mods),
        // (fmaxnum_ieee:{ *:[f32] } (fminnum_ieee:{ *:[f32] } (VOP3Mods:{ *:[f32] } f32:{ *:[f32] }:$src0, i32:{ *:[i32] }:$src0_mods), (VOP3Mods:{ *:[f32] } f32:{ *:[f32] }:$src1, i32:{ *:[i32] }:$src1_mods)), (fminnum:{ *:[f32] } (fmaxnum:{ *:[f32] } (VOP3Mods:{ *:[f32] } f32:{ *:[f32] }:$src0, i32:{ *:[i32] }:$src0_mods), (VOP3Mods:{ *:[f32] } f32:{ *:[f32] }:$src1, i32:{ *:[i32] }:$src1_mods)), (VOP3Mods:{ *:[f32] } f32:{ *:[f32] }:$src2, i32:{ *:[i32] }:$src2_mods)))<<P:Predicate_fmaxnum_like_nnan>>  =>  (V_MED3_F32_e64:{ *:[f32] } ?:{ *:[i32] }:$src0_mods, ?:{ *:[f32] }:$src0, ?:{ *:[i32] }:$src1_mods, ?:{ *:[f32] }:$src1, ?:{ *:[i32] }:$src2_mods, ?:{ *:[f32] }:$src2, 0:{ *:[i1] }, 0:{ *:[i32] })
        GIR_BuildMI, /*InsnID*/0, /*Opcode*/GIMT_Encode2(AMDGPU::V_MED3_F32_e64),
        GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/0, // DstI[vdst]
        GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/1, // src0_mods
        GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/0, // src0
        GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(1), /*SubOperand*/1, // src1_mods
        GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(1), /*SubOperand*/0, // src1
        GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(2), /*SubOperand*/1, // src2_mods
        GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(2), /*SubOperand*/0, // src2
        GIR_AddImm8, /*InsnID*/0, /*Imm*/0,
        GIR_AddImm8, /*InsnID*/0, /*Imm*/0,
        GIR_ConstrainSelectedInstOperands, /*InsnID*/0,
        GIR_EraseFromParent, /*InsnID*/0,
        // GIR_Coverage, 6485,
        GIR_Done,
      // Label 5130: @376236
      GIM_Try, /*On fail goto*//*Label 5131*/ GIMT_Encode4(376376), // Rule ID 10045 //
        GIM_CheckRegBankForClass, /*MI*/0, /*Op*/0, /*RC*/GIMT_Encode2(AMDGPU::VGPR_32RegClassID),
        GIM_RecordInsn, /*DefineMI*/1, /*MI*/0, /*OpIdx*/1, // MIs[1]
        GIM_CheckOpcode, /*MI*/1, GIMT_Encode2(TargetOpcode::G_FMINNUM_IEEE),
        GIM_CheckType, /*MI*/1, /*Op*/1, /*Type*/GILLT_s32,
        GIM_CheckType, /*MI*/1, /*Op*/2, /*Type*/GILLT_s32,
        GIM_RecordInsn, /*DefineMI*/2, /*MI*/0, /*OpIdx*/2, // MIs[2]
        GIM_CheckOpcode, /*MI*/2, GIMT_Encode2(TargetOpcode::G_FMINNUM),
        GIM_CheckType, /*MI*/2, /*Op*/1, /*Type*/GILLT_s32,
        GIM_CheckType, /*MI*/2, /*Op*/2, /*Type*/GILLT_s32,
        GIM_RecordInsn, /*DefineMI*/3, /*MI*/2, /*OpIdx*/1, // MIs[3]
        GIM_CheckOpcode, /*MI*/3, GIMT_Encode2(TargetOpcode::G_FMAXNUM),
        // MIs[3] VOP3Mods:src1:src1_mods
        GIM_CheckIsSameOperand, /*MI*/3, /*OpIdx*/1, /*OtherMI*/1, /*OtherOpIdx*/2,
        // MIs[3] VOP3Mods:src0:src0_mods
        GIM_CheckIsSameOperand, /*MI*/3, /*OpIdx*/2, /*OtherMI*/1, /*OtherOpIdx*/1,
        GIM_CheckCxxInsnPredicate, /*MI*/0, /*FnId*/GIMT_Encode2(GICXXPred_MI_Predicate_fmaxnum_like_nnan),
        GIM_CheckIsSafeToFold, /*InsnID*/1,
        GIM_CheckIsSafeToFold, /*InsnID*/2,
        GIM_CheckIsSafeToFold, /*InsnID*/3,
        GIM_CheckComplexPattern, /*MI*/1, /*Op*/1, /*Renderer*/GIMT_Encode2(0), GIMT_Encode2(GICP_gi_vop3mods),
        GIM_CheckComplexPattern, /*MI*/1, /*Op*/2, /*Renderer*/GIMT_Encode2(1), GIMT_Encode2(GICP_gi_vop3mods),
        GIM_CheckComplexPattern, /*MI*/2, /*Op*/2, /*Renderer*/GIMT_Encode2(2), GIMT_Encode2(GICP_gi_vop3mods),
        // (fmaxnum_ieee:{ *:[f32] } (fminnum_ieee:{ *:[f32] } (VOP3Mods:{ *:[f32] } f32:{ *:[f32] }:$src0, i32:{ *:[i32] }:$src0_mods), (VOP3Mods:{ *:[f32] } f32:{ *:[f32] }:$src1, i32:{ *:[i32] }:$src1_mods)), (fminnum:{ *:[f32] } (fmaxnum:{ *:[f32] } (VOP3Mods:{ *:[f32] } f32:{ *:[f32] }:$src1, i32:{ *:[i32] }:$src1_mods), (VOP3Mods:{ *:[f32] } f32:{ *:[f32] }:$src0, i32:{ *:[i32] }:$src0_mods)), (VOP3Mods:{ *:[f32] } f32:{ *:[f32] }:$src2, i32:{ *:[i32] }:$src2_mods)))<<P:Predicate_fmaxnum_like_nnan>>  =>  (V_MED3_F32_e64:{ *:[f32] } ?:{ *:[i32] }:$src0_mods, ?:{ *:[f32] }:$src0, ?:{ *:[i32] }:$src1_mods, ?:{ *:[f32] }:$src1, ?:{ *:[i32] }:$src2_mods, ?:{ *:[f32] }:$src2, 0:{ *:[i1] }, 0:{ *:[i32] })
        GIR_BuildMI, /*InsnID*/0, /*Opcode*/GIMT_Encode2(AMDGPU::V_MED3_F32_e64),
        GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/0, // DstI[vdst]
        GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/1, // src0_mods
        GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/0, // src0
        GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(1), /*SubOperand*/1, // src1_mods
        GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(1), /*SubOperand*/0, // src1
        GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(2), /*SubOperand*/1, // src2_mods
        GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(2), /*SubOperand*/0, // src2
        GIR_AddImm8, /*InsnID*/0, /*Imm*/0,
        GIR_AddImm8, /*InsnID*/0, /*Imm*/0,
        GIR_ConstrainSelectedInstOperands, /*InsnID*/0,
        GIR_EraseFromParent, /*InsnID*/0,
        // GIR_Coverage, 10045,
        GIR_Done,
      // Label 5131: @376376
      GIM_Try, /*On fail goto*//*Label 5132*/ GIMT_Encode4(376516), // Rule ID 10048 //
        GIM_CheckRegBankForClass, /*MI*/0, /*Op*/0, /*RC*/GIMT_Encode2(AMDGPU::VGPR_32RegClassID),
        GIM_RecordInsn, /*DefineMI*/1, /*MI*/0, /*OpIdx*/1, // MIs[1]
        GIM_CheckOpcode, /*MI*/1, GIMT_Encode2(TargetOpcode::G_FMINNUM_IEEE),
        GIM_CheckType, /*MI*/1, /*Op*/1, /*Type*/GILLT_s32,
        GIM_CheckType, /*MI*/1, /*Op*/2, /*Type*/GILLT_s32,
        GIM_RecordInsn, /*DefineMI*/2, /*MI*/0, /*OpIdx*/2, // MIs[2]
        GIM_CheckOpcode, /*MI*/2, GIMT_Encode2(TargetOpcode::G_FMINNUM),
        GIM_CheckType, /*MI*/2, /*Op*/1, /*Type*/GILLT_s32,
        GIM_CheckType, /*MI*/2, /*Op*/2, /*Type*/GILLT_s32,
        GIM_RecordInsn, /*DefineMI*/3, /*MI*/2, /*OpIdx*/1, // MIs[3]
        GIM_CheckOpcode, /*MI*/3, GIMT_Encode2(TargetOpcode::G_FMAXNUM),
        // MIs[3] VOP3Mods:src0:src0_mods
        GIM_CheckIsSameOperand, /*MI*/3, /*OpIdx*/1, /*OtherMI*/1, /*OtherOpIdx*/2,
        // MIs[3] VOP3Mods:src1:src1_mods
        GIM_CheckIsSameOperand, /*MI*/3, /*OpIdx*/2, /*OtherMI*/1, /*OtherOpIdx*/1,
        GIM_CheckCxxInsnPredicate, /*MI*/0, /*FnId*/GIMT_Encode2(GICXXPred_MI_Predicate_fmaxnum_like_nnan),
        GIM_CheckIsSafeToFold, /*InsnID*/1,
        GIM_CheckIsSafeToFold, /*InsnID*/2,
        GIM_CheckIsSafeToFold, /*InsnID*/3,
        GIM_CheckComplexPattern, /*MI*/1, /*Op*/1, /*Renderer*/GIMT_Encode2(0), GIMT_Encode2(GICP_gi_vop3mods),
        GIM_CheckComplexPattern, /*MI*/1, /*Op*/2, /*Renderer*/GIMT_Encode2(1), GIMT_Encode2(GICP_gi_vop3mods),
        GIM_CheckComplexPattern, /*MI*/2, /*Op*/2, /*Renderer*/GIMT_Encode2(2), GIMT_Encode2(GICP_gi_vop3mods),
        // (fmaxnum_ieee:{ *:[f32] } (fminnum_ieee:{ *:[f32] } (VOP3Mods:{ *:[f32] } f32:{ *:[f32] }:$src1, i32:{ *:[i32] }:$src1_mods), (VOP3Mods:{ *:[f32] } f32:{ *:[f32] }:$src0, i32:{ *:[i32] }:$src0_mods)), (fminnum:{ *:[f32] } (fmaxnum:{ *:[f32] } (VOP3Mods:{ *:[f32] } f32:{ *:[f32] }:$src0, i32:{ *:[i32] }:$src0_mods), (VOP3Mods:{ *:[f32] } f32:{ *:[f32] }:$src1, i32:{ *:[i32] }:$src1_mods)), (VOP3Mods:{ *:[f32] } f32:{ *:[f32] }:$src2, i32:{ *:[i32] }:$src2_mods)))<<P:Predicate_fmaxnum_like_nnan>>  =>  (V_MED3_F32_e64:{ *:[f32] } ?:{ *:[i32] }:$src0_mods, ?:{ *:[f32] }:$src0, ?:{ *:[i32] }:$src1_mods, ?:{ *:[f32] }:$src1, ?:{ *:[i32] }:$src2_mods, ?:{ *:[f32] }:$src2, 0:{ *:[i1] }, 0:{ *:[i32] })
        GIR_BuildMI, /*InsnID*/0, /*Opcode*/GIMT_Encode2(AMDGPU::V_MED3_F32_e64),
        GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/0, // DstI[vdst]
        GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(1), /*SubOperand*/1, // src0_mods
        GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(1), /*SubOperand*/0, // src0
        GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/1, // src1_mods
        GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/0, // src1
        GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(2), /*SubOperand*/1, // src2_mods
        GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(2), /*SubOperand*/0, // src2
        GIR_AddImm8, /*InsnID*/0, /*Imm*/0,
        GIR_AddImm8, /*InsnID*/0, /*Imm*/0,
        GIR_ConstrainSelectedInstOperands, /*InsnID*/0,
        GIR_EraseFromParent, /*InsnID*/0,
        // GIR_Coverage, 10048,
        GIR_Done,
      // Label 5132: @376516
      GIM_Try, /*On fail goto*//*Label 5133*/ GIMT_Encode4(376656), // Rule ID 10049 //
        GIM_CheckRegBankForClass, /*MI*/0, /*Op*/0, /*RC*/GIMT_Encode2(AMDGPU::VGPR_32RegClassID),
        GIM_RecordInsn, /*DefineMI*/1, /*MI*/0, /*OpIdx*/1, // MIs[1]
        GIM_CheckOpcode, /*MI*/1, GIMT_Encode2(TargetOpcode::G_FMINNUM_IEEE),
        GIM_CheckType, /*MI*/1, /*Op*/1, /*Type*/GILLT_s32,
        GIM_CheckType, /*MI*/1, /*Op*/2, /*Type*/GILLT_s32,
        GIM_RecordInsn, /*DefineMI*/2, /*MI*/0, /*OpIdx*/2, // MIs[2]
        GIM_CheckOpcode, /*MI*/2, GIMT_Encode2(TargetOpcode::G_FMINNUM),
        GIM_CheckType, /*MI*/2, /*Op*/1, /*Type*/GILLT_s32,
        GIM_CheckType, /*MI*/2, /*Op*/2, /*Type*/GILLT_s32,
        GIM_RecordInsn, /*DefineMI*/3, /*MI*/2, /*OpIdx*/1, // MIs[3]
        GIM_CheckOpcode, /*MI*/3, GIMT_Encode2(TargetOpcode::G_FMAXNUM),
        // MIs[3] VOP3Mods:src1:src1_mods
        GIM_CheckIsSameOperand, /*MI*/3, /*OpIdx*/1, /*OtherMI*/1, /*OtherOpIdx*/1,
        // MIs[3] VOP3Mods:src0:src0_mods
        GIM_CheckIsSameOperand, /*MI*/3, /*OpIdx*/2, /*OtherMI*/1, /*OtherOpIdx*/2,
        GIM_CheckCxxInsnPredicate, /*MI*/0, /*FnId*/GIMT_Encode2(GICXXPred_MI_Predicate_fmaxnum_like_nnan),
        GIM_CheckIsSafeToFold, /*InsnID*/1,
        GIM_CheckIsSafeToFold, /*InsnID*/2,
        GIM_CheckIsSafeToFold, /*InsnID*/3,
        GIM_CheckComplexPattern, /*MI*/1, /*Op*/1, /*Renderer*/GIMT_Encode2(0), GIMT_Encode2(GICP_gi_vop3mods),
        GIM_CheckComplexPattern, /*MI*/1, /*Op*/2, /*Renderer*/GIMT_Encode2(1), GIMT_Encode2(GICP_gi_vop3mods),
        GIM_CheckComplexPattern, /*MI*/2, /*Op*/2, /*Renderer*/GIMT_Encode2(2), GIMT_Encode2(GICP_gi_vop3mods),
        // (fmaxnum_ieee:{ *:[f32] } (fminnum_ieee:{ *:[f32] } (VOP3Mods:{ *:[f32] } f32:{ *:[f32] }:$src1, i32:{ *:[i32] }:$src1_mods), (VOP3Mods:{ *:[f32] } f32:{ *:[f32] }:$src0, i32:{ *:[i32] }:$src0_mods)), (fminnum:{ *:[f32] } (fmaxnum:{ *:[f32] } (VOP3Mods:{ *:[f32] } f32:{ *:[f32] }:$src1, i32:{ *:[i32] }:$src1_mods), (VOP3Mods:{ *:[f32] } f32:{ *:[f32] }:$src0, i32:{ *:[i32] }:$src0_mods)), (VOP3Mods:{ *:[f32] } f32:{ *:[f32] }:$src2, i32:{ *:[i32] }:$src2_mods)))<<P:Predicate_fmaxnum_like_nnan>>  =>  (V_MED3_F32_e64:{ *:[f32] } ?:{ *:[i32] }:$src0_mods, ?:{ *:[f32] }:$src0, ?:{ *:[i32] }:$src1_mods, ?:{ *:[f32] }:$src1, ?:{ *:[i32] }:$src2_mods, ?:{ *:[f32] }:$src2, 0:{ *:[i1] }, 0:{ *:[i32] })
        GIR_BuildMI, /*InsnID*/0, /*Opcode*/GIMT_Encode2(AMDGPU::V_MED3_F32_e64),
        GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/0, // DstI[vdst]
        GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(1), /*SubOperand*/1, // src0_mods
        GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(1), /*SubOperand*/0, // src0
        GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/1, // src1_mods
        GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/0, // src1
        GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(2), /*SubOperand*/1, // src2_mods
        GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(2), /*SubOperand*/0, // src2
        GIR_AddImm8, /*InsnID*/0, /*Imm*/0,
        GIR_AddImm8, /*InsnID*/0, /*Imm*/0,
        GIR_ConstrainSelectedInstOperands, /*InsnID*/0,
        GIR_EraseFromParent, /*InsnID*/0,
        // GIR_Coverage, 10049,
        GIR_Done,
      // Label 5133: @376656
      GIM_Try, /*On fail goto*//*Label 5134*/ GIMT_Encode4(376796), // Rule ID 6484 //
        GIM_CheckRegBankForClass, /*MI*/0, /*Op*/0, /*RC*/GIMT_Encode2(AMDGPU::VGPR_32RegClassID),
        GIM_RecordInsn, /*DefineMI*/1, /*MI*/0, /*OpIdx*/1, // MIs[1]
        GIM_CheckOpcode, /*MI*/1, GIMT_Encode2(TargetOpcode::G_FMINNUM_IEEE),
        GIM_CheckType, /*MI*/1, /*Op*/1, /*Type*/GILLT_s32,
        GIM_CheckType, /*MI*/1, /*Op*/2, /*Type*/GILLT_s32,
        GIM_RecordInsn, /*DefineMI*/2, /*MI*/0, /*OpIdx*/2, // MIs[2]
        GIM_CheckOpcode, /*MI*/2, GIMT_Encode2(TargetOpcode::G_FMINNUM),
        GIM_CheckType, /*MI*/2, /*Op*/1, /*Type*/GILLT_s32,
        GIM_CheckType, /*MI*/2, /*Op*/2, /*Type*/GILLT_s32,
        GIM_RecordInsn, /*DefineMI*/3, /*MI*/2, /*OpIdx*/1, // MIs[3]
        GIM_CheckOpcode, /*MI*/3, GIMT_Encode2(TargetOpcode::G_FMAXNUM_IEEE),
        // MIs[3] VOP3Mods:src0:src0_mods
        GIM_CheckIsSameOperand, /*MI*/3, /*OpIdx*/1, /*OtherMI*/1, /*OtherOpIdx*/1,
        // MIs[3] VOP3Mods:src1:src1_mods
        GIM_CheckIsSameOperand, /*MI*/3, /*OpIdx*/2, /*OtherMI*/1, /*OtherOpIdx*/2,
        GIM_CheckCxxInsnPredicate, /*MI*/0, /*FnId*/GIMT_Encode2(GICXXPred_MI_Predicate_fmaxnum_like_nnan),
        GIM_CheckIsSafeToFold, /*InsnID*/1,
        GIM_CheckIsSafeToFold, /*InsnID*/2,
        GIM_CheckIsSafeToFold, /*InsnID*/3,
        GIM_CheckComplexPattern, /*MI*/1, /*Op*/1, /*Renderer*/GIMT_Encode2(0), GIMT_Encode2(GICP_gi_vop3mods),
        GIM_CheckComplexPattern, /*MI*/1, /*Op*/2, /*Renderer*/GIMT_Encode2(1), GIMT_Encode2(GICP_gi_vop3mods),
        GIM_CheckComplexPattern, /*MI*/2, /*Op*/2, /*Renderer*/GIMT_Encode2(2), GIMT_Encode2(GICP_gi_vop3mods),
        // (fmaxnum_ieee:{ *:[f32] } (fminnum_ieee:{ *:[f32] } (VOP3Mods:{ *:[f32] } f32:{ *:[f32] }:$src0, i32:{ *:[i32] }:$src0_mods), (VOP3Mods:{ *:[f32] } f32:{ *:[f32] }:$src1, i32:{ *:[i32] }:$src1_mods)), (fminnum:{ *:[f32] } (fmaxnum_ieee:{ *:[f32] } (VOP3Mods:{ *:[f32] } f32:{ *:[f32] }:$src0, i32:{ *:[i32] }:$src0_mods), (VOP3Mods:{ *:[f32] } f32:{ *:[f32] }:$src1, i32:{ *:[i32] }:$src1_mods)), (VOP3Mods:{ *:[f32] } f32:{ *:[f32] }:$src2, i32:{ *:[i32] }:$src2_mods)))<<P:Predicate_fmaxnum_like_nnan>>  =>  (V_MED3_F32_e64:{ *:[f32] } ?:{ *:[i32] }:$src0_mods, ?:{ *:[f32] }:$src0, ?:{ *:[i32] }:$src1_mods, ?:{ *:[f32] }:$src1, ?:{ *:[i32] }:$src2_mods, ?:{ *:[f32] }:$src2, 0:{ *:[i1] }, 0:{ *:[i32] })
        GIR_BuildMI, /*InsnID*/0, /*Opcode*/GIMT_Encode2(AMDGPU::V_MED3_F32_e64),
        GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/0, // DstI[vdst]
        GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/1, // src0_mods
        GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/0, // src0
        GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(1), /*SubOperand*/1, // src1_mods
        GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(1), /*SubOperand*/0, // src1
        GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(2), /*SubOperand*/1, // src2_mods
        GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(2), /*SubOperand*/0, // src2
        GIR_AddImm8, /*InsnID*/0, /*Imm*/0,
        GIR_AddImm8, /*InsnID*/0, /*Imm*/0,
        GIR_ConstrainSelectedInstOperands, /*InsnID*/0,
        GIR_EraseFromParent, /*InsnID*/0,
        // GIR_Coverage, 6484,
        GIR_Done,
      // Label 5134: @376796
      GIM_Try, /*On fail goto*//*Label 5135*/ GIMT_Encode4(376936), // Rule ID 10030 //
        GIM_CheckRegBankForClass, /*MI*/0, /*Op*/0, /*RC*/GIMT_Encode2(AMDGPU::VGPR_32RegClassID),
        GIM_RecordInsn, /*DefineMI*/1, /*MI*/0, /*OpIdx*/1, // MIs[1]
        GIM_CheckOpcode, /*MI*/1, GIMT_Encode2(TargetOpcode::G_FMINNUM_IEEE),
        GIM_CheckType, /*MI*/1, /*Op*/1, /*Type*/GILLT_s32,
        GIM_CheckType, /*MI*/1, /*Op*/2, /*Type*/GILLT_s32,
        GIM_RecordInsn, /*DefineMI*/2, /*MI*/0, /*OpIdx*/2, // MIs[2]
        GIM_CheckOpcode, /*MI*/2, GIMT_Encode2(TargetOpcode::G_FMINNUM),
        GIM_CheckType, /*MI*/2, /*Op*/1, /*Type*/GILLT_s32,
        GIM_CheckType, /*MI*/2, /*Op*/2, /*Type*/GILLT_s32,
        GIM_RecordInsn, /*DefineMI*/3, /*MI*/2, /*OpIdx*/1, // MIs[3]
        GIM_CheckOpcode, /*MI*/3, GIMT_Encode2(TargetOpcode::G_FMAXNUM_IEEE),
        // MIs[3] VOP3Mods:src1:src1_mods
        GIM_CheckIsSameOperand, /*MI*/3, /*OpIdx*/1, /*OtherMI*/1, /*OtherOpIdx*/2,
        // MIs[3] VOP3Mods:src0:src0_mods
        GIM_CheckIsSameOperand, /*MI*/3, /*OpIdx*/2, /*OtherMI*/1, /*OtherOpIdx*/1,
        GIM_CheckCxxInsnPredicate, /*MI*/0, /*FnId*/GIMT_Encode2(GICXXPred_MI_Predicate_fmaxnum_like_nnan),
        GIM_CheckIsSafeToFold, /*InsnID*/1,
        GIM_CheckIsSafeToFold, /*InsnID*/2,
        GIM_CheckIsSafeToFold, /*InsnID*/3,
        GIM_CheckComplexPattern, /*MI*/1, /*Op*/1, /*Renderer*/GIMT_Encode2(0), GIMT_Encode2(GICP_gi_vop3mods),
        GIM_CheckComplexPattern, /*MI*/1, /*Op*/2, /*Renderer*/GIMT_Encode2(1), GIMT_Encode2(GICP_gi_vop3mods),
        GIM_CheckComplexPattern, /*MI*/2, /*Op*/2, /*Renderer*/GIMT_Encode2(2), GIMT_Encode2(GICP_gi_vop3mods),
        // (fmaxnum_ieee:{ *:[f32] } (fminnum_ieee:{ *:[f32] } (VOP3Mods:{ *:[f32] } f32:{ *:[f32] }:$src0, i32:{ *:[i32] }:$src0_mods), (VOP3Mods:{ *:[f32] } f32:{ *:[f32] }:$src1, i32:{ *:[i32] }:$src1_mods)), (fminnum:{ *:[f32] } (fmaxnum_ieee:{ *:[f32] } (VOP3Mods:{ *:[f32] } f32:{ *:[f32] }:$src1, i32:{ *:[i32] }:$src1_mods), (VOP3Mods:{ *:[f32] } f32:{ *:[f32] }:$src0, i32:{ *:[i32] }:$src0_mods)), (VOP3Mods:{ *:[f32] } f32:{ *:[f32] }:$src2, i32:{ *:[i32] }:$src2_mods)))<<P:Predicate_fmaxnum_like_nnan>>  =>  (V_MED3_F32_e64:{ *:[f32] } ?:{ *:[i32] }:$src0_mods, ?:{ *:[f32] }:$src0, ?:{ *:[i32] }:$src1_mods, ?:{ *:[f32] }:$src1, ?:{ *:[i32] }:$src2_mods, ?:{ *:[f32] }:$src2, 0:{ *:[i1] }, 0:{ *:[i32] })
        GIR_BuildMI, /*InsnID*/0, /*Opcode*/GIMT_Encode2(AMDGPU::V_MED3_F32_e64),
        GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/0, // DstI[vdst]
        GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/1, // src0_mods
        GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/0, // src0
        GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(1), /*SubOperand*/1, // src1_mods
        GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(1), /*SubOperand*/0, // src1
        GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(2), /*SubOperand*/1, // src2_mods
        GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(2), /*SubOperand*/0, // src2
        GIR_AddImm8, /*InsnID*/0, /*Imm*/0,
        GIR_AddImm8, /*InsnID*/0, /*Imm*/0,
        GIR_ConstrainSelectedInstOperands, /*InsnID*/0,
        GIR_EraseFromParent, /*InsnID*/0,
        // GIR_Coverage, 10030,
        GIR_Done,
      // Label 5135: @376936
      GIM_Try, /*On fail goto*//*Label 5136*/ GIMT_Encode4(377076), // Rule ID 10033 //
        GIM_CheckRegBankForClass, /*MI*/0, /*Op*/0, /*RC*/GIMT_Encode2(AMDGPU::VGPR_32RegClassID),
        GIM_RecordInsn, /*DefineMI*/1, /*MI*/0, /*OpIdx*/1, // MIs[1]
        GIM_CheckOpcode, /*MI*/1, GIMT_Encode2(TargetOpcode::G_FMINNUM_IEEE),
        GIM_CheckType, /*MI*/1, /*Op*/1, /*Type*/GILLT_s32,
        GIM_CheckType, /*MI*/1, /*Op*/2, /*Type*/GILLT_s32,
        GIM_RecordInsn, /*DefineMI*/2, /*MI*/0, /*OpIdx*/2, // MIs[2]
        GIM_CheckOpcode, /*MI*/2, GIMT_Encode2(TargetOpcode::G_FMINNUM),
        GIM_CheckType, /*MI*/2, /*Op*/1, /*Type*/GILLT_s32,
        GIM_CheckType, /*MI*/2, /*Op*/2, /*Type*/GILLT_s32,
        GIM_RecordInsn, /*DefineMI*/3, /*MI*/2, /*OpIdx*/1, // MIs[3]
        GIM_CheckOpcode, /*MI*/3, GIMT_Encode2(TargetOpcode::G_FMAXNUM_IEEE),
        // MIs[3] VOP3Mods:src0:src0_mods
        GIM_CheckIsSameOperand, /*MI*/3, /*OpIdx*/1, /*OtherMI*/1, /*OtherOpIdx*/2,
        // MIs[3] VOP3Mods:src1:src1_mods
        GIM_CheckIsSameOperand, /*MI*/3, /*OpIdx*/2, /*OtherMI*/1, /*OtherOpIdx*/1,
        GIM_CheckCxxInsnPredicate, /*MI*/0, /*FnId*/GIMT_Encode2(GICXXPred_MI_Predicate_fmaxnum_like_nnan),
        GIM_CheckIsSafeToFold, /*InsnID*/1,
        GIM_CheckIsSafeToFold, /*InsnID*/2,
        GIM_CheckIsSafeToFold, /*InsnID*/3,
        GIM_CheckComplexPattern, /*MI*/1, /*Op*/1, /*Renderer*/GIMT_Encode2(0), GIMT_Encode2(GICP_gi_vop3mods),
        GIM_CheckComplexPattern, /*MI*/1, /*Op*/2, /*Renderer*/GIMT_Encode2(1), GIMT_Encode2(GICP_gi_vop3mods),
        GIM_CheckComplexPattern, /*MI*/2, /*Op*/2, /*Renderer*/GIMT_Encode2(2), GIMT_Encode2(GICP_gi_vop3mods),
        // (fmaxnum_ieee:{ *:[f32] } (fminnum_ieee:{ *:[f32] } (VOP3Mods:{ *:[f32] } f32:{ *:[f32] }:$src1, i32:{ *:[i32] }:$src1_mods), (VOP3Mods:{ *:[f32] } f32:{ *:[f32] }:$src0, i32:{ *:[i32] }:$src0_mods)), (fminnum:{ *:[f32] } (fmaxnum_ieee:{ *:[f32] } (VOP3Mods:{ *:[f32] } f32:{ *:[f32] }:$src0, i32:{ *:[i32] }:$src0_mods), (VOP3Mods:{ *:[f32] } f32:{ *:[f32] }:$src1, i32:{ *:[i32] }:$src1_mods)), (VOP3Mods:{ *:[f32] } f32:{ *:[f32] }:$src2, i32:{ *:[i32] }:$src2_mods)))<<P:Predicate_fmaxnum_like_nnan>>  =>  (V_MED3_F32_e64:{ *:[f32] } ?:{ *:[i32] }:$src0_mods, ?:{ *:[f32] }:$src0, ?:{ *:[i32] }:$src1_mods, ?:{ *:[f32] }:$src1, ?:{ *:[i32] }:$src2_mods, ?:{ *:[f32] }:$src2, 0:{ *:[i1] }, 0:{ *:[i32] })
        GIR_BuildMI, /*InsnID*/0, /*Opcode*/GIMT_Encode2(AMDGPU::V_MED3_F32_e64),
        GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/0, // DstI[vdst]
        GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(1), /*SubOperand*/1, // src0_mods
        GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(1), /*SubOperand*/0, // src0
        GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/1, // src1_mods
        GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/0, // src1
        GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(2), /*SubOperand*/1, // src2_mods
        GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(2), /*SubOperand*/0, // src2
        GIR_AddImm8, /*InsnID*/0, /*Imm*/0,
        GIR_AddImm8, /*InsnID*/0, /*Imm*/0,
        GIR_ConstrainSelectedInstOperands, /*InsnID*/0,
        GIR_EraseFromParent, /*InsnID*/0,
        // GIR_Coverage, 10033,
        GIR_Done,
      // Label 5136: @377076
      GIM_Try, /*On fail goto*//*Label 5137*/ GIMT_Encode4(377216), // Rule ID 10034 //
        GIM_CheckRegBankForClass, /*MI*/0, /*Op*/0, /*RC*/GIMT_Encode2(AMDGPU::VGPR_32RegClassID),
        GIM_RecordInsn, /*DefineMI*/1, /*MI*/0, /*OpIdx*/1, // MIs[1]
        GIM_CheckOpcode, /*MI*/1, GIMT_Encode2(TargetOpcode::G_FMINNUM_IEEE),
        GIM_CheckType, /*MI*/1, /*Op*/1, /*Type*/GILLT_s32,
        GIM_CheckType, /*MI*/1, /*Op*/2, /*Type*/GILLT_s32,
        GIM_RecordInsn, /*DefineMI*/2, /*MI*/0, /*OpIdx*/2, // MIs[2]
        GIM_CheckOpcode, /*MI*/2, GIMT_Encode2(TargetOpcode::G_FMINNUM),
        GIM_CheckType, /*MI*/2, /*Op*/1, /*Type*/GILLT_s32,
        GIM_CheckType, /*MI*/2, /*Op*/2, /*Type*/GILLT_s32,
        GIM_RecordInsn, /*DefineMI*/3, /*MI*/2, /*OpIdx*/1, // MIs[3]
        GIM_CheckOpcode, /*MI*/3, GIMT_Encode2(TargetOpcode::G_FMAXNUM_IEEE),
        // MIs[3] VOP3Mods:src1:src1_mods
        GIM_CheckIsSameOperand, /*MI*/3, /*OpIdx*/1, /*OtherMI*/1, /*OtherOpIdx*/1,
        // MIs[3] VOP3Mods:src0:src0_mods
        GIM_CheckIsSameOperand, /*MI*/3, /*OpIdx*/2, /*OtherMI*/1, /*OtherOpIdx*/2,
        GIM_CheckCxxInsnPredicate, /*MI*/0, /*FnId*/GIMT_Encode2(GICXXPred_MI_Predicate_fmaxnum_like_nnan),
        GIM_CheckIsSafeToFold, /*InsnID*/1,
        GIM_CheckIsSafeToFold, /*InsnID*/2,
        GIM_CheckIsSafeToFold, /*InsnID*/3,
        GIM_CheckComplexPattern, /*MI*/1, /*Op*/1, /*Renderer*/GIMT_Encode2(0), GIMT_Encode2(GICP_gi_vop3mods),
        GIM_CheckComplexPattern, /*MI*/1, /*Op*/2, /*Renderer*/GIMT_Encode2(1), GIMT_Encode2(GICP_gi_vop3mods),
        GIM_CheckComplexPattern, /*MI*/2, /*Op*/2, /*Renderer*/GIMT_Encode2(2), GIMT_Encode2(GICP_gi_vop3mods),
        // (fmaxnum_ieee:{ *:[f32] } (fminnum_ieee:{ *:[f32] } (VOP3Mods:{ *:[f32] } f32:{ *:[f32] }:$src1, i32:{ *:[i32] }:$src1_mods), (VOP3Mods:{ *:[f32] } f32:{ *:[f32] }:$src0, i32:{ *:[i32] }:$src0_mods)), (fminnum:{ *:[f32] } (fmaxnum_ieee:{ *:[f32] } (VOP3Mods:{ *:[f32] } f32:{ *:[f32] }:$src1, i32:{ *:[i32] }:$src1_mods), (VOP3Mods:{ *:[f32] } f32:{ *:[f32] }:$src0, i32:{ *:[i32] }:$src0_mods)), (VOP3Mods:{ *:[f32] } f32:{ *:[f32] }:$src2, i32:{ *:[i32] }:$src2_mods)))<<P:Predicate_fmaxnum_like_nnan>>  =>  (V_MED3_F32_e64:{ *:[f32] } ?:{ *:[i32] }:$src0_mods, ?:{ *:[f32] }:$src0, ?:{ *:[i32] }:$src1_mods, ?:{ *:[f32] }:$src1, ?:{ *:[i32] }:$src2_mods, ?:{ *:[f32] }:$src2, 0:{ *:[i1] }, 0:{ *:[i32] })
        GIR_BuildMI, /*InsnID*/0, /*Opcode*/GIMT_Encode2(AMDGPU::V_MED3_F32_e64),
        GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/0, // DstI[vdst]
        GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(1), /*SubOperand*/1, // src0_mods
        GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(1), /*SubOperand*/0, // src0
        GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/1, // src1_mods
        GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/0, // src1
        GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(2), /*SubOperand*/1, // src2_mods
        GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(2), /*SubOperand*/0, // src2
        GIR_AddImm8, /*InsnID*/0, /*Imm*/0,
        GIR_AddImm8, /*InsnID*/0, /*Imm*/0,
        GIR_ConstrainSelectedInstOperands, /*InsnID*/0,
        GIR_EraseFromParent, /*InsnID*/0,
        // GIR_Coverage, 10034,
        GIR_Done,
      // Label 5137: @377216
      GIM_Try, /*On fail goto*//*Label 5138*/ GIMT_Encode4(377356), // Rule ID 10016 //
        GIM_CheckRegBankForClass, /*MI*/0, /*Op*/0, /*RC*/GIMT_Encode2(AMDGPU::VGPR_32RegClassID),
        GIM_RecordInsn, /*DefineMI*/1, /*MI*/0, /*OpIdx*/1, // MIs[1]
        GIM_CheckOpcode, /*MI*/1, GIMT_Encode2(TargetOpcode::G_FMINNUM_IEEE),
        GIM_CheckType, /*MI*/1, /*Op*/1, /*Type*/GILLT_s32,
        GIM_CheckType, /*MI*/1, /*Op*/2, /*Type*/GILLT_s32,
        GIM_RecordInsn, /*DefineMI*/2, /*MI*/0, /*OpIdx*/2, // MIs[2]
        GIM_CheckOpcode, /*MI*/2, GIMT_Encode2(TargetOpcode::G_FMINNUM_IEEE),
        GIM_CheckType, /*MI*/2, /*Op*/1, /*Type*/GILLT_s32,
        GIM_CheckType, /*MI*/2, /*Op*/2, /*Type*/GILLT_s32,
        GIM_RecordInsn, /*DefineMI*/3, /*MI*/2, /*OpIdx*/2, // MIs[3]
        GIM_CheckOpcode, /*MI*/3, GIMT_Encode2(TargetOpcode::G_FMAXNUM),
        // MIs[3] VOP3Mods:src0:src0_mods
        GIM_CheckIsSameOperand, /*MI*/3, /*OpIdx*/1, /*OtherMI*/1, /*OtherOpIdx*/1,
        // MIs[3] VOP3Mods:src1:src1_mods
        GIM_CheckIsSameOperand, /*MI*/3, /*OpIdx*/2, /*OtherMI*/1, /*OtherOpIdx*/2,
        GIM_CheckCxxInsnPredicate, /*MI*/0, /*FnId*/GIMT_Encode2(GICXXPred_MI_Predicate_fmaxnum_like_nnan),
        GIM_CheckIsSafeToFold, /*InsnID*/1,
        GIM_CheckIsSafeToFold, /*InsnID*/2,
        GIM_CheckIsSafeToFold, /*InsnID*/3,
        GIM_CheckComplexPattern, /*MI*/1, /*Op*/1, /*Renderer*/GIMT_Encode2(0), GIMT_Encode2(GICP_gi_vop3mods),
        GIM_CheckComplexPattern, /*MI*/1, /*Op*/2, /*Renderer*/GIMT_Encode2(1), GIMT_Encode2(GICP_gi_vop3mods),
        GIM_CheckComplexPattern, /*MI*/2, /*Op*/1, /*Renderer*/GIMT_Encode2(2), GIMT_Encode2(GICP_gi_vop3mods),
        // (fmaxnum_ieee:{ *:[f32] } (fminnum_ieee:{ *:[f32] } (VOP3Mods:{ *:[f32] } f32:{ *:[f32] }:$src0, i32:{ *:[i32] }:$src0_mods), (VOP3Mods:{ *:[f32] } f32:{ *:[f32] }:$src1, i32:{ *:[i32] }:$src1_mods)), (fminnum_ieee:{ *:[f32] } (VOP3Mods:{ *:[f32] } f32:{ *:[f32] }:$src2, i32:{ *:[i32] }:$src2_mods), (fmaxnum:{ *:[f32] } (VOP3Mods:{ *:[f32] } f32:{ *:[f32] }:$src0, i32:{ *:[i32] }:$src0_mods), (VOP3Mods:{ *:[f32] } f32:{ *:[f32] }:$src1, i32:{ *:[i32] }:$src1_mods))))<<P:Predicate_fmaxnum_like_nnan>>  =>  (V_MED3_F32_e64:{ *:[f32] } ?:{ *:[i32] }:$src0_mods, ?:{ *:[f32] }:$src0, ?:{ *:[i32] }:$src1_mods, ?:{ *:[f32] }:$src1, ?:{ *:[i32] }:$src2_mods, ?:{ *:[f32] }:$src2, 0:{ *:[i1] }, 0:{ *:[i32] })
        GIR_BuildMI, /*InsnID*/0, /*Opcode*/GIMT_Encode2(AMDGPU::V_MED3_F32_e64),
        GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/0, // DstI[vdst]
        GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/1, // src0_mods
        GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/0, // src0
        GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(1), /*SubOperand*/1, // src1_mods
        GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(1), /*SubOperand*/0, // src1
        GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(2), /*SubOperand*/1, // src2_mods
        GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(2), /*SubOperand*/0, // src2
        GIR_AddImm8, /*InsnID*/0, /*Imm*/0,
        GIR_AddImm8, /*InsnID*/0, /*Imm*/0,
        GIR_ConstrainSelectedInstOperands, /*InsnID*/0,
        GIR_EraseFromParent, /*InsnID*/0,
        // GIR_Coverage, 10016,
        GIR_Done,
      // Label 5138: @377356
      GIM_Try, /*On fail goto*//*Label 5139*/ GIMT_Encode4(377496), // Rule ID 10017 //
        GIM_CheckRegBankForClass, /*MI*/0, /*Op*/0, /*RC*/GIMT_Encode2(AMDGPU::VGPR_32RegClassID),
        GIM_RecordInsn, /*DefineMI*/1, /*MI*/0, /*OpIdx*/1, // MIs[1]
        GIM_CheckOpcode, /*MI*/1, GIMT_Encode2(TargetOpcode::G_FMINNUM_IEEE),
        GIM_CheckType, /*MI*/1, /*Op*/1, /*Type*/GILLT_s32,
        GIM_CheckType, /*MI*/1, /*Op*/2, /*Type*/GILLT_s32,
        GIM_RecordInsn, /*DefineMI*/2, /*MI*/0, /*OpIdx*/2, // MIs[2]
        GIM_CheckOpcode, /*MI*/2, GIMT_Encode2(TargetOpcode::G_FMINNUM_IEEE),
        GIM_CheckType, /*MI*/2, /*Op*/1, /*Type*/GILLT_s32,
        GIM_CheckType, /*MI*/2, /*Op*/2, /*Type*/GILLT_s32,
        GIM_RecordInsn, /*DefineMI*/3, /*MI*/2, /*OpIdx*/2, // MIs[3]
        GIM_CheckOpcode, /*MI*/3, GIMT_Encode2(TargetOpcode::G_FMAXNUM),
        // MIs[3] VOP3Mods:src1:src1_mods
        GIM_CheckIsSameOperand, /*MI*/3, /*OpIdx*/1, /*OtherMI*/1, /*OtherOpIdx*/2,
        // MIs[3] VOP3Mods:src0:src0_mods
        GIM_CheckIsSameOperand, /*MI*/3, /*OpIdx*/2, /*OtherMI*/1, /*OtherOpIdx*/1,
        GIM_CheckCxxInsnPredicate, /*MI*/0, /*FnId*/GIMT_Encode2(GICXXPred_MI_Predicate_fmaxnum_like_nnan),
        GIM_CheckIsSafeToFold, /*InsnID*/1,
        GIM_CheckIsSafeToFold, /*InsnID*/2,
        GIM_CheckIsSafeToFold, /*InsnID*/3,
        GIM_CheckComplexPattern, /*MI*/1, /*Op*/1, /*Renderer*/GIMT_Encode2(0), GIMT_Encode2(GICP_gi_vop3mods),
        GIM_CheckComplexPattern, /*MI*/1, /*Op*/2, /*Renderer*/GIMT_Encode2(1), GIMT_Encode2(GICP_gi_vop3mods),
        GIM_CheckComplexPattern, /*MI*/2, /*Op*/1, /*Renderer*/GIMT_Encode2(2), GIMT_Encode2(GICP_gi_vop3mods),
        // (fmaxnum_ieee:{ *:[f32] } (fminnum_ieee:{ *:[f32] } (VOP3Mods:{ *:[f32] } f32:{ *:[f32] }:$src0, i32:{ *:[i32] }:$src0_mods), (VOP3Mods:{ *:[f32] } f32:{ *:[f32] }:$src1, i32:{ *:[i32] }:$src1_mods)), (fminnum_ieee:{ *:[f32] } (VOP3Mods:{ *:[f32] } f32:{ *:[f32] }:$src2, i32:{ *:[i32] }:$src2_mods), (fmaxnum:{ *:[f32] } (VOP3Mods:{ *:[f32] } f32:{ *:[f32] }:$src1, i32:{ *:[i32] }:$src1_mods), (VOP3Mods:{ *:[f32] } f32:{ *:[f32] }:$src0, i32:{ *:[i32] }:$src0_mods))))<<P:Predicate_fmaxnum_like_nnan>>  =>  (V_MED3_F32_e64:{ *:[f32] } ?:{ *:[i32] }:$src0_mods, ?:{ *:[f32] }:$src0, ?:{ *:[i32] }:$src1_mods, ?:{ *:[f32] }:$src1, ?:{ *:[i32] }:$src2_mods, ?:{ *:[f32] }:$src2, 0:{ *:[i1] }, 0:{ *:[i32] })
        GIR_BuildMI, /*InsnID*/0, /*Opcode*/GIMT_Encode2(AMDGPU::V_MED3_F32_e64),
        GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/0, // DstI[vdst]
        GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/1, // src0_mods
        GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/0, // src0
        GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(1), /*SubOperand*/1, // src1_mods
        GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(1), /*SubOperand*/0, // src1
        GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(2), /*SubOperand*/1, // src2_mods
        GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(2), /*SubOperand*/0, // src2
        GIR_AddImm8, /*InsnID*/0, /*Imm*/0,
        GIR_AddImm8, /*InsnID*/0, /*Imm*/0,
        GIR_ConstrainSelectedInstOperands, /*InsnID*/0,
        GIR_EraseFromParent, /*InsnID*/0,
        // GIR_Coverage, 10017,
        GIR_Done,
      // Label 5139: @377496
      GIM_Try, /*On fail goto*//*Label 5140*/ GIMT_Encode4(377636), // Rule ID 10020 //
        GIM_CheckRegBankForClass, /*MI*/0, /*Op*/0, /*RC*/GIMT_Encode2(AMDGPU::VGPR_32RegClassID),
        GIM_RecordInsn, /*DefineMI*/1, /*MI*/0, /*OpIdx*/1, // MIs[1]
        GIM_CheckOpcode, /*MI*/1, GIMT_Encode2(TargetOpcode::G_FMINNUM_IEEE),
        GIM_CheckType, /*MI*/1, /*Op*/1, /*Type*/GILLT_s32,
        GIM_CheckType, /*MI*/1, /*Op*/2, /*Type*/GILLT_s32,
        GIM_RecordInsn, /*DefineMI*/2, /*MI*/0, /*OpIdx*/2, // MIs[2]
        GIM_CheckOpcode, /*MI*/2, GIMT_Encode2(TargetOpcode::G_FMINNUM_IEEE),
        GIM_CheckType, /*MI*/2, /*Op*/1, /*Type*/GILLT_s32,
        GIM_CheckType, /*MI*/2, /*Op*/2, /*Type*/GILLT_s32,
        GIM_RecordInsn, /*DefineMI*/3, /*MI*/2, /*OpIdx*/2, // MIs[3]
        GIM_CheckOpcode, /*MI*/3, GIMT_Encode2(TargetOpcode::G_FMAXNUM),
        // MIs[3] VOP3Mods:src0:src0_mods
        GIM_CheckIsSameOperand, /*MI*/3, /*OpIdx*/1, /*OtherMI*/1, /*OtherOpIdx*/2,
        // MIs[3] VOP3Mods:src1:src1_mods
        GIM_CheckIsSameOperand, /*MI*/3, /*OpIdx*/2, /*OtherMI*/1, /*OtherOpIdx*/1,
        GIM_CheckCxxInsnPredicate, /*MI*/0, /*FnId*/GIMT_Encode2(GICXXPred_MI_Predicate_fmaxnum_like_nnan),
        GIM_CheckIsSafeToFold, /*InsnID*/1,
        GIM_CheckIsSafeToFold, /*InsnID*/2,
        GIM_CheckIsSafeToFold, /*InsnID*/3,
        GIM_CheckComplexPattern, /*MI*/1, /*Op*/1, /*Renderer*/GIMT_Encode2(0), GIMT_Encode2(GICP_gi_vop3mods),
        GIM_CheckComplexPattern, /*MI*/1, /*Op*/2, /*Renderer*/GIMT_Encode2(1), GIMT_Encode2(GICP_gi_vop3mods),
        GIM_CheckComplexPattern, /*MI*/2, /*Op*/1, /*Renderer*/GIMT_Encode2(2), GIMT_Encode2(GICP_gi_vop3mods),
        // (fmaxnum_ieee:{ *:[f32] } (fminnum_ieee:{ *:[f32] } (VOP3Mods:{ *:[f32] } f32:{ *:[f32] }:$src1, i32:{ *:[i32] }:$src1_mods), (VOP3Mods:{ *:[f32] } f32:{ *:[f32] }:$src0, i32:{ *:[i32] }:$src0_mods)), (fminnum_ieee:{ *:[f32] } (VOP3Mods:{ *:[f32] } f32:{ *:[f32] }:$src2, i32:{ *:[i32] }:$src2_mods), (fmaxnum:{ *:[f32] } (VOP3Mods:{ *:[f32] } f32:{ *:[f32] }:$src0, i32:{ *:[i32] }:$src0_mods), (VOP3Mods:{ *:[f32] } f32:{ *:[f32] }:$src1, i32:{ *:[i32] }:$src1_mods))))<<P:Predicate_fmaxnum_like_nnan>>  =>  (V_MED3_F32_e64:{ *:[f32] } ?:{ *:[i32] }:$src0_mods, ?:{ *:[f32] }:$src0, ?:{ *:[i32] }:$src1_mods, ?:{ *:[f32] }:$src1, ?:{ *:[i32] }:$src2_mods, ?:{ *:[f32] }:$src2, 0:{ *:[i1] }, 0:{ *:[i32] })
        GIR_BuildMI, /*InsnID*/0, /*Opcode*/GIMT_Encode2(AMDGPU::V_MED3_F32_e64),
        GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/0, // DstI[vdst]
        GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(1), /*SubOperand*/1, // src0_mods
        GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(1), /*SubOperand*/0, // src0
        GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/1, // src1_mods
        GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/0, // src1
        GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(2), /*SubOperand*/1, // src2_mods
        GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(2), /*SubOperand*/0, // src2
        GIR_AddImm8, /*InsnID*/0, /*Imm*/0,
        GIR_AddImm8, /*InsnID*/0, /*Imm*/0,
        GIR_ConstrainSelectedInstOperands, /*InsnID*/0,
        GIR_EraseFromParent, /*InsnID*/0,
        // GIR_Coverage, 10020,
        GIR_Done,
      // Label 5140: @377636
      GIM_Try, /*On fail goto*//*Label 5141*/ GIMT_Encode4(377776), // Rule ID 10021 //
        GIM_CheckRegBankForClass, /*MI*/0, /*Op*/0, /*RC*/GIMT_Encode2(AMDGPU::VGPR_32RegClassID),
        GIM_RecordInsn, /*DefineMI*/1, /*MI*/0, /*OpIdx*/1, // MIs[1]
        GIM_CheckOpcode, /*MI*/1, GIMT_Encode2(TargetOpcode::G_FMINNUM_IEEE),
        GIM_CheckType, /*MI*/1, /*Op*/1, /*Type*/GILLT_s32,
        GIM_CheckType, /*MI*/1, /*Op*/2, /*Type*/GILLT_s32,
        GIM_RecordInsn, /*DefineMI*/2, /*MI*/0, /*OpIdx*/2, // MIs[2]
        GIM_CheckOpcode, /*MI*/2, GIMT_Encode2(TargetOpcode::G_FMINNUM_IEEE),
        GIM_CheckType, /*MI*/2, /*Op*/1, /*Type*/GILLT_s32,
        GIM_CheckType, /*MI*/2, /*Op*/2, /*Type*/GILLT_s32,
        GIM_RecordInsn, /*DefineMI*/3, /*MI*/2, /*OpIdx*/2, // MIs[3]
        GIM_CheckOpcode, /*MI*/3, GIMT_Encode2(TargetOpcode::G_FMAXNUM),
        // MIs[3] VOP3Mods:src1:src1_mods
        GIM_CheckIsSameOperand, /*MI*/3, /*OpIdx*/1, /*OtherMI*/1, /*OtherOpIdx*/1,
        // MIs[3] VOP3Mods:src0:src0_mods
        GIM_CheckIsSameOperand, /*MI*/3, /*OpIdx*/2, /*OtherMI*/1, /*OtherOpIdx*/2,
        GIM_CheckCxxInsnPredicate, /*MI*/0, /*FnId*/GIMT_Encode2(GICXXPred_MI_Predicate_fmaxnum_like_nnan),
        GIM_CheckIsSafeToFold, /*InsnID*/1,
        GIM_CheckIsSafeToFold, /*InsnID*/2,
        GIM_CheckIsSafeToFold, /*InsnID*/3,
        GIM_CheckComplexPattern, /*MI*/1, /*Op*/1, /*Renderer*/GIMT_Encode2(0), GIMT_Encode2(GICP_gi_vop3mods),
        GIM_CheckComplexPattern, /*MI*/1, /*Op*/2, /*Renderer*/GIMT_Encode2(1), GIMT_Encode2(GICP_gi_vop3mods),
        GIM_CheckComplexPattern, /*MI*/2, /*Op*/1, /*Renderer*/GIMT_Encode2(2), GIMT_Encode2(GICP_gi_vop3mods),
        // (fmaxnum_ieee:{ *:[f32] } (fminnum_ieee:{ *:[f32] } (VOP3Mods:{ *:[f32] } f32:{ *:[f32] }:$src1, i32:{ *:[i32] }:$src1_mods), (VOP3Mods:{ *:[f32] } f32:{ *:[f32] }:$src0, i32:{ *:[i32] }:$src0_mods)), (fminnum_ieee:{ *:[f32] } (VOP3Mods:{ *:[f32] } f32:{ *:[f32] }:$src2, i32:{ *:[i32] }:$src2_mods), (fmaxnum:{ *:[f32] } (VOP3Mods:{ *:[f32] } f32:{ *:[f32] }:$src1, i32:{ *:[i32] }:$src1_mods), (VOP3Mods:{ *:[f32] } f32:{ *:[f32] }:$src0, i32:{ *:[i32] }:$src0_mods))))<<P:Predicate_fmaxnum_like_nnan>>  =>  (V_MED3_F32_e64:{ *:[f32] } ?:{ *:[i32] }:$src0_mods, ?:{ *:[f32] }:$src0, ?:{ *:[i32] }:$src1_mods, ?:{ *:[f32] }:$src1, ?:{ *:[i32] }:$src2_mods, ?:{ *:[f32] }:$src2, 0:{ *:[i1] }, 0:{ *:[i32] })
        GIR_BuildMI, /*InsnID*/0, /*Opcode*/GIMT_Encode2(AMDGPU::V_MED3_F32_e64),
        GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/0, // DstI[vdst]
        GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(1), /*SubOperand*/1, // src0_mods
        GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(1), /*SubOperand*/0, // src0
        GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/1, // src1_mods
        GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/0, // src1
        GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(2), /*SubOperand*/1, // src2_mods
        GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(2), /*SubOperand*/0, // src2
        GIR_AddImm8, /*InsnID*/0, /*Imm*/0,
        GIR_AddImm8, /*InsnID*/0, /*Imm*/0,
        GIR_ConstrainSelectedInstOperands, /*InsnID*/0,
        GIR_EraseFromParent, /*InsnID*/0,
        // GIR_Coverage, 10021,
        GIR_Done,
      // Label 5141: @377776
      GIM_Try, /*On fail goto*//*Label 5142*/ GIMT_Encode4(377916), // Rule ID 10001 //
        GIM_CheckRegBankForClass, /*MI*/0, /*Op*/0, /*RC*/GIMT_Encode2(AMDGPU::VGPR_32RegClassID),
        GIM_RecordInsn, /*DefineMI*/1, /*MI*/0, /*OpIdx*/1, // MIs[1]
        GIM_CheckOpcode, /*MI*/1, GIMT_Encode2(TargetOpcode::G_FMINNUM_IEEE),
        GIM_CheckType, /*MI*/1, /*Op*/1, /*Type*/GILLT_s32,
        GIM_CheckType, /*MI*/1, /*Op*/2, /*Type*/GILLT_s32,
        GIM_RecordInsn, /*DefineMI*/2, /*MI*/0, /*OpIdx*/2, // MIs[2]
        GIM_CheckOpcode, /*MI*/2, GIMT_Encode2(TargetOpcode::G_FMINNUM_IEEE),
        GIM_CheckType, /*MI*/2, /*Op*/1, /*Type*/GILLT_s32,
        GIM_CheckType, /*MI*/2, /*Op*/2, /*Type*/GILLT_s32,
        GIM_RecordInsn, /*DefineMI*/3, /*MI*/2, /*OpIdx*/2, // MIs[3]
        GIM_CheckOpcode, /*MI*/3, GIMT_Encode2(TargetOpcode::G_FMAXNUM_IEEE),
        // MIs[3] VOP3Mods:src0:src0_mods
        GIM_CheckIsSameOperand, /*MI*/3, /*OpIdx*/1, /*OtherMI*/1, /*OtherOpIdx*/1,
        // MIs[3] VOP3Mods:src1:src1_mods
        GIM_CheckIsSameOperand, /*MI*/3, /*OpIdx*/2, /*OtherMI*/1, /*OtherOpIdx*/2,
        GIM_CheckCxxInsnPredicate, /*MI*/0, /*FnId*/GIMT_Encode2(GICXXPred_MI_Predicate_fmaxnum_like_nnan),
        GIM_CheckIsSafeToFold, /*InsnID*/1,
        GIM_CheckIsSafeToFold, /*InsnID*/2,
        GIM_CheckIsSafeToFold, /*InsnID*/3,
        GIM_CheckComplexPattern, /*MI*/1, /*Op*/1, /*Renderer*/GIMT_Encode2(0), GIMT_Encode2(GICP_gi_vop3mods),
        GIM_CheckComplexPattern, /*MI*/1, /*Op*/2, /*Renderer*/GIMT_Encode2(1), GIMT_Encode2(GICP_gi_vop3mods),
        GIM_CheckComplexPattern, /*MI*/2, /*Op*/1, /*Renderer*/GIMT_Encode2(2), GIMT_Encode2(GICP_gi_vop3mods),
        // (fmaxnum_ieee:{ *:[f32] } (fminnum_ieee:{ *:[f32] } (VOP3Mods:{ *:[f32] } f32:{ *:[f32] }:$src0, i32:{ *:[i32] }:$src0_mods), (VOP3Mods:{ *:[f32] } f32:{ *:[f32] }:$src1, i32:{ *:[i32] }:$src1_mods)), (fminnum_ieee:{ *:[f32] } (VOP3Mods:{ *:[f32] } f32:{ *:[f32] }:$src2, i32:{ *:[i32] }:$src2_mods), (fmaxnum_ieee:{ *:[f32] } (VOP3Mods:{ *:[f32] } f32:{ *:[f32] }:$src0, i32:{ *:[i32] }:$src0_mods), (VOP3Mods:{ *:[f32] } f32:{ *:[f32] }:$src1, i32:{ *:[i32] }:$src1_mods))))<<P:Predicate_fmaxnum_like_nnan>>  =>  (V_MED3_F32_e64:{ *:[f32] } ?:{ *:[i32] }:$src0_mods, ?:{ *:[f32] }:$src0, ?:{ *:[i32] }:$src1_mods, ?:{ *:[f32] }:$src1, ?:{ *:[i32] }:$src2_mods, ?:{ *:[f32] }:$src2, 0:{ *:[i1] }, 0:{ *:[i32] })
        GIR_BuildMI, /*InsnID*/0, /*Opcode*/GIMT_Encode2(AMDGPU::V_MED3_F32_e64),
        GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/0, // DstI[vdst]
        GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/1, // src0_mods
        GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/0, // src0
        GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(1), /*SubOperand*/1, // src1_mods
        GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(1), /*SubOperand*/0, // src1
        GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(2), /*SubOperand*/1, // src2_mods
        GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(2), /*SubOperand*/0, // src2
        GIR_AddImm8, /*InsnID*/0, /*Imm*/0,
        GIR_AddImm8, /*InsnID*/0, /*Imm*/0,
        GIR_ConstrainSelectedInstOperands, /*InsnID*/0,
        GIR_EraseFromParent, /*InsnID*/0,
        // GIR_Coverage, 10001,
        GIR_Done,
      // Label 5142: @377916
      GIM_Try, /*On fail goto*//*Label 5143*/ GIMT_Encode4(378056), // Rule ID 10002 //
        GIM_CheckRegBankForClass, /*MI*/0, /*Op*/0, /*RC*/GIMT_Encode2(AMDGPU::VGPR_32RegClassID),
        GIM_RecordInsn, /*DefineMI*/1, /*MI*/0, /*OpIdx*/1, // MIs[1]
        GIM_CheckOpcode, /*MI*/1, GIMT_Encode2(TargetOpcode::G_FMINNUM_IEEE),
        GIM_CheckType, /*MI*/1, /*Op*/1, /*Type*/GILLT_s32,
        GIM_CheckType, /*MI*/1, /*Op*/2, /*Type*/GILLT_s32,
        GIM_RecordInsn, /*DefineMI*/2, /*MI*/0, /*OpIdx*/2, // MIs[2]
        GIM_CheckOpcode, /*MI*/2, GIMT_Encode2(TargetOpcode::G_FMINNUM_IEEE),
        GIM_CheckType, /*MI*/2, /*Op*/1, /*Type*/GILLT_s32,
        GIM_CheckType, /*MI*/2, /*Op*/2, /*Type*/GILLT_s32,
        GIM_RecordInsn, /*DefineMI*/3, /*MI*/2, /*OpIdx*/2, // MIs[3]
        GIM_CheckOpcode, /*MI*/3, GIMT_Encode2(TargetOpcode::G_FMAXNUM_IEEE),
        // MIs[3] VOP3Mods:src1:src1_mods
        GIM_CheckIsSameOperand, /*MI*/3, /*OpIdx*/1, /*OtherMI*/1, /*OtherOpIdx*/2,
        // MIs[3] VOP3Mods:src0:src0_mods
        GIM_CheckIsSameOperand, /*MI*/3, /*OpIdx*/2, /*OtherMI*/1, /*OtherOpIdx*/1,
        GIM_CheckCxxInsnPredicate, /*MI*/0, /*FnId*/GIMT_Encode2(GICXXPred_MI_Predicate_fmaxnum_like_nnan),
        GIM_CheckIsSafeToFold, /*InsnID*/1,
        GIM_CheckIsSafeToFold, /*InsnID*/2,
        GIM_CheckIsSafeToFold, /*InsnID*/3,
        GIM_CheckComplexPattern, /*MI*/1, /*Op*/1, /*Renderer*/GIMT_Encode2(0), GIMT_Encode2(GICP_gi_vop3mods),
        GIM_CheckComplexPattern, /*MI*/1, /*Op*/2, /*Renderer*/GIMT_Encode2(1), GIMT_Encode2(GICP_gi_vop3mods),
        GIM_CheckComplexPattern, /*MI*/2, /*Op*/1, /*Renderer*/GIMT_Encode2(2), GIMT_Encode2(GICP_gi_vop3mods),
        // (fmaxnum_ieee:{ *:[f32] } (fminnum_ieee:{ *:[f32] } (VOP3Mods:{ *:[f32] } f32:{ *:[f32] }:$src0, i32:{ *:[i32] }:$src0_mods), (VOP3Mods:{ *:[f32] } f32:{ *:[f32] }:$src1, i32:{ *:[i32] }:$src1_mods)), (fminnum_ieee:{ *:[f32] } (VOP3Mods:{ *:[f32] } f32:{ *:[f32] }:$src2, i32:{ *:[i32] }:$src2_mods), (fmaxnum_ieee:{ *:[f32] } (VOP3Mods:{ *:[f32] } f32:{ *:[f32] }:$src1, i32:{ *:[i32] }:$src1_mods), (VOP3Mods:{ *:[f32] } f32:{ *:[f32] }:$src0, i32:{ *:[i32] }:$src0_mods))))<<P:Predicate_fmaxnum_like_nnan>>  =>  (V_MED3_F32_e64:{ *:[f32] } ?:{ *:[i32] }:$src0_mods, ?:{ *:[f32] }:$src0, ?:{ *:[i32] }:$src1_mods, ?:{ *:[f32] }:$src1, ?:{ *:[i32] }:$src2_mods, ?:{ *:[f32] }:$src2, 0:{ *:[i1] }, 0:{ *:[i32] })
        GIR_BuildMI, /*InsnID*/0, /*Opcode*/GIMT_Encode2(AMDGPU::V_MED3_F32_e64),
        GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/0, // DstI[vdst]
        GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/1, // src0_mods
        GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/0, // src0
        GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(1), /*SubOperand*/1, // src1_mods
        GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(1), /*SubOperand*/0, // src1
        GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(2), /*SubOperand*/1, // src2_mods
        GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(2), /*SubOperand*/0, // src2
        GIR_AddImm8, /*InsnID*/0, /*Imm*/0,
        GIR_AddImm8, /*InsnID*/0, /*Imm*/0,
        GIR_ConstrainSelectedInstOperands, /*InsnID*/0,
        GIR_EraseFromParent, /*InsnID*/0,
        // GIR_Coverage, 10002,
        GIR_Done,
      // Label 5143: @378056
      GIM_Try, /*On fail goto*//*Label 5144*/ GIMT_Encode4(378196), // Rule ID 10005 //
        GIM_CheckRegBankForClass, /*MI*/0, /*Op*/0, /*RC*/GIMT_Encode2(AMDGPU::VGPR_32RegClassID),
        GIM_RecordInsn, /*DefineMI*/1, /*MI*/0, /*OpIdx*/1, // MIs[1]
        GIM_CheckOpcode, /*MI*/1, GIMT_Encode2(TargetOpcode::G_FMINNUM_IEEE),
        GIM_CheckType, /*MI*/1, /*Op*/1, /*Type*/GILLT_s32,
        GIM_CheckType, /*MI*/1, /*Op*/2, /*Type*/GILLT_s32,
        GIM_RecordInsn, /*DefineMI*/2, /*MI*/0, /*OpIdx*/2, // MIs[2]
        GIM_CheckOpcode, /*MI*/2, GIMT_Encode2(TargetOpcode::G_FMINNUM_IEEE),
        GIM_CheckType, /*MI*/2, /*Op*/1, /*Type*/GILLT_s32,
        GIM_CheckType, /*MI*/2, /*Op*/2, /*Type*/GILLT_s32,
        GIM_RecordInsn, /*DefineMI*/3, /*MI*/2, /*OpIdx*/2, // MIs[3]
        GIM_CheckOpcode, /*MI*/3, GIMT_Encode2(TargetOpcode::G_FMAXNUM_IEEE),
        // MIs[3] VOP3Mods:src0:src0_mods
        GIM_CheckIsSameOperand, /*MI*/3, /*OpIdx*/1, /*OtherMI*/1, /*OtherOpIdx*/2,
        // MIs[3] VOP3Mods:src1:src1_mods
        GIM_CheckIsSameOperand, /*MI*/3, /*OpIdx*/2, /*OtherMI*/1, /*OtherOpIdx*/1,
        GIM_CheckCxxInsnPredicate, /*MI*/0, /*FnId*/GIMT_Encode2(GICXXPred_MI_Predicate_fmaxnum_like_nnan),
        GIM_CheckIsSafeToFold, /*InsnID*/1,
        GIM_CheckIsSafeToFold, /*InsnID*/2,
        GIM_CheckIsSafeToFold, /*InsnID*/3,
        GIM_CheckComplexPattern, /*MI*/1, /*Op*/1, /*Renderer*/GIMT_Encode2(0), GIMT_Encode2(GICP_gi_vop3mods),
        GIM_CheckComplexPattern, /*MI*/1, /*Op*/2, /*Renderer*/GIMT_Encode2(1), GIMT_Encode2(GICP_gi_vop3mods),
        GIM_CheckComplexPattern, /*MI*/2, /*Op*/1, /*Renderer*/GIMT_Encode2(2), GIMT_Encode2(GICP_gi_vop3mods),
        // (fmaxnum_ieee:{ *:[f32] } (fminnum_ieee:{ *:[f32] } (VOP3Mods:{ *:[f32] } f32:{ *:[f32] }:$src1, i32:{ *:[i32] }:$src1_mods), (VOP3Mods:{ *:[f32] } f32:{ *:[f32] }:$src0, i32:{ *:[i32] }:$src0_mods)), (fminnum_ieee:{ *:[f32] } (VOP3Mods:{ *:[f32] } f32:{ *:[f32] }:$src2, i32:{ *:[i32] }:$src2_mods), (fmaxnum_ieee:{ *:[f32] } (VOP3Mods:{ *:[f32] } f32:{ *:[f32] }:$src0, i32:{ *:[i32] }:$src0_mods), (VOP3Mods:{ *:[f32] } f32:{ *:[f32] }:$src1, i32:{ *:[i32] }:$src1_mods))))<<P:Predicate_fmaxnum_like_nnan>>  =>  (V_MED3_F32_e64:{ *:[f32] } ?:{ *:[i32] }:$src0_mods, ?:{ *:[f32] }:$src0, ?:{ *:[i32] }:$src1_mods, ?:{ *:[f32] }:$src1, ?:{ *:[i32] }:$src2_mods, ?:{ *:[f32] }:$src2, 0:{ *:[i1] }, 0:{ *:[i32] })
        GIR_BuildMI, /*InsnID*/0, /*Opcode*/GIMT_Encode2(AMDGPU::V_MED3_F32_e64),
        GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/0, // DstI[vdst]
        GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(1), /*SubOperand*/1, // src0_mods
        GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(1), /*SubOperand*/0, // src0
        GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/1, // src1_mods
        GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/0, // src1
        GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(2), /*SubOperand*/1, // src2_mods
        GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(2), /*SubOperand*/0, // src2
        GIR_AddImm8, /*InsnID*/0, /*Imm*/0,
        GIR_AddImm8, /*InsnID*/0, /*Imm*/0,
        GIR_ConstrainSelectedInstOperands, /*InsnID*/0,
        GIR_EraseFromParent, /*InsnID*/0,
        // GIR_Coverage, 10005,
        GIR_Done,
      // Label 5144: @378196
      GIM_Try, /*On fail goto*//*Label 5145*/ GIMT_Encode4(378336), // Rule ID 10006 //
        GIM_CheckRegBankForClass, /*MI*/0, /*Op*/0, /*RC*/GIMT_Encode2(AMDGPU::VGPR_32RegClassID),
        GIM_RecordInsn, /*DefineMI*/1, /*MI*/0, /*OpIdx*/1, // MIs[1]
        GIM_CheckOpcode, /*MI*/1, GIMT_Encode2(TargetOpcode::G_FMINNUM_IEEE),
        GIM_CheckType, /*MI*/1, /*Op*/1, /*Type*/GILLT_s32,
        GIM_CheckType, /*MI*/1, /*Op*/2, /*Type*/GILLT_s32,
        GIM_RecordInsn, /*DefineMI*/2, /*MI*/0, /*OpIdx*/2, // MIs[2]
        GIM_CheckOpcode, /*MI*/2, GIMT_Encode2(TargetOpcode::G_FMINNUM_IEEE),
        GIM_CheckType, /*MI*/2, /*Op*/1, /*Type*/GILLT_s32,
        GIM_CheckType, /*MI*/2, /*Op*/2, /*Type*/GILLT_s32,
        GIM_RecordInsn, /*DefineMI*/3, /*MI*/2, /*OpIdx*/2, // MIs[3]
        GIM_CheckOpcode, /*MI*/3, GIMT_Encode2(TargetOpcode::G_FMAXNUM_IEEE),
        // MIs[3] VOP3Mods:src1:src1_mods
        GIM_CheckIsSameOperand, /*MI*/3, /*OpIdx*/1, /*OtherMI*/1, /*OtherOpIdx*/1,
        // MIs[3] VOP3Mods:src0:src0_mods
        GIM_CheckIsSameOperand, /*MI*/3, /*OpIdx*/2, /*OtherMI*/1, /*OtherOpIdx*/2,
        GIM_CheckCxxInsnPredicate, /*MI*/0, /*FnId*/GIMT_Encode2(GICXXPred_MI_Predicate_fmaxnum_like_nnan),
        GIM_CheckIsSafeToFold, /*InsnID*/1,
        GIM_CheckIsSafeToFold, /*InsnID*/2,
        GIM_CheckIsSafeToFold, /*InsnID*/3,
        GIM_CheckComplexPattern, /*MI*/1, /*Op*/1, /*Renderer*/GIMT_Encode2(0), GIMT_Encode2(GICP_gi_vop3mods),
        GIM_CheckComplexPattern, /*MI*/1, /*Op*/2, /*Renderer*/GIMT_Encode2(1), GIMT_Encode2(GICP_gi_vop3mods),
        GIM_CheckComplexPattern, /*MI*/2, /*Op*/1, /*Renderer*/GIMT_Encode2(2), GIMT_Encode2(GICP_gi_vop3mods),
        // (fmaxnum_ieee:{ *:[f32] } (fminnum_ieee:{ *:[f32] } (VOP3Mods:{ *:[f32] } f32:{ *:[f32] }:$src1, i32:{ *:[i32] }:$src1_mods), (VOP3Mods:{ *:[f32] } f32:{ *:[f32] }:$src0, i32:{ *:[i32] }:$src0_mods)), (fminnum_ieee:{ *:[f32] } (VOP3Mods:{ *:[f32] } f32:{ *:[f32] }:$src2, i32:{ *:[i32] }:$src2_mods), (fmaxnum_ieee:{ *:[f32] } (VOP3Mods:{ *:[f32] } f32:{ *:[f32] }:$src1, i32:{ *:[i32] }:$src1_mods), (VOP3Mods:{ *:[f32] } f32:{ *:[f32] }:$src0, i32:{ *:[i32] }:$src0_mods))))<<P:Predicate_fmaxnum_like_nnan>>  =>  (V_MED3_F32_e64:{ *:[f32] } ?:{ *:[i32] }:$src0_mods, ?:{ *:[f32] }:$src0, ?:{ *:[i32] }:$src1_mods, ?:{ *:[f32] }:$src1, ?:{ *:[i32] }:$src2_mods, ?:{ *:[f32] }:$src2, 0:{ *:[i1] }, 0:{ *:[i32] })
        GIR_BuildMI, /*InsnID*/0, /*Opcode*/GIMT_Encode2(AMDGPU::V_MED3_F32_e64),
        GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/0, // DstI[vdst]
        GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(1), /*SubOperand*/1, // src0_mods
        GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(1), /*SubOperand*/0, // src0
        GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/1, // src1_mods
        GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/0, // src1
        GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(2), /*SubOperand*/1, // src2_mods
        GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(2), /*SubOperand*/0, // src2
        GIR_AddImm8, /*InsnID*/0, /*Imm*/0,
        GIR_AddImm8, /*InsnID*/0, /*Imm*/0,
        GIR_ConstrainSelectedInstOperands, /*InsnID*/0,
        GIR_EraseFromParent, /*InsnID*/0,
        // GIR_Coverage, 10006,
        GIR_Done,
      // Label 5145: @378336
      GIM_Try, /*On fail goto*//*Label 5146*/ GIMT_Encode4(378476), // Rule ID 6483 //
        GIM_CheckRegBankForClass, /*MI*/0, /*Op*/0, /*RC*/GIMT_Encode2(AMDGPU::VGPR_32RegClassID),
        GIM_RecordInsn, /*DefineMI*/1, /*MI*/0, /*OpIdx*/1, // MIs[1]
        GIM_CheckOpcode, /*MI*/1, GIMT_Encode2(TargetOpcode::G_FMINNUM_IEEE),
        GIM_CheckType, /*MI*/1, /*Op*/1, /*Type*/GILLT_s32,
        GIM_CheckType, /*MI*/1, /*Op*/2, /*Type*/GILLT_s32,
        GIM_RecordInsn, /*DefineMI*/2, /*MI*/0, /*OpIdx*/2, // MIs[2]
        GIM_CheckOpcode, /*MI*/2, GIMT_Encode2(TargetOpcode::G_FMINNUM_IEEE),
        GIM_CheckType, /*MI*/2, /*Op*/1, /*Type*/GILLT_s32,
        GIM_CheckType, /*MI*/2, /*Op*/2, /*Type*/GILLT_s32,
        GIM_RecordInsn, /*DefineMI*/3, /*MI*/2, /*OpIdx*/1, // MIs[3]
        GIM_CheckOpcode, /*MI*/3, GIMT_Encode2(TargetOpcode::G_FMAXNUM),
        // MIs[3] VOP3Mods:src0:src0_mods
        GIM_CheckIsSameOperand, /*MI*/3, /*OpIdx*/1, /*OtherMI*/1, /*OtherOpIdx*/1,
        // MIs[3] VOP3Mods:src1:src1_mods
        GIM_CheckIsSameOperand, /*MI*/3, /*OpIdx*/2, /*OtherMI*/1, /*OtherOpIdx*/2,
        GIM_CheckCxxInsnPredicate, /*MI*/0, /*FnId*/GIMT_Encode2(GICXXPred_MI_Predicate_fmaxnum_like_nnan),
        GIM_CheckIsSafeToFold, /*InsnID*/1,
        GIM_CheckIsSafeToFold, /*InsnID*/2,
        GIM_CheckIsSafeToFold, /*InsnID*/3,
        GIM_CheckComplexPattern, /*MI*/1, /*Op*/1, /*Renderer*/GIMT_Encode2(0), GIMT_Encode2(GICP_gi_vop3mods),
        GIM_CheckComplexPattern, /*MI*/1, /*Op*/2, /*Renderer*/GIMT_Encode2(1), GIMT_Encode2(GICP_gi_vop3mods),
        GIM_CheckComplexPattern, /*MI*/2, /*Op*/2, /*Renderer*/GIMT_Encode2(2), GIMT_Encode2(GICP_gi_vop3mods),
        // (fmaxnum_ieee:{ *:[f32] } (fminnum_ieee:{ *:[f32] } (VOP3Mods:{ *:[f32] } f32:{ *:[f32] }:$src0, i32:{ *:[i32] }:$src0_mods), (VOP3Mods:{ *:[f32] } f32:{ *:[f32] }:$src1, i32:{ *:[i32] }:$src1_mods)), (fminnum_ieee:{ *:[f32] } (fmaxnum:{ *:[f32] } (VOP3Mods:{ *:[f32] } f32:{ *:[f32] }:$src0, i32:{ *:[i32] }:$src0_mods), (VOP3Mods:{ *:[f32] } f32:{ *:[f32] }:$src1, i32:{ *:[i32] }:$src1_mods)), (VOP3Mods:{ *:[f32] } f32:{ *:[f32] }:$src2, i32:{ *:[i32] }:$src2_mods)))<<P:Predicate_fmaxnum_like_nnan>>  =>  (V_MED3_F32_e64:{ *:[f32] } ?:{ *:[i32] }:$src0_mods, ?:{ *:[f32] }:$src0, ?:{ *:[i32] }:$src1_mods, ?:{ *:[f32] }:$src1, ?:{ *:[i32] }:$src2_mods, ?:{ *:[f32] }:$src2, 0:{ *:[i1] }, 0:{ *:[i32] })
        GIR_BuildMI, /*InsnID*/0, /*Opcode*/GIMT_Encode2(AMDGPU::V_MED3_F32_e64),
        GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/0, // DstI[vdst]
        GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/1, // src0_mods
        GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/0, // src0
        GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(1), /*SubOperand*/1, // src1_mods
        GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(1), /*SubOperand*/0, // src1
        GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(2), /*SubOperand*/1, // src2_mods
        GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(2), /*SubOperand*/0, // src2
        GIR_AddImm8, /*InsnID*/0, /*Imm*/0,
        GIR_AddImm8, /*InsnID*/0, /*Imm*/0,
        GIR_ConstrainSelectedInstOperands, /*InsnID*/0,
        GIR_EraseFromParent, /*InsnID*/0,
        // GIR_Coverage, 6483,
        GIR_Done,
      // Label 5146: @378476
      GIM_Try, /*On fail goto*//*Label 5147*/ GIMT_Encode4(378616), // Rule ID 10015 //
        GIM_CheckRegBankForClass, /*MI*/0, /*Op*/0, /*RC*/GIMT_Encode2(AMDGPU::VGPR_32RegClassID),
        GIM_RecordInsn, /*DefineMI*/1, /*MI*/0, /*OpIdx*/1, // MIs[1]
        GIM_CheckOpcode, /*MI*/1, GIMT_Encode2(TargetOpcode::G_FMINNUM_IEEE),
        GIM_CheckType, /*MI*/1, /*Op*/1, /*Type*/GILLT_s32,
        GIM_CheckType, /*MI*/1, /*Op*/2, /*Type*/GILLT_s32,
        GIM_RecordInsn, /*DefineMI*/2, /*MI*/0, /*OpIdx*/2, // MIs[2]
        GIM_CheckOpcode, /*MI*/2, GIMT_Encode2(TargetOpcode::G_FMINNUM_IEEE),
        GIM_CheckType, /*MI*/2, /*Op*/1, /*Type*/GILLT_s32,
        GIM_CheckType, /*MI*/2, /*Op*/2, /*Type*/GILLT_s32,
        GIM_RecordInsn, /*DefineMI*/3, /*MI*/2, /*OpIdx*/1, // MIs[3]
        GIM_CheckOpcode, /*MI*/3, GIMT_Encode2(TargetOpcode::G_FMAXNUM),
        // MIs[3] VOP3Mods:src1:src1_mods
        GIM_CheckIsSameOperand, /*MI*/3, /*OpIdx*/1, /*OtherMI*/1, /*OtherOpIdx*/2,
        // MIs[3] VOP3Mods:src0:src0_mods
        GIM_CheckIsSameOperand, /*MI*/3, /*OpIdx*/2, /*OtherMI*/1, /*OtherOpIdx*/1,
        GIM_CheckCxxInsnPredicate, /*MI*/0, /*FnId*/GIMT_Encode2(GICXXPred_MI_Predicate_fmaxnum_like_nnan),
        GIM_CheckIsSafeToFold, /*InsnID*/1,
        GIM_CheckIsSafeToFold, /*InsnID*/2,
        GIM_CheckIsSafeToFold, /*InsnID*/3,
        GIM_CheckComplexPattern, /*MI*/1, /*Op*/1, /*Renderer*/GIMT_Encode2(0), GIMT_Encode2(GICP_gi_vop3mods),
        GIM_CheckComplexPattern, /*MI*/1, /*Op*/2, /*Renderer*/GIMT_Encode2(1), GIMT_Encode2(GICP_gi_vop3mods),
        GIM_CheckComplexPattern, /*MI*/2, /*Op*/2, /*Renderer*/GIMT_Encode2(2), GIMT_Encode2(GICP_gi_vop3mods),
        // (fmaxnum_ieee:{ *:[f32] } (fminnum_ieee:{ *:[f32] } (VOP3Mods:{ *:[f32] } f32:{ *:[f32] }:$src0, i32:{ *:[i32] }:$src0_mods), (VOP3Mods:{ *:[f32] } f32:{ *:[f32] }:$src1, i32:{ *:[i32] }:$src1_mods)), (fminnum_ieee:{ *:[f32] } (fmaxnum:{ *:[f32] } (VOP3Mods:{ *:[f32] } f32:{ *:[f32] }:$src1, i32:{ *:[i32] }:$src1_mods), (VOP3Mods:{ *:[f32] } f32:{ *:[f32] }:$src0, i32:{ *:[i32] }:$src0_mods)), (VOP3Mods:{ *:[f32] } f32:{ *:[f32] }:$src2, i32:{ *:[i32] }:$src2_mods)))<<P:Predicate_fmaxnum_like_nnan>>  =>  (V_MED3_F32_e64:{ *:[f32] } ?:{ *:[i32] }:$src0_mods, ?:{ *:[f32] }:$src0, ?:{ *:[i32] }:$src1_mods, ?:{ *:[f32] }:$src1, ?:{ *:[i32] }:$src2_mods, ?:{ *:[f32] }:$src2, 0:{ *:[i1] }, 0:{ *:[i32] })
        GIR_BuildMI, /*InsnID*/0, /*Opcode*/GIMT_Encode2(AMDGPU::V_MED3_F32_e64),
        GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/0, // DstI[vdst]
        GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/1, // src0_mods
        GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/0, // src0
        GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(1), /*SubOperand*/1, // src1_mods
        GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(1), /*SubOperand*/0, // src1
        GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(2), /*SubOperand*/1, // src2_mods
        GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(2), /*SubOperand*/0, // src2
        GIR_AddImm8, /*InsnID*/0, /*Imm*/0,
        GIR_AddImm8, /*InsnID*/0, /*Imm*/0,
        GIR_ConstrainSelectedInstOperands, /*InsnID*/0,
        GIR_EraseFromParent, /*InsnID*/0,
        // GIR_Coverage, 10015,
        GIR_Done,
      // Label 5147: @378616
      GIM_Try, /*On fail goto*//*Label 5148*/ GIMT_Encode4(378756), // Rule ID 10018 //
        GIM_CheckRegBankForClass, /*MI*/0, /*Op*/0, /*RC*/GIMT_Encode2(AMDGPU::VGPR_32RegClassID),
        GIM_RecordInsn, /*DefineMI*/1, /*MI*/0, /*OpIdx*/1, // MIs[1]
        GIM_CheckOpcode, /*MI*/1, GIMT_Encode2(TargetOpcode::G_FMINNUM_IEEE),
        GIM_CheckType, /*MI*/1, /*Op*/1, /*Type*/GILLT_s32,
        GIM_CheckType, /*MI*/1, /*Op*/2, /*Type*/GILLT_s32,
        GIM_RecordInsn, /*DefineMI*/2, /*MI*/0, /*OpIdx*/2, // MIs[2]
        GIM_CheckOpcode, /*MI*/2, GIMT_Encode2(TargetOpcode::G_FMINNUM_IEEE),
        GIM_CheckType, /*MI*/2, /*Op*/1, /*Type*/GILLT_s32,
        GIM_CheckType, /*MI*/2, /*Op*/2, /*Type*/GILLT_s32,
        GIM_RecordInsn, /*DefineMI*/3, /*MI*/2, /*OpIdx*/1, // MIs[3]
        GIM_CheckOpcode, /*MI*/3, GIMT_Encode2(TargetOpcode::G_FMAXNUM),
        // MIs[3] VOP3Mods:src0:src0_mods
        GIM_CheckIsSameOperand, /*MI*/3, /*OpIdx*/1, /*OtherMI*/1, /*OtherOpIdx*/2,
        // MIs[3] VOP3Mods:src1:src1_mods
        GIM_CheckIsSameOperand, /*MI*/3, /*OpIdx*/2, /*OtherMI*/1, /*OtherOpIdx*/1,
        GIM_CheckCxxInsnPredicate, /*MI*/0, /*FnId*/GIMT_Encode2(GICXXPred_MI_Predicate_fmaxnum_like_nnan),
        GIM_CheckIsSafeToFold, /*InsnID*/1,
        GIM_CheckIsSafeToFold, /*InsnID*/2,
        GIM_CheckIsSafeToFold, /*InsnID*/3,
        GIM_CheckComplexPattern, /*MI*/1, /*Op*/1, /*Renderer*/GIMT_Encode2(0), GIMT_Encode2(GICP_gi_vop3mods),
        GIM_CheckComplexPattern, /*MI*/1, /*Op*/2, /*Renderer*/GIMT_Encode2(1), GIMT_Encode2(GICP_gi_vop3mods),
        GIM_CheckComplexPattern, /*MI*/2, /*Op*/2, /*Renderer*/GIMT_Encode2(2), GIMT_Encode2(GICP_gi_vop3mods),
        // (fmaxnum_ieee:{ *:[f32] } (fminnum_ieee:{ *:[f32] } (VOP3Mods:{ *:[f32] } f32:{ *:[f32] }:$src1, i32:{ *:[i32] }:$src1_mods), (VOP3Mods:{ *:[f32] } f32:{ *:[f32] }:$src0, i32:{ *:[i32] }:$src0_mods)), (fminnum_ieee:{ *:[f32] } (fmaxnum:{ *:[f32] } (VOP3Mods:{ *:[f32] } f32:{ *:[f32] }:$src0, i32:{ *:[i32] }:$src0_mods), (VOP3Mods:{ *:[f32] } f32:{ *:[f32] }:$src1, i32:{ *:[i32] }:$src1_mods)), (VOP3Mods:{ *:[f32] } f32:{ *:[f32] }:$src2, i32:{ *:[i32] }:$src2_mods)))<<P:Predicate_fmaxnum_like_nnan>>  =>  (V_MED3_F32_e64:{ *:[f32] } ?:{ *:[i32] }:$src0_mods, ?:{ *:[f32] }:$src0, ?:{ *:[i32] }:$src1_mods, ?:{ *:[f32] }:$src1, ?:{ *:[i32] }:$src2_mods, ?:{ *:[f32] }:$src2, 0:{ *:[i1] }, 0:{ *:[i32] })
        GIR_BuildMI, /*InsnID*/0, /*Opcode*/GIMT_Encode2(AMDGPU::V_MED3_F32_e64),
        GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/0, // DstI[vdst]
        GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(1), /*SubOperand*/1, // src0_mods
        GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(1), /*SubOperand*/0, // src0
        GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/1, // src1_mods
        GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/0, // src1
        GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(2), /*SubOperand*/1, // src2_mods
        GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(2), /*SubOperand*/0, // src2
        GIR_AddImm8, /*InsnID*/0, /*Imm*/0,
        GIR_AddImm8, /*InsnID*/0, /*Imm*/0,
        GIR_ConstrainSelectedInstOperands, /*InsnID*/0,
        GIR_EraseFromParent, /*InsnID*/0,
        // GIR_Coverage, 10018,
        GIR_Done,
      // Label 5148: @378756
      GIM_Try, /*On fail goto*//*Label 5149*/ GIMT_Encode4(378896), // Rule ID 10019 //
        GIM_CheckRegBankForClass, /*MI*/0, /*Op*/0, /*RC*/GIMT_Encode2(AMDGPU::VGPR_32RegClassID),
        GIM_RecordInsn, /*DefineMI*/1, /*MI*/0, /*OpIdx*/1, // MIs[1]
        GIM_CheckOpcode, /*MI*/1, GIMT_Encode2(TargetOpcode::G_FMINNUM_IEEE),
        GIM_CheckType, /*MI*/1, /*Op*/1, /*Type*/GILLT_s32,
        GIM_CheckType, /*MI*/1, /*Op*/2, /*Type*/GILLT_s32,
        GIM_RecordInsn, /*DefineMI*/2, /*MI*/0, /*OpIdx*/2, // MIs[2]
        GIM_CheckOpcode, /*MI*/2, GIMT_Encode2(TargetOpcode::G_FMINNUM_IEEE),
        GIM_CheckType, /*MI*/2, /*Op*/1, /*Type*/GILLT_s32,
        GIM_CheckType, /*MI*/2, /*Op*/2, /*Type*/GILLT_s32,
        GIM_RecordInsn, /*DefineMI*/3, /*MI*/2, /*OpIdx*/1, // MIs[3]
        GIM_CheckOpcode, /*MI*/3, GIMT_Encode2(TargetOpcode::G_FMAXNUM),
        // MIs[3] VOP3Mods:src1:src1_mods
        GIM_CheckIsSameOperand, /*MI*/3, /*OpIdx*/1, /*OtherMI*/1, /*OtherOpIdx*/1,
        // MIs[3] VOP3Mods:src0:src0_mods
        GIM_CheckIsSameOperand, /*MI*/3, /*OpIdx*/2, /*OtherMI*/1, /*OtherOpIdx*/2,
        GIM_CheckCxxInsnPredicate, /*MI*/0, /*FnId*/GIMT_Encode2(GICXXPred_MI_Predicate_fmaxnum_like_nnan),
        GIM_CheckIsSafeToFold, /*InsnID*/1,
        GIM_CheckIsSafeToFold, /*InsnID*/2,
        GIM_CheckIsSafeToFold, /*InsnID*/3,
        GIM_CheckComplexPattern, /*MI*/1, /*Op*/1, /*Renderer*/GIMT_Encode2(0), GIMT_Encode2(GICP_gi_vop3mods),
        GIM_CheckComplexPattern, /*MI*/1, /*Op*/2, /*Renderer*/GIMT_Encode2(1), GIMT_Encode2(GICP_gi_vop3mods),
        GIM_CheckComplexPattern, /*MI*/2, /*Op*/2, /*Renderer*/GIMT_Encode2(2), GIMT_Encode2(GICP_gi_vop3mods),
        // (fmaxnum_ieee:{ *:[f32] } (fminnum_ieee:{ *:[f32] } (VOP3Mods:{ *:[f32] } f32:{ *:[f32] }:$src1, i32:{ *:[i32] }:$src1_mods), (VOP3Mods:{ *:[f32] } f32:{ *:[f32] }:$src0, i32:{ *:[i32] }:$src0_mods)), (fminnum_ieee:{ *:[f32] } (fmaxnum:{ *:[f32] } (VOP3Mods:{ *:[f32] } f32:{ *:[f32] }:$src1, i32:{ *:[i32] }:$src1_mods), (VOP3Mods:{ *:[f32] } f32:{ *:[f32] }:$src0, i32:{ *:[i32] }:$src0_mods)), (VOP3Mods:{ *:[f32] } f32:{ *:[f32] }:$src2, i32:{ *:[i32] }:$src2_mods)))<<P:Predicate_fmaxnum_like_nnan>>  =>  (V_MED3_F32_e64:{ *:[f32] } ?:{ *:[i32] }:$src0_mods, ?:{ *:[f32] }:$src0, ?:{ *:[i32] }:$src1_mods, ?:{ *:[f32] }:$src1, ?:{ *:[i32] }:$src2_mods, ?:{ *:[f32] }:$src2, 0:{ *:[i1] }, 0:{ *:[i32] })
        GIR_BuildMI, /*InsnID*/0, /*Opcode*/GIMT_Encode2(AMDGPU::V_MED3_F32_e64),
        GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/0, // DstI[vdst]
        GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(1), /*SubOperand*/1, // src0_mods
        GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(1), /*SubOperand*/0, // src0
        GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/1, // src1_mods
        GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/0, // src1
        GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(2), /*SubOperand*/1, // src2_mods
        GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(2), /*SubOperand*/0, // src2
        GIR_AddImm8, /*InsnID*/0, /*Imm*/0,
        GIR_AddImm8, /*InsnID*/0, /*Imm*/0,
        GIR_ConstrainSelectedInstOperands, /*InsnID*/0,
        GIR_EraseFromParent, /*InsnID*/0,
        // GIR_Coverage, 10019,
        GIR_Done,
      // Label 5149: @378896
      GIM_Try, /*On fail goto*//*Label 5150*/ GIMT_Encode4(379036), // Rule ID 6482 //
        GIM_CheckRegBankForClass, /*MI*/0, /*Op*/0, /*RC*/GIMT_Encode2(AMDGPU::VGPR_32RegClassID),
        GIM_RecordInsn, /*DefineMI*/1, /*MI*/0, /*OpIdx*/1, // MIs[1]
        GIM_CheckOpcode, /*MI*/1, GIMT_Encode2(TargetOpcode::G_FMINNUM_IEEE),
        GIM_CheckType, /*MI*/1, /*Op*/1, /*Type*/GILLT_s32,
        GIM_CheckType, /*MI*/1, /*Op*/2, /*Type*/GILLT_s32,
        GIM_RecordInsn, /*DefineMI*/2, /*MI*/0, /*OpIdx*/2, // MIs[2]
        GIM_CheckOpcode, /*MI*/2, GIMT_Encode2(TargetOpcode::G_FMINNUM_IEEE),
        GIM_CheckType, /*MI*/2, /*Op*/1, /*Type*/GILLT_s32,
        GIM_CheckType, /*MI*/2, /*Op*/2, /*Type*/GILLT_s32,
        GIM_RecordInsn, /*DefineMI*/3, /*MI*/2, /*OpIdx*/1, // MIs[3]
        GIM_CheckOpcode, /*MI*/3, GIMT_Encode2(TargetOpcode::G_FMAXNUM_IEEE),
        // MIs[3] VOP3Mods:src0:src0_mods
        GIM_CheckIsSameOperand, /*MI*/3, /*OpIdx*/1, /*OtherMI*/1, /*OtherOpIdx*/1,
        // MIs[3] VOP3Mods:src1:src1_mods
        GIM_CheckIsSameOperand, /*MI*/3, /*OpIdx*/2, /*OtherMI*/1, /*OtherOpIdx*/2,
        GIM_CheckCxxInsnPredicate, /*MI*/0, /*FnId*/GIMT_Encode2(GICXXPred_MI_Predicate_fmaxnum_like_nnan),
        GIM_CheckIsSafeToFold, /*InsnID*/1,
        GIM_CheckIsSafeToFold, /*InsnID*/2,
        GIM_CheckIsSafeToFold, /*InsnID*/3,
        GIM_CheckComplexPattern, /*MI*/1, /*Op*/1, /*Renderer*/GIMT_Encode2(0), GIMT_Encode2(GICP_gi_vop3mods),
        GIM_CheckComplexPattern, /*MI*/1, /*Op*/2, /*Renderer*/GIMT_Encode2(1), GIMT_Encode2(GICP_gi_vop3mods),
        GIM_CheckComplexPattern, /*MI*/2, /*Op*/2, /*Renderer*/GIMT_Encode2(2), GIMT_Encode2(GICP_gi_vop3mods),
        // (fmaxnum_ieee:{ *:[f32] } (fminnum_ieee:{ *:[f32] } (VOP3Mods:{ *:[f32] } f32:{ *:[f32] }:$src0, i32:{ *:[i32] }:$src0_mods), (VOP3Mods:{ *:[f32] } f32:{ *:[f32] }:$src1, i32:{ *:[i32] }:$src1_mods)), (fminnum_ieee:{ *:[f32] } (fmaxnum_ieee:{ *:[f32] } (VOP3Mods:{ *:[f32] } f32:{ *:[f32] }:$src0, i32:{ *:[i32] }:$src0_mods), (VOP3Mods:{ *:[f32] } f32:{ *:[f32] }:$src1, i32:{ *:[i32] }:$src1_mods)), (VOP3Mods:{ *:[f32] } f32:{ *:[f32] }:$src2, i32:{ *:[i32] }:$src2_mods)))<<P:Predicate_fmaxnum_like_nnan>>  =>  (V_MED3_F32_e64:{ *:[f32] } ?:{ *:[i32] }:$src0_mods, ?:{ *:[f32] }:$src0, ?:{ *:[i32] }:$src1_mods, ?:{ *:[f32] }:$src1, ?:{ *:[i32] }:$src2_mods, ?:{ *:[f32] }:$src2, 0:{ *:[i1] }, 0:{ *:[i32] })
        GIR_BuildMI, /*InsnID*/0, /*Opcode*/GIMT_Encode2(AMDGPU::V_MED3_F32_e64),
        GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/0, // DstI[vdst]
        GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/1, // src0_mods
        GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/0, // src0
        GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(1), /*SubOperand*/1, // src1_mods
        GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(1), /*SubOperand*/0, // src1
        GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(2), /*SubOperand*/1, // src2_mods
        GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(2), /*SubOperand*/0, // src2
        GIR_AddImm8, /*InsnID*/0, /*Imm*/0,
        GIR_AddImm8, /*InsnID*/0, /*Imm*/0,
        GIR_ConstrainSelectedInstOperands, /*InsnID*/0,
        GIR_EraseFromParent, /*InsnID*/0,
        // GIR_Coverage, 6482,
        GIR_Done,
      // Label 5150: @379036
      GIM_Try, /*On fail goto*//*Label 5151*/ GIMT_Encode4(379176), // Rule ID 10000 //
        GIM_CheckRegBankForClass, /*MI*/0, /*Op*/0, /*RC*/GIMT_Encode2(AMDGPU::VGPR_32RegClassID),
        GIM_RecordInsn, /*DefineMI*/1, /*MI*/0, /*OpIdx*/1, // MIs[1]
        GIM_CheckOpcode, /*MI*/1, GIMT_Encode2(TargetOpcode::G_FMINNUM_IEEE),
        GIM_CheckType, /*MI*/1, /*Op*/1, /*Type*/GILLT_s32,
        GIM_CheckType, /*MI*/1, /*Op*/2, /*Type*/GILLT_s32,
        GIM_RecordInsn, /*DefineMI*/2, /*MI*/0, /*OpIdx*/2, // MIs[2]
        GIM_CheckOpcode, /*MI*/2, GIMT_Encode2(TargetOpcode::G_FMINNUM_IEEE),
        GIM_CheckType, /*MI*/2, /*Op*/1, /*Type*/GILLT_s32,
        GIM_CheckType, /*MI*/2, /*Op*/2, /*Type*/GILLT_s32,
        GIM_RecordInsn, /*DefineMI*/3, /*MI*/2, /*OpIdx*/1, // MIs[3]
        GIM_CheckOpcode, /*MI*/3, GIMT_Encode2(TargetOpcode::G_FMAXNUM_IEEE),
        // MIs[3] VOP3Mods:src1:src1_mods
        GIM_CheckIsSameOperand, /*MI*/3, /*OpIdx*/1, /*OtherMI*/1, /*OtherOpIdx*/2,
        // MIs[3] VOP3Mods:src0:src0_mods
        GIM_CheckIsSameOperand, /*MI*/3, /*OpIdx*/2, /*OtherMI*/1, /*OtherOpIdx*/1,
        GIM_CheckCxxInsnPredicate, /*MI*/0, /*FnId*/GIMT_Encode2(GICXXPred_MI_Predicate_fmaxnum_like_nnan),
        GIM_CheckIsSafeToFold, /*InsnID*/1,
        GIM_CheckIsSafeToFold, /*InsnID*/2,
        GIM_CheckIsSafeToFold, /*InsnID*/3,
        GIM_CheckComplexPattern, /*MI*/1, /*Op*/1, /*Renderer*/GIMT_Encode2(0), GIMT_Encode2(GICP_gi_vop3mods),
        GIM_CheckComplexPattern, /*MI*/1, /*Op*/2, /*Renderer*/GIMT_Encode2(1), GIMT_Encode2(GICP_gi_vop3mods),
        GIM_CheckComplexPattern, /*MI*/2, /*Op*/2, /*Renderer*/GIMT_Encode2(2), GIMT_Encode2(GICP_gi_vop3mods),
        // (fmaxnum_ieee:{ *:[f32] } (fminnum_ieee:{ *:[f32] } (VOP3Mods:{ *:[f32] } f32:{ *:[f32] }:$src0, i32:{ *:[i32] }:$src0_mods), (VOP3Mods:{ *:[f32] } f32:{ *:[f32] }:$src1, i32:{ *:[i32] }:$src1_mods)), (fminnum_ieee:{ *:[f32] } (fmaxnum_ieee:{ *:[f32] } (VOP3Mods:{ *:[f32] } f32:{ *:[f32] }:$src1, i32:{ *:[i32] }:$src1_mods), (VOP3Mods:{ *:[f32] } f32:{ *:[f32] }:$src0, i32:{ *:[i32] }:$src0_mods)), (VOP3Mods:{ *:[f32] } f32:{ *:[f32] }:$src2, i32:{ *:[i32] }:$src2_mods)))<<P:Predicate_fmaxnum_like_nnan>>  =>  (V_MED3_F32_e64:{ *:[f32] } ?:{ *:[i32] }:$src0_mods, ?:{ *:[f32] }:$src0, ?:{ *:[i32] }:$src1_mods, ?:{ *:[f32] }:$src1, ?:{ *:[i32] }:$src2_mods, ?:{ *:[f32] }:$src2, 0:{ *:[i1] }, 0:{ *:[i32] })
        GIR_BuildMI, /*InsnID*/0, /*Opcode*/GIMT_Encode2(AMDGPU::V_MED3_F32_e64),
        GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/0, // DstI[vdst]
        GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/1, // src0_mods
        GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/0, // src0
        GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(1), /*SubOperand*/1, // src1_mods
        GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(1), /*SubOperand*/0, // src1
        GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(2), /*SubOperand*/1, // src2_mods
        GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(2), /*SubOperand*/0, // src2
        GIR_AddImm8, /*InsnID*/0, /*Imm*/0,
        GIR_AddImm8, /*InsnID*/0, /*Imm*/0,
        GIR_ConstrainSelectedInstOperands, /*InsnID*/0,
        GIR_EraseFromParent, /*InsnID*/0,
        // GIR_Coverage, 10000,
        GIR_Done,
      // Label 5151: @379176
      GIM_Try, /*On fail goto*//*Label 5152*/ GIMT_Encode4(379316), // Rule ID 10003 //
        GIM_CheckRegBankForClass, /*MI*/0, /*Op*/0, /*RC*/GIMT_Encode2(AMDGPU::VGPR_32RegClassID),
        GIM_RecordInsn, /*DefineMI*/1, /*MI*/0, /*OpIdx*/1, // MIs[1]
        GIM_CheckOpcode, /*MI*/1, GIMT_Encode2(TargetOpcode::G_FMINNUM_IEEE),
        GIM_CheckType, /*MI*/1, /*Op*/1, /*Type*/GILLT_s32,
        GIM_CheckType, /*MI*/1, /*Op*/2, /*Type*/GILLT_s32,
        GIM_RecordInsn, /*DefineMI*/2, /*MI*/0, /*OpIdx*/2, // MIs[2]
        GIM_CheckOpcode, /*MI*/2, GIMT_Encode2(TargetOpcode::G_FMINNUM_IEEE),
        GIM_CheckType, /*MI*/2, /*Op*/1, /*Type*/GILLT_s32,
        GIM_CheckType, /*MI*/2, /*Op*/2, /*Type*/GILLT_s32,
        GIM_RecordInsn, /*DefineMI*/3, /*MI*/2, /*OpIdx*/1, // MIs[3]
        GIM_CheckOpcode, /*MI*/3, GIMT_Encode2(TargetOpcode::G_FMAXNUM_IEEE),
        // MIs[3] VOP3Mods:src0:src0_mods
        GIM_CheckIsSameOperand, /*MI*/3, /*OpIdx*/1, /*OtherMI*/1, /*OtherOpIdx*/2,
        // MIs[3] VOP3Mods:src1:src1_mods
        GIM_CheckIsSameOperand, /*MI*/3, /*OpIdx*/2, /*OtherMI*/1, /*OtherOpIdx*/1,
        GIM_CheckCxxInsnPredicate, /*MI*/0, /*FnId*/GIMT_Encode2(GICXXPred_MI_Predicate_fmaxnum_like_nnan),
        GIM_CheckIsSafeToFold, /*InsnID*/1,
        GIM_CheckIsSafeToFold, /*InsnID*/2,
        GIM_CheckIsSafeToFold, /*InsnID*/3,
        GIM_CheckComplexPattern, /*MI*/1, /*Op*/1, /*Renderer*/GIMT_Encode2(0), GIMT_Encode2(GICP_gi_vop3mods),
        GIM_CheckComplexPattern, /*MI*/1, /*Op*/2, /*Renderer*/GIMT_Encode2(1), GIMT_Encode2(GICP_gi_vop3mods),
        GIM_CheckComplexPattern, /*MI*/2, /*Op*/2, /*Renderer*/GIMT_Encode2(2), GIMT_Encode2(GICP_gi_vop3mods),
        // (fmaxnum_ieee:{ *:[f32] } (fminnum_ieee:{ *:[f32] } (VOP3Mods:{ *:[f32] } f32:{ *:[f32] }:$src1, i32:{ *:[i32] }:$src1_mods), (VOP3Mods:{ *:[f32] } f32:{ *:[f32] }:$src0, i32:{ *:[i32] }:$src0_mods)), (fminnum_ieee:{ *:[f32] } (fmaxnum_ieee:{ *:[f32] } (VOP3Mods:{ *:[f32] } f32:{ *:[f32] }:$src0, i32:{ *:[i32] }:$src0_mods), (VOP3Mods:{ *:[f32] } f32:{ *:[f32] }:$src1, i32:{ *:[i32] }:$src1_mods)), (VOP3Mods:{ *:[f32] } f32:{ *:[f32] }:$src2, i32:{ *:[i32] }:$src2_mods)))<<P:Predicate_fmaxnum_like_nnan>>  =>  (V_MED3_F32_e64:{ *:[f32] } ?:{ *:[i32] }:$src0_mods, ?:{ *:[f32] }:$src0, ?:{ *:[i32] }:$src1_mods, ?:{ *:[f32] }:$src1, ?:{ *:[i32] }:$src2_mods, ?:{ *:[f32] }:$src2, 0:{ *:[i1] }, 0:{ *:[i32] })
        GIR_BuildMI, /*InsnID*/0, /*Opcode*/GIMT_Encode2(AMDGPU::V_MED3_F32_e64),
        GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/0, // DstI[vdst]
        GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(1), /*SubOperand*/1, // src0_mods
        GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(1), /*SubOperand*/0, // src0
        GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/1, // src1_mods
        GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/0, // src1
        GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(2), /*SubOperand*/1, // src2_mods
        GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(2), /*SubOperand*/0, // src2
        GIR_AddImm8, /*InsnID*/0, /*Imm*/0,
        GIR_AddImm8, /*InsnID*/0, /*Imm*/0,
        GIR_ConstrainSelectedInstOperands, /*InsnID*/0,
        GIR_EraseFromParent, /*InsnID*/0,
        // GIR_Coverage, 10003,
        GIR_Done,
      // Label 5152: @379316
      GIM_Try, /*On fail goto*//*Label 5153*/ GIMT_Encode4(379456), // Rule ID 10004 //
        GIM_CheckRegBankForClass, /*MI*/0, /*Op*/0, /*RC*/GIMT_Encode2(AMDGPU::VGPR_32RegClassID),
        GIM_RecordInsn, /*DefineMI*/1, /*MI*/0, /*OpIdx*/1, // MIs[1]
        GIM_CheckOpcode, /*MI*/1, GIMT_Encode2(TargetOpcode::G_FMINNUM_IEEE),
        GIM_CheckType, /*MI*/1, /*Op*/1, /*Type*/GILLT_s32,
        GIM_CheckType, /*MI*/1, /*Op*/2, /*Type*/GILLT_s32,
        GIM_RecordInsn, /*DefineMI*/2, /*MI*/0, /*OpIdx*/2, // MIs[2]
        GIM_CheckOpcode, /*MI*/2, GIMT_Encode2(TargetOpcode::G_FMINNUM_IEEE),
        GIM_CheckType, /*MI*/2, /*Op*/1, /*Type*/GILLT_s32,
        GIM_CheckType, /*MI*/2, /*Op*/2, /*Type*/GILLT_s32,
        GIM_RecordInsn, /*DefineMI*/3, /*MI*/2, /*OpIdx*/1, // MIs[3]
        GIM_CheckOpcode, /*MI*/3, GIMT_Encode2(TargetOpcode::G_FMAXNUM_IEEE),
        // MIs[3] VOP3Mods:src1:src1_mods
        GIM_CheckIsSameOperand, /*MI*/3, /*OpIdx*/1, /*OtherMI*/1, /*OtherOpIdx*/1,
        // MIs[3] VOP3Mods:src0:src0_mods
        GIM_CheckIsSameOperand, /*MI*/3, /*OpIdx*/2, /*OtherMI*/1, /*OtherOpIdx*/2,
        GIM_CheckCxxInsnPredicate, /*MI*/0, /*FnId*/GIMT_Encode2(GICXXPred_MI_Predicate_fmaxnum_like_nnan),
        GIM_CheckIsSafeToFold, /*InsnID*/1,
        GIM_CheckIsSafeToFold, /*InsnID*/2,
        GIM_CheckIsSafeToFold, /*InsnID*/3,
        GIM_CheckComplexPattern, /*MI*/1, /*Op*/1, /*Renderer*/GIMT_Encode2(0), GIMT_Encode2(GICP_gi_vop3mods),
        GIM_CheckComplexPattern, /*MI*/1, /*Op*/2, /*Renderer*/GIMT_Encode2(1), GIMT_Encode2(GICP_gi_vop3mods),
        GIM_CheckComplexPattern, /*MI*/2, /*Op*/2, /*Renderer*/GIMT_Encode2(2), GIMT_Encode2(GICP_gi_vop3mods),
        // (fmaxnum_ieee:{ *:[f32] } (fminnum_ieee:{ *:[f32] } (VOP3Mods:{ *:[f32] } f32:{ *:[f32] }:$src1, i32:{ *:[i32] }:$src1_mods), (VOP3Mods:{ *:[f32] } f32:{ *:[f32] }:$src0, i32:{ *:[i32] }:$src0_mods)), (fminnum_ieee:{ *:[f32] } (fmaxnum_ieee:{ *:[f32] } (VOP3Mods:{ *:[f32] } f32:{ *:[f32] }:$src1, i32:{ *:[i32] }:$src1_mods), (VOP3Mods:{ *:[f32] } f32:{ *:[f32] }:$src0, i32:{ *:[i32] }:$src0_mods)), (VOP3Mods:{ *:[f32] } f32:{ *:[f32] }:$src2, i32:{ *:[i32] }:$src2_mods)))<<P:Predicate_fmaxnum_like_nnan>>  =>  (V_MED3_F32_e64:{ *:[f32] } ?:{ *:[i32] }:$src0_mods, ?:{ *:[f32] }:$src0, ?:{ *:[i32] }:$src1_mods, ?:{ *:[f32] }:$src1, ?:{ *:[i32] }:$src2_mods, ?:{ *:[f32] }:$src2, 0:{ *:[i1] }, 0:{ *:[i32] })
        GIR_BuildMI, /*InsnID*/0, /*Opcode*/GIMT_Encode2(AMDGPU::V_MED3_F32_e64),
        GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/0, // DstI[vdst]
        GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(1), /*SubOperand*/1, // src0_mods
        GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(1), /*SubOperand*/0, // src0
        GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/1, // src1_mods
        GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/0, // src1
        GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(2), /*SubOperand*/1, // src2_mods
        GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(2), /*SubOperand*/0, // src2
        GIR_AddImm8, /*InsnID*/0, /*Imm*/0,
        GIR_AddImm8, /*InsnID*/0, /*Imm*/0,
        GIR_ConstrainSelectedInstOperands, /*InsnID*/0,
        GIR_EraseFromParent, /*InsnID*/0,
        // GIR_Coverage, 10004,
        GIR_Done,
      // Label 5153: @379456
      GIM_Try, /*On fail goto*//*Label 5154*/ GIMT_Encode4(379596), // Rule ID 10086 //
        GIM_CheckRegBankForClass, /*MI*/0, /*Op*/0, /*RC*/GIMT_Encode2(AMDGPU::VGPR_32RegClassID),
        GIM_RecordInsn, /*DefineMI*/1, /*MI*/0, /*OpIdx*/1, // MIs[1]
        GIM_CheckOpcode, /*MI*/1, GIMT_Encode2(TargetOpcode::G_FMINNUM_IEEE),
        GIM_CheckType, /*MI*/1, /*Op*/1, /*Type*/GILLT_s32,
        GIM_CheckType, /*MI*/1, /*Op*/2, /*Type*/GILLT_s32,
        GIM_RecordInsn, /*DefineMI*/2, /*MI*/1, /*OpIdx*/2, // MIs[2]
        GIM_CheckOpcode, /*MI*/2, GIMT_Encode2(TargetOpcode::G_FMAXNUM),
        GIM_CheckType, /*MI*/2, /*Op*/1, /*Type*/GILLT_s32,
        GIM_CheckType, /*MI*/2, /*Op*/2, /*Type*/GILLT_s32,
        GIM_RecordInsn, /*DefineMI*/3, /*MI*/0, /*OpIdx*/2, // MIs[3]
        GIM_CheckOpcode, /*MI*/3, GIMT_Encode2(TargetOpcode::G_FMINNUM),
        // MIs[3] VOP3Mods:src0:src0_mods
        GIM_CheckIsSameOperand, /*MI*/3, /*OpIdx*/1, /*OtherMI*/2, /*OtherOpIdx*/1,
        // MIs[3] VOP3Mods:src1:src1_mods
        GIM_CheckIsSameOperand, /*MI*/3, /*OpIdx*/2, /*OtherMI*/2, /*OtherOpIdx*/2,
        GIM_CheckCxxInsnPredicate, /*MI*/0, /*FnId*/GIMT_Encode2(GICXXPred_MI_Predicate_fmaxnum_like_nnan),
        GIM_CheckIsSafeToFold, /*InsnID*/1,
        GIM_CheckIsSafeToFold, /*InsnID*/2,
        GIM_CheckIsSafeToFold, /*InsnID*/3,
        GIM_CheckComplexPattern, /*MI*/1, /*Op*/1, /*Renderer*/GIMT_Encode2(0), GIMT_Encode2(GICP_gi_vop3mods),
        GIM_CheckComplexPattern, /*MI*/2, /*Op*/1, /*Renderer*/GIMT_Encode2(1), GIMT_Encode2(GICP_gi_vop3mods),
        GIM_CheckComplexPattern, /*MI*/2, /*Op*/2, /*Renderer*/GIMT_Encode2(2), GIMT_Encode2(GICP_gi_vop3mods),
        // (fmaxnum_ieee:{ *:[f32] } (fminnum_ieee:{ *:[f32] } (VOP3Mods:{ *:[f32] } f32:{ *:[f32] }:$src2, i32:{ *:[i32] }:$src2_mods), (fmaxnum:{ *:[f32] } (VOP3Mods:{ *:[f32] } f32:{ *:[f32] }:$src0, i32:{ *:[i32] }:$src0_mods), (VOP3Mods:{ *:[f32] } f32:{ *:[f32] }:$src1, i32:{ *:[i32] }:$src1_mods))), (fminnum:{ *:[f32] } (VOP3Mods:{ *:[f32] } f32:{ *:[f32] }:$src0, i32:{ *:[i32] }:$src0_mods), (VOP3Mods:{ *:[f32] } f32:{ *:[f32] }:$src1, i32:{ *:[i32] }:$src1_mods)))<<P:Predicate_fmaxnum_like_nnan>>  =>  (V_MED3_F32_e64:{ *:[f32] } ?:{ *:[i32] }:$src0_mods, ?:{ *:[f32] }:$src0, ?:{ *:[i32] }:$src1_mods, ?:{ *:[f32] }:$src1, ?:{ *:[i32] }:$src2_mods, ?:{ *:[f32] }:$src2, 0:{ *:[i1] }, 0:{ *:[i32] })
        GIR_BuildMI, /*InsnID*/0, /*Opcode*/GIMT_Encode2(AMDGPU::V_MED3_F32_e64),
        GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/0, // DstI[vdst]
        GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(1), /*SubOperand*/1, // src0_mods
        GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(1), /*SubOperand*/0, // src0
        GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(2), /*SubOperand*/1, // src1_mods
        GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(2), /*SubOperand*/0, // src1
        GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/1, // src2_mods
        GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/0, // src2
        GIR_AddImm8, /*InsnID*/0, /*Imm*/0,
        GIR_AddImm8, /*InsnID*/0, /*Imm*/0,
        GIR_ConstrainSelectedInstOperands, /*InsnID*/0,
        GIR_EraseFromParent, /*InsnID*/0,
        // GIR_Coverage, 10086,
        GIR_Done,
      // Label 5154: @379596
      GIM_Try, /*On fail goto*//*Label 5155*/ GIMT_Encode4(379736), // Rule ID 10087 //
        GIM_CheckRegBankForClass, /*MI*/0, /*Op*/0, /*RC*/GIMT_Encode2(AMDGPU::VGPR_32RegClassID),
        GIM_RecordInsn, /*DefineMI*/1, /*MI*/0, /*OpIdx*/1, // MIs[1]
        GIM_CheckOpcode, /*MI*/1, GIMT_Encode2(TargetOpcode::G_FMINNUM_IEEE),
        GIM_CheckType, /*MI*/1, /*Op*/1, /*Type*/GILLT_s32,
        GIM_CheckType, /*MI*/1, /*Op*/2, /*Type*/GILLT_s32,
        GIM_RecordInsn, /*DefineMI*/2, /*MI*/1, /*OpIdx*/2, // MIs[2]
        GIM_CheckOpcode, /*MI*/2, GIMT_Encode2(TargetOpcode::G_FMAXNUM),
        GIM_CheckType, /*MI*/2, /*Op*/1, /*Type*/GILLT_s32,
        GIM_CheckType, /*MI*/2, /*Op*/2, /*Type*/GILLT_s32,
        GIM_RecordInsn, /*DefineMI*/3, /*MI*/0, /*OpIdx*/2, // MIs[3]
        GIM_CheckOpcode, /*MI*/3, GIMT_Encode2(TargetOpcode::G_FMINNUM),
        // MIs[3] VOP3Mods:src1:src1_mods
        GIM_CheckIsSameOperand, /*MI*/3, /*OpIdx*/1, /*OtherMI*/2, /*OtherOpIdx*/2,
        // MIs[3] VOP3Mods:src0:src0_mods
        GIM_CheckIsSameOperand, /*MI*/3, /*OpIdx*/2, /*OtherMI*/2, /*OtherOpIdx*/1,
        GIM_CheckCxxInsnPredicate, /*MI*/0, /*FnId*/GIMT_Encode2(GICXXPred_MI_Predicate_fmaxnum_like_nnan),
        GIM_CheckIsSafeToFold, /*InsnID*/1,
        GIM_CheckIsSafeToFold, /*InsnID*/2,
        GIM_CheckIsSafeToFold, /*InsnID*/3,
        GIM_CheckComplexPattern, /*MI*/1, /*Op*/1, /*Renderer*/GIMT_Encode2(0), GIMT_Encode2(GICP_gi_vop3mods),
        GIM_CheckComplexPattern, /*MI*/2, /*Op*/1, /*Renderer*/GIMT_Encode2(1), GIMT_Encode2(GICP_gi_vop3mods),
        GIM_CheckComplexPattern, /*MI*/2, /*Op*/2, /*Renderer*/GIMT_Encode2(2), GIMT_Encode2(GICP_gi_vop3mods),
        // (fmaxnum_ieee:{ *:[f32] } (fminnum_ieee:{ *:[f32] } (VOP3Mods:{ *:[f32] } f32:{ *:[f32] }:$src2, i32:{ *:[i32] }:$src2_mods), (fmaxnum:{ *:[f32] } (VOP3Mods:{ *:[f32] } f32:{ *:[f32] }:$src0, i32:{ *:[i32] }:$src0_mods), (VOP3Mods:{ *:[f32] } f32:{ *:[f32] }:$src1, i32:{ *:[i32] }:$src1_mods))), (fminnum:{ *:[f32] } (VOP3Mods:{ *:[f32] } f32:{ *:[f32] }:$src1, i32:{ *:[i32] }:$src1_mods), (VOP3Mods:{ *:[f32] } f32:{ *:[f32] }:$src0, i32:{ *:[i32] }:$src0_mods)))<<P:Predicate_fmaxnum_like_nnan>>  =>  (V_MED3_F32_e64:{ *:[f32] } ?:{ *:[i32] }:$src0_mods, ?:{ *:[f32] }:$src0, ?:{ *:[i32] }:$src1_mods, ?:{ *:[f32] }:$src1, ?:{ *:[i32] }:$src2_mods, ?:{ *:[f32] }:$src2, 0:{ *:[i1] }, 0:{ *:[i32] })
        GIR_BuildMI, /*InsnID*/0, /*Opcode*/GIMT_Encode2(AMDGPU::V_MED3_F32_e64),
        GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/0, // DstI[vdst]
        GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(1), /*SubOperand*/1, // src0_mods
        GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(1), /*SubOperand*/0, // src0
        GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(2), /*SubOperand*/1, // src1_mods
        GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(2), /*SubOperand*/0, // src1
        GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/1, // src2_mods
        GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/0, // src2
        GIR_AddImm8, /*InsnID*/0, /*Imm*/0,
        GIR_AddImm8, /*InsnID*/0, /*Imm*/0,
        GIR_ConstrainSelectedInstOperands, /*InsnID*/0,
        GIR_EraseFromParent, /*InsnID*/0,
        // GIR_Coverage, 10087,
        GIR_Done,
      // Label 5155: @379736
      GIM_Try, /*On fail goto*//*Label 5156*/ GIMT_Encode4(379876), // Rule ID 10088 //
        GIM_CheckRegBankForClass, /*MI*/0, /*Op*/0, /*RC*/GIMT_Encode2(AMDGPU::VGPR_32RegClassID),
        GIM_RecordInsn, /*DefineMI*/1, /*MI*/0, /*OpIdx*/1, // MIs[1]
        GIM_CheckOpcode, /*MI*/1, GIMT_Encode2(TargetOpcode::G_FMINNUM_IEEE),
        GIM_CheckType, /*MI*/1, /*Op*/1, /*Type*/GILLT_s32,
        GIM_CheckType, /*MI*/1, /*Op*/2, /*Type*/GILLT_s32,
        GIM_RecordInsn, /*DefineMI*/2, /*MI*/1, /*OpIdx*/2, // MIs[2]
        GIM_CheckOpcode, /*MI*/2, GIMT_Encode2(TargetOpcode::G_FMAXNUM),
        GIM_CheckType, /*MI*/2, /*Op*/1, /*Type*/GILLT_s32,
        GIM_CheckType, /*MI*/2, /*Op*/2, /*Type*/GILLT_s32,
        GIM_RecordInsn, /*DefineMI*/3, /*MI*/0, /*OpIdx*/2, // MIs[3]
        GIM_CheckOpcode, /*MI*/3, GIMT_Encode2(TargetOpcode::G_FMINNUM),
        // MIs[3] VOP3Mods:src0:src0_mods
        GIM_CheckIsSameOperand, /*MI*/3, /*OpIdx*/1, /*OtherMI*/2, /*OtherOpIdx*/2,
        // MIs[3] VOP3Mods:src1:src1_mods
        GIM_CheckIsSameOperand, /*MI*/3, /*OpIdx*/2, /*OtherMI*/2, /*OtherOpIdx*/1,
        GIM_CheckCxxInsnPredicate, /*MI*/0, /*FnId*/GIMT_Encode2(GICXXPred_MI_Predicate_fmaxnum_like_nnan),
        GIM_CheckIsSafeToFold, /*InsnID*/1,
        GIM_CheckIsSafeToFold, /*InsnID*/2,
        GIM_CheckIsSafeToFold, /*InsnID*/3,
        GIM_CheckComplexPattern, /*MI*/1, /*Op*/1, /*Renderer*/GIMT_Encode2(0), GIMT_Encode2(GICP_gi_vop3mods),
        GIM_CheckComplexPattern, /*MI*/2, /*Op*/1, /*Renderer*/GIMT_Encode2(1), GIMT_Encode2(GICP_gi_vop3mods),
        GIM_CheckComplexPattern, /*MI*/2, /*Op*/2, /*Renderer*/GIMT_Encode2(2), GIMT_Encode2(GICP_gi_vop3mods),
        // (fmaxnum_ieee:{ *:[f32] } (fminnum_ieee:{ *:[f32] } (VOP3Mods:{ *:[f32] } f32:{ *:[f32] }:$src2, i32:{ *:[i32] }:$src2_mods), (fmaxnum:{ *:[f32] } (VOP3Mods:{ *:[f32] } f32:{ *:[f32] }:$src1, i32:{ *:[i32] }:$src1_mods), (VOP3Mods:{ *:[f32] } f32:{ *:[f32] }:$src0, i32:{ *:[i32] }:$src0_mods))), (fminnum:{ *:[f32] } (VOP3Mods:{ *:[f32] } f32:{ *:[f32] }:$src0, i32:{ *:[i32] }:$src0_mods), (VOP3Mods:{ *:[f32] } f32:{ *:[f32] }:$src1, i32:{ *:[i32] }:$src1_mods)))<<P:Predicate_fmaxnum_like_nnan>>  =>  (V_MED3_F32_e64:{ *:[f32] } ?:{ *:[i32] }:$src0_mods, ?:{ *:[f32] }:$src0, ?:{ *:[i32] }:$src1_mods, ?:{ *:[f32] }:$src1, ?:{ *:[i32] }:$src2_mods, ?:{ *:[f32] }:$src2, 0:{ *:[i1] }, 0:{ *:[i32] })
        GIR_BuildMI, /*InsnID*/0, /*Opcode*/GIMT_Encode2(AMDGPU::V_MED3_F32_e64),
        GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/0, // DstI[vdst]
        GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(2), /*SubOperand*/1, // src0_mods
        GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(2), /*SubOperand*/0, // src0
        GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(1), /*SubOperand*/1, // src1_mods
        GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(1), /*SubOperand*/0, // src1
        GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/1, // src2_mods
        GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/0, // src2
        GIR_AddImm8, /*InsnID*/0, /*Imm*/0,
        GIR_AddImm8, /*InsnID*/0, /*Imm*/0,
        GIR_ConstrainSelectedInstOperands, /*InsnID*/0,
        GIR_EraseFromParent, /*InsnID*/0,
        // GIR_Coverage, 10088,
        GIR_Done,
      // Label 5156: @379876
      GIM_Try, /*On fail goto*//*Label 5157*/ GIMT_Encode4(380016), // Rule ID 10089 //
        GIM_CheckRegBankForClass, /*MI*/0, /*Op*/0, /*RC*/GIMT_Encode2(AMDGPU::VGPR_32RegClassID),
        GIM_RecordInsn, /*DefineMI*/1, /*MI*/0, /*OpIdx*/1, // MIs[1]
        GIM_CheckOpcode, /*MI*/1, GIMT_Encode2(TargetOpcode::G_FMINNUM_IEEE),
        GIM_CheckType, /*MI*/1, /*Op*/1, /*Type*/GILLT_s32,
        GIM_CheckType, /*MI*/1, /*Op*/2, /*Type*/GILLT_s32,
        GIM_RecordInsn, /*DefineMI*/2, /*MI*/1, /*OpIdx*/2, // MIs[2]
        GIM_CheckOpcode, /*MI*/2, GIMT_Encode2(TargetOpcode::G_FMAXNUM),
        GIM_CheckType, /*MI*/2, /*Op*/1, /*Type*/GILLT_s32,
        GIM_CheckType, /*MI*/2, /*Op*/2, /*Type*/GILLT_s32,
        GIM_RecordInsn, /*DefineMI*/3, /*MI*/0, /*OpIdx*/2, // MIs[3]
        GIM_CheckOpcode, /*MI*/3, GIMT_Encode2(TargetOpcode::G_FMINNUM),
        // MIs[3] VOP3Mods:src1:src1_mods
        GIM_CheckIsSameOperand, /*MI*/3, /*OpIdx*/1, /*OtherMI*/2, /*OtherOpIdx*/1,
        // MIs[3] VOP3Mods:src0:src0_mods
        GIM_CheckIsSameOperand, /*MI*/3, /*OpIdx*/2, /*OtherMI*/2, /*OtherOpIdx*/2,
        GIM_CheckCxxInsnPredicate, /*MI*/0, /*FnId*/GIMT_Encode2(GICXXPred_MI_Predicate_fmaxnum_like_nnan),
        GIM_CheckIsSafeToFold, /*InsnID*/1,
        GIM_CheckIsSafeToFold, /*InsnID*/2,
        GIM_CheckIsSafeToFold, /*InsnID*/3,
        GIM_CheckComplexPattern, /*MI*/1, /*Op*/1, /*Renderer*/GIMT_Encode2(0), GIMT_Encode2(GICP_gi_vop3mods),
        GIM_CheckComplexPattern, /*MI*/2, /*Op*/1, /*Renderer*/GIMT_Encode2(1), GIMT_Encode2(GICP_gi_vop3mods),
        GIM_CheckComplexPattern, /*MI*/2, /*Op*/2, /*Renderer*/GIMT_Encode2(2), GIMT_Encode2(GICP_gi_vop3mods),
        // (fmaxnum_ieee:{ *:[f32] } (fminnum_ieee:{ *:[f32] } (VOP3Mods:{ *:[f32] } f32:{ *:[f32] }:$src2, i32:{ *:[i32] }:$src2_mods), (fmaxnum:{ *:[f32] } (VOP3Mods:{ *:[f32] } f32:{ *:[f32] }:$src1, i32:{ *:[i32] }:$src1_mods), (VOP3Mods:{ *:[f32] } f32:{ *:[f32] }:$src0, i32:{ *:[i32] }:$src0_mods))), (fminnum:{ *:[f32] } (VOP3Mods:{ *:[f32] } f32:{ *:[f32] }:$src1, i32:{ *:[i32] }:$src1_mods), (VOP3Mods:{ *:[f32] } f32:{ *:[f32] }:$src0, i32:{ *:[i32] }:$src0_mods)))<<P:Predicate_fmaxnum_like_nnan>>  =>  (V_MED3_F32_e64:{ *:[f32] } ?:{ *:[i32] }:$src0_mods, ?:{ *:[f32] }:$src0, ?:{ *:[i32] }:$src1_mods, ?:{ *:[f32] }:$src1, ?:{ *:[i32] }:$src2_mods, ?:{ *:[f32] }:$src2, 0:{ *:[i1] }, 0:{ *:[i32] })
        GIR_BuildMI, /*InsnID*/0, /*Opcode*/GIMT_Encode2(AMDGPU::V_MED3_F32_e64),
        GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/0, // DstI[vdst]
        GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(2), /*SubOperand*/1, // src0_mods
        GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(2), /*SubOperand*/0, // src0
        GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(1), /*SubOperand*/1, // src1_mods
        GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(1), /*SubOperand*/0, // src1
        GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/1, // src2_mods
        GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/0, // src2
        GIR_AddImm8, /*InsnID*/0, /*Imm*/0,
        GIR_AddImm8, /*InsnID*/0, /*Imm*/0,
        GIR_ConstrainSelectedInstOperands, /*InsnID*/0,
        GIR_EraseFromParent, /*InsnID*/0,
        // GIR_Coverage, 10089,
        GIR_Done,
      // Label 5157: @380016
      GIM_Try, /*On fail goto*//*Label 5158*/ GIMT_Encode4(380156), // Rule ID 10026 //
        GIM_CheckRegBankForClass, /*MI*/0, /*Op*/0, /*RC*/GIMT_Encode2(AMDGPU::VGPR_32RegClassID),
        GIM_RecordInsn, /*DefineMI*/1, /*MI*/0, /*OpIdx*/1, // MIs[1]
        GIM_CheckOpcode, /*MI*/1, GIMT_Encode2(TargetOpcode::G_FMINNUM_IEEE),
        GIM_CheckType, /*MI*/1, /*Op*/1, /*Type*/GILLT_s32,
        GIM_CheckType, /*MI*/1, /*Op*/2, /*Type*/GILLT_s32,
        GIM_RecordInsn, /*DefineMI*/2, /*MI*/1, /*OpIdx*/2, // MIs[2]
        GIM_CheckOpcode, /*MI*/2, GIMT_Encode2(TargetOpcode::G_FMAXNUM),
        GIM_CheckType, /*MI*/2, /*Op*/1, /*Type*/GILLT_s32,
        GIM_CheckType, /*MI*/2, /*Op*/2, /*Type*/GILLT_s32,
        GIM_RecordInsn, /*DefineMI*/3, /*MI*/0, /*OpIdx*/2, // MIs[3]
        GIM_CheckOpcode, /*MI*/3, GIMT_Encode2(TargetOpcode::G_FMINNUM_IEEE),
        // MIs[3] VOP3Mods:src0:src0_mods
        GIM_CheckIsSameOperand, /*MI*/3, /*OpIdx*/1, /*OtherMI*/2, /*OtherOpIdx*/1,
        // MIs[3] VOP3Mods:src1:src1_mods
        GIM_CheckIsSameOperand, /*MI*/3, /*OpIdx*/2, /*OtherMI*/2, /*OtherOpIdx*/2,
        GIM_CheckCxxInsnPredicate, /*MI*/0, /*FnId*/GIMT_Encode2(GICXXPred_MI_Predicate_fmaxnum_like_nnan),
        GIM_CheckIsSafeToFold, /*InsnID*/1,
        GIM_CheckIsSafeToFold, /*InsnID*/2,
        GIM_CheckIsSafeToFold, /*InsnID*/3,
        GIM_CheckComplexPattern, /*MI*/1, /*Op*/1, /*Renderer*/GIMT_Encode2(0), GIMT_Encode2(GICP_gi_vop3mods),
        GIM_CheckComplexPattern, /*MI*/2, /*Op*/1, /*Renderer*/GIMT_Encode2(1), GIMT_Encode2(GICP_gi_vop3mods),
        GIM_CheckComplexPattern, /*MI*/2, /*Op*/2, /*Renderer*/GIMT_Encode2(2), GIMT_Encode2(GICP_gi_vop3mods),
        // (fmaxnum_ieee:{ *:[f32] } (fminnum_ieee:{ *:[f32] } (VOP3Mods:{ *:[f32] } f32:{ *:[f32] }:$src2, i32:{ *:[i32] }:$src2_mods), (fmaxnum:{ *:[f32] } (VOP3Mods:{ *:[f32] } f32:{ *:[f32] }:$src0, i32:{ *:[i32] }:$src0_mods), (VOP3Mods:{ *:[f32] } f32:{ *:[f32] }:$src1, i32:{ *:[i32] }:$src1_mods))), (fminnum_ieee:{ *:[f32] } (VOP3Mods:{ *:[f32] } f32:{ *:[f32] }:$src0, i32:{ *:[i32] }:$src0_mods), (VOP3Mods:{ *:[f32] } f32:{ *:[f32] }:$src1, i32:{ *:[i32] }:$src1_mods)))<<P:Predicate_fmaxnum_like_nnan>>  =>  (V_MED3_F32_e64:{ *:[f32] } ?:{ *:[i32] }:$src0_mods, ?:{ *:[f32] }:$src0, ?:{ *:[i32] }:$src1_mods, ?:{ *:[f32] }:$src1, ?:{ *:[i32] }:$src2_mods, ?:{ *:[f32] }:$src2, 0:{ *:[i1] }, 0:{ *:[i32] })
        GIR_BuildMI, /*InsnID*/0, /*Opcode*/GIMT_Encode2(AMDGPU::V_MED3_F32_e64),
        GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/0, // DstI[vdst]
        GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(1), /*SubOperand*/1, // src0_mods
        GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(1), /*SubOperand*/0, // src0
        GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(2), /*SubOperand*/1, // src1_mods
        GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(2), /*SubOperand*/0, // src1
        GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/1, // src2_mods
        GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/0, // src2
        GIR_AddImm8, /*InsnID*/0, /*Imm*/0,
        GIR_AddImm8, /*InsnID*/0, /*Imm*/0,
        GIR_ConstrainSelectedInstOperands, /*InsnID*/0,
        GIR_EraseFromParent, /*InsnID*/0,
        // GIR_Coverage, 10026,
        GIR_Done,
      // Label 5158: @380156
      GIM_Try, /*On fail goto*//*Label 5159*/ GIMT_Encode4(380296), // Rule ID 10027 //
        GIM_CheckRegBankForClass, /*MI*/0, /*Op*/0, /*RC*/GIMT_Encode2(AMDGPU::VGPR_32RegClassID),
        GIM_RecordInsn, /*DefineMI*/1, /*MI*/0, /*OpIdx*/1, // MIs[1]
        GIM_CheckOpcode, /*MI*/1, GIMT_Encode2(TargetOpcode::G_FMINNUM_IEEE),
        GIM_CheckType, /*MI*/1, /*Op*/1, /*Type*/GILLT_s32,
        GIM_CheckType, /*MI*/1, /*Op*/2, /*Type*/GILLT_s32,
        GIM_RecordInsn, /*DefineMI*/2, /*MI*/1, /*OpIdx*/2, // MIs[2]
        GIM_CheckOpcode, /*MI*/2, GIMT_Encode2(TargetOpcode::G_FMAXNUM),
        GIM_CheckType, /*MI*/2, /*Op*/1, /*Type*/GILLT_s32,
        GIM_CheckType, /*MI*/2, /*Op*/2, /*Type*/GILLT_s32,
        GIM_RecordInsn, /*DefineMI*/3, /*MI*/0, /*OpIdx*/2, // MIs[3]
        GIM_CheckOpcode, /*MI*/3, GIMT_Encode2(TargetOpcode::G_FMINNUM_IEEE),
        // MIs[3] VOP3Mods:src1:src1_mods
        GIM_CheckIsSameOperand, /*MI*/3, /*OpIdx*/1, /*OtherMI*/2, /*OtherOpIdx*/2,
        // MIs[3] VOP3Mods:src0:src0_mods
        GIM_CheckIsSameOperand, /*MI*/3, /*OpIdx*/2, /*OtherMI*/2, /*OtherOpIdx*/1,
        GIM_CheckCxxInsnPredicate, /*MI*/0, /*FnId*/GIMT_Encode2(GICXXPred_MI_Predicate_fmaxnum_like_nnan),
        GIM_CheckIsSafeToFold, /*InsnID*/1,
        GIM_CheckIsSafeToFold, /*InsnID*/2,
        GIM_CheckIsSafeToFold, /*InsnID*/3,
        GIM_CheckComplexPattern, /*MI*/1, /*Op*/1, /*Renderer*/GIMT_Encode2(0), GIMT_Encode2(GICP_gi_vop3mods),
        GIM_CheckComplexPattern, /*MI*/2, /*Op*/1, /*Renderer*/GIMT_Encode2(1), GIMT_Encode2(GICP_gi_vop3mods),
        GIM_CheckComplexPattern, /*MI*/2, /*Op*/2, /*Renderer*/GIMT_Encode2(2), GIMT_Encode2(GICP_gi_vop3mods),
        // (fmaxnum_ieee:{ *:[f32] } (fminnum_ieee:{ *:[f32] } (VOP3Mods:{ *:[f32] } f32:{ *:[f32] }:$src2, i32:{ *:[i32] }:$src2_mods), (fmaxnum:{ *:[f32] } (VOP3Mods:{ *:[f32] } f32:{ *:[f32] }:$src0, i32:{ *:[i32] }:$src0_mods), (VOP3Mods:{ *:[f32] } f32:{ *:[f32] }:$src1, i32:{ *:[i32] }:$src1_mods))), (fminnum_ieee:{ *:[f32] } (VOP3Mods:{ *:[f32] } f32:{ *:[f32] }:$src1, i32:{ *:[i32] }:$src1_mods), (VOP3Mods:{ *:[f32] } f32:{ *:[f32] }:$src0, i32:{ *:[i32] }:$src0_mods)))<<P:Predicate_fmaxnum_like_nnan>>  =>  (V_MED3_F32_e64:{ *:[f32] } ?:{ *:[i32] }:$src0_mods, ?:{ *:[f32] }:$src0, ?:{ *:[i32] }:$src1_mods, ?:{ *:[f32] }:$src1, ?:{ *:[i32] }:$src2_mods, ?:{ *:[f32] }:$src2, 0:{ *:[i1] }, 0:{ *:[i32] })
        GIR_BuildMI, /*InsnID*/0, /*Opcode*/GIMT_Encode2(AMDGPU::V_MED3_F32_e64),
        GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/0, // DstI[vdst]
        GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(1), /*SubOperand*/1, // src0_mods
        GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(1), /*SubOperand*/0, // src0
        GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(2), /*SubOperand*/1, // src1_mods
        GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(2), /*SubOperand*/0, // src1
        GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/1, // src2_mods
        GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/0, // src2
        GIR_AddImm8, /*InsnID*/0, /*Imm*/0,
        GIR_AddImm8, /*InsnID*/0, /*Imm*/0,
        GIR_ConstrainSelectedInstOperands, /*InsnID*/0,
        GIR_EraseFromParent, /*InsnID*/0,
        // GIR_Coverage, 10027,
        GIR_Done,
      // Label 5159: @380296
      GIM_Try, /*On fail goto*//*Label 5160*/ GIMT_Encode4(380436), // Rule ID 10028 //
        GIM_CheckRegBankForClass, /*MI*/0, /*Op*/0, /*RC*/GIMT_Encode2(AMDGPU::VGPR_32RegClassID),
        GIM_RecordInsn, /*DefineMI*/1, /*MI*/0, /*OpIdx*/1, // MIs[1]
        GIM_CheckOpcode, /*MI*/1, GIMT_Encode2(TargetOpcode::G_FMINNUM_IEEE),
        GIM_CheckType, /*MI*/1, /*Op*/1, /*Type*/GILLT_s32,
        GIM_CheckType, /*MI*/1, /*Op*/2, /*Type*/GILLT_s32,
        GIM_RecordInsn, /*DefineMI*/2, /*MI*/1, /*OpIdx*/2, // MIs[2]
        GIM_CheckOpcode, /*MI*/2, GIMT_Encode2(TargetOpcode::G_FMAXNUM),
        GIM_CheckType, /*MI*/2, /*Op*/1, /*Type*/GILLT_s32,
        GIM_CheckType, /*MI*/2, /*Op*/2, /*Type*/GILLT_s32,
        GIM_RecordInsn, /*DefineMI*/3, /*MI*/0, /*OpIdx*/2, // MIs[3]
        GIM_CheckOpcode, /*MI*/3, GIMT_Encode2(TargetOpcode::G_FMINNUM_IEEE),
        // MIs[3] VOP3Mods:src0:src0_mods
        GIM_CheckIsSameOperand, /*MI*/3, /*OpIdx*/1, /*OtherMI*/2, /*OtherOpIdx*/2,
        // MIs[3] VOP3Mods:src1:src1_mods
        GIM_CheckIsSameOperand, /*MI*/3, /*OpIdx*/2, /*OtherMI*/2, /*OtherOpIdx*/1,
        GIM_CheckCxxInsnPredicate, /*MI*/0, /*FnId*/GIMT_Encode2(GICXXPred_MI_Predicate_fmaxnum_like_nnan),
        GIM_CheckIsSafeToFold, /*InsnID*/1,
        GIM_CheckIsSafeToFold, /*InsnID*/2,
        GIM_CheckIsSafeToFold, /*InsnID*/3,
        GIM_CheckComplexPattern, /*MI*/1, /*Op*/1, /*Renderer*/GIMT_Encode2(0), GIMT_Encode2(GICP_gi_vop3mods),
        GIM_CheckComplexPattern, /*MI*/2, /*Op*/1, /*Renderer*/GIMT_Encode2(1), GIMT_Encode2(GICP_gi_vop3mods),
        GIM_CheckComplexPattern, /*MI*/2, /*Op*/2, /*Renderer*/GIMT_Encode2(2), GIMT_Encode2(GICP_gi_vop3mods),
        // (fmaxnum_ieee:{ *:[f32] } (fminnum_ieee:{ *:[f32] } (VOP3Mods:{ *:[f32] } f32:{ *:[f32] }:$src2, i32:{ *:[i32] }:$src2_mods), (fmaxnum:{ *:[f32] } (VOP3Mods:{ *:[f32] } f32:{ *:[f32] }:$src1, i32:{ *:[i32] }:$src1_mods), (VOP3Mods:{ *:[f32] } f32:{ *:[f32] }:$src0, i32:{ *:[i32] }:$src0_mods))), (fminnum_ieee:{ *:[f32] } (VOP3Mods:{ *:[f32] } f32:{ *:[f32] }:$src0, i32:{ *:[i32] }:$src0_mods), (VOP3Mods:{ *:[f32] } f32:{ *:[f32] }:$src1, i32:{ *:[i32] }:$src1_mods)))<<P:Predicate_fmaxnum_like_nnan>>  =>  (V_MED3_F32_e64:{ *:[f32] } ?:{ *:[i32] }:$src0_mods, ?:{ *:[f32] }:$src0, ?:{ *:[i32] }:$src1_mods, ?:{ *:[f32] }:$src1, ?:{ *:[i32] }:$src2_mods, ?:{ *:[f32] }:$src2, 0:{ *:[i1] }, 0:{ *:[i32] })
        GIR_BuildMI, /*InsnID*/0, /*Opcode*/GIMT_Encode2(AMDGPU::V_MED3_F32_e64),
        GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/0, // DstI[vdst]
        GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(2), /*SubOperand*/1, // src0_mods
        GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(2), /*SubOperand*/0, // src0
        GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(1), /*SubOperand*/1, // src1_mods
        GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(1), /*SubOperand*/0, // src1
        GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/1, // src2_mods
        GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/0, // src2
        GIR_AddImm8, /*InsnID*/0, /*Imm*/0,
        GIR_AddImm8, /*InsnID*/0, /*Imm*/0,
        GIR_ConstrainSelectedInstOperands, /*InsnID*/0,
        GIR_EraseFromParent, /*InsnID*/0,
        // GIR_Coverage, 10028,
        GIR_Done,
      // Label 5160: @380436
      GIM_Try, /*On fail goto*//*Label 5161*/ GIMT_Encode4(380576), // Rule ID 10029 //
        GIM_CheckRegBankForClass, /*MI*/0, /*Op*/0, /*RC*/GIMT_Encode2(AMDGPU::VGPR_32RegClassID),
        GIM_RecordInsn, /*DefineMI*/1, /*MI*/0, /*OpIdx*/1, // MIs[1]
        GIM_CheckOpcode, /*MI*/1, GIMT_Encode2(TargetOpcode::G_FMINNUM_IEEE),
        GIM_CheckType, /*MI*/1, /*Op*/1, /*Type*/GILLT_s32,
        GIM_CheckType, /*MI*/1, /*Op*/2, /*Type*/GILLT_s32,
        GIM_RecordInsn, /*DefineMI*/2, /*MI*/1, /*OpIdx*/2, // MIs[2]
        GIM_CheckOpcode, /*MI*/2, GIMT_Encode2(TargetOpcode::G_FMAXNUM),
        GIM_CheckType, /*MI*/2, /*Op*/1, /*Type*/GILLT_s32,
        GIM_CheckType, /*MI*/2, /*Op*/2, /*Type*/GILLT_s32,
        GIM_RecordInsn, /*DefineMI*/3, /*MI*/0, /*OpIdx*/2, // MIs[3]
        GIM_CheckOpcode, /*MI*/3, GIMT_Encode2(TargetOpcode::G_FMINNUM_IEEE),
        // MIs[3] VOP3Mods:src1:src1_mods
        GIM_CheckIsSameOperand, /*MI*/3, /*OpIdx*/1, /*OtherMI*/2, /*OtherOpIdx*/1,
        // MIs[3] VOP3Mods:src0:src0_mods
        GIM_CheckIsSameOperand, /*MI*/3, /*OpIdx*/2, /*OtherMI*/2, /*OtherOpIdx*/2,
        GIM_CheckCxxInsnPredicate, /*MI*/0, /*FnId*/GIMT_Encode2(GICXXPred_MI_Predicate_fmaxnum_like_nnan),
        GIM_CheckIsSafeToFold, /*InsnID*/1,
        GIM_CheckIsSafeToFold, /*InsnID*/2,
        GIM_CheckIsSafeToFold, /*InsnID*/3,
        GIM_CheckComplexPattern, /*MI*/1, /*Op*/1, /*Renderer*/GIMT_Encode2(0), GIMT_Encode2(GICP_gi_vop3mods),
        GIM_CheckComplexPattern, /*MI*/2, /*Op*/1, /*Renderer*/GIMT_Encode2(1), GIMT_Encode2(GICP_gi_vop3mods),
        GIM_CheckComplexPattern, /*MI*/2, /*Op*/2, /*Renderer*/GIMT_Encode2(2), GIMT_Encode2(GICP_gi_vop3mods),
        // (fmaxnum_ieee:{ *:[f32] } (fminnum_ieee:{ *:[f32] } (VOP3Mods:{ *:[f32] } f32:{ *:[f32] }:$src2, i32:{ *:[i32] }:$src2_mods), (fmaxnum:{ *:[f32] } (VOP3Mods:{ *:[f32] } f32:{ *:[f32] }:$src1, i32:{ *:[i32] }:$src1_mods), (VOP3Mods:{ *:[f32] } f32:{ *:[f32] }:$src0, i32:{ *:[i32] }:$src0_mods))), (fminnum_ieee:{ *:[f32] } (VOP3Mods:{ *:[f32] } f32:{ *:[f32] }:$src1, i32:{ *:[i32] }:$src1_mods), (VOP3Mods:{ *:[f32] } f32:{ *:[f32] }:$src0, i32:{ *:[i32] }:$src0_mods)))<<P:Predicate_fmaxnum_like_nnan>>  =>  (V_MED3_F32_e64:{ *:[f32] } ?:{ *:[i32] }:$src0_mods, ?:{ *:[f32] }:$src0, ?:{ *:[i32] }:$src1_mods, ?:{ *:[f32] }:$src1, ?:{ *:[i32] }:$src2_mods, ?:{ *:[f32] }:$src2, 0:{ *:[i1] }, 0:{ *:[i32] })
        GIR_BuildMI, /*InsnID*/0, /*Opcode*/GIMT_Encode2(AMDGPU::V_MED3_F32_e64),
        GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/0, // DstI[vdst]
        GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(2), /*SubOperand*/1, // src0_mods
        GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(2), /*SubOperand*/0, // src0
        GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(1), /*SubOperand*/1, // src1_mods
        GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(1), /*SubOperand*/0, // src1
        GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/1, // src2_mods
        GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/0, // src2
        GIR_AddImm8, /*InsnID*/0, /*Imm*/0,
        GIR_AddImm8, /*InsnID*/0, /*Imm*/0,
        GIR_ConstrainSelectedInstOperands, /*InsnID*/0,
        GIR_EraseFromParent, /*InsnID*/0,
        // GIR_Coverage, 10029,
        GIR_Done,
      // Label 5161: @380576
      GIM_Try, /*On fail goto*//*Label 5162*/ GIMT_Encode4(380716), // Rule ID 10071 //
        GIM_CheckRegBankForClass, /*MI*/0, /*Op*/0, /*RC*/GIMT_Encode2(AMDGPU::VGPR_32RegClassID),
        GIM_RecordInsn, /*DefineMI*/1, /*MI*/0, /*OpIdx*/1, // MIs[1]
        GIM_CheckOpcode, /*MI*/1, GIMT_Encode2(TargetOpcode::G_FMINNUM_IEEE),
        GIM_CheckType, /*MI*/1, /*Op*/1, /*Type*/GILLT_s32,
        GIM_CheckType, /*MI*/1, /*Op*/2, /*Type*/GILLT_s32,
        GIM_RecordInsn, /*DefineMI*/2, /*MI*/1, /*OpIdx*/2, // MIs[2]
        GIM_CheckOpcode, /*MI*/2, GIMT_Encode2(TargetOpcode::G_FMAXNUM_IEEE),
        GIM_CheckType, /*MI*/2, /*Op*/1, /*Type*/GILLT_s32,
        GIM_CheckType, /*MI*/2, /*Op*/2, /*Type*/GILLT_s32,
        GIM_RecordInsn, /*DefineMI*/3, /*MI*/0, /*OpIdx*/2, // MIs[3]
        GIM_CheckOpcode, /*MI*/3, GIMT_Encode2(TargetOpcode::G_FMINNUM),
        // MIs[3] VOP3Mods:src0:src0_mods
        GIM_CheckIsSameOperand, /*MI*/3, /*OpIdx*/1, /*OtherMI*/2, /*OtherOpIdx*/1,
        // MIs[3] VOP3Mods:src1:src1_mods
        GIM_CheckIsSameOperand, /*MI*/3, /*OpIdx*/2, /*OtherMI*/2, /*OtherOpIdx*/2,
        GIM_CheckCxxInsnPredicate, /*MI*/0, /*FnId*/GIMT_Encode2(GICXXPred_MI_Predicate_fmaxnum_like_nnan),
        GIM_CheckIsSafeToFold, /*InsnID*/1,
        GIM_CheckIsSafeToFold, /*InsnID*/2,
        GIM_CheckIsSafeToFold, /*InsnID*/3,
        GIM_CheckComplexPattern, /*MI*/1, /*Op*/1, /*Renderer*/GIMT_Encode2(0), GIMT_Encode2(GICP_gi_vop3mods),
        GIM_CheckComplexPattern, /*MI*/2, /*Op*/1, /*Renderer*/GIMT_Encode2(1), GIMT_Encode2(GICP_gi_vop3mods),
        GIM_CheckComplexPattern, /*MI*/2, /*Op*/2, /*Renderer*/GIMT_Encode2(2), GIMT_Encode2(GICP_gi_vop3mods),
        // (fmaxnum_ieee:{ *:[f32] } (fminnum_ieee:{ *:[f32] } (VOP3Mods:{ *:[f32] } f32:{ *:[f32] }:$src2, i32:{ *:[i32] }:$src2_mods), (fmaxnum_ieee:{ *:[f32] } (VOP3Mods:{ *:[f32] } f32:{ *:[f32] }:$src0, i32:{ *:[i32] }:$src0_mods), (VOP3Mods:{ *:[f32] } f32:{ *:[f32] }:$src1, i32:{ *:[i32] }:$src1_mods))), (fminnum:{ *:[f32] } (VOP3Mods:{ *:[f32] } f32:{ *:[f32] }:$src0, i32:{ *:[i32] }:$src0_mods), (VOP3Mods:{ *:[f32] } f32:{ *:[f32] }:$src1, i32:{ *:[i32] }:$src1_mods)))<<P:Predicate_fmaxnum_like_nnan>>  =>  (V_MED3_F32_e64:{ *:[f32] } ?:{ *:[i32] }:$src0_mods, ?:{ *:[f32] }:$src0, ?:{ *:[i32] }:$src1_mods, ?:{ *:[f32] }:$src1, ?:{ *:[i32] }:$src2_mods, ?:{ *:[f32] }:$src2, 0:{ *:[i1] }, 0:{ *:[i32] })
        GIR_BuildMI, /*InsnID*/0, /*Opcode*/GIMT_Encode2(AMDGPU::V_MED3_F32_e64),
        GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/0, // DstI[vdst]
        GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(1), /*SubOperand*/1, // src0_mods
        GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(1), /*SubOperand*/0, // src0
        GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(2), /*SubOperand*/1, // src1_mods
        GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(2), /*SubOperand*/0, // src1
        GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/1, // src2_mods
        GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/0, // src2
        GIR_AddImm8, /*InsnID*/0, /*Imm*/0,
        GIR_AddImm8, /*InsnID*/0, /*Imm*/0,
        GIR_ConstrainSelectedInstOperands, /*InsnID*/0,
        GIR_EraseFromParent, /*InsnID*/0,
        // GIR_Coverage, 10071,
        GIR_Done,
      // Label 5162: @380716
      GIM_Try, /*On fail goto*//*Label 5163*/ GIMT_Encode4(380856), // Rule ID 10072 //
        GIM_CheckRegBankForClass, /*MI*/0, /*Op*/0, /*RC*/GIMT_Encode2(AMDGPU::VGPR_32RegClassID),
        GIM_RecordInsn, /*DefineMI*/1, /*MI*/0, /*OpIdx*/1, // MIs[1]
        GIM_CheckOpcode, /*MI*/1, GIMT_Encode2(TargetOpcode::G_FMINNUM_IEEE),
        GIM_CheckType, /*MI*/1, /*Op*/1, /*Type*/GILLT_s32,
        GIM_CheckType, /*MI*/1, /*Op*/2, /*Type*/GILLT_s32,
        GIM_RecordInsn, /*DefineMI*/2, /*MI*/1, /*OpIdx*/2, // MIs[2]
        GIM_CheckOpcode, /*MI*/2, GIMT_Encode2(TargetOpcode::G_FMAXNUM_IEEE),
        GIM_CheckType, /*MI*/2, /*Op*/1, /*Type*/GILLT_s32,
        GIM_CheckType, /*MI*/2, /*Op*/2, /*Type*/GILLT_s32,
        GIM_RecordInsn, /*DefineMI*/3, /*MI*/0, /*OpIdx*/2, // MIs[3]
        GIM_CheckOpcode, /*MI*/3, GIMT_Encode2(TargetOpcode::G_FMINNUM),
        // MIs[3] VOP3Mods:src1:src1_mods
        GIM_CheckIsSameOperand, /*MI*/3, /*OpIdx*/1, /*OtherMI*/2, /*OtherOpIdx*/2,
        // MIs[3] VOP3Mods:src0:src0_mods
        GIM_CheckIsSameOperand, /*MI*/3, /*OpIdx*/2, /*OtherMI*/2, /*OtherOpIdx*/1,
        GIM_CheckCxxInsnPredicate, /*MI*/0, /*FnId*/GIMT_Encode2(GICXXPred_MI_Predicate_fmaxnum_like_nnan),
        GIM_CheckIsSafeToFold, /*InsnID*/1,
        GIM_CheckIsSafeToFold, /*InsnID*/2,
        GIM_CheckIsSafeToFold, /*InsnID*/3,
        GIM_CheckComplexPattern, /*MI*/1, /*Op*/1, /*Renderer*/GIMT_Encode2(0), GIMT_Encode2(GICP_gi_vop3mods),
        GIM_CheckComplexPattern, /*MI*/2, /*Op*/1, /*Renderer*/GIMT_Encode2(1), GIMT_Encode2(GICP_gi_vop3mods),
        GIM_CheckComplexPattern, /*MI*/2, /*Op*/2, /*Renderer*/GIMT_Encode2(2), GIMT_Encode2(GICP_gi_vop3mods),
        // (fmaxnum_ieee:{ *:[f32] } (fminnum_ieee:{ *:[f32] } (VOP3Mods:{ *:[f32] } f32:{ *:[f32] }:$src2, i32:{ *:[i32] }:$src2_mods), (fmaxnum_ieee:{ *:[f32] } (VOP3Mods:{ *:[f32] } f32:{ *:[f32] }:$src0, i32:{ *:[i32] }:$src0_mods), (VOP3Mods:{ *:[f32] } f32:{ *:[f32] }:$src1, i32:{ *:[i32] }:$src1_mods))), (fminnum:{ *:[f32] } (VOP3Mods:{ *:[f32] } f32:{ *:[f32] }:$src1, i32:{ *:[i32] }:$src1_mods), (VOP3Mods:{ *:[f32] } f32:{ *:[f32] }:$src0, i32:{ *:[i32] }:$src0_mods)))<<P:Predicate_fmaxnum_like_nnan>>  =>  (V_MED3_F32_e64:{ *:[f32] } ?:{ *:[i32] }:$src0_mods, ?:{ *:[f32] }:$src0, ?:{ *:[i32] }:$src1_mods, ?:{ *:[f32] }:$src1, ?:{ *:[i32] }:$src2_mods, ?:{ *:[f32] }:$src2, 0:{ *:[i1] }, 0:{ *:[i32] })
        GIR_BuildMI, /*InsnID*/0, /*Opcode*/GIMT_Encode2(AMDGPU::V_MED3_F32_e64),
        GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/0, // DstI[vdst]
        GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(1), /*SubOperand*/1, // src0_mods
        GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(1), /*SubOperand*/0, // src0
        GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(2), /*SubOperand*/1, // src1_mods
        GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(2), /*SubOperand*/0, // src1
        GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/1, // src2_mods
        GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/0, // src2
        GIR_AddImm8, /*InsnID*/0, /*Imm*/0,
        GIR_AddImm8, /*InsnID*/0, /*Imm*/0,
        GIR_ConstrainSelectedInstOperands, /*InsnID*/0,
        GIR_EraseFromParent, /*InsnID*/0,
        // GIR_Coverage, 10072,
        GIR_Done,
      // Label 5163: @380856
      GIM_Try, /*On fail goto*//*Label 5164*/ GIMT_Encode4(380996), // Rule ID 10073 //
        GIM_CheckRegBankForClass, /*MI*/0, /*Op*/0, /*RC*/GIMT_Encode2(AMDGPU::VGPR_32RegClassID),
        GIM_RecordInsn, /*DefineMI*/1, /*MI*/0, /*OpIdx*/1, // MIs[1]
        GIM_CheckOpcode, /*MI*/1, GIMT_Encode2(TargetOpcode::G_FMINNUM_IEEE),
        GIM_CheckType, /*MI*/1, /*Op*/1, /*Type*/GILLT_s32,
        GIM_CheckType, /*MI*/1, /*Op*/2, /*Type*/GILLT_s32,
        GIM_RecordInsn, /*DefineMI*/2, /*MI*/1, /*OpIdx*/2, // MIs[2]
        GIM_CheckOpcode, /*MI*/2, GIMT_Encode2(TargetOpcode::G_FMAXNUM_IEEE),
        GIM_CheckType, /*MI*/2, /*Op*/1, /*Type*/GILLT_s32,
        GIM_CheckType, /*MI*/2, /*Op*/2, /*Type*/GILLT_s32,
        GIM_RecordInsn, /*DefineMI*/3, /*MI*/0, /*OpIdx*/2, // MIs[3]
        GIM_CheckOpcode, /*MI*/3, GIMT_Encode2(TargetOpcode::G_FMINNUM),
        // MIs[3] VOP3Mods:src0:src0_mods
        GIM_CheckIsSameOperand, /*MI*/3, /*OpIdx*/1, /*OtherMI*/2, /*OtherOpIdx*/2,
        // MIs[3] VOP3Mods:src1:src1_mods
        GIM_CheckIsSameOperand, /*MI*/3, /*OpIdx*/2, /*OtherMI*/2, /*OtherOpIdx*/1,
        GIM_CheckCxxInsnPredicate, /*MI*/0, /*FnId*/GIMT_Encode2(GICXXPred_MI_Predicate_fmaxnum_like_nnan),
        GIM_CheckIsSafeToFold, /*InsnID*/1,
        GIM_CheckIsSafeToFold, /*InsnID*/2,
        GIM_CheckIsSafeToFold, /*InsnID*/3,
        GIM_CheckComplexPattern, /*MI*/1, /*Op*/1, /*Renderer*/GIMT_Encode2(0), GIMT_Encode2(GICP_gi_vop3mods),
        GIM_CheckComplexPattern, /*MI*/2, /*Op*/1, /*Renderer*/GIMT_Encode2(1), GIMT_Encode2(GICP_gi_vop3mods),
        GIM_CheckComplexPattern, /*MI*/2, /*Op*/2, /*Renderer*/GIMT_Encode2(2), GIMT_Encode2(GICP_gi_vop3mods),
        // (fmaxnum_ieee:{ *:[f32] } (fminnum_ieee:{ *:[f32] } (VOP3Mods:{ *:[f32] } f32:{ *:[f32] }:$src2, i32:{ *:[i32] }:$src2_mods), (fmaxnum_ieee:{ *:[f32] } (VOP3Mods:{ *:[f32] } f32:{ *:[f32] }:$src1, i32:{ *:[i32] }:$src1_mods), (VOP3Mods:{ *:[f32] } f32:{ *:[f32] }:$src0, i32:{ *:[i32] }:$src0_mods))), (fminnum:{ *:[f32] } (VOP3Mods:{ *:[f32] } f32:{ *:[f32] }:$src0, i32:{ *:[i32] }:$src0_mods), (VOP3Mods:{ *:[f32] } f32:{ *:[f32] }:$src1, i32:{ *:[i32] }:$src1_mods)))<<P:Predicate_fmaxnum_like_nnan>>  =>  (V_MED3_F32_e64:{ *:[f32] } ?:{ *:[i32] }:$src0_mods, ?:{ *:[f32] }:$src0, ?:{ *:[i32] }:$src1_mods, ?:{ *:[f32] }:$src1, ?:{ *:[i32] }:$src2_mods, ?:{ *:[f32] }:$src2, 0:{ *:[i1] }, 0:{ *:[i32] })
        GIR_BuildMI, /*InsnID*/0, /*Opcode*/GIMT_Encode2(AMDGPU::V_MED3_F32_e64),
        GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/0, // DstI[vdst]
        GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(2), /*SubOperand*/1, // src0_mods
        GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(2), /*SubOperand*/0, // src0
        GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(1), /*SubOperand*/1, // src1_mods
        GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(1), /*SubOperand*/0, // src1
        GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/1, // src2_mods
        GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/0, // src2
        GIR_AddImm8, /*InsnID*/0, /*Imm*/0,
        GIR_AddImm8, /*InsnID*/0, /*Imm*/0,
        GIR_ConstrainSelectedInstOperands, /*InsnID*/0,
        GIR_EraseFromParent, /*InsnID*/0,
        // GIR_Coverage, 10073,
        GIR_Done,
      // Label 5164: @380996
      GIM_Try, /*On fail goto*//*Label 5165*/ GIMT_Encode4(381136), // Rule ID 10074 //
        GIM_CheckRegBankForClass, /*MI*/0, /*Op*/0, /*RC*/GIMT_Encode2(AMDGPU::VGPR_32RegClassID),
        GIM_RecordInsn, /*DefineMI*/1, /*MI*/0, /*OpIdx*/1, // MIs[1]
        GIM_CheckOpcode, /*MI*/1, GIMT_Encode2(TargetOpcode::G_FMINNUM_IEEE),
        GIM_CheckType, /*MI*/1, /*Op*/1, /*Type*/GILLT_s32,
        GIM_CheckType, /*MI*/1, /*Op*/2, /*Type*/GILLT_s32,
        GIM_RecordInsn, /*DefineMI*/2, /*MI*/1, /*OpIdx*/2, // MIs[2]
        GIM_CheckOpcode, /*MI*/2, GIMT_Encode2(TargetOpcode::G_FMAXNUM_IEEE),
        GIM_CheckType, /*MI*/2, /*Op*/1, /*Type*/GILLT_s32,
        GIM_CheckType, /*MI*/2, /*Op*/2, /*Type*/GILLT_s32,
        GIM_RecordInsn, /*DefineMI*/3, /*MI*/0, /*OpIdx*/2, // MIs[3]
        GIM_CheckOpcode, /*MI*/3, GIMT_Encode2(TargetOpcode::G_FMINNUM),
        // MIs[3] VOP3Mods:src1:src1_mods
        GIM_CheckIsSameOperand, /*MI*/3, /*OpIdx*/1, /*OtherMI*/2, /*OtherOpIdx*/1,
        // MIs[3] VOP3Mods:src0:src0_mods
        GIM_CheckIsSameOperand, /*MI*/3, /*OpIdx*/2, /*OtherMI*/2, /*OtherOpIdx*/2,
        GIM_CheckCxxInsnPredicate, /*MI*/0, /*FnId*/GIMT_Encode2(GICXXPred_MI_Predicate_fmaxnum_like_nnan),
        GIM_CheckIsSafeToFold, /*InsnID*/1,
        GIM_CheckIsSafeToFold, /*InsnID*/2,
        GIM_CheckIsSafeToFold, /*InsnID*/3,
        GIM_CheckComplexPattern, /*MI*/1, /*Op*/1, /*Renderer*/GIMT_Encode2(0), GIMT_Encode2(GICP_gi_vop3mods),
        GIM_CheckComplexPattern, /*MI*/2, /*Op*/1, /*Renderer*/GIMT_Encode2(1), GIMT_Encode2(GICP_gi_vop3mods),
        GIM_CheckComplexPattern, /*MI*/2, /*Op*/2, /*Renderer*/GIMT_Encode2(2), GIMT_Encode2(GICP_gi_vop3mods),
        // (fmaxnum_ieee:{ *:[f32] } (fminnum_ieee:{ *:[f32] } (VOP3Mods:{ *:[f32] } f32:{ *:[f32] }:$src2, i32:{ *:[i32] }:$src2_mods), (fmaxnum_ieee:{ *:[f32] } (VOP3Mods:{ *:[f32] } f32:{ *:[f32] }:$src1, i32:{ *:[i32] }:$src1_mods), (VOP3Mods:{ *:[f32] } f32:{ *:[f32] }:$src0, i32:{ *:[i32] }:$src0_mods))), (fminnum:{ *:[f32] } (VOP3Mods:{ *:[f32] } f32:{ *:[f32] }:$src1, i32:{ *:[i32] }:$src1_mods), (VOP3Mods:{ *:[f32] } f32:{ *:[f32] }:$src0, i32:{ *:[i32] }:$src0_mods)))<<P:Predicate_fmaxnum_like_nnan>>  =>  (V_MED3_F32_e64:{ *:[f32] } ?:{ *:[i32] }:$src0_mods, ?:{ *:[f32] }:$src0, ?:{ *:[i32] }:$src1_mods, ?:{ *:[f32] }:$src1, ?:{ *:[i32] }:$src2_mods, ?:{ *:[f32] }:$src2, 0:{ *:[i1] }, 0:{ *:[i32] })
        GIR_BuildMI, /*InsnID*/0, /*Opcode*/GIMT_Encode2(AMDGPU::V_MED3_F32_e64),
        GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/0, // DstI[vdst]
        GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(2), /*SubOperand*/1, // src0_mods
        GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(2), /*SubOperand*/0, // src0
        GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(1), /*SubOperand*/1, // src1_mods
        GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(1), /*SubOperand*/0, // src1
        GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/1, // src2_mods
        GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/0, // src2
        GIR_AddImm8, /*InsnID*/0, /*Imm*/0,
        GIR_AddImm8, /*InsnID*/0, /*Imm*/0,
        GIR_ConstrainSelectedInstOperands, /*InsnID*/0,
        GIR_EraseFromParent, /*InsnID*/0,
        // GIR_Coverage, 10074,
        GIR_Done,
      // Label 5165: @381136
      GIM_Try, /*On fail goto*//*Label 5166*/ GIMT_Encode4(381276), // Rule ID 10011 //
        GIM_CheckRegBankForClass, /*MI*/0, /*Op*/0, /*RC*/GIMT_Encode2(AMDGPU::VGPR_32RegClassID),
        GIM_RecordInsn, /*DefineMI*/1, /*MI*/0, /*OpIdx*/1, // MIs[1]
        GIM_CheckOpcode, /*MI*/1, GIMT_Encode2(TargetOpcode::G_FMINNUM_IEEE),
        GIM_CheckType, /*MI*/1, /*Op*/1, /*Type*/GILLT_s32,
        GIM_CheckType, /*MI*/1, /*Op*/2, /*Type*/GILLT_s32,
        GIM_RecordInsn, /*DefineMI*/2, /*MI*/1, /*OpIdx*/2, // MIs[2]
        GIM_CheckOpcode, /*MI*/2, GIMT_Encode2(TargetOpcode::G_FMAXNUM_IEEE),
        GIM_CheckType, /*MI*/2, /*Op*/1, /*Type*/GILLT_s32,
        GIM_CheckType, /*MI*/2, /*Op*/2, /*Type*/GILLT_s32,
        GIM_RecordInsn, /*DefineMI*/3, /*MI*/0, /*OpIdx*/2, // MIs[3]
        GIM_CheckOpcode, /*MI*/3, GIMT_Encode2(TargetOpcode::G_FMINNUM_IEEE),
        // MIs[3] VOP3Mods:src0:src0_mods
        GIM_CheckIsSameOperand, /*MI*/3, /*OpIdx*/1, /*OtherMI*/2, /*OtherOpIdx*/1,
        // MIs[3] VOP3Mods:src1:src1_mods
        GIM_CheckIsSameOperand, /*MI*/3, /*OpIdx*/2, /*OtherMI*/2, /*OtherOpIdx*/2,
        GIM_CheckCxxInsnPredicate, /*MI*/0, /*FnId*/GIMT_Encode2(GICXXPred_MI_Predicate_fmaxnum_like_nnan),
        GIM_CheckIsSafeToFold, /*InsnID*/1,
        GIM_CheckIsSafeToFold, /*InsnID*/2,
        GIM_CheckIsSafeToFold, /*InsnID*/3,
        GIM_CheckComplexPattern, /*MI*/1, /*Op*/1, /*Renderer*/GIMT_Encode2(0), GIMT_Encode2(GICP_gi_vop3mods),
        GIM_CheckComplexPattern, /*MI*/2, /*Op*/1, /*Renderer*/GIMT_Encode2(1), GIMT_Encode2(GICP_gi_vop3mods),
        GIM_CheckComplexPattern, /*MI*/2, /*Op*/2, /*Renderer*/GIMT_Encode2(2), GIMT_Encode2(GICP_gi_vop3mods),
        // (fmaxnum_ieee:{ *:[f32] } (fminnum_ieee:{ *:[f32] } (VOP3Mods:{ *:[f32] } f32:{ *:[f32] }:$src2, i32:{ *:[i32] }:$src2_mods), (fmaxnum_ieee:{ *:[f32] } (VOP3Mods:{ *:[f32] } f32:{ *:[f32] }:$src0, i32:{ *:[i32] }:$src0_mods), (VOP3Mods:{ *:[f32] } f32:{ *:[f32] }:$src1, i32:{ *:[i32] }:$src1_mods))), (fminnum_ieee:{ *:[f32] } (VOP3Mods:{ *:[f32] } f32:{ *:[f32] }:$src0, i32:{ *:[i32] }:$src0_mods), (VOP3Mods:{ *:[f32] } f32:{ *:[f32] }:$src1, i32:{ *:[i32] }:$src1_mods)))<<P:Predicate_fmaxnum_like_nnan>>  =>  (V_MED3_F32_e64:{ *:[f32] } ?:{ *:[i32] }:$src0_mods, ?:{ *:[f32] }:$src0, ?:{ *:[i32] }:$src1_mods, ?:{ *:[f32] }:$src1, ?:{ *:[i32] }:$src2_mods, ?:{ *:[f32] }:$src2, 0:{ *:[i1] }, 0:{ *:[i32] })
        GIR_BuildMI, /*InsnID*/0, /*Opcode*/GIMT_Encode2(AMDGPU::V_MED3_F32_e64),
        GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/0, // DstI[vdst]
        GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(1), /*SubOperand*/1, // src0_mods
        GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(1), /*SubOperand*/0, // src0
        GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(2), /*SubOperand*/1, // src1_mods
        GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(2), /*SubOperand*/0, // src1
        GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/1, // src2_mods
        GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/0, // src2
        GIR_AddImm8, /*InsnID*/0, /*Imm*/0,
        GIR_AddImm8, /*InsnID*/0, /*Imm*/0,
        GIR_ConstrainSelectedInstOperands, /*InsnID*/0,
        GIR_EraseFromParent, /*InsnID*/0,
        // GIR_Coverage, 10011,
        GIR_Done,
      // Label 5166: @381276
      GIM_Try, /*On fail goto*//*Label 5167*/ GIMT_Encode4(381416), // Rule ID 10012 //
        GIM_CheckRegBankForClass, /*MI*/0, /*Op*/0, /*RC*/GIMT_Encode2(AMDGPU::VGPR_32RegClassID),
        GIM_RecordInsn, /*DefineMI*/1, /*MI*/0, /*OpIdx*/1, // MIs[1]
        GIM_CheckOpcode, /*MI*/1, GIMT_Encode2(TargetOpcode::G_FMINNUM_IEEE),
        GIM_CheckType, /*MI*/1, /*Op*/1, /*Type*/GILLT_s32,
        GIM_CheckType, /*MI*/1, /*Op*/2, /*Type*/GILLT_s32,
        GIM_RecordInsn, /*DefineMI*/2, /*MI*/1, /*OpIdx*/2, // MIs[2]
        GIM_CheckOpcode, /*MI*/2, GIMT_Encode2(TargetOpcode::G_FMAXNUM_IEEE),
        GIM_CheckType, /*MI*/2, /*Op*/1, /*Type*/GILLT_s32,
        GIM_CheckType, /*MI*/2, /*Op*/2, /*Type*/GILLT_s32,
        GIM_RecordInsn, /*DefineMI*/3, /*MI*/0, /*OpIdx*/2, // MIs[3]
        GIM_CheckOpcode, /*MI*/3, GIMT_Encode2(TargetOpcode::G_FMINNUM_IEEE),
        // MIs[3] VOP3Mods:src1:src1_mods
        GIM_CheckIsSameOperand, /*MI*/3, /*OpIdx*/1, /*OtherMI*/2, /*OtherOpIdx*/2,
        // MIs[3] VOP3Mods:src0:src0_mods
        GIM_CheckIsSameOperand, /*MI*/3, /*OpIdx*/2, /*OtherMI*/2, /*OtherOpIdx*/1,
        GIM_CheckCxxInsnPredicate, /*MI*/0, /*FnId*/GIMT_Encode2(GICXXPred_MI_Predicate_fmaxnum_like_nnan),
        GIM_CheckIsSafeToFold, /*InsnID*/1,
        GIM_CheckIsSafeToFold, /*InsnID*/2,
        GIM_CheckIsSafeToFold, /*InsnID*/3,
        GIM_CheckComplexPattern, /*MI*/1, /*Op*/1, /*Renderer*/GIMT_Encode2(0), GIMT_Encode2(GICP_gi_vop3mods),
        GIM_CheckComplexPattern, /*MI*/2, /*Op*/1, /*Renderer*/GIMT_Encode2(1), GIMT_Encode2(GICP_gi_vop3mods),
        GIM_CheckComplexPattern, /*MI*/2, /*Op*/2, /*Renderer*/GIMT_Encode2(2), GIMT_Encode2(GICP_gi_vop3mods),
        // (fmaxnum_ieee:{ *:[f32] } (fminnum_ieee:{ *:[f32] } (VOP3Mods:{ *:[f32] } f32:{ *:[f32] }:$src2, i32:{ *:[i32] }:$src2_mods), (fmaxnum_ieee:{ *:[f32] } (VOP3Mods:{ *:[f32] } f32:{ *:[f32] }:$src0, i32:{ *:[i32] }:$src0_mods), (VOP3Mods:{ *:[f32] } f32:{ *:[f32] }:$src1, i32:{ *:[i32] }:$src1_mods))), (fminnum_ieee:{ *:[f32] } (VOP3Mods:{ *:[f32] } f32:{ *:[f32] }:$src1, i32:{ *:[i32] }:$src1_mods), (VOP3Mods:{ *:[f32] } f32:{ *:[f32] }:$src0, i32:{ *:[i32] }:$src0_mods)))<<P:Predicate_fmaxnum_like_nnan>>  =>  (V_MED3_F32_e64:{ *:[f32] } ?:{ *:[i32] }:$src0_mods, ?:{ *:[f32] }:$src0, ?:{ *:[i32] }:$src1_mods, ?:{ *:[f32] }:$src1, ?:{ *:[i32] }:$src2_mods, ?:{ *:[f32] }:$src2, 0:{ *:[i1] }, 0:{ *:[i32] })
        GIR_BuildMI, /*InsnID*/0, /*Opcode*/GIMT_Encode2(AMDGPU::V_MED3_F32_e64),
        GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/0, // DstI[vdst]
        GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(1), /*SubOperand*/1, // src0_mods
        GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(1), /*SubOperand*/0, // src0
        GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(2), /*SubOperand*/1, // src1_mods
        GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(2), /*SubOperand*/0, // src1
        GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/1, // src2_mods
        GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/0, // src2
        GIR_AddImm8, /*InsnID*/0, /*Imm*/0,
        GIR_AddImm8, /*InsnID*/0, /*Imm*/0,
        GIR_ConstrainSelectedInstOperands, /*InsnID*/0,
        GIR_EraseFromParent, /*InsnID*/0,
        // GIR_Coverage, 10012,
        GIR_Done,
      // Label 5167: @381416
      GIM_Try, /*On fail goto*//*Label 5168*/ GIMT_Encode4(381556), // Rule ID 10013 //
        GIM_CheckRegBankForClass, /*MI*/0, /*Op*/0, /*RC*/GIMT_Encode2(AMDGPU::VGPR_32RegClassID),
        GIM_RecordInsn, /*DefineMI*/1, /*MI*/0, /*OpIdx*/1, // MIs[1]
        GIM_CheckOpcode, /*MI*/1, GIMT_Encode2(TargetOpcode::G_FMINNUM_IEEE),
        GIM_CheckType, /*MI*/1, /*Op*/1, /*Type*/GILLT_s32,
        GIM_CheckType, /*MI*/1, /*Op*/2, /*Type*/GILLT_s32,
        GIM_RecordInsn, /*DefineMI*/2, /*MI*/1, /*OpIdx*/2, // MIs[2]
        GIM_CheckOpcode, /*MI*/2, GIMT_Encode2(TargetOpcode::G_FMAXNUM_IEEE),
        GIM_CheckType, /*MI*/2, /*Op*/1, /*Type*/GILLT_s32,
        GIM_CheckType, /*MI*/2, /*Op*/2, /*Type*/GILLT_s32,
        GIM_RecordInsn, /*DefineMI*/3, /*MI*/0, /*OpIdx*/2, // MIs[3]
        GIM_CheckOpcode, /*MI*/3, GIMT_Encode2(TargetOpcode::G_FMINNUM_IEEE),
        // MIs[3] VOP3Mods:src0:src0_mods
        GIM_CheckIsSameOperand, /*MI*/3, /*OpIdx*/1, /*OtherMI*/2, /*OtherOpIdx*/2,
        // MIs[3] VOP3Mods:src1:src1_mods
        GIM_CheckIsSameOperand, /*MI*/3, /*OpIdx*/2, /*OtherMI*/2, /*OtherOpIdx*/1,
        GIM_CheckCxxInsnPredicate, /*MI*/0, /*FnId*/GIMT_Encode2(GICXXPred_MI_Predicate_fmaxnum_like_nnan),
        GIM_CheckIsSafeToFold, /*InsnID*/1,
        GIM_CheckIsSafeToFold, /*InsnID*/2,
        GIM_CheckIsSafeToFold, /*InsnID*/3,
        GIM_CheckComplexPattern, /*MI*/1, /*Op*/1, /*Renderer*/GIMT_Encode2(0), GIMT_Encode2(GICP_gi_vop3mods),
        GIM_CheckComplexPattern, /*MI*/2, /*Op*/1, /*Renderer*/GIMT_Encode2(1), GIMT_Encode2(GICP_gi_vop3mods),
        GIM_CheckComplexPattern, /*MI*/2, /*Op*/2, /*Renderer*/GIMT_Encode2(2), GIMT_Encode2(GICP_gi_vop3mods),
        // (fmaxnum_ieee:{ *:[f32] } (fminnum_ieee:{ *:[f32] } (VOP3Mods:{ *:[f32] } f32:{ *:[f32] }:$src2, i32:{ *:[i32] }:$src2_mods), (fmaxnum_ieee:{ *:[f32] } (VOP3Mods:{ *:[f32] } f32:{ *:[f32] }:$src1, i32:{ *:[i32] }:$src1_mods), (VOP3Mods:{ *:[f32] } f32:{ *:[f32] }:$src0, i32:{ *:[i32] }:$src0_mods))), (fminnum_ieee:{ *:[f32] } (VOP3Mods:{ *:[f32] } f32:{ *:[f32] }:$src0, i32:{ *:[i32] }:$src0_mods), (VOP3Mods:{ *:[f32] } f32:{ *:[f32] }:$src1, i32:{ *:[i32] }:$src1_mods)))<<P:Predicate_fmaxnum_like_nnan>>  =>  (V_MED3_F32_e64:{ *:[f32] } ?:{ *:[i32] }:$src0_mods, ?:{ *:[f32] }:$src0, ?:{ *:[i32] }:$src1_mods, ?:{ *:[f32] }:$src1, ?:{ *:[i32] }:$src2_mods, ?:{ *:[f32] }:$src2, 0:{ *:[i1] }, 0:{ *:[i32] })
        GIR_BuildMI, /*InsnID*/0, /*Opcode*/GIMT_Encode2(AMDGPU::V_MED3_F32_e64),
        GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/0, // DstI[vdst]
        GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(2), /*SubOperand*/1, // src0_mods
        GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(2), /*SubOperand*/0, // src0
        GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(1), /*SubOperand*/1, // src1_mods
        GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(1), /*SubOperand*/0, // src1
        GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/1, // src2_mods
        GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/0, // src2
        GIR_AddImm8, /*InsnID*/0, /*Imm*/0,
        GIR_AddImm8, /*InsnID*/0, /*Imm*/0,
        GIR_ConstrainSelectedInstOperands, /*InsnID*/0,
        GIR_EraseFromParent, /*InsnID*/0,
        // GIR_Coverage, 10013,
        GIR_Done,
      // Label 5168: @381556
      GIM_Try, /*On fail goto*//*Label 5169*/ GIMT_Encode4(381696), // Rule ID 10014 //
        GIM_CheckRegBankForClass, /*MI*/0, /*Op*/0, /*RC*/GIMT_Encode2(AMDGPU::VGPR_32RegClassID),
        GIM_RecordInsn, /*DefineMI*/1, /*MI*/0, /*OpIdx*/1, // MIs[1]
        GIM_CheckOpcode, /*MI*/1, GIMT_Encode2(TargetOpcode::G_FMINNUM_IEEE),
        GIM_CheckType, /*MI*/1, /*Op*/1, /*Type*/GILLT_s32,
        GIM_CheckType, /*MI*/1, /*Op*/2, /*Type*/GILLT_s32,
        GIM_RecordInsn, /*DefineMI*/2, /*MI*/1, /*OpIdx*/2, // MIs[2]
        GIM_CheckOpcode, /*MI*/2, GIMT_Encode2(TargetOpcode::G_FMAXNUM_IEEE),
        GIM_CheckType, /*MI*/2, /*Op*/1, /*Type*/GILLT_s32,
        GIM_CheckType, /*MI*/2, /*Op*/2, /*Type*/GILLT_s32,
        GIM_RecordInsn, /*DefineMI*/3, /*MI*/0, /*OpIdx*/2, // MIs[3]
        GIM_CheckOpcode, /*MI*/3, GIMT_Encode2(TargetOpcode::G_FMINNUM_IEEE),
        // MIs[3] VOP3Mods:src1:src1_mods
        GIM_CheckIsSameOperand, /*MI*/3, /*OpIdx*/1, /*OtherMI*/2, /*OtherOpIdx*/1,
        // MIs[3] VOP3Mods:src0:src0_mods
        GIM_CheckIsSameOperand, /*MI*/3, /*OpIdx*/2, /*OtherMI*/2, /*OtherOpIdx*/2,
        GIM_CheckCxxInsnPredicate, /*MI*/0, /*FnId*/GIMT_Encode2(GICXXPred_MI_Predicate_fmaxnum_like_nnan),
        GIM_CheckIsSafeToFold, /*InsnID*/1,
        GIM_CheckIsSafeToFold, /*InsnID*/2,
        GIM_CheckIsSafeToFold, /*InsnID*/3,
        GIM_CheckComplexPattern, /*MI*/1, /*Op*/1, /*Renderer*/GIMT_Encode2(0), GIMT_Encode2(GICP_gi_vop3mods),
        GIM_CheckComplexPattern, /*MI*/2, /*Op*/1, /*Renderer*/GIMT_Encode2(1), GIMT_Encode2(GICP_gi_vop3mods),
        GIM_CheckComplexPattern, /*MI*/2, /*Op*/2, /*Renderer*/GIMT_Encode2(2), GIMT_Encode2(GICP_gi_vop3mods),
        // (fmaxnum_ieee:{ *:[f32] } (fminnum_ieee:{ *:[f32] } (VOP3Mods:{ *:[f32] } f32:{ *:[f32] }:$src2, i32:{ *:[i32] }:$src2_mods), (fmaxnum_ieee:{ *:[f32] } (VOP3Mods:{ *:[f32] } f32:{ *:[f32] }:$src1, i32:{ *:[i32] }:$src1_mods), (VOP3Mods:{ *:[f32] } f32:{ *:[f32] }:$src0, i32:{ *:[i32] }:$src0_mods))), (fminnum_ieee:{ *:[f32] } (VOP3Mods:{ *:[f32] } f32:{ *:[f32] }:$src1, i32:{ *:[i32] }:$src1_mods), (VOP3Mods:{ *:[f32] } f32:{ *:[f32] }:$src0, i32:{ *:[i32] }:$src0_mods)))<<P:Predicate_fmaxnum_like_nnan>>  =>  (V_MED3_F32_e64:{ *:[f32] } ?:{ *:[i32] }:$src0_mods, ?:{ *:[f32] }:$src0, ?:{ *:[i32] }:$src1_mods, ?:{ *:[f32] }:$src1, ?:{ *:[i32] }:$src2_mods, ?:{ *:[f32] }:$src2, 0:{ *:[i1] }, 0:{ *:[i32] })
        GIR_BuildMI, /*InsnID*/0, /*Opcode*/GIMT_Encode2(AMDGPU::V_MED3_F32_e64),
        GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/0, // DstI[vdst]
        GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(2), /*SubOperand*/1, // src0_mods
        GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(2), /*SubOperand*/0, // src0
        GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(1), /*SubOperand*/1, // src1_mods
        GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(1), /*SubOperand*/0, // src1
        GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/1, // src2_mods
        GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/0, // src2
        GIR_AddImm8, /*InsnID*/0, /*Imm*/0,
        GIR_AddImm8, /*InsnID*/0, /*Imm*/0,
        GIR_ConstrainSelectedInstOperands, /*InsnID*/0,
        GIR_EraseFromParent, /*InsnID*/0,
        // GIR_Coverage, 10014,
        GIR_Done,
      // Label 5169: @381696
      GIM_Try, /*On fail goto*//*Label 5170*/ GIMT_Encode4(381836), // Rule ID 10082 //
        GIM_CheckRegBankForClass, /*MI*/0, /*Op*/0, /*RC*/GIMT_Encode2(AMDGPU::VGPR_32RegClassID),
        GIM_RecordInsn, /*DefineMI*/1, /*MI*/0, /*OpIdx*/1, // MIs[1]
        GIM_CheckOpcode, /*MI*/1, GIMT_Encode2(TargetOpcode::G_FMINNUM_IEEE),
        GIM_CheckType, /*MI*/1, /*Op*/1, /*Type*/GILLT_s32,
        GIM_CheckType, /*MI*/1, /*Op*/2, /*Type*/GILLT_s32,
        GIM_RecordInsn, /*DefineMI*/2, /*MI*/1, /*OpIdx*/1, // MIs[2]
        GIM_CheckOpcode, /*MI*/2, GIMT_Encode2(TargetOpcode::G_FMAXNUM),
        GIM_CheckType, /*MI*/2, /*Op*/1, /*Type*/GILLT_s32,
        GIM_CheckType, /*MI*/2, /*Op*/2, /*Type*/GILLT_s32,
        GIM_RecordInsn, /*DefineMI*/3, /*MI*/0, /*OpIdx*/2, // MIs[3]
        GIM_CheckOpcode, /*MI*/3, GIMT_Encode2(TargetOpcode::G_FMINNUM),
        // MIs[3] VOP3Mods:src0:src0_mods
        GIM_CheckIsSameOperand, /*MI*/3, /*OpIdx*/1, /*OtherMI*/2, /*OtherOpIdx*/1,
        // MIs[3] VOP3Mods:src1:src1_mods
        GIM_CheckIsSameOperand, /*MI*/3, /*OpIdx*/2, /*OtherMI*/2, /*OtherOpIdx*/2,
        GIM_CheckCxxInsnPredicate, /*MI*/0, /*FnId*/GIMT_Encode2(GICXXPred_MI_Predicate_fmaxnum_like_nnan),
        GIM_CheckIsSafeToFold, /*InsnID*/1,
        GIM_CheckIsSafeToFold, /*InsnID*/2,
        GIM_CheckIsSafeToFold, /*InsnID*/3,
        GIM_CheckComplexPattern, /*MI*/1, /*Op*/2, /*Renderer*/GIMT_Encode2(2), GIMT_Encode2(GICP_gi_vop3mods),
        GIM_CheckComplexPattern, /*MI*/2, /*Op*/1, /*Renderer*/GIMT_Encode2(0), GIMT_Encode2(GICP_gi_vop3mods),
        GIM_CheckComplexPattern, /*MI*/2, /*Op*/2, /*Renderer*/GIMT_Encode2(1), GIMT_Encode2(GICP_gi_vop3mods),
        // (fmaxnum_ieee:{ *:[f32] } (fminnum_ieee:{ *:[f32] } (fmaxnum:{ *:[f32] } (VOP3Mods:{ *:[f32] } f32:{ *:[f32] }:$src0, i32:{ *:[i32] }:$src0_mods), (VOP3Mods:{ *:[f32] } f32:{ *:[f32] }:$src1, i32:{ *:[i32] }:$src1_mods)), (VOP3Mods:{ *:[f32] } f32:{ *:[f32] }:$src2, i32:{ *:[i32] }:$src2_mods)), (fminnum:{ *:[f32] } (VOP3Mods:{ *:[f32] } f32:{ *:[f32] }:$src0, i32:{ *:[i32] }:$src0_mods), (VOP3Mods:{ *:[f32] } f32:{ *:[f32] }:$src1, i32:{ *:[i32] }:$src1_mods)))<<P:Predicate_fmaxnum_like_nnan>>  =>  (V_MED3_F32_e64:{ *:[f32] } ?:{ *:[i32] }:$src0_mods, ?:{ *:[f32] }:$src0, ?:{ *:[i32] }:$src1_mods, ?:{ *:[f32] }:$src1, ?:{ *:[i32] }:$src2_mods, ?:{ *:[f32] }:$src2, 0:{ *:[i1] }, 0:{ *:[i32] })
        GIR_BuildMI, /*InsnID*/0, /*Opcode*/GIMT_Encode2(AMDGPU::V_MED3_F32_e64),
        GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/0, // DstI[vdst]
        GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/1, // src0_mods
        GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/0, // src0
        GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(1), /*SubOperand*/1, // src1_mods
        GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(1), /*SubOperand*/0, // src1
        GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(2), /*SubOperand*/1, // src2_mods
        GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(2), /*SubOperand*/0, // src2
        GIR_AddImm8, /*InsnID*/0, /*Imm*/0,
        GIR_AddImm8, /*InsnID*/0, /*Imm*/0,
        GIR_ConstrainSelectedInstOperands, /*InsnID*/0,
        GIR_EraseFromParent, /*InsnID*/0,
        // GIR_Coverage, 10082,
        GIR_Done,
      // Label 5170: @381836
      GIM_Try, /*On fail goto*//*Label 5171*/ GIMT_Encode4(381976), // Rule ID 10083 //
        GIM_CheckRegBankForClass, /*MI*/0, /*Op*/0, /*RC*/GIMT_Encode2(AMDGPU::VGPR_32RegClassID),
        GIM_RecordInsn, /*DefineMI*/1, /*MI*/0, /*OpIdx*/1, // MIs[1]
        GIM_CheckOpcode, /*MI*/1, GIMT_Encode2(TargetOpcode::G_FMINNUM_IEEE),
        GIM_CheckType, /*MI*/1, /*Op*/1, /*Type*/GILLT_s32,
        GIM_CheckType, /*MI*/1, /*Op*/2, /*Type*/GILLT_s32,
        GIM_RecordInsn, /*DefineMI*/2, /*MI*/1, /*OpIdx*/1, // MIs[2]
        GIM_CheckOpcode, /*MI*/2, GIMT_Encode2(TargetOpcode::G_FMAXNUM),
        GIM_CheckType, /*MI*/2, /*Op*/1, /*Type*/GILLT_s32,
        GIM_CheckType, /*MI*/2, /*Op*/2, /*Type*/GILLT_s32,
        GIM_RecordInsn, /*DefineMI*/3, /*MI*/0, /*OpIdx*/2, // MIs[3]
        GIM_CheckOpcode, /*MI*/3, GIMT_Encode2(TargetOpcode::G_FMINNUM),
        // MIs[3] VOP3Mods:src1:src1_mods
        GIM_CheckIsSameOperand, /*MI*/3, /*OpIdx*/1, /*OtherMI*/2, /*OtherOpIdx*/2,
        // MIs[3] VOP3Mods:src0:src0_mods
        GIM_CheckIsSameOperand, /*MI*/3, /*OpIdx*/2, /*OtherMI*/2, /*OtherOpIdx*/1,
        GIM_CheckCxxInsnPredicate, /*MI*/0, /*FnId*/GIMT_Encode2(GICXXPred_MI_Predicate_fmaxnum_like_nnan),
        GIM_CheckIsSafeToFold, /*InsnID*/1,
        GIM_CheckIsSafeToFold, /*InsnID*/2,
        GIM_CheckIsSafeToFold, /*InsnID*/3,
        GIM_CheckComplexPattern, /*MI*/1, /*Op*/2, /*Renderer*/GIMT_Encode2(2), GIMT_Encode2(GICP_gi_vop3mods),
        GIM_CheckComplexPattern, /*MI*/2, /*Op*/1, /*Renderer*/GIMT_Encode2(0), GIMT_Encode2(GICP_gi_vop3mods),
        GIM_CheckComplexPattern, /*MI*/2, /*Op*/2, /*Renderer*/GIMT_Encode2(1), GIMT_Encode2(GICP_gi_vop3mods),
        // (fmaxnum_ieee:{ *:[f32] } (fminnum_ieee:{ *:[f32] } (fmaxnum:{ *:[f32] } (VOP3Mods:{ *:[f32] } f32:{ *:[f32] }:$src0, i32:{ *:[i32] }:$src0_mods), (VOP3Mods:{ *:[f32] } f32:{ *:[f32] }:$src1, i32:{ *:[i32] }:$src1_mods)), (VOP3Mods:{ *:[f32] } f32:{ *:[f32] }:$src2, i32:{ *:[i32] }:$src2_mods)), (fminnum:{ *:[f32] } (VOP3Mods:{ *:[f32] } f32:{ *:[f32] }:$src1, i32:{ *:[i32] }:$src1_mods), (VOP3Mods:{ *:[f32] } f32:{ *:[f32] }:$src0, i32:{ *:[i32] }:$src0_mods)))<<P:Predicate_fmaxnum_like_nnan>>  =>  (V_MED3_F32_e64:{ *:[f32] } ?:{ *:[i32] }:$src0_mods, ?:{ *:[f32] }:$src0, ?:{ *:[i32] }:$src1_mods, ?:{ *:[f32] }:$src1, ?:{ *:[i32] }:$src2_mods, ?:{ *:[f32] }:$src2, 0:{ *:[i1] }, 0:{ *:[i32] })
        GIR_BuildMI, /*InsnID*/0, /*Opcode*/GIMT_Encode2(AMDGPU::V_MED3_F32_e64),
        GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/0, // DstI[vdst]
        GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/1, // src0_mods
        GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/0, // src0
        GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(1), /*SubOperand*/1, // src1_mods
        GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(1), /*SubOperand*/0, // src1
        GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(2), /*SubOperand*/1, // src2_mods
        GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(2), /*SubOperand*/0, // src2
        GIR_AddImm8, /*InsnID*/0, /*Imm*/0,
        GIR_AddImm8, /*InsnID*/0, /*Imm*/0,
        GIR_ConstrainSelectedInstOperands, /*InsnID*/0,
        GIR_EraseFromParent, /*InsnID*/0,
        // GIR_Coverage, 10083,
        GIR_Done,
      // Label 5171: @381976
      GIM_Try, /*On fail goto*//*Label 5172*/ GIMT_Encode4(382116), // Rule ID 10084 //
        GIM_CheckRegBankForClass, /*MI*/0, /*Op*/0, /*RC*/GIMT_Encode2(AMDGPU::VGPR_32RegClassID),
        GIM_RecordInsn, /*DefineMI*/1, /*MI*/0, /*OpIdx*/1, // MIs[1]
        GIM_CheckOpcode, /*MI*/1, GIMT_Encode2(TargetOpcode::G_FMINNUM_IEEE),
        GIM_CheckType, /*MI*/1, /*Op*/1, /*Type*/GILLT_s32,
        GIM_CheckType, /*MI*/1, /*Op*/2, /*Type*/GILLT_s32,
        GIM_RecordInsn, /*DefineMI*/2, /*MI*/1, /*OpIdx*/1, // MIs[2]
        GIM_CheckOpcode, /*MI*/2, GIMT_Encode2(TargetOpcode::G_FMAXNUM),
        GIM_CheckType, /*MI*/2, /*Op*/1, /*Type*/GILLT_s32,
        GIM_CheckType, /*MI*/2, /*Op*/2, /*Type*/GILLT_s32,
        GIM_RecordInsn, /*DefineMI*/3, /*MI*/0, /*OpIdx*/2, // MIs[3]
        GIM_CheckOpcode, /*MI*/3, GIMT_Encode2(TargetOpcode::G_FMINNUM),
        // MIs[3] VOP3Mods:src0:src0_mods
        GIM_CheckIsSameOperand, /*MI*/3, /*OpIdx*/1, /*OtherMI*/2, /*OtherOpIdx*/2,
        // MIs[3] VOP3Mods:src1:src1_mods
        GIM_CheckIsSameOperand, /*MI*/3, /*OpIdx*/2, /*OtherMI*/2, /*OtherOpIdx*/1,
        GIM_CheckCxxInsnPredicate, /*MI*/0, /*FnId*/GIMT_Encode2(GICXXPred_MI_Predicate_fmaxnum_like_nnan),
        GIM_CheckIsSafeToFold, /*InsnID*/1,
        GIM_CheckIsSafeToFold, /*InsnID*/2,
        GIM_CheckIsSafeToFold, /*InsnID*/3,
        GIM_CheckComplexPattern, /*MI*/1, /*Op*/2, /*Renderer*/GIMT_Encode2(2), GIMT_Encode2(GICP_gi_vop3mods),
        GIM_CheckComplexPattern, /*MI*/2, /*Op*/1, /*Renderer*/GIMT_Encode2(0), GIMT_Encode2(GICP_gi_vop3mods),
        GIM_CheckComplexPattern, /*MI*/2, /*Op*/2, /*Renderer*/GIMT_Encode2(1), GIMT_Encode2(GICP_gi_vop3mods),
        // (fmaxnum_ieee:{ *:[f32] } (fminnum_ieee:{ *:[f32] } (fmaxnum:{ *:[f32] } (VOP3Mods:{ *:[f32] } f32:{ *:[f32] }:$src1, i32:{ *:[i32] }:$src1_mods), (VOP3Mods:{ *:[f32] } f32:{ *:[f32] }:$src0, i32:{ *:[i32] }:$src0_mods)), (VOP3Mods:{ *:[f32] } f32:{ *:[f32] }:$src2, i32:{ *:[i32] }:$src2_mods)), (fminnum:{ *:[f32] } (VOP3Mods:{ *:[f32] } f32:{ *:[f32] }:$src0, i32:{ *:[i32] }:$src0_mods), (VOP3Mods:{ *:[f32] } f32:{ *:[f32] }:$src1, i32:{ *:[i32] }:$src1_mods)))<<P:Predicate_fmaxnum_like_nnan>>  =>  (V_MED3_F32_e64:{ *:[f32] } ?:{ *:[i32] }:$src0_mods, ?:{ *:[f32] }:$src0, ?:{ *:[i32] }:$src1_mods, ?:{ *:[f32] }:$src1, ?:{ *:[i32] }:$src2_mods, ?:{ *:[f32] }:$src2, 0:{ *:[i1] }, 0:{ *:[i32] })
        GIR_BuildMI, /*InsnID*/0, /*Opcode*/GIMT_Encode2(AMDGPU::V_MED3_F32_e64),
        GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/0, // DstI[vdst]
        GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(1), /*SubOperand*/1, // src0_mods
        GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(1), /*SubOperand*/0, // src0
        GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/1, // src1_mods
        GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/0, // src1
        GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(2), /*SubOperand*/1, // src2_mods
        GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(2), /*SubOperand*/0, // src2
        GIR_AddImm8, /*InsnID*/0, /*Imm*/0,
        GIR_AddImm8, /*InsnID*/0, /*Imm*/0,
        GIR_ConstrainSelectedInstOperands, /*InsnID*/0,
        GIR_EraseFromParent, /*InsnID*/0,
        // GIR_Coverage, 10084,
        GIR_Done,
      // Label 5172: @382116
      GIM_Try, /*On fail goto*//*Label 5173*/ GIMT_Encode4(382256), // Rule ID 10085 //
        GIM_CheckRegBankForClass, /*MI*/0, /*Op*/0, /*RC*/GIMT_Encode2(AMDGPU::VGPR_32RegClassID),
        GIM_RecordInsn, /*DefineMI*/1, /*MI*/0, /*OpIdx*/1, // MIs[1]
        GIM_CheckOpcode, /*MI*/1, GIMT_Encode2(TargetOpcode::G_FMINNUM_IEEE),
        GIM_CheckType, /*MI*/1, /*Op*/1, /*Type*/GILLT_s32,
        GIM_CheckType, /*MI*/1, /*Op*/2, /*Type*/GILLT_s32,
        GIM_RecordInsn, /*DefineMI*/2, /*MI*/1, /*OpIdx*/1, // MIs[2]
        GIM_CheckOpcode, /*MI*/2, GIMT_Encode2(TargetOpcode::G_FMAXNUM),
        GIM_CheckType, /*MI*/2, /*Op*/1, /*Type*/GILLT_s32,
        GIM_CheckType, /*MI*/2, /*Op*/2, /*Type*/GILLT_s32,
        GIM_RecordInsn, /*DefineMI*/3, /*MI*/0, /*OpIdx*/2, // MIs[3]
        GIM_CheckOpcode, /*MI*/3, GIMT_Encode2(TargetOpcode::G_FMINNUM),
        // MIs[3] VOP3Mods:src1:src1_mods
        GIM_CheckIsSameOperand, /*MI*/3, /*OpIdx*/1, /*OtherMI*/2, /*OtherOpIdx*/1,
        // MIs[3] VOP3Mods:src0:src0_mods
        GIM_CheckIsSameOperand, /*MI*/3, /*OpIdx*/2, /*OtherMI*/2, /*OtherOpIdx*/2,
        GIM_CheckCxxInsnPredicate, /*MI*/0, /*FnId*/GIMT_Encode2(GICXXPred_MI_Predicate_fmaxnum_like_nnan),
        GIM_CheckIsSafeToFold, /*InsnID*/1,
        GIM_CheckIsSafeToFold, /*InsnID*/2,
        GIM_CheckIsSafeToFold, /*InsnID*/3,
        GIM_CheckComplexPattern, /*MI*/1, /*Op*/2, /*Renderer*/GIMT_Encode2(2), GIMT_Encode2(GICP_gi_vop3mods),
        GIM_CheckComplexPattern, /*MI*/2, /*Op*/1, /*Renderer*/GIMT_Encode2(0), GIMT_Encode2(GICP_gi_vop3mods),
        GIM_CheckComplexPattern, /*MI*/2, /*Op*/2, /*Renderer*/GIMT_Encode2(1), GIMT_Encode2(GICP_gi_vop3mods),
        // (fmaxnum_ieee:{ *:[f32] } (fminnum_ieee:{ *:[f32] } (fmaxnum:{ *:[f32] } (VOP3Mods:{ *:[f32] } f32:{ *:[f32] }:$src1, i32:{ *:[i32] }:$src1_mods), (VOP3Mods:{ *:[f32] } f32:{ *:[f32] }:$src0, i32:{ *:[i32] }:$src0_mods)), (VOP3Mods:{ *:[f32] } f32:{ *:[f32] }:$src2, i32:{ *:[i32] }:$src2_mods)), (fminnum:{ *:[f32] } (VOP3Mods:{ *:[f32] } f32:{ *:[f32] }:$src1, i32:{ *:[i32] }:$src1_mods), (VOP3Mods:{ *:[f32] } f32:{ *:[f32] }:$src0, i32:{ *:[i32] }:$src0_mods)))<<P:Predicate_fmaxnum_like_nnan>>  =>  (V_MED3_F32_e64:{ *:[f32] } ?:{ *:[i32] }:$src0_mods, ?:{ *:[f32] }:$src0, ?:{ *:[i32] }:$src1_mods, ?:{ *:[f32] }:$src1, ?:{ *:[i32] }:$src2_mods, ?:{ *:[f32] }:$src2, 0:{ *:[i1] }, 0:{ *:[i32] })
        GIR_BuildMI, /*InsnID*/0, /*Opcode*/GIMT_Encode2(AMDGPU::V_MED3_F32_e64),
        GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/0, // DstI[vdst]
        GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(1), /*SubOperand*/1, // src0_mods
        GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(1), /*SubOperand*/0, // src0
        GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/1, // src1_mods
        GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/0, // src1
        GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(2), /*SubOperand*/1, // src2_mods
        GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(2), /*SubOperand*/0, // src2
        GIR_AddImm8, /*InsnID*/0, /*Imm*/0,
        GIR_AddImm8, /*InsnID*/0, /*Imm*/0,
        GIR_ConstrainSelectedInstOperands, /*InsnID*/0,
        GIR_EraseFromParent, /*InsnID*/0,
        // GIR_Coverage, 10085,
        GIR_Done,
      // Label 5173: @382256
      GIM_Try, /*On fail goto*//*Label 5174*/ GIMT_Encode4(382396), // Rule ID 10022 //
        GIM_CheckRegBankForClass, /*MI*/0, /*Op*/0, /*RC*/GIMT_Encode2(AMDGPU::VGPR_32RegClassID),
        GIM_RecordInsn, /*DefineMI*/1, /*MI*/0, /*OpIdx*/1, // MIs[1]
        GIM_CheckOpcode, /*MI*/1, GIMT_Encode2(TargetOpcode::G_FMINNUM_IEEE),
        GIM_CheckType, /*MI*/1, /*Op*/1, /*Type*/GILLT_s32,
        GIM_CheckType, /*MI*/1, /*Op*/2, /*Type*/GILLT_s32,
        GIM_RecordInsn, /*DefineMI*/2, /*MI*/1, /*OpIdx*/1, // MIs[2]
        GIM_CheckOpcode, /*MI*/2, GIMT_Encode2(TargetOpcode::G_FMAXNUM),
        GIM_CheckType, /*MI*/2, /*Op*/1, /*Type*/GILLT_s32,
        GIM_CheckType, /*MI*/2, /*Op*/2, /*Type*/GILLT_s32,
        GIM_RecordInsn, /*DefineMI*/3, /*MI*/0, /*OpIdx*/2, // MIs[3]
        GIM_CheckOpcode, /*MI*/3, GIMT_Encode2(TargetOpcode::G_FMINNUM_IEEE),
        // MIs[3] VOP3Mods:src0:src0_mods
        GIM_CheckIsSameOperand, /*MI*/3, /*OpIdx*/1, /*OtherMI*/2, /*OtherOpIdx*/1,
        // MIs[3] VOP3Mods:src1:src1_mods
        GIM_CheckIsSameOperand, /*MI*/3, /*OpIdx*/2, /*OtherMI*/2, /*OtherOpIdx*/2,
        GIM_CheckCxxInsnPredicate, /*MI*/0, /*FnId*/GIMT_Encode2(GICXXPred_MI_Predicate_fmaxnum_like_nnan),
        GIM_CheckIsSafeToFold, /*InsnID*/1,
        GIM_CheckIsSafeToFold, /*InsnID*/2,
        GIM_CheckIsSafeToFold, /*InsnID*/3,
        GIM_CheckComplexPattern, /*MI*/1, /*Op*/2, /*Renderer*/GIMT_Encode2(2), GIMT_Encode2(GICP_gi_vop3mods),
        GIM_CheckComplexPattern, /*MI*/2, /*Op*/1, /*Renderer*/GIMT_Encode2(0), GIMT_Encode2(GICP_gi_vop3mods),
        GIM_CheckComplexPattern, /*MI*/2, /*Op*/2, /*Renderer*/GIMT_Encode2(1), GIMT_Encode2(GICP_gi_vop3mods),
        // (fmaxnum_ieee:{ *:[f32] } (fminnum_ieee:{ *:[f32] } (fmaxnum:{ *:[f32] } (VOP3Mods:{ *:[f32] } f32:{ *:[f32] }:$src0, i32:{ *:[i32] }:$src0_mods), (VOP3Mods:{ *:[f32] } f32:{ *:[f32] }:$src1, i32:{ *:[i32] }:$src1_mods)), (VOP3Mods:{ *:[f32] } f32:{ *:[f32] }:$src2, i32:{ *:[i32] }:$src2_mods)), (fminnum_ieee:{ *:[f32] } (VOP3Mods:{ *:[f32] } f32:{ *:[f32] }:$src0, i32:{ *:[i32] }:$src0_mods), (VOP3Mods:{ *:[f32] } f32:{ *:[f32] }:$src1, i32:{ *:[i32] }:$src1_mods)))<<P:Predicate_fmaxnum_like_nnan>>  =>  (V_MED3_F32_e64:{ *:[f32] } ?:{ *:[i32] }:$src0_mods, ?:{ *:[f32] }:$src0, ?:{ *:[i32] }:$src1_mods, ?:{ *:[f32] }:$src1, ?:{ *:[i32] }:$src2_mods, ?:{ *:[f32] }:$src2, 0:{ *:[i1] }, 0:{ *:[i32] })
        GIR_BuildMI, /*InsnID*/0, /*Opcode*/GIMT_Encode2(AMDGPU::V_MED3_F32_e64),
        GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/0, // DstI[vdst]
        GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/1, // src0_mods
        GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/0, // src0
        GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(1), /*SubOperand*/1, // src1_mods
        GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(1), /*SubOperand*/0, // src1
        GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(2), /*SubOperand*/1, // src2_mods
        GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(2), /*SubOperand*/0, // src2
        GIR_AddImm8, /*InsnID*/0, /*Imm*/0,
        GIR_AddImm8, /*InsnID*/0, /*Imm*/0,
        GIR_ConstrainSelectedInstOperands, /*InsnID*/0,
        GIR_EraseFromParent, /*InsnID*/0,
        // GIR_Coverage, 10022,
        GIR_Done,
      // Label 5174: @382396
      GIM_Try, /*On fail goto*//*Label 5175*/ GIMT_Encode4(382536), // Rule ID 10023 //
        GIM_CheckRegBankForClass, /*MI*/0, /*Op*/0, /*RC*/GIMT_Encode2(AMDGPU::VGPR_32RegClassID),
        GIM_RecordInsn, /*DefineMI*/1, /*MI*/0, /*OpIdx*/1, // MIs[1]
        GIM_CheckOpcode, /*MI*/1, GIMT_Encode2(TargetOpcode::G_FMINNUM_IEEE),
        GIM_CheckType, /*MI*/1, /*Op*/1, /*Type*/GILLT_s32,
        GIM_CheckType, /*MI*/1, /*Op*/2, /*Type*/GILLT_s32,
        GIM_RecordInsn, /*DefineMI*/2, /*MI*/1, /*OpIdx*/1, // MIs[2]
        GIM_CheckOpcode, /*MI*/2, GIMT_Encode2(TargetOpcode::G_FMAXNUM),
        GIM_CheckType, /*MI*/2, /*Op*/1, /*Type*/GILLT_s32,
        GIM_CheckType, /*MI*/2, /*Op*/2, /*Type*/GILLT_s32,
        GIM_RecordInsn, /*DefineMI*/3, /*MI*/0, /*OpIdx*/2, // MIs[3]
        GIM_CheckOpcode, /*MI*/3, GIMT_Encode2(TargetOpcode::G_FMINNUM_IEEE),
        // MIs[3] VOP3Mods:src1:src1_mods
        GIM_CheckIsSameOperand, /*MI*/3, /*OpIdx*/1, /*OtherMI*/2, /*OtherOpIdx*/2,
        // MIs[3] VOP3Mods:src0:src0_mods
        GIM_CheckIsSameOperand, /*MI*/3, /*OpIdx*/2, /*OtherMI*/2, /*OtherOpIdx*/1,
        GIM_CheckCxxInsnPredicate, /*MI*/0, /*FnId*/GIMT_Encode2(GICXXPred_MI_Predicate_fmaxnum_like_nnan),
        GIM_CheckIsSafeToFold, /*InsnID*/1,
        GIM_CheckIsSafeToFold, /*InsnID*/2,
        GIM_CheckIsSafeToFold, /*InsnID*/3,
        GIM_CheckComplexPattern, /*MI*/1, /*Op*/2, /*Renderer*/GIMT_Encode2(2), GIMT_Encode2(GICP_gi_vop3mods),
        GIM_CheckComplexPattern, /*MI*/2, /*Op*/1, /*Renderer*/GIMT_Encode2(0), GIMT_Encode2(GICP_gi_vop3mods),
        GIM_CheckComplexPattern, /*MI*/2, /*Op*/2, /*Renderer*/GIMT_Encode2(1), GIMT_Encode2(GICP_gi_vop3mods),
        // (fmaxnum_ieee:{ *:[f32] } (fminnum_ieee:{ *:[f32] } (fmaxnum:{ *:[f32] } (VOP3Mods:{ *:[f32] } f32:{ *:[f32] }:$src0, i32:{ *:[i32] }:$src0_mods), (VOP3Mods:{ *:[f32] } f32:{ *:[f32] }:$src1, i32:{ *:[i32] }:$src1_mods)), (VOP3Mods:{ *:[f32] } f32:{ *:[f32] }:$src2, i32:{ *:[i32] }:$src2_mods)), (fminnum_ieee:{ *:[f32] } (VOP3Mods:{ *:[f32] } f32:{ *:[f32] }:$src1, i32:{ *:[i32] }:$src1_mods), (VOP3Mods:{ *:[f32] } f32:{ *:[f32] }:$src0, i32:{ *:[i32] }:$src0_mods)))<<P:Predicate_fmaxnum_like_nnan>>  =>  (V_MED3_F32_e64:{ *:[f32] } ?:{ *:[i32] }:$src0_mods, ?:{ *:[f32] }:$src0, ?:{ *:[i32] }:$src1_mods, ?:{ *:[f32] }:$src1, ?:{ *:[i32] }:$src2_mods, ?:{ *:[f32] }:$src2, 0:{ *:[i1] }, 0:{ *:[i32] })
        GIR_BuildMI, /*InsnID*/0, /*Opcode*/GIMT_Encode2(AMDGPU::V_MED3_F32_e64),
        GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/0, // DstI[vdst]
        GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/1, // src0_mods
        GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/0, // src0
        GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(1), /*SubOperand*/1, // src1_mods
        GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(1), /*SubOperand*/0, // src1
        GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(2), /*SubOperand*/1, // src2_mods
        GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(2), /*SubOperand*/0, // src2
        GIR_AddImm8, /*InsnID*/0, /*Imm*/0,
        GIR_AddImm8, /*InsnID*/0, /*Imm*/0,
        GIR_ConstrainSelectedInstOperands, /*InsnID*/0,
        GIR_EraseFromParent, /*InsnID*/0,
        // GIR_Coverage, 10023,
        GIR_Done,
      // Label 5175: @382536
      GIM_Try, /*On fail goto*//*Label 5176*/ GIMT_Encode4(382676), // Rule ID 10024 //
        GIM_CheckRegBankForClass, /*MI*/0, /*Op*/0, /*RC*/GIMT_Encode2(AMDGPU::VGPR_32RegClassID),
        GIM_RecordInsn, /*DefineMI*/1, /*MI*/0, /*OpIdx*/1, // MIs[1]
        GIM_CheckOpcode, /*MI*/1, GIMT_Encode2(TargetOpcode::G_FMINNUM_IEEE),
        GIM_CheckType, /*MI*/1, /*Op*/1, /*Type*/GILLT_s32,
        GIM_CheckType, /*MI*/1, /*Op*/2, /*Type*/GILLT_s32,
        GIM_RecordInsn, /*DefineMI*/2, /*MI*/1, /*OpIdx*/1, // MIs[2]
        GIM_CheckOpcode, /*MI*/2, GIMT_Encode2(TargetOpcode::G_FMAXNUM),
        GIM_CheckType, /*MI*/2, /*Op*/1, /*Type*/GILLT_s32,
        GIM_CheckType, /*MI*/2, /*Op*/2, /*Type*/GILLT_s32,
        GIM_RecordInsn, /*DefineMI*/3, /*MI*/0, /*OpIdx*/2, // MIs[3]
        GIM_CheckOpcode, /*MI*/3, GIMT_Encode2(TargetOpcode::G_FMINNUM_IEEE),
        // MIs[3] VOP3Mods:src0:src0_mods
        GIM_CheckIsSameOperand, /*MI*/3, /*OpIdx*/1, /*OtherMI*/2, /*OtherOpIdx*/2,
        // MIs[3] VOP3Mods:src1:src1_mods
        GIM_CheckIsSameOperand, /*MI*/3, /*OpIdx*/2, /*OtherMI*/2, /*OtherOpIdx*/1,
        GIM_CheckCxxInsnPredicate, /*MI*/0, /*FnId*/GIMT_Encode2(GICXXPred_MI_Predicate_fmaxnum_like_nnan),
        GIM_CheckIsSafeToFold, /*InsnID*/1,
        GIM_CheckIsSafeToFold, /*InsnID*/2,
        GIM_CheckIsSafeToFold, /*InsnID*/3,
        GIM_CheckComplexPattern, /*MI*/1, /*Op*/2, /*Renderer*/GIMT_Encode2(2), GIMT_Encode2(GICP_gi_vop3mods),
        GIM_CheckComplexPattern, /*MI*/2, /*Op*/1, /*Renderer*/GIMT_Encode2(0), GIMT_Encode2(GICP_gi_vop3mods),
        GIM_CheckComplexPattern, /*MI*/2, /*Op*/2, /*Renderer*/GIMT_Encode2(1), GIMT_Encode2(GICP_gi_vop3mods),
        // (fmaxnum_ieee:{ *:[f32] } (fminnum_ieee:{ *:[f32] } (fmaxnum:{ *:[f32] } (VOP3Mods:{ *:[f32] } f32:{ *:[f32] }:$src1, i32:{ *:[i32] }:$src1_mods), (VOP3Mods:{ *:[f32] } f32:{ *:[f32] }:$src0, i32:{ *:[i32] }:$src0_mods)), (VOP3Mods:{ *:[f32] } f32:{ *:[f32] }:$src2, i32:{ *:[i32] }:$src2_mods)), (fminnum_ieee:{ *:[f32] } (VOP3Mods:{ *:[f32] } f32:{ *:[f32] }:$src0, i32:{ *:[i32] }:$src0_mods), (VOP3Mods:{ *:[f32] } f32:{ *:[f32] }:$src1, i32:{ *:[i32] }:$src1_mods)))<<P:Predicate_fmaxnum_like_nnan>>  =>  (V_MED3_F32_e64:{ *:[f32] } ?:{ *:[i32] }:$src0_mods, ?:{ *:[f32] }:$src0, ?:{ *:[i32] }:$src1_mods, ?:{ *:[f32] }:$src1, ?:{ *:[i32] }:$src2_mods, ?:{ *:[f32] }:$src2, 0:{ *:[i1] }, 0:{ *:[i32] })
        GIR_BuildMI, /*InsnID*/0, /*Opcode*/GIMT_Encode2(AMDGPU::V_MED3_F32_e64),
        GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/0, // DstI[vdst]
        GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(1), /*SubOperand*/1, // src0_mods
        GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(1), /*SubOperand*/0, // src0
        GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/1, // src1_mods
        GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/0, // src1
        GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(2), /*SubOperand*/1, // src2_mods
        GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(2), /*SubOperand*/0, // src2
        GIR_AddImm8, /*InsnID*/0, /*Imm*/0,
        GIR_AddImm8, /*InsnID*/0, /*Imm*/0,
        GIR_ConstrainSelectedInstOperands, /*InsnID*/0,
        GIR_EraseFromParent, /*InsnID*/0,
        // GIR_Coverage, 10024,
        GIR_Done,
      // Label 5176: @382676
      GIM_Try, /*On fail goto*//*Label 5177*/ GIMT_Encode4(382816), // Rule ID 10025 //
        GIM_CheckRegBankForClass, /*MI*/0, /*Op*/0, /*RC*/GIMT_Encode2(AMDGPU::VGPR_32RegClassID),
        GIM_RecordInsn, /*DefineMI*/1, /*MI*/0, /*OpIdx*/1, // MIs[1]
        GIM_CheckOpcode, /*MI*/1, GIMT_Encode2(TargetOpcode::G_FMINNUM_IEEE),
        GIM_CheckType, /*MI*/1, /*Op*/1, /*Type*/GILLT_s32,
        GIM_CheckType, /*MI*/1, /*Op*/2, /*Type*/GILLT_s32,
        GIM_RecordInsn, /*DefineMI*/2, /*MI*/1, /*OpIdx*/1, // MIs[2]
        GIM_CheckOpcode, /*MI*/2, GIMT_Encode2(TargetOpcode::G_FMAXNUM),
        GIM_CheckType, /*MI*/2, /*Op*/1, /*Type*/GILLT_s32,
        GIM_CheckType, /*MI*/2, /*Op*/2, /*Type*/GILLT_s32,
        GIM_RecordInsn, /*DefineMI*/3, /*MI*/0, /*OpIdx*/2, // MIs[3]
        GIM_CheckOpcode, /*MI*/3, GIMT_Encode2(TargetOpcode::G_FMINNUM_IEEE),
        // MIs[3] VOP3Mods:src1:src1_mods
        GIM_CheckIsSameOperand, /*MI*/3, /*OpIdx*/1, /*OtherMI*/2, /*OtherOpIdx*/1,
        // MIs[3] VOP3Mods:src0:src0_mods
        GIM_CheckIsSameOperand, /*MI*/3, /*OpIdx*/2, /*OtherMI*/2, /*OtherOpIdx*/2,
        GIM_CheckCxxInsnPredicate, /*MI*/0, /*FnId*/GIMT_Encode2(GICXXPred_MI_Predicate_fmaxnum_like_nnan),
        GIM_CheckIsSafeToFold, /*InsnID*/1,
        GIM_CheckIsSafeToFold, /*InsnID*/2,
        GIM_CheckIsSafeToFold, /*InsnID*/3,
        GIM_CheckComplexPattern, /*MI*/1, /*Op*/2, /*Renderer*/GIMT_Encode2(2), GIMT_Encode2(GICP_gi_vop3mods),
        GIM_CheckComplexPattern, /*MI*/2, /*Op*/1, /*Renderer*/GIMT_Encode2(0), GIMT_Encode2(GICP_gi_vop3mods),
        GIM_CheckComplexPattern, /*MI*/2, /*Op*/2, /*Renderer*/GIMT_Encode2(1), GIMT_Encode2(GICP_gi_vop3mods),
        // (fmaxnum_ieee:{ *:[f32] } (fminnum_ieee:{ *:[f32] } (fmaxnum:{ *:[f32] } (VOP3Mods:{ *:[f32] } f32:{ *:[f32] }:$src1, i32:{ *:[i32] }:$src1_mods), (VOP3Mods:{ *:[f32] } f32:{ *:[f32] }:$src0, i32:{ *:[i32] }:$src0_mods)), (VOP3Mods:{ *:[f32] } f32:{ *:[f32] }:$src2, i32:{ *:[i32] }:$src2_mods)), (fminnum_ieee:{ *:[f32] } (VOP3Mods:{ *:[f32] } f32:{ *:[f32] }:$src1, i32:{ *:[i32] }:$src1_mods), (VOP3Mods:{ *:[f32] } f32:{ *:[f32] }:$src0, i32:{ *:[i32] }:$src0_mods)))<<P:Predicate_fmaxnum_like_nnan>>  =>  (V_MED3_F32_e64:{ *:[f32] } ?:{ *:[i32] }:$src0_mods, ?:{ *:[f32] }:$src0, ?:{ *:[i32] }:$src1_mods, ?:{ *:[f32] }:$src1, ?:{ *:[i32] }:$src2_mods, ?:{ *:[f32] }:$src2, 0:{ *:[i1] }, 0:{ *:[i32] })
        GIR_BuildMI, /*InsnID*/0, /*Opcode*/GIMT_Encode2(AMDGPU::V_MED3_F32_e64),
        GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/0, // DstI[vdst]
        GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(1), /*SubOperand*/1, // src0_mods
        GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(1), /*SubOperand*/0, // src0
        GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/1, // src1_mods
        GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/0, // src1
        GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(2), /*SubOperand*/1, // src2_mods
        GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(2), /*SubOperand*/0, // src2
        GIR_AddImm8, /*InsnID*/0, /*Imm*/0,
        GIR_AddImm8, /*InsnID*/0, /*Imm*/0,
        GIR_ConstrainSelectedInstOperands, /*InsnID*/0,
        GIR_EraseFromParent, /*InsnID*/0,
        // GIR_Coverage, 10025,
        GIR_Done,
      // Label 5177: @382816
      GIM_Try, /*On fail goto*//*Label 5178*/ GIMT_Encode4(382956), // Rule ID 10067 //
        GIM_CheckRegBankForClass, /*MI*/0, /*Op*/0, /*RC*/GIMT_Encode2(AMDGPU::VGPR_32RegClassID),
        GIM_RecordInsn, /*DefineMI*/1, /*MI*/0, /*OpIdx*/1, // MIs[1]
        GIM_CheckOpcode, /*MI*/1, GIMT_Encode2(TargetOpcode::G_FMINNUM_IEEE),
        GIM_CheckType, /*MI*/1, /*Op*/1, /*Type*/GILLT_s32,
        GIM_CheckType, /*MI*/1, /*Op*/2, /*Type*/GILLT_s32,
        GIM_RecordInsn, /*DefineMI*/2, /*MI*/1, /*OpIdx*/1, // MIs[2]
        GIM_CheckOpcode, /*MI*/2, GIMT_Encode2(TargetOpcode::G_FMAXNUM_IEEE),
        GIM_CheckType, /*MI*/2, /*Op*/1, /*Type*/GILLT_s32,
        GIM_CheckType, /*MI*/2, /*Op*/2, /*Type*/GILLT_s32,
        GIM_RecordInsn, /*DefineMI*/3, /*MI*/0, /*OpIdx*/2, // MIs[3]
        GIM_CheckOpcode, /*MI*/3, GIMT_Encode2(TargetOpcode::G_FMINNUM),
        // MIs[3] VOP3Mods:src0:src0_mods
        GIM_CheckIsSameOperand, /*MI*/3, /*OpIdx*/1, /*OtherMI*/2, /*OtherOpIdx*/1,
        // MIs[3] VOP3Mods:src1:src1_mods
        GIM_CheckIsSameOperand, /*MI*/3, /*OpIdx*/2, /*OtherMI*/2, /*OtherOpIdx*/2,
        GIM_CheckCxxInsnPredicate, /*MI*/0, /*FnId*/GIMT_Encode2(GICXXPred_MI_Predicate_fmaxnum_like_nnan),
        GIM_CheckIsSafeToFold, /*InsnID*/1,
        GIM_CheckIsSafeToFold, /*InsnID*/2,
        GIM_CheckIsSafeToFold, /*InsnID*/3,
        GIM_CheckComplexPattern, /*MI*/1, /*Op*/2, /*Renderer*/GIMT_Encode2(2), GIMT_Encode2(GICP_gi_vop3mods),
        GIM_CheckComplexPattern, /*MI*/2, /*Op*/1, /*Renderer*/GIMT_Encode2(0), GIMT_Encode2(GICP_gi_vop3mods),
        GIM_CheckComplexPattern, /*MI*/2, /*Op*/2, /*Renderer*/GIMT_Encode2(1), GIMT_Encode2(GICP_gi_vop3mods),
        // (fmaxnum_ieee:{ *:[f32] } (fminnum_ieee:{ *:[f32] } (fmaxnum_ieee:{ *:[f32] } (VOP3Mods:{ *:[f32] } f32:{ *:[f32] }:$src0, i32:{ *:[i32] }:$src0_mods), (VOP3Mods:{ *:[f32] } f32:{ *:[f32] }:$src1, i32:{ *:[i32] }:$src1_mods)), (VOP3Mods:{ *:[f32] } f32:{ *:[f32] }:$src2, i32:{ *:[i32] }:$src2_mods)), (fminnum:{ *:[f32] } (VOP3Mods:{ *:[f32] } f32:{ *:[f32] }:$src0, i32:{ *:[i32] }:$src0_mods), (VOP3Mods:{ *:[f32] } f32:{ *:[f32] }:$src1, i32:{ *:[i32] }:$src1_mods)))<<P:Predicate_fmaxnum_like_nnan>>  =>  (V_MED3_F32_e64:{ *:[f32] } ?:{ *:[i32] }:$src0_mods, ?:{ *:[f32] }:$src0, ?:{ *:[i32] }:$src1_mods, ?:{ *:[f32] }:$src1, ?:{ *:[i32] }:$src2_mods, ?:{ *:[f32] }:$src2, 0:{ *:[i1] }, 0:{ *:[i32] })
        GIR_BuildMI, /*InsnID*/0, /*Opcode*/GIMT_Encode2(AMDGPU::V_MED3_F32_e64),
        GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/0, // DstI[vdst]
        GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/1, // src0_mods
        GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/0, // src0
        GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(1), /*SubOperand*/1, // src1_mods
        GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(1), /*SubOperand*/0, // src1
        GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(2), /*SubOperand*/1, // src2_mods
        GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(2), /*SubOperand*/0, // src2
        GIR_AddImm8, /*InsnID*/0, /*Imm*/0,
        GIR_AddImm8, /*InsnID*/0, /*Imm*/0,
        GIR_ConstrainSelectedInstOperands, /*InsnID*/0,
        GIR_EraseFromParent, /*InsnID*/0,
        // GIR_Coverage, 10067,
        GIR_Done,
      // Label 5178: @382956
      GIM_Try, /*On fail goto*//*Label 5179*/ GIMT_Encode4(383096), // Rule ID 10068 //
        GIM_CheckRegBankForClass, /*MI*/0, /*Op*/0, /*RC*/GIMT_Encode2(AMDGPU::VGPR_32RegClassID),
        GIM_RecordInsn, /*DefineMI*/1, /*MI*/0, /*OpIdx*/1, // MIs[1]
        GIM_CheckOpcode, /*MI*/1, GIMT_Encode2(TargetOpcode::G_FMINNUM_IEEE),
        GIM_CheckType, /*MI*/1, /*Op*/1, /*Type*/GILLT_s32,
        GIM_CheckType, /*MI*/1, /*Op*/2, /*Type*/GILLT_s32,
        GIM_RecordInsn, /*DefineMI*/2, /*MI*/1, /*OpIdx*/1, // MIs[2]
        GIM_CheckOpcode, /*MI*/2, GIMT_Encode2(TargetOpcode::G_FMAXNUM_IEEE),
        GIM_CheckType, /*MI*/2, /*Op*/1, /*Type*/GILLT_s32,
        GIM_CheckType, /*MI*/2, /*Op*/2, /*Type*/GILLT_s32,
        GIM_RecordInsn, /*DefineMI*/3, /*MI*/0, /*OpIdx*/2, // MIs[3]
        GIM_CheckOpcode, /*MI*/3, GIMT_Encode2(TargetOpcode::G_FMINNUM),
        // MIs[3] VOP3Mods:src1:src1_mods
        GIM_CheckIsSameOperand, /*MI*/3, /*OpIdx*/1, /*OtherMI*/2, /*OtherOpIdx*/2,
        // MIs[3] VOP3Mods:src0:src0_mods
        GIM_CheckIsSameOperand, /*MI*/3, /*OpIdx*/2, /*OtherMI*/2, /*OtherOpIdx*/1,
        GIM_CheckCxxInsnPredicate, /*MI*/0, /*FnId*/GIMT_Encode2(GICXXPred_MI_Predicate_fmaxnum_like_nnan),
        GIM_CheckIsSafeToFold, /*InsnID*/1,
        GIM_CheckIsSafeToFold, /*InsnID*/2,
        GIM_CheckIsSafeToFold, /*InsnID*/3,
        GIM_CheckComplexPattern, /*MI*/1, /*Op*/2, /*Renderer*/GIMT_Encode2(2), GIMT_Encode2(GICP_gi_vop3mods),
        GIM_CheckComplexPattern, /*MI*/2, /*Op*/1, /*Renderer*/GIMT_Encode2(0), GIMT_Encode2(GICP_gi_vop3mods),
        GIM_CheckComplexPattern, /*MI*/2, /*Op*/2, /*Renderer*/GIMT_Encode2(1), GIMT_Encode2(GICP_gi_vop3mods),
        // (fmaxnum_ieee:{ *:[f32] } (fminnum_ieee:{ *:[f32] } (fmaxnum_ieee:{ *:[f32] } (VOP3Mods:{ *:[f32] } f32:{ *:[f32] }:$src0, i32:{ *:[i32] }:$src0_mods), (VOP3Mods:{ *:[f32] } f32:{ *:[f32] }:$src1, i32:{ *:[i32] }:$src1_mods)), (VOP3Mods:{ *:[f32] } f32:{ *:[f32] }:$src2, i32:{ *:[i32] }:$src2_mods)), (fminnum:{ *:[f32] } (VOP3Mods:{ *:[f32] } f32:{ *:[f32] }:$src1, i32:{ *:[i32] }:$src1_mods), (VOP3Mods:{ *:[f32] } f32:{ *:[f32] }:$src0, i32:{ *:[i32] }:$src0_mods)))<<P:Predicate_fmaxnum_like_nnan>>  =>  (V_MED3_F32_e64:{ *:[f32] } ?:{ *:[i32] }:$src0_mods, ?:{ *:[f32] }:$src0, ?:{ *:[i32] }:$src1_mods, ?:{ *:[f32] }:$src1, ?:{ *:[i32] }:$src2_mods, ?:{ *:[f32] }:$src2, 0:{ *:[i1] }, 0:{ *:[i32] })
        GIR_BuildMI, /*InsnID*/0, /*Opcode*/GIMT_Encode2(AMDGPU::V_MED3_F32_e64),
        GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/0, // DstI[vdst]
        GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/1, // src0_mods
        GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/0, // src0
        GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(1), /*SubOperand*/1, // src1_mods
        GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(1), /*SubOperand*/0, // src1
        GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(2), /*SubOperand*/1, // src2_mods
        GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(2), /*SubOperand*/0, // src2
        GIR_AddImm8, /*InsnID*/0, /*Imm*/0,
        GIR_AddImm8, /*InsnID*/0, /*Imm*/0,
        GIR_ConstrainSelectedInstOperands, /*InsnID*/0,
        GIR_EraseFromParent, /*InsnID*/0,
        // GIR_Coverage, 10068,
        GIR_Done,
      // Label 5179: @383096
      GIM_Try, /*On fail goto*//*Label 5180*/ GIMT_Encode4(383236), // Rule ID 10069 //
        GIM_CheckRegBankForClass, /*MI*/0, /*Op*/0, /*RC*/GIMT_Encode2(AMDGPU::VGPR_32RegClassID),
        GIM_RecordInsn, /*DefineMI*/1, /*MI*/0, /*OpIdx*/1, // MIs[1]
        GIM_CheckOpcode, /*MI*/1, GIMT_Encode2(TargetOpcode::G_FMINNUM_IEEE),
        GIM_CheckType, /*MI*/1, /*Op*/1, /*Type*/GILLT_s32,
        GIM_CheckType, /*MI*/1, /*Op*/2, /*Type*/GILLT_s32,
        GIM_RecordInsn, /*DefineMI*/2, /*MI*/1, /*OpIdx*/1, // MIs[2]
        GIM_CheckOpcode, /*MI*/2, GIMT_Encode2(TargetOpcode::G_FMAXNUM_IEEE),
        GIM_CheckType, /*MI*/2, /*Op*/1, /*Type*/GILLT_s32,
        GIM_CheckType, /*MI*/2, /*Op*/2, /*Type*/GILLT_s32,
        GIM_RecordInsn, /*DefineMI*/3, /*MI*/0, /*OpIdx*/2, // MIs[3]
        GIM_CheckOpcode, /*MI*/3, GIMT_Encode2(TargetOpcode::G_FMINNUM),
        // MIs[3] VOP3Mods:src0:src0_mods
        GIM_CheckIsSameOperand, /*MI*/3, /*OpIdx*/1, /*OtherMI*/2, /*OtherOpIdx*/2,
        // MIs[3] VOP3Mods:src1:src1_mods
        GIM_CheckIsSameOperand, /*MI*/3, /*OpIdx*/2, /*OtherMI*/2, /*OtherOpIdx*/1,
        GIM_CheckCxxInsnPredicate, /*MI*/0, /*FnId*/GIMT_Encode2(GICXXPred_MI_Predicate_fmaxnum_like_nnan),
        GIM_CheckIsSafeToFold, /*InsnID*/1,
        GIM_CheckIsSafeToFold, /*InsnID*/2,
        GIM_CheckIsSafeToFold, /*InsnID*/3,
        GIM_CheckComplexPattern, /*MI*/1, /*Op*/2, /*Renderer*/GIMT_Encode2(2), GIMT_Encode2(GICP_gi_vop3mods),
        GIM_CheckComplexPattern, /*MI*/2, /*Op*/1, /*Renderer*/GIMT_Encode2(0), GIMT_Encode2(GICP_gi_vop3mods),
        GIM_CheckComplexPattern, /*MI*/2, /*Op*/2, /*Renderer*/GIMT_Encode2(1), GIMT_Encode2(GICP_gi_vop3mods),
        // (fmaxnum_ieee:{ *:[f32] } (fminnum_ieee:{ *:[f32] } (fmaxnum_ieee:{ *:[f32] } (VOP3Mods:{ *:[f32] } f32:{ *:[f32] }:$src1, i32:{ *:[i32] }:$src1_mods), (VOP3Mods:{ *:[f32] } f32:{ *:[f32] }:$src0, i32:{ *:[i32] }:$src0_mods)), (VOP3Mods:{ *:[f32] } f32:{ *:[f32] }:$src2, i32:{ *:[i32] }:$src2_mods)), (fminnum:{ *:[f32] } (VOP3Mods:{ *:[f32] } f32:{ *:[f32] }:$src0, i32:{ *:[i32] }:$src0_mods), (VOP3Mods:{ *:[f32] } f32:{ *:[f32] }:$src1, i32:{ *:[i32] }:$src1_mods)))<<P:Predicate_fmaxnum_like_nnan>>  =>  (V_MED3_F32_e64:{ *:[f32] } ?:{ *:[i32] }:$src0_mods, ?:{ *:[f32] }:$src0, ?:{ *:[i32] }:$src1_mods, ?:{ *:[f32] }:$src1, ?:{ *:[i32] }:$src2_mods, ?:{ *:[f32] }:$src2, 0:{ *:[i1] }, 0:{ *:[i32] })
        GIR_BuildMI, /*InsnID*/0, /*Opcode*/GIMT_Encode2(AMDGPU::V_MED3_F32_e64),
        GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/0, // DstI[vdst]
        GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(1), /*SubOperand*/1, // src0_mods
        GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(1), /*SubOperand*/0, // src0
        GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/1, // src1_mods
        GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/0, // src1
        GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(2), /*SubOperand*/1, // src2_mods
        GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(2), /*SubOperand*/0, // src2
        GIR_AddImm8, /*InsnID*/0, /*Imm*/0,
        GIR_AddImm8, /*InsnID*/0, /*Imm*/0,
        GIR_ConstrainSelectedInstOperands, /*InsnID*/0,
        GIR_EraseFromParent, /*InsnID*/0,
        // GIR_Coverage, 10069,
        GIR_Done,
      // Label 5180: @383236
      GIM_Try, /*On fail goto*//*Label 5181*/ GIMT_Encode4(383376), // Rule ID 10070 //
        GIM_CheckRegBankForClass, /*MI*/0, /*Op*/0, /*RC*/GIMT_Encode2(AMDGPU::VGPR_32RegClassID),
        GIM_RecordInsn, /*DefineMI*/1, /*MI*/0, /*OpIdx*/1, // MIs[1]
        GIM_CheckOpcode, /*MI*/1, GIMT_Encode2(TargetOpcode::G_FMINNUM_IEEE),
        GIM_CheckType, /*MI*/1, /*Op*/1, /*Type*/GILLT_s32,
        GIM_CheckType, /*MI*/1, /*Op*/2, /*Type*/GILLT_s32,
        GIM_RecordInsn, /*DefineMI*/2, /*MI*/1, /*OpIdx*/1, // MIs[2]
        GIM_CheckOpcode, /*MI*/2, GIMT_Encode2(TargetOpcode::G_FMAXNUM_IEEE),
        GIM_CheckType, /*MI*/2, /*Op*/1, /*Type*/GILLT_s32,
        GIM_CheckType, /*MI*/2, /*Op*/2, /*Type*/GILLT_s32,
        GIM_RecordInsn, /*DefineMI*/3, /*MI*/0, /*OpIdx*/2, // MIs[3]
        GIM_CheckOpcode, /*MI*/3, GIMT_Encode2(TargetOpcode::G_FMINNUM),
        // MIs[3] VOP3Mods:src1:src1_mods
        GIM_CheckIsSameOperand, /*MI*/3, /*OpIdx*/1, /*OtherMI*/2, /*OtherOpIdx*/1,
        // MIs[3] VOP3Mods:src0:src0_mods
        GIM_CheckIsSameOperand, /*MI*/3, /*OpIdx*/2, /*OtherMI*/2, /*OtherOpIdx*/2,
        GIM_CheckCxxInsnPredicate, /*MI*/0, /*FnId*/GIMT_Encode2(GICXXPred_MI_Predicate_fmaxnum_like_nnan),
        GIM_CheckIsSafeToFold, /*InsnID*/1,
        GIM_CheckIsSafeToFold, /*InsnID*/2,
        GIM_CheckIsSafeToFold, /*InsnID*/3,
        GIM_CheckComplexPattern, /*MI*/1, /*Op*/2, /*Renderer*/GIMT_Encode2(2), GIMT_Encode2(GICP_gi_vop3mods),
        GIM_CheckComplexPattern, /*MI*/2, /*Op*/1, /*Renderer*/GIMT_Encode2(0), GIMT_Encode2(GICP_gi_vop3mods),
        GIM_CheckComplexPattern, /*MI*/2, /*Op*/2, /*Renderer*/GIMT_Encode2(1), GIMT_Encode2(GICP_gi_vop3mods),
        // (fmaxnum_ieee:{ *:[f32] } (fminnum_ieee:{ *:[f32] } (fmaxnum_ieee:{ *:[f32] } (VOP3Mods:{ *:[f32] } f32:{ *:[f32] }:$src1, i32:{ *:[i32] }:$src1_mods), (VOP3Mods:{ *:[f32] } f32:{ *:[f32] }:$src0, i32:{ *:[i32] }:$src0_mods)), (VOP3Mods:{ *:[f32] } f32:{ *:[f32] }:$src2, i32:{ *:[i32] }:$src2_mods)), (fminnum:{ *:[f32] } (VOP3Mods:{ *:[f32] } f32:{ *:[f32] }:$src1, i32:{ *:[i32] }:$src1_mods), (VOP3Mods:{ *:[f32] } f32:{ *:[f32] }:$src0, i32:{ *:[i32] }:$src0_mods)))<<P:Predicate_fmaxnum_like_nnan>>  =>  (V_MED3_F32_e64:{ *:[f32] } ?:{ *:[i32] }:$src0_mods, ?:{ *:[f32] }:$src0, ?:{ *:[i32] }:$src1_mods, ?:{ *:[f32] }:$src1, ?:{ *:[i32] }:$src2_mods, ?:{ *:[f32] }:$src2, 0:{ *:[i1] }, 0:{ *:[i32] })
        GIR_BuildMI, /*InsnID*/0, /*Opcode*/GIMT_Encode2(AMDGPU::V_MED3_F32_e64),
        GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/0, // DstI[vdst]
        GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(1), /*SubOperand*/1, // src0_mods
        GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(1), /*SubOperand*/0, // src0
        GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/1, // src1_mods
        GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/0, // src1
        GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(2), /*SubOperand*/1, // src2_mods
        GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(2), /*SubOperand*/0, // src2
        GIR_AddImm8, /*InsnID*/0, /*Imm*/0,
        GIR_AddImm8, /*InsnID*/0, /*Imm*/0,
        GIR_ConstrainSelectedInstOperands, /*InsnID*/0,
        GIR_EraseFromParent, /*InsnID*/0,
        // GIR_Coverage, 10070,
        GIR_Done,
      // Label 5181: @383376
      GIM_Try, /*On fail goto*//*Label 5182*/ GIMT_Encode4(383516), // Rule ID 10007 //
        GIM_CheckRegBankForClass, /*MI*/0, /*Op*/0, /*RC*/GIMT_Encode2(AMDGPU::VGPR_32RegClassID),
        GIM_RecordInsn, /*DefineMI*/1, /*MI*/0, /*OpIdx*/1, // MIs[1]
        GIM_CheckOpcode, /*MI*/1, GIMT_Encode2(TargetOpcode::G_FMINNUM_IEEE),
        GIM_CheckType, /*MI*/1, /*Op*/1, /*Type*/GILLT_s32,
        GIM_CheckType, /*MI*/1, /*Op*/2, /*Type*/GILLT_s32,
        GIM_RecordInsn, /*DefineMI*/2, /*MI*/1, /*OpIdx*/1, // MIs[2]
        GIM_CheckOpcode, /*MI*/2, GIMT_Encode2(TargetOpcode::G_FMAXNUM_IEEE),
        GIM_CheckType, /*MI*/2, /*Op*/1, /*Type*/GILLT_s32,
        GIM_CheckType, /*MI*/2, /*Op*/2, /*Type*/GILLT_s32,
        GIM_RecordInsn, /*DefineMI*/3, /*MI*/0, /*OpIdx*/2, // MIs[3]
        GIM_CheckOpcode, /*MI*/3, GIMT_Encode2(TargetOpcode::G_FMINNUM_IEEE),
        // MIs[3] VOP3Mods:src0:src0_mods
        GIM_CheckIsSameOperand, /*MI*/3, /*OpIdx*/1, /*OtherMI*/2, /*OtherOpIdx*/1,
        // MIs[3] VOP3Mods:src1:src1_mods
        GIM_CheckIsSameOperand, /*MI*/3, /*OpIdx*/2, /*OtherMI*/2, /*OtherOpIdx*/2,
        GIM_CheckCxxInsnPredicate, /*MI*/0, /*FnId*/GIMT_Encode2(GICXXPred_MI_Predicate_fmaxnum_like_nnan),
        GIM_CheckIsSafeToFold, /*InsnID*/1,
        GIM_CheckIsSafeToFold, /*InsnID*/2,
        GIM_CheckIsSafeToFold, /*InsnID*/3,
        GIM_CheckComplexPattern, /*MI*/1, /*Op*/2, /*Renderer*/GIMT_Encode2(2), GIMT_Encode2(GICP_gi_vop3mods),
        GIM_CheckComplexPattern, /*MI*/2, /*Op*/1, /*Renderer*/GIMT_Encode2(0), GIMT_Encode2(GICP_gi_vop3mods),
        GIM_CheckComplexPattern, /*MI*/2, /*Op*/2, /*Renderer*/GIMT_Encode2(1), GIMT_Encode2(GICP_gi_vop3mods),
        // (fmaxnum_ieee:{ *:[f32] } (fminnum_ieee:{ *:[f32] } (fmaxnum_ieee:{ *:[f32] } (VOP3Mods:{ *:[f32] } f32:{ *:[f32] }:$src0, i32:{ *:[i32] }:$src0_mods), (VOP3Mods:{ *:[f32] } f32:{ *:[f32] }:$src1, i32:{ *:[i32] }:$src1_mods)), (VOP3Mods:{ *:[f32] } f32:{ *:[f32] }:$src2, i32:{ *:[i32] }:$src2_mods)), (fminnum_ieee:{ *:[f32] } (VOP3Mods:{ *:[f32] } f32:{ *:[f32] }:$src0, i32:{ *:[i32] }:$src0_mods), (VOP3Mods:{ *:[f32] } f32:{ *:[f32] }:$src1, i32:{ *:[i32] }:$src1_mods)))<<P:Predicate_fmaxnum_like_nnan>>  =>  (V_MED3_F32_e64:{ *:[f32] } ?:{ *:[i32] }:$src0_mods, ?:{ *:[f32] }:$src0, ?:{ *:[i32] }:$src1_mods, ?:{ *:[f32] }:$src1, ?:{ *:[i32] }:$src2_mods, ?:{ *:[f32] }:$src2, 0:{ *:[i1] }, 0:{ *:[i32] })
        GIR_BuildMI, /*InsnID*/0, /*Opcode*/GIMT_Encode2(AMDGPU::V_MED3_F32_e64),
        GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/0, // DstI[vdst]
        GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/1, // src0_mods
        GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/0, // src0
        GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(1), /*SubOperand*/1, // src1_mods
        GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(1), /*SubOperand*/0, // src1
        GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(2), /*SubOperand*/1, // src2_mods
        GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(2), /*SubOperand*/0, // src2
        GIR_AddImm8, /*InsnID*/0, /*Imm*/0,
        GIR_AddImm8, /*InsnID*/0, /*Imm*/0,
        GIR_ConstrainSelectedInstOperands, /*InsnID*/0,
        GIR_EraseFromParent, /*InsnID*/0,
        // GIR_Coverage, 10007,
        GIR_Done,
      // Label 5182: @383516
      GIM_Try, /*On fail goto*//*Label 5183*/ GIMT_Encode4(383656), // Rule ID 10008 //
        GIM_CheckRegBankForClass, /*MI*/0, /*Op*/0, /*RC*/GIMT_Encode2(AMDGPU::VGPR_32RegClassID),
        GIM_RecordInsn, /*DefineMI*/1, /*MI*/0, /*OpIdx*/1, // MIs[1]
        GIM_CheckOpcode, /*MI*/1, GIMT_Encode2(TargetOpcode::G_FMINNUM_IEEE),
        GIM_CheckType, /*MI*/1, /*Op*/1, /*Type*/GILLT_s32,
        GIM_CheckType, /*MI*/1, /*Op*/2, /*Type*/GILLT_s32,
        GIM_RecordInsn, /*DefineMI*/2, /*MI*/1, /*OpIdx*/1, // MIs[2]
        GIM_CheckOpcode, /*MI*/2, GIMT_Encode2(TargetOpcode::G_FMAXNUM_IEEE),
        GIM_CheckType, /*MI*/2, /*Op*/1, /*Type*/GILLT_s32,
        GIM_CheckType, /*MI*/2, /*Op*/2, /*Type*/GILLT_s32,
        GIM_RecordInsn, /*DefineMI*/3, /*MI*/0, /*OpIdx*/2, // MIs[3]
        GIM_CheckOpcode, /*MI*/3, GIMT_Encode2(TargetOpcode::G_FMINNUM_IEEE),
        // MIs[3] VOP3Mods:src1:src1_mods
        GIM_CheckIsSameOperand, /*MI*/3, /*OpIdx*/1, /*OtherMI*/2, /*OtherOpIdx*/2,
        // MIs[3] VOP3Mods:src0:src0_mods
        GIM_CheckIsSameOperand, /*MI*/3, /*OpIdx*/2, /*OtherMI*/2, /*OtherOpIdx*/1,
        GIM_CheckCxxInsnPredicate, /*MI*/0, /*FnId*/GIMT_Encode2(GICXXPred_MI_Predicate_fmaxnum_like_nnan),
        GIM_CheckIsSafeToFold, /*InsnID*/1,
        GIM_CheckIsSafeToFold, /*InsnID*/2,
        GIM_CheckIsSafeToFold, /*InsnID*/3,
        GIM_CheckComplexPattern, /*MI*/1, /*Op*/2, /*Renderer*/GIMT_Encode2(2), GIMT_Encode2(GICP_gi_vop3mods),
        GIM_CheckComplexPattern, /*MI*/2, /*Op*/1, /*Renderer*/GIMT_Encode2(0), GIMT_Encode2(GICP_gi_vop3mods),
        GIM_CheckComplexPattern, /*MI*/2, /*Op*/2, /*Renderer*/GIMT_Encode2(1), GIMT_Encode2(GICP_gi_vop3mods),
        // (fmaxnum_ieee:{ *:[f32] } (fminnum_ieee:{ *:[f32] } (fmaxnum_ieee:{ *:[f32] } (VOP3Mods:{ *:[f32] } f32:{ *:[f32] }:$src0, i32:{ *:[i32] }:$src0_mods), (VOP3Mods:{ *:[f32] } f32:{ *:[f32] }:$src1, i32:{ *:[i32] }:$src1_mods)), (VOP3Mods:{ *:[f32] } f32:{ *:[f32] }:$src2, i32:{ *:[i32] }:$src2_mods)), (fminnum_ieee:{ *:[f32] } (VOP3Mods:{ *:[f32] } f32:{ *:[f32] }:$src1, i32:{ *:[i32] }:$src1_mods), (VOP3Mods:{ *:[f32] } f32:{ *:[f32] }:$src0, i32:{ *:[i32] }:$src0_mods)))<<P:Predicate_fmaxnum_like_nnan>>  =>  (V_MED3_F32_e64:{ *:[f32] } ?:{ *:[i32] }:$src0_mods, ?:{ *:[f32] }:$src0, ?:{ *:[i32] }:$src1_mods, ?:{ *:[f32] }:$src1, ?:{ *:[i32] }:$src2_mods, ?:{ *:[f32] }:$src2, 0:{ *:[i1] }, 0:{ *:[i32] })
        GIR_BuildMI, /*InsnID*/0, /*Opcode*/GIMT_Encode2(AMDGPU::V_MED3_F32_e64),
        GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/0, // DstI[vdst]
        GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/1, // src0_mods
        GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/0, // src0
        GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(1), /*SubOperand*/1, // src1_mods
        GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(1), /*SubOperand*/0, // src1
        GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(2), /*SubOperand*/1, // src2_mods
        GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(2), /*SubOperand*/0, // src2
        GIR_AddImm8, /*InsnID*/0, /*Imm*/0,
        GIR_AddImm8, /*InsnID*/0, /*Imm*/0,
        GIR_ConstrainSelectedInstOperands, /*InsnID*/0,
        GIR_EraseFromParent, /*InsnID*/0,
        // GIR_Coverage, 10008,
        GIR_Done,
      // Label 5183: @383656
      GIM_Try, /*On fail goto*//*Label 5184*/ GIMT_Encode4(383796), // Rule ID 10009 //
        GIM_CheckRegBankForClass, /*MI*/0, /*Op*/0, /*RC*/GIMT_Encode2(AMDGPU::VGPR_32RegClassID),
        GIM_RecordInsn, /*DefineMI*/1, /*MI*/0, /*OpIdx*/1, // MIs[1]
        GIM_CheckOpcode, /*MI*/1, GIMT_Encode2(TargetOpcode::G_FMINNUM_IEEE),
        GIM_CheckType, /*MI*/1, /*Op*/1, /*Type*/GILLT_s32,
        GIM_CheckType, /*MI*/1, /*Op*/2, /*Type*/GILLT_s32,
        GIM_RecordInsn, /*DefineMI*/2, /*MI*/1, /*OpIdx*/1, // MIs[2]
        GIM_CheckOpcode, /*MI*/2, GIMT_Encode2(TargetOpcode::G_FMAXNUM_IEEE),
        GIM_CheckType, /*MI*/2, /*Op*/1, /*Type*/GILLT_s32,
        GIM_CheckType, /*MI*/2, /*Op*/2, /*Type*/GILLT_s32,
        GIM_RecordInsn, /*DefineMI*/3, /*MI*/0, /*OpIdx*/2, // MIs[3]
        GIM_CheckOpcode, /*MI*/3, GIMT_Encode2(TargetOpcode::G_FMINNUM_IEEE),
        // MIs[3] VOP3Mods:src0:src0_mods
        GIM_CheckIsSameOperand, /*MI*/3, /*OpIdx*/1, /*OtherMI*/2, /*OtherOpIdx*/2,
        // MIs[3] VOP3Mods:src1:src1_mods
        GIM_CheckIsSameOperand, /*MI*/3, /*OpIdx*/2, /*OtherMI*/2, /*OtherOpIdx*/1,
        GIM_CheckCxxInsnPredicate, /*MI*/0, /*FnId*/GIMT_Encode2(GICXXPred_MI_Predicate_fmaxnum_like_nnan),
        GIM_CheckIsSafeToFold, /*InsnID*/1,
        GIM_CheckIsSafeToFold, /*InsnID*/2,
        GIM_CheckIsSafeToFold, /*InsnID*/3,
        GIM_CheckComplexPattern, /*MI*/1, /*Op*/2, /*Renderer*/GIMT_Encode2(2), GIMT_Encode2(GICP_gi_vop3mods),
        GIM_CheckComplexPattern, /*MI*/2, /*Op*/1, /*Renderer*/GIMT_Encode2(0), GIMT_Encode2(GICP_gi_vop3mods),
        GIM_CheckComplexPattern, /*MI*/2, /*Op*/2, /*Renderer*/GIMT_Encode2(1), GIMT_Encode2(GICP_gi_vop3mods),
        // (fmaxnum_ieee:{ *:[f32] } (fminnum_ieee:{ *:[f32] } (fmaxnum_ieee:{ *:[f32] } (VOP3Mods:{ *:[f32] } f32:{ *:[f32] }:$src1, i32:{ *:[i32] }:$src1_mods), (VOP3Mods:{ *:[f32] } f32:{ *:[f32] }:$src0, i32:{ *:[i32] }:$src0_mods)), (VOP3Mods:{ *:[f32] } f32:{ *:[f32] }:$src2, i32:{ *:[i32] }:$src2_mods)), (fminnum_ieee:{ *:[f32] } (VOP3Mods:{ *:[f32] } f32:{ *:[f32] }:$src0, i32:{ *:[i32] }:$src0_mods), (VOP3Mods:{ *:[f32] } f32:{ *:[f32] }:$src1, i32:{ *:[i32] }:$src1_mods)))<<P:Predicate_fmaxnum_like_nnan>>  =>  (V_MED3_F32_e64:{ *:[f32] } ?:{ *:[i32] }:$src0_mods, ?:{ *:[f32] }:$src0, ?:{ *:[i32] }:$src1_mods, ?:{ *:[f32] }:$src1, ?:{ *:[i32] }:$src2_mods, ?:{ *:[f32] }:$src2, 0:{ *:[i1] }, 0:{ *:[i32] })
        GIR_BuildMI, /*InsnID*/0, /*Opcode*/GIMT_Encode2(AMDGPU::V_MED3_F32_e64),
        GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/0, // DstI[vdst]
        GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(1), /*SubOperand*/1, // src0_mods
        GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(1), /*SubOperand*/0, // src0
        GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/1, // src1_mods
        GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/0, // src1
        GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(2), /*SubOperand*/1, // src2_mods
        GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(2), /*SubOperand*/0, // src2
        GIR_AddImm8, /*InsnID*/0, /*Imm*/0,
        GIR_AddImm8, /*InsnID*/0, /*Imm*/0,
        GIR_ConstrainSelectedInstOperands, /*InsnID*/0,
        GIR_EraseFromParent, /*InsnID*/0,
        // GIR_Coverage, 10009,
        GIR_Done,
      // Label 5184: @383796
      GIM_Try, /*On fail goto*//*Label 5185*/ GIMT_Encode4(383936), // Rule ID 10010 //
        GIM_CheckRegBankForClass, /*MI*/0, /*Op*/0, /*RC*/GIMT_Encode2(AMDGPU::VGPR_32RegClassID),
        GIM_RecordInsn, /*DefineMI*/1, /*MI*/0, /*OpIdx*/1, // MIs[1]
        GIM_CheckOpcode, /*MI*/1, GIMT_Encode2(TargetOpcode::G_FMINNUM_IEEE),
        GIM_CheckType, /*MI*/1, /*Op*/1, /*Type*/GILLT_s32,
        GIM_CheckType, /*MI*/1, /*Op*/2, /*Type*/GILLT_s32,
        GIM_RecordInsn, /*DefineMI*/2, /*MI*/1, /*OpIdx*/1, // MIs[2]
        GIM_CheckOpcode, /*MI*/2, GIMT_Encode2(TargetOpcode::G_FMAXNUM_IEEE),
        GIM_CheckType, /*MI*/2, /*Op*/1, /*Type*/GILLT_s32,
        GIM_CheckType, /*MI*/2, /*Op*/2, /*Type*/GILLT_s32,
        GIM_RecordInsn, /*DefineMI*/3, /*MI*/0, /*OpIdx*/2, // MIs[3]
        GIM_CheckOpcode, /*MI*/3, GIMT_Encode2(TargetOpcode::G_FMINNUM_IEEE),
        // MIs[3] VOP3Mods:src1:src1_mods
        GIM_CheckIsSameOperand, /*MI*/3, /*OpIdx*/1, /*OtherMI*/2, /*OtherOpIdx*/1,
        // MIs[3] VOP3Mods:src0:src0_mods
        GIM_CheckIsSameOperand, /*MI*/3, /*OpIdx*/2, /*OtherMI*/2, /*OtherOpIdx*/2,
        GIM_CheckCxxInsnPredicate, /*MI*/0, /*FnId*/GIMT_Encode2(GICXXPred_MI_Predicate_fmaxnum_like_nnan),
        GIM_CheckIsSafeToFold, /*InsnID*/1,
        GIM_CheckIsSafeToFold, /*InsnID*/2,
        GIM_CheckIsSafeToFold, /*InsnID*/3,
        GIM_CheckComplexPattern, /*MI*/1, /*Op*/2, /*Renderer*/GIMT_Encode2(2), GIMT_Encode2(GICP_gi_vop3mods),
        GIM_CheckComplexPattern, /*MI*/2, /*Op*/1, /*Renderer*/GIMT_Encode2(0), GIMT_Encode2(GICP_gi_vop3mods),
        GIM_CheckComplexPattern, /*MI*/2, /*Op*/2, /*Renderer*/GIMT_Encode2(1), GIMT_Encode2(GICP_gi_vop3mods),
        // (fmaxnum_ieee:{ *:[f32] } (fminnum_ieee:{ *:[f32] } (fmaxnum_ieee:{ *:[f32] } (VOP3Mods:{ *:[f32] } f32:{ *:[f32] }:$src1, i32:{ *:[i32] }:$src1_mods), (VOP3Mods:{ *:[f32] } f32:{ *:[f32] }:$src0, i32:{ *:[i32] }:$src0_mods)), (VOP3Mods:{ *:[f32] } f32:{ *:[f32] }:$src2, i32:{ *:[i32] }:$src2_mods)), (fminnum_ieee:{ *:[f32] } (VOP3Mods:{ *:[f32] } f32:{ *:[f32] }:$src1, i32:{ *:[i32] }:$src1_mods), (VOP3Mods:{ *:[f32] } f32:{ *:[f32] }:$src0, i32:{ *:[i32] }:$src0_mods)))<<P:Predicate_fmaxnum_like_nnan>>  =>  (V_MED3_F32_e64:{ *:[f32] } ?:{ *:[i32] }:$src0_mods, ?:{ *:[f32] }:$src0, ?:{ *:[i32] }:$src1_mods, ?:{ *:[f32] }:$src1, ?:{ *:[i32] }:$src2_mods, ?:{ *:[f32] }:$src2, 0:{ *:[i1] }, 0:{ *:[i32] })
        GIR_BuildMI, /*InsnID*/0, /*Opcode*/GIMT_Encode2(AMDGPU::V_MED3_F32_e64),
        GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/0, // DstI[vdst]
        GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(1), /*SubOperand*/1, // src0_mods
        GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(1), /*SubOperand*/0, // src0
        GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/1, // src1_mods
        GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/0, // src1
        GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(2), /*SubOperand*/1, // src2_mods
        GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(2), /*SubOperand*/0, // src2
        GIR_AddImm8, /*InsnID*/0, /*Imm*/0,
        GIR_AddImm8, /*InsnID*/0, /*Imm*/0,
        GIR_ConstrainSelectedInstOperands, /*InsnID*/0,
        GIR_EraseFromParent, /*InsnID*/0,
        // GIR_Coverage, 10010,
        GIR_Done,
      // Label 5185: @383936
      GIM_Try, /*On fail goto*//*Label 5186*/ GIMT_Encode4(384041), // Rule ID 10515 //
        GIM_CheckFeatures, GIMT_Encode2(GIFBS_isGFX11Plus),
        GIM_CheckRegBankForClass, /*MI*/0, /*Op*/0, /*RC*/GIMT_Encode2(AMDGPU::VGPR_32RegClassID),
        GIM_RecordInsn, /*DefineMI*/1, /*MI*/0, /*OpIdx*/2, // MIs[1]
        GIM_CheckOpcode, /*MI*/1, GIMT_Encode2(TargetOpcode::G_FMINNUM),
        GIM_CheckType, /*MI*/1, /*Op*/1, /*Type*/GILLT_s32,
        GIM_CheckType, /*MI*/1, /*Op*/2, /*Type*/GILLT_s32,
        GIM_CheckCxxInsnPredicate, /*MI*/1, /*FnId*/GIMT_Encode2(GICXXPred_MI_Predicate_fminnum_oneuse),
        GIM_CheckIsSafeToFold, /*InsnID*/1,
        GIM_CheckComplexPattern, /*MI*/0, /*Op*/1, /*Renderer*/GIMT_Encode2(0), GIMT_Encode2(GICP_gi_vop3mods),
        GIM_CheckComplexPattern, /*MI*/1, /*Op*/1, /*Renderer*/GIMT_Encode2(1), GIMT_Encode2(GICP_gi_vop3mods),
        GIM_CheckComplexPattern, /*MI*/1, /*Op*/2, /*Renderer*/GIMT_Encode2(2), GIMT_Encode2(GICP_gi_vop3mods),
        // (fmaxnum_ieee:{ *:[f32] } (VOP3Mods:{ *:[f32] } f32:{ *:[f32] }:$src2, i32:{ *:[i32] }:$src2_mods), (fminnum:{ *:[f32] } (VOP3Mods:{ *:[f32] } f32:{ *:[f32] }:$src0, i32:{ *:[i32] }:$src0_mods), (VOP3Mods:{ *:[f32] } f32:{ *:[f32] }:$src1, i32:{ *:[i32] }:$src1_mods))<<P:Predicate_fminnum_oneuse>>)  =>  (V_MINMAX_F32_e64:{ *:[f32] } ?:{ *:[i32] }:$src0_mods, ?:{ *:[f32] }:$src0, ?:{ *:[i32] }:$src1_mods, ?:{ *:[f32] }:$src1, ?:{ *:[i32] }:$src2_mods, ?:{ *:[f32] }:$src2, 0:{ *:[i1] }, 0:{ *:[i32] })
        GIR_BuildMI, /*InsnID*/0, /*Opcode*/GIMT_Encode2(AMDGPU::V_MINMAX_F32_e64),
        GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/0, // DstI[vdst]
        GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(1), /*SubOperand*/1, // src0_mods
        GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(1), /*SubOperand*/0, // src0
        GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(2), /*SubOperand*/1, // src1_mods
        GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(2), /*SubOperand*/0, // src1
        GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/1, // src2_mods
        GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/0, // src2
        GIR_AddImm8, /*InsnID*/0, /*Imm*/0,
        GIR_AddImm8, /*InsnID*/0, /*Imm*/0,
        GIR_ConstrainSelectedInstOperands, /*InsnID*/0,
        GIR_EraseFromParent, /*InsnID*/0,
        // GIR_Coverage, 10515,
        GIR_Done,
      // Label 5186: @384041
      GIM_Try, /*On fail goto*//*Label 5187*/ GIMT_Encode4(384146), // Rule ID 10514 //
        GIM_CheckFeatures, GIMT_Encode2(GIFBS_isGFX11Plus),
        GIM_CheckRegBankForClass, /*MI*/0, /*Op*/0, /*RC*/GIMT_Encode2(AMDGPU::VGPR_32RegClassID),
        GIM_RecordInsn, /*DefineMI*/1, /*MI*/0, /*OpIdx*/2, // MIs[1]
        GIM_CheckOpcode, /*MI*/1, GIMT_Encode2(TargetOpcode::G_FMINNUM_IEEE),
        GIM_CheckType, /*MI*/1, /*Op*/1, /*Type*/GILLT_s32,
        GIM_CheckType, /*MI*/1, /*Op*/2, /*Type*/GILLT_s32,
        GIM_CheckCxxInsnPredicate, /*MI*/1, /*FnId*/GIMT_Encode2(GICXXPred_MI_Predicate_fminnum_ieee_oneuse),
        GIM_CheckIsSafeToFold, /*InsnID*/1,
        GIM_CheckComplexPattern, /*MI*/0, /*Op*/1, /*Renderer*/GIMT_Encode2(0), GIMT_Encode2(GICP_gi_vop3mods),
        GIM_CheckComplexPattern, /*MI*/1, /*Op*/1, /*Renderer*/GIMT_Encode2(1), GIMT_Encode2(GICP_gi_vop3mods),
        GIM_CheckComplexPattern, /*MI*/1, /*Op*/2, /*Renderer*/GIMT_Encode2(2), GIMT_Encode2(GICP_gi_vop3mods),
        // (fmaxnum_ieee:{ *:[f32] } (VOP3Mods:{ *:[f32] } f32:{ *:[f32] }:$src2, i32:{ *:[i32] }:$src2_mods), (fminnum_ieee:{ *:[f32] } (VOP3Mods:{ *:[f32] } f32:{ *:[f32] }:$src0, i32:{ *:[i32] }:$src0_mods), (VOP3Mods:{ *:[f32] } f32:{ *:[f32] }:$src1, i32:{ *:[i32] }:$src1_mods))<<P:Predicate_fminnum_ieee_oneuse>>)  =>  (V_MINMAX_F32_e64:{ *:[f32] } ?:{ *:[i32] }:$src0_mods, ?:{ *:[f32] }:$src0, ?:{ *:[i32] }:$src1_mods, ?:{ *:[f32] }:$src1, ?:{ *:[i32] }:$src2_mods, ?:{ *:[f32] }:$src2, 0:{ *:[i1] }, 0:{ *:[i32] })
        GIR_BuildMI, /*InsnID*/0, /*Opcode*/GIMT_Encode2(AMDGPU::V_MINMAX_F32_e64),
        GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/0, // DstI[vdst]
        GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(1), /*SubOperand*/1, // src0_mods
        GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(1), /*SubOperand*/0, // src0
        GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(2), /*SubOperand*/1, // src1_mods
        GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(2), /*SubOperand*/0, // src1
        GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/1, // src2_mods
        GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/0, // src2
        GIR_AddImm8, /*InsnID*/0, /*Imm*/0,
        GIR_AddImm8, /*InsnID*/0, /*Imm*/0,
        GIR_ConstrainSelectedInstOperands, /*InsnID*/0,
        GIR_EraseFromParent, /*InsnID*/0,
        // GIR_Coverage, 10514,
        GIR_Done,
      // Label 5187: @384146
      GIM_Try, /*On fail goto*//*Label 5188*/ GIMT_Encode4(384251), // Rule ID 6521 //
        GIM_CheckFeatures, GIMT_Encode2(GIFBS_isGFX11Plus),
        GIM_CheckRegBankForClass, /*MI*/0, /*Op*/0, /*RC*/GIMT_Encode2(AMDGPU::VGPR_32RegClassID),
        GIM_RecordInsn, /*DefineMI*/1, /*MI*/0, /*OpIdx*/1, // MIs[1]
        GIM_CheckOpcode, /*MI*/1, GIMT_Encode2(TargetOpcode::G_FMINNUM),
        GIM_CheckType, /*MI*/1, /*Op*/1, /*Type*/GILLT_s32,
        GIM_CheckType, /*MI*/1, /*Op*/2, /*Type*/GILLT_s32,
        GIM_CheckCxxInsnPredicate, /*MI*/1, /*FnId*/GIMT_Encode2(GICXXPred_MI_Predicate_fminnum_oneuse),
        GIM_CheckIsSafeToFold, /*InsnID*/1,
        GIM_CheckComplexPattern, /*MI*/0, /*Op*/2, /*Renderer*/GIMT_Encode2(2), GIMT_Encode2(GICP_gi_vop3mods),
        GIM_CheckComplexPattern, /*MI*/1, /*Op*/1, /*Renderer*/GIMT_Encode2(0), GIMT_Encode2(GICP_gi_vop3mods),
        GIM_CheckComplexPattern, /*MI*/1, /*Op*/2, /*Renderer*/GIMT_Encode2(1), GIMT_Encode2(GICP_gi_vop3mods),
        // (fmaxnum_ieee:{ *:[f32] } (fminnum:{ *:[f32] } (VOP3Mods:{ *:[f32] } f32:{ *:[f32] }:$src0, i32:{ *:[i32] }:$src0_mods), (VOP3Mods:{ *:[f32] } f32:{ *:[f32] }:$src1, i32:{ *:[i32] }:$src1_mods))<<P:Predicate_fminnum_oneuse>>, (VOP3Mods:{ *:[f32] } f32:{ *:[f32] }:$src2, i32:{ *:[i32] }:$src2_mods))  =>  (V_MINMAX_F32_e64:{ *:[f32] } ?:{ *:[i32] }:$src0_mods, ?:{ *:[f32] }:$src0, ?:{ *:[i32] }:$src1_mods, ?:{ *:[f32] }:$src1, ?:{ *:[i32] }:$src2_mods, ?:{ *:[f32] }:$src2, 0:{ *:[i1] }, 0:{ *:[i32] })
        GIR_BuildMI, /*InsnID*/0, /*Opcode*/GIMT_Encode2(AMDGPU::V_MINMAX_F32_e64),
        GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/0, // DstI[vdst]
        GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/1, // src0_mods
        GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/0, // src0
        GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(1), /*SubOperand*/1, // src1_mods
        GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(1), /*SubOperand*/0, // src1
        GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(2), /*SubOperand*/1, // src2_mods
        GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(2), /*SubOperand*/0, // src2
        GIR_AddImm8, /*InsnID*/0, /*Imm*/0,
        GIR_AddImm8, /*InsnID*/0, /*Imm*/0,
        GIR_ConstrainSelectedInstOperands, /*InsnID*/0,
        GIR_EraseFromParent, /*InsnID*/0,
        // GIR_Coverage, 6521,
        GIR_Done,
      // Label 5188: @384251
      GIM_Try, /*On fail goto*//*Label 5189*/ GIMT_Encode4(384356), // Rule ID 6520 //
        GIM_CheckFeatures, GIMT_Encode2(GIFBS_isGFX11Plus),
        GIM_CheckRegBankForClass, /*MI*/0, /*Op*/0, /*RC*/GIMT_Encode2(AMDGPU::VGPR_32RegClassID),
        GIM_RecordInsn, /*DefineMI*/1, /*MI*/0, /*OpIdx*/1, // MIs[1]
        GIM_CheckOpcode, /*MI*/1, GIMT_Encode2(TargetOpcode::G_FMINNUM_IEEE),
        GIM_CheckType, /*MI*/1, /*Op*/1, /*Type*/GILLT_s32,
        GIM_CheckType, /*MI*/1, /*Op*/2, /*Type*/GILLT_s32,
        GIM_CheckCxxInsnPredicate, /*MI*/1, /*FnId*/GIMT_Encode2(GICXXPred_MI_Predicate_fminnum_ieee_oneuse),
        GIM_CheckIsSafeToFold, /*InsnID*/1,
        GIM_CheckComplexPattern, /*MI*/0, /*Op*/2, /*Renderer*/GIMT_Encode2(2), GIMT_Encode2(GICP_gi_vop3mods),
        GIM_CheckComplexPattern, /*MI*/1, /*Op*/1, /*Renderer*/GIMT_Encode2(0), GIMT_Encode2(GICP_gi_vop3mods),
        GIM_CheckComplexPattern, /*MI*/1, /*Op*/2, /*Renderer*/GIMT_Encode2(1), GIMT_Encode2(GICP_gi_vop3mods),
        // (fmaxnum_ieee:{ *:[f32] } (fminnum_ieee:{ *:[f32] } (VOP3Mods:{ *:[f32] } f32:{ *:[f32] }:$src0, i32:{ *:[i32] }:$src0_mods), (VOP3Mods:{ *:[f32] } f32:{ *:[f32] }:$src1, i32:{ *:[i32] }:$src1_mods))<<P:Predicate_fminnum_ieee_oneuse>>, (VOP3Mods:{ *:[f32] } f32:{ *:[f32] }:$src2, i32:{ *:[i32] }:$src2_mods))  =>  (V_MINMAX_F32_e64:{ *:[f32] } ?:{ *:[i32] }:$src0_mods, ?:{ *:[f32] }:$src0, ?:{ *:[i32] }:$src1_mods, ?:{ *:[f32] }:$src1, ?:{ *:[i32] }:$src2_mods, ?:{ *:[f32] }:$src2, 0:{ *:[i1] }, 0:{ *:[i32] })
        GIR_BuildMI, /*InsnID*/0, /*Opcode*/GIMT_Encode2(AMDGPU::V_MINMAX_F32_e64),
        GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/0, // DstI[vdst]
        GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/1, // src0_mods
        GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/0, // src0
        GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(1), /*SubOperand*/1, // src1_mods
        GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(1), /*SubOperand*/0, // src1
        GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(2), /*SubOperand*/1, // src2_mods
        GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(2), /*SubOperand*/0, // src2
        GIR_AddImm8, /*InsnID*/0, /*Imm*/0,
        GIR_AddImm8, /*InsnID*/0, /*Imm*/0,
        GIR_ConstrainSelectedInstOperands, /*InsnID*/0,
        GIR_EraseFromParent, /*InsnID*/0,
        // GIR_Coverage, 6520,
        GIR_Done,
      // Label 5189: @384356
      GIM_Try, /*On fail goto*//*Label 5190*/ GIMT_Encode4(384395), // Rule ID 94 //
        GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasSALUFloatInsts),
        GIM_CheckRegBankForClass, /*MI*/0, /*Op*/0, /*RC*/GIMT_Encode2(AMDGPU::SReg_32RegClassID),
        GIM_CheckRegBankForClass, /*MI*/0, /*Op*/1, /*RC*/GIMT_Encode2(AMDGPU::SReg_32RegClassID),
        GIM_CheckRegBankForClass, /*MI*/0, /*Op*/2, /*RC*/GIMT_Encode2(AMDGPU::SReg_32RegClassID),
        GIM_CheckCxxInsnPredicate, /*MI*/0, /*FnId*/GIMT_Encode2(GICXXPred_MI_Predicate_anonymous_17632),
        // (fmaxnum_ieee:{ *:[f32] } SSrc_f32:{ *:[f32] }:$src0, SSrc_f32:{ *:[f32] }:$src1)<<P:Predicate_anonymous_17632>>  =>  (S_MAX_F32:{ *:[f32] } SSrc_f32:{ *:[f32] }:$src0, SSrc_f32:{ *:[f32] }:$src1)
        GIR_MutateOpcode, /*InsnID*/0, /*RecycleInsnID*/0, /*Opcode*/GIMT_Encode2(AMDGPU::S_MAX_F32),
        GIR_AddImplicitUse, /*InsnID*/0, GIMT_Encode2(AMDGPU::MODE),
        GIR_ConstrainSelectedInstOperands, /*InsnID*/0,
        // GIR_Coverage, 94,
        GIR_Done,
      // Label 5190: @384395
      GIM_Try, /*On fail goto*//*Label 5191*/ GIMT_Encode4(384462), // Rule ID 741 //
        GIM_CheckRegBankForClass, /*MI*/0, /*Op*/0, /*RC*/GIMT_Encode2(AMDGPU::VGPR_32RegClassID),
        GIM_CheckComplexPattern, /*MI*/0, /*Op*/1, /*Renderer*/GIMT_Encode2(0), GIMT_Encode2(GICP_gi_vop3mods0),
        GIM_CheckComplexPattern, /*MI*/0, /*Op*/2, /*Renderer*/GIMT_Encode2(1), GIMT_Encode2(GICP_gi_vop3mods),
        // (fmaxnum_ieee:{ *:[f32] } (VOP3Mods0:{ *:[f32] } f32:{ *:[f32] }:$src0, i32:{ *:[i32] }:$src0_modifiers, i1:{ *:[i1] }:$clamp, i32:{ *:[i32] }:$omod), (VOP3Mods:{ *:[f32] } f32:{ *:[f32] }:$src1, i32:{ *:[i32] }:$src1_modifiers))  =>  (V_MAX_F32_e64:{ *:[f32] } i32:{ *:[i32] }:$src0_modifiers, f32:{ *:[f32] }:$src0, i32:{ *:[i32] }:$src1_modifiers, f32:{ *:[f32] }:$src1, i1:{ *:[i1] }:$clamp, i32:{ *:[i32] }:$omod)
        GIR_BuildMI, /*InsnID*/0, /*Opcode*/GIMT_Encode2(AMDGPU::V_MAX_F32_e64),
        GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/0, // DstI[vdst]
        GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/1, // src0_modifiers
        GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/0, // src0
        GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(1), /*SubOperand*/1, // src1_modifiers
        GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(1), /*SubOperand*/0, // src1
        GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/2, // clamp
        GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/3, // omod
        GIR_ConstrainSelectedInstOperands, /*InsnID*/0,
        GIR_EraseFromParent, /*InsnID*/0,
        // GIR_Coverage, 741,
        GIR_Done,
      // Label 5191: @384462
      GIM_Try, /*On fail goto*//*Label 5192*/ GIMT_Encode4(384529), // Rule ID 7133 //
        GIM_CheckRegBankForClass, /*MI*/0, /*Op*/0, /*RC*/GIMT_Encode2(AMDGPU::VGPR_32RegClassID),
        GIM_CheckComplexPattern, /*MI*/0, /*Op*/1, /*Renderer*/GIMT_Encode2(0), GIMT_Encode2(GICP_gi_vop3mods),
        GIM_CheckComplexPattern, /*MI*/0, /*Op*/2, /*Renderer*/GIMT_Encode2(1), GIMT_Encode2(GICP_gi_vop3mods0),
        // (fmaxnum_ieee:{ *:[f32] } (VOP3Mods:{ *:[f32] } f32:{ *:[f32] }:$src1, i32:{ *:[i32] }:$src1_modifiers), (VOP3Mods0:{ *:[f32] } f32:{ *:[f32] }:$src0, i32:{ *:[i32] }:$src0_modifiers, i1:{ *:[i1] }:$clamp, i32:{ *:[i32] }:$omod))  =>  (V_MAX_F32_e64:{ *:[f32] } i32:{ *:[i32] }:$src0_modifiers, f32:{ *:[f32] }:$src0, i32:{ *:[i32] }:$src1_modifiers, f32:{ *:[f32] }:$src1, i1:{ *:[i1] }:$clamp, i32:{ *:[i32] }:$omod)
        GIR_BuildMI, /*InsnID*/0, /*Opcode*/GIMT_Encode2(AMDGPU::V_MAX_F32_e64),
        GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/0, // DstI[vdst]
        GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(1), /*SubOperand*/1, // src0_modifiers
        GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(1), /*SubOperand*/0, // src0
        GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/1, // src1_modifiers
        GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/0, // src1
        GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(1), /*SubOperand*/2, // clamp
        GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(1), /*SubOperand*/3, // omod
        GIR_ConstrainSelectedInstOperands, /*InsnID*/0,
        GIR_EraseFromParent, /*InsnID*/0,
        // GIR_Coverage, 7133,
        GIR_Done,
      // Label 5192: @384529
      GIM_Reject,
    // Label 5057: @384530
    GIM_Reject,
    // Label 4914: @384531
    GIM_Try, /*On fail goto*//*Label 5193*/ GIMT_Encode4(384810),
      GIM_CheckType, /*MI*/0, /*Op*/1, /*Type*/GILLT_s64,
      GIM_CheckType, /*MI*/0, /*Op*/2, /*Type*/GILLT_s64,
      GIM_CheckRegBankForClass, /*MI*/0, /*Op*/0, /*RC*/GIMT_Encode2(AMDGPU::VReg_64RegClassID),
      GIM_Try, /*On fail goto*//*Label 5194*/ GIMT_Encode4(384614), // Rule ID 844 //
        GIM_CheckFeatures, GIMT_Encode2(GIFBS_isGFX12Plus),
        GIM_CheckComplexPattern, /*MI*/0, /*Op*/1, /*Renderer*/GIMT_Encode2(0), GIMT_Encode2(GICP_gi_vop3mods0),
        GIM_CheckComplexPattern, /*MI*/0, /*Op*/2, /*Renderer*/GIMT_Encode2(1), GIMT_Encode2(GICP_gi_vop3mods),
        // (fmaxnum_ieee:{ *:[f64] } (VOP3Mods0:{ *:[f64] } f64:{ *:[f64] }:$src0, i32:{ *:[i32] }:$src0_modifiers, i1:{ *:[i1] }:$clamp, i32:{ *:[i32] }:$omod), (VOP3Mods:{ *:[f64] } f64:{ *:[f64] }:$src1, i32:{ *:[i32] }:$src1_modifiers))  =>  (V_MAX_NUM_F64_e64:{ *:[f64] } i32:{ *:[i32] }:$src0_modifiers, f64:{ *:[f64] }:$src0, i32:{ *:[i32] }:$src1_modifiers, f64:{ *:[f64] }:$src1, i1:{ *:[i1] }:$clamp, i32:{ *:[i32] }:$omod)
        GIR_BuildMI, /*InsnID*/0, /*Opcode*/GIMT_Encode2(AMDGPU::V_MAX_NUM_F64_e64),
        GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/0, // DstI[vdst]
        GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/1, // src0_modifiers
        GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/0, // src0
        GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(1), /*SubOperand*/1, // src1_modifiers
        GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(1), /*SubOperand*/0, // src1
        GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/2, // clamp
        GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/3, // omod
        GIR_ConstrainSelectedInstOperands, /*InsnID*/0,
        GIR_EraseFromParent, /*InsnID*/0,
        // GIR_Coverage, 844,
        GIR_Done,
      // Label 5194: @384614
      GIM_Try, /*On fail goto*//*Label 5195*/ GIMT_Encode4(384679), // Rule ID 863 //
        GIM_CheckFeatures, GIMT_Encode2(GIFBS_isNotGFX12Plus),
        GIM_CheckComplexPattern, /*MI*/0, /*Op*/1, /*Renderer*/GIMT_Encode2(0), GIMT_Encode2(GICP_gi_vop3mods0),
        GIM_CheckComplexPattern, /*MI*/0, /*Op*/2, /*Renderer*/GIMT_Encode2(1), GIMT_Encode2(GICP_gi_vop3mods),
        // (fmaxnum_ieee:{ *:[f64] } (VOP3Mods0:{ *:[f64] } f64:{ *:[f64] }:$src0, i32:{ *:[i32] }:$src0_modifiers, i1:{ *:[i1] }:$clamp, i32:{ *:[i32] }:$omod), (VOP3Mods:{ *:[f64] } f64:{ *:[f64] }:$src1, i32:{ *:[i32] }:$src1_modifiers))  =>  (V_MAX_F64_e64:{ *:[f64] } i32:{ *:[i32] }:$src0_modifiers, f64:{ *:[f64] }:$src0, i32:{ *:[i32] }:$src1_modifiers, f64:{ *:[f64] }:$src1, i1:{ *:[i1] }:$clamp, i32:{ *:[i32] }:$omod)
        GIR_BuildMI, /*InsnID*/0, /*Opcode*/GIMT_Encode2(AMDGPU::V_MAX_F64_e64),
        GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/0, // DstI[vdst]
        GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/1, // src0_modifiers
        GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/0, // src0
        GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(1), /*SubOperand*/1, // src1_modifiers
        GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(1), /*SubOperand*/0, // src1
        GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/2, // clamp
        GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/3, // omod
        GIR_ConstrainSelectedInstOperands, /*InsnID*/0,
        GIR_EraseFromParent, /*InsnID*/0,
        // GIR_Coverage, 863,
        GIR_Done,
      // Label 5195: @384679
      GIM_Try, /*On fail goto*//*Label 5196*/ GIMT_Encode4(384744), // Rule ID 7167 //
        GIM_CheckFeatures, GIMT_Encode2(GIFBS_isGFX12Plus),
        GIM_CheckComplexPattern, /*MI*/0, /*Op*/1, /*Renderer*/GIMT_Encode2(0), GIMT_Encode2(GICP_gi_vop3mods),
        GIM_CheckComplexPattern, /*MI*/0, /*Op*/2, /*Renderer*/GIMT_Encode2(1), GIMT_Encode2(GICP_gi_vop3mods0),
        // (fmaxnum_ieee:{ *:[f64] } (VOP3Mods:{ *:[f64] } f64:{ *:[f64] }:$src1, i32:{ *:[i32] }:$src1_modifiers), (VOP3Mods0:{ *:[f64] } f64:{ *:[f64] }:$src0, i32:{ *:[i32] }:$src0_modifiers, i1:{ *:[i1] }:$clamp, i32:{ *:[i32] }:$omod))  =>  (V_MAX_NUM_F64_e64:{ *:[f64] } i32:{ *:[i32] }:$src0_modifiers, f64:{ *:[f64] }:$src0, i32:{ *:[i32] }:$src1_modifiers, f64:{ *:[f64] }:$src1, i1:{ *:[i1] }:$clamp, i32:{ *:[i32] }:$omod)
        GIR_BuildMI, /*InsnID*/0, /*Opcode*/GIMT_Encode2(AMDGPU::V_MAX_NUM_F64_e64),
        GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/0, // DstI[vdst]
        GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(1), /*SubOperand*/1, // src0_modifiers
        GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(1), /*SubOperand*/0, // src0
        GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/1, // src1_modifiers
        GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/0, // src1
        GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(1), /*SubOperand*/2, // clamp
        GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(1), /*SubOperand*/3, // omod
        GIR_ConstrainSelectedInstOperands, /*InsnID*/0,
        GIR_EraseFromParent, /*InsnID*/0,
        // GIR_Coverage, 7167,
        GIR_Done,
      // Label 5196: @384744
      GIM_Try, /*On fail goto*//*Label 5197*/ GIMT_Encode4(384809), // Rule ID 7181 //
        GIM_CheckFeatures, GIMT_Encode2(GIFBS_isNotGFX12Plus),
        GIM_CheckComplexPattern, /*MI*/0, /*Op*/1, /*Renderer*/GIMT_Encode2(0), GIMT_Encode2(GICP_gi_vop3mods),
        GIM_CheckComplexPattern, /*MI*/0, /*Op*/2, /*Renderer*/GIMT_Encode2(1), GIMT_Encode2(GICP_gi_vop3mods0),
        // (fmaxnum_ieee:{ *:[f64] } (VOP3Mods:{ *:[f64] } f64:{ *:[f64] }:$src1, i32:{ *:[i32] }:$src1_modifiers), (VOP3Mods0:{ *:[f64] } f64:{ *:[f64] }:$src0, i32:{ *:[i32] }:$src0_modifiers, i1:{ *:[i1] }:$clamp, i32:{ *:[i32] }:$omod))  =>  (V_MAX_F64_e64:{ *:[f64] } i32:{ *:[i32] }:$src0_modifiers, f64:{ *:[f64] }:$src0, i32:{ *:[i32] }:$src1_modifiers, f64:{ *:[f64] }:$src1, i1:{ *:[i1] }:$clamp, i32:{ *:[i32] }:$omod)
        GIR_BuildMI, /*InsnID*/0, /*Opcode*/GIMT_Encode2(AMDGPU::V_MAX_F64_e64),
        GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/0, // DstI[vdst]
        GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(1), /*SubOperand*/1, // src0_modifiers
        GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(1), /*SubOperand*/0, // src0
        GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/1, // src1_modifiers
        GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/0, // src1
        GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(1), /*SubOperand*/2, // clamp
        GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(1), /*SubOperand*/3, // omod
        GIR_ConstrainSelectedInstOperands, /*InsnID*/0,
        GIR_EraseFromParent, /*InsnID*/0,
        // GIR_Coverage, 7181,
        GIR_Done,
      // Label 5197: @384809
      GIM_Reject,
    // Label 5193: @384810
    GIM_Reject,
    // Label 4915: @384811
    GIM_Try, /*On fail goto*//*Label 5198*/ GIMT_Encode4(384891), // Rule ID 964 //
      GIM_CheckType, /*MI*/0, /*Op*/1, /*Type*/GILLT_v2s16,
      GIM_CheckType, /*MI*/0, /*Op*/2, /*Type*/GILLT_v2s16,
      GIM_CheckRegBankForClass, /*MI*/0, /*Op*/0, /*RC*/GIMT_Encode2(AMDGPU::VGPR_32RegClassID),
      GIM_CheckComplexPattern, /*MI*/0, /*Op*/1, /*Renderer*/GIMT_Encode2(0), GIMT_Encode2(GICP_gi_vop3pmods),
      GIM_CheckComplexPattern, /*MI*/0, /*Op*/2, /*Renderer*/GIMT_Encode2(1), GIMT_Encode2(GICP_gi_vop3pmods),
      // (fmaxnum_ieee:{ *:[v2f16] } (VOP3PMods:{ *:[v2f16] } v2f16:{ *:[v2f16] }:$src0, i32:{ *:[i32] }:$src0_modifiers), (VOP3PMods:{ *:[v2f16] } v2f16:{ *:[v2f16] }:$src1, i32:{ *:[i32] }:$src1_modifiers))  =>  (V_PK_MAX_F16:{ *:[v2f16] } i32:{ *:[i32] }:$src0_modifiers, v2f16:{ *:[v2f16] }:$src0, i32:{ *:[i32] }:$src1_modifiers, v2f16:{ *:[v2f16] }:$src1)
      GIR_BuildMI, /*InsnID*/0, /*Opcode*/GIMT_Encode2(AMDGPU::V_PK_MAX_F16),
      GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/0, // DstI[vdst]
      GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/1, // src0_modifiers
      GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/0, // src0
      GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(1), /*SubOperand*/1, // src1_modifiers
      GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(1), /*SubOperand*/0, // src1
      GIR_AddImm8, /*InsnID*/0, /*Imm*/0,
      GIR_AddImm8, /*InsnID*/0, /*Imm*/0,
      GIR_AddImm8, /*InsnID*/0, /*Imm*/0,
      GIR_AddImm8, /*InsnID*/0, /*Imm*/0,
      GIR_AddImm8, /*InsnID*/0, /*Imm*/0,
      GIR_ConstrainSelectedInstOperands, /*InsnID*/0,
      GIR_EraseFromParent, /*InsnID*/0,
      // GIR_Coverage, 964,
      GIR_Done,
    // Label 5198: @384891
    GIM_Reject,
    // Label 4916: @384892
    GIM_Reject,
    // Label 80: @384893
    GIM_SwitchType, /*MI*/0, /*Op*/0, /*[*/GIMT_Encode2(8), GIMT_Encode2(12), /*)*//*default:*//*Label 5203*/ GIMT_Encode4(385992),
    /*GILLT_s16*//*Label 5199*/ GIMT_Encode4(384920),
    /*GILLT_s32*//*Label 5200*/ GIMT_Encode4(385342),
    /*GILLT_s64*//*Label 5201*/ GIMT_Encode4(385758),
    /*GILLT_v2s16*//*Label 5202*/ GIMT_Encode4(385908),
    // Label 5199: @384920
    GIM_Try, /*On fail goto*//*Label 5204*/ GIMT_Encode4(385341),
      GIM_CheckType, /*MI*/0, /*Op*/1, /*Type*/GILLT_s16,
      GIM_CheckType, /*MI*/0, /*Op*/2, /*Type*/GILLT_s16,
      GIM_Try, /*On fail goto*//*Label 5205*/ GIMT_Encode4(385045), // Rule ID 10803 //
        GIM_CheckFeatures, GIMT_Encode2(GIFBS_isGFX12Plus),
        GIM_CheckRegBankForClass, /*MI*/0, /*Op*/0, /*RC*/GIMT_Encode2(AMDGPU::VGPR_32RegClassID),
        GIM_RecordInsn, /*DefineMI*/1, /*MI*/0, /*OpIdx*/2, // MIs[1]
        GIM_CheckOpcode, /*MI*/1, GIMT_Encode2(TargetOpcode::G_FMAXIMUM),
        GIM_CheckType, /*MI*/1, /*Op*/1, /*Type*/GILLT_s16,
        GIM_CheckType, /*MI*/1, /*Op*/2, /*Type*/GILLT_s16,
        GIM_CheckCxxInsnPredicate, /*MI*/1, /*FnId*/GIMT_Encode2(GICXXPred_MI_Predicate_fmaximum_oneuse),
        GIM_CheckCxxInsnPredicate, /*MI*/0, /*FnId*/GIMT_Encode2(GICXXPred_MI_Predicate_anonymous_23219),
        GIM_CheckIsSafeToFold, /*InsnID*/1,
        GIM_CheckComplexPattern, /*MI*/0, /*Op*/1, /*Renderer*/GIMT_Encode2(0), GIMT_Encode2(GICP_gi_vop3mods),
        GIM_CheckComplexPattern, /*MI*/1, /*Op*/1, /*Renderer*/GIMT_Encode2(1), GIMT_Encode2(GICP_gi_vop3mods),
        GIM_CheckComplexPattern, /*MI*/1, /*Op*/2, /*Renderer*/GIMT_Encode2(2), GIMT_Encode2(GICP_gi_vop3mods),
        // (fminimum:{ *:[f16] } (VOP3Mods:{ *:[f16] } f16:{ *:[f16] }:$src2, i32:{ *:[i32] }:$src2_mods), (fmaximum:{ *:[f16] } (VOP3Mods:{ *:[f16] } f16:{ *:[f16] }:$src0, i32:{ *:[i32] }:$src0_mods), (VOP3Mods:{ *:[f16] } f16:{ *:[f16] }:$src1, i32:{ *:[i32] }:$src1_mods))<<P:Predicate_fmaximum_oneuse>>)<<P:Predicate_anonymous_23219>>  =>  (V_MAXIMUMMINIMUM_F16_e64:{ *:[f16] } ?:{ *:[i32] }:$src0_mods, ?:{ *:[f16] }:$src0, ?:{ *:[i32] }:$src1_mods, ?:{ *:[f16] }:$src1, ?:{ *:[i32] }:$src2_mods, ?:{ *:[f16] }:$src2, 0:{ *:[i1] }, 0:{ *:[i32] })
        GIR_BuildMI, /*InsnID*/0, /*Opcode*/GIMT_Encode2(AMDGPU::V_MAXIMUMMINIMUM_F16_e64),
        GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/0, // DstI[vdst]
        GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(1), /*SubOperand*/1, // src0_mods
        GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(1), /*SubOperand*/0, // src0
        GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(2), /*SubOperand*/1, // src1_mods
        GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(2), /*SubOperand*/0, // src1
        GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/1, // src2_mods
        GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/0, // src2
        GIR_AddImm8, /*InsnID*/0, /*Imm*/0,
        GIR_AddImm8, /*InsnID*/0, /*Imm*/0,
        GIR_AddImm8, /*InsnID*/0, /*Imm*/0,
        GIR_ConstrainSelectedInstOperands, /*InsnID*/0,
        GIR_EraseFromParent, /*InsnID*/0,
        // GIR_Coverage, 10803,
        GIR_Done,
      // Label 5205: @385045
      GIM_Try, /*On fail goto*//*Label 5206*/ GIMT_Encode4(385157), // Rule ID 6557 //
        GIM_CheckFeatures, GIMT_Encode2(GIFBS_isGFX12Plus),
        GIM_CheckRegBankForClass, /*MI*/0, /*Op*/0, /*RC*/GIMT_Encode2(AMDGPU::VGPR_32RegClassID),
        GIM_RecordInsn, /*DefineMI*/1, /*MI*/0, /*OpIdx*/1, // MIs[1]
        GIM_CheckOpcode, /*MI*/1, GIMT_Encode2(TargetOpcode::G_FMAXIMUM),
        GIM_CheckType, /*MI*/1, /*Op*/1, /*Type*/GILLT_s16,
        GIM_CheckType, /*MI*/1, /*Op*/2, /*Type*/GILLT_s16,
        GIM_CheckCxxInsnPredicate, /*MI*/1, /*FnId*/GIMT_Encode2(GICXXPred_MI_Predicate_fmaximum_oneuse),
        GIM_CheckCxxInsnPredicate, /*MI*/0, /*FnId*/GIMT_Encode2(GICXXPred_MI_Predicate_anonymous_23219),
        GIM_CheckIsSafeToFold, /*InsnID*/1,
        GIM_CheckComplexPattern, /*MI*/0, /*Op*/2, /*Renderer*/GIMT_Encode2(2), GIMT_Encode2(GICP_gi_vop3mods),
        GIM_CheckComplexPattern, /*MI*/1, /*Op*/1, /*Renderer*/GIMT_Encode2(0), GIMT_Encode2(GICP_gi_vop3mods),
        GIM_CheckComplexPattern, /*MI*/1, /*Op*/2, /*Renderer*/GIMT_Encode2(1), GIMT_Encode2(GICP_gi_vop3mods),
        // (fminimum:{ *:[f16] } (fmaximum:{ *:[f16] } (VOP3Mods:{ *:[f16] } f16:{ *:[f16] }:$src0, i32:{ *:[i32] }:$src0_mods), (VOP3Mods:{ *:[f16] } f16:{ *:[f16] }:$src1, i32:{ *:[i32] }:$src1_mods))<<P:Predicate_fmaximum_oneuse>>, (VOP3Mods:{ *:[f16] } f16:{ *:[f16] }:$src2, i32:{ *:[i32] }:$src2_mods))<<P:Predicate_anonymous_23219>>  =>  (V_MAXIMUMMINIMUM_F16_e64:{ *:[f16] } ?:{ *:[i32] }:$src0_mods, ?:{ *:[f16] }:$src0, ?:{ *:[i32] }:$src1_mods, ?:{ *:[f16] }:$src1, ?:{ *:[i32] }:$src2_mods, ?:{ *:[f16] }:$src2, 0:{ *:[i1] }, 0:{ *:[i32] })
        GIR_BuildMI, /*InsnID*/0, /*Opcode*/GIMT_Encode2(AMDGPU::V_MAXIMUMMINIMUM_F16_e64),
        GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/0, // DstI[vdst]
        GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/1, // src0_mods
        GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/0, // src0
        GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(1), /*SubOperand*/1, // src1_mods
        GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(1), /*SubOperand*/0, // src1
        GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(2), /*SubOperand*/1, // src2_mods
        GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(2), /*SubOperand*/0, // src2
        GIR_AddImm8, /*InsnID*/0, /*Imm*/0,
        GIR_AddImm8, /*InsnID*/0, /*Imm*/0,
        GIR_AddImm8, /*InsnID*/0, /*Imm*/0,
        GIR_ConstrainSelectedInstOperands, /*InsnID*/0,
        GIR_EraseFromParent, /*InsnID*/0,
        // GIR_Coverage, 6557,
        GIR_Done,
      // Label 5206: @385157
      GIM_Try, /*On fail goto*//*Label 5207*/ GIMT_Encode4(385192), // Rule ID 118 //
        GIM_CheckFeatures, GIMT_Encode2(GIFBS_isGFX12Plus),
        GIM_CheckRegBankForClass, /*MI*/0, /*Op*/0, /*RC*/GIMT_Encode2(AMDGPU::SReg_32RegClassID),
        GIM_CheckRegBankForClass, /*MI*/0, /*Op*/1, /*RC*/GIMT_Encode2(AMDGPU::SReg_32RegClassID),
        GIM_CheckRegBankForClass, /*MI*/0, /*Op*/2, /*RC*/GIMT_Encode2(AMDGPU::SReg_32RegClassID),
        GIM_CheckCxxInsnPredicate, /*MI*/0, /*FnId*/GIMT_Encode2(GICXXPred_MI_Predicate_anonymous_17637),
        // (fminimum:{ *:[f16] } SSrc_f16:{ *:[f16] }:$src0, SSrc_f16:{ *:[f16] }:$src1)<<P:Predicate_anonymous_17637>>  =>  (S_MINIMUM_F16:{ *:[f16] } SSrc_f16:{ *:[f16] }:$src0, SSrc_f16:{ *:[f16] }:$src1)
        GIR_MutateOpcode, /*InsnID*/0, /*RecycleInsnID*/0, /*Opcode*/GIMT_Encode2(AMDGPU::S_MINIMUM_F16),
        GIR_ConstrainSelectedInstOperands, /*InsnID*/0,
        // GIR_Coverage, 118,
        GIR_Done,
      // Label 5207: @385192
      GIM_Try, /*On fail goto*//*Label 5208*/ GIMT_Encode4(385266), // Rule ID 870 //
        GIM_CheckFeatures, GIMT_Encode2(GIFBS_isGFX12Plus),
        GIM_CheckRegBankForClass, /*MI*/0, /*Op*/0, /*RC*/GIMT_Encode2(AMDGPU::VGPR_32RegClassID),
        GIM_CheckCxxInsnPredicate, /*MI*/0, /*FnId*/GIMT_Encode2(GICXXPred_MI_Predicate_anonymous_23219),
        GIM_CheckComplexPattern, /*MI*/0, /*Op*/1, /*Renderer*/GIMT_Encode2(0), GIMT_Encode2(GICP_gi_vop3mods0),
        GIM_CheckComplexPattern, /*MI*/0, /*Op*/2, /*Renderer*/GIMT_Encode2(1), GIMT_Encode2(GICP_gi_vop3mods),
        // (fminimum:{ *:[f16] } (VOP3Mods0:{ *:[f16] } f16:{ *:[f16] }:$src0, i32:{ *:[i32] }:$src0_modifiers, i1:{ *:[i1] }:$clamp, i32:{ *:[i32] }:$omod), (VOP3Mods:{ *:[f16] } f16:{ *:[f16] }:$src1, i32:{ *:[i32] }:$src1_modifiers))<<P:Predicate_anonymous_23219>>  =>  (V_MINIMUM_F16_e64:{ *:[f16] } i32:{ *:[i32] }:$src0_modifiers, f16:{ *:[f16] }:$src0, i32:{ *:[i32] }:$src1_modifiers, f16:{ *:[f16] }:$src1, i1:{ *:[i1] }:$clamp, i32:{ *:[i32] }:$omod)
        GIR_BuildMI, /*InsnID*/0, /*Opcode*/GIMT_Encode2(AMDGPU::V_MINIMUM_F16_e64),
        GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/0, // DstI[vdst]
        GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/1, // src0_modifiers
        GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/0, // src0
        GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(1), /*SubOperand*/1, // src1_modifiers
        GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(1), /*SubOperand*/0, // src1
        GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/2, // clamp
        GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/3, // omod
        GIR_ConstrainSelectedInstOperands, /*InsnID*/0,
        GIR_EraseFromParent, /*InsnID*/0,
        // GIR_Coverage, 870,
        GIR_Done,
      // Label 5208: @385266
      GIM_Try, /*On fail goto*//*Label 5209*/ GIMT_Encode4(385340), // Rule ID 7188 //
        GIM_CheckFeatures, GIMT_Encode2(GIFBS_isGFX12Plus),
        GIM_CheckRegBankForClass, /*MI*/0, /*Op*/0, /*RC*/GIMT_Encode2(AMDGPU::VGPR_32RegClassID),
        GIM_CheckCxxInsnPredicate, /*MI*/0, /*FnId*/GIMT_Encode2(GICXXPred_MI_Predicate_anonymous_23219),
        GIM_CheckComplexPattern, /*MI*/0, /*Op*/1, /*Renderer*/GIMT_Encode2(0), GIMT_Encode2(GICP_gi_vop3mods),
        GIM_CheckComplexPattern, /*MI*/0, /*Op*/2, /*Renderer*/GIMT_Encode2(1), GIMT_Encode2(GICP_gi_vop3mods0),
        // (fminimum:{ *:[f16] } (VOP3Mods:{ *:[f16] } f16:{ *:[f16] }:$src1, i32:{ *:[i32] }:$src1_modifiers), (VOP3Mods0:{ *:[f16] } f16:{ *:[f16] }:$src0, i32:{ *:[i32] }:$src0_modifiers, i1:{ *:[i1] }:$clamp, i32:{ *:[i32] }:$omod))<<P:Predicate_anonymous_23219>>  =>  (V_MINIMUM_F16_e64:{ *:[f16] } i32:{ *:[i32] }:$src0_modifiers, f16:{ *:[f16] }:$src0, i32:{ *:[i32] }:$src1_modifiers, f16:{ *:[f16] }:$src1, i1:{ *:[i1] }:$clamp, i32:{ *:[i32] }:$omod)
        GIR_BuildMI, /*InsnID*/0, /*Opcode*/GIMT_Encode2(AMDGPU::V_MINIMUM_F16_e64),
        GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/0, // DstI[vdst]
        GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(1), /*SubOperand*/1, // src0_modifiers
        GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(1), /*SubOperand*/0, // src0
        GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/1, // src1_modifiers
        GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/0, // src1
        GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(1), /*SubOperand*/2, // clamp
        GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(1), /*SubOperand*/3, // omod
        GIR_ConstrainSelectedInstOperands, /*InsnID*/0,
        GIR_EraseFromParent, /*InsnID*/0,
        // GIR_Coverage, 7188,
        GIR_Done,
      // Label 5209: @385340
      GIM_Reject,
    // Label 5204: @385341
    GIM_Reject,
    // Label 5200: @385342
    GIM_Try, /*On fail goto*//*Label 5210*/ GIMT_Encode4(385757),
      GIM_CheckType, /*MI*/0, /*Op*/1, /*Type*/GILLT_s32,
      GIM_CheckType, /*MI*/0, /*Op*/2, /*Type*/GILLT_s32,
      GIM_Try, /*On fail goto*//*Label 5211*/ GIMT_Encode4(385464), // Rule ID 10801 //
        GIM_CheckFeatures, GIMT_Encode2(GIFBS_isGFX12Plus),
        GIM_CheckRegBankForClass, /*MI*/0, /*Op*/0, /*RC*/GIMT_Encode2(AMDGPU::VGPR_32RegClassID),
        GIM_RecordInsn, /*DefineMI*/1, /*MI*/0, /*OpIdx*/2, // MIs[1]
        GIM_CheckOpcode, /*MI*/1, GIMT_Encode2(TargetOpcode::G_FMAXIMUM),
        GIM_CheckType, /*MI*/1, /*Op*/1, /*Type*/GILLT_s32,
        GIM_CheckType, /*MI*/1, /*Op*/2, /*Type*/GILLT_s32,
        GIM_CheckCxxInsnPredicate, /*MI*/1, /*FnId*/GIMT_Encode2(GICXXPred_MI_Predicate_fmaximum_oneuse),
        GIM_CheckCxxInsnPredicate, /*MI*/0, /*FnId*/GIMT_Encode2(GICXXPred_MI_Predicate_anonymous_23219),
        GIM_CheckIsSafeToFold, /*InsnID*/1,
        GIM_CheckComplexPattern, /*MI*/0, /*Op*/1, /*Renderer*/GIMT_Encode2(0), GIMT_Encode2(GICP_gi_vop3mods),
        GIM_CheckComplexPattern, /*MI*/1, /*Op*/1, /*Renderer*/GIMT_Encode2(1), GIMT_Encode2(GICP_gi_vop3mods),
        GIM_CheckComplexPattern, /*MI*/1, /*Op*/2, /*Renderer*/GIMT_Encode2(2), GIMT_Encode2(GICP_gi_vop3mods),
        // (fminimum:{ *:[f32] } (VOP3Mods:{ *:[f32] } f32:{ *:[f32] }:$src2, i32:{ *:[i32] }:$src2_mods), (fmaximum:{ *:[f32] } (VOP3Mods:{ *:[f32] } f32:{ *:[f32] }:$src0, i32:{ *:[i32] }:$src0_mods), (VOP3Mods:{ *:[f32] } f32:{ *:[f32] }:$src1, i32:{ *:[i32] }:$src1_mods))<<P:Predicate_fmaximum_oneuse>>)<<P:Predicate_anonymous_23219>>  =>  (V_MAXIMUMMINIMUM_F32_e64:{ *:[f32] } ?:{ *:[i32] }:$src0_mods, ?:{ *:[f32] }:$src0, ?:{ *:[i32] }:$src1_mods, ?:{ *:[f32] }:$src1, ?:{ *:[i32] }:$src2_mods, ?:{ *:[f32] }:$src2, 0:{ *:[i1] }, 0:{ *:[i32] })
        GIR_BuildMI, /*InsnID*/0, /*Opcode*/GIMT_Encode2(AMDGPU::V_MAXIMUMMINIMUM_F32_e64),
        GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/0, // DstI[vdst]
        GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(1), /*SubOperand*/1, // src0_mods
        GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(1), /*SubOperand*/0, // src0
        GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(2), /*SubOperand*/1, // src1_mods
        GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(2), /*SubOperand*/0, // src1
        GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/1, // src2_mods
        GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/0, // src2
        GIR_AddImm8, /*InsnID*/0, /*Imm*/0,
        GIR_AddImm8, /*InsnID*/0, /*Imm*/0,
        GIR_ConstrainSelectedInstOperands, /*InsnID*/0,
        GIR_EraseFromParent, /*InsnID*/0,
        // GIR_Coverage, 10801,
        GIR_Done,
      // Label 5211: @385464
      GIM_Try, /*On fail goto*//*Label 5212*/ GIMT_Encode4(385573), // Rule ID 6555 //
        GIM_CheckFeatures, GIMT_Encode2(GIFBS_isGFX12Plus),
        GIM_CheckRegBankForClass, /*MI*/0, /*Op*/0, /*RC*/GIMT_Encode2(AMDGPU::VGPR_32RegClassID),
        GIM_RecordInsn, /*DefineMI*/1, /*MI*/0, /*OpIdx*/1, // MIs[1]
        GIM_CheckOpcode, /*MI*/1, GIMT_Encode2(TargetOpcode::G_FMAXIMUM),
        GIM_CheckType, /*MI*/1, /*Op*/1, /*Type*/GILLT_s32,
        GIM_CheckType, /*MI*/1, /*Op*/2, /*Type*/GILLT_s32,
        GIM_CheckCxxInsnPredicate, /*MI*/1, /*FnId*/GIMT_Encode2(GICXXPred_MI_Predicate_fmaximum_oneuse),
        GIM_CheckCxxInsnPredicate, /*MI*/0, /*FnId*/GIMT_Encode2(GICXXPred_MI_Predicate_anonymous_23219),
        GIM_CheckIsSafeToFold, /*InsnID*/1,
        GIM_CheckComplexPattern, /*MI*/0, /*Op*/2, /*Renderer*/GIMT_Encode2(2), GIMT_Encode2(GICP_gi_vop3mods),
        GIM_CheckComplexPattern, /*MI*/1, /*Op*/1, /*Renderer*/GIMT_Encode2(0), GIMT_Encode2(GICP_gi_vop3mods),
        GIM_CheckComplexPattern, /*MI*/1, /*Op*/2, /*Renderer*/GIMT_Encode2(1), GIMT_Encode2(GICP_gi_vop3mods),
        // (fminimum:{ *:[f32] } (fmaximum:{ *:[f32] } (VOP3Mods:{ *:[f32] } f32:{ *:[f32] }:$src0, i32:{ *:[i32] }:$src0_mods), (VOP3Mods:{ *:[f32] } f32:{ *:[f32] }:$src1, i32:{ *:[i32] }:$src1_mods))<<P:Predicate_fmaximum_oneuse>>, (VOP3Mods:{ *:[f32] } f32:{ *:[f32] }:$src2, i32:{ *:[i32] }:$src2_mods))<<P:Predicate_anonymous_23219>>  =>  (V_MAXIMUMMINIMUM_F32_e64:{ *:[f32] } ?:{ *:[i32] }:$src0_mods, ?:{ *:[f32] }:$src0, ?:{ *:[i32] }:$src1_mods, ?:{ *:[f32] }:$src1, ?:{ *:[i32] }:$src2_mods, ?:{ *:[f32] }:$src2, 0:{ *:[i1] }, 0:{ *:[i32] })
        GIR_BuildMI, /*InsnID*/0, /*Opcode*/GIMT_Encode2(AMDGPU::V_MAXIMUMMINIMUM_F32_e64),
        GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/0, // DstI[vdst]
        GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/1, // src0_mods
        GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/0, // src0
        GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(1), /*SubOperand*/1, // src1_mods
        GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(1), /*SubOperand*/0, // src1
        GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(2), /*SubOperand*/1, // src2_mods
        GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(2), /*SubOperand*/0, // src2
        GIR_AddImm8, /*InsnID*/0, /*Imm*/0,
        GIR_AddImm8, /*InsnID*/0, /*Imm*/0,
        GIR_ConstrainSelectedInstOperands, /*InsnID*/0,
        GIR_EraseFromParent, /*InsnID*/0,
        // GIR_Coverage, 6555,
        GIR_Done,
      // Label 5212: @385573
      GIM_Try, /*On fail goto*//*Label 5213*/ GIMT_Encode4(385608), // Rule ID 116 //
        GIM_CheckFeatures, GIMT_Encode2(GIFBS_isGFX12Plus),
        GIM_CheckRegBankForClass, /*MI*/0, /*Op*/0, /*RC*/GIMT_Encode2(AMDGPU::SReg_32RegClassID),
        GIM_CheckRegBankForClass, /*MI*/0, /*Op*/1, /*RC*/GIMT_Encode2(AMDGPU::SReg_32RegClassID),
        GIM_CheckRegBankForClass, /*MI*/0, /*Op*/2, /*RC*/GIMT_Encode2(AMDGPU::SReg_32RegClassID),
        GIM_CheckCxxInsnPredicate, /*MI*/0, /*FnId*/GIMT_Encode2(GICXXPred_MI_Predicate_anonymous_17637),
        // (fminimum:{ *:[f32] } SSrc_f32:{ *:[f32] }:$src0, SSrc_f32:{ *:[f32] }:$src1)<<P:Predicate_anonymous_17637>>  =>  (S_MINIMUM_F32:{ *:[f32] } SSrc_f32:{ *:[f32] }:$src0, SSrc_f32:{ *:[f32] }:$src1)
        GIR_MutateOpcode, /*InsnID*/0, /*RecycleInsnID*/0, /*Opcode*/GIMT_Encode2(AMDGPU::S_MINIMUM_F32),
        GIR_ConstrainSelectedInstOperands, /*InsnID*/0,
        // GIR_Coverage, 116,
        GIR_Done,
      // Label 5213: @385608
      GIM_Try, /*On fail goto*//*Label 5214*/ GIMT_Encode4(385682), // Rule ID 868 //
        GIM_CheckFeatures, GIMT_Encode2(GIFBS_isGFX12Plus),
        GIM_CheckRegBankForClass, /*MI*/0, /*Op*/0, /*RC*/GIMT_Encode2(AMDGPU::VGPR_32RegClassID),
        GIM_CheckCxxInsnPredicate, /*MI*/0, /*FnId*/GIMT_Encode2(GICXXPred_MI_Predicate_anonymous_23219),
        GIM_CheckComplexPattern, /*MI*/0, /*Op*/1, /*Renderer*/GIMT_Encode2(0), GIMT_Encode2(GICP_gi_vop3mods0),
        GIM_CheckComplexPattern, /*MI*/0, /*Op*/2, /*Renderer*/GIMT_Encode2(1), GIMT_Encode2(GICP_gi_vop3mods),
        // (fminimum:{ *:[f32] } (VOP3Mods0:{ *:[f32] } f32:{ *:[f32] }:$src0, i32:{ *:[i32] }:$src0_modifiers, i1:{ *:[i1] }:$clamp, i32:{ *:[i32] }:$omod), (VOP3Mods:{ *:[f32] } f32:{ *:[f32] }:$src1, i32:{ *:[i32] }:$src1_modifiers))<<P:Predicate_anonymous_23219>>  =>  (V_MINIMUM_F32_e64:{ *:[f32] } i32:{ *:[i32] }:$src0_modifiers, f32:{ *:[f32] }:$src0, i32:{ *:[i32] }:$src1_modifiers, f32:{ *:[f32] }:$src1, i1:{ *:[i1] }:$clamp, i32:{ *:[i32] }:$omod)
        GIR_BuildMI, /*InsnID*/0, /*Opcode*/GIMT_Encode2(AMDGPU::V_MINIMUM_F32_e64),
        GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/0, // DstI[vdst]
        GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/1, // src0_modifiers
        GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/0, // src0
        GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(1), /*SubOperand*/1, // src1_modifiers
        GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(1), /*SubOperand*/0, // src1
        GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/2, // clamp
        GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/3, // omod
        GIR_ConstrainSelectedInstOperands, /*InsnID*/0,
        GIR_EraseFromParent, /*InsnID*/0,
        // GIR_Coverage, 868,
        GIR_Done,
      // Label 5214: @385682
      GIM_Try, /*On fail goto*//*Label 5215*/ GIMT_Encode4(385756), // Rule ID 7186 //
        GIM_CheckFeatures, GIMT_Encode2(GIFBS_isGFX12Plus),
        GIM_CheckRegBankForClass, /*MI*/0, /*Op*/0, /*RC*/GIMT_Encode2(AMDGPU::VGPR_32RegClassID),
        GIM_CheckCxxInsnPredicate, /*MI*/0, /*FnId*/GIMT_Encode2(GICXXPred_MI_Predicate_anonymous_23219),
        GIM_CheckComplexPattern, /*MI*/0, /*Op*/1, /*Renderer*/GIMT_Encode2(0), GIMT_Encode2(GICP_gi_vop3mods),
        GIM_CheckComplexPattern, /*MI*/0, /*Op*/2, /*Renderer*/GIMT_Encode2(1), GIMT_Encode2(GICP_gi_vop3mods0),
        // (fminimum:{ *:[f32] } (VOP3Mods:{ *:[f32] } f32:{ *:[f32] }:$src1, i32:{ *:[i32] }:$src1_modifiers), (VOP3Mods0:{ *:[f32] } f32:{ *:[f32] }:$src0, i32:{ *:[i32] }:$src0_modifiers, i1:{ *:[i1] }:$clamp, i32:{ *:[i32] }:$omod))<<P:Predicate_anonymous_23219>>  =>  (V_MINIMUM_F32_e64:{ *:[f32] } i32:{ *:[i32] }:$src0_modifiers, f32:{ *:[f32] }:$src0, i32:{ *:[i32] }:$src1_modifiers, f32:{ *:[f32] }:$src1, i1:{ *:[i1] }:$clamp, i32:{ *:[i32] }:$omod)
        GIR_BuildMI, /*InsnID*/0, /*Opcode*/GIMT_Encode2(AMDGPU::V_MINIMUM_F32_e64),
        GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/0, // DstI[vdst]
        GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(1), /*SubOperand*/1, // src0_modifiers
        GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(1), /*SubOperand*/0, // src0
        GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/1, // src1_modifiers
        GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/0, // src1
        GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(1), /*SubOperand*/2, // clamp
        GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(1), /*SubOperand*/3, // omod
        GIR_ConstrainSelectedInstOperands, /*InsnID*/0,
        GIR_EraseFromParent, /*InsnID*/0,
        // GIR_Coverage, 7186,
        GIR_Done,
      // Label 5215: @385756
      GIM_Reject,
    // Label 5210: @385757
    GIM_Reject,
    // Label 5201: @385758
    GIM_Try, /*On fail goto*//*Label 5216*/ GIMT_Encode4(385907),
      GIM_CheckType, /*MI*/0, /*Op*/1, /*Type*/GILLT_s64,
      GIM_CheckType, /*MI*/0, /*Op*/2, /*Type*/GILLT_s64,
      GIM_CheckRegBankForClass, /*MI*/0, /*Op*/0, /*RC*/GIMT_Encode2(AMDGPU::VReg_64RegClassID),
      GIM_Try, /*On fail goto*//*Label 5217*/ GIMT_Encode4(385841), // Rule ID 872 //
        GIM_CheckFeatures, GIMT_Encode2(GIFBS_isGFX12Plus),
        GIM_CheckComplexPattern, /*MI*/0, /*Op*/1, /*Renderer*/GIMT_Encode2(0), GIMT_Encode2(GICP_gi_vop3mods0),
        GIM_CheckComplexPattern, /*MI*/0, /*Op*/2, /*Renderer*/GIMT_Encode2(1), GIMT_Encode2(GICP_gi_vop3mods),
        // (fminimum:{ *:[f64] } (VOP3Mods0:{ *:[f64] } f64:{ *:[f64] }:$src0, i32:{ *:[i32] }:$src0_modifiers, i1:{ *:[i1] }:$clamp, i32:{ *:[i32] }:$omod), (VOP3Mods:{ *:[f64] } f64:{ *:[f64] }:$src1, i32:{ *:[i32] }:$src1_modifiers))  =>  (V_MINIMUM_F64_e64:{ *:[f64] } i32:{ *:[i32] }:$src0_modifiers, f64:{ *:[f64] }:$src0, i32:{ *:[i32] }:$src1_modifiers, f64:{ *:[f64] }:$src1, i1:{ *:[i1] }:$clamp, i32:{ *:[i32] }:$omod)
        GIR_BuildMI, /*InsnID*/0, /*Opcode*/GIMT_Encode2(AMDGPU::V_MINIMUM_F64_e64),
        GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/0, // DstI[vdst]
        GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/1, // src0_modifiers
        GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/0, // src0
        GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(1), /*SubOperand*/1, // src1_modifiers
        GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(1), /*SubOperand*/0, // src1
        GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/2, // clamp
        GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/3, // omod
        GIR_ConstrainSelectedInstOperands, /*InsnID*/0,
        GIR_EraseFromParent, /*InsnID*/0,
        // GIR_Coverage, 872,
        GIR_Done,
      // Label 5217: @385841
      GIM_Try, /*On fail goto*//*Label 5218*/ GIMT_Encode4(385906), // Rule ID 7190 //
        GIM_CheckFeatures, GIMT_Encode2(GIFBS_isGFX12Plus),
        GIM_CheckComplexPattern, /*MI*/0, /*Op*/1, /*Renderer*/GIMT_Encode2(0), GIMT_Encode2(GICP_gi_vop3mods),
        GIM_CheckComplexPattern, /*MI*/0, /*Op*/2, /*Renderer*/GIMT_Encode2(1), GIMT_Encode2(GICP_gi_vop3mods0),
        // (fminimum:{ *:[f64] } (VOP3Mods:{ *:[f64] } f64:{ *:[f64] }:$src1, i32:{ *:[i32] }:$src1_modifiers), (VOP3Mods0:{ *:[f64] } f64:{ *:[f64] }:$src0, i32:{ *:[i32] }:$src0_modifiers, i1:{ *:[i1] }:$clamp, i32:{ *:[i32] }:$omod))  =>  (V_MINIMUM_F64_e64:{ *:[f64] } i32:{ *:[i32] }:$src0_modifiers, f64:{ *:[f64] }:$src0, i32:{ *:[i32] }:$src1_modifiers, f64:{ *:[f64] }:$src1, i1:{ *:[i1] }:$clamp, i32:{ *:[i32] }:$omod)
        GIR_BuildMI, /*InsnID*/0, /*Opcode*/GIMT_Encode2(AMDGPU::V_MINIMUM_F64_e64),
        GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/0, // DstI[vdst]
        GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(1), /*SubOperand*/1, // src0_modifiers
        GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(1), /*SubOperand*/0, // src0
        GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/1, // src1_modifiers
        GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/0, // src1
        GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(1), /*SubOperand*/2, // clamp
        GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(1), /*SubOperand*/3, // omod
        GIR_ConstrainSelectedInstOperands, /*InsnID*/0,
        GIR_EraseFromParent, /*InsnID*/0,
        // GIR_Coverage, 7190,
        GIR_Done,
      // Label 5218: @385906
      GIM_Reject,
    // Label 5216: @385907
    GIM_Reject,
    // Label 5202: @385908
    GIM_Try, /*On fail goto*//*Label 5219*/ GIMT_Encode4(385991), // Rule ID 975 //
      GIM_CheckFeatures, GIMT_Encode2(GIFBS_isGFX12Plus),
      GIM_CheckType, /*MI*/0, /*Op*/1, /*Type*/GILLT_v2s16,
      GIM_CheckType, /*MI*/0, /*Op*/2, /*Type*/GILLT_v2s16,
      GIM_CheckRegBankForClass, /*MI*/0, /*Op*/0, /*RC*/GIMT_Encode2(AMDGPU::VGPR_32RegClassID),
      GIM_CheckComplexPattern, /*MI*/0, /*Op*/1, /*Renderer*/GIMT_Encode2(0), GIMT_Encode2(GICP_gi_vop3pmods),
      GIM_CheckComplexPattern, /*MI*/0, /*Op*/2, /*Renderer*/GIMT_Encode2(1), GIMT_Encode2(GICP_gi_vop3pmods),
      // (fminimum:{ *:[v2f16] } (VOP3PMods:{ *:[v2f16] } v2f16:{ *:[v2f16] }:$src0, i32:{ *:[i32] }:$src0_modifiers), (VOP3PMods:{ *:[v2f16] } v2f16:{ *:[v2f16] }:$src1, i32:{ *:[i32] }:$src1_modifiers))  =>  (V_PK_MINIMUM_F16:{ *:[v2f16] } i32:{ *:[i32] }:$src0_modifiers, v2f16:{ *:[v2f16] }:$src0, i32:{ *:[i32] }:$src1_modifiers, v2f16:{ *:[v2f16] }:$src1)
      GIR_BuildMI, /*InsnID*/0, /*Opcode*/GIMT_Encode2(AMDGPU::V_PK_MINIMUM_F16),
      GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/0, // DstI[vdst]
      GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/1, // src0_modifiers
      GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/0, // src0
      GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(1), /*SubOperand*/1, // src1_modifiers
      GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(1), /*SubOperand*/0, // src1
      GIR_AddImm8, /*InsnID*/0, /*Imm*/0,
      GIR_AddImm8, /*InsnID*/0, /*Imm*/0,
      GIR_AddImm8, /*InsnID*/0, /*Imm*/0,
      GIR_AddImm8, /*InsnID*/0, /*Imm*/0,
      GIR_AddImm8, /*InsnID*/0, /*Imm*/0,
      GIR_ConstrainSelectedInstOperands, /*InsnID*/0,
      GIR_EraseFromParent, /*InsnID*/0,
      // GIR_Coverage, 975,
      GIR_Done,
    // Label 5219: @385991
    GIM_Reject,
    // Label 5203: @385992
    GIM_Reject,
    // Label 81: @385993
    GIM_SwitchType, /*MI*/0, /*Op*/0, /*[*/GIMT_Encode2(8), GIMT_Encode2(12), /*)*//*default:*//*Label 5224*/ GIMT_Encode4(387092),
    /*GILLT_s16*//*Label 5220*/ GIMT_Encode4(386020),
    /*GILLT_s32*//*Label 5221*/ GIMT_Encode4(386442),
    /*GILLT_s64*//*Label 5222*/ GIMT_Encode4(386858),
    /*GILLT_v2s16*//*Label 5223*/ GIMT_Encode4(387008),
    // Label 5220: @386020
    GIM_Try, /*On fail goto*//*Label 5225*/ GIMT_Encode4(386441),
      GIM_CheckType, /*MI*/0, /*Op*/1, /*Type*/GILLT_s16,
      GIM_CheckType, /*MI*/0, /*Op*/2, /*Type*/GILLT_s16,
      GIM_Try, /*On fail goto*//*Label 5226*/ GIMT_Encode4(386145), // Rule ID 10802 //
        GIM_CheckFeatures, GIMT_Encode2(GIFBS_isGFX12Plus),
        GIM_CheckRegBankForClass, /*MI*/0, /*Op*/0, /*RC*/GIMT_Encode2(AMDGPU::VGPR_32RegClassID),
        GIM_RecordInsn, /*DefineMI*/1, /*MI*/0, /*OpIdx*/2, // MIs[1]
        GIM_CheckOpcode, /*MI*/1, GIMT_Encode2(TargetOpcode::G_FMINIMUM),
        GIM_CheckType, /*MI*/1, /*Op*/1, /*Type*/GILLT_s16,
        GIM_CheckType, /*MI*/1, /*Op*/2, /*Type*/GILLT_s16,
        GIM_CheckCxxInsnPredicate, /*MI*/1, /*FnId*/GIMT_Encode2(GICXXPred_MI_Predicate_fminimum_oneuse),
        GIM_CheckCxxInsnPredicate, /*MI*/0, /*FnId*/GIMT_Encode2(GICXXPred_MI_Predicate_anonymous_23222),
        GIM_CheckIsSafeToFold, /*InsnID*/1,
        GIM_CheckComplexPattern, /*MI*/0, /*Op*/1, /*Renderer*/GIMT_Encode2(0), GIMT_Encode2(GICP_gi_vop3mods),
        GIM_CheckComplexPattern, /*MI*/1, /*Op*/1, /*Renderer*/GIMT_Encode2(1), GIMT_Encode2(GICP_gi_vop3mods),
        GIM_CheckComplexPattern, /*MI*/1, /*Op*/2, /*Renderer*/GIMT_Encode2(2), GIMT_Encode2(GICP_gi_vop3mods),
        // (fmaximum:{ *:[f16] } (VOP3Mods:{ *:[f16] } f16:{ *:[f16] }:$src2, i32:{ *:[i32] }:$src2_mods), (fminimum:{ *:[f16] } (VOP3Mods:{ *:[f16] } f16:{ *:[f16] }:$src0, i32:{ *:[i32] }:$src0_mods), (VOP3Mods:{ *:[f16] } f16:{ *:[f16] }:$src1, i32:{ *:[i32] }:$src1_mods))<<P:Predicate_fminimum_oneuse>>)<<P:Predicate_anonymous_23222>>  =>  (V_MINIMUMMAXIMUM_F16_e64:{ *:[f16] } ?:{ *:[i32] }:$src0_mods, ?:{ *:[f16] }:$src0, ?:{ *:[i32] }:$src1_mods, ?:{ *:[f16] }:$src1, ?:{ *:[i32] }:$src2_mods, ?:{ *:[f16] }:$src2, 0:{ *:[i1] }, 0:{ *:[i32] })
        GIR_BuildMI, /*InsnID*/0, /*Opcode*/GIMT_Encode2(AMDGPU::V_MINIMUMMAXIMUM_F16_e64),
        GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/0, // DstI[vdst]
        GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(1), /*SubOperand*/1, // src0_mods
        GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(1), /*SubOperand*/0, // src0
        GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(2), /*SubOperand*/1, // src1_mods
        GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(2), /*SubOperand*/0, // src1
        GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/1, // src2_mods
        GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/0, // src2
        GIR_AddImm8, /*InsnID*/0, /*Imm*/0,
        GIR_AddImm8, /*InsnID*/0, /*Imm*/0,
        GIR_AddImm8, /*InsnID*/0, /*Imm*/0,
        GIR_ConstrainSelectedInstOperands, /*InsnID*/0,
        GIR_EraseFromParent, /*InsnID*/0,
        // GIR_Coverage, 10802,
        GIR_Done,
      // Label 5226: @386145
      GIM_Try, /*On fail goto*//*Label 5227*/ GIMT_Encode4(386257), // Rule ID 6556 //
        GIM_CheckFeatures, GIMT_Encode2(GIFBS_isGFX12Plus),
        GIM_CheckRegBankForClass, /*MI*/0, /*Op*/0, /*RC*/GIMT_Encode2(AMDGPU::VGPR_32RegClassID),
        GIM_RecordInsn, /*DefineMI*/1, /*MI*/0, /*OpIdx*/1, // MIs[1]
        GIM_CheckOpcode, /*MI*/1, GIMT_Encode2(TargetOpcode::G_FMINIMUM),
        GIM_CheckType, /*MI*/1, /*Op*/1, /*Type*/GILLT_s16,
        GIM_CheckType, /*MI*/1, /*Op*/2, /*Type*/GILLT_s16,
        GIM_CheckCxxInsnPredicate, /*MI*/1, /*FnId*/GIMT_Encode2(GICXXPred_MI_Predicate_fminimum_oneuse),
        GIM_CheckCxxInsnPredicate, /*MI*/0, /*FnId*/GIMT_Encode2(GICXXPred_MI_Predicate_anonymous_23222),
        GIM_CheckIsSafeToFold, /*InsnID*/1,
        GIM_CheckComplexPattern, /*MI*/0, /*Op*/2, /*Renderer*/GIMT_Encode2(2), GIMT_Encode2(GICP_gi_vop3mods),
        GIM_CheckComplexPattern, /*MI*/1, /*Op*/1, /*Renderer*/GIMT_Encode2(0), GIMT_Encode2(GICP_gi_vop3mods),
        GIM_CheckComplexPattern, /*MI*/1, /*Op*/2, /*Renderer*/GIMT_Encode2(1), GIMT_Encode2(GICP_gi_vop3mods),
        // (fmaximum:{ *:[f16] } (fminimum:{ *:[f16] } (VOP3Mods:{ *:[f16] } f16:{ *:[f16] }:$src0, i32:{ *:[i32] }:$src0_mods), (VOP3Mods:{ *:[f16] } f16:{ *:[f16] }:$src1, i32:{ *:[i32] }:$src1_mods))<<P:Predicate_fminimum_oneuse>>, (VOP3Mods:{ *:[f16] } f16:{ *:[f16] }:$src2, i32:{ *:[i32] }:$src2_mods))<<P:Predicate_anonymous_23222>>  =>  (V_MINIMUMMAXIMUM_F16_e64:{ *:[f16] } ?:{ *:[i32] }:$src0_mods, ?:{ *:[f16] }:$src0, ?:{ *:[i32] }:$src1_mods, ?:{ *:[f16] }:$src1, ?:{ *:[i32] }:$src2_mods, ?:{ *:[f16] }:$src2, 0:{ *:[i1] }, 0:{ *:[i32] })
        GIR_BuildMI, /*InsnID*/0, /*Opcode*/GIMT_Encode2(AMDGPU::V_MINIMUMMAXIMUM_F16_e64),
        GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/0, // DstI[vdst]
        GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/1, // src0_mods
        GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/0, // src0
        GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(1), /*SubOperand*/1, // src1_mods
        GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(1), /*SubOperand*/0, // src1
        GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(2), /*SubOperand*/1, // src2_mods
        GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(2), /*SubOperand*/0, // src2
        GIR_AddImm8, /*InsnID*/0, /*Imm*/0,
        GIR_AddImm8, /*InsnID*/0, /*Imm*/0,
        GIR_AddImm8, /*InsnID*/0, /*Imm*/0,
        GIR_ConstrainSelectedInstOperands, /*InsnID*/0,
        GIR_EraseFromParent, /*InsnID*/0,
        // GIR_Coverage, 6556,
        GIR_Done,
      // Label 5227: @386257
      GIM_Try, /*On fail goto*//*Label 5228*/ GIMT_Encode4(386292), // Rule ID 119 //
        GIM_CheckFeatures, GIMT_Encode2(GIFBS_isGFX12Plus),
        GIM_CheckRegBankForClass, /*MI*/0, /*Op*/0, /*RC*/GIMT_Encode2(AMDGPU::SReg_32RegClassID),
        GIM_CheckRegBankForClass, /*MI*/0, /*Op*/1, /*RC*/GIMT_Encode2(AMDGPU::SReg_32RegClassID),
        GIM_CheckRegBankForClass, /*MI*/0, /*Op*/2, /*RC*/GIMT_Encode2(AMDGPU::SReg_32RegClassID),
        GIM_CheckCxxInsnPredicate, /*MI*/0, /*FnId*/GIMT_Encode2(GICXXPred_MI_Predicate_anonymous_17638),
        // (fmaximum:{ *:[f16] } SSrc_f16:{ *:[f16] }:$src0, SSrc_f16:{ *:[f16] }:$src1)<<P:Predicate_anonymous_17638>>  =>  (S_MAXIMUM_F16:{ *:[f16] } SSrc_f16:{ *:[f16] }:$src0, SSrc_f16:{ *:[f16] }:$src1)
        GIR_MutateOpcode, /*InsnID*/0, /*RecycleInsnID*/0, /*Opcode*/GIMT_Encode2(AMDGPU::S_MAXIMUM_F16),
        GIR_ConstrainSelectedInstOperands, /*InsnID*/0,
        // GIR_Coverage, 119,
        GIR_Done,
      // Label 5228: @386292
      GIM_Try, /*On fail goto*//*Label 5229*/ GIMT_Encode4(386366), // Rule ID 871 //
        GIM_CheckFeatures, GIMT_Encode2(GIFBS_isGFX12Plus),
        GIM_CheckRegBankForClass, /*MI*/0, /*Op*/0, /*RC*/GIMT_Encode2(AMDGPU::VGPR_32RegClassID),
        GIM_CheckCxxInsnPredicate, /*MI*/0, /*FnId*/GIMT_Encode2(GICXXPred_MI_Predicate_anonymous_23222),
        GIM_CheckComplexPattern, /*MI*/0, /*Op*/1, /*Renderer*/GIMT_Encode2(0), GIMT_Encode2(GICP_gi_vop3mods0),
        GIM_CheckComplexPattern, /*MI*/0, /*Op*/2, /*Renderer*/GIMT_Encode2(1), GIMT_Encode2(GICP_gi_vop3mods),
        // (fmaximum:{ *:[f16] } (VOP3Mods0:{ *:[f16] } f16:{ *:[f16] }:$src0, i32:{ *:[i32] }:$src0_modifiers, i1:{ *:[i1] }:$clamp, i32:{ *:[i32] }:$omod), (VOP3Mods:{ *:[f16] } f16:{ *:[f16] }:$src1, i32:{ *:[i32] }:$src1_modifiers))<<P:Predicate_anonymous_23222>>  =>  (V_MAXIMUM_F16_e64:{ *:[f16] } i32:{ *:[i32] }:$src0_modifiers, f16:{ *:[f16] }:$src0, i32:{ *:[i32] }:$src1_modifiers, f16:{ *:[f16] }:$src1, i1:{ *:[i1] }:$clamp, i32:{ *:[i32] }:$omod)
        GIR_BuildMI, /*InsnID*/0, /*Opcode*/GIMT_Encode2(AMDGPU::V_MAXIMUM_F16_e64),
        GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/0, // DstI[vdst]
        GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/1, // src0_modifiers
        GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/0, // src0
        GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(1), /*SubOperand*/1, // src1_modifiers
        GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(1), /*SubOperand*/0, // src1
        GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/2, // clamp
        GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/3, // omod
        GIR_ConstrainSelectedInstOperands, /*InsnID*/0,
        GIR_EraseFromParent, /*InsnID*/0,
        // GIR_Coverage, 871,
        GIR_Done,
      // Label 5229: @386366
      GIM_Try, /*On fail goto*//*Label 5230*/ GIMT_Encode4(386440), // Rule ID 7189 //
        GIM_CheckFeatures, GIMT_Encode2(GIFBS_isGFX12Plus),
        GIM_CheckRegBankForClass, /*MI*/0, /*Op*/0, /*RC*/GIMT_Encode2(AMDGPU::VGPR_32RegClassID),
        GIM_CheckCxxInsnPredicate, /*MI*/0, /*FnId*/GIMT_Encode2(GICXXPred_MI_Predicate_anonymous_23222),
        GIM_CheckComplexPattern, /*MI*/0, /*Op*/1, /*Renderer*/GIMT_Encode2(0), GIMT_Encode2(GICP_gi_vop3mods),
        GIM_CheckComplexPattern, /*MI*/0, /*Op*/2, /*Renderer*/GIMT_Encode2(1), GIMT_Encode2(GICP_gi_vop3mods0),
        // (fmaximum:{ *:[f16] } (VOP3Mods:{ *:[f16] } f16:{ *:[f16] }:$src1, i32:{ *:[i32] }:$src1_modifiers), (VOP3Mods0:{ *:[f16] } f16:{ *:[f16] }:$src0, i32:{ *:[i32] }:$src0_modifiers, i1:{ *:[i1] }:$clamp, i32:{ *:[i32] }:$omod))<<P:Predicate_anonymous_23222>>  =>  (V_MAXIMUM_F16_e64:{ *:[f16] } i32:{ *:[i32] }:$src0_modifiers, f16:{ *:[f16] }:$src0, i32:{ *:[i32] }:$src1_modifiers, f16:{ *:[f16] }:$src1, i1:{ *:[i1] }:$clamp, i32:{ *:[i32] }:$omod)
        GIR_BuildMI, /*InsnID*/0, /*Opcode*/GIMT_Encode2(AMDGPU::V_MAXIMUM_F16_e64),
        GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/0, // DstI[vdst]
        GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(1), /*SubOperand*/1, // src0_modifiers
        GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(1), /*SubOperand*/0, // src0
        GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/1, // src1_modifiers
        GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/0, // src1
        GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(1), /*SubOperand*/2, // clamp
        GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(1), /*SubOperand*/3, // omod
        GIR_ConstrainSelectedInstOperands, /*InsnID*/0,
        GIR_EraseFromParent, /*InsnID*/0,
        // GIR_Coverage, 7189,
        GIR_Done,
      // Label 5230: @386440
      GIM_Reject,
    // Label 5225: @386441
    GIM_Reject,
    // Label 5221: @386442
    GIM_Try, /*On fail goto*//*Label 5231*/ GIMT_Encode4(386857),
      GIM_CheckType, /*MI*/0, /*Op*/1, /*Type*/GILLT_s32,
      GIM_CheckType, /*MI*/0, /*Op*/2, /*Type*/GILLT_s32,
      GIM_Try, /*On fail goto*//*Label 5232*/ GIMT_Encode4(386564), // Rule ID 10800 //
        GIM_CheckFeatures, GIMT_Encode2(GIFBS_isGFX12Plus),
        GIM_CheckRegBankForClass, /*MI*/0, /*Op*/0, /*RC*/GIMT_Encode2(AMDGPU::VGPR_32RegClassID),
        GIM_RecordInsn, /*DefineMI*/1, /*MI*/0, /*OpIdx*/2, // MIs[1]
        GIM_CheckOpcode, /*MI*/1, GIMT_Encode2(TargetOpcode::G_FMINIMUM),
        GIM_CheckType, /*MI*/1, /*Op*/1, /*Type*/GILLT_s32,
        GIM_CheckType, /*MI*/1, /*Op*/2, /*Type*/GILLT_s32,
        GIM_CheckCxxInsnPredicate, /*MI*/1, /*FnId*/GIMT_Encode2(GICXXPred_MI_Predicate_fminimum_oneuse),
        GIM_CheckCxxInsnPredicate, /*MI*/0, /*FnId*/GIMT_Encode2(GICXXPred_MI_Predicate_anonymous_23222),
        GIM_CheckIsSafeToFold, /*InsnID*/1,
        GIM_CheckComplexPattern, /*MI*/0, /*Op*/1, /*Renderer*/GIMT_Encode2(0), GIMT_Encode2(GICP_gi_vop3mods),
        GIM_CheckComplexPattern, /*MI*/1, /*Op*/1, /*Renderer*/GIMT_Encode2(1), GIMT_Encode2(GICP_gi_vop3mods),
        GIM_CheckComplexPattern, /*MI*/1, /*Op*/2, /*Renderer*/GIMT_Encode2(2), GIMT_Encode2(GICP_gi_vop3mods),
        // (fmaximum:{ *:[f32] } (VOP3Mods:{ *:[f32] } f32:{ *:[f32] }:$src2, i32:{ *:[i32] }:$src2_mods), (fminimum:{ *:[f32] } (VOP3Mods:{ *:[f32] } f32:{ *:[f32] }:$src0, i32:{ *:[i32] }:$src0_mods), (VOP3Mods:{ *:[f32] } f32:{ *:[f32] }:$src1, i32:{ *:[i32] }:$src1_mods))<<P:Predicate_fminimum_oneuse>>)<<P:Predicate_anonymous_23222>>  =>  (V_MINIMUMMAXIMUM_F32_e64:{ *:[f32] } ?:{ *:[i32] }:$src0_mods, ?:{ *:[f32] }:$src0, ?:{ *:[i32] }:$src1_mods, ?:{ *:[f32] }:$src1, ?:{ *:[i32] }:$src2_mods, ?:{ *:[f32] }:$src2, 0:{ *:[i1] }, 0:{ *:[i32] })
        GIR_BuildMI, /*InsnID*/0, /*Opcode*/GIMT_Encode2(AMDGPU::V_MINIMUMMAXIMUM_F32_e64),
        GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/0, // DstI[vdst]
        GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(1), /*SubOperand*/1, // src0_mods
        GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(1), /*SubOperand*/0, // src0
        GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(2), /*SubOperand*/1, // src1_mods
        GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(2), /*SubOperand*/0, // src1
        GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/1, // src2_mods
        GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/0, // src2
        GIR_AddImm8, /*InsnID*/0, /*Imm*/0,
        GIR_AddImm8, /*InsnID*/0, /*Imm*/0,
        GIR_ConstrainSelectedInstOperands, /*InsnID*/0,
        GIR_EraseFromParent, /*InsnID*/0,
        // GIR_Coverage, 10800,
        GIR_Done,
      // Label 5232: @386564
      GIM_Try, /*On fail goto*//*Label 5233*/ GIMT_Encode4(386673), // Rule ID 6554 //
        GIM_CheckFeatures, GIMT_Encode2(GIFBS_isGFX12Plus),
        GIM_CheckRegBankForClass, /*MI*/0, /*Op*/0, /*RC*/GIMT_Encode2(AMDGPU::VGPR_32RegClassID),
        GIM_RecordInsn, /*DefineMI*/1, /*MI*/0, /*OpIdx*/1, // MIs[1]
        GIM_CheckOpcode, /*MI*/1, GIMT_Encode2(TargetOpcode::G_FMINIMUM),
        GIM_CheckType, /*MI*/1, /*Op*/1, /*Type*/GILLT_s32,
        GIM_CheckType, /*MI*/1, /*Op*/2, /*Type*/GILLT_s32,
        GIM_CheckCxxInsnPredicate, /*MI*/1, /*FnId*/GIMT_Encode2(GICXXPred_MI_Predicate_fminimum_oneuse),
        GIM_CheckCxxInsnPredicate, /*MI*/0, /*FnId*/GIMT_Encode2(GICXXPred_MI_Predicate_anonymous_23222),
        GIM_CheckIsSafeToFold, /*InsnID*/1,
        GIM_CheckComplexPattern, /*MI*/0, /*Op*/2, /*Renderer*/GIMT_Encode2(2), GIMT_Encode2(GICP_gi_vop3mods),
        GIM_CheckComplexPattern, /*MI*/1, /*Op*/1, /*Renderer*/GIMT_Encode2(0), GIMT_Encode2(GICP_gi_vop3mods),
        GIM_CheckComplexPattern, /*MI*/1, /*Op*/2, /*Renderer*/GIMT_Encode2(1), GIMT_Encode2(GICP_gi_vop3mods),
        // (fmaximum:{ *:[f32] } (fminimum:{ *:[f32] } (VOP3Mods:{ *:[f32] } f32:{ *:[f32] }:$src0, i32:{ *:[i32] }:$src0_mods), (VOP3Mods:{ *:[f32] } f32:{ *:[f32] }:$src1, i32:{ *:[i32] }:$src1_mods))<<P:Predicate_fminimum_oneuse>>, (VOP3Mods:{ *:[f32] } f32:{ *:[f32] }:$src2, i32:{ *:[i32] }:$src2_mods))<<P:Predicate_anonymous_23222>>  =>  (V_MINIMUMMAXIMUM_F32_e64:{ *:[f32] } ?:{ *:[i32] }:$src0_mods, ?:{ *:[f32] }:$src0, ?:{ *:[i32] }:$src1_mods, ?:{ *:[f32] }:$src1, ?:{ *:[i32] }:$src2_mods, ?:{ *:[f32] }:$src2, 0:{ *:[i1] }, 0:{ *:[i32] })
        GIR_BuildMI, /*InsnID*/0, /*Opcode*/GIMT_Encode2(AMDGPU::V_MINIMUMMAXIMUM_F32_e64),
        GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/0, // DstI[vdst]
        GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/1, // src0_mods
        GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/0, // src0
        GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(1), /*SubOperand*/1, // src1_mods
        GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(1), /*SubOperand*/0, // src1
        GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(2), /*SubOperand*/1, // src2_mods
        GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(2), /*SubOperand*/0, // src2
        GIR_AddImm8, /*InsnID*/0, /*Imm*/0,
        GIR_AddImm8, /*InsnID*/0, /*Imm*/0,
        GIR_ConstrainSelectedInstOperands, /*InsnID*/0,
        GIR_EraseFromParent, /*InsnID*/0,
        // GIR_Coverage, 6554,
        GIR_Done,
      // Label 5233: @386673
      GIM_Try, /*On fail goto*//*Label 5234*/ GIMT_Encode4(386708), // Rule ID 117 //
        GIM_CheckFeatures, GIMT_Encode2(GIFBS_isGFX12Plus),
        GIM_CheckRegBankForClass, /*MI*/0, /*Op*/0, /*RC*/GIMT_Encode2(AMDGPU::SReg_32RegClassID),
        GIM_CheckRegBankForClass, /*MI*/0, /*Op*/1, /*RC*/GIMT_Encode2(AMDGPU::SReg_32RegClassID),
        GIM_CheckRegBankForClass, /*MI*/0, /*Op*/2, /*RC*/GIMT_Encode2(AMDGPU::SReg_32RegClassID),
        GIM_CheckCxxInsnPredicate, /*MI*/0, /*FnId*/GIMT_Encode2(GICXXPred_MI_Predicate_anonymous_17638),
        // (fmaximum:{ *:[f32] } SSrc_f32:{ *:[f32] }:$src0, SSrc_f32:{ *:[f32] }:$src1)<<P:Predicate_anonymous_17638>>  =>  (S_MAXIMUM_F32:{ *:[f32] } SSrc_f32:{ *:[f32] }:$src0, SSrc_f32:{ *:[f32] }:$src1)
        GIR_MutateOpcode, /*InsnID*/0, /*RecycleInsnID*/0, /*Opcode*/GIMT_Encode2(AMDGPU::S_MAXIMUM_F32),
        GIR_ConstrainSelectedInstOperands, /*InsnID*/0,
        // GIR_Coverage, 117,
        GIR_Done,
      // Label 5234: @386708
      GIM_Try, /*On fail goto*//*Label 5235*/ GIMT_Encode4(386782), // Rule ID 869 //
        GIM_CheckFeatures, GIMT_Encode2(GIFBS_isGFX12Plus),
        GIM_CheckRegBankForClass, /*MI*/0, /*Op*/0, /*RC*/GIMT_Encode2(AMDGPU::VGPR_32RegClassID),
        GIM_CheckCxxInsnPredicate, /*MI*/0, /*FnId*/GIMT_Encode2(GICXXPred_MI_Predicate_anonymous_23222),
        GIM_CheckComplexPattern, /*MI*/0, /*Op*/1, /*Renderer*/GIMT_Encode2(0), GIMT_Encode2(GICP_gi_vop3mods0),
        GIM_CheckComplexPattern, /*MI*/0, /*Op*/2, /*Renderer*/GIMT_Encode2(1), GIMT_Encode2(GICP_gi_vop3mods),
        // (fmaximum:{ *:[f32] } (VOP3Mods0:{ *:[f32] } f32:{ *:[f32] }:$src0, i32:{ *:[i32] }:$src0_modifiers, i1:{ *:[i1] }:$clamp, i32:{ *:[i32] }:$omod), (VOP3Mods:{ *:[f32] } f32:{ *:[f32] }:$src1, i32:{ *:[i32] }:$src1_modifiers))<<P:Predicate_anonymous_23222>>  =>  (V_MAXIMUM_F32_e64:{ *:[f32] } i32:{ *:[i32] }:$src0_modifiers, f32:{ *:[f32] }:$src0, i32:{ *:[i32] }:$src1_modifiers, f32:{ *:[f32] }:$src1, i1:{ *:[i1] }:$clamp, i32:{ *:[i32] }:$omod)
        GIR_BuildMI, /*InsnID*/0, /*Opcode*/GIMT_Encode2(AMDGPU::V_MAXIMUM_F32_e64),
        GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/0, // DstI[vdst]
        GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/1, // src0_modifiers
        GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/0, // src0
        GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(1), /*SubOperand*/1, // src1_modifiers
        GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(1), /*SubOperand*/0, // src1
        GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/2, // clamp
        GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/3, // omod
        GIR_ConstrainSelectedInstOperands, /*InsnID*/0,
        GIR_EraseFromParent, /*InsnID*/0,
        // GIR_Coverage, 869,
        GIR_Done,
      // Label 5235: @386782
      GIM_Try, /*On fail goto*//*Label 5236*/ GIMT_Encode4(386856), // Rule ID 7187 //
        GIM_CheckFeatures, GIMT_Encode2(GIFBS_isGFX12Plus),
        GIM_CheckRegBankForClass, /*MI*/0, /*Op*/0, /*RC*/GIMT_Encode2(AMDGPU::VGPR_32RegClassID),
        GIM_CheckCxxInsnPredicate, /*MI*/0, /*FnId*/GIMT_Encode2(GICXXPred_MI_Predicate_anonymous_23222),
        GIM_CheckComplexPattern, /*MI*/0, /*Op*/1, /*Renderer*/GIMT_Encode2(0), GIMT_Encode2(GICP_gi_vop3mods),
        GIM_CheckComplexPattern, /*MI*/0, /*Op*/2, /*Renderer*/GIMT_Encode2(1), GIMT_Encode2(GICP_gi_vop3mods0),
        // (fmaximum:{ *:[f32] } (VOP3Mods:{ *:[f32] } f32:{ *:[f32] }:$src1, i32:{ *:[i32] }:$src1_modifiers), (VOP3Mods0:{ *:[f32] } f32:{ *:[f32] }:$src0, i32:{ *:[i32] }:$src0_modifiers, i1:{ *:[i1] }:$clamp, i32:{ *:[i32] }:$omod))<<P:Predicate_anonymous_23222>>  =>  (V_MAXIMUM_F32_e64:{ *:[f32] } i32:{ *:[i32] }:$src0_modifiers, f32:{ *:[f32] }:$src0, i32:{ *:[i32] }:$src1_modifiers, f32:{ *:[f32] }:$src1, i1:{ *:[i1] }:$clamp, i32:{ *:[i32] }:$omod)
        GIR_BuildMI, /*InsnID*/0, /*Opcode*/GIMT_Encode2(AMDGPU::V_MAXIMUM_F32_e64),
        GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/0, // DstI[vdst]
        GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(1), /*SubOperand*/1, // src0_modifiers
        GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(1), /*SubOperand*/0, // src0
        GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/1, // src1_modifiers
        GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/0, // src1
        GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(1), /*SubOperand*/2, // clamp
        GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(1), /*SubOperand*/3, // omod
        GIR_ConstrainSelectedInstOperands, /*InsnID*/0,
        GIR_EraseFromParent, /*InsnID*/0,
        // GIR_Coverage, 7187,
        GIR_Done,
      // Label 5236: @386856
      GIM_Reject,
    // Label 5231: @386857
    GIM_Reject,
    // Label 5222: @386858
    GIM_Try, /*On fail goto*//*Label 5237*/ GIMT_Encode4(387007),
      GIM_CheckType, /*MI*/0, /*Op*/1, /*Type*/GILLT_s64,
      GIM_CheckType, /*MI*/0, /*Op*/2, /*Type*/GILLT_s64,
      GIM_CheckRegBankForClass, /*MI*/0, /*Op*/0, /*RC*/GIMT_Encode2(AMDGPU::VReg_64RegClassID),
      GIM_Try, /*On fail goto*//*Label 5238*/ GIMT_Encode4(386941), // Rule ID 873 //
        GIM_CheckFeatures, GIMT_Encode2(GIFBS_isGFX12Plus),
        GIM_CheckComplexPattern, /*MI*/0, /*Op*/1, /*Renderer*/GIMT_Encode2(0), GIMT_Encode2(GICP_gi_vop3mods0),
        GIM_CheckComplexPattern, /*MI*/0, /*Op*/2, /*Renderer*/GIMT_Encode2(1), GIMT_Encode2(GICP_gi_vop3mods),
        // (fmaximum:{ *:[f64] } (VOP3Mods0:{ *:[f64] } f64:{ *:[f64] }:$src0, i32:{ *:[i32] }:$src0_modifiers, i1:{ *:[i1] }:$clamp, i32:{ *:[i32] }:$omod), (VOP3Mods:{ *:[f64] } f64:{ *:[f64] }:$src1, i32:{ *:[i32] }:$src1_modifiers))  =>  (V_MAXIMUM_F64_e64:{ *:[f64] } i32:{ *:[i32] }:$src0_modifiers, f64:{ *:[f64] }:$src0, i32:{ *:[i32] }:$src1_modifiers, f64:{ *:[f64] }:$src1, i1:{ *:[i1] }:$clamp, i32:{ *:[i32] }:$omod)
        GIR_BuildMI, /*InsnID*/0, /*Opcode*/GIMT_Encode2(AMDGPU::V_MAXIMUM_F64_e64),
        GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/0, // DstI[vdst]
        GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/1, // src0_modifiers
        GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/0, // src0
        GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(1), /*SubOperand*/1, // src1_modifiers
        GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(1), /*SubOperand*/0, // src1
        GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/2, // clamp
        GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/3, // omod
        GIR_ConstrainSelectedInstOperands, /*InsnID*/0,
        GIR_EraseFromParent, /*InsnID*/0,
        // GIR_Coverage, 873,
        GIR_Done,
      // Label 5238: @386941
      GIM_Try, /*On fail goto*//*Label 5239*/ GIMT_Encode4(387006), // Rule ID 7191 //
        GIM_CheckFeatures, GIMT_Encode2(GIFBS_isGFX12Plus),
        GIM_CheckComplexPattern, /*MI*/0, /*Op*/1, /*Renderer*/GIMT_Encode2(0), GIMT_Encode2(GICP_gi_vop3mods),
        GIM_CheckComplexPattern, /*MI*/0, /*Op*/2, /*Renderer*/GIMT_Encode2(1), GIMT_Encode2(GICP_gi_vop3mods0),
        // (fmaximum:{ *:[f64] } (VOP3Mods:{ *:[f64] } f64:{ *:[f64] }:$src1, i32:{ *:[i32] }:$src1_modifiers), (VOP3Mods0:{ *:[f64] } f64:{ *:[f64] }:$src0, i32:{ *:[i32] }:$src0_modifiers, i1:{ *:[i1] }:$clamp, i32:{ *:[i32] }:$omod))  =>  (V_MAXIMUM_F64_e64:{ *:[f64] } i32:{ *:[i32] }:$src0_modifiers, f64:{ *:[f64] }:$src0, i32:{ *:[i32] }:$src1_modifiers, f64:{ *:[f64] }:$src1, i1:{ *:[i1] }:$clamp, i32:{ *:[i32] }:$omod)
        GIR_BuildMI, /*InsnID*/0, /*Opcode*/GIMT_Encode2(AMDGPU::V_MAXIMUM_F64_e64),
        GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/0, // DstI[vdst]
        GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(1), /*SubOperand*/1, // src0_modifiers
        GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(1), /*SubOperand*/0, // src0
        GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/1, // src1_modifiers
        GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/0, // src1
        GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(1), /*SubOperand*/2, // clamp
        GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(1), /*SubOperand*/3, // omod
        GIR_ConstrainSelectedInstOperands, /*InsnID*/0,
        GIR_EraseFromParent, /*InsnID*/0,
        // GIR_Coverage, 7191,
        GIR_Done,
      // Label 5239: @387006
      GIM_Reject,
    // Label 5237: @387007
    GIM_Reject,
    // Label 5223: @387008
    GIM_Try, /*On fail goto*//*Label 5240*/ GIMT_Encode4(387091), // Rule ID 974 //
      GIM_CheckFeatures, GIMT_Encode2(GIFBS_isGFX12Plus),
      GIM_CheckType, /*MI*/0, /*Op*/1, /*Type*/GILLT_v2s16,
      GIM_CheckType, /*MI*/0, /*Op*/2, /*Type*/GILLT_v2s16,
      GIM_CheckRegBankForClass, /*MI*/0, /*Op*/0, /*RC*/GIMT_Encode2(AMDGPU::VGPR_32RegClassID),
      GIM_CheckComplexPattern, /*MI*/0, /*Op*/1, /*Renderer*/GIMT_Encode2(0), GIMT_Encode2(GICP_gi_vop3pmods),
      GIM_CheckComplexPattern, /*MI*/0, /*Op*/2, /*Renderer*/GIMT_Encode2(1), GIMT_Encode2(GICP_gi_vop3pmods),
      // (fmaximum:{ *:[v2f16] } (VOP3PMods:{ *:[v2f16] } v2f16:{ *:[v2f16] }:$src0, i32:{ *:[i32] }:$src0_modifiers), (VOP3PMods:{ *:[v2f16] } v2f16:{ *:[v2f16] }:$src1, i32:{ *:[i32] }:$src1_modifiers))  =>  (V_PK_MAXIMUM_F16:{ *:[v2f16] } i32:{ *:[i32] }:$src0_modifiers, v2f16:{ *:[v2f16] }:$src0, i32:{ *:[i32] }:$src1_modifiers, v2f16:{ *:[v2f16] }:$src1)
      GIR_BuildMI, /*InsnID*/0, /*Opcode*/GIMT_Encode2(AMDGPU::V_PK_MAXIMUM_F16),
      GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/0, // DstI[vdst]
      GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/1, // src0_modifiers
      GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/0, // src0
      GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(1), /*SubOperand*/1, // src1_modifiers
      GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(1), /*SubOperand*/0, // src1
      GIR_AddImm8, /*InsnID*/0, /*Imm*/0,
      GIR_AddImm8, /*InsnID*/0, /*Imm*/0,
      GIR_AddImm8, /*InsnID*/0, /*Imm*/0,
      GIR_AddImm8, /*InsnID*/0, /*Imm*/0,
      GIR_AddImm8, /*InsnID*/0, /*Imm*/0,
      GIR_ConstrainSelectedInstOperands, /*InsnID*/0,
      GIR_EraseFromParent, /*InsnID*/0,
      // GIR_Coverage, 974,
      GIR_Done,
    // Label 5240: @387091
    GIM_Reject,
    // Label 5224: @387092
    GIM_Reject,
    // Label 82: @387093
    GIM_Try, /*On fail goto*//*Label 5241*/ GIMT_Encode4(387230),
      GIM_CheckType, /*MI*/0, /*Op*/0, /*Type*/GILLT_s32,
      GIM_CheckRegBankForClass, /*MI*/0, /*Op*/0, /*RC*/GIMT_Encode2(AMDGPU::SReg_32RegClassID),
      GIM_Try, /*On fail goto*//*Label 5242*/ GIMT_Encode4(387168), // Rule ID 1650 //
        GIM_CheckFeatures, GIMT_Encode2(GIFBS_isGFX9Plus),
        // (get_fpmode:{ *:[i32] })  =>  (S_AND_B32:{ *:[i32] }:{ *:[i1] } 8909823:{ *:[i32] }, (S_GETREG_B32:{ *:[i1] } 47105:{ *:[i32] }))
        GIR_MakeTempReg, /*TempRegID*/0, /*TypeID*/GILLT_s1,
        GIR_BuildMI, /*InsnID*/1, /*Opcode*/GIMT_Encode2(AMDGPU::S_GETREG_B32),
        GIR_AddTempRegister, /*InsnID*/1, /*TempRegID*/0, /*TempRegFlags*/GIMT_Encode2(RegState::Define),
        GIR_AddImm, /*InsnID*/1, /*Imm*/GIMT_Encode8(47105),
        GIR_ConstrainSelectedInstOperands, /*InsnID*/1,
        GIR_BuildMI, /*InsnID*/0, /*Opcode*/GIMT_Encode2(AMDGPU::S_AND_B32),
        GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/0, // DstI[sdst]
        GIR_AddImm, /*InsnID*/0, /*Imm*/GIMT_Encode8(8909823),
        GIR_AddSimpleTempRegister, /*InsnID*/0, /*TempRegID*/0,
        GIR_SetImplicitDefDead, /*InsnID*/0, /*OpIdx for AMDGPU::SCC*/0,
        GIR_ConstrainSelectedInstOperands, /*InsnID*/0,
        GIR_EraseFromParent, /*InsnID*/0,
        // GIR_Coverage, 1650,
        GIR_Done,
      // Label 5242: @387168
      GIM_Try, /*On fail goto*//*Label 5243*/ GIMT_Encode4(387229), // Rule ID 1651 //
        GIM_CheckFeatures, GIMT_Encode2(GIFBS_isNotGFX9Plus),
        // (get_fpmode:{ *:[i32] })  =>  (S_AND_B32:{ *:[i32] }:{ *:[i1] } 521215:{ *:[i32] }, (S_GETREG_B32:{ *:[i1] } 36865:{ *:[i32] }))
        GIR_MakeTempReg, /*TempRegID*/0, /*TypeID*/GILLT_s1,
        GIR_BuildMI, /*InsnID*/1, /*Opcode*/GIMT_Encode2(AMDGPU::S_GETREG_B32),
        GIR_AddTempRegister, /*InsnID*/1, /*TempRegID*/0, /*TempRegFlags*/GIMT_Encode2(RegState::Define),
        GIR_AddImm, /*InsnID*/1, /*Imm*/GIMT_Encode8(36865),
        GIR_ConstrainSelectedInstOperands, /*InsnID*/1,
        GIR_BuildMI, /*InsnID*/0, /*Opcode*/GIMT_Encode2(AMDGPU::S_AND_B32),
        GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/0, // DstI[sdst]
        GIR_AddImm, /*InsnID*/0, /*Imm*/GIMT_Encode8(521215),
        GIR_AddSimpleTempRegister, /*InsnID*/0, /*TempRegID*/0,
        GIR_SetImplicitDefDead, /*InsnID*/0, /*OpIdx for AMDGPU::SCC*/0,
        GIR_ConstrainSelectedInstOperands, /*InsnID*/0,
        GIR_EraseFromParent, /*InsnID*/0,
        // GIR_Coverage, 1651,
        GIR_Done,
      // Label 5243: @387229
      GIM_Reject,
    // Label 5241: @387230
    GIM_Reject,
    // Label 83: @387231
    GIM_Try, /*On fail goto*//*Label 5244*/ GIMT_Encode4(387319), // Rule ID 2189 //
      GIM_CheckFeatures, GIMT_Encode2(GIFBS_isGFX9Plus),
      GIM_CheckType, /*MI*/0, /*Op*/2, /*Type*/GILLT_s32,
      // MIs[0] DstI[vdst]
      GIM_CheckPointerToAny, /*MI*/0, /*Op*/0, /*SizeInBits*/32,
      GIM_CheckRegBankForClass, /*MI*/0, /*Op*/0, /*RC*/GIMT_Encode2(AMDGPU::VGPR_32RegClassID),
      // MIs[0] Operand 1
      GIM_CheckPointerToAny, /*MI*/0, /*Op*/1, /*SizeInBits*/32,
      GIM_RecordInsn, /*DefineMI*/1, /*MI*/0, /*OpIdx*/1, // MIs[1]
      GIM_CheckOpcode, /*MI*/1, GIMT_Encode2(TargetOpcode::G_PTR_ADD),
      GIM_CheckType, /*MI*/1, /*Op*/2, /*Type*/GILLT_s32,
      // MIs[1] src0
      GIM_CheckPointerToAny, /*MI*/1, /*Op*/1, /*SizeInBits*/32,
      GIM_RecordNamedOperand, /*MI*/1, /*Op*/1, /*StoreIdx*/0, // Name : pred:4:x
      GIM_RecordNamedOperand, /*MI*/1, /*Op*/2, /*StoreIdx*/1, // Name : pred:4:y
      GIM_CheckCxxInsnPredicate, /*MI*/1, /*FnId*/GIMT_Encode2(GICXXPred_MI_Predicate_anonymous_23611),
      GIM_RecordNamedOperand, /*MI*/0, /*Op*/2, /*StoreIdx*/2, // Name : pred:4:z
      GIM_CheckCxxInsnPredicate, /*MI*/0, /*FnId*/GIMT_Encode2(GICXXPred_MI_Predicate_anonymous_23610),
      GIM_CheckIsSafeToFold, /*InsnID*/1,
      // (ptradd:{ *:[i32] } (ptradd:{ *:[i32] } i32:{ *:[i32] }:$src0:$pred:4:x, i32:{ *:[i32] }:$src1:$pred:4:y)<<P:Predicate_anonymous_23611>>, i32:{ *:[i32] }:$src2:$pred:4:z)<<P:4:Predicate_anonymous_23610>>  =>  (V_ADD3_U32_e64:{ *:[i32] } VSrc_b32:{ *:[i32] }:$src0, VSrc_b32:{ *:[i32] }:$src1, VSrc_b32:{ *:[i32] }:$src2)
      GIR_BuildMI, /*InsnID*/0, /*Opcode*/GIMT_Encode2(AMDGPU::V_ADD3_U32_e64),
      GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/0, // DstI[vdst]
      GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/1, /*OpIdx*/1, // src0
      GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/1, /*OpIdx*/2, // src1
      GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/2, // src2
      GIR_ConstrainSelectedInstOperands, /*InsnID*/0,
      GIR_EraseFromParent, /*InsnID*/0,
      // GIR_Coverage, 2189,
      GIR_Done,
    // Label 5244: @387319
    GIM_Reject,
    // Label 84: @387320
    GIM_SwitchType, /*MI*/0, /*Op*/0, /*[*/GIMT_Encode2(8), GIMT_Encode2(12), /*)*//*default:*//*Label 5248*/ GIMT_Encode4(390801),
    /*GILLT_s16*//*Label 5245*/ GIMT_Encode4(387347),
    /*GILLT_s32*//*Label 5246*/ GIMT_Encode4(389071), GIMT_Encode4(0),
    /*GILLT_v2s16*//*Label 5247*/ GIMT_Encode4(390720),
    // Label 5245: @387347
    GIM_Try, /*On fail goto*//*Label 5249*/ GIMT_Encode4(389070),
      GIM_CheckType, /*MI*/0, /*Op*/1, /*Type*/GILLT_s16,
      GIM_CheckType, /*MI*/0, /*Op*/2, /*Type*/GILLT_s16,
      GIM_CheckRegBankForClass, /*MI*/0, /*Op*/0, /*RC*/GIMT_Encode2(AMDGPU::VGPR_32RegClassID),
      GIM_Try, /*On fail goto*//*Label 5250*/ GIMT_Encode4(387469), // Rule ID 10502 //
        GIM_CheckFeatures, GIMT_Encode2(GIFBS_isGFX9Plus),
        GIM_RecordInsn, /*DefineMI*/1, /*MI*/0, /*OpIdx*/1, // MIs[1]
        GIM_CheckOpcode, /*MI*/1, GIMT_Encode2(TargetOpcode::G_SMAX),
        GIM_CheckType, /*MI*/1, /*Op*/1, /*Type*/GILLT_s16,
        GIM_CheckType, /*MI*/1, /*Op*/2, /*Type*/GILLT_s16,
        GIM_RecordInsn, /*DefineMI*/2, /*MI*/1, /*OpIdx*/1, // MIs[2]
        GIM_CheckOpcode, /*MI*/2, GIMT_Encode2(TargetOpcode::G_SMIN),
        GIM_CheckType, /*MI*/2, /*Op*/1, /*Type*/GILLT_s16,
        GIM_CheckType, /*MI*/2, /*Op*/2, /*Type*/GILLT_s16,
        GIM_RecordInsn, /*DefineMI*/3, /*MI*/0, /*OpIdx*/2, // MIs[3]
        GIM_CheckOpcode, /*MI*/3, GIMT_Encode2(TargetOpcode::G_SMAX),
        // MIs[3] src0
        GIM_CheckIsSameOperand, /*MI*/3, /*OpIdx*/1, /*OtherMI*/2, /*OtherOpIdx*/1,
        // MIs[3] src1
        GIM_CheckIsSameOperand, /*MI*/3, /*OpIdx*/2, /*OtherMI*/2, /*OtherOpIdx*/2,
        GIM_CheckIsSafeToFold, /*InsnID*/1,
        GIM_CheckIsSafeToFold, /*InsnID*/2,
        GIM_CheckIsSafeToFold, /*InsnID*/3,
        // (smin:{ *:[i16] } (smax:{ *:[i16] } (smin:{ *:[i16] } i16:{ *:[i16] }:$src0, i16:{ *:[i16] }:$src1), i16:{ *:[i16] }:$src2), (smax:{ *:[i16] } i16:{ *:[i16] }:$src0, i16:{ *:[i16] }:$src1))  =>  (V_MED3_I16_e64:{ *:[i16] } 0:{ *:[i32] }, VSrc_b16:{ *:[i16] }:$src0, 0:{ *:[i32] }, VSrc_b16:{ *:[i16] }:$src1, 0:{ *:[i32] }, VSrc_b16:{ *:[i16] }:$src2, 0:{ *:[i1] })
        GIR_BuildMI, /*InsnID*/0, /*Opcode*/GIMT_Encode2(AMDGPU::V_MED3_I16_e64),
        GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/0, // DstI[vdst]
        GIR_AddImm8, /*InsnID*/0, /*Imm*/0,
        GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/2, /*OpIdx*/1, // src0
        GIR_AddImm8, /*InsnID*/0, /*Imm*/0,
        GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/2, /*OpIdx*/2, // src1
        GIR_AddImm8, /*InsnID*/0, /*Imm*/0,
        GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/1, /*OpIdx*/2, // src2
        GIR_AddImm8, /*InsnID*/0, /*Imm*/0,
        GIR_AddImm8, /*InsnID*/0, /*Imm*/0,
        GIR_ConstrainSelectedInstOperands, /*InsnID*/0,
        GIR_EraseFromParent, /*InsnID*/0,
        // GIR_Coverage, 10502,
        GIR_Done,
      // Label 5250: @387469
      GIM_Try, /*On fail goto*//*Label 5251*/ GIMT_Encode4(387573), // Rule ID 10503 //
        GIM_CheckFeatures, GIMT_Encode2(GIFBS_isGFX9Plus),
        GIM_RecordInsn, /*DefineMI*/1, /*MI*/0, /*OpIdx*/1, // MIs[1]
        GIM_CheckOpcode, /*MI*/1, GIMT_Encode2(TargetOpcode::G_SMAX),
        GIM_CheckType, /*MI*/1, /*Op*/1, /*Type*/GILLT_s16,
        GIM_CheckType, /*MI*/1, /*Op*/2, /*Type*/GILLT_s16,
        GIM_RecordInsn, /*DefineMI*/2, /*MI*/1, /*OpIdx*/1, // MIs[2]
        GIM_CheckOpcode, /*MI*/2, GIMT_Encode2(TargetOpcode::G_SMIN),
        GIM_CheckType, /*MI*/2, /*Op*/1, /*Type*/GILLT_s16,
        GIM_CheckType, /*MI*/2, /*Op*/2, /*Type*/GILLT_s16,
        GIM_RecordInsn, /*DefineMI*/3, /*MI*/0, /*OpIdx*/2, // MIs[3]
        GIM_CheckOpcode, /*MI*/3, GIMT_Encode2(TargetOpcode::G_SMAX),
        // MIs[3] src1
        GIM_CheckIsSameOperand, /*MI*/3, /*OpIdx*/1, /*OtherMI*/2, /*OtherOpIdx*/2,
        // MIs[3] src0
        GIM_CheckIsSameOperand, /*MI*/3, /*OpIdx*/2, /*OtherMI*/2, /*OtherOpIdx*/1,
        GIM_CheckIsSafeToFold, /*InsnID*/1,
        GIM_CheckIsSafeToFold, /*InsnID*/2,
        GIM_CheckIsSafeToFold, /*InsnID*/3,
        // (smin:{ *:[i16] } (smax:{ *:[i16] } (smin:{ *:[i16] } i16:{ *:[i16] }:$src0, i16:{ *:[i16] }:$src1), i16:{ *:[i16] }:$src2), (smax:{ *:[i16] } i16:{ *:[i16] }:$src1, i16:{ *:[i16] }:$src0))  =>  (V_MED3_I16_e64:{ *:[i16] } 0:{ *:[i32] }, VSrc_b16:{ *:[i16] }:$src0, 0:{ *:[i32] }, VSrc_b16:{ *:[i16] }:$src1, 0:{ *:[i32] }, VSrc_b16:{ *:[i16] }:$src2, 0:{ *:[i1] })
        GIR_BuildMI, /*InsnID*/0, /*Opcode*/GIMT_Encode2(AMDGPU::V_MED3_I16_e64),
        GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/0, // DstI[vdst]
        GIR_AddImm8, /*InsnID*/0, /*Imm*/0,
        GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/2, /*OpIdx*/1, // src0
        GIR_AddImm8, /*InsnID*/0, /*Imm*/0,
        GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/2, /*OpIdx*/2, // src1
        GIR_AddImm8, /*InsnID*/0, /*Imm*/0,
        GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/1, /*OpIdx*/2, // src2
        GIR_AddImm8, /*InsnID*/0, /*Imm*/0,
        GIR_AddImm8, /*InsnID*/0, /*Imm*/0,
        GIR_ConstrainSelectedInstOperands, /*InsnID*/0,
        GIR_EraseFromParent, /*InsnID*/0,
        // GIR_Coverage, 10503,
        GIR_Done,
      // Label 5251: @387573
      GIM_Try, /*On fail goto*//*Label 5252*/ GIMT_Encode4(387677), // Rule ID 10504 //
        GIM_CheckFeatures, GIMT_Encode2(GIFBS_isGFX9Plus),
        GIM_RecordInsn, /*DefineMI*/1, /*MI*/0, /*OpIdx*/1, // MIs[1]
        GIM_CheckOpcode, /*MI*/1, GIMT_Encode2(TargetOpcode::G_SMAX),
        GIM_CheckType, /*MI*/1, /*Op*/1, /*Type*/GILLT_s16,
        GIM_CheckType, /*MI*/1, /*Op*/2, /*Type*/GILLT_s16,
        GIM_RecordInsn, /*DefineMI*/2, /*MI*/1, /*OpIdx*/1, // MIs[2]
        GIM_CheckOpcode, /*MI*/2, GIMT_Encode2(TargetOpcode::G_SMIN),
        GIM_CheckType, /*MI*/2, /*Op*/1, /*Type*/GILLT_s16,
        GIM_CheckType, /*MI*/2, /*Op*/2, /*Type*/GILLT_s16,
        GIM_RecordInsn, /*DefineMI*/3, /*MI*/0, /*OpIdx*/2, // MIs[3]
        GIM_CheckOpcode, /*MI*/3, GIMT_Encode2(TargetOpcode::G_SMAX),
        // MIs[3] src0
        GIM_CheckIsSameOperand, /*MI*/3, /*OpIdx*/1, /*OtherMI*/2, /*OtherOpIdx*/2,
        // MIs[3] src1
        GIM_CheckIsSameOperand, /*MI*/3, /*OpIdx*/2, /*OtherMI*/2, /*OtherOpIdx*/1,
        GIM_CheckIsSafeToFold, /*InsnID*/1,
        GIM_CheckIsSafeToFold, /*InsnID*/2,
        GIM_CheckIsSafeToFold, /*InsnID*/3,
        // (smin:{ *:[i16] } (smax:{ *:[i16] } (smin:{ *:[i16] } i16:{ *:[i16] }:$src1, i16:{ *:[i16] }:$src0), i16:{ *:[i16] }:$src2), (smax:{ *:[i16] } i16:{ *:[i16] }:$src0, i16:{ *:[i16] }:$src1))  =>  (V_MED3_I16_e64:{ *:[i16] } 0:{ *:[i32] }, VSrc_b16:{ *:[i16] }:$src0, 0:{ *:[i32] }, VSrc_b16:{ *:[i16] }:$src1, 0:{ *:[i32] }, VSrc_b16:{ *:[i16] }:$src2, 0:{ *:[i1] })
        GIR_BuildMI, /*InsnID*/0, /*Opcode*/GIMT_Encode2(AMDGPU::V_MED3_I16_e64),
        GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/0, // DstI[vdst]
        GIR_AddImm8, /*InsnID*/0, /*Imm*/0,
        GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/2, /*OpIdx*/2, // src0
        GIR_AddImm8, /*InsnID*/0, /*Imm*/0,
        GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/2, /*OpIdx*/1, // src1
        GIR_AddImm8, /*InsnID*/0, /*Imm*/0,
        GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/1, /*OpIdx*/2, // src2
        GIR_AddImm8, /*InsnID*/0, /*Imm*/0,
        GIR_AddImm8, /*InsnID*/0, /*Imm*/0,
        GIR_ConstrainSelectedInstOperands, /*InsnID*/0,
        GIR_EraseFromParent, /*InsnID*/0,
        // GIR_Coverage, 10504,
        GIR_Done,
      // Label 5252: @387677
      GIM_Try, /*On fail goto*//*Label 5253*/ GIMT_Encode4(387781), // Rule ID 10505 //
        GIM_CheckFeatures, GIMT_Encode2(GIFBS_isGFX9Plus),
        GIM_RecordInsn, /*DefineMI*/1, /*MI*/0, /*OpIdx*/1, // MIs[1]
        GIM_CheckOpcode, /*MI*/1, GIMT_Encode2(TargetOpcode::G_SMAX),
        GIM_CheckType, /*MI*/1, /*Op*/1, /*Type*/GILLT_s16,
        GIM_CheckType, /*MI*/1, /*Op*/2, /*Type*/GILLT_s16,
        GIM_RecordInsn, /*DefineMI*/2, /*MI*/1, /*OpIdx*/1, // MIs[2]
        GIM_CheckOpcode, /*MI*/2, GIMT_Encode2(TargetOpcode::G_SMIN),
        GIM_CheckType, /*MI*/2, /*Op*/1, /*Type*/GILLT_s16,
        GIM_CheckType, /*MI*/2, /*Op*/2, /*Type*/GILLT_s16,
        GIM_RecordInsn, /*DefineMI*/3, /*MI*/0, /*OpIdx*/2, // MIs[3]
        GIM_CheckOpcode, /*MI*/3, GIMT_Encode2(TargetOpcode::G_SMAX),
        // MIs[3] src1
        GIM_CheckIsSameOperand, /*MI*/3, /*OpIdx*/1, /*OtherMI*/2, /*OtherOpIdx*/1,
        // MIs[3] src0
        GIM_CheckIsSameOperand, /*MI*/3, /*OpIdx*/2, /*OtherMI*/2, /*OtherOpIdx*/2,
        GIM_CheckIsSafeToFold, /*InsnID*/1,
        GIM_CheckIsSafeToFold, /*InsnID*/2,
        GIM_CheckIsSafeToFold, /*InsnID*/3,
        // (smin:{ *:[i16] } (smax:{ *:[i16] } (smin:{ *:[i16] } i16:{ *:[i16] }:$src1, i16:{ *:[i16] }:$src0), i16:{ *:[i16] }:$src2), (smax:{ *:[i16] } i16:{ *:[i16] }:$src1, i16:{ *:[i16] }:$src0))  =>  (V_MED3_I16_e64:{ *:[i16] } 0:{ *:[i32] }, VSrc_b16:{ *:[i16] }:$src0, 0:{ *:[i32] }, VSrc_b16:{ *:[i16] }:$src1, 0:{ *:[i32] }, VSrc_b16:{ *:[i16] }:$src2, 0:{ *:[i1] })
        GIR_BuildMI, /*InsnID*/0, /*Opcode*/GIMT_Encode2(AMDGPU::V_MED3_I16_e64),
        GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/0, // DstI[vdst]
        GIR_AddImm8, /*InsnID*/0, /*Imm*/0,
        GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/2, /*OpIdx*/2, // src0
        GIR_AddImm8, /*InsnID*/0, /*Imm*/0,
        GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/2, /*OpIdx*/1, // src1
        GIR_AddImm8, /*InsnID*/0, /*Imm*/0,
        GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/1, /*OpIdx*/2, // src2
        GIR_AddImm8, /*InsnID*/0, /*Imm*/0,
        GIR_AddImm8, /*InsnID*/0, /*Imm*/0,
        GIR_ConstrainSelectedInstOperands, /*InsnID*/0,
        GIR_EraseFromParent, /*InsnID*/0,
        // GIR_Coverage, 10505,
        GIR_Done,
      // Label 5253: @387781
      GIM_Try, /*On fail goto*//*Label 5254*/ GIMT_Encode4(387885), // Rule ID 10506 //
        GIM_CheckFeatures, GIMT_Encode2(GIFBS_isGFX9Plus),
        GIM_RecordInsn, /*DefineMI*/1, /*MI*/0, /*OpIdx*/1, // MIs[1]
        GIM_CheckOpcode, /*MI*/1, GIMT_Encode2(TargetOpcode::G_SMAX),
        GIM_CheckType, /*MI*/1, /*Op*/1, /*Type*/GILLT_s16,
        GIM_CheckType, /*MI*/1, /*Op*/2, /*Type*/GILLT_s16,
        GIM_RecordInsn, /*DefineMI*/2, /*MI*/1, /*OpIdx*/2, // MIs[2]
        GIM_CheckOpcode, /*MI*/2, GIMT_Encode2(TargetOpcode::G_SMIN),
        GIM_CheckType, /*MI*/2, /*Op*/1, /*Type*/GILLT_s16,
        GIM_CheckType, /*MI*/2, /*Op*/2, /*Type*/GILLT_s16,
        GIM_RecordInsn, /*DefineMI*/3, /*MI*/0, /*OpIdx*/2, // MIs[3]
        GIM_CheckOpcode, /*MI*/3, GIMT_Encode2(TargetOpcode::G_SMAX),
        // MIs[3] src0
        GIM_CheckIsSameOperand, /*MI*/3, /*OpIdx*/1, /*OtherMI*/2, /*OtherOpIdx*/1,
        // MIs[3] src1
        GIM_CheckIsSameOperand, /*MI*/3, /*OpIdx*/2, /*OtherMI*/2, /*OtherOpIdx*/2,
        GIM_CheckIsSafeToFold, /*InsnID*/1,
        GIM_CheckIsSafeToFold, /*InsnID*/2,
        GIM_CheckIsSafeToFold, /*InsnID*/3,
        // (smin:{ *:[i16] } (smax:{ *:[i16] } i16:{ *:[i16] }:$src2, (smin:{ *:[i16] } i16:{ *:[i16] }:$src0, i16:{ *:[i16] }:$src1)), (smax:{ *:[i16] } i16:{ *:[i16] }:$src0, i16:{ *:[i16] }:$src1))  =>  (V_MED3_I16_e64:{ *:[i16] } 0:{ *:[i32] }, VSrc_b16:{ *:[i16] }:$src0, 0:{ *:[i32] }, VSrc_b16:{ *:[i16] }:$src1, 0:{ *:[i32] }, VSrc_b16:{ *:[i16] }:$src2, 0:{ *:[i1] })
        GIR_BuildMI, /*InsnID*/0, /*Opcode*/GIMT_Encode2(AMDGPU::V_MED3_I16_e64),
        GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/0, // DstI[vdst]
        GIR_AddImm8, /*InsnID*/0, /*Imm*/0,
        GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/2, /*OpIdx*/1, // src0
        GIR_AddImm8, /*InsnID*/0, /*Imm*/0,
        GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/2, /*OpIdx*/2, // src1
        GIR_AddImm8, /*InsnID*/0, /*Imm*/0,
        GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/1, /*OpIdx*/1, // src2
        GIR_AddImm8, /*InsnID*/0, /*Imm*/0,
        GIR_AddImm8, /*InsnID*/0, /*Imm*/0,
        GIR_ConstrainSelectedInstOperands, /*InsnID*/0,
        GIR_EraseFromParent, /*InsnID*/0,
        // GIR_Coverage, 10506,
        GIR_Done,
      // Label 5254: @387885
      GIM_Try, /*On fail goto*//*Label 5255*/ GIMT_Encode4(387989), // Rule ID 10507 //
        GIM_CheckFeatures, GIMT_Encode2(GIFBS_isGFX9Plus),
        GIM_RecordInsn, /*DefineMI*/1, /*MI*/0, /*OpIdx*/1, // MIs[1]
        GIM_CheckOpcode, /*MI*/1, GIMT_Encode2(TargetOpcode::G_SMAX),
        GIM_CheckType, /*MI*/1, /*Op*/1, /*Type*/GILLT_s16,
        GIM_CheckType, /*MI*/1, /*Op*/2, /*Type*/GILLT_s16,
        GIM_RecordInsn, /*DefineMI*/2, /*MI*/1, /*OpIdx*/2, // MIs[2]
        GIM_CheckOpcode, /*MI*/2, GIMT_Encode2(TargetOpcode::G_SMIN),
        GIM_CheckType, /*MI*/2, /*Op*/1, /*Type*/GILLT_s16,
        GIM_CheckType, /*MI*/2, /*Op*/2, /*Type*/GILLT_s16,
        GIM_RecordInsn, /*DefineMI*/3, /*MI*/0, /*OpIdx*/2, // MIs[3]
        GIM_CheckOpcode, /*MI*/3, GIMT_Encode2(TargetOpcode::G_SMAX),
        // MIs[3] src1
        GIM_CheckIsSameOperand, /*MI*/3, /*OpIdx*/1, /*OtherMI*/2, /*OtherOpIdx*/2,
        // MIs[3] src0
        GIM_CheckIsSameOperand, /*MI*/3, /*OpIdx*/2, /*OtherMI*/2, /*OtherOpIdx*/1,
        GIM_CheckIsSafeToFold, /*InsnID*/1,
        GIM_CheckIsSafeToFold, /*InsnID*/2,
        GIM_CheckIsSafeToFold, /*InsnID*/3,
        // (smin:{ *:[i16] } (smax:{ *:[i16] } i16:{ *:[i16] }:$src2, (smin:{ *:[i16] } i16:{ *:[i16] }:$src0, i16:{ *:[i16] }:$src1)), (smax:{ *:[i16] } i16:{ *:[i16] }:$src1, i16:{ *:[i16] }:$src0))  =>  (V_MED3_I16_e64:{ *:[i16] } 0:{ *:[i32] }, VSrc_b16:{ *:[i16] }:$src0, 0:{ *:[i32] }, VSrc_b16:{ *:[i16] }:$src1, 0:{ *:[i32] }, VSrc_b16:{ *:[i16] }:$src2, 0:{ *:[i1] })
        GIR_BuildMI, /*InsnID*/0, /*Opcode*/GIMT_Encode2(AMDGPU::V_MED3_I16_e64),
        GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/0, // DstI[vdst]
        GIR_AddImm8, /*InsnID*/0, /*Imm*/0,
        GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/2, /*OpIdx*/1, // src0
        GIR_AddImm8, /*InsnID*/0, /*Imm*/0,
        GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/2, /*OpIdx*/2, // src1
        GIR_AddImm8, /*InsnID*/0, /*Imm*/0,
        GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/1, /*OpIdx*/1, // src2
        GIR_AddImm8, /*InsnID*/0, /*Imm*/0,
        GIR_AddImm8, /*InsnID*/0, /*Imm*/0,
        GIR_ConstrainSelectedInstOperands, /*InsnID*/0,
        GIR_EraseFromParent, /*InsnID*/0,
        // GIR_Coverage, 10507,
        GIR_Done,
      // Label 5255: @387989
      GIM_Try, /*On fail goto*//*Label 5256*/ GIMT_Encode4(388093), // Rule ID 10508 //
        GIM_CheckFeatures, GIMT_Encode2(GIFBS_isGFX9Plus),
        GIM_RecordInsn, /*DefineMI*/1, /*MI*/0, /*OpIdx*/1, // MIs[1]
        GIM_CheckOpcode, /*MI*/1, GIMT_Encode2(TargetOpcode::G_SMAX),
        GIM_CheckType, /*MI*/1, /*Op*/1, /*Type*/GILLT_s16,
        GIM_CheckType, /*MI*/1, /*Op*/2, /*Type*/GILLT_s16,
        GIM_RecordInsn, /*DefineMI*/2, /*MI*/1, /*OpIdx*/2, // MIs[2]
        GIM_CheckOpcode, /*MI*/2, GIMT_Encode2(TargetOpcode::G_SMIN),
        GIM_CheckType, /*MI*/2, /*Op*/1, /*Type*/GILLT_s16,
        GIM_CheckType, /*MI*/2, /*Op*/2, /*Type*/GILLT_s16,
        GIM_RecordInsn, /*DefineMI*/3, /*MI*/0, /*OpIdx*/2, // MIs[3]
        GIM_CheckOpcode, /*MI*/3, GIMT_Encode2(TargetOpcode::G_SMAX),
        // MIs[3] src0
        GIM_CheckIsSameOperand, /*MI*/3, /*OpIdx*/1, /*OtherMI*/2, /*OtherOpIdx*/2,
        // MIs[3] src1
        GIM_CheckIsSameOperand, /*MI*/3, /*OpIdx*/2, /*OtherMI*/2, /*OtherOpIdx*/1,
        GIM_CheckIsSafeToFold, /*InsnID*/1,
        GIM_CheckIsSafeToFold, /*InsnID*/2,
        GIM_CheckIsSafeToFold, /*InsnID*/3,
        // (smin:{ *:[i16] } (smax:{ *:[i16] } i16:{ *:[i16] }:$src2, (smin:{ *:[i16] } i16:{ *:[i16] }:$src1, i16:{ *:[i16] }:$src0)), (smax:{ *:[i16] } i16:{ *:[i16] }:$src0, i16:{ *:[i16] }:$src1))  =>  (V_MED3_I16_e64:{ *:[i16] } 0:{ *:[i32] }, VSrc_b16:{ *:[i16] }:$src0, 0:{ *:[i32] }, VSrc_b16:{ *:[i16] }:$src1, 0:{ *:[i32] }, VSrc_b16:{ *:[i16] }:$src2, 0:{ *:[i1] })
        GIR_BuildMI, /*InsnID*/0, /*Opcode*/GIMT_Encode2(AMDGPU::V_MED3_I16_e64),
        GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/0, // DstI[vdst]
        GIR_AddImm8, /*InsnID*/0, /*Imm*/0,
        GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/2, /*OpIdx*/2, // src0
        GIR_AddImm8, /*InsnID*/0, /*Imm*/0,
        GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/2, /*OpIdx*/1, // src1
        GIR_AddImm8, /*InsnID*/0, /*Imm*/0,
        GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/1, /*OpIdx*/1, // src2
        GIR_AddImm8, /*InsnID*/0, /*Imm*/0,
        GIR_AddImm8, /*InsnID*/0, /*Imm*/0,
        GIR_ConstrainSelectedInstOperands, /*InsnID*/0,
        GIR_EraseFromParent, /*InsnID*/0,
        // GIR_Coverage, 10508,
        GIR_Done,
      // Label 5256: @388093
      GIM_Try, /*On fail goto*//*Label 5257*/ GIMT_Encode4(388197), // Rule ID 10509 //
        GIM_CheckFeatures, GIMT_Encode2(GIFBS_isGFX9Plus),
        GIM_RecordInsn, /*DefineMI*/1, /*MI*/0, /*OpIdx*/1, // MIs[1]
        GIM_CheckOpcode, /*MI*/1, GIMT_Encode2(TargetOpcode::G_SMAX),
        GIM_CheckType, /*MI*/1, /*Op*/1, /*Type*/GILLT_s16,
        GIM_CheckType, /*MI*/1, /*Op*/2, /*Type*/GILLT_s16,
        GIM_RecordInsn, /*DefineMI*/2, /*MI*/1, /*OpIdx*/2, // MIs[2]
        GIM_CheckOpcode, /*MI*/2, GIMT_Encode2(TargetOpcode::G_SMIN),
        GIM_CheckType, /*MI*/2, /*Op*/1, /*Type*/GILLT_s16,
        GIM_CheckType, /*MI*/2, /*Op*/2, /*Type*/GILLT_s16,
        GIM_RecordInsn, /*DefineMI*/3, /*MI*/0, /*OpIdx*/2, // MIs[3]
        GIM_CheckOpcode, /*MI*/3, GIMT_Encode2(TargetOpcode::G_SMAX),
        // MIs[3] src1
        GIM_CheckIsSameOperand, /*MI*/3, /*OpIdx*/1, /*OtherMI*/2, /*OtherOpIdx*/1,
        // MIs[3] src0
        GIM_CheckIsSameOperand, /*MI*/3, /*OpIdx*/2, /*OtherMI*/2, /*OtherOpIdx*/2,
        GIM_CheckIsSafeToFold, /*InsnID*/1,
        GIM_CheckIsSafeToFold, /*InsnID*/2,
        GIM_CheckIsSafeToFold, /*InsnID*/3,
        // (smin:{ *:[i16] } (smax:{ *:[i16] } i16:{ *:[i16] }:$src2, (smin:{ *:[i16] } i16:{ *:[i16] }:$src1, i16:{ *:[i16] }:$src0)), (smax:{ *:[i16] } i16:{ *:[i16] }:$src1, i16:{ *:[i16] }:$src0))  =>  (V_MED3_I16_e64:{ *:[i16] } 0:{ *:[i32] }, VSrc_b16:{ *:[i16] }:$src0, 0:{ *:[i32] }, VSrc_b16:{ *:[i16] }:$src1, 0:{ *:[i32] }, VSrc_b16:{ *:[i16] }:$src2, 0:{ *:[i1] })
        GIR_BuildMI, /*InsnID*/0, /*Opcode*/GIMT_Encode2(AMDGPU::V_MED3_I16_e64),
        GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/0, // DstI[vdst]
        GIR_AddImm8, /*InsnID*/0, /*Imm*/0,
        GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/2, /*OpIdx*/2, // src0
        GIR_AddImm8, /*InsnID*/0, /*Imm*/0,
        GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/2, /*OpIdx*/1, // src1
        GIR_AddImm8, /*InsnID*/0, /*Imm*/0,
        GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/1, /*OpIdx*/1, // src2
        GIR_AddImm8, /*InsnID*/0, /*Imm*/0,
        GIR_AddImm8, /*InsnID*/0, /*Imm*/0,
        GIR_ConstrainSelectedInstOperands, /*InsnID*/0,
        GIR_EraseFromParent, /*InsnID*/0,
        // GIR_Coverage, 10509,
        GIR_Done,
      // Label 5257: @388197
      GIM_Try, /*On fail goto*//*Label 5258*/ GIMT_Encode4(388301), // Rule ID 6515 //
        GIM_CheckFeatures, GIMT_Encode2(GIFBS_isGFX9Plus),
        GIM_RecordInsn, /*DefineMI*/1, /*MI*/0, /*OpIdx*/1, // MIs[1]
        GIM_CheckOpcode, /*MI*/1, GIMT_Encode2(TargetOpcode::G_SMAX),
        GIM_CheckType, /*MI*/1, /*Op*/1, /*Type*/GILLT_s16,
        GIM_CheckType, /*MI*/1, /*Op*/2, /*Type*/GILLT_s16,
        GIM_RecordInsn, /*DefineMI*/2, /*MI*/0, /*OpIdx*/2, // MIs[2]
        GIM_CheckOpcode, /*MI*/2, GIMT_Encode2(TargetOpcode::G_SMAX),
        GIM_CheckType, /*MI*/2, /*Op*/1, /*Type*/GILLT_s16,
        GIM_CheckType, /*MI*/2, /*Op*/2, /*Type*/GILLT_s16,
        GIM_RecordInsn, /*DefineMI*/3, /*MI*/2, /*OpIdx*/1, // MIs[3]
        GIM_CheckOpcode, /*MI*/3, GIMT_Encode2(TargetOpcode::G_SMIN),
        // MIs[3] src0
        GIM_CheckIsSameOperand, /*MI*/3, /*OpIdx*/1, /*OtherMI*/1, /*OtherOpIdx*/1,
        // MIs[3] src1
        GIM_CheckIsSameOperand, /*MI*/3, /*OpIdx*/2, /*OtherMI*/1, /*OtherOpIdx*/2,
        GIM_CheckIsSafeToFold, /*InsnID*/1,
        GIM_CheckIsSafeToFold, /*InsnID*/2,
        GIM_CheckIsSafeToFold, /*InsnID*/3,
        // (smin:{ *:[i16] } (smax:{ *:[i16] } i16:{ *:[i16] }:$src0, i16:{ *:[i16] }:$src1), (smax:{ *:[i16] } (smin:{ *:[i16] } i16:{ *:[i16] }:$src0, i16:{ *:[i16] }:$src1), i16:{ *:[i16] }:$src2))  =>  (V_MED3_I16_e64:{ *:[i16] } 0:{ *:[i32] }, VSrc_b16:{ *:[i16] }:$src0, 0:{ *:[i32] }, VSrc_b16:{ *:[i16] }:$src1, 0:{ *:[i32] }, VSrc_b16:{ *:[i16] }:$src2, 0:{ *:[i1] })
        GIR_BuildMI, /*InsnID*/0, /*Opcode*/GIMT_Encode2(AMDGPU::V_MED3_I16_e64),
        GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/0, // DstI[vdst]
        GIR_AddImm8, /*InsnID*/0, /*Imm*/0,
        GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/1, /*OpIdx*/1, // src0
        GIR_AddImm8, /*InsnID*/0, /*Imm*/0,
        GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/1, /*OpIdx*/2, // src1
        GIR_AddImm8, /*InsnID*/0, /*Imm*/0,
        GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/2, /*OpIdx*/2, // src2
        GIR_AddImm8, /*InsnID*/0, /*Imm*/0,
        GIR_AddImm8, /*InsnID*/0, /*Imm*/0,
        GIR_ConstrainSelectedInstOperands, /*InsnID*/0,
        GIR_EraseFromParent, /*InsnID*/0,
        // GIR_Coverage, 6515,
        GIR_Done,
      // Label 5258: @388301
      GIM_Try, /*On fail goto*//*Label 5259*/ GIMT_Encode4(388405), // Rule ID 10495 //
        GIM_CheckFeatures, GIMT_Encode2(GIFBS_isGFX9Plus),
        GIM_RecordInsn, /*DefineMI*/1, /*MI*/0, /*OpIdx*/1, // MIs[1]
        GIM_CheckOpcode, /*MI*/1, GIMT_Encode2(TargetOpcode::G_SMAX),
        GIM_CheckType, /*MI*/1, /*Op*/1, /*Type*/GILLT_s16,
        GIM_CheckType, /*MI*/1, /*Op*/2, /*Type*/GILLT_s16,
        GIM_RecordInsn, /*DefineMI*/2, /*MI*/0, /*OpIdx*/2, // MIs[2]
        GIM_CheckOpcode, /*MI*/2, GIMT_Encode2(TargetOpcode::G_SMAX),
        GIM_CheckType, /*MI*/2, /*Op*/1, /*Type*/GILLT_s16,
        GIM_CheckType, /*MI*/2, /*Op*/2, /*Type*/GILLT_s16,
        GIM_RecordInsn, /*DefineMI*/3, /*MI*/2, /*OpIdx*/1, // MIs[3]
        GIM_CheckOpcode, /*MI*/3, GIMT_Encode2(TargetOpcode::G_SMIN),
        // MIs[3] src1
        GIM_CheckIsSameOperand, /*MI*/3, /*OpIdx*/1, /*OtherMI*/1, /*OtherOpIdx*/2,
        // MIs[3] src0
        GIM_CheckIsSameOperand, /*MI*/3, /*OpIdx*/2, /*OtherMI*/1, /*OtherOpIdx*/1,
        GIM_CheckIsSafeToFold, /*InsnID*/1,
        GIM_CheckIsSafeToFold, /*InsnID*/2,
        GIM_CheckIsSafeToFold, /*InsnID*/3,
        // (smin:{ *:[i16] } (smax:{ *:[i16] } i16:{ *:[i16] }:$src0, i16:{ *:[i16] }:$src1), (smax:{ *:[i16] } (smin:{ *:[i16] } i16:{ *:[i16] }:$src1, i16:{ *:[i16] }:$src0), i16:{ *:[i16] }:$src2))  =>  (V_MED3_I16_e64:{ *:[i16] } 0:{ *:[i32] }, VSrc_b16:{ *:[i16] }:$src0, 0:{ *:[i32] }, VSrc_b16:{ *:[i16] }:$src1, 0:{ *:[i32] }, VSrc_b16:{ *:[i16] }:$src2, 0:{ *:[i1] })
        GIR_BuildMI, /*InsnID*/0, /*Opcode*/GIMT_Encode2(AMDGPU::V_MED3_I16_e64),
        GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/0, // DstI[vdst]
        GIR_AddImm8, /*InsnID*/0, /*Imm*/0,
        GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/1, /*OpIdx*/1, // src0
        GIR_AddImm8, /*InsnID*/0, /*Imm*/0,
        GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/1, /*OpIdx*/2, // src1
        GIR_AddImm8, /*InsnID*/0, /*Imm*/0,
        GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/2, /*OpIdx*/2, // src2
        GIR_AddImm8, /*InsnID*/0, /*Imm*/0,
        GIR_AddImm8, /*InsnID*/0, /*Imm*/0,
        GIR_ConstrainSelectedInstOperands, /*InsnID*/0,
        GIR_EraseFromParent, /*InsnID*/0,
        // GIR_Coverage, 10495,
        GIR_Done,
      // Label 5259: @388405
      GIM_Try, /*On fail goto*//*Label 5260*/ GIMT_Encode4(388509), // Rule ID 10498 //
        GIM_CheckFeatures, GIMT_Encode2(GIFBS_isGFX9Plus),
        GIM_RecordInsn, /*DefineMI*/1, /*MI*/0, /*OpIdx*/1, // MIs[1]
        GIM_CheckOpcode, /*MI*/1, GIMT_Encode2(TargetOpcode::G_SMAX),
        GIM_CheckType, /*MI*/1, /*Op*/1, /*Type*/GILLT_s16,
        GIM_CheckType, /*MI*/1, /*Op*/2, /*Type*/GILLT_s16,
        GIM_RecordInsn, /*DefineMI*/2, /*MI*/0, /*OpIdx*/2, // MIs[2]
        GIM_CheckOpcode, /*MI*/2, GIMT_Encode2(TargetOpcode::G_SMAX),
        GIM_CheckType, /*MI*/2, /*Op*/1, /*Type*/GILLT_s16,
        GIM_CheckType, /*MI*/2, /*Op*/2, /*Type*/GILLT_s16,
        GIM_RecordInsn, /*DefineMI*/3, /*MI*/2, /*OpIdx*/1, // MIs[3]
        GIM_CheckOpcode, /*MI*/3, GIMT_Encode2(TargetOpcode::G_SMIN),
        // MIs[3] src0
        GIM_CheckIsSameOperand, /*MI*/3, /*OpIdx*/1, /*OtherMI*/1, /*OtherOpIdx*/2,
        // MIs[3] src1
        GIM_CheckIsSameOperand, /*MI*/3, /*OpIdx*/2, /*OtherMI*/1, /*OtherOpIdx*/1,
        GIM_CheckIsSafeToFold, /*InsnID*/1,
        GIM_CheckIsSafeToFold, /*InsnID*/2,
        GIM_CheckIsSafeToFold, /*InsnID*/3,
        // (smin:{ *:[i16] } (smax:{ *:[i16] } i16:{ *:[i16] }:$src1, i16:{ *:[i16] }:$src0), (smax:{ *:[i16] } (smin:{ *:[i16] } i16:{ *:[i16] }:$src0, i16:{ *:[i16] }:$src1), i16:{ *:[i16] }:$src2))  =>  (V_MED3_I16_e64:{ *:[i16] } 0:{ *:[i32] }, VSrc_b16:{ *:[i16] }:$src0, 0:{ *:[i32] }, VSrc_b16:{ *:[i16] }:$src1, 0:{ *:[i32] }, VSrc_b16:{ *:[i16] }:$src2, 0:{ *:[i1] })
        GIR_BuildMI, /*InsnID*/0, /*Opcode*/GIMT_Encode2(AMDGPU::V_MED3_I16_e64),
        GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/0, // DstI[vdst]
        GIR_AddImm8, /*InsnID*/0, /*Imm*/0,
        GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/1, /*OpIdx*/2, // src0
        GIR_AddImm8, /*InsnID*/0, /*Imm*/0,
        GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/1, /*OpIdx*/1, // src1
        GIR_AddImm8, /*InsnID*/0, /*Imm*/0,
        GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/2, /*OpIdx*/2, // src2
        GIR_AddImm8, /*InsnID*/0, /*Imm*/0,
        GIR_AddImm8, /*InsnID*/0, /*Imm*/0,
        GIR_ConstrainSelectedInstOperands, /*InsnID*/0,
        GIR_EraseFromParent, /*InsnID*/0,
        // GIR_Coverage, 10498,
        GIR_Done,
      // Label 5260: @388509
      GIM_Try, /*On fail goto*//*Label 5261*/ GIMT_Encode4(388613), // Rule ID 10499 //
        GIM_CheckFeatures, GIMT_Encode2(GIFBS_isGFX9Plus),
        GIM_RecordInsn, /*DefineMI*/1, /*MI*/0, /*OpIdx*/1, // MIs[1]
        GIM_CheckOpcode, /*MI*/1, GIMT_Encode2(TargetOpcode::G_SMAX),
        GIM_CheckType, /*MI*/1, /*Op*/1, /*Type*/GILLT_s16,
        GIM_CheckType, /*MI*/1, /*Op*/2, /*Type*/GILLT_s16,
        GIM_RecordInsn, /*DefineMI*/2, /*MI*/0, /*OpIdx*/2, // MIs[2]
        GIM_CheckOpcode, /*MI*/2, GIMT_Encode2(TargetOpcode::G_SMAX),
        GIM_CheckType, /*MI*/2, /*Op*/1, /*Type*/GILLT_s16,
        GIM_CheckType, /*MI*/2, /*Op*/2, /*Type*/GILLT_s16,
        GIM_RecordInsn, /*DefineMI*/3, /*MI*/2, /*OpIdx*/1, // MIs[3]
        GIM_CheckOpcode, /*MI*/3, GIMT_Encode2(TargetOpcode::G_SMIN),
        // MIs[3] src1
        GIM_CheckIsSameOperand, /*MI*/3, /*OpIdx*/1, /*OtherMI*/1, /*OtherOpIdx*/1,
        // MIs[3] src0
        GIM_CheckIsSameOperand, /*MI*/3, /*OpIdx*/2, /*OtherMI*/1, /*OtherOpIdx*/2,
        GIM_CheckIsSafeToFold, /*InsnID*/1,
        GIM_CheckIsSafeToFold, /*InsnID*/2,
        GIM_CheckIsSafeToFold, /*InsnID*/3,
        // (smin:{ *:[i16] } (smax:{ *:[i16] } i16:{ *:[i16] }:$src1, i16:{ *:[i16] }:$src0), (smax:{ *:[i16] } (smin:{ *:[i16] } i16:{ *:[i16] }:$src1, i16:{ *:[i16] }:$src0), i16:{ *:[i16] }:$src2))  =>  (V_MED3_I16_e64:{ *:[i16] } 0:{ *:[i32] }, VSrc_b16:{ *:[i16] }:$src0, 0:{ *:[i32] }, VSrc_b16:{ *:[i16] }:$src1, 0:{ *:[i32] }, VSrc_b16:{ *:[i16] }:$src2, 0:{ *:[i1] })
        GIR_BuildMI, /*InsnID*/0, /*Opcode*/GIMT_Encode2(AMDGPU::V_MED3_I16_e64),
        GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/0, // DstI[vdst]
        GIR_AddImm8, /*InsnID*/0, /*Imm*/0,
        GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/1, /*OpIdx*/2, // src0
        GIR_AddImm8, /*InsnID*/0, /*Imm*/0,
        GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/1, /*OpIdx*/1, // src1
        GIR_AddImm8, /*InsnID*/0, /*Imm*/0,
        GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/2, /*OpIdx*/2, // src2
        GIR_AddImm8, /*InsnID*/0, /*Imm*/0,
        GIR_AddImm8, /*InsnID*/0, /*Imm*/0,
        GIR_ConstrainSelectedInstOperands, /*InsnID*/0,
        GIR_EraseFromParent, /*InsnID*/0,
        // GIR_Coverage, 10499,
        GIR_Done,
      // Label 5261: @388613
      GIM_Try, /*On fail goto*//*Label 5262*/ GIMT_Encode4(388717), // Rule ID 10496 //
        GIM_CheckFeatures, GIMT_Encode2(GIFBS_isGFX9Plus),
        GIM_RecordInsn, /*DefineMI*/1, /*MI*/0, /*OpIdx*/1, // MIs[1]
        GIM_CheckOpcode, /*MI*/1, GIMT_Encode2(TargetOpcode::G_SMAX),
        GIM_CheckType, /*MI*/1, /*Op*/1, /*Type*/GILLT_s16,
        GIM_CheckType, /*MI*/1, /*Op*/2, /*Type*/GILLT_s16,
        GIM_RecordInsn, /*DefineMI*/2, /*MI*/0, /*OpIdx*/2, // MIs[2]
        GIM_CheckOpcode, /*MI*/2, GIMT_Encode2(TargetOpcode::G_SMAX),
        GIM_CheckType, /*MI*/2, /*Op*/1, /*Type*/GILLT_s16,
        GIM_CheckType, /*MI*/2, /*Op*/2, /*Type*/GILLT_s16,
        GIM_RecordInsn, /*DefineMI*/3, /*MI*/2, /*OpIdx*/2, // MIs[3]
        GIM_CheckOpcode, /*MI*/3, GIMT_Encode2(TargetOpcode::G_SMIN),
        // MIs[3] src0
        GIM_CheckIsSameOperand, /*MI*/3, /*OpIdx*/1, /*OtherMI*/1, /*OtherOpIdx*/1,
        // MIs[3] src1
        GIM_CheckIsSameOperand, /*MI*/3, /*OpIdx*/2, /*OtherMI*/1, /*OtherOpIdx*/2,
        GIM_CheckIsSafeToFold, /*InsnID*/1,
        GIM_CheckIsSafeToFold, /*InsnID*/2,
        GIM_CheckIsSafeToFold, /*InsnID*/3,
        // (smin:{ *:[i16] } (smax:{ *:[i16] } i16:{ *:[i16] }:$src0, i16:{ *:[i16] }:$src1), (smax:{ *:[i16] } i16:{ *:[i16] }:$src2, (smin:{ *:[i16] } i16:{ *:[i16] }:$src0, i16:{ *:[i16] }:$src1)))  =>  (V_MED3_I16_e64:{ *:[i16] } 0:{ *:[i32] }, VSrc_b16:{ *:[i16] }:$src0, 0:{ *:[i32] }, VSrc_b16:{ *:[i16] }:$src1, 0:{ *:[i32] }, VSrc_b16:{ *:[i16] }:$src2, 0:{ *:[i1] })
        GIR_BuildMI, /*InsnID*/0, /*Opcode*/GIMT_Encode2(AMDGPU::V_MED3_I16_e64),
        GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/0, // DstI[vdst]
        GIR_AddImm8, /*InsnID*/0, /*Imm*/0,
        GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/1, /*OpIdx*/1, // src0
        GIR_AddImm8, /*InsnID*/0, /*Imm*/0,
        GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/1, /*OpIdx*/2, // src1
        GIR_AddImm8, /*InsnID*/0, /*Imm*/0,
        GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/2, /*OpIdx*/1, // src2
        GIR_AddImm8, /*InsnID*/0, /*Imm*/0,
        GIR_AddImm8, /*InsnID*/0, /*Imm*/0,
        GIR_ConstrainSelectedInstOperands, /*InsnID*/0,
        GIR_EraseFromParent, /*InsnID*/0,
        // GIR_Coverage, 10496,
        GIR_Done,
      // Label 5262: @388717
      GIM_Try, /*On fail goto*//*Label 5263*/ GIMT_Encode4(388821), // Rule ID 10497 //
        GIM_CheckFeatures, GIMT_Encode2(GIFBS_isGFX9Plus),
        GIM_RecordInsn, /*DefineMI*/1, /*MI*/0, /*OpIdx*/1, // MIs[1]
        GIM_CheckOpcode, /*MI*/1, GIMT_Encode2(TargetOpcode::G_SMAX),
        GIM_CheckType, /*MI*/1, /*Op*/1, /*Type*/GILLT_s16,
        GIM_CheckType, /*MI*/1, /*Op*/2, /*Type*/GILLT_s16,
        GIM_RecordInsn, /*DefineMI*/2, /*MI*/0, /*OpIdx*/2, // MIs[2]
        GIM_CheckOpcode, /*MI*/2, GIMT_Encode2(TargetOpcode::G_SMAX),
        GIM_CheckType, /*MI*/2, /*Op*/1, /*Type*/GILLT_s16,
        GIM_CheckType, /*MI*/2, /*Op*/2, /*Type*/GILLT_s16,
        GIM_RecordInsn, /*DefineMI*/3, /*MI*/2, /*OpIdx*/2, // MIs[3]
        GIM_CheckOpcode, /*MI*/3, GIMT_Encode2(TargetOpcode::G_SMIN),
        // MIs[3] src1
        GIM_CheckIsSameOperand, /*MI*/3, /*OpIdx*/1, /*OtherMI*/1, /*OtherOpIdx*/2,
        // MIs[3] src0
        GIM_CheckIsSameOperand, /*MI*/3, /*OpIdx*/2, /*OtherMI*/1, /*OtherOpIdx*/1,
        GIM_CheckIsSafeToFold, /*InsnID*/1,
        GIM_CheckIsSafeToFold, /*InsnID*/2,
        GIM_CheckIsSafeToFold, /*InsnID*/3,
        // (smin:{ *:[i16] } (smax:{ *:[i16] } i16:{ *:[i16] }:$src0, i16:{ *:[i16] }:$src1), (smax:{ *:[i16] } i16:{ *:[i16] }:$src2, (smin:{ *:[i16] } i16:{ *:[i16] }:$src1, i16:{ *:[i16] }:$src0)))  =>  (V_MED3_I16_e64:{ *:[i16] } 0:{ *:[i32] }, VSrc_b16:{ *:[i16] }:$src0, 0:{ *:[i32] }, VSrc_b16:{ *:[i16] }:$src1, 0:{ *:[i32] }, VSrc_b16:{ *:[i16] }:$src2, 0:{ *:[i1] })
        GIR_BuildMI, /*InsnID*/0, /*Opcode*/GIMT_Encode2(AMDGPU::V_MED3_I16_e64),
        GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/0, // DstI[vdst]
        GIR_AddImm8, /*InsnID*/0, /*Imm*/0,
        GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/1, /*OpIdx*/1, // src0
        GIR_AddImm8, /*InsnID*/0, /*Imm*/0,
        GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/1, /*OpIdx*/2, // src1
        GIR_AddImm8, /*InsnID*/0, /*Imm*/0,
        GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/2, /*OpIdx*/1, // src2
        GIR_AddImm8, /*InsnID*/0, /*Imm*/0,
        GIR_AddImm8, /*InsnID*/0, /*Imm*/0,
        GIR_ConstrainSelectedInstOperands, /*InsnID*/0,
        GIR_EraseFromParent, /*InsnID*/0,
        // GIR_Coverage, 10497,
        GIR_Done,
      // Label 5263: @388821
      GIM_Try, /*On fail goto*//*Label 5264*/ GIMT_Encode4(388925), // Rule ID 10500 //
        GIM_CheckFeatures, GIMT_Encode2(GIFBS_isGFX9Plus),
        GIM_RecordInsn, /*DefineMI*/1, /*MI*/0, /*OpIdx*/1, // MIs[1]
        GIM_CheckOpcode, /*MI*/1, GIMT_Encode2(TargetOpcode::G_SMAX),
        GIM_CheckType, /*MI*/1, /*Op*/1, /*Type*/GILLT_s16,
        GIM_CheckType, /*MI*/1, /*Op*/2, /*Type*/GILLT_s16,
        GIM_RecordInsn, /*DefineMI*/2, /*MI*/0, /*OpIdx*/2, // MIs[2]
        GIM_CheckOpcode, /*MI*/2, GIMT_Encode2(TargetOpcode::G_SMAX),
        GIM_CheckType, /*MI*/2, /*Op*/1, /*Type*/GILLT_s16,
        GIM_CheckType, /*MI*/2, /*Op*/2, /*Type*/GILLT_s16,
        GIM_RecordInsn, /*DefineMI*/3, /*MI*/2, /*OpIdx*/2, // MIs[3]
        GIM_CheckOpcode, /*MI*/3, GIMT_Encode2(TargetOpcode::G_SMIN),
        // MIs[3] src0
        GIM_CheckIsSameOperand, /*MI*/3, /*OpIdx*/1, /*OtherMI*/1, /*OtherOpIdx*/2,
        // MIs[3] src1
        GIM_CheckIsSameOperand, /*MI*/3, /*OpIdx*/2, /*OtherMI*/1, /*OtherOpIdx*/1,
        GIM_CheckIsSafeToFold, /*InsnID*/1,
        GIM_CheckIsSafeToFold, /*InsnID*/2,
        GIM_CheckIsSafeToFold, /*InsnID*/3,
        // (smin:{ *:[i16] } (smax:{ *:[i16] } i16:{ *:[i16] }:$src1, i16:{ *:[i16] }:$src0), (smax:{ *:[i16] } i16:{ *:[i16] }:$src2, (smin:{ *:[i16] } i16:{ *:[i16] }:$src0, i16:{ *:[i16] }:$src1)))  =>  (V_MED3_I16_e64:{ *:[i16] } 0:{ *:[i32] }, VSrc_b16:{ *:[i16] }:$src0, 0:{ *:[i32] }, VSrc_b16:{ *:[i16] }:$src1, 0:{ *:[i32] }, VSrc_b16:{ *:[i16] }:$src2, 0:{ *:[i1] })
        GIR_BuildMI, /*InsnID*/0, /*Opcode*/GIMT_Encode2(AMDGPU::V_MED3_I16_e64),
        GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/0, // DstI[vdst]
        GIR_AddImm8, /*InsnID*/0, /*Imm*/0,
        GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/1, /*OpIdx*/2, // src0
        GIR_AddImm8, /*InsnID*/0, /*Imm*/0,
        GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/1, /*OpIdx*/1, // src1
        GIR_AddImm8, /*InsnID*/0, /*Imm*/0,
        GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/2, /*OpIdx*/1, // src2
        GIR_AddImm8, /*InsnID*/0, /*Imm*/0,
        GIR_AddImm8, /*InsnID*/0, /*Imm*/0,
        GIR_ConstrainSelectedInstOperands, /*InsnID*/0,
        GIR_EraseFromParent, /*InsnID*/0,
        // GIR_Coverage, 10500,
        GIR_Done,
      // Label 5264: @388925
      GIM_Try, /*On fail goto*//*Label 5265*/ GIMT_Encode4(389029), // Rule ID 10501 //
        GIM_CheckFeatures, GIMT_Encode2(GIFBS_isGFX9Plus),
        GIM_RecordInsn, /*DefineMI*/1, /*MI*/0, /*OpIdx*/1, // MIs[1]
        GIM_CheckOpcode, /*MI*/1, GIMT_Encode2(TargetOpcode::G_SMAX),
        GIM_CheckType, /*MI*/1, /*Op*/1, /*Type*/GILLT_s16,
        GIM_CheckType, /*MI*/1, /*Op*/2, /*Type*/GILLT_s16,
        GIM_RecordInsn, /*DefineMI*/2, /*MI*/0, /*OpIdx*/2, // MIs[2]
        GIM_CheckOpcode, /*MI*/2, GIMT_Encode2(TargetOpcode::G_SMAX),
        GIM_CheckType, /*MI*/2, /*Op*/1, /*Type*/GILLT_s16,
        GIM_CheckType, /*MI*/2, /*Op*/2, /*Type*/GILLT_s16,
        GIM_RecordInsn, /*DefineMI*/3, /*MI*/2, /*OpIdx*/2, // MIs[3]
        GIM_CheckOpcode, /*MI*/3, GIMT_Encode2(TargetOpcode::G_SMIN),
        // MIs[3] src1
        GIM_CheckIsSameOperand, /*MI*/3, /*OpIdx*/1, /*OtherMI*/1, /*OtherOpIdx*/1,
        // MIs[3] src0
        GIM_CheckIsSameOperand, /*MI*/3, /*OpIdx*/2, /*OtherMI*/1, /*OtherOpIdx*/2,
        GIM_CheckIsSafeToFold, /*InsnID*/1,
        GIM_CheckIsSafeToFold, /*InsnID*/2,
        GIM_CheckIsSafeToFold, /*InsnID*/3,
        // (smin:{ *:[i16] } (smax:{ *:[i16] } i16:{ *:[i16] }:$src1, i16:{ *:[i16] }:$src0), (smax:{ *:[i16] } i16:{ *:[i16] }:$src2, (smin:{ *:[i16] } i16:{ *:[i16] }:$src1, i16:{ *:[i16] }:$src0)))  =>  (V_MED3_I16_e64:{ *:[i16] } 0:{ *:[i32] }, VSrc_b16:{ *:[i16] }:$src0, 0:{ *:[i32] }, VSrc_b16:{ *:[i16] }:$src1, 0:{ *:[i32] }, VSrc_b16:{ *:[i16] }:$src2, 0:{ *:[i1] })
        GIR_BuildMI, /*InsnID*/0, /*Opcode*/GIMT_Encode2(AMDGPU::V_MED3_I16_e64),
        GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/0, // DstI[vdst]
        GIR_AddImm8, /*InsnID*/0, /*Imm*/0,
        GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/1, /*OpIdx*/2, // src0
        GIR_AddImm8, /*InsnID*/0, /*Imm*/0,
        GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/1, /*OpIdx*/1, // src1
        GIR_AddImm8, /*InsnID*/0, /*Imm*/0,
        GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/2, /*OpIdx*/1, // src2
        GIR_AddImm8, /*InsnID*/0, /*Imm*/0,
        GIR_AddImm8, /*InsnID*/0, /*Imm*/0,
        GIR_ConstrainSelectedInstOperands, /*InsnID*/0,
        GIR_EraseFromParent, /*InsnID*/0,
        // GIR_Coverage, 10501,
        GIR_Done,
      // Label 5265: @389029
      GIM_Try, /*On fail goto*//*Label 5266*/ GIMT_Encode4(389049), // Rule ID 831 //
        GIM_CheckFeatures, GIMT_Encode2(GIFBS_Has16BitInsts_NotHasTrue16BitInsts),
        // (smin:{ *:[i16] } i16:{ *:[i16] }:$src0, i16:{ *:[i16] }:$src1)  =>  (V_MIN_I16_e64:{ *:[i16] } i16:{ *:[i16] }:$src0, i16:{ *:[i16] }:$src1)
        GIR_MutateOpcode, /*InsnID*/0, /*RecycleInsnID*/0, /*Opcode*/GIMT_Encode2(AMDGPU::V_MIN_I16_e64),
        GIR_AddImplicitUse, /*InsnID*/0, GIMT_Encode2(AMDGPU::EXEC),
        GIR_ConstrainSelectedInstOperands, /*InsnID*/0,
        // GIR_Coverage, 831,
        GIR_Done,
      // Label 5266: @389049
      GIM_Try, /*On fail goto*//*Label 5267*/ GIMT_Encode4(389069), // Rule ID 832 //
        GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasTrue16BitInsts),
        // (smin:{ *:[i16] } i16:{ *:[i16] }:$src0, i16:{ *:[i16] }:$src1)  =>  (V_MIN_I16_t16_e64:{ *:[i16] } i16:{ *:[i16] }:$src0, i16:{ *:[i16] }:$src1)
        GIR_MutateOpcode, /*InsnID*/0, /*RecycleInsnID*/0, /*Opcode*/GIMT_Encode2(AMDGPU::V_MIN_I16_t16_e64),
        GIR_AddImplicitUse, /*InsnID*/0, GIMT_Encode2(AMDGPU::EXEC),
        GIR_ConstrainSelectedInstOperands, /*InsnID*/0,
        // GIR_Coverage, 832,
        GIR_Done,
      // Label 5267: @389069
      GIM_Reject,
    // Label 5249: @389070
    GIM_Reject,
    // Label 5246: @389071
    GIM_Try, /*On fail goto*//*Label 5268*/ GIMT_Encode4(390719),
      GIM_CheckType, /*MI*/0, /*Op*/1, /*Type*/GILLT_s32,
      GIM_CheckType, /*MI*/0, /*Op*/2, /*Type*/GILLT_s32,
      GIM_Try, /*On fail goto*//*Label 5269*/ GIMT_Encode4(389175), // Rule ID 9947 //
        GIM_CheckRegBankForClass, /*MI*/0, /*Op*/0, /*RC*/GIMT_Encode2(AMDGPU::VGPR_32RegClassID),
        GIM_RecordInsn, /*DefineMI*/1, /*MI*/0, /*OpIdx*/1, // MIs[1]
        GIM_CheckOpcode, /*MI*/1, GIMT_Encode2(TargetOpcode::G_SMAX),
        GIM_CheckType, /*MI*/1, /*Op*/1, /*Type*/GILLT_s32,
        GIM_CheckType, /*MI*/1, /*Op*/2, /*Type*/GILLT_s32,
        GIM_RecordInsn, /*DefineMI*/2, /*MI*/1, /*OpIdx*/1, // MIs[2]
        GIM_CheckOpcode, /*MI*/2, GIMT_Encode2(TargetOpcode::G_SMIN),
        GIM_CheckType, /*MI*/2, /*Op*/1, /*Type*/GILLT_s32,
        GIM_CheckType, /*MI*/2, /*Op*/2, /*Type*/GILLT_s32,
        GIM_RecordInsn, /*DefineMI*/3, /*MI*/0, /*OpIdx*/2, // MIs[3]
        GIM_CheckOpcode, /*MI*/3, GIMT_Encode2(TargetOpcode::G_SMAX),
        // MIs[3] src0
        GIM_CheckIsSameOperand, /*MI*/3, /*OpIdx*/1, /*OtherMI*/2, /*OtherOpIdx*/1,
        // MIs[3] src1
        GIM_CheckIsSameOperand, /*MI*/3, /*OpIdx*/2, /*OtherMI*/2, /*OtherOpIdx*/2,
        GIM_CheckIsSafeToFold, /*InsnID*/1,
        GIM_CheckIsSafeToFold, /*InsnID*/2,
        GIM_CheckIsSafeToFold, /*InsnID*/3,
        // (smin:{ *:[i32] } (smax:{ *:[i32] } (smin:{ *:[i32] } i32:{ *:[i32] }:$src0, i32:{ *:[i32] }:$src1), i32:{ *:[i32] }:$src2), (smax:{ *:[i32] } i32:{ *:[i32] }:$src0, i32:{ *:[i32] }:$src1))  =>  (V_MED3_I32_e64:{ *:[i32] } VSrc_b32:{ *:[i32] }:$src0, VSrc_b32:{ *:[i32] }:$src1, VSrc_b32:{ *:[i32] }:$src2)
        GIR_BuildMI, /*InsnID*/0, /*Opcode*/GIMT_Encode2(AMDGPU::V_MED3_I32_e64),
        GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/0, // DstI[vdst]
        GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/2, /*OpIdx*/1, // src0
        GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/2, /*OpIdx*/2, // src1
        GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/1, /*OpIdx*/2, // src2
        GIR_ConstrainSelectedInstOperands, /*InsnID*/0,
        GIR_EraseFromParent, /*InsnID*/0,
        // GIR_Coverage, 9947,
        GIR_Done,
      // Label 5269: @389175
      GIM_Try, /*On fail goto*//*Label 5270*/ GIMT_Encode4(389266), // Rule ID 9948 //
        GIM_CheckRegBankForClass, /*MI*/0, /*Op*/0, /*RC*/GIMT_Encode2(AMDGPU::VGPR_32RegClassID),
        GIM_RecordInsn, /*DefineMI*/1, /*MI*/0, /*OpIdx*/1, // MIs[1]
        GIM_CheckOpcode, /*MI*/1, GIMT_Encode2(TargetOpcode::G_SMAX),
        GIM_CheckType, /*MI*/1, /*Op*/1, /*Type*/GILLT_s32,
        GIM_CheckType, /*MI*/1, /*Op*/2, /*Type*/GILLT_s32,
        GIM_RecordInsn, /*DefineMI*/2, /*MI*/1, /*OpIdx*/1, // MIs[2]
        GIM_CheckOpcode, /*MI*/2, GIMT_Encode2(TargetOpcode::G_SMIN),
        GIM_CheckType, /*MI*/2, /*Op*/1, /*Type*/GILLT_s32,
        GIM_CheckType, /*MI*/2, /*Op*/2, /*Type*/GILLT_s32,
        GIM_RecordInsn, /*DefineMI*/3, /*MI*/0, /*OpIdx*/2, // MIs[3]
        GIM_CheckOpcode, /*MI*/3, GIMT_Encode2(TargetOpcode::G_SMAX),
        // MIs[3] src1
        GIM_CheckIsSameOperand, /*MI*/3, /*OpIdx*/1, /*OtherMI*/2, /*OtherOpIdx*/2,
        // MIs[3] src0
        GIM_CheckIsSameOperand, /*MI*/3, /*OpIdx*/2, /*OtherMI*/2, /*OtherOpIdx*/1,
        GIM_CheckIsSafeToFold, /*InsnID*/1,
        GIM_CheckIsSafeToFold, /*InsnID*/2,
        GIM_CheckIsSafeToFold, /*InsnID*/3,
        // (smin:{ *:[i32] } (smax:{ *:[i32] } (smin:{ *:[i32] } i32:{ *:[i32] }:$src0, i32:{ *:[i32] }:$src1), i32:{ *:[i32] }:$src2), (smax:{ *:[i32] } i32:{ *:[i32] }:$src1, i32:{ *:[i32] }:$src0))  =>  (V_MED3_I32_e64:{ *:[i32] } VSrc_b32:{ *:[i32] }:$src0, VSrc_b32:{ *:[i32] }:$src1, VSrc_b32:{ *:[i32] }:$src2)
        GIR_BuildMI, /*InsnID*/0, /*Opcode*/GIMT_Encode2(AMDGPU::V_MED3_I32_e64),
        GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/0, // DstI[vdst]
        GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/2, /*OpIdx*/1, // src0
        GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/2, /*OpIdx*/2, // src1
        GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/1, /*OpIdx*/2, // src2
        GIR_ConstrainSelectedInstOperands, /*InsnID*/0,
        GIR_EraseFromParent, /*InsnID*/0,
        // GIR_Coverage, 9948,
        GIR_Done,
      // Label 5270: @389266
      GIM_Try, /*On fail goto*//*Label 5271*/ GIMT_Encode4(389357), // Rule ID 9949 //
        GIM_CheckRegBankForClass, /*MI*/0, /*Op*/0, /*RC*/GIMT_Encode2(AMDGPU::VGPR_32RegClassID),
        GIM_RecordInsn, /*DefineMI*/1, /*MI*/0, /*OpIdx*/1, // MIs[1]
        GIM_CheckOpcode, /*MI*/1, GIMT_Encode2(TargetOpcode::G_SMAX),
        GIM_CheckType, /*MI*/1, /*Op*/1, /*Type*/GILLT_s32,
        GIM_CheckType, /*MI*/1, /*Op*/2, /*Type*/GILLT_s32,
        GIM_RecordInsn, /*DefineMI*/2, /*MI*/1, /*OpIdx*/1, // MIs[2]
        GIM_CheckOpcode, /*MI*/2, GIMT_Encode2(TargetOpcode::G_SMIN),
        GIM_CheckType, /*MI*/2, /*Op*/1, /*Type*/GILLT_s32,
        GIM_CheckType, /*MI*/2, /*Op*/2, /*Type*/GILLT_s32,
        GIM_RecordInsn, /*DefineMI*/3, /*MI*/0, /*OpIdx*/2, // MIs[3]
        GIM_CheckOpcode, /*MI*/3, GIMT_Encode2(TargetOpcode::G_SMAX),
        // MIs[3] src0
        GIM_CheckIsSameOperand, /*MI*/3, /*OpIdx*/1, /*OtherMI*/2, /*OtherOpIdx*/2,
        // MIs[3] src1
        GIM_CheckIsSameOperand, /*MI*/3, /*OpIdx*/2, /*OtherMI*/2, /*OtherOpIdx*/1,
        GIM_CheckIsSafeToFold, /*InsnID*/1,
        GIM_CheckIsSafeToFold, /*InsnID*/2,
        GIM_CheckIsSafeToFold, /*InsnID*/3,
        // (smin:{ *:[i32] } (smax:{ *:[i32] } (smin:{ *:[i32] } i32:{ *:[i32] }:$src1, i32:{ *:[i32] }:$src0), i32:{ *:[i32] }:$src2), (smax:{ *:[i32] } i32:{ *:[i32] }:$src0, i32:{ *:[i32] }:$src1))  =>  (V_MED3_I32_e64:{ *:[i32] } VSrc_b32:{ *:[i32] }:$src0, VSrc_b32:{ *:[i32] }:$src1, VSrc_b32:{ *:[i32] }:$src2)
        GIR_BuildMI, /*InsnID*/0, /*Opcode*/GIMT_Encode2(AMDGPU::V_MED3_I32_e64),
        GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/0, // DstI[vdst]
        GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/2, /*OpIdx*/2, // src0
        GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/2, /*OpIdx*/1, // src1
        GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/1, /*OpIdx*/2, // src2
        GIR_ConstrainSelectedInstOperands, /*InsnID*/0,
        GIR_EraseFromParent, /*InsnID*/0,
        // GIR_Coverage, 9949,
        GIR_Done,
      // Label 5271: @389357
      GIM_Try, /*On fail goto*//*Label 5272*/ GIMT_Encode4(389448), // Rule ID 9950 //
        GIM_CheckRegBankForClass, /*MI*/0, /*Op*/0, /*RC*/GIMT_Encode2(AMDGPU::VGPR_32RegClassID),
        GIM_RecordInsn, /*DefineMI*/1, /*MI*/0, /*OpIdx*/1, // MIs[1]
        GIM_CheckOpcode, /*MI*/1, GIMT_Encode2(TargetOpcode::G_SMAX),
        GIM_CheckType, /*MI*/1, /*Op*/1, /*Type*/GILLT_s32,
        GIM_CheckType, /*MI*/1, /*Op*/2, /*Type*/GILLT_s32,
        GIM_RecordInsn, /*DefineMI*/2, /*MI*/1, /*OpIdx*/1, // MIs[2]
        GIM_CheckOpcode, /*MI*/2, GIMT_Encode2(TargetOpcode::G_SMIN),
        GIM_CheckType, /*MI*/2, /*Op*/1, /*Type*/GILLT_s32,
        GIM_CheckType, /*MI*/2, /*Op*/2, /*Type*/GILLT_s32,
        GIM_RecordInsn, /*DefineMI*/3, /*MI*/0, /*OpIdx*/2, // MIs[3]
        GIM_CheckOpcode, /*MI*/3, GIMT_Encode2(TargetOpcode::G_SMAX),
        // MIs[3] src1
        GIM_CheckIsSameOperand, /*MI*/3, /*OpIdx*/1, /*OtherMI*/2, /*OtherOpIdx*/1,
        // MIs[3] src0
        GIM_CheckIsSameOperand, /*MI*/3, /*OpIdx*/2, /*OtherMI*/2, /*OtherOpIdx*/2,
        GIM_CheckIsSafeToFold, /*InsnID*/1,
        GIM_CheckIsSafeToFold, /*InsnID*/2,
        GIM_CheckIsSafeToFold, /*InsnID*/3,
        // (smin:{ *:[i32] } (smax:{ *:[i32] } (smin:{ *:[i32] } i32:{ *:[i32] }:$src1, i32:{ *:[i32] }:$src0), i32:{ *:[i32] }:$src2), (smax:{ *:[i32] } i32:{ *:[i32] }:$src1, i32:{ *:[i32] }:$src0))  =>  (V_MED3_I32_e64:{ *:[i32] } VSrc_b32:{ *:[i32] }:$src0, VSrc_b32:{ *:[i32] }:$src1, VSrc_b32:{ *:[i32] }:$src2)
        GIR_BuildMI, /*InsnID*/0, /*Opcode*/GIMT_Encode2(AMDGPU::V_MED3_I32_e64),
        GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/0, // DstI[vdst]
        GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/2, /*OpIdx*/2, // src0
        GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/2, /*OpIdx*/1, // src1
        GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/1, /*OpIdx*/2, // src2
        GIR_ConstrainSelectedInstOperands, /*InsnID*/0,
        GIR_EraseFromParent, /*InsnID*/0,
        // GIR_Coverage, 9950,
        GIR_Done,
      // Label 5272: @389448
      GIM_Try, /*On fail goto*//*Label 5273*/ GIMT_Encode4(389539), // Rule ID 9951 //
        GIM_CheckRegBankForClass, /*MI*/0, /*Op*/0, /*RC*/GIMT_Encode2(AMDGPU::VGPR_32RegClassID),
        GIM_RecordInsn, /*DefineMI*/1, /*MI*/0, /*OpIdx*/1, // MIs[1]
        GIM_CheckOpcode, /*MI*/1, GIMT_Encode2(TargetOpcode::G_SMAX),
        GIM_CheckType, /*MI*/1, /*Op*/1, /*Type*/GILLT_s32,
        GIM_CheckType, /*MI*/1, /*Op*/2, /*Type*/GILLT_s32,
        GIM_RecordInsn, /*DefineMI*/2, /*MI*/1, /*OpIdx*/2, // MIs[2]
        GIM_CheckOpcode, /*MI*/2, GIMT_Encode2(TargetOpcode::G_SMIN),
        GIM_CheckType, /*MI*/2, /*Op*/1, /*Type*/GILLT_s32,
        GIM_CheckType, /*MI*/2, /*Op*/2, /*Type*/GILLT_s32,
        GIM_RecordInsn, /*DefineMI*/3, /*MI*/0, /*OpIdx*/2, // MIs[3]
        GIM_CheckOpcode, /*MI*/3, GIMT_Encode2(TargetOpcode::G_SMAX),
        // MIs[3] src0
        GIM_CheckIsSameOperand, /*MI*/3, /*OpIdx*/1, /*OtherMI*/2, /*OtherOpIdx*/1,
        // MIs[3] src1
        GIM_CheckIsSameOperand, /*MI*/3, /*OpIdx*/2, /*OtherMI*/2, /*OtherOpIdx*/2,
        GIM_CheckIsSafeToFold, /*InsnID*/1,
        GIM_CheckIsSafeToFold, /*InsnID*/2,
        GIM_CheckIsSafeToFold, /*InsnID*/3,
        // (smin:{ *:[i32] } (smax:{ *:[i32] } i32:{ *:[i32] }:$src2, (smin:{ *:[i32] } i32:{ *:[i32] }:$src0, i32:{ *:[i32] }:$src1)), (smax:{ *:[i32] } i32:{ *:[i32] }:$src0, i32:{ *:[i32] }:$src1))  =>  (V_MED3_I32_e64:{ *:[i32] } VSrc_b32:{ *:[i32] }:$src0, VSrc_b32:{ *:[i32] }:$src1, VSrc_b32:{ *:[i32] }:$src2)
        GIR_BuildMI, /*InsnID*/0, /*Opcode*/GIMT_Encode2(AMDGPU::V_MED3_I32_e64),
        GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/0, // DstI[vdst]
        GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/2, /*OpIdx*/1, // src0
        GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/2, /*OpIdx*/2, // src1
        GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/1, /*OpIdx*/1, // src2
        GIR_ConstrainSelectedInstOperands, /*InsnID*/0,
        GIR_EraseFromParent, /*InsnID*/0,
        // GIR_Coverage, 9951,
        GIR_Done,
      // Label 5273: @389539
      GIM_Try, /*On fail goto*//*Label 5274*/ GIMT_Encode4(389630), // Rule ID 9952 //
        GIM_CheckRegBankForClass, /*MI*/0, /*Op*/0, /*RC*/GIMT_Encode2(AMDGPU::VGPR_32RegClassID),
        GIM_RecordInsn, /*DefineMI*/1, /*MI*/0, /*OpIdx*/1, // MIs[1]
        GIM_CheckOpcode, /*MI*/1, GIMT_Encode2(TargetOpcode::G_SMAX),
        GIM_CheckType, /*MI*/1, /*Op*/1, /*Type*/GILLT_s32,
        GIM_CheckType, /*MI*/1, /*Op*/2, /*Type*/GILLT_s32,
        GIM_RecordInsn, /*DefineMI*/2, /*MI*/1, /*OpIdx*/2, // MIs[2]
        GIM_CheckOpcode, /*MI*/2, GIMT_Encode2(TargetOpcode::G_SMIN),
        GIM_CheckType, /*MI*/2, /*Op*/1, /*Type*/GILLT_s32,
        GIM_CheckType, /*MI*/2, /*Op*/2, /*Type*/GILLT_s32,
        GIM_RecordInsn, /*DefineMI*/3, /*MI*/0, /*OpIdx*/2, // MIs[3]
        GIM_CheckOpcode, /*MI*/3, GIMT_Encode2(TargetOpcode::G_SMAX),
        // MIs[3] src1
        GIM_CheckIsSameOperand, /*MI*/3, /*OpIdx*/1, /*OtherMI*/2, /*OtherOpIdx*/2,
        // MIs[3] src0
        GIM_CheckIsSameOperand, /*MI*/3, /*OpIdx*/2, /*OtherMI*/2, /*OtherOpIdx*/1,
        GIM_CheckIsSafeToFold, /*InsnID*/1,
        GIM_CheckIsSafeToFold, /*InsnID*/2,
        GIM_CheckIsSafeToFold, /*InsnID*/3,
        // (smin:{ *:[i32] } (smax:{ *:[i32] } i32:{ *:[i32] }:$src2, (smin:{ *:[i32] } i32:{ *:[i32] }:$src0, i32:{ *:[i32] }:$src1)), (smax:{ *:[i32] } i32:{ *:[i32] }:$src1, i32:{ *:[i32] }:$src0))  =>  (V_MED3_I32_e64:{ *:[i32] } VSrc_b32:{ *:[i32] }:$src0, VSrc_b32:{ *:[i32] }:$src1, VSrc_b32:{ *:[i32] }:$src2)
        GIR_BuildMI, /*InsnID*/0, /*Opcode*/GIMT_Encode2(AMDGPU::V_MED3_I32_e64),
        GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/0, // DstI[vdst]
        GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/2, /*OpIdx*/1, // src0
        GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/2, /*OpIdx*/2, // src1
        GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/1, /*OpIdx*/1, // src2
        GIR_ConstrainSelectedInstOperands, /*InsnID*/0,
        GIR_EraseFromParent, /*InsnID*/0,
        // GIR_Coverage, 9952,
        GIR_Done,
      // Label 5274: @389630
      GIM_Try, /*On fail goto*//*Label 5275*/ GIMT_Encode4(389721), // Rule ID 9953 //
        GIM_CheckRegBankForClass, /*MI*/0, /*Op*/0, /*RC*/GIMT_Encode2(AMDGPU::VGPR_32RegClassID),
        GIM_RecordInsn, /*DefineMI*/1, /*MI*/0, /*OpIdx*/1, // MIs[1]
        GIM_CheckOpcode, /*MI*/1, GIMT_Encode2(TargetOpcode::G_SMAX),
        GIM_CheckType, /*MI*/1, /*Op*/1, /*Type*/GILLT_s32,
        GIM_CheckType, /*MI*/1, /*Op*/2, /*Type*/GILLT_s32,
        GIM_RecordInsn, /*DefineMI*/2, /*MI*/1, /*OpIdx*/2, // MIs[2]
        GIM_CheckOpcode, /*MI*/2, GIMT_Encode2(TargetOpcode::G_SMIN),
        GIM_CheckType, /*MI*/2, /*Op*/1, /*Type*/GILLT_s32,
        GIM_CheckType, /*MI*/2, /*Op*/2, /*Type*/GILLT_s32,
        GIM_RecordInsn, /*DefineMI*/3, /*MI*/0, /*OpIdx*/2, // MIs[3]
        GIM_CheckOpcode, /*MI*/3, GIMT_Encode2(TargetOpcode::G_SMAX),
        // MIs[3] src0
        GIM_CheckIsSameOperand, /*MI*/3, /*OpIdx*/1, /*OtherMI*/2, /*OtherOpIdx*/2,
        // MIs[3] src1
        GIM_CheckIsSameOperand, /*MI*/3, /*OpIdx*/2, /*OtherMI*/2, /*OtherOpIdx*/1,
        GIM_CheckIsSafeToFold, /*InsnID*/1,
        GIM_CheckIsSafeToFold, /*InsnID*/2,
        GIM_CheckIsSafeToFold, /*InsnID*/3,
        // (smin:{ *:[i32] } (smax:{ *:[i32] } i32:{ *:[i32] }:$src2, (smin:{ *:[i32] } i32:{ *:[i32] }:$src1, i32:{ *:[i32] }:$src0)), (smax:{ *:[i32] } i32:{ *:[i32] }:$src0, i32:{ *:[i32] }:$src1))  =>  (V_MED3_I32_e64:{ *:[i32] } VSrc_b32:{ *:[i32] }:$src0, VSrc_b32:{ *:[i32] }:$src1, VSrc_b32:{ *:[i32] }:$src2)
        GIR_BuildMI, /*InsnID*/0, /*Opcode*/GIMT_Encode2(AMDGPU::V_MED3_I32_e64),
        GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/0, // DstI[vdst]
        GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/2, /*OpIdx*/2, // src0
        GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/2, /*OpIdx*/1, // src1
        GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/1, /*OpIdx*/1, // src2
        GIR_ConstrainSelectedInstOperands, /*InsnID*/0,
        GIR_EraseFromParent, /*InsnID*/0,
        // GIR_Coverage, 9953,
        GIR_Done,
      // Label 5275: @389721
      GIM_Try, /*On fail goto*//*Label 5276*/ GIMT_Encode4(389812), // Rule ID 9954 //
        GIM_CheckRegBankForClass, /*MI*/0, /*Op*/0, /*RC*/GIMT_Encode2(AMDGPU::VGPR_32RegClassID),
        GIM_RecordInsn, /*DefineMI*/1, /*MI*/0, /*OpIdx*/1, // MIs[1]
        GIM_CheckOpcode, /*MI*/1, GIMT_Encode2(TargetOpcode::G_SMAX),
        GIM_CheckType, /*MI*/1, /*Op*/1, /*Type*/GILLT_s32,
        GIM_CheckType, /*MI*/1, /*Op*/2, /*Type*/GILLT_s32,
        GIM_RecordInsn, /*DefineMI*/2, /*MI*/1, /*OpIdx*/2, // MIs[2]
        GIM_CheckOpcode, /*MI*/2, GIMT_Encode2(TargetOpcode::G_SMIN),
        GIM_CheckType, /*MI*/2, /*Op*/1, /*Type*/GILLT_s32,
        GIM_CheckType, /*MI*/2, /*Op*/2, /*Type*/GILLT_s32,
        GIM_RecordInsn, /*DefineMI*/3, /*MI*/0, /*OpIdx*/2, // MIs[3]
        GIM_CheckOpcode, /*MI*/3, GIMT_Encode2(TargetOpcode::G_SMAX),
        // MIs[3] src1
        GIM_CheckIsSameOperand, /*MI*/3, /*OpIdx*/1, /*OtherMI*/2, /*OtherOpIdx*/1,
        // MIs[3] src0
        GIM_CheckIsSameOperand, /*MI*/3, /*OpIdx*/2, /*OtherMI*/2, /*OtherOpIdx*/2,
        GIM_CheckIsSafeToFold, /*InsnID*/1,
        GIM_CheckIsSafeToFold, /*InsnID*/2,
        GIM_CheckIsSafeToFold, /*InsnID*/3,
        // (smin:{ *:[i32] } (smax:{ *:[i32] } i32:{ *:[i32] }:$src2, (smin:{ *:[i32] } i32:{ *:[i32] }:$src1, i32:{ *:[i32] }:$src0)), (smax:{ *:[i32] } i32:{ *:[i32] }:$src1, i32:{ *:[i32] }:$src0))  =>  (V_MED3_I32_e64:{ *:[i32] } VSrc_b32:{ *:[i32] }:$src0, VSrc_b32:{ *:[i32] }:$src1, VSrc_b32:{ *:[i32] }:$src2)
        GIR_BuildMI, /*InsnID*/0, /*Opcode*/GIMT_Encode2(AMDGPU::V_MED3_I32_e64),
        GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/0, // DstI[vdst]
        GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/2, /*OpIdx*/2, // src0
        GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/2, /*OpIdx*/1, // src1
        GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/1, /*OpIdx*/1, // src2
        GIR_ConstrainSelectedInstOperands, /*InsnID*/0,
        GIR_EraseFromParent, /*InsnID*/0,
        // GIR_Coverage, 9954,
        GIR_Done,
      // Label 5276: @389812
      GIM_Try, /*On fail goto*//*Label 5277*/ GIMT_Encode4(389903), // Rule ID 6478 //
        GIM_CheckRegBankForClass, /*MI*/0, /*Op*/0, /*RC*/GIMT_Encode2(AMDGPU::VGPR_32RegClassID),
        GIM_RecordInsn, /*DefineMI*/1, /*MI*/0, /*OpIdx*/1, // MIs[1]
        GIM_CheckOpcode, /*MI*/1, GIMT_Encode2(TargetOpcode::G_SMAX),
        GIM_CheckType, /*MI*/1, /*Op*/1, /*Type*/GILLT_s32,
        GIM_CheckType, /*MI*/1, /*Op*/2, /*Type*/GILLT_s32,
        GIM_RecordInsn, /*DefineMI*/2, /*MI*/0, /*OpIdx*/2, // MIs[2]
        GIM_CheckOpcode, /*MI*/2, GIMT_Encode2(TargetOpcode::G_SMAX),
        GIM_CheckType, /*MI*/2, /*Op*/1, /*Type*/GILLT_s32,
        GIM_CheckType, /*MI*/2, /*Op*/2, /*Type*/GILLT_s32,
        GIM_RecordInsn, /*DefineMI*/3, /*MI*/2, /*OpIdx*/1, // MIs[3]
        GIM_CheckOpcode, /*MI*/3, GIMT_Encode2(TargetOpcode::G_SMIN),
        // MIs[3] src0
        GIM_CheckIsSameOperand, /*MI*/3, /*OpIdx*/1, /*OtherMI*/1, /*OtherOpIdx*/1,
        // MIs[3] src1
        GIM_CheckIsSameOperand, /*MI*/3, /*OpIdx*/2, /*OtherMI*/1, /*OtherOpIdx*/2,
        GIM_CheckIsSafeToFold, /*InsnID*/1,
        GIM_CheckIsSafeToFold, /*InsnID*/2,
        GIM_CheckIsSafeToFold, /*InsnID*/3,
        // (smin:{ *:[i32] } (smax:{ *:[i32] } i32:{ *:[i32] }:$src0, i32:{ *:[i32] }:$src1), (smax:{ *:[i32] } (smin:{ *:[i32] } i32:{ *:[i32] }:$src0, i32:{ *:[i32] }:$src1), i32:{ *:[i32] }:$src2))  =>  (V_MED3_I32_e64:{ *:[i32] } VSrc_b32:{ *:[i32] }:$src0, VSrc_b32:{ *:[i32] }:$src1, VSrc_b32:{ *:[i32] }:$src2)
        GIR_BuildMI, /*InsnID*/0, /*Opcode*/GIMT_Encode2(AMDGPU::V_MED3_I32_e64),
        GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/0, // DstI[vdst]
        GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/1, /*OpIdx*/1, // src0
        GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/1, /*OpIdx*/2, // src1
        GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/2, /*OpIdx*/2, // src2
        GIR_ConstrainSelectedInstOperands, /*InsnID*/0,
        GIR_EraseFromParent, /*InsnID*/0,
        // GIR_Coverage, 6478,
        GIR_Done,
      // Label 5277: @389903
      GIM_Try, /*On fail goto*//*Label 5278*/ GIMT_Encode4(389994), // Rule ID 9940 //
        GIM_CheckRegBankForClass, /*MI*/0, /*Op*/0, /*RC*/GIMT_Encode2(AMDGPU::VGPR_32RegClassID),
        GIM_RecordInsn, /*DefineMI*/1, /*MI*/0, /*OpIdx*/1, // MIs[1]
        GIM_CheckOpcode, /*MI*/1, GIMT_Encode2(TargetOpcode::G_SMAX),
        GIM_CheckType, /*MI*/1, /*Op*/1, /*Type*/GILLT_s32,
        GIM_CheckType, /*MI*/1, /*Op*/2, /*Type*/GILLT_s32,
        GIM_RecordInsn, /*DefineMI*/2, /*MI*/0, /*OpIdx*/2, // MIs[2]
        GIM_CheckOpcode, /*MI*/2, GIMT_Encode2(TargetOpcode::G_SMAX),
        GIM_CheckType, /*MI*/2, /*Op*/1, /*Type*/GILLT_s32,
        GIM_CheckType, /*MI*/2, /*Op*/2, /*Type*/GILLT_s32,
        GIM_RecordInsn, /*DefineMI*/3, /*MI*/2, /*OpIdx*/1, // MIs[3]
        GIM_CheckOpcode, /*MI*/3, GIMT_Encode2(TargetOpcode::G_SMIN),
        // MIs[3] src1
        GIM_CheckIsSameOperand, /*MI*/3, /*OpIdx*/1, /*OtherMI*/1, /*OtherOpIdx*/2,
        // MIs[3] src0
        GIM_CheckIsSameOperand, /*MI*/3, /*OpIdx*/2, /*OtherMI*/1, /*OtherOpIdx*/1,
        GIM_CheckIsSafeToFold, /*InsnID*/1,
        GIM_CheckIsSafeToFold, /*InsnID*/2,
        GIM_CheckIsSafeToFold, /*InsnID*/3,
        // (smin:{ *:[i32] } (smax:{ *:[i32] } i32:{ *:[i32] }:$src0, i32:{ *:[i32] }:$src1), (smax:{ *:[i32] } (smin:{ *:[i32] } i32:{ *:[i32] }:$src1, i32:{ *:[i32] }:$src0), i32:{ *:[i32] }:$src2))  =>  (V_MED3_I32_e64:{ *:[i32] } VSrc_b32:{ *:[i32] }:$src0, VSrc_b32:{ *:[i32] }:$src1, VSrc_b32:{ *:[i32] }:$src2)
        GIR_BuildMI, /*InsnID*/0, /*Opcode*/GIMT_Encode2(AMDGPU::V_MED3_I32_e64),
        GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/0, // DstI[vdst]
        GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/1, /*OpIdx*/1, // src0
        GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/1, /*OpIdx*/2, // src1
        GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/2, /*OpIdx*/2, // src2
        GIR_ConstrainSelectedInstOperands, /*InsnID*/0,
        GIR_EraseFromParent, /*InsnID*/0,
        // GIR_Coverage, 9940,
        GIR_Done,
      // Label 5278: @389994
      GIM_Try, /*On fail goto*//*Label 5279*/ GIMT_Encode4(390085), // Rule ID 9943 //
        GIM_CheckRegBankForClass, /*MI*/0, /*Op*/0, /*RC*/GIMT_Encode2(AMDGPU::VGPR_32RegClassID),
        GIM_RecordInsn, /*DefineMI*/1, /*MI*/0, /*OpIdx*/1, // MIs[1]
        GIM_CheckOpcode, /*MI*/1, GIMT_Encode2(TargetOpcode::G_SMAX),
        GIM_CheckType, /*MI*/1, /*Op*/1, /*Type*/GILLT_s32,
        GIM_CheckType, /*MI*/1, /*Op*/2, /*Type*/GILLT_s32,
        GIM_RecordInsn, /*DefineMI*/2, /*MI*/0, /*OpIdx*/2, // MIs[2]
        GIM_CheckOpcode, /*MI*/2, GIMT_Encode2(TargetOpcode::G_SMAX),
        GIM_CheckType, /*MI*/2, /*Op*/1, /*Type*/GILLT_s32,
        GIM_CheckType, /*MI*/2, /*Op*/2, /*Type*/GILLT_s32,
        GIM_RecordInsn, /*DefineMI*/3, /*MI*/2, /*OpIdx*/1, // MIs[3]
        GIM_CheckOpcode, /*MI*/3, GIMT_Encode2(TargetOpcode::G_SMIN),
        // MIs[3] src0
        GIM_CheckIsSameOperand, /*MI*/3, /*OpIdx*/1, /*OtherMI*/1, /*OtherOpIdx*/2,
        // MIs[3] src1
        GIM_CheckIsSameOperand, /*MI*/3, /*OpIdx*/2, /*OtherMI*/1, /*OtherOpIdx*/1,
        GIM_CheckIsSafeToFold, /*InsnID*/1,
        GIM_CheckIsSafeToFold, /*InsnID*/2,
        GIM_CheckIsSafeToFold, /*InsnID*/3,
        // (smin:{ *:[i32] } (smax:{ *:[i32] } i32:{ *:[i32] }:$src1, i32:{ *:[i32] }:$src0), (smax:{ *:[i32] } (smin:{ *:[i32] } i32:{ *:[i32] }:$src0, i32:{ *:[i32] }:$src1), i32:{ *:[i32] }:$src2))  =>  (V_MED3_I32_e64:{ *:[i32] } VSrc_b32:{ *:[i32] }:$src0, VSrc_b32:{ *:[i32] }:$src1, VSrc_b32:{ *:[i32] }:$src2)
        GIR_BuildMI, /*InsnID*/0, /*Opcode*/GIMT_Encode2(AMDGPU::V_MED3_I32_e64),
        GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/0, // DstI[vdst]
        GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/1, /*OpIdx*/2, // src0
        GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/1, /*OpIdx*/1, // src1
        GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/2, /*OpIdx*/2, // src2
        GIR_ConstrainSelectedInstOperands, /*InsnID*/0,
        GIR_EraseFromParent, /*InsnID*/0,
        // GIR_Coverage, 9943,
        GIR_Done,
      // Label 5279: @390085
      GIM_Try, /*On fail goto*//*Label 5280*/ GIMT_Encode4(390176), // Rule ID 9944 //
        GIM_CheckRegBankForClass, /*MI*/0, /*Op*/0, /*RC*/GIMT_Encode2(AMDGPU::VGPR_32RegClassID),
        GIM_RecordInsn, /*DefineMI*/1, /*MI*/0, /*OpIdx*/1, // MIs[1]
        GIM_CheckOpcode, /*MI*/1, GIMT_Encode2(TargetOpcode::G_SMAX),
        GIM_CheckType, /*MI*/1, /*Op*/1, /*Type*/GILLT_s32,
        GIM_CheckType, /*MI*/1, /*Op*/2, /*Type*/GILLT_s32,
        GIM_RecordInsn, /*DefineMI*/2, /*MI*/0, /*OpIdx*/2, // MIs[2]
        GIM_CheckOpcode, /*MI*/2, GIMT_Encode2(TargetOpcode::G_SMAX),
        GIM_CheckType, /*MI*/2, /*Op*/1, /*Type*/GILLT_s32,
        GIM_CheckType, /*MI*/2, /*Op*/2, /*Type*/GILLT_s32,
        GIM_RecordInsn, /*DefineMI*/3, /*MI*/2, /*OpIdx*/1, // MIs[3]
        GIM_CheckOpcode, /*MI*/3, GIMT_Encode2(TargetOpcode::G_SMIN),
        // MIs[3] src1
        GIM_CheckIsSameOperand, /*MI*/3, /*OpIdx*/1, /*OtherMI*/1, /*OtherOpIdx*/1,
        // MIs[3] src0
        GIM_CheckIsSameOperand, /*MI*/3, /*OpIdx*/2, /*OtherMI*/1, /*OtherOpIdx*/2,
        GIM_CheckIsSafeToFold, /*InsnID*/1,
        GIM_CheckIsSafeToFold, /*InsnID*/2,
        GIM_CheckIsSafeToFold, /*InsnID*/3,
        // (smin:{ *:[i32] } (smax:{ *:[i32] } i32:{ *:[i32] }:$src1, i32:{ *:[i32] }:$src0), (smax:{ *:[i32] } (smin:{ *:[i32] } i32:{ *:[i32] }:$src1, i32:{ *:[i32] }:$src0), i32:{ *:[i32] }:$src2))  =>  (V_MED3_I32_e64:{ *:[i32] } VSrc_b32:{ *:[i32] }:$src0, VSrc_b32:{ *:[i32] }:$src1, VSrc_b32:{ *:[i32] }:$src2)
        GIR_BuildMI, /*InsnID*/0, /*Opcode*/GIMT_Encode2(AMDGPU::V_MED3_I32_e64),
        GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/0, // DstI[vdst]
        GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/1, /*OpIdx*/2, // src0
        GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/1, /*OpIdx*/1, // src1
        GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/2, /*OpIdx*/2, // src2
        GIR_ConstrainSelectedInstOperands, /*InsnID*/0,
        GIR_EraseFromParent, /*InsnID*/0,
        // GIR_Coverage, 9944,
        GIR_Done,
      // Label 5280: @390176
      GIM_Try, /*On fail goto*//*Label 5281*/ GIMT_Encode4(390267), // Rule ID 9941 //
        GIM_CheckRegBankForClass, /*MI*/0, /*Op*/0, /*RC*/GIMT_Encode2(AMDGPU::VGPR_32RegClassID),
        GIM_RecordInsn, /*DefineMI*/1, /*MI*/0, /*OpIdx*/1, // MIs[1]
        GIM_CheckOpcode, /*MI*/1, GIMT_Encode2(TargetOpcode::G_SMAX),
        GIM_CheckType, /*MI*/1, /*Op*/1, /*Type*/GILLT_s32,
        GIM_CheckType, /*MI*/1, /*Op*/2, /*Type*/GILLT_s32,
        GIM_RecordInsn, /*DefineMI*/2, /*MI*/0, /*OpIdx*/2, // MIs[2]
        GIM_CheckOpcode, /*MI*/2, GIMT_Encode2(TargetOpcode::G_SMAX),
        GIM_CheckType, /*MI*/2, /*Op*/1, /*Type*/GILLT_s32,
        GIM_CheckType, /*MI*/2, /*Op*/2, /*Type*/GILLT_s32,
        GIM_RecordInsn, /*DefineMI*/3, /*MI*/2, /*OpIdx*/2, // MIs[3]
        GIM_CheckOpcode, /*MI*/3, GIMT_Encode2(TargetOpcode::G_SMIN),
        // MIs[3] src0
        GIM_CheckIsSameOperand, /*MI*/3, /*OpIdx*/1, /*OtherMI*/1, /*OtherOpIdx*/1,
        // MIs[3] src1
        GIM_CheckIsSameOperand, /*MI*/3, /*OpIdx*/2, /*OtherMI*/1, /*OtherOpIdx*/2,
        GIM_CheckIsSafeToFold, /*InsnID*/1,
        GIM_CheckIsSafeToFold, /*InsnID*/2,
        GIM_CheckIsSafeToFold, /*InsnID*/3,
        // (smin:{ *:[i32] } (smax:{ *:[i32] } i32:{ *:[i32] }:$src0, i32:{ *:[i32] }:$src1), (smax:{ *:[i32] } i32:{ *:[i32] }:$src2, (smin:{ *:[i32] } i32:{ *:[i32] }:$src0, i32:{ *:[i32] }:$src1)))  =>  (V_MED3_I32_e64:{ *:[i32] } VSrc_b32:{ *:[i32] }:$src0, VSrc_b32:{ *:[i32] }:$src1, VSrc_b32:{ *:[i32] }:$src2)
        GIR_BuildMI, /*InsnID*/0, /*Opcode*/GIMT_Encode2(AMDGPU::V_MED3_I32_e64),
        GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/0, // DstI[vdst]
        GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/1, /*OpIdx*/1, // src0
        GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/1, /*OpIdx*/2, // src1
        GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/2, /*OpIdx*/1, // src2
        GIR_ConstrainSelectedInstOperands, /*InsnID*/0,
        GIR_EraseFromParent, /*InsnID*/0,
        // GIR_Coverage, 9941,
        GIR_Done,
      // Label 5281: @390267
      GIM_Try, /*On fail goto*//*Label 5282*/ GIMT_Encode4(390358), // Rule ID 9942 //
        GIM_CheckRegBankForClass, /*MI*/0, /*Op*/0, /*RC*/GIMT_Encode2(AMDGPU::VGPR_32RegClassID),
        GIM_RecordInsn, /*DefineMI*/1, /*MI*/0, /*OpIdx*/1, // MIs[1]
        GIM_CheckOpcode, /*MI*/1, GIMT_Encode2(TargetOpcode::G_SMAX),
        GIM_CheckType, /*MI*/1, /*Op*/1, /*Type*/GILLT_s32,
        GIM_CheckType, /*MI*/1, /*Op*/2, /*Type*/GILLT_s32,
        GIM_RecordInsn, /*DefineMI*/2, /*MI*/0, /*OpIdx*/2, // MIs[2]
        GIM_CheckOpcode, /*MI*/2, GIMT_Encode2(TargetOpcode::G_SMAX),
        GIM_CheckType, /*MI*/2, /*Op*/1, /*Type*/GILLT_s32,
        GIM_CheckType, /*MI*/2, /*Op*/2, /*Type*/GILLT_s32,
        GIM_RecordInsn, /*DefineMI*/3, /*MI*/2, /*OpIdx*/2, // MIs[3]
        GIM_CheckOpcode, /*MI*/3, GIMT_Encode2(TargetOpcode::G_SMIN),
        // MIs[3] src1
        GIM_CheckIsSameOperand, /*MI*/3, /*OpIdx*/1, /*OtherMI*/1, /*OtherOpIdx*/2,
        // MIs[3] src0
        GIM_CheckIsSameOperand, /*MI*/3, /*OpIdx*/2, /*OtherMI*/1, /*OtherOpIdx*/1,
        GIM_CheckIsSafeToFold, /*InsnID*/1,
        GIM_CheckIsSafeToFold, /*InsnID*/2,
        GIM_CheckIsSafeToFold, /*InsnID*/3,
        // (smin:{ *:[i32] } (smax:{ *:[i32] } i32:{ *:[i32] }:$src0, i32:{ *:[i32] }:$src1), (smax:{ *:[i32] } i32:{ *:[i32] }:$src2, (smin:{ *:[i32] } i32:{ *:[i32] }:$src1, i32:{ *:[i32] }:$src0)))  =>  (V_MED3_I32_e64:{ *:[i32] } VSrc_b32:{ *:[i32] }:$src0, VSrc_b32:{ *:[i32] }:$src1, VSrc_b32:{ *:[i32] }:$src2)
        GIR_BuildMI, /*InsnID*/0, /*Opcode*/GIMT_Encode2(AMDGPU::V_MED3_I32_e64),
        GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/0, // DstI[vdst]
        GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/1, /*OpIdx*/1, // src0
        GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/1, /*OpIdx*/2, // src1
        GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/2, /*OpIdx*/1, // src2
        GIR_ConstrainSelectedInstOperands, /*InsnID*/0,
        GIR_EraseFromParent, /*InsnID*/0,
        // GIR_Coverage, 9942,
        GIR_Done,
      // Label 5282: @390358
      GIM_Try, /*On fail goto*//*Label 5283*/ GIMT_Encode4(390449), // Rule ID 9945 //
        GIM_CheckRegBankForClass, /*MI*/0, /*Op*/0, /*RC*/GIMT_Encode2(AMDGPU::VGPR_32RegClassID),
        GIM_RecordInsn, /*DefineMI*/1, /*MI*/0, /*OpIdx*/1, // MIs[1]
        GIM_CheckOpcode, /*MI*/1, GIMT_Encode2(TargetOpcode::G_SMAX),
        GIM_CheckType, /*MI*/1, /*Op*/1, /*Type*/GILLT_s32,
        GIM_CheckType, /*MI*/1, /*Op*/2, /*Type*/GILLT_s32,
        GIM_RecordInsn, /*DefineMI*/2, /*MI*/0, /*OpIdx*/2, // MIs[2]
        GIM_CheckOpcode, /*MI*/2, GIMT_Encode2(TargetOpcode::G_SMAX),
        GIM_CheckType, /*MI*/2, /*Op*/1, /*Type*/GILLT_s32,
        GIM_CheckType, /*MI*/2, /*Op*/2, /*Type*/GILLT_s32,
        GIM_RecordInsn, /*DefineMI*/3, /*MI*/2, /*OpIdx*/2, // MIs[3]
        GIM_CheckOpcode, /*MI*/3, GIMT_Encode2(TargetOpcode::G_SMIN),
        // MIs[3] src0
        GIM_CheckIsSameOperand, /*MI*/3, /*OpIdx*/1, /*OtherMI*/1, /*OtherOpIdx*/2,
        // MIs[3] src1
        GIM_CheckIsSameOperand, /*MI*/3, /*OpIdx*/2, /*OtherMI*/1, /*OtherOpIdx*/1,
        GIM_CheckIsSafeToFold, /*InsnID*/1,
        GIM_CheckIsSafeToFold, /*InsnID*/2,
        GIM_CheckIsSafeToFold, /*InsnID*/3,
        // (smin:{ *:[i32] } (smax:{ *:[i32] } i32:{ *:[i32] }:$src1, i32:{ *:[i32] }:$src0), (smax:{ *:[i32] } i32:{ *:[i32] }:$src2, (smin:{ *:[i32] } i32:{ *:[i32] }:$src0, i32:{ *:[i32] }:$src1)))  =>  (V_MED3_I32_e64:{ *:[i32] } VSrc_b32:{ *:[i32] }:$src0, VSrc_b32:{ *:[i32] }:$src1, VSrc_b32:{ *:[i32] }:$src2)
        GIR_BuildMI, /*InsnID*/0, /*Opcode*/GIMT_Encode2(AMDGPU::V_MED3_I32_e64),
        GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/0, // DstI[vdst]
        GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/1, /*OpIdx*/2, // src0
        GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/1, /*OpIdx*/1, // src1
        GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/2, /*OpIdx*/1, // src2
        GIR_ConstrainSelectedInstOperands, /*InsnID*/0,
        GIR_EraseFromParent, /*InsnID*/0,
        // GIR_Coverage, 9945,
        GIR_Done,
      // Label 5283: @390449
      GIM_Try, /*On fail goto*//*Label 5284*/ GIMT_Encode4(390540), // Rule ID 9946 //
        GIM_CheckRegBankForClass, /*MI*/0, /*Op*/0, /*RC*/GIMT_Encode2(AMDGPU::VGPR_32RegClassID),
        GIM_RecordInsn, /*DefineMI*/1, /*MI*/0, /*OpIdx*/1, // MIs[1]
        GIM_CheckOpcode, /*MI*/1, GIMT_Encode2(TargetOpcode::G_SMAX),
        GIM_CheckType, /*MI*/1, /*Op*/1, /*Type*/GILLT_s32,
        GIM_CheckType, /*MI*/1, /*Op*/2, /*Type*/GILLT_s32,
        GIM_RecordInsn, /*DefineMI*/2, /*MI*/0, /*OpIdx*/2, // MIs[2]
        GIM_CheckOpcode, /*MI*/2, GIMT_Encode2(TargetOpcode::G_SMAX),
        GIM_CheckType, /*MI*/2, /*Op*/1, /*Type*/GILLT_s32,
        GIM_CheckType, /*MI*/2, /*Op*/2, /*Type*/GILLT_s32,
        GIM_RecordInsn, /*DefineMI*/3, /*MI*/2, /*OpIdx*/2, // MIs[3]
        GIM_CheckOpcode, /*MI*/3, GIMT_Encode2(TargetOpcode::G_SMIN),
        // MIs[3] src1
        GIM_CheckIsSameOperand, /*MI*/3, /*OpIdx*/1, /*OtherMI*/1, /*OtherOpIdx*/1,
        // MIs[3] src0
        GIM_CheckIsSameOperand, /*MI*/3, /*OpIdx*/2, /*OtherMI*/1, /*OtherOpIdx*/2,
        GIM_CheckIsSafeToFold, /*InsnID*/1,
        GIM_CheckIsSafeToFold, /*InsnID*/2,
        GIM_CheckIsSafeToFold, /*InsnID*/3,
        // (smin:{ *:[i32] } (smax:{ *:[i32] } i32:{ *:[i32] }:$src1, i32:{ *:[i32] }:$src0), (smax:{ *:[i32] } i32:{ *:[i32] }:$src2, (smin:{ *:[i32] } i32:{ *:[i32] }:$src1, i32:{ *:[i32] }:$src0)))  =>  (V_MED3_I32_e64:{ *:[i32] } VSrc_b32:{ *:[i32] }:$src0, VSrc_b32:{ *:[i32] }:$src1, VSrc_b32:{ *:[i32] }:$src2)
        GIR_BuildMI, /*InsnID*/0, /*Opcode*/GIMT_Encode2(AMDGPU::V_MED3_I32_e64),
        GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/0, // DstI[vdst]
        GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/1, /*OpIdx*/2, // src0
        GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/1, /*OpIdx*/1, // src1
        GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/2, /*OpIdx*/1, // src2
        GIR_ConstrainSelectedInstOperands, /*InsnID*/0,
        GIR_EraseFromParent, /*InsnID*/0,
        // GIR_Coverage, 9946,
        GIR_Done,
      // Label 5284: @390540
      GIM_Try, /*On fail goto*//*Label 5285*/ GIMT_Encode4(390604), // Rule ID 6516 //
        GIM_CheckFeatures, GIMT_Encode2(GIFBS_isGFX11Plus),
        GIM_CheckRegBankForClass, /*MI*/0, /*Op*/0, /*RC*/GIMT_Encode2(AMDGPU::VGPR_32RegClassID),
        GIM_RecordInsn, /*DefineMI*/1, /*MI*/0, /*OpIdx*/1, // MIs[1]
        GIM_CheckOpcode, /*MI*/1, GIMT_Encode2(TargetOpcode::G_SMAX),
        GIM_CheckType, /*MI*/1, /*Op*/1, /*Type*/GILLT_s32,
        GIM_CheckType, /*MI*/1, /*Op*/2, /*Type*/GILLT_s32,
        GIM_CheckCxxInsnPredicate, /*MI*/1, /*FnId*/GIMT_Encode2(GICXXPred_MI_Predicate_smax_oneuse),
        GIM_CheckCxxInsnPredicate, /*MI*/0, /*FnId*/GIMT_Encode2(GICXXPred_MI_Predicate_anonymous_35362),
        GIM_CheckIsSafeToFold, /*InsnID*/1,
        // (smin:{ *:[i32] } (smax:{ *:[i32] } i32:{ *:[i32] }:$src0, i32:{ *:[i32] }:$src1)<<P:Predicate_smax_oneuse>>, i32:{ *:[i32] }:$src2)<<P:Predicate_anonymous_35362>>  =>  (V_MAXMIN_I32_e64:{ *:[i32] } VSrc_b32:{ *:[i32] }:$src0, VSrc_b32:{ *:[i32] }:$src1, VSrc_b32:{ *:[i32] }:$src2)
        GIR_BuildMI, /*InsnID*/0, /*Opcode*/GIMT_Encode2(AMDGPU::V_MAXMIN_I32_e64),
        GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/0, // DstI[vdst]
        GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/1, /*OpIdx*/1, // src0
        GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/1, /*OpIdx*/2, // src1
        GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/2, // src2
        GIR_ConstrainSelectedInstOperands, /*InsnID*/0,
        GIR_EraseFromParent, /*InsnID*/0,
        // GIR_Coverage, 6516,
        GIR_Done,
      // Label 5285: @390604
      GIM_Try, /*On fail goto*//*Label 5286*/ GIMT_Encode4(390668), // Rule ID 10510 //
        GIM_CheckFeatures, GIMT_Encode2(GIFBS_isGFX11Plus),
        GIM_CheckRegBankForClass, /*MI*/0, /*Op*/0, /*RC*/GIMT_Encode2(AMDGPU::VGPR_32RegClassID),
        GIM_RecordInsn, /*DefineMI*/1, /*MI*/0, /*OpIdx*/2, // MIs[1]
        GIM_CheckOpcode, /*MI*/1, GIMT_Encode2(TargetOpcode::G_SMAX),
        GIM_CheckType, /*MI*/1, /*Op*/1, /*Type*/GILLT_s32,
        GIM_CheckType, /*MI*/1, /*Op*/2, /*Type*/GILLT_s32,
        GIM_CheckCxxInsnPredicate, /*MI*/1, /*FnId*/GIMT_Encode2(GICXXPred_MI_Predicate_smax_oneuse),
        GIM_CheckCxxInsnPredicate, /*MI*/0, /*FnId*/GIMT_Encode2(GICXXPred_MI_Predicate_anonymous_35362),
        GIM_CheckIsSafeToFold, /*InsnID*/1,
        // (smin:{ *:[i32] } i32:{ *:[i32] }:$src2, (smax:{ *:[i32] } i32:{ *:[i32] }:$src0, i32:{ *:[i32] }:$src1)<<P:Predicate_smax_oneuse>>)<<P:Predicate_anonymous_35362>>  =>  (V_MAXMIN_I32_e64:{ *:[i32] } VSrc_b32:{ *:[i32] }:$src0, VSrc_b32:{ *:[i32] }:$src1, VSrc_b32:{ *:[i32] }:$src2)
        GIR_BuildMI, /*InsnID*/0, /*Opcode*/GIMT_Encode2(AMDGPU::V_MAXMIN_I32_e64),
        GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/0, // DstI[vdst]
        GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/1, /*OpIdx*/1, // src0
        GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/1, /*OpIdx*/2, // src1
        GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/1, // src2
        GIR_ConstrainSelectedInstOperands, /*InsnID*/0,
        GIR_EraseFromParent, /*InsnID*/0,
        // GIR_Coverage, 10510,
        GIR_Done,
      // Label 5286: @390668
      GIM_Try, /*On fail goto*//*Label 5287*/ GIMT_Encode4(390696), // Rule ID 49 //
        GIM_CheckRegBankForClass, /*MI*/0, /*Op*/0, /*RC*/GIMT_Encode2(AMDGPU::SReg_32RegClassID),
        GIM_CheckCxxInsnPredicate, /*MI*/0, /*FnId*/GIMT_Encode2(GICXXPred_MI_Predicate_anonymous_17607),
        // (smin:{ *:[i32] } i32:{ *:[i32] }:$src0, i32:{ *:[i32] }:$src1)<<P:Predicate_anonymous_17607>>  =>  (S_MIN_I32:{ *:[i32] }:{ *:[i1] } i32:{ *:[i32] }:$src0, i32:{ *:[i32] }:$src1)
        GIR_MutateOpcode, /*InsnID*/0, /*RecycleInsnID*/0, /*Opcode*/GIMT_Encode2(AMDGPU::S_MIN_I32),
        GIR_AddImplicitDef, /*InsnID*/0, GIMT_Encode2(AMDGPU::SCC), GIMT_Encode2(RegState::Dead),
        GIR_ConstrainSelectedInstOperands, /*InsnID*/0,
        // GIR_Coverage, 49,
        GIR_Done,
      // Label 5287: @390696
      GIM_Try, /*On fail goto*//*Label 5288*/ GIMT_Encode4(390718), // Rule ID 743 //
        GIM_CheckRegBankForClass, /*MI*/0, /*Op*/0, /*RC*/GIMT_Encode2(AMDGPU::VGPR_32RegClassID),
        // (smin:{ *:[i32] } i32:{ *:[i32] }:$src0, i32:{ *:[i32] }:$src1)  =>  (V_MIN_I32_e64:{ *:[i32] } i32:{ *:[i32] }:$src0, i32:{ *:[i32] }:$src1)
        GIR_MutateOpcode, /*InsnID*/0, /*RecycleInsnID*/0, /*Opcode*/GIMT_Encode2(AMDGPU::V_MIN_I32_e64),
        GIR_AddImplicitUse, /*InsnID*/0, GIMT_Encode2(AMDGPU::EXEC),
        GIR_ConstrainSelectedInstOperands, /*InsnID*/0,
        // GIR_Coverage, 743,
        GIR_Done,
      // Label 5288: @390718
      GIM_Reject,
    // Label 5268: @390719
    GIM_Reject,
    // Label 5247: @390720
    GIM_Try, /*On fail goto*//*Label 5289*/ GIMT_Encode4(390800), // Rule ID 970 //
      GIM_CheckType, /*MI*/0, /*Op*/1, /*Type*/GILLT_v2s16,
      GIM_CheckType, /*MI*/0, /*Op*/2, /*Type*/GILLT_v2s16,
      GIM_CheckRegBankForClass, /*MI*/0, /*Op*/0, /*RC*/GIMT_Encode2(AMDGPU::VGPR_32RegClassID),
      GIM_CheckComplexPattern, /*MI*/0, /*Op*/1, /*Renderer*/GIMT_Encode2(0), GIMT_Encode2(GICP_gi_vop3pmods),
      GIM_CheckComplexPattern, /*MI*/0, /*Op*/2, /*Renderer*/GIMT_Encode2(1), GIMT_Encode2(GICP_gi_vop3pmods),
      // (smin:{ *:[v2i16] } (VOP3PMods:{ *:[v2i16] } v2i16:{ *:[v2i16] }:$src0, i32:{ *:[i32] }:$src0_modifiers), (VOP3PMods:{ *:[v2i16] } v2i16:{ *:[v2i16] }:$src1, i32:{ *:[i32] }:$src1_modifiers))  =>  (V_PK_MIN_I16:{ *:[v2i16] } i32:{ *:[i32] }:$src0_modifiers, v2i16:{ *:[v2i16] }:$src0, i32:{ *:[i32] }:$src1_modifiers, v2i16:{ *:[v2i16] }:$src1)
      GIR_BuildMI, /*InsnID*/0, /*Opcode*/GIMT_Encode2(AMDGPU::V_PK_MIN_I16),
      GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/0, // DstI[vdst]
      GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/1, // src0_modifiers
      GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/0, // src0
      GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(1), /*SubOperand*/1, // src1_modifiers
      GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(1), /*SubOperand*/0, // src1
      GIR_AddImm8, /*InsnID*/0, /*Imm*/0,
      GIR_AddImm8, /*InsnID*/0, /*Imm*/0,
      GIR_AddImm8, /*InsnID*/0, /*Imm*/0,
      GIR_AddImm8, /*InsnID*/0, /*Imm*/0,
      GIR_AddImm8, /*InsnID*/0, /*Imm*/0,
      GIR_ConstrainSelectedInstOperands, /*InsnID*/0,
      GIR_EraseFromParent, /*InsnID*/0,
      // GIR_Coverage, 970,
      GIR_Done,
    // Label 5289: @390800
    GIM_Reject,
    // Label 5248: @390801
    GIM_Reject,
    // Label 85: @390802
    GIM_SwitchType, /*MI*/0, /*Op*/0, /*[*/GIMT_Encode2(8), GIMT_Encode2(12), /*)*//*default:*//*Label 5293*/ GIMT_Encode4(394481),
    /*GILLT_s16*//*Label 5290*/ GIMT_Encode4(390829),
    /*GILLT_s32*//*Label 5291*/ GIMT_Encode4(392553), GIMT_Encode4(0),
    /*GILLT_v2s16*//*Label 5292*/ GIMT_Encode4(394400),
    // Label 5290: @390829
    GIM_Try, /*On fail goto*//*Label 5294*/ GIMT_Encode4(392552),
      GIM_CheckType, /*MI*/0, /*Op*/1, /*Type*/GILLT_s16,
      GIM_CheckType, /*MI*/0, /*Op*/2, /*Type*/GILLT_s16,
      GIM_CheckRegBankForClass, /*MI*/0, /*Op*/0, /*RC*/GIMT_Encode2(AMDGPU::VGPR_32RegClassID),
      GIM_Try, /*On fail goto*//*Label 5295*/ GIMT_Encode4(390951), // Rule ID 10487 //
        GIM_CheckFeatures, GIMT_Encode2(GIFBS_isGFX9Plus),
        GIM_RecordInsn, /*DefineMI*/1, /*MI*/0, /*OpIdx*/1, // MIs[1]
        GIM_CheckOpcode, /*MI*/1, GIMT_Encode2(TargetOpcode::G_SMIN),
        GIM_CheckType, /*MI*/1, /*Op*/1, /*Type*/GILLT_s16,
        GIM_CheckType, /*MI*/1, /*Op*/2, /*Type*/GILLT_s16,
        GIM_RecordInsn, /*DefineMI*/2, /*MI*/1, /*OpIdx*/1, // MIs[2]
        GIM_CheckOpcode, /*MI*/2, GIMT_Encode2(TargetOpcode::G_SMAX),
        GIM_CheckType, /*MI*/2, /*Op*/1, /*Type*/GILLT_s16,
        GIM_CheckType, /*MI*/2, /*Op*/2, /*Type*/GILLT_s16,
        GIM_RecordInsn, /*DefineMI*/3, /*MI*/0, /*OpIdx*/2, // MIs[3]
        GIM_CheckOpcode, /*MI*/3, GIMT_Encode2(TargetOpcode::G_SMIN),
        // MIs[3] src0
        GIM_CheckIsSameOperand, /*MI*/3, /*OpIdx*/1, /*OtherMI*/2, /*OtherOpIdx*/1,
        // MIs[3] src1
        GIM_CheckIsSameOperand, /*MI*/3, /*OpIdx*/2, /*OtherMI*/2, /*OtherOpIdx*/2,
        GIM_CheckIsSafeToFold, /*InsnID*/1,
        GIM_CheckIsSafeToFold, /*InsnID*/2,
        GIM_CheckIsSafeToFold, /*InsnID*/3,
        // (smax:{ *:[i16] } (smin:{ *:[i16] } (smax:{ *:[i16] } i16:{ *:[i16] }:$src0, i16:{ *:[i16] }:$src1), i16:{ *:[i16] }:$src2), (smin:{ *:[i16] } i16:{ *:[i16] }:$src0, i16:{ *:[i16] }:$src1))  =>  (V_MED3_I16_e64:{ *:[i16] } 0:{ *:[i32] }, VSrc_b16:{ *:[i16] }:$src0, 0:{ *:[i32] }, VSrc_b16:{ *:[i16] }:$src1, 0:{ *:[i32] }, VSrc_b16:{ *:[i16] }:$src2, 0:{ *:[i1] })
        GIR_BuildMI, /*InsnID*/0, /*Opcode*/GIMT_Encode2(AMDGPU::V_MED3_I16_e64),
        GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/0, // DstI[vdst]
        GIR_AddImm8, /*InsnID*/0, /*Imm*/0,
        GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/2, /*OpIdx*/1, // src0
        GIR_AddImm8, /*InsnID*/0, /*Imm*/0,
        GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/2, /*OpIdx*/2, // src1
        GIR_AddImm8, /*InsnID*/0, /*Imm*/0,
        GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/1, /*OpIdx*/2, // src2
        GIR_AddImm8, /*InsnID*/0, /*Imm*/0,
        GIR_AddImm8, /*InsnID*/0, /*Imm*/0,
        GIR_ConstrainSelectedInstOperands, /*InsnID*/0,
        GIR_EraseFromParent, /*InsnID*/0,
        // GIR_Coverage, 10487,
        GIR_Done,
      // Label 5295: @390951
      GIM_Try, /*On fail goto*//*Label 5296*/ GIMT_Encode4(391055), // Rule ID 10488 //
        GIM_CheckFeatures, GIMT_Encode2(GIFBS_isGFX9Plus),
        GIM_RecordInsn, /*DefineMI*/1, /*MI*/0, /*OpIdx*/1, // MIs[1]
        GIM_CheckOpcode, /*MI*/1, GIMT_Encode2(TargetOpcode::G_SMIN),
        GIM_CheckType, /*MI*/1, /*Op*/1, /*Type*/GILLT_s16,
        GIM_CheckType, /*MI*/1, /*Op*/2, /*Type*/GILLT_s16,
        GIM_RecordInsn, /*DefineMI*/2, /*MI*/1, /*OpIdx*/1, // MIs[2]
        GIM_CheckOpcode, /*MI*/2, GIMT_Encode2(TargetOpcode::G_SMAX),
        GIM_CheckType, /*MI*/2, /*Op*/1, /*Type*/GILLT_s16,
        GIM_CheckType, /*MI*/2, /*Op*/2, /*Type*/GILLT_s16,
        GIM_RecordInsn, /*DefineMI*/3, /*MI*/0, /*OpIdx*/2, // MIs[3]
        GIM_CheckOpcode, /*MI*/3, GIMT_Encode2(TargetOpcode::G_SMIN),
        // MIs[3] src1
        GIM_CheckIsSameOperand, /*MI*/3, /*OpIdx*/1, /*OtherMI*/2, /*OtherOpIdx*/2,
        // MIs[3] src0
        GIM_CheckIsSameOperand, /*MI*/3, /*OpIdx*/2, /*OtherMI*/2, /*OtherOpIdx*/1,
        GIM_CheckIsSafeToFold, /*InsnID*/1,
        GIM_CheckIsSafeToFold, /*InsnID*/2,
        GIM_CheckIsSafeToFold, /*InsnID*/3,
        // (smax:{ *:[i16] } (smin:{ *:[i16] } (smax:{ *:[i16] } i16:{ *:[i16] }:$src0, i16:{ *:[i16] }:$src1), i16:{ *:[i16] }:$src2), (smin:{ *:[i16] } i16:{ *:[i16] }:$src1, i16:{ *:[i16] }:$src0))  =>  (V_MED3_I16_e64:{ *:[i16] } 0:{ *:[i32] }, VSrc_b16:{ *:[i16] }:$src0, 0:{ *:[i32] }, VSrc_b16:{ *:[i16] }:$src1, 0:{ *:[i32] }, VSrc_b16:{ *:[i16] }:$src2, 0:{ *:[i1] })
        GIR_BuildMI, /*InsnID*/0, /*Opcode*/GIMT_Encode2(AMDGPU::V_MED3_I16_e64),
        GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/0, // DstI[vdst]
        GIR_AddImm8, /*InsnID*/0, /*Imm*/0,
        GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/2, /*OpIdx*/1, // src0
        GIR_AddImm8, /*InsnID*/0, /*Imm*/0,
        GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/2, /*OpIdx*/2, // src1
        GIR_AddImm8, /*InsnID*/0, /*Imm*/0,
        GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/1, /*OpIdx*/2, // src2
        GIR_AddImm8, /*InsnID*/0, /*Imm*/0,
        GIR_AddImm8, /*InsnID*/0, /*Imm*/0,
        GIR_ConstrainSelectedInstOperands, /*InsnID*/0,
        GIR_EraseFromParent, /*InsnID*/0,
        // GIR_Coverage, 10488,
        GIR_Done,
      // Label 5296: @391055
      GIM_Try, /*On fail goto*//*Label 5297*/ GIMT_Encode4(391159), // Rule ID 10489 //
        GIM_CheckFeatures, GIMT_Encode2(GIFBS_isGFX9Plus),
        GIM_RecordInsn, /*DefineMI*/1, /*MI*/0, /*OpIdx*/1, // MIs[1]
        GIM_CheckOpcode, /*MI*/1, GIMT_Encode2(TargetOpcode::G_SMIN),
        GIM_CheckType, /*MI*/1, /*Op*/1, /*Type*/GILLT_s16,
        GIM_CheckType, /*MI*/1, /*Op*/2, /*Type*/GILLT_s16,
        GIM_RecordInsn, /*DefineMI*/2, /*MI*/1, /*OpIdx*/1, // MIs[2]
        GIM_CheckOpcode, /*MI*/2, GIMT_Encode2(TargetOpcode::G_SMAX),
        GIM_CheckType, /*MI*/2, /*Op*/1, /*Type*/GILLT_s16,
        GIM_CheckType, /*MI*/2, /*Op*/2, /*Type*/GILLT_s16,
        GIM_RecordInsn, /*DefineMI*/3, /*MI*/0, /*OpIdx*/2, // MIs[3]
        GIM_CheckOpcode, /*MI*/3, GIMT_Encode2(TargetOpcode::G_SMIN),
        // MIs[3] src0
        GIM_CheckIsSameOperand, /*MI*/3, /*OpIdx*/1, /*OtherMI*/2, /*OtherOpIdx*/2,
        // MIs[3] src1
        GIM_CheckIsSameOperand, /*MI*/3, /*OpIdx*/2, /*OtherMI*/2, /*OtherOpIdx*/1,
        GIM_CheckIsSafeToFold, /*InsnID*/1,
        GIM_CheckIsSafeToFold, /*InsnID*/2,
        GIM_CheckIsSafeToFold, /*InsnID*/3,
        // (smax:{ *:[i16] } (smin:{ *:[i16] } (smax:{ *:[i16] } i16:{ *:[i16] }:$src1, i16:{ *:[i16] }:$src0), i16:{ *:[i16] }:$src2), (smin:{ *:[i16] } i16:{ *:[i16] }:$src0, i16:{ *:[i16] }:$src1))  =>  (V_MED3_I16_e64:{ *:[i16] } 0:{ *:[i32] }, VSrc_b16:{ *:[i16] }:$src0, 0:{ *:[i32] }, VSrc_b16:{ *:[i16] }:$src1, 0:{ *:[i32] }, VSrc_b16:{ *:[i16] }:$src2, 0:{ *:[i1] })
        GIR_BuildMI, /*InsnID*/0, /*Opcode*/GIMT_Encode2(AMDGPU::V_MED3_I16_e64),
        GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/0, // DstI[vdst]
        GIR_AddImm8, /*InsnID*/0, /*Imm*/0,
        GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/2, /*OpIdx*/2, // src0
        GIR_AddImm8, /*InsnID*/0, /*Imm*/0,
        GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/2, /*OpIdx*/1, // src1
        GIR_AddImm8, /*InsnID*/0, /*Imm*/0,
        GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/1, /*OpIdx*/2, // src2
        GIR_AddImm8, /*InsnID*/0, /*Imm*/0,
        GIR_AddImm8, /*InsnID*/0, /*Imm*/0,
        GIR_ConstrainSelectedInstOperands, /*InsnID*/0,
        GIR_EraseFromParent, /*InsnID*/0,
        // GIR_Coverage, 10489,
        GIR_Done,
      // Label 5297: @391159
      GIM_Try, /*On fail goto*//*Label 5298*/ GIMT_Encode4(391263), // Rule ID 10490 //
        GIM_CheckFeatures, GIMT_Encode2(GIFBS_isGFX9Plus),
        GIM_RecordInsn, /*DefineMI*/1, /*MI*/0, /*OpIdx*/1, // MIs[1]
        GIM_CheckOpcode, /*MI*/1, GIMT_Encode2(TargetOpcode::G_SMIN),
        GIM_CheckType, /*MI*/1, /*Op*/1, /*Type*/GILLT_s16,
        GIM_CheckType, /*MI*/1, /*Op*/2, /*Type*/GILLT_s16,
        GIM_RecordInsn, /*DefineMI*/2, /*MI*/1, /*OpIdx*/1, // MIs[2]
        GIM_CheckOpcode, /*MI*/2, GIMT_Encode2(TargetOpcode::G_SMAX),
        GIM_CheckType, /*MI*/2, /*Op*/1, /*Type*/GILLT_s16,
        GIM_CheckType, /*MI*/2, /*Op*/2, /*Type*/GILLT_s16,
        GIM_RecordInsn, /*DefineMI*/3, /*MI*/0, /*OpIdx*/2, // MIs[3]
        GIM_CheckOpcode, /*MI*/3, GIMT_Encode2(TargetOpcode::G_SMIN),
        // MIs[3] src1
        GIM_CheckIsSameOperand, /*MI*/3, /*OpIdx*/1, /*OtherMI*/2, /*OtherOpIdx*/1,
        // MIs[3] src0
        GIM_CheckIsSameOperand, /*MI*/3, /*OpIdx*/2, /*OtherMI*/2, /*OtherOpIdx*/2,
        GIM_CheckIsSafeToFold, /*InsnID*/1,
        GIM_CheckIsSafeToFold, /*InsnID*/2,
        GIM_CheckIsSafeToFold, /*InsnID*/3,
        // (smax:{ *:[i16] } (smin:{ *:[i16] } (smax:{ *:[i16] } i16:{ *:[i16] }:$src1, i16:{ *:[i16] }:$src0), i16:{ *:[i16] }:$src2), (smin:{ *:[i16] } i16:{ *:[i16] }:$src1, i16:{ *:[i16] }:$src0))  =>  (V_MED3_I16_e64:{ *:[i16] } 0:{ *:[i32] }, VSrc_b16:{ *:[i16] }:$src0, 0:{ *:[i32] }, VSrc_b16:{ *:[i16] }:$src1, 0:{ *:[i32] }, VSrc_b16:{ *:[i16] }:$src2, 0:{ *:[i1] })
        GIR_BuildMI, /*InsnID*/0, /*Opcode*/GIMT_Encode2(AMDGPU::V_MED3_I16_e64),
        GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/0, // DstI[vdst]
        GIR_AddImm8, /*InsnID*/0, /*Imm*/0,
        GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/2, /*OpIdx*/2, // src0
        GIR_AddImm8, /*InsnID*/0, /*Imm*/0,
        GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/2, /*OpIdx*/1, // src1
        GIR_AddImm8, /*InsnID*/0, /*Imm*/0,
        GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/1, /*OpIdx*/2, // src2
        GIR_AddImm8, /*InsnID*/0, /*Imm*/0,
        GIR_AddImm8, /*InsnID*/0, /*Imm*/0,
        GIR_ConstrainSelectedInstOperands, /*InsnID*/0,
        GIR_EraseFromParent, /*InsnID*/0,
        // GIR_Coverage, 10490,
        GIR_Done,
      // Label 5298: @391263
      GIM_Try, /*On fail goto*//*Label 5299*/ GIMT_Encode4(391367), // Rule ID 10491 //
        GIM_CheckFeatures, GIMT_Encode2(GIFBS_isGFX9Plus),
        GIM_RecordInsn, /*DefineMI*/1, /*MI*/0, /*OpIdx*/1, // MIs[1]
        GIM_CheckOpcode, /*MI*/1, GIMT_Encode2(TargetOpcode::G_SMIN),
        GIM_CheckType, /*MI*/1, /*Op*/1, /*Type*/GILLT_s16,
        GIM_CheckType, /*MI*/1, /*Op*/2, /*Type*/GILLT_s16,
        GIM_RecordInsn, /*DefineMI*/2, /*MI*/1, /*OpIdx*/2, // MIs[2]
        GIM_CheckOpcode, /*MI*/2, GIMT_Encode2(TargetOpcode::G_SMAX),
        GIM_CheckType, /*MI*/2, /*Op*/1, /*Type*/GILLT_s16,
        GIM_CheckType, /*MI*/2, /*Op*/2, /*Type*/GILLT_s16,
        GIM_RecordInsn, /*DefineMI*/3, /*MI*/0, /*OpIdx*/2, // MIs[3]
        GIM_CheckOpcode, /*MI*/3, GIMT_Encode2(TargetOpcode::G_SMIN),
        // MIs[3] src0
        GIM_CheckIsSameOperand, /*MI*/3, /*OpIdx*/1, /*OtherMI*/2, /*OtherOpIdx*/1,
        // MIs[3] src1
        GIM_CheckIsSameOperand, /*MI*/3, /*OpIdx*/2, /*OtherMI*/2, /*OtherOpIdx*/2,
        GIM_CheckIsSafeToFold, /*InsnID*/1,
        GIM_CheckIsSafeToFold, /*InsnID*/2,
        GIM_CheckIsSafeToFold, /*InsnID*/3,
        // (smax:{ *:[i16] } (smin:{ *:[i16] } i16:{ *:[i16] }:$src2, (smax:{ *:[i16] } i16:{ *:[i16] }:$src0, i16:{ *:[i16] }:$src1)), (smin:{ *:[i16] } i16:{ *:[i16] }:$src0, i16:{ *:[i16] }:$src1))  =>  (V_MED3_I16_e64:{ *:[i16] } 0:{ *:[i32] }, VSrc_b16:{ *:[i16] }:$src0, 0:{ *:[i32] }, VSrc_b16:{ *:[i16] }:$src1, 0:{ *:[i32] }, VSrc_b16:{ *:[i16] }:$src2, 0:{ *:[i1] })
        GIR_BuildMI, /*InsnID*/0, /*Opcode*/GIMT_Encode2(AMDGPU::V_MED3_I16_e64),
        GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/0, // DstI[vdst]
        GIR_AddImm8, /*InsnID*/0, /*Imm*/0,
        GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/2, /*OpIdx*/1, // src0
        GIR_AddImm8, /*InsnID*/0, /*Imm*/0,
        GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/2, /*OpIdx*/2, // src1
        GIR_AddImm8, /*InsnID*/0, /*Imm*/0,
        GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/1, /*OpIdx*/1, // src2
        GIR_AddImm8, /*InsnID*/0, /*Imm*/0,
        GIR_AddImm8, /*InsnID*/0, /*Imm*/0,
        GIR_ConstrainSelectedInstOperands, /*InsnID*/0,
        GIR_EraseFromParent, /*InsnID*/0,
        // GIR_Coverage, 10491,
        GIR_Done,
      // Label 5299: @391367
      GIM_Try, /*On fail goto*//*Label 5300*/ GIMT_Encode4(391471), // Rule ID 10492 //
        GIM_CheckFeatures, GIMT_Encode2(GIFBS_isGFX9Plus),
        GIM_RecordInsn, /*DefineMI*/1, /*MI*/0, /*OpIdx*/1, // MIs[1]
        GIM_CheckOpcode, /*MI*/1, GIMT_Encode2(TargetOpcode::G_SMIN),
        GIM_CheckType, /*MI*/1, /*Op*/1, /*Type*/GILLT_s16,
        GIM_CheckType, /*MI*/1, /*Op*/2, /*Type*/GILLT_s16,
        GIM_RecordInsn, /*DefineMI*/2, /*MI*/1, /*OpIdx*/2, // MIs[2]
        GIM_CheckOpcode, /*MI*/2, GIMT_Encode2(TargetOpcode::G_SMAX),
        GIM_CheckType, /*MI*/2, /*Op*/1, /*Type*/GILLT_s16,
        GIM_CheckType, /*MI*/2, /*Op*/2, /*Type*/GILLT_s16,
        GIM_RecordInsn, /*DefineMI*/3, /*MI*/0, /*OpIdx*/2, // MIs[3]
        GIM_CheckOpcode, /*MI*/3, GIMT_Encode2(TargetOpcode::G_SMIN),
        // MIs[3] src1
        GIM_CheckIsSameOperand, /*MI*/3, /*OpIdx*/1, /*OtherMI*/2, /*OtherOpIdx*/2,
        // MIs[3] src0
        GIM_CheckIsSameOperand, /*MI*/3, /*OpIdx*/2, /*OtherMI*/2, /*OtherOpIdx*/1,
        GIM_CheckIsSafeToFold, /*InsnID*/1,
        GIM_CheckIsSafeToFold, /*InsnID*/2,
        GIM_CheckIsSafeToFold, /*InsnID*/3,
        // (smax:{ *:[i16] } (smin:{ *:[i16] } i16:{ *:[i16] }:$src2, (smax:{ *:[i16] } i16:{ *:[i16] }:$src0, i16:{ *:[i16] }:$src1)), (smin:{ *:[i16] } i16:{ *:[i16] }:$src1, i16:{ *:[i16] }:$src0))  =>  (V_MED3_I16_e64:{ *:[i16] } 0:{ *:[i32] }, VSrc_b16:{ *:[i16] }:$src0, 0:{ *:[i32] }, VSrc_b16:{ *:[i16] }:$src1, 0:{ *:[i32] }, VSrc_b16:{ *:[i16] }:$src2, 0:{ *:[i1] })
        GIR_BuildMI, /*InsnID*/0, /*Opcode*/GIMT_Encode2(AMDGPU::V_MED3_I16_e64),
        GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/0, // DstI[vdst]
        GIR_AddImm8, /*InsnID*/0, /*Imm*/0,
        GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/2, /*OpIdx*/1, // src0
        GIR_AddImm8, /*InsnID*/0, /*Imm*/0,
        GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/2, /*OpIdx*/2, // src1
        GIR_AddImm8, /*InsnID*/0, /*Imm*/0,
        GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/1, /*OpIdx*/1, // src2
        GIR_AddImm8, /*InsnID*/0, /*Imm*/0,
        GIR_AddImm8, /*InsnID*/0, /*Imm*/0,
        GIR_ConstrainSelectedInstOperands, /*InsnID*/0,
        GIR_EraseFromParent, /*InsnID*/0,
        // GIR_Coverage, 10492,
        GIR_Done,
      // Label 5300: @391471
      GIM_Try, /*On fail goto*//*Label 5301*/ GIMT_Encode4(391575), // Rule ID 10493 //
        GIM_CheckFeatures, GIMT_Encode2(GIFBS_isGFX9Plus),
        GIM_RecordInsn, /*DefineMI*/1, /*MI*/0, /*OpIdx*/1, // MIs[1]
        GIM_CheckOpcode, /*MI*/1, GIMT_Encode2(TargetOpcode::G_SMIN),
        GIM_CheckType, /*MI*/1, /*Op*/1, /*Type*/GILLT_s16,
        GIM_CheckType, /*MI*/1, /*Op*/2, /*Type*/GILLT_s16,
        GIM_RecordInsn, /*DefineMI*/2, /*MI*/1, /*OpIdx*/2, // MIs[2]
        GIM_CheckOpcode, /*MI*/2, GIMT_Encode2(TargetOpcode::G_SMAX),
        GIM_CheckType, /*MI*/2, /*Op*/1, /*Type*/GILLT_s16,
        GIM_CheckType, /*MI*/2, /*Op*/2, /*Type*/GILLT_s16,
        GIM_RecordInsn, /*DefineMI*/3, /*MI*/0, /*OpIdx*/2, // MIs[3]
        GIM_CheckOpcode, /*MI*/3, GIMT_Encode2(TargetOpcode::G_SMIN),
        // MIs[3] src0
        GIM_CheckIsSameOperand, /*MI*/3, /*OpIdx*/1, /*OtherMI*/2, /*OtherOpIdx*/2,
        // MIs[3] src1
        GIM_CheckIsSameOperand, /*MI*/3, /*OpIdx*/2, /*OtherMI*/2, /*OtherOpIdx*/1,
        GIM_CheckIsSafeToFold, /*InsnID*/1,
        GIM_CheckIsSafeToFold, /*InsnID*/2,
        GIM_CheckIsSafeToFold, /*InsnID*/3,
        // (smax:{ *:[i16] } (smin:{ *:[i16] } i16:{ *:[i16] }:$src2, (smax:{ *:[i16] } i16:{ *:[i16] }:$src1, i16:{ *:[i16] }:$src0)), (smin:{ *:[i16] } i16:{ *:[i16] }:$src0, i16:{ *:[i16] }:$src1))  =>  (V_MED3_I16_e64:{ *:[i16] } 0:{ *:[i32] }, VSrc_b16:{ *:[i16] }:$src0, 0:{ *:[i32] }, VSrc_b16:{ *:[i16] }:$src1, 0:{ *:[i32] }, VSrc_b16:{ *:[i16] }:$src2, 0:{ *:[i1] })
        GIR_BuildMI, /*InsnID*/0, /*Opcode*/GIMT_Encode2(AMDGPU::V_MED3_I16_e64),
        GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/0, // DstI[vdst]
        GIR_AddImm8, /*InsnID*/0, /*Imm*/0,
        GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/2, /*OpIdx*/2, // src0
        GIR_AddImm8, /*InsnID*/0, /*Imm*/0,
        GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/2, /*OpIdx*/1, // src1
        GIR_AddImm8, /*InsnID*/0, /*Imm*/0,
        GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/1, /*OpIdx*/1, // src2
        GIR_AddImm8, /*InsnID*/0, /*Imm*/0,
        GIR_AddImm8, /*InsnID*/0, /*Imm*/0,
        GIR_ConstrainSelectedInstOperands, /*InsnID*/0,
        GIR_EraseFromParent, /*InsnID*/0,
        // GIR_Coverage, 10493,
        GIR_Done,
      // Label 5301: @391575
      GIM_Try, /*On fail goto*//*Label 5302*/ GIMT_Encode4(391679), // Rule ID 10494 //
        GIM_CheckFeatures, GIMT_Encode2(GIFBS_isGFX9Plus),
        GIM_RecordInsn, /*DefineMI*/1, /*MI*/0, /*OpIdx*/1, // MIs[1]
        GIM_CheckOpcode, /*MI*/1, GIMT_Encode2(TargetOpcode::G_SMIN),
        GIM_CheckType, /*MI*/1, /*Op*/1, /*Type*/GILLT_s16,
        GIM_CheckType, /*MI*/1, /*Op*/2, /*Type*/GILLT_s16,
        GIM_RecordInsn, /*DefineMI*/2, /*MI*/1, /*OpIdx*/2, // MIs[2]
        GIM_CheckOpcode, /*MI*/2, GIMT_Encode2(TargetOpcode::G_SMAX),
        GIM_CheckType, /*MI*/2, /*Op*/1, /*Type*/GILLT_s16,
        GIM_CheckType, /*MI*/2, /*Op*/2, /*Type*/GILLT_s16,
        GIM_RecordInsn, /*DefineMI*/3, /*MI*/0, /*OpIdx*/2, // MIs[3]
        GIM_CheckOpcode, /*MI*/3, GIMT_Encode2(TargetOpcode::G_SMIN),
        // MIs[3] src1
        GIM_CheckIsSameOperand, /*MI*/3, /*OpIdx*/1, /*OtherMI*/2, /*OtherOpIdx*/1,
        // MIs[3] src0
        GIM_CheckIsSameOperand, /*MI*/3, /*OpIdx*/2, /*OtherMI*/2, /*OtherOpIdx*/2,
        GIM_CheckIsSafeToFold, /*InsnID*/1,
        GIM_CheckIsSafeToFold, /*InsnID*/2,
        GIM_CheckIsSafeToFold, /*InsnID*/3,
        // (smax:{ *:[i16] } (smin:{ *:[i16] } i16:{ *:[i16] }:$src2, (smax:{ *:[i16] } i16:{ *:[i16] }:$src1, i16:{ *:[i16] }:$src0)), (smin:{ *:[i16] } i16:{ *:[i16] }:$src1, i16:{ *:[i16] }:$src0))  =>  (V_MED3_I16_e64:{ *:[i16] } 0:{ *:[i32] }, VSrc_b16:{ *:[i16] }:$src0, 0:{ *:[i32] }, VSrc_b16:{ *:[i16] }:$src1, 0:{ *:[i32] }, VSrc_b16:{ *:[i16] }:$src2, 0:{ *:[i1] })
        GIR_BuildMI, /*InsnID*/0, /*Opcode*/GIMT_Encode2(AMDGPU::V_MED3_I16_e64),
        GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/0, // DstI[vdst]
        GIR_AddImm8, /*InsnID*/0, /*Imm*/0,
        GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/2, /*OpIdx*/2, // src0
        GIR_AddImm8, /*InsnID*/0, /*Imm*/0,
        GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/2, /*OpIdx*/1, // src1
        GIR_AddImm8, /*InsnID*/0, /*Imm*/0,
        GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/1, /*OpIdx*/1, // src2
        GIR_AddImm8, /*InsnID*/0, /*Imm*/0,
        GIR_AddImm8, /*InsnID*/0, /*Imm*/0,
        GIR_ConstrainSelectedInstOperands, /*InsnID*/0,
        GIR_EraseFromParent, /*InsnID*/0,
        // GIR_Coverage, 10494,
        GIR_Done,
      // Label 5302: @391679
      GIM_Try, /*On fail goto*//*Label 5303*/ GIMT_Encode4(391783), // Rule ID 6514 //
        GIM_CheckFeatures, GIMT_Encode2(GIFBS_isGFX9Plus),
        GIM_RecordInsn, /*DefineMI*/1, /*MI*/0, /*OpIdx*/1, // MIs[1]
        GIM_CheckOpcode, /*MI*/1, GIMT_Encode2(TargetOpcode::G_SMIN),
        GIM_CheckType, /*MI*/1, /*Op*/1, /*Type*/GILLT_s16,
        GIM_CheckType, /*MI*/1, /*Op*/2, /*Type*/GILLT_s16,
        GIM_RecordInsn, /*DefineMI*/2, /*MI*/0, /*OpIdx*/2, // MIs[2]
        GIM_CheckOpcode, /*MI*/2, GIMT_Encode2(TargetOpcode::G_SMIN),
        GIM_CheckType, /*MI*/2, /*Op*/1, /*Type*/GILLT_s16,
        GIM_CheckType, /*MI*/2, /*Op*/2, /*Type*/GILLT_s16,
        GIM_RecordInsn, /*DefineMI*/3, /*MI*/2, /*OpIdx*/1, // MIs[3]
        GIM_CheckOpcode, /*MI*/3, GIMT_Encode2(TargetOpcode::G_SMAX),
        // MIs[3] src0
        GIM_CheckIsSameOperand, /*MI*/3, /*OpIdx*/1, /*OtherMI*/1, /*OtherOpIdx*/1,
        // MIs[3] src1
        GIM_CheckIsSameOperand, /*MI*/3, /*OpIdx*/2, /*OtherMI*/1, /*OtherOpIdx*/2,
        GIM_CheckIsSafeToFold, /*InsnID*/1,
        GIM_CheckIsSafeToFold, /*InsnID*/2,
        GIM_CheckIsSafeToFold, /*InsnID*/3,
        // (smax:{ *:[i16] } (smin:{ *:[i16] } i16:{ *:[i16] }:$src0, i16:{ *:[i16] }:$src1), (smin:{ *:[i16] } (smax:{ *:[i16] } i16:{ *:[i16] }:$src0, i16:{ *:[i16] }:$src1), i16:{ *:[i16] }:$src2))  =>  (V_MED3_I16_e64:{ *:[i16] } 0:{ *:[i32] }, VSrc_b16:{ *:[i16] }:$src0, 0:{ *:[i32] }, VSrc_b16:{ *:[i16] }:$src1, 0:{ *:[i32] }, VSrc_b16:{ *:[i16] }:$src2, 0:{ *:[i1] })
        GIR_BuildMI, /*InsnID*/0, /*Opcode*/GIMT_Encode2(AMDGPU::V_MED3_I16_e64),
        GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/0, // DstI[vdst]
        GIR_AddImm8, /*InsnID*/0, /*Imm*/0,
        GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/1, /*OpIdx*/1, // src0
        GIR_AddImm8, /*InsnID*/0, /*Imm*/0,
        GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/1, /*OpIdx*/2, // src1
        GIR_AddImm8, /*InsnID*/0, /*Imm*/0,
        GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/2, /*OpIdx*/2, // src2
        GIR_AddImm8, /*InsnID*/0, /*Imm*/0,
        GIR_AddImm8, /*InsnID*/0, /*Imm*/0,
        GIR_ConstrainSelectedInstOperands, /*InsnID*/0,
        GIR_EraseFromParent, /*InsnID*/0,
        // GIR_Coverage, 6514,
        GIR_Done,
      // Label 5303: @391783
      GIM_Try, /*On fail goto*//*Label 5304*/ GIMT_Encode4(391887), // Rule ID 10480 //
        GIM_CheckFeatures, GIMT_Encode2(GIFBS_isGFX9Plus),
        GIM_RecordInsn, /*DefineMI*/1, /*MI*/0, /*OpIdx*/1, // MIs[1]
        GIM_CheckOpcode, /*MI*/1, GIMT_Encode2(TargetOpcode::G_SMIN),
        GIM_CheckType, /*MI*/1, /*Op*/1, /*Type*/GILLT_s16,
        GIM_CheckType, /*MI*/1, /*Op*/2, /*Type*/GILLT_s16,
        GIM_RecordInsn, /*DefineMI*/2, /*MI*/0, /*OpIdx*/2, // MIs[2]
        GIM_CheckOpcode, /*MI*/2, GIMT_Encode2(TargetOpcode::G_SMIN),
        GIM_CheckType, /*MI*/2, /*Op*/1, /*Type*/GILLT_s16,
        GIM_CheckType, /*MI*/2, /*Op*/2, /*Type*/GILLT_s16,
        GIM_RecordInsn, /*DefineMI*/3, /*MI*/2, /*OpIdx*/1, // MIs[3]
        GIM_CheckOpcode, /*MI*/3, GIMT_Encode2(TargetOpcode::G_SMAX),
        // MIs[3] src1
        GIM_CheckIsSameOperand, /*MI*/3, /*OpIdx*/1, /*OtherMI*/1, /*OtherOpIdx*/2,
        // MIs[3] src0
        GIM_CheckIsSameOperand, /*MI*/3, /*OpIdx*/2, /*OtherMI*/1, /*OtherOpIdx*/1,
        GIM_CheckIsSafeToFold, /*InsnID*/1,
        GIM_CheckIsSafeToFold, /*InsnID*/2,
        GIM_CheckIsSafeToFold, /*InsnID*/3,
        // (smax:{ *:[i16] } (smin:{ *:[i16] } i16:{ *:[i16] }:$src0, i16:{ *:[i16] }:$src1), (smin:{ *:[i16] } (smax:{ *:[i16] } i16:{ *:[i16] }:$src1, i16:{ *:[i16] }:$src0), i16:{ *:[i16] }:$src2))  =>  (V_MED3_I16_e64:{ *:[i16] } 0:{ *:[i32] }, VSrc_b16:{ *:[i16] }:$src0, 0:{ *:[i32] }, VSrc_b16:{ *:[i16] }:$src1, 0:{ *:[i32] }, VSrc_b16:{ *:[i16] }:$src2, 0:{ *:[i1] })
        GIR_BuildMI, /*InsnID*/0, /*Opcode*/GIMT_Encode2(AMDGPU::V_MED3_I16_e64),
        GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/0, // DstI[vdst]
        GIR_AddImm8, /*InsnID*/0, /*Imm*/0,
        GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/1, /*OpIdx*/1, // src0
        GIR_AddImm8, /*InsnID*/0, /*Imm*/0,
        GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/1, /*OpIdx*/2, // src1
        GIR_AddImm8, /*InsnID*/0, /*Imm*/0,
        GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/2, /*OpIdx*/2, // src2
        GIR_AddImm8, /*InsnID*/0, /*Imm*/0,
        GIR_AddImm8, /*InsnID*/0, /*Imm*/0,
        GIR_ConstrainSelectedInstOperands, /*InsnID*/0,
        GIR_EraseFromParent, /*InsnID*/0,
        // GIR_Coverage, 10480,
        GIR_Done,
      // Label 5304: @391887
      GIM_Try, /*On fail goto*//*Label 5305*/ GIMT_Encode4(391991), // Rule ID 10483 //
        GIM_CheckFeatures, GIMT_Encode2(GIFBS_isGFX9Plus),
        GIM_RecordInsn, /*DefineMI*/1, /*MI*/0, /*OpIdx*/1, // MIs[1]
        GIM_CheckOpcode, /*MI*/1, GIMT_Encode2(TargetOpcode::G_SMIN),
        GIM_CheckType, /*MI*/1, /*Op*/1, /*Type*/GILLT_s16,
        GIM_CheckType, /*MI*/1, /*Op*/2, /*Type*/GILLT_s16,
        GIM_RecordInsn, /*DefineMI*/2, /*MI*/0, /*OpIdx*/2, // MIs[2]
        GIM_CheckOpcode, /*MI*/2, GIMT_Encode2(TargetOpcode::G_SMIN),
        GIM_CheckType, /*MI*/2, /*Op*/1, /*Type*/GILLT_s16,
        GIM_CheckType, /*MI*/2, /*Op*/2, /*Type*/GILLT_s16,
        GIM_RecordInsn, /*DefineMI*/3, /*MI*/2, /*OpIdx*/1, // MIs[3]
        GIM_CheckOpcode, /*MI*/3, GIMT_Encode2(TargetOpcode::G_SMAX),
        // MIs[3] src0
        GIM_CheckIsSameOperand, /*MI*/3, /*OpIdx*/1, /*OtherMI*/1, /*OtherOpIdx*/2,
        // MIs[3] src1
        GIM_CheckIsSameOperand, /*MI*/3, /*OpIdx*/2, /*OtherMI*/1, /*OtherOpIdx*/1,
        GIM_CheckIsSafeToFold, /*InsnID*/1,
        GIM_CheckIsSafeToFold, /*InsnID*/2,
        GIM_CheckIsSafeToFold, /*InsnID*/3,
        // (smax:{ *:[i16] } (smin:{ *:[i16] } i16:{ *:[i16] }:$src1, i16:{ *:[i16] }:$src0), (smin:{ *:[i16] } (smax:{ *:[i16] } i16:{ *:[i16] }:$src0, i16:{ *:[i16] }:$src1), i16:{ *:[i16] }:$src2))  =>  (V_MED3_I16_e64:{ *:[i16] } 0:{ *:[i32] }, VSrc_b16:{ *:[i16] }:$src0, 0:{ *:[i32] }, VSrc_b16:{ *:[i16] }:$src1, 0:{ *:[i32] }, VSrc_b16:{ *:[i16] }:$src2, 0:{ *:[i1] })
        GIR_BuildMI, /*InsnID*/0, /*Opcode*/GIMT_Encode2(AMDGPU::V_MED3_I16_e64),
        GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/0, // DstI[vdst]
        GIR_AddImm8, /*InsnID*/0, /*Imm*/0,
        GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/1, /*OpIdx*/2, // src0
        GIR_AddImm8, /*InsnID*/0, /*Imm*/0,
        GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/1, /*OpIdx*/1, // src1
        GIR_AddImm8, /*InsnID*/0, /*Imm*/0,
        GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/2, /*OpIdx*/2, // src2
        GIR_AddImm8, /*InsnID*/0, /*Imm*/0,
        GIR_AddImm8, /*InsnID*/0, /*Imm*/0,
        GIR_ConstrainSelectedInstOperands, /*InsnID*/0,
        GIR_EraseFromParent, /*InsnID*/0,
        // GIR_Coverage, 10483,
        GIR_Done,
      // Label 5305: @391991
      GIM_Try, /*On fail goto*//*Label 5306*/ GIMT_Encode4(392095), // Rule ID 10484 //
        GIM_CheckFeatures, GIMT_Encode2(GIFBS_isGFX9Plus),
        GIM_RecordInsn, /*DefineMI*/1, /*MI*/0, /*OpIdx*/1, // MIs[1]
        GIM_CheckOpcode, /*MI*/1, GIMT_Encode2(TargetOpcode::G_SMIN),
        GIM_CheckType, /*MI*/1, /*Op*/1, /*Type*/GILLT_s16,
        GIM_CheckType, /*MI*/1, /*Op*/2, /*Type*/GILLT_s16,
        GIM_RecordInsn, /*DefineMI*/2, /*MI*/0, /*OpIdx*/2, // MIs[2]
        GIM_CheckOpcode, /*MI*/2, GIMT_Encode2(TargetOpcode::G_SMIN),
        GIM_CheckType, /*MI*/2, /*Op*/1, /*Type*/GILLT_s16,
        GIM_CheckType, /*MI*/2, /*Op*/2, /*Type*/GILLT_s16,
        GIM_RecordInsn, /*DefineMI*/3, /*MI*/2, /*OpIdx*/1, // MIs[3]
        GIM_CheckOpcode, /*MI*/3, GIMT_Encode2(TargetOpcode::G_SMAX),
        // MIs[3] src1
        GIM_CheckIsSameOperand, /*MI*/3, /*OpIdx*/1, /*OtherMI*/1, /*OtherOpIdx*/1,
        // MIs[3] src0
        GIM_CheckIsSameOperand, /*MI*/3, /*OpIdx*/2, /*OtherMI*/1, /*OtherOpIdx*/2,
        GIM_CheckIsSafeToFold, /*InsnID*/1,
        GIM_CheckIsSafeToFold, /*InsnID*/2,
        GIM_CheckIsSafeToFold, /*InsnID*/3,
        // (smax:{ *:[i16] } (smin:{ *:[i16] } i16:{ *:[i16] }:$src1, i16:{ *:[i16] }:$src0), (smin:{ *:[i16] } (smax:{ *:[i16] } i16:{ *:[i16] }:$src1, i16:{ *:[i16] }:$src0), i16:{ *:[i16] }:$src2))  =>  (V_MED3_I16_e64:{ *:[i16] } 0:{ *:[i32] }, VSrc_b16:{ *:[i16] }:$src0, 0:{ *:[i32] }, VSrc_b16:{ *:[i16] }:$src1, 0:{ *:[i32] }, VSrc_b16:{ *:[i16] }:$src2, 0:{ *:[i1] })
        GIR_BuildMI, /*InsnID*/0, /*Opcode*/GIMT_Encode2(AMDGPU::V_MED3_I16_e64),
        GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/0, // DstI[vdst]
        GIR_AddImm8, /*InsnID*/0, /*Imm*/0,
        GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/1, /*OpIdx*/2, // src0
        GIR_AddImm8, /*InsnID*/0, /*Imm*/0,
        GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/1, /*OpIdx*/1, // src1
        GIR_AddImm8, /*InsnID*/0, /*Imm*/0,
        GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/2, /*OpIdx*/2, // src2
        GIR_AddImm8, /*InsnID*/0, /*Imm*/0,
        GIR_AddImm8, /*InsnID*/0, /*Imm*/0,
        GIR_ConstrainSelectedInstOperands, /*InsnID*/0,
        GIR_EraseFromParent, /*InsnID*/0,
        // GIR_Coverage, 10484,
        GIR_Done,
      // Label 5306: @392095
      GIM_Try, /*On fail goto*//*Label 5307*/ GIMT_Encode4(392199), // Rule ID 10481 //
        GIM_CheckFeatures, GIMT_Encode2(GIFBS_isGFX9Plus),
        GIM_RecordInsn, /*DefineMI*/1, /*MI*/0, /*OpIdx*/1, // MIs[1]
        GIM_CheckOpcode, /*MI*/1, GIMT_Encode2(TargetOpcode::G_SMIN),
        GIM_CheckType, /*MI*/1, /*Op*/1, /*Type*/GILLT_s16,
        GIM_CheckType, /*MI*/1, /*Op*/2, /*Type*/GILLT_s16,
        GIM_RecordInsn, /*DefineMI*/2, /*MI*/0, /*OpIdx*/2, // MIs[2]
        GIM_CheckOpcode, /*MI*/2, GIMT_Encode2(TargetOpcode::G_SMIN),
        GIM_CheckType, /*MI*/2, /*Op*/1, /*Type*/GILLT_s16,
        GIM_CheckType, /*MI*/2, /*Op*/2, /*Type*/GILLT_s16,
        GIM_RecordInsn, /*DefineMI*/3, /*MI*/2, /*OpIdx*/2, // MIs[3]
        GIM_CheckOpcode, /*MI*/3, GIMT_Encode2(TargetOpcode::G_SMAX),
        // MIs[3] src0
        GIM_CheckIsSameOperand, /*MI*/3, /*OpIdx*/1, /*OtherMI*/1, /*OtherOpIdx*/1,
        // MIs[3] src1
        GIM_CheckIsSameOperand, /*MI*/3, /*OpIdx*/2, /*OtherMI*/1, /*OtherOpIdx*/2,
        GIM_CheckIsSafeToFold, /*InsnID*/1,
        GIM_CheckIsSafeToFold, /*InsnID*/2,
        GIM_CheckIsSafeToFold, /*InsnID*/3,
        // (smax:{ *:[i16] } (smin:{ *:[i16] } i16:{ *:[i16] }:$src0, i16:{ *:[i16] }:$src1), (smin:{ *:[i16] } i16:{ *:[i16] }:$src2, (smax:{ *:[i16] } i16:{ *:[i16] }:$src0, i16:{ *:[i16] }:$src1)))  =>  (V_MED3_I16_e64:{ *:[i16] } 0:{ *:[i32] }, VSrc_b16:{ *:[i16] }:$src0, 0:{ *:[i32] }, VSrc_b16:{ *:[i16] }:$src1, 0:{ *:[i32] }, VSrc_b16:{ *:[i16] }:$src2, 0:{ *:[i1] })
        GIR_BuildMI, /*InsnID*/0, /*Opcode*/GIMT_Encode2(AMDGPU::V_MED3_I16_e64),
        GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/0, // DstI[vdst]
        GIR_AddImm8, /*InsnID*/0, /*Imm*/0,
        GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/1, /*OpIdx*/1, // src0
        GIR_AddImm8, /*InsnID*/0, /*Imm*/0,
        GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/1, /*OpIdx*/2, // src1
        GIR_AddImm8, /*InsnID*/0, /*Imm*/0,
        GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/2, /*OpIdx*/1, // src2
        GIR_AddImm8, /*InsnID*/0, /*Imm*/0,
        GIR_AddImm8, /*InsnID*/0, /*Imm*/0,
        GIR_ConstrainSelectedInstOperands, /*InsnID*/0,
        GIR_EraseFromParent, /*InsnID*/0,
        // GIR_Coverage, 10481,
        GIR_Done,
      // Label 5307: @392199
      GIM_Try, /*On fail goto*//*Label 5308*/ GIMT_Encode4(392303), // Rule ID 10482 //
        GIM_CheckFeatures, GIMT_Encode2(GIFBS_isGFX9Plus),
        GIM_RecordInsn, /*DefineMI*/1, /*MI*/0, /*OpIdx*/1, // MIs[1]
        GIM_CheckOpcode, /*MI*/1, GIMT_Encode2(TargetOpcode::G_SMIN),
        GIM_CheckType, /*MI*/1, /*Op*/1, /*Type*/GILLT_s16,
        GIM_CheckType, /*MI*/1, /*Op*/2, /*Type*/GILLT_s16,
        GIM_RecordInsn, /*DefineMI*/2, /*MI*/0, /*OpIdx*/2, // MIs[2]
        GIM_CheckOpcode, /*MI*/2, GIMT_Encode2(TargetOpcode::G_SMIN),
        GIM_CheckType, /*MI*/2, /*Op*/1, /*Type*/GILLT_s16,
        GIM_CheckType, /*MI*/2, /*Op*/2, /*Type*/GILLT_s16,
        GIM_RecordInsn, /*DefineMI*/3, /*MI*/2, /*OpIdx*/2, // MIs[3]
        GIM_CheckOpcode, /*MI*/3, GIMT_Encode2(TargetOpcode::G_SMAX),
        // MIs[3] src1
        GIM_CheckIsSameOperand, /*MI*/3, /*OpIdx*/1, /*OtherMI*/1, /*OtherOpIdx*/2,
        // MIs[3] src0
        GIM_CheckIsSameOperand, /*MI*/3, /*OpIdx*/2, /*OtherMI*/1, /*OtherOpIdx*/1,
        GIM_CheckIsSafeToFold, /*InsnID*/1,
        GIM_CheckIsSafeToFold, /*InsnID*/2,
        GIM_CheckIsSafeToFold, /*InsnID*/3,
        // (smax:{ *:[i16] } (smin:{ *:[i16] } i16:{ *:[i16] }:$src0, i16:{ *:[i16] }:$src1), (smin:{ *:[i16] } i16:{ *:[i16] }:$src2, (smax:{ *:[i16] } i16:{ *:[i16] }:$src1, i16:{ *:[i16] }:$src0)))  =>  (V_MED3_I16_e64:{ *:[i16] } 0:{ *:[i32] }, VSrc_b16:{ *:[i16] }:$src0, 0:{ *:[i32] }, VSrc_b16:{ *:[i16] }:$src1, 0:{ *:[i32] }, VSrc_b16:{ *:[i16] }:$src2, 0:{ *:[i1] })
        GIR_BuildMI, /*InsnID*/0, /*Opcode*/GIMT_Encode2(AMDGPU::V_MED3_I16_e64),
        GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/0, // DstI[vdst]
        GIR_AddImm8, /*InsnID*/0, /*Imm*/0,
        GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/1, /*OpIdx*/1, // src0
        GIR_AddImm8, /*InsnID*/0, /*Imm*/0,
        GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/1, /*OpIdx*/2, // src1
        GIR_AddImm8, /*InsnID*/0, /*Imm*/0,
        GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/2, /*OpIdx*/1, // src2
        GIR_AddImm8, /*InsnID*/0, /*Imm*/0,
        GIR_AddImm8, /*InsnID*/0, /*Imm*/0,
        GIR_ConstrainSelectedInstOperands, /*InsnID*/0,
        GIR_EraseFromParent, /*InsnID*/0,
        // GIR_Coverage, 10482,
        GIR_Done,
      // Label 5308: @392303
      GIM_Try, /*On fail goto*//*Label 5309*/ GIMT_Encode4(392407), // Rule ID 10485 //
        GIM_CheckFeatures, GIMT_Encode2(GIFBS_isGFX9Plus),
        GIM_RecordInsn, /*DefineMI*/1, /*MI*/0, /*OpIdx*/1, // MIs[1]
        GIM_CheckOpcode, /*MI*/1, GIMT_Encode2(TargetOpcode::G_SMIN),
        GIM_CheckType, /*MI*/1, /*Op*/1, /*Type*/GILLT_s16,
        GIM_CheckType, /*MI*/1, /*Op*/2, /*Type*/GILLT_s16,
        GIM_RecordInsn, /*DefineMI*/2, /*MI*/0, /*OpIdx*/2, // MIs[2]
        GIM_CheckOpcode, /*MI*/2, GIMT_Encode2(TargetOpcode::G_SMIN),
        GIM_CheckType, /*MI*/2, /*Op*/1, /*Type*/GILLT_s16,
        GIM_CheckType, /*MI*/2, /*Op*/2, /*Type*/GILLT_s16,
        GIM_RecordInsn, /*DefineMI*/3, /*MI*/2, /*OpIdx*/2, // MIs[3]
        GIM_CheckOpcode, /*MI*/3, GIMT_Encode2(TargetOpcode::G_SMAX),
        // MIs[3] src0
        GIM_CheckIsSameOperand, /*MI*/3, /*OpIdx*/1, /*OtherMI*/1, /*OtherOpIdx*/2,
        // MIs[3] src1
        GIM_CheckIsSameOperand, /*MI*/3, /*OpIdx*/2, /*OtherMI*/1, /*OtherOpIdx*/1,
        GIM_CheckIsSafeToFold, /*InsnID*/1,
        GIM_CheckIsSafeToFold, /*InsnID*/2,
        GIM_CheckIsSafeToFold, /*InsnID*/3,
        // (smax:{ *:[i16] } (smin:{ *:[i16] } i16:{ *:[i16] }:$src1, i16:{ *:[i16] }:$src0), (smin:{ *:[i16] } i16:{ *:[i16] }:$src2, (smax:{ *:[i16] } i16:{ *:[i16] }:$src0, i16:{ *:[i16] }:$src1)))  =>  (V_MED3_I16_e64:{ *:[i16] } 0:{ *:[i32] }, VSrc_b16:{ *:[i16] }:$src0, 0:{ *:[i32] }, VSrc_b16:{ *:[i16] }:$src1, 0:{ *:[i32] }, VSrc_b16:{ *:[i16] }:$src2, 0:{ *:[i1] })
        GIR_BuildMI, /*InsnID*/0, /*Opcode*/GIMT_Encode2(AMDGPU::V_MED3_I16_e64),
        GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/0, // DstI[vdst]
        GIR_AddImm8, /*InsnID*/0, /*Imm*/0,
        GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/1, /*OpIdx*/2, // src0
        GIR_AddImm8, /*InsnID*/0, /*Imm*/0,
        GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/1, /*OpIdx*/1, // src1
        GIR_AddImm8, /*InsnID*/0, /*Imm*/0,
        GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/2, /*OpIdx*/1, // src2
        GIR_AddImm8, /*InsnID*/0, /*Imm*/0,
        GIR_AddImm8, /*InsnID*/0, /*Imm*/0,
        GIR_ConstrainSelectedInstOperands, /*InsnID*/0,
        GIR_EraseFromParent, /*InsnID*/0,
        // GIR_Coverage, 10485,
        GIR_Done,
      // Label 5309: @392407
      GIM_Try, /*On fail goto*//*Label 5310*/ GIMT_Encode4(392511), // Rule ID 10486 //
        GIM_CheckFeatures, GIMT_Encode2(GIFBS_isGFX9Plus),
        GIM_RecordInsn, /*DefineMI*/1, /*MI*/0, /*OpIdx*/1, // MIs[1]
        GIM_CheckOpcode, /*MI*/1, GIMT_Encode2(TargetOpcode::G_SMIN),
        GIM_CheckType, /*MI*/1, /*Op*/1, /*Type*/GILLT_s16,
        GIM_CheckType, /*MI*/1, /*Op*/2, /*Type*/GILLT_s16,
        GIM_RecordInsn, /*DefineMI*/2, /*MI*/0, /*OpIdx*/2, // MIs[2]
        GIM_CheckOpcode, /*MI*/2, GIMT_Encode2(TargetOpcode::G_SMIN),
        GIM_CheckType, /*MI*/2, /*Op*/1, /*Type*/GILLT_s16,
        GIM_CheckType, /*MI*/2, /*Op*/2, /*Type*/GILLT_s16,
        GIM_RecordInsn, /*DefineMI*/3, /*MI*/2, /*OpIdx*/2, // MIs[3]
        GIM_CheckOpcode, /*MI*/3, GIMT_Encode2(TargetOpcode::G_SMAX),
        // MIs[3] src1
        GIM_CheckIsSameOperand, /*MI*/3, /*OpIdx*/1, /*OtherMI*/1, /*OtherOpIdx*/1,
        // MIs[3] src0
        GIM_CheckIsSameOperand, /*MI*/3, /*OpIdx*/2, /*OtherMI*/1, /*OtherOpIdx*/2,
        GIM_CheckIsSafeToFold, /*InsnID*/1,
        GIM_CheckIsSafeToFold, /*InsnID*/2,
        GIM_CheckIsSafeToFold, /*InsnID*/3,
        // (smax:{ *:[i16] } (smin:{ *:[i16] } i16:{ *:[i16] }:$src1, i16:{ *:[i16] }:$src0), (smin:{ *:[i16] } i16:{ *:[i16] }:$src2, (smax:{ *:[i16] } i16:{ *:[i16] }:$src1, i16:{ *:[i16] }:$src0)))  =>  (V_MED3_I16_e64:{ *:[i16] } 0:{ *:[i32] }, VSrc_b16:{ *:[i16] }:$src0, 0:{ *:[i32] }, VSrc_b16:{ *:[i16] }:$src1, 0:{ *:[i32] }, VSrc_b16:{ *:[i16] }:$src2, 0:{ *:[i1] })
        GIR_BuildMI, /*InsnID*/0, /*Opcode*/GIMT_Encode2(AMDGPU::V_MED3_I16_e64),
        GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/0, // DstI[vdst]
        GIR_AddImm8, /*InsnID*/0, /*Imm*/0,
        GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/1, /*OpIdx*/2, // src0
        GIR_AddImm8, /*InsnID*/0, /*Imm*/0,
        GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/1, /*OpIdx*/1, // src1
        GIR_AddImm8, /*InsnID*/0, /*Imm*/0,
        GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/2, /*OpIdx*/1, // src2
        GIR_AddImm8, /*InsnID*/0, /*Imm*/0,
        GIR_AddImm8, /*InsnID*/0, /*Imm*/0,
        GIR_ConstrainSelectedInstOperands, /*InsnID*/0,
        GIR_EraseFromParent, /*InsnID*/0,
        // GIR_Coverage, 10486,
        GIR_Done,
      // Label 5310: @392511
      GIM_Try, /*On fail goto*//*Label 5311*/ GIMT_Encode4(392531), // Rule ID 827 //
        GIM_CheckFeatures, GIMT_Encode2(GIFBS_Has16BitInsts_NotHasTrue16BitInsts),
        // (smax:{ *:[i16] } i16:{ *:[i16] }:$src0, i16:{ *:[i16] }:$src1)  =>  (V_MAX_I16_e64:{ *:[i16] } i16:{ *:[i16] }:$src0, i16:{ *:[i16] }:$src1)
        GIR_MutateOpcode, /*InsnID*/0, /*RecycleInsnID*/0, /*Opcode*/GIMT_Encode2(AMDGPU::V_MAX_I16_e64),
        GIR_AddImplicitUse, /*InsnID*/0, GIMT_Encode2(AMDGPU::EXEC),
        GIR_ConstrainSelectedInstOperands, /*InsnID*/0,
        // GIR_Coverage, 827,
        GIR_Done,
      // Label 5311: @392531
      GIM_Try, /*On fail goto*//*Label 5312*/ GIMT_Encode4(392551), // Rule ID 828 //
        GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasTrue16BitInsts),
        // (smax:{ *:[i16] } i16:{ *:[i16] }:$src0, i16:{ *:[i16] }:$src1)  =>  (V_MAX_I16_t16_e64:{ *:[i16] } i16:{ *:[i16] }:$src0, i16:{ *:[i16] }:$src1)
        GIR_MutateOpcode, /*InsnID*/0, /*RecycleInsnID*/0, /*Opcode*/GIMT_Encode2(AMDGPU::V_MAX_I16_t16_e64),
        GIR_AddImplicitUse, /*InsnID*/0, GIMT_Encode2(AMDGPU::EXEC),
        GIR_ConstrainSelectedInstOperands, /*InsnID*/0,
        // GIR_Coverage, 828,
        GIR_Done,
      // Label 5312: @392551
      GIM_Reject,
    // Label 5294: @392552
    GIM_Reject,
    // Label 5291: @392553
    GIM_Try, /*On fail goto*//*Label 5313*/ GIMT_Encode4(394399),
      GIM_CheckType, /*MI*/0, /*Op*/1, /*Type*/GILLT_s32,
      GIM_Try, /*On fail goto*//*Label 5314*/ GIMT_Encode4(392657), // Rule ID 9962 //
        GIM_CheckType, /*MI*/0, /*Op*/2, /*Type*/GILLT_s32,
        GIM_CheckRegBankForClass, /*MI*/0, /*Op*/0, /*RC*/GIMT_Encode2(AMDGPU::VGPR_32RegClassID),
        GIM_RecordInsn, /*DefineMI*/1, /*MI*/0, /*OpIdx*/1, // MIs[1]
        GIM_CheckOpcode, /*MI*/1, GIMT_Encode2(TargetOpcode::G_SMIN),
        GIM_CheckType, /*MI*/1, /*Op*/1, /*Type*/GILLT_s32,
        GIM_CheckType, /*MI*/1, /*Op*/2, /*Type*/GILLT_s32,
        GIM_RecordInsn, /*DefineMI*/2, /*MI*/1, /*OpIdx*/1, // MIs[2]
        GIM_CheckOpcode, /*MI*/2, GIMT_Encode2(TargetOpcode::G_SMAX),
        GIM_CheckType, /*MI*/2, /*Op*/1, /*Type*/GILLT_s32,
        GIM_CheckType, /*MI*/2, /*Op*/2, /*Type*/GILLT_s32,
        GIM_RecordInsn, /*DefineMI*/3, /*MI*/0, /*OpIdx*/2, // MIs[3]
        GIM_CheckOpcode, /*MI*/3, GIMT_Encode2(TargetOpcode::G_SMIN),
        // MIs[3] src0
        GIM_CheckIsSameOperand, /*MI*/3, /*OpIdx*/1, /*OtherMI*/2, /*OtherOpIdx*/1,
        // MIs[3] src1
        GIM_CheckIsSameOperand, /*MI*/3, /*OpIdx*/2, /*OtherMI*/2, /*OtherOpIdx*/2,
        GIM_CheckIsSafeToFold, /*InsnID*/1,
        GIM_CheckIsSafeToFold, /*InsnID*/2,
        GIM_CheckIsSafeToFold, /*InsnID*/3,
        // (smax:{ *:[i32] } (smin:{ *:[i32] } (smax:{ *:[i32] } i32:{ *:[i32] }:$src0, i32:{ *:[i32] }:$src1), i32:{ *:[i32] }:$src2), (smin:{ *:[i32] } i32:{ *:[i32] }:$src0, i32:{ *:[i32] }:$src1))  =>  (V_MED3_I32_e64:{ *:[i32] } VSrc_b32:{ *:[i32] }:$src0, VSrc_b32:{ *:[i32] }:$src1, VSrc_b32:{ *:[i32] }:$src2)
        GIR_BuildMI, /*InsnID*/0, /*Opcode*/GIMT_Encode2(AMDGPU::V_MED3_I32_e64),
        GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/0, // DstI[vdst]
        GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/2, /*OpIdx*/1, // src0
        GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/2, /*OpIdx*/2, // src1
        GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/1, /*OpIdx*/2, // src2
        GIR_ConstrainSelectedInstOperands, /*InsnID*/0,
        GIR_EraseFromParent, /*InsnID*/0,
        // GIR_Coverage, 9962,
        GIR_Done,
      // Label 5314: @392657
      GIM_Try, /*On fail goto*//*Label 5315*/ GIMT_Encode4(392752), // Rule ID 9963 //
        GIM_CheckType, /*MI*/0, /*Op*/2, /*Type*/GILLT_s32,
        GIM_CheckRegBankForClass, /*MI*/0, /*Op*/0, /*RC*/GIMT_Encode2(AMDGPU::VGPR_32RegClassID),
        GIM_RecordInsn, /*DefineMI*/1, /*MI*/0, /*OpIdx*/1, // MIs[1]
        GIM_CheckOpcode, /*MI*/1, GIMT_Encode2(TargetOpcode::G_SMIN),
        GIM_CheckType, /*MI*/1, /*Op*/1, /*Type*/GILLT_s32,
        GIM_CheckType, /*MI*/1, /*Op*/2, /*Type*/GILLT_s32,
        GIM_RecordInsn, /*DefineMI*/2, /*MI*/1, /*OpIdx*/1, // MIs[2]
        GIM_CheckOpcode, /*MI*/2, GIMT_Encode2(TargetOpcode::G_SMAX),
        GIM_CheckType, /*MI*/2, /*Op*/1, /*Type*/GILLT_s32,
        GIM_CheckType, /*MI*/2, /*Op*/2, /*Type*/GILLT_s32,
        GIM_RecordInsn, /*DefineMI*/3, /*MI*/0, /*OpIdx*/2, // MIs[3]
        GIM_CheckOpcode, /*MI*/3, GIMT_Encode2(TargetOpcode::G_SMIN),
        // MIs[3] src1
        GIM_CheckIsSameOperand, /*MI*/3, /*OpIdx*/1, /*OtherMI*/2, /*OtherOpIdx*/2,
        // MIs[3] src0
        GIM_CheckIsSameOperand, /*MI*/3, /*OpIdx*/2, /*OtherMI*/2, /*OtherOpIdx*/1,
        GIM_CheckIsSafeToFold, /*InsnID*/1,
        GIM_CheckIsSafeToFold, /*InsnID*/2,
        GIM_CheckIsSafeToFold, /*InsnID*/3,
        // (smax:{ *:[i32] } (smin:{ *:[i32] } (smax:{ *:[i32] } i32:{ *:[i32] }:$src0, i32:{ *:[i32] }:$src1), i32:{ *:[i32] }:$src2), (smin:{ *:[i32] } i32:{ *:[i32] }:$src1, i32:{ *:[i32] }:$src0))  =>  (V_MED3_I32_e64:{ *:[i32] } VSrc_b32:{ *:[i32] }:$src0, VSrc_b32:{ *:[i32] }:$src1, VSrc_b32:{ *:[i32] }:$src2)
        GIR_BuildMI, /*InsnID*/0, /*Opcode*/GIMT_Encode2(AMDGPU::V_MED3_I32_e64),
        GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/0, // DstI[vdst]
        GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/2, /*OpIdx*/1, // src0
        GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/2, /*OpIdx*/2, // src1
        GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/1, /*OpIdx*/2, // src2
        GIR_ConstrainSelectedInstOperands, /*InsnID*/0,
        GIR_EraseFromParent, /*InsnID*/0,
        // GIR_Coverage, 9963,
        GIR_Done,
      // Label 5315: @392752
      GIM_Try, /*On fail goto*//*Label 5316*/ GIMT_Encode4(392847), // Rule ID 9964 //
        GIM_CheckType, /*MI*/0, /*Op*/2, /*Type*/GILLT_s32,
        GIM_CheckRegBankForClass, /*MI*/0, /*Op*/0, /*RC*/GIMT_Encode2(AMDGPU::VGPR_32RegClassID),
        GIM_RecordInsn, /*DefineMI*/1, /*MI*/0, /*OpIdx*/1, // MIs[1]
        GIM_CheckOpcode, /*MI*/1, GIMT_Encode2(TargetOpcode::G_SMIN),
        GIM_CheckType, /*MI*/1, /*Op*/1, /*Type*/GILLT_s32,
        GIM_CheckType, /*MI*/1, /*Op*/2, /*Type*/GILLT_s32,
        GIM_RecordInsn, /*DefineMI*/2, /*MI*/1, /*OpIdx*/1, // MIs[2]
        GIM_CheckOpcode, /*MI*/2, GIMT_Encode2(TargetOpcode::G_SMAX),
        GIM_CheckType, /*MI*/2, /*Op*/1, /*Type*/GILLT_s32,
        GIM_CheckType, /*MI*/2, /*Op*/2, /*Type*/GILLT_s32,
        GIM_RecordInsn, /*DefineMI*/3, /*MI*/0, /*OpIdx*/2, // MIs[3]
        GIM_CheckOpcode, /*MI*/3, GIMT_Encode2(TargetOpcode::G_SMIN),
        // MIs[3] src0
        GIM_CheckIsSameOperand, /*MI*/3, /*OpIdx*/1, /*OtherMI*/2, /*OtherOpIdx*/2,
        // MIs[3] src1
        GIM_CheckIsSameOperand, /*MI*/3, /*OpIdx*/2, /*OtherMI*/2, /*OtherOpIdx*/1,
        GIM_CheckIsSafeToFold, /*InsnID*/1,
        GIM_CheckIsSafeToFold, /*InsnID*/2,
        GIM_CheckIsSafeToFold, /*InsnID*/3,
        // (smax:{ *:[i32] } (smin:{ *:[i32] } (smax:{ *:[i32] } i32:{ *:[i32] }:$src1, i32:{ *:[i32] }:$src0), i32:{ *:[i32] }:$src2), (smin:{ *:[i32] } i32:{ *:[i32] }:$src0, i32:{ *:[i32] }:$src1))  =>  (V_MED3_I32_e64:{ *:[i32] } VSrc_b32:{ *:[i32] }:$src0, VSrc_b32:{ *:[i32] }:$src1, VSrc_b32:{ *:[i32] }:$src2)
        GIR_BuildMI, /*InsnID*/0, /*Opcode*/GIMT_Encode2(AMDGPU::V_MED3_I32_e64),
        GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/0, // DstI[vdst]
        GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/2, /*OpIdx*/2, // src0
        GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/2, /*OpIdx*/1, // src1
        GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/1, /*OpIdx*/2, // src2
        GIR_ConstrainSelectedInstOperands, /*InsnID*/0,
        GIR_EraseFromParent, /*InsnID*/0,
        // GIR_Coverage, 9964,
        GIR_Done,
      // Label 5316: @392847
      GIM_Try, /*On fail goto*//*Label 5317*/ GIMT_Encode4(392942), // Rule ID 9965 //
        GIM_CheckType, /*MI*/0, /*Op*/2, /*Type*/GILLT_s32,
        GIM_CheckRegBankForClass, /*MI*/0, /*Op*/0, /*RC*/GIMT_Encode2(AMDGPU::VGPR_32RegClassID),
        GIM_RecordInsn, /*DefineMI*/1, /*MI*/0, /*OpIdx*/1, // MIs[1]
        GIM_CheckOpcode, /*MI*/1, GIMT_Encode2(TargetOpcode::G_SMIN),
        GIM_CheckType, /*MI*/1, /*Op*/1, /*Type*/GILLT_s32,
        GIM_CheckType, /*MI*/1, /*Op*/2, /*Type*/GILLT_s32,
        GIM_RecordInsn, /*DefineMI*/2, /*MI*/1, /*OpIdx*/1, // MIs[2]
        GIM_CheckOpcode, /*MI*/2, GIMT_Encode2(TargetOpcode::G_SMAX),
        GIM_CheckType, /*MI*/2, /*Op*/1, /*Type*/GILLT_s32,
        GIM_CheckType, /*MI*/2, /*Op*/2, /*Type*/GILLT_s32,
        GIM_RecordInsn, /*DefineMI*/3, /*MI*/0, /*OpIdx*/2, // MIs[3]
        GIM_CheckOpcode, /*MI*/3, GIMT_Encode2(TargetOpcode::G_SMIN),
        // MIs[3] src1
        GIM_CheckIsSameOperand, /*MI*/3, /*OpIdx*/1, /*OtherMI*/2, /*OtherOpIdx*/1,
        // MIs[3] src0
        GIM_CheckIsSameOperand, /*MI*/3, /*OpIdx*/2, /*OtherMI*/2, /*OtherOpIdx*/2,
        GIM_CheckIsSafeToFold, /*InsnID*/1,
        GIM_CheckIsSafeToFold, /*InsnID*/2,
        GIM_CheckIsSafeToFold, /*InsnID*/3,
        // (smax:{ *:[i32] } (smin:{ *:[i32] } (smax:{ *:[i32] } i32:{ *:[i32] }:$src1, i32:{ *:[i32] }:$src0), i32:{ *:[i32] }:$src2), (smin:{ *:[i32] } i32:{ *:[i32] }:$src1, i32:{ *:[i32] }:$src0))  =>  (V_MED3_I32_e64:{ *:[i32] } VSrc_b32:{ *:[i32] }:$src0, VSrc_b32:{ *:[i32] }:$src1, VSrc_b32:{ *:[i32] }:$src2)
        GIR_BuildMI, /*InsnID*/0, /*Opcode*/GIMT_Encode2(AMDGPU::V_MED3_I32_e64),
        GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/0, // DstI[vdst]
        GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/2, /*OpIdx*/2, // src0
        GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/2, /*OpIdx*/1, // src1
        GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/1, /*OpIdx*/2, // src2
        GIR_ConstrainSelectedInstOperands, /*InsnID*/0,
        GIR_EraseFromParent, /*InsnID*/0,
        // GIR_Coverage, 9965,
        GIR_Done,
      // Label 5317: @392942
      GIM_Try, /*On fail goto*//*Label 5318*/ GIMT_Encode4(393037), // Rule ID 9966 //
        GIM_CheckType, /*MI*/0, /*Op*/2, /*Type*/GILLT_s32,
        GIM_CheckRegBankForClass, /*MI*/0, /*Op*/0, /*RC*/GIMT_Encode2(AMDGPU::VGPR_32RegClassID),
        GIM_RecordInsn, /*DefineMI*/1, /*MI*/0, /*OpIdx*/1, // MIs[1]
        GIM_CheckOpcode, /*MI*/1, GIMT_Encode2(TargetOpcode::G_SMIN),
        GIM_CheckType, /*MI*/1, /*Op*/1, /*Type*/GILLT_s32,
        GIM_CheckType, /*MI*/1, /*Op*/2, /*Type*/GILLT_s32,
        GIM_RecordInsn, /*DefineMI*/2, /*MI*/1, /*OpIdx*/2, // MIs[2]
        GIM_CheckOpcode, /*MI*/2, GIMT_Encode2(TargetOpcode::G_SMAX),
        GIM_CheckType, /*MI*/2, /*Op*/1, /*Type*/GILLT_s32,
        GIM_CheckType, /*MI*/2, /*Op*/2, /*Type*/GILLT_s32,
        GIM_RecordInsn, /*DefineMI*/3, /*MI*/0, /*OpIdx*/2, // MIs[3]
        GIM_CheckOpcode, /*MI*/3, GIMT_Encode2(TargetOpcode::G_SMIN),
        // MIs[3] src0
        GIM_CheckIsSameOperand, /*MI*/3, /*OpIdx*/1, /*OtherMI*/2, /*OtherOpIdx*/1,
        // MIs[3] src1
        GIM_CheckIsSameOperand, /*MI*/3, /*OpIdx*/2, /*OtherMI*/2, /*OtherOpIdx*/2,
        GIM_CheckIsSafeToFold, /*InsnID*/1,
        GIM_CheckIsSafeToFold, /*InsnID*/2,
        GIM_CheckIsSafeToFold, /*InsnID*/3,
        // (smax:{ *:[i32] } (smin:{ *:[i32] } i32:{ *:[i32] }:$src2, (smax:{ *:[i32] } i32:{ *:[i32] }:$src0, i32:{ *:[i32] }:$src1)), (smin:{ *:[i32] } i32:{ *:[i32] }:$src0, i32:{ *:[i32] }:$src1))  =>  (V_MED3_I32_e64:{ *:[i32] } VSrc_b32:{ *:[i32] }:$src0, VSrc_b32:{ *:[i32] }:$src1, VSrc_b32:{ *:[i32] }:$src2)
        GIR_BuildMI, /*InsnID*/0, /*Opcode*/GIMT_Encode2(AMDGPU::V_MED3_I32_e64),
        GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/0, // DstI[vdst]
        GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/2, /*OpIdx*/1, // src0
        GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/2, /*OpIdx*/2, // src1
        GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/1, /*OpIdx*/1, // src2
        GIR_ConstrainSelectedInstOperands, /*InsnID*/0,
        GIR_EraseFromParent, /*InsnID*/0,
        // GIR_Coverage, 9966,
        GIR_Done,
      // Label 5318: @393037
      GIM_Try, /*On fail goto*//*Label 5319*/ GIMT_Encode4(393132), // Rule ID 9967 //
        GIM_CheckType, /*MI*/0, /*Op*/2, /*Type*/GILLT_s32,
        GIM_CheckRegBankForClass, /*MI*/0, /*Op*/0, /*RC*/GIMT_Encode2(AMDGPU::VGPR_32RegClassID),
        GIM_RecordInsn, /*DefineMI*/1, /*MI*/0, /*OpIdx*/1, // MIs[1]
        GIM_CheckOpcode, /*MI*/1, GIMT_Encode2(TargetOpcode::G_SMIN),
        GIM_CheckType, /*MI*/1, /*Op*/1, /*Type*/GILLT_s32,
        GIM_CheckType, /*MI*/1, /*Op*/2, /*Type*/GILLT_s32,
        GIM_RecordInsn, /*DefineMI*/2, /*MI*/1, /*OpIdx*/2, // MIs[2]
        GIM_CheckOpcode, /*MI*/2, GIMT_Encode2(TargetOpcode::G_SMAX),
        GIM_CheckType, /*MI*/2, /*Op*/1, /*Type*/GILLT_s32,
        GIM_CheckType, /*MI*/2, /*Op*/2, /*Type*/GILLT_s32,
        GIM_RecordInsn, /*DefineMI*/3, /*MI*/0, /*OpIdx*/2, // MIs[3]
        GIM_CheckOpcode, /*MI*/3, GIMT_Encode2(TargetOpcode::G_SMIN),
        // MIs[3] src1
        GIM_CheckIsSameOperand, /*MI*/3, /*OpIdx*/1, /*OtherMI*/2, /*OtherOpIdx*/2,
        // MIs[3] src0
        GIM_CheckIsSameOperand, /*MI*/3, /*OpIdx*/2, /*OtherMI*/2, /*OtherOpIdx*/1,
        GIM_CheckIsSafeToFold, /*InsnID*/1,
        GIM_CheckIsSafeToFold, /*InsnID*/2,
        GIM_CheckIsSafeToFold, /*InsnID*/3,
        // (smax:{ *:[i32] } (smin:{ *:[i32] } i32:{ *:[i32] }:$src2, (smax:{ *:[i32] } i32:{ *:[i32] }:$src0, i32:{ *:[i32] }:$src1)), (smin:{ *:[i32] } i32:{ *:[i32] }:$src1, i32:{ *:[i32] }:$src0))  =>  (V_MED3_I32_e64:{ *:[i32] } VSrc_b32:{ *:[i32] }:$src0, VSrc_b32:{ *:[i32] }:$src1, VSrc_b32:{ *:[i32] }:$src2)
        GIR_BuildMI, /*InsnID*/0, /*Opcode*/GIMT_Encode2(AMDGPU::V_MED3_I32_e64),
        GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/0, // DstI[vdst]
        GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/2, /*OpIdx*/1, // src0
        GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/2, /*OpIdx*/2, // src1
        GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/1, /*OpIdx*/1, // src2
        GIR_ConstrainSelectedInstOperands, /*InsnID*/0,
        GIR_EraseFromParent, /*InsnID*/0,
        // GIR_Coverage, 9967,
        GIR_Done,
      // Label 5319: @393132
      GIM_Try, /*On fail goto*//*Label 5320*/ GIMT_Encode4(393227), // Rule ID 9968 //
        GIM_CheckType, /*MI*/0, /*Op*/2, /*Type*/GILLT_s32,
        GIM_CheckRegBankForClass, /*MI*/0, /*Op*/0, /*RC*/GIMT_Encode2(AMDGPU::VGPR_32RegClassID),
        GIM_RecordInsn, /*DefineMI*/1, /*MI*/0, /*OpIdx*/1, // MIs[1]
        GIM_CheckOpcode, /*MI*/1, GIMT_Encode2(TargetOpcode::G_SMIN),
        GIM_CheckType, /*MI*/1, /*Op*/1, /*Type*/GILLT_s32,
        GIM_CheckType, /*MI*/1, /*Op*/2, /*Type*/GILLT_s32,
        GIM_RecordInsn, /*DefineMI*/2, /*MI*/1, /*OpIdx*/2, // MIs[2]
        GIM_CheckOpcode, /*MI*/2, GIMT_Encode2(TargetOpcode::G_SMAX),
        GIM_CheckType, /*MI*/2, /*Op*/1, /*Type*/GILLT_s32,
        GIM_CheckType, /*MI*/2, /*Op*/2, /*Type*/GILLT_s32,
        GIM_RecordInsn, /*DefineMI*/3, /*MI*/0, /*OpIdx*/2, // MIs[3]
        GIM_CheckOpcode, /*MI*/3, GIMT_Encode2(TargetOpcode::G_SMIN),
        // MIs[3] src0
        GIM_CheckIsSameOperand, /*MI*/3, /*OpIdx*/1, /*OtherMI*/2, /*OtherOpIdx*/2,
        // MIs[3] src1
        GIM_CheckIsSameOperand, /*MI*/3, /*OpIdx*/2, /*OtherMI*/2, /*OtherOpIdx*/1,
        GIM_CheckIsSafeToFold, /*InsnID*/1,
        GIM_CheckIsSafeToFold, /*InsnID*/2,
        GIM_CheckIsSafeToFold, /*InsnID*/3,
        // (smax:{ *:[i32] } (smin:{ *:[i32] } i32:{ *:[i32] }:$src2, (smax:{ *:[i32] } i32:{ *:[i32] }:$src1, i32:{ *:[i32] }:$src0)), (smin:{ *:[i32] } i32:{ *:[i32] }:$src0, i32:{ *:[i32] }:$src1))  =>  (V_MED3_I32_e64:{ *:[i32] } VSrc_b32:{ *:[i32] }:$src0, VSrc_b32:{ *:[i32] }:$src1, VSrc_b32:{ *:[i32] }:$src2)
        GIR_BuildMI, /*InsnID*/0, /*Opcode*/GIMT_Encode2(AMDGPU::V_MED3_I32_e64),
        GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/0, // DstI[vdst]
        GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/2, /*OpIdx*/2, // src0
        GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/2, /*OpIdx*/1, // src1
        GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/1, /*OpIdx*/1, // src2
        GIR_ConstrainSelectedInstOperands, /*InsnID*/0,
        GIR_EraseFromParent, /*InsnID*/0,
        // GIR_Coverage, 9968,
        GIR_Done,
      // Label 5320: @393227
      GIM_Try, /*On fail goto*//*Label 5321*/ GIMT_Encode4(393322), // Rule ID 9969 //
        GIM_CheckType, /*MI*/0, /*Op*/2, /*Type*/GILLT_s32,
        GIM_CheckRegBankForClass, /*MI*/0, /*Op*/0, /*RC*/GIMT_Encode2(AMDGPU::VGPR_32RegClassID),
        GIM_RecordInsn, /*DefineMI*/1, /*MI*/0, /*OpIdx*/1, // MIs[1]
        GIM_CheckOpcode, /*MI*/1, GIMT_Encode2(TargetOpcode::G_SMIN),
        GIM_CheckType, /*MI*/1, /*Op*/1, /*Type*/GILLT_s32,
        GIM_CheckType, /*MI*/1, /*Op*/2, /*Type*/GILLT_s32,
        GIM_RecordInsn, /*DefineMI*/2, /*MI*/1, /*OpIdx*/2, // MIs[2]
        GIM_CheckOpcode, /*MI*/2, GIMT_Encode2(TargetOpcode::G_SMAX),
        GIM_CheckType, /*MI*/2, /*Op*/1, /*Type*/GILLT_s32,
        GIM_CheckType, /*MI*/2, /*Op*/2, /*Type*/GILLT_s32,
        GIM_RecordInsn, /*DefineMI*/3, /*MI*/0, /*OpIdx*/2, // MIs[3]
        GIM_CheckOpcode, /*MI*/3, GIMT_Encode2(TargetOpcode::G_SMIN),
        // MIs[3] src1
        GIM_CheckIsSameOperand, /*MI*/3, /*OpIdx*/1, /*OtherMI*/2, /*OtherOpIdx*/1,
        // MIs[3] src0
        GIM_CheckIsSameOperand, /*MI*/3, /*OpIdx*/2, /*OtherMI*/2, /*OtherOpIdx*/2,
        GIM_CheckIsSafeToFold, /*InsnID*/1,
        GIM_CheckIsSafeToFold, /*InsnID*/2,
        GIM_CheckIsSafeToFold, /*InsnID*/3,
        // (smax:{ *:[i32] } (smin:{ *:[i32] } i32:{ *:[i32] }:$src2, (smax:{ *:[i32] } i32:{ *:[i32] }:$src1, i32:{ *:[i32] }:$src0)), (smin:{ *:[i32] } i32:{ *:[i32] }:$src1, i32:{ *:[i32] }:$src0))  =>  (V_MED3_I32_e64:{ *:[i32] } VSrc_b32:{ *:[i32] }:$src0, VSrc_b32:{ *:[i32] }:$src1, VSrc_b32:{ *:[i32] }:$src2)
        GIR_BuildMI, /*InsnID*/0, /*Opcode*/GIMT_Encode2(AMDGPU::V_MED3_I32_e64),
        GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/0, // DstI[vdst]
        GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/2, /*OpIdx*/2, // src0
        GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/2, /*OpIdx*/1, // src1
        GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/1, /*OpIdx*/1, // src2
        GIR_ConstrainSelectedInstOperands, /*InsnID*/0,
        GIR_EraseFromParent, /*InsnID*/0,
        // GIR_Coverage, 9969,
        GIR_Done,
      // Label 5321: @393322
      GIM_Try, /*On fail goto*//*Label 5322*/ GIMT_Encode4(393417), // Rule ID 6479 //
        GIM_CheckType, /*MI*/0, /*Op*/2, /*Type*/GILLT_s32,
        GIM_CheckRegBankForClass, /*MI*/0, /*Op*/0, /*RC*/GIMT_Encode2(AMDGPU::VGPR_32RegClassID),
        GIM_RecordInsn, /*DefineMI*/1, /*MI*/0, /*OpIdx*/1, // MIs[1]
        GIM_CheckOpcode, /*MI*/1, GIMT_Encode2(TargetOpcode::G_SMIN),
        GIM_CheckType, /*MI*/1, /*Op*/1, /*Type*/GILLT_s32,
        GIM_CheckType, /*MI*/1, /*Op*/2, /*Type*/GILLT_s32,
        GIM_RecordInsn, /*DefineMI*/2, /*MI*/0, /*OpIdx*/2, // MIs[2]
        GIM_CheckOpcode, /*MI*/2, GIMT_Encode2(TargetOpcode::G_SMIN),
        GIM_CheckType, /*MI*/2, /*Op*/1, /*Type*/GILLT_s32,
        GIM_CheckType, /*MI*/2, /*Op*/2, /*Type*/GILLT_s32,
        GIM_RecordInsn, /*DefineMI*/3, /*MI*/2, /*OpIdx*/1, // MIs[3]
        GIM_CheckOpcode, /*MI*/3, GIMT_Encode2(TargetOpcode::G_SMAX),
        // MIs[3] src0
        GIM_CheckIsSameOperand, /*MI*/3, /*OpIdx*/1, /*OtherMI*/1, /*OtherOpIdx*/1,
        // MIs[3] src1
        GIM_CheckIsSameOperand, /*MI*/3, /*OpIdx*/2, /*OtherMI*/1, /*OtherOpIdx*/2,
        GIM_CheckIsSafeToFold, /*InsnID*/1,
        GIM_CheckIsSafeToFold, /*InsnID*/2,
        GIM_CheckIsSafeToFold, /*InsnID*/3,
        // (smax:{ *:[i32] } (smin:{ *:[i32] } i32:{ *:[i32] }:$src0, i32:{ *:[i32] }:$src1), (smin:{ *:[i32] } (smax:{ *:[i32] } i32:{ *:[i32] }:$src0, i32:{ *:[i32] }:$src1), i32:{ *:[i32] }:$src2))  =>  (V_MED3_I32_e64:{ *:[i32] } VSrc_b32:{ *:[i32] }:$src0, VSrc_b32:{ *:[i32] }:$src1, VSrc_b32:{ *:[i32] }:$src2)
        GIR_BuildMI, /*InsnID*/0, /*Opcode*/GIMT_Encode2(AMDGPU::V_MED3_I32_e64),
        GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/0, // DstI[vdst]
        GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/1, /*OpIdx*/1, // src0
        GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/1, /*OpIdx*/2, // src1
        GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/2, /*OpIdx*/2, // src2
        GIR_ConstrainSelectedInstOperands, /*InsnID*/0,
        GIR_EraseFromParent, /*InsnID*/0,
        // GIR_Coverage, 6479,
        GIR_Done,
      // Label 5322: @393417
      GIM_Try, /*On fail goto*//*Label 5323*/ GIMT_Encode4(393512), // Rule ID 9955 //
        GIM_CheckType, /*MI*/0, /*Op*/2, /*Type*/GILLT_s32,
        GIM_CheckRegBankForClass, /*MI*/0, /*Op*/0, /*RC*/GIMT_Encode2(AMDGPU::VGPR_32RegClassID),
        GIM_RecordInsn, /*DefineMI*/1, /*MI*/0, /*OpIdx*/1, // MIs[1]
        GIM_CheckOpcode, /*MI*/1, GIMT_Encode2(TargetOpcode::G_SMIN),
        GIM_CheckType, /*MI*/1, /*Op*/1, /*Type*/GILLT_s32,
        GIM_CheckType, /*MI*/1, /*Op*/2, /*Type*/GILLT_s32,
        GIM_RecordInsn, /*DefineMI*/2, /*MI*/0, /*OpIdx*/2, // MIs[2]
        GIM_CheckOpcode, /*MI*/2, GIMT_Encode2(TargetOpcode::G_SMIN),
        GIM_CheckType, /*MI*/2, /*Op*/1, /*Type*/GILLT_s32,
        GIM_CheckType, /*MI*/2, /*Op*/2, /*Type*/GILLT_s32,
        GIM_RecordInsn, /*DefineMI*/3, /*MI*/2, /*OpIdx*/1, // MIs[3]
        GIM_CheckOpcode, /*MI*/3, GIMT_Encode2(TargetOpcode::G_SMAX),
        // MIs[3] src1
        GIM_CheckIsSameOperand, /*MI*/3, /*OpIdx*/1, /*OtherMI*/1, /*OtherOpIdx*/2,
        // MIs[3] src0
        GIM_CheckIsSameOperand, /*MI*/3, /*OpIdx*/2, /*OtherMI*/1, /*OtherOpIdx*/1,
        GIM_CheckIsSafeToFold, /*InsnID*/1,
        GIM_CheckIsSafeToFold, /*InsnID*/2,
        GIM_CheckIsSafeToFold, /*InsnID*/3,
        // (smax:{ *:[i32] } (smin:{ *:[i32] } i32:{ *:[i32] }:$src0, i32:{ *:[i32] }:$src1), (smin:{ *:[i32] } (smax:{ *:[i32] } i32:{ *:[i32] }:$src1, i32:{ *:[i32] }:$src0), i32:{ *:[i32] }:$src2))  =>  (V_MED3_I32_e64:{ *:[i32] } VSrc_b32:{ *:[i32] }:$src0, VSrc_b32:{ *:[i32] }:$src1, VSrc_b32:{ *:[i32] }:$src2)
        GIR_BuildMI, /*InsnID*/0, /*Opcode*/GIMT_Encode2(AMDGPU::V_MED3_I32_e64),
        GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/0, // DstI[vdst]
        GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/1, /*OpIdx*/1, // src0
        GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/1, /*OpIdx*/2, // src1
        GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/2, /*OpIdx*/2, // src2
        GIR_ConstrainSelectedInstOperands, /*InsnID*/0,
        GIR_EraseFromParent, /*InsnID*/0,
        // GIR_Coverage, 9955,
        GIR_Done,
      // Label 5323: @393512
      GIM_Try, /*On fail goto*//*Label 5324*/ GIMT_Encode4(393607), // Rule ID 9958 //
        GIM_CheckType, /*MI*/0, /*Op*/2, /*Type*/GILLT_s32,
        GIM_CheckRegBankForClass, /*MI*/0, /*Op*/0, /*RC*/GIMT_Encode2(AMDGPU::VGPR_32RegClassID),
        GIM_RecordInsn, /*DefineMI*/1, /*MI*/0, /*OpIdx*/1, // MIs[1]
        GIM_CheckOpcode, /*MI*/1, GIMT_Encode2(TargetOpcode::G_SMIN),
        GIM_CheckType, /*MI*/1, /*Op*/1, /*Type*/GILLT_s32,
        GIM_CheckType, /*MI*/1, /*Op*/2, /*Type*/GILLT_s32,
        GIM_RecordInsn, /*DefineMI*/2, /*MI*/0, /*OpIdx*/2, // MIs[2]
        GIM_CheckOpcode, /*MI*/2, GIMT_Encode2(TargetOpcode::G_SMIN),
        GIM_CheckType, /*MI*/2, /*Op*/1, /*Type*/GILLT_s32,
        GIM_CheckType, /*MI*/2, /*Op*/2, /*Type*/GILLT_s32,
        GIM_RecordInsn, /*DefineMI*/3, /*MI*/2, /*OpIdx*/1, // MIs[3]
        GIM_CheckOpcode, /*MI*/3, GIMT_Encode2(TargetOpcode::G_SMAX),
        // MIs[3] src0
        GIM_CheckIsSameOperand, /*MI*/3, /*OpIdx*/1, /*OtherMI*/1, /*OtherOpIdx*/2,
        // MIs[3] src1
        GIM_CheckIsSameOperand, /*MI*/3, /*OpIdx*/2, /*OtherMI*/1, /*OtherOpIdx*/1,
        GIM_CheckIsSafeToFold, /*InsnID*/1,
        GIM_CheckIsSafeToFold, /*InsnID*/2,
        GIM_CheckIsSafeToFold, /*InsnID*/3,
        // (smax:{ *:[i32] } (smin:{ *:[i32] } i32:{ *:[i32] }:$src1, i32:{ *:[i32] }:$src0), (smin:{ *:[i32] } (smax:{ *:[i32] } i32:{ *:[i32] }:$src0, i32:{ *:[i32] }:$src1), i32:{ *:[i32] }:$src2))  =>  (V_MED3_I32_e64:{ *:[i32] } VSrc_b32:{ *:[i32] }:$src0, VSrc_b32:{ *:[i32] }:$src1, VSrc_b32:{ *:[i32] }:$src2)
        GIR_BuildMI, /*InsnID*/0, /*Opcode*/GIMT_Encode2(AMDGPU::V_MED3_I32_e64),
        GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/0, // DstI[vdst]
        GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/1, /*OpIdx*/2, // src0
        GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/1, /*OpIdx*/1, // src1
        GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/2, /*OpIdx*/2, // src2
        GIR_ConstrainSelectedInstOperands, /*InsnID*/0,
        GIR_EraseFromParent, /*InsnID*/0,
        // GIR_Coverage, 9958,
        GIR_Done,
      // Label 5324: @393607
      GIM_Try, /*On fail goto*//*Label 5325*/ GIMT_Encode4(393702), // Rule ID 9959 //
        GIM_CheckType, /*MI*/0, /*Op*/2, /*Type*/GILLT_s32,
        GIM_CheckRegBankForClass, /*MI*/0, /*Op*/0, /*RC*/GIMT_Encode2(AMDGPU::VGPR_32RegClassID),
        GIM_RecordInsn, /*DefineMI*/1, /*MI*/0, /*OpIdx*/1, // MIs[1]
        GIM_CheckOpcode, /*MI*/1, GIMT_Encode2(TargetOpcode::G_SMIN),
        GIM_CheckType, /*MI*/1, /*Op*/1, /*Type*/GILLT_s32,
        GIM_CheckType, /*MI*/1, /*Op*/2, /*Type*/GILLT_s32,
        GIM_RecordInsn, /*DefineMI*/2, /*MI*/0, /*OpIdx*/2, // MIs[2]
        GIM_CheckOpcode, /*MI*/2, GIMT_Encode2(TargetOpcode::G_SMIN),
        GIM_CheckType, /*MI*/2, /*Op*/1, /*Type*/GILLT_s32,
        GIM_CheckType, /*MI*/2, /*Op*/2, /*Type*/GILLT_s32,
        GIM_RecordInsn, /*DefineMI*/3, /*MI*/2, /*OpIdx*/1, // MIs[3]
        GIM_CheckOpcode, /*MI*/3, GIMT_Encode2(TargetOpcode::G_SMAX),
        // MIs[3] src1
        GIM_CheckIsSameOperand, /*MI*/3, /*OpIdx*/1, /*OtherMI*/1, /*OtherOpIdx*/1,
        // MIs[3] src0
        GIM_CheckIsSameOperand, /*MI*/3, /*OpIdx*/2, /*OtherMI*/1, /*OtherOpIdx*/2,
        GIM_CheckIsSafeToFold, /*InsnID*/1,
        GIM_CheckIsSafeToFold, /*InsnID*/2,
        GIM_CheckIsSafeToFold, /*InsnID*/3,
        // (smax:{ *:[i32] } (smin:{ *:[i32] } i32:{ *:[i32] }:$src1, i32:{ *:[i32] }:$src0), (smin:{ *:[i32] } (smax:{ *:[i32] } i32:{ *:[i32] }:$src1, i32:{ *:[i32] }:$src0), i32:{ *:[i32] }:$src2))  =>  (V_MED3_I32_e64:{ *:[i32] } VSrc_b32:{ *:[i32] }:$src0, VSrc_b32:{ *:[i32] }:$src1, VSrc_b32:{ *:[i32] }:$src2)
        GIR_BuildMI, /*InsnID*/0, /*Opcode*/GIMT_Encode2(AMDGPU::V_MED3_I32_e64),
        GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/0, // DstI[vdst]
        GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/1, /*OpIdx*/2, // src0
        GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/1, /*OpIdx*/1, // src1
        GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/2, /*OpIdx*/2, // src2
        GIR_ConstrainSelectedInstOperands, /*InsnID*/0,
        GIR_EraseFromParent, /*InsnID*/0,
        // GIR_Coverage, 9959,
        GIR_Done,
      // Label 5325: @393702
      GIM_Try, /*On fail goto*//*Label 5326*/ GIMT_Encode4(393797), // Rule ID 9956 //
        GIM_CheckType, /*MI*/0, /*Op*/2, /*Type*/GILLT_s32,
        GIM_CheckRegBankForClass, /*MI*/0, /*Op*/0, /*RC*/GIMT_Encode2(AMDGPU::VGPR_32RegClassID),
        GIM_RecordInsn, /*DefineMI*/1, /*MI*/0, /*OpIdx*/1, // MIs[1]
        GIM_CheckOpcode, /*MI*/1, GIMT_Encode2(TargetOpcode::G_SMIN),
        GIM_CheckType, /*MI*/1, /*Op*/1, /*Type*/GILLT_s32,
        GIM_CheckType, /*MI*/1, /*Op*/2, /*Type*/GILLT_s32,
        GIM_RecordInsn, /*DefineMI*/2, /*MI*/0, /*OpIdx*/2, // MIs[2]
        GIM_CheckOpcode, /*MI*/2, GIMT_Encode2(TargetOpcode::G_SMIN),
        GIM_CheckType, /*MI*/2, /*Op*/1, /*Type*/GILLT_s32,
        GIM_CheckType, /*MI*/2, /*Op*/2, /*Type*/GILLT_s32,
        GIM_RecordInsn, /*DefineMI*/3, /*MI*/2, /*OpIdx*/2, // MIs[3]
        GIM_CheckOpcode, /*MI*/3, GIMT_Encode2(TargetOpcode::G_SMAX),
        // MIs[3] src0
        GIM_CheckIsSameOperand, /*MI*/3, /*OpIdx*/1, /*OtherMI*/1, /*OtherOpIdx*/1,
        // MIs[3] src1
        GIM_CheckIsSameOperand, /*MI*/3, /*OpIdx*/2, /*OtherMI*/1, /*OtherOpIdx*/2,
        GIM_CheckIsSafeToFold, /*InsnID*/1,
        GIM_CheckIsSafeToFold, /*InsnID*/2,
        GIM_CheckIsSafeToFold, /*InsnID*/3,
        // (smax:{ *:[i32] } (smin:{ *:[i32] } i32:{ *:[i32] }:$src0, i32:{ *:[i32] }:$src1), (smin:{ *:[i32] } i32:{ *:[i32] }:$src2, (smax:{ *:[i32] } i32:{ *:[i32] }:$src0, i32:{ *:[i32] }:$src1)))  =>  (V_MED3_I32_e64:{ *:[i32] } VSrc_b32:{ *:[i32] }:$src0, VSrc_b32:{ *:[i32] }:$src1, VSrc_b32:{ *:[i32] }:$src2)
        GIR_BuildMI, /*InsnID*/0, /*Opcode*/GIMT_Encode2(AMDGPU::V_MED3_I32_e64),
        GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/0, // DstI[vdst]
        GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/1, /*OpIdx*/1, // src0
        GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/1, /*OpIdx*/2, // src1
        GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/2, /*OpIdx*/1, // src2
        GIR_ConstrainSelectedInstOperands, /*InsnID*/0,
        GIR_EraseFromParent, /*InsnID*/0,
        // GIR_Coverage, 9956,
        GIR_Done,
      // Label 5326: @393797
      GIM_Try, /*On fail goto*//*Label 5327*/ GIMT_Encode4(393892), // Rule ID 9957 //
        GIM_CheckType, /*MI*/0, /*Op*/2, /*Type*/GILLT_s32,
        GIM_CheckRegBankForClass, /*MI*/0, /*Op*/0, /*RC*/GIMT_Encode2(AMDGPU::VGPR_32RegClassID),
        GIM_RecordInsn, /*DefineMI*/1, /*MI*/0, /*OpIdx*/1, // MIs[1]
        GIM_CheckOpcode, /*MI*/1, GIMT_Encode2(TargetOpcode::G_SMIN),
        GIM_CheckType, /*MI*/1, /*Op*/1, /*Type*/GILLT_s32,
        GIM_CheckType, /*MI*/1, /*Op*/2, /*Type*/GILLT_s32,
        GIM_RecordInsn, /*DefineMI*/2, /*MI*/0, /*OpIdx*/2, // MIs[2]
        GIM_CheckOpcode, /*MI*/2, GIMT_Encode2(TargetOpcode::G_SMIN),
        GIM_CheckType, /*MI*/2, /*Op*/1, /*Type*/GILLT_s32,
        GIM_CheckType, /*MI*/2, /*Op*/2, /*Type*/GILLT_s32,
        GIM_RecordInsn, /*DefineMI*/3, /*MI*/2, /*OpIdx*/2, // MIs[3]
        GIM_CheckOpcode, /*MI*/3, GIMT_Encode2(TargetOpcode::G_SMAX),
        // MIs[3] src1
        GIM_CheckIsSameOperand, /*MI*/3, /*OpIdx*/1, /*OtherMI*/1, /*OtherOpIdx*/2,
        // MIs[3] src0
        GIM_CheckIsSameOperand, /*MI*/3, /*OpIdx*/2, /*OtherMI*/1, /*OtherOpIdx*/1,
        GIM_CheckIsSafeToFold, /*InsnID*/1,
        GIM_CheckIsSafeToFold, /*InsnID*/2,
        GIM_CheckIsSafeToFold, /*InsnID*/3,
        // (smax:{ *:[i32] } (smin:{ *:[i32] } i32:{ *:[i32] }:$src0, i32:{ *:[i32] }:$src1), (smin:{ *:[i32] } i32:{ *:[i32] }:$src2, (smax:{ *:[i32] } i32:{ *:[i32] }:$src1, i32:{ *:[i32] }:$src0)))  =>  (V_MED3_I32_e64:{ *:[i32] } VSrc_b32:{ *:[i32] }:$src0, VSrc_b32:{ *:[i32] }:$src1, VSrc_b32:{ *:[i32] }:$src2)
        GIR_BuildMI, /*InsnID*/0, /*Opcode*/GIMT_Encode2(AMDGPU::V_MED3_I32_e64),
        GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/0, // DstI[vdst]
        GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/1, /*OpIdx*/1, // src0
        GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/1, /*OpIdx*/2, // src1
        GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/2, /*OpIdx*/1, // src2
        GIR_ConstrainSelectedInstOperands, /*InsnID*/0,
        GIR_EraseFromParent, /*InsnID*/0,
        // GIR_Coverage, 9957,
        GIR_Done,
      // Label 5327: @393892
      GIM_Try, /*On fail goto*//*Label 5328*/ GIMT_Encode4(393987), // Rule ID 9960 //
        GIM_CheckType, /*MI*/0, /*Op*/2, /*Type*/GILLT_s32,
        GIM_CheckRegBankForClass, /*MI*/0, /*Op*/0, /*RC*/GIMT_Encode2(AMDGPU::VGPR_32RegClassID),
        GIM_RecordInsn, /*DefineMI*/1, /*MI*/0, /*OpIdx*/1, // MIs[1]
        GIM_CheckOpcode, /*MI*/1, GIMT_Encode2(TargetOpcode::G_SMIN),
        GIM_CheckType, /*MI*/1, /*Op*/1, /*Type*/GILLT_s32,
        GIM_CheckType, /*MI*/1, /*Op*/2, /*Type*/GILLT_s32,
        GIM_RecordInsn, /*DefineMI*/2, /*MI*/0, /*OpIdx*/2, // MIs[2]
        GIM_CheckOpcode, /*MI*/2, GIMT_Encode2(TargetOpcode::G_SMIN),
        GIM_CheckType, /*MI*/2, /*Op*/1, /*Type*/GILLT_s32,
        GIM_CheckType, /*MI*/2, /*Op*/2, /*Type*/GILLT_s32,
        GIM_RecordInsn, /*DefineMI*/3, /*MI*/2, /*OpIdx*/2, // MIs[3]
        GIM_CheckOpcode, /*MI*/3, GIMT_Encode2(TargetOpcode::G_SMAX),
        // MIs[3] src0
        GIM_CheckIsSameOperand, /*MI*/3, /*OpIdx*/1, /*OtherMI*/1, /*OtherOpIdx*/2,
        // MIs[3] src1
        GIM_CheckIsSameOperand, /*MI*/3, /*OpIdx*/2, /*OtherMI*/1, /*OtherOpIdx*/1,
        GIM_CheckIsSafeToFold, /*InsnID*/1,
        GIM_CheckIsSafeToFold, /*InsnID*/2,
        GIM_CheckIsSafeToFold, /*InsnID*/3,
        // (smax:{ *:[i32] } (smin:{ *:[i32] } i32:{ *:[i32] }:$src1, i32:{ *:[i32] }:$src0), (smin:{ *:[i32] } i32:{ *:[i32] }:$src2, (smax:{ *:[i32] } i32:{ *:[i32] }:$src0, i32:{ *:[i32] }:$src1)))  =>  (V_MED3_I32_e64:{ *:[i32] } VSrc_b32:{ *:[i32] }:$src0, VSrc_b32:{ *:[i32] }:$src1, VSrc_b32:{ *:[i32] }:$src2)
        GIR_BuildMI, /*InsnID*/0, /*Opcode*/GIMT_Encode2(AMDGPU::V_MED3_I32_e64),
        GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/0, // DstI[vdst]
        GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/1, /*OpIdx*/2, // src0
        GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/1, /*OpIdx*/1, // src1
        GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/2, /*OpIdx*/1, // src2
        GIR_ConstrainSelectedInstOperands, /*InsnID*/0,
        GIR_EraseFromParent, /*InsnID*/0,
        // GIR_Coverage, 9960,
        GIR_Done,
      // Label 5328: @393987
      GIM_Try, /*On fail goto*//*Label 5329*/ GIMT_Encode4(394082), // Rule ID 9961 //
        GIM_CheckType, /*MI*/0, /*Op*/2, /*Type*/GILLT_s32,
        GIM_CheckRegBankForClass, /*MI*/0, /*Op*/0, /*RC*/GIMT_Encode2(AMDGPU::VGPR_32RegClassID),
        GIM_RecordInsn, /*DefineMI*/1, /*MI*/0, /*OpIdx*/1, // MIs[1]
        GIM_CheckOpcode, /*MI*/1, GIMT_Encode2(TargetOpcode::G_SMIN),
        GIM_CheckType, /*MI*/1, /*Op*/1, /*Type*/GILLT_s32,
        GIM_CheckType, /*MI*/1, /*Op*/2, /*Type*/GILLT_s32,
        GIM_RecordInsn, /*DefineMI*/2, /*MI*/0, /*OpIdx*/2, // MIs[2]
        GIM_CheckOpcode, /*MI*/2, GIMT_Encode2(TargetOpcode::G_SMIN),
        GIM_CheckType, /*MI*/2, /*Op*/1, /*Type*/GILLT_s32,
        GIM_CheckType, /*MI*/2, /*Op*/2, /*Type*/GILLT_s32,
        GIM_RecordInsn, /*DefineMI*/3, /*MI*/2, /*OpIdx*/2, // MIs[3]
        GIM_CheckOpcode, /*MI*/3, GIMT_Encode2(TargetOpcode::G_SMAX),
        // MIs[3] src1
        GIM_CheckIsSameOperand, /*MI*/3, /*OpIdx*/1, /*OtherMI*/1, /*OtherOpIdx*/1,
        // MIs[3] src0
        GIM_CheckIsSameOperand, /*MI*/3, /*OpIdx*/2, /*OtherMI*/1, /*OtherOpIdx*/2,
        GIM_CheckIsSafeToFold, /*InsnID*/1,
        GIM_CheckIsSafeToFold, /*InsnID*/2,
        GIM_CheckIsSafeToFold, /*InsnID*/3,
        // (smax:{ *:[i32] } (smin:{ *:[i32] } i32:{ *:[i32] }:$src1, i32:{ *:[i32] }:$src0), (smin:{ *:[i32] } i32:{ *:[i32] }:$src2, (smax:{ *:[i32] } i32:{ *:[i32] }:$src1, i32:{ *:[i32] }:$src0)))  =>  (V_MED3_I32_e64:{ *:[i32] } VSrc_b32:{ *:[i32] }:$src0, VSrc_b32:{ *:[i32] }:$src1, VSrc_b32:{ *:[i32] }:$src2)
        GIR_BuildMI, /*InsnID*/0, /*Opcode*/GIMT_Encode2(AMDGPU::V_MED3_I32_e64),
        GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/0, // DstI[vdst]
        GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/1, /*OpIdx*/2, // src0
        GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/1, /*OpIdx*/1, // src1
        GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/2, /*OpIdx*/1, // src2
        GIR_ConstrainSelectedInstOperands, /*InsnID*/0,
        GIR_EraseFromParent, /*InsnID*/0,
        // GIR_Coverage, 9961,
        GIR_Done,
      // Label 5329: @394082
      GIM_Try, /*On fail goto*//*Label 5330*/ GIMT_Encode4(394143), // Rule ID 7195 //
        GIM_CheckRegBankForClass, /*MI*/0, /*Op*/0, /*RC*/GIMT_Encode2(AMDGPU::SReg_32RegClassID),
        GIM_RecordInsn, /*DefineMI*/1, /*MI*/0, /*OpIdx*/1, // MIs[1]
        GIM_CheckOpcode, /*MI*/1, GIMT_Encode2(TargetOpcode::G_SUB),
        GIM_CheckType, /*MI*/1, /*Op*/1, /*Type*/GILLT_s32,
        GIM_CheckType, /*MI*/1, /*Op*/2, /*Type*/GILLT_s32,
        GIM_CheckConstantInt8, /*MI*/1, /*Op*/1, 0,
        // MIs[0] x
        GIM_CheckIsSameOperand, /*MI*/0, /*OpIdx*/2, /*OtherMI*/1, /*OtherOpIdx*/2,
        GIM_CheckCxxInsnPredicate, /*MI*/0, /*FnId*/GIMT_Encode2(GICXXPred_MI_Predicate_anonymous_17609),
        GIM_CheckIsSafeToFold, /*InsnID*/1,
        // (smax:{ *:[i32] } (sub:{ *:[i32] } 0:{ *:[i32] }, i32:{ *:[i32] }:$x), i32:{ *:[i32] }:$x)<<P:Predicate_anonymous_17609>>  =>  (S_ABS_I32:{ *:[i32] }:{ *:[i1] } SReg_32:{ *:[i32] }:$x)
        GIR_BuildMI, /*InsnID*/0, /*Opcode*/GIMT_Encode2(AMDGPU::S_ABS_I32),
        GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/0, // DstI[sdst]
        GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/1, /*OpIdx*/2, // x
        GIR_SetImplicitDefDead, /*InsnID*/0, /*OpIdx for AMDGPU::SCC*/0,
        GIR_ConstrainSelectedInstOperands, /*InsnID*/0,
        GIR_EraseFromParent, /*InsnID*/0,
        // GIR_Coverage, 7195,
        GIR_Done,
      // Label 5330: @394143
      GIM_Try, /*On fail goto*//*Label 5331*/ GIMT_Encode4(394204), // Rule ID 1645 //
        GIM_CheckType, /*MI*/0, /*Op*/2, /*Type*/GILLT_s32,
        GIM_CheckRegBankForClass, /*MI*/0, /*Op*/0, /*RC*/GIMT_Encode2(AMDGPU::SReg_32RegClassID),
        GIM_RecordInsn, /*DefineMI*/1, /*MI*/0, /*OpIdx*/2, // MIs[1]
        GIM_CheckOpcode, /*MI*/1, GIMT_Encode2(TargetOpcode::G_SUB),
        GIM_CheckType, /*MI*/1, /*Op*/1, /*Type*/GILLT_s32,
        GIM_CheckConstantInt8, /*MI*/1, /*Op*/1, 0,
        // MIs[1] x
        GIM_CheckIsSameOperand, /*MI*/1, /*OpIdx*/2, /*OtherMI*/0, /*OtherOpIdx*/1,
        GIM_CheckCxxInsnPredicate, /*MI*/0, /*FnId*/GIMT_Encode2(GICXXPred_MI_Predicate_anonymous_17609),
        GIM_CheckIsSafeToFold, /*InsnID*/1,
        // (smax:{ *:[i32] } i32:{ *:[i32] }:$x, (sub:{ *:[i32] } 0:{ *:[i32] }, i32:{ *:[i32] }:$x))<<P:Predicate_anonymous_17609>>  =>  (S_ABS_I32:{ *:[i32] }:{ *:[i1] } SReg_32:{ *:[i32] }:$x)
        GIR_BuildMI, /*InsnID*/0, /*Opcode*/GIMT_Encode2(AMDGPU::S_ABS_I32),
        GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/0, // DstI[sdst]
        GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/1, // x
        GIR_SetImplicitDefDead, /*InsnID*/0, /*OpIdx for AMDGPU::SCC*/0,
        GIR_ConstrainSelectedInstOperands, /*InsnID*/0,
        GIR_EraseFromParent, /*InsnID*/0,
        // GIR_Coverage, 1645,
        GIR_Done,
      // Label 5331: @394204
      GIM_Try, /*On fail goto*//*Label 5332*/ GIMT_Encode4(394272), // Rule ID 6517 //
        GIM_CheckFeatures, GIMT_Encode2(GIFBS_isGFX11Plus),
        GIM_CheckType, /*MI*/0, /*Op*/2, /*Type*/GILLT_s32,
        GIM_CheckRegBankForClass, /*MI*/0, /*Op*/0, /*RC*/GIMT_Encode2(AMDGPU::VGPR_32RegClassID),
        GIM_RecordInsn, /*DefineMI*/1, /*MI*/0, /*OpIdx*/1, // MIs[1]
        GIM_CheckOpcode, /*MI*/1, GIMT_Encode2(TargetOpcode::G_SMIN),
        GIM_CheckType, /*MI*/1, /*Op*/1, /*Type*/GILLT_s32,
        GIM_CheckType, /*MI*/1, /*Op*/2, /*Type*/GILLT_s32,
        GIM_CheckCxxInsnPredicate, /*MI*/1, /*FnId*/GIMT_Encode2(GICXXPred_MI_Predicate_smin_oneuse),
        GIM_CheckCxxInsnPredicate, /*MI*/0, /*FnId*/GIMT_Encode2(GICXXPred_MI_Predicate_anonymous_35366),
        GIM_CheckIsSafeToFold, /*InsnID*/1,
        // (smax:{ *:[i32] } (smin:{ *:[i32] } i32:{ *:[i32] }:$src0, i32:{ *:[i32] }:$src1)<<P:Predicate_smin_oneuse>>, i32:{ *:[i32] }:$src2)<<P:Predicate_anonymous_35366>>  =>  (V_MINMAX_I32_e64:{ *:[i32] } VSrc_b32:{ *:[i32] }:$src0, VSrc_b32:{ *:[i32] }:$src1, VSrc_b32:{ *:[i32] }:$src2)
        GIR_BuildMI, /*InsnID*/0, /*Opcode*/GIMT_Encode2(AMDGPU::V_MINMAX_I32_e64),
        GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/0, // DstI[vdst]
        GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/1, /*OpIdx*/1, // src0
        GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/1, /*OpIdx*/2, // src1
        GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/2, // src2
        GIR_ConstrainSelectedInstOperands, /*InsnID*/0,
        GIR_EraseFromParent, /*InsnID*/0,
        // GIR_Coverage, 6517,
        GIR_Done,
      // Label 5332: @394272
      GIM_Try, /*On fail goto*//*Label 5333*/ GIMT_Encode4(394340), // Rule ID 10511 //
        GIM_CheckFeatures, GIMT_Encode2(GIFBS_isGFX11Plus),
        GIM_CheckType, /*MI*/0, /*Op*/2, /*Type*/GILLT_s32,
        GIM_CheckRegBankForClass, /*MI*/0, /*Op*/0, /*RC*/GIMT_Encode2(AMDGPU::VGPR_32RegClassID),
        GIM_RecordInsn, /*DefineMI*/1, /*MI*/0, /*OpIdx*/2, // MIs[1]
        GIM_CheckOpcode, /*MI*/1, GIMT_Encode2(TargetOpcode::G_SMIN),
        GIM_CheckType, /*MI*/1, /*Op*/1, /*Type*/GILLT_s32,
        GIM_CheckType, /*MI*/1, /*Op*/2, /*Type*/GILLT_s32,
        GIM_CheckCxxInsnPredicate, /*MI*/1, /*FnId*/GIMT_Encode2(GICXXPred_MI_Predicate_smin_oneuse),
        GIM_CheckCxxInsnPredicate, /*MI*/0, /*FnId*/GIMT_Encode2(GICXXPred_MI_Predicate_anonymous_35366),
        GIM_CheckIsSafeToFold, /*InsnID*/1,
        // (smax:{ *:[i32] } i32:{ *:[i32] }:$src2, (smin:{ *:[i32] } i32:{ *:[i32] }:$src0, i32:{ *:[i32] }:$src1)<<P:Predicate_smin_oneuse>>)<<P:Predicate_anonymous_35366>>  =>  (V_MINMAX_I32_e64:{ *:[i32] } VSrc_b32:{ *:[i32] }:$src0, VSrc_b32:{ *:[i32] }:$src1, VSrc_b32:{ *:[i32] }:$src2)
        GIR_BuildMI, /*InsnID*/0, /*Opcode*/GIMT_Encode2(AMDGPU::V_MINMAX_I32_e64),
        GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/0, // DstI[vdst]
        GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/1, /*OpIdx*/1, // src0
        GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/1, /*OpIdx*/2, // src1
        GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/1, // src2
        GIR_ConstrainSelectedInstOperands, /*InsnID*/0,
        GIR_EraseFromParent, /*InsnID*/0,
        // GIR_Coverage, 10511,
        GIR_Done,
      // Label 5333: @394340
      GIM_Try, /*On fail goto*//*Label 5334*/ GIMT_Encode4(394372), // Rule ID 51 //
        GIM_CheckType, /*MI*/0, /*Op*/2, /*Type*/GILLT_s32,
        GIM_CheckRegBankForClass, /*MI*/0, /*Op*/0, /*RC*/GIMT_Encode2(AMDGPU::SReg_32RegClassID),
        GIM_CheckCxxInsnPredicate, /*MI*/0, /*FnId*/GIMT_Encode2(GICXXPred_MI_Predicate_anonymous_17609),
        // (smax:{ *:[i32] } i32:{ *:[i32] }:$src0, i32:{ *:[i32] }:$src1)<<P:Predicate_anonymous_17609>>  =>  (S_MAX_I32:{ *:[i32] }:{ *:[i1] } i32:{ *:[i32] }:$src0, i32:{ *:[i32] }:$src1)
        GIR_MutateOpcode, /*InsnID*/0, /*RecycleInsnID*/0, /*Opcode*/GIMT_Encode2(AMDGPU::S_MAX_I32),
        GIR_AddImplicitDef, /*InsnID*/0, GIMT_Encode2(AMDGPU::SCC), GIMT_Encode2(RegState::Dead),
        GIR_ConstrainSelectedInstOperands, /*InsnID*/0,
        // GIR_Coverage, 51,
        GIR_Done,
      // Label 5334: @394372
      GIM_Try, /*On fail goto*//*Label 5335*/ GIMT_Encode4(394398), // Rule ID 744 //
        GIM_CheckType, /*MI*/0, /*Op*/2, /*Type*/GILLT_s32,
        GIM_CheckRegBankForClass, /*MI*/0, /*Op*/0, /*RC*/GIMT_Encode2(AMDGPU::VGPR_32RegClassID),
        // (smax:{ *:[i32] } i32:{ *:[i32] }:$src0, i32:{ *:[i32] }:$src1)  =>  (V_MAX_I32_e64:{ *:[i32] } i32:{ *:[i32] }:$src0, i32:{ *:[i32] }:$src1)
        GIR_MutateOpcode, /*InsnID*/0, /*RecycleInsnID*/0, /*Opcode*/GIMT_Encode2(AMDGPU::V_MAX_I32_e64),
        GIR_AddImplicitUse, /*InsnID*/0, GIMT_Encode2(AMDGPU::EXEC),
        GIR_ConstrainSelectedInstOperands, /*InsnID*/0,
        // GIR_Coverage, 744,
        GIR_Done,
      // Label 5335: @394398
      GIM_Reject,
    // Label 5313: @394399
    GIM_Reject,
    // Label 5292: @394400
    GIM_Try, /*On fail goto*//*Label 5336*/ GIMT_Encode4(394480), // Rule ID 972 //
      GIM_CheckType, /*MI*/0, /*Op*/1, /*Type*/GILLT_v2s16,
      GIM_CheckType, /*MI*/0, /*Op*/2, /*Type*/GILLT_v2s16,
      GIM_CheckRegBankForClass, /*MI*/0, /*Op*/0, /*RC*/GIMT_Encode2(AMDGPU::VGPR_32RegClassID),
      GIM_CheckComplexPattern, /*MI*/0, /*Op*/1, /*Renderer*/GIMT_Encode2(0), GIMT_Encode2(GICP_gi_vop3pmods),
      GIM_CheckComplexPattern, /*MI*/0, /*Op*/2, /*Renderer*/GIMT_Encode2(1), GIMT_Encode2(GICP_gi_vop3pmods),
      // (smax:{ *:[v2i16] } (VOP3PMods:{ *:[v2i16] } v2i16:{ *:[v2i16] }:$src0, i32:{ *:[i32] }:$src0_modifiers), (VOP3PMods:{ *:[v2i16] } v2i16:{ *:[v2i16] }:$src1, i32:{ *:[i32] }:$src1_modifiers))  =>  (V_PK_MAX_I16:{ *:[v2i16] } i32:{ *:[i32] }:$src0_modifiers, v2i16:{ *:[v2i16] }:$src0, i32:{ *:[i32] }:$src1_modifiers, v2i16:{ *:[v2i16] }:$src1)
      GIR_BuildMI, /*InsnID*/0, /*Opcode*/GIMT_Encode2(AMDGPU::V_PK_MAX_I16),
      GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/0, // DstI[vdst]
      GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/1, // src0_modifiers
      GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/0, // src0
      GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(1), /*SubOperand*/1, // src1_modifiers
      GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(1), /*SubOperand*/0, // src1
      GIR_AddImm8, /*InsnID*/0, /*Imm*/0,
      GIR_AddImm8, /*InsnID*/0, /*Imm*/0,
      GIR_AddImm8, /*InsnID*/0, /*Imm*/0,
      GIR_AddImm8, /*InsnID*/0, /*Imm*/0,
      GIR_AddImm8, /*InsnID*/0, /*Imm*/0,
      GIR_ConstrainSelectedInstOperands, /*InsnID*/0,
      GIR_EraseFromParent, /*InsnID*/0,
      // GIR_Coverage, 972,
      GIR_Done,
    // Label 5336: @394480
    GIM_Reject,
    // Label 5293: @394481
    GIM_Reject,
    // Label 86: @394482
    GIM_SwitchType, /*MI*/0, /*Op*/0, /*[*/GIMT_Encode2(8), GIMT_Encode2(12), /*)*//*default:*//*Label 5340*/ GIMT_Encode4(397963),
    /*GILLT_s16*//*Label 5337*/ GIMT_Encode4(394509),
    /*GILLT_s32*//*Label 5338*/ GIMT_Encode4(396233), GIMT_Encode4(0),
    /*GILLT_v2s16*//*Label 5339*/ GIMT_Encode4(397882),
    // Label 5337: @394509
    GIM_Try, /*On fail goto*//*Label 5341*/ GIMT_Encode4(396232),
      GIM_CheckType, /*MI*/0, /*Op*/1, /*Type*/GILLT_s16,
      GIM_CheckType, /*MI*/0, /*Op*/2, /*Type*/GILLT_s16,
      GIM_CheckRegBankForClass, /*MI*/0, /*Op*/0, /*RC*/GIMT_Encode2(AMDGPU::VGPR_32RegClassID),
      GIM_Try, /*On fail goto*//*Label 5342*/ GIMT_Encode4(394631), // Rule ID 10792 //
        GIM_CheckFeatures, GIMT_Encode2(GIFBS_isGFX9Plus),
        GIM_RecordInsn, /*DefineMI*/1, /*MI*/0, /*OpIdx*/1, // MIs[1]
        GIM_CheckOpcode, /*MI*/1, GIMT_Encode2(TargetOpcode::G_UMAX),
        GIM_CheckType, /*MI*/1, /*Op*/1, /*Type*/GILLT_s16,
        GIM_CheckType, /*MI*/1, /*Op*/2, /*Type*/GILLT_s16,
        GIM_RecordInsn, /*DefineMI*/2, /*MI*/1, /*OpIdx*/1, // MIs[2]
        GIM_CheckOpcode, /*MI*/2, GIMT_Encode2(TargetOpcode::G_UMIN),
        GIM_CheckType, /*MI*/2, /*Op*/1, /*Type*/GILLT_s16,
        GIM_CheckType, /*MI*/2, /*Op*/2, /*Type*/GILLT_s16,
        GIM_RecordInsn, /*DefineMI*/3, /*MI*/0, /*OpIdx*/2, // MIs[3]
        GIM_CheckOpcode, /*MI*/3, GIMT_Encode2(TargetOpcode::G_UMAX),
        // MIs[3] src0
        GIM_CheckIsSameOperand, /*MI*/3, /*OpIdx*/1, /*OtherMI*/2, /*OtherOpIdx*/1,
        // MIs[3] src1
        GIM_CheckIsSameOperand, /*MI*/3, /*OpIdx*/2, /*OtherMI*/2, /*OtherOpIdx*/2,
        GIM_CheckIsSafeToFold, /*InsnID*/1,
        GIM_CheckIsSafeToFold, /*InsnID*/2,
        GIM_CheckIsSafeToFold, /*InsnID*/3,
        // (umin:{ *:[i16] } (umax:{ *:[i16] } (umin:{ *:[i16] } i16:{ *:[i16] }:$src0, i16:{ *:[i16] }:$src1), i16:{ *:[i16] }:$src2), (umax:{ *:[i16] } i16:{ *:[i16] }:$src0, i16:{ *:[i16] }:$src1))  =>  (V_MED3_U16_e64:{ *:[i16] } 0:{ *:[i32] }, VSrc_b16:{ *:[i16] }:$src0, 0:{ *:[i32] }, VSrc_b16:{ *:[i16] }:$src1, 0:{ *:[i32] }, VSrc_b16:{ *:[i16] }:$src2, 0:{ *:[i1] })
        GIR_BuildMI, /*InsnID*/0, /*Opcode*/GIMT_Encode2(AMDGPU::V_MED3_U16_e64),
        GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/0, // DstI[vdst]
        GIR_AddImm8, /*InsnID*/0, /*Imm*/0,
        GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/2, /*OpIdx*/1, // src0
        GIR_AddImm8, /*InsnID*/0, /*Imm*/0,
        GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/2, /*OpIdx*/2, // src1
        GIR_AddImm8, /*InsnID*/0, /*Imm*/0,
        GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/1, /*OpIdx*/2, // src2
        GIR_AddImm8, /*InsnID*/0, /*Imm*/0,
        GIR_AddImm8, /*InsnID*/0, /*Imm*/0,
        GIR_ConstrainSelectedInstOperands, /*InsnID*/0,
        GIR_EraseFromParent, /*InsnID*/0,
        // GIR_Coverage, 10792,
        GIR_Done,
      // Label 5342: @394631
      GIM_Try, /*On fail goto*//*Label 5343*/ GIMT_Encode4(394735), // Rule ID 10793 //
        GIM_CheckFeatures, GIMT_Encode2(GIFBS_isGFX9Plus),
        GIM_RecordInsn, /*DefineMI*/1, /*MI*/0, /*OpIdx*/1, // MIs[1]
        GIM_CheckOpcode, /*MI*/1, GIMT_Encode2(TargetOpcode::G_UMAX),
        GIM_CheckType, /*MI*/1, /*Op*/1, /*Type*/GILLT_s16,
        GIM_CheckType, /*MI*/1, /*Op*/2, /*Type*/GILLT_s16,
        GIM_RecordInsn, /*DefineMI*/2, /*MI*/1, /*OpIdx*/1, // MIs[2]
        GIM_CheckOpcode, /*MI*/2, GIMT_Encode2(TargetOpcode::G_UMIN),
        GIM_CheckType, /*MI*/2, /*Op*/1, /*Type*/GILLT_s16,
        GIM_CheckType, /*MI*/2, /*Op*/2, /*Type*/GILLT_s16,
        GIM_RecordInsn, /*DefineMI*/3, /*MI*/0, /*OpIdx*/2, // MIs[3]
        GIM_CheckOpcode, /*MI*/3, GIMT_Encode2(TargetOpcode::G_UMAX),
        // MIs[3] src1
        GIM_CheckIsSameOperand, /*MI*/3, /*OpIdx*/1, /*OtherMI*/2, /*OtherOpIdx*/2,
        // MIs[3] src0
        GIM_CheckIsSameOperand, /*MI*/3, /*OpIdx*/2, /*OtherMI*/2, /*OtherOpIdx*/1,
        GIM_CheckIsSafeToFold, /*InsnID*/1,
        GIM_CheckIsSafeToFold, /*InsnID*/2,
        GIM_CheckIsSafeToFold, /*InsnID*/3,
        // (umin:{ *:[i16] } (umax:{ *:[i16] } (umin:{ *:[i16] } i16:{ *:[i16] }:$src0, i16:{ *:[i16] }:$src1), i16:{ *:[i16] }:$src2), (umax:{ *:[i16] } i16:{ *:[i16] }:$src1, i16:{ *:[i16] }:$src0))  =>  (V_MED3_U16_e64:{ *:[i16] } 0:{ *:[i32] }, VSrc_b16:{ *:[i16] }:$src0, 0:{ *:[i32] }, VSrc_b16:{ *:[i16] }:$src1, 0:{ *:[i32] }, VSrc_b16:{ *:[i16] }:$src2, 0:{ *:[i1] })
        GIR_BuildMI, /*InsnID*/0, /*Opcode*/GIMT_Encode2(AMDGPU::V_MED3_U16_e64),
        GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/0, // DstI[vdst]
        GIR_AddImm8, /*InsnID*/0, /*Imm*/0,
        GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/2, /*OpIdx*/1, // src0
        GIR_AddImm8, /*InsnID*/0, /*Imm*/0,
        GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/2, /*OpIdx*/2, // src1
        GIR_AddImm8, /*InsnID*/0, /*Imm*/0,
        GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/1, /*OpIdx*/2, // src2
        GIR_AddImm8, /*InsnID*/0, /*Imm*/0,
        GIR_AddImm8, /*InsnID*/0, /*Imm*/0,
        GIR_ConstrainSelectedInstOperands, /*InsnID*/0,
        GIR_EraseFromParent, /*InsnID*/0,
        // GIR_Coverage, 10793,
        GIR_Done,
      // Label 5343: @394735
      GIM_Try, /*On fail goto*//*Label 5344*/ GIMT_Encode4(394839), // Rule ID 10794 //
        GIM_CheckFeatures, GIMT_Encode2(GIFBS_isGFX9Plus),
        GIM_RecordInsn, /*DefineMI*/1, /*MI*/0, /*OpIdx*/1, // MIs[1]
        GIM_CheckOpcode, /*MI*/1, GIMT_Encode2(TargetOpcode::G_UMAX),
        GIM_CheckType, /*MI*/1, /*Op*/1, /*Type*/GILLT_s16,
        GIM_CheckType, /*MI*/1, /*Op*/2, /*Type*/GILLT_s16,
        GIM_RecordInsn, /*DefineMI*/2, /*MI*/1, /*OpIdx*/1, // MIs[2]
        GIM_CheckOpcode, /*MI*/2, GIMT_Encode2(TargetOpcode::G_UMIN),
        GIM_CheckType, /*MI*/2, /*Op*/1, /*Type*/GILLT_s16,
        GIM_CheckType, /*MI*/2, /*Op*/2, /*Type*/GILLT_s16,
        GIM_RecordInsn, /*DefineMI*/3, /*MI*/0, /*OpIdx*/2, // MIs[3]
        GIM_CheckOpcode, /*MI*/3, GIMT_Encode2(TargetOpcode::G_UMAX),
        // MIs[3] src0
        GIM_CheckIsSameOperand, /*MI*/3, /*OpIdx*/1, /*OtherMI*/2, /*OtherOpIdx*/2,
        // MIs[3] src1
        GIM_CheckIsSameOperand, /*MI*/3, /*OpIdx*/2, /*OtherMI*/2, /*OtherOpIdx*/1,
        GIM_CheckIsSafeToFold, /*InsnID*/1,
        GIM_CheckIsSafeToFold, /*InsnID*/2,
        GIM_CheckIsSafeToFold, /*InsnID*/3,
        // (umin:{ *:[i16] } (umax:{ *:[i16] } (umin:{ *:[i16] } i16:{ *:[i16] }:$src1, i16:{ *:[i16] }:$src0), i16:{ *:[i16] }:$src2), (umax:{ *:[i16] } i16:{ *:[i16] }:$src0, i16:{ *:[i16] }:$src1))  =>  (V_MED3_U16_e64:{ *:[i16] } 0:{ *:[i32] }, VSrc_b16:{ *:[i16] }:$src0, 0:{ *:[i32] }, VSrc_b16:{ *:[i16] }:$src1, 0:{ *:[i32] }, VSrc_b16:{ *:[i16] }:$src2, 0:{ *:[i1] })
        GIR_BuildMI, /*InsnID*/0, /*Opcode*/GIMT_Encode2(AMDGPU::V_MED3_U16_e64),
        GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/0, // DstI[vdst]
        GIR_AddImm8, /*InsnID*/0, /*Imm*/0,
        GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/2, /*OpIdx*/2, // src0
        GIR_AddImm8, /*InsnID*/0, /*Imm*/0,
        GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/2, /*OpIdx*/1, // src1
        GIR_AddImm8, /*InsnID*/0, /*Imm*/0,
        GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/1, /*OpIdx*/2, // src2
        GIR_AddImm8, /*InsnID*/0, /*Imm*/0,
        GIR_AddImm8, /*InsnID*/0, /*Imm*/0,
        GIR_ConstrainSelectedInstOperands, /*InsnID*/0,
        GIR_EraseFromParent, /*InsnID*/0,
        // GIR_Coverage, 10794,
        GIR_Done,
      // Label 5344: @394839
      GIM_Try, /*On fail goto*//*Label 5345*/ GIMT_Encode4(394943), // Rule ID 10795 //
        GIM_CheckFeatures, GIMT_Encode2(GIFBS_isGFX9Plus),
        GIM_RecordInsn, /*DefineMI*/1, /*MI*/0, /*OpIdx*/1, // MIs[1]
        GIM_CheckOpcode, /*MI*/1, GIMT_Encode2(TargetOpcode::G_UMAX),
        GIM_CheckType, /*MI*/1, /*Op*/1, /*Type*/GILLT_s16,
        GIM_CheckType, /*MI*/1, /*Op*/2, /*Type*/GILLT_s16,
        GIM_RecordInsn, /*DefineMI*/2, /*MI*/1, /*OpIdx*/1, // MIs[2]
        GIM_CheckOpcode, /*MI*/2, GIMT_Encode2(TargetOpcode::G_UMIN),
        GIM_CheckType, /*MI*/2, /*Op*/1, /*Type*/GILLT_s16,
        GIM_CheckType, /*MI*/2, /*Op*/2, /*Type*/GILLT_s16,
        GIM_RecordInsn, /*DefineMI*/3, /*MI*/0, /*OpIdx*/2, // MIs[3]
        GIM_CheckOpcode, /*MI*/3, GIMT_Encode2(TargetOpcode::G_UMAX),
        // MIs[3] src1
        GIM_CheckIsSameOperand, /*MI*/3, /*OpIdx*/1, /*OtherMI*/2, /*OtherOpIdx*/1,
        // MIs[3] src0
        GIM_CheckIsSameOperand, /*MI*/3, /*OpIdx*/2, /*OtherMI*/2, /*OtherOpIdx*/2,
        GIM_CheckIsSafeToFold, /*InsnID*/1,
        GIM_CheckIsSafeToFold, /*InsnID*/2,
        GIM_CheckIsSafeToFold, /*InsnID*/3,
        // (umin:{ *:[i16] } (umax:{ *:[i16] } (umin:{ *:[i16] } i16:{ *:[i16] }:$src1, i16:{ *:[i16] }:$src0), i16:{ *:[i16] }:$src2), (umax:{ *:[i16] } i16:{ *:[i16] }:$src1, i16:{ *:[i16] }:$src0))  =>  (V_MED3_U16_e64:{ *:[i16] } 0:{ *:[i32] }, VSrc_b16:{ *:[i16] }:$src0, 0:{ *:[i32] }, VSrc_b16:{ *:[i16] }:$src1, 0:{ *:[i32] }, VSrc_b16:{ *:[i16] }:$src2, 0:{ *:[i1] })
        GIR_BuildMI, /*InsnID*/0, /*Opcode*/GIMT_Encode2(AMDGPU::V_MED3_U16_e64),
        GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/0, // DstI[vdst]
        GIR_AddImm8, /*InsnID*/0, /*Imm*/0,
        GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/2, /*OpIdx*/2, // src0
        GIR_AddImm8, /*InsnID*/0, /*Imm*/0,
        GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/2, /*OpIdx*/1, // src1
        GIR_AddImm8, /*InsnID*/0, /*Imm*/0,
        GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/1, /*OpIdx*/2, // src2
        GIR_AddImm8, /*InsnID*/0, /*Imm*/0,
        GIR_AddImm8, /*InsnID*/0, /*Imm*/0,
        GIR_ConstrainSelectedInstOperands, /*InsnID*/0,
        GIR_EraseFromParent, /*InsnID*/0,
        // GIR_Coverage, 10795,
        GIR_Done,
      // Label 5345: @394943
      GIM_Try, /*On fail goto*//*Label 5346*/ GIMT_Encode4(395047), // Rule ID 10796 //
        GIM_CheckFeatures, GIMT_Encode2(GIFBS_isGFX9Plus),
        GIM_RecordInsn, /*DefineMI*/1, /*MI*/0, /*OpIdx*/1, // MIs[1]
        GIM_CheckOpcode, /*MI*/1, GIMT_Encode2(TargetOpcode::G_UMAX),
        GIM_CheckType, /*MI*/1, /*Op*/1, /*Type*/GILLT_s16,
        GIM_CheckType, /*MI*/1, /*Op*/2, /*Type*/GILLT_s16,
        GIM_RecordInsn, /*DefineMI*/2, /*MI*/1, /*OpIdx*/2, // MIs[2]
        GIM_CheckOpcode, /*MI*/2, GIMT_Encode2(TargetOpcode::G_UMIN),
        GIM_CheckType, /*MI*/2, /*Op*/1, /*Type*/GILLT_s16,
        GIM_CheckType, /*MI*/2, /*Op*/2, /*Type*/GILLT_s16,
        GIM_RecordInsn, /*DefineMI*/3, /*MI*/0, /*OpIdx*/2, // MIs[3]
        GIM_CheckOpcode, /*MI*/3, GIMT_Encode2(TargetOpcode::G_UMAX),
        // MIs[3] src0
        GIM_CheckIsSameOperand, /*MI*/3, /*OpIdx*/1, /*OtherMI*/2, /*OtherOpIdx*/1,
        // MIs[3] src1
        GIM_CheckIsSameOperand, /*MI*/3, /*OpIdx*/2, /*OtherMI*/2, /*OtherOpIdx*/2,
        GIM_CheckIsSafeToFold, /*InsnID*/1,
        GIM_CheckIsSafeToFold, /*InsnID*/2,
        GIM_CheckIsSafeToFold, /*InsnID*/3,
        // (umin:{ *:[i16] } (umax:{ *:[i16] } i16:{ *:[i16] }:$src2, (umin:{ *:[i16] } i16:{ *:[i16] }:$src0, i16:{ *:[i16] }:$src1)), (umax:{ *:[i16] } i16:{ *:[i16] }:$src0, i16:{ *:[i16] }:$src1))  =>  (V_MED3_U16_e64:{ *:[i16] } 0:{ *:[i32] }, VSrc_b16:{ *:[i16] }:$src0, 0:{ *:[i32] }, VSrc_b16:{ *:[i16] }:$src1, 0:{ *:[i32] }, VSrc_b16:{ *:[i16] }:$src2, 0:{ *:[i1] })
        GIR_BuildMI, /*InsnID*/0, /*Opcode*/GIMT_Encode2(AMDGPU::V_MED3_U16_e64),
        GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/0, // DstI[vdst]
        GIR_AddImm8, /*InsnID*/0, /*Imm*/0,
        GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/2, /*OpIdx*/1, // src0
        GIR_AddImm8, /*InsnID*/0, /*Imm*/0,
        GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/2, /*OpIdx*/2, // src1
        GIR_AddImm8, /*InsnID*/0, /*Imm*/0,
        GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/1, /*OpIdx*/1, // src2
        GIR_AddImm8, /*InsnID*/0, /*Imm*/0,
        GIR_AddImm8, /*InsnID*/0, /*Imm*/0,
        GIR_ConstrainSelectedInstOperands, /*InsnID*/0,
        GIR_EraseFromParent, /*InsnID*/0,
        // GIR_Coverage, 10796,
        GIR_Done,
      // Label 5346: @395047
      GIM_Try, /*On fail goto*//*Label 5347*/ GIMT_Encode4(395151), // Rule ID 10797 //
        GIM_CheckFeatures, GIMT_Encode2(GIFBS_isGFX9Plus),
        GIM_RecordInsn, /*DefineMI*/1, /*MI*/0, /*OpIdx*/1, // MIs[1]
        GIM_CheckOpcode, /*MI*/1, GIMT_Encode2(TargetOpcode::G_UMAX),
        GIM_CheckType, /*MI*/1, /*Op*/1, /*Type*/GILLT_s16,
        GIM_CheckType, /*MI*/1, /*Op*/2, /*Type*/GILLT_s16,
        GIM_RecordInsn, /*DefineMI*/2, /*MI*/1, /*OpIdx*/2, // MIs[2]
        GIM_CheckOpcode, /*MI*/2, GIMT_Encode2(TargetOpcode::G_UMIN),
        GIM_CheckType, /*MI*/2, /*Op*/1, /*Type*/GILLT_s16,
        GIM_CheckType, /*MI*/2, /*Op*/2, /*Type*/GILLT_s16,
        GIM_RecordInsn, /*DefineMI*/3, /*MI*/0, /*OpIdx*/2, // MIs[3]
        GIM_CheckOpcode, /*MI*/3, GIMT_Encode2(TargetOpcode::G_UMAX),
        // MIs[3] src1
        GIM_CheckIsSameOperand, /*MI*/3, /*OpIdx*/1, /*OtherMI*/2, /*OtherOpIdx*/2,
        // MIs[3] src0
        GIM_CheckIsSameOperand, /*MI*/3, /*OpIdx*/2, /*OtherMI*/2, /*OtherOpIdx*/1,
        GIM_CheckIsSafeToFold, /*InsnID*/1,
        GIM_CheckIsSafeToFold, /*InsnID*/2,
        GIM_CheckIsSafeToFold, /*InsnID*/3,
        // (umin:{ *:[i16] } (umax:{ *:[i16] } i16:{ *:[i16] }:$src2, (umin:{ *:[i16] } i16:{ *:[i16] }:$src0, i16:{ *:[i16] }:$src1)), (umax:{ *:[i16] } i16:{ *:[i16] }:$src1, i16:{ *:[i16] }:$src0))  =>  (V_MED3_U16_e64:{ *:[i16] } 0:{ *:[i32] }, VSrc_b16:{ *:[i16] }:$src0, 0:{ *:[i32] }, VSrc_b16:{ *:[i16] }:$src1, 0:{ *:[i32] }, VSrc_b16:{ *:[i16] }:$src2, 0:{ *:[i1] })
        GIR_BuildMI, /*InsnID*/0, /*Opcode*/GIMT_Encode2(AMDGPU::V_MED3_U16_e64),
        GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/0, // DstI[vdst]
        GIR_AddImm8, /*InsnID*/0, /*Imm*/0,
        GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/2, /*OpIdx*/1, // src0
        GIR_AddImm8, /*InsnID*/0, /*Imm*/0,
        GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/2, /*OpIdx*/2, // src1
        GIR_AddImm8, /*InsnID*/0, /*Imm*/0,
        GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/1, /*OpIdx*/1, // src2
        GIR_AddImm8, /*InsnID*/0, /*Imm*/0,
        GIR_AddImm8, /*InsnID*/0, /*Imm*/0,
        GIR_ConstrainSelectedInstOperands, /*InsnID*/0,
        GIR_EraseFromParent, /*InsnID*/0,
        // GIR_Coverage, 10797,
        GIR_Done,
      // Label 5347: @395151
      GIM_Try, /*On fail goto*//*Label 5348*/ GIMT_Encode4(395255), // Rule ID 10798 //
        GIM_CheckFeatures, GIMT_Encode2(GIFBS_isGFX9Plus),
        GIM_RecordInsn, /*DefineMI*/1, /*MI*/0, /*OpIdx*/1, // MIs[1]
        GIM_CheckOpcode, /*MI*/1, GIMT_Encode2(TargetOpcode::G_UMAX),
        GIM_CheckType, /*MI*/1, /*Op*/1, /*Type*/GILLT_s16,
        GIM_CheckType, /*MI*/1, /*Op*/2, /*Type*/GILLT_s16,
        GIM_RecordInsn, /*DefineMI*/2, /*MI*/1, /*OpIdx*/2, // MIs[2]
        GIM_CheckOpcode, /*MI*/2, GIMT_Encode2(TargetOpcode::G_UMIN),
        GIM_CheckType, /*MI*/2, /*Op*/1, /*Type*/GILLT_s16,
        GIM_CheckType, /*MI*/2, /*Op*/2, /*Type*/GILLT_s16,
        GIM_RecordInsn, /*DefineMI*/3, /*MI*/0, /*OpIdx*/2, // MIs[3]
        GIM_CheckOpcode, /*MI*/3, GIMT_Encode2(TargetOpcode::G_UMAX),
        // MIs[3] src0
        GIM_CheckIsSameOperand, /*MI*/3, /*OpIdx*/1, /*OtherMI*/2, /*OtherOpIdx*/2,
        // MIs[3] src1
        GIM_CheckIsSameOperand, /*MI*/3, /*OpIdx*/2, /*OtherMI*/2, /*OtherOpIdx*/1,
        GIM_CheckIsSafeToFold, /*InsnID*/1,
        GIM_CheckIsSafeToFold, /*InsnID*/2,
        GIM_CheckIsSafeToFold, /*InsnID*/3,
        // (umin:{ *:[i16] } (umax:{ *:[i16] } i16:{ *:[i16] }:$src2, (umin:{ *:[i16] } i16:{ *:[i16] }:$src1, i16:{ *:[i16] }:$src0)), (umax:{ *:[i16] } i16:{ *:[i16] }:$src0, i16:{ *:[i16] }:$src1))  =>  (V_MED3_U16_e64:{ *:[i16] } 0:{ *:[i32] }, VSrc_b16:{ *:[i16] }:$src0, 0:{ *:[i32] }, VSrc_b16:{ *:[i16] }:$src1, 0:{ *:[i32] }, VSrc_b16:{ *:[i16] }:$src2, 0:{ *:[i1] })
        GIR_BuildMI, /*InsnID*/0, /*Opcode*/GIMT_Encode2(AMDGPU::V_MED3_U16_e64),
        GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/0, // DstI[vdst]
        GIR_AddImm8, /*InsnID*/0, /*Imm*/0,
        GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/2, /*OpIdx*/2, // src0
        GIR_AddImm8, /*InsnID*/0, /*Imm*/0,
        GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/2, /*OpIdx*/1, // src1
        GIR_AddImm8, /*InsnID*/0, /*Imm*/0,
        GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/1, /*OpIdx*/1, // src2
        GIR_AddImm8, /*InsnID*/0, /*Imm*/0,
        GIR_AddImm8, /*InsnID*/0, /*Imm*/0,
        GIR_ConstrainSelectedInstOperands, /*InsnID*/0,
        GIR_EraseFromParent, /*InsnID*/0,
        // GIR_Coverage, 10798,
        GIR_Done,
      // Label 5348: @395255
      GIM_Try, /*On fail goto*//*Label 5349*/ GIMT_Encode4(395359), // Rule ID 10799 //
        GIM_CheckFeatures, GIMT_Encode2(GIFBS_isGFX9Plus),
        GIM_RecordInsn, /*DefineMI*/1, /*MI*/0, /*OpIdx*/1, // MIs[1]
        GIM_CheckOpcode, /*MI*/1, GIMT_Encode2(TargetOpcode::G_UMAX),
        GIM_CheckType, /*MI*/1, /*Op*/1, /*Type*/GILLT_s16,
        GIM_CheckType, /*MI*/1, /*Op*/2, /*Type*/GILLT_s16,
        GIM_RecordInsn, /*DefineMI*/2, /*MI*/1, /*OpIdx*/2, // MIs[2]
        GIM_CheckOpcode, /*MI*/2, GIMT_Encode2(TargetOpcode::G_UMIN),
        GIM_CheckType, /*MI*/2, /*Op*/1, /*Type*/GILLT_s16,
        GIM_CheckType, /*MI*/2, /*Op*/2, /*Type*/GILLT_s16,
        GIM_RecordInsn, /*DefineMI*/3, /*MI*/0, /*OpIdx*/2, // MIs[3]
        GIM_CheckOpcode, /*MI*/3, GIMT_Encode2(TargetOpcode::G_UMAX),
        // MIs[3] src1
        GIM_CheckIsSameOperand, /*MI*/3, /*OpIdx*/1, /*OtherMI*/2, /*OtherOpIdx*/1,
        // MIs[3] src0
        GIM_CheckIsSameOperand, /*MI*/3, /*OpIdx*/2, /*OtherMI*/2, /*OtherOpIdx*/2,
        GIM_CheckIsSafeToFold, /*InsnID*/1,
        GIM_CheckIsSafeToFold, /*InsnID*/2,
        GIM_CheckIsSafeToFold, /*InsnID*/3,
        // (umin:{ *:[i16] } (umax:{ *:[i16] } i16:{ *:[i16] }:$src2, (umin:{ *:[i16] } i16:{ *:[i16] }:$src1, i16:{ *:[i16] }:$src0)), (umax:{ *:[i16] } i16:{ *:[i16] }:$src1, i16:{ *:[i16] }:$src0))  =>  (V_MED3_U16_e64:{ *:[i16] } 0:{ *:[i32] }, VSrc_b16:{ *:[i16] }:$src0, 0:{ *:[i32] }, VSrc_b16:{ *:[i16] }:$src1, 0:{ *:[i32] }, VSrc_b16:{ *:[i16] }:$src2, 0:{ *:[i1] })
        GIR_BuildMI, /*InsnID*/0, /*Opcode*/GIMT_Encode2(AMDGPU::V_MED3_U16_e64),
        GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/0, // DstI[vdst]
        GIR_AddImm8, /*InsnID*/0, /*Imm*/0,
        GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/2, /*OpIdx*/2, // src0
        GIR_AddImm8, /*InsnID*/0, /*Imm*/0,
        GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/2, /*OpIdx*/1, // src1
        GIR_AddImm8, /*InsnID*/0, /*Imm*/0,
        GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/1, /*OpIdx*/1, // src2
        GIR_AddImm8, /*InsnID*/0, /*Imm*/0,
        GIR_AddImm8, /*InsnID*/0, /*Imm*/0,
        GIR_ConstrainSelectedInstOperands, /*InsnID*/0,
        GIR_EraseFromParent, /*InsnID*/0,
        // GIR_Coverage, 10799,
        GIR_Done,
      // Label 5349: @395359
      GIM_Try, /*On fail goto*//*Label 5350*/ GIMT_Encode4(395463), // Rule ID 6553 //
        GIM_CheckFeatures, GIMT_Encode2(GIFBS_isGFX9Plus),
        GIM_RecordInsn, /*DefineMI*/1, /*MI*/0, /*OpIdx*/1, // MIs[1]
        GIM_CheckOpcode, /*MI*/1, GIMT_Encode2(TargetOpcode::G_UMAX),
        GIM_CheckType, /*MI*/1, /*Op*/1, /*Type*/GILLT_s16,
        GIM_CheckType, /*MI*/1, /*Op*/2, /*Type*/GILLT_s16,
        GIM_RecordInsn, /*DefineMI*/2, /*MI*/0, /*OpIdx*/2, // MIs[2]
        GIM_CheckOpcode, /*MI*/2, GIMT_Encode2(TargetOpcode::G_UMAX),
        GIM_CheckType, /*MI*/2, /*Op*/1, /*Type*/GILLT_s16,
        GIM_CheckType, /*MI*/2, /*Op*/2, /*Type*/GILLT_s16,
        GIM_RecordInsn, /*DefineMI*/3, /*MI*/2, /*OpIdx*/1, // MIs[3]
        GIM_CheckOpcode, /*MI*/3, GIMT_Encode2(TargetOpcode::G_UMIN),
        // MIs[3] src0
        GIM_CheckIsSameOperand, /*MI*/3, /*OpIdx*/1, /*OtherMI*/1, /*OtherOpIdx*/1,
        // MIs[3] src1
        GIM_CheckIsSameOperand, /*MI*/3, /*OpIdx*/2, /*OtherMI*/1, /*OtherOpIdx*/2,
        GIM_CheckIsSafeToFold, /*InsnID*/1,
        GIM_CheckIsSafeToFold, /*InsnID*/2,
        GIM_CheckIsSafeToFold, /*InsnID*/3,
        // (umin:{ *:[i16] } (umax:{ *:[i16] } i16:{ *:[i16] }:$src0, i16:{ *:[i16] }:$src1), (umax:{ *:[i16] } (umin:{ *:[i16] } i16:{ *:[i16] }:$src0, i16:{ *:[i16] }:$src1), i16:{ *:[i16] }:$src2))  =>  (V_MED3_U16_e64:{ *:[i16] } 0:{ *:[i32] }, VSrc_b16:{ *:[i16] }:$src0, 0:{ *:[i32] }, VSrc_b16:{ *:[i16] }:$src1, 0:{ *:[i32] }, VSrc_b16:{ *:[i16] }:$src2, 0:{ *:[i1] })
        GIR_BuildMI, /*InsnID*/0, /*Opcode*/GIMT_Encode2(AMDGPU::V_MED3_U16_e64),
        GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/0, // DstI[vdst]
        GIR_AddImm8, /*InsnID*/0, /*Imm*/0,
        GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/1, /*OpIdx*/1, // src0
        GIR_AddImm8, /*InsnID*/0, /*Imm*/0,
        GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/1, /*OpIdx*/2, // src1
        GIR_AddImm8, /*InsnID*/0, /*Imm*/0,
        GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/2, /*OpIdx*/2, // src2
        GIR_AddImm8, /*InsnID*/0, /*Imm*/0,
        GIR_AddImm8, /*InsnID*/0, /*Imm*/0,
        GIR_ConstrainSelectedInstOperands, /*InsnID*/0,
        GIR_EraseFromParent, /*InsnID*/0,
        // GIR_Coverage, 6553,
        GIR_Done,
      // Label 5350: @395463
      GIM_Try, /*On fail goto*//*Label 5351*/ GIMT_Encode4(395567), // Rule ID 10785 //
        GIM_CheckFeatures, GIMT_Encode2(GIFBS_isGFX9Plus),
        GIM_RecordInsn, /*DefineMI*/1, /*MI*/0, /*OpIdx*/1, // MIs[1]
        GIM_CheckOpcode, /*MI*/1, GIMT_Encode2(TargetOpcode::G_UMAX),
        GIM_CheckType, /*MI*/1, /*Op*/1, /*Type*/GILLT_s16,
        GIM_CheckType, /*MI*/1, /*Op*/2, /*Type*/GILLT_s16,
        GIM_RecordInsn, /*DefineMI*/2, /*MI*/0, /*OpIdx*/2, // MIs[2]
        GIM_CheckOpcode, /*MI*/2, GIMT_Encode2(TargetOpcode::G_UMAX),
        GIM_CheckType, /*MI*/2, /*Op*/1, /*Type*/GILLT_s16,
        GIM_CheckType, /*MI*/2, /*Op*/2, /*Type*/GILLT_s16,
        GIM_RecordInsn, /*DefineMI*/3, /*MI*/2, /*OpIdx*/1, // MIs[3]
        GIM_CheckOpcode, /*MI*/3, GIMT_Encode2(TargetOpcode::G_UMIN),
        // MIs[3] src1
        GIM_CheckIsSameOperand, /*MI*/3, /*OpIdx*/1, /*OtherMI*/1, /*OtherOpIdx*/2,
        // MIs[3] src0
        GIM_CheckIsSameOperand, /*MI*/3, /*OpIdx*/2, /*OtherMI*/1, /*OtherOpIdx*/1,
        GIM_CheckIsSafeToFold, /*InsnID*/1,
        GIM_CheckIsSafeToFold, /*InsnID*/2,
        GIM_CheckIsSafeToFold, /*InsnID*/3,
        // (umin:{ *:[i16] } (umax:{ *:[i16] } i16:{ *:[i16] }:$src0, i16:{ *:[i16] }:$src1), (umax:{ *:[i16] } (umin:{ *:[i16] } i16:{ *:[i16] }:$src1, i16:{ *:[i16] }:$src0), i16:{ *:[i16] }:$src2))  =>  (V_MED3_U16_e64:{ *:[i16] } 0:{ *:[i32] }, VSrc_b16:{ *:[i16] }:$src0, 0:{ *:[i32] }, VSrc_b16:{ *:[i16] }:$src1, 0:{ *:[i32] }, VSrc_b16:{ *:[i16] }:$src2, 0:{ *:[i1] })
        GIR_BuildMI, /*InsnID*/0, /*Opcode*/GIMT_Encode2(AMDGPU::V_MED3_U16_e64),
        GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/0, // DstI[vdst]
        GIR_AddImm8, /*InsnID*/0, /*Imm*/0,
        GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/1, /*OpIdx*/1, // src0
        GIR_AddImm8, /*InsnID*/0, /*Imm*/0,
        GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/1, /*OpIdx*/2, // src1
        GIR_AddImm8, /*InsnID*/0, /*Imm*/0,
        GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/2, /*OpIdx*/2, // src2
        GIR_AddImm8, /*InsnID*/0, /*Imm*/0,
        GIR_AddImm8, /*InsnID*/0, /*Imm*/0,
        GIR_ConstrainSelectedInstOperands, /*InsnID*/0,
        GIR_EraseFromParent, /*InsnID*/0,
        // GIR_Coverage, 10785,
        GIR_Done,
      // Label 5351: @395567
      GIM_Try, /*On fail goto*//*Label 5352*/ GIMT_Encode4(395671), // Rule ID 10788 //
        GIM_CheckFeatures, GIMT_Encode2(GIFBS_isGFX9Plus),
        GIM_RecordInsn, /*DefineMI*/1, /*MI*/0, /*OpIdx*/1, // MIs[1]
        GIM_CheckOpcode, /*MI*/1, GIMT_Encode2(TargetOpcode::G_UMAX),
        GIM_CheckType, /*MI*/1, /*Op*/1, /*Type*/GILLT_s16,
        GIM_CheckType, /*MI*/1, /*Op*/2, /*Type*/GILLT_s16,
        GIM_RecordInsn, /*DefineMI*/2, /*MI*/0, /*OpIdx*/2, // MIs[2]
        GIM_CheckOpcode, /*MI*/2, GIMT_Encode2(TargetOpcode::G_UMAX),
        GIM_CheckType, /*MI*/2, /*Op*/1, /*Type*/GILLT_s16,
        GIM_CheckType, /*MI*/2, /*Op*/2, /*Type*/GILLT_s16,
        GIM_RecordInsn, /*DefineMI*/3, /*MI*/2, /*OpIdx*/1, // MIs[3]
        GIM_CheckOpcode, /*MI*/3, GIMT_Encode2(TargetOpcode::G_UMIN),
        // MIs[3] src0
        GIM_CheckIsSameOperand, /*MI*/3, /*OpIdx*/1, /*OtherMI*/1, /*OtherOpIdx*/2,
        // MIs[3] src1
        GIM_CheckIsSameOperand, /*MI*/3, /*OpIdx*/2, /*OtherMI*/1, /*OtherOpIdx*/1,
        GIM_CheckIsSafeToFold, /*InsnID*/1,
        GIM_CheckIsSafeToFold, /*InsnID*/2,
        GIM_CheckIsSafeToFold, /*InsnID*/3,
        // (umin:{ *:[i16] } (umax:{ *:[i16] } i16:{ *:[i16] }:$src1, i16:{ *:[i16] }:$src0), (umax:{ *:[i16] } (umin:{ *:[i16] } i16:{ *:[i16] }:$src0, i16:{ *:[i16] }:$src1), i16:{ *:[i16] }:$src2))  =>  (V_MED3_U16_e64:{ *:[i16] } 0:{ *:[i32] }, VSrc_b16:{ *:[i16] }:$src0, 0:{ *:[i32] }, VSrc_b16:{ *:[i16] }:$src1, 0:{ *:[i32] }, VSrc_b16:{ *:[i16] }:$src2, 0:{ *:[i1] })
        GIR_BuildMI, /*InsnID*/0, /*Opcode*/GIMT_Encode2(AMDGPU::V_MED3_U16_e64),
        GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/0, // DstI[vdst]
        GIR_AddImm8, /*InsnID*/0, /*Imm*/0,
        GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/1, /*OpIdx*/2, // src0
        GIR_AddImm8, /*InsnID*/0, /*Imm*/0,
        GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/1, /*OpIdx*/1, // src1
        GIR_AddImm8, /*InsnID*/0, /*Imm*/0,
        GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/2, /*OpIdx*/2, // src2
        GIR_AddImm8, /*InsnID*/0, /*Imm*/0,
        GIR_AddImm8, /*InsnID*/0, /*Imm*/0,
        GIR_ConstrainSelectedInstOperands, /*InsnID*/0,
        GIR_EraseFromParent, /*InsnID*/0,
        // GIR_Coverage, 10788,
        GIR_Done,
      // Label 5352: @395671
      GIM_Try, /*On fail goto*//*Label 5353*/ GIMT_Encode4(395775), // Rule ID 10789 //
        GIM_CheckFeatures, GIMT_Encode2(GIFBS_isGFX9Plus),
        GIM_RecordInsn, /*DefineMI*/1, /*MI*/0, /*OpIdx*/1, // MIs[1]
        GIM_CheckOpcode, /*MI*/1, GIMT_Encode2(TargetOpcode::G_UMAX),
        GIM_CheckType, /*MI*/1, /*Op*/1, /*Type*/GILLT_s16,
        GIM_CheckType, /*MI*/1, /*Op*/2, /*Type*/GILLT_s16,
        GIM_RecordInsn, /*DefineMI*/2, /*MI*/0, /*OpIdx*/2, // MIs[2]
        GIM_CheckOpcode, /*MI*/2, GIMT_Encode2(TargetOpcode::G_UMAX),
        GIM_CheckType, /*MI*/2, /*Op*/1, /*Type*/GILLT_s16,
        GIM_CheckType, /*MI*/2, /*Op*/2, /*Type*/GILLT_s16,
        GIM_RecordInsn, /*DefineMI*/3, /*MI*/2, /*OpIdx*/1, // MIs[3]
        GIM_CheckOpcode, /*MI*/3, GIMT_Encode2(TargetOpcode::G_UMIN),
        // MIs[3] src1
        GIM_CheckIsSameOperand, /*MI*/3, /*OpIdx*/1, /*OtherMI*/1, /*OtherOpIdx*/1,
        // MIs[3] src0
        GIM_CheckIsSameOperand, /*MI*/3, /*OpIdx*/2, /*OtherMI*/1, /*OtherOpIdx*/2,
        GIM_CheckIsSafeToFold, /*InsnID*/1,
        GIM_CheckIsSafeToFold, /*InsnID*/2,
        GIM_CheckIsSafeToFold, /*InsnID*/3,
        // (umin:{ *:[i16] } (umax:{ *:[i16] } i16:{ *:[i16] }:$src1, i16:{ *:[i16] }:$src0), (umax:{ *:[i16] } (umin:{ *:[i16] } i16:{ *:[i16] }:$src1, i16:{ *:[i16] }:$src0), i16:{ *:[i16] }:$src2))  =>  (V_MED3_U16_e64:{ *:[i16] } 0:{ *:[i32] }, VSrc_b16:{ *:[i16] }:$src0, 0:{ *:[i32] }, VSrc_b16:{ *:[i16] }:$src1, 0:{ *:[i32] }, VSrc_b16:{ *:[i16] }:$src2, 0:{ *:[i1] })
        GIR_BuildMI, /*InsnID*/0, /*Opcode*/GIMT_Encode2(AMDGPU::V_MED3_U16_e64),
        GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/0, // DstI[vdst]
        GIR_AddImm8, /*InsnID*/0, /*Imm*/0,
        GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/1, /*OpIdx*/2, // src0
        GIR_AddImm8, /*InsnID*/0, /*Imm*/0,
        GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/1, /*OpIdx*/1, // src1
        GIR_AddImm8, /*InsnID*/0, /*Imm*/0,
        GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/2, /*OpIdx*/2, // src2
        GIR_AddImm8, /*InsnID*/0, /*Imm*/0,
        GIR_AddImm8, /*InsnID*/0, /*Imm*/0,
        GIR_ConstrainSelectedInstOperands, /*InsnID*/0,
        GIR_EraseFromParent, /*InsnID*/0,
        // GIR_Coverage, 10789,
        GIR_Done,
      // Label 5353: @395775
      GIM_Try, /*On fail goto*//*Label 5354*/ GIMT_Encode4(395879), // Rule ID 10786 //
        GIM_CheckFeatures, GIMT_Encode2(GIFBS_isGFX9Plus),
        GIM_RecordInsn, /*DefineMI*/1, /*MI*/0, /*OpIdx*/1, // MIs[1]
        GIM_CheckOpcode, /*MI*/1, GIMT_Encode2(TargetOpcode::G_UMAX),
        GIM_CheckType, /*MI*/1, /*Op*/1, /*Type*/GILLT_s16,
        GIM_CheckType, /*MI*/1, /*Op*/2, /*Type*/GILLT_s16,
        GIM_RecordInsn, /*DefineMI*/2, /*MI*/0, /*OpIdx*/2, // MIs[2]
        GIM_CheckOpcode, /*MI*/2, GIMT_Encode2(TargetOpcode::G_UMAX),
        GIM_CheckType, /*MI*/2, /*Op*/1, /*Type*/GILLT_s16,
        GIM_CheckType, /*MI*/2, /*Op*/2, /*Type*/GILLT_s16,
        GIM_RecordInsn, /*DefineMI*/3, /*MI*/2, /*OpIdx*/2, // MIs[3]
        GIM_CheckOpcode, /*MI*/3, GIMT_Encode2(TargetOpcode::G_UMIN),
        // MIs[3] src0
        GIM_CheckIsSameOperand, /*MI*/3, /*OpIdx*/1, /*OtherMI*/1, /*OtherOpIdx*/1,
        // MIs[3] src1
        GIM_CheckIsSameOperand, /*MI*/3, /*OpIdx*/2, /*OtherMI*/1, /*OtherOpIdx*/2,
        GIM_CheckIsSafeToFold, /*InsnID*/1,
        GIM_CheckIsSafeToFold, /*InsnID*/2,
        GIM_CheckIsSafeToFold, /*InsnID*/3,
        // (umin:{ *:[i16] } (umax:{ *:[i16] } i16:{ *:[i16] }:$src0, i16:{ *:[i16] }:$src1), (umax:{ *:[i16] } i16:{ *:[i16] }:$src2, (umin:{ *:[i16] } i16:{ *:[i16] }:$src0, i16:{ *:[i16] }:$src1)))  =>  (V_MED3_U16_e64:{ *:[i16] } 0:{ *:[i32] }, VSrc_b16:{ *:[i16] }:$src0, 0:{ *:[i32] }, VSrc_b16:{ *:[i16] }:$src1, 0:{ *:[i32] }, VSrc_b16:{ *:[i16] }:$src2, 0:{ *:[i1] })
        GIR_BuildMI, /*InsnID*/0, /*Opcode*/GIMT_Encode2(AMDGPU::V_MED3_U16_e64),
        GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/0, // DstI[vdst]
        GIR_AddImm8, /*InsnID*/0, /*Imm*/0,
        GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/1, /*OpIdx*/1, // src0
        GIR_AddImm8, /*InsnID*/0, /*Imm*/0,
        GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/1, /*OpIdx*/2, // src1
        GIR_AddImm8, /*InsnID*/0, /*Imm*/0,
        GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/2, /*OpIdx*/1, // src2
        GIR_AddImm8, /*InsnID*/0, /*Imm*/0,
        GIR_AddImm8, /*InsnID*/0, /*Imm*/0,
        GIR_ConstrainSelectedInstOperands, /*InsnID*/0,
        GIR_EraseFromParent, /*InsnID*/0,
        // GIR_Coverage, 10786,
        GIR_Done,
      // Label 5354: @395879
      GIM_Try, /*On fail goto*//*Label 5355*/ GIMT_Encode4(395983), // Rule ID 10787 //
        GIM_CheckFeatures, GIMT_Encode2(GIFBS_isGFX9Plus),
        GIM_RecordInsn, /*DefineMI*/1, /*MI*/0, /*OpIdx*/1, // MIs[1]
        GIM_CheckOpcode, /*MI*/1, GIMT_Encode2(TargetOpcode::G_UMAX),
        GIM_CheckType, /*MI*/1, /*Op*/1, /*Type*/GILLT_s16,
        GIM_CheckType, /*MI*/1, /*Op*/2, /*Type*/GILLT_s16,
        GIM_RecordInsn, /*DefineMI*/2, /*MI*/0, /*OpIdx*/2, // MIs[2]
        GIM_CheckOpcode, /*MI*/2, GIMT_Encode2(TargetOpcode::G_UMAX),
        GIM_CheckType, /*MI*/2, /*Op*/1, /*Type*/GILLT_s16,
        GIM_CheckType, /*MI*/2, /*Op*/2, /*Type*/GILLT_s16,
        GIM_RecordInsn, /*DefineMI*/3, /*MI*/2, /*OpIdx*/2, // MIs[3]
        GIM_CheckOpcode, /*MI*/3, GIMT_Encode2(TargetOpcode::G_UMIN),
        // MIs[3] src1
        GIM_CheckIsSameOperand, /*MI*/3, /*OpIdx*/1, /*OtherMI*/1, /*OtherOpIdx*/2,
        // MIs[3] src0
        GIM_CheckIsSameOperand, /*MI*/3, /*OpIdx*/2, /*OtherMI*/1, /*OtherOpIdx*/1,
        GIM_CheckIsSafeToFold, /*InsnID*/1,
        GIM_CheckIsSafeToFold, /*InsnID*/2,
        GIM_CheckIsSafeToFold, /*InsnID*/3,
        // (umin:{ *:[i16] } (umax:{ *:[i16] } i16:{ *:[i16] }:$src0, i16:{ *:[i16] }:$src1), (umax:{ *:[i16] } i16:{ *:[i16] }:$src2, (umin:{ *:[i16] } i16:{ *:[i16] }:$src1, i16:{ *:[i16] }:$src0)))  =>  (V_MED3_U16_e64:{ *:[i16] } 0:{ *:[i32] }, VSrc_b16:{ *:[i16] }:$src0, 0:{ *:[i32] }, VSrc_b16:{ *:[i16] }:$src1, 0:{ *:[i32] }, VSrc_b16:{ *:[i16] }:$src2, 0:{ *:[i1] })
        GIR_BuildMI, /*InsnID*/0, /*Opcode*/GIMT_Encode2(AMDGPU::V_MED3_U16_e64),
        GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/0, // DstI[vdst]
        GIR_AddImm8, /*InsnID*/0, /*Imm*/0,
        GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/1, /*OpIdx*/1, // src0
        GIR_AddImm8, /*InsnID*/0, /*Imm*/0,
        GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/1, /*OpIdx*/2, // src1
        GIR_AddImm8, /*InsnID*/0, /*Imm*/0,
        GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/2, /*OpIdx*/1, // src2
        GIR_AddImm8, /*InsnID*/0, /*Imm*/0,
        GIR_AddImm8, /*InsnID*/0, /*Imm*/0,
        GIR_ConstrainSelectedInstOperands, /*InsnID*/0,
        GIR_EraseFromParent, /*InsnID*/0,
        // GIR_Coverage, 10787,
        GIR_Done,
      // Label 5355: @395983
      GIM_Try, /*On fail goto*//*Label 5356*/ GIMT_Encode4(396087), // Rule ID 10790 //
        GIM_CheckFeatures, GIMT_Encode2(GIFBS_isGFX9Plus),
        GIM_RecordInsn, /*DefineMI*/1, /*MI*/0, /*OpIdx*/1, // MIs[1]
        GIM_CheckOpcode, /*MI*/1, GIMT_Encode2(TargetOpcode::G_UMAX),
        GIM_CheckType, /*MI*/1, /*Op*/1, /*Type*/GILLT_s16,
        GIM_CheckType, /*MI*/1, /*Op*/2, /*Type*/GILLT_s16,
        GIM_RecordInsn, /*DefineMI*/2, /*MI*/0, /*OpIdx*/2, // MIs[2]
        GIM_CheckOpcode, /*MI*/2, GIMT_Encode2(TargetOpcode::G_UMAX),
        GIM_CheckType, /*MI*/2, /*Op*/1, /*Type*/GILLT_s16,
        GIM_CheckType, /*MI*/2, /*Op*/2, /*Type*/GILLT_s16,
        GIM_RecordInsn, /*DefineMI*/3, /*MI*/2, /*OpIdx*/2, // MIs[3]
        GIM_CheckOpcode, /*MI*/3, GIMT_Encode2(TargetOpcode::G_UMIN),
        // MIs[3] src0
        GIM_CheckIsSameOperand, /*MI*/3, /*OpIdx*/1, /*OtherMI*/1, /*OtherOpIdx*/2,
        // MIs[3] src1
        GIM_CheckIsSameOperand, /*MI*/3, /*OpIdx*/2, /*OtherMI*/1, /*OtherOpIdx*/1,
        GIM_CheckIsSafeToFold, /*InsnID*/1,
        GIM_CheckIsSafeToFold, /*InsnID*/2,
        GIM_CheckIsSafeToFold, /*InsnID*/3,
        // (umin:{ *:[i16] } (umax:{ *:[i16] } i16:{ *:[i16] }:$src1, i16:{ *:[i16] }:$src0), (umax:{ *:[i16] } i16:{ *:[i16] }:$src2, (umin:{ *:[i16] } i16:{ *:[i16] }:$src0, i16:{ *:[i16] }:$src1)))  =>  (V_MED3_U16_e64:{ *:[i16] } 0:{ *:[i32] }, VSrc_b16:{ *:[i16] }:$src0, 0:{ *:[i32] }, VSrc_b16:{ *:[i16] }:$src1, 0:{ *:[i32] }, VSrc_b16:{ *:[i16] }:$src2, 0:{ *:[i1] })
        GIR_BuildMI, /*InsnID*/0, /*Opcode*/GIMT_Encode2(AMDGPU::V_MED3_U16_e64),
        GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/0, // DstI[vdst]
        GIR_AddImm8, /*InsnID*/0, /*Imm*/0,
        GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/1, /*OpIdx*/2, // src0
        GIR_AddImm8, /*InsnID*/0, /*Imm*/0,
        GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/1, /*OpIdx*/1, // src1
        GIR_AddImm8, /*InsnID*/0, /*Imm*/0,
        GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/2, /*OpIdx*/1, // src2
        GIR_AddImm8, /*InsnID*/0, /*Imm*/0,
        GIR_AddImm8, /*InsnID*/0, /*Imm*/0,
        GIR_ConstrainSelectedInstOperands, /*InsnID*/0,
        GIR_EraseFromParent, /*InsnID*/0,
        // GIR_Coverage, 10790,
        GIR_Done,
      // Label 5356: @396087
      GIM_Try, /*On fail goto*//*Label 5357*/ GIMT_Encode4(396191), // Rule ID 10791 //
        GIM_CheckFeatures, GIMT_Encode2(GIFBS_isGFX9Plus),
        GIM_RecordInsn, /*DefineMI*/1, /*MI*/0, /*OpIdx*/1, // MIs[1]
        GIM_CheckOpcode, /*MI*/1, GIMT_Encode2(TargetOpcode::G_UMAX),
        GIM_CheckType, /*MI*/1, /*Op*/1, /*Type*/GILLT_s16,
        GIM_CheckType, /*MI*/1, /*Op*/2, /*Type*/GILLT_s16,
        GIM_RecordInsn, /*DefineMI*/2, /*MI*/0, /*OpIdx*/2, // MIs[2]
        GIM_CheckOpcode, /*MI*/2, GIMT_Encode2(TargetOpcode::G_UMAX),
        GIM_CheckType, /*MI*/2, /*Op*/1, /*Type*/GILLT_s16,
        GIM_CheckType, /*MI*/2, /*Op*/2, /*Type*/GILLT_s16,
        GIM_RecordInsn, /*DefineMI*/3, /*MI*/2, /*OpIdx*/2, // MIs[3]
        GIM_CheckOpcode, /*MI*/3, GIMT_Encode2(TargetOpcode::G_UMIN),
        // MIs[3] src1
        GIM_CheckIsSameOperand, /*MI*/3, /*OpIdx*/1, /*OtherMI*/1, /*OtherOpIdx*/1,
        // MIs[3] src0
        GIM_CheckIsSameOperand, /*MI*/3, /*OpIdx*/2, /*OtherMI*/1, /*OtherOpIdx*/2,
        GIM_CheckIsSafeToFold, /*InsnID*/1,
        GIM_CheckIsSafeToFold, /*InsnID*/2,
        GIM_CheckIsSafeToFold, /*InsnID*/3,
        // (umin:{ *:[i16] } (umax:{ *:[i16] } i16:{ *:[i16] }:$src1, i16:{ *:[i16] }:$src0), (umax:{ *:[i16] } i16:{ *:[i16] }:$src2, (umin:{ *:[i16] } i16:{ *:[i16] }:$src1, i16:{ *:[i16] }:$src0)))  =>  (V_MED3_U16_e64:{ *:[i16] } 0:{ *:[i32] }, VSrc_b16:{ *:[i16] }:$src0, 0:{ *:[i32] }, VSrc_b16:{ *:[i16] }:$src1, 0:{ *:[i32] }, VSrc_b16:{ *:[i16] }:$src2, 0:{ *:[i1] })
        GIR_BuildMI, /*InsnID*/0, /*Opcode*/GIMT_Encode2(AMDGPU::V_MED3_U16_e64),
        GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/0, // DstI[vdst]
        GIR_AddImm8, /*InsnID*/0, /*Imm*/0,
        GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/1, /*OpIdx*/2, // src0
        GIR_AddImm8, /*InsnID*/0, /*Imm*/0,
        GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/1, /*OpIdx*/1, // src1
        GIR_AddImm8, /*InsnID*/0, /*Imm*/0,
        GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/2, /*OpIdx*/1, // src2
        GIR_AddImm8, /*InsnID*/0, /*Imm*/0,
        GIR_AddImm8, /*InsnID*/0, /*Imm*/0,
        GIR_ConstrainSelectedInstOperands, /*InsnID*/0,
        GIR_EraseFromParent, /*InsnID*/0,
        // GIR_Coverage, 10791,
        GIR_Done,
      // Label 5357: @396191
      GIM_Try, /*On fail goto*//*Label 5358*/ GIMT_Encode4(396211), // Rule ID 829 //
        GIM_CheckFeatures, GIMT_Encode2(GIFBS_Has16BitInsts_NotHasTrue16BitInsts),
        // (umin:{ *:[i16] } i16:{ *:[i16] }:$src0, i16:{ *:[i16] }:$src1)  =>  (V_MIN_U16_e64:{ *:[i16] } i16:{ *:[i16] }:$src0, i16:{ *:[i16] }:$src1)
        GIR_MutateOpcode, /*InsnID*/0, /*RecycleInsnID*/0, /*Opcode*/GIMT_Encode2(AMDGPU::V_MIN_U16_e64),
        GIR_AddImplicitUse, /*InsnID*/0, GIMT_Encode2(AMDGPU::EXEC),
        GIR_ConstrainSelectedInstOperands, /*InsnID*/0,
        // GIR_Coverage, 829,
        GIR_Done,
      // Label 5358: @396211
      GIM_Try, /*On fail goto*//*Label 5359*/ GIMT_Encode4(396231), // Rule ID 830 //
        GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasTrue16BitInsts),
        // (umin:{ *:[i16] } i16:{ *:[i16] }:$src0, i16:{ *:[i16] }:$src1)  =>  (V_MIN_U16_t16_e64:{ *:[i16] } i16:{ *:[i16] }:$src0, i16:{ *:[i16] }:$src1)
        GIR_MutateOpcode, /*InsnID*/0, /*RecycleInsnID*/0, /*Opcode*/GIMT_Encode2(AMDGPU::V_MIN_U16_t16_e64),
        GIR_AddImplicitUse, /*InsnID*/0, GIMT_Encode2(AMDGPU::EXEC),
        GIR_ConstrainSelectedInstOperands, /*InsnID*/0,
        // GIR_Coverage, 830,
        GIR_Done,
      // Label 5359: @396231
      GIM_Reject,
    // Label 5341: @396232
    GIM_Reject,
    // Label 5338: @396233
    GIM_Try, /*On fail goto*//*Label 5360*/ GIMT_Encode4(397881),
      GIM_CheckType, /*MI*/0, /*Op*/1, /*Type*/GILLT_s32,
      GIM_CheckType, /*MI*/0, /*Op*/2, /*Type*/GILLT_s32,
      GIM_Try, /*On fail goto*//*Label 5361*/ GIMT_Encode4(396337), // Rule ID 9977 //
        GIM_CheckRegBankForClass, /*MI*/0, /*Op*/0, /*RC*/GIMT_Encode2(AMDGPU::VGPR_32RegClassID),
        GIM_RecordInsn, /*DefineMI*/1, /*MI*/0, /*OpIdx*/1, // MIs[1]
        GIM_CheckOpcode, /*MI*/1, GIMT_Encode2(TargetOpcode::G_UMAX),
        GIM_CheckType, /*MI*/1, /*Op*/1, /*Type*/GILLT_s32,
        GIM_CheckType, /*MI*/1, /*Op*/2, /*Type*/GILLT_s32,
        GIM_RecordInsn, /*DefineMI*/2, /*MI*/1, /*OpIdx*/1, // MIs[2]
        GIM_CheckOpcode, /*MI*/2, GIMT_Encode2(TargetOpcode::G_UMIN),
        GIM_CheckType, /*MI*/2, /*Op*/1, /*Type*/GILLT_s32,
        GIM_CheckType, /*MI*/2, /*Op*/2, /*Type*/GILLT_s32,
        GIM_RecordInsn, /*DefineMI*/3, /*MI*/0, /*OpIdx*/2, // MIs[3]
        GIM_CheckOpcode, /*MI*/3, GIMT_Encode2(TargetOpcode::G_UMAX),
        // MIs[3] src0
        GIM_CheckIsSameOperand, /*MI*/3, /*OpIdx*/1, /*OtherMI*/2, /*OtherOpIdx*/1,
        // MIs[3] src1
        GIM_CheckIsSameOperand, /*MI*/3, /*OpIdx*/2, /*OtherMI*/2, /*OtherOpIdx*/2,
        GIM_CheckIsSafeToFold, /*InsnID*/1,
        GIM_CheckIsSafeToFold, /*InsnID*/2,
        GIM_CheckIsSafeToFold, /*InsnID*/3,
        // (umin:{ *:[i32] } (umax:{ *:[i32] } (umin:{ *:[i32] } i32:{ *:[i32] }:$src0, i32:{ *:[i32] }:$src1), i32:{ *:[i32] }:$src2), (umax:{ *:[i32] } i32:{ *:[i32] }:$src0, i32:{ *:[i32] }:$src1))  =>  (V_MED3_U32_e64:{ *:[i32] } VSrc_b32:{ *:[i32] }:$src0, VSrc_b32:{ *:[i32] }:$src1, VSrc_b32:{ *:[i32] }:$src2)
        GIR_BuildMI, /*InsnID*/0, /*Opcode*/GIMT_Encode2(AMDGPU::V_MED3_U32_e64),
        GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/0, // DstI[vdst]
        GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/2, /*OpIdx*/1, // src0
        GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/2, /*OpIdx*/2, // src1
        GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/1, /*OpIdx*/2, // src2
        GIR_ConstrainSelectedInstOperands, /*InsnID*/0,
        GIR_EraseFromParent, /*InsnID*/0,
        // GIR_Coverage, 9977,
        GIR_Done,
      // Label 5361: @396337
      GIM_Try, /*On fail goto*//*Label 5362*/ GIMT_Encode4(396428), // Rule ID 9978 //
        GIM_CheckRegBankForClass, /*MI*/0, /*Op*/0, /*RC*/GIMT_Encode2(AMDGPU::VGPR_32RegClassID),
        GIM_RecordInsn, /*DefineMI*/1, /*MI*/0, /*OpIdx*/1, // MIs[1]
        GIM_CheckOpcode, /*MI*/1, GIMT_Encode2(TargetOpcode::G_UMAX),
        GIM_CheckType, /*MI*/1, /*Op*/1, /*Type*/GILLT_s32,
        GIM_CheckType, /*MI*/1, /*Op*/2, /*Type*/GILLT_s32,
        GIM_RecordInsn, /*DefineMI*/2, /*MI*/1, /*OpIdx*/1, // MIs[2]
        GIM_CheckOpcode, /*MI*/2, GIMT_Encode2(TargetOpcode::G_UMIN),
        GIM_CheckType, /*MI*/2, /*Op*/1, /*Type*/GILLT_s32,
        GIM_CheckType, /*MI*/2, /*Op*/2, /*Type*/GILLT_s32,
        GIM_RecordInsn, /*DefineMI*/3, /*MI*/0, /*OpIdx*/2, // MIs[3]
        GIM_CheckOpcode, /*MI*/3, GIMT_Encode2(TargetOpcode::G_UMAX),
        // MIs[3] src1
        GIM_CheckIsSameOperand, /*MI*/3, /*OpIdx*/1, /*OtherMI*/2, /*OtherOpIdx*/2,
        // MIs[3] src0
        GIM_CheckIsSameOperand, /*MI*/3, /*OpIdx*/2, /*OtherMI*/2, /*OtherOpIdx*/1,
        GIM_CheckIsSafeToFold, /*InsnID*/1,
        GIM_CheckIsSafeToFold, /*InsnID*/2,
        GIM_CheckIsSafeToFold, /*InsnID*/3,
        // (umin:{ *:[i32] } (umax:{ *:[i32] } (umin:{ *:[i32] } i32:{ *:[i32] }:$src0, i32:{ *:[i32] }:$src1), i32:{ *:[i32] }:$src2), (umax:{ *:[i32] } i32:{ *:[i32] }:$src1, i32:{ *:[i32] }:$src0))  =>  (V_MED3_U32_e64:{ *:[i32] } VSrc_b32:{ *:[i32] }:$src0, VSrc_b32:{ *:[i32] }:$src1, VSrc_b32:{ *:[i32] }:$src2)
        GIR_BuildMI, /*InsnID*/0, /*Opcode*/GIMT_Encode2(AMDGPU::V_MED3_U32_e64),
        GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/0, // DstI[vdst]
        GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/2, /*OpIdx*/1, // src0
        GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/2, /*OpIdx*/2, // src1
        GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/1, /*OpIdx*/2, // src2
        GIR_ConstrainSelectedInstOperands, /*InsnID*/0,
        GIR_EraseFromParent, /*InsnID*/0,
        // GIR_Coverage, 9978,
        GIR_Done,
      // Label 5362: @396428
      GIM_Try, /*On fail goto*//*Label 5363*/ GIMT_Encode4(396519), // Rule ID 9979 //
        GIM_CheckRegBankForClass, /*MI*/0, /*Op*/0, /*RC*/GIMT_Encode2(AMDGPU::VGPR_32RegClassID),
        GIM_RecordInsn, /*DefineMI*/1, /*MI*/0, /*OpIdx*/1, // MIs[1]
        GIM_CheckOpcode, /*MI*/1, GIMT_Encode2(TargetOpcode::G_UMAX),
        GIM_CheckType, /*MI*/1, /*Op*/1, /*Type*/GILLT_s32,
        GIM_CheckType, /*MI*/1, /*Op*/2, /*Type*/GILLT_s32,
        GIM_RecordInsn, /*DefineMI*/2, /*MI*/1, /*OpIdx*/1, // MIs[2]
        GIM_CheckOpcode, /*MI*/2, GIMT_Encode2(TargetOpcode::G_UMIN),
        GIM_CheckType, /*MI*/2, /*Op*/1, /*Type*/GILLT_s32,
        GIM_CheckType, /*MI*/2, /*Op*/2, /*Type*/GILLT_s32,
        GIM_RecordInsn, /*DefineMI*/3, /*MI*/0, /*OpIdx*/2, // MIs[3]
        GIM_CheckOpcode, /*MI*/3, GIMT_Encode2(TargetOpcode::G_UMAX),
        // MIs[3] src0
        GIM_CheckIsSameOperand, /*MI*/3, /*OpIdx*/1, /*OtherMI*/2, /*OtherOpIdx*/2,
        // MIs[3] src1
        GIM_CheckIsSameOperand, /*MI*/3, /*OpIdx*/2, /*OtherMI*/2, /*OtherOpIdx*/1,
        GIM_CheckIsSafeToFold, /*InsnID*/1,
        GIM_CheckIsSafeToFold, /*InsnID*/2,
        GIM_CheckIsSafeToFold, /*InsnID*/3,
        // (umin:{ *:[i32] } (umax:{ *:[i32] } (umin:{ *:[i32] } i32:{ *:[i32] }:$src1, i32:{ *:[i32] }:$src0), i32:{ *:[i32] }:$src2), (umax:{ *:[i32] } i32:{ *:[i32] }:$src0, i32:{ *:[i32] }:$src1))  =>  (V_MED3_U32_e64:{ *:[i32] } VSrc_b32:{ *:[i32] }:$src0, VSrc_b32:{ *:[i32] }:$src1, VSrc_b32:{ *:[i32] }:$src2)
        GIR_BuildMI, /*InsnID*/0, /*Opcode*/GIMT_Encode2(AMDGPU::V_MED3_U32_e64),
        GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/0, // DstI[vdst]
        GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/2, /*OpIdx*/2, // src0
        GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/2, /*OpIdx*/1, // src1
        GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/1, /*OpIdx*/2, // src2
        GIR_ConstrainSelectedInstOperands, /*InsnID*/0,
        GIR_EraseFromParent, /*InsnID*/0,
        // GIR_Coverage, 9979,
        GIR_Done,
      // Label 5363: @396519
      GIM_Try, /*On fail goto*//*Label 5364*/ GIMT_Encode4(396610), // Rule ID 9980 //
        GIM_CheckRegBankForClass, /*MI*/0, /*Op*/0, /*RC*/GIMT_Encode2(AMDGPU::VGPR_32RegClassID),
        GIM_RecordInsn, /*DefineMI*/1, /*MI*/0, /*OpIdx*/1, // MIs[1]
        GIM_CheckOpcode, /*MI*/1, GIMT_Encode2(TargetOpcode::G_UMAX),
        GIM_CheckType, /*MI*/1, /*Op*/1, /*Type*/GILLT_s32,
        GIM_CheckType, /*MI*/1, /*Op*/2, /*Type*/GILLT_s32,
        GIM_RecordInsn, /*DefineMI*/2, /*MI*/1, /*OpIdx*/1, // MIs[2]
        GIM_CheckOpcode, /*MI*/2, GIMT_Encode2(TargetOpcode::G_UMIN),
        GIM_CheckType, /*MI*/2, /*Op*/1, /*Type*/GILLT_s32,
        GIM_CheckType, /*MI*/2, /*Op*/2, /*Type*/GILLT_s32,
        GIM_RecordInsn, /*DefineMI*/3, /*MI*/0, /*OpIdx*/2, // MIs[3]
        GIM_CheckOpcode, /*MI*/3, GIMT_Encode2(TargetOpcode::G_UMAX),
        // MIs[3] src1
        GIM_CheckIsSameOperand, /*MI*/3, /*OpIdx*/1, /*OtherMI*/2, /*OtherOpIdx*/1,
        // MIs[3] src0
        GIM_CheckIsSameOperand, /*MI*/3, /*OpIdx*/2, /*OtherMI*/2, /*OtherOpIdx*/2,
        GIM_CheckIsSafeToFold, /*InsnID*/1,
        GIM_CheckIsSafeToFold, /*InsnID*/2,
        GIM_CheckIsSafeToFold, /*InsnID*/3,
        // (umin:{ *:[i32] } (umax:{ *:[i32] } (umin:{ *:[i32] } i32:{ *:[i32] }:$src1, i32:{ *:[i32] }:$src0), i32:{ *:[i32] }:$src2), (umax:{ *:[i32] } i32:{ *:[i32] }:$src1, i32:{ *:[i32] }:$src0))  =>  (V_MED3_U32_e64:{ *:[i32] } VSrc_b32:{ *:[i32] }:$src0, VSrc_b32:{ *:[i32] }:$src1, VSrc_b32:{ *:[i32] }:$src2)
        GIR_BuildMI, /*InsnID*/0, /*Opcode*/GIMT_Encode2(AMDGPU::V_MED3_U32_e64),
        GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/0, // DstI[vdst]
        GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/2, /*OpIdx*/2, // src0
        GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/2, /*OpIdx*/1, // src1
        GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/1, /*OpIdx*/2, // src2
        GIR_ConstrainSelectedInstOperands, /*InsnID*/0,
        GIR_EraseFromParent, /*InsnID*/0,
        // GIR_Coverage, 9980,
        GIR_Done,
      // Label 5364: @396610
      GIM_Try, /*On fail goto*//*Label 5365*/ GIMT_Encode4(396701), // Rule ID 9981 //
        GIM_CheckRegBankForClass, /*MI*/0, /*Op*/0, /*RC*/GIMT_Encode2(AMDGPU::VGPR_32RegClassID),
        GIM_RecordInsn, /*DefineMI*/1, /*MI*/0, /*OpIdx*/1, // MIs[1]
        GIM_CheckOpcode, /*MI*/1, GIMT_Encode2(TargetOpcode::G_UMAX),
        GIM_CheckType, /*MI*/1, /*Op*/1, /*Type*/GILLT_s32,
        GIM_CheckType, /*MI*/1, /*Op*/2, /*Type*/GILLT_s32,
        GIM_RecordInsn, /*DefineMI*/2, /*MI*/1, /*OpIdx*/2, // MIs[2]
        GIM_CheckOpcode, /*MI*/2, GIMT_Encode2(TargetOpcode::G_UMIN),
        GIM_CheckType, /*MI*/2, /*Op*/1, /*Type*/GILLT_s32,
        GIM_CheckType, /*MI*/2, /*Op*/2, /*Type*/GILLT_s32,
        GIM_RecordInsn, /*DefineMI*/3, /*MI*/0, /*OpIdx*/2, // MIs[3]
        GIM_CheckOpcode, /*MI*/3, GIMT_Encode2(TargetOpcode::G_UMAX),
        // MIs[3] src0
        GIM_CheckIsSameOperand, /*MI*/3, /*OpIdx*/1, /*OtherMI*/2, /*OtherOpIdx*/1,
        // MIs[3] src1
        GIM_CheckIsSameOperand, /*MI*/3, /*OpIdx*/2, /*OtherMI*/2, /*OtherOpIdx*/2,
        GIM_CheckIsSafeToFold, /*InsnID*/1,
        GIM_CheckIsSafeToFold, /*InsnID*/2,
        GIM_CheckIsSafeToFold, /*InsnID*/3,
        // (umin:{ *:[i32] } (umax:{ *:[i32] } i32:{ *:[i32] }:$src2, (umin:{ *:[i32] } i32:{ *:[i32] }:$src0, i32:{ *:[i32] }:$src1)), (umax:{ *:[i32] } i32:{ *:[i32] }:$src0, i32:{ *:[i32] }:$src1))  =>  (V_MED3_U32_e64:{ *:[i32] } VSrc_b32:{ *:[i32] }:$src0, VSrc_b32:{ *:[i32] }:$src1, VSrc_b32:{ *:[i32] }:$src2)
        GIR_BuildMI, /*InsnID*/0, /*Opcode*/GIMT_Encode2(AMDGPU::V_MED3_U32_e64),
        GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/0, // DstI[vdst]
        GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/2, /*OpIdx*/1, // src0
        GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/2, /*OpIdx*/2, // src1
        GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/1, /*OpIdx*/1, // src2
        GIR_ConstrainSelectedInstOperands, /*InsnID*/0,
        GIR_EraseFromParent, /*InsnID*/0,
        // GIR_Coverage, 9981,
        GIR_Done,
      // Label 5365: @396701
      GIM_Try, /*On fail goto*//*Label 5366*/ GIMT_Encode4(396792), // Rule ID 9982 //
        GIM_CheckRegBankForClass, /*MI*/0, /*Op*/0, /*RC*/GIMT_Encode2(AMDGPU::VGPR_32RegClassID),
        GIM_RecordInsn, /*DefineMI*/1, /*MI*/0, /*OpIdx*/1, // MIs[1]
        GIM_CheckOpcode, /*MI*/1, GIMT_Encode2(TargetOpcode::G_UMAX),
        GIM_CheckType, /*MI*/1, /*Op*/1, /*Type*/GILLT_s32,
        GIM_CheckType, /*MI*/1, /*Op*/2, /*Type*/GILLT_s32,
        GIM_RecordInsn, /*DefineMI*/2, /*MI*/1, /*OpIdx*/2, // MIs[2]
        GIM_CheckOpcode, /*MI*/2, GIMT_Encode2(TargetOpcode::G_UMIN),
        GIM_CheckType, /*MI*/2, /*Op*/1, /*Type*/GILLT_s32,
        GIM_CheckType, /*MI*/2, /*Op*/2, /*Type*/GILLT_s32,
        GIM_RecordInsn, /*DefineMI*/3, /*MI*/0, /*OpIdx*/2, // MIs[3]
        GIM_CheckOpcode, /*MI*/3, GIMT_Encode2(TargetOpcode::G_UMAX),
        // MIs[3] src1
        GIM_CheckIsSameOperand, /*MI*/3, /*OpIdx*/1, /*OtherMI*/2, /*OtherOpIdx*/2,
        // MIs[3] src0
        GIM_CheckIsSameOperand, /*MI*/3, /*OpIdx*/2, /*OtherMI*/2, /*OtherOpIdx*/1,
        GIM_CheckIsSafeToFold, /*InsnID*/1,
        GIM_CheckIsSafeToFold, /*InsnID*/2,
        GIM_CheckIsSafeToFold, /*InsnID*/3,
        // (umin:{ *:[i32] } (umax:{ *:[i32] } i32:{ *:[i32] }:$src2, (umin:{ *:[i32] } i32:{ *:[i32] }:$src0, i32:{ *:[i32] }:$src1)), (umax:{ *:[i32] } i32:{ *:[i32] }:$src1, i32:{ *:[i32] }:$src0))  =>  (V_MED3_U32_e64:{ *:[i32] } VSrc_b32:{ *:[i32] }:$src0, VSrc_b32:{ *:[i32] }:$src1, VSrc_b32:{ *:[i32] }:$src2)
        GIR_BuildMI, /*InsnID*/0, /*Opcode*/GIMT_Encode2(AMDGPU::V_MED3_U32_e64),
        GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/0, // DstI[vdst]
        GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/2, /*OpIdx*/1, // src0
        GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/2, /*OpIdx*/2, // src1
        GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/1, /*OpIdx*/1, // src2
        GIR_ConstrainSelectedInstOperands, /*InsnID*/0,
        GIR_EraseFromParent, /*InsnID*/0,
        // GIR_Coverage, 9982,
        GIR_Done,
      // Label 5366: @396792
      GIM_Try, /*On fail goto*//*Label 5367*/ GIMT_Encode4(396883), // Rule ID 9983 //
        GIM_CheckRegBankForClass, /*MI*/0, /*Op*/0, /*RC*/GIMT_Encode2(AMDGPU::VGPR_32RegClassID),
        GIM_RecordInsn, /*DefineMI*/1, /*MI*/0, /*OpIdx*/1, // MIs[1]
        GIM_CheckOpcode, /*MI*/1, GIMT_Encode2(TargetOpcode::G_UMAX),
        GIM_CheckType, /*MI*/1, /*Op*/1, /*Type*/GILLT_s32,
        GIM_CheckType, /*MI*/1, /*Op*/2, /*Type*/GILLT_s32,
        GIM_RecordInsn, /*DefineMI*/2, /*MI*/1, /*OpIdx*/2, // MIs[2]
        GIM_CheckOpcode, /*MI*/2, GIMT_Encode2(TargetOpcode::G_UMIN),
        GIM_CheckType, /*MI*/2, /*Op*/1, /*Type*/GILLT_s32,
        GIM_CheckType, /*MI*/2, /*Op*/2, /*Type*/GILLT_s32,
        GIM_RecordInsn, /*DefineMI*/3, /*MI*/0, /*OpIdx*/2, // MIs[3]
        GIM_CheckOpcode, /*MI*/3, GIMT_Encode2(TargetOpcode::G_UMAX),
        // MIs[3] src0
        GIM_CheckIsSameOperand, /*MI*/3, /*OpIdx*/1, /*OtherMI*/2, /*OtherOpIdx*/2,
        // MIs[3] src1
        GIM_CheckIsSameOperand, /*MI*/3, /*OpIdx*/2, /*OtherMI*/2, /*OtherOpIdx*/1,
        GIM_CheckIsSafeToFold, /*InsnID*/1,
        GIM_CheckIsSafeToFold, /*InsnID*/2,
        GIM_CheckIsSafeToFold, /*InsnID*/3,
        // (umin:{ *:[i32] } (umax:{ *:[i32] } i32:{ *:[i32] }:$src2, (umin:{ *:[i32] } i32:{ *:[i32] }:$src1, i32:{ *:[i32] }:$src0)), (umax:{ *:[i32] } i32:{ *:[i32] }:$src0, i32:{ *:[i32] }:$src1))  =>  (V_MED3_U32_e64:{ *:[i32] } VSrc_b32:{ *:[i32] }:$src0, VSrc_b32:{ *:[i32] }:$src1, VSrc_b32:{ *:[i32] }:$src2)
        GIR_BuildMI, /*InsnID*/0, /*Opcode*/GIMT_Encode2(AMDGPU::V_MED3_U32_e64),
        GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/0, // DstI[vdst]
        GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/2, /*OpIdx*/2, // src0
        GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/2, /*OpIdx*/1, // src1
        GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/1, /*OpIdx*/1, // src2
        GIR_ConstrainSelectedInstOperands, /*InsnID*/0,
        GIR_EraseFromParent, /*InsnID*/0,
        // GIR_Coverage, 9983,
        GIR_Done,
      // Label 5367: @396883
      GIM_Try, /*On fail goto*//*Label 5368*/ GIMT_Encode4(396974), // Rule ID 9984 //
        GIM_CheckRegBankForClass, /*MI*/0, /*Op*/0, /*RC*/GIMT_Encode2(AMDGPU::VGPR_32RegClassID),
        GIM_RecordInsn, /*DefineMI*/1, /*MI*/0, /*OpIdx*/1, // MIs[1]
        GIM_CheckOpcode, /*MI*/1, GIMT_Encode2(TargetOpcode::G_UMAX),
        GIM_CheckType, /*MI*/1, /*Op*/1, /*Type*/GILLT_s32,
        GIM_CheckType, /*MI*/1, /*Op*/2, /*Type*/GILLT_s32,
        GIM_RecordInsn, /*DefineMI*/2, /*MI*/1, /*OpIdx*/2, // MIs[2]
        GIM_CheckOpcode, /*MI*/2, GIMT_Encode2(TargetOpcode::G_UMIN),
        GIM_CheckType, /*MI*/2, /*Op*/1, /*Type*/GILLT_s32,
        GIM_CheckType, /*MI*/2, /*Op*/2, /*Type*/GILLT_s32,
        GIM_RecordInsn, /*DefineMI*/3, /*MI*/0, /*OpIdx*/2, // MIs[3]
        GIM_CheckOpcode, /*MI*/3, GIMT_Encode2(TargetOpcode::G_UMAX),
        // MIs[3] src1
        GIM_CheckIsSameOperand, /*MI*/3, /*OpIdx*/1, /*OtherMI*/2, /*OtherOpIdx*/1,
        // MIs[3] src0
        GIM_CheckIsSameOperand, /*MI*/3, /*OpIdx*/2, /*OtherMI*/2, /*OtherOpIdx*/2,
        GIM_CheckIsSafeToFold, /*InsnID*/1,
        GIM_CheckIsSafeToFold, /*InsnID*/2,
        GIM_CheckIsSafeToFold, /*InsnID*/3,
        // (umin:{ *:[i32] } (umax:{ *:[i32] } i32:{ *:[i32] }:$src2, (umin:{ *:[i32] } i32:{ *:[i32] }:$src1, i32:{ *:[i32] }:$src0)), (umax:{ *:[i32] } i32:{ *:[i32] }:$src1, i32:{ *:[i32] }:$src0))  =>  (V_MED3_U32_e64:{ *:[i32] } VSrc_b32:{ *:[i32] }:$src0, VSrc_b32:{ *:[i32] }:$src1, VSrc_b32:{ *:[i32] }:$src2)
        GIR_BuildMI, /*InsnID*/0, /*Opcode*/GIMT_Encode2(AMDGPU::V_MED3_U32_e64),
        GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/0, // DstI[vdst]
        GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/2, /*OpIdx*/2, // src0
        GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/2, /*OpIdx*/1, // src1
        GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/1, /*OpIdx*/1, // src2
        GIR_ConstrainSelectedInstOperands, /*InsnID*/0,
        GIR_EraseFromParent, /*InsnID*/0,
        // GIR_Coverage, 9984,
        GIR_Done,
      // Label 5368: @396974
      GIM_Try, /*On fail goto*//*Label 5369*/ GIMT_Encode4(397065), // Rule ID 6480 //
        GIM_CheckRegBankForClass, /*MI*/0, /*Op*/0, /*RC*/GIMT_Encode2(AMDGPU::VGPR_32RegClassID),
        GIM_RecordInsn, /*DefineMI*/1, /*MI*/0, /*OpIdx*/1, // MIs[1]
        GIM_CheckOpcode, /*MI*/1, GIMT_Encode2(TargetOpcode::G_UMAX),
        GIM_CheckType, /*MI*/1, /*Op*/1, /*Type*/GILLT_s32,
        GIM_CheckType, /*MI*/1, /*Op*/2, /*Type*/GILLT_s32,
        GIM_RecordInsn, /*DefineMI*/2, /*MI*/0, /*OpIdx*/2, // MIs[2]
        GIM_CheckOpcode, /*MI*/2, GIMT_Encode2(TargetOpcode::G_UMAX),
        GIM_CheckType, /*MI*/2, /*Op*/1, /*Type*/GILLT_s32,
        GIM_CheckType, /*MI*/2, /*Op*/2, /*Type*/GILLT_s32,
        GIM_RecordInsn, /*DefineMI*/3, /*MI*/2, /*OpIdx*/1, // MIs[3]
        GIM_CheckOpcode, /*MI*/3, GIMT_Encode2(TargetOpcode::G_UMIN),
        // MIs[3] src0
        GIM_CheckIsSameOperand, /*MI*/3, /*OpIdx*/1, /*OtherMI*/1, /*OtherOpIdx*/1,
        // MIs[3] src1
        GIM_CheckIsSameOperand, /*MI*/3, /*OpIdx*/2, /*OtherMI*/1, /*OtherOpIdx*/2,
        GIM_CheckIsSafeToFold, /*InsnID*/1,
        GIM_CheckIsSafeToFold, /*InsnID*/2,
        GIM_CheckIsSafeToFold, /*InsnID*/3,
        // (umin:{ *:[i32] } (umax:{ *:[i32] } i32:{ *:[i32] }:$src0, i32:{ *:[i32] }:$src1), (umax:{ *:[i32] } (umin:{ *:[i32] } i32:{ *:[i32] }:$src0, i32:{ *:[i32] }:$src1), i32:{ *:[i32] }:$src2))  =>  (V_MED3_U32_e64:{ *:[i32] } VSrc_b32:{ *:[i32] }:$src0, VSrc_b32:{ *:[i32] }:$src1, VSrc_b32:{ *:[i32] }:$src2)
        GIR_BuildMI, /*InsnID*/0, /*Opcode*/GIMT_Encode2(AMDGPU::V_MED3_U32_e64),
        GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/0, // DstI[vdst]
        GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/1, /*OpIdx*/1, // src0
        GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/1, /*OpIdx*/2, // src1
        GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/2, /*OpIdx*/2, // src2
        GIR_ConstrainSelectedInstOperands, /*InsnID*/0,
        GIR_EraseFromParent, /*InsnID*/0,
        // GIR_Coverage, 6480,
        GIR_Done,
      // Label 5369: @397065
      GIM_Try, /*On fail goto*//*Label 5370*/ GIMT_Encode4(397156), // Rule ID 9970 //
        GIM_CheckRegBankForClass, /*MI*/0, /*Op*/0, /*RC*/GIMT_Encode2(AMDGPU::VGPR_32RegClassID),
        GIM_RecordInsn, /*DefineMI*/1, /*MI*/0, /*OpIdx*/1, // MIs[1]
        GIM_CheckOpcode, /*MI*/1, GIMT_Encode2(TargetOpcode::G_UMAX),
        GIM_CheckType, /*MI*/1, /*Op*/1, /*Type*/GILLT_s32,
        GIM_CheckType, /*MI*/1, /*Op*/2, /*Type*/GILLT_s32,
        GIM_RecordInsn, /*DefineMI*/2, /*MI*/0, /*OpIdx*/2, // MIs[2]
        GIM_CheckOpcode, /*MI*/2, GIMT_Encode2(TargetOpcode::G_UMAX),
        GIM_CheckType, /*MI*/2, /*Op*/1, /*Type*/GILLT_s32,
        GIM_CheckType, /*MI*/2, /*Op*/2, /*Type*/GILLT_s32,
        GIM_RecordInsn, /*DefineMI*/3, /*MI*/2, /*OpIdx*/1, // MIs[3]
        GIM_CheckOpcode, /*MI*/3, GIMT_Encode2(TargetOpcode::G_UMIN),
        // MIs[3] src1
        GIM_CheckIsSameOperand, /*MI*/3, /*OpIdx*/1, /*OtherMI*/1, /*OtherOpIdx*/2,
        // MIs[3] src0
        GIM_CheckIsSameOperand, /*MI*/3, /*OpIdx*/2, /*OtherMI*/1, /*OtherOpIdx*/1,
        GIM_CheckIsSafeToFold, /*InsnID*/1,
        GIM_CheckIsSafeToFold, /*InsnID*/2,
        GIM_CheckIsSafeToFold, /*InsnID*/3,
        // (umin:{ *:[i32] } (umax:{ *:[i32] } i32:{ *:[i32] }:$src0, i32:{ *:[i32] }:$src1), (umax:{ *:[i32] } (umin:{ *:[i32] } i32:{ *:[i32] }:$src1, i32:{ *:[i32] }:$src0), i32:{ *:[i32] }:$src2))  =>  (V_MED3_U32_e64:{ *:[i32] } VSrc_b32:{ *:[i32] }:$src0, VSrc_b32:{ *:[i32] }:$src1, VSrc_b32:{ *:[i32] }:$src2)
        GIR_BuildMI, /*InsnID*/0, /*Opcode*/GIMT_Encode2(AMDGPU::V_MED3_U32_e64),
        GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/0, // DstI[vdst]
        GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/1, /*OpIdx*/1, // src0
        GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/1, /*OpIdx*/2, // src1
        GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/2, /*OpIdx*/2, // src2
        GIR_ConstrainSelectedInstOperands, /*InsnID*/0,
        GIR_EraseFromParent, /*InsnID*/0,
        // GIR_Coverage, 9970,
        GIR_Done,
      // Label 5370: @397156
      GIM_Try, /*On fail goto*//*Label 5371*/ GIMT_Encode4(397247), // Rule ID 9973 //
        GIM_CheckRegBankForClass, /*MI*/0, /*Op*/0, /*RC*/GIMT_Encode2(AMDGPU::VGPR_32RegClassID),
        GIM_RecordInsn, /*DefineMI*/1, /*MI*/0, /*OpIdx*/1, // MIs[1]
        GIM_CheckOpcode, /*MI*/1, GIMT_Encode2(TargetOpcode::G_UMAX),
        GIM_CheckType, /*MI*/1, /*Op*/1, /*Type*/GILLT_s32,
        GIM_CheckType, /*MI*/1, /*Op*/2, /*Type*/GILLT_s32,
        GIM_RecordInsn, /*DefineMI*/2, /*MI*/0, /*OpIdx*/2, // MIs[2]
        GIM_CheckOpcode, /*MI*/2, GIMT_Encode2(TargetOpcode::G_UMAX),
        GIM_CheckType, /*MI*/2, /*Op*/1, /*Type*/GILLT_s32,
        GIM_CheckType, /*MI*/2, /*Op*/2, /*Type*/GILLT_s32,
        GIM_RecordInsn, /*DefineMI*/3, /*MI*/2, /*OpIdx*/1, // MIs[3]
        GIM_CheckOpcode, /*MI*/3, GIMT_Encode2(TargetOpcode::G_UMIN),
        // MIs[3] src0
        GIM_CheckIsSameOperand, /*MI*/3, /*OpIdx*/1, /*OtherMI*/1, /*OtherOpIdx*/2,
        // MIs[3] src1
        GIM_CheckIsSameOperand, /*MI*/3, /*OpIdx*/2, /*OtherMI*/1, /*OtherOpIdx*/1,
        GIM_CheckIsSafeToFold, /*InsnID*/1,
        GIM_CheckIsSafeToFold, /*InsnID*/2,
        GIM_CheckIsSafeToFold, /*InsnID*/3,
        // (umin:{ *:[i32] } (umax:{ *:[i32] } i32:{ *:[i32] }:$src1, i32:{ *:[i32] }:$src0), (umax:{ *:[i32] } (umin:{ *:[i32] } i32:{ *:[i32] }:$src0, i32:{ *:[i32] }:$src1), i32:{ *:[i32] }:$src2))  =>  (V_MED3_U32_e64:{ *:[i32] } VSrc_b32:{ *:[i32] }:$src0, VSrc_b32:{ *:[i32] }:$src1, VSrc_b32:{ *:[i32] }:$src2)
        GIR_BuildMI, /*InsnID*/0, /*Opcode*/GIMT_Encode2(AMDGPU::V_MED3_U32_e64),
        GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/0, // DstI[vdst]
        GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/1, /*OpIdx*/2, // src0
        GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/1, /*OpIdx*/1, // src1
        GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/2, /*OpIdx*/2, // src2
        GIR_ConstrainSelectedInstOperands, /*InsnID*/0,
        GIR_EraseFromParent, /*InsnID*/0,
        // GIR_Coverage, 9973,
        GIR_Done,
      // Label 5371: @397247
      GIM_Try, /*On fail goto*//*Label 5372*/ GIMT_Encode4(397338), // Rule ID 9974 //
        GIM_CheckRegBankForClass, /*MI*/0, /*Op*/0, /*RC*/GIMT_Encode2(AMDGPU::VGPR_32RegClassID),
        GIM_RecordInsn, /*DefineMI*/1, /*MI*/0, /*OpIdx*/1, // MIs[1]
        GIM_CheckOpcode, /*MI*/1, GIMT_Encode2(TargetOpcode::G_UMAX),
        GIM_CheckType, /*MI*/1, /*Op*/1, /*Type*/GILLT_s32,
        GIM_CheckType, /*MI*/1, /*Op*/2, /*Type*/GILLT_s32,
        GIM_RecordInsn, /*DefineMI*/2, /*MI*/0, /*OpIdx*/2, // MIs[2]
        GIM_CheckOpcode, /*MI*/2, GIMT_Encode2(TargetOpcode::G_UMAX),
        GIM_CheckType, /*MI*/2, /*Op*/1, /*Type*/GILLT_s32,
        GIM_CheckType, /*MI*/2, /*Op*/2, /*Type*/GILLT_s32,
        GIM_RecordInsn, /*DefineMI*/3, /*MI*/2, /*OpIdx*/1, // MIs[3]
        GIM_CheckOpcode, /*MI*/3, GIMT_Encode2(TargetOpcode::G_UMIN),
        // MIs[3] src1
        GIM_CheckIsSameOperand, /*MI*/3, /*OpIdx*/1, /*OtherMI*/1, /*OtherOpIdx*/1,
        // MIs[3] src0
        GIM_CheckIsSameOperand, /*MI*/3, /*OpIdx*/2, /*OtherMI*/1, /*OtherOpIdx*/2,
        GIM_CheckIsSafeToFold, /*InsnID*/1,
        GIM_CheckIsSafeToFold, /*InsnID*/2,
        GIM_CheckIsSafeToFold, /*InsnID*/3,
        // (umin:{ *:[i32] } (umax:{ *:[i32] } i32:{ *:[i32] }:$src1, i32:{ *:[i32] }:$src0), (umax:{ *:[i32] } (umin:{ *:[i32] } i32:{ *:[i32] }:$src1, i32:{ *:[i32] }:$src0), i32:{ *:[i32] }:$src2))  =>  (V_MED3_U32_e64:{ *:[i32] } VSrc_b32:{ *:[i32] }:$src0, VSrc_b32:{ *:[i32] }:$src1, VSrc_b32:{ *:[i32] }:$src2)
        GIR_BuildMI, /*InsnID*/0, /*Opcode*/GIMT_Encode2(AMDGPU::V_MED3_U32_e64),
        GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/0, // DstI[vdst]
        GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/1, /*OpIdx*/2, // src0
        GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/1, /*OpIdx*/1, // src1
        GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/2, /*OpIdx*/2, // src2
        GIR_ConstrainSelectedInstOperands, /*InsnID*/0,
        GIR_EraseFromParent, /*InsnID*/0,
        // GIR_Coverage, 9974,
        GIR_Done,
      // Label 5372: @397338
      GIM_Try, /*On fail goto*//*Label 5373*/ GIMT_Encode4(397429), // Rule ID 9971 //
        GIM_CheckRegBankForClass, /*MI*/0, /*Op*/0, /*RC*/GIMT_Encode2(AMDGPU::VGPR_32RegClassID),
        GIM_RecordInsn, /*DefineMI*/1, /*MI*/0, /*OpIdx*/1, // MIs[1]
        GIM_CheckOpcode, /*MI*/1, GIMT_Encode2(TargetOpcode::G_UMAX),
        GIM_CheckType, /*MI*/1, /*Op*/1, /*Type*/GILLT_s32,
        GIM_CheckType, /*MI*/1, /*Op*/2, /*Type*/GILLT_s32,
        GIM_RecordInsn, /*DefineMI*/2, /*MI*/0, /*OpIdx*/2, // MIs[2]
        GIM_CheckOpcode, /*MI*/2, GIMT_Encode2(TargetOpcode::G_UMAX),
        GIM_CheckType, /*MI*/2, /*Op*/1, /*Type*/GILLT_s32,
        GIM_CheckType, /*MI*/2, /*Op*/2, /*Type*/GILLT_s32,
        GIM_RecordInsn, /*DefineMI*/3, /*MI*/2, /*OpIdx*/2, // MIs[3]
        GIM_CheckOpcode, /*MI*/3, GIMT_Encode2(TargetOpcode::G_UMIN),
        // MIs[3] src0
        GIM_CheckIsSameOperand, /*MI*/3, /*OpIdx*/1, /*OtherMI*/1, /*OtherOpIdx*/1,
        // MIs[3] src1
        GIM_CheckIsSameOperand, /*MI*/3, /*OpIdx*/2, /*OtherMI*/1, /*OtherOpIdx*/2,
        GIM_CheckIsSafeToFold, /*InsnID*/1,
        GIM_CheckIsSafeToFold, /*InsnID*/2,
        GIM_CheckIsSafeToFold, /*InsnID*/3,
        // (umin:{ *:[i32] } (umax:{ *:[i32] } i32:{ *:[i32] }:$src0, i32:{ *:[i32] }:$src1), (umax:{ *:[i32] } i32:{ *:[i32] }:$src2, (umin:{ *:[i32] } i32:{ *:[i32] }:$src0, i32:{ *:[i32] }:$src1)))  =>  (V_MED3_U32_e64:{ *:[i32] } VSrc_b32:{ *:[i32] }:$src0, VSrc_b32:{ *:[i32] }:$src1, VSrc_b32:{ *:[i32] }:$src2)
        GIR_BuildMI, /*InsnID*/0, /*Opcode*/GIMT_Encode2(AMDGPU::V_MED3_U32_e64),
        GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/0, // DstI[vdst]
        GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/1, /*OpIdx*/1, // src0
        GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/1, /*OpIdx*/2, // src1
        GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/2, /*OpIdx*/1, // src2
        GIR_ConstrainSelectedInstOperands, /*InsnID*/0,
        GIR_EraseFromParent, /*InsnID*/0,
        // GIR_Coverage, 9971,
        GIR_Done,
      // Label 5373: @397429
      GIM_Try, /*On fail goto*//*Label 5374*/ GIMT_Encode4(397520), // Rule ID 9972 //
        GIM_CheckRegBankForClass, /*MI*/0, /*Op*/0, /*RC*/GIMT_Encode2(AMDGPU::VGPR_32RegClassID),
        GIM_RecordInsn, /*DefineMI*/1, /*MI*/0, /*OpIdx*/1, // MIs[1]
        GIM_CheckOpcode, /*MI*/1, GIMT_Encode2(TargetOpcode::G_UMAX),
        GIM_CheckType, /*MI*/1, /*Op*/1, /*Type*/GILLT_s32,
        GIM_CheckType, /*MI*/1, /*Op*/2, /*Type*/GILLT_s32,
        GIM_RecordInsn, /*DefineMI*/2, /*MI*/0, /*OpIdx*/2, // MIs[2]
        GIM_CheckOpcode, /*MI*/2, GIMT_Encode2(TargetOpcode::G_UMAX),
        GIM_CheckType, /*MI*/2, /*Op*/1, /*Type*/GILLT_s32,
        GIM_CheckType, /*MI*/2, /*Op*/2, /*Type*/GILLT_s32,
        GIM_RecordInsn, /*DefineMI*/3, /*MI*/2, /*OpIdx*/2, // MIs[3]
        GIM_CheckOpcode, /*MI*/3, GIMT_Encode2(TargetOpcode::G_UMIN),
        // MIs[3] src1
        GIM_CheckIsSameOperand, /*MI*/3, /*OpIdx*/1, /*OtherMI*/1, /*OtherOpIdx*/2,
        // MIs[3] src0
        GIM_CheckIsSameOperand, /*MI*/3, /*OpIdx*/2, /*OtherMI*/1, /*OtherOpIdx*/1,
        GIM_CheckIsSafeToFold, /*InsnID*/1,
        GIM_CheckIsSafeToFold, /*InsnID*/2,
        GIM_CheckIsSafeToFold, /*InsnID*/3,
        // (umin:{ *:[i32] } (umax:{ *:[i32] } i32:{ *:[i32] }:$src0, i32:{ *:[i32] }:$src1), (umax:{ *:[i32] } i32:{ *:[i32] }:$src2, (umin:{ *:[i32] } i32:{ *:[i32] }:$src1, i32:{ *:[i32] }:$src0)))  =>  (V_MED3_U32_e64:{ *:[i32] } VSrc_b32:{ *:[i32] }:$src0, VSrc_b32:{ *:[i32] }:$src1, VSrc_b32:{ *:[i32] }:$src2)
        GIR_BuildMI, /*InsnID*/0, /*Opcode*/GIMT_Encode2(AMDGPU::V_MED3_U32_e64),
        GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/0, // DstI[vdst]
        GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/1, /*OpIdx*/1, // src0
        GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/1, /*OpIdx*/2, // src1
        GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/2, /*OpIdx*/1, // src2
        GIR_ConstrainSelectedInstOperands, /*InsnID*/0,
        GIR_EraseFromParent, /*InsnID*/0,
        // GIR_Coverage, 9972,
        GIR_Done,
      // Label 5374: @397520
      GIM_Try, /*On fail goto*//*Label 5375*/ GIMT_Encode4(397611), // Rule ID 9975 //
        GIM_CheckRegBankForClass, /*MI*/0, /*Op*/0, /*RC*/GIMT_Encode2(AMDGPU::VGPR_32RegClassID),
        GIM_RecordInsn, /*DefineMI*/1, /*MI*/0, /*OpIdx*/1, // MIs[1]
        GIM_CheckOpcode, /*MI*/1, GIMT_Encode2(TargetOpcode::G_UMAX),
        GIM_CheckType, /*MI*/1, /*Op*/1, /*Type*/GILLT_s32,
        GIM_CheckType, /*MI*/1, /*Op*/2, /*Type*/GILLT_s32,
        GIM_RecordInsn, /*DefineMI*/2, /*MI*/0, /*OpIdx*/2, // MIs[2]
        GIM_CheckOpcode, /*MI*/2, GIMT_Encode2(TargetOpcode::G_UMAX),
        GIM_CheckType, /*MI*/2, /*Op*/1, /*Type*/GILLT_s32,
        GIM_CheckType, /*MI*/2, /*Op*/2, /*Type*/GILLT_s32,
        GIM_RecordInsn, /*DefineMI*/3, /*MI*/2, /*OpIdx*/2, // MIs[3]
        GIM_CheckOpcode, /*MI*/3, GIMT_Encode2(TargetOpcode::G_UMIN),
        // MIs[3] src0
        GIM_CheckIsSameOperand, /*MI*/3, /*OpIdx*/1, /*OtherMI*/1, /*OtherOpIdx*/2,
        // MIs[3] src1
        GIM_CheckIsSameOperand, /*MI*/3, /*OpIdx*/2, /*OtherMI*/1, /*OtherOpIdx*/1,
        GIM_CheckIsSafeToFold, /*InsnID*/1,
        GIM_CheckIsSafeToFold, /*InsnID*/2,
        GIM_CheckIsSafeToFold, /*InsnID*/3,
        // (umin:{ *:[i32] } (umax:{ *:[i32] } i32:{ *:[i32] }:$src1, i32:{ *:[i32] }:$src0), (umax:{ *:[i32] } i32:{ *:[i32] }:$src2, (umin:{ *:[i32] } i32:{ *:[i32] }:$src0, i32:{ *:[i32] }:$src1)))  =>  (V_MED3_U32_e64:{ *:[i32] } VSrc_b32:{ *:[i32] }:$src0, VSrc_b32:{ *:[i32] }:$src1, VSrc_b32:{ *:[i32] }:$src2)
        GIR_BuildMI, /*InsnID*/0, /*Opcode*/GIMT_Encode2(AMDGPU::V_MED3_U32_e64),
        GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/0, // DstI[vdst]
        GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/1, /*OpIdx*/2, // src0
        GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/1, /*OpIdx*/1, // src1
        GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/2, /*OpIdx*/1, // src2
        GIR_ConstrainSelectedInstOperands, /*InsnID*/0,
        GIR_EraseFromParent, /*InsnID*/0,
        // GIR_Coverage, 9975,
        GIR_Done,
      // Label 5375: @397611
      GIM_Try, /*On fail goto*//*Label 5376*/ GIMT_Encode4(397702), // Rule ID 9976 //
        GIM_CheckRegBankForClass, /*MI*/0, /*Op*/0, /*RC*/GIMT_Encode2(AMDGPU::VGPR_32RegClassID),
        GIM_RecordInsn, /*DefineMI*/1, /*MI*/0, /*OpIdx*/1, // MIs[1]
        GIM_CheckOpcode, /*MI*/1, GIMT_Encode2(TargetOpcode::G_UMAX),
        GIM_CheckType, /*MI*/1, /*Op*/1, /*Type*/GILLT_s32,
        GIM_CheckType, /*MI*/1, /*Op*/2, /*Type*/GILLT_s32,
        GIM_RecordInsn, /*DefineMI*/2, /*MI*/0, /*OpIdx*/2, // MIs[2]
        GIM_CheckOpcode, /*MI*/2, GIMT_Encode2(TargetOpcode::G_UMAX),
        GIM_CheckType, /*MI*/2, /*Op*/1, /*Type*/GILLT_s32,
        GIM_CheckType, /*MI*/2, /*Op*/2, /*Type*/GILLT_s32,
        GIM_RecordInsn, /*DefineMI*/3, /*MI*/2, /*OpIdx*/2, // MIs[3]
        GIM_CheckOpcode, /*MI*/3, GIMT_Encode2(TargetOpcode::G_UMIN),
        // MIs[3] src1
        GIM_CheckIsSameOperand, /*MI*/3, /*OpIdx*/1, /*OtherMI*/1, /*OtherOpIdx*/1,
        // MIs[3] src0
        GIM_CheckIsSameOperand, /*MI*/3, /*OpIdx*/2, /*OtherMI*/1, /*OtherOpIdx*/2,
        GIM_CheckIsSafeToFold, /*InsnID*/1,
        GIM_CheckIsSafeToFold, /*InsnID*/2,
        GIM_CheckIsSafeToFold, /*InsnID*/3,
        // (umin:{ *:[i32] } (umax:{ *:[i32] } i32:{ *:[i32] }:$src1, i32:{ *:[i32] }:$src0), (umax:{ *:[i32] } i32:{ *:[i32] }:$src2, (umin:{ *:[i32] } i32:{ *:[i32] }:$src1, i32:{ *:[i32] }:$src0)))  =>  (V_MED3_U32_e64:{ *:[i32] } VSrc_b32:{ *:[i32] }:$src0, VSrc_b32:{ *:[i32] }:$src1, VSrc_b32:{ *:[i32] }:$src2)
        GIR_BuildMI, /*InsnID*/0, /*Opcode*/GIMT_Encode2(AMDGPU::V_MED3_U32_e64),
        GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/0, // DstI[vdst]
        GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/1, /*OpIdx*/2, // src0
        GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/1, /*OpIdx*/1, // src1
        GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/2, /*OpIdx*/1, // src2
        GIR_ConstrainSelectedInstOperands, /*InsnID*/0,
        GIR_EraseFromParent, /*InsnID*/0,
        // GIR_Coverage, 9976,
        GIR_Done,
      // Label 5376: @397702
      GIM_Try, /*On fail goto*//*Label 5377*/ GIMT_Encode4(397766), // Rule ID 6518 //
        GIM_CheckFeatures, GIMT_Encode2(GIFBS_isGFX11Plus),
        GIM_CheckRegBankForClass, /*MI*/0, /*Op*/0, /*RC*/GIMT_Encode2(AMDGPU::VGPR_32RegClassID),
        GIM_RecordInsn, /*DefineMI*/1, /*MI*/0, /*OpIdx*/1, // MIs[1]
        GIM_CheckOpcode, /*MI*/1, GIMT_Encode2(TargetOpcode::G_UMAX),
        GIM_CheckType, /*MI*/1, /*Op*/1, /*Type*/GILLT_s32,
        GIM_CheckType, /*MI*/1, /*Op*/2, /*Type*/GILLT_s32,
        GIM_CheckCxxInsnPredicate, /*MI*/1, /*FnId*/GIMT_Encode2(GICXXPred_MI_Predicate_umax_oneuse),
        GIM_CheckCxxInsnPredicate, /*MI*/0, /*FnId*/GIMT_Encode2(GICXXPred_MI_Predicate_anonymous_35368),
        GIM_CheckIsSafeToFold, /*InsnID*/1,
        // (umin:{ *:[i32] } (umax:{ *:[i32] } i32:{ *:[i32] }:$src0, i32:{ *:[i32] }:$src1)<<P:Predicate_umax_oneuse>>, i32:{ *:[i32] }:$src2)<<P:Predicate_anonymous_35368>>  =>  (V_MAXMIN_U32_e64:{ *:[i32] } VSrc_b32:{ *:[i32] }:$src0, VSrc_b32:{ *:[i32] }:$src1, VSrc_b32:{ *:[i32] }:$src2)
        GIR_BuildMI, /*InsnID*/0, /*Opcode*/GIMT_Encode2(AMDGPU::V_MAXMIN_U32_e64),
        GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/0, // DstI[vdst]
        GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/1, /*OpIdx*/1, // src0
        GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/1, /*OpIdx*/2, // src1
        GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/2, // src2
        GIR_ConstrainSelectedInstOperands, /*InsnID*/0,
        GIR_EraseFromParent, /*InsnID*/0,
        // GIR_Coverage, 6518,
        GIR_Done,
      // Label 5377: @397766
      GIM_Try, /*On fail goto*//*Label 5378*/ GIMT_Encode4(397830), // Rule ID 10512 //
        GIM_CheckFeatures, GIMT_Encode2(GIFBS_isGFX11Plus),
        GIM_CheckRegBankForClass, /*MI*/0, /*Op*/0, /*RC*/GIMT_Encode2(AMDGPU::VGPR_32RegClassID),
        GIM_RecordInsn, /*DefineMI*/1, /*MI*/0, /*OpIdx*/2, // MIs[1]
        GIM_CheckOpcode, /*MI*/1, GIMT_Encode2(TargetOpcode::G_UMAX),
        GIM_CheckType, /*MI*/1, /*Op*/1, /*Type*/GILLT_s32,
        GIM_CheckType, /*MI*/1, /*Op*/2, /*Type*/GILLT_s32,
        GIM_CheckCxxInsnPredicate, /*MI*/1, /*FnId*/GIMT_Encode2(GICXXPred_MI_Predicate_umax_oneuse),
        GIM_CheckCxxInsnPredicate, /*MI*/0, /*FnId*/GIMT_Encode2(GICXXPred_MI_Predicate_anonymous_35368),
        GIM_CheckIsSafeToFold, /*InsnID*/1,
        // (umin:{ *:[i32] } i32:{ *:[i32] }:$src2, (umax:{ *:[i32] } i32:{ *:[i32] }:$src0, i32:{ *:[i32] }:$src1)<<P:Predicate_umax_oneuse>>)<<P:Predicate_anonymous_35368>>  =>  (V_MAXMIN_U32_e64:{ *:[i32] } VSrc_b32:{ *:[i32] }:$src0, VSrc_b32:{ *:[i32] }:$src1, VSrc_b32:{ *:[i32] }:$src2)
        GIR_BuildMI, /*InsnID*/0, /*Opcode*/GIMT_Encode2(AMDGPU::V_MAXMIN_U32_e64),
        GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/0, // DstI[vdst]
        GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/1, /*OpIdx*/1, // src0
        GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/1, /*OpIdx*/2, // src1
        GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/1, // src2
        GIR_ConstrainSelectedInstOperands, /*InsnID*/0,
        GIR_EraseFromParent, /*InsnID*/0,
        // GIR_Coverage, 10512,
        GIR_Done,
      // Label 5378: @397830
      GIM_Try, /*On fail goto*//*Label 5379*/ GIMT_Encode4(397858), // Rule ID 50 //
        GIM_CheckRegBankForClass, /*MI*/0, /*Op*/0, /*RC*/GIMT_Encode2(AMDGPU::SReg_32RegClassID),
        GIM_CheckCxxInsnPredicate, /*MI*/0, /*FnId*/GIMT_Encode2(GICXXPred_MI_Predicate_anonymous_17608),
        // (umin:{ *:[i32] } i32:{ *:[i32] }:$src0, i32:{ *:[i32] }:$src1)<<P:Predicate_anonymous_17608>>  =>  (S_MIN_U32:{ *:[i32] }:{ *:[i1] } i32:{ *:[i32] }:$src0, i32:{ *:[i32] }:$src1)
        GIR_MutateOpcode, /*InsnID*/0, /*RecycleInsnID*/0, /*Opcode*/GIMT_Encode2(AMDGPU::S_MIN_U32),
        GIR_AddImplicitDef, /*InsnID*/0, GIMT_Encode2(AMDGPU::SCC), GIMT_Encode2(RegState::Dead),
        GIR_ConstrainSelectedInstOperands, /*InsnID*/0,
        // GIR_Coverage, 50,
        GIR_Done,
      // Label 5379: @397858
      GIM_Try, /*On fail goto*//*Label 5380*/ GIMT_Encode4(397880), // Rule ID 745 //
        GIM_CheckRegBankForClass, /*MI*/0, /*Op*/0, /*RC*/GIMT_Encode2(AMDGPU::VGPR_32RegClassID),
        // (umin:{ *:[i32] } i32:{ *:[i32] }:$src0, i32:{ *:[i32] }:$src1)  =>  (V_MIN_U32_e64:{ *:[i32] } i32:{ *:[i32] }:$src0, i32:{ *:[i32] }:$src1)
        GIR_MutateOpcode, /*InsnID*/0, /*RecycleInsnID*/0, /*Opcode*/GIMT_Encode2(AMDGPU::V_MIN_U32_e64),
        GIR_AddImplicitUse, /*InsnID*/0, GIMT_Encode2(AMDGPU::EXEC),
        GIR_ConstrainSelectedInstOperands, /*InsnID*/0,
        // GIR_Coverage, 745,
        GIR_Done,
      // Label 5380: @397880
      GIM_Reject,
    // Label 5360: @397881
    GIM_Reject,
    // Label 5339: @397882
    GIM_Try, /*On fail goto*//*Label 5381*/ GIMT_Encode4(397962), // Rule ID 971 //
      GIM_CheckType, /*MI*/0, /*Op*/1, /*Type*/GILLT_v2s16,
      GIM_CheckType, /*MI*/0, /*Op*/2, /*Type*/GILLT_v2s16,
      GIM_CheckRegBankForClass, /*MI*/0, /*Op*/0, /*RC*/GIMT_Encode2(AMDGPU::VGPR_32RegClassID),
      GIM_CheckComplexPattern, /*MI*/0, /*Op*/1, /*Renderer*/GIMT_Encode2(0), GIMT_Encode2(GICP_gi_vop3pmods),
      GIM_CheckComplexPattern, /*MI*/0, /*Op*/2, /*Renderer*/GIMT_Encode2(1), GIMT_Encode2(GICP_gi_vop3pmods),
      // (umin:{ *:[v2i16] } (VOP3PMods:{ *:[v2i16] } v2i16:{ *:[v2i16] }:$src0, i32:{ *:[i32] }:$src0_modifiers), (VOP3PMods:{ *:[v2i16] } v2i16:{ *:[v2i16] }:$src1, i32:{ *:[i32] }:$src1_modifiers))  =>  (V_PK_MIN_U16:{ *:[v2i16] } i32:{ *:[i32] }:$src0_modifiers, v2i16:{ *:[v2i16] }:$src0, i32:{ *:[i32] }:$src1_modifiers, v2i16:{ *:[v2i16] }:$src1)
      GIR_BuildMI, /*InsnID*/0, /*Opcode*/GIMT_Encode2(AMDGPU::V_PK_MIN_U16),
      GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/0, // DstI[vdst]
      GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/1, // src0_modifiers
      GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/0, // src0
      GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(1), /*SubOperand*/1, // src1_modifiers
      GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(1), /*SubOperand*/0, // src1
      GIR_AddImm8, /*InsnID*/0, /*Imm*/0,
      GIR_AddImm8, /*InsnID*/0, /*Imm*/0,
      GIR_AddImm8, /*InsnID*/0, /*Imm*/0,
      GIR_AddImm8, /*InsnID*/0, /*Imm*/0,
      GIR_AddImm8, /*InsnID*/0, /*Imm*/0,
      GIR_ConstrainSelectedInstOperands, /*InsnID*/0,
      GIR_EraseFromParent, /*InsnID*/0,
      // GIR_Coverage, 971,
      GIR_Done,
    // Label 5381: @397962
    GIM_Reject,
    // Label 5340: @397963
    GIM_Reject,
    // Label 87: @397964
    GIM_SwitchType, /*MI*/0, /*Op*/0, /*[*/GIMT_Encode2(8), GIMT_Encode2(12), /*)*//*default:*//*Label 5385*/ GIMT_Encode4(401445),
    /*GILLT_s16*//*Label 5382*/ GIMT_Encode4(397991),
    /*GILLT_s32*//*Label 5383*/ GIMT_Encode4(399715), GIMT_Encode4(0),
    /*GILLT_v2s16*//*Label 5384*/ GIMT_Encode4(401364),
    // Label 5382: @397991
    GIM_Try, /*On fail goto*//*Label 5386*/ GIMT_Encode4(399714),
      GIM_CheckType, /*MI*/0, /*Op*/1, /*Type*/GILLT_s16,
      GIM_CheckType, /*MI*/0, /*Op*/2, /*Type*/GILLT_s16,
      GIM_CheckRegBankForClass, /*MI*/0, /*Op*/0, /*RC*/GIMT_Encode2(AMDGPU::VGPR_32RegClassID),
      GIM_Try, /*On fail goto*//*Label 5387*/ GIMT_Encode4(398113), // Rule ID 10777 //
        GIM_CheckFeatures, GIMT_Encode2(GIFBS_isGFX9Plus),
        GIM_RecordInsn, /*DefineMI*/1, /*MI*/0, /*OpIdx*/1, // MIs[1]
        GIM_CheckOpcode, /*MI*/1, GIMT_Encode2(TargetOpcode::G_UMIN),
        GIM_CheckType, /*MI*/1, /*Op*/1, /*Type*/GILLT_s16,
        GIM_CheckType, /*MI*/1, /*Op*/2, /*Type*/GILLT_s16,
        GIM_RecordInsn, /*DefineMI*/2, /*MI*/1, /*OpIdx*/1, // MIs[2]
        GIM_CheckOpcode, /*MI*/2, GIMT_Encode2(TargetOpcode::G_UMAX),
        GIM_CheckType, /*MI*/2, /*Op*/1, /*Type*/GILLT_s16,
        GIM_CheckType, /*MI*/2, /*Op*/2, /*Type*/GILLT_s16,
        GIM_RecordInsn, /*DefineMI*/3, /*MI*/0, /*OpIdx*/2, // MIs[3]
        GIM_CheckOpcode, /*MI*/3, GIMT_Encode2(TargetOpcode::G_UMIN),
        // MIs[3] src0
        GIM_CheckIsSameOperand, /*MI*/3, /*OpIdx*/1, /*OtherMI*/2, /*OtherOpIdx*/1,
        // MIs[3] src1
        GIM_CheckIsSameOperand, /*MI*/3, /*OpIdx*/2, /*OtherMI*/2, /*OtherOpIdx*/2,
        GIM_CheckIsSafeToFold, /*InsnID*/1,
        GIM_CheckIsSafeToFold, /*InsnID*/2,
        GIM_CheckIsSafeToFold, /*InsnID*/3,
        // (umax:{ *:[i16] } (umin:{ *:[i16] } (umax:{ *:[i16] } i16:{ *:[i16] }:$src0, i16:{ *:[i16] }:$src1), i16:{ *:[i16] }:$src2), (umin:{ *:[i16] } i16:{ *:[i16] }:$src0, i16:{ *:[i16] }:$src1))  =>  (V_MED3_U16_e64:{ *:[i16] } 0:{ *:[i32] }, VSrc_b16:{ *:[i16] }:$src0, 0:{ *:[i32] }, VSrc_b16:{ *:[i16] }:$src1, 0:{ *:[i32] }, VSrc_b16:{ *:[i16] }:$src2, 0:{ *:[i1] })
        GIR_BuildMI, /*InsnID*/0, /*Opcode*/GIMT_Encode2(AMDGPU::V_MED3_U16_e64),
        GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/0, // DstI[vdst]
        GIR_AddImm8, /*InsnID*/0, /*Imm*/0,
        GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/2, /*OpIdx*/1, // src0
        GIR_AddImm8, /*InsnID*/0, /*Imm*/0,
        GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/2, /*OpIdx*/2, // src1
        GIR_AddImm8, /*InsnID*/0, /*Imm*/0,
        GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/1, /*OpIdx*/2, // src2
        GIR_AddImm8, /*InsnID*/0, /*Imm*/0,
        GIR_AddImm8, /*InsnID*/0, /*Imm*/0,
        GIR_ConstrainSelectedInstOperands, /*InsnID*/0,
        GIR_EraseFromParent, /*InsnID*/0,
        // GIR_Coverage, 10777,
        GIR_Done,
      // Label 5387: @398113
      GIM_Try, /*On fail goto*//*Label 5388*/ GIMT_Encode4(398217), // Rule ID 10778 //
        GIM_CheckFeatures, GIMT_Encode2(GIFBS_isGFX9Plus),
        GIM_RecordInsn, /*DefineMI*/1, /*MI*/0, /*OpIdx*/1, // MIs[1]
        GIM_CheckOpcode, /*MI*/1, GIMT_Encode2(TargetOpcode::G_UMIN),
        GIM_CheckType, /*MI*/1, /*Op*/1, /*Type*/GILLT_s16,
        GIM_CheckType, /*MI*/1, /*Op*/2, /*Type*/GILLT_s16,
        GIM_RecordInsn, /*DefineMI*/2, /*MI*/1, /*OpIdx*/1, // MIs[2]
        GIM_CheckOpcode, /*MI*/2, GIMT_Encode2(TargetOpcode::G_UMAX),
        GIM_CheckType, /*MI*/2, /*Op*/1, /*Type*/GILLT_s16,
        GIM_CheckType, /*MI*/2, /*Op*/2, /*Type*/GILLT_s16,
        GIM_RecordInsn, /*DefineMI*/3, /*MI*/0, /*OpIdx*/2, // MIs[3]
        GIM_CheckOpcode, /*MI*/3, GIMT_Encode2(TargetOpcode::G_UMIN),
        // MIs[3] src1
        GIM_CheckIsSameOperand, /*MI*/3, /*OpIdx*/1, /*OtherMI*/2, /*OtherOpIdx*/2,
        // MIs[3] src0
        GIM_CheckIsSameOperand, /*MI*/3, /*OpIdx*/2, /*OtherMI*/2, /*OtherOpIdx*/1,
        GIM_CheckIsSafeToFold, /*InsnID*/1,
        GIM_CheckIsSafeToFold, /*InsnID*/2,
        GIM_CheckIsSafeToFold, /*InsnID*/3,
        // (umax:{ *:[i16] } (umin:{ *:[i16] } (umax:{ *:[i16] } i16:{ *:[i16] }:$src0, i16:{ *:[i16] }:$src1), i16:{ *:[i16] }:$src2), (umin:{ *:[i16] } i16:{ *:[i16] }:$src1, i16:{ *:[i16] }:$src0))  =>  (V_MED3_U16_e64:{ *:[i16] } 0:{ *:[i32] }, VSrc_b16:{ *:[i16] }:$src0, 0:{ *:[i32] }, VSrc_b16:{ *:[i16] }:$src1, 0:{ *:[i32] }, VSrc_b16:{ *:[i16] }:$src2, 0:{ *:[i1] })
        GIR_BuildMI, /*InsnID*/0, /*Opcode*/GIMT_Encode2(AMDGPU::V_MED3_U16_e64),
        GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/0, // DstI[vdst]
        GIR_AddImm8, /*InsnID*/0, /*Imm*/0,
        GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/2, /*OpIdx*/1, // src0
        GIR_AddImm8, /*InsnID*/0, /*Imm*/0,
        GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/2, /*OpIdx*/2, // src1
        GIR_AddImm8, /*InsnID*/0, /*Imm*/0,
        GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/1, /*OpIdx*/2, // src2
        GIR_AddImm8, /*InsnID*/0, /*Imm*/0,
        GIR_AddImm8, /*InsnID*/0, /*Imm*/0,
        GIR_ConstrainSelectedInstOperands, /*InsnID*/0,
        GIR_EraseFromParent, /*InsnID*/0,
        // GIR_Coverage, 10778,
        GIR_Done,
      // Label 5388: @398217
      GIM_Try, /*On fail goto*//*Label 5389*/ GIMT_Encode4(398321), // Rule ID 10779 //
        GIM_CheckFeatures, GIMT_Encode2(GIFBS_isGFX9Plus),
        GIM_RecordInsn, /*DefineMI*/1, /*MI*/0, /*OpIdx*/1, // MIs[1]
        GIM_CheckOpcode, /*MI*/1, GIMT_Encode2(TargetOpcode::G_UMIN),
        GIM_CheckType, /*MI*/1, /*Op*/1, /*Type*/GILLT_s16,
        GIM_CheckType, /*MI*/1, /*Op*/2, /*Type*/GILLT_s16,
        GIM_RecordInsn, /*DefineMI*/2, /*MI*/1, /*OpIdx*/1, // MIs[2]
        GIM_CheckOpcode, /*MI*/2, GIMT_Encode2(TargetOpcode::G_UMAX),
        GIM_CheckType, /*MI*/2, /*Op*/1, /*Type*/GILLT_s16,
        GIM_CheckType, /*MI*/2, /*Op*/2, /*Type*/GILLT_s16,
        GIM_RecordInsn, /*DefineMI*/3, /*MI*/0, /*OpIdx*/2, // MIs[3]
        GIM_CheckOpcode, /*MI*/3, GIMT_Encode2(TargetOpcode::G_UMIN),
        // MIs[3] src0
        GIM_CheckIsSameOperand, /*MI*/3, /*OpIdx*/1, /*OtherMI*/2, /*OtherOpIdx*/2,
        // MIs[3] src1
        GIM_CheckIsSameOperand, /*MI*/3, /*OpIdx*/2, /*OtherMI*/2, /*OtherOpIdx*/1,
        GIM_CheckIsSafeToFold, /*InsnID*/1,
        GIM_CheckIsSafeToFold, /*InsnID*/2,
        GIM_CheckIsSafeToFold, /*InsnID*/3,
        // (umax:{ *:[i16] } (umin:{ *:[i16] } (umax:{ *:[i16] } i16:{ *:[i16] }:$src1, i16:{ *:[i16] }:$src0), i16:{ *:[i16] }:$src2), (umin:{ *:[i16] } i16:{ *:[i16] }:$src0, i16:{ *:[i16] }:$src1))  =>  (V_MED3_U16_e64:{ *:[i16] } 0:{ *:[i32] }, VSrc_b16:{ *:[i16] }:$src0, 0:{ *:[i32] }, VSrc_b16:{ *:[i16] }:$src1, 0:{ *:[i32] }, VSrc_b16:{ *:[i16] }:$src2, 0:{ *:[i1] })
        GIR_BuildMI, /*InsnID*/0, /*Opcode*/GIMT_Encode2(AMDGPU::V_MED3_U16_e64),
        GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/0, // DstI[vdst]
        GIR_AddImm8, /*InsnID*/0, /*Imm*/0,
        GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/2, /*OpIdx*/2, // src0
        GIR_AddImm8, /*InsnID*/0, /*Imm*/0,
        GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/2, /*OpIdx*/1, // src1
        GIR_AddImm8, /*InsnID*/0, /*Imm*/0,
        GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/1, /*OpIdx*/2, // src2
        GIR_AddImm8, /*InsnID*/0, /*Imm*/0,
        GIR_AddImm8, /*InsnID*/0, /*Imm*/0,
        GIR_ConstrainSelectedInstOperands, /*InsnID*/0,
        GIR_EraseFromParent, /*InsnID*/0,
        // GIR_Coverage, 10779,
        GIR_Done,
      // Label 5389: @398321
      GIM_Try, /*On fail goto*//*Label 5390*/ GIMT_Encode4(398425), // Rule ID 10780 //
        GIM_CheckFeatures, GIMT_Encode2(GIFBS_isGFX9Plus),
        GIM_RecordInsn, /*DefineMI*/1, /*MI*/0, /*OpIdx*/1, // MIs[1]
        GIM_CheckOpcode, /*MI*/1, GIMT_Encode2(TargetOpcode::G_UMIN),
        GIM_CheckType, /*MI*/1, /*Op*/1, /*Type*/GILLT_s16,
        GIM_CheckType, /*MI*/1, /*Op*/2, /*Type*/GILLT_s16,
        GIM_RecordInsn, /*DefineMI*/2, /*MI*/1, /*OpIdx*/1, // MIs[2]
        GIM_CheckOpcode, /*MI*/2, GIMT_Encode2(TargetOpcode::G_UMAX),
        GIM_CheckType, /*MI*/2, /*Op*/1, /*Type*/GILLT_s16,
        GIM_CheckType, /*MI*/2, /*Op*/2, /*Type*/GILLT_s16,
        GIM_RecordInsn, /*DefineMI*/3, /*MI*/0, /*OpIdx*/2, // MIs[3]
        GIM_CheckOpcode, /*MI*/3, GIMT_Encode2(TargetOpcode::G_UMIN),
        // MIs[3] src1
        GIM_CheckIsSameOperand, /*MI*/3, /*OpIdx*/1, /*OtherMI*/2, /*OtherOpIdx*/1,
        // MIs[3] src0
        GIM_CheckIsSameOperand, /*MI*/3, /*OpIdx*/2, /*OtherMI*/2, /*OtherOpIdx*/2,
        GIM_CheckIsSafeToFold, /*InsnID*/1,
        GIM_CheckIsSafeToFold, /*InsnID*/2,
        GIM_CheckIsSafeToFold, /*InsnID*/3,
        // (umax:{ *:[i16] } (umin:{ *:[i16] } (umax:{ *:[i16] } i16:{ *:[i16] }:$src1, i16:{ *:[i16] }:$src0), i16:{ *:[i16] }:$src2), (umin:{ *:[i16] } i16:{ *:[i16] }:$src1, i16:{ *:[i16] }:$src0))  =>  (V_MED3_U16_e64:{ *:[i16] } 0:{ *:[i32] }, VSrc_b16:{ *:[i16] }:$src0, 0:{ *:[i32] }, VSrc_b16:{ *:[i16] }:$src1, 0:{ *:[i32] }, VSrc_b16:{ *:[i16] }:$src2, 0:{ *:[i1] })
        GIR_BuildMI, /*InsnID*/0, /*Opcode*/GIMT_Encode2(AMDGPU::V_MED3_U16_e64),
        GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/0, // DstI[vdst]
        GIR_AddImm8, /*InsnID*/0, /*Imm*/0,
        GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/2, /*OpIdx*/2, // src0
        GIR_AddImm8, /*InsnID*/0, /*Imm*/0,
        GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/2, /*OpIdx*/1, // src1
        GIR_AddImm8, /*InsnID*/0, /*Imm*/0,
        GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/1, /*OpIdx*/2, // src2
        GIR_AddImm8, /*InsnID*/0, /*Imm*/0,
        GIR_AddImm8, /*InsnID*/0, /*Imm*/0,
        GIR_ConstrainSelectedInstOperands, /*InsnID*/0,
        GIR_EraseFromParent, /*InsnID*/0,
        // GIR_Coverage, 10780,
        GIR_Done,
      // Label 5390: @398425
      GIM_Try, /*On fail goto*//*Label 5391*/ GIMT_Encode4(398529), // Rule ID 10781 //
        GIM_CheckFeatures, GIMT_Encode2(GIFBS_isGFX9Plus),
        GIM_RecordInsn, /*DefineMI*/1, /*MI*/0, /*OpIdx*/1, // MIs[1]
        GIM_CheckOpcode, /*MI*/1, GIMT_Encode2(TargetOpcode::G_UMIN),
        GIM_CheckType, /*MI*/1, /*Op*/1, /*Type*/GILLT_s16,
        GIM_CheckType, /*MI*/1, /*Op*/2, /*Type*/GILLT_s16,
        GIM_RecordInsn, /*DefineMI*/2, /*MI*/1, /*OpIdx*/2, // MIs[2]
        GIM_CheckOpcode, /*MI*/2, GIMT_Encode2(TargetOpcode::G_UMAX),
        GIM_CheckType, /*MI*/2, /*Op*/1, /*Type*/GILLT_s16,
        GIM_CheckType, /*MI*/2, /*Op*/2, /*Type*/GILLT_s16,
        GIM_RecordInsn, /*DefineMI*/3, /*MI*/0, /*OpIdx*/2, // MIs[3]
        GIM_CheckOpcode, /*MI*/3, GIMT_Encode2(TargetOpcode::G_UMIN),
        // MIs[3] src0
        GIM_CheckIsSameOperand, /*MI*/3, /*OpIdx*/1, /*OtherMI*/2, /*OtherOpIdx*/1,
        // MIs[3] src1
        GIM_CheckIsSameOperand, /*MI*/3, /*OpIdx*/2, /*OtherMI*/2, /*OtherOpIdx*/2,
        GIM_CheckIsSafeToFold, /*InsnID*/1,
        GIM_CheckIsSafeToFold, /*InsnID*/2,
        GIM_CheckIsSafeToFold, /*InsnID*/3,
        // (umax:{ *:[i16] } (umin:{ *:[i16] } i16:{ *:[i16] }:$src2, (umax:{ *:[i16] } i16:{ *:[i16] }:$src0, i16:{ *:[i16] }:$src1)), (umin:{ *:[i16] } i16:{ *:[i16] }:$src0, i16:{ *:[i16] }:$src1))  =>  (V_MED3_U16_e64:{ *:[i16] } 0:{ *:[i32] }, VSrc_b16:{ *:[i16] }:$src0, 0:{ *:[i32] }, VSrc_b16:{ *:[i16] }:$src1, 0:{ *:[i32] }, VSrc_b16:{ *:[i16] }:$src2, 0:{ *:[i1] })
        GIR_BuildMI, /*InsnID*/0, /*Opcode*/GIMT_Encode2(AMDGPU::V_MED3_U16_e64),
        GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/0, // DstI[vdst]
        GIR_AddImm8, /*InsnID*/0, /*Imm*/0,
        GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/2, /*OpIdx*/1, // src0
        GIR_AddImm8, /*InsnID*/0, /*Imm*/0,
        GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/2, /*OpIdx*/2, // src1
        GIR_AddImm8, /*InsnID*/0, /*Imm*/0,
        GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/1, /*OpIdx*/1, // src2
        GIR_AddImm8, /*InsnID*/0, /*Imm*/0,
        GIR_AddImm8, /*InsnID*/0, /*Imm*/0,
        GIR_ConstrainSelectedInstOperands, /*InsnID*/0,
        GIR_EraseFromParent, /*InsnID*/0,
        // GIR_Coverage, 10781,
        GIR_Done,
      // Label 5391: @398529
      GIM_Try, /*On fail goto*//*Label 5392*/ GIMT_Encode4(398633), // Rule ID 10782 //
        GIM_CheckFeatures, GIMT_Encode2(GIFBS_isGFX9Plus),
        GIM_RecordInsn, /*DefineMI*/1, /*MI*/0, /*OpIdx*/1, // MIs[1]
        GIM_CheckOpcode, /*MI*/1, GIMT_Encode2(TargetOpcode::G_UMIN),
        GIM_CheckType, /*MI*/1, /*Op*/1, /*Type*/GILLT_s16,
        GIM_CheckType, /*MI*/1, /*Op*/2, /*Type*/GILLT_s16,
        GIM_RecordInsn, /*DefineMI*/2, /*MI*/1, /*OpIdx*/2, // MIs[2]
        GIM_CheckOpcode, /*MI*/2, GIMT_Encode2(TargetOpcode::G_UMAX),
        GIM_CheckType, /*MI*/2, /*Op*/1, /*Type*/GILLT_s16,
        GIM_CheckType, /*MI*/2, /*Op*/2, /*Type*/GILLT_s16,
        GIM_RecordInsn, /*DefineMI*/3, /*MI*/0, /*OpIdx*/2, // MIs[3]
        GIM_CheckOpcode, /*MI*/3, GIMT_Encode2(TargetOpcode::G_UMIN),
        // MIs[3] src1
        GIM_CheckIsSameOperand, /*MI*/3, /*OpIdx*/1, /*OtherMI*/2, /*OtherOpIdx*/2,
        // MIs[3] src0
        GIM_CheckIsSameOperand, /*MI*/3, /*OpIdx*/2, /*OtherMI*/2, /*OtherOpIdx*/1,
        GIM_CheckIsSafeToFold, /*InsnID*/1,
        GIM_CheckIsSafeToFold, /*InsnID*/2,
        GIM_CheckIsSafeToFold, /*InsnID*/3,
        // (umax:{ *:[i16] } (umin:{ *:[i16] } i16:{ *:[i16] }:$src2, (umax:{ *:[i16] } i16:{ *:[i16] }:$src0, i16:{ *:[i16] }:$src1)), (umin:{ *:[i16] } i16:{ *:[i16] }:$src1, i16:{ *:[i16] }:$src0))  =>  (V_MED3_U16_e64:{ *:[i16] } 0:{ *:[i32] }, VSrc_b16:{ *:[i16] }:$src0, 0:{ *:[i32] }, VSrc_b16:{ *:[i16] }:$src1, 0:{ *:[i32] }, VSrc_b16:{ *:[i16] }:$src2, 0:{ *:[i1] })
        GIR_BuildMI, /*InsnID*/0, /*Opcode*/GIMT_Encode2(AMDGPU::V_MED3_U16_e64),
        GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/0, // DstI[vdst]
        GIR_AddImm8, /*InsnID*/0, /*Imm*/0,
        GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/2, /*OpIdx*/1, // src0
        GIR_AddImm8, /*InsnID*/0, /*Imm*/0,
        GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/2, /*OpIdx*/2, // src1
        GIR_AddImm8, /*InsnID*/0, /*Imm*/0,
        GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/1, /*OpIdx*/1, // src2
        GIR_AddImm8, /*InsnID*/0, /*Imm*/0,
        GIR_AddImm8, /*InsnID*/0, /*Imm*/0,
        GIR_ConstrainSelectedInstOperands, /*InsnID*/0,
        GIR_EraseFromParent, /*InsnID*/0,
        // GIR_Coverage, 10782,
        GIR_Done,
      // Label 5392: @398633
      GIM_Try, /*On fail goto*//*Label 5393*/ GIMT_Encode4(398737), // Rule ID 10783 //
        GIM_CheckFeatures, GIMT_Encode2(GIFBS_isGFX9Plus),
        GIM_RecordInsn, /*DefineMI*/1, /*MI*/0, /*OpIdx*/1, // MIs[1]
        GIM_CheckOpcode, /*MI*/1, GIMT_Encode2(TargetOpcode::G_UMIN),
        GIM_CheckType, /*MI*/1, /*Op*/1, /*Type*/GILLT_s16,
        GIM_CheckType, /*MI*/1, /*Op*/2, /*Type*/GILLT_s16,
        GIM_RecordInsn, /*DefineMI*/2, /*MI*/1, /*OpIdx*/2, // MIs[2]
        GIM_CheckOpcode, /*MI*/2, GIMT_Encode2(TargetOpcode::G_UMAX),
        GIM_CheckType, /*MI*/2, /*Op*/1, /*Type*/GILLT_s16,
        GIM_CheckType, /*MI*/2, /*Op*/2, /*Type*/GILLT_s16,
        GIM_RecordInsn, /*DefineMI*/3, /*MI*/0, /*OpIdx*/2, // MIs[3]
        GIM_CheckOpcode, /*MI*/3, GIMT_Encode2(TargetOpcode::G_UMIN),
        // MIs[3] src0
        GIM_CheckIsSameOperand, /*MI*/3, /*OpIdx*/1, /*OtherMI*/2, /*OtherOpIdx*/2,
        // MIs[3] src1
        GIM_CheckIsSameOperand, /*MI*/3, /*OpIdx*/2, /*OtherMI*/2, /*OtherOpIdx*/1,
        GIM_CheckIsSafeToFold, /*InsnID*/1,
        GIM_CheckIsSafeToFold, /*InsnID*/2,
        GIM_CheckIsSafeToFold, /*InsnID*/3,
        // (umax:{ *:[i16] } (umin:{ *:[i16] } i16:{ *:[i16] }:$src2, (umax:{ *:[i16] } i16:{ *:[i16] }:$src1, i16:{ *:[i16] }:$src0)), (umin:{ *:[i16] } i16:{ *:[i16] }:$src0, i16:{ *:[i16] }:$src1))  =>  (V_MED3_U16_e64:{ *:[i16] } 0:{ *:[i32] }, VSrc_b16:{ *:[i16] }:$src0, 0:{ *:[i32] }, VSrc_b16:{ *:[i16] }:$src1, 0:{ *:[i32] }, VSrc_b16:{ *:[i16] }:$src2, 0:{ *:[i1] })
        GIR_BuildMI, /*InsnID*/0, /*Opcode*/GIMT_Encode2(AMDGPU::V_MED3_U16_e64),
        GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/0, // DstI[vdst]
        GIR_AddImm8, /*InsnID*/0, /*Imm*/0,
        GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/2, /*OpIdx*/2, // src0
        GIR_AddImm8, /*InsnID*/0, /*Imm*/0,
        GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/2, /*OpIdx*/1, // src1
        GIR_AddImm8, /*InsnID*/0, /*Imm*/0,
        GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/1, /*OpIdx*/1, // src2
        GIR_AddImm8, /*InsnID*/0, /*Imm*/0,
        GIR_AddImm8, /*InsnID*/0, /*Imm*/0,
        GIR_ConstrainSelectedInstOperands, /*InsnID*/0,
        GIR_EraseFromParent, /*InsnID*/0,
        // GIR_Coverage, 10783,
        GIR_Done,
      // Label 5393: @398737
      GIM_Try, /*On fail goto*//*Label 5394*/ GIMT_Encode4(398841), // Rule ID 10784 //
        GIM_CheckFeatures, GIMT_Encode2(GIFBS_isGFX9Plus),
        GIM_RecordInsn, /*DefineMI*/1, /*MI*/0, /*OpIdx*/1, // MIs[1]
        GIM_CheckOpcode, /*MI*/1, GIMT_Encode2(TargetOpcode::G_UMIN),
        GIM_CheckType, /*MI*/1, /*Op*/1, /*Type*/GILLT_s16,
        GIM_CheckType, /*MI*/1, /*Op*/2, /*Type*/GILLT_s16,
        GIM_RecordInsn, /*DefineMI*/2, /*MI*/1, /*OpIdx*/2, // MIs[2]
        GIM_CheckOpcode, /*MI*/2, GIMT_Encode2(TargetOpcode::G_UMAX),
        GIM_CheckType, /*MI*/2, /*Op*/1, /*Type*/GILLT_s16,
        GIM_CheckType, /*MI*/2, /*Op*/2, /*Type*/GILLT_s16,
        GIM_RecordInsn, /*DefineMI*/3, /*MI*/0, /*OpIdx*/2, // MIs[3]
        GIM_CheckOpcode, /*MI*/3, GIMT_Encode2(TargetOpcode::G_UMIN),
        // MIs[3] src1
        GIM_CheckIsSameOperand, /*MI*/3, /*OpIdx*/1, /*OtherMI*/2, /*OtherOpIdx*/1,
        // MIs[3] src0
        GIM_CheckIsSameOperand, /*MI*/3, /*OpIdx*/2, /*OtherMI*/2, /*OtherOpIdx*/2,
        GIM_CheckIsSafeToFold, /*InsnID*/1,
        GIM_CheckIsSafeToFold, /*InsnID*/2,
        GIM_CheckIsSafeToFold, /*InsnID*/3,
        // (umax:{ *:[i16] } (umin:{ *:[i16] } i16:{ *:[i16] }:$src2, (umax:{ *:[i16] } i16:{ *:[i16] }:$src1, i16:{ *:[i16] }:$src0)), (umin:{ *:[i16] } i16:{ *:[i16] }:$src1, i16:{ *:[i16] }:$src0))  =>  (V_MED3_U16_e64:{ *:[i16] } 0:{ *:[i32] }, VSrc_b16:{ *:[i16] }:$src0, 0:{ *:[i32] }, VSrc_b16:{ *:[i16] }:$src1, 0:{ *:[i32] }, VSrc_b16:{ *:[i16] }:$src2, 0:{ *:[i1] })
        GIR_BuildMI, /*InsnID*/0, /*Opcode*/GIMT_Encode2(AMDGPU::V_MED3_U16_e64),
        GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/0, // DstI[vdst]
        GIR_AddImm8, /*InsnID*/0, /*Imm*/0,
        GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/2, /*OpIdx*/2, // src0
        GIR_AddImm8, /*InsnID*/0, /*Imm*/0,
        GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/2, /*OpIdx*/1, // src1
        GIR_AddImm8, /*InsnID*/0, /*Imm*/0,
        GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/1, /*OpIdx*/1, // src2
        GIR_AddImm8, /*InsnID*/0, /*Imm*/0,
        GIR_AddImm8, /*InsnID*/0, /*Imm*/0,
        GIR_ConstrainSelectedInstOperands, /*InsnID*/0,
        GIR_EraseFromParent, /*InsnID*/0,
        // GIR_Coverage, 10784,
        GIR_Done,
      // Label 5394: @398841
      GIM_Try, /*On fail goto*//*Label 5395*/ GIMT_Encode4(398945), // Rule ID 6552 //
        GIM_CheckFeatures, GIMT_Encode2(GIFBS_isGFX9Plus),
        GIM_RecordInsn, /*DefineMI*/1, /*MI*/0, /*OpIdx*/1, // MIs[1]
        GIM_CheckOpcode, /*MI*/1, GIMT_Encode2(TargetOpcode::G_UMIN),
        GIM_CheckType, /*MI*/1, /*Op*/1, /*Type*/GILLT_s16,
        GIM_CheckType, /*MI*/1, /*Op*/2, /*Type*/GILLT_s16,
        GIM_RecordInsn, /*DefineMI*/2, /*MI*/0, /*OpIdx*/2, // MIs[2]
        GIM_CheckOpcode, /*MI*/2, GIMT_Encode2(TargetOpcode::G_UMIN),
        GIM_CheckType, /*MI*/2, /*Op*/1, /*Type*/GILLT_s16,
        GIM_CheckType, /*MI*/2, /*Op*/2, /*Type*/GILLT_s16,
        GIM_RecordInsn, /*DefineMI*/3, /*MI*/2, /*OpIdx*/1, // MIs[3]
        GIM_CheckOpcode, /*MI*/3, GIMT_Encode2(TargetOpcode::G_UMAX),
        // MIs[3] src0
        GIM_CheckIsSameOperand, /*MI*/3, /*OpIdx*/1, /*OtherMI*/1, /*OtherOpIdx*/1,
        // MIs[3] src1
        GIM_CheckIsSameOperand, /*MI*/3, /*OpIdx*/2, /*OtherMI*/1, /*OtherOpIdx*/2,
        GIM_CheckIsSafeToFold, /*InsnID*/1,
        GIM_CheckIsSafeToFold, /*InsnID*/2,
        GIM_CheckIsSafeToFold, /*InsnID*/3,
        // (umax:{ *:[i16] } (umin:{ *:[i16] } i16:{ *:[i16] }:$src0, i16:{ *:[i16] }:$src1), (umin:{ *:[i16] } (umax:{ *:[i16] } i16:{ *:[i16] }:$src0, i16:{ *:[i16] }:$src1), i16:{ *:[i16] }:$src2))  =>  (V_MED3_U16_e64:{ *:[i16] } 0:{ *:[i32] }, VSrc_b16:{ *:[i16] }:$src0, 0:{ *:[i32] }, VSrc_b16:{ *:[i16] }:$src1, 0:{ *:[i32] }, VSrc_b16:{ *:[i16] }:$src2, 0:{ *:[i1] })
        GIR_BuildMI, /*InsnID*/0, /*Opcode*/GIMT_Encode2(AMDGPU::V_MED3_U16_e64),
        GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/0, // DstI[vdst]
        GIR_AddImm8, /*InsnID*/0, /*Imm*/0,
        GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/1, /*OpIdx*/1, // src0
        GIR_AddImm8, /*InsnID*/0, /*Imm*/0,
        GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/1, /*OpIdx*/2, // src1
        GIR_AddImm8, /*InsnID*/0, /*Imm*/0,
        GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/2, /*OpIdx*/2, // src2
        GIR_AddImm8, /*InsnID*/0, /*Imm*/0,
        GIR_AddImm8, /*InsnID*/0, /*Imm*/0,
        GIR_ConstrainSelectedInstOperands, /*InsnID*/0,
        GIR_EraseFromParent, /*InsnID*/0,
        // GIR_Coverage, 6552,
        GIR_Done,
      // Label 5395: @398945
      GIM_Try, /*On fail goto*//*Label 5396*/ GIMT_Encode4(399049), // Rule ID 10770 //
        GIM_CheckFeatures, GIMT_Encode2(GIFBS_isGFX9Plus),
        GIM_RecordInsn, /*DefineMI*/1, /*MI*/0, /*OpIdx*/1, // MIs[1]
        GIM_CheckOpcode, /*MI*/1, GIMT_Encode2(TargetOpcode::G_UMIN),
        GIM_CheckType, /*MI*/1, /*Op*/1, /*Type*/GILLT_s16,
        GIM_CheckType, /*MI*/1, /*Op*/2, /*Type*/GILLT_s16,
        GIM_RecordInsn, /*DefineMI*/2, /*MI*/0, /*OpIdx*/2, // MIs[2]
        GIM_CheckOpcode, /*MI*/2, GIMT_Encode2(TargetOpcode::G_UMIN),
        GIM_CheckType, /*MI*/2, /*Op*/1, /*Type*/GILLT_s16,
        GIM_CheckType, /*MI*/2, /*Op*/2, /*Type*/GILLT_s16,
        GIM_RecordInsn, /*DefineMI*/3, /*MI*/2, /*OpIdx*/1, // MIs[3]
        GIM_CheckOpcode, /*MI*/3, GIMT_Encode2(TargetOpcode::G_UMAX),
        // MIs[3] src1
        GIM_CheckIsSameOperand, /*MI*/3, /*OpIdx*/1, /*OtherMI*/1, /*OtherOpIdx*/2,
        // MIs[3] src0
        GIM_CheckIsSameOperand, /*MI*/3, /*OpIdx*/2, /*OtherMI*/1, /*OtherOpIdx*/1,
        GIM_CheckIsSafeToFold, /*InsnID*/1,
        GIM_CheckIsSafeToFold, /*InsnID*/2,
        GIM_CheckIsSafeToFold, /*InsnID*/3,
        // (umax:{ *:[i16] } (umin:{ *:[i16] } i16:{ *:[i16] }:$src0, i16:{ *:[i16] }:$src1), (umin:{ *:[i16] } (umax:{ *:[i16] } i16:{ *:[i16] }:$src1, i16:{ *:[i16] }:$src0), i16:{ *:[i16] }:$src2))  =>  (V_MED3_U16_e64:{ *:[i16] } 0:{ *:[i32] }, VSrc_b16:{ *:[i16] }:$src0, 0:{ *:[i32] }, VSrc_b16:{ *:[i16] }:$src1, 0:{ *:[i32] }, VSrc_b16:{ *:[i16] }:$src2, 0:{ *:[i1] })
        GIR_BuildMI, /*InsnID*/0, /*Opcode*/GIMT_Encode2(AMDGPU::V_MED3_U16_e64),
        GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/0, // DstI[vdst]
        GIR_AddImm8, /*InsnID*/0, /*Imm*/0,
        GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/1, /*OpIdx*/1, // src0
        GIR_AddImm8, /*InsnID*/0, /*Imm*/0,
        GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/1, /*OpIdx*/2, // src1
        GIR_AddImm8, /*InsnID*/0, /*Imm*/0,
        GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/2, /*OpIdx*/2, // src2
        GIR_AddImm8, /*InsnID*/0, /*Imm*/0,
        GIR_AddImm8, /*InsnID*/0, /*Imm*/0,
        GIR_ConstrainSelectedInstOperands, /*InsnID*/0,
        GIR_EraseFromParent, /*InsnID*/0,
        // GIR_Coverage, 10770,
        GIR_Done,
      // Label 5396: @399049
      GIM_Try, /*On fail goto*//*Label 5397*/ GIMT_Encode4(399153), // Rule ID 10773 //
        GIM_CheckFeatures, GIMT_Encode2(GIFBS_isGFX9Plus),
        GIM_RecordInsn, /*DefineMI*/1, /*MI*/0, /*OpIdx*/1, // MIs[1]
        GIM_CheckOpcode, /*MI*/1, GIMT_Encode2(TargetOpcode::G_UMIN),
        GIM_CheckType, /*MI*/1, /*Op*/1, /*Type*/GILLT_s16,
        GIM_CheckType, /*MI*/1, /*Op*/2, /*Type*/GILLT_s16,
        GIM_RecordInsn, /*DefineMI*/2, /*MI*/0, /*OpIdx*/2, // MIs[2]
        GIM_CheckOpcode, /*MI*/2, GIMT_Encode2(TargetOpcode::G_UMIN),
        GIM_CheckType, /*MI*/2, /*Op*/1, /*Type*/GILLT_s16,
        GIM_CheckType, /*MI*/2, /*Op*/2, /*Type*/GILLT_s16,
        GIM_RecordInsn, /*DefineMI*/3, /*MI*/2, /*OpIdx*/1, // MIs[3]
        GIM_CheckOpcode, /*MI*/3, GIMT_Encode2(TargetOpcode::G_UMAX),
        // MIs[3] src0
        GIM_CheckIsSameOperand, /*MI*/3, /*OpIdx*/1, /*OtherMI*/1, /*OtherOpIdx*/2,
        // MIs[3] src1
        GIM_CheckIsSameOperand, /*MI*/3, /*OpIdx*/2, /*OtherMI*/1, /*OtherOpIdx*/1,
        GIM_CheckIsSafeToFold, /*InsnID*/1,
        GIM_CheckIsSafeToFold, /*InsnID*/2,
        GIM_CheckIsSafeToFold, /*InsnID*/3,
        // (umax:{ *:[i16] } (umin:{ *:[i16] } i16:{ *:[i16] }:$src1, i16:{ *:[i16] }:$src0), (umin:{ *:[i16] } (umax:{ *:[i16] } i16:{ *:[i16] }:$src0, i16:{ *:[i16] }:$src1), i16:{ *:[i16] }:$src2))  =>  (V_MED3_U16_e64:{ *:[i16] } 0:{ *:[i32] }, VSrc_b16:{ *:[i16] }:$src0, 0:{ *:[i32] }, VSrc_b16:{ *:[i16] }:$src1, 0:{ *:[i32] }, VSrc_b16:{ *:[i16] }:$src2, 0:{ *:[i1] })
        GIR_BuildMI, /*InsnID*/0, /*Opcode*/GIMT_Encode2(AMDGPU::V_MED3_U16_e64),
        GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/0, // DstI[vdst]
        GIR_AddImm8, /*InsnID*/0, /*Imm*/0,
        GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/1, /*OpIdx*/2, // src0
        GIR_AddImm8, /*InsnID*/0, /*Imm*/0,
        GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/1, /*OpIdx*/1, // src1
        GIR_AddImm8, /*InsnID*/0, /*Imm*/0,
        GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/2, /*OpIdx*/2, // src2
        GIR_AddImm8, /*InsnID*/0, /*Imm*/0,
        GIR_AddImm8, /*InsnID*/0, /*Imm*/0,
        GIR_ConstrainSelectedInstOperands, /*InsnID*/0,
        GIR_EraseFromParent, /*InsnID*/0,
        // GIR_Coverage, 10773,
        GIR_Done,
      // Label 5397: @399153
      GIM_Try, /*On fail goto*//*Label 5398*/ GIMT_Encode4(399257), // Rule ID 10774 //
        GIM_CheckFeatures, GIMT_Encode2(GIFBS_isGFX9Plus),
        GIM_RecordInsn, /*DefineMI*/1, /*MI*/0, /*OpIdx*/1, // MIs[1]
        GIM_CheckOpcode, /*MI*/1, GIMT_Encode2(TargetOpcode::G_UMIN),
        GIM_CheckType, /*MI*/1, /*Op*/1, /*Type*/GILLT_s16,
        GIM_CheckType, /*MI*/1, /*Op*/2, /*Type*/GILLT_s16,
        GIM_RecordInsn, /*DefineMI*/2, /*MI*/0, /*OpIdx*/2, // MIs[2]
        GIM_CheckOpcode, /*MI*/2, GIMT_Encode2(TargetOpcode::G_UMIN),
        GIM_CheckType, /*MI*/2, /*Op*/1, /*Type*/GILLT_s16,
        GIM_CheckType, /*MI*/2, /*Op*/2, /*Type*/GILLT_s16,
        GIM_RecordInsn, /*DefineMI*/3, /*MI*/2, /*OpIdx*/1, // MIs[3]
        GIM_CheckOpcode, /*MI*/3, GIMT_Encode2(TargetOpcode::G_UMAX),
        // MIs[3] src1
        GIM_CheckIsSameOperand, /*MI*/3, /*OpIdx*/1, /*OtherMI*/1, /*OtherOpIdx*/1,
        // MIs[3] src0
        GIM_CheckIsSameOperand, /*MI*/3, /*OpIdx*/2, /*OtherMI*/1, /*OtherOpIdx*/2,
        GIM_CheckIsSafeToFold, /*InsnID*/1,
        GIM_CheckIsSafeToFold, /*InsnID*/2,
        GIM_CheckIsSafeToFold, /*InsnID*/3,
        // (umax:{ *:[i16] } (umin:{ *:[i16] } i16:{ *:[i16] }:$src1, i16:{ *:[i16] }:$src0), (umin:{ *:[i16] } (umax:{ *:[i16] } i16:{ *:[i16] }:$src1, i16:{ *:[i16] }:$src0), i16:{ *:[i16] }:$src2))  =>  (V_MED3_U16_e64:{ *:[i16] } 0:{ *:[i32] }, VSrc_b16:{ *:[i16] }:$src0, 0:{ *:[i32] }, VSrc_b16:{ *:[i16] }:$src1, 0:{ *:[i32] }, VSrc_b16:{ *:[i16] }:$src2, 0:{ *:[i1] })
        GIR_BuildMI, /*InsnID*/0, /*Opcode*/GIMT_Encode2(AMDGPU::V_MED3_U16_e64),
        GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/0, // DstI[vdst]
        GIR_AddImm8, /*InsnID*/0, /*Imm*/0,
        GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/1, /*OpIdx*/2, // src0
        GIR_AddImm8, /*InsnID*/0, /*Imm*/0,
        GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/1, /*OpIdx*/1, // src1
        GIR_AddImm8, /*InsnID*/0, /*Imm*/0,
        GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/2, /*OpIdx*/2, // src2
        GIR_AddImm8, /*InsnID*/0, /*Imm*/0,
        GIR_AddImm8, /*InsnID*/0, /*Imm*/0,
        GIR_ConstrainSelectedInstOperands, /*InsnID*/0,
        GIR_EraseFromParent, /*InsnID*/0,
        // GIR_Coverage, 10774,
        GIR_Done,
      // Label 5398: @399257
      GIM_Try, /*On fail goto*//*Label 5399*/ GIMT_Encode4(399361), // Rule ID 10771 //
        GIM_CheckFeatures, GIMT_Encode2(GIFBS_isGFX9Plus),
        GIM_RecordInsn, /*DefineMI*/1, /*MI*/0, /*OpIdx*/1, // MIs[1]
        GIM_CheckOpcode, /*MI*/1, GIMT_Encode2(TargetOpcode::G_UMIN),
        GIM_CheckType, /*MI*/1, /*Op*/1, /*Type*/GILLT_s16,
        GIM_CheckType, /*MI*/1, /*Op*/2, /*Type*/GILLT_s16,
        GIM_RecordInsn, /*DefineMI*/2, /*MI*/0, /*OpIdx*/2, // MIs[2]
        GIM_CheckOpcode, /*MI*/2, GIMT_Encode2(TargetOpcode::G_UMIN),
        GIM_CheckType, /*MI*/2, /*Op*/1, /*Type*/GILLT_s16,
        GIM_CheckType, /*MI*/2, /*Op*/2, /*Type*/GILLT_s16,
        GIM_RecordInsn, /*DefineMI*/3, /*MI*/2, /*OpIdx*/2, // MIs[3]
        GIM_CheckOpcode, /*MI*/3, GIMT_Encode2(TargetOpcode::G_UMAX),
        // MIs[3] src0
        GIM_CheckIsSameOperand, /*MI*/3, /*OpIdx*/1, /*OtherMI*/1, /*OtherOpIdx*/1,
        // MIs[3] src1
        GIM_CheckIsSameOperand, /*MI*/3, /*OpIdx*/2, /*OtherMI*/1, /*OtherOpIdx*/2,
        GIM_CheckIsSafeToFold, /*InsnID*/1,
        GIM_CheckIsSafeToFold, /*InsnID*/2,
        GIM_CheckIsSafeToFold, /*InsnID*/3,
        // (umax:{ *:[i16] } (umin:{ *:[i16] } i16:{ *:[i16] }:$src0, i16:{ *:[i16] }:$src1), (umin:{ *:[i16] } i16:{ *:[i16] }:$src2, (umax:{ *:[i16] } i16:{ *:[i16] }:$src0, i16:{ *:[i16] }:$src1)))  =>  (V_MED3_U16_e64:{ *:[i16] } 0:{ *:[i32] }, VSrc_b16:{ *:[i16] }:$src0, 0:{ *:[i32] }, VSrc_b16:{ *:[i16] }:$src1, 0:{ *:[i32] }, VSrc_b16:{ *:[i16] }:$src2, 0:{ *:[i1] })
        GIR_BuildMI, /*InsnID*/0, /*Opcode*/GIMT_Encode2(AMDGPU::V_MED3_U16_e64),
        GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/0, // DstI[vdst]
        GIR_AddImm8, /*InsnID*/0, /*Imm*/0,
        GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/1, /*OpIdx*/1, // src0
        GIR_AddImm8, /*InsnID*/0, /*Imm*/0,
        GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/1, /*OpIdx*/2, // src1
        GIR_AddImm8, /*InsnID*/0, /*Imm*/0,
        GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/2, /*OpIdx*/1, // src2
        GIR_AddImm8, /*InsnID*/0, /*Imm*/0,
        GIR_AddImm8, /*InsnID*/0, /*Imm*/0,
        GIR_ConstrainSelectedInstOperands, /*InsnID*/0,
        GIR_EraseFromParent, /*InsnID*/0,
        // GIR_Coverage, 10771,
        GIR_Done,
      // Label 5399: @399361
      GIM_Try, /*On fail goto*//*Label 5400*/ GIMT_Encode4(399465), // Rule ID 10772 //
        GIM_CheckFeatures, GIMT_Encode2(GIFBS_isGFX9Plus),
        GIM_RecordInsn, /*DefineMI*/1, /*MI*/0, /*OpIdx*/1, // MIs[1]
        GIM_CheckOpcode, /*MI*/1, GIMT_Encode2(TargetOpcode::G_UMIN),
        GIM_CheckType, /*MI*/1, /*Op*/1, /*Type*/GILLT_s16,
        GIM_CheckType, /*MI*/1, /*Op*/2, /*Type*/GILLT_s16,
        GIM_RecordInsn, /*DefineMI*/2, /*MI*/0, /*OpIdx*/2, // MIs[2]
        GIM_CheckOpcode, /*MI*/2, GIMT_Encode2(TargetOpcode::G_UMIN),
        GIM_CheckType, /*MI*/2, /*Op*/1, /*Type*/GILLT_s16,
        GIM_CheckType, /*MI*/2, /*Op*/2, /*Type*/GILLT_s16,
        GIM_RecordInsn, /*DefineMI*/3, /*MI*/2, /*OpIdx*/2, // MIs[3]
        GIM_CheckOpcode, /*MI*/3, GIMT_Encode2(TargetOpcode::G_UMAX),
        // MIs[3] src1
        GIM_CheckIsSameOperand, /*MI*/3, /*OpIdx*/1, /*OtherMI*/1, /*OtherOpIdx*/2,
        // MIs[3] src0
        GIM_CheckIsSameOperand, /*MI*/3, /*OpIdx*/2, /*OtherMI*/1, /*OtherOpIdx*/1,
        GIM_CheckIsSafeToFold, /*InsnID*/1,
        GIM_CheckIsSafeToFold, /*InsnID*/2,
        GIM_CheckIsSafeToFold, /*InsnID*/3,
        // (umax:{ *:[i16] } (umin:{ *:[i16] } i16:{ *:[i16] }:$src0, i16:{ *:[i16] }:$src1), (umin:{ *:[i16] } i16:{ *:[i16] }:$src2, (umax:{ *:[i16] } i16:{ *:[i16] }:$src1, i16:{ *:[i16] }:$src0)))  =>  (V_MED3_U16_e64:{ *:[i16] } 0:{ *:[i32] }, VSrc_b16:{ *:[i16] }:$src0, 0:{ *:[i32] }, VSrc_b16:{ *:[i16] }:$src1, 0:{ *:[i32] }, VSrc_b16:{ *:[i16] }:$src2, 0:{ *:[i1] })
        GIR_BuildMI, /*InsnID*/0, /*Opcode*/GIMT_Encode2(AMDGPU::V_MED3_U16_e64),
        GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/0, // DstI[vdst]
        GIR_AddImm8, /*InsnID*/0, /*Imm*/0,
        GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/1, /*OpIdx*/1, // src0
        GIR_AddImm8, /*InsnID*/0, /*Imm*/0,
        GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/1, /*OpIdx*/2, // src1
        GIR_AddImm8, /*InsnID*/0, /*Imm*/0,
        GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/2, /*OpIdx*/1, // src2
        GIR_AddImm8, /*InsnID*/0, /*Imm*/0,
        GIR_AddImm8, /*InsnID*/0, /*Imm*/0,
        GIR_ConstrainSelectedInstOperands, /*InsnID*/0,
        GIR_EraseFromParent, /*InsnID*/0,
        // GIR_Coverage, 10772,
        GIR_Done,
      // Label 5400: @399465
      GIM_Try, /*On fail goto*//*Label 5401*/ GIMT_Encode4(399569), // Rule ID 10775 //
        GIM_CheckFeatures, GIMT_Encode2(GIFBS_isGFX9Plus),
        GIM_RecordInsn, /*DefineMI*/1, /*MI*/0, /*OpIdx*/1, // MIs[1]
        GIM_CheckOpcode, /*MI*/1, GIMT_Encode2(TargetOpcode::G_UMIN),
        GIM_CheckType, /*MI*/1, /*Op*/1, /*Type*/GILLT_s16,
        GIM_CheckType, /*MI*/1, /*Op*/2, /*Type*/GILLT_s16,
        GIM_RecordInsn, /*DefineMI*/2, /*MI*/0, /*OpIdx*/2, // MIs[2]
        GIM_CheckOpcode, /*MI*/2, GIMT_Encode2(TargetOpcode::G_UMIN),
        GIM_CheckType, /*MI*/2, /*Op*/1, /*Type*/GILLT_s16,
        GIM_CheckType, /*MI*/2, /*Op*/2, /*Type*/GILLT_s16,
        GIM_RecordInsn, /*DefineMI*/3, /*MI*/2, /*OpIdx*/2, // MIs[3]
        GIM_CheckOpcode, /*MI*/3, GIMT_Encode2(TargetOpcode::G_UMAX),
        // MIs[3] src0
        GIM_CheckIsSameOperand, /*MI*/3, /*OpIdx*/1, /*OtherMI*/1, /*OtherOpIdx*/2,
        // MIs[3] src1
        GIM_CheckIsSameOperand, /*MI*/3, /*OpIdx*/2, /*OtherMI*/1, /*OtherOpIdx*/1,
        GIM_CheckIsSafeToFold, /*InsnID*/1,
        GIM_CheckIsSafeToFold, /*InsnID*/2,
        GIM_CheckIsSafeToFold, /*InsnID*/3,
        // (umax:{ *:[i16] } (umin:{ *:[i16] } i16:{ *:[i16] }:$src1, i16:{ *:[i16] }:$src0), (umin:{ *:[i16] } i16:{ *:[i16] }:$src2, (umax:{ *:[i16] } i16:{ *:[i16] }:$src0, i16:{ *:[i16] }:$src1)))  =>  (V_MED3_U16_e64:{ *:[i16] } 0:{ *:[i32] }, VSrc_b16:{ *:[i16] }:$src0, 0:{ *:[i32] }, VSrc_b16:{ *:[i16] }:$src1, 0:{ *:[i32] }, VSrc_b16:{ *:[i16] }:$src2, 0:{ *:[i1] })
        GIR_BuildMI, /*InsnID*/0, /*Opcode*/GIMT_Encode2(AMDGPU::V_MED3_U16_e64),
        GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/0, // DstI[vdst]
        GIR_AddImm8, /*InsnID*/0, /*Imm*/0,
        GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/1, /*OpIdx*/2, // src0
        GIR_AddImm8, /*InsnID*/0, /*Imm*/0,
        GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/1, /*OpIdx*/1, // src1
        GIR_AddImm8, /*InsnID*/0, /*Imm*/0,
        GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/2, /*OpIdx*/1, // src2
        GIR_AddImm8, /*InsnID*/0, /*Imm*/0,
        GIR_AddImm8, /*InsnID*/0, /*Imm*/0,
        GIR_ConstrainSelectedInstOperands, /*InsnID*/0,
        GIR_EraseFromParent, /*InsnID*/0,
        // GIR_Coverage, 10775,
        GIR_Done,
      // Label 5401: @399569
      GIM_Try, /*On fail goto*//*Label 5402*/ GIMT_Encode4(399673), // Rule ID 10776 //
        GIM_CheckFeatures, GIMT_Encode2(GIFBS_isGFX9Plus),
        GIM_RecordInsn, /*DefineMI*/1, /*MI*/0, /*OpIdx*/1, // MIs[1]
        GIM_CheckOpcode, /*MI*/1, GIMT_Encode2(TargetOpcode::G_UMIN),
        GIM_CheckType, /*MI*/1, /*Op*/1, /*Type*/GILLT_s16,
        GIM_CheckType, /*MI*/1, /*Op*/2, /*Type*/GILLT_s16,
        GIM_RecordInsn, /*DefineMI*/2, /*MI*/0, /*OpIdx*/2, // MIs[2]
        GIM_CheckOpcode, /*MI*/2, GIMT_Encode2(TargetOpcode::G_UMIN),
        GIM_CheckType, /*MI*/2, /*Op*/1, /*Type*/GILLT_s16,
        GIM_CheckType, /*MI*/2, /*Op*/2, /*Type*/GILLT_s16,
        GIM_RecordInsn, /*DefineMI*/3, /*MI*/2, /*OpIdx*/2, // MIs[3]
        GIM_CheckOpcode, /*MI*/3, GIMT_Encode2(TargetOpcode::G_UMAX),
        // MIs[3] src1
        GIM_CheckIsSameOperand, /*MI*/3, /*OpIdx*/1, /*OtherMI*/1, /*OtherOpIdx*/1,
        // MIs[3] src0
        GIM_CheckIsSameOperand, /*MI*/3, /*OpIdx*/2, /*OtherMI*/1, /*OtherOpIdx*/2,
        GIM_CheckIsSafeToFold, /*InsnID*/1,
        GIM_CheckIsSafeToFold, /*InsnID*/2,
        GIM_CheckIsSafeToFold, /*InsnID*/3,
        // (umax:{ *:[i16] } (umin:{ *:[i16] } i16:{ *:[i16] }:$src1, i16:{ *:[i16] }:$src0), (umin:{ *:[i16] } i16:{ *:[i16] }:$src2, (umax:{ *:[i16] } i16:{ *:[i16] }:$src1, i16:{ *:[i16] }:$src0)))  =>  (V_MED3_U16_e64:{ *:[i16] } 0:{ *:[i32] }, VSrc_b16:{ *:[i16] }:$src0, 0:{ *:[i32] }, VSrc_b16:{ *:[i16] }:$src1, 0:{ *:[i32] }, VSrc_b16:{ *:[i16] }:$src2, 0:{ *:[i1] })
        GIR_BuildMI, /*InsnID*/0, /*Opcode*/GIMT_Encode2(AMDGPU::V_MED3_U16_e64),
        GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/0, // DstI[vdst]
        GIR_AddImm8, /*InsnID*/0, /*Imm*/0,
        GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/1, /*OpIdx*/2, // src0
        GIR_AddImm8, /*InsnID*/0, /*Imm*/0,
        GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/1, /*OpIdx*/1, // src1
        GIR_AddImm8, /*InsnID*/0, /*Imm*/0,
        GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/2, /*OpIdx*/1, // src2
        GIR_AddImm8, /*InsnID*/0, /*Imm*/0,
        GIR_AddImm8, /*InsnID*/0, /*Imm*/0,
        GIR_ConstrainSelectedInstOperands, /*InsnID*/0,
        GIR_EraseFromParent, /*InsnID*/0,
        // GIR_Coverage, 10776,
        GIR_Done,
      // Label 5402: @399673
      GIM_Try, /*On fail goto*//*Label 5403*/ GIMT_Encode4(399693), // Rule ID 825 //
        GIM_CheckFeatures, GIMT_Encode2(GIFBS_Has16BitInsts_NotHasTrue16BitInsts),
        // (umax:{ *:[i16] } i16:{ *:[i16] }:$src0, i16:{ *:[i16] }:$src1)  =>  (V_MAX_U16_e64:{ *:[i16] } i16:{ *:[i16] }:$src0, i16:{ *:[i16] }:$src1)
        GIR_MutateOpcode, /*InsnID*/0, /*RecycleInsnID*/0, /*Opcode*/GIMT_Encode2(AMDGPU::V_MAX_U16_e64),
        GIR_AddImplicitUse, /*InsnID*/0, GIMT_Encode2(AMDGPU::EXEC),
        GIR_ConstrainSelectedInstOperands, /*InsnID*/0,
        // GIR_Coverage, 825,
        GIR_Done,
      // Label 5403: @399693
      GIM_Try, /*On fail goto*//*Label 5404*/ GIMT_Encode4(399713), // Rule ID 826 //
        GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasTrue16BitInsts),
        // (umax:{ *:[i16] } i16:{ *:[i16] }:$src0, i16:{ *:[i16] }:$src1)  =>  (V_MAX_U16_t16_e64:{ *:[i16] } i16:{ *:[i16] }:$src0, i16:{ *:[i16] }:$src1)
        GIR_MutateOpcode, /*InsnID*/0, /*RecycleInsnID*/0, /*Opcode*/GIMT_Encode2(AMDGPU::V_MAX_U16_t16_e64),
        GIR_AddImplicitUse, /*InsnID*/0, GIMT_Encode2(AMDGPU::EXEC),
        GIR_ConstrainSelectedInstOperands, /*InsnID*/0,
        // GIR_Coverage, 826,
        GIR_Done,
      // Label 5404: @399713
      GIM_Reject,
    // Label 5386: @399714
    GIM_Reject,
    // Label 5383: @399715
    GIM_Try, /*On fail goto*//*Label 5405*/ GIMT_Encode4(401363),
      GIM_CheckType, /*MI*/0, /*Op*/1, /*Type*/GILLT_s32,
      GIM_CheckType, /*MI*/0, /*Op*/2, /*Type*/GILLT_s32,
      GIM_Try, /*On fail goto*//*Label 5406*/ GIMT_Encode4(399819), // Rule ID 9992 //
        GIM_CheckRegBankForClass, /*MI*/0, /*Op*/0, /*RC*/GIMT_Encode2(AMDGPU::VGPR_32RegClassID),
        GIM_RecordInsn, /*DefineMI*/1, /*MI*/0, /*OpIdx*/1, // MIs[1]
        GIM_CheckOpcode, /*MI*/1, GIMT_Encode2(TargetOpcode::G_UMIN),
        GIM_CheckType, /*MI*/1, /*Op*/1, /*Type*/GILLT_s32,
        GIM_CheckType, /*MI*/1, /*Op*/2, /*Type*/GILLT_s32,
        GIM_RecordInsn, /*DefineMI*/2, /*MI*/1, /*OpIdx*/1, // MIs[2]
        GIM_CheckOpcode, /*MI*/2, GIMT_Encode2(TargetOpcode::G_UMAX),
        GIM_CheckType, /*MI*/2, /*Op*/1, /*Type*/GILLT_s32,
        GIM_CheckType, /*MI*/2, /*Op*/2, /*Type*/GILLT_s32,
        GIM_RecordInsn, /*DefineMI*/3, /*MI*/0, /*OpIdx*/2, // MIs[3]
        GIM_CheckOpcode, /*MI*/3, GIMT_Encode2(TargetOpcode::G_UMIN),
        // MIs[3] src0
        GIM_CheckIsSameOperand, /*MI*/3, /*OpIdx*/1, /*OtherMI*/2, /*OtherOpIdx*/1,
        // MIs[3] src1
        GIM_CheckIsSameOperand, /*MI*/3, /*OpIdx*/2, /*OtherMI*/2, /*OtherOpIdx*/2,
        GIM_CheckIsSafeToFold, /*InsnID*/1,
        GIM_CheckIsSafeToFold, /*InsnID*/2,
        GIM_CheckIsSafeToFold, /*InsnID*/3,
        // (umax:{ *:[i32] } (umin:{ *:[i32] } (umax:{ *:[i32] } i32:{ *:[i32] }:$src0, i32:{ *:[i32] }:$src1), i32:{ *:[i32] }:$src2), (umin:{ *:[i32] } i32:{ *:[i32] }:$src0, i32:{ *:[i32] }:$src1))  =>  (V_MED3_U32_e64:{ *:[i32] } VSrc_b32:{ *:[i32] }:$src0, VSrc_b32:{ *:[i32] }:$src1, VSrc_b32:{ *:[i32] }:$src2)
        GIR_BuildMI, /*InsnID*/0, /*Opcode*/GIMT_Encode2(AMDGPU::V_MED3_U32_e64),
        GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/0, // DstI[vdst]
        GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/2, /*OpIdx*/1, // src0
        GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/2, /*OpIdx*/2, // src1
        GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/1, /*OpIdx*/2, // src2
        GIR_ConstrainSelectedInstOperands, /*InsnID*/0,
        GIR_EraseFromParent, /*InsnID*/0,
        // GIR_Coverage, 9992,
        GIR_Done,
      // Label 5406: @399819
      GIM_Try, /*On fail goto*//*Label 5407*/ GIMT_Encode4(399910), // Rule ID 9993 //
        GIM_CheckRegBankForClass, /*MI*/0, /*Op*/0, /*RC*/GIMT_Encode2(AMDGPU::VGPR_32RegClassID),
        GIM_RecordInsn, /*DefineMI*/1, /*MI*/0, /*OpIdx*/1, // MIs[1]
        GIM_CheckOpcode, /*MI*/1, GIMT_Encode2(TargetOpcode::G_UMIN),
        GIM_CheckType, /*MI*/1, /*Op*/1, /*Type*/GILLT_s32,
        GIM_CheckType, /*MI*/1, /*Op*/2, /*Type*/GILLT_s32,
        GIM_RecordInsn, /*DefineMI*/2, /*MI*/1, /*OpIdx*/1, // MIs[2]
        GIM_CheckOpcode, /*MI*/2, GIMT_Encode2(TargetOpcode::G_UMAX),
        GIM_CheckType, /*MI*/2, /*Op*/1, /*Type*/GILLT_s32,
        GIM_CheckType, /*MI*/2, /*Op*/2, /*Type*/GILLT_s32,
        GIM_RecordInsn, /*DefineMI*/3, /*MI*/0, /*OpIdx*/2, // MIs[3]
        GIM_CheckOpcode, /*MI*/3, GIMT_Encode2(TargetOpcode::G_UMIN),
        // MIs[3] src1
        GIM_CheckIsSameOperand, /*MI*/3, /*OpIdx*/1, /*OtherMI*/2, /*OtherOpIdx*/2,
        // MIs[3] src0
        GIM_CheckIsSameOperand, /*MI*/3, /*OpIdx*/2, /*OtherMI*/2, /*OtherOpIdx*/1,
        GIM_CheckIsSafeToFold, /*InsnID*/1,
        GIM_CheckIsSafeToFold, /*InsnID*/2,
        GIM_CheckIsSafeToFold, /*InsnID*/3,
        // (umax:{ *:[i32] } (umin:{ *:[i32] } (umax:{ *:[i32] } i32:{ *:[i32] }:$src0, i32:{ *:[i32] }:$src1), i32:{ *:[i32] }:$src2), (umin:{ *:[i32] } i32:{ *:[i32] }:$src1, i32:{ *:[i32] }:$src0))  =>  (V_MED3_U32_e64:{ *:[i32] } VSrc_b32:{ *:[i32] }:$src0, VSrc_b32:{ *:[i32] }:$src1, VSrc_b32:{ *:[i32] }:$src2)
        GIR_BuildMI, /*InsnID*/0, /*Opcode*/GIMT_Encode2(AMDGPU::V_MED3_U32_e64),
        GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/0, // DstI[vdst]
        GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/2, /*OpIdx*/1, // src0
        GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/2, /*OpIdx*/2, // src1
        GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/1, /*OpIdx*/2, // src2
        GIR_ConstrainSelectedInstOperands, /*InsnID*/0,
        GIR_EraseFromParent, /*InsnID*/0,
        // GIR_Coverage, 9993,
        GIR_Done,
      // Label 5407: @399910
      GIM_Try, /*On fail goto*//*Label 5408*/ GIMT_Encode4(400001), // Rule ID 9994 //
        GIM_CheckRegBankForClass, /*MI*/0, /*Op*/0, /*RC*/GIMT_Encode2(AMDGPU::VGPR_32RegClassID),
        GIM_RecordInsn, /*DefineMI*/1, /*MI*/0, /*OpIdx*/1, // MIs[1]
        GIM_CheckOpcode, /*MI*/1, GIMT_Encode2(TargetOpcode::G_UMIN),
        GIM_CheckType, /*MI*/1, /*Op*/1, /*Type*/GILLT_s32,
        GIM_CheckType, /*MI*/1, /*Op*/2, /*Type*/GILLT_s32,
        GIM_RecordInsn, /*DefineMI*/2, /*MI*/1, /*OpIdx*/1, // MIs[2]
        GIM_CheckOpcode, /*MI*/2, GIMT_Encode2(TargetOpcode::G_UMAX),
        GIM_CheckType, /*MI*/2, /*Op*/1, /*Type*/GILLT_s32,
        GIM_CheckType, /*MI*/2, /*Op*/2, /*Type*/GILLT_s32,
        GIM_RecordInsn, /*DefineMI*/3, /*MI*/0, /*OpIdx*/2, // MIs[3]
        GIM_CheckOpcode, /*MI*/3, GIMT_Encode2(TargetOpcode::G_UMIN),
        // MIs[3] src0
        GIM_CheckIsSameOperand, /*MI*/3, /*OpIdx*/1, /*OtherMI*/2, /*OtherOpIdx*/2,
        // MIs[3] src1
        GIM_CheckIsSameOperand, /*MI*/3, /*OpIdx*/2, /*OtherMI*/2, /*OtherOpIdx*/1,
        GIM_CheckIsSafeToFold, /*InsnID*/1,
        GIM_CheckIsSafeToFold, /*InsnID*/2,
        GIM_CheckIsSafeToFold, /*InsnID*/3,
        // (umax:{ *:[i32] } (umin:{ *:[i32] } (umax:{ *:[i32] } i32:{ *:[i32] }:$src1, i32:{ *:[i32] }:$src0), i32:{ *:[i32] }:$src2), (umin:{ *:[i32] } i32:{ *:[i32] }:$src0, i32:{ *:[i32] }:$src1))  =>  (V_MED3_U32_e64:{ *:[i32] } VSrc_b32:{ *:[i32] }:$src0, VSrc_b32:{ *:[i32] }:$src1, VSrc_b32:{ *:[i32] }:$src2)
        GIR_BuildMI, /*InsnID*/0, /*Opcode*/GIMT_Encode2(AMDGPU::V_MED3_U32_e64),
        GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/0, // DstI[vdst]
        GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/2, /*OpIdx*/2, // src0
        GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/2, /*OpIdx*/1, // src1
        GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/1, /*OpIdx*/2, // src2
        GIR_ConstrainSelectedInstOperands, /*InsnID*/0,
        GIR_EraseFromParent, /*InsnID*/0,
        // GIR_Coverage, 9994,
        GIR_Done,
      // Label 5408: @400001
      GIM_Try, /*On fail goto*//*Label 5409*/ GIMT_Encode4(400092), // Rule ID 9995 //
        GIM_CheckRegBankForClass, /*MI*/0, /*Op*/0, /*RC*/GIMT_Encode2(AMDGPU::VGPR_32RegClassID),
        GIM_RecordInsn, /*DefineMI*/1, /*MI*/0, /*OpIdx*/1, // MIs[1]
        GIM_CheckOpcode, /*MI*/1, GIMT_Encode2(TargetOpcode::G_UMIN),
        GIM_CheckType, /*MI*/1, /*Op*/1, /*Type*/GILLT_s32,
        GIM_CheckType, /*MI*/1, /*Op*/2, /*Type*/GILLT_s32,
        GIM_RecordInsn, /*DefineMI*/2, /*MI*/1, /*OpIdx*/1, // MIs[2]
        GIM_CheckOpcode, /*MI*/2, GIMT_Encode2(TargetOpcode::G_UMAX),
        GIM_CheckType, /*MI*/2, /*Op*/1, /*Type*/GILLT_s32,
        GIM_CheckType, /*MI*/2, /*Op*/2, /*Type*/GILLT_s32,
        GIM_RecordInsn, /*DefineMI*/3, /*MI*/0, /*OpIdx*/2, // MIs[3]
        GIM_CheckOpcode, /*MI*/3, GIMT_Encode2(TargetOpcode::G_UMIN),
        // MIs[3] src1
        GIM_CheckIsSameOperand, /*MI*/3, /*OpIdx*/1, /*OtherMI*/2, /*OtherOpIdx*/1,
        // MIs[3] src0
        GIM_CheckIsSameOperand, /*MI*/3, /*OpIdx*/2, /*OtherMI*/2, /*OtherOpIdx*/2,
        GIM_CheckIsSafeToFold, /*InsnID*/1,
        GIM_CheckIsSafeToFold, /*InsnID*/2,
        GIM_CheckIsSafeToFold, /*InsnID*/3,
        // (umax:{ *:[i32] } (umin:{ *:[i32] } (umax:{ *:[i32] } i32:{ *:[i32] }:$src1, i32:{ *:[i32] }:$src0), i32:{ *:[i32] }:$src2), (umin:{ *:[i32] } i32:{ *:[i32] }:$src1, i32:{ *:[i32] }:$src0))  =>  (V_MED3_U32_e64:{ *:[i32] } VSrc_b32:{ *:[i32] }:$src0, VSrc_b32:{ *:[i32] }:$src1, VSrc_b32:{ *:[i32] }:$src2)
        GIR_BuildMI, /*InsnID*/0, /*Opcode*/GIMT_Encode2(AMDGPU::V_MED3_U32_e64),
        GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/0, // DstI[vdst]
        GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/2, /*OpIdx*/2, // src0
        GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/2, /*OpIdx*/1, // src1
        GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/1, /*OpIdx*/2, // src2
        GIR_ConstrainSelectedInstOperands, /*InsnID*/0,
        GIR_EraseFromParent, /*InsnID*/0,
        // GIR_Coverage, 9995,
        GIR_Done,
      // Label 5409: @400092
      GIM_Try, /*On fail goto*//*Label 5410*/ GIMT_Encode4(400183), // Rule ID 9996 //
        GIM_CheckRegBankForClass, /*MI*/0, /*Op*/0, /*RC*/GIMT_Encode2(AMDGPU::VGPR_32RegClassID),
        GIM_RecordInsn, /*DefineMI*/1, /*MI*/0, /*OpIdx*/1, // MIs[1]
        GIM_CheckOpcode, /*MI*/1, GIMT_Encode2(TargetOpcode::G_UMIN),
        GIM_CheckType, /*MI*/1, /*Op*/1, /*Type*/GILLT_s32,
        GIM_CheckType, /*MI*/1, /*Op*/2, /*Type*/GILLT_s32,
        GIM_RecordInsn, /*DefineMI*/2, /*MI*/1, /*OpIdx*/2, // MIs[2]
        GIM_CheckOpcode, /*MI*/2, GIMT_Encode2(TargetOpcode::G_UMAX),
        GIM_CheckType, /*MI*/2, /*Op*/1, /*Type*/GILLT_s32,
        GIM_CheckType, /*MI*/2, /*Op*/2, /*Type*/GILLT_s32,
        GIM_RecordInsn, /*DefineMI*/3, /*MI*/0, /*OpIdx*/2, // MIs[3]
        GIM_CheckOpcode, /*MI*/3, GIMT_Encode2(TargetOpcode::G_UMIN),
        // MIs[3] src0
        GIM_CheckIsSameOperand, /*MI*/3, /*OpIdx*/1, /*OtherMI*/2, /*OtherOpIdx*/1,
        // MIs[3] src1
        GIM_CheckIsSameOperand, /*MI*/3, /*OpIdx*/2, /*OtherMI*/2, /*OtherOpIdx*/2,
        GIM_CheckIsSafeToFold, /*InsnID*/1,
        GIM_CheckIsSafeToFold, /*InsnID*/2,
        GIM_CheckIsSafeToFold, /*InsnID*/3,
        // (umax:{ *:[i32] } (umin:{ *:[i32] } i32:{ *:[i32] }:$src2, (umax:{ *:[i32] } i32:{ *:[i32] }:$src0, i32:{ *:[i32] }:$src1)), (umin:{ *:[i32] } i32:{ *:[i32] }:$src0, i32:{ *:[i32] }:$src1))  =>  (V_MED3_U32_e64:{ *:[i32] } VSrc_b32:{ *:[i32] }:$src0, VSrc_b32:{ *:[i32] }:$src1, VSrc_b32:{ *:[i32] }:$src2)
        GIR_BuildMI, /*InsnID*/0, /*Opcode*/GIMT_Encode2(AMDGPU::V_MED3_U32_e64),
        GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/0, // DstI[vdst]
        GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/2, /*OpIdx*/1, // src0
        GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/2, /*OpIdx*/2, // src1
        GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/1, /*OpIdx*/1, // src2
        GIR_ConstrainSelectedInstOperands, /*InsnID*/0,
        GIR_EraseFromParent, /*InsnID*/0,
        // GIR_Coverage, 9996,
        GIR_Done,
      // Label 5410: @400183
      GIM_Try, /*On fail goto*//*Label 5411*/ GIMT_Encode4(400274), // Rule ID 9997 //
        GIM_CheckRegBankForClass, /*MI*/0, /*Op*/0, /*RC*/GIMT_Encode2(AMDGPU::VGPR_32RegClassID),
        GIM_RecordInsn, /*DefineMI*/1, /*MI*/0, /*OpIdx*/1, // MIs[1]
        GIM_CheckOpcode, /*MI*/1, GIMT_Encode2(TargetOpcode::G_UMIN),
        GIM_CheckType, /*MI*/1, /*Op*/1, /*Type*/GILLT_s32,
        GIM_CheckType, /*MI*/1, /*Op*/2, /*Type*/GILLT_s32,
        GIM_RecordInsn, /*DefineMI*/2, /*MI*/1, /*OpIdx*/2, // MIs[2]
        GIM_CheckOpcode, /*MI*/2, GIMT_Encode2(TargetOpcode::G_UMAX),
        GIM_CheckType, /*MI*/2, /*Op*/1, /*Type*/GILLT_s32,
        GIM_CheckType, /*MI*/2, /*Op*/2, /*Type*/GILLT_s32,
        GIM_RecordInsn, /*DefineMI*/3, /*MI*/0, /*OpIdx*/2, // MIs[3]
        GIM_CheckOpcode, /*MI*/3, GIMT_Encode2(TargetOpcode::G_UMIN),
        // MIs[3] src1
        GIM_CheckIsSameOperand, /*MI*/3, /*OpIdx*/1, /*OtherMI*/2, /*OtherOpIdx*/2,
        // MIs[3] src0
        GIM_CheckIsSameOperand, /*MI*/3, /*OpIdx*/2, /*OtherMI*/2, /*OtherOpIdx*/1,
        GIM_CheckIsSafeToFold, /*InsnID*/1,
        GIM_CheckIsSafeToFold, /*InsnID*/2,
        GIM_CheckIsSafeToFold, /*InsnID*/3,
        // (umax:{ *:[i32] } (umin:{ *:[i32] } i32:{ *:[i32] }:$src2, (umax:{ *:[i32] } i32:{ *:[i32] }:$src0, i32:{ *:[i32] }:$src1)), (umin:{ *:[i32] } i32:{ *:[i32] }:$src1, i32:{ *:[i32] }:$src0))  =>  (V_MED3_U32_e64:{ *:[i32] } VSrc_b32:{ *:[i32] }:$src0, VSrc_b32:{ *:[i32] }:$src1, VSrc_b32:{ *:[i32] }:$src2)
        GIR_BuildMI, /*InsnID*/0, /*Opcode*/GIMT_Encode2(AMDGPU::V_MED3_U32_e64),
        GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/0, // DstI[vdst]
        GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/2, /*OpIdx*/1, // src0
        GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/2, /*OpIdx*/2, // src1
        GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/1, /*OpIdx*/1, // src2
        GIR_ConstrainSelectedInstOperands, /*InsnID*/0,
        GIR_EraseFromParent, /*InsnID*/0,
        // GIR_Coverage, 9997,
        GIR_Done,
      // Label 5411: @400274
      GIM_Try, /*On fail goto*//*Label 5412*/ GIMT_Encode4(400365), // Rule ID 9998 //
        GIM_CheckRegBankForClass, /*MI*/0, /*Op*/0, /*RC*/GIMT_Encode2(AMDGPU::VGPR_32RegClassID),
        GIM_RecordInsn, /*DefineMI*/1, /*MI*/0, /*OpIdx*/1, // MIs[1]
        GIM_CheckOpcode, /*MI*/1, GIMT_Encode2(TargetOpcode::G_UMIN),
        GIM_CheckType, /*MI*/1, /*Op*/1, /*Type*/GILLT_s32,
        GIM_CheckType, /*MI*/1, /*Op*/2, /*Type*/GILLT_s32,
        GIM_RecordInsn, /*DefineMI*/2, /*MI*/1, /*OpIdx*/2, // MIs[2]
        GIM_CheckOpcode, /*MI*/2, GIMT_Encode2(TargetOpcode::G_UMAX),
        GIM_CheckType, /*MI*/2, /*Op*/1, /*Type*/GILLT_s32,
        GIM_CheckType, /*MI*/2, /*Op*/2, /*Type*/GILLT_s32,
        GIM_RecordInsn, /*DefineMI*/3, /*MI*/0, /*OpIdx*/2, // MIs[3]
        GIM_CheckOpcode, /*MI*/3, GIMT_Encode2(TargetOpcode::G_UMIN),
        // MIs[3] src0
        GIM_CheckIsSameOperand, /*MI*/3, /*OpIdx*/1, /*OtherMI*/2, /*OtherOpIdx*/2,
        // MIs[3] src1
        GIM_CheckIsSameOperand, /*MI*/3, /*OpIdx*/2, /*OtherMI*/2, /*OtherOpIdx*/1,
        GIM_CheckIsSafeToFold, /*InsnID*/1,
        GIM_CheckIsSafeToFold, /*InsnID*/2,
        GIM_CheckIsSafeToFold, /*InsnID*/3,
        // (umax:{ *:[i32] } (umin:{ *:[i32] } i32:{ *:[i32] }:$src2, (umax:{ *:[i32] } i32:{ *:[i32] }:$src1, i32:{ *:[i32] }:$src0)), (umin:{ *:[i32] } i32:{ *:[i32] }:$src0, i32:{ *:[i32] }:$src1))  =>  (V_MED3_U32_e64:{ *:[i32] } VSrc_b32:{ *:[i32] }:$src0, VSrc_b32:{ *:[i32] }:$src1, VSrc_b32:{ *:[i32] }:$src2)
        GIR_BuildMI, /*InsnID*/0, /*Opcode*/GIMT_Encode2(AMDGPU::V_MED3_U32_e64),
        GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/0, // DstI[vdst]
        GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/2, /*OpIdx*/2, // src0
        GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/2, /*OpIdx*/1, // src1
        GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/1, /*OpIdx*/1, // src2
        GIR_ConstrainSelectedInstOperands, /*InsnID*/0,
        GIR_EraseFromParent, /*InsnID*/0,
        // GIR_Coverage, 9998,
        GIR_Done,
      // Label 5412: @400365
      GIM_Try, /*On fail goto*//*Label 5413*/ GIMT_Encode4(400456), // Rule ID 9999 //
        GIM_CheckRegBankForClass, /*MI*/0, /*Op*/0, /*RC*/GIMT_Encode2(AMDGPU::VGPR_32RegClassID),
        GIM_RecordInsn, /*DefineMI*/1, /*MI*/0, /*OpIdx*/1, // MIs[1]
        GIM_CheckOpcode, /*MI*/1, GIMT_Encode2(TargetOpcode::G_UMIN),
        GIM_CheckType, /*MI*/1, /*Op*/1, /*Type*/GILLT_s32,
        GIM_CheckType, /*MI*/1, /*Op*/2, /*Type*/GILLT_s32,
        GIM_RecordInsn, /*DefineMI*/2, /*MI*/1, /*OpIdx*/2, // MIs[2]
        GIM_CheckOpcode, /*MI*/2, GIMT_Encode2(TargetOpcode::G_UMAX),
        GIM_CheckType, /*MI*/2, /*Op*/1, /*Type*/GILLT_s32,
        GIM_CheckType, /*MI*/2, /*Op*/2, /*Type*/GILLT_s32,
        GIM_RecordInsn, /*DefineMI*/3, /*MI*/0, /*OpIdx*/2, // MIs[3]
        GIM_CheckOpcode, /*MI*/3, GIMT_Encode2(TargetOpcode::G_UMIN),
        // MIs[3] src1
        GIM_CheckIsSameOperand, /*MI*/3, /*OpIdx*/1, /*OtherMI*/2, /*OtherOpIdx*/1,
        // MIs[3] src0
        GIM_CheckIsSameOperand, /*MI*/3, /*OpIdx*/2, /*OtherMI*/2, /*OtherOpIdx*/2,
        GIM_CheckIsSafeToFold, /*InsnID*/1,
        GIM_CheckIsSafeToFold, /*InsnID*/2,
        GIM_CheckIsSafeToFold, /*InsnID*/3,
        // (umax:{ *:[i32] } (umin:{ *:[i32] } i32:{ *:[i32] }:$src2, (umax:{ *:[i32] } i32:{ *:[i32] }:$src1, i32:{ *:[i32] }:$src0)), (umin:{ *:[i32] } i32:{ *:[i32] }:$src1, i32:{ *:[i32] }:$src0))  =>  (V_MED3_U32_e64:{ *:[i32] } VSrc_b32:{ *:[i32] }:$src0, VSrc_b32:{ *:[i32] }:$src1, VSrc_b32:{ *:[i32] }:$src2)
        GIR_BuildMI, /*InsnID*/0, /*Opcode*/GIMT_Encode2(AMDGPU::V_MED3_U32_e64),
        GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/0, // DstI[vdst]
        GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/2, /*OpIdx*/2, // src0
        GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/2, /*OpIdx*/1, // src1
        GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/1, /*OpIdx*/1, // src2
        GIR_ConstrainSelectedInstOperands, /*InsnID*/0,
        GIR_EraseFromParent, /*InsnID*/0,
        // GIR_Coverage, 9999,
        GIR_Done,
      // Label 5413: @400456
      GIM_Try, /*On fail goto*//*Label 5414*/ GIMT_Encode4(400547), // Rule ID 6481 //
        GIM_CheckRegBankForClass, /*MI*/0, /*Op*/0, /*RC*/GIMT_Encode2(AMDGPU::VGPR_32RegClassID),
        GIM_RecordInsn, /*DefineMI*/1, /*MI*/0, /*OpIdx*/1, // MIs[1]
        GIM_CheckOpcode, /*MI*/1, GIMT_Encode2(TargetOpcode::G_UMIN),
        GIM_CheckType, /*MI*/1, /*Op*/1, /*Type*/GILLT_s32,
        GIM_CheckType, /*MI*/1, /*Op*/2, /*Type*/GILLT_s32,
        GIM_RecordInsn, /*DefineMI*/2, /*MI*/0, /*OpIdx*/2, // MIs[2]
        GIM_CheckOpcode, /*MI*/2, GIMT_Encode2(TargetOpcode::G_UMIN),
        GIM_CheckType, /*MI*/2, /*Op*/1, /*Type*/GILLT_s32,
        GIM_CheckType, /*MI*/2, /*Op*/2, /*Type*/GILLT_s32,
        GIM_RecordInsn, /*DefineMI*/3, /*MI*/2, /*OpIdx*/1, // MIs[3]
        GIM_CheckOpcode, /*MI*/3, GIMT_Encode2(TargetOpcode::G_UMAX),
        // MIs[3] src0
        GIM_CheckIsSameOperand, /*MI*/3, /*OpIdx*/1, /*OtherMI*/1, /*OtherOpIdx*/1,
        // MIs[3] src1
        GIM_CheckIsSameOperand, /*MI*/3, /*OpIdx*/2, /*OtherMI*/1, /*OtherOpIdx*/2,
        GIM_CheckIsSafeToFold, /*InsnID*/1,
        GIM_CheckIsSafeToFold, /*InsnID*/2,
        GIM_CheckIsSafeToFold, /*InsnID*/3,
        // (umax:{ *:[i32] } (umin:{ *:[i32] } i32:{ *:[i32] }:$src0, i32:{ *:[i32] }:$src1), (umin:{ *:[i32] } (umax:{ *:[i32] } i32:{ *:[i32] }:$src0, i32:{ *:[i32] }:$src1), i32:{ *:[i32] }:$src2))  =>  (V_MED3_U32_e64:{ *:[i32] } VSrc_b32:{ *:[i32] }:$src0, VSrc_b32:{ *:[i32] }:$src1, VSrc_b32:{ *:[i32] }:$src2)
        GIR_BuildMI, /*InsnID*/0, /*Opcode*/GIMT_Encode2(AMDGPU::V_MED3_U32_e64),
        GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/0, // DstI[vdst]
        GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/1, /*OpIdx*/1, // src0
        GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/1, /*OpIdx*/2, // src1
        GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/2, /*OpIdx*/2, // src2
        GIR_ConstrainSelectedInstOperands, /*InsnID*/0,
        GIR_EraseFromParent, /*InsnID*/0,
        // GIR_Coverage, 6481,
        GIR_Done,
      // Label 5414: @400547
      GIM_Try, /*On fail goto*//*Label 5415*/ GIMT_Encode4(400638), // Rule ID 9985 //
        GIM_CheckRegBankForClass, /*MI*/0, /*Op*/0, /*RC*/GIMT_Encode2(AMDGPU::VGPR_32RegClassID),
        GIM_RecordInsn, /*DefineMI*/1, /*MI*/0, /*OpIdx*/1, // MIs[1]
        GIM_CheckOpcode, /*MI*/1, GIMT_Encode2(TargetOpcode::G_UMIN),
        GIM_CheckType, /*MI*/1, /*Op*/1, /*Type*/GILLT_s32,
        GIM_CheckType, /*MI*/1, /*Op*/2, /*Type*/GILLT_s32,
        GIM_RecordInsn, /*DefineMI*/2, /*MI*/0, /*OpIdx*/2, // MIs[2]
        GIM_CheckOpcode, /*MI*/2, GIMT_Encode2(TargetOpcode::G_UMIN),
        GIM_CheckType, /*MI*/2, /*Op*/1, /*Type*/GILLT_s32,
        GIM_CheckType, /*MI*/2, /*Op*/2, /*Type*/GILLT_s32,
        GIM_RecordInsn, /*DefineMI*/3, /*MI*/2, /*OpIdx*/1, // MIs[3]
        GIM_CheckOpcode, /*MI*/3, GIMT_Encode2(TargetOpcode::G_UMAX),
        // MIs[3] src1
        GIM_CheckIsSameOperand, /*MI*/3, /*OpIdx*/1, /*OtherMI*/1, /*OtherOpIdx*/2,
        // MIs[3] src0
        GIM_CheckIsSameOperand, /*MI*/3, /*OpIdx*/2, /*OtherMI*/1, /*OtherOpIdx*/1,
        GIM_CheckIsSafeToFold, /*InsnID*/1,
        GIM_CheckIsSafeToFold, /*InsnID*/2,
        GIM_CheckIsSafeToFold, /*InsnID*/3,
        // (umax:{ *:[i32] } (umin:{ *:[i32] } i32:{ *:[i32] }:$src0, i32:{ *:[i32] }:$src1), (umin:{ *:[i32] } (umax:{ *:[i32] } i32:{ *:[i32] }:$src1, i32:{ *:[i32] }:$src0), i32:{ *:[i32] }:$src2))  =>  (V_MED3_U32_e64:{ *:[i32] } VSrc_b32:{ *:[i32] }:$src0, VSrc_b32:{ *:[i32] }:$src1, VSrc_b32:{ *:[i32] }:$src2)
        GIR_BuildMI, /*InsnID*/0, /*Opcode*/GIMT_Encode2(AMDGPU::V_MED3_U32_e64),
        GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/0, // DstI[vdst]
        GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/1, /*OpIdx*/1, // src0
        GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/1, /*OpIdx*/2, // src1
        GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/2, /*OpIdx*/2, // src2
        GIR_ConstrainSelectedInstOperands, /*InsnID*/0,
        GIR_EraseFromParent, /*InsnID*/0,
        // GIR_Coverage, 9985,
        GIR_Done,
      // Label 5415: @400638
      GIM_Try, /*On fail goto*//*Label 5416*/ GIMT_Encode4(400729), // Rule ID 9988 //
        GIM_CheckRegBankForClass, /*MI*/0, /*Op*/0, /*RC*/GIMT_Encode2(AMDGPU::VGPR_32RegClassID),
        GIM_RecordInsn, /*DefineMI*/1, /*MI*/0, /*OpIdx*/1, // MIs[1]
        GIM_CheckOpcode, /*MI*/1, GIMT_Encode2(TargetOpcode::G_UMIN),
        GIM_CheckType, /*MI*/1, /*Op*/1, /*Type*/GILLT_s32,
        GIM_CheckType, /*MI*/1, /*Op*/2, /*Type*/GILLT_s32,
        GIM_RecordInsn, /*DefineMI*/2, /*MI*/0, /*OpIdx*/2, // MIs[2]
        GIM_CheckOpcode, /*MI*/2, GIMT_Encode2(TargetOpcode::G_UMIN),
        GIM_CheckType, /*MI*/2, /*Op*/1, /*Type*/GILLT_s32,
        GIM_CheckType, /*MI*/2, /*Op*/2, /*Type*/GILLT_s32,
        GIM_RecordInsn, /*DefineMI*/3, /*MI*/2, /*OpIdx*/1, // MIs[3]
        GIM_CheckOpcode, /*MI*/3, GIMT_Encode2(TargetOpcode::G_UMAX),
        // MIs[3] src0
        GIM_CheckIsSameOperand, /*MI*/3, /*OpIdx*/1, /*OtherMI*/1, /*OtherOpIdx*/2,
        // MIs[3] src1
        GIM_CheckIsSameOperand, /*MI*/3, /*OpIdx*/2, /*OtherMI*/1, /*OtherOpIdx*/1,
        GIM_CheckIsSafeToFold, /*InsnID*/1,
        GIM_CheckIsSafeToFold, /*InsnID*/2,
        GIM_CheckIsSafeToFold, /*InsnID*/3,
        // (umax:{ *:[i32] } (umin:{ *:[i32] } i32:{ *:[i32] }:$src1, i32:{ *:[i32] }:$src0), (umin:{ *:[i32] } (umax:{ *:[i32] } i32:{ *:[i32] }:$src0, i32:{ *:[i32] }:$src1), i32:{ *:[i32] }:$src2))  =>  (V_MED3_U32_e64:{ *:[i32] } VSrc_b32:{ *:[i32] }:$src0, VSrc_b32:{ *:[i32] }:$src1, VSrc_b32:{ *:[i32] }:$src2)
        GIR_BuildMI, /*InsnID*/0, /*Opcode*/GIMT_Encode2(AMDGPU::V_MED3_U32_e64),
        GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/0, // DstI[vdst]
        GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/1, /*OpIdx*/2, // src0
        GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/1, /*OpIdx*/1, // src1
        GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/2, /*OpIdx*/2, // src2
        GIR_ConstrainSelectedInstOperands, /*InsnID*/0,
        GIR_EraseFromParent, /*InsnID*/0,
        // GIR_Coverage, 9988,
        GIR_Done,
      // Label 5416: @400729
      GIM_Try, /*On fail goto*//*Label 5417*/ GIMT_Encode4(400820), // Rule ID 9989 //
        GIM_CheckRegBankForClass, /*MI*/0, /*Op*/0, /*RC*/GIMT_Encode2(AMDGPU::VGPR_32RegClassID),
        GIM_RecordInsn, /*DefineMI*/1, /*MI*/0, /*OpIdx*/1, // MIs[1]
        GIM_CheckOpcode, /*MI*/1, GIMT_Encode2(TargetOpcode::G_UMIN),
        GIM_CheckType, /*MI*/1, /*Op*/1, /*Type*/GILLT_s32,
        GIM_CheckType, /*MI*/1, /*Op*/2, /*Type*/GILLT_s32,
        GIM_RecordInsn, /*DefineMI*/2, /*MI*/0, /*OpIdx*/2, // MIs[2]
        GIM_CheckOpcode, /*MI*/2, GIMT_Encode2(TargetOpcode::G_UMIN),
        GIM_CheckType, /*MI*/2, /*Op*/1, /*Type*/GILLT_s32,
        GIM_CheckType, /*MI*/2, /*Op*/2, /*Type*/GILLT_s32,
        GIM_RecordInsn, /*DefineMI*/3, /*MI*/2, /*OpIdx*/1, // MIs[3]
        GIM_CheckOpcode, /*MI*/3, GIMT_Encode2(TargetOpcode::G_UMAX),
        // MIs[3] src1
        GIM_CheckIsSameOperand, /*MI*/3, /*OpIdx*/1, /*OtherMI*/1, /*OtherOpIdx*/1,
        // MIs[3] src0
        GIM_CheckIsSameOperand, /*MI*/3, /*OpIdx*/2, /*OtherMI*/1, /*OtherOpIdx*/2,
        GIM_CheckIsSafeToFold, /*InsnID*/1,
        GIM_CheckIsSafeToFold, /*InsnID*/2,
        GIM_CheckIsSafeToFold, /*InsnID*/3,
        // (umax:{ *:[i32] } (umin:{ *:[i32] } i32:{ *:[i32] }:$src1, i32:{ *:[i32] }:$src0), (umin:{ *:[i32] } (umax:{ *:[i32] } i32:{ *:[i32] }:$src1, i32:{ *:[i32] }:$src0), i32:{ *:[i32] }:$src2))  =>  (V_MED3_U32_e64:{ *:[i32] } VSrc_b32:{ *:[i32] }:$src0, VSrc_b32:{ *:[i32] }:$src1, VSrc_b32:{ *:[i32] }:$src2)
        GIR_BuildMI, /*InsnID*/0, /*Opcode*/GIMT_Encode2(AMDGPU::V_MED3_U32_e64),
        GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/0, // DstI[vdst]
        GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/1, /*OpIdx*/2, // src0
        GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/1, /*OpIdx*/1, // src1
        GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/2, /*OpIdx*/2, // src2
        GIR_ConstrainSelectedInstOperands, /*InsnID*/0,
        GIR_EraseFromParent, /*InsnID*/0,
        // GIR_Coverage, 9989,
        GIR_Done,
      // Label 5417: @400820
      GIM_Try, /*On fail goto*//*Label 5418*/ GIMT_Encode4(400911), // Rule ID 9986 //
        GIM_CheckRegBankForClass, /*MI*/0, /*Op*/0, /*RC*/GIMT_Encode2(AMDGPU::VGPR_32RegClassID),
        GIM_RecordInsn, /*DefineMI*/1, /*MI*/0, /*OpIdx*/1, // MIs[1]
        GIM_CheckOpcode, /*MI*/1, GIMT_Encode2(TargetOpcode::G_UMIN),
        GIM_CheckType, /*MI*/1, /*Op*/1, /*Type*/GILLT_s32,
        GIM_CheckType, /*MI*/1, /*Op*/2, /*Type*/GILLT_s32,
        GIM_RecordInsn, /*DefineMI*/2, /*MI*/0, /*OpIdx*/2, // MIs[2]
        GIM_CheckOpcode, /*MI*/2, GIMT_Encode2(TargetOpcode::G_UMIN),
        GIM_CheckType, /*MI*/2, /*Op*/1, /*Type*/GILLT_s32,
        GIM_CheckType, /*MI*/2, /*Op*/2, /*Type*/GILLT_s32,
        GIM_RecordInsn, /*DefineMI*/3, /*MI*/2, /*OpIdx*/2, // MIs[3]
        GIM_CheckOpcode, /*MI*/3, GIMT_Encode2(TargetOpcode::G_UMAX),
        // MIs[3] src0
        GIM_CheckIsSameOperand, /*MI*/3, /*OpIdx*/1, /*OtherMI*/1, /*OtherOpIdx*/1,
        // MIs[3] src1
        GIM_CheckIsSameOperand, /*MI*/3, /*OpIdx*/2, /*OtherMI*/1, /*OtherOpIdx*/2,
        GIM_CheckIsSafeToFold, /*InsnID*/1,
        GIM_CheckIsSafeToFold, /*InsnID*/2,
        GIM_CheckIsSafeToFold, /*InsnID*/3,
        // (umax:{ *:[i32] } (umin:{ *:[i32] } i32:{ *:[i32] }:$src0, i32:{ *:[i32] }:$src1), (umin:{ *:[i32] } i32:{ *:[i32] }:$src2, (umax:{ *:[i32] } i32:{ *:[i32] }:$src0, i32:{ *:[i32] }:$src1)))  =>  (V_MED3_U32_e64:{ *:[i32] } VSrc_b32:{ *:[i32] }:$src0, VSrc_b32:{ *:[i32] }:$src1, VSrc_b32:{ *:[i32] }:$src2)
        GIR_BuildMI, /*InsnID*/0, /*Opcode*/GIMT_Encode2(AMDGPU::V_MED3_U32_e64),
        GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/0, // DstI[vdst]
        GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/1, /*OpIdx*/1, // src0
        GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/1, /*OpIdx*/2, // src1
        GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/2, /*OpIdx*/1, // src2
        GIR_ConstrainSelectedInstOperands, /*InsnID*/0,
        GIR_EraseFromParent, /*InsnID*/0,
        // GIR_Coverage, 9986,
        GIR_Done,
      // Label 5418: @400911
      GIM_Try, /*On fail goto*//*Label 5419*/ GIMT_Encode4(401002), // Rule ID 9987 //
        GIM_CheckRegBankForClass, /*MI*/0, /*Op*/0, /*RC*/GIMT_Encode2(AMDGPU::VGPR_32RegClassID),
        GIM_RecordInsn, /*DefineMI*/1, /*MI*/0, /*OpIdx*/1, // MIs[1]
        GIM_CheckOpcode, /*MI*/1, GIMT_Encode2(TargetOpcode::G_UMIN),
        GIM_CheckType, /*MI*/1, /*Op*/1, /*Type*/GILLT_s32,
        GIM_CheckType, /*MI*/1, /*Op*/2, /*Type*/GILLT_s32,
        GIM_RecordInsn, /*DefineMI*/2, /*MI*/0, /*OpIdx*/2, // MIs[2]
        GIM_CheckOpcode, /*MI*/2, GIMT_Encode2(TargetOpcode::G_UMIN),
        GIM_CheckType, /*MI*/2, /*Op*/1, /*Type*/GILLT_s32,
        GIM_CheckType, /*MI*/2, /*Op*/2, /*Type*/GILLT_s32,
        GIM_RecordInsn, /*DefineMI*/3, /*MI*/2, /*OpIdx*/2, // MIs[3]
        GIM_CheckOpcode, /*MI*/3, GIMT_Encode2(TargetOpcode::G_UMAX),
        // MIs[3] src1
        GIM_CheckIsSameOperand, /*MI*/3, /*OpIdx*/1, /*OtherMI*/1, /*OtherOpIdx*/2,
        // MIs[3] src0
        GIM_CheckIsSameOperand, /*MI*/3, /*OpIdx*/2, /*OtherMI*/1, /*OtherOpIdx*/1,
        GIM_CheckIsSafeToFold, /*InsnID*/1,
        GIM_CheckIsSafeToFold, /*InsnID*/2,
        GIM_CheckIsSafeToFold, /*InsnID*/3,
        // (umax:{ *:[i32] } (umin:{ *:[i32] } i32:{ *:[i32] }:$src0, i32:{ *:[i32] }:$src1), (umin:{ *:[i32] } i32:{ *:[i32] }:$src2, (umax:{ *:[i32] } i32:{ *:[i32] }:$src1, i32:{ *:[i32] }:$src0)))  =>  (V_MED3_U32_e64:{ *:[i32] } VSrc_b32:{ *:[i32] }:$src0, VSrc_b32:{ *:[i32] }:$src1, VSrc_b32:{ *:[i32] }:$src2)
        GIR_BuildMI, /*InsnID*/0, /*Opcode*/GIMT_Encode2(AMDGPU::V_MED3_U32_e64),
        GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/0, // DstI[vdst]
        GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/1, /*OpIdx*/1, // src0
        GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/1, /*OpIdx*/2, // src1
        GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/2, /*OpIdx*/1, // src2
        GIR_ConstrainSelectedInstOperands, /*InsnID*/0,
        GIR_EraseFromParent, /*InsnID*/0,
        // GIR_Coverage, 9987,
        GIR_Done,
      // Label 5419: @401002
      GIM_Try, /*On fail goto*//*Label 5420*/ GIMT_Encode4(401093), // Rule ID 9990 //
        GIM_CheckRegBankForClass, /*MI*/0, /*Op*/0, /*RC*/GIMT_Encode2(AMDGPU::VGPR_32RegClassID),
        GIM_RecordInsn, /*DefineMI*/1, /*MI*/0, /*OpIdx*/1, // MIs[1]
        GIM_CheckOpcode, /*MI*/1, GIMT_Encode2(TargetOpcode::G_UMIN),
        GIM_CheckType, /*MI*/1, /*Op*/1, /*Type*/GILLT_s32,
        GIM_CheckType, /*MI*/1, /*Op*/2, /*Type*/GILLT_s32,
        GIM_RecordInsn, /*DefineMI*/2, /*MI*/0, /*OpIdx*/2, // MIs[2]
        GIM_CheckOpcode, /*MI*/2, GIMT_Encode2(TargetOpcode::G_UMIN),
        GIM_CheckType, /*MI*/2, /*Op*/1, /*Type*/GILLT_s32,
        GIM_CheckType, /*MI*/2, /*Op*/2, /*Type*/GILLT_s32,
        GIM_RecordInsn, /*DefineMI*/3, /*MI*/2, /*OpIdx*/2, // MIs[3]
        GIM_CheckOpcode, /*MI*/3, GIMT_Encode2(TargetOpcode::G_UMAX),
        // MIs[3] src0
        GIM_CheckIsSameOperand, /*MI*/3, /*OpIdx*/1, /*OtherMI*/1, /*OtherOpIdx*/2,
        // MIs[3] src1
        GIM_CheckIsSameOperand, /*MI*/3, /*OpIdx*/2, /*OtherMI*/1, /*OtherOpIdx*/1,
        GIM_CheckIsSafeToFold, /*InsnID*/1,
        GIM_CheckIsSafeToFold, /*InsnID*/2,
        GIM_CheckIsSafeToFold, /*InsnID*/3,
        // (umax:{ *:[i32] } (umin:{ *:[i32] } i32:{ *:[i32] }:$src1, i32:{ *:[i32] }:$src0), (umin:{ *:[i32] } i32:{ *:[i32] }:$src2, (umax:{ *:[i32] } i32:{ *:[i32] }:$src0, i32:{ *:[i32] }:$src1)))  =>  (V_MED3_U32_e64:{ *:[i32] } VSrc_b32:{ *:[i32] }:$src0, VSrc_b32:{ *:[i32] }:$src1, VSrc_b32:{ *:[i32] }:$src2)
        GIR_BuildMI, /*InsnID*/0, /*Opcode*/GIMT_Encode2(AMDGPU::V_MED3_U32_e64),
        GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/0, // DstI[vdst]
        GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/1, /*OpIdx*/2, // src0
        GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/1, /*OpIdx*/1, // src1
        GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/2, /*OpIdx*/1, // src2
        GIR_ConstrainSelectedInstOperands, /*InsnID*/0,
        GIR_EraseFromParent, /*InsnID*/0,
        // GIR_Coverage, 9990,
        GIR_Done,
      // Label 5420: @401093
      GIM_Try, /*On fail goto*//*Label 5421*/ GIMT_Encode4(401184), // Rule ID 9991 //
        GIM_CheckRegBankForClass, /*MI*/0, /*Op*/0, /*RC*/GIMT_Encode2(AMDGPU::VGPR_32RegClassID),
        GIM_RecordInsn, /*DefineMI*/1, /*MI*/0, /*OpIdx*/1, // MIs[1]
        GIM_CheckOpcode, /*MI*/1, GIMT_Encode2(TargetOpcode::G_UMIN),
        GIM_CheckType, /*MI*/1, /*Op*/1, /*Type*/GILLT_s32,
        GIM_CheckType, /*MI*/1, /*Op*/2, /*Type*/GILLT_s32,
        GIM_RecordInsn, /*DefineMI*/2, /*MI*/0, /*OpIdx*/2, // MIs[2]
        GIM_CheckOpcode, /*MI*/2, GIMT_Encode2(TargetOpcode::G_UMIN),
        GIM_CheckType, /*MI*/2, /*Op*/1, /*Type*/GILLT_s32,
        GIM_CheckType, /*MI*/2, /*Op*/2, /*Type*/GILLT_s32,
        GIM_RecordInsn, /*DefineMI*/3, /*MI*/2, /*OpIdx*/2, // MIs[3]
        GIM_CheckOpcode, /*MI*/3, GIMT_Encode2(TargetOpcode::G_UMAX),
        // MIs[3] src1
        GIM_CheckIsSameOperand, /*MI*/3, /*OpIdx*/1, /*OtherMI*/1, /*OtherOpIdx*/1,
        // MIs[3] src0
        GIM_CheckIsSameOperand, /*MI*/3, /*OpIdx*/2, /*OtherMI*/1, /*OtherOpIdx*/2,
        GIM_CheckIsSafeToFold, /*InsnID*/1,
        GIM_CheckIsSafeToFold, /*InsnID*/2,
        GIM_CheckIsSafeToFold, /*InsnID*/3,
        // (umax:{ *:[i32] } (umin:{ *:[i32] } i32:{ *:[i32] }:$src1, i32:{ *:[i32] }:$src0), (umin:{ *:[i32] } i32:{ *:[i32] }:$src2, (umax:{ *:[i32] } i32:{ *:[i32] }:$src1, i32:{ *:[i32] }:$src0)))  =>  (V_MED3_U32_e64:{ *:[i32] } VSrc_b32:{ *:[i32] }:$src0, VSrc_b32:{ *:[i32] }:$src1, VSrc_b32:{ *:[i32] }:$src2)
        GIR_BuildMI, /*InsnID*/0, /*Opcode*/GIMT_Encode2(AMDGPU::V_MED3_U32_e64),
        GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/0, // DstI[vdst]
        GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/1, /*OpIdx*/2, // src0
        GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/1, /*OpIdx*/1, // src1
        GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/2, /*OpIdx*/1, // src2
        GIR_ConstrainSelectedInstOperands, /*InsnID*/0,
        GIR_EraseFromParent, /*InsnID*/0,
        // GIR_Coverage, 9991,
        GIR_Done,
      // Label 5421: @401184
      GIM_Try, /*On fail goto*//*Label 5422*/ GIMT_Encode4(401248), // Rule ID 6519 //
        GIM_CheckFeatures, GIMT_Encode2(GIFBS_isGFX11Plus),
        GIM_CheckRegBankForClass, /*MI*/0, /*Op*/0, /*RC*/GIMT_Encode2(AMDGPU::VGPR_32RegClassID),
        GIM_RecordInsn, /*DefineMI*/1, /*MI*/0, /*OpIdx*/1, // MIs[1]
        GIM_CheckOpcode, /*MI*/1, GIMT_Encode2(TargetOpcode::G_UMIN),
        GIM_CheckType, /*MI*/1, /*Op*/1, /*Type*/GILLT_s32,
        GIM_CheckType, /*MI*/1, /*Op*/2, /*Type*/GILLT_s32,
        GIM_CheckCxxInsnPredicate, /*MI*/1, /*FnId*/GIMT_Encode2(GICXXPred_MI_Predicate_umin_oneuse),
        GIM_CheckCxxInsnPredicate, /*MI*/0, /*FnId*/GIMT_Encode2(GICXXPred_MI_Predicate_anonymous_35370),
        GIM_CheckIsSafeToFold, /*InsnID*/1,
        // (umax:{ *:[i32] } (umin:{ *:[i32] } i32:{ *:[i32] }:$src0, i32:{ *:[i32] }:$src1)<<P:Predicate_umin_oneuse>>, i32:{ *:[i32] }:$src2)<<P:Predicate_anonymous_35370>>  =>  (V_MINMAX_U32_e64:{ *:[i32] } VSrc_b32:{ *:[i32] }:$src0, VSrc_b32:{ *:[i32] }:$src1, VSrc_b32:{ *:[i32] }:$src2)
        GIR_BuildMI, /*InsnID*/0, /*Opcode*/GIMT_Encode2(AMDGPU::V_MINMAX_U32_e64),
        GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/0, // DstI[vdst]
        GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/1, /*OpIdx*/1, // src0
        GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/1, /*OpIdx*/2, // src1
        GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/2, // src2
        GIR_ConstrainSelectedInstOperands, /*InsnID*/0,
        GIR_EraseFromParent, /*InsnID*/0,
        // GIR_Coverage, 6519,
        GIR_Done,
      // Label 5422: @401248
      GIM_Try, /*On fail goto*//*Label 5423*/ GIMT_Encode4(401312), // Rule ID 10513 //
        GIM_CheckFeatures, GIMT_Encode2(GIFBS_isGFX11Plus),
        GIM_CheckRegBankForClass, /*MI*/0, /*Op*/0, /*RC*/GIMT_Encode2(AMDGPU::VGPR_32RegClassID),
        GIM_RecordInsn, /*DefineMI*/1, /*MI*/0, /*OpIdx*/2, // MIs[1]
        GIM_CheckOpcode, /*MI*/1, GIMT_Encode2(TargetOpcode::G_UMIN),
        GIM_CheckType, /*MI*/1, /*Op*/1, /*Type*/GILLT_s32,
        GIM_CheckType, /*MI*/1, /*Op*/2, /*Type*/GILLT_s32,
        GIM_CheckCxxInsnPredicate, /*MI*/1, /*FnId*/GIMT_Encode2(GICXXPred_MI_Predicate_umin_oneuse),
        GIM_CheckCxxInsnPredicate, /*MI*/0, /*FnId*/GIMT_Encode2(GICXXPred_MI_Predicate_anonymous_35370),
        GIM_CheckIsSafeToFold, /*InsnID*/1,
        // (umax:{ *:[i32] } i32:{ *:[i32] }:$src2, (umin:{ *:[i32] } i32:{ *:[i32] }:$src0, i32:{ *:[i32] }:$src1)<<P:Predicate_umin_oneuse>>)<<P:Predicate_anonymous_35370>>  =>  (V_MINMAX_U32_e64:{ *:[i32] } VSrc_b32:{ *:[i32] }:$src0, VSrc_b32:{ *:[i32] }:$src1, VSrc_b32:{ *:[i32] }:$src2)
        GIR_BuildMI, /*InsnID*/0, /*Opcode*/GIMT_Encode2(AMDGPU::V_MINMAX_U32_e64),
        GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/0, // DstI[vdst]
        GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/1, /*OpIdx*/1, // src0
        GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/1, /*OpIdx*/2, // src1
        GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/1, // src2
        GIR_ConstrainSelectedInstOperands, /*InsnID*/0,
        GIR_EraseFromParent, /*InsnID*/0,
        // GIR_Coverage, 10513,
        GIR_Done,
      // Label 5423: @401312
      GIM_Try, /*On fail goto*//*Label 5424*/ GIMT_Encode4(401340), // Rule ID 52 //
        GIM_CheckRegBankForClass, /*MI*/0, /*Op*/0, /*RC*/GIMT_Encode2(AMDGPU::SReg_32RegClassID),
        GIM_CheckCxxInsnPredicate, /*MI*/0, /*FnId*/GIMT_Encode2(GICXXPred_MI_Predicate_anonymous_17610),
        // (umax:{ *:[i32] } i32:{ *:[i32] }:$src0, i32:{ *:[i32] }:$src1)<<P:Predicate_anonymous_17610>>  =>  (S_MAX_U32:{ *:[i32] }:{ *:[i1] } i32:{ *:[i32] }:$src0, i32:{ *:[i32] }:$src1)
        GIR_MutateOpcode, /*InsnID*/0, /*RecycleInsnID*/0, /*Opcode*/GIMT_Encode2(AMDGPU::S_MAX_U32),
        GIR_AddImplicitDef, /*InsnID*/0, GIMT_Encode2(AMDGPU::SCC), GIMT_Encode2(RegState::Dead),
        GIR_ConstrainSelectedInstOperands, /*InsnID*/0,
        // GIR_Coverage, 52,
        GIR_Done,
      // Label 5424: @401340
      GIM_Try, /*On fail goto*//*Label 5425*/ GIMT_Encode4(401362), // Rule ID 746 //
        GIM_CheckRegBankForClass, /*MI*/0, /*Op*/0, /*RC*/GIMT_Encode2(AMDGPU::VGPR_32RegClassID),
        // (umax:{ *:[i32] } i32:{ *:[i32] }:$src0, i32:{ *:[i32] }:$src1)  =>  (V_MAX_U32_e64:{ *:[i32] } i32:{ *:[i32] }:$src0, i32:{ *:[i32] }:$src1)
        GIR_MutateOpcode, /*InsnID*/0, /*RecycleInsnID*/0, /*Opcode*/GIMT_Encode2(AMDGPU::V_MAX_U32_e64),
        GIR_AddImplicitUse, /*InsnID*/0, GIMT_Encode2(AMDGPU::EXEC),
        GIR_ConstrainSelectedInstOperands, /*InsnID*/0,
        // GIR_Coverage, 746,
        GIR_Done,
      // Label 5425: @401362
      GIM_Reject,
    // Label 5405: @401363
    GIM_Reject,
    // Label 5384: @401364
    GIM_Try, /*On fail goto*//*Label 5426*/ GIMT_Encode4(401444), // Rule ID 973 //
      GIM_CheckType, /*MI*/0, /*Op*/1, /*Type*/GILLT_v2s16,
      GIM_CheckType, /*MI*/0, /*Op*/2, /*Type*/GILLT_v2s16,
      GIM_CheckRegBankForClass, /*MI*/0, /*Op*/0, /*RC*/GIMT_Encode2(AMDGPU::VGPR_32RegClassID),
      GIM_CheckComplexPattern, /*MI*/0, /*Op*/1, /*Renderer*/GIMT_Encode2(0), GIMT_Encode2(GICP_gi_vop3pmods),
      GIM_CheckComplexPattern, /*MI*/0, /*Op*/2, /*Renderer*/GIMT_Encode2(1), GIMT_Encode2(GICP_gi_vop3pmods),
      // (umax:{ *:[v2i16] } (VOP3PMods:{ *:[v2i16] } v2i16:{ *:[v2i16] }:$src0, i32:{ *:[i32] }:$src0_modifiers), (VOP3PMods:{ *:[v2i16] } v2i16:{ *:[v2i16] }:$src1, i32:{ *:[i32] }:$src1_modifiers))  =>  (V_PK_MAX_U16:{ *:[v2i16] } i32:{ *:[i32] }:$src0_modifiers, v2i16:{ *:[v2i16] }:$src0, i32:{ *:[i32] }:$src1_modifiers, v2i16:{ *:[v2i16] }:$src1)
      GIR_BuildMI, /*InsnID*/0, /*Opcode*/GIMT_Encode2(AMDGPU::V_PK_MAX_U16),
      GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/0, // DstI[vdst]
      GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/1, // src0_modifiers
      GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/0, // src0
      GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(1), /*SubOperand*/1, // src1_modifiers
      GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(1), /*SubOperand*/0, // src1
      GIR_AddImm8, /*InsnID*/0, /*Imm*/0,
      GIR_AddImm8, /*InsnID*/0, /*Imm*/0,
      GIR_AddImm8, /*InsnID*/0, /*Imm*/0,
      GIR_AddImm8, /*InsnID*/0, /*Imm*/0,
      GIR_AddImm8, /*InsnID*/0, /*Imm*/0,
      GIR_ConstrainSelectedInstOperands, /*InsnID*/0,
      GIR_EraseFromParent, /*InsnID*/0,
      // GIR_Coverage, 973,
      GIR_Done,
    // Label 5426: @401444
    GIM_Reject,
    // Label 5385: @401445
    GIM_Reject,
    // Label 88: @401446
    GIM_Try, /*On fail goto*//*Label 5427*/ GIMT_Encode4(401604),
      GIM_CheckType, /*MI*/0, /*Op*/0, /*Type*/GILLT_s32,
      GIM_CheckType, /*MI*/0, /*Op*/1, /*Type*/GILLT_s32,
      GIM_Try, /*On fail goto*//*Label 5428*/ GIMT_Encode4(401517), // Rule ID 6379 //
        GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasAddNoCarryInsts),
        GIM_CheckRegBankForClass, /*MI*/0, /*Op*/0, /*RC*/GIMT_Encode2(AMDGPU::VGPR_32RegClassID),
        GIM_CheckCxxInsnPredicate, /*MI*/0, /*FnId*/GIMT_Encode2(GICXXPred_MI_Predicate_anonymous_35193),
        // (abs:{ *:[i32] } i32:{ *:[i32] }:$src)<<P:Predicate_anonymous_35193>>  =>  (V_MAX_I32_e64:{ *:[i32] } (V_SUB_U32_e32:{ *:[i16] } 0:{ *:[i32] }, ?:{ *:[i32] }:$src), ?:{ *:[i32] }:$src)
        GIR_MakeTempReg, /*TempRegID*/0, /*TypeID*/GILLT_s16,
        GIR_BuildMI, /*InsnID*/1, /*Opcode*/GIMT_Encode2(AMDGPU::V_SUB_U32_e32),
        GIR_AddTempRegister, /*InsnID*/1, /*TempRegID*/0, /*TempRegFlags*/GIMT_Encode2(RegState::Define),
        GIR_AddImm8, /*InsnID*/1, /*Imm*/0,
        GIR_Copy, /*NewInsnID*/1, /*OldInsnID*/0, /*OpIdx*/1, // src
        GIR_ConstrainSelectedInstOperands, /*InsnID*/1,
        GIR_BuildMI, /*InsnID*/0, /*Opcode*/GIMT_Encode2(AMDGPU::V_MAX_I32_e64),
        GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/0, // DstI[vdst]
        GIR_AddSimpleTempRegister, /*InsnID*/0, /*TempRegID*/0,
        GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/1, // src
        GIR_ConstrainSelectedInstOperands, /*InsnID*/0,
        GIR_EraseFromParent, /*InsnID*/0,
        // GIR_Coverage, 6379,
        GIR_Done,
      // Label 5428: @401517
      GIM_Try, /*On fail goto*//*Label 5429*/ GIMT_Encode4(401545), // Rule ID 23 //
        GIM_CheckRegBankForClass, /*MI*/0, /*Op*/0, /*RC*/GIMT_Encode2(AMDGPU::SReg_32RegClassID),
        GIM_CheckCxxInsnPredicate, /*MI*/0, /*FnId*/GIMT_Encode2(GICXXPred_MI_Predicate_anonymous_17577),
        // (abs:{ *:[i32] } i32:{ *:[i32] }:$src0)<<P:Predicate_anonymous_17577>>  =>  (S_ABS_I32:{ *:[i32] }:{ *:[i1] } i32:{ *:[i32] }:$src0)
        GIR_MutateOpcode, /*InsnID*/0, /*RecycleInsnID*/0, /*Opcode*/GIMT_Encode2(AMDGPU::S_ABS_I32),
        GIR_AddImplicitDef, /*InsnID*/0, GIMT_Encode2(AMDGPU::SCC), GIMT_Encode2(RegState::Dead),
        GIR_ConstrainSelectedInstOperands, /*InsnID*/0,
        // GIR_Coverage, 23,
        GIR_Done,
      // Label 5429: @401545
      GIM_Try, /*On fail goto*//*Label 5430*/ GIMT_Encode4(401603), // Rule ID 6378 //
        GIM_CheckRegBankForClass, /*MI*/0, /*Op*/0, /*RC*/GIMT_Encode2(AMDGPU::VGPR_32RegClassID),
        GIM_CheckCxxInsnPredicate, /*MI*/0, /*FnId*/GIMT_Encode2(GICXXPred_MI_Predicate_anonymous_35193),
        // (abs:{ *:[i32] } i32:{ *:[i32] }:$src)<<P:Predicate_anonymous_35193>>  =>  (V_MAX_I32_e64:{ *:[i32] } (V_SUB_CO_U32_e32:{ *:[i16] } 0:{ *:[i32] }, ?:{ *:[i32] }:$src), ?:{ *:[i32] }:$src)
        GIR_MakeTempReg, /*TempRegID*/0, /*TypeID*/GILLT_s16,
        GIR_BuildMI, /*InsnID*/1, /*Opcode*/GIMT_Encode2(AMDGPU::V_SUB_CO_U32_e32),
        GIR_AddTempRegister, /*InsnID*/1, /*TempRegID*/0, /*TempRegFlags*/GIMT_Encode2(RegState::Define),
        GIR_AddImm8, /*InsnID*/1, /*Imm*/0,
        GIR_Copy, /*NewInsnID*/1, /*OldInsnID*/0, /*OpIdx*/1, // src
        GIR_SetImplicitDefDead, /*InsnID*/1, /*OpIdx for AMDGPU::VCC*/0,
        GIR_ConstrainSelectedInstOperands, /*InsnID*/1,
        GIR_BuildMI, /*InsnID*/0, /*Opcode*/GIMT_Encode2(AMDGPU::V_MAX_I32_e64),
        GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/0, // DstI[vdst]
        GIR_AddSimpleTempRegister, /*InsnID*/0, /*TempRegID*/0,
        GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/1, // src
        GIR_ConstrainSelectedInstOperands, /*InsnID*/0,
        GIR_EraseFromParent, /*InsnID*/0,
        // GIR_Coverage, 6378,
        GIR_Done,
      // Label 5430: @401603
      GIM_Reject,
    // Label 5427: @401604
    GIM_Reject,
    // Label 89: @401605
    GIM_Try, /*On fail goto*//*Label 5431*/ GIMT_Encode4(401640),
      GIM_CheckIsMBB, /*MI*/0, /*Op*/0,
      GIM_Try, /*On fail goto*//*Label 5432*/ GIMT_Encode4(401626), // Rule ID 181 //
        // (br (bb:{ *:[Other] }):$simm16)  =>  (S_BRANCH (bb:{ *:[Other] }):$simm16)
        GIR_MutateOpcode, /*InsnID*/0, /*RecycleInsnID*/0, /*Opcode*/GIMT_Encode2(AMDGPU::S_BRANCH),
        GIR_ConstrainSelectedInstOperands, /*InsnID*/0,
        // GIR_Coverage, 181,
        GIR_Done,
      // Label 5432: @401626
      GIM_Try, /*On fail goto*//*Label 5433*/ GIMT_Encode4(401639), // Rule ID 182 //
        // (br (bb:{ *:[Other] }):$simm16)  =>  (S_BRANCH_pad_s_nop (bb:{ *:[Other] }):$simm16)
        GIR_MutateOpcode, /*InsnID*/0, /*RecycleInsnID*/0, /*Opcode*/GIMT_Encode2(AMDGPU::S_BRANCH_pad_s_nop),
        GIR_ConstrainSelectedInstOperands, /*InsnID*/0,
        // GIR_Coverage, 182,
        GIR_Done,
      // Label 5433: @401639
      GIM_Reject,
    // Label 5431: @401640
    GIM_Reject,
    // Label 90: @401641
    GIM_Try, /*On fail goto*//*Label 5434*/ GIMT_Encode4(401751),
      GIM_CheckType, /*MI*/0, /*Op*/0, /*Type*/GILLT_s32,
      GIM_SwitchType, /*MI*/0, /*Op*/1, /*[*/GIMT_Encode2(9), GIMT_Encode2(11), /*)*//*default:*//*Label 5437*/ GIMT_Encode4(401750),
      /*GILLT_s32*//*Label 5435*/ GIMT_Encode4(401669),
      /*GILLT_s64*//*Label 5436*/ GIMT_Encode4(401727),
      // Label 5435: @401669
      GIM_Try, /*On fail goto*//*Label 5438*/ GIMT_Encode4(401691), // Rule ID 10 //
        GIM_CheckRegBankForClass, /*MI*/0, /*Op*/0, /*RC*/GIMT_Encode2(AMDGPU::SReg_32RegClassID),
        GIM_CheckCxxInsnPredicate, /*MI*/0, /*FnId*/GIMT_Encode2(GICXXPred_MI_Predicate_anonymous_17569),
        // (cttz_zero_undef:{ *:[i32] } i32:{ *:[i32] }:$src0)<<P:Predicate_anonymous_17569>>  =>  (S_FF1_I32_B32:{ *:[i32] } i32:{ *:[i32] }:$src0)
        GIR_MutateOpcode, /*InsnID*/0, /*RecycleInsnID*/0, /*Opcode*/GIMT_Encode2(AMDGPU::S_FF1_I32_B32),
        GIR_ConstrainSelectedInstOperands, /*InsnID*/0,
        // GIR_Coverage, 10,
        GIR_Done,
      // Label 5438: @401691
      GIM_Try, /*On fail goto*//*Label 5439*/ GIMT_Encode4(401726), // Rule ID 627 //
        GIM_CheckRegBankForClass, /*MI*/0, /*Op*/0, /*RC*/GIMT_Encode2(AMDGPU::VGPR_32RegClassID),
        GIM_CheckComplexPattern, /*MI*/0, /*Op*/1, /*Renderer*/GIMT_Encode2(0), GIMT_Encode2(GICP_gi_vop3mods0),
        // (cttz_zero_undef:{ *:[i32] } (VOP3Mods0:{ *:[i32] } i32:{ *:[i32] }:$src0))  =>  (V_FFBL_B32_e64:{ *:[i32] } i32:{ *:[i32] }:$src0)
        GIR_BuildMI, /*InsnID*/0, /*Opcode*/GIMT_Encode2(AMDGPU::V_FFBL_B32_e64),
        GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/0, // DstI[vdst]
        GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/0, // src0
        GIR_ConstrainSelectedInstOperands, /*InsnID*/0,
        GIR_EraseFromParent, /*InsnID*/0,
        // GIR_Coverage, 627,
        GIR_Done,
      // Label 5439: @401726
      GIM_Reject,
      // Label 5436: @401727
      GIM_Try, /*On fail goto*//*Label 5440*/ GIMT_Encode4(401749), // Rule ID 8 //
        GIM_CheckRegBankForClass, /*MI*/0, /*Op*/0, /*RC*/GIMT_Encode2(AMDGPU::SReg_32RegClassID),
        GIM_CheckCxxInsnPredicate, /*MI*/0, /*FnId*/GIMT_Encode2(GICXXPred_MI_Predicate_anonymous_17569),
        // (cttz_zero_undef:{ *:[i32] } i64:{ *:[i64] }:$src0)<<P:Predicate_anonymous_17569>>  =>  (S_FF1_I32_B64:{ *:[i32] } i64:{ *:[i64] }:$src0)
        GIR_MutateOpcode, /*InsnID*/0, /*RecycleInsnID*/0, /*Opcode*/GIMT_Encode2(AMDGPU::S_FF1_I32_B64),
        GIR_ConstrainSelectedInstOperands, /*InsnID*/0,
        // GIR_Coverage, 8,
        GIR_Done,
      // Label 5440: @401749
      GIM_Reject,
      // Label 5437: @401750
      GIM_Reject,
    // Label 5434: @401751
    GIM_Reject,
    // Label 91: @401752
    GIM_Try, /*On fail goto*//*Label 5441*/ GIMT_Encode4(401866),
      GIM_CheckType, /*MI*/0, /*Op*/0, /*Type*/GILLT_s32,
      GIM_SwitchType, /*MI*/0, /*Op*/1, /*[*/GIMT_Encode2(9), GIMT_Encode2(11), /*)*//*default:*//*Label 5444*/ GIMT_Encode4(401826),
      /*GILLT_s32*//*Label 5442*/ GIMT_Encode4(401780),
      /*GILLT_s64*//*Label 5443*/ GIMT_Encode4(401803),
      // Label 5442: @401780
      GIM_Try, /*On fail goto*//*Label 5445*/ GIMT_Encode4(401802), // Rule ID 12 //
        GIM_CheckRegBankForClass, /*MI*/0, /*Op*/0, /*RC*/GIMT_Encode2(AMDGPU::SReg_32RegClassID),
        GIM_CheckCxxInsnPredicate, /*MI*/0, /*FnId*/GIMT_Encode2(GICXXPred_MI_Predicate_anonymous_17570),
        // (ctlz_zero_undef:{ *:[i32] } i32:{ *:[i32] }:$src0)<<P:Predicate_anonymous_17570>>  =>  (S_FLBIT_I32_B32:{ *:[i32] } i32:{ *:[i32] }:$src0)
        GIR_MutateOpcode, /*InsnID*/0, /*RecycleInsnID*/0, /*Opcode*/GIMT_Encode2(AMDGPU::S_FLBIT_I32_B32),
        GIR_ConstrainSelectedInstOperands, /*InsnID*/0,
        // GIR_Coverage, 12,
        GIR_Done,
      // Label 5445: @401802
      GIM_Reject,
      // Label 5443: @401803
      GIM_Try, /*On fail goto*//*Label 5446*/ GIMT_Encode4(401825), // Rule ID 14 //
        GIM_CheckRegBankForClass, /*MI*/0, /*Op*/0, /*RC*/GIMT_Encode2(AMDGPU::SReg_32RegClassID),
        GIM_CheckCxxInsnPredicate, /*MI*/0, /*FnId*/GIMT_Encode2(GICXXPred_MI_Predicate_anonymous_17570),
        // (ctlz_zero_undef:{ *:[i32] } i64:{ *:[i64] }:$src0)<<P:Predicate_anonymous_17570>>  =>  (S_FLBIT_I32_B64:{ *:[i32] } i64:{ *:[i64] }:$src0)
        GIR_MutateOpcode, /*InsnID*/0, /*RecycleInsnID*/0, /*Opcode*/GIMT_Encode2(AMDGPU::S_FLBIT_I32_B64),
        GIR_ConstrainSelectedInstOperands, /*InsnID*/0,
        // GIR_Coverage, 14,
        GIR_Done,
      // Label 5446: @401825
      GIM_Reject,
      // Label 5444: @401826
      GIM_Try, /*On fail goto*//*Label 5447*/ GIMT_Encode4(401865), // Rule ID 625 //
        GIM_CheckType, /*MI*/0, /*Op*/1, /*Type*/GILLT_s32,
        GIM_CheckRegBankForClass, /*MI*/0, /*Op*/0, /*RC*/GIMT_Encode2(AMDGPU::VGPR_32RegClassID),
        GIM_CheckComplexPattern, /*MI*/0, /*Op*/1, /*Renderer*/GIMT_Encode2(0), GIMT_Encode2(GICP_gi_vop3mods0),
        // (ctlz_zero_undef:{ *:[i32] } (VOP3Mods0:{ *:[i32] } i32:{ *:[i32] }:$src0))  =>  (V_FFBH_U32_e64:{ *:[i32] } i32:{ *:[i32] }:$src0)
        GIR_BuildMI, /*InsnID*/0, /*Opcode*/GIMT_Encode2(AMDGPU::V_FFBH_U32_e64),
        GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/0, // DstI[vdst]
        GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/0, // src0
        GIR_ConstrainSelectedInstOperands, /*InsnID*/0,
        GIR_EraseFromParent, /*InsnID*/0,
        // GIR_Coverage, 625,
        GIR_Done,
      // Label 5447: @401865
      GIM_Reject,
    // Label 5441: @401866
    GIM_Reject,
    // Label 92: @401867
    GIM_Try, /*On fail goto*//*Label 5448*/ GIMT_Encode4(401992),
      GIM_CheckType, /*MI*/0, /*Op*/0, /*Type*/GILLT_s32,
      GIM_SwitchType, /*MI*/0, /*Op*/1, /*[*/GIMT_Encode2(9), GIMT_Encode2(11), /*)*//*default:*//*Label 5451*/ GIMT_Encode4(401953),
      /*GILLT_s32*//*Label 5449*/ GIMT_Encode4(401895),
      /*GILLT_s64*//*Label 5450*/ GIMT_Encode4(401924),
      // Label 5449: @401895
      GIM_Try, /*On fail goto*//*Label 5452*/ GIMT_Encode4(401923), // Rule ID 6 //
        GIM_CheckRegBankForClass, /*MI*/0, /*Op*/0, /*RC*/GIMT_Encode2(AMDGPU::SReg_32RegClassID),
        GIM_CheckCxxInsnPredicate, /*MI*/0, /*FnId*/GIMT_Encode2(GICXXPred_MI_Predicate_anonymous_17568),
        // (ctpop:{ *:[i32] } i32:{ *:[i32] }:$src0)<<P:Predicate_anonymous_17568>>  =>  (S_BCNT1_I32_B32:{ *:[i32] }:{ *:[i1] } i32:{ *:[i32] }:$src0)
        GIR_MutateOpcode, /*InsnID*/0, /*RecycleInsnID*/0, /*Opcode*/GIMT_Encode2(AMDGPU::S_BCNT1_I32_B32),
        GIR_AddImplicitDef, /*InsnID*/0, GIMT_Encode2(AMDGPU::SCC), GIMT_Encode2(RegState::Dead),
        GIR_ConstrainSelectedInstOperands, /*InsnID*/0,
        // GIR_Coverage, 6,
        GIR_Done,
      // Label 5452: @401923
      GIM_Reject,
      // Label 5450: @401924
      GIM_Try, /*On fail goto*//*Label 5453*/ GIMT_Encode4(401952), // Rule ID 7 //
        GIM_CheckRegBankForClass, /*MI*/0, /*Op*/0, /*RC*/GIMT_Encode2(AMDGPU::SReg_32RegClassID),
        GIM_CheckCxxInsnPredicate, /*MI*/0, /*FnId*/GIMT_Encode2(GICXXPred_MI_Predicate_anonymous_17568),
        // (ctpop:{ *:[i32] } i64:{ *:[i64] }:$src0)<<P:Predicate_anonymous_17568>>  =>  (S_BCNT1_I32_B64:{ *:[i32] }:{ *:[i1] } i64:{ *:[i64] }:$src0)
        GIR_MutateOpcode, /*InsnID*/0, /*RecycleInsnID*/0, /*Opcode*/GIMT_Encode2(AMDGPU::S_BCNT1_I32_B64),
        GIR_AddImplicitDef, /*InsnID*/0, GIMT_Encode2(AMDGPU::SCC), GIMT_Encode2(RegState::Dead),
        GIR_ConstrainSelectedInstOperands, /*InsnID*/0,
        // GIR_Coverage, 7,
        GIR_Done,
      // Label 5453: @401952
      GIM_Reject,
      // Label 5451: @401953
      GIM_Try, /*On fail goto*//*Label 5454*/ GIMT_Encode4(401991), // Rule ID 5902 //
        GIM_CheckType, /*MI*/0, /*Op*/1, /*Type*/GILLT_s32,
        GIM_CheckRegBankForClass, /*MI*/0, /*Op*/0, /*RC*/GIMT_Encode2(AMDGPU::VGPR_32RegClassID),
        GIM_CheckCxxInsnPredicate, /*MI*/0, /*FnId*/GIMT_Encode2(GICXXPred_MI_Predicate_anonymous_34681),
        // (ctpop:{ *:[i32] } i32:{ *:[i32] }:$popcnt)<<P:Predicate_anonymous_34681>>  =>  (V_BCNT_U32_B32_e64:{ *:[i32] } VSrc_b32:{ *:[i32] }:$popcnt, 0:{ *:[i32] })
        GIR_BuildMI, /*InsnID*/0, /*Opcode*/GIMT_Encode2(AMDGPU::V_BCNT_U32_B32_e64),
        GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/0, // DstI[vdst]
        GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/1, // popcnt
        GIR_AddImm8, /*InsnID*/0, /*Imm*/0,
        GIR_ConstrainSelectedInstOperands, /*InsnID*/0,
        GIR_EraseFromParent, /*InsnID*/0,
        // GIR_Coverage, 5902,
        GIR_Done,
      // Label 5454: @401991
      GIM_Reject,
    // Label 5448: @401992
    GIM_Reject,
    // Label 93: @401993
    GIM_SwitchType, /*MI*/0, /*Op*/0, /*[*/GIMT_Encode2(8), GIMT_Encode2(12), /*)*//*default:*//*Label 5459*/ GIMT_Encode4(402987),
    /*GILLT_s16*//*Label 5455*/ GIMT_Encode4(402020),
    /*GILLT_s32*//*Label 5456*/ GIMT_Encode4(402085),
    /*GILLT_s64*//*Label 5457*/ GIMT_Encode4(402257),
    /*GILLT_v2s16*//*Label 5458*/ GIMT_Encode4(402922),
    // Label 5455: @402020
    GIM_Try, /*On fail goto*//*Label 5460*/ GIMT_Encode4(402084), // Rule ID 6396 //
      GIM_CheckFeatures, GIMT_Encode2(GIFBS_isGFX8Plus),
      GIM_CheckType, /*MI*/0, /*Op*/1, /*Type*/GILLT_s16,
      GIM_CheckRegBankForClass, /*MI*/0, /*Op*/0, /*RC*/GIMT_Encode2(AMDGPU::VGPR_32RegClassID),
      // (bswap:{ *:[i16] } i16:{ *:[i16] }:$a)  =>  (V_PERM_B32_e64:{ *:[i16] } 0:{ *:[i32] }, VSrc_b32:{ *:[i16] }:$a, (S_MOV_B32:{ *:[i16] } 202113025:{ *:[i32] }))
      GIR_MakeTempReg, /*TempRegID*/0, /*TypeID*/GILLT_s16,
      GIR_BuildMI, /*InsnID*/1, /*Opcode*/GIMT_Encode2(AMDGPU::S_MOV_B32),
      GIR_AddTempRegister, /*InsnID*/1, /*TempRegID*/0, /*TempRegFlags*/GIMT_Encode2(RegState::Define),
      GIR_AddImm, /*InsnID*/1, /*Imm*/GIMT_Encode8(202113025),
      GIR_ConstrainSelectedInstOperands, /*InsnID*/1,
      GIR_BuildMI, /*InsnID*/0, /*Opcode*/GIMT_Encode2(AMDGPU::V_PERM_B32_e64),
      GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/0, // DstI[vdst]
      GIR_AddImm8, /*InsnID*/0, /*Imm*/0,
      GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/1, // a
      GIR_AddSimpleTempRegister, /*InsnID*/0, /*TempRegID*/0,
      GIR_ConstrainSelectedInstOperands, /*InsnID*/0,
      GIR_EraseFromParent, /*InsnID*/0,
      // GIR_Coverage, 6396,
      GIR_Done,
    // Label 5460: @402084
    GIM_Reject,
    // Label 5456: @402085
    GIM_Try, /*On fail goto*//*Label 5461*/ GIMT_Encode4(402256),
      GIM_CheckType, /*MI*/0, /*Op*/1, /*Type*/GILLT_s32,
      GIM_CheckRegBankForClass, /*MI*/0, /*Op*/0, /*RC*/GIMT_Encode2(AMDGPU::VGPR_32RegClassID),
      GIM_Try, /*On fail goto*//*Label 5462*/ GIMT_Encode4(402154), // Rule ID 6394 //
        GIM_CheckFeatures, GIMT_Encode2(GIFBS_isGFX8Plus),
        // (bswap:{ *:[i32] } i32:{ *:[i32] }:$a)  =>  (V_PERM_B32_e64:{ *:[i32] } 0:{ *:[i32] }, VSrc_b32:{ *:[i32] }:$a, (S_MOV_B32:{ *:[i16] } 66051:{ *:[i32] }))
        GIR_MakeTempReg, /*TempRegID*/0, /*TypeID*/GILLT_s16,
        GIR_BuildMI, /*InsnID*/1, /*Opcode*/GIMT_Encode2(AMDGPU::S_MOV_B32),
        GIR_AddTempRegister, /*InsnID*/1, /*TempRegID*/0, /*TempRegFlags*/GIMT_Encode2(RegState::Define),
        GIR_AddImm, /*InsnID*/1, /*Imm*/GIMT_Encode8(66051),
        GIR_ConstrainSelectedInstOperands, /*InsnID*/1,
        GIR_BuildMI, /*InsnID*/0, /*Opcode*/GIMT_Encode2(AMDGPU::V_PERM_B32_e64),
        GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/0, // DstI[vdst]
        GIR_AddImm8, /*InsnID*/0, /*Imm*/0,
        GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/1, // a
        GIR_AddSimpleTempRegister, /*InsnID*/0, /*TempRegID*/0,
        GIR_ConstrainSelectedInstOperands, /*InsnID*/0,
        GIR_EraseFromParent, /*InsnID*/0,
        // GIR_Coverage, 6394,
        GIR_Done,
      // Label 5462: @402154
      GIM_Try, /*On fail goto*//*Label 5463*/ GIMT_Encode4(402255), // Rule ID 6392 //
        // (bswap:{ *:[i32] } i32:{ *:[i32] }:$a)  =>  (V_BFI_B32_e64:{ *:[i32] } (S_MOV_B32:{ *:[i16] } 16711935:{ *:[i32] }), (V_ALIGNBIT_B32_e64:{ *:[i16] } VSrc_b32:{ *:[i32] }:$a, VSrc_b32:{ *:[i32] }:$a, 24:{ *:[i32] }), (V_ALIGNBIT_B32_e64:{ *:[i16] } VSrc_b32:{ *:[i32] }:$a, VSrc_b32:{ *:[i32] }:$a, 8:{ *:[i32] }))
        GIR_MakeTempReg, /*TempRegID*/0, /*TypeID*/GILLT_s16,
        GIR_MakeTempReg, /*TempRegID*/1, /*TypeID*/GILLT_s16,
        GIR_MakeTempReg, /*TempRegID*/2, /*TypeID*/GILLT_s16,
        GIR_BuildMI, /*InsnID*/3, /*Opcode*/GIMT_Encode2(AMDGPU::V_ALIGNBIT_B32_e64),
        GIR_AddTempRegister, /*InsnID*/3, /*TempRegID*/2, /*TempRegFlags*/GIMT_Encode2(RegState::Define),
        GIR_Copy, /*NewInsnID*/3, /*OldInsnID*/0, /*OpIdx*/1, // a
        GIR_Copy, /*NewInsnID*/3, /*OldInsnID*/0, /*OpIdx*/1, // a
        GIR_AddImm8, /*InsnID*/3, /*Imm*/8,
        GIR_ConstrainSelectedInstOperands, /*InsnID*/3,
        GIR_BuildMI, /*InsnID*/2, /*Opcode*/GIMT_Encode2(AMDGPU::V_ALIGNBIT_B32_e64),
        GIR_AddTempRegister, /*InsnID*/2, /*TempRegID*/1, /*TempRegFlags*/GIMT_Encode2(RegState::Define),
        GIR_Copy, /*NewInsnID*/2, /*OldInsnID*/0, /*OpIdx*/1, // a
        GIR_Copy, /*NewInsnID*/2, /*OldInsnID*/0, /*OpIdx*/1, // a
        GIR_AddImm8, /*InsnID*/2, /*Imm*/24,
        GIR_ConstrainSelectedInstOperands, /*InsnID*/2,
        GIR_BuildMI, /*InsnID*/1, /*Opcode*/GIMT_Encode2(AMDGPU::S_MOV_B32),
        GIR_AddTempRegister, /*InsnID*/1, /*TempRegID*/0, /*TempRegFlags*/GIMT_Encode2(RegState::Define),
        GIR_AddImm, /*InsnID*/1, /*Imm*/GIMT_Encode8(16711935),
        GIR_ConstrainSelectedInstOperands, /*InsnID*/1,
        GIR_BuildMI, /*InsnID*/0, /*Opcode*/GIMT_Encode2(AMDGPU::V_BFI_B32_e64),
        GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/0, // DstI[vdst]
        GIR_AddSimpleTempRegister, /*InsnID*/0, /*TempRegID*/0,
        GIR_AddSimpleTempRegister, /*InsnID*/0, /*TempRegID*/1,
        GIR_AddSimpleTempRegister, /*InsnID*/0, /*TempRegID*/2,
        GIR_ConstrainSelectedInstOperands, /*InsnID*/0,
        GIR_EraseFromParent, /*InsnID*/0,
        // GIR_Coverage, 6392,
        GIR_Done,
      // Label 5463: @402255
      GIM_Reject,
    // Label 5461: @402256
    GIM_Reject,
    // Label 5457: @402257
    GIM_Try, /*On fail goto*//*Label 5464*/ GIMT_Encode4(402921),
      GIM_CheckType, /*MI*/0, /*Op*/1, /*Type*/GILLT_s64,
      GIM_CheckRegBankForClass, /*MI*/0, /*Op*/0, /*RC*/GIMT_Encode2(AMDGPU::VReg_64RegClassID),
      GIM_Try, /*On fail goto*//*Label 5465*/ GIMT_Encode4(402467), // Rule ID 6395 //
        GIM_CheckFeatures, GIMT_Encode2(GIFBS_isGFX8Plus),
        // (bswap:{ *:[i64] } i64:{ *:[i64] }:$a)  =>  (REG_SEQUENCE:{ *:[i64] } VReg_64:{ *:[i32] }, (V_PERM_B32_e64:{ *:[i16] } 0:{ *:[i32] }, (EXTRACT_SUBREG:{ *:[i16] } VReg_64:{ *:[i64] }:$a, sub1:{ *:[i32] }), (S_MOV_B32:{ *:[i16] } 66051:{ *:[i32] })), sub0:{ *:[i32] }, (V_PERM_B32_e64:{ *:[i16] } 0:{ *:[i32] }, (EXTRACT_SUBREG:{ *:[i16] } VReg_64:{ *:[i64] }:$a, sub0:{ *:[i32] }), (S_MOV_B32:{ *:[i16] } 66051:{ *:[i32] })), sub1:{ *:[i32] })
        GIR_MakeTempReg, /*TempRegID*/0, /*TypeID*/GILLT_s16,
        GIR_MakeTempReg, /*TempRegID*/1, /*TypeID*/GILLT_s16,
        GIR_MakeTempReg, /*TempRegID*/2, /*TypeID*/GILLT_s16,
        GIR_MakeTempReg, /*TempRegID*/3, /*TypeID*/GILLT_s16,
        GIR_MakeTempReg, /*TempRegID*/4, /*TypeID*/GILLT_s16,
        GIR_MakeTempReg, /*TempRegID*/5, /*TypeID*/GILLT_s16,
        GIR_BuildMI, /*InsnID*/6, /*Opcode*/GIMT_Encode2(AMDGPU::S_MOV_B32),
        GIR_AddTempRegister, /*InsnID*/6, /*TempRegID*/5, /*TempRegFlags*/GIMT_Encode2(RegState::Define),
        GIR_AddImm, /*InsnID*/6, /*Imm*/GIMT_Encode8(66051),
        GIR_ConstrainSelectedInstOperands, /*InsnID*/6,
        GIR_BuildMI, /*InsnID*/5, /*Opcode*/GIMT_Encode2(TargetOpcode::COPY),
        GIR_AddTempRegister, /*InsnID*/5, /*TempRegID*/4, /*TempRegFlags*/GIMT_Encode2(RegState::Define),
        GIR_CopySubReg, /*NewInsnID*/5, /*OldInsnID*/0, /*OpIdx*/1, /*SubRegIdx*/GIMT_Encode2(3), // a
        GIR_ConstrainOperandRC, /*InsnID*/5, /*Op*/0, GIMT_Encode2(AMDGPU::VGPR_32RegClassID),
        GIR_ConstrainOperandRC, /*InsnID*/5, /*Op*/1, GIMT_Encode2(AMDGPU::VReg_64RegClassID),
        GIR_BuildMI, /*InsnID*/4, /*Opcode*/GIMT_Encode2(AMDGPU::V_PERM_B32_e64),
        GIR_AddTempRegister, /*InsnID*/4, /*TempRegID*/3, /*TempRegFlags*/GIMT_Encode2(RegState::Define),
        GIR_AddImm8, /*InsnID*/4, /*Imm*/0,
        GIR_AddSimpleTempRegister, /*InsnID*/4, /*TempRegID*/4,
        GIR_AddSimpleTempRegister, /*InsnID*/4, /*TempRegID*/5,
        GIR_ConstrainSelectedInstOperands, /*InsnID*/4,
        GIR_BuildMI, /*InsnID*/3, /*Opcode*/GIMT_Encode2(AMDGPU::S_MOV_B32),
        GIR_AddTempRegister, /*InsnID*/3, /*TempRegID*/2, /*TempRegFlags*/GIMT_Encode2(RegState::Define),
        GIR_AddImm, /*InsnID*/3, /*Imm*/GIMT_Encode8(66051),
        GIR_ConstrainSelectedInstOperands, /*InsnID*/3,
        GIR_BuildMI, /*InsnID*/2, /*Opcode*/GIMT_Encode2(TargetOpcode::COPY),
        GIR_AddTempRegister, /*InsnID*/2, /*TempRegID*/1, /*TempRegFlags*/GIMT_Encode2(RegState::Define),
        GIR_CopySubReg, /*NewInsnID*/2, /*OldInsnID*/0, /*OpIdx*/1, /*SubRegIdx*/GIMT_Encode2(11), // a
        GIR_ConstrainOperandRC, /*InsnID*/2, /*Op*/0, GIMT_Encode2(AMDGPU::VGPR_32RegClassID),
        GIR_ConstrainOperandRC, /*InsnID*/2, /*Op*/1, GIMT_Encode2(AMDGPU::VReg_64RegClassID),
        GIR_BuildMI, /*InsnID*/1, /*Opcode*/GIMT_Encode2(AMDGPU::V_PERM_B32_e64),
        GIR_AddTempRegister, /*InsnID*/1, /*TempRegID*/0, /*TempRegFlags*/GIMT_Encode2(RegState::Define),
        GIR_AddImm8, /*InsnID*/1, /*Imm*/0,
        GIR_AddSimpleTempRegister, /*InsnID*/1, /*TempRegID*/1,
        GIR_AddSimpleTempRegister, /*InsnID*/1, /*TempRegID*/2,
        GIR_ConstrainSelectedInstOperands, /*InsnID*/1,
        GIR_BuildMI, /*InsnID*/0, /*Opcode*/GIMT_Encode2(TargetOpcode::REG_SEQUENCE),
        GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/0, // DstI[dst]
        GIR_AddSimpleTempRegister, /*InsnID*/0, /*TempRegID*/0,
        GIR_AddImm8, /*InsnID*/0, /*SubRegIndex*/3,
        GIR_AddSimpleTempRegister, /*InsnID*/0, /*TempRegID*/3,
        GIR_AddImm8, /*InsnID*/0, /*SubRegIndex*/11,
        GIR_ConstrainOperandRC, /*InsnID*/0, /*Op*/0, GIMT_Encode2(AMDGPU::VReg_64RegClassID),
        GIR_ConstrainOperandRC, /*InsnID*/0, /*Op*/1, GIMT_Encode2(AMDGPU::VGPR_32RegClassID),
        GIR_ConstrainOperandRC, /*InsnID*/0, /*Op*/3, GIMT_Encode2(AMDGPU::VGPR_32RegClassID),
        GIR_EraseFromParent, /*InsnID*/0,
        // GIR_Coverage, 6395,
        GIR_Done,
      // Label 5465: @402467
      GIM_Try, /*On fail goto*//*Label 5466*/ GIMT_Encode4(402920), // Rule ID 6393 //
        // (bswap:{ *:[i64] } i64:{ *:[i64] }:$a)  =>  (REG_SEQUENCE:{ *:[i64] } VReg_64:{ *:[i32] }, (V_BFI_B32_e64:{ *:[i16] } (S_MOV_B32:{ *:[i16] } 16711935:{ *:[i32] }), (V_ALIGNBIT_B32_e64:{ *:[i16] } (EXTRACT_SUBREG:{ *:[i32] } VReg_64:{ *:[i64] }:$a, sub1:{ *:[i32] }), (EXTRACT_SUBREG:{ *:[i32] } VReg_64:{ *:[i64] }:$a, sub1:{ *:[i32] }), 24:{ *:[i32] }), (V_ALIGNBIT_B32_e64:{ *:[i16] } (EXTRACT_SUBREG:{ *:[i32] } VReg_64:{ *:[i64] }:$a, sub1:{ *:[i32] }), (EXTRACT_SUBREG:{ *:[i32] } VReg_64:{ *:[i64] }:$a, sub1:{ *:[i32] }), 8:{ *:[i32] })), sub0:{ *:[i32] }, (V_BFI_B32_e64:{ *:[i16] } (S_MOV_B32:{ *:[i16] } 16711935:{ *:[i32] }), (V_ALIGNBIT_B32_e64:{ *:[i16] } (EXTRACT_SUBREG:{ *:[i32] } VReg_64:{ *:[i64] }:$a, sub0:{ *:[i32] }), (EXTRACT_SUBREG:{ *:[i32] } VReg_64:{ *:[i64] }:$a, sub0:{ *:[i32] }), 24:{ *:[i32] }), (V_ALIGNBIT_B32_e64:{ *:[i16] } (EXTRACT_SUBREG:{ *:[i32] } VReg_64:{ *:[i64] }:$a, sub0:{ *:[i32] }), (EXTRACT_SUBREG:{ *:[i32] } VReg_64:{ *:[i64] }:$a, sub0:{ *:[i32] }), 8:{ *:[i32] })), sub1:{ *:[i32] })
        GIR_MakeTempReg, /*TempRegID*/0, /*TypeID*/GILLT_s16,
        GIR_MakeTempReg, /*TempRegID*/1, /*TypeID*/GILLT_s16,
        GIR_MakeTempReg, /*TempRegID*/2, /*TypeID*/GILLT_s16,
        GIR_MakeTempReg, /*TempRegID*/3, /*TypeID*/GILLT_s32,
        GIR_MakeTempReg, /*TempRegID*/4, /*TypeID*/GILLT_s32,
        GIR_MakeTempReg, /*TempRegID*/5, /*TypeID*/GILLT_s16,
        GIR_MakeTempReg, /*TempRegID*/6, /*TypeID*/GILLT_s32,
        GIR_MakeTempReg, /*TempRegID*/7, /*TypeID*/GILLT_s32,
        GIR_MakeTempReg, /*TempRegID*/8, /*TypeID*/GILLT_s16,
        GIR_MakeTempReg, /*TempRegID*/9, /*TypeID*/GILLT_s16,
        GIR_MakeTempReg, /*TempRegID*/10, /*TypeID*/GILLT_s16,
        GIR_MakeTempReg, /*TempRegID*/11, /*TypeID*/GILLT_s32,
        GIR_MakeTempReg, /*TempRegID*/12, /*TypeID*/GILLT_s32,
        GIR_MakeTempReg, /*TempRegID*/13, /*TypeID*/GILLT_s16,
        GIR_MakeTempReg, /*TempRegID*/14, /*TypeID*/GILLT_s32,
        GIR_MakeTempReg, /*TempRegID*/15, /*TypeID*/GILLT_s32,
        GIR_BuildMI, /*InsnID*/16, /*Opcode*/GIMT_Encode2(TargetOpcode::COPY),
        GIR_AddTempRegister, /*InsnID*/16, /*TempRegID*/15, /*TempRegFlags*/GIMT_Encode2(RegState::Define),
        GIR_CopySubReg, /*NewInsnID*/16, /*OldInsnID*/0, /*OpIdx*/1, /*SubRegIdx*/GIMT_Encode2(3), // a
        GIR_ConstrainOperandRC, /*InsnID*/16, /*Op*/0, GIMT_Encode2(AMDGPU::VGPR_32RegClassID),
        GIR_ConstrainOperandRC, /*InsnID*/16, /*Op*/1, GIMT_Encode2(AMDGPU::VReg_64RegClassID),
        GIR_BuildMI, /*InsnID*/15, /*Opcode*/GIMT_Encode2(TargetOpcode::COPY),
        GIR_AddTempRegister, /*InsnID*/15, /*TempRegID*/14, /*TempRegFlags*/GIMT_Encode2(RegState::Define),
        GIR_CopySubReg, /*NewInsnID*/15, /*OldInsnID*/0, /*OpIdx*/1, /*SubRegIdx*/GIMT_Encode2(3), // a
        GIR_ConstrainOperandRC, /*InsnID*/15, /*Op*/0, GIMT_Encode2(AMDGPU::VGPR_32RegClassID),
        GIR_ConstrainOperandRC, /*InsnID*/15, /*Op*/1, GIMT_Encode2(AMDGPU::VReg_64RegClassID),
        GIR_BuildMI, /*InsnID*/14, /*Opcode*/GIMT_Encode2(AMDGPU::V_ALIGNBIT_B32_e64),
        GIR_AddTempRegister, /*InsnID*/14, /*TempRegID*/13, /*TempRegFlags*/GIMT_Encode2(RegState::Define),
        GIR_AddSimpleTempRegister, /*InsnID*/14, /*TempRegID*/14,
        GIR_AddSimpleTempRegister, /*InsnID*/14, /*TempRegID*/15,
        GIR_AddImm8, /*InsnID*/14, /*Imm*/8,
        GIR_ConstrainSelectedInstOperands, /*InsnID*/14,
        GIR_BuildMI, /*InsnID*/13, /*Opcode*/GIMT_Encode2(TargetOpcode::COPY),
        GIR_AddTempRegister, /*InsnID*/13, /*TempRegID*/12, /*TempRegFlags*/GIMT_Encode2(RegState::Define),
        GIR_CopySubReg, /*NewInsnID*/13, /*OldInsnID*/0, /*OpIdx*/1, /*SubRegIdx*/GIMT_Encode2(3), // a
        GIR_ConstrainOperandRC, /*InsnID*/13, /*Op*/0, GIMT_Encode2(AMDGPU::VGPR_32RegClassID),
        GIR_ConstrainOperandRC, /*InsnID*/13, /*Op*/1, GIMT_Encode2(AMDGPU::VReg_64RegClassID),
        GIR_BuildMI, /*InsnID*/12, /*Opcode*/GIMT_Encode2(TargetOpcode::COPY),
        GIR_AddTempRegister, /*InsnID*/12, /*TempRegID*/11, /*TempRegFlags*/GIMT_Encode2(RegState::Define),
        GIR_CopySubReg, /*NewInsnID*/12, /*OldInsnID*/0, /*OpIdx*/1, /*SubRegIdx*/GIMT_Encode2(3), // a
        GIR_ConstrainOperandRC, /*InsnID*/12, /*Op*/0, GIMT_Encode2(AMDGPU::VGPR_32RegClassID),
        GIR_ConstrainOperandRC, /*InsnID*/12, /*Op*/1, GIMT_Encode2(AMDGPU::VReg_64RegClassID),
        GIR_BuildMI, /*InsnID*/11, /*Opcode*/GIMT_Encode2(AMDGPU::V_ALIGNBIT_B32_e64),
        GIR_AddTempRegister, /*InsnID*/11, /*TempRegID*/10, /*TempRegFlags*/GIMT_Encode2(RegState::Define),
        GIR_AddSimpleTempRegister, /*InsnID*/11, /*TempRegID*/11,
        GIR_AddSimpleTempRegister, /*InsnID*/11, /*TempRegID*/12,
        GIR_AddImm8, /*InsnID*/11, /*Imm*/24,
        GIR_ConstrainSelectedInstOperands, /*InsnID*/11,
        GIR_BuildMI, /*InsnID*/10, /*Opcode*/GIMT_Encode2(AMDGPU::S_MOV_B32),
        GIR_AddTempRegister, /*InsnID*/10, /*TempRegID*/9, /*TempRegFlags*/GIMT_Encode2(RegState::Define),
        GIR_AddImm, /*InsnID*/10, /*Imm*/GIMT_Encode8(16711935),
        GIR_ConstrainSelectedInstOperands, /*InsnID*/10,
        GIR_BuildMI, /*InsnID*/9, /*Opcode*/GIMT_Encode2(AMDGPU::V_BFI_B32_e64),
        GIR_AddTempRegister, /*InsnID*/9, /*TempRegID*/8, /*TempRegFlags*/GIMT_Encode2(RegState::Define),
        GIR_AddSimpleTempRegister, /*InsnID*/9, /*TempRegID*/9,
        GIR_AddSimpleTempRegister, /*InsnID*/9, /*TempRegID*/10,
        GIR_AddSimpleTempRegister, /*InsnID*/9, /*TempRegID*/13,
        GIR_ConstrainSelectedInstOperands, /*InsnID*/9,
        GIR_BuildMI, /*InsnID*/8, /*Opcode*/GIMT_Encode2(TargetOpcode::COPY),
        GIR_AddTempRegister, /*InsnID*/8, /*TempRegID*/7, /*TempRegFlags*/GIMT_Encode2(RegState::Define),
        GIR_CopySubReg, /*NewInsnID*/8, /*OldInsnID*/0, /*OpIdx*/1, /*SubRegIdx*/GIMT_Encode2(11), // a
        GIR_ConstrainOperandRC, /*InsnID*/8, /*Op*/0, GIMT_Encode2(AMDGPU::VGPR_32RegClassID),
        GIR_ConstrainOperandRC, /*InsnID*/8, /*Op*/1, GIMT_Encode2(AMDGPU::VReg_64RegClassID),
        GIR_BuildMI, /*InsnID*/7, /*Opcode*/GIMT_Encode2(TargetOpcode::COPY),
        GIR_AddTempRegister, /*InsnID*/7, /*TempRegID*/6, /*TempRegFlags*/GIMT_Encode2(RegState::Define),
        GIR_CopySubReg, /*NewInsnID*/7, /*OldInsnID*/0, /*OpIdx*/1, /*SubRegIdx*/GIMT_Encode2(11), // a
        GIR_ConstrainOperandRC, /*InsnID*/7, /*Op*/0, GIMT_Encode2(AMDGPU::VGPR_32RegClassID),
        GIR_ConstrainOperandRC, /*InsnID*/7, /*Op*/1, GIMT_Encode2(AMDGPU::VReg_64RegClassID),
        GIR_BuildMI, /*InsnID*/6, /*Opcode*/GIMT_Encode2(AMDGPU::V_ALIGNBIT_B32_e64),
        GIR_AddTempRegister, /*InsnID*/6, /*TempRegID*/5, /*TempRegFlags*/GIMT_Encode2(RegState::Define),
        GIR_AddSimpleTempRegister, /*InsnID*/6, /*TempRegID*/6,
        GIR_AddSimpleTempRegister, /*InsnID*/6, /*TempRegID*/7,
        GIR_AddImm8, /*InsnID*/6, /*Imm*/8,
        GIR_ConstrainSelectedInstOperands, /*InsnID*/6,
        GIR_BuildMI, /*InsnID*/5, /*Opcode*/GIMT_Encode2(TargetOpcode::COPY),
        GIR_AddTempRegister, /*InsnID*/5, /*TempRegID*/4, /*TempRegFlags*/GIMT_Encode2(RegState::Define),
        GIR_CopySubReg, /*NewInsnID*/5, /*OldInsnID*/0, /*OpIdx*/1, /*SubRegIdx*/GIMT_Encode2(11), // a
        GIR_ConstrainOperandRC, /*InsnID*/5, /*Op*/0, GIMT_Encode2(AMDGPU::VGPR_32RegClassID),
        GIR_ConstrainOperandRC, /*InsnID*/5, /*Op*/1, GIMT_Encode2(AMDGPU::VReg_64RegClassID),
        GIR_BuildMI, /*InsnID*/4, /*Opcode*/GIMT_Encode2(TargetOpcode::COPY),
        GIR_AddTempRegister, /*InsnID*/4, /*TempRegID*/3, /*TempRegFlags*/GIMT_Encode2(RegState::Define),
        GIR_CopySubReg, /*NewInsnID*/4, /*OldInsnID*/0, /*OpIdx*/1, /*SubRegIdx*/GIMT_Encode2(11), // a
        GIR_ConstrainOperandRC, /*InsnID*/4, /*Op*/0, GIMT_Encode2(AMDGPU::VGPR_32RegClassID),
        GIR_ConstrainOperandRC, /*InsnID*/4, /*Op*/1, GIMT_Encode2(AMDGPU::VReg_64RegClassID),
        GIR_BuildMI, /*InsnID*/3, /*Opcode*/GIMT_Encode2(AMDGPU::V_ALIGNBIT_B32_e64),
        GIR_AddTempRegister, /*InsnID*/3, /*TempRegID*/2, /*TempRegFlags*/GIMT_Encode2(RegState::Define),
        GIR_AddSimpleTempRegister, /*InsnID*/3, /*TempRegID*/3,
        GIR_AddSimpleTempRegister, /*InsnID*/3, /*TempRegID*/4,
        GIR_AddImm8, /*InsnID*/3, /*Imm*/24,
        GIR_ConstrainSelectedInstOperands, /*InsnID*/3,
        GIR_BuildMI, /*InsnID*/2, /*Opcode*/GIMT_Encode2(AMDGPU::S_MOV_B32),
        GIR_AddTempRegister, /*InsnID*/2, /*TempRegID*/1, /*TempRegFlags*/GIMT_Encode2(RegState::Define),
        GIR_AddImm, /*InsnID*/2, /*Imm*/GIMT_Encode8(16711935),
        GIR_ConstrainSelectedInstOperands, /*InsnID*/2,
        GIR_BuildMI, /*InsnID*/1, /*Opcode*/GIMT_Encode2(AMDGPU::V_BFI_B32_e64),
        GIR_AddTempRegister, /*InsnID*/1, /*TempRegID*/0, /*TempRegFlags*/GIMT_Encode2(RegState::Define),
        GIR_AddSimpleTempRegister, /*InsnID*/1, /*TempRegID*/1,
        GIR_AddSimpleTempRegister, /*InsnID*/1, /*TempRegID*/2,
        GIR_AddSimpleTempRegister, /*InsnID*/1, /*TempRegID*/5,
        GIR_ConstrainSelectedInstOperands, /*InsnID*/1,
        GIR_BuildMI, /*InsnID*/0, /*Opcode*/GIMT_Encode2(TargetOpcode::REG_SEQUENCE),
        GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/0, // DstI[dst]
        GIR_AddSimpleTempRegister, /*InsnID*/0, /*TempRegID*/0,
        GIR_AddImm8, /*InsnID*/0, /*SubRegIndex*/3,
        GIR_AddSimpleTempRegister, /*InsnID*/0, /*TempRegID*/8,
        GIR_AddImm8, /*InsnID*/0, /*SubRegIndex*/11,
        GIR_ConstrainOperandRC, /*InsnID*/0, /*Op*/0, GIMT_Encode2(AMDGPU::VReg_64RegClassID),
        GIR_ConstrainOperandRC, /*InsnID*/0, /*Op*/1, GIMT_Encode2(AMDGPU::VGPR_32RegClassID),
        GIR_ConstrainOperandRC, /*InsnID*/0, /*Op*/3, GIMT_Encode2(AMDGPU::VGPR_32RegClassID),
        GIR_EraseFromParent, /*InsnID*/0,
        // GIR_Coverage, 6393,
        GIR_Done,
      // Label 5466: @402920
      GIM_Reject,
    // Label 5464: @402921
    GIM_Reject,
    // Label 5458: @402922
    GIM_Try, /*On fail goto*//*Label 5467*/ GIMT_Encode4(402986), // Rule ID 6398 //
      GIM_CheckFeatures, GIMT_Encode2(GIFBS_isGFX8Plus),
      GIM_CheckType, /*MI*/0, /*Op*/1, /*Type*/GILLT_v2s16,
      GIM_CheckRegBankForClass, /*MI*/0, /*Op*/0, /*RC*/GIMT_Encode2(AMDGPU::VGPR_32RegClassID),
      // (bswap:{ *:[v2i16] } v2i16:{ *:[v2i16] }:$a)  =>  (V_PERM_B32_e64:{ *:[v2i16] } 0:{ *:[i32] }, VSrc_b32:{ *:[v2i16] }:$a, (S_MOV_B32:{ *:[i16] } 33751041:{ *:[i32] }))
      GIR_MakeTempReg, /*TempRegID*/0, /*TypeID*/GILLT_s16,
      GIR_BuildMI, /*InsnID*/1, /*Opcode*/GIMT_Encode2(AMDGPU::S_MOV_B32),
      GIR_AddTempRegister, /*InsnID*/1, /*TempRegID*/0, /*TempRegFlags*/GIMT_Encode2(RegState::Define),
      GIR_AddImm, /*InsnID*/1, /*Imm*/GIMT_Encode8(33751041),
      GIR_ConstrainSelectedInstOperands, /*InsnID*/1,
      GIR_BuildMI, /*InsnID*/0, /*Opcode*/GIMT_Encode2(AMDGPU::V_PERM_B32_e64),
      GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/0, // DstI[vdst]
      GIR_AddImm8, /*InsnID*/0, /*Imm*/0,
      GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/1, // a
      GIR_AddSimpleTempRegister, /*InsnID*/0, /*TempRegID*/0,
      GIR_ConstrainSelectedInstOperands, /*InsnID*/0,
      GIR_EraseFromParent, /*InsnID*/0,
      // GIR_Coverage, 6398,
      GIR_Done,
    // Label 5467: @402986
    GIM_Reject,
    // Label 5459: @402987
    GIM_Reject,
    // Label 94: @402988
    GIM_SwitchType, /*MI*/0, /*Op*/0, /*[*/GIMT_Encode2(9), GIMT_Encode2(11), /*)*//*default:*//*Label 5470*/ GIMT_Encode4(403254),
    /*GILLT_s32*//*Label 5468*/ GIMT_Encode4(403007),
    /*GILLT_s64*//*Label 5469*/ GIMT_Encode4(403079),
    // Label 5468: @403007
    GIM_Try, /*On fail goto*//*Label 5471*/ GIMT_Encode4(403078),
      GIM_CheckType, /*MI*/0, /*Op*/1, /*Type*/GILLT_s32,
      GIM_Try, /*On fail goto*//*Label 5472*/ GIMT_Encode4(403038), // Rule ID 4 //
        GIM_CheckRegBankForClass, /*MI*/0, /*Op*/0, /*RC*/GIMT_Encode2(AMDGPU::SReg_32RegClassID),
        GIM_CheckCxxInsnPredicate, /*MI*/0, /*FnId*/GIMT_Encode2(GICXXPred_MI_Predicate_anonymous_17567),
        // (bitreverse:{ *:[i32] } i32:{ *:[i32] }:$src0)<<P:Predicate_anonymous_17567>>  =>  (S_BREV_B32:{ *:[i32] } i32:{ *:[i32] }:$src0)
        GIR_MutateOpcode, /*InsnID*/0, /*RecycleInsnID*/0, /*Opcode*/GIMT_Encode2(AMDGPU::S_BREV_B32),
        GIR_ConstrainSelectedInstOperands, /*InsnID*/0,
        // GIR_Coverage, 4,
        GIR_Done,
      // Label 5472: @403038
      GIM_Try, /*On fail goto*//*Label 5473*/ GIMT_Encode4(403077), // Rule ID 624 //
        GIM_CheckRegBankForClass, /*MI*/0, /*Op*/0, /*RC*/GIMT_Encode2(AMDGPU::VGPR_32RegClassID),
        GIM_CheckCxxInsnPredicate, /*MI*/0, /*FnId*/GIMT_Encode2(GICXXPred_MI_Predicate_anonymous_21180),
        GIM_CheckComplexPattern, /*MI*/0, /*Op*/1, /*Renderer*/GIMT_Encode2(0), GIMT_Encode2(GICP_gi_vop3mods0),
        // (bitreverse:{ *:[i32] } (VOP3Mods0:{ *:[i32] } i32:{ *:[i32] }:$src0))<<P:Predicate_anonymous_21180>>  =>  (V_BFREV_B32_e64:{ *:[i32] } i32:{ *:[i32] }:$src0)
        GIR_BuildMI, /*InsnID*/0, /*Opcode*/GIMT_Encode2(AMDGPU::V_BFREV_B32_e64),
        GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/0, // DstI[vdst]
        GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/0, // src0
        GIR_ConstrainSelectedInstOperands, /*InsnID*/0,
        GIR_EraseFromParent, /*InsnID*/0,
        // GIR_Coverage, 624,
        GIR_Done,
      // Label 5473: @403077
      GIM_Reject,
    // Label 5471: @403078
    GIM_Reject,
    // Label 5469: @403079
    GIM_Try, /*On fail goto*//*Label 5474*/ GIMT_Encode4(403253),
      GIM_CheckType, /*MI*/0, /*Op*/1, /*Type*/GILLT_s64,
      GIM_Try, /*On fail goto*//*Label 5475*/ GIMT_Encode4(403110), // Rule ID 5 //
        GIM_CheckRegBankForClass, /*MI*/0, /*Op*/0, /*RC*/GIMT_Encode2(AMDGPU::SReg_64RegClassID),
        GIM_CheckCxxInsnPredicate, /*MI*/0, /*FnId*/GIMT_Encode2(GICXXPred_MI_Predicate_anonymous_17567),
        // (bitreverse:{ *:[i64] } i64:{ *:[i64] }:$src0)<<P:Predicate_anonymous_17567>>  =>  (S_BREV_B64:{ *:[i64] } i64:{ *:[i64] }:$src0)
        GIR_MutateOpcode, /*InsnID*/0, /*RecycleInsnID*/0, /*Opcode*/GIMT_Encode2(AMDGPU::S_BREV_B64),
        GIR_ConstrainSelectedInstOperands, /*InsnID*/0,
        // GIR_Coverage, 5,
        GIR_Done,
      // Label 5475: @403110
      GIM_Try, /*On fail goto*//*Label 5476*/ GIMT_Encode4(403252), // Rule ID 6399 //
        GIM_CheckRegBankForClass, /*MI*/0, /*Op*/0, /*RC*/GIMT_Encode2(AMDGPU::VReg_64RegClassID),
        GIM_CheckCxxInsnPredicate, /*MI*/0, /*FnId*/GIMT_Encode2(GICXXPred_MI_Predicate_anonymous_21180),
        // (bitreverse:{ *:[i64] } i64:{ *:[i64] }:$a)<<P:Predicate_anonymous_21180>>  =>  (REG_SEQUENCE:{ *:[i64] } VReg_64:{ *:[i32] }, (V_BFREV_B32_e64:{ *:[i16] } (EXTRACT_SUBREG:{ *:[i32] } VReg_64:{ *:[i64] }:$a, sub1:{ *:[i32] })), sub0:{ *:[i32] }, (V_BFREV_B32_e64:{ *:[i16] } (EXTRACT_SUBREG:{ *:[i32] } VReg_64:{ *:[i64] }:$a, sub0:{ *:[i32] })), sub1:{ *:[i32] })
        GIR_MakeTempReg, /*TempRegID*/0, /*TypeID*/GILLT_s16,
        GIR_MakeTempReg, /*TempRegID*/1, /*TypeID*/GILLT_s32,
        GIR_MakeTempReg, /*TempRegID*/2, /*TypeID*/GILLT_s16,
        GIR_MakeTempReg, /*TempRegID*/3, /*TypeID*/GILLT_s32,
        GIR_BuildMI, /*InsnID*/4, /*Opcode*/GIMT_Encode2(TargetOpcode::COPY),
        GIR_AddTempRegister, /*InsnID*/4, /*TempRegID*/3, /*TempRegFlags*/GIMT_Encode2(RegState::Define),
        GIR_CopySubReg, /*NewInsnID*/4, /*OldInsnID*/0, /*OpIdx*/1, /*SubRegIdx*/GIMT_Encode2(3), // a
        GIR_ConstrainOperandRC, /*InsnID*/4, /*Op*/0, GIMT_Encode2(AMDGPU::VGPR_32RegClassID),
        GIR_ConstrainOperandRC, /*InsnID*/4, /*Op*/1, GIMT_Encode2(AMDGPU::VReg_64RegClassID),
        GIR_BuildMI, /*InsnID*/3, /*Opcode*/GIMT_Encode2(AMDGPU::V_BFREV_B32_e64),
        GIR_AddTempRegister, /*InsnID*/3, /*TempRegID*/2, /*TempRegFlags*/GIMT_Encode2(RegState::Define),
        GIR_AddSimpleTempRegister, /*InsnID*/3, /*TempRegID*/3,
        GIR_ConstrainSelectedInstOperands, /*InsnID*/3,
        GIR_BuildMI, /*InsnID*/2, /*Opcode*/GIMT_Encode2(TargetOpcode::COPY),
        GIR_AddTempRegister, /*InsnID*/2, /*TempRegID*/1, /*TempRegFlags*/GIMT_Encode2(RegState::Define),
        GIR_CopySubReg, /*NewInsnID*/2, /*OldInsnID*/0, /*OpIdx*/1, /*SubRegIdx*/GIMT_Encode2(11), // a
        GIR_ConstrainOperandRC, /*InsnID*/2, /*Op*/0, GIMT_Encode2(AMDGPU::VGPR_32RegClassID),
        GIR_ConstrainOperandRC, /*InsnID*/2, /*Op*/1, GIMT_Encode2(AMDGPU::VReg_64RegClassID),
        GIR_BuildMI, /*InsnID*/1, /*Opcode*/GIMT_Encode2(AMDGPU::V_BFREV_B32_e64),
        GIR_AddTempRegister, /*InsnID*/1, /*TempRegID*/0, /*TempRegFlags*/GIMT_Encode2(RegState::Define),
        GIR_AddSimpleTempRegister, /*InsnID*/1, /*TempRegID*/1,
        GIR_ConstrainSelectedInstOperands, /*InsnID*/1,
        GIR_BuildMI, /*InsnID*/0, /*Opcode*/GIMT_Encode2(TargetOpcode::REG_SEQUENCE),
        GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/0, // DstI[dst]
        GIR_AddSimpleTempRegister, /*InsnID*/0, /*TempRegID*/0,
        GIR_AddImm8, /*InsnID*/0, /*SubRegIndex*/3,
        GIR_AddSimpleTempRegister, /*InsnID*/0, /*TempRegID*/2,
        GIR_AddImm8, /*InsnID*/0, /*SubRegIndex*/11,
        GIR_ConstrainOperandRC, /*InsnID*/0, /*Op*/0, GIMT_Encode2(AMDGPU::VReg_64RegClassID),
        GIR_ConstrainOperandRC, /*InsnID*/0, /*Op*/1, GIMT_Encode2(AMDGPU::VGPR_32RegClassID),
        GIR_ConstrainOperandRC, /*InsnID*/0, /*Op*/3, GIMT_Encode2(AMDGPU::VGPR_32RegClassID),
        GIR_EraseFromParent, /*InsnID*/0,
        // GIR_Coverage, 6399,
        GIR_Done,
      // Label 5476: @403252
      GIM_Reject,
    // Label 5474: @403253
    GIM_Reject,
    // Label 5470: @403254
    GIM_Reject,
    // Label 95: @403255
    GIM_SwitchType, /*MI*/0, /*Op*/0, /*[*/GIMT_Encode2(8), GIMT_Encode2(11), /*)*//*default:*//*Label 5480*/ GIMT_Encode4(403625),
    /*GILLT_s16*//*Label 5477*/ GIMT_Encode4(403278),
    /*GILLT_s32*//*Label 5478*/ GIMT_Encode4(403477),
    /*GILLT_s64*//*Label 5479*/ GIMT_Encode4(403567),
    // Label 5477: @403278
    GIM_Try, /*On fail goto*//*Label 5481*/ GIMT_Encode4(403476),
      GIM_CheckType, /*MI*/0, /*Op*/1, /*Type*/GILLT_s16,
      GIM_Try, /*On fail goto*//*Label 5482*/ GIMT_Encode4(403316), // Rule ID 37 //
        GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasSALUFloatInsts),
        GIM_CheckRegBankForClass, /*MI*/0, /*Op*/0, /*RC*/GIMT_Encode2(AMDGPU::SReg_32RegClassID),
        GIM_CheckCxxInsnPredicate, /*MI*/0, /*FnId*/GIMT_Encode2(GICXXPred_MI_Predicate_anonymous_17598),
        // (fceil:{ *:[f16] } f16:{ *:[f16] }:$src0)<<P:Predicate_anonymous_17598>>  =>  (S_CEIL_F16:{ *:[f16] } f16:{ *:[f16] }:$src0)
        GIR_MutateOpcode, /*InsnID*/0, /*RecycleInsnID*/0, /*Opcode*/GIMT_Encode2(AMDGPU::S_CEIL_F16),
        GIR_AddImplicitUse, /*InsnID*/0, GIMT_Encode2(AMDGPU::MODE),
        GIR_ConstrainSelectedInstOperands, /*InsnID*/0,
        // GIR_Coverage, 37,
        GIR_Done,
      // Label 5482: @403316
      GIM_Try, /*On fail goto*//*Label 5483*/ GIMT_Encode4(403369), // Rule ID 707 //
        GIM_CheckFeatures, GIMT_Encode2(GIFBS_Has16BitInsts_NotHasTrue16BitInsts),
        GIM_CheckRegBankForClass, /*MI*/0, /*Op*/0, /*RC*/GIMT_Encode2(AMDGPU::VGPR_32RegClassID),
        GIM_CheckComplexPattern, /*MI*/0, /*Op*/1, /*Renderer*/GIMT_Encode2(0), GIMT_Encode2(GICP_gi_vop3mods0),
        // (fceil:{ *:[f16] } (VOP3Mods0:{ *:[f16] } f16:{ *:[f16] }:$src0, i32:{ *:[i32] }:$src0_modifiers, i1:{ *:[i1] }:$clamp, i32:{ *:[i32] }:$omod))  =>  (V_CEIL_F16_e64:{ *:[f16] } i32:{ *:[i32] }:$src0_modifiers, f16:{ *:[f16] }:$src0, i1:{ *:[i1] }:$clamp, i32:{ *:[i32] }:$omod)
        GIR_BuildMI, /*InsnID*/0, /*Opcode*/GIMT_Encode2(AMDGPU::V_CEIL_F16_e64),
        GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/0, // DstI[vdst]
        GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/1, // src0_modifiers
        GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/0, // src0
        GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/2, // clamp
        GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/3, // omod
        GIR_ConstrainSelectedInstOperands, /*InsnID*/0,
        GIR_EraseFromParent, /*InsnID*/0,
        // GIR_Coverage, 707,
        GIR_Done,
      // Label 5483: @403369
      GIM_Try, /*On fail goto*//*Label 5484*/ GIMT_Encode4(403422), // Rule ID 708 //
        GIM_CheckFeatures, GIMT_Encode2(GIFBS_UseRealTrue16Insts),
        GIM_CheckRegBankForClass, /*MI*/0, /*Op*/0, /*RC*/GIMT_Encode2(AMDGPU::VGPR_16RegClassID),
        GIM_CheckComplexPattern, /*MI*/0, /*Op*/1, /*Renderer*/GIMT_Encode2(0), GIMT_Encode2(GICP_gi_vop3mods0),
        // (fceil:{ *:[f16] } (VOP3Mods0:{ *:[f16] } f16:{ *:[f16] }:$src0, i32:{ *:[i32] }:$src0_modifiers, i1:{ *:[i1] }:$clamp, i32:{ *:[i32] }:$omod))  =>  (V_CEIL_F16_t16_e64:{ *:[f16] } i32:{ *:[i32] }:$src0_modifiers, f16:{ *:[f16] }:$src0, i1:{ *:[i1] }:$clamp, i32:{ *:[i32] }:$omod)
        GIR_BuildMI, /*InsnID*/0, /*Opcode*/GIMT_Encode2(AMDGPU::V_CEIL_F16_t16_e64),
        GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/0, // DstI[vdst]
        GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/1, // src0_modifiers
        GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/0, // src0
        GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/2, // clamp
        GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/3, // omod
        GIR_ConstrainSelectedInstOperands, /*InsnID*/0,
        GIR_EraseFromParent, /*InsnID*/0,
        // GIR_Coverage, 708,
        GIR_Done,
      // Label 5484: @403422
      GIM_Try, /*On fail goto*//*Label 5485*/ GIMT_Encode4(403475), // Rule ID 709 //
        GIM_CheckFeatures, GIMT_Encode2(GIFBS_UseFakeTrue16Insts),
        GIM_CheckRegBankForClass, /*MI*/0, /*Op*/0, /*RC*/GIMT_Encode2(AMDGPU::VGPR_32RegClassID),
        GIM_CheckComplexPattern, /*MI*/0, /*Op*/1, /*Renderer*/GIMT_Encode2(0), GIMT_Encode2(GICP_gi_vop3mods0),
        // (fceil:{ *:[f16] } (VOP3Mods0:{ *:[f16] } f16:{ *:[f16] }:$src0, i32:{ *:[i32] }:$src0_modifiers, i1:{ *:[i1] }:$clamp, i32:{ *:[i32] }:$omod))  =>  (V_CEIL_F16_fake16_e64:{ *:[f16] } i32:{ *:[i32] }:$src0_modifiers, f16:{ *:[f16] }:$src0, i1:{ *:[i1] }:$clamp, i32:{ *:[i32] }:$omod)
        GIR_BuildMI, /*InsnID*/0, /*Opcode*/GIMT_Encode2(AMDGPU::V_CEIL_F16_fake16_e64),
        GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/0, // DstI[vdst]
        GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/1, // src0_modifiers
        GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/0, // src0
        GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/2, // clamp
        GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/3, // omod
        GIR_ConstrainSelectedInstOperands, /*InsnID*/0,
        GIR_EraseFromParent, /*InsnID*/0,
        // GIR_Coverage, 709,
        GIR_Done,
      // Label 5485: @403475
      GIM_Reject,
    // Label 5481: @403476
    GIM_Reject,
    // Label 5478: @403477
    GIM_Try, /*On fail goto*//*Label 5486*/ GIMT_Encode4(403566),
      GIM_CheckType, /*MI*/0, /*Op*/1, /*Type*/GILLT_s32,
      GIM_Try, /*On fail goto*//*Label 5487*/ GIMT_Encode4(403515), // Rule ID 32 //
        GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasSALUFloatInsts),
        GIM_CheckRegBankForClass, /*MI*/0, /*Op*/0, /*RC*/GIMT_Encode2(AMDGPU::SReg_32RegClassID),
        GIM_CheckCxxInsnPredicate, /*MI*/0, /*FnId*/GIMT_Encode2(GICXXPred_MI_Predicate_anonymous_17598),
        // (fceil:{ *:[f32] } f32:{ *:[f32] }:$src0)<<P:Predicate_anonymous_17598>>  =>  (S_CEIL_F32:{ *:[f32] } f32:{ *:[f32] }:$src0)
        GIR_MutateOpcode, /*InsnID*/0, /*RecycleInsnID*/0, /*Opcode*/GIMT_Encode2(AMDGPU::S_CEIL_F32),
        GIR_AddImplicitUse, /*InsnID*/0, GIMT_Encode2(AMDGPU::MODE),
        GIR_ConstrainSelectedInstOperands, /*InsnID*/0,
        // GIR_Coverage, 32,
        GIR_Done,
      // Label 5487: @403515
      GIM_Try, /*On fail goto*//*Label 5488*/ GIMT_Encode4(403565), // Rule ID 602 //
        GIM_CheckRegBankForClass, /*MI*/0, /*Op*/0, /*RC*/GIMT_Encode2(AMDGPU::VGPR_32RegClassID),
        GIM_CheckComplexPattern, /*MI*/0, /*Op*/1, /*Renderer*/GIMT_Encode2(0), GIMT_Encode2(GICP_gi_vop3mods0),
        // (fceil:{ *:[f32] } (VOP3Mods0:{ *:[f32] } f32:{ *:[f32] }:$src0, i32:{ *:[i32] }:$src0_modifiers, i1:{ *:[i1] }:$clamp, i32:{ *:[i32] }:$omod))  =>  (V_CEIL_F32_e64:{ *:[f32] } i32:{ *:[i32] }:$src0_modifiers, f32:{ *:[f32] }:$src0, i1:{ *:[i1] }:$clamp, i32:{ *:[i32] }:$omod)
        GIR_BuildMI, /*InsnID*/0, /*Opcode*/GIMT_Encode2(AMDGPU::V_CEIL_F32_e64),
        GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/0, // DstI[vdst]
        GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/1, // src0_modifiers
        GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/0, // src0
        GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/2, // clamp
        GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/3, // omod
        GIR_ConstrainSelectedInstOperands, /*InsnID*/0,
        GIR_EraseFromParent, /*InsnID*/0,
        // GIR_Coverage, 602,
        GIR_Done,
      // Label 5488: @403565
      GIM_Reject,
    // Label 5486: @403566
    GIM_Reject,
    // Label 5479: @403567
    GIM_Try, /*On fail goto*//*Label 5489*/ GIMT_Encode4(403624), // Rule ID 646 //
      GIM_CheckFeatures, GIMT_Encode2(GIFBS_isGFX7Plus),
      GIM_CheckType, /*MI*/0, /*Op*/1, /*Type*/GILLT_s64,
      GIM_CheckRegBankForClass, /*MI*/0, /*Op*/0, /*RC*/GIMT_Encode2(AMDGPU::VReg_64RegClassID),
      GIM_CheckComplexPattern, /*MI*/0, /*Op*/1, /*Renderer*/GIMT_Encode2(0), GIMT_Encode2(GICP_gi_vop3mods0),
      // (fceil:{ *:[f64] } (VOP3Mods0:{ *:[f64] } f64:{ *:[f64] }:$src0, i32:{ *:[i32] }:$src0_modifiers, i1:{ *:[i1] }:$clamp, i32:{ *:[i32] }:$omod))  =>  (V_CEIL_F64_e64:{ *:[f64] } i32:{ *:[i32] }:$src0_modifiers, f64:{ *:[f64] }:$src0, i1:{ *:[i1] }:$clamp, i32:{ *:[i32] }:$omod)
      GIR_BuildMI, /*InsnID*/0, /*Opcode*/GIMT_Encode2(AMDGPU::V_CEIL_F64_e64),
      GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/0, // DstI[vdst]
      GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/1, // src0_modifiers
      GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/0, // src0
      GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/2, // clamp
      GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/3, // omod
      GIR_ConstrainSelectedInstOperands, /*InsnID*/0,
      GIR_EraseFromParent, /*InsnID*/0,
      // GIR_Coverage, 646,
      GIR_Done,
    // Label 5489: @403624
    GIM_Reject,
    // Label 5480: @403625
    GIM_Reject,
    // Label 96: @403626
    GIM_SwitchType, /*MI*/0, /*Op*/0, /*[*/GIMT_Encode2(8), GIMT_Encode2(10), /*)*//*default:*//*Label 5492*/ GIMT_Encode4(403954),
    /*GILLT_s16*//*Label 5490*/ GIMT_Encode4(403645),
    /*GILLT_s32*//*Label 5491*/ GIMT_Encode4(403892),
    // Label 5490: @403645
    GIM_Try, /*On fail goto*//*Label 5493*/ GIMT_Encode4(403891),
      GIM_CheckType, /*MI*/0, /*Op*/1, /*Type*/GILLT_s16,
      GIM_Try, /*On fail goto*//*Label 5494*/ GIMT_Encode4(403731), // Rule ID 2234 //
        GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasPseudoScalarTrans),
        GIM_CheckRegBankForClass, /*MI*/0, /*Op*/0, /*RC*/GIMT_Encode2(AMDGPU::SReg_32_XEXECRegClassID),
        GIM_CheckCxxInsnPredicate, /*MI*/0, /*FnId*/GIMT_Encode2(GICXXPred_MI_Predicate_anonymous_23776),
        GIM_CheckComplexPattern, /*MI*/0, /*Op*/1, /*Renderer*/GIMT_Encode2(0), GIMT_Encode2(GICP_gi_vop3mods0),
        // (fsqrt:{ *:[f16] } (VOP3Mods0:{ *:[f16] } f16:{ *:[f16] }:$src0, i32:{ *:[i32] }:$src0_modifiers, i1:{ *:[i1] }:$clamp, i32:{ *:[i32] }:$omod))<<P:Predicate_anonymous_23776>>  =>  (COPY_TO_REGCLASS:{ *:[f16] } (V_S_SQRT_F16_e64:{ *:[f32] } i32:{ *:[i32] }:$src0_modifiers, f16:{ *:[f16] }:$src0, i1:{ *:[i1] }:$clamp, i32:{ *:[i32] }:$omod), SReg_32_XEXEC:{ *:[i32] })
        GIR_MakeTempReg, /*TempRegID*/0, /*TypeID*/GILLT_s32,
        GIR_BuildMI, /*InsnID*/1, /*Opcode*/GIMT_Encode2(AMDGPU::V_S_SQRT_F16_e64),
        GIR_AddTempRegister, /*InsnID*/1, /*TempRegID*/0, /*TempRegFlags*/GIMT_Encode2(RegState::Define),
        GIR_ComplexSubOperandRenderer, /*InsnID*/1, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/1, // src0_modifiers
        GIR_ComplexSubOperandRenderer, /*InsnID*/1, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/0, // src0
        GIR_ComplexSubOperandRenderer, /*InsnID*/1, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/2, // clamp
        GIR_ComplexSubOperandRenderer, /*InsnID*/1, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/3, // omod
        GIR_ConstrainSelectedInstOperands, /*InsnID*/1,
        GIR_BuildMI, /*InsnID*/0, /*Opcode*/GIMT_Encode2(TargetOpcode::COPY),
        GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/0, // DstI[dst]
        GIR_AddSimpleTempRegister, /*InsnID*/0, /*TempRegID*/0,
        GIR_ConstrainOperandRC, /*InsnID*/0, /*Op*/0, GIMT_Encode2(AMDGPU::SReg_32_XEXECRegClassID),
        GIR_EraseFromParent, /*InsnID*/0,
        // GIR_Coverage, 2234,
        GIR_Done,
      // Label 5494: @403731
      GIM_Try, /*On fail goto*//*Label 5495*/ GIMT_Encode4(403784), // Rule ID 663 //
        GIM_CheckFeatures, GIMT_Encode2(GIFBS_Has16BitInsts_NotHasTrue16BitInsts),
        GIM_CheckRegBankForClass, /*MI*/0, /*Op*/0, /*RC*/GIMT_Encode2(AMDGPU::VGPR_32RegClassID),
        GIM_CheckComplexPattern, /*MI*/0, /*Op*/1, /*Renderer*/GIMT_Encode2(0), GIMT_Encode2(GICP_gi_vop3mods0),
        // (fsqrt:{ *:[f16] } (VOP3Mods0:{ *:[f16] } f16:{ *:[f16] }:$src0, i32:{ *:[i32] }:$src0_modifiers, i1:{ *:[i1] }:$clamp, i32:{ *:[i32] }:$omod))  =>  (V_SQRT_F16_e64:{ *:[f16] } i32:{ *:[i32] }:$src0_modifiers, f16:{ *:[f16] }:$src0, i1:{ *:[i1] }:$clamp, i32:{ *:[i32] }:$omod)
        GIR_BuildMI, /*InsnID*/0, /*Opcode*/GIMT_Encode2(AMDGPU::V_SQRT_F16_e64),
        GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/0, // DstI[vdst]
        GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/1, // src0_modifiers
        GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/0, // src0
        GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/2, // clamp
        GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/3, // omod
        GIR_ConstrainSelectedInstOperands, /*InsnID*/0,
        GIR_EraseFromParent, /*InsnID*/0,
        // GIR_Coverage, 663,
        GIR_Done,
      // Label 5495: @403784
      GIM_Try, /*On fail goto*//*Label 5496*/ GIMT_Encode4(403837), // Rule ID 665 //
        GIM_CheckFeatures, GIMT_Encode2(GIFBS_UseRealTrue16Insts),
        GIM_CheckRegBankForClass, /*MI*/0, /*Op*/0, /*RC*/GIMT_Encode2(AMDGPU::VGPR_16RegClassID),
        GIM_CheckComplexPattern, /*MI*/0, /*Op*/1, /*Renderer*/GIMT_Encode2(0), GIMT_Encode2(GICP_gi_vop3mods0),
        // (fsqrt:{ *:[f16] } (VOP3Mods0:{ *:[f16] } f16:{ *:[f16] }:$src0, i32:{ *:[i32] }:$src0_modifiers, i1:{ *:[i1] }:$clamp, i32:{ *:[i32] }:$omod))  =>  (V_SQRT_F16_t16_e64:{ *:[f16] } i32:{ *:[i32] }:$src0_modifiers, f16:{ *:[f16] }:$src0, i1:{ *:[i1] }:$clamp, i32:{ *:[i32] }:$omod)
        GIR_BuildMI, /*InsnID*/0, /*Opcode*/GIMT_Encode2(AMDGPU::V_SQRT_F16_t16_e64),
        GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/0, // DstI[vdst]
        GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/1, // src0_modifiers
        GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/0, // src0
        GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/2, // clamp
        GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/3, // omod
        GIR_ConstrainSelectedInstOperands, /*InsnID*/0,
        GIR_EraseFromParent, /*InsnID*/0,
        // GIR_Coverage, 665,
        GIR_Done,
      // Label 5496: @403837
      GIM_Try, /*On fail goto*//*Label 5497*/ GIMT_Encode4(403890), // Rule ID 667 //
        GIM_CheckFeatures, GIMT_Encode2(GIFBS_UseFakeTrue16Insts),
        GIM_CheckRegBankForClass, /*MI*/0, /*Op*/0, /*RC*/GIMT_Encode2(AMDGPU::VGPR_32RegClassID),
        GIM_CheckComplexPattern, /*MI*/0, /*Op*/1, /*Renderer*/GIMT_Encode2(0), GIMT_Encode2(GICP_gi_vop3mods0),
        // (fsqrt:{ *:[f16] } (VOP3Mods0:{ *:[f16] } f16:{ *:[f16] }:$src0, i32:{ *:[i32] }:$src0_modifiers, i1:{ *:[i1] }:$clamp, i32:{ *:[i32] }:$omod))  =>  (V_SQRT_F16_fake16_e64:{ *:[f16] } i32:{ *:[i32] }:$src0_modifiers, f16:{ *:[f16] }:$src0, i1:{ *:[i1] }:$clamp, i32:{ *:[i32] }:$omod)
        GIR_BuildMI, /*InsnID*/0, /*Opcode*/GIMT_Encode2(AMDGPU::V_SQRT_F16_fake16_e64),
        GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/0, // DstI[vdst]
        GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/1, // src0_modifiers
        GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/0, // src0
        GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/2, // clamp
        GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/3, // omod
        GIR_ConstrainSelectedInstOperands, /*InsnID*/0,
        GIR_EraseFromParent, /*InsnID*/0,
        // GIR_Coverage, 667,
        GIR_Done,
      // Label 5497: @403890
      GIM_Reject,
    // Label 5493: @403891
    GIM_Reject,
    // Label 5491: @403892
    GIM_Try, /*On fail goto*//*Label 5498*/ GIMT_Encode4(403953), // Rule ID 956 //
      GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasPseudoScalarTrans),
      GIM_CheckType, /*MI*/0, /*Op*/1, /*Type*/GILLT_s32,
      GIM_CheckRegBankForClass, /*MI*/0, /*Op*/0, /*RC*/GIMT_Encode2(AMDGPU::SReg_32_XEXECRegClassID),
      GIM_CheckCxxInsnPredicate, /*MI*/0, /*FnId*/GIMT_Encode2(GICXXPred_MI_Predicate_anonymous_23776),
      GIM_CheckComplexPattern, /*MI*/0, /*Op*/1, /*Renderer*/GIMT_Encode2(0), GIMT_Encode2(GICP_gi_vop3mods0),
      // (fsqrt:{ *:[f32] } (VOP3Mods0:{ *:[f32] } f32:{ *:[f32] }:$src0, i32:{ *:[i32] }:$src0_modifiers, i1:{ *:[i1] }:$clamp, i32:{ *:[i32] }:$omod))<<P:Predicate_anonymous_23776>>  =>  (V_S_SQRT_F32_e64:{ *:[f32] } i32:{ *:[i32] }:$src0_modifiers, f32:{ *:[f32] }:$src0, i1:{ *:[i1] }:$clamp, i32:{ *:[i32] }:$omod)
      GIR_BuildMI, /*InsnID*/0, /*Opcode*/GIMT_Encode2(AMDGPU::V_S_SQRT_F32_e64),
      GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/0, // DstI[vdst]
      GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/1, // src0_modifiers
      GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/0, // src0
      GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/2, // clamp
      GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/3, // omod
      GIR_ConstrainSelectedInstOperands, /*InsnID*/0,
      GIR_EraseFromParent, /*InsnID*/0,
      // GIR_Coverage, 956,
      GIR_Done,
    // Label 5498: @403953
    GIM_Reject,
    // Label 5492: @403954
    GIM_Reject,
    // Label 97: @403955
    GIM_SwitchType, /*MI*/0, /*Op*/0, /*[*/GIMT_Encode2(8), GIMT_Encode2(11), /*)*//*default:*//*Label 5502*/ GIMT_Encode4(404517),
    /*GILLT_s16*//*Label 5499*/ GIMT_Encode4(403978),
    /*GILLT_s32*//*Label 5500*/ GIMT_Encode4(404177),
    /*GILLT_s64*//*Label 5501*/ GIMT_Encode4(404267),
    // Label 5499: @403978
    GIM_Try, /*On fail goto*//*Label 5503*/ GIMT_Encode4(404176),
      GIM_CheckType, /*MI*/0, /*Op*/1, /*Type*/GILLT_s16,
      GIM_Try, /*On fail goto*//*Label 5504*/ GIMT_Encode4(404016), // Rule ID 38 //
        GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasSALUFloatInsts),
        GIM_CheckRegBankForClass, /*MI*/0, /*Op*/0, /*RC*/GIMT_Encode2(AMDGPU::SReg_32RegClassID),
        GIM_CheckCxxInsnPredicate, /*MI*/0, /*FnId*/GIMT_Encode2(GICXXPred_MI_Predicate_anonymous_17599),
        // (ffloor:{ *:[f16] } f16:{ *:[f16] }:$src0)<<P:Predicate_anonymous_17599>>  =>  (S_FLOOR_F16:{ *:[f16] } f16:{ *:[f16] }:$src0)
        GIR_MutateOpcode, /*InsnID*/0, /*RecycleInsnID*/0, /*Opcode*/GIMT_Encode2(AMDGPU::S_FLOOR_F16),
        GIR_AddImplicitUse, /*InsnID*/0, GIMT_Encode2(AMDGPU::MODE),
        GIR_ConstrainSelectedInstOperands, /*InsnID*/0,
        // GIR_Coverage, 38,
        GIR_Done,
      // Label 5504: @404016
      GIM_Try, /*On fail goto*//*Label 5505*/ GIMT_Encode4(404069), // Rule ID 704 //
        GIM_CheckFeatures, GIMT_Encode2(GIFBS_Has16BitInsts_NotHasTrue16BitInsts),
        GIM_CheckRegBankForClass, /*MI*/0, /*Op*/0, /*RC*/GIMT_Encode2(AMDGPU::VGPR_32RegClassID),
        GIM_CheckComplexPattern, /*MI*/0, /*Op*/1, /*Renderer*/GIMT_Encode2(0), GIMT_Encode2(GICP_gi_vop3mods0),
        // (ffloor:{ *:[f16] } (VOP3Mods0:{ *:[f16] } f16:{ *:[f16] }:$src0, i32:{ *:[i32] }:$src0_modifiers, i1:{ *:[i1] }:$clamp, i32:{ *:[i32] }:$omod))  =>  (V_FLOOR_F16_e64:{ *:[f16] } i32:{ *:[i32] }:$src0_modifiers, f16:{ *:[f16] }:$src0, i1:{ *:[i1] }:$clamp, i32:{ *:[i32] }:$omod)
        GIR_BuildMI, /*InsnID*/0, /*Opcode*/GIMT_Encode2(AMDGPU::V_FLOOR_F16_e64),
        GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/0, // DstI[vdst]
        GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/1, // src0_modifiers
        GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/0, // src0
        GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/2, // clamp
        GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/3, // omod
        GIR_ConstrainSelectedInstOperands, /*InsnID*/0,
        GIR_EraseFromParent, /*InsnID*/0,
        // GIR_Coverage, 704,
        GIR_Done,
      // Label 5505: @404069
      GIM_Try, /*On fail goto*//*Label 5506*/ GIMT_Encode4(404122), // Rule ID 705 //
        GIM_CheckFeatures, GIMT_Encode2(GIFBS_UseRealTrue16Insts),
        GIM_CheckRegBankForClass, /*MI*/0, /*Op*/0, /*RC*/GIMT_Encode2(AMDGPU::VGPR_16RegClassID),
        GIM_CheckComplexPattern, /*MI*/0, /*Op*/1, /*Renderer*/GIMT_Encode2(0), GIMT_Encode2(GICP_gi_vop3mods0),
        // (ffloor:{ *:[f16] } (VOP3Mods0:{ *:[f16] } f16:{ *:[f16] }:$src0, i32:{ *:[i32] }:$src0_modifiers, i1:{ *:[i1] }:$clamp, i32:{ *:[i32] }:$omod))  =>  (V_FLOOR_F16_t16_e64:{ *:[f16] } i32:{ *:[i32] }:$src0_modifiers, f16:{ *:[f16] }:$src0, i1:{ *:[i1] }:$clamp, i32:{ *:[i32] }:$omod)
        GIR_BuildMI, /*InsnID*/0, /*Opcode*/GIMT_Encode2(AMDGPU::V_FLOOR_F16_t16_e64),
        GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/0, // DstI[vdst]
        GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/1, // src0_modifiers
        GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/0, // src0
        GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/2, // clamp
        GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/3, // omod
        GIR_ConstrainSelectedInstOperands, /*InsnID*/0,
        GIR_EraseFromParent, /*InsnID*/0,
        // GIR_Coverage, 705,
        GIR_Done,
      // Label 5506: @404122
      GIM_Try, /*On fail goto*//*Label 5507*/ GIMT_Encode4(404175), // Rule ID 706 //
        GIM_CheckFeatures, GIMT_Encode2(GIFBS_UseFakeTrue16Insts),
        GIM_CheckRegBankForClass, /*MI*/0, /*Op*/0, /*RC*/GIMT_Encode2(AMDGPU::VGPR_32RegClassID),
        GIM_CheckComplexPattern, /*MI*/0, /*Op*/1, /*Renderer*/GIMT_Encode2(0), GIMT_Encode2(GICP_gi_vop3mods0),
        // (ffloor:{ *:[f16] } (VOP3Mods0:{ *:[f16] } f16:{ *:[f16] }:$src0, i32:{ *:[i32] }:$src0_modifiers, i1:{ *:[i1] }:$clamp, i32:{ *:[i32] }:$omod))  =>  (V_FLOOR_F16_fake16_e64:{ *:[f16] } i32:{ *:[i32] }:$src0_modifiers, f16:{ *:[f16] }:$src0, i1:{ *:[i1] }:$clamp, i32:{ *:[i32] }:$omod)
        GIR_BuildMI, /*InsnID*/0, /*Opcode*/GIMT_Encode2(AMDGPU::V_FLOOR_F16_fake16_e64),
        GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/0, // DstI[vdst]
        GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/1, // src0_modifiers
        GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/0, // src0
        GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/2, // clamp
        GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/3, // omod
        GIR_ConstrainSelectedInstOperands, /*InsnID*/0,
        GIR_EraseFromParent, /*InsnID*/0,
        // GIR_Coverage, 706,
        GIR_Done,
      // Label 5507: @404175
      GIM_Reject,
    // Label 5503: @404176
    GIM_Reject,
    // Label 5500: @404177
    GIM_Try, /*On fail goto*//*Label 5508*/ GIMT_Encode4(404266),
      GIM_CheckType, /*MI*/0, /*Op*/1, /*Type*/GILLT_s32,
      GIM_Try, /*On fail goto*//*Label 5509*/ GIMT_Encode4(404215), // Rule ID 33 //
        GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasSALUFloatInsts),
        GIM_CheckRegBankForClass, /*MI*/0, /*Op*/0, /*RC*/GIMT_Encode2(AMDGPU::SReg_32RegClassID),
        GIM_CheckCxxInsnPredicate, /*MI*/0, /*FnId*/GIMT_Encode2(GICXXPred_MI_Predicate_anonymous_17599),
        // (ffloor:{ *:[f32] } f32:{ *:[f32] }:$src0)<<P:Predicate_anonymous_17599>>  =>  (S_FLOOR_F32:{ *:[f32] } f32:{ *:[f32] }:$src0)
        GIR_MutateOpcode, /*InsnID*/0, /*RecycleInsnID*/0, /*Opcode*/GIMT_Encode2(AMDGPU::S_FLOOR_F32),
        GIR_AddImplicitUse, /*InsnID*/0, GIMT_Encode2(AMDGPU::MODE),
        GIR_ConstrainSelectedInstOperands, /*InsnID*/0,
        // GIR_Coverage, 33,
        GIR_Done,
      // Label 5509: @404215
      GIM_Try, /*On fail goto*//*Label 5510*/ GIMT_Encode4(404265), // Rule ID 604 //
        GIM_CheckRegBankForClass, /*MI*/0, /*Op*/0, /*RC*/GIMT_Encode2(AMDGPU::VGPR_32RegClassID),
        GIM_CheckComplexPattern, /*MI*/0, /*Op*/1, /*Renderer*/GIMT_Encode2(0), GIMT_Encode2(GICP_gi_vop3mods0),
        // (ffloor:{ *:[f32] } (VOP3Mods0:{ *:[f32] } f32:{ *:[f32] }:$src0, i32:{ *:[i32] }:$src0_modifiers, i1:{ *:[i1] }:$clamp, i32:{ *:[i32] }:$omod))  =>  (V_FLOOR_F32_e64:{ *:[f32] } i32:{ *:[i32] }:$src0_modifiers, f32:{ *:[f32] }:$src0, i1:{ *:[i1] }:$clamp, i32:{ *:[i32] }:$omod)
        GIR_BuildMI, /*InsnID*/0, /*Opcode*/GIMT_Encode2(AMDGPU::V_FLOOR_F32_e64),
        GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/0, // DstI[vdst]
        GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/1, // src0_modifiers
        GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/0, // src0
        GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/2, // clamp
        GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/3, // omod
        GIR_ConstrainSelectedInstOperands, /*InsnID*/0,
        GIR_EraseFromParent, /*InsnID*/0,
        // GIR_Coverage, 604,
        GIR_Done,
      // Label 5510: @404265
      GIM_Reject,
    // Label 5508: @404266
    GIM_Reject,
    // Label 5501: @404267
    GIM_Try, /*On fail goto*//*Label 5511*/ GIMT_Encode4(404516),
      GIM_CheckType, /*MI*/0, /*Op*/1, /*Type*/GILLT_s64,
      GIM_CheckRegBankForClass, /*MI*/0, /*Op*/0, /*RC*/GIMT_Encode2(AMDGPU::VReg_64RegClassID),
      GIM_Try, /*On fail goto*//*Label 5512*/ GIMT_Encode4(404467), // Rule ID 6461 //
        GIM_CheckFeatures, GIMT_Encode2(GIFBS_isGFX6),
        GIM_CheckComplexPattern, /*MI*/0, /*Op*/1, /*Renderer*/GIMT_Encode2(0), GIMT_Encode2(GICP_gi_vop3mods),
        // (ffloor:{ *:[f64] } (VOP3Mods:{ *:[f64] } f64:{ *:[f64] }:$x, i32:{ *:[i32] }:$mods))  =>  (V_ADD_F64_e64:{ *:[f64] } ?:{ *:[i32] }:$mods, ?:{ *:[f64] }:$x, 1:{ *:[i32] }, (V_CNDMASK_B64_PSEUDO:{ *:[i64] } (V_MIN_F64_e64:{ *:[i64] } 0:{ *:[i32] }, (V_FRACT_F64_e64:{ *:[i64] } ?:{ *:[i32] }:$mods, ?:{ *:[f64] }:$x), 0:{ *:[i32] }, (V_MOV_B64_PSEUDO:{ *:[i64] } 4607182418800017407:{ *:[i64] })), ?:{ *:[f64] }:$x, (V_CMP_CLASS_F64_e64:{ *:[i1] } 0:{ *:[i32] }, ?:{ *:[f64] }:$x, 3:{ *:[i32] })))
        GIR_MakeTempReg, /*TempRegID*/0, /*TypeID*/GILLT_s64,
        GIR_MakeTempReg, /*TempRegID*/1, /*TypeID*/GILLT_s64,
        GIR_MakeTempReg, /*TempRegID*/2, /*TypeID*/GILLT_s64,
        GIR_MakeTempReg, /*TempRegID*/3, /*TypeID*/GILLT_s64,
        GIR_MakeTempReg, /*TempRegID*/4, /*TypeID*/GILLT_s1,
        GIR_BuildMI, /*InsnID*/5, /*Opcode*/GIMT_Encode2(AMDGPU::V_CMP_CLASS_F64_e64),
        GIR_AddTempRegister, /*InsnID*/5, /*TempRegID*/4, /*TempRegFlags*/GIMT_Encode2(RegState::Define),
        GIR_AddImm8, /*InsnID*/5, /*Imm*/0,
        GIR_ComplexSubOperandRenderer, /*InsnID*/5, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/0, // x
        GIR_AddImm8, /*InsnID*/5, /*Imm*/3,
        GIR_ConstrainSelectedInstOperands, /*InsnID*/5,
        GIR_BuildMI, /*InsnID*/4, /*Opcode*/GIMT_Encode2(AMDGPU::V_MOV_B64_PSEUDO),
        GIR_AddTempRegister, /*InsnID*/4, /*TempRegID*/3, /*TempRegFlags*/GIMT_Encode2(RegState::Define),
        GIR_AddImm, /*InsnID*/4, /*Imm*/GIMT_Encode8(4607182418800017407),
        GIR_ConstrainSelectedInstOperands, /*InsnID*/4,
        GIR_BuildMI, /*InsnID*/3, /*Opcode*/GIMT_Encode2(AMDGPU::V_FRACT_F64_e64),
        GIR_AddTempRegister, /*InsnID*/3, /*TempRegID*/2, /*TempRegFlags*/GIMT_Encode2(RegState::Define),
        GIR_ComplexSubOperandRenderer, /*InsnID*/3, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/1, // mods
        GIR_ComplexSubOperandRenderer, /*InsnID*/3, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/0, // x
        GIR_AddImm8, /*InsnID*/3, /*Imm*/0,
        GIR_AddImm8, /*InsnID*/3, /*Imm*/0,
        GIR_ConstrainSelectedInstOperands, /*InsnID*/3,
        GIR_BuildMI, /*InsnID*/2, /*Opcode*/GIMT_Encode2(AMDGPU::V_MIN_F64_e64),
        GIR_AddTempRegister, /*InsnID*/2, /*TempRegID*/1, /*TempRegFlags*/GIMT_Encode2(RegState::Define),
        GIR_AddImm8, /*InsnID*/2, /*Imm*/0,
        GIR_AddSimpleTempRegister, /*InsnID*/2, /*TempRegID*/2,
        GIR_AddImm8, /*InsnID*/2, /*Imm*/0,
        GIR_AddSimpleTempRegister, /*InsnID*/2, /*TempRegID*/3,
        GIR_AddImm8, /*InsnID*/2, /*Imm*/0,
        GIR_AddImm8, /*InsnID*/2, /*Imm*/0,
        GIR_ConstrainSelectedInstOperands, /*InsnID*/2,
        GIR_BuildMI, /*InsnID*/1, /*Opcode*/GIMT_Encode2(AMDGPU::V_CNDMASK_B64_PSEUDO),
        GIR_AddTempRegister, /*InsnID*/1, /*TempRegID*/0, /*TempRegFlags*/GIMT_Encode2(RegState::Define),
        GIR_AddSimpleTempRegister, /*InsnID*/1, /*TempRegID*/1,
        GIR_ComplexSubOperandRenderer, /*InsnID*/1, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/0, // x
        GIR_AddSimpleTempRegister, /*InsnID*/1, /*TempRegID*/4,
        GIR_ConstrainSelectedInstOperands, /*InsnID*/1,
        GIR_BuildMI, /*InsnID*/0, /*Opcode*/GIMT_Encode2(AMDGPU::V_ADD_F64_e64),
        GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/0, // DstI[vdst]
        GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/1, // mods
        GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/0, // x
        GIR_AddImm8, /*InsnID*/0, /*Imm*/1,
        GIR_AddSimpleTempRegister, /*InsnID*/0, /*TempRegID*/0,
        GIR_AddImm8, /*InsnID*/0, /*Imm*/0,
        GIR_AddImm8, /*InsnID*/0, /*Imm*/0,
        GIR_ConstrainSelectedInstOperands, /*InsnID*/0,
        GIR_EraseFromParent, /*InsnID*/0,
        // GIR_Coverage, 6461,
        GIR_Done,
      // Label 5512: @404467
      GIM_Try, /*On fail goto*//*Label 5513*/ GIMT_Encode4(404515), // Rule ID 648 //
        GIM_CheckFeatures, GIMT_Encode2(GIFBS_isGFX7Plus),
        GIM_CheckComplexPattern, /*MI*/0, /*Op*/1, /*Renderer*/GIMT_Encode2(0), GIMT_Encode2(GICP_gi_vop3mods0),
        // (ffloor:{ *:[f64] } (VOP3Mods0:{ *:[f64] } f64:{ *:[f64] }:$src0, i32:{ *:[i32] }:$src0_modifiers, i1:{ *:[i1] }:$clamp, i32:{ *:[i32] }:$omod))  =>  (V_FLOOR_F64_e64:{ *:[f64] } i32:{ *:[i32] }:$src0_modifiers, f64:{ *:[f64] }:$src0, i1:{ *:[i1] }:$clamp, i32:{ *:[i32] }:$omod)
        GIR_BuildMI, /*InsnID*/0, /*Opcode*/GIMT_Encode2(AMDGPU::V_FLOOR_F64_e64),
        GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/0, // DstI[vdst]
        GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/1, // src0_modifiers
        GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/0, // src0
        GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/2, // clamp
        GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/3, // omod
        GIR_ConstrainSelectedInstOperands, /*InsnID*/0,
        GIR_EraseFromParent, /*InsnID*/0,
        // GIR_Coverage, 648,
        GIR_Done,
      // Label 5513: @404515
      GIM_Reject,
    // Label 5511: @404516
    GIM_Reject,
    // Label 5502: @404517
    GIM_Reject,
    // Label 98: @404518
    GIM_SwitchType, /*MI*/0, /*Op*/0, /*[*/GIMT_Encode2(8), GIMT_Encode2(13), /*)*//*default:*//*Label 5519*/ GIMT_Encode4(405656),
    /*GILLT_s16*//*Label 5514*/ GIMT_Encode4(404549),
    /*GILLT_s32*//*Label 5515*/ GIMT_Encode4(405023),
    /*GILLT_s64*//*Label 5516*/ GIMT_Encode4(405211),
    /*GILLT_v2s16*//*Label 5517*/ GIMT_Encode4(405491),
    /*GILLT_v2s32*//*Label 5518*/ GIMT_Encode4(405572),
    // Label 5514: @404549
    GIM_Try, /*On fail goto*//*Label 5520*/ GIMT_Encode4(405022),
      GIM_CheckType, /*MI*/0, /*Op*/1, /*Type*/GILLT_s16,
      GIM_CheckType, /*MI*/0, /*Op*/2, /*Type*/GILLT_s16,
      GIM_Try, /*On fail goto*//*Label 5521*/ GIMT_Encode4(404601), // Rule ID 98 //
        GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasSALUFloatInsts),
        GIM_CheckRegBankForClass, /*MI*/0, /*Op*/0, /*RC*/GIMT_Encode2(AMDGPU::SReg_32RegClassID),
        GIM_CheckRegBankForClass, /*MI*/0, /*Op*/1, /*RC*/GIMT_Encode2(AMDGPU::SReg_32RegClassID),
        GIM_CheckRegBankForClass, /*MI*/0, /*Op*/2, /*RC*/GIMT_Encode2(AMDGPU::SReg_32RegClassID),
        GIM_CheckCxxInsnPredicate, /*MI*/0, /*FnId*/GIMT_Encode2(GICXXPred_MI_Predicate_anonymous_17630),
        // (strict_fadd:{ *:[f16] } SSrc_f16:{ *:[f16] }:$src0, SSrc_f16:{ *:[f16] }:$src1)<<P:Predicate_anonymous_17630>>  =>  (S_ADD_F16:{ *:[f16] } SSrc_f16:{ *:[f16] }:$src0, SSrc_f16:{ *:[f16] }:$src1)
        GIR_MutateOpcode, /*InsnID*/0, /*RecycleInsnID*/0, /*Opcode*/GIMT_Encode2(AMDGPU::S_ADD_F16),
        GIR_AddImplicitUse, /*InsnID*/0, GIMT_Encode2(AMDGPU::MODE),
        GIR_ConstrainSelectedInstOperands, /*InsnID*/0,
        // GIR_Coverage, 98,
        GIR_Done,
      // Label 5521: @404601
      GIM_Try, /*On fail goto*//*Label 5522*/ GIMT_Encode4(404671), // Rule ID 793 //
        GIM_CheckFeatures, GIMT_Encode2(GIFBS_Has16BitInsts_NotHasTrue16BitInsts),
        GIM_CheckRegBankForClass, /*MI*/0, /*Op*/0, /*RC*/GIMT_Encode2(AMDGPU::VGPR_32RegClassID),
        GIM_CheckComplexPattern, /*MI*/0, /*Op*/1, /*Renderer*/GIMT_Encode2(0), GIMT_Encode2(GICP_gi_vop3mods0),
        GIM_CheckComplexPattern, /*MI*/0, /*Op*/2, /*Renderer*/GIMT_Encode2(1), GIMT_Encode2(GICP_gi_vop3mods),
        // (strict_fadd:{ *:[f16] } (VOP3Mods0:{ *:[f16] } f16:{ *:[f16] }:$src0, i32:{ *:[i32] }:$src0_modifiers, i1:{ *:[i1] }:$clamp, i32:{ *:[i32] }:$omod), (VOP3Mods:{ *:[f16] } f16:{ *:[f16] }:$src1, i32:{ *:[i32] }:$src1_modifiers))  =>  (V_ADD_F16_e64:{ *:[f16] } i32:{ *:[i32] }:$src0_modifiers, f16:{ *:[f16] }:$src0, i32:{ *:[i32] }:$src1_modifiers, f16:{ *:[f16] }:$src1, i1:{ *:[i1] }:$clamp, i32:{ *:[i32] }:$omod)
        GIR_BuildMI, /*InsnID*/0, /*Opcode*/GIMT_Encode2(AMDGPU::V_ADD_F16_e64),
        GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/0, // DstI[vdst]
        GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/1, // src0_modifiers
        GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/0, // src0
        GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(1), /*SubOperand*/1, // src1_modifiers
        GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(1), /*SubOperand*/0, // src1
        GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/2, // clamp
        GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/3, // omod
        GIR_ConstrainSelectedInstOperands, /*InsnID*/0,
        GIR_EraseFromParent, /*InsnID*/0,
        // GIR_Coverage, 793,
        GIR_Done,
      // Label 5522: @404671
      GIM_Try, /*On fail goto*//*Label 5523*/ GIMT_Encode4(404741), // Rule ID 795 //
        GIM_CheckFeatures, GIMT_Encode2(GIFBS_UseRealTrue16Insts),
        GIM_CheckRegBankForClass, /*MI*/0, /*Op*/0, /*RC*/GIMT_Encode2(AMDGPU::VGPR_16RegClassID),
        GIM_CheckComplexPattern, /*MI*/0, /*Op*/1, /*Renderer*/GIMT_Encode2(0), GIMT_Encode2(GICP_gi_vop3mods0),
        GIM_CheckComplexPattern, /*MI*/0, /*Op*/2, /*Renderer*/GIMT_Encode2(1), GIMT_Encode2(GICP_gi_vop3mods),
        // (strict_fadd:{ *:[f16] } (VOP3Mods0:{ *:[f16] } f16:{ *:[f16] }:$src0, i32:{ *:[i32] }:$src0_modifiers, i1:{ *:[i1] }:$clamp, i32:{ *:[i32] }:$omod), (VOP3Mods:{ *:[f16] } f16:{ *:[f16] }:$src1, i32:{ *:[i32] }:$src1_modifiers))  =>  (V_ADD_F16_t16_e64:{ *:[f16] } i32:{ *:[i32] }:$src0_modifiers, f16:{ *:[f16] }:$src0, i32:{ *:[i32] }:$src1_modifiers, f16:{ *:[f16] }:$src1, i1:{ *:[i1] }:$clamp, i32:{ *:[i32] }:$omod)
        GIR_BuildMI, /*InsnID*/0, /*Opcode*/GIMT_Encode2(AMDGPU::V_ADD_F16_t16_e64),
        GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/0, // DstI[vdst]
        GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/1, // src0_modifiers
        GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/0, // src0
        GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(1), /*SubOperand*/1, // src1_modifiers
        GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(1), /*SubOperand*/0, // src1
        GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/2, // clamp
        GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/3, // omod
        GIR_ConstrainSelectedInstOperands, /*InsnID*/0,
        GIR_EraseFromParent, /*InsnID*/0,
        // GIR_Coverage, 795,
        GIR_Done,
      // Label 5523: @404741
      GIM_Try, /*On fail goto*//*Label 5524*/ GIMT_Encode4(404811), // Rule ID 797 //
        GIM_CheckFeatures, GIMT_Encode2(GIFBS_UseFakeTrue16Insts),
        GIM_CheckRegBankForClass, /*MI*/0, /*Op*/0, /*RC*/GIMT_Encode2(AMDGPU::VGPR_32RegClassID),
        GIM_CheckComplexPattern, /*MI*/0, /*Op*/1, /*Renderer*/GIMT_Encode2(0), GIMT_Encode2(GICP_gi_vop3mods0),
        GIM_CheckComplexPattern, /*MI*/0, /*Op*/2, /*Renderer*/GIMT_Encode2(1), GIMT_Encode2(GICP_gi_vop3mods),
        // (strict_fadd:{ *:[f16] } (VOP3Mods0:{ *:[f16] } f16:{ *:[f16] }:$src0, i32:{ *:[i32] }:$src0_modifiers, i1:{ *:[i1] }:$clamp, i32:{ *:[i32] }:$omod), (VOP3Mods:{ *:[f16] } f16:{ *:[f16] }:$src1, i32:{ *:[i32] }:$src1_modifiers))  =>  (V_ADD_F16_fake16_e64:{ *:[f16] } i32:{ *:[i32] }:$src0_modifiers, f16:{ *:[f16] }:$src0, i32:{ *:[i32] }:$src1_modifiers, f16:{ *:[f16] }:$src1, i1:{ *:[i1] }:$clamp, i32:{ *:[i32] }:$omod)
        GIR_BuildMI, /*InsnID*/0, /*Opcode*/GIMT_Encode2(AMDGPU::V_ADD_F16_fake16_e64),
        GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/0, // DstI[vdst]
        GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/1, // src0_modifiers
        GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/0, // src0
        GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(1), /*SubOperand*/1, // src1_modifiers
        GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(1), /*SubOperand*/0, // src1
        GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/2, // clamp
        GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/3, // omod
        GIR_ConstrainSelectedInstOperands, /*InsnID*/0,
        GIR_EraseFromParent, /*InsnID*/0,
        // GIR_Coverage, 797,
        GIR_Done,
      // Label 5524: @404811
      GIM_Try, /*On fail goto*//*Label 5525*/ GIMT_Encode4(404881), // Rule ID 7136 //
        GIM_CheckFeatures, GIMT_Encode2(GIFBS_Has16BitInsts_NotHasTrue16BitInsts),
        GIM_CheckRegBankForClass, /*MI*/0, /*Op*/0, /*RC*/GIMT_Encode2(AMDGPU::VGPR_32RegClassID),
        GIM_CheckComplexPattern, /*MI*/0, /*Op*/1, /*Renderer*/GIMT_Encode2(0), GIMT_Encode2(GICP_gi_vop3mods),
        GIM_CheckComplexPattern, /*MI*/0, /*Op*/2, /*Renderer*/GIMT_Encode2(1), GIMT_Encode2(GICP_gi_vop3mods0),
        // (strict_fadd:{ *:[f16] } (VOP3Mods:{ *:[f16] } f16:{ *:[f16] }:$src1, i32:{ *:[i32] }:$src1_modifiers), (VOP3Mods0:{ *:[f16] } f16:{ *:[f16] }:$src0, i32:{ *:[i32] }:$src0_modifiers, i1:{ *:[i1] }:$clamp, i32:{ *:[i32] }:$omod))  =>  (V_ADD_F16_e64:{ *:[f16] } i32:{ *:[i32] }:$src0_modifiers, f16:{ *:[f16] }:$src0, i32:{ *:[i32] }:$src1_modifiers, f16:{ *:[f16] }:$src1, i1:{ *:[i1] }:$clamp, i32:{ *:[i32] }:$omod)
        GIR_BuildMI, /*InsnID*/0, /*Opcode*/GIMT_Encode2(AMDGPU::V_ADD_F16_e64),
        GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/0, // DstI[vdst]
        GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(1), /*SubOperand*/1, // src0_modifiers
        GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(1), /*SubOperand*/0, // src0
        GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/1, // src1_modifiers
        GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/0, // src1
        GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(1), /*SubOperand*/2, // clamp
        GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(1), /*SubOperand*/3, // omod
        GIR_ConstrainSelectedInstOperands, /*InsnID*/0,
        GIR_EraseFromParent, /*InsnID*/0,
        // GIR_Coverage, 7136,
        GIR_Done,
      // Label 5525: @404881
      GIM_Try, /*On fail goto*//*Label 5526*/ GIMT_Encode4(404951), // Rule ID 7138 //
        GIM_CheckFeatures, GIMT_Encode2(GIFBS_UseRealTrue16Insts),
        GIM_CheckRegBankForClass, /*MI*/0, /*Op*/0, /*RC*/GIMT_Encode2(AMDGPU::VGPR_16RegClassID),
        GIM_CheckComplexPattern, /*MI*/0, /*Op*/1, /*Renderer*/GIMT_Encode2(0), GIMT_Encode2(GICP_gi_vop3mods),
        GIM_CheckComplexPattern, /*MI*/0, /*Op*/2, /*Renderer*/GIMT_Encode2(1), GIMT_Encode2(GICP_gi_vop3mods0),
        // (strict_fadd:{ *:[f16] } (VOP3Mods:{ *:[f16] } f16:{ *:[f16] }:$src1, i32:{ *:[i32] }:$src1_modifiers), (VOP3Mods0:{ *:[f16] } f16:{ *:[f16] }:$src0, i32:{ *:[i32] }:$src0_modifiers, i1:{ *:[i1] }:$clamp, i32:{ *:[i32] }:$omod))  =>  (V_ADD_F16_t16_e64:{ *:[f16] } i32:{ *:[i32] }:$src0_modifiers, f16:{ *:[f16] }:$src0, i32:{ *:[i32] }:$src1_modifiers, f16:{ *:[f16] }:$src1, i1:{ *:[i1] }:$clamp, i32:{ *:[i32] }:$omod)
        GIR_BuildMI, /*InsnID*/0, /*Opcode*/GIMT_Encode2(AMDGPU::V_ADD_F16_t16_e64),
        GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/0, // DstI[vdst]
        GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(1), /*SubOperand*/1, // src0_modifiers
        GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(1), /*SubOperand*/0, // src0
        GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/1, // src1_modifiers
        GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/0, // src1
        GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(1), /*SubOperand*/2, // clamp
        GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(1), /*SubOperand*/3, // omod
        GIR_ConstrainSelectedInstOperands, /*InsnID*/0,
        GIR_EraseFromParent, /*InsnID*/0,
        // GIR_Coverage, 7138,
        GIR_Done,
      // Label 5526: @404951
      GIM_Try, /*On fail goto*//*Label 5527*/ GIMT_Encode4(405021), // Rule ID 7140 //
        GIM_CheckFeatures, GIMT_Encode2(GIFBS_UseFakeTrue16Insts),
        GIM_CheckRegBankForClass, /*MI*/0, /*Op*/0, /*RC*/GIMT_Encode2(AMDGPU::VGPR_32RegClassID),
        GIM_CheckComplexPattern, /*MI*/0, /*Op*/1, /*Renderer*/GIMT_Encode2(0), GIMT_Encode2(GICP_gi_vop3mods),
        GIM_CheckComplexPattern, /*MI*/0, /*Op*/2, /*Renderer*/GIMT_Encode2(1), GIMT_Encode2(GICP_gi_vop3mods0),
        // (strict_fadd:{ *:[f16] } (VOP3Mods:{ *:[f16] } f16:{ *:[f16] }:$src1, i32:{ *:[i32] }:$src1_modifiers), (VOP3Mods0:{ *:[f16] } f16:{ *:[f16] }:$src0, i32:{ *:[i32] }:$src0_modifiers, i1:{ *:[i1] }:$clamp, i32:{ *:[i32] }:$omod))  =>  (V_ADD_F16_fake16_e64:{ *:[f16] } i32:{ *:[i32] }:$src0_modifiers, f16:{ *:[f16] }:$src0, i32:{ *:[i32] }:$src1_modifiers, f16:{ *:[f16] }:$src1, i1:{ *:[i1] }:$clamp, i32:{ *:[i32] }:$omod)
        GIR_BuildMI, /*InsnID*/0, /*Opcode*/GIMT_Encode2(AMDGPU::V_ADD_F16_fake16_e64),
        GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/0, // DstI[vdst]
        GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(1), /*SubOperand*/1, // src0_modifiers
        GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(1), /*SubOperand*/0, // src0
        GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/1, // src1_modifiers
        GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/0, // src1
        GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(1), /*SubOperand*/2, // clamp
        GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(1), /*SubOperand*/3, // omod
        GIR_ConstrainSelectedInstOperands, /*InsnID*/0,
        GIR_EraseFromParent, /*InsnID*/0,
        // GIR_Coverage, 7140,
        GIR_Done,
      // Label 5527: @405021
      GIM_Reject,
    // Label 5520: @405022
    GIM_Reject,
    // Label 5515: @405023
    GIM_Try, /*On fail goto*//*Label 5528*/ GIMT_Encode4(405210),
      GIM_CheckType, /*MI*/0, /*Op*/1, /*Type*/GILLT_s32,
      GIM_CheckType, /*MI*/0, /*Op*/2, /*Type*/GILLT_s32,
      GIM_Try, /*On fail goto*//*Label 5529*/ GIMT_Encode4(405075), // Rule ID 90 //
        GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasSALUFloatInsts),
        GIM_CheckRegBankForClass, /*MI*/0, /*Op*/0, /*RC*/GIMT_Encode2(AMDGPU::SReg_32RegClassID),
        GIM_CheckRegBankForClass, /*MI*/0, /*Op*/1, /*RC*/GIMT_Encode2(AMDGPU::SReg_32RegClassID),
        GIM_CheckRegBankForClass, /*MI*/0, /*Op*/2, /*RC*/GIMT_Encode2(AMDGPU::SReg_32RegClassID),
        GIM_CheckCxxInsnPredicate, /*MI*/0, /*FnId*/GIMT_Encode2(GICXXPred_MI_Predicate_anonymous_17630),
        // (strict_fadd:{ *:[f32] } SSrc_f32:{ *:[f32] }:$src0, SSrc_f32:{ *:[f32] }:$src1)<<P:Predicate_anonymous_17630>>  =>  (S_ADD_F32:{ *:[f32] } SSrc_f32:{ *:[f32] }:$src0, SSrc_f32:{ *:[f32] }:$src1)
        GIR_MutateOpcode, /*InsnID*/0, /*RecycleInsnID*/0, /*Opcode*/GIMT_Encode2(AMDGPU::S_ADD_F32),
        GIR_AddImplicitUse, /*InsnID*/0, GIMT_Encode2(AMDGPU::MODE),
        GIR_ConstrainSelectedInstOperands, /*InsnID*/0,
        // GIR_Coverage, 90,
        GIR_Done,
      // Label 5529: @405075
      GIM_Try, /*On fail goto*//*Label 5530*/ GIMT_Encode4(405142), // Rule ID 723 //
        GIM_CheckRegBankForClass, /*MI*/0, /*Op*/0, /*RC*/GIMT_Encode2(AMDGPU::VGPR_32RegClassID),
        GIM_CheckComplexPattern, /*MI*/0, /*Op*/1, /*Renderer*/GIMT_Encode2(0), GIMT_Encode2(GICP_gi_vop3mods0),
        GIM_CheckComplexPattern, /*MI*/0, /*Op*/2, /*Renderer*/GIMT_Encode2(1), GIMT_Encode2(GICP_gi_vop3mods),
        // (strict_fadd:{ *:[f32] } (VOP3Mods0:{ *:[f32] } f32:{ *:[f32] }:$src0, i32:{ *:[i32] }:$src0_modifiers, i1:{ *:[i1] }:$clamp, i32:{ *:[i32] }:$omod), (VOP3Mods:{ *:[f32] } f32:{ *:[f32] }:$src1, i32:{ *:[i32] }:$src1_modifiers))  =>  (V_ADD_F32_e64:{ *:[f32] } i32:{ *:[i32] }:$src0_modifiers, f32:{ *:[f32] }:$src0, i32:{ *:[i32] }:$src1_modifiers, f32:{ *:[f32] }:$src1, i1:{ *:[i1] }:$clamp, i32:{ *:[i32] }:$omod)
        GIR_BuildMI, /*InsnID*/0, /*Opcode*/GIMT_Encode2(AMDGPU::V_ADD_F32_e64),
        GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/0, // DstI[vdst]
        GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/1, // src0_modifiers
        GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/0, // src0
        GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(1), /*SubOperand*/1, // src1_modifiers
        GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(1), /*SubOperand*/0, // src1
        GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/2, // clamp
        GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/3, // omod
        GIR_ConstrainSelectedInstOperands, /*InsnID*/0,
        GIR_EraseFromParent, /*InsnID*/0,
        // GIR_Coverage, 723,
        GIR_Done,
      // Label 5530: @405142
      GIM_Try, /*On fail goto*//*Label 5531*/ GIMT_Encode4(405209), // Rule ID 7125 //
        GIM_CheckRegBankForClass, /*MI*/0, /*Op*/0, /*RC*/GIMT_Encode2(AMDGPU::VGPR_32RegClassID),
        GIM_CheckComplexPattern, /*MI*/0, /*Op*/1, /*Renderer*/GIMT_Encode2(0), GIMT_Encode2(GICP_gi_vop3mods),
        GIM_CheckComplexPattern, /*MI*/0, /*Op*/2, /*Renderer*/GIMT_Encode2(1), GIMT_Encode2(GICP_gi_vop3mods0),
        // (strict_fadd:{ *:[f32] } (VOP3Mods:{ *:[f32] } f32:{ *:[f32] }:$src1, i32:{ *:[i32] }:$src1_modifiers), (VOP3Mods0:{ *:[f32] } f32:{ *:[f32] }:$src0, i32:{ *:[i32] }:$src0_modifiers, i1:{ *:[i1] }:$clamp, i32:{ *:[i32] }:$omod))  =>  (V_ADD_F32_e64:{ *:[f32] } i32:{ *:[i32] }:$src0_modifiers, f32:{ *:[f32] }:$src0, i32:{ *:[i32] }:$src1_modifiers, f32:{ *:[f32] }:$src1, i1:{ *:[i1] }:$clamp, i32:{ *:[i32] }:$omod)
        GIR_BuildMI, /*InsnID*/0, /*Opcode*/GIMT_Encode2(AMDGPU::V_ADD_F32_e64),
        GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/0, // DstI[vdst]
        GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(1), /*SubOperand*/1, // src0_modifiers
        GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(1), /*SubOperand*/0, // src0
        GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/1, // src1_modifiers
        GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/0, // src1
        GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(1), /*SubOperand*/2, // clamp
        GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(1), /*SubOperand*/3, // omod
        GIR_ConstrainSelectedInstOperands, /*InsnID*/0,
        GIR_EraseFromParent, /*InsnID*/0,
        // GIR_Coverage, 7125,
        GIR_Done,
      // Label 5531: @405209
      GIM_Reject,
    // Label 5528: @405210
    GIM_Reject,
    // Label 5516: @405211
    GIM_Try, /*On fail goto*//*Label 5532*/ GIMT_Encode4(405490),
      GIM_CheckType, /*MI*/0, /*Op*/1, /*Type*/GILLT_s64,
      GIM_CheckType, /*MI*/0, /*Op*/2, /*Type*/GILLT_s64,
      GIM_CheckRegBankForClass, /*MI*/0, /*Op*/0, /*RC*/GIMT_Encode2(AMDGPU::VReg_64RegClassID),
      GIM_Try, /*On fail goto*//*Label 5533*/ GIMT_Encode4(405294), // Rule ID 839 //
        GIM_CheckFeatures, GIMT_Encode2(GIFBS_isGFX12Plus),
        GIM_CheckComplexPattern, /*MI*/0, /*Op*/1, /*Renderer*/GIMT_Encode2(0), GIMT_Encode2(GICP_gi_vop3mods0),
        GIM_CheckComplexPattern, /*MI*/0, /*Op*/2, /*Renderer*/GIMT_Encode2(1), GIMT_Encode2(GICP_gi_vop3mods),
        // (strict_fadd:{ *:[f64] } (VOP3Mods0:{ *:[f64] } f64:{ *:[f64] }:$src0, i32:{ *:[i32] }:$src0_modifiers, i1:{ *:[i1] }:$clamp, i32:{ *:[i32] }:$omod), (VOP3Mods:{ *:[f64] } f64:{ *:[f64] }:$src1, i32:{ *:[i32] }:$src1_modifiers))  =>  (V_ADD_F64_pseudo_e64:{ *:[f64] } i32:{ *:[i32] }:$src0_modifiers, f64:{ *:[f64] }:$src0, i32:{ *:[i32] }:$src1_modifiers, f64:{ *:[f64] }:$src1, i1:{ *:[i1] }:$clamp, i32:{ *:[i32] }:$omod)
        GIR_BuildMI, /*InsnID*/0, /*Opcode*/GIMT_Encode2(AMDGPU::V_ADD_F64_pseudo_e64),
        GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/0, // DstI[vdst]
        GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/1, // src0_modifiers
        GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/0, // src0
        GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(1), /*SubOperand*/1, // src1_modifiers
        GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(1), /*SubOperand*/0, // src1
        GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/2, // clamp
        GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/3, // omod
        GIR_ConstrainSelectedInstOperands, /*InsnID*/0,
        GIR_EraseFromParent, /*InsnID*/0,
        // GIR_Coverage, 839,
        GIR_Done,
      // Label 5533: @405294
      GIM_Try, /*On fail goto*//*Label 5534*/ GIMT_Encode4(405359), // Rule ID 857 //
        GIM_CheckFeatures, GIMT_Encode2(GIFBS_isNotGFX12Plus),
        GIM_CheckComplexPattern, /*MI*/0, /*Op*/1, /*Renderer*/GIMT_Encode2(0), GIMT_Encode2(GICP_gi_vop3mods0),
        GIM_CheckComplexPattern, /*MI*/0, /*Op*/2, /*Renderer*/GIMT_Encode2(1), GIMT_Encode2(GICP_gi_vop3mods),
        // (strict_fadd:{ *:[f64] } (VOP3Mods0:{ *:[f64] } f64:{ *:[f64] }:$src0, i32:{ *:[i32] }:$src0_modifiers, i1:{ *:[i1] }:$clamp, i32:{ *:[i32] }:$omod), (VOP3Mods:{ *:[f64] } f64:{ *:[f64] }:$src1, i32:{ *:[i32] }:$src1_modifiers))  =>  (V_ADD_F64_e64:{ *:[f64] } i32:{ *:[i32] }:$src0_modifiers, f64:{ *:[f64] }:$src0, i32:{ *:[i32] }:$src1_modifiers, f64:{ *:[f64] }:$src1, i1:{ *:[i1] }:$clamp, i32:{ *:[i32] }:$omod)
        GIR_BuildMI, /*InsnID*/0, /*Opcode*/GIMT_Encode2(AMDGPU::V_ADD_F64_e64),
        GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/0, // DstI[vdst]
        GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/1, // src0_modifiers
        GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/0, // src0
        GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(1), /*SubOperand*/1, // src1_modifiers
        GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(1), /*SubOperand*/0, // src1
        GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/2, // clamp
        GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/3, // omod
        GIR_ConstrainSelectedInstOperands, /*InsnID*/0,
        GIR_EraseFromParent, /*InsnID*/0,
        // GIR_Coverage, 857,
        GIR_Done,
      // Label 5534: @405359
      GIM_Try, /*On fail goto*//*Label 5535*/ GIMT_Encode4(405424), // Rule ID 7162 //
        GIM_CheckFeatures, GIMT_Encode2(GIFBS_isGFX12Plus),
        GIM_CheckComplexPattern, /*MI*/0, /*Op*/1, /*Renderer*/GIMT_Encode2(0), GIMT_Encode2(GICP_gi_vop3mods),
        GIM_CheckComplexPattern, /*MI*/0, /*Op*/2, /*Renderer*/GIMT_Encode2(1), GIMT_Encode2(GICP_gi_vop3mods0),
        // (strict_fadd:{ *:[f64] } (VOP3Mods:{ *:[f64] } f64:{ *:[f64] }:$src1, i32:{ *:[i32] }:$src1_modifiers), (VOP3Mods0:{ *:[f64] } f64:{ *:[f64] }:$src0, i32:{ *:[i32] }:$src0_modifiers, i1:{ *:[i1] }:$clamp, i32:{ *:[i32] }:$omod))  =>  (V_ADD_F64_pseudo_e64:{ *:[f64] } i32:{ *:[i32] }:$src0_modifiers, f64:{ *:[f64] }:$src0, i32:{ *:[i32] }:$src1_modifiers, f64:{ *:[f64] }:$src1, i1:{ *:[i1] }:$clamp, i32:{ *:[i32] }:$omod)
        GIR_BuildMI, /*InsnID*/0, /*Opcode*/GIMT_Encode2(AMDGPU::V_ADD_F64_pseudo_e64),
        GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/0, // DstI[vdst]
        GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(1), /*SubOperand*/1, // src0_modifiers
        GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(1), /*SubOperand*/0, // src0
        GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/1, // src1_modifiers
        GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/0, // src1
        GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(1), /*SubOperand*/2, // clamp
        GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(1), /*SubOperand*/3, // omod
        GIR_ConstrainSelectedInstOperands, /*InsnID*/0,
        GIR_EraseFromParent, /*InsnID*/0,
        // GIR_Coverage, 7162,
        GIR_Done,
      // Label 5535: @405424
      GIM_Try, /*On fail goto*//*Label 5536*/ GIMT_Encode4(405489), // Rule ID 7175 //
        GIM_CheckFeatures, GIMT_Encode2(GIFBS_isNotGFX12Plus),
        GIM_CheckComplexPattern, /*MI*/0, /*Op*/1, /*Renderer*/GIMT_Encode2(0), GIMT_Encode2(GICP_gi_vop3mods),
        GIM_CheckComplexPattern, /*MI*/0, /*Op*/2, /*Renderer*/GIMT_Encode2(1), GIMT_Encode2(GICP_gi_vop3mods0),
        // (strict_fadd:{ *:[f64] } (VOP3Mods:{ *:[f64] } f64:{ *:[f64] }:$src1, i32:{ *:[i32] }:$src1_modifiers), (VOP3Mods0:{ *:[f64] } f64:{ *:[f64] }:$src0, i32:{ *:[i32] }:$src0_modifiers, i1:{ *:[i1] }:$clamp, i32:{ *:[i32] }:$omod))  =>  (V_ADD_F64_e64:{ *:[f64] } i32:{ *:[i32] }:$src0_modifiers, f64:{ *:[f64] }:$src0, i32:{ *:[i32] }:$src1_modifiers, f64:{ *:[f64] }:$src1, i1:{ *:[i1] }:$clamp, i32:{ *:[i32] }:$omod)
        GIR_BuildMI, /*InsnID*/0, /*Opcode*/GIMT_Encode2(AMDGPU::V_ADD_F64_e64),
        GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/0, // DstI[vdst]
        GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(1), /*SubOperand*/1, // src0_modifiers
        GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(1), /*SubOperand*/0, // src0
        GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/1, // src1_modifiers
        GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/0, // src1
        GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(1), /*SubOperand*/2, // clamp
        GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(1), /*SubOperand*/3, // omod
        GIR_ConstrainSelectedInstOperands, /*InsnID*/0,
        GIR_EraseFromParent, /*InsnID*/0,
        // GIR_Coverage, 7175,
        GIR_Done,
      // Label 5536: @405489
      GIM_Reject,
    // Label 5532: @405490
    GIM_Reject,
    // Label 5517: @405491
    GIM_Try, /*On fail goto*//*Label 5537*/ GIMT_Encode4(405571), // Rule ID 960 //
      GIM_CheckType, /*MI*/0, /*Op*/1, /*Type*/GILLT_v2s16,
      GIM_CheckType, /*MI*/0, /*Op*/2, /*Type*/GILLT_v2s16,
      GIM_CheckRegBankForClass, /*MI*/0, /*Op*/0, /*RC*/GIMT_Encode2(AMDGPU::VGPR_32RegClassID),
      GIM_CheckComplexPattern, /*MI*/0, /*Op*/1, /*Renderer*/GIMT_Encode2(0), GIMT_Encode2(GICP_gi_vop3pmods),
      GIM_CheckComplexPattern, /*MI*/0, /*Op*/2, /*Renderer*/GIMT_Encode2(1), GIMT_Encode2(GICP_gi_vop3pmods),
      // (strict_fadd:{ *:[v2f16] } (VOP3PMods:{ *:[v2f16] } v2f16:{ *:[v2f16] }:$src0, i32:{ *:[i32] }:$src0_modifiers), (VOP3PMods:{ *:[v2f16] } v2f16:{ *:[v2f16] }:$src1, i32:{ *:[i32] }:$src1_modifiers))  =>  (V_PK_ADD_F16:{ *:[v2f16] } i32:{ *:[i32] }:$src0_modifiers, v2f16:{ *:[v2f16] }:$src0, i32:{ *:[i32] }:$src1_modifiers, v2f16:{ *:[v2f16] }:$src1)
      GIR_BuildMI, /*InsnID*/0, /*Opcode*/GIMT_Encode2(AMDGPU::V_PK_ADD_F16),
      GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/0, // DstI[vdst]
      GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/1, // src0_modifiers
      GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/0, // src0
      GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(1), /*SubOperand*/1, // src1_modifiers
      GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(1), /*SubOperand*/0, // src1
      GIR_AddImm8, /*InsnID*/0, /*Imm*/0,
      GIR_AddImm8, /*InsnID*/0, /*Imm*/0,
      GIR_AddImm8, /*InsnID*/0, /*Imm*/0,
      GIR_AddImm8, /*InsnID*/0, /*Imm*/0,
      GIR_AddImm8, /*InsnID*/0, /*Imm*/0,
      GIR_ConstrainSelectedInstOperands, /*InsnID*/0,
      GIR_EraseFromParent, /*InsnID*/0,
      // GIR_Coverage, 960,
      GIR_Done,
    // Label 5537: @405571
    GIM_Reject,
    // Label 5518: @405572
    GIM_Try, /*On fail goto*//*Label 5538*/ GIMT_Encode4(405655), // Rule ID 1088 //
      GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasPackedFP32Ops),
      GIM_CheckType, /*MI*/0, /*Op*/1, /*Type*/GILLT_v2s32,
      GIM_CheckType, /*MI*/0, /*Op*/2, /*Type*/GILLT_v2s32,
      GIM_CheckRegBankForClass, /*MI*/0, /*Op*/0, /*RC*/GIMT_Encode2(AMDGPU::VReg_64RegClassID),
      GIM_CheckComplexPattern, /*MI*/0, /*Op*/1, /*Renderer*/GIMT_Encode2(0), GIMT_Encode2(GICP_gi_vop3pmods),
      GIM_CheckComplexPattern, /*MI*/0, /*Op*/2, /*Renderer*/GIMT_Encode2(1), GIMT_Encode2(GICP_gi_vop3pmods),
      // (strict_fadd:{ *:[v2f32] } (VOP3PMods:{ *:[v2f32] } v2f32:{ *:[v2f32] }:$src0, i32:{ *:[i32] }:$src0_modifiers), (VOP3PMods:{ *:[v2f32] } v2f32:{ *:[v2f32] }:$src1, i32:{ *:[i32] }:$src1_modifiers))  =>  (V_PK_ADD_F32:{ *:[v2f32] } i32:{ *:[i32] }:$src0_modifiers, v2f32:{ *:[v2f32] }:$src0, i32:{ *:[i32] }:$src1_modifiers, v2f32:{ *:[v2f32] }:$src1)
      GIR_BuildMI, /*InsnID*/0, /*Opcode*/GIMT_Encode2(AMDGPU::V_PK_ADD_F32),
      GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/0, // DstI[vdst]
      GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/1, // src0_modifiers
      GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/0, // src0
      GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(1), /*SubOperand*/1, // src1_modifiers
      GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(1), /*SubOperand*/0, // src1
      GIR_AddImm8, /*InsnID*/0, /*Imm*/0,
      GIR_AddImm8, /*InsnID*/0, /*Imm*/0,
      GIR_AddImm8, /*InsnID*/0, /*Imm*/0,
      GIR_AddImm8, /*InsnID*/0, /*Imm*/0,
      GIR_AddImm8, /*InsnID*/0, /*Imm*/0,
      GIR_ConstrainSelectedInstOperands, /*InsnID*/0,
      GIR_EraseFromParent, /*InsnID*/0,
      // GIR_Coverage, 1088,
      GIR_Done,
    // Label 5538: @405655
    GIM_Reject,
    // Label 5519: @405656
    GIM_Reject,
    // Label 99: @405657
    GIM_SwitchType, /*MI*/0, /*Op*/0, /*[*/GIMT_Encode2(8), GIMT_Encode2(10), /*)*//*default:*//*Label 5541*/ GIMT_Encode4(406061),
    /*GILLT_s16*//*Label 5539*/ GIMT_Encode4(405676),
    /*GILLT_s32*//*Label 5540*/ GIMT_Encode4(405940),
    // Label 5539: @405676
    GIM_Try, /*On fail goto*//*Label 5542*/ GIMT_Encode4(405939),
      GIM_CheckType, /*MI*/0, /*Op*/1, /*Type*/GILLT_s16,
      GIM_CheckType, /*MI*/0, /*Op*/2, /*Type*/GILLT_s16,
      GIM_Try, /*On fail goto*//*Label 5543*/ GIMT_Encode4(405728), // Rule ID 106 //
        GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasSALUFloatInsts),
        GIM_CheckRegBankForClass, /*MI*/0, /*Op*/0, /*RC*/GIMT_Encode2(AMDGPU::SReg_32RegClassID),
        GIM_CheckRegBankForClass, /*MI*/0, /*Op*/1, /*RC*/GIMT_Encode2(AMDGPU::SReg_32RegClassID),
        GIM_CheckRegBankForClass, /*MI*/0, /*Op*/2, /*RC*/GIMT_Encode2(AMDGPU::SReg_32RegClassID),
        GIM_CheckCxxInsnPredicate, /*MI*/0, /*FnId*/GIMT_Encode2(GICXXPred_MI_Predicate_anonymous_17634),
        // (strict_fsub:{ *:[f16] } SSrc_f16:{ *:[f16] }:$src0, SSrc_f16:{ *:[f16] }:$src1)<<P:Predicate_anonymous_17634>>  =>  (S_SUB_F16:{ *:[f16] } SSrc_f16:{ *:[f16] }:$src0, SSrc_f16:{ *:[f16] }:$src1)
        GIR_MutateOpcode, /*InsnID*/0, /*RecycleInsnID*/0, /*Opcode*/GIMT_Encode2(AMDGPU::S_SUB_F16),
        GIR_AddImplicitUse, /*InsnID*/0, GIMT_Encode2(AMDGPU::MODE),
        GIR_ConstrainSelectedInstOperands, /*InsnID*/0,
        // GIR_Coverage, 106,
        GIR_Done,
      // Label 5543: @405728
      GIM_Try, /*On fail goto*//*Label 5544*/ GIMT_Encode4(405798), // Rule ID 799 //
        GIM_CheckFeatures, GIMT_Encode2(GIFBS_Has16BitInsts_NotHasTrue16BitInsts),
        GIM_CheckRegBankForClass, /*MI*/0, /*Op*/0, /*RC*/GIMT_Encode2(AMDGPU::VGPR_32RegClassID),
        GIM_CheckComplexPattern, /*MI*/0, /*Op*/1, /*Renderer*/GIMT_Encode2(0), GIMT_Encode2(GICP_gi_vop3mods0),
        GIM_CheckComplexPattern, /*MI*/0, /*Op*/2, /*Renderer*/GIMT_Encode2(1), GIMT_Encode2(GICP_gi_vop3mods),
        // (strict_fsub:{ *:[f16] } (VOP3Mods0:{ *:[f16] } f16:{ *:[f16] }:$src0, i32:{ *:[i32] }:$src0_modifiers, i1:{ *:[i1] }:$clamp, i32:{ *:[i32] }:$omod), (VOP3Mods:{ *:[f16] } f16:{ *:[f16] }:$src1, i32:{ *:[i32] }:$src1_modifiers))  =>  (V_SUB_F16_e64:{ *:[f16] } i32:{ *:[i32] }:$src0_modifiers, f16:{ *:[f16] }:$src0, i32:{ *:[i32] }:$src1_modifiers, f16:{ *:[f16] }:$src1, i1:{ *:[i1] }:$clamp, i32:{ *:[i32] }:$omod)
        GIR_BuildMI, /*InsnID*/0, /*Opcode*/GIMT_Encode2(AMDGPU::V_SUB_F16_e64),
        GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/0, // DstI[vdst]
        GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/1, // src0_modifiers
        GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/0, // src0
        GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(1), /*SubOperand*/1, // src1_modifiers
        GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(1), /*SubOperand*/0, // src1
        GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/2, // clamp
        GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/3, // omod
        GIR_ConstrainSelectedInstOperands, /*InsnID*/0,
        GIR_EraseFromParent, /*InsnID*/0,
        // GIR_Coverage, 799,
        GIR_Done,
      // Label 5544: @405798
      GIM_Try, /*On fail goto*//*Label 5545*/ GIMT_Encode4(405868), // Rule ID 801 //
        GIM_CheckFeatures, GIMT_Encode2(GIFBS_UseRealTrue16Insts),
        GIM_CheckRegBankForClass, /*MI*/0, /*Op*/0, /*RC*/GIMT_Encode2(AMDGPU::VGPR_16RegClassID),
        GIM_CheckComplexPattern, /*MI*/0, /*Op*/1, /*Renderer*/GIMT_Encode2(0), GIMT_Encode2(GICP_gi_vop3mods0),
        GIM_CheckComplexPattern, /*MI*/0, /*Op*/2, /*Renderer*/GIMT_Encode2(1), GIMT_Encode2(GICP_gi_vop3mods),
        // (strict_fsub:{ *:[f16] } (VOP3Mods0:{ *:[f16] } f16:{ *:[f16] }:$src0, i32:{ *:[i32] }:$src0_modifiers, i1:{ *:[i1] }:$clamp, i32:{ *:[i32] }:$omod), (VOP3Mods:{ *:[f16] } f16:{ *:[f16] }:$src1, i32:{ *:[i32] }:$src1_modifiers))  =>  (V_SUB_F16_t16_e64:{ *:[f16] } i32:{ *:[i32] }:$src0_modifiers, f16:{ *:[f16] }:$src0, i32:{ *:[i32] }:$src1_modifiers, f16:{ *:[f16] }:$src1, i1:{ *:[i1] }:$clamp, i32:{ *:[i32] }:$omod)
        GIR_BuildMI, /*InsnID*/0, /*Opcode*/GIMT_Encode2(AMDGPU::V_SUB_F16_t16_e64),
        GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/0, // DstI[vdst]
        GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/1, // src0_modifiers
        GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/0, // src0
        GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(1), /*SubOperand*/1, // src1_modifiers
        GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(1), /*SubOperand*/0, // src1
        GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/2, // clamp
        GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/3, // omod
        GIR_ConstrainSelectedInstOperands, /*InsnID*/0,
        GIR_EraseFromParent, /*InsnID*/0,
        // GIR_Coverage, 801,
        GIR_Done,
      // Label 5545: @405868
      GIM_Try, /*On fail goto*//*Label 5546*/ GIMT_Encode4(405938), // Rule ID 803 //
        GIM_CheckFeatures, GIMT_Encode2(GIFBS_UseFakeTrue16Insts),
        GIM_CheckRegBankForClass, /*MI*/0, /*Op*/0, /*RC*/GIMT_Encode2(AMDGPU::VGPR_32RegClassID),
        GIM_CheckComplexPattern, /*MI*/0, /*Op*/1, /*Renderer*/GIMT_Encode2(0), GIMT_Encode2(GICP_gi_vop3mods0),
        GIM_CheckComplexPattern, /*MI*/0, /*Op*/2, /*Renderer*/GIMT_Encode2(1), GIMT_Encode2(GICP_gi_vop3mods),
        // (strict_fsub:{ *:[f16] } (VOP3Mods0:{ *:[f16] } f16:{ *:[f16] }:$src0, i32:{ *:[i32] }:$src0_modifiers, i1:{ *:[i1] }:$clamp, i32:{ *:[i32] }:$omod), (VOP3Mods:{ *:[f16] } f16:{ *:[f16] }:$src1, i32:{ *:[i32] }:$src1_modifiers))  =>  (V_SUB_F16_fake16_e64:{ *:[f16] } i32:{ *:[i32] }:$src0_modifiers, f16:{ *:[f16] }:$src0, i32:{ *:[i32] }:$src1_modifiers, f16:{ *:[f16] }:$src1, i1:{ *:[i1] }:$clamp, i32:{ *:[i32] }:$omod)
        GIR_BuildMI, /*InsnID*/0, /*Opcode*/GIMT_Encode2(AMDGPU::V_SUB_F16_fake16_e64),
        GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/0, // DstI[vdst]
        GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/1, // src0_modifiers
        GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/0, // src0
        GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(1), /*SubOperand*/1, // src1_modifiers
        GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(1), /*SubOperand*/0, // src1
        GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/2, // clamp
        GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/3, // omod
        GIR_ConstrainSelectedInstOperands, /*InsnID*/0,
        GIR_EraseFromParent, /*InsnID*/0,
        // GIR_Coverage, 803,
        GIR_Done,
      // Label 5546: @405938
      GIM_Reject,
    // Label 5542: @405939
    GIM_Reject,
    // Label 5540: @405940
    GIM_Try, /*On fail goto*//*Label 5547*/ GIMT_Encode4(406060),
      GIM_CheckType, /*MI*/0, /*Op*/1, /*Type*/GILLT_s32,
      GIM_CheckType, /*MI*/0, /*Op*/2, /*Type*/GILLT_s32,
      GIM_Try, /*On fail goto*//*Label 5548*/ GIMT_Encode4(405992), // Rule ID 108 //
        GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasSALUFloatInsts),
        GIM_CheckRegBankForClass, /*MI*/0, /*Op*/0, /*RC*/GIMT_Encode2(AMDGPU::SReg_32RegClassID),
        GIM_CheckRegBankForClass, /*MI*/0, /*Op*/1, /*RC*/GIMT_Encode2(AMDGPU::SReg_32RegClassID),
        GIM_CheckRegBankForClass, /*MI*/0, /*Op*/2, /*RC*/GIMT_Encode2(AMDGPU::SReg_32RegClassID),
        GIM_CheckCxxInsnPredicate, /*MI*/0, /*FnId*/GIMT_Encode2(GICXXPred_MI_Predicate_anonymous_17634),
        // (strict_fsub:{ *:[f32] } SSrc_f32:{ *:[f32] }:$src0, SSrc_f32:{ *:[f32] }:$src1)<<P:Predicate_anonymous_17634>>  =>  (S_SUB_F32:{ *:[f32] } SSrc_f32:{ *:[f32] }:$src0, SSrc_f32:{ *:[f32] }:$src1)
        GIR_MutateOpcode, /*InsnID*/0, /*RecycleInsnID*/0, /*Opcode*/GIMT_Encode2(AMDGPU::S_SUB_F32),
        GIR_AddImplicitUse, /*InsnID*/0, GIMT_Encode2(AMDGPU::MODE),
        GIR_ConstrainSelectedInstOperands, /*InsnID*/0,
        // GIR_Coverage, 108,
        GIR_Done,
      // Label 5548: @405992
      GIM_Try, /*On fail goto*//*Label 5549*/ GIMT_Encode4(406059), // Rule ID 725 //
        GIM_CheckRegBankForClass, /*MI*/0, /*Op*/0, /*RC*/GIMT_Encode2(AMDGPU::VGPR_32RegClassID),
        GIM_CheckComplexPattern, /*MI*/0, /*Op*/1, /*Renderer*/GIMT_Encode2(0), GIMT_Encode2(GICP_gi_vop3mods0),
        GIM_CheckComplexPattern, /*MI*/0, /*Op*/2, /*Renderer*/GIMT_Encode2(1), GIMT_Encode2(GICP_gi_vop3mods),
        // (strict_fsub:{ *:[f32] } (VOP3Mods0:{ *:[f32] } f32:{ *:[f32] }:$src0, i32:{ *:[i32] }:$src0_modifiers, i1:{ *:[i1] }:$clamp, i32:{ *:[i32] }:$omod), (VOP3Mods:{ *:[f32] } f32:{ *:[f32] }:$src1, i32:{ *:[i32] }:$src1_modifiers))  =>  (V_SUB_F32_e64:{ *:[f32] } i32:{ *:[i32] }:$src0_modifiers, f32:{ *:[f32] }:$src0, i32:{ *:[i32] }:$src1_modifiers, f32:{ *:[f32] }:$src1, i1:{ *:[i1] }:$clamp, i32:{ *:[i32] }:$omod)
        GIR_BuildMI, /*InsnID*/0, /*Opcode*/GIMT_Encode2(AMDGPU::V_SUB_F32_e64),
        GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/0, // DstI[vdst]
        GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/1, // src0_modifiers
        GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/0, // src0
        GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(1), /*SubOperand*/1, // src1_modifiers
        GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(1), /*SubOperand*/0, // src1
        GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/2, // clamp
        GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/3, // omod
        GIR_ConstrainSelectedInstOperands, /*InsnID*/0,
        GIR_EraseFromParent, /*InsnID*/0,
        // GIR_Coverage, 725,
        GIR_Done,
      // Label 5549: @406059
      GIM_Reject,
    // Label 5547: @406060
    GIM_Reject,
    // Label 5541: @406061
    GIM_Reject,
    // Label 100: @406062
    GIM_SwitchType, /*MI*/0, /*Op*/0, /*[*/GIMT_Encode2(8), GIMT_Encode2(13), /*)*//*default:*//*Label 5555*/ GIMT_Encode4(407538),
    /*GILLT_s16*//*Label 5550*/ GIMT_Encode4(406093),
    /*GILLT_s32*//*Label 5551*/ GIMT_Encode4(406567),
    /*GILLT_s64*//*Label 5552*/ GIMT_Encode4(406755),
    /*GILLT_v2s16*//*Label 5553*/ GIMT_Encode4(407373),
    /*GILLT_v2s32*//*Label 5554*/ GIMT_Encode4(407454),
    // Label 5550: @406093
    GIM_Try, /*On fail goto*//*Label 5556*/ GIMT_Encode4(406566),
      GIM_CheckType, /*MI*/0, /*Op*/1, /*Type*/GILLT_s16,
      GIM_CheckType, /*MI*/0, /*Op*/2, /*Type*/GILLT_s16,
      GIM_Try, /*On fail goto*//*Label 5557*/ GIMT_Encode4(406145), // Rule ID 100 //
        GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasSALUFloatInsts),
        GIM_CheckRegBankForClass, /*MI*/0, /*Op*/0, /*RC*/GIMT_Encode2(AMDGPU::SReg_32RegClassID),
        GIM_CheckRegBankForClass, /*MI*/0, /*Op*/1, /*RC*/GIMT_Encode2(AMDGPU::SReg_32RegClassID),
        GIM_CheckRegBankForClass, /*MI*/0, /*Op*/2, /*RC*/GIMT_Encode2(AMDGPU::SReg_32RegClassID),
        GIM_CheckCxxInsnPredicate, /*MI*/0, /*FnId*/GIMT_Encode2(GICXXPred_MI_Predicate_anonymous_17633),
        // (strict_fmul:{ *:[f16] } SSrc_f16:{ *:[f16] }:$src0, SSrc_f16:{ *:[f16] }:$src1)<<P:Predicate_anonymous_17633>>  =>  (S_MUL_F16:{ *:[f16] } SSrc_f16:{ *:[f16] }:$src0, SSrc_f16:{ *:[f16] }:$src1)
        GIR_MutateOpcode, /*InsnID*/0, /*RecycleInsnID*/0, /*Opcode*/GIMT_Encode2(AMDGPU::S_MUL_F16),
        GIR_AddImplicitUse, /*InsnID*/0, GIMT_Encode2(AMDGPU::MODE),
        GIR_ConstrainSelectedInstOperands, /*InsnID*/0,
        // GIR_Coverage, 100,
        GIR_Done,
      // Label 5557: @406145
      GIM_Try, /*On fail goto*//*Label 5558*/ GIMT_Encode4(406215), // Rule ID 805 //
        GIM_CheckFeatures, GIMT_Encode2(GIFBS_Has16BitInsts_NotHasTrue16BitInsts),
        GIM_CheckRegBankForClass, /*MI*/0, /*Op*/0, /*RC*/GIMT_Encode2(AMDGPU::VGPR_32RegClassID),
        GIM_CheckComplexPattern, /*MI*/0, /*Op*/1, /*Renderer*/GIMT_Encode2(0), GIMT_Encode2(GICP_gi_vop3mods0),
        GIM_CheckComplexPattern, /*MI*/0, /*Op*/2, /*Renderer*/GIMT_Encode2(1), GIMT_Encode2(GICP_gi_vop3mods),
        // (strict_fmul:{ *:[f16] } (VOP3Mods0:{ *:[f16] } f16:{ *:[f16] }:$src0, i32:{ *:[i32] }:$src0_modifiers, i1:{ *:[i1] }:$clamp, i32:{ *:[i32] }:$omod), (VOP3Mods:{ *:[f16] } f16:{ *:[f16] }:$src1, i32:{ *:[i32] }:$src1_modifiers))  =>  (V_MUL_F16_e64:{ *:[f16] } i32:{ *:[i32] }:$src0_modifiers, f16:{ *:[f16] }:$src0, i32:{ *:[i32] }:$src1_modifiers, f16:{ *:[f16] }:$src1, i1:{ *:[i1] }:$clamp, i32:{ *:[i32] }:$omod)
        GIR_BuildMI, /*InsnID*/0, /*Opcode*/GIMT_Encode2(AMDGPU::V_MUL_F16_e64),
        GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/0, // DstI[vdst]
        GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/1, // src0_modifiers
        GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/0, // src0
        GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(1), /*SubOperand*/1, // src1_modifiers
        GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(1), /*SubOperand*/0, // src1
        GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/2, // clamp
        GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/3, // omod
        GIR_ConstrainSelectedInstOperands, /*InsnID*/0,
        GIR_EraseFromParent, /*InsnID*/0,
        // GIR_Coverage, 805,
        GIR_Done,
      // Label 5558: @406215
      GIM_Try, /*On fail goto*//*Label 5559*/ GIMT_Encode4(406285), // Rule ID 807 //
        GIM_CheckFeatures, GIMT_Encode2(GIFBS_UseRealTrue16Insts),
        GIM_CheckRegBankForClass, /*MI*/0, /*Op*/0, /*RC*/GIMT_Encode2(AMDGPU::VGPR_16RegClassID),
        GIM_CheckComplexPattern, /*MI*/0, /*Op*/1, /*Renderer*/GIMT_Encode2(0), GIMT_Encode2(GICP_gi_vop3mods0),
        GIM_CheckComplexPattern, /*MI*/0, /*Op*/2, /*Renderer*/GIMT_Encode2(1), GIMT_Encode2(GICP_gi_vop3mods),
        // (strict_fmul:{ *:[f16] } (VOP3Mods0:{ *:[f16] } f16:{ *:[f16] }:$src0, i32:{ *:[i32] }:$src0_modifiers, i1:{ *:[i1] }:$clamp, i32:{ *:[i32] }:$omod), (VOP3Mods:{ *:[f16] } f16:{ *:[f16] }:$src1, i32:{ *:[i32] }:$src1_modifiers))  =>  (V_MUL_F16_t16_e64:{ *:[f16] } i32:{ *:[i32] }:$src0_modifiers, f16:{ *:[f16] }:$src0, i32:{ *:[i32] }:$src1_modifiers, f16:{ *:[f16] }:$src1, i1:{ *:[i1] }:$clamp, i32:{ *:[i32] }:$omod)
        GIR_BuildMI, /*InsnID*/0, /*Opcode*/GIMT_Encode2(AMDGPU::V_MUL_F16_t16_e64),
        GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/0, // DstI[vdst]
        GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/1, // src0_modifiers
        GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/0, // src0
        GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(1), /*SubOperand*/1, // src1_modifiers
        GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(1), /*SubOperand*/0, // src1
        GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/2, // clamp
        GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/3, // omod
        GIR_ConstrainSelectedInstOperands, /*InsnID*/0,
        GIR_EraseFromParent, /*InsnID*/0,
        // GIR_Coverage, 807,
        GIR_Done,
      // Label 5559: @406285
      GIM_Try, /*On fail goto*//*Label 5560*/ GIMT_Encode4(406355), // Rule ID 809 //
        GIM_CheckFeatures, GIMT_Encode2(GIFBS_UseFakeTrue16Insts),
        GIM_CheckRegBankForClass, /*MI*/0, /*Op*/0, /*RC*/GIMT_Encode2(AMDGPU::VGPR_32RegClassID),
        GIM_CheckComplexPattern, /*MI*/0, /*Op*/1, /*Renderer*/GIMT_Encode2(0), GIMT_Encode2(GICP_gi_vop3mods0),
        GIM_CheckComplexPattern, /*MI*/0, /*Op*/2, /*Renderer*/GIMT_Encode2(1), GIMT_Encode2(GICP_gi_vop3mods),
        // (strict_fmul:{ *:[f16] } (VOP3Mods0:{ *:[f16] } f16:{ *:[f16] }:$src0, i32:{ *:[i32] }:$src0_modifiers, i1:{ *:[i1] }:$clamp, i32:{ *:[i32] }:$omod), (VOP3Mods:{ *:[f16] } f16:{ *:[f16] }:$src1, i32:{ *:[i32] }:$src1_modifiers))  =>  (V_MUL_F16_fake16_e64:{ *:[f16] } i32:{ *:[i32] }:$src0_modifiers, f16:{ *:[f16] }:$src0, i32:{ *:[i32] }:$src1_modifiers, f16:{ *:[f16] }:$src1, i1:{ *:[i1] }:$clamp, i32:{ *:[i32] }:$omod)
        GIR_BuildMI, /*InsnID*/0, /*Opcode*/GIMT_Encode2(AMDGPU::V_MUL_F16_fake16_e64),
        GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/0, // DstI[vdst]
        GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/1, // src0_modifiers
        GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/0, // src0
        GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(1), /*SubOperand*/1, // src1_modifiers
        GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(1), /*SubOperand*/0, // src1
        GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/2, // clamp
        GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/3, // omod
        GIR_ConstrainSelectedInstOperands, /*InsnID*/0,
        GIR_EraseFromParent, /*InsnID*/0,
        // GIR_Coverage, 809,
        GIR_Done,
      // Label 5560: @406355
      GIM_Try, /*On fail goto*//*Label 5561*/ GIMT_Encode4(406425), // Rule ID 7142 //
        GIM_CheckFeatures, GIMT_Encode2(GIFBS_Has16BitInsts_NotHasTrue16BitInsts),
        GIM_CheckRegBankForClass, /*MI*/0, /*Op*/0, /*RC*/GIMT_Encode2(AMDGPU::VGPR_32RegClassID),
        GIM_CheckComplexPattern, /*MI*/0, /*Op*/1, /*Renderer*/GIMT_Encode2(0), GIMT_Encode2(GICP_gi_vop3mods),
        GIM_CheckComplexPattern, /*MI*/0, /*Op*/2, /*Renderer*/GIMT_Encode2(1), GIMT_Encode2(GICP_gi_vop3mods0),
        // (strict_fmul:{ *:[f16] } (VOP3Mods:{ *:[f16] } f16:{ *:[f16] }:$src1, i32:{ *:[i32] }:$src1_modifiers), (VOP3Mods0:{ *:[f16] } f16:{ *:[f16] }:$src0, i32:{ *:[i32] }:$src0_modifiers, i1:{ *:[i1] }:$clamp, i32:{ *:[i32] }:$omod))  =>  (V_MUL_F16_e64:{ *:[f16] } i32:{ *:[i32] }:$src0_modifiers, f16:{ *:[f16] }:$src0, i32:{ *:[i32] }:$src1_modifiers, f16:{ *:[f16] }:$src1, i1:{ *:[i1] }:$clamp, i32:{ *:[i32] }:$omod)
        GIR_BuildMI, /*InsnID*/0, /*Opcode*/GIMT_Encode2(AMDGPU::V_MUL_F16_e64),
        GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/0, // DstI[vdst]
        GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(1), /*SubOperand*/1, // src0_modifiers
        GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(1), /*SubOperand*/0, // src0
        GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/1, // src1_modifiers
        GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/0, // src1
        GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(1), /*SubOperand*/2, // clamp
        GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(1), /*SubOperand*/3, // omod
        GIR_ConstrainSelectedInstOperands, /*InsnID*/0,
        GIR_EraseFromParent, /*InsnID*/0,
        // GIR_Coverage, 7142,
        GIR_Done,
      // Label 5561: @406425
      GIM_Try, /*On fail goto*//*Label 5562*/ GIMT_Encode4(406495), // Rule ID 7144 //
        GIM_CheckFeatures, GIMT_Encode2(GIFBS_UseRealTrue16Insts),
        GIM_CheckRegBankForClass, /*MI*/0, /*Op*/0, /*RC*/GIMT_Encode2(AMDGPU::VGPR_16RegClassID),
        GIM_CheckComplexPattern, /*MI*/0, /*Op*/1, /*Renderer*/GIMT_Encode2(0), GIMT_Encode2(GICP_gi_vop3mods),
        GIM_CheckComplexPattern, /*MI*/0, /*Op*/2, /*Renderer*/GIMT_Encode2(1), GIMT_Encode2(GICP_gi_vop3mods0),
        // (strict_fmul:{ *:[f16] } (VOP3Mods:{ *:[f16] } f16:{ *:[f16] }:$src1, i32:{ *:[i32] }:$src1_modifiers), (VOP3Mods0:{ *:[f16] } f16:{ *:[f16] }:$src0, i32:{ *:[i32] }:$src0_modifiers, i1:{ *:[i1] }:$clamp, i32:{ *:[i32] }:$omod))  =>  (V_MUL_F16_t16_e64:{ *:[f16] } i32:{ *:[i32] }:$src0_modifiers, f16:{ *:[f16] }:$src0, i32:{ *:[i32] }:$src1_modifiers, f16:{ *:[f16] }:$src1, i1:{ *:[i1] }:$clamp, i32:{ *:[i32] }:$omod)
        GIR_BuildMI, /*InsnID*/0, /*Opcode*/GIMT_Encode2(AMDGPU::V_MUL_F16_t16_e64),
        GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/0, // DstI[vdst]
        GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(1), /*SubOperand*/1, // src0_modifiers
        GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(1), /*SubOperand*/0, // src0
        GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/1, // src1_modifiers
        GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/0, // src1
        GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(1), /*SubOperand*/2, // clamp
        GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(1), /*SubOperand*/3, // omod
        GIR_ConstrainSelectedInstOperands, /*InsnID*/0,
        GIR_EraseFromParent, /*InsnID*/0,
        // GIR_Coverage, 7144,
        GIR_Done,
      // Label 5562: @406495
      GIM_Try, /*On fail goto*//*Label 5563*/ GIMT_Encode4(406565), // Rule ID 7146 //
        GIM_CheckFeatures, GIMT_Encode2(GIFBS_UseFakeTrue16Insts),
        GIM_CheckRegBankForClass, /*MI*/0, /*Op*/0, /*RC*/GIMT_Encode2(AMDGPU::VGPR_32RegClassID),
        GIM_CheckComplexPattern, /*MI*/0, /*Op*/1, /*Renderer*/GIMT_Encode2(0), GIMT_Encode2(GICP_gi_vop3mods),
        GIM_CheckComplexPattern, /*MI*/0, /*Op*/2, /*Renderer*/GIMT_Encode2(1), GIMT_Encode2(GICP_gi_vop3mods0),
        // (strict_fmul:{ *:[f16] } (VOP3Mods:{ *:[f16] } f16:{ *:[f16] }:$src1, i32:{ *:[i32] }:$src1_modifiers), (VOP3Mods0:{ *:[f16] } f16:{ *:[f16] }:$src0, i32:{ *:[i32] }:$src0_modifiers, i1:{ *:[i1] }:$clamp, i32:{ *:[i32] }:$omod))  =>  (V_MUL_F16_fake16_e64:{ *:[f16] } i32:{ *:[i32] }:$src0_modifiers, f16:{ *:[f16] }:$src0, i32:{ *:[i32] }:$src1_modifiers, f16:{ *:[f16] }:$src1, i1:{ *:[i1] }:$clamp, i32:{ *:[i32] }:$omod)
        GIR_BuildMI, /*InsnID*/0, /*Opcode*/GIMT_Encode2(AMDGPU::V_MUL_F16_fake16_e64),
        GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/0, // DstI[vdst]
        GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(1), /*SubOperand*/1, // src0_modifiers
        GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(1), /*SubOperand*/0, // src0
        GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/1, // src1_modifiers
        GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/0, // src1
        GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(1), /*SubOperand*/2, // clamp
        GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(1), /*SubOperand*/3, // omod
        GIR_ConstrainSelectedInstOperands, /*InsnID*/0,
        GIR_EraseFromParent, /*InsnID*/0,
        // GIR_Coverage, 7146,
        GIR_Done,
      // Label 5563: @406565
      GIM_Reject,
    // Label 5556: @406566
    GIM_Reject,
    // Label 5551: @406567
    GIM_Try, /*On fail goto*//*Label 5564*/ GIMT_Encode4(406754),
      GIM_CheckType, /*MI*/0, /*Op*/1, /*Type*/GILLT_s32,
      GIM_CheckType, /*MI*/0, /*Op*/2, /*Type*/GILLT_s32,
      GIM_Try, /*On fail goto*//*Label 5565*/ GIMT_Encode4(406619), // Rule ID 96 //
        GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasSALUFloatInsts),
        GIM_CheckRegBankForClass, /*MI*/0, /*Op*/0, /*RC*/GIMT_Encode2(AMDGPU::SReg_32RegClassID),
        GIM_CheckRegBankForClass, /*MI*/0, /*Op*/1, /*RC*/GIMT_Encode2(AMDGPU::SReg_32RegClassID),
        GIM_CheckRegBankForClass, /*MI*/0, /*Op*/2, /*RC*/GIMT_Encode2(AMDGPU::SReg_32RegClassID),
        GIM_CheckCxxInsnPredicate, /*MI*/0, /*FnId*/GIMT_Encode2(GICXXPred_MI_Predicate_anonymous_17633),
        // (strict_fmul:{ *:[f32] } SSrc_f32:{ *:[f32] }:$src0, SSrc_f32:{ *:[f32] }:$src1)<<P:Predicate_anonymous_17633>>  =>  (S_MUL_F32:{ *:[f32] } SSrc_f32:{ *:[f32] }:$src0, SSrc_f32:{ *:[f32] }:$src1)
        GIR_MutateOpcode, /*InsnID*/0, /*RecycleInsnID*/0, /*Opcode*/GIMT_Encode2(AMDGPU::S_MUL_F32),
        GIR_AddImplicitUse, /*InsnID*/0, GIMT_Encode2(AMDGPU::MODE),
        GIR_ConstrainSelectedInstOperands, /*InsnID*/0,
        // GIR_Coverage, 96,
        GIR_Done,
      // Label 5565: @406619
      GIM_Try, /*On fail goto*//*Label 5566*/ GIMT_Encode4(406686), // Rule ID 729 //
        GIM_CheckRegBankForClass, /*MI*/0, /*Op*/0, /*RC*/GIMT_Encode2(AMDGPU::VGPR_32RegClassID),
        GIM_CheckComplexPattern, /*MI*/0, /*Op*/1, /*Renderer*/GIMT_Encode2(0), GIMT_Encode2(GICP_gi_vop3mods0),
        GIM_CheckComplexPattern, /*MI*/0, /*Op*/2, /*Renderer*/GIMT_Encode2(1), GIMT_Encode2(GICP_gi_vop3mods),
        // (strict_fmul:{ *:[f32] } (VOP3Mods0:{ *:[f32] } f32:{ *:[f32] }:$src0, i32:{ *:[i32] }:$src0_modifiers, i1:{ *:[i1] }:$clamp, i32:{ *:[i32] }:$omod), (VOP3Mods:{ *:[f32] } f32:{ *:[f32] }:$src1, i32:{ *:[i32] }:$src1_modifiers))  =>  (V_MUL_F32_e64:{ *:[f32] } i32:{ *:[i32] }:$src0_modifiers, f32:{ *:[f32] }:$src0, i32:{ *:[i32] }:$src1_modifiers, f32:{ *:[f32] }:$src1, i1:{ *:[i1] }:$clamp, i32:{ *:[i32] }:$omod)
        GIR_BuildMI, /*InsnID*/0, /*Opcode*/GIMT_Encode2(AMDGPU::V_MUL_F32_e64),
        GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/0, // DstI[vdst]
        GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/1, // src0_modifiers
        GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/0, // src0
        GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(1), /*SubOperand*/1, // src1_modifiers
        GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(1), /*SubOperand*/0, // src1
        GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/2, // clamp
        GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/3, // omod
        GIR_ConstrainSelectedInstOperands, /*InsnID*/0,
        GIR_EraseFromParent, /*InsnID*/0,
        // GIR_Coverage, 729,
        GIR_Done,
      // Label 5566: @406686
      GIM_Try, /*On fail goto*//*Label 5567*/ GIMT_Encode4(406753), // Rule ID 7129 //
        GIM_CheckRegBankForClass, /*MI*/0, /*Op*/0, /*RC*/GIMT_Encode2(AMDGPU::VGPR_32RegClassID),
        GIM_CheckComplexPattern, /*MI*/0, /*Op*/1, /*Renderer*/GIMT_Encode2(0), GIMT_Encode2(GICP_gi_vop3mods),
        GIM_CheckComplexPattern, /*MI*/0, /*Op*/2, /*Renderer*/GIMT_Encode2(1), GIMT_Encode2(GICP_gi_vop3mods0),
        // (strict_fmul:{ *:[f32] } (VOP3Mods:{ *:[f32] } f32:{ *:[f32] }:$src1, i32:{ *:[i32] }:$src1_modifiers), (VOP3Mods0:{ *:[f32] } f32:{ *:[f32] }:$src0, i32:{ *:[i32] }:$src0_modifiers, i1:{ *:[i1] }:$clamp, i32:{ *:[i32] }:$omod))  =>  (V_MUL_F32_e64:{ *:[f32] } i32:{ *:[i32] }:$src0_modifiers, f32:{ *:[f32] }:$src0, i32:{ *:[i32] }:$src1_modifiers, f32:{ *:[f32] }:$src1, i1:{ *:[i1] }:$clamp, i32:{ *:[i32] }:$omod)
        GIR_BuildMI, /*InsnID*/0, /*Opcode*/GIMT_Encode2(AMDGPU::V_MUL_F32_e64),
        GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/0, // DstI[vdst]
        GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(1), /*SubOperand*/1, // src0_modifiers
        GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(1), /*SubOperand*/0, // src0
        GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/1, // src1_modifiers
        GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/0, // src1
        GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(1), /*SubOperand*/2, // clamp
        GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(1), /*SubOperand*/3, // omod
        GIR_ConstrainSelectedInstOperands, /*InsnID*/0,
        GIR_EraseFromParent, /*InsnID*/0,
        // GIR_Coverage, 7129,
        GIR_Done,
      // Label 5567: @406753
      GIM_Reject,
    // Label 5564: @406754
    GIM_Reject,
    // Label 5552: @406755
    GIM_Try, /*On fail goto*//*Label 5568*/ GIMT_Encode4(407372),
      GIM_CheckType, /*MI*/0, /*Op*/1, /*Type*/GILLT_s64,
      GIM_CheckType, /*MI*/0, /*Op*/2, /*Type*/GILLT_s64,
      GIM_CheckRegBankForClass, /*MI*/0, /*Op*/0, /*RC*/GIMT_Encode2(AMDGPU::VReg_64RegClassID),
      GIM_Try, /*On fail goto*//*Label 5569*/ GIMT_Encode4(406853), // Rule ID 6558 //
        GIM_RecordInsn, /*DefineMI*/1, /*MI*/0, /*OpIdx*/2, // MIs[1]
        GIM_CheckOpcode, /*MI*/1, GIMT_Encode2(TargetOpcode::G_FCONSTANT),
        GIM_CheckAPFloatImmPredicate, /*MI*/1, /*Predicate*/GIMT_Encode2(GICXXPred_APFloat_Predicate_fpimm_pos_pow2_prefer_ldexp_f64),
        // MIs[1] Operand 1
        // No operand predicates
        GIM_CheckIsSafeToFold, /*InsnID*/1,
        GIM_CheckComplexPattern, /*MI*/0, /*Op*/1, /*Renderer*/GIMT_Encode2(0), GIMT_Encode2(GICP_gi_vop3mods),
        // (strict_fmul:{ *:[f64] } (VOP3Mods:{ *:[f64] } f64:{ *:[f64] }:$src0, i32:{ *:[i32] }:$src0_mods), (fpimm:{ *:[f64] })<<P:Predicate_fpimm_pos_pow2_prefer_ldexp_f64>><<X:FPPow2ToExponentXForm>>:$src1)  =>  (V_LDEXP_F64_e64:{ *:[f64] } i32:{ *:[i32] }:$src0_mods, VSrc_b64:{ *:[f64] }:$src0, 0:{ *:[i32] }, (S_MOV_B32:{ *:[i16] } (FPPow2ToExponentXForm:{ *:[i32] } ?:{ *:[f64] }:$src1)))
        GIR_MakeTempReg, /*TempRegID*/0, /*TypeID*/GILLT_s16,
        GIR_BuildMI, /*InsnID*/1, /*Opcode*/GIMT_Encode2(AMDGPU::S_MOV_B32),
        GIR_AddTempRegister, /*InsnID*/1, /*TempRegID*/0, /*TempRegFlags*/GIMT_Encode2(RegState::Define),
        GIR_CustomRenderer, /*InsnID*/1, /*OldInsnID*/1, /*Renderer*/GIMT_Encode2(GICR_renderFPPow2ToExponent), // src1
        GIR_ConstrainSelectedInstOperands, /*InsnID*/1,
        GIR_BuildMI, /*InsnID*/0, /*Opcode*/GIMT_Encode2(AMDGPU::V_LDEXP_F64_e64),
        GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/0, // DstI[vdst]
        GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/1, // src0_mods
        GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/0, // src0
        GIR_AddImm8, /*InsnID*/0, /*Imm*/0,
        GIR_AddSimpleTempRegister, /*InsnID*/0, /*TempRegID*/0,
        GIR_AddImm8, /*InsnID*/0, /*Imm*/0,
        GIR_AddImm8, /*InsnID*/0, /*Imm*/0,
        GIR_ConstrainSelectedInstOperands, /*InsnID*/0,
        GIR_EraseFromParent, /*InsnID*/0,
        // GIR_Coverage, 6558,
        GIR_Done,
      // Label 5569: @406853
      GIM_Try, /*On fail goto*//*Label 5570*/ GIMT_Encode4(406933), // Rule ID 10804 //
        GIM_RecordInsn, /*DefineMI*/1, /*MI*/0, /*OpIdx*/1, // MIs[1]
        GIM_CheckOpcode, /*MI*/1, GIMT_Encode2(TargetOpcode::G_FCONSTANT),
        GIM_CheckAPFloatImmPredicate, /*MI*/1, /*Predicate*/GIMT_Encode2(GICXXPred_APFloat_Predicate_fpimm_pos_pow2_prefer_ldexp_f64),
        // MIs[1] Operand 1
        // No operand predicates
        GIM_CheckIsSafeToFold, /*InsnID*/1,
        GIM_CheckComplexPattern, /*MI*/0, /*Op*/2, /*Renderer*/GIMT_Encode2(0), GIMT_Encode2(GICP_gi_vop3mods),
        // (strict_fmul:{ *:[f64] } (fpimm:{ *:[f64] })<<P:Predicate_fpimm_pos_pow2_prefer_ldexp_f64>><<X:FPPow2ToExponentXForm>>:$src1, (VOP3Mods:{ *:[f64] } f64:{ *:[f64] }:$src0, i32:{ *:[i32] }:$src0_mods))  =>  (V_LDEXP_F64_e64:{ *:[f64] } i32:{ *:[i32] }:$src0_mods, VSrc_b64:{ *:[f64] }:$src0, 0:{ *:[i32] }, (S_MOV_B32:{ *:[i16] } (FPPow2ToExponentXForm:{ *:[i32] } ?:{ *:[f64] }:$src1)))
        GIR_MakeTempReg, /*TempRegID*/0, /*TypeID*/GILLT_s16,
        GIR_BuildMI, /*InsnID*/1, /*Opcode*/GIMT_Encode2(AMDGPU::S_MOV_B32),
        GIR_AddTempRegister, /*InsnID*/1, /*TempRegID*/0, /*TempRegFlags*/GIMT_Encode2(RegState::Define),
        GIR_CustomRenderer, /*InsnID*/1, /*OldInsnID*/1, /*Renderer*/GIMT_Encode2(GICR_renderFPPow2ToExponent), // src1
        GIR_ConstrainSelectedInstOperands, /*InsnID*/1,
        GIR_BuildMI, /*InsnID*/0, /*Opcode*/GIMT_Encode2(AMDGPU::V_LDEXP_F64_e64),
        GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/0, // DstI[vdst]
        GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/1, // src0_mods
        GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/0, // src0
        GIR_AddImm8, /*InsnID*/0, /*Imm*/0,
        GIR_AddSimpleTempRegister, /*InsnID*/0, /*TempRegID*/0,
        GIR_AddImm8, /*InsnID*/0, /*Imm*/0,
        GIR_AddImm8, /*InsnID*/0, /*Imm*/0,
        GIR_ConstrainSelectedInstOperands, /*InsnID*/0,
        GIR_EraseFromParent, /*InsnID*/0,
        // GIR_Coverage, 10804,
        GIR_Done,
      // Label 5570: @406933
      GIM_Try, /*On fail goto*//*Label 5571*/ GIMT_Encode4(407017), // Rule ID 6562 //
        GIM_RecordInsn, /*DefineMI*/1, /*MI*/0, /*OpIdx*/1, // MIs[1]
        GIM_CheckOpcode, /*MI*/1, GIMT_Encode2(TargetOpcode::G_FABS),
        GIM_CheckType, /*MI*/1, /*Op*/1, /*Type*/GILLT_s64,
        GIM_RecordInsn, /*DefineMI*/2, /*MI*/0, /*OpIdx*/2, // MIs[2]
        GIM_CheckOpcode, /*MI*/2, GIMT_Encode2(TargetOpcode::G_FCONSTANT),
        GIM_CheckAPFloatImmPredicate, /*MI*/2, /*Predicate*/GIMT_Encode2(GICXXPred_APFloat_Predicate_fpimm_neg_pow2_prefer_ldexp_f64),
        // MIs[2] Operand 1
        // No operand predicates
        GIM_CheckIsSafeToFold, /*InsnID*/1,
        GIM_CheckIsSafeToFold, /*InsnID*/2,
        // (strict_fmul:{ *:[f64] } (fabs:{ *:[f64] } f64:{ *:[f64] }:$src0), (fpimm:{ *:[f64] })<<P:Predicate_fpimm_neg_pow2_prefer_ldexp_f64>><<X:FPPow2ToExponentXForm>>:$src1)  =>  (V_LDEXP_F64_e64:{ *:[f64] } 3:{ *:[i32] }, VSrc_b64:{ *:[f64] }:$src0, 0:{ *:[i32] }, (S_MOV_B32:{ *:[i16] } (FPPow2ToExponentXForm:{ *:[i32] } ?:{ *:[f64] }:$src1)))
        GIR_MakeTempReg, /*TempRegID*/0, /*TypeID*/GILLT_s16,
        GIR_BuildMI, /*InsnID*/1, /*Opcode*/GIMT_Encode2(AMDGPU::S_MOV_B32),
        GIR_AddTempRegister, /*InsnID*/1, /*TempRegID*/0, /*TempRegFlags*/GIMT_Encode2(RegState::Define),
        GIR_CustomRenderer, /*InsnID*/1, /*OldInsnID*/2, /*Renderer*/GIMT_Encode2(GICR_renderFPPow2ToExponent), // src1
        GIR_ConstrainSelectedInstOperands, /*InsnID*/1,
        GIR_BuildMI, /*InsnID*/0, /*Opcode*/GIMT_Encode2(AMDGPU::V_LDEXP_F64_e64),
        GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/0, // DstI[vdst]
        GIR_AddImm8, /*InsnID*/0, /*Imm*/3,
        GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/1, /*OpIdx*/1, // src0
        GIR_AddImm8, /*InsnID*/0, /*Imm*/0,
        GIR_AddSimpleTempRegister, /*InsnID*/0, /*TempRegID*/0,
        GIR_AddImm8, /*InsnID*/0, /*Imm*/0,
        GIR_AddImm8, /*InsnID*/0, /*Imm*/0,
        GIR_ConstrainSelectedInstOperands, /*InsnID*/0,
        GIR_EraseFromParent, /*InsnID*/0,
        // GIR_Coverage, 6562,
        GIR_Done,
      // Label 5571: @407017
      GIM_Try, /*On fail goto*//*Label 5572*/ GIMT_Encode4(407101), // Rule ID 10808 //
        GIM_RecordInsn, /*DefineMI*/1, /*MI*/0, /*OpIdx*/1, // MIs[1]
        GIM_CheckOpcode, /*MI*/1, GIMT_Encode2(TargetOpcode::G_FCONSTANT),
        GIM_CheckAPFloatImmPredicate, /*MI*/1, /*Predicate*/GIMT_Encode2(GICXXPred_APFloat_Predicate_fpimm_neg_pow2_prefer_ldexp_f64),
        // MIs[1] Operand 1
        // No operand predicates
        GIM_RecordInsn, /*DefineMI*/2, /*MI*/0, /*OpIdx*/2, // MIs[2]
        GIM_CheckOpcode, /*MI*/2, GIMT_Encode2(TargetOpcode::G_FABS),
        GIM_CheckType, /*MI*/2, /*Op*/1, /*Type*/GILLT_s64,
        GIM_CheckIsSafeToFold, /*InsnID*/1,
        GIM_CheckIsSafeToFold, /*InsnID*/2,
        // (strict_fmul:{ *:[f64] } (fpimm:{ *:[f64] })<<P:Predicate_fpimm_neg_pow2_prefer_ldexp_f64>><<X:FPPow2ToExponentXForm>>:$src1, (fabs:{ *:[f64] } f64:{ *:[f64] }:$src0))  =>  (V_LDEXP_F64_e64:{ *:[f64] } 3:{ *:[i32] }, VSrc_b64:{ *:[f64] }:$src0, 0:{ *:[i32] }, (S_MOV_B32:{ *:[i16] } (FPPow2ToExponentXForm:{ *:[i32] } ?:{ *:[f64] }:$src1)))
        GIR_MakeTempReg, /*TempRegID*/0, /*TypeID*/GILLT_s16,
        GIR_BuildMI, /*InsnID*/1, /*Opcode*/GIMT_Encode2(AMDGPU::S_MOV_B32),
        GIR_AddTempRegister, /*InsnID*/1, /*TempRegID*/0, /*TempRegFlags*/GIMT_Encode2(RegState::Define),
        GIR_CustomRenderer, /*InsnID*/1, /*OldInsnID*/1, /*Renderer*/GIMT_Encode2(GICR_renderFPPow2ToExponent), // src1
        GIR_ConstrainSelectedInstOperands, /*InsnID*/1,
        GIR_BuildMI, /*InsnID*/0, /*Opcode*/GIMT_Encode2(AMDGPU::V_LDEXP_F64_e64),
        GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/0, // DstI[vdst]
        GIR_AddImm8, /*InsnID*/0, /*Imm*/3,
        GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/2, /*OpIdx*/1, // src0
        GIR_AddImm8, /*InsnID*/0, /*Imm*/0,
        GIR_AddSimpleTempRegister, /*InsnID*/0, /*TempRegID*/0,
        GIR_AddImm8, /*InsnID*/0, /*Imm*/0,
        GIR_AddImm8, /*InsnID*/0, /*Imm*/0,
        GIR_ConstrainSelectedInstOperands, /*InsnID*/0,
        GIR_EraseFromParent, /*InsnID*/0,
        // GIR_Coverage, 10808,
        GIR_Done,
      // Label 5572: @407101
      GIM_Try, /*On fail goto*//*Label 5573*/ GIMT_Encode4(407171), // Rule ID 10806 //
        GIM_RecordInsn, /*DefineMI*/1, /*MI*/0, /*OpIdx*/1, // MIs[1]
        GIM_CheckOpcode, /*MI*/1, GIMT_Encode2(TargetOpcode::G_FCONSTANT),
        GIM_CheckAPFloatImmPredicate, /*MI*/1, /*Predicate*/GIMT_Encode2(GICXXPred_APFloat_Predicate_fpimm_neg_pow2_prefer_ldexp_f64),
        // MIs[1] Operand 1
        // No operand predicates
        GIM_CheckIsSafeToFold, /*InsnID*/1,
        // (strict_fmul:{ *:[f64] } (fpimm:{ *:[f64] })<<P:Predicate_fpimm_neg_pow2_prefer_ldexp_f64>><<X:FPPow2ToExponentXForm>>:$src1, f64:{ *:[f64] }:$src0)  =>  (V_LDEXP_F64_e64:{ *:[f64] } 1:{ *:[i32] }, VSrc_b64:{ *:[f64] }:$src0, 0:{ *:[i32] }, (S_MOV_B32:{ *:[i16] } (FPPow2ToExponentXForm:{ *:[i32] } ?:{ *:[f64] }:$src1)))
        GIR_MakeTempReg, /*TempRegID*/0, /*TypeID*/GILLT_s16,
        GIR_BuildMI, /*InsnID*/1, /*Opcode*/GIMT_Encode2(AMDGPU::S_MOV_B32),
        GIR_AddTempRegister, /*InsnID*/1, /*TempRegID*/0, /*TempRegFlags*/GIMT_Encode2(RegState::Define),
        GIR_CustomRenderer, /*InsnID*/1, /*OldInsnID*/1, /*Renderer*/GIMT_Encode2(GICR_renderFPPow2ToExponent), // src1
        GIR_ConstrainSelectedInstOperands, /*InsnID*/1,
        GIR_BuildMI, /*InsnID*/0, /*Opcode*/GIMT_Encode2(AMDGPU::V_LDEXP_F64_e64),
        GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/0, // DstI[vdst]
        GIR_AddImm8, /*InsnID*/0, /*Imm*/1,
        GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/2, // src0
        GIR_AddImm8, /*InsnID*/0, /*Imm*/0,
        GIR_AddSimpleTempRegister, /*InsnID*/0, /*TempRegID*/0,
        GIR_AddImm8, /*InsnID*/0, /*Imm*/0,
        GIR_AddImm8, /*InsnID*/0, /*Imm*/0,
        GIR_ConstrainSelectedInstOperands, /*InsnID*/0,
        GIR_EraseFromParent, /*InsnID*/0,
        // GIR_Coverage, 10806,
        GIR_Done,
      // Label 5573: @407171
      GIM_Try, /*On fail goto*//*Label 5574*/ GIMT_Encode4(407241), // Rule ID 6560 //
        GIM_RecordInsn, /*DefineMI*/1, /*MI*/0, /*OpIdx*/2, // MIs[1]
        GIM_CheckOpcode, /*MI*/1, GIMT_Encode2(TargetOpcode::G_FCONSTANT),
        GIM_CheckAPFloatImmPredicate, /*MI*/1, /*Predicate*/GIMT_Encode2(GICXXPred_APFloat_Predicate_fpimm_neg_pow2_prefer_ldexp_f64),
        // MIs[1] Operand 1
        // No operand predicates
        GIM_CheckIsSafeToFold, /*InsnID*/1,
        // (strict_fmul:{ *:[f64] } f64:{ *:[f64] }:$src0, (fpimm:{ *:[f64] })<<P:Predicate_fpimm_neg_pow2_prefer_ldexp_f64>><<X:FPPow2ToExponentXForm>>:$src1)  =>  (V_LDEXP_F64_e64:{ *:[f64] } 1:{ *:[i32] }, VSrc_b64:{ *:[f64] }:$src0, 0:{ *:[i32] }, (S_MOV_B32:{ *:[i16] } (FPPow2ToExponentXForm:{ *:[i32] } ?:{ *:[f64] }:$src1)))
        GIR_MakeTempReg, /*TempRegID*/0, /*TypeID*/GILLT_s16,
        GIR_BuildMI, /*InsnID*/1, /*Opcode*/GIMT_Encode2(AMDGPU::S_MOV_B32),
        GIR_AddTempRegister, /*InsnID*/1, /*TempRegID*/0, /*TempRegFlags*/GIMT_Encode2(RegState::Define),
        GIR_CustomRenderer, /*InsnID*/1, /*OldInsnID*/1, /*Renderer*/GIMT_Encode2(GICR_renderFPPow2ToExponent), // src1
        GIR_ConstrainSelectedInstOperands, /*InsnID*/1,
        GIR_BuildMI, /*InsnID*/0, /*Opcode*/GIMT_Encode2(AMDGPU::V_LDEXP_F64_e64),
        GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/0, // DstI[vdst]
        GIR_AddImm8, /*InsnID*/0, /*Imm*/1,
        GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/1, // src0
        GIR_AddImm8, /*InsnID*/0, /*Imm*/0,
        GIR_AddSimpleTempRegister, /*InsnID*/0, /*TempRegID*/0,
        GIR_AddImm8, /*InsnID*/0, /*Imm*/0,
        GIR_AddImm8, /*InsnID*/0, /*Imm*/0,
        GIR_ConstrainSelectedInstOperands, /*InsnID*/0,
        GIR_EraseFromParent, /*InsnID*/0,
        // GIR_Coverage, 6560,
        GIR_Done,
      // Label 5574: @407241
      GIM_Try, /*On fail goto*//*Label 5575*/ GIMT_Encode4(407306), // Rule ID 859 //
        GIM_CheckFeatures, GIMT_Encode2(GIFBS_isNotGFX12Plus),
        GIM_CheckComplexPattern, /*MI*/0, /*Op*/1, /*Renderer*/GIMT_Encode2(0), GIMT_Encode2(GICP_gi_vop3mods0),
        GIM_CheckComplexPattern, /*MI*/0, /*Op*/2, /*Renderer*/GIMT_Encode2(1), GIMT_Encode2(GICP_gi_vop3mods),
        // (strict_fmul:{ *:[f64] } (VOP3Mods0:{ *:[f64] } f64:{ *:[f64] }:$src0, i32:{ *:[i32] }:$src0_modifiers, i1:{ *:[i1] }:$clamp, i32:{ *:[i32] }:$omod), (VOP3Mods:{ *:[f64] } f64:{ *:[f64] }:$src1, i32:{ *:[i32] }:$src1_modifiers))  =>  (V_MUL_F64_e64:{ *:[f64] } i32:{ *:[i32] }:$src0_modifiers, f64:{ *:[f64] }:$src0, i32:{ *:[i32] }:$src1_modifiers, f64:{ *:[f64] }:$src1, i1:{ *:[i1] }:$clamp, i32:{ *:[i32] }:$omod)
        GIR_BuildMI, /*InsnID*/0, /*Opcode*/GIMT_Encode2(AMDGPU::V_MUL_F64_e64),
        GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/0, // DstI[vdst]
        GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/1, // src0_modifiers
        GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/0, // src0
        GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(1), /*SubOperand*/1, // src1_modifiers
        GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(1), /*SubOperand*/0, // src1
        GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/2, // clamp
        GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/3, // omod
        GIR_ConstrainSelectedInstOperands, /*InsnID*/0,
        GIR_EraseFromParent, /*InsnID*/0,
        // GIR_Coverage, 859,
        GIR_Done,
      // Label 5575: @407306
      GIM_Try, /*On fail goto*//*Label 5576*/ GIMT_Encode4(407371), // Rule ID 7177 //
        GIM_CheckFeatures, GIMT_Encode2(GIFBS_isNotGFX12Plus),
        GIM_CheckComplexPattern, /*MI*/0, /*Op*/1, /*Renderer*/GIMT_Encode2(0), GIMT_Encode2(GICP_gi_vop3mods),
        GIM_CheckComplexPattern, /*MI*/0, /*Op*/2, /*Renderer*/GIMT_Encode2(1), GIMT_Encode2(GICP_gi_vop3mods0),
        // (strict_fmul:{ *:[f64] } (VOP3Mods:{ *:[f64] } f64:{ *:[f64] }:$src1, i32:{ *:[i32] }:$src1_modifiers), (VOP3Mods0:{ *:[f64] } f64:{ *:[f64] }:$src0, i32:{ *:[i32] }:$src0_modifiers, i1:{ *:[i1] }:$clamp, i32:{ *:[i32] }:$omod))  =>  (V_MUL_F64_e64:{ *:[f64] } i32:{ *:[i32] }:$src0_modifiers, f64:{ *:[f64] }:$src0, i32:{ *:[i32] }:$src1_modifiers, f64:{ *:[f64] }:$src1, i1:{ *:[i1] }:$clamp, i32:{ *:[i32] }:$omod)
        GIR_BuildMI, /*InsnID*/0, /*Opcode*/GIMT_Encode2(AMDGPU::V_MUL_F64_e64),
        GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/0, // DstI[vdst]
        GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(1), /*SubOperand*/1, // src0_modifiers
        GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(1), /*SubOperand*/0, // src0
        GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/1, // src1_modifiers
        GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/0, // src1
        GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(1), /*SubOperand*/2, // clamp
        GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(1), /*SubOperand*/3, // omod
        GIR_ConstrainSelectedInstOperands, /*InsnID*/0,
        GIR_EraseFromParent, /*InsnID*/0,
        // GIR_Coverage, 7177,
        GIR_Done,
      // Label 5576: @407371
      GIM_Reject,
    // Label 5568: @407372
    GIM_Reject,
    // Label 5553: @407373
    GIM_Try, /*On fail goto*//*Label 5577*/ GIMT_Encode4(407453), // Rule ID 962 //
      GIM_CheckType, /*MI*/0, /*Op*/1, /*Type*/GILLT_v2s16,
      GIM_CheckType, /*MI*/0, /*Op*/2, /*Type*/GILLT_v2s16,
      GIM_CheckRegBankForClass, /*MI*/0, /*Op*/0, /*RC*/GIMT_Encode2(AMDGPU::VGPR_32RegClassID),
      GIM_CheckComplexPattern, /*MI*/0, /*Op*/1, /*Renderer*/GIMT_Encode2(0), GIMT_Encode2(GICP_gi_vop3pmods),
      GIM_CheckComplexPattern, /*MI*/0, /*Op*/2, /*Renderer*/GIMT_Encode2(1), GIMT_Encode2(GICP_gi_vop3pmods),
      // (strict_fmul:{ *:[v2f16] } (VOP3PMods:{ *:[v2f16] } v2f16:{ *:[v2f16] }:$src0, i32:{ *:[i32] }:$src0_modifiers), (VOP3PMods:{ *:[v2f16] } v2f16:{ *:[v2f16] }:$src1, i32:{ *:[i32] }:$src1_modifiers))  =>  (V_PK_MUL_F16:{ *:[v2f16] } i32:{ *:[i32] }:$src0_modifiers, v2f16:{ *:[v2f16] }:$src0, i32:{ *:[i32] }:$src1_modifiers, v2f16:{ *:[v2f16] }:$src1)
      GIR_BuildMI, /*InsnID*/0, /*Opcode*/GIMT_Encode2(AMDGPU::V_PK_MUL_F16),
      GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/0, // DstI[vdst]
      GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/1, // src0_modifiers
      GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/0, // src0
      GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(1), /*SubOperand*/1, // src1_modifiers
      GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(1), /*SubOperand*/0, // src1
      GIR_AddImm8, /*InsnID*/0, /*Imm*/0,
      GIR_AddImm8, /*InsnID*/0, /*Imm*/0,
      GIR_AddImm8, /*InsnID*/0, /*Imm*/0,
      GIR_AddImm8, /*InsnID*/0, /*Imm*/0,
      GIR_AddImm8, /*InsnID*/0, /*Imm*/0,
      GIR_ConstrainSelectedInstOperands, /*InsnID*/0,
      GIR_EraseFromParent, /*InsnID*/0,
      // GIR_Coverage, 962,
      GIR_Done,
    // Label 5577: @407453
    GIM_Reject,
    // Label 5554: @407454
    GIM_Try, /*On fail goto*//*Label 5578*/ GIMT_Encode4(407537), // Rule ID 1086 //
      GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasPackedFP32Ops),
      GIM_CheckType, /*MI*/0, /*Op*/1, /*Type*/GILLT_v2s32,
      GIM_CheckType, /*MI*/0, /*Op*/2, /*Type*/GILLT_v2s32,
      GIM_CheckRegBankForClass, /*MI*/0, /*Op*/0, /*RC*/GIMT_Encode2(AMDGPU::VReg_64RegClassID),
      GIM_CheckComplexPattern, /*MI*/0, /*Op*/1, /*Renderer*/GIMT_Encode2(0), GIMT_Encode2(GICP_gi_vop3pmods),
      GIM_CheckComplexPattern, /*MI*/0, /*Op*/2, /*Renderer*/GIMT_Encode2(1), GIMT_Encode2(GICP_gi_vop3pmods),
      // (strict_fmul:{ *:[v2f32] } (VOP3PMods:{ *:[v2f32] } v2f32:{ *:[v2f32] }:$src0, i32:{ *:[i32] }:$src0_modifiers), (VOP3PMods:{ *:[v2f32] } v2f32:{ *:[v2f32] }:$src1, i32:{ *:[i32] }:$src1_modifiers))  =>  (V_PK_MUL_F32:{ *:[v2f32] } i32:{ *:[i32] }:$src0_modifiers, v2f32:{ *:[v2f32] }:$src0, i32:{ *:[i32] }:$src1_modifiers, v2f32:{ *:[v2f32] }:$src1)
      GIR_BuildMI, /*InsnID*/0, /*Opcode*/GIMT_Encode2(AMDGPU::V_PK_MUL_F32),
      GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/0, // DstI[vdst]
      GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/1, // src0_modifiers
      GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/0, // src0
      GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(1), /*SubOperand*/1, // src1_modifiers
      GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(1), /*SubOperand*/0, // src1
      GIR_AddImm8, /*InsnID*/0, /*Imm*/0,
      GIR_AddImm8, /*InsnID*/0, /*Imm*/0,
      GIR_AddImm8, /*InsnID*/0, /*Imm*/0,
      GIR_AddImm8, /*InsnID*/0, /*Imm*/0,
      GIR_AddImm8, /*InsnID*/0, /*Imm*/0,
      GIR_ConstrainSelectedInstOperands, /*InsnID*/0,
      GIR_EraseFromParent, /*InsnID*/0,
      // GIR_Coverage, 1086,
      GIR_Done,
    // Label 5578: @407537
    GIM_Reject,
    // Label 5555: @407538
    GIM_Reject,
    // Label 101: @407539
    GIM_SwitchType, /*MI*/0, /*Op*/0, /*[*/GIMT_Encode2(8), GIMT_Encode2(13), /*)*//*default:*//*Label 5584*/ GIMT_Encode4(408513),
    /*GILLT_s16*//*Label 5579*/ GIMT_Encode4(407570),
    /*GILLT_s32*//*Label 5580*/ GIMT_Encode4(407893),
    /*GILLT_s64*//*Label 5581*/ GIMT_Encode4(408124),
    /*GILLT_v2s16*//*Label 5582*/ GIMT_Encode4(408306),
    /*GILLT_v2s32*//*Label 5583*/ GIMT_Encode4(408408),
    // Label 5579: @407570
    GIM_Try, /*On fail goto*//*Label 5585*/ GIMT_Encode4(407892),
      GIM_CheckType, /*MI*/0, /*Op*/1, /*Type*/GILLT_s16,
      GIM_CheckType, /*MI*/0, /*Op*/2, /*Type*/GILLT_s16,
      GIM_CheckType, /*MI*/0, /*Op*/3, /*Type*/GILLT_s16,
      GIM_Try, /*On fail goto*//*Label 5586*/ GIMT_Encode4(407631), // Rule ID 114 //
        GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasSALUFloatInsts),
        GIM_CheckRegBankForClass, /*MI*/0, /*Op*/0, /*RC*/GIMT_Encode2(AMDGPU::SReg_32RegClassID),
        GIM_CheckRegBankForClass, /*MI*/0, /*Op*/1, /*RC*/GIMT_Encode2(AMDGPU::SReg_32RegClassID),
        GIM_CheckRegBankForClass, /*MI*/0, /*Op*/2, /*RC*/GIMT_Encode2(AMDGPU::SReg_32RegClassID),
        GIM_CheckRegBankForClass, /*MI*/0, /*Op*/3, /*RC*/GIMT_Encode2(AMDGPU::SReg_32RegClassID),
        GIM_CheckCxxInsnPredicate, /*MI*/0, /*FnId*/GIMT_Encode2(GICXXPred_MI_Predicate_anonymous_17636),
        // (strict_fma:{ *:[f16] } SSrc_f16:{ *:[f16] }:$src0, SSrc_f16:{ *:[f16] }:$src1, SReg_32:{ *:[f16] }:$src2)<<P:Predicate_anonymous_17636>>  =>  (S_FMAC_F16:{ *:[f16] } SSrc_f16:{ *:[f16] }:$src0, SSrc_f16:{ *:[f16] }:$src1, SReg_32:{ *:[f16] }:$src2)
        GIR_MutateOpcode, /*InsnID*/0, /*RecycleInsnID*/0, /*Opcode*/GIMT_Encode2(AMDGPU::S_FMAC_F16),
        GIR_AddImplicitUse, /*InsnID*/0, GIMT_Encode2(AMDGPU::MODE),
        GIR_ConstrainSelectedInstOperands, /*InsnID*/0,
        // GIR_Coverage, 114,
        GIR_Done,
      // Label 5586: @407631
      GIM_Try, /*On fail goto*//*Label 5587*/ GIMT_Encode4(407718), // Rule ID 921 //
        GIM_CheckFeatures, GIMT_Encode2(GIFBS_Has16BitInsts_isGFX8Only),
        GIM_CheckRegBankForClass, /*MI*/0, /*Op*/0, /*RC*/GIMT_Encode2(AMDGPU::VGPR_32RegClassID),
        GIM_CheckComplexPattern, /*MI*/0, /*Op*/1, /*Renderer*/GIMT_Encode2(0), GIMT_Encode2(GICP_gi_vop3mods0),
        GIM_CheckComplexPattern, /*MI*/0, /*Op*/2, /*Renderer*/GIMT_Encode2(1), GIMT_Encode2(GICP_gi_vop3mods),
        GIM_CheckComplexPattern, /*MI*/0, /*Op*/3, /*Renderer*/GIMT_Encode2(2), GIMT_Encode2(GICP_gi_vop3mods),
        // (strict_fma:{ *:[f16] } (VOP3Mods0:{ *:[f16] } f16:{ *:[f16] }:$src0, i32:{ *:[i32] }:$src0_modifiers, i1:{ *:[i1] }:$clamp, i32:{ *:[i32] }:$omod), (VOP3Mods:{ *:[f16] } f16:{ *:[f16] }:$src1, i32:{ *:[i32] }:$src1_modifiers), (VOP3Mods:{ *:[f16] } f16:{ *:[f16] }:$src2, i32:{ *:[i32] }:$src2_modifiers))  =>  (V_FMA_F16_e64:{ *:[f16] } i32:{ *:[i32] }:$src0_modifiers, f16:{ *:[f16] }:$src0, i32:{ *:[i32] }:$src1_modifiers, f16:{ *:[f16] }:$src1, i32:{ *:[i32] }:$src2_modifiers, f16:{ *:[f16] }:$src2, i1:{ *:[i1] }:$clamp, i32:{ *:[i32] }:$omod)
        GIR_BuildMI, /*InsnID*/0, /*Opcode*/GIMT_Encode2(AMDGPU::V_FMA_F16_e64),
        GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/0, // DstI[vdst]
        GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/1, // src0_modifiers
        GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/0, // src0
        GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(1), /*SubOperand*/1, // src1_modifiers
        GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(1), /*SubOperand*/0, // src1
        GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(2), /*SubOperand*/1, // src2_modifiers
        GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(2), /*SubOperand*/0, // src2
        GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/2, // clamp
        GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/3, // omod
        GIR_ConstrainSelectedInstOperands, /*InsnID*/0,
        GIR_EraseFromParent, /*InsnID*/0,
        // GIR_Coverage, 921,
        GIR_Done,
      // Label 5587: @407718
      GIM_Try, /*On fail goto*//*Label 5588*/ GIMT_Encode4(407805), // Rule ID 7192 //
        GIM_CheckFeatures, GIMT_Encode2(GIFBS_Has16BitInsts_isGFX8Only),
        GIM_CheckRegBankForClass, /*MI*/0, /*Op*/0, /*RC*/GIMT_Encode2(AMDGPU::VGPR_32RegClassID),
        GIM_CheckComplexPattern, /*MI*/0, /*Op*/1, /*Renderer*/GIMT_Encode2(0), GIMT_Encode2(GICP_gi_vop3mods),
        GIM_CheckComplexPattern, /*MI*/0, /*Op*/2, /*Renderer*/GIMT_Encode2(1), GIMT_Encode2(GICP_gi_vop3mods0),
        GIM_CheckComplexPattern, /*MI*/0, /*Op*/3, /*Renderer*/GIMT_Encode2(2), GIMT_Encode2(GICP_gi_vop3mods),
        // (strict_fma:{ *:[f16] } (VOP3Mods:{ *:[f16] } f16:{ *:[f16] }:$src1, i32:{ *:[i32] }:$src1_modifiers), (VOP3Mods0:{ *:[f16] } f16:{ *:[f16] }:$src0, i32:{ *:[i32] }:$src0_modifiers, i1:{ *:[i1] }:$clamp, i32:{ *:[i32] }:$omod), (VOP3Mods:{ *:[f16] } f16:{ *:[f16] }:$src2, i32:{ *:[i32] }:$src2_modifiers))  =>  (V_FMA_F16_e64:{ *:[f16] } i32:{ *:[i32] }:$src0_modifiers, f16:{ *:[f16] }:$src0, i32:{ *:[i32] }:$src1_modifiers, f16:{ *:[f16] }:$src1, i32:{ *:[i32] }:$src2_modifiers, f16:{ *:[f16] }:$src2, i1:{ *:[i1] }:$clamp, i32:{ *:[i32] }:$omod)
        GIR_BuildMI, /*InsnID*/0, /*Opcode*/GIMT_Encode2(AMDGPU::V_FMA_F16_e64),
        GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/0, // DstI[vdst]
        GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(1), /*SubOperand*/1, // src0_modifiers
        GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(1), /*SubOperand*/0, // src0
        GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/1, // src1_modifiers
        GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/0, // src1
        GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(2), /*SubOperand*/1, // src2_modifiers
        GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(2), /*SubOperand*/0, // src2
        GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(1), /*SubOperand*/2, // clamp
        GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(1), /*SubOperand*/3, // omod
        GIR_ConstrainSelectedInstOperands, /*InsnID*/0,
        GIR_EraseFromParent, /*InsnID*/0,
        // GIR_Coverage, 7192,
        GIR_Done,
      // Label 5588: @407805
      GIM_Try, /*On fail goto*//*Label 5589*/ GIMT_Encode4(407891), // Rule ID 925 //
        GIM_CheckFeatures, GIMT_Encode2(GIFBS_isGFX9Plus),
        GIM_CheckRegBankForClass, /*MI*/0, /*Op*/0, /*RC*/GIMT_Encode2(AMDGPU::VGPR_32RegClassID),
        GIM_CheckComplexPattern, /*MI*/0, /*Op*/1, /*Renderer*/GIMT_Encode2(0), GIMT_Encode2(GICP_gi_vop3opselmods),
        GIM_CheckComplexPattern, /*MI*/0, /*Op*/2, /*Renderer*/GIMT_Encode2(1), GIMT_Encode2(GICP_gi_vop3opselmods),
        GIM_CheckComplexPattern, /*MI*/0, /*Op*/3, /*Renderer*/GIMT_Encode2(2), GIMT_Encode2(GICP_gi_vop3opselmods),
        // (strict_fma:{ *:[f16] } (VOP3OpSelMods:{ *:[f16] } f16:{ *:[f16] }:$src0, i32:{ *:[i32] }:$src0_modifiers), (VOP3OpSelMods:{ *:[f16] } f16:{ *:[f16] }:$src1, i32:{ *:[i32] }:$src1_modifiers), (VOP3OpSelMods:{ *:[f16] } f16:{ *:[f16] }:$src2, i32:{ *:[i32] }:$src2_modifiers))  =>  (V_FMA_F16_gfx9_e64:{ *:[f16] } i32:{ *:[i32] }:$src0_modifiers, f16:{ *:[f16] }:$src0, i32:{ *:[i32] }:$src1_modifiers, f16:{ *:[f16] }:$src1, i32:{ *:[i32] }:$src2_modifiers, f16:{ *:[f16] }:$src2)
        GIR_BuildMI, /*InsnID*/0, /*Opcode*/GIMT_Encode2(AMDGPU::V_FMA_F16_gfx9_e64),
        GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/0, // DstI[vdst]
        GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/1, // src0_modifiers
        GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/0, // src0
        GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(1), /*SubOperand*/1, // src1_modifiers
        GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(1), /*SubOperand*/0, // src1
        GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(2), /*SubOperand*/1, // src2_modifiers
        GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(2), /*SubOperand*/0, // src2
        GIR_AddImm8, /*InsnID*/0, /*Imm*/0,
        GIR_AddImm8, /*InsnID*/0, /*Imm*/0,
        GIR_AddImm8, /*InsnID*/0, /*Imm*/0,
        GIR_ConstrainSelectedInstOperands, /*InsnID*/0,
        GIR_EraseFromParent, /*InsnID*/0,
        // GIR_Coverage, 925,
        GIR_Done,
      // Label 5589: @407891
      GIM_Reject,
    // Label 5585: @407892
    GIM_Reject,
    // Label 5580: @407893
    GIM_Try, /*On fail goto*//*Label 5590*/ GIMT_Encode4(408123),
      GIM_CheckType, /*MI*/0, /*Op*/1, /*Type*/GILLT_s32,
      GIM_CheckType, /*MI*/0, /*Op*/2, /*Type*/GILLT_s32,
      GIM_CheckType, /*MI*/0, /*Op*/3, /*Type*/GILLT_s32,
      GIM_Try, /*On fail goto*//*Label 5591*/ GIMT_Encode4(407954), // Rule ID 112 //
        GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasSALUFloatInsts),
        GIM_CheckRegBankForClass, /*MI*/0, /*Op*/0, /*RC*/GIMT_Encode2(AMDGPU::SReg_32RegClassID),
        GIM_CheckRegBankForClass, /*MI*/0, /*Op*/1, /*RC*/GIMT_Encode2(AMDGPU::SReg_32RegClassID),
        GIM_CheckRegBankForClass, /*MI*/0, /*Op*/2, /*RC*/GIMT_Encode2(AMDGPU::SReg_32RegClassID),
        GIM_CheckRegBankForClass, /*MI*/0, /*Op*/3, /*RC*/GIMT_Encode2(AMDGPU::SReg_32RegClassID),
        GIM_CheckCxxInsnPredicate, /*MI*/0, /*FnId*/GIMT_Encode2(GICXXPred_MI_Predicate_anonymous_17636),
        // (strict_fma:{ *:[f32] } SSrc_f32:{ *:[f32] }:$src0, SSrc_f32:{ *:[f32] }:$src1, SReg_32:{ *:[f32] }:$src2)<<P:Predicate_anonymous_17636>>  =>  (S_FMAC_F32:{ *:[f32] } SSrc_f32:{ *:[f32] }:$src0, SSrc_f32:{ *:[f32] }:$src1, SReg_32:{ *:[f32] }:$src2)
        GIR_MutateOpcode, /*InsnID*/0, /*RecycleInsnID*/0, /*Opcode*/GIMT_Encode2(AMDGPU::S_FMAC_F32),
        GIR_AddImplicitUse, /*InsnID*/0, GIMT_Encode2(AMDGPU::MODE),
        GIR_ConstrainSelectedInstOperands, /*InsnID*/0,
        // GIR_Coverage, 112,
        GIR_Done,
      // Label 5591: @407954
      GIM_Try, /*On fail goto*//*Label 5592*/ GIMT_Encode4(408038), // Rule ID 852 //
        GIM_CheckRegBankForClass, /*MI*/0, /*Op*/0, /*RC*/GIMT_Encode2(AMDGPU::VGPR_32RegClassID),
        GIM_CheckComplexPattern, /*MI*/0, /*Op*/1, /*Renderer*/GIMT_Encode2(0), GIMT_Encode2(GICP_gi_vop3mods0),
        GIM_CheckComplexPattern, /*MI*/0, /*Op*/2, /*Renderer*/GIMT_Encode2(1), GIMT_Encode2(GICP_gi_vop3mods),
        GIM_CheckComplexPattern, /*MI*/0, /*Op*/3, /*Renderer*/GIMT_Encode2(2), GIMT_Encode2(GICP_gi_vop3mods),
        // (strict_fma:{ *:[f32] } (VOP3Mods0:{ *:[f32] } f32:{ *:[f32] }:$src0, i32:{ *:[i32] }:$src0_modifiers, i1:{ *:[i1] }:$clamp, i32:{ *:[i32] }:$omod), (VOP3Mods:{ *:[f32] } f32:{ *:[f32] }:$src1, i32:{ *:[i32] }:$src1_modifiers), (VOP3Mods:{ *:[f32] } f32:{ *:[f32] }:$src2, i32:{ *:[i32] }:$src2_modifiers))  =>  (V_FMA_F32_e64:{ *:[f32] } i32:{ *:[i32] }:$src0_modifiers, f32:{ *:[f32] }:$src0, i32:{ *:[i32] }:$src1_modifiers, f32:{ *:[f32] }:$src1, i32:{ *:[i32] }:$src2_modifiers, f32:{ *:[f32] }:$src2, i1:{ *:[i1] }:$clamp, i32:{ *:[i32] }:$omod)
        GIR_BuildMI, /*InsnID*/0, /*Opcode*/GIMT_Encode2(AMDGPU::V_FMA_F32_e64),
        GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/0, // DstI[vdst]
        GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/1, // src0_modifiers
        GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/0, // src0
        GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(1), /*SubOperand*/1, // src1_modifiers
        GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(1), /*SubOperand*/0, // src1
        GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(2), /*SubOperand*/1, // src2_modifiers
        GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(2), /*SubOperand*/0, // src2
        GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/2, // clamp
        GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/3, // omod
        GIR_ConstrainSelectedInstOperands, /*InsnID*/0,
        GIR_EraseFromParent, /*InsnID*/0,
        // GIR_Coverage, 852,
        GIR_Done,
      // Label 5592: @408038
      GIM_Try, /*On fail goto*//*Label 5593*/ GIMT_Encode4(408122), // Rule ID 7171 //
        GIM_CheckRegBankForClass, /*MI*/0, /*Op*/0, /*RC*/GIMT_Encode2(AMDGPU::VGPR_32RegClassID),
        GIM_CheckComplexPattern, /*MI*/0, /*Op*/1, /*Renderer*/GIMT_Encode2(0), GIMT_Encode2(GICP_gi_vop3mods),
        GIM_CheckComplexPattern, /*MI*/0, /*Op*/2, /*Renderer*/GIMT_Encode2(1), GIMT_Encode2(GICP_gi_vop3mods0),
        GIM_CheckComplexPattern, /*MI*/0, /*Op*/3, /*Renderer*/GIMT_Encode2(2), GIMT_Encode2(GICP_gi_vop3mods),
        // (strict_fma:{ *:[f32] } (VOP3Mods:{ *:[f32] } f32:{ *:[f32] }:$src1, i32:{ *:[i32] }:$src1_modifiers), (VOP3Mods0:{ *:[f32] } f32:{ *:[f32] }:$src0, i32:{ *:[i32] }:$src0_modifiers, i1:{ *:[i1] }:$clamp, i32:{ *:[i32] }:$omod), (VOP3Mods:{ *:[f32] } f32:{ *:[f32] }:$src2, i32:{ *:[i32] }:$src2_modifiers))  =>  (V_FMA_F32_e64:{ *:[f32] } i32:{ *:[i32] }:$src0_modifiers, f32:{ *:[f32] }:$src0, i32:{ *:[i32] }:$src1_modifiers, f32:{ *:[f32] }:$src1, i32:{ *:[i32] }:$src2_modifiers, f32:{ *:[f32] }:$src2, i1:{ *:[i1] }:$clamp, i32:{ *:[i32] }:$omod)
        GIR_BuildMI, /*InsnID*/0, /*Opcode*/GIMT_Encode2(AMDGPU::V_FMA_F32_e64),
        GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/0, // DstI[vdst]
        GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(1), /*SubOperand*/1, // src0_modifiers
        GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(1), /*SubOperand*/0, // src0
        GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/1, // src1_modifiers
        GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/0, // src1
        GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(2), /*SubOperand*/1, // src2_modifiers
        GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(2), /*SubOperand*/0, // src2
        GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(1), /*SubOperand*/2, // clamp
        GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(1), /*SubOperand*/3, // omod
        GIR_ConstrainSelectedInstOperands, /*InsnID*/0,
        GIR_EraseFromParent, /*InsnID*/0,
        // GIR_Coverage, 7171,
        GIR_Done,
      // Label 5593: @408122
      GIM_Reject,
    // Label 5590: @408123
    GIM_Reject,
    // Label 5581: @408124
    GIM_Try, /*On fail goto*//*Label 5594*/ GIMT_Encode4(408305),
      GIM_CheckType, /*MI*/0, /*Op*/1, /*Type*/GILLT_s64,
      GIM_CheckType, /*MI*/0, /*Op*/2, /*Type*/GILLT_s64,
      GIM_CheckType, /*MI*/0, /*Op*/3, /*Type*/GILLT_s64,
      GIM_CheckRegBankForClass, /*MI*/0, /*Op*/0, /*RC*/GIMT_Encode2(AMDGPU::VReg_64RegClassID),
      GIM_Try, /*On fail goto*//*Label 5595*/ GIMT_Encode4(408225), // Rule ID 855 //
        GIM_CheckComplexPattern, /*MI*/0, /*Op*/1, /*Renderer*/GIMT_Encode2(0), GIMT_Encode2(GICP_gi_vop3mods0),
        GIM_CheckComplexPattern, /*MI*/0, /*Op*/2, /*Renderer*/GIMT_Encode2(1), GIMT_Encode2(GICP_gi_vop3mods),
        GIM_CheckComplexPattern, /*MI*/0, /*Op*/3, /*Renderer*/GIMT_Encode2(2), GIMT_Encode2(GICP_gi_vop3mods),
        // (strict_fma:{ *:[f64] } (VOP3Mods0:{ *:[f64] } f64:{ *:[f64] }:$src0, i32:{ *:[i32] }:$src0_modifiers, i1:{ *:[i1] }:$clamp, i32:{ *:[i32] }:$omod), (VOP3Mods:{ *:[f64] } f64:{ *:[f64] }:$src1, i32:{ *:[i32] }:$src1_modifiers), (VOP3Mods:{ *:[f64] } f64:{ *:[f64] }:$src2, i32:{ *:[i32] }:$src2_modifiers))  =>  (V_FMA_F64_e64:{ *:[f64] } i32:{ *:[i32] }:$src0_modifiers, f64:{ *:[f64] }:$src0, i32:{ *:[i32] }:$src1_modifiers, f64:{ *:[f64] }:$src1, i32:{ *:[i32] }:$src2_modifiers, f64:{ *:[f64] }:$src2, i1:{ *:[i1] }:$clamp, i32:{ *:[i32] }:$omod)
        GIR_BuildMI, /*InsnID*/0, /*Opcode*/GIMT_Encode2(AMDGPU::V_FMA_F64_e64),
        GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/0, // DstI[vdst]
        GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/1, // src0_modifiers
        GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/0, // src0
        GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(1), /*SubOperand*/1, // src1_modifiers
        GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(1), /*SubOperand*/0, // src1
        GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(2), /*SubOperand*/1, // src2_modifiers
        GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(2), /*SubOperand*/0, // src2
        GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/2, // clamp
        GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/3, // omod
        GIR_ConstrainSelectedInstOperands, /*InsnID*/0,
        GIR_EraseFromParent, /*InsnID*/0,
        // GIR_Coverage, 855,
        GIR_Done,
      // Label 5595: @408225
      GIM_Try, /*On fail goto*//*Label 5596*/ GIMT_Encode4(408304), // Rule ID 7173 //
        GIM_CheckComplexPattern, /*MI*/0, /*Op*/1, /*Renderer*/GIMT_Encode2(0), GIMT_Encode2(GICP_gi_vop3mods),
        GIM_CheckComplexPattern, /*MI*/0, /*Op*/2, /*Renderer*/GIMT_Encode2(1), GIMT_Encode2(GICP_gi_vop3mods0),
        GIM_CheckComplexPattern, /*MI*/0, /*Op*/3, /*Renderer*/GIMT_Encode2(2), GIMT_Encode2(GICP_gi_vop3mods),
        // (strict_fma:{ *:[f64] } (VOP3Mods:{ *:[f64] } f64:{ *:[f64] }:$src1, i32:{ *:[i32] }:$src1_modifiers), (VOP3Mods0:{ *:[f64] } f64:{ *:[f64] }:$src0, i32:{ *:[i32] }:$src0_modifiers, i1:{ *:[i1] }:$clamp, i32:{ *:[i32] }:$omod), (VOP3Mods:{ *:[f64] } f64:{ *:[f64] }:$src2, i32:{ *:[i32] }:$src2_modifiers))  =>  (V_FMA_F64_e64:{ *:[f64] } i32:{ *:[i32] }:$src0_modifiers, f64:{ *:[f64] }:$src0, i32:{ *:[i32] }:$src1_modifiers, f64:{ *:[f64] }:$src1, i32:{ *:[i32] }:$src2_modifiers, f64:{ *:[f64] }:$src2, i1:{ *:[i1] }:$clamp, i32:{ *:[i32] }:$omod)
        GIR_BuildMI, /*InsnID*/0, /*Opcode*/GIMT_Encode2(AMDGPU::V_FMA_F64_e64),
        GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/0, // DstI[vdst]
        GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(1), /*SubOperand*/1, // src0_modifiers
        GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(1), /*SubOperand*/0, // src0
        GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/1, // src1_modifiers
        GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/0, // src1
        GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(2), /*SubOperand*/1, // src2_modifiers
        GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(2), /*SubOperand*/0, // src2
        GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(1), /*SubOperand*/2, // clamp
        GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(1), /*SubOperand*/3, // omod
        GIR_ConstrainSelectedInstOperands, /*InsnID*/0,
        GIR_EraseFromParent, /*InsnID*/0,
        // GIR_Coverage, 7173,
        GIR_Done,
      // Label 5596: @408304
      GIM_Reject,
    // Label 5594: @408305
    GIM_Reject,
    // Label 5582: @408306
    GIM_Try, /*On fail goto*//*Label 5597*/ GIMT_Encode4(408407), // Rule ID 958 //
      GIM_CheckType, /*MI*/0, /*Op*/1, /*Type*/GILLT_v2s16,
      GIM_CheckType, /*MI*/0, /*Op*/2, /*Type*/GILLT_v2s16,
      GIM_CheckType, /*MI*/0, /*Op*/3, /*Type*/GILLT_v2s16,
      GIM_CheckRegBankForClass, /*MI*/0, /*Op*/0, /*RC*/GIMT_Encode2(AMDGPU::VGPR_32RegClassID),
      GIM_CheckComplexPattern, /*MI*/0, /*Op*/1, /*Renderer*/GIMT_Encode2(0), GIMT_Encode2(GICP_gi_vop3pmods),
      GIM_CheckComplexPattern, /*MI*/0, /*Op*/2, /*Renderer*/GIMT_Encode2(1), GIMT_Encode2(GICP_gi_vop3pmods),
      GIM_CheckComplexPattern, /*MI*/0, /*Op*/3, /*Renderer*/GIMT_Encode2(2), GIMT_Encode2(GICP_gi_vop3pmods),
      // (strict_fma:{ *:[v2f16] } (VOP3PMods:{ *:[v2f16] } v2f16:{ *:[v2f16] }:$src0, i32:{ *:[i32] }:$src0_modifiers), (VOP3PMods:{ *:[v2f16] } v2f16:{ *:[v2f16] }:$src1, i32:{ *:[i32] }:$src1_modifiers), (VOP3PMods:{ *:[v2f16] } v2f16:{ *:[v2f16] }:$src2, i32:{ *:[i32] }:$src2_modifiers))  =>  (V_PK_FMA_F16:{ *:[v2f16] } i32:{ *:[i32] }:$src0_modifiers, v2f16:{ *:[v2f16] }:$src0, i32:{ *:[i32] }:$src1_modifiers, v2f16:{ *:[v2f16] }:$src1, i32:{ *:[i32] }:$src2_modifiers, v2f16:{ *:[v2f16] }:$src2)
      GIR_BuildMI, /*InsnID*/0, /*Opcode*/GIMT_Encode2(AMDGPU::V_PK_FMA_F16),
      GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/0, // DstI[vdst]
      GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/1, // src0_modifiers
      GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/0, // src0
      GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(1), /*SubOperand*/1, // src1_modifiers
      GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(1), /*SubOperand*/0, // src1
      GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(2), /*SubOperand*/1, // src2_modifiers
      GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(2), /*SubOperand*/0, // src2
      GIR_AddImm8, /*InsnID*/0, /*Imm*/0,
      GIR_AddImm8, /*InsnID*/0, /*Imm*/0,
      GIR_AddImm8, /*InsnID*/0, /*Imm*/0,
      GIR_AddImm8, /*InsnID*/0, /*Imm*/0,
      GIR_AddImm8, /*InsnID*/0, /*Imm*/0,
      GIR_ConstrainSelectedInstOperands, /*InsnID*/0,
      GIR_EraseFromParent, /*InsnID*/0,
      // GIR_Coverage, 958,
      GIR_Done,
    // Label 5597: @408407
    GIM_Reject,
    // Label 5583: @408408
    GIM_Try, /*On fail goto*//*Label 5598*/ GIMT_Encode4(408512), // Rule ID 1084 //
      GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasPackedFP32Ops),
      GIM_CheckType, /*MI*/0, /*Op*/1, /*Type*/GILLT_v2s32,
      GIM_CheckType, /*MI*/0, /*Op*/2, /*Type*/GILLT_v2s32,
      GIM_CheckType, /*MI*/0, /*Op*/3, /*Type*/GILLT_v2s32,
      GIM_CheckRegBankForClass, /*MI*/0, /*Op*/0, /*RC*/GIMT_Encode2(AMDGPU::VReg_64RegClassID),
      GIM_CheckComplexPattern, /*MI*/0, /*Op*/1, /*Renderer*/GIMT_Encode2(0), GIMT_Encode2(GICP_gi_vop3pmods),
      GIM_CheckComplexPattern, /*MI*/0, /*Op*/2, /*Renderer*/GIMT_Encode2(1), GIMT_Encode2(GICP_gi_vop3pmods),
      GIM_CheckComplexPattern, /*MI*/0, /*Op*/3, /*Renderer*/GIMT_Encode2(2), GIMT_Encode2(GICP_gi_vop3pmods),
      // (strict_fma:{ *:[v2f32] } (VOP3PMods:{ *:[v2f32] } v2f32:{ *:[v2f32] }:$src0, i32:{ *:[i32] }:$src0_modifiers), (VOP3PMods:{ *:[v2f32] } v2f32:{ *:[v2f32] }:$src1, i32:{ *:[i32] }:$src1_modifiers), (VOP3PMods:{ *:[v2f32] } v2f32:{ *:[v2f32] }:$src2, i32:{ *:[i32] }:$src2_modifiers))  =>  (V_PK_FMA_F32:{ *:[v2f32] } i32:{ *:[i32] }:$src0_modifiers, v2f32:{ *:[v2f32] }:$src0, i32:{ *:[i32] }:$src1_modifiers, v2f32:{ *:[v2f32] }:$src1, i32:{ *:[i32] }:$src2_modifiers, v2f32:{ *:[v2f32] }:$src2)
      GIR_BuildMI, /*InsnID*/0, /*Opcode*/GIMT_Encode2(AMDGPU::V_PK_FMA_F32),
      GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/0, // DstI[vdst]
      GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/1, // src0_modifiers
      GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/0, // src0
      GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(1), /*SubOperand*/1, // src1_modifiers
      GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(1), /*SubOperand*/0, // src1
      GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(2), /*SubOperand*/1, // src2_modifiers
      GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(2), /*SubOperand*/0, // src2
      GIR_AddImm8, /*InsnID*/0, /*Imm*/0,
      GIR_AddImm8, /*InsnID*/0, /*Imm*/0,
      GIR_AddImm8, /*InsnID*/0, /*Imm*/0,
      GIR_AddImm8, /*InsnID*/0, /*Imm*/0,
      GIR_AddImm8, /*InsnID*/0, /*Imm*/0,
      GIR_ConstrainSelectedInstOperands, /*InsnID*/0,
      GIR_EraseFromParent, /*InsnID*/0,
      // GIR_Coverage, 1084,
      GIR_Done,
    // Label 5598: @408512
    GIM_Reject,
    // Label 5584: @408513
    GIM_Reject,
    // Label 102: @408514
    GIM_SwitchType, /*MI*/0, /*Op*/0, /*[*/GIMT_Encode2(8), GIMT_Encode2(11), /*)*//*default:*//*Label 5602*/ GIMT_Encode4(408839),
    /*GILLT_s16*//*Label 5599*/ GIMT_Encode4(408537),
    /*GILLT_s32*//*Label 5600*/ GIMT_Encode4(408687),
    /*GILLT_s64*//*Label 5601*/ GIMT_Encode4(408763),
    // Label 5599: @408537
    GIM_Try, /*On fail goto*//*Label 5603*/ GIMT_Encode4(408686),
      GIM_CheckType, /*MI*/0, /*Op*/1, /*Type*/GILLT_s16,
      GIM_CheckType, /*MI*/0, /*Op*/2, /*Type*/GILLT_s16,
      GIM_CheckRegBankForClass, /*MI*/0, /*Op*/0, /*RC*/GIMT_Encode2(AMDGPU::VGPR_32RegClassID),
      GIM_Try, /*On fail goto*//*Label 5604*/ GIMT_Encode4(408620), // Rule ID 2111 //
        GIM_CheckFeatures, GIMT_Encode2(GIFBS_NotHasTrue16BitInsts),
        GIM_CheckComplexPattern, /*MI*/0, /*Op*/1, /*Renderer*/GIMT_Encode2(0), GIMT_Encode2(GICP_gi_vop3mods0),
        GIM_CheckComplexPattern, /*MI*/0, /*Op*/2, /*Renderer*/GIMT_Encode2(1), GIMT_Encode2(GICP_gi_vop3mods0),
        // (strict_fldexp:{ *:[f16] } (VOP3Mods0:{ *:[f16] } f16:{ *:[f16] }:$src0, i32:{ *:[i32] }:$src0_modifiers, i1:{ *:[i1] }:$clamp, i32:{ *:[i32] }:$omod), (VOP3Mods0:{ *:[i16] } f16:{ *:[f16] }:$src1, i32:{ *:[i32] }:$src1_modifiers))  =>  (V_LDEXP_F16_e64:{ *:[f16] } ?:{ *:[i32] }:$src0_modifiers, ?:{ *:[f16] }:$src0, ?:{ *:[i32] }:$src1_modifiers, ?:{ *:[f16] }:$src1, ?:{ *:[i1] }:$clamp, ?:{ *:[i32] }:$omod)
        GIR_BuildMI, /*InsnID*/0, /*Opcode*/GIMT_Encode2(AMDGPU::V_LDEXP_F16_e64),
        GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/0, // DstI[vdst]
        GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/1, // src0_modifiers
        GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/0, // src0
        GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(1), /*SubOperand*/1, // src1_modifiers
        GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(1), /*SubOperand*/0, // src1
        GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/2, // clamp
        GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/3, // omod
        GIR_ConstrainSelectedInstOperands, /*InsnID*/0,
        GIR_EraseFromParent, /*InsnID*/0,
        // GIR_Coverage, 2111,
        GIR_Done,
      // Label 5604: @408620
      GIM_Try, /*On fail goto*//*Label 5605*/ GIMT_Encode4(408685), // Rule ID 2113 //
        GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasTrue16BitInsts),
        GIM_CheckComplexPattern, /*MI*/0, /*Op*/1, /*Renderer*/GIMT_Encode2(0), GIMT_Encode2(GICP_gi_vop3mods0),
        GIM_CheckComplexPattern, /*MI*/0, /*Op*/2, /*Renderer*/GIMT_Encode2(1), GIMT_Encode2(GICP_gi_vop3mods0),
        // (strict_fldexp:{ *:[f16] } (VOP3Mods0:{ *:[f16] } f16:{ *:[f16] }:$src0, i32:{ *:[i32] }:$src0_modifiers, i1:{ *:[i1] }:$clamp, i32:{ *:[i32] }:$omod), (VOP3Mods0:{ *:[i16] } f16:{ *:[f16] }:$src1, i32:{ *:[i32] }:$src1_modifiers))  =>  (V_LDEXP_F16_t16_e64:{ *:[f16] } ?:{ *:[i32] }:$src0_modifiers, ?:{ *:[f16] }:$src0, ?:{ *:[i32] }:$src1_modifiers, ?:{ *:[f16] }:$src1, ?:{ *:[i1] }:$clamp, ?:{ *:[i32] }:$omod)
        GIR_BuildMI, /*InsnID*/0, /*Opcode*/GIMT_Encode2(AMDGPU::V_LDEXP_F16_t16_e64),
        GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/0, // DstI[vdst]
        GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/1, // src0_modifiers
        GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/0, // src0
        GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(1), /*SubOperand*/1, // src1_modifiers
        GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(1), /*SubOperand*/0, // src1
        GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/2, // clamp
        GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/3, // omod
        GIR_ConstrainSelectedInstOperands, /*InsnID*/0,
        GIR_EraseFromParent, /*InsnID*/0,
        // GIR_Coverage, 2113,
        GIR_Done,
      // Label 5605: @408685
      GIM_Reject,
    // Label 5603: @408686
    GIM_Reject,
    // Label 5600: @408687
    GIM_Try, /*On fail goto*//*Label 5606*/ GIMT_Encode4(408762), // Rule ID 761 //
      GIM_CheckType, /*MI*/0, /*Op*/1, /*Type*/GILLT_s32,
      GIM_CheckType, /*MI*/0, /*Op*/2, /*Type*/GILLT_s32,
      GIM_CheckRegBankForClass, /*MI*/0, /*Op*/0, /*RC*/GIMT_Encode2(AMDGPU::VGPR_32RegClassID),
      GIM_CheckComplexPattern, /*MI*/0, /*Op*/1, /*Renderer*/GIMT_Encode2(0), GIMT_Encode2(GICP_gi_vop3mods0),
      GIM_CheckComplexPattern, /*MI*/0, /*Op*/2, /*Renderer*/GIMT_Encode2(1), GIMT_Encode2(GICP_gi_vop3mods),
      // (strict_fldexp:{ *:[f32] } (VOP3Mods0:{ *:[f32] } f32:{ *:[f32] }:$src0, i32:{ *:[i32] }:$src0_modifiers, i1:{ *:[i1] }:$clamp, i32:{ *:[i32] }:$omod), (VOP3Mods:{ *:[i32] } i32:{ *:[i32] }:$src1, i32:{ *:[i32] }:$src1_modifiers))  =>  (V_LDEXP_F32_e64:{ *:[f32] } i32:{ *:[i32] }:$src0_modifiers, f32:{ *:[f32] }:$src0, i32:{ *:[i32] }:$src1_modifiers, i32:{ *:[i32] }:$src1, i1:{ *:[i1] }:$clamp, i32:{ *:[i32] }:$omod)
      GIR_BuildMI, /*InsnID*/0, /*Opcode*/GIMT_Encode2(AMDGPU::V_LDEXP_F32_e64),
      GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/0, // DstI[vdst]
      GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/1, // src0_modifiers
      GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/0, // src0
      GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(1), /*SubOperand*/1, // src1_modifiers
      GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(1), /*SubOperand*/0, // src1
      GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/2, // clamp
      GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/3, // omod
      GIR_ConstrainSelectedInstOperands, /*InsnID*/0,
      GIR_EraseFromParent, /*InsnID*/0,
      // GIR_Coverage, 761,
      GIR_Done,
    // Label 5606: @408762
    GIM_Reject,
    // Label 5601: @408763
    GIM_Try, /*On fail goto*//*Label 5607*/ GIMT_Encode4(408838), // Rule ID 902 //
      GIM_CheckType, /*MI*/0, /*Op*/1, /*Type*/GILLT_s64,
      GIM_CheckType, /*MI*/0, /*Op*/2, /*Type*/GILLT_s32,
      GIM_CheckRegBankForClass, /*MI*/0, /*Op*/0, /*RC*/GIMT_Encode2(AMDGPU::VReg_64RegClassID),
      GIM_CheckComplexPattern, /*MI*/0, /*Op*/1, /*Renderer*/GIMT_Encode2(0), GIMT_Encode2(GICP_gi_vop3mods0),
      GIM_CheckComplexPattern, /*MI*/0, /*Op*/2, /*Renderer*/GIMT_Encode2(1), GIMT_Encode2(GICP_gi_vop3mods),
      // (strict_fldexp:{ *:[f64] } (VOP3Mods0:{ *:[f64] } f64:{ *:[f64] }:$src0, i32:{ *:[i32] }:$src0_modifiers, i1:{ *:[i1] }:$clamp, i32:{ *:[i32] }:$omod), (VOP3Mods:{ *:[i32] } i32:{ *:[i32] }:$src1, i32:{ *:[i32] }:$src1_modifiers))  =>  (V_LDEXP_F64_e64:{ *:[f64] } i32:{ *:[i32] }:$src0_modifiers, f64:{ *:[f64] }:$src0, i32:{ *:[i32] }:$src1_modifiers, i32:{ *:[i32] }:$src1, i1:{ *:[i1] }:$clamp, i32:{ *:[i32] }:$omod)
      GIR_BuildMI, /*InsnID*/0, /*Opcode*/GIMT_Encode2(AMDGPU::V_LDEXP_F64_e64),
      GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/0, // DstI[vdst]
      GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/1, // src0_modifiers
      GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/0, // src0
      GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(1), /*SubOperand*/1, // src1_modifiers
      GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(1), /*SubOperand*/0, // src1
      GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/2, // clamp
      GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/3, // omod
      GIR_ConstrainSelectedInstOperands, /*InsnID*/0,
      GIR_EraseFromParent, /*InsnID*/0,
      // GIR_Coverage, 902,
      GIR_Done,
    // Label 5607: @408838
    GIM_Reject,
    // Label 5602: @408839
    GIM_Reject,
    // Label 103: @408840
    GIM_SwitchType, /*MI*/0, /*Op*/0, /*[*/GIMT_Encode2(9), GIMT_Encode2(11), /*)*//*default:*//*Label 5610*/ GIMT_Encode4(411337),
    /*GILLT_s32*//*Label 5608*/ GIMT_Encode4(408859),
    /*GILLT_s64*//*Label 5609*/ GIMT_Encode4(410098),
    // Label 5608: @408859
    GIM_Try, /*On fail goto*//*Label 5611*/ GIMT_Encode4(410097),
      GIM_CheckType, /*MI*/0, /*Op*/2, /*Type*/GILLT_v2s32,
      GIM_Try, /*On fail goto*//*Label 5612*/ GIMT_Encode4(408936), // Rule ID 4700 //
        GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasUnrestrictedSOffset),
        GIM_CheckMemoryAddressSpace, /*MI*/0, /*MMO*/0, /*NumAddrSpace*/3, /*AddrSpace*/1, /*AddrSpace*/4, /*AddrSpace*/6,
        GIM_CheckHasNoUse, /*MI*/0,
        GIM_CheckPointerToAny, /*MI*/0, /*Op*/1, /*SizeInBits*/0,
        GIM_CheckComplexPattern, /*MI*/0, /*Op*/1, /*Renderer*/GIMT_Encode2(0), GIMT_Encode2(GICP_gi_mubuf_addr64),
        // (AMDGPUatomic_cmp_swap:{ *:[i32] } (MUBUFAddr64:{ *:[iPTR] } v4i32:{ *:[v4i32] }:$srsrc, i64:{ *:[i64] }:$vaddr, i32:{ *:[i32] }:$soffset, i32:{ *:[i32] }:$offset), v2i32:{ *:[v2i32] }:$vdata_in)<<P:Predicate_AMDGPUatomic_cmp_swap_global_noret_32>>  =>  (BUFFER_ATOMIC_CMPSWAP_ADDR64 VReg_64:{ *:[v2i32] }:$vdata_in, VReg_64:{ *:[i64] }:$vaddr, SReg_128:{ *:[v4i32] }:$srsrc, SCSrc_b32:{ *:[i32] }:$soffset, offset:{ *:[i32] }:$offset)
        GIR_BuildMI, /*InsnID*/0, /*Opcode*/GIMT_Encode2(AMDGPU::BUFFER_ATOMIC_CMPSWAP_ADDR64),
        GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/2, // vdata_in
        GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/1, // vaddr
        GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/0, // srsrc
        GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/2, // soffset
        GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/3, // offset
        GIR_AddImm8, /*InsnID*/0, /*Imm*/0,
        GIR_MergeMemOperands, /*InsnID*/0, /*NumInsns*/1, /*MergeInsnID's*/0,
        GIR_ConstrainSelectedInstOperands, /*InsnID*/0,
        GIR_EraseFromParent, /*InsnID*/0,
        // GIR_Coverage, 4700,
        GIR_Done,
      // Label 5612: @408936
      GIM_Try, /*On fail goto*//*Label 5613*/ GIMT_Encode4(409001), // Rule ID 4704 //
        GIM_CheckMemoryAddressSpace, /*MI*/0, /*MMO*/0, /*NumAddrSpace*/3, /*AddrSpace*/1, /*AddrSpace*/4, /*AddrSpace*/6,
        GIM_CheckHasNoUse, /*MI*/0,
        GIM_CheckPointerToAny, /*MI*/0, /*Op*/1, /*SizeInBits*/0,
        GIM_CheckComplexPattern, /*MI*/0, /*Op*/1, /*Renderer*/GIMT_Encode2(0), GIMT_Encode2(GICP_gi_mubuf_addr64),
        // (AMDGPUatomic_cmp_swap:{ *:[i32] } (MUBUFAddr64:{ *:[iPTR] } v4i32:{ *:[v4i32] }:$srsrc, i64:{ *:[i64] }:$vaddr, i32:{ *:[i32] }:$soffset, i32:{ *:[i32] }:$offset), v2i32:{ *:[v2i32] }:$vdata_in)<<P:Predicate_AMDGPUatomic_cmp_swap_global_noret_32>>  =>  (BUFFER_ATOMIC_CMPSWAP_VBUFFER_ADDR64 VReg_64:{ *:[v2i32] }:$vdata_in, VReg_64:{ *:[i64] }:$vaddr, SReg_128:{ *:[v4i32] }:$srsrc, SCSrc_b32:{ *:[i32] }:$soffset, offset:{ *:[i32] }:$offset)
        GIR_BuildMI, /*InsnID*/0, /*Opcode*/GIMT_Encode2(AMDGPU::BUFFER_ATOMIC_CMPSWAP_VBUFFER_ADDR64),
        GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/2, // vdata_in
        GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/1, // vaddr
        GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/0, // srsrc
        GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/2, // soffset
        GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/3, // offset
        GIR_AddImm8, /*InsnID*/0, /*Imm*/0,
        GIR_MergeMemOperands, /*InsnID*/0, /*NumInsns*/1, /*MergeInsnID's*/0,
        GIR_ConstrainSelectedInstOperands, /*InsnID*/0,
        GIR_EraseFromParent, /*InsnID*/0,
        // GIR_Coverage, 4704,
        GIR_Done,
      // Label 5613: @409001
      GIM_Try, /*On fail goto*//*Label 5614*/ GIMT_Encode4(409122), // Rule ID 4508 //
        GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasUnrestrictedSOffset),
        GIM_CheckMemoryAddressSpace, /*MI*/0, /*MMO*/0, /*NumAddrSpace*/3, /*AddrSpace*/1, /*AddrSpace*/4, /*AddrSpace*/6,
        GIM_CheckRegBankForClass, /*MI*/0, /*Op*/0, /*RC*/GIMT_Encode2(AMDGPU::VReg_64RegClassID),
        GIM_CheckPointerToAny, /*MI*/0, /*Op*/1, /*SizeInBits*/0,
        GIM_CheckComplexPattern, /*MI*/0, /*Op*/1, /*Renderer*/GIMT_Encode2(0), GIMT_Encode2(GICP_gi_mubuf_addr64),
        // (AMDGPUatomic_cmp_swap:{ *:[i32] } (MUBUFAddr64:{ *:[iPTR] } v4i32:{ *:[v4i32] }:$srsrc, i64:{ *:[i64] }:$vaddr, i32:{ *:[i32] }:$soffset, i32:{ *:[i32] }:$offset), v2i32:{ *:[v2i32] }:$vdata_in)<<P:Predicate_AMDGPUatomic_cmp_swap_global_32>>  =>  (EXTRACT_SUBREG:{ *:[i32] } (COPY_TO_REGCLASS:{ *:[i32] } (BUFFER_ATOMIC_CMPSWAP_ADDR64_RTN:{ *:[i64] } VReg_64:{ *:[v2i32] }:$vdata_in, VReg_64:{ *:[i64] }:$vaddr, SReg_128:{ *:[v4i32] }:$srsrc, SCSrc_b32:{ *:[i32] }:$soffset, offset:{ *:[i32] }:$offset), VReg_64:{ *:[i32] }), sub0:{ *:[i32] })
        GIR_MakeTempReg, /*TempRegID*/0, /*TypeID*/GILLT_s32,
        GIR_MakeTempReg, /*TempRegID*/1, /*TypeID*/GILLT_s64,
        GIR_BuildMI, /*InsnID*/2, /*Opcode*/GIMT_Encode2(AMDGPU::BUFFER_ATOMIC_CMPSWAP_ADDR64_RTN),
        GIR_AddTempRegister, /*InsnID*/2, /*TempRegID*/1, /*TempRegFlags*/GIMT_Encode2(RegState::Define),
        GIR_Copy, /*NewInsnID*/2, /*OldInsnID*/0, /*OpIdx*/2, // vdata_in
        GIR_ComplexSubOperandRenderer, /*InsnID*/2, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/1, // vaddr
        GIR_ComplexSubOperandRenderer, /*InsnID*/2, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/0, // srsrc
        GIR_ComplexSubOperandRenderer, /*InsnID*/2, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/2, // soffset
        GIR_ComplexSubOperandRenderer, /*InsnID*/2, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/3, // offset
        GIR_AddImm8, /*InsnID*/2, /*Imm*/1,
        GIR_MergeMemOperands, /*InsnID*/2, /*NumInsns*/1, /*MergeInsnID's*/0,
        GIR_ConstrainSelectedInstOperands, /*InsnID*/2,
        GIR_BuildMI, /*InsnID*/1, /*Opcode*/GIMT_Encode2(TargetOpcode::COPY),
        GIR_AddTempRegister, /*InsnID*/1, /*TempRegID*/0, /*TempRegFlags*/GIMT_Encode2(RegState::Define),
        GIR_AddSimpleTempRegister, /*InsnID*/1, /*TempRegID*/1,
        GIR_ConstrainSelectedInstOperands, /*InsnID*/1,
        GIR_BuildMI, /*InsnID*/0, /*Opcode*/GIMT_Encode2(TargetOpcode::COPY),
        GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/0, // DstI[dst]
        GIR_AddTempSubRegister, /*InsnID*/0, /*TempRegID*/0, /*TempRegFlags*/GIMT_Encode2(0), GIMT_Encode2(AMDGPU::sub0),
        GIR_ConstrainOperandRC, /*InsnID*/0, /*Op*/0, GIMT_Encode2(AMDGPU::VGPR_32RegClassID),
        GIR_ConstrainOperandRC, /*InsnID*/0, /*Op*/1, GIMT_Encode2(AMDGPU::VReg_64RegClassID),
        GIR_EraseFromParent, /*InsnID*/0,
        // GIR_Coverage, 4508,
        GIR_Done,
      // Label 5614: @409122
      GIM_Try, /*On fail goto*//*Label 5615*/ GIMT_Encode4(409240), // Rule ID 4702 //
        GIM_CheckMemoryAddressSpace, /*MI*/0, /*MMO*/0, /*NumAddrSpace*/3, /*AddrSpace*/1, /*AddrSpace*/4, /*AddrSpace*/6,
        GIM_CheckRegBankForClass, /*MI*/0, /*Op*/0, /*RC*/GIMT_Encode2(AMDGPU::VReg_64RegClassID),
        GIM_CheckPointerToAny, /*MI*/0, /*Op*/1, /*SizeInBits*/0,
        GIM_CheckComplexPattern, /*MI*/0, /*Op*/1, /*Renderer*/GIMT_Encode2(0), GIMT_Encode2(GICP_gi_mubuf_addr64),
        // (AMDGPUatomic_cmp_swap:{ *:[i32] } (MUBUFAddr64:{ *:[iPTR] } v4i32:{ *:[v4i32] }:$srsrc, i64:{ *:[i64] }:$vaddr, i32:{ *:[i32] }:$soffset, i32:{ *:[i32] }:$offset), v2i32:{ *:[v2i32] }:$vdata_in)<<P:Predicate_AMDGPUatomic_cmp_swap_global_32>>  =>  (EXTRACT_SUBREG:{ *:[i32] } (COPY_TO_REGCLASS:{ *:[i32] } (BUFFER_ATOMIC_CMPSWAP_VBUFFER_ADDR64_RTN:{ *:[i64] } VReg_64:{ *:[v2i32] }:$vdata_in, VReg_64:{ *:[i64] }:$vaddr, SReg_128:{ *:[v4i32] }:$srsrc, SCSrc_b32:{ *:[i32] }:$soffset, offset:{ *:[i32] }:$offset), VReg_64:{ *:[i32] }), sub0:{ *:[i32] })
        GIR_MakeTempReg, /*TempRegID*/0, /*TypeID*/GILLT_s32,
        GIR_MakeTempReg, /*TempRegID*/1, /*TypeID*/GILLT_s64,
        GIR_BuildMI, /*InsnID*/2, /*Opcode*/GIMT_Encode2(AMDGPU::BUFFER_ATOMIC_CMPSWAP_VBUFFER_ADDR64_RTN),
        GIR_AddTempRegister, /*InsnID*/2, /*TempRegID*/1, /*TempRegFlags*/GIMT_Encode2(RegState::Define),
        GIR_Copy, /*NewInsnID*/2, /*OldInsnID*/0, /*OpIdx*/2, // vdata_in
        GIR_ComplexSubOperandRenderer, /*InsnID*/2, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/1, // vaddr
        GIR_ComplexSubOperandRenderer, /*InsnID*/2, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/0, // srsrc
        GIR_ComplexSubOperandRenderer, /*InsnID*/2, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/2, // soffset
        GIR_ComplexSubOperandRenderer, /*InsnID*/2, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/3, // offset
        GIR_AddImm8, /*InsnID*/2, /*Imm*/1,
        GIR_MergeMemOperands, /*InsnID*/2, /*NumInsns*/1, /*MergeInsnID's*/0,
        GIR_ConstrainSelectedInstOperands, /*InsnID*/2,
        GIR_BuildMI, /*InsnID*/1, /*Opcode*/GIMT_Encode2(TargetOpcode::COPY),
        GIR_AddTempRegister, /*InsnID*/1, /*TempRegID*/0, /*TempRegFlags*/GIMT_Encode2(RegState::Define),
        GIR_AddSimpleTempRegister, /*InsnID*/1, /*TempRegID*/1,
        GIR_ConstrainSelectedInstOperands, /*InsnID*/1,
        GIR_BuildMI, /*InsnID*/0, /*Opcode*/GIMT_Encode2(TargetOpcode::COPY),
        GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/0, // DstI[dst]
        GIR_AddTempSubRegister, /*InsnID*/0, /*TempRegID*/0, /*TempRegFlags*/GIMT_Encode2(0), GIMT_Encode2(AMDGPU::sub0),
        GIR_ConstrainOperandRC, /*InsnID*/0, /*Op*/0, GIMT_Encode2(AMDGPU::VGPR_32RegClassID),
        GIR_ConstrainOperandRC, /*InsnID*/0, /*Op*/1, GIMT_Encode2(AMDGPU::VReg_64RegClassID),
        GIR_EraseFromParent, /*InsnID*/0,
        // GIR_Coverage, 4702,
        GIR_Done,
      // Label 5615: @409240
      GIM_Try, /*On fail goto*//*Label 5616*/ GIMT_Encode4(409303), // Rule ID 4699 //
        GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasUnrestrictedSOffset),
        GIM_CheckMemoryAddressSpace, /*MI*/0, /*MMO*/0, /*NumAddrSpace*/3, /*AddrSpace*/1, /*AddrSpace*/4, /*AddrSpace*/6,
        GIM_CheckHasNoUse, /*MI*/0,
        GIM_CheckPointerToAny, /*MI*/0, /*Op*/1, /*SizeInBits*/0,
        GIM_CheckComplexPattern, /*MI*/0, /*Op*/1, /*Renderer*/GIMT_Encode2(0), GIMT_Encode2(GICP_gi_mubuf_offset),
        // (AMDGPUatomic_cmp_swap:{ *:[i32] } (MUBUFOffset:{ *:[iPTR] } v4i32:{ *:[v4i32] }:$srsrc, i32:{ *:[i32] }:$soffset, i32:{ *:[i32] }:$offset), v2i32:{ *:[v2i32] }:$vdata_in)<<P:Predicate_AMDGPUatomic_cmp_swap_global_noret_32>>  =>  (BUFFER_ATOMIC_CMPSWAP_OFFSET VReg_64:{ *:[v2i32] }:$vdata_in, SReg_128:{ *:[v4i32] }:$srsrc, SCSrc_b32:{ *:[i32] }:$soffset, offset:{ *:[i32] }:$offset)
        GIR_BuildMI, /*InsnID*/0, /*Opcode*/GIMT_Encode2(AMDGPU::BUFFER_ATOMIC_CMPSWAP_OFFSET),
        GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/2, // vdata_in
        GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/0, // srsrc
        GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/1, // soffset
        GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/2, // offset
        GIR_AddImm8, /*InsnID*/0, /*Imm*/0,
        GIR_MergeMemOperands, /*InsnID*/0, /*NumInsns*/1, /*MergeInsnID's*/0,
        GIR_ConstrainSelectedInstOperands, /*InsnID*/0,
        GIR_EraseFromParent, /*InsnID*/0,
        // GIR_Coverage, 4699,
        GIR_Done,
      // Label 5616: @409303
      GIM_Try, /*On fail goto*//*Label 5617*/ GIMT_Encode4(409363), // Rule ID 4703 //
        GIM_CheckMemoryAddressSpace, /*MI*/0, /*MMO*/0, /*NumAddrSpace*/3, /*AddrSpace*/1, /*AddrSpace*/4, /*AddrSpace*/6,
        GIM_CheckHasNoUse, /*MI*/0,
        GIM_CheckPointerToAny, /*MI*/0, /*Op*/1, /*SizeInBits*/0,
        GIM_CheckComplexPattern, /*MI*/0, /*Op*/1, /*Renderer*/GIMT_Encode2(0), GIMT_Encode2(GICP_gi_mubuf_offset),
        // (AMDGPUatomic_cmp_swap:{ *:[i32] } (MUBUFOffset:{ *:[iPTR] } v4i32:{ *:[v4i32] }:$srsrc, i32:{ *:[i32] }:$soffset, i32:{ *:[i32] }:$offset), v2i32:{ *:[v2i32] }:$vdata_in)<<P:Predicate_AMDGPUatomic_cmp_swap_global_noret_32>>  =>  (BUFFER_ATOMIC_CMPSWAP_VBUFFER_OFFSET VReg_64:{ *:[v2i32] }:$vdata_in, SReg_128:{ *:[v4i32] }:$srsrc, SCSrc_b32:{ *:[i32] }:$soffset, offset:{ *:[i32] }:$offset)
        GIR_BuildMI, /*InsnID*/0, /*Opcode*/GIMT_Encode2(AMDGPU::BUFFER_ATOMIC_CMPSWAP_VBUFFER_OFFSET),
        GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/2, // vdata_in
        GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/0, // srsrc
        GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/1, // soffset
        GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/2, // offset
        GIR_AddImm8, /*InsnID*/0, /*Imm*/0,
        GIR_MergeMemOperands, /*InsnID*/0, /*NumInsns*/1, /*MergeInsnID's*/0,
        GIR_ConstrainSelectedInstOperands, /*InsnID*/0,
        GIR_EraseFromParent, /*InsnID*/0,
        // GIR_Coverage, 4703,
        GIR_Done,
      // Label 5617: @409363
      GIM_Try, /*On fail goto*//*Label 5618*/ GIMT_Encode4(409479), // Rule ID 4507 //
        GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasUnrestrictedSOffset),
        GIM_CheckMemoryAddressSpace, /*MI*/0, /*MMO*/0, /*NumAddrSpace*/3, /*AddrSpace*/1, /*AddrSpace*/4, /*AddrSpace*/6,
        GIM_CheckRegBankForClass, /*MI*/0, /*Op*/0, /*RC*/GIMT_Encode2(AMDGPU::VReg_64RegClassID),
        GIM_CheckPointerToAny, /*MI*/0, /*Op*/1, /*SizeInBits*/0,
        GIM_CheckComplexPattern, /*MI*/0, /*Op*/1, /*Renderer*/GIMT_Encode2(0), GIMT_Encode2(GICP_gi_mubuf_offset),
        // (AMDGPUatomic_cmp_swap:{ *:[i32] } (MUBUFOffset:{ *:[iPTR] } v4i32:{ *:[v4i32] }:$srsrc, i32:{ *:[i32] }:$soffset, i32:{ *:[i32] }:$offset), v2i32:{ *:[v2i32] }:$vdata_in)<<P:Predicate_AMDGPUatomic_cmp_swap_global_32>>  =>  (EXTRACT_SUBREG:{ *:[i32] } (COPY_TO_REGCLASS:{ *:[i32] } (BUFFER_ATOMIC_CMPSWAP_OFFSET_RTN:{ *:[i64] } VReg_64:{ *:[v2i32] }:$vdata_in, SReg_128:{ *:[v4i32] }:$srsrc, SCSrc_b32:{ *:[i32] }:$soffset, offset:{ *:[i32] }:$offset), VReg_64:{ *:[i32] }), sub0:{ *:[i32] })
        GIR_MakeTempReg, /*TempRegID*/0, /*TypeID*/GILLT_s32,
        GIR_MakeTempReg, /*TempRegID*/1, /*TypeID*/GILLT_s64,
        GIR_BuildMI, /*InsnID*/2, /*Opcode*/GIMT_Encode2(AMDGPU::BUFFER_ATOMIC_CMPSWAP_OFFSET_RTN),
        GIR_AddTempRegister, /*InsnID*/2, /*TempRegID*/1, /*TempRegFlags*/GIMT_Encode2(RegState::Define),
        GIR_Copy, /*NewInsnID*/2, /*OldInsnID*/0, /*OpIdx*/2, // vdata_in
        GIR_ComplexSubOperandRenderer, /*InsnID*/2, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/0, // srsrc
        GIR_ComplexSubOperandRenderer, /*InsnID*/2, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/1, // soffset
        GIR_ComplexSubOperandRenderer, /*InsnID*/2, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/2, // offset
        GIR_AddImm8, /*InsnID*/2, /*Imm*/1,
        GIR_MergeMemOperands, /*InsnID*/2, /*NumInsns*/1, /*MergeInsnID's*/0,
        GIR_ConstrainSelectedInstOperands, /*InsnID*/2,
        GIR_BuildMI, /*InsnID*/1, /*Opcode*/GIMT_Encode2(TargetOpcode::COPY),
        GIR_AddTempRegister, /*InsnID*/1, /*TempRegID*/0, /*TempRegFlags*/GIMT_Encode2(RegState::Define),
        GIR_AddSimpleTempRegister, /*InsnID*/1, /*TempRegID*/1,
        GIR_ConstrainSelectedInstOperands, /*InsnID*/1,
        GIR_BuildMI, /*InsnID*/0, /*Opcode*/GIMT_Encode2(TargetOpcode::COPY),
        GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/0, // DstI[dst]
        GIR_AddTempSubRegister, /*InsnID*/0, /*TempRegID*/0, /*TempRegFlags*/GIMT_Encode2(0), GIMT_Encode2(AMDGPU::sub0),
        GIR_ConstrainOperandRC, /*InsnID*/0, /*Op*/0, GIMT_Encode2(AMDGPU::VGPR_32RegClassID),
        GIR_ConstrainOperandRC, /*InsnID*/0, /*Op*/1, GIMT_Encode2(AMDGPU::VReg_64RegClassID),
        GIR_EraseFromParent, /*InsnID*/0,
        // GIR_Coverage, 4507,
        GIR_Done,
      // Label 5618: @409479
      GIM_Try, /*On fail goto*//*Label 5619*/ GIMT_Encode4(409592), // Rule ID 4701 //
        GIM_CheckMemoryAddressSpace, /*MI*/0, /*MMO*/0, /*NumAddrSpace*/3, /*AddrSpace*/1, /*AddrSpace*/4, /*AddrSpace*/6,
        GIM_CheckRegBankForClass, /*MI*/0, /*Op*/0, /*RC*/GIMT_Encode2(AMDGPU::VReg_64RegClassID),
        GIM_CheckPointerToAny, /*MI*/0, /*Op*/1, /*SizeInBits*/0,
        GIM_CheckComplexPattern, /*MI*/0, /*Op*/1, /*Renderer*/GIMT_Encode2(0), GIMT_Encode2(GICP_gi_mubuf_offset),
        // (AMDGPUatomic_cmp_swap:{ *:[i32] } (MUBUFOffset:{ *:[iPTR] } v4i32:{ *:[v4i32] }:$srsrc, i32:{ *:[i32] }:$soffset, i32:{ *:[i32] }:$offset), v2i32:{ *:[v2i32] }:$vdata_in)<<P:Predicate_AMDGPUatomic_cmp_swap_global_32>>  =>  (EXTRACT_SUBREG:{ *:[i32] } (COPY_TO_REGCLASS:{ *:[i32] } (BUFFER_ATOMIC_CMPSWAP_VBUFFER_OFFSET_RTN:{ *:[i64] } VReg_64:{ *:[v2i32] }:$vdata_in, SReg_128:{ *:[v4i32] }:$srsrc, SCSrc_b32:{ *:[i32] }:$soffset, offset:{ *:[i32] }:$offset), VReg_64:{ *:[i32] }), sub0:{ *:[i32] })
        GIR_MakeTempReg, /*TempRegID*/0, /*TypeID*/GILLT_s32,
        GIR_MakeTempReg, /*TempRegID*/1, /*TypeID*/GILLT_s64,
        GIR_BuildMI, /*InsnID*/2, /*Opcode*/GIMT_Encode2(AMDGPU::BUFFER_ATOMIC_CMPSWAP_VBUFFER_OFFSET_RTN),
        GIR_AddTempRegister, /*InsnID*/2, /*TempRegID*/1, /*TempRegFlags*/GIMT_Encode2(RegState::Define),
        GIR_Copy, /*NewInsnID*/2, /*OldInsnID*/0, /*OpIdx*/2, // vdata_in
        GIR_ComplexSubOperandRenderer, /*InsnID*/2, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/0, // srsrc
        GIR_ComplexSubOperandRenderer, /*InsnID*/2, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/1, // soffset
        GIR_ComplexSubOperandRenderer, /*InsnID*/2, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/2, // offset
        GIR_AddImm8, /*InsnID*/2, /*Imm*/1,
        GIR_MergeMemOperands, /*InsnID*/2, /*NumInsns*/1, /*MergeInsnID's*/0,
        GIR_ConstrainSelectedInstOperands, /*InsnID*/2,
        GIR_BuildMI, /*InsnID*/1, /*Opcode*/GIMT_Encode2(TargetOpcode::COPY),
        GIR_AddTempRegister, /*InsnID*/1, /*TempRegID*/0, /*TempRegFlags*/GIMT_Encode2(RegState::Define),
        GIR_AddSimpleTempRegister, /*InsnID*/1, /*TempRegID*/1,
        GIR_ConstrainSelectedInstOperands, /*InsnID*/1,
        GIR_BuildMI, /*InsnID*/0, /*Opcode*/GIMT_Encode2(TargetOpcode::COPY),
        GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/0, // DstI[dst]
        GIR_AddTempSubRegister, /*InsnID*/0, /*TempRegID*/0, /*TempRegFlags*/GIMT_Encode2(0), GIMT_Encode2(AMDGPU::sub0),
        GIR_ConstrainOperandRC, /*InsnID*/0, /*Op*/0, GIMT_Encode2(AMDGPU::VGPR_32RegClassID),
        GIR_ConstrainOperandRC, /*InsnID*/0, /*Op*/1, GIMT_Encode2(AMDGPU::VReg_64RegClassID),
        GIR_EraseFromParent, /*InsnID*/0,
        // GIR_Coverage, 4701,
        GIR_Done,
      // Label 5619: @409592
      GIM_Try, /*On fail goto*//*Label 5620*/ GIMT_Encode4(409655), // Rule ID 3191 //
        GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasFlatGlobalInsts),
        GIM_CheckMemoryAddressSpace, /*MI*/0, /*MMO*/0, /*NumAddrSpace*/3, /*AddrSpace*/1, /*AddrSpace*/4, /*AddrSpace*/6,
        GIM_CheckHasNoUse, /*MI*/0,
        GIM_CheckPointerToAny, /*MI*/0, /*Op*/1, /*SizeInBits*/0,
        GIM_CheckComplexPattern, /*MI*/0, /*Op*/1, /*Renderer*/GIMT_Encode2(0), GIMT_Encode2(GICP_gi_global_saddr),
        // (AMDGPUatomic_cmp_swap:{ *:[i32] } (GlobalSAddr:{ *:[iPTR] } SReg_64:{ *:[i64] }:$saddr, VGPR_32:{ *:[i32] }:$voffset, i32:{ *:[i32] }:$offset), v2i32:{ *:[v2i32] }:$data)<<P:Predicate_AMDGPUatomic_cmp_swap_global_noret_32>>  =>  (GLOBAL_ATOMIC_CMPSWAP_SADDR ?:{ *:[i32] }:$voffset, anonymous_15036:{ *:[v2i32] }:$data, ?:{ *:[i64] }:$saddr, ?:{ *:[i32] }:$offset)
        GIR_BuildMI, /*InsnID*/0, /*Opcode*/GIMT_Encode2(AMDGPU::GLOBAL_ATOMIC_CMPSWAP_SADDR),
        GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/1, // voffset
        GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/2, // data
        GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/0, // saddr
        GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/2, // offset
        GIR_AddImm8, /*InsnID*/0, /*Imm*/0,
        GIR_MergeMemOperands, /*InsnID*/0, /*NumInsns*/1, /*MergeInsnID's*/0,
        GIR_ConstrainSelectedInstOperands, /*InsnID*/0,
        GIR_EraseFromParent, /*InsnID*/0,
        // GIR_Coverage, 3191,
        GIR_Done,
      // Label 5620: @409655
      GIM_Try, /*On fail goto*//*Label 5621*/ GIMT_Encode4(409725), // Rule ID 3193 //
        GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasFlatGlobalInsts),
        GIM_CheckMemoryAddressSpace, /*MI*/0, /*MMO*/0, /*NumAddrSpace*/3, /*AddrSpace*/1, /*AddrSpace*/4, /*AddrSpace*/6,
        GIM_CheckRegBankForClass, /*MI*/0, /*Op*/0, /*RC*/GIMT_Encode2(AMDGPU::AV_32RegClassID),
        GIM_CheckPointerToAny, /*MI*/0, /*Op*/1, /*SizeInBits*/0,
        GIM_CheckComplexPattern, /*MI*/0, /*Op*/1, /*Renderer*/GIMT_Encode2(0), GIMT_Encode2(GICP_gi_global_saddr),
        // (AMDGPUatomic_cmp_swap:{ *:[i32] } (GlobalSAddr:{ *:[iPTR] } SReg_64:{ *:[i64] }:$saddr, VGPR_32:{ *:[i32] }:$voffset, i32:{ *:[i32] }:$offset), v2i32:{ *:[v2i32] }:$data)<<P:Predicate_AMDGPUatomic_cmp_swap_global_32>>  =>  (GLOBAL_ATOMIC_CMPSWAP_SADDR_RTN:{ *:[i32] } ?:{ *:[i32] }:$voffset, anonymous_15036:{ *:[v2i32] }:$data, ?:{ *:[i64] }:$saddr, ?:{ *:[i32] }:$offset)
        GIR_BuildMI, /*InsnID*/0, /*Opcode*/GIMT_Encode2(AMDGPU::GLOBAL_ATOMIC_CMPSWAP_SADDR_RTN),
        GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/0, // DstI[vdst]
        GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/1, // voffset
        GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/2, // data
        GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/0, // saddr
        GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/2, // offset
        GIR_AddImm8, /*InsnID*/0, /*Imm*/1,
        GIR_MergeMemOperands, /*InsnID*/0, /*NumInsns*/1, /*MergeInsnID's*/0,
        GIR_ConstrainSelectedInstOperands, /*InsnID*/0,
        GIR_EraseFromParent, /*InsnID*/0,
        // GIR_Coverage, 3193,
        GIR_Done,
      // Label 5621: @409725
      GIM_Try, /*On fail goto*//*Label 5622*/ GIMT_Encode4(409783), // Rule ID 3190 //
        GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasFlatGlobalInsts),
        GIM_CheckMemoryAddressSpace, /*MI*/0, /*MMO*/0, /*NumAddrSpace*/3, /*AddrSpace*/1, /*AddrSpace*/4, /*AddrSpace*/6,
        GIM_CheckHasNoUse, /*MI*/0,
        GIM_CheckPointerToAny, /*MI*/0, /*Op*/1, /*SizeInBits*/0,
        GIM_CheckComplexPattern, /*MI*/0, /*Op*/1, /*Renderer*/GIMT_Encode2(0), GIMT_Encode2(GICP_gi_global_offset),
        // (AMDGPUatomic_cmp_swap:{ *:[i32] } (GlobalOffset:{ *:[iPTR] } i64:{ *:[i64] }:$vaddr, i32:{ *:[i32] }:$offset), v2i32:{ *:[v2i32] }:$data)<<P:Predicate_AMDGPUatomic_cmp_swap_global_noret_32>>  =>  (GLOBAL_ATOMIC_CMPSWAP VReg_64:{ *:[i64] }:$vaddr, anonymous_15036:{ *:[v2i32] }:$data, ?:{ *:[i32] }:$offset)
        GIR_BuildMI, /*InsnID*/0, /*Opcode*/GIMT_Encode2(AMDGPU::GLOBAL_ATOMIC_CMPSWAP),
        GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/0, // vaddr
        GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/2, // data
        GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/1, // offset
        GIR_AddImm8, /*InsnID*/0, /*Imm*/0,
        GIR_MergeMemOperands, /*InsnID*/0, /*NumInsns*/1, /*MergeInsnID's*/0,
        GIR_ConstrainSelectedInstOperands, /*InsnID*/0,
        GIR_EraseFromParent, /*InsnID*/0,
        // GIR_Coverage, 3190,
        GIR_Done,
      // Label 5622: @409783
      GIM_Try, /*On fail goto*//*Label 5623*/ GIMT_Encode4(409848), // Rule ID 3192 //
        GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasFlatGlobalInsts),
        GIM_CheckMemoryAddressSpace, /*MI*/0, /*MMO*/0, /*NumAddrSpace*/3, /*AddrSpace*/1, /*AddrSpace*/4, /*AddrSpace*/6,
        GIM_CheckRegBankForClass, /*MI*/0, /*Op*/0, /*RC*/GIMT_Encode2(AMDGPU::AV_32RegClassID),
        GIM_CheckPointerToAny, /*MI*/0, /*Op*/1, /*SizeInBits*/0,
        GIM_CheckComplexPattern, /*MI*/0, /*Op*/1, /*Renderer*/GIMT_Encode2(0), GIMT_Encode2(GICP_gi_global_offset),
        // (AMDGPUatomic_cmp_swap:{ *:[i32] } (GlobalOffset:{ *:[iPTR] } i64:{ *:[i64] }:$vaddr, i32:{ *:[i32] }:$offset), v2i32:{ *:[v2i32] }:$data)<<P:Predicate_AMDGPUatomic_cmp_swap_global_32>>  =>  (GLOBAL_ATOMIC_CMPSWAP_RTN:{ *:[i32] } VReg_64:{ *:[i64] }:$vaddr, anonymous_15036:{ *:[v2i32] }:$data, ?:{ *:[i32] }:$offset)
        GIR_BuildMI, /*InsnID*/0, /*Opcode*/GIMT_Encode2(AMDGPU::GLOBAL_ATOMIC_CMPSWAP_RTN),
        GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/0, // DstI[vdst]
        GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/0, // vaddr
        GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/2, // data
        GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/1, // offset
        GIR_AddImm8, /*InsnID*/0, /*Imm*/1,
        GIR_MergeMemOperands, /*InsnID*/0, /*NumInsns*/1, /*MergeInsnID's*/0,
        GIR_ConstrainSelectedInstOperands, /*InsnID*/0,
        GIR_EraseFromParent, /*InsnID*/0,
        // GIR_Coverage, 3192,
        GIR_Done,
      // Label 5623: @409848
      GIM_Try, /*On fail goto*//*Label 5624*/ GIMT_Encode4(409907), // Rule ID 2850 //
        GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasFlatAddressSpace),
        GIM_CheckMemoryAddressSpace, /*MI*/0, /*MMO*/0, /*NumAddrSpace*/4, /*AddrSpace*/0, /*AddrSpace*/1, /*AddrSpace*/4, /*AddrSpace*/6,
        GIM_CheckHasNoUse, /*MI*/0,
        GIM_CheckPointerToAny, /*MI*/0, /*Op*/1, /*SizeInBits*/0,
        GIM_CheckComplexPattern, /*MI*/0, /*Op*/1, /*Renderer*/GIMT_Encode2(0), GIMT_Encode2(GICP_gi_flat_offset),
        // (AMDGPUatomic_cmp_swap:{ *:[i32] } (FlatOffset:{ *:[iPTR] } i64:{ *:[i64] }:$vaddr, i32:{ *:[i32] }:$offset), v2i32:{ *:[v2i32] }:$data)<<P:Predicate_AMDGPUatomic_cmp_swap_flat_noret_32>>  =>  (FLAT_ATOMIC_CMPSWAP VReg_64:{ *:[i64] }:$vaddr, anonymous_15036:{ *:[v2i32] }:$data, ?:{ *:[i32] }:$offset)
        GIR_BuildMI, /*InsnID*/0, /*Opcode*/GIMT_Encode2(AMDGPU::FLAT_ATOMIC_CMPSWAP),
        GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/0, // vaddr
        GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/2, // data
        GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/1, // offset
        GIR_AddImm8, /*InsnID*/0, /*Imm*/0,
        GIR_MergeMemOperands, /*InsnID*/0, /*NumInsns*/1, /*MergeInsnID's*/0,
        GIR_ConstrainSelectedInstOperands, /*InsnID*/0,
        GIR_EraseFromParent, /*InsnID*/0,
        // GIR_Coverage, 2850,
        GIR_Done,
      // Label 5624: @409907
      GIM_Try, /*On fail goto*//*Label 5625*/ GIMT_Encode4(409965), // Rule ID 2902 //
        GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasFlatAddressSpace),
        GIM_CheckMemoryAddressSpace, /*MI*/0, /*MMO*/0, /*NumAddrSpace*/3, /*AddrSpace*/1, /*AddrSpace*/4, /*AddrSpace*/6,
        GIM_CheckHasNoUse, /*MI*/0,
        GIM_CheckPointerToAny, /*MI*/0, /*Op*/1, /*SizeInBits*/0,
        GIM_CheckComplexPattern, /*MI*/0, /*Op*/1, /*Renderer*/GIMT_Encode2(0), GIMT_Encode2(GICP_gi_flat_offset),
        // (AMDGPUatomic_cmp_swap:{ *:[i32] } (FlatOffset:{ *:[iPTR] } i64:{ *:[i64] }:$vaddr, i32:{ *:[i32] }:$offset), v2i32:{ *:[v2i32] }:$data)<<P:Predicate_AMDGPUatomic_cmp_swap_global_noret_32>>  =>  (FLAT_ATOMIC_CMPSWAP VReg_64:{ *:[i64] }:$vaddr, anonymous_15036:{ *:[v2i32] }:$data, ?:{ *:[i32] }:$offset)
        GIR_BuildMI, /*InsnID*/0, /*Opcode*/GIMT_Encode2(AMDGPU::FLAT_ATOMIC_CMPSWAP),
        GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/0, // vaddr
        GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/2, // data
        GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/1, // offset
        GIR_AddImm8, /*InsnID*/0, /*Imm*/0,
        GIR_MergeMemOperands, /*InsnID*/0, /*NumInsns*/1, /*MergeInsnID's*/0,
        GIR_ConstrainSelectedInstOperands, /*InsnID*/0,
        GIR_EraseFromParent, /*InsnID*/0,
        // GIR_Coverage, 2902,
        GIR_Done,
      // Label 5625: @409965
      GIM_Try, /*On fail goto*//*Label 5626*/ GIMT_Encode4(410031), // Rule ID 2849 //
        GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasFlatAddressSpace),
        GIM_CheckMemoryAddressSpace, /*MI*/0, /*MMO*/0, /*NumAddrSpace*/4, /*AddrSpace*/0, /*AddrSpace*/1, /*AddrSpace*/4, /*AddrSpace*/6,
        GIM_CheckRegBankForClass, /*MI*/0, /*Op*/0, /*RC*/GIMT_Encode2(AMDGPU::AV_32RegClassID),
        GIM_CheckPointerToAny, /*MI*/0, /*Op*/1, /*SizeInBits*/0,
        GIM_CheckComplexPattern, /*MI*/0, /*Op*/1, /*Renderer*/GIMT_Encode2(0), GIMT_Encode2(GICP_gi_flat_offset),
        // (AMDGPUatomic_cmp_swap:{ *:[i32] } (FlatOffset:{ *:[iPTR] } i64:{ *:[i64] }:$vaddr, i32:{ *:[i32] }:$offset), v2i32:{ *:[v2i32] }:$data)<<P:Predicate_AMDGPUatomic_cmp_swap_flat_32>>  =>  (FLAT_ATOMIC_CMPSWAP_RTN:{ *:[i32] } VReg_64:{ *:[i64] }:$vaddr, anonymous_15036:{ *:[v2i32] }:$data, ?:{ *:[i32] }:$offset)
        GIR_BuildMI, /*InsnID*/0, /*Opcode*/GIMT_Encode2(AMDGPU::FLAT_ATOMIC_CMPSWAP_RTN),
        GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/0, // DstI[vdst]
        GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/0, // vaddr
        GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/2, // data
        GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/1, // offset
        GIR_AddImm8, /*InsnID*/0, /*Imm*/1,
        GIR_MergeMemOperands, /*InsnID*/0, /*NumInsns*/1, /*MergeInsnID's*/0,
        GIR_ConstrainSelectedInstOperands, /*InsnID*/0,
        GIR_EraseFromParent, /*InsnID*/0,
        // GIR_Coverage, 2849,
        GIR_Done,
      // Label 5626: @410031
      GIM_Try, /*On fail goto*//*Label 5627*/ GIMT_Encode4(410096), // Rule ID 2901 //
        GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasFlatAddressSpace),
        GIM_CheckMemoryAddressSpace, /*MI*/0, /*MMO*/0, /*NumAddrSpace*/3, /*AddrSpace*/1, /*AddrSpace*/4, /*AddrSpace*/6,
        GIM_CheckRegBankForClass, /*MI*/0, /*Op*/0, /*RC*/GIMT_Encode2(AMDGPU::AV_32RegClassID),
        GIM_CheckPointerToAny, /*MI*/0, /*Op*/1, /*SizeInBits*/0,
        GIM_CheckComplexPattern, /*MI*/0, /*Op*/1, /*Renderer*/GIMT_Encode2(0), GIMT_Encode2(GICP_gi_flat_offset),
        // (AMDGPUatomic_cmp_swap:{ *:[i32] } (FlatOffset:{ *:[iPTR] } i64:{ *:[i64] }:$vaddr, i32:{ *:[i32] }:$offset), v2i32:{ *:[v2i32] }:$data)<<P:Predicate_AMDGPUatomic_cmp_swap_global_32>>  =>  (FLAT_ATOMIC_CMPSWAP_RTN:{ *:[i32] } VReg_64:{ *:[i64] }:$vaddr, anonymous_15036:{ *:[v2i32] }:$data, ?:{ *:[i32] }:$offset)
        GIR_BuildMI, /*InsnID*/0, /*Opcode*/GIMT_Encode2(AMDGPU::FLAT_ATOMIC_CMPSWAP_RTN),
        GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/0, // DstI[vdst]
        GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/0, // vaddr
        GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/2, // data
        GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/1, // offset
        GIR_AddImm8, /*InsnID*/0, /*Imm*/1,
        GIR_MergeMemOperands, /*InsnID*/0, /*NumInsns*/1, /*MergeInsnID's*/0,
        GIR_ConstrainSelectedInstOperands, /*InsnID*/0,
        GIR_EraseFromParent, /*InsnID*/0,
        // GIR_Coverage, 2901,
        GIR_Done,
      // Label 5627: @410096
      GIM_Reject,
    // Label 5611: @410097
    GIM_Reject,
    // Label 5609: @410098
    GIM_Try, /*On fail goto*//*Label 5628*/ GIMT_Encode4(411336),
      GIM_CheckType, /*MI*/0, /*Op*/2, /*Type*/GILLT_v2s64,
      GIM_Try, /*On fail goto*//*Label 5629*/ GIMT_Encode4(410175), // Rule ID 4708 //
        GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasUnrestrictedSOffset),
        GIM_CheckMemoryAddressSpace, /*MI*/0, /*MMO*/0, /*NumAddrSpace*/3, /*AddrSpace*/1, /*AddrSpace*/4, /*AddrSpace*/6,
        GIM_CheckHasNoUse, /*MI*/0,
        GIM_CheckPointerToAny, /*MI*/0, /*Op*/1, /*SizeInBits*/0,
        GIM_CheckComplexPattern, /*MI*/0, /*Op*/1, /*Renderer*/GIMT_Encode2(0), GIMT_Encode2(GICP_gi_mubuf_addr64),
        // (AMDGPUatomic_cmp_swap:{ *:[i64] } (MUBUFAddr64:{ *:[iPTR] } v4i32:{ *:[v4i32] }:$srsrc, i64:{ *:[i64] }:$vaddr, i32:{ *:[i32] }:$soffset, i32:{ *:[i32] }:$offset), v2i64:{ *:[v2i64] }:$vdata_in)<<P:Predicate_AMDGPUatomic_cmp_swap_global_noret_64>>  =>  (BUFFER_ATOMIC_CMPSWAP_X2_ADDR64 VReg_128:{ *:[v2i64] }:$vdata_in, VReg_64:{ *:[i64] }:$vaddr, SReg_128:{ *:[v4i32] }:$srsrc, SCSrc_b32:{ *:[i32] }:$soffset, offset:{ *:[i32] }:$offset)
        GIR_BuildMI, /*InsnID*/0, /*Opcode*/GIMT_Encode2(AMDGPU::BUFFER_ATOMIC_CMPSWAP_X2_ADDR64),
        GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/2, // vdata_in
        GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/1, // vaddr
        GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/0, // srsrc
        GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/2, // soffset
        GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/3, // offset
        GIR_AddImm8, /*InsnID*/0, /*Imm*/0,
        GIR_MergeMemOperands, /*InsnID*/0, /*NumInsns*/1, /*MergeInsnID's*/0,
        GIR_ConstrainSelectedInstOperands, /*InsnID*/0,
        GIR_EraseFromParent, /*InsnID*/0,
        // GIR_Coverage, 4708,
        GIR_Done,
      // Label 5629: @410175
      GIM_Try, /*On fail goto*//*Label 5630*/ GIMT_Encode4(410240), // Rule ID 4712 //
        GIM_CheckMemoryAddressSpace, /*MI*/0, /*MMO*/0, /*NumAddrSpace*/3, /*AddrSpace*/1, /*AddrSpace*/4, /*AddrSpace*/6,
        GIM_CheckHasNoUse, /*MI*/0,
        GIM_CheckPointerToAny, /*MI*/0, /*Op*/1, /*SizeInBits*/0,
        GIM_CheckComplexPattern, /*MI*/0, /*Op*/1, /*Renderer*/GIMT_Encode2(0), GIMT_Encode2(GICP_gi_mubuf_addr64),
        // (AMDGPUatomic_cmp_swap:{ *:[i64] } (MUBUFAddr64:{ *:[iPTR] } v4i32:{ *:[v4i32] }:$srsrc, i64:{ *:[i64] }:$vaddr, i32:{ *:[i32] }:$soffset, i32:{ *:[i32] }:$offset), v2i64:{ *:[v2i64] }:$vdata_in)<<P:Predicate_AMDGPUatomic_cmp_swap_global_noret_64>>  =>  (BUFFER_ATOMIC_CMPSWAP_X2_VBUFFER_ADDR64 VReg_128:{ *:[v2i64] }:$vdata_in, VReg_64:{ *:[i64] }:$vaddr, SReg_128:{ *:[v4i32] }:$srsrc, SCSrc_b32:{ *:[i32] }:$soffset, offset:{ *:[i32] }:$offset)
        GIR_BuildMI, /*InsnID*/0, /*Opcode*/GIMT_Encode2(AMDGPU::BUFFER_ATOMIC_CMPSWAP_X2_VBUFFER_ADDR64),
        GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/2, // vdata_in
        GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/1, // vaddr
        GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/0, // srsrc
        GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/2, // soffset
        GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/3, // offset
        GIR_AddImm8, /*InsnID*/0, /*Imm*/0,
        GIR_MergeMemOperands, /*InsnID*/0, /*NumInsns*/1, /*MergeInsnID's*/0,
        GIR_ConstrainSelectedInstOperands, /*InsnID*/0,
        GIR_EraseFromParent, /*InsnID*/0,
        // GIR_Coverage, 4712,
        GIR_Done,
      // Label 5630: @410240
      GIM_Try, /*On fail goto*//*Label 5631*/ GIMT_Encode4(410361), // Rule ID 4706 //
        GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasUnrestrictedSOffset),
        GIM_CheckMemoryAddressSpace, /*MI*/0, /*MMO*/0, /*NumAddrSpace*/3, /*AddrSpace*/1, /*AddrSpace*/4, /*AddrSpace*/6,
        GIM_CheckRegBankForClass, /*MI*/0, /*Op*/0, /*RC*/GIMT_Encode2(AMDGPU::VReg_128RegClassID),
        GIM_CheckPointerToAny, /*MI*/0, /*Op*/1, /*SizeInBits*/0,
        GIM_CheckComplexPattern, /*MI*/0, /*Op*/1, /*Renderer*/GIMT_Encode2(0), GIMT_Encode2(GICP_gi_mubuf_addr64),
        // (AMDGPUatomic_cmp_swap:{ *:[i64] } (MUBUFAddr64:{ *:[iPTR] } v4i32:{ *:[v4i32] }:$srsrc, i64:{ *:[i64] }:$vaddr, i32:{ *:[i32] }:$soffset, i32:{ *:[i32] }:$offset), v2i64:{ *:[v2i64] }:$vdata_in)<<P:Predicate_AMDGPUatomic_cmp_swap_global_64>>  =>  (EXTRACT_SUBREG:{ *:[i64] } (COPY_TO_REGCLASS:{ *:[i64] } (BUFFER_ATOMIC_CMPSWAP_X2_ADDR64_RTN:{ *:[v8i16] } VReg_128:{ *:[v2i64] }:$vdata_in, VReg_64:{ *:[i64] }:$vaddr, SReg_128:{ *:[v4i32] }:$srsrc, SCSrc_b32:{ *:[i32] }:$soffset, offset:{ *:[i32] }:$offset), VReg_128:{ *:[i32] }), sub0_sub1:{ *:[i32] })
        GIR_MakeTempReg, /*TempRegID*/0, /*TypeID*/GILLT_s64,
        GIR_MakeTempReg, /*TempRegID*/1, /*TypeID*/GILLT_v8s16,
        GIR_BuildMI, /*InsnID*/2, /*Opcode*/GIMT_Encode2(AMDGPU::BUFFER_ATOMIC_CMPSWAP_X2_ADDR64_RTN),
        GIR_AddTempRegister, /*InsnID*/2, /*TempRegID*/1, /*TempRegFlags*/GIMT_Encode2(RegState::Define),
        GIR_Copy, /*NewInsnID*/2, /*OldInsnID*/0, /*OpIdx*/2, // vdata_in
        GIR_ComplexSubOperandRenderer, /*InsnID*/2, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/1, // vaddr
        GIR_ComplexSubOperandRenderer, /*InsnID*/2, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/0, // srsrc
        GIR_ComplexSubOperandRenderer, /*InsnID*/2, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/2, // soffset
        GIR_ComplexSubOperandRenderer, /*InsnID*/2, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/3, // offset
        GIR_AddImm8, /*InsnID*/2, /*Imm*/1,
        GIR_MergeMemOperands, /*InsnID*/2, /*NumInsns*/1, /*MergeInsnID's*/0,
        GIR_ConstrainSelectedInstOperands, /*InsnID*/2,
        GIR_BuildMI, /*InsnID*/1, /*Opcode*/GIMT_Encode2(TargetOpcode::COPY),
        GIR_AddTempRegister, /*InsnID*/1, /*TempRegID*/0, /*TempRegFlags*/GIMT_Encode2(RegState::Define),
        GIR_AddSimpleTempRegister, /*InsnID*/1, /*TempRegID*/1,
        GIR_ConstrainSelectedInstOperands, /*InsnID*/1,
        GIR_BuildMI, /*InsnID*/0, /*Opcode*/GIMT_Encode2(TargetOpcode::COPY),
        GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/0, // DstI[dst]
        GIR_AddTempSubRegister, /*InsnID*/0, /*TempRegID*/0, /*TempRegFlags*/GIMT_Encode2(0), GIMT_Encode2(AMDGPU::sub0_sub1),
        GIR_ConstrainOperandRC, /*InsnID*/0, /*Op*/0, GIMT_Encode2(AMDGPU::VReg_64RegClassID),
        GIR_ConstrainOperandRC, /*InsnID*/0, /*Op*/1, GIMT_Encode2(AMDGPU::VReg_128RegClassID),
        GIR_EraseFromParent, /*InsnID*/0,
        // GIR_Coverage, 4706,
        GIR_Done,
      // Label 5631: @410361
      GIM_Try, /*On fail goto*//*Label 5632*/ GIMT_Encode4(410479), // Rule ID 4710 //
        GIM_CheckMemoryAddressSpace, /*MI*/0, /*MMO*/0, /*NumAddrSpace*/3, /*AddrSpace*/1, /*AddrSpace*/4, /*AddrSpace*/6,
        GIM_CheckRegBankForClass, /*MI*/0, /*Op*/0, /*RC*/GIMT_Encode2(AMDGPU::VReg_128RegClassID),
        GIM_CheckPointerToAny, /*MI*/0, /*Op*/1, /*SizeInBits*/0,
        GIM_CheckComplexPattern, /*MI*/0, /*Op*/1, /*Renderer*/GIMT_Encode2(0), GIMT_Encode2(GICP_gi_mubuf_addr64),
        // (AMDGPUatomic_cmp_swap:{ *:[i64] } (MUBUFAddr64:{ *:[iPTR] } v4i32:{ *:[v4i32] }:$srsrc, i64:{ *:[i64] }:$vaddr, i32:{ *:[i32] }:$soffset, i32:{ *:[i32] }:$offset), v2i64:{ *:[v2i64] }:$vdata_in)<<P:Predicate_AMDGPUatomic_cmp_swap_global_64>>  =>  (EXTRACT_SUBREG:{ *:[i64] } (COPY_TO_REGCLASS:{ *:[i64] } (BUFFER_ATOMIC_CMPSWAP_X2_VBUFFER_ADDR64_RTN:{ *:[v8i16] } VReg_128:{ *:[v2i64] }:$vdata_in, VReg_64:{ *:[i64] }:$vaddr, SReg_128:{ *:[v4i32] }:$srsrc, SCSrc_b32:{ *:[i32] }:$soffset, offset:{ *:[i32] }:$offset), VReg_128:{ *:[i32] }), sub0_sub1:{ *:[i32] })
        GIR_MakeTempReg, /*TempRegID*/0, /*TypeID*/GILLT_s64,
        GIR_MakeTempReg, /*TempRegID*/1, /*TypeID*/GILLT_v8s16,
        GIR_BuildMI, /*InsnID*/2, /*Opcode*/GIMT_Encode2(AMDGPU::BUFFER_ATOMIC_CMPSWAP_X2_VBUFFER_ADDR64_RTN),
        GIR_AddTempRegister, /*InsnID*/2, /*TempRegID*/1, /*TempRegFlags*/GIMT_Encode2(RegState::Define),
        GIR_Copy, /*NewInsnID*/2, /*OldInsnID*/0, /*OpIdx*/2, // vdata_in
        GIR_ComplexSubOperandRenderer, /*InsnID*/2, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/1, // vaddr
        GIR_ComplexSubOperandRenderer, /*InsnID*/2, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/0, // srsrc
        GIR_ComplexSubOperandRenderer, /*InsnID*/2, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/2, // soffset
        GIR_ComplexSubOperandRenderer, /*InsnID*/2, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/3, // offset
        GIR_AddImm8, /*InsnID*/2, /*Imm*/1,
        GIR_MergeMemOperands, /*InsnID*/2, /*NumInsns*/1, /*MergeInsnID's*/0,
        GIR_ConstrainSelectedInstOperands, /*InsnID*/2,
        GIR_BuildMI, /*InsnID*/1, /*Opcode*/GIMT_Encode2(TargetOpcode::COPY),
        GIR_AddTempRegister, /*InsnID*/1, /*TempRegID*/0, /*TempRegFlags*/GIMT_Encode2(RegState::Define),
        GIR_AddSimpleTempRegister, /*InsnID*/1, /*TempRegID*/1,
        GIR_ConstrainSelectedInstOperands, /*InsnID*/1,
        GIR_BuildMI, /*InsnID*/0, /*Opcode*/GIMT_Encode2(TargetOpcode::COPY),
        GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/0, // DstI[dst]
        GIR_AddTempSubRegister, /*InsnID*/0, /*TempRegID*/0, /*TempRegFlags*/GIMT_Encode2(0), GIMT_Encode2(AMDGPU::sub0_sub1),
        GIR_ConstrainOperandRC, /*InsnID*/0, /*Op*/0, GIMT_Encode2(AMDGPU::VReg_64RegClassID),
        GIR_ConstrainOperandRC, /*InsnID*/0, /*Op*/1, GIMT_Encode2(AMDGPU::VReg_128RegClassID),
        GIR_EraseFromParent, /*InsnID*/0,
        // GIR_Coverage, 4710,
        GIR_Done,
      // Label 5632: @410479
      GIM_Try, /*On fail goto*//*Label 5633*/ GIMT_Encode4(410542), // Rule ID 4707 //
        GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasUnrestrictedSOffset),
        GIM_CheckMemoryAddressSpace, /*MI*/0, /*MMO*/0, /*NumAddrSpace*/3, /*AddrSpace*/1, /*AddrSpace*/4, /*AddrSpace*/6,
        GIM_CheckHasNoUse, /*MI*/0,
        GIM_CheckPointerToAny, /*MI*/0, /*Op*/1, /*SizeInBits*/0,
        GIM_CheckComplexPattern, /*MI*/0, /*Op*/1, /*Renderer*/GIMT_Encode2(0), GIMT_Encode2(GICP_gi_mubuf_offset),
        // (AMDGPUatomic_cmp_swap:{ *:[i64] } (MUBUFOffset:{ *:[iPTR] } v4i32:{ *:[v4i32] }:$srsrc, i32:{ *:[i32] }:$soffset, i32:{ *:[i32] }:$offset), v2i64:{ *:[v2i64] }:$vdata_in)<<P:Predicate_AMDGPUatomic_cmp_swap_global_noret_64>>  =>  (BUFFER_ATOMIC_CMPSWAP_X2_OFFSET VReg_128:{ *:[v2i64] }:$vdata_in, SReg_128:{ *:[v4i32] }:$srsrc, SCSrc_b32:{ *:[i32] }:$soffset, offset:{ *:[i32] }:$offset)
        GIR_BuildMI, /*InsnID*/0, /*Opcode*/GIMT_Encode2(AMDGPU::BUFFER_ATOMIC_CMPSWAP_X2_OFFSET),
        GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/2, // vdata_in
        GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/0, // srsrc
        GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/1, // soffset
        GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/2, // offset
        GIR_AddImm8, /*InsnID*/0, /*Imm*/0,
        GIR_MergeMemOperands, /*InsnID*/0, /*NumInsns*/1, /*MergeInsnID's*/0,
        GIR_ConstrainSelectedInstOperands, /*InsnID*/0,
        GIR_EraseFromParent, /*InsnID*/0,
        // GIR_Coverage, 4707,
        GIR_Done,
      // Label 5633: @410542
      GIM_Try, /*On fail goto*//*Label 5634*/ GIMT_Encode4(410602), // Rule ID 4711 //
        GIM_CheckMemoryAddressSpace, /*MI*/0, /*MMO*/0, /*NumAddrSpace*/3, /*AddrSpace*/1, /*AddrSpace*/4, /*AddrSpace*/6,
        GIM_CheckHasNoUse, /*MI*/0,
        GIM_CheckPointerToAny, /*MI*/0, /*Op*/1, /*SizeInBits*/0,
        GIM_CheckComplexPattern, /*MI*/0, /*Op*/1, /*Renderer*/GIMT_Encode2(0), GIMT_Encode2(GICP_gi_mubuf_offset),
        // (AMDGPUatomic_cmp_swap:{ *:[i64] } (MUBUFOffset:{ *:[iPTR] } v4i32:{ *:[v4i32] }:$srsrc, i32:{ *:[i32] }:$soffset, i32:{ *:[i32] }:$offset), v2i64:{ *:[v2i64] }:$vdata_in)<<P:Predicate_AMDGPUatomic_cmp_swap_global_noret_64>>  =>  (BUFFER_ATOMIC_CMPSWAP_X2_VBUFFER_OFFSET VReg_128:{ *:[v2i64] }:$vdata_in, SReg_128:{ *:[v4i32] }:$srsrc, SCSrc_b32:{ *:[i32] }:$soffset, offset:{ *:[i32] }:$offset)
        GIR_BuildMI, /*InsnID*/0, /*Opcode*/GIMT_Encode2(AMDGPU::BUFFER_ATOMIC_CMPSWAP_X2_VBUFFER_OFFSET),
        GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/2, // vdata_in
        GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/0, // srsrc
        GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/1, // soffset
        GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/2, // offset
        GIR_AddImm8, /*InsnID*/0, /*Imm*/0,
        GIR_MergeMemOperands, /*InsnID*/0, /*NumInsns*/1, /*MergeInsnID's*/0,
        GIR_ConstrainSelectedInstOperands, /*InsnID*/0,
        GIR_EraseFromParent, /*InsnID*/0,
        // GIR_Coverage, 4711,
        GIR_Done,
      // Label 5634: @410602
      GIM_Try, /*On fail goto*//*Label 5635*/ GIMT_Encode4(410718), // Rule ID 4705 //
        GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasUnrestrictedSOffset),
        GIM_CheckMemoryAddressSpace, /*MI*/0, /*MMO*/0, /*NumAddrSpace*/3, /*AddrSpace*/1, /*AddrSpace*/4, /*AddrSpace*/6,
        GIM_CheckRegBankForClass, /*MI*/0, /*Op*/0, /*RC*/GIMT_Encode2(AMDGPU::VReg_128RegClassID),
        GIM_CheckPointerToAny, /*MI*/0, /*Op*/1, /*SizeInBits*/0,
        GIM_CheckComplexPattern, /*MI*/0, /*Op*/1, /*Renderer*/GIMT_Encode2(0), GIMT_Encode2(GICP_gi_mubuf_offset),
        // (AMDGPUatomic_cmp_swap:{ *:[i64] } (MUBUFOffset:{ *:[iPTR] } v4i32:{ *:[v4i32] }:$srsrc, i32:{ *:[i32] }:$soffset, i32:{ *:[i32] }:$offset), v2i64:{ *:[v2i64] }:$vdata_in)<<P:Predicate_AMDGPUatomic_cmp_swap_global_64>>  =>  (EXTRACT_SUBREG:{ *:[i64] } (COPY_TO_REGCLASS:{ *:[i64] } (BUFFER_ATOMIC_CMPSWAP_X2_OFFSET_RTN:{ *:[v8i16] } VReg_128:{ *:[v2i64] }:$vdata_in, SReg_128:{ *:[v4i32] }:$srsrc, SCSrc_b32:{ *:[i32] }:$soffset, offset:{ *:[i32] }:$offset), VReg_128:{ *:[i32] }), sub0_sub1:{ *:[i32] })
        GIR_MakeTempReg, /*TempRegID*/0, /*TypeID*/GILLT_s64,
        GIR_MakeTempReg, /*TempRegID*/1, /*TypeID*/GILLT_v8s16,
        GIR_BuildMI, /*InsnID*/2, /*Opcode*/GIMT_Encode2(AMDGPU::BUFFER_ATOMIC_CMPSWAP_X2_OFFSET_RTN),
        GIR_AddTempRegister, /*InsnID*/2, /*TempRegID*/1, /*TempRegFlags*/GIMT_Encode2(RegState::Define),
        GIR_Copy, /*NewInsnID*/2, /*OldInsnID*/0, /*OpIdx*/2, // vdata_in
        GIR_ComplexSubOperandRenderer, /*InsnID*/2, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/0, // srsrc
        GIR_ComplexSubOperandRenderer, /*InsnID*/2, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/1, // soffset
        GIR_ComplexSubOperandRenderer, /*InsnID*/2, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/2, // offset
        GIR_AddImm8, /*InsnID*/2, /*Imm*/1,
        GIR_MergeMemOperands, /*InsnID*/2, /*NumInsns*/1, /*MergeInsnID's*/0,
        GIR_ConstrainSelectedInstOperands, /*InsnID*/2,
        GIR_BuildMI, /*InsnID*/1, /*Opcode*/GIMT_Encode2(TargetOpcode::COPY),
        GIR_AddTempRegister, /*InsnID*/1, /*TempRegID*/0, /*TempRegFlags*/GIMT_Encode2(RegState::Define),
        GIR_AddSimpleTempRegister, /*InsnID*/1, /*TempRegID*/1,
        GIR_ConstrainSelectedInstOperands, /*InsnID*/1,
        GIR_BuildMI, /*InsnID*/0, /*Opcode*/GIMT_Encode2(TargetOpcode::COPY),
        GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/0, // DstI[dst]
        GIR_AddTempSubRegister, /*InsnID*/0, /*TempRegID*/0, /*TempRegFlags*/GIMT_Encode2(0), GIMT_Encode2(AMDGPU::sub0_sub1),
        GIR_ConstrainOperandRC, /*InsnID*/0, /*Op*/0, GIMT_Encode2(AMDGPU::VReg_64RegClassID),
        GIR_ConstrainOperandRC, /*InsnID*/0, /*Op*/1, GIMT_Encode2(AMDGPU::VReg_128RegClassID),
        GIR_EraseFromParent, /*InsnID*/0,
        // GIR_Coverage, 4705,
        GIR_Done,
      // Label 5635: @410718
      GIM_Try, /*On fail goto*//*Label 5636*/ GIMT_Encode4(410831), // Rule ID 4709 //
        GIM_CheckMemoryAddressSpace, /*MI*/0, /*MMO*/0, /*NumAddrSpace*/3, /*AddrSpace*/1, /*AddrSpace*/4, /*AddrSpace*/6,
        GIM_CheckRegBankForClass, /*MI*/0, /*Op*/0, /*RC*/GIMT_Encode2(AMDGPU::VReg_128RegClassID),
        GIM_CheckPointerToAny, /*MI*/0, /*Op*/1, /*SizeInBits*/0,
        GIM_CheckComplexPattern, /*MI*/0, /*Op*/1, /*Renderer*/GIMT_Encode2(0), GIMT_Encode2(GICP_gi_mubuf_offset),
        // (AMDGPUatomic_cmp_swap:{ *:[i64] } (MUBUFOffset:{ *:[iPTR] } v4i32:{ *:[v4i32] }:$srsrc, i32:{ *:[i32] }:$soffset, i32:{ *:[i32] }:$offset), v2i64:{ *:[v2i64] }:$vdata_in)<<P:Predicate_AMDGPUatomic_cmp_swap_global_64>>  =>  (EXTRACT_SUBREG:{ *:[i64] } (COPY_TO_REGCLASS:{ *:[i64] } (BUFFER_ATOMIC_CMPSWAP_X2_VBUFFER_OFFSET_RTN:{ *:[v8i16] } VReg_128:{ *:[v2i64] }:$vdata_in, SReg_128:{ *:[v4i32] }:$srsrc, SCSrc_b32:{ *:[i32] }:$soffset, offset:{ *:[i32] }:$offset), VReg_128:{ *:[i32] }), sub0_sub1:{ *:[i32] })
        GIR_MakeTempReg, /*TempRegID*/0, /*TypeID*/GILLT_s64,
        GIR_MakeTempReg, /*TempRegID*/1, /*TypeID*/GILLT_v8s16,
        GIR_BuildMI, /*InsnID*/2, /*Opcode*/GIMT_Encode2(AMDGPU::BUFFER_ATOMIC_CMPSWAP_X2_VBUFFER_OFFSET_RTN),
        GIR_AddTempRegister, /*InsnID*/2, /*TempRegID*/1, /*TempRegFlags*/GIMT_Encode2(RegState::Define),
        GIR_Copy, /*NewInsnID*/2, /*OldInsnID*/0, /*OpIdx*/2, // vdata_in
        GIR_ComplexSubOperandRenderer, /*InsnID*/2, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/0, // srsrc
        GIR_ComplexSubOperandRenderer, /*InsnID*/2, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/1, // soffset
        GIR_ComplexSubOperandRenderer, /*InsnID*/2, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/2, // offset
        GIR_AddImm8, /*InsnID*/2, /*Imm*/1,
        GIR_MergeMemOperands, /*InsnID*/2, /*NumInsns*/1, /*MergeInsnID's*/0,
        GIR_ConstrainSelectedInstOperands, /*InsnID*/2,
        GIR_BuildMI, /*InsnID*/1, /*Opcode*/GIMT_Encode2(TargetOpcode::COPY),
        GIR_AddTempRegister, /*InsnID*/1, /*TempRegID*/0, /*TempRegFlags*/GIMT_Encode2(RegState::Define),
        GIR_AddSimpleTempRegister, /*InsnID*/1, /*TempRegID*/1,
        GIR_ConstrainSelectedInstOperands, /*InsnID*/1,
        GIR_BuildMI, /*InsnID*/0, /*Opcode*/GIMT_Encode2(TargetOpcode::COPY),
        GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/0, // DstI[dst]
        GIR_AddTempSubRegister, /*InsnID*/0, /*TempRegID*/0, /*TempRegFlags*/GIMT_Encode2(0), GIMT_Encode2(AMDGPU::sub0_sub1),
        GIR_ConstrainOperandRC, /*InsnID*/0, /*Op*/0, GIMT_Encode2(AMDGPU::VReg_64RegClassID),
        GIR_ConstrainOperandRC, /*InsnID*/0, /*Op*/1, GIMT_Encode2(AMDGPU::VReg_128RegClassID),
        GIR_EraseFromParent, /*InsnID*/0,
        // GIR_Coverage, 4709,
        GIR_Done,
      // Label 5636: @410831
      GIM_Try, /*On fail goto*//*Label 5637*/ GIMT_Encode4(410894), // Rule ID 3247 //
        GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasFlatGlobalInsts),
        GIM_CheckMemoryAddressSpace, /*MI*/0, /*MMO*/0, /*NumAddrSpace*/3, /*AddrSpace*/1, /*AddrSpace*/4, /*AddrSpace*/6,
        GIM_CheckHasNoUse, /*MI*/0,
        GIM_CheckPointerToAny, /*MI*/0, /*Op*/1, /*SizeInBits*/0,
        GIM_CheckComplexPattern, /*MI*/0, /*Op*/1, /*Renderer*/GIMT_Encode2(0), GIMT_Encode2(GICP_gi_global_saddr),
        // (AMDGPUatomic_cmp_swap:{ *:[i64] } (GlobalSAddr:{ *:[iPTR] } SReg_64:{ *:[i64] }:$saddr, VGPR_32:{ *:[i32] }:$voffset, i32:{ *:[i32] }:$offset), v2i64:{ *:[v2i64] }:$data)<<P:Predicate_AMDGPUatomic_cmp_swap_global_noret_64>>  =>  (GLOBAL_ATOMIC_CMPSWAP_X2_SADDR ?:{ *:[i32] }:$voffset, anonymous_15034:{ *:[v2i64] }:$data, ?:{ *:[i64] }:$saddr, ?:{ *:[i32] }:$offset)
        GIR_BuildMI, /*InsnID*/0, /*Opcode*/GIMT_Encode2(AMDGPU::GLOBAL_ATOMIC_CMPSWAP_X2_SADDR),
        GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/1, // voffset
        GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/2, // data
        GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/0, // saddr
        GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/2, // offset
        GIR_AddImm8, /*InsnID*/0, /*Imm*/0,
        GIR_MergeMemOperands, /*InsnID*/0, /*NumInsns*/1, /*MergeInsnID's*/0,
        GIR_ConstrainSelectedInstOperands, /*InsnID*/0,
        GIR_EraseFromParent, /*InsnID*/0,
        // GIR_Coverage, 3247,
        GIR_Done,
      // Label 5637: @410894
      GIM_Try, /*On fail goto*//*Label 5638*/ GIMT_Encode4(410964), // Rule ID 3249 //
        GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasFlatGlobalInsts),
        GIM_CheckMemoryAddressSpace, /*MI*/0, /*MMO*/0, /*NumAddrSpace*/3, /*AddrSpace*/1, /*AddrSpace*/4, /*AddrSpace*/6,
        GIM_CheckRegBankForClass, /*MI*/0, /*Op*/0, /*RC*/GIMT_Encode2(AMDGPU::AV_64RegClassID),
        GIM_CheckPointerToAny, /*MI*/0, /*Op*/1, /*SizeInBits*/0,
        GIM_CheckComplexPattern, /*MI*/0, /*Op*/1, /*Renderer*/GIMT_Encode2(0), GIMT_Encode2(GICP_gi_global_saddr),
        // (AMDGPUatomic_cmp_swap:{ *:[i64] } (GlobalSAddr:{ *:[iPTR] } SReg_64:{ *:[i64] }:$saddr, VGPR_32:{ *:[i32] }:$voffset, i32:{ *:[i32] }:$offset), v2i64:{ *:[v2i64] }:$data)<<P:Predicate_AMDGPUatomic_cmp_swap_global_64>>  =>  (GLOBAL_ATOMIC_CMPSWAP_X2_SADDR_RTN:{ *:[i64] } ?:{ *:[i32] }:$voffset, anonymous_15034:{ *:[v2i64] }:$data, ?:{ *:[i64] }:$saddr, ?:{ *:[i32] }:$offset)
        GIR_BuildMI, /*InsnID*/0, /*Opcode*/GIMT_Encode2(AMDGPU::GLOBAL_ATOMIC_CMPSWAP_X2_SADDR_RTN),
        GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/0, // DstI[vdst]
        GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/1, // voffset
        GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/2, // data
        GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/0, // saddr
        GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/2, // offset
        GIR_AddImm8, /*InsnID*/0, /*Imm*/1,
        GIR_MergeMemOperands, /*InsnID*/0, /*NumInsns*/1, /*MergeInsnID's*/0,
        GIR_ConstrainSelectedInstOperands, /*InsnID*/0,
        GIR_EraseFromParent, /*InsnID*/0,
        // GIR_Coverage, 3249,
        GIR_Done,
      // Label 5638: @410964
      GIM_Try, /*On fail goto*//*Label 5639*/ GIMT_Encode4(411022), // Rule ID 3246 //
        GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasFlatGlobalInsts),
        GIM_CheckMemoryAddressSpace, /*MI*/0, /*MMO*/0, /*NumAddrSpace*/3, /*AddrSpace*/1, /*AddrSpace*/4, /*AddrSpace*/6,
        GIM_CheckHasNoUse, /*MI*/0,
        GIM_CheckPointerToAny, /*MI*/0, /*Op*/1, /*SizeInBits*/0,
        GIM_CheckComplexPattern, /*MI*/0, /*Op*/1, /*Renderer*/GIMT_Encode2(0), GIMT_Encode2(GICP_gi_global_offset),
        // (AMDGPUatomic_cmp_swap:{ *:[i64] } (GlobalOffset:{ *:[iPTR] } i64:{ *:[i64] }:$vaddr, i32:{ *:[i32] }:$offset), v2i64:{ *:[v2i64] }:$data)<<P:Predicate_AMDGPUatomic_cmp_swap_global_noret_64>>  =>  (GLOBAL_ATOMIC_CMPSWAP_X2 VReg_64:{ *:[i64] }:$vaddr, anonymous_15034:{ *:[v2i64] }:$data, ?:{ *:[i32] }:$offset)
        GIR_BuildMI, /*InsnID*/0, /*Opcode*/GIMT_Encode2(AMDGPU::GLOBAL_ATOMIC_CMPSWAP_X2),
        GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/0, // vaddr
        GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/2, // data
        GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/1, // offset
        GIR_AddImm8, /*InsnID*/0, /*Imm*/0,
        GIR_MergeMemOperands, /*InsnID*/0, /*NumInsns*/1, /*MergeInsnID's*/0,
        GIR_ConstrainSelectedInstOperands, /*InsnID*/0,
        GIR_EraseFromParent, /*InsnID*/0,
        // GIR_Coverage, 3246,
        GIR_Done,
      // Label 5639: @411022
      GIM_Try, /*On fail goto*//*Label 5640*/ GIMT_Encode4(411087), // Rule ID 3248 //
        GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasFlatGlobalInsts),
        GIM_CheckMemoryAddressSpace, /*MI*/0, /*MMO*/0, /*NumAddrSpace*/3, /*AddrSpace*/1, /*AddrSpace*/4, /*AddrSpace*/6,
        GIM_CheckRegBankForClass, /*MI*/0, /*Op*/0, /*RC*/GIMT_Encode2(AMDGPU::AV_64RegClassID),
        GIM_CheckPointerToAny, /*MI*/0, /*Op*/1, /*SizeInBits*/0,
        GIM_CheckComplexPattern, /*MI*/0, /*Op*/1, /*Renderer*/GIMT_Encode2(0), GIMT_Encode2(GICP_gi_global_offset),
        // (AMDGPUatomic_cmp_swap:{ *:[i64] } (GlobalOffset:{ *:[iPTR] } i64:{ *:[i64] }:$vaddr, i32:{ *:[i32] }:$offset), v2i64:{ *:[v2i64] }:$data)<<P:Predicate_AMDGPUatomic_cmp_swap_global_64>>  =>  (GLOBAL_ATOMIC_CMPSWAP_X2_RTN:{ *:[i64] } VReg_64:{ *:[i64] }:$vaddr, anonymous_15034:{ *:[v2i64] }:$data, ?:{ *:[i32] }:$offset)
        GIR_BuildMI, /*InsnID*/0, /*Opcode*/GIMT_Encode2(AMDGPU::GLOBAL_ATOMIC_CMPSWAP_X2_RTN),
        GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/0, // DstI[vdst]
        GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/0, // vaddr
        GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/2, // data
        GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/1, // offset
        GIR_AddImm8, /*InsnID*/0, /*Imm*/1,
        GIR_MergeMemOperands, /*InsnID*/0, /*NumInsns*/1, /*MergeInsnID's*/0,
        GIR_ConstrainSelectedInstOperands, /*InsnID*/0,
        GIR_EraseFromParent, /*InsnID*/0,
        // GIR_Coverage, 3248,
        GIR_Done,
      // Label 5640: @411087
      GIM_Try, /*On fail goto*//*Label 5641*/ GIMT_Encode4(411146), // Rule ID 2876 //
        GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasFlatAddressSpace),
        GIM_CheckMemoryAddressSpace, /*MI*/0, /*MMO*/0, /*NumAddrSpace*/4, /*AddrSpace*/0, /*AddrSpace*/1, /*AddrSpace*/4, /*AddrSpace*/6,
        GIM_CheckHasNoUse, /*MI*/0,
        GIM_CheckPointerToAny, /*MI*/0, /*Op*/1, /*SizeInBits*/0,
        GIM_CheckComplexPattern, /*MI*/0, /*Op*/1, /*Renderer*/GIMT_Encode2(0), GIMT_Encode2(GICP_gi_flat_offset),
        // (AMDGPUatomic_cmp_swap:{ *:[i64] } (FlatOffset:{ *:[iPTR] } i64:{ *:[i64] }:$vaddr, i32:{ *:[i32] }:$offset), v2i64:{ *:[v2i64] }:$data)<<P:Predicate_AMDGPUatomic_cmp_swap_flat_noret_64>>  =>  (FLAT_ATOMIC_CMPSWAP_X2 VReg_64:{ *:[i64] }:$vaddr, anonymous_15034:{ *:[v2i64] }:$data, ?:{ *:[i32] }:$offset)
        GIR_BuildMI, /*InsnID*/0, /*Opcode*/GIMT_Encode2(AMDGPU::FLAT_ATOMIC_CMPSWAP_X2),
        GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/0, // vaddr
        GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/2, // data
        GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/1, // offset
        GIR_AddImm8, /*InsnID*/0, /*Imm*/0,
        GIR_MergeMemOperands, /*InsnID*/0, /*NumInsns*/1, /*MergeInsnID's*/0,
        GIR_ConstrainSelectedInstOperands, /*InsnID*/0,
        GIR_EraseFromParent, /*InsnID*/0,
        // GIR_Coverage, 2876,
        GIR_Done,
      // Label 5641: @411146
      GIM_Try, /*On fail goto*//*Label 5642*/ GIMT_Encode4(411204), // Rule ID 2928 //
        GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasFlatAddressSpace),
        GIM_CheckMemoryAddressSpace, /*MI*/0, /*MMO*/0, /*NumAddrSpace*/3, /*AddrSpace*/1, /*AddrSpace*/4, /*AddrSpace*/6,
        GIM_CheckHasNoUse, /*MI*/0,
        GIM_CheckPointerToAny, /*MI*/0, /*Op*/1, /*SizeInBits*/0,
        GIM_CheckComplexPattern, /*MI*/0, /*Op*/1, /*Renderer*/GIMT_Encode2(0), GIMT_Encode2(GICP_gi_flat_offset),
        // (AMDGPUatomic_cmp_swap:{ *:[i64] } (FlatOffset:{ *:[iPTR] } i64:{ *:[i64] }:$vaddr, i32:{ *:[i32] }:$offset), v2i64:{ *:[v2i64] }:$data)<<P:Predicate_AMDGPUatomic_cmp_swap_global_noret_64>>  =>  (FLAT_ATOMIC_CMPSWAP_X2 VReg_64:{ *:[i64] }:$vaddr, anonymous_15034:{ *:[v2i64] }:$data, ?:{ *:[i32] }:$offset)
        GIR_BuildMI, /*InsnID*/0, /*Opcode*/GIMT_Encode2(AMDGPU::FLAT_ATOMIC_CMPSWAP_X2),
        GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/0, // vaddr
        GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/2, // data
        GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/1, // offset
        GIR_AddImm8, /*InsnID*/0, /*Imm*/0,
        GIR_MergeMemOperands, /*InsnID*/0, /*NumInsns*/1, /*MergeInsnID's*/0,
        GIR_ConstrainSelectedInstOperands, /*InsnID*/0,
        GIR_EraseFromParent, /*InsnID*/0,
        // GIR_Coverage, 2928,
        GIR_Done,
      // Label 5642: @411204
      GIM_Try, /*On fail goto*//*Label 5643*/ GIMT_Encode4(411270), // Rule ID 2875 //
        GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasFlatAddressSpace),
        GIM_CheckMemoryAddressSpace, /*MI*/0, /*MMO*/0, /*NumAddrSpace*/4, /*AddrSpace*/0, /*AddrSpace*/1, /*AddrSpace*/4, /*AddrSpace*/6,
        GIM_CheckRegBankForClass, /*MI*/0, /*Op*/0, /*RC*/GIMT_Encode2(AMDGPU::AV_64RegClassID),
        GIM_CheckPointerToAny, /*MI*/0, /*Op*/1, /*SizeInBits*/0,
        GIM_CheckComplexPattern, /*MI*/0, /*Op*/1, /*Renderer*/GIMT_Encode2(0), GIMT_Encode2(GICP_gi_flat_offset),
        // (AMDGPUatomic_cmp_swap:{ *:[i64] } (FlatOffset:{ *:[iPTR] } i64:{ *:[i64] }:$vaddr, i32:{ *:[i32] }:$offset), v2i64:{ *:[v2i64] }:$data)<<P:Predicate_AMDGPUatomic_cmp_swap_flat_64>>  =>  (FLAT_ATOMIC_CMPSWAP_X2_RTN:{ *:[i64] } VReg_64:{ *:[i64] }:$vaddr, anonymous_15034:{ *:[v2i64] }:$data, ?:{ *:[i32] }:$offset)
        GIR_BuildMI, /*InsnID*/0, /*Opcode*/GIMT_Encode2(AMDGPU::FLAT_ATOMIC_CMPSWAP_X2_RTN),
        GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/0, // DstI[vdst]
        GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/0, // vaddr
        GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/2, // data
        GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/1, // offset
        GIR_AddImm8, /*InsnID*/0, /*Imm*/1,
        GIR_MergeMemOperands, /*InsnID*/0, /*NumInsns*/1, /*MergeInsnID's*/0,
        GIR_ConstrainSelectedInstOperands, /*InsnID*/0,
        GIR_EraseFromParent, /*InsnID*/0,
        // GIR_Coverage, 2875,
        GIR_Done,
      // Label 5643: @411270
      GIM_Try, /*On fail goto*//*Label 5644*/ GIMT_Encode4(411335), // Rule ID 2927 //
        GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasFlatAddressSpace),
        GIM_CheckMemoryAddressSpace, /*MI*/0, /*MMO*/0, /*NumAddrSpace*/3, /*AddrSpace*/1, /*AddrSpace*/4, /*AddrSpace*/6,
        GIM_CheckRegBankForClass, /*MI*/0, /*Op*/0, /*RC*/GIMT_Encode2(AMDGPU::AV_64RegClassID),
        GIM_CheckPointerToAny, /*MI*/0, /*Op*/1, /*SizeInBits*/0,
        GIM_CheckComplexPattern, /*MI*/0, /*Op*/1, /*Renderer*/GIMT_Encode2(0), GIMT_Encode2(GICP_gi_flat_offset),
        // (AMDGPUatomic_cmp_swap:{ *:[i64] } (FlatOffset:{ *:[iPTR] } i64:{ *:[i64] }:$vaddr, i32:{ *:[i32] }:$offset), v2i64:{ *:[v2i64] }:$data)<<P:Predicate_AMDGPUatomic_cmp_swap_global_64>>  =>  (FLAT_ATOMIC_CMPSWAP_X2_RTN:{ *:[i64] } VReg_64:{ *:[i64] }:$vaddr, anonymous_15034:{ *:[v2i64] }:$data, ?:{ *:[i32] }:$offset)
        GIR_BuildMI, /*InsnID*/0, /*Opcode*/GIMT_Encode2(AMDGPU::FLAT_ATOMIC_CMPSWAP_X2_RTN),
        GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/0, // DstI[vdst]
        GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/0, // vaddr
        GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/2, // data
        GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/1, // offset
        GIR_AddImm8, /*InsnID*/0, /*Imm*/1,
        GIR_MergeMemOperands, /*InsnID*/0, /*NumInsns*/1, /*MergeInsnID's*/0,
        GIR_ConstrainSelectedInstOperands, /*InsnID*/0,
        GIR_EraseFromParent, /*InsnID*/0,
        // GIR_Coverage, 2927,
        GIR_Done,
      // Label 5644: @411335
      GIM_Reject,
    // Label 5628: @411336
    GIM_Reject,
    // Label 5610: @411337
    GIM_Reject,
    // Label 104: @411338
    GIM_SwitchType, /*MI*/0, /*Op*/0, /*[*/GIMT_Encode2(9), GIMT_Encode2(11), /*)*//*default:*//*Label 5647*/ GIMT_Encode4(413236),
    /*GILLT_s32*//*Label 5645*/ GIMT_Encode4(411357),
    /*GILLT_s64*//*Label 5646*/ GIMT_Encode4(412106),
    // Label 5645: @411357
    GIM_Try, /*On fail goto*//*Label 5648*/ GIMT_Encode4(412105),
      GIM_CheckType, /*MI*/0, /*Op*/2, /*Type*/GILLT_s32,
      GIM_Try, /*On fail goto*//*Label 5649*/ GIMT_Encode4(411422), // Rule ID 6977 //
        GIM_CheckFeatures, GIMT_Encode2(GIFBS_LDSRequiresM0Init),
        GIM_CheckMemoryAddressSpace, /*MI*/0, /*MMO*/0, /*NumAddrSpace*/1, /*AddrSpace*/3,
        GIM_CheckHasNoUse, /*MI*/0,
        GIM_CheckPointerToAny, /*MI*/0, /*Op*/1, /*SizeInBits*/0,
        GIM_CheckComplexPattern, /*MI*/0, /*Op*/1, /*Renderer*/GIMT_Encode2(0), GIMT_Encode2(GICP_gi_ds_1addr_1offset),
        // (atomic_load_fmax_glue:{ *:[f32] } (DS1Addr1Offset:{ *:[iPTR] } i32:{ *:[i32] }:$ptr, i32:{ *:[i32] }:$offset), f32:{ *:[f32] }:$value)<<P:Predicate_atomic_load_fmax_local_m0_noret_32>>  =>  (DS_MAX_F32 ?:{ *:[i32] }:$ptr, anonymous_15037:{ *:[f32] }:$value, offset:{ *:[i32] }:$offset, 0:{ *:[i1] })
        GIR_BuildMI, /*InsnID*/0, /*Opcode*/GIMT_Encode2(AMDGPU::DS_MAX_F32),
        GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/0, // ptr
        GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/2, // value
        GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/1, // offset
        GIR_AddImm8, /*InsnID*/0, /*Imm*/0,
        GIR_MergeMemOperands, /*InsnID*/0, /*NumInsns*/1, /*MergeInsnID's*/0,
        GIR_ConstrainSelectedInstOperands, /*InsnID*/0,
        GIR_EraseFromParent, /*InsnID*/0,
        // GIR_Coverage, 6977,
        GIR_Done,
      // Label 5649: @411422
      GIM_Try, /*On fail goto*//*Label 5650*/ GIMT_Encode4(411478), // Rule ID 6979 //
        GIM_CheckFeatures, GIMT_Encode2(GIFBS_NotLDSRequiresM0Init),
        GIM_CheckMemoryAddressSpace, /*MI*/0, /*MMO*/0, /*NumAddrSpace*/1, /*AddrSpace*/3,
        GIM_CheckHasNoUse, /*MI*/0,
        GIM_CheckPointerToAny, /*MI*/0, /*Op*/1, /*SizeInBits*/0,
        GIM_CheckComplexPattern, /*MI*/0, /*Op*/1, /*Renderer*/GIMT_Encode2(0), GIMT_Encode2(GICP_gi_ds_1addr_1offset),
        // (SIatomic_fmax:{ *:[f32] } (DS1Addr1Offset:{ *:[iPTR] } i32:{ *:[i32] }:$ptr, i32:{ *:[i32] }:$offset), f32:{ *:[f32] }:$value)<<P:Predicate_atomic_load_fmax_local_noret_32>>  =>  (DS_MAX_F32_gfx9 ?:{ *:[i32] }:$ptr, anonymous_15037:{ *:[f32] }:$value, offset:{ *:[i32] }:$offset, 0:{ *:[i1] })
        GIR_BuildMI, /*InsnID*/0, /*Opcode*/GIMT_Encode2(AMDGPU::DS_MAX_F32_gfx9),
        GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/0, // ptr
        GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/2, // value
        GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/1, // offset
        GIR_AddImm8, /*InsnID*/0, /*Imm*/0,
        GIR_MergeMemOperands, /*InsnID*/0, /*NumInsns*/1, /*MergeInsnID's*/0,
        GIR_ConstrainSelectedInstOperands, /*InsnID*/0,
        GIR_EraseFromParent, /*InsnID*/0,
        // GIR_Coverage, 6979,
        GIR_Done,
      // Label 5650: @411478
      GIM_Try, /*On fail goto*//*Label 5651*/ GIMT_Encode4(411534), // Rule ID 6981 //
        GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasGDS),
        GIM_CheckMemoryAddressSpace, /*MI*/0, /*MMO*/0, /*NumAddrSpace*/1, /*AddrSpace*/2,
        GIM_CheckHasNoUse, /*MI*/0,
        GIM_CheckPointerToAny, /*MI*/0, /*Op*/1, /*SizeInBits*/0,
        GIM_CheckComplexPattern, /*MI*/0, /*Op*/1, /*Renderer*/GIMT_Encode2(0), GIMT_Encode2(GICP_gi_ds_1addr_1offset),
        // (atomic_load_fmax_glue:{ *:[f32] } (DS1Addr1Offset:{ *:[iPTR] } i32:{ *:[i32] }:$ptr, i32:{ *:[i32] }:$offset), f32:{ *:[f32] }:$value)<<P:Predicate_atomic_load_fmax_region_m0_noret_32>>  =>  (DS_MAX_F32 ?:{ *:[i32] }:$ptr, anonymous_15037:{ *:[f32] }:$value, offset:{ *:[i32] }:$offset, 1:{ *:[i1] })
        GIR_BuildMI, /*InsnID*/0, /*Opcode*/GIMT_Encode2(AMDGPU::DS_MAX_F32),
        GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/0, // ptr
        GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/2, // value
        GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/1, // offset
        GIR_AddImm8, /*InsnID*/0, /*Imm*/1,
        GIR_MergeMemOperands, /*InsnID*/0, /*NumInsns*/1, /*MergeInsnID's*/0,
        GIR_ConstrainSelectedInstOperands, /*InsnID*/0,
        GIR_EraseFromParent, /*InsnID*/0,
        // GIR_Coverage, 6981,
        GIR_Done,
      // Label 5651: @411534
      GIM_Try, /*On fail goto*//*Label 5652*/ GIMT_Encode4(411597), // Rule ID 6976 //
        GIM_CheckFeatures, GIMT_Encode2(GIFBS_LDSRequiresM0Init),
        GIM_CheckMemoryAddressSpace, /*MI*/0, /*MMO*/0, /*NumAddrSpace*/1, /*AddrSpace*/3,
        GIM_CheckRegBankForClass, /*MI*/0, /*Op*/0, /*RC*/GIMT_Encode2(AMDGPU::AV_32RegClassID),
        GIM_CheckPointerToAny, /*MI*/0, /*Op*/1, /*SizeInBits*/0,
        GIM_CheckComplexPattern, /*MI*/0, /*Op*/1, /*Renderer*/GIMT_Encode2(0), GIMT_Encode2(GICP_gi_ds_1addr_1offset),
        // (atomic_load_fmax_glue:{ *:[f32] } (DS1Addr1Offset:{ *:[iPTR] } i32:{ *:[i32] }:$ptr, i32:{ *:[i32] }:$offset), f32:{ *:[f32] }:$value)<<P:Predicate_atomic_load_fmax_local_m0_32>>  =>  (DS_MAX_RTN_F32:{ *:[f32] } ?:{ *:[i32] }:$ptr, anonymous_15037:{ *:[f32] }:$value, offset:{ *:[i32] }:$offset, 0:{ *:[i1] })
        GIR_BuildMI, /*InsnID*/0, /*Opcode*/GIMT_Encode2(AMDGPU::DS_MAX_RTN_F32),
        GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/0, // DstI[vdst]
        GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/0, // ptr
        GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/2, // value
        GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/1, // offset
        GIR_AddImm8, /*InsnID*/0, /*Imm*/0,
        GIR_MergeMemOperands, /*InsnID*/0, /*NumInsns*/1, /*MergeInsnID's*/0,
        GIR_ConstrainSelectedInstOperands, /*InsnID*/0,
        GIR_EraseFromParent, /*InsnID*/0,
        // GIR_Coverage, 6976,
        GIR_Done,
      // Label 5652: @411597
      GIM_Try, /*On fail goto*//*Label 5653*/ GIMT_Encode4(411660), // Rule ID 6978 //
        GIM_CheckFeatures, GIMT_Encode2(GIFBS_NotLDSRequiresM0Init),
        GIM_CheckMemoryAddressSpace, /*MI*/0, /*MMO*/0, /*NumAddrSpace*/1, /*AddrSpace*/3,
        GIM_CheckRegBankForClass, /*MI*/0, /*Op*/0, /*RC*/GIMT_Encode2(AMDGPU::AV_32RegClassID),
        GIM_CheckPointerToAny, /*MI*/0, /*Op*/1, /*SizeInBits*/0,
        GIM_CheckComplexPattern, /*MI*/0, /*Op*/1, /*Renderer*/GIMT_Encode2(0), GIMT_Encode2(GICP_gi_ds_1addr_1offset),
        // (SIatomic_fmax:{ *:[f32] } (DS1Addr1Offset:{ *:[iPTR] } i32:{ *:[i32] }:$ptr, i32:{ *:[i32] }:$offset), f32:{ *:[f32] }:$value)<<P:Predicate_atomic_load_fmax_local_32>>  =>  (DS_MAX_RTN_F32_gfx9:{ *:[f32] } ?:{ *:[i32] }:$ptr, anonymous_15037:{ *:[f32] }:$value, offset:{ *:[i32] }:$offset, 0:{ *:[i1] })
        GIR_BuildMI, /*InsnID*/0, /*Opcode*/GIMT_Encode2(AMDGPU::DS_MAX_RTN_F32_gfx9),
        GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/0, // DstI[vdst]
        GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/0, // ptr
        GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/2, // value
        GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/1, // offset
        GIR_AddImm8, /*InsnID*/0, /*Imm*/0,
        GIR_MergeMemOperands, /*InsnID*/0, /*NumInsns*/1, /*MergeInsnID's*/0,
        GIR_ConstrainSelectedInstOperands, /*InsnID*/0,
        GIR_EraseFromParent, /*InsnID*/0,
        // GIR_Coverage, 6978,
        GIR_Done,
      // Label 5653: @411660
      GIM_Try, /*On fail goto*//*Label 5654*/ GIMT_Encode4(411723), // Rule ID 6980 //
        GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasGDS),
        GIM_CheckMemoryAddressSpace, /*MI*/0, /*MMO*/0, /*NumAddrSpace*/1, /*AddrSpace*/2,
        GIM_CheckRegBankForClass, /*MI*/0, /*Op*/0, /*RC*/GIMT_Encode2(AMDGPU::AV_32RegClassID),
        GIM_CheckPointerToAny, /*MI*/0, /*Op*/1, /*SizeInBits*/0,
        GIM_CheckComplexPattern, /*MI*/0, /*Op*/1, /*Renderer*/GIMT_Encode2(0), GIMT_Encode2(GICP_gi_ds_1addr_1offset),
        // (atomic_load_fmax_glue:{ *:[f32] } (DS1Addr1Offset:{ *:[iPTR] } i32:{ *:[i32] }:$ptr, i32:{ *:[i32] }:$offset), f32:{ *:[f32] }:$value)<<P:Predicate_atomic_load_fmax_region_m0_32>>  =>  (DS_MAX_RTN_F32:{ *:[f32] } ?:{ *:[i32] }:$ptr, anonymous_15037:{ *:[f32] }:$value, offset:{ *:[i32] }:$offset, 1:{ *:[i1] })
        GIR_BuildMI, /*InsnID*/0, /*Opcode*/GIMT_Encode2(AMDGPU::DS_MAX_RTN_F32),
        GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/0, // DstI[vdst]
        GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/0, // ptr
        GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/2, // value
        GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/1, // offset
        GIR_AddImm8, /*InsnID*/0, /*Imm*/1,
        GIR_MergeMemOperands, /*InsnID*/0, /*NumInsns*/1, /*MergeInsnID's*/0,
        GIR_ConstrainSelectedInstOperands, /*InsnID*/0,
        GIR_EraseFromParent, /*InsnID*/0,
        // GIR_Coverage, 6980,
        GIR_Done,
      // Label 5654: @411723
      GIM_Try, /*On fail goto*//*Label 5655*/ GIMT_Encode4(411786), // Rule ID 3281 //
        GIM_CheckFeatures, GIMT_Encode2(GIFBS_isGFX10Plus),
        GIM_CheckMemoryAddressSpace, /*MI*/0, /*MMO*/0, /*NumAddrSpace*/3, /*AddrSpace*/1, /*AddrSpace*/4, /*AddrSpace*/6,
        GIM_CheckHasNoUse, /*MI*/0,
        GIM_CheckPointerToAny, /*MI*/0, /*Op*/1, /*SizeInBits*/0,
        GIM_CheckComplexPattern, /*MI*/0, /*Op*/1, /*Renderer*/GIMT_Encode2(0), GIMT_Encode2(GICP_gi_global_saddr),
        // (SIatomic_fmax:{ *:[f32] } (GlobalSAddr:{ *:[iPTR] } SReg_64:{ *:[i64] }:$saddr, VGPR_32:{ *:[i32] }:$voffset, i32:{ *:[i32] }:$offset), f32:{ *:[f32] }:$data)<<P:Predicate_atomic_load_fmax_global_noret_32>>  =>  (GLOBAL_ATOMIC_FMAX_SADDR ?:{ *:[i32] }:$voffset, anonymous_15037:{ *:[f32] }:$data, ?:{ *:[i64] }:$saddr, ?:{ *:[i32] }:$offset)
        GIR_BuildMI, /*InsnID*/0, /*Opcode*/GIMT_Encode2(AMDGPU::GLOBAL_ATOMIC_FMAX_SADDR),
        GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/1, // voffset
        GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/2, // data
        GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/0, // saddr
        GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/2, // offset
        GIR_AddImm8, /*InsnID*/0, /*Imm*/0,
        GIR_MergeMemOperands, /*InsnID*/0, /*NumInsns*/1, /*MergeInsnID's*/0,
        GIR_ConstrainSelectedInstOperands, /*InsnID*/0,
        GIR_EraseFromParent, /*InsnID*/0,
        // GIR_Coverage, 3281,
        GIR_Done,
      // Label 5655: @411786
      GIM_Try, /*On fail goto*//*Label 5656*/ GIMT_Encode4(411856), // Rule ID 3283 //
        GIM_CheckFeatures, GIMT_Encode2(GIFBS_isGFX10Plus),
        GIM_CheckMemoryAddressSpace, /*MI*/0, /*MMO*/0, /*NumAddrSpace*/3, /*AddrSpace*/1, /*AddrSpace*/4, /*AddrSpace*/6,
        GIM_CheckRegBankForClass, /*MI*/0, /*Op*/0, /*RC*/GIMT_Encode2(AMDGPU::AV_32RegClassID),
        GIM_CheckPointerToAny, /*MI*/0, /*Op*/1, /*SizeInBits*/0,
        GIM_CheckComplexPattern, /*MI*/0, /*Op*/1, /*Renderer*/GIMT_Encode2(0), GIMT_Encode2(GICP_gi_global_saddr),
        // (SIatomic_fmax:{ *:[f32] } (GlobalSAddr:{ *:[iPTR] } SReg_64:{ *:[i64] }:$saddr, VGPR_32:{ *:[i32] }:$voffset, i32:{ *:[i32] }:$offset), f32:{ *:[f32] }:$data)<<P:Predicate_atomic_load_fmax_global_32>>  =>  (GLOBAL_ATOMIC_FMAX_SADDR_RTN:{ *:[f32] } ?:{ *:[i32] }:$voffset, anonymous_15037:{ *:[f32] }:$data, ?:{ *:[i64] }:$saddr, ?:{ *:[i32] }:$offset)
        GIR_BuildMI, /*InsnID*/0, /*Opcode*/GIMT_Encode2(AMDGPU::GLOBAL_ATOMIC_FMAX_SADDR_RTN),
        GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/0, // DstI[vdst]
        GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/1, // voffset
        GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/2, // data
        GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/0, // saddr
        GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/2, // offset
        GIR_AddImm8, /*InsnID*/0, /*Imm*/1,
        GIR_MergeMemOperands, /*InsnID*/0, /*NumInsns*/1, /*MergeInsnID's*/0,
        GIR_ConstrainSelectedInstOperands, /*InsnID*/0,
        GIR_EraseFromParent, /*InsnID*/0,
        // GIR_Coverage, 3283,
        GIR_Done,
      // Label 5656: @411856
      GIM_Try, /*On fail goto*//*Label 5657*/ GIMT_Encode4(411914), // Rule ID 3280 //
        GIM_CheckFeatures, GIMT_Encode2(GIFBS_isGFX10Plus),
        GIM_CheckMemoryAddressSpace, /*MI*/0, /*MMO*/0, /*NumAddrSpace*/3, /*AddrSpace*/1, /*AddrSpace*/4, /*AddrSpace*/6,
        GIM_CheckHasNoUse, /*MI*/0,
        GIM_CheckPointerToAny, /*MI*/0, /*Op*/1, /*SizeInBits*/0,
        GIM_CheckComplexPattern, /*MI*/0, /*Op*/1, /*Renderer*/GIMT_Encode2(0), GIMT_Encode2(GICP_gi_global_offset),
        // (SIatomic_fmax:{ *:[f32] } (GlobalOffset:{ *:[iPTR] } i64:{ *:[i64] }:$vaddr, i32:{ *:[i32] }:$offset), f32:{ *:[f32] }:$data)<<P:Predicate_atomic_load_fmax_global_noret_32>>  =>  (GLOBAL_ATOMIC_FMAX VReg_64:{ *:[i64] }:$vaddr, anonymous_15037:{ *:[f32] }:$data, ?:{ *:[i32] }:$offset)
        GIR_BuildMI, /*InsnID*/0, /*Opcode*/GIMT_Encode2(AMDGPU::GLOBAL_ATOMIC_FMAX),
        GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/0, // vaddr
        GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/2, // data
        GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/1, // offset
        GIR_AddImm8, /*InsnID*/0, /*Imm*/0,
        GIR_MergeMemOperands, /*InsnID*/0, /*NumInsns*/1, /*MergeInsnID's*/0,
        GIR_ConstrainSelectedInstOperands, /*InsnID*/0,
        GIR_EraseFromParent, /*InsnID*/0,
        // GIR_Coverage, 3280,
        GIR_Done,
      // Label 5657: @411914
      GIM_Try, /*On fail goto*//*Label 5658*/ GIMT_Encode4(411979), // Rule ID 3282 //
        GIM_CheckFeatures, GIMT_Encode2(GIFBS_isGFX10Plus),
        GIM_CheckMemoryAddressSpace, /*MI*/0, /*MMO*/0, /*NumAddrSpace*/3, /*AddrSpace*/1, /*AddrSpace*/4, /*AddrSpace*/6,
        GIM_CheckRegBankForClass, /*MI*/0, /*Op*/0, /*RC*/GIMT_Encode2(AMDGPU::AV_32RegClassID),
        GIM_CheckPointerToAny, /*MI*/0, /*Op*/1, /*SizeInBits*/0,
        GIM_CheckComplexPattern, /*MI*/0, /*Op*/1, /*Renderer*/GIMT_Encode2(0), GIMT_Encode2(GICP_gi_global_offset),
        // (SIatomic_fmax:{ *:[f32] } (GlobalOffset:{ *:[iPTR] } i64:{ *:[i64] }:$vaddr, i32:{ *:[i32] }:$offset), f32:{ *:[f32] }:$data)<<P:Predicate_atomic_load_fmax_global_32>>  =>  (GLOBAL_ATOMIC_FMAX_RTN:{ *:[f32] } VReg_64:{ *:[i64] }:$vaddr, anonymous_15037:{ *:[f32] }:$data, ?:{ *:[i32] }:$offset)
        GIR_BuildMI, /*InsnID*/0, /*Opcode*/GIMT_Encode2(AMDGPU::GLOBAL_ATOMIC_FMAX_RTN),
        GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/0, // DstI[vdst]
        GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/0, // vaddr
        GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/2, // data
        GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/1, // offset
        GIR_AddImm8, /*InsnID*/0, /*Imm*/1,
        GIR_MergeMemOperands, /*InsnID*/0, /*NumInsns*/1, /*MergeInsnID's*/0,
        GIR_ConstrainSelectedInstOperands, /*InsnID*/0,
        GIR_EraseFromParent, /*InsnID*/0,
        // GIR_Coverage, 3282,
        GIR_Done,
      // Label 5658: @411979
      GIM_Try, /*On fail goto*//*Label 5659*/ GIMT_Encode4(412038), // Rule ID 3285 //
        GIM_CheckFeatures, GIMT_Encode2(GIFBS_isGFX10Plus),
        GIM_CheckMemoryAddressSpace, /*MI*/0, /*MMO*/0, /*NumAddrSpace*/4, /*AddrSpace*/0, /*AddrSpace*/1, /*AddrSpace*/4, /*AddrSpace*/6,
        GIM_CheckHasNoUse, /*MI*/0,
        GIM_CheckPointerToAny, /*MI*/0, /*Op*/1, /*SizeInBits*/0,
        GIM_CheckComplexPattern, /*MI*/0, /*Op*/1, /*Renderer*/GIMT_Encode2(0), GIMT_Encode2(GICP_gi_global_offset),
        // (SIatomic_fmax:{ *:[f32] } (GlobalOffset:{ *:[iPTR] } i64:{ *:[i64] }:$vaddr, i32:{ *:[i32] }:$offset), f32:{ *:[f32] }:$data)<<P:Predicate_atomic_load_fmax_flat_noret_32>>  =>  (FLAT_ATOMIC_FMAX VReg_64:{ *:[i64] }:$vaddr, anonymous_15037:{ *:[f32] }:$data, ?:{ *:[i32] }:$offset)
        GIR_BuildMI, /*InsnID*/0, /*Opcode*/GIMT_Encode2(AMDGPU::FLAT_ATOMIC_FMAX),
        GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/0, // vaddr
        GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/2, // data
        GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/1, // offset
        GIR_AddImm8, /*InsnID*/0, /*Imm*/0,
        GIR_MergeMemOperands, /*InsnID*/0, /*NumInsns*/1, /*MergeInsnID's*/0,
        GIR_ConstrainSelectedInstOperands, /*InsnID*/0,
        GIR_EraseFromParent, /*InsnID*/0,
        // GIR_Coverage, 3285,
        GIR_Done,
      // Label 5659: @412038
      GIM_Try, /*On fail goto*//*Label 5660*/ GIMT_Encode4(412104), // Rule ID 3284 //
        GIM_CheckFeatures, GIMT_Encode2(GIFBS_isGFX10Plus),
        GIM_CheckMemoryAddressSpace, /*MI*/0, /*MMO*/0, /*NumAddrSpace*/4, /*AddrSpace*/0, /*AddrSpace*/1, /*AddrSpace*/4, /*AddrSpace*/6,
        GIM_CheckRegBankForClass, /*MI*/0, /*Op*/0, /*RC*/GIMT_Encode2(AMDGPU::AV_32RegClassID),
        GIM_CheckPointerToAny, /*MI*/0, /*Op*/1, /*SizeInBits*/0,
        GIM_CheckComplexPattern, /*MI*/0, /*Op*/1, /*Renderer*/GIMT_Encode2(0), GIMT_Encode2(GICP_gi_global_offset),
        // (SIatomic_fmax:{ *:[f32] } (GlobalOffset:{ *:[iPTR] } i64:{ *:[i64] }:$vaddr, i32:{ *:[i32] }:$offset), f32:{ *:[f32] }:$data)<<P:Predicate_atomic_load_fmax_flat_32>>  =>  (FLAT_ATOMIC_FMAX_RTN:{ *:[f32] } VReg_64:{ *:[i64] }:$vaddr, anonymous_15037:{ *:[f32] }:$data, ?:{ *:[i32] }:$offset)
        GIR_BuildMI, /*InsnID*/0, /*Opcode*/GIMT_Encode2(AMDGPU::FLAT_ATOMIC_FMAX_RTN),
        GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/0, // DstI[vdst]
        GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/0, // vaddr
        GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/2, // data
        GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/1, // offset
        GIR_AddImm8, /*InsnID*/0, /*Imm*/1,
        GIR_MergeMemOperands, /*InsnID*/0, /*NumInsns*/1, /*MergeInsnID's*/0,
        GIR_ConstrainSelectedInstOperands, /*InsnID*/0,
        GIR_EraseFromParent, /*InsnID*/0,
        // GIR_Coverage, 3284,
        GIR_Done,
      // Label 5660: @412104
      GIM_Reject,
    // Label 5648: @412105
    GIM_Reject,
    // Label 5646: @412106
    GIM_Try, /*On fail goto*//*Label 5661*/ GIMT_Encode4(413235),
      GIM_CheckType, /*MI*/0, /*Op*/2, /*Type*/GILLT_s64,
      GIM_Try, /*On fail goto*//*Label 5662*/ GIMT_Encode4(412171), // Rule ID 7064 //
        GIM_CheckFeatures, GIMT_Encode2(GIFBS_LDSRequiresM0Init),
        GIM_CheckMemoryAddressSpace, /*MI*/0, /*MMO*/0, /*NumAddrSpace*/1, /*AddrSpace*/3,
        GIM_CheckHasNoUse, /*MI*/0,
        GIM_CheckPointerToAny, /*MI*/0, /*Op*/1, /*SizeInBits*/0,
        GIM_CheckComplexPattern, /*MI*/0, /*Op*/1, /*Renderer*/GIMT_Encode2(0), GIMT_Encode2(GICP_gi_ds_1addr_1offset),
        // (atomic_load_fmax_glue:{ *:[f64] } (DS1Addr1Offset:{ *:[iPTR] } i32:{ *:[i32] }:$ptr, i32:{ *:[i32] }:$offset), f64:{ *:[f64] }:$value)<<P:Predicate_atomic_load_fmax_local_m0_noret_64>>  =>  (DS_MAX_F64 ?:{ *:[i32] }:$ptr, anonymous_15036:{ *:[f64] }:$value, offset:{ *:[i32] }:$offset, 0:{ *:[i1] })
        GIR_BuildMI, /*InsnID*/0, /*Opcode*/GIMT_Encode2(AMDGPU::DS_MAX_F64),
        GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/0, // ptr
        GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/2, // value
        GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/1, // offset
        GIR_AddImm8, /*InsnID*/0, /*Imm*/0,
        GIR_MergeMemOperands, /*InsnID*/0, /*NumInsns*/1, /*MergeInsnID's*/0,
        GIR_ConstrainSelectedInstOperands, /*InsnID*/0,
        GIR_EraseFromParent, /*InsnID*/0,
        // GIR_Coverage, 7064,
        GIR_Done,
      // Label 5662: @412171
      GIM_Try, /*On fail goto*//*Label 5663*/ GIMT_Encode4(412227), // Rule ID 7066 //
        GIM_CheckFeatures, GIMT_Encode2(GIFBS_NotLDSRequiresM0Init),
        GIM_CheckMemoryAddressSpace, /*MI*/0, /*MMO*/0, /*NumAddrSpace*/1, /*AddrSpace*/3,
        GIM_CheckHasNoUse, /*MI*/0,
        GIM_CheckPointerToAny, /*MI*/0, /*Op*/1, /*SizeInBits*/0,
        GIM_CheckComplexPattern, /*MI*/0, /*Op*/1, /*Renderer*/GIMT_Encode2(0), GIMT_Encode2(GICP_gi_ds_1addr_1offset),
        // (SIatomic_fmax:{ *:[f64] } (DS1Addr1Offset:{ *:[iPTR] } i32:{ *:[i32] }:$ptr, i32:{ *:[i32] }:$offset), f64:{ *:[f64] }:$value)<<P:Predicate_atomic_load_fmax_local_noret_64>>  =>  (DS_MAX_F64_gfx9 ?:{ *:[i32] }:$ptr, anonymous_15036:{ *:[f64] }:$value, offset:{ *:[i32] }:$offset, 0:{ *:[i1] })
        GIR_BuildMI, /*InsnID*/0, /*Opcode*/GIMT_Encode2(AMDGPU::DS_MAX_F64_gfx9),
        GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/0, // ptr
        GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/2, // value
        GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/1, // offset
        GIR_AddImm8, /*InsnID*/0, /*Imm*/0,
        GIR_MergeMemOperands, /*InsnID*/0, /*NumInsns*/1, /*MergeInsnID's*/0,
        GIR_ConstrainSelectedInstOperands, /*InsnID*/0,
        GIR_EraseFromParent, /*InsnID*/0,
        // GIR_Coverage, 7066,
        GIR_Done,
      // Label 5663: @412227
      GIM_Try, /*On fail goto*//*Label 5664*/ GIMT_Encode4(412283), // Rule ID 7068 //
        GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasGDS),
        GIM_CheckMemoryAddressSpace, /*MI*/0, /*MMO*/0, /*NumAddrSpace*/1, /*AddrSpace*/2,
        GIM_CheckHasNoUse, /*MI*/0,
        GIM_CheckPointerToAny, /*MI*/0, /*Op*/1, /*SizeInBits*/0,
        GIM_CheckComplexPattern, /*MI*/0, /*Op*/1, /*Renderer*/GIMT_Encode2(0), GIMT_Encode2(GICP_gi_ds_1addr_1offset),
        // (atomic_load_fmax_glue:{ *:[f64] } (DS1Addr1Offset:{ *:[iPTR] } i32:{ *:[i32] }:$ptr, i32:{ *:[i32] }:$offset), f64:{ *:[f64] }:$value)<<P:Predicate_atomic_load_fmax_region_m0_noret_64>>  =>  (DS_MAX_F64 ?:{ *:[i32] }:$ptr, anonymous_15036:{ *:[f64] }:$value, offset:{ *:[i32] }:$offset, 1:{ *:[i1] })
        GIR_BuildMI, /*InsnID*/0, /*Opcode*/GIMT_Encode2(AMDGPU::DS_MAX_F64),
        GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/0, // ptr
        GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/2, // value
        GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/1, // offset
        GIR_AddImm8, /*InsnID*/0, /*Imm*/1,
        GIR_MergeMemOperands, /*InsnID*/0, /*NumInsns*/1, /*MergeInsnID's*/0,
        GIR_ConstrainSelectedInstOperands, /*InsnID*/0,
        GIR_EraseFromParent, /*InsnID*/0,
        // GIR_Coverage, 7068,
        GIR_Done,
      // Label 5664: @412283
      GIM_Try, /*On fail goto*//*Label 5665*/ GIMT_Encode4(412346), // Rule ID 7063 //
        GIM_CheckFeatures, GIMT_Encode2(GIFBS_LDSRequiresM0Init),
        GIM_CheckMemoryAddressSpace, /*MI*/0, /*MMO*/0, /*NumAddrSpace*/1, /*AddrSpace*/3,
        GIM_CheckRegBankForClass, /*MI*/0, /*Op*/0, /*RC*/GIMT_Encode2(AMDGPU::AV_64RegClassID),
        GIM_CheckPointerToAny, /*MI*/0, /*Op*/1, /*SizeInBits*/0,
        GIM_CheckComplexPattern, /*MI*/0, /*Op*/1, /*Renderer*/GIMT_Encode2(0), GIMT_Encode2(GICP_gi_ds_1addr_1offset),
        // (atomic_load_fmax_glue:{ *:[f64] } (DS1Addr1Offset:{ *:[iPTR] } i32:{ *:[i32] }:$ptr, i32:{ *:[i32] }:$offset), f64:{ *:[f64] }:$value)<<P:Predicate_atomic_load_fmax_local_m0_64>>  =>  (DS_MAX_RTN_F64:{ *:[f64] } ?:{ *:[i32] }:$ptr, anonymous_15036:{ *:[f64] }:$value, offset:{ *:[i32] }:$offset, 0:{ *:[i1] })
        GIR_BuildMI, /*InsnID*/0, /*Opcode*/GIMT_Encode2(AMDGPU::DS_MAX_RTN_F64),
        GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/0, // DstI[vdst]
        GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/0, // ptr
        GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/2, // value
        GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/1, // offset
        GIR_AddImm8, /*InsnID*/0, /*Imm*/0,
        GIR_MergeMemOperands, /*InsnID*/0, /*NumInsns*/1, /*MergeInsnID's*/0,
        GIR_ConstrainSelectedInstOperands, /*InsnID*/0,
        GIR_EraseFromParent, /*InsnID*/0,
        // GIR_Coverage, 7063,
        GIR_Done,
      // Label 5665: @412346
      GIM_Try, /*On fail goto*//*Label 5666*/ GIMT_Encode4(412409), // Rule ID 7065 //
        GIM_CheckFeatures, GIMT_Encode2(GIFBS_NotLDSRequiresM0Init),
        GIM_CheckMemoryAddressSpace, /*MI*/0, /*MMO*/0, /*NumAddrSpace*/1, /*AddrSpace*/3,
        GIM_CheckRegBankForClass, /*MI*/0, /*Op*/0, /*RC*/GIMT_Encode2(AMDGPU::AV_64RegClassID),
        GIM_CheckPointerToAny, /*MI*/0, /*Op*/1, /*SizeInBits*/0,
        GIM_CheckComplexPattern, /*MI*/0, /*Op*/1, /*Renderer*/GIMT_Encode2(0), GIMT_Encode2(GICP_gi_ds_1addr_1offset),
        // (SIatomic_fmax:{ *:[f64] } (DS1Addr1Offset:{ *:[iPTR] } i32:{ *:[i32] }:$ptr, i32:{ *:[i32] }:$offset), f64:{ *:[f64] }:$value)<<P:Predicate_atomic_load_fmax_local_64>>  =>  (DS_MAX_RTN_F64_gfx9:{ *:[f64] } ?:{ *:[i32] }:$ptr, anonymous_15036:{ *:[f64] }:$value, offset:{ *:[i32] }:$offset, 0:{ *:[i1] })
        GIR_BuildMI, /*InsnID*/0, /*Opcode*/GIMT_Encode2(AMDGPU::DS_MAX_RTN_F64_gfx9),
        GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/0, // DstI[vdst]
        GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/0, // ptr
        GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/2, // value
        GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/1, // offset
        GIR_AddImm8, /*InsnID*/0, /*Imm*/0,
        GIR_MergeMemOperands, /*InsnID*/0, /*NumInsns*/1, /*MergeInsnID's*/0,
        GIR_ConstrainSelectedInstOperands, /*InsnID*/0,
        GIR_EraseFromParent, /*InsnID*/0,
        // GIR_Coverage, 7065,
        GIR_Done,
      // Label 5666: @412409
      GIM_Try, /*On fail goto*//*Label 5667*/ GIMT_Encode4(412472), // Rule ID 7067 //
        GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasGDS),
        GIM_CheckMemoryAddressSpace, /*MI*/0, /*MMO*/0, /*NumAddrSpace*/1, /*AddrSpace*/2,
        GIM_CheckRegBankForClass, /*MI*/0, /*Op*/0, /*RC*/GIMT_Encode2(AMDGPU::AV_64RegClassID),
        GIM_CheckPointerToAny, /*MI*/0, /*Op*/1, /*SizeInBits*/0,
        GIM_CheckComplexPattern, /*MI*/0, /*Op*/1, /*Renderer*/GIMT_Encode2(0), GIMT_Encode2(GICP_gi_ds_1addr_1offset),
        // (atomic_load_fmax_glue:{ *:[f64] } (DS1Addr1Offset:{ *:[iPTR] } i32:{ *:[i32] }:$ptr, i32:{ *:[i32] }:$offset), f64:{ *:[f64] }:$value)<<P:Predicate_atomic_load_fmax_region_m0_64>>  =>  (DS_MAX_RTN_F64:{ *:[f64] } ?:{ *:[i32] }:$ptr, anonymous_15036:{ *:[f64] }:$value, offset:{ *:[i32] }:$offset, 1:{ *:[i1] })
        GIR_BuildMI, /*InsnID*/0, /*Opcode*/GIMT_Encode2(AMDGPU::DS_MAX_RTN_F64),
        GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/0, // DstI[vdst]
        GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/0, // ptr
        GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/2, // value
        GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/1, // offset
        GIR_AddImm8, /*InsnID*/0, /*Imm*/1,
        GIR_MergeMemOperands, /*InsnID*/0, /*NumInsns*/1, /*MergeInsnID's*/0,
        GIR_ConstrainSelectedInstOperands, /*InsnID*/0,
        GIR_EraseFromParent, /*InsnID*/0,
        // GIR_Coverage, 7067,
        GIR_Done,
      // Label 5667: @412472
      GIM_Try, /*On fail goto*//*Label 5668*/ GIMT_Encode4(412535), // Rule ID 3303 //
        GIM_CheckFeatures, GIMT_Encode2(GIFBS_isGFX10Only),
        GIM_CheckMemoryAddressSpace, /*MI*/0, /*MMO*/0, /*NumAddrSpace*/3, /*AddrSpace*/1, /*AddrSpace*/4, /*AddrSpace*/6,
        GIM_CheckHasNoUse, /*MI*/0,
        GIM_CheckPointerToAny, /*MI*/0, /*Op*/1, /*SizeInBits*/0,
        GIM_CheckComplexPattern, /*MI*/0, /*Op*/1, /*Renderer*/GIMT_Encode2(0), GIMT_Encode2(GICP_gi_global_saddr),
        // (SIatomic_fmax:{ *:[f64] } (GlobalSAddr:{ *:[iPTR] } SReg_64:{ *:[i64] }:$saddr, VGPR_32:{ *:[i32] }:$voffset, i32:{ *:[i32] }:$offset), f64:{ *:[f64] }:$data)<<P:Predicate_atomic_load_fmax_global_noret_64>>  =>  (GLOBAL_ATOMIC_FMAX_X2_SADDR ?:{ *:[i32] }:$voffset, anonymous_15036:{ *:[f64] }:$data, ?:{ *:[i64] }:$saddr, ?:{ *:[i32] }:$offset)
        GIR_BuildMI, /*InsnID*/0, /*Opcode*/GIMT_Encode2(AMDGPU::GLOBAL_ATOMIC_FMAX_X2_SADDR),
        GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/1, // voffset
        GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/2, // data
        GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/0, // saddr
        GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/2, // offset
        GIR_AddImm8, /*InsnID*/0, /*Imm*/0,
        GIR_MergeMemOperands, /*InsnID*/0, /*NumInsns*/1, /*MergeInsnID's*/0,
        GIR_ConstrainSelectedInstOperands, /*InsnID*/0,
        GIR_EraseFromParent, /*InsnID*/0,
        // GIR_Coverage, 3303,
        GIR_Done,
      // Label 5668: @412535
      GIM_Try, /*On fail goto*//*Label 5669*/ GIMT_Encode4(412598), // Rule ID 3363 //
        GIM_CheckFeatures, GIMT_Encode2(GIFBS_isGFX90APlus),
        GIM_CheckMemoryAddressSpace, /*MI*/0, /*MMO*/0, /*NumAddrSpace*/3, /*AddrSpace*/1, /*AddrSpace*/4, /*AddrSpace*/6,
        GIM_CheckHasNoUse, /*MI*/0,
        GIM_CheckPointerToAny, /*MI*/0, /*Op*/1, /*SizeInBits*/0,
        GIM_CheckComplexPattern, /*MI*/0, /*Op*/1, /*Renderer*/GIMT_Encode2(0), GIMT_Encode2(GICP_gi_global_saddr),
        // (SIatomic_fmax:{ *:[f64] } (GlobalSAddr:{ *:[iPTR] } SReg_64:{ *:[i64] }:$saddr, VGPR_32:{ *:[i32] }:$voffset, i32:{ *:[i32] }:$offset), f64:{ *:[f64] }:$data)<<P:Predicate_atomic_load_fmax_global_noret_64>>  =>  (GLOBAL_ATOMIC_MAX_F64_SADDR ?:{ *:[i32] }:$voffset, anonymous_15036:{ *:[f64] }:$data, ?:{ *:[i64] }:$saddr, ?:{ *:[i32] }:$offset)
        GIR_BuildMI, /*InsnID*/0, /*Opcode*/GIMT_Encode2(AMDGPU::GLOBAL_ATOMIC_MAX_F64_SADDR),
        GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/1, // voffset
        GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/2, // data
        GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/0, // saddr
        GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/2, // offset
        GIR_AddImm8, /*InsnID*/0, /*Imm*/0,
        GIR_MergeMemOperands, /*InsnID*/0, /*NumInsns*/1, /*MergeInsnID's*/0,
        GIR_ConstrainSelectedInstOperands, /*InsnID*/0,
        GIR_EraseFromParent, /*InsnID*/0,
        // GIR_Coverage, 3363,
        GIR_Done,
      // Label 5669: @412598
      GIM_Try, /*On fail goto*//*Label 5670*/ GIMT_Encode4(412668), // Rule ID 3305 //
        GIM_CheckFeatures, GIMT_Encode2(GIFBS_isGFX10Only),
        GIM_CheckMemoryAddressSpace, /*MI*/0, /*MMO*/0, /*NumAddrSpace*/3, /*AddrSpace*/1, /*AddrSpace*/4, /*AddrSpace*/6,
        GIM_CheckRegBankForClass, /*MI*/0, /*Op*/0, /*RC*/GIMT_Encode2(AMDGPU::AV_64RegClassID),
        GIM_CheckPointerToAny, /*MI*/0, /*Op*/1, /*SizeInBits*/0,
        GIM_CheckComplexPattern, /*MI*/0, /*Op*/1, /*Renderer*/GIMT_Encode2(0), GIMT_Encode2(GICP_gi_global_saddr),
        // (SIatomic_fmax:{ *:[f64] } (GlobalSAddr:{ *:[iPTR] } SReg_64:{ *:[i64] }:$saddr, VGPR_32:{ *:[i32] }:$voffset, i32:{ *:[i32] }:$offset), f64:{ *:[f64] }:$data)<<P:Predicate_atomic_load_fmax_global_64>>  =>  (GLOBAL_ATOMIC_FMAX_X2_SADDR_RTN:{ *:[f64] } ?:{ *:[i32] }:$voffset, anonymous_15036:{ *:[f64] }:$data, ?:{ *:[i64] }:$saddr, ?:{ *:[i32] }:$offset)
        GIR_BuildMI, /*InsnID*/0, /*Opcode*/GIMT_Encode2(AMDGPU::GLOBAL_ATOMIC_FMAX_X2_SADDR_RTN),
        GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/0, // DstI[vdst]
        GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/1, // voffset
        GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/2, // data
        GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/0, // saddr
        GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/2, // offset
        GIR_AddImm8, /*InsnID*/0, /*Imm*/1,
        GIR_MergeMemOperands, /*InsnID*/0, /*NumInsns*/1, /*MergeInsnID's*/0,
        GIR_ConstrainSelectedInstOperands, /*InsnID*/0,
        GIR_EraseFromParent, /*InsnID*/0,
        // GIR_Coverage, 3305,
        GIR_Done,
      // Label 5670: @412668
      GIM_Try, /*On fail goto*//*Label 5671*/ GIMT_Encode4(412738), // Rule ID 3365 //
        GIM_CheckFeatures, GIMT_Encode2(GIFBS_isGFX90APlus),
        GIM_CheckMemoryAddressSpace, /*MI*/0, /*MMO*/0, /*NumAddrSpace*/3, /*AddrSpace*/1, /*AddrSpace*/4, /*AddrSpace*/6,
        GIM_CheckRegBankForClass, /*MI*/0, /*Op*/0, /*RC*/GIMT_Encode2(AMDGPU::AV_64RegClassID),
        GIM_CheckPointerToAny, /*MI*/0, /*Op*/1, /*SizeInBits*/0,
        GIM_CheckComplexPattern, /*MI*/0, /*Op*/1, /*Renderer*/GIMT_Encode2(0), GIMT_Encode2(GICP_gi_global_saddr),
        // (SIatomic_fmax:{ *:[f64] } (GlobalSAddr:{ *:[iPTR] } SReg_64:{ *:[i64] }:$saddr, VGPR_32:{ *:[i32] }:$voffset, i32:{ *:[i32] }:$offset), f64:{ *:[f64] }:$data)<<P:Predicate_atomic_load_fmax_global_64>>  =>  (GLOBAL_ATOMIC_MAX_F64_SADDR_RTN:{ *:[f64] } ?:{ *:[i32] }:$voffset, anonymous_15036:{ *:[f64] }:$data, ?:{ *:[i64] }:$saddr, ?:{ *:[i32] }:$offset)
        GIR_BuildMI, /*InsnID*/0, /*Opcode*/GIMT_Encode2(AMDGPU::GLOBAL_ATOMIC_MAX_F64_SADDR_RTN),
        GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/0, // DstI[vdst]
        GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/1, // voffset
        GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/2, // data
        GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/0, // saddr
        GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/2, // offset
        GIR_AddImm8, /*InsnID*/0, /*Imm*/1,
        GIR_MergeMemOperands, /*InsnID*/0, /*NumInsns*/1, /*MergeInsnID's*/0,
        GIR_ConstrainSelectedInstOperands, /*InsnID*/0,
        GIR_EraseFromParent, /*InsnID*/0,
        // GIR_Coverage, 3365,
        GIR_Done,
      // Label 5671: @412738
      GIM_Try, /*On fail goto*//*Label 5672*/ GIMT_Encode4(412796), // Rule ID 3302 //
        GIM_CheckFeatures, GIMT_Encode2(GIFBS_isGFX10Only),
        GIM_CheckMemoryAddressSpace, /*MI*/0, /*MMO*/0, /*NumAddrSpace*/3, /*AddrSpace*/1, /*AddrSpace*/4, /*AddrSpace*/6,
        GIM_CheckHasNoUse, /*MI*/0,
        GIM_CheckPointerToAny, /*MI*/0, /*Op*/1, /*SizeInBits*/0,
        GIM_CheckComplexPattern, /*MI*/0, /*Op*/1, /*Renderer*/GIMT_Encode2(0), GIMT_Encode2(GICP_gi_global_offset),
        // (SIatomic_fmax:{ *:[f64] } (GlobalOffset:{ *:[iPTR] } i64:{ *:[i64] }:$vaddr, i32:{ *:[i32] }:$offset), f64:{ *:[f64] }:$data)<<P:Predicate_atomic_load_fmax_global_noret_64>>  =>  (GLOBAL_ATOMIC_FMAX_X2 VReg_64:{ *:[i64] }:$vaddr, anonymous_15036:{ *:[f64] }:$data, ?:{ *:[i32] }:$offset)
        GIR_BuildMI, /*InsnID*/0, /*Opcode*/GIMT_Encode2(AMDGPU::GLOBAL_ATOMIC_FMAX_X2),
        GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/0, // vaddr
        GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/2, // data
        GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/1, // offset
        GIR_AddImm8, /*InsnID*/0, /*Imm*/0,
        GIR_MergeMemOperands, /*InsnID*/0, /*NumInsns*/1, /*MergeInsnID's*/0,
        GIR_ConstrainSelectedInstOperands, /*InsnID*/0,
        GIR_EraseFromParent, /*InsnID*/0,
        // GIR_Coverage, 3302,
        GIR_Done,
      // Label 5672: @412796
      GIM_Try, /*On fail goto*//*Label 5673*/ GIMT_Encode4(412854), // Rule ID 3362 //
        GIM_CheckFeatures, GIMT_Encode2(GIFBS_isGFX90APlus),
        GIM_CheckMemoryAddressSpace, /*MI*/0, /*MMO*/0, /*NumAddrSpace*/3, /*AddrSpace*/1, /*AddrSpace*/4, /*AddrSpace*/6,
        GIM_CheckHasNoUse, /*MI*/0,
        GIM_CheckPointerToAny, /*MI*/0, /*Op*/1, /*SizeInBits*/0,
        GIM_CheckComplexPattern, /*MI*/0, /*Op*/1, /*Renderer*/GIMT_Encode2(0), GIMT_Encode2(GICP_gi_global_offset),
        // (SIatomic_fmax:{ *:[f64] } (GlobalOffset:{ *:[iPTR] } i64:{ *:[i64] }:$vaddr, i32:{ *:[i32] }:$offset), f64:{ *:[f64] }:$data)<<P:Predicate_atomic_load_fmax_global_noret_64>>  =>  (GLOBAL_ATOMIC_MAX_F64 VReg_64:{ *:[i64] }:$vaddr, anonymous_15036:{ *:[f64] }:$data, ?:{ *:[i32] }:$offset)
        GIR_BuildMI, /*InsnID*/0, /*Opcode*/GIMT_Encode2(AMDGPU::GLOBAL_ATOMIC_MAX_F64),
        GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/0, // vaddr
        GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/2, // data
        GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/1, // offset
        GIR_AddImm8, /*InsnID*/0, /*Imm*/0,
        GIR_MergeMemOperands, /*InsnID*/0, /*NumInsns*/1, /*MergeInsnID's*/0,
        GIR_ConstrainSelectedInstOperands, /*InsnID*/0,
        GIR_EraseFromParent, /*InsnID*/0,
        // GIR_Coverage, 3362,
        GIR_Done,
      // Label 5673: @412854
      GIM_Try, /*On fail goto*//*Label 5674*/ GIMT_Encode4(412919), // Rule ID 3304 //
        GIM_CheckFeatures, GIMT_Encode2(GIFBS_isGFX10Only),
        GIM_CheckMemoryAddressSpace, /*MI*/0, /*MMO*/0, /*NumAddrSpace*/3, /*AddrSpace*/1, /*AddrSpace*/4, /*AddrSpace*/6,
        GIM_CheckRegBankForClass, /*MI*/0, /*Op*/0, /*RC*/GIMT_Encode2(AMDGPU::AV_64RegClassID),
        GIM_CheckPointerToAny, /*MI*/0, /*Op*/1, /*SizeInBits*/0,
        GIM_CheckComplexPattern, /*MI*/0, /*Op*/1, /*Renderer*/GIMT_Encode2(0), GIMT_Encode2(GICP_gi_global_offset),
        // (SIatomic_fmax:{ *:[f64] } (GlobalOffset:{ *:[iPTR] } i64:{ *:[i64] }:$vaddr, i32:{ *:[i32] }:$offset), f64:{ *:[f64] }:$data)<<P:Predicate_atomic_load_fmax_global_64>>  =>  (GLOBAL_ATOMIC_FMAX_X2_RTN:{ *:[f64] } VReg_64:{ *:[i64] }:$vaddr, anonymous_15036:{ *:[f64] }:$data, ?:{ *:[i32] }:$offset)
        GIR_BuildMI, /*InsnID*/0, /*Opcode*/GIMT_Encode2(AMDGPU::GLOBAL_ATOMIC_FMAX_X2_RTN),
        GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/0, // DstI[vdst]
        GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/0, // vaddr
        GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/2, // data
        GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/1, // offset
        GIR_AddImm8, /*InsnID*/0, /*Imm*/1,
        GIR_MergeMemOperands, /*InsnID*/0, /*NumInsns*/1, /*MergeInsnID's*/0,
        GIR_ConstrainSelectedInstOperands, /*InsnID*/0,
        GIR_EraseFromParent, /*InsnID*/0,
        // GIR_Coverage, 3304,
        GIR_Done,
      // Label 5674: @412919
      GIM_Try, /*On fail goto*//*Label 5675*/ GIMT_Encode4(412984), // Rule ID 3364 //
        GIM_CheckFeatures, GIMT_Encode2(GIFBS_isGFX90APlus),
        GIM_CheckMemoryAddressSpace, /*MI*/0, /*MMO*/0, /*NumAddrSpace*/3, /*AddrSpace*/1, /*AddrSpace*/4, /*AddrSpace*/6,
        GIM_CheckRegBankForClass, /*MI*/0, /*Op*/0, /*RC*/GIMT_Encode2(AMDGPU::AV_64RegClassID),
        GIM_CheckPointerToAny, /*MI*/0, /*Op*/1, /*SizeInBits*/0,
        GIM_CheckComplexPattern, /*MI*/0, /*Op*/1, /*Renderer*/GIMT_Encode2(0), GIMT_Encode2(GICP_gi_global_offset),
        // (SIatomic_fmax:{ *:[f64] } (GlobalOffset:{ *:[iPTR] } i64:{ *:[i64] }:$vaddr, i32:{ *:[i32] }:$offset), f64:{ *:[f64] }:$data)<<P:Predicate_atomic_load_fmax_global_64>>  =>  (GLOBAL_ATOMIC_MAX_F64_RTN:{ *:[f64] } VReg_64:{ *:[i64] }:$vaddr, anonymous_15036:{ *:[f64] }:$data, ?:{ *:[i32] }:$offset)
        GIR_BuildMI, /*InsnID*/0, /*Opcode*/GIMT_Encode2(AMDGPU::GLOBAL_ATOMIC_MAX_F64_RTN),
        GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/0, // DstI[vdst]
        GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/0, // vaddr
        GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/2, // data
        GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/1, // offset
        GIR_AddImm8, /*InsnID*/0, /*Imm*/1,
        GIR_MergeMemOperands, /*InsnID*/0, /*NumInsns*/1, /*MergeInsnID's*/0,
        GIR_ConstrainSelectedInstOperands, /*InsnID*/0,
        GIR_EraseFromParent, /*InsnID*/0,
        // GIR_Coverage, 3364,
        GIR_Done,
      // Label 5675: @412984
      GIM_Try, /*On fail goto*//*Label 5676*/ GIMT_Encode4(413043), // Rule ID 3317 //
        GIM_CheckFeatures, GIMT_Encode2(GIFBS_isGFX10Only),
        GIM_CheckMemoryAddressSpace, /*MI*/0, /*MMO*/0, /*NumAddrSpace*/4, /*AddrSpace*/0, /*AddrSpace*/1, /*AddrSpace*/4, /*AddrSpace*/6,
        GIM_CheckHasNoUse, /*MI*/0,
        GIM_CheckPointerToAny, /*MI*/0, /*Op*/1, /*SizeInBits*/0,
        GIM_CheckComplexPattern, /*MI*/0, /*Op*/1, /*Renderer*/GIMT_Encode2(0), GIMT_Encode2(GICP_gi_global_offset),
        // (SIatomic_fmax:{ *:[f64] } (GlobalOffset:{ *:[iPTR] } i64:{ *:[i64] }:$vaddr, i32:{ *:[i32] }:$offset), f64:{ *:[f64] }:$data)<<P:Predicate_atomic_load_fmax_flat_noret_64>>  =>  (FLAT_ATOMIC_FMAX_X2 VReg_64:{ *:[i64] }:$vaddr, anonymous_15036:{ *:[f64] }:$data, ?:{ *:[i32] }:$offset)
        GIR_BuildMI, /*InsnID*/0, /*Opcode*/GIMT_Encode2(AMDGPU::FLAT_ATOMIC_FMAX_X2),
        GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/0, // vaddr
        GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/2, // data
        GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/1, // offset
        GIR_AddImm8, /*InsnID*/0, /*Imm*/0,
        GIR_MergeMemOperands, /*InsnID*/0, /*NumInsns*/1, /*MergeInsnID's*/0,
        GIR_ConstrainSelectedInstOperands, /*InsnID*/0,
        GIR_EraseFromParent, /*InsnID*/0,
        // GIR_Coverage, 3317,
        GIR_Done,
      // Label 5676: @413043
      GIM_Try, /*On fail goto*//*Label 5677*/ GIMT_Encode4(413102), // Rule ID 3387 //
        GIM_CheckFeatures, GIMT_Encode2(GIFBS_isGFX90APlus),
        GIM_CheckMemoryAddressSpace, /*MI*/0, /*MMO*/0, /*NumAddrSpace*/4, /*AddrSpace*/0, /*AddrSpace*/1, /*AddrSpace*/4, /*AddrSpace*/6,
        GIM_CheckHasNoUse, /*MI*/0,
        GIM_CheckPointerToAny, /*MI*/0, /*Op*/1, /*SizeInBits*/0,
        GIM_CheckComplexPattern, /*MI*/0, /*Op*/1, /*Renderer*/GIMT_Encode2(0), GIMT_Encode2(GICP_gi_global_offset),
        // (SIatomic_fmax:{ *:[f64] } (GlobalOffset:{ *:[iPTR] } i64:{ *:[i64] }:$vaddr, i32:{ *:[i32] }:$offset), f64:{ *:[f64] }:$data)<<P:Predicate_atomic_load_fmax_flat_noret_64>>  =>  (FLAT_ATOMIC_MAX_F64 VReg_64:{ *:[i64] }:$vaddr, anonymous_15036:{ *:[f64] }:$data, ?:{ *:[i32] }:$offset)
        GIR_BuildMI, /*InsnID*/0, /*Opcode*/GIMT_Encode2(AMDGPU::FLAT_ATOMIC_MAX_F64),
        GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/0, // vaddr
        GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/2, // data
        GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/1, // offset
        GIR_AddImm8, /*InsnID*/0, /*Imm*/0,
        GIR_MergeMemOperands, /*InsnID*/0, /*NumInsns*/1, /*MergeInsnID's*/0,
        GIR_ConstrainSelectedInstOperands, /*InsnID*/0,
        GIR_EraseFromParent, /*InsnID*/0,
        // GIR_Coverage, 3387,
        GIR_Done,
      // Label 5677: @413102
      GIM_Try, /*On fail goto*//*Label 5678*/ GIMT_Encode4(413168), // Rule ID 3316 //
        GIM_CheckFeatures, GIMT_Encode2(GIFBS_isGFX10Only),
        GIM_CheckMemoryAddressSpace, /*MI*/0, /*MMO*/0, /*NumAddrSpace*/4, /*AddrSpace*/0, /*AddrSpace*/1, /*AddrSpace*/4, /*AddrSpace*/6,
        GIM_CheckRegBankForClass, /*MI*/0, /*Op*/0, /*RC*/GIMT_Encode2(AMDGPU::AV_64RegClassID),
        GIM_CheckPointerToAny, /*MI*/0, /*Op*/1, /*SizeInBits*/0,
        GIM_CheckComplexPattern, /*MI*/0, /*Op*/1, /*Renderer*/GIMT_Encode2(0), GIMT_Encode2(GICP_gi_global_offset),
        // (SIatomic_fmax:{ *:[f64] } (GlobalOffset:{ *:[iPTR] } i64:{ *:[i64] }:$vaddr, i32:{ *:[i32] }:$offset), f64:{ *:[f64] }:$data)<<P:Predicate_atomic_load_fmax_flat_64>>  =>  (FLAT_ATOMIC_FMAX_X2_RTN:{ *:[f64] } VReg_64:{ *:[i64] }:$vaddr, anonymous_15036:{ *:[f64] }:$data, ?:{ *:[i32] }:$offset)
        GIR_BuildMI, /*InsnID*/0, /*Opcode*/GIMT_Encode2(AMDGPU::FLAT_ATOMIC_FMAX_X2_RTN),
        GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/0, // DstI[vdst]
        GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/0, // vaddr
        GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/2, // data
        GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/1, // offset
        GIR_AddImm8, /*InsnID*/0, /*Imm*/1,
        GIR_MergeMemOperands, /*InsnID*/0, /*NumInsns*/1, /*MergeInsnID's*/0,
        GIR_ConstrainSelectedInstOperands, /*InsnID*/0,
        GIR_EraseFromParent, /*InsnID*/0,
        // GIR_Coverage, 3316,
        GIR_Done,
      // Label 5678: @413168
      GIM_Try, /*On fail goto*//*Label 5679*/ GIMT_Encode4(413234), // Rule ID 3386 //
        GIM_CheckFeatures, GIMT_Encode2(GIFBS_isGFX90APlus),
        GIM_CheckMemoryAddressSpace, /*MI*/0, /*MMO*/0, /*NumAddrSpace*/4, /*AddrSpace*/0, /*AddrSpace*/1, /*AddrSpace*/4, /*AddrSpace*/6,
        GIM_CheckRegBankForClass, /*MI*/0, /*Op*/0, /*RC*/GIMT_Encode2(AMDGPU::AV_64RegClassID),
        GIM_CheckPointerToAny, /*MI*/0, /*Op*/1, /*SizeInBits*/0,
        GIM_CheckComplexPattern, /*MI*/0, /*Op*/1, /*Renderer*/GIMT_Encode2(0), GIMT_Encode2(GICP_gi_global_offset),
        // (SIatomic_fmax:{ *:[f64] } (GlobalOffset:{ *:[iPTR] } i64:{ *:[i64] }:$vaddr, i32:{ *:[i32] }:$offset), f64:{ *:[f64] }:$data)<<P:Predicate_atomic_load_fmax_flat_64>>  =>  (FLAT_ATOMIC_MAX_F64_RTN:{ *:[f64] } VReg_64:{ *:[i64] }:$vaddr, anonymous_15036:{ *:[f64] }:$data, ?:{ *:[i32] }:$offset)
        GIR_BuildMI, /*InsnID*/0, /*Opcode*/GIMT_Encode2(AMDGPU::FLAT_ATOMIC_MAX_F64_RTN),
        GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/0, // DstI[vdst]
        GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/0, // vaddr
        GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/2, // data
        GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/1, // offset
        GIR_AddImm8, /*InsnID*/0, /*Imm*/1,
        GIR_MergeMemOperands, /*InsnID*/0, /*NumInsns*/1, /*MergeInsnID's*/0,
        GIR_ConstrainSelectedInstOperands, /*InsnID*/0,
        GIR_EraseFromParent, /*InsnID*/0,
        // GIR_Coverage, 3386,
        GIR_Done,
      // Label 5679: @413234
      GIM_Reject,
    // Label 5661: @413235
    GIM_Reject,
    // Label 5647: @413236
    GIM_Reject,
    // Label 105: @413237
    GIM_SwitchType, /*MI*/0, /*Op*/0, /*[*/GIMT_Encode2(9), GIMT_Encode2(11), /*)*//*default:*//*Label 5682*/ GIMT_Encode4(415135),
    /*GILLT_s32*//*Label 5680*/ GIMT_Encode4(413256),
    /*GILLT_s64*//*Label 5681*/ GIMT_Encode4(414005),
    // Label 5680: @413256
    GIM_Try, /*On fail goto*//*Label 5683*/ GIMT_Encode4(414004),
      GIM_CheckType, /*MI*/0, /*Op*/2, /*Type*/GILLT_s32,
      GIM_Try, /*On fail goto*//*Label 5684*/ GIMT_Encode4(413321), // Rule ID 6971 //
        GIM_CheckFeatures, GIMT_Encode2(GIFBS_LDSRequiresM0Init),
        GIM_CheckMemoryAddressSpace, /*MI*/0, /*MMO*/0, /*NumAddrSpace*/1, /*AddrSpace*/3,
        GIM_CheckHasNoUse, /*MI*/0,
        GIM_CheckPointerToAny, /*MI*/0, /*Op*/1, /*SizeInBits*/0,
        GIM_CheckComplexPattern, /*MI*/0, /*Op*/1, /*Renderer*/GIMT_Encode2(0), GIMT_Encode2(GICP_gi_ds_1addr_1offset),
        // (atomic_load_fmin_glue:{ *:[f32] } (DS1Addr1Offset:{ *:[iPTR] } i32:{ *:[i32] }:$ptr, i32:{ *:[i32] }:$offset), f32:{ *:[f32] }:$value)<<P:Predicate_atomic_load_fmin_local_m0_noret_32>>  =>  (DS_MIN_F32 ?:{ *:[i32] }:$ptr, anonymous_15037:{ *:[f32] }:$value, offset:{ *:[i32] }:$offset, 0:{ *:[i1] })
        GIR_BuildMI, /*InsnID*/0, /*Opcode*/GIMT_Encode2(AMDGPU::DS_MIN_F32),
        GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/0, // ptr
        GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/2, // value
        GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/1, // offset
        GIR_AddImm8, /*InsnID*/0, /*Imm*/0,
        GIR_MergeMemOperands, /*InsnID*/0, /*NumInsns*/1, /*MergeInsnID's*/0,
        GIR_ConstrainSelectedInstOperands, /*InsnID*/0,
        GIR_EraseFromParent, /*InsnID*/0,
        // GIR_Coverage, 6971,
        GIR_Done,
      // Label 5684: @413321
      GIM_Try, /*On fail goto*//*Label 5685*/ GIMT_Encode4(413377), // Rule ID 6973 //
        GIM_CheckFeatures, GIMT_Encode2(GIFBS_NotLDSRequiresM0Init),
        GIM_CheckMemoryAddressSpace, /*MI*/0, /*MMO*/0, /*NumAddrSpace*/1, /*AddrSpace*/3,
        GIM_CheckHasNoUse, /*MI*/0,
        GIM_CheckPointerToAny, /*MI*/0, /*Op*/1, /*SizeInBits*/0,
        GIM_CheckComplexPattern, /*MI*/0, /*Op*/1, /*Renderer*/GIMT_Encode2(0), GIMT_Encode2(GICP_gi_ds_1addr_1offset),
        // (SIatomic_fmin:{ *:[f32] } (DS1Addr1Offset:{ *:[iPTR] } i32:{ *:[i32] }:$ptr, i32:{ *:[i32] }:$offset), f32:{ *:[f32] }:$value)<<P:Predicate_atomic_load_fmin_local_noret_32>>  =>  (DS_MIN_F32_gfx9 ?:{ *:[i32] }:$ptr, anonymous_15037:{ *:[f32] }:$value, offset:{ *:[i32] }:$offset, 0:{ *:[i1] })
        GIR_BuildMI, /*InsnID*/0, /*Opcode*/GIMT_Encode2(AMDGPU::DS_MIN_F32_gfx9),
        GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/0, // ptr
        GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/2, // value
        GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/1, // offset
        GIR_AddImm8, /*InsnID*/0, /*Imm*/0,
        GIR_MergeMemOperands, /*InsnID*/0, /*NumInsns*/1, /*MergeInsnID's*/0,
        GIR_ConstrainSelectedInstOperands, /*InsnID*/0,
        GIR_EraseFromParent, /*InsnID*/0,
        // GIR_Coverage, 6973,
        GIR_Done,
      // Label 5685: @413377
      GIM_Try, /*On fail goto*//*Label 5686*/ GIMT_Encode4(413433), // Rule ID 6975 //
        GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasGDS),
        GIM_CheckMemoryAddressSpace, /*MI*/0, /*MMO*/0, /*NumAddrSpace*/1, /*AddrSpace*/2,
        GIM_CheckHasNoUse, /*MI*/0,
        GIM_CheckPointerToAny, /*MI*/0, /*Op*/1, /*SizeInBits*/0,
        GIM_CheckComplexPattern, /*MI*/0, /*Op*/1, /*Renderer*/GIMT_Encode2(0), GIMT_Encode2(GICP_gi_ds_1addr_1offset),
        // (atomic_load_fmin_glue:{ *:[f32] } (DS1Addr1Offset:{ *:[iPTR] } i32:{ *:[i32] }:$ptr, i32:{ *:[i32] }:$offset), f32:{ *:[f32] }:$value)<<P:Predicate_atomic_load_fmin_region_m0_noret_32>>  =>  (DS_MIN_F32 ?:{ *:[i32] }:$ptr, anonymous_15037:{ *:[f32] }:$value, offset:{ *:[i32] }:$offset, 1:{ *:[i1] })
        GIR_BuildMI, /*InsnID*/0, /*Opcode*/GIMT_Encode2(AMDGPU::DS_MIN_F32),
        GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/0, // ptr
        GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/2, // value
        GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/1, // offset
        GIR_AddImm8, /*InsnID*/0, /*Imm*/1,
        GIR_MergeMemOperands, /*InsnID*/0, /*NumInsns*/1, /*MergeInsnID's*/0,
        GIR_ConstrainSelectedInstOperands, /*InsnID*/0,
        GIR_EraseFromParent, /*InsnID*/0,
        // GIR_Coverage, 6975,
        GIR_Done,
      // Label 5686: @413433
      GIM_Try, /*On fail goto*//*Label 5687*/ GIMT_Encode4(413496), // Rule ID 6970 //
        GIM_CheckFeatures, GIMT_Encode2(GIFBS_LDSRequiresM0Init),
        GIM_CheckMemoryAddressSpace, /*MI*/0, /*MMO*/0, /*NumAddrSpace*/1, /*AddrSpace*/3,
        GIM_CheckRegBankForClass, /*MI*/0, /*Op*/0, /*RC*/GIMT_Encode2(AMDGPU::AV_32RegClassID),
        GIM_CheckPointerToAny, /*MI*/0, /*Op*/1, /*SizeInBits*/0,
        GIM_CheckComplexPattern, /*MI*/0, /*Op*/1, /*Renderer*/GIMT_Encode2(0), GIMT_Encode2(GICP_gi_ds_1addr_1offset),
        // (atomic_load_fmin_glue:{ *:[f32] } (DS1Addr1Offset:{ *:[iPTR] } i32:{ *:[i32] }:$ptr, i32:{ *:[i32] }:$offset), f32:{ *:[f32] }:$value)<<P:Predicate_atomic_load_fmin_local_m0_32>>  =>  (DS_MIN_RTN_F32:{ *:[f32] } ?:{ *:[i32] }:$ptr, anonymous_15037:{ *:[f32] }:$value, offset:{ *:[i32] }:$offset, 0:{ *:[i1] })
        GIR_BuildMI, /*InsnID*/0, /*Opcode*/GIMT_Encode2(AMDGPU::DS_MIN_RTN_F32),
        GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/0, // DstI[vdst]
        GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/0, // ptr
        GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/2, // value
        GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/1, // offset
        GIR_AddImm8, /*InsnID*/0, /*Imm*/0,
        GIR_MergeMemOperands, /*InsnID*/0, /*NumInsns*/1, /*MergeInsnID's*/0,
        GIR_ConstrainSelectedInstOperands, /*InsnID*/0,
        GIR_EraseFromParent, /*InsnID*/0,
        // GIR_Coverage, 6970,
        GIR_Done,
      // Label 5687: @413496
      GIM_Try, /*On fail goto*//*Label 5688*/ GIMT_Encode4(413559), // Rule ID 6972 //
        GIM_CheckFeatures, GIMT_Encode2(GIFBS_NotLDSRequiresM0Init),
        GIM_CheckMemoryAddressSpace, /*MI*/0, /*MMO*/0, /*NumAddrSpace*/1, /*AddrSpace*/3,
        GIM_CheckRegBankForClass, /*MI*/0, /*Op*/0, /*RC*/GIMT_Encode2(AMDGPU::AV_32RegClassID),
        GIM_CheckPointerToAny, /*MI*/0, /*Op*/1, /*SizeInBits*/0,
        GIM_CheckComplexPattern, /*MI*/0, /*Op*/1, /*Renderer*/GIMT_Encode2(0), GIMT_Encode2(GICP_gi_ds_1addr_1offset),
        // (SIatomic_fmin:{ *:[f32] } (DS1Addr1Offset:{ *:[iPTR] } i32:{ *:[i32] }:$ptr, i32:{ *:[i32] }:$offset), f32:{ *:[f32] }:$value)<<P:Predicate_atomic_load_fmin_local_32>>  =>  (DS_MIN_RTN_F32_gfx9:{ *:[f32] } ?:{ *:[i32] }:$ptr, anonymous_15037:{ *:[f32] }:$value, offset:{ *:[i32] }:$offset, 0:{ *:[i1] })
        GIR_BuildMI, /*InsnID*/0, /*Opcode*/GIMT_Encode2(AMDGPU::DS_MIN_RTN_F32_gfx9),
        GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/0, // DstI[vdst]
        GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/0, // ptr
        GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/2, // value
        GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/1, // offset
        GIR_AddImm8, /*InsnID*/0, /*Imm*/0,
        GIR_MergeMemOperands, /*InsnID*/0, /*NumInsns*/1, /*MergeInsnID's*/0,
        GIR_ConstrainSelectedInstOperands, /*InsnID*/0,
        GIR_EraseFromParent, /*InsnID*/0,
        // GIR_Coverage, 6972,
        GIR_Done,
      // Label 5688: @413559
      GIM_Try, /*On fail goto*//*Label 5689*/ GIMT_Encode4(413622), // Rule ID 6974 //
        GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasGDS),
        GIM_CheckMemoryAddressSpace, /*MI*/0, /*MMO*/0, /*NumAddrSpace*/1, /*AddrSpace*/2,
        GIM_CheckRegBankForClass, /*MI*/0, /*Op*/0, /*RC*/GIMT_Encode2(AMDGPU::AV_32RegClassID),
        GIM_CheckPointerToAny, /*MI*/0, /*Op*/1, /*SizeInBits*/0,
        GIM_CheckComplexPattern, /*MI*/0, /*Op*/1, /*Renderer*/GIMT_Encode2(0), GIMT_Encode2(GICP_gi_ds_1addr_1offset),
        // (atomic_load_fmin_glue:{ *:[f32] } (DS1Addr1Offset:{ *:[iPTR] } i32:{ *:[i32] }:$ptr, i32:{ *:[i32] }:$offset), f32:{ *:[f32] }:$value)<<P:Predicate_atomic_load_fmin_region_m0_32>>  =>  (DS_MIN_RTN_F32:{ *:[f32] } ?:{ *:[i32] }:$ptr, anonymous_15037:{ *:[f32] }:$value, offset:{ *:[i32] }:$offset, 1:{ *:[i1] })
        GIR_BuildMI, /*InsnID*/0, /*Opcode*/GIMT_Encode2(AMDGPU::DS_MIN_RTN_F32),
        GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/0, // DstI[vdst]
        GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/0, // ptr
        GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/2, // value
        GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/1, // offset
        GIR_AddImm8, /*InsnID*/0, /*Imm*/1,
        GIR_MergeMemOperands, /*InsnID*/0, /*NumInsns*/1, /*MergeInsnID's*/0,
        GIR_ConstrainSelectedInstOperands, /*InsnID*/0,
        GIR_EraseFromParent, /*InsnID*/0,
        // GIR_Coverage, 6974,
        GIR_Done,
      // Label 5689: @413622
      GIM_Try, /*On fail goto*//*Label 5690*/ GIMT_Encode4(413685), // Rule ID 3277 //
        GIM_CheckFeatures, GIMT_Encode2(GIFBS_isGFX10Plus),
        GIM_CheckMemoryAddressSpace, /*MI*/0, /*MMO*/0, /*NumAddrSpace*/3, /*AddrSpace*/1, /*AddrSpace*/4, /*AddrSpace*/6,
        GIM_CheckHasNoUse, /*MI*/0,
        GIM_CheckPointerToAny, /*MI*/0, /*Op*/1, /*SizeInBits*/0,
        GIM_CheckComplexPattern, /*MI*/0, /*Op*/1, /*Renderer*/GIMT_Encode2(0), GIMT_Encode2(GICP_gi_global_saddr),
        // (SIatomic_fmin:{ *:[f32] } (GlobalSAddr:{ *:[iPTR] } SReg_64:{ *:[i64] }:$saddr, VGPR_32:{ *:[i32] }:$voffset, i32:{ *:[i32] }:$offset), f32:{ *:[f32] }:$data)<<P:Predicate_atomic_load_fmin_global_noret_32>>  =>  (GLOBAL_ATOMIC_FMIN_SADDR ?:{ *:[i32] }:$voffset, anonymous_15037:{ *:[f32] }:$data, ?:{ *:[i64] }:$saddr, ?:{ *:[i32] }:$offset)
        GIR_BuildMI, /*InsnID*/0, /*Opcode*/GIMT_Encode2(AMDGPU::GLOBAL_ATOMIC_FMIN_SADDR),
        GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/1, // voffset
        GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/2, // data
        GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/0, // saddr
        GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/2, // offset
        GIR_AddImm8, /*InsnID*/0, /*Imm*/0,
        GIR_MergeMemOperands, /*InsnID*/0, /*NumInsns*/1, /*MergeInsnID's*/0,
        GIR_ConstrainSelectedInstOperands, /*InsnID*/0,
        GIR_EraseFromParent, /*InsnID*/0,
        // GIR_Coverage, 3277,
        GIR_Done,
      // Label 5690: @413685
      GIM_Try, /*On fail goto*//*Label 5691*/ GIMT_Encode4(413755), // Rule ID 3279 //
        GIM_CheckFeatures, GIMT_Encode2(GIFBS_isGFX10Plus),
        GIM_CheckMemoryAddressSpace, /*MI*/0, /*MMO*/0, /*NumAddrSpace*/3, /*AddrSpace*/1, /*AddrSpace*/4, /*AddrSpace*/6,
        GIM_CheckRegBankForClass, /*MI*/0, /*Op*/0, /*RC*/GIMT_Encode2(AMDGPU::AV_32RegClassID),
        GIM_CheckPointerToAny, /*MI*/0, /*Op*/1, /*SizeInBits*/0,
        GIM_CheckComplexPattern, /*MI*/0, /*Op*/1, /*Renderer*/GIMT_Encode2(0), GIMT_Encode2(GICP_gi_global_saddr),
        // (SIatomic_fmin:{ *:[f32] } (GlobalSAddr:{ *:[iPTR] } SReg_64:{ *:[i64] }:$saddr, VGPR_32:{ *:[i32] }:$voffset, i32:{ *:[i32] }:$offset), f32:{ *:[f32] }:$data)<<P:Predicate_atomic_load_fmin_global_32>>  =>  (GLOBAL_ATOMIC_FMIN_SADDR_RTN:{ *:[f32] } ?:{ *:[i32] }:$voffset, anonymous_15037:{ *:[f32] }:$data, ?:{ *:[i64] }:$saddr, ?:{ *:[i32] }:$offset)
        GIR_BuildMI, /*InsnID*/0, /*Opcode*/GIMT_Encode2(AMDGPU::GLOBAL_ATOMIC_FMIN_SADDR_RTN),
        GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/0, // DstI[vdst]
        GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/1, // voffset
        GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/2, // data
        GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/0, // saddr
        GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/2, // offset
        GIR_AddImm8, /*InsnID*/0, /*Imm*/1,
        GIR_MergeMemOperands, /*InsnID*/0, /*NumInsns*/1, /*MergeInsnID's*/0,
        GIR_ConstrainSelectedInstOperands, /*InsnID*/0,
        GIR_EraseFromParent, /*InsnID*/0,
        // GIR_Coverage, 3279,
        GIR_Done,
      // Label 5691: @413755
      GIM_Try, /*On fail goto*//*Label 5692*/ GIMT_Encode4(413813), // Rule ID 3276 //
        GIM_CheckFeatures, GIMT_Encode2(GIFBS_isGFX10Plus),
        GIM_CheckMemoryAddressSpace, /*MI*/0, /*MMO*/0, /*NumAddrSpace*/3, /*AddrSpace*/1, /*AddrSpace*/4, /*AddrSpace*/6,
        GIM_CheckHasNoUse, /*MI*/0,
        GIM_CheckPointerToAny, /*MI*/0, /*Op*/1, /*SizeInBits*/0,
        GIM_CheckComplexPattern, /*MI*/0, /*Op*/1, /*Renderer*/GIMT_Encode2(0), GIMT_Encode2(GICP_gi_global_offset),
        // (SIatomic_fmin:{ *:[f32] } (GlobalOffset:{ *:[iPTR] } i64:{ *:[i64] }:$vaddr, i32:{ *:[i32] }:$offset), f32:{ *:[f32] }:$data)<<P:Predicate_atomic_load_fmin_global_noret_32>>  =>  (GLOBAL_ATOMIC_FMIN VReg_64:{ *:[i64] }:$vaddr, anonymous_15037:{ *:[f32] }:$data, ?:{ *:[i32] }:$offset)
        GIR_BuildMI, /*InsnID*/0, /*Opcode*/GIMT_Encode2(AMDGPU::GLOBAL_ATOMIC_FMIN),
        GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/0, // vaddr
        GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/2, // data
        GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/1, // offset
        GIR_AddImm8, /*InsnID*/0, /*Imm*/0,
        GIR_MergeMemOperands, /*InsnID*/0, /*NumInsns*/1, /*MergeInsnID's*/0,
        GIR_ConstrainSelectedInstOperands, /*InsnID*/0,
        GIR_EraseFromParent, /*InsnID*/0,
        // GIR_Coverage, 3276,
        GIR_Done,
      // Label 5692: @413813
      GIM_Try, /*On fail goto*//*Label 5693*/ GIMT_Encode4(413878), // Rule ID 3278 //
        GIM_CheckFeatures, GIMT_Encode2(GIFBS_isGFX10Plus),
        GIM_CheckMemoryAddressSpace, /*MI*/0, /*MMO*/0, /*NumAddrSpace*/3, /*AddrSpace*/1, /*AddrSpace*/4, /*AddrSpace*/6,
        GIM_CheckRegBankForClass, /*MI*/0, /*Op*/0, /*RC*/GIMT_Encode2(AMDGPU::AV_32RegClassID),
        GIM_CheckPointerToAny, /*MI*/0, /*Op*/1, /*SizeInBits*/0,
        GIM_CheckComplexPattern, /*MI*/0, /*Op*/1, /*Renderer*/GIMT_Encode2(0), GIMT_Encode2(GICP_gi_global_offset),
        // (SIatomic_fmin:{ *:[f32] } (GlobalOffset:{ *:[iPTR] } i64:{ *:[i64] }:$vaddr, i32:{ *:[i32] }:$offset), f32:{ *:[f32] }:$data)<<P:Predicate_atomic_load_fmin_global_32>>  =>  (GLOBAL_ATOMIC_FMIN_RTN:{ *:[f32] } VReg_64:{ *:[i64] }:$vaddr, anonymous_15037:{ *:[f32] }:$data, ?:{ *:[i32] }:$offset)
        GIR_BuildMI, /*InsnID*/0, /*Opcode*/GIMT_Encode2(AMDGPU::GLOBAL_ATOMIC_FMIN_RTN),
        GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/0, // DstI[vdst]
        GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/0, // vaddr
        GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/2, // data
        GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/1, // offset
        GIR_AddImm8, /*InsnID*/0, /*Imm*/1,
        GIR_MergeMemOperands, /*InsnID*/0, /*NumInsns*/1, /*MergeInsnID's*/0,
        GIR_ConstrainSelectedInstOperands, /*InsnID*/0,
        GIR_EraseFromParent, /*InsnID*/0,
        // GIR_Coverage, 3278,
        GIR_Done,
      // Label 5693: @413878
      GIM_Try, /*On fail goto*//*Label 5694*/ GIMT_Encode4(413937), // Rule ID 2748 //
        GIM_CheckFeatures, GIMT_Encode2(GIFBS_isGFX10Plus),
        GIM_CheckMemoryAddressSpace, /*MI*/0, /*MMO*/0, /*NumAddrSpace*/4, /*AddrSpace*/0, /*AddrSpace*/1, /*AddrSpace*/4, /*AddrSpace*/6,
        GIM_CheckHasNoUse, /*MI*/0,
        GIM_CheckPointerToAny, /*MI*/0, /*Op*/1, /*SizeInBits*/0,
        GIM_CheckComplexPattern, /*MI*/0, /*Op*/1, /*Renderer*/GIMT_Encode2(0), GIMT_Encode2(GICP_gi_global_offset),
        // (SIatomic_fmin:{ *:[f32] } (GlobalOffset:{ *:[iPTR] } i64:{ *:[i64] }:$vaddr, i32:{ *:[i32] }:$offset), f32:{ *:[f32] }:$data)<<P:Predicate_atomic_load_fmin_flat_noret_32>>  =>  (FLAT_ATOMIC_FMIN VReg_64:{ *:[i64] }:$vaddr, anonymous_15037:{ *:[f32] }:$data, ?:{ *:[i32] }:$offset)
        GIR_BuildMI, /*InsnID*/0, /*Opcode*/GIMT_Encode2(AMDGPU::FLAT_ATOMIC_FMIN),
        GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/0, // vaddr
        GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/2, // data
        GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/1, // offset
        GIR_AddImm8, /*InsnID*/0, /*Imm*/0,
        GIR_MergeMemOperands, /*InsnID*/0, /*NumInsns*/1, /*MergeInsnID's*/0,
        GIR_ConstrainSelectedInstOperands, /*InsnID*/0,
        GIR_EraseFromParent, /*InsnID*/0,
        // GIR_Coverage, 2748,
        GIR_Done,
      // Label 5694: @413937
      GIM_Try, /*On fail goto*//*Label 5695*/ GIMT_Encode4(414003), // Rule ID 2747 //
        GIM_CheckFeatures, GIMT_Encode2(GIFBS_isGFX10Plus),
        GIM_CheckMemoryAddressSpace, /*MI*/0, /*MMO*/0, /*NumAddrSpace*/4, /*AddrSpace*/0, /*AddrSpace*/1, /*AddrSpace*/4, /*AddrSpace*/6,
        GIM_CheckRegBankForClass, /*MI*/0, /*Op*/0, /*RC*/GIMT_Encode2(AMDGPU::AV_32RegClassID),
        GIM_CheckPointerToAny, /*MI*/0, /*Op*/1, /*SizeInBits*/0,
        GIM_CheckComplexPattern, /*MI*/0, /*Op*/1, /*Renderer*/GIMT_Encode2(0), GIMT_Encode2(GICP_gi_global_offset),
        // (SIatomic_fmin:{ *:[f32] } (GlobalOffset:{ *:[iPTR] } i64:{ *:[i64] }:$vaddr, i32:{ *:[i32] }:$offset), f32:{ *:[f32] }:$data)<<P:Predicate_atomic_load_fmin_flat_32>>  =>  (FLAT_ATOMIC_FMIN_RTN:{ *:[f32] } VReg_64:{ *:[i64] }:$vaddr, anonymous_15037:{ *:[f32] }:$data, ?:{ *:[i32] }:$offset)
        GIR_BuildMI, /*InsnID*/0, /*Opcode*/GIMT_Encode2(AMDGPU::FLAT_ATOMIC_FMIN_RTN),
        GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/0, // DstI[vdst]
        GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/0, // vaddr
        GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/2, // data
        GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/1, // offset
        GIR_AddImm8, /*InsnID*/0, /*Imm*/1,
        GIR_MergeMemOperands, /*InsnID*/0, /*NumInsns*/1, /*MergeInsnID's*/0,
        GIR_ConstrainSelectedInstOperands, /*InsnID*/0,
        GIR_EraseFromParent, /*InsnID*/0,
        // GIR_Coverage, 2747,
        GIR_Done,
      // Label 5695: @414003
      GIM_Reject,
    // Label 5683: @414004
    GIM_Reject,
    // Label 5681: @414005
    GIM_Try, /*On fail goto*//*Label 5696*/ GIMT_Encode4(415134),
      GIM_CheckType, /*MI*/0, /*Op*/2, /*Type*/GILLT_s64,
      GIM_Try, /*On fail goto*//*Label 5697*/ GIMT_Encode4(414070), // Rule ID 7058 //
        GIM_CheckFeatures, GIMT_Encode2(GIFBS_LDSRequiresM0Init),
        GIM_CheckMemoryAddressSpace, /*MI*/0, /*MMO*/0, /*NumAddrSpace*/1, /*AddrSpace*/3,
        GIM_CheckHasNoUse, /*MI*/0,
        GIM_CheckPointerToAny, /*MI*/0, /*Op*/1, /*SizeInBits*/0,
        GIM_CheckComplexPattern, /*MI*/0, /*Op*/1, /*Renderer*/GIMT_Encode2(0), GIMT_Encode2(GICP_gi_ds_1addr_1offset),
        // (atomic_load_fmin_glue:{ *:[f64] } (DS1Addr1Offset:{ *:[iPTR] } i32:{ *:[i32] }:$ptr, i32:{ *:[i32] }:$offset), f64:{ *:[f64] }:$value)<<P:Predicate_atomic_load_fmin_local_m0_noret_64>>  =>  (DS_MIN_F64 ?:{ *:[i32] }:$ptr, anonymous_15036:{ *:[f64] }:$value, offset:{ *:[i32] }:$offset, 0:{ *:[i1] })
        GIR_BuildMI, /*InsnID*/0, /*Opcode*/GIMT_Encode2(AMDGPU::DS_MIN_F64),
        GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/0, // ptr
        GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/2, // value
        GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/1, // offset
        GIR_AddImm8, /*InsnID*/0, /*Imm*/0,
        GIR_MergeMemOperands, /*InsnID*/0, /*NumInsns*/1, /*MergeInsnID's*/0,
        GIR_ConstrainSelectedInstOperands, /*InsnID*/0,
        GIR_EraseFromParent, /*InsnID*/0,
        // GIR_Coverage, 7058,
        GIR_Done,
      // Label 5697: @414070
      GIM_Try, /*On fail goto*//*Label 5698*/ GIMT_Encode4(414126), // Rule ID 7060 //
        GIM_CheckFeatures, GIMT_Encode2(GIFBS_NotLDSRequiresM0Init),
        GIM_CheckMemoryAddressSpace, /*MI*/0, /*MMO*/0, /*NumAddrSpace*/1, /*AddrSpace*/3,
        GIM_CheckHasNoUse, /*MI*/0,
        GIM_CheckPointerToAny, /*MI*/0, /*Op*/1, /*SizeInBits*/0,
        GIM_CheckComplexPattern, /*MI*/0, /*Op*/1, /*Renderer*/GIMT_Encode2(0), GIMT_Encode2(GICP_gi_ds_1addr_1offset),
        // (SIatomic_fmin:{ *:[f64] } (DS1Addr1Offset:{ *:[iPTR] } i32:{ *:[i32] }:$ptr, i32:{ *:[i32] }:$offset), f64:{ *:[f64] }:$value)<<P:Predicate_atomic_load_fmin_local_noret_64>>  =>  (DS_MIN_F64_gfx9 ?:{ *:[i32] }:$ptr, anonymous_15036:{ *:[f64] }:$value, offset:{ *:[i32] }:$offset, 0:{ *:[i1] })
        GIR_BuildMI, /*InsnID*/0, /*Opcode*/GIMT_Encode2(AMDGPU::DS_MIN_F64_gfx9),
        GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/0, // ptr
        GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/2, // value
        GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/1, // offset
        GIR_AddImm8, /*InsnID*/0, /*Imm*/0,
        GIR_MergeMemOperands, /*InsnID*/0, /*NumInsns*/1, /*MergeInsnID's*/0,
        GIR_ConstrainSelectedInstOperands, /*InsnID*/0,
        GIR_EraseFromParent, /*InsnID*/0,
        // GIR_Coverage, 7060,
        GIR_Done,
      // Label 5698: @414126
      GIM_Try, /*On fail goto*//*Label 5699*/ GIMT_Encode4(414182), // Rule ID 7062 //
        GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasGDS),
        GIM_CheckMemoryAddressSpace, /*MI*/0, /*MMO*/0, /*NumAddrSpace*/1, /*AddrSpace*/2,
        GIM_CheckHasNoUse, /*MI*/0,
        GIM_CheckPointerToAny, /*MI*/0, /*Op*/1, /*SizeInBits*/0,
        GIM_CheckComplexPattern, /*MI*/0, /*Op*/1, /*Renderer*/GIMT_Encode2(0), GIMT_Encode2(GICP_gi_ds_1addr_1offset),
        // (atomic_load_fmin_glue:{ *:[f64] } (DS1Addr1Offset:{ *:[iPTR] } i32:{ *:[i32] }:$ptr, i32:{ *:[i32] }:$offset), f64:{ *:[f64] }:$value)<<P:Predicate_atomic_load_fmin_region_m0_noret_64>>  =>  (DS_MIN_F64 ?:{ *:[i32] }:$ptr, anonymous_15036:{ *:[f64] }:$value, offset:{ *:[i32] }:$offset, 1:{ *:[i1] })
        GIR_BuildMI, /*InsnID*/0, /*Opcode*/GIMT_Encode2(AMDGPU::DS_MIN_F64),
        GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/0, // ptr
        GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/2, // value
        GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/1, // offset
        GIR_AddImm8, /*InsnID*/0, /*Imm*/1,
        GIR_MergeMemOperands, /*InsnID*/0, /*NumInsns*/1, /*MergeInsnID's*/0,
        GIR_ConstrainSelectedInstOperands, /*InsnID*/0,
        GIR_EraseFromParent, /*InsnID*/0,
        // GIR_Coverage, 7062,
        GIR_Done,
      // Label 5699: @414182
      GIM_Try, /*On fail goto*//*Label 5700*/ GIMT_Encode4(414245), // Rule ID 7057 //
        GIM_CheckFeatures, GIMT_Encode2(GIFBS_LDSRequiresM0Init),
        GIM_CheckMemoryAddressSpace, /*MI*/0, /*MMO*/0, /*NumAddrSpace*/1, /*AddrSpace*/3,
        GIM_CheckRegBankForClass, /*MI*/0, /*Op*/0, /*RC*/GIMT_Encode2(AMDGPU::AV_64RegClassID),
        GIM_CheckPointerToAny, /*MI*/0, /*Op*/1, /*SizeInBits*/0,
        GIM_CheckComplexPattern, /*MI*/0, /*Op*/1, /*Renderer*/GIMT_Encode2(0), GIMT_Encode2(GICP_gi_ds_1addr_1offset),
        // (atomic_load_fmin_glue:{ *:[f64] } (DS1Addr1Offset:{ *:[iPTR] } i32:{ *:[i32] }:$ptr, i32:{ *:[i32] }:$offset), f64:{ *:[f64] }:$value)<<P:Predicate_atomic_load_fmin_local_m0_64>>  =>  (DS_MIN_RTN_F64:{ *:[f64] } ?:{ *:[i32] }:$ptr, anonymous_15036:{ *:[f64] }:$value, offset:{ *:[i32] }:$offset, 0:{ *:[i1] })
        GIR_BuildMI, /*InsnID*/0, /*Opcode*/GIMT_Encode2(AMDGPU::DS_MIN_RTN_F64),
        GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/0, // DstI[vdst]
        GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/0, // ptr
        GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/2, // value
        GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/1, // offset
        GIR_AddImm8, /*InsnID*/0, /*Imm*/0,
        GIR_MergeMemOperands, /*InsnID*/0, /*NumInsns*/1, /*MergeInsnID's*/0,
        GIR_ConstrainSelectedInstOperands, /*InsnID*/0,
        GIR_EraseFromParent, /*InsnID*/0,
        // GIR_Coverage, 7057,
        GIR_Done,
      // Label 5700: @414245
      GIM_Try, /*On fail goto*//*Label 5701*/ GIMT_Encode4(414308), // Rule ID 7059 //
        GIM_CheckFeatures, GIMT_Encode2(GIFBS_NotLDSRequiresM0Init),
        GIM_CheckMemoryAddressSpace, /*MI*/0, /*MMO*/0, /*NumAddrSpace*/1, /*AddrSpace*/3,
        GIM_CheckRegBankForClass, /*MI*/0, /*Op*/0, /*RC*/GIMT_Encode2(AMDGPU::AV_64RegClassID),
        GIM_CheckPointerToAny, /*MI*/0, /*Op*/1, /*SizeInBits*/0,
        GIM_CheckComplexPattern, /*MI*/0, /*Op*/1, /*Renderer*/GIMT_Encode2(0), GIMT_Encode2(GICP_gi_ds_1addr_1offset),
        // (SIatomic_fmin:{ *:[f64] } (DS1Addr1Offset:{ *:[iPTR] } i32:{ *:[i32] }:$ptr, i32:{ *:[i32] }:$offset), f64:{ *:[f64] }:$value)<<P:Predicate_atomic_load_fmin_local_64>>  =>  (DS_MIN_RTN_F64_gfx9:{ *:[f64] } ?:{ *:[i32] }:$ptr, anonymous_15036:{ *:[f64] }:$value, offset:{ *:[i32] }:$offset, 0:{ *:[i1] })
        GIR_BuildMI, /*InsnID*/0, /*Opcode*/GIMT_Encode2(AMDGPU::DS_MIN_RTN_F64_gfx9),
        GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/0, // DstI[vdst]
        GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/0, // ptr
        GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/2, // value
        GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/1, // offset
        GIR_AddImm8, /*InsnID*/0, /*Imm*/0,
        GIR_MergeMemOperands, /*InsnID*/0, /*NumInsns*/1, /*MergeInsnID's*/0,
        GIR_ConstrainSelectedInstOperands, /*InsnID*/0,
        GIR_EraseFromParent, /*InsnID*/0,
        // GIR_Coverage, 7059,
        GIR_Done,
      // Label 5701: @414308
      GIM_Try, /*On fail goto*//*Label 5702*/ GIMT_Encode4(414371), // Rule ID 7061 //
        GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasGDS),
        GIM_CheckMemoryAddressSpace, /*MI*/0, /*MMO*/0, /*NumAddrSpace*/1, /*AddrSpace*/2,
        GIM_CheckRegBankForClass, /*MI*/0, /*Op*/0, /*RC*/GIMT_Encode2(AMDGPU::AV_64RegClassID),
        GIM_CheckPointerToAny, /*MI*/0, /*Op*/1, /*SizeInBits*/0,
        GIM_CheckComplexPattern, /*MI*/0, /*Op*/1, /*Renderer*/GIMT_Encode2(0), GIMT_Encode2(GICP_gi_ds_1addr_1offset),
        // (atomic_load_fmin_glue:{ *:[f64] } (DS1Addr1Offset:{ *:[iPTR] } i32:{ *:[i32] }:$ptr, i32:{ *:[i32] }:$offset), f64:{ *:[f64] }:$value)<<P:Predicate_atomic_load_fmin_region_m0_64>>  =>  (DS_MIN_RTN_F64:{ *:[f64] } ?:{ *:[i32] }:$ptr, anonymous_15036:{ *:[f64] }:$value, offset:{ *:[i32] }:$offset, 1:{ *:[i1] })
        GIR_BuildMI, /*InsnID*/0, /*Opcode*/GIMT_Encode2(AMDGPU::DS_MIN_RTN_F64),
        GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/0, // DstI[vdst]
        GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/0, // ptr
        GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/2, // value
        GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/1, // offset
        GIR_AddImm8, /*InsnID*/0, /*Imm*/1,
        GIR_MergeMemOperands, /*InsnID*/0, /*NumInsns*/1, /*MergeInsnID's*/0,
        GIR_ConstrainSelectedInstOperands, /*InsnID*/0,
        GIR_EraseFromParent, /*InsnID*/0,
        // GIR_Coverage, 7061,
        GIR_Done,
      // Label 5702: @414371
      GIM_Try, /*On fail goto*//*Label 5703*/ GIMT_Encode4(414434), // Rule ID 3299 //
        GIM_CheckFeatures, GIMT_Encode2(GIFBS_isGFX10Only),
        GIM_CheckMemoryAddressSpace, /*MI*/0, /*MMO*/0, /*NumAddrSpace*/3, /*AddrSpace*/1, /*AddrSpace*/4, /*AddrSpace*/6,
        GIM_CheckHasNoUse, /*MI*/0,
        GIM_CheckPointerToAny, /*MI*/0, /*Op*/1, /*SizeInBits*/0,
        GIM_CheckComplexPattern, /*MI*/0, /*Op*/1, /*Renderer*/GIMT_Encode2(0), GIMT_Encode2(GICP_gi_global_saddr),
        // (SIatomic_fmin:{ *:[f64] } (GlobalSAddr:{ *:[iPTR] } SReg_64:{ *:[i64] }:$saddr, VGPR_32:{ *:[i32] }:$voffset, i32:{ *:[i32] }:$offset), f64:{ *:[f64] }:$data)<<P:Predicate_atomic_load_fmin_global_noret_64>>  =>  (GLOBAL_ATOMIC_FMIN_X2_SADDR ?:{ *:[i32] }:$voffset, anonymous_15036:{ *:[f64] }:$data, ?:{ *:[i64] }:$saddr, ?:{ *:[i32] }:$offset)
        GIR_BuildMI, /*InsnID*/0, /*Opcode*/GIMT_Encode2(AMDGPU::GLOBAL_ATOMIC_FMIN_X2_SADDR),
        GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/1, // voffset
        GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/2, // data
        GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/0, // saddr
        GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/2, // offset
        GIR_AddImm8, /*InsnID*/0, /*Imm*/0,
        GIR_MergeMemOperands, /*InsnID*/0, /*NumInsns*/1, /*MergeInsnID's*/0,
        GIR_ConstrainSelectedInstOperands, /*InsnID*/0,
        GIR_EraseFromParent, /*InsnID*/0,
        // GIR_Coverage, 3299,
        GIR_Done,
      // Label 5703: @414434
      GIM_Try, /*On fail goto*//*Label 5704*/ GIMT_Encode4(414497), // Rule ID 3359 //
        GIM_CheckFeatures, GIMT_Encode2(GIFBS_isGFX90APlus),
        GIM_CheckMemoryAddressSpace, /*MI*/0, /*MMO*/0, /*NumAddrSpace*/3, /*AddrSpace*/1, /*AddrSpace*/4, /*AddrSpace*/6,
        GIM_CheckHasNoUse, /*MI*/0,
        GIM_CheckPointerToAny, /*MI*/0, /*Op*/1, /*SizeInBits*/0,
        GIM_CheckComplexPattern, /*MI*/0, /*Op*/1, /*Renderer*/GIMT_Encode2(0), GIMT_Encode2(GICP_gi_global_saddr),
        // (SIatomic_fmin:{ *:[f64] } (GlobalSAddr:{ *:[iPTR] } SReg_64:{ *:[i64] }:$saddr, VGPR_32:{ *:[i32] }:$voffset, i32:{ *:[i32] }:$offset), f64:{ *:[f64] }:$data)<<P:Predicate_atomic_load_fmin_global_noret_64>>  =>  (GLOBAL_ATOMIC_MIN_F64_SADDR ?:{ *:[i32] }:$voffset, anonymous_15036:{ *:[f64] }:$data, ?:{ *:[i64] }:$saddr, ?:{ *:[i32] }:$offset)
        GIR_BuildMI, /*InsnID*/0, /*Opcode*/GIMT_Encode2(AMDGPU::GLOBAL_ATOMIC_MIN_F64_SADDR),
        GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/1, // voffset
        GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/2, // data
        GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/0, // saddr
        GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/2, // offset
        GIR_AddImm8, /*InsnID*/0, /*Imm*/0,
        GIR_MergeMemOperands, /*InsnID*/0, /*NumInsns*/1, /*MergeInsnID's*/0,
        GIR_ConstrainSelectedInstOperands, /*InsnID*/0,
        GIR_EraseFromParent, /*InsnID*/0,
        // GIR_Coverage, 3359,
        GIR_Done,
      // Label 5704: @414497
      GIM_Try, /*On fail goto*//*Label 5705*/ GIMT_Encode4(414567), // Rule ID 3301 //
        GIM_CheckFeatures, GIMT_Encode2(GIFBS_isGFX10Only),
        GIM_CheckMemoryAddressSpace, /*MI*/0, /*MMO*/0, /*NumAddrSpace*/3, /*AddrSpace*/1, /*AddrSpace*/4, /*AddrSpace*/6,
        GIM_CheckRegBankForClass, /*MI*/0, /*Op*/0, /*RC*/GIMT_Encode2(AMDGPU::AV_64RegClassID),
        GIM_CheckPointerToAny, /*MI*/0, /*Op*/1, /*SizeInBits*/0,
        GIM_CheckComplexPattern, /*MI*/0, /*Op*/1, /*Renderer*/GIMT_Encode2(0), GIMT_Encode2(GICP_gi_global_saddr),
        // (SIatomic_fmin:{ *:[f64] } (GlobalSAddr:{ *:[iPTR] } SReg_64:{ *:[i64] }:$saddr, VGPR_32:{ *:[i32] }:$voffset, i32:{ *:[i32] }:$offset), f64:{ *:[f64] }:$data)<<P:Predicate_atomic_load_fmin_global_64>>  =>  (GLOBAL_ATOMIC_FMIN_X2_SADDR_RTN:{ *:[f64] } ?:{ *:[i32] }:$voffset, anonymous_15036:{ *:[f64] }:$data, ?:{ *:[i64] }:$saddr, ?:{ *:[i32] }:$offset)
        GIR_BuildMI, /*InsnID*/0, /*Opcode*/GIMT_Encode2(AMDGPU::GLOBAL_ATOMIC_FMIN_X2_SADDR_RTN),
        GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/0, // DstI[vdst]
        GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/1, // voffset
        GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/2, // data
        GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/0, // saddr
        GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/2, // offset
        GIR_AddImm8, /*InsnID*/0, /*Imm*/1,
        GIR_MergeMemOperands, /*InsnID*/0, /*NumInsns*/1, /*MergeInsnID's*/0,
        GIR_ConstrainSelectedInstOperands, /*InsnID*/0,
        GIR_EraseFromParent, /*InsnID*/0,
        // GIR_Coverage, 3301,
        GIR_Done,
      // Label 5705: @414567
      GIM_Try, /*On fail goto*//*Label 5706*/ GIMT_Encode4(414637), // Rule ID 3361 //
        GIM_CheckFeatures, GIMT_Encode2(GIFBS_isGFX90APlus),
        GIM_CheckMemoryAddressSpace, /*MI*/0, /*MMO*/0, /*NumAddrSpace*/3, /*AddrSpace*/1, /*AddrSpace*/4, /*AddrSpace*/6,
        GIM_CheckRegBankForClass, /*MI*/0, /*Op*/0, /*RC*/GIMT_Encode2(AMDGPU::AV_64RegClassID),
        GIM_CheckPointerToAny, /*MI*/0, /*Op*/1, /*SizeInBits*/0,
        GIM_CheckComplexPattern, /*MI*/0, /*Op*/1, /*Renderer*/GIMT_Encode2(0), GIMT_Encode2(GICP_gi_global_saddr),
        // (SIatomic_fmin:{ *:[f64] } (GlobalSAddr:{ *:[iPTR] } SReg_64:{ *:[i64] }:$saddr, VGPR_32:{ *:[i32] }:$voffset, i32:{ *:[i32] }:$offset), f64:{ *:[f64] }:$data)<<P:Predicate_atomic_load_fmin_global_64>>  =>  (GLOBAL_ATOMIC_MIN_F64_SADDR_RTN:{ *:[f64] } ?:{ *:[i32] }:$voffset, anonymous_15036:{ *:[f64] }:$data, ?:{ *:[i64] }:$saddr, ?:{ *:[i32] }:$offset)
        GIR_BuildMI, /*InsnID*/0, /*Opcode*/GIMT_Encode2(AMDGPU::GLOBAL_ATOMIC_MIN_F64_SADDR_RTN),
        GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/0, // DstI[vdst]
        GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/1, // voffset
        GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/2, // data
        GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/0, // saddr
        GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/2, // offset
        GIR_AddImm8, /*InsnID*/0, /*Imm*/1,
        GIR_MergeMemOperands, /*InsnID*/0, /*NumInsns*/1, /*MergeInsnID's*/0,
        GIR_ConstrainSelectedInstOperands, /*InsnID*/0,
        GIR_EraseFromParent, /*InsnID*/0,
        // GIR_Coverage, 3361,
        GIR_Done,
      // Label 5706: @414637
      GIM_Try, /*On fail goto*//*Label 5707*/ GIMT_Encode4(414695), // Rule ID 3298 //
        GIM_CheckFeatures, GIMT_Encode2(GIFBS_isGFX10Only),
        GIM_CheckMemoryAddressSpace, /*MI*/0, /*MMO*/0, /*NumAddrSpace*/3, /*AddrSpace*/1, /*AddrSpace*/4, /*AddrSpace*/6,
        GIM_CheckHasNoUse, /*MI*/0,
        GIM_CheckPointerToAny, /*MI*/0, /*Op*/1, /*SizeInBits*/0,
        GIM_CheckComplexPattern, /*MI*/0, /*Op*/1, /*Renderer*/GIMT_Encode2(0), GIMT_Encode2(GICP_gi_global_offset),
        // (SIatomic_fmin:{ *:[f64] } (GlobalOffset:{ *:[iPTR] } i64:{ *:[i64] }:$vaddr, i32:{ *:[i32] }:$offset), f64:{ *:[f64] }:$data)<<P:Predicate_atomic_load_fmin_global_noret_64>>  =>  (GLOBAL_ATOMIC_FMIN_X2 VReg_64:{ *:[i64] }:$vaddr, anonymous_15036:{ *:[f64] }:$data, ?:{ *:[i32] }:$offset)
        GIR_BuildMI, /*InsnID*/0, /*Opcode*/GIMT_Encode2(AMDGPU::GLOBAL_ATOMIC_FMIN_X2),
        GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/0, // vaddr
        GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/2, // data
        GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/1, // offset
        GIR_AddImm8, /*InsnID*/0, /*Imm*/0,
        GIR_MergeMemOperands, /*InsnID*/0, /*NumInsns*/1, /*MergeInsnID's*/0,
        GIR_ConstrainSelectedInstOperands, /*InsnID*/0,
        GIR_EraseFromParent, /*InsnID*/0,
        // GIR_Coverage, 3298,
        GIR_Done,
      // Label 5707: @414695
      GIM_Try, /*On fail goto*//*Label 5708*/ GIMT_Encode4(414753), // Rule ID 3358 //
        GIM_CheckFeatures, GIMT_Encode2(GIFBS_isGFX90APlus),
        GIM_CheckMemoryAddressSpace, /*MI*/0, /*MMO*/0, /*NumAddrSpace*/3, /*AddrSpace*/1, /*AddrSpace*/4, /*AddrSpace*/6,
        GIM_CheckHasNoUse, /*MI*/0,
        GIM_CheckPointerToAny, /*MI*/0, /*Op*/1, /*SizeInBits*/0,
        GIM_CheckComplexPattern, /*MI*/0, /*Op*/1, /*Renderer*/GIMT_Encode2(0), GIMT_Encode2(GICP_gi_global_offset),
        // (SIatomic_fmin:{ *:[f64] } (GlobalOffset:{ *:[iPTR] } i64:{ *:[i64] }:$vaddr, i32:{ *:[i32] }:$offset), f64:{ *:[f64] }:$data)<<P:Predicate_atomic_load_fmin_global_noret_64>>  =>  (GLOBAL_ATOMIC_MIN_F64 VReg_64:{ *:[i64] }:$vaddr, anonymous_15036:{ *:[f64] }:$data, ?:{ *:[i32] }:$offset)
        GIR_BuildMI, /*InsnID*/0, /*Opcode*/GIMT_Encode2(AMDGPU::GLOBAL_ATOMIC_MIN_F64),
        GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/0, // vaddr
        GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/2, // data
        GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/1, // offset
        GIR_AddImm8, /*InsnID*/0, /*Imm*/0,
        GIR_MergeMemOperands, /*InsnID*/0, /*NumInsns*/1, /*MergeInsnID's*/0,
        GIR_ConstrainSelectedInstOperands, /*InsnID*/0,
        GIR_EraseFromParent, /*InsnID*/0,
        // GIR_Coverage, 3358,
        GIR_Done,
      // Label 5708: @414753
      GIM_Try, /*On fail goto*//*Label 5709*/ GIMT_Encode4(414818), // Rule ID 3300 //
        GIM_CheckFeatures, GIMT_Encode2(GIFBS_isGFX10Only),
        GIM_CheckMemoryAddressSpace, /*MI*/0, /*MMO*/0, /*NumAddrSpace*/3, /*AddrSpace*/1, /*AddrSpace*/4, /*AddrSpace*/6,
        GIM_CheckRegBankForClass, /*MI*/0, /*Op*/0, /*RC*/GIMT_Encode2(AMDGPU::AV_64RegClassID),
        GIM_CheckPointerToAny, /*MI*/0, /*Op*/1, /*SizeInBits*/0,
        GIM_CheckComplexPattern, /*MI*/0, /*Op*/1, /*Renderer*/GIMT_Encode2(0), GIMT_Encode2(GICP_gi_global_offset),
        // (SIatomic_fmin:{ *:[f64] } (GlobalOffset:{ *:[iPTR] } i64:{ *:[i64] }:$vaddr, i32:{ *:[i32] }:$offset), f64:{ *:[f64] }:$data)<<P:Predicate_atomic_load_fmin_global_64>>  =>  (GLOBAL_ATOMIC_FMIN_X2_RTN:{ *:[f64] } VReg_64:{ *:[i64] }:$vaddr, anonymous_15036:{ *:[f64] }:$data, ?:{ *:[i32] }:$offset)
        GIR_BuildMI, /*InsnID*/0, /*Opcode*/GIMT_Encode2(AMDGPU::GLOBAL_ATOMIC_FMIN_X2_RTN),
        GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/0, // DstI[vdst]
        GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/0, // vaddr
        GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/2, // data
        GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/1, // offset
        GIR_AddImm8, /*InsnID*/0, /*Imm*/1,
        GIR_MergeMemOperands, /*InsnID*/0, /*NumInsns*/1, /*MergeInsnID's*/0,
        GIR_ConstrainSelectedInstOperands, /*InsnID*/0,
        GIR_EraseFromParent, /*InsnID*/0,
        // GIR_Coverage, 3300,
        GIR_Done,
      // Label 5709: @414818
      GIM_Try, /*On fail goto*//*Label 5710*/ GIMT_Encode4(414883), // Rule ID 3360 //
        GIM_CheckFeatures, GIMT_Encode2(GIFBS_isGFX90APlus),
        GIM_CheckMemoryAddressSpace, /*MI*/0, /*MMO*/0, /*NumAddrSpace*/3, /*AddrSpace*/1, /*AddrSpace*/4, /*AddrSpace*/6,
        GIM_CheckRegBankForClass, /*MI*/0, /*Op*/0, /*RC*/GIMT_Encode2(AMDGPU::AV_64RegClassID),
        GIM_CheckPointerToAny, /*MI*/0, /*Op*/1, /*SizeInBits*/0,
        GIM_CheckComplexPattern, /*MI*/0, /*Op*/1, /*Renderer*/GIMT_Encode2(0), GIMT_Encode2(GICP_gi_global_offset),
        // (SIatomic_fmin:{ *:[f64] } (GlobalOffset:{ *:[iPTR] } i64:{ *:[i64] }:$vaddr, i32:{ *:[i32] }:$offset), f64:{ *:[f64] }:$data)<<P:Predicate_atomic_load_fmin_global_64>>  =>  (GLOBAL_ATOMIC_MIN_F64_RTN:{ *:[f64] } VReg_64:{ *:[i64] }:$vaddr, anonymous_15036:{ *:[f64] }:$data, ?:{ *:[i32] }:$offset)
        GIR_BuildMI, /*InsnID*/0, /*Opcode*/GIMT_Encode2(AMDGPU::GLOBAL_ATOMIC_MIN_F64_RTN),
        GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/0, // DstI[vdst]
        GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/0, // vaddr
        GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/2, // data
        GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/1, // offset
        GIR_AddImm8, /*InsnID*/0, /*Imm*/1,
        GIR_MergeMemOperands, /*InsnID*/0, /*NumInsns*/1, /*MergeInsnID's*/0,
        GIR_ConstrainSelectedInstOperands, /*InsnID*/0,
        GIR_EraseFromParent, /*InsnID*/0,
        // GIR_Coverage, 3360,
        GIR_Done,
      // Label 5710: @414883
      GIM_Try, /*On fail goto*//*Label 5711*/ GIMT_Encode4(414942), // Rule ID 3315 //
        GIM_CheckFeatures, GIMT_Encode2(GIFBS_isGFX10Only),
        GIM_CheckMemoryAddressSpace, /*MI*/0, /*MMO*/0, /*NumAddrSpace*/4, /*AddrSpace*/0, /*AddrSpace*/1, /*AddrSpace*/4, /*AddrSpace*/6,
        GIM_CheckHasNoUse, /*MI*/0,
        GIM_CheckPointerToAny, /*MI*/0, /*Op*/1, /*SizeInBits*/0,
        GIM_CheckComplexPattern, /*MI*/0, /*Op*/1, /*Renderer*/GIMT_Encode2(0), GIMT_Encode2(GICP_gi_global_offset),
        // (SIatomic_fmin:{ *:[f64] } (GlobalOffset:{ *:[iPTR] } i64:{ *:[i64] }:$vaddr, i32:{ *:[i32] }:$offset), f64:{ *:[f64] }:$data)<<P:Predicate_atomic_load_fmin_flat_noret_64>>  =>  (FLAT_ATOMIC_FMIN_X2 VReg_64:{ *:[i64] }:$vaddr, anonymous_15036:{ *:[f64] }:$data, ?:{ *:[i32] }:$offset)
        GIR_BuildMI, /*InsnID*/0, /*Opcode*/GIMT_Encode2(AMDGPU::FLAT_ATOMIC_FMIN_X2),
        GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/0, // vaddr
        GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/2, // data
        GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/1, // offset
        GIR_AddImm8, /*InsnID*/0, /*Imm*/0,
        GIR_MergeMemOperands, /*InsnID*/0, /*NumInsns*/1, /*MergeInsnID's*/0,
        GIR_ConstrainSelectedInstOperands, /*InsnID*/0,
        GIR_EraseFromParent, /*InsnID*/0,
        // GIR_Coverage, 3315,
        GIR_Done,
      // Label 5711: @414942
      GIM_Try, /*On fail goto*//*Label 5712*/ GIMT_Encode4(415001), // Rule ID 3385 //
        GIM_CheckFeatures, GIMT_Encode2(GIFBS_isGFX90APlus),
        GIM_CheckMemoryAddressSpace, /*MI*/0, /*MMO*/0, /*NumAddrSpace*/4, /*AddrSpace*/0, /*AddrSpace*/1, /*AddrSpace*/4, /*AddrSpace*/6,
        GIM_CheckHasNoUse, /*MI*/0,
        GIM_CheckPointerToAny, /*MI*/0, /*Op*/1, /*SizeInBits*/0,
        GIM_CheckComplexPattern, /*MI*/0, /*Op*/1, /*Renderer*/GIMT_Encode2(0), GIMT_Encode2(GICP_gi_global_offset),
        // (SIatomic_fmin:{ *:[f64] } (GlobalOffset:{ *:[iPTR] } i64:{ *:[i64] }:$vaddr, i32:{ *:[i32] }:$offset), f64:{ *:[f64] }:$data)<<P:Predicate_atomic_load_fmin_flat_noret_64>>  =>  (FLAT_ATOMIC_MIN_F64 VReg_64:{ *:[i64] }:$vaddr, anonymous_15036:{ *:[f64] }:$data, ?:{ *:[i32] }:$offset)
        GIR_BuildMI, /*InsnID*/0, /*Opcode*/GIMT_Encode2(AMDGPU::FLAT_ATOMIC_MIN_F64),
        GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/0, // vaddr
        GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/2, // data
        GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/1, // offset
        GIR_AddImm8, /*InsnID*/0, /*Imm*/0,
        GIR_MergeMemOperands, /*InsnID*/0, /*NumInsns*/1, /*MergeInsnID's*/0,
        GIR_ConstrainSelectedInstOperands, /*InsnID*/0,
        GIR_EraseFromParent, /*InsnID*/0,
        // GIR_Coverage, 3385,
        GIR_Done,
      // Label 5712: @415001
      GIM_Try, /*On fail goto*//*Label 5713*/ GIMT_Encode4(415067), // Rule ID 3314 //
        GIM_CheckFeatures, GIMT_Encode2(GIFBS_isGFX10Only),
        GIM_CheckMemoryAddressSpace, /*MI*/0, /*MMO*/0, /*NumAddrSpace*/4, /*AddrSpace*/0, /*AddrSpace*/1, /*AddrSpace*/4, /*AddrSpace*/6,
        GIM_CheckRegBankForClass, /*MI*/0, /*Op*/0, /*RC*/GIMT_Encode2(AMDGPU::AV_64RegClassID),
        GIM_CheckPointerToAny, /*MI*/0, /*Op*/1, /*SizeInBits*/0,
        GIM_CheckComplexPattern, /*MI*/0, /*Op*/1, /*Renderer*/GIMT_Encode2(0), GIMT_Encode2(GICP_gi_global_offset),
        // (SIatomic_fmin:{ *:[f64] } (GlobalOffset:{ *:[iPTR] } i64:{ *:[i64] }:$vaddr, i32:{ *:[i32] }:$offset), f64:{ *:[f64] }:$data)<<P:Predicate_atomic_load_fmin_flat_64>>  =>  (FLAT_ATOMIC_FMIN_X2_RTN:{ *:[f64] } VReg_64:{ *:[i64] }:$vaddr, anonymous_15036:{ *:[f64] }:$data, ?:{ *:[i32] }:$offset)
        GIR_BuildMI, /*InsnID*/0, /*Opcode*/GIMT_Encode2(AMDGPU::FLAT_ATOMIC_FMIN_X2_RTN),
        GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/0, // DstI[vdst]
        GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/0, // vaddr
        GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/2, // data
        GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/1, // offset
        GIR_AddImm8, /*InsnID*/0, /*Imm*/1,
        GIR_MergeMemOperands, /*InsnID*/0, /*NumInsns*/1, /*MergeInsnID's*/0,
        GIR_ConstrainSelectedInstOperands, /*InsnID*/0,
        GIR_EraseFromParent, /*InsnID*/0,
        // GIR_Coverage, 3314,
        GIR_Done,
      // Label 5713: @415067
      GIM_Try, /*On fail goto*//*Label 5714*/ GIMT_Encode4(415133), // Rule ID 3384 //
        GIM_CheckFeatures, GIMT_Encode2(GIFBS_isGFX90APlus),
        GIM_CheckMemoryAddressSpace, /*MI*/0, /*MMO*/0, /*NumAddrSpace*/4, /*AddrSpace*/0, /*AddrSpace*/1, /*AddrSpace*/4, /*AddrSpace*/6,
        GIM_CheckRegBankForClass, /*MI*/0, /*Op*/0, /*RC*/GIMT_Encode2(AMDGPU::AV_64RegClassID),
        GIM_CheckPointerToAny, /*MI*/0, /*Op*/1, /*SizeInBits*/0,
        GIM_CheckComplexPattern, /*MI*/0, /*Op*/1, /*Renderer*/GIMT_Encode2(0), GIMT_Encode2(GICP_gi_global_offset),
        // (SIatomic_fmin:{ *:[f64] } (GlobalOffset:{ *:[iPTR] } i64:{ *:[i64] }:$vaddr, i32:{ *:[i32] }:$offset), f64:{ *:[f64] }:$data)<<P:Predicate_atomic_load_fmin_flat_64>>  =>  (FLAT_ATOMIC_MIN_F64_RTN:{ *:[f64] } VReg_64:{ *:[i64] }:$vaddr, anonymous_15036:{ *:[f64] }:$data, ?:{ *:[i32] }:$offset)
        GIR_BuildMI, /*InsnID*/0, /*Opcode*/GIMT_Encode2(AMDGPU::FLAT_ATOMIC_MIN_F64_RTN),
        GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/0, // DstI[vdst]
        GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/0, // vaddr
        GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/2, // data
        GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/1, // offset
        GIR_AddImm8, /*InsnID*/0, /*Imm*/1,
        GIR_MergeMemOperands, /*InsnID*/0, /*NumInsns*/1, /*MergeInsnID's*/0,
        GIR_ConstrainSelectedInstOperands, /*InsnID*/0,
        GIR_EraseFromParent, /*InsnID*/0,
        // GIR_Coverage, 3384,
        GIR_Done,
      // Label 5714: @415133
      GIM_Reject,
    // Label 5696: @415134
    GIM_Reject,
    // Label 5682: @415135
    GIM_Reject,
    // Label 106: @415136
    GIM_SwitchType, /*MI*/0, /*Op*/0, /*[*/GIMT_Encode2(9), GIMT_Encode2(11), /*)*//*default:*//*Label 5717*/ GIMT_Encode4(417929),
    /*GILLT_s32*//*Label 5715*/ GIMT_Encode4(415155),
    /*GILLT_s64*//*Label 5716*/ GIMT_Encode4(416542),
    // Label 5715: @415155
    GIM_Try, /*On fail goto*//*Label 5718*/ GIMT_Encode4(416541),
      GIM_CheckType, /*MI*/0, /*Op*/1, /*Type*/GILLT_s32,
      GIM_CheckType, /*MI*/0, /*Op*/2, /*Type*/GILLT_v4s32,
      GIM_CheckType, /*MI*/0, /*Op*/3, /*Type*/GILLT_s32,
      GIM_CheckType, /*MI*/0, /*Op*/4, /*Type*/GILLT_s32,
      GIM_CheckType, /*MI*/0, /*Op*/5, /*Type*/GILLT_s32,
      GIM_Try, /*On fail goto*//*Label 5719*/ GIMT_Encode4(415258), // Rule ID 4749 //
        GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasUnrestrictedSOffset),
        GIM_CheckHasNoUse, /*MI*/0,
        GIM_CheckConstantInt8, /*MI*/0, /*Op*/3, 0,
        GIM_CheckConstantInt8, /*MI*/0, /*Op*/4, 0,
        // MIs[0] offset
        GIM_CheckIsImm, /*MI*/0, /*Op*/6,
        // MIs[0] auxiliary
        GIM_CheckIsImm, /*MI*/0, /*Op*/7,
        // MIs[0] Operand 8
        GIM_CheckLiteralInt, /*MI*/0, /*Op*/8, GIMT_Encode8(0),
        GIM_CheckComplexPattern, /*MI*/0, /*Op*/5, /*Renderer*/GIMT_Encode2(0), GIMT_Encode2(GICP_gi_buf_soffset),
        // (SIbuffer_atomic_add:{ *:[i32] } i32:{ *:[i32] }:$vdata_in, v4i32:{ *:[v4i32] }:$rsrc, 0:{ *:[i32] }, 0:{ *:[i32] }, (BUFSOffset:{ *:[i32] } i32:{ *:[i32] }:$soffset), (timm:{ *:[i32] }):$offset, (timm:{ *:[i32] }):$auxiliary, 0:{ *:[i1] })<<P:Predicate_SIbuffer_atomic_add_noret>>  =>  (BUFFER_ATOMIC_ADD_OFFSET anonymous_15037:{ *:[i32] }:$vdata_in, SReg_128:{ *:[v4i32] }:$rsrc, SCSrc_b32:{ *:[i32] }:$soffset, (timm:{ *:[i32] }):$offset, (extract_cpol:{ *:[i32] } ?:{ *:[i32] }:$auxiliary))
        GIR_BuildMI, /*InsnID*/0, /*Opcode*/GIMT_Encode2(AMDGPU::BUFFER_ATOMIC_ADD_OFFSET),
        GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/1, // vdata_in
        GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/2, // rsrc
        GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/0, // soffset
        GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/6, // offset
        GIR_CustomOperandRenderer, /*InsnID*/0, /*OldInsnID*/0, /*OpIdx*/7, /*OperandRenderer*/GIMT_Encode2(GICR_renderExtractCPol), // auxiliary
        GIR_MergeMemOperands, /*InsnID*/0, /*NumInsns*/1, /*MergeInsnID's*/0,
        GIR_ConstrainSelectedInstOperands, /*InsnID*/0,
        GIR_EraseFromParent, /*InsnID*/0,
        // GIR_Coverage, 4749,
        GIR_Done,
      // Label 5719: @415258
      GIM_Try, /*On fail goto*//*Label 5720*/ GIMT_Encode4(415333), // Rule ID 4757 //
        GIM_CheckHasNoUse, /*MI*/0,
        GIM_CheckConstantInt8, /*MI*/0, /*Op*/3, 0,
        GIM_CheckConstantInt8, /*MI*/0, /*Op*/4, 0,
        // MIs[0] offset
        GIM_CheckIsImm, /*MI*/0, /*Op*/6,
        // MIs[0] auxiliary
        GIM_CheckIsImm, /*MI*/0, /*Op*/7,
        // MIs[0] Operand 8
        GIM_CheckLiteralInt, /*MI*/0, /*Op*/8, GIMT_Encode8(0),
        GIM_CheckComplexPattern, /*MI*/0, /*Op*/5, /*Renderer*/GIMT_Encode2(0), GIMT_Encode2(GICP_gi_buf_soffset),
        // (SIbuffer_atomic_add:{ *:[i32] } i32:{ *:[i32] }:$vdata_in, v4i32:{ *:[v4i32] }:$rsrc, 0:{ *:[i32] }, 0:{ *:[i32] }, (BUFSOffset:{ *:[i32] } i32:{ *:[i32] }:$soffset), (timm:{ *:[i32] }):$offset, (timm:{ *:[i32] }):$auxiliary, 0:{ *:[i1] })<<P:Predicate_SIbuffer_atomic_add_noret>>  =>  (BUFFER_ATOMIC_ADD_VBUFFER_OFFSET anonymous_15037:{ *:[i32] }:$vdata_in, SReg_128:{ *:[v4i32] }:$rsrc, SCSrc_b32:{ *:[i32] }:$soffset, (timm:{ *:[i32] }):$offset, (extract_cpol:{ *:[i32] } ?:{ *:[i32] }:$auxiliary))
        GIR_BuildMI, /*InsnID*/0, /*Opcode*/GIMT_Encode2(AMDGPU::BUFFER_ATOMIC_ADD_VBUFFER_OFFSET),
        GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/1, // vdata_in
        GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/2, // rsrc
        GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/0, // soffset
        GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/6, // offset
        GIR_CustomOperandRenderer, /*InsnID*/0, /*OldInsnID*/0, /*OpIdx*/7, /*OperandRenderer*/GIMT_Encode2(GICR_renderExtractCPol), // auxiliary
        GIR_MergeMemOperands, /*InsnID*/0, /*NumInsns*/1, /*MergeInsnID's*/0,
        GIR_ConstrainSelectedInstOperands, /*InsnID*/0,
        GIR_EraseFromParent, /*InsnID*/0,
        // GIR_Coverage, 4757,
        GIR_Done,
      // Label 5720: @415333
      GIM_Try, /*On fail goto*//*Label 5721*/ GIMT_Encode4(415418), // Rule ID 4745 //
        GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasUnrestrictedSOffset),
        GIM_CheckRegBankForClass, /*MI*/0, /*Op*/0, /*RC*/GIMT_Encode2(AMDGPU::AV_32RegClassID),
        GIM_CheckConstantInt8, /*MI*/0, /*Op*/3, 0,
        GIM_CheckConstantInt8, /*MI*/0, /*Op*/4, 0,
        // MIs[0] offset
        GIM_CheckIsImm, /*MI*/0, /*Op*/6,
        // MIs[0] auxiliary
        GIM_CheckIsImm, /*MI*/0, /*Op*/7,
        // MIs[0] Operand 8
        GIM_CheckLiteralInt, /*MI*/0, /*Op*/8, GIMT_Encode8(0),
        GIM_CheckComplexPattern, /*MI*/0, /*Op*/5, /*Renderer*/GIMT_Encode2(0), GIMT_Encode2(GICP_gi_buf_soffset),
        // (SIbuffer_atomic_add:{ *:[i32] } i32:{ *:[i32] }:$vdata_in, v4i32:{ *:[v4i32] }:$rsrc, 0:{ *:[i32] }, 0:{ *:[i32] }, (BUFSOffset:{ *:[i32] } i32:{ *:[i32] }:$soffset), (timm:{ *:[i32] }):$offset, (timm:{ *:[i32] }):$auxiliary, 0:{ *:[i1] })  =>  (BUFFER_ATOMIC_ADD_OFFSET_RTN:{ *:[i32] } anonymous_15037:{ *:[i32] }:$vdata_in, SReg_128:{ *:[v4i32] }:$rsrc, SCSrc_b32:{ *:[i32] }:$soffset, (timm:{ *:[i32] }):$offset, (extract_cpol_set_glc:{ *:[i32] } ?:{ *:[i32] }:$auxiliary))
        GIR_BuildMI, /*InsnID*/0, /*Opcode*/GIMT_Encode2(AMDGPU::BUFFER_ATOMIC_ADD_OFFSET_RTN),
        GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/0, // DstI[vdata]
        GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/1, // vdata_in
        GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/2, // rsrc
        GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/0, // soffset
        GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/6, // offset
        GIR_CustomOperandRenderer, /*InsnID*/0, /*OldInsnID*/0, /*OpIdx*/7, /*OperandRenderer*/GIMT_Encode2(GICR_renderExtractCpolSetGLC), // auxiliary
        GIR_MergeMemOperands, /*InsnID*/0, /*NumInsns*/1, /*MergeInsnID's*/0,
        GIR_ConstrainSelectedInstOperands, /*InsnID*/0,
        GIR_EraseFromParent, /*InsnID*/0,
        // GIR_Coverage, 4745,
        GIR_Done,
      // Label 5721: @415418
      GIM_Try, /*On fail goto*//*Label 5722*/ GIMT_Encode4(415500), // Rule ID 4753 //
        GIM_CheckRegBankForClass, /*MI*/0, /*Op*/0, /*RC*/GIMT_Encode2(AMDGPU::AV_32RegClassID),
        GIM_CheckConstantInt8, /*MI*/0, /*Op*/3, 0,
        GIM_CheckConstantInt8, /*MI*/0, /*Op*/4, 0,
        // MIs[0] offset
        GIM_CheckIsImm, /*MI*/0, /*Op*/6,
        // MIs[0] auxiliary
        GIM_CheckIsImm, /*MI*/0, /*Op*/7,
        // MIs[0] Operand 8
        GIM_CheckLiteralInt, /*MI*/0, /*Op*/8, GIMT_Encode8(0),
        GIM_CheckComplexPattern, /*MI*/0, /*Op*/5, /*Renderer*/GIMT_Encode2(0), GIMT_Encode2(GICP_gi_buf_soffset),
        // (SIbuffer_atomic_add:{ *:[i32] } i32:{ *:[i32] }:$vdata_in, v4i32:{ *:[v4i32] }:$rsrc, 0:{ *:[i32] }, 0:{ *:[i32] }, (BUFSOffset:{ *:[i32] } i32:{ *:[i32] }:$soffset), (timm:{ *:[i32] }):$offset, (timm:{ *:[i32] }):$auxiliary, 0:{ *:[i1] })  =>  (BUFFER_ATOMIC_ADD_VBUFFER_OFFSET_RTN:{ *:[i32] } anonymous_15037:{ *:[i32] }:$vdata_in, SReg_128:{ *:[v4i32] }:$rsrc, SCSrc_b32:{ *:[i32] }:$soffset, (timm:{ *:[i32] }):$offset, (extract_cpol_set_glc:{ *:[i32] } ?:{ *:[i32] }:$auxiliary))
        GIR_BuildMI, /*InsnID*/0, /*Opcode*/GIMT_Encode2(AMDGPU::BUFFER_ATOMIC_ADD_VBUFFER_OFFSET_RTN),
        GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/0, // DstI[vdata]
        GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/1, // vdata_in
        GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/2, // rsrc
        GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/0, // soffset
        GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/6, // offset
        GIR_CustomOperandRenderer, /*InsnID*/0, /*OldInsnID*/0, /*OpIdx*/7, /*OperandRenderer*/GIMT_Encode2(GICR_renderExtractCpolSetGLC), // auxiliary
        GIR_MergeMemOperands, /*InsnID*/0, /*NumInsns*/1, /*MergeInsnID's*/0,
        GIR_ConstrainSelectedInstOperands, /*InsnID*/0,
        GIR_EraseFromParent, /*InsnID*/0,
        // GIR_Coverage, 4753,
        GIR_Done,
      // Label 5722: @415500
      GIM_Try, /*On fail goto*//*Label 5723*/ GIMT_Encode4(415578), // Rule ID 4751 //
        GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasUnrestrictedSOffset),
        GIM_CheckHasNoUse, /*MI*/0,
        GIM_CheckConstantInt8, /*MI*/0, /*Op*/3, 0,
        // MIs[0] offset
        GIM_CheckIsImm, /*MI*/0, /*Op*/6,
        // MIs[0] auxiliary
        GIM_CheckIsImm, /*MI*/0, /*Op*/7,
        // MIs[0] Operand 8
        GIM_CheckLiteralInt, /*MI*/0, /*Op*/8, GIMT_Encode8(0),
        GIM_CheckComplexPattern, /*MI*/0, /*Op*/5, /*Renderer*/GIMT_Encode2(0), GIMT_Encode2(GICP_gi_buf_soffset),
        // (SIbuffer_atomic_add:{ *:[i32] } i32:{ *:[i32] }:$vdata_in, v4i32:{ *:[v4i32] }:$rsrc, 0:{ *:[i32] }, i32:{ *:[i32] }:$voffset, (BUFSOffset:{ *:[i32] } i32:{ *:[i32] }:$soffset), (timm:{ *:[i32] }):$offset, (timm:{ *:[i32] }):$auxiliary, 0:{ *:[i1] })<<P:Predicate_SIbuffer_atomic_add_noret>>  =>  (BUFFER_ATOMIC_ADD_OFFEN anonymous_15037:{ *:[i32] }:$vdata_in, VGPR_32:{ *:[i32] }:$voffset, SReg_128:{ *:[v4i32] }:$rsrc, SCSrc_b32:{ *:[i32] }:$soffset, (timm:{ *:[i32] }):$offset, (extract_cpol:{ *:[i32] } ?:{ *:[i32] }:$auxiliary))
        GIR_BuildMI, /*InsnID*/0, /*Opcode*/GIMT_Encode2(AMDGPU::BUFFER_ATOMIC_ADD_OFFEN),
        GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/1, // vdata_in
        GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/4, // voffset
        GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/2, // rsrc
        GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/0, // soffset
        GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/6, // offset
        GIR_CustomOperandRenderer, /*InsnID*/0, /*OldInsnID*/0, /*OpIdx*/7, /*OperandRenderer*/GIMT_Encode2(GICR_renderExtractCPol), // auxiliary
        GIR_MergeMemOperands, /*InsnID*/0, /*NumInsns*/1, /*MergeInsnID's*/0,
        GIR_ConstrainSelectedInstOperands, /*InsnID*/0,
        GIR_EraseFromParent, /*InsnID*/0,
        // GIR_Coverage, 4751,
        GIR_Done,
      // Label 5723: @415578
      GIM_Try, /*On fail goto*//*Label 5724*/ GIMT_Encode4(415653), // Rule ID 4759 //
        GIM_CheckHasNoUse, /*MI*/0,
        GIM_CheckConstantInt8, /*MI*/0, /*Op*/3, 0,
        // MIs[0] offset
        GIM_CheckIsImm, /*MI*/0, /*Op*/6,
        // MIs[0] auxiliary
        GIM_CheckIsImm, /*MI*/0, /*Op*/7,
        // MIs[0] Operand 8
        GIM_CheckLiteralInt, /*MI*/0, /*Op*/8, GIMT_Encode8(0),
        GIM_CheckComplexPattern, /*MI*/0, /*Op*/5, /*Renderer*/GIMT_Encode2(0), GIMT_Encode2(GICP_gi_buf_soffset),
        // (SIbuffer_atomic_add:{ *:[i32] } i32:{ *:[i32] }:$vdata_in, v4i32:{ *:[v4i32] }:$rsrc, 0:{ *:[i32] }, i32:{ *:[i32] }:$voffset, (BUFSOffset:{ *:[i32] } i32:{ *:[i32] }:$soffset), (timm:{ *:[i32] }):$offset, (timm:{ *:[i32] }):$auxiliary, 0:{ *:[i1] })<<P:Predicate_SIbuffer_atomic_add_noret>>  =>  (BUFFER_ATOMIC_ADD_VBUFFER_OFFEN anonymous_15037:{ *:[i32] }:$vdata_in, VGPR_32:{ *:[i32] }:$voffset, SReg_128:{ *:[v4i32] }:$rsrc, SCSrc_b32:{ *:[i32] }:$soffset, (timm:{ *:[i32] }):$offset, (extract_cpol:{ *:[i32] } ?:{ *:[i32] }:$auxiliary))
        GIR_BuildMI, /*InsnID*/0, /*Opcode*/GIMT_Encode2(AMDGPU::BUFFER_ATOMIC_ADD_VBUFFER_OFFEN),
        GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/1, // vdata_in
        GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/4, // voffset
        GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/2, // rsrc
        GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/0, // soffset
        GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/6, // offset
        GIR_CustomOperandRenderer, /*InsnID*/0, /*OldInsnID*/0, /*OpIdx*/7, /*OperandRenderer*/GIMT_Encode2(GICR_renderExtractCPol), // auxiliary
        GIR_MergeMemOperands, /*InsnID*/0, /*NumInsns*/1, /*MergeInsnID's*/0,
        GIR_ConstrainSelectedInstOperands, /*InsnID*/0,
        GIR_EraseFromParent, /*InsnID*/0,
        // GIR_Coverage, 4759,
        GIR_Done,
      // Label 5724: @415653
      GIM_Try, /*On fail goto*//*Label 5725*/ GIMT_Encode4(415738), // Rule ID 4747 //
        GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasUnrestrictedSOffset),
        GIM_CheckRegBankForClass, /*MI*/0, /*Op*/0, /*RC*/GIMT_Encode2(AMDGPU::AV_32RegClassID),
        GIM_CheckConstantInt8, /*MI*/0, /*Op*/3, 0,
        // MIs[0] offset
        GIM_CheckIsImm, /*MI*/0, /*Op*/6,
        // MIs[0] auxiliary
        GIM_CheckIsImm, /*MI*/0, /*Op*/7,
        // MIs[0] Operand 8
        GIM_CheckLiteralInt, /*MI*/0, /*Op*/8, GIMT_Encode8(0),
        GIM_CheckComplexPattern, /*MI*/0, /*Op*/5, /*Renderer*/GIMT_Encode2(0), GIMT_Encode2(GICP_gi_buf_soffset),
        // (SIbuffer_atomic_add:{ *:[i32] } i32:{ *:[i32] }:$vdata_in, v4i32:{ *:[v4i32] }:$rsrc, 0:{ *:[i32] }, i32:{ *:[i32] }:$voffset, (BUFSOffset:{ *:[i32] } i32:{ *:[i32] }:$soffset), (timm:{ *:[i32] }):$offset, (timm:{ *:[i32] }):$auxiliary, 0:{ *:[i1] })  =>  (BUFFER_ATOMIC_ADD_OFFEN_RTN:{ *:[i32] } anonymous_15037:{ *:[i32] }:$vdata_in, VGPR_32:{ *:[i32] }:$voffset, SReg_128:{ *:[v4i32] }:$rsrc, SCSrc_b32:{ *:[i32] }:$soffset, (timm:{ *:[i32] }):$offset, (extract_cpol_set_glc:{ *:[i32] } ?:{ *:[i32] }:$auxiliary))
        GIR_BuildMI, /*InsnID*/0, /*Opcode*/GIMT_Encode2(AMDGPU::BUFFER_ATOMIC_ADD_OFFEN_RTN),
        GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/0, // DstI[vdata]
        GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/1, // vdata_in
        GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/4, // voffset
        GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/2, // rsrc
        GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/0, // soffset
        GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/6, // offset
        GIR_CustomOperandRenderer, /*InsnID*/0, /*OldInsnID*/0, /*OpIdx*/7, /*OperandRenderer*/GIMT_Encode2(GICR_renderExtractCpolSetGLC), // auxiliary
        GIR_MergeMemOperands, /*InsnID*/0, /*NumInsns*/1, /*MergeInsnID's*/0,
        GIR_ConstrainSelectedInstOperands, /*InsnID*/0,
        GIR_EraseFromParent, /*InsnID*/0,
        // GIR_Coverage, 4747,
        GIR_Done,
      // Label 5725: @415738
      GIM_Try, /*On fail goto*//*Label 5726*/ GIMT_Encode4(415820), // Rule ID 4755 //
        GIM_CheckRegBankForClass, /*MI*/0, /*Op*/0, /*RC*/GIMT_Encode2(AMDGPU::AV_32RegClassID),
        GIM_CheckConstantInt8, /*MI*/0, /*Op*/3, 0,
        // MIs[0] offset
        GIM_CheckIsImm, /*MI*/0, /*Op*/6,
        // MIs[0] auxiliary
        GIM_CheckIsImm, /*MI*/0, /*Op*/7,
        // MIs[0] Operand 8
        GIM_CheckLiteralInt, /*MI*/0, /*Op*/8, GIMT_Encode8(0),
        GIM_CheckComplexPattern, /*MI*/0, /*Op*/5, /*Renderer*/GIMT_Encode2(0), GIMT_Encode2(GICP_gi_buf_soffset),
        // (SIbuffer_atomic_add:{ *:[i32] } i32:{ *:[i32] }:$vdata_in, v4i32:{ *:[v4i32] }:$rsrc, 0:{ *:[i32] }, i32:{ *:[i32] }:$voffset, (BUFSOffset:{ *:[i32] } i32:{ *:[i32] }:$soffset), (timm:{ *:[i32] }):$offset, (timm:{ *:[i32] }):$auxiliary, 0:{ *:[i1] })  =>  (BUFFER_ATOMIC_ADD_VBUFFER_OFFEN_RTN:{ *:[i32] } anonymous_15037:{ *:[i32] }:$vdata_in, VGPR_32:{ *:[i32] }:$voffset, SReg_128:{ *:[v4i32] }:$rsrc, SCSrc_b32:{ *:[i32] }:$soffset, (timm:{ *:[i32] }):$offset, (extract_cpol_set_glc:{ *:[i32] } ?:{ *:[i32] }:$auxiliary))
        GIR_BuildMI, /*InsnID*/0, /*Opcode*/GIMT_Encode2(AMDGPU::BUFFER_ATOMIC_ADD_VBUFFER_OFFEN_RTN),
        GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/0, // DstI[vdata]
        GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/1, // vdata_in
        GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/4, // voffset
        GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/2, // rsrc
        GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/0, // soffset
        GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/6, // offset
        GIR_CustomOperandRenderer, /*InsnID*/0, /*OldInsnID*/0, /*OpIdx*/7, /*OperandRenderer*/GIMT_Encode2(GICR_renderExtractCpolSetGLC), // auxiliary
        GIR_MergeMemOperands, /*InsnID*/0, /*NumInsns*/1, /*MergeInsnID's*/0,
        GIR_ConstrainSelectedInstOperands, /*InsnID*/0,
        GIR_EraseFromParent, /*InsnID*/0,
        // GIR_Coverage, 4755,
        GIR_Done,
      // Label 5726: @415820
      GIM_Try, /*On fail goto*//*Label 5727*/ GIMT_Encode4(415890), // Rule ID 4750 //
        GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasUnrestrictedSOffset),
        GIM_CheckHasNoUse, /*MI*/0,
        GIM_CheckConstantInt8, /*MI*/0, /*Op*/4, 0,
        // MIs[0] offset
        GIM_CheckIsImm, /*MI*/0, /*Op*/6,
        // MIs[0] auxiliary
        GIM_CheckIsImm, /*MI*/0, /*Op*/7,
        // MIs[0] Operand 8
        GIM_CheckIsImm, /*MI*/0, /*Op*/8,
        GIM_CheckComplexPattern, /*MI*/0, /*Op*/5, /*Renderer*/GIMT_Encode2(0), GIMT_Encode2(GICP_gi_buf_soffset),
        // (SIbuffer_atomic_add:{ *:[i32] } i32:{ *:[i32] }:$vdata_in, v4i32:{ *:[v4i32] }:$rsrc, i32:{ *:[i32] }:$vindex, 0:{ *:[i32] }, (BUFSOffset:{ *:[i32] } i32:{ *:[i32] }:$soffset), (timm:{ *:[i32] }):$offset, (timm:{ *:[i32] }):$auxiliary, (timm:{ *:[i1] }))<<P:Predicate_SIbuffer_atomic_add_noret>>  =>  (BUFFER_ATOMIC_ADD_IDXEN anonymous_15037:{ *:[i32] }:$vdata_in, VGPR_32:{ *:[i32] }:$vindex, SReg_128:{ *:[v4i32] }:$rsrc, SCSrc_b32:{ *:[i32] }:$soffset, (timm:{ *:[i32] }):$offset, (extract_cpol:{ *:[i32] } ?:{ *:[i32] }:$auxiliary))
        GIR_BuildMI, /*InsnID*/0, /*Opcode*/GIMT_Encode2(AMDGPU::BUFFER_ATOMIC_ADD_IDXEN),
        GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/1, // vdata_in
        GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/3, // vindex
        GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/2, // rsrc
        GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/0, // soffset
        GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/6, // offset
        GIR_CustomOperandRenderer, /*InsnID*/0, /*OldInsnID*/0, /*OpIdx*/7, /*OperandRenderer*/GIMT_Encode2(GICR_renderExtractCPol), // auxiliary
        GIR_MergeMemOperands, /*InsnID*/0, /*NumInsns*/1, /*MergeInsnID's*/0,
        GIR_ConstrainSelectedInstOperands, /*InsnID*/0,
        GIR_EraseFromParent, /*InsnID*/0,
        // GIR_Coverage, 4750,
        GIR_Done,
      // Label 5727: @415890
      GIM_Try, /*On fail goto*//*Label 5728*/ GIMT_Encode4(415957), // Rule ID 4758 //
        GIM_CheckHasNoUse, /*MI*/0,
        GIM_CheckConstantInt8, /*MI*/0, /*Op*/4, 0,
        // MIs[0] offset
        GIM_CheckIsImm, /*MI*/0, /*Op*/6,
        // MIs[0] auxiliary
        GIM_CheckIsImm, /*MI*/0, /*Op*/7,
        // MIs[0] Operand 8
        GIM_CheckIsImm, /*MI*/0, /*Op*/8,
        GIM_CheckComplexPattern, /*MI*/0, /*Op*/5, /*Renderer*/GIMT_Encode2(0), GIMT_Encode2(GICP_gi_buf_soffset),
        // (SIbuffer_atomic_add:{ *:[i32] } i32:{ *:[i32] }:$vdata_in, v4i32:{ *:[v4i32] }:$rsrc, i32:{ *:[i32] }:$vindex, 0:{ *:[i32] }, (BUFSOffset:{ *:[i32] } i32:{ *:[i32] }:$soffset), (timm:{ *:[i32] }):$offset, (timm:{ *:[i32] }):$auxiliary, (timm:{ *:[i1] }))<<P:Predicate_SIbuffer_atomic_add_noret>>  =>  (BUFFER_ATOMIC_ADD_VBUFFER_IDXEN anonymous_15037:{ *:[i32] }:$vdata_in, VGPR_32:{ *:[i32] }:$vindex, SReg_128:{ *:[v4i32] }:$rsrc, SCSrc_b32:{ *:[i32] }:$soffset, (timm:{ *:[i32] }):$offset, (extract_cpol:{ *:[i32] } ?:{ *:[i32] }:$auxiliary))
        GIR_BuildMI, /*InsnID*/0, /*Opcode*/GIMT_Encode2(AMDGPU::BUFFER_ATOMIC_ADD_VBUFFER_IDXEN),
        GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/1, // vdata_in
        GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/3, // vindex
        GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/2, // rsrc
        GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/0, // soffset
        GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/6, // offset
        GIR_CustomOperandRenderer, /*InsnID*/0, /*OldInsnID*/0, /*OpIdx*/7, /*OperandRenderer*/GIMT_Encode2(GICR_renderExtractCPol), // auxiliary
        GIR_MergeMemOperands, /*InsnID*/0, /*NumInsns*/1, /*MergeInsnID's*/0,
        GIR_ConstrainSelectedInstOperands, /*InsnID*/0,
        GIR_EraseFromParent, /*InsnID*/0,
        // GIR_Coverage, 4758,
        GIR_Done,
      // Label 5728: @415957
      GIM_Try, /*On fail goto*//*Label 5729*/ GIMT_Encode4(416034), // Rule ID 4746 //
        GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasUnrestrictedSOffset),
        GIM_CheckRegBankForClass, /*MI*/0, /*Op*/0, /*RC*/GIMT_Encode2(AMDGPU::AV_32RegClassID),
        GIM_CheckConstantInt8, /*MI*/0, /*Op*/4, 0,
        // MIs[0] offset
        GIM_CheckIsImm, /*MI*/0, /*Op*/6,
        // MIs[0] auxiliary
        GIM_CheckIsImm, /*MI*/0, /*Op*/7,
        // MIs[0] Operand 8
        GIM_CheckIsImm, /*MI*/0, /*Op*/8,
        GIM_CheckComplexPattern, /*MI*/0, /*Op*/5, /*Renderer*/GIMT_Encode2(0), GIMT_Encode2(GICP_gi_buf_soffset),
        // (SIbuffer_atomic_add:{ *:[i32] } i32:{ *:[i32] }:$vdata_in, v4i32:{ *:[v4i32] }:$rsrc, i32:{ *:[i32] }:$vindex, 0:{ *:[i32] }, (BUFSOffset:{ *:[i32] } i32:{ *:[i32] }:$soffset), (timm:{ *:[i32] }):$offset, (timm:{ *:[i32] }):$auxiliary, (timm:{ *:[i1] }))  =>  (BUFFER_ATOMIC_ADD_IDXEN_RTN:{ *:[i32] } anonymous_15037:{ *:[i32] }:$vdata_in, VGPR_32:{ *:[i32] }:$vindex, SReg_128:{ *:[v4i32] }:$rsrc, SCSrc_b32:{ *:[i32] }:$soffset, (timm:{ *:[i32] }):$offset, (extract_cpol_set_glc:{ *:[i32] } ?:{ *:[i32] }:$auxiliary))
        GIR_BuildMI, /*InsnID*/0, /*Opcode*/GIMT_Encode2(AMDGPU::BUFFER_ATOMIC_ADD_IDXEN_RTN),
        GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/0, // DstI[vdata]
        GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/1, // vdata_in
        GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/3, // vindex
        GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/2, // rsrc
        GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/0, // soffset
        GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/6, // offset
        GIR_CustomOperandRenderer, /*InsnID*/0, /*OldInsnID*/0, /*OpIdx*/7, /*OperandRenderer*/GIMT_Encode2(GICR_renderExtractCpolSetGLC), // auxiliary
        GIR_MergeMemOperands, /*InsnID*/0, /*NumInsns*/1, /*MergeInsnID's*/0,
        GIR_ConstrainSelectedInstOperands, /*InsnID*/0,
        GIR_EraseFromParent, /*InsnID*/0,
        // GIR_Coverage, 4746,
        GIR_Done,
      // Label 5729: @416034
      GIM_Try, /*On fail goto*//*Label 5730*/ GIMT_Encode4(416108), // Rule ID 4754 //
        GIM_CheckRegBankForClass, /*MI*/0, /*Op*/0, /*RC*/GIMT_Encode2(AMDGPU::AV_32RegClassID),
        GIM_CheckConstantInt8, /*MI*/0, /*Op*/4, 0,
        // MIs[0] offset
        GIM_CheckIsImm, /*MI*/0, /*Op*/6,
        // MIs[0] auxiliary
        GIM_CheckIsImm, /*MI*/0, /*Op*/7,
        // MIs[0] Operand 8
        GIM_CheckIsImm, /*MI*/0, /*Op*/8,
        GIM_CheckComplexPattern, /*MI*/0, /*Op*/5, /*Renderer*/GIMT_Encode2(0), GIMT_Encode2(GICP_gi_buf_soffset),
        // (SIbuffer_atomic_add:{ *:[i32] } i32:{ *:[i32] }:$vdata_in, v4i32:{ *:[v4i32] }:$rsrc, i32:{ *:[i32] }:$vindex, 0:{ *:[i32] }, (BUFSOffset:{ *:[i32] } i32:{ *:[i32] }:$soffset), (timm:{ *:[i32] }):$offset, (timm:{ *:[i32] }):$auxiliary, (timm:{ *:[i1] }))  =>  (BUFFER_ATOMIC_ADD_VBUFFER_IDXEN_RTN:{ *:[i32] } anonymous_15037:{ *:[i32] }:$vdata_in, VGPR_32:{ *:[i32] }:$vindex, SReg_128:{ *:[v4i32] }:$rsrc, SCSrc_b32:{ *:[i32] }:$soffset, (timm:{ *:[i32] }):$offset, (extract_cpol_set_glc:{ *:[i32] } ?:{ *:[i32] }:$auxiliary))
        GIR_BuildMI, /*InsnID*/0, /*Opcode*/GIMT_Encode2(AMDGPU::BUFFER_ATOMIC_ADD_VBUFFER_IDXEN_RTN),
        GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/0, // DstI[vdata]
        GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/1, // vdata_in
        GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/3, // vindex
        GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/2, // rsrc
        GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/0, // soffset
        GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/6, // offset
        GIR_CustomOperandRenderer, /*InsnID*/0, /*OldInsnID*/0, /*OpIdx*/7, /*OperandRenderer*/GIMT_Encode2(GICR_renderExtractCpolSetGLC), // auxiliary
        GIR_MergeMemOperands, /*InsnID*/0, /*NumInsns*/1, /*MergeInsnID's*/0,
        GIR_ConstrainSelectedInstOperands, /*InsnID*/0,
        GIR_EraseFromParent, /*InsnID*/0,
        // GIR_Coverage, 4754,
        GIR_Done,
      // Label 5730: @416108
      GIM_Try, /*On fail goto*//*Label 5731*/ GIMT_Encode4(416214), // Rule ID 4752 //
        GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasUnrestrictedSOffset),
        GIM_CheckHasNoUse, /*MI*/0,
        // MIs[0] offset
        GIM_CheckIsImm, /*MI*/0, /*Op*/6,
        // MIs[0] auxiliary
        GIM_CheckIsImm, /*MI*/0, /*Op*/7,
        // MIs[0] Operand 8
        GIM_CheckIsImm, /*MI*/0, /*Op*/8,
        GIM_CheckComplexPattern, /*MI*/0, /*Op*/5, /*Renderer*/GIMT_Encode2(0), GIMT_Encode2(GICP_gi_buf_soffset),
        // (SIbuffer_atomic_add:{ *:[i32] } i32:{ *:[i32] }:$vdata_in, v4i32:{ *:[v4i32] }:$rsrc, i32:{ *:[i32] }:$vindex, i32:{ *:[i32] }:$voffset, (BUFSOffset:{ *:[i32] } i32:{ *:[i32] }:$soffset), (timm:{ *:[i32] }):$offset, (timm:{ *:[i32] }):$auxiliary, (timm:{ *:[i1] }))<<P:Predicate_SIbuffer_atomic_add_noret>>  =>  (BUFFER_ATOMIC_ADD_BOTHEN anonymous_15037:{ *:[i32] }:$vdata_in, (REG_SEQUENCE:{ *:[i64] } VReg_64:{ *:[i32] }, VGPR_32:{ *:[i32] }:$vindex, sub0:{ *:[i32] }, VGPR_32:{ *:[i32] }:$voffset, sub1:{ *:[i32] }), SReg_128:{ *:[v4i32] }:$rsrc, SCSrc_b32:{ *:[i32] }:$soffset, (timm:{ *:[i32] }):$offset, (extract_cpol:{ *:[i32] } ?:{ *:[i32] }:$auxiliary))
        GIR_MakeTempReg, /*TempRegID*/0, /*TypeID*/GILLT_s64,
        GIR_BuildMI, /*InsnID*/1, /*Opcode*/GIMT_Encode2(TargetOpcode::REG_SEQUENCE),
        GIR_AddTempRegister, /*InsnID*/1, /*TempRegID*/0, /*TempRegFlags*/GIMT_Encode2(RegState::Define),
        GIR_Copy, /*NewInsnID*/1, /*OldInsnID*/0, /*OpIdx*/3, // vindex
        GIR_AddImm8, /*InsnID*/1, /*SubRegIndex*/3,
        GIR_Copy, /*NewInsnID*/1, /*OldInsnID*/0, /*OpIdx*/4, // voffset
        GIR_AddImm8, /*InsnID*/1, /*SubRegIndex*/11,
        GIR_ConstrainOperandRC, /*InsnID*/1, /*Op*/0, GIMT_Encode2(AMDGPU::VReg_64RegClassID),
        GIR_ConstrainOperandRC, /*InsnID*/1, /*Op*/1, GIMT_Encode2(AMDGPU::VGPR_32RegClassID),
        GIR_ConstrainOperandRC, /*InsnID*/1, /*Op*/3, GIMT_Encode2(AMDGPU::VGPR_32RegClassID),
        GIR_BuildMI, /*InsnID*/0, /*Opcode*/GIMT_Encode2(AMDGPU::BUFFER_ATOMIC_ADD_BOTHEN),
        GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/1, // vdata_in
        GIR_AddSimpleTempRegister, /*InsnID*/0, /*TempRegID*/0,
        GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/2, // rsrc
        GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/0, // soffset
        GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/6, // offset
        GIR_CustomOperandRenderer, /*InsnID*/0, /*OldInsnID*/0, /*OpIdx*/7, /*OperandRenderer*/GIMT_Encode2(GICR_renderExtractCPol), // auxiliary
        GIR_MergeMemOperands, /*InsnID*/0, /*NumInsns*/1, /*MergeInsnID's*/0,
        GIR_ConstrainSelectedInstOperands, /*InsnID*/0,
        GIR_EraseFromParent, /*InsnID*/0,
        // GIR_Coverage, 4752,
        GIR_Done,
      // Label 5731: @416214
      GIM_Try, /*On fail goto*//*Label 5732*/ GIMT_Encode4(416317), // Rule ID 4760 //
        GIM_CheckHasNoUse, /*MI*/0,
        // MIs[0] offset
        GIM_CheckIsImm, /*MI*/0, /*Op*/6,
        // MIs[0] auxiliary
        GIM_CheckIsImm, /*MI*/0, /*Op*/7,
        // MIs[0] Operand 8
        GIM_CheckIsImm, /*MI*/0, /*Op*/8,
        GIM_CheckComplexPattern, /*MI*/0, /*Op*/5, /*Renderer*/GIMT_Encode2(0), GIMT_Encode2(GICP_gi_buf_soffset),
        // (SIbuffer_atomic_add:{ *:[i32] } i32:{ *:[i32] }:$vdata_in, v4i32:{ *:[v4i32] }:$rsrc, i32:{ *:[i32] }:$vindex, i32:{ *:[i32] }:$voffset, (BUFSOffset:{ *:[i32] } i32:{ *:[i32] }:$soffset), (timm:{ *:[i32] }):$offset, (timm:{ *:[i32] }):$auxiliary, (timm:{ *:[i1] }))<<P:Predicate_SIbuffer_atomic_add_noret>>  =>  (BUFFER_ATOMIC_ADD_VBUFFER_BOTHEN anonymous_15037:{ *:[i32] }:$vdata_in, (REG_SEQUENCE:{ *:[i64] } VReg_64:{ *:[i32] }, VGPR_32:{ *:[i32] }:$vindex, sub0:{ *:[i32] }, VGPR_32:{ *:[i32] }:$voffset, sub1:{ *:[i32] }), SReg_128:{ *:[v4i32] }:$rsrc, SCSrc_b32:{ *:[i32] }:$soffset, (timm:{ *:[i32] }):$offset, (extract_cpol:{ *:[i32] } ?:{ *:[i32] }:$auxiliary))
        GIR_MakeTempReg, /*TempRegID*/0, /*TypeID*/GILLT_s64,
        GIR_BuildMI, /*InsnID*/1, /*Opcode*/GIMT_Encode2(TargetOpcode::REG_SEQUENCE),
        GIR_AddTempRegister, /*InsnID*/1, /*TempRegID*/0, /*TempRegFlags*/GIMT_Encode2(RegState::Define),
        GIR_Copy, /*NewInsnID*/1, /*OldInsnID*/0, /*OpIdx*/3, // vindex
        GIR_AddImm8, /*InsnID*/1, /*SubRegIndex*/3,
        GIR_Copy, /*NewInsnID*/1, /*OldInsnID*/0, /*OpIdx*/4, // voffset
        GIR_AddImm8, /*InsnID*/1, /*SubRegIndex*/11,
        GIR_ConstrainOperandRC, /*InsnID*/1, /*Op*/0, GIMT_Encode2(AMDGPU::VReg_64RegClassID),
        GIR_ConstrainOperandRC, /*InsnID*/1, /*Op*/1, GIMT_Encode2(AMDGPU::VGPR_32RegClassID),
        GIR_ConstrainOperandRC, /*InsnID*/1, /*Op*/3, GIMT_Encode2(AMDGPU::VGPR_32RegClassID),
        GIR_BuildMI, /*InsnID*/0, /*Opcode*/GIMT_Encode2(AMDGPU::BUFFER_ATOMIC_ADD_VBUFFER_BOTHEN),
        GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/1, // vdata_in
        GIR_AddSimpleTempRegister, /*InsnID*/0, /*TempRegID*/0,
        GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/2, // rsrc
        GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/0, // soffset
        GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/6, // offset
        GIR_CustomOperandRenderer, /*InsnID*/0, /*OldInsnID*/0, /*OpIdx*/7, /*OperandRenderer*/GIMT_Encode2(GICR_renderExtractCPol), // auxiliary
        GIR_MergeMemOperands, /*InsnID*/0, /*NumInsns*/1, /*MergeInsnID's*/0,
        GIR_ConstrainSelectedInstOperands, /*InsnID*/0,
        GIR_EraseFromParent, /*InsnID*/0,
        // GIR_Coverage, 4760,
        GIR_Done,
      // Label 5732: @416317
      GIM_Try, /*On fail goto*//*Label 5733*/ GIMT_Encode4(416430), // Rule ID 4748 //
        GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasUnrestrictedSOffset),
        GIM_CheckRegBankForClass, /*MI*/0, /*Op*/0, /*RC*/GIMT_Encode2(AMDGPU::AV_32RegClassID),
        // MIs[0] offset
        GIM_CheckIsImm, /*MI*/0, /*Op*/6,
        // MIs[0] auxiliary
        GIM_CheckIsImm, /*MI*/0, /*Op*/7,
        // MIs[0] Operand 8
        GIM_CheckIsImm, /*MI*/0, /*Op*/8,
        GIM_CheckComplexPattern, /*MI*/0, /*Op*/5, /*Renderer*/GIMT_Encode2(0), GIMT_Encode2(GICP_gi_buf_soffset),
        // (SIbuffer_atomic_add:{ *:[i32] } i32:{ *:[i32] }:$vdata_in, v4i32:{ *:[v4i32] }:$rsrc, i32:{ *:[i32] }:$vindex, i32:{ *:[i32] }:$voffset, (BUFSOffset:{ *:[i32] } i32:{ *:[i32] }:$soffset), (timm:{ *:[i32] }):$offset, (timm:{ *:[i32] }):$auxiliary, (timm:{ *:[i1] }))  =>  (BUFFER_ATOMIC_ADD_BOTHEN_RTN:{ *:[i32] } anonymous_15037:{ *:[i32] }:$vdata_in, (REG_SEQUENCE:{ *:[i64] } VReg_64:{ *:[i32] }, VGPR_32:{ *:[i32] }:$vindex, sub0:{ *:[i32] }, VGPR_32:{ *:[i32] }:$voffset, sub1:{ *:[i32] }), SReg_128:{ *:[v4i32] }:$rsrc, SCSrc_b32:{ *:[i32] }:$soffset, (timm:{ *:[i32] }):$offset, (extract_cpol_set_glc:{ *:[i32] } ?:{ *:[i32] }:$auxiliary))
        GIR_MakeTempReg, /*TempRegID*/0, /*TypeID*/GILLT_s64,
        GIR_BuildMI, /*InsnID*/1, /*Opcode*/GIMT_Encode2(TargetOpcode::REG_SEQUENCE),
        GIR_AddTempRegister, /*InsnID*/1, /*TempRegID*/0, /*TempRegFlags*/GIMT_Encode2(RegState::Define),
        GIR_Copy, /*NewInsnID*/1, /*OldInsnID*/0, /*OpIdx*/3, // vindex
        GIR_AddImm8, /*InsnID*/1, /*SubRegIndex*/3,
        GIR_Copy, /*NewInsnID*/1, /*OldInsnID*/0, /*OpIdx*/4, // voffset
        GIR_AddImm8, /*InsnID*/1, /*SubRegIndex*/11,
        GIR_ConstrainOperandRC, /*InsnID*/1, /*Op*/0, GIMT_Encode2(AMDGPU::VReg_64RegClassID),
        GIR_ConstrainOperandRC, /*InsnID*/1, /*Op*/1, GIMT_Encode2(AMDGPU::VGPR_32RegClassID),
        GIR_ConstrainOperandRC, /*InsnID*/1, /*Op*/3, GIMT_Encode2(AMDGPU::VGPR_32RegClassID),
        GIR_BuildMI, /*InsnID*/0, /*Opcode*/GIMT_Encode2(AMDGPU::BUFFER_ATOMIC_ADD_BOTHEN_RTN),
        GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/0, // DstI[vdata]
        GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/1, // vdata_in
        GIR_AddSimpleTempRegister, /*InsnID*/0, /*TempRegID*/0,
        GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/2, // rsrc
        GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/0, // soffset
        GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/6, // offset
        GIR_CustomOperandRenderer, /*InsnID*/0, /*OldInsnID*/0, /*OpIdx*/7, /*OperandRenderer*/GIMT_Encode2(GICR_renderExtractCpolSetGLC), // auxiliary
        GIR_MergeMemOperands, /*InsnID*/0, /*NumInsns*/1, /*MergeInsnID's*/0,
        GIR_ConstrainSelectedInstOperands, /*InsnID*/0,
        GIR_EraseFromParent, /*InsnID*/0,
        // GIR_Coverage, 4748,
        GIR_Done,
      // Label 5733: @416430
      GIM_Try, /*On fail goto*//*Label 5734*/ GIMT_Encode4(416540), // Rule ID 4756 //
        GIM_CheckRegBankForClass, /*MI*/0, /*Op*/0, /*RC*/GIMT_Encode2(AMDGPU::AV_32RegClassID),
        // MIs[0] offset
        GIM_CheckIsImm, /*MI*/0, /*Op*/6,
        // MIs[0] auxiliary
        GIM_CheckIsImm, /*MI*/0, /*Op*/7,
        // MIs[0] Operand 8
        GIM_CheckIsImm, /*MI*/0, /*Op*/8,
        GIM_CheckComplexPattern, /*MI*/0, /*Op*/5, /*Renderer*/GIMT_Encode2(0), GIMT_Encode2(GICP_gi_buf_soffset),
        // (SIbuffer_atomic_add:{ *:[i32] } i32:{ *:[i32] }:$vdata_in, v4i32:{ *:[v4i32] }:$rsrc, i32:{ *:[i32] }:$vindex, i32:{ *:[i32] }:$voffset, (BUFSOffset:{ *:[i32] } i32:{ *:[i32] }:$soffset), (timm:{ *:[i32] }):$offset, (timm:{ *:[i32] }):$auxiliary, (timm:{ *:[i1] }))  =>  (BUFFER_ATOMIC_ADD_VBUFFER_BOTHEN_RTN:{ *:[i32] } anonymous_15037:{ *:[i32] }:$vdata_in, (REG_SEQUENCE:{ *:[i64] } VReg_64:{ *:[i32] }, VGPR_32:{ *:[i32] }:$vindex, sub0:{ *:[i32] }, VGPR_32:{ *:[i32] }:$voffset, sub1:{ *:[i32] }), SReg_128:{ *:[v4i32] }:$rsrc, SCSrc_b32:{ *:[i32] }:$soffset, (timm:{ *:[i32] }):$offset, (extract_cpol_set_glc:{ *:[i32] } ?:{ *:[i32] }:$auxiliary))
        GIR_MakeTempReg, /*TempRegID*/0, /*TypeID*/GILLT_s64,
        GIR_BuildMI, /*InsnID*/1, /*Opcode*/GIMT_Encode2(TargetOpcode::REG_SEQUENCE),
        GIR_AddTempRegister, /*InsnID*/1, /*TempRegID*/0, /*TempRegFlags*/GIMT_Encode2(RegState::Define),
        GIR_Copy, /*NewInsnID*/1, /*OldInsnID*/0, /*OpIdx*/3, // vindex
        GIR_AddImm8, /*InsnID*/1, /*SubRegIndex*/3,
        GIR_Copy, /*NewInsnID*/1, /*OldInsnID*/0, /*OpIdx*/4, // voffset
        GIR_AddImm8, /*InsnID*/1, /*SubRegIndex*/11,
        GIR_ConstrainOperandRC, /*InsnID*/1, /*Op*/0, GIMT_Encode2(AMDGPU::VReg_64RegClassID),
        GIR_ConstrainOperandRC, /*InsnID*/1, /*Op*/1, GIMT_Encode2(AMDGPU::VGPR_32RegClassID),
        GIR_ConstrainOperandRC, /*InsnID*/1, /*Op*/3, GIMT_Encode2(AMDGPU::VGPR_32RegClassID),
        GIR_BuildMI, /*InsnID*/0, /*Opcode*/GIMT_Encode2(AMDGPU::BUFFER_ATOMIC_ADD_VBUFFER_BOTHEN_RTN),
        GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/0, // DstI[vdata]
        GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/1, // vdata_in
        GIR_AddSimpleTempRegister, /*InsnID*/0, /*TempRegID*/0,
        GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/2, // rsrc
        GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/0, // soffset
        GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/6, // offset
        GIR_CustomOperandRenderer, /*InsnID*/0, /*OldInsnID*/0, /*OpIdx*/7, /*OperandRenderer*/GIMT_Encode2(GICR_renderExtractCpolSetGLC), // auxiliary
        GIR_MergeMemOperands, /*InsnID*/0, /*NumInsns*/1, /*MergeInsnID's*/0,
        GIR_ConstrainSelectedInstOperands, /*InsnID*/0,
        GIR_EraseFromParent, /*InsnID*/0,
        // GIR_Coverage, 4756,
        GIR_Done,
      // Label 5734: @416540
      GIM_Reject,
    // Label 5718: @416541
    GIM_Reject,
    // Label 5716: @416542
    GIM_Try, /*On fail goto*//*Label 5735*/ GIMT_Encode4(417928),
      GIM_CheckType, /*MI*/0, /*Op*/1, /*Type*/GILLT_s64,
      GIM_CheckType, /*MI*/0, /*Op*/2, /*Type*/GILLT_v4s32,
      GIM_CheckType, /*MI*/0, /*Op*/3, /*Type*/GILLT_s32,
      GIM_CheckType, /*MI*/0, /*Op*/4, /*Type*/GILLT_s32,
      GIM_CheckType, /*MI*/0, /*Op*/5, /*Type*/GILLT_s32,
      GIM_Try, /*On fail goto*//*Label 5736*/ GIMT_Encode4(416645), // Rule ID 4949 //
        GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasUnrestrictedSOffset),
        GIM_CheckHasNoUse, /*MI*/0,
        GIM_CheckConstantInt8, /*MI*/0, /*Op*/3, 0,
        GIM_CheckConstantInt8, /*MI*/0, /*Op*/4, 0,
        // MIs[0] offset
        GIM_CheckIsImm, /*MI*/0, /*Op*/6,
        // MIs[0] auxiliary
        GIM_CheckIsImm, /*MI*/0, /*Op*/7,
        // MIs[0] Operand 8
        GIM_CheckLiteralInt, /*MI*/0, /*Op*/8, GIMT_Encode8(0),
        GIM_CheckComplexPattern, /*MI*/0, /*Op*/5, /*Renderer*/GIMT_Encode2(0), GIMT_Encode2(GICP_gi_buf_soffset),
        // (SIbuffer_atomic_add:{ *:[i64] } i64:{ *:[i64] }:$vdata_in, v4i32:{ *:[v4i32] }:$rsrc, 0:{ *:[i32] }, 0:{ *:[i32] }, (BUFSOffset:{ *:[i32] } i32:{ *:[i32] }:$soffset), (timm:{ *:[i32] }):$offset, (timm:{ *:[i32] }):$auxiliary, 0:{ *:[i1] })<<P:Predicate_SIbuffer_atomic_add_noret>>  =>  (BUFFER_ATOMIC_ADD_X2_OFFSET anonymous_15036:{ *:[i64] }:$vdata_in, SReg_128:{ *:[v4i32] }:$rsrc, SCSrc_b32:{ *:[i32] }:$soffset, (timm:{ *:[i32] }):$offset, (extract_cpol:{ *:[i32] } ?:{ *:[i32] }:$auxiliary))
        GIR_BuildMI, /*InsnID*/0, /*Opcode*/GIMT_Encode2(AMDGPU::BUFFER_ATOMIC_ADD_X2_OFFSET),
        GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/1, // vdata_in
        GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/2, // rsrc
        GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/0, // soffset
        GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/6, // offset
        GIR_CustomOperandRenderer, /*InsnID*/0, /*OldInsnID*/0, /*OpIdx*/7, /*OperandRenderer*/GIMT_Encode2(GICR_renderExtractCPol), // auxiliary
        GIR_MergeMemOperands, /*InsnID*/0, /*NumInsns*/1, /*MergeInsnID's*/0,
        GIR_ConstrainSelectedInstOperands, /*InsnID*/0,
        GIR_EraseFromParent, /*InsnID*/0,
        // GIR_Coverage, 4949,
        GIR_Done,
      // Label 5736: @416645
      GIM_Try, /*On fail goto*//*Label 5737*/ GIMT_Encode4(416720), // Rule ID 4957 //
        GIM_CheckHasNoUse, /*MI*/0,
        GIM_CheckConstantInt8, /*MI*/0, /*Op*/3, 0,
        GIM_CheckConstantInt8, /*MI*/0, /*Op*/4, 0,
        // MIs[0] offset
        GIM_CheckIsImm, /*MI*/0, /*Op*/6,
        // MIs[0] auxiliary
        GIM_CheckIsImm, /*MI*/0, /*Op*/7,
        // MIs[0] Operand 8
        GIM_CheckLiteralInt, /*MI*/0, /*Op*/8, GIMT_Encode8(0),
        GIM_CheckComplexPattern, /*MI*/0, /*Op*/5, /*Renderer*/GIMT_Encode2(0), GIMT_Encode2(GICP_gi_buf_soffset),
        // (SIbuffer_atomic_add:{ *:[i64] } i64:{ *:[i64] }:$vdata_in, v4i32:{ *:[v4i32] }:$rsrc, 0:{ *:[i32] }, 0:{ *:[i32] }, (BUFSOffset:{ *:[i32] } i32:{ *:[i32] }:$soffset), (timm:{ *:[i32] }):$offset, (timm:{ *:[i32] }):$auxiliary, 0:{ *:[i1] })<<P:Predicate_SIbuffer_atomic_add_noret>>  =>  (BUFFER_ATOMIC_ADD_X2_VBUFFER_OFFSET anonymous_15036:{ *:[i64] }:$vdata_in, SReg_128:{ *:[v4i32] }:$rsrc, SCSrc_b32:{ *:[i32] }:$soffset, (timm:{ *:[i32] }):$offset, (extract_cpol:{ *:[i32] } ?:{ *:[i32] }:$auxiliary))
        GIR_BuildMI, /*InsnID*/0, /*Opcode*/GIMT_Encode2(AMDGPU::BUFFER_ATOMIC_ADD_X2_VBUFFER_OFFSET),
        GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/1, // vdata_in
        GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/2, // rsrc
        GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/0, // soffset
        GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/6, // offset
        GIR_CustomOperandRenderer, /*InsnID*/0, /*OldInsnID*/0, /*OpIdx*/7, /*OperandRenderer*/GIMT_Encode2(GICR_renderExtractCPol), // auxiliary
        GIR_MergeMemOperands, /*InsnID*/0, /*NumInsns*/1, /*MergeInsnID's*/0,
        GIR_ConstrainSelectedInstOperands, /*InsnID*/0,
        GIR_EraseFromParent, /*InsnID*/0,
        // GIR_Coverage, 4957,
        GIR_Done,
      // Label 5737: @416720
      GIM_Try, /*On fail goto*//*Label 5738*/ GIMT_Encode4(416805), // Rule ID 4945 //
        GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasUnrestrictedSOffset),
        GIM_CheckRegBankForClass, /*MI*/0, /*Op*/0, /*RC*/GIMT_Encode2(AMDGPU::AV_64RegClassID),
        GIM_CheckConstantInt8, /*MI*/0, /*Op*/3, 0,
        GIM_CheckConstantInt8, /*MI*/0, /*Op*/4, 0,
        // MIs[0] offset
        GIM_CheckIsImm, /*MI*/0, /*Op*/6,
        // MIs[0] auxiliary
        GIM_CheckIsImm, /*MI*/0, /*Op*/7,
        // MIs[0] Operand 8
        GIM_CheckLiteralInt, /*MI*/0, /*Op*/8, GIMT_Encode8(0),
        GIM_CheckComplexPattern, /*MI*/0, /*Op*/5, /*Renderer*/GIMT_Encode2(0), GIMT_Encode2(GICP_gi_buf_soffset),
        // (SIbuffer_atomic_add:{ *:[i64] } i64:{ *:[i64] }:$vdata_in, v4i32:{ *:[v4i32] }:$rsrc, 0:{ *:[i32] }, 0:{ *:[i32] }, (BUFSOffset:{ *:[i32] } i32:{ *:[i32] }:$soffset), (timm:{ *:[i32] }):$offset, (timm:{ *:[i32] }):$auxiliary, 0:{ *:[i1] })  =>  (BUFFER_ATOMIC_ADD_X2_OFFSET_RTN:{ *:[i64] } anonymous_15036:{ *:[i64] }:$vdata_in, SReg_128:{ *:[v4i32] }:$rsrc, SCSrc_b32:{ *:[i32] }:$soffset, (timm:{ *:[i32] }):$offset, (extract_cpol_set_glc:{ *:[i32] } ?:{ *:[i32] }:$auxiliary))
        GIR_BuildMI, /*InsnID*/0, /*Opcode*/GIMT_Encode2(AMDGPU::BUFFER_ATOMIC_ADD_X2_OFFSET_RTN),
        GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/0, // DstI[vdata]
        GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/1, // vdata_in
        GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/2, // rsrc
        GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/0, // soffset
        GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/6, // offset
        GIR_CustomOperandRenderer, /*InsnID*/0, /*OldInsnID*/0, /*OpIdx*/7, /*OperandRenderer*/GIMT_Encode2(GICR_renderExtractCpolSetGLC), // auxiliary
        GIR_MergeMemOperands, /*InsnID*/0, /*NumInsns*/1, /*MergeInsnID's*/0,
        GIR_ConstrainSelectedInstOperands, /*InsnID*/0,
        GIR_EraseFromParent, /*InsnID*/0,
        // GIR_Coverage, 4945,
        GIR_Done,
      // Label 5738: @416805
      GIM_Try, /*On fail goto*//*Label 5739*/ GIMT_Encode4(416887), // Rule ID 4953 //
        GIM_CheckRegBankForClass, /*MI*/0, /*Op*/0, /*RC*/GIMT_Encode2(AMDGPU::AV_64RegClassID),
        GIM_CheckConstantInt8, /*MI*/0, /*Op*/3, 0,
        GIM_CheckConstantInt8, /*MI*/0, /*Op*/4, 0,
        // MIs[0] offset
        GIM_CheckIsImm, /*MI*/0, /*Op*/6,
        // MIs[0] auxiliary
        GIM_CheckIsImm, /*MI*/0, /*Op*/7,
        // MIs[0] Operand 8
        GIM_CheckLiteralInt, /*MI*/0, /*Op*/8, GIMT_Encode8(0),
        GIM_CheckComplexPattern, /*MI*/0, /*Op*/5, /*Renderer*/GIMT_Encode2(0), GIMT_Encode2(GICP_gi_buf_soffset),
        // (SIbuffer_atomic_add:{ *:[i64] } i64:{ *:[i64] }:$vdata_in, v4i32:{ *:[v4i32] }:$rsrc, 0:{ *:[i32] }, 0:{ *:[i32] }, (BUFSOffset:{ *:[i32] } i32:{ *:[i32] }:$soffset), (timm:{ *:[i32] }):$offset, (timm:{ *:[i32] }):$auxiliary, 0:{ *:[i1] })  =>  (BUFFER_ATOMIC_ADD_X2_VBUFFER_OFFSET_RTN:{ *:[i64] } anonymous_15036:{ *:[i64] }:$vdata_in, SReg_128:{ *:[v4i32] }:$rsrc, SCSrc_b32:{ *:[i32] }:$soffset, (timm:{ *:[i32] }):$offset, (extract_cpol_set_glc:{ *:[i32] } ?:{ *:[i32] }:$auxiliary))
        GIR_BuildMI, /*InsnID*/0, /*Opcode*/GIMT_Encode2(AMDGPU::BUFFER_ATOMIC_ADD_X2_VBUFFER_OFFSET_RTN),
        GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/0, // DstI[vdata]
        GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/1, // vdata_in
        GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/2, // rsrc
        GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/0, // soffset
        GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/6, // offset
        GIR_CustomOperandRenderer, /*InsnID*/0, /*OldInsnID*/0, /*OpIdx*/7, /*OperandRenderer*/GIMT_Encode2(GICR_renderExtractCpolSetGLC), // auxiliary
        GIR_MergeMemOperands, /*InsnID*/0, /*NumInsns*/1, /*MergeInsnID's*/0,
        GIR_ConstrainSelectedInstOperands, /*InsnID*/0,
        GIR_EraseFromParent, /*InsnID*/0,
        // GIR_Coverage, 4953,
        GIR_Done,
      // Label 5739: @416887
      GIM_Try, /*On fail goto*//*Label 5740*/ GIMT_Encode4(416965), // Rule ID 4951 //
        GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasUnrestrictedSOffset),
        GIM_CheckHasNoUse, /*MI*/0,
        GIM_CheckConstantInt8, /*MI*/0, /*Op*/3, 0,
        // MIs[0] offset
        GIM_CheckIsImm, /*MI*/0, /*Op*/6,
        // MIs[0] auxiliary
        GIM_CheckIsImm, /*MI*/0, /*Op*/7,
        // MIs[0] Operand 8
        GIM_CheckLiteralInt, /*MI*/0, /*Op*/8, GIMT_Encode8(0),
        GIM_CheckComplexPattern, /*MI*/0, /*Op*/5, /*Renderer*/GIMT_Encode2(0), GIMT_Encode2(GICP_gi_buf_soffset),
        // (SIbuffer_atomic_add:{ *:[i64] } i64:{ *:[i64] }:$vdata_in, v4i32:{ *:[v4i32] }:$rsrc, 0:{ *:[i32] }, i32:{ *:[i32] }:$voffset, (BUFSOffset:{ *:[i32] } i32:{ *:[i32] }:$soffset), (timm:{ *:[i32] }):$offset, (timm:{ *:[i32] }):$auxiliary, 0:{ *:[i1] })<<P:Predicate_SIbuffer_atomic_add_noret>>  =>  (BUFFER_ATOMIC_ADD_X2_OFFEN anonymous_15036:{ *:[i64] }:$vdata_in, VGPR_32:{ *:[i32] }:$voffset, SReg_128:{ *:[v4i32] }:$rsrc, SCSrc_b32:{ *:[i32] }:$soffset, (timm:{ *:[i32] }):$offset, (extract_cpol:{ *:[i32] } ?:{ *:[i32] }:$auxiliary))
        GIR_BuildMI, /*InsnID*/0, /*Opcode*/GIMT_Encode2(AMDGPU::BUFFER_ATOMIC_ADD_X2_OFFEN),
        GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/1, // vdata_in
        GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/4, // voffset
        GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/2, // rsrc
        GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/0, // soffset
        GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/6, // offset
        GIR_CustomOperandRenderer, /*InsnID*/0, /*OldInsnID*/0, /*OpIdx*/7, /*OperandRenderer*/GIMT_Encode2(GICR_renderExtractCPol), // auxiliary
        GIR_MergeMemOperands, /*InsnID*/0, /*NumInsns*/1, /*MergeInsnID's*/0,
        GIR_ConstrainSelectedInstOperands, /*InsnID*/0,
        GIR_EraseFromParent, /*InsnID*/0,
        // GIR_Coverage, 4951,
        GIR_Done,
      // Label 5740: @416965
      GIM_Try, /*On fail goto*//*Label 5741*/ GIMT_Encode4(417040), // Rule ID 4959 //
        GIM_CheckHasNoUse, /*MI*/0,
        GIM_CheckConstantInt8, /*MI*/0, /*Op*/3, 0,
        // MIs[0] offset
        GIM_CheckIsImm, /*MI*/0, /*Op*/6,
        // MIs[0] auxiliary
        GIM_CheckIsImm, /*MI*/0, /*Op*/7,
        // MIs[0] Operand 8
        GIM_CheckLiteralInt, /*MI*/0, /*Op*/8, GIMT_Encode8(0),
        GIM_CheckComplexPattern, /*MI*/0, /*Op*/5, /*Renderer*/GIMT_Encode2(0), GIMT_Encode2(GICP_gi_buf_soffset),
        // (SIbuffer_atomic_add:{ *:[i64] } i64:{ *:[i64] }:$vdata_in, v4i32:{ *:[v4i32] }:$rsrc, 0:{ *:[i32] }, i32:{ *:[i32] }:$voffset, (BUFSOffset:{ *:[i32] } i32:{ *:[i32] }:$soffset), (timm:{ *:[i32] }):$offset, (timm:{ *:[i32] }):$auxiliary, 0:{ *:[i1] })<<P:Predicate_SIbuffer_atomic_add_noret>>  =>  (BUFFER_ATOMIC_ADD_X2_VBUFFER_OFFEN anonymous_15036:{ *:[i64] }:$vdata_in, VGPR_32:{ *:[i32] }:$voffset, SReg_128:{ *:[v4i32] }:$rsrc, SCSrc_b32:{ *:[i32] }:$soffset, (timm:{ *:[i32] }):$offset, (extract_cpol:{ *:[i32] } ?:{ *:[i32] }:$auxiliary))
        GIR_BuildMI, /*InsnID*/0, /*Opcode*/GIMT_Encode2(AMDGPU::BUFFER_ATOMIC_ADD_X2_VBUFFER_OFFEN),
        GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/1, // vdata_in
        GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/4, // voffset
        GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/2, // rsrc
        GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/0, // soffset
        GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/6, // offset
        GIR_CustomOperandRenderer, /*InsnID*/0, /*OldInsnID*/0, /*OpIdx*/7, /*OperandRenderer*/GIMT_Encode2(GICR_renderExtractCPol), // auxiliary
        GIR_MergeMemOperands, /*InsnID*/0, /*NumInsns*/1, /*MergeInsnID's*/0,
        GIR_ConstrainSelectedInstOperands, /*InsnID*/0,
        GIR_EraseFromParent, /*InsnID*/0,
        // GIR_Coverage, 4959,
        GIR_Done,
      // Label 5741: @417040
      GIM_Try, /*On fail goto*//*Label 5742*/ GIMT_Encode4(417125), // Rule ID 4947 //
        GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasUnrestrictedSOffset),
        GIM_CheckRegBankForClass, /*MI*/0, /*Op*/0, /*RC*/GIMT_Encode2(AMDGPU::AV_64RegClassID),
        GIM_CheckConstantInt8, /*MI*/0, /*Op*/3, 0,
        // MIs[0] offset
        GIM_CheckIsImm, /*MI*/0, /*Op*/6,
        // MIs[0] auxiliary
        GIM_CheckIsImm, /*MI*/0, /*Op*/7,
        // MIs[0] Operand 8
        GIM_CheckLiteralInt, /*MI*/0, /*Op*/8, GIMT_Encode8(0),
        GIM_CheckComplexPattern, /*MI*/0, /*Op*/5, /*Renderer*/GIMT_Encode2(0), GIMT_Encode2(GICP_gi_buf_soffset),
        // (SIbuffer_atomic_add:{ *:[i64] } i64:{ *:[i64] }:$vdata_in, v4i32:{ *:[v4i32] }:$rsrc, 0:{ *:[i32] }, i32:{ *:[i32] }:$voffset, (BUFSOffset:{ *:[i32] } i32:{ *:[i32] }:$soffset), (timm:{ *:[i32] }):$offset, (timm:{ *:[i32] }):$auxiliary, 0:{ *:[i1] })  =>  (BUFFER_ATOMIC_ADD_X2_OFFEN_RTN:{ *:[i64] } anonymous_15036:{ *:[i64] }:$vdata_in, VGPR_32:{ *:[i32] }:$voffset, SReg_128:{ *:[v4i32] }:$rsrc, SCSrc_b32:{ *:[i32] }:$soffset, (timm:{ *:[i32] }):$offset, (extract_cpol_set_glc:{ *:[i32] } ?:{ *:[i32] }:$auxiliary))
        GIR_BuildMI, /*InsnID*/0, /*Opcode*/GIMT_Encode2(AMDGPU::BUFFER_ATOMIC_ADD_X2_OFFEN_RTN),
        GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/0, // DstI[vdata]
        GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/1, // vdata_in
        GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/4, // voffset
        GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/2, // rsrc
        GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/0, // soffset
        GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/6, // offset
        GIR_CustomOperandRenderer, /*InsnID*/0, /*OldInsnID*/0, /*OpIdx*/7, /*OperandRenderer*/GIMT_Encode2(GICR_renderExtractCpolSetGLC), // auxiliary
        GIR_MergeMemOperands, /*InsnID*/0, /*NumInsns*/1, /*MergeInsnID's*/0,
        GIR_ConstrainSelectedInstOperands, /*InsnID*/0,
        GIR_EraseFromParent, /*InsnID*/0,
        // GIR_Coverage, 4947,
        GIR_Done,
      // Label 5742: @417125
      GIM_Try, /*On fail goto*//*Label 5743*/ GIMT_Encode4(417207), // Rule ID 4955 //
        GIM_CheckRegBankForClass, /*MI*/0, /*Op*/0, /*RC*/GIMT_Encode2(AMDGPU::AV_64RegClassID),
        GIM_CheckConstantInt8, /*MI*/0, /*Op*/3, 0,
        // MIs[0] offset
        GIM_CheckIsImm, /*MI*/0, /*Op*/6,
        // MIs[0] auxiliary
        GIM_CheckIsImm, /*MI*/0, /*Op*/7,
        // MIs[0] Operand 8
        GIM_CheckLiteralInt, /*MI*/0, /*Op*/8, GIMT_Encode8(0),
        GIM_CheckComplexPattern, /*MI*/0, /*Op*/5, /*Renderer*/GIMT_Encode2(0), GIMT_Encode2(GICP_gi_buf_soffset),
        // (SIbuffer_atomic_add:{ *:[i64] } i64:{ *:[i64] }:$vdata_in, v4i32:{ *:[v4i32] }:$rsrc, 0:{ *:[i32] }, i32:{ *:[i32] }:$voffset, (BUFSOffset:{ *:[i32] } i32:{ *:[i32] }:$soffset), (timm:{ *:[i32] }):$offset, (timm:{ *:[i32] }):$auxiliary, 0:{ *:[i1] })  =>  (BUFFER_ATOMIC_ADD_X2_VBUFFER_OFFEN_RTN:{ *:[i64] } anonymous_15036:{ *:[i64] }:$vdata_in, VGPR_32:{ *:[i32] }:$voffset, SReg_128:{ *:[v4i32] }:$rsrc, SCSrc_b32:{ *:[i32] }:$soffset, (timm:{ *:[i32] }):$offset, (extract_cpol_set_glc:{ *:[i32] } ?:{ *:[i32] }:$auxiliary))
        GIR_BuildMI, /*InsnID*/0, /*Opcode*/GIMT_Encode2(AMDGPU::BUFFER_ATOMIC_ADD_X2_VBUFFER_OFFEN_RTN),
        GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/0, // DstI[vdata]
        GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/1, // vdata_in
        GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/4, // voffset
        GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/2, // rsrc
        GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/0, // soffset
        GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/6, // offset
        GIR_CustomOperandRenderer, /*InsnID*/0, /*OldInsnID*/0, /*OpIdx*/7, /*OperandRenderer*/GIMT_Encode2(GICR_renderExtractCpolSetGLC), // auxiliary
        GIR_MergeMemOperands, /*InsnID*/0, /*NumInsns*/1, /*MergeInsnID's*/0,
        GIR_ConstrainSelectedInstOperands, /*InsnID*/0,
        GIR_EraseFromParent, /*InsnID*/0,
        // GIR_Coverage, 4955,
        GIR_Done,
      // Label 5743: @417207
      GIM_Try, /*On fail goto*//*Label 5744*/ GIMT_Encode4(417277), // Rule ID 4950 //
        GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasUnrestrictedSOffset),
        GIM_CheckHasNoUse, /*MI*/0,
        GIM_CheckConstantInt8, /*MI*/0, /*Op*/4, 0,
        // MIs[0] offset
        GIM_CheckIsImm, /*MI*/0, /*Op*/6,
        // MIs[0] auxiliary
        GIM_CheckIsImm, /*MI*/0, /*Op*/7,
        // MIs[0] Operand 8
        GIM_CheckIsImm, /*MI*/0, /*Op*/8,
        GIM_CheckComplexPattern, /*MI*/0, /*Op*/5, /*Renderer*/GIMT_Encode2(0), GIMT_Encode2(GICP_gi_buf_soffset),
        // (SIbuffer_atomic_add:{ *:[i64] } i64:{ *:[i64] }:$vdata_in, v4i32:{ *:[v4i32] }:$rsrc, i32:{ *:[i32] }:$vindex, 0:{ *:[i32] }, (BUFSOffset:{ *:[i32] } i32:{ *:[i32] }:$soffset), (timm:{ *:[i32] }):$offset, (timm:{ *:[i32] }):$auxiliary, (timm:{ *:[i1] }))<<P:Predicate_SIbuffer_atomic_add_noret>>  =>  (BUFFER_ATOMIC_ADD_X2_IDXEN anonymous_15036:{ *:[i64] }:$vdata_in, VGPR_32:{ *:[i32] }:$vindex, SReg_128:{ *:[v4i32] }:$rsrc, SCSrc_b32:{ *:[i32] }:$soffset, (timm:{ *:[i32] }):$offset, (extract_cpol:{ *:[i32] } ?:{ *:[i32] }:$auxiliary))
        GIR_BuildMI, /*InsnID*/0, /*Opcode*/GIMT_Encode2(AMDGPU::BUFFER_ATOMIC_ADD_X2_IDXEN),
        GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/1, // vdata_in
        GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/3, // vindex
        GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/2, // rsrc
        GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/0, // soffset
        GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/6, // offset
        GIR_CustomOperandRenderer, /*InsnID*/0, /*OldInsnID*/0, /*OpIdx*/7, /*OperandRenderer*/GIMT_Encode2(GICR_renderExtractCPol), // auxiliary
        GIR_MergeMemOperands, /*InsnID*/0, /*NumInsns*/1, /*MergeInsnID's*/0,
        GIR_ConstrainSelectedInstOperands, /*InsnID*/0,
        GIR_EraseFromParent, /*InsnID*/0,
        // GIR_Coverage, 4950,
        GIR_Done,
      // Label 5744: @417277
      GIM_Try, /*On fail goto*//*Label 5745*/ GIMT_Encode4(417344), // Rule ID 4958 //
        GIM_CheckHasNoUse, /*MI*/0,
        GIM_CheckConstantInt8, /*MI*/0, /*Op*/4, 0,
        // MIs[0] offset
        GIM_CheckIsImm, /*MI*/0, /*Op*/6,
        // MIs[0] auxiliary
        GIM_CheckIsImm, /*MI*/0, /*Op*/7,
        // MIs[0] Operand 8
        GIM_CheckIsImm, /*MI*/0, /*Op*/8,
        GIM_CheckComplexPattern, /*MI*/0, /*Op*/5, /*Renderer*/GIMT_Encode2(0), GIMT_Encode2(GICP_gi_buf_soffset),
        // (SIbuffer_atomic_add:{ *:[i64] } i64:{ *:[i64] }:$vdata_in, v4i32:{ *:[v4i32] }:$rsrc, i32:{ *:[i32] }:$vindex, 0:{ *:[i32] }, (BUFSOffset:{ *:[i32] } i32:{ *:[i32] }:$soffset), (timm:{ *:[i32] }):$offset, (timm:{ *:[i32] }):$auxiliary, (timm:{ *:[i1] }))<<P:Predicate_SIbuffer_atomic_add_noret>>  =>  (BUFFER_ATOMIC_ADD_X2_VBUFFER_IDXEN anonymous_15036:{ *:[i64] }:$vdata_in, VGPR_32:{ *:[i32] }:$vindex, SReg_128:{ *:[v4i32] }:$rsrc, SCSrc_b32:{ *:[i32] }:$soffset, (timm:{ *:[i32] }):$offset, (extract_cpol:{ *:[i32] } ?:{ *:[i32] }:$auxiliary))
        GIR_BuildMI, /*InsnID*/0, /*Opcode*/GIMT_Encode2(AMDGPU::BUFFER_ATOMIC_ADD_X2_VBUFFER_IDXEN),
        GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/1, // vdata_in
        GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/3, // vindex
        GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/2, // rsrc
        GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/0, // soffset
        GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/6, // offset
        GIR_CustomOperandRenderer, /*InsnID*/0, /*OldInsnID*/0, /*OpIdx*/7, /*OperandRenderer*/GIMT_Encode2(GICR_renderExtractCPol), // auxiliary
        GIR_MergeMemOperands, /*InsnID*/0, /*NumInsns*/1, /*MergeInsnID's*/0,
        GIR_ConstrainSelectedInstOperands, /*InsnID*/0,
        GIR_EraseFromParent, /*InsnID*/0,
        // GIR_Coverage, 4958,
        GIR_Done,
      // Label 5745: @417344
      GIM_Try, /*On fail goto*//*Label 5746*/ GIMT_Encode4(417421), // Rule ID 4946 //
        GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasUnrestrictedSOffset),
        GIM_CheckRegBankForClass, /*MI*/0, /*Op*/0, /*RC*/GIMT_Encode2(AMDGPU::AV_64RegClassID),
        GIM_CheckConstantInt8, /*MI*/0, /*Op*/4, 0,
        // MIs[0] offset
        GIM_CheckIsImm, /*MI*/0, /*Op*/6,
        // MIs[0] auxiliary
        GIM_CheckIsImm, /*MI*/0, /*Op*/7,
        // MIs[0] Operand 8
        GIM_CheckIsImm, /*MI*/0, /*Op*/8,
        GIM_CheckComplexPattern, /*MI*/0, /*Op*/5, /*Renderer*/GIMT_Encode2(0), GIMT_Encode2(GICP_gi_buf_soffset),
        // (SIbuffer_atomic_add:{ *:[i64] } i64:{ *:[i64] }:$vdata_in, v4i32:{ *:[v4i32] }:$rsrc, i32:{ *:[i32] }:$vindex, 0:{ *:[i32] }, (BUFSOffset:{ *:[i32] } i32:{ *:[i32] }:$soffset), (timm:{ *:[i32] }):$offset, (timm:{ *:[i32] }):$auxiliary, (timm:{ *:[i1] }))  =>  (BUFFER_ATOMIC_ADD_X2_IDXEN_RTN:{ *:[i64] } anonymous_15036:{ *:[i64] }:$vdata_in, VGPR_32:{ *:[i32] }:$vindex, SReg_128:{ *:[v4i32] }:$rsrc, SCSrc_b32:{ *:[i32] }:$soffset, (timm:{ *:[i32] }):$offset, (extract_cpol_set_glc:{ *:[i32] } ?:{ *:[i32] }:$auxiliary))
        GIR_BuildMI, /*InsnID*/0, /*Opcode*/GIMT_Encode2(AMDGPU::BUFFER_ATOMIC_ADD_X2_IDXEN_RTN),
        GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/0, // DstI[vdata]
        GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/1, // vdata_in
        GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/3, // vindex
        GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/2, // rsrc
        GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/0, // soffset
        GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/6, // offset
        GIR_CustomOperandRenderer, /*InsnID*/0, /*OldInsnID*/0, /*OpIdx*/7, /*OperandRenderer*/GIMT_Encode2(GICR_renderExtractCpolSetGLC), // auxiliary
        GIR_MergeMemOperands, /*InsnID*/0, /*NumInsns*/1, /*MergeInsnID's*/0,
        GIR_ConstrainSelectedInstOperands, /*InsnID*/0,
        GIR_EraseFromParent, /*InsnID*/0,
        // GIR_Coverage, 4946,
        GIR_Done,
      // Label 5746: @417421
      GIM_Try, /*On fail goto*//*Label 5747*/ GIMT_Encode4(417495), // Rule ID 4954 //
        GIM_CheckRegBankForClass, /*MI*/0, /*Op*/0, /*RC*/GIMT_Encode2(AMDGPU::AV_64RegClassID),
        GIM_CheckConstantInt8, /*MI*/0, /*Op*/4, 0,
        // MIs[0] offset
        GIM_CheckIsImm, /*MI*/0, /*Op*/6,
        // MIs[0] auxiliary
        GIM_CheckIsImm, /*MI*/0, /*Op*/7,
        // MIs[0] Operand 8
        GIM_CheckIsImm, /*MI*/0, /*Op*/8,
        GIM_CheckComplexPattern, /*MI*/0, /*Op*/5, /*Renderer*/GIMT_Encode2(0), GIMT_Encode2(GICP_gi_buf_soffset),
        // (SIbuffer_atomic_add:{ *:[i64] } i64:{ *:[i64] }:$vdata_in, v4i32:{ *:[v4i32] }:$rsrc, i32:{ *:[i32] }:$vindex, 0:{ *:[i32] }, (BUFSOffset:{ *:[i32] } i32:{ *:[i32] }:$soffset), (timm:{ *:[i32] }):$offset, (timm:{ *:[i32] }):$auxiliary, (timm:{ *:[i1] }))  =>  (BUFFER_ATOMIC_ADD_X2_VBUFFER_IDXEN_RTN:{ *:[i64] } anonymous_15036:{ *:[i64] }:$vdata_in, VGPR_32:{ *:[i32] }:$vindex, SReg_128:{ *:[v4i32] }:$rsrc, SCSrc_b32:{ *:[i32] }:$soffset, (timm:{ *:[i32] }):$offset, (extract_cpol_set_glc:{ *:[i32] } ?:{ *:[i32] }:$auxiliary))
        GIR_BuildMI, /*InsnID*/0, /*Opcode*/GIMT_Encode2(AMDGPU::BUFFER_ATOMIC_ADD_X2_VBUFFER_IDXEN_RTN),
        GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/0, // DstI[vdata]
        GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/1, // vdata_in
        GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/3, // vindex
        GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/2, // rsrc
        GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/0, // soffset
        GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/6, // offset
        GIR_CustomOperandRenderer, /*InsnID*/0, /*OldInsnID*/0, /*OpIdx*/7, /*OperandRenderer*/GIMT_Encode2(GICR_renderExtractCpolSetGLC), // auxiliary
        GIR_MergeMemOperands, /*InsnID*/0, /*NumInsns*/1, /*MergeInsnID's*/0,
        GIR_ConstrainSelectedInstOperands, /*InsnID*/0,
        GIR_EraseFromParent, /*InsnID*/0,
        // GIR_Coverage, 4954,
        GIR_Done,
      // Label 5747: @417495
      GIM_Try, /*On fail goto*//*Label 5748*/ GIMT_Encode4(417601), // Rule ID 4952 //
        GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasUnrestrictedSOffset),
        GIM_CheckHasNoUse, /*MI*/0,
        // MIs[0] offset
        GIM_CheckIsImm, /*MI*/0, /*Op*/6,
        // MIs[0] auxiliary
        GIM_CheckIsImm, /*MI*/0, /*Op*/7,
        // MIs[0] Operand 8
        GIM_CheckIsImm, /*MI*/0, /*Op*/8,
        GIM_CheckComplexPattern, /*MI*/0, /*Op*/5, /*Renderer*/GIMT_Encode2(0), GIMT_Encode2(GICP_gi_buf_soffset),
        // (SIbuffer_atomic_add:{ *:[i64] } i64:{ *:[i64] }:$vdata_in, v4i32:{ *:[v4i32] }:$rsrc, i32:{ *:[i32] }:$vindex, i32:{ *:[i32] }:$voffset, (BUFSOffset:{ *:[i32] } i32:{ *:[i32] }:$soffset), (timm:{ *:[i32] }):$offset, (timm:{ *:[i32] }):$auxiliary, (timm:{ *:[i1] }))<<P:Predicate_SIbuffer_atomic_add_noret>>  =>  (BUFFER_ATOMIC_ADD_X2_BOTHEN anonymous_15036:{ *:[i64] }:$vdata_in, (REG_SEQUENCE:{ *:[i64] } VReg_64:{ *:[i32] }, VGPR_32:{ *:[i32] }:$vindex, sub0:{ *:[i32] }, VGPR_32:{ *:[i32] }:$voffset, sub1:{ *:[i32] }), SReg_128:{ *:[v4i32] }:$rsrc, SCSrc_b32:{ *:[i32] }:$soffset, (timm:{ *:[i32] }):$offset, (extract_cpol:{ *:[i32] } ?:{ *:[i32] }:$auxiliary))
        GIR_MakeTempReg, /*TempRegID*/0, /*TypeID*/GILLT_s64,
        GIR_BuildMI, /*InsnID*/1, /*Opcode*/GIMT_Encode2(TargetOpcode::REG_SEQUENCE),
        GIR_AddTempRegister, /*InsnID*/1, /*TempRegID*/0, /*TempRegFlags*/GIMT_Encode2(RegState::Define),
        GIR_Copy, /*NewInsnID*/1, /*OldInsnID*/0, /*OpIdx*/3, // vindex
        GIR_AddImm8, /*InsnID*/1, /*SubRegIndex*/3,
        GIR_Copy, /*NewInsnID*/1, /*OldInsnID*/0, /*OpIdx*/4, // voffset
        GIR_AddImm8, /*InsnID*/1, /*SubRegIndex*/11,
        GIR_ConstrainOperandRC, /*InsnID*/1, /*Op*/0, GIMT_Encode2(AMDGPU::VReg_64RegClassID),
        GIR_ConstrainOperandRC, /*InsnID*/1, /*Op*/1, GIMT_Encode2(AMDGPU::VGPR_32RegClassID),
        GIR_ConstrainOperandRC, /*InsnID*/1, /*Op*/3, GIMT_Encode2(AMDGPU::VGPR_32RegClassID),
        GIR_BuildMI, /*InsnID*/0, /*Opcode*/GIMT_Encode2(AMDGPU::BUFFER_ATOMIC_ADD_X2_BOTHEN),
        GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/1, // vdata_in
        GIR_AddSimpleTempRegister, /*InsnID*/0, /*TempRegID*/0,
        GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/2, // rsrc
        GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/0, // soffset
        GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/6, // offset
        GIR_CustomOperandRenderer, /*InsnID*/0, /*OldInsnID*/0, /*OpIdx*/7, /*OperandRenderer*/GIMT_Encode2(GICR_renderExtractCPol), // auxiliary
        GIR_MergeMemOperands, /*InsnID*/0, /*NumInsns*/1, /*MergeInsnID's*/0,
        GIR_ConstrainSelectedInstOperands, /*InsnID*/0,
        GIR_EraseFromParent, /*InsnID*/0,
        // GIR_Coverage, 4952,
        GIR_Done,
      // Label 5748: @417601
      GIM_Try, /*On fail goto*//*Label 5749*/ GIMT_Encode4(417704), // Rule ID 4960 //
        GIM_CheckHasNoUse, /*MI*/0,
        // MIs[0] offset
        GIM_CheckIsImm, /*MI*/0, /*Op*/6,
        // MIs[0] auxiliary
        GIM_CheckIsImm, /*MI*/0, /*Op*/7,
        // MIs[0] Operand 8
        GIM_CheckIsImm, /*MI*/0, /*Op*/8,
        GIM_CheckComplexPattern, /*MI*/0, /*Op*/5, /*Renderer*/GIMT_Encode2(0), GIMT_Encode2(GICP_gi_buf_soffset),
        // (SIbuffer_atomic_add:{ *:[i64] } i64:{ *:[i64] }:$vdata_in, v4i32:{ *:[v4i32] }:$rsrc, i32:{ *:[i32] }:$vindex, i32:{ *:[i32] }:$voffset, (BUFSOffset:{ *:[i32] } i32:{ *:[i32] }:$soffset), (timm:{ *:[i32] }):$offset, (timm:{ *:[i32] }):$auxiliary, (timm:{ *:[i1] }))<<P:Predicate_SIbuffer_atomic_add_noret>>  =>  (BUFFER_ATOMIC_ADD_X2_VBUFFER_BOTHEN anonymous_15036:{ *:[i64] }:$vdata_in, (REG_SEQUENCE:{ *:[i64] } VReg_64:{ *:[i32] }, VGPR_32:{ *:[i32] }:$vindex, sub0:{ *:[i32] }, VGPR_32:{ *:[i32] }:$voffset, sub1:{ *:[i32] }), SReg_128:{ *:[v4i32] }:$rsrc, SCSrc_b32:{ *:[i32] }:$soffset, (timm:{ *:[i32] }):$offset, (extract_cpol:{ *:[i32] } ?:{ *:[i32] }:$auxiliary))
        GIR_MakeTempReg, /*TempRegID*/0, /*TypeID*/GILLT_s64,
        GIR_BuildMI, /*InsnID*/1, /*Opcode*/GIMT_Encode2(TargetOpcode::REG_SEQUENCE),
        GIR_AddTempRegister, /*InsnID*/1, /*TempRegID*/0, /*TempRegFlags*/GIMT_Encode2(RegState::Define),
        GIR_Copy, /*NewInsnID*/1, /*OldInsnID*/0, /*OpIdx*/3, // vindex
        GIR_AddImm8, /*InsnID*/1, /*SubRegIndex*/3,
        GIR_Copy, /*NewInsnID*/1, /*OldInsnID*/0, /*OpIdx*/4, // voffset
        GIR_AddImm8, /*InsnID*/1, /*SubRegIndex*/11,
        GIR_ConstrainOperandRC, /*InsnID*/1, /*Op*/0, GIMT_Encode2(AMDGPU::VReg_64RegClassID),
        GIR_ConstrainOperandRC, /*InsnID*/1, /*Op*/1, GIMT_Encode2(AMDGPU::VGPR_32RegClassID),
        GIR_ConstrainOperandRC, /*InsnID*/1, /*Op*/3, GIMT_Encode2(AMDGPU::VGPR_32RegClassID),
        GIR_BuildMI, /*InsnID*/0, /*Opcode*/GIMT_Encode2(AMDGPU::BUFFER_ATOMIC_ADD_X2_VBUFFER_BOTHEN),
        GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/1, // vdata_in
        GIR_AddSimpleTempRegister, /*InsnID*/0, /*TempRegID*/0,
        GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/2, // rsrc
        GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/0, // soffset
        GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/6, // offset
        GIR_CustomOperandRenderer, /*InsnID*/0, /*OldInsnID*/0, /*OpIdx*/7, /*OperandRenderer*/GIMT_Encode2(GICR_renderExtractCPol), // auxiliary
        GIR_MergeMemOperands, /*InsnID*/0, /*NumInsns*/1, /*MergeInsnID's*/0,
        GIR_ConstrainSelectedInstOperands, /*InsnID*/0,
        GIR_EraseFromParent, /*InsnID*/0,
        // GIR_Coverage, 4960,
        GIR_Done,
      // Label 5749: @417704
      GIM_Try, /*On fail goto*//*Label 5750*/ GIMT_Encode4(417817), // Rule ID 4948 //
        GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasUnrestrictedSOffset),
        GIM_CheckRegBankForClass, /*MI*/0, /*Op*/0, /*RC*/GIMT_Encode2(AMDGPU::AV_64RegClassID),
        // MIs[0] offset
        GIM_CheckIsImm, /*MI*/0, /*Op*/6,
        // MIs[0] auxiliary
        GIM_CheckIsImm, /*MI*/0, /*Op*/7,
        // MIs[0] Operand 8
        GIM_CheckIsImm, /*MI*/0, /*Op*/8,
        GIM_CheckComplexPattern, /*MI*/0, /*Op*/5, /*Renderer*/GIMT_Encode2(0), GIMT_Encode2(GICP_gi_buf_soffset),
        // (SIbuffer_atomic_add:{ *:[i64] } i64:{ *:[i64] }:$vdata_in, v4i32:{ *:[v4i32] }:$rsrc, i32:{ *:[i32] }:$vindex, i32:{ *:[i32] }:$voffset, (BUFSOffset:{ *:[i32] } i32:{ *:[i32] }:$soffset), (timm:{ *:[i32] }):$offset, (timm:{ *:[i32] }):$auxiliary, (timm:{ *:[i1] }))  =>  (BUFFER_ATOMIC_ADD_X2_BOTHEN_RTN:{ *:[i64] } anonymous_15036:{ *:[i64] }:$vdata_in, (REG_SEQUENCE:{ *:[i64] } VReg_64:{ *:[i32] }, VGPR_32:{ *:[i32] }:$vindex, sub0:{ *:[i32] }, VGPR_32:{ *:[i32] }:$voffset, sub1:{ *:[i32] }), SReg_128:{ *:[v4i32] }:$rsrc, SCSrc_b32:{ *:[i32] }:$soffset, (timm:{ *:[i32] }):$offset, (extract_cpol_set_glc:{ *:[i32] } ?:{ *:[i32] }:$auxiliary))
        GIR_MakeTempReg, /*TempRegID*/0, /*TypeID*/GILLT_s64,
        GIR_BuildMI, /*InsnID*/1, /*Opcode*/GIMT_Encode2(TargetOpcode::REG_SEQUENCE),
        GIR_AddTempRegister, /*InsnID*/1, /*TempRegID*/0, /*TempRegFlags*/GIMT_Encode2(RegState::Define),
        GIR_Copy, /*NewInsnID*/1, /*OldInsnID*/0, /*OpIdx*/3, // vindex
        GIR_AddImm8, /*InsnID*/1, /*SubRegIndex*/3,
        GIR_Copy, /*NewInsnID*/1, /*OldInsnID*/0, /*OpIdx*/4, // voffset
        GIR_AddImm8, /*InsnID*/1, /*SubRegIndex*/11,
        GIR_ConstrainOperandRC, /*InsnID*/1, /*Op*/0, GIMT_Encode2(AMDGPU::VReg_64RegClassID),
        GIR_ConstrainOperandRC, /*InsnID*/1, /*Op*/1, GIMT_Encode2(AMDGPU::VGPR_32RegClassID),
        GIR_ConstrainOperandRC, /*InsnID*/1, /*Op*/3, GIMT_Encode2(AMDGPU::VGPR_32RegClassID),
        GIR_BuildMI, /*InsnID*/0, /*Opcode*/GIMT_Encode2(AMDGPU::BUFFER_ATOMIC_ADD_X2_BOTHEN_RTN),
        GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/0, // DstI[vdata]
        GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/1, // vdata_in
        GIR_AddSimpleTempRegister, /*InsnID*/0, /*TempRegID*/0,
        GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/2, // rsrc
        GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/0, // soffset
        GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/6, // offset
        GIR_CustomOperandRenderer, /*InsnID*/0, /*OldInsnID*/0, /*OpIdx*/7, /*OperandRenderer*/GIMT_Encode2(GICR_renderExtractCpolSetGLC), // auxiliary
        GIR_MergeMemOperands, /*InsnID*/0, /*NumInsns*/1, /*MergeInsnID's*/0,
        GIR_ConstrainSelectedInstOperands, /*InsnID*/0,
        GIR_EraseFromParent, /*InsnID*/0,
        // GIR_Coverage, 4948,
        GIR_Done,
      // Label 5750: @417817
      GIM_Try, /*On fail goto*//*Label 5751*/ GIMT_Encode4(417927), // Rule ID 4956 //
        GIM_CheckRegBankForClass, /*MI*/0, /*Op*/0, /*RC*/GIMT_Encode2(AMDGPU::AV_64RegClassID),
        // MIs[0] offset
        GIM_CheckIsImm, /*MI*/0, /*Op*/6,
        // MIs[0] auxiliary
        GIM_CheckIsImm, /*MI*/0, /*Op*/7,
        // MIs[0] Operand 8
        GIM_CheckIsImm, /*MI*/0, /*Op*/8,
        GIM_CheckComplexPattern, /*MI*/0, /*Op*/5, /*Renderer*/GIMT_Encode2(0), GIMT_Encode2(GICP_gi_buf_soffset),
        // (SIbuffer_atomic_add:{ *:[i64] } i64:{ *:[i64] }:$vdata_in, v4i32:{ *:[v4i32] }:$rsrc, i32:{ *:[i32] }:$vindex, i32:{ *:[i32] }:$voffset, (BUFSOffset:{ *:[i32] } i32:{ *:[i32] }:$soffset), (timm:{ *:[i32] }):$offset, (timm:{ *:[i32] }):$auxiliary, (timm:{ *:[i1] }))  =>  (BUFFER_ATOMIC_ADD_X2_VBUFFER_BOTHEN_RTN:{ *:[i64] } anonymous_15036:{ *:[i64] }:$vdata_in, (REG_SEQUENCE:{ *:[i64] } VReg_64:{ *:[i32] }, VGPR_32:{ *:[i32] }:$vindex, sub0:{ *:[i32] }, VGPR_32:{ *:[i32] }:$voffset, sub1:{ *:[i32] }), SReg_128:{ *:[v4i32] }:$rsrc, SCSrc_b32:{ *:[i32] }:$soffset, (timm:{ *:[i32] }):$offset, (extract_cpol_set_glc:{ *:[i32] } ?:{ *:[i32] }:$auxiliary))
        GIR_MakeTempReg, /*TempRegID*/0, /*TypeID*/GILLT_s64,
        GIR_BuildMI, /*InsnID*/1, /*Opcode*/GIMT_Encode2(TargetOpcode::REG_SEQUENCE),
        GIR_AddTempRegister, /*InsnID*/1, /*TempRegID*/0, /*TempRegFlags*/GIMT_Encode2(RegState::Define),
        GIR_Copy, /*NewInsnID*/1, /*OldInsnID*/0, /*OpIdx*/3, // vindex
        GIR_AddImm8, /*InsnID*/1, /*SubRegIndex*/3,
        GIR_Copy, /*NewInsnID*/1, /*OldInsnID*/0, /*OpIdx*/4, // voffset
        GIR_AddImm8, /*InsnID*/1, /*SubRegIndex*/11,
        GIR_ConstrainOperandRC, /*InsnID*/1, /*Op*/0, GIMT_Encode2(AMDGPU::VReg_64RegClassID),
        GIR_ConstrainOperandRC, /*InsnID*/1, /*Op*/1, GIMT_Encode2(AMDGPU::VGPR_32RegClassID),
        GIR_ConstrainOperandRC, /*InsnID*/1, /*Op*/3, GIMT_Encode2(AMDGPU::VGPR_32RegClassID),
        GIR_BuildMI, /*InsnID*/0, /*Opcode*/GIMT_Encode2(AMDGPU::BUFFER_ATOMIC_ADD_X2_VBUFFER_BOTHEN_RTN),
        GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/0, // DstI[vdata]
        GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/1, // vdata_in
        GIR_AddSimpleTempRegister, /*InsnID*/0, /*TempRegID*/0,
        GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/2, // rsrc
        GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/0, // soffset
        GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/6, // offset
        GIR_CustomOperandRenderer, /*InsnID*/0, /*OldInsnID*/0, /*OpIdx*/7, /*OperandRenderer*/GIMT_Encode2(GICR_renderExtractCpolSetGLC), // auxiliary
        GIR_MergeMemOperands, /*InsnID*/0, /*NumInsns*/1, /*MergeInsnID's*/0,
        GIR_ConstrainSelectedInstOperands, /*InsnID*/0,
        GIR_EraseFromParent, /*InsnID*/0,
        // GIR_Coverage, 4956,
        GIR_Done,
      // Label 5751: @417927
      GIM_Reject,
    // Label 5735: @417928
    GIM_Reject,
    // Label 5717: @417929
    GIM_Reject,
    // Label 107: @417930
    GIM_SwitchType, /*MI*/0, /*Op*/0, /*[*/GIMT_Encode2(9), GIMT_Encode2(11), /*)*//*default:*//*Label 5754*/ GIMT_Encode4(420723),
    /*GILLT_s32*//*Label 5752*/ GIMT_Encode4(417949),
    /*GILLT_s64*//*Label 5753*/ GIMT_Encode4(419336),
    // Label 5752: @417949
    GIM_Try, /*On fail goto*//*Label 5755*/ GIMT_Encode4(419335),
      GIM_CheckType, /*MI*/0, /*Op*/1, /*Type*/GILLT_s32,
      GIM_CheckType, /*MI*/0, /*Op*/2, /*Type*/GILLT_v4s32,
      GIM_CheckType, /*MI*/0, /*Op*/3, /*Type*/GILLT_s32,
      GIM_CheckType, /*MI*/0, /*Op*/4, /*Type*/GILLT_s32,
      GIM_CheckType, /*MI*/0, /*Op*/5, /*Type*/GILLT_s32,
      GIM_Try, /*On fail goto*//*Label 5756*/ GIMT_Encode4(418052), // Rule ID 4845 //
        GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasUnrestrictedSOffset),
        GIM_CheckHasNoUse, /*MI*/0,
        GIM_CheckConstantInt8, /*MI*/0, /*Op*/3, 0,
        GIM_CheckConstantInt8, /*MI*/0, /*Op*/4, 0,
        // MIs[0] offset
        GIM_CheckIsImm, /*MI*/0, /*Op*/6,
        // MIs[0] auxiliary
        GIM_CheckIsImm, /*MI*/0, /*Op*/7,
        // MIs[0] Operand 8
        GIM_CheckLiteralInt, /*MI*/0, /*Op*/8, GIMT_Encode8(0),
        GIM_CheckComplexPattern, /*MI*/0, /*Op*/5, /*Renderer*/GIMT_Encode2(0), GIMT_Encode2(GICP_gi_buf_soffset),
        // (SIbuffer_atomic_and:{ *:[i32] } i32:{ *:[i32] }:$vdata_in, v4i32:{ *:[v4i32] }:$rsrc, 0:{ *:[i32] }, 0:{ *:[i32] }, (BUFSOffset:{ *:[i32] } i32:{ *:[i32] }:$soffset), (timm:{ *:[i32] }):$offset, (timm:{ *:[i32] }):$auxiliary, 0:{ *:[i1] })<<P:Predicate_SIbuffer_atomic_and_noret>>  =>  (BUFFER_ATOMIC_AND_OFFSET anonymous_15037:{ *:[i32] }:$vdata_in, SReg_128:{ *:[v4i32] }:$rsrc, SCSrc_b32:{ *:[i32] }:$soffset, (timm:{ *:[i32] }):$offset, (extract_cpol:{ *:[i32] } ?:{ *:[i32] }:$auxiliary))
        GIR_BuildMI, /*InsnID*/0, /*Opcode*/GIMT_Encode2(AMDGPU::BUFFER_ATOMIC_AND_OFFSET),
        GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/1, // vdata_in
        GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/2, // rsrc
        GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/0, // soffset
        GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/6, // offset
        GIR_CustomOperandRenderer, /*InsnID*/0, /*OldInsnID*/0, /*OpIdx*/7, /*OperandRenderer*/GIMT_Encode2(GICR_renderExtractCPol), // auxiliary
        GIR_MergeMemOperands, /*InsnID*/0, /*NumInsns*/1, /*MergeInsnID's*/0,
        GIR_ConstrainSelectedInstOperands, /*InsnID*/0,
        GIR_EraseFromParent, /*InsnID*/0,
        // GIR_Coverage, 4845,
        GIR_Done,
      // Label 5756: @418052
      GIM_Try, /*On fail goto*//*Label 5757*/ GIMT_Encode4(418127), // Rule ID 4853 //
        GIM_CheckHasNoUse, /*MI*/0,
        GIM_CheckConstantInt8, /*MI*/0, /*Op*/3, 0,
        GIM_CheckConstantInt8, /*MI*/0, /*Op*/4, 0,
        // MIs[0] offset
        GIM_CheckIsImm, /*MI*/0, /*Op*/6,
        // MIs[0] auxiliary
        GIM_CheckIsImm, /*MI*/0, /*Op*/7,
        // MIs[0] Operand 8
        GIM_CheckLiteralInt, /*MI*/0, /*Op*/8, GIMT_Encode8(0),
        GIM_CheckComplexPattern, /*MI*/0, /*Op*/5, /*Renderer*/GIMT_Encode2(0), GIMT_Encode2(GICP_gi_buf_soffset),
        // (SIbuffer_atomic_and:{ *:[i32] } i32:{ *:[i32] }:$vdata_in, v4i32:{ *:[v4i32] }:$rsrc, 0:{ *:[i32] }, 0:{ *:[i32] }, (BUFSOffset:{ *:[i32] } i32:{ *:[i32] }:$soffset), (timm:{ *:[i32] }):$offset, (timm:{ *:[i32] }):$auxiliary, 0:{ *:[i1] })<<P:Predicate_SIbuffer_atomic_and_noret>>  =>  (BUFFER_ATOMIC_AND_VBUFFER_OFFSET anonymous_15037:{ *:[i32] }:$vdata_in, SReg_128:{ *:[v4i32] }:$rsrc, SCSrc_b32:{ *:[i32] }:$soffset, (timm:{ *:[i32] }):$offset, (extract_cpol:{ *:[i32] } ?:{ *:[i32] }:$auxiliary))
        GIR_BuildMI, /*InsnID*/0, /*Opcode*/GIMT_Encode2(AMDGPU::BUFFER_ATOMIC_AND_VBUFFER_OFFSET),
        GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/1, // vdata_in
        GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/2, // rsrc
        GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/0, // soffset
        GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/6, // offset
        GIR_CustomOperandRenderer, /*InsnID*/0, /*OldInsnID*/0, /*OpIdx*/7, /*OperandRenderer*/GIMT_Encode2(GICR_renderExtractCPol), // auxiliary
        GIR_MergeMemOperands, /*InsnID*/0, /*NumInsns*/1, /*MergeInsnID's*/0,
        GIR_ConstrainSelectedInstOperands, /*InsnID*/0,
        GIR_EraseFromParent, /*InsnID*/0,
        // GIR_Coverage, 4853,
        GIR_Done,
      // Label 5757: @418127
      GIM_Try, /*On fail goto*//*Label 5758*/ GIMT_Encode4(418212), // Rule ID 4841 //
        GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasUnrestrictedSOffset),
        GIM_CheckRegBankForClass, /*MI*/0, /*Op*/0, /*RC*/GIMT_Encode2(AMDGPU::AV_32RegClassID),
        GIM_CheckConstantInt8, /*MI*/0, /*Op*/3, 0,
        GIM_CheckConstantInt8, /*MI*/0, /*Op*/4, 0,
        // MIs[0] offset
        GIM_CheckIsImm, /*MI*/0, /*Op*/6,
        // MIs[0] auxiliary
        GIM_CheckIsImm, /*MI*/0, /*Op*/7,
        // MIs[0] Operand 8
        GIM_CheckLiteralInt, /*MI*/0, /*Op*/8, GIMT_Encode8(0),
        GIM_CheckComplexPattern, /*MI*/0, /*Op*/5, /*Renderer*/GIMT_Encode2(0), GIMT_Encode2(GICP_gi_buf_soffset),
        // (SIbuffer_atomic_and:{ *:[i32] } i32:{ *:[i32] }:$vdata_in, v4i32:{ *:[v4i32] }:$rsrc, 0:{ *:[i32] }, 0:{ *:[i32] }, (BUFSOffset:{ *:[i32] } i32:{ *:[i32] }:$soffset), (timm:{ *:[i32] }):$offset, (timm:{ *:[i32] }):$auxiliary, 0:{ *:[i1] })  =>  (BUFFER_ATOMIC_AND_OFFSET_RTN:{ *:[i32] } anonymous_15037:{ *:[i32] }:$vdata_in, SReg_128:{ *:[v4i32] }:$rsrc, SCSrc_b32:{ *:[i32] }:$soffset, (timm:{ *:[i32] }):$offset, (extract_cpol_set_glc:{ *:[i32] } ?:{ *:[i32] }:$auxiliary))
        GIR_BuildMI, /*InsnID*/0, /*Opcode*/GIMT_Encode2(AMDGPU::BUFFER_ATOMIC_AND_OFFSET_RTN),
        GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/0, // DstI[vdata]
        GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/1, // vdata_in
        GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/2, // rsrc
        GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/0, // soffset
        GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/6, // offset
        GIR_CustomOperandRenderer, /*InsnID*/0, /*OldInsnID*/0, /*OpIdx*/7, /*OperandRenderer*/GIMT_Encode2(GICR_renderExtractCpolSetGLC), // auxiliary
        GIR_MergeMemOperands, /*InsnID*/0, /*NumInsns*/1, /*MergeInsnID's*/0,
        GIR_ConstrainSelectedInstOperands, /*InsnID*/0,
        GIR_EraseFromParent, /*InsnID*/0,
        // GIR_Coverage, 4841,
        GIR_Done,
      // Label 5758: @418212
      GIM_Try, /*On fail goto*//*Label 5759*/ GIMT_Encode4(418294), // Rule ID 4849 //
        GIM_CheckRegBankForClass, /*MI*/0, /*Op*/0, /*RC*/GIMT_Encode2(AMDGPU::AV_32RegClassID),
        GIM_CheckConstantInt8, /*MI*/0, /*Op*/3, 0,
        GIM_CheckConstantInt8, /*MI*/0, /*Op*/4, 0,
        // MIs[0] offset
        GIM_CheckIsImm, /*MI*/0, /*Op*/6,
        // MIs[0] auxiliary
        GIM_CheckIsImm, /*MI*/0, /*Op*/7,
        // MIs[0] Operand 8
        GIM_CheckLiteralInt, /*MI*/0, /*Op*/8, GIMT_Encode8(0),
        GIM_CheckComplexPattern, /*MI*/0, /*Op*/5, /*Renderer*/GIMT_Encode2(0), GIMT_Encode2(GICP_gi_buf_soffset),
        // (SIbuffer_atomic_and:{ *:[i32] } i32:{ *:[i32] }:$vdata_in, v4i32:{ *:[v4i32] }:$rsrc, 0:{ *:[i32] }, 0:{ *:[i32] }, (BUFSOffset:{ *:[i32] } i32:{ *:[i32] }:$soffset), (timm:{ *:[i32] }):$offset, (timm:{ *:[i32] }):$auxiliary, 0:{ *:[i1] })  =>  (BUFFER_ATOMIC_AND_VBUFFER_OFFSET_RTN:{ *:[i32] } anonymous_15037:{ *:[i32] }:$vdata_in, SReg_128:{ *:[v4i32] }:$rsrc, SCSrc_b32:{ *:[i32] }:$soffset, (timm:{ *:[i32] }):$offset, (extract_cpol_set_glc:{ *:[i32] } ?:{ *:[i32] }:$auxiliary))
        GIR_BuildMI, /*InsnID*/0, /*Opcode*/GIMT_Encode2(AMDGPU::BUFFER_ATOMIC_AND_VBUFFER_OFFSET_RTN),
        GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/0, // DstI[vdata]
        GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/1, // vdata_in
        GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/2, // rsrc
        GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/0, // soffset
        GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/6, // offset
        GIR_CustomOperandRenderer, /*InsnID*/0, /*OldInsnID*/0, /*OpIdx*/7, /*OperandRenderer*/GIMT_Encode2(GICR_renderExtractCpolSetGLC), // auxiliary
        GIR_MergeMemOperands, /*InsnID*/0, /*NumInsns*/1, /*MergeInsnID's*/0,
        GIR_ConstrainSelectedInstOperands, /*InsnID*/0,
        GIR_EraseFromParent, /*InsnID*/0,
        // GIR_Coverage, 4849,
        GIR_Done,
      // Label 5759: @418294
      GIM_Try, /*On fail goto*//*Label 5760*/ GIMT_Encode4(418372), // Rule ID 4847 //
        GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasUnrestrictedSOffset),
        GIM_CheckHasNoUse, /*MI*/0,
        GIM_CheckConstantInt8, /*MI*/0, /*Op*/3, 0,
        // MIs[0] offset
        GIM_CheckIsImm, /*MI*/0, /*Op*/6,
        // MIs[0] auxiliary
        GIM_CheckIsImm, /*MI*/0, /*Op*/7,
        // MIs[0] Operand 8
        GIM_CheckLiteralInt, /*MI*/0, /*Op*/8, GIMT_Encode8(0),
        GIM_CheckComplexPattern, /*MI*/0, /*Op*/5, /*Renderer*/GIMT_Encode2(0), GIMT_Encode2(GICP_gi_buf_soffset),
        // (SIbuffer_atomic_and:{ *:[i32] } i32:{ *:[i32] }:$vdata_in, v4i32:{ *:[v4i32] }:$rsrc, 0:{ *:[i32] }, i32:{ *:[i32] }:$voffset, (BUFSOffset:{ *:[i32] } i32:{ *:[i32] }:$soffset), (timm:{ *:[i32] }):$offset, (timm:{ *:[i32] }):$auxiliary, 0:{ *:[i1] })<<P:Predicate_SIbuffer_atomic_and_noret>>  =>  (BUFFER_ATOMIC_AND_OFFEN anonymous_15037:{ *:[i32] }:$vdata_in, VGPR_32:{ *:[i32] }:$voffset, SReg_128:{ *:[v4i32] }:$rsrc, SCSrc_b32:{ *:[i32] }:$soffset, (timm:{ *:[i32] }):$offset, (extract_cpol:{ *:[i32] } ?:{ *:[i32] }:$auxiliary))
        GIR_BuildMI, /*InsnID*/0, /*Opcode*/GIMT_Encode2(AMDGPU::BUFFER_ATOMIC_AND_OFFEN),
        GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/1, // vdata_in
        GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/4, // voffset
        GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/2, // rsrc
        GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/0, // soffset
        GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/6, // offset
        GIR_CustomOperandRenderer, /*InsnID*/0, /*OldInsnID*/0, /*OpIdx*/7, /*OperandRenderer*/GIMT_Encode2(GICR_renderExtractCPol), // auxiliary
        GIR_MergeMemOperands, /*InsnID*/0, /*NumInsns*/1, /*MergeInsnID's*/0,
        GIR_ConstrainSelectedInstOperands, /*InsnID*/0,
        GIR_EraseFromParent, /*InsnID*/0,
        // GIR_Coverage, 4847,
        GIR_Done,
      // Label 5760: @418372
      GIM_Try, /*On fail goto*//*Label 5761*/ GIMT_Encode4(418447), // Rule ID 4855 //
        GIM_CheckHasNoUse, /*MI*/0,
        GIM_CheckConstantInt8, /*MI*/0, /*Op*/3, 0,
        // MIs[0] offset
        GIM_CheckIsImm, /*MI*/0, /*Op*/6,
        // MIs[0] auxiliary
        GIM_CheckIsImm, /*MI*/0, /*Op*/7,
        // MIs[0] Operand 8
        GIM_CheckLiteralInt, /*MI*/0, /*Op*/8, GIMT_Encode8(0),
        GIM_CheckComplexPattern, /*MI*/0, /*Op*/5, /*Renderer*/GIMT_Encode2(0), GIMT_Encode2(GICP_gi_buf_soffset),
        // (SIbuffer_atomic_and:{ *:[i32] } i32:{ *:[i32] }:$vdata_in, v4i32:{ *:[v4i32] }:$rsrc, 0:{ *:[i32] }, i32:{ *:[i32] }:$voffset, (BUFSOffset:{ *:[i32] } i32:{ *:[i32] }:$soffset), (timm:{ *:[i32] }):$offset, (timm:{ *:[i32] }):$auxiliary, 0:{ *:[i1] })<<P:Predicate_SIbuffer_atomic_and_noret>>  =>  (BUFFER_ATOMIC_AND_VBUFFER_OFFEN anonymous_15037:{ *:[i32] }:$vdata_in, VGPR_32:{ *:[i32] }:$voffset, SReg_128:{ *:[v4i32] }:$rsrc, SCSrc_b32:{ *:[i32] }:$soffset, (timm:{ *:[i32] }):$offset, (extract_cpol:{ *:[i32] } ?:{ *:[i32] }:$auxiliary))
        GIR_BuildMI, /*InsnID*/0, /*Opcode*/GIMT_Encode2(AMDGPU::BUFFER_ATOMIC_AND_VBUFFER_OFFEN),
        GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/1, // vdata_in
        GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/4, // voffset
        GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/2, // rsrc
        GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/0, // soffset
        GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/6, // offset
        GIR_CustomOperandRenderer, /*InsnID*/0, /*OldInsnID*/0, /*OpIdx*/7, /*OperandRenderer*/GIMT_Encode2(GICR_renderExtractCPol), // auxiliary
        GIR_MergeMemOperands, /*InsnID*/0, /*NumInsns*/1, /*MergeInsnID's*/0,
        GIR_ConstrainSelectedInstOperands, /*InsnID*/0,
        GIR_EraseFromParent, /*InsnID*/0,
        // GIR_Coverage, 4855,
        GIR_Done,
      // Label 5761: @418447
      GIM_Try, /*On fail goto*//*Label 5762*/ GIMT_Encode4(418532), // Rule ID 4843 //
        GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasUnrestrictedSOffset),
        GIM_CheckRegBankForClass, /*MI*/0, /*Op*/0, /*RC*/GIMT_Encode2(AMDGPU::AV_32RegClassID),
        GIM_CheckConstantInt8, /*MI*/0, /*Op*/3, 0,
        // MIs[0] offset
        GIM_CheckIsImm, /*MI*/0, /*Op*/6,
        // MIs[0] auxiliary
        GIM_CheckIsImm, /*MI*/0, /*Op*/7,
        // MIs[0] Operand 8
        GIM_CheckLiteralInt, /*MI*/0, /*Op*/8, GIMT_Encode8(0),
        GIM_CheckComplexPattern, /*MI*/0, /*Op*/5, /*Renderer*/GIMT_Encode2(0), GIMT_Encode2(GICP_gi_buf_soffset),
        // (SIbuffer_atomic_and:{ *:[i32] } i32:{ *:[i32] }:$vdata_in, v4i32:{ *:[v4i32] }:$rsrc, 0:{ *:[i32] }, i32:{ *:[i32] }:$voffset, (BUFSOffset:{ *:[i32] } i32:{ *:[i32] }:$soffset), (timm:{ *:[i32] }):$offset, (timm:{ *:[i32] }):$auxiliary, 0:{ *:[i1] })  =>  (BUFFER_ATOMIC_AND_OFFEN_RTN:{ *:[i32] } anonymous_15037:{ *:[i32] }:$vdata_in, VGPR_32:{ *:[i32] }:$voffset, SReg_128:{ *:[v4i32] }:$rsrc, SCSrc_b32:{ *:[i32] }:$soffset, (timm:{ *:[i32] }):$offset, (extract_cpol_set_glc:{ *:[i32] } ?:{ *:[i32] }:$auxiliary))
        GIR_BuildMI, /*InsnID*/0, /*Opcode*/GIMT_Encode2(AMDGPU::BUFFER_ATOMIC_AND_OFFEN_RTN),
        GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/0, // DstI[vdata]
        GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/1, // vdata_in
        GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/4, // voffset
        GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/2, // rsrc
        GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/0, // soffset
        GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/6, // offset
        GIR_CustomOperandRenderer, /*InsnID*/0, /*OldInsnID*/0, /*OpIdx*/7, /*OperandRenderer*/GIMT_Encode2(GICR_renderExtractCpolSetGLC), // auxiliary
        GIR_MergeMemOperands, /*InsnID*/0, /*NumInsns*/1, /*MergeInsnID's*/0,
        GIR_ConstrainSelectedInstOperands, /*InsnID*/0,
        GIR_EraseFromParent, /*InsnID*/0,
        // GIR_Coverage, 4843,
        GIR_Done,
      // Label 5762: @418532
      GIM_Try, /*On fail goto*//*Label 5763*/ GIMT_Encode4(418614), // Rule ID 4851 //
        GIM_CheckRegBankForClass, /*MI*/0, /*Op*/0, /*RC*/GIMT_Encode2(AMDGPU::AV_32RegClassID),
        GIM_CheckConstantInt8, /*MI*/0, /*Op*/3, 0,
        // MIs[0] offset
        GIM_CheckIsImm, /*MI*/0, /*Op*/6,
        // MIs[0] auxiliary
        GIM_CheckIsImm, /*MI*/0, /*Op*/7,
        // MIs[0] Operand 8
        GIM_CheckLiteralInt, /*MI*/0, /*Op*/8, GIMT_Encode8(0),
        GIM_CheckComplexPattern, /*MI*/0, /*Op*/5, /*Renderer*/GIMT_Encode2(0), GIMT_Encode2(GICP_gi_buf_soffset),
        // (SIbuffer_atomic_and:{ *:[i32] } i32:{ *:[i32] }:$vdata_in, v4i32:{ *:[v4i32] }:$rsrc, 0:{ *:[i32] }, i32:{ *:[i32] }:$voffset, (BUFSOffset:{ *:[i32] } i32:{ *:[i32] }:$soffset), (timm:{ *:[i32] }):$offset, (timm:{ *:[i32] }):$auxiliary, 0:{ *:[i1] })  =>  (BUFFER_ATOMIC_AND_VBUFFER_OFFEN_RTN:{ *:[i32] } anonymous_15037:{ *:[i32] }:$vdata_in, VGPR_32:{ *:[i32] }:$voffset, SReg_128:{ *:[v4i32] }:$rsrc, SCSrc_b32:{ *:[i32] }:$soffset, (timm:{ *:[i32] }):$offset, (extract_cpol_set_glc:{ *:[i32] } ?:{ *:[i32] }:$auxiliary))
        GIR_BuildMI, /*InsnID*/0, /*Opcode*/GIMT_Encode2(AMDGPU::BUFFER_ATOMIC_AND_VBUFFER_OFFEN_RTN),
        GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/0, // DstI[vdata]
        GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/1, // vdata_in
        GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/4, // voffset
        GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/2, // rsrc
        GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/0, // soffset
        GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/6, // offset
        GIR_CustomOperandRenderer, /*InsnID*/0, /*OldInsnID*/0, /*OpIdx*/7, /*OperandRenderer*/GIMT_Encode2(GICR_renderExtractCpolSetGLC), // auxiliary
        GIR_MergeMemOperands, /*InsnID*/0, /*NumInsns*/1, /*MergeInsnID's*/0,
        GIR_ConstrainSelectedInstOperands, /*InsnID*/0,
        GIR_EraseFromParent, /*InsnID*/0,
        // GIR_Coverage, 4851,
        GIR_Done,
      // Label 5763: @418614
      GIM_Try, /*On fail goto*//*Label 5764*/ GIMT_Encode4(418684), // Rule ID 4846 //
        GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasUnrestrictedSOffset),
        GIM_CheckHasNoUse, /*MI*/0,
        GIM_CheckConstantInt8, /*MI*/0, /*Op*/4, 0,
        // MIs[0] offset
        GIM_CheckIsImm, /*MI*/0, /*Op*/6,
        // MIs[0] auxiliary
        GIM_CheckIsImm, /*MI*/0, /*Op*/7,
        // MIs[0] Operand 8
        GIM_CheckIsImm, /*MI*/0, /*Op*/8,
        GIM_CheckComplexPattern, /*MI*/0, /*Op*/5, /*Renderer*/GIMT_Encode2(0), GIMT_Encode2(GICP_gi_buf_soffset),
        // (SIbuffer_atomic_and:{ *:[i32] } i32:{ *:[i32] }:$vdata_in, v4i32:{ *:[v4i32] }:$rsrc, i32:{ *:[i32] }:$vindex, 0:{ *:[i32] }, (BUFSOffset:{ *:[i32] } i32:{ *:[i32] }:$soffset), (timm:{ *:[i32] }):$offset, (timm:{ *:[i32] }):$auxiliary, (timm:{ *:[i1] }))<<P:Predicate_SIbuffer_atomic_and_noret>>  =>  (BUFFER_ATOMIC_AND_IDXEN anonymous_15037:{ *:[i32] }:$vdata_in, VGPR_32:{ *:[i32] }:$vindex, SReg_128:{ *:[v4i32] }:$rsrc, SCSrc_b32:{ *:[i32] }:$soffset, (timm:{ *:[i32] }):$offset, (extract_cpol:{ *:[i32] } ?:{ *:[i32] }:$auxiliary))
        GIR_BuildMI, /*InsnID*/0, /*Opcode*/GIMT_Encode2(AMDGPU::BUFFER_ATOMIC_AND_IDXEN),
        GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/1, // vdata_in
        GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/3, // vindex
        GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/2, // rsrc
        GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/0, // soffset
        GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/6, // offset
        GIR_CustomOperandRenderer, /*InsnID*/0, /*OldInsnID*/0, /*OpIdx*/7, /*OperandRenderer*/GIMT_Encode2(GICR_renderExtractCPol), // auxiliary
        GIR_MergeMemOperands, /*InsnID*/0, /*NumInsns*/1, /*MergeInsnID's*/0,
        GIR_ConstrainSelectedInstOperands, /*InsnID*/0,
        GIR_EraseFromParent, /*InsnID*/0,
        // GIR_Coverage, 4846,
        GIR_Done,
      // Label 5764: @418684
      GIM_Try, /*On fail goto*//*Label 5765*/ GIMT_Encode4(418751), // Rule ID 4854 //
        GIM_CheckHasNoUse, /*MI*/0,
        GIM_CheckConstantInt8, /*MI*/0, /*Op*/4, 0,
        // MIs[0] offset
        GIM_CheckIsImm, /*MI*/0, /*Op*/6,
        // MIs[0] auxiliary
        GIM_CheckIsImm, /*MI*/0, /*Op*/7,
        // MIs[0] Operand 8
        GIM_CheckIsImm, /*MI*/0, /*Op*/8,
        GIM_CheckComplexPattern, /*MI*/0, /*Op*/5, /*Renderer*/GIMT_Encode2(0), GIMT_Encode2(GICP_gi_buf_soffset),
        // (SIbuffer_atomic_and:{ *:[i32] } i32:{ *:[i32] }:$vdata_in, v4i32:{ *:[v4i32] }:$rsrc, i32:{ *:[i32] }:$vindex, 0:{ *:[i32] }, (BUFSOffset:{ *:[i32] } i32:{ *:[i32] }:$soffset), (timm:{ *:[i32] }):$offset, (timm:{ *:[i32] }):$auxiliary, (timm:{ *:[i1] }))<<P:Predicate_SIbuffer_atomic_and_noret>>  =>  (BUFFER_ATOMIC_AND_VBUFFER_IDXEN anonymous_15037:{ *:[i32] }:$vdata_in, VGPR_32:{ *:[i32] }:$vindex, SReg_128:{ *:[v4i32] }:$rsrc, SCSrc_b32:{ *:[i32] }:$soffset, (timm:{ *:[i32] }):$offset, (extract_cpol:{ *:[i32] } ?:{ *:[i32] }:$auxiliary))
        GIR_BuildMI, /*InsnID*/0, /*Opcode*/GIMT_Encode2(AMDGPU::BUFFER_ATOMIC_AND_VBUFFER_IDXEN),
        GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/1, // vdata_in
        GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/3, // vindex
        GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/2, // rsrc
        GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/0, // soffset
        GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/6, // offset
        GIR_CustomOperandRenderer, /*InsnID*/0, /*OldInsnID*/0, /*OpIdx*/7, /*OperandRenderer*/GIMT_Encode2(GICR_renderExtractCPol), // auxiliary
        GIR_MergeMemOperands, /*InsnID*/0, /*NumInsns*/1, /*MergeInsnID's*/0,
        GIR_ConstrainSelectedInstOperands, /*InsnID*/0,
        GIR_EraseFromParent, /*InsnID*/0,
        // GIR_Coverage, 4854,
        GIR_Done,
      // Label 5765: @418751
      GIM_Try, /*On fail goto*//*Label 5766*/ GIMT_Encode4(418828), // Rule ID 4842 //
        GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasUnrestrictedSOffset),
        GIM_CheckRegBankForClass, /*MI*/0, /*Op*/0, /*RC*/GIMT_Encode2(AMDGPU::AV_32RegClassID),
        GIM_CheckConstantInt8, /*MI*/0, /*Op*/4, 0,
        // MIs[0] offset
        GIM_CheckIsImm, /*MI*/0, /*Op*/6,
        // MIs[0] auxiliary
        GIM_CheckIsImm, /*MI*/0, /*Op*/7,
        // MIs[0] Operand 8
        GIM_CheckIsImm, /*MI*/0, /*Op*/8,
        GIM_CheckComplexPattern, /*MI*/0, /*Op*/5, /*Renderer*/GIMT_Encode2(0), GIMT_Encode2(GICP_gi_buf_soffset),
        // (SIbuffer_atomic_and:{ *:[i32] } i32:{ *:[i32] }:$vdata_in, v4i32:{ *:[v4i32] }:$rsrc, i32:{ *:[i32] }:$vindex, 0:{ *:[i32] }, (BUFSOffset:{ *:[i32] } i32:{ *:[i32] }:$soffset), (timm:{ *:[i32] }):$offset, (timm:{ *:[i32] }):$auxiliary, (timm:{ *:[i1] }))  =>  (BUFFER_ATOMIC_AND_IDXEN_RTN:{ *:[i32] } anonymous_15037:{ *:[i32] }:$vdata_in, VGPR_32:{ *:[i32] }:$vindex, SReg_128:{ *:[v4i32] }:$rsrc, SCSrc_b32:{ *:[i32] }:$soffset, (timm:{ *:[i32] }):$offset, (extract_cpol_set_glc:{ *:[i32] } ?:{ *:[i32] }:$auxiliary))
        GIR_BuildMI, /*InsnID*/0, /*Opcode*/GIMT_Encode2(AMDGPU::BUFFER_ATOMIC_AND_IDXEN_RTN),
        GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/0, // DstI[vdata]
        GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/1, // vdata_in
        GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/3, // vindex
        GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/2, // rsrc
        GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/0, // soffset
        GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/6, // offset
        GIR_CustomOperandRenderer, /*InsnID*/0, /*OldInsnID*/0, /*OpIdx*/7, /*OperandRenderer*/GIMT_Encode2(GICR_renderExtractCpolSetGLC), // auxiliary
        GIR_MergeMemOperands, /*InsnID*/0, /*NumInsns*/1, /*MergeInsnID's*/0,
        GIR_ConstrainSelectedInstOperands, /*InsnID*/0,
        GIR_EraseFromParent, /*InsnID*/0,
        // GIR_Coverage, 4842,
        GIR_Done,
      // Label 5766: @418828
      GIM_Try, /*On fail goto*//*Label 5767*/ GIMT_Encode4(418902), // Rule ID 4850 //
        GIM_CheckRegBankForClass, /*MI*/0, /*Op*/0, /*RC*/GIMT_Encode2(AMDGPU::AV_32RegClassID),
        GIM_CheckConstantInt8, /*MI*/0, /*Op*/4, 0,
        // MIs[0] offset
        GIM_CheckIsImm, /*MI*/0, /*Op*/6,
        // MIs[0] auxiliary
        GIM_CheckIsImm, /*MI*/0, /*Op*/7,
        // MIs[0] Operand 8
        GIM_CheckIsImm, /*MI*/0, /*Op*/8,
        GIM_CheckComplexPattern, /*MI*/0, /*Op*/5, /*Renderer*/GIMT_Encode2(0), GIMT_Encode2(GICP_gi_buf_soffset),
        // (SIbuffer_atomic_and:{ *:[i32] } i32:{ *:[i32] }:$vdata_in, v4i32:{ *:[v4i32] }:$rsrc, i32:{ *:[i32] }:$vindex, 0:{ *:[i32] }, (BUFSOffset:{ *:[i32] } i32:{ *:[i32] }:$soffset), (timm:{ *:[i32] }):$offset, (timm:{ *:[i32] }):$auxiliary, (timm:{ *:[i1] }))  =>  (BUFFER_ATOMIC_AND_VBUFFER_IDXEN_RTN:{ *:[i32] } anonymous_15037:{ *:[i32] }:$vdata_in, VGPR_32:{ *:[i32] }:$vindex, SReg_128:{ *:[v4i32] }:$rsrc, SCSrc_b32:{ *:[i32] }:$soffset, (timm:{ *:[i32] }):$offset, (extract_cpol_set_glc:{ *:[i32] } ?:{ *:[i32] }:$auxiliary))
        GIR_BuildMI, /*InsnID*/0, /*Opcode*/GIMT_Encode2(AMDGPU::BUFFER_ATOMIC_AND_VBUFFER_IDXEN_RTN),
        GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/0, // DstI[vdata]
        GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/1, // vdata_in
        GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/3, // vindex
        GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/2, // rsrc
        GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/0, // soffset
        GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/6, // offset
        GIR_CustomOperandRenderer, /*InsnID*/0, /*OldInsnID*/0, /*OpIdx*/7, /*OperandRenderer*/GIMT_Encode2(GICR_renderExtractCpolSetGLC), // auxiliary
        GIR_MergeMemOperands, /*InsnID*/0, /*NumInsns*/1, /*MergeInsnID's*/0,
        GIR_ConstrainSelectedInstOperands, /*InsnID*/0,
        GIR_EraseFromParent, /*InsnID*/0,
        // GIR_Coverage, 4850,
        GIR_Done,
      // Label 5767: @418902
      GIM_Try, /*On fail goto*//*Label 5768*/ GIMT_Encode4(419008), // Rule ID 4848 //
        GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasUnrestrictedSOffset),
        GIM_CheckHasNoUse, /*MI*/0,
        // MIs[0] offset
        GIM_CheckIsImm, /*MI*/0, /*Op*/6,
        // MIs[0] auxiliary
        GIM_CheckIsImm, /*MI*/0, /*Op*/7,
        // MIs[0] Operand 8
        GIM_CheckIsImm, /*MI*/0, /*Op*/8,
        GIM_CheckComplexPattern, /*MI*/0, /*Op*/5, /*Renderer*/GIMT_Encode2(0), GIMT_Encode2(GICP_gi_buf_soffset),
        // (SIbuffer_atomic_and:{ *:[i32] } i32:{ *:[i32] }:$vdata_in, v4i32:{ *:[v4i32] }:$rsrc, i32:{ *:[i32] }:$vindex, i32:{ *:[i32] }:$voffset, (BUFSOffset:{ *:[i32] } i32:{ *:[i32] }:$soffset), (timm:{ *:[i32] }):$offset, (timm:{ *:[i32] }):$auxiliary, (timm:{ *:[i1] }))<<P:Predicate_SIbuffer_atomic_and_noret>>  =>  (BUFFER_ATOMIC_AND_BOTHEN anonymous_15037:{ *:[i32] }:$vdata_in, (REG_SEQUENCE:{ *:[i64] } VReg_64:{ *:[i32] }, VGPR_32:{ *:[i32] }:$vindex, sub0:{ *:[i32] }, VGPR_32:{ *:[i32] }:$voffset, sub1:{ *:[i32] }), SReg_128:{ *:[v4i32] }:$rsrc, SCSrc_b32:{ *:[i32] }:$soffset, (timm:{ *:[i32] }):$offset, (extract_cpol:{ *:[i32] } ?:{ *:[i32] }:$auxiliary))
        GIR_MakeTempReg, /*TempRegID*/0, /*TypeID*/GILLT_s64,
        GIR_BuildMI, /*InsnID*/1, /*Opcode*/GIMT_Encode2(TargetOpcode::REG_SEQUENCE),
        GIR_AddTempRegister, /*InsnID*/1, /*TempRegID*/0, /*TempRegFlags*/GIMT_Encode2(RegState::Define),
        GIR_Copy, /*NewInsnID*/1, /*OldInsnID*/0, /*OpIdx*/3, // vindex
        GIR_AddImm8, /*InsnID*/1, /*SubRegIndex*/3,
        GIR_Copy, /*NewInsnID*/1, /*OldInsnID*/0, /*OpIdx*/4, // voffset
        GIR_AddImm8, /*InsnID*/1, /*SubRegIndex*/11,
        GIR_ConstrainOperandRC, /*InsnID*/1, /*Op*/0, GIMT_Encode2(AMDGPU::VReg_64RegClassID),
        GIR_ConstrainOperandRC, /*InsnID*/1, /*Op*/1, GIMT_Encode2(AMDGPU::VGPR_32RegClassID),
        GIR_ConstrainOperandRC, /*InsnID*/1, /*Op*/3, GIMT_Encode2(AMDGPU::VGPR_32RegClassID),
        GIR_BuildMI, /*InsnID*/0, /*Opcode*/GIMT_Encode2(AMDGPU::BUFFER_ATOMIC_AND_BOTHEN),
        GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/1, // vdata_in
        GIR_AddSimpleTempRegister, /*InsnID*/0, /*TempRegID*/0,
        GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/2, // rsrc
        GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/0, // soffset
        GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/6, // offset
        GIR_CustomOperandRenderer, /*InsnID*/0, /*OldInsnID*/0, /*OpIdx*/7, /*OperandRenderer*/GIMT_Encode2(GICR_renderExtractCPol), // auxiliary
        GIR_MergeMemOperands, /*InsnID*/0, /*NumInsns*/1, /*MergeInsnID's*/0,
        GIR_ConstrainSelectedInstOperands, /*InsnID*/0,
        GIR_EraseFromParent, /*InsnID*/0,
        // GIR_Coverage, 4848,
        GIR_Done,
      // Label 5768: @419008
      GIM_Try, /*On fail goto*//*Label 5769*/ GIMT_Encode4(419111), // Rule ID 4856 //
        GIM_CheckHasNoUse, /*MI*/0,
        // MIs[0] offset
        GIM_CheckIsImm, /*MI*/0, /*Op*/6,
        // MIs[0] auxiliary
        GIM_CheckIsImm, /*MI*/0, /*Op*/7,
        // MIs[0] Operand 8
        GIM_CheckIsImm, /*MI*/0, /*Op*/8,
        GIM_CheckComplexPattern, /*MI*/0, /*Op*/5, /*Renderer*/GIMT_Encode2(0), GIMT_Encode2(GICP_gi_buf_soffset),
        // (SIbuffer_atomic_and:{ *:[i32] } i32:{ *:[i32] }:$vdata_in, v4i32:{ *:[v4i32] }:$rsrc, i32:{ *:[i32] }:$vindex, i32:{ *:[i32] }:$voffset, (BUFSOffset:{ *:[i32] } i32:{ *:[i32] }:$soffset), (timm:{ *:[i32] }):$offset, (timm:{ *:[i32] }):$auxiliary, (timm:{ *:[i1] }))<<P:Predicate_SIbuffer_atomic_and_noret>>  =>  (BUFFER_ATOMIC_AND_VBUFFER_BOTHEN anonymous_15037:{ *:[i32] }:$vdata_in, (REG_SEQUENCE:{ *:[i64] } VReg_64:{ *:[i32] }, VGPR_32:{ *:[i32] }:$vindex, sub0:{ *:[i32] }, VGPR_32:{ *:[i32] }:$voffset, sub1:{ *:[i32] }), SReg_128:{ *:[v4i32] }:$rsrc, SCSrc_b32:{ *:[i32] }:$soffset, (timm:{ *:[i32] }):$offset, (extract_cpol:{ *:[i32] } ?:{ *:[i32] }:$auxiliary))
        GIR_MakeTempReg, /*TempRegID*/0, /*TypeID*/GILLT_s64,
        GIR_BuildMI, /*InsnID*/1, /*Opcode*/GIMT_Encode2(TargetOpcode::REG_SEQUENCE),
        GIR_AddTempRegister, /*InsnID*/1, /*TempRegID*/0, /*TempRegFlags*/GIMT_Encode2(RegState::Define),
        GIR_Copy, /*NewInsnID*/1, /*OldInsnID*/0, /*OpIdx*/3, // vindex
        GIR_AddImm8, /*InsnID*/1, /*SubRegIndex*/3,
        GIR_Copy, /*NewInsnID*/1, /*OldInsnID*/0, /*OpIdx*/4, // voffset
        GIR_AddImm8, /*InsnID*/1, /*SubRegIndex*/11,
        GIR_ConstrainOperandRC, /*InsnID*/1, /*Op*/0, GIMT_Encode2(AMDGPU::VReg_64RegClassID),
        GIR_ConstrainOperandRC, /*InsnID*/1, /*Op*/1, GIMT_Encode2(AMDGPU::VGPR_32RegClassID),
        GIR_ConstrainOperandRC, /*InsnID*/1, /*Op*/3, GIMT_Encode2(AMDGPU::VGPR_32RegClassID),
        GIR_BuildMI, /*InsnID*/0, /*Opcode*/GIMT_Encode2(AMDGPU::BUFFER_ATOMIC_AND_VBUFFER_BOTHEN),
        GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/1, // vdata_in
        GIR_AddSimpleTempRegister, /*InsnID*/0, /*TempRegID*/0,
        GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/2, // rsrc
        GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/0, // soffset
        GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/6, // offset
        GIR_CustomOperandRenderer, /*InsnID*/0, /*OldInsnID*/0, /*OpIdx*/7, /*OperandRenderer*/GIMT_Encode2(GICR_renderExtractCPol), // auxiliary
        GIR_MergeMemOperands, /*InsnID*/0, /*NumInsns*/1, /*MergeInsnID's*/0,
        GIR_ConstrainSelectedInstOperands, /*InsnID*/0,
        GIR_EraseFromParent, /*InsnID*/0,
        // GIR_Coverage, 4856,
        GIR_Done,
      // Label 5769: @419111
      GIM_Try, /*On fail goto*//*Label 5770*/ GIMT_Encode4(419224), // Rule ID 4844 //
        GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasUnrestrictedSOffset),
        GIM_CheckRegBankForClass, /*MI*/0, /*Op*/0, /*RC*/GIMT_Encode2(AMDGPU::AV_32RegClassID),
        // MIs[0] offset
        GIM_CheckIsImm, /*MI*/0, /*Op*/6,
        // MIs[0] auxiliary
        GIM_CheckIsImm, /*MI*/0, /*Op*/7,
        // MIs[0] Operand 8
        GIM_CheckIsImm, /*MI*/0, /*Op*/8,
        GIM_CheckComplexPattern, /*MI*/0, /*Op*/5, /*Renderer*/GIMT_Encode2(0), GIMT_Encode2(GICP_gi_buf_soffset),
        // (SIbuffer_atomic_and:{ *:[i32] } i32:{ *:[i32] }:$vdata_in, v4i32:{ *:[v4i32] }:$rsrc, i32:{ *:[i32] }:$vindex, i32:{ *:[i32] }:$voffset, (BUFSOffset:{ *:[i32] } i32:{ *:[i32] }:$soffset), (timm:{ *:[i32] }):$offset, (timm:{ *:[i32] }):$auxiliary, (timm:{ *:[i1] }))  =>  (BUFFER_ATOMIC_AND_BOTHEN_RTN:{ *:[i32] } anonymous_15037:{ *:[i32] }:$vdata_in, (REG_SEQUENCE:{ *:[i64] } VReg_64:{ *:[i32] }, VGPR_32:{ *:[i32] }:$vindex, sub0:{ *:[i32] }, VGPR_32:{ *:[i32] }:$voffset, sub1:{ *:[i32] }), SReg_128:{ *:[v4i32] }:$rsrc, SCSrc_b32:{ *:[i32] }:$soffset, (timm:{ *:[i32] }):$offset, (extract_cpol_set_glc:{ *:[i32] } ?:{ *:[i32] }:$auxiliary))
        GIR_MakeTempReg, /*TempRegID*/0, /*TypeID*/GILLT_s64,
        GIR_BuildMI, /*InsnID*/1, /*Opcode*/GIMT_Encode2(TargetOpcode::REG_SEQUENCE),
        GIR_AddTempRegister, /*InsnID*/1, /*TempRegID*/0, /*TempRegFlags*/GIMT_Encode2(RegState::Define),
        GIR_Copy, /*NewInsnID*/1, /*OldInsnID*/0, /*OpIdx*/3, // vindex
        GIR_AddImm8, /*InsnID*/1, /*SubRegIndex*/3,
        GIR_Copy, /*NewInsnID*/1, /*OldInsnID*/0, /*OpIdx*/4, // voffset
        GIR_AddImm8, /*InsnID*/1, /*SubRegIndex*/11,
        GIR_ConstrainOperandRC, /*InsnID*/1, /*Op*/0, GIMT_Encode2(AMDGPU::VReg_64RegClassID),
        GIR_ConstrainOperandRC, /*InsnID*/1, /*Op*/1, GIMT_Encode2(AMDGPU::VGPR_32RegClassID),
        GIR_ConstrainOperandRC, /*InsnID*/1, /*Op*/3, GIMT_Encode2(AMDGPU::VGPR_32RegClassID),
        GIR_BuildMI, /*InsnID*/0, /*Opcode*/GIMT_Encode2(AMDGPU::BUFFER_ATOMIC_AND_BOTHEN_RTN),
        GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/0, // DstI[vdata]
        GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/1, // vdata_in
        GIR_AddSimpleTempRegister, /*InsnID*/0, /*TempRegID*/0,
        GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/2, // rsrc
        GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/0, // soffset
        GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/6, // offset
        GIR_CustomOperandRenderer, /*InsnID*/0, /*OldInsnID*/0, /*OpIdx*/7, /*OperandRenderer*/GIMT_Encode2(GICR_renderExtractCpolSetGLC), // auxiliary
        GIR_MergeMemOperands, /*InsnID*/0, /*NumInsns*/1, /*MergeInsnID's*/0,
        GIR_ConstrainSelectedInstOperands, /*InsnID*/0,
        GIR_EraseFromParent, /*InsnID*/0,
        // GIR_Coverage, 4844,
        GIR_Done,
      // Label 5770: @419224
      GIM_Try, /*On fail goto*//*Label 5771*/ GIMT_Encode4(419334), // Rule ID 4852 //
        GIM_CheckRegBankForClass, /*MI*/0, /*Op*/0, /*RC*/GIMT_Encode2(AMDGPU::AV_32RegClassID),
        // MIs[0] offset
        GIM_CheckIsImm, /*MI*/0, /*Op*/6,
        // MIs[0] auxiliary
        GIM_CheckIsImm, /*MI*/0, /*Op*/7,
        // MIs[0] Operand 8
        GIM_CheckIsImm, /*MI*/0, /*Op*/8,
        GIM_CheckComplexPattern, /*MI*/0, /*Op*/5, /*Renderer*/GIMT_Encode2(0), GIMT_Encode2(GICP_gi_buf_soffset),
        // (SIbuffer_atomic_and:{ *:[i32] } i32:{ *:[i32] }:$vdata_in, v4i32:{ *:[v4i32] }:$rsrc, i32:{ *:[i32] }:$vindex, i32:{ *:[i32] }:$voffset, (BUFSOffset:{ *:[i32] } i32:{ *:[i32] }:$soffset), (timm:{ *:[i32] }):$offset, (timm:{ *:[i32] }):$auxiliary, (timm:{ *:[i1] }))  =>  (BUFFER_ATOMIC_AND_VBUFFER_BOTHEN_RTN:{ *:[i32] } anonymous_15037:{ *:[i32] }:$vdata_in, (REG_SEQUENCE:{ *:[i64] } VReg_64:{ *:[i32] }, VGPR_32:{ *:[i32] }:$vindex, sub0:{ *:[i32] }, VGPR_32:{ *:[i32] }:$voffset, sub1:{ *:[i32] }), SReg_128:{ *:[v4i32] }:$rsrc, SCSrc_b32:{ *:[i32] }:$soffset, (timm:{ *:[i32] }):$offset, (extract_cpol_set_glc:{ *:[i32] } ?:{ *:[i32] }:$auxiliary))
        GIR_MakeTempReg, /*TempRegID*/0, /*TypeID*/GILLT_s64,
        GIR_BuildMI, /*InsnID*/1, /*Opcode*/GIMT_Encode2(TargetOpcode::REG_SEQUENCE),
        GIR_AddTempRegister, /*InsnID*/1, /*TempRegID*/0, /*TempRegFlags*/GIMT_Encode2(RegState::Define),
        GIR_Copy, /*NewInsnID*/1, /*OldInsnID*/0, /*OpIdx*/3, // vindex
        GIR_AddImm8, /*InsnID*/1, /*SubRegIndex*/3,
        GIR_Copy, /*NewInsnID*/1, /*OldInsnID*/0, /*OpIdx*/4, // voffset
        GIR_AddImm8, /*InsnID*/1, /*SubRegIndex*/11,
        GIR_ConstrainOperandRC, /*InsnID*/1, /*Op*/0, GIMT_Encode2(AMDGPU::VReg_64RegClassID),
        GIR_ConstrainOperandRC, /*InsnID*/1, /*Op*/1, GIMT_Encode2(AMDGPU::VGPR_32RegClassID),
        GIR_ConstrainOperandRC, /*InsnID*/1, /*Op*/3, GIMT_Encode2(AMDGPU::VGPR_32RegClassID),
        GIR_BuildMI, /*InsnID*/0, /*Opcode*/GIMT_Encode2(AMDGPU::BUFFER_ATOMIC_AND_VBUFFER_BOTHEN_RTN),
        GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/0, // DstI[vdata]
        GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/1, // vdata_in
        GIR_AddSimpleTempRegister, /*InsnID*/0, /*TempRegID*/0,
        GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/2, // rsrc
        GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/0, // soffset
        GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/6, // offset
        GIR_CustomOperandRenderer, /*InsnID*/0, /*OldInsnID*/0, /*OpIdx*/7, /*OperandRenderer*/GIMT_Encode2(GICR_renderExtractCpolSetGLC), // auxiliary
        GIR_MergeMemOperands, /*InsnID*/0, /*NumInsns*/1, /*MergeInsnID's*/0,
        GIR_ConstrainSelectedInstOperands, /*InsnID*/0,
        GIR_EraseFromParent, /*InsnID*/0,
        // GIR_Coverage, 4852,
        GIR_Done,
      // Label 5771: @419334
      GIM_Reject,
    // Label 5755: @419335
    GIM_Reject,
    // Label 5753: @419336
    GIM_Try, /*On fail goto*//*Label 5772*/ GIMT_Encode4(420722),
      GIM_CheckType, /*MI*/0, /*Op*/1, /*Type*/GILLT_s64,
      GIM_CheckType, /*MI*/0, /*Op*/2, /*Type*/GILLT_v4s32,
      GIM_CheckType, /*MI*/0, /*Op*/3, /*Type*/GILLT_s32,
      GIM_CheckType, /*MI*/0, /*Op*/4, /*Type*/GILLT_s32,
      GIM_CheckType, /*MI*/0, /*Op*/5, /*Type*/GILLT_s32,
      GIM_Try, /*On fail goto*//*Label 5773*/ GIMT_Encode4(419439), // Rule ID 5045 //
        GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasUnrestrictedSOffset),
        GIM_CheckHasNoUse, /*MI*/0,
        GIM_CheckConstantInt8, /*MI*/0, /*Op*/3, 0,
        GIM_CheckConstantInt8, /*MI*/0, /*Op*/4, 0,
        // MIs[0] offset
        GIM_CheckIsImm, /*MI*/0, /*Op*/6,
        // MIs[0] auxiliary
        GIM_CheckIsImm, /*MI*/0, /*Op*/7,
        // MIs[0] Operand 8
        GIM_CheckLiteralInt, /*MI*/0, /*Op*/8, GIMT_Encode8(0),
        GIM_CheckComplexPattern, /*MI*/0, /*Op*/5, /*Renderer*/GIMT_Encode2(0), GIMT_Encode2(GICP_gi_buf_soffset),
        // (SIbuffer_atomic_and:{ *:[i64] } i64:{ *:[i64] }:$vdata_in, v4i32:{ *:[v4i32] }:$rsrc, 0:{ *:[i32] }, 0:{ *:[i32] }, (BUFSOffset:{ *:[i32] } i32:{ *:[i32] }:$soffset), (timm:{ *:[i32] }):$offset, (timm:{ *:[i32] }):$auxiliary, 0:{ *:[i1] })<<P:Predicate_SIbuffer_atomic_and_noret>>  =>  (BUFFER_ATOMIC_AND_X2_OFFSET anonymous_15036:{ *:[i64] }:$vdata_in, SReg_128:{ *:[v4i32] }:$rsrc, SCSrc_b32:{ *:[i32] }:$soffset, (timm:{ *:[i32] }):$offset, (extract_cpol:{ *:[i32] } ?:{ *:[i32] }:$auxiliary))
        GIR_BuildMI, /*InsnID*/0, /*Opcode*/GIMT_Encode2(AMDGPU::BUFFER_ATOMIC_AND_X2_OFFSET),
        GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/1, // vdata_in
        GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/2, // rsrc
        GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/0, // soffset
        GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/6, // offset
        GIR_CustomOperandRenderer, /*InsnID*/0, /*OldInsnID*/0, /*OpIdx*/7, /*OperandRenderer*/GIMT_Encode2(GICR_renderExtractCPol), // auxiliary
        GIR_MergeMemOperands, /*InsnID*/0, /*NumInsns*/1, /*MergeInsnID's*/0,
        GIR_ConstrainSelectedInstOperands, /*InsnID*/0,
        GIR_EraseFromParent, /*InsnID*/0,
        // GIR_Coverage, 5045,
        GIR_Done,
      // Label 5773: @419439
      GIM_Try, /*On fail goto*//*Label 5774*/ GIMT_Encode4(419514), // Rule ID 5053 //
        GIM_CheckHasNoUse, /*MI*/0,
        GIM_CheckConstantInt8, /*MI*/0, /*Op*/3, 0,
        GIM_CheckConstantInt8, /*MI*/0, /*Op*/4, 0,
        // MIs[0] offset
        GIM_CheckIsImm, /*MI*/0, /*Op*/6,
        // MIs[0] auxiliary
        GIM_CheckIsImm, /*MI*/0, /*Op*/7,
        // MIs[0] Operand 8
        GIM_CheckLiteralInt, /*MI*/0, /*Op*/8, GIMT_Encode8(0),
        GIM_CheckComplexPattern, /*MI*/0, /*Op*/5, /*Renderer*/GIMT_Encode2(0), GIMT_Encode2(GICP_gi_buf_soffset),
        // (SIbuffer_atomic_and:{ *:[i64] } i64:{ *:[i64] }:$vdata_in, v4i32:{ *:[v4i32] }:$rsrc, 0:{ *:[i32] }, 0:{ *:[i32] }, (BUFSOffset:{ *:[i32] } i32:{ *:[i32] }:$soffset), (timm:{ *:[i32] }):$offset, (timm:{ *:[i32] }):$auxiliary, 0:{ *:[i1] })<<P:Predicate_SIbuffer_atomic_and_noret>>  =>  (BUFFER_ATOMIC_AND_X2_VBUFFER_OFFSET anonymous_15036:{ *:[i64] }:$vdata_in, SReg_128:{ *:[v4i32] }:$rsrc, SCSrc_b32:{ *:[i32] }:$soffset, (timm:{ *:[i32] }):$offset, (extract_cpol:{ *:[i32] } ?:{ *:[i32] }:$auxiliary))
        GIR_BuildMI, /*InsnID*/0, /*Opcode*/GIMT_Encode2(AMDGPU::BUFFER_ATOMIC_AND_X2_VBUFFER_OFFSET),
        GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/1, // vdata_in
        GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/2, // rsrc
        GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/0, // soffset
        GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/6, // offset
        GIR_CustomOperandRenderer, /*InsnID*/0, /*OldInsnID*/0, /*OpIdx*/7, /*OperandRenderer*/GIMT_Encode2(GICR_renderExtractCPol), // auxiliary
        GIR_MergeMemOperands, /*InsnID*/0, /*NumInsns*/1, /*MergeInsnID's*/0,
        GIR_ConstrainSelectedInstOperands, /*InsnID*/0,
        GIR_EraseFromParent, /*InsnID*/0,
        // GIR_Coverage, 5053,
        GIR_Done,
      // Label 5774: @419514
      GIM_Try, /*On fail goto*//*Label 5775*/ GIMT_Encode4(419599), // Rule ID 5041 //
        GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasUnrestrictedSOffset),
        GIM_CheckRegBankForClass, /*MI*/0, /*Op*/0, /*RC*/GIMT_Encode2(AMDGPU::AV_64RegClassID),
        GIM_CheckConstantInt8, /*MI*/0, /*Op*/3, 0,
        GIM_CheckConstantInt8, /*MI*/0, /*Op*/4, 0,
        // MIs[0] offset
        GIM_CheckIsImm, /*MI*/0, /*Op*/6,
        // MIs[0] auxiliary
        GIM_CheckIsImm, /*MI*/0, /*Op*/7,
        // MIs[0] Operand 8
        GIM_CheckLiteralInt, /*MI*/0, /*Op*/8, GIMT_Encode8(0),
        GIM_CheckComplexPattern, /*MI*/0, /*Op*/5, /*Renderer*/GIMT_Encode2(0), GIMT_Encode2(GICP_gi_buf_soffset),
        // (SIbuffer_atomic_and:{ *:[i64] } i64:{ *:[i64] }:$vdata_in, v4i32:{ *:[v4i32] }:$rsrc, 0:{ *:[i32] }, 0:{ *:[i32] }, (BUFSOffset:{ *:[i32] } i32:{ *:[i32] }:$soffset), (timm:{ *:[i32] }):$offset, (timm:{ *:[i32] }):$auxiliary, 0:{ *:[i1] })  =>  (BUFFER_ATOMIC_AND_X2_OFFSET_RTN:{ *:[i64] } anonymous_15036:{ *:[i64] }:$vdata_in, SReg_128:{ *:[v4i32] }:$rsrc, SCSrc_b32:{ *:[i32] }:$soffset, (timm:{ *:[i32] }):$offset, (extract_cpol_set_glc:{ *:[i32] } ?:{ *:[i32] }:$auxiliary))
        GIR_BuildMI, /*InsnID*/0, /*Opcode*/GIMT_Encode2(AMDGPU::BUFFER_ATOMIC_AND_X2_OFFSET_RTN),
        GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/0, // DstI[vdata]
        GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/1, // vdata_in
        GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/2, // rsrc
        GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/0, // soffset
        GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/6, // offset
        GIR_CustomOperandRenderer, /*InsnID*/0, /*OldInsnID*/0, /*OpIdx*/7, /*OperandRenderer*/GIMT_Encode2(GICR_renderExtractCpolSetGLC), // auxiliary
        GIR_MergeMemOperands, /*InsnID*/0, /*NumInsns*/1, /*MergeInsnID's*/0,
        GIR_ConstrainSelectedInstOperands, /*InsnID*/0,
        GIR_EraseFromParent, /*InsnID*/0,
        // GIR_Coverage, 5041,
        GIR_Done,
      // Label 5775: @419599
      GIM_Try, /*On fail goto*//*Label 5776*/ GIMT_Encode4(419681), // Rule ID 5049 //
        GIM_CheckRegBankForClass, /*MI*/0, /*Op*/0, /*RC*/GIMT_Encode2(AMDGPU::AV_64RegClassID),
        GIM_CheckConstantInt8, /*MI*/0, /*Op*/3, 0,
        GIM_CheckConstantInt8, /*MI*/0, /*Op*/4, 0,
        // MIs[0] offset
        GIM_CheckIsImm, /*MI*/0, /*Op*/6,
        // MIs[0] auxiliary
        GIM_CheckIsImm, /*MI*/0, /*Op*/7,
        // MIs[0] Operand 8
        GIM_CheckLiteralInt, /*MI*/0, /*Op*/8, GIMT_Encode8(0),
        GIM_CheckComplexPattern, /*MI*/0, /*Op*/5, /*Renderer*/GIMT_Encode2(0), GIMT_Encode2(GICP_gi_buf_soffset),
        // (SIbuffer_atomic_and:{ *:[i64] } i64:{ *:[i64] }:$vdata_in, v4i32:{ *:[v4i32] }:$rsrc, 0:{ *:[i32] }, 0:{ *:[i32] }, (BUFSOffset:{ *:[i32] } i32:{ *:[i32] }:$soffset), (timm:{ *:[i32] }):$offset, (timm:{ *:[i32] }):$auxiliary, 0:{ *:[i1] })  =>  (BUFFER_ATOMIC_AND_X2_VBUFFER_OFFSET_RTN:{ *:[i64] } anonymous_15036:{ *:[i64] }:$vdata_in, SReg_128:{ *:[v4i32] }:$rsrc, SCSrc_b32:{ *:[i32] }:$soffset, (timm:{ *:[i32] }):$offset, (extract_cpol_set_glc:{ *:[i32] } ?:{ *:[i32] }:$auxiliary))
        GIR_BuildMI, /*InsnID*/0, /*Opcode*/GIMT_Encode2(AMDGPU::BUFFER_ATOMIC_AND_X2_VBUFFER_OFFSET_RTN),
        GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/0, // DstI[vdata]
        GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/1, // vdata_in
        GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/2, // rsrc
        GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/0, // soffset
        GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/6, // offset
        GIR_CustomOperandRenderer, /*InsnID*/0, /*OldInsnID*/0, /*OpIdx*/7, /*OperandRenderer*/GIMT_Encode2(GICR_renderExtractCpolSetGLC), // auxiliary
        GIR_MergeMemOperands, /*InsnID*/0, /*NumInsns*/1, /*MergeInsnID's*/0,
        GIR_ConstrainSelectedInstOperands, /*InsnID*/0,
        GIR_EraseFromParent, /*InsnID*/0,
        // GIR_Coverage, 5049,
        GIR_Done,
      // Label 5776: @419681
      GIM_Try, /*On fail goto*//*Label 5777*/ GIMT_Encode4(419759), // Rule ID 5047 //
        GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasUnrestrictedSOffset),
        GIM_CheckHasNoUse, /*MI*/0,
        GIM_CheckConstantInt8, /*MI*/0, /*Op*/3, 0,
        // MIs[0] offset
        GIM_CheckIsImm, /*MI*/0, /*Op*/6,
        // MIs[0] auxiliary
        GIM_CheckIsImm, /*MI*/0, /*Op*/7,
        // MIs[0] Operand 8
        GIM_CheckLiteralInt, /*MI*/0, /*Op*/8, GIMT_Encode8(0),
        GIM_CheckComplexPattern, /*MI*/0, /*Op*/5, /*Renderer*/GIMT_Encode2(0), GIMT_Encode2(GICP_gi_buf_soffset),
        // (SIbuffer_atomic_and:{ *:[i64] } i64:{ *:[i64] }:$vdata_in, v4i32:{ *:[v4i32] }:$rsrc, 0:{ *:[i32] }, i32:{ *:[i32] }:$voffset, (BUFSOffset:{ *:[i32] } i32:{ *:[i32] }:$soffset), (timm:{ *:[i32] }):$offset, (timm:{ *:[i32] }):$auxiliary, 0:{ *:[i1] })<<P:Predicate_SIbuffer_atomic_and_noret>>  =>  (BUFFER_ATOMIC_AND_X2_OFFEN anonymous_15036:{ *:[i64] }:$vdata_in, VGPR_32:{ *:[i32] }:$voffset, SReg_128:{ *:[v4i32] }:$rsrc, SCSrc_b32:{ *:[i32] }:$soffset, (timm:{ *:[i32] }):$offset, (extract_cpol:{ *:[i32] } ?:{ *:[i32] }:$auxiliary))
        GIR_BuildMI, /*InsnID*/0, /*Opcode*/GIMT_Encode2(AMDGPU::BUFFER_ATOMIC_AND_X2_OFFEN),
        GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/1, // vdata_in
        GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/4, // voffset
        GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/2, // rsrc
        GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/0, // soffset
        GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/6, // offset
        GIR_CustomOperandRenderer, /*InsnID*/0, /*OldInsnID*/0, /*OpIdx*/7, /*OperandRenderer*/GIMT_Encode2(GICR_renderExtractCPol), // auxiliary
        GIR_MergeMemOperands, /*InsnID*/0, /*NumInsns*/1, /*MergeInsnID's*/0,
        GIR_ConstrainSelectedInstOperands, /*InsnID*/0,
        GIR_EraseFromParent, /*InsnID*/0,
        // GIR_Coverage, 5047,
        GIR_Done,
      // Label 5777: @419759
      GIM_Try, /*On fail goto*//*Label 5778*/ GIMT_Encode4(419834), // Rule ID 5055 //
        GIM_CheckHasNoUse, /*MI*/0,
        GIM_CheckConstantInt8, /*MI*/0, /*Op*/3, 0,
        // MIs[0] offset
        GIM_CheckIsImm, /*MI*/0, /*Op*/6,
        // MIs[0] auxiliary
        GIM_CheckIsImm, /*MI*/0, /*Op*/7,
        // MIs[0] Operand 8
        GIM_CheckLiteralInt, /*MI*/0, /*Op*/8, GIMT_Encode8(0),
        GIM_CheckComplexPattern, /*MI*/0, /*Op*/5, /*Renderer*/GIMT_Encode2(0), GIMT_Encode2(GICP_gi_buf_soffset),
        // (SIbuffer_atomic_and:{ *:[i64] } i64:{ *:[i64] }:$vdata_in, v4i32:{ *:[v4i32] }:$rsrc, 0:{ *:[i32] }, i32:{ *:[i32] }:$voffset, (BUFSOffset:{ *:[i32] } i32:{ *:[i32] }:$soffset), (timm:{ *:[i32] }):$offset, (timm:{ *:[i32] }):$auxiliary, 0:{ *:[i1] })<<P:Predicate_SIbuffer_atomic_and_noret>>  =>  (BUFFER_ATOMIC_AND_X2_VBUFFER_OFFEN anonymous_15036:{ *:[i64] }:$vdata_in, VGPR_32:{ *:[i32] }:$voffset, SReg_128:{ *:[v4i32] }:$rsrc, SCSrc_b32:{ *:[i32] }:$soffset, (timm:{ *:[i32] }):$offset, (extract_cpol:{ *:[i32] } ?:{ *:[i32] }:$auxiliary))
        GIR_BuildMI, /*InsnID*/0, /*Opcode*/GIMT_Encode2(AMDGPU::BUFFER_ATOMIC_AND_X2_VBUFFER_OFFEN),
        GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/1, // vdata_in
        GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/4, // voffset
        GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/2, // rsrc
        GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/0, // soffset
        GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/6, // offset
        GIR_CustomOperandRenderer, /*InsnID*/0, /*OldInsnID*/0, /*OpIdx*/7, /*OperandRenderer*/GIMT_Encode2(GICR_renderExtractCPol), // auxiliary
        GIR_MergeMemOperands, /*InsnID*/0, /*NumInsns*/1, /*MergeInsnID's*/0,
        GIR_ConstrainSelectedInstOperands, /*InsnID*/0,
        GIR_EraseFromParent, /*InsnID*/0,
        // GIR_Coverage, 5055,
        GIR_Done,
      // Label 5778: @419834
      GIM_Try, /*On fail goto*//*Label 5779*/ GIMT_Encode4(419919), // Rule ID 5043 //
        GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasUnrestrictedSOffset),
        GIM_CheckRegBankForClass, /*MI*/0, /*Op*/0, /*RC*/GIMT_Encode2(AMDGPU::AV_64RegClassID),
        GIM_CheckConstantInt8, /*MI*/0, /*Op*/3, 0,
        // MIs[0] offset
        GIM_CheckIsImm, /*MI*/0, /*Op*/6,
        // MIs[0] auxiliary
        GIM_CheckIsImm, /*MI*/0, /*Op*/7,
        // MIs[0] Operand 8
        GIM_CheckLiteralInt, /*MI*/0, /*Op*/8, GIMT_Encode8(0),
        GIM_CheckComplexPattern, /*MI*/0, /*Op*/5, /*Renderer*/GIMT_Encode2(0), GIMT_Encode2(GICP_gi_buf_soffset),
        // (SIbuffer_atomic_and:{ *:[i64] } i64:{ *:[i64] }:$vdata_in, v4i32:{ *:[v4i32] }:$rsrc, 0:{ *:[i32] }, i32:{ *:[i32] }:$voffset, (BUFSOffset:{ *:[i32] } i32:{ *:[i32] }:$soffset), (timm:{ *:[i32] }):$offset, (timm:{ *:[i32] }):$auxiliary, 0:{ *:[i1] })  =>  (BUFFER_ATOMIC_AND_X2_OFFEN_RTN:{ *:[i64] } anonymous_15036:{ *:[i64] }:$vdata_in, VGPR_32:{ *:[i32] }:$voffset, SReg_128:{ *:[v4i32] }:$rsrc, SCSrc_b32:{ *:[i32] }:$soffset, (timm:{ *:[i32] }):$offset, (extract_cpol_set_glc:{ *:[i32] } ?:{ *:[i32] }:$auxiliary))
        GIR_BuildMI, /*InsnID*/0, /*Opcode*/GIMT_Encode2(AMDGPU::BUFFER_ATOMIC_AND_X2_OFFEN_RTN),
        GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/0, // DstI[vdata]
        GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/1, // vdata_in
        GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/4, // voffset
        GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/2, // rsrc
        GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/0, // soffset
        GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/6, // offset
        GIR_CustomOperandRenderer, /*InsnID*/0, /*OldInsnID*/0, /*OpIdx*/7, /*OperandRenderer*/GIMT_Encode2(GICR_renderExtractCpolSetGLC), // auxiliary
        GIR_MergeMemOperands, /*InsnID*/0, /*NumInsns*/1, /*MergeInsnID's*/0,
        GIR_ConstrainSelectedInstOperands, /*InsnID*/0,
        GIR_EraseFromParent, /*InsnID*/0,
        // GIR_Coverage, 5043,
        GIR_Done,
      // Label 5779: @419919
      GIM_Try, /*On fail goto*//*Label 5780*/ GIMT_Encode4(420001), // Rule ID 5051 //
        GIM_CheckRegBankForClass, /*MI*/0, /*Op*/0, /*RC*/GIMT_Encode2(AMDGPU::AV_64RegClassID),
        GIM_CheckConstantInt8, /*MI*/0, /*Op*/3, 0,
        // MIs[0] offset
        GIM_CheckIsImm, /*MI*/0, /*Op*/6,
        // MIs[0] auxiliary
        GIM_CheckIsImm, /*MI*/0, /*Op*/7,
        // MIs[0] Operand 8
        GIM_CheckLiteralInt, /*MI*/0, /*Op*/8, GIMT_Encode8(0),
        GIM_CheckComplexPattern, /*MI*/0, /*Op*/5, /*Renderer*/GIMT_Encode2(0), GIMT_Encode2(GICP_gi_buf_soffset),
        // (SIbuffer_atomic_and:{ *:[i64] } i64:{ *:[i64] }:$vdata_in, v4i32:{ *:[v4i32] }:$rsrc, 0:{ *:[i32] }, i32:{ *:[i32] }:$voffset, (BUFSOffset:{ *:[i32] } i32:{ *:[i32] }:$soffset), (timm:{ *:[i32] }):$offset, (timm:{ *:[i32] }):$auxiliary, 0:{ *:[i1] })  =>  (BUFFER_ATOMIC_AND_X2_VBUFFER_OFFEN_RTN:{ *:[i64] } anonymous_15036:{ *:[i64] }:$vdata_in, VGPR_32:{ *:[i32] }:$voffset, SReg_128:{ *:[v4i32] }:$rsrc, SCSrc_b32:{ *:[i32] }:$soffset, (timm:{ *:[i32] }):$offset, (extract_cpol_set_glc:{ *:[i32] } ?:{ *:[i32] }:$auxiliary))
        GIR_BuildMI, /*InsnID*/0, /*Opcode*/GIMT_Encode2(AMDGPU::BUFFER_ATOMIC_AND_X2_VBUFFER_OFFEN_RTN),
        GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/0, // DstI[vdata]
        GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/1, // vdata_in
        GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/4, // voffset
        GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/2, // rsrc
        GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/0, // soffset
        GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/6, // offset
        GIR_CustomOperandRenderer, /*InsnID*/0, /*OldInsnID*/0, /*OpIdx*/7, /*OperandRenderer*/GIMT_Encode2(GICR_renderExtractCpolSetGLC), // auxiliary
        GIR_MergeMemOperands, /*InsnID*/0, /*NumInsns*/1, /*MergeInsnID's*/0,
        GIR_ConstrainSelectedInstOperands, /*InsnID*/0,
        GIR_EraseFromParent, /*InsnID*/0,
        // GIR_Coverage, 5051,
        GIR_Done,
      // Label 5780: @420001
      GIM_Try, /*On fail goto*//*Label 5781*/ GIMT_Encode4(420071), // Rule ID 5046 //
        GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasUnrestrictedSOffset),
        GIM_CheckHasNoUse, /*MI*/0,
        GIM_CheckConstantInt8, /*MI*/0, /*Op*/4, 0,
        // MIs[0] offset
        GIM_CheckIsImm, /*MI*/0, /*Op*/6,
        // MIs[0] auxiliary
        GIM_CheckIsImm, /*MI*/0, /*Op*/7,
        // MIs[0] Operand 8
        GIM_CheckIsImm, /*MI*/0, /*Op*/8,
        GIM_CheckComplexPattern, /*MI*/0, /*Op*/5, /*Renderer*/GIMT_Encode2(0), GIMT_Encode2(GICP_gi_buf_soffset),
        // (SIbuffer_atomic_and:{ *:[i64] } i64:{ *:[i64] }:$vdata_in, v4i32:{ *:[v4i32] }:$rsrc, i32:{ *:[i32] }:$vindex, 0:{ *:[i32] }, (BUFSOffset:{ *:[i32] } i32:{ *:[i32] }:$soffset), (timm:{ *:[i32] }):$offset, (timm:{ *:[i32] }):$auxiliary, (timm:{ *:[i1] }))<<P:Predicate_SIbuffer_atomic_and_noret>>  =>  (BUFFER_ATOMIC_AND_X2_IDXEN anonymous_15036:{ *:[i64] }:$vdata_in, VGPR_32:{ *:[i32] }:$vindex, SReg_128:{ *:[v4i32] }:$rsrc, SCSrc_b32:{ *:[i32] }:$soffset, (timm:{ *:[i32] }):$offset, (extract_cpol:{ *:[i32] } ?:{ *:[i32] }:$auxiliary))
        GIR_BuildMI, /*InsnID*/0, /*Opcode*/GIMT_Encode2(AMDGPU::BUFFER_ATOMIC_AND_X2_IDXEN),
        GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/1, // vdata_in
        GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/3, // vindex
        GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/2, // rsrc
        GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/0, // soffset
        GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/6, // offset
        GIR_CustomOperandRenderer, /*InsnID*/0, /*OldInsnID*/0, /*OpIdx*/7, /*OperandRenderer*/GIMT_Encode2(GICR_renderExtractCPol), // auxiliary
        GIR_MergeMemOperands, /*InsnID*/0, /*NumInsns*/1, /*MergeInsnID's*/0,
        GIR_ConstrainSelectedInstOperands, /*InsnID*/0,
        GIR_EraseFromParent, /*InsnID*/0,
        // GIR_Coverage, 5046,
        GIR_Done,
      // Label 5781: @420071
      GIM_Try, /*On fail goto*//*Label 5782*/ GIMT_Encode4(420138), // Rule ID 5054 //
        GIM_CheckHasNoUse, /*MI*/0,
        GIM_CheckConstantInt8, /*MI*/0, /*Op*/4, 0,
        // MIs[0] offset
        GIM_CheckIsImm, /*MI*/0, /*Op*/6,
        // MIs[0] auxiliary
        GIM_CheckIsImm, /*MI*/0, /*Op*/7,
        // MIs[0] Operand 8
        GIM_CheckIsImm, /*MI*/0, /*Op*/8,
        GIM_CheckComplexPattern, /*MI*/0, /*Op*/5, /*Renderer*/GIMT_Encode2(0), GIMT_Encode2(GICP_gi_buf_soffset),
        // (SIbuffer_atomic_and:{ *:[i64] } i64:{ *:[i64] }:$vdata_in, v4i32:{ *:[v4i32] }:$rsrc, i32:{ *:[i32] }:$vindex, 0:{ *:[i32] }, (BUFSOffset:{ *:[i32] } i32:{ *:[i32] }:$soffset), (timm:{ *:[i32] }):$offset, (timm:{ *:[i32] }):$auxiliary, (timm:{ *:[i1] }))<<P:Predicate_SIbuffer_atomic_and_noret>>  =>  (BUFFER_ATOMIC_AND_X2_VBUFFER_IDXEN anonymous_15036:{ *:[i64] }:$vdata_in, VGPR_32:{ *:[i32] }:$vindex, SReg_128:{ *:[v4i32] }:$rsrc, SCSrc_b32:{ *:[i32] }:$soffset, (timm:{ *:[i32] }):$offset, (extract_cpol:{ *:[i32] } ?:{ *:[i32] }:$auxiliary))
        GIR_BuildMI, /*InsnID*/0, /*Opcode*/GIMT_Encode2(AMDGPU::BUFFER_ATOMIC_AND_X2_VBUFFER_IDXEN),
        GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/1, // vdata_in
        GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/3, // vindex
        GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/2, // rsrc
        GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/0, // soffset
        GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/6, // offset
        GIR_CustomOperandRenderer, /*InsnID*/0, /*OldInsnID*/0, /*OpIdx*/7, /*OperandRenderer*/GIMT_Encode2(GICR_renderExtractCPol), // auxiliary
        GIR_MergeMemOperands, /*InsnID*/0, /*NumInsns*/1, /*MergeInsnID's*/0,
        GIR_ConstrainSelectedInstOperands, /*InsnID*/0,
        GIR_EraseFromParent, /*InsnID*/0,
        // GIR_Coverage, 5054,
        GIR_Done,
      // Label 5782: @420138
      GIM_Try, /*On fail goto*//*Label 5783*/ GIMT_Encode4(420215), // Rule ID 5042 //
        GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasUnrestrictedSOffset),
        GIM_CheckRegBankForClass, /*MI*/0, /*Op*/0, /*RC*/GIMT_Encode2(AMDGPU::AV_64RegClassID),
        GIM_CheckConstantInt8, /*MI*/0, /*Op*/4, 0,
        // MIs[0] offset
        GIM_CheckIsImm, /*MI*/0, /*Op*/6,
        // MIs[0] auxiliary
        GIM_CheckIsImm, /*MI*/0, /*Op*/7,
        // MIs[0] Operand 8
        GIM_CheckIsImm, /*MI*/0, /*Op*/8,
        GIM_CheckComplexPattern, /*MI*/0, /*Op*/5, /*Renderer*/GIMT_Encode2(0), GIMT_Encode2(GICP_gi_buf_soffset),
        // (SIbuffer_atomic_and:{ *:[i64] } i64:{ *:[i64] }:$vdata_in, v4i32:{ *:[v4i32] }:$rsrc, i32:{ *:[i32] }:$vindex, 0:{ *:[i32] }, (BUFSOffset:{ *:[i32] } i32:{ *:[i32] }:$soffset), (timm:{ *:[i32] }):$offset, (timm:{ *:[i32] }):$auxiliary, (timm:{ *:[i1] }))  =>  (BUFFER_ATOMIC_AND_X2_IDXEN_RTN:{ *:[i64] } anonymous_15036:{ *:[i64] }:$vdata_in, VGPR_32:{ *:[i32] }:$vindex, SReg_128:{ *:[v4i32] }:$rsrc, SCSrc_b32:{ *:[i32] }:$soffset, (timm:{ *:[i32] }):$offset, (extract_cpol_set_glc:{ *:[i32] } ?:{ *:[i32] }:$auxiliary))
        GIR_BuildMI, /*InsnID*/0, /*Opcode*/GIMT_Encode2(AMDGPU::BUFFER_ATOMIC_AND_X2_IDXEN_RTN),
        GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/0, // DstI[vdata]
        GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/1, // vdata_in
        GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/3, // vindex
        GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/2, // rsrc
        GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/0, // soffset
        GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/6, // offset
        GIR_CustomOperandRenderer, /*InsnID*/0, /*OldInsnID*/0, /*OpIdx*/7, /*OperandRenderer*/GIMT_Encode2(GICR_renderExtractCpolSetGLC), // auxiliary
        GIR_MergeMemOperands, /*InsnID*/0, /*NumInsns*/1, /*MergeInsnID's*/0,
        GIR_ConstrainSelectedInstOperands, /*InsnID*/0,
        GIR_EraseFromParent, /*InsnID*/0,
        // GIR_Coverage, 5042,
        GIR_Done,
      // Label 5783: @420215
      GIM_Try, /*On fail goto*//*Label 5784*/ GIMT_Encode4(420289), // Rule ID 5050 //
        GIM_CheckRegBankForClass, /*MI*/0, /*Op*/0, /*RC*/GIMT_Encode2(AMDGPU::AV_64RegClassID),
        GIM_CheckConstantInt8, /*MI*/0, /*Op*/4, 0,
        // MIs[0] offset
        GIM_CheckIsImm, /*MI*/0, /*Op*/6,
        // MIs[0] auxiliary
        GIM_CheckIsImm, /*MI*/0, /*Op*/7,
        // MIs[0] Operand 8
        GIM_CheckIsImm, /*MI*/0, /*Op*/8,
        GIM_CheckComplexPattern, /*MI*/0, /*Op*/5, /*Renderer*/GIMT_Encode2(0), GIMT_Encode2(GICP_gi_buf_soffset),
        // (SIbuffer_atomic_and:{ *:[i64] } i64:{ *:[i64] }:$vdata_in, v4i32:{ *:[v4i32] }:$rsrc, i32:{ *:[i32] }:$vindex, 0:{ *:[i32] }, (BUFSOffset:{ *:[i32] } i32:{ *:[i32] }:$soffset), (timm:{ *:[i32] }):$offset, (timm:{ *:[i32] }):$auxiliary, (timm:{ *:[i1] }))  =>  (BUFFER_ATOMIC_AND_X2_VBUFFER_IDXEN_RTN:{ *:[i64] } anonymous_15036:{ *:[i64] }:$vdata_in, VGPR_32:{ *:[i32] }:$vindex, SReg_128:{ *:[v4i32] }:$rsrc, SCSrc_b32:{ *:[i32] }:$soffset, (timm:{ *:[i32] }):$offset, (extract_cpol_set_glc:{ *:[i32] } ?:{ *:[i32] }:$auxiliary))
        GIR_BuildMI, /*InsnID*/0, /*Opcode*/GIMT_Encode2(AMDGPU::BUFFER_ATOMIC_AND_X2_VBUFFER_IDXEN_RTN),
        GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/0, // DstI[vdata]
        GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/1, // vdata_in
        GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/3, // vindex
        GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/2, // rsrc
        GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/0, // soffset
        GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/6, // offset
        GIR_CustomOperandRenderer, /*InsnID*/0, /*OldInsnID*/0, /*OpIdx*/7, /*OperandRenderer*/GIMT_Encode2(GICR_renderExtractCpolSetGLC), // auxiliary
        GIR_MergeMemOperands, /*InsnID*/0, /*NumInsns*/1, /*MergeInsnID's*/0,
        GIR_ConstrainSelectedInstOperands, /*InsnID*/0,
        GIR_EraseFromParent, /*InsnID*/0,
        // GIR_Coverage, 5050,
        GIR_Done,
      // Label 5784: @420289
      GIM_Try, /*On fail goto*//*Label 5785*/ GIMT_Encode4(420395), // Rule ID 5048 //
        GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasUnrestrictedSOffset),
        GIM_CheckHasNoUse, /*MI*/0,
        // MIs[0] offset
        GIM_CheckIsImm, /*MI*/0, /*Op*/6,
        // MIs[0] auxiliary
        GIM_CheckIsImm, /*MI*/0, /*Op*/7,
        // MIs[0] Operand 8
        GIM_CheckIsImm, /*MI*/0, /*Op*/8,
        GIM_CheckComplexPattern, /*MI*/0, /*Op*/5, /*Renderer*/GIMT_Encode2(0), GIMT_Encode2(GICP_gi_buf_soffset),
        // (SIbuffer_atomic_and:{ *:[i64] } i64:{ *:[i64] }:$vdata_in, v4i32:{ *:[v4i32] }:$rsrc, i32:{ *:[i32] }:$vindex, i32:{ *:[i32] }:$voffset, (BUFSOffset:{ *:[i32] } i32:{ *:[i32] }:$soffset), (timm:{ *:[i32] }):$offset, (timm:{ *:[i32] }):$auxiliary, (timm:{ *:[i1] }))<<P:Predicate_SIbuffer_atomic_and_noret>>  =>  (BUFFER_ATOMIC_AND_X2_BOTHEN anonymous_15036:{ *:[i64] }:$vdata_in, (REG_SEQUENCE:{ *:[i64] } VReg_64:{ *:[i32] }, VGPR_32:{ *:[i32] }:$vindex, sub0:{ *:[i32] }, VGPR_32:{ *:[i32] }:$voffset, sub1:{ *:[i32] }), SReg_128:{ *:[v4i32] }:$rsrc, SCSrc_b32:{ *:[i32] }:$soffset, (timm:{ *:[i32] }):$offset, (extract_cpol:{ *:[i32] } ?:{ *:[i32] }:$auxiliary))
        GIR_MakeTempReg, /*TempRegID*/0, /*TypeID*/GILLT_s64,
        GIR_BuildMI, /*InsnID*/1, /*Opcode*/GIMT_Encode2(TargetOpcode::REG_SEQUENCE),
        GIR_AddTempRegister, /*InsnID*/1, /*TempRegID*/0, /*TempRegFlags*/GIMT_Encode2(RegState::Define),
        GIR_Copy, /*NewInsnID*/1, /*OldInsnID*/0, /*OpIdx*/3, // vindex
        GIR_AddImm8, /*InsnID*/1, /*SubRegIndex*/3,
        GIR_Copy, /*NewInsnID*/1, /*OldInsnID*/0, /*OpIdx*/4, // voffset
        GIR_AddImm8, /*InsnID*/1, /*SubRegIndex*/11,
        GIR_ConstrainOperandRC, /*InsnID*/1, /*Op*/0, GIMT_Encode2(AMDGPU::VReg_64RegClassID),
        GIR_ConstrainOperandRC, /*InsnID*/1, /*Op*/1, GIMT_Encode2(AMDGPU::VGPR_32RegClassID),
        GIR_ConstrainOperandRC, /*InsnID*/1, /*Op*/3, GIMT_Encode2(AMDGPU::VGPR_32RegClassID),
        GIR_BuildMI, /*InsnID*/0, /*Opcode*/GIMT_Encode2(AMDGPU::BUFFER_ATOMIC_AND_X2_BOTHEN),
        GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/1, // vdata_in
        GIR_AddSimpleTempRegister, /*InsnID*/0, /*TempRegID*/0,
        GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/2, // rsrc
        GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/0, // soffset
        GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/6, // offset
        GIR_CustomOperandRenderer, /*InsnID*/0, /*OldInsnID*/0, /*OpIdx*/7, /*OperandRenderer*/GIMT_Encode2(GICR_renderExtractCPol), // auxiliary
        GIR_MergeMemOperands, /*InsnID*/0, /*NumInsns*/1, /*MergeInsnID's*/0,
        GIR_ConstrainSelectedInstOperands, /*InsnID*/0,
        GIR_EraseFromParent, /*InsnID*/0,
        // GIR_Coverage, 5048,
        GIR_Done,
      // Label 5785: @420395
      GIM_Try, /*On fail goto*//*Label 5786*/ GIMT_Encode4(420498), // Rule ID 5056 //
        GIM_CheckHasNoUse, /*MI*/0,
        // MIs[0] offset
        GIM_CheckIsImm, /*MI*/0, /*Op*/6,
        // MIs[0] auxiliary
        GIM_CheckIsImm, /*MI*/0, /*Op*/7,
        // MIs[0] Operand 8
        GIM_CheckIsImm, /*MI*/0, /*Op*/8,
        GIM_CheckComplexPattern, /*MI*/0, /*Op*/5, /*Renderer*/GIMT_Encode2(0), GIMT_Encode2(GICP_gi_buf_soffset),
        // (SIbuffer_atomic_and:{ *:[i64] } i64:{ *:[i64] }:$vdata_in, v4i32:{ *:[v4i32] }:$rsrc, i32:{ *:[i32] }:$vindex, i32:{ *:[i32] }:$voffset, (BUFSOffset:{ *:[i32] } i32:{ *:[i32] }:$soffset), (timm:{ *:[i32] }):$offset, (timm:{ *:[i32] }):$auxiliary, (timm:{ *:[i1] }))<<P:Predicate_SIbuffer_atomic_and_noret>>  =>  (BUFFER_ATOMIC_AND_X2_VBUFFER_BOTHEN anonymous_15036:{ *:[i64] }:$vdata_in, (REG_SEQUENCE:{ *:[i64] } VReg_64:{ *:[i32] }, VGPR_32:{ *:[i32] }:$vindex, sub0:{ *:[i32] }, VGPR_32:{ *:[i32] }:$voffset, sub1:{ *:[i32] }), SReg_128:{ *:[v4i32] }:$rsrc, SCSrc_b32:{ *:[i32] }:$soffset, (timm:{ *:[i32] }):$offset, (extract_cpol:{ *:[i32] } ?:{ *:[i32] }:$auxiliary))
        GIR_MakeTempReg, /*TempRegID*/0, /*TypeID*/GILLT_s64,
        GIR_BuildMI, /*InsnID*/1, /*Opcode*/GIMT_Encode2(TargetOpcode::REG_SEQUENCE),
        GIR_AddTempRegister, /*InsnID*/1, /*TempRegID*/0, /*TempRegFlags*/GIMT_Encode2(RegState::Define),
        GIR_Copy, /*NewInsnID*/1, /*OldInsnID*/0, /*OpIdx*/3, // vindex
        GIR_AddImm8, /*InsnID*/1, /*SubRegIndex*/3,
        GIR_Copy, /*NewInsnID*/1, /*OldInsnID*/0, /*OpIdx*/4, // voffset
        GIR_AddImm8, /*InsnID*/1, /*SubRegIndex*/11,
        GIR_ConstrainOperandRC, /*InsnID*/1, /*Op*/0, GIMT_Encode2(AMDGPU::VReg_64RegClassID),
        GIR_ConstrainOperandRC, /*InsnID*/1, /*Op*/1, GIMT_Encode2(AMDGPU::VGPR_32RegClassID),
        GIR_ConstrainOperandRC, /*InsnID*/1, /*Op*/3, GIMT_Encode2(AMDGPU::VGPR_32RegClassID),
        GIR_BuildMI, /*InsnID*/0, /*Opcode*/GIMT_Encode2(AMDGPU::BUFFER_ATOMIC_AND_X2_VBUFFER_BOTHEN),
        GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/1, // vdata_in
        GIR_AddSimpleTempRegister, /*InsnID*/0, /*TempRegID*/0,
        GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/2, // rsrc
        GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/0, // soffset
        GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/6, // offset
        GIR_CustomOperandRenderer, /*InsnID*/0, /*OldInsnID*/0, /*OpIdx*/7, /*OperandRenderer*/GIMT_Encode2(GICR_renderExtractCPol), // auxiliary
        GIR_MergeMemOperands, /*InsnID*/0, /*NumInsns*/1, /*MergeInsnID's*/0,
        GIR_ConstrainSelectedInstOperands, /*InsnID*/0,
        GIR_EraseFromParent, /*InsnID*/0,
        // GIR_Coverage, 5056,
        GIR_Done,
      // Label 5786: @420498
      GIM_Try, /*On fail goto*//*Label 5787*/ GIMT_Encode4(420611), // Rule ID 5044 //
        GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasUnrestrictedSOffset),
        GIM_CheckRegBankForClass, /*MI*/0, /*Op*/0, /*RC*/GIMT_Encode2(AMDGPU::AV_64RegClassID),
        // MIs[0] offset
        GIM_CheckIsImm, /*MI*/0, /*Op*/6,
        // MIs[0] auxiliary
        GIM_CheckIsImm, /*MI*/0, /*Op*/7,
        // MIs[0] Operand 8
        GIM_CheckIsImm, /*MI*/0, /*Op*/8,
        GIM_CheckComplexPattern, /*MI*/0, /*Op*/5, /*Renderer*/GIMT_Encode2(0), GIMT_Encode2(GICP_gi_buf_soffset),
        // (SIbuffer_atomic_and:{ *:[i64] } i64:{ *:[i64] }:$vdata_in, v4i32:{ *:[v4i32] }:$rsrc, i32:{ *:[i32] }:$vindex, i32:{ *:[i32] }:$voffset, (BUFSOffset:{ *:[i32] } i32:{ *:[i32] }:$soffset), (timm:{ *:[i32] }):$offset, (timm:{ *:[i32] }):$auxiliary, (timm:{ *:[i1] }))  =>  (BUFFER_ATOMIC_AND_X2_BOTHEN_RTN:{ *:[i64] } anonymous_15036:{ *:[i64] }:$vdata_in, (REG_SEQUENCE:{ *:[i64] } VReg_64:{ *:[i32] }, VGPR_32:{ *:[i32] }:$vindex, sub0:{ *:[i32] }, VGPR_32:{ *:[i32] }:$voffset, sub1:{ *:[i32] }), SReg_128:{ *:[v4i32] }:$rsrc, SCSrc_b32:{ *:[i32] }:$soffset, (timm:{ *:[i32] }):$offset, (extract_cpol_set_glc:{ *:[i32] } ?:{ *:[i32] }:$auxiliary))
        GIR_MakeTempReg, /*TempRegID*/0, /*TypeID*/GILLT_s64,
        GIR_BuildMI, /*InsnID*/1, /*Opcode*/GIMT_Encode2(TargetOpcode::REG_SEQUENCE),
        GIR_AddTempRegister, /*InsnID*/1, /*TempRegID*/0, /*TempRegFlags*/GIMT_Encode2(RegState::Define),
        GIR_Copy, /*NewInsnID*/1, /*OldInsnID*/0, /*OpIdx*/3, // vindex
        GIR_AddImm8, /*InsnID*/1, /*SubRegIndex*/3,
        GIR_Copy, /*NewInsnID*/1, /*OldInsnID*/0, /*OpIdx*/4, // voffset
        GIR_AddImm8, /*InsnID*/1, /*SubRegIndex*/11,
        GIR_ConstrainOperandRC, /*InsnID*/1, /*Op*/0, GIMT_Encode2(AMDGPU::VReg_64RegClassID),
        GIR_ConstrainOperandRC, /*InsnID*/1, /*Op*/1, GIMT_Encode2(AMDGPU::VGPR_32RegClassID),
        GIR_ConstrainOperandRC, /*InsnID*/1, /*Op*/3, GIMT_Encode2(AMDGPU::VGPR_32RegClassID),
        GIR_BuildMI, /*InsnID*/0, /*Opcode*/GIMT_Encode2(AMDGPU::BUFFER_ATOMIC_AND_X2_BOTHEN_RTN),
        GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/0, // DstI[vdata]
        GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/1, // vdata_in
        GIR_AddSimpleTempRegister, /*InsnID*/0, /*TempRegID*/0,
        GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/2, // rsrc
        GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/0, // soffset
        GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/6, // offset
        GIR_CustomOperandRenderer, /*InsnID*/0, /*OldInsnID*/0, /*OpIdx*/7, /*OperandRenderer*/GIMT_Encode2(GICR_renderExtractCpolSetGLC), // auxiliary
        GIR_MergeMemOperands, /*InsnID*/0, /*NumInsns*/1, /*MergeInsnID's*/0,
        GIR_ConstrainSelectedInstOperands, /*InsnID*/0,
        GIR_EraseFromParent, /*InsnID*/0,
        // GIR_Coverage, 5044,
        GIR_Done,
      // Label 5787: @420611
      GIM_Try, /*On fail goto*//*Label 5788*/ GIMT_Encode4(420721), // Rule ID 5052 //
        GIM_CheckRegBankForClass, /*MI*/0, /*Op*/0, /*RC*/GIMT_Encode2(AMDGPU::AV_64RegClassID),
        // MIs[0] offset
        GIM_CheckIsImm, /*MI*/0, /*Op*/6,
        // MIs[0] auxiliary
        GIM_CheckIsImm, /*MI*/0, /*Op*/7,
        // MIs[0] Operand 8
        GIM_CheckIsImm, /*MI*/0, /*Op*/8,
        GIM_CheckComplexPattern, /*MI*/0, /*Op*/5, /*Renderer*/GIMT_Encode2(0), GIMT_Encode2(GICP_gi_buf_soffset),
        // (SIbuffer_atomic_and:{ *:[i64] } i64:{ *:[i64] }:$vdata_in, v4i32:{ *:[v4i32] }:$rsrc, i32:{ *:[i32] }:$vindex, i32:{ *:[i32] }:$voffset, (BUFSOffset:{ *:[i32] } i32:{ *:[i32] }:$soffset), (timm:{ *:[i32] }):$offset, (timm:{ *:[i32] }):$auxiliary, (timm:{ *:[i1] }))  =>  (BUFFER_ATOMIC_AND_X2_VBUFFER_BOTHEN_RTN:{ *:[i64] } anonymous_15036:{ *:[i64] }:$vdata_in, (REG_SEQUENCE:{ *:[i64] } VReg_64:{ *:[i32] }, VGPR_32:{ *:[i32] }:$vindex, sub0:{ *:[i32] }, VGPR_32:{ *:[i32] }:$voffset, sub1:{ *:[i32] }), SReg_128:{ *:[v4i32] }:$rsrc, SCSrc_b32:{ *:[i32] }:$soffset, (timm:{ *:[i32] }):$offset, (extract_cpol_set_glc:{ *:[i32] } ?:{ *:[i32] }:$auxiliary))
        GIR_MakeTempReg, /*TempRegID*/0, /*TypeID*/GILLT_s64,
        GIR_BuildMI, /*InsnID*/1, /*Opcode*/GIMT_Encode2(TargetOpcode::REG_SEQUENCE),
        GIR_AddTempRegister, /*InsnID*/1, /*TempRegID*/0, /*TempRegFlags*/GIMT_Encode2(RegState::Define),
        GIR_Copy, /*NewInsnID*/1, /*OldInsnID*/0, /*OpIdx*/3, // vindex
        GIR_AddImm8, /*InsnID*/1, /*SubRegIndex*/3,
        GIR_Copy, /*NewInsnID*/1, /*OldInsnID*/0, /*OpIdx*/4, // voffset
        GIR_AddImm8, /*InsnID*/1, /*SubRegIndex*/11,
        GIR_ConstrainOperandRC, /*InsnID*/1, /*Op*/0, GIMT_Encode2(AMDGPU::VReg_64RegClassID),
        GIR_ConstrainOperandRC, /*InsnID*/1, /*Op*/1, GIMT_Encode2(AMDGPU::VGPR_32RegClassID),
        GIR_ConstrainOperandRC, /*InsnID*/1, /*Op*/3, GIMT_Encode2(AMDGPU::VGPR_32RegClassID),
        GIR_BuildMI, /*InsnID*/0, /*Opcode*/GIMT_Encode2(AMDGPU::BUFFER_ATOMIC_AND_X2_VBUFFER_BOTHEN_RTN),
        GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/0, // DstI[vdata]
        GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/1, // vdata_in
        GIR_AddSimpleTempRegister, /*InsnID*/0, /*TempRegID*/0,
        GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/2, // rsrc
        GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/0, // soffset
        GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/6, // offset
        GIR_CustomOperandRenderer, /*InsnID*/0, /*OldInsnID*/0, /*OpIdx*/7, /*OperandRenderer*/GIMT_Encode2(GICR_renderExtractCpolSetGLC), // auxiliary
        GIR_MergeMemOperands, /*InsnID*/0, /*NumInsns*/1, /*MergeInsnID's*/0,
        GIR_ConstrainSelectedInstOperands, /*InsnID*/0,
        GIR_EraseFromParent, /*InsnID*/0,
        // GIR_Coverage, 5052,
        GIR_Done,
      // Label 5788: @420721
      GIM_Reject,
    // Label 5772: @420722
    GIM_Reject,
    // Label 5754: @420723
    GIM_Reject,
    // Label 108: @420724
    GIM_SwitchType, /*MI*/0, /*Op*/0, /*[*/GIMT_Encode2(9), GIMT_Encode2(11), /*)*//*default:*//*Label 5791*/ GIMT_Encode4(425269),
    /*GILLT_s32*//*Label 5789*/ GIMT_Encode4(420743),
    /*GILLT_s64*//*Label 5790*/ GIMT_Encode4(423006),
    // Label 5789: @420743
    GIM_Try, /*On fail goto*//*Label 5792*/ GIMT_Encode4(423005),
      GIM_CheckType, /*MI*/0, /*Op*/1, /*Type*/GILLT_s32,
      GIM_CheckType, /*MI*/0, /*Op*/2, /*Type*/GILLT_s32,
      GIM_CheckType, /*MI*/0, /*Op*/3, /*Type*/GILLT_v4s32,
      GIM_CheckType, /*MI*/0, /*Op*/4, /*Type*/GILLT_s32,
      GIM_CheckType, /*MI*/0, /*Op*/5, /*Type*/GILLT_s32,
      GIM_CheckType, /*MI*/0, /*Op*/6, /*Type*/GILLT_s32,
      GIM_Try, /*On fail goto*//*Label 5793*/ GIMT_Encode4(420890), // Rule ID 5293 //
        GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasUnrestrictedSOffset),
        GIM_CheckHasNoUse, /*MI*/0,
        GIM_CheckConstantInt8, /*MI*/0, /*Op*/4, 0,
        GIM_CheckConstantInt8, /*MI*/0, /*Op*/5, 0,
        // MIs[0] offset
        GIM_CheckIsImm, /*MI*/0, /*Op*/7,
        // MIs[0] auxiliary
        GIM_CheckIsImm, /*MI*/0, /*Op*/8,
        // MIs[0] Operand 9
        GIM_CheckLiteralInt, /*MI*/0, /*Op*/9, GIMT_Encode8(0),
        GIM_CheckComplexPattern, /*MI*/0, /*Op*/6, /*Renderer*/GIMT_Encode2(0), GIMT_Encode2(GICP_gi_buf_soffset),
        // (SIbuffer_atomic_cmpswap:{ *:[i32] } i32:{ *:[i32] }:$data, i32:{ *:[i32] }:$cmp, v4i32:{ *:[v4i32] }:$rsrc, 0:{ *:[i32] }, 0:{ *:[i32] }, (BUFSOffset:{ *:[i32] } i32:{ *:[i32] }:$soffset), (timm:{ *:[i32] }):$offset, (timm:{ *:[i32] }):$auxiliary, 0:{ *:[i1] })<<P:Predicate_SIbuffer_atomic_cmpswap_noret>>  =>  (BUFFER_ATOMIC_CMPSWAP_OFFSET (REG_SEQUENCE:{ *:[i64] } VReg_64:{ *:[i32] }, anonymous_15037:{ *:[i32] }:$data, sub0:{ *:[i32] }, anonymous_15037:{ *:[i32] }:$cmp, sub1:{ *:[i32] }), SReg_128:{ *:[v4i32] }:$rsrc, SCSrc_b32:{ *:[i32] }:$soffset, (timm:{ *:[i32] }):$offset, (extract_cpol:{ *:[i32] } ?:{ *:[i32] }:$auxiliary))
        GIR_MakeTempReg, /*TempRegID*/0, /*TypeID*/GILLT_s64,
        GIR_BuildMI, /*InsnID*/1, /*Opcode*/GIMT_Encode2(TargetOpcode::REG_SEQUENCE),
        GIR_AddTempRegister, /*InsnID*/1, /*TempRegID*/0, /*TempRegFlags*/GIMT_Encode2(RegState::Define),
        GIR_Copy, /*NewInsnID*/1, /*OldInsnID*/0, /*OpIdx*/1, // data
        GIR_AddImm8, /*InsnID*/1, /*SubRegIndex*/3,
        GIR_Copy, /*NewInsnID*/1, /*OldInsnID*/0, /*OpIdx*/2, // cmp
        GIR_AddImm8, /*InsnID*/1, /*SubRegIndex*/11,
        GIR_ConstrainOperandRC, /*InsnID*/1, /*Op*/0, GIMT_Encode2(AMDGPU::VReg_64RegClassID),
        GIR_ConstrainOperandRC, /*InsnID*/1, /*Op*/1, GIMT_Encode2(AMDGPU::VGPR_32RegClassID),
        GIR_ConstrainOperandRC, /*InsnID*/1, /*Op*/3, GIMT_Encode2(AMDGPU::VGPR_32RegClassID),
        GIR_BuildMI, /*InsnID*/0, /*Opcode*/GIMT_Encode2(AMDGPU::BUFFER_ATOMIC_CMPSWAP_OFFSET),
        GIR_AddSimpleTempRegister, /*InsnID*/0, /*TempRegID*/0,
        GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/3, // rsrc
        GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/0, // soffset
        GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/7, // offset
        GIR_CustomOperandRenderer, /*InsnID*/0, /*OldInsnID*/0, /*OpIdx*/8, /*OperandRenderer*/GIMT_Encode2(GICR_renderExtractCPol), // auxiliary
        GIR_MergeMemOperands, /*InsnID*/0, /*NumInsns*/1, /*MergeInsnID's*/0,
        GIR_ConstrainSelectedInstOperands, /*InsnID*/0,
        GIR_EraseFromParent, /*InsnID*/0,
        // GIR_Coverage, 5293,
        GIR_Done,
      // Label 5793: @420890
      GIM_Try, /*On fail goto*//*Label 5794*/ GIMT_Encode4(421005), // Rule ID 5301 //
        GIM_CheckHasNoUse, /*MI*/0,
        GIM_CheckConstantInt8, /*MI*/0, /*Op*/4, 0,
        GIM_CheckConstantInt8, /*MI*/0, /*Op*/5, 0,
        // MIs[0] offset
        GIM_CheckIsImm, /*MI*/0, /*Op*/7,
        // MIs[0] auxiliary
        GIM_CheckIsImm, /*MI*/0, /*Op*/8,
        // MIs[0] Operand 9
        GIM_CheckLiteralInt, /*MI*/0, /*Op*/9, GIMT_Encode8(0),
        GIM_CheckComplexPattern, /*MI*/0, /*Op*/6, /*Renderer*/GIMT_Encode2(0), GIMT_Encode2(GICP_gi_buf_soffset),
        // (SIbuffer_atomic_cmpswap:{ *:[i32] } i32:{ *:[i32] }:$data, i32:{ *:[i32] }:$cmp, v4i32:{ *:[v4i32] }:$rsrc, 0:{ *:[i32] }, 0:{ *:[i32] }, (BUFSOffset:{ *:[i32] } i32:{ *:[i32] }:$soffset), (timm:{ *:[i32] }):$offset, (timm:{ *:[i32] }):$auxiliary, 0:{ *:[i1] })<<P:Predicate_SIbuffer_atomic_cmpswap_noret>>  =>  (BUFFER_ATOMIC_CMPSWAP_VBUFFER_OFFSET (REG_SEQUENCE:{ *:[i64] } VReg_64:{ *:[i32] }, anonymous_15037:{ *:[i32] }:$data, sub0:{ *:[i32] }, anonymous_15037:{ *:[i32] }:$cmp, sub1:{ *:[i32] }), SReg_128:{ *:[v4i32] }:$rsrc, SCSrc_b32:{ *:[i32] }:$soffset, (timm:{ *:[i32] }):$offset, (extract_cpol:{ *:[i32] } ?:{ *:[i32] }:$auxiliary))
        GIR_MakeTempReg, /*TempRegID*/0, /*TypeID*/GILLT_s64,
        GIR_BuildMI, /*InsnID*/1, /*Opcode*/GIMT_Encode2(TargetOpcode::REG_SEQUENCE),
        GIR_AddTempRegister, /*InsnID*/1, /*TempRegID*/0, /*TempRegFlags*/GIMT_Encode2(RegState::Define),
        GIR_Copy, /*NewInsnID*/1, /*OldInsnID*/0, /*OpIdx*/1, // data
        GIR_AddImm8, /*InsnID*/1, /*SubRegIndex*/3,
        GIR_Copy, /*NewInsnID*/1, /*OldInsnID*/0, /*OpIdx*/2, // cmp
        GIR_AddImm8, /*InsnID*/1, /*SubRegIndex*/11,
        GIR_ConstrainOperandRC, /*InsnID*/1, /*Op*/0, GIMT_Encode2(AMDGPU::VReg_64RegClassID),
        GIR_ConstrainOperandRC, /*InsnID*/1, /*Op*/1, GIMT_Encode2(AMDGPU::VGPR_32RegClassID),
        GIR_ConstrainOperandRC, /*InsnID*/1, /*Op*/3, GIMT_Encode2(AMDGPU::VGPR_32RegClassID),
        GIR_BuildMI, /*InsnID*/0, /*Opcode*/GIMT_Encode2(AMDGPU::BUFFER_ATOMIC_CMPSWAP_VBUFFER_OFFSET),
        GIR_AddSimpleTempRegister, /*InsnID*/0, /*TempRegID*/0,
        GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/3, // rsrc
        GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/0, // soffset
        GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/7, // offset
        GIR_CustomOperandRenderer, /*InsnID*/0, /*OldInsnID*/0, /*OpIdx*/8, /*OperandRenderer*/GIMT_Encode2(GICR_renderExtractCPol), // auxiliary
        GIR_MergeMemOperands, /*InsnID*/0, /*NumInsns*/1, /*MergeInsnID's*/0,
        GIR_ConstrainSelectedInstOperands, /*InsnID*/0,
        GIR_EraseFromParent, /*InsnID*/0,
        // GIR_Coverage, 5301,
        GIR_Done,
      // Label 5794: @421005
      GIM_Try, /*On fail goto*//*Label 5795*/ GIMT_Encode4(421159), // Rule ID 5289 //
        GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasUnrestrictedSOffset),
        GIM_CheckRegBankForClass, /*MI*/0, /*Op*/0, /*RC*/GIMT_Encode2(AMDGPU::AV_64RegClassID),
        GIM_CheckConstantInt8, /*MI*/0, /*Op*/4, 0,
        GIM_CheckConstantInt8, /*MI*/0, /*Op*/5, 0,
        // MIs[0] offset
        GIM_CheckIsImm, /*MI*/0, /*Op*/7,
        // MIs[0] auxiliary
        GIM_CheckIsImm, /*MI*/0, /*Op*/8,
        // MIs[0] Operand 9
        GIM_CheckLiteralInt, /*MI*/0, /*Op*/9, GIMT_Encode8(0),
        GIM_CheckComplexPattern, /*MI*/0, /*Op*/6, /*Renderer*/GIMT_Encode2(0), GIMT_Encode2(GICP_gi_buf_soffset),
        // (SIbuffer_atomic_cmpswap:{ *:[i32] } i32:{ *:[i32] }:$data, i32:{ *:[i32] }:$cmp, v4i32:{ *:[v4i32] }:$rsrc, 0:{ *:[i32] }, 0:{ *:[i32] }, (BUFSOffset:{ *:[i32] } i32:{ *:[i32] }:$soffset), (timm:{ *:[i32] }):$offset, (timm:{ *:[i32] }):$auxiliary, 0:{ *:[i1] })  =>  (EXTRACT_SUBREG:{ *:[i32] } (BUFFER_ATOMIC_CMPSWAP_OFFSET_RTN:{ *:[i64] } (REG_SEQUENCE:{ *:[i64] } VReg_64:{ *:[i32] }, anonymous_15037:{ *:[i32] }:$data, sub0:{ *:[i32] }, anonymous_15037:{ *:[i32] }:$cmp, sub1:{ *:[i32] }), SReg_128:{ *:[v4i32] }:$rsrc, SCSrc_b32:{ *:[i32] }:$soffset, (timm:{ *:[i32] }):$offset, (extract_cpol_set_glc:{ *:[i32] } ?:{ *:[i32] }:$auxiliary)), sub0:{ *:[i32] })
        GIR_MakeTempReg, /*TempRegID*/0, /*TypeID*/GILLT_s64,
        GIR_MakeTempReg, /*TempRegID*/1, /*TypeID*/GILLT_s64,
        GIR_BuildMI, /*InsnID*/2, /*Opcode*/GIMT_Encode2(TargetOpcode::REG_SEQUENCE),
        GIR_AddTempRegister, /*InsnID*/2, /*TempRegID*/1, /*TempRegFlags*/GIMT_Encode2(RegState::Define),
        GIR_Copy, /*NewInsnID*/2, /*OldInsnID*/0, /*OpIdx*/1, // data
        GIR_AddImm8, /*InsnID*/2, /*SubRegIndex*/3,
        GIR_Copy, /*NewInsnID*/2, /*OldInsnID*/0, /*OpIdx*/2, // cmp
        GIR_AddImm8, /*InsnID*/2, /*SubRegIndex*/11,
        GIR_ConstrainOperandRC, /*InsnID*/2, /*Op*/0, GIMT_Encode2(AMDGPU::VReg_64RegClassID),
        GIR_ConstrainOperandRC, /*InsnID*/2, /*Op*/1, GIMT_Encode2(AMDGPU::VGPR_32RegClassID),
        GIR_ConstrainOperandRC, /*InsnID*/2, /*Op*/3, GIMT_Encode2(AMDGPU::VGPR_32RegClassID),
        GIR_BuildMI, /*InsnID*/1, /*Opcode*/GIMT_Encode2(AMDGPU::BUFFER_ATOMIC_CMPSWAP_OFFSET_RTN),
        GIR_AddTempRegister, /*InsnID*/1, /*TempRegID*/0, /*TempRegFlags*/GIMT_Encode2(RegState::Define),
        GIR_AddSimpleTempRegister, /*InsnID*/1, /*TempRegID*/1,
        GIR_Copy, /*NewInsnID*/1, /*OldInsnID*/0, /*OpIdx*/3, // rsrc
        GIR_ComplexSubOperandRenderer, /*InsnID*/1, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/0, // soffset
        GIR_Copy, /*NewInsnID*/1, /*OldInsnID*/0, /*OpIdx*/7, // offset
        GIR_CustomOperandRenderer, /*InsnID*/1, /*OldInsnID*/0, /*OpIdx*/8, /*OperandRenderer*/GIMT_Encode2(GICR_renderExtractCpolSetGLC), // auxiliary
        GIR_MergeMemOperands, /*InsnID*/1, /*NumInsns*/1, /*MergeInsnID's*/0,
        GIR_ConstrainSelectedInstOperands, /*InsnID*/1,
        GIR_BuildMI, /*InsnID*/0, /*Opcode*/GIMT_Encode2(TargetOpcode::COPY),
        GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/0, // DstI[dst]
        GIR_AddTempSubRegister, /*InsnID*/0, /*TempRegID*/0, /*TempRegFlags*/GIMT_Encode2(0), GIMT_Encode2(AMDGPU::sub0),
        GIR_ConstrainOperandRC, /*InsnID*/0, /*Op*/0, GIMT_Encode2(AMDGPU::AV_32RegClassID),
        GIR_ConstrainOperandRC, /*InsnID*/0, /*Op*/1, GIMT_Encode2(AMDGPU::AV_64RegClassID),
        GIR_EraseFromParent, /*InsnID*/0,
        // GIR_Coverage, 5289,
        GIR_Done,
      // Label 5795: @421159
      GIM_Try, /*On fail goto*//*Label 5796*/ GIMT_Encode4(421310), // Rule ID 5297 //
        GIM_CheckRegBankForClass, /*MI*/0, /*Op*/0, /*RC*/GIMT_Encode2(AMDGPU::AV_64RegClassID),
        GIM_CheckConstantInt8, /*MI*/0, /*Op*/4, 0,
        GIM_CheckConstantInt8, /*MI*/0, /*Op*/5, 0,
        // MIs[0] offset
        GIM_CheckIsImm, /*MI*/0, /*Op*/7,
        // MIs[0] auxiliary
        GIM_CheckIsImm, /*MI*/0, /*Op*/8,
        // MIs[0] Operand 9
        GIM_CheckLiteralInt, /*MI*/0, /*Op*/9, GIMT_Encode8(0),
        GIM_CheckComplexPattern, /*MI*/0, /*Op*/6, /*Renderer*/GIMT_Encode2(0), GIMT_Encode2(GICP_gi_buf_soffset),
        // (SIbuffer_atomic_cmpswap:{ *:[i32] } i32:{ *:[i32] }:$data, i32:{ *:[i32] }:$cmp, v4i32:{ *:[v4i32] }:$rsrc, 0:{ *:[i32] }, 0:{ *:[i32] }, (BUFSOffset:{ *:[i32] } i32:{ *:[i32] }:$soffset), (timm:{ *:[i32] }):$offset, (timm:{ *:[i32] }):$auxiliary, 0:{ *:[i1] })  =>  (EXTRACT_SUBREG:{ *:[i32] } (BUFFER_ATOMIC_CMPSWAP_VBUFFER_OFFSET_RTN:{ *:[i64] } (REG_SEQUENCE:{ *:[i64] } VReg_64:{ *:[i32] }, anonymous_15037:{ *:[i32] }:$data, sub0:{ *:[i32] }, anonymous_15037:{ *:[i32] }:$cmp, sub1:{ *:[i32] }), SReg_128:{ *:[v4i32] }:$rsrc, SCSrc_b32:{ *:[i32] }:$soffset, (timm:{ *:[i32] }):$offset, (extract_cpol_set_glc:{ *:[i32] } ?:{ *:[i32] }:$auxiliary)), sub0:{ *:[i32] })
        GIR_MakeTempReg, /*TempRegID*/0, /*TypeID*/GILLT_s64,
        GIR_MakeTempReg, /*TempRegID*/1, /*TypeID*/GILLT_s64,
        GIR_BuildMI, /*InsnID*/2, /*Opcode*/GIMT_Encode2(TargetOpcode::REG_SEQUENCE),
        GIR_AddTempRegister, /*InsnID*/2, /*TempRegID*/1, /*TempRegFlags*/GIMT_Encode2(RegState::Define),
        GIR_Copy, /*NewInsnID*/2, /*OldInsnID*/0, /*OpIdx*/1, // data
        GIR_AddImm8, /*InsnID*/2, /*SubRegIndex*/3,
        GIR_Copy, /*NewInsnID*/2, /*OldInsnID*/0, /*OpIdx*/2, // cmp
        GIR_AddImm8, /*InsnID*/2, /*SubRegIndex*/11,
        GIR_ConstrainOperandRC, /*InsnID*/2, /*Op*/0, GIMT_Encode2(AMDGPU::VReg_64RegClassID),
        GIR_ConstrainOperandRC, /*InsnID*/2, /*Op*/1, GIMT_Encode2(AMDGPU::VGPR_32RegClassID),
        GIR_ConstrainOperandRC, /*InsnID*/2, /*Op*/3, GIMT_Encode2(AMDGPU::VGPR_32RegClassID),
        GIR_BuildMI, /*InsnID*/1, /*Opcode*/GIMT_Encode2(AMDGPU::BUFFER_ATOMIC_CMPSWAP_VBUFFER_OFFSET_RTN),
        GIR_AddTempRegister, /*InsnID*/1, /*TempRegID*/0, /*TempRegFlags*/GIMT_Encode2(RegState::Define),
        GIR_AddSimpleTempRegister, /*InsnID*/1, /*TempRegID*/1,
        GIR_Copy, /*NewInsnID*/1, /*OldInsnID*/0, /*OpIdx*/3, // rsrc
        GIR_ComplexSubOperandRenderer, /*InsnID*/1, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/0, // soffset
        GIR_Copy, /*NewInsnID*/1, /*OldInsnID*/0, /*OpIdx*/7, // offset
        GIR_CustomOperandRenderer, /*InsnID*/1, /*OldInsnID*/0, /*OpIdx*/8, /*OperandRenderer*/GIMT_Encode2(GICR_renderExtractCpolSetGLC), // auxiliary
        GIR_MergeMemOperands, /*InsnID*/1, /*NumInsns*/1, /*MergeInsnID's*/0,
        GIR_ConstrainSelectedInstOperands, /*InsnID*/1,
        GIR_BuildMI, /*InsnID*/0, /*Opcode*/GIMT_Encode2(TargetOpcode::COPY),
        GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/0, // DstI[dst]
        GIR_AddTempSubRegister, /*InsnID*/0, /*TempRegID*/0, /*TempRegFlags*/GIMT_Encode2(0), GIMT_Encode2(AMDGPU::sub0),
        GIR_ConstrainOperandRC, /*InsnID*/0, /*Op*/0, GIMT_Encode2(AMDGPU::AV_32RegClassID),
        GIR_ConstrainOperandRC, /*InsnID*/0, /*Op*/1, GIMT_Encode2(AMDGPU::AV_64RegClassID),
        GIR_EraseFromParent, /*InsnID*/0,
        // GIR_Coverage, 5297,
        GIR_Done,
      // Label 5796: @421310
      GIM_Try, /*On fail goto*//*Label 5797*/ GIMT_Encode4(421428), // Rule ID 5295 //
        GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasUnrestrictedSOffset),
        GIM_CheckHasNoUse, /*MI*/0,
        GIM_CheckConstantInt8, /*MI*/0, /*Op*/4, 0,
        // MIs[0] offset
        GIM_CheckIsImm, /*MI*/0, /*Op*/7,
        // MIs[0] auxiliary
        GIM_CheckIsImm, /*MI*/0, /*Op*/8,
        // MIs[0] Operand 9
        GIM_CheckLiteralInt, /*MI*/0, /*Op*/9, GIMT_Encode8(0),
        GIM_CheckComplexPattern, /*MI*/0, /*Op*/6, /*Renderer*/GIMT_Encode2(0), GIMT_Encode2(GICP_gi_buf_soffset),
        // (SIbuffer_atomic_cmpswap:{ *:[i32] } i32:{ *:[i32] }:$data, i32:{ *:[i32] }:$cmp, v4i32:{ *:[v4i32] }:$rsrc, 0:{ *:[i32] }, i32:{ *:[i32] }:$voffset, (BUFSOffset:{ *:[i32] } i32:{ *:[i32] }:$soffset), (timm:{ *:[i32] }):$offset, (timm:{ *:[i32] }):$auxiliary, 0:{ *:[i1] })<<P:Predicate_SIbuffer_atomic_cmpswap_noret>>  =>  (BUFFER_ATOMIC_CMPSWAP_OFFEN (REG_SEQUENCE:{ *:[i64] } VReg_64:{ *:[i32] }, anonymous_15037:{ *:[i32] }:$data, sub0:{ *:[i32] }, anonymous_15037:{ *:[i32] }:$cmp, sub1:{ *:[i32] }), VGPR_32:{ *:[i32] }:$voffset, SReg_128:{ *:[v4i32] }:$rsrc, SCSrc_b32:{ *:[i32] }:$soffset, (timm:{ *:[i32] }):$offset, (extract_cpol:{ *:[i32] } ?:{ *:[i32] }:$auxiliary))
        GIR_MakeTempReg, /*TempRegID*/0, /*TypeID*/GILLT_s64,
        GIR_BuildMI, /*InsnID*/1, /*Opcode*/GIMT_Encode2(TargetOpcode::REG_SEQUENCE),
        GIR_AddTempRegister, /*InsnID*/1, /*TempRegID*/0, /*TempRegFlags*/GIMT_Encode2(RegState::Define),
        GIR_Copy, /*NewInsnID*/1, /*OldInsnID*/0, /*OpIdx*/1, // data
        GIR_AddImm8, /*InsnID*/1, /*SubRegIndex*/3,
        GIR_Copy, /*NewInsnID*/1, /*OldInsnID*/0, /*OpIdx*/2, // cmp
        GIR_AddImm8, /*InsnID*/1, /*SubRegIndex*/11,
        GIR_ConstrainOperandRC, /*InsnID*/1, /*Op*/0, GIMT_Encode2(AMDGPU::VReg_64RegClassID),
        GIR_ConstrainOperandRC, /*InsnID*/1, /*Op*/1, GIMT_Encode2(AMDGPU::VGPR_32RegClassID),
        GIR_ConstrainOperandRC, /*InsnID*/1, /*Op*/3, GIMT_Encode2(AMDGPU::VGPR_32RegClassID),
        GIR_BuildMI, /*InsnID*/0, /*Opcode*/GIMT_Encode2(AMDGPU::BUFFER_ATOMIC_CMPSWAP_OFFEN),
        GIR_AddSimpleTempRegister, /*InsnID*/0, /*TempRegID*/0,
        GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/5, // voffset
        GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/3, // rsrc
        GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/0, // soffset
        GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/7, // offset
        GIR_CustomOperandRenderer, /*InsnID*/0, /*OldInsnID*/0, /*OpIdx*/8, /*OperandRenderer*/GIMT_Encode2(GICR_renderExtractCPol), // auxiliary
        GIR_MergeMemOperands, /*InsnID*/0, /*NumInsns*/1, /*MergeInsnID's*/0,
        GIR_ConstrainSelectedInstOperands, /*InsnID*/0,
        GIR_EraseFromParent, /*InsnID*/0,
        // GIR_Coverage, 5295,
        GIR_Done,
      // Label 5797: @421428
      GIM_Try, /*On fail goto*//*Label 5798*/ GIMT_Encode4(421543), // Rule ID 5303 //
        GIM_CheckHasNoUse, /*MI*/0,
        GIM_CheckConstantInt8, /*MI*/0, /*Op*/4, 0,
        // MIs[0] offset
        GIM_CheckIsImm, /*MI*/0, /*Op*/7,
        // MIs[0] auxiliary
        GIM_CheckIsImm, /*MI*/0, /*Op*/8,
        // MIs[0] Operand 9
        GIM_CheckLiteralInt, /*MI*/0, /*Op*/9, GIMT_Encode8(0),
        GIM_CheckComplexPattern, /*MI*/0, /*Op*/6, /*Renderer*/GIMT_Encode2(0), GIMT_Encode2(GICP_gi_buf_soffset),
        // (SIbuffer_atomic_cmpswap:{ *:[i32] } i32:{ *:[i32] }:$data, i32:{ *:[i32] }:$cmp, v4i32:{ *:[v4i32] }:$rsrc, 0:{ *:[i32] }, i32:{ *:[i32] }:$voffset, (BUFSOffset:{ *:[i32] } i32:{ *:[i32] }:$soffset), (timm:{ *:[i32] }):$offset, (timm:{ *:[i32] }):$auxiliary, 0:{ *:[i1] })<<P:Predicate_SIbuffer_atomic_cmpswap_noret>>  =>  (BUFFER_ATOMIC_CMPSWAP_VBUFFER_OFFEN (REG_SEQUENCE:{ *:[i64] } VReg_64:{ *:[i32] }, anonymous_15037:{ *:[i32] }:$data, sub0:{ *:[i32] }, anonymous_15037:{ *:[i32] }:$cmp, sub1:{ *:[i32] }), VGPR_32:{ *:[i32] }:$voffset, SReg_128:{ *:[v4i32] }:$rsrc, SCSrc_b32:{ *:[i32] }:$soffset, (timm:{ *:[i32] }):$offset, (extract_cpol:{ *:[i32] } ?:{ *:[i32] }:$auxiliary))
        GIR_MakeTempReg, /*TempRegID*/0, /*TypeID*/GILLT_s64,
        GIR_BuildMI, /*InsnID*/1, /*Opcode*/GIMT_Encode2(TargetOpcode::REG_SEQUENCE),
        GIR_AddTempRegister, /*InsnID*/1, /*TempRegID*/0, /*TempRegFlags*/GIMT_Encode2(RegState::Define),
        GIR_Copy, /*NewInsnID*/1, /*OldInsnID*/0, /*OpIdx*/1, // data
        GIR_AddImm8, /*InsnID*/1, /*SubRegIndex*/3,
        GIR_Copy, /*NewInsnID*/1, /*OldInsnID*/0, /*OpIdx*/2, // cmp
        GIR_AddImm8, /*InsnID*/1, /*SubRegIndex*/11,
        GIR_ConstrainOperandRC, /*InsnID*/1, /*Op*/0, GIMT_Encode2(AMDGPU::VReg_64RegClassID),
        GIR_ConstrainOperandRC, /*InsnID*/1, /*Op*/1, GIMT_Encode2(AMDGPU::VGPR_32RegClassID),
        GIR_ConstrainOperandRC, /*InsnID*/1, /*Op*/3, GIMT_Encode2(AMDGPU::VGPR_32RegClassID),
        GIR_BuildMI, /*InsnID*/0, /*Opcode*/GIMT_Encode2(AMDGPU::BUFFER_ATOMIC_CMPSWAP_VBUFFER_OFFEN),
        GIR_AddSimpleTempRegister, /*InsnID*/0, /*TempRegID*/0,
        GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/5, // voffset
        GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/3, // rsrc
        GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/0, // soffset
        GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/7, // offset
        GIR_CustomOperandRenderer, /*InsnID*/0, /*OldInsnID*/0, /*OpIdx*/8, /*OperandRenderer*/GIMT_Encode2(GICR_renderExtractCPol), // auxiliary
        GIR_MergeMemOperands, /*InsnID*/0, /*NumInsns*/1, /*MergeInsnID's*/0,
        GIR_ConstrainSelectedInstOperands, /*InsnID*/0,
        GIR_EraseFromParent, /*InsnID*/0,
        // GIR_Coverage, 5303,
        GIR_Done,
      // Label 5798: @421543
      GIM_Try, /*On fail goto*//*Label 5799*/ GIMT_Encode4(421697), // Rule ID 5291 //
        GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasUnrestrictedSOffset),
        GIM_CheckRegBankForClass, /*MI*/0, /*Op*/0, /*RC*/GIMT_Encode2(AMDGPU::AV_64RegClassID),
        GIM_CheckConstantInt8, /*MI*/0, /*Op*/4, 0,
        // MIs[0] offset
        GIM_CheckIsImm, /*MI*/0, /*Op*/7,
        // MIs[0] auxiliary
        GIM_CheckIsImm, /*MI*/0, /*Op*/8,
        // MIs[0] Operand 9
        GIM_CheckLiteralInt, /*MI*/0, /*Op*/9, GIMT_Encode8(0),
        GIM_CheckComplexPattern, /*MI*/0, /*Op*/6, /*Renderer*/GIMT_Encode2(0), GIMT_Encode2(GICP_gi_buf_soffset),
        // (SIbuffer_atomic_cmpswap:{ *:[i32] } i32:{ *:[i32] }:$data, i32:{ *:[i32] }:$cmp, v4i32:{ *:[v4i32] }:$rsrc, 0:{ *:[i32] }, i32:{ *:[i32] }:$voffset, (BUFSOffset:{ *:[i32] } i32:{ *:[i32] }:$soffset), (timm:{ *:[i32] }):$offset, (timm:{ *:[i32] }):$auxiliary, 0:{ *:[i1] })  =>  (EXTRACT_SUBREG:{ *:[i32] } (BUFFER_ATOMIC_CMPSWAP_OFFEN_RTN:{ *:[i64] } (REG_SEQUENCE:{ *:[i64] } VReg_64:{ *:[i32] }, anonymous_15037:{ *:[i32] }:$data, sub0:{ *:[i32] }, anonymous_15037:{ *:[i32] }:$cmp, sub1:{ *:[i32] }), VGPR_32:{ *:[i32] }:$voffset, SReg_128:{ *:[v4i32] }:$rsrc, SCSrc_b32:{ *:[i32] }:$soffset, (timm:{ *:[i32] }):$offset, (extract_cpol_set_glc:{ *:[i32] } ?:{ *:[i32] }:$auxiliary)), sub0:{ *:[i32] })
        GIR_MakeTempReg, /*TempRegID*/0, /*TypeID*/GILLT_s64,
        GIR_MakeTempReg, /*TempRegID*/1, /*TypeID*/GILLT_s64,
        GIR_BuildMI, /*InsnID*/2, /*Opcode*/GIMT_Encode2(TargetOpcode::REG_SEQUENCE),
        GIR_AddTempRegister, /*InsnID*/2, /*TempRegID*/1, /*TempRegFlags*/GIMT_Encode2(RegState::Define),
        GIR_Copy, /*NewInsnID*/2, /*OldInsnID*/0, /*OpIdx*/1, // data
        GIR_AddImm8, /*InsnID*/2, /*SubRegIndex*/3,
        GIR_Copy, /*NewInsnID*/2, /*OldInsnID*/0, /*OpIdx*/2, // cmp
        GIR_AddImm8, /*InsnID*/2, /*SubRegIndex*/11,
        GIR_ConstrainOperandRC, /*InsnID*/2, /*Op*/0, GIMT_Encode2(AMDGPU::VReg_64RegClassID),
        GIR_ConstrainOperandRC, /*InsnID*/2, /*Op*/1, GIMT_Encode2(AMDGPU::VGPR_32RegClassID),
        GIR_ConstrainOperandRC, /*InsnID*/2, /*Op*/3, GIMT_Encode2(AMDGPU::VGPR_32RegClassID),
        GIR_BuildMI, /*InsnID*/1, /*Opcode*/GIMT_Encode2(AMDGPU::BUFFER_ATOMIC_CMPSWAP_OFFEN_RTN),
        GIR_AddTempRegister, /*InsnID*/1, /*TempRegID*/0, /*TempRegFlags*/GIMT_Encode2(RegState::Define),
        GIR_AddSimpleTempRegister, /*InsnID*/1, /*TempRegID*/1,
        GIR_Copy, /*NewInsnID*/1, /*OldInsnID*/0, /*OpIdx*/5, // voffset
        GIR_Copy, /*NewInsnID*/1, /*OldInsnID*/0, /*OpIdx*/3, // rsrc
        GIR_ComplexSubOperandRenderer, /*InsnID*/1, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/0, // soffset
        GIR_Copy, /*NewInsnID*/1, /*OldInsnID*/0, /*OpIdx*/7, // offset
        GIR_CustomOperandRenderer, /*InsnID*/1, /*OldInsnID*/0, /*OpIdx*/8, /*OperandRenderer*/GIMT_Encode2(GICR_renderExtractCpolSetGLC), // auxiliary
        GIR_MergeMemOperands, /*InsnID*/1, /*NumInsns*/1, /*MergeInsnID's*/0,
        GIR_ConstrainSelectedInstOperands, /*InsnID*/1,
        GIR_BuildMI, /*InsnID*/0, /*Opcode*/GIMT_Encode2(TargetOpcode::COPY),
        GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/0, // DstI[dst]
        GIR_AddTempSubRegister, /*InsnID*/0, /*TempRegID*/0, /*TempRegFlags*/GIMT_Encode2(0), GIMT_Encode2(AMDGPU::sub0),
        GIR_ConstrainOperandRC, /*InsnID*/0, /*Op*/0, GIMT_Encode2(AMDGPU::AV_32RegClassID),
        GIR_ConstrainOperandRC, /*InsnID*/0, /*Op*/1, GIMT_Encode2(AMDGPU::AV_64RegClassID),
        GIR_EraseFromParent, /*InsnID*/0,
        // GIR_Coverage, 5291,
        GIR_Done,
      // Label 5799: @421697
      GIM_Try, /*On fail goto*//*Label 5800*/ GIMT_Encode4(421848), // Rule ID 5299 //
        GIM_CheckRegBankForClass, /*MI*/0, /*Op*/0, /*RC*/GIMT_Encode2(AMDGPU::AV_64RegClassID),
        GIM_CheckConstantInt8, /*MI*/0, /*Op*/4, 0,
        // MIs[0] offset
        GIM_CheckIsImm, /*MI*/0, /*Op*/7,
        // MIs[0] auxiliary
        GIM_CheckIsImm, /*MI*/0, /*Op*/8,
        // MIs[0] Operand 9
        GIM_CheckLiteralInt, /*MI*/0, /*Op*/9, GIMT_Encode8(0),
        GIM_CheckComplexPattern, /*MI*/0, /*Op*/6, /*Renderer*/GIMT_Encode2(0), GIMT_Encode2(GICP_gi_buf_soffset),
        // (SIbuffer_atomic_cmpswap:{ *:[i32] } i32:{ *:[i32] }:$data, i32:{ *:[i32] }:$cmp, v4i32:{ *:[v4i32] }:$rsrc, 0:{ *:[i32] }, i32:{ *:[i32] }:$voffset, (BUFSOffset:{ *:[i32] } i32:{ *:[i32] }:$soffset), (timm:{ *:[i32] }):$offset, (timm:{ *:[i32] }):$auxiliary, 0:{ *:[i1] })  =>  (EXTRACT_SUBREG:{ *:[i32] } (BUFFER_ATOMIC_CMPSWAP_VBUFFER_OFFEN_RTN:{ *:[i64] } (REG_SEQUENCE:{ *:[i64] } VReg_64:{ *:[i32] }, anonymous_15037:{ *:[i32] }:$data, sub0:{ *:[i32] }, anonymous_15037:{ *:[i32] }:$cmp, sub1:{ *:[i32] }), VGPR_32:{ *:[i32] }:$voffset, SReg_128:{ *:[v4i32] }:$rsrc, SCSrc_b32:{ *:[i32] }:$soffset, (timm:{ *:[i32] }):$offset, (extract_cpol_set_glc:{ *:[i32] } ?:{ *:[i32] }:$auxiliary)), sub0:{ *:[i32] })
        GIR_MakeTempReg, /*TempRegID*/0, /*TypeID*/GILLT_s64,
        GIR_MakeTempReg, /*TempRegID*/1, /*TypeID*/GILLT_s64,
        GIR_BuildMI, /*InsnID*/2, /*Opcode*/GIMT_Encode2(TargetOpcode::REG_SEQUENCE),
        GIR_AddTempRegister, /*InsnID*/2, /*TempRegID*/1, /*TempRegFlags*/GIMT_Encode2(RegState::Define),
        GIR_Copy, /*NewInsnID*/2, /*OldInsnID*/0, /*OpIdx*/1, // data
        GIR_AddImm8, /*InsnID*/2, /*SubRegIndex*/3,
        GIR_Copy, /*NewInsnID*/2, /*OldInsnID*/0, /*OpIdx*/2, // cmp
        GIR_AddImm8, /*InsnID*/2, /*SubRegIndex*/11,
        GIR_ConstrainOperandRC, /*InsnID*/2, /*Op*/0, GIMT_Encode2(AMDGPU::VReg_64RegClassID),
        GIR_ConstrainOperandRC, /*InsnID*/2, /*Op*/1, GIMT_Encode2(AMDGPU::VGPR_32RegClassID),
        GIR_ConstrainOperandRC, /*InsnID*/2, /*Op*/3, GIMT_Encode2(AMDGPU::VGPR_32RegClassID),
        GIR_BuildMI, /*InsnID*/1, /*Opcode*/GIMT_Encode2(AMDGPU::BUFFER_ATOMIC_CMPSWAP_VBUFFER_OFFEN_RTN),
        GIR_AddTempRegister, /*InsnID*/1, /*TempRegID*/0, /*TempRegFlags*/GIMT_Encode2(RegState::Define),
        GIR_AddSimpleTempRegister, /*InsnID*/1, /*TempRegID*/1,
        GIR_Copy, /*NewInsnID*/1, /*OldInsnID*/0, /*OpIdx*/5, // voffset
        GIR_Copy, /*NewInsnID*/1, /*OldInsnID*/0, /*OpIdx*/3, // rsrc
        GIR_ComplexSubOperandRenderer, /*InsnID*/1, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/0, // soffset
        GIR_Copy, /*NewInsnID*/1, /*OldInsnID*/0, /*OpIdx*/7, // offset
        GIR_CustomOperandRenderer, /*InsnID*/1, /*OldInsnID*/0, /*OpIdx*/8, /*OperandRenderer*/GIMT_Encode2(GICR_renderExtractCpolSetGLC), // auxiliary
        GIR_MergeMemOperands, /*InsnID*/1, /*NumInsns*/1, /*MergeInsnID's*/0,
        GIR_ConstrainSelectedInstOperands, /*InsnID*/1,
        GIR_BuildMI, /*InsnID*/0, /*Opcode*/GIMT_Encode2(TargetOpcode::COPY),
        GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/0, // DstI[dst]
        GIR_AddTempSubRegister, /*InsnID*/0, /*TempRegID*/0, /*TempRegFlags*/GIMT_Encode2(0), GIMT_Encode2(AMDGPU::sub0),
        GIR_ConstrainOperandRC, /*InsnID*/0, /*Op*/0, GIMT_Encode2(AMDGPU::AV_32RegClassID),
        GIR_ConstrainOperandRC, /*InsnID*/0, /*Op*/1, GIMT_Encode2(AMDGPU::AV_64RegClassID),
        GIR_EraseFromParent, /*InsnID*/0,
        // GIR_Coverage, 5299,
        GIR_Done,
      // Label 5800: @421848
      GIM_Try, /*On fail goto*//*Label 5801*/ GIMT_Encode4(421958), // Rule ID 5294 //
        GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasUnrestrictedSOffset),
        GIM_CheckHasNoUse, /*MI*/0,
        GIM_CheckConstantInt8, /*MI*/0, /*Op*/5, 0,
        // MIs[0] offset
        GIM_CheckIsImm, /*MI*/0, /*Op*/7,
        // MIs[0] auxiliary
        GIM_CheckIsImm, /*MI*/0, /*Op*/8,
        // MIs[0] Operand 9
        GIM_CheckIsImm, /*MI*/0, /*Op*/9,
        GIM_CheckComplexPattern, /*MI*/0, /*Op*/6, /*Renderer*/GIMT_Encode2(0), GIMT_Encode2(GICP_gi_buf_soffset),
        // (SIbuffer_atomic_cmpswap:{ *:[i32] } i32:{ *:[i32] }:$data, i32:{ *:[i32] }:$cmp, v4i32:{ *:[v4i32] }:$rsrc, i32:{ *:[i32] }:$vindex, 0:{ *:[i32] }, (BUFSOffset:{ *:[i32] } i32:{ *:[i32] }:$soffset), (timm:{ *:[i32] }):$offset, (timm:{ *:[i32] }):$auxiliary, (timm:{ *:[i1] }))<<P:Predicate_SIbuffer_atomic_cmpswap_noret>>  =>  (BUFFER_ATOMIC_CMPSWAP_IDXEN (REG_SEQUENCE:{ *:[i64] } VReg_64:{ *:[i32] }, anonymous_15037:{ *:[i32] }:$data, sub0:{ *:[i32] }, anonymous_15037:{ *:[i32] }:$cmp, sub1:{ *:[i32] }), VGPR_32:{ *:[i32] }:$vindex, SReg_128:{ *:[v4i32] }:$rsrc, SCSrc_b32:{ *:[i32] }:$soffset, (timm:{ *:[i32] }):$offset, (extract_cpol:{ *:[i32] } ?:{ *:[i32] }:$auxiliary))
        GIR_MakeTempReg, /*TempRegID*/0, /*TypeID*/GILLT_s64,
        GIR_BuildMI, /*InsnID*/1, /*Opcode*/GIMT_Encode2(TargetOpcode::REG_SEQUENCE),
        GIR_AddTempRegister, /*InsnID*/1, /*TempRegID*/0, /*TempRegFlags*/GIMT_Encode2(RegState::Define),
        GIR_Copy, /*NewInsnID*/1, /*OldInsnID*/0, /*OpIdx*/1, // data
        GIR_AddImm8, /*InsnID*/1, /*SubRegIndex*/3,
        GIR_Copy, /*NewInsnID*/1, /*OldInsnID*/0, /*OpIdx*/2, // cmp
        GIR_AddImm8, /*InsnID*/1, /*SubRegIndex*/11,
        GIR_ConstrainOperandRC, /*InsnID*/1, /*Op*/0, GIMT_Encode2(AMDGPU::VReg_64RegClassID),
        GIR_ConstrainOperandRC, /*InsnID*/1, /*Op*/1, GIMT_Encode2(AMDGPU::VGPR_32RegClassID),
        GIR_ConstrainOperandRC, /*InsnID*/1, /*Op*/3, GIMT_Encode2(AMDGPU::VGPR_32RegClassID),
        GIR_BuildMI, /*InsnID*/0, /*Opcode*/GIMT_Encode2(AMDGPU::BUFFER_ATOMIC_CMPSWAP_IDXEN),
        GIR_AddSimpleTempRegister, /*InsnID*/0, /*TempRegID*/0,
        GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/4, // vindex
        GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/3, // rsrc
        GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/0, // soffset
        GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/7, // offset
        GIR_CustomOperandRenderer, /*InsnID*/0, /*OldInsnID*/0, /*OpIdx*/8, /*OperandRenderer*/GIMT_Encode2(GICR_renderExtractCPol), // auxiliary
        GIR_MergeMemOperands, /*InsnID*/0, /*NumInsns*/1, /*MergeInsnID's*/0,
        GIR_ConstrainSelectedInstOperands, /*InsnID*/0,
        GIR_EraseFromParent, /*InsnID*/0,
        // GIR_Coverage, 5294,
        GIR_Done,
      // Label 5801: @421958
      GIM_Try, /*On fail goto*//*Label 5802*/ GIMT_Encode4(422065), // Rule ID 5302 //
        GIM_CheckHasNoUse, /*MI*/0,
        GIM_CheckConstantInt8, /*MI*/0, /*Op*/5, 0,
        // MIs[0] offset
        GIM_CheckIsImm, /*MI*/0, /*Op*/7,
        // MIs[0] auxiliary
        GIM_CheckIsImm, /*MI*/0, /*Op*/8,
        // MIs[0] Operand 9
        GIM_CheckIsImm, /*MI*/0, /*Op*/9,
        GIM_CheckComplexPattern, /*MI*/0, /*Op*/6, /*Renderer*/GIMT_Encode2(0), GIMT_Encode2(GICP_gi_buf_soffset),
        // (SIbuffer_atomic_cmpswap:{ *:[i32] } i32:{ *:[i32] }:$data, i32:{ *:[i32] }:$cmp, v4i32:{ *:[v4i32] }:$rsrc, i32:{ *:[i32] }:$vindex, 0:{ *:[i32] }, (BUFSOffset:{ *:[i32] } i32:{ *:[i32] }:$soffset), (timm:{ *:[i32] }):$offset, (timm:{ *:[i32] }):$auxiliary, (timm:{ *:[i1] }))<<P:Predicate_SIbuffer_atomic_cmpswap_noret>>  =>  (BUFFER_ATOMIC_CMPSWAP_VBUFFER_IDXEN (REG_SEQUENCE:{ *:[i64] } VReg_64:{ *:[i32] }, anonymous_15037:{ *:[i32] }:$data, sub0:{ *:[i32] }, anonymous_15037:{ *:[i32] }:$cmp, sub1:{ *:[i32] }), VGPR_32:{ *:[i32] }:$vindex, SReg_128:{ *:[v4i32] }:$rsrc, SCSrc_b32:{ *:[i32] }:$soffset, (timm:{ *:[i32] }):$offset, (extract_cpol:{ *:[i32] } ?:{ *:[i32] }:$auxiliary))
        GIR_MakeTempReg, /*TempRegID*/0, /*TypeID*/GILLT_s64,
        GIR_BuildMI, /*InsnID*/1, /*Opcode*/GIMT_Encode2(TargetOpcode::REG_SEQUENCE),
        GIR_AddTempRegister, /*InsnID*/1, /*TempRegID*/0, /*TempRegFlags*/GIMT_Encode2(RegState::Define),
        GIR_Copy, /*NewInsnID*/1, /*OldInsnID*/0, /*OpIdx*/1, // data
        GIR_AddImm8, /*InsnID*/1, /*SubRegIndex*/3,
        GIR_Copy, /*NewInsnID*/1, /*OldInsnID*/0, /*OpIdx*/2, // cmp
        GIR_AddImm8, /*InsnID*/1, /*SubRegIndex*/11,
        GIR_ConstrainOperandRC, /*InsnID*/1, /*Op*/0, GIMT_Encode2(AMDGPU::VReg_64RegClassID),
        GIR_ConstrainOperandRC, /*InsnID*/1, /*Op*/1, GIMT_Encode2(AMDGPU::VGPR_32RegClassID),
        GIR_ConstrainOperandRC, /*InsnID*/1, /*Op*/3, GIMT_Encode2(AMDGPU::VGPR_32RegClassID),
        GIR_BuildMI, /*InsnID*/0, /*Opcode*/GIMT_Encode2(AMDGPU::BUFFER_ATOMIC_CMPSWAP_VBUFFER_IDXEN),
        GIR_AddSimpleTempRegister, /*InsnID*/0, /*TempRegID*/0,
        GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/4, // vindex
        GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/3, // rsrc
        GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/0, // soffset
        GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/7, // offset
        GIR_CustomOperandRenderer, /*InsnID*/0, /*OldInsnID*/0, /*OpIdx*/8, /*OperandRenderer*/GIMT_Encode2(GICR_renderExtractCPol), // auxiliary
        GIR_MergeMemOperands, /*InsnID*/0, /*NumInsns*/1, /*MergeInsnID's*/0,
        GIR_ConstrainSelectedInstOperands, /*InsnID*/0,
        GIR_EraseFromParent, /*InsnID*/0,
        // GIR_Coverage, 5302,
        GIR_Done,
      // Label 5802: @422065
      GIM_Try, /*On fail goto*//*Label 5803*/ GIMT_Encode4(422211), // Rule ID 5290 //
        GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasUnrestrictedSOffset),
        GIM_CheckRegBankForClass, /*MI*/0, /*Op*/0, /*RC*/GIMT_Encode2(AMDGPU::AV_64RegClassID),
        GIM_CheckConstantInt8, /*MI*/0, /*Op*/5, 0,
        // MIs[0] offset
        GIM_CheckIsImm, /*MI*/0, /*Op*/7,
        // MIs[0] auxiliary
        GIM_CheckIsImm, /*MI*/0, /*Op*/8,
        // MIs[0] Operand 9
        GIM_CheckIsImm, /*MI*/0, /*Op*/9,
        GIM_CheckComplexPattern, /*MI*/0, /*Op*/6, /*Renderer*/GIMT_Encode2(0), GIMT_Encode2(GICP_gi_buf_soffset),
        // (SIbuffer_atomic_cmpswap:{ *:[i32] } i32:{ *:[i32] }:$data, i32:{ *:[i32] }:$cmp, v4i32:{ *:[v4i32] }:$rsrc, i32:{ *:[i32] }:$vindex, 0:{ *:[i32] }, (BUFSOffset:{ *:[i32] } i32:{ *:[i32] }:$soffset), (timm:{ *:[i32] }):$offset, (timm:{ *:[i32] }):$auxiliary, (timm:{ *:[i1] }))  =>  (EXTRACT_SUBREG:{ *:[i32] } (BUFFER_ATOMIC_CMPSWAP_IDXEN_RTN:{ *:[i64] } (REG_SEQUENCE:{ *:[i64] } VReg_64:{ *:[i32] }, anonymous_15037:{ *:[i32] }:$data, sub0:{ *:[i32] }, anonymous_15037:{ *:[i32] }:$cmp, sub1:{ *:[i32] }), VGPR_32:{ *:[i32] }:$vindex, SReg_128:{ *:[v4i32] }:$rsrc, SCSrc_b32:{ *:[i32] }:$soffset, (timm:{ *:[i32] }):$offset, (extract_cpol_set_glc:{ *:[i32] } ?:{ *:[i32] }:$auxiliary)), sub0:{ *:[i32] })
        GIR_MakeTempReg, /*TempRegID*/0, /*TypeID*/GILLT_s64,
        GIR_MakeTempReg, /*TempRegID*/1, /*TypeID*/GILLT_s64,
        GIR_BuildMI, /*InsnID*/2, /*Opcode*/GIMT_Encode2(TargetOpcode::REG_SEQUENCE),
        GIR_AddTempRegister, /*InsnID*/2, /*TempRegID*/1, /*TempRegFlags*/GIMT_Encode2(RegState::Define),
        GIR_Copy, /*NewInsnID*/2, /*OldInsnID*/0, /*OpIdx*/1, // data
        GIR_AddImm8, /*InsnID*/2, /*SubRegIndex*/3,
        GIR_Copy, /*NewInsnID*/2, /*OldInsnID*/0, /*OpIdx*/2, // cmp
        GIR_AddImm8, /*InsnID*/2, /*SubRegIndex*/11,
        GIR_ConstrainOperandRC, /*InsnID*/2, /*Op*/0, GIMT_Encode2(AMDGPU::VReg_64RegClassID),
        GIR_ConstrainOperandRC, /*InsnID*/2, /*Op*/1, GIMT_Encode2(AMDGPU::VGPR_32RegClassID),
        GIR_ConstrainOperandRC, /*InsnID*/2, /*Op*/3, GIMT_Encode2(AMDGPU::VGPR_32RegClassID),
        GIR_BuildMI, /*InsnID*/1, /*Opcode*/GIMT_Encode2(AMDGPU::BUFFER_ATOMIC_CMPSWAP_IDXEN_RTN),
        GIR_AddTempRegister, /*InsnID*/1, /*TempRegID*/0, /*TempRegFlags*/GIMT_Encode2(RegState::Define),
        GIR_AddSimpleTempRegister, /*InsnID*/1, /*TempRegID*/1,
        GIR_Copy, /*NewInsnID*/1, /*OldInsnID*/0, /*OpIdx*/4, // vindex
        GIR_Copy, /*NewInsnID*/1, /*OldInsnID*/0, /*OpIdx*/3, // rsrc
        GIR_ComplexSubOperandRenderer, /*InsnID*/1, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/0, // soffset
        GIR_Copy, /*NewInsnID*/1, /*OldInsnID*/0, /*OpIdx*/7, // offset
        GIR_CustomOperandRenderer, /*InsnID*/1, /*OldInsnID*/0, /*OpIdx*/8, /*OperandRenderer*/GIMT_Encode2(GICR_renderExtractCpolSetGLC), // auxiliary
        GIR_MergeMemOperands, /*InsnID*/1, /*NumInsns*/1, /*MergeInsnID's*/0,
        GIR_ConstrainSelectedInstOperands, /*InsnID*/1,
        GIR_BuildMI, /*InsnID*/0, /*Opcode*/GIMT_Encode2(TargetOpcode::COPY),
        GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/0, // DstI[dst]
        GIR_AddTempSubRegister, /*InsnID*/0, /*TempRegID*/0, /*TempRegFlags*/GIMT_Encode2(0), GIMT_Encode2(AMDGPU::sub0),
        GIR_ConstrainOperandRC, /*InsnID*/0, /*Op*/0, GIMT_Encode2(AMDGPU::AV_32RegClassID),
        GIR_ConstrainOperandRC, /*InsnID*/0, /*Op*/1, GIMT_Encode2(AMDGPU::AV_64RegClassID),
        GIR_EraseFromParent, /*InsnID*/0,
        // GIR_Coverage, 5290,
        GIR_Done,
      // Label 5803: @422211
      GIM_Try, /*On fail goto*//*Label 5804*/ GIMT_Encode4(422354), // Rule ID 5298 //
        GIM_CheckRegBankForClass, /*MI*/0, /*Op*/0, /*RC*/GIMT_Encode2(AMDGPU::AV_64RegClassID),
        GIM_CheckConstantInt8, /*MI*/0, /*Op*/5, 0,
        // MIs[0] offset
        GIM_CheckIsImm, /*MI*/0, /*Op*/7,
        // MIs[0] auxiliary
        GIM_CheckIsImm, /*MI*/0, /*Op*/8,
        // MIs[0] Operand 9
        GIM_CheckIsImm, /*MI*/0, /*Op*/9,
        GIM_CheckComplexPattern, /*MI*/0, /*Op*/6, /*Renderer*/GIMT_Encode2(0), GIMT_Encode2(GICP_gi_buf_soffset),
        // (SIbuffer_atomic_cmpswap:{ *:[i32] } i32:{ *:[i32] }:$data, i32:{ *:[i32] }:$cmp, v4i32:{ *:[v4i32] }:$rsrc, i32:{ *:[i32] }:$vindex, 0:{ *:[i32] }, (BUFSOffset:{ *:[i32] } i32:{ *:[i32] }:$soffset), (timm:{ *:[i32] }):$offset, (timm:{ *:[i32] }):$auxiliary, (timm:{ *:[i1] }))  =>  (EXTRACT_SUBREG:{ *:[i32] } (BUFFER_ATOMIC_CMPSWAP_VBUFFER_IDXEN_RTN:{ *:[i64] } (REG_SEQUENCE:{ *:[i64] } VReg_64:{ *:[i32] }, anonymous_15037:{ *:[i32] }:$data, sub0:{ *:[i32] }, anonymous_15037:{ *:[i32] }:$cmp, sub1:{ *:[i32] }), VGPR_32:{ *:[i32] }:$vindex, SReg_128:{ *:[v4i32] }:$rsrc, SCSrc_b32:{ *:[i32] }:$soffset, (timm:{ *:[i32] }):$offset, (extract_cpol_set_glc:{ *:[i32] } ?:{ *:[i32] }:$auxiliary)), sub0:{ *:[i32] })
        GIR_MakeTempReg, /*TempRegID*/0, /*TypeID*/GILLT_s64,
        GIR_MakeTempReg, /*TempRegID*/1, /*TypeID*/GILLT_s64,
        GIR_BuildMI, /*InsnID*/2, /*Opcode*/GIMT_Encode2(TargetOpcode::REG_SEQUENCE),
        GIR_AddTempRegister, /*InsnID*/2, /*TempRegID*/1, /*TempRegFlags*/GIMT_Encode2(RegState::Define),
        GIR_Copy, /*NewInsnID*/2, /*OldInsnID*/0, /*OpIdx*/1, // data
        GIR_AddImm8, /*InsnID*/2, /*SubRegIndex*/3,
        GIR_Copy, /*NewInsnID*/2, /*OldInsnID*/0, /*OpIdx*/2, // cmp
        GIR_AddImm8, /*InsnID*/2, /*SubRegIndex*/11,
        GIR_ConstrainOperandRC, /*InsnID*/2, /*Op*/0, GIMT_Encode2(AMDGPU::VReg_64RegClassID),
        GIR_ConstrainOperandRC, /*InsnID*/2, /*Op*/1, GIMT_Encode2(AMDGPU::VGPR_32RegClassID),
        GIR_ConstrainOperandRC, /*InsnID*/2, /*Op*/3, GIMT_Encode2(AMDGPU::VGPR_32RegClassID),
        GIR_BuildMI, /*InsnID*/1, /*Opcode*/GIMT_Encode2(AMDGPU::BUFFER_ATOMIC_CMPSWAP_VBUFFER_IDXEN_RTN),
        GIR_AddTempRegister, /*InsnID*/1, /*TempRegID*/0, /*TempRegFlags*/GIMT_Encode2(RegState::Define),
        GIR_AddSimpleTempRegister, /*InsnID*/1, /*TempRegID*/1,
        GIR_Copy, /*NewInsnID*/1, /*OldInsnID*/0, /*OpIdx*/4, // vindex
        GIR_Copy, /*NewInsnID*/1, /*OldInsnID*/0, /*OpIdx*/3, // rsrc
        GIR_ComplexSubOperandRenderer, /*InsnID*/1, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/0, // soffset
        GIR_Copy, /*NewInsnID*/1, /*OldInsnID*/0, /*OpIdx*/7, // offset
        GIR_CustomOperandRenderer, /*InsnID*/1, /*OldInsnID*/0, /*OpIdx*/8, /*OperandRenderer*/GIMT_Encode2(GICR_renderExtractCpolSetGLC), // auxiliary
        GIR_MergeMemOperands, /*InsnID*/1, /*NumInsns*/1, /*MergeInsnID's*/0,
        GIR_ConstrainSelectedInstOperands, /*InsnID*/1,
        GIR_BuildMI, /*InsnID*/0, /*Opcode*/GIMT_Encode2(TargetOpcode::COPY),
        GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/0, // DstI[dst]
        GIR_AddTempSubRegister, /*InsnID*/0, /*TempRegID*/0, /*TempRegFlags*/GIMT_Encode2(0), GIMT_Encode2(AMDGPU::sub0),
        GIR_ConstrainOperandRC, /*InsnID*/0, /*Op*/0, GIMT_Encode2(AMDGPU::AV_32RegClassID),
        GIR_ConstrainOperandRC, /*InsnID*/0, /*Op*/1, GIMT_Encode2(AMDGPU::AV_64RegClassID),
        GIR_EraseFromParent, /*InsnID*/0,
        // GIR_Coverage, 5298,
        GIR_Done,
      // Label 5804: @422354
      GIM_Try, /*On fail goto*//*Label 5805*/ GIMT_Encode4(422500), // Rule ID 5296 //
        GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasUnrestrictedSOffset),
        GIM_CheckHasNoUse, /*MI*/0,
        // MIs[0] offset
        GIM_CheckIsImm, /*MI*/0, /*Op*/7,
        // MIs[0] auxiliary
        GIM_CheckIsImm, /*MI*/0, /*Op*/8,
        // MIs[0] Operand 9
        GIM_CheckIsImm, /*MI*/0, /*Op*/9,
        GIM_CheckComplexPattern, /*MI*/0, /*Op*/6, /*Renderer*/GIMT_Encode2(0), GIMT_Encode2(GICP_gi_buf_soffset),
        // (SIbuffer_atomic_cmpswap:{ *:[i32] } i32:{ *:[i32] }:$data, i32:{ *:[i32] }:$cmp, v4i32:{ *:[v4i32] }:$rsrc, i32:{ *:[i32] }:$vindex, i32:{ *:[i32] }:$voffset, (BUFSOffset:{ *:[i32] } i32:{ *:[i32] }:$soffset), (timm:{ *:[i32] }):$offset, (timm:{ *:[i32] }):$auxiliary, (timm:{ *:[i1] }))<<P:Predicate_SIbuffer_atomic_cmpswap_noret>>  =>  (BUFFER_ATOMIC_CMPSWAP_BOTHEN (REG_SEQUENCE:{ *:[i64] } VReg_64:{ *:[i32] }, anonymous_15037:{ *:[i32] }:$data, sub0:{ *:[i32] }, anonymous_15037:{ *:[i32] }:$cmp, sub1:{ *:[i32] }), (REG_SEQUENCE:{ *:[i64] } VReg_64:{ *:[i32] }, VGPR_32:{ *:[i32] }:$vindex, sub0:{ *:[i32] }, VGPR_32:{ *:[i32] }:$voffset, sub1:{ *:[i32] }), SReg_128:{ *:[v4i32] }:$rsrc, SCSrc_b32:{ *:[i32] }:$soffset, (timm:{ *:[i32] }):$offset, (extract_cpol:{ *:[i32] } ?:{ *:[i32] }:$auxiliary))
        GIR_MakeTempReg, /*TempRegID*/0, /*TypeID*/GILLT_s64,
        GIR_MakeTempReg, /*TempRegID*/1, /*TypeID*/GILLT_s64,
        GIR_BuildMI, /*InsnID*/2, /*Opcode*/GIMT_Encode2(TargetOpcode::REG_SEQUENCE),
        GIR_AddTempRegister, /*InsnID*/2, /*TempRegID*/1, /*TempRegFlags*/GIMT_Encode2(RegState::Define),
        GIR_Copy, /*NewInsnID*/2, /*OldInsnID*/0, /*OpIdx*/4, // vindex
        GIR_AddImm8, /*InsnID*/2, /*SubRegIndex*/3,
        GIR_Copy, /*NewInsnID*/2, /*OldInsnID*/0, /*OpIdx*/5, // voffset
        GIR_AddImm8, /*InsnID*/2, /*SubRegIndex*/11,
        GIR_ConstrainOperandRC, /*InsnID*/2, /*Op*/0, GIMT_Encode2(AMDGPU::VReg_64RegClassID),
        GIR_ConstrainOperandRC, /*InsnID*/2, /*Op*/1, GIMT_Encode2(AMDGPU::VGPR_32RegClassID),
        GIR_ConstrainOperandRC, /*InsnID*/2, /*Op*/3, GIMT_Encode2(AMDGPU::VGPR_32RegClassID),
        GIR_BuildMI, /*InsnID*/1, /*Opcode*/GIMT_Encode2(TargetOpcode::REG_SEQUENCE),
        GIR_AddTempRegister, /*InsnID*/1, /*TempRegID*/0, /*TempRegFlags*/GIMT_Encode2(RegState::Define),
        GIR_Copy, /*NewInsnID*/1, /*OldInsnID*/0, /*OpIdx*/1, // data
        GIR_AddImm8, /*InsnID*/1, /*SubRegIndex*/3,
        GIR_Copy, /*NewInsnID*/1, /*OldInsnID*/0, /*OpIdx*/2, // cmp
        GIR_AddImm8, /*InsnID*/1, /*SubRegIndex*/11,
        GIR_ConstrainOperandRC, /*InsnID*/1, /*Op*/0, GIMT_Encode2(AMDGPU::VReg_64RegClassID),
        GIR_ConstrainOperandRC, /*InsnID*/1, /*Op*/1, GIMT_Encode2(AMDGPU::VGPR_32RegClassID),
        GIR_ConstrainOperandRC, /*InsnID*/1, /*Op*/3, GIMT_Encode2(AMDGPU::VGPR_32RegClassID),
        GIR_BuildMI, /*InsnID*/0, /*Opcode*/GIMT_Encode2(AMDGPU::BUFFER_ATOMIC_CMPSWAP_BOTHEN),
        GIR_AddSimpleTempRegister, /*InsnID*/0, /*TempRegID*/0,
        GIR_AddSimpleTempRegister, /*InsnID*/0, /*TempRegID*/1,
        GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/3, // rsrc
        GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/0, // soffset
        GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/7, // offset
        GIR_CustomOperandRenderer, /*InsnID*/0, /*OldInsnID*/0, /*OpIdx*/8, /*OperandRenderer*/GIMT_Encode2(GICR_renderExtractCPol), // auxiliary
        GIR_MergeMemOperands, /*InsnID*/0, /*NumInsns*/1, /*MergeInsnID's*/0,
        GIR_ConstrainSelectedInstOperands, /*InsnID*/0,
        GIR_EraseFromParent, /*InsnID*/0,
        // GIR_Coverage, 5296,
        GIR_Done,
      // Label 5805: @422500
      GIM_Try, /*On fail goto*//*Label 5806*/ GIMT_Encode4(422643), // Rule ID 5304 //
        GIM_CheckHasNoUse, /*MI*/0,
        // MIs[0] offset
        GIM_CheckIsImm, /*MI*/0, /*Op*/7,
        // MIs[0] auxiliary
        GIM_CheckIsImm, /*MI*/0, /*Op*/8,
        // MIs[0] Operand 9
        GIM_CheckIsImm, /*MI*/0, /*Op*/9,
        GIM_CheckComplexPattern, /*MI*/0, /*Op*/6, /*Renderer*/GIMT_Encode2(0), GIMT_Encode2(GICP_gi_buf_soffset),
        // (SIbuffer_atomic_cmpswap:{ *:[i32] } i32:{ *:[i32] }:$data, i32:{ *:[i32] }:$cmp, v4i32:{ *:[v4i32] }:$rsrc, i32:{ *:[i32] }:$vindex, i32:{ *:[i32] }:$voffset, (BUFSOffset:{ *:[i32] } i32:{ *:[i32] }:$soffset), (timm:{ *:[i32] }):$offset, (timm:{ *:[i32] }):$auxiliary, (timm:{ *:[i1] }))<<P:Predicate_SIbuffer_atomic_cmpswap_noret>>  =>  (BUFFER_ATOMIC_CMPSWAP_VBUFFER_BOTHEN (REG_SEQUENCE:{ *:[i64] } VReg_64:{ *:[i32] }, anonymous_15037:{ *:[i32] }:$data, sub0:{ *:[i32] }, anonymous_15037:{ *:[i32] }:$cmp, sub1:{ *:[i32] }), (REG_SEQUENCE:{ *:[i64] } VReg_64:{ *:[i32] }, VGPR_32:{ *:[i32] }:$vindex, sub0:{ *:[i32] }, VGPR_32:{ *:[i32] }:$voffset, sub1:{ *:[i32] }), SReg_128:{ *:[v4i32] }:$rsrc, SCSrc_b32:{ *:[i32] }:$soffset, (timm:{ *:[i32] }):$offset, (extract_cpol:{ *:[i32] } ?:{ *:[i32] }:$auxiliary))
        GIR_MakeTempReg, /*TempRegID*/0, /*TypeID*/GILLT_s64,
        GIR_MakeTempReg, /*TempRegID*/1, /*TypeID*/GILLT_s64,
        GIR_BuildMI, /*InsnID*/2, /*Opcode*/GIMT_Encode2(TargetOpcode::REG_SEQUENCE),
        GIR_AddTempRegister, /*InsnID*/2, /*TempRegID*/1, /*TempRegFlags*/GIMT_Encode2(RegState::Define),
        GIR_Copy, /*NewInsnID*/2, /*OldInsnID*/0, /*OpIdx*/4, // vindex
        GIR_AddImm8, /*InsnID*/2, /*SubRegIndex*/3,
        GIR_Copy, /*NewInsnID*/2, /*OldInsnID*/0, /*OpIdx*/5, // voffset
        GIR_AddImm8, /*InsnID*/2, /*SubRegIndex*/11,
        GIR_ConstrainOperandRC, /*InsnID*/2, /*Op*/0, GIMT_Encode2(AMDGPU::VReg_64RegClassID),
        GIR_ConstrainOperandRC, /*InsnID*/2, /*Op*/1, GIMT_Encode2(AMDGPU::VGPR_32RegClassID),
        GIR_ConstrainOperandRC, /*InsnID*/2, /*Op*/3, GIMT_Encode2(AMDGPU::VGPR_32RegClassID),
        GIR_BuildMI, /*InsnID*/1, /*Opcode*/GIMT_Encode2(TargetOpcode::REG_SEQUENCE),
        GIR_AddTempRegister, /*InsnID*/1, /*TempRegID*/0, /*TempRegFlags*/GIMT_Encode2(RegState::Define),
        GIR_Copy, /*NewInsnID*/1, /*OldInsnID*/0, /*OpIdx*/1, // data
        GIR_AddImm8, /*InsnID*/1, /*SubRegIndex*/3,
        GIR_Copy, /*NewInsnID*/1, /*OldInsnID*/0, /*OpIdx*/2, // cmp
        GIR_AddImm8, /*InsnID*/1, /*SubRegIndex*/11,
        GIR_ConstrainOperandRC, /*InsnID*/1, /*Op*/0, GIMT_Encode2(AMDGPU::VReg_64RegClassID),
        GIR_ConstrainOperandRC, /*InsnID*/1, /*Op*/1, GIMT_Encode2(AMDGPU::VGPR_32RegClassID),
        GIR_ConstrainOperandRC, /*InsnID*/1, /*Op*/3, GIMT_Encode2(AMDGPU::VGPR_32RegClassID),
        GIR_BuildMI, /*InsnID*/0, /*Opcode*/GIMT_Encode2(AMDGPU::BUFFER_ATOMIC_CMPSWAP_VBUFFER_BOTHEN),
        GIR_AddSimpleTempRegister, /*InsnID*/0, /*TempRegID*/0,
        GIR_AddSimpleTempRegister, /*InsnID*/0, /*TempRegID*/1,
        GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/3, // rsrc
        GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/0, // soffset
        GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/7, // offset
        GIR_CustomOperandRenderer, /*InsnID*/0, /*OldInsnID*/0, /*OpIdx*/8, /*OperandRenderer*/GIMT_Encode2(GICR_renderExtractCPol), // auxiliary
        GIR_MergeMemOperands, /*InsnID*/0, /*NumInsns*/1, /*MergeInsnID's*/0,
        GIR_ConstrainSelectedInstOperands, /*InsnID*/0,
        GIR_EraseFromParent, /*InsnID*/0,
        // GIR_Coverage, 5304,
        GIR_Done,
      // Label 5806: @422643
      GIM_Try, /*On fail goto*//*Label 5807*/ GIMT_Encode4(422825), // Rule ID 5292 //
        GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasUnrestrictedSOffset),
        GIM_CheckRegBankForClass, /*MI*/0, /*Op*/0, /*RC*/GIMT_Encode2(AMDGPU::AV_64RegClassID),
        // MIs[0] offset
        GIM_CheckIsImm, /*MI*/0, /*Op*/7,
        // MIs[0] auxiliary
        GIM_CheckIsImm, /*MI*/0, /*Op*/8,
        // MIs[0] Operand 9
        GIM_CheckIsImm, /*MI*/0, /*Op*/9,
        GIM_CheckComplexPattern, /*MI*/0, /*Op*/6, /*Renderer*/GIMT_Encode2(0), GIMT_Encode2(GICP_gi_buf_soffset),
        // (SIbuffer_atomic_cmpswap:{ *:[i32] } i32:{ *:[i32] }:$data, i32:{ *:[i32] }:$cmp, v4i32:{ *:[v4i32] }:$rsrc, i32:{ *:[i32] }:$vindex, i32:{ *:[i32] }:$voffset, (BUFSOffset:{ *:[i32] } i32:{ *:[i32] }:$soffset), (timm:{ *:[i32] }):$offset, (timm:{ *:[i32] }):$auxiliary, (timm:{ *:[i1] }))  =>  (EXTRACT_SUBREG:{ *:[i32] } (BUFFER_ATOMIC_CMPSWAP_BOTHEN_RTN:{ *:[i64] } (REG_SEQUENCE:{ *:[i64] } VReg_64:{ *:[i32] }, anonymous_15037:{ *:[i32] }:$data, sub0:{ *:[i32] }, anonymous_15037:{ *:[i32] }:$cmp, sub1:{ *:[i32] }), (REG_SEQUENCE:{ *:[i64] } VReg_64:{ *:[i32] }, VGPR_32:{ *:[i32] }:$vindex, sub0:{ *:[i32] }, VGPR_32:{ *:[i32] }:$voffset, sub1:{ *:[i32] }), SReg_128:{ *:[v4i32] }:$rsrc, SCSrc_b32:{ *:[i32] }:$soffset, (timm:{ *:[i32] }):$offset, (extract_cpol_set_glc:{ *:[i32] } ?:{ *:[i32] }:$auxiliary)), sub0:{ *:[i32] })
        GIR_MakeTempReg, /*TempRegID*/0, /*TypeID*/GILLT_s64,
        GIR_MakeTempReg, /*TempRegID*/1, /*TypeID*/GILLT_s64,
        GIR_MakeTempReg, /*TempRegID*/2, /*TypeID*/GILLT_s64,
        GIR_BuildMI, /*InsnID*/3, /*Opcode*/GIMT_Encode2(TargetOpcode::REG_SEQUENCE),
        GIR_AddTempRegister, /*InsnID*/3, /*TempRegID*/2, /*TempRegFlags*/GIMT_Encode2(RegState::Define),
        GIR_Copy, /*NewInsnID*/3, /*OldInsnID*/0, /*OpIdx*/4, // vindex
        GIR_AddImm8, /*InsnID*/3, /*SubRegIndex*/3,
        GIR_Copy, /*NewInsnID*/3, /*OldInsnID*/0, /*OpIdx*/5, // voffset
        GIR_AddImm8, /*InsnID*/3, /*SubRegIndex*/11,
        GIR_ConstrainOperandRC, /*InsnID*/3, /*Op*/0, GIMT_Encode2(AMDGPU::VReg_64RegClassID),
        GIR_ConstrainOperandRC, /*InsnID*/3, /*Op*/1, GIMT_Encode2(AMDGPU::VGPR_32RegClassID),
        GIR_ConstrainOperandRC, /*InsnID*/3, /*Op*/3, GIMT_Encode2(AMDGPU::VGPR_32RegClassID),
        GIR_BuildMI, /*InsnID*/2, /*Opcode*/GIMT_Encode2(TargetOpcode::REG_SEQUENCE),
        GIR_AddTempRegister, /*InsnID*/2, /*TempRegID*/1, /*TempRegFlags*/GIMT_Encode2(RegState::Define),
        GIR_Copy, /*NewInsnID*/2, /*OldInsnID*/0, /*OpIdx*/1, // data
        GIR_AddImm8, /*InsnID*/2, /*SubRegIndex*/3,
        GIR_Copy, /*NewInsnID*/2, /*OldInsnID*/0, /*OpIdx*/2, // cmp
        GIR_AddImm8, /*InsnID*/2, /*SubRegIndex*/11,
        GIR_ConstrainOperandRC, /*InsnID*/2, /*Op*/0, GIMT_Encode2(AMDGPU::VReg_64RegClassID),
        GIR_ConstrainOperandRC, /*InsnID*/2, /*Op*/1, GIMT_Encode2(AMDGPU::VGPR_32RegClassID),
        GIR_ConstrainOperandRC, /*InsnID*/2, /*Op*/3, GIMT_Encode2(AMDGPU::VGPR_32RegClassID),
        GIR_BuildMI, /*InsnID*/1, /*Opcode*/GIMT_Encode2(AMDGPU::BUFFER_ATOMIC_CMPSWAP_BOTHEN_RTN),
        GIR_AddTempRegister, /*InsnID*/1, /*TempRegID*/0, /*TempRegFlags*/GIMT_Encode2(RegState::Define),
        GIR_AddSimpleTempRegister, /*InsnID*/1, /*TempRegID*/1,
        GIR_AddSimpleTempRegister, /*InsnID*/1, /*TempRegID*/2,
        GIR_Copy, /*NewInsnID*/1, /*OldInsnID*/0, /*OpIdx*/3, // rsrc
        GIR_ComplexSubOperandRenderer, /*InsnID*/1, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/0, // soffset
        GIR_Copy, /*NewInsnID*/1, /*OldInsnID*/0, /*OpIdx*/7, // offset
        GIR_CustomOperandRenderer, /*InsnID*/1, /*OldInsnID*/0, /*OpIdx*/8, /*OperandRenderer*/GIMT_Encode2(GICR_renderExtractCpolSetGLC), // auxiliary
        GIR_MergeMemOperands, /*InsnID*/1, /*NumInsns*/1, /*MergeInsnID's*/0,
        GIR_ConstrainSelectedInstOperands, /*InsnID*/1,
        GIR_BuildMI, /*InsnID*/0, /*Opcode*/GIMT_Encode2(TargetOpcode::COPY),
        GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/0, // DstI[dst]
        GIR_AddTempSubRegister, /*InsnID*/0, /*TempRegID*/0, /*TempRegFlags*/GIMT_Encode2(0), GIMT_Encode2(AMDGPU::sub0),
        GIR_ConstrainOperandRC, /*InsnID*/0, /*Op*/0, GIMT_Encode2(AMDGPU::AV_32RegClassID),
        GIR_ConstrainOperandRC, /*InsnID*/0, /*Op*/1, GIMT_Encode2(AMDGPU::AV_64RegClassID),
        GIR_EraseFromParent, /*InsnID*/0,
        // GIR_Coverage, 5292,
        GIR_Done,
      // Label 5807: @422825
      GIM_Try, /*On fail goto*//*Label 5808*/ GIMT_Encode4(423004), // Rule ID 5300 //
        GIM_CheckRegBankForClass, /*MI*/0, /*Op*/0, /*RC*/GIMT_Encode2(AMDGPU::AV_64RegClassID),
        // MIs[0] offset
        GIM_CheckIsImm, /*MI*/0, /*Op*/7,
        // MIs[0] auxiliary
        GIM_CheckIsImm, /*MI*/0, /*Op*/8,
        // MIs[0] Operand 9
        GIM_CheckIsImm, /*MI*/0, /*Op*/9,
        GIM_CheckComplexPattern, /*MI*/0, /*Op*/6, /*Renderer*/GIMT_Encode2(0), GIMT_Encode2(GICP_gi_buf_soffset),
        // (SIbuffer_atomic_cmpswap:{ *:[i32] } i32:{ *:[i32] }:$data, i32:{ *:[i32] }:$cmp, v4i32:{ *:[v4i32] }:$rsrc, i32:{ *:[i32] }:$vindex, i32:{ *:[i32] }:$voffset, (BUFSOffset:{ *:[i32] } i32:{ *:[i32] }:$soffset), (timm:{ *:[i32] }):$offset, (timm:{ *:[i32] }):$auxiliary, (timm:{ *:[i1] }))  =>  (EXTRACT_SUBREG:{ *:[i32] } (BUFFER_ATOMIC_CMPSWAP_VBUFFER_BOTHEN_RTN:{ *:[i64] } (REG_SEQUENCE:{ *:[i64] } VReg_64:{ *:[i32] }, anonymous_15037:{ *:[i32] }:$data, sub0:{ *:[i32] }, anonymous_15037:{ *:[i32] }:$cmp, sub1:{ *:[i32] }), (REG_SEQUENCE:{ *:[i64] } VReg_64:{ *:[i32] }, VGPR_32:{ *:[i32] }:$vindex, sub0:{ *:[i32] }, VGPR_32:{ *:[i32] }:$voffset, sub1:{ *:[i32] }), SReg_128:{ *:[v4i32] }:$rsrc, SCSrc_b32:{ *:[i32] }:$soffset, (timm:{ *:[i32] }):$offset, (extract_cpol_set_glc:{ *:[i32] } ?:{ *:[i32] }:$auxiliary)), sub0:{ *:[i32] })
        GIR_MakeTempReg, /*TempRegID*/0, /*TypeID*/GILLT_s64,
        GIR_MakeTempReg, /*TempRegID*/1, /*TypeID*/GILLT_s64,
        GIR_MakeTempReg, /*TempRegID*/2, /*TypeID*/GILLT_s64,
        GIR_BuildMI, /*InsnID*/3, /*Opcode*/GIMT_Encode2(TargetOpcode::REG_SEQUENCE),
        GIR_AddTempRegister, /*InsnID*/3, /*TempRegID*/2, /*TempRegFlags*/GIMT_Encode2(RegState::Define),
        GIR_Copy, /*NewInsnID*/3, /*OldInsnID*/0, /*OpIdx*/4, // vindex
        GIR_AddImm8, /*InsnID*/3, /*SubRegIndex*/3,
        GIR_Copy, /*NewInsnID*/3, /*OldInsnID*/0, /*OpIdx*/5, // voffset
        GIR_AddImm8, /*InsnID*/3, /*SubRegIndex*/11,
        GIR_ConstrainOperandRC, /*InsnID*/3, /*Op*/0, GIMT_Encode2(AMDGPU::VReg_64RegClassID),
        GIR_ConstrainOperandRC, /*InsnID*/3, /*Op*/1, GIMT_Encode2(AMDGPU::VGPR_32RegClassID),
        GIR_ConstrainOperandRC, /*InsnID*/3, /*Op*/3, GIMT_Encode2(AMDGPU::VGPR_32RegClassID),
        GIR_BuildMI, /*InsnID*/2, /*Opcode*/GIMT_Encode2(TargetOpcode::REG_SEQUENCE),
        GIR_AddTempRegister, /*InsnID*/2, /*TempRegID*/1, /*TempRegFlags*/GIMT_Encode2(RegState::Define),
        GIR_Copy, /*NewInsnID*/2, /*OldInsnID*/0, /*OpIdx*/1, // data
        GIR_AddImm8, /*InsnID*/2, /*SubRegIndex*/3,
        GIR_Copy, /*NewInsnID*/2, /*OldInsnID*/0, /*OpIdx*/2, // cmp
        GIR_AddImm8, /*InsnID*/2, /*SubRegIndex*/11,
        GIR_ConstrainOperandRC, /*InsnID*/2, /*Op*/0, GIMT_Encode2(AMDGPU::VReg_64RegClassID),
        GIR_ConstrainOperandRC, /*InsnID*/2, /*Op*/1, GIMT_Encode2(AMDGPU::VGPR_32RegClassID),
        GIR_ConstrainOperandRC, /*InsnID*/2, /*Op*/3, GIMT_Encode2(AMDGPU::VGPR_32RegClassID),
        GIR_BuildMI, /*InsnID*/1, /*Opcode*/GIMT_Encode2(AMDGPU::BUFFER_ATOMIC_CMPSWAP_VBUFFER_BOTHEN_RTN),
        GIR_AddTempRegister, /*InsnID*/1, /*TempRegID*/0, /*TempRegFlags*/GIMT_Encode2(RegState::Define),
        GIR_AddSimpleTempRegister, /*InsnID*/1, /*TempRegID*/1,
        GIR_AddSimpleTempRegister, /*InsnID*/1, /*TempRegID*/2,
        GIR_Copy, /*NewInsnID*/1, /*OldInsnID*/0, /*OpIdx*/3, // rsrc
        GIR_ComplexSubOperandRenderer, /*InsnID*/1, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/0, // soffset
        GIR_Copy, /*NewInsnID*/1, /*OldInsnID*/0, /*OpIdx*/7, // offset
        GIR_CustomOperandRenderer, /*InsnID*/1, /*OldInsnID*/0, /*OpIdx*/8, /*OperandRenderer*/GIMT_Encode2(GICR_renderExtractCpolSetGLC), // auxiliary
        GIR_MergeMemOperands, /*InsnID*/1, /*NumInsns*/1, /*MergeInsnID's*/0,
        GIR_ConstrainSelectedInstOperands, /*InsnID*/1,
        GIR_BuildMI, /*InsnID*/0, /*Opcode*/GIMT_Encode2(TargetOpcode::COPY),
        GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/0, // DstI[dst]
        GIR_AddTempSubRegister, /*InsnID*/0, /*TempRegID*/0, /*TempRegFlags*/GIMT_Encode2(0), GIMT_Encode2(AMDGPU::sub0),
        GIR_ConstrainOperandRC, /*InsnID*/0, /*Op*/0, GIMT_Encode2(AMDGPU::AV_32RegClassID),
        GIR_ConstrainOperandRC, /*InsnID*/0, /*Op*/1, GIMT_Encode2(AMDGPU::AV_64RegClassID),
        GIR_EraseFromParent, /*InsnID*/0,
        // GIR_Coverage, 5300,
        GIR_Done,
      // Label 5808: @423004
      GIM_Reject,
    // Label 5792: @423005
    GIM_Reject,
    // Label 5790: @423006
    GIM_Try, /*On fail goto*//*Label 5809*/ GIMT_Encode4(425268),
      GIM_CheckType, /*MI*/0, /*Op*/1, /*Type*/GILLT_s64,
      GIM_CheckType, /*MI*/0, /*Op*/2, /*Type*/GILLT_s64,
      GIM_CheckType, /*MI*/0, /*Op*/3, /*Type*/GILLT_v4s32,
      GIM_CheckType, /*MI*/0, /*Op*/4, /*Type*/GILLT_s32,
      GIM_CheckType, /*MI*/0, /*Op*/5, /*Type*/GILLT_s32,
      GIM_CheckType, /*MI*/0, /*Op*/6, /*Type*/GILLT_s32,
      GIM_Try, /*On fail goto*//*Label 5810*/ GIMT_Encode4(423153), // Rule ID 5309 //
        GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasUnrestrictedSOffset),
        GIM_CheckHasNoUse, /*MI*/0,
        GIM_CheckConstantInt8, /*MI*/0, /*Op*/4, 0,
        GIM_CheckConstantInt8, /*MI*/0, /*Op*/5, 0,
        // MIs[0] offset
        GIM_CheckIsImm, /*MI*/0, /*Op*/7,
        // MIs[0] auxiliary
        GIM_CheckIsImm, /*MI*/0, /*Op*/8,
        // MIs[0] Operand 9
        GIM_CheckLiteralInt, /*MI*/0, /*Op*/9, GIMT_Encode8(0),
        GIM_CheckComplexPattern, /*MI*/0, /*Op*/6, /*Renderer*/GIMT_Encode2(0), GIMT_Encode2(GICP_gi_buf_soffset),
        // (SIbuffer_atomic_cmpswap:{ *:[i64] } i64:{ *:[i64] }:$data, i64:{ *:[i64] }:$cmp, v4i32:{ *:[v4i32] }:$rsrc, 0:{ *:[i32] }, 0:{ *:[i32] }, (BUFSOffset:{ *:[i32] } i32:{ *:[i32] }:$soffset), (timm:{ *:[i32] }):$offset, (timm:{ *:[i32] }):$auxiliary, 0:{ *:[i1] })<<P:Predicate_SIbuffer_atomic_cmpswap_noret>>  =>  (BUFFER_ATOMIC_CMPSWAP_X2_OFFSET (REG_SEQUENCE:{ *:[v8i16] } VReg_128:{ *:[i32] }, anonymous_15036:{ *:[i64] }:$data, sub0_sub1:{ *:[i32] }, anonymous_15036:{ *:[i64] }:$cmp, sub2_sub3:{ *:[i32] }), SReg_128:{ *:[v4i32] }:$rsrc, SCSrc_b32:{ *:[i32] }:$soffset, (timm:{ *:[i32] }):$offset, (extract_cpol:{ *:[i32] } ?:{ *:[i32] }:$auxiliary))
        GIR_MakeTempReg, /*TempRegID*/0, /*TypeID*/GILLT_v8s16,
        GIR_BuildMI, /*InsnID*/1, /*Opcode*/GIMT_Encode2(TargetOpcode::REG_SEQUENCE),
        GIR_AddTempRegister, /*InsnID*/1, /*TempRegID*/0, /*TempRegFlags*/GIMT_Encode2(RegState::Define),
        GIR_Copy, /*NewInsnID*/1, /*OldInsnID*/0, /*OpIdx*/1, // data
        GIR_AddImm8, /*InsnID*/1, /*SubRegIndex*/4,
        GIR_Copy, /*NewInsnID*/1, /*OldInsnID*/0, /*OpIdx*/2, // cmp
        GIR_AddImm8, /*InsnID*/1, /*SubRegIndex*/24,
        GIR_ConstrainOperandRC, /*InsnID*/1, /*Op*/0, GIMT_Encode2(AMDGPU::VReg_128RegClassID),
        GIR_ConstrainOperandRC, /*InsnID*/1, /*Op*/1, GIMT_Encode2(AMDGPU::VReg_64RegClassID),
        GIR_ConstrainOperandRC, /*InsnID*/1, /*Op*/3, GIMT_Encode2(AMDGPU::VReg_64RegClassID),
        GIR_BuildMI, /*InsnID*/0, /*Opcode*/GIMT_Encode2(AMDGPU::BUFFER_ATOMIC_CMPSWAP_X2_OFFSET),
        GIR_AddSimpleTempRegister, /*InsnID*/0, /*TempRegID*/0,
        GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/3, // rsrc
        GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/0, // soffset
        GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/7, // offset
        GIR_CustomOperandRenderer, /*InsnID*/0, /*OldInsnID*/0, /*OpIdx*/8, /*OperandRenderer*/GIMT_Encode2(GICR_renderExtractCPol), // auxiliary
        GIR_MergeMemOperands, /*InsnID*/0, /*NumInsns*/1, /*MergeInsnID's*/0,
        GIR_ConstrainSelectedInstOperands, /*InsnID*/0,
        GIR_EraseFromParent, /*InsnID*/0,
        // GIR_Coverage, 5309,
        GIR_Done,
      // Label 5810: @423153
      GIM_Try, /*On fail goto*//*Label 5811*/ GIMT_Encode4(423268), // Rule ID 5317 //
        GIM_CheckHasNoUse, /*MI*/0,
        GIM_CheckConstantInt8, /*MI*/0, /*Op*/4, 0,
        GIM_CheckConstantInt8, /*MI*/0, /*Op*/5, 0,
        // MIs[0] offset
        GIM_CheckIsImm, /*MI*/0, /*Op*/7,
        // MIs[0] auxiliary
        GIM_CheckIsImm, /*MI*/0, /*Op*/8,
        // MIs[0] Operand 9
        GIM_CheckLiteralInt, /*MI*/0, /*Op*/9, GIMT_Encode8(0),
        GIM_CheckComplexPattern, /*MI*/0, /*Op*/6, /*Renderer*/GIMT_Encode2(0), GIMT_Encode2(GICP_gi_buf_soffset),
        // (SIbuffer_atomic_cmpswap:{ *:[i64] } i64:{ *:[i64] }:$data, i64:{ *:[i64] }:$cmp, v4i32:{ *:[v4i32] }:$rsrc, 0:{ *:[i32] }, 0:{ *:[i32] }, (BUFSOffset:{ *:[i32] } i32:{ *:[i32] }:$soffset), (timm:{ *:[i32] }):$offset, (timm:{ *:[i32] }):$auxiliary, 0:{ *:[i1] })<<P:Predicate_SIbuffer_atomic_cmpswap_noret>>  =>  (BUFFER_ATOMIC_CMPSWAP_X2_VBUFFER_OFFSET (REG_SEQUENCE:{ *:[v8i16] } VReg_128:{ *:[i32] }, anonymous_15036:{ *:[i64] }:$data, sub0_sub1:{ *:[i32] }, anonymous_15036:{ *:[i64] }:$cmp, sub2_sub3:{ *:[i32] }), SReg_128:{ *:[v4i32] }:$rsrc, SCSrc_b32:{ *:[i32] }:$soffset, (timm:{ *:[i32] }):$offset, (extract_cpol:{ *:[i32] } ?:{ *:[i32] }:$auxiliary))
        GIR_MakeTempReg, /*TempRegID*/0, /*TypeID*/GILLT_v8s16,
        GIR_BuildMI, /*InsnID*/1, /*Opcode*/GIMT_Encode2(TargetOpcode::REG_SEQUENCE),
        GIR_AddTempRegister, /*InsnID*/1, /*TempRegID*/0, /*TempRegFlags*/GIMT_Encode2(RegState::Define),
        GIR_Copy, /*NewInsnID*/1, /*OldInsnID*/0, /*OpIdx*/1, // data
        GIR_AddImm8, /*InsnID*/1, /*SubRegIndex*/4,
        GIR_Copy, /*NewInsnID*/1, /*OldInsnID*/0, /*OpIdx*/2, // cmp
        GIR_AddImm8, /*InsnID*/1, /*SubRegIndex*/24,
        GIR_ConstrainOperandRC, /*InsnID*/1, /*Op*/0, GIMT_Encode2(AMDGPU::VReg_128RegClassID),
        GIR_ConstrainOperandRC, /*InsnID*/1, /*Op*/1, GIMT_Encode2(AMDGPU::VReg_64RegClassID),
        GIR_ConstrainOperandRC, /*InsnID*/1, /*Op*/3, GIMT_Encode2(AMDGPU::VReg_64RegClassID),
        GIR_BuildMI, /*InsnID*/0, /*Opcode*/GIMT_Encode2(AMDGPU::BUFFER_ATOMIC_CMPSWAP_X2_VBUFFER_OFFSET),
        GIR_AddSimpleTempRegister, /*InsnID*/0, /*TempRegID*/0,
        GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/3, // rsrc
        GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/0, // soffset
        GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/7, // offset
        GIR_CustomOperandRenderer, /*InsnID*/0, /*OldInsnID*/0, /*OpIdx*/8, /*OperandRenderer*/GIMT_Encode2(GICR_renderExtractCPol), // auxiliary
        GIR_MergeMemOperands, /*InsnID*/0, /*NumInsns*/1, /*MergeInsnID's*/0,
        GIR_ConstrainSelectedInstOperands, /*InsnID*/0,
        GIR_EraseFromParent, /*InsnID*/0,
        // GIR_Coverage, 5317,
        GIR_Done,
      // Label 5811: @423268
      GIM_Try, /*On fail goto*//*Label 5812*/ GIMT_Encode4(423422), // Rule ID 5305 //
        GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasUnrestrictedSOffset),
        GIM_CheckRegBankForClass, /*MI*/0, /*Op*/0, /*RC*/GIMT_Encode2(AMDGPU::AV_128RegClassID),
        GIM_CheckConstantInt8, /*MI*/0, /*Op*/4, 0,
        GIM_CheckConstantInt8, /*MI*/0, /*Op*/5, 0,
        // MIs[0] offset
        GIM_CheckIsImm, /*MI*/0, /*Op*/7,
        // MIs[0] auxiliary
        GIM_CheckIsImm, /*MI*/0, /*Op*/8,
        // MIs[0] Operand 9
        GIM_CheckLiteralInt, /*MI*/0, /*Op*/9, GIMT_Encode8(0),
        GIM_CheckComplexPattern, /*MI*/0, /*Op*/6, /*Renderer*/GIMT_Encode2(0), GIMT_Encode2(GICP_gi_buf_soffset),
        // (SIbuffer_atomic_cmpswap:{ *:[i64] } i64:{ *:[i64] }:$data, i64:{ *:[i64] }:$cmp, v4i32:{ *:[v4i32] }:$rsrc, 0:{ *:[i32] }, 0:{ *:[i32] }, (BUFSOffset:{ *:[i32] } i32:{ *:[i32] }:$soffset), (timm:{ *:[i32] }):$offset, (timm:{ *:[i32] }):$auxiliary, 0:{ *:[i1] })  =>  (EXTRACT_SUBREG:{ *:[i64] } (BUFFER_ATOMIC_CMPSWAP_X2_OFFSET_RTN:{ *:[v8i16] } (REG_SEQUENCE:{ *:[v8i16] } VReg_128:{ *:[i32] }, anonymous_15036:{ *:[i64] }:$data, sub0_sub1:{ *:[i32] }, anonymous_15036:{ *:[i64] }:$cmp, sub2_sub3:{ *:[i32] }), SReg_128:{ *:[v4i32] }:$rsrc, SCSrc_b32:{ *:[i32] }:$soffset, (timm:{ *:[i32] }):$offset, (extract_cpol_set_glc:{ *:[i32] } ?:{ *:[i32] }:$auxiliary)), sub0_sub1:{ *:[i32] })
        GIR_MakeTempReg, /*TempRegID*/0, /*TypeID*/GILLT_v8s16,
        GIR_MakeTempReg, /*TempRegID*/1, /*TypeID*/GILLT_v8s16,
        GIR_BuildMI, /*InsnID*/2, /*Opcode*/GIMT_Encode2(TargetOpcode::REG_SEQUENCE),
        GIR_AddTempRegister, /*InsnID*/2, /*TempRegID*/1, /*TempRegFlags*/GIMT_Encode2(RegState::Define),
        GIR_Copy, /*NewInsnID*/2, /*OldInsnID*/0, /*OpIdx*/1, // data
        GIR_AddImm8, /*InsnID*/2, /*SubRegIndex*/4,
        GIR_Copy, /*NewInsnID*/2, /*OldInsnID*/0, /*OpIdx*/2, // cmp
        GIR_AddImm8, /*InsnID*/2, /*SubRegIndex*/24,
        GIR_ConstrainOperandRC, /*InsnID*/2, /*Op*/0, GIMT_Encode2(AMDGPU::VReg_128RegClassID),
        GIR_ConstrainOperandRC, /*InsnID*/2, /*Op*/1, GIMT_Encode2(AMDGPU::VReg_64RegClassID),
        GIR_ConstrainOperandRC, /*InsnID*/2, /*Op*/3, GIMT_Encode2(AMDGPU::VReg_64RegClassID),
        GIR_BuildMI, /*InsnID*/1, /*Opcode*/GIMT_Encode2(AMDGPU::BUFFER_ATOMIC_CMPSWAP_X2_OFFSET_RTN),
        GIR_AddTempRegister, /*InsnID*/1, /*TempRegID*/0, /*TempRegFlags*/GIMT_Encode2(RegState::Define),
        GIR_AddSimpleTempRegister, /*InsnID*/1, /*TempRegID*/1,
        GIR_Copy, /*NewInsnID*/1, /*OldInsnID*/0, /*OpIdx*/3, // rsrc
        GIR_ComplexSubOperandRenderer, /*InsnID*/1, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/0, // soffset
        GIR_Copy, /*NewInsnID*/1, /*OldInsnID*/0, /*OpIdx*/7, // offset
        GIR_CustomOperandRenderer, /*InsnID*/1, /*OldInsnID*/0, /*OpIdx*/8, /*OperandRenderer*/GIMT_Encode2(GICR_renderExtractCpolSetGLC), // auxiliary
        GIR_MergeMemOperands, /*InsnID*/1, /*NumInsns*/1, /*MergeInsnID's*/0,
        GIR_ConstrainSelectedInstOperands, /*InsnID*/1,
        GIR_BuildMI, /*InsnID*/0, /*Opcode*/GIMT_Encode2(TargetOpcode::COPY),
        GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/0, // DstI[dst]
        GIR_AddTempSubRegister, /*InsnID*/0, /*TempRegID*/0, /*TempRegFlags*/GIMT_Encode2(0), GIMT_Encode2(AMDGPU::sub0_sub1),
        GIR_ConstrainOperandRC, /*InsnID*/0, /*Op*/0, GIMT_Encode2(AMDGPU::AV_64RegClassID),
        GIR_ConstrainOperandRC, /*InsnID*/0, /*Op*/1, GIMT_Encode2(AMDGPU::AV_128RegClassID),
        GIR_EraseFromParent, /*InsnID*/0,
        // GIR_Coverage, 5305,
        GIR_Done,
      // Label 5812: @423422
      GIM_Try, /*On fail goto*//*Label 5813*/ GIMT_Encode4(423573), // Rule ID 5313 //
        GIM_CheckRegBankForClass, /*MI*/0, /*Op*/0, /*RC*/GIMT_Encode2(AMDGPU::AV_128RegClassID),
        GIM_CheckConstantInt8, /*MI*/0, /*Op*/4, 0,
        GIM_CheckConstantInt8, /*MI*/0, /*Op*/5, 0,
        // MIs[0] offset
        GIM_CheckIsImm, /*MI*/0, /*Op*/7,
        // MIs[0] auxiliary
        GIM_CheckIsImm, /*MI*/0, /*Op*/8,
        // MIs[0] Operand 9
        GIM_CheckLiteralInt, /*MI*/0, /*Op*/9, GIMT_Encode8(0),
        GIM_CheckComplexPattern, /*MI*/0, /*Op*/6, /*Renderer*/GIMT_Encode2(0), GIMT_Encode2(GICP_gi_buf_soffset),
        // (SIbuffer_atomic_cmpswap:{ *:[i64] } i64:{ *:[i64] }:$data, i64:{ *:[i64] }:$cmp, v4i32:{ *:[v4i32] }:$rsrc, 0:{ *:[i32] }, 0:{ *:[i32] }, (BUFSOffset:{ *:[i32] } i32:{ *:[i32] }:$soffset), (timm:{ *:[i32] }):$offset, (timm:{ *:[i32] }):$auxiliary, 0:{ *:[i1] })  =>  (EXTRACT_SUBREG:{ *:[i64] } (BUFFER_ATOMIC_CMPSWAP_X2_VBUFFER_OFFSET_RTN:{ *:[v8i16] } (REG_SEQUENCE:{ *:[v8i16] } VReg_128:{ *:[i32] }, anonymous_15036:{ *:[i64] }:$data, sub0_sub1:{ *:[i32] }, anonymous_15036:{ *:[i64] }:$cmp, sub2_sub3:{ *:[i32] }), SReg_128:{ *:[v4i32] }:$rsrc, SCSrc_b32:{ *:[i32] }:$soffset, (timm:{ *:[i32] }):$offset, (extract_cpol_set_glc:{ *:[i32] } ?:{ *:[i32] }:$auxiliary)), sub0_sub1:{ *:[i32] })
        GIR_MakeTempReg, /*TempRegID*/0, /*TypeID*/GILLT_v8s16,
        GIR_MakeTempReg, /*TempRegID*/1, /*TypeID*/GILLT_v8s16,
        GIR_BuildMI, /*InsnID*/2, /*Opcode*/GIMT_Encode2(TargetOpcode::REG_SEQUENCE),
        GIR_AddTempRegister, /*InsnID*/2, /*TempRegID*/1, /*TempRegFlags*/GIMT_Encode2(RegState::Define),
        GIR_Copy, /*NewInsnID*/2, /*OldInsnID*/0, /*OpIdx*/1, // data
        GIR_AddImm8, /*InsnID*/2, /*SubRegIndex*/4,
        GIR_Copy, /*NewInsnID*/2, /*OldInsnID*/0, /*OpIdx*/2, // cmp
        GIR_AddImm8, /*InsnID*/2, /*SubRegIndex*/24,
        GIR_ConstrainOperandRC, /*InsnID*/2, /*Op*/0, GIMT_Encode2(AMDGPU::VReg_128RegClassID),
        GIR_ConstrainOperandRC, /*InsnID*/2, /*Op*/1, GIMT_Encode2(AMDGPU::VReg_64RegClassID),
        GIR_ConstrainOperandRC, /*InsnID*/2, /*Op*/3, GIMT_Encode2(AMDGPU::VReg_64RegClassID),
        GIR_BuildMI, /*InsnID*/1, /*Opcode*/GIMT_Encode2(AMDGPU::BUFFER_ATOMIC_CMPSWAP_X2_VBUFFER_OFFSET_RTN),
        GIR_AddTempRegister, /*InsnID*/1, /*TempRegID*/0, /*TempRegFlags*/GIMT_Encode2(RegState::Define),
        GIR_AddSimpleTempRegister, /*InsnID*/1, /*TempRegID*/1,
        GIR_Copy, /*NewInsnID*/1, /*OldInsnID*/0, /*OpIdx*/3, // rsrc
        GIR_ComplexSubOperandRenderer, /*InsnID*/1, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/0, // soffset
        GIR_Copy, /*NewInsnID*/1, /*OldInsnID*/0, /*OpIdx*/7, // offset
        GIR_CustomOperandRenderer, /*InsnID*/1, /*OldInsnID*/0, /*OpIdx*/8, /*OperandRenderer*/GIMT_Encode2(GICR_renderExtractCpolSetGLC), // auxiliary
        GIR_MergeMemOperands, /*InsnID*/1, /*NumInsns*/1, /*MergeInsnID's*/0,
        GIR_ConstrainSelectedInstOperands, /*InsnID*/1,
        GIR_BuildMI, /*InsnID*/0, /*Opcode*/GIMT_Encode2(TargetOpcode::COPY),
        GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/0, // DstI[dst]
        GIR_AddTempSubRegister, /*InsnID*/0, /*TempRegID*/0, /*TempRegFlags*/GIMT_Encode2(0), GIMT_Encode2(AMDGPU::sub0_sub1),
        GIR_ConstrainOperandRC, /*InsnID*/0, /*Op*/0, GIMT_Encode2(AMDGPU::AV_64RegClassID),
        GIR_ConstrainOperandRC, /*InsnID*/0, /*Op*/1, GIMT_Encode2(AMDGPU::AV_128RegClassID),
        GIR_EraseFromParent, /*InsnID*/0,
        // GIR_Coverage, 5313,
        GIR_Done,
      // Label 5813: @423573
      GIM_Try, /*On fail goto*//*Label 5814*/ GIMT_Encode4(423691), // Rule ID 5311 //
        GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasUnrestrictedSOffset),
        GIM_CheckHasNoUse, /*MI*/0,
        GIM_CheckConstantInt8, /*MI*/0, /*Op*/4, 0,
        // MIs[0] offset
        GIM_CheckIsImm, /*MI*/0, /*Op*/7,
        // MIs[0] auxiliary
        GIM_CheckIsImm, /*MI*/0, /*Op*/8,
        // MIs[0] Operand 9
        GIM_CheckLiteralInt, /*MI*/0, /*Op*/9, GIMT_Encode8(0),
        GIM_CheckComplexPattern, /*MI*/0, /*Op*/6, /*Renderer*/GIMT_Encode2(0), GIMT_Encode2(GICP_gi_buf_soffset),
        // (SIbuffer_atomic_cmpswap:{ *:[i64] } i64:{ *:[i64] }:$data, i64:{ *:[i64] }:$cmp, v4i32:{ *:[v4i32] }:$rsrc, 0:{ *:[i32] }, i32:{ *:[i32] }:$voffset, (BUFSOffset:{ *:[i32] } i32:{ *:[i32] }:$soffset), (timm:{ *:[i32] }):$offset, (timm:{ *:[i32] }):$auxiliary, 0:{ *:[i1] })<<P:Predicate_SIbuffer_atomic_cmpswap_noret>>  =>  (BUFFER_ATOMIC_CMPSWAP_X2_OFFEN (REG_SEQUENCE:{ *:[v8i16] } VReg_128:{ *:[i32] }, anonymous_15036:{ *:[i64] }:$data, sub0_sub1:{ *:[i32] }, anonymous_15036:{ *:[i64] }:$cmp, sub2_sub3:{ *:[i32] }), VGPR_32:{ *:[i32] }:$voffset, SReg_128:{ *:[v4i32] }:$rsrc, SCSrc_b32:{ *:[i32] }:$soffset, (timm:{ *:[i32] }):$offset, (extract_cpol:{ *:[i32] } ?:{ *:[i32] }:$auxiliary))
        GIR_MakeTempReg, /*TempRegID*/0, /*TypeID*/GILLT_v8s16,
        GIR_BuildMI, /*InsnID*/1, /*Opcode*/GIMT_Encode2(TargetOpcode::REG_SEQUENCE),
        GIR_AddTempRegister, /*InsnID*/1, /*TempRegID*/0, /*TempRegFlags*/GIMT_Encode2(RegState::Define),
        GIR_Copy, /*NewInsnID*/1, /*OldInsnID*/0, /*OpIdx*/1, // data
        GIR_AddImm8, /*InsnID*/1, /*SubRegIndex*/4,
        GIR_Copy, /*NewInsnID*/1, /*OldInsnID*/0, /*OpIdx*/2, // cmp
        GIR_AddImm8, /*InsnID*/1, /*SubRegIndex*/24,
        GIR_ConstrainOperandRC, /*InsnID*/1, /*Op*/0, GIMT_Encode2(AMDGPU::VReg_128RegClassID),
        GIR_ConstrainOperandRC, /*InsnID*/1, /*Op*/1, GIMT_Encode2(AMDGPU::VReg_64RegClassID),
        GIR_ConstrainOperandRC, /*InsnID*/1, /*Op*/3, GIMT_Encode2(AMDGPU::VReg_64RegClassID),
        GIR_BuildMI, /*InsnID*/0, /*Opcode*/GIMT_Encode2(AMDGPU::BUFFER_ATOMIC_CMPSWAP_X2_OFFEN),
        GIR_AddSimpleTempRegister, /*InsnID*/0, /*TempRegID*/0,
        GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/5, // voffset
        GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/3, // rsrc
        GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/0, // soffset
        GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/7, // offset
        GIR_CustomOperandRenderer, /*InsnID*/0, /*OldInsnID*/0, /*OpIdx*/8, /*OperandRenderer*/GIMT_Encode2(GICR_renderExtractCPol), // auxiliary
        GIR_MergeMemOperands, /*InsnID*/0, /*NumInsns*/1, /*MergeInsnID's*/0,
        GIR_ConstrainSelectedInstOperands, /*InsnID*/0,
        GIR_EraseFromParent, /*InsnID*/0,
        // GIR_Coverage, 5311,
        GIR_Done,
      // Label 5814: @423691
      GIM_Try, /*On fail goto*//*Label 5815*/ GIMT_Encode4(423806), // Rule ID 5319 //
        GIM_CheckHasNoUse, /*MI*/0,
        GIM_CheckConstantInt8, /*MI*/0, /*Op*/4, 0,
        // MIs[0] offset
        GIM_CheckIsImm, /*MI*/0, /*Op*/7,
        // MIs[0] auxiliary
        GIM_CheckIsImm, /*MI*/0, /*Op*/8,
        // MIs[0] Operand 9
        GIM_CheckLiteralInt, /*MI*/0, /*Op*/9, GIMT_Encode8(0),
        GIM_CheckComplexPattern, /*MI*/0, /*Op*/6, /*Renderer*/GIMT_Encode2(0), GIMT_Encode2(GICP_gi_buf_soffset),
        // (SIbuffer_atomic_cmpswap:{ *:[i64] } i64:{ *:[i64] }:$data, i64:{ *:[i64] }:$cmp, v4i32:{ *:[v4i32] }:$rsrc, 0:{ *:[i32] }, i32:{ *:[i32] }:$voffset, (BUFSOffset:{ *:[i32] } i32:{ *:[i32] }:$soffset), (timm:{ *:[i32] }):$offset, (timm:{ *:[i32] }):$auxiliary, 0:{ *:[i1] })<<P:Predicate_SIbuffer_atomic_cmpswap_noret>>  =>  (BUFFER_ATOMIC_CMPSWAP_X2_VBUFFER_OFFEN (REG_SEQUENCE:{ *:[v8i16] } VReg_128:{ *:[i32] }, anonymous_15036:{ *:[i64] }:$data, sub0_sub1:{ *:[i32] }, anonymous_15036:{ *:[i64] }:$cmp, sub2_sub3:{ *:[i32] }), VGPR_32:{ *:[i32] }:$voffset, SReg_128:{ *:[v4i32] }:$rsrc, SCSrc_b32:{ *:[i32] }:$soffset, (timm:{ *:[i32] }):$offset, (extract_cpol:{ *:[i32] } ?:{ *:[i32] }:$auxiliary))
        GIR_MakeTempReg, /*TempRegID*/0, /*TypeID*/GILLT_v8s16,
        GIR_BuildMI, /*InsnID*/1, /*Opcode*/GIMT_Encode2(TargetOpcode::REG_SEQUENCE),
        GIR_AddTempRegister, /*InsnID*/1, /*TempRegID*/0, /*TempRegFlags*/GIMT_Encode2(RegState::Define),
        GIR_Copy, /*NewInsnID*/1, /*OldInsnID*/0, /*OpIdx*/1, // data
        GIR_AddImm8, /*InsnID*/1, /*SubRegIndex*/4,
        GIR_Copy, /*NewInsnID*/1, /*OldInsnID*/0, /*OpIdx*/2, // cmp
        GIR_AddImm8, /*InsnID*/1, /*SubRegIndex*/24,
        GIR_ConstrainOperandRC, /*InsnID*/1, /*Op*/0, GIMT_Encode2(AMDGPU::VReg_128RegClassID),
        GIR_ConstrainOperandRC, /*InsnID*/1, /*Op*/1, GIMT_Encode2(AMDGPU::VReg_64RegClassID),
        GIR_ConstrainOperandRC, /*InsnID*/1, /*Op*/3, GIMT_Encode2(AMDGPU::VReg_64RegClassID),
        GIR_BuildMI, /*InsnID*/0, /*Opcode*/GIMT_Encode2(AMDGPU::BUFFER_ATOMIC_CMPSWAP_X2_VBUFFER_OFFEN),
        GIR_AddSimpleTempRegister, /*InsnID*/0, /*TempRegID*/0,
        GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/5, // voffset
        GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/3, // rsrc
        GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/0, // soffset
        GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/7, // offset
        GIR_CustomOperandRenderer, /*InsnID*/0, /*OldInsnID*/0, /*OpIdx*/8, /*OperandRenderer*/GIMT_Encode2(GICR_renderExtractCPol), // auxiliary
        GIR_MergeMemOperands, /*InsnID*/0, /*NumInsns*/1, /*MergeInsnID's*/0,
        GIR_ConstrainSelectedInstOperands, /*InsnID*/0,
        GIR_EraseFromParent, /*InsnID*/0,
        // GIR_Coverage, 5319,
        GIR_Done,
      // Label 5815: @423806
      GIM_Try, /*On fail goto*//*Label 5816*/ GIMT_Encode4(423960), // Rule ID 5307 //
        GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasUnrestrictedSOffset),
        GIM_CheckRegBankForClass, /*MI*/0, /*Op*/0, /*RC*/GIMT_Encode2(AMDGPU::AV_128RegClassID),
        GIM_CheckConstantInt8, /*MI*/0, /*Op*/4, 0,
        // MIs[0] offset
        GIM_CheckIsImm, /*MI*/0, /*Op*/7,
        // MIs[0] auxiliary
        GIM_CheckIsImm, /*MI*/0, /*Op*/8,
        // MIs[0] Operand 9
        GIM_CheckLiteralInt, /*MI*/0, /*Op*/9, GIMT_Encode8(0),
        GIM_CheckComplexPattern, /*MI*/0, /*Op*/6, /*Renderer*/GIMT_Encode2(0), GIMT_Encode2(GICP_gi_buf_soffset),
        // (SIbuffer_atomic_cmpswap:{ *:[i64] } i64:{ *:[i64] }:$data, i64:{ *:[i64] }:$cmp, v4i32:{ *:[v4i32] }:$rsrc, 0:{ *:[i32] }, i32:{ *:[i32] }:$voffset, (BUFSOffset:{ *:[i32] } i32:{ *:[i32] }:$soffset), (timm:{ *:[i32] }):$offset, (timm:{ *:[i32] }):$auxiliary, 0:{ *:[i1] })  =>  (EXTRACT_SUBREG:{ *:[i64] } (BUFFER_ATOMIC_CMPSWAP_X2_OFFEN_RTN:{ *:[v8i16] } (REG_SEQUENCE:{ *:[v8i16] } VReg_128:{ *:[i32] }, anonymous_15036:{ *:[i64] }:$data, sub0_sub1:{ *:[i32] }, anonymous_15036:{ *:[i64] }:$cmp, sub2_sub3:{ *:[i32] }), VGPR_32:{ *:[i32] }:$voffset, SReg_128:{ *:[v4i32] }:$rsrc, SCSrc_b32:{ *:[i32] }:$soffset, (timm:{ *:[i32] }):$offset, (extract_cpol_set_glc:{ *:[i32] } ?:{ *:[i32] }:$auxiliary)), sub0_sub1:{ *:[i32] })
        GIR_MakeTempReg, /*TempRegID*/0, /*TypeID*/GILLT_v8s16,
        GIR_MakeTempReg, /*TempRegID*/1, /*TypeID*/GILLT_v8s16,
        GIR_BuildMI, /*InsnID*/2, /*Opcode*/GIMT_Encode2(TargetOpcode::REG_SEQUENCE),
        GIR_AddTempRegister, /*InsnID*/2, /*TempRegID*/1, /*TempRegFlags*/GIMT_Encode2(RegState::Define),
        GIR_Copy, /*NewInsnID*/2, /*OldInsnID*/0, /*OpIdx*/1, // data
        GIR_AddImm8, /*InsnID*/2, /*SubRegIndex*/4,
        GIR_Copy, /*NewInsnID*/2, /*OldInsnID*/0, /*OpIdx*/2, // cmp
        GIR_AddImm8, /*InsnID*/2, /*SubRegIndex*/24,
        GIR_ConstrainOperandRC, /*InsnID*/2, /*Op*/0, GIMT_Encode2(AMDGPU::VReg_128RegClassID),
        GIR_ConstrainOperandRC, /*InsnID*/2, /*Op*/1, GIMT_Encode2(AMDGPU::VReg_64RegClassID),
        GIR_ConstrainOperandRC, /*InsnID*/2, /*Op*/3, GIMT_Encode2(AMDGPU::VReg_64RegClassID),
        GIR_BuildMI, /*InsnID*/1, /*Opcode*/GIMT_Encode2(AMDGPU::BUFFER_ATOMIC_CMPSWAP_X2_OFFEN_RTN),
        GIR_AddTempRegister, /*InsnID*/1, /*TempRegID*/0, /*TempRegFlags*/GIMT_Encode2(RegState::Define),
        GIR_AddSimpleTempRegister, /*InsnID*/1, /*TempRegID*/1,
        GIR_Copy, /*NewInsnID*/1, /*OldInsnID*/0, /*OpIdx*/5, // voffset
        GIR_Copy, /*NewInsnID*/1, /*OldInsnID*/0, /*OpIdx*/3, // rsrc
        GIR_ComplexSubOperandRenderer, /*InsnID*/1, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/0, // soffset
        GIR_Copy, /*NewInsnID*/1, /*OldInsnID*/0, /*OpIdx*/7, // offset
        GIR_CustomOperandRenderer, /*InsnID*/1, /*OldInsnID*/0, /*OpIdx*/8, /*OperandRenderer*/GIMT_Encode2(GICR_renderExtractCpolSetGLC), // auxiliary
        GIR_MergeMemOperands, /*InsnID*/1, /*NumInsns*/1, /*MergeInsnID's*/0,
        GIR_ConstrainSelectedInstOperands, /*InsnID*/1,
        GIR_BuildMI, /*InsnID*/0, /*Opcode*/GIMT_Encode2(TargetOpcode::COPY),
        GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/0, // DstI[dst]
        GIR_AddTempSubRegister, /*InsnID*/0, /*TempRegID*/0, /*TempRegFlags*/GIMT_Encode2(0), GIMT_Encode2(AMDGPU::sub0_sub1),
        GIR_ConstrainOperandRC, /*InsnID*/0, /*Op*/0, GIMT_Encode2(AMDGPU::AV_64RegClassID),
        GIR_ConstrainOperandRC, /*InsnID*/0, /*Op*/1, GIMT_Encode2(AMDGPU::AV_128RegClassID),
        GIR_EraseFromParent, /*InsnID*/0,
        // GIR_Coverage, 5307,
        GIR_Done,
      // Label 5816: @423960
      GIM_Try, /*On fail goto*//*Label 5817*/ GIMT_Encode4(424111), // Rule ID 5315 //
        GIM_CheckRegBankForClass, /*MI*/0, /*Op*/0, /*RC*/GIMT_Encode2(AMDGPU::AV_128RegClassID),
        GIM_CheckConstantInt8, /*MI*/0, /*Op*/4, 0,
        // MIs[0] offset
        GIM_CheckIsImm, /*MI*/0, /*Op*/7,
        // MIs[0] auxiliary
        GIM_CheckIsImm, /*MI*/0, /*Op*/8,
        // MIs[0] Operand 9
        GIM_CheckLiteralInt, /*MI*/0, /*Op*/9, GIMT_Encode8(0),
        GIM_CheckComplexPattern, /*MI*/0, /*Op*/6, /*Renderer*/GIMT_Encode2(0), GIMT_Encode2(GICP_gi_buf_soffset),
        // (SIbuffer_atomic_cmpswap:{ *:[i64] } i64:{ *:[i64] }:$data, i64:{ *:[i64] }:$cmp, v4i32:{ *:[v4i32] }:$rsrc, 0:{ *:[i32] }, i32:{ *:[i32] }:$voffset, (BUFSOffset:{ *:[i32] } i32:{ *:[i32] }:$soffset), (timm:{ *:[i32] }):$offset, (timm:{ *:[i32] }):$auxiliary, 0:{ *:[i1] })  =>  (EXTRACT_SUBREG:{ *:[i64] } (BUFFER_ATOMIC_CMPSWAP_X2_VBUFFER_OFFEN_RTN:{ *:[v8i16] } (REG_SEQUENCE:{ *:[v8i16] } VReg_128:{ *:[i32] }, anonymous_15036:{ *:[i64] }:$data, sub0_sub1:{ *:[i32] }, anonymous_15036:{ *:[i64] }:$cmp, sub2_sub3:{ *:[i32] }), VGPR_32:{ *:[i32] }:$voffset, SReg_128:{ *:[v4i32] }:$rsrc, SCSrc_b32:{ *:[i32] }:$soffset, (timm:{ *:[i32] }):$offset, (extract_cpol_set_glc:{ *:[i32] } ?:{ *:[i32] }:$auxiliary)), sub0_sub1:{ *:[i32] })
        GIR_MakeTempReg, /*TempRegID*/0, /*TypeID*/GILLT_v8s16,
        GIR_MakeTempReg, /*TempRegID*/1, /*TypeID*/GILLT_v8s16,
        GIR_BuildMI, /*InsnID*/2, /*Opcode*/GIMT_Encode2(TargetOpcode::REG_SEQUENCE),
        GIR_AddTempRegister, /*InsnID*/2, /*TempRegID*/1, /*TempRegFlags*/GIMT_Encode2(RegState::Define),
        GIR_Copy, /*NewInsnID*/2, /*OldInsnID*/0, /*OpIdx*/1, // data
        GIR_AddImm8, /*InsnID*/2, /*SubRegIndex*/4,
        GIR_Copy, /*NewInsnID*/2, /*OldInsnID*/0, /*OpIdx*/2, // cmp
        GIR_AddImm8, /*InsnID*/2, /*SubRegIndex*/24,
        GIR_ConstrainOperandRC, /*InsnID*/2, /*Op*/0, GIMT_Encode2(AMDGPU::VReg_128RegClassID),
        GIR_ConstrainOperandRC, /*InsnID*/2, /*Op*/1, GIMT_Encode2(AMDGPU::VReg_64RegClassID),
        GIR_ConstrainOperandRC, /*InsnID*/2, /*Op*/3, GIMT_Encode2(AMDGPU::VReg_64RegClassID),
        GIR_BuildMI, /*InsnID*/1, /*Opcode*/GIMT_Encode2(AMDGPU::BUFFER_ATOMIC_CMPSWAP_X2_VBUFFER_OFFEN_RTN),
        GIR_AddTempRegister, /*InsnID*/1, /*TempRegID*/0, /*TempRegFlags*/GIMT_Encode2(RegState::Define),
        GIR_AddSimpleTempRegister, /*InsnID*/1, /*TempRegID*/1,
        GIR_Copy, /*NewInsnID*/1, /*OldInsnID*/0, /*OpIdx*/5, // voffset
        GIR_Copy, /*NewInsnID*/1, /*OldInsnID*/0, /*OpIdx*/3, // rsrc
        GIR_ComplexSubOperandRenderer, /*InsnID*/1, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/0, // soffset
        GIR_Copy, /*NewInsnID*/1, /*OldInsnID*/0, /*OpIdx*/7, // offset
        GIR_CustomOperandRenderer, /*InsnID*/1, /*OldInsnID*/0, /*OpIdx*/8, /*OperandRenderer*/GIMT_Encode2(GICR_renderExtractCpolSetGLC), // auxiliary
        GIR_MergeMemOperands, /*InsnID*/1, /*NumInsns*/1, /*MergeInsnID's*/0,
        GIR_ConstrainSelectedInstOperands, /*InsnID*/1,
        GIR_BuildMI, /*InsnID*/0, /*Opcode*/GIMT_Encode2(TargetOpcode::COPY),
        GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/0, // DstI[dst]
        GIR_AddTempSubRegister, /*InsnID*/0, /*TempRegID*/0, /*TempRegFlags*/GIMT_Encode2(0), GIMT_Encode2(AMDGPU::sub0_sub1),
        GIR_ConstrainOperandRC, /*InsnID*/0, /*Op*/0, GIMT_Encode2(AMDGPU::AV_64RegClassID),
        GIR_ConstrainOperandRC, /*InsnID*/0, /*Op*/1, GIMT_Encode2(AMDGPU::AV_128RegClassID),
        GIR_EraseFromParent, /*InsnID*/0,
        // GIR_Coverage, 5315,
        GIR_Done,
      // Label 5817: @424111
      GIM_Try, /*On fail goto*//*Label 5818*/ GIMT_Encode4(424221), // Rule ID 5310 //
        GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasUnrestrictedSOffset),
        GIM_CheckHasNoUse, /*MI*/0,
        GIM_CheckConstantInt8, /*MI*/0, /*Op*/5, 0,
        // MIs[0] offset
        GIM_CheckIsImm, /*MI*/0, /*Op*/7,
        // MIs[0] auxiliary
        GIM_CheckIsImm, /*MI*/0, /*Op*/8,
        // MIs[0] Operand 9
        GIM_CheckIsImm, /*MI*/0, /*Op*/9,
        GIM_CheckComplexPattern, /*MI*/0, /*Op*/6, /*Renderer*/GIMT_Encode2(0), GIMT_Encode2(GICP_gi_buf_soffset),
        // (SIbuffer_atomic_cmpswap:{ *:[i64] } i64:{ *:[i64] }:$data, i64:{ *:[i64] }:$cmp, v4i32:{ *:[v4i32] }:$rsrc, i32:{ *:[i32] }:$vindex, 0:{ *:[i32] }, (BUFSOffset:{ *:[i32] } i32:{ *:[i32] }:$soffset), (timm:{ *:[i32] }):$offset, (timm:{ *:[i32] }):$auxiliary, (timm:{ *:[i1] }))<<P:Predicate_SIbuffer_atomic_cmpswap_noret>>  =>  (BUFFER_ATOMIC_CMPSWAP_X2_IDXEN (REG_SEQUENCE:{ *:[v8i16] } VReg_128:{ *:[i32] }, anonymous_15036:{ *:[i64] }:$data, sub0_sub1:{ *:[i32] }, anonymous_15036:{ *:[i64] }:$cmp, sub2_sub3:{ *:[i32] }), VGPR_32:{ *:[i32] }:$vindex, SReg_128:{ *:[v4i32] }:$rsrc, SCSrc_b32:{ *:[i32] }:$soffset, (timm:{ *:[i32] }):$offset, (extract_cpol:{ *:[i32] } ?:{ *:[i32] }:$auxiliary))
        GIR_MakeTempReg, /*TempRegID*/0, /*TypeID*/GILLT_v8s16,
        GIR_BuildMI, /*InsnID*/1, /*Opcode*/GIMT_Encode2(TargetOpcode::REG_SEQUENCE),
        GIR_AddTempRegister, /*InsnID*/1, /*TempRegID*/0, /*TempRegFlags*/GIMT_Encode2(RegState::Define),
        GIR_Copy, /*NewInsnID*/1, /*OldInsnID*/0, /*OpIdx*/1, // data
        GIR_AddImm8, /*InsnID*/1, /*SubRegIndex*/4,
        GIR_Copy, /*NewInsnID*/1, /*OldInsnID*/0, /*OpIdx*/2, // cmp
        GIR_AddImm8, /*InsnID*/1, /*SubRegIndex*/24,
        GIR_ConstrainOperandRC, /*InsnID*/1, /*Op*/0, GIMT_Encode2(AMDGPU::VReg_128RegClassID),
        GIR_ConstrainOperandRC, /*InsnID*/1, /*Op*/1, GIMT_Encode2(AMDGPU::VReg_64RegClassID),
        GIR_ConstrainOperandRC, /*InsnID*/1, /*Op*/3, GIMT_Encode2(AMDGPU::VReg_64RegClassID),
        GIR_BuildMI, /*InsnID*/0, /*Opcode*/GIMT_Encode2(AMDGPU::BUFFER_ATOMIC_CMPSWAP_X2_IDXEN),
        GIR_AddSimpleTempRegister, /*InsnID*/0, /*TempRegID*/0,
        GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/4, // vindex
        GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/3, // rsrc
        GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/0, // soffset
        GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/7, // offset
        GIR_CustomOperandRenderer, /*InsnID*/0, /*OldInsnID*/0, /*OpIdx*/8, /*OperandRenderer*/GIMT_Encode2(GICR_renderExtractCPol), // auxiliary
        GIR_MergeMemOperands, /*InsnID*/0, /*NumInsns*/1, /*MergeInsnID's*/0,
        GIR_ConstrainSelectedInstOperands, /*InsnID*/0,
        GIR_EraseFromParent, /*InsnID*/0,
        // GIR_Coverage, 5310,
        GIR_Done,
      // Label 5818: @424221
      GIM_Try, /*On fail goto*//*Label 5819*/ GIMT_Encode4(424328), // Rule ID 5318 //
        GIM_CheckHasNoUse, /*MI*/0,
        GIM_CheckConstantInt8, /*MI*/0, /*Op*/5, 0,
        // MIs[0] offset
        GIM_CheckIsImm, /*MI*/0, /*Op*/7,
        // MIs[0] auxiliary
        GIM_CheckIsImm, /*MI*/0, /*Op*/8,
        // MIs[0] Operand 9
        GIM_CheckIsImm, /*MI*/0, /*Op*/9,
        GIM_CheckComplexPattern, /*MI*/0, /*Op*/6, /*Renderer*/GIMT_Encode2(0), GIMT_Encode2(GICP_gi_buf_soffset),
        // (SIbuffer_atomic_cmpswap:{ *:[i64] } i64:{ *:[i64] }:$data, i64:{ *:[i64] }:$cmp, v4i32:{ *:[v4i32] }:$rsrc, i32:{ *:[i32] }:$vindex, 0:{ *:[i32] }, (BUFSOffset:{ *:[i32] } i32:{ *:[i32] }:$soffset), (timm:{ *:[i32] }):$offset, (timm:{ *:[i32] }):$auxiliary, (timm:{ *:[i1] }))<<P:Predicate_SIbuffer_atomic_cmpswap_noret>>  =>  (BUFFER_ATOMIC_CMPSWAP_X2_VBUFFER_IDXEN (REG_SEQUENCE:{ *:[v8i16] } VReg_128:{ *:[i32] }, anonymous_15036:{ *:[i64] }:$data, sub0_sub1:{ *:[i32] }, anonymous_15036:{ *:[i64] }:$cmp, sub2_sub3:{ *:[i32] }), VGPR_32:{ *:[i32] }:$vindex, SReg_128:{ *:[v4i32] }:$rsrc, SCSrc_b32:{ *:[i32] }:$soffset, (timm:{ *:[i32] }):$offset, (extract_cpol:{ *:[i32] } ?:{ *:[i32] }:$auxiliary))
        GIR_MakeTempReg, /*TempRegID*/0, /*TypeID*/GILLT_v8s16,
        GIR_BuildMI, /*InsnID*/1, /*Opcode*/GIMT_Encode2(TargetOpcode::REG_SEQUENCE),
        GIR_AddTempRegister, /*InsnID*/1, /*TempRegID*/0, /*TempRegFlags*/GIMT_Encode2(RegState::Define),
        GIR_Copy, /*NewInsnID*/1, /*OldInsnID*/0, /*OpIdx*/1, // data
        GIR_AddImm8, /*InsnID*/1, /*SubRegIndex*/4,
        GIR_Copy, /*NewInsnID*/1, /*OldInsnID*/0, /*OpIdx*/2, // cmp
        GIR_AddImm8, /*InsnID*/1, /*SubRegIndex*/24,
        GIR_ConstrainOperandRC, /*InsnID*/1, /*Op*/0, GIMT_Encode2(AMDGPU::VReg_128RegClassID),
        GIR_ConstrainOperandRC, /*InsnID*/1, /*Op*/1, GIMT_Encode2(AMDGPU::VReg_64RegClassID),
        GIR_ConstrainOperandRC, /*InsnID*/1, /*Op*/3, GIMT_Encode2(AMDGPU::VReg_64RegClassID),
        GIR_BuildMI, /*InsnID*/0, /*Opcode*/GIMT_Encode2(AMDGPU::BUFFER_ATOMIC_CMPSWAP_X2_VBUFFER_IDXEN),
        GIR_AddSimpleTempRegister, /*InsnID*/0, /*TempRegID*/0,
        GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/4, // vindex
        GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/3, // rsrc
        GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/0, // soffset
        GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/7, // offset
        GIR_CustomOperandRenderer, /*InsnID*/0, /*OldInsnID*/0, /*OpIdx*/8, /*OperandRenderer*/GIMT_Encode2(GICR_renderExtractCPol), // auxiliary
        GIR_MergeMemOperands, /*InsnID*/0, /*NumInsns*/1, /*MergeInsnID's*/0,
        GIR_ConstrainSelectedInstOperands, /*InsnID*/0,
        GIR_EraseFromParent, /*InsnID*/0,
        // GIR_Coverage, 5318,
        GIR_Done,
      // Label 5819: @424328
      GIM_Try, /*On fail goto*//*Label 5820*/ GIMT_Encode4(424474), // Rule ID 5306 //
        GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasUnrestrictedSOffset),
        GIM_CheckRegBankForClass, /*MI*/0, /*Op*/0, /*RC*/GIMT_Encode2(AMDGPU::AV_128RegClassID),
        GIM_CheckConstantInt8, /*MI*/0, /*Op*/5, 0,
        // MIs[0] offset
        GIM_CheckIsImm, /*MI*/0, /*Op*/7,
        // MIs[0] auxiliary
        GIM_CheckIsImm, /*MI*/0, /*Op*/8,
        // MIs[0] Operand 9
        GIM_CheckIsImm, /*MI*/0, /*Op*/9,
        GIM_CheckComplexPattern, /*MI*/0, /*Op*/6, /*Renderer*/GIMT_Encode2(0), GIMT_Encode2(GICP_gi_buf_soffset),
        // (SIbuffer_atomic_cmpswap:{ *:[i64] } i64:{ *:[i64] }:$data, i64:{ *:[i64] }:$cmp, v4i32:{ *:[v4i32] }:$rsrc, i32:{ *:[i32] }:$vindex, 0:{ *:[i32] }, (BUFSOffset:{ *:[i32] } i32:{ *:[i32] }:$soffset), (timm:{ *:[i32] }):$offset, (timm:{ *:[i32] }):$auxiliary, (timm:{ *:[i1] }))  =>  (EXTRACT_SUBREG:{ *:[i64] } (BUFFER_ATOMIC_CMPSWAP_X2_IDXEN_RTN:{ *:[v8i16] } (REG_SEQUENCE:{ *:[v8i16] } VReg_128:{ *:[i32] }, anonymous_15036:{ *:[i64] }:$data, sub0_sub1:{ *:[i32] }, anonymous_15036:{ *:[i64] }:$cmp, sub2_sub3:{ *:[i32] }), VGPR_32:{ *:[i32] }:$vindex, SReg_128:{ *:[v4i32] }:$rsrc, SCSrc_b32:{ *:[i32] }:$soffset, (timm:{ *:[i32] }):$offset, (extract_cpol_set_glc:{ *:[i32] } ?:{ *:[i32] }:$auxiliary)), sub0_sub1:{ *:[i32] })
        GIR_MakeTempReg, /*TempRegID*/0, /*TypeID*/GILLT_v8s16,
        GIR_MakeTempReg, /*TempRegID*/1, /*TypeID*/GILLT_v8s16,
        GIR_BuildMI, /*InsnID*/2, /*Opcode*/GIMT_Encode2(TargetOpcode::REG_SEQUENCE),
        GIR_AddTempRegister, /*InsnID*/2, /*TempRegID*/1, /*TempRegFlags*/GIMT_Encode2(RegState::Define),
        GIR_Copy, /*NewInsnID*/2, /*OldInsnID*/0, /*OpIdx*/1, // data
        GIR_AddImm8, /*InsnID*/2, /*SubRegIndex*/4,
        GIR_Copy, /*NewInsnID*/2, /*OldInsnID*/0, /*OpIdx*/2, // cmp
        GIR_AddImm8, /*InsnID*/2, /*SubRegIndex*/24,
        GIR_ConstrainOperandRC, /*InsnID*/2, /*Op*/0, GIMT_Encode2(AMDGPU::VReg_128RegClassID),
        GIR_ConstrainOperandRC, /*InsnID*/2, /*Op*/1, GIMT_Encode2(AMDGPU::VReg_64RegClassID),
        GIR_ConstrainOperandRC, /*InsnID*/2, /*Op*/3, GIMT_Encode2(AMDGPU::VReg_64RegClassID),
        GIR_BuildMI, /*InsnID*/1, /*Opcode*/GIMT_Encode2(AMDGPU::BUFFER_ATOMIC_CMPSWAP_X2_IDXEN_RTN),
        GIR_AddTempRegister, /*InsnID*/1, /*TempRegID*/0, /*TempRegFlags*/GIMT_Encode2(RegState::Define),
        GIR_AddSimpleTempRegister, /*InsnID*/1, /*TempRegID*/1,
        GIR_Copy, /*NewInsnID*/1, /*OldInsnID*/0, /*OpIdx*/4, // vindex
        GIR_Copy, /*NewInsnID*/1, /*OldInsnID*/0, /*OpIdx*/3, // rsrc
        GIR_ComplexSubOperandRenderer, /*InsnID*/1, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/0, // soffset
        GIR_Copy, /*NewInsnID*/1, /*OldInsnID*/0, /*OpIdx*/7, // offset
        GIR_CustomOperandRenderer, /*InsnID*/1, /*OldInsnID*/0, /*OpIdx*/8, /*OperandRenderer*/GIMT_Encode2(GICR_renderExtractCpolSetGLC), // auxiliary
        GIR_MergeMemOperands, /*InsnID*/1, /*NumInsns*/1, /*MergeInsnID's*/0,
        GIR_ConstrainSelectedInstOperands, /*InsnID*/1,
        GIR_BuildMI, /*InsnID*/0, /*Opcode*/GIMT_Encode2(TargetOpcode::COPY),
        GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/0, // DstI[dst]
        GIR_AddTempSubRegister, /*InsnID*/0, /*TempRegID*/0, /*TempRegFlags*/GIMT_Encode2(0), GIMT_Encode2(AMDGPU::sub0_sub1),
        GIR_ConstrainOperandRC, /*InsnID*/0, /*Op*/0, GIMT_Encode2(AMDGPU::AV_64RegClassID),
        GIR_ConstrainOperandRC, /*InsnID*/0, /*Op*/1, GIMT_Encode2(AMDGPU::AV_128RegClassID),
        GIR_EraseFromParent, /*InsnID*/0,
        // GIR_Coverage, 5306,
        GIR_Done,
      // Label 5820: @424474
      GIM_Try, /*On fail goto*//*Label 5821*/ GIMT_Encode4(424617), // Rule ID 5314 //
        GIM_CheckRegBankForClass, /*MI*/0, /*Op*/0, /*RC*/GIMT_Encode2(AMDGPU::AV_128RegClassID),
        GIM_CheckConstantInt8, /*MI*/0, /*Op*/5, 0,
        // MIs[0] offset
        GIM_CheckIsImm, /*MI*/0, /*Op*/7,
        // MIs[0] auxiliary
        GIM_CheckIsImm, /*MI*/0, /*Op*/8,
        // MIs[0] Operand 9
        GIM_CheckIsImm, /*MI*/0, /*Op*/9,
        GIM_CheckComplexPattern, /*MI*/0, /*Op*/6, /*Renderer*/GIMT_Encode2(0), GIMT_Encode2(GICP_gi_buf_soffset),
        // (SIbuffer_atomic_cmpswap:{ *:[i64] } i64:{ *:[i64] }:$data, i64:{ *:[i64] }:$cmp, v4i32:{ *:[v4i32] }:$rsrc, i32:{ *:[i32] }:$vindex, 0:{ *:[i32] }, (BUFSOffset:{ *:[i32] } i32:{ *:[i32] }:$soffset), (timm:{ *:[i32] }):$offset, (timm:{ *:[i32] }):$auxiliary, (timm:{ *:[i1] }))  =>  (EXTRACT_SUBREG:{ *:[i64] } (BUFFER_ATOMIC_CMPSWAP_X2_VBUFFER_IDXEN_RTN:{ *:[v8i16] } (REG_SEQUENCE:{ *:[v8i16] } VReg_128:{ *:[i32] }, anonymous_15036:{ *:[i64] }:$data, sub0_sub1:{ *:[i32] }, anonymous_15036:{ *:[i64] }:$cmp, sub2_sub3:{ *:[i32] }), VGPR_32:{ *:[i32] }:$vindex, SReg_128:{ *:[v4i32] }:$rsrc, SCSrc_b32:{ *:[i32] }:$soffset, (timm:{ *:[i32] }):$offset, (extract_cpol_set_glc:{ *:[i32] } ?:{ *:[i32] }:$auxiliary)), sub0_sub1:{ *:[i32] })
        GIR_MakeTempReg, /*TempRegID*/0, /*TypeID*/GILLT_v8s16,
        GIR_MakeTempReg, /*TempRegID*/1, /*TypeID*/GILLT_v8s16,
        GIR_BuildMI, /*InsnID*/2, /*Opcode*/GIMT_Encode2(TargetOpcode::REG_SEQUENCE),
        GIR_AddTempRegister, /*InsnID*/2, /*TempRegID*/1, /*TempRegFlags*/GIMT_Encode2(RegState::Define),
        GIR_Copy, /*NewInsnID*/2, /*OldInsnID*/0, /*OpIdx*/1, // data
        GIR_AddImm8, /*InsnID*/2, /*SubRegIndex*/4,
        GIR_Copy, /*NewInsnID*/2, /*OldInsnID*/0, /*OpIdx*/2, // cmp
        GIR_AddImm8, /*InsnID*/2, /*SubRegIndex*/24,
        GIR_ConstrainOperandRC, /*InsnID*/2, /*Op*/0, GIMT_Encode2(AMDGPU::VReg_128RegClassID),
        GIR_ConstrainOperandRC, /*InsnID*/2, /*Op*/1, GIMT_Encode2(AMDGPU::VReg_64RegClassID),
        GIR_ConstrainOperandRC, /*InsnID*/2, /*Op*/3, GIMT_Encode2(AMDGPU::VReg_64RegClassID),
        GIR_BuildMI, /*InsnID*/1, /*Opcode*/GIMT_Encode2(AMDGPU::BUFFER_ATOMIC_CMPSWAP_X2_VBUFFER_IDXEN_RTN),
        GIR_AddTempRegister, /*InsnID*/1, /*TempRegID*/0, /*TempRegFlags*/GIMT_Encode2(RegState::Define),
        GIR_AddSimpleTempRegister, /*InsnID*/1, /*TempRegID*/1,
        GIR_Copy, /*NewInsnID*/1, /*OldInsnID*/0, /*OpIdx*/4, // vindex
        GIR_Copy, /*NewInsnID*/1, /*OldInsnID*/0, /*OpIdx*/3, // rsrc
        GIR_ComplexSubOperandRenderer, /*InsnID*/1, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/0, // soffset
        GIR_Copy, /*NewInsnID*/1, /*OldInsnID*/0, /*OpIdx*/7, // offset
        GIR_CustomOperandRenderer, /*InsnID*/1, /*OldInsnID*/0, /*OpIdx*/8, /*OperandRenderer*/GIMT_Encode2(GICR_renderExtractCpolSetGLC), // auxiliary
        GIR_MergeMemOperands, /*InsnID*/1, /*NumInsns*/1, /*MergeInsnID's*/0,
        GIR_ConstrainSelectedInstOperands, /*InsnID*/1,
        GIR_BuildMI, /*InsnID*/0, /*Opcode*/GIMT_Encode2(TargetOpcode::COPY),
        GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/0, // DstI[dst]
        GIR_AddTempSubRegister, /*InsnID*/0, /*TempRegID*/0, /*TempRegFlags*/GIMT_Encode2(0), GIMT_Encode2(AMDGPU::sub0_sub1),
        GIR_ConstrainOperandRC, /*InsnID*/0, /*Op*/0, GIMT_Encode2(AMDGPU::AV_64RegClassID),
        GIR_ConstrainOperandRC, /*InsnID*/0, /*Op*/1, GIMT_Encode2(AMDGPU::AV_128RegClassID),
        GIR_EraseFromParent, /*InsnID*/0,
        // GIR_Coverage, 5314,
        GIR_Done,
      // Label 5821: @424617
      GIM_Try, /*On fail goto*//*Label 5822*/ GIMT_Encode4(424763), // Rule ID 5312 //
        GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasUnrestrictedSOffset),
        GIM_CheckHasNoUse, /*MI*/0,
        // MIs[0] offset
        GIM_CheckIsImm, /*MI*/0, /*Op*/7,
        // MIs[0] auxiliary
        GIM_CheckIsImm, /*MI*/0, /*Op*/8,
        // MIs[0] Operand 9
        GIM_CheckIsImm, /*MI*/0, /*Op*/9,
        GIM_CheckComplexPattern, /*MI*/0, /*Op*/6, /*Renderer*/GIMT_Encode2(0), GIMT_Encode2(GICP_gi_buf_soffset),
        // (SIbuffer_atomic_cmpswap:{ *:[i64] } i64:{ *:[i64] }:$data, i64:{ *:[i64] }:$cmp, v4i32:{ *:[v4i32] }:$rsrc, i32:{ *:[i32] }:$vindex, i32:{ *:[i32] }:$voffset, (BUFSOffset:{ *:[i32] } i32:{ *:[i32] }:$soffset), (timm:{ *:[i32] }):$offset, (timm:{ *:[i32] }):$auxiliary, (timm:{ *:[i1] }))<<P:Predicate_SIbuffer_atomic_cmpswap_noret>>  =>  (BUFFER_ATOMIC_CMPSWAP_X2_BOTHEN (REG_SEQUENCE:{ *:[v8i16] } VReg_128:{ *:[i32] }, anonymous_15036:{ *:[i64] }:$data, sub0_sub1:{ *:[i32] }, anonymous_15036:{ *:[i64] }:$cmp, sub2_sub3:{ *:[i32] }), (REG_SEQUENCE:{ *:[i64] } VReg_64:{ *:[i32] }, VGPR_32:{ *:[i32] }:$vindex, sub0:{ *:[i32] }, VGPR_32:{ *:[i32] }:$voffset, sub1:{ *:[i32] }), SReg_128:{ *:[v4i32] }:$rsrc, SCSrc_b32:{ *:[i32] }:$soffset, (timm:{ *:[i32] }):$offset, (extract_cpol:{ *:[i32] } ?:{ *:[i32] }:$auxiliary))
        GIR_MakeTempReg, /*TempRegID*/0, /*TypeID*/GILLT_v8s16,
        GIR_MakeTempReg, /*TempRegID*/1, /*TypeID*/GILLT_s64,
        GIR_BuildMI, /*InsnID*/2, /*Opcode*/GIMT_Encode2(TargetOpcode::REG_SEQUENCE),
        GIR_AddTempRegister, /*InsnID*/2, /*TempRegID*/1, /*TempRegFlags*/GIMT_Encode2(RegState::Define),
        GIR_Copy, /*NewInsnID*/2, /*OldInsnID*/0, /*OpIdx*/4, // vindex
        GIR_AddImm8, /*InsnID*/2, /*SubRegIndex*/3,
        GIR_Copy, /*NewInsnID*/2, /*OldInsnID*/0, /*OpIdx*/5, // voffset
        GIR_AddImm8, /*InsnID*/2, /*SubRegIndex*/11,
        GIR_ConstrainOperandRC, /*InsnID*/2, /*Op*/0, GIMT_Encode2(AMDGPU::VReg_64RegClassID),
        GIR_ConstrainOperandRC, /*InsnID*/2, /*Op*/1, GIMT_Encode2(AMDGPU::VGPR_32RegClassID),
        GIR_ConstrainOperandRC, /*InsnID*/2, /*Op*/3, GIMT_Encode2(AMDGPU::VGPR_32RegClassID),
        GIR_BuildMI, /*InsnID*/1, /*Opcode*/GIMT_Encode2(TargetOpcode::REG_SEQUENCE),
        GIR_AddTempRegister, /*InsnID*/1, /*TempRegID*/0, /*TempRegFlags*/GIMT_Encode2(RegState::Define),
        GIR_Copy, /*NewInsnID*/1, /*OldInsnID*/0, /*OpIdx*/1, // data
        GIR_AddImm8, /*InsnID*/1, /*SubRegIndex*/4,
        GIR_Copy, /*NewInsnID*/1, /*OldInsnID*/0, /*OpIdx*/2, // cmp
        GIR_AddImm8, /*InsnID*/1, /*SubRegIndex*/24,
        GIR_ConstrainOperandRC, /*InsnID*/1, /*Op*/0, GIMT_Encode2(AMDGPU::VReg_128RegClassID),
        GIR_ConstrainOperandRC, /*InsnID*/1, /*Op*/1, GIMT_Encode2(AMDGPU::VReg_64RegClassID),
        GIR_ConstrainOperandRC, /*InsnID*/1, /*Op*/3, GIMT_Encode2(AMDGPU::VReg_64RegClassID),
        GIR_BuildMI, /*InsnID*/0, /*Opcode*/GIMT_Encode2(AMDGPU::BUFFER_ATOMIC_CMPSWAP_X2_BOTHEN),
        GIR_AddSimpleTempRegister, /*InsnID*/0, /*TempRegID*/0,
        GIR_AddSimpleTempRegister, /*InsnID*/0, /*TempRegID*/1,
        GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/3, // rsrc
        GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/0, // soffset
        GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/7, // offset
        GIR_CustomOperandRenderer, /*InsnID*/0, /*OldInsnID*/0, /*OpIdx*/8, /*OperandRenderer*/GIMT_Encode2(GICR_renderExtractCPol), // auxiliary
        GIR_MergeMemOperands, /*InsnID*/0, /*NumInsns*/1, /*MergeInsnID's*/0,
        GIR_ConstrainSelectedInstOperands, /*InsnID*/0,
        GIR_EraseFromParent, /*InsnID*/0,
        // GIR_Coverage, 5312,
        GIR_Done,
      // Label 5822: @424763
      GIM_Try, /*On fail goto*//*Label 5823*/ GIMT_Encode4(424906), // Rule ID 5320 //
        GIM_CheckHasNoUse, /*MI*/0,
        // MIs[0] offset
        GIM_CheckIsImm, /*MI*/0, /*Op*/7,
        // MIs[0] auxiliary
        GIM_CheckIsImm, /*MI*/0, /*Op*/8,
        // MIs[0] Operand 9
        GIM_CheckIsImm, /*MI*/0, /*Op*/9,
        GIM_CheckComplexPattern, /*MI*/0, /*Op*/6, /*Renderer*/GIMT_Encode2(0), GIMT_Encode2(GICP_gi_buf_soffset),
        // (SIbuffer_atomic_cmpswap:{ *:[i64] } i64:{ *:[i64] }:$data, i64:{ *:[i64] }:$cmp, v4i32:{ *:[v4i32] }:$rsrc, i32:{ *:[i32] }:$vindex, i32:{ *:[i32] }:$voffset, (BUFSOffset:{ *:[i32] } i32:{ *:[i32] }:$soffset), (timm:{ *:[i32] }):$offset, (timm:{ *:[i32] }):$auxiliary, (timm:{ *:[i1] }))<<P:Predicate_SIbuffer_atomic_cmpswap_noret>>  =>  (BUFFER_ATOMIC_CMPSWAP_X2_VBUFFER_BOTHEN (REG_SEQUENCE:{ *:[v8i16] } VReg_128:{ *:[i32] }, anonymous_15036:{ *:[i64] }:$data, sub0_sub1:{ *:[i32] }, anonymous_15036:{ *:[i64] }:$cmp, sub2_sub3:{ *:[i32] }), (REG_SEQUENCE:{ *:[i64] } VReg_64:{ *:[i32] }, VGPR_32:{ *:[i32] }:$vindex, sub0:{ *:[i32] }, VGPR_32:{ *:[i32] }:$voffset, sub1:{ *:[i32] }), SReg_128:{ *:[v4i32] }:$rsrc, SCSrc_b32:{ *:[i32] }:$soffset, (timm:{ *:[i32] }):$offset, (extract_cpol:{ *:[i32] } ?:{ *:[i32] }:$auxiliary))
        GIR_MakeTempReg, /*TempRegID*/0, /*TypeID*/GILLT_v8s16,
        GIR_MakeTempReg, /*TempRegID*/1, /*TypeID*/GILLT_s64,
        GIR_BuildMI, /*InsnID*/2, /*Opcode*/GIMT_Encode2(TargetOpcode::REG_SEQUENCE),
        GIR_AddTempRegister, /*InsnID*/2, /*TempRegID*/1, /*TempRegFlags*/GIMT_Encode2(RegState::Define),
        GIR_Copy, /*NewInsnID*/2, /*OldInsnID*/0, /*OpIdx*/4, // vindex
        GIR_AddImm8, /*InsnID*/2, /*SubRegIndex*/3,
        GIR_Copy, /*NewInsnID*/2, /*OldInsnID*/0, /*OpIdx*/5, // voffset
        GIR_AddImm8, /*InsnID*/2, /*SubRegIndex*/11,
        GIR_ConstrainOperandRC, /*InsnID*/2, /*Op*/0, GIMT_Encode2(AMDGPU::VReg_64RegClassID),
        GIR_ConstrainOperandRC, /*InsnID*/2, /*Op*/1, GIMT_Encode2(AMDGPU::VGPR_32RegClassID),
        GIR_ConstrainOperandRC, /*InsnID*/2, /*Op*/3, GIMT_Encode2(AMDGPU::VGPR_32RegClassID),
        GIR_BuildMI, /*InsnID*/1, /*Opcode*/GIMT_Encode2(TargetOpcode::REG_SEQUENCE),
        GIR_AddTempRegister, /*InsnID*/1, /*TempRegID*/0, /*TempRegFlags*/GIMT_Encode2(RegState::Define),
        GIR_Copy, /*NewInsnID*/1, /*OldInsnID*/0, /*OpIdx*/1, // data
        GIR_AddImm8, /*InsnID*/1, /*SubRegIndex*/4,
        GIR_Copy, /*NewInsnID*/1, /*OldInsnID*/0, /*OpIdx*/2, // cmp
        GIR_AddImm8, /*InsnID*/1, /*SubRegIndex*/24,
        GIR_ConstrainOperandRC, /*InsnID*/1, /*Op*/0, GIMT_Encode2(AMDGPU::VReg_128RegClassID),
        GIR_ConstrainOperandRC, /*InsnID*/1, /*Op*/1, GIMT_Encode2(AMDGPU::VReg_64RegClassID),
        GIR_ConstrainOperandRC, /*InsnID*/1, /*Op*/3, GIMT_Encode2(AMDGPU::VReg_64RegClassID),
        GIR_BuildMI, /*InsnID*/0, /*Opcode*/GIMT_Encode2(AMDGPU::BUFFER_ATOMIC_CMPSWAP_X2_VBUFFER_BOTHEN),
        GIR_AddSimpleTempRegister, /*InsnID*/0, /*TempRegID*/0,
        GIR_AddSimpleTempRegister, /*InsnID*/0, /*TempRegID*/1,
        GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/3, // rsrc
        GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/0, // soffset
        GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/7, // offset
        GIR_CustomOperandRenderer, /*InsnID*/0, /*OldInsnID*/0, /*OpIdx*/8, /*OperandRenderer*/GIMT_Encode2(GICR_renderExtractCPol), // auxiliary
        GIR_MergeMemOperands, /*InsnID*/0, /*NumInsns*/1, /*MergeInsnID's*/0,
        GIR_ConstrainSelectedInstOperands, /*InsnID*/0,
        GIR_EraseFromParent, /*InsnID*/0,
        // GIR_Coverage, 5320,
        GIR_Done,
      // Label 5823: @424906
      GIM_Try, /*On fail goto*//*Label 5824*/ GIMT_Encode4(425088), // Rule ID 5308 //
        GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasUnrestrictedSOffset),
        GIM_CheckRegBankForClass, /*MI*/0, /*Op*/0, /*RC*/GIMT_Encode2(AMDGPU::AV_128RegClassID),
        // MIs[0] offset
        GIM_CheckIsImm, /*MI*/0, /*Op*/7,
        // MIs[0] auxiliary
        GIM_CheckIsImm, /*MI*/0, /*Op*/8,
        // MIs[0] Operand 9
        GIM_CheckIsImm, /*MI*/0, /*Op*/9,
        GIM_CheckComplexPattern, /*MI*/0, /*Op*/6, /*Renderer*/GIMT_Encode2(0), GIMT_Encode2(GICP_gi_buf_soffset),
        // (SIbuffer_atomic_cmpswap:{ *:[i64] } i64:{ *:[i64] }:$data, i64:{ *:[i64] }:$cmp, v4i32:{ *:[v4i32] }:$rsrc, i32:{ *:[i32] }:$vindex, i32:{ *:[i32] }:$voffset, (BUFSOffset:{ *:[i32] } i32:{ *:[i32] }:$soffset), (timm:{ *:[i32] }):$offset, (timm:{ *:[i32] }):$auxiliary, (timm:{ *:[i1] }))  =>  (EXTRACT_SUBREG:{ *:[i64] } (BUFFER_ATOMIC_CMPSWAP_X2_BOTHEN_RTN:{ *:[v8i16] } (REG_SEQUENCE:{ *:[v8i16] } VReg_128:{ *:[i32] }, anonymous_15036:{ *:[i64] }:$data, sub0_sub1:{ *:[i32] }, anonymous_15036:{ *:[i64] }:$cmp, sub2_sub3:{ *:[i32] }), (REG_SEQUENCE:{ *:[i64] } VReg_64:{ *:[i32] }, VGPR_32:{ *:[i32] }:$vindex, sub0:{ *:[i32] }, VGPR_32:{ *:[i32] }:$voffset, sub1:{ *:[i32] }), SReg_128:{ *:[v4i32] }:$rsrc, SCSrc_b32:{ *:[i32] }:$soffset, (timm:{ *:[i32] }):$offset, (extract_cpol_set_glc:{ *:[i32] } ?:{ *:[i32] }:$auxiliary)), sub0_sub1:{ *:[i32] })
        GIR_MakeTempReg, /*TempRegID*/0, /*TypeID*/GILLT_v8s16,
        GIR_MakeTempReg, /*TempRegID*/1, /*TypeID*/GILLT_v8s16,
        GIR_MakeTempReg, /*TempRegID*/2, /*TypeID*/GILLT_s64,
        GIR_BuildMI, /*InsnID*/3, /*Opcode*/GIMT_Encode2(TargetOpcode::REG_SEQUENCE),
        GIR_AddTempRegister, /*InsnID*/3, /*TempRegID*/2, /*TempRegFlags*/GIMT_Encode2(RegState::Define),
        GIR_Copy, /*NewInsnID*/3, /*OldInsnID*/0, /*OpIdx*/4, // vindex
        GIR_AddImm8, /*InsnID*/3, /*SubRegIndex*/3,
        GIR_Copy, /*NewInsnID*/3, /*OldInsnID*/0, /*OpIdx*/5, // voffset
        GIR_AddImm8, /*InsnID*/3, /*SubRegIndex*/11,
        GIR_ConstrainOperandRC, /*InsnID*/3, /*Op*/0, GIMT_Encode2(AMDGPU::VReg_64RegClassID),
        GIR_ConstrainOperandRC, /*InsnID*/3, /*Op*/1, GIMT_Encode2(AMDGPU::VGPR_32RegClassID),
        GIR_ConstrainOperandRC, /*InsnID*/3, /*Op*/3, GIMT_Encode2(AMDGPU::VGPR_32RegClassID),
        GIR_BuildMI, /*InsnID*/2, /*Opcode*/GIMT_Encode2(TargetOpcode::REG_SEQUENCE),
        GIR_AddTempRegister, /*InsnID*/2, /*TempRegID*/1, /*TempRegFlags*/GIMT_Encode2(RegState::Define),
        GIR_Copy, /*NewInsnID*/2, /*OldInsnID*/0, /*OpIdx*/1, // data
        GIR_AddImm8, /*InsnID*/2, /*SubRegIndex*/4,
        GIR_Copy, /*NewInsnID*/2, /*OldInsnID*/0, /*OpIdx*/2, // cmp
        GIR_AddImm8, /*InsnID*/2, /*SubRegIndex*/24,
        GIR_ConstrainOperandRC, /*InsnID*/2, /*Op*/0, GIMT_Encode2(AMDGPU::VReg_128RegClassID),
        GIR_ConstrainOperandRC, /*InsnID*/2, /*Op*/1, GIMT_Encode2(AMDGPU::VReg_64RegClassID),
        GIR_ConstrainOperandRC, /*InsnID*/2, /*Op*/3, GIMT_Encode2(AMDGPU::VReg_64RegClassID),
        GIR_BuildMI, /*InsnID*/1, /*Opcode*/GIMT_Encode2(AMDGPU::BUFFER_ATOMIC_CMPSWAP_X2_BOTHEN_RTN),
        GIR_AddTempRegister, /*InsnID*/1, /*TempRegID*/0, /*TempRegFlags*/GIMT_Encode2(RegState::Define),
        GIR_AddSimpleTempRegister, /*InsnID*/1, /*TempRegID*/1,
        GIR_AddSimpleTempRegister, /*InsnID*/1, /*TempRegID*/2,
        GIR_Copy, /*NewInsnID*/1, /*OldInsnID*/0, /*OpIdx*/3, // rsrc
        GIR_ComplexSubOperandRenderer, /*InsnID*/1, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/0, // soffset
        GIR_Copy, /*NewInsnID*/1, /*OldInsnID*/0, /*OpIdx*/7, // offset
        GIR_CustomOperandRenderer, /*InsnID*/1, /*OldInsnID*/0, /*OpIdx*/8, /*OperandRenderer*/GIMT_Encode2(GICR_renderExtractCpolSetGLC), // auxiliary
        GIR_MergeMemOperands, /*InsnID*/1, /*NumInsns*/1, /*MergeInsnID's*/0,
        GIR_ConstrainSelectedInstOperands, /*InsnID*/1,
        GIR_BuildMI, /*InsnID*/0, /*Opcode*/GIMT_Encode2(TargetOpcode::COPY),
        GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/0, // DstI[dst]
        GIR_AddTempSubRegister, /*InsnID*/0, /*TempRegID*/0, /*TempRegFlags*/GIMT_Encode2(0), GIMT_Encode2(AMDGPU::sub0_sub1),
        GIR_ConstrainOperandRC, /*InsnID*/0, /*Op*/0, GIMT_Encode2(AMDGPU::AV_64RegClassID),
        GIR_ConstrainOperandRC, /*InsnID*/0, /*Op*/1, GIMT_Encode2(AMDGPU::AV_128RegClassID),
        GIR_EraseFromParent, /*InsnID*/0,
        // GIR_Coverage, 5308,
        GIR_Done,
      // Label 5824: @425088
      GIM_Try, /*On fail goto*//*Label 5825*/ GIMT_Encode4(425267), // Rule ID 5316 //
        GIM_CheckRegBankForClass, /*MI*/0, /*Op*/0, /*RC*/GIMT_Encode2(AMDGPU::AV_128RegClassID),
        // MIs[0] offset
        GIM_CheckIsImm, /*MI*/0, /*Op*/7,
        // MIs[0] auxiliary
        GIM_CheckIsImm, /*MI*/0, /*Op*/8,
        // MIs[0] Operand 9
        GIM_CheckIsImm, /*MI*/0, /*Op*/9,
        GIM_CheckComplexPattern, /*MI*/0, /*Op*/6, /*Renderer*/GIMT_Encode2(0), GIMT_Encode2(GICP_gi_buf_soffset),
        // (SIbuffer_atomic_cmpswap:{ *:[i64] } i64:{ *:[i64] }:$data, i64:{ *:[i64] }:$cmp, v4i32:{ *:[v4i32] }:$rsrc, i32:{ *:[i32] }:$vindex, i32:{ *:[i32] }:$voffset, (BUFSOffset:{ *:[i32] } i32:{ *:[i32] }:$soffset), (timm:{ *:[i32] }):$offset, (timm:{ *:[i32] }):$auxiliary, (timm:{ *:[i1] }))  =>  (EXTRACT_SUBREG:{ *:[i64] } (BUFFER_ATOMIC_CMPSWAP_X2_VBUFFER_BOTHEN_RTN:{ *:[v8i16] } (REG_SEQUENCE:{ *:[v8i16] } VReg_128:{ *:[i32] }, anonymous_15036:{ *:[i64] }:$data, sub0_sub1:{ *:[i32] }, anonymous_15036:{ *:[i64] }:$cmp, sub2_sub3:{ *:[i32] }), (REG_SEQUENCE:{ *:[i64] } VReg_64:{ *:[i32] }, VGPR_32:{ *:[i32] }:$vindex, sub0:{ *:[i32] }, VGPR_32:{ *:[i32] }:$voffset, sub1:{ *:[i32] }), SReg_128:{ *:[v4i32] }:$rsrc, SCSrc_b32:{ *:[i32] }:$soffset, (timm:{ *:[i32] }):$offset, (extract_cpol_set_glc:{ *:[i32] } ?:{ *:[i32] }:$auxiliary)), sub0_sub1:{ *:[i32] })
        GIR_MakeTempReg, /*TempRegID*/0, /*TypeID*/GILLT_v8s16,
        GIR_MakeTempReg, /*TempRegID*/1, /*TypeID*/GILLT_v8s16,
        GIR_MakeTempReg, /*TempRegID*/2, /*TypeID*/GILLT_s64,
        GIR_BuildMI, /*InsnID*/3, /*Opcode*/GIMT_Encode2(TargetOpcode::REG_SEQUENCE),
        GIR_AddTempRegister, /*InsnID*/3, /*TempRegID*/2, /*TempRegFlags*/GIMT_Encode2(RegState::Define),
        GIR_Copy, /*NewInsnID*/3, /*OldInsnID*/0, /*OpIdx*/4, // vindex
        GIR_AddImm8, /*InsnID*/3, /*SubRegIndex*/3,
        GIR_Copy, /*NewInsnID*/3, /*OldInsnID*/0, /*OpIdx*/5, // voffset
        GIR_AddImm8, /*InsnID*/3, /*SubRegIndex*/11,
        GIR_ConstrainOperandRC, /*InsnID*/3, /*Op*/0, GIMT_Encode2(AMDGPU::VReg_64RegClassID),
        GIR_ConstrainOperandRC, /*InsnID*/3, /*Op*/1, GIMT_Encode2(AMDGPU::VGPR_32RegClassID),
        GIR_ConstrainOperandRC, /*InsnID*/3, /*Op*/3, GIMT_Encode2(AMDGPU::VGPR_32RegClassID),
        GIR_BuildMI, /*InsnID*/2, /*Opcode*/GIMT_Encode2(TargetOpcode::REG_SEQUENCE),
        GIR_AddTempRegister, /*InsnID*/2, /*TempRegID*/1, /*TempRegFlags*/GIMT_Encode2(RegState::Define),
        GIR_Copy, /*NewInsnID*/2, /*OldInsnID*/0, /*OpIdx*/1, // data
        GIR_AddImm8, /*InsnID*/2, /*SubRegIndex*/4,
        GIR_Copy, /*NewInsnID*/2, /*OldInsnID*/0, /*OpIdx*/2, // cmp
        GIR_AddImm8, /*InsnID*/2, /*SubRegIndex*/24,
        GIR_ConstrainOperandRC, /*InsnID*/2, /*Op*/0, GIMT_Encode2(AMDGPU::VReg_128RegClassID),
        GIR_ConstrainOperandRC, /*InsnID*/2, /*Op*/1, GIMT_Encode2(AMDGPU::VReg_64RegClassID),
        GIR_ConstrainOperandRC, /*InsnID*/2, /*Op*/3, GIMT_Encode2(AMDGPU::VReg_64RegClassID),
        GIR_BuildMI, /*InsnID*/1, /*Opcode*/GIMT_Encode2(AMDGPU::BUFFER_ATOMIC_CMPSWAP_X2_VBUFFER_BOTHEN_RTN),
        GIR_AddTempRegister, /*InsnID*/1, /*TempRegID*/0, /*TempRegFlags*/GIMT_Encode2(RegState::Define),
        GIR_AddSimpleTempRegister, /*InsnID*/1, /*TempRegID*/1,
        GIR_AddSimpleTempRegister, /*InsnID*/1, /*TempRegID*/2,
        GIR_Copy, /*NewInsnID*/1, /*OldInsnID*/0, /*OpIdx*/3, // rsrc
        GIR_ComplexSubOperandRenderer, /*InsnID*/1, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/0, // soffset
        GIR_Copy, /*NewInsnID*/1, /*OldInsnID*/0, /*OpIdx*/7, // offset
        GIR_CustomOperandRenderer, /*InsnID*/1, /*OldInsnID*/0, /*OpIdx*/8, /*OperandRenderer*/GIMT_Encode2(GICR_renderExtractCpolSetGLC), // auxiliary
        GIR_MergeMemOperands, /*InsnID*/1, /*NumInsns*/1, /*MergeInsnID's*/0,
        GIR_ConstrainSelectedInstOperands, /*InsnID*/1,
        GIR_BuildMI, /*InsnID*/0, /*Opcode*/GIMT_Encode2(TargetOpcode::COPY),
        GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/0, // DstI[dst]
        GIR_AddTempSubRegister, /*InsnID*/0, /*TempRegID*/0, /*TempRegFlags*/GIMT_Encode2(0), GIMT_Encode2(AMDGPU::sub0_sub1),
        GIR_ConstrainOperandRC, /*InsnID*/0, /*Op*/0, GIMT_Encode2(AMDGPU::AV_64RegClassID),
        GIR_ConstrainOperandRC, /*InsnID*/0, /*Op*/1, GIMT_Encode2(AMDGPU::AV_128RegClassID),
        GIR_EraseFromParent, /*InsnID*/0,
        // GIR_Coverage, 5316,
        GIR_Done,
      // Label 5825: @425267
      GIM_Reject,
    // Label 5809: @425268
    GIM_Reject,
    // Label 5791: @425269
    GIM_Reject,
    // Label 109: @425270
    GIM_Try, /*On fail goto*//*Label 5826*/ GIMT_Encode4(425992),
      GIM_CheckType, /*MI*/0, /*Op*/0, /*Type*/GILLT_s32,
      GIM_CheckType, /*MI*/0, /*Op*/1, /*Type*/GILLT_s32,
      GIM_CheckType, /*MI*/0, /*Op*/2, /*Type*/GILLT_v4s32,
      GIM_CheckType, /*MI*/0, /*Op*/3, /*Type*/GILLT_s32,
      GIM_CheckType, /*MI*/0, /*Op*/4, /*Type*/GILLT_s32,
      GIM_CheckType, /*MI*/0, /*Op*/5, /*Type*/GILLT_s32,
      GIM_Try, /*On fail goto*//*Label 5827*/ GIMT_Encode4(425377), // Rule ID 5141 //
        GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasAtomicCSubNoRtnInsts_isGFX12Plus),
        GIM_CheckHasNoUse, /*MI*/0,
        GIM_CheckConstantInt8, /*MI*/0, /*Op*/3, 0,
        GIM_CheckConstantInt8, /*MI*/0, /*Op*/4, 0,
        // MIs[0] offset
        GIM_CheckIsImm, /*MI*/0, /*Op*/6,
        // MIs[0] auxiliary
        GIM_CheckIsImm, /*MI*/0, /*Op*/7,
        // MIs[0] Operand 8
        GIM_CheckLiteralInt, /*MI*/0, /*Op*/8, GIMT_Encode8(0),
        GIM_CheckComplexPattern, /*MI*/0, /*Op*/5, /*Renderer*/GIMT_Encode2(0), GIMT_Encode2(GICP_gi_buf_soffset),
        // (SIbuffer_atomic_cond_sub_u32:{ *:[i32] } i32:{ *:[i32] }:$vdata_in, v4i32:{ *:[v4i32] }:$rsrc, 0:{ *:[i32] }, 0:{ *:[i32] }, (BUFSOffset:{ *:[i32] } i32:{ *:[i32] }:$soffset), (timm:{ *:[i32] }):$offset, (timm:{ *:[i32] }):$auxiliary, 0:{ *:[i1] })<<P:Predicate_SIbuffer_atomic_cond_sub_u32_noret>>  =>  (BUFFER_ATOMIC_COND_SUB_U32_VBUFFER_OFFSET anonymous_15037:{ *:[i32] }:$vdata_in, SReg_128:{ *:[v4i32] }:$rsrc, SCSrc_b32:{ *:[i32] }:$soffset, (timm:{ *:[i32] }):$offset, (extract_cpol:{ *:[i32] } ?:{ *:[i32] }:$auxiliary))
        GIR_BuildMI, /*InsnID*/0, /*Opcode*/GIMT_Encode2(AMDGPU::BUFFER_ATOMIC_COND_SUB_U32_VBUFFER_OFFSET),
        GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/1, // vdata_in
        GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/2, // rsrc
        GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/0, // soffset
        GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/6, // offset
        GIR_CustomOperandRenderer, /*InsnID*/0, /*OldInsnID*/0, /*OpIdx*/7, /*OperandRenderer*/GIMT_Encode2(GICR_renderExtractCPol), // auxiliary
        GIR_MergeMemOperands, /*InsnID*/0, /*NumInsns*/1, /*MergeInsnID's*/0,
        GIR_ConstrainSelectedInstOperands, /*InsnID*/0,
        GIR_EraseFromParent, /*InsnID*/0,
        // GIR_Coverage, 5141,
        GIR_Done,
      // Label 5827: @425377
      GIM_Try, /*On fail goto*//*Label 5828*/ GIMT_Encode4(425462), // Rule ID 5137 //
        GIM_CheckFeatures, GIMT_Encode2(GIFBS_isGFX12Plus),
        GIM_CheckRegBankForClass, /*MI*/0, /*Op*/0, /*RC*/GIMT_Encode2(AMDGPU::AV_32RegClassID),
        GIM_CheckConstantInt8, /*MI*/0, /*Op*/3, 0,
        GIM_CheckConstantInt8, /*MI*/0, /*Op*/4, 0,
        // MIs[0] offset
        GIM_CheckIsImm, /*MI*/0, /*Op*/6,
        // MIs[0] auxiliary
        GIM_CheckIsImm, /*MI*/0, /*Op*/7,
        // MIs[0] Operand 8
        GIM_CheckLiteralInt, /*MI*/0, /*Op*/8, GIMT_Encode8(0),
        GIM_CheckComplexPattern, /*MI*/0, /*Op*/5, /*Renderer*/GIMT_Encode2(0), GIMT_Encode2(GICP_gi_buf_soffset),
        // (SIbuffer_atomic_cond_sub_u32:{ *:[i32] } i32:{ *:[i32] }:$vdata_in, v4i32:{ *:[v4i32] }:$rsrc, 0:{ *:[i32] }, 0:{ *:[i32] }, (BUFSOffset:{ *:[i32] } i32:{ *:[i32] }:$soffset), (timm:{ *:[i32] }):$offset, (timm:{ *:[i32] }):$auxiliary, 0:{ *:[i1] })  =>  (BUFFER_ATOMIC_COND_SUB_U32_VBUFFER_OFFSET_RTN:{ *:[i32] } anonymous_15037:{ *:[i32] }:$vdata_in, SReg_128:{ *:[v4i32] }:$rsrc, SCSrc_b32:{ *:[i32] }:$soffset, (timm:{ *:[i32] }):$offset, (extract_cpol_set_glc:{ *:[i32] } ?:{ *:[i32] }:$auxiliary))
        GIR_BuildMI, /*InsnID*/0, /*Opcode*/GIMT_Encode2(AMDGPU::BUFFER_ATOMIC_COND_SUB_U32_VBUFFER_OFFSET_RTN),
        GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/0, // DstI[vdata]
        GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/1, // vdata_in
        GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/2, // rsrc
        GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/0, // soffset
        GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/6, // offset
        GIR_CustomOperandRenderer, /*InsnID*/0, /*OldInsnID*/0, /*OpIdx*/7, /*OperandRenderer*/GIMT_Encode2(GICR_renderExtractCpolSetGLC), // auxiliary
        GIR_MergeMemOperands, /*InsnID*/0, /*NumInsns*/1, /*MergeInsnID's*/0,
        GIR_ConstrainSelectedInstOperands, /*InsnID*/0,
        GIR_EraseFromParent, /*InsnID*/0,
        // GIR_Coverage, 5137,
        GIR_Done,
      // Label 5828: @425462
      GIM_Try, /*On fail goto*//*Label 5829*/ GIMT_Encode4(425540), // Rule ID 5143 //
        GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasAtomicCSubNoRtnInsts_isGFX12Plus),
        GIM_CheckHasNoUse, /*MI*/0,
        GIM_CheckConstantInt8, /*MI*/0, /*Op*/3, 0,
        // MIs[0] offset
        GIM_CheckIsImm, /*MI*/0, /*Op*/6,
        // MIs[0] auxiliary
        GIM_CheckIsImm, /*MI*/0, /*Op*/7,
        // MIs[0] Operand 8
        GIM_CheckLiteralInt, /*MI*/0, /*Op*/8, GIMT_Encode8(0),
        GIM_CheckComplexPattern, /*MI*/0, /*Op*/5, /*Renderer*/GIMT_Encode2(0), GIMT_Encode2(GICP_gi_buf_soffset),
        // (SIbuffer_atomic_cond_sub_u32:{ *:[i32] } i32:{ *:[i32] }:$vdata_in, v4i32:{ *:[v4i32] }:$rsrc, 0:{ *:[i32] }, i32:{ *:[i32] }:$voffset, (BUFSOffset:{ *:[i32] } i32:{ *:[i32] }:$soffset), (timm:{ *:[i32] }):$offset, (timm:{ *:[i32] }):$auxiliary, 0:{ *:[i1] })<<P:Predicate_SIbuffer_atomic_cond_sub_u32_noret>>  =>  (BUFFER_ATOMIC_COND_SUB_U32_VBUFFER_OFFEN anonymous_15037:{ *:[i32] }:$vdata_in, VGPR_32:{ *:[i32] }:$voffset, SReg_128:{ *:[v4i32] }:$rsrc, SCSrc_b32:{ *:[i32] }:$soffset, (timm:{ *:[i32] }):$offset, (extract_cpol:{ *:[i32] } ?:{ *:[i32] }:$auxiliary))
        GIR_BuildMI, /*InsnID*/0, /*Opcode*/GIMT_Encode2(AMDGPU::BUFFER_ATOMIC_COND_SUB_U32_VBUFFER_OFFEN),
        GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/1, // vdata_in
        GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/4, // voffset
        GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/2, // rsrc
        GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/0, // soffset
        GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/6, // offset
        GIR_CustomOperandRenderer, /*InsnID*/0, /*OldInsnID*/0, /*OpIdx*/7, /*OperandRenderer*/GIMT_Encode2(GICR_renderExtractCPol), // auxiliary
        GIR_MergeMemOperands, /*InsnID*/0, /*NumInsns*/1, /*MergeInsnID's*/0,
        GIR_ConstrainSelectedInstOperands, /*InsnID*/0,
        GIR_EraseFromParent, /*InsnID*/0,
        // GIR_Coverage, 5143,
        GIR_Done,
      // Label 5829: @425540
      GIM_Try, /*On fail goto*//*Label 5830*/ GIMT_Encode4(425625), // Rule ID 5139 //
        GIM_CheckFeatures, GIMT_Encode2(GIFBS_isGFX12Plus),
        GIM_CheckRegBankForClass, /*MI*/0, /*Op*/0, /*RC*/GIMT_Encode2(AMDGPU::AV_32RegClassID),
        GIM_CheckConstantInt8, /*MI*/0, /*Op*/3, 0,
        // MIs[0] offset
        GIM_CheckIsImm, /*MI*/0, /*Op*/6,
        // MIs[0] auxiliary
        GIM_CheckIsImm, /*MI*/0, /*Op*/7,
        // MIs[0] Operand 8
        GIM_CheckLiteralInt, /*MI*/0, /*Op*/8, GIMT_Encode8(0),
        GIM_CheckComplexPattern, /*MI*/0, /*Op*/5, /*Renderer*/GIMT_Encode2(0), GIMT_Encode2(GICP_gi_buf_soffset),
        // (SIbuffer_atomic_cond_sub_u32:{ *:[i32] } i32:{ *:[i32] }:$vdata_in, v4i32:{ *:[v4i32] }:$rsrc, 0:{ *:[i32] }, i32:{ *:[i32] }:$voffset, (BUFSOffset:{ *:[i32] } i32:{ *:[i32] }:$soffset), (timm:{ *:[i32] }):$offset, (timm:{ *:[i32] }):$auxiliary, 0:{ *:[i1] })  =>  (BUFFER_ATOMIC_COND_SUB_U32_VBUFFER_OFFEN_RTN:{ *:[i32] } anonymous_15037:{ *:[i32] }:$vdata_in, VGPR_32:{ *:[i32] }:$voffset, SReg_128:{ *:[v4i32] }:$rsrc, SCSrc_b32:{ *:[i32] }:$soffset, (timm:{ *:[i32] }):$offset, (extract_cpol_set_glc:{ *:[i32] } ?:{ *:[i32] }:$auxiliary))
        GIR_BuildMI, /*InsnID*/0, /*Opcode*/GIMT_Encode2(AMDGPU::BUFFER_ATOMIC_COND_SUB_U32_VBUFFER_OFFEN_RTN),
        GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/0, // DstI[vdata]
        GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/1, // vdata_in
        GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/4, // voffset
        GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/2, // rsrc
        GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/0, // soffset
        GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/6, // offset
        GIR_CustomOperandRenderer, /*InsnID*/0, /*OldInsnID*/0, /*OpIdx*/7, /*OperandRenderer*/GIMT_Encode2(GICR_renderExtractCpolSetGLC), // auxiliary
        GIR_MergeMemOperands, /*InsnID*/0, /*NumInsns*/1, /*MergeInsnID's*/0,
        GIR_ConstrainSelectedInstOperands, /*InsnID*/0,
        GIR_EraseFromParent, /*InsnID*/0,
        // GIR_Coverage, 5139,
        GIR_Done,
      // Label 5830: @425625
      GIM_Try, /*On fail goto*//*Label 5831*/ GIMT_Encode4(425695), // Rule ID 5142 //
        GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasAtomicCSubNoRtnInsts_isGFX12Plus),
        GIM_CheckHasNoUse, /*MI*/0,
        GIM_CheckConstantInt8, /*MI*/0, /*Op*/4, 0,
        // MIs[0] offset
        GIM_CheckIsImm, /*MI*/0, /*Op*/6,
        // MIs[0] auxiliary
        GIM_CheckIsImm, /*MI*/0, /*Op*/7,
        // MIs[0] Operand 8
        GIM_CheckIsImm, /*MI*/0, /*Op*/8,
        GIM_CheckComplexPattern, /*MI*/0, /*Op*/5, /*Renderer*/GIMT_Encode2(0), GIMT_Encode2(GICP_gi_buf_soffset),
        // (SIbuffer_atomic_cond_sub_u32:{ *:[i32] } i32:{ *:[i32] }:$vdata_in, v4i32:{ *:[v4i32] }:$rsrc, i32:{ *:[i32] }:$vindex, 0:{ *:[i32] }, (BUFSOffset:{ *:[i32] } i32:{ *:[i32] }:$soffset), (timm:{ *:[i32] }):$offset, (timm:{ *:[i32] }):$auxiliary, (timm:{ *:[i1] }))<<P:Predicate_SIbuffer_atomic_cond_sub_u32_noret>>  =>  (BUFFER_ATOMIC_COND_SUB_U32_VBUFFER_IDXEN anonymous_15037:{ *:[i32] }:$vdata_in, VGPR_32:{ *:[i32] }:$vindex, SReg_128:{ *:[v4i32] }:$rsrc, SCSrc_b32:{ *:[i32] }:$soffset, (timm:{ *:[i32] }):$offset, (extract_cpol:{ *:[i32] } ?:{ *:[i32] }:$auxiliary))
        GIR_BuildMI, /*InsnID*/0, /*Opcode*/GIMT_Encode2(AMDGPU::BUFFER_ATOMIC_COND_SUB_U32_VBUFFER_IDXEN),
        GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/1, // vdata_in
        GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/3, // vindex
        GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/2, // rsrc
        GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/0, // soffset
        GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/6, // offset
        GIR_CustomOperandRenderer, /*InsnID*/0, /*OldInsnID*/0, /*OpIdx*/7, /*OperandRenderer*/GIMT_Encode2(GICR_renderExtractCPol), // auxiliary
        GIR_MergeMemOperands, /*InsnID*/0, /*NumInsns*/1, /*MergeInsnID's*/0,
        GIR_ConstrainSelectedInstOperands, /*InsnID*/0,
        GIR_EraseFromParent, /*InsnID*/0,
        // GIR_Coverage, 5142,
        GIR_Done,
      // Label 5831: @425695
      GIM_Try, /*On fail goto*//*Label 5832*/ GIMT_Encode4(425772), // Rule ID 5138 //
        GIM_CheckFeatures, GIMT_Encode2(GIFBS_isGFX12Plus),
        GIM_CheckRegBankForClass, /*MI*/0, /*Op*/0, /*RC*/GIMT_Encode2(AMDGPU::AV_32RegClassID),
        GIM_CheckConstantInt8, /*MI*/0, /*Op*/4, 0,
        // MIs[0] offset
        GIM_CheckIsImm, /*MI*/0, /*Op*/6,
        // MIs[0] auxiliary
        GIM_CheckIsImm, /*MI*/0, /*Op*/7,
        // MIs[0] Operand 8
        GIM_CheckIsImm, /*MI*/0, /*Op*/8,
        GIM_CheckComplexPattern, /*MI*/0, /*Op*/5, /*Renderer*/GIMT_Encode2(0), GIMT_Encode2(GICP_gi_buf_soffset),
        // (SIbuffer_atomic_cond_sub_u32:{ *:[i32] } i32:{ *:[i32] }:$vdata_in, v4i32:{ *:[v4i32] }:$rsrc, i32:{ *:[i32] }:$vindex, 0:{ *:[i32] }, (BUFSOffset:{ *:[i32] } i32:{ *:[i32] }:$soffset), (timm:{ *:[i32] }):$offset, (timm:{ *:[i32] }):$auxiliary, (timm:{ *:[i1] }))  =>  (BUFFER_ATOMIC_COND_SUB_U32_VBUFFER_IDXEN_RTN:{ *:[i32] } anonymous_15037:{ *:[i32] }:$vdata_in, VGPR_32:{ *:[i32] }:$vindex, SReg_128:{ *:[v4i32] }:$rsrc, SCSrc_b32:{ *:[i32] }:$soffset, (timm:{ *:[i32] }):$offset, (extract_cpol_set_glc:{ *:[i32] } ?:{ *:[i32] }:$auxiliary))
        GIR_BuildMI, /*InsnID*/0, /*Opcode*/GIMT_Encode2(AMDGPU::BUFFER_ATOMIC_COND_SUB_U32_VBUFFER_IDXEN_RTN),
        GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/0, // DstI[vdata]
        GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/1, // vdata_in
        GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/3, // vindex
        GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/2, // rsrc
        GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/0, // soffset
        GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/6, // offset
        GIR_CustomOperandRenderer, /*InsnID*/0, /*OldInsnID*/0, /*OpIdx*/7, /*OperandRenderer*/GIMT_Encode2(GICR_renderExtractCpolSetGLC), // auxiliary
        GIR_MergeMemOperands, /*InsnID*/0, /*NumInsns*/1, /*MergeInsnID's*/0,
        GIR_ConstrainSelectedInstOperands, /*InsnID*/0,
        GIR_EraseFromParent, /*InsnID*/0,
        // GIR_Coverage, 5138,
        GIR_Done,
      // Label 5832: @425772
      GIM_Try, /*On fail goto*//*Label 5833*/ GIMT_Encode4(425878), // Rule ID 5144 //
        GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasAtomicCSubNoRtnInsts_isGFX12Plus),
        GIM_CheckHasNoUse, /*MI*/0,
        // MIs[0] offset
        GIM_CheckIsImm, /*MI*/0, /*Op*/6,
        // MIs[0] auxiliary
        GIM_CheckIsImm, /*MI*/0, /*Op*/7,
        // MIs[0] Operand 8
        GIM_CheckIsImm, /*MI*/0, /*Op*/8,
        GIM_CheckComplexPattern, /*MI*/0, /*Op*/5, /*Renderer*/GIMT_Encode2(0), GIMT_Encode2(GICP_gi_buf_soffset),
        // (SIbuffer_atomic_cond_sub_u32:{ *:[i32] } i32:{ *:[i32] }:$vdata_in, v4i32:{ *:[v4i32] }:$rsrc, i32:{ *:[i32] }:$vindex, i32:{ *:[i32] }:$voffset, (BUFSOffset:{ *:[i32] } i32:{ *:[i32] }:$soffset), (timm:{ *:[i32] }):$offset, (timm:{ *:[i32] }):$auxiliary, (timm:{ *:[i1] }))<<P:Predicate_SIbuffer_atomic_cond_sub_u32_noret>>  =>  (BUFFER_ATOMIC_COND_SUB_U32_VBUFFER_BOTHEN anonymous_15037:{ *:[i32] }:$vdata_in, (REG_SEQUENCE:{ *:[i64] } VReg_64:{ *:[i32] }, VGPR_32:{ *:[i32] }:$vindex, sub0:{ *:[i32] }, VGPR_32:{ *:[i32] }:$voffset, sub1:{ *:[i32] }), SReg_128:{ *:[v4i32] }:$rsrc, SCSrc_b32:{ *:[i32] }:$soffset, (timm:{ *:[i32] }):$offset, (extract_cpol:{ *:[i32] } ?:{ *:[i32] }:$auxiliary))
        GIR_MakeTempReg, /*TempRegID*/0, /*TypeID*/GILLT_s64,
        GIR_BuildMI, /*InsnID*/1, /*Opcode*/GIMT_Encode2(TargetOpcode::REG_SEQUENCE),
        GIR_AddTempRegister, /*InsnID*/1, /*TempRegID*/0, /*TempRegFlags*/GIMT_Encode2(RegState::Define),
        GIR_Copy, /*NewInsnID*/1, /*OldInsnID*/0, /*OpIdx*/3, // vindex
        GIR_AddImm8, /*InsnID*/1, /*SubRegIndex*/3,
        GIR_Copy, /*NewInsnID*/1, /*OldInsnID*/0, /*OpIdx*/4, // voffset
        GIR_AddImm8, /*InsnID*/1, /*SubRegIndex*/11,
        GIR_ConstrainOperandRC, /*InsnID*/1, /*Op*/0, GIMT_Encode2(AMDGPU::VReg_64RegClassID),
        GIR_ConstrainOperandRC, /*InsnID*/1, /*Op*/1, GIMT_Encode2(AMDGPU::VGPR_32RegClassID),
        GIR_ConstrainOperandRC, /*InsnID*/1, /*Op*/3, GIMT_Encode2(AMDGPU::VGPR_32RegClassID),
        GIR_BuildMI, /*InsnID*/0, /*Opcode*/GIMT_Encode2(AMDGPU::BUFFER_ATOMIC_COND_SUB_U32_VBUFFER_BOTHEN),
        GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/1, // vdata_in
        GIR_AddSimpleTempRegister, /*InsnID*/0, /*TempRegID*/0,
        GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/2, // rsrc
        GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/0, // soffset
        GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/6, // offset
        GIR_CustomOperandRenderer, /*InsnID*/0, /*OldInsnID*/0, /*OpIdx*/7, /*OperandRenderer*/GIMT_Encode2(GICR_renderExtractCPol), // auxiliary
        GIR_MergeMemOperands, /*InsnID*/0, /*NumInsns*/1, /*MergeInsnID's*/0,
        GIR_ConstrainSelectedInstOperands, /*InsnID*/0,
        GIR_EraseFromParent, /*InsnID*/0,
        // GIR_Coverage, 5144,
        GIR_Done,
      // Label 5833: @425878
      GIM_Try, /*On fail goto*//*Label 5834*/ GIMT_Encode4(425991), // Rule ID 5140 //
        GIM_CheckFeatures, GIMT_Encode2(GIFBS_isGFX12Plus),
        GIM_CheckRegBankForClass, /*MI*/0, /*Op*/0, /*RC*/GIMT_Encode2(AMDGPU::AV_32RegClassID),
        // MIs[0] offset
        GIM_CheckIsImm, /*MI*/0, /*Op*/6,
        // MIs[0] auxiliary
        GIM_CheckIsImm, /*MI*/0, /*Op*/7,
        // MIs[0] Operand 8
        GIM_CheckIsImm, /*MI*/0, /*Op*/8,
        GIM_CheckComplexPattern, /*MI*/0, /*Op*/5, /*Renderer*/GIMT_Encode2(0), GIMT_Encode2(GICP_gi_buf_soffset),
        // (SIbuffer_atomic_cond_sub_u32:{ *:[i32] } i32:{ *:[i32] }:$vdata_in, v4i32:{ *:[v4i32] }:$rsrc, i32:{ *:[i32] }:$vindex, i32:{ *:[i32] }:$voffset, (BUFSOffset:{ *:[i32] } i32:{ *:[i32] }:$soffset), (timm:{ *:[i32] }):$offset, (timm:{ *:[i32] }):$auxiliary, (timm:{ *:[i1] }))  =>  (BUFFER_ATOMIC_COND_SUB_U32_VBUFFER_BOTHEN_RTN:{ *:[i32] } anonymous_15037:{ *:[i32] }:$vdata_in, (REG_SEQUENCE:{ *:[i64] } VReg_64:{ *:[i32] }, VGPR_32:{ *:[i32] }:$vindex, sub0:{ *:[i32] }, VGPR_32:{ *:[i32] }:$voffset, sub1:{ *:[i32] }), SReg_128:{ *:[v4i32] }:$rsrc, SCSrc_b32:{ *:[i32] }:$soffset, (timm:{ *:[i32] }):$offset, (extract_cpol_set_glc:{ *:[i32] } ?:{ *:[i32] }:$auxiliary))
        GIR_MakeTempReg, /*TempRegID*/0, /*TypeID*/GILLT_s64,
        GIR_BuildMI, /*InsnID*/1, /*Opcode*/GIMT_Encode2(TargetOpcode::REG_SEQUENCE),
        GIR_AddTempRegister, /*InsnID*/1, /*TempRegID*/0, /*TempRegFlags*/GIMT_Encode2(RegState::Define),
        GIR_Copy, /*NewInsnID*/1, /*OldInsnID*/0, /*OpIdx*/3, // vindex
        GIR_AddImm8, /*InsnID*/1, /*SubRegIndex*/3,
        GIR_Copy, /*NewInsnID*/1, /*OldInsnID*/0, /*OpIdx*/4, // voffset
        GIR_AddImm8, /*InsnID*/1, /*SubRegIndex*/11,
        GIR_ConstrainOperandRC, /*InsnID*/1, /*Op*/0, GIMT_Encode2(AMDGPU::VReg_64RegClassID),
        GIR_ConstrainOperandRC, /*InsnID*/1, /*Op*/1, GIMT_Encode2(AMDGPU::VGPR_32RegClassID),
        GIR_ConstrainOperandRC, /*InsnID*/1, /*Op*/3, GIMT_Encode2(AMDGPU::VGPR_32RegClassID),
        GIR_BuildMI, /*InsnID*/0, /*Opcode*/GIMT_Encode2(AMDGPU::BUFFER_ATOMIC_COND_SUB_U32_VBUFFER_BOTHEN_RTN),
        GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/0, // DstI[vdata]
        GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/1, // vdata_in
        GIR_AddSimpleTempRegister, /*InsnID*/0, /*TempRegID*/0,
        GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/2, // rsrc
        GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/0, // soffset
        GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/6, // offset
        GIR_CustomOperandRenderer, /*InsnID*/0, /*OldInsnID*/0, /*OpIdx*/7, /*OperandRenderer*/GIMT_Encode2(GICR_renderExtractCpolSetGLC), // auxiliary
        GIR_MergeMemOperands, /*InsnID*/0, /*NumInsns*/1, /*MergeInsnID's*/0,
        GIR_ConstrainSelectedInstOperands, /*InsnID*/0,
        GIR_EraseFromParent, /*InsnID*/0,
        // GIR_Coverage, 5140,
        GIR_Done,
      // Label 5834: @425991
      GIM_Reject,
    // Label 5826: @425992
    GIM_Reject,
    // Label 110: @425993
    GIM_SwitchType, /*MI*/0, /*Op*/0, /*[*/GIMT_Encode2(9), GIMT_Encode2(11), /*)*//*default:*//*Label 5837*/ GIMT_Encode4(428786),
    /*GILLT_s32*//*Label 5835*/ GIMT_Encode4(426012),
    /*GILLT_s64*//*Label 5836*/ GIMT_Encode4(427399),
    // Label 5835: @426012
    GIM_Try, /*On fail goto*//*Label 5838*/ GIMT_Encode4(427398),
      GIM_CheckType, /*MI*/0, /*Op*/1, /*Type*/GILLT_s32,
      GIM_CheckType, /*MI*/0, /*Op*/2, /*Type*/GILLT_v4s32,
      GIM_CheckType, /*MI*/0, /*Op*/3, /*Type*/GILLT_s32,
      GIM_CheckType, /*MI*/0, /*Op*/4, /*Type*/GILLT_s32,
      GIM_CheckType, /*MI*/0, /*Op*/5, /*Type*/GILLT_s32,
      GIM_Try, /*On fail goto*//*Label 5839*/ GIMT_Encode4(426115), // Rule ID 4909 //
        GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasUnrestrictedSOffset),
        GIM_CheckHasNoUse, /*MI*/0,
        GIM_CheckConstantInt8, /*MI*/0, /*Op*/3, 0,
        GIM_CheckConstantInt8, /*MI*/0, /*Op*/4, 0,
        // MIs[0] offset
        GIM_CheckIsImm, /*MI*/0, /*Op*/6,
        // MIs[0] auxiliary
        GIM_CheckIsImm, /*MI*/0, /*Op*/7,
        // MIs[0] Operand 8
        GIM_CheckLiteralInt, /*MI*/0, /*Op*/8, GIMT_Encode8(0),
        GIM_CheckComplexPattern, /*MI*/0, /*Op*/5, /*Renderer*/GIMT_Encode2(0), GIMT_Encode2(GICP_gi_buf_soffset),
        // (SIbuffer_atomic_dec:{ *:[i32] } i32:{ *:[i32] }:$vdata_in, v4i32:{ *:[v4i32] }:$rsrc, 0:{ *:[i32] }, 0:{ *:[i32] }, (BUFSOffset:{ *:[i32] } i32:{ *:[i32] }:$soffset), (timm:{ *:[i32] }):$offset, (timm:{ *:[i32] }):$auxiliary, 0:{ *:[i1] })<<P:Predicate_SIbuffer_atomic_dec_noret>>  =>  (BUFFER_ATOMIC_DEC_OFFSET anonymous_15037:{ *:[i32] }:$vdata_in, SReg_128:{ *:[v4i32] }:$rsrc, SCSrc_b32:{ *:[i32] }:$soffset, (timm:{ *:[i32] }):$offset, (extract_cpol:{ *:[i32] } ?:{ *:[i32] }:$auxiliary))
        GIR_BuildMI, /*InsnID*/0, /*Opcode*/GIMT_Encode2(AMDGPU::BUFFER_ATOMIC_DEC_OFFSET),
        GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/1, // vdata_in
        GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/2, // rsrc
        GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/0, // soffset
        GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/6, // offset
        GIR_CustomOperandRenderer, /*InsnID*/0, /*OldInsnID*/0, /*OpIdx*/7, /*OperandRenderer*/GIMT_Encode2(GICR_renderExtractCPol), // auxiliary
        GIR_MergeMemOperands, /*InsnID*/0, /*NumInsns*/1, /*MergeInsnID's*/0,
        GIR_ConstrainSelectedInstOperands, /*InsnID*/0,
        GIR_EraseFromParent, /*InsnID*/0,
        // GIR_Coverage, 4909,
        GIR_Done,
      // Label 5839: @426115
      GIM_Try, /*On fail goto*//*Label 5840*/ GIMT_Encode4(426190), // Rule ID 4917 //
        GIM_CheckHasNoUse, /*MI*/0,
        GIM_CheckConstantInt8, /*MI*/0, /*Op*/3, 0,
        GIM_CheckConstantInt8, /*MI*/0, /*Op*/4, 0,
        // MIs[0] offset
        GIM_CheckIsImm, /*MI*/0, /*Op*/6,
        // MIs[0] auxiliary
        GIM_CheckIsImm, /*MI*/0, /*Op*/7,
        // MIs[0] Operand 8
        GIM_CheckLiteralInt, /*MI*/0, /*Op*/8, GIMT_Encode8(0),
        GIM_CheckComplexPattern, /*MI*/0, /*Op*/5, /*Renderer*/GIMT_Encode2(0), GIMT_Encode2(GICP_gi_buf_soffset),
        // (SIbuffer_atomic_dec:{ *:[i32] } i32:{ *:[i32] }:$vdata_in, v4i32:{ *:[v4i32] }:$rsrc, 0:{ *:[i32] }, 0:{ *:[i32] }, (BUFSOffset:{ *:[i32] } i32:{ *:[i32] }:$soffset), (timm:{ *:[i32] }):$offset, (timm:{ *:[i32] }):$auxiliary, 0:{ *:[i1] })<<P:Predicate_SIbuffer_atomic_dec_noret>>  =>  (BUFFER_ATOMIC_DEC_VBUFFER_OFFSET anonymous_15037:{ *:[i32] }:$vdata_in, SReg_128:{ *:[v4i32] }:$rsrc, SCSrc_b32:{ *:[i32] }:$soffset, (timm:{ *:[i32] }):$offset, (extract_cpol:{ *:[i32] } ?:{ *:[i32] }:$auxiliary))
        GIR_BuildMI, /*InsnID*/0, /*Opcode*/GIMT_Encode2(AMDGPU::BUFFER_ATOMIC_DEC_VBUFFER_OFFSET),
        GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/1, // vdata_in
        GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/2, // rsrc
        GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/0, // soffset
        GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/6, // offset
        GIR_CustomOperandRenderer, /*InsnID*/0, /*OldInsnID*/0, /*OpIdx*/7, /*OperandRenderer*/GIMT_Encode2(GICR_renderExtractCPol), // auxiliary
        GIR_MergeMemOperands, /*InsnID*/0, /*NumInsns*/1, /*MergeInsnID's*/0,
        GIR_ConstrainSelectedInstOperands, /*InsnID*/0,
        GIR_EraseFromParent, /*InsnID*/0,
        // GIR_Coverage, 4917,
        GIR_Done,
      // Label 5840: @426190
      GIM_Try, /*On fail goto*//*Label 5841*/ GIMT_Encode4(426275), // Rule ID 4905 //
        GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasUnrestrictedSOffset),
        GIM_CheckRegBankForClass, /*MI*/0, /*Op*/0, /*RC*/GIMT_Encode2(AMDGPU::AV_32RegClassID),
        GIM_CheckConstantInt8, /*MI*/0, /*Op*/3, 0,
        GIM_CheckConstantInt8, /*MI*/0, /*Op*/4, 0,
        // MIs[0] offset
        GIM_CheckIsImm, /*MI*/0, /*Op*/6,
        // MIs[0] auxiliary
        GIM_CheckIsImm, /*MI*/0, /*Op*/7,
        // MIs[0] Operand 8
        GIM_CheckLiteralInt, /*MI*/0, /*Op*/8, GIMT_Encode8(0),
        GIM_CheckComplexPattern, /*MI*/0, /*Op*/5, /*Renderer*/GIMT_Encode2(0), GIMT_Encode2(GICP_gi_buf_soffset),
        // (SIbuffer_atomic_dec:{ *:[i32] } i32:{ *:[i32] }:$vdata_in, v4i32:{ *:[v4i32] }:$rsrc, 0:{ *:[i32] }, 0:{ *:[i32] }, (BUFSOffset:{ *:[i32] } i32:{ *:[i32] }:$soffset), (timm:{ *:[i32] }):$offset, (timm:{ *:[i32] }):$auxiliary, 0:{ *:[i1] })  =>  (BUFFER_ATOMIC_DEC_OFFSET_RTN:{ *:[i32] } anonymous_15037:{ *:[i32] }:$vdata_in, SReg_128:{ *:[v4i32] }:$rsrc, SCSrc_b32:{ *:[i32] }:$soffset, (timm:{ *:[i32] }):$offset, (extract_cpol_set_glc:{ *:[i32] } ?:{ *:[i32] }:$auxiliary))
        GIR_BuildMI, /*InsnID*/0, /*Opcode*/GIMT_Encode2(AMDGPU::BUFFER_ATOMIC_DEC_OFFSET_RTN),
        GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/0, // DstI[vdata]
        GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/1, // vdata_in
        GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/2, // rsrc
        GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/0, // soffset
        GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/6, // offset
        GIR_CustomOperandRenderer, /*InsnID*/0, /*OldInsnID*/0, /*OpIdx*/7, /*OperandRenderer*/GIMT_Encode2(GICR_renderExtractCpolSetGLC), // auxiliary
        GIR_MergeMemOperands, /*InsnID*/0, /*NumInsns*/1, /*MergeInsnID's*/0,
        GIR_ConstrainSelectedInstOperands, /*InsnID*/0,
        GIR_EraseFromParent, /*InsnID*/0,
        // GIR_Coverage, 4905,
        GIR_Done,
      // Label 5841: @426275
      GIM_Try, /*On fail goto*//*Label 5842*/ GIMT_Encode4(426357), // Rule ID 4913 //
        GIM_CheckRegBankForClass, /*MI*/0, /*Op*/0, /*RC*/GIMT_Encode2(AMDGPU::AV_32RegClassID),
        GIM_CheckConstantInt8, /*MI*/0, /*Op*/3, 0,
        GIM_CheckConstantInt8, /*MI*/0, /*Op*/4, 0,
        // MIs[0] offset
        GIM_CheckIsImm, /*MI*/0, /*Op*/6,
        // MIs[0] auxiliary
        GIM_CheckIsImm, /*MI*/0, /*Op*/7,
        // MIs[0] Operand 8
        GIM_CheckLiteralInt, /*MI*/0, /*Op*/8, GIMT_Encode8(0),
        GIM_CheckComplexPattern, /*MI*/0, /*Op*/5, /*Renderer*/GIMT_Encode2(0), GIMT_Encode2(GICP_gi_buf_soffset),
        // (SIbuffer_atomic_dec:{ *:[i32] } i32:{ *:[i32] }:$vdata_in, v4i32:{ *:[v4i32] }:$rsrc, 0:{ *:[i32] }, 0:{ *:[i32] }, (BUFSOffset:{ *:[i32] } i32:{ *:[i32] }:$soffset), (timm:{ *:[i32] }):$offset, (timm:{ *:[i32] }):$auxiliary, 0:{ *:[i1] })  =>  (BUFFER_ATOMIC_DEC_VBUFFER_OFFSET_RTN:{ *:[i32] } anonymous_15037:{ *:[i32] }:$vdata_in, SReg_128:{ *:[v4i32] }:$rsrc, SCSrc_b32:{ *:[i32] }:$soffset, (timm:{ *:[i32] }):$offset, (extract_cpol_set_glc:{ *:[i32] } ?:{ *:[i32] }:$auxiliary))
        GIR_BuildMI, /*InsnID*/0, /*Opcode*/GIMT_Encode2(AMDGPU::BUFFER_ATOMIC_DEC_VBUFFER_OFFSET_RTN),
        GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/0, // DstI[vdata]
        GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/1, // vdata_in
        GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/2, // rsrc
        GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/0, // soffset
        GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/6, // offset
        GIR_CustomOperandRenderer, /*InsnID*/0, /*OldInsnID*/0, /*OpIdx*/7, /*OperandRenderer*/GIMT_Encode2(GICR_renderExtractCpolSetGLC), // auxiliary
        GIR_MergeMemOperands, /*InsnID*/0, /*NumInsns*/1, /*MergeInsnID's*/0,
        GIR_ConstrainSelectedInstOperands, /*InsnID*/0,
        GIR_EraseFromParent, /*InsnID*/0,
        // GIR_Coverage, 4913,
        GIR_Done,
      // Label 5842: @426357
      GIM_Try, /*On fail goto*//*Label 5843*/ GIMT_Encode4(426435), // Rule ID 4911 //
        GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasUnrestrictedSOffset),
        GIM_CheckHasNoUse, /*MI*/0,
        GIM_CheckConstantInt8, /*MI*/0, /*Op*/3, 0,
        // MIs[0] offset
        GIM_CheckIsImm, /*MI*/0, /*Op*/6,
        // MIs[0] auxiliary
        GIM_CheckIsImm, /*MI*/0, /*Op*/7,
        // MIs[0] Operand 8
        GIM_CheckLiteralInt, /*MI*/0, /*Op*/8, GIMT_Encode8(0),
        GIM_CheckComplexPattern, /*MI*/0, /*Op*/5, /*Renderer*/GIMT_Encode2(0), GIMT_Encode2(GICP_gi_buf_soffset),
        // (SIbuffer_atomic_dec:{ *:[i32] } i32:{ *:[i32] }:$vdata_in, v4i32:{ *:[v4i32] }:$rsrc, 0:{ *:[i32] }, i32:{ *:[i32] }:$voffset, (BUFSOffset:{ *:[i32] } i32:{ *:[i32] }:$soffset), (timm:{ *:[i32] }):$offset, (timm:{ *:[i32] }):$auxiliary, 0:{ *:[i1] })<<P:Predicate_SIbuffer_atomic_dec_noret>>  =>  (BUFFER_ATOMIC_DEC_OFFEN anonymous_15037:{ *:[i32] }:$vdata_in, VGPR_32:{ *:[i32] }:$voffset, SReg_128:{ *:[v4i32] }:$rsrc, SCSrc_b32:{ *:[i32] }:$soffset, (timm:{ *:[i32] }):$offset, (extract_cpol:{ *:[i32] } ?:{ *:[i32] }:$auxiliary))
        GIR_BuildMI, /*InsnID*/0, /*Opcode*/GIMT_Encode2(AMDGPU::BUFFER_ATOMIC_DEC_OFFEN),
        GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/1, // vdata_in
        GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/4, // voffset
        GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/2, // rsrc
        GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/0, // soffset
        GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/6, // offset
        GIR_CustomOperandRenderer, /*InsnID*/0, /*OldInsnID*/0, /*OpIdx*/7, /*OperandRenderer*/GIMT_Encode2(GICR_renderExtractCPol), // auxiliary
        GIR_MergeMemOperands, /*InsnID*/0, /*NumInsns*/1, /*MergeInsnID's*/0,
        GIR_ConstrainSelectedInstOperands, /*InsnID*/0,
        GIR_EraseFromParent, /*InsnID*/0,
        // GIR_Coverage, 4911,
        GIR_Done,
      // Label 5843: @426435
      GIM_Try, /*On fail goto*//*Label 5844*/ GIMT_Encode4(426510), // Rule ID 4919 //
        GIM_CheckHasNoUse, /*MI*/0,
        GIM_CheckConstantInt8, /*MI*/0, /*Op*/3, 0,
        // MIs[0] offset
        GIM_CheckIsImm, /*MI*/0, /*Op*/6,
        // MIs[0] auxiliary
        GIM_CheckIsImm, /*MI*/0, /*Op*/7,
        // MIs[0] Operand 8
        GIM_CheckLiteralInt, /*MI*/0, /*Op*/8, GIMT_Encode8(0),
        GIM_CheckComplexPattern, /*MI*/0, /*Op*/5, /*Renderer*/GIMT_Encode2(0), GIMT_Encode2(GICP_gi_buf_soffset),
        // (SIbuffer_atomic_dec:{ *:[i32] } i32:{ *:[i32] }:$vdata_in, v4i32:{ *:[v4i32] }:$rsrc, 0:{ *:[i32] }, i32:{ *:[i32] }:$voffset, (BUFSOffset:{ *:[i32] } i32:{ *:[i32] }:$soffset), (timm:{ *:[i32] }):$offset, (timm:{ *:[i32] }):$auxiliary, 0:{ *:[i1] })<<P:Predicate_SIbuffer_atomic_dec_noret>>  =>  (BUFFER_ATOMIC_DEC_VBUFFER_OFFEN anonymous_15037:{ *:[i32] }:$vdata_in, VGPR_32:{ *:[i32] }:$voffset, SReg_128:{ *:[v4i32] }:$rsrc, SCSrc_b32:{ *:[i32] }:$soffset, (timm:{ *:[i32] }):$offset, (extract_cpol:{ *:[i32] } ?:{ *:[i32] }:$auxiliary))
        GIR_BuildMI, /*InsnID*/0, /*Opcode*/GIMT_Encode2(AMDGPU::BUFFER_ATOMIC_DEC_VBUFFER_OFFEN),
        GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/1, // vdata_in
        GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/4, // voffset
        GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/2, // rsrc
        GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/0, // soffset
        GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/6, // offset
        GIR_CustomOperandRenderer, /*InsnID*/0, /*OldInsnID*/0, /*OpIdx*/7, /*OperandRenderer*/GIMT_Encode2(GICR_renderExtractCPol), // auxiliary
        GIR_MergeMemOperands, /*InsnID*/0, /*NumInsns*/1, /*MergeInsnID's*/0,
        GIR_ConstrainSelectedInstOperands, /*InsnID*/0,
        GIR_EraseFromParent, /*InsnID*/0,
        // GIR_Coverage, 4919,
        GIR_Done,
      // Label 5844: @426510
      GIM_Try, /*On fail goto*//*Label 5845*/ GIMT_Encode4(426595), // Rule ID 4907 //
        GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasUnrestrictedSOffset),
        GIM_CheckRegBankForClass, /*MI*/0, /*Op*/0, /*RC*/GIMT_Encode2(AMDGPU::AV_32RegClassID),
        GIM_CheckConstantInt8, /*MI*/0, /*Op*/3, 0,
        // MIs[0] offset
        GIM_CheckIsImm, /*MI*/0, /*Op*/6,
        // MIs[0] auxiliary
        GIM_CheckIsImm, /*MI*/0, /*Op*/7,
        // MIs[0] Operand 8
        GIM_CheckLiteralInt, /*MI*/0, /*Op*/8, GIMT_Encode8(0),
        GIM_CheckComplexPattern, /*MI*/0, /*Op*/5, /*Renderer*/GIMT_Encode2(0), GIMT_Encode2(GICP_gi_buf_soffset),
        // (SIbuffer_atomic_dec:{ *:[i32] } i32:{ *:[i32] }:$vdata_in, v4i32:{ *:[v4i32] }:$rsrc, 0:{ *:[i32] }, i32:{ *:[i32] }:$voffset, (BUFSOffset:{ *:[i32] } i32:{ *:[i32] }:$soffset), (timm:{ *:[i32] }):$offset, (timm:{ *:[i32] }):$auxiliary, 0:{ *:[i1] })  =>  (BUFFER_ATOMIC_DEC_OFFEN_RTN:{ *:[i32] } anonymous_15037:{ *:[i32] }:$vdata_in, VGPR_32:{ *:[i32] }:$voffset, SReg_128:{ *:[v4i32] }:$rsrc, SCSrc_b32:{ *:[i32] }:$soffset, (timm:{ *:[i32] }):$offset, (extract_cpol_set_glc:{ *:[i32] } ?:{ *:[i32] }:$auxiliary))
        GIR_BuildMI, /*InsnID*/0, /*Opcode*/GIMT_Encode2(AMDGPU::BUFFER_ATOMIC_DEC_OFFEN_RTN),
        GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/0, // DstI[vdata]
        GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/1, // vdata_in
        GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/4, // voffset
        GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/2, // rsrc
        GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/0, // soffset
        GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/6, // offset
        GIR_CustomOperandRenderer, /*InsnID*/0, /*OldInsnID*/0, /*OpIdx*/7, /*OperandRenderer*/GIMT_Encode2(GICR_renderExtractCpolSetGLC), // auxiliary
        GIR_MergeMemOperands, /*InsnID*/0, /*NumInsns*/1, /*MergeInsnID's*/0,
        GIR_ConstrainSelectedInstOperands, /*InsnID*/0,
        GIR_EraseFromParent, /*InsnID*/0,
        // GIR_Coverage, 4907,
        GIR_Done,
      // Label 5845: @426595
      GIM_Try, /*On fail goto*//*Label 5846*/ GIMT_Encode4(426677), // Rule ID 4915 //
        GIM_CheckRegBankForClass, /*MI*/0, /*Op*/0, /*RC*/GIMT_Encode2(AMDGPU::AV_32RegClassID),
        GIM_CheckConstantInt8, /*MI*/0, /*Op*/3, 0,
        // MIs[0] offset
        GIM_CheckIsImm, /*MI*/0, /*Op*/6,
        // MIs[0] auxiliary
        GIM_CheckIsImm, /*MI*/0, /*Op*/7,
        // MIs[0] Operand 8
        GIM_CheckLiteralInt, /*MI*/0, /*Op*/8, GIMT_Encode8(0),
        GIM_CheckComplexPattern, /*MI*/0, /*Op*/5, /*Renderer*/GIMT_Encode2(0), GIMT_Encode2(GICP_gi_buf_soffset),
        // (SIbuffer_atomic_dec:{ *:[i32] } i32:{ *:[i32] }:$vdata_in, v4i32:{ *:[v4i32] }:$rsrc, 0:{ *:[i32] }, i32:{ *:[i32] }:$voffset, (BUFSOffset:{ *:[i32] } i32:{ *:[i32] }:$soffset), (timm:{ *:[i32] }):$offset, (timm:{ *:[i32] }):$auxiliary, 0:{ *:[i1] })  =>  (BUFFER_ATOMIC_DEC_VBUFFER_OFFEN_RTN:{ *:[i32] } anonymous_15037:{ *:[i32] }:$vdata_in, VGPR_32:{ *:[i32] }:$voffset, SReg_128:{ *:[v4i32] }:$rsrc, SCSrc_b32:{ *:[i32] }:$soffset, (timm:{ *:[i32] }):$offset, (extract_cpol_set_glc:{ *:[i32] } ?:{ *:[i32] }:$auxiliary))
        GIR_BuildMI, /*InsnID*/0, /*Opcode*/GIMT_Encode2(AMDGPU::BUFFER_ATOMIC_DEC_VBUFFER_OFFEN_RTN),
        GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/0, // DstI[vdata]
        GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/1, // vdata_in
        GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/4, // voffset
        GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/2, // rsrc
        GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/0, // soffset
        GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/6, // offset
        GIR_CustomOperandRenderer, /*InsnID*/0, /*OldInsnID*/0, /*OpIdx*/7, /*OperandRenderer*/GIMT_Encode2(GICR_renderExtractCpolSetGLC), // auxiliary
        GIR_MergeMemOperands, /*InsnID*/0, /*NumInsns*/1, /*MergeInsnID's*/0,
        GIR_ConstrainSelectedInstOperands, /*InsnID*/0,
        GIR_EraseFromParent, /*InsnID*/0,
        // GIR_Coverage, 4915,
        GIR_Done,
      // Label 5846: @426677
      GIM_Try, /*On fail goto*//*Label 5847*/ GIMT_Encode4(426747), // Rule ID 4910 //
        GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasUnrestrictedSOffset),
        GIM_CheckHasNoUse, /*MI*/0,
        GIM_CheckConstantInt8, /*MI*/0, /*Op*/4, 0,
        // MIs[0] offset
        GIM_CheckIsImm, /*MI*/0, /*Op*/6,
        // MIs[0] auxiliary
        GIM_CheckIsImm, /*MI*/0, /*Op*/7,
        // MIs[0] Operand 8
        GIM_CheckIsImm, /*MI*/0, /*Op*/8,
        GIM_CheckComplexPattern, /*MI*/0, /*Op*/5, /*Renderer*/GIMT_Encode2(0), GIMT_Encode2(GICP_gi_buf_soffset),
        // (SIbuffer_atomic_dec:{ *:[i32] } i32:{ *:[i32] }:$vdata_in, v4i32:{ *:[v4i32] }:$rsrc, i32:{ *:[i32] }:$vindex, 0:{ *:[i32] }, (BUFSOffset:{ *:[i32] } i32:{ *:[i32] }:$soffset), (timm:{ *:[i32] }):$offset, (timm:{ *:[i32] }):$auxiliary, (timm:{ *:[i1] }))<<P:Predicate_SIbuffer_atomic_dec_noret>>  =>  (BUFFER_ATOMIC_DEC_IDXEN anonymous_15037:{ *:[i32] }:$vdata_in, VGPR_32:{ *:[i32] }:$vindex, SReg_128:{ *:[v4i32] }:$rsrc, SCSrc_b32:{ *:[i32] }:$soffset, (timm:{ *:[i32] }):$offset, (extract_cpol:{ *:[i32] } ?:{ *:[i32] }:$auxiliary))
        GIR_BuildMI, /*InsnID*/0, /*Opcode*/GIMT_Encode2(AMDGPU::BUFFER_ATOMIC_DEC_IDXEN),
        GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/1, // vdata_in
        GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/3, // vindex
        GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/2, // rsrc
        GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/0, // soffset
        GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/6, // offset
        GIR_CustomOperandRenderer, /*InsnID*/0, /*OldInsnID*/0, /*OpIdx*/7, /*OperandRenderer*/GIMT_Encode2(GICR_renderExtractCPol), // auxiliary
        GIR_MergeMemOperands, /*InsnID*/0, /*NumInsns*/1, /*MergeInsnID's*/0,
        GIR_ConstrainSelectedInstOperands, /*InsnID*/0,
        GIR_EraseFromParent, /*InsnID*/0,
        // GIR_Coverage, 4910,
        GIR_Done,
      // Label 5847: @426747
      GIM_Try, /*On fail goto*//*Label 5848*/ GIMT_Encode4(426814), // Rule ID 4918 //
        GIM_CheckHasNoUse, /*MI*/0,
        GIM_CheckConstantInt8, /*MI*/0, /*Op*/4, 0,
        // MIs[0] offset
        GIM_CheckIsImm, /*MI*/0, /*Op*/6,
        // MIs[0] auxiliary
        GIM_CheckIsImm, /*MI*/0, /*Op*/7,
        // MIs[0] Operand 8
        GIM_CheckIsImm, /*MI*/0, /*Op*/8,
        GIM_CheckComplexPattern, /*MI*/0, /*Op*/5, /*Renderer*/GIMT_Encode2(0), GIMT_Encode2(GICP_gi_buf_soffset),
        // (SIbuffer_atomic_dec:{ *:[i32] } i32:{ *:[i32] }:$vdata_in, v4i32:{ *:[v4i32] }:$rsrc, i32:{ *:[i32] }:$vindex, 0:{ *:[i32] }, (BUFSOffset:{ *:[i32] } i32:{ *:[i32] }:$soffset), (timm:{ *:[i32] }):$offset, (timm:{ *:[i32] }):$auxiliary, (timm:{ *:[i1] }))<<P:Predicate_SIbuffer_atomic_dec_noret>>  =>  (BUFFER_ATOMIC_DEC_VBUFFER_IDXEN anonymous_15037:{ *:[i32] }:$vdata_in, VGPR_32:{ *:[i32] }:$vindex, SReg_128:{ *:[v4i32] }:$rsrc, SCSrc_b32:{ *:[i32] }:$soffset, (timm:{ *:[i32] }):$offset, (extract_cpol:{ *:[i32] } ?:{ *:[i32] }:$auxiliary))
        GIR_BuildMI, /*InsnID*/0, /*Opcode*/GIMT_Encode2(AMDGPU::BUFFER_ATOMIC_DEC_VBUFFER_IDXEN),
        GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/1, // vdata_in
        GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/3, // vindex
        GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/2, // rsrc
        GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/0, // soffset
        GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/6, // offset
        GIR_CustomOperandRenderer, /*InsnID*/0, /*OldInsnID*/0, /*OpIdx*/7, /*OperandRenderer*/GIMT_Encode2(GICR_renderExtractCPol), // auxiliary
        GIR_MergeMemOperands, /*InsnID*/0, /*NumInsns*/1, /*MergeInsnID's*/0,
        GIR_ConstrainSelectedInstOperands, /*InsnID*/0,
        GIR_EraseFromParent, /*InsnID*/0,
        // GIR_Coverage, 4918,
        GIR_Done,
      // Label 5848: @426814
      GIM_Try, /*On fail goto*//*Label 5849*/ GIMT_Encode4(426891), // Rule ID 4906 //
        GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasUnrestrictedSOffset),
        GIM_CheckRegBankForClass, /*MI*/0, /*Op*/0, /*RC*/GIMT_Encode2(AMDGPU::AV_32RegClassID),
        GIM_CheckConstantInt8, /*MI*/0, /*Op*/4, 0,
        // MIs[0] offset
        GIM_CheckIsImm, /*MI*/0, /*Op*/6,
        // MIs[0] auxiliary
        GIM_CheckIsImm, /*MI*/0, /*Op*/7,
        // MIs[0] Operand 8
        GIM_CheckIsImm, /*MI*/0, /*Op*/8,
        GIM_CheckComplexPattern, /*MI*/0, /*Op*/5, /*Renderer*/GIMT_Encode2(0), GIMT_Encode2(GICP_gi_buf_soffset),
        // (SIbuffer_atomic_dec:{ *:[i32] } i32:{ *:[i32] }:$vdata_in, v4i32:{ *:[v4i32] }:$rsrc, i32:{ *:[i32] }:$vindex, 0:{ *:[i32] }, (BUFSOffset:{ *:[i32] } i32:{ *:[i32] }:$soffset), (timm:{ *:[i32] }):$offset, (timm:{ *:[i32] }):$auxiliary, (timm:{ *:[i1] }))  =>  (BUFFER_ATOMIC_DEC_IDXEN_RTN:{ *:[i32] } anonymous_15037:{ *:[i32] }:$vdata_in, VGPR_32:{ *:[i32] }:$vindex, SReg_128:{ *:[v4i32] }:$rsrc, SCSrc_b32:{ *:[i32] }:$soffset, (timm:{ *:[i32] }):$offset, (extract_cpol_set_glc:{ *:[i32] } ?:{ *:[i32] }:$auxiliary))
        GIR_BuildMI, /*InsnID*/0, /*Opcode*/GIMT_Encode2(AMDGPU::BUFFER_ATOMIC_DEC_IDXEN_RTN),
        GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/0, // DstI[vdata]
        GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/1, // vdata_in
        GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/3, // vindex
        GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/2, // rsrc
        GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/0, // soffset
        GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/6, // offset
        GIR_CustomOperandRenderer, /*InsnID*/0, /*OldInsnID*/0, /*OpIdx*/7, /*OperandRenderer*/GIMT_Encode2(GICR_renderExtractCpolSetGLC), // auxiliary
        GIR_MergeMemOperands, /*InsnID*/0, /*NumInsns*/1, /*MergeInsnID's*/0,
        GIR_ConstrainSelectedInstOperands, /*InsnID*/0,
        GIR_EraseFromParent, /*InsnID*/0,
        // GIR_Coverage, 4906,
        GIR_Done,
      // Label 5849: @426891
      GIM_Try, /*On fail goto*//*Label 5850*/ GIMT_Encode4(426965), // Rule ID 4914 //
        GIM_CheckRegBankForClass, /*MI*/0, /*Op*/0, /*RC*/GIMT_Encode2(AMDGPU::AV_32RegClassID),
        GIM_CheckConstantInt8, /*MI*/0, /*Op*/4, 0,
        // MIs[0] offset
        GIM_CheckIsImm, /*MI*/0, /*Op*/6,
        // MIs[0] auxiliary
        GIM_CheckIsImm, /*MI*/0, /*Op*/7,
        // MIs[0] Operand 8
        GIM_CheckIsImm, /*MI*/0, /*Op*/8,
        GIM_CheckComplexPattern, /*MI*/0, /*Op*/5, /*Renderer*/GIMT_Encode2(0), GIMT_Encode2(GICP_gi_buf_soffset),
        // (SIbuffer_atomic_dec:{ *:[i32] } i32:{ *:[i32] }:$vdata_in, v4i32:{ *:[v4i32] }:$rsrc, i32:{ *:[i32] }:$vindex, 0:{ *:[i32] }, (BUFSOffset:{ *:[i32] } i32:{ *:[i32] }:$soffset), (timm:{ *:[i32] }):$offset, (timm:{ *:[i32] }):$auxiliary, (timm:{ *:[i1] }))  =>  (BUFFER_ATOMIC_DEC_VBUFFER_IDXEN_RTN:{ *:[i32] } anonymous_15037:{ *:[i32] }:$vdata_in, VGPR_32:{ *:[i32] }:$vindex, SReg_128:{ *:[v4i32] }:$rsrc, SCSrc_b32:{ *:[i32] }:$soffset, (timm:{ *:[i32] }):$offset, (extract_cpol_set_glc:{ *:[i32] } ?:{ *:[i32] }:$auxiliary))
        GIR_BuildMI, /*InsnID*/0, /*Opcode*/GIMT_Encode2(AMDGPU::BUFFER_ATOMIC_DEC_VBUFFER_IDXEN_RTN),
        GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/0, // DstI[vdata]
        GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/1, // vdata_in
        GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/3, // vindex
        GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/2, // rsrc
        GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/0, // soffset
        GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/6, // offset
        GIR_CustomOperandRenderer, /*InsnID*/0, /*OldInsnID*/0, /*OpIdx*/7, /*OperandRenderer*/GIMT_Encode2(GICR_renderExtractCpolSetGLC), // auxiliary
        GIR_MergeMemOperands, /*InsnID*/0, /*NumInsns*/1, /*MergeInsnID's*/0,
        GIR_ConstrainSelectedInstOperands, /*InsnID*/0,
        GIR_EraseFromParent, /*InsnID*/0,
        // GIR_Coverage, 4914,
        GIR_Done,
      // Label 5850: @426965
      GIM_Try, /*On fail goto*//*Label 5851*/ GIMT_Encode4(427071), // Rule ID 4912 //
        GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasUnrestrictedSOffset),
        GIM_CheckHasNoUse, /*MI*/0,
        // MIs[0] offset
        GIM_CheckIsImm, /*MI*/0, /*Op*/6,
        // MIs[0] auxiliary
        GIM_CheckIsImm, /*MI*/0, /*Op*/7,
        // MIs[0] Operand 8
        GIM_CheckIsImm, /*MI*/0, /*Op*/8,
        GIM_CheckComplexPattern, /*MI*/0, /*Op*/5, /*Renderer*/GIMT_Encode2(0), GIMT_Encode2(GICP_gi_buf_soffset),
        // (SIbuffer_atomic_dec:{ *:[i32] } i32:{ *:[i32] }:$vdata_in, v4i32:{ *:[v4i32] }:$rsrc, i32:{ *:[i32] }:$vindex, i32:{ *:[i32] }:$voffset, (BUFSOffset:{ *:[i32] } i32:{ *:[i32] }:$soffset), (timm:{ *:[i32] }):$offset, (timm:{ *:[i32] }):$auxiliary, (timm:{ *:[i1] }))<<P:Predicate_SIbuffer_atomic_dec_noret>>  =>  (BUFFER_ATOMIC_DEC_BOTHEN anonymous_15037:{ *:[i32] }:$vdata_in, (REG_SEQUENCE:{ *:[i64] } VReg_64:{ *:[i32] }, VGPR_32:{ *:[i32] }:$vindex, sub0:{ *:[i32] }, VGPR_32:{ *:[i32] }:$voffset, sub1:{ *:[i32] }), SReg_128:{ *:[v4i32] }:$rsrc, SCSrc_b32:{ *:[i32] }:$soffset, (timm:{ *:[i32] }):$offset, (extract_cpol:{ *:[i32] } ?:{ *:[i32] }:$auxiliary))
        GIR_MakeTempReg, /*TempRegID*/0, /*TypeID*/GILLT_s64,
        GIR_BuildMI, /*InsnID*/1, /*Opcode*/GIMT_Encode2(TargetOpcode::REG_SEQUENCE),
        GIR_AddTempRegister, /*InsnID*/1, /*TempRegID*/0, /*TempRegFlags*/GIMT_Encode2(RegState::Define),
        GIR_Copy, /*NewInsnID*/1, /*OldInsnID*/0, /*OpIdx*/3, // vindex
        GIR_AddImm8, /*InsnID*/1, /*SubRegIndex*/3,
        GIR_Copy, /*NewInsnID*/1, /*OldInsnID*/0, /*OpIdx*/4, // voffset
        GIR_AddImm8, /*InsnID*/1, /*SubRegIndex*/11,
        GIR_ConstrainOperandRC, /*InsnID*/1, /*Op*/0, GIMT_Encode2(AMDGPU::VReg_64RegClassID),
        GIR_ConstrainOperandRC, /*InsnID*/1, /*Op*/1, GIMT_Encode2(AMDGPU::VGPR_32RegClassID),
        GIR_ConstrainOperandRC, /*InsnID*/1, /*Op*/3, GIMT_Encode2(AMDGPU::VGPR_32RegClassID),
        GIR_BuildMI, /*InsnID*/0, /*Opcode*/GIMT_Encode2(AMDGPU::BUFFER_ATOMIC_DEC_BOTHEN),
        GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/1, // vdata_in
        GIR_AddSimpleTempRegister, /*InsnID*/0, /*TempRegID*/0,
        GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/2, // rsrc
        GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/0, // soffset
        GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/6, // offset
        GIR_CustomOperandRenderer, /*InsnID*/0, /*OldInsnID*/0, /*OpIdx*/7, /*OperandRenderer*/GIMT_Encode2(GICR_renderExtractCPol), // auxiliary
        GIR_MergeMemOperands, /*InsnID*/0, /*NumInsns*/1, /*MergeInsnID's*/0,
        GIR_ConstrainSelectedInstOperands, /*InsnID*/0,
        GIR_EraseFromParent, /*InsnID*/0,
        // GIR_Coverage, 4912,
        GIR_Done,
      // Label 5851: @427071
      GIM_Try, /*On fail goto*//*Label 5852*/ GIMT_Encode4(427174), // Rule ID 4920 //
        GIM_CheckHasNoUse, /*MI*/0,
        // MIs[0] offset
        GIM_CheckIsImm, /*MI*/0, /*Op*/6,
        // MIs[0] auxiliary
        GIM_CheckIsImm, /*MI*/0, /*Op*/7,
        // MIs[0] Operand 8
        GIM_CheckIsImm, /*MI*/0, /*Op*/8,
        GIM_CheckComplexPattern, /*MI*/0, /*Op*/5, /*Renderer*/GIMT_Encode2(0), GIMT_Encode2(GICP_gi_buf_soffset),
        // (SIbuffer_atomic_dec:{ *:[i32] } i32:{ *:[i32] }:$vdata_in, v4i32:{ *:[v4i32] }:$rsrc, i32:{ *:[i32] }:$vindex, i32:{ *:[i32] }:$voffset, (BUFSOffset:{ *:[i32] } i32:{ *:[i32] }:$soffset), (timm:{ *:[i32] }):$offset, (timm:{ *:[i32] }):$auxiliary, (timm:{ *:[i1] }))<<P:Predicate_SIbuffer_atomic_dec_noret>>  =>  (BUFFER_ATOMIC_DEC_VBUFFER_BOTHEN anonymous_15037:{ *:[i32] }:$vdata_in, (REG_SEQUENCE:{ *:[i64] } VReg_64:{ *:[i32] }, VGPR_32:{ *:[i32] }:$vindex, sub0:{ *:[i32] }, VGPR_32:{ *:[i32] }:$voffset, sub1:{ *:[i32] }), SReg_128:{ *:[v4i32] }:$rsrc, SCSrc_b32:{ *:[i32] }:$soffset, (timm:{ *:[i32] }):$offset, (extract_cpol:{ *:[i32] } ?:{ *:[i32] }:$auxiliary))
        GIR_MakeTempReg, /*TempRegID*/0, /*TypeID*/GILLT_s64,
        GIR_BuildMI, /*InsnID*/1, /*Opcode*/GIMT_Encode2(TargetOpcode::REG_SEQUENCE),
        GIR_AddTempRegister, /*InsnID*/1, /*TempRegID*/0, /*TempRegFlags*/GIMT_Encode2(RegState::Define),
        GIR_Copy, /*NewInsnID*/1, /*OldInsnID*/0, /*OpIdx*/3, // vindex
        GIR_AddImm8, /*InsnID*/1, /*SubRegIndex*/3,
        GIR_Copy, /*NewInsnID*/1, /*OldInsnID*/0, /*OpIdx*/4, // voffset
        GIR_AddImm8, /*InsnID*/1, /*SubRegIndex*/11,
        GIR_ConstrainOperandRC, /*InsnID*/1, /*Op*/0, GIMT_Encode2(AMDGPU::VReg_64RegClassID),
        GIR_ConstrainOperandRC, /*InsnID*/1, /*Op*/1, GIMT_Encode2(AMDGPU::VGPR_32RegClassID),
        GIR_ConstrainOperandRC, /*InsnID*/1, /*Op*/3, GIMT_Encode2(AMDGPU::VGPR_32RegClassID),
        GIR_BuildMI, /*InsnID*/0, /*Opcode*/GIMT_Encode2(AMDGPU::BUFFER_ATOMIC_DEC_VBUFFER_BOTHEN),
        GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/1, // vdata_in
        GIR_AddSimpleTempRegister, /*InsnID*/0, /*TempRegID*/0,
        GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/2, // rsrc
        GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/0, // soffset
        GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/6, // offset
        GIR_CustomOperandRenderer, /*InsnID*/0, /*OldInsnID*/0, /*OpIdx*/7, /*OperandRenderer*/GIMT_Encode2(GICR_renderExtractCPol), // auxiliary
        GIR_MergeMemOperands, /*InsnID*/0, /*NumInsns*/1, /*MergeInsnID's*/0,
        GIR_ConstrainSelectedInstOperands, /*InsnID*/0,
        GIR_EraseFromParent, /*InsnID*/0,
        // GIR_Coverage, 4920,
        GIR_Done,
      // Label 5852: @427174
      GIM_Try, /*On fail goto*//*Label 5853*/ GIMT_Encode4(427287), // Rule ID 4908 //
        GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasUnrestrictedSOffset),
        GIM_CheckRegBankForClass, /*MI*/0, /*Op*/0, /*RC*/GIMT_Encode2(AMDGPU::AV_32RegClassID),
        // MIs[0] offset
        GIM_CheckIsImm, /*MI*/0, /*Op*/6,
        // MIs[0] auxiliary
        GIM_CheckIsImm, /*MI*/0, /*Op*/7,
        // MIs[0] Operand 8
        GIM_CheckIsImm, /*MI*/0, /*Op*/8,
        GIM_CheckComplexPattern, /*MI*/0, /*Op*/5, /*Renderer*/GIMT_Encode2(0), GIMT_Encode2(GICP_gi_buf_soffset),
        // (SIbuffer_atomic_dec:{ *:[i32] } i32:{ *:[i32] }:$vdata_in, v4i32:{ *:[v4i32] }:$rsrc, i32:{ *:[i32] }:$vindex, i32:{ *:[i32] }:$voffset, (BUFSOffset:{ *:[i32] } i32:{ *:[i32] }:$soffset), (timm:{ *:[i32] }):$offset, (timm:{ *:[i32] }):$auxiliary, (timm:{ *:[i1] }))  =>  (BUFFER_ATOMIC_DEC_BOTHEN_RTN:{ *:[i32] } anonymous_15037:{ *:[i32] }:$vdata_in, (REG_SEQUENCE:{ *:[i64] } VReg_64:{ *:[i32] }, VGPR_32:{ *:[i32] }:$vindex, sub0:{ *:[i32] }, VGPR_32:{ *:[i32] }:$voffset, sub1:{ *:[i32] }), SReg_128:{ *:[v4i32] }:$rsrc, SCSrc_b32:{ *:[i32] }:$soffset, (timm:{ *:[i32] }):$offset, (extract_cpol_set_glc:{ *:[i32] } ?:{ *:[i32] }:$auxiliary))
        GIR_MakeTempReg, /*TempRegID*/0, /*TypeID*/GILLT_s64,
        GIR_BuildMI, /*InsnID*/1, /*Opcode*/GIMT_Encode2(TargetOpcode::REG_SEQUENCE),
        GIR_AddTempRegister, /*InsnID*/1, /*TempRegID*/0, /*TempRegFlags*/GIMT_Encode2(RegState::Define),
        GIR_Copy, /*NewInsnID*/1, /*OldInsnID*/0, /*OpIdx*/3, // vindex
        GIR_AddImm8, /*InsnID*/1, /*SubRegIndex*/3,
        GIR_Copy, /*NewInsnID*/1, /*OldInsnID*/0, /*OpIdx*/4, // voffset
        GIR_AddImm8, /*InsnID*/1, /*SubRegIndex*/11,
        GIR_ConstrainOperandRC, /*InsnID*/1, /*Op*/0, GIMT_Encode2(AMDGPU::VReg_64RegClassID),
        GIR_ConstrainOperandRC, /*InsnID*/1, /*Op*/1, GIMT_Encode2(AMDGPU::VGPR_32RegClassID),
        GIR_ConstrainOperandRC, /*InsnID*/1, /*Op*/3, GIMT_Encode2(AMDGPU::VGPR_32RegClassID),
        GIR_BuildMI, /*InsnID*/0, /*Opcode*/GIMT_Encode2(AMDGPU::BUFFER_ATOMIC_DEC_BOTHEN_RTN),
        GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/0, // DstI[vdata]
        GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/1, // vdata_in
        GIR_AddSimpleTempRegister, /*InsnID*/0, /*TempRegID*/0,
        GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/2, // rsrc
        GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/0, // soffset
        GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/6, // offset
        GIR_CustomOperandRenderer, /*InsnID*/0, /*OldInsnID*/0, /*OpIdx*/7, /*OperandRenderer*/GIMT_Encode2(GICR_renderExtractCpolSetGLC), // auxiliary
        GIR_MergeMemOperands, /*InsnID*/0, /*NumInsns*/1, /*MergeInsnID's*/0,
        GIR_ConstrainSelectedInstOperands, /*InsnID*/0,
        GIR_EraseFromParent, /*InsnID*/0,
        // GIR_Coverage, 4908,
        GIR_Done,
      // Label 5853: @427287
      GIM_Try, /*On fail goto*//*Label 5854*/ GIMT_Encode4(427397), // Rule ID 4916 //
        GIM_CheckRegBankForClass, /*MI*/0, /*Op*/0, /*RC*/GIMT_Encode2(AMDGPU::AV_32RegClassID),
        // MIs[0] offset
        GIM_CheckIsImm, /*MI*/0, /*Op*/6,
        // MIs[0] auxiliary
        GIM_CheckIsImm, /*MI*/0, /*Op*/7,
        // MIs[0] Operand 8
        GIM_CheckIsImm, /*MI*/0, /*Op*/8,
        GIM_CheckComplexPattern, /*MI*/0, /*Op*/5, /*Renderer*/GIMT_Encode2(0), GIMT_Encode2(GICP_gi_buf_soffset),
        // (SIbuffer_atomic_dec:{ *:[i32] } i32:{ *:[i32] }:$vdata_in, v4i32:{ *:[v4i32] }:$rsrc, i32:{ *:[i32] }:$vindex, i32:{ *:[i32] }:$voffset, (BUFSOffset:{ *:[i32] } i32:{ *:[i32] }:$soffset), (timm:{ *:[i32] }):$offset, (timm:{ *:[i32] }):$auxiliary, (timm:{ *:[i1] }))  =>  (BUFFER_ATOMIC_DEC_VBUFFER_BOTHEN_RTN:{ *:[i32] } anonymous_15037:{ *:[i32] }:$vdata_in, (REG_SEQUENCE:{ *:[i64] } VReg_64:{ *:[i32] }, VGPR_32:{ *:[i32] }:$vindex, sub0:{ *:[i32] }, VGPR_32:{ *:[i32] }:$voffset, sub1:{ *:[i32] }), SReg_128:{ *:[v4i32] }:$rsrc, SCSrc_b32:{ *:[i32] }:$soffset, (timm:{ *:[i32] }):$offset, (extract_cpol_set_glc:{ *:[i32] } ?:{ *:[i32] }:$auxiliary))
        GIR_MakeTempReg, /*TempRegID*/0, /*TypeID*/GILLT_s64,
        GIR_BuildMI, /*InsnID*/1, /*Opcode*/GIMT_Encode2(TargetOpcode::REG_SEQUENCE),
        GIR_AddTempRegister, /*InsnID*/1, /*TempRegID*/0, /*TempRegFlags*/GIMT_Encode2(RegState::Define),
        GIR_Copy, /*NewInsnID*/1, /*OldInsnID*/0, /*OpIdx*/3, // vindex
        GIR_AddImm8, /*InsnID*/1, /*SubRegIndex*/3,
        GIR_Copy, /*NewInsnID*/1, /*OldInsnID*/0, /*OpIdx*/4, // voffset
        GIR_AddImm8, /*InsnID*/1, /*SubRegIndex*/11,
        GIR_ConstrainOperandRC, /*InsnID*/1, /*Op*/0, GIMT_Encode2(AMDGPU::VReg_64RegClassID),
        GIR_ConstrainOperandRC, /*InsnID*/1, /*Op*/1, GIMT_Encode2(AMDGPU::VGPR_32RegClassID),
        GIR_ConstrainOperandRC, /*InsnID*/1, /*Op*/3, GIMT_Encode2(AMDGPU::VGPR_32RegClassID),
        GIR_BuildMI, /*InsnID*/0, /*Opcode*/GIMT_Encode2(AMDGPU::BUFFER_ATOMIC_DEC_VBUFFER_BOTHEN_RTN),
        GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/0, // DstI[vdata]
        GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/1, // vdata_in
        GIR_AddSimpleTempRegister, /*InsnID*/0, /*TempRegID*/0,
        GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/2, // rsrc
        GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/0, // soffset
        GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/6, // offset
        GIR_CustomOperandRenderer, /*InsnID*/0, /*OldInsnID*/0, /*OpIdx*/7, /*OperandRenderer*/GIMT_Encode2(GICR_renderExtractCpolSetGLC), // auxiliary
        GIR_MergeMemOperands, /*InsnID*/0, /*NumInsns*/1, /*MergeInsnID's*/0,
        GIR_ConstrainSelectedInstOperands, /*InsnID*/0,
        GIR_EraseFromParent, /*InsnID*/0,
        // GIR_Coverage, 4916,
        GIR_Done,
      // Label 5854: @427397
      GIM_Reject,
    // Label 5838: @427398
    GIM_Reject,
    // Label 5836: @427399
    GIM_Try, /*On fail goto*//*Label 5855*/ GIMT_Encode4(428785),
      GIM_CheckType, /*MI*/0, /*Op*/1, /*Type*/GILLT_s64,
      GIM_CheckType, /*MI*/0, /*Op*/2, /*Type*/GILLT_v4s32,
      GIM_CheckType, /*MI*/0, /*Op*/3, /*Type*/GILLT_s32,
      GIM_CheckType, /*MI*/0, /*Op*/4, /*Type*/GILLT_s32,
      GIM_CheckType, /*MI*/0, /*Op*/5, /*Type*/GILLT_s32,
      GIM_Try, /*On fail goto*//*Label 5856*/ GIMT_Encode4(427502), // Rule ID 5109 //
        GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasUnrestrictedSOffset),
        GIM_CheckHasNoUse, /*MI*/0,
        GIM_CheckConstantInt8, /*MI*/0, /*Op*/3, 0,
        GIM_CheckConstantInt8, /*MI*/0, /*Op*/4, 0,
        // MIs[0] offset
        GIM_CheckIsImm, /*MI*/0, /*Op*/6,
        // MIs[0] auxiliary
        GIM_CheckIsImm, /*MI*/0, /*Op*/7,
        // MIs[0] Operand 8
        GIM_CheckLiteralInt, /*MI*/0, /*Op*/8, GIMT_Encode8(0),
        GIM_CheckComplexPattern, /*MI*/0, /*Op*/5, /*Renderer*/GIMT_Encode2(0), GIMT_Encode2(GICP_gi_buf_soffset),
        // (SIbuffer_atomic_dec:{ *:[i64] } i64:{ *:[i64] }:$vdata_in, v4i32:{ *:[v4i32] }:$rsrc, 0:{ *:[i32] }, 0:{ *:[i32] }, (BUFSOffset:{ *:[i32] } i32:{ *:[i32] }:$soffset), (timm:{ *:[i32] }):$offset, (timm:{ *:[i32] }):$auxiliary, 0:{ *:[i1] })<<P:Predicate_SIbuffer_atomic_dec_noret>>  =>  (BUFFER_ATOMIC_DEC_X2_OFFSET anonymous_15036:{ *:[i64] }:$vdata_in, SReg_128:{ *:[v4i32] }:$rsrc, SCSrc_b32:{ *:[i32] }:$soffset, (timm:{ *:[i32] }):$offset, (extract_cpol:{ *:[i32] } ?:{ *:[i32] }:$auxiliary))
        GIR_BuildMI, /*InsnID*/0, /*Opcode*/GIMT_Encode2(AMDGPU::BUFFER_ATOMIC_DEC_X2_OFFSET),
        GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/1, // vdata_in
        GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/2, // rsrc
        GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/0, // soffset
        GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/6, // offset
        GIR_CustomOperandRenderer, /*InsnID*/0, /*OldInsnID*/0, /*OpIdx*/7, /*OperandRenderer*/GIMT_Encode2(GICR_renderExtractCPol), // auxiliary
        GIR_MergeMemOperands, /*InsnID*/0, /*NumInsns*/1, /*MergeInsnID's*/0,
        GIR_ConstrainSelectedInstOperands, /*InsnID*/0,
        GIR_EraseFromParent, /*InsnID*/0,
        // GIR_Coverage, 5109,
        GIR_Done,
      // Label 5856: @427502
      GIM_Try, /*On fail goto*//*Label 5857*/ GIMT_Encode4(427577), // Rule ID 5117 //
        GIM_CheckHasNoUse, /*MI*/0,
        GIM_CheckConstantInt8, /*MI*/0, /*Op*/3, 0,
        GIM_CheckConstantInt8, /*MI*/0, /*Op*/4, 0,
        // MIs[0] offset
        GIM_CheckIsImm, /*MI*/0, /*Op*/6,
        // MIs[0] auxiliary
        GIM_CheckIsImm, /*MI*/0, /*Op*/7,
        // MIs[0] Operand 8
        GIM_CheckLiteralInt, /*MI*/0, /*Op*/8, GIMT_Encode8(0),
        GIM_CheckComplexPattern, /*MI*/0, /*Op*/5, /*Renderer*/GIMT_Encode2(0), GIMT_Encode2(GICP_gi_buf_soffset),
        // (SIbuffer_atomic_dec:{ *:[i64] } i64:{ *:[i64] }:$vdata_in, v4i32:{ *:[v4i32] }:$rsrc, 0:{ *:[i32] }, 0:{ *:[i32] }, (BUFSOffset:{ *:[i32] } i32:{ *:[i32] }:$soffset), (timm:{ *:[i32] }):$offset, (timm:{ *:[i32] }):$auxiliary, 0:{ *:[i1] })<<P:Predicate_SIbuffer_atomic_dec_noret>>  =>  (BUFFER_ATOMIC_DEC_X2_VBUFFER_OFFSET anonymous_15036:{ *:[i64] }:$vdata_in, SReg_128:{ *:[v4i32] }:$rsrc, SCSrc_b32:{ *:[i32] }:$soffset, (timm:{ *:[i32] }):$offset, (extract_cpol:{ *:[i32] } ?:{ *:[i32] }:$auxiliary))
        GIR_BuildMI, /*InsnID*/0, /*Opcode*/GIMT_Encode2(AMDGPU::BUFFER_ATOMIC_DEC_X2_VBUFFER_OFFSET),
        GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/1, // vdata_in
        GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/2, // rsrc
        GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/0, // soffset
        GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/6, // offset
        GIR_CustomOperandRenderer, /*InsnID*/0, /*OldInsnID*/0, /*OpIdx*/7, /*OperandRenderer*/GIMT_Encode2(GICR_renderExtractCPol), // auxiliary
        GIR_MergeMemOperands, /*InsnID*/0, /*NumInsns*/1, /*MergeInsnID's*/0,
        GIR_ConstrainSelectedInstOperands, /*InsnID*/0,
        GIR_EraseFromParent, /*InsnID*/0,
        // GIR_Coverage, 5117,
        GIR_Done,
      // Label 5857: @427577
      GIM_Try, /*On fail goto*//*Label 5858*/ GIMT_Encode4(427662), // Rule ID 5105 //
        GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasUnrestrictedSOffset),
        GIM_CheckRegBankForClass, /*MI*/0, /*Op*/0, /*RC*/GIMT_Encode2(AMDGPU::AV_64RegClassID),
        GIM_CheckConstantInt8, /*MI*/0, /*Op*/3, 0,
        GIM_CheckConstantInt8, /*MI*/0, /*Op*/4, 0,
        // MIs[0] offset
        GIM_CheckIsImm, /*MI*/0, /*Op*/6,
        // MIs[0] auxiliary
        GIM_CheckIsImm, /*MI*/0, /*Op*/7,
        // MIs[0] Operand 8
        GIM_CheckLiteralInt, /*MI*/0, /*Op*/8, GIMT_Encode8(0),
        GIM_CheckComplexPattern, /*MI*/0, /*Op*/5, /*Renderer*/GIMT_Encode2(0), GIMT_Encode2(GICP_gi_buf_soffset),
        // (SIbuffer_atomic_dec:{ *:[i64] } i64:{ *:[i64] }:$vdata_in, v4i32:{ *:[v4i32] }:$rsrc, 0:{ *:[i32] }, 0:{ *:[i32] }, (BUFSOffset:{ *:[i32] } i32:{ *:[i32] }:$soffset), (timm:{ *:[i32] }):$offset, (timm:{ *:[i32] }):$auxiliary, 0:{ *:[i1] })  =>  (BUFFER_ATOMIC_DEC_X2_OFFSET_RTN:{ *:[i64] } anonymous_15036:{ *:[i64] }:$vdata_in, SReg_128:{ *:[v4i32] }:$rsrc, SCSrc_b32:{ *:[i32] }:$soffset, (timm:{ *:[i32] }):$offset, (extract_cpol_set_glc:{ *:[i32] } ?:{ *:[i32] }:$auxiliary))
        GIR_BuildMI, /*InsnID*/0, /*Opcode*/GIMT_Encode2(AMDGPU::BUFFER_ATOMIC_DEC_X2_OFFSET_RTN),
        GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/0, // DstI[vdata]
        GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/1, // vdata_in
        GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/2, // rsrc
        GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/0, // soffset
        GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/6, // offset
        GIR_CustomOperandRenderer, /*InsnID*/0, /*OldInsnID*/0, /*OpIdx*/7, /*OperandRenderer*/GIMT_Encode2(GICR_renderExtractCpolSetGLC), // auxiliary
        GIR_MergeMemOperands, /*InsnID*/0, /*NumInsns*/1, /*MergeInsnID's*/0,
        GIR_ConstrainSelectedInstOperands, /*InsnID*/0,
        GIR_EraseFromParent, /*InsnID*/0,
        // GIR_Coverage, 5105,
        GIR_Done,
      // Label 5858: @427662
      GIM_Try, /*On fail goto*//*Label 5859*/ GIMT_Encode4(427744), // Rule ID 5113 //
        GIM_CheckRegBankForClass, /*MI*/0, /*Op*/0, /*RC*/GIMT_Encode2(AMDGPU::AV_64RegClassID),
        GIM_CheckConstantInt8, /*MI*/0, /*Op*/3, 0,
        GIM_CheckConstantInt8, /*MI*/0, /*Op*/4, 0,
        // MIs[0] offset
        GIM_CheckIsImm, /*MI*/0, /*Op*/6,
        // MIs[0] auxiliary
        GIM_CheckIsImm, /*MI*/0, /*Op*/7,
        // MIs[0] Operand 8
        GIM_CheckLiteralInt, /*MI*/0, /*Op*/8, GIMT_Encode8(0),
        GIM_CheckComplexPattern, /*MI*/0, /*Op*/5, /*Renderer*/GIMT_Encode2(0), GIMT_Encode2(GICP_gi_buf_soffset),
        // (SIbuffer_atomic_dec:{ *:[i64] } i64:{ *:[i64] }:$vdata_in, v4i32:{ *:[v4i32] }:$rsrc, 0:{ *:[i32] }, 0:{ *:[i32] }, (BUFSOffset:{ *:[i32] } i32:{ *:[i32] }:$soffset), (timm:{ *:[i32] }):$offset, (timm:{ *:[i32] }):$auxiliary, 0:{ *:[i1] })  =>  (BUFFER_ATOMIC_DEC_X2_VBUFFER_OFFSET_RTN:{ *:[i64] } anonymous_15036:{ *:[i64] }:$vdata_in, SReg_128:{ *:[v4i32] }:$rsrc, SCSrc_b32:{ *:[i32] }:$soffset, (timm:{ *:[i32] }):$offset, (extract_cpol_set_glc:{ *:[i32] } ?:{ *:[i32] }:$auxiliary))
        GIR_BuildMI, /*InsnID*/0, /*Opcode*/GIMT_Encode2(AMDGPU::BUFFER_ATOMIC_DEC_X2_VBUFFER_OFFSET_RTN),
        GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/0, // DstI[vdata]
        GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/1, // vdata_in
        GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/2, // rsrc
        GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/0, // soffset
        GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/6, // offset
        GIR_CustomOperandRenderer, /*InsnID*/0, /*OldInsnID*/0, /*OpIdx*/7, /*OperandRenderer*/GIMT_Encode2(GICR_renderExtractCpolSetGLC), // auxiliary
        GIR_MergeMemOperands, /*InsnID*/0, /*NumInsns*/1, /*MergeInsnID's*/0,
        GIR_ConstrainSelectedInstOperands, /*InsnID*/0,
        GIR_EraseFromParent, /*InsnID*/0,
        // GIR_Coverage, 5113,
        GIR_Done,
      // Label 5859: @427744
      GIM_Try, /*On fail goto*//*Label 5860*/ GIMT_Encode4(427822), // Rule ID 5111 //
        GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasUnrestrictedSOffset),
        GIM_CheckHasNoUse, /*MI*/0,
        GIM_CheckConstantInt8, /*MI*/0, /*Op*/3, 0,
        // MIs[0] offset
        GIM_CheckIsImm, /*MI*/0, /*Op*/6,
        // MIs[0] auxiliary
        GIM_CheckIsImm, /*MI*/0, /*Op*/7,
        // MIs[0] Operand 8
        GIM_CheckLiteralInt, /*MI*/0, /*Op*/8, GIMT_Encode8(0),
        GIM_CheckComplexPattern, /*MI*/0, /*Op*/5, /*Renderer*/GIMT_Encode2(0), GIMT_Encode2(GICP_gi_buf_soffset),
        // (SIbuffer_atomic_dec:{ *:[i64] } i64:{ *:[i64] }:$vdata_in, v4i32:{ *:[v4i32] }:$rsrc, 0:{ *:[i32] }, i32:{ *:[i32] }:$voffset, (BUFSOffset:{ *:[i32] } i32:{ *:[i32] }:$soffset), (timm:{ *:[i32] }):$offset, (timm:{ *:[i32] }):$auxiliary, 0:{ *:[i1] })<<P:Predicate_SIbuffer_atomic_dec_noret>>  =>  (BUFFER_ATOMIC_DEC_X2_OFFEN anonymous_15036:{ *:[i64] }:$vdata_in, VGPR_32:{ *:[i32] }:$voffset, SReg_128:{ *:[v4i32] }:$rsrc, SCSrc_b32:{ *:[i32] }:$soffset, (timm:{ *:[i32] }):$offset, (extract_cpol:{ *:[i32] } ?:{ *:[i32] }:$auxiliary))
        GIR_BuildMI, /*InsnID*/0, /*Opcode*/GIMT_Encode2(AMDGPU::BUFFER_ATOMIC_DEC_X2_OFFEN),
        GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/1, // vdata_in
        GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/4, // voffset
        GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/2, // rsrc
        GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/0, // soffset
        GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/6, // offset
        GIR_CustomOperandRenderer, /*InsnID*/0, /*OldInsnID*/0, /*OpIdx*/7, /*OperandRenderer*/GIMT_Encode2(GICR_renderExtractCPol), // auxiliary
        GIR_MergeMemOperands, /*InsnID*/0, /*NumInsns*/1, /*MergeInsnID's*/0,
        GIR_ConstrainSelectedInstOperands, /*InsnID*/0,
        GIR_EraseFromParent, /*InsnID*/0,
        // GIR_Coverage, 5111,
        GIR_Done,
      // Label 5860: @427822
      GIM_Try, /*On fail goto*//*Label 5861*/ GIMT_Encode4(427897), // Rule ID 5119 //
        GIM_CheckHasNoUse, /*MI*/0,
        GIM_CheckConstantInt8, /*MI*/0, /*Op*/3, 0,
        // MIs[0] offset
        GIM_CheckIsImm, /*MI*/0, /*Op*/6,
        // MIs[0] auxiliary
        GIM_CheckIsImm, /*MI*/0, /*Op*/7,
        // MIs[0] Operand 8
        GIM_CheckLiteralInt, /*MI*/0, /*Op*/8, GIMT_Encode8(0),
        GIM_CheckComplexPattern, /*MI*/0, /*Op*/5, /*Renderer*/GIMT_Encode2(0), GIMT_Encode2(GICP_gi_buf_soffset),
        // (SIbuffer_atomic_dec:{ *:[i64] } i64:{ *:[i64] }:$vdata_in, v4i32:{ *:[v4i32] }:$rsrc, 0:{ *:[i32] }, i32:{ *:[i32] }:$voffset, (BUFSOffset:{ *:[i32] } i32:{ *:[i32] }:$soffset), (timm:{ *:[i32] }):$offset, (timm:{ *:[i32] }):$auxiliary, 0:{ *:[i1] })<<P:Predicate_SIbuffer_atomic_dec_noret>>  =>  (BUFFER_ATOMIC_DEC_X2_VBUFFER_OFFEN anonymous_15036:{ *:[i64] }:$vdata_in, VGPR_32:{ *:[i32] }:$voffset, SReg_128:{ *:[v4i32] }:$rsrc, SCSrc_b32:{ *:[i32] }:$soffset, (timm:{ *:[i32] }):$offset, (extract_cpol:{ *:[i32] } ?:{ *:[i32] }:$auxiliary))
        GIR_BuildMI, /*InsnID*/0, /*Opcode*/GIMT_Encode2(AMDGPU::BUFFER_ATOMIC_DEC_X2_VBUFFER_OFFEN),
        GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/1, // vdata_in
        GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/4, // voffset
        GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/2, // rsrc
        GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/0, // soffset
        GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/6, // offset
        GIR_CustomOperandRenderer, /*InsnID*/0, /*OldInsnID*/0, /*OpIdx*/7, /*OperandRenderer*/GIMT_Encode2(GICR_renderExtractCPol), // auxiliary
        GIR_MergeMemOperands, /*InsnID*/0, /*NumInsns*/1, /*MergeInsnID's*/0,
        GIR_ConstrainSelectedInstOperands, /*InsnID*/0,
        GIR_EraseFromParent, /*InsnID*/0,
        // GIR_Coverage, 5119,
        GIR_Done,
      // Label 5861: @427897
      GIM_Try, /*On fail goto*//*Label 5862*/ GIMT_Encode4(427982), // Rule ID 5107 //
        GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasUnrestrictedSOffset),
        GIM_CheckRegBankForClass, /*MI*/0, /*Op*/0, /*RC*/GIMT_Encode2(AMDGPU::AV_64RegClassID),
        GIM_CheckConstantInt8, /*MI*/0, /*Op*/3, 0,
        // MIs[0] offset
        GIM_CheckIsImm, /*MI*/0, /*Op*/6,
        // MIs[0] auxiliary
        GIM_CheckIsImm, /*MI*/0, /*Op*/7,
        // MIs[0] Operand 8
        GIM_CheckLiteralInt, /*MI*/0, /*Op*/8, GIMT_Encode8(0),
        GIM_CheckComplexPattern, /*MI*/0, /*Op*/5, /*Renderer*/GIMT_Encode2(0), GIMT_Encode2(GICP_gi_buf_soffset),
        // (SIbuffer_atomic_dec:{ *:[i64] } i64:{ *:[i64] }:$vdata_in, v4i32:{ *:[v4i32] }:$rsrc, 0:{ *:[i32] }, i32:{ *:[i32] }:$voffset, (BUFSOffset:{ *:[i32] } i32:{ *:[i32] }:$soffset), (timm:{ *:[i32] }):$offset, (timm:{ *:[i32] }):$auxiliary, 0:{ *:[i1] })  =>  (BUFFER_ATOMIC_DEC_X2_OFFEN_RTN:{ *:[i64] } anonymous_15036:{ *:[i64] }:$vdata_in, VGPR_32:{ *:[i32] }:$voffset, SReg_128:{ *:[v4i32] }:$rsrc, SCSrc_b32:{ *:[i32] }:$soffset, (timm:{ *:[i32] }):$offset, (extract_cpol_set_glc:{ *:[i32] } ?:{ *:[i32] }:$auxiliary))
        GIR_BuildMI, /*InsnID*/0, /*Opcode*/GIMT_Encode2(AMDGPU::BUFFER_ATOMIC_DEC_X2_OFFEN_RTN),
        GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/0, // DstI[vdata]
        GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/1, // vdata_in
        GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/4, // voffset
        GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/2, // rsrc
        GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/0, // soffset
        GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/6, // offset
        GIR_CustomOperandRenderer, /*InsnID*/0, /*OldInsnID*/0, /*OpIdx*/7, /*OperandRenderer*/GIMT_Encode2(GICR_renderExtractCpolSetGLC), // auxiliary
        GIR_MergeMemOperands, /*InsnID*/0, /*NumInsns*/1, /*MergeInsnID's*/0,
        GIR_ConstrainSelectedInstOperands, /*InsnID*/0,
        GIR_EraseFromParent, /*InsnID*/0,
        // GIR_Coverage, 5107,
        GIR_Done,
      // Label 5862: @427982
      GIM_Try, /*On fail goto*//*Label 5863*/ GIMT_Encode4(428064), // Rule ID 5115 //
        GIM_CheckRegBankForClass, /*MI*/0, /*Op*/0, /*RC*/GIMT_Encode2(AMDGPU::AV_64RegClassID),
        GIM_CheckConstantInt8, /*MI*/0, /*Op*/3, 0,
        // MIs[0] offset
        GIM_CheckIsImm, /*MI*/0, /*Op*/6,
        // MIs[0] auxiliary
        GIM_CheckIsImm, /*MI*/0, /*Op*/7,
        // MIs[0] Operand 8
        GIM_CheckLiteralInt, /*MI*/0, /*Op*/8, GIMT_Encode8(0),
        GIM_CheckComplexPattern, /*MI*/0, /*Op*/5, /*Renderer*/GIMT_Encode2(0), GIMT_Encode2(GICP_gi_buf_soffset),
        // (SIbuffer_atomic_dec:{ *:[i64] } i64:{ *:[i64] }:$vdata_in, v4i32:{ *:[v4i32] }:$rsrc, 0:{ *:[i32] }, i32:{ *:[i32] }:$voffset, (BUFSOffset:{ *:[i32] } i32:{ *:[i32] }:$soffset), (timm:{ *:[i32] }):$offset, (timm:{ *:[i32] }):$auxiliary, 0:{ *:[i1] })  =>  (BUFFER_ATOMIC_DEC_X2_VBUFFER_OFFEN_RTN:{ *:[i64] } anonymous_15036:{ *:[i64] }:$vdata_in, VGPR_32:{ *:[i32] }:$voffset, SReg_128:{ *:[v4i32] }:$rsrc, SCSrc_b32:{ *:[i32] }:$soffset, (timm:{ *:[i32] }):$offset, (extract_cpol_set_glc:{ *:[i32] } ?:{ *:[i32] }:$auxiliary))
        GIR_BuildMI, /*InsnID*/0, /*Opcode*/GIMT_Encode2(AMDGPU::BUFFER_ATOMIC_DEC_X2_VBUFFER_OFFEN_RTN),
        GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/0, // DstI[vdata]
        GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/1, // vdata_in
        GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/4, // voffset
        GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/2, // rsrc
        GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/0, // soffset
        GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/6, // offset
        GIR_CustomOperandRenderer, /*InsnID*/0, /*OldInsnID*/0, /*OpIdx*/7, /*OperandRenderer*/GIMT_Encode2(GICR_renderExtractCpolSetGLC), // auxiliary
        GIR_MergeMemOperands, /*InsnID*/0, /*NumInsns*/1, /*MergeInsnID's*/0,
        GIR_ConstrainSelectedInstOperands, /*InsnID*/0,
        GIR_EraseFromParent, /*InsnID*/0,
        // GIR_Coverage, 5115,
        GIR_Done,
      // Label 5863: @428064
      GIM_Try, /*On fail goto*//*Label 5864*/ GIMT_Encode4(428134), // Rule ID 5110 //
        GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasUnrestrictedSOffset),
        GIM_CheckHasNoUse, /*MI*/0,
        GIM_CheckConstantInt8, /*MI*/0, /*Op*/4, 0,
        // MIs[0] offset
        GIM_CheckIsImm, /*MI*/0, /*Op*/6,
        // MIs[0] auxiliary
        GIM_CheckIsImm, /*MI*/0, /*Op*/7,
        // MIs[0] Operand 8
        GIM_CheckIsImm, /*MI*/0, /*Op*/8,
        GIM_CheckComplexPattern, /*MI*/0, /*Op*/5, /*Renderer*/GIMT_Encode2(0), GIMT_Encode2(GICP_gi_buf_soffset),
        // (SIbuffer_atomic_dec:{ *:[i64] } i64:{ *:[i64] }:$vdata_in, v4i32:{ *:[v4i32] }:$rsrc, i32:{ *:[i32] }:$vindex, 0:{ *:[i32] }, (BUFSOffset:{ *:[i32] } i32:{ *:[i32] }:$soffset), (timm:{ *:[i32] }):$offset, (timm:{ *:[i32] }):$auxiliary, (timm:{ *:[i1] }))<<P:Predicate_SIbuffer_atomic_dec_noret>>  =>  (BUFFER_ATOMIC_DEC_X2_IDXEN anonymous_15036:{ *:[i64] }:$vdata_in, VGPR_32:{ *:[i32] }:$vindex, SReg_128:{ *:[v4i32] }:$rsrc, SCSrc_b32:{ *:[i32] }:$soffset, (timm:{ *:[i32] }):$offset, (extract_cpol:{ *:[i32] } ?:{ *:[i32] }:$auxiliary))
        GIR_BuildMI, /*InsnID*/0, /*Opcode*/GIMT_Encode2(AMDGPU::BUFFER_ATOMIC_DEC_X2_IDXEN),
        GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/1, // vdata_in
        GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/3, // vindex
        GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/2, // rsrc
        GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/0, // soffset
        GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/6, // offset
        GIR_CustomOperandRenderer, /*InsnID*/0, /*OldInsnID*/0, /*OpIdx*/7, /*OperandRenderer*/GIMT_Encode2(GICR_renderExtractCPol), // auxiliary
        GIR_MergeMemOperands, /*InsnID*/0, /*NumInsns*/1, /*MergeInsnID's*/0,
        GIR_ConstrainSelectedInstOperands, /*InsnID*/0,
        GIR_EraseFromParent, /*InsnID*/0,
        // GIR_Coverage, 5110,
        GIR_Done,
      // Label 5864: @428134
      GIM_Try, /*On fail goto*//*Label 5865*/ GIMT_Encode4(428201), // Rule ID 5118 //
        GIM_CheckHasNoUse, /*MI*/0,
        GIM_CheckConstantInt8, /*MI*/0, /*Op*/4, 0,
        // MIs[0] offset
        GIM_CheckIsImm, /*MI*/0, /*Op*/6,
        // MIs[0] auxiliary
        GIM_CheckIsImm, /*MI*/0, /*Op*/7,
        // MIs[0] Operand 8
        GIM_CheckIsImm, /*MI*/0, /*Op*/8,
        GIM_CheckComplexPattern, /*MI*/0, /*Op*/5, /*Renderer*/GIMT_Encode2(0), GIMT_Encode2(GICP_gi_buf_soffset),
        // (SIbuffer_atomic_dec:{ *:[i64] } i64:{ *:[i64] }:$vdata_in, v4i32:{ *:[v4i32] }:$rsrc, i32:{ *:[i32] }:$vindex, 0:{ *:[i32] }, (BUFSOffset:{ *:[i32] } i32:{ *:[i32] }:$soffset), (timm:{ *:[i32] }):$offset, (timm:{ *:[i32] }):$auxiliary, (timm:{ *:[i1] }))<<P:Predicate_SIbuffer_atomic_dec_noret>>  =>  (BUFFER_ATOMIC_DEC_X2_VBUFFER_IDXEN anonymous_15036:{ *:[i64] }:$vdata_in, VGPR_32:{ *:[i32] }:$vindex, SReg_128:{ *:[v4i32] }:$rsrc, SCSrc_b32:{ *:[i32] }:$soffset, (timm:{ *:[i32] }):$offset, (extract_cpol:{ *:[i32] } ?:{ *:[i32] }:$auxiliary))
        GIR_BuildMI, /*InsnID*/0, /*Opcode*/GIMT_Encode2(AMDGPU::BUFFER_ATOMIC_DEC_X2_VBUFFER_IDXEN),
        GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/1, // vdata_in
        GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/3, // vindex
        GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/2, // rsrc
        GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/0, // soffset
        GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/6, // offset
        GIR_CustomOperandRenderer, /*InsnID*/0, /*OldInsnID*/0, /*OpIdx*/7, /*OperandRenderer*/GIMT_Encode2(GICR_renderExtractCPol), // auxiliary
        GIR_MergeMemOperands, /*InsnID*/0, /*NumInsns*/1, /*MergeInsnID's*/0,
        GIR_ConstrainSelectedInstOperands, /*InsnID*/0,
        GIR_EraseFromParent, /*InsnID*/0,
        // GIR_Coverage, 5118,
        GIR_Done,
      // Label 5865: @428201
      GIM_Try, /*On fail goto*//*Label 5866*/ GIMT_Encode4(428278), // Rule ID 5106 //
        GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasUnrestrictedSOffset),
        GIM_CheckRegBankForClass, /*MI*/0, /*Op*/0, /*RC*/GIMT_Encode2(AMDGPU::AV_64RegClassID),
        GIM_CheckConstantInt8, /*MI*/0, /*Op*/4, 0,
        // MIs[0] offset
        GIM_CheckIsImm, /*MI*/0, /*Op*/6,
        // MIs[0] auxiliary
        GIM_CheckIsImm, /*MI*/0, /*Op*/7,
        // MIs[0] Operand 8
        GIM_CheckIsImm, /*MI*/0, /*Op*/8,
        GIM_CheckComplexPattern, /*MI*/0, /*Op*/5, /*Renderer*/GIMT_Encode2(0), GIMT_Encode2(GICP_gi_buf_soffset),
        // (SIbuffer_atomic_dec:{ *:[i64] } i64:{ *:[i64] }:$vdata_in, v4i32:{ *:[v4i32] }:$rsrc, i32:{ *:[i32] }:$vindex, 0:{ *:[i32] }, (BUFSOffset:{ *:[i32] } i32:{ *:[i32] }:$soffset), (timm:{ *:[i32] }):$offset, (timm:{ *:[i32] }):$auxiliary, (timm:{ *:[i1] }))  =>  (BUFFER_ATOMIC_DEC_X2_IDXEN_RTN:{ *:[i64] } anonymous_15036:{ *:[i64] }:$vdata_in, VGPR_32:{ *:[i32] }:$vindex, SReg_128:{ *:[v4i32] }:$rsrc, SCSrc_b32:{ *:[i32] }:$soffset, (timm:{ *:[i32] }):$offset, (extract_cpol_set_glc:{ *:[i32] } ?:{ *:[i32] }:$auxiliary))
        GIR_BuildMI, /*InsnID*/0, /*Opcode*/GIMT_Encode2(AMDGPU::BUFFER_ATOMIC_DEC_X2_IDXEN_RTN),
        GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/0, // DstI[vdata]
        GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/1, // vdata_in
        GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/3, // vindex
        GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/2, // rsrc
        GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/0, // soffset
        GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/6, // offset
        GIR_CustomOperandRenderer, /*InsnID*/0, /*OldInsnID*/0, /*OpIdx*/7, /*OperandRenderer*/GIMT_Encode2(GICR_renderExtractCpolSetGLC), // auxiliary
        GIR_MergeMemOperands, /*InsnID*/0, /*NumInsns*/1, /*MergeInsnID's*/0,
        GIR_ConstrainSelectedInstOperands, /*InsnID*/0,
        GIR_EraseFromParent, /*InsnID*/0,
        // GIR_Coverage, 5106,
        GIR_Done,
      // Label 5866: @428278
      GIM_Try, /*On fail goto*//*Label 5867*/ GIMT_Encode4(428352), // Rule ID 5114 //
        GIM_CheckRegBankForClass, /*MI*/0, /*Op*/0, /*RC*/GIMT_Encode2(AMDGPU::AV_64RegClassID),
        GIM_CheckConstantInt8, /*MI*/0, /*Op*/4, 0,
        // MIs[0] offset
        GIM_CheckIsImm, /*MI*/0, /*Op*/6,
        // MIs[0] auxiliary
        GIM_CheckIsImm, /*MI*/0, /*Op*/7,
        // MIs[0] Operand 8
        GIM_CheckIsImm, /*MI*/0, /*Op*/8,
        GIM_CheckComplexPattern, /*MI*/0, /*Op*/5, /*Renderer*/GIMT_Encode2(0), GIMT_Encode2(GICP_gi_buf_soffset),
        // (SIbuffer_atomic_dec:{ *:[i64] } i64:{ *:[i64] }:$vdata_in, v4i32:{ *:[v4i32] }:$rsrc, i32:{ *:[i32] }:$vindex, 0:{ *:[i32] }, (BUFSOffset:{ *:[i32] } i32:{ *:[i32] }:$soffset), (timm:{ *:[i32] }):$offset, (timm:{ *:[i32] }):$auxiliary, (timm:{ *:[i1] }))  =>  (BUFFER_ATOMIC_DEC_X2_VBUFFER_IDXEN_RTN:{ *:[i64] } anonymous_15036:{ *:[i64] }:$vdata_in, VGPR_32:{ *:[i32] }:$vindex, SReg_128:{ *:[v4i32] }:$rsrc, SCSrc_b32:{ *:[i32] }:$soffset, (timm:{ *:[i32] }):$offset, (extract_cpol_set_glc:{ *:[i32] } ?:{ *:[i32] }:$auxiliary))
        GIR_BuildMI, /*InsnID*/0, /*Opcode*/GIMT_Encode2(AMDGPU::BUFFER_ATOMIC_DEC_X2_VBUFFER_IDXEN_RTN),
        GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/0, // DstI[vdata]
        GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/1, // vdata_in
        GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/3, // vindex
        GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/2, // rsrc
        GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/0, // soffset
        GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/6, // offset
        GIR_CustomOperandRenderer, /*InsnID*/0, /*OldInsnID*/0, /*OpIdx*/7, /*OperandRenderer*/GIMT_Encode2(GICR_renderExtractCpolSetGLC), // auxiliary
        GIR_MergeMemOperands, /*InsnID*/0, /*NumInsns*/1, /*MergeInsnID's*/0,
        GIR_ConstrainSelectedInstOperands, /*InsnID*/0,
        GIR_EraseFromParent, /*InsnID*/0,
        // GIR_Coverage, 5114,
        GIR_Done,
      // Label 5867: @428352
      GIM_Try, /*On fail goto*//*Label 5868*/ GIMT_Encode4(428458), // Rule ID 5112 //
        GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasUnrestrictedSOffset),
        GIM_CheckHasNoUse, /*MI*/0,
        // MIs[0] offset
        GIM_CheckIsImm, /*MI*/0, /*Op*/6,
        // MIs[0] auxiliary
        GIM_CheckIsImm, /*MI*/0, /*Op*/7,
        // MIs[0] Operand 8
        GIM_CheckIsImm, /*MI*/0, /*Op*/8,
        GIM_CheckComplexPattern, /*MI*/0, /*Op*/5, /*Renderer*/GIMT_Encode2(0), GIMT_Encode2(GICP_gi_buf_soffset),
        // (SIbuffer_atomic_dec:{ *:[i64] } i64:{ *:[i64] }:$vdata_in, v4i32:{ *:[v4i32] }:$rsrc, i32:{ *:[i32] }:$vindex, i32:{ *:[i32] }:$voffset, (BUFSOffset:{ *:[i32] } i32:{ *:[i32] }:$soffset), (timm:{ *:[i32] }):$offset, (timm:{ *:[i32] }):$auxiliary, (timm:{ *:[i1] }))<<P:Predicate_SIbuffer_atomic_dec_noret>>  =>  (BUFFER_ATOMIC_DEC_X2_BOTHEN anonymous_15036:{ *:[i64] }:$vdata_in, (REG_SEQUENCE:{ *:[i64] } VReg_64:{ *:[i32] }, VGPR_32:{ *:[i32] }:$vindex, sub0:{ *:[i32] }, VGPR_32:{ *:[i32] }:$voffset, sub1:{ *:[i32] }), SReg_128:{ *:[v4i32] }:$rsrc, SCSrc_b32:{ *:[i32] }:$soffset, (timm:{ *:[i32] }):$offset, (extract_cpol:{ *:[i32] } ?:{ *:[i32] }:$auxiliary))
        GIR_MakeTempReg, /*TempRegID*/0, /*TypeID*/GILLT_s64,
        GIR_BuildMI, /*InsnID*/1, /*Opcode*/GIMT_Encode2(TargetOpcode::REG_SEQUENCE),
        GIR_AddTempRegister, /*InsnID*/1, /*TempRegID*/0, /*TempRegFlags*/GIMT_Encode2(RegState::Define),
        GIR_Copy, /*NewInsnID*/1, /*OldInsnID*/0, /*OpIdx*/3, // vindex
        GIR_AddImm8, /*InsnID*/1, /*SubRegIndex*/3,
        GIR_Copy, /*NewInsnID*/1, /*OldInsnID*/0, /*OpIdx*/4, // voffset
        GIR_AddImm8, /*InsnID*/1, /*SubRegIndex*/11,
        GIR_ConstrainOperandRC, /*InsnID*/1, /*Op*/0, GIMT_Encode2(AMDGPU::VReg_64RegClassID),
        GIR_ConstrainOperandRC, /*InsnID*/1, /*Op*/1, GIMT_Encode2(AMDGPU::VGPR_32RegClassID),
        GIR_ConstrainOperandRC, /*InsnID*/1, /*Op*/3, GIMT_Encode2(AMDGPU::VGPR_32RegClassID),
        GIR_BuildMI, /*InsnID*/0, /*Opcode*/GIMT_Encode2(AMDGPU::BUFFER_ATOMIC_DEC_X2_BOTHEN),
        GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/1, // vdata_in
        GIR_AddSimpleTempRegister, /*InsnID*/0, /*TempRegID*/0,
        GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/2, // rsrc
        GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/0, // soffset
        GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/6, // offset
        GIR_CustomOperandRenderer, /*InsnID*/0, /*OldInsnID*/0, /*OpIdx*/7, /*OperandRenderer*/GIMT_Encode2(GICR_renderExtractCPol), // auxiliary
        GIR_MergeMemOperands, /*InsnID*/0, /*NumInsns*/1, /*MergeInsnID's*/0,
        GIR_ConstrainSelectedInstOperands, /*InsnID*/0,
        GIR_EraseFromParent, /*InsnID*/0,
        // GIR_Coverage, 5112,
        GIR_Done,
      // Label 5868: @428458
      GIM_Try, /*On fail goto*//*Label 5869*/ GIMT_Encode4(428561), // Rule ID 5120 //
        GIM_CheckHasNoUse, /*MI*/0,
        // MIs[0] offset
        GIM_CheckIsImm, /*MI*/0, /*Op*/6,
        // MIs[0] auxiliary
        GIM_CheckIsImm, /*MI*/0, /*Op*/7,
        // MIs[0] Operand 8
        GIM_CheckIsImm, /*MI*/0, /*Op*/8,
        GIM_CheckComplexPattern, /*MI*/0, /*Op*/5, /*Renderer*/GIMT_Encode2(0), GIMT_Encode2(GICP_gi_buf_soffset),
        // (SIbuffer_atomic_dec:{ *:[i64] } i64:{ *:[i64] }:$vdata_in, v4i32:{ *:[v4i32] }:$rsrc, i32:{ *:[i32] }:$vindex, i32:{ *:[i32] }:$voffset, (BUFSOffset:{ *:[i32] } i32:{ *:[i32] }:$soffset), (timm:{ *:[i32] }):$offset, (timm:{ *:[i32] }):$auxiliary, (timm:{ *:[i1] }))<<P:Predicate_SIbuffer_atomic_dec_noret>>  =>  (BUFFER_ATOMIC_DEC_X2_VBUFFER_BOTHEN anonymous_15036:{ *:[i64] }:$vdata_in, (REG_SEQUENCE:{ *:[i64] } VReg_64:{ *:[i32] }, VGPR_32:{ *:[i32] }:$vindex, sub0:{ *:[i32] }, VGPR_32:{ *:[i32] }:$voffset, sub1:{ *:[i32] }), SReg_128:{ *:[v4i32] }:$rsrc, SCSrc_b32:{ *:[i32] }:$soffset, (timm:{ *:[i32] }):$offset, (extract_cpol:{ *:[i32] } ?:{ *:[i32] }:$auxiliary))
        GIR_MakeTempReg, /*TempRegID*/0, /*TypeID*/GILLT_s64,
        GIR_BuildMI, /*InsnID*/1, /*Opcode*/GIMT_Encode2(TargetOpcode::REG_SEQUENCE),
        GIR_AddTempRegister, /*InsnID*/1, /*TempRegID*/0, /*TempRegFlags*/GIMT_Encode2(RegState::Define),
        GIR_Copy, /*NewInsnID*/1, /*OldInsnID*/0, /*OpIdx*/3, // vindex
        GIR_AddImm8, /*InsnID*/1, /*SubRegIndex*/3,
        GIR_Copy, /*NewInsnID*/1, /*OldInsnID*/0, /*OpIdx*/4, // voffset
        GIR_AddImm8, /*InsnID*/1, /*SubRegIndex*/11,
        GIR_ConstrainOperandRC, /*InsnID*/1, /*Op*/0, GIMT_Encode2(AMDGPU::VReg_64RegClassID),
        GIR_ConstrainOperandRC, /*InsnID*/1, /*Op*/1, GIMT_Encode2(AMDGPU::VGPR_32RegClassID),
        GIR_ConstrainOperandRC, /*InsnID*/1, /*Op*/3, GIMT_Encode2(AMDGPU::VGPR_32RegClassID),
        GIR_BuildMI, /*InsnID*/0, /*Opcode*/GIMT_Encode2(AMDGPU::BUFFER_ATOMIC_DEC_X2_VBUFFER_BOTHEN),
        GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/1, // vdata_in
        GIR_AddSimpleTempRegister, /*InsnID*/0, /*TempRegID*/0,
        GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/2, // rsrc
        GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/0, // soffset
        GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/6, // offset
        GIR_CustomOperandRenderer, /*InsnID*/0, /*OldInsnID*/0, /*OpIdx*/7, /*OperandRenderer*/GIMT_Encode2(GICR_renderExtractCPol), // auxiliary
        GIR_MergeMemOperands, /*InsnID*/0, /*NumInsns*/1, /*MergeInsnID's*/0,
        GIR_ConstrainSelectedInstOperands, /*InsnID*/0,
        GIR_EraseFromParent, /*InsnID*/0,
        // GIR_Coverage, 5120,
        GIR_Done,
      // Label 5869: @428561
      GIM_Try, /*On fail goto*//*Label 5870*/ GIMT_Encode4(428674), // Rule ID 5108 //
        GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasUnrestrictedSOffset),
        GIM_CheckRegBankForClass, /*MI*/0, /*Op*/0, /*RC*/GIMT_Encode2(AMDGPU::AV_64RegClassID),
        // MIs[0] offset
        GIM_CheckIsImm, /*MI*/0, /*Op*/6,
        // MIs[0] auxiliary
        GIM_CheckIsImm, /*MI*/0, /*Op*/7,
        // MIs[0] Operand 8
        GIM_CheckIsImm, /*MI*/0, /*Op*/8,
        GIM_CheckComplexPattern, /*MI*/0, /*Op*/5, /*Renderer*/GIMT_Encode2(0), GIMT_Encode2(GICP_gi_buf_soffset),
        // (SIbuffer_atomic_dec:{ *:[i64] } i64:{ *:[i64] }:$vdata_in, v4i32:{ *:[v4i32] }:$rsrc, i32:{ *:[i32] }:$vindex, i32:{ *:[i32] }:$voffset, (BUFSOffset:{ *:[i32] } i32:{ *:[i32] }:$soffset), (timm:{ *:[i32] }):$offset, (timm:{ *:[i32] }):$auxiliary, (timm:{ *:[i1] }))  =>  (BUFFER_ATOMIC_DEC_X2_BOTHEN_RTN:{ *:[i64] } anonymous_15036:{ *:[i64] }:$vdata_in, (REG_SEQUENCE:{ *:[i64] } VReg_64:{ *:[i32] }, VGPR_32:{ *:[i32] }:$vindex, sub0:{ *:[i32] }, VGPR_32:{ *:[i32] }:$voffset, sub1:{ *:[i32] }), SReg_128:{ *:[v4i32] }:$rsrc, SCSrc_b32:{ *:[i32] }:$soffset, (timm:{ *:[i32] }):$offset, (extract_cpol_set_glc:{ *:[i32] } ?:{ *:[i32] }:$auxiliary))
        GIR_MakeTempReg, /*TempRegID*/0, /*TypeID*/GILLT_s64,
        GIR_BuildMI, /*InsnID*/1, /*Opcode*/GIMT_Encode2(TargetOpcode::REG_SEQUENCE),
        GIR_AddTempRegister, /*InsnID*/1, /*TempRegID*/0, /*TempRegFlags*/GIMT_Encode2(RegState::Define),
        GIR_Copy, /*NewInsnID*/1, /*OldInsnID*/0, /*OpIdx*/3, // vindex
        GIR_AddImm8, /*InsnID*/1, /*SubRegIndex*/3,
        GIR_Copy, /*NewInsnID*/1, /*OldInsnID*/0, /*OpIdx*/4, // voffset
        GIR_AddImm8, /*InsnID*/1, /*SubRegIndex*/11,
        GIR_ConstrainOperandRC, /*InsnID*/1, /*Op*/0, GIMT_Encode2(AMDGPU::VReg_64RegClassID),
        GIR_ConstrainOperandRC, /*InsnID*/1, /*Op*/1, GIMT_Encode2(AMDGPU::VGPR_32RegClassID),
        GIR_ConstrainOperandRC, /*InsnID*/1, /*Op*/3, GIMT_Encode2(AMDGPU::VGPR_32RegClassID),
        GIR_BuildMI, /*InsnID*/0, /*Opcode*/GIMT_Encode2(AMDGPU::BUFFER_ATOMIC_DEC_X2_BOTHEN_RTN),
        GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/0, // DstI[vdata]
        GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/1, // vdata_in
        GIR_AddSimpleTempRegister, /*InsnID*/0, /*TempRegID*/0,
        GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/2, // rsrc
        GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/0, // soffset
        GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/6, // offset
        GIR_CustomOperandRenderer, /*InsnID*/0, /*OldInsnID*/0, /*OpIdx*/7, /*OperandRenderer*/GIMT_Encode2(GICR_renderExtractCpolSetGLC), // auxiliary
        GIR_MergeMemOperands, /*InsnID*/0, /*NumInsns*/1, /*MergeInsnID's*/0,
        GIR_ConstrainSelectedInstOperands, /*InsnID*/0,
        GIR_EraseFromParent, /*InsnID*/0,
        // GIR_Coverage, 5108,
        GIR_Done,
      // Label 5870: @428674
      GIM_Try, /*On fail goto*//*Label 5871*/ GIMT_Encode4(428784), // Rule ID 5116 //
        GIM_CheckRegBankForClass, /*MI*/0, /*Op*/0, /*RC*/GIMT_Encode2(AMDGPU::AV_64RegClassID),
        // MIs[0] offset
        GIM_CheckIsImm, /*MI*/0, /*Op*/6,
        // MIs[0] auxiliary
        GIM_CheckIsImm, /*MI*/0, /*Op*/7,
        // MIs[0] Operand 8
        GIM_CheckIsImm, /*MI*/0, /*Op*/8,
        GIM_CheckComplexPattern, /*MI*/0, /*Op*/5, /*Renderer*/GIMT_Encode2(0), GIMT_Encode2(GICP_gi_buf_soffset),
        // (SIbuffer_atomic_dec:{ *:[i64] } i64:{ *:[i64] }:$vdata_in, v4i32:{ *:[v4i32] }:$rsrc, i32:{ *:[i32] }:$vindex, i32:{ *:[i32] }:$voffset, (BUFSOffset:{ *:[i32] } i32:{ *:[i32] }:$soffset), (timm:{ *:[i32] }):$offset, (timm:{ *:[i32] }):$auxiliary, (timm:{ *:[i1] }))  =>  (BUFFER_ATOMIC_DEC_X2_VBUFFER_BOTHEN_RTN:{ *:[i64] } anonymous_15036:{ *:[i64] }:$vdata_in, (REG_SEQUENCE:{ *:[i64] } VReg_64:{ *:[i32] }, VGPR_32:{ *:[i32] }:$vindex, sub0:{ *:[i32] }, VGPR_32:{ *:[i32] }:$voffset, sub1:{ *:[i32] }), SReg_128:{ *:[v4i32] }:$rsrc, SCSrc_b32:{ *:[i32] }:$soffset, (timm:{ *:[i32] }):$offset, (extract_cpol_set_glc:{ *:[i32] } ?:{ *:[i32] }:$auxiliary))
        GIR_MakeTempReg, /*TempRegID*/0, /*TypeID*/GILLT_s64,
        GIR_BuildMI, /*InsnID*/1, /*Opcode*/GIMT_Encode2(TargetOpcode::REG_SEQUENCE),
        GIR_AddTempRegister, /*InsnID*/1, /*TempRegID*/0, /*TempRegFlags*/GIMT_Encode2(RegState::Define),
        GIR_Copy, /*NewInsnID*/1, /*OldInsnID*/0, /*OpIdx*/3, // vindex
        GIR_AddImm8, /*InsnID*/1, /*SubRegIndex*/3,
        GIR_Copy, /*NewInsnID*/1, /*OldInsnID*/0, /*OpIdx*/4, // voffset
        GIR_AddImm8, /*InsnID*/1, /*SubRegIndex*/11,
        GIR_ConstrainOperandRC, /*InsnID*/1, /*Op*/0, GIMT_Encode2(AMDGPU::VReg_64RegClassID),
        GIR_ConstrainOperandRC, /*InsnID*/1, /*Op*/1, GIMT_Encode2(AMDGPU::VGPR_32RegClassID),
        GIR_ConstrainOperandRC, /*InsnID*/1, /*Op*/3, GIMT_Encode2(AMDGPU::VGPR_32RegClassID),
        GIR_BuildMI, /*InsnID*/0, /*Opcode*/GIMT_Encode2(AMDGPU::BUFFER_ATOMIC_DEC_X2_VBUFFER_BOTHEN_RTN),
        GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/0, // DstI[vdata]
        GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/1, // vdata_in
        GIR_AddSimpleTempRegister, /*InsnID*/0, /*TempRegID*/0,
        GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/2, // rsrc
        GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/0, // soffset
        GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/6, // offset
        GIR_CustomOperandRenderer, /*InsnID*/0, /*OldInsnID*/0, /*OpIdx*/7, /*OperandRenderer*/GIMT_Encode2(GICR_renderExtractCpolSetGLC), // auxiliary
        GIR_MergeMemOperands, /*InsnID*/0, /*NumInsns*/1, /*MergeInsnID's*/0,
        GIR_ConstrainSelectedInstOperands, /*InsnID*/0,
        GIR_EraseFromParent, /*InsnID*/0,
        // GIR_Coverage, 5116,
        GIR_Done,
      // Label 5871: @428784
      GIM_Reject,
    // Label 5855: @428785
    GIM_Reject,
    // Label 5837: @428786
    GIM_Reject,
    // Label 111: @428787
    GIM_SwitchType, /*MI*/0, /*Op*/0, /*[*/GIMT_Encode2(9), GIMT_Encode2(12), /*)*//*default:*//*Label 5875*/ GIMT_Encode4(433043),
    /*GILLT_s32*//*Label 5872*/ GIMT_Encode4(428810),
    /*GILLT_s64*//*Label 5873*/ GIMT_Encode4(430221),
    /*GILLT_v2s16*//*Label 5874*/ GIMT_Encode4(431632),
    // Label 5872: @428810
    GIM_Try, /*On fail goto*//*Label 5876*/ GIMT_Encode4(430220),
      GIM_CheckType, /*MI*/0, /*Op*/1, /*Type*/GILLT_s32,
      GIM_CheckType, /*MI*/0, /*Op*/2, /*Type*/GILLT_v4s32,
      GIM_CheckType, /*MI*/0, /*Op*/3, /*Type*/GILLT_s32,
      GIM_CheckType, /*MI*/0, /*Op*/4, /*Type*/GILLT_s32,
      GIM_CheckType, /*MI*/0, /*Op*/5, /*Type*/GILLT_s32,
      GIM_Try, /*On fail goto*//*Label 5877*/ GIMT_Encode4(428913), // Rule ID 5209 //
        GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasAtomicFaddNoRtnInsts_HasUnrestrictedSOffset),
        GIM_CheckHasNoUse, /*MI*/0,
        GIM_CheckConstantInt8, /*MI*/0, /*Op*/3, 0,
        GIM_CheckConstantInt8, /*MI*/0, /*Op*/4, 0,
        // MIs[0] offset
        GIM_CheckIsImm, /*MI*/0, /*Op*/6,
        // MIs[0] auxiliary
        GIM_CheckIsImm, /*MI*/0, /*Op*/7,
        // MIs[0] Operand 8
        GIM_CheckLiteralInt, /*MI*/0, /*Op*/8, GIMT_Encode8(0),
        GIM_CheckComplexPattern, /*MI*/0, /*Op*/5, /*Renderer*/GIMT_Encode2(0), GIMT_Encode2(GICP_gi_buf_soffset),
        // (SIbuffer_atomic_fadd:{ *:[f32] } f32:{ *:[f32] }:$vdata_in, v4i32:{ *:[v4i32] }:$rsrc, 0:{ *:[i32] }, 0:{ *:[i32] }, (BUFSOffset:{ *:[i32] } i32:{ *:[i32] }:$soffset), (timm:{ *:[i32] }):$offset, (timm:{ *:[i32] }):$auxiliary, 0:{ *:[i1] })<<P:Predicate_SIbuffer_atomic_fadd_noret>>  =>  (BUFFER_ATOMIC_ADD_F32_OFFSET anonymous_15037:{ *:[f32] }:$vdata_in, SReg_128:{ *:[v4i32] }:$rsrc, SCSrc_b32:{ *:[i32] }:$soffset, (timm:{ *:[i32] }):$offset, (extract_cpol:{ *:[i32] } ?:{ *:[i32] }:$auxiliary))
        GIR_BuildMI, /*InsnID*/0, /*Opcode*/GIMT_Encode2(AMDGPU::BUFFER_ATOMIC_ADD_F32_OFFSET),
        GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/1, // vdata_in
        GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/2, // rsrc
        GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/0, // soffset
        GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/6, // offset
        GIR_CustomOperandRenderer, /*InsnID*/0, /*OldInsnID*/0, /*OpIdx*/7, /*OperandRenderer*/GIMT_Encode2(GICR_renderExtractCPol), // auxiliary
        GIR_MergeMemOperands, /*InsnID*/0, /*NumInsns*/1, /*MergeInsnID's*/0,
        GIR_ConstrainSelectedInstOperands, /*InsnID*/0,
        GIR_EraseFromParent, /*InsnID*/0,
        // GIR_Coverage, 5209,
        GIR_Done,
      // Label 5877: @428913
      GIM_Try, /*On fail goto*//*Label 5878*/ GIMT_Encode4(428991), // Rule ID 5213 //
        GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasAtomicFaddNoRtnInsts),
        GIM_CheckHasNoUse, /*MI*/0,
        GIM_CheckConstantInt8, /*MI*/0, /*Op*/3, 0,
        GIM_CheckConstantInt8, /*MI*/0, /*Op*/4, 0,
        // MIs[0] offset
        GIM_CheckIsImm, /*MI*/0, /*Op*/6,
        // MIs[0] auxiliary
        GIM_CheckIsImm, /*MI*/0, /*Op*/7,
        // MIs[0] Operand 8
        GIM_CheckLiteralInt, /*MI*/0, /*Op*/8, GIMT_Encode8(0),
        GIM_CheckComplexPattern, /*MI*/0, /*Op*/5, /*Renderer*/GIMT_Encode2(0), GIMT_Encode2(GICP_gi_buf_soffset),
        // (SIbuffer_atomic_fadd:{ *:[f32] } f32:{ *:[f32] }:$vdata_in, v4i32:{ *:[v4i32] }:$rsrc, 0:{ *:[i32] }, 0:{ *:[i32] }, (BUFSOffset:{ *:[i32] } i32:{ *:[i32] }:$soffset), (timm:{ *:[i32] }):$offset, (timm:{ *:[i32] }):$auxiliary, 0:{ *:[i1] })<<P:Predicate_SIbuffer_atomic_fadd_noret>>  =>  (BUFFER_ATOMIC_ADD_F32_VBUFFER_OFFSET anonymous_15037:{ *:[f32] }:$vdata_in, SReg_128:{ *:[v4i32] }:$rsrc, SCSrc_b32:{ *:[i32] }:$soffset, (timm:{ *:[i32] }):$offset, (extract_cpol:{ *:[i32] } ?:{ *:[i32] }:$auxiliary))
        GIR_BuildMI, /*InsnID*/0, /*Opcode*/GIMT_Encode2(AMDGPU::BUFFER_ATOMIC_ADD_F32_VBUFFER_OFFSET),
        GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/1, // vdata_in
        GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/2, // rsrc
        GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/0, // soffset
        GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/6, // offset
        GIR_CustomOperandRenderer, /*InsnID*/0, /*OldInsnID*/0, /*OpIdx*/7, /*OperandRenderer*/GIMT_Encode2(GICR_renderExtractCPol), // auxiliary
        GIR_MergeMemOperands, /*InsnID*/0, /*NumInsns*/1, /*MergeInsnID's*/0,
        GIR_ConstrainSelectedInstOperands, /*InsnID*/0,
        GIR_EraseFromParent, /*InsnID*/0,
        // GIR_Coverage, 5213,
        GIR_Done,
      // Label 5878: @428991
      GIM_Try, /*On fail goto*//*Label 5879*/ GIMT_Encode4(429076), // Rule ID 5225 //
        GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasAtomicFaddRtnInsts_HasUnrestrictedSOffset),
        GIM_CheckRegBankForClass, /*MI*/0, /*Op*/0, /*RC*/GIMT_Encode2(AMDGPU::AV_32RegClassID),
        GIM_CheckConstantInt8, /*MI*/0, /*Op*/3, 0,
        GIM_CheckConstantInt8, /*MI*/0, /*Op*/4, 0,
        // MIs[0] offset
        GIM_CheckIsImm, /*MI*/0, /*Op*/6,
        // MIs[0] auxiliary
        GIM_CheckIsImm, /*MI*/0, /*Op*/7,
        // MIs[0] Operand 8
        GIM_CheckLiteralInt, /*MI*/0, /*Op*/8, GIMT_Encode8(0),
        GIM_CheckComplexPattern, /*MI*/0, /*Op*/5, /*Renderer*/GIMT_Encode2(0), GIMT_Encode2(GICP_gi_buf_soffset),
        // (SIbuffer_atomic_fadd:{ *:[f32] } f32:{ *:[f32] }:$vdata_in, v4i32:{ *:[v4i32] }:$rsrc, 0:{ *:[i32] }, 0:{ *:[i32] }, (BUFSOffset:{ *:[i32] } i32:{ *:[i32] }:$soffset), (timm:{ *:[i32] }):$offset, (timm:{ *:[i32] }):$auxiliary, 0:{ *:[i1] })  =>  (BUFFER_ATOMIC_ADD_F32_OFFSET_RTN:{ *:[f32] } anonymous_15037:{ *:[f32] }:$vdata_in, SReg_128:{ *:[v4i32] }:$rsrc, SCSrc_b32:{ *:[i32] }:$soffset, (timm:{ *:[i32] }):$offset, (extract_cpol_set_glc:{ *:[i32] } ?:{ *:[i32] }:$auxiliary))
        GIR_BuildMI, /*InsnID*/0, /*Opcode*/GIMT_Encode2(AMDGPU::BUFFER_ATOMIC_ADD_F32_OFFSET_RTN),
        GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/0, // DstI[vdata]
        GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/1, // vdata_in
        GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/2, // rsrc
        GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/0, // soffset
        GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/6, // offset
        GIR_CustomOperandRenderer, /*InsnID*/0, /*OldInsnID*/0, /*OpIdx*/7, /*OperandRenderer*/GIMT_Encode2(GICR_renderExtractCpolSetGLC), // auxiliary
        GIR_MergeMemOperands, /*InsnID*/0, /*NumInsns*/1, /*MergeInsnID's*/0,
        GIR_ConstrainSelectedInstOperands, /*InsnID*/0,
        GIR_EraseFromParent, /*InsnID*/0,
        // GIR_Coverage, 5225,
        GIR_Done,
      // Label 5879: @429076
      GIM_Try, /*On fail goto*//*Label 5880*/ GIMT_Encode4(429161), // Rule ID 5229 //
        GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasAtomicFaddRtnInsts),
        GIM_CheckRegBankForClass, /*MI*/0, /*Op*/0, /*RC*/GIMT_Encode2(AMDGPU::AV_32RegClassID),
        GIM_CheckConstantInt8, /*MI*/0, /*Op*/3, 0,
        GIM_CheckConstantInt8, /*MI*/0, /*Op*/4, 0,
        // MIs[0] offset
        GIM_CheckIsImm, /*MI*/0, /*Op*/6,
        // MIs[0] auxiliary
        GIM_CheckIsImm, /*MI*/0, /*Op*/7,
        // MIs[0] Operand 8
        GIM_CheckLiteralInt, /*MI*/0, /*Op*/8, GIMT_Encode8(0),
        GIM_CheckComplexPattern, /*MI*/0, /*Op*/5, /*Renderer*/GIMT_Encode2(0), GIMT_Encode2(GICP_gi_buf_soffset),
        // (SIbuffer_atomic_fadd:{ *:[f32] } f32:{ *:[f32] }:$vdata_in, v4i32:{ *:[v4i32] }:$rsrc, 0:{ *:[i32] }, 0:{ *:[i32] }, (BUFSOffset:{ *:[i32] } i32:{ *:[i32] }:$soffset), (timm:{ *:[i32] }):$offset, (timm:{ *:[i32] }):$auxiliary, 0:{ *:[i1] })  =>  (BUFFER_ATOMIC_ADD_F32_VBUFFER_OFFSET_RTN:{ *:[f32] } anonymous_15037:{ *:[f32] }:$vdata_in, SReg_128:{ *:[v4i32] }:$rsrc, SCSrc_b32:{ *:[i32] }:$soffset, (timm:{ *:[i32] }):$offset, (extract_cpol_set_glc:{ *:[i32] } ?:{ *:[i32] }:$auxiliary))
        GIR_BuildMI, /*InsnID*/0, /*Opcode*/GIMT_Encode2(AMDGPU::BUFFER_ATOMIC_ADD_F32_VBUFFER_OFFSET_RTN),
        GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/0, // DstI[vdata]
        GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/1, // vdata_in
        GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/2, // rsrc
        GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/0, // soffset
        GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/6, // offset
        GIR_CustomOperandRenderer, /*InsnID*/0, /*OldInsnID*/0, /*OpIdx*/7, /*OperandRenderer*/GIMT_Encode2(GICR_renderExtractCpolSetGLC), // auxiliary
        GIR_MergeMemOperands, /*InsnID*/0, /*NumInsns*/1, /*MergeInsnID's*/0,
        GIR_ConstrainSelectedInstOperands, /*InsnID*/0,
        GIR_EraseFromParent, /*InsnID*/0,
        // GIR_Coverage, 5229,
        GIR_Done,
      // Label 5880: @429161
      GIM_Try, /*On fail goto*//*Label 5881*/ GIMT_Encode4(429239), // Rule ID 5211 //
        GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasAtomicFaddNoRtnInsts_HasUnrestrictedSOffset),
        GIM_CheckHasNoUse, /*MI*/0,
        GIM_CheckConstantInt8, /*MI*/0, /*Op*/3, 0,
        // MIs[0] offset
        GIM_CheckIsImm, /*MI*/0, /*Op*/6,
        // MIs[0] auxiliary
        GIM_CheckIsImm, /*MI*/0, /*Op*/7,
        // MIs[0] Operand 8
        GIM_CheckLiteralInt, /*MI*/0, /*Op*/8, GIMT_Encode8(0),
        GIM_CheckComplexPattern, /*MI*/0, /*Op*/5, /*Renderer*/GIMT_Encode2(0), GIMT_Encode2(GICP_gi_buf_soffset),
        // (SIbuffer_atomic_fadd:{ *:[f32] } f32:{ *:[f32] }:$vdata_in, v4i32:{ *:[v4i32] }:$rsrc, 0:{ *:[i32] }, i32:{ *:[i32] }:$voffset, (BUFSOffset:{ *:[i32] } i32:{ *:[i32] }:$soffset), (timm:{ *:[i32] }):$offset, (timm:{ *:[i32] }):$auxiliary, 0:{ *:[i1] })<<P:Predicate_SIbuffer_atomic_fadd_noret>>  =>  (BUFFER_ATOMIC_ADD_F32_OFFEN anonymous_15037:{ *:[f32] }:$vdata_in, VGPR_32:{ *:[i32] }:$voffset, SReg_128:{ *:[v4i32] }:$rsrc, SCSrc_b32:{ *:[i32] }:$soffset, (timm:{ *:[i32] }):$offset, (extract_cpol:{ *:[i32] } ?:{ *:[i32] }:$auxiliary))
        GIR_BuildMI, /*InsnID*/0, /*Opcode*/GIMT_Encode2(AMDGPU::BUFFER_ATOMIC_ADD_F32_OFFEN),
        GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/1, // vdata_in
        GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/4, // voffset
        GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/2, // rsrc
        GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/0, // soffset
        GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/6, // offset
        GIR_CustomOperandRenderer, /*InsnID*/0, /*OldInsnID*/0, /*OpIdx*/7, /*OperandRenderer*/GIMT_Encode2(GICR_renderExtractCPol), // auxiliary
        GIR_MergeMemOperands, /*InsnID*/0, /*NumInsns*/1, /*MergeInsnID's*/0,
        GIR_ConstrainSelectedInstOperands, /*InsnID*/0,
        GIR_EraseFromParent, /*InsnID*/0,
        // GIR_Coverage, 5211,
        GIR_Done,
      // Label 5881: @429239
      GIM_Try, /*On fail goto*//*Label 5882*/ GIMT_Encode4(429317), // Rule ID 5215 //
        GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasAtomicFaddNoRtnInsts),
        GIM_CheckHasNoUse, /*MI*/0,
        GIM_CheckConstantInt8, /*MI*/0, /*Op*/3, 0,
        // MIs[0] offset
        GIM_CheckIsImm, /*MI*/0, /*Op*/6,
        // MIs[0] auxiliary
        GIM_CheckIsImm, /*MI*/0, /*Op*/7,
        // MIs[0] Operand 8
        GIM_CheckLiteralInt, /*MI*/0, /*Op*/8, GIMT_Encode8(0),
        GIM_CheckComplexPattern, /*MI*/0, /*Op*/5, /*Renderer*/GIMT_Encode2(0), GIMT_Encode2(GICP_gi_buf_soffset),
        // (SIbuffer_atomic_fadd:{ *:[f32] } f32:{ *:[f32] }:$vdata_in, v4i32:{ *:[v4i32] }:$rsrc, 0:{ *:[i32] }, i32:{ *:[i32] }:$voffset, (BUFSOffset:{ *:[i32] } i32:{ *:[i32] }:$soffset), (timm:{ *:[i32] }):$offset, (timm:{ *:[i32] }):$auxiliary, 0:{ *:[i1] })<<P:Predicate_SIbuffer_atomic_fadd_noret>>  =>  (BUFFER_ATOMIC_ADD_F32_VBUFFER_OFFEN anonymous_15037:{ *:[f32] }:$vdata_in, VGPR_32:{ *:[i32] }:$voffset, SReg_128:{ *:[v4i32] }:$rsrc, SCSrc_b32:{ *:[i32] }:$soffset, (timm:{ *:[i32] }):$offset, (extract_cpol:{ *:[i32] } ?:{ *:[i32] }:$auxiliary))
        GIR_BuildMI, /*InsnID*/0, /*Opcode*/GIMT_Encode2(AMDGPU::BUFFER_ATOMIC_ADD_F32_VBUFFER_OFFEN),
        GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/1, // vdata_in
        GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/4, // voffset
        GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/2, // rsrc
        GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/0, // soffset
        GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/6, // offset
        GIR_CustomOperandRenderer, /*InsnID*/0, /*OldInsnID*/0, /*OpIdx*/7, /*OperandRenderer*/GIMT_Encode2(GICR_renderExtractCPol), // auxiliary
        GIR_MergeMemOperands, /*InsnID*/0, /*NumInsns*/1, /*MergeInsnID's*/0,
        GIR_ConstrainSelectedInstOperands, /*InsnID*/0,
        GIR_EraseFromParent, /*InsnID*/0,
        // GIR_Coverage, 5215,
        GIR_Done,
      // Label 5882: @429317
      GIM_Try, /*On fail goto*//*Label 5883*/ GIMT_Encode4(429402), // Rule ID 5227 //
        GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasAtomicFaddRtnInsts_HasUnrestrictedSOffset),
        GIM_CheckRegBankForClass, /*MI*/0, /*Op*/0, /*RC*/GIMT_Encode2(AMDGPU::AV_32RegClassID),
        GIM_CheckConstantInt8, /*MI*/0, /*Op*/3, 0,
        // MIs[0] offset
        GIM_CheckIsImm, /*MI*/0, /*Op*/6,
        // MIs[0] auxiliary
        GIM_CheckIsImm, /*MI*/0, /*Op*/7,
        // MIs[0] Operand 8
        GIM_CheckLiteralInt, /*MI*/0, /*Op*/8, GIMT_Encode8(0),
        GIM_CheckComplexPattern, /*MI*/0, /*Op*/5, /*Renderer*/GIMT_Encode2(0), GIMT_Encode2(GICP_gi_buf_soffset),
        // (SIbuffer_atomic_fadd:{ *:[f32] } f32:{ *:[f32] }:$vdata_in, v4i32:{ *:[v4i32] }:$rsrc, 0:{ *:[i32] }, i32:{ *:[i32] }:$voffset, (BUFSOffset:{ *:[i32] } i32:{ *:[i32] }:$soffset), (timm:{ *:[i32] }):$offset, (timm:{ *:[i32] }):$auxiliary, 0:{ *:[i1] })  =>  (BUFFER_ATOMIC_ADD_F32_OFFEN_RTN:{ *:[f32] } anonymous_15037:{ *:[f32] }:$vdata_in, VGPR_32:{ *:[i32] }:$voffset, SReg_128:{ *:[v4i32] }:$rsrc, SCSrc_b32:{ *:[i32] }:$soffset, (timm:{ *:[i32] }):$offset, (extract_cpol_set_glc:{ *:[i32] } ?:{ *:[i32] }:$auxiliary))
        GIR_BuildMI, /*InsnID*/0, /*Opcode*/GIMT_Encode2(AMDGPU::BUFFER_ATOMIC_ADD_F32_OFFEN_RTN),
        GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/0, // DstI[vdata]
        GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/1, // vdata_in
        GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/4, // voffset
        GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/2, // rsrc
        GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/0, // soffset
        GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/6, // offset
        GIR_CustomOperandRenderer, /*InsnID*/0, /*OldInsnID*/0, /*OpIdx*/7, /*OperandRenderer*/GIMT_Encode2(GICR_renderExtractCpolSetGLC), // auxiliary
        GIR_MergeMemOperands, /*InsnID*/0, /*NumInsns*/1, /*MergeInsnID's*/0,
        GIR_ConstrainSelectedInstOperands, /*InsnID*/0,
        GIR_EraseFromParent, /*InsnID*/0,
        // GIR_Coverage, 5227,
        GIR_Done,
      // Label 5883: @429402
      GIM_Try, /*On fail goto*//*Label 5884*/ GIMT_Encode4(429487), // Rule ID 5231 //
        GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasAtomicFaddRtnInsts),
        GIM_CheckRegBankForClass, /*MI*/0, /*Op*/0, /*RC*/GIMT_Encode2(AMDGPU::AV_32RegClassID),
        GIM_CheckConstantInt8, /*MI*/0, /*Op*/3, 0,
        // MIs[0] offset
        GIM_CheckIsImm, /*MI*/0, /*Op*/6,
        // MIs[0] auxiliary
        GIM_CheckIsImm, /*MI*/0, /*Op*/7,
        // MIs[0] Operand 8
        GIM_CheckLiteralInt, /*MI*/0, /*Op*/8, GIMT_Encode8(0),
        GIM_CheckComplexPattern, /*MI*/0, /*Op*/5, /*Renderer*/GIMT_Encode2(0), GIMT_Encode2(GICP_gi_buf_soffset),
        // (SIbuffer_atomic_fadd:{ *:[f32] } f32:{ *:[f32] }:$vdata_in, v4i32:{ *:[v4i32] }:$rsrc, 0:{ *:[i32] }, i32:{ *:[i32] }:$voffset, (BUFSOffset:{ *:[i32] } i32:{ *:[i32] }:$soffset), (timm:{ *:[i32] }):$offset, (timm:{ *:[i32] }):$auxiliary, 0:{ *:[i1] })  =>  (BUFFER_ATOMIC_ADD_F32_VBUFFER_OFFEN_RTN:{ *:[f32] } anonymous_15037:{ *:[f32] }:$vdata_in, VGPR_32:{ *:[i32] }:$voffset, SReg_128:{ *:[v4i32] }:$rsrc, SCSrc_b32:{ *:[i32] }:$soffset, (timm:{ *:[i32] }):$offset, (extract_cpol_set_glc:{ *:[i32] } ?:{ *:[i32] }:$auxiliary))
        GIR_BuildMI, /*InsnID*/0, /*Opcode*/GIMT_Encode2(AMDGPU::BUFFER_ATOMIC_ADD_F32_VBUFFER_OFFEN_RTN),
        GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/0, // DstI[vdata]
        GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/1, // vdata_in
        GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/4, // voffset
        GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/2, // rsrc
        GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/0, // soffset
        GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/6, // offset
        GIR_CustomOperandRenderer, /*InsnID*/0, /*OldInsnID*/0, /*OpIdx*/7, /*OperandRenderer*/GIMT_Encode2(GICR_renderExtractCpolSetGLC), // auxiliary
        GIR_MergeMemOperands, /*InsnID*/0, /*NumInsns*/1, /*MergeInsnID's*/0,
        GIR_ConstrainSelectedInstOperands, /*InsnID*/0,
        GIR_EraseFromParent, /*InsnID*/0,
        // GIR_Coverage, 5231,
        GIR_Done,
      // Label 5884: @429487
      GIM_Try, /*On fail goto*//*Label 5885*/ GIMT_Encode4(429557), // Rule ID 5210 //
        GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasAtomicFaddNoRtnInsts_HasUnrestrictedSOffset),
        GIM_CheckHasNoUse, /*MI*/0,
        GIM_CheckConstantInt8, /*MI*/0, /*Op*/4, 0,
        // MIs[0] offset
        GIM_CheckIsImm, /*MI*/0, /*Op*/6,
        // MIs[0] auxiliary
        GIM_CheckIsImm, /*MI*/0, /*Op*/7,
        // MIs[0] Operand 8
        GIM_CheckIsImm, /*MI*/0, /*Op*/8,
        GIM_CheckComplexPattern, /*MI*/0, /*Op*/5, /*Renderer*/GIMT_Encode2(0), GIMT_Encode2(GICP_gi_buf_soffset),
        // (SIbuffer_atomic_fadd:{ *:[f32] } f32:{ *:[f32] }:$vdata_in, v4i32:{ *:[v4i32] }:$rsrc, i32:{ *:[i32] }:$vindex, 0:{ *:[i32] }, (BUFSOffset:{ *:[i32] } i32:{ *:[i32] }:$soffset), (timm:{ *:[i32] }):$offset, (timm:{ *:[i32] }):$auxiliary, (timm:{ *:[i1] }))<<P:Predicate_SIbuffer_atomic_fadd_noret>>  =>  (BUFFER_ATOMIC_ADD_F32_IDXEN anonymous_15037:{ *:[f32] }:$vdata_in, VGPR_32:{ *:[i32] }:$vindex, SReg_128:{ *:[v4i32] }:$rsrc, SCSrc_b32:{ *:[i32] }:$soffset, (timm:{ *:[i32] }):$offset, (extract_cpol:{ *:[i32] } ?:{ *:[i32] }:$auxiliary))
        GIR_BuildMI, /*InsnID*/0, /*Opcode*/GIMT_Encode2(AMDGPU::BUFFER_ATOMIC_ADD_F32_IDXEN),
        GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/1, // vdata_in
        GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/3, // vindex
        GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/2, // rsrc
        GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/0, // soffset
        GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/6, // offset
        GIR_CustomOperandRenderer, /*InsnID*/0, /*OldInsnID*/0, /*OpIdx*/7, /*OperandRenderer*/GIMT_Encode2(GICR_renderExtractCPol), // auxiliary
        GIR_MergeMemOperands, /*InsnID*/0, /*NumInsns*/1, /*MergeInsnID's*/0,
        GIR_ConstrainSelectedInstOperands, /*InsnID*/0,
        GIR_EraseFromParent, /*InsnID*/0,
        // GIR_Coverage, 5210,
        GIR_Done,
      // Label 5885: @429557
      GIM_Try, /*On fail goto*//*Label 5886*/ GIMT_Encode4(429627), // Rule ID 5214 //
        GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasAtomicFaddNoRtnInsts),
        GIM_CheckHasNoUse, /*MI*/0,
        GIM_CheckConstantInt8, /*MI*/0, /*Op*/4, 0,
        // MIs[0] offset
        GIM_CheckIsImm, /*MI*/0, /*Op*/6,
        // MIs[0] auxiliary
        GIM_CheckIsImm, /*MI*/0, /*Op*/7,
        // MIs[0] Operand 8
        GIM_CheckIsImm, /*MI*/0, /*Op*/8,
        GIM_CheckComplexPattern, /*MI*/0, /*Op*/5, /*Renderer*/GIMT_Encode2(0), GIMT_Encode2(GICP_gi_buf_soffset),
        // (SIbuffer_atomic_fadd:{ *:[f32] } f32:{ *:[f32] }:$vdata_in, v4i32:{ *:[v4i32] }:$rsrc, i32:{ *:[i32] }:$vindex, 0:{ *:[i32] }, (BUFSOffset:{ *:[i32] } i32:{ *:[i32] }:$soffset), (timm:{ *:[i32] }):$offset, (timm:{ *:[i32] }):$auxiliary, (timm:{ *:[i1] }))<<P:Predicate_SIbuffer_atomic_fadd_noret>>  =>  (BUFFER_ATOMIC_ADD_F32_VBUFFER_IDXEN anonymous_15037:{ *:[f32] }:$vdata_in, VGPR_32:{ *:[i32] }:$vindex, SReg_128:{ *:[v4i32] }:$rsrc, SCSrc_b32:{ *:[i32] }:$soffset, (timm:{ *:[i32] }):$offset, (extract_cpol:{ *:[i32] } ?:{ *:[i32] }:$auxiliary))
        GIR_BuildMI, /*InsnID*/0, /*Opcode*/GIMT_Encode2(AMDGPU::BUFFER_ATOMIC_ADD_F32_VBUFFER_IDXEN),
        GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/1, // vdata_in
        GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/3, // vindex
        GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/2, // rsrc
        GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/0, // soffset
        GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/6, // offset
        GIR_CustomOperandRenderer, /*InsnID*/0, /*OldInsnID*/0, /*OpIdx*/7, /*OperandRenderer*/GIMT_Encode2(GICR_renderExtractCPol), // auxiliary
        GIR_MergeMemOperands, /*InsnID*/0, /*NumInsns*/1, /*MergeInsnID's*/0,
        GIR_ConstrainSelectedInstOperands, /*InsnID*/0,
        GIR_EraseFromParent, /*InsnID*/0,
        // GIR_Coverage, 5214,
        GIR_Done,
      // Label 5886: @429627
      GIM_Try, /*On fail goto*//*Label 5887*/ GIMT_Encode4(429704), // Rule ID 5226 //
        GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasAtomicFaddRtnInsts_HasUnrestrictedSOffset),
        GIM_CheckRegBankForClass, /*MI*/0, /*Op*/0, /*RC*/GIMT_Encode2(AMDGPU::AV_32RegClassID),
        GIM_CheckConstantInt8, /*MI*/0, /*Op*/4, 0,
        // MIs[0] offset
        GIM_CheckIsImm, /*MI*/0, /*Op*/6,
        // MIs[0] auxiliary
        GIM_CheckIsImm, /*MI*/0, /*Op*/7,
        // MIs[0] Operand 8
        GIM_CheckIsImm, /*MI*/0, /*Op*/8,
        GIM_CheckComplexPattern, /*MI*/0, /*Op*/5, /*Renderer*/GIMT_Encode2(0), GIMT_Encode2(GICP_gi_buf_soffset),
        // (SIbuffer_atomic_fadd:{ *:[f32] } f32:{ *:[f32] }:$vdata_in, v4i32:{ *:[v4i32] }:$rsrc, i32:{ *:[i32] }:$vindex, 0:{ *:[i32] }, (BUFSOffset:{ *:[i32] } i32:{ *:[i32] }:$soffset), (timm:{ *:[i32] }):$offset, (timm:{ *:[i32] }):$auxiliary, (timm:{ *:[i1] }))  =>  (BUFFER_ATOMIC_ADD_F32_IDXEN_RTN:{ *:[f32] } anonymous_15037:{ *:[f32] }:$vdata_in, VGPR_32:{ *:[i32] }:$vindex, SReg_128:{ *:[v4i32] }:$rsrc, SCSrc_b32:{ *:[i32] }:$soffset, (timm:{ *:[i32] }):$offset, (extract_cpol_set_glc:{ *:[i32] } ?:{ *:[i32] }:$auxiliary))
        GIR_BuildMI, /*InsnID*/0, /*Opcode*/GIMT_Encode2(AMDGPU::BUFFER_ATOMIC_ADD_F32_IDXEN_RTN),
        GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/0, // DstI[vdata]
        GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/1, // vdata_in
        GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/3, // vindex
        GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/2, // rsrc
        GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/0, // soffset
        GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/6, // offset
        GIR_CustomOperandRenderer, /*InsnID*/0, /*OldInsnID*/0, /*OpIdx*/7, /*OperandRenderer*/GIMT_Encode2(GICR_renderExtractCpolSetGLC), // auxiliary
        GIR_MergeMemOperands, /*InsnID*/0, /*NumInsns*/1, /*MergeInsnID's*/0,
        GIR_ConstrainSelectedInstOperands, /*InsnID*/0,
        GIR_EraseFromParent, /*InsnID*/0,
        // GIR_Coverage, 5226,
        GIR_Done,
      // Label 5887: @429704
      GIM_Try, /*On fail goto*//*Label 5888*/ GIMT_Encode4(429781), // Rule ID 5230 //
        GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasAtomicFaddRtnInsts),
        GIM_CheckRegBankForClass, /*MI*/0, /*Op*/0, /*RC*/GIMT_Encode2(AMDGPU::AV_32RegClassID),
        GIM_CheckConstantInt8, /*MI*/0, /*Op*/4, 0,
        // MIs[0] offset
        GIM_CheckIsImm, /*MI*/0, /*Op*/6,
        // MIs[0] auxiliary
        GIM_CheckIsImm, /*MI*/0, /*Op*/7,
        // MIs[0] Operand 8
        GIM_CheckIsImm, /*MI*/0, /*Op*/8,
        GIM_CheckComplexPattern, /*MI*/0, /*Op*/5, /*Renderer*/GIMT_Encode2(0), GIMT_Encode2(GICP_gi_buf_soffset),
        // (SIbuffer_atomic_fadd:{ *:[f32] } f32:{ *:[f32] }:$vdata_in, v4i32:{ *:[v4i32] }:$rsrc, i32:{ *:[i32] }:$vindex, 0:{ *:[i32] }, (BUFSOffset:{ *:[i32] } i32:{ *:[i32] }:$soffset), (timm:{ *:[i32] }):$offset, (timm:{ *:[i32] }):$auxiliary, (timm:{ *:[i1] }))  =>  (BUFFER_ATOMIC_ADD_F32_VBUFFER_IDXEN_RTN:{ *:[f32] } anonymous_15037:{ *:[f32] }:$vdata_in, VGPR_32:{ *:[i32] }:$vindex, SReg_128:{ *:[v4i32] }:$rsrc, SCSrc_b32:{ *:[i32] }:$soffset, (timm:{ *:[i32] }):$offset, (extract_cpol_set_glc:{ *:[i32] } ?:{ *:[i32] }:$auxiliary))
        GIR_BuildMI, /*InsnID*/0, /*Opcode*/GIMT_Encode2(AMDGPU::BUFFER_ATOMIC_ADD_F32_VBUFFER_IDXEN_RTN),
        GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/0, // DstI[vdata]
        GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/1, // vdata_in
        GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/3, // vindex
        GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/2, // rsrc
        GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/0, // soffset
        GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/6, // offset
        GIR_CustomOperandRenderer, /*InsnID*/0, /*OldInsnID*/0, /*OpIdx*/7, /*OperandRenderer*/GIMT_Encode2(GICR_renderExtractCpolSetGLC), // auxiliary
        GIR_MergeMemOperands, /*InsnID*/0, /*NumInsns*/1, /*MergeInsnID's*/0,
        GIR_ConstrainSelectedInstOperands, /*InsnID*/0,
        GIR_EraseFromParent, /*InsnID*/0,
        // GIR_Coverage, 5230,
        GIR_Done,
      // Label 5888: @429781
      GIM_Try, /*On fail goto*//*Label 5889*/ GIMT_Encode4(429887), // Rule ID 5212 //
        GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasAtomicFaddNoRtnInsts_HasUnrestrictedSOffset),
        GIM_CheckHasNoUse, /*MI*/0,
        // MIs[0] offset
        GIM_CheckIsImm, /*MI*/0, /*Op*/6,
        // MIs[0] auxiliary
        GIM_CheckIsImm, /*MI*/0, /*Op*/7,
        // MIs[0] Operand 8
        GIM_CheckIsImm, /*MI*/0, /*Op*/8,
        GIM_CheckComplexPattern, /*MI*/0, /*Op*/5, /*Renderer*/GIMT_Encode2(0), GIMT_Encode2(GICP_gi_buf_soffset),
        // (SIbuffer_atomic_fadd:{ *:[f32] } f32:{ *:[f32] }:$vdata_in, v4i32:{ *:[v4i32] }:$rsrc, i32:{ *:[i32] }:$vindex, i32:{ *:[i32] }:$voffset, (BUFSOffset:{ *:[i32] } i32:{ *:[i32] }:$soffset), (timm:{ *:[i32] }):$offset, (timm:{ *:[i32] }):$auxiliary, (timm:{ *:[i1] }))<<P:Predicate_SIbuffer_atomic_fadd_noret>>  =>  (BUFFER_ATOMIC_ADD_F32_BOTHEN anonymous_15037:{ *:[f32] }:$vdata_in, (REG_SEQUENCE:{ *:[i64] } VReg_64:{ *:[i32] }, VGPR_32:{ *:[i32] }:$vindex, sub0:{ *:[i32] }, VGPR_32:{ *:[i32] }:$voffset, sub1:{ *:[i32] }), SReg_128:{ *:[v4i32] }:$rsrc, SCSrc_b32:{ *:[i32] }:$soffset, (timm:{ *:[i32] }):$offset, (extract_cpol:{ *:[i32] } ?:{ *:[i32] }:$auxiliary))
        GIR_MakeTempReg, /*TempRegID*/0, /*TypeID*/GILLT_s64,
        GIR_BuildMI, /*InsnID*/1, /*Opcode*/GIMT_Encode2(TargetOpcode::REG_SEQUENCE),
        GIR_AddTempRegister, /*InsnID*/1, /*TempRegID*/0, /*TempRegFlags*/GIMT_Encode2(RegState::Define),
        GIR_Copy, /*NewInsnID*/1, /*OldInsnID*/0, /*OpIdx*/3, // vindex
        GIR_AddImm8, /*InsnID*/1, /*SubRegIndex*/3,
        GIR_Copy, /*NewInsnID*/1, /*OldInsnID*/0, /*OpIdx*/4, // voffset
        GIR_AddImm8, /*InsnID*/1, /*SubRegIndex*/11,
        GIR_ConstrainOperandRC, /*InsnID*/1, /*Op*/0, GIMT_Encode2(AMDGPU::VReg_64RegClassID),
        GIR_ConstrainOperandRC, /*InsnID*/1, /*Op*/1, GIMT_Encode2(AMDGPU::VGPR_32RegClassID),
        GIR_ConstrainOperandRC, /*InsnID*/1, /*Op*/3, GIMT_Encode2(AMDGPU::VGPR_32RegClassID),
        GIR_BuildMI, /*InsnID*/0, /*Opcode*/GIMT_Encode2(AMDGPU::BUFFER_ATOMIC_ADD_F32_BOTHEN),
        GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/1, // vdata_in
        GIR_AddSimpleTempRegister, /*InsnID*/0, /*TempRegID*/0,
        GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/2, // rsrc
        GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/0, // soffset
        GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/6, // offset
        GIR_CustomOperandRenderer, /*InsnID*/0, /*OldInsnID*/0, /*OpIdx*/7, /*OperandRenderer*/GIMT_Encode2(GICR_renderExtractCPol), // auxiliary
        GIR_MergeMemOperands, /*InsnID*/0, /*NumInsns*/1, /*MergeInsnID's*/0,
        GIR_ConstrainSelectedInstOperands, /*InsnID*/0,
        GIR_EraseFromParent, /*InsnID*/0,
        // GIR_Coverage, 5212,
        GIR_Done,
      // Label 5889: @429887
      GIM_Try, /*On fail goto*//*Label 5890*/ GIMT_Encode4(429993), // Rule ID 5216 //
        GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasAtomicFaddNoRtnInsts),
        GIM_CheckHasNoUse, /*MI*/0,
        // MIs[0] offset
        GIM_CheckIsImm, /*MI*/0, /*Op*/6,
        // MIs[0] auxiliary
        GIM_CheckIsImm, /*MI*/0, /*Op*/7,
        // MIs[0] Operand 8
        GIM_CheckIsImm, /*MI*/0, /*Op*/8,
        GIM_CheckComplexPattern, /*MI*/0, /*Op*/5, /*Renderer*/GIMT_Encode2(0), GIMT_Encode2(GICP_gi_buf_soffset),
        // (SIbuffer_atomic_fadd:{ *:[f32] } f32:{ *:[f32] }:$vdata_in, v4i32:{ *:[v4i32] }:$rsrc, i32:{ *:[i32] }:$vindex, i32:{ *:[i32] }:$voffset, (BUFSOffset:{ *:[i32] } i32:{ *:[i32] }:$soffset), (timm:{ *:[i32] }):$offset, (timm:{ *:[i32] }):$auxiliary, (timm:{ *:[i1] }))<<P:Predicate_SIbuffer_atomic_fadd_noret>>  =>  (BUFFER_ATOMIC_ADD_F32_VBUFFER_BOTHEN anonymous_15037:{ *:[f32] }:$vdata_in, (REG_SEQUENCE:{ *:[i64] } VReg_64:{ *:[i32] }, VGPR_32:{ *:[i32] }:$vindex, sub0:{ *:[i32] }, VGPR_32:{ *:[i32] }:$voffset, sub1:{ *:[i32] }), SReg_128:{ *:[v4i32] }:$rsrc, SCSrc_b32:{ *:[i32] }:$soffset, (timm:{ *:[i32] }):$offset, (extract_cpol:{ *:[i32] } ?:{ *:[i32] }:$auxiliary))
        GIR_MakeTempReg, /*TempRegID*/0, /*TypeID*/GILLT_s64,
        GIR_BuildMI, /*InsnID*/1, /*Opcode*/GIMT_Encode2(TargetOpcode::REG_SEQUENCE),
        GIR_AddTempRegister, /*InsnID*/1, /*TempRegID*/0, /*TempRegFlags*/GIMT_Encode2(RegState::Define),
        GIR_Copy, /*NewInsnID*/1, /*OldInsnID*/0, /*OpIdx*/3, // vindex
        GIR_AddImm8, /*InsnID*/1, /*SubRegIndex*/3,
        GIR_Copy, /*NewInsnID*/1, /*OldInsnID*/0, /*OpIdx*/4, // voffset
        GIR_AddImm8, /*InsnID*/1, /*SubRegIndex*/11,
        GIR_ConstrainOperandRC, /*InsnID*/1, /*Op*/0, GIMT_Encode2(AMDGPU::VReg_64RegClassID),
        GIR_ConstrainOperandRC, /*InsnID*/1, /*Op*/1, GIMT_Encode2(AMDGPU::VGPR_32RegClassID),
        GIR_ConstrainOperandRC, /*InsnID*/1, /*Op*/3, GIMT_Encode2(AMDGPU::VGPR_32RegClassID),
        GIR_BuildMI, /*InsnID*/0, /*Opcode*/GIMT_Encode2(AMDGPU::BUFFER_ATOMIC_ADD_F32_VBUFFER_BOTHEN),
        GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/1, // vdata_in
        GIR_AddSimpleTempRegister, /*InsnID*/0, /*TempRegID*/0,
        GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/2, // rsrc
        GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/0, // soffset
        GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/6, // offset
        GIR_CustomOperandRenderer, /*InsnID*/0, /*OldInsnID*/0, /*OpIdx*/7, /*OperandRenderer*/GIMT_Encode2(GICR_renderExtractCPol), // auxiliary
        GIR_MergeMemOperands, /*InsnID*/0, /*NumInsns*/1, /*MergeInsnID's*/0,
        GIR_ConstrainSelectedInstOperands, /*InsnID*/0,
        GIR_EraseFromParent, /*InsnID*/0,
        // GIR_Coverage, 5216,
        GIR_Done,
      // Label 5890: @429993
      GIM_Try, /*On fail goto*//*Label 5891*/ GIMT_Encode4(430106), // Rule ID 5228 //
        GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasAtomicFaddRtnInsts_HasUnrestrictedSOffset),
        GIM_CheckRegBankForClass, /*MI*/0, /*Op*/0, /*RC*/GIMT_Encode2(AMDGPU::AV_32RegClassID),
        // MIs[0] offset
        GIM_CheckIsImm, /*MI*/0, /*Op*/6,
        // MIs[0] auxiliary
        GIM_CheckIsImm, /*MI*/0, /*Op*/7,
        // MIs[0] Operand 8
        GIM_CheckIsImm, /*MI*/0, /*Op*/8,
        GIM_CheckComplexPattern, /*MI*/0, /*Op*/5, /*Renderer*/GIMT_Encode2(0), GIMT_Encode2(GICP_gi_buf_soffset),
        // (SIbuffer_atomic_fadd:{ *:[f32] } f32:{ *:[f32] }:$vdata_in, v4i32:{ *:[v4i32] }:$rsrc, i32:{ *:[i32] }:$vindex, i32:{ *:[i32] }:$voffset, (BUFSOffset:{ *:[i32] } i32:{ *:[i32] }:$soffset), (timm:{ *:[i32] }):$offset, (timm:{ *:[i32] }):$auxiliary, (timm:{ *:[i1] }))  =>  (BUFFER_ATOMIC_ADD_F32_BOTHEN_RTN:{ *:[f32] } anonymous_15037:{ *:[f32] }:$vdata_in, (REG_SEQUENCE:{ *:[i64] } VReg_64:{ *:[i32] }, VGPR_32:{ *:[i32] }:$vindex, sub0:{ *:[i32] }, VGPR_32:{ *:[i32] }:$voffset, sub1:{ *:[i32] }), SReg_128:{ *:[v4i32] }:$rsrc, SCSrc_b32:{ *:[i32] }:$soffset, (timm:{ *:[i32] }):$offset, (extract_cpol_set_glc:{ *:[i32] } ?:{ *:[i32] }:$auxiliary))
        GIR_MakeTempReg, /*TempRegID*/0, /*TypeID*/GILLT_s64,
        GIR_BuildMI, /*InsnID*/1, /*Opcode*/GIMT_Encode2(TargetOpcode::REG_SEQUENCE),
        GIR_AddTempRegister, /*InsnID*/1, /*TempRegID*/0, /*TempRegFlags*/GIMT_Encode2(RegState::Define),
        GIR_Copy, /*NewInsnID*/1, /*OldInsnID*/0, /*OpIdx*/3, // vindex
        GIR_AddImm8, /*InsnID*/1, /*SubRegIndex*/3,
        GIR_Copy, /*NewInsnID*/1, /*OldInsnID*/0, /*OpIdx*/4, // voffset
        GIR_AddImm8, /*InsnID*/1, /*SubRegIndex*/11,
        GIR_ConstrainOperandRC, /*InsnID*/1, /*Op*/0, GIMT_Encode2(AMDGPU::VReg_64RegClassID),
        GIR_ConstrainOperandRC, /*InsnID*/1, /*Op*/1, GIMT_Encode2(AMDGPU::VGPR_32RegClassID),
        GIR_ConstrainOperandRC, /*InsnID*/1, /*Op*/3, GIMT_Encode2(AMDGPU::VGPR_32RegClassID),
        GIR_BuildMI, /*InsnID*/0, /*Opcode*/GIMT_Encode2(AMDGPU::BUFFER_ATOMIC_ADD_F32_BOTHEN_RTN),
        GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/0, // DstI[vdata]
        GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/1, // vdata_in
        GIR_AddSimpleTempRegister, /*InsnID*/0, /*TempRegID*/0,
        GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/2, // rsrc
        GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/0, // soffset
        GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/6, // offset
        GIR_CustomOperandRenderer, /*InsnID*/0, /*OldInsnID*/0, /*OpIdx*/7, /*OperandRenderer*/GIMT_Encode2(GICR_renderExtractCpolSetGLC), // auxiliary
        GIR_MergeMemOperands, /*InsnID*/0, /*NumInsns*/1, /*MergeInsnID's*/0,
        GIR_ConstrainSelectedInstOperands, /*InsnID*/0,
        GIR_EraseFromParent, /*InsnID*/0,
        // GIR_Coverage, 5228,
        GIR_Done,
      // Label 5891: @430106
      GIM_Try, /*On fail goto*//*Label 5892*/ GIMT_Encode4(430219), // Rule ID 5232 //
        GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasAtomicFaddRtnInsts),
        GIM_CheckRegBankForClass, /*MI*/0, /*Op*/0, /*RC*/GIMT_Encode2(AMDGPU::AV_32RegClassID),
        // MIs[0] offset
        GIM_CheckIsImm, /*MI*/0, /*Op*/6,
        // MIs[0] auxiliary
        GIM_CheckIsImm, /*MI*/0, /*Op*/7,
        // MIs[0] Operand 8
        GIM_CheckIsImm, /*MI*/0, /*Op*/8,
        GIM_CheckComplexPattern, /*MI*/0, /*Op*/5, /*Renderer*/GIMT_Encode2(0), GIMT_Encode2(GICP_gi_buf_soffset),
        // (SIbuffer_atomic_fadd:{ *:[f32] } f32:{ *:[f32] }:$vdata_in, v4i32:{ *:[v4i32] }:$rsrc, i32:{ *:[i32] }:$vindex, i32:{ *:[i32] }:$voffset, (BUFSOffset:{ *:[i32] } i32:{ *:[i32] }:$soffset), (timm:{ *:[i32] }):$offset, (timm:{ *:[i32] }):$auxiliary, (timm:{ *:[i1] }))  =>  (BUFFER_ATOMIC_ADD_F32_VBUFFER_BOTHEN_RTN:{ *:[f32] } anonymous_15037:{ *:[f32] }:$vdata_in, (REG_SEQUENCE:{ *:[i64] } VReg_64:{ *:[i32] }, VGPR_32:{ *:[i32] }:$vindex, sub0:{ *:[i32] }, VGPR_32:{ *:[i32] }:$voffset, sub1:{ *:[i32] }), SReg_128:{ *:[v4i32] }:$rsrc, SCSrc_b32:{ *:[i32] }:$soffset, (timm:{ *:[i32] }):$offset, (extract_cpol_set_glc:{ *:[i32] } ?:{ *:[i32] }:$auxiliary))
        GIR_MakeTempReg, /*TempRegID*/0, /*TypeID*/GILLT_s64,
        GIR_BuildMI, /*InsnID*/1, /*Opcode*/GIMT_Encode2(TargetOpcode::REG_SEQUENCE),
        GIR_AddTempRegister, /*InsnID*/1, /*TempRegID*/0, /*TempRegFlags*/GIMT_Encode2(RegState::Define),
        GIR_Copy, /*NewInsnID*/1, /*OldInsnID*/0, /*OpIdx*/3, // vindex
        GIR_AddImm8, /*InsnID*/1, /*SubRegIndex*/3,
        GIR_Copy, /*NewInsnID*/1, /*OldInsnID*/0, /*OpIdx*/4, // voffset
        GIR_AddImm8, /*InsnID*/1, /*SubRegIndex*/11,
        GIR_ConstrainOperandRC, /*InsnID*/1, /*Op*/0, GIMT_Encode2(AMDGPU::VReg_64RegClassID),
        GIR_ConstrainOperandRC, /*InsnID*/1, /*Op*/1, GIMT_Encode2(AMDGPU::VGPR_32RegClassID),
        GIR_ConstrainOperandRC, /*InsnID*/1, /*Op*/3, GIMT_Encode2(AMDGPU::VGPR_32RegClassID),
        GIR_BuildMI, /*InsnID*/0, /*Opcode*/GIMT_Encode2(AMDGPU::BUFFER_ATOMIC_ADD_F32_VBUFFER_BOTHEN_RTN),
        GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/0, // DstI[vdata]
        GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/1, // vdata_in
        GIR_AddSimpleTempRegister, /*InsnID*/0, /*TempRegID*/0,
        GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/2, // rsrc
        GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/0, // soffset
        GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/6, // offset
        GIR_CustomOperandRenderer, /*InsnID*/0, /*OldInsnID*/0, /*OpIdx*/7, /*OperandRenderer*/GIMT_Encode2(GICR_renderExtractCpolSetGLC), // auxiliary
        GIR_MergeMemOperands, /*InsnID*/0, /*NumInsns*/1, /*MergeInsnID's*/0,
        GIR_ConstrainSelectedInstOperands, /*InsnID*/0,
        GIR_EraseFromParent, /*InsnID*/0,
        // GIR_Coverage, 5232,
        GIR_Done,
      // Label 5892: @430219
      GIM_Reject,
    // Label 5876: @430220
    GIM_Reject,
    // Label 5873: @430221
    GIM_Try, /*On fail goto*//*Label 5893*/ GIMT_Encode4(431631),
      GIM_CheckType, /*MI*/0, /*Op*/1, /*Type*/GILLT_s64,
      GIM_CheckType, /*MI*/0, /*Op*/2, /*Type*/GILLT_v4s32,
      GIM_CheckType, /*MI*/0, /*Op*/3, /*Type*/GILLT_s32,
      GIM_CheckType, /*MI*/0, /*Op*/4, /*Type*/GILLT_s32,
      GIM_CheckType, /*MI*/0, /*Op*/5, /*Type*/GILLT_s32,
      GIM_Try, /*On fail goto*//*Label 5894*/ GIMT_Encode4(430324), // Rule ID 5245 //
        GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasUnrestrictedSOffset_isGFX90APlus),
        GIM_CheckHasNoUse, /*MI*/0,
        GIM_CheckConstantInt8, /*MI*/0, /*Op*/3, 0,
        GIM_CheckConstantInt8, /*MI*/0, /*Op*/4, 0,
        // MIs[0] offset
        GIM_CheckIsImm, /*MI*/0, /*Op*/6,
        // MIs[0] auxiliary
        GIM_CheckIsImm, /*MI*/0, /*Op*/7,
        // MIs[0] Operand 8
        GIM_CheckLiteralInt, /*MI*/0, /*Op*/8, GIMT_Encode8(0),
        GIM_CheckComplexPattern, /*MI*/0, /*Op*/5, /*Renderer*/GIMT_Encode2(0), GIMT_Encode2(GICP_gi_buf_soffset),
        // (SIbuffer_atomic_fadd:{ *:[f64] } f64:{ *:[f64] }:$vdata_in, v4i32:{ *:[v4i32] }:$rsrc, 0:{ *:[i32] }, 0:{ *:[i32] }, (BUFSOffset:{ *:[i32] } i32:{ *:[i32] }:$soffset), (timm:{ *:[i32] }):$offset, (timm:{ *:[i32] }):$auxiliary, 0:{ *:[i1] })<<P:Predicate_SIbuffer_atomic_fadd_noret>>  =>  (BUFFER_ATOMIC_ADD_F64_OFFSET anonymous_15036:{ *:[f64] }:$vdata_in, SReg_128:{ *:[v4i32] }:$rsrc, SCSrc_b32:{ *:[i32] }:$soffset, (timm:{ *:[i32] }):$offset, (extract_cpol:{ *:[i32] } ?:{ *:[i32] }:$auxiliary))
        GIR_BuildMI, /*InsnID*/0, /*Opcode*/GIMT_Encode2(AMDGPU::BUFFER_ATOMIC_ADD_F64_OFFSET),
        GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/1, // vdata_in
        GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/2, // rsrc
        GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/0, // soffset
        GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/6, // offset
        GIR_CustomOperandRenderer, /*InsnID*/0, /*OldInsnID*/0, /*OpIdx*/7, /*OperandRenderer*/GIMT_Encode2(GICR_renderExtractCPol), // auxiliary
        GIR_MergeMemOperands, /*InsnID*/0, /*NumInsns*/1, /*MergeInsnID's*/0,
        GIR_ConstrainSelectedInstOperands, /*InsnID*/0,
        GIR_EraseFromParent, /*InsnID*/0,
        // GIR_Coverage, 5245,
        GIR_Done,
      // Label 5894: @430324
      GIM_Try, /*On fail goto*//*Label 5895*/ GIMT_Encode4(430402), // Rule ID 5253 //
        GIM_CheckFeatures, GIMT_Encode2(GIFBS_isGFX90APlus),
        GIM_CheckHasNoUse, /*MI*/0,
        GIM_CheckConstantInt8, /*MI*/0, /*Op*/3, 0,
        GIM_CheckConstantInt8, /*MI*/0, /*Op*/4, 0,
        // MIs[0] offset
        GIM_CheckIsImm, /*MI*/0, /*Op*/6,
        // MIs[0] auxiliary
        GIM_CheckIsImm, /*MI*/0, /*Op*/7,
        // MIs[0] Operand 8
        GIM_CheckLiteralInt, /*MI*/0, /*Op*/8, GIMT_Encode8(0),
        GIM_CheckComplexPattern, /*MI*/0, /*Op*/5, /*Renderer*/GIMT_Encode2(0), GIMT_Encode2(GICP_gi_buf_soffset),
        // (SIbuffer_atomic_fadd:{ *:[f64] } f64:{ *:[f64] }:$vdata_in, v4i32:{ *:[v4i32] }:$rsrc, 0:{ *:[i32] }, 0:{ *:[i32] }, (BUFSOffset:{ *:[i32] } i32:{ *:[i32] }:$soffset), (timm:{ *:[i32] }):$offset, (timm:{ *:[i32] }):$auxiliary, 0:{ *:[i1] })<<P:Predicate_SIbuffer_atomic_fadd_noret>>  =>  (BUFFER_ATOMIC_ADD_F64_VBUFFER_OFFSET anonymous_15036:{ *:[f64] }:$vdata_in, SReg_128:{ *:[v4i32] }:$rsrc, SCSrc_b32:{ *:[i32] }:$soffset, (timm:{ *:[i32] }):$offset, (extract_cpol:{ *:[i32] } ?:{ *:[i32] }:$auxiliary))
        GIR_BuildMI, /*InsnID*/0, /*Opcode*/GIMT_Encode2(AMDGPU::BUFFER_ATOMIC_ADD_F64_VBUFFER_OFFSET),
        GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/1, // vdata_in
        GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/2, // rsrc
        GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/0, // soffset
        GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/6, // offset
        GIR_CustomOperandRenderer, /*InsnID*/0, /*OldInsnID*/0, /*OpIdx*/7, /*OperandRenderer*/GIMT_Encode2(GICR_renderExtractCPol), // auxiliary
        GIR_MergeMemOperands, /*InsnID*/0, /*NumInsns*/1, /*MergeInsnID's*/0,
        GIR_ConstrainSelectedInstOperands, /*InsnID*/0,
        GIR_EraseFromParent, /*InsnID*/0,
        // GIR_Coverage, 5253,
        GIR_Done,
      // Label 5895: @430402
      GIM_Try, /*On fail goto*//*Label 5896*/ GIMT_Encode4(430487), // Rule ID 5241 //
        GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasUnrestrictedSOffset_isGFX90APlus),
        GIM_CheckRegBankForClass, /*MI*/0, /*Op*/0, /*RC*/GIMT_Encode2(AMDGPU::AV_64RegClassID),
        GIM_CheckConstantInt8, /*MI*/0, /*Op*/3, 0,
        GIM_CheckConstantInt8, /*MI*/0, /*Op*/4, 0,
        // MIs[0] offset
        GIM_CheckIsImm, /*MI*/0, /*Op*/6,
        // MIs[0] auxiliary
        GIM_CheckIsImm, /*MI*/0, /*Op*/7,
        // MIs[0] Operand 8
        GIM_CheckLiteralInt, /*MI*/0, /*Op*/8, GIMT_Encode8(0),
        GIM_CheckComplexPattern, /*MI*/0, /*Op*/5, /*Renderer*/GIMT_Encode2(0), GIMT_Encode2(GICP_gi_buf_soffset),
        // (SIbuffer_atomic_fadd:{ *:[f64] } f64:{ *:[f64] }:$vdata_in, v4i32:{ *:[v4i32] }:$rsrc, 0:{ *:[i32] }, 0:{ *:[i32] }, (BUFSOffset:{ *:[i32] } i32:{ *:[i32] }:$soffset), (timm:{ *:[i32] }):$offset, (timm:{ *:[i32] }):$auxiliary, 0:{ *:[i1] })  =>  (BUFFER_ATOMIC_ADD_F64_OFFSET_RTN:{ *:[f64] } anonymous_15036:{ *:[f64] }:$vdata_in, SReg_128:{ *:[v4i32] }:$rsrc, SCSrc_b32:{ *:[i32] }:$soffset, (timm:{ *:[i32] }):$offset, (extract_cpol_set_glc:{ *:[i32] } ?:{ *:[i32] }:$auxiliary))
        GIR_BuildMI, /*InsnID*/0, /*Opcode*/GIMT_Encode2(AMDGPU::BUFFER_ATOMIC_ADD_F64_OFFSET_RTN),
        GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/0, // DstI[vdata]
        GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/1, // vdata_in
        GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/2, // rsrc
        GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/0, // soffset
        GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/6, // offset
        GIR_CustomOperandRenderer, /*InsnID*/0, /*OldInsnID*/0, /*OpIdx*/7, /*OperandRenderer*/GIMT_Encode2(GICR_renderExtractCpolSetGLC), // auxiliary
        GIR_MergeMemOperands, /*InsnID*/0, /*NumInsns*/1, /*MergeInsnID's*/0,
        GIR_ConstrainSelectedInstOperands, /*InsnID*/0,
        GIR_EraseFromParent, /*InsnID*/0,
        // GIR_Coverage, 5241,
        GIR_Done,
      // Label 5896: @430487
      GIM_Try, /*On fail goto*//*Label 5897*/ GIMT_Encode4(430572), // Rule ID 5249 //
        GIM_CheckFeatures, GIMT_Encode2(GIFBS_isGFX90APlus),
        GIM_CheckRegBankForClass, /*MI*/0, /*Op*/0, /*RC*/GIMT_Encode2(AMDGPU::AV_64RegClassID),
        GIM_CheckConstantInt8, /*MI*/0, /*Op*/3, 0,
        GIM_CheckConstantInt8, /*MI*/0, /*Op*/4, 0,
        // MIs[0] offset
        GIM_CheckIsImm, /*MI*/0, /*Op*/6,
        // MIs[0] auxiliary
        GIM_CheckIsImm, /*MI*/0, /*Op*/7,
        // MIs[0] Operand 8
        GIM_CheckLiteralInt, /*MI*/0, /*Op*/8, GIMT_Encode8(0),
        GIM_CheckComplexPattern, /*MI*/0, /*Op*/5, /*Renderer*/GIMT_Encode2(0), GIMT_Encode2(GICP_gi_buf_soffset),
        // (SIbuffer_atomic_fadd:{ *:[f64] } f64:{ *:[f64] }:$vdata_in, v4i32:{ *:[v4i32] }:$rsrc, 0:{ *:[i32] }, 0:{ *:[i32] }, (BUFSOffset:{ *:[i32] } i32:{ *:[i32] }:$soffset), (timm:{ *:[i32] }):$offset, (timm:{ *:[i32] }):$auxiliary, 0:{ *:[i1] })  =>  (BUFFER_ATOMIC_ADD_F64_VBUFFER_OFFSET_RTN:{ *:[f64] } anonymous_15036:{ *:[f64] }:$vdata_in, SReg_128:{ *:[v4i32] }:$rsrc, SCSrc_b32:{ *:[i32] }:$soffset, (timm:{ *:[i32] }):$offset, (extract_cpol_set_glc:{ *:[i32] } ?:{ *:[i32] }:$auxiliary))
        GIR_BuildMI, /*InsnID*/0, /*Opcode*/GIMT_Encode2(AMDGPU::BUFFER_ATOMIC_ADD_F64_VBUFFER_OFFSET_RTN),
        GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/0, // DstI[vdata]
        GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/1, // vdata_in
        GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/2, // rsrc
        GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/0, // soffset
        GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/6, // offset
        GIR_CustomOperandRenderer, /*InsnID*/0, /*OldInsnID*/0, /*OpIdx*/7, /*OperandRenderer*/GIMT_Encode2(GICR_renderExtractCpolSetGLC), // auxiliary
        GIR_MergeMemOperands, /*InsnID*/0, /*NumInsns*/1, /*MergeInsnID's*/0,
        GIR_ConstrainSelectedInstOperands, /*InsnID*/0,
        GIR_EraseFromParent, /*InsnID*/0,
        // GIR_Coverage, 5249,
        GIR_Done,
      // Label 5897: @430572
      GIM_Try, /*On fail goto*//*Label 5898*/ GIMT_Encode4(430650), // Rule ID 5247 //
        GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasUnrestrictedSOffset_isGFX90APlus),
        GIM_CheckHasNoUse, /*MI*/0,
        GIM_CheckConstantInt8, /*MI*/0, /*Op*/3, 0,
        // MIs[0] offset
        GIM_CheckIsImm, /*MI*/0, /*Op*/6,
        // MIs[0] auxiliary
        GIM_CheckIsImm, /*MI*/0, /*Op*/7,
        // MIs[0] Operand 8
        GIM_CheckLiteralInt, /*MI*/0, /*Op*/8, GIMT_Encode8(0),
        GIM_CheckComplexPattern, /*MI*/0, /*Op*/5, /*Renderer*/GIMT_Encode2(0), GIMT_Encode2(GICP_gi_buf_soffset),
        // (SIbuffer_atomic_fadd:{ *:[f64] } f64:{ *:[f64] }:$vdata_in, v4i32:{ *:[v4i32] }:$rsrc, 0:{ *:[i32] }, i32:{ *:[i32] }:$voffset, (BUFSOffset:{ *:[i32] } i32:{ *:[i32] }:$soffset), (timm:{ *:[i32] }):$offset, (timm:{ *:[i32] }):$auxiliary, 0:{ *:[i1] })<<P:Predicate_SIbuffer_atomic_fadd_noret>>  =>  (BUFFER_ATOMIC_ADD_F64_OFFEN anonymous_15036:{ *:[f64] }:$vdata_in, VGPR_32:{ *:[i32] }:$voffset, SReg_128:{ *:[v4i32] }:$rsrc, SCSrc_b32:{ *:[i32] }:$soffset, (timm:{ *:[i32] }):$offset, (extract_cpol:{ *:[i32] } ?:{ *:[i32] }:$auxiliary))
        GIR_BuildMI, /*InsnID*/0, /*Opcode*/GIMT_Encode2(AMDGPU::BUFFER_ATOMIC_ADD_F64_OFFEN),
        GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/1, // vdata_in
        GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/4, // voffset
        GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/2, // rsrc
        GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/0, // soffset
        GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/6, // offset
        GIR_CustomOperandRenderer, /*InsnID*/0, /*OldInsnID*/0, /*OpIdx*/7, /*OperandRenderer*/GIMT_Encode2(GICR_renderExtractCPol), // auxiliary
        GIR_MergeMemOperands, /*InsnID*/0, /*NumInsns*/1, /*MergeInsnID's*/0,
        GIR_ConstrainSelectedInstOperands, /*InsnID*/0,
        GIR_EraseFromParent, /*InsnID*/0,
        // GIR_Coverage, 5247,
        GIR_Done,
      // Label 5898: @430650
      GIM_Try, /*On fail goto*//*Label 5899*/ GIMT_Encode4(430728), // Rule ID 5255 //
        GIM_CheckFeatures, GIMT_Encode2(GIFBS_isGFX90APlus),
        GIM_CheckHasNoUse, /*MI*/0,
        GIM_CheckConstantInt8, /*MI*/0, /*Op*/3, 0,
        // MIs[0] offset
        GIM_CheckIsImm, /*MI*/0, /*Op*/6,
        // MIs[0] auxiliary
        GIM_CheckIsImm, /*MI*/0, /*Op*/7,
        // MIs[0] Operand 8
        GIM_CheckLiteralInt, /*MI*/0, /*Op*/8, GIMT_Encode8(0),
        GIM_CheckComplexPattern, /*MI*/0, /*Op*/5, /*Renderer*/GIMT_Encode2(0), GIMT_Encode2(GICP_gi_buf_soffset),
        // (SIbuffer_atomic_fadd:{ *:[f64] } f64:{ *:[f64] }:$vdata_in, v4i32:{ *:[v4i32] }:$rsrc, 0:{ *:[i32] }, i32:{ *:[i32] }:$voffset, (BUFSOffset:{ *:[i32] } i32:{ *:[i32] }:$soffset), (timm:{ *:[i32] }):$offset, (timm:{ *:[i32] }):$auxiliary, 0:{ *:[i1] })<<P:Predicate_SIbuffer_atomic_fadd_noret>>  =>  (BUFFER_ATOMIC_ADD_F64_VBUFFER_OFFEN anonymous_15036:{ *:[f64] }:$vdata_in, VGPR_32:{ *:[i32] }:$voffset, SReg_128:{ *:[v4i32] }:$rsrc, SCSrc_b32:{ *:[i32] }:$soffset, (timm:{ *:[i32] }):$offset, (extract_cpol:{ *:[i32] } ?:{ *:[i32] }:$auxiliary))
        GIR_BuildMI, /*InsnID*/0, /*Opcode*/GIMT_Encode2(AMDGPU::BUFFER_ATOMIC_ADD_F64_VBUFFER_OFFEN),
        GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/1, // vdata_in
        GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/4, // voffset
        GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/2, // rsrc
        GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/0, // soffset
        GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/6, // offset
        GIR_CustomOperandRenderer, /*InsnID*/0, /*OldInsnID*/0, /*OpIdx*/7, /*OperandRenderer*/GIMT_Encode2(GICR_renderExtractCPol), // auxiliary
        GIR_MergeMemOperands, /*InsnID*/0, /*NumInsns*/1, /*MergeInsnID's*/0,
        GIR_ConstrainSelectedInstOperands, /*InsnID*/0,
        GIR_EraseFromParent, /*InsnID*/0,
        // GIR_Coverage, 5255,
        GIR_Done,
      // Label 5899: @430728
      GIM_Try, /*On fail goto*//*Label 5900*/ GIMT_Encode4(430813), // Rule ID 5243 //
        GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasUnrestrictedSOffset_isGFX90APlus),
        GIM_CheckRegBankForClass, /*MI*/0, /*Op*/0, /*RC*/GIMT_Encode2(AMDGPU::AV_64RegClassID),
        GIM_CheckConstantInt8, /*MI*/0, /*Op*/3, 0,
        // MIs[0] offset
        GIM_CheckIsImm, /*MI*/0, /*Op*/6,
        // MIs[0] auxiliary
        GIM_CheckIsImm, /*MI*/0, /*Op*/7,
        // MIs[0] Operand 8
        GIM_CheckLiteralInt, /*MI*/0, /*Op*/8, GIMT_Encode8(0),
        GIM_CheckComplexPattern, /*MI*/0, /*Op*/5, /*Renderer*/GIMT_Encode2(0), GIMT_Encode2(GICP_gi_buf_soffset),
        // (SIbuffer_atomic_fadd:{ *:[f64] } f64:{ *:[f64] }:$vdata_in, v4i32:{ *:[v4i32] }:$rsrc, 0:{ *:[i32] }, i32:{ *:[i32] }:$voffset, (BUFSOffset:{ *:[i32] } i32:{ *:[i32] }:$soffset), (timm:{ *:[i32] }):$offset, (timm:{ *:[i32] }):$auxiliary, 0:{ *:[i1] })  =>  (BUFFER_ATOMIC_ADD_F64_OFFEN_RTN:{ *:[f64] } anonymous_15036:{ *:[f64] }:$vdata_in, VGPR_32:{ *:[i32] }:$voffset, SReg_128:{ *:[v4i32] }:$rsrc, SCSrc_b32:{ *:[i32] }:$soffset, (timm:{ *:[i32] }):$offset, (extract_cpol_set_glc:{ *:[i32] } ?:{ *:[i32] }:$auxiliary))
        GIR_BuildMI, /*InsnID*/0, /*Opcode*/GIMT_Encode2(AMDGPU::BUFFER_ATOMIC_ADD_F64_OFFEN_RTN),
        GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/0, // DstI[vdata]
        GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/1, // vdata_in
        GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/4, // voffset
        GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/2, // rsrc
        GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/0, // soffset
        GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/6, // offset
        GIR_CustomOperandRenderer, /*InsnID*/0, /*OldInsnID*/0, /*OpIdx*/7, /*OperandRenderer*/GIMT_Encode2(GICR_renderExtractCpolSetGLC), // auxiliary
        GIR_MergeMemOperands, /*InsnID*/0, /*NumInsns*/1, /*MergeInsnID's*/0,
        GIR_ConstrainSelectedInstOperands, /*InsnID*/0,
        GIR_EraseFromParent, /*InsnID*/0,
        // GIR_Coverage, 5243,
        GIR_Done,
      // Label 5900: @430813
      GIM_Try, /*On fail goto*//*Label 5901*/ GIMT_Encode4(430898), // Rule ID 5251 //
        GIM_CheckFeatures, GIMT_Encode2(GIFBS_isGFX90APlus),
        GIM_CheckRegBankForClass, /*MI*/0, /*Op*/0, /*RC*/GIMT_Encode2(AMDGPU::AV_64RegClassID),
        GIM_CheckConstantInt8, /*MI*/0, /*Op*/3, 0,
        // MIs[0] offset
        GIM_CheckIsImm, /*MI*/0, /*Op*/6,
        // MIs[0] auxiliary
        GIM_CheckIsImm, /*MI*/0, /*Op*/7,
        // MIs[0] Operand 8
        GIM_CheckLiteralInt, /*MI*/0, /*Op*/8, GIMT_Encode8(0),
        GIM_CheckComplexPattern, /*MI*/0, /*Op*/5, /*Renderer*/GIMT_Encode2(0), GIMT_Encode2(GICP_gi_buf_soffset),
        // (SIbuffer_atomic_fadd:{ *:[f64] } f64:{ *:[f64] }:$vdata_in, v4i32:{ *:[v4i32] }:$rsrc, 0:{ *:[i32] }, i32:{ *:[i32] }:$voffset, (BUFSOffset:{ *:[i32] } i32:{ *:[i32] }:$soffset), (timm:{ *:[i32] }):$offset, (timm:{ *:[i32] }):$auxiliary, 0:{ *:[i1] })  =>  (BUFFER_ATOMIC_ADD_F64_VBUFFER_OFFEN_RTN:{ *:[f64] } anonymous_15036:{ *:[f64] }:$vdata_in, VGPR_32:{ *:[i32] }:$voffset, SReg_128:{ *:[v4i32] }:$rsrc, SCSrc_b32:{ *:[i32] }:$soffset, (timm:{ *:[i32] }):$offset, (extract_cpol_set_glc:{ *:[i32] } ?:{ *:[i32] }:$auxiliary))
        GIR_BuildMI, /*InsnID*/0, /*Opcode*/GIMT_Encode2(AMDGPU::BUFFER_ATOMIC_ADD_F64_VBUFFER_OFFEN_RTN),
        GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/0, // DstI[vdata]
        GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/1, // vdata_in
        GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/4, // voffset
        GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/2, // rsrc
        GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/0, // soffset
        GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/6, // offset
        GIR_CustomOperandRenderer, /*InsnID*/0, /*OldInsnID*/0, /*OpIdx*/7, /*OperandRenderer*/GIMT_Encode2(GICR_renderExtractCpolSetGLC), // auxiliary
        GIR_MergeMemOperands, /*InsnID*/0, /*NumInsns*/1, /*MergeInsnID's*/0,
        GIR_ConstrainSelectedInstOperands, /*InsnID*/0,
        GIR_EraseFromParent, /*InsnID*/0,
        // GIR_Coverage, 5251,
        GIR_Done,
      // Label 5901: @430898
      GIM_Try, /*On fail goto*//*Label 5902*/ GIMT_Encode4(430968), // Rule ID 5246 //
        GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasUnrestrictedSOffset_isGFX90APlus),
        GIM_CheckHasNoUse, /*MI*/0,
        GIM_CheckConstantInt8, /*MI*/0, /*Op*/4, 0,
        // MIs[0] offset
        GIM_CheckIsImm, /*MI*/0, /*Op*/6,
        // MIs[0] auxiliary
        GIM_CheckIsImm, /*MI*/0, /*Op*/7,
        // MIs[0] Operand 8
        GIM_CheckIsImm, /*MI*/0, /*Op*/8,
        GIM_CheckComplexPattern, /*MI*/0, /*Op*/5, /*Renderer*/GIMT_Encode2(0), GIMT_Encode2(GICP_gi_buf_soffset),
        // (SIbuffer_atomic_fadd:{ *:[f64] } f64:{ *:[f64] }:$vdata_in, v4i32:{ *:[v4i32] }:$rsrc, i32:{ *:[i32] }:$vindex, 0:{ *:[i32] }, (BUFSOffset:{ *:[i32] } i32:{ *:[i32] }:$soffset), (timm:{ *:[i32] }):$offset, (timm:{ *:[i32] }):$auxiliary, (timm:{ *:[i1] }))<<P:Predicate_SIbuffer_atomic_fadd_noret>>  =>  (BUFFER_ATOMIC_ADD_F64_IDXEN anonymous_15036:{ *:[f64] }:$vdata_in, VGPR_32:{ *:[i32] }:$vindex, SReg_128:{ *:[v4i32] }:$rsrc, SCSrc_b32:{ *:[i32] }:$soffset, (timm:{ *:[i32] }):$offset, (extract_cpol:{ *:[i32] } ?:{ *:[i32] }:$auxiliary))
        GIR_BuildMI, /*InsnID*/0, /*Opcode*/GIMT_Encode2(AMDGPU::BUFFER_ATOMIC_ADD_F64_IDXEN),
        GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/1, // vdata_in
        GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/3, // vindex
        GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/2, // rsrc
        GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/0, // soffset
        GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/6, // offset
        GIR_CustomOperandRenderer, /*InsnID*/0, /*OldInsnID*/0, /*OpIdx*/7, /*OperandRenderer*/GIMT_Encode2(GICR_renderExtractCPol), // auxiliary
        GIR_MergeMemOperands, /*InsnID*/0, /*NumInsns*/1, /*MergeInsnID's*/0,
        GIR_ConstrainSelectedInstOperands, /*InsnID*/0,
        GIR_EraseFromParent, /*InsnID*/0,
        // GIR_Coverage, 5246,
        GIR_Done,
      // Label 5902: @430968
      GIM_Try, /*On fail goto*//*Label 5903*/ GIMT_Encode4(431038), // Rule ID 5254 //
        GIM_CheckFeatures, GIMT_Encode2(GIFBS_isGFX90APlus),
        GIM_CheckHasNoUse, /*MI*/0,
        GIM_CheckConstantInt8, /*MI*/0, /*Op*/4, 0,
        // MIs[0] offset
        GIM_CheckIsImm, /*MI*/0, /*Op*/6,
        // MIs[0] auxiliary
        GIM_CheckIsImm, /*MI*/0, /*Op*/7,
        // MIs[0] Operand 8
        GIM_CheckIsImm, /*MI*/0, /*Op*/8,
        GIM_CheckComplexPattern, /*MI*/0, /*Op*/5, /*Renderer*/GIMT_Encode2(0), GIMT_Encode2(GICP_gi_buf_soffset),
        // (SIbuffer_atomic_fadd:{ *:[f64] } f64:{ *:[f64] }:$vdata_in, v4i32:{ *:[v4i32] }:$rsrc, i32:{ *:[i32] }:$vindex, 0:{ *:[i32] }, (BUFSOffset:{ *:[i32] } i32:{ *:[i32] }:$soffset), (timm:{ *:[i32] }):$offset, (timm:{ *:[i32] }):$auxiliary, (timm:{ *:[i1] }))<<P:Predicate_SIbuffer_atomic_fadd_noret>>  =>  (BUFFER_ATOMIC_ADD_F64_VBUFFER_IDXEN anonymous_15036:{ *:[f64] }:$vdata_in, VGPR_32:{ *:[i32] }:$vindex, SReg_128:{ *:[v4i32] }:$rsrc, SCSrc_b32:{ *:[i32] }:$soffset, (timm:{ *:[i32] }):$offset, (extract_cpol:{ *:[i32] } ?:{ *:[i32] }:$auxiliary))
        GIR_BuildMI, /*InsnID*/0, /*Opcode*/GIMT_Encode2(AMDGPU::BUFFER_ATOMIC_ADD_F64_VBUFFER_IDXEN),
        GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/1, // vdata_in
        GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/3, // vindex
        GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/2, // rsrc
        GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/0, // soffset
        GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/6, // offset
        GIR_CustomOperandRenderer, /*InsnID*/0, /*OldInsnID*/0, /*OpIdx*/7, /*OperandRenderer*/GIMT_Encode2(GICR_renderExtractCPol), // auxiliary
        GIR_MergeMemOperands, /*InsnID*/0, /*NumInsns*/1, /*MergeInsnID's*/0,
        GIR_ConstrainSelectedInstOperands, /*InsnID*/0,
        GIR_EraseFromParent, /*InsnID*/0,
        // GIR_Coverage, 5254,
        GIR_Done,
      // Label 5903: @431038
      GIM_Try, /*On fail goto*//*Label 5904*/ GIMT_Encode4(431115), // Rule ID 5242 //
        GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasUnrestrictedSOffset_isGFX90APlus),
        GIM_CheckRegBankForClass, /*MI*/0, /*Op*/0, /*RC*/GIMT_Encode2(AMDGPU::AV_64RegClassID),
        GIM_CheckConstantInt8, /*MI*/0, /*Op*/4, 0,
        // MIs[0] offset
        GIM_CheckIsImm, /*MI*/0, /*Op*/6,
        // MIs[0] auxiliary
        GIM_CheckIsImm, /*MI*/0, /*Op*/7,
        // MIs[0] Operand 8
        GIM_CheckIsImm, /*MI*/0, /*Op*/8,
        GIM_CheckComplexPattern, /*MI*/0, /*Op*/5, /*Renderer*/GIMT_Encode2(0), GIMT_Encode2(GICP_gi_buf_soffset),
        // (SIbuffer_atomic_fadd:{ *:[f64] } f64:{ *:[f64] }:$vdata_in, v4i32:{ *:[v4i32] }:$rsrc, i32:{ *:[i32] }:$vindex, 0:{ *:[i32] }, (BUFSOffset:{ *:[i32] } i32:{ *:[i32] }:$soffset), (timm:{ *:[i32] }):$offset, (timm:{ *:[i32] }):$auxiliary, (timm:{ *:[i1] }))  =>  (BUFFER_ATOMIC_ADD_F64_IDXEN_RTN:{ *:[f64] } anonymous_15036:{ *:[f64] }:$vdata_in, VGPR_32:{ *:[i32] }:$vindex, SReg_128:{ *:[v4i32] }:$rsrc, SCSrc_b32:{ *:[i32] }:$soffset, (timm:{ *:[i32] }):$offset, (extract_cpol_set_glc:{ *:[i32] } ?:{ *:[i32] }:$auxiliary))
        GIR_BuildMI, /*InsnID*/0, /*Opcode*/GIMT_Encode2(AMDGPU::BUFFER_ATOMIC_ADD_F64_IDXEN_RTN),
        GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/0, // DstI[vdata]
        GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/1, // vdata_in
        GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/3, // vindex
        GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/2, // rsrc
        GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/0, // soffset
        GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/6, // offset
        GIR_CustomOperandRenderer, /*InsnID*/0, /*OldInsnID*/0, /*OpIdx*/7, /*OperandRenderer*/GIMT_Encode2(GICR_renderExtractCpolSetGLC), // auxiliary
        GIR_MergeMemOperands, /*InsnID*/0, /*NumInsns*/1, /*MergeInsnID's*/0,
        GIR_ConstrainSelectedInstOperands, /*InsnID*/0,
        GIR_EraseFromParent, /*InsnID*/0,
        // GIR_Coverage, 5242,
        GIR_Done,
      // Label 5904: @431115
      GIM_Try, /*On fail goto*//*Label 5905*/ GIMT_Encode4(431192), // Rule ID 5250 //
        GIM_CheckFeatures, GIMT_Encode2(GIFBS_isGFX90APlus),
        GIM_CheckRegBankForClass, /*MI*/0, /*Op*/0, /*RC*/GIMT_Encode2(AMDGPU::AV_64RegClassID),
        GIM_CheckConstantInt8, /*MI*/0, /*Op*/4, 0,
        // MIs[0] offset
        GIM_CheckIsImm, /*MI*/0, /*Op*/6,
        // MIs[0] auxiliary
        GIM_CheckIsImm, /*MI*/0, /*Op*/7,
        // MIs[0] Operand 8
        GIM_CheckIsImm, /*MI*/0, /*Op*/8,
        GIM_CheckComplexPattern, /*MI*/0, /*Op*/5, /*Renderer*/GIMT_Encode2(0), GIMT_Encode2(GICP_gi_buf_soffset),
        // (SIbuffer_atomic_fadd:{ *:[f64] } f64:{ *:[f64] }:$vdata_in, v4i32:{ *:[v4i32] }:$rsrc, i32:{ *:[i32] }:$vindex, 0:{ *:[i32] }, (BUFSOffset:{ *:[i32] } i32:{ *:[i32] }:$soffset), (timm:{ *:[i32] }):$offset, (timm:{ *:[i32] }):$auxiliary, (timm:{ *:[i1] }))  =>  (BUFFER_ATOMIC_ADD_F64_VBUFFER_IDXEN_RTN:{ *:[f64] } anonymous_15036:{ *:[f64] }:$vdata_in, VGPR_32:{ *:[i32] }:$vindex, SReg_128:{ *:[v4i32] }:$rsrc, SCSrc_b32:{ *:[i32] }:$soffset, (timm:{ *:[i32] }):$offset, (extract_cpol_set_glc:{ *:[i32] } ?:{ *:[i32] }:$auxiliary))
        GIR_BuildMI, /*InsnID*/0, /*Opcode*/GIMT_Encode2(AMDGPU::BUFFER_ATOMIC_ADD_F64_VBUFFER_IDXEN_RTN),
        GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/0, // DstI[vdata]
        GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/1, // vdata_in
        GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/3, // vindex
        GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/2, // rsrc
        GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/0, // soffset
        GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/6, // offset
        GIR_CustomOperandRenderer, /*InsnID*/0, /*OldInsnID*/0, /*OpIdx*/7, /*OperandRenderer*/GIMT_Encode2(GICR_renderExtractCpolSetGLC), // auxiliary
        GIR_MergeMemOperands, /*InsnID*/0, /*NumInsns*/1, /*MergeInsnID's*/0,
        GIR_ConstrainSelectedInstOperands, /*InsnID*/0,
        GIR_EraseFromParent, /*InsnID*/0,
        // GIR_Coverage, 5250,
        GIR_Done,
      // Label 5905: @431192
      GIM_Try, /*On fail goto*//*Label 5906*/ GIMT_Encode4(431298), // Rule ID 5248 //
        GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasUnrestrictedSOffset_isGFX90APlus),
        GIM_CheckHasNoUse, /*MI*/0,
        // MIs[0] offset
        GIM_CheckIsImm, /*MI*/0, /*Op*/6,
        // MIs[0] auxiliary
        GIM_CheckIsImm, /*MI*/0, /*Op*/7,
        // MIs[0] Operand 8
        GIM_CheckIsImm, /*MI*/0, /*Op*/8,
        GIM_CheckComplexPattern, /*MI*/0, /*Op*/5, /*Renderer*/GIMT_Encode2(0), GIMT_Encode2(GICP_gi_buf_soffset),
        // (SIbuffer_atomic_fadd:{ *:[f64] } f64:{ *:[f64] }:$vdata_in, v4i32:{ *:[v4i32] }:$rsrc, i32:{ *:[i32] }:$vindex, i32:{ *:[i32] }:$voffset, (BUFSOffset:{ *:[i32] } i32:{ *:[i32] }:$soffset), (timm:{ *:[i32] }):$offset, (timm:{ *:[i32] }):$auxiliary, (timm:{ *:[i1] }))<<P:Predicate_SIbuffer_atomic_fadd_noret>>  =>  (BUFFER_ATOMIC_ADD_F64_BOTHEN anonymous_15036:{ *:[f64] }:$vdata_in, (REG_SEQUENCE:{ *:[i64] } VReg_64:{ *:[i32] }, VGPR_32:{ *:[i32] }:$vindex, sub0:{ *:[i32] }, VGPR_32:{ *:[i32] }:$voffset, sub1:{ *:[i32] }), SReg_128:{ *:[v4i32] }:$rsrc, SCSrc_b32:{ *:[i32] }:$soffset, (timm:{ *:[i32] }):$offset, (extract_cpol:{ *:[i32] } ?:{ *:[i32] }:$auxiliary))
        GIR_MakeTempReg, /*TempRegID*/0, /*TypeID*/GILLT_s64,
        GIR_BuildMI, /*InsnID*/1, /*Opcode*/GIMT_Encode2(TargetOpcode::REG_SEQUENCE),
        GIR_AddTempRegister, /*InsnID*/1, /*TempRegID*/0, /*TempRegFlags*/GIMT_Encode2(RegState::Define),
        GIR_Copy, /*NewInsnID*/1, /*OldInsnID*/0, /*OpIdx*/3, // vindex
        GIR_AddImm8, /*InsnID*/1, /*SubRegIndex*/3,
        GIR_Copy, /*NewInsnID*/1, /*OldInsnID*/0, /*OpIdx*/4, // voffset
        GIR_AddImm8, /*InsnID*/1, /*SubRegIndex*/11,
        GIR_ConstrainOperandRC, /*InsnID*/1, /*Op*/0, GIMT_Encode2(AMDGPU::VReg_64RegClassID),
        GIR_ConstrainOperandRC, /*InsnID*/1, /*Op*/1, GIMT_Encode2(AMDGPU::VGPR_32RegClassID),
        GIR_ConstrainOperandRC, /*InsnID*/1, /*Op*/3, GIMT_Encode2(AMDGPU::VGPR_32RegClassID),
        GIR_BuildMI, /*InsnID*/0, /*Opcode*/GIMT_Encode2(AMDGPU::BUFFER_ATOMIC_ADD_F64_BOTHEN),
        GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/1, // vdata_in
        GIR_AddSimpleTempRegister, /*InsnID*/0, /*TempRegID*/0,
        GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/2, // rsrc
        GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/0, // soffset
        GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/6, // offset
        GIR_CustomOperandRenderer, /*InsnID*/0, /*OldInsnID*/0, /*OpIdx*/7, /*OperandRenderer*/GIMT_Encode2(GICR_renderExtractCPol), // auxiliary
        GIR_MergeMemOperands, /*InsnID*/0, /*NumInsns*/1, /*MergeInsnID's*/0,
        GIR_ConstrainSelectedInstOperands, /*InsnID*/0,
        GIR_EraseFromParent, /*InsnID*/0,
        // GIR_Coverage, 5248,
        GIR_Done,
      // Label 5906: @431298
      GIM_Try, /*On fail goto*//*Label 5907*/ GIMT_Encode4(431404), // Rule ID 5256 //
        GIM_CheckFeatures, GIMT_Encode2(GIFBS_isGFX90APlus),
        GIM_CheckHasNoUse, /*MI*/0,
        // MIs[0] offset
        GIM_CheckIsImm, /*MI*/0, /*Op*/6,
        // MIs[0] auxiliary
        GIM_CheckIsImm, /*MI*/0, /*Op*/7,
        // MIs[0] Operand 8
        GIM_CheckIsImm, /*MI*/0, /*Op*/8,
        GIM_CheckComplexPattern, /*MI*/0, /*Op*/5, /*Renderer*/GIMT_Encode2(0), GIMT_Encode2(GICP_gi_buf_soffset),
        // (SIbuffer_atomic_fadd:{ *:[f64] } f64:{ *:[f64] }:$vdata_in, v4i32:{ *:[v4i32] }:$rsrc, i32:{ *:[i32] }:$vindex, i32:{ *:[i32] }:$voffset, (BUFSOffset:{ *:[i32] } i32:{ *:[i32] }:$soffset), (timm:{ *:[i32] }):$offset, (timm:{ *:[i32] }):$auxiliary, (timm:{ *:[i1] }))<<P:Predicate_SIbuffer_atomic_fadd_noret>>  =>  (BUFFER_ATOMIC_ADD_F64_VBUFFER_BOTHEN anonymous_15036:{ *:[f64] }:$vdata_in, (REG_SEQUENCE:{ *:[i64] } VReg_64:{ *:[i32] }, VGPR_32:{ *:[i32] }:$vindex, sub0:{ *:[i32] }, VGPR_32:{ *:[i32] }:$voffset, sub1:{ *:[i32] }), SReg_128:{ *:[v4i32] }:$rsrc, SCSrc_b32:{ *:[i32] }:$soffset, (timm:{ *:[i32] }):$offset, (extract_cpol:{ *:[i32] } ?:{ *:[i32] }:$auxiliary))
        GIR_MakeTempReg, /*TempRegID*/0, /*TypeID*/GILLT_s64,
        GIR_BuildMI, /*InsnID*/1, /*Opcode*/GIMT_Encode2(TargetOpcode::REG_SEQUENCE),
        GIR_AddTempRegister, /*InsnID*/1, /*TempRegID*/0, /*TempRegFlags*/GIMT_Encode2(RegState::Define),
        GIR_Copy, /*NewInsnID*/1, /*OldInsnID*/0, /*OpIdx*/3, // vindex
        GIR_AddImm8, /*InsnID*/1, /*SubRegIndex*/3,
        GIR_Copy, /*NewInsnID*/1, /*OldInsnID*/0, /*OpIdx*/4, // voffset
        GIR_AddImm8, /*InsnID*/1, /*SubRegIndex*/11,
        GIR_ConstrainOperandRC, /*InsnID*/1, /*Op*/0, GIMT_Encode2(AMDGPU::VReg_64RegClassID),
        GIR_ConstrainOperandRC, /*InsnID*/1, /*Op*/1, GIMT_Encode2(AMDGPU::VGPR_32RegClassID),
        GIR_ConstrainOperandRC, /*InsnID*/1, /*Op*/3, GIMT_Encode2(AMDGPU::VGPR_32RegClassID),
        GIR_BuildMI, /*InsnID*/0, /*Opcode*/GIMT_Encode2(AMDGPU::BUFFER_ATOMIC_ADD_F64_VBUFFER_BOTHEN),
        GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/1, // vdata_in
        GIR_AddSimpleTempRegister, /*InsnID*/0, /*TempRegID*/0,
        GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/2, // rsrc
        GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/0, // soffset
        GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/6, // offset
        GIR_CustomOperandRenderer, /*InsnID*/0, /*OldInsnID*/0, /*OpIdx*/7, /*OperandRenderer*/GIMT_Encode2(GICR_renderExtractCPol), // auxiliary
        GIR_MergeMemOperands, /*InsnID*/0, /*NumInsns*/1, /*MergeInsnID's*/0,
        GIR_ConstrainSelectedInstOperands, /*InsnID*/0,
        GIR_EraseFromParent, /*InsnID*/0,
        // GIR_Coverage, 5256,
        GIR_Done,
      // Label 5907: @431404
      GIM_Try, /*On fail goto*//*Label 5908*/ GIMT_Encode4(431517), // Rule ID 5244 //
        GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasUnrestrictedSOffset_isGFX90APlus),
        GIM_CheckRegBankForClass, /*MI*/0, /*Op*/0, /*RC*/GIMT_Encode2(AMDGPU::AV_64RegClassID),
        // MIs[0] offset
        GIM_CheckIsImm, /*MI*/0, /*Op*/6,
        // MIs[0] auxiliary
        GIM_CheckIsImm, /*MI*/0, /*Op*/7,
        // MIs[0] Operand 8
        GIM_CheckIsImm, /*MI*/0, /*Op*/8,
        GIM_CheckComplexPattern, /*MI*/0, /*Op*/5, /*Renderer*/GIMT_Encode2(0), GIMT_Encode2(GICP_gi_buf_soffset),
        // (SIbuffer_atomic_fadd:{ *:[f64] } f64:{ *:[f64] }:$vdata_in, v4i32:{ *:[v4i32] }:$rsrc, i32:{ *:[i32] }:$vindex, i32:{ *:[i32] }:$voffset, (BUFSOffset:{ *:[i32] } i32:{ *:[i32] }:$soffset), (timm:{ *:[i32] }):$offset, (timm:{ *:[i32] }):$auxiliary, (timm:{ *:[i1] }))  =>  (BUFFER_ATOMIC_ADD_F64_BOTHEN_RTN:{ *:[f64] } anonymous_15036:{ *:[f64] }:$vdata_in, (REG_SEQUENCE:{ *:[i64] } VReg_64:{ *:[i32] }, VGPR_32:{ *:[i32] }:$vindex, sub0:{ *:[i32] }, VGPR_32:{ *:[i32] }:$voffset, sub1:{ *:[i32] }), SReg_128:{ *:[v4i32] }:$rsrc, SCSrc_b32:{ *:[i32] }:$soffset, (timm:{ *:[i32] }):$offset, (extract_cpol_set_glc:{ *:[i32] } ?:{ *:[i32] }:$auxiliary))
        GIR_MakeTempReg, /*TempRegID*/0, /*TypeID*/GILLT_s64,
        GIR_BuildMI, /*InsnID*/1, /*Opcode*/GIMT_Encode2(TargetOpcode::REG_SEQUENCE),
        GIR_AddTempRegister, /*InsnID*/1, /*TempRegID*/0, /*TempRegFlags*/GIMT_Encode2(RegState::Define),
        GIR_Copy, /*NewInsnID*/1, /*OldInsnID*/0, /*OpIdx*/3, // vindex
        GIR_AddImm8, /*InsnID*/1, /*SubRegIndex*/3,
        GIR_Copy, /*NewInsnID*/1, /*OldInsnID*/0, /*OpIdx*/4, // voffset
        GIR_AddImm8, /*InsnID*/1, /*SubRegIndex*/11,
        GIR_ConstrainOperandRC, /*InsnID*/1, /*Op*/0, GIMT_Encode2(AMDGPU::VReg_64RegClassID),
        GIR_ConstrainOperandRC, /*InsnID*/1, /*Op*/1, GIMT_Encode2(AMDGPU::VGPR_32RegClassID),
        GIR_ConstrainOperandRC, /*InsnID*/1, /*Op*/3, GIMT_Encode2(AMDGPU::VGPR_32RegClassID),
        GIR_BuildMI, /*InsnID*/0, /*Opcode*/GIMT_Encode2(AMDGPU::BUFFER_ATOMIC_ADD_F64_BOTHEN_RTN),
        GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/0, // DstI[vdata]
        GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/1, // vdata_in
        GIR_AddSimpleTempRegister, /*InsnID*/0, /*TempRegID*/0,
        GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/2, // rsrc
        GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/0, // soffset
        GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/6, // offset
        GIR_CustomOperandRenderer, /*InsnID*/0, /*OldInsnID*/0, /*OpIdx*/7, /*OperandRenderer*/GIMT_Encode2(GICR_renderExtractCpolSetGLC), // auxiliary
        GIR_MergeMemOperands, /*InsnID*/0, /*NumInsns*/1, /*MergeInsnID's*/0,
        GIR_ConstrainSelectedInstOperands, /*InsnID*/0,
        GIR_EraseFromParent, /*InsnID*/0,
        // GIR_Coverage, 5244,
        GIR_Done,
      // Label 5908: @431517
      GIM_Try, /*On fail goto*//*Label 5909*/ GIMT_Encode4(431630), // Rule ID 5252 //
        GIM_CheckFeatures, GIMT_Encode2(GIFBS_isGFX90APlus),
        GIM_CheckRegBankForClass, /*MI*/0, /*Op*/0, /*RC*/GIMT_Encode2(AMDGPU::AV_64RegClassID),
        // MIs[0] offset
        GIM_CheckIsImm, /*MI*/0, /*Op*/6,
        // MIs[0] auxiliary
        GIM_CheckIsImm, /*MI*/0, /*Op*/7,
        // MIs[0] Operand 8
        GIM_CheckIsImm, /*MI*/0, /*Op*/8,
        GIM_CheckComplexPattern, /*MI*/0, /*Op*/5, /*Renderer*/GIMT_Encode2(0), GIMT_Encode2(GICP_gi_buf_soffset),
        // (SIbuffer_atomic_fadd:{ *:[f64] } f64:{ *:[f64] }:$vdata_in, v4i32:{ *:[v4i32] }:$rsrc, i32:{ *:[i32] }:$vindex, i32:{ *:[i32] }:$voffset, (BUFSOffset:{ *:[i32] } i32:{ *:[i32] }:$soffset), (timm:{ *:[i32] }):$offset, (timm:{ *:[i32] }):$auxiliary, (timm:{ *:[i1] }))  =>  (BUFFER_ATOMIC_ADD_F64_VBUFFER_BOTHEN_RTN:{ *:[f64] } anonymous_15036:{ *:[f64] }:$vdata_in, (REG_SEQUENCE:{ *:[i64] } VReg_64:{ *:[i32] }, VGPR_32:{ *:[i32] }:$vindex, sub0:{ *:[i32] }, VGPR_32:{ *:[i32] }:$voffset, sub1:{ *:[i32] }), SReg_128:{ *:[v4i32] }:$rsrc, SCSrc_b32:{ *:[i32] }:$soffset, (timm:{ *:[i32] }):$offset, (extract_cpol_set_glc:{ *:[i32] } ?:{ *:[i32] }:$auxiliary))
        GIR_MakeTempReg, /*TempRegID*/0, /*TypeID*/GILLT_s64,
        GIR_BuildMI, /*InsnID*/1, /*Opcode*/GIMT_Encode2(TargetOpcode::REG_SEQUENCE),
        GIR_AddTempRegister, /*InsnID*/1, /*TempRegID*/0, /*TempRegFlags*/GIMT_Encode2(RegState::Define),
        GIR_Copy, /*NewInsnID*/1, /*OldInsnID*/0, /*OpIdx*/3, // vindex
        GIR_AddImm8, /*InsnID*/1, /*SubRegIndex*/3,
        GIR_Copy, /*NewInsnID*/1, /*OldInsnID*/0, /*OpIdx*/4, // voffset
        GIR_AddImm8, /*InsnID*/1, /*SubRegIndex*/11,
        GIR_ConstrainOperandRC, /*InsnID*/1, /*Op*/0, GIMT_Encode2(AMDGPU::VReg_64RegClassID),
        GIR_ConstrainOperandRC, /*InsnID*/1, /*Op*/1, GIMT_Encode2(AMDGPU::VGPR_32RegClassID),
        GIR_ConstrainOperandRC, /*InsnID*/1, /*Op*/3, GIMT_Encode2(AMDGPU::VGPR_32RegClassID),
        GIR_BuildMI, /*InsnID*/0, /*Opcode*/GIMT_Encode2(AMDGPU::BUFFER_ATOMIC_ADD_F64_VBUFFER_BOTHEN_RTN),
        GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/0, // DstI[vdata]
        GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/1, // vdata_in
        GIR_AddSimpleTempRegister, /*InsnID*/0, /*TempRegID*/0,
        GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/2, // rsrc
        GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/0, // soffset
        GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/6, // offset
        GIR_CustomOperandRenderer, /*InsnID*/0, /*OldInsnID*/0, /*OpIdx*/7, /*OperandRenderer*/GIMT_Encode2(GICR_renderExtractCpolSetGLC), // auxiliary
        GIR_MergeMemOperands, /*InsnID*/0, /*NumInsns*/1, /*MergeInsnID's*/0,
        GIR_ConstrainSelectedInstOperands, /*InsnID*/0,
        GIR_EraseFromParent, /*InsnID*/0,
        // GIR_Coverage, 5252,
        GIR_Done,
      // Label 5909: @431630
      GIM_Reject,
    // Label 5893: @431631
    GIM_Reject,
    // Label 5874: @431632
    GIM_Try, /*On fail goto*//*Label 5910*/ GIMT_Encode4(433042),
      GIM_CheckType, /*MI*/0, /*Op*/1, /*Type*/GILLT_v2s16,
      GIM_CheckType, /*MI*/0, /*Op*/2, /*Type*/GILLT_v4s32,
      GIM_CheckType, /*MI*/0, /*Op*/3, /*Type*/GILLT_s32,
      GIM_CheckType, /*MI*/0, /*Op*/4, /*Type*/GILLT_s32,
      GIM_CheckType, /*MI*/0, /*Op*/5, /*Type*/GILLT_s32,
      GIM_Try, /*On fail goto*//*Label 5911*/ GIMT_Encode4(431735), // Rule ID 5217 //
        GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasAtomicBufferGlobalPkAddF16NoRtnInsts_isGFX9Only),
        GIM_CheckHasNoUse, /*MI*/0,
        GIM_CheckConstantInt8, /*MI*/0, /*Op*/3, 0,
        GIM_CheckConstantInt8, /*MI*/0, /*Op*/4, 0,
        // MIs[0] offset
        GIM_CheckIsImm, /*MI*/0, /*Op*/6,
        // MIs[0] auxiliary
        GIM_CheckIsImm, /*MI*/0, /*Op*/7,
        // MIs[0] Operand 8
        GIM_CheckLiteralInt, /*MI*/0, /*Op*/8, GIMT_Encode8(0),
        GIM_CheckComplexPattern, /*MI*/0, /*Op*/5, /*Renderer*/GIMT_Encode2(0), GIMT_Encode2(GICP_gi_buf_soffset),
        // (SIbuffer_atomic_fadd:{ *:[v2f16] } v2f16:{ *:[v2f16] }:$vdata_in, v4i32:{ *:[v4i32] }:$rsrc, 0:{ *:[i32] }, 0:{ *:[i32] }, (BUFSOffset:{ *:[i32] } i32:{ *:[i32] }:$soffset), (timm:{ *:[i32] }):$offset, (timm:{ *:[i32] }):$auxiliary, 0:{ *:[i1] })<<P:Predicate_SIbuffer_atomic_fadd_noret>>  =>  (BUFFER_ATOMIC_PK_ADD_F16_OFFSET anonymous_15037:{ *:[v2f16] }:$vdata_in, SReg_128:{ *:[v4i32] }:$rsrc, SCSrc_b32:{ *:[i32] }:$soffset, (timm:{ *:[i32] }):$offset, (extract_cpol:{ *:[i32] } ?:{ *:[i32] }:$auxiliary))
        GIR_BuildMI, /*InsnID*/0, /*Opcode*/GIMT_Encode2(AMDGPU::BUFFER_ATOMIC_PK_ADD_F16_OFFSET),
        GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/1, // vdata_in
        GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/2, // rsrc
        GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/0, // soffset
        GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/6, // offset
        GIR_CustomOperandRenderer, /*InsnID*/0, /*OldInsnID*/0, /*OpIdx*/7, /*OperandRenderer*/GIMT_Encode2(GICR_renderExtractCPol), // auxiliary
        GIR_MergeMemOperands, /*InsnID*/0, /*NumInsns*/1, /*MergeInsnID's*/0,
        GIR_ConstrainSelectedInstOperands, /*InsnID*/0,
        GIR_EraseFromParent, /*InsnID*/0,
        // GIR_Coverage, 5217,
        GIR_Done,
      // Label 5911: @431735
      GIM_Try, /*On fail goto*//*Label 5912*/ GIMT_Encode4(431813), // Rule ID 5221 //
        GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasAtomicBufferGlobalPkAddF16NoRtnInsts_isGFX12Plus),
        GIM_CheckHasNoUse, /*MI*/0,
        GIM_CheckConstantInt8, /*MI*/0, /*Op*/3, 0,
        GIM_CheckConstantInt8, /*MI*/0, /*Op*/4, 0,
        // MIs[0] offset
        GIM_CheckIsImm, /*MI*/0, /*Op*/6,
        // MIs[0] auxiliary
        GIM_CheckIsImm, /*MI*/0, /*Op*/7,
        // MIs[0] Operand 8
        GIM_CheckLiteralInt, /*MI*/0, /*Op*/8, GIMT_Encode8(0),
        GIM_CheckComplexPattern, /*MI*/0, /*Op*/5, /*Renderer*/GIMT_Encode2(0), GIMT_Encode2(GICP_gi_buf_soffset),
        // (SIbuffer_atomic_fadd:{ *:[v2f16] } v2f16:{ *:[v2f16] }:$vdata_in, v4i32:{ *:[v4i32] }:$rsrc, 0:{ *:[i32] }, 0:{ *:[i32] }, (BUFSOffset:{ *:[i32] } i32:{ *:[i32] }:$soffset), (timm:{ *:[i32] }):$offset, (timm:{ *:[i32] }):$auxiliary, 0:{ *:[i1] })<<P:Predicate_SIbuffer_atomic_fadd_noret>>  =>  (BUFFER_ATOMIC_PK_ADD_F16_VBUFFER_OFFSET anonymous_15037:{ *:[v2f16] }:$vdata_in, SReg_128:{ *:[v4i32] }:$rsrc, SCSrc_b32:{ *:[i32] }:$soffset, (timm:{ *:[i32] }):$offset, (extract_cpol:{ *:[i32] } ?:{ *:[i32] }:$auxiliary))
        GIR_BuildMI, /*InsnID*/0, /*Opcode*/GIMT_Encode2(AMDGPU::BUFFER_ATOMIC_PK_ADD_F16_VBUFFER_OFFSET),
        GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/1, // vdata_in
        GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/2, // rsrc
        GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/0, // soffset
        GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/6, // offset
        GIR_CustomOperandRenderer, /*InsnID*/0, /*OldInsnID*/0, /*OpIdx*/7, /*OperandRenderer*/GIMT_Encode2(GICR_renderExtractCPol), // auxiliary
        GIR_MergeMemOperands, /*InsnID*/0, /*NumInsns*/1, /*MergeInsnID's*/0,
        GIR_ConstrainSelectedInstOperands, /*InsnID*/0,
        GIR_EraseFromParent, /*InsnID*/0,
        // GIR_Coverage, 5221,
        GIR_Done,
      // Label 5912: @431813
      GIM_Try, /*On fail goto*//*Label 5913*/ GIMT_Encode4(431898), // Rule ID 5233 //
        GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasAtomicBufferGlobalPkAddF16Insts_isGFX9Only),
        GIM_CheckRegBankForClass, /*MI*/0, /*Op*/0, /*RC*/GIMT_Encode2(AMDGPU::AV_32RegClassID),
        GIM_CheckConstantInt8, /*MI*/0, /*Op*/3, 0,
        GIM_CheckConstantInt8, /*MI*/0, /*Op*/4, 0,
        // MIs[0] offset
        GIM_CheckIsImm, /*MI*/0, /*Op*/6,
        // MIs[0] auxiliary
        GIM_CheckIsImm, /*MI*/0, /*Op*/7,
        // MIs[0] Operand 8
        GIM_CheckLiteralInt, /*MI*/0, /*Op*/8, GIMT_Encode8(0),
        GIM_CheckComplexPattern, /*MI*/0, /*Op*/5, /*Renderer*/GIMT_Encode2(0), GIMT_Encode2(GICP_gi_buf_soffset),
        // (SIbuffer_atomic_fadd:{ *:[v2f16] } v2f16:{ *:[v2f16] }:$vdata_in, v4i32:{ *:[v4i32] }:$rsrc, 0:{ *:[i32] }, 0:{ *:[i32] }, (BUFSOffset:{ *:[i32] } i32:{ *:[i32] }:$soffset), (timm:{ *:[i32] }):$offset, (timm:{ *:[i32] }):$auxiliary, 0:{ *:[i1] })  =>  (BUFFER_ATOMIC_PK_ADD_F16_OFFSET_RTN:{ *:[v2f16] } anonymous_15037:{ *:[v2f16] }:$vdata_in, SReg_128:{ *:[v4i32] }:$rsrc, SCSrc_b32:{ *:[i32] }:$soffset, (timm:{ *:[i32] }):$offset, (extract_cpol_set_glc:{ *:[i32] } ?:{ *:[i32] }:$auxiliary))
        GIR_BuildMI, /*InsnID*/0, /*Opcode*/GIMT_Encode2(AMDGPU::BUFFER_ATOMIC_PK_ADD_F16_OFFSET_RTN),
        GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/0, // DstI[vdata]
        GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/1, // vdata_in
        GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/2, // rsrc
        GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/0, // soffset
        GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/6, // offset
        GIR_CustomOperandRenderer, /*InsnID*/0, /*OldInsnID*/0, /*OpIdx*/7, /*OperandRenderer*/GIMT_Encode2(GICR_renderExtractCpolSetGLC), // auxiliary
        GIR_MergeMemOperands, /*InsnID*/0, /*NumInsns*/1, /*MergeInsnID's*/0,
        GIR_ConstrainSelectedInstOperands, /*InsnID*/0,
        GIR_EraseFromParent, /*InsnID*/0,
        // GIR_Coverage, 5233,
        GIR_Done,
      // Label 5913: @431898
      GIM_Try, /*On fail goto*//*Label 5914*/ GIMT_Encode4(431983), // Rule ID 5237 //
        GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasAtomicBufferGlobalPkAddF16Insts_isGFX12Plus),
        GIM_CheckRegBankForClass, /*MI*/0, /*Op*/0, /*RC*/GIMT_Encode2(AMDGPU::AV_32RegClassID),
        GIM_CheckConstantInt8, /*MI*/0, /*Op*/3, 0,
        GIM_CheckConstantInt8, /*MI*/0, /*Op*/4, 0,
        // MIs[0] offset
        GIM_CheckIsImm, /*MI*/0, /*Op*/6,
        // MIs[0] auxiliary
        GIM_CheckIsImm, /*MI*/0, /*Op*/7,
        // MIs[0] Operand 8
        GIM_CheckLiteralInt, /*MI*/0, /*Op*/8, GIMT_Encode8(0),
        GIM_CheckComplexPattern, /*MI*/0, /*Op*/5, /*Renderer*/GIMT_Encode2(0), GIMT_Encode2(GICP_gi_buf_soffset),
        // (SIbuffer_atomic_fadd:{ *:[v2f16] } v2f16:{ *:[v2f16] }:$vdata_in, v4i32:{ *:[v4i32] }:$rsrc, 0:{ *:[i32] }, 0:{ *:[i32] }, (BUFSOffset:{ *:[i32] } i32:{ *:[i32] }:$soffset), (timm:{ *:[i32] }):$offset, (timm:{ *:[i32] }):$auxiliary, 0:{ *:[i1] })  =>  (BUFFER_ATOMIC_PK_ADD_F16_VBUFFER_OFFSET_RTN:{ *:[v2f16] } anonymous_15037:{ *:[v2f16] }:$vdata_in, SReg_128:{ *:[v4i32] }:$rsrc, SCSrc_b32:{ *:[i32] }:$soffset, (timm:{ *:[i32] }):$offset, (extract_cpol_set_glc:{ *:[i32] } ?:{ *:[i32] }:$auxiliary))
        GIR_BuildMI, /*InsnID*/0, /*Opcode*/GIMT_Encode2(AMDGPU::BUFFER_ATOMIC_PK_ADD_F16_VBUFFER_OFFSET_RTN),
        GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/0, // DstI[vdata]
        GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/1, // vdata_in
        GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/2, // rsrc
        GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/0, // soffset
        GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/6, // offset
        GIR_CustomOperandRenderer, /*InsnID*/0, /*OldInsnID*/0, /*OpIdx*/7, /*OperandRenderer*/GIMT_Encode2(GICR_renderExtractCpolSetGLC), // auxiliary
        GIR_MergeMemOperands, /*InsnID*/0, /*NumInsns*/1, /*MergeInsnID's*/0,
        GIR_ConstrainSelectedInstOperands, /*InsnID*/0,
        GIR_EraseFromParent, /*InsnID*/0,
        // GIR_Coverage, 5237,
        GIR_Done,
      // Label 5914: @431983
      GIM_Try, /*On fail goto*//*Label 5915*/ GIMT_Encode4(432061), // Rule ID 5219 //
        GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasAtomicBufferGlobalPkAddF16NoRtnInsts_isGFX9Only),
        GIM_CheckHasNoUse, /*MI*/0,
        GIM_CheckConstantInt8, /*MI*/0, /*Op*/3, 0,
        // MIs[0] offset
        GIM_CheckIsImm, /*MI*/0, /*Op*/6,
        // MIs[0] auxiliary
        GIM_CheckIsImm, /*MI*/0, /*Op*/7,
        // MIs[0] Operand 8
        GIM_CheckLiteralInt, /*MI*/0, /*Op*/8, GIMT_Encode8(0),
        GIM_CheckComplexPattern, /*MI*/0, /*Op*/5, /*Renderer*/GIMT_Encode2(0), GIMT_Encode2(GICP_gi_buf_soffset),
        // (SIbuffer_atomic_fadd:{ *:[v2f16] } v2f16:{ *:[v2f16] }:$vdata_in, v4i32:{ *:[v4i32] }:$rsrc, 0:{ *:[i32] }, i32:{ *:[i32] }:$voffset, (BUFSOffset:{ *:[i32] } i32:{ *:[i32] }:$soffset), (timm:{ *:[i32] }):$offset, (timm:{ *:[i32] }):$auxiliary, 0:{ *:[i1] })<<P:Predicate_SIbuffer_atomic_fadd_noret>>  =>  (BUFFER_ATOMIC_PK_ADD_F16_OFFEN anonymous_15037:{ *:[v2f16] }:$vdata_in, VGPR_32:{ *:[i32] }:$voffset, SReg_128:{ *:[v4i32] }:$rsrc, SCSrc_b32:{ *:[i32] }:$soffset, (timm:{ *:[i32] }):$offset, (extract_cpol:{ *:[i32] } ?:{ *:[i32] }:$auxiliary))
        GIR_BuildMI, /*InsnID*/0, /*Opcode*/GIMT_Encode2(AMDGPU::BUFFER_ATOMIC_PK_ADD_F16_OFFEN),
        GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/1, // vdata_in
        GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/4, // voffset
        GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/2, // rsrc
        GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/0, // soffset
        GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/6, // offset
        GIR_CustomOperandRenderer, /*InsnID*/0, /*OldInsnID*/0, /*OpIdx*/7, /*OperandRenderer*/GIMT_Encode2(GICR_renderExtractCPol), // auxiliary
        GIR_MergeMemOperands, /*InsnID*/0, /*NumInsns*/1, /*MergeInsnID's*/0,
        GIR_ConstrainSelectedInstOperands, /*InsnID*/0,
        GIR_EraseFromParent, /*InsnID*/0,
        // GIR_Coverage, 5219,
        GIR_Done,
      // Label 5915: @432061
      GIM_Try, /*On fail goto*//*Label 5916*/ GIMT_Encode4(432139), // Rule ID 5223 //
        GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasAtomicBufferGlobalPkAddF16NoRtnInsts_isGFX12Plus),
        GIM_CheckHasNoUse, /*MI*/0,
        GIM_CheckConstantInt8, /*MI*/0, /*Op*/3, 0,
        // MIs[0] offset
        GIM_CheckIsImm, /*MI*/0, /*Op*/6,
        // MIs[0] auxiliary
        GIM_CheckIsImm, /*MI*/0, /*Op*/7,
        // MIs[0] Operand 8
        GIM_CheckLiteralInt, /*MI*/0, /*Op*/8, GIMT_Encode8(0),
        GIM_CheckComplexPattern, /*MI*/0, /*Op*/5, /*Renderer*/GIMT_Encode2(0), GIMT_Encode2(GICP_gi_buf_soffset),
        // (SIbuffer_atomic_fadd:{ *:[v2f16] } v2f16:{ *:[v2f16] }:$vdata_in, v4i32:{ *:[v4i32] }:$rsrc, 0:{ *:[i32] }, i32:{ *:[i32] }:$voffset, (BUFSOffset:{ *:[i32] } i32:{ *:[i32] }:$soffset), (timm:{ *:[i32] }):$offset, (timm:{ *:[i32] }):$auxiliary, 0:{ *:[i1] })<<P:Predicate_SIbuffer_atomic_fadd_noret>>  =>  (BUFFER_ATOMIC_PK_ADD_F16_VBUFFER_OFFEN anonymous_15037:{ *:[v2f16] }:$vdata_in, VGPR_32:{ *:[i32] }:$voffset, SReg_128:{ *:[v4i32] }:$rsrc, SCSrc_b32:{ *:[i32] }:$soffset, (timm:{ *:[i32] }):$offset, (extract_cpol:{ *:[i32] } ?:{ *:[i32] }:$auxiliary))
        GIR_BuildMI, /*InsnID*/0, /*Opcode*/GIMT_Encode2(AMDGPU::BUFFER_ATOMIC_PK_ADD_F16_VBUFFER_OFFEN),
        GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/1, // vdata_in
        GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/4, // voffset
        GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/2, // rsrc
        GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/0, // soffset
        GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/6, // offset
        GIR_CustomOperandRenderer, /*InsnID*/0, /*OldInsnID*/0, /*OpIdx*/7, /*OperandRenderer*/GIMT_Encode2(GICR_renderExtractCPol), // auxiliary
        GIR_MergeMemOperands, /*InsnID*/0, /*NumInsns*/1, /*MergeInsnID's*/0,
        GIR_ConstrainSelectedInstOperands, /*InsnID*/0,
        GIR_EraseFromParent, /*InsnID*/0,
        // GIR_Coverage, 5223,
        GIR_Done,
      // Label 5916: @432139
      GIM_Try, /*On fail goto*//*Label 5917*/ GIMT_Encode4(432224), // Rule ID 5235 //
        GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasAtomicBufferGlobalPkAddF16Insts_isGFX9Only),
        GIM_CheckRegBankForClass, /*MI*/0, /*Op*/0, /*RC*/GIMT_Encode2(AMDGPU::AV_32RegClassID),
        GIM_CheckConstantInt8, /*MI*/0, /*Op*/3, 0,
        // MIs[0] offset
        GIM_CheckIsImm, /*MI*/0, /*Op*/6,
        // MIs[0] auxiliary
        GIM_CheckIsImm, /*MI*/0, /*Op*/7,
        // MIs[0] Operand 8
        GIM_CheckLiteralInt, /*MI*/0, /*Op*/8, GIMT_Encode8(0),
        GIM_CheckComplexPattern, /*MI*/0, /*Op*/5, /*Renderer*/GIMT_Encode2(0), GIMT_Encode2(GICP_gi_buf_soffset),
        // (SIbuffer_atomic_fadd:{ *:[v2f16] } v2f16:{ *:[v2f16] }:$vdata_in, v4i32:{ *:[v4i32] }:$rsrc, 0:{ *:[i32] }, i32:{ *:[i32] }:$voffset, (BUFSOffset:{ *:[i32] } i32:{ *:[i32] }:$soffset), (timm:{ *:[i32] }):$offset, (timm:{ *:[i32] }):$auxiliary, 0:{ *:[i1] })  =>  (BUFFER_ATOMIC_PK_ADD_F16_OFFEN_RTN:{ *:[v2f16] } anonymous_15037:{ *:[v2f16] }:$vdata_in, VGPR_32:{ *:[i32] }:$voffset, SReg_128:{ *:[v4i32] }:$rsrc, SCSrc_b32:{ *:[i32] }:$soffset, (timm:{ *:[i32] }):$offset, (extract_cpol_set_glc:{ *:[i32] } ?:{ *:[i32] }:$auxiliary))
        GIR_BuildMI, /*InsnID*/0, /*Opcode*/GIMT_Encode2(AMDGPU::BUFFER_ATOMIC_PK_ADD_F16_OFFEN_RTN),
        GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/0, // DstI[vdata]
        GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/1, // vdata_in
        GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/4, // voffset
        GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/2, // rsrc
        GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/0, // soffset
        GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/6, // offset
        GIR_CustomOperandRenderer, /*InsnID*/0, /*OldInsnID*/0, /*OpIdx*/7, /*OperandRenderer*/GIMT_Encode2(GICR_renderExtractCpolSetGLC), // auxiliary
        GIR_MergeMemOperands, /*InsnID*/0, /*NumInsns*/1, /*MergeInsnID's*/0,
        GIR_ConstrainSelectedInstOperands, /*InsnID*/0,
        GIR_EraseFromParent, /*InsnID*/0,
        // GIR_Coverage, 5235,
        GIR_Done,
      // Label 5917: @432224
      GIM_Try, /*On fail goto*//*Label 5918*/ GIMT_Encode4(432309), // Rule ID 5239 //
        GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasAtomicBufferGlobalPkAddF16Insts_isGFX12Plus),
        GIM_CheckRegBankForClass, /*MI*/0, /*Op*/0, /*RC*/GIMT_Encode2(AMDGPU::AV_32RegClassID),
        GIM_CheckConstantInt8, /*MI*/0, /*Op*/3, 0,
        // MIs[0] offset
        GIM_CheckIsImm, /*MI*/0, /*Op*/6,
        // MIs[0] auxiliary
        GIM_CheckIsImm, /*MI*/0, /*Op*/7,
        // MIs[0] Operand 8
        GIM_CheckLiteralInt, /*MI*/0, /*Op*/8, GIMT_Encode8(0),
        GIM_CheckComplexPattern, /*MI*/0, /*Op*/5, /*Renderer*/GIMT_Encode2(0), GIMT_Encode2(GICP_gi_buf_soffset),
        // (SIbuffer_atomic_fadd:{ *:[v2f16] } v2f16:{ *:[v2f16] }:$vdata_in, v4i32:{ *:[v4i32] }:$rsrc, 0:{ *:[i32] }, i32:{ *:[i32] }:$voffset, (BUFSOffset:{ *:[i32] } i32:{ *:[i32] }:$soffset), (timm:{ *:[i32] }):$offset, (timm:{ *:[i32] }):$auxiliary, 0:{ *:[i1] })  =>  (BUFFER_ATOMIC_PK_ADD_F16_VBUFFER_OFFEN_RTN:{ *:[v2f16] } anonymous_15037:{ *:[v2f16] }:$vdata_in, VGPR_32:{ *:[i32] }:$voffset, SReg_128:{ *:[v4i32] }:$rsrc, SCSrc_b32:{ *:[i32] }:$soffset, (timm:{ *:[i32] }):$offset, (extract_cpol_set_glc:{ *:[i32] } ?:{ *:[i32] }:$auxiliary))
        GIR_BuildMI, /*InsnID*/0, /*Opcode*/GIMT_Encode2(AMDGPU::BUFFER_ATOMIC_PK_ADD_F16_VBUFFER_OFFEN_RTN),
        GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/0, // DstI[vdata]
        GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/1, // vdata_in
        GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/4, // voffset
        GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/2, // rsrc
        GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/0, // soffset
        GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/6, // offset
        GIR_CustomOperandRenderer, /*InsnID*/0, /*OldInsnID*/0, /*OpIdx*/7, /*OperandRenderer*/GIMT_Encode2(GICR_renderExtractCpolSetGLC), // auxiliary
        GIR_MergeMemOperands, /*InsnID*/0, /*NumInsns*/1, /*MergeInsnID's*/0,
        GIR_ConstrainSelectedInstOperands, /*InsnID*/0,
        GIR_EraseFromParent, /*InsnID*/0,
        // GIR_Coverage, 5239,
        GIR_Done,
      // Label 5918: @432309
      GIM_Try, /*On fail goto*//*Label 5919*/ GIMT_Encode4(432379), // Rule ID 5218 //
        GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasAtomicBufferGlobalPkAddF16NoRtnInsts_isGFX9Only),
        GIM_CheckHasNoUse, /*MI*/0,
        GIM_CheckConstantInt8, /*MI*/0, /*Op*/4, 0,
        // MIs[0] offset
        GIM_CheckIsImm, /*MI*/0, /*Op*/6,
        // MIs[0] auxiliary
        GIM_CheckIsImm, /*MI*/0, /*Op*/7,
        // MIs[0] Operand 8
        GIM_CheckIsImm, /*MI*/0, /*Op*/8,
        GIM_CheckComplexPattern, /*MI*/0, /*Op*/5, /*Renderer*/GIMT_Encode2(0), GIMT_Encode2(GICP_gi_buf_soffset),
        // (SIbuffer_atomic_fadd:{ *:[v2f16] } v2f16:{ *:[v2f16] }:$vdata_in, v4i32:{ *:[v4i32] }:$rsrc, i32:{ *:[i32] }:$vindex, 0:{ *:[i32] }, (BUFSOffset:{ *:[i32] } i32:{ *:[i32] }:$soffset), (timm:{ *:[i32] }):$offset, (timm:{ *:[i32] }):$auxiliary, (timm:{ *:[i1] }))<<P:Predicate_SIbuffer_atomic_fadd_noret>>  =>  (BUFFER_ATOMIC_PK_ADD_F16_IDXEN anonymous_15037:{ *:[v2f16] }:$vdata_in, VGPR_32:{ *:[i32] }:$vindex, SReg_128:{ *:[v4i32] }:$rsrc, SCSrc_b32:{ *:[i32] }:$soffset, (timm:{ *:[i32] }):$offset, (extract_cpol:{ *:[i32] } ?:{ *:[i32] }:$auxiliary))
        GIR_BuildMI, /*InsnID*/0, /*Opcode*/GIMT_Encode2(AMDGPU::BUFFER_ATOMIC_PK_ADD_F16_IDXEN),
        GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/1, // vdata_in
        GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/3, // vindex
        GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/2, // rsrc
        GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/0, // soffset
        GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/6, // offset
        GIR_CustomOperandRenderer, /*InsnID*/0, /*OldInsnID*/0, /*OpIdx*/7, /*OperandRenderer*/GIMT_Encode2(GICR_renderExtractCPol), // auxiliary
        GIR_MergeMemOperands, /*InsnID*/0, /*NumInsns*/1, /*MergeInsnID's*/0,
        GIR_ConstrainSelectedInstOperands, /*InsnID*/0,
        GIR_EraseFromParent, /*InsnID*/0,
        // GIR_Coverage, 5218,
        GIR_Done,
      // Label 5919: @432379
      GIM_Try, /*On fail goto*//*Label 5920*/ GIMT_Encode4(432449), // Rule ID 5222 //
        GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasAtomicBufferGlobalPkAddF16NoRtnInsts_isGFX12Plus),
        GIM_CheckHasNoUse, /*MI*/0,
        GIM_CheckConstantInt8, /*MI*/0, /*Op*/4, 0,
        // MIs[0] offset
        GIM_CheckIsImm, /*MI*/0, /*Op*/6,
        // MIs[0] auxiliary
        GIM_CheckIsImm, /*MI*/0, /*Op*/7,
        // MIs[0] Operand 8
        GIM_CheckIsImm, /*MI*/0, /*Op*/8,
        GIM_CheckComplexPattern, /*MI*/0, /*Op*/5, /*Renderer*/GIMT_Encode2(0), GIMT_Encode2(GICP_gi_buf_soffset),
        // (SIbuffer_atomic_fadd:{ *:[v2f16] } v2f16:{ *:[v2f16] }:$vdata_in, v4i32:{ *:[v4i32] }:$rsrc, i32:{ *:[i32] }:$vindex, 0:{ *:[i32] }, (BUFSOffset:{ *:[i32] } i32:{ *:[i32] }:$soffset), (timm:{ *:[i32] }):$offset, (timm:{ *:[i32] }):$auxiliary, (timm:{ *:[i1] }))<<P:Predicate_SIbuffer_atomic_fadd_noret>>  =>  (BUFFER_ATOMIC_PK_ADD_F16_VBUFFER_IDXEN anonymous_15037:{ *:[v2f16] }:$vdata_in, VGPR_32:{ *:[i32] }:$vindex, SReg_128:{ *:[v4i32] }:$rsrc, SCSrc_b32:{ *:[i32] }:$soffset, (timm:{ *:[i32] }):$offset, (extract_cpol:{ *:[i32] } ?:{ *:[i32] }:$auxiliary))
        GIR_BuildMI, /*InsnID*/0, /*Opcode*/GIMT_Encode2(AMDGPU::BUFFER_ATOMIC_PK_ADD_F16_VBUFFER_IDXEN),
        GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/1, // vdata_in
        GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/3, // vindex
        GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/2, // rsrc
        GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/0, // soffset
        GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/6, // offset
        GIR_CustomOperandRenderer, /*InsnID*/0, /*OldInsnID*/0, /*OpIdx*/7, /*OperandRenderer*/GIMT_Encode2(GICR_renderExtractCPol), // auxiliary
        GIR_MergeMemOperands, /*InsnID*/0, /*NumInsns*/1, /*MergeInsnID's*/0,
        GIR_ConstrainSelectedInstOperands, /*InsnID*/0,
        GIR_EraseFromParent, /*InsnID*/0,
        // GIR_Coverage, 5222,
        GIR_Done,
      // Label 5920: @432449
      GIM_Try, /*On fail goto*//*Label 5921*/ GIMT_Encode4(432526), // Rule ID 5234 //
        GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasAtomicBufferGlobalPkAddF16Insts_isGFX9Only),
        GIM_CheckRegBankForClass, /*MI*/0, /*Op*/0, /*RC*/GIMT_Encode2(AMDGPU::AV_32RegClassID),
        GIM_CheckConstantInt8, /*MI*/0, /*Op*/4, 0,
        // MIs[0] offset
        GIM_CheckIsImm, /*MI*/0, /*Op*/6,
        // MIs[0] auxiliary
        GIM_CheckIsImm, /*MI*/0, /*Op*/7,
        // MIs[0] Operand 8
        GIM_CheckIsImm, /*MI*/0, /*Op*/8,
        GIM_CheckComplexPattern, /*MI*/0, /*Op*/5, /*Renderer*/GIMT_Encode2(0), GIMT_Encode2(GICP_gi_buf_soffset),
        // (SIbuffer_atomic_fadd:{ *:[v2f16] } v2f16:{ *:[v2f16] }:$vdata_in, v4i32:{ *:[v4i32] }:$rsrc, i32:{ *:[i32] }:$vindex, 0:{ *:[i32] }, (BUFSOffset:{ *:[i32] } i32:{ *:[i32] }:$soffset), (timm:{ *:[i32] }):$offset, (timm:{ *:[i32] }):$auxiliary, (timm:{ *:[i1] }))  =>  (BUFFER_ATOMIC_PK_ADD_F16_IDXEN_RTN:{ *:[v2f16] } anonymous_15037:{ *:[v2f16] }:$vdata_in, VGPR_32:{ *:[i32] }:$vindex, SReg_128:{ *:[v4i32] }:$rsrc, SCSrc_b32:{ *:[i32] }:$soffset, (timm:{ *:[i32] }):$offset, (extract_cpol_set_glc:{ *:[i32] } ?:{ *:[i32] }:$auxiliary))
        GIR_BuildMI, /*InsnID*/0, /*Opcode*/GIMT_Encode2(AMDGPU::BUFFER_ATOMIC_PK_ADD_F16_IDXEN_RTN),
        GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/0, // DstI[vdata]
        GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/1, // vdata_in
        GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/3, // vindex
        GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/2, // rsrc
        GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/0, // soffset
        GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/6, // offset
        GIR_CustomOperandRenderer, /*InsnID*/0, /*OldInsnID*/0, /*OpIdx*/7, /*OperandRenderer*/GIMT_Encode2(GICR_renderExtractCpolSetGLC), // auxiliary
        GIR_MergeMemOperands, /*InsnID*/0, /*NumInsns*/1, /*MergeInsnID's*/0,
        GIR_ConstrainSelectedInstOperands, /*InsnID*/0,
        GIR_EraseFromParent, /*InsnID*/0,
        // GIR_Coverage, 5234,
        GIR_Done,
      // Label 5921: @432526
      GIM_Try, /*On fail goto*//*Label 5922*/ GIMT_Encode4(432603), // Rule ID 5238 //
        GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasAtomicBufferGlobalPkAddF16Insts_isGFX12Plus),
        GIM_CheckRegBankForClass, /*MI*/0, /*Op*/0, /*RC*/GIMT_Encode2(AMDGPU::AV_32RegClassID),
        GIM_CheckConstantInt8, /*MI*/0, /*Op*/4, 0,
        // MIs[0] offset
        GIM_CheckIsImm, /*MI*/0, /*Op*/6,
        // MIs[0] auxiliary
        GIM_CheckIsImm, /*MI*/0, /*Op*/7,
        // MIs[0] Operand 8
        GIM_CheckIsImm, /*MI*/0, /*Op*/8,
        GIM_CheckComplexPattern, /*MI*/0, /*Op*/5, /*Renderer*/GIMT_Encode2(0), GIMT_Encode2(GICP_gi_buf_soffset),
        // (SIbuffer_atomic_fadd:{ *:[v2f16] } v2f16:{ *:[v2f16] }:$vdata_in, v4i32:{ *:[v4i32] }:$rsrc, i32:{ *:[i32] }:$vindex, 0:{ *:[i32] }, (BUFSOffset:{ *:[i32] } i32:{ *:[i32] }:$soffset), (timm:{ *:[i32] }):$offset, (timm:{ *:[i32] }):$auxiliary, (timm:{ *:[i1] }))  =>  (BUFFER_ATOMIC_PK_ADD_F16_VBUFFER_IDXEN_RTN:{ *:[v2f16] } anonymous_15037:{ *:[v2f16] }:$vdata_in, VGPR_32:{ *:[i32] }:$vindex, SReg_128:{ *:[v4i32] }:$rsrc, SCSrc_b32:{ *:[i32] }:$soffset, (timm:{ *:[i32] }):$offset, (extract_cpol_set_glc:{ *:[i32] } ?:{ *:[i32] }:$auxiliary))
        GIR_BuildMI, /*InsnID*/0, /*Opcode*/GIMT_Encode2(AMDGPU::BUFFER_ATOMIC_PK_ADD_F16_VBUFFER_IDXEN_RTN),
        GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/0, // DstI[vdata]
        GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/1, // vdata_in
        GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/3, // vindex
        GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/2, // rsrc
        GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/0, // soffset
        GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/6, // offset
        GIR_CustomOperandRenderer, /*InsnID*/0, /*OldInsnID*/0, /*OpIdx*/7, /*OperandRenderer*/GIMT_Encode2(GICR_renderExtractCpolSetGLC), // auxiliary
        GIR_MergeMemOperands, /*InsnID*/0, /*NumInsns*/1, /*MergeInsnID's*/0,
        GIR_ConstrainSelectedInstOperands, /*InsnID*/0,
        GIR_EraseFromParent, /*InsnID*/0,
        // GIR_Coverage, 5238,
        GIR_Done,
      // Label 5922: @432603
      GIM_Try, /*On fail goto*//*Label 5923*/ GIMT_Encode4(432709), // Rule ID 5220 //
        GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasAtomicBufferGlobalPkAddF16NoRtnInsts_isGFX9Only),
        GIM_CheckHasNoUse, /*MI*/0,
        // MIs[0] offset
        GIM_CheckIsImm, /*MI*/0, /*Op*/6,
        // MIs[0] auxiliary
        GIM_CheckIsImm, /*MI*/0, /*Op*/7,
        // MIs[0] Operand 8
        GIM_CheckIsImm, /*MI*/0, /*Op*/8,
        GIM_CheckComplexPattern, /*MI*/0, /*Op*/5, /*Renderer*/GIMT_Encode2(0), GIMT_Encode2(GICP_gi_buf_soffset),
        // (SIbuffer_atomic_fadd:{ *:[v2f16] } v2f16:{ *:[v2f16] }:$vdata_in, v4i32:{ *:[v4i32] }:$rsrc, i32:{ *:[i32] }:$vindex, i32:{ *:[i32] }:$voffset, (BUFSOffset:{ *:[i32] } i32:{ *:[i32] }:$soffset), (timm:{ *:[i32] }):$offset, (timm:{ *:[i32] }):$auxiliary, (timm:{ *:[i1] }))<<P:Predicate_SIbuffer_atomic_fadd_noret>>  =>  (BUFFER_ATOMIC_PK_ADD_F16_BOTHEN anonymous_15037:{ *:[v2f16] }:$vdata_in, (REG_SEQUENCE:{ *:[i64] } VReg_64:{ *:[i32] }, VGPR_32:{ *:[i32] }:$vindex, sub0:{ *:[i32] }, VGPR_32:{ *:[i32] }:$voffset, sub1:{ *:[i32] }), SReg_128:{ *:[v4i32] }:$rsrc, SCSrc_b32:{ *:[i32] }:$soffset, (timm:{ *:[i32] }):$offset, (extract_cpol:{ *:[i32] } ?:{ *:[i32] }:$auxiliary))
        GIR_MakeTempReg, /*TempRegID*/0, /*TypeID*/GILLT_s64,
        GIR_BuildMI, /*InsnID*/1, /*Opcode*/GIMT_Encode2(TargetOpcode::REG_SEQUENCE),
        GIR_AddTempRegister, /*InsnID*/1, /*TempRegID*/0, /*TempRegFlags*/GIMT_Encode2(RegState::Define),
        GIR_Copy, /*NewInsnID*/1, /*OldInsnID*/0, /*OpIdx*/3, // vindex
        GIR_AddImm8, /*InsnID*/1, /*SubRegIndex*/3,
        GIR_Copy, /*NewInsnID*/1, /*OldInsnID*/0, /*OpIdx*/4, // voffset
        GIR_AddImm8, /*InsnID*/1, /*SubRegIndex*/11,
        GIR_ConstrainOperandRC, /*InsnID*/1, /*Op*/0, GIMT_Encode2(AMDGPU::VReg_64RegClassID),
        GIR_ConstrainOperandRC, /*InsnID*/1, /*Op*/1, GIMT_Encode2(AMDGPU::VGPR_32RegClassID),
        GIR_ConstrainOperandRC, /*InsnID*/1, /*Op*/3, GIMT_Encode2(AMDGPU::VGPR_32RegClassID),
        GIR_BuildMI, /*InsnID*/0, /*Opcode*/GIMT_Encode2(AMDGPU::BUFFER_ATOMIC_PK_ADD_F16_BOTHEN),
        GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/1, // vdata_in
        GIR_AddSimpleTempRegister, /*InsnID*/0, /*TempRegID*/0,
        GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/2, // rsrc
        GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/0, // soffset
        GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/6, // offset
        GIR_CustomOperandRenderer, /*InsnID*/0, /*OldInsnID*/0, /*OpIdx*/7, /*OperandRenderer*/GIMT_Encode2(GICR_renderExtractCPol), // auxiliary
        GIR_MergeMemOperands, /*InsnID*/0, /*NumInsns*/1, /*MergeInsnID's*/0,
        GIR_ConstrainSelectedInstOperands, /*InsnID*/0,
        GIR_EraseFromParent, /*InsnID*/0,
        // GIR_Coverage, 5220,
        GIR_Done,
      // Label 5923: @432709
      GIM_Try, /*On fail goto*//*Label 5924*/ GIMT_Encode4(432815), // Rule ID 5224 //
        GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasAtomicBufferGlobalPkAddF16NoRtnInsts_isGFX12Plus),
        GIM_CheckHasNoUse, /*MI*/0,
        // MIs[0] offset
        GIM_CheckIsImm, /*MI*/0, /*Op*/6,
        // MIs[0] auxiliary
        GIM_CheckIsImm, /*MI*/0, /*Op*/7,
        // MIs[0] Operand 8
        GIM_CheckIsImm, /*MI*/0, /*Op*/8,
        GIM_CheckComplexPattern, /*MI*/0, /*Op*/5, /*Renderer*/GIMT_Encode2(0), GIMT_Encode2(GICP_gi_buf_soffset),
        // (SIbuffer_atomic_fadd:{ *:[v2f16] } v2f16:{ *:[v2f16] }:$vdata_in, v4i32:{ *:[v4i32] }:$rsrc, i32:{ *:[i32] }:$vindex, i32:{ *:[i32] }:$voffset, (BUFSOffset:{ *:[i32] } i32:{ *:[i32] }:$soffset), (timm:{ *:[i32] }):$offset, (timm:{ *:[i32] }):$auxiliary, (timm:{ *:[i1] }))<<P:Predicate_SIbuffer_atomic_fadd_noret>>  =>  (BUFFER_ATOMIC_PK_ADD_F16_VBUFFER_BOTHEN anonymous_15037:{ *:[v2f16] }:$vdata_in, (REG_SEQUENCE:{ *:[i64] } VReg_64:{ *:[i32] }, VGPR_32:{ *:[i32] }:$vindex, sub0:{ *:[i32] }, VGPR_32:{ *:[i32] }:$voffset, sub1:{ *:[i32] }), SReg_128:{ *:[v4i32] }:$rsrc, SCSrc_b32:{ *:[i32] }:$soffset, (timm:{ *:[i32] }):$offset, (extract_cpol:{ *:[i32] } ?:{ *:[i32] }:$auxiliary))
        GIR_MakeTempReg, /*TempRegID*/0, /*TypeID*/GILLT_s64,
        GIR_BuildMI, /*InsnID*/1, /*Opcode*/GIMT_Encode2(TargetOpcode::REG_SEQUENCE),
        GIR_AddTempRegister, /*InsnID*/1, /*TempRegID*/0, /*TempRegFlags*/GIMT_Encode2(RegState::Define),
        GIR_Copy, /*NewInsnID*/1, /*OldInsnID*/0, /*OpIdx*/3, // vindex
        GIR_AddImm8, /*InsnID*/1, /*SubRegIndex*/3,
        GIR_Copy, /*NewInsnID*/1, /*OldInsnID*/0, /*OpIdx*/4, // voffset
        GIR_AddImm8, /*InsnID*/1, /*SubRegIndex*/11,
        GIR_ConstrainOperandRC, /*InsnID*/1, /*Op*/0, GIMT_Encode2(AMDGPU::VReg_64RegClassID),
        GIR_ConstrainOperandRC, /*InsnID*/1, /*Op*/1, GIMT_Encode2(AMDGPU::VGPR_32RegClassID),
        GIR_ConstrainOperandRC, /*InsnID*/1, /*Op*/3, GIMT_Encode2(AMDGPU::VGPR_32RegClassID),
        GIR_BuildMI, /*InsnID*/0, /*Opcode*/GIMT_Encode2(AMDGPU::BUFFER_ATOMIC_PK_ADD_F16_VBUFFER_BOTHEN),
        GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/1, // vdata_in
        GIR_AddSimpleTempRegister, /*InsnID*/0, /*TempRegID*/0,
        GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/2, // rsrc
        GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/0, // soffset
        GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/6, // offset
        GIR_CustomOperandRenderer, /*InsnID*/0, /*OldInsnID*/0, /*OpIdx*/7, /*OperandRenderer*/GIMT_Encode2(GICR_renderExtractCPol), // auxiliary
        GIR_MergeMemOperands, /*InsnID*/0, /*NumInsns*/1, /*MergeInsnID's*/0,
        GIR_ConstrainSelectedInstOperands, /*InsnID*/0,
        GIR_EraseFromParent, /*InsnID*/0,
        // GIR_Coverage, 5224,
        GIR_Done,
      // Label 5924: @432815
      GIM_Try, /*On fail goto*//*Label 5925*/ GIMT_Encode4(432928), // Rule ID 5236 //
        GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasAtomicBufferGlobalPkAddF16Insts_isGFX9Only),
        GIM_CheckRegBankForClass, /*MI*/0, /*Op*/0, /*RC*/GIMT_Encode2(AMDGPU::AV_32RegClassID),
        // MIs[0] offset
        GIM_CheckIsImm, /*MI*/0, /*Op*/6,
        // MIs[0] auxiliary
        GIM_CheckIsImm, /*MI*/0, /*Op*/7,
        // MIs[0] Operand 8
        GIM_CheckIsImm, /*MI*/0, /*Op*/8,
        GIM_CheckComplexPattern, /*MI*/0, /*Op*/5, /*Renderer*/GIMT_Encode2(0), GIMT_Encode2(GICP_gi_buf_soffset),
        // (SIbuffer_atomic_fadd:{ *:[v2f16] } v2f16:{ *:[v2f16] }:$vdata_in, v4i32:{ *:[v4i32] }:$rsrc, i32:{ *:[i32] }:$vindex, i32:{ *:[i32] }:$voffset, (BUFSOffset:{ *:[i32] } i32:{ *:[i32] }:$soffset), (timm:{ *:[i32] }):$offset, (timm:{ *:[i32] }):$auxiliary, (timm:{ *:[i1] }))  =>  (BUFFER_ATOMIC_PK_ADD_F16_BOTHEN_RTN:{ *:[v2f16] } anonymous_15037:{ *:[v2f16] }:$vdata_in, (REG_SEQUENCE:{ *:[i64] } VReg_64:{ *:[i32] }, VGPR_32:{ *:[i32] }:$vindex, sub0:{ *:[i32] }, VGPR_32:{ *:[i32] }:$voffset, sub1:{ *:[i32] }), SReg_128:{ *:[v4i32] }:$rsrc, SCSrc_b32:{ *:[i32] }:$soffset, (timm:{ *:[i32] }):$offset, (extract_cpol_set_glc:{ *:[i32] } ?:{ *:[i32] }:$auxiliary))
        GIR_MakeTempReg, /*TempRegID*/0, /*TypeID*/GILLT_s64,
        GIR_BuildMI, /*InsnID*/1, /*Opcode*/GIMT_Encode2(TargetOpcode::REG_SEQUENCE),
        GIR_AddTempRegister, /*InsnID*/1, /*TempRegID*/0, /*TempRegFlags*/GIMT_Encode2(RegState::Define),
        GIR_Copy, /*NewInsnID*/1, /*OldInsnID*/0, /*OpIdx*/3, // vindex
        GIR_AddImm8, /*InsnID*/1, /*SubRegIndex*/3,
        GIR_Copy, /*NewInsnID*/1, /*OldInsnID*/0, /*OpIdx*/4, // voffset
        GIR_AddImm8, /*InsnID*/1, /*SubRegIndex*/11,
        GIR_ConstrainOperandRC, /*InsnID*/1, /*Op*/0, GIMT_Encode2(AMDGPU::VReg_64RegClassID),
        GIR_ConstrainOperandRC, /*InsnID*/1, /*Op*/1, GIMT_Encode2(AMDGPU::VGPR_32RegClassID),
        GIR_ConstrainOperandRC, /*InsnID*/1, /*Op*/3, GIMT_Encode2(AMDGPU::VGPR_32RegClassID),
        GIR_BuildMI, /*InsnID*/0, /*Opcode*/GIMT_Encode2(AMDGPU::BUFFER_ATOMIC_PK_ADD_F16_BOTHEN_RTN),
        GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/0, // DstI[vdata]
        GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/1, // vdata_in
        GIR_AddSimpleTempRegister, /*InsnID*/0, /*TempRegID*/0,
        GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/2, // rsrc
        GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/0, // soffset
        GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/6, // offset
        GIR_CustomOperandRenderer, /*InsnID*/0, /*OldInsnID*/0, /*OpIdx*/7, /*OperandRenderer*/GIMT_Encode2(GICR_renderExtractCpolSetGLC), // auxiliary
        GIR_MergeMemOperands, /*InsnID*/0, /*NumInsns*/1, /*MergeInsnID's*/0,
        GIR_ConstrainSelectedInstOperands, /*InsnID*/0,
        GIR_EraseFromParent, /*InsnID*/0,
        // GIR_Coverage, 5236,
        GIR_Done,
      // Label 5925: @432928
      GIM_Try, /*On fail goto*//*Label 5926*/ GIMT_Encode4(433041), // Rule ID 5240 //
        GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasAtomicBufferGlobalPkAddF16Insts_isGFX12Plus),
        GIM_CheckRegBankForClass, /*MI*/0, /*Op*/0, /*RC*/GIMT_Encode2(AMDGPU::AV_32RegClassID),
        // MIs[0] offset
        GIM_CheckIsImm, /*MI*/0, /*Op*/6,
        // MIs[0] auxiliary
        GIM_CheckIsImm, /*MI*/0, /*Op*/7,
        // MIs[0] Operand 8
        GIM_CheckIsImm, /*MI*/0, /*Op*/8,
        GIM_CheckComplexPattern, /*MI*/0, /*Op*/5, /*Renderer*/GIMT_Encode2(0), GIMT_Encode2(GICP_gi_buf_soffset),
        // (SIbuffer_atomic_fadd:{ *:[v2f16] } v2f16:{ *:[v2f16] }:$vdata_in, v4i32:{ *:[v4i32] }:$rsrc, i32:{ *:[i32] }:$vindex, i32:{ *:[i32] }:$voffset, (BUFSOffset:{ *:[i32] } i32:{ *:[i32] }:$soffset), (timm:{ *:[i32] }):$offset, (timm:{ *:[i32] }):$auxiliary, (timm:{ *:[i1] }))  =>  (BUFFER_ATOMIC_PK_ADD_F16_VBUFFER_BOTHEN_RTN:{ *:[v2f16] } anonymous_15037:{ *:[v2f16] }:$vdata_in, (REG_SEQUENCE:{ *:[i64] } VReg_64:{ *:[i32] }, VGPR_32:{ *:[i32] }:$vindex, sub0:{ *:[i32] }, VGPR_32:{ *:[i32] }:$voffset, sub1:{ *:[i32] }), SReg_128:{ *:[v4i32] }:$rsrc, SCSrc_b32:{ *:[i32] }:$soffset, (timm:{ *:[i32] }):$offset, (extract_cpol_set_glc:{ *:[i32] } ?:{ *:[i32] }:$auxiliary))
        GIR_MakeTempReg, /*TempRegID*/0, /*TypeID*/GILLT_s64,
        GIR_BuildMI, /*InsnID*/1, /*Opcode*/GIMT_Encode2(TargetOpcode::REG_SEQUENCE),
        GIR_AddTempRegister, /*InsnID*/1, /*TempRegID*/0, /*TempRegFlags*/GIMT_Encode2(RegState::Define),
        GIR_Copy, /*NewInsnID*/1, /*OldInsnID*/0, /*OpIdx*/3, // vindex
        GIR_AddImm8, /*InsnID*/1, /*SubRegIndex*/3,
        GIR_Copy, /*NewInsnID*/1, /*OldInsnID*/0, /*OpIdx*/4, // voffset
        GIR_AddImm8, /*InsnID*/1, /*SubRegIndex*/11,
        GIR_ConstrainOperandRC, /*InsnID*/1, /*Op*/0, GIMT_Encode2(AMDGPU::VReg_64RegClassID),
        GIR_ConstrainOperandRC, /*InsnID*/1, /*Op*/1, GIMT_Encode2(AMDGPU::VGPR_32RegClassID),
        GIR_ConstrainOperandRC, /*InsnID*/1, /*Op*/3, GIMT_Encode2(AMDGPU::VGPR_32RegClassID),
        GIR_BuildMI, /*InsnID*/0, /*Opcode*/GIMT_Encode2(AMDGPU::BUFFER_ATOMIC_PK_ADD_F16_VBUFFER_BOTHEN_RTN),
        GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/0, // DstI[vdata]
        GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/1, // vdata_in
        GIR_AddSimpleTempRegister, /*InsnID*/0, /*TempRegID*/0,
        GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/2, // rsrc
        GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/0, // soffset
        GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/6, // offset
        GIR_CustomOperandRenderer, /*InsnID*/0, /*OldInsnID*/0, /*OpIdx*/7, /*OperandRenderer*/GIMT_Encode2(GICR_renderExtractCpolSetGLC), // auxiliary
        GIR_MergeMemOperands, /*InsnID*/0, /*NumInsns*/1, /*MergeInsnID's*/0,
        GIR_ConstrainSelectedInstOperands, /*InsnID*/0,
        GIR_EraseFromParent, /*InsnID*/0,
        // GIR_Coverage, 5240,
        GIR_Done,
      // Label 5926: @433041
      GIM_Reject,
    // Label 5910: @433042
    GIM_Reject,
    // Label 5875: @433043
    GIM_Reject,
    // Label 112: @433044
    GIM_Try, /*On fail goto*//*Label 5927*/ GIMT_Encode4(433766),
      GIM_CheckType, /*MI*/0, /*Op*/0, /*Type*/GILLT_v2s16,
      GIM_CheckType, /*MI*/0, /*Op*/1, /*Type*/GILLT_v2s16,
      GIM_CheckType, /*MI*/0, /*Op*/2, /*Type*/GILLT_v4s32,
      GIM_CheckType, /*MI*/0, /*Op*/3, /*Type*/GILLT_s32,
      GIM_CheckType, /*MI*/0, /*Op*/4, /*Type*/GILLT_s32,
      GIM_CheckType, /*MI*/0, /*Op*/5, /*Type*/GILLT_s32,
      GIM_Try, /*On fail goto*//*Label 5928*/ GIMT_Encode4(433151), // Rule ID 5133 //
        GIM_CheckFeatures, GIMT_Encode2(GIFBS_isGFX12Plus),
        GIM_CheckHasNoUse, /*MI*/0,
        GIM_CheckConstantInt8, /*MI*/0, /*Op*/3, 0,
        GIM_CheckConstantInt8, /*MI*/0, /*Op*/4, 0,
        // MIs[0] offset
        GIM_CheckIsImm, /*MI*/0, /*Op*/6,
        // MIs[0] auxiliary
        GIM_CheckIsImm, /*MI*/0, /*Op*/7,
        // MIs[0] Operand 8
        GIM_CheckLiteralInt, /*MI*/0, /*Op*/8, GIMT_Encode8(0),
        GIM_CheckComplexPattern, /*MI*/0, /*Op*/5, /*Renderer*/GIMT_Encode2(0), GIMT_Encode2(GICP_gi_buf_soffset),
        // (SIbuffer_atomic_fadd_bf16:{ *:[v2bf16] } v2bf16:{ *:[v2bf16] }:$vdata_in, v4i32:{ *:[v4i32] }:$rsrc, 0:{ *:[i32] }, 0:{ *:[i32] }, (BUFSOffset:{ *:[i32] } i32:{ *:[i32] }:$soffset), (timm:{ *:[i32] }):$offset, (timm:{ *:[i32] }):$auxiliary, 0:{ *:[i1] })<<P:Predicate_SIbuffer_atomic_fadd_bf16_noret>>  =>  (BUFFER_ATOMIC_PK_ADD_BF16_VBUFFER_OFFSET anonymous_15037:{ *:[v2bf16] }:$vdata_in, SReg_128:{ *:[v4i32] }:$rsrc, SCSrc_b32:{ *:[i32] }:$soffset, (timm:{ *:[i32] }):$offset, (extract_cpol:{ *:[i32] } ?:{ *:[i32] }:$auxiliary))
        GIR_BuildMI, /*InsnID*/0, /*Opcode*/GIMT_Encode2(AMDGPU::BUFFER_ATOMIC_PK_ADD_BF16_VBUFFER_OFFSET),
        GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/1, // vdata_in
        GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/2, // rsrc
        GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/0, // soffset
        GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/6, // offset
        GIR_CustomOperandRenderer, /*InsnID*/0, /*OldInsnID*/0, /*OpIdx*/7, /*OperandRenderer*/GIMT_Encode2(GICR_renderExtractCPol), // auxiliary
        GIR_MergeMemOperands, /*InsnID*/0, /*NumInsns*/1, /*MergeInsnID's*/0,
        GIR_ConstrainSelectedInstOperands, /*InsnID*/0,
        GIR_EraseFromParent, /*InsnID*/0,
        // GIR_Coverage, 5133,
        GIR_Done,
      // Label 5928: @433151
      GIM_Try, /*On fail goto*//*Label 5929*/ GIMT_Encode4(433236), // Rule ID 5129 //
        GIM_CheckFeatures, GIMT_Encode2(GIFBS_isGFX12Plus),
        GIM_CheckRegBankForClass, /*MI*/0, /*Op*/0, /*RC*/GIMT_Encode2(AMDGPU::AV_32RegClassID),
        GIM_CheckConstantInt8, /*MI*/0, /*Op*/3, 0,
        GIM_CheckConstantInt8, /*MI*/0, /*Op*/4, 0,
        // MIs[0] offset
        GIM_CheckIsImm, /*MI*/0, /*Op*/6,
        // MIs[0] auxiliary
        GIM_CheckIsImm, /*MI*/0, /*Op*/7,
        // MIs[0] Operand 8
        GIM_CheckLiteralInt, /*MI*/0, /*Op*/8, GIMT_Encode8(0),
        GIM_CheckComplexPattern, /*MI*/0, /*Op*/5, /*Renderer*/GIMT_Encode2(0), GIMT_Encode2(GICP_gi_buf_soffset),
        // (SIbuffer_atomic_fadd_bf16:{ *:[v2bf16] } v2bf16:{ *:[v2bf16] }:$vdata_in, v4i32:{ *:[v4i32] }:$rsrc, 0:{ *:[i32] }, 0:{ *:[i32] }, (BUFSOffset:{ *:[i32] } i32:{ *:[i32] }:$soffset), (timm:{ *:[i32] }):$offset, (timm:{ *:[i32] }):$auxiliary, 0:{ *:[i1] })  =>  (BUFFER_ATOMIC_PK_ADD_BF16_VBUFFER_OFFSET_RTN:{ *:[v2bf16] } anonymous_15037:{ *:[v2bf16] }:$vdata_in, SReg_128:{ *:[v4i32] }:$rsrc, SCSrc_b32:{ *:[i32] }:$soffset, (timm:{ *:[i32] }):$offset, (extract_cpol_set_glc:{ *:[i32] } ?:{ *:[i32] }:$auxiliary))
        GIR_BuildMI, /*InsnID*/0, /*Opcode*/GIMT_Encode2(AMDGPU::BUFFER_ATOMIC_PK_ADD_BF16_VBUFFER_OFFSET_RTN),
        GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/0, // DstI[vdata]
        GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/1, // vdata_in
        GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/2, // rsrc
        GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/0, // soffset
        GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/6, // offset
        GIR_CustomOperandRenderer, /*InsnID*/0, /*OldInsnID*/0, /*OpIdx*/7, /*OperandRenderer*/GIMT_Encode2(GICR_renderExtractCpolSetGLC), // auxiliary
        GIR_MergeMemOperands, /*InsnID*/0, /*NumInsns*/1, /*MergeInsnID's*/0,
        GIR_ConstrainSelectedInstOperands, /*InsnID*/0,
        GIR_EraseFromParent, /*InsnID*/0,
        // GIR_Coverage, 5129,
        GIR_Done,
      // Label 5929: @433236
      GIM_Try, /*On fail goto*//*Label 5930*/ GIMT_Encode4(433314), // Rule ID 5135 //
        GIM_CheckFeatures, GIMT_Encode2(GIFBS_isGFX12Plus),
        GIM_CheckHasNoUse, /*MI*/0,
        GIM_CheckConstantInt8, /*MI*/0, /*Op*/3, 0,
        // MIs[0] offset
        GIM_CheckIsImm, /*MI*/0, /*Op*/6,
        // MIs[0] auxiliary
        GIM_CheckIsImm, /*MI*/0, /*Op*/7,
        // MIs[0] Operand 8
        GIM_CheckLiteralInt, /*MI*/0, /*Op*/8, GIMT_Encode8(0),
        GIM_CheckComplexPattern, /*MI*/0, /*Op*/5, /*Renderer*/GIMT_Encode2(0), GIMT_Encode2(GICP_gi_buf_soffset),
        // (SIbuffer_atomic_fadd_bf16:{ *:[v2bf16] } v2bf16:{ *:[v2bf16] }:$vdata_in, v4i32:{ *:[v4i32] }:$rsrc, 0:{ *:[i32] }, i32:{ *:[i32] }:$voffset, (BUFSOffset:{ *:[i32] } i32:{ *:[i32] }:$soffset), (timm:{ *:[i32] }):$offset, (timm:{ *:[i32] }):$auxiliary, 0:{ *:[i1] })<<P:Predicate_SIbuffer_atomic_fadd_bf16_noret>>  =>  (BUFFER_ATOMIC_PK_ADD_BF16_VBUFFER_OFFEN anonymous_15037:{ *:[v2bf16] }:$vdata_in, VGPR_32:{ *:[i32] }:$voffset, SReg_128:{ *:[v4i32] }:$rsrc, SCSrc_b32:{ *:[i32] }:$soffset, (timm:{ *:[i32] }):$offset, (extract_cpol:{ *:[i32] } ?:{ *:[i32] }:$auxiliary))
        GIR_BuildMI, /*InsnID*/0, /*Opcode*/GIMT_Encode2(AMDGPU::BUFFER_ATOMIC_PK_ADD_BF16_VBUFFER_OFFEN),
        GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/1, // vdata_in
        GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/4, // voffset
        GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/2, // rsrc
        GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/0, // soffset
        GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/6, // offset
        GIR_CustomOperandRenderer, /*InsnID*/0, /*OldInsnID*/0, /*OpIdx*/7, /*OperandRenderer*/GIMT_Encode2(GICR_renderExtractCPol), // auxiliary
        GIR_MergeMemOperands, /*InsnID*/0, /*NumInsns*/1, /*MergeInsnID's*/0,
        GIR_ConstrainSelectedInstOperands, /*InsnID*/0,
        GIR_EraseFromParent, /*InsnID*/0,
        // GIR_Coverage, 5135,
        GIR_Done,
      // Label 5930: @433314
      GIM_Try, /*On fail goto*//*Label 5931*/ GIMT_Encode4(433399), // Rule ID 5131 //
        GIM_CheckFeatures, GIMT_Encode2(GIFBS_isGFX12Plus),
        GIM_CheckRegBankForClass, /*MI*/0, /*Op*/0, /*RC*/GIMT_Encode2(AMDGPU::AV_32RegClassID),
        GIM_CheckConstantInt8, /*MI*/0, /*Op*/3, 0,
        // MIs[0] offset
        GIM_CheckIsImm, /*MI*/0, /*Op*/6,
        // MIs[0] auxiliary
        GIM_CheckIsImm, /*MI*/0, /*Op*/7,
        // MIs[0] Operand 8
        GIM_CheckLiteralInt, /*MI*/0, /*Op*/8, GIMT_Encode8(0),
        GIM_CheckComplexPattern, /*MI*/0, /*Op*/5, /*Renderer*/GIMT_Encode2(0), GIMT_Encode2(GICP_gi_buf_soffset),
        // (SIbuffer_atomic_fadd_bf16:{ *:[v2bf16] } v2bf16:{ *:[v2bf16] }:$vdata_in, v4i32:{ *:[v4i32] }:$rsrc, 0:{ *:[i32] }, i32:{ *:[i32] }:$voffset, (BUFSOffset:{ *:[i32] } i32:{ *:[i32] }:$soffset), (timm:{ *:[i32] }):$offset, (timm:{ *:[i32] }):$auxiliary, 0:{ *:[i1] })  =>  (BUFFER_ATOMIC_PK_ADD_BF16_VBUFFER_OFFEN_RTN:{ *:[v2bf16] } anonymous_15037:{ *:[v2bf16] }:$vdata_in, VGPR_32:{ *:[i32] }:$voffset, SReg_128:{ *:[v4i32] }:$rsrc, SCSrc_b32:{ *:[i32] }:$soffset, (timm:{ *:[i32] }):$offset, (extract_cpol_set_glc:{ *:[i32] } ?:{ *:[i32] }:$auxiliary))
        GIR_BuildMI, /*InsnID*/0, /*Opcode*/GIMT_Encode2(AMDGPU::BUFFER_ATOMIC_PK_ADD_BF16_VBUFFER_OFFEN_RTN),
        GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/0, // DstI[vdata]
        GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/1, // vdata_in
        GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/4, // voffset
        GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/2, // rsrc
        GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/0, // soffset
        GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/6, // offset
        GIR_CustomOperandRenderer, /*InsnID*/0, /*OldInsnID*/0, /*OpIdx*/7, /*OperandRenderer*/GIMT_Encode2(GICR_renderExtractCpolSetGLC), // auxiliary
        GIR_MergeMemOperands, /*InsnID*/0, /*NumInsns*/1, /*MergeInsnID's*/0,
        GIR_ConstrainSelectedInstOperands, /*InsnID*/0,
        GIR_EraseFromParent, /*InsnID*/0,
        // GIR_Coverage, 5131,
        GIR_Done,
      // Label 5931: @433399
      GIM_Try, /*On fail goto*//*Label 5932*/ GIMT_Encode4(433469), // Rule ID 5134 //
        GIM_CheckFeatures, GIMT_Encode2(GIFBS_isGFX12Plus),
        GIM_CheckHasNoUse, /*MI*/0,
        GIM_CheckConstantInt8, /*MI*/0, /*Op*/4, 0,
        // MIs[0] offset
        GIM_CheckIsImm, /*MI*/0, /*Op*/6,
        // MIs[0] auxiliary
        GIM_CheckIsImm, /*MI*/0, /*Op*/7,
        // MIs[0] Operand 8
        GIM_CheckIsImm, /*MI*/0, /*Op*/8,
        GIM_CheckComplexPattern, /*MI*/0, /*Op*/5, /*Renderer*/GIMT_Encode2(0), GIMT_Encode2(GICP_gi_buf_soffset),
        // (SIbuffer_atomic_fadd_bf16:{ *:[v2bf16] } v2bf16:{ *:[v2bf16] }:$vdata_in, v4i32:{ *:[v4i32] }:$rsrc, i32:{ *:[i32] }:$vindex, 0:{ *:[i32] }, (BUFSOffset:{ *:[i32] } i32:{ *:[i32] }:$soffset), (timm:{ *:[i32] }):$offset, (timm:{ *:[i32] }):$auxiliary, (timm:{ *:[i1] }))<<P:Predicate_SIbuffer_atomic_fadd_bf16_noret>>  =>  (BUFFER_ATOMIC_PK_ADD_BF16_VBUFFER_IDXEN anonymous_15037:{ *:[v2bf16] }:$vdata_in, VGPR_32:{ *:[i32] }:$vindex, SReg_128:{ *:[v4i32] }:$rsrc, SCSrc_b32:{ *:[i32] }:$soffset, (timm:{ *:[i32] }):$offset, (extract_cpol:{ *:[i32] } ?:{ *:[i32] }:$auxiliary))
        GIR_BuildMI, /*InsnID*/0, /*Opcode*/GIMT_Encode2(AMDGPU::BUFFER_ATOMIC_PK_ADD_BF16_VBUFFER_IDXEN),
        GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/1, // vdata_in
        GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/3, // vindex
        GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/2, // rsrc
        GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/0, // soffset
        GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/6, // offset
        GIR_CustomOperandRenderer, /*InsnID*/0, /*OldInsnID*/0, /*OpIdx*/7, /*OperandRenderer*/GIMT_Encode2(GICR_renderExtractCPol), // auxiliary
        GIR_MergeMemOperands, /*InsnID*/0, /*NumInsns*/1, /*MergeInsnID's*/0,
        GIR_ConstrainSelectedInstOperands, /*InsnID*/0,
        GIR_EraseFromParent, /*InsnID*/0,
        // GIR_Coverage, 5134,
        GIR_Done,
      // Label 5932: @433469
      GIM_Try, /*On fail goto*//*Label 5933*/ GIMT_Encode4(433546), // Rule ID 5130 //
        GIM_CheckFeatures, GIMT_Encode2(GIFBS_isGFX12Plus),
        GIM_CheckRegBankForClass, /*MI*/0, /*Op*/0, /*RC*/GIMT_Encode2(AMDGPU::AV_32RegClassID),
        GIM_CheckConstantInt8, /*MI*/0, /*Op*/4, 0,
        // MIs[0] offset
        GIM_CheckIsImm, /*MI*/0, /*Op*/6,
        // MIs[0] auxiliary
        GIM_CheckIsImm, /*MI*/0, /*Op*/7,
        // MIs[0] Operand 8
        GIM_CheckIsImm, /*MI*/0, /*Op*/8,
        GIM_CheckComplexPattern, /*MI*/0, /*Op*/5, /*Renderer*/GIMT_Encode2(0), GIMT_Encode2(GICP_gi_buf_soffset),
        // (SIbuffer_atomic_fadd_bf16:{ *:[v2bf16] } v2bf16:{ *:[v2bf16] }:$vdata_in, v4i32:{ *:[v4i32] }:$rsrc, i32:{ *:[i32] }:$vindex, 0:{ *:[i32] }, (BUFSOffset:{ *:[i32] } i32:{ *:[i32] }:$soffset), (timm:{ *:[i32] }):$offset, (timm:{ *:[i32] }):$auxiliary, (timm:{ *:[i1] }))  =>  (BUFFER_ATOMIC_PK_ADD_BF16_VBUFFER_IDXEN_RTN:{ *:[v2bf16] } anonymous_15037:{ *:[v2bf16] }:$vdata_in, VGPR_32:{ *:[i32] }:$vindex, SReg_128:{ *:[v4i32] }:$rsrc, SCSrc_b32:{ *:[i32] }:$soffset, (timm:{ *:[i32] }):$offset, (extract_cpol_set_glc:{ *:[i32] } ?:{ *:[i32] }:$auxiliary))
        GIR_BuildMI, /*InsnID*/0, /*Opcode*/GIMT_Encode2(AMDGPU::BUFFER_ATOMIC_PK_ADD_BF16_VBUFFER_IDXEN_RTN),
        GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/0, // DstI[vdata]
        GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/1, // vdata_in
        GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/3, // vindex
        GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/2, // rsrc
        GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/0, // soffset
        GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/6, // offset
        GIR_CustomOperandRenderer, /*InsnID*/0, /*OldInsnID*/0, /*OpIdx*/7, /*OperandRenderer*/GIMT_Encode2(GICR_renderExtractCpolSetGLC), // auxiliary
        GIR_MergeMemOperands, /*InsnID*/0, /*NumInsns*/1, /*MergeInsnID's*/0,
        GIR_ConstrainSelectedInstOperands, /*InsnID*/0,
        GIR_EraseFromParent, /*InsnID*/0,
        // GIR_Coverage, 5130,
        GIR_Done,
      // Label 5933: @433546
      GIM_Try, /*On fail goto*//*Label 5934*/ GIMT_Encode4(433652), // Rule ID 5136 //
        GIM_CheckFeatures, GIMT_Encode2(GIFBS_isGFX12Plus),
        GIM_CheckHasNoUse, /*MI*/0,
        // MIs[0] offset
        GIM_CheckIsImm, /*MI*/0, /*Op*/6,
        // MIs[0] auxiliary
        GIM_CheckIsImm, /*MI*/0, /*Op*/7,
        // MIs[0] Operand 8
        GIM_CheckIsImm, /*MI*/0, /*Op*/8,
        GIM_CheckComplexPattern, /*MI*/0, /*Op*/5, /*Renderer*/GIMT_Encode2(0), GIMT_Encode2(GICP_gi_buf_soffset),
        // (SIbuffer_atomic_fadd_bf16:{ *:[v2bf16] } v2bf16:{ *:[v2bf16] }:$vdata_in, v4i32:{ *:[v4i32] }:$rsrc, i32:{ *:[i32] }:$vindex, i32:{ *:[i32] }:$voffset, (BUFSOffset:{ *:[i32] } i32:{ *:[i32] }:$soffset), (timm:{ *:[i32] }):$offset, (timm:{ *:[i32] }):$auxiliary, (timm:{ *:[i1] }))<<P:Predicate_SIbuffer_atomic_fadd_bf16_noret>>  =>  (BUFFER_ATOMIC_PK_ADD_BF16_VBUFFER_BOTHEN anonymous_15037:{ *:[v2bf16] }:$vdata_in, (REG_SEQUENCE:{ *:[i64] } VReg_64:{ *:[i32] }, VGPR_32:{ *:[i32] }:$vindex, sub0:{ *:[i32] }, VGPR_32:{ *:[i32] }:$voffset, sub1:{ *:[i32] }), SReg_128:{ *:[v4i32] }:$rsrc, SCSrc_b32:{ *:[i32] }:$soffset, (timm:{ *:[i32] }):$offset, (extract_cpol:{ *:[i32] } ?:{ *:[i32] }:$auxiliary))
        GIR_MakeTempReg, /*TempRegID*/0, /*TypeID*/GILLT_s64,
        GIR_BuildMI, /*InsnID*/1, /*Opcode*/GIMT_Encode2(TargetOpcode::REG_SEQUENCE),
        GIR_AddTempRegister, /*InsnID*/1, /*TempRegID*/0, /*TempRegFlags*/GIMT_Encode2(RegState::Define),
        GIR_Copy, /*NewInsnID*/1, /*OldInsnID*/0, /*OpIdx*/3, // vindex
        GIR_AddImm8, /*InsnID*/1, /*SubRegIndex*/3,
        GIR_Copy, /*NewInsnID*/1, /*OldInsnID*/0, /*OpIdx*/4, // voffset
        GIR_AddImm8, /*InsnID*/1, /*SubRegIndex*/11,
        GIR_ConstrainOperandRC, /*InsnID*/1, /*Op*/0, GIMT_Encode2(AMDGPU::VReg_64RegClassID),
        GIR_ConstrainOperandRC, /*InsnID*/1, /*Op*/1, GIMT_Encode2(AMDGPU::VGPR_32RegClassID),
        GIR_ConstrainOperandRC, /*InsnID*/1, /*Op*/3, GIMT_Encode2(AMDGPU::VGPR_32RegClassID),
        GIR_BuildMI, /*InsnID*/0, /*Opcode*/GIMT_Encode2(AMDGPU::BUFFER_ATOMIC_PK_ADD_BF16_VBUFFER_BOTHEN),
        GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/1, // vdata_in
        GIR_AddSimpleTempRegister, /*InsnID*/0, /*TempRegID*/0,
        GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/2, // rsrc
        GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/0, // soffset
        GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/6, // offset
        GIR_CustomOperandRenderer, /*InsnID*/0, /*OldInsnID*/0, /*OpIdx*/7, /*OperandRenderer*/GIMT_Encode2(GICR_renderExtractCPol), // auxiliary
        GIR_MergeMemOperands, /*InsnID*/0, /*NumInsns*/1, /*MergeInsnID's*/0,
        GIR_ConstrainSelectedInstOperands, /*InsnID*/0,
        GIR_EraseFromParent, /*InsnID*/0,
        // GIR_Coverage, 5136,
        GIR_Done,
      // Label 5934: @433652
      GIM_Try, /*On fail goto*//*Label 5935*/ GIMT_Encode4(433765), // Rule ID 5132 //
        GIM_CheckFeatures, GIMT_Encode2(GIFBS_isGFX12Plus),
        GIM_CheckRegBankForClass, /*MI*/0, /*Op*/0, /*RC*/GIMT_Encode2(AMDGPU::AV_32RegClassID),
        // MIs[0] offset
        GIM_CheckIsImm, /*MI*/0, /*Op*/6,
        // MIs[0] auxiliary
        GIM_CheckIsImm, /*MI*/0, /*Op*/7,
        // MIs[0] Operand 8
        GIM_CheckIsImm, /*MI*/0, /*Op*/8,
        GIM_CheckComplexPattern, /*MI*/0, /*Op*/5, /*Renderer*/GIMT_Encode2(0), GIMT_Encode2(GICP_gi_buf_soffset),
        // (SIbuffer_atomic_fadd_bf16:{ *:[v2bf16] } v2bf16:{ *:[v2bf16] }:$vdata_in, v4i32:{ *:[v4i32] }:$rsrc, i32:{ *:[i32] }:$vindex, i32:{ *:[i32] }:$voffset, (BUFSOffset:{ *:[i32] } i32:{ *:[i32] }:$soffset), (timm:{ *:[i32] }):$offset, (timm:{ *:[i32] }):$auxiliary, (timm:{ *:[i1] }))  =>  (BUFFER_ATOMIC_PK_ADD_BF16_VBUFFER_BOTHEN_RTN:{ *:[v2bf16] } anonymous_15037:{ *:[v2bf16] }:$vdata_in, (REG_SEQUENCE:{ *:[i64] } VReg_64:{ *:[i32] }, VGPR_32:{ *:[i32] }:$vindex, sub0:{ *:[i32] }, VGPR_32:{ *:[i32] }:$voffset, sub1:{ *:[i32] }), SReg_128:{ *:[v4i32] }:$rsrc, SCSrc_b32:{ *:[i32] }:$soffset, (timm:{ *:[i32] }):$offset, (extract_cpol_set_glc:{ *:[i32] } ?:{ *:[i32] }:$auxiliary))
        GIR_MakeTempReg, /*TempRegID*/0, /*TypeID*/GILLT_s64,
        GIR_BuildMI, /*InsnID*/1, /*Opcode*/GIMT_Encode2(TargetOpcode::REG_SEQUENCE),
        GIR_AddTempRegister, /*InsnID*/1, /*TempRegID*/0, /*TempRegFlags*/GIMT_Encode2(RegState::Define),
        GIR_Copy, /*NewInsnID*/1, /*OldInsnID*/0, /*OpIdx*/3, // vindex
        GIR_AddImm8, /*InsnID*/1, /*SubRegIndex*/3,
        GIR_Copy, /*NewInsnID*/1, /*OldInsnID*/0, /*OpIdx*/4, // voffset
        GIR_AddImm8, /*InsnID*/1, /*SubRegIndex*/11,
        GIR_ConstrainOperandRC, /*InsnID*/1, /*Op*/0, GIMT_Encode2(AMDGPU::VReg_64RegClassID),
        GIR_ConstrainOperandRC, /*InsnID*/1, /*Op*/1, GIMT_Encode2(AMDGPU::VGPR_32RegClassID),
        GIR_ConstrainOperandRC, /*InsnID*/1, /*Op*/3, GIMT_Encode2(AMDGPU::VGPR_32RegClassID),
        GIR_BuildMI, /*InsnID*/0, /*Opcode*/GIMT_Encode2(AMDGPU::BUFFER_ATOMIC_PK_ADD_BF16_VBUFFER_BOTHEN_RTN),
        GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/0, // DstI[vdata]
        GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/1, // vdata_in
        GIR_AddSimpleTempRegister, /*InsnID*/0, /*TempRegID*/0,
        GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/2, // rsrc
        GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/0, // soffset
        GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/6, // offset
        GIR_CustomOperandRenderer, /*InsnID*/0, /*OldInsnID*/0, /*OpIdx*/7, /*OperandRenderer*/GIMT_Encode2(GICR_renderExtractCpolSetGLC), // auxiliary
        GIR_MergeMemOperands, /*InsnID*/0, /*NumInsns*/1, /*MergeInsnID's*/0,
        GIR_ConstrainSelectedInstOperands, /*InsnID*/0,
        GIR_EraseFromParent, /*InsnID*/0,
        // GIR_Coverage, 5132,
        GIR_Done,
      // Label 5935: @433765
      GIM_Reject,
    // Label 5927: @433766
    GIM_Reject,
    // Label 113: @433767
    GIM_SwitchType, /*MI*/0, /*Op*/0, /*[*/GIMT_Encode2(9), GIMT_Encode2(11), /*)*//*default:*//*Label 5938*/ GIMT_Encode4(437992),
    /*GILLT_s32*//*Label 5936*/ GIMT_Encode4(433786),
    /*GILLT_s64*//*Label 5937*/ GIMT_Encode4(435197),
    // Label 5936: @433786
    GIM_Try, /*On fail goto*//*Label 5939*/ GIMT_Encode4(435196),
      GIM_CheckType, /*MI*/0, /*Op*/1, /*Type*/GILLT_s32,
      GIM_CheckType, /*MI*/0, /*Op*/2, /*Type*/GILLT_v4s32,
      GIM_CheckType, /*MI*/0, /*Op*/3, /*Type*/GILLT_s32,
      GIM_CheckType, /*MI*/0, /*Op*/4, /*Type*/GILLT_s32,
      GIM_CheckType, /*MI*/0, /*Op*/5, /*Type*/GILLT_s32,
      GIM_Try, /*On fail goto*//*Label 5940*/ GIMT_Encode4(433889), // Rule ID 5165 //
        GIM_CheckFeatures, GIMT_Encode2(GIFBS_isGFX6GFX7GFX10Plus),
        GIM_CheckHasNoUse, /*MI*/0,
        GIM_CheckConstantInt8, /*MI*/0, /*Op*/3, 0,
        GIM_CheckConstantInt8, /*MI*/0, /*Op*/4, 0,
        // MIs[0] offset
        GIM_CheckIsImm, /*MI*/0, /*Op*/6,
        // MIs[0] auxiliary
        GIM_CheckIsImm, /*MI*/0, /*Op*/7,
        // MIs[0] Operand 8
        GIM_CheckLiteralInt, /*MI*/0, /*Op*/8, GIMT_Encode8(0),
        GIM_CheckComplexPattern, /*MI*/0, /*Op*/5, /*Renderer*/GIMT_Encode2(0), GIMT_Encode2(GICP_gi_buf_soffset),
        // (SIbuffer_atomic_fmax:{ *:[f32] } f32:{ *:[f32] }:$vdata_in, v4i32:{ *:[v4i32] }:$rsrc, 0:{ *:[i32] }, 0:{ *:[i32] }, (BUFSOffset:{ *:[i32] } i32:{ *:[i32] }:$soffset), (timm:{ *:[i32] }):$offset, (timm:{ *:[i32] }):$auxiliary, 0:{ *:[i1] })<<P:Predicate_SIbuffer_atomic_fmax_noret>>  =>  (BUFFER_ATOMIC_FMAX_OFFSET anonymous_15037:{ *:[f32] }:$vdata_in, SReg_128:{ *:[v4i32] }:$rsrc, SCSrc_b32:{ *:[i32] }:$soffset, (timm:{ *:[i32] }):$offset, (extract_cpol:{ *:[i32] } ?:{ *:[i32] }:$auxiliary))
        GIR_BuildMI, /*InsnID*/0, /*Opcode*/GIMT_Encode2(AMDGPU::BUFFER_ATOMIC_FMAX_OFFSET),
        GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/1, // vdata_in
        GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/2, // rsrc
        GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/0, // soffset
        GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/6, // offset
        GIR_CustomOperandRenderer, /*InsnID*/0, /*OldInsnID*/0, /*OpIdx*/7, /*OperandRenderer*/GIMT_Encode2(GICR_renderExtractCPol), // auxiliary
        GIR_MergeMemOperands, /*InsnID*/0, /*NumInsns*/1, /*MergeInsnID's*/0,
        GIR_ConstrainSelectedInstOperands, /*InsnID*/0,
        GIR_EraseFromParent, /*InsnID*/0,
        // GIR_Coverage, 5165,
        GIR_Done,
      // Label 5940: @433889
      GIM_Try, /*On fail goto*//*Label 5941*/ GIMT_Encode4(433967), // Rule ID 5173 //
        GIM_CheckFeatures, GIMT_Encode2(GIFBS_isGFX6GFX7GFX10Plus),
        GIM_CheckHasNoUse, /*MI*/0,
        GIM_CheckConstantInt8, /*MI*/0, /*Op*/3, 0,
        GIM_CheckConstantInt8, /*MI*/0, /*Op*/4, 0,
        // MIs[0] offset
        GIM_CheckIsImm, /*MI*/0, /*Op*/6,
        // MIs[0] auxiliary
        GIM_CheckIsImm, /*MI*/0, /*Op*/7,
        // MIs[0] Operand 8
        GIM_CheckLiteralInt, /*MI*/0, /*Op*/8, GIMT_Encode8(0),
        GIM_CheckComplexPattern, /*MI*/0, /*Op*/5, /*Renderer*/GIMT_Encode2(0), GIMT_Encode2(GICP_gi_buf_soffset),
        // (SIbuffer_atomic_fmax:{ *:[f32] } f32:{ *:[f32] }:$vdata_in, v4i32:{ *:[v4i32] }:$rsrc, 0:{ *:[i32] }, 0:{ *:[i32] }, (BUFSOffset:{ *:[i32] } i32:{ *:[i32] }:$soffset), (timm:{ *:[i32] }):$offset, (timm:{ *:[i32] }):$auxiliary, 0:{ *:[i1] })<<P:Predicate_SIbuffer_atomic_fmax_noret>>  =>  (BUFFER_ATOMIC_FMAX_VBUFFER_OFFSET anonymous_15037:{ *:[f32] }:$vdata_in, SReg_128:{ *:[v4i32] }:$rsrc, SCSrc_b32:{ *:[i32] }:$soffset, (timm:{ *:[i32] }):$offset, (extract_cpol:{ *:[i32] } ?:{ *:[i32] }:$auxiliary))
        GIR_BuildMI, /*InsnID*/0, /*Opcode*/GIMT_Encode2(AMDGPU::BUFFER_ATOMIC_FMAX_VBUFFER_OFFSET),
        GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/1, // vdata_in
        GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/2, // rsrc
        GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/0, // soffset
        GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/6, // offset
        GIR_CustomOperandRenderer, /*InsnID*/0, /*OldInsnID*/0, /*OpIdx*/7, /*OperandRenderer*/GIMT_Encode2(GICR_renderExtractCPol), // auxiliary
        GIR_MergeMemOperands, /*InsnID*/0, /*NumInsns*/1, /*MergeInsnID's*/0,
        GIR_ConstrainSelectedInstOperands, /*InsnID*/0,
        GIR_EraseFromParent, /*InsnID*/0,
        // GIR_Coverage, 5173,
        GIR_Done,
      // Label 5941: @433967
      GIM_Try, /*On fail goto*//*Label 5942*/ GIMT_Encode4(434052), // Rule ID 5161 //
        GIM_CheckFeatures, GIMT_Encode2(GIFBS_isGFX6GFX7GFX10Plus),
        GIM_CheckRegBankForClass, /*MI*/0, /*Op*/0, /*RC*/GIMT_Encode2(AMDGPU::AV_32RegClassID),
        GIM_CheckConstantInt8, /*MI*/0, /*Op*/3, 0,
        GIM_CheckConstantInt8, /*MI*/0, /*Op*/4, 0,
        // MIs[0] offset
        GIM_CheckIsImm, /*MI*/0, /*Op*/6,
        // MIs[0] auxiliary
        GIM_CheckIsImm, /*MI*/0, /*Op*/7,
        // MIs[0] Operand 8
        GIM_CheckLiteralInt, /*MI*/0, /*Op*/8, GIMT_Encode8(0),
        GIM_CheckComplexPattern, /*MI*/0, /*Op*/5, /*Renderer*/GIMT_Encode2(0), GIMT_Encode2(GICP_gi_buf_soffset),
        // (SIbuffer_atomic_fmax:{ *:[f32] } f32:{ *:[f32] }:$vdata_in, v4i32:{ *:[v4i32] }:$rsrc, 0:{ *:[i32] }, 0:{ *:[i32] }, (BUFSOffset:{ *:[i32] } i32:{ *:[i32] }:$soffset), (timm:{ *:[i32] }):$offset, (timm:{ *:[i32] }):$auxiliary, 0:{ *:[i1] })  =>  (BUFFER_ATOMIC_FMAX_OFFSET_RTN:{ *:[f32] } anonymous_15037:{ *:[f32] }:$vdata_in, SReg_128:{ *:[v4i32] }:$rsrc, SCSrc_b32:{ *:[i32] }:$soffset, (timm:{ *:[i32] }):$offset, (extract_cpol_set_glc:{ *:[i32] } ?:{ *:[i32] }:$auxiliary))
        GIR_BuildMI, /*InsnID*/0, /*Opcode*/GIMT_Encode2(AMDGPU::BUFFER_ATOMIC_FMAX_OFFSET_RTN),
        GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/0, // DstI[vdata]
        GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/1, // vdata_in
        GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/2, // rsrc
        GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/0, // soffset
        GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/6, // offset
        GIR_CustomOperandRenderer, /*InsnID*/0, /*OldInsnID*/0, /*OpIdx*/7, /*OperandRenderer*/GIMT_Encode2(GICR_renderExtractCpolSetGLC), // auxiliary
        GIR_MergeMemOperands, /*InsnID*/0, /*NumInsns*/1, /*MergeInsnID's*/0,
        GIR_ConstrainSelectedInstOperands, /*InsnID*/0,
        GIR_EraseFromParent, /*InsnID*/0,
        // GIR_Coverage, 5161,
        GIR_Done,
      // Label 5942: @434052
      GIM_Try, /*On fail goto*//*Label 5943*/ GIMT_Encode4(434137), // Rule ID 5169 //
        GIM_CheckFeatures, GIMT_Encode2(GIFBS_isGFX6GFX7GFX10Plus),
        GIM_CheckRegBankForClass, /*MI*/0, /*Op*/0, /*RC*/GIMT_Encode2(AMDGPU::AV_32RegClassID),
        GIM_CheckConstantInt8, /*MI*/0, /*Op*/3, 0,
        GIM_CheckConstantInt8, /*MI*/0, /*Op*/4, 0,
        // MIs[0] offset
        GIM_CheckIsImm, /*MI*/0, /*Op*/6,
        // MIs[0] auxiliary
        GIM_CheckIsImm, /*MI*/0, /*Op*/7,
        // MIs[0] Operand 8
        GIM_CheckLiteralInt, /*MI*/0, /*Op*/8, GIMT_Encode8(0),
        GIM_CheckComplexPattern, /*MI*/0, /*Op*/5, /*Renderer*/GIMT_Encode2(0), GIMT_Encode2(GICP_gi_buf_soffset),
        // (SIbuffer_atomic_fmax:{ *:[f32] } f32:{ *:[f32] }:$vdata_in, v4i32:{ *:[v4i32] }:$rsrc, 0:{ *:[i32] }, 0:{ *:[i32] }, (BUFSOffset:{ *:[i32] } i32:{ *:[i32] }:$soffset), (timm:{ *:[i32] }):$offset, (timm:{ *:[i32] }):$auxiliary, 0:{ *:[i1] })  =>  (BUFFER_ATOMIC_FMAX_VBUFFER_OFFSET_RTN:{ *:[f32] } anonymous_15037:{ *:[f32] }:$vdata_in, SReg_128:{ *:[v4i32] }:$rsrc, SCSrc_b32:{ *:[i32] }:$soffset, (timm:{ *:[i32] }):$offset, (extract_cpol_set_glc:{ *:[i32] } ?:{ *:[i32] }:$auxiliary))
        GIR_BuildMI, /*InsnID*/0, /*Opcode*/GIMT_Encode2(AMDGPU::BUFFER_ATOMIC_FMAX_VBUFFER_OFFSET_RTN),
        GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/0, // DstI[vdata]
        GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/1, // vdata_in
        GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/2, // rsrc
        GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/0, // soffset
        GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/6, // offset
        GIR_CustomOperandRenderer, /*InsnID*/0, /*OldInsnID*/0, /*OpIdx*/7, /*OperandRenderer*/GIMT_Encode2(GICR_renderExtractCpolSetGLC), // auxiliary
        GIR_MergeMemOperands, /*InsnID*/0, /*NumInsns*/1, /*MergeInsnID's*/0,
        GIR_ConstrainSelectedInstOperands, /*InsnID*/0,
        GIR_EraseFromParent, /*InsnID*/0,
        // GIR_Coverage, 5169,
        GIR_Done,
      // Label 5943: @434137
      GIM_Try, /*On fail goto*//*Label 5944*/ GIMT_Encode4(434215), // Rule ID 5167 //
        GIM_CheckFeatures, GIMT_Encode2(GIFBS_isGFX6GFX7GFX10Plus),
        GIM_CheckHasNoUse, /*MI*/0,
        GIM_CheckConstantInt8, /*MI*/0, /*Op*/3, 0,
        // MIs[0] offset
        GIM_CheckIsImm, /*MI*/0, /*Op*/6,
        // MIs[0] auxiliary
        GIM_CheckIsImm, /*MI*/0, /*Op*/7,
        // MIs[0] Operand 8
        GIM_CheckLiteralInt, /*MI*/0, /*Op*/8, GIMT_Encode8(0),
        GIM_CheckComplexPattern, /*MI*/0, /*Op*/5, /*Renderer*/GIMT_Encode2(0), GIMT_Encode2(GICP_gi_buf_soffset),
        // (SIbuffer_atomic_fmax:{ *:[f32] } f32:{ *:[f32] }:$vdata_in, v4i32:{ *:[v4i32] }:$rsrc, 0:{ *:[i32] }, i32:{ *:[i32] }:$voffset, (BUFSOffset:{ *:[i32] } i32:{ *:[i32] }:$soffset), (timm:{ *:[i32] }):$offset, (timm:{ *:[i32] }):$auxiliary, 0:{ *:[i1] })<<P:Predicate_SIbuffer_atomic_fmax_noret>>  =>  (BUFFER_ATOMIC_FMAX_OFFEN anonymous_15037:{ *:[f32] }:$vdata_in, VGPR_32:{ *:[i32] }:$voffset, SReg_128:{ *:[v4i32] }:$rsrc, SCSrc_b32:{ *:[i32] }:$soffset, (timm:{ *:[i32] }):$offset, (extract_cpol:{ *:[i32] } ?:{ *:[i32] }:$auxiliary))
        GIR_BuildMI, /*InsnID*/0, /*Opcode*/GIMT_Encode2(AMDGPU::BUFFER_ATOMIC_FMAX_OFFEN),
        GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/1, // vdata_in
        GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/4, // voffset
        GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/2, // rsrc
        GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/0, // soffset
        GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/6, // offset
        GIR_CustomOperandRenderer, /*InsnID*/0, /*OldInsnID*/0, /*OpIdx*/7, /*OperandRenderer*/GIMT_Encode2(GICR_renderExtractCPol), // auxiliary
        GIR_MergeMemOperands, /*InsnID*/0, /*NumInsns*/1, /*MergeInsnID's*/0,
        GIR_ConstrainSelectedInstOperands, /*InsnID*/0,
        GIR_EraseFromParent, /*InsnID*/0,
        // GIR_Coverage, 5167,
        GIR_Done,
      // Label 5944: @434215
      GIM_Try, /*On fail goto*//*Label 5945*/ GIMT_Encode4(434293), // Rule ID 5175 //
        GIM_CheckFeatures, GIMT_Encode2(GIFBS_isGFX6GFX7GFX10Plus),
        GIM_CheckHasNoUse, /*MI*/0,
        GIM_CheckConstantInt8, /*MI*/0, /*Op*/3, 0,
        // MIs[0] offset
        GIM_CheckIsImm, /*MI*/0, /*Op*/6,
        // MIs[0] auxiliary
        GIM_CheckIsImm, /*MI*/0, /*Op*/7,
        // MIs[0] Operand 8
        GIM_CheckLiteralInt, /*MI*/0, /*Op*/8, GIMT_Encode8(0),
        GIM_CheckComplexPattern, /*MI*/0, /*Op*/5, /*Renderer*/GIMT_Encode2(0), GIMT_Encode2(GICP_gi_buf_soffset),
        // (SIbuffer_atomic_fmax:{ *:[f32] } f32:{ *:[f32] }:$vdata_in, v4i32:{ *:[v4i32] }:$rsrc, 0:{ *:[i32] }, i32:{ *:[i32] }:$voffset, (BUFSOffset:{ *:[i32] } i32:{ *:[i32] }:$soffset), (timm:{ *:[i32] }):$offset, (timm:{ *:[i32] }):$auxiliary, 0:{ *:[i1] })<<P:Predicate_SIbuffer_atomic_fmax_noret>>  =>  (BUFFER_ATOMIC_FMAX_VBUFFER_OFFEN anonymous_15037:{ *:[f32] }:$vdata_in, VGPR_32:{ *:[i32] }:$voffset, SReg_128:{ *:[v4i32] }:$rsrc, SCSrc_b32:{ *:[i32] }:$soffset, (timm:{ *:[i32] }):$offset, (extract_cpol:{ *:[i32] } ?:{ *:[i32] }:$auxiliary))
        GIR_BuildMI, /*InsnID*/0, /*Opcode*/GIMT_Encode2(AMDGPU::BUFFER_ATOMIC_FMAX_VBUFFER_OFFEN),
        GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/1, // vdata_in
        GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/4, // voffset
        GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/2, // rsrc
        GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/0, // soffset
        GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/6, // offset
        GIR_CustomOperandRenderer, /*InsnID*/0, /*OldInsnID*/0, /*OpIdx*/7, /*OperandRenderer*/GIMT_Encode2(GICR_renderExtractCPol), // auxiliary
        GIR_MergeMemOperands, /*InsnID*/0, /*NumInsns*/1, /*MergeInsnID's*/0,
        GIR_ConstrainSelectedInstOperands, /*InsnID*/0,
        GIR_EraseFromParent, /*InsnID*/0,
        // GIR_Coverage, 5175,
        GIR_Done,
      // Label 5945: @434293
      GIM_Try, /*On fail goto*//*Label 5946*/ GIMT_Encode4(434378), // Rule ID 5163 //
        GIM_CheckFeatures, GIMT_Encode2(GIFBS_isGFX6GFX7GFX10Plus),
        GIM_CheckRegBankForClass, /*MI*/0, /*Op*/0, /*RC*/GIMT_Encode2(AMDGPU::AV_32RegClassID),
        GIM_CheckConstantInt8, /*MI*/0, /*Op*/3, 0,
        // MIs[0] offset
        GIM_CheckIsImm, /*MI*/0, /*Op*/6,
        // MIs[0] auxiliary
        GIM_CheckIsImm, /*MI*/0, /*Op*/7,
        // MIs[0] Operand 8
        GIM_CheckLiteralInt, /*MI*/0, /*Op*/8, GIMT_Encode8(0),
        GIM_CheckComplexPattern, /*MI*/0, /*Op*/5, /*Renderer*/GIMT_Encode2(0), GIMT_Encode2(GICP_gi_buf_soffset),
        // (SIbuffer_atomic_fmax:{ *:[f32] } f32:{ *:[f32] }:$vdata_in, v4i32:{ *:[v4i32] }:$rsrc, 0:{ *:[i32] }, i32:{ *:[i32] }:$voffset, (BUFSOffset:{ *:[i32] } i32:{ *:[i32] }:$soffset), (timm:{ *:[i32] }):$offset, (timm:{ *:[i32] }):$auxiliary, 0:{ *:[i1] })  =>  (BUFFER_ATOMIC_FMAX_OFFEN_RTN:{ *:[f32] } anonymous_15037:{ *:[f32] }:$vdata_in, VGPR_32:{ *:[i32] }:$voffset, SReg_128:{ *:[v4i32] }:$rsrc, SCSrc_b32:{ *:[i32] }:$soffset, (timm:{ *:[i32] }):$offset, (extract_cpol_set_glc:{ *:[i32] } ?:{ *:[i32] }:$auxiliary))
        GIR_BuildMI, /*InsnID*/0, /*Opcode*/GIMT_Encode2(AMDGPU::BUFFER_ATOMIC_FMAX_OFFEN_RTN),
        GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/0, // DstI[vdata]
        GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/1, // vdata_in
        GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/4, // voffset
        GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/2, // rsrc
        GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/0, // soffset
        GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/6, // offset
        GIR_CustomOperandRenderer, /*InsnID*/0, /*OldInsnID*/0, /*OpIdx*/7, /*OperandRenderer*/GIMT_Encode2(GICR_renderExtractCpolSetGLC), // auxiliary
        GIR_MergeMemOperands, /*InsnID*/0, /*NumInsns*/1, /*MergeInsnID's*/0,
        GIR_ConstrainSelectedInstOperands, /*InsnID*/0,
        GIR_EraseFromParent, /*InsnID*/0,
        // GIR_Coverage, 5163,
        GIR_Done,
      // Label 5946: @434378
      GIM_Try, /*On fail goto*//*Label 5947*/ GIMT_Encode4(434463), // Rule ID 5171 //
        GIM_CheckFeatures, GIMT_Encode2(GIFBS_isGFX6GFX7GFX10Plus),
        GIM_CheckRegBankForClass, /*MI*/0, /*Op*/0, /*RC*/GIMT_Encode2(AMDGPU::AV_32RegClassID),
        GIM_CheckConstantInt8, /*MI*/0, /*Op*/3, 0,
        // MIs[0] offset
        GIM_CheckIsImm, /*MI*/0, /*Op*/6,
        // MIs[0] auxiliary
        GIM_CheckIsImm, /*MI*/0, /*Op*/7,
        // MIs[0] Operand 8
        GIM_CheckLiteralInt, /*MI*/0, /*Op*/8, GIMT_Encode8(0),
        GIM_CheckComplexPattern, /*MI*/0, /*Op*/5, /*Renderer*/GIMT_Encode2(0), GIMT_Encode2(GICP_gi_buf_soffset),
        // (SIbuffer_atomic_fmax:{ *:[f32] } f32:{ *:[f32] }:$vdata_in, v4i32:{ *:[v4i32] }:$rsrc, 0:{ *:[i32] }, i32:{ *:[i32] }:$voffset, (BUFSOffset:{ *:[i32] } i32:{ *:[i32] }:$soffset), (timm:{ *:[i32] }):$offset, (timm:{ *:[i32] }):$auxiliary, 0:{ *:[i1] })  =>  (BUFFER_ATOMIC_FMAX_VBUFFER_OFFEN_RTN:{ *:[f32] } anonymous_15037:{ *:[f32] }:$vdata_in, VGPR_32:{ *:[i32] }:$voffset, SReg_128:{ *:[v4i32] }:$rsrc, SCSrc_b32:{ *:[i32] }:$soffset, (timm:{ *:[i32] }):$offset, (extract_cpol_set_glc:{ *:[i32] } ?:{ *:[i32] }:$auxiliary))
        GIR_BuildMI, /*InsnID*/0, /*Opcode*/GIMT_Encode2(AMDGPU::BUFFER_ATOMIC_FMAX_VBUFFER_OFFEN_RTN),
        GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/0, // DstI[vdata]
        GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/1, // vdata_in
        GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/4, // voffset
        GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/2, // rsrc
        GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/0, // soffset
        GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/6, // offset
        GIR_CustomOperandRenderer, /*InsnID*/0, /*OldInsnID*/0, /*OpIdx*/7, /*OperandRenderer*/GIMT_Encode2(GICR_renderExtractCpolSetGLC), // auxiliary
        GIR_MergeMemOperands, /*InsnID*/0, /*NumInsns*/1, /*MergeInsnID's*/0,
        GIR_ConstrainSelectedInstOperands, /*InsnID*/0,
        GIR_EraseFromParent, /*InsnID*/0,
        // GIR_Coverage, 5171,
        GIR_Done,
      // Label 5947: @434463
      GIM_Try, /*On fail goto*//*Label 5948*/ GIMT_Encode4(434533), // Rule ID 5166 //
        GIM_CheckFeatures, GIMT_Encode2(GIFBS_isGFX6GFX7GFX10Plus),
        GIM_CheckHasNoUse, /*MI*/0,
        GIM_CheckConstantInt8, /*MI*/0, /*Op*/4, 0,
        // MIs[0] offset
        GIM_CheckIsImm, /*MI*/0, /*Op*/6,
        // MIs[0] auxiliary
        GIM_CheckIsImm, /*MI*/0, /*Op*/7,
        // MIs[0] Operand 8
        GIM_CheckIsImm, /*MI*/0, /*Op*/8,
        GIM_CheckComplexPattern, /*MI*/0, /*Op*/5, /*Renderer*/GIMT_Encode2(0), GIMT_Encode2(GICP_gi_buf_soffset),
        // (SIbuffer_atomic_fmax:{ *:[f32] } f32:{ *:[f32] }:$vdata_in, v4i32:{ *:[v4i32] }:$rsrc, i32:{ *:[i32] }:$vindex, 0:{ *:[i32] }, (BUFSOffset:{ *:[i32] } i32:{ *:[i32] }:$soffset), (timm:{ *:[i32] }):$offset, (timm:{ *:[i32] }):$auxiliary, (timm:{ *:[i1] }))<<P:Predicate_SIbuffer_atomic_fmax_noret>>  =>  (BUFFER_ATOMIC_FMAX_IDXEN anonymous_15037:{ *:[f32] }:$vdata_in, VGPR_32:{ *:[i32] }:$vindex, SReg_128:{ *:[v4i32] }:$rsrc, SCSrc_b32:{ *:[i32] }:$soffset, (timm:{ *:[i32] }):$offset, (extract_cpol:{ *:[i32] } ?:{ *:[i32] }:$auxiliary))
        GIR_BuildMI, /*InsnID*/0, /*Opcode*/GIMT_Encode2(AMDGPU::BUFFER_ATOMIC_FMAX_IDXEN),
        GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/1, // vdata_in
        GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/3, // vindex
        GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/2, // rsrc
        GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/0, // soffset
        GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/6, // offset
        GIR_CustomOperandRenderer, /*InsnID*/0, /*OldInsnID*/0, /*OpIdx*/7, /*OperandRenderer*/GIMT_Encode2(GICR_renderExtractCPol), // auxiliary
        GIR_MergeMemOperands, /*InsnID*/0, /*NumInsns*/1, /*MergeInsnID's*/0,
        GIR_ConstrainSelectedInstOperands, /*InsnID*/0,
        GIR_EraseFromParent, /*InsnID*/0,
        // GIR_Coverage, 5166,
        GIR_Done,
      // Label 5948: @434533
      GIM_Try, /*On fail goto*//*Label 5949*/ GIMT_Encode4(434603), // Rule ID 5174 //
        GIM_CheckFeatures, GIMT_Encode2(GIFBS_isGFX6GFX7GFX10Plus),
        GIM_CheckHasNoUse, /*MI*/0,
        GIM_CheckConstantInt8, /*MI*/0, /*Op*/4, 0,
        // MIs[0] offset
        GIM_CheckIsImm, /*MI*/0, /*Op*/6,
        // MIs[0] auxiliary
        GIM_CheckIsImm, /*MI*/0, /*Op*/7,
        // MIs[0] Operand 8
        GIM_CheckIsImm, /*MI*/0, /*Op*/8,
        GIM_CheckComplexPattern, /*MI*/0, /*Op*/5, /*Renderer*/GIMT_Encode2(0), GIMT_Encode2(GICP_gi_buf_soffset),
        // (SIbuffer_atomic_fmax:{ *:[f32] } f32:{ *:[f32] }:$vdata_in, v4i32:{ *:[v4i32] }:$rsrc, i32:{ *:[i32] }:$vindex, 0:{ *:[i32] }, (BUFSOffset:{ *:[i32] } i32:{ *:[i32] }:$soffset), (timm:{ *:[i32] }):$offset, (timm:{ *:[i32] }):$auxiliary, (timm:{ *:[i1] }))<<P:Predicate_SIbuffer_atomic_fmax_noret>>  =>  (BUFFER_ATOMIC_FMAX_VBUFFER_IDXEN anonymous_15037:{ *:[f32] }:$vdata_in, VGPR_32:{ *:[i32] }:$vindex, SReg_128:{ *:[v4i32] }:$rsrc, SCSrc_b32:{ *:[i32] }:$soffset, (timm:{ *:[i32] }):$offset, (extract_cpol:{ *:[i32] } ?:{ *:[i32] }:$auxiliary))
        GIR_BuildMI, /*InsnID*/0, /*Opcode*/GIMT_Encode2(AMDGPU::BUFFER_ATOMIC_FMAX_VBUFFER_IDXEN),
        GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/1, // vdata_in
        GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/3, // vindex
        GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/2, // rsrc
        GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/0, // soffset
        GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/6, // offset
        GIR_CustomOperandRenderer, /*InsnID*/0, /*OldInsnID*/0, /*OpIdx*/7, /*OperandRenderer*/GIMT_Encode2(GICR_renderExtractCPol), // auxiliary
        GIR_MergeMemOperands, /*InsnID*/0, /*NumInsns*/1, /*MergeInsnID's*/0,
        GIR_ConstrainSelectedInstOperands, /*InsnID*/0,
        GIR_EraseFromParent, /*InsnID*/0,
        // GIR_Coverage, 5174,
        GIR_Done,
      // Label 5949: @434603
      GIM_Try, /*On fail goto*//*Label 5950*/ GIMT_Encode4(434680), // Rule ID 5162 //
        GIM_CheckFeatures, GIMT_Encode2(GIFBS_isGFX6GFX7GFX10Plus),
        GIM_CheckRegBankForClass, /*MI*/0, /*Op*/0, /*RC*/GIMT_Encode2(AMDGPU::AV_32RegClassID),
        GIM_CheckConstantInt8, /*MI*/0, /*Op*/4, 0,
        // MIs[0] offset
        GIM_CheckIsImm, /*MI*/0, /*Op*/6,
        // MIs[0] auxiliary
        GIM_CheckIsImm, /*MI*/0, /*Op*/7,
        // MIs[0] Operand 8
        GIM_CheckIsImm, /*MI*/0, /*Op*/8,
        GIM_CheckComplexPattern, /*MI*/0, /*Op*/5, /*Renderer*/GIMT_Encode2(0), GIMT_Encode2(GICP_gi_buf_soffset),
        // (SIbuffer_atomic_fmax:{ *:[f32] } f32:{ *:[f32] }:$vdata_in, v4i32:{ *:[v4i32] }:$rsrc, i32:{ *:[i32] }:$vindex, 0:{ *:[i32] }, (BUFSOffset:{ *:[i32] } i32:{ *:[i32] }:$soffset), (timm:{ *:[i32] }):$offset, (timm:{ *:[i32] }):$auxiliary, (timm:{ *:[i1] }))  =>  (BUFFER_ATOMIC_FMAX_IDXEN_RTN:{ *:[f32] } anonymous_15037:{ *:[f32] }:$vdata_in, VGPR_32:{ *:[i32] }:$vindex, SReg_128:{ *:[v4i32] }:$rsrc, SCSrc_b32:{ *:[i32] }:$soffset, (timm:{ *:[i32] }):$offset, (extract_cpol_set_glc:{ *:[i32] } ?:{ *:[i32] }:$auxiliary))
        GIR_BuildMI, /*InsnID*/0, /*Opcode*/GIMT_Encode2(AMDGPU::BUFFER_ATOMIC_FMAX_IDXEN_RTN),
        GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/0, // DstI[vdata]
        GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/1, // vdata_in
        GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/3, // vindex
        GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/2, // rsrc
        GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/0, // soffset
        GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/6, // offset
        GIR_CustomOperandRenderer, /*InsnID*/0, /*OldInsnID*/0, /*OpIdx*/7, /*OperandRenderer*/GIMT_Encode2(GICR_renderExtractCpolSetGLC), // auxiliary
        GIR_MergeMemOperands, /*InsnID*/0, /*NumInsns*/1, /*MergeInsnID's*/0,
        GIR_ConstrainSelectedInstOperands, /*InsnID*/0,
        GIR_EraseFromParent, /*InsnID*/0,
        // GIR_Coverage, 5162,
        GIR_Done,
      // Label 5950: @434680
      GIM_Try, /*On fail goto*//*Label 5951*/ GIMT_Encode4(434757), // Rule ID 5170 //
        GIM_CheckFeatures, GIMT_Encode2(GIFBS_isGFX6GFX7GFX10Plus),
        GIM_CheckRegBankForClass, /*MI*/0, /*Op*/0, /*RC*/GIMT_Encode2(AMDGPU::AV_32RegClassID),
        GIM_CheckConstantInt8, /*MI*/0, /*Op*/4, 0,
        // MIs[0] offset
        GIM_CheckIsImm, /*MI*/0, /*Op*/6,
        // MIs[0] auxiliary
        GIM_CheckIsImm, /*MI*/0, /*Op*/7,
        // MIs[0] Operand 8
        GIM_CheckIsImm, /*MI*/0, /*Op*/8,
        GIM_CheckComplexPattern, /*MI*/0, /*Op*/5, /*Renderer*/GIMT_Encode2(0), GIMT_Encode2(GICP_gi_buf_soffset),
        // (SIbuffer_atomic_fmax:{ *:[f32] } f32:{ *:[f32] }:$vdata_in, v4i32:{ *:[v4i32] }:$rsrc, i32:{ *:[i32] }:$vindex, 0:{ *:[i32] }, (BUFSOffset:{ *:[i32] } i32:{ *:[i32] }:$soffset), (timm:{ *:[i32] }):$offset, (timm:{ *:[i32] }):$auxiliary, (timm:{ *:[i1] }))  =>  (BUFFER_ATOMIC_FMAX_VBUFFER_IDXEN_RTN:{ *:[f32] } anonymous_15037:{ *:[f32] }:$vdata_in, VGPR_32:{ *:[i32] }:$vindex, SReg_128:{ *:[v4i32] }:$rsrc, SCSrc_b32:{ *:[i32] }:$soffset, (timm:{ *:[i32] }):$offset, (extract_cpol_set_glc:{ *:[i32] } ?:{ *:[i32] }:$auxiliary))
        GIR_BuildMI, /*InsnID*/0, /*Opcode*/GIMT_Encode2(AMDGPU::BUFFER_ATOMIC_FMAX_VBUFFER_IDXEN_RTN),
        GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/0, // DstI[vdata]
        GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/1, // vdata_in
        GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/3, // vindex
        GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/2, // rsrc
        GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/0, // soffset
        GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/6, // offset
        GIR_CustomOperandRenderer, /*InsnID*/0, /*OldInsnID*/0, /*OpIdx*/7, /*OperandRenderer*/GIMT_Encode2(GICR_renderExtractCpolSetGLC), // auxiliary
        GIR_MergeMemOperands, /*InsnID*/0, /*NumInsns*/1, /*MergeInsnID's*/0,
        GIR_ConstrainSelectedInstOperands, /*InsnID*/0,
        GIR_EraseFromParent, /*InsnID*/0,
        // GIR_Coverage, 5170,
        GIR_Done,
      // Label 5951: @434757
      GIM_Try, /*On fail goto*//*Label 5952*/ GIMT_Encode4(434863), // Rule ID 5168 //
        GIM_CheckFeatures, GIMT_Encode2(GIFBS_isGFX6GFX7GFX10Plus),
        GIM_CheckHasNoUse, /*MI*/0,
        // MIs[0] offset
        GIM_CheckIsImm, /*MI*/0, /*Op*/6,
        // MIs[0] auxiliary
        GIM_CheckIsImm, /*MI*/0, /*Op*/7,
        // MIs[0] Operand 8
        GIM_CheckIsImm, /*MI*/0, /*Op*/8,
        GIM_CheckComplexPattern, /*MI*/0, /*Op*/5, /*Renderer*/GIMT_Encode2(0), GIMT_Encode2(GICP_gi_buf_soffset),
        // (SIbuffer_atomic_fmax:{ *:[f32] } f32:{ *:[f32] }:$vdata_in, v4i32:{ *:[v4i32] }:$rsrc, i32:{ *:[i32] }:$vindex, i32:{ *:[i32] }:$voffset, (BUFSOffset:{ *:[i32] } i32:{ *:[i32] }:$soffset), (timm:{ *:[i32] }):$offset, (timm:{ *:[i32] }):$auxiliary, (timm:{ *:[i1] }))<<P:Predicate_SIbuffer_atomic_fmax_noret>>  =>  (BUFFER_ATOMIC_FMAX_BOTHEN anonymous_15037:{ *:[f32] }:$vdata_in, (REG_SEQUENCE:{ *:[i64] } VReg_64:{ *:[i32] }, VGPR_32:{ *:[i32] }:$vindex, sub0:{ *:[i32] }, VGPR_32:{ *:[i32] }:$voffset, sub1:{ *:[i32] }), SReg_128:{ *:[v4i32] }:$rsrc, SCSrc_b32:{ *:[i32] }:$soffset, (timm:{ *:[i32] }):$offset, (extract_cpol:{ *:[i32] } ?:{ *:[i32] }:$auxiliary))
        GIR_MakeTempReg, /*TempRegID*/0, /*TypeID*/GILLT_s64,
        GIR_BuildMI, /*InsnID*/1, /*Opcode*/GIMT_Encode2(TargetOpcode::REG_SEQUENCE),
        GIR_AddTempRegister, /*InsnID*/1, /*TempRegID*/0, /*TempRegFlags*/GIMT_Encode2(RegState::Define),
        GIR_Copy, /*NewInsnID*/1, /*OldInsnID*/0, /*OpIdx*/3, // vindex
        GIR_AddImm8, /*InsnID*/1, /*SubRegIndex*/3,
        GIR_Copy, /*NewInsnID*/1, /*OldInsnID*/0, /*OpIdx*/4, // voffset
        GIR_AddImm8, /*InsnID*/1, /*SubRegIndex*/11,
        GIR_ConstrainOperandRC, /*InsnID*/1, /*Op*/0, GIMT_Encode2(AMDGPU::VReg_64RegClassID),
        GIR_ConstrainOperandRC, /*InsnID*/1, /*Op*/1, GIMT_Encode2(AMDGPU::VGPR_32RegClassID),
        GIR_ConstrainOperandRC, /*InsnID*/1, /*Op*/3, GIMT_Encode2(AMDGPU::VGPR_32RegClassID),
        GIR_BuildMI, /*InsnID*/0, /*Opcode*/GIMT_Encode2(AMDGPU::BUFFER_ATOMIC_FMAX_BOTHEN),
        GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/1, // vdata_in
        GIR_AddSimpleTempRegister, /*InsnID*/0, /*TempRegID*/0,
        GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/2, // rsrc
        GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/0, // soffset
        GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/6, // offset
        GIR_CustomOperandRenderer, /*InsnID*/0, /*OldInsnID*/0, /*OpIdx*/7, /*OperandRenderer*/GIMT_Encode2(GICR_renderExtractCPol), // auxiliary
        GIR_MergeMemOperands, /*InsnID*/0, /*NumInsns*/1, /*MergeInsnID's*/0,
        GIR_ConstrainSelectedInstOperands, /*InsnID*/0,
        GIR_EraseFromParent, /*InsnID*/0,
        // GIR_Coverage, 5168,
        GIR_Done,
      // Label 5952: @434863
      GIM_Try, /*On fail goto*//*Label 5953*/ GIMT_Encode4(434969), // Rule ID 5176 //
        GIM_CheckFeatures, GIMT_Encode2(GIFBS_isGFX6GFX7GFX10Plus),
        GIM_CheckHasNoUse, /*MI*/0,
        // MIs[0] offset
        GIM_CheckIsImm, /*MI*/0, /*Op*/6,
        // MIs[0] auxiliary
        GIM_CheckIsImm, /*MI*/0, /*Op*/7,
        // MIs[0] Operand 8
        GIM_CheckIsImm, /*MI*/0, /*Op*/8,
        GIM_CheckComplexPattern, /*MI*/0, /*Op*/5, /*Renderer*/GIMT_Encode2(0), GIMT_Encode2(GICP_gi_buf_soffset),
        // (SIbuffer_atomic_fmax:{ *:[f32] } f32:{ *:[f32] }:$vdata_in, v4i32:{ *:[v4i32] }:$rsrc, i32:{ *:[i32] }:$vindex, i32:{ *:[i32] }:$voffset, (BUFSOffset:{ *:[i32] } i32:{ *:[i32] }:$soffset), (timm:{ *:[i32] }):$offset, (timm:{ *:[i32] }):$auxiliary, (timm:{ *:[i1] }))<<P:Predicate_SIbuffer_atomic_fmax_noret>>  =>  (BUFFER_ATOMIC_FMAX_VBUFFER_BOTHEN anonymous_15037:{ *:[f32] }:$vdata_in, (REG_SEQUENCE:{ *:[i64] } VReg_64:{ *:[i32] }, VGPR_32:{ *:[i32] }:$vindex, sub0:{ *:[i32] }, VGPR_32:{ *:[i32] }:$voffset, sub1:{ *:[i32] }), SReg_128:{ *:[v4i32] }:$rsrc, SCSrc_b32:{ *:[i32] }:$soffset, (timm:{ *:[i32] }):$offset, (extract_cpol:{ *:[i32] } ?:{ *:[i32] }:$auxiliary))
        GIR_MakeTempReg, /*TempRegID*/0, /*TypeID*/GILLT_s64,
        GIR_BuildMI, /*InsnID*/1, /*Opcode*/GIMT_Encode2(TargetOpcode::REG_SEQUENCE),
        GIR_AddTempRegister, /*InsnID*/1, /*TempRegID*/0, /*TempRegFlags*/GIMT_Encode2(RegState::Define),
        GIR_Copy, /*NewInsnID*/1, /*OldInsnID*/0, /*OpIdx*/3, // vindex
        GIR_AddImm8, /*InsnID*/1, /*SubRegIndex*/3,
        GIR_Copy, /*NewInsnID*/1, /*OldInsnID*/0, /*OpIdx*/4, // voffset
        GIR_AddImm8, /*InsnID*/1, /*SubRegIndex*/11,
        GIR_ConstrainOperandRC, /*InsnID*/1, /*Op*/0, GIMT_Encode2(AMDGPU::VReg_64RegClassID),
        GIR_ConstrainOperandRC, /*InsnID*/1, /*Op*/1, GIMT_Encode2(AMDGPU::VGPR_32RegClassID),
        GIR_ConstrainOperandRC, /*InsnID*/1, /*Op*/3, GIMT_Encode2(AMDGPU::VGPR_32RegClassID),
        GIR_BuildMI, /*InsnID*/0, /*Opcode*/GIMT_Encode2(AMDGPU::BUFFER_ATOMIC_FMAX_VBUFFER_BOTHEN),
        GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/1, // vdata_in
        GIR_AddSimpleTempRegister, /*InsnID*/0, /*TempRegID*/0,
        GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/2, // rsrc
        GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/0, // soffset
        GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/6, // offset
        GIR_CustomOperandRenderer, /*InsnID*/0, /*OldInsnID*/0, /*OpIdx*/7, /*OperandRenderer*/GIMT_Encode2(GICR_renderExtractCPol), // auxiliary
        GIR_MergeMemOperands, /*InsnID*/0, /*NumInsns*/1, /*MergeInsnID's*/0,
        GIR_ConstrainSelectedInstOperands, /*InsnID*/0,
        GIR_EraseFromParent, /*InsnID*/0,
        // GIR_Coverage, 5176,
        GIR_Done,
      // Label 5953: @434969
      GIM_Try, /*On fail goto*//*Label 5954*/ GIMT_Encode4(435082), // Rule ID 5164 //
        GIM_CheckFeatures, GIMT_Encode2(GIFBS_isGFX6GFX7GFX10Plus),
        GIM_CheckRegBankForClass, /*MI*/0, /*Op*/0, /*RC*/GIMT_Encode2(AMDGPU::AV_32RegClassID),
        // MIs[0] offset
        GIM_CheckIsImm, /*MI*/0, /*Op*/6,
        // MIs[0] auxiliary
        GIM_CheckIsImm, /*MI*/0, /*Op*/7,
        // MIs[0] Operand 8
        GIM_CheckIsImm, /*MI*/0, /*Op*/8,
        GIM_CheckComplexPattern, /*MI*/0, /*Op*/5, /*Renderer*/GIMT_Encode2(0), GIMT_Encode2(GICP_gi_buf_soffset),
        // (SIbuffer_atomic_fmax:{ *:[f32] } f32:{ *:[f32] }:$vdata_in, v4i32:{ *:[v4i32] }:$rsrc, i32:{ *:[i32] }:$vindex, i32:{ *:[i32] }:$voffset, (BUFSOffset:{ *:[i32] } i32:{ *:[i32] }:$soffset), (timm:{ *:[i32] }):$offset, (timm:{ *:[i32] }):$auxiliary, (timm:{ *:[i1] }))  =>  (BUFFER_ATOMIC_FMAX_BOTHEN_RTN:{ *:[f32] } anonymous_15037:{ *:[f32] }:$vdata_in, (REG_SEQUENCE:{ *:[i64] } VReg_64:{ *:[i32] }, VGPR_32:{ *:[i32] }:$vindex, sub0:{ *:[i32] }, VGPR_32:{ *:[i32] }:$voffset, sub1:{ *:[i32] }), SReg_128:{ *:[v4i32] }:$rsrc, SCSrc_b32:{ *:[i32] }:$soffset, (timm:{ *:[i32] }):$offset, (extract_cpol_set_glc:{ *:[i32] } ?:{ *:[i32] }:$auxiliary))
        GIR_MakeTempReg, /*TempRegID*/0, /*TypeID*/GILLT_s64,
        GIR_BuildMI, /*InsnID*/1, /*Opcode*/GIMT_Encode2(TargetOpcode::REG_SEQUENCE),
        GIR_AddTempRegister, /*InsnID*/1, /*TempRegID*/0, /*TempRegFlags*/GIMT_Encode2(RegState::Define),
        GIR_Copy, /*NewInsnID*/1, /*OldInsnID*/0, /*OpIdx*/3, // vindex
        GIR_AddImm8, /*InsnID*/1, /*SubRegIndex*/3,
        GIR_Copy, /*NewInsnID*/1, /*OldInsnID*/0, /*OpIdx*/4, // voffset
        GIR_AddImm8, /*InsnID*/1, /*SubRegIndex*/11,
        GIR_ConstrainOperandRC, /*InsnID*/1, /*Op*/0, GIMT_Encode2(AMDGPU::VReg_64RegClassID),
        GIR_ConstrainOperandRC, /*InsnID*/1, /*Op*/1, GIMT_Encode2(AMDGPU::VGPR_32RegClassID),
        GIR_ConstrainOperandRC, /*InsnID*/1, /*Op*/3, GIMT_Encode2(AMDGPU::VGPR_32RegClassID),
        GIR_BuildMI, /*InsnID*/0, /*Opcode*/GIMT_Encode2(AMDGPU::BUFFER_ATOMIC_FMAX_BOTHEN_RTN),
        GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/0, // DstI[vdata]
        GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/1, // vdata_in
        GIR_AddSimpleTempRegister, /*InsnID*/0, /*TempRegID*/0,
        GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/2, // rsrc
        GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/0, // soffset
        GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/6, // offset
        GIR_CustomOperandRenderer, /*InsnID*/0, /*OldInsnID*/0, /*OpIdx*/7, /*OperandRenderer*/GIMT_Encode2(GICR_renderExtractCpolSetGLC), // auxiliary
        GIR_MergeMemOperands, /*InsnID*/0, /*NumInsns*/1, /*MergeInsnID's*/0,
        GIR_ConstrainSelectedInstOperands, /*InsnID*/0,
        GIR_EraseFromParent, /*InsnID*/0,
        // GIR_Coverage, 5164,
        GIR_Done,
      // Label 5954: @435082
      GIM_Try, /*On fail goto*//*Label 5955*/ GIMT_Encode4(435195), // Rule ID 5172 //
        GIM_CheckFeatures, GIMT_Encode2(GIFBS_isGFX6GFX7GFX10Plus),
        GIM_CheckRegBankForClass, /*MI*/0, /*Op*/0, /*RC*/GIMT_Encode2(AMDGPU::AV_32RegClassID),
        // MIs[0] offset
        GIM_CheckIsImm, /*MI*/0, /*Op*/6,
        // MIs[0] auxiliary
        GIM_CheckIsImm, /*MI*/0, /*Op*/7,
        // MIs[0] Operand 8
        GIM_CheckIsImm, /*MI*/0, /*Op*/8,
        GIM_CheckComplexPattern, /*MI*/0, /*Op*/5, /*Renderer*/GIMT_Encode2(0), GIMT_Encode2(GICP_gi_buf_soffset),
        // (SIbuffer_atomic_fmax:{ *:[f32] } f32:{ *:[f32] }:$vdata_in, v4i32:{ *:[v4i32] }:$rsrc, i32:{ *:[i32] }:$vindex, i32:{ *:[i32] }:$voffset, (BUFSOffset:{ *:[i32] } i32:{ *:[i32] }:$soffset), (timm:{ *:[i32] }):$offset, (timm:{ *:[i32] }):$auxiliary, (timm:{ *:[i1] }))  =>  (BUFFER_ATOMIC_FMAX_VBUFFER_BOTHEN_RTN:{ *:[f32] } anonymous_15037:{ *:[f32] }:$vdata_in, (REG_SEQUENCE:{ *:[i64] } VReg_64:{ *:[i32] }, VGPR_32:{ *:[i32] }:$vindex, sub0:{ *:[i32] }, VGPR_32:{ *:[i32] }:$voffset, sub1:{ *:[i32] }), SReg_128:{ *:[v4i32] }:$rsrc, SCSrc_b32:{ *:[i32] }:$soffset, (timm:{ *:[i32] }):$offset, (extract_cpol_set_glc:{ *:[i32] } ?:{ *:[i32] }:$auxiliary))
        GIR_MakeTempReg, /*TempRegID*/0, /*TypeID*/GILLT_s64,
        GIR_BuildMI, /*InsnID*/1, /*Opcode*/GIMT_Encode2(TargetOpcode::REG_SEQUENCE),
        GIR_AddTempRegister, /*InsnID*/1, /*TempRegID*/0, /*TempRegFlags*/GIMT_Encode2(RegState::Define),
        GIR_Copy, /*NewInsnID*/1, /*OldInsnID*/0, /*OpIdx*/3, // vindex
        GIR_AddImm8, /*InsnID*/1, /*SubRegIndex*/3,
        GIR_Copy, /*NewInsnID*/1, /*OldInsnID*/0, /*OpIdx*/4, // voffset
        GIR_AddImm8, /*InsnID*/1, /*SubRegIndex*/11,
        GIR_ConstrainOperandRC, /*InsnID*/1, /*Op*/0, GIMT_Encode2(AMDGPU::VReg_64RegClassID),
        GIR_ConstrainOperandRC, /*InsnID*/1, /*Op*/1, GIMT_Encode2(AMDGPU::VGPR_32RegClassID),
        GIR_ConstrainOperandRC, /*InsnID*/1, /*Op*/3, GIMT_Encode2(AMDGPU::VGPR_32RegClassID),
        GIR_BuildMI, /*InsnID*/0, /*Opcode*/GIMT_Encode2(AMDGPU::BUFFER_ATOMIC_FMAX_VBUFFER_BOTHEN_RTN),
        GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/0, // DstI[vdata]
        GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/1, // vdata_in
        GIR_AddSimpleTempRegister, /*InsnID*/0, /*TempRegID*/0,
        GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/2, // rsrc
        GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/0, // soffset
        GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/6, // offset
        GIR_CustomOperandRenderer, /*InsnID*/0, /*OldInsnID*/0, /*OpIdx*/7, /*OperandRenderer*/GIMT_Encode2(GICR_renderExtractCpolSetGLC), // auxiliary
        GIR_MergeMemOperands, /*InsnID*/0, /*NumInsns*/1, /*MergeInsnID's*/0,
        GIR_ConstrainSelectedInstOperands, /*InsnID*/0,
        GIR_EraseFromParent, /*InsnID*/0,
        // GIR_Coverage, 5172,
        GIR_Done,
      // Label 5955: @435195
      GIM_Reject,
    // Label 5939: @435196
    GIM_Reject,
    // Label 5937: @435197
    GIM_Try, /*On fail goto*//*Label 5956*/ GIMT_Encode4(437991),
      GIM_CheckType, /*MI*/0, /*Op*/1, /*Type*/GILLT_s64,
      GIM_CheckType, /*MI*/0, /*Op*/2, /*Type*/GILLT_v4s32,
      GIM_CheckType, /*MI*/0, /*Op*/3, /*Type*/GILLT_s32,
      GIM_CheckType, /*MI*/0, /*Op*/4, /*Type*/GILLT_s32,
      GIM_CheckType, /*MI*/0, /*Op*/5, /*Type*/GILLT_s32,
      GIM_Try, /*On fail goto*//*Label 5957*/ GIMT_Encode4(435300), // Rule ID 5197 //
        GIM_CheckFeatures, GIMT_Encode2(GIFBS_isGFX6GFX7GFX10),
        GIM_CheckHasNoUse, /*MI*/0,
        GIM_CheckConstantInt8, /*MI*/0, /*Op*/3, 0,
        GIM_CheckConstantInt8, /*MI*/0, /*Op*/4, 0,
        // MIs[0] offset
        GIM_CheckIsImm, /*MI*/0, /*Op*/6,
        // MIs[0] auxiliary
        GIM_CheckIsImm, /*MI*/0, /*Op*/7,
        // MIs[0] Operand 8
        GIM_CheckLiteralInt, /*MI*/0, /*Op*/8, GIMT_Encode8(0),
        GIM_CheckComplexPattern, /*MI*/0, /*Op*/5, /*Renderer*/GIMT_Encode2(0), GIMT_Encode2(GICP_gi_buf_soffset),
        // (SIbuffer_atomic_fmax:{ *:[f64] } f64:{ *:[f64] }:$vdata_in, v4i32:{ *:[v4i32] }:$rsrc, 0:{ *:[i32] }, 0:{ *:[i32] }, (BUFSOffset:{ *:[i32] } i32:{ *:[i32] }:$soffset), (timm:{ *:[i32] }):$offset, (timm:{ *:[i32] }):$auxiliary, 0:{ *:[i1] })<<P:Predicate_SIbuffer_atomic_fmax_noret>>  =>  (BUFFER_ATOMIC_FMAX_X2_OFFSET anonymous_15036:{ *:[f64] }:$vdata_in, SReg_128:{ *:[v4i32] }:$rsrc, SCSrc_b32:{ *:[i32] }:$soffset, (timm:{ *:[i32] }):$offset, (extract_cpol:{ *:[i32] } ?:{ *:[i32] }:$auxiliary))
        GIR_BuildMI, /*InsnID*/0, /*Opcode*/GIMT_Encode2(AMDGPU::BUFFER_ATOMIC_FMAX_X2_OFFSET),
        GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/1, // vdata_in
        GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/2, // rsrc
        GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/0, // soffset
        GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/6, // offset
        GIR_CustomOperandRenderer, /*InsnID*/0, /*OldInsnID*/0, /*OpIdx*/7, /*OperandRenderer*/GIMT_Encode2(GICR_renderExtractCPol), // auxiliary
        GIR_MergeMemOperands, /*InsnID*/0, /*NumInsns*/1, /*MergeInsnID's*/0,
        GIR_ConstrainSelectedInstOperands, /*InsnID*/0,
        GIR_EraseFromParent, /*InsnID*/0,
        // GIR_Coverage, 5197,
        GIR_Done,
      // Label 5957: @435300
      GIM_Try, /*On fail goto*//*Label 5958*/ GIMT_Encode4(435378), // Rule ID 5205 //
        GIM_CheckFeatures, GIMT_Encode2(GIFBS_isGFX6GFX7GFX10),
        GIM_CheckHasNoUse, /*MI*/0,
        GIM_CheckConstantInt8, /*MI*/0, /*Op*/3, 0,
        GIM_CheckConstantInt8, /*MI*/0, /*Op*/4, 0,
        // MIs[0] offset
        GIM_CheckIsImm, /*MI*/0, /*Op*/6,
        // MIs[0] auxiliary
        GIM_CheckIsImm, /*MI*/0, /*Op*/7,
        // MIs[0] Operand 8
        GIM_CheckLiteralInt, /*MI*/0, /*Op*/8, GIMT_Encode8(0),
        GIM_CheckComplexPattern, /*MI*/0, /*Op*/5, /*Renderer*/GIMT_Encode2(0), GIMT_Encode2(GICP_gi_buf_soffset),
        // (SIbuffer_atomic_fmax:{ *:[f64] } f64:{ *:[f64] }:$vdata_in, v4i32:{ *:[v4i32] }:$rsrc, 0:{ *:[i32] }, 0:{ *:[i32] }, (BUFSOffset:{ *:[i32] } i32:{ *:[i32] }:$soffset), (timm:{ *:[i32] }):$offset, (timm:{ *:[i32] }):$auxiliary, 0:{ *:[i1] })<<P:Predicate_SIbuffer_atomic_fmax_noret>>  =>  (BUFFER_ATOMIC_FMAX_X2_VBUFFER_OFFSET anonymous_15036:{ *:[f64] }:$vdata_in, SReg_128:{ *:[v4i32] }:$rsrc, SCSrc_b32:{ *:[i32] }:$soffset, (timm:{ *:[i32] }):$offset, (extract_cpol:{ *:[i32] } ?:{ *:[i32] }:$auxiliary))
        GIR_BuildMI, /*InsnID*/0, /*Opcode*/GIMT_Encode2(AMDGPU::BUFFER_ATOMIC_FMAX_X2_VBUFFER_OFFSET),
        GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/1, // vdata_in
        GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/2, // rsrc
        GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/0, // soffset
        GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/6, // offset
        GIR_CustomOperandRenderer, /*InsnID*/0, /*OldInsnID*/0, /*OpIdx*/7, /*OperandRenderer*/GIMT_Encode2(GICR_renderExtractCPol), // auxiliary
        GIR_MergeMemOperands, /*InsnID*/0, /*NumInsns*/1, /*MergeInsnID's*/0,
        GIR_ConstrainSelectedInstOperands, /*InsnID*/0,
        GIR_EraseFromParent, /*InsnID*/0,
        // GIR_Coverage, 5205,
        GIR_Done,
      // Label 5958: @435378
      GIM_Try, /*On fail goto*//*Label 5959*/ GIMT_Encode4(435456), // Rule ID 5277 //
        GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasUnrestrictedSOffset_isGFX90APlus),
        GIM_CheckHasNoUse, /*MI*/0,
        GIM_CheckConstantInt8, /*MI*/0, /*Op*/3, 0,
        GIM_CheckConstantInt8, /*MI*/0, /*Op*/4, 0,
        // MIs[0] offset
        GIM_CheckIsImm, /*MI*/0, /*Op*/6,
        // MIs[0] auxiliary
        GIM_CheckIsImm, /*MI*/0, /*Op*/7,
        // MIs[0] Operand 8
        GIM_CheckLiteralInt, /*MI*/0, /*Op*/8, GIMT_Encode8(0),
        GIM_CheckComplexPattern, /*MI*/0, /*Op*/5, /*Renderer*/GIMT_Encode2(0), GIMT_Encode2(GICP_gi_buf_soffset),
        // (SIbuffer_atomic_fmax:{ *:[f64] } f64:{ *:[f64] }:$vdata_in, v4i32:{ *:[v4i32] }:$rsrc, 0:{ *:[i32] }, 0:{ *:[i32] }, (BUFSOffset:{ *:[i32] } i32:{ *:[i32] }:$soffset), (timm:{ *:[i32] }):$offset, (timm:{ *:[i32] }):$auxiliary, 0:{ *:[i1] })<<P:Predicate_SIbuffer_atomic_fmax_noret>>  =>  (BUFFER_ATOMIC_MAX_F64_OFFSET anonymous_15036:{ *:[f64] }:$vdata_in, SReg_128:{ *:[v4i32] }:$rsrc, SCSrc_b32:{ *:[i32] }:$soffset, (timm:{ *:[i32] }):$offset, (extract_cpol:{ *:[i32] } ?:{ *:[i32] }:$auxiliary))
        GIR_BuildMI, /*InsnID*/0, /*Opcode*/GIMT_Encode2(AMDGPU::BUFFER_ATOMIC_MAX_F64_OFFSET),
        GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/1, // vdata_in
        GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/2, // rsrc
        GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/0, // soffset
        GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/6, // offset
        GIR_CustomOperandRenderer, /*InsnID*/0, /*OldInsnID*/0, /*OpIdx*/7, /*OperandRenderer*/GIMT_Encode2(GICR_renderExtractCPol), // auxiliary
        GIR_MergeMemOperands, /*InsnID*/0, /*NumInsns*/1, /*MergeInsnID's*/0,
        GIR_ConstrainSelectedInstOperands, /*InsnID*/0,
        GIR_EraseFromParent, /*InsnID*/0,
        // GIR_Coverage, 5277,
        GIR_Done,
      // Label 5959: @435456
      GIM_Try, /*On fail goto*//*Label 5960*/ GIMT_Encode4(435534), // Rule ID 5285 //
        GIM_CheckFeatures, GIMT_Encode2(GIFBS_isGFX90APlus),
        GIM_CheckHasNoUse, /*MI*/0,
        GIM_CheckConstantInt8, /*MI*/0, /*Op*/3, 0,
        GIM_CheckConstantInt8, /*MI*/0, /*Op*/4, 0,
        // MIs[0] offset
        GIM_CheckIsImm, /*MI*/0, /*Op*/6,
        // MIs[0] auxiliary
        GIM_CheckIsImm, /*MI*/0, /*Op*/7,
        // MIs[0] Operand 8
        GIM_CheckLiteralInt, /*MI*/0, /*Op*/8, GIMT_Encode8(0),
        GIM_CheckComplexPattern, /*MI*/0, /*Op*/5, /*Renderer*/GIMT_Encode2(0), GIMT_Encode2(GICP_gi_buf_soffset),
        // (SIbuffer_atomic_fmax:{ *:[f64] } f64:{ *:[f64] }:$vdata_in, v4i32:{ *:[v4i32] }:$rsrc, 0:{ *:[i32] }, 0:{ *:[i32] }, (BUFSOffset:{ *:[i32] } i32:{ *:[i32] }:$soffset), (timm:{ *:[i32] }):$offset, (timm:{ *:[i32] }):$auxiliary, 0:{ *:[i1] })<<P:Predicate_SIbuffer_atomic_fmax_noret>>  =>  (BUFFER_ATOMIC_MAX_F64_VBUFFER_OFFSET anonymous_15036:{ *:[f64] }:$vdata_in, SReg_128:{ *:[v4i32] }:$rsrc, SCSrc_b32:{ *:[i32] }:$soffset, (timm:{ *:[i32] }):$offset, (extract_cpol:{ *:[i32] } ?:{ *:[i32] }:$auxiliary))
        GIR_BuildMI, /*InsnID*/0, /*Opcode*/GIMT_Encode2(AMDGPU::BUFFER_ATOMIC_MAX_F64_VBUFFER_OFFSET),
        GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/1, // vdata_in
        GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/2, // rsrc
        GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/0, // soffset
        GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/6, // offset
        GIR_CustomOperandRenderer, /*InsnID*/0, /*OldInsnID*/0, /*OpIdx*/7, /*OperandRenderer*/GIMT_Encode2(GICR_renderExtractCPol), // auxiliary
        GIR_MergeMemOperands, /*InsnID*/0, /*NumInsns*/1, /*MergeInsnID's*/0,
        GIR_ConstrainSelectedInstOperands, /*InsnID*/0,
        GIR_EraseFromParent, /*InsnID*/0,
        // GIR_Coverage, 5285,
        GIR_Done,
      // Label 5960: @435534
      GIM_Try, /*On fail goto*//*Label 5961*/ GIMT_Encode4(435619), // Rule ID 5193 //
        GIM_CheckFeatures, GIMT_Encode2(GIFBS_isGFX6GFX7GFX10),
        GIM_CheckRegBankForClass, /*MI*/0, /*Op*/0, /*RC*/GIMT_Encode2(AMDGPU::AV_64RegClassID),
        GIM_CheckConstantInt8, /*MI*/0, /*Op*/3, 0,
        GIM_CheckConstantInt8, /*MI*/0, /*Op*/4, 0,
        // MIs[0] offset
        GIM_CheckIsImm, /*MI*/0, /*Op*/6,
        // MIs[0] auxiliary
        GIM_CheckIsImm, /*MI*/0, /*Op*/7,
        // MIs[0] Operand 8
        GIM_CheckLiteralInt, /*MI*/0, /*Op*/8, GIMT_Encode8(0),
        GIM_CheckComplexPattern, /*MI*/0, /*Op*/5, /*Renderer*/GIMT_Encode2(0), GIMT_Encode2(GICP_gi_buf_soffset),
        // (SIbuffer_atomic_fmax:{ *:[f64] } f64:{ *:[f64] }:$vdata_in, v4i32:{ *:[v4i32] }:$rsrc, 0:{ *:[i32] }, 0:{ *:[i32] }, (BUFSOffset:{ *:[i32] } i32:{ *:[i32] }:$soffset), (timm:{ *:[i32] }):$offset, (timm:{ *:[i32] }):$auxiliary, 0:{ *:[i1] })  =>  (BUFFER_ATOMIC_FMAX_X2_OFFSET_RTN:{ *:[f64] } anonymous_15036:{ *:[f64] }:$vdata_in, SReg_128:{ *:[v4i32] }:$rsrc, SCSrc_b32:{ *:[i32] }:$soffset, (timm:{ *:[i32] }):$offset, (extract_cpol_set_glc:{ *:[i32] } ?:{ *:[i32] }:$auxiliary))
        GIR_BuildMI, /*InsnID*/0, /*Opcode*/GIMT_Encode2(AMDGPU::BUFFER_ATOMIC_FMAX_X2_OFFSET_RTN),
        GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/0, // DstI[vdata]
        GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/1, // vdata_in
        GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/2, // rsrc
        GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/0, // soffset
        GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/6, // offset
        GIR_CustomOperandRenderer, /*InsnID*/0, /*OldInsnID*/0, /*OpIdx*/7, /*OperandRenderer*/GIMT_Encode2(GICR_renderExtractCpolSetGLC), // auxiliary
        GIR_MergeMemOperands, /*InsnID*/0, /*NumInsns*/1, /*MergeInsnID's*/0,
        GIR_ConstrainSelectedInstOperands, /*InsnID*/0,
        GIR_EraseFromParent, /*InsnID*/0,
        // GIR_Coverage, 5193,
        GIR_Done,
      // Label 5961: @435619
      GIM_Try, /*On fail goto*//*Label 5962*/ GIMT_Encode4(435704), // Rule ID 5201 //
        GIM_CheckFeatures, GIMT_Encode2(GIFBS_isGFX6GFX7GFX10),
        GIM_CheckRegBankForClass, /*MI*/0, /*Op*/0, /*RC*/GIMT_Encode2(AMDGPU::AV_64RegClassID),
        GIM_CheckConstantInt8, /*MI*/0, /*Op*/3, 0,
        GIM_CheckConstantInt8, /*MI*/0, /*Op*/4, 0,
        // MIs[0] offset
        GIM_CheckIsImm, /*MI*/0, /*Op*/6,
        // MIs[0] auxiliary
        GIM_CheckIsImm, /*MI*/0, /*Op*/7,
        // MIs[0] Operand 8
        GIM_CheckLiteralInt, /*MI*/0, /*Op*/8, GIMT_Encode8(0),
        GIM_CheckComplexPattern, /*MI*/0, /*Op*/5, /*Renderer*/GIMT_Encode2(0), GIMT_Encode2(GICP_gi_buf_soffset),
        // (SIbuffer_atomic_fmax:{ *:[f64] } f64:{ *:[f64] }:$vdata_in, v4i32:{ *:[v4i32] }:$rsrc, 0:{ *:[i32] }, 0:{ *:[i32] }, (BUFSOffset:{ *:[i32] } i32:{ *:[i32] }:$soffset), (timm:{ *:[i32] }):$offset, (timm:{ *:[i32] }):$auxiliary, 0:{ *:[i1] })  =>  (BUFFER_ATOMIC_FMAX_X2_VBUFFER_OFFSET_RTN:{ *:[f64] } anonymous_15036:{ *:[f64] }:$vdata_in, SReg_128:{ *:[v4i32] }:$rsrc, SCSrc_b32:{ *:[i32] }:$soffset, (timm:{ *:[i32] }):$offset, (extract_cpol_set_glc:{ *:[i32] } ?:{ *:[i32] }:$auxiliary))
        GIR_BuildMI, /*InsnID*/0, /*Opcode*/GIMT_Encode2(AMDGPU::BUFFER_ATOMIC_FMAX_X2_VBUFFER_OFFSET_RTN),
        GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/0, // DstI[vdata]
        GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/1, // vdata_in
        GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/2, // rsrc
        GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/0, // soffset
        GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/6, // offset
        GIR_CustomOperandRenderer, /*InsnID*/0, /*OldInsnID*/0, /*OpIdx*/7, /*OperandRenderer*/GIMT_Encode2(GICR_renderExtractCpolSetGLC), // auxiliary
        GIR_MergeMemOperands, /*InsnID*/0, /*NumInsns*/1, /*MergeInsnID's*/0,
        GIR_ConstrainSelectedInstOperands, /*InsnID*/0,
        GIR_EraseFromParent, /*InsnID*/0,
        // GIR_Coverage, 5201,
        GIR_Done,
      // Label 5962: @435704
      GIM_Try, /*On fail goto*//*Label 5963*/ GIMT_Encode4(435789), // Rule ID 5273 //
        GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasUnrestrictedSOffset_isGFX90APlus),
        GIM_CheckRegBankForClass, /*MI*/0, /*Op*/0, /*RC*/GIMT_Encode2(AMDGPU::AV_64RegClassID),
        GIM_CheckConstantInt8, /*MI*/0, /*Op*/3, 0,
        GIM_CheckConstantInt8, /*MI*/0, /*Op*/4, 0,
        // MIs[0] offset
        GIM_CheckIsImm, /*MI*/0, /*Op*/6,
        // MIs[0] auxiliary
        GIM_CheckIsImm, /*MI*/0, /*Op*/7,
        // MIs[0] Operand 8
        GIM_CheckLiteralInt, /*MI*/0, /*Op*/8, GIMT_Encode8(0),
        GIM_CheckComplexPattern, /*MI*/0, /*Op*/5, /*Renderer*/GIMT_Encode2(0), GIMT_Encode2(GICP_gi_buf_soffset),
        // (SIbuffer_atomic_fmax:{ *:[f64] } f64:{ *:[f64] }:$vdata_in, v4i32:{ *:[v4i32] }:$rsrc, 0:{ *:[i32] }, 0:{ *:[i32] }, (BUFSOffset:{ *:[i32] } i32:{ *:[i32] }:$soffset), (timm:{ *:[i32] }):$offset, (timm:{ *:[i32] }):$auxiliary, 0:{ *:[i1] })  =>  (BUFFER_ATOMIC_MAX_F64_OFFSET_RTN:{ *:[f64] } anonymous_15036:{ *:[f64] }:$vdata_in, SReg_128:{ *:[v4i32] }:$rsrc, SCSrc_b32:{ *:[i32] }:$soffset, (timm:{ *:[i32] }):$offset, (extract_cpol_set_glc:{ *:[i32] } ?:{ *:[i32] }:$auxiliary))
        GIR_BuildMI, /*InsnID*/0, /*Opcode*/GIMT_Encode2(AMDGPU::BUFFER_ATOMIC_MAX_F64_OFFSET_RTN),
        GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/0, // DstI[vdata]
        GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/1, // vdata_in
        GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/2, // rsrc
        GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/0, // soffset
        GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/6, // offset
        GIR_CustomOperandRenderer, /*InsnID*/0, /*OldInsnID*/0, /*OpIdx*/7, /*OperandRenderer*/GIMT_Encode2(GICR_renderExtractCpolSetGLC), // auxiliary
        GIR_MergeMemOperands, /*InsnID*/0, /*NumInsns*/1, /*MergeInsnID's*/0,
        GIR_ConstrainSelectedInstOperands, /*InsnID*/0,
        GIR_EraseFromParent, /*InsnID*/0,
        // GIR_Coverage, 5273,
        GIR_Done,
      // Label 5963: @435789
      GIM_Try, /*On fail goto*//*Label 5964*/ GIMT_Encode4(435874), // Rule ID 5281 //
        GIM_CheckFeatures, GIMT_Encode2(GIFBS_isGFX90APlus),
        GIM_CheckRegBankForClass, /*MI*/0, /*Op*/0, /*RC*/GIMT_Encode2(AMDGPU::AV_64RegClassID),
        GIM_CheckConstantInt8, /*MI*/0, /*Op*/3, 0,
        GIM_CheckConstantInt8, /*MI*/0, /*Op*/4, 0,
        // MIs[0] offset
        GIM_CheckIsImm, /*MI*/0, /*Op*/6,
        // MIs[0] auxiliary
        GIM_CheckIsImm, /*MI*/0, /*Op*/7,
        // MIs[0] Operand 8
        GIM_CheckLiteralInt, /*MI*/0, /*Op*/8, GIMT_Encode8(0),
        GIM_CheckComplexPattern, /*MI*/0, /*Op*/5, /*Renderer*/GIMT_Encode2(0), GIMT_Encode2(GICP_gi_buf_soffset),
        // (SIbuffer_atomic_fmax:{ *:[f64] } f64:{ *:[f64] }:$vdata_in, v4i32:{ *:[v4i32] }:$rsrc, 0:{ *:[i32] }, 0:{ *:[i32] }, (BUFSOffset:{ *:[i32] } i32:{ *:[i32] }:$soffset), (timm:{ *:[i32] }):$offset, (timm:{ *:[i32] }):$auxiliary, 0:{ *:[i1] })  =>  (BUFFER_ATOMIC_MAX_F64_VBUFFER_OFFSET_RTN:{ *:[f64] } anonymous_15036:{ *:[f64] }:$vdata_in, SReg_128:{ *:[v4i32] }:$rsrc, SCSrc_b32:{ *:[i32] }:$soffset, (timm:{ *:[i32] }):$offset, (extract_cpol_set_glc:{ *:[i32] } ?:{ *:[i32] }:$auxiliary))
        GIR_BuildMI, /*InsnID*/0, /*Opcode*/GIMT_Encode2(AMDGPU::BUFFER_ATOMIC_MAX_F64_VBUFFER_OFFSET_RTN),
        GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/0, // DstI[vdata]
        GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/1, // vdata_in
        GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/2, // rsrc
        GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/0, // soffset
        GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/6, // offset
        GIR_CustomOperandRenderer, /*InsnID*/0, /*OldInsnID*/0, /*OpIdx*/7, /*OperandRenderer*/GIMT_Encode2(GICR_renderExtractCpolSetGLC), // auxiliary
        GIR_MergeMemOperands, /*InsnID*/0, /*NumInsns*/1, /*MergeInsnID's*/0,
        GIR_ConstrainSelectedInstOperands, /*InsnID*/0,
        GIR_EraseFromParent, /*InsnID*/0,
        // GIR_Coverage, 5281,
        GIR_Done,
      // Label 5964: @435874
      GIM_Try, /*On fail goto*//*Label 5965*/ GIMT_Encode4(435952), // Rule ID 5199 //
        GIM_CheckFeatures, GIMT_Encode2(GIFBS_isGFX6GFX7GFX10),
        GIM_CheckHasNoUse, /*MI*/0,
        GIM_CheckConstantInt8, /*MI*/0, /*Op*/3, 0,
        // MIs[0] offset
        GIM_CheckIsImm, /*MI*/0, /*Op*/6,
        // MIs[0] auxiliary
        GIM_CheckIsImm, /*MI*/0, /*Op*/7,
        // MIs[0] Operand 8
        GIM_CheckLiteralInt, /*MI*/0, /*Op*/8, GIMT_Encode8(0),
        GIM_CheckComplexPattern, /*MI*/0, /*Op*/5, /*Renderer*/GIMT_Encode2(0), GIMT_Encode2(GICP_gi_buf_soffset),
        // (SIbuffer_atomic_fmax:{ *:[f64] } f64:{ *:[f64] }:$vdata_in, v4i32:{ *:[v4i32] }:$rsrc, 0:{ *:[i32] }, i32:{ *:[i32] }:$voffset, (BUFSOffset:{ *:[i32] } i32:{ *:[i32] }:$soffset), (timm:{ *:[i32] }):$offset, (timm:{ *:[i32] }):$auxiliary, 0:{ *:[i1] })<<P:Predicate_SIbuffer_atomic_fmax_noret>>  =>  (BUFFER_ATOMIC_FMAX_X2_OFFEN anonymous_15036:{ *:[f64] }:$vdata_in, VGPR_32:{ *:[i32] }:$voffset, SReg_128:{ *:[v4i32] }:$rsrc, SCSrc_b32:{ *:[i32] }:$soffset, (timm:{ *:[i32] }):$offset, (extract_cpol:{ *:[i32] } ?:{ *:[i32] }:$auxiliary))
        GIR_BuildMI, /*InsnID*/0, /*Opcode*/GIMT_Encode2(AMDGPU::BUFFER_ATOMIC_FMAX_X2_OFFEN),
        GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/1, // vdata_in
        GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/4, // voffset
        GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/2, // rsrc
        GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/0, // soffset
        GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/6, // offset
        GIR_CustomOperandRenderer, /*InsnID*/0, /*OldInsnID*/0, /*OpIdx*/7, /*OperandRenderer*/GIMT_Encode2(GICR_renderExtractCPol), // auxiliary
        GIR_MergeMemOperands, /*InsnID*/0, /*NumInsns*/1, /*MergeInsnID's*/0,
        GIR_ConstrainSelectedInstOperands, /*InsnID*/0,
        GIR_EraseFromParent, /*InsnID*/0,
        // GIR_Coverage, 5199,
        GIR_Done,
      // Label 5965: @435952
      GIM_Try, /*On fail goto*//*Label 5966*/ GIMT_Encode4(436030), // Rule ID 5207 //
        GIM_CheckFeatures, GIMT_Encode2(GIFBS_isGFX6GFX7GFX10),
        GIM_CheckHasNoUse, /*MI*/0,
        GIM_CheckConstantInt8, /*MI*/0, /*Op*/3, 0,
        // MIs[0] offset
        GIM_CheckIsImm, /*MI*/0, /*Op*/6,
        // MIs[0] auxiliary
        GIM_CheckIsImm, /*MI*/0, /*Op*/7,
        // MIs[0] Operand 8
        GIM_CheckLiteralInt, /*MI*/0, /*Op*/8, GIMT_Encode8(0),
        GIM_CheckComplexPattern, /*MI*/0, /*Op*/5, /*Renderer*/GIMT_Encode2(0), GIMT_Encode2(GICP_gi_buf_soffset),
        // (SIbuffer_atomic_fmax:{ *:[f64] } f64:{ *:[f64] }:$vdata_in, v4i32:{ *:[v4i32] }:$rsrc, 0:{ *:[i32] }, i32:{ *:[i32] }:$voffset, (BUFSOffset:{ *:[i32] } i32:{ *:[i32] }:$soffset), (timm:{ *:[i32] }):$offset, (timm:{ *:[i32] }):$auxiliary, 0:{ *:[i1] })<<P:Predicate_SIbuffer_atomic_fmax_noret>>  =>  (BUFFER_ATOMIC_FMAX_X2_VBUFFER_OFFEN anonymous_15036:{ *:[f64] }:$vdata_in, VGPR_32:{ *:[i32] }:$voffset, SReg_128:{ *:[v4i32] }:$rsrc, SCSrc_b32:{ *:[i32] }:$soffset, (timm:{ *:[i32] }):$offset, (extract_cpol:{ *:[i32] } ?:{ *:[i32] }:$auxiliary))
        GIR_BuildMI, /*InsnID*/0, /*Opcode*/GIMT_Encode2(AMDGPU::BUFFER_ATOMIC_FMAX_X2_VBUFFER_OFFEN),
        GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/1, // vdata_in
        GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/4, // voffset
        GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/2, // rsrc
        GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/0, // soffset
        GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/6, // offset
        GIR_CustomOperandRenderer, /*InsnID*/0, /*OldInsnID*/0, /*OpIdx*/7, /*OperandRenderer*/GIMT_Encode2(GICR_renderExtractCPol), // auxiliary
        GIR_MergeMemOperands, /*InsnID*/0, /*NumInsns*/1, /*MergeInsnID's*/0,
        GIR_ConstrainSelectedInstOperands, /*InsnID*/0,
        GIR_EraseFromParent, /*InsnID*/0,
        // GIR_Coverage, 5207,
        GIR_Done,
      // Label 5966: @436030
      GIM_Try, /*On fail goto*//*Label 5967*/ GIMT_Encode4(436108), // Rule ID 5279 //
        GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasUnrestrictedSOffset_isGFX90APlus),
        GIM_CheckHasNoUse, /*MI*/0,
        GIM_CheckConstantInt8, /*MI*/0, /*Op*/3, 0,
        // MIs[0] offset
        GIM_CheckIsImm, /*MI*/0, /*Op*/6,
        // MIs[0] auxiliary
        GIM_CheckIsImm, /*MI*/0, /*Op*/7,
        // MIs[0] Operand 8
        GIM_CheckLiteralInt, /*MI*/0, /*Op*/8, GIMT_Encode8(0),
        GIM_CheckComplexPattern, /*MI*/0, /*Op*/5, /*Renderer*/GIMT_Encode2(0), GIMT_Encode2(GICP_gi_buf_soffset),
        // (SIbuffer_atomic_fmax:{ *:[f64] } f64:{ *:[f64] }:$vdata_in, v4i32:{ *:[v4i32] }:$rsrc, 0:{ *:[i32] }, i32:{ *:[i32] }:$voffset, (BUFSOffset:{ *:[i32] } i32:{ *:[i32] }:$soffset), (timm:{ *:[i32] }):$offset, (timm:{ *:[i32] }):$auxiliary, 0:{ *:[i1] })<<P:Predicate_SIbuffer_atomic_fmax_noret>>  =>  (BUFFER_ATOMIC_MAX_F64_OFFEN anonymous_15036:{ *:[f64] }:$vdata_in, VGPR_32:{ *:[i32] }:$voffset, SReg_128:{ *:[v4i32] }:$rsrc, SCSrc_b32:{ *:[i32] }:$soffset, (timm:{ *:[i32] }):$offset, (extract_cpol:{ *:[i32] } ?:{ *:[i32] }:$auxiliary))
        GIR_BuildMI, /*InsnID*/0, /*Opcode*/GIMT_Encode2(AMDGPU::BUFFER_ATOMIC_MAX_F64_OFFEN),
        GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/1, // vdata_in
        GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/4, // voffset
        GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/2, // rsrc
        GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/0, // soffset
        GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/6, // offset
        GIR_CustomOperandRenderer, /*InsnID*/0, /*OldInsnID*/0, /*OpIdx*/7, /*OperandRenderer*/GIMT_Encode2(GICR_renderExtractCPol), // auxiliary
        GIR_MergeMemOperands, /*InsnID*/0, /*NumInsns*/1, /*MergeInsnID's*/0,
        GIR_ConstrainSelectedInstOperands, /*InsnID*/0,
        GIR_EraseFromParent, /*InsnID*/0,
        // GIR_Coverage, 5279,
        GIR_Done,
      // Label 5967: @436108
      GIM_Try, /*On fail goto*//*Label 5968*/ GIMT_Encode4(436186), // Rule ID 5287 //
        GIM_CheckFeatures, GIMT_Encode2(GIFBS_isGFX90APlus),
        GIM_CheckHasNoUse, /*MI*/0,
        GIM_CheckConstantInt8, /*MI*/0, /*Op*/3, 0,
        // MIs[0] offset
        GIM_CheckIsImm, /*MI*/0, /*Op*/6,
        // MIs[0] auxiliary
        GIM_CheckIsImm, /*MI*/0, /*Op*/7,
        // MIs[0] Operand 8
        GIM_CheckLiteralInt, /*MI*/0, /*Op*/8, GIMT_Encode8(0),
        GIM_CheckComplexPattern, /*MI*/0, /*Op*/5, /*Renderer*/GIMT_Encode2(0), GIMT_Encode2(GICP_gi_buf_soffset),
        // (SIbuffer_atomic_fmax:{ *:[f64] } f64:{ *:[f64] }:$vdata_in, v4i32:{ *:[v4i32] }:$rsrc, 0:{ *:[i32] }, i32:{ *:[i32] }:$voffset, (BUFSOffset:{ *:[i32] } i32:{ *:[i32] }:$soffset), (timm:{ *:[i32] }):$offset, (timm:{ *:[i32] }):$auxiliary, 0:{ *:[i1] })<<P:Predicate_SIbuffer_atomic_fmax_noret>>  =>  (BUFFER_ATOMIC_MAX_F64_VBUFFER_OFFEN anonymous_15036:{ *:[f64] }:$vdata_in, VGPR_32:{ *:[i32] }:$voffset, SReg_128:{ *:[v4i32] }:$rsrc, SCSrc_b32:{ *:[i32] }:$soffset, (timm:{ *:[i32] }):$offset, (extract_cpol:{ *:[i32] } ?:{ *:[i32] }:$auxiliary))
        GIR_BuildMI, /*InsnID*/0, /*Opcode*/GIMT_Encode2(AMDGPU::BUFFER_ATOMIC_MAX_F64_VBUFFER_OFFEN),
        GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/1, // vdata_in
        GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/4, // voffset
        GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/2, // rsrc
        GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/0, // soffset
        GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/6, // offset
        GIR_CustomOperandRenderer, /*InsnID*/0, /*OldInsnID*/0, /*OpIdx*/7, /*OperandRenderer*/GIMT_Encode2(GICR_renderExtractCPol), // auxiliary
        GIR_MergeMemOperands, /*InsnID*/0, /*NumInsns*/1, /*MergeInsnID's*/0,
        GIR_ConstrainSelectedInstOperands, /*InsnID*/0,
        GIR_EraseFromParent, /*InsnID*/0,
        // GIR_Coverage, 5287,
        GIR_Done,
      // Label 5968: @436186
      GIM_Try, /*On fail goto*//*Label 5969*/ GIMT_Encode4(436271), // Rule ID 5195 //
        GIM_CheckFeatures, GIMT_Encode2(GIFBS_isGFX6GFX7GFX10),
        GIM_CheckRegBankForClass, /*MI*/0, /*Op*/0, /*RC*/GIMT_Encode2(AMDGPU::AV_64RegClassID),
        GIM_CheckConstantInt8, /*MI*/0, /*Op*/3, 0,
        // MIs[0] offset
        GIM_CheckIsImm, /*MI*/0, /*Op*/6,
        // MIs[0] auxiliary
        GIM_CheckIsImm, /*MI*/0, /*Op*/7,
        // MIs[0] Operand 8
        GIM_CheckLiteralInt, /*MI*/0, /*Op*/8, GIMT_Encode8(0),
        GIM_CheckComplexPattern, /*MI*/0, /*Op*/5, /*Renderer*/GIMT_Encode2(0), GIMT_Encode2(GICP_gi_buf_soffset),
        // (SIbuffer_atomic_fmax:{ *:[f64] } f64:{ *:[f64] }:$vdata_in, v4i32:{ *:[v4i32] }:$rsrc, 0:{ *:[i32] }, i32:{ *:[i32] }:$voffset, (BUFSOffset:{ *:[i32] } i32:{ *:[i32] }:$soffset), (timm:{ *:[i32] }):$offset, (timm:{ *:[i32] }):$auxiliary, 0:{ *:[i1] })  =>  (BUFFER_ATOMIC_FMAX_X2_OFFEN_RTN:{ *:[f64] } anonymous_15036:{ *:[f64] }:$vdata_in, VGPR_32:{ *:[i32] }:$voffset, SReg_128:{ *:[v4i32] }:$rsrc, SCSrc_b32:{ *:[i32] }:$soffset, (timm:{ *:[i32] }):$offset, (extract_cpol_set_glc:{ *:[i32] } ?:{ *:[i32] }:$auxiliary))
        GIR_BuildMI, /*InsnID*/0, /*Opcode*/GIMT_Encode2(AMDGPU::BUFFER_ATOMIC_FMAX_X2_OFFEN_RTN),
        GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/0, // DstI[vdata]
        GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/1, // vdata_in
        GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/4, // voffset
        GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/2, // rsrc
        GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/0, // soffset
        GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/6, // offset
        GIR_CustomOperandRenderer, /*InsnID*/0, /*OldInsnID*/0, /*OpIdx*/7, /*OperandRenderer*/GIMT_Encode2(GICR_renderExtractCpolSetGLC), // auxiliary
        GIR_MergeMemOperands, /*InsnID*/0, /*NumInsns*/1, /*MergeInsnID's*/0,
        GIR_ConstrainSelectedInstOperands, /*InsnID*/0,
        GIR_EraseFromParent, /*InsnID*/0,
        // GIR_Coverage, 5195,
        GIR_Done,
      // Label 5969: @436271
      GIM_Try, /*On fail goto*//*Label 5970*/ GIMT_Encode4(436356), // Rule ID 5203 //
        GIM_CheckFeatures, GIMT_Encode2(GIFBS_isGFX6GFX7GFX10),
        GIM_CheckRegBankForClass, /*MI*/0, /*Op*/0, /*RC*/GIMT_Encode2(AMDGPU::AV_64RegClassID),
        GIM_CheckConstantInt8, /*MI*/0, /*Op*/3, 0,
        // MIs[0] offset
        GIM_CheckIsImm, /*MI*/0, /*Op*/6,
        // MIs[0] auxiliary
        GIM_CheckIsImm, /*MI*/0, /*Op*/7,
        // MIs[0] Operand 8
        GIM_CheckLiteralInt, /*MI*/0, /*Op*/8, GIMT_Encode8(0),
        GIM_CheckComplexPattern, /*MI*/0, /*Op*/5, /*Renderer*/GIMT_Encode2(0), GIMT_Encode2(GICP_gi_buf_soffset),
        // (SIbuffer_atomic_fmax:{ *:[f64] } f64:{ *:[f64] }:$vdata_in, v4i32:{ *:[v4i32] }:$rsrc, 0:{ *:[i32] }, i32:{ *:[i32] }:$voffset, (BUFSOffset:{ *:[i32] } i32:{ *:[i32] }:$soffset), (timm:{ *:[i32] }):$offset, (timm:{ *:[i32] }):$auxiliary, 0:{ *:[i1] })  =>  (BUFFER_ATOMIC_FMAX_X2_VBUFFER_OFFEN_RTN:{ *:[f64] } anonymous_15036:{ *:[f64] }:$vdata_in, VGPR_32:{ *:[i32] }:$voffset, SReg_128:{ *:[v4i32] }:$rsrc, SCSrc_b32:{ *:[i32] }:$soffset, (timm:{ *:[i32] }):$offset, (extract_cpol_set_glc:{ *:[i32] } ?:{ *:[i32] }:$auxiliary))
        GIR_BuildMI, /*InsnID*/0, /*Opcode*/GIMT_Encode2(AMDGPU::BUFFER_ATOMIC_FMAX_X2_VBUFFER_OFFEN_RTN),
        GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/0, // DstI[vdata]
        GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/1, // vdata_in
        GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/4, // voffset
        GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/2, // rsrc
        GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/0, // soffset
        GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/6, // offset
        GIR_CustomOperandRenderer, /*InsnID*/0, /*OldInsnID*/0, /*OpIdx*/7, /*OperandRenderer*/GIMT_Encode2(GICR_renderExtractCpolSetGLC), // auxiliary
        GIR_MergeMemOperands, /*InsnID*/0, /*NumInsns*/1, /*MergeInsnID's*/0,
        GIR_ConstrainSelectedInstOperands, /*InsnID*/0,
        GIR_EraseFromParent, /*InsnID*/0,
        // GIR_Coverage, 5203,
        GIR_Done,
      // Label 5970: @436356
      GIM_Try, /*On fail goto*//*Label 5971*/ GIMT_Encode4(436441), // Rule ID 5275 //
        GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasUnrestrictedSOffset_isGFX90APlus),
        GIM_CheckRegBankForClass, /*MI*/0, /*Op*/0, /*RC*/GIMT_Encode2(AMDGPU::AV_64RegClassID),
        GIM_CheckConstantInt8, /*MI*/0, /*Op*/3, 0,
        // MIs[0] offset
        GIM_CheckIsImm, /*MI*/0, /*Op*/6,
        // MIs[0] auxiliary
        GIM_CheckIsImm, /*MI*/0, /*Op*/7,
        // MIs[0] Operand 8
        GIM_CheckLiteralInt, /*MI*/0, /*Op*/8, GIMT_Encode8(0),
        GIM_CheckComplexPattern, /*MI*/0, /*Op*/5, /*Renderer*/GIMT_Encode2(0), GIMT_Encode2(GICP_gi_buf_soffset),
        // (SIbuffer_atomic_fmax:{ *:[f64] } f64:{ *:[f64] }:$vdata_in, v4i32:{ *:[v4i32] }:$rsrc, 0:{ *:[i32] }, i32:{ *:[i32] }:$voffset, (BUFSOffset:{ *:[i32] } i32:{ *:[i32] }:$soffset), (timm:{ *:[i32] }):$offset, (timm:{ *:[i32] }):$auxiliary, 0:{ *:[i1] })  =>  (BUFFER_ATOMIC_MAX_F64_OFFEN_RTN:{ *:[f64] } anonymous_15036:{ *:[f64] }:$vdata_in, VGPR_32:{ *:[i32] }:$voffset, SReg_128:{ *:[v4i32] }:$rsrc, SCSrc_b32:{ *:[i32] }:$soffset, (timm:{ *:[i32] }):$offset, (extract_cpol_set_glc:{ *:[i32] } ?:{ *:[i32] }:$auxiliary))
        GIR_BuildMI, /*InsnID*/0, /*Opcode*/GIMT_Encode2(AMDGPU::BUFFER_ATOMIC_MAX_F64_OFFEN_RTN),
        GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/0, // DstI[vdata]
        GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/1, // vdata_in
        GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/4, // voffset
        GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/2, // rsrc
        GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/0, // soffset
        GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/6, // offset
        GIR_CustomOperandRenderer, /*InsnID*/0, /*OldInsnID*/0, /*OpIdx*/7, /*OperandRenderer*/GIMT_Encode2(GICR_renderExtractCpolSetGLC), // auxiliary
        GIR_MergeMemOperands, /*InsnID*/0, /*NumInsns*/1, /*MergeInsnID's*/0,
        GIR_ConstrainSelectedInstOperands, /*InsnID*/0,
        GIR_EraseFromParent, /*InsnID*/0,
        // GIR_Coverage, 5275,
        GIR_Done,
      // Label 5971: @436441
      GIM_Try, /*On fail goto*//*Label 5972*/ GIMT_Encode4(436526), // Rule ID 5283 //
        GIM_CheckFeatures, GIMT_Encode2(GIFBS_isGFX90APlus),
        GIM_CheckRegBankForClass, /*MI*/0, /*Op*/0, /*RC*/GIMT_Encode2(AMDGPU::AV_64RegClassID),
        GIM_CheckConstantInt8, /*MI*/0, /*Op*/3, 0,
        // MIs[0] offset
        GIM_CheckIsImm, /*MI*/0, /*Op*/6,
        // MIs[0] auxiliary
        GIM_CheckIsImm, /*MI*/0, /*Op*/7,
        // MIs[0] Operand 8
        GIM_CheckLiteralInt, /*MI*/0, /*Op*/8, GIMT_Encode8(0),
        GIM_CheckComplexPattern, /*MI*/0, /*Op*/5, /*Renderer*/GIMT_Encode2(0), GIMT_Encode2(GICP_gi_buf_soffset),
        // (SIbuffer_atomic_fmax:{ *:[f64] } f64:{ *:[f64] }:$vdata_in, v4i32:{ *:[v4i32] }:$rsrc, 0:{ *:[i32] }, i32:{ *:[i32] }:$voffset, (BUFSOffset:{ *:[i32] } i32:{ *:[i32] }:$soffset), (timm:{ *:[i32] }):$offset, (timm:{ *:[i32] }):$auxiliary, 0:{ *:[i1] })  =>  (BUFFER_ATOMIC_MAX_F64_VBUFFER_OFFEN_RTN:{ *:[f64] } anonymous_15036:{ *:[f64] }:$vdata_in, VGPR_32:{ *:[i32] }:$voffset, SReg_128:{ *:[v4i32] }:$rsrc, SCSrc_b32:{ *:[i32] }:$soffset, (timm:{ *:[i32] }):$offset, (extract_cpol_set_glc:{ *:[i32] } ?:{ *:[i32] }:$auxiliary))
        GIR_BuildMI, /*InsnID*/0, /*Opcode*/GIMT_Encode2(AMDGPU::BUFFER_ATOMIC_MAX_F64_VBUFFER_OFFEN_RTN),
        GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/0, // DstI[vdata]
        GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/1, // vdata_in
        GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/4, // voffset
        GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/2, // rsrc
        GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/0, // soffset
        GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/6, // offset
        GIR_CustomOperandRenderer, /*InsnID*/0, /*OldInsnID*/0, /*OpIdx*/7, /*OperandRenderer*/GIMT_Encode2(GICR_renderExtractCpolSetGLC), // auxiliary
        GIR_MergeMemOperands, /*InsnID*/0, /*NumInsns*/1, /*MergeInsnID's*/0,
        GIR_ConstrainSelectedInstOperands, /*InsnID*/0,
        GIR_EraseFromParent, /*InsnID*/0,
        // GIR_Coverage, 5283,
        GIR_Done,
      // Label 5972: @436526
      GIM_Try, /*On fail goto*//*Label 5973*/ GIMT_Encode4(436596), // Rule ID 5198 //
        GIM_CheckFeatures, GIMT_Encode2(GIFBS_isGFX6GFX7GFX10),
        GIM_CheckHasNoUse, /*MI*/0,
        GIM_CheckConstantInt8, /*MI*/0, /*Op*/4, 0,
        // MIs[0] offset
        GIM_CheckIsImm, /*MI*/0, /*Op*/6,
        // MIs[0] auxiliary
        GIM_CheckIsImm, /*MI*/0, /*Op*/7,
        // MIs[0] Operand 8
        GIM_CheckIsImm, /*MI*/0, /*Op*/8,
        GIM_CheckComplexPattern, /*MI*/0, /*Op*/5, /*Renderer*/GIMT_Encode2(0), GIMT_Encode2(GICP_gi_buf_soffset),
        // (SIbuffer_atomic_fmax:{ *:[f64] } f64:{ *:[f64] }:$vdata_in, v4i32:{ *:[v4i32] }:$rsrc, i32:{ *:[i32] }:$vindex, 0:{ *:[i32] }, (BUFSOffset:{ *:[i32] } i32:{ *:[i32] }:$soffset), (timm:{ *:[i32] }):$offset, (timm:{ *:[i32] }):$auxiliary, (timm:{ *:[i1] }))<<P:Predicate_SIbuffer_atomic_fmax_noret>>  =>  (BUFFER_ATOMIC_FMAX_X2_IDXEN anonymous_15036:{ *:[f64] }:$vdata_in, VGPR_32:{ *:[i32] }:$vindex, SReg_128:{ *:[v4i32] }:$rsrc, SCSrc_b32:{ *:[i32] }:$soffset, (timm:{ *:[i32] }):$offset, (extract_cpol:{ *:[i32] } ?:{ *:[i32] }:$auxiliary))
        GIR_BuildMI, /*InsnID*/0, /*Opcode*/GIMT_Encode2(AMDGPU::BUFFER_ATOMIC_FMAX_X2_IDXEN),
        GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/1, // vdata_in
        GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/3, // vindex
        GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/2, // rsrc
        GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/0, // soffset
        GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/6, // offset
        GIR_CustomOperandRenderer, /*InsnID*/0, /*OldInsnID*/0, /*OpIdx*/7, /*OperandRenderer*/GIMT_Encode2(GICR_renderExtractCPol), // auxiliary
        GIR_MergeMemOperands, /*InsnID*/0, /*NumInsns*/1, /*MergeInsnID's*/0,
        GIR_ConstrainSelectedInstOperands, /*InsnID*/0,
        GIR_EraseFromParent, /*InsnID*/0,
        // GIR_Coverage, 5198,
        GIR_Done,
      // Label 5973: @436596
      GIM_Try, /*On fail goto*//*Label 5974*/ GIMT_Encode4(436666), // Rule ID 5206 //
        GIM_CheckFeatures, GIMT_Encode2(GIFBS_isGFX6GFX7GFX10),
        GIM_CheckHasNoUse, /*MI*/0,
        GIM_CheckConstantInt8, /*MI*/0, /*Op*/4, 0,
        // MIs[0] offset
        GIM_CheckIsImm, /*MI*/0, /*Op*/6,
        // MIs[0] auxiliary
        GIM_CheckIsImm, /*MI*/0, /*Op*/7,
        // MIs[0] Operand 8
        GIM_CheckIsImm, /*MI*/0, /*Op*/8,
        GIM_CheckComplexPattern, /*MI*/0, /*Op*/5, /*Renderer*/GIMT_Encode2(0), GIMT_Encode2(GICP_gi_buf_soffset),
        // (SIbuffer_atomic_fmax:{ *:[f64] } f64:{ *:[f64] }:$vdata_in, v4i32:{ *:[v4i32] }:$rsrc, i32:{ *:[i32] }:$vindex, 0:{ *:[i32] }, (BUFSOffset:{ *:[i32] } i32:{ *:[i32] }:$soffset), (timm:{ *:[i32] }):$offset, (timm:{ *:[i32] }):$auxiliary, (timm:{ *:[i1] }))<<P:Predicate_SIbuffer_atomic_fmax_noret>>  =>  (BUFFER_ATOMIC_FMAX_X2_VBUFFER_IDXEN anonymous_15036:{ *:[f64] }:$vdata_in, VGPR_32:{ *:[i32] }:$vindex, SReg_128:{ *:[v4i32] }:$rsrc, SCSrc_b32:{ *:[i32] }:$soffset, (timm:{ *:[i32] }):$offset, (extract_cpol:{ *:[i32] } ?:{ *:[i32] }:$auxiliary))
        GIR_BuildMI, /*InsnID*/0, /*Opcode*/GIMT_Encode2(AMDGPU::BUFFER_ATOMIC_FMAX_X2_VBUFFER_IDXEN),
        GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/1, // vdata_in
        GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/3, // vindex
        GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/2, // rsrc
        GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/0, // soffset
        GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/6, // offset
        GIR_CustomOperandRenderer, /*InsnID*/0, /*OldInsnID*/0, /*OpIdx*/7, /*OperandRenderer*/GIMT_Encode2(GICR_renderExtractCPol), // auxiliary
        GIR_MergeMemOperands, /*InsnID*/0, /*NumInsns*/1, /*MergeInsnID's*/0,
        GIR_ConstrainSelectedInstOperands, /*InsnID*/0,
        GIR_EraseFromParent, /*InsnID*/0,
        // GIR_Coverage, 5206,
        GIR_Done,
      // Label 5974: @436666
      GIM_Try, /*On fail goto*//*Label 5975*/ GIMT_Encode4(436736), // Rule ID 5278 //
        GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasUnrestrictedSOffset_isGFX90APlus),
        GIM_CheckHasNoUse, /*MI*/0,
        GIM_CheckConstantInt8, /*MI*/0, /*Op*/4, 0,
        // MIs[0] offset
        GIM_CheckIsImm, /*MI*/0, /*Op*/6,
        // MIs[0] auxiliary
        GIM_CheckIsImm, /*MI*/0, /*Op*/7,
        // MIs[0] Operand 8
        GIM_CheckIsImm, /*MI*/0, /*Op*/8,
        GIM_CheckComplexPattern, /*MI*/0, /*Op*/5, /*Renderer*/GIMT_Encode2(0), GIMT_Encode2(GICP_gi_buf_soffset),
        // (SIbuffer_atomic_fmax:{ *:[f64] } f64:{ *:[f64] }:$vdata_in, v4i32:{ *:[v4i32] }:$rsrc, i32:{ *:[i32] }:$vindex, 0:{ *:[i32] }, (BUFSOffset:{ *:[i32] } i32:{ *:[i32] }:$soffset), (timm:{ *:[i32] }):$offset, (timm:{ *:[i32] }):$auxiliary, (timm:{ *:[i1] }))<<P:Predicate_SIbuffer_atomic_fmax_noret>>  =>  (BUFFER_ATOMIC_MAX_F64_IDXEN anonymous_15036:{ *:[f64] }:$vdata_in, VGPR_32:{ *:[i32] }:$vindex, SReg_128:{ *:[v4i32] }:$rsrc, SCSrc_b32:{ *:[i32] }:$soffset, (timm:{ *:[i32] }):$offset, (extract_cpol:{ *:[i32] } ?:{ *:[i32] }:$auxiliary))
        GIR_BuildMI, /*InsnID*/0, /*Opcode*/GIMT_Encode2(AMDGPU::BUFFER_ATOMIC_MAX_F64_IDXEN),
        GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/1, // vdata_in
        GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/3, // vindex
        GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/2, // rsrc
        GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/0, // soffset
        GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/6, // offset
        GIR_CustomOperandRenderer, /*InsnID*/0, /*OldInsnID*/0, /*OpIdx*/7, /*OperandRenderer*/GIMT_Encode2(GICR_renderExtractCPol), // auxiliary
        GIR_MergeMemOperands, /*InsnID*/0, /*NumInsns*/1, /*MergeInsnID's*/0,
        GIR_ConstrainSelectedInstOperands, /*InsnID*/0,
        GIR_EraseFromParent, /*InsnID*/0,
        // GIR_Coverage, 5278,
        GIR_Done,
      // Label 5975: @436736
      GIM_Try, /*On fail goto*//*Label 5976*/ GIMT_Encode4(436806), // Rule ID 5286 //
        GIM_CheckFeatures, GIMT_Encode2(GIFBS_isGFX90APlus),
        GIM_CheckHasNoUse, /*MI*/0,
        GIM_CheckConstantInt8, /*MI*/0, /*Op*/4, 0,
        // MIs[0] offset
        GIM_CheckIsImm, /*MI*/0, /*Op*/6,
        // MIs[0] auxiliary
        GIM_CheckIsImm, /*MI*/0, /*Op*/7,
        // MIs[0] Operand 8
        GIM_CheckIsImm, /*MI*/0, /*Op*/8,
        GIM_CheckComplexPattern, /*MI*/0, /*Op*/5, /*Renderer*/GIMT_Encode2(0), GIMT_Encode2(GICP_gi_buf_soffset),
        // (SIbuffer_atomic_fmax:{ *:[f64] } f64:{ *:[f64] }:$vdata_in, v4i32:{ *:[v4i32] }:$rsrc, i32:{ *:[i32] }:$vindex, 0:{ *:[i32] }, (BUFSOffset:{ *:[i32] } i32:{ *:[i32] }:$soffset), (timm:{ *:[i32] }):$offset, (timm:{ *:[i32] }):$auxiliary, (timm:{ *:[i1] }))<<P:Predicate_SIbuffer_atomic_fmax_noret>>  =>  (BUFFER_ATOMIC_MAX_F64_VBUFFER_IDXEN anonymous_15036:{ *:[f64] }:$vdata_in, VGPR_32:{ *:[i32] }:$vindex, SReg_128:{ *:[v4i32] }:$rsrc, SCSrc_b32:{ *:[i32] }:$soffset, (timm:{ *:[i32] }):$offset, (extract_cpol:{ *:[i32] } ?:{ *:[i32] }:$auxiliary))
        GIR_BuildMI, /*InsnID*/0, /*Opcode*/GIMT_Encode2(AMDGPU::BUFFER_ATOMIC_MAX_F64_VBUFFER_IDXEN),
        GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/1, // vdata_in
        GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/3, // vindex
        GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/2, // rsrc
        GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/0, // soffset
        GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/6, // offset
        GIR_CustomOperandRenderer, /*InsnID*/0, /*OldInsnID*/0, /*OpIdx*/7, /*OperandRenderer*/GIMT_Encode2(GICR_renderExtractCPol), // auxiliary
        GIR_MergeMemOperands, /*InsnID*/0, /*NumInsns*/1, /*MergeInsnID's*/0,
        GIR_ConstrainSelectedInstOperands, /*InsnID*/0,
        GIR_EraseFromParent, /*InsnID*/0,
        // GIR_Coverage, 5286,
        GIR_Done,
      // Label 5976: @436806
      GIM_Try, /*On fail goto*//*Label 5977*/ GIMT_Encode4(436883), // Rule ID 5194 //
        GIM_CheckFeatures, GIMT_Encode2(GIFBS_isGFX6GFX7GFX10),
        GIM_CheckRegBankForClass, /*MI*/0, /*Op*/0, /*RC*/GIMT_Encode2(AMDGPU::AV_64RegClassID),
        GIM_CheckConstantInt8, /*MI*/0, /*Op*/4, 0,
        // MIs[0] offset
        GIM_CheckIsImm, /*MI*/0, /*Op*/6,
        // MIs[0] auxiliary
        GIM_CheckIsImm, /*MI*/0, /*Op*/7,
        // MIs[0] Operand 8
        GIM_CheckIsImm, /*MI*/0, /*Op*/8,
        GIM_CheckComplexPattern, /*MI*/0, /*Op*/5, /*Renderer*/GIMT_Encode2(0), GIMT_Encode2(GICP_gi_buf_soffset),
        // (SIbuffer_atomic_fmax:{ *:[f64] } f64:{ *:[f64] }:$vdata_in, v4i32:{ *:[v4i32] }:$rsrc, i32:{ *:[i32] }:$vindex, 0:{ *:[i32] }, (BUFSOffset:{ *:[i32] } i32:{ *:[i32] }:$soffset), (timm:{ *:[i32] }):$offset, (timm:{ *:[i32] }):$auxiliary, (timm:{ *:[i1] }))  =>  (BUFFER_ATOMIC_FMAX_X2_IDXEN_RTN:{ *:[f64] } anonymous_15036:{ *:[f64] }:$vdata_in, VGPR_32:{ *:[i32] }:$vindex, SReg_128:{ *:[v4i32] }:$rsrc, SCSrc_b32:{ *:[i32] }:$soffset, (timm:{ *:[i32] }):$offset, (extract_cpol_set_glc:{ *:[i32] } ?:{ *:[i32] }:$auxiliary))
        GIR_BuildMI, /*InsnID*/0, /*Opcode*/GIMT_Encode2(AMDGPU::BUFFER_ATOMIC_FMAX_X2_IDXEN_RTN),
        GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/0, // DstI[vdata]
        GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/1, // vdata_in
        GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/3, // vindex
        GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/2, // rsrc
        GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/0, // soffset
        GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/6, // offset
        GIR_CustomOperandRenderer, /*InsnID*/0, /*OldInsnID*/0, /*OpIdx*/7, /*OperandRenderer*/GIMT_Encode2(GICR_renderExtractCpolSetGLC), // auxiliary
        GIR_MergeMemOperands, /*InsnID*/0, /*NumInsns*/1, /*MergeInsnID's*/0,
        GIR_ConstrainSelectedInstOperands, /*InsnID*/0,
        GIR_EraseFromParent, /*InsnID*/0,
        // GIR_Coverage, 5194,
        GIR_Done,
      // Label 5977: @436883
      GIM_Try, /*On fail goto*//*Label 5978*/ GIMT_Encode4(436960), // Rule ID 5202 //
        GIM_CheckFeatures, GIMT_Encode2(GIFBS_isGFX6GFX7GFX10),
        GIM_CheckRegBankForClass, /*MI*/0, /*Op*/0, /*RC*/GIMT_Encode2(AMDGPU::AV_64RegClassID),
        GIM_CheckConstantInt8, /*MI*/0, /*Op*/4, 0,
        // MIs[0] offset
        GIM_CheckIsImm, /*MI*/0, /*Op*/6,
        // MIs[0] auxiliary
        GIM_CheckIsImm, /*MI*/0, /*Op*/7,
        // MIs[0] Operand 8
        GIM_CheckIsImm, /*MI*/0, /*Op*/8,
        GIM_CheckComplexPattern, /*MI*/0, /*Op*/5, /*Renderer*/GIMT_Encode2(0), GIMT_Encode2(GICP_gi_buf_soffset),
        // (SIbuffer_atomic_fmax:{ *:[f64] } f64:{ *:[f64] }:$vdata_in, v4i32:{ *:[v4i32] }:$rsrc, i32:{ *:[i32] }:$vindex, 0:{ *:[i32] }, (BUFSOffset:{ *:[i32] } i32:{ *:[i32] }:$soffset), (timm:{ *:[i32] }):$offset, (timm:{ *:[i32] }):$auxiliary, (timm:{ *:[i1] }))  =>  (BUFFER_ATOMIC_FMAX_X2_VBUFFER_IDXEN_RTN:{ *:[f64] } anonymous_15036:{ *:[f64] }:$vdata_in, VGPR_32:{ *:[i32] }:$vindex, SReg_128:{ *:[v4i32] }:$rsrc, SCSrc_b32:{ *:[i32] }:$soffset, (timm:{ *:[i32] }):$offset, (extract_cpol_set_glc:{ *:[i32] } ?:{ *:[i32] }:$auxiliary))
        GIR_BuildMI, /*InsnID*/0, /*Opcode*/GIMT_Encode2(AMDGPU::BUFFER_ATOMIC_FMAX_X2_VBUFFER_IDXEN_RTN),
        GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/0, // DstI[vdata]
        GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/1, // vdata_in
        GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/3, // vindex
        GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/2, // rsrc
        GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/0, // soffset
        GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/6, // offset
        GIR_CustomOperandRenderer, /*InsnID*/0, /*OldInsnID*/0, /*OpIdx*/7, /*OperandRenderer*/GIMT_Encode2(GICR_renderExtractCpolSetGLC), // auxiliary
        GIR_MergeMemOperands, /*InsnID*/0, /*NumInsns*/1, /*MergeInsnID's*/0,
        GIR_ConstrainSelectedInstOperands, /*InsnID*/0,
        GIR_EraseFromParent, /*InsnID*/0,
        // GIR_Coverage, 5202,
        GIR_Done,
      // Label 5978: @436960
      GIM_Try, /*On fail goto*//*Label 5979*/ GIMT_Encode4(437037), // Rule ID 5274 //
        GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasUnrestrictedSOffset_isGFX90APlus),
        GIM_CheckRegBankForClass, /*MI*/0, /*Op*/0, /*RC*/GIMT_Encode2(AMDGPU::AV_64RegClassID),
        GIM_CheckConstantInt8, /*MI*/0, /*Op*/4, 0,
        // MIs[0] offset
        GIM_CheckIsImm, /*MI*/0, /*Op*/6,
        // MIs[0] auxiliary
        GIM_CheckIsImm, /*MI*/0, /*Op*/7,
        // MIs[0] Operand 8
        GIM_CheckIsImm, /*MI*/0, /*Op*/8,
        GIM_CheckComplexPattern, /*MI*/0, /*Op*/5, /*Renderer*/GIMT_Encode2(0), GIMT_Encode2(GICP_gi_buf_soffset),
        // (SIbuffer_atomic_fmax:{ *:[f64] } f64:{ *:[f64] }:$vdata_in, v4i32:{ *:[v4i32] }:$rsrc, i32:{ *:[i32] }:$vindex, 0:{ *:[i32] }, (BUFSOffset:{ *:[i32] } i32:{ *:[i32] }:$soffset), (timm:{ *:[i32] }):$offset, (timm:{ *:[i32] }):$auxiliary, (timm:{ *:[i1] }))  =>  (BUFFER_ATOMIC_MAX_F64_IDXEN_RTN:{ *:[f64] } anonymous_15036:{ *:[f64] }:$vdata_in, VGPR_32:{ *:[i32] }:$vindex, SReg_128:{ *:[v4i32] }:$rsrc, SCSrc_b32:{ *:[i32] }:$soffset, (timm:{ *:[i32] }):$offset, (extract_cpol_set_glc:{ *:[i32] } ?:{ *:[i32] }:$auxiliary))
        GIR_BuildMI, /*InsnID*/0, /*Opcode*/GIMT_Encode2(AMDGPU::BUFFER_ATOMIC_MAX_F64_IDXEN_RTN),
        GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/0, // DstI[vdata]
        GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/1, // vdata_in
        GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/3, // vindex
        GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/2, // rsrc
        GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/0, // soffset
        GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/6, // offset
        GIR_CustomOperandRenderer, /*InsnID*/0, /*OldInsnID*/0, /*OpIdx*/7, /*OperandRenderer*/GIMT_Encode2(GICR_renderExtractCpolSetGLC), // auxiliary
        GIR_MergeMemOperands, /*InsnID*/0, /*NumInsns*/1, /*MergeInsnID's*/0,
        GIR_ConstrainSelectedInstOperands, /*InsnID*/0,
        GIR_EraseFromParent, /*InsnID*/0,
        // GIR_Coverage, 5274,
        GIR_Done,
      // Label 5979: @437037
      GIM_Try, /*On fail goto*//*Label 5980*/ GIMT_Encode4(437114), // Rule ID 5282 //
        GIM_CheckFeatures, GIMT_Encode2(GIFBS_isGFX90APlus),
        GIM_CheckRegBankForClass, /*MI*/0, /*Op*/0, /*RC*/GIMT_Encode2(AMDGPU::AV_64RegClassID),
        GIM_CheckConstantInt8, /*MI*/0, /*Op*/4, 0,
        // MIs[0] offset
        GIM_CheckIsImm, /*MI*/0, /*Op*/6,
        // MIs[0] auxiliary
        GIM_CheckIsImm, /*MI*/0, /*Op*/7,
        // MIs[0] Operand 8
        GIM_CheckIsImm, /*MI*/0, /*Op*/8,
        GIM_CheckComplexPattern, /*MI*/0, /*Op*/5, /*Renderer*/GIMT_Encode2(0), GIMT_Encode2(GICP_gi_buf_soffset),
        // (SIbuffer_atomic_fmax:{ *:[f64] } f64:{ *:[f64] }:$vdata_in, v4i32:{ *:[v4i32] }:$rsrc, i32:{ *:[i32] }:$vindex, 0:{ *:[i32] }, (BUFSOffset:{ *:[i32] } i32:{ *:[i32] }:$soffset), (timm:{ *:[i32] }):$offset, (timm:{ *:[i32] }):$auxiliary, (timm:{ *:[i1] }))  =>  (BUFFER_ATOMIC_MAX_F64_VBUFFER_IDXEN_RTN:{ *:[f64] } anonymous_15036:{ *:[f64] }:$vdata_in, VGPR_32:{ *:[i32] }:$vindex, SReg_128:{ *:[v4i32] }:$rsrc, SCSrc_b32:{ *:[i32] }:$soffset, (timm:{ *:[i32] }):$offset, (extract_cpol_set_glc:{ *:[i32] } ?:{ *:[i32] }:$auxiliary))
        GIR_BuildMI, /*InsnID*/0, /*Opcode*/GIMT_Encode2(AMDGPU::BUFFER_ATOMIC_MAX_F64_VBUFFER_IDXEN_RTN),
        GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/0, // DstI[vdata]
        GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/1, // vdata_in
        GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/3, // vindex
        GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/2, // rsrc
        GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/0, // soffset
        GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/6, // offset
        GIR_CustomOperandRenderer, /*InsnID*/0, /*OldInsnID*/0, /*OpIdx*/7, /*OperandRenderer*/GIMT_Encode2(GICR_renderExtractCpolSetGLC), // auxiliary
        GIR_MergeMemOperands, /*InsnID*/0, /*NumInsns*/1, /*MergeInsnID's*/0,
        GIR_ConstrainSelectedInstOperands, /*InsnID*/0,
        GIR_EraseFromParent, /*InsnID*/0,
        // GIR_Coverage, 5282,
        GIR_Done,
      // Label 5980: @437114
      GIM_Try, /*On fail goto*//*Label 5981*/ GIMT_Encode4(437220), // Rule ID 5200 //
        GIM_CheckFeatures, GIMT_Encode2(GIFBS_isGFX6GFX7GFX10),
        GIM_CheckHasNoUse, /*MI*/0,
        // MIs[0] offset
        GIM_CheckIsImm, /*MI*/0, /*Op*/6,
        // MIs[0] auxiliary
        GIM_CheckIsImm, /*MI*/0, /*Op*/7,
        // MIs[0] Operand 8
        GIM_CheckIsImm, /*MI*/0, /*Op*/8,
        GIM_CheckComplexPattern, /*MI*/0, /*Op*/5, /*Renderer*/GIMT_Encode2(0), GIMT_Encode2(GICP_gi_buf_soffset),
        // (SIbuffer_atomic_fmax:{ *:[f64] } f64:{ *:[f64] }:$vdata_in, v4i32:{ *:[v4i32] }:$rsrc, i32:{ *:[i32] }:$vindex, i32:{ *:[i32] }:$voffset, (BUFSOffset:{ *:[i32] } i32:{ *:[i32] }:$soffset), (timm:{ *:[i32] }):$offset, (timm:{ *:[i32] }):$auxiliary, (timm:{ *:[i1] }))<<P:Predicate_SIbuffer_atomic_fmax_noret>>  =>  (BUFFER_ATOMIC_FMAX_X2_BOTHEN anonymous_15036:{ *:[f64] }:$vdata_in, (REG_SEQUENCE:{ *:[i64] } VReg_64:{ *:[i32] }, VGPR_32:{ *:[i32] }:$vindex, sub0:{ *:[i32] }, VGPR_32:{ *:[i32] }:$voffset, sub1:{ *:[i32] }), SReg_128:{ *:[v4i32] }:$rsrc, SCSrc_b32:{ *:[i32] }:$soffset, (timm:{ *:[i32] }):$offset, (extract_cpol:{ *:[i32] } ?:{ *:[i32] }:$auxiliary))
        GIR_MakeTempReg, /*TempRegID*/0, /*TypeID*/GILLT_s64,
        GIR_BuildMI, /*InsnID*/1, /*Opcode*/GIMT_Encode2(TargetOpcode::REG_SEQUENCE),
        GIR_AddTempRegister, /*InsnID*/1, /*TempRegID*/0, /*TempRegFlags*/GIMT_Encode2(RegState::Define),
        GIR_Copy, /*NewInsnID*/1, /*OldInsnID*/0, /*OpIdx*/3, // vindex
        GIR_AddImm8, /*InsnID*/1, /*SubRegIndex*/3,
        GIR_Copy, /*NewInsnID*/1, /*OldInsnID*/0, /*OpIdx*/4, // voffset
        GIR_AddImm8, /*InsnID*/1, /*SubRegIndex*/11,
        GIR_ConstrainOperandRC, /*InsnID*/1, /*Op*/0, GIMT_Encode2(AMDGPU::VReg_64RegClassID),
        GIR_ConstrainOperandRC, /*InsnID*/1, /*Op*/1, GIMT_Encode2(AMDGPU::VGPR_32RegClassID),
        GIR_ConstrainOperandRC, /*InsnID*/1, /*Op*/3, GIMT_Encode2(AMDGPU::VGPR_32RegClassID),
        GIR_BuildMI, /*InsnID*/0, /*Opcode*/GIMT_Encode2(AMDGPU::BUFFER_ATOMIC_FMAX_X2_BOTHEN),
        GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/1, // vdata_in
        GIR_AddSimpleTempRegister, /*InsnID*/0, /*TempRegID*/0,
        GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/2, // rsrc
        GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/0, // soffset
        GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/6, // offset
        GIR_CustomOperandRenderer, /*InsnID*/0, /*OldInsnID*/0, /*OpIdx*/7, /*OperandRenderer*/GIMT_Encode2(GICR_renderExtractCPol), // auxiliary
        GIR_MergeMemOperands, /*InsnID*/0, /*NumInsns*/1, /*MergeInsnID's*/0,
        GIR_ConstrainSelectedInstOperands, /*InsnID*/0,
        GIR_EraseFromParent, /*InsnID*/0,
        // GIR_Coverage, 5200,
        GIR_Done,
      // Label 5981: @437220
      GIM_Try, /*On fail goto*//*Label 5982*/ GIMT_Encode4(437326), // Rule ID 5208 //
        GIM_CheckFeatures, GIMT_Encode2(GIFBS_isGFX6GFX7GFX10),
        GIM_CheckHasNoUse, /*MI*/0,
        // MIs[0] offset
        GIM_CheckIsImm, /*MI*/0, /*Op*/6,
        // MIs[0] auxiliary
        GIM_CheckIsImm, /*MI*/0, /*Op*/7,
        // MIs[0] Operand 8
        GIM_CheckIsImm, /*MI*/0, /*Op*/8,
        GIM_CheckComplexPattern, /*MI*/0, /*Op*/5, /*Renderer*/GIMT_Encode2(0), GIMT_Encode2(GICP_gi_buf_soffset),
        // (SIbuffer_atomic_fmax:{ *:[f64] } f64:{ *:[f64] }:$vdata_in, v4i32:{ *:[v4i32] }:$rsrc, i32:{ *:[i32] }:$vindex, i32:{ *:[i32] }:$voffset, (BUFSOffset:{ *:[i32] } i32:{ *:[i32] }:$soffset), (timm:{ *:[i32] }):$offset, (timm:{ *:[i32] }):$auxiliary, (timm:{ *:[i1] }))<<P:Predicate_SIbuffer_atomic_fmax_noret>>  =>  (BUFFER_ATOMIC_FMAX_X2_VBUFFER_BOTHEN anonymous_15036:{ *:[f64] }:$vdata_in, (REG_SEQUENCE:{ *:[i64] } VReg_64:{ *:[i32] }, VGPR_32:{ *:[i32] }:$vindex, sub0:{ *:[i32] }, VGPR_32:{ *:[i32] }:$voffset, sub1:{ *:[i32] }), SReg_128:{ *:[v4i32] }:$rsrc, SCSrc_b32:{ *:[i32] }:$soffset, (timm:{ *:[i32] }):$offset, (extract_cpol:{ *:[i32] } ?:{ *:[i32] }:$auxiliary))
        GIR_MakeTempReg, /*TempRegID*/0, /*TypeID*/GILLT_s64,
        GIR_BuildMI, /*InsnID*/1, /*Opcode*/GIMT_Encode2(TargetOpcode::REG_SEQUENCE),
        GIR_AddTempRegister, /*InsnID*/1, /*TempRegID*/0, /*TempRegFlags*/GIMT_Encode2(RegState::Define),
        GIR_Copy, /*NewInsnID*/1, /*OldInsnID*/0, /*OpIdx*/3, // vindex
        GIR_AddImm8, /*InsnID*/1, /*SubRegIndex*/3,
        GIR_Copy, /*NewInsnID*/1, /*OldInsnID*/0, /*OpIdx*/4, // voffset
        GIR_AddImm8, /*InsnID*/1, /*SubRegIndex*/11,
        GIR_ConstrainOperandRC, /*InsnID*/1, /*Op*/0, GIMT_Encode2(AMDGPU::VReg_64RegClassID),
        GIR_ConstrainOperandRC, /*InsnID*/1, /*Op*/1, GIMT_Encode2(AMDGPU::VGPR_32RegClassID),
        GIR_ConstrainOperandRC, /*InsnID*/1, /*Op*/3, GIMT_Encode2(AMDGPU::VGPR_32RegClassID),
        GIR_BuildMI, /*InsnID*/0, /*Opcode*/GIMT_Encode2(AMDGPU::BUFFER_ATOMIC_FMAX_X2_VBUFFER_BOTHEN),
        GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/1, // vdata_in
        GIR_AddSimpleTempRegister, /*InsnID*/0, /*TempRegID*/0,
        GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/2, // rsrc
        GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/0, // soffset
        GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/6, // offset
        GIR_CustomOperandRenderer, /*InsnID*/0, /*OldInsnID*/0, /*OpIdx*/7, /*OperandRenderer*/GIMT_Encode2(GICR_renderExtractCPol), // auxiliary
        GIR_MergeMemOperands, /*InsnID*/0, /*NumInsns*/1, /*MergeInsnID's*/0,
        GIR_ConstrainSelectedInstOperands, /*InsnID*/0,
        GIR_EraseFromParent, /*InsnID*/0,
        // GIR_Coverage, 5208,
        GIR_Done,
      // Label 5982: @437326
      GIM_Try, /*On fail goto*//*Label 5983*/ GIMT_Encode4(437432), // Rule ID 5280 //
        GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasUnrestrictedSOffset_isGFX90APlus),
        GIM_CheckHasNoUse, /*MI*/0,
        // MIs[0] offset
        GIM_CheckIsImm, /*MI*/0, /*Op*/6,
        // MIs[0] auxiliary
        GIM_CheckIsImm, /*MI*/0, /*Op*/7,
        // MIs[0] Operand 8
        GIM_CheckIsImm, /*MI*/0, /*Op*/8,
        GIM_CheckComplexPattern, /*MI*/0, /*Op*/5, /*Renderer*/GIMT_Encode2(0), GIMT_Encode2(GICP_gi_buf_soffset),
        // (SIbuffer_atomic_fmax:{ *:[f64] } f64:{ *:[f64] }:$vdata_in, v4i32:{ *:[v4i32] }:$rsrc, i32:{ *:[i32] }:$vindex, i32:{ *:[i32] }:$voffset, (BUFSOffset:{ *:[i32] } i32:{ *:[i32] }:$soffset), (timm:{ *:[i32] }):$offset, (timm:{ *:[i32] }):$auxiliary, (timm:{ *:[i1] }))<<P:Predicate_SIbuffer_atomic_fmax_noret>>  =>  (BUFFER_ATOMIC_MAX_F64_BOTHEN anonymous_15036:{ *:[f64] }:$vdata_in, (REG_SEQUENCE:{ *:[i64] } VReg_64:{ *:[i32] }, VGPR_32:{ *:[i32] }:$vindex, sub0:{ *:[i32] }, VGPR_32:{ *:[i32] }:$voffset, sub1:{ *:[i32] }), SReg_128:{ *:[v4i32] }:$rsrc, SCSrc_b32:{ *:[i32] }:$soffset, (timm:{ *:[i32] }):$offset, (extract_cpol:{ *:[i32] } ?:{ *:[i32] }:$auxiliary))
        GIR_MakeTempReg, /*TempRegID*/0, /*TypeID*/GILLT_s64,
        GIR_BuildMI, /*InsnID*/1, /*Opcode*/GIMT_Encode2(TargetOpcode::REG_SEQUENCE),
        GIR_AddTempRegister, /*InsnID*/1, /*TempRegID*/0, /*TempRegFlags*/GIMT_Encode2(RegState::Define),
        GIR_Copy, /*NewInsnID*/1, /*OldInsnID*/0, /*OpIdx*/3, // vindex
        GIR_AddImm8, /*InsnID*/1, /*SubRegIndex*/3,
        GIR_Copy, /*NewInsnID*/1, /*OldInsnID*/0, /*OpIdx*/4, // voffset
        GIR_AddImm8, /*InsnID*/1, /*SubRegIndex*/11,
        GIR_ConstrainOperandRC, /*InsnID*/1, /*Op*/0, GIMT_Encode2(AMDGPU::VReg_64RegClassID),
        GIR_ConstrainOperandRC, /*InsnID*/1, /*Op*/1, GIMT_Encode2(AMDGPU::VGPR_32RegClassID),
        GIR_ConstrainOperandRC, /*InsnID*/1, /*Op*/3, GIMT_Encode2(AMDGPU::VGPR_32RegClassID),
        GIR_BuildMI, /*InsnID*/0, /*Opcode*/GIMT_Encode2(AMDGPU::BUFFER_ATOMIC_MAX_F64_BOTHEN),
        GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/1, // vdata_in
        GIR_AddSimpleTempRegister, /*InsnID*/0, /*TempRegID*/0,
        GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/2, // rsrc
        GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/0, // soffset
        GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/6, // offset
        GIR_CustomOperandRenderer, /*InsnID*/0, /*OldInsnID*/0, /*OpIdx*/7, /*OperandRenderer*/GIMT_Encode2(GICR_renderExtractCPol), // auxiliary
        GIR_MergeMemOperands, /*InsnID*/0, /*NumInsns*/1, /*MergeInsnID's*/0,
        GIR_ConstrainSelectedInstOperands, /*InsnID*/0,
        GIR_EraseFromParent, /*InsnID*/0,
        // GIR_Coverage, 5280,
        GIR_Done,
      // Label 5983: @437432
      GIM_Try, /*On fail goto*//*Label 5984*/ GIMT_Encode4(437538), // Rule ID 5288 //
        GIM_CheckFeatures, GIMT_Encode2(GIFBS_isGFX90APlus),
        GIM_CheckHasNoUse, /*MI*/0,
        // MIs[0] offset
        GIM_CheckIsImm, /*MI*/0, /*Op*/6,
        // MIs[0] auxiliary
        GIM_CheckIsImm, /*MI*/0, /*Op*/7,
        // MIs[0] Operand 8
        GIM_CheckIsImm, /*MI*/0, /*Op*/8,
        GIM_CheckComplexPattern, /*MI*/0, /*Op*/5, /*Renderer*/GIMT_Encode2(0), GIMT_Encode2(GICP_gi_buf_soffset),
        // (SIbuffer_atomic_fmax:{ *:[f64] } f64:{ *:[f64] }:$vdata_in, v4i32:{ *:[v4i32] }:$rsrc, i32:{ *:[i32] }:$vindex, i32:{ *:[i32] }:$voffset, (BUFSOffset:{ *:[i32] } i32:{ *:[i32] }:$soffset), (timm:{ *:[i32] }):$offset, (timm:{ *:[i32] }):$auxiliary, (timm:{ *:[i1] }))<<P:Predicate_SIbuffer_atomic_fmax_noret>>  =>  (BUFFER_ATOMIC_MAX_F64_VBUFFER_BOTHEN anonymous_15036:{ *:[f64] }:$vdata_in, (REG_SEQUENCE:{ *:[i64] } VReg_64:{ *:[i32] }, VGPR_32:{ *:[i32] }:$vindex, sub0:{ *:[i32] }, VGPR_32:{ *:[i32] }:$voffset, sub1:{ *:[i32] }), SReg_128:{ *:[v4i32] }:$rsrc, SCSrc_b32:{ *:[i32] }:$soffset, (timm:{ *:[i32] }):$offset, (extract_cpol:{ *:[i32] } ?:{ *:[i32] }:$auxiliary))
        GIR_MakeTempReg, /*TempRegID*/0, /*TypeID*/GILLT_s64,
        GIR_BuildMI, /*InsnID*/1, /*Opcode*/GIMT_Encode2(TargetOpcode::REG_SEQUENCE),
        GIR_AddTempRegister, /*InsnID*/1, /*TempRegID*/0, /*TempRegFlags*/GIMT_Encode2(RegState::Define),
        GIR_Copy, /*NewInsnID*/1, /*OldInsnID*/0, /*OpIdx*/3, // vindex
        GIR_AddImm8, /*InsnID*/1, /*SubRegIndex*/3,
        GIR_Copy, /*NewInsnID*/1, /*OldInsnID*/0, /*OpIdx*/4, // voffset
        GIR_AddImm8, /*InsnID*/1, /*SubRegIndex*/11,
        GIR_ConstrainOperandRC, /*InsnID*/1, /*Op*/0, GIMT_Encode2(AMDGPU::VReg_64RegClassID),
        GIR_ConstrainOperandRC, /*InsnID*/1, /*Op*/1, GIMT_Encode2(AMDGPU::VGPR_32RegClassID),
        GIR_ConstrainOperandRC, /*InsnID*/1, /*Op*/3, GIMT_Encode2(AMDGPU::VGPR_32RegClassID),
        GIR_BuildMI, /*InsnID*/0, /*Opcode*/GIMT_Encode2(AMDGPU::BUFFER_ATOMIC_MAX_F64_VBUFFER_BOTHEN),
        GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/1, // vdata_in
        GIR_AddSimpleTempRegister, /*InsnID*/0, /*TempRegID*/0,
        GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/2, // rsrc
        GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/0, // soffset
        GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/6, // offset
        GIR_CustomOperandRenderer, /*InsnID*/0, /*OldInsnID*/0, /*OpIdx*/7, /*OperandRenderer*/GIMT_Encode2(GICR_renderExtractCPol), // auxiliary
        GIR_MergeMemOperands, /*InsnID*/0, /*NumInsns*/1, /*MergeInsnID's*/0,
        GIR_ConstrainSelectedInstOperands, /*InsnID*/0,
        GIR_EraseFromParent, /*InsnID*/0,
        // GIR_Coverage, 5288,
        GIR_Done,
      // Label 5984: @437538
      GIM_Try, /*On fail goto*//*Label 5985*/ GIMT_Encode4(437651), // Rule ID 5196 //
        GIM_CheckFeatures, GIMT_Encode2(GIFBS_isGFX6GFX7GFX10),
        GIM_CheckRegBankForClass, /*MI*/0, /*Op*/0, /*RC*/GIMT_Encode2(AMDGPU::AV_64RegClassID),
        // MIs[0] offset
        GIM_CheckIsImm, /*MI*/0, /*Op*/6,
        // MIs[0] auxiliary
        GIM_CheckIsImm, /*MI*/0, /*Op*/7,
        // MIs[0] Operand 8
        GIM_CheckIsImm, /*MI*/0, /*Op*/8,
        GIM_CheckComplexPattern, /*MI*/0, /*Op*/5, /*Renderer*/GIMT_Encode2(0), GIMT_Encode2(GICP_gi_buf_soffset),
        // (SIbuffer_atomic_fmax:{ *:[f64] } f64:{ *:[f64] }:$vdata_in, v4i32:{ *:[v4i32] }:$rsrc, i32:{ *:[i32] }:$vindex, i32:{ *:[i32] }:$voffset, (BUFSOffset:{ *:[i32] } i32:{ *:[i32] }:$soffset), (timm:{ *:[i32] }):$offset, (timm:{ *:[i32] }):$auxiliary, (timm:{ *:[i1] }))  =>  (BUFFER_ATOMIC_FMAX_X2_BOTHEN_RTN:{ *:[f64] } anonymous_15036:{ *:[f64] }:$vdata_in, (REG_SEQUENCE:{ *:[i64] } VReg_64:{ *:[i32] }, VGPR_32:{ *:[i32] }:$vindex, sub0:{ *:[i32] }, VGPR_32:{ *:[i32] }:$voffset, sub1:{ *:[i32] }), SReg_128:{ *:[v4i32] }:$rsrc, SCSrc_b32:{ *:[i32] }:$soffset, (timm:{ *:[i32] }):$offset, (extract_cpol_set_glc:{ *:[i32] } ?:{ *:[i32] }:$auxiliary))
        GIR_MakeTempReg, /*TempRegID*/0, /*TypeID*/GILLT_s64,
        GIR_BuildMI, /*InsnID*/1, /*Opcode*/GIMT_Encode2(TargetOpcode::REG_SEQUENCE),
        GIR_AddTempRegister, /*InsnID*/1, /*TempRegID*/0, /*TempRegFlags*/GIMT_Encode2(RegState::Define),
        GIR_Copy, /*NewInsnID*/1, /*OldInsnID*/0, /*OpIdx*/3, // vindex
        GIR_AddImm8, /*InsnID*/1, /*SubRegIndex*/3,
        GIR_Copy, /*NewInsnID*/1, /*OldInsnID*/0, /*OpIdx*/4, // voffset
        GIR_AddImm8, /*InsnID*/1, /*SubRegIndex*/11,
        GIR_ConstrainOperandRC, /*InsnID*/1, /*Op*/0, GIMT_Encode2(AMDGPU::VReg_64RegClassID),
        GIR_ConstrainOperandRC, /*InsnID*/1, /*Op*/1, GIMT_Encode2(AMDGPU::VGPR_32RegClassID),
        GIR_ConstrainOperandRC, /*InsnID*/1, /*Op*/3, GIMT_Encode2(AMDGPU::VGPR_32RegClassID),
        GIR_BuildMI, /*InsnID*/0, /*Opcode*/GIMT_Encode2(AMDGPU::BUFFER_ATOMIC_FMAX_X2_BOTHEN_RTN),
        GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/0, // DstI[vdata]
        GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/1, // vdata_in
        GIR_AddSimpleTempRegister, /*InsnID*/0, /*TempRegID*/0,
        GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/2, // rsrc
        GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/0, // soffset
        GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/6, // offset
        GIR_CustomOperandRenderer, /*InsnID*/0, /*OldInsnID*/0, /*OpIdx*/7, /*OperandRenderer*/GIMT_Encode2(GICR_renderExtractCpolSetGLC), // auxiliary
        GIR_MergeMemOperands, /*InsnID*/0, /*NumInsns*/1, /*MergeInsnID's*/0,
        GIR_ConstrainSelectedInstOperands, /*InsnID*/0,
        GIR_EraseFromParent, /*InsnID*/0,
        // GIR_Coverage, 5196,
        GIR_Done,
      // Label 5985: @437651
      GIM_Try, /*On fail goto*//*Label 5986*/ GIMT_Encode4(437764), // Rule ID 5204 //
        GIM_CheckFeatures, GIMT_Encode2(GIFBS_isGFX6GFX7GFX10),
        GIM_CheckRegBankForClass, /*MI*/0, /*Op*/0, /*RC*/GIMT_Encode2(AMDGPU::AV_64RegClassID),
        // MIs[0] offset
        GIM_CheckIsImm, /*MI*/0, /*Op*/6,
        // MIs[0] auxiliary
        GIM_CheckIsImm, /*MI*/0, /*Op*/7,
        // MIs[0] Operand 8
        GIM_CheckIsImm, /*MI*/0, /*Op*/8,
        GIM_CheckComplexPattern, /*MI*/0, /*Op*/5, /*Renderer*/GIMT_Encode2(0), GIMT_Encode2(GICP_gi_buf_soffset),
        // (SIbuffer_atomic_fmax:{ *:[f64] } f64:{ *:[f64] }:$vdata_in, v4i32:{ *:[v4i32] }:$rsrc, i32:{ *:[i32] }:$vindex, i32:{ *:[i32] }:$voffset, (BUFSOffset:{ *:[i32] } i32:{ *:[i32] }:$soffset), (timm:{ *:[i32] }):$offset, (timm:{ *:[i32] }):$auxiliary, (timm:{ *:[i1] }))  =>  (BUFFER_ATOMIC_FMAX_X2_VBUFFER_BOTHEN_RTN:{ *:[f64] } anonymous_15036:{ *:[f64] }:$vdata_in, (REG_SEQUENCE:{ *:[i64] } VReg_64:{ *:[i32] }, VGPR_32:{ *:[i32] }:$vindex, sub0:{ *:[i32] }, VGPR_32:{ *:[i32] }:$voffset, sub1:{ *:[i32] }), SReg_128:{ *:[v4i32] }:$rsrc, SCSrc_b32:{ *:[i32] }:$soffset, (timm:{ *:[i32] }):$offset, (extract_cpol_set_glc:{ *:[i32] } ?:{ *:[i32] }:$auxiliary))
        GIR_MakeTempReg, /*TempRegID*/0, /*TypeID*/GILLT_s64,
        GIR_BuildMI, /*InsnID*/1, /*Opcode*/GIMT_Encode2(TargetOpcode::REG_SEQUENCE),
        GIR_AddTempRegister, /*InsnID*/1, /*TempRegID*/0, /*TempRegFlags*/GIMT_Encode2(RegState::Define),
        GIR_Copy, /*NewInsnID*/1, /*OldInsnID*/0, /*OpIdx*/3, // vindex
        GIR_AddImm8, /*InsnID*/1, /*SubRegIndex*/3,
        GIR_Copy, /*NewInsnID*/1, /*OldInsnID*/0, /*OpIdx*/4, // voffset
        GIR_AddImm8, /*InsnID*/1, /*SubRegIndex*/11,
        GIR_ConstrainOperandRC, /*InsnID*/1, /*Op*/0, GIMT_Encode2(AMDGPU::VReg_64RegClassID),
        GIR_ConstrainOperandRC, /*InsnID*/1, /*Op*/1, GIMT_Encode2(AMDGPU::VGPR_32RegClassID),
        GIR_ConstrainOperandRC, /*InsnID*/1, /*Op*/3, GIMT_Encode2(AMDGPU::VGPR_32RegClassID),
        GIR_BuildMI, /*InsnID*/0, /*Opcode*/GIMT_Encode2(AMDGPU::BUFFER_ATOMIC_FMAX_X2_VBUFFER_BOTHEN_RTN),
        GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/0, // DstI[vdata]
        GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/1, // vdata_in
        GIR_AddSimpleTempRegister, /*InsnID*/0, /*TempRegID*/0,
        GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/2, // rsrc
        GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/0, // soffset
        GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/6, // offset
        GIR_CustomOperandRenderer, /*InsnID*/0, /*OldInsnID*/0, /*OpIdx*/7, /*OperandRenderer*/GIMT_Encode2(GICR_renderExtractCpolSetGLC), // auxiliary
        GIR_MergeMemOperands, /*InsnID*/0, /*NumInsns*/1, /*MergeInsnID's*/0,
        GIR_ConstrainSelectedInstOperands, /*InsnID*/0,
        GIR_EraseFromParent, /*InsnID*/0,
        // GIR_Coverage, 5204,
        GIR_Done,
      // Label 5986: @437764
      GIM_Try, /*On fail goto*//*Label 5987*/ GIMT_Encode4(437877), // Rule ID 5276 //
        GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasUnrestrictedSOffset_isGFX90APlus),
        GIM_CheckRegBankForClass, /*MI*/0, /*Op*/0, /*RC*/GIMT_Encode2(AMDGPU::AV_64RegClassID),
        // MIs[0] offset
        GIM_CheckIsImm, /*MI*/0, /*Op*/6,
        // MIs[0] auxiliary
        GIM_CheckIsImm, /*MI*/0, /*Op*/7,
        // MIs[0] Operand 8
        GIM_CheckIsImm, /*MI*/0, /*Op*/8,
        GIM_CheckComplexPattern, /*MI*/0, /*Op*/5, /*Renderer*/GIMT_Encode2(0), GIMT_Encode2(GICP_gi_buf_soffset),
        // (SIbuffer_atomic_fmax:{ *:[f64] } f64:{ *:[f64] }:$vdata_in, v4i32:{ *:[v4i32] }:$rsrc, i32:{ *:[i32] }:$vindex, i32:{ *:[i32] }:$voffset, (BUFSOffset:{ *:[i32] } i32:{ *:[i32] }:$soffset), (timm:{ *:[i32] }):$offset, (timm:{ *:[i32] }):$auxiliary, (timm:{ *:[i1] }))  =>  (BUFFER_ATOMIC_MAX_F64_BOTHEN_RTN:{ *:[f64] } anonymous_15036:{ *:[f64] }:$vdata_in, (REG_SEQUENCE:{ *:[i64] } VReg_64:{ *:[i32] }, VGPR_32:{ *:[i32] }:$vindex, sub0:{ *:[i32] }, VGPR_32:{ *:[i32] }:$voffset, sub1:{ *:[i32] }), SReg_128:{ *:[v4i32] }:$rsrc, SCSrc_b32:{ *:[i32] }:$soffset, (timm:{ *:[i32] }):$offset, (extract_cpol_set_glc:{ *:[i32] } ?:{ *:[i32] }:$auxiliary))
        GIR_MakeTempReg, /*TempRegID*/0, /*TypeID*/GILLT_s64,
        GIR_BuildMI, /*InsnID*/1, /*Opcode*/GIMT_Encode2(TargetOpcode::REG_SEQUENCE),
        GIR_AddTempRegister, /*InsnID*/1, /*TempRegID*/0, /*TempRegFlags*/GIMT_Encode2(RegState::Define),
        GIR_Copy, /*NewInsnID*/1, /*OldInsnID*/0, /*OpIdx*/3, // vindex
        GIR_AddImm8, /*InsnID*/1, /*SubRegIndex*/3,
        GIR_Copy, /*NewInsnID*/1, /*OldInsnID*/0, /*OpIdx*/4, // voffset
        GIR_AddImm8, /*InsnID*/1, /*SubRegIndex*/11,
        GIR_ConstrainOperandRC, /*InsnID*/1, /*Op*/0, GIMT_Encode2(AMDGPU::VReg_64RegClassID),
        GIR_ConstrainOperandRC, /*InsnID*/1, /*Op*/1, GIMT_Encode2(AMDGPU::VGPR_32RegClassID),
        GIR_ConstrainOperandRC, /*InsnID*/1, /*Op*/3, GIMT_Encode2(AMDGPU::VGPR_32RegClassID),
        GIR_BuildMI, /*InsnID*/0, /*Opcode*/GIMT_Encode2(AMDGPU::BUFFER_ATOMIC_MAX_F64_BOTHEN_RTN),
        GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/0, // DstI[vdata]
        GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/1, // vdata_in
        GIR_AddSimpleTempRegister, /*InsnID*/0, /*TempRegID*/0,
        GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/2, // rsrc
        GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/0, // soffset
        GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/6, // offset
        GIR_CustomOperandRenderer, /*InsnID*/0, /*OldInsnID*/0, /*OpIdx*/7, /*OperandRenderer*/GIMT_Encode2(GICR_renderExtractCpolSetGLC), // auxiliary
        GIR_MergeMemOperands, /*InsnID*/0, /*NumInsns*/1, /*MergeInsnID's*/0,
        GIR_ConstrainSelectedInstOperands, /*InsnID*/0,
        GIR_EraseFromParent, /*InsnID*/0,
        // GIR_Coverage, 5276,
        GIR_Done,
      // Label 5987: @437877
      GIM_Try, /*On fail goto*//*Label 5988*/ GIMT_Encode4(437990), // Rule ID 5284 //
        GIM_CheckFeatures, GIMT_Encode2(GIFBS_isGFX90APlus),
        GIM_CheckRegBankForClass, /*MI*/0, /*Op*/0, /*RC*/GIMT_Encode2(AMDGPU::AV_64RegClassID),
        // MIs[0] offset
        GIM_CheckIsImm, /*MI*/0, /*Op*/6,
        // MIs[0] auxiliary
        GIM_CheckIsImm, /*MI*/0, /*Op*/7,
        // MIs[0] Operand 8
        GIM_CheckIsImm, /*MI*/0, /*Op*/8,
        GIM_CheckComplexPattern, /*MI*/0, /*Op*/5, /*Renderer*/GIMT_Encode2(0), GIMT_Encode2(GICP_gi_buf_soffset),
        // (SIbuffer_atomic_fmax:{ *:[f64] } f64:{ *:[f64] }:$vdata_in, v4i32:{ *:[v4i32] }:$rsrc, i32:{ *:[i32] }:$vindex, i32:{ *:[i32] }:$voffset, (BUFSOffset:{ *:[i32] } i32:{ *:[i32] }:$soffset), (timm:{ *:[i32] }):$offset, (timm:{ *:[i32] }):$auxiliary, (timm:{ *:[i1] }))  =>  (BUFFER_ATOMIC_MAX_F64_VBUFFER_BOTHEN_RTN:{ *:[f64] } anonymous_15036:{ *:[f64] }:$vdata_in, (REG_SEQUENCE:{ *:[i64] } VReg_64:{ *:[i32] }, VGPR_32:{ *:[i32] }:$vindex, sub0:{ *:[i32] }, VGPR_32:{ *:[i32] }:$voffset, sub1:{ *:[i32] }), SReg_128:{ *:[v4i32] }:$rsrc, SCSrc_b32:{ *:[i32] }:$soffset, (timm:{ *:[i32] }):$offset, (extract_cpol_set_glc:{ *:[i32] } ?:{ *:[i32] }:$auxiliary))
        GIR_MakeTempReg, /*TempRegID*/0, /*TypeID*/GILLT_s64,
        GIR_BuildMI, /*InsnID*/1, /*Opcode*/GIMT_Encode2(TargetOpcode::REG_SEQUENCE),
        GIR_AddTempRegister, /*InsnID*/1, /*TempRegID*/0, /*TempRegFlags*/GIMT_Encode2(RegState::Define),
        GIR_Copy, /*NewInsnID*/1, /*OldInsnID*/0, /*OpIdx*/3, // vindex
        GIR_AddImm8, /*InsnID*/1, /*SubRegIndex*/3,
        GIR_Copy, /*NewInsnID*/1, /*OldInsnID*/0, /*OpIdx*/4, // voffset
        GIR_AddImm8, /*InsnID*/1, /*SubRegIndex*/11,
        GIR_ConstrainOperandRC, /*InsnID*/1, /*Op*/0, GIMT_Encode2(AMDGPU::VReg_64RegClassID),
        GIR_ConstrainOperandRC, /*InsnID*/1, /*Op*/1, GIMT_Encode2(AMDGPU::VGPR_32RegClassID),
        GIR_ConstrainOperandRC, /*InsnID*/1, /*Op*/3, GIMT_Encode2(AMDGPU::VGPR_32RegClassID),
        GIR_BuildMI, /*InsnID*/0, /*Opcode*/GIMT_Encode2(AMDGPU::BUFFER_ATOMIC_MAX_F64_VBUFFER_BOTHEN_RTN),
        GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/0, // DstI[vdata]
        GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/1, // vdata_in
        GIR_AddSimpleTempRegister, /*InsnID*/0, /*TempRegID*/0,
        GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/2, // rsrc
        GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/0, // soffset
        GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/6, // offset
        GIR_CustomOperandRenderer, /*InsnID*/0, /*OldInsnID*/0, /*OpIdx*/7, /*OperandRenderer*/GIMT_Encode2(GICR_renderExtractCpolSetGLC), // auxiliary
        GIR_MergeMemOperands, /*InsnID*/0, /*NumInsns*/1, /*MergeInsnID's*/0,
        GIR_ConstrainSelectedInstOperands, /*InsnID*/0,
        GIR_EraseFromParent, /*InsnID*/0,
        // GIR_Coverage, 5284,
        GIR_Done,
      // Label 5988: @437990
      GIM_Reject,
    // Label 5956: @437991
    GIM_Reject,
    // Label 5938: @437992
    GIM_Reject,
    // Label 114: @437993
    GIM_SwitchType, /*MI*/0, /*Op*/0, /*[*/GIMT_Encode2(9), GIMT_Encode2(11), /*)*//*default:*//*Label 5991*/ GIMT_Encode4(442218),
    /*GILLT_s32*//*Label 5989*/ GIMT_Encode4(438012),
    /*GILLT_s64*//*Label 5990*/ GIMT_Encode4(439423),
    // Label 5989: @438012
    GIM_Try, /*On fail goto*//*Label 5992*/ GIMT_Encode4(439422),
      GIM_CheckType, /*MI*/0, /*Op*/1, /*Type*/GILLT_s32,
      GIM_CheckType, /*MI*/0, /*Op*/2, /*Type*/GILLT_v4s32,
      GIM_CheckType, /*MI*/0, /*Op*/3, /*Type*/GILLT_s32,
      GIM_CheckType, /*MI*/0, /*Op*/4, /*Type*/GILLT_s32,
      GIM_CheckType, /*MI*/0, /*Op*/5, /*Type*/GILLT_s32,
      GIM_Try, /*On fail goto*//*Label 5993*/ GIMT_Encode4(438115), // Rule ID 5149 //
        GIM_CheckFeatures, GIMT_Encode2(GIFBS_isGFX6GFX7GFX10Plus),
        GIM_CheckHasNoUse, /*MI*/0,
        GIM_CheckConstantInt8, /*MI*/0, /*Op*/3, 0,
        GIM_CheckConstantInt8, /*MI*/0, /*Op*/4, 0,
        // MIs[0] offset
        GIM_CheckIsImm, /*MI*/0, /*Op*/6,
        // MIs[0] auxiliary
        GIM_CheckIsImm, /*MI*/0, /*Op*/7,
        // MIs[0] Operand 8
        GIM_CheckLiteralInt, /*MI*/0, /*Op*/8, GIMT_Encode8(0),
        GIM_CheckComplexPattern, /*MI*/0, /*Op*/5, /*Renderer*/GIMT_Encode2(0), GIMT_Encode2(GICP_gi_buf_soffset),
        // (SIbuffer_atomic_fmin:{ *:[f32] } f32:{ *:[f32] }:$vdata_in, v4i32:{ *:[v4i32] }:$rsrc, 0:{ *:[i32] }, 0:{ *:[i32] }, (BUFSOffset:{ *:[i32] } i32:{ *:[i32] }:$soffset), (timm:{ *:[i32] }):$offset, (timm:{ *:[i32] }):$auxiliary, 0:{ *:[i1] })<<P:Predicate_SIbuffer_atomic_fmin_noret>>  =>  (BUFFER_ATOMIC_FMIN_OFFSET anonymous_15037:{ *:[f32] }:$vdata_in, SReg_128:{ *:[v4i32] }:$rsrc, SCSrc_b32:{ *:[i32] }:$soffset, (timm:{ *:[i32] }):$offset, (extract_cpol:{ *:[i32] } ?:{ *:[i32] }:$auxiliary))
        GIR_BuildMI, /*InsnID*/0, /*Opcode*/GIMT_Encode2(AMDGPU::BUFFER_ATOMIC_FMIN_OFFSET),
        GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/1, // vdata_in
        GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/2, // rsrc
        GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/0, // soffset
        GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/6, // offset
        GIR_CustomOperandRenderer, /*InsnID*/0, /*OldInsnID*/0, /*OpIdx*/7, /*OperandRenderer*/GIMT_Encode2(GICR_renderExtractCPol), // auxiliary
        GIR_MergeMemOperands, /*InsnID*/0, /*NumInsns*/1, /*MergeInsnID's*/0,
        GIR_ConstrainSelectedInstOperands, /*InsnID*/0,
        GIR_EraseFromParent, /*InsnID*/0,
        // GIR_Coverage, 5149,
        GIR_Done,
      // Label 5993: @438115
      GIM_Try, /*On fail goto*//*Label 5994*/ GIMT_Encode4(438193), // Rule ID 5157 //
        GIM_CheckFeatures, GIMT_Encode2(GIFBS_isGFX6GFX7GFX10Plus),
        GIM_CheckHasNoUse, /*MI*/0,
        GIM_CheckConstantInt8, /*MI*/0, /*Op*/3, 0,
        GIM_CheckConstantInt8, /*MI*/0, /*Op*/4, 0,
        // MIs[0] offset
        GIM_CheckIsImm, /*MI*/0, /*Op*/6,
        // MIs[0] auxiliary
        GIM_CheckIsImm, /*MI*/0, /*Op*/7,
        // MIs[0] Operand 8
        GIM_CheckLiteralInt, /*MI*/0, /*Op*/8, GIMT_Encode8(0),
        GIM_CheckComplexPattern, /*MI*/0, /*Op*/5, /*Renderer*/GIMT_Encode2(0), GIMT_Encode2(GICP_gi_buf_soffset),
        // (SIbuffer_atomic_fmin:{ *:[f32] } f32:{ *:[f32] }:$vdata_in, v4i32:{ *:[v4i32] }:$rsrc, 0:{ *:[i32] }, 0:{ *:[i32] }, (BUFSOffset:{ *:[i32] } i32:{ *:[i32] }:$soffset), (timm:{ *:[i32] }):$offset, (timm:{ *:[i32] }):$auxiliary, 0:{ *:[i1] })<<P:Predicate_SIbuffer_atomic_fmin_noret>>  =>  (BUFFER_ATOMIC_FMIN_VBUFFER_OFFSET anonymous_15037:{ *:[f32] }:$vdata_in, SReg_128:{ *:[v4i32] }:$rsrc, SCSrc_b32:{ *:[i32] }:$soffset, (timm:{ *:[i32] }):$offset, (extract_cpol:{ *:[i32] } ?:{ *:[i32] }:$auxiliary))
        GIR_BuildMI, /*InsnID*/0, /*Opcode*/GIMT_Encode2(AMDGPU::BUFFER_ATOMIC_FMIN_VBUFFER_OFFSET),
        GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/1, // vdata_in
        GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/2, // rsrc
        GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/0, // soffset
        GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/6, // offset
        GIR_CustomOperandRenderer, /*InsnID*/0, /*OldInsnID*/0, /*OpIdx*/7, /*OperandRenderer*/GIMT_Encode2(GICR_renderExtractCPol), // auxiliary
        GIR_MergeMemOperands, /*InsnID*/0, /*NumInsns*/1, /*MergeInsnID's*/0,
        GIR_ConstrainSelectedInstOperands, /*InsnID*/0,
        GIR_EraseFromParent, /*InsnID*/0,
        // GIR_Coverage, 5157,
        GIR_Done,
      // Label 5994: @438193
      GIM_Try, /*On fail goto*//*Label 5995*/ GIMT_Encode4(438278), // Rule ID 5145 //
        GIM_CheckFeatures, GIMT_Encode2(GIFBS_isGFX6GFX7GFX10Plus),
        GIM_CheckRegBankForClass, /*MI*/0, /*Op*/0, /*RC*/GIMT_Encode2(AMDGPU::AV_32RegClassID),
        GIM_CheckConstantInt8, /*MI*/0, /*Op*/3, 0,
        GIM_CheckConstantInt8, /*MI*/0, /*Op*/4, 0,
        // MIs[0] offset
        GIM_CheckIsImm, /*MI*/0, /*Op*/6,
        // MIs[0] auxiliary
        GIM_CheckIsImm, /*MI*/0, /*Op*/7,
        // MIs[0] Operand 8
        GIM_CheckLiteralInt, /*MI*/0, /*Op*/8, GIMT_Encode8(0),
        GIM_CheckComplexPattern, /*MI*/0, /*Op*/5, /*Renderer*/GIMT_Encode2(0), GIMT_Encode2(GICP_gi_buf_soffset),
        // (SIbuffer_atomic_fmin:{ *:[f32] } f32:{ *:[f32] }:$vdata_in, v4i32:{ *:[v4i32] }:$rsrc, 0:{ *:[i32] }, 0:{ *:[i32] }, (BUFSOffset:{ *:[i32] } i32:{ *:[i32] }:$soffset), (timm:{ *:[i32] }):$offset, (timm:{ *:[i32] }):$auxiliary, 0:{ *:[i1] })  =>  (BUFFER_ATOMIC_FMIN_OFFSET_RTN:{ *:[f32] } anonymous_15037:{ *:[f32] }:$vdata_in, SReg_128:{ *:[v4i32] }:$rsrc, SCSrc_b32:{ *:[i32] }:$soffset, (timm:{ *:[i32] }):$offset, (extract_cpol_set_glc:{ *:[i32] } ?:{ *:[i32] }:$auxiliary))
        GIR_BuildMI, /*InsnID*/0, /*Opcode*/GIMT_Encode2(AMDGPU::BUFFER_ATOMIC_FMIN_OFFSET_RTN),
        GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/0, // DstI[vdata]
        GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/1, // vdata_in
        GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/2, // rsrc
        GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/0, // soffset
        GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/6, // offset
        GIR_CustomOperandRenderer, /*InsnID*/0, /*OldInsnID*/0, /*OpIdx*/7, /*OperandRenderer*/GIMT_Encode2(GICR_renderExtractCpolSetGLC), // auxiliary
        GIR_MergeMemOperands, /*InsnID*/0, /*NumInsns*/1, /*MergeInsnID's*/0,
        GIR_ConstrainSelectedInstOperands, /*InsnID*/0,
        GIR_EraseFromParent, /*InsnID*/0,
        // GIR_Coverage, 5145,
        GIR_Done,
      // Label 5995: @438278
      GIM_Try, /*On fail goto*//*Label 5996*/ GIMT_Encode4(438363), // Rule ID 5153 //
        GIM_CheckFeatures, GIMT_Encode2(GIFBS_isGFX6GFX7GFX10Plus),
        GIM_CheckRegBankForClass, /*MI*/0, /*Op*/0, /*RC*/GIMT_Encode2(AMDGPU::AV_32RegClassID),
        GIM_CheckConstantInt8, /*MI*/0, /*Op*/3, 0,
        GIM_CheckConstantInt8, /*MI*/0, /*Op*/4, 0,
        // MIs[0] offset
        GIM_CheckIsImm, /*MI*/0, /*Op*/6,
        // MIs[0] auxiliary
        GIM_CheckIsImm, /*MI*/0, /*Op*/7,
        // MIs[0] Operand 8
        GIM_CheckLiteralInt, /*MI*/0, /*Op*/8, GIMT_Encode8(0),
        GIM_CheckComplexPattern, /*MI*/0, /*Op*/5, /*Renderer*/GIMT_Encode2(0), GIMT_Encode2(GICP_gi_buf_soffset),
        // (SIbuffer_atomic_fmin:{ *:[f32] } f32:{ *:[f32] }:$vdata_in, v4i32:{ *:[v4i32] }:$rsrc, 0:{ *:[i32] }, 0:{ *:[i32] }, (BUFSOffset:{ *:[i32] } i32:{ *:[i32] }:$soffset), (timm:{ *:[i32] }):$offset, (timm:{ *:[i32] }):$auxiliary, 0:{ *:[i1] })  =>  (BUFFER_ATOMIC_FMIN_VBUFFER_OFFSET_RTN:{ *:[f32] } anonymous_15037:{ *:[f32] }:$vdata_in, SReg_128:{ *:[v4i32] }:$rsrc, SCSrc_b32:{ *:[i32] }:$soffset, (timm:{ *:[i32] }):$offset, (extract_cpol_set_glc:{ *:[i32] } ?:{ *:[i32] }:$auxiliary))
        GIR_BuildMI, /*InsnID*/0, /*Opcode*/GIMT_Encode2(AMDGPU::BUFFER_ATOMIC_FMIN_VBUFFER_OFFSET_RTN),
        GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/0, // DstI[vdata]
        GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/1, // vdata_in
        GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/2, // rsrc
        GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/0, // soffset
        GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/6, // offset
        GIR_CustomOperandRenderer, /*InsnID*/0, /*OldInsnID*/0, /*OpIdx*/7, /*OperandRenderer*/GIMT_Encode2(GICR_renderExtractCpolSetGLC), // auxiliary
        GIR_MergeMemOperands, /*InsnID*/0, /*NumInsns*/1, /*MergeInsnID's*/0,
        GIR_ConstrainSelectedInstOperands, /*InsnID*/0,
        GIR_EraseFromParent, /*InsnID*/0,
        // GIR_Coverage, 5153,
        GIR_Done,
      // Label 5996: @438363
      GIM_Try, /*On fail goto*//*Label 5997*/ GIMT_Encode4(438441), // Rule ID 5151 //
        GIM_CheckFeatures, GIMT_Encode2(GIFBS_isGFX6GFX7GFX10Plus),
        GIM_CheckHasNoUse, /*MI*/0,
        GIM_CheckConstantInt8, /*MI*/0, /*Op*/3, 0,
        // MIs[0] offset
        GIM_CheckIsImm, /*MI*/0, /*Op*/6,
        // MIs[0] auxiliary
        GIM_CheckIsImm, /*MI*/0, /*Op*/7,
        // MIs[0] Operand 8
        GIM_CheckLiteralInt, /*MI*/0, /*Op*/8, GIMT_Encode8(0),
        GIM_CheckComplexPattern, /*MI*/0, /*Op*/5, /*Renderer*/GIMT_Encode2(0), GIMT_Encode2(GICP_gi_buf_soffset),
        // (SIbuffer_atomic_fmin:{ *:[f32] } f32:{ *:[f32] }:$vdata_in, v4i32:{ *:[v4i32] }:$rsrc, 0:{ *:[i32] }, i32:{ *:[i32] }:$voffset, (BUFSOffset:{ *:[i32] } i32:{ *:[i32] }:$soffset), (timm:{ *:[i32] }):$offset, (timm:{ *:[i32] }):$auxiliary, 0:{ *:[i1] })<<P:Predicate_SIbuffer_atomic_fmin_noret>>  =>  (BUFFER_ATOMIC_FMIN_OFFEN anonymous_15037:{ *:[f32] }:$vdata_in, VGPR_32:{ *:[i32] }:$voffset, SReg_128:{ *:[v4i32] }:$rsrc, SCSrc_b32:{ *:[i32] }:$soffset, (timm:{ *:[i32] }):$offset, (extract_cpol:{ *:[i32] } ?:{ *:[i32] }:$auxiliary))
        GIR_BuildMI, /*InsnID*/0, /*Opcode*/GIMT_Encode2(AMDGPU::BUFFER_ATOMIC_FMIN_OFFEN),
        GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/1, // vdata_in
        GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/4, // voffset
        GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/2, // rsrc
        GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/0, // soffset
        GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/6, // offset
        GIR_CustomOperandRenderer, /*InsnID*/0, /*OldInsnID*/0, /*OpIdx*/7, /*OperandRenderer*/GIMT_Encode2(GICR_renderExtractCPol), // auxiliary
        GIR_MergeMemOperands, /*InsnID*/0, /*NumInsns*/1, /*MergeInsnID's*/0,
        GIR_ConstrainSelectedInstOperands, /*InsnID*/0,
        GIR_EraseFromParent, /*InsnID*/0,
        // GIR_Coverage, 5151,
        GIR_Done,
      // Label 5997: @438441
      GIM_Try, /*On fail goto*//*Label 5998*/ GIMT_Encode4(438519), // Rule ID 5159 //
        GIM_CheckFeatures, GIMT_Encode2(GIFBS_isGFX6GFX7GFX10Plus),
        GIM_CheckHasNoUse, /*MI*/0,
        GIM_CheckConstantInt8, /*MI*/0, /*Op*/3, 0,
        // MIs[0] offset
        GIM_CheckIsImm, /*MI*/0, /*Op*/6,
        // MIs[0] auxiliary
        GIM_CheckIsImm, /*MI*/0, /*Op*/7,
        // MIs[0] Operand 8
        GIM_CheckLiteralInt, /*MI*/0, /*Op*/8, GIMT_Encode8(0),
        GIM_CheckComplexPattern, /*MI*/0, /*Op*/5, /*Renderer*/GIMT_Encode2(0), GIMT_Encode2(GICP_gi_buf_soffset),
        // (SIbuffer_atomic_fmin:{ *:[f32] } f32:{ *:[f32] }:$vdata_in, v4i32:{ *:[v4i32] }:$rsrc, 0:{ *:[i32] }, i32:{ *:[i32] }:$voffset, (BUFSOffset:{ *:[i32] } i32:{ *:[i32] }:$soffset), (timm:{ *:[i32] }):$offset, (timm:{ *:[i32] }):$auxiliary, 0:{ *:[i1] })<<P:Predicate_SIbuffer_atomic_fmin_noret>>  =>  (BUFFER_ATOMIC_FMIN_VBUFFER_OFFEN anonymous_15037:{ *:[f32] }:$vdata_in, VGPR_32:{ *:[i32] }:$voffset, SReg_128:{ *:[v4i32] }:$rsrc, SCSrc_b32:{ *:[i32] }:$soffset, (timm:{ *:[i32] }):$offset, (extract_cpol:{ *:[i32] } ?:{ *:[i32] }:$auxiliary))
        GIR_BuildMI, /*InsnID*/0, /*Opcode*/GIMT_Encode2(AMDGPU::BUFFER_ATOMIC_FMIN_VBUFFER_OFFEN),
        GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/1, // vdata_in
        GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/4, // voffset
        GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/2, // rsrc
        GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/0, // soffset
        GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/6, // offset
        GIR_CustomOperandRenderer, /*InsnID*/0, /*OldInsnID*/0, /*OpIdx*/7, /*OperandRenderer*/GIMT_Encode2(GICR_renderExtractCPol), // auxiliary
        GIR_MergeMemOperands, /*InsnID*/0, /*NumInsns*/1, /*MergeInsnID's*/0,
        GIR_ConstrainSelectedInstOperands, /*InsnID*/0,
        GIR_EraseFromParent, /*InsnID*/0,
        // GIR_Coverage, 5159,
        GIR_Done,
      // Label 5998: @438519
      GIM_Try, /*On fail goto*//*Label 5999*/ GIMT_Encode4(438604), // Rule ID 5147 //
        GIM_CheckFeatures, GIMT_Encode2(GIFBS_isGFX6GFX7GFX10Plus),
        GIM_CheckRegBankForClass, /*MI*/0, /*Op*/0, /*RC*/GIMT_Encode2(AMDGPU::AV_32RegClassID),
        GIM_CheckConstantInt8, /*MI*/0, /*Op*/3, 0,
        // MIs[0] offset
        GIM_CheckIsImm, /*MI*/0, /*Op*/6,
        // MIs[0] auxiliary
        GIM_CheckIsImm, /*MI*/0, /*Op*/7,
        // MIs[0] Operand 8
        GIM_CheckLiteralInt, /*MI*/0, /*Op*/8, GIMT_Encode8(0),
        GIM_CheckComplexPattern, /*MI*/0, /*Op*/5, /*Renderer*/GIMT_Encode2(0), GIMT_Encode2(GICP_gi_buf_soffset),
        // (SIbuffer_atomic_fmin:{ *:[f32] } f32:{ *:[f32] }:$vdata_in, v4i32:{ *:[v4i32] }:$rsrc, 0:{ *:[i32] }, i32:{ *:[i32] }:$voffset, (BUFSOffset:{ *:[i32] } i32:{ *:[i32] }:$soffset), (timm:{ *:[i32] }):$offset, (timm:{ *:[i32] }):$auxiliary, 0:{ *:[i1] })  =>  (BUFFER_ATOMIC_FMIN_OFFEN_RTN:{ *:[f32] } anonymous_15037:{ *:[f32] }:$vdata_in, VGPR_32:{ *:[i32] }:$voffset, SReg_128:{ *:[v4i32] }:$rsrc, SCSrc_b32:{ *:[i32] }:$soffset, (timm:{ *:[i32] }):$offset, (extract_cpol_set_glc:{ *:[i32] } ?:{ *:[i32] }:$auxiliary))
        GIR_BuildMI, /*InsnID*/0, /*Opcode*/GIMT_Encode2(AMDGPU::BUFFER_ATOMIC_FMIN_OFFEN_RTN),
        GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/0, // DstI[vdata]
        GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/1, // vdata_in
        GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/4, // voffset
        GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/2, // rsrc
        GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/0, // soffset
        GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/6, // offset
        GIR_CustomOperandRenderer, /*InsnID*/0, /*OldInsnID*/0, /*OpIdx*/7, /*OperandRenderer*/GIMT_Encode2(GICR_renderExtractCpolSetGLC), // auxiliary
        GIR_MergeMemOperands, /*InsnID*/0, /*NumInsns*/1, /*MergeInsnID's*/0,
        GIR_ConstrainSelectedInstOperands, /*InsnID*/0,
        GIR_EraseFromParent, /*InsnID*/0,
        // GIR_Coverage, 5147,
        GIR_Done,
      // Label 5999: @438604
      GIM_Try, /*On fail goto*//*Label 6000*/ GIMT_Encode4(438689), // Rule ID 5155 //
        GIM_CheckFeatures, GIMT_Encode2(GIFBS_isGFX6GFX7GFX10Plus),
        GIM_CheckRegBankForClass, /*MI*/0, /*Op*/0, /*RC*/GIMT_Encode2(AMDGPU::AV_32RegClassID),
        GIM_CheckConstantInt8, /*MI*/0, /*Op*/3, 0,
        // MIs[0] offset
        GIM_CheckIsImm, /*MI*/0, /*Op*/6,
        // MIs[0] auxiliary
        GIM_CheckIsImm, /*MI*/0, /*Op*/7,
        // MIs[0] Operand 8
        GIM_CheckLiteralInt, /*MI*/0, /*Op*/8, GIMT_Encode8(0),
        GIM_CheckComplexPattern, /*MI*/0, /*Op*/5, /*Renderer*/GIMT_Encode2(0), GIMT_Encode2(GICP_gi_buf_soffset),
        // (SIbuffer_atomic_fmin:{ *:[f32] } f32:{ *:[f32] }:$vdata_in, v4i32:{ *:[v4i32] }:$rsrc, 0:{ *:[i32] }, i32:{ *:[i32] }:$voffset, (BUFSOffset:{ *:[i32] } i32:{ *:[i32] }:$soffset), (timm:{ *:[i32] }):$offset, (timm:{ *:[i32] }):$auxiliary, 0:{ *:[i1] })  =>  (BUFFER_ATOMIC_FMIN_VBUFFER_OFFEN_RTN:{ *:[f32] } anonymous_15037:{ *:[f32] }:$vdata_in, VGPR_32:{ *:[i32] }:$voffset, SReg_128:{ *:[v4i32] }:$rsrc, SCSrc_b32:{ *:[i32] }:$soffset, (timm:{ *:[i32] }):$offset, (extract_cpol_set_glc:{ *:[i32] } ?:{ *:[i32] }:$auxiliary))
        GIR_BuildMI, /*InsnID*/0, /*Opcode*/GIMT_Encode2(AMDGPU::BUFFER_ATOMIC_FMIN_VBUFFER_OFFEN_RTN),
        GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/0, // DstI[vdata]
        GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/1, // vdata_in
        GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/4, // voffset
        GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/2, // rsrc
        GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/0, // soffset
        GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/6, // offset
        GIR_CustomOperandRenderer, /*InsnID*/0, /*OldInsnID*/0, /*OpIdx*/7, /*OperandRenderer*/GIMT_Encode2(GICR_renderExtractCpolSetGLC), // auxiliary
        GIR_MergeMemOperands, /*InsnID*/0, /*NumInsns*/1, /*MergeInsnID's*/0,
        GIR_ConstrainSelectedInstOperands, /*InsnID*/0,
        GIR_EraseFromParent, /*InsnID*/0,
        // GIR_Coverage, 5155,
        GIR_Done,
      // Label 6000: @438689
      GIM_Try, /*On fail goto*//*Label 6001*/ GIMT_Encode4(438759), // Rule ID 5150 //
        GIM_CheckFeatures, GIMT_Encode2(GIFBS_isGFX6GFX7GFX10Plus),
        GIM_CheckHasNoUse, /*MI*/0,
        GIM_CheckConstantInt8, /*MI*/0, /*Op*/4, 0,
        // MIs[0] offset
        GIM_CheckIsImm, /*MI*/0, /*Op*/6,
        // MIs[0] auxiliary
        GIM_CheckIsImm, /*MI*/0, /*Op*/7,
        // MIs[0] Operand 8
        GIM_CheckIsImm, /*MI*/0, /*Op*/8,
        GIM_CheckComplexPattern, /*MI*/0, /*Op*/5, /*Renderer*/GIMT_Encode2(0), GIMT_Encode2(GICP_gi_buf_soffset),
        // (SIbuffer_atomic_fmin:{ *:[f32] } f32:{ *:[f32] }:$vdata_in, v4i32:{ *:[v4i32] }:$rsrc, i32:{ *:[i32] }:$vindex, 0:{ *:[i32] }, (BUFSOffset:{ *:[i32] } i32:{ *:[i32] }:$soffset), (timm:{ *:[i32] }):$offset, (timm:{ *:[i32] }):$auxiliary, (timm:{ *:[i1] }))<<P:Predicate_SIbuffer_atomic_fmin_noret>>  =>  (BUFFER_ATOMIC_FMIN_IDXEN anonymous_15037:{ *:[f32] }:$vdata_in, VGPR_32:{ *:[i32] }:$vindex, SReg_128:{ *:[v4i32] }:$rsrc, SCSrc_b32:{ *:[i32] }:$soffset, (timm:{ *:[i32] }):$offset, (extract_cpol:{ *:[i32] } ?:{ *:[i32] }:$auxiliary))
        GIR_BuildMI, /*InsnID*/0, /*Opcode*/GIMT_Encode2(AMDGPU::BUFFER_ATOMIC_FMIN_IDXEN),
        GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/1, // vdata_in
        GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/3, // vindex
        GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/2, // rsrc
        GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/0, // soffset
        GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/6, // offset
        GIR_CustomOperandRenderer, /*InsnID*/0, /*OldInsnID*/0, /*OpIdx*/7, /*OperandRenderer*/GIMT_Encode2(GICR_renderExtractCPol), // auxiliary
        GIR_MergeMemOperands, /*InsnID*/0, /*NumInsns*/1, /*MergeInsnID's*/0,
        GIR_ConstrainSelectedInstOperands, /*InsnID*/0,
        GIR_EraseFromParent, /*InsnID*/0,
        // GIR_Coverage, 5150,
        GIR_Done,
      // Label 6001: @438759
      GIM_Try, /*On fail goto*//*Label 6002*/ GIMT_Encode4(438829), // Rule ID 5158 //
        GIM_CheckFeatures, GIMT_Encode2(GIFBS_isGFX6GFX7GFX10Plus),
        GIM_CheckHasNoUse, /*MI*/0,
        GIM_CheckConstantInt8, /*MI*/0, /*Op*/4, 0,
        // MIs[0] offset
        GIM_CheckIsImm, /*MI*/0, /*Op*/6,
        // MIs[0] auxiliary
        GIM_CheckIsImm, /*MI*/0, /*Op*/7,
        // MIs[0] Operand 8
        GIM_CheckIsImm, /*MI*/0, /*Op*/8,
        GIM_CheckComplexPattern, /*MI*/0, /*Op*/5, /*Renderer*/GIMT_Encode2(0), GIMT_Encode2(GICP_gi_buf_soffset),
        // (SIbuffer_atomic_fmin:{ *:[f32] } f32:{ *:[f32] }:$vdata_in, v4i32:{ *:[v4i32] }:$rsrc, i32:{ *:[i32] }:$vindex, 0:{ *:[i32] }, (BUFSOffset:{ *:[i32] } i32:{ *:[i32] }:$soffset), (timm:{ *:[i32] }):$offset, (timm:{ *:[i32] }):$auxiliary, (timm:{ *:[i1] }))<<P:Predicate_SIbuffer_atomic_fmin_noret>>  =>  (BUFFER_ATOMIC_FMIN_VBUFFER_IDXEN anonymous_15037:{ *:[f32] }:$vdata_in, VGPR_32:{ *:[i32] }:$vindex, SReg_128:{ *:[v4i32] }:$rsrc, SCSrc_b32:{ *:[i32] }:$soffset, (timm:{ *:[i32] }):$offset, (extract_cpol:{ *:[i32] } ?:{ *:[i32] }:$auxiliary))
        GIR_BuildMI, /*InsnID*/0, /*Opcode*/GIMT_Encode2(AMDGPU::BUFFER_ATOMIC_FMIN_VBUFFER_IDXEN),
        GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/1, // vdata_in
        GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/3, // vindex
        GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/2, // rsrc
        GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/0, // soffset
        GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/6, // offset
        GIR_CustomOperandRenderer, /*InsnID*/0, /*OldInsnID*/0, /*OpIdx*/7, /*OperandRenderer*/GIMT_Encode2(GICR_renderExtractCPol), // auxiliary
        GIR_MergeMemOperands, /*InsnID*/0, /*NumInsns*/1, /*MergeInsnID's*/0,
        GIR_ConstrainSelectedInstOperands, /*InsnID*/0,
        GIR_EraseFromParent, /*InsnID*/0,
        // GIR_Coverage, 5158,
        GIR_Done,
      // Label 6002: @438829
      GIM_Try, /*On fail goto*//*Label 6003*/ GIMT_Encode4(438906), // Rule ID 5146 //
        GIM_CheckFeatures, GIMT_Encode2(GIFBS_isGFX6GFX7GFX10Plus),
        GIM_CheckRegBankForClass, /*MI*/0, /*Op*/0, /*RC*/GIMT_Encode2(AMDGPU::AV_32RegClassID),
        GIM_CheckConstantInt8, /*MI*/0, /*Op*/4, 0,
        // MIs[0] offset
        GIM_CheckIsImm, /*MI*/0, /*Op*/6,
        // MIs[0] auxiliary
        GIM_CheckIsImm, /*MI*/0, /*Op*/7,
        // MIs[0] Operand 8
        GIM_CheckIsImm, /*MI*/0, /*Op*/8,
        GIM_CheckComplexPattern, /*MI*/0, /*Op*/5, /*Renderer*/GIMT_Encode2(0), GIMT_Encode2(GICP_gi_buf_soffset),
        // (SIbuffer_atomic_fmin:{ *:[f32] } f32:{ *:[f32] }:$vdata_in, v4i32:{ *:[v4i32] }:$rsrc, i32:{ *:[i32] }:$vindex, 0:{ *:[i32] }, (BUFSOffset:{ *:[i32] } i32:{ *:[i32] }:$soffset), (timm:{ *:[i32] }):$offset, (timm:{ *:[i32] }):$auxiliary, (timm:{ *:[i1] }))  =>  (BUFFER_ATOMIC_FMIN_IDXEN_RTN:{ *:[f32] } anonymous_15037:{ *:[f32] }:$vdata_in, VGPR_32:{ *:[i32] }:$vindex, SReg_128:{ *:[v4i32] }:$rsrc, SCSrc_b32:{ *:[i32] }:$soffset, (timm:{ *:[i32] }):$offset, (extract_cpol_set_glc:{ *:[i32] } ?:{ *:[i32] }:$auxiliary))
        GIR_BuildMI, /*InsnID*/0, /*Opcode*/GIMT_Encode2(AMDGPU::BUFFER_ATOMIC_FMIN_IDXEN_RTN),
        GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/0, // DstI[vdata]
        GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/1, // vdata_in
        GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/3, // vindex
        GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/2, // rsrc
        GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/0, // soffset
        GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/6, // offset
        GIR_CustomOperandRenderer, /*InsnID*/0, /*OldInsnID*/0, /*OpIdx*/7, /*OperandRenderer*/GIMT_Encode2(GICR_renderExtractCpolSetGLC), // auxiliary
        GIR_MergeMemOperands, /*InsnID*/0, /*NumInsns*/1, /*MergeInsnID's*/0,
        GIR_ConstrainSelectedInstOperands, /*InsnID*/0,
        GIR_EraseFromParent, /*InsnID*/0,
        // GIR_Coverage, 5146,
        GIR_Done,
      // Label 6003: @438906
      GIM_Try, /*On fail goto*//*Label 6004*/ GIMT_Encode4(438983), // Rule ID 5154 //
        GIM_CheckFeatures, GIMT_Encode2(GIFBS_isGFX6GFX7GFX10Plus),
        GIM_CheckRegBankForClass, /*MI*/0, /*Op*/0, /*RC*/GIMT_Encode2(AMDGPU::AV_32RegClassID),
        GIM_CheckConstantInt8, /*MI*/0, /*Op*/4, 0,
        // MIs[0] offset
        GIM_CheckIsImm, /*MI*/0, /*Op*/6,
        // MIs[0] auxiliary
        GIM_CheckIsImm, /*MI*/0, /*Op*/7,
        // MIs[0] Operand 8
        GIM_CheckIsImm, /*MI*/0, /*Op*/8,
        GIM_CheckComplexPattern, /*MI*/0, /*Op*/5, /*Renderer*/GIMT_Encode2(0), GIMT_Encode2(GICP_gi_buf_soffset),
        // (SIbuffer_atomic_fmin:{ *:[f32] } f32:{ *:[f32] }:$vdata_in, v4i32:{ *:[v4i32] }:$rsrc, i32:{ *:[i32] }:$vindex, 0:{ *:[i32] }, (BUFSOffset:{ *:[i32] } i32:{ *:[i32] }:$soffset), (timm:{ *:[i32] }):$offset, (timm:{ *:[i32] }):$auxiliary, (timm:{ *:[i1] }))  =>  (BUFFER_ATOMIC_FMIN_VBUFFER_IDXEN_RTN:{ *:[f32] } anonymous_15037:{ *:[f32] }:$vdata_in, VGPR_32:{ *:[i32] }:$vindex, SReg_128:{ *:[v4i32] }:$rsrc, SCSrc_b32:{ *:[i32] }:$soffset, (timm:{ *:[i32] }):$offset, (extract_cpol_set_glc:{ *:[i32] } ?:{ *:[i32] }:$auxiliary))
        GIR_BuildMI, /*InsnID*/0, /*Opcode*/GIMT_Encode2(AMDGPU::BUFFER_ATOMIC_FMIN_VBUFFER_IDXEN_RTN),
        GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/0, // DstI[vdata]
        GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/1, // vdata_in
        GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/3, // vindex
        GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/2, // rsrc
        GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/0, // soffset
        GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/6, // offset
        GIR_CustomOperandRenderer, /*InsnID*/0, /*OldInsnID*/0, /*OpIdx*/7, /*OperandRenderer*/GIMT_Encode2(GICR_renderExtractCpolSetGLC), // auxiliary
        GIR_MergeMemOperands, /*InsnID*/0, /*NumInsns*/1, /*MergeInsnID's*/0,
        GIR_ConstrainSelectedInstOperands, /*InsnID*/0,
        GIR_EraseFromParent, /*InsnID*/0,
        // GIR_Coverage, 5154,
        GIR_Done,
      // Label 6004: @438983
      GIM_Try, /*On fail goto*//*Label 6005*/ GIMT_Encode4(439089), // Rule ID 5152 //
        GIM_CheckFeatures, GIMT_Encode2(GIFBS_isGFX6GFX7GFX10Plus),
        GIM_CheckHasNoUse, /*MI*/0,
        // MIs[0] offset
        GIM_CheckIsImm, /*MI*/0, /*Op*/6,
        // MIs[0] auxiliary
        GIM_CheckIsImm, /*MI*/0, /*Op*/7,
        // MIs[0] Operand 8
        GIM_CheckIsImm, /*MI*/0, /*Op*/8,
        GIM_CheckComplexPattern, /*MI*/0, /*Op*/5, /*Renderer*/GIMT_Encode2(0), GIMT_Encode2(GICP_gi_buf_soffset),
        // (SIbuffer_atomic_fmin:{ *:[f32] } f32:{ *:[f32] }:$vdata_in, v4i32:{ *:[v4i32] }:$rsrc, i32:{ *:[i32] }:$vindex, i32:{ *:[i32] }:$voffset, (BUFSOffset:{ *:[i32] } i32:{ *:[i32] }:$soffset), (timm:{ *:[i32] }):$offset, (timm:{ *:[i32] }):$auxiliary, (timm:{ *:[i1] }))<<P:Predicate_SIbuffer_atomic_fmin_noret>>  =>  (BUFFER_ATOMIC_FMIN_BOTHEN anonymous_15037:{ *:[f32] }:$vdata_in, (REG_SEQUENCE:{ *:[i64] } VReg_64:{ *:[i32] }, VGPR_32:{ *:[i32] }:$vindex, sub0:{ *:[i32] }, VGPR_32:{ *:[i32] }:$voffset, sub1:{ *:[i32] }), SReg_128:{ *:[v4i32] }:$rsrc, SCSrc_b32:{ *:[i32] }:$soffset, (timm:{ *:[i32] }):$offset, (extract_cpol:{ *:[i32] } ?:{ *:[i32] }:$auxiliary))
        GIR_MakeTempReg, /*TempRegID*/0, /*TypeID*/GILLT_s64,
        GIR_BuildMI, /*InsnID*/1, /*Opcode*/GIMT_Encode2(TargetOpcode::REG_SEQUENCE),
        GIR_AddTempRegister, /*InsnID*/1, /*TempRegID*/0, /*TempRegFlags*/GIMT_Encode2(RegState::Define),
        GIR_Copy, /*NewInsnID*/1, /*OldInsnID*/0, /*OpIdx*/3, // vindex
        GIR_AddImm8, /*InsnID*/1, /*SubRegIndex*/3,
        GIR_Copy, /*NewInsnID*/1, /*OldInsnID*/0, /*OpIdx*/4, // voffset
        GIR_AddImm8, /*InsnID*/1, /*SubRegIndex*/11,
        GIR_ConstrainOperandRC, /*InsnID*/1, /*Op*/0, GIMT_Encode2(AMDGPU::VReg_64RegClassID),
        GIR_ConstrainOperandRC, /*InsnID*/1, /*Op*/1, GIMT_Encode2(AMDGPU::VGPR_32RegClassID),
        GIR_ConstrainOperandRC, /*InsnID*/1, /*Op*/3, GIMT_Encode2(AMDGPU::VGPR_32RegClassID),
        GIR_BuildMI, /*InsnID*/0, /*Opcode*/GIMT_Encode2(AMDGPU::BUFFER_ATOMIC_FMIN_BOTHEN),
        GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/1, // vdata_in
        GIR_AddSimpleTempRegister, /*InsnID*/0, /*TempRegID*/0,
        GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/2, // rsrc
        GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/0, // soffset
        GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/6, // offset
        GIR_CustomOperandRenderer, /*InsnID*/0, /*OldInsnID*/0, /*OpIdx*/7, /*OperandRenderer*/GIMT_Encode2(GICR_renderExtractCPol), // auxiliary
        GIR_MergeMemOperands, /*InsnID*/0, /*NumInsns*/1, /*MergeInsnID's*/0,
        GIR_ConstrainSelectedInstOperands, /*InsnID*/0,
        GIR_EraseFromParent, /*InsnID*/0,
        // GIR_Coverage, 5152,
        GIR_Done,
      // Label 6005: @439089
      GIM_Try, /*On fail goto*//*Label 6006*/ GIMT_Encode4(439195), // Rule ID 5160 //
        GIM_CheckFeatures, GIMT_Encode2(GIFBS_isGFX6GFX7GFX10Plus),
        GIM_CheckHasNoUse, /*MI*/0,
        // MIs[0] offset
        GIM_CheckIsImm, /*MI*/0, /*Op*/6,
        // MIs[0] auxiliary
        GIM_CheckIsImm, /*MI*/0, /*Op*/7,
        // MIs[0] Operand 8
        GIM_CheckIsImm, /*MI*/0, /*Op*/8,
        GIM_CheckComplexPattern, /*MI*/0, /*Op*/5, /*Renderer*/GIMT_Encode2(0), GIMT_Encode2(GICP_gi_buf_soffset),
        // (SIbuffer_atomic_fmin:{ *:[f32] } f32:{ *:[f32] }:$vdata_in, v4i32:{ *:[v4i32] }:$rsrc, i32:{ *:[i32] }:$vindex, i32:{ *:[i32] }:$voffset, (BUFSOffset:{ *:[i32] } i32:{ *:[i32] }:$soffset), (timm:{ *:[i32] }):$offset, (timm:{ *:[i32] }):$auxiliary, (timm:{ *:[i1] }))<<P:Predicate_SIbuffer_atomic_fmin_noret>>  =>  (BUFFER_ATOMIC_FMIN_VBUFFER_BOTHEN anonymous_15037:{ *:[f32] }:$vdata_in, (REG_SEQUENCE:{ *:[i64] } VReg_64:{ *:[i32] }, VGPR_32:{ *:[i32] }:$vindex, sub0:{ *:[i32] }, VGPR_32:{ *:[i32] }:$voffset, sub1:{ *:[i32] }), SReg_128:{ *:[v4i32] }:$rsrc, SCSrc_b32:{ *:[i32] }:$soffset, (timm:{ *:[i32] }):$offset, (extract_cpol:{ *:[i32] } ?:{ *:[i32] }:$auxiliary))
        GIR_MakeTempReg, /*TempRegID*/0, /*TypeID*/GILLT_s64,
        GIR_BuildMI, /*InsnID*/1, /*Opcode*/GIMT_Encode2(TargetOpcode::REG_SEQUENCE),
        GIR_AddTempRegister, /*InsnID*/1, /*TempRegID*/0, /*TempRegFlags*/GIMT_Encode2(RegState::Define),
        GIR_Copy, /*NewInsnID*/1, /*OldInsnID*/0, /*OpIdx*/3, // vindex
        GIR_AddImm8, /*InsnID*/1, /*SubRegIndex*/3,
        GIR_Copy, /*NewInsnID*/1, /*OldInsnID*/0, /*OpIdx*/4, // voffset
        GIR_AddImm8, /*InsnID*/1, /*SubRegIndex*/11,
        GIR_ConstrainOperandRC, /*InsnID*/1, /*Op*/0, GIMT_Encode2(AMDGPU::VReg_64RegClassID),
        GIR_ConstrainOperandRC, /*InsnID*/1, /*Op*/1, GIMT_Encode2(AMDGPU::VGPR_32RegClassID),
        GIR_ConstrainOperandRC, /*InsnID*/1, /*Op*/3, GIMT_Encode2(AMDGPU::VGPR_32RegClassID),
        GIR_BuildMI, /*InsnID*/0, /*Opcode*/GIMT_Encode2(AMDGPU::BUFFER_ATOMIC_FMIN_VBUFFER_BOTHEN),
        GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/1, // vdata_in
        GIR_AddSimpleTempRegister, /*InsnID*/0, /*TempRegID*/0,
        GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/2, // rsrc
        GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/0, // soffset
        GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/6, // offset
        GIR_CustomOperandRenderer, /*InsnID*/0, /*OldInsnID*/0, /*OpIdx*/7, /*OperandRenderer*/GIMT_Encode2(GICR_renderExtractCPol), // auxiliary
        GIR_MergeMemOperands, /*InsnID*/0, /*NumInsns*/1, /*MergeInsnID's*/0,
        GIR_ConstrainSelectedInstOperands, /*InsnID*/0,
        GIR_EraseFromParent, /*InsnID*/0,
        // GIR_Coverage, 5160,
        GIR_Done,
      // Label 6006: @439195
      GIM_Try, /*On fail goto*//*Label 6007*/ GIMT_Encode4(439308), // Rule ID 5148 //
        GIM_CheckFeatures, GIMT_Encode2(GIFBS_isGFX6GFX7GFX10Plus),
        GIM_CheckRegBankForClass, /*MI*/0, /*Op*/0, /*RC*/GIMT_Encode2(AMDGPU::AV_32RegClassID),
        // MIs[0] offset
        GIM_CheckIsImm, /*MI*/0, /*Op*/6,
        // MIs[0] auxiliary
        GIM_CheckIsImm, /*MI*/0, /*Op*/7,
        // MIs[0] Operand 8
        GIM_CheckIsImm, /*MI*/0, /*Op*/8,
        GIM_CheckComplexPattern, /*MI*/0, /*Op*/5, /*Renderer*/GIMT_Encode2(0), GIMT_Encode2(GICP_gi_buf_soffset),
        // (SIbuffer_atomic_fmin:{ *:[f32] } f32:{ *:[f32] }:$vdata_in, v4i32:{ *:[v4i32] }:$rsrc, i32:{ *:[i32] }:$vindex, i32:{ *:[i32] }:$voffset, (BUFSOffset:{ *:[i32] } i32:{ *:[i32] }:$soffset), (timm:{ *:[i32] }):$offset, (timm:{ *:[i32] }):$auxiliary, (timm:{ *:[i1] }))  =>  (BUFFER_ATOMIC_FMIN_BOTHEN_RTN:{ *:[f32] } anonymous_15037:{ *:[f32] }:$vdata_in, (REG_SEQUENCE:{ *:[i64] } VReg_64:{ *:[i32] }, VGPR_32:{ *:[i32] }:$vindex, sub0:{ *:[i32] }, VGPR_32:{ *:[i32] }:$voffset, sub1:{ *:[i32] }), SReg_128:{ *:[v4i32] }:$rsrc, SCSrc_b32:{ *:[i32] }:$soffset, (timm:{ *:[i32] }):$offset, (extract_cpol_set_glc:{ *:[i32] } ?:{ *:[i32] }:$auxiliary))
        GIR_MakeTempReg, /*TempRegID*/0, /*TypeID*/GILLT_s64,
        GIR_BuildMI, /*InsnID*/1, /*Opcode*/GIMT_Encode2(TargetOpcode::REG_SEQUENCE),
        GIR_AddTempRegister, /*InsnID*/1, /*TempRegID*/0, /*TempRegFlags*/GIMT_Encode2(RegState::Define),
        GIR_Copy, /*NewInsnID*/1, /*OldInsnID*/0, /*OpIdx*/3, // vindex
        GIR_AddImm8, /*InsnID*/1, /*SubRegIndex*/3,
        GIR_Copy, /*NewInsnID*/1, /*OldInsnID*/0, /*OpIdx*/4, // voffset
        GIR_AddImm8, /*InsnID*/1, /*SubRegIndex*/11,
        GIR_ConstrainOperandRC, /*InsnID*/1, /*Op*/0, GIMT_Encode2(AMDGPU::VReg_64RegClassID),
        GIR_ConstrainOperandRC, /*InsnID*/1, /*Op*/1, GIMT_Encode2(AMDGPU::VGPR_32RegClassID),
        GIR_ConstrainOperandRC, /*InsnID*/1, /*Op*/3, GIMT_Encode2(AMDGPU::VGPR_32RegClassID),
        GIR_BuildMI, /*InsnID*/0, /*Opcode*/GIMT_Encode2(AMDGPU::BUFFER_ATOMIC_FMIN_BOTHEN_RTN),
        GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/0, // DstI[vdata]
        GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/1, // vdata_in
        GIR_AddSimpleTempRegister, /*InsnID*/0, /*TempRegID*/0,
        GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/2, // rsrc
        GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/0, // soffset
        GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/6, // offset
        GIR_CustomOperandRenderer, /*InsnID*/0, /*OldInsnID*/0, /*OpIdx*/7, /*OperandRenderer*/GIMT_Encode2(GICR_renderExtractCpolSetGLC), // auxiliary
        GIR_MergeMemOperands, /*InsnID*/0, /*NumInsns*/1, /*MergeInsnID's*/0,
        GIR_ConstrainSelectedInstOperands, /*InsnID*/0,
        GIR_EraseFromParent, /*InsnID*/0,
        // GIR_Coverage, 5148,
        GIR_Done,
      // Label 6007: @439308
      GIM_Try, /*On fail goto*//*Label 6008*/ GIMT_Encode4(439421), // Rule ID 5156 //
        GIM_CheckFeatures, GIMT_Encode2(GIFBS_isGFX6GFX7GFX10Plus),
        GIM_CheckRegBankForClass, /*MI*/0, /*Op*/0, /*RC*/GIMT_Encode2(AMDGPU::AV_32RegClassID),
        // MIs[0] offset
        GIM_CheckIsImm, /*MI*/0, /*Op*/6,
        // MIs[0] auxiliary
        GIM_CheckIsImm, /*MI*/0, /*Op*/7,
        // MIs[0] Operand 8
        GIM_CheckIsImm, /*MI*/0, /*Op*/8,
        GIM_CheckComplexPattern, /*MI*/0, /*Op*/5, /*Renderer*/GIMT_Encode2(0), GIMT_Encode2(GICP_gi_buf_soffset),
        // (SIbuffer_atomic_fmin:{ *:[f32] } f32:{ *:[f32] }:$vdata_in, v4i32:{ *:[v4i32] }:$rsrc, i32:{ *:[i32] }:$vindex, i32:{ *:[i32] }:$voffset, (BUFSOffset:{ *:[i32] } i32:{ *:[i32] }:$soffset), (timm:{ *:[i32] }):$offset, (timm:{ *:[i32] }):$auxiliary, (timm:{ *:[i1] }))  =>  (BUFFER_ATOMIC_FMIN_VBUFFER_BOTHEN_RTN:{ *:[f32] } anonymous_15037:{ *:[f32] }:$vdata_in, (REG_SEQUENCE:{ *:[i64] } VReg_64:{ *:[i32] }, VGPR_32:{ *:[i32] }:$vindex, sub0:{ *:[i32] }, VGPR_32:{ *:[i32] }:$voffset, sub1:{ *:[i32] }), SReg_128:{ *:[v4i32] }:$rsrc, SCSrc_b32:{ *:[i32] }:$soffset, (timm:{ *:[i32] }):$offset, (extract_cpol_set_glc:{ *:[i32] } ?:{ *:[i32] }:$auxiliary))
        GIR_MakeTempReg, /*TempRegID*/0, /*TypeID*/GILLT_s64,
        GIR_BuildMI, /*InsnID*/1, /*Opcode*/GIMT_Encode2(TargetOpcode::REG_SEQUENCE),
        GIR_AddTempRegister, /*InsnID*/1, /*TempRegID*/0, /*TempRegFlags*/GIMT_Encode2(RegState::Define),
        GIR_Copy, /*NewInsnID*/1, /*OldInsnID*/0, /*OpIdx*/3, // vindex
        GIR_AddImm8, /*InsnID*/1, /*SubRegIndex*/3,
        GIR_Copy, /*NewInsnID*/1, /*OldInsnID*/0, /*OpIdx*/4, // voffset
        GIR_AddImm8, /*InsnID*/1, /*SubRegIndex*/11,
        GIR_ConstrainOperandRC, /*InsnID*/1, /*Op*/0, GIMT_Encode2(AMDGPU::VReg_64RegClassID),
        GIR_ConstrainOperandRC, /*InsnID*/1, /*Op*/1, GIMT_Encode2(AMDGPU::VGPR_32RegClassID),
        GIR_ConstrainOperandRC, /*InsnID*/1, /*Op*/3, GIMT_Encode2(AMDGPU::VGPR_32RegClassID),
        GIR_BuildMI, /*InsnID*/0, /*Opcode*/GIMT_Encode2(AMDGPU::BUFFER_ATOMIC_FMIN_VBUFFER_BOTHEN_RTN),
        GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/0, // DstI[vdata]
        GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/1, // vdata_in
        GIR_AddSimpleTempRegister, /*InsnID*/0, /*TempRegID*/0,
        GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/2, // rsrc
        GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/0, // soffset
        GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/6, // offset
        GIR_CustomOperandRenderer, /*InsnID*/0, /*OldInsnID*/0, /*OpIdx*/7, /*OperandRenderer*/GIMT_Encode2(GICR_renderExtractCpolSetGLC), // auxiliary
        GIR_MergeMemOperands, /*InsnID*/0, /*NumInsns*/1, /*MergeInsnID's*/0,
        GIR_ConstrainSelectedInstOperands, /*InsnID*/0,
        GIR_EraseFromParent, /*InsnID*/0,
        // GIR_Coverage, 5156,
        GIR_Done,
      // Label 6008: @439421
      GIM_Reject,
    // Label 5992: @439422
    GIM_Reject,
    // Label 5990: @439423
    GIM_Try, /*On fail goto*//*Label 6009*/ GIMT_Encode4(442217),
      GIM_CheckType, /*MI*/0, /*Op*/1, /*Type*/GILLT_s64,
      GIM_CheckType, /*MI*/0, /*Op*/2, /*Type*/GILLT_v4s32,
      GIM_CheckType, /*MI*/0, /*Op*/3, /*Type*/GILLT_s32,
      GIM_CheckType, /*MI*/0, /*Op*/4, /*Type*/GILLT_s32,
      GIM_CheckType, /*MI*/0, /*Op*/5, /*Type*/GILLT_s32,
      GIM_Try, /*On fail goto*//*Label 6010*/ GIMT_Encode4(439526), // Rule ID 5181 //
        GIM_CheckFeatures, GIMT_Encode2(GIFBS_isGFX6GFX7GFX10),
        GIM_CheckHasNoUse, /*MI*/0,
        GIM_CheckConstantInt8, /*MI*/0, /*Op*/3, 0,
        GIM_CheckConstantInt8, /*MI*/0, /*Op*/4, 0,
        // MIs[0] offset
        GIM_CheckIsImm, /*MI*/0, /*Op*/6,
        // MIs[0] auxiliary
        GIM_CheckIsImm, /*MI*/0, /*Op*/7,
        // MIs[0] Operand 8
        GIM_CheckLiteralInt, /*MI*/0, /*Op*/8, GIMT_Encode8(0),
        GIM_CheckComplexPattern, /*MI*/0, /*Op*/5, /*Renderer*/GIMT_Encode2(0), GIMT_Encode2(GICP_gi_buf_soffset),
        // (SIbuffer_atomic_fmin:{ *:[f64] } f64:{ *:[f64] }:$vdata_in, v4i32:{ *:[v4i32] }:$rsrc, 0:{ *:[i32] }, 0:{ *:[i32] }, (BUFSOffset:{ *:[i32] } i32:{ *:[i32] }:$soffset), (timm:{ *:[i32] }):$offset, (timm:{ *:[i32] }):$auxiliary, 0:{ *:[i1] })<<P:Predicate_SIbuffer_atomic_fmin_noret>>  =>  (BUFFER_ATOMIC_FMIN_X2_OFFSET anonymous_15036:{ *:[f64] }:$vdata_in, SReg_128:{ *:[v4i32] }:$rsrc, SCSrc_b32:{ *:[i32] }:$soffset, (timm:{ *:[i32] }):$offset, (extract_cpol:{ *:[i32] } ?:{ *:[i32] }:$auxiliary))
        GIR_BuildMI, /*InsnID*/0, /*Opcode*/GIMT_Encode2(AMDGPU::BUFFER_ATOMIC_FMIN_X2_OFFSET),
        GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/1, // vdata_in
        GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/2, // rsrc
        GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/0, // soffset
        GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/6, // offset
        GIR_CustomOperandRenderer, /*InsnID*/0, /*OldInsnID*/0, /*OpIdx*/7, /*OperandRenderer*/GIMT_Encode2(GICR_renderExtractCPol), // auxiliary
        GIR_MergeMemOperands, /*InsnID*/0, /*NumInsns*/1, /*MergeInsnID's*/0,
        GIR_ConstrainSelectedInstOperands, /*InsnID*/0,
        GIR_EraseFromParent, /*InsnID*/0,
        // GIR_Coverage, 5181,
        GIR_Done,
      // Label 6010: @439526
      GIM_Try, /*On fail goto*//*Label 6011*/ GIMT_Encode4(439604), // Rule ID 5189 //
        GIM_CheckFeatures, GIMT_Encode2(GIFBS_isGFX6GFX7GFX10),
        GIM_CheckHasNoUse, /*MI*/0,
        GIM_CheckConstantInt8, /*MI*/0, /*Op*/3, 0,
        GIM_CheckConstantInt8, /*MI*/0, /*Op*/4, 0,
        // MIs[0] offset
        GIM_CheckIsImm, /*MI*/0, /*Op*/6,
        // MIs[0] auxiliary
        GIM_CheckIsImm, /*MI*/0, /*Op*/7,
        // MIs[0] Operand 8
        GIM_CheckLiteralInt, /*MI*/0, /*Op*/8, GIMT_Encode8(0),
        GIM_CheckComplexPattern, /*MI*/0, /*Op*/5, /*Renderer*/GIMT_Encode2(0), GIMT_Encode2(GICP_gi_buf_soffset),
        // (SIbuffer_atomic_fmin:{ *:[f64] } f64:{ *:[f64] }:$vdata_in, v4i32:{ *:[v4i32] }:$rsrc, 0:{ *:[i32] }, 0:{ *:[i32] }, (BUFSOffset:{ *:[i32] } i32:{ *:[i32] }:$soffset), (timm:{ *:[i32] }):$offset, (timm:{ *:[i32] }):$auxiliary, 0:{ *:[i1] })<<P:Predicate_SIbuffer_atomic_fmin_noret>>  =>  (BUFFER_ATOMIC_FMIN_X2_VBUFFER_OFFSET anonymous_15036:{ *:[f64] }:$vdata_in, SReg_128:{ *:[v4i32] }:$rsrc, SCSrc_b32:{ *:[i32] }:$soffset, (timm:{ *:[i32] }):$offset, (extract_cpol:{ *:[i32] } ?:{ *:[i32] }:$auxiliary))
        GIR_BuildMI, /*InsnID*/0, /*Opcode*/GIMT_Encode2(AMDGPU::BUFFER_ATOMIC_FMIN_X2_VBUFFER_OFFSET),
        GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/1, // vdata_in
        GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/2, // rsrc
        GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/0, // soffset
        GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/6, // offset
        GIR_CustomOperandRenderer, /*InsnID*/0, /*OldInsnID*/0, /*OpIdx*/7, /*OperandRenderer*/GIMT_Encode2(GICR_renderExtractCPol), // auxiliary
        GIR_MergeMemOperands, /*InsnID*/0, /*NumInsns*/1, /*MergeInsnID's*/0,
        GIR_ConstrainSelectedInstOperands, /*InsnID*/0,
        GIR_EraseFromParent, /*InsnID*/0,
        // GIR_Coverage, 5189,
        GIR_Done,
      // Label 6011: @439604
      GIM_Try, /*On fail goto*//*Label 6012*/ GIMT_Encode4(439682), // Rule ID 5261 //
        GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasUnrestrictedSOffset_isGFX90APlus),
        GIM_CheckHasNoUse, /*MI*/0,
        GIM_CheckConstantInt8, /*MI*/0, /*Op*/3, 0,
        GIM_CheckConstantInt8, /*MI*/0, /*Op*/4, 0,
        // MIs[0] offset
        GIM_CheckIsImm, /*MI*/0, /*Op*/6,
        // MIs[0] auxiliary
        GIM_CheckIsImm, /*MI*/0, /*Op*/7,
        // MIs[0] Operand 8
        GIM_CheckLiteralInt, /*MI*/0, /*Op*/8, GIMT_Encode8(0),
        GIM_CheckComplexPattern, /*MI*/0, /*Op*/5, /*Renderer*/GIMT_Encode2(0), GIMT_Encode2(GICP_gi_buf_soffset),
        // (SIbuffer_atomic_fmin:{ *:[f64] } f64:{ *:[f64] }:$vdata_in, v4i32:{ *:[v4i32] }:$rsrc, 0:{ *:[i32] }, 0:{ *:[i32] }, (BUFSOffset:{ *:[i32] } i32:{ *:[i32] }:$soffset), (timm:{ *:[i32] }):$offset, (timm:{ *:[i32] }):$auxiliary, 0:{ *:[i1] })<<P:Predicate_SIbuffer_atomic_fmin_noret>>  =>  (BUFFER_ATOMIC_MIN_F64_OFFSET anonymous_15036:{ *:[f64] }:$vdata_in, SReg_128:{ *:[v4i32] }:$rsrc, SCSrc_b32:{ *:[i32] }:$soffset, (timm:{ *:[i32] }):$offset, (extract_cpol:{ *:[i32] } ?:{ *:[i32] }:$auxiliary))
        GIR_BuildMI, /*InsnID*/0, /*Opcode*/GIMT_Encode2(AMDGPU::BUFFER_ATOMIC_MIN_F64_OFFSET),
        GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/1, // vdata_in
        GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/2, // rsrc
        GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/0, // soffset
        GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/6, // offset
        GIR_CustomOperandRenderer, /*InsnID*/0, /*OldInsnID*/0, /*OpIdx*/7, /*OperandRenderer*/GIMT_Encode2(GICR_renderExtractCPol), // auxiliary
        GIR_MergeMemOperands, /*InsnID*/0, /*NumInsns*/1, /*MergeInsnID's*/0,
        GIR_ConstrainSelectedInstOperands, /*InsnID*/0,
        GIR_EraseFromParent, /*InsnID*/0,
        // GIR_Coverage, 5261,
        GIR_Done,
      // Label 6012: @439682
      GIM_Try, /*On fail goto*//*Label 6013*/ GIMT_Encode4(439760), // Rule ID 5269 //
        GIM_CheckFeatures, GIMT_Encode2(GIFBS_isGFX90APlus),
        GIM_CheckHasNoUse, /*MI*/0,
        GIM_CheckConstantInt8, /*MI*/0, /*Op*/3, 0,
        GIM_CheckConstantInt8, /*MI*/0, /*Op*/4, 0,
        // MIs[0] offset
        GIM_CheckIsImm, /*MI*/0, /*Op*/6,
        // MIs[0] auxiliary
        GIM_CheckIsImm, /*MI*/0, /*Op*/7,
        // MIs[0] Operand 8
        GIM_CheckLiteralInt, /*MI*/0, /*Op*/8, GIMT_Encode8(0),
        GIM_CheckComplexPattern, /*MI*/0, /*Op*/5, /*Renderer*/GIMT_Encode2(0), GIMT_Encode2(GICP_gi_buf_soffset),
        // (SIbuffer_atomic_fmin:{ *:[f64] } f64:{ *:[f64] }:$vdata_in, v4i32:{ *:[v4i32] }:$rsrc, 0:{ *:[i32] }, 0:{ *:[i32] }, (BUFSOffset:{ *:[i32] } i32:{ *:[i32] }:$soffset), (timm:{ *:[i32] }):$offset, (timm:{ *:[i32] }):$auxiliary, 0:{ *:[i1] })<<P:Predicate_SIbuffer_atomic_fmin_noret>>  =>  (BUFFER_ATOMIC_MIN_F64_VBUFFER_OFFSET anonymous_15036:{ *:[f64] }:$vdata_in, SReg_128:{ *:[v4i32] }:$rsrc, SCSrc_b32:{ *:[i32] }:$soffset, (timm:{ *:[i32] }):$offset, (extract_cpol:{ *:[i32] } ?:{ *:[i32] }:$auxiliary))
        GIR_BuildMI, /*InsnID*/0, /*Opcode*/GIMT_Encode2(AMDGPU::BUFFER_ATOMIC_MIN_F64_VBUFFER_OFFSET),
        GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/1, // vdata_in
        GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/2, // rsrc
        GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/0, // soffset
        GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/6, // offset
        GIR_CustomOperandRenderer, /*InsnID*/0, /*OldInsnID*/0, /*OpIdx*/7, /*OperandRenderer*/GIMT_Encode2(GICR_renderExtractCPol), // auxiliary
        GIR_MergeMemOperands, /*InsnID*/0, /*NumInsns*/1, /*MergeInsnID's*/0,
        GIR_ConstrainSelectedInstOperands, /*InsnID*/0,
        GIR_EraseFromParent, /*InsnID*/0,
        // GIR_Coverage, 5269,
        GIR_Done,
      // Label 6013: @439760
      GIM_Try, /*On fail goto*//*Label 6014*/ GIMT_Encode4(439845), // Rule ID 5177 //
        GIM_CheckFeatures, GIMT_Encode2(GIFBS_isGFX6GFX7GFX10),
        GIM_CheckRegBankForClass, /*MI*/0, /*Op*/0, /*RC*/GIMT_Encode2(AMDGPU::AV_64RegClassID),
        GIM_CheckConstantInt8, /*MI*/0, /*Op*/3, 0,
        GIM_CheckConstantInt8, /*MI*/0, /*Op*/4, 0,
        // MIs[0] offset
        GIM_CheckIsImm, /*MI*/0, /*Op*/6,
        // MIs[0] auxiliary
        GIM_CheckIsImm, /*MI*/0, /*Op*/7,
        // MIs[0] Operand 8
        GIM_CheckLiteralInt, /*MI*/0, /*Op*/8, GIMT_Encode8(0),
        GIM_CheckComplexPattern, /*MI*/0, /*Op*/5, /*Renderer*/GIMT_Encode2(0), GIMT_Encode2(GICP_gi_buf_soffset),
        // (SIbuffer_atomic_fmin:{ *:[f64] } f64:{ *:[f64] }:$vdata_in, v4i32:{ *:[v4i32] }:$rsrc, 0:{ *:[i32] }, 0:{ *:[i32] }, (BUFSOffset:{ *:[i32] } i32:{ *:[i32] }:$soffset), (timm:{ *:[i32] }):$offset, (timm:{ *:[i32] }):$auxiliary, 0:{ *:[i1] })  =>  (BUFFER_ATOMIC_FMIN_X2_OFFSET_RTN:{ *:[f64] } anonymous_15036:{ *:[f64] }:$vdata_in, SReg_128:{ *:[v4i32] }:$rsrc, SCSrc_b32:{ *:[i32] }:$soffset, (timm:{ *:[i32] }):$offset, (extract_cpol_set_glc:{ *:[i32] } ?:{ *:[i32] }:$auxiliary))
        GIR_BuildMI, /*InsnID*/0, /*Opcode*/GIMT_Encode2(AMDGPU::BUFFER_ATOMIC_FMIN_X2_OFFSET_RTN),
        GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/0, // DstI[vdata]
        GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/1, // vdata_in
        GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/2, // rsrc
        GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/0, // soffset
        GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/6, // offset
        GIR_CustomOperandRenderer, /*InsnID*/0, /*OldInsnID*/0, /*OpIdx*/7, /*OperandRenderer*/GIMT_Encode2(GICR_renderExtractCpolSetGLC), // auxiliary
        GIR_MergeMemOperands, /*InsnID*/0, /*NumInsns*/1, /*MergeInsnID's*/0,
        GIR_ConstrainSelectedInstOperands, /*InsnID*/0,
        GIR_EraseFromParent, /*InsnID*/0,
        // GIR_Coverage, 5177,
        GIR_Done,
      // Label 6014: @439845
      GIM_Try, /*On fail goto*//*Label 6015*/ GIMT_Encode4(439930), // Rule ID 5185 //
        GIM_CheckFeatures, GIMT_Encode2(GIFBS_isGFX6GFX7GFX10),
        GIM_CheckRegBankForClass, /*MI*/0, /*Op*/0, /*RC*/GIMT_Encode2(AMDGPU::AV_64RegClassID),
        GIM_CheckConstantInt8, /*MI*/0, /*Op*/3, 0,
        GIM_CheckConstantInt8, /*MI*/0, /*Op*/4, 0,
        // MIs[0] offset
        GIM_CheckIsImm, /*MI*/0, /*Op*/6,
        // MIs[0] auxiliary
        GIM_CheckIsImm, /*MI*/0, /*Op*/7,
        // MIs[0] Operand 8
        GIM_CheckLiteralInt, /*MI*/0, /*Op*/8, GIMT_Encode8(0),
        GIM_CheckComplexPattern, /*MI*/0, /*Op*/5, /*Renderer*/GIMT_Encode2(0), GIMT_Encode2(GICP_gi_buf_soffset),
        // (SIbuffer_atomic_fmin:{ *:[f64] } f64:{ *:[f64] }:$vdata_in, v4i32:{ *:[v4i32] }:$rsrc, 0:{ *:[i32] }, 0:{ *:[i32] }, (BUFSOffset:{ *:[i32] } i32:{ *:[i32] }:$soffset), (timm:{ *:[i32] }):$offset, (timm:{ *:[i32] }):$auxiliary, 0:{ *:[i1] })  =>  (BUFFER_ATOMIC_FMIN_X2_VBUFFER_OFFSET_RTN:{ *:[f64] } anonymous_15036:{ *:[f64] }:$vdata_in, SReg_128:{ *:[v4i32] }:$rsrc, SCSrc_b32:{ *:[i32] }:$soffset, (timm:{ *:[i32] }):$offset, (extract_cpol_set_glc:{ *:[i32] } ?:{ *:[i32] }:$auxiliary))
        GIR_BuildMI, /*InsnID*/0, /*Opcode*/GIMT_Encode2(AMDGPU::BUFFER_ATOMIC_FMIN_X2_VBUFFER_OFFSET_RTN),
        GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/0, // DstI[vdata]
        GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/1, // vdata_in
        GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/2, // rsrc
        GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/0, // soffset
        GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/6, // offset
        GIR_CustomOperandRenderer, /*InsnID*/0, /*OldInsnID*/0, /*OpIdx*/7, /*OperandRenderer*/GIMT_Encode2(GICR_renderExtractCpolSetGLC), // auxiliary
        GIR_MergeMemOperands, /*InsnID*/0, /*NumInsns*/1, /*MergeInsnID's*/0,
        GIR_ConstrainSelectedInstOperands, /*InsnID*/0,
        GIR_EraseFromParent, /*InsnID*/0,
        // GIR_Coverage, 5185,
        GIR_Done,
      // Label 6015: @439930
      GIM_Try, /*On fail goto*//*Label 6016*/ GIMT_Encode4(440015), // Rule ID 5257 //
        GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasUnrestrictedSOffset_isGFX90APlus),
        GIM_CheckRegBankForClass, /*MI*/0, /*Op*/0, /*RC*/GIMT_Encode2(AMDGPU::AV_64RegClassID),
        GIM_CheckConstantInt8, /*MI*/0, /*Op*/3, 0,
        GIM_CheckConstantInt8, /*MI*/0, /*Op*/4, 0,
        // MIs[0] offset
        GIM_CheckIsImm, /*MI*/0, /*Op*/6,
        // MIs[0] auxiliary
        GIM_CheckIsImm, /*MI*/0, /*Op*/7,
        // MIs[0] Operand 8
        GIM_CheckLiteralInt, /*MI*/0, /*Op*/8, GIMT_Encode8(0),
        GIM_CheckComplexPattern, /*MI*/0, /*Op*/5, /*Renderer*/GIMT_Encode2(0), GIMT_Encode2(GICP_gi_buf_soffset),
        // (SIbuffer_atomic_fmin:{ *:[f64] } f64:{ *:[f64] }:$vdata_in, v4i32:{ *:[v4i32] }:$rsrc, 0:{ *:[i32] }, 0:{ *:[i32] }, (BUFSOffset:{ *:[i32] } i32:{ *:[i32] }:$soffset), (timm:{ *:[i32] }):$offset, (timm:{ *:[i32] }):$auxiliary, 0:{ *:[i1] })  =>  (BUFFER_ATOMIC_MIN_F64_OFFSET_RTN:{ *:[f64] } anonymous_15036:{ *:[f64] }:$vdata_in, SReg_128:{ *:[v4i32] }:$rsrc, SCSrc_b32:{ *:[i32] }:$soffset, (timm:{ *:[i32] }):$offset, (extract_cpol_set_glc:{ *:[i32] } ?:{ *:[i32] }:$auxiliary))
        GIR_BuildMI, /*InsnID*/0, /*Opcode*/GIMT_Encode2(AMDGPU::BUFFER_ATOMIC_MIN_F64_OFFSET_RTN),
        GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/0, // DstI[vdata]
        GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/1, // vdata_in
        GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/2, // rsrc
        GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/0, // soffset
        GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/6, // offset
        GIR_CustomOperandRenderer, /*InsnID*/0, /*OldInsnID*/0, /*OpIdx*/7, /*OperandRenderer*/GIMT_Encode2(GICR_renderExtractCpolSetGLC), // auxiliary
        GIR_MergeMemOperands, /*InsnID*/0, /*NumInsns*/1, /*MergeInsnID's*/0,
        GIR_ConstrainSelectedInstOperands, /*InsnID*/0,
        GIR_EraseFromParent, /*InsnID*/0,
        // GIR_Coverage, 5257,
        GIR_Done,
      // Label 6016: @440015
      GIM_Try, /*On fail goto*//*Label 6017*/ GIMT_Encode4(440100), // Rule ID 5265 //
        GIM_CheckFeatures, GIMT_Encode2(GIFBS_isGFX90APlus),
        GIM_CheckRegBankForClass, /*MI*/0, /*Op*/0, /*RC*/GIMT_Encode2(AMDGPU::AV_64RegClassID),
        GIM_CheckConstantInt8, /*MI*/0, /*Op*/3, 0,
        GIM_CheckConstantInt8, /*MI*/0, /*Op*/4, 0,
        // MIs[0] offset
        GIM_CheckIsImm, /*MI*/0, /*Op*/6,
        // MIs[0] auxiliary
        GIM_CheckIsImm, /*MI*/0, /*Op*/7,
        // MIs[0] Operand 8
        GIM_CheckLiteralInt, /*MI*/0, /*Op*/8, GIMT_Encode8(0),
        GIM_CheckComplexPattern, /*MI*/0, /*Op*/5, /*Renderer*/GIMT_Encode2(0), GIMT_Encode2(GICP_gi_buf_soffset),
        // (SIbuffer_atomic_fmin:{ *:[f64] } f64:{ *:[f64] }:$vdata_in, v4i32:{ *:[v4i32] }:$rsrc, 0:{ *:[i32] }, 0:{ *:[i32] }, (BUFSOffset:{ *:[i32] } i32:{ *:[i32] }:$soffset), (timm:{ *:[i32] }):$offset, (timm:{ *:[i32] }):$auxiliary, 0:{ *:[i1] })  =>  (BUFFER_ATOMIC_MIN_F64_VBUFFER_OFFSET_RTN:{ *:[f64] } anonymous_15036:{ *:[f64] }:$vdata_in, SReg_128:{ *:[v4i32] }:$rsrc, SCSrc_b32:{ *:[i32] }:$soffset, (timm:{ *:[i32] }):$offset, (extract_cpol_set_glc:{ *:[i32] } ?:{ *:[i32] }:$auxiliary))
        GIR_BuildMI, /*InsnID*/0, /*Opcode*/GIMT_Encode2(AMDGPU::BUFFER_ATOMIC_MIN_F64_VBUFFER_OFFSET_RTN),
        GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/0, // DstI[vdata]
        GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/1, // vdata_in
        GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/2, // rsrc
        GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/0, // soffset
        GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/6, // offset
        GIR_CustomOperandRenderer, /*InsnID*/0, /*OldInsnID*/0, /*OpIdx*/7, /*OperandRenderer*/GIMT_Encode2(GICR_renderExtractCpolSetGLC), // auxiliary
        GIR_MergeMemOperands, /*InsnID*/0, /*NumInsns*/1, /*MergeInsnID's*/0,
        GIR_ConstrainSelectedInstOperands, /*InsnID*/0,
        GIR_EraseFromParent, /*InsnID*/0,
        // GIR_Coverage, 5265,
        GIR_Done,
      // Label 6017: @440100
      GIM_Try, /*On fail goto*//*Label 6018*/ GIMT_Encode4(440178), // Rule ID 5183 //
        GIM_CheckFeatures, GIMT_Encode2(GIFBS_isGFX6GFX7GFX10),
        GIM_CheckHasNoUse, /*MI*/0,
        GIM_CheckConstantInt8, /*MI*/0, /*Op*/3, 0,
        // MIs[0] offset
        GIM_CheckIsImm, /*MI*/0, /*Op*/6,
        // MIs[0] auxiliary
        GIM_CheckIsImm, /*MI*/0, /*Op*/7,
        // MIs[0] Operand 8
        GIM_CheckLiteralInt, /*MI*/0, /*Op*/8, GIMT_Encode8(0),
        GIM_CheckComplexPattern, /*MI*/0, /*Op*/5, /*Renderer*/GIMT_Encode2(0), GIMT_Encode2(GICP_gi_buf_soffset),
        // (SIbuffer_atomic_fmin:{ *:[f64] } f64:{ *:[f64] }:$vdata_in, v4i32:{ *:[v4i32] }:$rsrc, 0:{ *:[i32] }, i32:{ *:[i32] }:$voffset, (BUFSOffset:{ *:[i32] } i32:{ *:[i32] }:$soffset), (timm:{ *:[i32] }):$offset, (timm:{ *:[i32] }):$auxiliary, 0:{ *:[i1] })<<P:Predicate_SIbuffer_atomic_fmin_noret>>  =>  (BUFFER_ATOMIC_FMIN_X2_OFFEN anonymous_15036:{ *:[f64] }:$vdata_in, VGPR_32:{ *:[i32] }:$voffset, SReg_128:{ *:[v4i32] }:$rsrc, SCSrc_b32:{ *:[i32] }:$soffset, (timm:{ *:[i32] }):$offset, (extract_cpol:{ *:[i32] } ?:{ *:[i32] }:$auxiliary))
        GIR_BuildMI, /*InsnID*/0, /*Opcode*/GIMT_Encode2(AMDGPU::BUFFER_ATOMIC_FMIN_X2_OFFEN),
        GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/1, // vdata_in
        GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/4, // voffset
        GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/2, // rsrc
        GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/0, // soffset
        GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/6, // offset
        GIR_CustomOperandRenderer, /*InsnID*/0, /*OldInsnID*/0, /*OpIdx*/7, /*OperandRenderer*/GIMT_Encode2(GICR_renderExtractCPol), // auxiliary
        GIR_MergeMemOperands, /*InsnID*/0, /*NumInsns*/1, /*MergeInsnID's*/0,
        GIR_ConstrainSelectedInstOperands, /*InsnID*/0,
        GIR_EraseFromParent, /*InsnID*/0,
        // GIR_Coverage, 5183,
        GIR_Done,
      // Label 6018: @440178
      GIM_Try, /*On fail goto*//*Label 6019*/ GIMT_Encode4(440256), // Rule ID 5191 //
        GIM_CheckFeatures, GIMT_Encode2(GIFBS_isGFX6GFX7GFX10),
        GIM_CheckHasNoUse, /*MI*/0,
        GIM_CheckConstantInt8, /*MI*/0, /*Op*/3, 0,
        // MIs[0] offset
        GIM_CheckIsImm, /*MI*/0, /*Op*/6,
        // MIs[0] auxiliary
        GIM_CheckIsImm, /*MI*/0, /*Op*/7,
        // MIs[0] Operand 8
        GIM_CheckLiteralInt, /*MI*/0, /*Op*/8, GIMT_Encode8(0),
        GIM_CheckComplexPattern, /*MI*/0, /*Op*/5, /*Renderer*/GIMT_Encode2(0), GIMT_Encode2(GICP_gi_buf_soffset),
        // (SIbuffer_atomic_fmin:{ *:[f64] } f64:{ *:[f64] }:$vdata_in, v4i32:{ *:[v4i32] }:$rsrc, 0:{ *:[i32] }, i32:{ *:[i32] }:$voffset, (BUFSOffset:{ *:[i32] } i32:{ *:[i32] }:$soffset), (timm:{ *:[i32] }):$offset, (timm:{ *:[i32] }):$auxiliary, 0:{ *:[i1] })<<P:Predicate_SIbuffer_atomic_fmin_noret>>  =>  (BUFFER_ATOMIC_FMIN_X2_VBUFFER_OFFEN anonymous_15036:{ *:[f64] }:$vdata_in, VGPR_32:{ *:[i32] }:$voffset, SReg_128:{ *:[v4i32] }:$rsrc, SCSrc_b32:{ *:[i32] }:$soffset, (timm:{ *:[i32] }):$offset, (extract_cpol:{ *:[i32] } ?:{ *:[i32] }:$auxiliary))
        GIR_BuildMI, /*InsnID*/0, /*Opcode*/GIMT_Encode2(AMDGPU::BUFFER_ATOMIC_FMIN_X2_VBUFFER_OFFEN),
        GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/1, // vdata_in
        GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/4, // voffset
        GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/2, // rsrc
        GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/0, // soffset
        GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/6, // offset
        GIR_CustomOperandRenderer, /*InsnID*/0, /*OldInsnID*/0, /*OpIdx*/7, /*OperandRenderer*/GIMT_Encode2(GICR_renderExtractCPol), // auxiliary
        GIR_MergeMemOperands, /*InsnID*/0, /*NumInsns*/1, /*MergeInsnID's*/0,
        GIR_ConstrainSelectedInstOperands, /*InsnID*/0,
        GIR_EraseFromParent, /*InsnID*/0,
        // GIR_Coverage, 5191,
        GIR_Done,
      // Label 6019: @440256
      GIM_Try, /*On fail goto*//*Label 6020*/ GIMT_Encode4(440334), // Rule ID 5263 //
        GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasUnrestrictedSOffset_isGFX90APlus),
        GIM_CheckHasNoUse, /*MI*/0,
        GIM_CheckConstantInt8, /*MI*/0, /*Op*/3, 0,
        // MIs[0] offset
        GIM_CheckIsImm, /*MI*/0, /*Op*/6,
        // MIs[0] auxiliary
        GIM_CheckIsImm, /*MI*/0, /*Op*/7,
        // MIs[0] Operand 8
        GIM_CheckLiteralInt, /*MI*/0, /*Op*/8, GIMT_Encode8(0),
        GIM_CheckComplexPattern, /*MI*/0, /*Op*/5, /*Renderer*/GIMT_Encode2(0), GIMT_Encode2(GICP_gi_buf_soffset),
        // (SIbuffer_atomic_fmin:{ *:[f64] } f64:{ *:[f64] }:$vdata_in, v4i32:{ *:[v4i32] }:$rsrc, 0:{ *:[i32] }, i32:{ *:[i32] }:$voffset, (BUFSOffset:{ *:[i32] } i32:{ *:[i32] }:$soffset), (timm:{ *:[i32] }):$offset, (timm:{ *:[i32] }):$auxiliary, 0:{ *:[i1] })<<P:Predicate_SIbuffer_atomic_fmin_noret>>  =>  (BUFFER_ATOMIC_MIN_F64_OFFEN anonymous_15036:{ *:[f64] }:$vdata_in, VGPR_32:{ *:[i32] }:$voffset, SReg_128:{ *:[v4i32] }:$rsrc, SCSrc_b32:{ *:[i32] }:$soffset, (timm:{ *:[i32] }):$offset, (extract_cpol:{ *:[i32] } ?:{ *:[i32] }:$auxiliary))
        GIR_BuildMI, /*InsnID*/0, /*Opcode*/GIMT_Encode2(AMDGPU::BUFFER_ATOMIC_MIN_F64_OFFEN),
        GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/1, // vdata_in
        GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/4, // voffset
        GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/2, // rsrc
        GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/0, // soffset
        GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/6, // offset
        GIR_CustomOperandRenderer, /*InsnID*/0, /*OldInsnID*/0, /*OpIdx*/7, /*OperandRenderer*/GIMT_Encode2(GICR_renderExtractCPol), // auxiliary
        GIR_MergeMemOperands, /*InsnID*/0, /*NumInsns*/1, /*MergeInsnID's*/0,
        GIR_ConstrainSelectedInstOperands, /*InsnID*/0,
        GIR_EraseFromParent, /*InsnID*/0,
        // GIR_Coverage, 5263,
        GIR_Done,
      // Label 6020: @440334
      GIM_Try, /*On fail goto*//*Label 6021*/ GIMT_Encode4(440412), // Rule ID 5271 //
        GIM_CheckFeatures, GIMT_Encode2(GIFBS_isGFX90APlus),
        GIM_CheckHasNoUse, /*MI*/0,
        GIM_CheckConstantInt8, /*MI*/0, /*Op*/3, 0,
        // MIs[0] offset
        GIM_CheckIsImm, /*MI*/0, /*Op*/6,
        // MIs[0] auxiliary
        GIM_CheckIsImm, /*MI*/0, /*Op*/7,
        // MIs[0] Operand 8
        GIM_CheckLiteralInt, /*MI*/0, /*Op*/8, GIMT_Encode8(0),
        GIM_CheckComplexPattern, /*MI*/0, /*Op*/5, /*Renderer*/GIMT_Encode2(0), GIMT_Encode2(GICP_gi_buf_soffset),
        // (SIbuffer_atomic_fmin:{ *:[f64] } f64:{ *:[f64] }:$vdata_in, v4i32:{ *:[v4i32] }:$rsrc, 0:{ *:[i32] }, i32:{ *:[i32] }:$voffset, (BUFSOffset:{ *:[i32] } i32:{ *:[i32] }:$soffset), (timm:{ *:[i32] }):$offset, (timm:{ *:[i32] }):$auxiliary, 0:{ *:[i1] })<<P:Predicate_SIbuffer_atomic_fmin_noret>>  =>  (BUFFER_ATOMIC_MIN_F64_VBUFFER_OFFEN anonymous_15036:{ *:[f64] }:$vdata_in, VGPR_32:{ *:[i32] }:$voffset, SReg_128:{ *:[v4i32] }:$rsrc, SCSrc_b32:{ *:[i32] }:$soffset, (timm:{ *:[i32] }):$offset, (extract_cpol:{ *:[i32] } ?:{ *:[i32] }:$auxiliary))
        GIR_BuildMI, /*InsnID*/0, /*Opcode*/GIMT_Encode2(AMDGPU::BUFFER_ATOMIC_MIN_F64_VBUFFER_OFFEN),
        GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/1, // vdata_in
        GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/4, // voffset
        GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/2, // rsrc
        GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/0, // soffset
        GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/6, // offset
        GIR_CustomOperandRenderer, /*InsnID*/0, /*OldInsnID*/0, /*OpIdx*/7, /*OperandRenderer*/GIMT_Encode2(GICR_renderExtractCPol), // auxiliary
        GIR_MergeMemOperands, /*InsnID*/0, /*NumInsns*/1, /*MergeInsnID's*/0,
        GIR_ConstrainSelectedInstOperands, /*InsnID*/0,
        GIR_EraseFromParent, /*InsnID*/0,
        // GIR_Coverage, 5271,
        GIR_Done,
      // Label 6021: @440412
      GIM_Try, /*On fail goto*//*Label 6022*/ GIMT_Encode4(440497), // Rule ID 5179 //
        GIM_CheckFeatures, GIMT_Encode2(GIFBS_isGFX6GFX7GFX10),
        GIM_CheckRegBankForClass, /*MI*/0, /*Op*/0, /*RC*/GIMT_Encode2(AMDGPU::AV_64RegClassID),
        GIM_CheckConstantInt8, /*MI*/0, /*Op*/3, 0,
        // MIs[0] offset
        GIM_CheckIsImm, /*MI*/0, /*Op*/6,
        // MIs[0] auxiliary
        GIM_CheckIsImm, /*MI*/0, /*Op*/7,
        // MIs[0] Operand 8
        GIM_CheckLiteralInt, /*MI*/0, /*Op*/8, GIMT_Encode8(0),
        GIM_CheckComplexPattern, /*MI*/0, /*Op*/5, /*Renderer*/GIMT_Encode2(0), GIMT_Encode2(GICP_gi_buf_soffset),
        // (SIbuffer_atomic_fmin:{ *:[f64] } f64:{ *:[f64] }:$vdata_in, v4i32:{ *:[v4i32] }:$rsrc, 0:{ *:[i32] }, i32:{ *:[i32] }:$voffset, (BUFSOffset:{ *:[i32] } i32:{ *:[i32] }:$soffset), (timm:{ *:[i32] }):$offset, (timm:{ *:[i32] }):$auxiliary, 0:{ *:[i1] })  =>  (BUFFER_ATOMIC_FMIN_X2_OFFEN_RTN:{ *:[f64] } anonymous_15036:{ *:[f64] }:$vdata_in, VGPR_32:{ *:[i32] }:$voffset, SReg_128:{ *:[v4i32] }:$rsrc, SCSrc_b32:{ *:[i32] }:$soffset, (timm:{ *:[i32] }):$offset, (extract_cpol_set_glc:{ *:[i32] } ?:{ *:[i32] }:$auxiliary))
        GIR_BuildMI, /*InsnID*/0, /*Opcode*/GIMT_Encode2(AMDGPU::BUFFER_ATOMIC_FMIN_X2_OFFEN_RTN),
        GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/0, // DstI[vdata]
        GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/1, // vdata_in
        GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/4, // voffset
        GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/2, // rsrc
        GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/0, // soffset
        GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/6, // offset
        GIR_CustomOperandRenderer, /*InsnID*/0, /*OldInsnID*/0, /*OpIdx*/7, /*OperandRenderer*/GIMT_Encode2(GICR_renderExtractCpolSetGLC), // auxiliary
        GIR_MergeMemOperands, /*InsnID*/0, /*NumInsns*/1, /*MergeInsnID's*/0,
        GIR_ConstrainSelectedInstOperands, /*InsnID*/0,
        GIR_EraseFromParent, /*InsnID*/0,
        // GIR_Coverage, 5179,
        GIR_Done,
      // Label 6022: @440497
      GIM_Try, /*On fail goto*//*Label 6023*/ GIMT_Encode4(440582), // Rule ID 5187 //
        GIM_CheckFeatures, GIMT_Encode2(GIFBS_isGFX6GFX7GFX10),
        GIM_CheckRegBankForClass, /*MI*/0, /*Op*/0, /*RC*/GIMT_Encode2(AMDGPU::AV_64RegClassID),
        GIM_CheckConstantInt8, /*MI*/0, /*Op*/3, 0,
        // MIs[0] offset
        GIM_CheckIsImm, /*MI*/0, /*Op*/6,
        // MIs[0] auxiliary
        GIM_CheckIsImm, /*MI*/0, /*Op*/7,
        // MIs[0] Operand 8
        GIM_CheckLiteralInt, /*MI*/0, /*Op*/8, GIMT_Encode8(0),
        GIM_CheckComplexPattern, /*MI*/0, /*Op*/5, /*Renderer*/GIMT_Encode2(0), GIMT_Encode2(GICP_gi_buf_soffset),
        // (SIbuffer_atomic_fmin:{ *:[f64] } f64:{ *:[f64] }:$vdata_in, v4i32:{ *:[v4i32] }:$rsrc, 0:{ *:[i32] }, i32:{ *:[i32] }:$voffset, (BUFSOffset:{ *:[i32] } i32:{ *:[i32] }:$soffset), (timm:{ *:[i32] }):$offset, (timm:{ *:[i32] }):$auxiliary, 0:{ *:[i1] })  =>  (BUFFER_ATOMIC_FMIN_X2_VBUFFER_OFFEN_RTN:{ *:[f64] } anonymous_15036:{ *:[f64] }:$vdata_in, VGPR_32:{ *:[i32] }:$voffset, SReg_128:{ *:[v4i32] }:$rsrc, SCSrc_b32:{ *:[i32] }:$soffset, (timm:{ *:[i32] }):$offset, (extract_cpol_set_glc:{ *:[i32] } ?:{ *:[i32] }:$auxiliary))
        GIR_BuildMI, /*InsnID*/0, /*Opcode*/GIMT_Encode2(AMDGPU::BUFFER_ATOMIC_FMIN_X2_VBUFFER_OFFEN_RTN),
        GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/0, // DstI[vdata]
        GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/1, // vdata_in
        GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/4, // voffset
        GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/2, // rsrc
        GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/0, // soffset
        GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/6, // offset
        GIR_CustomOperandRenderer, /*InsnID*/0, /*OldInsnID*/0, /*OpIdx*/7, /*OperandRenderer*/GIMT_Encode2(GICR_renderExtractCpolSetGLC), // auxiliary
        GIR_MergeMemOperands, /*InsnID*/0, /*NumInsns*/1, /*MergeInsnID's*/0,
        GIR_ConstrainSelectedInstOperands, /*InsnID*/0,
        GIR_EraseFromParent, /*InsnID*/0,
        // GIR_Coverage, 5187,
        GIR_Done,
      // Label 6023: @440582
      GIM_Try, /*On fail goto*//*Label 6024*/ GIMT_Encode4(440667), // Rule ID 5259 //
        GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasUnrestrictedSOffset_isGFX90APlus),
        GIM_CheckRegBankForClass, /*MI*/0, /*Op*/0, /*RC*/GIMT_Encode2(AMDGPU::AV_64RegClassID),
        GIM_CheckConstantInt8, /*MI*/0, /*Op*/3, 0,
        // MIs[0] offset
        GIM_CheckIsImm, /*MI*/0, /*Op*/6,
        // MIs[0] auxiliary
        GIM_CheckIsImm, /*MI*/0, /*Op*/7,
        // MIs[0] Operand 8
        GIM_CheckLiteralInt, /*MI*/0, /*Op*/8, GIMT_Encode8(0),
        GIM_CheckComplexPattern, /*MI*/0, /*Op*/5, /*Renderer*/GIMT_Encode2(0), GIMT_Encode2(GICP_gi_buf_soffset),
        // (SIbuffer_atomic_fmin:{ *:[f64] } f64:{ *:[f64] }:$vdata_in, v4i32:{ *:[v4i32] }:$rsrc, 0:{ *:[i32] }, i32:{ *:[i32] }:$voffset, (BUFSOffset:{ *:[i32] } i32:{ *:[i32] }:$soffset), (timm:{ *:[i32] }):$offset, (timm:{ *:[i32] }):$auxiliary, 0:{ *:[i1] })  =>  (BUFFER_ATOMIC_MIN_F64_OFFEN_RTN:{ *:[f64] } anonymous_15036:{ *:[f64] }:$vdata_in, VGPR_32:{ *:[i32] }:$voffset, SReg_128:{ *:[v4i32] }:$rsrc, SCSrc_b32:{ *:[i32] }:$soffset, (timm:{ *:[i32] }):$offset, (extract_cpol_set_glc:{ *:[i32] } ?:{ *:[i32] }:$auxiliary))
        GIR_BuildMI, /*InsnID*/0, /*Opcode*/GIMT_Encode2(AMDGPU::BUFFER_ATOMIC_MIN_F64_OFFEN_RTN),
        GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/0, // DstI[vdata]
        GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/1, // vdata_in
        GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/4, // voffset
        GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/2, // rsrc
        GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/0, // soffset
        GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/6, // offset
        GIR_CustomOperandRenderer, /*InsnID*/0, /*OldInsnID*/0, /*OpIdx*/7, /*OperandRenderer*/GIMT_Encode2(GICR_renderExtractCpolSetGLC), // auxiliary
        GIR_MergeMemOperands, /*InsnID*/0, /*NumInsns*/1, /*MergeInsnID's*/0,
        GIR_ConstrainSelectedInstOperands, /*InsnID*/0,
        GIR_EraseFromParent, /*InsnID*/0,
        // GIR_Coverage, 5259,
        GIR_Done,
      // Label 6024: @440667
      GIM_Try, /*On fail goto*//*Label 6025*/ GIMT_Encode4(440752), // Rule ID 5267 //
        GIM_CheckFeatures, GIMT_Encode2(GIFBS_isGFX90APlus),
        GIM_CheckRegBankForClass, /*MI*/0, /*Op*/0, /*RC*/GIMT_Encode2(AMDGPU::AV_64RegClassID),
        GIM_CheckConstantInt8, /*MI*/0, /*Op*/3, 0,
        // MIs[0] offset
        GIM_CheckIsImm, /*MI*/0, /*Op*/6,
        // MIs[0] auxiliary
        GIM_CheckIsImm, /*MI*/0, /*Op*/7,
        // MIs[0] Operand 8
        GIM_CheckLiteralInt, /*MI*/0, /*Op*/8, GIMT_Encode8(0),
        GIM_CheckComplexPattern, /*MI*/0, /*Op*/5, /*Renderer*/GIMT_Encode2(0), GIMT_Encode2(GICP_gi_buf_soffset),
        // (SIbuffer_atomic_fmin:{ *:[f64] } f64:{ *:[f64] }:$vdata_in, v4i32:{ *:[v4i32] }:$rsrc, 0:{ *:[i32] }, i32:{ *:[i32] }:$voffset, (BUFSOffset:{ *:[i32] } i32:{ *:[i32] }:$soffset), (timm:{ *:[i32] }):$offset, (timm:{ *:[i32] }):$auxiliary, 0:{ *:[i1] })  =>  (BUFFER_ATOMIC_MIN_F64_VBUFFER_OFFEN_RTN:{ *:[f64] } anonymous_15036:{ *:[f64] }:$vdata_in, VGPR_32:{ *:[i32] }:$voffset, SReg_128:{ *:[v4i32] }:$rsrc, SCSrc_b32:{ *:[i32] }:$soffset, (timm:{ *:[i32] }):$offset, (extract_cpol_set_glc:{ *:[i32] } ?:{ *:[i32] }:$auxiliary))
        GIR_BuildMI, /*InsnID*/0, /*Opcode*/GIMT_Encode2(AMDGPU::BUFFER_ATOMIC_MIN_F64_VBUFFER_OFFEN_RTN),
        GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/0, // DstI[vdata]
        GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/1, // vdata_in
        GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/4, // voffset
        GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/2, // rsrc
        GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/0, // soffset
        GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/6, // offset
        GIR_CustomOperandRenderer, /*InsnID*/0, /*OldInsnID*/0, /*OpIdx*/7, /*OperandRenderer*/GIMT_Encode2(GICR_renderExtractCpolSetGLC), // auxiliary
        GIR_MergeMemOperands, /*InsnID*/0, /*NumInsns*/1, /*MergeInsnID's*/0,
        GIR_ConstrainSelectedInstOperands, /*InsnID*/0,
        GIR_EraseFromParent, /*InsnID*/0,
        // GIR_Coverage, 5267,
        GIR_Done,
      // Label 6025: @440752
      GIM_Try, /*On fail goto*//*Label 6026*/ GIMT_Encode4(440822), // Rule ID 5182 //
        GIM_CheckFeatures, GIMT_Encode2(GIFBS_isGFX6GFX7GFX10),
        GIM_CheckHasNoUse, /*MI*/0,
        GIM_CheckConstantInt8, /*MI*/0, /*Op*/4, 0,
        // MIs[0] offset
        GIM_CheckIsImm, /*MI*/0, /*Op*/6,
        // MIs[0] auxiliary
        GIM_CheckIsImm, /*MI*/0, /*Op*/7,
        // MIs[0] Operand 8
        GIM_CheckIsImm, /*MI*/0, /*Op*/8,
        GIM_CheckComplexPattern, /*MI*/0, /*Op*/5, /*Renderer*/GIMT_Encode2(0), GIMT_Encode2(GICP_gi_buf_soffset),
        // (SIbuffer_atomic_fmin:{ *:[f64] } f64:{ *:[f64] }:$vdata_in, v4i32:{ *:[v4i32] }:$rsrc, i32:{ *:[i32] }:$vindex, 0:{ *:[i32] }, (BUFSOffset:{ *:[i32] } i32:{ *:[i32] }:$soffset), (timm:{ *:[i32] }):$offset, (timm:{ *:[i32] }):$auxiliary, (timm:{ *:[i1] }))<<P:Predicate_SIbuffer_atomic_fmin_noret>>  =>  (BUFFER_ATOMIC_FMIN_X2_IDXEN anonymous_15036:{ *:[f64] }:$vdata_in, VGPR_32:{ *:[i32] }:$vindex, SReg_128:{ *:[v4i32] }:$rsrc, SCSrc_b32:{ *:[i32] }:$soffset, (timm:{ *:[i32] }):$offset, (extract_cpol:{ *:[i32] } ?:{ *:[i32] }:$auxiliary))
        GIR_BuildMI, /*InsnID*/0, /*Opcode*/GIMT_Encode2(AMDGPU::BUFFER_ATOMIC_FMIN_X2_IDXEN),
        GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/1, // vdata_in
        GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/3, // vindex
        GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/2, // rsrc
        GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/0, // soffset
        GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/6, // offset
        GIR_CustomOperandRenderer, /*InsnID*/0, /*OldInsnID*/0, /*OpIdx*/7, /*OperandRenderer*/GIMT_Encode2(GICR_renderExtractCPol), // auxiliary
        GIR_MergeMemOperands, /*InsnID*/0, /*NumInsns*/1, /*MergeInsnID's*/0,
        GIR_ConstrainSelectedInstOperands, /*InsnID*/0,
        GIR_EraseFromParent, /*InsnID*/0,
        // GIR_Coverage, 5182,
        GIR_Done,
      // Label 6026: @440822
      GIM_Try, /*On fail goto*//*Label 6027*/ GIMT_Encode4(440892), // Rule ID 5190 //
        GIM_CheckFeatures, GIMT_Encode2(GIFBS_isGFX6GFX7GFX10),
        GIM_CheckHasNoUse, /*MI*/0,
        GIM_CheckConstantInt8, /*MI*/0, /*Op*/4, 0,
        // MIs[0] offset
        GIM_CheckIsImm, /*MI*/0, /*Op*/6,
        // MIs[0] auxiliary
        GIM_CheckIsImm, /*MI*/0, /*Op*/7,
        // MIs[0] Operand 8
        GIM_CheckIsImm, /*MI*/0, /*Op*/8,
        GIM_CheckComplexPattern, /*MI*/0, /*Op*/5, /*Renderer*/GIMT_Encode2(0), GIMT_Encode2(GICP_gi_buf_soffset),
        // (SIbuffer_atomic_fmin:{ *:[f64] } f64:{ *:[f64] }:$vdata_in, v4i32:{ *:[v4i32] }:$rsrc, i32:{ *:[i32] }:$vindex, 0:{ *:[i32] }, (BUFSOffset:{ *:[i32] } i32:{ *:[i32] }:$soffset), (timm:{ *:[i32] }):$offset, (timm:{ *:[i32] }):$auxiliary, (timm:{ *:[i1] }))<<P:Predicate_SIbuffer_atomic_fmin_noret>>  =>  (BUFFER_ATOMIC_FMIN_X2_VBUFFER_IDXEN anonymous_15036:{ *:[f64] }:$vdata_in, VGPR_32:{ *:[i32] }:$vindex, SReg_128:{ *:[v4i32] }:$rsrc, SCSrc_b32:{ *:[i32] }:$soffset, (timm:{ *:[i32] }):$offset, (extract_cpol:{ *:[i32] } ?:{ *:[i32] }:$auxiliary))
        GIR_BuildMI, /*InsnID*/0, /*Opcode*/GIMT_Encode2(AMDGPU::BUFFER_ATOMIC_FMIN_X2_VBUFFER_IDXEN),
        GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/1, // vdata_in
        GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/3, // vindex
        GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/2, // rsrc
        GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/0, // soffset
        GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/6, // offset
        GIR_CustomOperandRenderer, /*InsnID*/0, /*OldInsnID*/0, /*OpIdx*/7, /*OperandRenderer*/GIMT_Encode2(GICR_renderExtractCPol), // auxiliary
        GIR_MergeMemOperands, /*InsnID*/0, /*NumInsns*/1, /*MergeInsnID's*/0,
        GIR_ConstrainSelectedInstOperands, /*InsnID*/0,
        GIR_EraseFromParent, /*InsnID*/0,
        // GIR_Coverage, 5190,
        GIR_Done,
      // Label 6027: @440892
      GIM_Try, /*On fail goto*//*Label 6028*/ GIMT_Encode4(440962), // Rule ID 5262 //
        GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasUnrestrictedSOffset_isGFX90APlus),
        GIM_CheckHasNoUse, /*MI*/0,
        GIM_CheckConstantInt8, /*MI*/0, /*Op*/4, 0,
        // MIs[0] offset
        GIM_CheckIsImm, /*MI*/0, /*Op*/6,
        // MIs[0] auxiliary
        GIM_CheckIsImm, /*MI*/0, /*Op*/7,
        // MIs[0] Operand 8
        GIM_CheckIsImm, /*MI*/0, /*Op*/8,
        GIM_CheckComplexPattern, /*MI*/0, /*Op*/5, /*Renderer*/GIMT_Encode2(0), GIMT_Encode2(GICP_gi_buf_soffset),
        // (SIbuffer_atomic_fmin:{ *:[f64] } f64:{ *:[f64] }:$vdata_in, v4i32:{ *:[v4i32] }:$rsrc, i32:{ *:[i32] }:$vindex, 0:{ *:[i32] }, (BUFSOffset:{ *:[i32] } i32:{ *:[i32] }:$soffset), (timm:{ *:[i32] }):$offset, (timm:{ *:[i32] }):$auxiliary, (timm:{ *:[i1] }))<<P:Predicate_SIbuffer_atomic_fmin_noret>>  =>  (BUFFER_ATOMIC_MIN_F64_IDXEN anonymous_15036:{ *:[f64] }:$vdata_in, VGPR_32:{ *:[i32] }:$vindex, SReg_128:{ *:[v4i32] }:$rsrc, SCSrc_b32:{ *:[i32] }:$soffset, (timm:{ *:[i32] }):$offset, (extract_cpol:{ *:[i32] } ?:{ *:[i32] }:$auxiliary))
        GIR_BuildMI, /*InsnID*/0, /*Opcode*/GIMT_Encode2(AMDGPU::BUFFER_ATOMIC_MIN_F64_IDXEN),
        GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/1, // vdata_in
        GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/3, // vindex
        GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/2, // rsrc
        GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/0, // soffset
        GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/6, // offset
        GIR_CustomOperandRenderer, /*InsnID*/0, /*OldInsnID*/0, /*OpIdx*/7, /*OperandRenderer*/GIMT_Encode2(GICR_renderExtractCPol), // auxiliary
        GIR_MergeMemOperands, /*InsnID*/0, /*NumInsns*/1, /*MergeInsnID's*/0,
        GIR_ConstrainSelectedInstOperands, /*InsnID*/0,
        GIR_EraseFromParent, /*InsnID*/0,
        // GIR_Coverage, 5262,
        GIR_Done,
      // Label 6028: @440962
      GIM_Try, /*On fail goto*//*Label 6029*/ GIMT_Encode4(441032), // Rule ID 5270 //
        GIM_CheckFeatures, GIMT_Encode2(GIFBS_isGFX90APlus),
        GIM_CheckHasNoUse, /*MI*/0,
        GIM_CheckConstantInt8, /*MI*/0, /*Op*/4, 0,
        // MIs[0] offset
        GIM_CheckIsImm, /*MI*/0, /*Op*/6,
        // MIs[0] auxiliary
        GIM_CheckIsImm, /*MI*/0, /*Op*/7,
        // MIs[0] Operand 8
        GIM_CheckIsImm, /*MI*/0, /*Op*/8,
        GIM_CheckComplexPattern, /*MI*/0, /*Op*/5, /*Renderer*/GIMT_Encode2(0), GIMT_Encode2(GICP_gi_buf_soffset),
        // (SIbuffer_atomic_fmin:{ *:[f64] } f64:{ *:[f64] }:$vdata_in, v4i32:{ *:[v4i32] }:$rsrc, i32:{ *:[i32] }:$vindex, 0:{ *:[i32] }, (BUFSOffset:{ *:[i32] } i32:{ *:[i32] }:$soffset), (timm:{ *:[i32] }):$offset, (timm:{ *:[i32] }):$auxiliary, (timm:{ *:[i1] }))<<P:Predicate_SIbuffer_atomic_fmin_noret>>  =>  (BUFFER_ATOMIC_MIN_F64_VBUFFER_IDXEN anonymous_15036:{ *:[f64] }:$vdata_in, VGPR_32:{ *:[i32] }:$vindex, SReg_128:{ *:[v4i32] }:$rsrc, SCSrc_b32:{ *:[i32] }:$soffset, (timm:{ *:[i32] }):$offset, (extract_cpol:{ *:[i32] } ?:{ *:[i32] }:$auxiliary))
        GIR_BuildMI, /*InsnID*/0, /*Opcode*/GIMT_Encode2(AMDGPU::BUFFER_ATOMIC_MIN_F64_VBUFFER_IDXEN),
        GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/1, // vdata_in
        GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/3, // vindex
        GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/2, // rsrc
        GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/0, // soffset
        GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/6, // offset
        GIR_CustomOperandRenderer, /*InsnID*/0, /*OldInsnID*/0, /*OpIdx*/7, /*OperandRenderer*/GIMT_Encode2(GICR_renderExtractCPol), // auxiliary
        GIR_MergeMemOperands, /*InsnID*/0, /*NumInsns*/1, /*MergeInsnID's*/0,
        GIR_ConstrainSelectedInstOperands, /*InsnID*/0,
        GIR_EraseFromParent, /*InsnID*/0,
        // GIR_Coverage, 5270,
        GIR_Done,
      // Label 6029: @441032
      GIM_Try, /*On fail goto*//*Label 6030*/ GIMT_Encode4(441109), // Rule ID 5178 //
        GIM_CheckFeatures, GIMT_Encode2(GIFBS_isGFX6GFX7GFX10),
        GIM_CheckRegBankForClass, /*MI*/0, /*Op*/0, /*RC*/GIMT_Encode2(AMDGPU::AV_64RegClassID),
        GIM_CheckConstantInt8, /*MI*/0, /*Op*/4, 0,
        // MIs[0] offset
        GIM_CheckIsImm, /*MI*/0, /*Op*/6,
        // MIs[0] auxiliary
        GIM_CheckIsImm, /*MI*/0, /*Op*/7,
        // MIs[0] Operand 8
        GIM_CheckIsImm, /*MI*/0, /*Op*/8,
        GIM_CheckComplexPattern, /*MI*/0, /*Op*/5, /*Renderer*/GIMT_Encode2(0), GIMT_Encode2(GICP_gi_buf_soffset),
        // (SIbuffer_atomic_fmin:{ *:[f64] } f64:{ *:[f64] }:$vdata_in, v4i32:{ *:[v4i32] }:$rsrc, i32:{ *:[i32] }:$vindex, 0:{ *:[i32] }, (BUFSOffset:{ *:[i32] } i32:{ *:[i32] }:$soffset), (timm:{ *:[i32] }):$offset, (timm:{ *:[i32] }):$auxiliary, (timm:{ *:[i1] }))  =>  (BUFFER_ATOMIC_FMIN_X2_IDXEN_RTN:{ *:[f64] } anonymous_15036:{ *:[f64] }:$vdata_in, VGPR_32:{ *:[i32] }:$vindex, SReg_128:{ *:[v4i32] }:$rsrc, SCSrc_b32:{ *:[i32] }:$soffset, (timm:{ *:[i32] }):$offset, (extract_cpol_set_glc:{ *:[i32] } ?:{ *:[i32] }:$auxiliary))
        GIR_BuildMI, /*InsnID*/0, /*Opcode*/GIMT_Encode2(AMDGPU::BUFFER_ATOMIC_FMIN_X2_IDXEN_RTN),
        GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/0, // DstI[vdata]
        GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/1, // vdata_in
        GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/3, // vindex
        GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/2, // rsrc
        GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/0, // soffset
        GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/6, // offset
        GIR_CustomOperandRenderer, /*InsnID*/0, /*OldInsnID*/0, /*OpIdx*/7, /*OperandRenderer*/GIMT_Encode2(GICR_renderExtractCpolSetGLC), // auxiliary
        GIR_MergeMemOperands, /*InsnID*/0, /*NumInsns*/1, /*MergeInsnID's*/0,
        GIR_ConstrainSelectedInstOperands, /*InsnID*/0,
        GIR_EraseFromParent, /*InsnID*/0,
        // GIR_Coverage, 5178,
        GIR_Done,
      // Label 6030: @441109
      GIM_Try, /*On fail goto*//*Label 6031*/ GIMT_Encode4(441186), // Rule ID 5186 //
        GIM_CheckFeatures, GIMT_Encode2(GIFBS_isGFX6GFX7GFX10),
        GIM_CheckRegBankForClass, /*MI*/0, /*Op*/0, /*RC*/GIMT_Encode2(AMDGPU::AV_64RegClassID),
        GIM_CheckConstantInt8, /*MI*/0, /*Op*/4, 0,
        // MIs[0] offset
        GIM_CheckIsImm, /*MI*/0, /*Op*/6,
        // MIs[0] auxiliary
        GIM_CheckIsImm, /*MI*/0, /*Op*/7,
        // MIs[0] Operand 8
        GIM_CheckIsImm, /*MI*/0, /*Op*/8,
        GIM_CheckComplexPattern, /*MI*/0, /*Op*/5, /*Renderer*/GIMT_Encode2(0), GIMT_Encode2(GICP_gi_buf_soffset),
        // (SIbuffer_atomic_fmin:{ *:[f64] } f64:{ *:[f64] }:$vdata_in, v4i32:{ *:[v4i32] }:$rsrc, i32:{ *:[i32] }:$vindex, 0:{ *:[i32] }, (BUFSOffset:{ *:[i32] } i32:{ *:[i32] }:$soffset), (timm:{ *:[i32] }):$offset, (timm:{ *:[i32] }):$auxiliary, (timm:{ *:[i1] }))  =>  (BUFFER_ATOMIC_FMIN_X2_VBUFFER_IDXEN_RTN:{ *:[f64] } anonymous_15036:{ *:[f64] }:$vdata_in, VGPR_32:{ *:[i32] }:$vindex, SReg_128:{ *:[v4i32] }:$rsrc, SCSrc_b32:{ *:[i32] }:$soffset, (timm:{ *:[i32] }):$offset, (extract_cpol_set_glc:{ *:[i32] } ?:{ *:[i32] }:$auxiliary))
        GIR_BuildMI, /*InsnID*/0, /*Opcode*/GIMT_Encode2(AMDGPU::BUFFER_ATOMIC_FMIN_X2_VBUFFER_IDXEN_RTN),
        GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/0, // DstI[vdata]
        GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/1, // vdata_in
        GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/3, // vindex
        GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/2, // rsrc
        GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/0, // soffset
        GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/6, // offset
        GIR_CustomOperandRenderer, /*InsnID*/0, /*OldInsnID*/0, /*OpIdx*/7, /*OperandRenderer*/GIMT_Encode2(GICR_renderExtractCpolSetGLC), // auxiliary
        GIR_MergeMemOperands, /*InsnID*/0, /*NumInsns*/1, /*MergeInsnID's*/0,
        GIR_ConstrainSelectedInstOperands, /*InsnID*/0,
        GIR_EraseFromParent, /*InsnID*/0,
        // GIR_Coverage, 5186,
        GIR_Done,
      // Label 6031: @441186
      GIM_Try, /*On fail goto*//*Label 6032*/ GIMT_Encode4(441263), // Rule ID 5258 //
        GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasUnrestrictedSOffset_isGFX90APlus),
        GIM_CheckRegBankForClass, /*MI*/0, /*Op*/0, /*RC*/GIMT_Encode2(AMDGPU::AV_64RegClassID),
        GIM_CheckConstantInt8, /*MI*/0, /*Op*/4, 0,
        // MIs[0] offset
        GIM_CheckIsImm, /*MI*/0, /*Op*/6,
        // MIs[0] auxiliary
        GIM_CheckIsImm, /*MI*/0, /*Op*/7,
        // MIs[0] Operand 8
        GIM_CheckIsImm, /*MI*/0, /*Op*/8,
        GIM_CheckComplexPattern, /*MI*/0, /*Op*/5, /*Renderer*/GIMT_Encode2(0), GIMT_Encode2(GICP_gi_buf_soffset),
        // (SIbuffer_atomic_fmin:{ *:[f64] } f64:{ *:[f64] }:$vdata_in, v4i32:{ *:[v4i32] }:$rsrc, i32:{ *:[i32] }:$vindex, 0:{ *:[i32] }, (BUFSOffset:{ *:[i32] } i32:{ *:[i32] }:$soffset), (timm:{ *:[i32] }):$offset, (timm:{ *:[i32] }):$auxiliary, (timm:{ *:[i1] }))  =>  (BUFFER_ATOMIC_MIN_F64_IDXEN_RTN:{ *:[f64] } anonymous_15036:{ *:[f64] }:$vdata_in, VGPR_32:{ *:[i32] }:$vindex, SReg_128:{ *:[v4i32] }:$rsrc, SCSrc_b32:{ *:[i32] }:$soffset, (timm:{ *:[i32] }):$offset, (extract_cpol_set_glc:{ *:[i32] } ?:{ *:[i32] }:$auxiliary))
        GIR_BuildMI, /*InsnID*/0, /*Opcode*/GIMT_Encode2(AMDGPU::BUFFER_ATOMIC_MIN_F64_IDXEN_RTN),
        GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/0, // DstI[vdata]
        GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/1, // vdata_in
        GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/3, // vindex
        GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/2, // rsrc
        GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/0, // soffset
        GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/6, // offset
        GIR_CustomOperandRenderer, /*InsnID*/0, /*OldInsnID*/0, /*OpIdx*/7, /*OperandRenderer*/GIMT_Encode2(GICR_renderExtractCpolSetGLC), // auxiliary
        GIR_MergeMemOperands, /*InsnID*/0, /*NumInsns*/1, /*MergeInsnID's*/0,
        GIR_ConstrainSelectedInstOperands, /*InsnID*/0,
        GIR_EraseFromParent, /*InsnID*/0,
        // GIR_Coverage, 5258,
        GIR_Done,
      // Label 6032: @441263
      GIM_Try, /*On fail goto*//*Label 6033*/ GIMT_Encode4(441340), // Rule ID 5266 //
        GIM_CheckFeatures, GIMT_Encode2(GIFBS_isGFX90APlus),
        GIM_CheckRegBankForClass, /*MI*/0, /*Op*/0, /*RC*/GIMT_Encode2(AMDGPU::AV_64RegClassID),
        GIM_CheckConstantInt8, /*MI*/0, /*Op*/4, 0,
        // MIs[0] offset
        GIM_CheckIsImm, /*MI*/0, /*Op*/6,
        // MIs[0] auxiliary
        GIM_CheckIsImm, /*MI*/0, /*Op*/7,
        // MIs[0] Operand 8
        GIM_CheckIsImm, /*MI*/0, /*Op*/8,
        GIM_CheckComplexPattern, /*MI*/0, /*Op*/5, /*Renderer*/GIMT_Encode2(0), GIMT_Encode2(GICP_gi_buf_soffset),
        // (SIbuffer_atomic_fmin:{ *:[f64] } f64:{ *:[f64] }:$vdata_in, v4i32:{ *:[v4i32] }:$rsrc, i32:{ *:[i32] }:$vindex, 0:{ *:[i32] }, (BUFSOffset:{ *:[i32] } i32:{ *:[i32] }:$soffset), (timm:{ *:[i32] }):$offset, (timm:{ *:[i32] }):$auxiliary, (timm:{ *:[i1] }))  =>  (BUFFER_ATOMIC_MIN_F64_VBUFFER_IDXEN_RTN:{ *:[f64] } anonymous_15036:{ *:[f64] }:$vdata_in, VGPR_32:{ *:[i32] }:$vindex, SReg_128:{ *:[v4i32] }:$rsrc, SCSrc_b32:{ *:[i32] }:$soffset, (timm:{ *:[i32] }):$offset, (extract_cpol_set_glc:{ *:[i32] } ?:{ *:[i32] }:$auxiliary))
        GIR_BuildMI, /*InsnID*/0, /*Opcode*/GIMT_Encode2(AMDGPU::BUFFER_ATOMIC_MIN_F64_VBUFFER_IDXEN_RTN),
        GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/0, // DstI[vdata]
        GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/1, // vdata_in
        GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/3, // vindex
        GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/2, // rsrc
        GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/0, // soffset
        GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/6, // offset
        GIR_CustomOperandRenderer, /*InsnID*/0, /*OldInsnID*/0, /*OpIdx*/7, /*OperandRenderer*/GIMT_Encode2(GICR_renderExtractCpolSetGLC), // auxiliary
        GIR_MergeMemOperands, /*InsnID*/0, /*NumInsns*/1, /*MergeInsnID's*/0,
        GIR_ConstrainSelectedInstOperands, /*InsnID*/0,
        GIR_EraseFromParent, /*InsnID*/0,
        // GIR_Coverage, 5266,
        GIR_Done,
      // Label 6033: @441340
      GIM_Try, /*On fail goto*//*Label 6034*/ GIMT_Encode4(441446), // Rule ID 5184 //
        GIM_CheckFeatures, GIMT_Encode2(GIFBS_isGFX6GFX7GFX10),
        GIM_CheckHasNoUse, /*MI*/0,
        // MIs[0] offset
        GIM_CheckIsImm, /*MI*/0, /*Op*/6,
        // MIs[0] auxiliary
        GIM_CheckIsImm, /*MI*/0, /*Op*/7,
        // MIs[0] Operand 8
        GIM_CheckIsImm, /*MI*/0, /*Op*/8,
        GIM_CheckComplexPattern, /*MI*/0, /*Op*/5, /*Renderer*/GIMT_Encode2(0), GIMT_Encode2(GICP_gi_buf_soffset),
        // (SIbuffer_atomic_fmin:{ *:[f64] } f64:{ *:[f64] }:$vdata_in, v4i32:{ *:[v4i32] }:$rsrc, i32:{ *:[i32] }:$vindex, i32:{ *:[i32] }:$voffset, (BUFSOffset:{ *:[i32] } i32:{ *:[i32] }:$soffset), (timm:{ *:[i32] }):$offset, (timm:{ *:[i32] }):$auxiliary, (timm:{ *:[i1] }))<<P:Predicate_SIbuffer_atomic_fmin_noret>>  =>  (BUFFER_ATOMIC_FMIN_X2_BOTHEN anonymous_15036:{ *:[f64] }:$vdata_in, (REG_SEQUENCE:{ *:[i64] } VReg_64:{ *:[i32] }, VGPR_32:{ *:[i32] }:$vindex, sub0:{ *:[i32] }, VGPR_32:{ *:[i32] }:$voffset, sub1:{ *:[i32] }), SReg_128:{ *:[v4i32] }:$rsrc, SCSrc_b32:{ *:[i32] }:$soffset, (timm:{ *:[i32] }):$offset, (extract_cpol:{ *:[i32] } ?:{ *:[i32] }:$auxiliary))
        GIR_MakeTempReg, /*TempRegID*/0, /*TypeID*/GILLT_s64,
        GIR_BuildMI, /*InsnID*/1, /*Opcode*/GIMT_Encode2(TargetOpcode::REG_SEQUENCE),
        GIR_AddTempRegister, /*InsnID*/1, /*TempRegID*/0, /*TempRegFlags*/GIMT_Encode2(RegState::Define),
        GIR_Copy, /*NewInsnID*/1, /*OldInsnID*/0, /*OpIdx*/3, // vindex
        GIR_AddImm8, /*InsnID*/1, /*SubRegIndex*/3,
        GIR_Copy, /*NewInsnID*/1, /*OldInsnID*/0, /*OpIdx*/4, // voffset
        GIR_AddImm8, /*InsnID*/1, /*SubRegIndex*/11,
        GIR_ConstrainOperandRC, /*InsnID*/1, /*Op*/0, GIMT_Encode2(AMDGPU::VReg_64RegClassID),
        GIR_ConstrainOperandRC, /*InsnID*/1, /*Op*/1, GIMT_Encode2(AMDGPU::VGPR_32RegClassID),
        GIR_ConstrainOperandRC, /*InsnID*/1, /*Op*/3, GIMT_Encode2(AMDGPU::VGPR_32RegClassID),
        GIR_BuildMI, /*InsnID*/0, /*Opcode*/GIMT_Encode2(AMDGPU::BUFFER_ATOMIC_FMIN_X2_BOTHEN),
        GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/1, // vdata_in
        GIR_AddSimpleTempRegister, /*InsnID*/0, /*TempRegID*/0,
        GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/2, // rsrc
        GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/0, // soffset
        GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/6, // offset
        GIR_CustomOperandRenderer, /*InsnID*/0, /*OldInsnID*/0, /*OpIdx*/7, /*OperandRenderer*/GIMT_Encode2(GICR_renderExtractCPol), // auxiliary
        GIR_MergeMemOperands, /*InsnID*/0, /*NumInsns*/1, /*MergeInsnID's*/0,
        GIR_ConstrainSelectedInstOperands, /*InsnID*/0,
        GIR_EraseFromParent, /*InsnID*/0,
        // GIR_Coverage, 5184,
        GIR_Done,
      // Label 6034: @441446
      GIM_Try, /*On fail goto*//*Label 6035*/ GIMT_Encode4(441552), // Rule ID 5192 //
        GIM_CheckFeatures, GIMT_Encode2(GIFBS_isGFX6GFX7GFX10),
        GIM_CheckHasNoUse, /*MI*/0,
        // MIs[0] offset
        GIM_CheckIsImm, /*MI*/0, /*Op*/6,
        // MIs[0] auxiliary
        GIM_CheckIsImm, /*MI*/0, /*Op*/7,
        // MIs[0] Operand 8
        GIM_CheckIsImm, /*MI*/0, /*Op*/8,
        GIM_CheckComplexPattern, /*MI*/0, /*Op*/5, /*Renderer*/GIMT_Encode2(0), GIMT_Encode2(GICP_gi_buf_soffset),
        // (SIbuffer_atomic_fmin:{ *:[f64] } f64:{ *:[f64] }:$vdata_in, v4i32:{ *:[v4i32] }:$rsrc, i32:{ *:[i32] }:$vindex, i32:{ *:[i32] }:$voffset, (BUFSOffset:{ *:[i32] } i32:{ *:[i32] }:$soffset), (timm:{ *:[i32] }):$offset, (timm:{ *:[i32] }):$auxiliary, (timm:{ *:[i1] }))<<P:Predicate_SIbuffer_atomic_fmin_noret>>  =>  (BUFFER_ATOMIC_FMIN_X2_VBUFFER_BOTHEN anonymous_15036:{ *:[f64] }:$vdata_in, (REG_SEQUENCE:{ *:[i64] } VReg_64:{ *:[i32] }, VGPR_32:{ *:[i32] }:$vindex, sub0:{ *:[i32] }, VGPR_32:{ *:[i32] }:$voffset, sub1:{ *:[i32] }), SReg_128:{ *:[v4i32] }:$rsrc, SCSrc_b32:{ *:[i32] }:$soffset, (timm:{ *:[i32] }):$offset, (extract_cpol:{ *:[i32] } ?:{ *:[i32] }:$auxiliary))
        GIR_MakeTempReg, /*TempRegID*/0, /*TypeID*/GILLT_s64,
        GIR_BuildMI, /*InsnID*/1, /*Opcode*/GIMT_Encode2(TargetOpcode::REG_SEQUENCE),
        GIR_AddTempRegister, /*InsnID*/1, /*TempRegID*/0, /*TempRegFlags*/GIMT_Encode2(RegState::Define),
        GIR_Copy, /*NewInsnID*/1, /*OldInsnID*/0, /*OpIdx*/3, // vindex
        GIR_AddImm8, /*InsnID*/1, /*SubRegIndex*/3,
        GIR_Copy, /*NewInsnID*/1, /*OldInsnID*/0, /*OpIdx*/4, // voffset
        GIR_AddImm8, /*InsnID*/1, /*SubRegIndex*/11,
        GIR_ConstrainOperandRC, /*InsnID*/1, /*Op*/0, GIMT_Encode2(AMDGPU::VReg_64RegClassID),
        GIR_ConstrainOperandRC, /*InsnID*/1, /*Op*/1, GIMT_Encode2(AMDGPU::VGPR_32RegClassID),
        GIR_ConstrainOperandRC, /*InsnID*/1, /*Op*/3, GIMT_Encode2(AMDGPU::VGPR_32RegClassID),
        GIR_BuildMI, /*InsnID*/0, /*Opcode*/GIMT_Encode2(AMDGPU::BUFFER_ATOMIC_FMIN_X2_VBUFFER_BOTHEN),
        GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/1, // vdata_in
        GIR_AddSimpleTempRegister, /*InsnID*/0, /*TempRegID*/0,
        GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/2, // rsrc
        GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/0, // soffset
        GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/6, // offset
        GIR_CustomOperandRenderer, /*InsnID*/0, /*OldInsnID*/0, /*OpIdx*/7, /*OperandRenderer*/GIMT_Encode2(GICR_renderExtractCPol), // auxiliary
        GIR_MergeMemOperands, /*InsnID*/0, /*NumInsns*/1, /*MergeInsnID's*/0,
        GIR_ConstrainSelectedInstOperands, /*InsnID*/0,
        GIR_EraseFromParent, /*InsnID*/0,
        // GIR_Coverage, 5192,
        GIR_Done,
      // Label 6035: @441552
      GIM_Try, /*On fail goto*//*Label 6036*/ GIMT_Encode4(441658), // Rule ID 5264 //
        GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasUnrestrictedSOffset_isGFX90APlus),
        GIM_CheckHasNoUse, /*MI*/0,
        // MIs[0] offset
        GIM_CheckIsImm, /*MI*/0, /*Op*/6,
        // MIs[0] auxiliary
        GIM_CheckIsImm, /*MI*/0, /*Op*/7,
        // MIs[0] Operand 8
        GIM_CheckIsImm, /*MI*/0, /*Op*/8,
        GIM_CheckComplexPattern, /*MI*/0, /*Op*/5, /*Renderer*/GIMT_Encode2(0), GIMT_Encode2(GICP_gi_buf_soffset),
        // (SIbuffer_atomic_fmin:{ *:[f64] } f64:{ *:[f64] }:$vdata_in, v4i32:{ *:[v4i32] }:$rsrc, i32:{ *:[i32] }:$vindex, i32:{ *:[i32] }:$voffset, (BUFSOffset:{ *:[i32] } i32:{ *:[i32] }:$soffset), (timm:{ *:[i32] }):$offset, (timm:{ *:[i32] }):$auxiliary, (timm:{ *:[i1] }))<<P:Predicate_SIbuffer_atomic_fmin_noret>>  =>  (BUFFER_ATOMIC_MIN_F64_BOTHEN anonymous_15036:{ *:[f64] }:$vdata_in, (REG_SEQUENCE:{ *:[i64] } VReg_64:{ *:[i32] }, VGPR_32:{ *:[i32] }:$vindex, sub0:{ *:[i32] }, VGPR_32:{ *:[i32] }:$voffset, sub1:{ *:[i32] }), SReg_128:{ *:[v4i32] }:$rsrc, SCSrc_b32:{ *:[i32] }:$soffset, (timm:{ *:[i32] }):$offset, (extract_cpol:{ *:[i32] } ?:{ *:[i32] }:$auxiliary))
        GIR_MakeTempReg, /*TempRegID*/0, /*TypeID*/GILLT_s64,
        GIR_BuildMI, /*InsnID*/1, /*Opcode*/GIMT_Encode2(TargetOpcode::REG_SEQUENCE),
        GIR_AddTempRegister, /*InsnID*/1, /*TempRegID*/0, /*TempRegFlags*/GIMT_Encode2(RegState::Define),
        GIR_Copy, /*NewInsnID*/1, /*OldInsnID*/0, /*OpIdx*/3, // vindex
        GIR_AddImm8, /*InsnID*/1, /*SubRegIndex*/3,
        GIR_Copy, /*NewInsnID*/1, /*OldInsnID*/0, /*OpIdx*/4, // voffset
        GIR_AddImm8, /*InsnID*/1, /*SubRegIndex*/11,
        GIR_ConstrainOperandRC, /*InsnID*/1, /*Op*/0, GIMT_Encode2(AMDGPU::VReg_64RegClassID),
        GIR_ConstrainOperandRC, /*InsnID*/1, /*Op*/1, GIMT_Encode2(AMDGPU::VGPR_32RegClassID),
        GIR_ConstrainOperandRC, /*InsnID*/1, /*Op*/3, GIMT_Encode2(AMDGPU::VGPR_32RegClassID),
        GIR_BuildMI, /*InsnID*/0, /*Opcode*/GIMT_Encode2(AMDGPU::BUFFER_ATOMIC_MIN_F64_BOTHEN),
        GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/1, // vdata_in
        GIR_AddSimpleTempRegister, /*InsnID*/0, /*TempRegID*/0,
        GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/2, // rsrc
        GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/0, // soffset
        GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/6, // offset
        GIR_CustomOperandRenderer, /*InsnID*/0, /*OldInsnID*/0, /*OpIdx*/7, /*OperandRenderer*/GIMT_Encode2(GICR_renderExtractCPol), // auxiliary
        GIR_MergeMemOperands, /*InsnID*/0, /*NumInsns*/1, /*MergeInsnID's*/0,
        GIR_ConstrainSelectedInstOperands, /*InsnID*/0,
        GIR_EraseFromParent, /*InsnID*/0,
        // GIR_Coverage, 5264,
        GIR_Done,
      // Label 6036: @441658
      GIM_Try, /*On fail goto*//*Label 6037*/ GIMT_Encode4(441764), // Rule ID 5272 //
        GIM_CheckFeatures, GIMT_Encode2(GIFBS_isGFX90APlus),
        GIM_CheckHasNoUse, /*MI*/0,
        // MIs[0] offset
        GIM_CheckIsImm, /*MI*/0, /*Op*/6,
        // MIs[0] auxiliary
        GIM_CheckIsImm, /*MI*/0, /*Op*/7,
        // MIs[0] Operand 8
        GIM_CheckIsImm, /*MI*/0, /*Op*/8,
        GIM_CheckComplexPattern, /*MI*/0, /*Op*/5, /*Renderer*/GIMT_Encode2(0), GIMT_Encode2(GICP_gi_buf_soffset),
        // (SIbuffer_atomic_fmin:{ *:[f64] } f64:{ *:[f64] }:$vdata_in, v4i32:{ *:[v4i32] }:$rsrc, i32:{ *:[i32] }:$vindex, i32:{ *:[i32] }:$voffset, (BUFSOffset:{ *:[i32] } i32:{ *:[i32] }:$soffset), (timm:{ *:[i32] }):$offset, (timm:{ *:[i32] }):$auxiliary, (timm:{ *:[i1] }))<<P:Predicate_SIbuffer_atomic_fmin_noret>>  =>  (BUFFER_ATOMIC_MIN_F64_VBUFFER_BOTHEN anonymous_15036:{ *:[f64] }:$vdata_in, (REG_SEQUENCE:{ *:[i64] } VReg_64:{ *:[i32] }, VGPR_32:{ *:[i32] }:$vindex, sub0:{ *:[i32] }, VGPR_32:{ *:[i32] }:$voffset, sub1:{ *:[i32] }), SReg_128:{ *:[v4i32] }:$rsrc, SCSrc_b32:{ *:[i32] }:$soffset, (timm:{ *:[i32] }):$offset, (extract_cpol:{ *:[i32] } ?:{ *:[i32] }:$auxiliary))
        GIR_MakeTempReg, /*TempRegID*/0, /*TypeID*/GILLT_s64,
        GIR_BuildMI, /*InsnID*/1, /*Opcode*/GIMT_Encode2(TargetOpcode::REG_SEQUENCE),
        GIR_AddTempRegister, /*InsnID*/1, /*TempRegID*/0, /*TempRegFlags*/GIMT_Encode2(RegState::Define),
        GIR_Copy, /*NewInsnID*/1, /*OldInsnID*/0, /*OpIdx*/3, // vindex
        GIR_AddImm8, /*InsnID*/1, /*SubRegIndex*/3,
        GIR_Copy, /*NewInsnID*/1, /*OldInsnID*/0, /*OpIdx*/4, // voffset
        GIR_AddImm8, /*InsnID*/1, /*SubRegIndex*/11,
        GIR_ConstrainOperandRC, /*InsnID*/1, /*Op*/0, GIMT_Encode2(AMDGPU::VReg_64RegClassID),
        GIR_ConstrainOperandRC, /*InsnID*/1, /*Op*/1, GIMT_Encode2(AMDGPU::VGPR_32RegClassID),
        GIR_ConstrainOperandRC, /*InsnID*/1, /*Op*/3, GIMT_Encode2(AMDGPU::VGPR_32RegClassID),
        GIR_BuildMI, /*InsnID*/0, /*Opcode*/GIMT_Encode2(AMDGPU::BUFFER_ATOMIC_MIN_F64_VBUFFER_BOTHEN),
        GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/1, // vdata_in
        GIR_AddSimpleTempRegister, /*InsnID*/0, /*TempRegID*/0,
        GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/2, // rsrc
        GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/0, // soffset
        GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/6, // offset
        GIR_CustomOperandRenderer, /*InsnID*/0, /*OldInsnID*/0, /*OpIdx*/7, /*OperandRenderer*/GIMT_Encode2(GICR_renderExtractCPol), // auxiliary
        GIR_MergeMemOperands, /*InsnID*/0, /*NumInsns*/1, /*MergeInsnID's*/0,
        GIR_ConstrainSelectedInstOperands, /*InsnID*/0,
        GIR_EraseFromParent, /*InsnID*/0,
        // GIR_Coverage, 5272,
        GIR_Done,
      // Label 6037: @441764
      GIM_Try, /*On fail goto*//*Label 6038*/ GIMT_Encode4(441877), // Rule ID 5180 //
        GIM_CheckFeatures, GIMT_Encode2(GIFBS_isGFX6GFX7GFX10),
        GIM_CheckRegBankForClass, /*MI*/0, /*Op*/0, /*RC*/GIMT_Encode2(AMDGPU::AV_64RegClassID),
        // MIs[0] offset
        GIM_CheckIsImm, /*MI*/0, /*Op*/6,
        // MIs[0] auxiliary
        GIM_CheckIsImm, /*MI*/0, /*Op*/7,
        // MIs[0] Operand 8
        GIM_CheckIsImm, /*MI*/0, /*Op*/8,
        GIM_CheckComplexPattern, /*MI*/0, /*Op*/5, /*Renderer*/GIMT_Encode2(0), GIMT_Encode2(GICP_gi_buf_soffset),
        // (SIbuffer_atomic_fmin:{ *:[f64] } f64:{ *:[f64] }:$vdata_in, v4i32:{ *:[v4i32] }:$rsrc, i32:{ *:[i32] }:$vindex, i32:{ *:[i32] }:$voffset, (BUFSOffset:{ *:[i32] } i32:{ *:[i32] }:$soffset), (timm:{ *:[i32] }):$offset, (timm:{ *:[i32] }):$auxiliary, (timm:{ *:[i1] }))  =>  (BUFFER_ATOMIC_FMIN_X2_BOTHEN_RTN:{ *:[f64] } anonymous_15036:{ *:[f64] }:$vdata_in, (REG_SEQUENCE:{ *:[i64] } VReg_64:{ *:[i32] }, VGPR_32:{ *:[i32] }:$vindex, sub0:{ *:[i32] }, VGPR_32:{ *:[i32] }:$voffset, sub1:{ *:[i32] }), SReg_128:{ *:[v4i32] }:$rsrc, SCSrc_b32:{ *:[i32] }:$soffset, (timm:{ *:[i32] }):$offset, (extract_cpol_set_glc:{ *:[i32] } ?:{ *:[i32] }:$auxiliary))
        GIR_MakeTempReg, /*TempRegID*/0, /*TypeID*/GILLT_s64,
        GIR_BuildMI, /*InsnID*/1, /*Opcode*/GIMT_Encode2(TargetOpcode::REG_SEQUENCE),
        GIR_AddTempRegister, /*InsnID*/1, /*TempRegID*/0, /*TempRegFlags*/GIMT_Encode2(RegState::Define),
        GIR_Copy, /*NewInsnID*/1, /*OldInsnID*/0, /*OpIdx*/3, // vindex
        GIR_AddImm8, /*InsnID*/1, /*SubRegIndex*/3,
        GIR_Copy, /*NewInsnID*/1, /*OldInsnID*/0, /*OpIdx*/4, // voffset
        GIR_AddImm8, /*InsnID*/1, /*SubRegIndex*/11,
        GIR_ConstrainOperandRC, /*InsnID*/1, /*Op*/0, GIMT_Encode2(AMDGPU::VReg_64RegClassID),
        GIR_ConstrainOperandRC, /*InsnID*/1, /*Op*/1, GIMT_Encode2(AMDGPU::VGPR_32RegClassID),
        GIR_ConstrainOperandRC, /*InsnID*/1, /*Op*/3, GIMT_Encode2(AMDGPU::VGPR_32RegClassID),
        GIR_BuildMI, /*InsnID*/0, /*Opcode*/GIMT_Encode2(AMDGPU::BUFFER_ATOMIC_FMIN_X2_BOTHEN_RTN),
        GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/0, // DstI[vdata]
        GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/1, // vdata_in
        GIR_AddSimpleTempRegister, /*InsnID*/0, /*TempRegID*/0,
        GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/2, // rsrc
        GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/0, // soffset
        GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/6, // offset
        GIR_CustomOperandRenderer, /*InsnID*/0, /*OldInsnID*/0, /*OpIdx*/7, /*OperandRenderer*/GIMT_Encode2(GICR_renderExtractCpolSetGLC), // auxiliary
        GIR_MergeMemOperands, /*InsnID*/0, /*NumInsns*/1, /*MergeInsnID's*/0,
        GIR_ConstrainSelectedInstOperands, /*InsnID*/0,
        GIR_EraseFromParent, /*InsnID*/0,
        // GIR_Coverage, 5180,
        GIR_Done,
      // Label 6038: @441877
      GIM_Try, /*On fail goto*//*Label 6039*/ GIMT_Encode4(441990), // Rule ID 5188 //
        GIM_CheckFeatures, GIMT_Encode2(GIFBS_isGFX6GFX7GFX10),
        GIM_CheckRegBankForClass, /*MI*/0, /*Op*/0, /*RC*/GIMT_Encode2(AMDGPU::AV_64RegClassID),
        // MIs[0] offset
        GIM_CheckIsImm, /*MI*/0, /*Op*/6,
        // MIs[0] auxiliary
        GIM_CheckIsImm, /*MI*/0, /*Op*/7,
        // MIs[0] Operand 8
        GIM_CheckIsImm, /*MI*/0, /*Op*/8,
        GIM_CheckComplexPattern, /*MI*/0, /*Op*/5, /*Renderer*/GIMT_Encode2(0), GIMT_Encode2(GICP_gi_buf_soffset),
        // (SIbuffer_atomic_fmin:{ *:[f64] } f64:{ *:[f64] }:$vdata_in, v4i32:{ *:[v4i32] }:$rsrc, i32:{ *:[i32] }:$vindex, i32:{ *:[i32] }:$voffset, (BUFSOffset:{ *:[i32] } i32:{ *:[i32] }:$soffset), (timm:{ *:[i32] }):$offset, (timm:{ *:[i32] }):$auxiliary, (timm:{ *:[i1] }))  =>  (BUFFER_ATOMIC_FMIN_X2_VBUFFER_BOTHEN_RTN:{ *:[f64] } anonymous_15036:{ *:[f64] }:$vdata_in, (REG_SEQUENCE:{ *:[i64] } VReg_64:{ *:[i32] }, VGPR_32:{ *:[i32] }:$vindex, sub0:{ *:[i32] }, VGPR_32:{ *:[i32] }:$voffset, sub1:{ *:[i32] }), SReg_128:{ *:[v4i32] }:$rsrc, SCSrc_b32:{ *:[i32] }:$soffset, (timm:{ *:[i32] }):$offset, (extract_cpol_set_glc:{ *:[i32] } ?:{ *:[i32] }:$auxiliary))
        GIR_MakeTempReg, /*TempRegID*/0, /*TypeID*/GILLT_s64,
        GIR_BuildMI, /*InsnID*/1, /*Opcode*/GIMT_Encode2(TargetOpcode::REG_SEQUENCE),
        GIR_AddTempRegister, /*InsnID*/1, /*TempRegID*/0, /*TempRegFlags*/GIMT_Encode2(RegState::Define),
        GIR_Copy, /*NewInsnID*/1, /*OldInsnID*/0, /*OpIdx*/3, // vindex
        GIR_AddImm8, /*InsnID*/1, /*SubRegIndex*/3,
        GIR_Copy, /*NewInsnID*/1, /*OldInsnID*/0, /*OpIdx*/4, // voffset
        GIR_AddImm8, /*InsnID*/1, /*SubRegIndex*/11,
        GIR_ConstrainOperandRC, /*InsnID*/1, /*Op*/0, GIMT_Encode2(AMDGPU::VReg_64RegClassID),
        GIR_ConstrainOperandRC, /*InsnID*/1, /*Op*/1, GIMT_Encode2(AMDGPU::VGPR_32RegClassID),
        GIR_ConstrainOperandRC, /*InsnID*/1, /*Op*/3, GIMT_Encode2(AMDGPU::VGPR_32RegClassID),
        GIR_BuildMI, /*InsnID*/0, /*Opcode*/GIMT_Encode2(AMDGPU::BUFFER_ATOMIC_FMIN_X2_VBUFFER_BOTHEN_RTN),
        GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/0, // DstI[vdata]
        GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/1, // vdata_in
        GIR_AddSimpleTempRegister, /*InsnID*/0, /*TempRegID*/0,
        GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/2, // rsrc
        GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/0, // soffset
        GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/6, // offset
        GIR_CustomOperandRenderer, /*InsnID*/0, /*OldInsnID*/0, /*OpIdx*/7, /*OperandRenderer*/GIMT_Encode2(GICR_renderExtractCpolSetGLC), // auxiliary
        GIR_MergeMemOperands, /*InsnID*/0, /*NumInsns*/1, /*MergeInsnID's*/0,
        GIR_ConstrainSelectedInstOperands, /*InsnID*/0,
        GIR_EraseFromParent, /*InsnID*/0,
        // GIR_Coverage, 5188,
        GIR_Done,
      // Label 6039: @441990
      GIM_Try, /*On fail goto*//*Label 6040*/ GIMT_Encode4(442103), // Rule ID 5260 //
        GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasUnrestrictedSOffset_isGFX90APlus),
        GIM_CheckRegBankForClass, /*MI*/0, /*Op*/0, /*RC*/GIMT_Encode2(AMDGPU::AV_64RegClassID),
        // MIs[0] offset
        GIM_CheckIsImm, /*MI*/0, /*Op*/6,
        // MIs[0] auxiliary
        GIM_CheckIsImm, /*MI*/0, /*Op*/7,
        // MIs[0] Operand 8
        GIM_CheckIsImm, /*MI*/0, /*Op*/8,
        GIM_CheckComplexPattern, /*MI*/0, /*Op*/5, /*Renderer*/GIMT_Encode2(0), GIMT_Encode2(GICP_gi_buf_soffset),
        // (SIbuffer_atomic_fmin:{ *:[f64] } f64:{ *:[f64] }:$vdata_in, v4i32:{ *:[v4i32] }:$rsrc, i32:{ *:[i32] }:$vindex, i32:{ *:[i32] }:$voffset, (BUFSOffset:{ *:[i32] } i32:{ *:[i32] }:$soffset), (timm:{ *:[i32] }):$offset, (timm:{ *:[i32] }):$auxiliary, (timm:{ *:[i1] }))  =>  (BUFFER_ATOMIC_MIN_F64_BOTHEN_RTN:{ *:[f64] } anonymous_15036:{ *:[f64] }:$vdata_in, (REG_SEQUENCE:{ *:[i64] } VReg_64:{ *:[i32] }, VGPR_32:{ *:[i32] }:$vindex, sub0:{ *:[i32] }, VGPR_32:{ *:[i32] }:$voffset, sub1:{ *:[i32] }), SReg_128:{ *:[v4i32] }:$rsrc, SCSrc_b32:{ *:[i32] }:$soffset, (timm:{ *:[i32] }):$offset, (extract_cpol_set_glc:{ *:[i32] } ?:{ *:[i32] }:$auxiliary))
        GIR_MakeTempReg, /*TempRegID*/0, /*TypeID*/GILLT_s64,
        GIR_BuildMI, /*InsnID*/1, /*Opcode*/GIMT_Encode2(TargetOpcode::REG_SEQUENCE),
        GIR_AddTempRegister, /*InsnID*/1, /*TempRegID*/0, /*TempRegFlags*/GIMT_Encode2(RegState::Define),
        GIR_Copy, /*NewInsnID*/1, /*OldInsnID*/0, /*OpIdx*/3, // vindex
        GIR_AddImm8, /*InsnID*/1, /*SubRegIndex*/3,
        GIR_Copy, /*NewInsnID*/1, /*OldInsnID*/0, /*OpIdx*/4, // voffset
        GIR_AddImm8, /*InsnID*/1, /*SubRegIndex*/11,
        GIR_ConstrainOperandRC, /*InsnID*/1, /*Op*/0, GIMT_Encode2(AMDGPU::VReg_64RegClassID),
        GIR_ConstrainOperandRC, /*InsnID*/1, /*Op*/1, GIMT_Encode2(AMDGPU::VGPR_32RegClassID),
        GIR_ConstrainOperandRC, /*InsnID*/1, /*Op*/3, GIMT_Encode2(AMDGPU::VGPR_32RegClassID),
        GIR_BuildMI, /*InsnID*/0, /*Opcode*/GIMT_Encode2(AMDGPU::BUFFER_ATOMIC_MIN_F64_BOTHEN_RTN),
        GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/0, // DstI[vdata]
        GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/1, // vdata_in
        GIR_AddSimpleTempRegister, /*InsnID*/0, /*TempRegID*/0,
        GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/2, // rsrc
        GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/0, // soffset
        GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/6, // offset
        GIR_CustomOperandRenderer, /*InsnID*/0, /*OldInsnID*/0, /*OpIdx*/7, /*OperandRenderer*/GIMT_Encode2(GICR_renderExtractCpolSetGLC), // auxiliary
        GIR_MergeMemOperands, /*InsnID*/0, /*NumInsns*/1, /*MergeInsnID's*/0,
        GIR_ConstrainSelectedInstOperands, /*InsnID*/0,
        GIR_EraseFromParent, /*InsnID*/0,
        // GIR_Coverage, 5260,
        GIR_Done,
      // Label 6040: @442103
      GIM_Try, /*On fail goto*//*Label 6041*/ GIMT_Encode4(442216), // Rule ID 5268 //
        GIM_CheckFeatures, GIMT_Encode2(GIFBS_isGFX90APlus),
        GIM_CheckRegBankForClass, /*MI*/0, /*Op*/0, /*RC*/GIMT_Encode2(AMDGPU::AV_64RegClassID),
        // MIs[0] offset
        GIM_CheckIsImm, /*MI*/0, /*Op*/6,
        // MIs[0] auxiliary
        GIM_CheckIsImm, /*MI*/0, /*Op*/7,
        // MIs[0] Operand 8
        GIM_CheckIsImm, /*MI*/0, /*Op*/8,
        GIM_CheckComplexPattern, /*MI*/0, /*Op*/5, /*Renderer*/GIMT_Encode2(0), GIMT_Encode2(GICP_gi_buf_soffset),
        // (SIbuffer_atomic_fmin:{ *:[f64] } f64:{ *:[f64] }:$vdata_in, v4i32:{ *:[v4i32] }:$rsrc, i32:{ *:[i32] }:$vindex, i32:{ *:[i32] }:$voffset, (BUFSOffset:{ *:[i32] } i32:{ *:[i32] }:$soffset), (timm:{ *:[i32] }):$offset, (timm:{ *:[i32] }):$auxiliary, (timm:{ *:[i1] }))  =>  (BUFFER_ATOMIC_MIN_F64_VBUFFER_BOTHEN_RTN:{ *:[f64] } anonymous_15036:{ *:[f64] }:$vdata_in, (REG_SEQUENCE:{ *:[i64] } VReg_64:{ *:[i32] }, VGPR_32:{ *:[i32] }:$vindex, sub0:{ *:[i32] }, VGPR_32:{ *:[i32] }:$voffset, sub1:{ *:[i32] }), SReg_128:{ *:[v4i32] }:$rsrc, SCSrc_b32:{ *:[i32] }:$soffset, (timm:{ *:[i32] }):$offset, (extract_cpol_set_glc:{ *:[i32] } ?:{ *:[i32] }:$auxiliary))
        GIR_MakeTempReg, /*TempRegID*/0, /*TypeID*/GILLT_s64,
        GIR_BuildMI, /*InsnID*/1, /*Opcode*/GIMT_Encode2(TargetOpcode::REG_SEQUENCE),
        GIR_AddTempRegister, /*InsnID*/1, /*TempRegID*/0, /*TempRegFlags*/GIMT_Encode2(RegState::Define),
        GIR_Copy, /*NewInsnID*/1, /*OldInsnID*/0, /*OpIdx*/3, // vindex
        GIR_AddImm8, /*InsnID*/1, /*SubRegIndex*/3,
        GIR_Copy, /*NewInsnID*/1, /*OldInsnID*/0, /*OpIdx*/4, // voffset
        GIR_AddImm8, /*InsnID*/1, /*SubRegIndex*/11,
        GIR_ConstrainOperandRC, /*InsnID*/1, /*Op*/0, GIMT_Encode2(AMDGPU::VReg_64RegClassID),
        GIR_ConstrainOperandRC, /*InsnID*/1, /*Op*/1, GIMT_Encode2(AMDGPU::VGPR_32RegClassID),
        GIR_ConstrainOperandRC, /*InsnID*/1, /*Op*/3, GIMT_Encode2(AMDGPU::VGPR_32RegClassID),
        GIR_BuildMI, /*InsnID*/0, /*Opcode*/GIMT_Encode2(AMDGPU::BUFFER_ATOMIC_MIN_F64_VBUFFER_BOTHEN_RTN),
        GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/0, // DstI[vdata]
        GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/1, // vdata_in
        GIR_AddSimpleTempRegister, /*InsnID*/0, /*TempRegID*/0,
        GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/2, // rsrc
        GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/0, // soffset
        GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/6, // offset
        GIR_CustomOperandRenderer, /*InsnID*/0, /*OldInsnID*/0, /*OpIdx*/7, /*OperandRenderer*/GIMT_Encode2(GICR_renderExtractCpolSetGLC), // auxiliary
        GIR_MergeMemOperands, /*InsnID*/0, /*NumInsns*/1, /*MergeInsnID's*/0,
        GIR_ConstrainSelectedInstOperands, /*InsnID*/0,
        GIR_EraseFromParent, /*InsnID*/0,
        // GIR_Coverage, 5268,
        GIR_Done,
      // Label 6041: @442216
      GIM_Reject,
    // Label 6009: @442217
    GIM_Reject,
    // Label 5991: @442218
    GIM_Reject,
    // Label 115: @442219
    GIM_SwitchType, /*MI*/0, /*Op*/0, /*[*/GIMT_Encode2(9), GIMT_Encode2(11), /*)*//*default:*//*Label 6044*/ GIMT_Encode4(445012),
    /*GILLT_s32*//*Label 6042*/ GIMT_Encode4(442238),
    /*GILLT_s64*//*Label 6043*/ GIMT_Encode4(443625),
    // Label 6042: @442238
    GIM_Try, /*On fail goto*//*Label 6045*/ GIMT_Encode4(443624),
      GIM_CheckType, /*MI*/0, /*Op*/1, /*Type*/GILLT_s32,
      GIM_CheckType, /*MI*/0, /*Op*/2, /*Type*/GILLT_v4s32,
      GIM_CheckType, /*MI*/0, /*Op*/3, /*Type*/GILLT_s32,
      GIM_CheckType, /*MI*/0, /*Op*/4, /*Type*/GILLT_s32,
      GIM_CheckType, /*MI*/0, /*Op*/5, /*Type*/GILLT_s32,
      GIM_Try, /*On fail goto*//*Label 6046*/ GIMT_Encode4(442341), // Rule ID 4893 //
        GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasUnrestrictedSOffset),
        GIM_CheckHasNoUse, /*MI*/0,
        GIM_CheckConstantInt8, /*MI*/0, /*Op*/3, 0,
        GIM_CheckConstantInt8, /*MI*/0, /*Op*/4, 0,
        // MIs[0] offset
        GIM_CheckIsImm, /*MI*/0, /*Op*/6,
        // MIs[0] auxiliary
        GIM_CheckIsImm, /*MI*/0, /*Op*/7,
        // MIs[0] Operand 8
        GIM_CheckLiteralInt, /*MI*/0, /*Op*/8, GIMT_Encode8(0),
        GIM_CheckComplexPattern, /*MI*/0, /*Op*/5, /*Renderer*/GIMT_Encode2(0), GIMT_Encode2(GICP_gi_buf_soffset),
        // (SIbuffer_atomic_inc:{ *:[i32] } i32:{ *:[i32] }:$vdata_in, v4i32:{ *:[v4i32] }:$rsrc, 0:{ *:[i32] }, 0:{ *:[i32] }, (BUFSOffset:{ *:[i32] } i32:{ *:[i32] }:$soffset), (timm:{ *:[i32] }):$offset, (timm:{ *:[i32] }):$auxiliary, 0:{ *:[i1] })<<P:Predicate_SIbuffer_atomic_inc_noret>>  =>  (BUFFER_ATOMIC_INC_OFFSET anonymous_15037:{ *:[i32] }:$vdata_in, SReg_128:{ *:[v4i32] }:$rsrc, SCSrc_b32:{ *:[i32] }:$soffset, (timm:{ *:[i32] }):$offset, (extract_cpol:{ *:[i32] } ?:{ *:[i32] }:$auxiliary))
        GIR_BuildMI, /*InsnID*/0, /*Opcode*/GIMT_Encode2(AMDGPU::BUFFER_ATOMIC_INC_OFFSET),
        GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/1, // vdata_in
        GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/2, // rsrc
        GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/0, // soffset
        GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/6, // offset
        GIR_CustomOperandRenderer, /*InsnID*/0, /*OldInsnID*/0, /*OpIdx*/7, /*OperandRenderer*/GIMT_Encode2(GICR_renderExtractCPol), // auxiliary
        GIR_MergeMemOperands, /*InsnID*/0, /*NumInsns*/1, /*MergeInsnID's*/0,
        GIR_ConstrainSelectedInstOperands, /*InsnID*/0,
        GIR_EraseFromParent, /*InsnID*/0,
        // GIR_Coverage, 4893,
        GIR_Done,
      // Label 6046: @442341
      GIM_Try, /*On fail goto*//*Label 6047*/ GIMT_Encode4(442416), // Rule ID 4901 //
        GIM_CheckHasNoUse, /*MI*/0,
        GIM_CheckConstantInt8, /*MI*/0, /*Op*/3, 0,
        GIM_CheckConstantInt8, /*MI*/0, /*Op*/4, 0,
        // MIs[0] offset
        GIM_CheckIsImm, /*MI*/0, /*Op*/6,
        // MIs[0] auxiliary
        GIM_CheckIsImm, /*MI*/0, /*Op*/7,
        // MIs[0] Operand 8
        GIM_CheckLiteralInt, /*MI*/0, /*Op*/8, GIMT_Encode8(0),
        GIM_CheckComplexPattern, /*MI*/0, /*Op*/5, /*Renderer*/GIMT_Encode2(0), GIMT_Encode2(GICP_gi_buf_soffset),
        // (SIbuffer_atomic_inc:{ *:[i32] } i32:{ *:[i32] }:$vdata_in, v4i32:{ *:[v4i32] }:$rsrc, 0:{ *:[i32] }, 0:{ *:[i32] }, (BUFSOffset:{ *:[i32] } i32:{ *:[i32] }:$soffset), (timm:{ *:[i32] }):$offset, (timm:{ *:[i32] }):$auxiliary, 0:{ *:[i1] })<<P:Predicate_SIbuffer_atomic_inc_noret>>  =>  (BUFFER_ATOMIC_INC_VBUFFER_OFFSET anonymous_15037:{ *:[i32] }:$vdata_in, SReg_128:{ *:[v4i32] }:$rsrc, SCSrc_b32:{ *:[i32] }:$soffset, (timm:{ *:[i32] }):$offset, (extract_cpol:{ *:[i32] } ?:{ *:[i32] }:$auxiliary))
        GIR_BuildMI, /*InsnID*/0, /*Opcode*/GIMT_Encode2(AMDGPU::BUFFER_ATOMIC_INC_VBUFFER_OFFSET),
        GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/1, // vdata_in
        GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/2, // rsrc
        GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/0, // soffset
        GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/6, // offset
        GIR_CustomOperandRenderer, /*InsnID*/0, /*OldInsnID*/0, /*OpIdx*/7, /*OperandRenderer*/GIMT_Encode2(GICR_renderExtractCPol), // auxiliary
        GIR_MergeMemOperands, /*InsnID*/0, /*NumInsns*/1, /*MergeInsnID's*/0,
        GIR_ConstrainSelectedInstOperands, /*InsnID*/0,
        GIR_EraseFromParent, /*InsnID*/0,
        // GIR_Coverage, 4901,
        GIR_Done,
      // Label 6047: @442416
      GIM_Try, /*On fail goto*//*Label 6048*/ GIMT_Encode4(442501), // Rule ID 4889 //
        GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasUnrestrictedSOffset),
        GIM_CheckRegBankForClass, /*MI*/0, /*Op*/0, /*RC*/GIMT_Encode2(AMDGPU::AV_32RegClassID),
        GIM_CheckConstantInt8, /*MI*/0, /*Op*/3, 0,
        GIM_CheckConstantInt8, /*MI*/0, /*Op*/4, 0,
        // MIs[0] offset
        GIM_CheckIsImm, /*MI*/0, /*Op*/6,
        // MIs[0] auxiliary
        GIM_CheckIsImm, /*MI*/0, /*Op*/7,
        // MIs[0] Operand 8
        GIM_CheckLiteralInt, /*MI*/0, /*Op*/8, GIMT_Encode8(0),
        GIM_CheckComplexPattern, /*MI*/0, /*Op*/5, /*Renderer*/GIMT_Encode2(0), GIMT_Encode2(GICP_gi_buf_soffset),
        // (SIbuffer_atomic_inc:{ *:[i32] } i32:{ *:[i32] }:$vdata_in, v4i32:{ *:[v4i32] }:$rsrc, 0:{ *:[i32] }, 0:{ *:[i32] }, (BUFSOffset:{ *:[i32] } i32:{ *:[i32] }:$soffset), (timm:{ *:[i32] }):$offset, (timm:{ *:[i32] }):$auxiliary, 0:{ *:[i1] })  =>  (BUFFER_ATOMIC_INC_OFFSET_RTN:{ *:[i32] } anonymous_15037:{ *:[i32] }:$vdata_in, SReg_128:{ *:[v4i32] }:$rsrc, SCSrc_b32:{ *:[i32] }:$soffset, (timm:{ *:[i32] }):$offset, (extract_cpol_set_glc:{ *:[i32] } ?:{ *:[i32] }:$auxiliary))
        GIR_BuildMI, /*InsnID*/0, /*Opcode*/GIMT_Encode2(AMDGPU::BUFFER_ATOMIC_INC_OFFSET_RTN),
        GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/0, // DstI[vdata]
        GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/1, // vdata_in
        GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/2, // rsrc
        GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/0, // soffset
        GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/6, // offset
        GIR_CustomOperandRenderer, /*InsnID*/0, /*OldInsnID*/0, /*OpIdx*/7, /*OperandRenderer*/GIMT_Encode2(GICR_renderExtractCpolSetGLC), // auxiliary
        GIR_MergeMemOperands, /*InsnID*/0, /*NumInsns*/1, /*MergeInsnID's*/0,
        GIR_ConstrainSelectedInstOperands, /*InsnID*/0,
        GIR_EraseFromParent, /*InsnID*/0,
        // GIR_Coverage, 4889,
        GIR_Done,
      // Label 6048: @442501
      GIM_Try, /*On fail goto*//*Label 6049*/ GIMT_Encode4(442583), // Rule ID 4897 //
        GIM_CheckRegBankForClass, /*MI*/0, /*Op*/0, /*RC*/GIMT_Encode2(AMDGPU::AV_32RegClassID),
        GIM_CheckConstantInt8, /*MI*/0, /*Op*/3, 0,
        GIM_CheckConstantInt8, /*MI*/0, /*Op*/4, 0,
        // MIs[0] offset
        GIM_CheckIsImm, /*MI*/0, /*Op*/6,
        // MIs[0] auxiliary
        GIM_CheckIsImm, /*MI*/0, /*Op*/7,
        // MIs[0] Operand 8
        GIM_CheckLiteralInt, /*MI*/0, /*Op*/8, GIMT_Encode8(0),
        GIM_CheckComplexPattern, /*MI*/0, /*Op*/5, /*Renderer*/GIMT_Encode2(0), GIMT_Encode2(GICP_gi_buf_soffset),
        // (SIbuffer_atomic_inc:{ *:[i32] } i32:{ *:[i32] }:$vdata_in, v4i32:{ *:[v4i32] }:$rsrc, 0:{ *:[i32] }, 0:{ *:[i32] }, (BUFSOffset:{ *:[i32] } i32:{ *:[i32] }:$soffset), (timm:{ *:[i32] }):$offset, (timm:{ *:[i32] }):$auxiliary, 0:{ *:[i1] })  =>  (BUFFER_ATOMIC_INC_VBUFFER_OFFSET_RTN:{ *:[i32] } anonymous_15037:{ *:[i32] }:$vdata_in, SReg_128:{ *:[v4i32] }:$rsrc, SCSrc_b32:{ *:[i32] }:$soffset, (timm:{ *:[i32] }):$offset, (extract_cpol_set_glc:{ *:[i32] } ?:{ *:[i32] }:$auxiliary))
        GIR_BuildMI, /*InsnID*/0, /*Opcode*/GIMT_Encode2(AMDGPU::BUFFER_ATOMIC_INC_VBUFFER_OFFSET_RTN),
        GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/0, // DstI[vdata]
        GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/1, // vdata_in
        GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/2, // rsrc
        GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/0, // soffset
        GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/6, // offset
        GIR_CustomOperandRenderer, /*InsnID*/0, /*OldInsnID*/0, /*OpIdx*/7, /*OperandRenderer*/GIMT_Encode2(GICR_renderExtractCpolSetGLC), // auxiliary
        GIR_MergeMemOperands, /*InsnID*/0, /*NumInsns*/1, /*MergeInsnID's*/0,
        GIR_ConstrainSelectedInstOperands, /*InsnID*/0,
        GIR_EraseFromParent, /*InsnID*/0,
        // GIR_Coverage, 4897,
        GIR_Done,
      // Label 6049: @442583
      GIM_Try, /*On fail goto*//*Label 6050*/ GIMT_Encode4(442661), // Rule ID 4895 //
        GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasUnrestrictedSOffset),
        GIM_CheckHasNoUse, /*MI*/0,
        GIM_CheckConstantInt8, /*MI*/0, /*Op*/3, 0,
        // MIs[0] offset
        GIM_CheckIsImm, /*MI*/0, /*Op*/6,
        // MIs[0] auxiliary
        GIM_CheckIsImm, /*MI*/0, /*Op*/7,
        // MIs[0] Operand 8
        GIM_CheckLiteralInt, /*MI*/0, /*Op*/8, GIMT_Encode8(0),
        GIM_CheckComplexPattern, /*MI*/0, /*Op*/5, /*Renderer*/GIMT_Encode2(0), GIMT_Encode2(GICP_gi_buf_soffset),
        // (SIbuffer_atomic_inc:{ *:[i32] } i32:{ *:[i32] }:$vdata_in, v4i32:{ *:[v4i32] }:$rsrc, 0:{ *:[i32] }, i32:{ *:[i32] }:$voffset, (BUFSOffset:{ *:[i32] } i32:{ *:[i32] }:$soffset), (timm:{ *:[i32] }):$offset, (timm:{ *:[i32] }):$auxiliary, 0:{ *:[i1] })<<P:Predicate_SIbuffer_atomic_inc_noret>>  =>  (BUFFER_ATOMIC_INC_OFFEN anonymous_15037:{ *:[i32] }:$vdata_in, VGPR_32:{ *:[i32] }:$voffset, SReg_128:{ *:[v4i32] }:$rsrc, SCSrc_b32:{ *:[i32] }:$soffset, (timm:{ *:[i32] }):$offset, (extract_cpol:{ *:[i32] } ?:{ *:[i32] }:$auxiliary))
        GIR_BuildMI, /*InsnID*/0, /*Opcode*/GIMT_Encode2(AMDGPU::BUFFER_ATOMIC_INC_OFFEN),
        GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/1, // vdata_in
        GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/4, // voffset
        GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/2, // rsrc
        GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/0, // soffset
        GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/6, // offset
        GIR_CustomOperandRenderer, /*InsnID*/0, /*OldInsnID*/0, /*OpIdx*/7, /*OperandRenderer*/GIMT_Encode2(GICR_renderExtractCPol), // auxiliary
        GIR_MergeMemOperands, /*InsnID*/0, /*NumInsns*/1, /*MergeInsnID's*/0,
        GIR_ConstrainSelectedInstOperands, /*InsnID*/0,
        GIR_EraseFromParent, /*InsnID*/0,
        // GIR_Coverage, 4895,
        GIR_Done,
      // Label 6050: @442661
      GIM_Try, /*On fail goto*//*Label 6051*/ GIMT_Encode4(442736), // Rule ID 4903 //
        GIM_CheckHasNoUse, /*MI*/0,
        GIM_CheckConstantInt8, /*MI*/0, /*Op*/3, 0,
        // MIs[0] offset
        GIM_CheckIsImm, /*MI*/0, /*Op*/6,
        // MIs[0] auxiliary
        GIM_CheckIsImm, /*MI*/0, /*Op*/7,
        // MIs[0] Operand 8
        GIM_CheckLiteralInt, /*MI*/0, /*Op*/8, GIMT_Encode8(0),
        GIM_CheckComplexPattern, /*MI*/0, /*Op*/5, /*Renderer*/GIMT_Encode2(0), GIMT_Encode2(GICP_gi_buf_soffset),
        // (SIbuffer_atomic_inc:{ *:[i32] } i32:{ *:[i32] }:$vdata_in, v4i32:{ *:[v4i32] }:$rsrc, 0:{ *:[i32] }, i32:{ *:[i32] }:$voffset, (BUFSOffset:{ *:[i32] } i32:{ *:[i32] }:$soffset), (timm:{ *:[i32] }):$offset, (timm:{ *:[i32] }):$auxiliary, 0:{ *:[i1] })<<P:Predicate_SIbuffer_atomic_inc_noret>>  =>  (BUFFER_ATOMIC_INC_VBUFFER_OFFEN anonymous_15037:{ *:[i32] }:$vdata_in, VGPR_32:{ *:[i32] }:$voffset, SReg_128:{ *:[v4i32] }:$rsrc, SCSrc_b32:{ *:[i32] }:$soffset, (timm:{ *:[i32] }):$offset, (extract_cpol:{ *:[i32] } ?:{ *:[i32] }:$auxiliary))
        GIR_BuildMI, /*InsnID*/0, /*Opcode*/GIMT_Encode2(AMDGPU::BUFFER_ATOMIC_INC_VBUFFER_OFFEN),
        GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/1, // vdata_in
        GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/4, // voffset
        GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/2, // rsrc
        GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/0, // soffset
        GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/6, // offset
        GIR_CustomOperandRenderer, /*InsnID*/0, /*OldInsnID*/0, /*OpIdx*/7, /*OperandRenderer*/GIMT_Encode2(GICR_renderExtractCPol), // auxiliary
        GIR_MergeMemOperands, /*InsnID*/0, /*NumInsns*/1, /*MergeInsnID's*/0,
        GIR_ConstrainSelectedInstOperands, /*InsnID*/0,
        GIR_EraseFromParent, /*InsnID*/0,
        // GIR_Coverage, 4903,
        GIR_Done,
      // Label 6051: @442736
      GIM_Try, /*On fail goto*//*Label 6052*/ GIMT_Encode4(442821), // Rule ID 4891 //
        GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasUnrestrictedSOffset),
        GIM_CheckRegBankForClass, /*MI*/0, /*Op*/0, /*RC*/GIMT_Encode2(AMDGPU::AV_32RegClassID),
        GIM_CheckConstantInt8, /*MI*/0, /*Op*/3, 0,
        // MIs[0] offset
        GIM_CheckIsImm, /*MI*/0, /*Op*/6,
        // MIs[0] auxiliary
        GIM_CheckIsImm, /*MI*/0, /*Op*/7,
        // MIs[0] Operand 8
        GIM_CheckLiteralInt, /*MI*/0, /*Op*/8, GIMT_Encode8(0),
        GIM_CheckComplexPattern, /*MI*/0, /*Op*/5, /*Renderer*/GIMT_Encode2(0), GIMT_Encode2(GICP_gi_buf_soffset),
        // (SIbuffer_atomic_inc:{ *:[i32] } i32:{ *:[i32] }:$vdata_in, v4i32:{ *:[v4i32] }:$rsrc, 0:{ *:[i32] }, i32:{ *:[i32] }:$voffset, (BUFSOffset:{ *:[i32] } i32:{ *:[i32] }:$soffset), (timm:{ *:[i32] }):$offset, (timm:{ *:[i32] }):$auxiliary, 0:{ *:[i1] })  =>  (BUFFER_ATOMIC_INC_OFFEN_RTN:{ *:[i32] } anonymous_15037:{ *:[i32] }:$vdata_in, VGPR_32:{ *:[i32] }:$voffset, SReg_128:{ *:[v4i32] }:$rsrc, SCSrc_b32:{ *:[i32] }:$soffset, (timm:{ *:[i32] }):$offset, (extract_cpol_set_glc:{ *:[i32] } ?:{ *:[i32] }:$auxiliary))
        GIR_BuildMI, /*InsnID*/0, /*Opcode*/GIMT_Encode2(AMDGPU::BUFFER_ATOMIC_INC_OFFEN_RTN),
        GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/0, // DstI[vdata]
        GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/1, // vdata_in
        GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/4, // voffset
        GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/2, // rsrc
        GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/0, // soffset
        GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/6, // offset
        GIR_CustomOperandRenderer, /*InsnID*/0, /*OldInsnID*/0, /*OpIdx*/7, /*OperandRenderer*/GIMT_Encode2(GICR_renderExtractCpolSetGLC), // auxiliary
        GIR_MergeMemOperands, /*InsnID*/0, /*NumInsns*/1, /*MergeInsnID's*/0,
        GIR_ConstrainSelectedInstOperands, /*InsnID*/0,
        GIR_EraseFromParent, /*InsnID*/0,
        // GIR_Coverage, 4891,
        GIR_Done,
      // Label 6052: @442821
      GIM_Try, /*On fail goto*//*Label 6053*/ GIMT_Encode4(442903), // Rule ID 4899 //
        GIM_CheckRegBankForClass, /*MI*/0, /*Op*/0, /*RC*/GIMT_Encode2(AMDGPU::AV_32RegClassID),
        GIM_CheckConstantInt8, /*MI*/0, /*Op*/3, 0,
        // MIs[0] offset
        GIM_CheckIsImm, /*MI*/0, /*Op*/6,
        // MIs[0] auxiliary
        GIM_CheckIsImm, /*MI*/0, /*Op*/7,
        // MIs[0] Operand 8
        GIM_CheckLiteralInt, /*MI*/0, /*Op*/8, GIMT_Encode8(0),
        GIM_CheckComplexPattern, /*MI*/0, /*Op*/5, /*Renderer*/GIMT_Encode2(0), GIMT_Encode2(GICP_gi_buf_soffset),
        // (SIbuffer_atomic_inc:{ *:[i32] } i32:{ *:[i32] }:$vdata_in, v4i32:{ *:[v4i32] }:$rsrc, 0:{ *:[i32] }, i32:{ *:[i32] }:$voffset, (BUFSOffset:{ *:[i32] } i32:{ *:[i32] }:$soffset), (timm:{ *:[i32] }):$offset, (timm:{ *:[i32] }):$auxiliary, 0:{ *:[i1] })  =>  (BUFFER_ATOMIC_INC_VBUFFER_OFFEN_RTN:{ *:[i32] } anonymous_15037:{ *:[i32] }:$vdata_in, VGPR_32:{ *:[i32] }:$voffset, SReg_128:{ *:[v4i32] }:$rsrc, SCSrc_b32:{ *:[i32] }:$soffset, (timm:{ *:[i32] }):$offset, (extract_cpol_set_glc:{ *:[i32] } ?:{ *:[i32] }:$auxiliary))
        GIR_BuildMI, /*InsnID*/0, /*Opcode*/GIMT_Encode2(AMDGPU::BUFFER_ATOMIC_INC_VBUFFER_OFFEN_RTN),
        GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/0, // DstI[vdata]
        GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/1, // vdata_in
        GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/4, // voffset
        GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/2, // rsrc
        GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/0, // soffset
        GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/6, // offset
        GIR_CustomOperandRenderer, /*InsnID*/0, /*OldInsnID*/0, /*OpIdx*/7, /*OperandRenderer*/GIMT_Encode2(GICR_renderExtractCpolSetGLC), // auxiliary
        GIR_MergeMemOperands, /*InsnID*/0, /*NumInsns*/1, /*MergeInsnID's*/0,
        GIR_ConstrainSelectedInstOperands, /*InsnID*/0,
        GIR_EraseFromParent, /*InsnID*/0,
        // GIR_Coverage, 4899,
        GIR_Done,
      // Label 6053: @442903
      GIM_Try, /*On fail goto*//*Label 6054*/ GIMT_Encode4(442973), // Rule ID 4894 //
        GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasUnrestrictedSOffset),
        GIM_CheckHasNoUse, /*MI*/0,
        GIM_CheckConstantInt8, /*MI*/0, /*Op*/4, 0,
        // MIs[0] offset
        GIM_CheckIsImm, /*MI*/0, /*Op*/6,
        // MIs[0] auxiliary
        GIM_CheckIsImm, /*MI*/0, /*Op*/7,
        // MIs[0] Operand 8
        GIM_CheckIsImm, /*MI*/0, /*Op*/8,
        GIM_CheckComplexPattern, /*MI*/0, /*Op*/5, /*Renderer*/GIMT_Encode2(0), GIMT_Encode2(GICP_gi_buf_soffset),
        // (SIbuffer_atomic_inc:{ *:[i32] } i32:{ *:[i32] }:$vdata_in, v4i32:{ *:[v4i32] }:$rsrc, i32:{ *:[i32] }:$vindex, 0:{ *:[i32] }, (BUFSOffset:{ *:[i32] } i32:{ *:[i32] }:$soffset), (timm:{ *:[i32] }):$offset, (timm:{ *:[i32] }):$auxiliary, (timm:{ *:[i1] }))<<P:Predicate_SIbuffer_atomic_inc_noret>>  =>  (BUFFER_ATOMIC_INC_IDXEN anonymous_15037:{ *:[i32] }:$vdata_in, VGPR_32:{ *:[i32] }:$vindex, SReg_128:{ *:[v4i32] }:$rsrc, SCSrc_b32:{ *:[i32] }:$soffset, (timm:{ *:[i32] }):$offset, (extract_cpol:{ *:[i32] } ?:{ *:[i32] }:$auxiliary))
        GIR_BuildMI, /*InsnID*/0, /*Opcode*/GIMT_Encode2(AMDGPU::BUFFER_ATOMIC_INC_IDXEN),
        GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/1, // vdata_in
        GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/3, // vindex
        GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/2, // rsrc
        GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/0, // soffset
        GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/6, // offset
        GIR_CustomOperandRenderer, /*InsnID*/0, /*OldInsnID*/0, /*OpIdx*/7, /*OperandRenderer*/GIMT_Encode2(GICR_renderExtractCPol), // auxiliary
        GIR_MergeMemOperands, /*InsnID*/0, /*NumInsns*/1, /*MergeInsnID's*/0,
        GIR_ConstrainSelectedInstOperands, /*InsnID*/0,
        GIR_EraseFromParent, /*InsnID*/0,
        // GIR_Coverage, 4894,
        GIR_Done,
      // Label 6054: @442973
      GIM_Try, /*On fail goto*//*Label 6055*/ GIMT_Encode4(443040), // Rule ID 4902 //
        GIM_CheckHasNoUse, /*MI*/0,
        GIM_CheckConstantInt8, /*MI*/0, /*Op*/4, 0,
        // MIs[0] offset
        GIM_CheckIsImm, /*MI*/0, /*Op*/6,
        // MIs[0] auxiliary
        GIM_CheckIsImm, /*MI*/0, /*Op*/7,
        // MIs[0] Operand 8
        GIM_CheckIsImm, /*MI*/0, /*Op*/8,
        GIM_CheckComplexPattern, /*MI*/0, /*Op*/5, /*Renderer*/GIMT_Encode2(0), GIMT_Encode2(GICP_gi_buf_soffset),
        // (SIbuffer_atomic_inc:{ *:[i32] } i32:{ *:[i32] }:$vdata_in, v4i32:{ *:[v4i32] }:$rsrc, i32:{ *:[i32] }:$vindex, 0:{ *:[i32] }, (BUFSOffset:{ *:[i32] } i32:{ *:[i32] }:$soffset), (timm:{ *:[i32] }):$offset, (timm:{ *:[i32] }):$auxiliary, (timm:{ *:[i1] }))<<P:Predicate_SIbuffer_atomic_inc_noret>>  =>  (BUFFER_ATOMIC_INC_VBUFFER_IDXEN anonymous_15037:{ *:[i32] }:$vdata_in, VGPR_32:{ *:[i32] }:$vindex, SReg_128:{ *:[v4i32] }:$rsrc, SCSrc_b32:{ *:[i32] }:$soffset, (timm:{ *:[i32] }):$offset, (extract_cpol:{ *:[i32] } ?:{ *:[i32] }:$auxiliary))
        GIR_BuildMI, /*InsnID*/0, /*Opcode*/GIMT_Encode2(AMDGPU::BUFFER_ATOMIC_INC_VBUFFER_IDXEN),
        GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/1, // vdata_in
        GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/3, // vindex
        GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/2, // rsrc
        GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/0, // soffset
        GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/6, // offset
        GIR_CustomOperandRenderer, /*InsnID*/0, /*OldInsnID*/0, /*OpIdx*/7, /*OperandRenderer*/GIMT_Encode2(GICR_renderExtractCPol), // auxiliary
        GIR_MergeMemOperands, /*InsnID*/0, /*NumInsns*/1, /*MergeInsnID's*/0,
        GIR_ConstrainSelectedInstOperands, /*InsnID*/0,
        GIR_EraseFromParent, /*InsnID*/0,
        // GIR_Coverage, 4902,
        GIR_Done,
      // Label 6055: @443040
      GIM_Try, /*On fail goto*//*Label 6056*/ GIMT_Encode4(443117), // Rule ID 4890 //
        GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasUnrestrictedSOffset),
        GIM_CheckRegBankForClass, /*MI*/0, /*Op*/0, /*RC*/GIMT_Encode2(AMDGPU::AV_32RegClassID),
        GIM_CheckConstantInt8, /*MI*/0, /*Op*/4, 0,
        // MIs[0] offset
        GIM_CheckIsImm, /*MI*/0, /*Op*/6,
        // MIs[0] auxiliary
        GIM_CheckIsImm, /*MI*/0, /*Op*/7,
        // MIs[0] Operand 8
        GIM_CheckIsImm, /*MI*/0, /*Op*/8,
        GIM_CheckComplexPattern, /*MI*/0, /*Op*/5, /*Renderer*/GIMT_Encode2(0), GIMT_Encode2(GICP_gi_buf_soffset),
        // (SIbuffer_atomic_inc:{ *:[i32] } i32:{ *:[i32] }:$vdata_in, v4i32:{ *:[v4i32] }:$rsrc, i32:{ *:[i32] }:$vindex, 0:{ *:[i32] }, (BUFSOffset:{ *:[i32] } i32:{ *:[i32] }:$soffset), (timm:{ *:[i32] }):$offset, (timm:{ *:[i32] }):$auxiliary, (timm:{ *:[i1] }))  =>  (BUFFER_ATOMIC_INC_IDXEN_RTN:{ *:[i32] } anonymous_15037:{ *:[i32] }:$vdata_in, VGPR_32:{ *:[i32] }:$vindex, SReg_128:{ *:[v4i32] }:$rsrc, SCSrc_b32:{ *:[i32] }:$soffset, (timm:{ *:[i32] }):$offset, (extract_cpol_set_glc:{ *:[i32] } ?:{ *:[i32] }:$auxiliary))
        GIR_BuildMI, /*InsnID*/0, /*Opcode*/GIMT_Encode2(AMDGPU::BUFFER_ATOMIC_INC_IDXEN_RTN),
        GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/0, // DstI[vdata]
        GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/1, // vdata_in
        GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/3, // vindex
        GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/2, // rsrc
        GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/0, // soffset
        GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/6, // offset
        GIR_CustomOperandRenderer, /*InsnID*/0, /*OldInsnID*/0, /*OpIdx*/7, /*OperandRenderer*/GIMT_Encode2(GICR_renderExtractCpolSetGLC), // auxiliary
        GIR_MergeMemOperands, /*InsnID*/0, /*NumInsns*/1, /*MergeInsnID's*/0,
        GIR_ConstrainSelectedInstOperands, /*InsnID*/0,
        GIR_EraseFromParent, /*InsnID*/0,
        // GIR_Coverage, 4890,
        GIR_Done,
      // Label 6056: @443117
      GIM_Try, /*On fail goto*//*Label 6057*/ GIMT_Encode4(443191), // Rule ID 4898 //
        GIM_CheckRegBankForClass, /*MI*/0, /*Op*/0, /*RC*/GIMT_Encode2(AMDGPU::AV_32RegClassID),
        GIM_CheckConstantInt8, /*MI*/0, /*Op*/4, 0,
        // MIs[0] offset
        GIM_CheckIsImm, /*MI*/0, /*Op*/6,
        // MIs[0] auxiliary
        GIM_CheckIsImm, /*MI*/0, /*Op*/7,
        // MIs[0] Operand 8
        GIM_CheckIsImm, /*MI*/0, /*Op*/8,
        GIM_CheckComplexPattern, /*MI*/0, /*Op*/5, /*Renderer*/GIMT_Encode2(0), GIMT_Encode2(GICP_gi_buf_soffset),
        // (SIbuffer_atomic_inc:{ *:[i32] } i32:{ *:[i32] }:$vdata_in, v4i32:{ *:[v4i32] }:$rsrc, i32:{ *:[i32] }:$vindex, 0:{ *:[i32] }, (BUFSOffset:{ *:[i32] } i32:{ *:[i32] }:$soffset), (timm:{ *:[i32] }):$offset, (timm:{ *:[i32] }):$auxiliary, (timm:{ *:[i1] }))  =>  (BUFFER_ATOMIC_INC_VBUFFER_IDXEN_RTN:{ *:[i32] } anonymous_15037:{ *:[i32] }:$vdata_in, VGPR_32:{ *:[i32] }:$vindex, SReg_128:{ *:[v4i32] }:$rsrc, SCSrc_b32:{ *:[i32] }:$soffset, (timm:{ *:[i32] }):$offset, (extract_cpol_set_glc:{ *:[i32] } ?:{ *:[i32] }:$auxiliary))
        GIR_BuildMI, /*InsnID*/0, /*Opcode*/GIMT_Encode2(AMDGPU::BUFFER_ATOMIC_INC_VBUFFER_IDXEN_RTN),
        GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/0, // DstI[vdata]
        GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/1, // vdata_in
        GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/3, // vindex
        GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/2, // rsrc
        GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/0, // soffset
        GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/6, // offset
        GIR_CustomOperandRenderer, /*InsnID*/0, /*OldInsnID*/0, /*OpIdx*/7, /*OperandRenderer*/GIMT_Encode2(GICR_renderExtractCpolSetGLC), // auxiliary
        GIR_MergeMemOperands, /*InsnID*/0, /*NumInsns*/1, /*MergeInsnID's*/0,
        GIR_ConstrainSelectedInstOperands, /*InsnID*/0,
        GIR_EraseFromParent, /*InsnID*/0,
        // GIR_Coverage, 4898,
        GIR_Done,
      // Label 6057: @443191
      GIM_Try, /*On fail goto*//*Label 6058*/ GIMT_Encode4(443297), // Rule ID 4896 //
        GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasUnrestrictedSOffset),
        GIM_CheckHasNoUse, /*MI*/0,
        // MIs[0] offset
        GIM_CheckIsImm, /*MI*/0, /*Op*/6,
        // MIs[0] auxiliary
        GIM_CheckIsImm, /*MI*/0, /*Op*/7,
        // MIs[0] Operand 8
        GIM_CheckIsImm, /*MI*/0, /*Op*/8,
        GIM_CheckComplexPattern, /*MI*/0, /*Op*/5, /*Renderer*/GIMT_Encode2(0), GIMT_Encode2(GICP_gi_buf_soffset),
        // (SIbuffer_atomic_inc:{ *:[i32] } i32:{ *:[i32] }:$vdata_in, v4i32:{ *:[v4i32] }:$rsrc, i32:{ *:[i32] }:$vindex, i32:{ *:[i32] }:$voffset, (BUFSOffset:{ *:[i32] } i32:{ *:[i32] }:$soffset), (timm:{ *:[i32] }):$offset, (timm:{ *:[i32] }):$auxiliary, (timm:{ *:[i1] }))<<P:Predicate_SIbuffer_atomic_inc_noret>>  =>  (BUFFER_ATOMIC_INC_BOTHEN anonymous_15037:{ *:[i32] }:$vdata_in, (REG_SEQUENCE:{ *:[i64] } VReg_64:{ *:[i32] }, VGPR_32:{ *:[i32] }:$vindex, sub0:{ *:[i32] }, VGPR_32:{ *:[i32] }:$voffset, sub1:{ *:[i32] }), SReg_128:{ *:[v4i32] }:$rsrc, SCSrc_b32:{ *:[i32] }:$soffset, (timm:{ *:[i32] }):$offset, (extract_cpol:{ *:[i32] } ?:{ *:[i32] }:$auxiliary))
        GIR_MakeTempReg, /*TempRegID*/0, /*TypeID*/GILLT_s64,
        GIR_BuildMI, /*InsnID*/1, /*Opcode*/GIMT_Encode2(TargetOpcode::REG_SEQUENCE),
        GIR_AddTempRegister, /*InsnID*/1, /*TempRegID*/0, /*TempRegFlags*/GIMT_Encode2(RegState::Define),
        GIR_Copy, /*NewInsnID*/1, /*OldInsnID*/0, /*OpIdx*/3, // vindex
        GIR_AddImm8, /*InsnID*/1, /*SubRegIndex*/3,
        GIR_Copy, /*NewInsnID*/1, /*OldInsnID*/0, /*OpIdx*/4, // voffset
        GIR_AddImm8, /*InsnID*/1, /*SubRegIndex*/11,
        GIR_ConstrainOperandRC, /*InsnID*/1, /*Op*/0, GIMT_Encode2(AMDGPU::VReg_64RegClassID),
        GIR_ConstrainOperandRC, /*InsnID*/1, /*Op*/1, GIMT_Encode2(AMDGPU::VGPR_32RegClassID),
        GIR_ConstrainOperandRC, /*InsnID*/1, /*Op*/3, GIMT_Encode2(AMDGPU::VGPR_32RegClassID),
        GIR_BuildMI, /*InsnID*/0, /*Opcode*/GIMT_Encode2(AMDGPU::BUFFER_ATOMIC_INC_BOTHEN),
        GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/1, // vdata_in
        GIR_AddSimpleTempRegister, /*InsnID*/0, /*TempRegID*/0,
        GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/2, // rsrc
        GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/0, // soffset
        GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/6, // offset
        GIR_CustomOperandRenderer, /*InsnID*/0, /*OldInsnID*/0, /*OpIdx*/7, /*OperandRenderer*/GIMT_Encode2(GICR_renderExtractCPol), // auxiliary
        GIR_MergeMemOperands, /*InsnID*/0, /*NumInsns*/1, /*MergeInsnID's*/0,
        GIR_ConstrainSelectedInstOperands, /*InsnID*/0,
        GIR_EraseFromParent, /*InsnID*/0,
        // GIR_Coverage, 4896,
        GIR_Done,
      // Label 6058: @443297
      GIM_Try, /*On fail goto*//*Label 6059*/ GIMT_Encode4(443400), // Rule ID 4904 //
        GIM_CheckHasNoUse, /*MI*/0,
        // MIs[0] offset
        GIM_CheckIsImm, /*MI*/0, /*Op*/6,
        // MIs[0] auxiliary
        GIM_CheckIsImm, /*MI*/0, /*Op*/7,
        // MIs[0] Operand 8
        GIM_CheckIsImm, /*MI*/0, /*Op*/8,
        GIM_CheckComplexPattern, /*MI*/0, /*Op*/5, /*Renderer*/GIMT_Encode2(0), GIMT_Encode2(GICP_gi_buf_soffset),
        // (SIbuffer_atomic_inc:{ *:[i32] } i32:{ *:[i32] }:$vdata_in, v4i32:{ *:[v4i32] }:$rsrc, i32:{ *:[i32] }:$vindex, i32:{ *:[i32] }:$voffset, (BUFSOffset:{ *:[i32] } i32:{ *:[i32] }:$soffset), (timm:{ *:[i32] }):$offset, (timm:{ *:[i32] }):$auxiliary, (timm:{ *:[i1] }))<<P:Predicate_SIbuffer_atomic_inc_noret>>  =>  (BUFFER_ATOMIC_INC_VBUFFER_BOTHEN anonymous_15037:{ *:[i32] }:$vdata_in, (REG_SEQUENCE:{ *:[i64] } VReg_64:{ *:[i32] }, VGPR_32:{ *:[i32] }:$vindex, sub0:{ *:[i32] }, VGPR_32:{ *:[i32] }:$voffset, sub1:{ *:[i32] }), SReg_128:{ *:[v4i32] }:$rsrc, SCSrc_b32:{ *:[i32] }:$soffset, (timm:{ *:[i32] }):$offset, (extract_cpol:{ *:[i32] } ?:{ *:[i32] }:$auxiliary))
        GIR_MakeTempReg, /*TempRegID*/0, /*TypeID*/GILLT_s64,
        GIR_BuildMI, /*InsnID*/1, /*Opcode*/GIMT_Encode2(TargetOpcode::REG_SEQUENCE),
        GIR_AddTempRegister, /*InsnID*/1, /*TempRegID*/0, /*TempRegFlags*/GIMT_Encode2(RegState::Define),
        GIR_Copy, /*NewInsnID*/1, /*OldInsnID*/0, /*OpIdx*/3, // vindex
        GIR_AddImm8, /*InsnID*/1, /*SubRegIndex*/3,
        GIR_Copy, /*NewInsnID*/1, /*OldInsnID*/0, /*OpIdx*/4, // voffset
        GIR_AddImm8, /*InsnID*/1, /*SubRegIndex*/11,
        GIR_ConstrainOperandRC, /*InsnID*/1, /*Op*/0, GIMT_Encode2(AMDGPU::VReg_64RegClassID),
        GIR_ConstrainOperandRC, /*InsnID*/1, /*Op*/1, GIMT_Encode2(AMDGPU::VGPR_32RegClassID),
        GIR_ConstrainOperandRC, /*InsnID*/1, /*Op*/3, GIMT_Encode2(AMDGPU::VGPR_32RegClassID),
        GIR_BuildMI, /*InsnID*/0, /*Opcode*/GIMT_Encode2(AMDGPU::BUFFER_ATOMIC_INC_VBUFFER_BOTHEN),
        GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/1, // vdata_in
        GIR_AddSimpleTempRegister, /*InsnID*/0, /*TempRegID*/0,
        GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/2, // rsrc
        GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/0, // soffset
        GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/6, // offset
        GIR_CustomOperandRenderer, /*InsnID*/0, /*OldInsnID*/0, /*OpIdx*/7, /*OperandRenderer*/GIMT_Encode2(GICR_renderExtractCPol), // auxiliary
        GIR_MergeMemOperands, /*InsnID*/0, /*NumInsns*/1, /*MergeInsnID's*/0,
        GIR_ConstrainSelectedInstOperands, /*InsnID*/0,
        GIR_EraseFromParent, /*InsnID*/0,
        // GIR_Coverage, 4904,
        GIR_Done,
      // Label 6059: @443400
      GIM_Try, /*On fail goto*//*Label 6060*/ GIMT_Encode4(443513), // Rule ID 4892 //
        GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasUnrestrictedSOffset),
        GIM_CheckRegBankForClass, /*MI*/0, /*Op*/0, /*RC*/GIMT_Encode2(AMDGPU::AV_32RegClassID),
        // MIs[0] offset
        GIM_CheckIsImm, /*MI*/0, /*Op*/6,
        // MIs[0] auxiliary
        GIM_CheckIsImm, /*MI*/0, /*Op*/7,
        // MIs[0] Operand 8
        GIM_CheckIsImm, /*MI*/0, /*Op*/8,
        GIM_CheckComplexPattern, /*MI*/0, /*Op*/5, /*Renderer*/GIMT_Encode2(0), GIMT_Encode2(GICP_gi_buf_soffset),
        // (SIbuffer_atomic_inc:{ *:[i32] } i32:{ *:[i32] }:$vdata_in, v4i32:{ *:[v4i32] }:$rsrc, i32:{ *:[i32] }:$vindex, i32:{ *:[i32] }:$voffset, (BUFSOffset:{ *:[i32] } i32:{ *:[i32] }:$soffset), (timm:{ *:[i32] }):$offset, (timm:{ *:[i32] }):$auxiliary, (timm:{ *:[i1] }))  =>  (BUFFER_ATOMIC_INC_BOTHEN_RTN:{ *:[i32] } anonymous_15037:{ *:[i32] }:$vdata_in, (REG_SEQUENCE:{ *:[i64] } VReg_64:{ *:[i32] }, VGPR_32:{ *:[i32] }:$vindex, sub0:{ *:[i32] }, VGPR_32:{ *:[i32] }:$voffset, sub1:{ *:[i32] }), SReg_128:{ *:[v4i32] }:$rsrc, SCSrc_b32:{ *:[i32] }:$soffset, (timm:{ *:[i32] }):$offset, (extract_cpol_set_glc:{ *:[i32] } ?:{ *:[i32] }:$auxiliary))
        GIR_MakeTempReg, /*TempRegID*/0, /*TypeID*/GILLT_s64,
        GIR_BuildMI, /*InsnID*/1, /*Opcode*/GIMT_Encode2(TargetOpcode::REG_SEQUENCE),
        GIR_AddTempRegister, /*InsnID*/1, /*TempRegID*/0, /*TempRegFlags*/GIMT_Encode2(RegState::Define),
        GIR_Copy, /*NewInsnID*/1, /*OldInsnID*/0, /*OpIdx*/3, // vindex
        GIR_AddImm8, /*InsnID*/1, /*SubRegIndex*/3,
        GIR_Copy, /*NewInsnID*/1, /*OldInsnID*/0, /*OpIdx*/4, // voffset
        GIR_AddImm8, /*InsnID*/1, /*SubRegIndex*/11,
        GIR_ConstrainOperandRC, /*InsnID*/1, /*Op*/0, GIMT_Encode2(AMDGPU::VReg_64RegClassID),
        GIR_ConstrainOperandRC, /*InsnID*/1, /*Op*/1, GIMT_Encode2(AMDGPU::VGPR_32RegClassID),
        GIR_ConstrainOperandRC, /*InsnID*/1, /*Op*/3, GIMT_Encode2(AMDGPU::VGPR_32RegClassID),
        GIR_BuildMI, /*InsnID*/0, /*Opcode*/GIMT_Encode2(AMDGPU::BUFFER_ATOMIC_INC_BOTHEN_RTN),
        GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/0, // DstI[vdata]
        GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/1, // vdata_in
        GIR_AddSimpleTempRegister, /*InsnID*/0, /*TempRegID*/0,
        GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/2, // rsrc
        GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/0, // soffset
        GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/6, // offset
        GIR_CustomOperandRenderer, /*InsnID*/0, /*OldInsnID*/0, /*OpIdx*/7, /*OperandRenderer*/GIMT_Encode2(GICR_renderExtractCpolSetGLC), // auxiliary
        GIR_MergeMemOperands, /*InsnID*/0, /*NumInsns*/1, /*MergeInsnID's*/0,
        GIR_ConstrainSelectedInstOperands, /*InsnID*/0,
        GIR_EraseFromParent, /*InsnID*/0,
        // GIR_Coverage, 4892,
        GIR_Done,
      // Label 6060: @443513
      GIM_Try, /*On fail goto*//*Label 6061*/ GIMT_Encode4(443623), // Rule ID 4900 //
        GIM_CheckRegBankForClass, /*MI*/0, /*Op*/0, /*RC*/GIMT_Encode2(AMDGPU::AV_32RegClassID),
        // MIs[0] offset
        GIM_CheckIsImm, /*MI*/0, /*Op*/6,
        // MIs[0] auxiliary
        GIM_CheckIsImm, /*MI*/0, /*Op*/7,
        // MIs[0] Operand 8
        GIM_CheckIsImm, /*MI*/0, /*Op*/8,
        GIM_CheckComplexPattern, /*MI*/0, /*Op*/5, /*Renderer*/GIMT_Encode2(0), GIMT_Encode2(GICP_gi_buf_soffset),
        // (SIbuffer_atomic_inc:{ *:[i32] } i32:{ *:[i32] }:$vdata_in, v4i32:{ *:[v4i32] }:$rsrc, i32:{ *:[i32] }:$vindex, i32:{ *:[i32] }:$voffset, (BUFSOffset:{ *:[i32] } i32:{ *:[i32] }:$soffset), (timm:{ *:[i32] }):$offset, (timm:{ *:[i32] }):$auxiliary, (timm:{ *:[i1] }))  =>  (BUFFER_ATOMIC_INC_VBUFFER_BOTHEN_RTN:{ *:[i32] } anonymous_15037:{ *:[i32] }:$vdata_in, (REG_SEQUENCE:{ *:[i64] } VReg_64:{ *:[i32] }, VGPR_32:{ *:[i32] }:$vindex, sub0:{ *:[i32] }, VGPR_32:{ *:[i32] }:$voffset, sub1:{ *:[i32] }), SReg_128:{ *:[v4i32] }:$rsrc, SCSrc_b32:{ *:[i32] }:$soffset, (timm:{ *:[i32] }):$offset, (extract_cpol_set_glc:{ *:[i32] } ?:{ *:[i32] }:$auxiliary))
        GIR_MakeTempReg, /*TempRegID*/0, /*TypeID*/GILLT_s64,
        GIR_BuildMI, /*InsnID*/1, /*Opcode*/GIMT_Encode2(TargetOpcode::REG_SEQUENCE),
        GIR_AddTempRegister, /*InsnID*/1, /*TempRegID*/0, /*TempRegFlags*/GIMT_Encode2(RegState::Define),
        GIR_Copy, /*NewInsnID*/1, /*OldInsnID*/0, /*OpIdx*/3, // vindex
        GIR_AddImm8, /*InsnID*/1, /*SubRegIndex*/3,
        GIR_Copy, /*NewInsnID*/1, /*OldInsnID*/0, /*OpIdx*/4, // voffset
        GIR_AddImm8, /*InsnID*/1, /*SubRegIndex*/11,
        GIR_ConstrainOperandRC, /*InsnID*/1, /*Op*/0, GIMT_Encode2(AMDGPU::VReg_64RegClassID),
        GIR_ConstrainOperandRC, /*InsnID*/1, /*Op*/1, GIMT_Encode2(AMDGPU::VGPR_32RegClassID),
        GIR_ConstrainOperandRC, /*InsnID*/1, /*Op*/3, GIMT_Encode2(AMDGPU::VGPR_32RegClassID),
        GIR_BuildMI, /*InsnID*/0, /*Opcode*/GIMT_Encode2(AMDGPU::BUFFER_ATOMIC_INC_VBUFFER_BOTHEN_RTN),
        GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/0, // DstI[vdata]
        GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/1, // vdata_in
        GIR_AddSimpleTempRegister, /*InsnID*/0, /*TempRegID*/0,
        GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/2, // rsrc
        GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/0, // soffset
        GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/6, // offset
        GIR_CustomOperandRenderer, /*InsnID*/0, /*OldInsnID*/0, /*OpIdx*/7, /*OperandRenderer*/GIMT_Encode2(GICR_renderExtractCpolSetGLC), // auxiliary
        GIR_MergeMemOperands, /*InsnID*/0, /*NumInsns*/1, /*MergeInsnID's*/0,
        GIR_ConstrainSelectedInstOperands, /*InsnID*/0,
        GIR_EraseFromParent, /*InsnID*/0,
        // GIR_Coverage, 4900,
        GIR_Done,
      // Label 6061: @443623
      GIM_Reject,
    // Label 6045: @443624
    GIM_Reject,
    // Label 6043: @443625
    GIM_Try, /*On fail goto*//*Label 6062*/ GIMT_Encode4(445011),
      GIM_CheckType, /*MI*/0, /*Op*/1, /*Type*/GILLT_s64,
      GIM_CheckType, /*MI*/0, /*Op*/2, /*Type*/GILLT_v4s32,
      GIM_CheckType, /*MI*/0, /*Op*/3, /*Type*/GILLT_s32,
      GIM_CheckType, /*MI*/0, /*Op*/4, /*Type*/GILLT_s32,
      GIM_CheckType, /*MI*/0, /*Op*/5, /*Type*/GILLT_s32,
      GIM_Try, /*On fail goto*//*Label 6063*/ GIMT_Encode4(443728), // Rule ID 5093 //
        GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasUnrestrictedSOffset),
        GIM_CheckHasNoUse, /*MI*/0,
        GIM_CheckConstantInt8, /*MI*/0, /*Op*/3, 0,
        GIM_CheckConstantInt8, /*MI*/0, /*Op*/4, 0,
        // MIs[0] offset
        GIM_CheckIsImm, /*MI*/0, /*Op*/6,
        // MIs[0] auxiliary
        GIM_CheckIsImm, /*MI*/0, /*Op*/7,
        // MIs[0] Operand 8
        GIM_CheckLiteralInt, /*MI*/0, /*Op*/8, GIMT_Encode8(0),
        GIM_CheckComplexPattern, /*MI*/0, /*Op*/5, /*Renderer*/GIMT_Encode2(0), GIMT_Encode2(GICP_gi_buf_soffset),
        // (SIbuffer_atomic_inc:{ *:[i64] } i64:{ *:[i64] }:$vdata_in, v4i32:{ *:[v4i32] }:$rsrc, 0:{ *:[i32] }, 0:{ *:[i32] }, (BUFSOffset:{ *:[i32] } i32:{ *:[i32] }:$soffset), (timm:{ *:[i32] }):$offset, (timm:{ *:[i32] }):$auxiliary, 0:{ *:[i1] })<<P:Predicate_SIbuffer_atomic_inc_noret>>  =>  (BUFFER_ATOMIC_INC_X2_OFFSET anonymous_15036:{ *:[i64] }:$vdata_in, SReg_128:{ *:[v4i32] }:$rsrc, SCSrc_b32:{ *:[i32] }:$soffset, (timm:{ *:[i32] }):$offset, (extract_cpol:{ *:[i32] } ?:{ *:[i32] }:$auxiliary))
        GIR_BuildMI, /*InsnID*/0, /*Opcode*/GIMT_Encode2(AMDGPU::BUFFER_ATOMIC_INC_X2_OFFSET),
        GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/1, // vdata_in
        GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/2, // rsrc
        GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/0, // soffset
        GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/6, // offset
        GIR_CustomOperandRenderer, /*InsnID*/0, /*OldInsnID*/0, /*OpIdx*/7, /*OperandRenderer*/GIMT_Encode2(GICR_renderExtractCPol), // auxiliary
        GIR_MergeMemOperands, /*InsnID*/0, /*NumInsns*/1, /*MergeInsnID's*/0,
        GIR_ConstrainSelectedInstOperands, /*InsnID*/0,
        GIR_EraseFromParent, /*InsnID*/0,
        // GIR_Coverage, 5093,
        GIR_Done,
      // Label 6063: @443728
      GIM_Try, /*On fail goto*//*Label 6064*/ GIMT_Encode4(443803), // Rule ID 5101 //
        GIM_CheckHasNoUse, /*MI*/0,
        GIM_CheckConstantInt8, /*MI*/0, /*Op*/3, 0,
        GIM_CheckConstantInt8, /*MI*/0, /*Op*/4, 0,
        // MIs[0] offset
        GIM_CheckIsImm, /*MI*/0, /*Op*/6,
        // MIs[0] auxiliary
        GIM_CheckIsImm, /*MI*/0, /*Op*/7,
        // MIs[0] Operand 8
        GIM_CheckLiteralInt, /*MI*/0, /*Op*/8, GIMT_Encode8(0),
        GIM_CheckComplexPattern, /*MI*/0, /*Op*/5, /*Renderer*/GIMT_Encode2(0), GIMT_Encode2(GICP_gi_buf_soffset),
        // (SIbuffer_atomic_inc:{ *:[i64] } i64:{ *:[i64] }:$vdata_in, v4i32:{ *:[v4i32] }:$rsrc, 0:{ *:[i32] }, 0:{ *:[i32] }, (BUFSOffset:{ *:[i32] } i32:{ *:[i32] }:$soffset), (timm:{ *:[i32] }):$offset, (timm:{ *:[i32] }):$auxiliary, 0:{ *:[i1] })<<P:Predicate_SIbuffer_atomic_inc_noret>>  =>  (BUFFER_ATOMIC_INC_X2_VBUFFER_OFFSET anonymous_15036:{ *:[i64] }:$vdata_in, SReg_128:{ *:[v4i32] }:$rsrc, SCSrc_b32:{ *:[i32] }:$soffset, (timm:{ *:[i32] }):$offset, (extract_cpol:{ *:[i32] } ?:{ *:[i32] }:$auxiliary))
        GIR_BuildMI, /*InsnID*/0, /*Opcode*/GIMT_Encode2(AMDGPU::BUFFER_ATOMIC_INC_X2_VBUFFER_OFFSET),
        GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/1, // vdata_in
        GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/2, // rsrc
        GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/0, // soffset
        GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/6, // offset
        GIR_CustomOperandRenderer, /*InsnID*/0, /*OldInsnID*/0, /*OpIdx*/7, /*OperandRenderer*/GIMT_Encode2(GICR_renderExtractCPol), // auxiliary
        GIR_MergeMemOperands, /*InsnID*/0, /*NumInsns*/1, /*MergeInsnID's*/0,
        GIR_ConstrainSelectedInstOperands, /*InsnID*/0,
        GIR_EraseFromParent, /*InsnID*/0,
        // GIR_Coverage, 5101,
        GIR_Done,
      // Label 6064: @443803
      GIM_Try, /*On fail goto*//*Label 6065*/ GIMT_Encode4(443888), // Rule ID 5089 //
        GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasUnrestrictedSOffset),
        GIM_CheckRegBankForClass, /*MI*/0, /*Op*/0, /*RC*/GIMT_Encode2(AMDGPU::AV_64RegClassID),
        GIM_CheckConstantInt8, /*MI*/0, /*Op*/3, 0,
        GIM_CheckConstantInt8, /*MI*/0, /*Op*/4, 0,
        // MIs[0] offset
        GIM_CheckIsImm, /*MI*/0, /*Op*/6,
        // MIs[0] auxiliary
        GIM_CheckIsImm, /*MI*/0, /*Op*/7,
        // MIs[0] Operand 8
        GIM_CheckLiteralInt, /*MI*/0, /*Op*/8, GIMT_Encode8(0),
        GIM_CheckComplexPattern, /*MI*/0, /*Op*/5, /*Renderer*/GIMT_Encode2(0), GIMT_Encode2(GICP_gi_buf_soffset),
        // (SIbuffer_atomic_inc:{ *:[i64] } i64:{ *:[i64] }:$vdata_in, v4i32:{ *:[v4i32] }:$rsrc, 0:{ *:[i32] }, 0:{ *:[i32] }, (BUFSOffset:{ *:[i32] } i32:{ *:[i32] }:$soffset), (timm:{ *:[i32] }):$offset, (timm:{ *:[i32] }):$auxiliary, 0:{ *:[i1] })  =>  (BUFFER_ATOMIC_INC_X2_OFFSET_RTN:{ *:[i64] } anonymous_15036:{ *:[i64] }:$vdata_in, SReg_128:{ *:[v4i32] }:$rsrc, SCSrc_b32:{ *:[i32] }:$soffset, (timm:{ *:[i32] }):$offset, (extract_cpol_set_glc:{ *:[i32] } ?:{ *:[i32] }:$auxiliary))
        GIR_BuildMI, /*InsnID*/0, /*Opcode*/GIMT_Encode2(AMDGPU::BUFFER_ATOMIC_INC_X2_OFFSET_RTN),
        GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/0, // DstI[vdata]
        GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/1, // vdata_in
        GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/2, // rsrc
        GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/0, // soffset
        GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/6, // offset
        GIR_CustomOperandRenderer, /*InsnID*/0, /*OldInsnID*/0, /*OpIdx*/7, /*OperandRenderer*/GIMT_Encode2(GICR_renderExtractCpolSetGLC), // auxiliary
        GIR_MergeMemOperands, /*InsnID*/0, /*NumInsns*/1, /*MergeInsnID's*/0,
        GIR_ConstrainSelectedInstOperands, /*InsnID*/0,
        GIR_EraseFromParent, /*InsnID*/0,
        // GIR_Coverage, 5089,
        GIR_Done,
      // Label 6065: @443888
      GIM_Try, /*On fail goto*//*Label 6066*/ GIMT_Encode4(443970), // Rule ID 5097 //
        GIM_CheckRegBankForClass, /*MI*/0, /*Op*/0, /*RC*/GIMT_Encode2(AMDGPU::AV_64RegClassID),
        GIM_CheckConstantInt8, /*MI*/0, /*Op*/3, 0,
        GIM_CheckConstantInt8, /*MI*/0, /*Op*/4, 0,
        // MIs[0] offset
        GIM_CheckIsImm, /*MI*/0, /*Op*/6,
        // MIs[0] auxiliary
        GIM_CheckIsImm, /*MI*/0, /*Op*/7,
        // MIs[0] Operand 8
        GIM_CheckLiteralInt, /*MI*/0, /*Op*/8, GIMT_Encode8(0),
        GIM_CheckComplexPattern, /*MI*/0, /*Op*/5, /*Renderer*/GIMT_Encode2(0), GIMT_Encode2(GICP_gi_buf_soffset),
        // (SIbuffer_atomic_inc:{ *:[i64] } i64:{ *:[i64] }:$vdata_in, v4i32:{ *:[v4i32] }:$rsrc, 0:{ *:[i32] }, 0:{ *:[i32] }, (BUFSOffset:{ *:[i32] } i32:{ *:[i32] }:$soffset), (timm:{ *:[i32] }):$offset, (timm:{ *:[i32] }):$auxiliary, 0:{ *:[i1] })  =>  (BUFFER_ATOMIC_INC_X2_VBUFFER_OFFSET_RTN:{ *:[i64] } anonymous_15036:{ *:[i64] }:$vdata_in, SReg_128:{ *:[v4i32] }:$rsrc, SCSrc_b32:{ *:[i32] }:$soffset, (timm:{ *:[i32] }):$offset, (extract_cpol_set_glc:{ *:[i32] } ?:{ *:[i32] }:$auxiliary))
        GIR_BuildMI, /*InsnID*/0, /*Opcode*/GIMT_Encode2(AMDGPU::BUFFER_ATOMIC_INC_X2_VBUFFER_OFFSET_RTN),
        GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/0, // DstI[vdata]
        GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/1, // vdata_in
        GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/2, // rsrc
        GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/0, // soffset
        GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/6, // offset
        GIR_CustomOperandRenderer, /*InsnID*/0, /*OldInsnID*/0, /*OpIdx*/7, /*OperandRenderer*/GIMT_Encode2(GICR_renderExtractCpolSetGLC), // auxiliary
        GIR_MergeMemOperands, /*InsnID*/0, /*NumInsns*/1, /*MergeInsnID's*/0,
        GIR_ConstrainSelectedInstOperands, /*InsnID*/0,
        GIR_EraseFromParent, /*InsnID*/0,
        // GIR_Coverage, 5097,
        GIR_Done,
      // Label 6066: @443970
      GIM_Try, /*On fail goto*//*Label 6067*/ GIMT_Encode4(444048), // Rule ID 5095 //
        GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasUnrestrictedSOffset),
        GIM_CheckHasNoUse, /*MI*/0,
        GIM_CheckConstantInt8, /*MI*/0, /*Op*/3, 0,
        // MIs[0] offset
        GIM_CheckIsImm, /*MI*/0, /*Op*/6,
        // MIs[0] auxiliary
        GIM_CheckIsImm, /*MI*/0, /*Op*/7,
        // MIs[0] Operand 8
        GIM_CheckLiteralInt, /*MI*/0, /*Op*/8, GIMT_Encode8(0),
        GIM_CheckComplexPattern, /*MI*/0, /*Op*/5, /*Renderer*/GIMT_Encode2(0), GIMT_Encode2(GICP_gi_buf_soffset),
        // (SIbuffer_atomic_inc:{ *:[i64] } i64:{ *:[i64] }:$vdata_in, v4i32:{ *:[v4i32] }:$rsrc, 0:{ *:[i32] }, i32:{ *:[i32] }:$voffset, (BUFSOffset:{ *:[i32] } i32:{ *:[i32] }:$soffset), (timm:{ *:[i32] }):$offset, (timm:{ *:[i32] }):$auxiliary, 0:{ *:[i1] })<<P:Predicate_SIbuffer_atomic_inc_noret>>  =>  (BUFFER_ATOMIC_INC_X2_OFFEN anonymous_15036:{ *:[i64] }:$vdata_in, VGPR_32:{ *:[i32] }:$voffset, SReg_128:{ *:[v4i32] }:$rsrc, SCSrc_b32:{ *:[i32] }:$soffset, (timm:{ *:[i32] }):$offset, (extract_cpol:{ *:[i32] } ?:{ *:[i32] }:$auxiliary))
        GIR_BuildMI, /*InsnID*/0, /*Opcode*/GIMT_Encode2(AMDGPU::BUFFER_ATOMIC_INC_X2_OFFEN),
        GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/1, // vdata_in
        GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/4, // voffset
        GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/2, // rsrc
        GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/0, // soffset
        GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/6, // offset
        GIR_CustomOperandRenderer, /*InsnID*/0, /*OldInsnID*/0, /*OpIdx*/7, /*OperandRenderer*/GIMT_Encode2(GICR_renderExtractCPol), // auxiliary
        GIR_MergeMemOperands, /*InsnID*/0, /*NumInsns*/1, /*MergeInsnID's*/0,
        GIR_ConstrainSelectedInstOperands, /*InsnID*/0,
        GIR_EraseFromParent, /*InsnID*/0,
        // GIR_Coverage, 5095,
        GIR_Done,
      // Label 6067: @444048
      GIM_Try, /*On fail goto*//*Label 6068*/ GIMT_Encode4(444123), // Rule ID 5103 //
        GIM_CheckHasNoUse, /*MI*/0,
        GIM_CheckConstantInt8, /*MI*/0, /*Op*/3, 0,
        // MIs[0] offset
        GIM_CheckIsImm, /*MI*/0, /*Op*/6,
        // MIs[0] auxiliary
        GIM_CheckIsImm, /*MI*/0, /*Op*/7,
        // MIs[0] Operand 8
        GIM_CheckLiteralInt, /*MI*/0, /*Op*/8, GIMT_Encode8(0),
        GIM_CheckComplexPattern, /*MI*/0, /*Op*/5, /*Renderer*/GIMT_Encode2(0), GIMT_Encode2(GICP_gi_buf_soffset),
        // (SIbuffer_atomic_inc:{ *:[i64] } i64:{ *:[i64] }:$vdata_in, v4i32:{ *:[v4i32] }:$rsrc, 0:{ *:[i32] }, i32:{ *:[i32] }:$voffset, (BUFSOffset:{ *:[i32] } i32:{ *:[i32] }:$soffset), (timm:{ *:[i32] }):$offset, (timm:{ *:[i32] }):$auxiliary, 0:{ *:[i1] })<<P:Predicate_SIbuffer_atomic_inc_noret>>  =>  (BUFFER_ATOMIC_INC_X2_VBUFFER_OFFEN anonymous_15036:{ *:[i64] }:$vdata_in, VGPR_32:{ *:[i32] }:$voffset, SReg_128:{ *:[v4i32] }:$rsrc, SCSrc_b32:{ *:[i32] }:$soffset, (timm:{ *:[i32] }):$offset, (extract_cpol:{ *:[i32] } ?:{ *:[i32] }:$auxiliary))
        GIR_BuildMI, /*InsnID*/0, /*Opcode*/GIMT_Encode2(AMDGPU::BUFFER_ATOMIC_INC_X2_VBUFFER_OFFEN),
        GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/1, // vdata_in
        GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/4, // voffset
        GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/2, // rsrc
        GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/0, // soffset
        GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/6, // offset
        GIR_CustomOperandRenderer, /*InsnID*/0, /*OldInsnID*/0, /*OpIdx*/7, /*OperandRenderer*/GIMT_Encode2(GICR_renderExtractCPol), // auxiliary
        GIR_MergeMemOperands, /*InsnID*/0, /*NumInsns*/1, /*MergeInsnID's*/0,
        GIR_ConstrainSelectedInstOperands, /*InsnID*/0,
        GIR_EraseFromParent, /*InsnID*/0,
        // GIR_Coverage, 5103,
        GIR_Done,
      // Label 6068: @444123
      GIM_Try, /*On fail goto*//*Label 6069*/ GIMT_Encode4(444208), // Rule ID 5091 //
        GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasUnrestrictedSOffset),
        GIM_CheckRegBankForClass, /*MI*/0, /*Op*/0, /*RC*/GIMT_Encode2(AMDGPU::AV_64RegClassID),
        GIM_CheckConstantInt8, /*MI*/0, /*Op*/3, 0,
        // MIs[0] offset
        GIM_CheckIsImm, /*MI*/0, /*Op*/6,
        // MIs[0] auxiliary
        GIM_CheckIsImm, /*MI*/0, /*Op*/7,
        // MIs[0] Operand 8
        GIM_CheckLiteralInt, /*MI*/0, /*Op*/8, GIMT_Encode8(0),
        GIM_CheckComplexPattern, /*MI*/0, /*Op*/5, /*Renderer*/GIMT_Encode2(0), GIMT_Encode2(GICP_gi_buf_soffset),
        // (SIbuffer_atomic_inc:{ *:[i64] } i64:{ *:[i64] }:$vdata_in, v4i32:{ *:[v4i32] }:$rsrc, 0:{ *:[i32] }, i32:{ *:[i32] }:$voffset, (BUFSOffset:{ *:[i32] } i32:{ *:[i32] }:$soffset), (timm:{ *:[i32] }):$offset, (timm:{ *:[i32] }):$auxiliary, 0:{ *:[i1] })  =>  (BUFFER_ATOMIC_INC_X2_OFFEN_RTN:{ *:[i64] } anonymous_15036:{ *:[i64] }:$vdata_in, VGPR_32:{ *:[i32] }:$voffset, SReg_128:{ *:[v4i32] }:$rsrc, SCSrc_b32:{ *:[i32] }:$soffset, (timm:{ *:[i32] }):$offset, (extract_cpol_set_glc:{ *:[i32] } ?:{ *:[i32] }:$auxiliary))
        GIR_BuildMI, /*InsnID*/0, /*Opcode*/GIMT_Encode2(AMDGPU::BUFFER_ATOMIC_INC_X2_OFFEN_RTN),
        GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/0, // DstI[vdata]
        GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/1, // vdata_in
        GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/4, // voffset
        GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/2, // rsrc
        GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/0, // soffset
        GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/6, // offset
        GIR_CustomOperandRenderer, /*InsnID*/0, /*OldInsnID*/0, /*OpIdx*/7, /*OperandRenderer*/GIMT_Encode2(GICR_renderExtractCpolSetGLC), // auxiliary
        GIR_MergeMemOperands, /*InsnID*/0, /*NumInsns*/1, /*MergeInsnID's*/0,
        GIR_ConstrainSelectedInstOperands, /*InsnID*/0,
        GIR_EraseFromParent, /*InsnID*/0,
        // GIR_Coverage, 5091,
        GIR_Done,
      // Label 6069: @444208
      GIM_Try, /*On fail goto*//*Label 6070*/ GIMT_Encode4(444290), // Rule ID 5099 //
        GIM_CheckRegBankForClass, /*MI*/0, /*Op*/0, /*RC*/GIMT_Encode2(AMDGPU::AV_64RegClassID),
        GIM_CheckConstantInt8, /*MI*/0, /*Op*/3, 0,
        // MIs[0] offset
        GIM_CheckIsImm, /*MI*/0, /*Op*/6,
        // MIs[0] auxiliary
        GIM_CheckIsImm, /*MI*/0, /*Op*/7,
        // MIs[0] Operand 8
        GIM_CheckLiteralInt, /*MI*/0, /*Op*/8, GIMT_Encode8(0),
        GIM_CheckComplexPattern, /*MI*/0, /*Op*/5, /*Renderer*/GIMT_Encode2(0), GIMT_Encode2(GICP_gi_buf_soffset),
        // (SIbuffer_atomic_inc:{ *:[i64] } i64:{ *:[i64] }:$vdata_in, v4i32:{ *:[v4i32] }:$rsrc, 0:{ *:[i32] }, i32:{ *:[i32] }:$voffset, (BUFSOffset:{ *:[i32] } i32:{ *:[i32] }:$soffset), (timm:{ *:[i32] }):$offset, (timm:{ *:[i32] }):$auxiliary, 0:{ *:[i1] })  =>  (BUFFER_ATOMIC_INC_X2_VBUFFER_OFFEN_RTN:{ *:[i64] } anonymous_15036:{ *:[i64] }:$vdata_in, VGPR_32:{ *:[i32] }:$voffset, SReg_128:{ *:[v4i32] }:$rsrc, SCSrc_b32:{ *:[i32] }:$soffset, (timm:{ *:[i32] }):$offset, (extract_cpol_set_glc:{ *:[i32] } ?:{ *:[i32] }:$auxiliary))
        GIR_BuildMI, /*InsnID*/0, /*Opcode*/GIMT_Encode2(AMDGPU::BUFFER_ATOMIC_INC_X2_VBUFFER_OFFEN_RTN),
        GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/0, // DstI[vdata]
        GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/1, // vdata_in
        GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/4, // voffset
        GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/2, // rsrc
        GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/0, // soffset
        GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/6, // offset
        GIR_CustomOperandRenderer, /*InsnID*/0, /*OldInsnID*/0, /*OpIdx*/7, /*OperandRenderer*/GIMT_Encode2(GICR_renderExtractCpolSetGLC), // auxiliary
        GIR_MergeMemOperands, /*InsnID*/0, /*NumInsns*/1, /*MergeInsnID's*/0,
        GIR_ConstrainSelectedInstOperands, /*InsnID*/0,
        GIR_EraseFromParent, /*InsnID*/0,
        // GIR_Coverage, 5099,
        GIR_Done,
      // Label 6070: @444290
      GIM_Try, /*On fail goto*//*Label 6071*/ GIMT_Encode4(444360), // Rule ID 5094 //
        GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasUnrestrictedSOffset),
        GIM_CheckHasNoUse, /*MI*/0,
        GIM_CheckConstantInt8, /*MI*/0, /*Op*/4, 0,
        // MIs[0] offset
        GIM_CheckIsImm, /*MI*/0, /*Op*/6,
        // MIs[0] auxiliary
        GIM_CheckIsImm, /*MI*/0, /*Op*/7,
        // MIs[0] Operand 8
        GIM_CheckIsImm, /*MI*/0, /*Op*/8,
        GIM_CheckComplexPattern, /*MI*/0, /*Op*/5, /*Renderer*/GIMT_Encode2(0), GIMT_Encode2(GICP_gi_buf_soffset),
        // (SIbuffer_atomic_inc:{ *:[i64] } i64:{ *:[i64] }:$vdata_in, v4i32:{ *:[v4i32] }:$rsrc, i32:{ *:[i32] }:$vindex, 0:{ *:[i32] }, (BUFSOffset:{ *:[i32] } i32:{ *:[i32] }:$soffset), (timm:{ *:[i32] }):$offset, (timm:{ *:[i32] }):$auxiliary, (timm:{ *:[i1] }))<<P:Predicate_SIbuffer_atomic_inc_noret>>  =>  (BUFFER_ATOMIC_INC_X2_IDXEN anonymous_15036:{ *:[i64] }:$vdata_in, VGPR_32:{ *:[i32] }:$vindex, SReg_128:{ *:[v4i32] }:$rsrc, SCSrc_b32:{ *:[i32] }:$soffset, (timm:{ *:[i32] }):$offset, (extract_cpol:{ *:[i32] } ?:{ *:[i32] }:$auxiliary))
        GIR_BuildMI, /*InsnID*/0, /*Opcode*/GIMT_Encode2(AMDGPU::BUFFER_ATOMIC_INC_X2_IDXEN),
        GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/1, // vdata_in
        GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/3, // vindex
        GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/2, // rsrc
        GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/0, // soffset
        GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/6, // offset
        GIR_CustomOperandRenderer, /*InsnID*/0, /*OldInsnID*/0, /*OpIdx*/7, /*OperandRenderer*/GIMT_Encode2(GICR_renderExtractCPol), // auxiliary
        GIR_MergeMemOperands, /*InsnID*/0, /*NumInsns*/1, /*MergeInsnID's*/0,
        GIR_ConstrainSelectedInstOperands, /*InsnID*/0,
        GIR_EraseFromParent, /*InsnID*/0,
        // GIR_Coverage, 5094,
        GIR_Done,
      // Label 6071: @444360
      GIM_Try, /*On fail goto*//*Label 6072*/ GIMT_Encode4(444427), // Rule ID 5102 //
        GIM_CheckHasNoUse, /*MI*/0,
        GIM_CheckConstantInt8, /*MI*/0, /*Op*/4, 0,
        // MIs[0] offset
        GIM_CheckIsImm, /*MI*/0, /*Op*/6,
        // MIs[0] auxiliary
        GIM_CheckIsImm, /*MI*/0, /*Op*/7,
        // MIs[0] Operand 8
        GIM_CheckIsImm, /*MI*/0, /*Op*/8,
        GIM_CheckComplexPattern, /*MI*/0, /*Op*/5, /*Renderer*/GIMT_Encode2(0), GIMT_Encode2(GICP_gi_buf_soffset),
        // (SIbuffer_atomic_inc:{ *:[i64] } i64:{ *:[i64] }:$vdata_in, v4i32:{ *:[v4i32] }:$rsrc, i32:{ *:[i32] }:$vindex, 0:{ *:[i32] }, (BUFSOffset:{ *:[i32] } i32:{ *:[i32] }:$soffset), (timm:{ *:[i32] }):$offset, (timm:{ *:[i32] }):$auxiliary, (timm:{ *:[i1] }))<<P:Predicate_SIbuffer_atomic_inc_noret>>  =>  (BUFFER_ATOMIC_INC_X2_VBUFFER_IDXEN anonymous_15036:{ *:[i64] }:$vdata_in, VGPR_32:{ *:[i32] }:$vindex, SReg_128:{ *:[v4i32] }:$rsrc, SCSrc_b32:{ *:[i32] }:$soffset, (timm:{ *:[i32] }):$offset, (extract_cpol:{ *:[i32] } ?:{ *:[i32] }:$auxiliary))
        GIR_BuildMI, /*InsnID*/0, /*Opcode*/GIMT_Encode2(AMDGPU::BUFFER_ATOMIC_INC_X2_VBUFFER_IDXEN),
        GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/1, // vdata_in
        GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/3, // vindex
        GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/2, // rsrc
        GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/0, // soffset
        GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/6, // offset
        GIR_CustomOperandRenderer, /*InsnID*/0, /*OldInsnID*/0, /*OpIdx*/7, /*OperandRenderer*/GIMT_Encode2(GICR_renderExtractCPol), // auxiliary
        GIR_MergeMemOperands, /*InsnID*/0, /*NumInsns*/1, /*MergeInsnID's*/0,
        GIR_ConstrainSelectedInstOperands, /*InsnID*/0,
        GIR_EraseFromParent, /*InsnID*/0,
        // GIR_Coverage, 5102,
        GIR_Done,
      // Label 6072: @444427
      GIM_Try, /*On fail goto*//*Label 6073*/ GIMT_Encode4(444504), // Rule ID 5090 //
        GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasUnrestrictedSOffset),
        GIM_CheckRegBankForClass, /*MI*/0, /*Op*/0, /*RC*/GIMT_Encode2(AMDGPU::AV_64RegClassID),
        GIM_CheckConstantInt8, /*MI*/0, /*Op*/4, 0,
        // MIs[0] offset
        GIM_CheckIsImm, /*MI*/0, /*Op*/6,
        // MIs[0] auxiliary
        GIM_CheckIsImm, /*MI*/0, /*Op*/7,
        // MIs[0] Operand 8
        GIM_CheckIsImm, /*MI*/0, /*Op*/8,
        GIM_CheckComplexPattern, /*MI*/0, /*Op*/5, /*Renderer*/GIMT_Encode2(0), GIMT_Encode2(GICP_gi_buf_soffset),
        // (SIbuffer_atomic_inc:{ *:[i64] } i64:{ *:[i64] }:$vdata_in, v4i32:{ *:[v4i32] }:$rsrc, i32:{ *:[i32] }:$vindex, 0:{ *:[i32] }, (BUFSOffset:{ *:[i32] } i32:{ *:[i32] }:$soffset), (timm:{ *:[i32] }):$offset, (timm:{ *:[i32] }):$auxiliary, (timm:{ *:[i1] }))  =>  (BUFFER_ATOMIC_INC_X2_IDXEN_RTN:{ *:[i64] } anonymous_15036:{ *:[i64] }:$vdata_in, VGPR_32:{ *:[i32] }:$vindex, SReg_128:{ *:[v4i32] }:$rsrc, SCSrc_b32:{ *:[i32] }:$soffset, (timm:{ *:[i32] }):$offset, (extract_cpol_set_glc:{ *:[i32] } ?:{ *:[i32] }:$auxiliary))
        GIR_BuildMI, /*InsnID*/0, /*Opcode*/GIMT_Encode2(AMDGPU::BUFFER_ATOMIC_INC_X2_IDXEN_RTN),
        GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/0, // DstI[vdata]
        GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/1, // vdata_in
        GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/3, // vindex
        GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/2, // rsrc
        GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/0, // soffset
        GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/6, // offset
        GIR_CustomOperandRenderer, /*InsnID*/0, /*OldInsnID*/0, /*OpIdx*/7, /*OperandRenderer*/GIMT_Encode2(GICR_renderExtractCpolSetGLC), // auxiliary
        GIR_MergeMemOperands, /*InsnID*/0, /*NumInsns*/1, /*MergeInsnID's*/0,
        GIR_ConstrainSelectedInstOperands, /*InsnID*/0,
        GIR_EraseFromParent, /*InsnID*/0,
        // GIR_Coverage, 5090,
        GIR_Done,
      // Label 6073: @444504
      GIM_Try, /*On fail goto*//*Label 6074*/ GIMT_Encode4(444578), // Rule ID 5098 //
        GIM_CheckRegBankForClass, /*MI*/0, /*Op*/0, /*RC*/GIMT_Encode2(AMDGPU::AV_64RegClassID),
        GIM_CheckConstantInt8, /*MI*/0, /*Op*/4, 0,
        // MIs[0] offset
        GIM_CheckIsImm, /*MI*/0, /*Op*/6,
        // MIs[0] auxiliary
        GIM_CheckIsImm, /*MI*/0, /*Op*/7,
        // MIs[0] Operand 8
        GIM_CheckIsImm, /*MI*/0, /*Op*/8,
        GIM_CheckComplexPattern, /*MI*/0, /*Op*/5, /*Renderer*/GIMT_Encode2(0), GIMT_Encode2(GICP_gi_buf_soffset),
        // (SIbuffer_atomic_inc:{ *:[i64] } i64:{ *:[i64] }:$vdata_in, v4i32:{ *:[v4i32] }:$rsrc, i32:{ *:[i32] }:$vindex, 0:{ *:[i32] }, (BUFSOffset:{ *:[i32] } i32:{ *:[i32] }:$soffset), (timm:{ *:[i32] }):$offset, (timm:{ *:[i32] }):$auxiliary, (timm:{ *:[i1] }))  =>  (BUFFER_ATOMIC_INC_X2_VBUFFER_IDXEN_RTN:{ *:[i64] } anonymous_15036:{ *:[i64] }:$vdata_in, VGPR_32:{ *:[i32] }:$vindex, SReg_128:{ *:[v4i32] }:$rsrc, SCSrc_b32:{ *:[i32] }:$soffset, (timm:{ *:[i32] }):$offset, (extract_cpol_set_glc:{ *:[i32] } ?:{ *:[i32] }:$auxiliary))
        GIR_BuildMI, /*InsnID*/0, /*Opcode*/GIMT_Encode2(AMDGPU::BUFFER_ATOMIC_INC_X2_VBUFFER_IDXEN_RTN),
        GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/0, // DstI[vdata]
        GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/1, // vdata_in
        GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/3, // vindex
        GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/2, // rsrc
        GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/0, // soffset
        GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/6, // offset
        GIR_CustomOperandRenderer, /*InsnID*/0, /*OldInsnID*/0, /*OpIdx*/7, /*OperandRenderer*/GIMT_Encode2(GICR_renderExtractCpolSetGLC), // auxiliary
        GIR_MergeMemOperands, /*InsnID*/0, /*NumInsns*/1, /*MergeInsnID's*/0,
        GIR_ConstrainSelectedInstOperands, /*InsnID*/0,
        GIR_EraseFromParent, /*InsnID*/0,
        // GIR_Coverage, 5098,
        GIR_Done,
      // Label 6074: @444578
      GIM_Try, /*On fail goto*//*Label 6075*/ GIMT_Encode4(444684), // Rule ID 5096 //
        GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasUnrestrictedSOffset),
        GIM_CheckHasNoUse, /*MI*/0,
        // MIs[0] offset
        GIM_CheckIsImm, /*MI*/0, /*Op*/6,
        // MIs[0] auxiliary
        GIM_CheckIsImm, /*MI*/0, /*Op*/7,
        // MIs[0] Operand 8
        GIM_CheckIsImm, /*MI*/0, /*Op*/8,
        GIM_CheckComplexPattern, /*MI*/0, /*Op*/5, /*Renderer*/GIMT_Encode2(0), GIMT_Encode2(GICP_gi_buf_soffset),
        // (SIbuffer_atomic_inc:{ *:[i64] } i64:{ *:[i64] }:$vdata_in, v4i32:{ *:[v4i32] }:$rsrc, i32:{ *:[i32] }:$vindex, i32:{ *:[i32] }:$voffset, (BUFSOffset:{ *:[i32] } i32:{ *:[i32] }:$soffset), (timm:{ *:[i32] }):$offset, (timm:{ *:[i32] }):$auxiliary, (timm:{ *:[i1] }))<<P:Predicate_SIbuffer_atomic_inc_noret>>  =>  (BUFFER_ATOMIC_INC_X2_BOTHEN anonymous_15036:{ *:[i64] }:$vdata_in, (REG_SEQUENCE:{ *:[i64] } VReg_64:{ *:[i32] }, VGPR_32:{ *:[i32] }:$vindex, sub0:{ *:[i32] }, VGPR_32:{ *:[i32] }:$voffset, sub1:{ *:[i32] }), SReg_128:{ *:[v4i32] }:$rsrc, SCSrc_b32:{ *:[i32] }:$soffset, (timm:{ *:[i32] }):$offset, (extract_cpol:{ *:[i32] } ?:{ *:[i32] }:$auxiliary))
        GIR_MakeTempReg, /*TempRegID*/0, /*TypeID*/GILLT_s64,
        GIR_BuildMI, /*InsnID*/1, /*Opcode*/GIMT_Encode2(TargetOpcode::REG_SEQUENCE),
        GIR_AddTempRegister, /*InsnID*/1, /*TempRegID*/0, /*TempRegFlags*/GIMT_Encode2(RegState::Define),
        GIR_Copy, /*NewInsnID*/1, /*OldInsnID*/0, /*OpIdx*/3, // vindex
        GIR_AddImm8, /*InsnID*/1, /*SubRegIndex*/3,
        GIR_Copy, /*NewInsnID*/1, /*OldInsnID*/0, /*OpIdx*/4, // voffset
        GIR_AddImm8, /*InsnID*/1, /*SubRegIndex*/11,
        GIR_ConstrainOperandRC, /*InsnID*/1, /*Op*/0, GIMT_Encode2(AMDGPU::VReg_64RegClassID),
        GIR_ConstrainOperandRC, /*InsnID*/1, /*Op*/1, GIMT_Encode2(AMDGPU::VGPR_32RegClassID),
        GIR_ConstrainOperandRC, /*InsnID*/1, /*Op*/3, GIMT_Encode2(AMDGPU::VGPR_32RegClassID),
        GIR_BuildMI, /*InsnID*/0, /*Opcode*/GIMT_Encode2(AMDGPU::BUFFER_ATOMIC_INC_X2_BOTHEN),
        GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/1, // vdata_in
        GIR_AddSimpleTempRegister, /*InsnID*/0, /*TempRegID*/0,
        GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/2, // rsrc
        GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/0, // soffset
        GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/6, // offset
        GIR_CustomOperandRenderer, /*InsnID*/0, /*OldInsnID*/0, /*OpIdx*/7, /*OperandRenderer*/GIMT_Encode2(GICR_renderExtractCPol), // auxiliary
        GIR_MergeMemOperands, /*InsnID*/0, /*NumInsns*/1, /*MergeInsnID's*/0,
        GIR_ConstrainSelectedInstOperands, /*InsnID*/0,
        GIR_EraseFromParent, /*InsnID*/0,
        // GIR_Coverage, 5096,
        GIR_Done,
      // Label 6075: @444684
      GIM_Try, /*On fail goto*//*Label 6076*/ GIMT_Encode4(444787), // Rule ID 5104 //
        GIM_CheckHasNoUse, /*MI*/0,
        // MIs[0] offset
        GIM_CheckIsImm, /*MI*/0, /*Op*/6,
        // MIs[0] auxiliary
        GIM_CheckIsImm, /*MI*/0, /*Op*/7,
        // MIs[0] Operand 8
        GIM_CheckIsImm, /*MI*/0, /*Op*/8,
        GIM_CheckComplexPattern, /*MI*/0, /*Op*/5, /*Renderer*/GIMT_Encode2(0), GIMT_Encode2(GICP_gi_buf_soffset),
        // (SIbuffer_atomic_inc:{ *:[i64] } i64:{ *:[i64] }:$vdata_in, v4i32:{ *:[v4i32] }:$rsrc, i32:{ *:[i32] }:$vindex, i32:{ *:[i32] }:$voffset, (BUFSOffset:{ *:[i32] } i32:{ *:[i32] }:$soffset), (timm:{ *:[i32] }):$offset, (timm:{ *:[i32] }):$auxiliary, (timm:{ *:[i1] }))<<P:Predicate_SIbuffer_atomic_inc_noret>>  =>  (BUFFER_ATOMIC_INC_X2_VBUFFER_BOTHEN anonymous_15036:{ *:[i64] }:$vdata_in, (REG_SEQUENCE:{ *:[i64] } VReg_64:{ *:[i32] }, VGPR_32:{ *:[i32] }:$vindex, sub0:{ *:[i32] }, VGPR_32:{ *:[i32] }:$voffset, sub1:{ *:[i32] }), SReg_128:{ *:[v4i32] }:$rsrc, SCSrc_b32:{ *:[i32] }:$soffset, (timm:{ *:[i32] }):$offset, (extract_cpol:{ *:[i32] } ?:{ *:[i32] }:$auxiliary))
        GIR_MakeTempReg, /*TempRegID*/0, /*TypeID*/GILLT_s64,
        GIR_BuildMI, /*InsnID*/1, /*Opcode*/GIMT_Encode2(TargetOpcode::REG_SEQUENCE),
        GIR_AddTempRegister, /*InsnID*/1, /*TempRegID*/0, /*TempRegFlags*/GIMT_Encode2(RegState::Define),
        GIR_Copy, /*NewInsnID*/1, /*OldInsnID*/0, /*OpIdx*/3, // vindex
        GIR_AddImm8, /*InsnID*/1, /*SubRegIndex*/3,
        GIR_Copy, /*NewInsnID*/1, /*OldInsnID*/0, /*OpIdx*/4, // voffset
        GIR_AddImm8, /*InsnID*/1, /*SubRegIndex*/11,
        GIR_ConstrainOperandRC, /*InsnID*/1, /*Op*/0, GIMT_Encode2(AMDGPU::VReg_64RegClassID),
        GIR_ConstrainOperandRC, /*InsnID*/1, /*Op*/1, GIMT_Encode2(AMDGPU::VGPR_32RegClassID),
        GIR_ConstrainOperandRC, /*InsnID*/1, /*Op*/3, GIMT_Encode2(AMDGPU::VGPR_32RegClassID),
        GIR_BuildMI, /*InsnID*/0, /*Opcode*/GIMT_Encode2(AMDGPU::BUFFER_ATOMIC_INC_X2_VBUFFER_BOTHEN),
        GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/1, // vdata_in
        GIR_AddSimpleTempRegister, /*InsnID*/0, /*TempRegID*/0,
        GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/2, // rsrc
        GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/0, // soffset
        GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/6, // offset
        GIR_CustomOperandRenderer, /*InsnID*/0, /*OldInsnID*/0, /*OpIdx*/7, /*OperandRenderer*/GIMT_Encode2(GICR_renderExtractCPol), // auxiliary
        GIR_MergeMemOperands, /*InsnID*/0, /*NumInsns*/1, /*MergeInsnID's*/0,
        GIR_ConstrainSelectedInstOperands, /*InsnID*/0,
        GIR_EraseFromParent, /*InsnID*/0,
        // GIR_Coverage, 5104,
        GIR_Done,
      // Label 6076: @444787
      GIM_Try, /*On fail goto*//*Label 6077*/ GIMT_Encode4(444900), // Rule ID 5092 //
        GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasUnrestrictedSOffset),
        GIM_CheckRegBankForClass, /*MI*/0, /*Op*/0, /*RC*/GIMT_Encode2(AMDGPU::AV_64RegClassID),
        // MIs[0] offset
        GIM_CheckIsImm, /*MI*/0, /*Op*/6,
        // MIs[0] auxiliary
        GIM_CheckIsImm, /*MI*/0, /*Op*/7,
        // MIs[0] Operand 8
        GIM_CheckIsImm, /*MI*/0, /*Op*/8,
        GIM_CheckComplexPattern, /*MI*/0, /*Op*/5, /*Renderer*/GIMT_Encode2(0), GIMT_Encode2(GICP_gi_buf_soffset),
        // (SIbuffer_atomic_inc:{ *:[i64] } i64:{ *:[i64] }:$vdata_in, v4i32:{ *:[v4i32] }:$rsrc, i32:{ *:[i32] }:$vindex, i32:{ *:[i32] }:$voffset, (BUFSOffset:{ *:[i32] } i32:{ *:[i32] }:$soffset), (timm:{ *:[i32] }):$offset, (timm:{ *:[i32] }):$auxiliary, (timm:{ *:[i1] }))  =>  (BUFFER_ATOMIC_INC_X2_BOTHEN_RTN:{ *:[i64] } anonymous_15036:{ *:[i64] }:$vdata_in, (REG_SEQUENCE:{ *:[i64] } VReg_64:{ *:[i32] }, VGPR_32:{ *:[i32] }:$vindex, sub0:{ *:[i32] }, VGPR_32:{ *:[i32] }:$voffset, sub1:{ *:[i32] }), SReg_128:{ *:[v4i32] }:$rsrc, SCSrc_b32:{ *:[i32] }:$soffset, (timm:{ *:[i32] }):$offset, (extract_cpol_set_glc:{ *:[i32] } ?:{ *:[i32] }:$auxiliary))
        GIR_MakeTempReg, /*TempRegID*/0, /*TypeID*/GILLT_s64,
        GIR_BuildMI, /*InsnID*/1, /*Opcode*/GIMT_Encode2(TargetOpcode::REG_SEQUENCE),
        GIR_AddTempRegister, /*InsnID*/1, /*TempRegID*/0, /*TempRegFlags*/GIMT_Encode2(RegState::Define),
        GIR_Copy, /*NewInsnID*/1, /*OldInsnID*/0, /*OpIdx*/3, // vindex
        GIR_AddImm8, /*InsnID*/1, /*SubRegIndex*/3,
        GIR_Copy, /*NewInsnID*/1, /*OldInsnID*/0, /*OpIdx*/4, // voffset
        GIR_AddImm8, /*InsnID*/1, /*SubRegIndex*/11,
        GIR_ConstrainOperandRC, /*InsnID*/1, /*Op*/0, GIMT_Encode2(AMDGPU::VReg_64RegClassID),
        GIR_ConstrainOperandRC, /*InsnID*/1, /*Op*/1, GIMT_Encode2(AMDGPU::VGPR_32RegClassID),
        GIR_ConstrainOperandRC, /*InsnID*/1, /*Op*/3, GIMT_Encode2(AMDGPU::VGPR_32RegClassID),
        GIR_BuildMI, /*InsnID*/0, /*Opcode*/GIMT_Encode2(AMDGPU::BUFFER_ATOMIC_INC_X2_BOTHEN_RTN),
        GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/0, // DstI[vdata]
        GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/1, // vdata_in
        GIR_AddSimpleTempRegister, /*InsnID*/0, /*TempRegID*/0,
        GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/2, // rsrc
        GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/0, // soffset
        GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/6, // offset
        GIR_CustomOperandRenderer, /*InsnID*/0, /*OldInsnID*/0, /*OpIdx*/7, /*OperandRenderer*/GIMT_Encode2(GICR_renderExtractCpolSetGLC), // auxiliary
        GIR_MergeMemOperands, /*InsnID*/0, /*NumInsns*/1, /*MergeInsnID's*/0,
        GIR_ConstrainSelectedInstOperands, /*InsnID*/0,
        GIR_EraseFromParent, /*InsnID*/0,
        // GIR_Coverage, 5092,
        GIR_Done,
      // Label 6077: @444900
      GIM_Try, /*On fail goto*//*Label 6078*/ GIMT_Encode4(445010), // Rule ID 5100 //
        GIM_CheckRegBankForClass, /*MI*/0, /*Op*/0, /*RC*/GIMT_Encode2(AMDGPU::AV_64RegClassID),
        // MIs[0] offset
        GIM_CheckIsImm, /*MI*/0, /*Op*/6,
        // MIs[0] auxiliary
        GIM_CheckIsImm, /*MI*/0, /*Op*/7,
        // MIs[0] Operand 8
        GIM_CheckIsImm, /*MI*/0, /*Op*/8,
        GIM_CheckComplexPattern, /*MI*/0, /*Op*/5, /*Renderer*/GIMT_Encode2(0), GIMT_Encode2(GICP_gi_buf_soffset),
        // (SIbuffer_atomic_inc:{ *:[i64] } i64:{ *:[i64] }:$vdata_in, v4i32:{ *:[v4i32] }:$rsrc, i32:{ *:[i32] }:$vindex, i32:{ *:[i32] }:$voffset, (BUFSOffset:{ *:[i32] } i32:{ *:[i32] }:$soffset), (timm:{ *:[i32] }):$offset, (timm:{ *:[i32] }):$auxiliary, (timm:{ *:[i1] }))  =>  (BUFFER_ATOMIC_INC_X2_VBUFFER_BOTHEN_RTN:{ *:[i64] } anonymous_15036:{ *:[i64] }:$vdata_in, (REG_SEQUENCE:{ *:[i64] } VReg_64:{ *:[i32] }, VGPR_32:{ *:[i32] }:$vindex, sub0:{ *:[i32] }, VGPR_32:{ *:[i32] }:$voffset, sub1:{ *:[i32] }), SReg_128:{ *:[v4i32] }:$rsrc, SCSrc_b32:{ *:[i32] }:$soffset, (timm:{ *:[i32] }):$offset, (extract_cpol_set_glc:{ *:[i32] } ?:{ *:[i32] }:$auxiliary))
        GIR_MakeTempReg, /*TempRegID*/0, /*TypeID*/GILLT_s64,
        GIR_BuildMI, /*InsnID*/1, /*Opcode*/GIMT_Encode2(TargetOpcode::REG_SEQUENCE),
        GIR_AddTempRegister, /*InsnID*/1, /*TempRegID*/0, /*TempRegFlags*/GIMT_Encode2(RegState::Define),
        GIR_Copy, /*NewInsnID*/1, /*OldInsnID*/0, /*OpIdx*/3, // vindex
        GIR_AddImm8, /*InsnID*/1, /*SubRegIndex*/3,
        GIR_Copy, /*NewInsnID*/1, /*OldInsnID*/0, /*OpIdx*/4, // voffset
        GIR_AddImm8, /*InsnID*/1, /*SubRegIndex*/11,
        GIR_ConstrainOperandRC, /*InsnID*/1, /*Op*/0, GIMT_Encode2(AMDGPU::VReg_64RegClassID),
        GIR_ConstrainOperandRC, /*InsnID*/1, /*Op*/1, GIMT_Encode2(AMDGPU::VGPR_32RegClassID),
        GIR_ConstrainOperandRC, /*InsnID*/1, /*Op*/3, GIMT_Encode2(AMDGPU::VGPR_32RegClassID),
        GIR_BuildMI, /*InsnID*/0, /*Opcode*/GIMT_Encode2(AMDGPU::BUFFER_ATOMIC_INC_X2_VBUFFER_BOTHEN_RTN),
        GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/0, // DstI[vdata]
        GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/1, // vdata_in
        GIR_AddSimpleTempRegister, /*InsnID*/0, /*TempRegID*/0,
        GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/2, // rsrc
        GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/0, // soffset
        GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/6, // offset
        GIR_CustomOperandRenderer, /*InsnID*/0, /*OldInsnID*/0, /*OpIdx*/7, /*OperandRenderer*/GIMT_Encode2(GICR_renderExtractCpolSetGLC), // auxiliary
        GIR_MergeMemOperands, /*InsnID*/0, /*NumInsns*/1, /*MergeInsnID's*/0,
        GIR_ConstrainSelectedInstOperands, /*InsnID*/0,
        GIR_EraseFromParent, /*InsnID*/0,
        // GIR_Coverage, 5100,
        GIR_Done,
      // Label 6078: @445010
      GIM_Reject,
    // Label 6062: @445011
    GIM_Reject,
    // Label 6044: @445012
    GIM_Reject,
    // Label 116: @445013
    GIM_SwitchType, /*MI*/0, /*Op*/0, /*[*/GIMT_Encode2(9), GIMT_Encode2(11), /*)*//*default:*//*Label 6081*/ GIMT_Encode4(447806),
    /*GILLT_s32*//*Label 6079*/ GIMT_Encode4(445032),
    /*GILLT_s64*//*Label 6080*/ GIMT_Encode4(446419),
    // Label 6079: @445032
    GIM_Try, /*On fail goto*//*Label 6082*/ GIMT_Encode4(446418),
      GIM_CheckType, /*MI*/0, /*Op*/1, /*Type*/GILLT_s32,
      GIM_CheckType, /*MI*/0, /*Op*/2, /*Type*/GILLT_v4s32,
      GIM_CheckType, /*MI*/0, /*Op*/3, /*Type*/GILLT_s32,
      GIM_CheckType, /*MI*/0, /*Op*/4, /*Type*/GILLT_s32,
      GIM_CheckType, /*MI*/0, /*Op*/5, /*Type*/GILLT_s32,
      GIM_Try, /*On fail goto*//*Label 6083*/ GIMT_Encode4(445135), // Rule ID 4861 //
        GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasUnrestrictedSOffset),
        GIM_CheckHasNoUse, /*MI*/0,
        GIM_CheckConstantInt8, /*MI*/0, /*Op*/3, 0,
        GIM_CheckConstantInt8, /*MI*/0, /*Op*/4, 0,
        // MIs[0] offset
        GIM_CheckIsImm, /*MI*/0, /*Op*/6,
        // MIs[0] auxiliary
        GIM_CheckIsImm, /*MI*/0, /*Op*/7,
        // MIs[0] Operand 8
        GIM_CheckLiteralInt, /*MI*/0, /*Op*/8, GIMT_Encode8(0),
        GIM_CheckComplexPattern, /*MI*/0, /*Op*/5, /*Renderer*/GIMT_Encode2(0), GIMT_Encode2(GICP_gi_buf_soffset),
        // (SIbuffer_atomic_or:{ *:[i32] } i32:{ *:[i32] }:$vdata_in, v4i32:{ *:[v4i32] }:$rsrc, 0:{ *:[i32] }, 0:{ *:[i32] }, (BUFSOffset:{ *:[i32] } i32:{ *:[i32] }:$soffset), (timm:{ *:[i32] }):$offset, (timm:{ *:[i32] }):$auxiliary, 0:{ *:[i1] })<<P:Predicate_SIbuffer_atomic_or_noret>>  =>  (BUFFER_ATOMIC_OR_OFFSET anonymous_15037:{ *:[i32] }:$vdata_in, SReg_128:{ *:[v4i32] }:$rsrc, SCSrc_b32:{ *:[i32] }:$soffset, (timm:{ *:[i32] }):$offset, (extract_cpol:{ *:[i32] } ?:{ *:[i32] }:$auxiliary))
        GIR_BuildMI, /*InsnID*/0, /*Opcode*/GIMT_Encode2(AMDGPU::BUFFER_ATOMIC_OR_OFFSET),
        GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/1, // vdata_in
        GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/2, // rsrc
        GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/0, // soffset
        GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/6, // offset
        GIR_CustomOperandRenderer, /*InsnID*/0, /*OldInsnID*/0, /*OpIdx*/7, /*OperandRenderer*/GIMT_Encode2(GICR_renderExtractCPol), // auxiliary
        GIR_MergeMemOperands, /*InsnID*/0, /*NumInsns*/1, /*MergeInsnID's*/0,
        GIR_ConstrainSelectedInstOperands, /*InsnID*/0,
        GIR_EraseFromParent, /*InsnID*/0,
        // GIR_Coverage, 4861,
        GIR_Done,
      // Label 6083: @445135
      GIM_Try, /*On fail goto*//*Label 6084*/ GIMT_Encode4(445210), // Rule ID 4869 //
        GIM_CheckHasNoUse, /*MI*/0,
        GIM_CheckConstantInt8, /*MI*/0, /*Op*/3, 0,
        GIM_CheckConstantInt8, /*MI*/0, /*Op*/4, 0,
        // MIs[0] offset
        GIM_CheckIsImm, /*MI*/0, /*Op*/6,
        // MIs[0] auxiliary
        GIM_CheckIsImm, /*MI*/0, /*Op*/7,
        // MIs[0] Operand 8
        GIM_CheckLiteralInt, /*MI*/0, /*Op*/8, GIMT_Encode8(0),
        GIM_CheckComplexPattern, /*MI*/0, /*Op*/5, /*Renderer*/GIMT_Encode2(0), GIMT_Encode2(GICP_gi_buf_soffset),
        // (SIbuffer_atomic_or:{ *:[i32] } i32:{ *:[i32] }:$vdata_in, v4i32:{ *:[v4i32] }:$rsrc, 0:{ *:[i32] }, 0:{ *:[i32] }, (BUFSOffset:{ *:[i32] } i32:{ *:[i32] }:$soffset), (timm:{ *:[i32] }):$offset, (timm:{ *:[i32] }):$auxiliary, 0:{ *:[i1] })<<P:Predicate_SIbuffer_atomic_or_noret>>  =>  (BUFFER_ATOMIC_OR_VBUFFER_OFFSET anonymous_15037:{ *:[i32] }:$vdata_in, SReg_128:{ *:[v4i32] }:$rsrc, SCSrc_b32:{ *:[i32] }:$soffset, (timm:{ *:[i32] }):$offset, (extract_cpol:{ *:[i32] } ?:{ *:[i32] }:$auxiliary))
        GIR_BuildMI, /*InsnID*/0, /*Opcode*/GIMT_Encode2(AMDGPU::BUFFER_ATOMIC_OR_VBUFFER_OFFSET),
        GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/1, // vdata_in
        GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/2, // rsrc
        GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/0, // soffset
        GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/6, // offset
        GIR_CustomOperandRenderer, /*InsnID*/0, /*OldInsnID*/0, /*OpIdx*/7, /*OperandRenderer*/GIMT_Encode2(GICR_renderExtractCPol), // auxiliary
        GIR_MergeMemOperands, /*InsnID*/0, /*NumInsns*/1, /*MergeInsnID's*/0,
        GIR_ConstrainSelectedInstOperands, /*InsnID*/0,
        GIR_EraseFromParent, /*InsnID*/0,
        // GIR_Coverage, 4869,
        GIR_Done,
      // Label 6084: @445210
      GIM_Try, /*On fail goto*//*Label 6085*/ GIMT_Encode4(445295), // Rule ID 4857 //
        GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasUnrestrictedSOffset),
        GIM_CheckRegBankForClass, /*MI*/0, /*Op*/0, /*RC*/GIMT_Encode2(AMDGPU::AV_32RegClassID),
        GIM_CheckConstantInt8, /*MI*/0, /*Op*/3, 0,
        GIM_CheckConstantInt8, /*MI*/0, /*Op*/4, 0,
        // MIs[0] offset
        GIM_CheckIsImm, /*MI*/0, /*Op*/6,
        // MIs[0] auxiliary
        GIM_CheckIsImm, /*MI*/0, /*Op*/7,
        // MIs[0] Operand 8
        GIM_CheckLiteralInt, /*MI*/0, /*Op*/8, GIMT_Encode8(0),
        GIM_CheckComplexPattern, /*MI*/0, /*Op*/5, /*Renderer*/GIMT_Encode2(0), GIMT_Encode2(GICP_gi_buf_soffset),
        // (SIbuffer_atomic_or:{ *:[i32] } i32:{ *:[i32] }:$vdata_in, v4i32:{ *:[v4i32] }:$rsrc, 0:{ *:[i32] }, 0:{ *:[i32] }, (BUFSOffset:{ *:[i32] } i32:{ *:[i32] }:$soffset), (timm:{ *:[i32] }):$offset, (timm:{ *:[i32] }):$auxiliary, 0:{ *:[i1] })  =>  (BUFFER_ATOMIC_OR_OFFSET_RTN:{ *:[i32] } anonymous_15037:{ *:[i32] }:$vdata_in, SReg_128:{ *:[v4i32] }:$rsrc, SCSrc_b32:{ *:[i32] }:$soffset, (timm:{ *:[i32] }):$offset, (extract_cpol_set_glc:{ *:[i32] } ?:{ *:[i32] }:$auxiliary))
        GIR_BuildMI, /*InsnID*/0, /*Opcode*/GIMT_Encode2(AMDGPU::BUFFER_ATOMIC_OR_OFFSET_RTN),
        GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/0, // DstI[vdata]
        GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/1, // vdata_in
        GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/2, // rsrc
        GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/0, // soffset
        GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/6, // offset
        GIR_CustomOperandRenderer, /*InsnID*/0, /*OldInsnID*/0, /*OpIdx*/7, /*OperandRenderer*/GIMT_Encode2(GICR_renderExtractCpolSetGLC), // auxiliary
        GIR_MergeMemOperands, /*InsnID*/0, /*NumInsns*/1, /*MergeInsnID's*/0,
        GIR_ConstrainSelectedInstOperands, /*InsnID*/0,
        GIR_EraseFromParent, /*InsnID*/0,
        // GIR_Coverage, 4857,
        GIR_Done,
      // Label 6085: @445295
      GIM_Try, /*On fail goto*//*Label 6086*/ GIMT_Encode4(445377), // Rule ID 4865 //
        GIM_CheckRegBankForClass, /*MI*/0, /*Op*/0, /*RC*/GIMT_Encode2(AMDGPU::AV_32RegClassID),
        GIM_CheckConstantInt8, /*MI*/0, /*Op*/3, 0,
        GIM_CheckConstantInt8, /*MI*/0, /*Op*/4, 0,
        // MIs[0] offset
        GIM_CheckIsImm, /*MI*/0, /*Op*/6,
        // MIs[0] auxiliary
        GIM_CheckIsImm, /*MI*/0, /*Op*/7,
        // MIs[0] Operand 8
        GIM_CheckLiteralInt, /*MI*/0, /*Op*/8, GIMT_Encode8(0),
        GIM_CheckComplexPattern, /*MI*/0, /*Op*/5, /*Renderer*/GIMT_Encode2(0), GIMT_Encode2(GICP_gi_buf_soffset),
        // (SIbuffer_atomic_or:{ *:[i32] } i32:{ *:[i32] }:$vdata_in, v4i32:{ *:[v4i32] }:$rsrc, 0:{ *:[i32] }, 0:{ *:[i32] }, (BUFSOffset:{ *:[i32] } i32:{ *:[i32] }:$soffset), (timm:{ *:[i32] }):$offset, (timm:{ *:[i32] }):$auxiliary, 0:{ *:[i1] })  =>  (BUFFER_ATOMIC_OR_VBUFFER_OFFSET_RTN:{ *:[i32] } anonymous_15037:{ *:[i32] }:$vdata_in, SReg_128:{ *:[v4i32] }:$rsrc, SCSrc_b32:{ *:[i32] }:$soffset, (timm:{ *:[i32] }):$offset, (extract_cpol_set_glc:{ *:[i32] } ?:{ *:[i32] }:$auxiliary))
        GIR_BuildMI, /*InsnID*/0, /*Opcode*/GIMT_Encode2(AMDGPU::BUFFER_ATOMIC_OR_VBUFFER_OFFSET_RTN),
        GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/0, // DstI[vdata]
        GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/1, // vdata_in
        GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/2, // rsrc
        GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/0, // soffset
        GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/6, // offset
        GIR_CustomOperandRenderer, /*InsnID*/0, /*OldInsnID*/0, /*OpIdx*/7, /*OperandRenderer*/GIMT_Encode2(GICR_renderExtractCpolSetGLC), // auxiliary
        GIR_MergeMemOperands, /*InsnID*/0, /*NumInsns*/1, /*MergeInsnID's*/0,
        GIR_ConstrainSelectedInstOperands, /*InsnID*/0,
        GIR_EraseFromParent, /*InsnID*/0,
        // GIR_Coverage, 4865,
        GIR_Done,
      // Label 6086: @445377
      GIM_Try, /*On fail goto*//*Label 6087*/ GIMT_Encode4(445455), // Rule ID 4863 //
        GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasUnrestrictedSOffset),
        GIM_CheckHasNoUse, /*MI*/0,
        GIM_CheckConstantInt8, /*MI*/0, /*Op*/3, 0,
        // MIs[0] offset
        GIM_CheckIsImm, /*MI*/0, /*Op*/6,
        // MIs[0] auxiliary
        GIM_CheckIsImm, /*MI*/0, /*Op*/7,
        // MIs[0] Operand 8
        GIM_CheckLiteralInt, /*MI*/0, /*Op*/8, GIMT_Encode8(0),
        GIM_CheckComplexPattern, /*MI*/0, /*Op*/5, /*Renderer*/GIMT_Encode2(0), GIMT_Encode2(GICP_gi_buf_soffset),
        // (SIbuffer_atomic_or:{ *:[i32] } i32:{ *:[i32] }:$vdata_in, v4i32:{ *:[v4i32] }:$rsrc, 0:{ *:[i32] }, i32:{ *:[i32] }:$voffset, (BUFSOffset:{ *:[i32] } i32:{ *:[i32] }:$soffset), (timm:{ *:[i32] }):$offset, (timm:{ *:[i32] }):$auxiliary, 0:{ *:[i1] })<<P:Predicate_SIbuffer_atomic_or_noret>>  =>  (BUFFER_ATOMIC_OR_OFFEN anonymous_15037:{ *:[i32] }:$vdata_in, VGPR_32:{ *:[i32] }:$voffset, SReg_128:{ *:[v4i32] }:$rsrc, SCSrc_b32:{ *:[i32] }:$soffset, (timm:{ *:[i32] }):$offset, (extract_cpol:{ *:[i32] } ?:{ *:[i32] }:$auxiliary))
        GIR_BuildMI, /*InsnID*/0, /*Opcode*/GIMT_Encode2(AMDGPU::BUFFER_ATOMIC_OR_OFFEN),
        GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/1, // vdata_in
        GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/4, // voffset
        GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/2, // rsrc
        GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/0, // soffset
        GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/6, // offset
        GIR_CustomOperandRenderer, /*InsnID*/0, /*OldInsnID*/0, /*OpIdx*/7, /*OperandRenderer*/GIMT_Encode2(GICR_renderExtractCPol), // auxiliary
        GIR_MergeMemOperands, /*InsnID*/0, /*NumInsns*/1, /*MergeInsnID's*/0,
        GIR_ConstrainSelectedInstOperands, /*InsnID*/0,
        GIR_EraseFromParent, /*InsnID*/0,
        // GIR_Coverage, 4863,
        GIR_Done,
      // Label 6087: @445455
      GIM_Try, /*On fail goto*//*Label 6088*/ GIMT_Encode4(445530), // Rule ID 4871 //
        GIM_CheckHasNoUse, /*MI*/0,
        GIM_CheckConstantInt8, /*MI*/0, /*Op*/3, 0,
        // MIs[0] offset
        GIM_CheckIsImm, /*MI*/0, /*Op*/6,
        // MIs[0] auxiliary
        GIM_CheckIsImm, /*MI*/0, /*Op*/7,
        // MIs[0] Operand 8
        GIM_CheckLiteralInt, /*MI*/0, /*Op*/8, GIMT_Encode8(0),
        GIM_CheckComplexPattern, /*MI*/0, /*Op*/5, /*Renderer*/GIMT_Encode2(0), GIMT_Encode2(GICP_gi_buf_soffset),
        // (SIbuffer_atomic_or:{ *:[i32] } i32:{ *:[i32] }:$vdata_in, v4i32:{ *:[v4i32] }:$rsrc, 0:{ *:[i32] }, i32:{ *:[i32] }:$voffset, (BUFSOffset:{ *:[i32] } i32:{ *:[i32] }:$soffset), (timm:{ *:[i32] }):$offset, (timm:{ *:[i32] }):$auxiliary, 0:{ *:[i1] })<<P:Predicate_SIbuffer_atomic_or_noret>>  =>  (BUFFER_ATOMIC_OR_VBUFFER_OFFEN anonymous_15037:{ *:[i32] }:$vdata_in, VGPR_32:{ *:[i32] }:$voffset, SReg_128:{ *:[v4i32] }:$rsrc, SCSrc_b32:{ *:[i32] }:$soffset, (timm:{ *:[i32] }):$offset, (extract_cpol:{ *:[i32] } ?:{ *:[i32] }:$auxiliary))
        GIR_BuildMI, /*InsnID*/0, /*Opcode*/GIMT_Encode2(AMDGPU::BUFFER_ATOMIC_OR_VBUFFER_OFFEN),
        GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/1, // vdata_in
        GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/4, // voffset
        GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/2, // rsrc
        GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/0, // soffset
        GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/6, // offset
        GIR_CustomOperandRenderer, /*InsnID*/0, /*OldInsnID*/0, /*OpIdx*/7, /*OperandRenderer*/GIMT_Encode2(GICR_renderExtractCPol), // auxiliary
        GIR_MergeMemOperands, /*InsnID*/0, /*NumInsns*/1, /*MergeInsnID's*/0,
        GIR_ConstrainSelectedInstOperands, /*InsnID*/0,
        GIR_EraseFromParent, /*InsnID*/0,
        // GIR_Coverage, 4871,
        GIR_Done,
      // Label 6088: @445530
      GIM_Try, /*On fail goto*//*Label 6089*/ GIMT_Encode4(445615), // Rule ID 4859 //
        GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasUnrestrictedSOffset),
        GIM_CheckRegBankForClass, /*MI*/0, /*Op*/0, /*RC*/GIMT_Encode2(AMDGPU::AV_32RegClassID),
        GIM_CheckConstantInt8, /*MI*/0, /*Op*/3, 0,
        // MIs[0] offset
        GIM_CheckIsImm, /*MI*/0, /*Op*/6,
        // MIs[0] auxiliary
        GIM_CheckIsImm, /*MI*/0, /*Op*/7,
        // MIs[0] Operand 8
        GIM_CheckLiteralInt, /*MI*/0, /*Op*/8, GIMT_Encode8(0),
        GIM_CheckComplexPattern, /*MI*/0, /*Op*/5, /*Renderer*/GIMT_Encode2(0), GIMT_Encode2(GICP_gi_buf_soffset),
        // (SIbuffer_atomic_or:{ *:[i32] } i32:{ *:[i32] }:$vdata_in, v4i32:{ *:[v4i32] }:$rsrc, 0:{ *:[i32] }, i32:{ *:[i32] }:$voffset, (BUFSOffset:{ *:[i32] } i32:{ *:[i32] }:$soffset), (timm:{ *:[i32] }):$offset, (timm:{ *:[i32] }):$auxiliary, 0:{ *:[i1] })  =>  (BUFFER_ATOMIC_OR_OFFEN_RTN:{ *:[i32] } anonymous_15037:{ *:[i32] }:$vdata_in, VGPR_32:{ *:[i32] }:$voffset, SReg_128:{ *:[v4i32] }:$rsrc, SCSrc_b32:{ *:[i32] }:$soffset, (timm:{ *:[i32] }):$offset, (extract_cpol_set_glc:{ *:[i32] } ?:{ *:[i32] }:$auxiliary))
        GIR_BuildMI, /*InsnID*/0, /*Opcode*/GIMT_Encode2(AMDGPU::BUFFER_ATOMIC_OR_OFFEN_RTN),
        GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/0, // DstI[vdata]
        GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/1, // vdata_in
        GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/4, // voffset
        GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/2, // rsrc
        GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/0, // soffset
        GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/6, // offset
        GIR_CustomOperandRenderer, /*InsnID*/0, /*OldInsnID*/0, /*OpIdx*/7, /*OperandRenderer*/GIMT_Encode2(GICR_renderExtractCpolSetGLC), // auxiliary
        GIR_MergeMemOperands, /*InsnID*/0, /*NumInsns*/1, /*MergeInsnID's*/0,
        GIR_ConstrainSelectedInstOperands, /*InsnID*/0,
        GIR_EraseFromParent, /*InsnID*/0,
        // GIR_Coverage, 4859,
        GIR_Done,
      // Label 6089: @445615
      GIM_Try, /*On fail goto*//*Label 6090*/ GIMT_Encode4(445697), // Rule ID 4867 //
        GIM_CheckRegBankForClass, /*MI*/0, /*Op*/0, /*RC*/GIMT_Encode2(AMDGPU::AV_32RegClassID),
        GIM_CheckConstantInt8, /*MI*/0, /*Op*/3, 0,
        // MIs[0] offset
        GIM_CheckIsImm, /*MI*/0, /*Op*/6,
        // MIs[0] auxiliary
        GIM_CheckIsImm, /*MI*/0, /*Op*/7,
        // MIs[0] Operand 8
        GIM_CheckLiteralInt, /*MI*/0, /*Op*/8, GIMT_Encode8(0),
        GIM_CheckComplexPattern, /*MI*/0, /*Op*/5, /*Renderer*/GIMT_Encode2(0), GIMT_Encode2(GICP_gi_buf_soffset),
        // (SIbuffer_atomic_or:{ *:[i32] } i32:{ *:[i32] }:$vdata_in, v4i32:{ *:[v4i32] }:$rsrc, 0:{ *:[i32] }, i32:{ *:[i32] }:$voffset, (BUFSOffset:{ *:[i32] } i32:{ *:[i32] }:$soffset), (timm:{ *:[i32] }):$offset, (timm:{ *:[i32] }):$auxiliary, 0:{ *:[i1] })  =>  (BUFFER_ATOMIC_OR_VBUFFER_OFFEN_RTN:{ *:[i32] } anonymous_15037:{ *:[i32] }:$vdata_in, VGPR_32:{ *:[i32] }:$voffset, SReg_128:{ *:[v4i32] }:$rsrc, SCSrc_b32:{ *:[i32] }:$soffset, (timm:{ *:[i32] }):$offset, (extract_cpol_set_glc:{ *:[i32] } ?:{ *:[i32] }:$auxiliary))
        GIR_BuildMI, /*InsnID*/0, /*Opcode*/GIMT_Encode2(AMDGPU::BUFFER_ATOMIC_OR_VBUFFER_OFFEN_RTN),
        GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/0, // DstI[vdata]
        GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/1, // vdata_in
        GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/4, // voffset
        GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/2, // rsrc
        GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/0, // soffset
        GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/6, // offset
        GIR_CustomOperandRenderer, /*InsnID*/0, /*OldInsnID*/0, /*OpIdx*/7, /*OperandRenderer*/GIMT_Encode2(GICR_renderExtractCpolSetGLC), // auxiliary
        GIR_MergeMemOperands, /*InsnID*/0, /*NumInsns*/1, /*MergeInsnID's*/0,
        GIR_ConstrainSelectedInstOperands, /*InsnID*/0,
        GIR_EraseFromParent, /*InsnID*/0,
        // GIR_Coverage, 4867,
        GIR_Done,
      // Label 6090: @445697
      GIM_Try, /*On fail goto*//*Label 6091*/ GIMT_Encode4(445767), // Rule ID 4862 //
        GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasUnrestrictedSOffset),
        GIM_CheckHasNoUse, /*MI*/0,
        GIM_CheckConstantInt8, /*MI*/0, /*Op*/4, 0,
        // MIs[0] offset
        GIM_CheckIsImm, /*MI*/0, /*Op*/6,
        // MIs[0] auxiliary
        GIM_CheckIsImm, /*MI*/0, /*Op*/7,
        // MIs[0] Operand 8
        GIM_CheckIsImm, /*MI*/0, /*Op*/8,
        GIM_CheckComplexPattern, /*MI*/0, /*Op*/5, /*Renderer*/GIMT_Encode2(0), GIMT_Encode2(GICP_gi_buf_soffset),
        // (SIbuffer_atomic_or:{ *:[i32] } i32:{ *:[i32] }:$vdata_in, v4i32:{ *:[v4i32] }:$rsrc, i32:{ *:[i32] }:$vindex, 0:{ *:[i32] }, (BUFSOffset:{ *:[i32] } i32:{ *:[i32] }:$soffset), (timm:{ *:[i32] }):$offset, (timm:{ *:[i32] }):$auxiliary, (timm:{ *:[i1] }))<<P:Predicate_SIbuffer_atomic_or_noret>>  =>  (BUFFER_ATOMIC_OR_IDXEN anonymous_15037:{ *:[i32] }:$vdata_in, VGPR_32:{ *:[i32] }:$vindex, SReg_128:{ *:[v4i32] }:$rsrc, SCSrc_b32:{ *:[i32] }:$soffset, (timm:{ *:[i32] }):$offset, (extract_cpol:{ *:[i32] } ?:{ *:[i32] }:$auxiliary))
        GIR_BuildMI, /*InsnID*/0, /*Opcode*/GIMT_Encode2(AMDGPU::BUFFER_ATOMIC_OR_IDXEN),
        GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/1, // vdata_in
        GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/3, // vindex
        GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/2, // rsrc
        GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/0, // soffset
        GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/6, // offset
        GIR_CustomOperandRenderer, /*InsnID*/0, /*OldInsnID*/0, /*OpIdx*/7, /*OperandRenderer*/GIMT_Encode2(GICR_renderExtractCPol), // auxiliary
        GIR_MergeMemOperands, /*InsnID*/0, /*NumInsns*/1, /*MergeInsnID's*/0,
        GIR_ConstrainSelectedInstOperands, /*InsnID*/0,
        GIR_EraseFromParent, /*InsnID*/0,
        // GIR_Coverage, 4862,
        GIR_Done,
      // Label 6091: @445767
      GIM_Try, /*On fail goto*//*Label 6092*/ GIMT_Encode4(445834), // Rule ID 4870 //
        GIM_CheckHasNoUse, /*MI*/0,
        GIM_CheckConstantInt8, /*MI*/0, /*Op*/4, 0,
        // MIs[0] offset
        GIM_CheckIsImm, /*MI*/0, /*Op*/6,
        // MIs[0] auxiliary
        GIM_CheckIsImm, /*MI*/0, /*Op*/7,
        // MIs[0] Operand 8
        GIM_CheckIsImm, /*MI*/0, /*Op*/8,
        GIM_CheckComplexPattern, /*MI*/0, /*Op*/5, /*Renderer*/GIMT_Encode2(0), GIMT_Encode2(GICP_gi_buf_soffset),
        // (SIbuffer_atomic_or:{ *:[i32] } i32:{ *:[i32] }:$vdata_in, v4i32:{ *:[v4i32] }:$rsrc, i32:{ *:[i32] }:$vindex, 0:{ *:[i32] }, (BUFSOffset:{ *:[i32] } i32:{ *:[i32] }:$soffset), (timm:{ *:[i32] }):$offset, (timm:{ *:[i32] }):$auxiliary, (timm:{ *:[i1] }))<<P:Predicate_SIbuffer_atomic_or_noret>>  =>  (BUFFER_ATOMIC_OR_VBUFFER_IDXEN anonymous_15037:{ *:[i32] }:$vdata_in, VGPR_32:{ *:[i32] }:$vindex, SReg_128:{ *:[v4i32] }:$rsrc, SCSrc_b32:{ *:[i32] }:$soffset, (timm:{ *:[i32] }):$offset, (extract_cpol:{ *:[i32] } ?:{ *:[i32] }:$auxiliary))
        GIR_BuildMI, /*InsnID*/0, /*Opcode*/GIMT_Encode2(AMDGPU::BUFFER_ATOMIC_OR_VBUFFER_IDXEN),
        GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/1, // vdata_in
        GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/3, // vindex
        GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/2, // rsrc
        GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/0, // soffset
        GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/6, // offset
        GIR_CustomOperandRenderer, /*InsnID*/0, /*OldInsnID*/0, /*OpIdx*/7, /*OperandRenderer*/GIMT_Encode2(GICR_renderExtractCPol), // auxiliary
        GIR_MergeMemOperands, /*InsnID*/0, /*NumInsns*/1, /*MergeInsnID's*/0,
        GIR_ConstrainSelectedInstOperands, /*InsnID*/0,
        GIR_EraseFromParent, /*InsnID*/0,
        // GIR_Coverage, 4870,
        GIR_Done,
      // Label 6092: @445834
      GIM_Try, /*On fail goto*//*Label 6093*/ GIMT_Encode4(445911), // Rule ID 4858 //
        GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasUnrestrictedSOffset),
        GIM_CheckRegBankForClass, /*MI*/0, /*Op*/0, /*RC*/GIMT_Encode2(AMDGPU::AV_32RegClassID),
        GIM_CheckConstantInt8, /*MI*/0, /*Op*/4, 0,
        // MIs[0] offset
        GIM_CheckIsImm, /*MI*/0, /*Op*/6,
        // MIs[0] auxiliary
        GIM_CheckIsImm, /*MI*/0, /*Op*/7,
        // MIs[0] Operand 8
        GIM_CheckIsImm, /*MI*/0, /*Op*/8,
        GIM_CheckComplexPattern, /*MI*/0, /*Op*/5, /*Renderer*/GIMT_Encode2(0), GIMT_Encode2(GICP_gi_buf_soffset),
        // (SIbuffer_atomic_or:{ *:[i32] } i32:{ *:[i32] }:$vdata_in, v4i32:{ *:[v4i32] }:$rsrc, i32:{ *:[i32] }:$vindex, 0:{ *:[i32] }, (BUFSOffset:{ *:[i32] } i32:{ *:[i32] }:$soffset), (timm:{ *:[i32] }):$offset, (timm:{ *:[i32] }):$auxiliary, (timm:{ *:[i1] }))  =>  (BUFFER_ATOMIC_OR_IDXEN_RTN:{ *:[i32] } anonymous_15037:{ *:[i32] }:$vdata_in, VGPR_32:{ *:[i32] }:$vindex, SReg_128:{ *:[v4i32] }:$rsrc, SCSrc_b32:{ *:[i32] }:$soffset, (timm:{ *:[i32] }):$offset, (extract_cpol_set_glc:{ *:[i32] } ?:{ *:[i32] }:$auxiliary))
        GIR_BuildMI, /*InsnID*/0, /*Opcode*/GIMT_Encode2(AMDGPU::BUFFER_ATOMIC_OR_IDXEN_RTN),
        GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/0, // DstI[vdata]
        GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/1, // vdata_in
        GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/3, // vindex
        GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/2, // rsrc
        GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/0, // soffset
        GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/6, // offset
        GIR_CustomOperandRenderer, /*InsnID*/0, /*OldInsnID*/0, /*OpIdx*/7, /*OperandRenderer*/GIMT_Encode2(GICR_renderExtractCpolSetGLC), // auxiliary
        GIR_MergeMemOperands, /*InsnID*/0, /*NumInsns*/1, /*MergeInsnID's*/0,
        GIR_ConstrainSelectedInstOperands, /*InsnID*/0,
        GIR_EraseFromParent, /*InsnID*/0,
        // GIR_Coverage, 4858,
        GIR_Done,
      // Label 6093: @445911
      GIM_Try, /*On fail goto*//*Label 6094*/ GIMT_Encode4(445985), // Rule ID 4866 //
        GIM_CheckRegBankForClass, /*MI*/0, /*Op*/0, /*RC*/GIMT_Encode2(AMDGPU::AV_32RegClassID),
        GIM_CheckConstantInt8, /*MI*/0, /*Op*/4, 0,
        // MIs[0] offset
        GIM_CheckIsImm, /*MI*/0, /*Op*/6,
        // MIs[0] auxiliary
        GIM_CheckIsImm, /*MI*/0, /*Op*/7,
        // MIs[0] Operand 8
        GIM_CheckIsImm, /*MI*/0, /*Op*/8,
        GIM_CheckComplexPattern, /*MI*/0, /*Op*/5, /*Renderer*/GIMT_Encode2(0), GIMT_Encode2(GICP_gi_buf_soffset),
        // (SIbuffer_atomic_or:{ *:[i32] } i32:{ *:[i32] }:$vdata_in, v4i32:{ *:[v4i32] }:$rsrc, i32:{ *:[i32] }:$vindex, 0:{ *:[i32] }, (BUFSOffset:{ *:[i32] } i32:{ *:[i32] }:$soffset), (timm:{ *:[i32] }):$offset, (timm:{ *:[i32] }):$auxiliary, (timm:{ *:[i1] }))  =>  (BUFFER_ATOMIC_OR_VBUFFER_IDXEN_RTN:{ *:[i32] } anonymous_15037:{ *:[i32] }:$vdata_in, VGPR_32:{ *:[i32] }:$vindex, SReg_128:{ *:[v4i32] }:$rsrc, SCSrc_b32:{ *:[i32] }:$soffset, (timm:{ *:[i32] }):$offset, (extract_cpol_set_glc:{ *:[i32] } ?:{ *:[i32] }:$auxiliary))
        GIR_BuildMI, /*InsnID*/0, /*Opcode*/GIMT_Encode2(AMDGPU::BUFFER_ATOMIC_OR_VBUFFER_IDXEN_RTN),
        GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/0, // DstI[vdata]
        GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/1, // vdata_in
        GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/3, // vindex
        GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/2, // rsrc
        GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/0, // soffset
        GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/6, // offset
        GIR_CustomOperandRenderer, /*InsnID*/0, /*OldInsnID*/0, /*OpIdx*/7, /*OperandRenderer*/GIMT_Encode2(GICR_renderExtractCpolSetGLC), // auxiliary
        GIR_MergeMemOperands, /*InsnID*/0, /*NumInsns*/1, /*MergeInsnID's*/0,
        GIR_ConstrainSelectedInstOperands, /*InsnID*/0,
        GIR_EraseFromParent, /*InsnID*/0,
        // GIR_Coverage, 4866,
        GIR_Done,
      // Label 6094: @445985
      GIM_Try, /*On fail goto*//*Label 6095*/ GIMT_Encode4(446091), // Rule ID 4864 //
        GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasUnrestrictedSOffset),
        GIM_CheckHasNoUse, /*MI*/0,
        // MIs[0] offset
        GIM_CheckIsImm, /*MI*/0, /*Op*/6,
        // MIs[0] auxiliary
        GIM_CheckIsImm, /*MI*/0, /*Op*/7,
        // MIs[0] Operand 8
        GIM_CheckIsImm, /*MI*/0, /*Op*/8,
        GIM_CheckComplexPattern, /*MI*/0, /*Op*/5, /*Renderer*/GIMT_Encode2(0), GIMT_Encode2(GICP_gi_buf_soffset),
        // (SIbuffer_atomic_or:{ *:[i32] } i32:{ *:[i32] }:$vdata_in, v4i32:{ *:[v4i32] }:$rsrc, i32:{ *:[i32] }:$vindex, i32:{ *:[i32] }:$voffset, (BUFSOffset:{ *:[i32] } i32:{ *:[i32] }:$soffset), (timm:{ *:[i32] }):$offset, (timm:{ *:[i32] }):$auxiliary, (timm:{ *:[i1] }))<<P:Predicate_SIbuffer_atomic_or_noret>>  =>  (BUFFER_ATOMIC_OR_BOTHEN anonymous_15037:{ *:[i32] }:$vdata_in, (REG_SEQUENCE:{ *:[i64] } VReg_64:{ *:[i32] }, VGPR_32:{ *:[i32] }:$vindex, sub0:{ *:[i32] }, VGPR_32:{ *:[i32] }:$voffset, sub1:{ *:[i32] }), SReg_128:{ *:[v4i32] }:$rsrc, SCSrc_b32:{ *:[i32] }:$soffset, (timm:{ *:[i32] }):$offset, (extract_cpol:{ *:[i32] } ?:{ *:[i32] }:$auxiliary))
        GIR_MakeTempReg, /*TempRegID*/0, /*TypeID*/GILLT_s64,
        GIR_BuildMI, /*InsnID*/1, /*Opcode*/GIMT_Encode2(TargetOpcode::REG_SEQUENCE),
        GIR_AddTempRegister, /*InsnID*/1, /*TempRegID*/0, /*TempRegFlags*/GIMT_Encode2(RegState::Define),
        GIR_Copy, /*NewInsnID*/1, /*OldInsnID*/0, /*OpIdx*/3, // vindex
        GIR_AddImm8, /*InsnID*/1, /*SubRegIndex*/3,
        GIR_Copy, /*NewInsnID*/1, /*OldInsnID*/0, /*OpIdx*/4, // voffset
        GIR_AddImm8, /*InsnID*/1, /*SubRegIndex*/11,
        GIR_ConstrainOperandRC, /*InsnID*/1, /*Op*/0, GIMT_Encode2(AMDGPU::VReg_64RegClassID),
        GIR_ConstrainOperandRC, /*InsnID*/1, /*Op*/1, GIMT_Encode2(AMDGPU::VGPR_32RegClassID),
        GIR_ConstrainOperandRC, /*InsnID*/1, /*Op*/3, GIMT_Encode2(AMDGPU::VGPR_32RegClassID),
        GIR_BuildMI, /*InsnID*/0, /*Opcode*/GIMT_Encode2(AMDGPU::BUFFER_ATOMIC_OR_BOTHEN),
        GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/1, // vdata_in
        GIR_AddSimpleTempRegister, /*InsnID*/0, /*TempRegID*/0,
        GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/2, // rsrc
        GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/0, // soffset
        GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/6, // offset
        GIR_CustomOperandRenderer, /*InsnID*/0, /*OldInsnID*/0, /*OpIdx*/7, /*OperandRenderer*/GIMT_Encode2(GICR_renderExtractCPol), // auxiliary
        GIR_MergeMemOperands, /*InsnID*/0, /*NumInsns*/1, /*MergeInsnID's*/0,
        GIR_ConstrainSelectedInstOperands, /*InsnID*/0,
        GIR_EraseFromParent, /*InsnID*/0,
        // GIR_Coverage, 4864,
        GIR_Done,
      // Label 6095: @446091
      GIM_Try, /*On fail goto*//*Label 6096*/ GIMT_Encode4(446194), // Rule ID 4872 //
        GIM_CheckHasNoUse, /*MI*/0,
        // MIs[0] offset
        GIM_CheckIsImm, /*MI*/0, /*Op*/6,
        // MIs[0] auxiliary
        GIM_CheckIsImm, /*MI*/0, /*Op*/7,
        // MIs[0] Operand 8
        GIM_CheckIsImm, /*MI*/0, /*Op*/8,
        GIM_CheckComplexPattern, /*MI*/0, /*Op*/5, /*Renderer*/GIMT_Encode2(0), GIMT_Encode2(GICP_gi_buf_soffset),
        // (SIbuffer_atomic_or:{ *:[i32] } i32:{ *:[i32] }:$vdata_in, v4i32:{ *:[v4i32] }:$rsrc, i32:{ *:[i32] }:$vindex, i32:{ *:[i32] }:$voffset, (BUFSOffset:{ *:[i32] } i32:{ *:[i32] }:$soffset), (timm:{ *:[i32] }):$offset, (timm:{ *:[i32] }):$auxiliary, (timm:{ *:[i1] }))<<P:Predicate_SIbuffer_atomic_or_noret>>  =>  (BUFFER_ATOMIC_OR_VBUFFER_BOTHEN anonymous_15037:{ *:[i32] }:$vdata_in, (REG_SEQUENCE:{ *:[i64] } VReg_64:{ *:[i32] }, VGPR_32:{ *:[i32] }:$vindex, sub0:{ *:[i32] }, VGPR_32:{ *:[i32] }:$voffset, sub1:{ *:[i32] }), SReg_128:{ *:[v4i32] }:$rsrc, SCSrc_b32:{ *:[i32] }:$soffset, (timm:{ *:[i32] }):$offset, (extract_cpol:{ *:[i32] } ?:{ *:[i32] }:$auxiliary))
        GIR_MakeTempReg, /*TempRegID*/0, /*TypeID*/GILLT_s64,
        GIR_BuildMI, /*InsnID*/1, /*Opcode*/GIMT_Encode2(TargetOpcode::REG_SEQUENCE),
        GIR_AddTempRegister, /*InsnID*/1, /*TempRegID*/0, /*TempRegFlags*/GIMT_Encode2(RegState::Define),
        GIR_Copy, /*NewInsnID*/1, /*OldInsnID*/0, /*OpIdx*/3, // vindex
        GIR_AddImm8, /*InsnID*/1, /*SubRegIndex*/3,
        GIR_Copy, /*NewInsnID*/1, /*OldInsnID*/0, /*OpIdx*/4, // voffset
        GIR_AddImm8, /*InsnID*/1, /*SubRegIndex*/11,
        GIR_ConstrainOperandRC, /*InsnID*/1, /*Op*/0, GIMT_Encode2(AMDGPU::VReg_64RegClassID),
        GIR_ConstrainOperandRC, /*InsnID*/1, /*Op*/1, GIMT_Encode2(AMDGPU::VGPR_32RegClassID),
        GIR_ConstrainOperandRC, /*InsnID*/1, /*Op*/3, GIMT_Encode2(AMDGPU::VGPR_32RegClassID),
        GIR_BuildMI, /*InsnID*/0, /*Opcode*/GIMT_Encode2(AMDGPU::BUFFER_ATOMIC_OR_VBUFFER_BOTHEN),
        GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/1, // vdata_in
        GIR_AddSimpleTempRegister, /*InsnID*/0, /*TempRegID*/0,
        GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/2, // rsrc
        GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/0, // soffset
        GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/6, // offset
        GIR_CustomOperandRenderer, /*InsnID*/0, /*OldInsnID*/0, /*OpIdx*/7, /*OperandRenderer*/GIMT_Encode2(GICR_renderExtractCPol), // auxiliary
        GIR_MergeMemOperands, /*InsnID*/0, /*NumInsns*/1, /*MergeInsnID's*/0,
        GIR_ConstrainSelectedInstOperands, /*InsnID*/0,
        GIR_EraseFromParent, /*InsnID*/0,
        // GIR_Coverage, 4872,
        GIR_Done,
      // Label 6096: @446194
      GIM_Try, /*On fail goto*//*Label 6097*/ GIMT_Encode4(446307), // Rule ID 4860 //
        GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasUnrestrictedSOffset),
        GIM_CheckRegBankForClass, /*MI*/0, /*Op*/0, /*RC*/GIMT_Encode2(AMDGPU::AV_32RegClassID),
        // MIs[0] offset
        GIM_CheckIsImm, /*MI*/0, /*Op*/6,
        // MIs[0] auxiliary
        GIM_CheckIsImm, /*MI*/0, /*Op*/7,
        // MIs[0] Operand 8
        GIM_CheckIsImm, /*MI*/0, /*Op*/8,
        GIM_CheckComplexPattern, /*MI*/0, /*Op*/5, /*Renderer*/GIMT_Encode2(0), GIMT_Encode2(GICP_gi_buf_soffset),
        // (SIbuffer_atomic_or:{ *:[i32] } i32:{ *:[i32] }:$vdata_in, v4i32:{ *:[v4i32] }:$rsrc, i32:{ *:[i32] }:$vindex, i32:{ *:[i32] }:$voffset, (BUFSOffset:{ *:[i32] } i32:{ *:[i32] }:$soffset), (timm:{ *:[i32] }):$offset, (timm:{ *:[i32] }):$auxiliary, (timm:{ *:[i1] }))  =>  (BUFFER_ATOMIC_OR_BOTHEN_RTN:{ *:[i32] } anonymous_15037:{ *:[i32] }:$vdata_in, (REG_SEQUENCE:{ *:[i64] } VReg_64:{ *:[i32] }, VGPR_32:{ *:[i32] }:$vindex, sub0:{ *:[i32] }, VGPR_32:{ *:[i32] }:$voffset, sub1:{ *:[i32] }), SReg_128:{ *:[v4i32] }:$rsrc, SCSrc_b32:{ *:[i32] }:$soffset, (timm:{ *:[i32] }):$offset, (extract_cpol_set_glc:{ *:[i32] } ?:{ *:[i32] }:$auxiliary))
        GIR_MakeTempReg, /*TempRegID*/0, /*TypeID*/GILLT_s64,
        GIR_BuildMI, /*InsnID*/1, /*Opcode*/GIMT_Encode2(TargetOpcode::REG_SEQUENCE),
        GIR_AddTempRegister, /*InsnID*/1, /*TempRegID*/0, /*TempRegFlags*/GIMT_Encode2(RegState::Define),
        GIR_Copy, /*NewInsnID*/1, /*OldInsnID*/0, /*OpIdx*/3, // vindex
        GIR_AddImm8, /*InsnID*/1, /*SubRegIndex*/3,
        GIR_Copy, /*NewInsnID*/1, /*OldInsnID*/0, /*OpIdx*/4, // voffset
        GIR_AddImm8, /*InsnID*/1, /*SubRegIndex*/11,
        GIR_ConstrainOperandRC, /*InsnID*/1, /*Op*/0, GIMT_Encode2(AMDGPU::VReg_64RegClassID),
        GIR_ConstrainOperandRC, /*InsnID*/1, /*Op*/1, GIMT_Encode2(AMDGPU::VGPR_32RegClassID),
        GIR_ConstrainOperandRC, /*InsnID*/1, /*Op*/3, GIMT_Encode2(AMDGPU::VGPR_32RegClassID),
        GIR_BuildMI, /*InsnID*/0, /*Opcode*/GIMT_Encode2(AMDGPU::BUFFER_ATOMIC_OR_BOTHEN_RTN),
        GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/0, // DstI[vdata]
        GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/1, // vdata_in
        GIR_AddSimpleTempRegister, /*InsnID*/0, /*TempRegID*/0,
        GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/2, // rsrc
        GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/0, // soffset
        GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/6, // offset
        GIR_CustomOperandRenderer, /*InsnID*/0, /*OldInsnID*/0, /*OpIdx*/7, /*OperandRenderer*/GIMT_Encode2(GICR_renderExtractCpolSetGLC), // auxiliary
        GIR_MergeMemOperands, /*InsnID*/0, /*NumInsns*/1, /*MergeInsnID's*/0,
        GIR_ConstrainSelectedInstOperands, /*InsnID*/0,
        GIR_EraseFromParent, /*InsnID*/0,
        // GIR_Coverage, 4860,
        GIR_Done,
      // Label 6097: @446307
      GIM_Try, /*On fail goto*//*Label 6098*/ GIMT_Encode4(446417), // Rule ID 4868 //
        GIM_CheckRegBankForClass, /*MI*/0, /*Op*/0, /*RC*/GIMT_Encode2(AMDGPU::AV_32RegClassID),
        // MIs[0] offset
        GIM_CheckIsImm, /*MI*/0, /*Op*/6,
        // MIs[0] auxiliary
        GIM_CheckIsImm, /*MI*/0, /*Op*/7,
        // MIs[0] Operand 8
        GIM_CheckIsImm, /*MI*/0, /*Op*/8,
        GIM_CheckComplexPattern, /*MI*/0, /*Op*/5, /*Renderer*/GIMT_Encode2(0), GIMT_Encode2(GICP_gi_buf_soffset),
        // (SIbuffer_atomic_or:{ *:[i32] } i32:{ *:[i32] }:$vdata_in, v4i32:{ *:[v4i32] }:$rsrc, i32:{ *:[i32] }:$vindex, i32:{ *:[i32] }:$voffset, (BUFSOffset:{ *:[i32] } i32:{ *:[i32] }:$soffset), (timm:{ *:[i32] }):$offset, (timm:{ *:[i32] }):$auxiliary, (timm:{ *:[i1] }))  =>  (BUFFER_ATOMIC_OR_VBUFFER_BOTHEN_RTN:{ *:[i32] } anonymous_15037:{ *:[i32] }:$vdata_in, (REG_SEQUENCE:{ *:[i64] } VReg_64:{ *:[i32] }, VGPR_32:{ *:[i32] }:$vindex, sub0:{ *:[i32] }, VGPR_32:{ *:[i32] }:$voffset, sub1:{ *:[i32] }), SReg_128:{ *:[v4i32] }:$rsrc, SCSrc_b32:{ *:[i32] }:$soffset, (timm:{ *:[i32] }):$offset, (extract_cpol_set_glc:{ *:[i32] } ?:{ *:[i32] }:$auxiliary))
        GIR_MakeTempReg, /*TempRegID*/0, /*TypeID*/GILLT_s64,
        GIR_BuildMI, /*InsnID*/1, /*Opcode*/GIMT_Encode2(TargetOpcode::REG_SEQUENCE),
        GIR_AddTempRegister, /*InsnID*/1, /*TempRegID*/0, /*TempRegFlags*/GIMT_Encode2(RegState::Define),
        GIR_Copy, /*NewInsnID*/1, /*OldInsnID*/0, /*OpIdx*/3, // vindex
        GIR_AddImm8, /*InsnID*/1, /*SubRegIndex*/3,
        GIR_Copy, /*NewInsnID*/1, /*OldInsnID*/0, /*OpIdx*/4, // voffset
        GIR_AddImm8, /*InsnID*/1, /*SubRegIndex*/11,
        GIR_ConstrainOperandRC, /*InsnID*/1, /*Op*/0, GIMT_Encode2(AMDGPU::VReg_64RegClassID),
        GIR_ConstrainOperandRC, /*InsnID*/1, /*Op*/1, GIMT_Encode2(AMDGPU::VGPR_32RegClassID),
        GIR_ConstrainOperandRC, /*InsnID*/1, /*Op*/3, GIMT_Encode2(AMDGPU::VGPR_32RegClassID),
        GIR_BuildMI, /*InsnID*/0, /*Opcode*/GIMT_Encode2(AMDGPU::BUFFER_ATOMIC_OR_VBUFFER_BOTHEN_RTN),
        GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/0, // DstI[vdata]
        GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/1, // vdata_in
        GIR_AddSimpleTempRegister, /*InsnID*/0, /*TempRegID*/0,
        GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/2, // rsrc
        GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/0, // soffset
        GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/6, // offset
        GIR_CustomOperandRenderer, /*InsnID*/0, /*OldInsnID*/0, /*OpIdx*/7, /*OperandRenderer*/GIMT_Encode2(GICR_renderExtractCpolSetGLC), // auxiliary
        GIR_MergeMemOperands, /*InsnID*/0, /*NumInsns*/1, /*MergeInsnID's*/0,
        GIR_ConstrainSelectedInstOperands, /*InsnID*/0,
        GIR_EraseFromParent, /*InsnID*/0,
        // GIR_Coverage, 4868,
        GIR_Done,
      // Label 6098: @446417
      GIM_Reject,
    // Label 6082: @446418
    GIM_Reject,
    // Label 6080: @446419
    GIM_Try, /*On fail goto*//*Label 6099*/ GIMT_Encode4(447805),
      GIM_CheckType, /*MI*/0, /*Op*/1, /*Type*/GILLT_s64,
      GIM_CheckType, /*MI*/0, /*Op*/2, /*Type*/GILLT_v4s32,
      GIM_CheckType, /*MI*/0, /*Op*/3, /*Type*/GILLT_s32,
      GIM_CheckType, /*MI*/0, /*Op*/4, /*Type*/GILLT_s32,
      GIM_CheckType, /*MI*/0, /*Op*/5, /*Type*/GILLT_s32,
      GIM_Try, /*On fail goto*//*Label 6100*/ GIMT_Encode4(446522), // Rule ID 5061 //
        GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasUnrestrictedSOffset),
        GIM_CheckHasNoUse, /*MI*/0,
        GIM_CheckConstantInt8, /*MI*/0, /*Op*/3, 0,
        GIM_CheckConstantInt8, /*MI*/0, /*Op*/4, 0,
        // MIs[0] offset
        GIM_CheckIsImm, /*MI*/0, /*Op*/6,
        // MIs[0] auxiliary
        GIM_CheckIsImm, /*MI*/0, /*Op*/7,
        // MIs[0] Operand 8
        GIM_CheckLiteralInt, /*MI*/0, /*Op*/8, GIMT_Encode8(0),
        GIM_CheckComplexPattern, /*MI*/0, /*Op*/5, /*Renderer*/GIMT_Encode2(0), GIMT_Encode2(GICP_gi_buf_soffset),
        // (SIbuffer_atomic_or:{ *:[i64] } i64:{ *:[i64] }:$vdata_in, v4i32:{ *:[v4i32] }:$rsrc, 0:{ *:[i32] }, 0:{ *:[i32] }, (BUFSOffset:{ *:[i32] } i32:{ *:[i32] }:$soffset), (timm:{ *:[i32] }):$offset, (timm:{ *:[i32] }):$auxiliary, 0:{ *:[i1] })<<P:Predicate_SIbuffer_atomic_or_noret>>  =>  (BUFFER_ATOMIC_OR_X2_OFFSET anonymous_15036:{ *:[i64] }:$vdata_in, SReg_128:{ *:[v4i32] }:$rsrc, SCSrc_b32:{ *:[i32] }:$soffset, (timm:{ *:[i32] }):$offset, (extract_cpol:{ *:[i32] } ?:{ *:[i32] }:$auxiliary))
        GIR_BuildMI, /*InsnID*/0, /*Opcode*/GIMT_Encode2(AMDGPU::BUFFER_ATOMIC_OR_X2_OFFSET),
        GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/1, // vdata_in
        GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/2, // rsrc
        GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/0, // soffset
        GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/6, // offset
        GIR_CustomOperandRenderer, /*InsnID*/0, /*OldInsnID*/0, /*OpIdx*/7, /*OperandRenderer*/GIMT_Encode2(GICR_renderExtractCPol), // auxiliary
        GIR_MergeMemOperands, /*InsnID*/0, /*NumInsns*/1, /*MergeInsnID's*/0,
        GIR_ConstrainSelectedInstOperands, /*InsnID*/0,
        GIR_EraseFromParent, /*InsnID*/0,
        // GIR_Coverage, 5061,
        GIR_Done,
      // Label 6100: @446522
      GIM_Try, /*On fail goto*//*Label 6101*/ GIMT_Encode4(446597), // Rule ID 5069 //
        GIM_CheckHasNoUse, /*MI*/0,
        GIM_CheckConstantInt8, /*MI*/0, /*Op*/3, 0,
        GIM_CheckConstantInt8, /*MI*/0, /*Op*/4, 0,
        // MIs[0] offset
        GIM_CheckIsImm, /*MI*/0, /*Op*/6,
        // MIs[0] auxiliary
        GIM_CheckIsImm, /*MI*/0, /*Op*/7,
        // MIs[0] Operand 8
        GIM_CheckLiteralInt, /*MI*/0, /*Op*/8, GIMT_Encode8(0),
        GIM_CheckComplexPattern, /*MI*/0, /*Op*/5, /*Renderer*/GIMT_Encode2(0), GIMT_Encode2(GICP_gi_buf_soffset),
        // (SIbuffer_atomic_or:{ *:[i64] } i64:{ *:[i64] }:$vdata_in, v4i32:{ *:[v4i32] }:$rsrc, 0:{ *:[i32] }, 0:{ *:[i32] }, (BUFSOffset:{ *:[i32] } i32:{ *:[i32] }:$soffset), (timm:{ *:[i32] }):$offset, (timm:{ *:[i32] }):$auxiliary, 0:{ *:[i1] })<<P:Predicate_SIbuffer_atomic_or_noret>>  =>  (BUFFER_ATOMIC_OR_X2_VBUFFER_OFFSET anonymous_15036:{ *:[i64] }:$vdata_in, SReg_128:{ *:[v4i32] }:$rsrc, SCSrc_b32:{ *:[i32] }:$soffset, (timm:{ *:[i32] }):$offset, (extract_cpol:{ *:[i32] } ?:{ *:[i32] }:$auxiliary))
        GIR_BuildMI, /*InsnID*/0, /*Opcode*/GIMT_Encode2(AMDGPU::BUFFER_ATOMIC_OR_X2_VBUFFER_OFFSET),
        GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/1, // vdata_in
        GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/2, // rsrc
        GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/0, // soffset
        GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/6, // offset
        GIR_CustomOperandRenderer, /*InsnID*/0, /*OldInsnID*/0, /*OpIdx*/7, /*OperandRenderer*/GIMT_Encode2(GICR_renderExtractCPol), // auxiliary
        GIR_MergeMemOperands, /*InsnID*/0, /*NumInsns*/1, /*MergeInsnID's*/0,
        GIR_ConstrainSelectedInstOperands, /*InsnID*/0,
        GIR_EraseFromParent, /*InsnID*/0,
        // GIR_Coverage, 5069,
        GIR_Done,
      // Label 6101: @446597
      GIM_Try, /*On fail goto*//*Label 6102*/ GIMT_Encode4(446682), // Rule ID 5057 //
        GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasUnrestrictedSOffset),
        GIM_CheckRegBankForClass, /*MI*/0, /*Op*/0, /*RC*/GIMT_Encode2(AMDGPU::AV_64RegClassID),
        GIM_CheckConstantInt8, /*MI*/0, /*Op*/3, 0,
        GIM_CheckConstantInt8, /*MI*/0, /*Op*/4, 0,
        // MIs[0] offset
        GIM_CheckIsImm, /*MI*/0, /*Op*/6,
        // MIs[0] auxiliary
        GIM_CheckIsImm, /*MI*/0, /*Op*/7,
        // MIs[0] Operand 8
        GIM_CheckLiteralInt, /*MI*/0, /*Op*/8, GIMT_Encode8(0),
        GIM_CheckComplexPattern, /*MI*/0, /*Op*/5, /*Renderer*/GIMT_Encode2(0), GIMT_Encode2(GICP_gi_buf_soffset),
        // (SIbuffer_atomic_or:{ *:[i64] } i64:{ *:[i64] }:$vdata_in, v4i32:{ *:[v4i32] }:$rsrc, 0:{ *:[i32] }, 0:{ *:[i32] }, (BUFSOffset:{ *:[i32] } i32:{ *:[i32] }:$soffset), (timm:{ *:[i32] }):$offset, (timm:{ *:[i32] }):$auxiliary, 0:{ *:[i1] })  =>  (BUFFER_ATOMIC_OR_X2_OFFSET_RTN:{ *:[i64] } anonymous_15036:{ *:[i64] }:$vdata_in, SReg_128:{ *:[v4i32] }:$rsrc, SCSrc_b32:{ *:[i32] }:$soffset, (timm:{ *:[i32] }):$offset, (extract_cpol_set_glc:{ *:[i32] } ?:{ *:[i32] }:$auxiliary))
        GIR_BuildMI, /*InsnID*/0, /*Opcode*/GIMT_Encode2(AMDGPU::BUFFER_ATOMIC_OR_X2_OFFSET_RTN),
        GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/0, // DstI[vdata]
        GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/1, // vdata_in
        GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/2, // rsrc
        GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/0, // soffset
        GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/6, // offset
        GIR_CustomOperandRenderer, /*InsnID*/0, /*OldInsnID*/0, /*OpIdx*/7, /*OperandRenderer*/GIMT_Encode2(GICR_renderExtractCpolSetGLC), // auxiliary
        GIR_MergeMemOperands, /*InsnID*/0, /*NumInsns*/1, /*MergeInsnID's*/0,
        GIR_ConstrainSelectedInstOperands, /*InsnID*/0,
        GIR_EraseFromParent, /*InsnID*/0,
        // GIR_Coverage, 5057,
        GIR_Done,
      // Label 6102: @446682
      GIM_Try, /*On fail goto*//*Label 6103*/ GIMT_Encode4(446764), // Rule ID 5065 //
        GIM_CheckRegBankForClass, /*MI*/0, /*Op*/0, /*RC*/GIMT_Encode2(AMDGPU::AV_64RegClassID),
        GIM_CheckConstantInt8, /*MI*/0, /*Op*/3, 0,
        GIM_CheckConstantInt8, /*MI*/0, /*Op*/4, 0,
        // MIs[0] offset
        GIM_CheckIsImm, /*MI*/0, /*Op*/6,
        // MIs[0] auxiliary
        GIM_CheckIsImm, /*MI*/0, /*Op*/7,
        // MIs[0] Operand 8
        GIM_CheckLiteralInt, /*MI*/0, /*Op*/8, GIMT_Encode8(0),
        GIM_CheckComplexPattern, /*MI*/0, /*Op*/5, /*Renderer*/GIMT_Encode2(0), GIMT_Encode2(GICP_gi_buf_soffset),
        // (SIbuffer_atomic_or:{ *:[i64] } i64:{ *:[i64] }:$vdata_in, v4i32:{ *:[v4i32] }:$rsrc, 0:{ *:[i32] }, 0:{ *:[i32] }, (BUFSOffset:{ *:[i32] } i32:{ *:[i32] }:$soffset), (timm:{ *:[i32] }):$offset, (timm:{ *:[i32] }):$auxiliary, 0:{ *:[i1] })  =>  (BUFFER_ATOMIC_OR_X2_VBUFFER_OFFSET_RTN:{ *:[i64] } anonymous_15036:{ *:[i64] }:$vdata_in, SReg_128:{ *:[v4i32] }:$rsrc, SCSrc_b32:{ *:[i32] }:$soffset, (timm:{ *:[i32] }):$offset, (extract_cpol_set_glc:{ *:[i32] } ?:{ *:[i32] }:$auxiliary))
        GIR_BuildMI, /*InsnID*/0, /*Opcode*/GIMT_Encode2(AMDGPU::BUFFER_ATOMIC_OR_X2_VBUFFER_OFFSET_RTN),
        GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/0, // DstI[vdata]
        GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/1, // vdata_in
        GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/2, // rsrc
        GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/0, // soffset
        GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/6, // offset
        GIR_CustomOperandRenderer, /*InsnID*/0, /*OldInsnID*/0, /*OpIdx*/7, /*OperandRenderer*/GIMT_Encode2(GICR_renderExtractCpolSetGLC), // auxiliary
        GIR_MergeMemOperands, /*InsnID*/0, /*NumInsns*/1, /*MergeInsnID's*/0,
        GIR_ConstrainSelectedInstOperands, /*InsnID*/0,
        GIR_EraseFromParent, /*InsnID*/0,
        // GIR_Coverage, 5065,
        GIR_Done,
      // Label 6103: @446764
      GIM_Try, /*On fail goto*//*Label 6104*/ GIMT_Encode4(446842), // Rule ID 5063 //
        GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasUnrestrictedSOffset),
        GIM_CheckHasNoUse, /*MI*/0,
        GIM_CheckConstantInt8, /*MI*/0, /*Op*/3, 0,
        // MIs[0] offset
        GIM_CheckIsImm, /*MI*/0, /*Op*/6,
        // MIs[0] auxiliary
        GIM_CheckIsImm, /*MI*/0, /*Op*/7,
        // MIs[0] Operand 8
        GIM_CheckLiteralInt, /*MI*/0, /*Op*/8, GIMT_Encode8(0),
        GIM_CheckComplexPattern, /*MI*/0, /*Op*/5, /*Renderer*/GIMT_Encode2(0), GIMT_Encode2(GICP_gi_buf_soffset),
        // (SIbuffer_atomic_or:{ *:[i64] } i64:{ *:[i64] }:$vdata_in, v4i32:{ *:[v4i32] }:$rsrc, 0:{ *:[i32] }, i32:{ *:[i32] }:$voffset, (BUFSOffset:{ *:[i32] } i32:{ *:[i32] }:$soffset), (timm:{ *:[i32] }):$offset, (timm:{ *:[i32] }):$auxiliary, 0:{ *:[i1] })<<P:Predicate_SIbuffer_atomic_or_noret>>  =>  (BUFFER_ATOMIC_OR_X2_OFFEN anonymous_15036:{ *:[i64] }:$vdata_in, VGPR_32:{ *:[i32] }:$voffset, SReg_128:{ *:[v4i32] }:$rsrc, SCSrc_b32:{ *:[i32] }:$soffset, (timm:{ *:[i32] }):$offset, (extract_cpol:{ *:[i32] } ?:{ *:[i32] }:$auxiliary))
        GIR_BuildMI, /*InsnID*/0, /*Opcode*/GIMT_Encode2(AMDGPU::BUFFER_ATOMIC_OR_X2_OFFEN),
        GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/1, // vdata_in
        GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/4, // voffset
        GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/2, // rsrc
        GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/0, // soffset
        GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/6, // offset
        GIR_CustomOperandRenderer, /*InsnID*/0, /*OldInsnID*/0, /*OpIdx*/7, /*OperandRenderer*/GIMT_Encode2(GICR_renderExtractCPol), // auxiliary
        GIR_MergeMemOperands, /*InsnID*/0, /*NumInsns*/1, /*MergeInsnID's*/0,
        GIR_ConstrainSelectedInstOperands, /*InsnID*/0,
        GIR_EraseFromParent, /*InsnID*/0,
        // GIR_Coverage, 5063,
        GIR_Done,
      // Label 6104: @446842
      GIM_Try, /*On fail goto*//*Label 6105*/ GIMT_Encode4(446917), // Rule ID 5071 //
        GIM_CheckHasNoUse, /*MI*/0,
        GIM_CheckConstantInt8, /*MI*/0, /*Op*/3, 0,
        // MIs[0] offset
        GIM_CheckIsImm, /*MI*/0, /*Op*/6,
        // MIs[0] auxiliary
        GIM_CheckIsImm, /*MI*/0, /*Op*/7,
        // MIs[0] Operand 8
        GIM_CheckLiteralInt, /*MI*/0, /*Op*/8, GIMT_Encode8(0),
        GIM_CheckComplexPattern, /*MI*/0, /*Op*/5, /*Renderer*/GIMT_Encode2(0), GIMT_Encode2(GICP_gi_buf_soffset),
        // (SIbuffer_atomic_or:{ *:[i64] } i64:{ *:[i64] }:$vdata_in, v4i32:{ *:[v4i32] }:$rsrc, 0:{ *:[i32] }, i32:{ *:[i32] }:$voffset, (BUFSOffset:{ *:[i32] } i32:{ *:[i32] }:$soffset), (timm:{ *:[i32] }):$offset, (timm:{ *:[i32] }):$auxiliary, 0:{ *:[i1] })<<P:Predicate_SIbuffer_atomic_or_noret>>  =>  (BUFFER_ATOMIC_OR_X2_VBUFFER_OFFEN anonymous_15036:{ *:[i64] }:$vdata_in, VGPR_32:{ *:[i32] }:$voffset, SReg_128:{ *:[v4i32] }:$rsrc, SCSrc_b32:{ *:[i32] }:$soffset, (timm:{ *:[i32] }):$offset, (extract_cpol:{ *:[i32] } ?:{ *:[i32] }:$auxiliary))
        GIR_BuildMI, /*InsnID*/0, /*Opcode*/GIMT_Encode2(AMDGPU::BUFFER_ATOMIC_OR_X2_VBUFFER_OFFEN),
        GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/1, // vdata_in
        GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/4, // voffset
        GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/2, // rsrc
        GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/0, // soffset
        GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/6, // offset
        GIR_CustomOperandRenderer, /*InsnID*/0, /*OldInsnID*/0, /*OpIdx*/7, /*OperandRenderer*/GIMT_Encode2(GICR_renderExtractCPol), // auxiliary
        GIR_MergeMemOperands, /*InsnID*/0, /*NumInsns*/1, /*MergeInsnID's*/0,
        GIR_ConstrainSelectedInstOperands, /*InsnID*/0,
        GIR_EraseFromParent, /*InsnID*/0,
        // GIR_Coverage, 5071,
        GIR_Done,
      // Label 6105: @446917
      GIM_Try, /*On fail goto*//*Label 6106*/ GIMT_Encode4(447002), // Rule ID 5059 //
        GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasUnrestrictedSOffset),
        GIM_CheckRegBankForClass, /*MI*/0, /*Op*/0, /*RC*/GIMT_Encode2(AMDGPU::AV_64RegClassID),
        GIM_CheckConstantInt8, /*MI*/0, /*Op*/3, 0,
        // MIs[0] offset
        GIM_CheckIsImm, /*MI*/0, /*Op*/6,
        // MIs[0] auxiliary
        GIM_CheckIsImm, /*MI*/0, /*Op*/7,
        // MIs[0] Operand 8
        GIM_CheckLiteralInt, /*MI*/0, /*Op*/8, GIMT_Encode8(0),
        GIM_CheckComplexPattern, /*MI*/0, /*Op*/5, /*Renderer*/GIMT_Encode2(0), GIMT_Encode2(GICP_gi_buf_soffset),
        // (SIbuffer_atomic_or:{ *:[i64] } i64:{ *:[i64] }:$vdata_in, v4i32:{ *:[v4i32] }:$rsrc, 0:{ *:[i32] }, i32:{ *:[i32] }:$voffset, (BUFSOffset:{ *:[i32] } i32:{ *:[i32] }:$soffset), (timm:{ *:[i32] }):$offset, (timm:{ *:[i32] }):$auxiliary, 0:{ *:[i1] })  =>  (BUFFER_ATOMIC_OR_X2_OFFEN_RTN:{ *:[i64] } anonymous_15036:{ *:[i64] }:$vdata_in, VGPR_32:{ *:[i32] }:$voffset, SReg_128:{ *:[v4i32] }:$rsrc, SCSrc_b32:{ *:[i32] }:$soffset, (timm:{ *:[i32] }):$offset, (extract_cpol_set_glc:{ *:[i32] } ?:{ *:[i32] }:$auxiliary))
        GIR_BuildMI, /*InsnID*/0, /*Opcode*/GIMT_Encode2(AMDGPU::BUFFER_ATOMIC_OR_X2_OFFEN_RTN),
        GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/0, // DstI[vdata]
        GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/1, // vdata_in
        GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/4, // voffset
        GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/2, // rsrc
        GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/0, // soffset
        GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/6, // offset
        GIR_CustomOperandRenderer, /*InsnID*/0, /*OldInsnID*/0, /*OpIdx*/7, /*OperandRenderer*/GIMT_Encode2(GICR_renderExtractCpolSetGLC), // auxiliary
        GIR_MergeMemOperands, /*InsnID*/0, /*NumInsns*/1, /*MergeInsnID's*/0,
        GIR_ConstrainSelectedInstOperands, /*InsnID*/0,
        GIR_EraseFromParent, /*InsnID*/0,
        // GIR_Coverage, 5059,
        GIR_Done,
      // Label 6106: @447002
      GIM_Try, /*On fail goto*//*Label 6107*/ GIMT_Encode4(447084), // Rule ID 5067 //
        GIM_CheckRegBankForClass, /*MI*/0, /*Op*/0, /*RC*/GIMT_Encode2(AMDGPU::AV_64RegClassID),
        GIM_CheckConstantInt8, /*MI*/0, /*Op*/3, 0,
        // MIs[0] offset
        GIM_CheckIsImm, /*MI*/0, /*Op*/6,
        // MIs[0] auxiliary
        GIM_CheckIsImm, /*MI*/0, /*Op*/7,
        // MIs[0] Operand 8
        GIM_CheckLiteralInt, /*MI*/0, /*Op*/8, GIMT_Encode8(0),
        GIM_CheckComplexPattern, /*MI*/0, /*Op*/5, /*Renderer*/GIMT_Encode2(0), GIMT_Encode2(GICP_gi_buf_soffset),
        // (SIbuffer_atomic_or:{ *:[i64] } i64:{ *:[i64] }:$vdata_in, v4i32:{ *:[v4i32] }:$rsrc, 0:{ *:[i32] }, i32:{ *:[i32] }:$voffset, (BUFSOffset:{ *:[i32] } i32:{ *:[i32] }:$soffset), (timm:{ *:[i32] }):$offset, (timm:{ *:[i32] }):$auxiliary, 0:{ *:[i1] })  =>  (BUFFER_ATOMIC_OR_X2_VBUFFER_OFFEN_RTN:{ *:[i64] } anonymous_15036:{ *:[i64] }:$vdata_in, VGPR_32:{ *:[i32] }:$voffset, SReg_128:{ *:[v4i32] }:$rsrc, SCSrc_b32:{ *:[i32] }:$soffset, (timm:{ *:[i32] }):$offset, (extract_cpol_set_glc:{ *:[i32] } ?:{ *:[i32] }:$auxiliary))
        GIR_BuildMI, /*InsnID*/0, /*Opcode*/GIMT_Encode2(AMDGPU::BUFFER_ATOMIC_OR_X2_VBUFFER_OFFEN_RTN),
        GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/0, // DstI[vdata]
        GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/1, // vdata_in
        GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/4, // voffset
        GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/2, // rsrc
        GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/0, // soffset
        GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/6, // offset
        GIR_CustomOperandRenderer, /*InsnID*/0, /*OldInsnID*/0, /*OpIdx*/7, /*OperandRenderer*/GIMT_Encode2(GICR_renderExtractCpolSetGLC), // auxiliary
        GIR_MergeMemOperands, /*InsnID*/0, /*NumInsns*/1, /*MergeInsnID's*/0,
        GIR_ConstrainSelectedInstOperands, /*InsnID*/0,
        GIR_EraseFromParent, /*InsnID*/0,
        // GIR_Coverage, 5067,
        GIR_Done,
      // Label 6107: @447084
      GIM_Try, /*On fail goto*//*Label 6108*/ GIMT_Encode4(447154), // Rule ID 5062 //
        GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasUnrestrictedSOffset),
        GIM_CheckHasNoUse, /*MI*/0,
        GIM_CheckConstantInt8, /*MI*/0, /*Op*/4, 0,
        // MIs[0] offset
        GIM_CheckIsImm, /*MI*/0, /*Op*/6,
        // MIs[0] auxiliary
        GIM_CheckIsImm, /*MI*/0, /*Op*/7,
        // MIs[0] Operand 8
        GIM_CheckIsImm, /*MI*/0, /*Op*/8,
        GIM_CheckComplexPattern, /*MI*/0, /*Op*/5, /*Renderer*/GIMT_Encode2(0), GIMT_Encode2(GICP_gi_buf_soffset),
        // (SIbuffer_atomic_or:{ *:[i64] } i64:{ *:[i64] }:$vdata_in, v4i32:{ *:[v4i32] }:$rsrc, i32:{ *:[i32] }:$vindex, 0:{ *:[i32] }, (BUFSOffset:{ *:[i32] } i32:{ *:[i32] }:$soffset), (timm:{ *:[i32] }):$offset, (timm:{ *:[i32] }):$auxiliary, (timm:{ *:[i1] }))<<P:Predicate_SIbuffer_atomic_or_noret>>  =>  (BUFFER_ATOMIC_OR_X2_IDXEN anonymous_15036:{ *:[i64] }:$vdata_in, VGPR_32:{ *:[i32] }:$vindex, SReg_128:{ *:[v4i32] }:$rsrc, SCSrc_b32:{ *:[i32] }:$soffset, (timm:{ *:[i32] }):$offset, (extract_cpol:{ *:[i32] } ?:{ *:[i32] }:$auxiliary))
        GIR_BuildMI, /*InsnID*/0, /*Opcode*/GIMT_Encode2(AMDGPU::BUFFER_ATOMIC_OR_X2_IDXEN),
        GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/1, // vdata_in
        GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/3, // vindex
        GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/2, // rsrc
        GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/0, // soffset
        GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/6, // offset
        GIR_CustomOperandRenderer, /*InsnID*/0, /*OldInsnID*/0, /*OpIdx*/7, /*OperandRenderer*/GIMT_Encode2(GICR_renderExtractCPol), // auxiliary
        GIR_MergeMemOperands, /*InsnID*/0, /*NumInsns*/1, /*MergeInsnID's*/0,
        GIR_ConstrainSelectedInstOperands, /*InsnID*/0,
        GIR_EraseFromParent, /*InsnID*/0,
        // GIR_Coverage, 5062,
        GIR_Done,
      // Label 6108: @447154
      GIM_Try, /*On fail goto*//*Label 6109*/ GIMT_Encode4(447221), // Rule ID 5070 //
        GIM_CheckHasNoUse, /*MI*/0,
        GIM_CheckConstantInt8, /*MI*/0, /*Op*/4, 0,
        // MIs[0] offset
        GIM_CheckIsImm, /*MI*/0, /*Op*/6,
        // MIs[0] auxiliary
        GIM_CheckIsImm, /*MI*/0, /*Op*/7,
        // MIs[0] Operand 8
        GIM_CheckIsImm, /*MI*/0, /*Op*/8,
        GIM_CheckComplexPattern, /*MI*/0, /*Op*/5, /*Renderer*/GIMT_Encode2(0), GIMT_Encode2(GICP_gi_buf_soffset),
        // (SIbuffer_atomic_or:{ *:[i64] } i64:{ *:[i64] }:$vdata_in, v4i32:{ *:[v4i32] }:$rsrc, i32:{ *:[i32] }:$vindex, 0:{ *:[i32] }, (BUFSOffset:{ *:[i32] } i32:{ *:[i32] }:$soffset), (timm:{ *:[i32] }):$offset, (timm:{ *:[i32] }):$auxiliary, (timm:{ *:[i1] }))<<P:Predicate_SIbuffer_atomic_or_noret>>  =>  (BUFFER_ATOMIC_OR_X2_VBUFFER_IDXEN anonymous_15036:{ *:[i64] }:$vdata_in, VGPR_32:{ *:[i32] }:$vindex, SReg_128:{ *:[v4i32] }:$rsrc, SCSrc_b32:{ *:[i32] }:$soffset, (timm:{ *:[i32] }):$offset, (extract_cpol:{ *:[i32] } ?:{ *:[i32] }:$auxiliary))
        GIR_BuildMI, /*InsnID*/0, /*Opcode*/GIMT_Encode2(AMDGPU::BUFFER_ATOMIC_OR_X2_VBUFFER_IDXEN),
        GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/1, // vdata_in
        GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/3, // vindex
        GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/2, // rsrc
        GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/0, // soffset
        GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/6, // offset
        GIR_CustomOperandRenderer, /*InsnID*/0, /*OldInsnID*/0, /*OpIdx*/7, /*OperandRenderer*/GIMT_Encode2(GICR_renderExtractCPol), // auxiliary
        GIR_MergeMemOperands, /*InsnID*/0, /*NumInsns*/1, /*MergeInsnID's*/0,
        GIR_ConstrainSelectedInstOperands, /*InsnID*/0,
        GIR_EraseFromParent, /*InsnID*/0,
        // GIR_Coverage, 5070,
        GIR_Done,
      // Label 6109: @447221
      GIM_Try, /*On fail goto*//*Label 6110*/ GIMT_Encode4(447298), // Rule ID 5058 //
        GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasUnrestrictedSOffset),
        GIM_CheckRegBankForClass, /*MI*/0, /*Op*/0, /*RC*/GIMT_Encode2(AMDGPU::AV_64RegClassID),
        GIM_CheckConstantInt8, /*MI*/0, /*Op*/4, 0,
        // MIs[0] offset
        GIM_CheckIsImm, /*MI*/0, /*Op*/6,
        // MIs[0] auxiliary
        GIM_CheckIsImm, /*MI*/0, /*Op*/7,
        // MIs[0] Operand 8
        GIM_CheckIsImm, /*MI*/0, /*Op*/8,
        GIM_CheckComplexPattern, /*MI*/0, /*Op*/5, /*Renderer*/GIMT_Encode2(0), GIMT_Encode2(GICP_gi_buf_soffset),
        // (SIbuffer_atomic_or:{ *:[i64] } i64:{ *:[i64] }:$vdata_in, v4i32:{ *:[v4i32] }:$rsrc, i32:{ *:[i32] }:$vindex, 0:{ *:[i32] }, (BUFSOffset:{ *:[i32] } i32:{ *:[i32] }:$soffset), (timm:{ *:[i32] }):$offset, (timm:{ *:[i32] }):$auxiliary, (timm:{ *:[i1] }))  =>  (BUFFER_ATOMIC_OR_X2_IDXEN_RTN:{ *:[i64] } anonymous_15036:{ *:[i64] }:$vdata_in, VGPR_32:{ *:[i32] }:$vindex, SReg_128:{ *:[v4i32] }:$rsrc, SCSrc_b32:{ *:[i32] }:$soffset, (timm:{ *:[i32] }):$offset, (extract_cpol_set_glc:{ *:[i32] } ?:{ *:[i32] }:$auxiliary))
        GIR_BuildMI, /*InsnID*/0, /*Opcode*/GIMT_Encode2(AMDGPU::BUFFER_ATOMIC_OR_X2_IDXEN_RTN),
        GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/0, // DstI[vdata]
        GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/1, // vdata_in
        GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/3, // vindex
        GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/2, // rsrc
        GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/0, // soffset
        GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/6, // offset
        GIR_CustomOperandRenderer, /*InsnID*/0, /*OldInsnID*/0, /*OpIdx*/7, /*OperandRenderer*/GIMT_Encode2(GICR_renderExtractCpolSetGLC), // auxiliary
        GIR_MergeMemOperands, /*InsnID*/0, /*NumInsns*/1, /*MergeInsnID's*/0,
        GIR_ConstrainSelectedInstOperands, /*InsnID*/0,
        GIR_EraseFromParent, /*InsnID*/0,
        // GIR_Coverage, 5058,
        GIR_Done,
      // Label 6110: @447298
      GIM_Try, /*On fail goto*//*Label 6111*/ GIMT_Encode4(447372), // Rule ID 5066 //
        GIM_CheckRegBankForClass, /*MI*/0, /*Op*/0, /*RC*/GIMT_Encode2(AMDGPU::AV_64RegClassID),
        GIM_CheckConstantInt8, /*MI*/0, /*Op*/4, 0,
        // MIs[0] offset
        GIM_CheckIsImm, /*MI*/0, /*Op*/6,
        // MIs[0] auxiliary
        GIM_CheckIsImm, /*MI*/0, /*Op*/7,
        // MIs[0] Operand 8
        GIM_CheckIsImm, /*MI*/0, /*Op*/8,
        GIM_CheckComplexPattern, /*MI*/0, /*Op*/5, /*Renderer*/GIMT_Encode2(0), GIMT_Encode2(GICP_gi_buf_soffset),
        // (SIbuffer_atomic_or:{ *:[i64] } i64:{ *:[i64] }:$vdata_in, v4i32:{ *:[v4i32] }:$rsrc, i32:{ *:[i32] }:$vindex, 0:{ *:[i32] }, (BUFSOffset:{ *:[i32] } i32:{ *:[i32] }:$soffset), (timm:{ *:[i32] }):$offset, (timm:{ *:[i32] }):$auxiliary, (timm:{ *:[i1] }))  =>  (BUFFER_ATOMIC_OR_X2_VBUFFER_IDXEN_RTN:{ *:[i64] } anonymous_15036:{ *:[i64] }:$vdata_in, VGPR_32:{ *:[i32] }:$vindex, SReg_128:{ *:[v4i32] }:$rsrc, SCSrc_b32:{ *:[i32] }:$soffset, (timm:{ *:[i32] }):$offset, (extract_cpol_set_glc:{ *:[i32] } ?:{ *:[i32] }:$auxiliary))
        GIR_BuildMI, /*InsnID*/0, /*Opcode*/GIMT_Encode2(AMDGPU::BUFFER_ATOMIC_OR_X2_VBUFFER_IDXEN_RTN),
        GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/0, // DstI[vdata]
        GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/1, // vdata_in
        GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/3, // vindex
        GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/2, // rsrc
        GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/0, // soffset
        GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/6, // offset
        GIR_CustomOperandRenderer, /*InsnID*/0, /*OldInsnID*/0, /*OpIdx*/7, /*OperandRenderer*/GIMT_Encode2(GICR_renderExtractCpolSetGLC), // auxiliary
        GIR_MergeMemOperands, /*InsnID*/0, /*NumInsns*/1, /*MergeInsnID's*/0,
        GIR_ConstrainSelectedInstOperands, /*InsnID*/0,
        GIR_EraseFromParent, /*InsnID*/0,
        // GIR_Coverage, 5066,
        GIR_Done,
      // Label 6111: @447372
      GIM_Try, /*On fail goto*//*Label 6112*/ GIMT_Encode4(447478), // Rule ID 5064 //
        GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasUnrestrictedSOffset),
        GIM_CheckHasNoUse, /*MI*/0,
        // MIs[0] offset
        GIM_CheckIsImm, /*MI*/0, /*Op*/6,
        // MIs[0] auxiliary
        GIM_CheckIsImm, /*MI*/0, /*Op*/7,
        // MIs[0] Operand 8
        GIM_CheckIsImm, /*MI*/0, /*Op*/8,
        GIM_CheckComplexPattern, /*MI*/0, /*Op*/5, /*Renderer*/GIMT_Encode2(0), GIMT_Encode2(GICP_gi_buf_soffset),
        // (SIbuffer_atomic_or:{ *:[i64] } i64:{ *:[i64] }:$vdata_in, v4i32:{ *:[v4i32] }:$rsrc, i32:{ *:[i32] }:$vindex, i32:{ *:[i32] }:$voffset, (BUFSOffset:{ *:[i32] } i32:{ *:[i32] }:$soffset), (timm:{ *:[i32] }):$offset, (timm:{ *:[i32] }):$auxiliary, (timm:{ *:[i1] }))<<P:Predicate_SIbuffer_atomic_or_noret>>  =>  (BUFFER_ATOMIC_OR_X2_BOTHEN anonymous_15036:{ *:[i64] }:$vdata_in, (REG_SEQUENCE:{ *:[i64] } VReg_64:{ *:[i32] }, VGPR_32:{ *:[i32] }:$vindex, sub0:{ *:[i32] }, VGPR_32:{ *:[i32] }:$voffset, sub1:{ *:[i32] }), SReg_128:{ *:[v4i32] }:$rsrc, SCSrc_b32:{ *:[i32] }:$soffset, (timm:{ *:[i32] }):$offset, (extract_cpol:{ *:[i32] } ?:{ *:[i32] }:$auxiliary))
        GIR_MakeTempReg, /*TempRegID*/0, /*TypeID*/GILLT_s64,
        GIR_BuildMI, /*InsnID*/1, /*Opcode*/GIMT_Encode2(TargetOpcode::REG_SEQUENCE),
        GIR_AddTempRegister, /*InsnID*/1, /*TempRegID*/0, /*TempRegFlags*/GIMT_Encode2(RegState::Define),
        GIR_Copy, /*NewInsnID*/1, /*OldInsnID*/0, /*OpIdx*/3, // vindex
        GIR_AddImm8, /*InsnID*/1, /*SubRegIndex*/3,
        GIR_Copy, /*NewInsnID*/1, /*OldInsnID*/0, /*OpIdx*/4, // voffset
        GIR_AddImm8, /*InsnID*/1, /*SubRegIndex*/11,
        GIR_ConstrainOperandRC, /*InsnID*/1, /*Op*/0, GIMT_Encode2(AMDGPU::VReg_64RegClassID),
        GIR_ConstrainOperandRC, /*InsnID*/1, /*Op*/1, GIMT_Encode2(AMDGPU::VGPR_32RegClassID),
        GIR_ConstrainOperandRC, /*InsnID*/1, /*Op*/3, GIMT_Encode2(AMDGPU::VGPR_32RegClassID),
        GIR_BuildMI, /*InsnID*/0, /*Opcode*/GIMT_Encode2(AMDGPU::BUFFER_ATOMIC_OR_X2_BOTHEN),
        GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/1, // vdata_in
        GIR_AddSimpleTempRegister, /*InsnID*/0, /*TempRegID*/0,
        GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/2, // rsrc
        GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/0, // soffset
        GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/6, // offset
        GIR_CustomOperandRenderer, /*InsnID*/0, /*OldInsnID*/0, /*OpIdx*/7, /*OperandRenderer*/GIMT_Encode2(GICR_renderExtractCPol), // auxiliary
        GIR_MergeMemOperands, /*InsnID*/0, /*NumInsns*/1, /*MergeInsnID's*/0,
        GIR_ConstrainSelectedInstOperands, /*InsnID*/0,
        GIR_EraseFromParent, /*InsnID*/0,
        // GIR_Coverage, 5064,
        GIR_Done,
      // Label 6112: @447478
      GIM_Try, /*On fail goto*//*Label 6113*/ GIMT_Encode4(447581), // Rule ID 5072 //
        GIM_CheckHasNoUse, /*MI*/0,
        // MIs[0] offset
        GIM_CheckIsImm, /*MI*/0, /*Op*/6,
        // MIs[0] auxiliary
        GIM_CheckIsImm, /*MI*/0, /*Op*/7,
        // MIs[0] Operand 8
        GIM_CheckIsImm, /*MI*/0, /*Op*/8,
        GIM_CheckComplexPattern, /*MI*/0, /*Op*/5, /*Renderer*/GIMT_Encode2(0), GIMT_Encode2(GICP_gi_buf_soffset),
        // (SIbuffer_atomic_or:{ *:[i64] } i64:{ *:[i64] }:$vdata_in, v4i32:{ *:[v4i32] }:$rsrc, i32:{ *:[i32] }:$vindex, i32:{ *:[i32] }:$voffset, (BUFSOffset:{ *:[i32] } i32:{ *:[i32] }:$soffset), (timm:{ *:[i32] }):$offset, (timm:{ *:[i32] }):$auxiliary, (timm:{ *:[i1] }))<<P:Predicate_SIbuffer_atomic_or_noret>>  =>  (BUFFER_ATOMIC_OR_X2_VBUFFER_BOTHEN anonymous_15036:{ *:[i64] }:$vdata_in, (REG_SEQUENCE:{ *:[i64] } VReg_64:{ *:[i32] }, VGPR_32:{ *:[i32] }:$vindex, sub0:{ *:[i32] }, VGPR_32:{ *:[i32] }:$voffset, sub1:{ *:[i32] }), SReg_128:{ *:[v4i32] }:$rsrc, SCSrc_b32:{ *:[i32] }:$soffset, (timm:{ *:[i32] }):$offset, (extract_cpol:{ *:[i32] } ?:{ *:[i32] }:$auxiliary))
        GIR_MakeTempReg, /*TempRegID*/0, /*TypeID*/GILLT_s64,
        GIR_BuildMI, /*InsnID*/1, /*Opcode*/GIMT_Encode2(TargetOpcode::REG_SEQUENCE),
        GIR_AddTempRegister, /*InsnID*/1, /*TempRegID*/0, /*TempRegFlags*/GIMT_Encode2(RegState::Define),
        GIR_Copy, /*NewInsnID*/1, /*OldInsnID*/0, /*OpIdx*/3, // vindex
        GIR_AddImm8, /*InsnID*/1, /*SubRegIndex*/3,
        GIR_Copy, /*NewInsnID*/1, /*OldInsnID*/0, /*OpIdx*/4, // voffset
        GIR_AddImm8, /*InsnID*/1, /*SubRegIndex*/11,
        GIR_ConstrainOperandRC, /*InsnID*/1, /*Op*/0, GIMT_Encode2(AMDGPU::VReg_64RegClassID),
        GIR_ConstrainOperandRC, /*InsnID*/1, /*Op*/1, GIMT_Encode2(AMDGPU::VGPR_32RegClassID),
        GIR_ConstrainOperandRC, /*InsnID*/1, /*Op*/3, GIMT_Encode2(AMDGPU::VGPR_32RegClassID),
        GIR_BuildMI, /*InsnID*/0, /*Opcode*/GIMT_Encode2(AMDGPU::BUFFER_ATOMIC_OR_X2_VBUFFER_BOTHEN),
        GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/1, // vdata_in
        GIR_AddSimpleTempRegister, /*InsnID*/0, /*TempRegID*/0,
        GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/2, // rsrc
        GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/0, // soffset
        GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/6, // offset
        GIR_CustomOperandRenderer, /*InsnID*/0, /*OldInsnID*/0, /*OpIdx*/7, /*OperandRenderer*/GIMT_Encode2(GICR_renderExtractCPol), // auxiliary
        GIR_MergeMemOperands, /*InsnID*/0, /*NumInsns*/1, /*MergeInsnID's*/0,
        GIR_ConstrainSelectedInstOperands, /*InsnID*/0,
        GIR_EraseFromParent, /*InsnID*/0,
        // GIR_Coverage, 5072,
        GIR_Done,
      // Label 6113: @447581
      GIM_Try, /*On fail goto*//*Label 6114*/ GIMT_Encode4(447694), // Rule ID 5060 //
        GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasUnrestrictedSOffset),
        GIM_CheckRegBankForClass, /*MI*/0, /*Op*/0, /*RC*/GIMT_Encode2(AMDGPU::AV_64RegClassID),
        // MIs[0] offset
        GIM_CheckIsImm, /*MI*/0, /*Op*/6,
        // MIs[0] auxiliary
        GIM_CheckIsImm, /*MI*/0, /*Op*/7,
        // MIs[0] Operand 8
        GIM_CheckIsImm, /*MI*/0, /*Op*/8,
        GIM_CheckComplexPattern, /*MI*/0, /*Op*/5, /*Renderer*/GIMT_Encode2(0), GIMT_Encode2(GICP_gi_buf_soffset),
        // (SIbuffer_atomic_or:{ *:[i64] } i64:{ *:[i64] }:$vdata_in, v4i32:{ *:[v4i32] }:$rsrc, i32:{ *:[i32] }:$vindex, i32:{ *:[i32] }:$voffset, (BUFSOffset:{ *:[i32] } i32:{ *:[i32] }:$soffset), (timm:{ *:[i32] }):$offset, (timm:{ *:[i32] }):$auxiliary, (timm:{ *:[i1] }))  =>  (BUFFER_ATOMIC_OR_X2_BOTHEN_RTN:{ *:[i64] } anonymous_15036:{ *:[i64] }:$vdata_in, (REG_SEQUENCE:{ *:[i64] } VReg_64:{ *:[i32] }, VGPR_32:{ *:[i32] }:$vindex, sub0:{ *:[i32] }, VGPR_32:{ *:[i32] }:$voffset, sub1:{ *:[i32] }), SReg_128:{ *:[v4i32] }:$rsrc, SCSrc_b32:{ *:[i32] }:$soffset, (timm:{ *:[i32] }):$offset, (extract_cpol_set_glc:{ *:[i32] } ?:{ *:[i32] }:$auxiliary))
        GIR_MakeTempReg, /*TempRegID*/0, /*TypeID*/GILLT_s64,
        GIR_BuildMI, /*InsnID*/1, /*Opcode*/GIMT_Encode2(TargetOpcode::REG_SEQUENCE),
        GIR_AddTempRegister, /*InsnID*/1, /*TempRegID*/0, /*TempRegFlags*/GIMT_Encode2(RegState::Define),
        GIR_Copy, /*NewInsnID*/1, /*OldInsnID*/0, /*OpIdx*/3, // vindex
        GIR_AddImm8, /*InsnID*/1, /*SubRegIndex*/3,
        GIR_Copy, /*NewInsnID*/1, /*OldInsnID*/0, /*OpIdx*/4, // voffset
        GIR_AddImm8, /*InsnID*/1, /*SubRegIndex*/11,
        GIR_ConstrainOperandRC, /*InsnID*/1, /*Op*/0, GIMT_Encode2(AMDGPU::VReg_64RegClassID),
        GIR_ConstrainOperandRC, /*InsnID*/1, /*Op*/1, GIMT_Encode2(AMDGPU::VGPR_32RegClassID),
        GIR_ConstrainOperandRC, /*InsnID*/1, /*Op*/3, GIMT_Encode2(AMDGPU::VGPR_32RegClassID),
        GIR_BuildMI, /*InsnID*/0, /*Opcode*/GIMT_Encode2(AMDGPU::BUFFER_ATOMIC_OR_X2_BOTHEN_RTN),
        GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/0, // DstI[vdata]
        GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/1, // vdata_in
        GIR_AddSimpleTempRegister, /*InsnID*/0, /*TempRegID*/0,
        GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/2, // rsrc
        GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/0, // soffset
        GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/6, // offset
        GIR_CustomOperandRenderer, /*InsnID*/0, /*OldInsnID*/0, /*OpIdx*/7, /*OperandRenderer*/GIMT_Encode2(GICR_renderExtractCpolSetGLC), // auxiliary
        GIR_MergeMemOperands, /*InsnID*/0, /*NumInsns*/1, /*MergeInsnID's*/0,
        GIR_ConstrainSelectedInstOperands, /*InsnID*/0,
        GIR_EraseFromParent, /*InsnID*/0,
        // GIR_Coverage, 5060,
        GIR_Done,
      // Label 6114: @447694
      GIM_Try, /*On fail goto*//*Label 6115*/ GIMT_Encode4(447804), // Rule ID 5068 //
        GIM_CheckRegBankForClass, /*MI*/0, /*Op*/0, /*RC*/GIMT_Encode2(AMDGPU::AV_64RegClassID),
        // MIs[0] offset
        GIM_CheckIsImm, /*MI*/0, /*Op*/6,
        // MIs[0] auxiliary
        GIM_CheckIsImm, /*MI*/0, /*Op*/7,
        // MIs[0] Operand 8
        GIM_CheckIsImm, /*MI*/0, /*Op*/8,
        GIM_CheckComplexPattern, /*MI*/0, /*Op*/5, /*Renderer*/GIMT_Encode2(0), GIMT_Encode2(GICP_gi_buf_soffset),
        // (SIbuffer_atomic_or:{ *:[i64] } i64:{ *:[i64] }:$vdata_in, v4i32:{ *:[v4i32] }:$rsrc, i32:{ *:[i32] }:$vindex, i32:{ *:[i32] }:$voffset, (BUFSOffset:{ *:[i32] } i32:{ *:[i32] }:$soffset), (timm:{ *:[i32] }):$offset, (timm:{ *:[i32] }):$auxiliary, (timm:{ *:[i1] }))  =>  (BUFFER_ATOMIC_OR_X2_VBUFFER_BOTHEN_RTN:{ *:[i64] } anonymous_15036:{ *:[i64] }:$vdata_in, (REG_SEQUENCE:{ *:[i64] } VReg_64:{ *:[i32] }, VGPR_32:{ *:[i32] }:$vindex, sub0:{ *:[i32] }, VGPR_32:{ *:[i32] }:$voffset, sub1:{ *:[i32] }), SReg_128:{ *:[v4i32] }:$rsrc, SCSrc_b32:{ *:[i32] }:$soffset, (timm:{ *:[i32] }):$offset, (extract_cpol_set_glc:{ *:[i32] } ?:{ *:[i32] }:$auxiliary))
        GIR_MakeTempReg, /*TempRegID*/0, /*TypeID*/GILLT_s64,
        GIR_BuildMI, /*InsnID*/1, /*Opcode*/GIMT_Encode2(TargetOpcode::REG_SEQUENCE),
        GIR_AddTempRegister, /*InsnID*/1, /*TempRegID*/0, /*TempRegFlags*/GIMT_Encode2(RegState::Define),
        GIR_Copy, /*NewInsnID*/1, /*OldInsnID*/0, /*OpIdx*/3, // vindex
        GIR_AddImm8, /*InsnID*/1, /*SubRegIndex*/3,
        GIR_Copy, /*NewInsnID*/1, /*OldInsnID*/0, /*OpIdx*/4, // voffset
        GIR_AddImm8, /*InsnID*/1, /*SubRegIndex*/11,
        GIR_ConstrainOperandRC, /*InsnID*/1, /*Op*/0, GIMT_Encode2(AMDGPU::VReg_64RegClassID),
        GIR_ConstrainOperandRC, /*InsnID*/1, /*Op*/1, GIMT_Encode2(AMDGPU::VGPR_32RegClassID),
        GIR_ConstrainOperandRC, /*InsnID*/1, /*Op*/3, GIMT_Encode2(AMDGPU::VGPR_32RegClassID),
        GIR_BuildMI, /*InsnID*/0, /*Opcode*/GIMT_Encode2(AMDGPU::BUFFER_ATOMIC_OR_X2_VBUFFER_BOTHEN_RTN),
        GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/0, // DstI[vdata]
        GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/1, // vdata_in
        GIR_AddSimpleTempRegister, /*InsnID*/0, /*TempRegID*/0,
        GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/2, // rsrc
        GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/0, // soffset
        GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/6, // offset
        GIR_CustomOperandRenderer, /*InsnID*/0, /*OldInsnID*/0, /*OpIdx*/7, /*OperandRenderer*/GIMT_Encode2(GICR_renderExtractCpolSetGLC), // auxiliary
        GIR_MergeMemOperands, /*InsnID*/0, /*NumInsns*/1, /*MergeInsnID's*/0,
        GIR_ConstrainSelectedInstOperands, /*InsnID*/0,
        GIR_EraseFromParent, /*InsnID*/0,
        // GIR_Coverage, 5068,
        GIR_Done,
      // Label 6115: @447804
      GIM_Reject,
    // Label 6099: @447805
    GIM_Reject,
    // Label 6081: @447806
    GIM_Reject,
    // Label 117: @447807
    GIM_SwitchType, /*MI*/0, /*Op*/0, /*[*/GIMT_Encode2(9), GIMT_Encode2(11), /*)*//*default:*//*Label 6118*/ GIMT_Encode4(450600),
    /*GILLT_s32*//*Label 6116*/ GIMT_Encode4(447826),
    /*GILLT_s64*//*Label 6117*/ GIMT_Encode4(449213),
    // Label 6116: @447826
    GIM_Try, /*On fail goto*//*Label 6119*/ GIMT_Encode4(449212),
      GIM_CheckType, /*MI*/0, /*Op*/1, /*Type*/GILLT_s32,
      GIM_CheckType, /*MI*/0, /*Op*/2, /*Type*/GILLT_v4s32,
      GIM_CheckType, /*MI*/0, /*Op*/3, /*Type*/GILLT_s32,
      GIM_CheckType, /*MI*/0, /*Op*/4, /*Type*/GILLT_s32,
      GIM_CheckType, /*MI*/0, /*Op*/5, /*Type*/GILLT_s32,
      GIM_Try, /*On fail goto*//*Label 6120*/ GIMT_Encode4(447929), // Rule ID 4813 //
        GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasUnrestrictedSOffset),
        GIM_CheckHasNoUse, /*MI*/0,
        GIM_CheckConstantInt8, /*MI*/0, /*Op*/3, 0,
        GIM_CheckConstantInt8, /*MI*/0, /*Op*/4, 0,
        // MIs[0] offset
        GIM_CheckIsImm, /*MI*/0, /*Op*/6,
        // MIs[0] auxiliary
        GIM_CheckIsImm, /*MI*/0, /*Op*/7,
        // MIs[0] Operand 8
        GIM_CheckLiteralInt, /*MI*/0, /*Op*/8, GIMT_Encode8(0),
        GIM_CheckComplexPattern, /*MI*/0, /*Op*/5, /*Renderer*/GIMT_Encode2(0), GIMT_Encode2(GICP_gi_buf_soffset),
        // (SIbuffer_atomic_smax:{ *:[i32] } i32:{ *:[i32] }:$vdata_in, v4i32:{ *:[v4i32] }:$rsrc, 0:{ *:[i32] }, 0:{ *:[i32] }, (BUFSOffset:{ *:[i32] } i32:{ *:[i32] }:$soffset), (timm:{ *:[i32] }):$offset, (timm:{ *:[i32] }):$auxiliary, 0:{ *:[i1] })<<P:Predicate_SIbuffer_atomic_smax_noret>>  =>  (BUFFER_ATOMIC_SMAX_OFFSET anonymous_15037:{ *:[i32] }:$vdata_in, SReg_128:{ *:[v4i32] }:$rsrc, SCSrc_b32:{ *:[i32] }:$soffset, (timm:{ *:[i32] }):$offset, (extract_cpol:{ *:[i32] } ?:{ *:[i32] }:$auxiliary))
        GIR_BuildMI, /*InsnID*/0, /*Opcode*/GIMT_Encode2(AMDGPU::BUFFER_ATOMIC_SMAX_OFFSET),
        GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/1, // vdata_in
        GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/2, // rsrc
        GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/0, // soffset
        GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/6, // offset
        GIR_CustomOperandRenderer, /*InsnID*/0, /*OldInsnID*/0, /*OpIdx*/7, /*OperandRenderer*/GIMT_Encode2(GICR_renderExtractCPol), // auxiliary
        GIR_MergeMemOperands, /*InsnID*/0, /*NumInsns*/1, /*MergeInsnID's*/0,
        GIR_ConstrainSelectedInstOperands, /*InsnID*/0,
        GIR_EraseFromParent, /*InsnID*/0,
        // GIR_Coverage, 4813,
        GIR_Done,
      // Label 6120: @447929
      GIM_Try, /*On fail goto*//*Label 6121*/ GIMT_Encode4(448004), // Rule ID 4821 //
        GIM_CheckHasNoUse, /*MI*/0,
        GIM_CheckConstantInt8, /*MI*/0, /*Op*/3, 0,
        GIM_CheckConstantInt8, /*MI*/0, /*Op*/4, 0,
        // MIs[0] offset
        GIM_CheckIsImm, /*MI*/0, /*Op*/6,
        // MIs[0] auxiliary
        GIM_CheckIsImm, /*MI*/0, /*Op*/7,
        // MIs[0] Operand 8
        GIM_CheckLiteralInt, /*MI*/0, /*Op*/8, GIMT_Encode8(0),
        GIM_CheckComplexPattern, /*MI*/0, /*Op*/5, /*Renderer*/GIMT_Encode2(0), GIMT_Encode2(GICP_gi_buf_soffset),
        // (SIbuffer_atomic_smax:{ *:[i32] } i32:{ *:[i32] }:$vdata_in, v4i32:{ *:[v4i32] }:$rsrc, 0:{ *:[i32] }, 0:{ *:[i32] }, (BUFSOffset:{ *:[i32] } i32:{ *:[i32] }:$soffset), (timm:{ *:[i32] }):$offset, (timm:{ *:[i32] }):$auxiliary, 0:{ *:[i1] })<<P:Predicate_SIbuffer_atomic_smax_noret>>  =>  (BUFFER_ATOMIC_SMAX_VBUFFER_OFFSET anonymous_15037:{ *:[i32] }:$vdata_in, SReg_128:{ *:[v4i32] }:$rsrc, SCSrc_b32:{ *:[i32] }:$soffset, (timm:{ *:[i32] }):$offset, (extract_cpol:{ *:[i32] } ?:{ *:[i32] }:$auxiliary))
        GIR_BuildMI, /*InsnID*/0, /*Opcode*/GIMT_Encode2(AMDGPU::BUFFER_ATOMIC_SMAX_VBUFFER_OFFSET),
        GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/1, // vdata_in
        GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/2, // rsrc
        GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/0, // soffset
        GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/6, // offset
        GIR_CustomOperandRenderer, /*InsnID*/0, /*OldInsnID*/0, /*OpIdx*/7, /*OperandRenderer*/GIMT_Encode2(GICR_renderExtractCPol), // auxiliary
        GIR_MergeMemOperands, /*InsnID*/0, /*NumInsns*/1, /*MergeInsnID's*/0,
        GIR_ConstrainSelectedInstOperands, /*InsnID*/0,
        GIR_EraseFromParent, /*InsnID*/0,
        // GIR_Coverage, 4821,
        GIR_Done,
      // Label 6121: @448004
      GIM_Try, /*On fail goto*//*Label 6122*/ GIMT_Encode4(448089), // Rule ID 4809 //
        GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasUnrestrictedSOffset),
        GIM_CheckRegBankForClass, /*MI*/0, /*Op*/0, /*RC*/GIMT_Encode2(AMDGPU::AV_32RegClassID),
        GIM_CheckConstantInt8, /*MI*/0, /*Op*/3, 0,
        GIM_CheckConstantInt8, /*MI*/0, /*Op*/4, 0,
        // MIs[0] offset
        GIM_CheckIsImm, /*MI*/0, /*Op*/6,
        // MIs[0] auxiliary
        GIM_CheckIsImm, /*MI*/0, /*Op*/7,
        // MIs[0] Operand 8
        GIM_CheckLiteralInt, /*MI*/0, /*Op*/8, GIMT_Encode8(0),
        GIM_CheckComplexPattern, /*MI*/0, /*Op*/5, /*Renderer*/GIMT_Encode2(0), GIMT_Encode2(GICP_gi_buf_soffset),
        // (SIbuffer_atomic_smax:{ *:[i32] } i32:{ *:[i32] }:$vdata_in, v4i32:{ *:[v4i32] }:$rsrc, 0:{ *:[i32] }, 0:{ *:[i32] }, (BUFSOffset:{ *:[i32] } i32:{ *:[i32] }:$soffset), (timm:{ *:[i32] }):$offset, (timm:{ *:[i32] }):$auxiliary, 0:{ *:[i1] })  =>  (BUFFER_ATOMIC_SMAX_OFFSET_RTN:{ *:[i32] } anonymous_15037:{ *:[i32] }:$vdata_in, SReg_128:{ *:[v4i32] }:$rsrc, SCSrc_b32:{ *:[i32] }:$soffset, (timm:{ *:[i32] }):$offset, (extract_cpol_set_glc:{ *:[i32] } ?:{ *:[i32] }:$auxiliary))
        GIR_BuildMI, /*InsnID*/0, /*Opcode*/GIMT_Encode2(AMDGPU::BUFFER_ATOMIC_SMAX_OFFSET_RTN),
        GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/0, // DstI[vdata]
        GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/1, // vdata_in
        GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/2, // rsrc
        GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/0, // soffset
        GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/6, // offset
        GIR_CustomOperandRenderer, /*InsnID*/0, /*OldInsnID*/0, /*OpIdx*/7, /*OperandRenderer*/GIMT_Encode2(GICR_renderExtractCpolSetGLC), // auxiliary
        GIR_MergeMemOperands, /*InsnID*/0, /*NumInsns*/1, /*MergeInsnID's*/0,
        GIR_ConstrainSelectedInstOperands, /*InsnID*/0,
        GIR_EraseFromParent, /*InsnID*/0,
        // GIR_Coverage, 4809,
        GIR_Done,
      // Label 6122: @448089
      GIM_Try, /*On fail goto*//*Label 6123*/ GIMT_Encode4(448171), // Rule ID 4817 //
        GIM_CheckRegBankForClass, /*MI*/0, /*Op*/0, /*RC*/GIMT_Encode2(AMDGPU::AV_32RegClassID),
        GIM_CheckConstantInt8, /*MI*/0, /*Op*/3, 0,
        GIM_CheckConstantInt8, /*MI*/0, /*Op*/4, 0,
        // MIs[0] offset
        GIM_CheckIsImm, /*MI*/0, /*Op*/6,
        // MIs[0] auxiliary
        GIM_CheckIsImm, /*MI*/0, /*Op*/7,
        // MIs[0] Operand 8
        GIM_CheckLiteralInt, /*MI*/0, /*Op*/8, GIMT_Encode8(0),
        GIM_CheckComplexPattern, /*MI*/0, /*Op*/5, /*Renderer*/GIMT_Encode2(0), GIMT_Encode2(GICP_gi_buf_soffset),
        // (SIbuffer_atomic_smax:{ *:[i32] } i32:{ *:[i32] }:$vdata_in, v4i32:{ *:[v4i32] }:$rsrc, 0:{ *:[i32] }, 0:{ *:[i32] }, (BUFSOffset:{ *:[i32] } i32:{ *:[i32] }:$soffset), (timm:{ *:[i32] }):$offset, (timm:{ *:[i32] }):$auxiliary, 0:{ *:[i1] })  =>  (BUFFER_ATOMIC_SMAX_VBUFFER_OFFSET_RTN:{ *:[i32] } anonymous_15037:{ *:[i32] }:$vdata_in, SReg_128:{ *:[v4i32] }:$rsrc, SCSrc_b32:{ *:[i32] }:$soffset, (timm:{ *:[i32] }):$offset, (extract_cpol_set_glc:{ *:[i32] } ?:{ *:[i32] }:$auxiliary))
        GIR_BuildMI, /*InsnID*/0, /*Opcode*/GIMT_Encode2(AMDGPU::BUFFER_ATOMIC_SMAX_VBUFFER_OFFSET_RTN),
        GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/0, // DstI[vdata]
        GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/1, // vdata_in
        GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/2, // rsrc
        GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/0, // soffset
        GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/6, // offset
        GIR_CustomOperandRenderer, /*InsnID*/0, /*OldInsnID*/0, /*OpIdx*/7, /*OperandRenderer*/GIMT_Encode2(GICR_renderExtractCpolSetGLC), // auxiliary
        GIR_MergeMemOperands, /*InsnID*/0, /*NumInsns*/1, /*MergeInsnID's*/0,
        GIR_ConstrainSelectedInstOperands, /*InsnID*/0,
        GIR_EraseFromParent, /*InsnID*/0,
        // GIR_Coverage, 4817,
        GIR_Done,
      // Label 6123: @448171
      GIM_Try, /*On fail goto*//*Label 6124*/ GIMT_Encode4(448249), // Rule ID 4815 //
        GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasUnrestrictedSOffset),
        GIM_CheckHasNoUse, /*MI*/0,
        GIM_CheckConstantInt8, /*MI*/0, /*Op*/3, 0,
        // MIs[0] offset
        GIM_CheckIsImm, /*MI*/0, /*Op*/6,
        // MIs[0] auxiliary
        GIM_CheckIsImm, /*MI*/0, /*Op*/7,
        // MIs[0] Operand 8
        GIM_CheckLiteralInt, /*MI*/0, /*Op*/8, GIMT_Encode8(0),
        GIM_CheckComplexPattern, /*MI*/0, /*Op*/5, /*Renderer*/GIMT_Encode2(0), GIMT_Encode2(GICP_gi_buf_soffset),
        // (SIbuffer_atomic_smax:{ *:[i32] } i32:{ *:[i32] }:$vdata_in, v4i32:{ *:[v4i32] }:$rsrc, 0:{ *:[i32] }, i32:{ *:[i32] }:$voffset, (BUFSOffset:{ *:[i32] } i32:{ *:[i32] }:$soffset), (timm:{ *:[i32] }):$offset, (timm:{ *:[i32] }):$auxiliary, 0:{ *:[i1] })<<P:Predicate_SIbuffer_atomic_smax_noret>>  =>  (BUFFER_ATOMIC_SMAX_OFFEN anonymous_15037:{ *:[i32] }:$vdata_in, VGPR_32:{ *:[i32] }:$voffset, SReg_128:{ *:[v4i32] }:$rsrc, SCSrc_b32:{ *:[i32] }:$soffset, (timm:{ *:[i32] }):$offset, (extract_cpol:{ *:[i32] } ?:{ *:[i32] }:$auxiliary))
        GIR_BuildMI, /*InsnID*/0, /*Opcode*/GIMT_Encode2(AMDGPU::BUFFER_ATOMIC_SMAX_OFFEN),
        GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/1, // vdata_in
        GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/4, // voffset
        GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/2, // rsrc
        GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/0, // soffset
        GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/6, // offset
        GIR_CustomOperandRenderer, /*InsnID*/0, /*OldInsnID*/0, /*OpIdx*/7, /*OperandRenderer*/GIMT_Encode2(GICR_renderExtractCPol), // auxiliary
        GIR_MergeMemOperands, /*InsnID*/0, /*NumInsns*/1, /*MergeInsnID's*/0,
        GIR_ConstrainSelectedInstOperands, /*InsnID*/0,
        GIR_EraseFromParent, /*InsnID*/0,
        // GIR_Coverage, 4815,
        GIR_Done,
      // Label 6124: @448249
      GIM_Try, /*On fail goto*//*Label 6125*/ GIMT_Encode4(448324), // Rule ID 4823 //
        GIM_CheckHasNoUse, /*MI*/0,
        GIM_CheckConstantInt8, /*MI*/0, /*Op*/3, 0,
        // MIs[0] offset
        GIM_CheckIsImm, /*MI*/0, /*Op*/6,
        // MIs[0] auxiliary
        GIM_CheckIsImm, /*MI*/0, /*Op*/7,
        // MIs[0] Operand 8
        GIM_CheckLiteralInt, /*MI*/0, /*Op*/8, GIMT_Encode8(0),
        GIM_CheckComplexPattern, /*MI*/0, /*Op*/5, /*Renderer*/GIMT_Encode2(0), GIMT_Encode2(GICP_gi_buf_soffset),
        // (SIbuffer_atomic_smax:{ *:[i32] } i32:{ *:[i32] }:$vdata_in, v4i32:{ *:[v4i32] }:$rsrc, 0:{ *:[i32] }, i32:{ *:[i32] }:$voffset, (BUFSOffset:{ *:[i32] } i32:{ *:[i32] }:$soffset), (timm:{ *:[i32] }):$offset, (timm:{ *:[i32] }):$auxiliary, 0:{ *:[i1] })<<P:Predicate_SIbuffer_atomic_smax_noret>>  =>  (BUFFER_ATOMIC_SMAX_VBUFFER_OFFEN anonymous_15037:{ *:[i32] }:$vdata_in, VGPR_32:{ *:[i32] }:$voffset, SReg_128:{ *:[v4i32] }:$rsrc, SCSrc_b32:{ *:[i32] }:$soffset, (timm:{ *:[i32] }):$offset, (extract_cpol:{ *:[i32] } ?:{ *:[i32] }:$auxiliary))
        GIR_BuildMI, /*InsnID*/0, /*Opcode*/GIMT_Encode2(AMDGPU::BUFFER_ATOMIC_SMAX_VBUFFER_OFFEN),
        GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/1, // vdata_in
        GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/4, // voffset
        GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/2, // rsrc
        GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/0, // soffset
        GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/6, // offset
        GIR_CustomOperandRenderer, /*InsnID*/0, /*OldInsnID*/0, /*OpIdx*/7, /*OperandRenderer*/GIMT_Encode2(GICR_renderExtractCPol), // auxiliary
        GIR_MergeMemOperands, /*InsnID*/0, /*NumInsns*/1, /*MergeInsnID's*/0,
        GIR_ConstrainSelectedInstOperands, /*InsnID*/0,
        GIR_EraseFromParent, /*InsnID*/0,
        // GIR_Coverage, 4823,
        GIR_Done,
      // Label 6125: @448324
      GIM_Try, /*On fail goto*//*Label 6126*/ GIMT_Encode4(448409), // Rule ID 4811 //
        GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasUnrestrictedSOffset),
        GIM_CheckRegBankForClass, /*MI*/0, /*Op*/0, /*RC*/GIMT_Encode2(AMDGPU::AV_32RegClassID),
        GIM_CheckConstantInt8, /*MI*/0, /*Op*/3, 0,
        // MIs[0] offset
        GIM_CheckIsImm, /*MI*/0, /*Op*/6,
        // MIs[0] auxiliary
        GIM_CheckIsImm, /*MI*/0, /*Op*/7,
        // MIs[0] Operand 8
        GIM_CheckLiteralInt, /*MI*/0, /*Op*/8, GIMT_Encode8(0),
        GIM_CheckComplexPattern, /*MI*/0, /*Op*/5, /*Renderer*/GIMT_Encode2(0), GIMT_Encode2(GICP_gi_buf_soffset),
        // (SIbuffer_atomic_smax:{ *:[i32] } i32:{ *:[i32] }:$vdata_in, v4i32:{ *:[v4i32] }:$rsrc, 0:{ *:[i32] }, i32:{ *:[i32] }:$voffset, (BUFSOffset:{ *:[i32] } i32:{ *:[i32] }:$soffset), (timm:{ *:[i32] }):$offset, (timm:{ *:[i32] }):$auxiliary, 0:{ *:[i1] })  =>  (BUFFER_ATOMIC_SMAX_OFFEN_RTN:{ *:[i32] } anonymous_15037:{ *:[i32] }:$vdata_in, VGPR_32:{ *:[i32] }:$voffset, SReg_128:{ *:[v4i32] }:$rsrc, SCSrc_b32:{ *:[i32] }:$soffset, (timm:{ *:[i32] }):$offset, (extract_cpol_set_glc:{ *:[i32] } ?:{ *:[i32] }:$auxiliary))
        GIR_BuildMI, /*InsnID*/0, /*Opcode*/GIMT_Encode2(AMDGPU::BUFFER_ATOMIC_SMAX_OFFEN_RTN),
        GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/0, // DstI[vdata]
        GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/1, // vdata_in
        GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/4, // voffset
        GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/2, // rsrc
        GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/0, // soffset
        GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/6, // offset
        GIR_CustomOperandRenderer, /*InsnID*/0, /*OldInsnID*/0, /*OpIdx*/7, /*OperandRenderer*/GIMT_Encode2(GICR_renderExtractCpolSetGLC), // auxiliary
        GIR_MergeMemOperands, /*InsnID*/0, /*NumInsns*/1, /*MergeInsnID's*/0,
        GIR_ConstrainSelectedInstOperands, /*InsnID*/0,
        GIR_EraseFromParent, /*InsnID*/0,
        // GIR_Coverage, 4811,
        GIR_Done,
      // Label 6126: @448409
      GIM_Try, /*On fail goto*//*Label 6127*/ GIMT_Encode4(448491), // Rule ID 4819 //
        GIM_CheckRegBankForClass, /*MI*/0, /*Op*/0, /*RC*/GIMT_Encode2(AMDGPU::AV_32RegClassID),
        GIM_CheckConstantInt8, /*MI*/0, /*Op*/3, 0,
        // MIs[0] offset
        GIM_CheckIsImm, /*MI*/0, /*Op*/6,
        // MIs[0] auxiliary
        GIM_CheckIsImm, /*MI*/0, /*Op*/7,
        // MIs[0] Operand 8
        GIM_CheckLiteralInt, /*MI*/0, /*Op*/8, GIMT_Encode8(0),
        GIM_CheckComplexPattern, /*MI*/0, /*Op*/5, /*Renderer*/GIMT_Encode2(0), GIMT_Encode2(GICP_gi_buf_soffset),
        // (SIbuffer_atomic_smax:{ *:[i32] } i32:{ *:[i32] }:$vdata_in, v4i32:{ *:[v4i32] }:$rsrc, 0:{ *:[i32] }, i32:{ *:[i32] }:$voffset, (BUFSOffset:{ *:[i32] } i32:{ *:[i32] }:$soffset), (timm:{ *:[i32] }):$offset, (timm:{ *:[i32] }):$auxiliary, 0:{ *:[i1] })  =>  (BUFFER_ATOMIC_SMAX_VBUFFER_OFFEN_RTN:{ *:[i32] } anonymous_15037:{ *:[i32] }:$vdata_in, VGPR_32:{ *:[i32] }:$voffset, SReg_128:{ *:[v4i32] }:$rsrc, SCSrc_b32:{ *:[i32] }:$soffset, (timm:{ *:[i32] }):$offset, (extract_cpol_set_glc:{ *:[i32] } ?:{ *:[i32] }:$auxiliary))
        GIR_BuildMI, /*InsnID*/0, /*Opcode*/GIMT_Encode2(AMDGPU::BUFFER_ATOMIC_SMAX_VBUFFER_OFFEN_RTN),
        GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/0, // DstI[vdata]
        GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/1, // vdata_in
        GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/4, // voffset
        GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/2, // rsrc
        GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/0, // soffset
        GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/6, // offset
        GIR_CustomOperandRenderer, /*InsnID*/0, /*OldInsnID*/0, /*OpIdx*/7, /*OperandRenderer*/GIMT_Encode2(GICR_renderExtractCpolSetGLC), // auxiliary
        GIR_MergeMemOperands, /*InsnID*/0, /*NumInsns*/1, /*MergeInsnID's*/0,
        GIR_ConstrainSelectedInstOperands, /*InsnID*/0,
        GIR_EraseFromParent, /*InsnID*/0,
        // GIR_Coverage, 4819,
        GIR_Done,
      // Label 6127: @448491
      GIM_Try, /*On fail goto*//*Label 6128*/ GIMT_Encode4(448561), // Rule ID 4814 //
        GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasUnrestrictedSOffset),
        GIM_CheckHasNoUse, /*MI*/0,
        GIM_CheckConstantInt8, /*MI*/0, /*Op*/4, 0,
        // MIs[0] offset
        GIM_CheckIsImm, /*MI*/0, /*Op*/6,
        // MIs[0] auxiliary
        GIM_CheckIsImm, /*MI*/0, /*Op*/7,
        // MIs[0] Operand 8
        GIM_CheckIsImm, /*MI*/0, /*Op*/8,
        GIM_CheckComplexPattern, /*MI*/0, /*Op*/5, /*Renderer*/GIMT_Encode2(0), GIMT_Encode2(GICP_gi_buf_soffset),
        // (SIbuffer_atomic_smax:{ *:[i32] } i32:{ *:[i32] }:$vdata_in, v4i32:{ *:[v4i32] }:$rsrc, i32:{ *:[i32] }:$vindex, 0:{ *:[i32] }, (BUFSOffset:{ *:[i32] } i32:{ *:[i32] }:$soffset), (timm:{ *:[i32] }):$offset, (timm:{ *:[i32] }):$auxiliary, (timm:{ *:[i1] }))<<P:Predicate_SIbuffer_atomic_smax_noret>>  =>  (BUFFER_ATOMIC_SMAX_IDXEN anonymous_15037:{ *:[i32] }:$vdata_in, VGPR_32:{ *:[i32] }:$vindex, SReg_128:{ *:[v4i32] }:$rsrc, SCSrc_b32:{ *:[i32] }:$soffset, (timm:{ *:[i32] }):$offset, (extract_cpol:{ *:[i32] } ?:{ *:[i32] }:$auxiliary))
        GIR_BuildMI, /*InsnID*/0, /*Opcode*/GIMT_Encode2(AMDGPU::BUFFER_ATOMIC_SMAX_IDXEN),
        GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/1, // vdata_in
        GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/3, // vindex
        GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/2, // rsrc
        GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/0, // soffset
        GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/6, // offset
        GIR_CustomOperandRenderer, /*InsnID*/0, /*OldInsnID*/0, /*OpIdx*/7, /*OperandRenderer*/GIMT_Encode2(GICR_renderExtractCPol), // auxiliary
        GIR_MergeMemOperands, /*InsnID*/0, /*NumInsns*/1, /*MergeInsnID's*/0,
        GIR_ConstrainSelectedInstOperands, /*InsnID*/0,
        GIR_EraseFromParent, /*InsnID*/0,
        // GIR_Coverage, 4814,
        GIR_Done,
      // Label 6128: @448561
      GIM_Try, /*On fail goto*//*Label 6129*/ GIMT_Encode4(448628), // Rule ID 4822 //
        GIM_CheckHasNoUse, /*MI*/0,
        GIM_CheckConstantInt8, /*MI*/0, /*Op*/4, 0,
        // MIs[0] offset
        GIM_CheckIsImm, /*MI*/0, /*Op*/6,
        // MIs[0] auxiliary
        GIM_CheckIsImm, /*MI*/0, /*Op*/7,
        // MIs[0] Operand 8
        GIM_CheckIsImm, /*MI*/0, /*Op*/8,
        GIM_CheckComplexPattern, /*MI*/0, /*Op*/5, /*Renderer*/GIMT_Encode2(0), GIMT_Encode2(GICP_gi_buf_soffset),
        // (SIbuffer_atomic_smax:{ *:[i32] } i32:{ *:[i32] }:$vdata_in, v4i32:{ *:[v4i32] }:$rsrc, i32:{ *:[i32] }:$vindex, 0:{ *:[i32] }, (BUFSOffset:{ *:[i32] } i32:{ *:[i32] }:$soffset), (timm:{ *:[i32] }):$offset, (timm:{ *:[i32] }):$auxiliary, (timm:{ *:[i1] }))<<P:Predicate_SIbuffer_atomic_smax_noret>>  =>  (BUFFER_ATOMIC_SMAX_VBUFFER_IDXEN anonymous_15037:{ *:[i32] }:$vdata_in, VGPR_32:{ *:[i32] }:$vindex, SReg_128:{ *:[v4i32] }:$rsrc, SCSrc_b32:{ *:[i32] }:$soffset, (timm:{ *:[i32] }):$offset, (extract_cpol:{ *:[i32] } ?:{ *:[i32] }:$auxiliary))
        GIR_BuildMI, /*InsnID*/0, /*Opcode*/GIMT_Encode2(AMDGPU::BUFFER_ATOMIC_SMAX_VBUFFER_IDXEN),
        GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/1, // vdata_in
        GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/3, // vindex
        GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/2, // rsrc
        GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/0, // soffset
        GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/6, // offset
        GIR_CustomOperandRenderer, /*InsnID*/0, /*OldInsnID*/0, /*OpIdx*/7, /*OperandRenderer*/GIMT_Encode2(GICR_renderExtractCPol), // auxiliary
        GIR_MergeMemOperands, /*InsnID*/0, /*NumInsns*/1, /*MergeInsnID's*/0,
        GIR_ConstrainSelectedInstOperands, /*InsnID*/0,
        GIR_EraseFromParent, /*InsnID*/0,
        // GIR_Coverage, 4822,
        GIR_Done,
      // Label 6129: @448628
      GIM_Try, /*On fail goto*//*Label 6130*/ GIMT_Encode4(448705), // Rule ID 4810 //
        GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasUnrestrictedSOffset),
        GIM_CheckRegBankForClass, /*MI*/0, /*Op*/0, /*RC*/GIMT_Encode2(AMDGPU::AV_32RegClassID),
        GIM_CheckConstantInt8, /*MI*/0, /*Op*/4, 0,
        // MIs[0] offset
        GIM_CheckIsImm, /*MI*/0, /*Op*/6,
        // MIs[0] auxiliary
        GIM_CheckIsImm, /*MI*/0, /*Op*/7,
        // MIs[0] Operand 8
        GIM_CheckIsImm, /*MI*/0, /*Op*/8,
        GIM_CheckComplexPattern, /*MI*/0, /*Op*/5, /*Renderer*/GIMT_Encode2(0), GIMT_Encode2(GICP_gi_buf_soffset),
        // (SIbuffer_atomic_smax:{ *:[i32] } i32:{ *:[i32] }:$vdata_in, v4i32:{ *:[v4i32] }:$rsrc, i32:{ *:[i32] }:$vindex, 0:{ *:[i32] }, (BUFSOffset:{ *:[i32] } i32:{ *:[i32] }:$soffset), (timm:{ *:[i32] }):$offset, (timm:{ *:[i32] }):$auxiliary, (timm:{ *:[i1] }))  =>  (BUFFER_ATOMIC_SMAX_IDXEN_RTN:{ *:[i32] } anonymous_15037:{ *:[i32] }:$vdata_in, VGPR_32:{ *:[i32] }:$vindex, SReg_128:{ *:[v4i32] }:$rsrc, SCSrc_b32:{ *:[i32] }:$soffset, (timm:{ *:[i32] }):$offset, (extract_cpol_set_glc:{ *:[i32] } ?:{ *:[i32] }:$auxiliary))
        GIR_BuildMI, /*InsnID*/0, /*Opcode*/GIMT_Encode2(AMDGPU::BUFFER_ATOMIC_SMAX_IDXEN_RTN),
        GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/0, // DstI[vdata]
        GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/1, // vdata_in
        GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/3, // vindex
        GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/2, // rsrc
        GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/0, // soffset
        GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/6, // offset
        GIR_CustomOperandRenderer, /*InsnID*/0, /*OldInsnID*/0, /*OpIdx*/7, /*OperandRenderer*/GIMT_Encode2(GICR_renderExtractCpolSetGLC), // auxiliary
        GIR_MergeMemOperands, /*InsnID*/0, /*NumInsns*/1, /*MergeInsnID's*/0,
        GIR_ConstrainSelectedInstOperands, /*InsnID*/0,
        GIR_EraseFromParent, /*InsnID*/0,
        // GIR_Coverage, 4810,
        GIR_Done,
      // Label 6130: @448705
      GIM_Try, /*On fail goto*//*Label 6131*/ GIMT_Encode4(448779), // Rule ID 4818 //
        GIM_CheckRegBankForClass, /*MI*/0, /*Op*/0, /*RC*/GIMT_Encode2(AMDGPU::AV_32RegClassID),
        GIM_CheckConstantInt8, /*MI*/0, /*Op*/4, 0,
        // MIs[0] offset
        GIM_CheckIsImm, /*MI*/0, /*Op*/6,
        // MIs[0] auxiliary
        GIM_CheckIsImm, /*MI*/0, /*Op*/7,
        // MIs[0] Operand 8
        GIM_CheckIsImm, /*MI*/0, /*Op*/8,
        GIM_CheckComplexPattern, /*MI*/0, /*Op*/5, /*Renderer*/GIMT_Encode2(0), GIMT_Encode2(GICP_gi_buf_soffset),
        // (SIbuffer_atomic_smax:{ *:[i32] } i32:{ *:[i32] }:$vdata_in, v4i32:{ *:[v4i32] }:$rsrc, i32:{ *:[i32] }:$vindex, 0:{ *:[i32] }, (BUFSOffset:{ *:[i32] } i32:{ *:[i32] }:$soffset), (timm:{ *:[i32] }):$offset, (timm:{ *:[i32] }):$auxiliary, (timm:{ *:[i1] }))  =>  (BUFFER_ATOMIC_SMAX_VBUFFER_IDXEN_RTN:{ *:[i32] } anonymous_15037:{ *:[i32] }:$vdata_in, VGPR_32:{ *:[i32] }:$vindex, SReg_128:{ *:[v4i32] }:$rsrc, SCSrc_b32:{ *:[i32] }:$soffset, (timm:{ *:[i32] }):$offset, (extract_cpol_set_glc:{ *:[i32] } ?:{ *:[i32] }:$auxiliary))
        GIR_BuildMI, /*InsnID*/0, /*Opcode*/GIMT_Encode2(AMDGPU::BUFFER_ATOMIC_SMAX_VBUFFER_IDXEN_RTN),
        GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/0, // DstI[vdata]
        GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/1, // vdata_in
        GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/3, // vindex
        GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/2, // rsrc
        GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/0, // soffset
        GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/6, // offset
        GIR_CustomOperandRenderer, /*InsnID*/0, /*OldInsnID*/0, /*OpIdx*/7, /*OperandRenderer*/GIMT_Encode2(GICR_renderExtractCpolSetGLC), // auxiliary
        GIR_MergeMemOperands, /*InsnID*/0, /*NumInsns*/1, /*MergeInsnID's*/0,
        GIR_ConstrainSelectedInstOperands, /*InsnID*/0,
        GIR_EraseFromParent, /*InsnID*/0,
        // GIR_Coverage, 4818,
        GIR_Done,
      // Label 6131: @448779
      GIM_Try, /*On fail goto*//*Label 6132*/ GIMT_Encode4(448885), // Rule ID 4816 //
        GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasUnrestrictedSOffset),
        GIM_CheckHasNoUse, /*MI*/0,
        // MIs[0] offset
        GIM_CheckIsImm, /*MI*/0, /*Op*/6,
        // MIs[0] auxiliary
        GIM_CheckIsImm, /*MI*/0, /*Op*/7,
        // MIs[0] Operand 8
        GIM_CheckIsImm, /*MI*/0, /*Op*/8,
        GIM_CheckComplexPattern, /*MI*/0, /*Op*/5, /*Renderer*/GIMT_Encode2(0), GIMT_Encode2(GICP_gi_buf_soffset),
        // (SIbuffer_atomic_smax:{ *:[i32] } i32:{ *:[i32] }:$vdata_in, v4i32:{ *:[v4i32] }:$rsrc, i32:{ *:[i32] }:$vindex, i32:{ *:[i32] }:$voffset, (BUFSOffset:{ *:[i32] } i32:{ *:[i32] }:$soffset), (timm:{ *:[i32] }):$offset, (timm:{ *:[i32] }):$auxiliary, (timm:{ *:[i1] }))<<P:Predicate_SIbuffer_atomic_smax_noret>>  =>  (BUFFER_ATOMIC_SMAX_BOTHEN anonymous_15037:{ *:[i32] }:$vdata_in, (REG_SEQUENCE:{ *:[i64] } VReg_64:{ *:[i32] }, VGPR_32:{ *:[i32] }:$vindex, sub0:{ *:[i32] }, VGPR_32:{ *:[i32] }:$voffset, sub1:{ *:[i32] }), SReg_128:{ *:[v4i32] }:$rsrc, SCSrc_b32:{ *:[i32] }:$soffset, (timm:{ *:[i32] }):$offset, (extract_cpol:{ *:[i32] } ?:{ *:[i32] }:$auxiliary))
        GIR_MakeTempReg, /*TempRegID*/0, /*TypeID*/GILLT_s64,
        GIR_BuildMI, /*InsnID*/1, /*Opcode*/GIMT_Encode2(TargetOpcode::REG_SEQUENCE),
        GIR_AddTempRegister, /*InsnID*/1, /*TempRegID*/0, /*TempRegFlags*/GIMT_Encode2(RegState::Define),
        GIR_Copy, /*NewInsnID*/1, /*OldInsnID*/0, /*OpIdx*/3, // vindex
        GIR_AddImm8, /*InsnID*/1, /*SubRegIndex*/3,
        GIR_Copy, /*NewInsnID*/1, /*OldInsnID*/0, /*OpIdx*/4, // voffset
        GIR_AddImm8, /*InsnID*/1, /*SubRegIndex*/11,
        GIR_ConstrainOperandRC, /*InsnID*/1, /*Op*/0, GIMT_Encode2(AMDGPU::VReg_64RegClassID),
        GIR_ConstrainOperandRC, /*InsnID*/1, /*Op*/1, GIMT_Encode2(AMDGPU::VGPR_32RegClassID),
        GIR_ConstrainOperandRC, /*InsnID*/1, /*Op*/3, GIMT_Encode2(AMDGPU::VGPR_32RegClassID),
        GIR_BuildMI, /*InsnID*/0, /*Opcode*/GIMT_Encode2(AMDGPU::BUFFER_ATOMIC_SMAX_BOTHEN),
        GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/1, // vdata_in
        GIR_AddSimpleTempRegister, /*InsnID*/0, /*TempRegID*/0,
        GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/2, // rsrc
        GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/0, // soffset
        GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/6, // offset
        GIR_CustomOperandRenderer, /*InsnID*/0, /*OldInsnID*/0, /*OpIdx*/7, /*OperandRenderer*/GIMT_Encode2(GICR_renderExtractCPol), // auxiliary
        GIR_MergeMemOperands, /*InsnID*/0, /*NumInsns*/1, /*MergeInsnID's*/0,
        GIR_ConstrainSelectedInstOperands, /*InsnID*/0,
        GIR_EraseFromParent, /*InsnID*/0,
        // GIR_Coverage, 4816,
        GIR_Done,
      // Label 6132: @448885
      GIM_Try, /*On fail goto*//*Label 6133*/ GIMT_Encode4(448988), // Rule ID 4824 //
        GIM_CheckHasNoUse, /*MI*/0,
        // MIs[0] offset
        GIM_CheckIsImm, /*MI*/0, /*Op*/6,
        // MIs[0] auxiliary
        GIM_CheckIsImm, /*MI*/0, /*Op*/7,
        // MIs[0] Operand 8
        GIM_CheckIsImm, /*MI*/0, /*Op*/8,
        GIM_CheckComplexPattern, /*MI*/0, /*Op*/5, /*Renderer*/GIMT_Encode2(0), GIMT_Encode2(GICP_gi_buf_soffset),
        // (SIbuffer_atomic_smax:{ *:[i32] } i32:{ *:[i32] }:$vdata_in, v4i32:{ *:[v4i32] }:$rsrc, i32:{ *:[i32] }:$vindex, i32:{ *:[i32] }:$voffset, (BUFSOffset:{ *:[i32] } i32:{ *:[i32] }:$soffset), (timm:{ *:[i32] }):$offset, (timm:{ *:[i32] }):$auxiliary, (timm:{ *:[i1] }))<<P:Predicate_SIbuffer_atomic_smax_noret>>  =>  (BUFFER_ATOMIC_SMAX_VBUFFER_BOTHEN anonymous_15037:{ *:[i32] }:$vdata_in, (REG_SEQUENCE:{ *:[i64] } VReg_64:{ *:[i32] }, VGPR_32:{ *:[i32] }:$vindex, sub0:{ *:[i32] }, VGPR_32:{ *:[i32] }:$voffset, sub1:{ *:[i32] }), SReg_128:{ *:[v4i32] }:$rsrc, SCSrc_b32:{ *:[i32] }:$soffset, (timm:{ *:[i32] }):$offset, (extract_cpol:{ *:[i32] } ?:{ *:[i32] }:$auxiliary))
        GIR_MakeTempReg, /*TempRegID*/0, /*TypeID*/GILLT_s64,
        GIR_BuildMI, /*InsnID*/1, /*Opcode*/GIMT_Encode2(TargetOpcode::REG_SEQUENCE),
        GIR_AddTempRegister, /*InsnID*/1, /*TempRegID*/0, /*TempRegFlags*/GIMT_Encode2(RegState::Define),
        GIR_Copy, /*NewInsnID*/1, /*OldInsnID*/0, /*OpIdx*/3, // vindex
        GIR_AddImm8, /*InsnID*/1, /*SubRegIndex*/3,
        GIR_Copy, /*NewInsnID*/1, /*OldInsnID*/0, /*OpIdx*/4, // voffset
        GIR_AddImm8, /*InsnID*/1, /*SubRegIndex*/11,
        GIR_ConstrainOperandRC, /*InsnID*/1, /*Op*/0, GIMT_Encode2(AMDGPU::VReg_64RegClassID),
        GIR_ConstrainOperandRC, /*InsnID*/1, /*Op*/1, GIMT_Encode2(AMDGPU::VGPR_32RegClassID),
        GIR_ConstrainOperandRC, /*InsnID*/1, /*Op*/3, GIMT_Encode2(AMDGPU::VGPR_32RegClassID),
        GIR_BuildMI, /*InsnID*/0, /*Opcode*/GIMT_Encode2(AMDGPU::BUFFER_ATOMIC_SMAX_VBUFFER_BOTHEN),
        GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/1, // vdata_in
        GIR_AddSimpleTempRegister, /*InsnID*/0, /*TempRegID*/0,
        GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/2, // rsrc
        GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/0, // soffset
        GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/6, // offset
        GIR_CustomOperandRenderer, /*InsnID*/0, /*OldInsnID*/0, /*OpIdx*/7, /*OperandRenderer*/GIMT_Encode2(GICR_renderExtractCPol), // auxiliary
        GIR_MergeMemOperands, /*InsnID*/0, /*NumInsns*/1, /*MergeInsnID's*/0,
        GIR_ConstrainSelectedInstOperands, /*InsnID*/0,
        GIR_EraseFromParent, /*InsnID*/0,
        // GIR_Coverage, 4824,
        GIR_Done,
      // Label 6133: @448988
      GIM_Try, /*On fail goto*//*Label 6134*/ GIMT_Encode4(449101), // Rule ID 4812 //
        GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasUnrestrictedSOffset),
        GIM_CheckRegBankForClass, /*MI*/0, /*Op*/0, /*RC*/GIMT_Encode2(AMDGPU::AV_32RegClassID),
        // MIs[0] offset
        GIM_CheckIsImm, /*MI*/0, /*Op*/6,
        // MIs[0] auxiliary
        GIM_CheckIsImm, /*MI*/0, /*Op*/7,
        // MIs[0] Operand 8
        GIM_CheckIsImm, /*MI*/0, /*Op*/8,
        GIM_CheckComplexPattern, /*MI*/0, /*Op*/5, /*Renderer*/GIMT_Encode2(0), GIMT_Encode2(GICP_gi_buf_soffset),
        // (SIbuffer_atomic_smax:{ *:[i32] } i32:{ *:[i32] }:$vdata_in, v4i32:{ *:[v4i32] }:$rsrc, i32:{ *:[i32] }:$vindex, i32:{ *:[i32] }:$voffset, (BUFSOffset:{ *:[i32] } i32:{ *:[i32] }:$soffset), (timm:{ *:[i32] }):$offset, (timm:{ *:[i32] }):$auxiliary, (timm:{ *:[i1] }))  =>  (BUFFER_ATOMIC_SMAX_BOTHEN_RTN:{ *:[i32] } anonymous_15037:{ *:[i32] }:$vdata_in, (REG_SEQUENCE:{ *:[i64] } VReg_64:{ *:[i32] }, VGPR_32:{ *:[i32] }:$vindex, sub0:{ *:[i32] }, VGPR_32:{ *:[i32] }:$voffset, sub1:{ *:[i32] }), SReg_128:{ *:[v4i32] }:$rsrc, SCSrc_b32:{ *:[i32] }:$soffset, (timm:{ *:[i32] }):$offset, (extract_cpol_set_glc:{ *:[i32] } ?:{ *:[i32] }:$auxiliary))
        GIR_MakeTempReg, /*TempRegID*/0, /*TypeID*/GILLT_s64,
        GIR_BuildMI, /*InsnID*/1, /*Opcode*/GIMT_Encode2(TargetOpcode::REG_SEQUENCE),
        GIR_AddTempRegister, /*InsnID*/1, /*TempRegID*/0, /*TempRegFlags*/GIMT_Encode2(RegState::Define),
        GIR_Copy, /*NewInsnID*/1, /*OldInsnID*/0, /*OpIdx*/3, // vindex
        GIR_AddImm8, /*InsnID*/1, /*SubRegIndex*/3,
        GIR_Copy, /*NewInsnID*/1, /*OldInsnID*/0, /*OpIdx*/4, // voffset
        GIR_AddImm8, /*InsnID*/1, /*SubRegIndex*/11,
        GIR_ConstrainOperandRC, /*InsnID*/1, /*Op*/0, GIMT_Encode2(AMDGPU::VReg_64RegClassID),
        GIR_ConstrainOperandRC, /*InsnID*/1, /*Op*/1, GIMT_Encode2(AMDGPU::VGPR_32RegClassID),
        GIR_ConstrainOperandRC, /*InsnID*/1, /*Op*/3, GIMT_Encode2(AMDGPU::VGPR_32RegClassID),
        GIR_BuildMI, /*InsnID*/0, /*Opcode*/GIMT_Encode2(AMDGPU::BUFFER_ATOMIC_SMAX_BOTHEN_RTN),
        GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/0, // DstI[vdata]
        GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/1, // vdata_in
        GIR_AddSimpleTempRegister, /*InsnID*/0, /*TempRegID*/0,
        GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/2, // rsrc
        GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/0, // soffset
        GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/6, // offset
        GIR_CustomOperandRenderer, /*InsnID*/0, /*OldInsnID*/0, /*OpIdx*/7, /*OperandRenderer*/GIMT_Encode2(GICR_renderExtractCpolSetGLC), // auxiliary
        GIR_MergeMemOperands, /*InsnID*/0, /*NumInsns*/1, /*MergeInsnID's*/0,
        GIR_ConstrainSelectedInstOperands, /*InsnID*/0,
        GIR_EraseFromParent, /*InsnID*/0,
        // GIR_Coverage, 4812,
        GIR_Done,
      // Label 6134: @449101
      GIM_Try, /*On fail goto*//*Label 6135*/ GIMT_Encode4(449211), // Rule ID 4820 //
        GIM_CheckRegBankForClass, /*MI*/0, /*Op*/0, /*RC*/GIMT_Encode2(AMDGPU::AV_32RegClassID),
        // MIs[0] offset
        GIM_CheckIsImm, /*MI*/0, /*Op*/6,
        // MIs[0] auxiliary
        GIM_CheckIsImm, /*MI*/0, /*Op*/7,
        // MIs[0] Operand 8
        GIM_CheckIsImm, /*MI*/0, /*Op*/8,
        GIM_CheckComplexPattern, /*MI*/0, /*Op*/5, /*Renderer*/GIMT_Encode2(0), GIMT_Encode2(GICP_gi_buf_soffset),
        // (SIbuffer_atomic_smax:{ *:[i32] } i32:{ *:[i32] }:$vdata_in, v4i32:{ *:[v4i32] }:$rsrc, i32:{ *:[i32] }:$vindex, i32:{ *:[i32] }:$voffset, (BUFSOffset:{ *:[i32] } i32:{ *:[i32] }:$soffset), (timm:{ *:[i32] }):$offset, (timm:{ *:[i32] }):$auxiliary, (timm:{ *:[i1] }))  =>  (BUFFER_ATOMIC_SMAX_VBUFFER_BOTHEN_RTN:{ *:[i32] } anonymous_15037:{ *:[i32] }:$vdata_in, (REG_SEQUENCE:{ *:[i64] } VReg_64:{ *:[i32] }, VGPR_32:{ *:[i32] }:$vindex, sub0:{ *:[i32] }, VGPR_32:{ *:[i32] }:$voffset, sub1:{ *:[i32] }), SReg_128:{ *:[v4i32] }:$rsrc, SCSrc_b32:{ *:[i32] }:$soffset, (timm:{ *:[i32] }):$offset, (extract_cpol_set_glc:{ *:[i32] } ?:{ *:[i32] }:$auxiliary))
        GIR_MakeTempReg, /*TempRegID*/0, /*TypeID*/GILLT_s64,
        GIR_BuildMI, /*InsnID*/1, /*Opcode*/GIMT_Encode2(TargetOpcode::REG_SEQUENCE),
        GIR_AddTempRegister, /*InsnID*/1, /*TempRegID*/0, /*TempRegFlags*/GIMT_Encode2(RegState::Define),
        GIR_Copy, /*NewInsnID*/1, /*OldInsnID*/0, /*OpIdx*/3, // vindex
        GIR_AddImm8, /*InsnID*/1, /*SubRegIndex*/3,
        GIR_Copy, /*NewInsnID*/1, /*OldInsnID*/0, /*OpIdx*/4, // voffset
        GIR_AddImm8, /*InsnID*/1, /*SubRegIndex*/11,
        GIR_ConstrainOperandRC, /*InsnID*/1, /*Op*/0, GIMT_Encode2(AMDGPU::VReg_64RegClassID),
        GIR_ConstrainOperandRC, /*InsnID*/1, /*Op*/1, GIMT_Encode2(AMDGPU::VGPR_32RegClassID),
        GIR_ConstrainOperandRC, /*InsnID*/1, /*Op*/3, GIMT_Encode2(AMDGPU::VGPR_32RegClassID),
        GIR_BuildMI, /*InsnID*/0, /*Opcode*/GIMT_Encode2(AMDGPU::BUFFER_ATOMIC_SMAX_VBUFFER_BOTHEN_RTN),
        GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/0, // DstI[vdata]
        GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/1, // vdata_in
        GIR_AddSimpleTempRegister, /*InsnID*/0, /*TempRegID*/0,
        GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/2, // rsrc
        GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/0, // soffset
        GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/6, // offset
        GIR_CustomOperandRenderer, /*InsnID*/0, /*OldInsnID*/0, /*OpIdx*/7, /*OperandRenderer*/GIMT_Encode2(GICR_renderExtractCpolSetGLC), // auxiliary
        GIR_MergeMemOperands, /*InsnID*/0, /*NumInsns*/1, /*MergeInsnID's*/0,
        GIR_ConstrainSelectedInstOperands, /*InsnID*/0,
        GIR_EraseFromParent, /*InsnID*/0,
        // GIR_Coverage, 4820,
        GIR_Done,
      // Label 6135: @449211
      GIM_Reject,
    // Label 6119: @449212
    GIM_Reject,
    // Label 6117: @449213
    GIM_Try, /*On fail goto*//*Label 6136*/ GIMT_Encode4(450599),
      GIM_CheckType, /*MI*/0, /*Op*/1, /*Type*/GILLT_s64,
      GIM_CheckType, /*MI*/0, /*Op*/2, /*Type*/GILLT_v4s32,
      GIM_CheckType, /*MI*/0, /*Op*/3, /*Type*/GILLT_s32,
      GIM_CheckType, /*MI*/0, /*Op*/4, /*Type*/GILLT_s32,
      GIM_CheckType, /*MI*/0, /*Op*/5, /*Type*/GILLT_s32,
      GIM_Try, /*On fail goto*//*Label 6137*/ GIMT_Encode4(449316), // Rule ID 5013 //
        GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasUnrestrictedSOffset),
        GIM_CheckHasNoUse, /*MI*/0,
        GIM_CheckConstantInt8, /*MI*/0, /*Op*/3, 0,
        GIM_CheckConstantInt8, /*MI*/0, /*Op*/4, 0,
        // MIs[0] offset
        GIM_CheckIsImm, /*MI*/0, /*Op*/6,
        // MIs[0] auxiliary
        GIM_CheckIsImm, /*MI*/0, /*Op*/7,
        // MIs[0] Operand 8
        GIM_CheckLiteralInt, /*MI*/0, /*Op*/8, GIMT_Encode8(0),
        GIM_CheckComplexPattern, /*MI*/0, /*Op*/5, /*Renderer*/GIMT_Encode2(0), GIMT_Encode2(GICP_gi_buf_soffset),
        // (SIbuffer_atomic_smax:{ *:[i64] } i64:{ *:[i64] }:$vdata_in, v4i32:{ *:[v4i32] }:$rsrc, 0:{ *:[i32] }, 0:{ *:[i32] }, (BUFSOffset:{ *:[i32] } i32:{ *:[i32] }:$soffset), (timm:{ *:[i32] }):$offset, (timm:{ *:[i32] }):$auxiliary, 0:{ *:[i1] })<<P:Predicate_SIbuffer_atomic_smax_noret>>  =>  (BUFFER_ATOMIC_SMAX_X2_OFFSET anonymous_15036:{ *:[i64] }:$vdata_in, SReg_128:{ *:[v4i32] }:$rsrc, SCSrc_b32:{ *:[i32] }:$soffset, (timm:{ *:[i32] }):$offset, (extract_cpol:{ *:[i32] } ?:{ *:[i32] }:$auxiliary))
        GIR_BuildMI, /*InsnID*/0, /*Opcode*/GIMT_Encode2(AMDGPU::BUFFER_ATOMIC_SMAX_X2_OFFSET),
        GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/1, // vdata_in
        GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/2, // rsrc
        GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/0, // soffset
        GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/6, // offset
        GIR_CustomOperandRenderer, /*InsnID*/0, /*OldInsnID*/0, /*OpIdx*/7, /*OperandRenderer*/GIMT_Encode2(GICR_renderExtractCPol), // auxiliary
        GIR_MergeMemOperands, /*InsnID*/0, /*NumInsns*/1, /*MergeInsnID's*/0,
        GIR_ConstrainSelectedInstOperands, /*InsnID*/0,
        GIR_EraseFromParent, /*InsnID*/0,
        // GIR_Coverage, 5013,
        GIR_Done,
      // Label 6137: @449316
      GIM_Try, /*On fail goto*//*Label 6138*/ GIMT_Encode4(449391), // Rule ID 5021 //
        GIM_CheckHasNoUse, /*MI*/0,
        GIM_CheckConstantInt8, /*MI*/0, /*Op*/3, 0,
        GIM_CheckConstantInt8, /*MI*/0, /*Op*/4, 0,
        // MIs[0] offset
        GIM_CheckIsImm, /*MI*/0, /*Op*/6,
        // MIs[0] auxiliary
        GIM_CheckIsImm, /*MI*/0, /*Op*/7,
        // MIs[0] Operand 8
        GIM_CheckLiteralInt, /*MI*/0, /*Op*/8, GIMT_Encode8(0),
        GIM_CheckComplexPattern, /*MI*/0, /*Op*/5, /*Renderer*/GIMT_Encode2(0), GIMT_Encode2(GICP_gi_buf_soffset),
        // (SIbuffer_atomic_smax:{ *:[i64] } i64:{ *:[i64] }:$vdata_in, v4i32:{ *:[v4i32] }:$rsrc, 0:{ *:[i32] }, 0:{ *:[i32] }, (BUFSOffset:{ *:[i32] } i32:{ *:[i32] }:$soffset), (timm:{ *:[i32] }):$offset, (timm:{ *:[i32] }):$auxiliary, 0:{ *:[i1] })<<P:Predicate_SIbuffer_atomic_smax_noret>>  =>  (BUFFER_ATOMIC_SMAX_X2_VBUFFER_OFFSET anonymous_15036:{ *:[i64] }:$vdata_in, SReg_128:{ *:[v4i32] }:$rsrc, SCSrc_b32:{ *:[i32] }:$soffset, (timm:{ *:[i32] }):$offset, (extract_cpol:{ *:[i32] } ?:{ *:[i32] }:$auxiliary))
        GIR_BuildMI, /*InsnID*/0, /*Opcode*/GIMT_Encode2(AMDGPU::BUFFER_ATOMIC_SMAX_X2_VBUFFER_OFFSET),
        GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/1, // vdata_in
        GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/2, // rsrc
        GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/0, // soffset
        GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/6, // offset
        GIR_CustomOperandRenderer, /*InsnID*/0, /*OldInsnID*/0, /*OpIdx*/7, /*OperandRenderer*/GIMT_Encode2(GICR_renderExtractCPol), // auxiliary
        GIR_MergeMemOperands, /*InsnID*/0, /*NumInsns*/1, /*MergeInsnID's*/0,
        GIR_ConstrainSelectedInstOperands, /*InsnID*/0,
        GIR_EraseFromParent, /*InsnID*/0,
        // GIR_Coverage, 5021,
        GIR_Done,
      // Label 6138: @449391
      GIM_Try, /*On fail goto*//*Label 6139*/ GIMT_Encode4(449476), // Rule ID 5009 //
        GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasUnrestrictedSOffset),
        GIM_CheckRegBankForClass, /*MI*/0, /*Op*/0, /*RC*/GIMT_Encode2(AMDGPU::AV_64RegClassID),
        GIM_CheckConstantInt8, /*MI*/0, /*Op*/3, 0,
        GIM_CheckConstantInt8, /*MI*/0, /*Op*/4, 0,
        // MIs[0] offset
        GIM_CheckIsImm, /*MI*/0, /*Op*/6,
        // MIs[0] auxiliary
        GIM_CheckIsImm, /*MI*/0, /*Op*/7,
        // MIs[0] Operand 8
        GIM_CheckLiteralInt, /*MI*/0, /*Op*/8, GIMT_Encode8(0),
        GIM_CheckComplexPattern, /*MI*/0, /*Op*/5, /*Renderer*/GIMT_Encode2(0), GIMT_Encode2(GICP_gi_buf_soffset),
        // (SIbuffer_atomic_smax:{ *:[i64] } i64:{ *:[i64] }:$vdata_in, v4i32:{ *:[v4i32] }:$rsrc, 0:{ *:[i32] }, 0:{ *:[i32] }, (BUFSOffset:{ *:[i32] } i32:{ *:[i32] }:$soffset), (timm:{ *:[i32] }):$offset, (timm:{ *:[i32] }):$auxiliary, 0:{ *:[i1] })  =>  (BUFFER_ATOMIC_SMAX_X2_OFFSET_RTN:{ *:[i64] } anonymous_15036:{ *:[i64] }:$vdata_in, SReg_128:{ *:[v4i32] }:$rsrc, SCSrc_b32:{ *:[i32] }:$soffset, (timm:{ *:[i32] }):$offset, (extract_cpol_set_glc:{ *:[i32] } ?:{ *:[i32] }:$auxiliary))
        GIR_BuildMI, /*InsnID*/0, /*Opcode*/GIMT_Encode2(AMDGPU::BUFFER_ATOMIC_SMAX_X2_OFFSET_RTN),
        GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/0, // DstI[vdata]
        GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/1, // vdata_in
        GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/2, // rsrc
        GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/0, // soffset
        GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/6, // offset
        GIR_CustomOperandRenderer, /*InsnID*/0, /*OldInsnID*/0, /*OpIdx*/7, /*OperandRenderer*/GIMT_Encode2(GICR_renderExtractCpolSetGLC), // auxiliary
        GIR_MergeMemOperands, /*InsnID*/0, /*NumInsns*/1, /*MergeInsnID's*/0,
        GIR_ConstrainSelectedInstOperands, /*InsnID*/0,
        GIR_EraseFromParent, /*InsnID*/0,
        // GIR_Coverage, 5009,
        GIR_Done,
      // Label 6139: @449476
      GIM_Try, /*On fail goto*//*Label 6140*/ GIMT_Encode4(449558), // Rule ID 5017 //
        GIM_CheckRegBankForClass, /*MI*/0, /*Op*/0, /*RC*/GIMT_Encode2(AMDGPU::AV_64RegClassID),
        GIM_CheckConstantInt8, /*MI*/0, /*Op*/3, 0,
        GIM_CheckConstantInt8, /*MI*/0, /*Op*/4, 0,
        // MIs[0] offset
        GIM_CheckIsImm, /*MI*/0, /*Op*/6,
        // MIs[0] auxiliary
        GIM_CheckIsImm, /*MI*/0, /*Op*/7,
        // MIs[0] Operand 8
        GIM_CheckLiteralInt, /*MI*/0, /*Op*/8, GIMT_Encode8(0),
        GIM_CheckComplexPattern, /*MI*/0, /*Op*/5, /*Renderer*/GIMT_Encode2(0), GIMT_Encode2(GICP_gi_buf_soffset),
        // (SIbuffer_atomic_smax:{ *:[i64] } i64:{ *:[i64] }:$vdata_in, v4i32:{ *:[v4i32] }:$rsrc, 0:{ *:[i32] }, 0:{ *:[i32] }, (BUFSOffset:{ *:[i32] } i32:{ *:[i32] }:$soffset), (timm:{ *:[i32] }):$offset, (timm:{ *:[i32] }):$auxiliary, 0:{ *:[i1] })  =>  (BUFFER_ATOMIC_SMAX_X2_VBUFFER_OFFSET_RTN:{ *:[i64] } anonymous_15036:{ *:[i64] }:$vdata_in, SReg_128:{ *:[v4i32] }:$rsrc, SCSrc_b32:{ *:[i32] }:$soffset, (timm:{ *:[i32] }):$offset, (extract_cpol_set_glc:{ *:[i32] } ?:{ *:[i32] }:$auxiliary))
        GIR_BuildMI, /*InsnID*/0, /*Opcode*/GIMT_Encode2(AMDGPU::BUFFER_ATOMIC_SMAX_X2_VBUFFER_OFFSET_RTN),
        GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/0, // DstI[vdata]
        GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/1, // vdata_in
        GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/2, // rsrc
        GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/0, // soffset
        GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/6, // offset
        GIR_CustomOperandRenderer, /*InsnID*/0, /*OldInsnID*/0, /*OpIdx*/7, /*OperandRenderer*/GIMT_Encode2(GICR_renderExtractCpolSetGLC), // auxiliary
        GIR_MergeMemOperands, /*InsnID*/0, /*NumInsns*/1, /*MergeInsnID's*/0,
        GIR_ConstrainSelectedInstOperands, /*InsnID*/0,
        GIR_EraseFromParent, /*InsnID*/0,
        // GIR_Coverage, 5017,
        GIR_Done,
      // Label 6140: @449558
      GIM_Try, /*On fail goto*//*Label 6141*/ GIMT_Encode4(449636), // Rule ID 5015 //
        GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasUnrestrictedSOffset),
        GIM_CheckHasNoUse, /*MI*/0,
        GIM_CheckConstantInt8, /*MI*/0, /*Op*/3, 0,
        // MIs[0] offset
        GIM_CheckIsImm, /*MI*/0, /*Op*/6,
        // MIs[0] auxiliary
        GIM_CheckIsImm, /*MI*/0, /*Op*/7,
        // MIs[0] Operand 8
        GIM_CheckLiteralInt, /*MI*/0, /*Op*/8, GIMT_Encode8(0),
        GIM_CheckComplexPattern, /*MI*/0, /*Op*/5, /*Renderer*/GIMT_Encode2(0), GIMT_Encode2(GICP_gi_buf_soffset),
        // (SIbuffer_atomic_smax:{ *:[i64] } i64:{ *:[i64] }:$vdata_in, v4i32:{ *:[v4i32] }:$rsrc, 0:{ *:[i32] }, i32:{ *:[i32] }:$voffset, (BUFSOffset:{ *:[i32] } i32:{ *:[i32] }:$soffset), (timm:{ *:[i32] }):$offset, (timm:{ *:[i32] }):$auxiliary, 0:{ *:[i1] })<<P:Predicate_SIbuffer_atomic_smax_noret>>  =>  (BUFFER_ATOMIC_SMAX_X2_OFFEN anonymous_15036:{ *:[i64] }:$vdata_in, VGPR_32:{ *:[i32] }:$voffset, SReg_128:{ *:[v4i32] }:$rsrc, SCSrc_b32:{ *:[i32] }:$soffset, (timm:{ *:[i32] }):$offset, (extract_cpol:{ *:[i32] } ?:{ *:[i32] }:$auxiliary))
        GIR_BuildMI, /*InsnID*/0, /*Opcode*/GIMT_Encode2(AMDGPU::BUFFER_ATOMIC_SMAX_X2_OFFEN),
        GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/1, // vdata_in
        GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/4, // voffset
        GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/2, // rsrc
        GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/0, // soffset
        GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/6, // offset
        GIR_CustomOperandRenderer, /*InsnID*/0, /*OldInsnID*/0, /*OpIdx*/7, /*OperandRenderer*/GIMT_Encode2(GICR_renderExtractCPol), // auxiliary
        GIR_MergeMemOperands, /*InsnID*/0, /*NumInsns*/1, /*MergeInsnID's*/0,
        GIR_ConstrainSelectedInstOperands, /*InsnID*/0,
        GIR_EraseFromParent, /*InsnID*/0,
        // GIR_Coverage, 5015,
        GIR_Done,
      // Label 6141: @449636
      GIM_Try, /*On fail goto*//*Label 6142*/ GIMT_Encode4(449711), // Rule ID 5023 //
        GIM_CheckHasNoUse, /*MI*/0,
        GIM_CheckConstantInt8, /*MI*/0, /*Op*/3, 0,
        // MIs[0] offset
        GIM_CheckIsImm, /*MI*/0, /*Op*/6,
        // MIs[0] auxiliary
        GIM_CheckIsImm, /*MI*/0, /*Op*/7,
        // MIs[0] Operand 8
        GIM_CheckLiteralInt, /*MI*/0, /*Op*/8, GIMT_Encode8(0),
        GIM_CheckComplexPattern, /*MI*/0, /*Op*/5, /*Renderer*/GIMT_Encode2(0), GIMT_Encode2(GICP_gi_buf_soffset),
        // (SIbuffer_atomic_smax:{ *:[i64] } i64:{ *:[i64] }:$vdata_in, v4i32:{ *:[v4i32] }:$rsrc, 0:{ *:[i32] }, i32:{ *:[i32] }:$voffset, (BUFSOffset:{ *:[i32] } i32:{ *:[i32] }:$soffset), (timm:{ *:[i32] }):$offset, (timm:{ *:[i32] }):$auxiliary, 0:{ *:[i1] })<<P:Predicate_SIbuffer_atomic_smax_noret>>  =>  (BUFFER_ATOMIC_SMAX_X2_VBUFFER_OFFEN anonymous_15036:{ *:[i64] }:$vdata_in, VGPR_32:{ *:[i32] }:$voffset, SReg_128:{ *:[v4i32] }:$rsrc, SCSrc_b32:{ *:[i32] }:$soffset, (timm:{ *:[i32] }):$offset, (extract_cpol:{ *:[i32] } ?:{ *:[i32] }:$auxiliary))
        GIR_BuildMI, /*InsnID*/0, /*Opcode*/GIMT_Encode2(AMDGPU::BUFFER_ATOMIC_SMAX_X2_VBUFFER_OFFEN),
        GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/1, // vdata_in
        GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/4, // voffset
        GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/2, // rsrc
        GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/0, // soffset
        GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/6, // offset
        GIR_CustomOperandRenderer, /*InsnID*/0, /*OldInsnID*/0, /*OpIdx*/7, /*OperandRenderer*/GIMT_Encode2(GICR_renderExtractCPol), // auxiliary
        GIR_MergeMemOperands, /*InsnID*/0, /*NumInsns*/1, /*MergeInsnID's*/0,
        GIR_ConstrainSelectedInstOperands, /*InsnID*/0,
        GIR_EraseFromParent, /*InsnID*/0,
        // GIR_Coverage, 5023,
        GIR_Done,
      // Label 6142: @449711
      GIM_Try, /*On fail goto*//*Label 6143*/ GIMT_Encode4(449796), // Rule ID 5011 //
        GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasUnrestrictedSOffset),
        GIM_CheckRegBankForClass, /*MI*/0, /*Op*/0, /*RC*/GIMT_Encode2(AMDGPU::AV_64RegClassID),
        GIM_CheckConstantInt8, /*MI*/0, /*Op*/3, 0,
        // MIs[0] offset
        GIM_CheckIsImm, /*MI*/0, /*Op*/6,
        // MIs[0] auxiliary
        GIM_CheckIsImm, /*MI*/0, /*Op*/7,
        // MIs[0] Operand 8
        GIM_CheckLiteralInt, /*MI*/0, /*Op*/8, GIMT_Encode8(0),
        GIM_CheckComplexPattern, /*MI*/0, /*Op*/5, /*Renderer*/GIMT_Encode2(0), GIMT_Encode2(GICP_gi_buf_soffset),
        // (SIbuffer_atomic_smax:{ *:[i64] } i64:{ *:[i64] }:$vdata_in, v4i32:{ *:[v4i32] }:$rsrc, 0:{ *:[i32] }, i32:{ *:[i32] }:$voffset, (BUFSOffset:{ *:[i32] } i32:{ *:[i32] }:$soffset), (timm:{ *:[i32] }):$offset, (timm:{ *:[i32] }):$auxiliary, 0:{ *:[i1] })  =>  (BUFFER_ATOMIC_SMAX_X2_OFFEN_RTN:{ *:[i64] } anonymous_15036:{ *:[i64] }:$vdata_in, VGPR_32:{ *:[i32] }:$voffset, SReg_128:{ *:[v4i32] }:$rsrc, SCSrc_b32:{ *:[i32] }:$soffset, (timm:{ *:[i32] }):$offset, (extract_cpol_set_glc:{ *:[i32] } ?:{ *:[i32] }:$auxiliary))
        GIR_BuildMI, /*InsnID*/0, /*Opcode*/GIMT_Encode2(AMDGPU::BUFFER_ATOMIC_SMAX_X2_OFFEN_RTN),
        GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/0, // DstI[vdata]
        GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/1, // vdata_in
        GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/4, // voffset
        GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/2, // rsrc
        GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/0, // soffset
        GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/6, // offset
        GIR_CustomOperandRenderer, /*InsnID*/0, /*OldInsnID*/0, /*OpIdx*/7, /*OperandRenderer*/GIMT_Encode2(GICR_renderExtractCpolSetGLC), // auxiliary
        GIR_MergeMemOperands, /*InsnID*/0, /*NumInsns*/1, /*MergeInsnID's*/0,
        GIR_ConstrainSelectedInstOperands, /*InsnID*/0,
        GIR_EraseFromParent, /*InsnID*/0,
        // GIR_Coverage, 5011,
        GIR_Done,
      // Label 6143: @449796
      GIM_Try, /*On fail goto*//*Label 6144*/ GIMT_Encode4(449878), // Rule ID 5019 //
        GIM_CheckRegBankForClass, /*MI*/0, /*Op*/0, /*RC*/GIMT_Encode2(AMDGPU::AV_64RegClassID),
        GIM_CheckConstantInt8, /*MI*/0, /*Op*/3, 0,
        // MIs[0] offset
        GIM_CheckIsImm, /*MI*/0, /*Op*/6,
        // MIs[0] auxiliary
        GIM_CheckIsImm, /*MI*/0, /*Op*/7,
        // MIs[0] Operand 8
        GIM_CheckLiteralInt, /*MI*/0, /*Op*/8, GIMT_Encode8(0),
        GIM_CheckComplexPattern, /*MI*/0, /*Op*/5, /*Renderer*/GIMT_Encode2(0), GIMT_Encode2(GICP_gi_buf_soffset),
        // (SIbuffer_atomic_smax:{ *:[i64] } i64:{ *:[i64] }:$vdata_in, v4i32:{ *:[v4i32] }:$rsrc, 0:{ *:[i32] }, i32:{ *:[i32] }:$voffset, (BUFSOffset:{ *:[i32] } i32:{ *:[i32] }:$soffset), (timm:{ *:[i32] }):$offset, (timm:{ *:[i32] }):$auxiliary, 0:{ *:[i1] })  =>  (BUFFER_ATOMIC_SMAX_X2_VBUFFER_OFFEN_RTN:{ *:[i64] } anonymous_15036:{ *:[i64] }:$vdata_in, VGPR_32:{ *:[i32] }:$voffset, SReg_128:{ *:[v4i32] }:$rsrc, SCSrc_b32:{ *:[i32] }:$soffset, (timm:{ *:[i32] }):$offset, (extract_cpol_set_glc:{ *:[i32] } ?:{ *:[i32] }:$auxiliary))
        GIR_BuildMI, /*InsnID*/0, /*Opcode*/GIMT_Encode2(AMDGPU::BUFFER_ATOMIC_SMAX_X2_VBUFFER_OFFEN_RTN),
        GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/0, // DstI[vdata]
        GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/1, // vdata_in
        GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/4, // voffset
        GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/2, // rsrc
        GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/0, // soffset
        GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/6, // offset
        GIR_CustomOperandRenderer, /*InsnID*/0, /*OldInsnID*/0, /*OpIdx*/7, /*OperandRenderer*/GIMT_Encode2(GICR_renderExtractCpolSetGLC), // auxiliary
        GIR_MergeMemOperands, /*InsnID*/0, /*NumInsns*/1, /*MergeInsnID's*/0,
        GIR_ConstrainSelectedInstOperands, /*InsnID*/0,
        GIR_EraseFromParent, /*InsnID*/0,
        // GIR_Coverage, 5019,
        GIR_Done,
      // Label 6144: @449878
      GIM_Try, /*On fail goto*//*Label 6145*/ GIMT_Encode4(449948), // Rule ID 5014 //
        GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasUnrestrictedSOffset),
        GIM_CheckHasNoUse, /*MI*/0,
        GIM_CheckConstantInt8, /*MI*/0, /*Op*/4, 0,
        // MIs[0] offset
        GIM_CheckIsImm, /*MI*/0, /*Op*/6,
        // MIs[0] auxiliary
        GIM_CheckIsImm, /*MI*/0, /*Op*/7,
        // MIs[0] Operand 8
        GIM_CheckIsImm, /*MI*/0, /*Op*/8,
        GIM_CheckComplexPattern, /*MI*/0, /*Op*/5, /*Renderer*/GIMT_Encode2(0), GIMT_Encode2(GICP_gi_buf_soffset),
        // (SIbuffer_atomic_smax:{ *:[i64] } i64:{ *:[i64] }:$vdata_in, v4i32:{ *:[v4i32] }:$rsrc, i32:{ *:[i32] }:$vindex, 0:{ *:[i32] }, (BUFSOffset:{ *:[i32] } i32:{ *:[i32] }:$soffset), (timm:{ *:[i32] }):$offset, (timm:{ *:[i32] }):$auxiliary, (timm:{ *:[i1] }))<<P:Predicate_SIbuffer_atomic_smax_noret>>  =>  (BUFFER_ATOMIC_SMAX_X2_IDXEN anonymous_15036:{ *:[i64] }:$vdata_in, VGPR_32:{ *:[i32] }:$vindex, SReg_128:{ *:[v4i32] }:$rsrc, SCSrc_b32:{ *:[i32] }:$soffset, (timm:{ *:[i32] }):$offset, (extract_cpol:{ *:[i32] } ?:{ *:[i32] }:$auxiliary))
        GIR_BuildMI, /*InsnID*/0, /*Opcode*/GIMT_Encode2(AMDGPU::BUFFER_ATOMIC_SMAX_X2_IDXEN),
        GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/1, // vdata_in
        GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/3, // vindex
        GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/2, // rsrc
        GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/0, // soffset
        GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/6, // offset
        GIR_CustomOperandRenderer, /*InsnID*/0, /*OldInsnID*/0, /*OpIdx*/7, /*OperandRenderer*/GIMT_Encode2(GICR_renderExtractCPol), // auxiliary
        GIR_MergeMemOperands, /*InsnID*/0, /*NumInsns*/1, /*MergeInsnID's*/0,
        GIR_ConstrainSelectedInstOperands, /*InsnID*/0,
        GIR_EraseFromParent, /*InsnID*/0,
        // GIR_Coverage, 5014,
        GIR_Done,
      // Label 6145: @449948
      GIM_Try, /*On fail goto*//*Label 6146*/ GIMT_Encode4(450015), // Rule ID 5022 //
        GIM_CheckHasNoUse, /*MI*/0,
        GIM_CheckConstantInt8, /*MI*/0, /*Op*/4, 0,
        // MIs[0] offset
        GIM_CheckIsImm, /*MI*/0, /*Op*/6,
        // MIs[0] auxiliary
        GIM_CheckIsImm, /*MI*/0, /*Op*/7,
        // MIs[0] Operand 8
        GIM_CheckIsImm, /*MI*/0, /*Op*/8,
        GIM_CheckComplexPattern, /*MI*/0, /*Op*/5, /*Renderer*/GIMT_Encode2(0), GIMT_Encode2(GICP_gi_buf_soffset),
        // (SIbuffer_atomic_smax:{ *:[i64] } i64:{ *:[i64] }:$vdata_in, v4i32:{ *:[v4i32] }:$rsrc, i32:{ *:[i32] }:$vindex, 0:{ *:[i32] }, (BUFSOffset:{ *:[i32] } i32:{ *:[i32] }:$soffset), (timm:{ *:[i32] }):$offset, (timm:{ *:[i32] }):$auxiliary, (timm:{ *:[i1] }))<<P:Predicate_SIbuffer_atomic_smax_noret>>  =>  (BUFFER_ATOMIC_SMAX_X2_VBUFFER_IDXEN anonymous_15036:{ *:[i64] }:$vdata_in, VGPR_32:{ *:[i32] }:$vindex, SReg_128:{ *:[v4i32] }:$rsrc, SCSrc_b32:{ *:[i32] }:$soffset, (timm:{ *:[i32] }):$offset, (extract_cpol:{ *:[i32] } ?:{ *:[i32] }:$auxiliary))
        GIR_BuildMI, /*InsnID*/0, /*Opcode*/GIMT_Encode2(AMDGPU::BUFFER_ATOMIC_SMAX_X2_VBUFFER_IDXEN),
        GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/1, // vdata_in
        GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/3, // vindex
        GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/2, // rsrc
        GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/0, // soffset
        GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/6, // offset
        GIR_CustomOperandRenderer, /*InsnID*/0, /*OldInsnID*/0, /*OpIdx*/7, /*OperandRenderer*/GIMT_Encode2(GICR_renderExtractCPol), // auxiliary
        GIR_MergeMemOperands, /*InsnID*/0, /*NumInsns*/1, /*MergeInsnID's*/0,
        GIR_ConstrainSelectedInstOperands, /*InsnID*/0,
        GIR_EraseFromParent, /*InsnID*/0,
        // GIR_Coverage, 5022,
        GIR_Done,
      // Label 6146: @450015
      GIM_Try, /*On fail goto*//*Label 6147*/ GIMT_Encode4(450092), // Rule ID 5010 //
        GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasUnrestrictedSOffset),
        GIM_CheckRegBankForClass, /*MI*/0, /*Op*/0, /*RC*/GIMT_Encode2(AMDGPU::AV_64RegClassID),
        GIM_CheckConstantInt8, /*MI*/0, /*Op*/4, 0,
        // MIs[0] offset
        GIM_CheckIsImm, /*MI*/0, /*Op*/6,
        // MIs[0] auxiliary
        GIM_CheckIsImm, /*MI*/0, /*Op*/7,
        // MIs[0] Operand 8
        GIM_CheckIsImm, /*MI*/0, /*Op*/8,
        GIM_CheckComplexPattern, /*MI*/0, /*Op*/5, /*Renderer*/GIMT_Encode2(0), GIMT_Encode2(GICP_gi_buf_soffset),
        // (SIbuffer_atomic_smax:{ *:[i64] } i64:{ *:[i64] }:$vdata_in, v4i32:{ *:[v4i32] }:$rsrc, i32:{ *:[i32] }:$vindex, 0:{ *:[i32] }, (BUFSOffset:{ *:[i32] } i32:{ *:[i32] }:$soffset), (timm:{ *:[i32] }):$offset, (timm:{ *:[i32] }):$auxiliary, (timm:{ *:[i1] }))  =>  (BUFFER_ATOMIC_SMAX_X2_IDXEN_RTN:{ *:[i64] } anonymous_15036:{ *:[i64] }:$vdata_in, VGPR_32:{ *:[i32] }:$vindex, SReg_128:{ *:[v4i32] }:$rsrc, SCSrc_b32:{ *:[i32] }:$soffset, (timm:{ *:[i32] }):$offset, (extract_cpol_set_glc:{ *:[i32] } ?:{ *:[i32] }:$auxiliary))
        GIR_BuildMI, /*InsnID*/0, /*Opcode*/GIMT_Encode2(AMDGPU::BUFFER_ATOMIC_SMAX_X2_IDXEN_RTN),
        GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/0, // DstI[vdata]
        GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/1, // vdata_in
        GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/3, // vindex
        GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/2, // rsrc
        GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/0, // soffset
        GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/6, // offset
        GIR_CustomOperandRenderer, /*InsnID*/0, /*OldInsnID*/0, /*OpIdx*/7, /*OperandRenderer*/GIMT_Encode2(GICR_renderExtractCpolSetGLC), // auxiliary
        GIR_MergeMemOperands, /*InsnID*/0, /*NumInsns*/1, /*MergeInsnID's*/0,
        GIR_ConstrainSelectedInstOperands, /*InsnID*/0,
        GIR_EraseFromParent, /*InsnID*/0,
        // GIR_Coverage, 5010,
        GIR_Done,
      // Label 6147: @450092
      GIM_Try, /*On fail goto*//*Label 6148*/ GIMT_Encode4(450166), // Rule ID 5018 //
        GIM_CheckRegBankForClass, /*MI*/0, /*Op*/0, /*RC*/GIMT_Encode2(AMDGPU::AV_64RegClassID),
        GIM_CheckConstantInt8, /*MI*/0, /*Op*/4, 0,
        // MIs[0] offset
        GIM_CheckIsImm, /*MI*/0, /*Op*/6,
        // MIs[0] auxiliary
        GIM_CheckIsImm, /*MI*/0, /*Op*/7,
        // MIs[0] Operand 8
        GIM_CheckIsImm, /*MI*/0, /*Op*/8,
        GIM_CheckComplexPattern, /*MI*/0, /*Op*/5, /*Renderer*/GIMT_Encode2(0), GIMT_Encode2(GICP_gi_buf_soffset),
        // (SIbuffer_atomic_smax:{ *:[i64] } i64:{ *:[i64] }:$vdata_in, v4i32:{ *:[v4i32] }:$rsrc, i32:{ *:[i32] }:$vindex, 0:{ *:[i32] }, (BUFSOffset:{ *:[i32] } i32:{ *:[i32] }:$soffset), (timm:{ *:[i32] }):$offset, (timm:{ *:[i32] }):$auxiliary, (timm:{ *:[i1] }))  =>  (BUFFER_ATOMIC_SMAX_X2_VBUFFER_IDXEN_RTN:{ *:[i64] } anonymous_15036:{ *:[i64] }:$vdata_in, VGPR_32:{ *:[i32] }:$vindex, SReg_128:{ *:[v4i32] }:$rsrc, SCSrc_b32:{ *:[i32] }:$soffset, (timm:{ *:[i32] }):$offset, (extract_cpol_set_glc:{ *:[i32] } ?:{ *:[i32] }:$auxiliary))
        GIR_BuildMI, /*InsnID*/0, /*Opcode*/GIMT_Encode2(AMDGPU::BUFFER_ATOMIC_SMAX_X2_VBUFFER_IDXEN_RTN),
        GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/0, // DstI[vdata]
        GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/1, // vdata_in
        GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/3, // vindex
        GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/2, // rsrc
        GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/0, // soffset
        GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/6, // offset
        GIR_CustomOperandRenderer, /*InsnID*/0, /*OldInsnID*/0, /*OpIdx*/7, /*OperandRenderer*/GIMT_Encode2(GICR_renderExtractCpolSetGLC), // auxiliary
        GIR_MergeMemOperands, /*InsnID*/0, /*NumInsns*/1, /*MergeInsnID's*/0,
        GIR_ConstrainSelectedInstOperands, /*InsnID*/0,
        GIR_EraseFromParent, /*InsnID*/0,
        // GIR_Coverage, 5018,
        GIR_Done,
      // Label 6148: @450166
      GIM_Try, /*On fail goto*//*Label 6149*/ GIMT_Encode4(450272), // Rule ID 5016 //
        GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasUnrestrictedSOffset),
        GIM_CheckHasNoUse, /*MI*/0,
        // MIs[0] offset
        GIM_CheckIsImm, /*MI*/0, /*Op*/6,
        // MIs[0] auxiliary
        GIM_CheckIsImm, /*MI*/0, /*Op*/7,
        // MIs[0] Operand 8
        GIM_CheckIsImm, /*MI*/0, /*Op*/8,
        GIM_CheckComplexPattern, /*MI*/0, /*Op*/5, /*Renderer*/GIMT_Encode2(0), GIMT_Encode2(GICP_gi_buf_soffset),
        // (SIbuffer_atomic_smax:{ *:[i64] } i64:{ *:[i64] }:$vdata_in, v4i32:{ *:[v4i32] }:$rsrc, i32:{ *:[i32] }:$vindex, i32:{ *:[i32] }:$voffset, (BUFSOffset:{ *:[i32] } i32:{ *:[i32] }:$soffset), (timm:{ *:[i32] }):$offset, (timm:{ *:[i32] }):$auxiliary, (timm:{ *:[i1] }))<<P:Predicate_SIbuffer_atomic_smax_noret>>  =>  (BUFFER_ATOMIC_SMAX_X2_BOTHEN anonymous_15036:{ *:[i64] }:$vdata_in, (REG_SEQUENCE:{ *:[i64] } VReg_64:{ *:[i32] }, VGPR_32:{ *:[i32] }:$vindex, sub0:{ *:[i32] }, VGPR_32:{ *:[i32] }:$voffset, sub1:{ *:[i32] }), SReg_128:{ *:[v4i32] }:$rsrc, SCSrc_b32:{ *:[i32] }:$soffset, (timm:{ *:[i32] }):$offset, (extract_cpol:{ *:[i32] } ?:{ *:[i32] }:$auxiliary))
        GIR_MakeTempReg, /*TempRegID*/0, /*TypeID*/GILLT_s64,
        GIR_BuildMI, /*InsnID*/1, /*Opcode*/GIMT_Encode2(TargetOpcode::REG_SEQUENCE),
        GIR_AddTempRegister, /*InsnID*/1, /*TempRegID*/0, /*TempRegFlags*/GIMT_Encode2(RegState::Define),
        GIR_Copy, /*NewInsnID*/1, /*OldInsnID*/0, /*OpIdx*/3, // vindex
        GIR_AddImm8, /*InsnID*/1, /*SubRegIndex*/3,
        GIR_Copy, /*NewInsnID*/1, /*OldInsnID*/0, /*OpIdx*/4, // voffset
        GIR_AddImm8, /*InsnID*/1, /*SubRegIndex*/11,
        GIR_ConstrainOperandRC, /*InsnID*/1, /*Op*/0, GIMT_Encode2(AMDGPU::VReg_64RegClassID),
        GIR_ConstrainOperandRC, /*InsnID*/1, /*Op*/1, GIMT_Encode2(AMDGPU::VGPR_32RegClassID),
        GIR_ConstrainOperandRC, /*InsnID*/1, /*Op*/3, GIMT_Encode2(AMDGPU::VGPR_32RegClassID),
        GIR_BuildMI, /*InsnID*/0, /*Opcode*/GIMT_Encode2(AMDGPU::BUFFER_ATOMIC_SMAX_X2_BOTHEN),
        GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/1, // vdata_in
        GIR_AddSimpleTempRegister, /*InsnID*/0, /*TempRegID*/0,
        GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/2, // rsrc
        GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/0, // soffset
        GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/6, // offset
        GIR_CustomOperandRenderer, /*InsnID*/0, /*OldInsnID*/0, /*OpIdx*/7, /*OperandRenderer*/GIMT_Encode2(GICR_renderExtractCPol), // auxiliary
        GIR_MergeMemOperands, /*InsnID*/0, /*NumInsns*/1, /*MergeInsnID's*/0,
        GIR_ConstrainSelectedInstOperands, /*InsnID*/0,
        GIR_EraseFromParent, /*InsnID*/0,
        // GIR_Coverage, 5016,
        GIR_Done,
      // Label 6149: @450272
      GIM_Try, /*On fail goto*//*Label 6150*/ GIMT_Encode4(450375), // Rule ID 5024 //
        GIM_CheckHasNoUse, /*MI*/0,
        // MIs[0] offset
        GIM_CheckIsImm, /*MI*/0, /*Op*/6,
        // MIs[0] auxiliary
        GIM_CheckIsImm, /*MI*/0, /*Op*/7,
        // MIs[0] Operand 8
        GIM_CheckIsImm, /*MI*/0, /*Op*/8,
        GIM_CheckComplexPattern, /*MI*/0, /*Op*/5, /*Renderer*/GIMT_Encode2(0), GIMT_Encode2(GICP_gi_buf_soffset),
        // (SIbuffer_atomic_smax:{ *:[i64] } i64:{ *:[i64] }:$vdata_in, v4i32:{ *:[v4i32] }:$rsrc, i32:{ *:[i32] }:$vindex, i32:{ *:[i32] }:$voffset, (BUFSOffset:{ *:[i32] } i32:{ *:[i32] }:$soffset), (timm:{ *:[i32] }):$offset, (timm:{ *:[i32] }):$auxiliary, (timm:{ *:[i1] }))<<P:Predicate_SIbuffer_atomic_smax_noret>>  =>  (BUFFER_ATOMIC_SMAX_X2_VBUFFER_BOTHEN anonymous_15036:{ *:[i64] }:$vdata_in, (REG_SEQUENCE:{ *:[i64] } VReg_64:{ *:[i32] }, VGPR_32:{ *:[i32] }:$vindex, sub0:{ *:[i32] }, VGPR_32:{ *:[i32] }:$voffset, sub1:{ *:[i32] }), SReg_128:{ *:[v4i32] }:$rsrc, SCSrc_b32:{ *:[i32] }:$soffset, (timm:{ *:[i32] }):$offset, (extract_cpol:{ *:[i32] } ?:{ *:[i32] }:$auxiliary))
        GIR_MakeTempReg, /*TempRegID*/0, /*TypeID*/GILLT_s64,
        GIR_BuildMI, /*InsnID*/1, /*Opcode*/GIMT_Encode2(TargetOpcode::REG_SEQUENCE),
        GIR_AddTempRegister, /*InsnID*/1, /*TempRegID*/0, /*TempRegFlags*/GIMT_Encode2(RegState::Define),
        GIR_Copy, /*NewInsnID*/1, /*OldInsnID*/0, /*OpIdx*/3, // vindex
        GIR_AddImm8, /*InsnID*/1, /*SubRegIndex*/3,
        GIR_Copy, /*NewInsnID*/1, /*OldInsnID*/0, /*OpIdx*/4, // voffset
        GIR_AddImm8, /*InsnID*/1, /*SubRegIndex*/11,
        GIR_ConstrainOperandRC, /*InsnID*/1, /*Op*/0, GIMT_Encode2(AMDGPU::VReg_64RegClassID),
        GIR_ConstrainOperandRC, /*InsnID*/1, /*Op*/1, GIMT_Encode2(AMDGPU::VGPR_32RegClassID),
        GIR_ConstrainOperandRC, /*InsnID*/1, /*Op*/3, GIMT_Encode2(AMDGPU::VGPR_32RegClassID),
        GIR_BuildMI, /*InsnID*/0, /*Opcode*/GIMT_Encode2(AMDGPU::BUFFER_ATOMIC_SMAX_X2_VBUFFER_BOTHEN),
        GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/1, // vdata_in
        GIR_AddSimpleTempRegister, /*InsnID*/0, /*TempRegID*/0,
        GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/2, // rsrc
        GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/0, // soffset
        GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/6, // offset
        GIR_CustomOperandRenderer, /*InsnID*/0, /*OldInsnID*/0, /*OpIdx*/7, /*OperandRenderer*/GIMT_Encode2(GICR_renderExtractCPol), // auxiliary
        GIR_MergeMemOperands, /*InsnID*/0, /*NumInsns*/1, /*MergeInsnID's*/0,
        GIR_ConstrainSelectedInstOperands, /*InsnID*/0,
        GIR_EraseFromParent, /*InsnID*/0,
        // GIR_Coverage, 5024,
        GIR_Done,
      // Label 6150: @450375
      GIM_Try, /*On fail goto*//*Label 6151*/ GIMT_Encode4(450488), // Rule ID 5012 //
        GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasUnrestrictedSOffset),
        GIM_CheckRegBankForClass, /*MI*/0, /*Op*/0, /*RC*/GIMT_Encode2(AMDGPU::AV_64RegClassID),
        // MIs[0] offset
        GIM_CheckIsImm, /*MI*/0, /*Op*/6,
        // MIs[0] auxiliary
        GIM_CheckIsImm, /*MI*/0, /*Op*/7,
        // MIs[0] Operand 8
        GIM_CheckIsImm, /*MI*/0, /*Op*/8,
        GIM_CheckComplexPattern, /*MI*/0, /*Op*/5, /*Renderer*/GIMT_Encode2(0), GIMT_Encode2(GICP_gi_buf_soffset),
        // (SIbuffer_atomic_smax:{ *:[i64] } i64:{ *:[i64] }:$vdata_in, v4i32:{ *:[v4i32] }:$rsrc, i32:{ *:[i32] }:$vindex, i32:{ *:[i32] }:$voffset, (BUFSOffset:{ *:[i32] } i32:{ *:[i32] }:$soffset), (timm:{ *:[i32] }):$offset, (timm:{ *:[i32] }):$auxiliary, (timm:{ *:[i1] }))  =>  (BUFFER_ATOMIC_SMAX_X2_BOTHEN_RTN:{ *:[i64] } anonymous_15036:{ *:[i64] }:$vdata_in, (REG_SEQUENCE:{ *:[i64] } VReg_64:{ *:[i32] }, VGPR_32:{ *:[i32] }:$vindex, sub0:{ *:[i32] }, VGPR_32:{ *:[i32] }:$voffset, sub1:{ *:[i32] }), SReg_128:{ *:[v4i32] }:$rsrc, SCSrc_b32:{ *:[i32] }:$soffset, (timm:{ *:[i32] }):$offset, (extract_cpol_set_glc:{ *:[i32] } ?:{ *:[i32] }:$auxiliary))
        GIR_MakeTempReg, /*TempRegID*/0, /*TypeID*/GILLT_s64,
        GIR_BuildMI, /*InsnID*/1, /*Opcode*/GIMT_Encode2(TargetOpcode::REG_SEQUENCE),
        GIR_AddTempRegister, /*InsnID*/1, /*TempRegID*/0, /*TempRegFlags*/GIMT_Encode2(RegState::Define),
        GIR_Copy, /*NewInsnID*/1, /*OldInsnID*/0, /*OpIdx*/3, // vindex
        GIR_AddImm8, /*InsnID*/1, /*SubRegIndex*/3,
        GIR_Copy, /*NewInsnID*/1, /*OldInsnID*/0, /*OpIdx*/4, // voffset
        GIR_AddImm8, /*InsnID*/1, /*SubRegIndex*/11,
        GIR_ConstrainOperandRC, /*InsnID*/1, /*Op*/0, GIMT_Encode2(AMDGPU::VReg_64RegClassID),
        GIR_ConstrainOperandRC, /*InsnID*/1, /*Op*/1, GIMT_Encode2(AMDGPU::VGPR_32RegClassID),
        GIR_ConstrainOperandRC, /*InsnID*/1, /*Op*/3, GIMT_Encode2(AMDGPU::VGPR_32RegClassID),
        GIR_BuildMI, /*InsnID*/0, /*Opcode*/GIMT_Encode2(AMDGPU::BUFFER_ATOMIC_SMAX_X2_BOTHEN_RTN),
        GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/0, // DstI[vdata]
        GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/1, // vdata_in
        GIR_AddSimpleTempRegister, /*InsnID*/0, /*TempRegID*/0,
        GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/2, // rsrc
        GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/0, // soffset
        GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/6, // offset
        GIR_CustomOperandRenderer, /*InsnID*/0, /*OldInsnID*/0, /*OpIdx*/7, /*OperandRenderer*/GIMT_Encode2(GICR_renderExtractCpolSetGLC), // auxiliary
        GIR_MergeMemOperands, /*InsnID*/0, /*NumInsns*/1, /*MergeInsnID's*/0,
        GIR_ConstrainSelectedInstOperands, /*InsnID*/0,
        GIR_EraseFromParent, /*InsnID*/0,
        // GIR_Coverage, 5012,
        GIR_Done,
      // Label 6151: @450488
      GIM_Try, /*On fail goto*//*Label 6152*/ GIMT_Encode4(450598), // Rule ID 5020 //
        GIM_CheckRegBankForClass, /*MI*/0, /*Op*/0, /*RC*/GIMT_Encode2(AMDGPU::AV_64RegClassID),
        // MIs[0] offset
        GIM_CheckIsImm, /*MI*/0, /*Op*/6,
        // MIs[0] auxiliary
        GIM_CheckIsImm, /*MI*/0, /*Op*/7,
        // MIs[0] Operand 8
        GIM_CheckIsImm, /*MI*/0, /*Op*/8,
        GIM_CheckComplexPattern, /*MI*/0, /*Op*/5, /*Renderer*/GIMT_Encode2(0), GIMT_Encode2(GICP_gi_buf_soffset),
        // (SIbuffer_atomic_smax:{ *:[i64] } i64:{ *:[i64] }:$vdata_in, v4i32:{ *:[v4i32] }:$rsrc, i32:{ *:[i32] }:$vindex, i32:{ *:[i32] }:$voffset, (BUFSOffset:{ *:[i32] } i32:{ *:[i32] }:$soffset), (timm:{ *:[i32] }):$offset, (timm:{ *:[i32] }):$auxiliary, (timm:{ *:[i1] }))  =>  (BUFFER_ATOMIC_SMAX_X2_VBUFFER_BOTHEN_RTN:{ *:[i64] } anonymous_15036:{ *:[i64] }:$vdata_in, (REG_SEQUENCE:{ *:[i64] } VReg_64:{ *:[i32] }, VGPR_32:{ *:[i32] }:$vindex, sub0:{ *:[i32] }, VGPR_32:{ *:[i32] }:$voffset, sub1:{ *:[i32] }), SReg_128:{ *:[v4i32] }:$rsrc, SCSrc_b32:{ *:[i32] }:$soffset, (timm:{ *:[i32] }):$offset, (extract_cpol_set_glc:{ *:[i32] } ?:{ *:[i32] }:$auxiliary))
        GIR_MakeTempReg, /*TempRegID*/0, /*TypeID*/GILLT_s64,
        GIR_BuildMI, /*InsnID*/1, /*Opcode*/GIMT_Encode2(TargetOpcode::REG_SEQUENCE),
        GIR_AddTempRegister, /*InsnID*/1, /*TempRegID*/0, /*TempRegFlags*/GIMT_Encode2(RegState::Define),
        GIR_Copy, /*NewInsnID*/1, /*OldInsnID*/0, /*OpIdx*/3, // vindex
        GIR_AddImm8, /*InsnID*/1, /*SubRegIndex*/3,
        GIR_Copy, /*NewInsnID*/1, /*OldInsnID*/0, /*OpIdx*/4, // voffset
        GIR_AddImm8, /*InsnID*/1, /*SubRegIndex*/11,
        GIR_ConstrainOperandRC, /*InsnID*/1, /*Op*/0, GIMT_Encode2(AMDGPU::VReg_64RegClassID),
        GIR_ConstrainOperandRC, /*InsnID*/1, /*Op*/1, GIMT_Encode2(AMDGPU::VGPR_32RegClassID),
        GIR_ConstrainOperandRC, /*InsnID*/1, /*Op*/3, GIMT_Encode2(AMDGPU::VGPR_32RegClassID),
        GIR_BuildMI, /*InsnID*/0, /*Opcode*/GIMT_Encode2(AMDGPU::BUFFER_ATOMIC_SMAX_X2_VBUFFER_BOTHEN_RTN),
        GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/0, // DstI[vdata]
        GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/1, // vdata_in
        GIR_AddSimpleTempRegister, /*InsnID*/0, /*TempRegID*/0,
        GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/2, // rsrc
        GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/0, // soffset
        GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/6, // offset
        GIR_CustomOperandRenderer, /*InsnID*/0, /*OldInsnID*/0, /*OpIdx*/7, /*OperandRenderer*/GIMT_Encode2(GICR_renderExtractCpolSetGLC), // auxiliary
        GIR_MergeMemOperands, /*InsnID*/0, /*NumInsns*/1, /*MergeInsnID's*/0,
        GIR_ConstrainSelectedInstOperands, /*InsnID*/0,
        GIR_EraseFromParent, /*InsnID*/0,
        // GIR_Coverage, 5020,
        GIR_Done,
      // Label 6152: @450598
      GIM_Reject,
    // Label 6136: @450599
    GIM_Reject,
    // Label 6118: @450600
    GIM_Reject,
    // Label 118: @450601
    GIM_SwitchType, /*MI*/0, /*Op*/0, /*[*/GIMT_Encode2(9), GIMT_Encode2(11), /*)*//*default:*//*Label 6155*/ GIMT_Encode4(453394),
    /*GILLT_s32*//*Label 6153*/ GIMT_Encode4(450620),
    /*GILLT_s64*//*Label 6154*/ GIMT_Encode4(452007),
    // Label 6153: @450620
    GIM_Try, /*On fail goto*//*Label 6156*/ GIMT_Encode4(452006),
      GIM_CheckType, /*MI*/0, /*Op*/1, /*Type*/GILLT_s32,
      GIM_CheckType, /*MI*/0, /*Op*/2, /*Type*/GILLT_v4s32,
      GIM_CheckType, /*MI*/0, /*Op*/3, /*Type*/GILLT_s32,
      GIM_CheckType, /*MI*/0, /*Op*/4, /*Type*/GILLT_s32,
      GIM_CheckType, /*MI*/0, /*Op*/5, /*Type*/GILLT_s32,
      GIM_Try, /*On fail goto*//*Label 6157*/ GIMT_Encode4(450723), // Rule ID 4781 //
        GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasUnrestrictedSOffset),
        GIM_CheckHasNoUse, /*MI*/0,
        GIM_CheckConstantInt8, /*MI*/0, /*Op*/3, 0,
        GIM_CheckConstantInt8, /*MI*/0, /*Op*/4, 0,
        // MIs[0] offset
        GIM_CheckIsImm, /*MI*/0, /*Op*/6,
        // MIs[0] auxiliary
        GIM_CheckIsImm, /*MI*/0, /*Op*/7,
        // MIs[0] Operand 8
        GIM_CheckLiteralInt, /*MI*/0, /*Op*/8, GIMT_Encode8(0),
        GIM_CheckComplexPattern, /*MI*/0, /*Op*/5, /*Renderer*/GIMT_Encode2(0), GIMT_Encode2(GICP_gi_buf_soffset),
        // (SIbuffer_atomic_smin:{ *:[i32] } i32:{ *:[i32] }:$vdata_in, v4i32:{ *:[v4i32] }:$rsrc, 0:{ *:[i32] }, 0:{ *:[i32] }, (BUFSOffset:{ *:[i32] } i32:{ *:[i32] }:$soffset), (timm:{ *:[i32] }):$offset, (timm:{ *:[i32] }):$auxiliary, 0:{ *:[i1] })<<P:Predicate_SIbuffer_atomic_smin_noret>>  =>  (BUFFER_ATOMIC_SMIN_OFFSET anonymous_15037:{ *:[i32] }:$vdata_in, SReg_128:{ *:[v4i32] }:$rsrc, SCSrc_b32:{ *:[i32] }:$soffset, (timm:{ *:[i32] }):$offset, (extract_cpol:{ *:[i32] } ?:{ *:[i32] }:$auxiliary))
        GIR_BuildMI, /*InsnID*/0, /*Opcode*/GIMT_Encode2(AMDGPU::BUFFER_ATOMIC_SMIN_OFFSET),
        GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/1, // vdata_in
        GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/2, // rsrc
        GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/0, // soffset
        GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/6, // offset
        GIR_CustomOperandRenderer, /*InsnID*/0, /*OldInsnID*/0, /*OpIdx*/7, /*OperandRenderer*/GIMT_Encode2(GICR_renderExtractCPol), // auxiliary
        GIR_MergeMemOperands, /*InsnID*/0, /*NumInsns*/1, /*MergeInsnID's*/0,
        GIR_ConstrainSelectedInstOperands, /*InsnID*/0,
        GIR_EraseFromParent, /*InsnID*/0,
        // GIR_Coverage, 4781,
        GIR_Done,
      // Label 6157: @450723
      GIM_Try, /*On fail goto*//*Label 6158*/ GIMT_Encode4(450798), // Rule ID 4789 //
        GIM_CheckHasNoUse, /*MI*/0,
        GIM_CheckConstantInt8, /*MI*/0, /*Op*/3, 0,
        GIM_CheckConstantInt8, /*MI*/0, /*Op*/4, 0,
        // MIs[0] offset
        GIM_CheckIsImm, /*MI*/0, /*Op*/6,
        // MIs[0] auxiliary
        GIM_CheckIsImm, /*MI*/0, /*Op*/7,
        // MIs[0] Operand 8
        GIM_CheckLiteralInt, /*MI*/0, /*Op*/8, GIMT_Encode8(0),
        GIM_CheckComplexPattern, /*MI*/0, /*Op*/5, /*Renderer*/GIMT_Encode2(0), GIMT_Encode2(GICP_gi_buf_soffset),
        // (SIbuffer_atomic_smin:{ *:[i32] } i32:{ *:[i32] }:$vdata_in, v4i32:{ *:[v4i32] }:$rsrc, 0:{ *:[i32] }, 0:{ *:[i32] }, (BUFSOffset:{ *:[i32] } i32:{ *:[i32] }:$soffset), (timm:{ *:[i32] }):$offset, (timm:{ *:[i32] }):$auxiliary, 0:{ *:[i1] })<<P:Predicate_SIbuffer_atomic_smin_noret>>  =>  (BUFFER_ATOMIC_SMIN_VBUFFER_OFFSET anonymous_15037:{ *:[i32] }:$vdata_in, SReg_128:{ *:[v4i32] }:$rsrc, SCSrc_b32:{ *:[i32] }:$soffset, (timm:{ *:[i32] }):$offset, (extract_cpol:{ *:[i32] } ?:{ *:[i32] }:$auxiliary))
        GIR_BuildMI, /*InsnID*/0, /*Opcode*/GIMT_Encode2(AMDGPU::BUFFER_ATOMIC_SMIN_VBUFFER_OFFSET),
        GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/1, // vdata_in
        GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/2, // rsrc
        GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/0, // soffset
        GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/6, // offset
        GIR_CustomOperandRenderer, /*InsnID*/0, /*OldInsnID*/0, /*OpIdx*/7, /*OperandRenderer*/GIMT_Encode2(GICR_renderExtractCPol), // auxiliary
        GIR_MergeMemOperands, /*InsnID*/0, /*NumInsns*/1, /*MergeInsnID's*/0,
        GIR_ConstrainSelectedInstOperands, /*InsnID*/0,
        GIR_EraseFromParent, /*InsnID*/0,
        // GIR_Coverage, 4789,
        GIR_Done,
      // Label 6158: @450798
      GIM_Try, /*On fail goto*//*Label 6159*/ GIMT_Encode4(450883), // Rule ID 4777 //
        GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasUnrestrictedSOffset),
        GIM_CheckRegBankForClass, /*MI*/0, /*Op*/0, /*RC*/GIMT_Encode2(AMDGPU::AV_32RegClassID),
        GIM_CheckConstantInt8, /*MI*/0, /*Op*/3, 0,
        GIM_CheckConstantInt8, /*MI*/0, /*Op*/4, 0,
        // MIs[0] offset
        GIM_CheckIsImm, /*MI*/0, /*Op*/6,
        // MIs[0] auxiliary
        GIM_CheckIsImm, /*MI*/0, /*Op*/7,
        // MIs[0] Operand 8
        GIM_CheckLiteralInt, /*MI*/0, /*Op*/8, GIMT_Encode8(0),
        GIM_CheckComplexPattern, /*MI*/0, /*Op*/5, /*Renderer*/GIMT_Encode2(0), GIMT_Encode2(GICP_gi_buf_soffset),
        // (SIbuffer_atomic_smin:{ *:[i32] } i32:{ *:[i32] }:$vdata_in, v4i32:{ *:[v4i32] }:$rsrc, 0:{ *:[i32] }, 0:{ *:[i32] }, (BUFSOffset:{ *:[i32] } i32:{ *:[i32] }:$soffset), (timm:{ *:[i32] }):$offset, (timm:{ *:[i32] }):$auxiliary, 0:{ *:[i1] })  =>  (BUFFER_ATOMIC_SMIN_OFFSET_RTN:{ *:[i32] } anonymous_15037:{ *:[i32] }:$vdata_in, SReg_128:{ *:[v4i32] }:$rsrc, SCSrc_b32:{ *:[i32] }:$soffset, (timm:{ *:[i32] }):$offset, (extract_cpol_set_glc:{ *:[i32] } ?:{ *:[i32] }:$auxiliary))
        GIR_BuildMI, /*InsnID*/0, /*Opcode*/GIMT_Encode2(AMDGPU::BUFFER_ATOMIC_SMIN_OFFSET_RTN),
        GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/0, // DstI[vdata]
        GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/1, // vdata_in
        GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/2, // rsrc
        GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/0, // soffset
        GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/6, // offset
        GIR_CustomOperandRenderer, /*InsnID*/0, /*OldInsnID*/0, /*OpIdx*/7, /*OperandRenderer*/GIMT_Encode2(GICR_renderExtractCpolSetGLC), // auxiliary
        GIR_MergeMemOperands, /*InsnID*/0, /*NumInsns*/1, /*MergeInsnID's*/0,
        GIR_ConstrainSelectedInstOperands, /*InsnID*/0,
        GIR_EraseFromParent, /*InsnID*/0,
        // GIR_Coverage, 4777,
        GIR_Done,
      // Label 6159: @450883
      GIM_Try, /*On fail goto*//*Label 6160*/ GIMT_Encode4(450965), // Rule ID 4785 //
        GIM_CheckRegBankForClass, /*MI*/0, /*Op*/0, /*RC*/GIMT_Encode2(AMDGPU::AV_32RegClassID),
        GIM_CheckConstantInt8, /*MI*/0, /*Op*/3, 0,
        GIM_CheckConstantInt8, /*MI*/0, /*Op*/4, 0,
        // MIs[0] offset
        GIM_CheckIsImm, /*MI*/0, /*Op*/6,
        // MIs[0] auxiliary
        GIM_CheckIsImm, /*MI*/0, /*Op*/7,
        // MIs[0] Operand 8
        GIM_CheckLiteralInt, /*MI*/0, /*Op*/8, GIMT_Encode8(0),
        GIM_CheckComplexPattern, /*MI*/0, /*Op*/5, /*Renderer*/GIMT_Encode2(0), GIMT_Encode2(GICP_gi_buf_soffset),
        // (SIbuffer_atomic_smin:{ *:[i32] } i32:{ *:[i32] }:$vdata_in, v4i32:{ *:[v4i32] }:$rsrc, 0:{ *:[i32] }, 0:{ *:[i32] }, (BUFSOffset:{ *:[i32] } i32:{ *:[i32] }:$soffset), (timm:{ *:[i32] }):$offset, (timm:{ *:[i32] }):$auxiliary, 0:{ *:[i1] })  =>  (BUFFER_ATOMIC_SMIN_VBUFFER_OFFSET_RTN:{ *:[i32] } anonymous_15037:{ *:[i32] }:$vdata_in, SReg_128:{ *:[v4i32] }:$rsrc, SCSrc_b32:{ *:[i32] }:$soffset, (timm:{ *:[i32] }):$offset, (extract_cpol_set_glc:{ *:[i32] } ?:{ *:[i32] }:$auxiliary))
        GIR_BuildMI, /*InsnID*/0, /*Opcode*/GIMT_Encode2(AMDGPU::BUFFER_ATOMIC_SMIN_VBUFFER_OFFSET_RTN),
        GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/0, // DstI[vdata]
        GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/1, // vdata_in
        GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/2, // rsrc
        GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/0, // soffset
        GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/6, // offset
        GIR_CustomOperandRenderer, /*InsnID*/0, /*OldInsnID*/0, /*OpIdx*/7, /*OperandRenderer*/GIMT_Encode2(GICR_renderExtractCpolSetGLC), // auxiliary
        GIR_MergeMemOperands, /*InsnID*/0, /*NumInsns*/1, /*MergeInsnID's*/0,
        GIR_ConstrainSelectedInstOperands, /*InsnID*/0,
        GIR_EraseFromParent, /*InsnID*/0,
        // GIR_Coverage, 4785,
        GIR_Done,
      // Label 6160: @450965
      GIM_Try, /*On fail goto*//*Label 6161*/ GIMT_Encode4(451043), // Rule ID 4783 //
        GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasUnrestrictedSOffset),
        GIM_CheckHasNoUse, /*MI*/0,
        GIM_CheckConstantInt8, /*MI*/0, /*Op*/3, 0,
        // MIs[0] offset
        GIM_CheckIsImm, /*MI*/0, /*Op*/6,
        // MIs[0] auxiliary
        GIM_CheckIsImm, /*MI*/0, /*Op*/7,
        // MIs[0] Operand 8
        GIM_CheckLiteralInt, /*MI*/0, /*Op*/8, GIMT_Encode8(0),
        GIM_CheckComplexPattern, /*MI*/0, /*Op*/5, /*Renderer*/GIMT_Encode2(0), GIMT_Encode2(GICP_gi_buf_soffset),
        // (SIbuffer_atomic_smin:{ *:[i32] } i32:{ *:[i32] }:$vdata_in, v4i32:{ *:[v4i32] }:$rsrc, 0:{ *:[i32] }, i32:{ *:[i32] }:$voffset, (BUFSOffset:{ *:[i32] } i32:{ *:[i32] }:$soffset), (timm:{ *:[i32] }):$offset, (timm:{ *:[i32] }):$auxiliary, 0:{ *:[i1] })<<P:Predicate_SIbuffer_atomic_smin_noret>>  =>  (BUFFER_ATOMIC_SMIN_OFFEN anonymous_15037:{ *:[i32] }:$vdata_in, VGPR_32:{ *:[i32] }:$voffset, SReg_128:{ *:[v4i32] }:$rsrc, SCSrc_b32:{ *:[i32] }:$soffset, (timm:{ *:[i32] }):$offset, (extract_cpol:{ *:[i32] } ?:{ *:[i32] }:$auxiliary))
        GIR_BuildMI, /*InsnID*/0, /*Opcode*/GIMT_Encode2(AMDGPU::BUFFER_ATOMIC_SMIN_OFFEN),
        GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/1, // vdata_in
        GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/4, // voffset
        GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/2, // rsrc
        GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/0, // soffset
        GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/6, // offset
        GIR_CustomOperandRenderer, /*InsnID*/0, /*OldInsnID*/0, /*OpIdx*/7, /*OperandRenderer*/GIMT_Encode2(GICR_renderExtractCPol), // auxiliary
        GIR_MergeMemOperands, /*InsnID*/0, /*NumInsns*/1, /*MergeInsnID's*/0,
        GIR_ConstrainSelectedInstOperands, /*InsnID*/0,
        GIR_EraseFromParent, /*InsnID*/0,
        // GIR_Coverage, 4783,
        GIR_Done,
      // Label 6161: @451043
      GIM_Try, /*On fail goto*//*Label 6162*/ GIMT_Encode4(451118), // Rule ID 4791 //
        GIM_CheckHasNoUse, /*MI*/0,
        GIM_CheckConstantInt8, /*MI*/0, /*Op*/3, 0,
        // MIs[0] offset
        GIM_CheckIsImm, /*MI*/0, /*Op*/6,
        // MIs[0] auxiliary
        GIM_CheckIsImm, /*MI*/0, /*Op*/7,
        // MIs[0] Operand 8
        GIM_CheckLiteralInt, /*MI*/0, /*Op*/8, GIMT_Encode8(0),
        GIM_CheckComplexPattern, /*MI*/0, /*Op*/5, /*Renderer*/GIMT_Encode2(0), GIMT_Encode2(GICP_gi_buf_soffset),
        // (SIbuffer_atomic_smin:{ *:[i32] } i32:{ *:[i32] }:$vdata_in, v4i32:{ *:[v4i32] }:$rsrc, 0:{ *:[i32] }, i32:{ *:[i32] }:$voffset, (BUFSOffset:{ *:[i32] } i32:{ *:[i32] }:$soffset), (timm:{ *:[i32] }):$offset, (timm:{ *:[i32] }):$auxiliary, 0:{ *:[i1] })<<P:Predicate_SIbuffer_atomic_smin_noret>>  =>  (BUFFER_ATOMIC_SMIN_VBUFFER_OFFEN anonymous_15037:{ *:[i32] }:$vdata_in, VGPR_32:{ *:[i32] }:$voffset, SReg_128:{ *:[v4i32] }:$rsrc, SCSrc_b32:{ *:[i32] }:$soffset, (timm:{ *:[i32] }):$offset, (extract_cpol:{ *:[i32] } ?:{ *:[i32] }:$auxiliary))
        GIR_BuildMI, /*InsnID*/0, /*Opcode*/GIMT_Encode2(AMDGPU::BUFFER_ATOMIC_SMIN_VBUFFER_OFFEN),
        GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/1, // vdata_in
        GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/4, // voffset
        GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/2, // rsrc
        GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/0, // soffset
        GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/6, // offset
        GIR_CustomOperandRenderer, /*InsnID*/0, /*OldInsnID*/0, /*OpIdx*/7, /*OperandRenderer*/GIMT_Encode2(GICR_renderExtractCPol), // auxiliary
        GIR_MergeMemOperands, /*InsnID*/0, /*NumInsns*/1, /*MergeInsnID's*/0,
        GIR_ConstrainSelectedInstOperands, /*InsnID*/0,
        GIR_EraseFromParent, /*InsnID*/0,
        // GIR_Coverage, 4791,
        GIR_Done,
      // Label 6162: @451118
      GIM_Try, /*On fail goto*//*Label 6163*/ GIMT_Encode4(451203), // Rule ID 4779 //
        GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasUnrestrictedSOffset),
        GIM_CheckRegBankForClass, /*MI*/0, /*Op*/0, /*RC*/GIMT_Encode2(AMDGPU::AV_32RegClassID),
        GIM_CheckConstantInt8, /*MI*/0, /*Op*/3, 0,
        // MIs[0] offset
        GIM_CheckIsImm, /*MI*/0, /*Op*/6,
        // MIs[0] auxiliary
        GIM_CheckIsImm, /*MI*/0, /*Op*/7,
        // MIs[0] Operand 8
        GIM_CheckLiteralInt, /*MI*/0, /*Op*/8, GIMT_Encode8(0),
        GIM_CheckComplexPattern, /*MI*/0, /*Op*/5, /*Renderer*/GIMT_Encode2(0), GIMT_Encode2(GICP_gi_buf_soffset),
        // (SIbuffer_atomic_smin:{ *:[i32] } i32:{ *:[i32] }:$vdata_in, v4i32:{ *:[v4i32] }:$rsrc, 0:{ *:[i32] }, i32:{ *:[i32] }:$voffset, (BUFSOffset:{ *:[i32] } i32:{ *:[i32] }:$soffset), (timm:{ *:[i32] }):$offset, (timm:{ *:[i32] }):$auxiliary, 0:{ *:[i1] })  =>  (BUFFER_ATOMIC_SMIN_OFFEN_RTN:{ *:[i32] } anonymous_15037:{ *:[i32] }:$vdata_in, VGPR_32:{ *:[i32] }:$voffset, SReg_128:{ *:[v4i32] }:$rsrc, SCSrc_b32:{ *:[i32] }:$soffset, (timm:{ *:[i32] }):$offset, (extract_cpol_set_glc:{ *:[i32] } ?:{ *:[i32] }:$auxiliary))
        GIR_BuildMI, /*InsnID*/0, /*Opcode*/GIMT_Encode2(AMDGPU::BUFFER_ATOMIC_SMIN_OFFEN_RTN),
        GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/0, // DstI[vdata]
        GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/1, // vdata_in
        GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/4, // voffset
        GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/2, // rsrc
        GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/0, // soffset
        GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/6, // offset
        GIR_CustomOperandRenderer, /*InsnID*/0, /*OldInsnID*/0, /*OpIdx*/7, /*OperandRenderer*/GIMT_Encode2(GICR_renderExtractCpolSetGLC), // auxiliary
        GIR_MergeMemOperands, /*InsnID*/0, /*NumInsns*/1, /*MergeInsnID's*/0,
        GIR_ConstrainSelectedInstOperands, /*InsnID*/0,
        GIR_EraseFromParent, /*InsnID*/0,
        // GIR_Coverage, 4779,
        GIR_Done,
      // Label 6163: @451203
      GIM_Try, /*On fail goto*//*Label 6164*/ GIMT_Encode4(451285), // Rule ID 4787 //
        GIM_CheckRegBankForClass, /*MI*/0, /*Op*/0, /*RC*/GIMT_Encode2(AMDGPU::AV_32RegClassID),
        GIM_CheckConstantInt8, /*MI*/0, /*Op*/3, 0,
        // MIs[0] offset
        GIM_CheckIsImm, /*MI*/0, /*Op*/6,
        // MIs[0] auxiliary
        GIM_CheckIsImm, /*MI*/0, /*Op*/7,
        // MIs[0] Operand 8
        GIM_CheckLiteralInt, /*MI*/0, /*Op*/8, GIMT_Encode8(0),
        GIM_CheckComplexPattern, /*MI*/0, /*Op*/5, /*Renderer*/GIMT_Encode2(0), GIMT_Encode2(GICP_gi_buf_soffset),
        // (SIbuffer_atomic_smin:{ *:[i32] } i32:{ *:[i32] }:$vdata_in, v4i32:{ *:[v4i32] }:$rsrc, 0:{ *:[i32] }, i32:{ *:[i32] }:$voffset, (BUFSOffset:{ *:[i32] } i32:{ *:[i32] }:$soffset), (timm:{ *:[i32] }):$offset, (timm:{ *:[i32] }):$auxiliary, 0:{ *:[i1] })  =>  (BUFFER_ATOMIC_SMIN_VBUFFER_OFFEN_RTN:{ *:[i32] } anonymous_15037:{ *:[i32] }:$vdata_in, VGPR_32:{ *:[i32] }:$voffset, SReg_128:{ *:[v4i32] }:$rsrc, SCSrc_b32:{ *:[i32] }:$soffset, (timm:{ *:[i32] }):$offset, (extract_cpol_set_glc:{ *:[i32] } ?:{ *:[i32] }:$auxiliary))
        GIR_BuildMI, /*InsnID*/0, /*Opcode*/GIMT_Encode2(AMDGPU::BUFFER_ATOMIC_SMIN_VBUFFER_OFFEN_RTN),
        GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/0, // DstI[vdata]
        GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/1, // vdata_in
        GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/4, // voffset
        GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/2, // rsrc
        GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/0, // soffset
        GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/6, // offset
        GIR_CustomOperandRenderer, /*InsnID*/0, /*OldInsnID*/0, /*OpIdx*/7, /*OperandRenderer*/GIMT_Encode2(GICR_renderExtractCpolSetGLC), // auxiliary
        GIR_MergeMemOperands, /*InsnID*/0, /*NumInsns*/1, /*MergeInsnID's*/0,
        GIR_ConstrainSelectedInstOperands, /*InsnID*/0,
        GIR_EraseFromParent, /*InsnID*/0,
        // GIR_Coverage, 4787,
        GIR_Done,
      // Label 6164: @451285
      GIM_Try, /*On fail goto*//*Label 6165*/ GIMT_Encode4(451355), // Rule ID 4782 //
        GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasUnrestrictedSOffset),
        GIM_CheckHasNoUse, /*MI*/0,
        GIM_CheckConstantInt8, /*MI*/0, /*Op*/4, 0,
        // MIs[0] offset
        GIM_CheckIsImm, /*MI*/0, /*Op*/6,
        // MIs[0] auxiliary
        GIM_CheckIsImm, /*MI*/0, /*Op*/7,
        // MIs[0] Operand 8
        GIM_CheckIsImm, /*MI*/0, /*Op*/8,
        GIM_CheckComplexPattern, /*MI*/0, /*Op*/5, /*Renderer*/GIMT_Encode2(0), GIMT_Encode2(GICP_gi_buf_soffset),
        // (SIbuffer_atomic_smin:{ *:[i32] } i32:{ *:[i32] }:$vdata_in, v4i32:{ *:[v4i32] }:$rsrc, i32:{ *:[i32] }:$vindex, 0:{ *:[i32] }, (BUFSOffset:{ *:[i32] } i32:{ *:[i32] }:$soffset), (timm:{ *:[i32] }):$offset, (timm:{ *:[i32] }):$auxiliary, (timm:{ *:[i1] }))<<P:Predicate_SIbuffer_atomic_smin_noret>>  =>  (BUFFER_ATOMIC_SMIN_IDXEN anonymous_15037:{ *:[i32] }:$vdata_in, VGPR_32:{ *:[i32] }:$vindex, SReg_128:{ *:[v4i32] }:$rsrc, SCSrc_b32:{ *:[i32] }:$soffset, (timm:{ *:[i32] }):$offset, (extract_cpol:{ *:[i32] } ?:{ *:[i32] }:$auxiliary))
        GIR_BuildMI, /*InsnID*/0, /*Opcode*/GIMT_Encode2(AMDGPU::BUFFER_ATOMIC_SMIN_IDXEN),
        GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/1, // vdata_in
        GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/3, // vindex
        GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/2, // rsrc
        GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/0, // soffset
        GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/6, // offset
        GIR_CustomOperandRenderer, /*InsnID*/0, /*OldInsnID*/0, /*OpIdx*/7, /*OperandRenderer*/GIMT_Encode2(GICR_renderExtractCPol), // auxiliary
        GIR_MergeMemOperands, /*InsnID*/0, /*NumInsns*/1, /*MergeInsnID's*/0,
        GIR_ConstrainSelectedInstOperands, /*InsnID*/0,
        GIR_EraseFromParent, /*InsnID*/0,
        // GIR_Coverage, 4782,
        GIR_Done,
      // Label 6165: @451355
      GIM_Try, /*On fail goto*//*Label 6166*/ GIMT_Encode4(451422), // Rule ID 4790 //
        GIM_CheckHasNoUse, /*MI*/0,
        GIM_CheckConstantInt8, /*MI*/0, /*Op*/4, 0,
        // MIs[0] offset
        GIM_CheckIsImm, /*MI*/0, /*Op*/6,
        // MIs[0] auxiliary
        GIM_CheckIsImm, /*MI*/0, /*Op*/7,
        // MIs[0] Operand 8
        GIM_CheckIsImm, /*MI*/0, /*Op*/8,
        GIM_CheckComplexPattern, /*MI*/0, /*Op*/5, /*Renderer*/GIMT_Encode2(0), GIMT_Encode2(GICP_gi_buf_soffset),
        // (SIbuffer_atomic_smin:{ *:[i32] } i32:{ *:[i32] }:$vdata_in, v4i32:{ *:[v4i32] }:$rsrc, i32:{ *:[i32] }:$vindex, 0:{ *:[i32] }, (BUFSOffset:{ *:[i32] } i32:{ *:[i32] }:$soffset), (timm:{ *:[i32] }):$offset, (timm:{ *:[i32] }):$auxiliary, (timm:{ *:[i1] }))<<P:Predicate_SIbuffer_atomic_smin_noret>>  =>  (BUFFER_ATOMIC_SMIN_VBUFFER_IDXEN anonymous_15037:{ *:[i32] }:$vdata_in, VGPR_32:{ *:[i32] }:$vindex, SReg_128:{ *:[v4i32] }:$rsrc, SCSrc_b32:{ *:[i32] }:$soffset, (timm:{ *:[i32] }):$offset, (extract_cpol:{ *:[i32] } ?:{ *:[i32] }:$auxiliary))
        GIR_BuildMI, /*InsnID*/0, /*Opcode*/GIMT_Encode2(AMDGPU::BUFFER_ATOMIC_SMIN_VBUFFER_IDXEN),
        GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/1, // vdata_in
        GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/3, // vindex
        GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/2, // rsrc
        GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/0, // soffset
        GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/6, // offset
        GIR_CustomOperandRenderer, /*InsnID*/0, /*OldInsnID*/0, /*OpIdx*/7, /*OperandRenderer*/GIMT_Encode2(GICR_renderExtractCPol), // auxiliary
        GIR_MergeMemOperands, /*InsnID*/0, /*NumInsns*/1, /*MergeInsnID's*/0,
        GIR_ConstrainSelectedInstOperands, /*InsnID*/0,
        GIR_EraseFromParent, /*InsnID*/0,
        // GIR_Coverage, 4790,
        GIR_Done,
      // Label 6166: @451422
      GIM_Try, /*On fail goto*//*Label 6167*/ GIMT_Encode4(451499), // Rule ID 4778 //
        GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasUnrestrictedSOffset),
        GIM_CheckRegBankForClass, /*MI*/0, /*Op*/0, /*RC*/GIMT_Encode2(AMDGPU::AV_32RegClassID),
        GIM_CheckConstantInt8, /*MI*/0, /*Op*/4, 0,
        // MIs[0] offset
        GIM_CheckIsImm, /*MI*/0, /*Op*/6,
        // MIs[0] auxiliary
        GIM_CheckIsImm, /*MI*/0, /*Op*/7,
        // MIs[0] Operand 8
        GIM_CheckIsImm, /*MI*/0, /*Op*/8,
        GIM_CheckComplexPattern, /*MI*/0, /*Op*/5, /*Renderer*/GIMT_Encode2(0), GIMT_Encode2(GICP_gi_buf_soffset),
        // (SIbuffer_atomic_smin:{ *:[i32] } i32:{ *:[i32] }:$vdata_in, v4i32:{ *:[v4i32] }:$rsrc, i32:{ *:[i32] }:$vindex, 0:{ *:[i32] }, (BUFSOffset:{ *:[i32] } i32:{ *:[i32] }:$soffset), (timm:{ *:[i32] }):$offset, (timm:{ *:[i32] }):$auxiliary, (timm:{ *:[i1] }))  =>  (BUFFER_ATOMIC_SMIN_IDXEN_RTN:{ *:[i32] } anonymous_15037:{ *:[i32] }:$vdata_in, VGPR_32:{ *:[i32] }:$vindex, SReg_128:{ *:[v4i32] }:$rsrc, SCSrc_b32:{ *:[i32] }:$soffset, (timm:{ *:[i32] }):$offset, (extract_cpol_set_glc:{ *:[i32] } ?:{ *:[i32] }:$auxiliary))
        GIR_BuildMI, /*InsnID*/0, /*Opcode*/GIMT_Encode2(AMDGPU::BUFFER_ATOMIC_SMIN_IDXEN_RTN),
        GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/0, // DstI[vdata]
        GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/1, // vdata_in
        GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/3, // vindex
        GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/2, // rsrc
        GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/0, // soffset
        GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/6, // offset
        GIR_CustomOperandRenderer, /*InsnID*/0, /*OldInsnID*/0, /*OpIdx*/7, /*OperandRenderer*/GIMT_Encode2(GICR_renderExtractCpolSetGLC), // auxiliary
        GIR_MergeMemOperands, /*InsnID*/0, /*NumInsns*/1, /*MergeInsnID's*/0,
        GIR_ConstrainSelectedInstOperands, /*InsnID*/0,
        GIR_EraseFromParent, /*InsnID*/0,
        // GIR_Coverage, 4778,
        GIR_Done,
      // Label 6167: @451499
      GIM_Try, /*On fail goto*//*Label 6168*/ GIMT_Encode4(451573), // Rule ID 4786 //
        GIM_CheckRegBankForClass, /*MI*/0, /*Op*/0, /*RC*/GIMT_Encode2(AMDGPU::AV_32RegClassID),
        GIM_CheckConstantInt8, /*MI*/0, /*Op*/4, 0,
        // MIs[0] offset
        GIM_CheckIsImm, /*MI*/0, /*Op*/6,
        // MIs[0] auxiliary
        GIM_CheckIsImm, /*MI*/0, /*Op*/7,
        // MIs[0] Operand 8
        GIM_CheckIsImm, /*MI*/0, /*Op*/8,
        GIM_CheckComplexPattern, /*MI*/0, /*Op*/5, /*Renderer*/GIMT_Encode2(0), GIMT_Encode2(GICP_gi_buf_soffset),
        // (SIbuffer_atomic_smin:{ *:[i32] } i32:{ *:[i32] }:$vdata_in, v4i32:{ *:[v4i32] }:$rsrc, i32:{ *:[i32] }:$vindex, 0:{ *:[i32] }, (BUFSOffset:{ *:[i32] } i32:{ *:[i32] }:$soffset), (timm:{ *:[i32] }):$offset, (timm:{ *:[i32] }):$auxiliary, (timm:{ *:[i1] }))  =>  (BUFFER_ATOMIC_SMIN_VBUFFER_IDXEN_RTN:{ *:[i32] } anonymous_15037:{ *:[i32] }:$vdata_in, VGPR_32:{ *:[i32] }:$vindex, SReg_128:{ *:[v4i32] }:$rsrc, SCSrc_b32:{ *:[i32] }:$soffset, (timm:{ *:[i32] }):$offset, (extract_cpol_set_glc:{ *:[i32] } ?:{ *:[i32] }:$auxiliary))
        GIR_BuildMI, /*InsnID*/0, /*Opcode*/GIMT_Encode2(AMDGPU::BUFFER_ATOMIC_SMIN_VBUFFER_IDXEN_RTN),
        GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/0, // DstI[vdata]
        GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/1, // vdata_in
        GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/3, // vindex
        GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/2, // rsrc
        GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/0, // soffset
        GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/6, // offset
        GIR_CustomOperandRenderer, /*InsnID*/0, /*OldInsnID*/0, /*OpIdx*/7, /*OperandRenderer*/GIMT_Encode2(GICR_renderExtractCpolSetGLC), // auxiliary
        GIR_MergeMemOperands, /*InsnID*/0, /*NumInsns*/1, /*MergeInsnID's*/0,
        GIR_ConstrainSelectedInstOperands, /*InsnID*/0,
        GIR_EraseFromParent, /*InsnID*/0,
        // GIR_Coverage, 4786,
        GIR_Done,
      // Label 6168: @451573
      GIM_Try, /*On fail goto*//*Label 6169*/ GIMT_Encode4(451679), // Rule ID 4784 //
        GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasUnrestrictedSOffset),
        GIM_CheckHasNoUse, /*MI*/0,
        // MIs[0] offset
        GIM_CheckIsImm, /*MI*/0, /*Op*/6,
        // MIs[0] auxiliary
        GIM_CheckIsImm, /*MI*/0, /*Op*/7,
        // MIs[0] Operand 8
        GIM_CheckIsImm, /*MI*/0, /*Op*/8,
        GIM_CheckComplexPattern, /*MI*/0, /*Op*/5, /*Renderer*/GIMT_Encode2(0), GIMT_Encode2(GICP_gi_buf_soffset),
        // (SIbuffer_atomic_smin:{ *:[i32] } i32:{ *:[i32] }:$vdata_in, v4i32:{ *:[v4i32] }:$rsrc, i32:{ *:[i32] }:$vindex, i32:{ *:[i32] }:$voffset, (BUFSOffset:{ *:[i32] } i32:{ *:[i32] }:$soffset), (timm:{ *:[i32] }):$offset, (timm:{ *:[i32] }):$auxiliary, (timm:{ *:[i1] }))<<P:Predicate_SIbuffer_atomic_smin_noret>>  =>  (BUFFER_ATOMIC_SMIN_BOTHEN anonymous_15037:{ *:[i32] }:$vdata_in, (REG_SEQUENCE:{ *:[i64] } VReg_64:{ *:[i32] }, VGPR_32:{ *:[i32] }:$vindex, sub0:{ *:[i32] }, VGPR_32:{ *:[i32] }:$voffset, sub1:{ *:[i32] }), SReg_128:{ *:[v4i32] }:$rsrc, SCSrc_b32:{ *:[i32] }:$soffset, (timm:{ *:[i32] }):$offset, (extract_cpol:{ *:[i32] } ?:{ *:[i32] }:$auxiliary))
        GIR_MakeTempReg, /*TempRegID*/0, /*TypeID*/GILLT_s64,
        GIR_BuildMI, /*InsnID*/1, /*Opcode*/GIMT_Encode2(TargetOpcode::REG_SEQUENCE),
        GIR_AddTempRegister, /*InsnID*/1, /*TempRegID*/0, /*TempRegFlags*/GIMT_Encode2(RegState::Define),
        GIR_Copy, /*NewInsnID*/1, /*OldInsnID*/0, /*OpIdx*/3, // vindex
        GIR_AddImm8, /*InsnID*/1, /*SubRegIndex*/3,
        GIR_Copy, /*NewInsnID*/1, /*OldInsnID*/0, /*OpIdx*/4, // voffset
        GIR_AddImm8, /*InsnID*/1, /*SubRegIndex*/11,
        GIR_ConstrainOperandRC, /*InsnID*/1, /*Op*/0, GIMT_Encode2(AMDGPU::VReg_64RegClassID),
        GIR_ConstrainOperandRC, /*InsnID*/1, /*Op*/1, GIMT_Encode2(AMDGPU::VGPR_32RegClassID),
        GIR_ConstrainOperandRC, /*InsnID*/1, /*Op*/3, GIMT_Encode2(AMDGPU::VGPR_32RegClassID),
        GIR_BuildMI, /*InsnID*/0, /*Opcode*/GIMT_Encode2(AMDGPU::BUFFER_ATOMIC_SMIN_BOTHEN),
        GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/1, // vdata_in
        GIR_AddSimpleTempRegister, /*InsnID*/0, /*TempRegID*/0,
        GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/2, // rsrc
        GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/0, // soffset
        GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/6, // offset
        GIR_CustomOperandRenderer, /*InsnID*/0, /*OldInsnID*/0, /*OpIdx*/7, /*OperandRenderer*/GIMT_Encode2(GICR_renderExtractCPol), // auxiliary
        GIR_MergeMemOperands, /*InsnID*/0, /*NumInsns*/1, /*MergeInsnID's*/0,
        GIR_ConstrainSelectedInstOperands, /*InsnID*/0,
        GIR_EraseFromParent, /*InsnID*/0,
        // GIR_Coverage, 4784,
        GIR_Done,
      // Label 6169: @451679
      GIM_Try, /*On fail goto*//*Label 6170*/ GIMT_Encode4(451782), // Rule ID 4792 //
        GIM_CheckHasNoUse, /*MI*/0,
        // MIs[0] offset
        GIM_CheckIsImm, /*MI*/0, /*Op*/6,
        // MIs[0] auxiliary
        GIM_CheckIsImm, /*MI*/0, /*Op*/7,
        // MIs[0] Operand 8
        GIM_CheckIsImm, /*MI*/0, /*Op*/8,
        GIM_CheckComplexPattern, /*MI*/0, /*Op*/5, /*Renderer*/GIMT_Encode2(0), GIMT_Encode2(GICP_gi_buf_soffset),
        // (SIbuffer_atomic_smin:{ *:[i32] } i32:{ *:[i32] }:$vdata_in, v4i32:{ *:[v4i32] }:$rsrc, i32:{ *:[i32] }:$vindex, i32:{ *:[i32] }:$voffset, (BUFSOffset:{ *:[i32] } i32:{ *:[i32] }:$soffset), (timm:{ *:[i32] }):$offset, (timm:{ *:[i32] }):$auxiliary, (timm:{ *:[i1] }))<<P:Predicate_SIbuffer_atomic_smin_noret>>  =>  (BUFFER_ATOMIC_SMIN_VBUFFER_BOTHEN anonymous_15037:{ *:[i32] }:$vdata_in, (REG_SEQUENCE:{ *:[i64] } VReg_64:{ *:[i32] }, VGPR_32:{ *:[i32] }:$vindex, sub0:{ *:[i32] }, VGPR_32:{ *:[i32] }:$voffset, sub1:{ *:[i32] }), SReg_128:{ *:[v4i32] }:$rsrc, SCSrc_b32:{ *:[i32] }:$soffset, (timm:{ *:[i32] }):$offset, (extract_cpol:{ *:[i32] } ?:{ *:[i32] }:$auxiliary))
        GIR_MakeTempReg, /*TempRegID*/0, /*TypeID*/GILLT_s64,
        GIR_BuildMI, /*InsnID*/1, /*Opcode*/GIMT_Encode2(TargetOpcode::REG_SEQUENCE),
        GIR_AddTempRegister, /*InsnID*/1, /*TempRegID*/0, /*TempRegFlags*/GIMT_Encode2(RegState::Define),
        GIR_Copy, /*NewInsnID*/1, /*OldInsnID*/0, /*OpIdx*/3, // vindex
        GIR_AddImm8, /*InsnID*/1, /*SubRegIndex*/3,
        GIR_Copy, /*NewInsnID*/1, /*OldInsnID*/0, /*OpIdx*/4, // voffset
        GIR_AddImm8, /*InsnID*/1, /*SubRegIndex*/11,
        GIR_ConstrainOperandRC, /*InsnID*/1, /*Op*/0, GIMT_Encode2(AMDGPU::VReg_64RegClassID),
        GIR_ConstrainOperandRC, /*InsnID*/1, /*Op*/1, GIMT_Encode2(AMDGPU::VGPR_32RegClassID),
        GIR_ConstrainOperandRC, /*InsnID*/1, /*Op*/3, GIMT_Encode2(AMDGPU::VGPR_32RegClassID),
        GIR_BuildMI, /*InsnID*/0, /*Opcode*/GIMT_Encode2(AMDGPU::BUFFER_ATOMIC_SMIN_VBUFFER_BOTHEN),
        GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/1, // vdata_in
        GIR_AddSimpleTempRegister, /*InsnID*/0, /*TempRegID*/0,
        GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/2, // rsrc
        GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/0, // soffset
        GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/6, // offset
        GIR_CustomOperandRenderer, /*InsnID*/0, /*OldInsnID*/0, /*OpIdx*/7, /*OperandRenderer*/GIMT_Encode2(GICR_renderExtractCPol), // auxiliary
        GIR_MergeMemOperands, /*InsnID*/0, /*NumInsns*/1, /*MergeInsnID's*/0,
        GIR_ConstrainSelectedInstOperands, /*InsnID*/0,
        GIR_EraseFromParent, /*InsnID*/0,
        // GIR_Coverage, 4792,
        GIR_Done,
      // Label 6170: @451782
      GIM_Try, /*On fail goto*//*Label 6171*/ GIMT_Encode4(451895), // Rule ID 4780 //
        GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasUnrestrictedSOffset),
        GIM_CheckRegBankForClass, /*MI*/0, /*Op*/0, /*RC*/GIMT_Encode2(AMDGPU::AV_32RegClassID),
        // MIs[0] offset
        GIM_CheckIsImm, /*MI*/0, /*Op*/6,
        // MIs[0] auxiliary
        GIM_CheckIsImm, /*MI*/0, /*Op*/7,
        // MIs[0] Operand 8
        GIM_CheckIsImm, /*MI*/0, /*Op*/8,
        GIM_CheckComplexPattern, /*MI*/0, /*Op*/5, /*Renderer*/GIMT_Encode2(0), GIMT_Encode2(GICP_gi_buf_soffset),
        // (SIbuffer_atomic_smin:{ *:[i32] } i32:{ *:[i32] }:$vdata_in, v4i32:{ *:[v4i32] }:$rsrc, i32:{ *:[i32] }:$vindex, i32:{ *:[i32] }:$voffset, (BUFSOffset:{ *:[i32] } i32:{ *:[i32] }:$soffset), (timm:{ *:[i32] }):$offset, (timm:{ *:[i32] }):$auxiliary, (timm:{ *:[i1] }))  =>  (BUFFER_ATOMIC_SMIN_BOTHEN_RTN:{ *:[i32] } anonymous_15037:{ *:[i32] }:$vdata_in, (REG_SEQUENCE:{ *:[i64] } VReg_64:{ *:[i32] }, VGPR_32:{ *:[i32] }:$vindex, sub0:{ *:[i32] }, VGPR_32:{ *:[i32] }:$voffset, sub1:{ *:[i32] }), SReg_128:{ *:[v4i32] }:$rsrc, SCSrc_b32:{ *:[i32] }:$soffset, (timm:{ *:[i32] }):$offset, (extract_cpol_set_glc:{ *:[i32] } ?:{ *:[i32] }:$auxiliary))
        GIR_MakeTempReg, /*TempRegID*/0, /*TypeID*/GILLT_s64,
        GIR_BuildMI, /*InsnID*/1, /*Opcode*/GIMT_Encode2(TargetOpcode::REG_SEQUENCE),
        GIR_AddTempRegister, /*InsnID*/1, /*TempRegID*/0, /*TempRegFlags*/GIMT_Encode2(RegState::Define),
        GIR_Copy, /*NewInsnID*/1, /*OldInsnID*/0, /*OpIdx*/3, // vindex
        GIR_AddImm8, /*InsnID*/1, /*SubRegIndex*/3,
        GIR_Copy, /*NewInsnID*/1, /*OldInsnID*/0, /*OpIdx*/4, // voffset
        GIR_AddImm8, /*InsnID*/1, /*SubRegIndex*/11,
        GIR_ConstrainOperandRC, /*InsnID*/1, /*Op*/0, GIMT_Encode2(AMDGPU::VReg_64RegClassID),
        GIR_ConstrainOperandRC, /*InsnID*/1, /*Op*/1, GIMT_Encode2(AMDGPU::VGPR_32RegClassID),
        GIR_ConstrainOperandRC, /*InsnID*/1, /*Op*/3, GIMT_Encode2(AMDGPU::VGPR_32RegClassID),
        GIR_BuildMI, /*InsnID*/0, /*Opcode*/GIMT_Encode2(AMDGPU::BUFFER_ATOMIC_SMIN_BOTHEN_RTN),
        GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/0, // DstI[vdata]
        GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/1, // vdata_in
        GIR_AddSimpleTempRegister, /*InsnID*/0, /*TempRegID*/0,
        GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/2, // rsrc
        GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/0, // soffset
        GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/6, // offset
        GIR_CustomOperandRenderer, /*InsnID*/0, /*OldInsnID*/0, /*OpIdx*/7, /*OperandRenderer*/GIMT_Encode2(GICR_renderExtractCpolSetGLC), // auxiliary
        GIR_MergeMemOperands, /*InsnID*/0, /*NumInsns*/1, /*MergeInsnID's*/0,
        GIR_ConstrainSelectedInstOperands, /*InsnID*/0,
        GIR_EraseFromParent, /*InsnID*/0,
        // GIR_Coverage, 4780,
        GIR_Done,
      // Label 6171: @451895
      GIM_Try, /*On fail goto*//*Label 6172*/ GIMT_Encode4(452005), // Rule ID 4788 //
        GIM_CheckRegBankForClass, /*MI*/0, /*Op*/0, /*RC*/GIMT_Encode2(AMDGPU::AV_32RegClassID),
        // MIs[0] offset
        GIM_CheckIsImm, /*MI*/0, /*Op*/6,
        // MIs[0] auxiliary
        GIM_CheckIsImm, /*MI*/0, /*Op*/7,
        // MIs[0] Operand 8
        GIM_CheckIsImm, /*MI*/0, /*Op*/8,
        GIM_CheckComplexPattern, /*MI*/0, /*Op*/5, /*Renderer*/GIMT_Encode2(0), GIMT_Encode2(GICP_gi_buf_soffset),
        // (SIbuffer_atomic_smin:{ *:[i32] } i32:{ *:[i32] }:$vdata_in, v4i32:{ *:[v4i32] }:$rsrc, i32:{ *:[i32] }:$vindex, i32:{ *:[i32] }:$voffset, (BUFSOffset:{ *:[i32] } i32:{ *:[i32] }:$soffset), (timm:{ *:[i32] }):$offset, (timm:{ *:[i32] }):$auxiliary, (timm:{ *:[i1] }))  =>  (BUFFER_ATOMIC_SMIN_VBUFFER_BOTHEN_RTN:{ *:[i32] } anonymous_15037:{ *:[i32] }:$vdata_in, (REG_SEQUENCE:{ *:[i64] } VReg_64:{ *:[i32] }, VGPR_32:{ *:[i32] }:$vindex, sub0:{ *:[i32] }, VGPR_32:{ *:[i32] }:$voffset, sub1:{ *:[i32] }), SReg_128:{ *:[v4i32] }:$rsrc, SCSrc_b32:{ *:[i32] }:$soffset, (timm:{ *:[i32] }):$offset, (extract_cpol_set_glc:{ *:[i32] } ?:{ *:[i32] }:$auxiliary))
        GIR_MakeTempReg, /*TempRegID*/0, /*TypeID*/GILLT_s64,
        GIR_BuildMI, /*InsnID*/1, /*Opcode*/GIMT_Encode2(TargetOpcode::REG_SEQUENCE),
        GIR_AddTempRegister, /*InsnID*/1, /*TempRegID*/0, /*TempRegFlags*/GIMT_Encode2(RegState::Define),
        GIR_Copy, /*NewInsnID*/1, /*OldInsnID*/0, /*OpIdx*/3, // vindex
        GIR_AddImm8, /*InsnID*/1, /*SubRegIndex*/3,
        GIR_Copy, /*NewInsnID*/1, /*OldInsnID*/0, /*OpIdx*/4, // voffset
        GIR_AddImm8, /*InsnID*/1, /*SubRegIndex*/11,
        GIR_ConstrainOperandRC, /*InsnID*/1, /*Op*/0, GIMT_Encode2(AMDGPU::VReg_64RegClassID),
        GIR_ConstrainOperandRC, /*InsnID*/1, /*Op*/1, GIMT_Encode2(AMDGPU::VGPR_32RegClassID),
        GIR_ConstrainOperandRC, /*InsnID*/1, /*Op*/3, GIMT_Encode2(AMDGPU::VGPR_32RegClassID),
        GIR_BuildMI, /*InsnID*/0, /*Opcode*/GIMT_Encode2(AMDGPU::BUFFER_ATOMIC_SMIN_VBUFFER_BOTHEN_RTN),
        GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/0, // DstI[vdata]
        GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/1, // vdata_in
        GIR_AddSimpleTempRegister, /*InsnID*/0, /*TempRegID*/0,
        GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/2, // rsrc
        GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/0, // soffset
        GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/6, // offset
        GIR_CustomOperandRenderer, /*InsnID*/0, /*OldInsnID*/0, /*OpIdx*/7, /*OperandRenderer*/GIMT_Encode2(GICR_renderExtractCpolSetGLC), // auxiliary
        GIR_MergeMemOperands, /*InsnID*/0, /*NumInsns*/1, /*MergeInsnID's*/0,
        GIR_ConstrainSelectedInstOperands, /*InsnID*/0,
        GIR_EraseFromParent, /*InsnID*/0,
        // GIR_Coverage, 4788,
        GIR_Done,
      // Label 6172: @452005
      GIM_Reject,
    // Label 6156: @452006
    GIM_Reject,
    // Label 6154: @452007
    GIM_Try, /*On fail goto*//*Label 6173*/ GIMT_Encode4(453393),
      GIM_CheckType, /*MI*/0, /*Op*/1, /*Type*/GILLT_s64,
      GIM_CheckType, /*MI*/0, /*Op*/2, /*Type*/GILLT_v4s32,
      GIM_CheckType, /*MI*/0, /*Op*/3, /*Type*/GILLT_s32,
      GIM_CheckType, /*MI*/0, /*Op*/4, /*Type*/GILLT_s32,
      GIM_CheckType, /*MI*/0, /*Op*/5, /*Type*/GILLT_s32,
      GIM_Try, /*On fail goto*//*Label 6174*/ GIMT_Encode4(452110), // Rule ID 4981 //
        GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasUnrestrictedSOffset),
        GIM_CheckHasNoUse, /*MI*/0,
        GIM_CheckConstantInt8, /*MI*/0, /*Op*/3, 0,
        GIM_CheckConstantInt8, /*MI*/0, /*Op*/4, 0,
        // MIs[0] offset
        GIM_CheckIsImm, /*MI*/0, /*Op*/6,
        // MIs[0] auxiliary
        GIM_CheckIsImm, /*MI*/0, /*Op*/7,
        // MIs[0] Operand 8
        GIM_CheckLiteralInt, /*MI*/0, /*Op*/8, GIMT_Encode8(0),
        GIM_CheckComplexPattern, /*MI*/0, /*Op*/5, /*Renderer*/GIMT_Encode2(0), GIMT_Encode2(GICP_gi_buf_soffset),
        // (SIbuffer_atomic_smin:{ *:[i64] } i64:{ *:[i64] }:$vdata_in, v4i32:{ *:[v4i32] }:$rsrc, 0:{ *:[i32] }, 0:{ *:[i32] }, (BUFSOffset:{ *:[i32] } i32:{ *:[i32] }:$soffset), (timm:{ *:[i32] }):$offset, (timm:{ *:[i32] }):$auxiliary, 0:{ *:[i1] })<<P:Predicate_SIbuffer_atomic_smin_noret>>  =>  (BUFFER_ATOMIC_SMIN_X2_OFFSET anonymous_15036:{ *:[i64] }:$vdata_in, SReg_128:{ *:[v4i32] }:$rsrc, SCSrc_b32:{ *:[i32] }:$soffset, (timm:{ *:[i32] }):$offset, (extract_cpol:{ *:[i32] } ?:{ *:[i32] }:$auxiliary))
        GIR_BuildMI, /*InsnID*/0, /*Opcode*/GIMT_Encode2(AMDGPU::BUFFER_ATOMIC_SMIN_X2_OFFSET),
        GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/1, // vdata_in
        GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/2, // rsrc
        GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/0, // soffset
        GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/6, // offset
        GIR_CustomOperandRenderer, /*InsnID*/0, /*OldInsnID*/0, /*OpIdx*/7, /*OperandRenderer*/GIMT_Encode2(GICR_renderExtractCPol), // auxiliary
        GIR_MergeMemOperands, /*InsnID*/0, /*NumInsns*/1, /*MergeInsnID's*/0,
        GIR_ConstrainSelectedInstOperands, /*InsnID*/0,
        GIR_EraseFromParent, /*InsnID*/0,
        // GIR_Coverage, 4981,
        GIR_Done,
      // Label 6174: @452110
      GIM_Try, /*On fail goto*//*Label 6175*/ GIMT_Encode4(452185), // Rule ID 4989 //
        GIM_CheckHasNoUse, /*MI*/0,
        GIM_CheckConstantInt8, /*MI*/0, /*Op*/3, 0,
        GIM_CheckConstantInt8, /*MI*/0, /*Op*/4, 0,
        // MIs[0] offset
        GIM_CheckIsImm, /*MI*/0, /*Op*/6,
        // MIs[0] auxiliary
        GIM_CheckIsImm, /*MI*/0, /*Op*/7,
        // MIs[0] Operand 8
        GIM_CheckLiteralInt, /*MI*/0, /*Op*/8, GIMT_Encode8(0),
        GIM_CheckComplexPattern, /*MI*/0, /*Op*/5, /*Renderer*/GIMT_Encode2(0), GIMT_Encode2(GICP_gi_buf_soffset),
        // (SIbuffer_atomic_smin:{ *:[i64] } i64:{ *:[i64] }:$vdata_in, v4i32:{ *:[v4i32] }:$rsrc, 0:{ *:[i32] }, 0:{ *:[i32] }, (BUFSOffset:{ *:[i32] } i32:{ *:[i32] }:$soffset), (timm:{ *:[i32] }):$offset, (timm:{ *:[i32] }):$auxiliary, 0:{ *:[i1] })<<P:Predicate_SIbuffer_atomic_smin_noret>>  =>  (BUFFER_ATOMIC_SMIN_X2_VBUFFER_OFFSET anonymous_15036:{ *:[i64] }:$vdata_in, SReg_128:{ *:[v4i32] }:$rsrc, SCSrc_b32:{ *:[i32] }:$soffset, (timm:{ *:[i32] }):$offset, (extract_cpol:{ *:[i32] } ?:{ *:[i32] }:$auxiliary))
        GIR_BuildMI, /*InsnID*/0, /*Opcode*/GIMT_Encode2(AMDGPU::BUFFER_ATOMIC_SMIN_X2_VBUFFER_OFFSET),
        GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/1, // vdata_in
        GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/2, // rsrc
        GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/0, // soffset
        GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/6, // offset
        GIR_CustomOperandRenderer, /*InsnID*/0, /*OldInsnID*/0, /*OpIdx*/7, /*OperandRenderer*/GIMT_Encode2(GICR_renderExtractCPol), // auxiliary
        GIR_MergeMemOperands, /*InsnID*/0, /*NumInsns*/1, /*MergeInsnID's*/0,
        GIR_ConstrainSelectedInstOperands, /*InsnID*/0,
        GIR_EraseFromParent, /*InsnID*/0,
        // GIR_Coverage, 4989,
        GIR_Done,
      // Label 6175: @452185
      GIM_Try, /*On fail goto*//*Label 6176*/ GIMT_Encode4(452270), // Rule ID 4977 //
        GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasUnrestrictedSOffset),
        GIM_CheckRegBankForClass, /*MI*/0, /*Op*/0, /*RC*/GIMT_Encode2(AMDGPU::AV_64RegClassID),
        GIM_CheckConstantInt8, /*MI*/0, /*Op*/3, 0,
        GIM_CheckConstantInt8, /*MI*/0, /*Op*/4, 0,
        // MIs[0] offset
        GIM_CheckIsImm, /*MI*/0, /*Op*/6,
        // MIs[0] auxiliary
        GIM_CheckIsImm, /*MI*/0, /*Op*/7,
        // MIs[0] Operand 8
        GIM_CheckLiteralInt, /*MI*/0, /*Op*/8, GIMT_Encode8(0),
        GIM_CheckComplexPattern, /*MI*/0, /*Op*/5, /*Renderer*/GIMT_Encode2(0), GIMT_Encode2(GICP_gi_buf_soffset),
        // (SIbuffer_atomic_smin:{ *:[i64] } i64:{ *:[i64] }:$vdata_in, v4i32:{ *:[v4i32] }:$rsrc, 0:{ *:[i32] }, 0:{ *:[i32] }, (BUFSOffset:{ *:[i32] } i32:{ *:[i32] }:$soffset), (timm:{ *:[i32] }):$offset, (timm:{ *:[i32] }):$auxiliary, 0:{ *:[i1] })  =>  (BUFFER_ATOMIC_SMIN_X2_OFFSET_RTN:{ *:[i64] } anonymous_15036:{ *:[i64] }:$vdata_in, SReg_128:{ *:[v4i32] }:$rsrc, SCSrc_b32:{ *:[i32] }:$soffset, (timm:{ *:[i32] }):$offset, (extract_cpol_set_glc:{ *:[i32] } ?:{ *:[i32] }:$auxiliary))
        GIR_BuildMI, /*InsnID*/0, /*Opcode*/GIMT_Encode2(AMDGPU::BUFFER_ATOMIC_SMIN_X2_OFFSET_RTN),
        GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/0, // DstI[vdata]
        GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/1, // vdata_in
        GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/2, // rsrc
        GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/0, // soffset
        GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/6, // offset
        GIR_CustomOperandRenderer, /*InsnID*/0, /*OldInsnID*/0, /*OpIdx*/7, /*OperandRenderer*/GIMT_Encode2(GICR_renderExtractCpolSetGLC), // auxiliary
        GIR_MergeMemOperands, /*InsnID*/0, /*NumInsns*/1, /*MergeInsnID's*/0,
        GIR_ConstrainSelectedInstOperands, /*InsnID*/0,
        GIR_EraseFromParent, /*InsnID*/0,
        // GIR_Coverage, 4977,
        GIR_Done,
      // Label 6176: @452270
      GIM_Try, /*On fail goto*//*Label 6177*/ GIMT_Encode4(452352), // Rule ID 4985 //
        GIM_CheckRegBankForClass, /*MI*/0, /*Op*/0, /*RC*/GIMT_Encode2(AMDGPU::AV_64RegClassID),
        GIM_CheckConstantInt8, /*MI*/0, /*Op*/3, 0,
        GIM_CheckConstantInt8, /*MI*/0, /*Op*/4, 0,
        // MIs[0] offset
        GIM_CheckIsImm, /*MI*/0, /*Op*/6,
        // MIs[0] auxiliary
        GIM_CheckIsImm, /*MI*/0, /*Op*/7,
        // MIs[0] Operand 8
        GIM_CheckLiteralInt, /*MI*/0, /*Op*/8, GIMT_Encode8(0),
        GIM_CheckComplexPattern, /*MI*/0, /*Op*/5, /*Renderer*/GIMT_Encode2(0), GIMT_Encode2(GICP_gi_buf_soffset),
        // (SIbuffer_atomic_smin:{ *:[i64] } i64:{ *:[i64] }:$vdata_in, v4i32:{ *:[v4i32] }:$rsrc, 0:{ *:[i32] }, 0:{ *:[i32] }, (BUFSOffset:{ *:[i32] } i32:{ *:[i32] }:$soffset), (timm:{ *:[i32] }):$offset, (timm:{ *:[i32] }):$auxiliary, 0:{ *:[i1] })  =>  (BUFFER_ATOMIC_SMIN_X2_VBUFFER_OFFSET_RTN:{ *:[i64] } anonymous_15036:{ *:[i64] }:$vdata_in, SReg_128:{ *:[v4i32] }:$rsrc, SCSrc_b32:{ *:[i32] }:$soffset, (timm:{ *:[i32] }):$offset, (extract_cpol_set_glc:{ *:[i32] } ?:{ *:[i32] }:$auxiliary))
        GIR_BuildMI, /*InsnID*/0, /*Opcode*/GIMT_Encode2(AMDGPU::BUFFER_ATOMIC_SMIN_X2_VBUFFER_OFFSET_RTN),
        GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/0, // DstI[vdata]
        GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/1, // vdata_in
        GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/2, // rsrc
        GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/0, // soffset
        GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/6, // offset
        GIR_CustomOperandRenderer, /*InsnID*/0, /*OldInsnID*/0, /*OpIdx*/7, /*OperandRenderer*/GIMT_Encode2(GICR_renderExtractCpolSetGLC), // auxiliary
        GIR_MergeMemOperands, /*InsnID*/0, /*NumInsns*/1, /*MergeInsnID's*/0,
        GIR_ConstrainSelectedInstOperands, /*InsnID*/0,
        GIR_EraseFromParent, /*InsnID*/0,
        // GIR_Coverage, 4985,
        GIR_Done,
      // Label 6177: @452352
      GIM_Try, /*On fail goto*//*Label 6178*/ GIMT_Encode4(452430), // Rule ID 4983 //
        GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasUnrestrictedSOffset),
        GIM_CheckHasNoUse, /*MI*/0,
        GIM_CheckConstantInt8, /*MI*/0, /*Op*/3, 0,
        // MIs[0] offset
        GIM_CheckIsImm, /*MI*/0, /*Op*/6,
        // MIs[0] auxiliary
        GIM_CheckIsImm, /*MI*/0, /*Op*/7,
        // MIs[0] Operand 8
        GIM_CheckLiteralInt, /*MI*/0, /*Op*/8, GIMT_Encode8(0),
        GIM_CheckComplexPattern, /*MI*/0, /*Op*/5, /*Renderer*/GIMT_Encode2(0), GIMT_Encode2(GICP_gi_buf_soffset),
        // (SIbuffer_atomic_smin:{ *:[i64] } i64:{ *:[i64] }:$vdata_in, v4i32:{ *:[v4i32] }:$rsrc, 0:{ *:[i32] }, i32:{ *:[i32] }:$voffset, (BUFSOffset:{ *:[i32] } i32:{ *:[i32] }:$soffset), (timm:{ *:[i32] }):$offset, (timm:{ *:[i32] }):$auxiliary, 0:{ *:[i1] })<<P:Predicate_SIbuffer_atomic_smin_noret>>  =>  (BUFFER_ATOMIC_SMIN_X2_OFFEN anonymous_15036:{ *:[i64] }:$vdata_in, VGPR_32:{ *:[i32] }:$voffset, SReg_128:{ *:[v4i32] }:$rsrc, SCSrc_b32:{ *:[i32] }:$soffset, (timm:{ *:[i32] }):$offset, (extract_cpol:{ *:[i32] } ?:{ *:[i32] }:$auxiliary))
        GIR_BuildMI, /*InsnID*/0, /*Opcode*/GIMT_Encode2(AMDGPU::BUFFER_ATOMIC_SMIN_X2_OFFEN),
        GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/1, // vdata_in
        GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/4, // voffset
        GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/2, // rsrc
        GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/0, // soffset
        GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/6, // offset
        GIR_CustomOperandRenderer, /*InsnID*/0, /*OldInsnID*/0, /*OpIdx*/7, /*OperandRenderer*/GIMT_Encode2(GICR_renderExtractCPol), // auxiliary
        GIR_MergeMemOperands, /*InsnID*/0, /*NumInsns*/1, /*MergeInsnID's*/0,
        GIR_ConstrainSelectedInstOperands, /*InsnID*/0,
        GIR_EraseFromParent, /*InsnID*/0,
        // GIR_Coverage, 4983,
        GIR_Done,
      // Label 6178: @452430
      GIM_Try, /*On fail goto*//*Label 6179*/ GIMT_Encode4(452505), // Rule ID 4991 //
        GIM_CheckHasNoUse, /*MI*/0,
        GIM_CheckConstantInt8, /*MI*/0, /*Op*/3, 0,
        // MIs[0] offset
        GIM_CheckIsImm, /*MI*/0, /*Op*/6,
        // MIs[0] auxiliary
        GIM_CheckIsImm, /*MI*/0, /*Op*/7,
        // MIs[0] Operand 8
        GIM_CheckLiteralInt, /*MI*/0, /*Op*/8, GIMT_Encode8(0),
        GIM_CheckComplexPattern, /*MI*/0, /*Op*/5, /*Renderer*/GIMT_Encode2(0), GIMT_Encode2(GICP_gi_buf_soffset),
        // (SIbuffer_atomic_smin:{ *:[i64] } i64:{ *:[i64] }:$vdata_in, v4i32:{ *:[v4i32] }:$rsrc, 0:{ *:[i32] }, i32:{ *:[i32] }:$voffset, (BUFSOffset:{ *:[i32] } i32:{ *:[i32] }:$soffset), (timm:{ *:[i32] }):$offset, (timm:{ *:[i32] }):$auxiliary, 0:{ *:[i1] })<<P:Predicate_SIbuffer_atomic_smin_noret>>  =>  (BUFFER_ATOMIC_SMIN_X2_VBUFFER_OFFEN anonymous_15036:{ *:[i64] }:$vdata_in, VGPR_32:{ *:[i32] }:$voffset, SReg_128:{ *:[v4i32] }:$rsrc, SCSrc_b32:{ *:[i32] }:$soffset, (timm:{ *:[i32] }):$offset, (extract_cpol:{ *:[i32] } ?:{ *:[i32] }:$auxiliary))
        GIR_BuildMI, /*InsnID*/0, /*Opcode*/GIMT_Encode2(AMDGPU::BUFFER_ATOMIC_SMIN_X2_VBUFFER_OFFEN),
        GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/1, // vdata_in
        GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/4, // voffset
        GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/2, // rsrc
        GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/0, // soffset
        GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/6, // offset
        GIR_CustomOperandRenderer, /*InsnID*/0, /*OldInsnID*/0, /*OpIdx*/7, /*OperandRenderer*/GIMT_Encode2(GICR_renderExtractCPol), // auxiliary
        GIR_MergeMemOperands, /*InsnID*/0, /*NumInsns*/1, /*MergeInsnID's*/0,
        GIR_ConstrainSelectedInstOperands, /*InsnID*/0,
        GIR_EraseFromParent, /*InsnID*/0,
        // GIR_Coverage, 4991,
        GIR_Done,
      // Label 6179: @452505
      GIM_Try, /*On fail goto*//*Label 6180*/ GIMT_Encode4(452590), // Rule ID 4979 //
        GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasUnrestrictedSOffset),
        GIM_CheckRegBankForClass, /*MI*/0, /*Op*/0, /*RC*/GIMT_Encode2(AMDGPU::AV_64RegClassID),
        GIM_CheckConstantInt8, /*MI*/0, /*Op*/3, 0,
        // MIs[0] offset
        GIM_CheckIsImm, /*MI*/0, /*Op*/6,
        // MIs[0] auxiliary
        GIM_CheckIsImm, /*MI*/0, /*Op*/7,
        // MIs[0] Operand 8
        GIM_CheckLiteralInt, /*MI*/0, /*Op*/8, GIMT_Encode8(0),
        GIM_CheckComplexPattern, /*MI*/0, /*Op*/5, /*Renderer*/GIMT_Encode2(0), GIMT_Encode2(GICP_gi_buf_soffset),
        // (SIbuffer_atomic_smin:{ *:[i64] } i64:{ *:[i64] }:$vdata_in, v4i32:{ *:[v4i32] }:$rsrc, 0:{ *:[i32] }, i32:{ *:[i32] }:$voffset, (BUFSOffset:{ *:[i32] } i32:{ *:[i32] }:$soffset), (timm:{ *:[i32] }):$offset, (timm:{ *:[i32] }):$auxiliary, 0:{ *:[i1] })  =>  (BUFFER_ATOMIC_SMIN_X2_OFFEN_RTN:{ *:[i64] } anonymous_15036:{ *:[i64] }:$vdata_in, VGPR_32:{ *:[i32] }:$voffset, SReg_128:{ *:[v4i32] }:$rsrc, SCSrc_b32:{ *:[i32] }:$soffset, (timm:{ *:[i32] }):$offset, (extract_cpol_set_glc:{ *:[i32] } ?:{ *:[i32] }:$auxiliary))
        GIR_BuildMI, /*InsnID*/0, /*Opcode*/GIMT_Encode2(AMDGPU::BUFFER_ATOMIC_SMIN_X2_OFFEN_RTN),
        GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/0, // DstI[vdata]
        GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/1, // vdata_in
        GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/4, // voffset
        GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/2, // rsrc
        GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/0, // soffset
        GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/6, // offset
        GIR_CustomOperandRenderer, /*InsnID*/0, /*OldInsnID*/0, /*OpIdx*/7, /*OperandRenderer*/GIMT_Encode2(GICR_renderExtractCpolSetGLC), // auxiliary
        GIR_MergeMemOperands, /*InsnID*/0, /*NumInsns*/1, /*MergeInsnID's*/0,
        GIR_ConstrainSelectedInstOperands, /*InsnID*/0,
        GIR_EraseFromParent, /*InsnID*/0,
        // GIR_Coverage, 4979,
        GIR_Done,
      // Label 6180: @452590
      GIM_Try, /*On fail goto*//*Label 6181*/ GIMT_Encode4(452672), // Rule ID 4987 //
        GIM_CheckRegBankForClass, /*MI*/0, /*Op*/0, /*RC*/GIMT_Encode2(AMDGPU::AV_64RegClassID),
        GIM_CheckConstantInt8, /*MI*/0, /*Op*/3, 0,
        // MIs[0] offset
        GIM_CheckIsImm, /*MI*/0, /*Op*/6,
        // MIs[0] auxiliary
        GIM_CheckIsImm, /*MI*/0, /*Op*/7,
        // MIs[0] Operand 8
        GIM_CheckLiteralInt, /*MI*/0, /*Op*/8, GIMT_Encode8(0),
        GIM_CheckComplexPattern, /*MI*/0, /*Op*/5, /*Renderer*/GIMT_Encode2(0), GIMT_Encode2(GICP_gi_buf_soffset),
        // (SIbuffer_atomic_smin:{ *:[i64] } i64:{ *:[i64] }:$vdata_in, v4i32:{ *:[v4i32] }:$rsrc, 0:{ *:[i32] }, i32:{ *:[i32] }:$voffset, (BUFSOffset:{ *:[i32] } i32:{ *:[i32] }:$soffset), (timm:{ *:[i32] }):$offset, (timm:{ *:[i32] }):$auxiliary, 0:{ *:[i1] })  =>  (BUFFER_ATOMIC_SMIN_X2_VBUFFER_OFFEN_RTN:{ *:[i64] } anonymous_15036:{ *:[i64] }:$vdata_in, VGPR_32:{ *:[i32] }:$voffset, SReg_128:{ *:[v4i32] }:$rsrc, SCSrc_b32:{ *:[i32] }:$soffset, (timm:{ *:[i32] }):$offset, (extract_cpol_set_glc:{ *:[i32] } ?:{ *:[i32] }:$auxiliary))
        GIR_BuildMI, /*InsnID*/0, /*Opcode*/GIMT_Encode2(AMDGPU::BUFFER_ATOMIC_SMIN_X2_VBUFFER_OFFEN_RTN),
        GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/0, // DstI[vdata]
        GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/1, // vdata_in
        GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/4, // voffset
        GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/2, // rsrc
        GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/0, // soffset
        GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/6, // offset
        GIR_CustomOperandRenderer, /*InsnID*/0, /*OldInsnID*/0, /*OpIdx*/7, /*OperandRenderer*/GIMT_Encode2(GICR_renderExtractCpolSetGLC), // auxiliary
        GIR_MergeMemOperands, /*InsnID*/0, /*NumInsns*/1, /*MergeInsnID's*/0,
        GIR_ConstrainSelectedInstOperands, /*InsnID*/0,
        GIR_EraseFromParent, /*InsnID*/0,
        // GIR_Coverage, 4987,
        GIR_Done,
      // Label 6181: @452672
      GIM_Try, /*On fail goto*//*Label 6182*/ GIMT_Encode4(452742), // Rule ID 4982 //
        GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasUnrestrictedSOffset),
        GIM_CheckHasNoUse, /*MI*/0,
        GIM_CheckConstantInt8, /*MI*/0, /*Op*/4, 0,
        // MIs[0] offset
        GIM_CheckIsImm, /*MI*/0, /*Op*/6,
        // MIs[0] auxiliary
        GIM_CheckIsImm, /*MI*/0, /*Op*/7,
        // MIs[0] Operand 8
        GIM_CheckIsImm, /*MI*/0, /*Op*/8,
        GIM_CheckComplexPattern, /*MI*/0, /*Op*/5, /*Renderer*/GIMT_Encode2(0), GIMT_Encode2(GICP_gi_buf_soffset),
        // (SIbuffer_atomic_smin:{ *:[i64] } i64:{ *:[i64] }:$vdata_in, v4i32:{ *:[v4i32] }:$rsrc, i32:{ *:[i32] }:$vindex, 0:{ *:[i32] }, (BUFSOffset:{ *:[i32] } i32:{ *:[i32] }:$soffset), (timm:{ *:[i32] }):$offset, (timm:{ *:[i32] }):$auxiliary, (timm:{ *:[i1] }))<<P:Predicate_SIbuffer_atomic_smin_noret>>  =>  (BUFFER_ATOMIC_SMIN_X2_IDXEN anonymous_15036:{ *:[i64] }:$vdata_in, VGPR_32:{ *:[i32] }:$vindex, SReg_128:{ *:[v4i32] }:$rsrc, SCSrc_b32:{ *:[i32] }:$soffset, (timm:{ *:[i32] }):$offset, (extract_cpol:{ *:[i32] } ?:{ *:[i32] }:$auxiliary))
        GIR_BuildMI, /*InsnID*/0, /*Opcode*/GIMT_Encode2(AMDGPU::BUFFER_ATOMIC_SMIN_X2_IDXEN),
        GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/1, // vdata_in
        GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/3, // vindex
        GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/2, // rsrc
        GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/0, // soffset
        GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/6, // offset
        GIR_CustomOperandRenderer, /*InsnID*/0, /*OldInsnID*/0, /*OpIdx*/7, /*OperandRenderer*/GIMT_Encode2(GICR_renderExtractCPol), // auxiliary
        GIR_MergeMemOperands, /*InsnID*/0, /*NumInsns*/1, /*MergeInsnID's*/0,
        GIR_ConstrainSelectedInstOperands, /*InsnID*/0,
        GIR_EraseFromParent, /*InsnID*/0,
        // GIR_Coverage, 4982,
        GIR_Done,
      // Label 6182: @452742
      GIM_Try, /*On fail goto*//*Label 6183*/ GIMT_Encode4(452809), // Rule ID 4990 //
        GIM_CheckHasNoUse, /*MI*/0,
        GIM_CheckConstantInt8, /*MI*/0, /*Op*/4, 0,
        // MIs[0] offset
        GIM_CheckIsImm, /*MI*/0, /*Op*/6,
        // MIs[0] auxiliary
        GIM_CheckIsImm, /*MI*/0, /*Op*/7,
        // MIs[0] Operand 8
        GIM_CheckIsImm, /*MI*/0, /*Op*/8,
        GIM_CheckComplexPattern, /*MI*/0, /*Op*/5, /*Renderer*/GIMT_Encode2(0), GIMT_Encode2(GICP_gi_buf_soffset),
        // (SIbuffer_atomic_smin:{ *:[i64] } i64:{ *:[i64] }:$vdata_in, v4i32:{ *:[v4i32] }:$rsrc, i32:{ *:[i32] }:$vindex, 0:{ *:[i32] }, (BUFSOffset:{ *:[i32] } i32:{ *:[i32] }:$soffset), (timm:{ *:[i32] }):$offset, (timm:{ *:[i32] }):$auxiliary, (timm:{ *:[i1] }))<<P:Predicate_SIbuffer_atomic_smin_noret>>  =>  (BUFFER_ATOMIC_SMIN_X2_VBUFFER_IDXEN anonymous_15036:{ *:[i64] }:$vdata_in, VGPR_32:{ *:[i32] }:$vindex, SReg_128:{ *:[v4i32] }:$rsrc, SCSrc_b32:{ *:[i32] }:$soffset, (timm:{ *:[i32] }):$offset, (extract_cpol:{ *:[i32] } ?:{ *:[i32] }:$auxiliary))
        GIR_BuildMI, /*InsnID*/0, /*Opcode*/GIMT_Encode2(AMDGPU::BUFFER_ATOMIC_SMIN_X2_VBUFFER_IDXEN),
        GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/1, // vdata_in
        GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/3, // vindex
        GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/2, // rsrc
        GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/0, // soffset
        GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/6, // offset
        GIR_CustomOperandRenderer, /*InsnID*/0, /*OldInsnID*/0, /*OpIdx*/7, /*OperandRenderer*/GIMT_Encode2(GICR_renderExtractCPol), // auxiliary
        GIR_MergeMemOperands, /*InsnID*/0, /*NumInsns*/1, /*MergeInsnID's*/0,
        GIR_ConstrainSelectedInstOperands, /*InsnID*/0,
        GIR_EraseFromParent, /*InsnID*/0,
        // GIR_Coverage, 4990,
        GIR_Done,
      // Label 6183: @452809
      GIM_Try, /*On fail goto*//*Label 6184*/ GIMT_Encode4(452886), // Rule ID 4978 //
        GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasUnrestrictedSOffset),
        GIM_CheckRegBankForClass, /*MI*/0, /*Op*/0, /*RC*/GIMT_Encode2(AMDGPU::AV_64RegClassID),
        GIM_CheckConstantInt8, /*MI*/0, /*Op*/4, 0,
        // MIs[0] offset
        GIM_CheckIsImm, /*MI*/0, /*Op*/6,
        // MIs[0] auxiliary
        GIM_CheckIsImm, /*MI*/0, /*Op*/7,
        // MIs[0] Operand 8
        GIM_CheckIsImm, /*MI*/0, /*Op*/8,
        GIM_CheckComplexPattern, /*MI*/0, /*Op*/5, /*Renderer*/GIMT_Encode2(0), GIMT_Encode2(GICP_gi_buf_soffset),
        // (SIbuffer_atomic_smin:{ *:[i64] } i64:{ *:[i64] }:$vdata_in, v4i32:{ *:[v4i32] }:$rsrc, i32:{ *:[i32] }:$vindex, 0:{ *:[i32] }, (BUFSOffset:{ *:[i32] } i32:{ *:[i32] }:$soffset), (timm:{ *:[i32] }):$offset, (timm:{ *:[i32] }):$auxiliary, (timm:{ *:[i1] }))  =>  (BUFFER_ATOMIC_SMIN_X2_IDXEN_RTN:{ *:[i64] } anonymous_15036:{ *:[i64] }:$vdata_in, VGPR_32:{ *:[i32] }:$vindex, SReg_128:{ *:[v4i32] }:$rsrc, SCSrc_b32:{ *:[i32] }:$soffset, (timm:{ *:[i32] }):$offset, (extract_cpol_set_glc:{ *:[i32] } ?:{ *:[i32] }:$auxiliary))
        GIR_BuildMI, /*InsnID*/0, /*Opcode*/GIMT_Encode2(AMDGPU::BUFFER_ATOMIC_SMIN_X2_IDXEN_RTN),
        GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/0, // DstI[vdata]
        GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/1, // vdata_in
        GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/3, // vindex
        GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/2, // rsrc
        GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/0, // soffset
        GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/6, // offset
        GIR_CustomOperandRenderer, /*InsnID*/0, /*OldInsnID*/0, /*OpIdx*/7, /*OperandRenderer*/GIMT_Encode2(GICR_renderExtractCpolSetGLC), // auxiliary
        GIR_MergeMemOperands, /*InsnID*/0, /*NumInsns*/1, /*MergeInsnID's*/0,
        GIR_ConstrainSelectedInstOperands, /*InsnID*/0,
        GIR_EraseFromParent, /*InsnID*/0,
        // GIR_Coverage, 4978,
        GIR_Done,
      // Label 6184: @452886
      GIM_Try, /*On fail goto*//*Label 6185*/ GIMT_Encode4(452960), // Rule ID 4986 //
        GIM_CheckRegBankForClass, /*MI*/0, /*Op*/0, /*RC*/GIMT_Encode2(AMDGPU::AV_64RegClassID),
        GIM_CheckConstantInt8, /*MI*/0, /*Op*/4, 0,
        // MIs[0] offset
        GIM_CheckIsImm, /*MI*/0, /*Op*/6,
        // MIs[0] auxiliary
        GIM_CheckIsImm, /*MI*/0, /*Op*/7,
        // MIs[0] Operand 8
        GIM_CheckIsImm, /*MI*/0, /*Op*/8,
        GIM_CheckComplexPattern, /*MI*/0, /*Op*/5, /*Renderer*/GIMT_Encode2(0), GIMT_Encode2(GICP_gi_buf_soffset),
        // (SIbuffer_atomic_smin:{ *:[i64] } i64:{ *:[i64] }:$vdata_in, v4i32:{ *:[v4i32] }:$rsrc, i32:{ *:[i32] }:$vindex, 0:{ *:[i32] }, (BUFSOffset:{ *:[i32] } i32:{ *:[i32] }:$soffset), (timm:{ *:[i32] }):$offset, (timm:{ *:[i32] }):$auxiliary, (timm:{ *:[i1] }))  =>  (BUFFER_ATOMIC_SMIN_X2_VBUFFER_IDXEN_RTN:{ *:[i64] } anonymous_15036:{ *:[i64] }:$vdata_in, VGPR_32:{ *:[i32] }:$vindex, SReg_128:{ *:[v4i32] }:$rsrc, SCSrc_b32:{ *:[i32] }:$soffset, (timm:{ *:[i32] }):$offset, (extract_cpol_set_glc:{ *:[i32] } ?:{ *:[i32] }:$auxiliary))
        GIR_BuildMI, /*InsnID*/0, /*Opcode*/GIMT_Encode2(AMDGPU::BUFFER_ATOMIC_SMIN_X2_VBUFFER_IDXEN_RTN),
        GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/0, // DstI[vdata]
        GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/1, // vdata_in
        GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/3, // vindex
        GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/2, // rsrc
        GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/0, // soffset
        GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/6, // offset
        GIR_CustomOperandRenderer, /*InsnID*/0, /*OldInsnID*/0, /*OpIdx*/7, /*OperandRenderer*/GIMT_Encode2(GICR_renderExtractCpolSetGLC), // auxiliary
        GIR_MergeMemOperands, /*InsnID*/0, /*NumInsns*/1, /*MergeInsnID's*/0,
        GIR_ConstrainSelectedInstOperands, /*InsnID*/0,
        GIR_EraseFromParent, /*InsnID*/0,
        // GIR_Coverage, 4986,
        GIR_Done,
      // Label 6185: @452960
      GIM_Try, /*On fail goto*//*Label 6186*/ GIMT_Encode4(453066), // Rule ID 4984 //
        GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasUnrestrictedSOffset),
        GIM_CheckHasNoUse, /*MI*/0,
        // MIs[0] offset
        GIM_CheckIsImm, /*MI*/0, /*Op*/6,
        // MIs[0] auxiliary
        GIM_CheckIsImm, /*MI*/0, /*Op*/7,
        // MIs[0] Operand 8
        GIM_CheckIsImm, /*MI*/0, /*Op*/8,
        GIM_CheckComplexPattern, /*MI*/0, /*Op*/5, /*Renderer*/GIMT_Encode2(0), GIMT_Encode2(GICP_gi_buf_soffset),
        // (SIbuffer_atomic_smin:{ *:[i64] } i64:{ *:[i64] }:$vdata_in, v4i32:{ *:[v4i32] }:$rsrc, i32:{ *:[i32] }:$vindex, i32:{ *:[i32] }:$voffset, (BUFSOffset:{ *:[i32] } i32:{ *:[i32] }:$soffset), (timm:{ *:[i32] }):$offset, (timm:{ *:[i32] }):$auxiliary, (timm:{ *:[i1] }))<<P:Predicate_SIbuffer_atomic_smin_noret>>  =>  (BUFFER_ATOMIC_SMIN_X2_BOTHEN anonymous_15036:{ *:[i64] }:$vdata_in, (REG_SEQUENCE:{ *:[i64] } VReg_64:{ *:[i32] }, VGPR_32:{ *:[i32] }:$vindex, sub0:{ *:[i32] }, VGPR_32:{ *:[i32] }:$voffset, sub1:{ *:[i32] }), SReg_128:{ *:[v4i32] }:$rsrc, SCSrc_b32:{ *:[i32] }:$soffset, (timm:{ *:[i32] }):$offset, (extract_cpol:{ *:[i32] } ?:{ *:[i32] }:$auxiliary))
        GIR_MakeTempReg, /*TempRegID*/0, /*TypeID*/GILLT_s64,
        GIR_BuildMI, /*InsnID*/1, /*Opcode*/GIMT_Encode2(TargetOpcode::REG_SEQUENCE),
        GIR_AddTempRegister, /*InsnID*/1, /*TempRegID*/0, /*TempRegFlags*/GIMT_Encode2(RegState::Define),
        GIR_Copy, /*NewInsnID*/1, /*OldInsnID*/0, /*OpIdx*/3, // vindex
        GIR_AddImm8, /*InsnID*/1, /*SubRegIndex*/3,
        GIR_Copy, /*NewInsnID*/1, /*OldInsnID*/0, /*OpIdx*/4, // voffset
        GIR_AddImm8, /*InsnID*/1, /*SubRegIndex*/11,
        GIR_ConstrainOperandRC, /*InsnID*/1, /*Op*/0, GIMT_Encode2(AMDGPU::VReg_64RegClassID),
        GIR_ConstrainOperandRC, /*InsnID*/1, /*Op*/1, GIMT_Encode2(AMDGPU::VGPR_32RegClassID),
        GIR_ConstrainOperandRC, /*InsnID*/1, /*Op*/3, GIMT_Encode2(AMDGPU::VGPR_32RegClassID),
        GIR_BuildMI, /*InsnID*/0, /*Opcode*/GIMT_Encode2(AMDGPU::BUFFER_ATOMIC_SMIN_X2_BOTHEN),
        GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/1, // vdata_in
        GIR_AddSimpleTempRegister, /*InsnID*/0, /*TempRegID*/0,
        GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/2, // rsrc
        GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/0, // soffset
        GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/6, // offset
        GIR_CustomOperandRenderer, /*InsnID*/0, /*OldInsnID*/0, /*OpIdx*/7, /*OperandRenderer*/GIMT_Encode2(GICR_renderExtractCPol), // auxiliary
        GIR_MergeMemOperands, /*InsnID*/0, /*NumInsns*/1, /*MergeInsnID's*/0,
        GIR_ConstrainSelectedInstOperands, /*InsnID*/0,
        GIR_EraseFromParent, /*InsnID*/0,
        // GIR_Coverage, 4984,
        GIR_Done,
      // Label 6186: @453066
      GIM_Try, /*On fail goto*//*Label 6187*/ GIMT_Encode4(453169), // Rule ID 4992 //
        GIM_CheckHasNoUse, /*MI*/0,
        // MIs[0] offset
        GIM_CheckIsImm, /*MI*/0, /*Op*/6,
        // MIs[0] auxiliary
        GIM_CheckIsImm, /*MI*/0, /*Op*/7,
        // MIs[0] Operand 8
        GIM_CheckIsImm, /*MI*/0, /*Op*/8,
        GIM_CheckComplexPattern, /*MI*/0, /*Op*/5, /*Renderer*/GIMT_Encode2(0), GIMT_Encode2(GICP_gi_buf_soffset),
        // (SIbuffer_atomic_smin:{ *:[i64] } i64:{ *:[i64] }:$vdata_in, v4i32:{ *:[v4i32] }:$rsrc, i32:{ *:[i32] }:$vindex, i32:{ *:[i32] }:$voffset, (BUFSOffset:{ *:[i32] } i32:{ *:[i32] }:$soffset), (timm:{ *:[i32] }):$offset, (timm:{ *:[i32] }):$auxiliary, (timm:{ *:[i1] }))<<P:Predicate_SIbuffer_atomic_smin_noret>>  =>  (BUFFER_ATOMIC_SMIN_X2_VBUFFER_BOTHEN anonymous_15036:{ *:[i64] }:$vdata_in, (REG_SEQUENCE:{ *:[i64] } VReg_64:{ *:[i32] }, VGPR_32:{ *:[i32] }:$vindex, sub0:{ *:[i32] }, VGPR_32:{ *:[i32] }:$voffset, sub1:{ *:[i32] }), SReg_128:{ *:[v4i32] }:$rsrc, SCSrc_b32:{ *:[i32] }:$soffset, (timm:{ *:[i32] }):$offset, (extract_cpol:{ *:[i32] } ?:{ *:[i32] }:$auxiliary))
        GIR_MakeTempReg, /*TempRegID*/0, /*TypeID*/GILLT_s64,
        GIR_BuildMI, /*InsnID*/1, /*Opcode*/GIMT_Encode2(TargetOpcode::REG_SEQUENCE),
        GIR_AddTempRegister, /*InsnID*/1, /*TempRegID*/0, /*TempRegFlags*/GIMT_Encode2(RegState::Define),
        GIR_Copy, /*NewInsnID*/1, /*OldInsnID*/0, /*OpIdx*/3, // vindex
        GIR_AddImm8, /*InsnID*/1, /*SubRegIndex*/3,
        GIR_Copy, /*NewInsnID*/1, /*OldInsnID*/0, /*OpIdx*/4, // voffset
        GIR_AddImm8, /*InsnID*/1, /*SubRegIndex*/11,
        GIR_ConstrainOperandRC, /*InsnID*/1, /*Op*/0, GIMT_Encode2(AMDGPU::VReg_64RegClassID),
        GIR_ConstrainOperandRC, /*InsnID*/1, /*Op*/1, GIMT_Encode2(AMDGPU::VGPR_32RegClassID),
        GIR_ConstrainOperandRC, /*InsnID*/1, /*Op*/3, GIMT_Encode2(AMDGPU::VGPR_32RegClassID),
        GIR_BuildMI, /*InsnID*/0, /*Opcode*/GIMT_Encode2(AMDGPU::BUFFER_ATOMIC_SMIN_X2_VBUFFER_BOTHEN),
        GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/1, // vdata_in
        GIR_AddSimpleTempRegister, /*InsnID*/0, /*TempRegID*/0,
        GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/2, // rsrc
        GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/0, // soffset
        GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/6, // offset
        GIR_CustomOperandRenderer, /*InsnID*/0, /*OldInsnID*/0, /*OpIdx*/7, /*OperandRenderer*/GIMT_Encode2(GICR_renderExtractCPol), // auxiliary
        GIR_MergeMemOperands, /*InsnID*/0, /*NumInsns*/1, /*MergeInsnID's*/0,
        GIR_ConstrainSelectedInstOperands, /*InsnID*/0,
        GIR_EraseFromParent, /*InsnID*/0,
        // GIR_Coverage, 4992,
        GIR_Done,
      // Label 6187: @453169
      GIM_Try, /*On fail goto*//*Label 6188*/ GIMT_Encode4(453282), // Rule ID 4980 //
        GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasUnrestrictedSOffset),
        GIM_CheckRegBankForClass, /*MI*/0, /*Op*/0, /*RC*/GIMT_Encode2(AMDGPU::AV_64RegClassID),
        // MIs[0] offset
        GIM_CheckIsImm, /*MI*/0, /*Op*/6,
        // MIs[0] auxiliary
        GIM_CheckIsImm, /*MI*/0, /*Op*/7,
        // MIs[0] Operand 8
        GIM_CheckIsImm, /*MI*/0, /*Op*/8,
        GIM_CheckComplexPattern, /*MI*/0, /*Op*/5, /*Renderer*/GIMT_Encode2(0), GIMT_Encode2(GICP_gi_buf_soffset),
        // (SIbuffer_atomic_smin:{ *:[i64] } i64:{ *:[i64] }:$vdata_in, v4i32:{ *:[v4i32] }:$rsrc, i32:{ *:[i32] }:$vindex, i32:{ *:[i32] }:$voffset, (BUFSOffset:{ *:[i32] } i32:{ *:[i32] }:$soffset), (timm:{ *:[i32] }):$offset, (timm:{ *:[i32] }):$auxiliary, (timm:{ *:[i1] }))  =>  (BUFFER_ATOMIC_SMIN_X2_BOTHEN_RTN:{ *:[i64] } anonymous_15036:{ *:[i64] }:$vdata_in, (REG_SEQUENCE:{ *:[i64] } VReg_64:{ *:[i32] }, VGPR_32:{ *:[i32] }:$vindex, sub0:{ *:[i32] }, VGPR_32:{ *:[i32] }:$voffset, sub1:{ *:[i32] }), SReg_128:{ *:[v4i32] }:$rsrc, SCSrc_b32:{ *:[i32] }:$soffset, (timm:{ *:[i32] }):$offset, (extract_cpol_set_glc:{ *:[i32] } ?:{ *:[i32] }:$auxiliary))
        GIR_MakeTempReg, /*TempRegID*/0, /*TypeID*/GILLT_s64,
        GIR_BuildMI, /*InsnID*/1, /*Opcode*/GIMT_Encode2(TargetOpcode::REG_SEQUENCE),
        GIR_AddTempRegister, /*InsnID*/1, /*TempRegID*/0, /*TempRegFlags*/GIMT_Encode2(RegState::Define),
        GIR_Copy, /*NewInsnID*/1, /*OldInsnID*/0, /*OpIdx*/3, // vindex
        GIR_AddImm8, /*InsnID*/1, /*SubRegIndex*/3,
        GIR_Copy, /*NewInsnID*/1, /*OldInsnID*/0, /*OpIdx*/4, // voffset
        GIR_AddImm8, /*InsnID*/1, /*SubRegIndex*/11,
        GIR_ConstrainOperandRC, /*InsnID*/1, /*Op*/0, GIMT_Encode2(AMDGPU::VReg_64RegClassID),
        GIR_ConstrainOperandRC, /*InsnID*/1, /*Op*/1, GIMT_Encode2(AMDGPU::VGPR_32RegClassID),
        GIR_ConstrainOperandRC, /*InsnID*/1, /*Op*/3, GIMT_Encode2(AMDGPU::VGPR_32RegClassID),
        GIR_BuildMI, /*InsnID*/0, /*Opcode*/GIMT_Encode2(AMDGPU::BUFFER_ATOMIC_SMIN_X2_BOTHEN_RTN),
        GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/0, // DstI[vdata]
        GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/1, // vdata_in
        GIR_AddSimpleTempRegister, /*InsnID*/0, /*TempRegID*/0,
        GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/2, // rsrc
        GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/0, // soffset
        GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/6, // offset
        GIR_CustomOperandRenderer, /*InsnID*/0, /*OldInsnID*/0, /*OpIdx*/7, /*OperandRenderer*/GIMT_Encode2(GICR_renderExtractCpolSetGLC), // auxiliary
        GIR_MergeMemOperands, /*InsnID*/0, /*NumInsns*/1, /*MergeInsnID's*/0,
        GIR_ConstrainSelectedInstOperands, /*InsnID*/0,
        GIR_EraseFromParent, /*InsnID*/0,
        // GIR_Coverage, 4980,
        GIR_Done,
      // Label 6188: @453282
      GIM_Try, /*On fail goto*//*Label 6189*/ GIMT_Encode4(453392), // Rule ID 4988 //
        GIM_CheckRegBankForClass, /*MI*/0, /*Op*/0, /*RC*/GIMT_Encode2(AMDGPU::AV_64RegClassID),
        // MIs[0] offset
        GIM_CheckIsImm, /*MI*/0, /*Op*/6,
        // MIs[0] auxiliary
        GIM_CheckIsImm, /*MI*/0, /*Op*/7,
        // MIs[0] Operand 8
        GIM_CheckIsImm, /*MI*/0, /*Op*/8,
        GIM_CheckComplexPattern, /*MI*/0, /*Op*/5, /*Renderer*/GIMT_Encode2(0), GIMT_Encode2(GICP_gi_buf_soffset),
        // (SIbuffer_atomic_smin:{ *:[i64] } i64:{ *:[i64] }:$vdata_in, v4i32:{ *:[v4i32] }:$rsrc, i32:{ *:[i32] }:$vindex, i32:{ *:[i32] }:$voffset, (BUFSOffset:{ *:[i32] } i32:{ *:[i32] }:$soffset), (timm:{ *:[i32] }):$offset, (timm:{ *:[i32] }):$auxiliary, (timm:{ *:[i1] }))  =>  (BUFFER_ATOMIC_SMIN_X2_VBUFFER_BOTHEN_RTN:{ *:[i64] } anonymous_15036:{ *:[i64] }:$vdata_in, (REG_SEQUENCE:{ *:[i64] } VReg_64:{ *:[i32] }, VGPR_32:{ *:[i32] }:$vindex, sub0:{ *:[i32] }, VGPR_32:{ *:[i32] }:$voffset, sub1:{ *:[i32] }), SReg_128:{ *:[v4i32] }:$rsrc, SCSrc_b32:{ *:[i32] }:$soffset, (timm:{ *:[i32] }):$offset, (extract_cpol_set_glc:{ *:[i32] } ?:{ *:[i32] }:$auxiliary))
        GIR_MakeTempReg, /*TempRegID*/0, /*TypeID*/GILLT_s64,
        GIR_BuildMI, /*InsnID*/1, /*Opcode*/GIMT_Encode2(TargetOpcode::REG_SEQUENCE),
        GIR_AddTempRegister, /*InsnID*/1, /*TempRegID*/0, /*TempRegFlags*/GIMT_Encode2(RegState::Define),
        GIR_Copy, /*NewInsnID*/1, /*OldInsnID*/0, /*OpIdx*/3, // vindex
        GIR_AddImm8, /*InsnID*/1, /*SubRegIndex*/3,
        GIR_Copy, /*NewInsnID*/1, /*OldInsnID*/0, /*OpIdx*/4, // voffset
        GIR_AddImm8, /*InsnID*/1, /*SubRegIndex*/11,
        GIR_ConstrainOperandRC, /*InsnID*/1, /*Op*/0, GIMT_Encode2(AMDGPU::VReg_64RegClassID),
        GIR_ConstrainOperandRC, /*InsnID*/1, /*Op*/1, GIMT_Encode2(AMDGPU::VGPR_32RegClassID),
        GIR_ConstrainOperandRC, /*InsnID*/1, /*Op*/3, GIMT_Encode2(AMDGPU::VGPR_32RegClassID),
        GIR_BuildMI, /*InsnID*/0, /*Opcode*/GIMT_Encode2(AMDGPU::BUFFER_ATOMIC_SMIN_X2_VBUFFER_BOTHEN_RTN),
        GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/0, // DstI[vdata]
        GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/1, // vdata_in
        GIR_AddSimpleTempRegister, /*InsnID*/0, /*TempRegID*/0,
        GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/2, // rsrc
        GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/0, // soffset
        GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/6, // offset
        GIR_CustomOperandRenderer, /*InsnID*/0, /*OldInsnID*/0, /*OpIdx*/7, /*OperandRenderer*/GIMT_Encode2(GICR_renderExtractCpolSetGLC), // auxiliary
        GIR_MergeMemOperands, /*InsnID*/0, /*NumInsns*/1, /*MergeInsnID's*/0,
        GIR_ConstrainSelectedInstOperands, /*InsnID*/0,
        GIR_EraseFromParent, /*InsnID*/0,
        // GIR_Coverage, 4988,
        GIR_Done,
      // Label 6189: @453392
      GIM_Reject,
    // Label 6173: @453393
    GIM_Reject,
    // Label 6155: @453394
    GIM_Reject,
    // Label 119: @453395
    GIM_SwitchType, /*MI*/0, /*Op*/0, /*[*/GIMT_Encode2(9), GIMT_Encode2(11), /*)*//*default:*//*Label 6192*/ GIMT_Encode4(456188),
    /*GILLT_s32*//*Label 6190*/ GIMT_Encode4(453414),
    /*GILLT_s64*//*Label 6191*/ GIMT_Encode4(454801),
    // Label 6190: @453414
    GIM_Try, /*On fail goto*//*Label 6193*/ GIMT_Encode4(454800),
      GIM_CheckType, /*MI*/0, /*Op*/1, /*Type*/GILLT_s32,
      GIM_CheckType, /*MI*/0, /*Op*/2, /*Type*/GILLT_v4s32,
      GIM_CheckType, /*MI*/0, /*Op*/3, /*Type*/GILLT_s32,
      GIM_CheckType, /*MI*/0, /*Op*/4, /*Type*/GILLT_s32,
      GIM_CheckType, /*MI*/0, /*Op*/5, /*Type*/GILLT_s32,
      GIM_Try, /*On fail goto*//*Label 6194*/ GIMT_Encode4(453517), // Rule ID 4765 //
        GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasUnrestrictedSOffset),
        GIM_CheckHasNoUse, /*MI*/0,
        GIM_CheckConstantInt8, /*MI*/0, /*Op*/3, 0,
        GIM_CheckConstantInt8, /*MI*/0, /*Op*/4, 0,
        // MIs[0] offset
        GIM_CheckIsImm, /*MI*/0, /*Op*/6,
        // MIs[0] auxiliary
        GIM_CheckIsImm, /*MI*/0, /*Op*/7,
        // MIs[0] Operand 8
        GIM_CheckLiteralInt, /*MI*/0, /*Op*/8, GIMT_Encode8(0),
        GIM_CheckComplexPattern, /*MI*/0, /*Op*/5, /*Renderer*/GIMT_Encode2(0), GIMT_Encode2(GICP_gi_buf_soffset),
        // (SIbuffer_atomic_sub:{ *:[i32] } i32:{ *:[i32] }:$vdata_in, v4i32:{ *:[v4i32] }:$rsrc, 0:{ *:[i32] }, 0:{ *:[i32] }, (BUFSOffset:{ *:[i32] } i32:{ *:[i32] }:$soffset), (timm:{ *:[i32] }):$offset, (timm:{ *:[i32] }):$auxiliary, 0:{ *:[i1] })<<P:Predicate_SIbuffer_atomic_sub_noret>>  =>  (BUFFER_ATOMIC_SUB_OFFSET anonymous_15037:{ *:[i32] }:$vdata_in, SReg_128:{ *:[v4i32] }:$rsrc, SCSrc_b32:{ *:[i32] }:$soffset, (timm:{ *:[i32] }):$offset, (extract_cpol:{ *:[i32] } ?:{ *:[i32] }:$auxiliary))
        GIR_BuildMI, /*InsnID*/0, /*Opcode*/GIMT_Encode2(AMDGPU::BUFFER_ATOMIC_SUB_OFFSET),
        GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/1, // vdata_in
        GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/2, // rsrc
        GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/0, // soffset
        GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/6, // offset
        GIR_CustomOperandRenderer, /*InsnID*/0, /*OldInsnID*/0, /*OpIdx*/7, /*OperandRenderer*/GIMT_Encode2(GICR_renderExtractCPol), // auxiliary
        GIR_MergeMemOperands, /*InsnID*/0, /*NumInsns*/1, /*MergeInsnID's*/0,
        GIR_ConstrainSelectedInstOperands, /*InsnID*/0,
        GIR_EraseFromParent, /*InsnID*/0,
        // GIR_Coverage, 4765,
        GIR_Done,
      // Label 6194: @453517
      GIM_Try, /*On fail goto*//*Label 6195*/ GIMT_Encode4(453592), // Rule ID 4773 //
        GIM_CheckHasNoUse, /*MI*/0,
        GIM_CheckConstantInt8, /*MI*/0, /*Op*/3, 0,
        GIM_CheckConstantInt8, /*MI*/0, /*Op*/4, 0,
        // MIs[0] offset
        GIM_CheckIsImm, /*MI*/0, /*Op*/6,
        // MIs[0] auxiliary
        GIM_CheckIsImm, /*MI*/0, /*Op*/7,
        // MIs[0] Operand 8
        GIM_CheckLiteralInt, /*MI*/0, /*Op*/8, GIMT_Encode8(0),
        GIM_CheckComplexPattern, /*MI*/0, /*Op*/5, /*Renderer*/GIMT_Encode2(0), GIMT_Encode2(GICP_gi_buf_soffset),
        // (SIbuffer_atomic_sub:{ *:[i32] } i32:{ *:[i32] }:$vdata_in, v4i32:{ *:[v4i32] }:$rsrc, 0:{ *:[i32] }, 0:{ *:[i32] }, (BUFSOffset:{ *:[i32] } i32:{ *:[i32] }:$soffset), (timm:{ *:[i32] }):$offset, (timm:{ *:[i32] }):$auxiliary, 0:{ *:[i1] })<<P:Predicate_SIbuffer_atomic_sub_noret>>  =>  (BUFFER_ATOMIC_SUB_VBUFFER_OFFSET anonymous_15037:{ *:[i32] }:$vdata_in, SReg_128:{ *:[v4i32] }:$rsrc, SCSrc_b32:{ *:[i32] }:$soffset, (timm:{ *:[i32] }):$offset, (extract_cpol:{ *:[i32] } ?:{ *:[i32] }:$auxiliary))
        GIR_BuildMI, /*InsnID*/0, /*Opcode*/GIMT_Encode2(AMDGPU::BUFFER_ATOMIC_SUB_VBUFFER_OFFSET),
        GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/1, // vdata_in
        GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/2, // rsrc
        GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/0, // soffset
        GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/6, // offset
        GIR_CustomOperandRenderer, /*InsnID*/0, /*OldInsnID*/0, /*OpIdx*/7, /*OperandRenderer*/GIMT_Encode2(GICR_renderExtractCPol), // auxiliary
        GIR_MergeMemOperands, /*InsnID*/0, /*NumInsns*/1, /*MergeInsnID's*/0,
        GIR_ConstrainSelectedInstOperands, /*InsnID*/0,
        GIR_EraseFromParent, /*InsnID*/0,
        // GIR_Coverage, 4773,
        GIR_Done,
      // Label 6195: @453592
      GIM_Try, /*On fail goto*//*Label 6196*/ GIMT_Encode4(453677), // Rule ID 4761 //
        GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasUnrestrictedSOffset),
        GIM_CheckRegBankForClass, /*MI*/0, /*Op*/0, /*RC*/GIMT_Encode2(AMDGPU::AV_32RegClassID),
        GIM_CheckConstantInt8, /*MI*/0, /*Op*/3, 0,
        GIM_CheckConstantInt8, /*MI*/0, /*Op*/4, 0,
        // MIs[0] offset
        GIM_CheckIsImm, /*MI*/0, /*Op*/6,
        // MIs[0] auxiliary
        GIM_CheckIsImm, /*MI*/0, /*Op*/7,
        // MIs[0] Operand 8
        GIM_CheckLiteralInt, /*MI*/0, /*Op*/8, GIMT_Encode8(0),
        GIM_CheckComplexPattern, /*MI*/0, /*Op*/5, /*Renderer*/GIMT_Encode2(0), GIMT_Encode2(GICP_gi_buf_soffset),
        // (SIbuffer_atomic_sub:{ *:[i32] } i32:{ *:[i32] }:$vdata_in, v4i32:{ *:[v4i32] }:$rsrc, 0:{ *:[i32] }, 0:{ *:[i32] }, (BUFSOffset:{ *:[i32] } i32:{ *:[i32] }:$soffset), (timm:{ *:[i32] }):$offset, (timm:{ *:[i32] }):$auxiliary, 0:{ *:[i1] })  =>  (BUFFER_ATOMIC_SUB_OFFSET_RTN:{ *:[i32] } anonymous_15037:{ *:[i32] }:$vdata_in, SReg_128:{ *:[v4i32] }:$rsrc, SCSrc_b32:{ *:[i32] }:$soffset, (timm:{ *:[i32] }):$offset, (extract_cpol_set_glc:{ *:[i32] } ?:{ *:[i32] }:$auxiliary))
        GIR_BuildMI, /*InsnID*/0, /*Opcode*/GIMT_Encode2(AMDGPU::BUFFER_ATOMIC_SUB_OFFSET_RTN),
        GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/0, // DstI[vdata]
        GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/1, // vdata_in
        GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/2, // rsrc
        GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/0, // soffset
        GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/6, // offset
        GIR_CustomOperandRenderer, /*InsnID*/0, /*OldInsnID*/0, /*OpIdx*/7, /*OperandRenderer*/GIMT_Encode2(GICR_renderExtractCpolSetGLC), // auxiliary
        GIR_MergeMemOperands, /*InsnID*/0, /*NumInsns*/1, /*MergeInsnID's*/0,
        GIR_ConstrainSelectedInstOperands, /*InsnID*/0,
        GIR_EraseFromParent, /*InsnID*/0,
        // GIR_Coverage, 4761,
        GIR_Done,
      // Label 6196: @453677
      GIM_Try, /*On fail goto*//*Label 6197*/ GIMT_Encode4(453759), // Rule ID 4769 //
        GIM_CheckRegBankForClass, /*MI*/0, /*Op*/0, /*RC*/GIMT_Encode2(AMDGPU::AV_32RegClassID),
        GIM_CheckConstantInt8, /*MI*/0, /*Op*/3, 0,
        GIM_CheckConstantInt8, /*MI*/0, /*Op*/4, 0,
        // MIs[0] offset
        GIM_CheckIsImm, /*MI*/0, /*Op*/6,
        // MIs[0] auxiliary
        GIM_CheckIsImm, /*MI*/0, /*Op*/7,
        // MIs[0] Operand 8
        GIM_CheckLiteralInt, /*MI*/0, /*Op*/8, GIMT_Encode8(0),
        GIM_CheckComplexPattern, /*MI*/0, /*Op*/5, /*Renderer*/GIMT_Encode2(0), GIMT_Encode2(GICP_gi_buf_soffset),
        // (SIbuffer_atomic_sub:{ *:[i32] } i32:{ *:[i32] }:$vdata_in, v4i32:{ *:[v4i32] }:$rsrc, 0:{ *:[i32] }, 0:{ *:[i32] }, (BUFSOffset:{ *:[i32] } i32:{ *:[i32] }:$soffset), (timm:{ *:[i32] }):$offset, (timm:{ *:[i32] }):$auxiliary, 0:{ *:[i1] })  =>  (BUFFER_ATOMIC_SUB_VBUFFER_OFFSET_RTN:{ *:[i32] } anonymous_15037:{ *:[i32] }:$vdata_in, SReg_128:{ *:[v4i32] }:$rsrc, SCSrc_b32:{ *:[i32] }:$soffset, (timm:{ *:[i32] }):$offset, (extract_cpol_set_glc:{ *:[i32] } ?:{ *:[i32] }:$auxiliary))
        GIR_BuildMI, /*InsnID*/0, /*Opcode*/GIMT_Encode2(AMDGPU::BUFFER_ATOMIC_SUB_VBUFFER_OFFSET_RTN),
        GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/0, // DstI[vdata]
        GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/1, // vdata_in
        GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/2, // rsrc
        GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/0, // soffset
        GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/6, // offset
        GIR_CustomOperandRenderer, /*InsnID*/0, /*OldInsnID*/0, /*OpIdx*/7, /*OperandRenderer*/GIMT_Encode2(GICR_renderExtractCpolSetGLC), // auxiliary
        GIR_MergeMemOperands, /*InsnID*/0, /*NumInsns*/1, /*MergeInsnID's*/0,
        GIR_ConstrainSelectedInstOperands, /*InsnID*/0,
        GIR_EraseFromParent, /*InsnID*/0,
        // GIR_Coverage, 4769,
        GIR_Done,
      // Label 6197: @453759
      GIM_Try, /*On fail goto*//*Label 6198*/ GIMT_Encode4(453837), // Rule ID 4767 //
        GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasUnrestrictedSOffset),
        GIM_CheckHasNoUse, /*MI*/0,
        GIM_CheckConstantInt8, /*MI*/0, /*Op*/3, 0,
        // MIs[0] offset
        GIM_CheckIsImm, /*MI*/0, /*Op*/6,
        // MIs[0] auxiliary
        GIM_CheckIsImm, /*MI*/0, /*Op*/7,
        // MIs[0] Operand 8
        GIM_CheckLiteralInt, /*MI*/0, /*Op*/8, GIMT_Encode8(0),
        GIM_CheckComplexPattern, /*MI*/0, /*Op*/5, /*Renderer*/GIMT_Encode2(0), GIMT_Encode2(GICP_gi_buf_soffset),
        // (SIbuffer_atomic_sub:{ *:[i32] } i32:{ *:[i32] }:$vdata_in, v4i32:{ *:[v4i32] }:$rsrc, 0:{ *:[i32] }, i32:{ *:[i32] }:$voffset, (BUFSOffset:{ *:[i32] } i32:{ *:[i32] }:$soffset), (timm:{ *:[i32] }):$offset, (timm:{ *:[i32] }):$auxiliary, 0:{ *:[i1] })<<P:Predicate_SIbuffer_atomic_sub_noret>>  =>  (BUFFER_ATOMIC_SUB_OFFEN anonymous_15037:{ *:[i32] }:$vdata_in, VGPR_32:{ *:[i32] }:$voffset, SReg_128:{ *:[v4i32] }:$rsrc, SCSrc_b32:{ *:[i32] }:$soffset, (timm:{ *:[i32] }):$offset, (extract_cpol:{ *:[i32] } ?:{ *:[i32] }:$auxiliary))
        GIR_BuildMI, /*InsnID*/0, /*Opcode*/GIMT_Encode2(AMDGPU::BUFFER_ATOMIC_SUB_OFFEN),
        GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/1, // vdata_in
        GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/4, // voffset
        GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/2, // rsrc
        GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/0, // soffset
        GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/6, // offset
        GIR_CustomOperandRenderer, /*InsnID*/0, /*OldInsnID*/0, /*OpIdx*/7, /*OperandRenderer*/GIMT_Encode2(GICR_renderExtractCPol), // auxiliary
        GIR_MergeMemOperands, /*InsnID*/0, /*NumInsns*/1, /*MergeInsnID's*/0,
        GIR_ConstrainSelectedInstOperands, /*InsnID*/0,
        GIR_EraseFromParent, /*InsnID*/0,
        // GIR_Coverage, 4767,
        GIR_Done,
      // Label 6198: @453837
      GIM_Try, /*On fail goto*//*Label 6199*/ GIMT_Encode4(453912), // Rule ID 4775 //
        GIM_CheckHasNoUse, /*MI*/0,
        GIM_CheckConstantInt8, /*MI*/0, /*Op*/3, 0,
        // MIs[0] offset
        GIM_CheckIsImm, /*MI*/0, /*Op*/6,
        // MIs[0] auxiliary
        GIM_CheckIsImm, /*MI*/0, /*Op*/7,
        // MIs[0] Operand 8
        GIM_CheckLiteralInt, /*MI*/0, /*Op*/8, GIMT_Encode8(0),
        GIM_CheckComplexPattern, /*MI*/0, /*Op*/5, /*Renderer*/GIMT_Encode2(0), GIMT_Encode2(GICP_gi_buf_soffset),
        // (SIbuffer_atomic_sub:{ *:[i32] } i32:{ *:[i32] }:$vdata_in, v4i32:{ *:[v4i32] }:$rsrc, 0:{ *:[i32] }, i32:{ *:[i32] }:$voffset, (BUFSOffset:{ *:[i32] } i32:{ *:[i32] }:$soffset), (timm:{ *:[i32] }):$offset, (timm:{ *:[i32] }):$auxiliary, 0:{ *:[i1] })<<P:Predicate_SIbuffer_atomic_sub_noret>>  =>  (BUFFER_ATOMIC_SUB_VBUFFER_OFFEN anonymous_15037:{ *:[i32] }:$vdata_in, VGPR_32:{ *:[i32] }:$voffset, SReg_128:{ *:[v4i32] }:$rsrc, SCSrc_b32:{ *:[i32] }:$soffset, (timm:{ *:[i32] }):$offset, (extract_cpol:{ *:[i32] } ?:{ *:[i32] }:$auxiliary))
        GIR_BuildMI, /*InsnID*/0, /*Opcode*/GIMT_Encode2(AMDGPU::BUFFER_ATOMIC_SUB_VBUFFER_OFFEN),
        GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/1, // vdata_in
        GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/4, // voffset
        GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/2, // rsrc
        GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/0, // soffset
        GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/6, // offset
        GIR_CustomOperandRenderer, /*InsnID*/0, /*OldInsnID*/0, /*OpIdx*/7, /*OperandRenderer*/GIMT_Encode2(GICR_renderExtractCPol), // auxiliary
        GIR_MergeMemOperands, /*InsnID*/0, /*NumInsns*/1, /*MergeInsnID's*/0,
        GIR_ConstrainSelectedInstOperands, /*InsnID*/0,
        GIR_EraseFromParent, /*InsnID*/0,
        // GIR_Coverage, 4775,
        GIR_Done,
      // Label 6199: @453912
      GIM_Try, /*On fail goto*//*Label 6200*/ GIMT_Encode4(453997), // Rule ID 4763 //
        GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasUnrestrictedSOffset),
        GIM_CheckRegBankForClass, /*MI*/0, /*Op*/0, /*RC*/GIMT_Encode2(AMDGPU::AV_32RegClassID),
        GIM_CheckConstantInt8, /*MI*/0, /*Op*/3, 0,
        // MIs[0] offset
        GIM_CheckIsImm, /*MI*/0, /*Op*/6,
        // MIs[0] auxiliary
        GIM_CheckIsImm, /*MI*/0, /*Op*/7,
        // MIs[0] Operand 8
        GIM_CheckLiteralInt, /*MI*/0, /*Op*/8, GIMT_Encode8(0),
        GIM_CheckComplexPattern, /*MI*/0, /*Op*/5, /*Renderer*/GIMT_Encode2(0), GIMT_Encode2(GICP_gi_buf_soffset),
        // (SIbuffer_atomic_sub:{ *:[i32] } i32:{ *:[i32] }:$vdata_in, v4i32:{ *:[v4i32] }:$rsrc, 0:{ *:[i32] }, i32:{ *:[i32] }:$voffset, (BUFSOffset:{ *:[i32] } i32:{ *:[i32] }:$soffset), (timm:{ *:[i32] }):$offset, (timm:{ *:[i32] }):$auxiliary, 0:{ *:[i1] })  =>  (BUFFER_ATOMIC_SUB_OFFEN_RTN:{ *:[i32] } anonymous_15037:{ *:[i32] }:$vdata_in, VGPR_32:{ *:[i32] }:$voffset, SReg_128:{ *:[v4i32] }:$rsrc, SCSrc_b32:{ *:[i32] }:$soffset, (timm:{ *:[i32] }):$offset, (extract_cpol_set_glc:{ *:[i32] } ?:{ *:[i32] }:$auxiliary))
        GIR_BuildMI, /*InsnID*/0, /*Opcode*/GIMT_Encode2(AMDGPU::BUFFER_ATOMIC_SUB_OFFEN_RTN),
        GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/0, // DstI[vdata]
        GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/1, // vdata_in
        GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/4, // voffset
        GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/2, // rsrc
        GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/0, // soffset
        GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/6, // offset
        GIR_CustomOperandRenderer, /*InsnID*/0, /*OldInsnID*/0, /*OpIdx*/7, /*OperandRenderer*/GIMT_Encode2(GICR_renderExtractCpolSetGLC), // auxiliary
        GIR_MergeMemOperands, /*InsnID*/0, /*NumInsns*/1, /*MergeInsnID's*/0,
        GIR_ConstrainSelectedInstOperands, /*InsnID*/0,
        GIR_EraseFromParent, /*InsnID*/0,
        // GIR_Coverage, 4763,
        GIR_Done,
      // Label 6200: @453997
      GIM_Try, /*On fail goto*//*Label 6201*/ GIMT_Encode4(454079), // Rule ID 4771 //
        GIM_CheckRegBankForClass, /*MI*/0, /*Op*/0, /*RC*/GIMT_Encode2(AMDGPU::AV_32RegClassID),
        GIM_CheckConstantInt8, /*MI*/0, /*Op*/3, 0,
        // MIs[0] offset
        GIM_CheckIsImm, /*MI*/0, /*Op*/6,
        // MIs[0] auxiliary
        GIM_CheckIsImm, /*MI*/0, /*Op*/7,
        // MIs[0] Operand 8
        GIM_CheckLiteralInt, /*MI*/0, /*Op*/8, GIMT_Encode8(0),
        GIM_CheckComplexPattern, /*MI*/0, /*Op*/5, /*Renderer*/GIMT_Encode2(0), GIMT_Encode2(GICP_gi_buf_soffset),
        // (SIbuffer_atomic_sub:{ *:[i32] } i32:{ *:[i32] }:$vdata_in, v4i32:{ *:[v4i32] }:$rsrc, 0:{ *:[i32] }, i32:{ *:[i32] }:$voffset, (BUFSOffset:{ *:[i32] } i32:{ *:[i32] }:$soffset), (timm:{ *:[i32] }):$offset, (timm:{ *:[i32] }):$auxiliary, 0:{ *:[i1] })  =>  (BUFFER_ATOMIC_SUB_VBUFFER_OFFEN_RTN:{ *:[i32] } anonymous_15037:{ *:[i32] }:$vdata_in, VGPR_32:{ *:[i32] }:$voffset, SReg_128:{ *:[v4i32] }:$rsrc, SCSrc_b32:{ *:[i32] }:$soffset, (timm:{ *:[i32] }):$offset, (extract_cpol_set_glc:{ *:[i32] } ?:{ *:[i32] }:$auxiliary))
        GIR_BuildMI, /*InsnID*/0, /*Opcode*/GIMT_Encode2(AMDGPU::BUFFER_ATOMIC_SUB_VBUFFER_OFFEN_RTN),
        GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/0, // DstI[vdata]
        GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/1, // vdata_in
        GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/4, // voffset
        GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/2, // rsrc
        GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/0, // soffset
        GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/6, // offset
        GIR_CustomOperandRenderer, /*InsnID*/0, /*OldInsnID*/0, /*OpIdx*/7, /*OperandRenderer*/GIMT_Encode2(GICR_renderExtractCpolSetGLC), // auxiliary
        GIR_MergeMemOperands, /*InsnID*/0, /*NumInsns*/1, /*MergeInsnID's*/0,
        GIR_ConstrainSelectedInstOperands, /*InsnID*/0,
        GIR_EraseFromParent, /*InsnID*/0,
        // GIR_Coverage, 4771,
        GIR_Done,
      // Label 6201: @454079
      GIM_Try, /*On fail goto*//*Label 6202*/ GIMT_Encode4(454149), // Rule ID 4766 //
        GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasUnrestrictedSOffset),
        GIM_CheckHasNoUse, /*MI*/0,
        GIM_CheckConstantInt8, /*MI*/0, /*Op*/4, 0,
        // MIs[0] offset
        GIM_CheckIsImm, /*MI*/0, /*Op*/6,
        // MIs[0] auxiliary
        GIM_CheckIsImm, /*MI*/0, /*Op*/7,
        // MIs[0] Operand 8
        GIM_CheckIsImm, /*MI*/0, /*Op*/8,
        GIM_CheckComplexPattern, /*MI*/0, /*Op*/5, /*Renderer*/GIMT_Encode2(0), GIMT_Encode2(GICP_gi_buf_soffset),
        // (SIbuffer_atomic_sub:{ *:[i32] } i32:{ *:[i32] }:$vdata_in, v4i32:{ *:[v4i32] }:$rsrc, i32:{ *:[i32] }:$vindex, 0:{ *:[i32] }, (BUFSOffset:{ *:[i32] } i32:{ *:[i32] }:$soffset), (timm:{ *:[i32] }):$offset, (timm:{ *:[i32] }):$auxiliary, (timm:{ *:[i1] }))<<P:Predicate_SIbuffer_atomic_sub_noret>>  =>  (BUFFER_ATOMIC_SUB_IDXEN anonymous_15037:{ *:[i32] }:$vdata_in, VGPR_32:{ *:[i32] }:$vindex, SReg_128:{ *:[v4i32] }:$rsrc, SCSrc_b32:{ *:[i32] }:$soffset, (timm:{ *:[i32] }):$offset, (extract_cpol:{ *:[i32] } ?:{ *:[i32] }:$auxiliary))
        GIR_BuildMI, /*InsnID*/0, /*Opcode*/GIMT_Encode2(AMDGPU::BUFFER_ATOMIC_SUB_IDXEN),
        GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/1, // vdata_in
        GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/3, // vindex
        GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/2, // rsrc
        GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/0, // soffset
        GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/6, // offset
        GIR_CustomOperandRenderer, /*InsnID*/0, /*OldInsnID*/0, /*OpIdx*/7, /*OperandRenderer*/GIMT_Encode2(GICR_renderExtractCPol), // auxiliary
        GIR_MergeMemOperands, /*InsnID*/0, /*NumInsns*/1, /*MergeInsnID's*/0,
        GIR_ConstrainSelectedInstOperands, /*InsnID*/0,
        GIR_EraseFromParent, /*InsnID*/0,
        // GIR_Coverage, 4766,
        GIR_Done,
      // Label 6202: @454149
      GIM_Try, /*On fail goto*//*Label 6203*/ GIMT_Encode4(454216), // Rule ID 4774 //
        GIM_CheckHasNoUse, /*MI*/0,
        GIM_CheckConstantInt8, /*MI*/0, /*Op*/4, 0,
        // MIs[0] offset
        GIM_CheckIsImm, /*MI*/0, /*Op*/6,
        // MIs[0] auxiliary
        GIM_CheckIsImm, /*MI*/0, /*Op*/7,
        // MIs[0] Operand 8
        GIM_CheckIsImm, /*MI*/0, /*Op*/8,
        GIM_CheckComplexPattern, /*MI*/0, /*Op*/5, /*Renderer*/GIMT_Encode2(0), GIMT_Encode2(GICP_gi_buf_soffset),
        // (SIbuffer_atomic_sub:{ *:[i32] } i32:{ *:[i32] }:$vdata_in, v4i32:{ *:[v4i32] }:$rsrc, i32:{ *:[i32] }:$vindex, 0:{ *:[i32] }, (BUFSOffset:{ *:[i32] } i32:{ *:[i32] }:$soffset), (timm:{ *:[i32] }):$offset, (timm:{ *:[i32] }):$auxiliary, (timm:{ *:[i1] }))<<P:Predicate_SIbuffer_atomic_sub_noret>>  =>  (BUFFER_ATOMIC_SUB_VBUFFER_IDXEN anonymous_15037:{ *:[i32] }:$vdata_in, VGPR_32:{ *:[i32] }:$vindex, SReg_128:{ *:[v4i32] }:$rsrc, SCSrc_b32:{ *:[i32] }:$soffset, (timm:{ *:[i32] }):$offset, (extract_cpol:{ *:[i32] } ?:{ *:[i32] }:$auxiliary))
        GIR_BuildMI, /*InsnID*/0, /*Opcode*/GIMT_Encode2(AMDGPU::BUFFER_ATOMIC_SUB_VBUFFER_IDXEN),
        GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/1, // vdata_in
        GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/3, // vindex
        GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/2, // rsrc
        GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/0, // soffset
        GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/6, // offset
        GIR_CustomOperandRenderer, /*InsnID*/0, /*OldInsnID*/0, /*OpIdx*/7, /*OperandRenderer*/GIMT_Encode2(GICR_renderExtractCPol), // auxiliary
        GIR_MergeMemOperands, /*InsnID*/0, /*NumInsns*/1, /*MergeInsnID's*/0,
        GIR_ConstrainSelectedInstOperands, /*InsnID*/0,
        GIR_EraseFromParent, /*InsnID*/0,
        // GIR_Coverage, 4774,
        GIR_Done,
      // Label 6203: @454216
      GIM_Try, /*On fail goto*//*Label 6204*/ GIMT_Encode4(454293), // Rule ID 4762 //
        GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasUnrestrictedSOffset),
        GIM_CheckRegBankForClass, /*MI*/0, /*Op*/0, /*RC*/GIMT_Encode2(AMDGPU::AV_32RegClassID),
        GIM_CheckConstantInt8, /*MI*/0, /*Op*/4, 0,
        // MIs[0] offset
        GIM_CheckIsImm, /*MI*/0, /*Op*/6,
        // MIs[0] auxiliary
        GIM_CheckIsImm, /*MI*/0, /*Op*/7,
        // MIs[0] Operand 8
        GIM_CheckIsImm, /*MI*/0, /*Op*/8,
        GIM_CheckComplexPattern, /*MI*/0, /*Op*/5, /*Renderer*/GIMT_Encode2(0), GIMT_Encode2(GICP_gi_buf_soffset),
        // (SIbuffer_atomic_sub:{ *:[i32] } i32:{ *:[i32] }:$vdata_in, v4i32:{ *:[v4i32] }:$rsrc, i32:{ *:[i32] }:$vindex, 0:{ *:[i32] }, (BUFSOffset:{ *:[i32] } i32:{ *:[i32] }:$soffset), (timm:{ *:[i32] }):$offset, (timm:{ *:[i32] }):$auxiliary, (timm:{ *:[i1] }))  =>  (BUFFER_ATOMIC_SUB_IDXEN_RTN:{ *:[i32] } anonymous_15037:{ *:[i32] }:$vdata_in, VGPR_32:{ *:[i32] }:$vindex, SReg_128:{ *:[v4i32] }:$rsrc, SCSrc_b32:{ *:[i32] }:$soffset, (timm:{ *:[i32] }):$offset, (extract_cpol_set_glc:{ *:[i32] } ?:{ *:[i32] }:$auxiliary))
        GIR_BuildMI, /*InsnID*/0, /*Opcode*/GIMT_Encode2(AMDGPU::BUFFER_ATOMIC_SUB_IDXEN_RTN),
        GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/0, // DstI[vdata]
        GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/1, // vdata_in
        GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/3, // vindex
        GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/2, // rsrc
        GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/0, // soffset
        GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/6, // offset
        GIR_CustomOperandRenderer, /*InsnID*/0, /*OldInsnID*/0, /*OpIdx*/7, /*OperandRenderer*/GIMT_Encode2(GICR_renderExtractCpolSetGLC), // auxiliary
        GIR_MergeMemOperands, /*InsnID*/0, /*NumInsns*/1, /*MergeInsnID's*/0,
        GIR_ConstrainSelectedInstOperands, /*InsnID*/0,
        GIR_EraseFromParent, /*InsnID*/0,
        // GIR_Coverage, 4762,
        GIR_Done,
      // Label 6204: @454293
      GIM_Try, /*On fail goto*//*Label 6205*/ GIMT_Encode4(454367), // Rule ID 4770 //
        GIM_CheckRegBankForClass, /*MI*/0, /*Op*/0, /*RC*/GIMT_Encode2(AMDGPU::AV_32RegClassID),
        GIM_CheckConstantInt8, /*MI*/0, /*Op*/4, 0,
        // MIs[0] offset
        GIM_CheckIsImm, /*MI*/0, /*Op*/6,
        // MIs[0] auxiliary
        GIM_CheckIsImm, /*MI*/0, /*Op*/7,
        // MIs[0] Operand 8
        GIM_CheckIsImm, /*MI*/0, /*Op*/8,
        GIM_CheckComplexPattern, /*MI*/0, /*Op*/5, /*Renderer*/GIMT_Encode2(0), GIMT_Encode2(GICP_gi_buf_soffset),
        // (SIbuffer_atomic_sub:{ *:[i32] } i32:{ *:[i32] }:$vdata_in, v4i32:{ *:[v4i32] }:$rsrc, i32:{ *:[i32] }:$vindex, 0:{ *:[i32] }, (BUFSOffset:{ *:[i32] } i32:{ *:[i32] }:$soffset), (timm:{ *:[i32] }):$offset, (timm:{ *:[i32] }):$auxiliary, (timm:{ *:[i1] }))  =>  (BUFFER_ATOMIC_SUB_VBUFFER_IDXEN_RTN:{ *:[i32] } anonymous_15037:{ *:[i32] }:$vdata_in, VGPR_32:{ *:[i32] }:$vindex, SReg_128:{ *:[v4i32] }:$rsrc, SCSrc_b32:{ *:[i32] }:$soffset, (timm:{ *:[i32] }):$offset, (extract_cpol_set_glc:{ *:[i32] } ?:{ *:[i32] }:$auxiliary))
        GIR_BuildMI, /*InsnID*/0, /*Opcode*/GIMT_Encode2(AMDGPU::BUFFER_ATOMIC_SUB_VBUFFER_IDXEN_RTN),
        GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/0, // DstI[vdata]
        GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/1, // vdata_in
        GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/3, // vindex
        GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/2, // rsrc
        GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/0, // soffset
        GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/6, // offset
        GIR_CustomOperandRenderer, /*InsnID*/0, /*OldInsnID*/0, /*OpIdx*/7, /*OperandRenderer*/GIMT_Encode2(GICR_renderExtractCpolSetGLC), // auxiliary
        GIR_MergeMemOperands, /*InsnID*/0, /*NumInsns*/1, /*MergeInsnID's*/0,
        GIR_ConstrainSelectedInstOperands, /*InsnID*/0,
        GIR_EraseFromParent, /*InsnID*/0,
        // GIR_Coverage, 4770,
        GIR_Done,
      // Label 6205: @454367
      GIM_Try, /*On fail goto*//*Label 6206*/ GIMT_Encode4(454473), // Rule ID 4768 //
        GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasUnrestrictedSOffset),
        GIM_CheckHasNoUse, /*MI*/0,
        // MIs[0] offset
        GIM_CheckIsImm, /*MI*/0, /*Op*/6,
        // MIs[0] auxiliary
        GIM_CheckIsImm, /*MI*/0, /*Op*/7,
        // MIs[0] Operand 8
        GIM_CheckIsImm, /*MI*/0, /*Op*/8,
        GIM_CheckComplexPattern, /*MI*/0, /*Op*/5, /*Renderer*/GIMT_Encode2(0), GIMT_Encode2(GICP_gi_buf_soffset),
        // (SIbuffer_atomic_sub:{ *:[i32] } i32:{ *:[i32] }:$vdata_in, v4i32:{ *:[v4i32] }:$rsrc, i32:{ *:[i32] }:$vindex, i32:{ *:[i32] }:$voffset, (BUFSOffset:{ *:[i32] } i32:{ *:[i32] }:$soffset), (timm:{ *:[i32] }):$offset, (timm:{ *:[i32] }):$auxiliary, (timm:{ *:[i1] }))<<P:Predicate_SIbuffer_atomic_sub_noret>>  =>  (BUFFER_ATOMIC_SUB_BOTHEN anonymous_15037:{ *:[i32] }:$vdata_in, (REG_SEQUENCE:{ *:[i64] } VReg_64:{ *:[i32] }, VGPR_32:{ *:[i32] }:$vindex, sub0:{ *:[i32] }, VGPR_32:{ *:[i32] }:$voffset, sub1:{ *:[i32] }), SReg_128:{ *:[v4i32] }:$rsrc, SCSrc_b32:{ *:[i32] }:$soffset, (timm:{ *:[i32] }):$offset, (extract_cpol:{ *:[i32] } ?:{ *:[i32] }:$auxiliary))
        GIR_MakeTempReg, /*TempRegID*/0, /*TypeID*/GILLT_s64,
        GIR_BuildMI, /*InsnID*/1, /*Opcode*/GIMT_Encode2(TargetOpcode::REG_SEQUENCE),
        GIR_AddTempRegister, /*InsnID*/1, /*TempRegID*/0, /*TempRegFlags*/GIMT_Encode2(RegState::Define),
        GIR_Copy, /*NewInsnID*/1, /*OldInsnID*/0, /*OpIdx*/3, // vindex
        GIR_AddImm8, /*InsnID*/1, /*SubRegIndex*/3,
        GIR_Copy, /*NewInsnID*/1, /*OldInsnID*/0, /*OpIdx*/4, // voffset
        GIR_AddImm8, /*InsnID*/1, /*SubRegIndex*/11,
        GIR_ConstrainOperandRC, /*InsnID*/1, /*Op*/0, GIMT_Encode2(AMDGPU::VReg_64RegClassID),
        GIR_ConstrainOperandRC, /*InsnID*/1, /*Op*/1, GIMT_Encode2(AMDGPU::VGPR_32RegClassID),
        GIR_ConstrainOperandRC, /*InsnID*/1, /*Op*/3, GIMT_Encode2(AMDGPU::VGPR_32RegClassID),
        GIR_BuildMI, /*InsnID*/0, /*Opcode*/GIMT_Encode2(AMDGPU::BUFFER_ATOMIC_SUB_BOTHEN),
        GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/1, // vdata_in
        GIR_AddSimpleTempRegister, /*InsnID*/0, /*TempRegID*/0,
        GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/2, // rsrc
        GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/0, // soffset
        GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/6, // offset
        GIR_CustomOperandRenderer, /*InsnID*/0, /*OldInsnID*/0, /*OpIdx*/7, /*OperandRenderer*/GIMT_Encode2(GICR_renderExtractCPol), // auxiliary
        GIR_MergeMemOperands, /*InsnID*/0, /*NumInsns*/1, /*MergeInsnID's*/0,
        GIR_ConstrainSelectedInstOperands, /*InsnID*/0,
        GIR_EraseFromParent, /*InsnID*/0,
        // GIR_Coverage, 4768,
        GIR_Done,
      // Label 6206: @454473
      GIM_Try, /*On fail goto*//*Label 6207*/ GIMT_Encode4(454576), // Rule ID 4776 //
        GIM_CheckHasNoUse, /*MI*/0,
        // MIs[0] offset
        GIM_CheckIsImm, /*MI*/0, /*Op*/6,
        // MIs[0] auxiliary
        GIM_CheckIsImm, /*MI*/0, /*Op*/7,
        // MIs[0] Operand 8
        GIM_CheckIsImm, /*MI*/0, /*Op*/8,
        GIM_CheckComplexPattern, /*MI*/0, /*Op*/5, /*Renderer*/GIMT_Encode2(0), GIMT_Encode2(GICP_gi_buf_soffset),
        // (SIbuffer_atomic_sub:{ *:[i32] } i32:{ *:[i32] }:$vdata_in, v4i32:{ *:[v4i32] }:$rsrc, i32:{ *:[i32] }:$vindex, i32:{ *:[i32] }:$voffset, (BUFSOffset:{ *:[i32] } i32:{ *:[i32] }:$soffset), (timm:{ *:[i32] }):$offset, (timm:{ *:[i32] }):$auxiliary, (timm:{ *:[i1] }))<<P:Predicate_SIbuffer_atomic_sub_noret>>  =>  (BUFFER_ATOMIC_SUB_VBUFFER_BOTHEN anonymous_15037:{ *:[i32] }:$vdata_in, (REG_SEQUENCE:{ *:[i64] } VReg_64:{ *:[i32] }, VGPR_32:{ *:[i32] }:$vindex, sub0:{ *:[i32] }, VGPR_32:{ *:[i32] }:$voffset, sub1:{ *:[i32] }), SReg_128:{ *:[v4i32] }:$rsrc, SCSrc_b32:{ *:[i32] }:$soffset, (timm:{ *:[i32] }):$offset, (extract_cpol:{ *:[i32] } ?:{ *:[i32] }:$auxiliary))
        GIR_MakeTempReg, /*TempRegID*/0, /*TypeID*/GILLT_s64,
        GIR_BuildMI, /*InsnID*/1, /*Opcode*/GIMT_Encode2(TargetOpcode::REG_SEQUENCE),
        GIR_AddTempRegister, /*InsnID*/1, /*TempRegID*/0, /*TempRegFlags*/GIMT_Encode2(RegState::Define),
        GIR_Copy, /*NewInsnID*/1, /*OldInsnID*/0, /*OpIdx*/3, // vindex
        GIR_AddImm8, /*InsnID*/1, /*SubRegIndex*/3,
        GIR_Copy, /*NewInsnID*/1, /*OldInsnID*/0, /*OpIdx*/4, // voffset
        GIR_AddImm8, /*InsnID*/1, /*SubRegIndex*/11,
        GIR_ConstrainOperandRC, /*InsnID*/1, /*Op*/0, GIMT_Encode2(AMDGPU::VReg_64RegClassID),
        GIR_ConstrainOperandRC, /*InsnID*/1, /*Op*/1, GIMT_Encode2(AMDGPU::VGPR_32RegClassID),
        GIR_ConstrainOperandRC, /*InsnID*/1, /*Op*/3, GIMT_Encode2(AMDGPU::VGPR_32RegClassID),
        GIR_BuildMI, /*InsnID*/0, /*Opcode*/GIMT_Encode2(AMDGPU::BUFFER_ATOMIC_SUB_VBUFFER_BOTHEN),
        GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/1, // vdata_in
        GIR_AddSimpleTempRegister, /*InsnID*/0, /*TempRegID*/0,
        GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/2, // rsrc
        GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/0, // soffset
        GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/6, // offset
        GIR_CustomOperandRenderer, /*InsnID*/0, /*OldInsnID*/0, /*OpIdx*/7, /*OperandRenderer*/GIMT_Encode2(GICR_renderExtractCPol), // auxiliary
        GIR_MergeMemOperands, /*InsnID*/0, /*NumInsns*/1, /*MergeInsnID's*/0,
        GIR_ConstrainSelectedInstOperands, /*InsnID*/0,
        GIR_EraseFromParent, /*InsnID*/0,
        // GIR_Coverage, 4776,
        GIR_Done,
      // Label 6207: @454576
      GIM_Try, /*On fail goto*//*Label 6208*/ GIMT_Encode4(454689), // Rule ID 4764 //
        GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasUnrestrictedSOffset),
        GIM_CheckRegBankForClass, /*MI*/0, /*Op*/0, /*RC*/GIMT_Encode2(AMDGPU::AV_32RegClassID),
        // MIs[0] offset
        GIM_CheckIsImm, /*MI*/0, /*Op*/6,
        // MIs[0] auxiliary
        GIM_CheckIsImm, /*MI*/0, /*Op*/7,
        // MIs[0] Operand 8
        GIM_CheckIsImm, /*MI*/0, /*Op*/8,
        GIM_CheckComplexPattern, /*MI*/0, /*Op*/5, /*Renderer*/GIMT_Encode2(0), GIMT_Encode2(GICP_gi_buf_soffset),
        // (SIbuffer_atomic_sub:{ *:[i32] } i32:{ *:[i32] }:$vdata_in, v4i32:{ *:[v4i32] }:$rsrc, i32:{ *:[i32] }:$vindex, i32:{ *:[i32] }:$voffset, (BUFSOffset:{ *:[i32] } i32:{ *:[i32] }:$soffset), (timm:{ *:[i32] }):$offset, (timm:{ *:[i32] }):$auxiliary, (timm:{ *:[i1] }))  =>  (BUFFER_ATOMIC_SUB_BOTHEN_RTN:{ *:[i32] } anonymous_15037:{ *:[i32] }:$vdata_in, (REG_SEQUENCE:{ *:[i64] } VReg_64:{ *:[i32] }, VGPR_32:{ *:[i32] }:$vindex, sub0:{ *:[i32] }, VGPR_32:{ *:[i32] }:$voffset, sub1:{ *:[i32] }), SReg_128:{ *:[v4i32] }:$rsrc, SCSrc_b32:{ *:[i32] }:$soffset, (timm:{ *:[i32] }):$offset, (extract_cpol_set_glc:{ *:[i32] } ?:{ *:[i32] }:$auxiliary))
        GIR_MakeTempReg, /*TempRegID*/0, /*TypeID*/GILLT_s64,
        GIR_BuildMI, /*InsnID*/1, /*Opcode*/GIMT_Encode2(TargetOpcode::REG_SEQUENCE),
        GIR_AddTempRegister, /*InsnID*/1, /*TempRegID*/0, /*TempRegFlags*/GIMT_Encode2(RegState::Define),
        GIR_Copy, /*NewInsnID*/1, /*OldInsnID*/0, /*OpIdx*/3, // vindex
        GIR_AddImm8, /*InsnID*/1, /*SubRegIndex*/3,
        GIR_Copy, /*NewInsnID*/1, /*OldInsnID*/0, /*OpIdx*/4, // voffset
        GIR_AddImm8, /*InsnID*/1, /*SubRegIndex*/11,
        GIR_ConstrainOperandRC, /*InsnID*/1, /*Op*/0, GIMT_Encode2(AMDGPU::VReg_64RegClassID),
        GIR_ConstrainOperandRC, /*InsnID*/1, /*Op*/1, GIMT_Encode2(AMDGPU::VGPR_32RegClassID),
        GIR_ConstrainOperandRC, /*InsnID*/1, /*Op*/3, GIMT_Encode2(AMDGPU::VGPR_32RegClassID),
        GIR_BuildMI, /*InsnID*/0, /*Opcode*/GIMT_Encode2(AMDGPU::BUFFER_ATOMIC_SUB_BOTHEN_RTN),
        GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/0, // DstI[vdata]
        GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/1, // vdata_in
        GIR_AddSimpleTempRegister, /*InsnID*/0, /*TempRegID*/0,
        GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/2, // rsrc
        GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/0, // soffset
        GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/6, // offset
        GIR_CustomOperandRenderer, /*InsnID*/0, /*OldInsnID*/0, /*OpIdx*/7, /*OperandRenderer*/GIMT_Encode2(GICR_renderExtractCpolSetGLC), // auxiliary
        GIR_MergeMemOperands, /*InsnID*/0, /*NumInsns*/1, /*MergeInsnID's*/0,
        GIR_ConstrainSelectedInstOperands, /*InsnID*/0,
        GIR_EraseFromParent, /*InsnID*/0,
        // GIR_Coverage, 4764,
        GIR_Done,
      // Label 6208: @454689
      GIM_Try, /*On fail goto*//*Label 6209*/ GIMT_Encode4(454799), // Rule ID 4772 //
        GIM_CheckRegBankForClass, /*MI*/0, /*Op*/0, /*RC*/GIMT_Encode2(AMDGPU::AV_32RegClassID),
        // MIs[0] offset
        GIM_CheckIsImm, /*MI*/0, /*Op*/6,
        // MIs[0] auxiliary
        GIM_CheckIsImm, /*MI*/0, /*Op*/7,
        // MIs[0] Operand 8
        GIM_CheckIsImm, /*MI*/0, /*Op*/8,
        GIM_CheckComplexPattern, /*MI*/0, /*Op*/5, /*Renderer*/GIMT_Encode2(0), GIMT_Encode2(GICP_gi_buf_soffset),
        // (SIbuffer_atomic_sub:{ *:[i32] } i32:{ *:[i32] }:$vdata_in, v4i32:{ *:[v4i32] }:$rsrc, i32:{ *:[i32] }:$vindex, i32:{ *:[i32] }:$voffset, (BUFSOffset:{ *:[i32] } i32:{ *:[i32] }:$soffset), (timm:{ *:[i32] }):$offset, (timm:{ *:[i32] }):$auxiliary, (timm:{ *:[i1] }))  =>  (BUFFER_ATOMIC_SUB_VBUFFER_BOTHEN_RTN:{ *:[i32] } anonymous_15037:{ *:[i32] }:$vdata_in, (REG_SEQUENCE:{ *:[i64] } VReg_64:{ *:[i32] }, VGPR_32:{ *:[i32] }:$vindex, sub0:{ *:[i32] }, VGPR_32:{ *:[i32] }:$voffset, sub1:{ *:[i32] }), SReg_128:{ *:[v4i32] }:$rsrc, SCSrc_b32:{ *:[i32] }:$soffset, (timm:{ *:[i32] }):$offset, (extract_cpol_set_glc:{ *:[i32] } ?:{ *:[i32] }:$auxiliary))
        GIR_MakeTempReg, /*TempRegID*/0, /*TypeID*/GILLT_s64,
        GIR_BuildMI, /*InsnID*/1, /*Opcode*/GIMT_Encode2(TargetOpcode::REG_SEQUENCE),
        GIR_AddTempRegister, /*InsnID*/1, /*TempRegID*/0, /*TempRegFlags*/GIMT_Encode2(RegState::Define),
        GIR_Copy, /*NewInsnID*/1, /*OldInsnID*/0, /*OpIdx*/3, // vindex
        GIR_AddImm8, /*InsnID*/1, /*SubRegIndex*/3,
        GIR_Copy, /*NewInsnID*/1, /*OldInsnID*/0, /*OpIdx*/4, // voffset
        GIR_AddImm8, /*InsnID*/1, /*SubRegIndex*/11,
        GIR_ConstrainOperandRC, /*InsnID*/1, /*Op*/0, GIMT_Encode2(AMDGPU::VReg_64RegClassID),
        GIR_ConstrainOperandRC, /*InsnID*/1, /*Op*/1, GIMT_Encode2(AMDGPU::VGPR_32RegClassID),
        GIR_ConstrainOperandRC, /*InsnID*/1, /*Op*/3, GIMT_Encode2(AMDGPU::VGPR_32RegClassID),
        GIR_BuildMI, /*InsnID*/0, /*Opcode*/GIMT_Encode2(AMDGPU::BUFFER_ATOMIC_SUB_VBUFFER_BOTHEN_RTN),
        GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/0, // DstI[vdata]
        GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/1, // vdata_in
        GIR_AddSimpleTempRegister, /*InsnID*/0, /*TempRegID*/0,
        GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/2, // rsrc
        GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/0, // soffset
        GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/6, // offset
        GIR_CustomOperandRenderer, /*InsnID*/0, /*OldInsnID*/0, /*OpIdx*/7, /*OperandRenderer*/GIMT_Encode2(GICR_renderExtractCpolSetGLC), // auxiliary
        GIR_MergeMemOperands, /*InsnID*/0, /*NumInsns*/1, /*MergeInsnID's*/0,
        GIR_ConstrainSelectedInstOperands, /*InsnID*/0,
        GIR_EraseFromParent, /*InsnID*/0,
        // GIR_Coverage, 4772,
        GIR_Done,
      // Label 6209: @454799
      GIM_Reject,
    // Label 6193: @454800
    GIM_Reject,
    // Label 6191: @454801
    GIM_Try, /*On fail goto*//*Label 6210*/ GIMT_Encode4(456187),
      GIM_CheckType, /*MI*/0, /*Op*/1, /*Type*/GILLT_s64,
      GIM_CheckType, /*MI*/0, /*Op*/2, /*Type*/GILLT_v4s32,
      GIM_CheckType, /*MI*/0, /*Op*/3, /*Type*/GILLT_s32,
      GIM_CheckType, /*MI*/0, /*Op*/4, /*Type*/GILLT_s32,
      GIM_CheckType, /*MI*/0, /*Op*/5, /*Type*/GILLT_s32,
      GIM_Try, /*On fail goto*//*Label 6211*/ GIMT_Encode4(454904), // Rule ID 4965 //
        GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasUnrestrictedSOffset),
        GIM_CheckHasNoUse, /*MI*/0,
        GIM_CheckConstantInt8, /*MI*/0, /*Op*/3, 0,
        GIM_CheckConstantInt8, /*MI*/0, /*Op*/4, 0,
        // MIs[0] offset
        GIM_CheckIsImm, /*MI*/0, /*Op*/6,
        // MIs[0] auxiliary
        GIM_CheckIsImm, /*MI*/0, /*Op*/7,
        // MIs[0] Operand 8
        GIM_CheckLiteralInt, /*MI*/0, /*Op*/8, GIMT_Encode8(0),
        GIM_CheckComplexPattern, /*MI*/0, /*Op*/5, /*Renderer*/GIMT_Encode2(0), GIMT_Encode2(GICP_gi_buf_soffset),
        // (SIbuffer_atomic_sub:{ *:[i64] } i64:{ *:[i64] }:$vdata_in, v4i32:{ *:[v4i32] }:$rsrc, 0:{ *:[i32] }, 0:{ *:[i32] }, (BUFSOffset:{ *:[i32] } i32:{ *:[i32] }:$soffset), (timm:{ *:[i32] }):$offset, (timm:{ *:[i32] }):$auxiliary, 0:{ *:[i1] })<<P:Predicate_SIbuffer_atomic_sub_noret>>  =>  (BUFFER_ATOMIC_SUB_X2_OFFSET anonymous_15036:{ *:[i64] }:$vdata_in, SReg_128:{ *:[v4i32] }:$rsrc, SCSrc_b32:{ *:[i32] }:$soffset, (timm:{ *:[i32] }):$offset, (extract_cpol:{ *:[i32] } ?:{ *:[i32] }:$auxiliary))
        GIR_BuildMI, /*InsnID*/0, /*Opcode*/GIMT_Encode2(AMDGPU::BUFFER_ATOMIC_SUB_X2_OFFSET),
        GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/1, // vdata_in
        GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/2, // rsrc
        GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/0, // soffset
        GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/6, // offset
        GIR_CustomOperandRenderer, /*InsnID*/0, /*OldInsnID*/0, /*OpIdx*/7, /*OperandRenderer*/GIMT_Encode2(GICR_renderExtractCPol), // auxiliary
        GIR_MergeMemOperands, /*InsnID*/0, /*NumInsns*/1, /*MergeInsnID's*/0,
        GIR_ConstrainSelectedInstOperands, /*InsnID*/0,
        GIR_EraseFromParent, /*InsnID*/0,
        // GIR_Coverage, 4965,
        GIR_Done,
      // Label 6211: @454904
      GIM_Try, /*On fail goto*//*Label 6212*/ GIMT_Encode4(454979), // Rule ID 4973 //
        GIM_CheckHasNoUse, /*MI*/0,
        GIM_CheckConstantInt8, /*MI*/0, /*Op*/3, 0,
        GIM_CheckConstantInt8, /*MI*/0, /*Op*/4, 0,
        // MIs[0] offset
        GIM_CheckIsImm, /*MI*/0, /*Op*/6,
        // MIs[0] auxiliary
        GIM_CheckIsImm, /*MI*/0, /*Op*/7,
        // MIs[0] Operand 8
        GIM_CheckLiteralInt, /*MI*/0, /*Op*/8, GIMT_Encode8(0),
        GIM_CheckComplexPattern, /*MI*/0, /*Op*/5, /*Renderer*/GIMT_Encode2(0), GIMT_Encode2(GICP_gi_buf_soffset),
        // (SIbuffer_atomic_sub:{ *:[i64] } i64:{ *:[i64] }:$vdata_in, v4i32:{ *:[v4i32] }:$rsrc, 0:{ *:[i32] }, 0:{ *:[i32] }, (BUFSOffset:{ *:[i32] } i32:{ *:[i32] }:$soffset), (timm:{ *:[i32] }):$offset, (timm:{ *:[i32] }):$auxiliary, 0:{ *:[i1] })<<P:Predicate_SIbuffer_atomic_sub_noret>>  =>  (BUFFER_ATOMIC_SUB_X2_VBUFFER_OFFSET anonymous_15036:{ *:[i64] }:$vdata_in, SReg_128:{ *:[v4i32] }:$rsrc, SCSrc_b32:{ *:[i32] }:$soffset, (timm:{ *:[i32] }):$offset, (extract_cpol:{ *:[i32] } ?:{ *:[i32] }:$auxiliary))
        GIR_BuildMI, /*InsnID*/0, /*Opcode*/GIMT_Encode2(AMDGPU::BUFFER_ATOMIC_SUB_X2_VBUFFER_OFFSET),
        GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/1, // vdata_in
        GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/2, // rsrc
        GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/0, // soffset
        GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/6, // offset
        GIR_CustomOperandRenderer, /*InsnID*/0, /*OldInsnID*/0, /*OpIdx*/7, /*OperandRenderer*/GIMT_Encode2(GICR_renderExtractCPol), // auxiliary
        GIR_MergeMemOperands, /*InsnID*/0, /*NumInsns*/1, /*MergeInsnID's*/0,
        GIR_ConstrainSelectedInstOperands, /*InsnID*/0,
        GIR_EraseFromParent, /*InsnID*/0,
        // GIR_Coverage, 4973,
        GIR_Done,
      // Label 6212: @454979
      GIM_Try, /*On fail goto*//*Label 6213*/ GIMT_Encode4(455064), // Rule ID 4961 //
        GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasUnrestrictedSOffset),
        GIM_CheckRegBankForClass, /*MI*/0, /*Op*/0, /*RC*/GIMT_Encode2(AMDGPU::AV_64RegClassID),
        GIM_CheckConstantInt8, /*MI*/0, /*Op*/3, 0,
        GIM_CheckConstantInt8, /*MI*/0, /*Op*/4, 0,
        // MIs[0] offset
        GIM_CheckIsImm, /*MI*/0, /*Op*/6,
        // MIs[0] auxiliary
        GIM_CheckIsImm, /*MI*/0, /*Op*/7,
        // MIs[0] Operand 8
        GIM_CheckLiteralInt, /*MI*/0, /*Op*/8, GIMT_Encode8(0),
        GIM_CheckComplexPattern, /*MI*/0, /*Op*/5, /*Renderer*/GIMT_Encode2(0), GIMT_Encode2(GICP_gi_buf_soffset),
        // (SIbuffer_atomic_sub:{ *:[i64] } i64:{ *:[i64] }:$vdata_in, v4i32:{ *:[v4i32] }:$rsrc, 0:{ *:[i32] }, 0:{ *:[i32] }, (BUFSOffset:{ *:[i32] } i32:{ *:[i32] }:$soffset), (timm:{ *:[i32] }):$offset, (timm:{ *:[i32] }):$auxiliary, 0:{ *:[i1] })  =>  (BUFFER_ATOMIC_SUB_X2_OFFSET_RTN:{ *:[i64] } anonymous_15036:{ *:[i64] }:$vdata_in, SReg_128:{ *:[v4i32] }:$rsrc, SCSrc_b32:{ *:[i32] }:$soffset, (timm:{ *:[i32] }):$offset, (extract_cpol_set_glc:{ *:[i32] } ?:{ *:[i32] }:$auxiliary))
        GIR_BuildMI, /*InsnID*/0, /*Opcode*/GIMT_Encode2(AMDGPU::BUFFER_ATOMIC_SUB_X2_OFFSET_RTN),
        GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/0, // DstI[vdata]
        GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/1, // vdata_in
        GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/2, // rsrc
        GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/0, // soffset
        GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/6, // offset
        GIR_CustomOperandRenderer, /*InsnID*/0, /*OldInsnID*/0, /*OpIdx*/7, /*OperandRenderer*/GIMT_Encode2(GICR_renderExtractCpolSetGLC), // auxiliary
        GIR_MergeMemOperands, /*InsnID*/0, /*NumInsns*/1, /*MergeInsnID's*/0,
        GIR_ConstrainSelectedInstOperands, /*InsnID*/0,
        GIR_EraseFromParent, /*InsnID*/0,
        // GIR_Coverage, 4961,
        GIR_Done,
      // Label 6213: @455064
      GIM_Try, /*On fail goto*//*Label 6214*/ GIMT_Encode4(455146), // Rule ID 4969 //
        GIM_CheckRegBankForClass, /*MI*/0, /*Op*/0, /*RC*/GIMT_Encode2(AMDGPU::AV_64RegClassID),
        GIM_CheckConstantInt8, /*MI*/0, /*Op*/3, 0,
        GIM_CheckConstantInt8, /*MI*/0, /*Op*/4, 0,
        // MIs[0] offset
        GIM_CheckIsImm, /*MI*/0, /*Op*/6,
        // MIs[0] auxiliary
        GIM_CheckIsImm, /*MI*/0, /*Op*/7,
        // MIs[0] Operand 8
        GIM_CheckLiteralInt, /*MI*/0, /*Op*/8, GIMT_Encode8(0),
        GIM_CheckComplexPattern, /*MI*/0, /*Op*/5, /*Renderer*/GIMT_Encode2(0), GIMT_Encode2(GICP_gi_buf_soffset),
        // (SIbuffer_atomic_sub:{ *:[i64] } i64:{ *:[i64] }:$vdata_in, v4i32:{ *:[v4i32] }:$rsrc, 0:{ *:[i32] }, 0:{ *:[i32] }, (BUFSOffset:{ *:[i32] } i32:{ *:[i32] }:$soffset), (timm:{ *:[i32] }):$offset, (timm:{ *:[i32] }):$auxiliary, 0:{ *:[i1] })  =>  (BUFFER_ATOMIC_SUB_X2_VBUFFER_OFFSET_RTN:{ *:[i64] } anonymous_15036:{ *:[i64] }:$vdata_in, SReg_128:{ *:[v4i32] }:$rsrc, SCSrc_b32:{ *:[i32] }:$soffset, (timm:{ *:[i32] }):$offset, (extract_cpol_set_glc:{ *:[i32] } ?:{ *:[i32] }:$auxiliary))
        GIR_BuildMI, /*InsnID*/0, /*Opcode*/GIMT_Encode2(AMDGPU::BUFFER_ATOMIC_SUB_X2_VBUFFER_OFFSET_RTN),
        GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/0, // DstI[vdata]
        GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/1, // vdata_in
        GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/2, // rsrc
        GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/0, // soffset
        GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/6, // offset
        GIR_CustomOperandRenderer, /*InsnID*/0, /*OldInsnID*/0, /*OpIdx*/7, /*OperandRenderer*/GIMT_Encode2(GICR_renderExtractCpolSetGLC), // auxiliary
        GIR_MergeMemOperands, /*InsnID*/0, /*NumInsns*/1, /*MergeInsnID's*/0,
        GIR_ConstrainSelectedInstOperands, /*InsnID*/0,
        GIR_EraseFromParent, /*InsnID*/0,
        // GIR_Coverage, 4969,
        GIR_Done,
      // Label 6214: @455146
      GIM_Try, /*On fail goto*//*Label 6215*/ GIMT_Encode4(455224), // Rule ID 4967 //
        GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasUnrestrictedSOffset),
        GIM_CheckHasNoUse, /*MI*/0,
        GIM_CheckConstantInt8, /*MI*/0, /*Op*/3, 0,
        // MIs[0] offset
        GIM_CheckIsImm, /*MI*/0, /*Op*/6,
        // MIs[0] auxiliary
        GIM_CheckIsImm, /*MI*/0, /*Op*/7,
        // MIs[0] Operand 8
        GIM_CheckLiteralInt, /*MI*/0, /*Op*/8, GIMT_Encode8(0),
        GIM_CheckComplexPattern, /*MI*/0, /*Op*/5, /*Renderer*/GIMT_Encode2(0), GIMT_Encode2(GICP_gi_buf_soffset),
        // (SIbuffer_atomic_sub:{ *:[i64] } i64:{ *:[i64] }:$vdata_in, v4i32:{ *:[v4i32] }:$rsrc, 0:{ *:[i32] }, i32:{ *:[i32] }:$voffset, (BUFSOffset:{ *:[i32] } i32:{ *:[i32] }:$soffset), (timm:{ *:[i32] }):$offset, (timm:{ *:[i32] }):$auxiliary, 0:{ *:[i1] })<<P:Predicate_SIbuffer_atomic_sub_noret>>  =>  (BUFFER_ATOMIC_SUB_X2_OFFEN anonymous_15036:{ *:[i64] }:$vdata_in, VGPR_32:{ *:[i32] }:$voffset, SReg_128:{ *:[v4i32] }:$rsrc, SCSrc_b32:{ *:[i32] }:$soffset, (timm:{ *:[i32] }):$offset, (extract_cpol:{ *:[i32] } ?:{ *:[i32] }:$auxiliary))
        GIR_BuildMI, /*InsnID*/0, /*Opcode*/GIMT_Encode2(AMDGPU::BUFFER_ATOMIC_SUB_X2_OFFEN),
        GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/1, // vdata_in
        GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/4, // voffset
        GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/2, // rsrc
        GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/0, // soffset
        GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/6, // offset
        GIR_CustomOperandRenderer, /*InsnID*/0, /*OldInsnID*/0, /*OpIdx*/7, /*OperandRenderer*/GIMT_Encode2(GICR_renderExtractCPol), // auxiliary
        GIR_MergeMemOperands, /*InsnID*/0, /*NumInsns*/1, /*MergeInsnID's*/0,
        GIR_ConstrainSelectedInstOperands, /*InsnID*/0,
        GIR_EraseFromParent, /*InsnID*/0,
        // GIR_Coverage, 4967,
        GIR_Done,
      // Label 6215: @455224
      GIM_Try, /*On fail goto*//*Label 6216*/ GIMT_Encode4(455299), // Rule ID 4975 //
        GIM_CheckHasNoUse, /*MI*/0,
        GIM_CheckConstantInt8, /*MI*/0, /*Op*/3, 0,
        // MIs[0] offset
        GIM_CheckIsImm, /*MI*/0, /*Op*/6,
        // MIs[0] auxiliary
        GIM_CheckIsImm, /*MI*/0, /*Op*/7,
        // MIs[0] Operand 8
        GIM_CheckLiteralInt, /*MI*/0, /*Op*/8, GIMT_Encode8(0),
        GIM_CheckComplexPattern, /*MI*/0, /*Op*/5, /*Renderer*/GIMT_Encode2(0), GIMT_Encode2(GICP_gi_buf_soffset),
        // (SIbuffer_atomic_sub:{ *:[i64] } i64:{ *:[i64] }:$vdata_in, v4i32:{ *:[v4i32] }:$rsrc, 0:{ *:[i32] }, i32:{ *:[i32] }:$voffset, (BUFSOffset:{ *:[i32] } i32:{ *:[i32] }:$soffset), (timm:{ *:[i32] }):$offset, (timm:{ *:[i32] }):$auxiliary, 0:{ *:[i1] })<<P:Predicate_SIbuffer_atomic_sub_noret>>  =>  (BUFFER_ATOMIC_SUB_X2_VBUFFER_OFFEN anonymous_15036:{ *:[i64] }:$vdata_in, VGPR_32:{ *:[i32] }:$voffset, SReg_128:{ *:[v4i32] }:$rsrc, SCSrc_b32:{ *:[i32] }:$soffset, (timm:{ *:[i32] }):$offset, (extract_cpol:{ *:[i32] } ?:{ *:[i32] }:$auxiliary))
        GIR_BuildMI, /*InsnID*/0, /*Opcode*/GIMT_Encode2(AMDGPU::BUFFER_ATOMIC_SUB_X2_VBUFFER_OFFEN),
        GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/1, // vdata_in
        GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/4, // voffset
        GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/2, // rsrc
        GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/0, // soffset
        GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/6, // offset
        GIR_CustomOperandRenderer, /*InsnID*/0, /*OldInsnID*/0, /*OpIdx*/7, /*OperandRenderer*/GIMT_Encode2(GICR_renderExtractCPol), // auxiliary
        GIR_MergeMemOperands, /*InsnID*/0, /*NumInsns*/1, /*MergeInsnID's*/0,
        GIR_ConstrainSelectedInstOperands, /*InsnID*/0,
        GIR_EraseFromParent, /*InsnID*/0,
        // GIR_Coverage, 4975,
        GIR_Done,
      // Label 6216: @455299
      GIM_Try, /*On fail goto*//*Label 6217*/ GIMT_Encode4(455384), // Rule ID 4963 //
        GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasUnrestrictedSOffset),
        GIM_CheckRegBankForClass, /*MI*/0, /*Op*/0, /*RC*/GIMT_Encode2(AMDGPU::AV_64RegClassID),
        GIM_CheckConstantInt8, /*MI*/0, /*Op*/3, 0,
        // MIs[0] offset
        GIM_CheckIsImm, /*MI*/0, /*Op*/6,
        // MIs[0] auxiliary
        GIM_CheckIsImm, /*MI*/0, /*Op*/7,
        // MIs[0] Operand 8
        GIM_CheckLiteralInt, /*MI*/0, /*Op*/8, GIMT_Encode8(0),
        GIM_CheckComplexPattern, /*MI*/0, /*Op*/5, /*Renderer*/GIMT_Encode2(0), GIMT_Encode2(GICP_gi_buf_soffset),
        // (SIbuffer_atomic_sub:{ *:[i64] } i64:{ *:[i64] }:$vdata_in, v4i32:{ *:[v4i32] }:$rsrc, 0:{ *:[i32] }, i32:{ *:[i32] }:$voffset, (BUFSOffset:{ *:[i32] } i32:{ *:[i32] }:$soffset), (timm:{ *:[i32] }):$offset, (timm:{ *:[i32] }):$auxiliary, 0:{ *:[i1] })  =>  (BUFFER_ATOMIC_SUB_X2_OFFEN_RTN:{ *:[i64] } anonymous_15036:{ *:[i64] }:$vdata_in, VGPR_32:{ *:[i32] }:$voffset, SReg_128:{ *:[v4i32] }:$rsrc, SCSrc_b32:{ *:[i32] }:$soffset, (timm:{ *:[i32] }):$offset, (extract_cpol_set_glc:{ *:[i32] } ?:{ *:[i32] }:$auxiliary))
        GIR_BuildMI, /*InsnID*/0, /*Opcode*/GIMT_Encode2(AMDGPU::BUFFER_ATOMIC_SUB_X2_OFFEN_RTN),
        GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/0, // DstI[vdata]
        GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/1, // vdata_in
        GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/4, // voffset
        GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/2, // rsrc
        GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/0, // soffset
        GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/6, // offset
        GIR_CustomOperandRenderer, /*InsnID*/0, /*OldInsnID*/0, /*OpIdx*/7, /*OperandRenderer*/GIMT_Encode2(GICR_renderExtractCpolSetGLC), // auxiliary
        GIR_MergeMemOperands, /*InsnID*/0, /*NumInsns*/1, /*MergeInsnID's*/0,
        GIR_ConstrainSelectedInstOperands, /*InsnID*/0,
        GIR_EraseFromParent, /*InsnID*/0,
        // GIR_Coverage, 4963,
        GIR_Done,
      // Label 6217: @455384
      GIM_Try, /*On fail goto*//*Label 6218*/ GIMT_Encode4(455466), // Rule ID 4971 //
        GIM_CheckRegBankForClass, /*MI*/0, /*Op*/0, /*RC*/GIMT_Encode2(AMDGPU::AV_64RegClassID),
        GIM_CheckConstantInt8, /*MI*/0, /*Op*/3, 0,
        // MIs[0] offset
        GIM_CheckIsImm, /*MI*/0, /*Op*/6,
        // MIs[0] auxiliary
        GIM_CheckIsImm, /*MI*/0, /*Op*/7,
        // MIs[0] Operand 8
        GIM_CheckLiteralInt, /*MI*/0, /*Op*/8, GIMT_Encode8(0),
        GIM_CheckComplexPattern, /*MI*/0, /*Op*/5, /*Renderer*/GIMT_Encode2(0), GIMT_Encode2(GICP_gi_buf_soffset),
        // (SIbuffer_atomic_sub:{ *:[i64] } i64:{ *:[i64] }:$vdata_in, v4i32:{ *:[v4i32] }:$rsrc, 0:{ *:[i32] }, i32:{ *:[i32] }:$voffset, (BUFSOffset:{ *:[i32] } i32:{ *:[i32] }:$soffset), (timm:{ *:[i32] }):$offset, (timm:{ *:[i32] }):$auxiliary, 0:{ *:[i1] })  =>  (BUFFER_ATOMIC_SUB_X2_VBUFFER_OFFEN_RTN:{ *:[i64] } anonymous_15036:{ *:[i64] }:$vdata_in, VGPR_32:{ *:[i32] }:$voffset, SReg_128:{ *:[v4i32] }:$rsrc, SCSrc_b32:{ *:[i32] }:$soffset, (timm:{ *:[i32] }):$offset, (extract_cpol_set_glc:{ *:[i32] } ?:{ *:[i32] }:$auxiliary))
        GIR_BuildMI, /*InsnID*/0, /*Opcode*/GIMT_Encode2(AMDGPU::BUFFER_ATOMIC_SUB_X2_VBUFFER_OFFEN_RTN),
        GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/0, // DstI[vdata]
        GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/1, // vdata_in
        GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/4, // voffset
        GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/2, // rsrc
        GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/0, // soffset
        GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/6, // offset
        GIR_CustomOperandRenderer, /*InsnID*/0, /*OldInsnID*/0, /*OpIdx*/7, /*OperandRenderer*/GIMT_Encode2(GICR_renderExtractCpolSetGLC), // auxiliary
        GIR_MergeMemOperands, /*InsnID*/0, /*NumInsns*/1, /*MergeInsnID's*/0,
        GIR_ConstrainSelectedInstOperands, /*InsnID*/0,
        GIR_EraseFromParent, /*InsnID*/0,
        // GIR_Coverage, 4971,
        GIR_Done,
      // Label 6218: @455466
      GIM_Try, /*On fail goto*//*Label 6219*/ GIMT_Encode4(455536), // Rule ID 4966 //
        GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasUnrestrictedSOffset),
        GIM_CheckHasNoUse, /*MI*/0,
        GIM_CheckConstantInt8, /*MI*/0, /*Op*/4, 0,
        // MIs[0] offset
        GIM_CheckIsImm, /*MI*/0, /*Op*/6,
        // MIs[0] auxiliary
        GIM_CheckIsImm, /*MI*/0, /*Op*/7,
        // MIs[0] Operand 8
        GIM_CheckIsImm, /*MI*/0, /*Op*/8,
        GIM_CheckComplexPattern, /*MI*/0, /*Op*/5, /*Renderer*/GIMT_Encode2(0), GIMT_Encode2(GICP_gi_buf_soffset),
        // (SIbuffer_atomic_sub:{ *:[i64] } i64:{ *:[i64] }:$vdata_in, v4i32:{ *:[v4i32] }:$rsrc, i32:{ *:[i32] }:$vindex, 0:{ *:[i32] }, (BUFSOffset:{ *:[i32] } i32:{ *:[i32] }:$soffset), (timm:{ *:[i32] }):$offset, (timm:{ *:[i32] }):$auxiliary, (timm:{ *:[i1] }))<<P:Predicate_SIbuffer_atomic_sub_noret>>  =>  (BUFFER_ATOMIC_SUB_X2_IDXEN anonymous_15036:{ *:[i64] }:$vdata_in, VGPR_32:{ *:[i32] }:$vindex, SReg_128:{ *:[v4i32] }:$rsrc, SCSrc_b32:{ *:[i32] }:$soffset, (timm:{ *:[i32] }):$offset, (extract_cpol:{ *:[i32] } ?:{ *:[i32] }:$auxiliary))
        GIR_BuildMI, /*InsnID*/0, /*Opcode*/GIMT_Encode2(AMDGPU::BUFFER_ATOMIC_SUB_X2_IDXEN),
        GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/1, // vdata_in
        GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/3, // vindex
        GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/2, // rsrc
        GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/0, // soffset
        GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/6, // offset
        GIR_CustomOperandRenderer, /*InsnID*/0, /*OldInsnID*/0, /*OpIdx*/7, /*OperandRenderer*/GIMT_Encode2(GICR_renderExtractCPol), // auxiliary
        GIR_MergeMemOperands, /*InsnID*/0, /*NumInsns*/1, /*MergeInsnID's*/0,
        GIR_ConstrainSelectedInstOperands, /*InsnID*/0,
        GIR_EraseFromParent, /*InsnID*/0,
        // GIR_Coverage, 4966,
        GIR_Done,
      // Label 6219: @455536
      GIM_Try, /*On fail goto*//*Label 6220*/ GIMT_Encode4(455603), // Rule ID 4974 //
        GIM_CheckHasNoUse, /*MI*/0,
        GIM_CheckConstantInt8, /*MI*/0, /*Op*/4, 0,
        // MIs[0] offset
        GIM_CheckIsImm, /*MI*/0, /*Op*/6,
        // MIs[0] auxiliary
        GIM_CheckIsImm, /*MI*/0, /*Op*/7,
        // MIs[0] Operand 8
        GIM_CheckIsImm, /*MI*/0, /*Op*/8,
        GIM_CheckComplexPattern, /*MI*/0, /*Op*/5, /*Renderer*/GIMT_Encode2(0), GIMT_Encode2(GICP_gi_buf_soffset),
        // (SIbuffer_atomic_sub:{ *:[i64] } i64:{ *:[i64] }:$vdata_in, v4i32:{ *:[v4i32] }:$rsrc, i32:{ *:[i32] }:$vindex, 0:{ *:[i32] }, (BUFSOffset:{ *:[i32] } i32:{ *:[i32] }:$soffset), (timm:{ *:[i32] }):$offset, (timm:{ *:[i32] }):$auxiliary, (timm:{ *:[i1] }))<<P:Predicate_SIbuffer_atomic_sub_noret>>  =>  (BUFFER_ATOMIC_SUB_X2_VBUFFER_IDXEN anonymous_15036:{ *:[i64] }:$vdata_in, VGPR_32:{ *:[i32] }:$vindex, SReg_128:{ *:[v4i32] }:$rsrc, SCSrc_b32:{ *:[i32] }:$soffset, (timm:{ *:[i32] }):$offset, (extract_cpol:{ *:[i32] } ?:{ *:[i32] }:$auxiliary))
        GIR_BuildMI, /*InsnID*/0, /*Opcode*/GIMT_Encode2(AMDGPU::BUFFER_ATOMIC_SUB_X2_VBUFFER_IDXEN),
        GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/1, // vdata_in
        GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/3, // vindex
        GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/2, // rsrc
        GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/0, // soffset
        GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/6, // offset
        GIR_CustomOperandRenderer, /*InsnID*/0, /*OldInsnID*/0, /*OpIdx*/7, /*OperandRenderer*/GIMT_Encode2(GICR_renderExtractCPol), // auxiliary
        GIR_MergeMemOperands, /*InsnID*/0, /*NumInsns*/1, /*MergeInsnID's*/0,
        GIR_ConstrainSelectedInstOperands, /*InsnID*/0,
        GIR_EraseFromParent, /*InsnID*/0,
        // GIR_Coverage, 4974,
        GIR_Done,
      // Label 6220: @455603
      GIM_Try, /*On fail goto*//*Label 6221*/ GIMT_Encode4(455680), // Rule ID 4962 //
        GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasUnrestrictedSOffset),
        GIM_CheckRegBankForClass, /*MI*/0, /*Op*/0, /*RC*/GIMT_Encode2(AMDGPU::AV_64RegClassID),
        GIM_CheckConstantInt8, /*MI*/0, /*Op*/4, 0,
        // MIs[0] offset
        GIM_CheckIsImm, /*MI*/0, /*Op*/6,
        // MIs[0] auxiliary
        GIM_CheckIsImm, /*MI*/0, /*Op*/7,
        // MIs[0] Operand 8
        GIM_CheckIsImm, /*MI*/0, /*Op*/8,
        GIM_CheckComplexPattern, /*MI*/0, /*Op*/5, /*Renderer*/GIMT_Encode2(0), GIMT_Encode2(GICP_gi_buf_soffset),
        // (SIbuffer_atomic_sub:{ *:[i64] } i64:{ *:[i64] }:$vdata_in, v4i32:{ *:[v4i32] }:$rsrc, i32:{ *:[i32] }:$vindex, 0:{ *:[i32] }, (BUFSOffset:{ *:[i32] } i32:{ *:[i32] }:$soffset), (timm:{ *:[i32] }):$offset, (timm:{ *:[i32] }):$auxiliary, (timm:{ *:[i1] }))  =>  (BUFFER_ATOMIC_SUB_X2_IDXEN_RTN:{ *:[i64] } anonymous_15036:{ *:[i64] }:$vdata_in, VGPR_32:{ *:[i32] }:$vindex, SReg_128:{ *:[v4i32] }:$rsrc, SCSrc_b32:{ *:[i32] }:$soffset, (timm:{ *:[i32] }):$offset, (extract_cpol_set_glc:{ *:[i32] } ?:{ *:[i32] }:$auxiliary))
        GIR_BuildMI, /*InsnID*/0, /*Opcode*/GIMT_Encode2(AMDGPU::BUFFER_ATOMIC_SUB_X2_IDXEN_RTN),
        GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/0, // DstI[vdata]
        GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/1, // vdata_in
        GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/3, // vindex
        GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/2, // rsrc
        GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/0, // soffset
        GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/6, // offset
        GIR_CustomOperandRenderer, /*InsnID*/0, /*OldInsnID*/0, /*OpIdx*/7, /*OperandRenderer*/GIMT_Encode2(GICR_renderExtractCpolSetGLC), // auxiliary
        GIR_MergeMemOperands, /*InsnID*/0, /*NumInsns*/1, /*MergeInsnID's*/0,
        GIR_ConstrainSelectedInstOperands, /*InsnID*/0,
        GIR_EraseFromParent, /*InsnID*/0,
        // GIR_Coverage, 4962,
        GIR_Done,
      // Label 6221: @455680
      GIM_Try, /*On fail goto*//*Label 6222*/ GIMT_Encode4(455754), // Rule ID 4970 //
        GIM_CheckRegBankForClass, /*MI*/0, /*Op*/0, /*RC*/GIMT_Encode2(AMDGPU::AV_64RegClassID),
        GIM_CheckConstantInt8, /*MI*/0, /*Op*/4, 0,
        // MIs[0] offset
        GIM_CheckIsImm, /*MI*/0, /*Op*/6,
        // MIs[0] auxiliary
        GIM_CheckIsImm, /*MI*/0, /*Op*/7,
        // MIs[0] Operand 8
        GIM_CheckIsImm, /*MI*/0, /*Op*/8,
        GIM_CheckComplexPattern, /*MI*/0, /*Op*/5, /*Renderer*/GIMT_Encode2(0), GIMT_Encode2(GICP_gi_buf_soffset),
        // (SIbuffer_atomic_sub:{ *:[i64] } i64:{ *:[i64] }:$vdata_in, v4i32:{ *:[v4i32] }:$rsrc, i32:{ *:[i32] }:$vindex, 0:{ *:[i32] }, (BUFSOffset:{ *:[i32] } i32:{ *:[i32] }:$soffset), (timm:{ *:[i32] }):$offset, (timm:{ *:[i32] }):$auxiliary, (timm:{ *:[i1] }))  =>  (BUFFER_ATOMIC_SUB_X2_VBUFFER_IDXEN_RTN:{ *:[i64] } anonymous_15036:{ *:[i64] }:$vdata_in, VGPR_32:{ *:[i32] }:$vindex, SReg_128:{ *:[v4i32] }:$rsrc, SCSrc_b32:{ *:[i32] }:$soffset, (timm:{ *:[i32] }):$offset, (extract_cpol_set_glc:{ *:[i32] } ?:{ *:[i32] }:$auxiliary))
        GIR_BuildMI, /*InsnID*/0, /*Opcode*/GIMT_Encode2(AMDGPU::BUFFER_ATOMIC_SUB_X2_VBUFFER_IDXEN_RTN),
        GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/0, // DstI[vdata]
        GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/1, // vdata_in
        GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/3, // vindex
        GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/2, // rsrc
        GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/0, // soffset
        GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/6, // offset
        GIR_CustomOperandRenderer, /*InsnID*/0, /*OldInsnID*/0, /*OpIdx*/7, /*OperandRenderer*/GIMT_Encode2(GICR_renderExtractCpolSetGLC), // auxiliary
        GIR_MergeMemOperands, /*InsnID*/0, /*NumInsns*/1, /*MergeInsnID's*/0,
        GIR_ConstrainSelectedInstOperands, /*InsnID*/0,
        GIR_EraseFromParent, /*InsnID*/0,
        // GIR_Coverage, 4970,
        GIR_Done,
      // Label 6222: @455754
      GIM_Try, /*On fail goto*//*Label 6223*/ GIMT_Encode4(455860), // Rule ID 4968 //
        GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasUnrestrictedSOffset),
        GIM_CheckHasNoUse, /*MI*/0,
        // MIs[0] offset
        GIM_CheckIsImm, /*MI*/0, /*Op*/6,
        // MIs[0] auxiliary
        GIM_CheckIsImm, /*MI*/0, /*Op*/7,
        // MIs[0] Operand 8
        GIM_CheckIsImm, /*MI*/0, /*Op*/8,
        GIM_CheckComplexPattern, /*MI*/0, /*Op*/5, /*Renderer*/GIMT_Encode2(0), GIMT_Encode2(GICP_gi_buf_soffset),
        // (SIbuffer_atomic_sub:{ *:[i64] } i64:{ *:[i64] }:$vdata_in, v4i32:{ *:[v4i32] }:$rsrc, i32:{ *:[i32] }:$vindex, i32:{ *:[i32] }:$voffset, (BUFSOffset:{ *:[i32] } i32:{ *:[i32] }:$soffset), (timm:{ *:[i32] }):$offset, (timm:{ *:[i32] }):$auxiliary, (timm:{ *:[i1] }))<<P:Predicate_SIbuffer_atomic_sub_noret>>  =>  (BUFFER_ATOMIC_SUB_X2_BOTHEN anonymous_15036:{ *:[i64] }:$vdata_in, (REG_SEQUENCE:{ *:[i64] } VReg_64:{ *:[i32] }, VGPR_32:{ *:[i32] }:$vindex, sub0:{ *:[i32] }, VGPR_32:{ *:[i32] }:$voffset, sub1:{ *:[i32] }), SReg_128:{ *:[v4i32] }:$rsrc, SCSrc_b32:{ *:[i32] }:$soffset, (timm:{ *:[i32] }):$offset, (extract_cpol:{ *:[i32] } ?:{ *:[i32] }:$auxiliary))
        GIR_MakeTempReg, /*TempRegID*/0, /*TypeID*/GILLT_s64,
        GIR_BuildMI, /*InsnID*/1, /*Opcode*/GIMT_Encode2(TargetOpcode::REG_SEQUENCE),
        GIR_AddTempRegister, /*InsnID*/1, /*TempRegID*/0, /*TempRegFlags*/GIMT_Encode2(RegState::Define),
        GIR_Copy, /*NewInsnID*/1, /*OldInsnID*/0, /*OpIdx*/3, // vindex
        GIR_AddImm8, /*InsnID*/1, /*SubRegIndex*/3,
        GIR_Copy, /*NewInsnID*/1, /*OldInsnID*/0, /*OpIdx*/4, // voffset
        GIR_AddImm8, /*InsnID*/1, /*SubRegIndex*/11,
        GIR_ConstrainOperandRC, /*InsnID*/1, /*Op*/0, GIMT_Encode2(AMDGPU::VReg_64RegClassID),
        GIR_ConstrainOperandRC, /*InsnID*/1, /*Op*/1, GIMT_Encode2(AMDGPU::VGPR_32RegClassID),
        GIR_ConstrainOperandRC, /*InsnID*/1, /*Op*/3, GIMT_Encode2(AMDGPU::VGPR_32RegClassID),
        GIR_BuildMI, /*InsnID*/0, /*Opcode*/GIMT_Encode2(AMDGPU::BUFFER_ATOMIC_SUB_X2_BOTHEN),
        GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/1, // vdata_in
        GIR_AddSimpleTempRegister, /*InsnID*/0, /*TempRegID*/0,
        GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/2, // rsrc
        GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/0, // soffset
        GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/6, // offset
        GIR_CustomOperandRenderer, /*InsnID*/0, /*OldInsnID*/0, /*OpIdx*/7, /*OperandRenderer*/GIMT_Encode2(GICR_renderExtractCPol), // auxiliary
        GIR_MergeMemOperands, /*InsnID*/0, /*NumInsns*/1, /*MergeInsnID's*/0,
        GIR_ConstrainSelectedInstOperands, /*InsnID*/0,
        GIR_EraseFromParent, /*InsnID*/0,
        // GIR_Coverage, 4968,
        GIR_Done,
      // Label 6223: @455860
      GIM_Try, /*On fail goto*//*Label 6224*/ GIMT_Encode4(455963), // Rule ID 4976 //
        GIM_CheckHasNoUse, /*MI*/0,
        // MIs[0] offset
        GIM_CheckIsImm, /*MI*/0, /*Op*/6,
        // MIs[0] auxiliary
        GIM_CheckIsImm, /*MI*/0, /*Op*/7,
        // MIs[0] Operand 8
        GIM_CheckIsImm, /*MI*/0, /*Op*/8,
        GIM_CheckComplexPattern, /*MI*/0, /*Op*/5, /*Renderer*/GIMT_Encode2(0), GIMT_Encode2(GICP_gi_buf_soffset),
        // (SIbuffer_atomic_sub:{ *:[i64] } i64:{ *:[i64] }:$vdata_in, v4i32:{ *:[v4i32] }:$rsrc, i32:{ *:[i32] }:$vindex, i32:{ *:[i32] }:$voffset, (BUFSOffset:{ *:[i32] } i32:{ *:[i32] }:$soffset), (timm:{ *:[i32] }):$offset, (timm:{ *:[i32] }):$auxiliary, (timm:{ *:[i1] }))<<P:Predicate_SIbuffer_atomic_sub_noret>>  =>  (BUFFER_ATOMIC_SUB_X2_VBUFFER_BOTHEN anonymous_15036:{ *:[i64] }:$vdata_in, (REG_SEQUENCE:{ *:[i64] } VReg_64:{ *:[i32] }, VGPR_32:{ *:[i32] }:$vindex, sub0:{ *:[i32] }, VGPR_32:{ *:[i32] }:$voffset, sub1:{ *:[i32] }), SReg_128:{ *:[v4i32] }:$rsrc, SCSrc_b32:{ *:[i32] }:$soffset, (timm:{ *:[i32] }):$offset, (extract_cpol:{ *:[i32] } ?:{ *:[i32] }:$auxiliary))
        GIR_MakeTempReg, /*TempRegID*/0, /*TypeID*/GILLT_s64,
        GIR_BuildMI, /*InsnID*/1, /*Opcode*/GIMT_Encode2(TargetOpcode::REG_SEQUENCE),
        GIR_AddTempRegister, /*InsnID*/1, /*TempRegID*/0, /*TempRegFlags*/GIMT_Encode2(RegState::Define),
        GIR_Copy, /*NewInsnID*/1, /*OldInsnID*/0, /*OpIdx*/3, // vindex
        GIR_AddImm8, /*InsnID*/1, /*SubRegIndex*/3,
        GIR_Copy, /*NewInsnID*/1, /*OldInsnID*/0, /*OpIdx*/4, // voffset
        GIR_AddImm8, /*InsnID*/1, /*SubRegIndex*/11,
        GIR_ConstrainOperandRC, /*InsnID*/1, /*Op*/0, GIMT_Encode2(AMDGPU::VReg_64RegClassID),
        GIR_ConstrainOperandRC, /*InsnID*/1, /*Op*/1, GIMT_Encode2(AMDGPU::VGPR_32RegClassID),
        GIR_ConstrainOperandRC, /*InsnID*/1, /*Op*/3, GIMT_Encode2(AMDGPU::VGPR_32RegClassID),
        GIR_BuildMI, /*InsnID*/0, /*Opcode*/GIMT_Encode2(AMDGPU::BUFFER_ATOMIC_SUB_X2_VBUFFER_BOTHEN),
        GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/1, // vdata_in
        GIR_AddSimpleTempRegister, /*InsnID*/0, /*TempRegID*/0,
        GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/2, // rsrc
        GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/0, // soffset
        GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/6, // offset
        GIR_CustomOperandRenderer, /*InsnID*/0, /*OldInsnID*/0, /*OpIdx*/7, /*OperandRenderer*/GIMT_Encode2(GICR_renderExtractCPol), // auxiliary
        GIR_MergeMemOperands, /*InsnID*/0, /*NumInsns*/1, /*MergeInsnID's*/0,
        GIR_ConstrainSelectedInstOperands, /*InsnID*/0,
        GIR_EraseFromParent, /*InsnID*/0,
        // GIR_Coverage, 4976,
        GIR_Done,
      // Label 6224: @455963
      GIM_Try, /*On fail goto*//*Label 6225*/ GIMT_Encode4(456076), // Rule ID 4964 //
        GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasUnrestrictedSOffset),
        GIM_CheckRegBankForClass, /*MI*/0, /*Op*/0, /*RC*/GIMT_Encode2(AMDGPU::AV_64RegClassID),
        // MIs[0] offset
        GIM_CheckIsImm, /*MI*/0, /*Op*/6,
        // MIs[0] auxiliary
        GIM_CheckIsImm, /*MI*/0, /*Op*/7,
        // MIs[0] Operand 8
        GIM_CheckIsImm, /*MI*/0, /*Op*/8,
        GIM_CheckComplexPattern, /*MI*/0, /*Op*/5, /*Renderer*/GIMT_Encode2(0), GIMT_Encode2(GICP_gi_buf_soffset),
        // (SIbuffer_atomic_sub:{ *:[i64] } i64:{ *:[i64] }:$vdata_in, v4i32:{ *:[v4i32] }:$rsrc, i32:{ *:[i32] }:$vindex, i32:{ *:[i32] }:$voffset, (BUFSOffset:{ *:[i32] } i32:{ *:[i32] }:$soffset), (timm:{ *:[i32] }):$offset, (timm:{ *:[i32] }):$auxiliary, (timm:{ *:[i1] }))  =>  (BUFFER_ATOMIC_SUB_X2_BOTHEN_RTN:{ *:[i64] } anonymous_15036:{ *:[i64] }:$vdata_in, (REG_SEQUENCE:{ *:[i64] } VReg_64:{ *:[i32] }, VGPR_32:{ *:[i32] }:$vindex, sub0:{ *:[i32] }, VGPR_32:{ *:[i32] }:$voffset, sub1:{ *:[i32] }), SReg_128:{ *:[v4i32] }:$rsrc, SCSrc_b32:{ *:[i32] }:$soffset, (timm:{ *:[i32] }):$offset, (extract_cpol_set_glc:{ *:[i32] } ?:{ *:[i32] }:$auxiliary))
        GIR_MakeTempReg, /*TempRegID*/0, /*TypeID*/GILLT_s64,
        GIR_BuildMI, /*InsnID*/1, /*Opcode*/GIMT_Encode2(TargetOpcode::REG_SEQUENCE),
        GIR_AddTempRegister, /*InsnID*/1, /*TempRegID*/0, /*TempRegFlags*/GIMT_Encode2(RegState::Define),
        GIR_Copy, /*NewInsnID*/1, /*OldInsnID*/0, /*OpIdx*/3, // vindex
        GIR_AddImm8, /*InsnID*/1, /*SubRegIndex*/3,
        GIR_Copy, /*NewInsnID*/1, /*OldInsnID*/0, /*OpIdx*/4, // voffset
        GIR_AddImm8, /*InsnID*/1, /*SubRegIndex*/11,
        GIR_ConstrainOperandRC, /*InsnID*/1, /*Op*/0, GIMT_Encode2(AMDGPU::VReg_64RegClassID),
        GIR_ConstrainOperandRC, /*InsnID*/1, /*Op*/1, GIMT_Encode2(AMDGPU::VGPR_32RegClassID),
        GIR_ConstrainOperandRC, /*InsnID*/1, /*Op*/3, GIMT_Encode2(AMDGPU::VGPR_32RegClassID),
        GIR_BuildMI, /*InsnID*/0, /*Opcode*/GIMT_Encode2(AMDGPU::BUFFER_ATOMIC_SUB_X2_BOTHEN_RTN),
        GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/0, // DstI[vdata]
        GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/1, // vdata_in
        GIR_AddSimpleTempRegister, /*InsnID*/0, /*TempRegID*/0,
        GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/2, // rsrc
        GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/0, // soffset
        GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/6, // offset
        GIR_CustomOperandRenderer, /*InsnID*/0, /*OldInsnID*/0, /*OpIdx*/7, /*OperandRenderer*/GIMT_Encode2(GICR_renderExtractCpolSetGLC), // auxiliary
        GIR_MergeMemOperands, /*InsnID*/0, /*NumInsns*/1, /*MergeInsnID's*/0,
        GIR_ConstrainSelectedInstOperands, /*InsnID*/0,
        GIR_EraseFromParent, /*InsnID*/0,
        // GIR_Coverage, 4964,
        GIR_Done,
      // Label 6225: @456076
      GIM_Try, /*On fail goto*//*Label 6226*/ GIMT_Encode4(456186), // Rule ID 4972 //
        GIM_CheckRegBankForClass, /*MI*/0, /*Op*/0, /*RC*/GIMT_Encode2(AMDGPU::AV_64RegClassID),
        // MIs[0] offset
        GIM_CheckIsImm, /*MI*/0, /*Op*/6,
        // MIs[0] auxiliary
        GIM_CheckIsImm, /*MI*/0, /*Op*/7,
        // MIs[0] Operand 8
        GIM_CheckIsImm, /*MI*/0, /*Op*/8,
        GIM_CheckComplexPattern, /*MI*/0, /*Op*/5, /*Renderer*/GIMT_Encode2(0), GIMT_Encode2(GICP_gi_buf_soffset),
        // (SIbuffer_atomic_sub:{ *:[i64] } i64:{ *:[i64] }:$vdata_in, v4i32:{ *:[v4i32] }:$rsrc, i32:{ *:[i32] }:$vindex, i32:{ *:[i32] }:$voffset, (BUFSOffset:{ *:[i32] } i32:{ *:[i32] }:$soffset), (timm:{ *:[i32] }):$offset, (timm:{ *:[i32] }):$auxiliary, (timm:{ *:[i1] }))  =>  (BUFFER_ATOMIC_SUB_X2_VBUFFER_BOTHEN_RTN:{ *:[i64] } anonymous_15036:{ *:[i64] }:$vdata_in, (REG_SEQUENCE:{ *:[i64] } VReg_64:{ *:[i32] }, VGPR_32:{ *:[i32] }:$vindex, sub0:{ *:[i32] }, VGPR_32:{ *:[i32] }:$voffset, sub1:{ *:[i32] }), SReg_128:{ *:[v4i32] }:$rsrc, SCSrc_b32:{ *:[i32] }:$soffset, (timm:{ *:[i32] }):$offset, (extract_cpol_set_glc:{ *:[i32] } ?:{ *:[i32] }:$auxiliary))
        GIR_MakeTempReg, /*TempRegID*/0, /*TypeID*/GILLT_s64,
        GIR_BuildMI, /*InsnID*/1, /*Opcode*/GIMT_Encode2(TargetOpcode::REG_SEQUENCE),
        GIR_AddTempRegister, /*InsnID*/1, /*TempRegID*/0, /*TempRegFlags*/GIMT_Encode2(RegState::Define),
        GIR_Copy, /*NewInsnID*/1, /*OldInsnID*/0, /*OpIdx*/3, // vindex
        GIR_AddImm8, /*InsnID*/1, /*SubRegIndex*/3,
        GIR_Copy, /*NewInsnID*/1, /*OldInsnID*/0, /*OpIdx*/4, // voffset
        GIR_AddImm8, /*InsnID*/1, /*SubRegIndex*/11,
        GIR_ConstrainOperandRC, /*InsnID*/1, /*Op*/0, GIMT_Encode2(AMDGPU::VReg_64RegClassID),
        GIR_ConstrainOperandRC, /*InsnID*/1, /*Op*/1, GIMT_Encode2(AMDGPU::VGPR_32RegClassID),
        GIR_ConstrainOperandRC, /*InsnID*/1, /*Op*/3, GIMT_Encode2(AMDGPU::VGPR_32RegClassID),
        GIR_BuildMI, /*InsnID*/0, /*Opcode*/GIMT_Encode2(AMDGPU::BUFFER_ATOMIC_SUB_X2_VBUFFER_BOTHEN_RTN),
        GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/0, // DstI[vdata]
        GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/1, // vdata_in
        GIR_AddSimpleTempRegister, /*InsnID*/0, /*TempRegID*/0,
        GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/2, // rsrc
        GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/0, // soffset
        GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/6, // offset
        GIR_CustomOperandRenderer, /*InsnID*/0, /*OldInsnID*/0, /*OpIdx*/7, /*OperandRenderer*/GIMT_Encode2(GICR_renderExtractCpolSetGLC), // auxiliary
        GIR_MergeMemOperands, /*InsnID*/0, /*NumInsns*/1, /*MergeInsnID's*/0,
        GIR_ConstrainSelectedInstOperands, /*InsnID*/0,
        GIR_EraseFromParent, /*InsnID*/0,
        // GIR_Coverage, 4972,
        GIR_Done,
      // Label 6226: @456186
      GIM_Reject,
    // Label 6210: @456187
    GIM_Reject,
    // Label 6192: @456188
    GIM_Reject,
    // Label 120: @456189
    GIM_SwitchType, /*MI*/0, /*Op*/0, /*[*/GIMT_Encode2(9), GIMT_Encode2(11), /*)*//*default:*//*Label 6229*/ GIMT_Encode4(460342),
    /*GILLT_s32*//*Label 6227*/ GIMT_Encode4(456208),
    /*GILLT_s64*//*Label 6228*/ GIMT_Encode4(458955),
    // Label 6227: @456208
    GIM_Try, /*On fail goto*//*Label 6230*/ GIMT_Encode4(458954),
      GIM_CheckType, /*MI*/0, /*Op*/1, /*Type*/GILLT_s32,
      GIM_CheckType, /*MI*/0, /*Op*/2, /*Type*/GILLT_v4s32,
      GIM_CheckType, /*MI*/0, /*Op*/3, /*Type*/GILLT_s32,
      GIM_CheckType, /*MI*/0, /*Op*/4, /*Type*/GILLT_s32,
      GIM_CheckType, /*MI*/0, /*Op*/5, /*Type*/GILLT_s32,
      GIM_Try, /*On fail goto*//*Label 6231*/ GIMT_Encode4(456311), // Rule ID 4717 //
        GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasUnrestrictedSOffset),
        GIM_CheckHasNoUse, /*MI*/0,
        GIM_CheckConstantInt8, /*MI*/0, /*Op*/3, 0,
        GIM_CheckConstantInt8, /*MI*/0, /*Op*/4, 0,
        // MIs[0] offset
        GIM_CheckIsImm, /*MI*/0, /*Op*/6,
        // MIs[0] auxiliary
        GIM_CheckIsImm, /*MI*/0, /*Op*/7,
        // MIs[0] Operand 8
        GIM_CheckLiteralInt, /*MI*/0, /*Op*/8, GIMT_Encode8(0),
        GIM_CheckComplexPattern, /*MI*/0, /*Op*/5, /*Renderer*/GIMT_Encode2(0), GIMT_Encode2(GICP_gi_buf_soffset),
        // (SIbuffer_atomic_swap:{ *:[i32] } i32:{ *:[i32] }:$vdata_in, v4i32:{ *:[v4i32] }:$rsrc, 0:{ *:[i32] }, 0:{ *:[i32] }, (BUFSOffset:{ *:[i32] } i32:{ *:[i32] }:$soffset), (timm:{ *:[i32] }):$offset, (timm:{ *:[i32] }):$auxiliary, 0:{ *:[i1] })<<P:Predicate_SIbuffer_atomic_swap_noret>>  =>  (BUFFER_ATOMIC_SWAP_OFFSET anonymous_15037:{ *:[i32] }:$vdata_in, SReg_128:{ *:[v4i32] }:$rsrc, SCSrc_b32:{ *:[i32] }:$soffset, (timm:{ *:[i32] }):$offset, (extract_cpol:{ *:[i32] } ?:{ *:[i32] }:$auxiliary))
        GIR_BuildMI, /*InsnID*/0, /*Opcode*/GIMT_Encode2(AMDGPU::BUFFER_ATOMIC_SWAP_OFFSET),
        GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/1, // vdata_in
        GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/2, // rsrc
        GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/0, // soffset
        GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/6, // offset
        GIR_CustomOperandRenderer, /*InsnID*/0, /*OldInsnID*/0, /*OpIdx*/7, /*OperandRenderer*/GIMT_Encode2(GICR_renderExtractCPol), // auxiliary
        GIR_MergeMemOperands, /*InsnID*/0, /*NumInsns*/1, /*MergeInsnID's*/0,
        GIR_ConstrainSelectedInstOperands, /*InsnID*/0,
        GIR_EraseFromParent, /*InsnID*/0,
        // GIR_Coverage, 4717,
        GIR_Done,
      // Label 6231: @456311
      GIM_Try, /*On fail goto*//*Label 6232*/ GIMT_Encode4(456386), // Rule ID 4725 //
        GIM_CheckHasNoUse, /*MI*/0,
        GIM_CheckConstantInt8, /*MI*/0, /*Op*/3, 0,
        GIM_CheckConstantInt8, /*MI*/0, /*Op*/4, 0,
        // MIs[0] offset
        GIM_CheckIsImm, /*MI*/0, /*Op*/6,
        // MIs[0] auxiliary
        GIM_CheckIsImm, /*MI*/0, /*Op*/7,
        // MIs[0] Operand 8
        GIM_CheckLiteralInt, /*MI*/0, /*Op*/8, GIMT_Encode8(0),
        GIM_CheckComplexPattern, /*MI*/0, /*Op*/5, /*Renderer*/GIMT_Encode2(0), GIMT_Encode2(GICP_gi_buf_soffset),
        // (SIbuffer_atomic_swap:{ *:[i32] } i32:{ *:[i32] }:$vdata_in, v4i32:{ *:[v4i32] }:$rsrc, 0:{ *:[i32] }, 0:{ *:[i32] }, (BUFSOffset:{ *:[i32] } i32:{ *:[i32] }:$soffset), (timm:{ *:[i32] }):$offset, (timm:{ *:[i32] }):$auxiliary, 0:{ *:[i1] })<<P:Predicate_SIbuffer_atomic_swap_noret>>  =>  (BUFFER_ATOMIC_SWAP_VBUFFER_OFFSET anonymous_15037:{ *:[i32] }:$vdata_in, SReg_128:{ *:[v4i32] }:$rsrc, SCSrc_b32:{ *:[i32] }:$soffset, (timm:{ *:[i32] }):$offset, (extract_cpol:{ *:[i32] } ?:{ *:[i32] }:$auxiliary))
        GIR_BuildMI, /*InsnID*/0, /*Opcode*/GIMT_Encode2(AMDGPU::BUFFER_ATOMIC_SWAP_VBUFFER_OFFSET),
        GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/1, // vdata_in
        GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/2, // rsrc
        GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/0, // soffset
        GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/6, // offset
        GIR_CustomOperandRenderer, /*InsnID*/0, /*OldInsnID*/0, /*OpIdx*/7, /*OperandRenderer*/GIMT_Encode2(GICR_renderExtractCPol), // auxiliary
        GIR_MergeMemOperands, /*InsnID*/0, /*NumInsns*/1, /*MergeInsnID's*/0,
        GIR_ConstrainSelectedInstOperands, /*InsnID*/0,
        GIR_EraseFromParent, /*InsnID*/0,
        // GIR_Coverage, 4725,
        GIR_Done,
      // Label 6232: @456386
      GIM_Try, /*On fail goto*//*Label 6233*/ GIMT_Encode4(456464), // Rule ID 4733 //
        GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasUnrestrictedSOffset),
        GIM_CheckHasNoUse, /*MI*/0,
        GIM_CheckConstantInt8, /*MI*/0, /*Op*/3, 0,
        GIM_CheckConstantInt8, /*MI*/0, /*Op*/4, 0,
        // MIs[0] offset
        GIM_CheckIsImm, /*MI*/0, /*Op*/6,
        // MIs[0] auxiliary
        GIM_CheckIsImm, /*MI*/0, /*Op*/7,
        // MIs[0] Operand 8
        GIM_CheckLiteralInt, /*MI*/0, /*Op*/8, GIMT_Encode8(0),
        GIM_CheckComplexPattern, /*MI*/0, /*Op*/5, /*Renderer*/GIMT_Encode2(0), GIMT_Encode2(GICP_gi_buf_soffset),
        // (SIbuffer_atomic_swap:{ *:[f32] } f32:{ *:[f32] }:$vdata_in, v4i32:{ *:[v4i32] }:$rsrc, 0:{ *:[i32] }, 0:{ *:[i32] }, (BUFSOffset:{ *:[i32] } i32:{ *:[i32] }:$soffset), (timm:{ *:[i32] }):$offset, (timm:{ *:[i32] }):$auxiliary, 0:{ *:[i1] })<<P:Predicate_SIbuffer_atomic_swap_noret>>  =>  (BUFFER_ATOMIC_SWAP_OFFSET anonymous_15037:{ *:[f32] }:$vdata_in, SReg_128:{ *:[v4i32] }:$rsrc, SCSrc_b32:{ *:[i32] }:$soffset, (timm:{ *:[i32] }):$offset, (extract_cpol:{ *:[i32] } ?:{ *:[i32] }:$auxiliary))
        GIR_BuildMI, /*InsnID*/0, /*Opcode*/GIMT_Encode2(AMDGPU::BUFFER_ATOMIC_SWAP_OFFSET),
        GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/1, // vdata_in
        GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/2, // rsrc
        GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/0, // soffset
        GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/6, // offset
        GIR_CustomOperandRenderer, /*InsnID*/0, /*OldInsnID*/0, /*OpIdx*/7, /*OperandRenderer*/GIMT_Encode2(GICR_renderExtractCPol), // auxiliary
        GIR_MergeMemOperands, /*InsnID*/0, /*NumInsns*/1, /*MergeInsnID's*/0,
        GIR_ConstrainSelectedInstOperands, /*InsnID*/0,
        GIR_EraseFromParent, /*InsnID*/0,
        // GIR_Coverage, 4733,
        GIR_Done,
      // Label 6233: @456464
      GIM_Try, /*On fail goto*//*Label 6234*/ GIMT_Encode4(456539), // Rule ID 4741 //
        GIM_CheckHasNoUse, /*MI*/0,
        GIM_CheckConstantInt8, /*MI*/0, /*Op*/3, 0,
        GIM_CheckConstantInt8, /*MI*/0, /*Op*/4, 0,
        // MIs[0] offset
        GIM_CheckIsImm, /*MI*/0, /*Op*/6,
        // MIs[0] auxiliary
        GIM_CheckIsImm, /*MI*/0, /*Op*/7,
        // MIs[0] Operand 8
        GIM_CheckLiteralInt, /*MI*/0, /*Op*/8, GIMT_Encode8(0),
        GIM_CheckComplexPattern, /*MI*/0, /*Op*/5, /*Renderer*/GIMT_Encode2(0), GIMT_Encode2(GICP_gi_buf_soffset),
        // (SIbuffer_atomic_swap:{ *:[f32] } f32:{ *:[f32] }:$vdata_in, v4i32:{ *:[v4i32] }:$rsrc, 0:{ *:[i32] }, 0:{ *:[i32] }, (BUFSOffset:{ *:[i32] } i32:{ *:[i32] }:$soffset), (timm:{ *:[i32] }):$offset, (timm:{ *:[i32] }):$auxiliary, 0:{ *:[i1] })<<P:Predicate_SIbuffer_atomic_swap_noret>>  =>  (BUFFER_ATOMIC_SWAP_VBUFFER_OFFSET anonymous_15037:{ *:[f32] }:$vdata_in, SReg_128:{ *:[v4i32] }:$rsrc, SCSrc_b32:{ *:[i32] }:$soffset, (timm:{ *:[i32] }):$offset, (extract_cpol:{ *:[i32] } ?:{ *:[i32] }:$auxiliary))
        GIR_BuildMI, /*InsnID*/0, /*Opcode*/GIMT_Encode2(AMDGPU::BUFFER_ATOMIC_SWAP_VBUFFER_OFFSET),
        GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/1, // vdata_in
        GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/2, // rsrc
        GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/0, // soffset
        GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/6, // offset
        GIR_CustomOperandRenderer, /*InsnID*/0, /*OldInsnID*/0, /*OpIdx*/7, /*OperandRenderer*/GIMT_Encode2(GICR_renderExtractCPol), // auxiliary
        GIR_MergeMemOperands, /*InsnID*/0, /*NumInsns*/1, /*MergeInsnID's*/0,
        GIR_ConstrainSelectedInstOperands, /*InsnID*/0,
        GIR_EraseFromParent, /*InsnID*/0,
        // GIR_Coverage, 4741,
        GIR_Done,
      // Label 6234: @456539
      GIM_Try, /*On fail goto*//*Label 6235*/ GIMT_Encode4(456624), // Rule ID 4713 //
        GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasUnrestrictedSOffset),
        GIM_CheckRegBankForClass, /*MI*/0, /*Op*/0, /*RC*/GIMT_Encode2(AMDGPU::AV_32RegClassID),
        GIM_CheckConstantInt8, /*MI*/0, /*Op*/3, 0,
        GIM_CheckConstantInt8, /*MI*/0, /*Op*/4, 0,
        // MIs[0] offset
        GIM_CheckIsImm, /*MI*/0, /*Op*/6,
        // MIs[0] auxiliary
        GIM_CheckIsImm, /*MI*/0, /*Op*/7,
        // MIs[0] Operand 8
        GIM_CheckLiteralInt, /*MI*/0, /*Op*/8, GIMT_Encode8(0),
        GIM_CheckComplexPattern, /*MI*/0, /*Op*/5, /*Renderer*/GIMT_Encode2(0), GIMT_Encode2(GICP_gi_buf_soffset),
        // (SIbuffer_atomic_swap:{ *:[i32] } i32:{ *:[i32] }:$vdata_in, v4i32:{ *:[v4i32] }:$rsrc, 0:{ *:[i32] }, 0:{ *:[i32] }, (BUFSOffset:{ *:[i32] } i32:{ *:[i32] }:$soffset), (timm:{ *:[i32] }):$offset, (timm:{ *:[i32] }):$auxiliary, 0:{ *:[i1] })  =>  (BUFFER_ATOMIC_SWAP_OFFSET_RTN:{ *:[i32] } anonymous_15037:{ *:[i32] }:$vdata_in, SReg_128:{ *:[v4i32] }:$rsrc, SCSrc_b32:{ *:[i32] }:$soffset, (timm:{ *:[i32] }):$offset, (extract_cpol_set_glc:{ *:[i32] } ?:{ *:[i32] }:$auxiliary))
        GIR_BuildMI, /*InsnID*/0, /*Opcode*/GIMT_Encode2(AMDGPU::BUFFER_ATOMIC_SWAP_OFFSET_RTN),
        GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/0, // DstI[vdata]
        GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/1, // vdata_in
        GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/2, // rsrc
        GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/0, // soffset
        GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/6, // offset
        GIR_CustomOperandRenderer, /*InsnID*/0, /*OldInsnID*/0, /*OpIdx*/7, /*OperandRenderer*/GIMT_Encode2(GICR_renderExtractCpolSetGLC), // auxiliary
        GIR_MergeMemOperands, /*InsnID*/0, /*NumInsns*/1, /*MergeInsnID's*/0,
        GIR_ConstrainSelectedInstOperands, /*InsnID*/0,
        GIR_EraseFromParent, /*InsnID*/0,
        // GIR_Coverage, 4713,
        GIR_Done,
      // Label 6235: @456624
      GIM_Try, /*On fail goto*//*Label 6236*/ GIMT_Encode4(456706), // Rule ID 4721 //
        GIM_CheckRegBankForClass, /*MI*/0, /*Op*/0, /*RC*/GIMT_Encode2(AMDGPU::AV_32RegClassID),
        GIM_CheckConstantInt8, /*MI*/0, /*Op*/3, 0,
        GIM_CheckConstantInt8, /*MI*/0, /*Op*/4, 0,
        // MIs[0] offset
        GIM_CheckIsImm, /*MI*/0, /*Op*/6,
        // MIs[0] auxiliary
        GIM_CheckIsImm, /*MI*/0, /*Op*/7,
        // MIs[0] Operand 8
        GIM_CheckLiteralInt, /*MI*/0, /*Op*/8, GIMT_Encode8(0),
        GIM_CheckComplexPattern, /*MI*/0, /*Op*/5, /*Renderer*/GIMT_Encode2(0), GIMT_Encode2(GICP_gi_buf_soffset),
        // (SIbuffer_atomic_swap:{ *:[i32] } i32:{ *:[i32] }:$vdata_in, v4i32:{ *:[v4i32] }:$rsrc, 0:{ *:[i32] }, 0:{ *:[i32] }, (BUFSOffset:{ *:[i32] } i32:{ *:[i32] }:$soffset), (timm:{ *:[i32] }):$offset, (timm:{ *:[i32] }):$auxiliary, 0:{ *:[i1] })  =>  (BUFFER_ATOMIC_SWAP_VBUFFER_OFFSET_RTN:{ *:[i32] } anonymous_15037:{ *:[i32] }:$vdata_in, SReg_128:{ *:[v4i32] }:$rsrc, SCSrc_b32:{ *:[i32] }:$soffset, (timm:{ *:[i32] }):$offset, (extract_cpol_set_glc:{ *:[i32] } ?:{ *:[i32] }:$auxiliary))
        GIR_BuildMI, /*InsnID*/0, /*Opcode*/GIMT_Encode2(AMDGPU::BUFFER_ATOMIC_SWAP_VBUFFER_OFFSET_RTN),
        GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/0, // DstI[vdata]
        GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/1, // vdata_in
        GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/2, // rsrc
        GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/0, // soffset
        GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/6, // offset
        GIR_CustomOperandRenderer, /*InsnID*/0, /*OldInsnID*/0, /*OpIdx*/7, /*OperandRenderer*/GIMT_Encode2(GICR_renderExtractCpolSetGLC), // auxiliary
        GIR_MergeMemOperands, /*InsnID*/0, /*NumInsns*/1, /*MergeInsnID's*/0,
        GIR_ConstrainSelectedInstOperands, /*InsnID*/0,
        GIR_EraseFromParent, /*InsnID*/0,
        // GIR_Coverage, 4721,
        GIR_Done,
      // Label 6236: @456706
      GIM_Try, /*On fail goto*//*Label 6237*/ GIMT_Encode4(456791), // Rule ID 4729 //
        GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasUnrestrictedSOffset),
        GIM_CheckRegBankForClass, /*MI*/0, /*Op*/0, /*RC*/GIMT_Encode2(AMDGPU::AV_32RegClassID),
        GIM_CheckConstantInt8, /*MI*/0, /*Op*/3, 0,
        GIM_CheckConstantInt8, /*MI*/0, /*Op*/4, 0,
        // MIs[0] offset
        GIM_CheckIsImm, /*MI*/0, /*Op*/6,
        // MIs[0] auxiliary
        GIM_CheckIsImm, /*MI*/0, /*Op*/7,
        // MIs[0] Operand 8
        GIM_CheckLiteralInt, /*MI*/0, /*Op*/8, GIMT_Encode8(0),
        GIM_CheckComplexPattern, /*MI*/0, /*Op*/5, /*Renderer*/GIMT_Encode2(0), GIMT_Encode2(GICP_gi_buf_soffset),
        // (SIbuffer_atomic_swap:{ *:[f32] } f32:{ *:[f32] }:$vdata_in, v4i32:{ *:[v4i32] }:$rsrc, 0:{ *:[i32] }, 0:{ *:[i32] }, (BUFSOffset:{ *:[i32] } i32:{ *:[i32] }:$soffset), (timm:{ *:[i32] }):$offset, (timm:{ *:[i32] }):$auxiliary, 0:{ *:[i1] })  =>  (BUFFER_ATOMIC_SWAP_OFFSET_RTN:{ *:[f32] } anonymous_15037:{ *:[f32] }:$vdata_in, SReg_128:{ *:[v4i32] }:$rsrc, SCSrc_b32:{ *:[i32] }:$soffset, (timm:{ *:[i32] }):$offset, (extract_cpol_set_glc:{ *:[i32] } ?:{ *:[i32] }:$auxiliary))
        GIR_BuildMI, /*InsnID*/0, /*Opcode*/GIMT_Encode2(AMDGPU::BUFFER_ATOMIC_SWAP_OFFSET_RTN),
        GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/0, // DstI[vdata]
        GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/1, // vdata_in
        GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/2, // rsrc
        GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/0, // soffset
        GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/6, // offset
        GIR_CustomOperandRenderer, /*InsnID*/0, /*OldInsnID*/0, /*OpIdx*/7, /*OperandRenderer*/GIMT_Encode2(GICR_renderExtractCpolSetGLC), // auxiliary
        GIR_MergeMemOperands, /*InsnID*/0, /*NumInsns*/1, /*MergeInsnID's*/0,
        GIR_ConstrainSelectedInstOperands, /*InsnID*/0,
        GIR_EraseFromParent, /*InsnID*/0,
        // GIR_Coverage, 4729,
        GIR_Done,
      // Label 6237: @456791
      GIM_Try, /*On fail goto*//*Label 6238*/ GIMT_Encode4(456873), // Rule ID 4737 //
        GIM_CheckRegBankForClass, /*MI*/0, /*Op*/0, /*RC*/GIMT_Encode2(AMDGPU::AV_32RegClassID),
        GIM_CheckConstantInt8, /*MI*/0, /*Op*/3, 0,
        GIM_CheckConstantInt8, /*MI*/0, /*Op*/4, 0,
        // MIs[0] offset
        GIM_CheckIsImm, /*MI*/0, /*Op*/6,
        // MIs[0] auxiliary
        GIM_CheckIsImm, /*MI*/0, /*Op*/7,
        // MIs[0] Operand 8
        GIM_CheckLiteralInt, /*MI*/0, /*Op*/8, GIMT_Encode8(0),
        GIM_CheckComplexPattern, /*MI*/0, /*Op*/5, /*Renderer*/GIMT_Encode2(0), GIMT_Encode2(GICP_gi_buf_soffset),
        // (SIbuffer_atomic_swap:{ *:[f32] } f32:{ *:[f32] }:$vdata_in, v4i32:{ *:[v4i32] }:$rsrc, 0:{ *:[i32] }, 0:{ *:[i32] }, (BUFSOffset:{ *:[i32] } i32:{ *:[i32] }:$soffset), (timm:{ *:[i32] }):$offset, (timm:{ *:[i32] }):$auxiliary, 0:{ *:[i1] })  =>  (BUFFER_ATOMIC_SWAP_VBUFFER_OFFSET_RTN:{ *:[f32] } anonymous_15037:{ *:[f32] }:$vdata_in, SReg_128:{ *:[v4i32] }:$rsrc, SCSrc_b32:{ *:[i32] }:$soffset, (timm:{ *:[i32] }):$offset, (extract_cpol_set_glc:{ *:[i32] } ?:{ *:[i32] }:$auxiliary))
        GIR_BuildMI, /*InsnID*/0, /*Opcode*/GIMT_Encode2(AMDGPU::BUFFER_ATOMIC_SWAP_VBUFFER_OFFSET_RTN),
        GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/0, // DstI[vdata]
        GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/1, // vdata_in
        GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/2, // rsrc
        GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/0, // soffset
        GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/6, // offset
        GIR_CustomOperandRenderer, /*InsnID*/0, /*OldInsnID*/0, /*OpIdx*/7, /*OperandRenderer*/GIMT_Encode2(GICR_renderExtractCpolSetGLC), // auxiliary
        GIR_MergeMemOperands, /*InsnID*/0, /*NumInsns*/1, /*MergeInsnID's*/0,
        GIR_ConstrainSelectedInstOperands, /*InsnID*/0,
        GIR_EraseFromParent, /*InsnID*/0,
        // GIR_Coverage, 4737,
        GIR_Done,
      // Label 6238: @456873
      GIM_Try, /*On fail goto*//*Label 6239*/ GIMT_Encode4(456951), // Rule ID 4719 //
        GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasUnrestrictedSOffset),
        GIM_CheckHasNoUse, /*MI*/0,
        GIM_CheckConstantInt8, /*MI*/0, /*Op*/3, 0,
        // MIs[0] offset
        GIM_CheckIsImm, /*MI*/0, /*Op*/6,
        // MIs[0] auxiliary
        GIM_CheckIsImm, /*MI*/0, /*Op*/7,
        // MIs[0] Operand 8
        GIM_CheckLiteralInt, /*MI*/0, /*Op*/8, GIMT_Encode8(0),
        GIM_CheckComplexPattern, /*MI*/0, /*Op*/5, /*Renderer*/GIMT_Encode2(0), GIMT_Encode2(GICP_gi_buf_soffset),
        // (SIbuffer_atomic_swap:{ *:[i32] } i32:{ *:[i32] }:$vdata_in, v4i32:{ *:[v4i32] }:$rsrc, 0:{ *:[i32] }, i32:{ *:[i32] }:$voffset, (BUFSOffset:{ *:[i32] } i32:{ *:[i32] }:$soffset), (timm:{ *:[i32] }):$offset, (timm:{ *:[i32] }):$auxiliary, 0:{ *:[i1] })<<P:Predicate_SIbuffer_atomic_swap_noret>>  =>  (BUFFER_ATOMIC_SWAP_OFFEN anonymous_15037:{ *:[i32] }:$vdata_in, VGPR_32:{ *:[i32] }:$voffset, SReg_128:{ *:[v4i32] }:$rsrc, SCSrc_b32:{ *:[i32] }:$soffset, (timm:{ *:[i32] }):$offset, (extract_cpol:{ *:[i32] } ?:{ *:[i32] }:$auxiliary))
        GIR_BuildMI, /*InsnID*/0, /*Opcode*/GIMT_Encode2(AMDGPU::BUFFER_ATOMIC_SWAP_OFFEN),
        GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/1, // vdata_in
        GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/4, // voffset
        GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/2, // rsrc
        GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/0, // soffset
        GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/6, // offset
        GIR_CustomOperandRenderer, /*InsnID*/0, /*OldInsnID*/0, /*OpIdx*/7, /*OperandRenderer*/GIMT_Encode2(GICR_renderExtractCPol), // auxiliary
        GIR_MergeMemOperands, /*InsnID*/0, /*NumInsns*/1, /*MergeInsnID's*/0,
        GIR_ConstrainSelectedInstOperands, /*InsnID*/0,
        GIR_EraseFromParent, /*InsnID*/0,
        // GIR_Coverage, 4719,
        GIR_Done,
      // Label 6239: @456951
      GIM_Try, /*On fail goto*//*Label 6240*/ GIMT_Encode4(457026), // Rule ID 4727 //
        GIM_CheckHasNoUse, /*MI*/0,
        GIM_CheckConstantInt8, /*MI*/0, /*Op*/3, 0,
        // MIs[0] offset
        GIM_CheckIsImm, /*MI*/0, /*Op*/6,
        // MIs[0] auxiliary
        GIM_CheckIsImm, /*MI*/0, /*Op*/7,
        // MIs[0] Operand 8
        GIM_CheckLiteralInt, /*MI*/0, /*Op*/8, GIMT_Encode8(0),
        GIM_CheckComplexPattern, /*MI*/0, /*Op*/5, /*Renderer*/GIMT_Encode2(0), GIMT_Encode2(GICP_gi_buf_soffset),
        // (SIbuffer_atomic_swap:{ *:[i32] } i32:{ *:[i32] }:$vdata_in, v4i32:{ *:[v4i32] }:$rsrc, 0:{ *:[i32] }, i32:{ *:[i32] }:$voffset, (BUFSOffset:{ *:[i32] } i32:{ *:[i32] }:$soffset), (timm:{ *:[i32] }):$offset, (timm:{ *:[i32] }):$auxiliary, 0:{ *:[i1] })<<P:Predicate_SIbuffer_atomic_swap_noret>>  =>  (BUFFER_ATOMIC_SWAP_VBUFFER_OFFEN anonymous_15037:{ *:[i32] }:$vdata_in, VGPR_32:{ *:[i32] }:$voffset, SReg_128:{ *:[v4i32] }:$rsrc, SCSrc_b32:{ *:[i32] }:$soffset, (timm:{ *:[i32] }):$offset, (extract_cpol:{ *:[i32] } ?:{ *:[i32] }:$auxiliary))
        GIR_BuildMI, /*InsnID*/0, /*Opcode*/GIMT_Encode2(AMDGPU::BUFFER_ATOMIC_SWAP_VBUFFER_OFFEN),
        GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/1, // vdata_in
        GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/4, // voffset
        GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/2, // rsrc
        GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/0, // soffset
        GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/6, // offset
        GIR_CustomOperandRenderer, /*InsnID*/0, /*OldInsnID*/0, /*OpIdx*/7, /*OperandRenderer*/GIMT_Encode2(GICR_renderExtractCPol), // auxiliary
        GIR_MergeMemOperands, /*InsnID*/0, /*NumInsns*/1, /*MergeInsnID's*/0,
        GIR_ConstrainSelectedInstOperands, /*InsnID*/0,
        GIR_EraseFromParent, /*InsnID*/0,
        // GIR_Coverage, 4727,
        GIR_Done,
      // Label 6240: @457026
      GIM_Try, /*On fail goto*//*Label 6241*/ GIMT_Encode4(457104), // Rule ID 4735 //
        GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasUnrestrictedSOffset),
        GIM_CheckHasNoUse, /*MI*/0,
        GIM_CheckConstantInt8, /*MI*/0, /*Op*/3, 0,
        // MIs[0] offset
        GIM_CheckIsImm, /*MI*/0, /*Op*/6,
        // MIs[0] auxiliary
        GIM_CheckIsImm, /*MI*/0, /*Op*/7,
        // MIs[0] Operand 8
        GIM_CheckLiteralInt, /*MI*/0, /*Op*/8, GIMT_Encode8(0),
        GIM_CheckComplexPattern, /*MI*/0, /*Op*/5, /*Renderer*/GIMT_Encode2(0), GIMT_Encode2(GICP_gi_buf_soffset),
        // (SIbuffer_atomic_swap:{ *:[f32] } f32:{ *:[f32] }:$vdata_in, v4i32:{ *:[v4i32] }:$rsrc, 0:{ *:[i32] }, i32:{ *:[i32] }:$voffset, (BUFSOffset:{ *:[i32] } i32:{ *:[i32] }:$soffset), (timm:{ *:[i32] }):$offset, (timm:{ *:[i32] }):$auxiliary, 0:{ *:[i1] })<<P:Predicate_SIbuffer_atomic_swap_noret>>  =>  (BUFFER_ATOMIC_SWAP_OFFEN anonymous_15037:{ *:[f32] }:$vdata_in, VGPR_32:{ *:[i32] }:$voffset, SReg_128:{ *:[v4i32] }:$rsrc, SCSrc_b32:{ *:[i32] }:$soffset, (timm:{ *:[i32] }):$offset, (extract_cpol:{ *:[i32] } ?:{ *:[i32] }:$auxiliary))
        GIR_BuildMI, /*InsnID*/0, /*Opcode*/GIMT_Encode2(AMDGPU::BUFFER_ATOMIC_SWAP_OFFEN),
        GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/1, // vdata_in
        GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/4, // voffset
        GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/2, // rsrc
        GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/0, // soffset
        GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/6, // offset
        GIR_CustomOperandRenderer, /*InsnID*/0, /*OldInsnID*/0, /*OpIdx*/7, /*OperandRenderer*/GIMT_Encode2(GICR_renderExtractCPol), // auxiliary
        GIR_MergeMemOperands, /*InsnID*/0, /*NumInsns*/1, /*MergeInsnID's*/0,
        GIR_ConstrainSelectedInstOperands, /*InsnID*/0,
        GIR_EraseFromParent, /*InsnID*/0,
        // GIR_Coverage, 4735,
        GIR_Done,
      // Label 6241: @457104
      GIM_Try, /*On fail goto*//*Label 6242*/ GIMT_Encode4(457179), // Rule ID 4743 //
        GIM_CheckHasNoUse, /*MI*/0,
        GIM_CheckConstantInt8, /*MI*/0, /*Op*/3, 0,
        // MIs[0] offset
        GIM_CheckIsImm, /*MI*/0, /*Op*/6,
        // MIs[0] auxiliary
        GIM_CheckIsImm, /*MI*/0, /*Op*/7,
        // MIs[0] Operand 8
        GIM_CheckLiteralInt, /*MI*/0, /*Op*/8, GIMT_Encode8(0),
        GIM_CheckComplexPattern, /*MI*/0, /*Op*/5, /*Renderer*/GIMT_Encode2(0), GIMT_Encode2(GICP_gi_buf_soffset),
        // (SIbuffer_atomic_swap:{ *:[f32] } f32:{ *:[f32] }:$vdata_in, v4i32:{ *:[v4i32] }:$rsrc, 0:{ *:[i32] }, i32:{ *:[i32] }:$voffset, (BUFSOffset:{ *:[i32] } i32:{ *:[i32] }:$soffset), (timm:{ *:[i32] }):$offset, (timm:{ *:[i32] }):$auxiliary, 0:{ *:[i1] })<<P:Predicate_SIbuffer_atomic_swap_noret>>  =>  (BUFFER_ATOMIC_SWAP_VBUFFER_OFFEN anonymous_15037:{ *:[f32] }:$vdata_in, VGPR_32:{ *:[i32] }:$voffset, SReg_128:{ *:[v4i32] }:$rsrc, SCSrc_b32:{ *:[i32] }:$soffset, (timm:{ *:[i32] }):$offset, (extract_cpol:{ *:[i32] } ?:{ *:[i32] }:$auxiliary))
        GIR_BuildMI, /*InsnID*/0, /*Opcode*/GIMT_Encode2(AMDGPU::BUFFER_ATOMIC_SWAP_VBUFFER_OFFEN),
        GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/1, // vdata_in
        GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/4, // voffset
        GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/2, // rsrc
        GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/0, // soffset
        GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/6, // offset
        GIR_CustomOperandRenderer, /*InsnID*/0, /*OldInsnID*/0, /*OpIdx*/7, /*OperandRenderer*/GIMT_Encode2(GICR_renderExtractCPol), // auxiliary
        GIR_MergeMemOperands, /*InsnID*/0, /*NumInsns*/1, /*MergeInsnID's*/0,
        GIR_ConstrainSelectedInstOperands, /*InsnID*/0,
        GIR_EraseFromParent, /*InsnID*/0,
        // GIR_Coverage, 4743,
        GIR_Done,
      // Label 6242: @457179
      GIM_Try, /*On fail goto*//*Label 6243*/ GIMT_Encode4(457264), // Rule ID 4715 //
        GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasUnrestrictedSOffset),
        GIM_CheckRegBankForClass, /*MI*/0, /*Op*/0, /*RC*/GIMT_Encode2(AMDGPU::AV_32RegClassID),
        GIM_CheckConstantInt8, /*MI*/0, /*Op*/3, 0,
        // MIs[0] offset
        GIM_CheckIsImm, /*MI*/0, /*Op*/6,
        // MIs[0] auxiliary
        GIM_CheckIsImm, /*MI*/0, /*Op*/7,
        // MIs[0] Operand 8
        GIM_CheckLiteralInt, /*MI*/0, /*Op*/8, GIMT_Encode8(0),
        GIM_CheckComplexPattern, /*MI*/0, /*Op*/5, /*Renderer*/GIMT_Encode2(0), GIMT_Encode2(GICP_gi_buf_soffset),
        // (SIbuffer_atomic_swap:{ *:[i32] } i32:{ *:[i32] }:$vdata_in, v4i32:{ *:[v4i32] }:$rsrc, 0:{ *:[i32] }, i32:{ *:[i32] }:$voffset, (BUFSOffset:{ *:[i32] } i32:{ *:[i32] }:$soffset), (timm:{ *:[i32] }):$offset, (timm:{ *:[i32] }):$auxiliary, 0:{ *:[i1] })  =>  (BUFFER_ATOMIC_SWAP_OFFEN_RTN:{ *:[i32] } anonymous_15037:{ *:[i32] }:$vdata_in, VGPR_32:{ *:[i32] }:$voffset, SReg_128:{ *:[v4i32] }:$rsrc, SCSrc_b32:{ *:[i32] }:$soffset, (timm:{ *:[i32] }):$offset, (extract_cpol_set_glc:{ *:[i32] } ?:{ *:[i32] }:$auxiliary))
        GIR_BuildMI, /*InsnID*/0, /*Opcode*/GIMT_Encode2(AMDGPU::BUFFER_ATOMIC_SWAP_OFFEN_RTN),
        GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/0, // DstI[vdata]
        GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/1, // vdata_in
        GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/4, // voffset
        GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/2, // rsrc
        GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/0, // soffset
        GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/6, // offset
        GIR_CustomOperandRenderer, /*InsnID*/0, /*OldInsnID*/0, /*OpIdx*/7, /*OperandRenderer*/GIMT_Encode2(GICR_renderExtractCpolSetGLC), // auxiliary
        GIR_MergeMemOperands, /*InsnID*/0, /*NumInsns*/1, /*MergeInsnID's*/0,
        GIR_ConstrainSelectedInstOperands, /*InsnID*/0,
        GIR_EraseFromParent, /*InsnID*/0,
        // GIR_Coverage, 4715,
        GIR_Done,
      // Label 6243: @457264
      GIM_Try, /*On fail goto*//*Label 6244*/ GIMT_Encode4(457346), // Rule ID 4723 //
        GIM_CheckRegBankForClass, /*MI*/0, /*Op*/0, /*RC*/GIMT_Encode2(AMDGPU::AV_32RegClassID),
        GIM_CheckConstantInt8, /*MI*/0, /*Op*/3, 0,
        // MIs[0] offset
        GIM_CheckIsImm, /*MI*/0, /*Op*/6,
        // MIs[0] auxiliary
        GIM_CheckIsImm, /*MI*/0, /*Op*/7,
        // MIs[0] Operand 8
        GIM_CheckLiteralInt, /*MI*/0, /*Op*/8, GIMT_Encode8(0),
        GIM_CheckComplexPattern, /*MI*/0, /*Op*/5, /*Renderer*/GIMT_Encode2(0), GIMT_Encode2(GICP_gi_buf_soffset),
        // (SIbuffer_atomic_swap:{ *:[i32] } i32:{ *:[i32] }:$vdata_in, v4i32:{ *:[v4i32] }:$rsrc, 0:{ *:[i32] }, i32:{ *:[i32] }:$voffset, (BUFSOffset:{ *:[i32] } i32:{ *:[i32] }:$soffset), (timm:{ *:[i32] }):$offset, (timm:{ *:[i32] }):$auxiliary, 0:{ *:[i1] })  =>  (BUFFER_ATOMIC_SWAP_VBUFFER_OFFEN_RTN:{ *:[i32] } anonymous_15037:{ *:[i32] }:$vdata_in, VGPR_32:{ *:[i32] }:$voffset, SReg_128:{ *:[v4i32] }:$rsrc, SCSrc_b32:{ *:[i32] }:$soffset, (timm:{ *:[i32] }):$offset, (extract_cpol_set_glc:{ *:[i32] } ?:{ *:[i32] }:$auxiliary))
        GIR_BuildMI, /*InsnID*/0, /*Opcode*/GIMT_Encode2(AMDGPU::BUFFER_ATOMIC_SWAP_VBUFFER_OFFEN_RTN),
        GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/0, // DstI[vdata]
        GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/1, // vdata_in
        GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/4, // voffset
        GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/2, // rsrc
        GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/0, // soffset
        GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/6, // offset
        GIR_CustomOperandRenderer, /*InsnID*/0, /*OldInsnID*/0, /*OpIdx*/7, /*OperandRenderer*/GIMT_Encode2(GICR_renderExtractCpolSetGLC), // auxiliary
        GIR_MergeMemOperands, /*InsnID*/0, /*NumInsns*/1, /*MergeInsnID's*/0,
        GIR_ConstrainSelectedInstOperands, /*InsnID*/0,
        GIR_EraseFromParent, /*InsnID*/0,
        // GIR_Coverage, 4723,
        GIR_Done,
      // Label 6244: @457346
      GIM_Try, /*On fail goto*//*Label 6245*/ GIMT_Encode4(457431), // Rule ID 4731 //
        GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasUnrestrictedSOffset),
        GIM_CheckRegBankForClass, /*MI*/0, /*Op*/0, /*RC*/GIMT_Encode2(AMDGPU::AV_32RegClassID),
        GIM_CheckConstantInt8, /*MI*/0, /*Op*/3, 0,
        // MIs[0] offset
        GIM_CheckIsImm, /*MI*/0, /*Op*/6,
        // MIs[0] auxiliary
        GIM_CheckIsImm, /*MI*/0, /*Op*/7,
        // MIs[0] Operand 8
        GIM_CheckLiteralInt, /*MI*/0, /*Op*/8, GIMT_Encode8(0),
        GIM_CheckComplexPattern, /*MI*/0, /*Op*/5, /*Renderer*/GIMT_Encode2(0), GIMT_Encode2(GICP_gi_buf_soffset),
        // (SIbuffer_atomic_swap:{ *:[f32] } f32:{ *:[f32] }:$vdata_in, v4i32:{ *:[v4i32] }:$rsrc, 0:{ *:[i32] }, i32:{ *:[i32] }:$voffset, (BUFSOffset:{ *:[i32] } i32:{ *:[i32] }:$soffset), (timm:{ *:[i32] }):$offset, (timm:{ *:[i32] }):$auxiliary, 0:{ *:[i1] })  =>  (BUFFER_ATOMIC_SWAP_OFFEN_RTN:{ *:[f32] } anonymous_15037:{ *:[f32] }:$vdata_in, VGPR_32:{ *:[i32] }:$voffset, SReg_128:{ *:[v4i32] }:$rsrc, SCSrc_b32:{ *:[i32] }:$soffset, (timm:{ *:[i32] }):$offset, (extract_cpol_set_glc:{ *:[i32] } ?:{ *:[i32] }:$auxiliary))
        GIR_BuildMI, /*InsnID*/0, /*Opcode*/GIMT_Encode2(AMDGPU::BUFFER_ATOMIC_SWAP_OFFEN_RTN),
        GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/0, // DstI[vdata]
        GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/1, // vdata_in
        GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/4, // voffset
        GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/2, // rsrc
        GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/0, // soffset
        GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/6, // offset
        GIR_CustomOperandRenderer, /*InsnID*/0, /*OldInsnID*/0, /*OpIdx*/7, /*OperandRenderer*/GIMT_Encode2(GICR_renderExtractCpolSetGLC), // auxiliary
        GIR_MergeMemOperands, /*InsnID*/0, /*NumInsns*/1, /*MergeInsnID's*/0,
        GIR_ConstrainSelectedInstOperands, /*InsnID*/0,
        GIR_EraseFromParent, /*InsnID*/0,
        // GIR_Coverage, 4731,
        GIR_Done,
      // Label 6245: @457431
      GIM_Try, /*On fail goto*//*Label 6246*/ GIMT_Encode4(457513), // Rule ID 4739 //
        GIM_CheckRegBankForClass, /*MI*/0, /*Op*/0, /*RC*/GIMT_Encode2(AMDGPU::AV_32RegClassID),
        GIM_CheckConstantInt8, /*MI*/0, /*Op*/3, 0,
        // MIs[0] offset
        GIM_CheckIsImm, /*MI*/0, /*Op*/6,
        // MIs[0] auxiliary
        GIM_CheckIsImm, /*MI*/0, /*Op*/7,
        // MIs[0] Operand 8
        GIM_CheckLiteralInt, /*MI*/0, /*Op*/8, GIMT_Encode8(0),
        GIM_CheckComplexPattern, /*MI*/0, /*Op*/5, /*Renderer*/GIMT_Encode2(0), GIMT_Encode2(GICP_gi_buf_soffset),
        // (SIbuffer_atomic_swap:{ *:[f32] } f32:{ *:[f32] }:$vdata_in, v4i32:{ *:[v4i32] }:$rsrc, 0:{ *:[i32] }, i32:{ *:[i32] }:$voffset, (BUFSOffset:{ *:[i32] } i32:{ *:[i32] }:$soffset), (timm:{ *:[i32] }):$offset, (timm:{ *:[i32] }):$auxiliary, 0:{ *:[i1] })  =>  (BUFFER_ATOMIC_SWAP_VBUFFER_OFFEN_RTN:{ *:[f32] } anonymous_15037:{ *:[f32] }:$vdata_in, VGPR_32:{ *:[i32] }:$voffset, SReg_128:{ *:[v4i32] }:$rsrc, SCSrc_b32:{ *:[i32] }:$soffset, (timm:{ *:[i32] }):$offset, (extract_cpol_set_glc:{ *:[i32] } ?:{ *:[i32] }:$auxiliary))
        GIR_BuildMI, /*InsnID*/0, /*Opcode*/GIMT_Encode2(AMDGPU::BUFFER_ATOMIC_SWAP_VBUFFER_OFFEN_RTN),
        GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/0, // DstI[vdata]
        GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/1, // vdata_in
        GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/4, // voffset
        GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/2, // rsrc
        GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/0, // soffset
        GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/6, // offset
        GIR_CustomOperandRenderer, /*InsnID*/0, /*OldInsnID*/0, /*OpIdx*/7, /*OperandRenderer*/GIMT_Encode2(GICR_renderExtractCpolSetGLC), // auxiliary
        GIR_MergeMemOperands, /*InsnID*/0, /*NumInsns*/1, /*MergeInsnID's*/0,
        GIR_ConstrainSelectedInstOperands, /*InsnID*/0,
        GIR_EraseFromParent, /*InsnID*/0,
        // GIR_Coverage, 4739,
        GIR_Done,
      // Label 6246: @457513
      GIM_Try, /*On fail goto*//*Label 6247*/ GIMT_Encode4(457583), // Rule ID 4718 //
        GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasUnrestrictedSOffset),
        GIM_CheckHasNoUse, /*MI*/0,
        GIM_CheckConstantInt8, /*MI*/0, /*Op*/4, 0,
        // MIs[0] offset
        GIM_CheckIsImm, /*MI*/0, /*Op*/6,
        // MIs[0] auxiliary
        GIM_CheckIsImm, /*MI*/0, /*Op*/7,
        // MIs[0] Operand 8
        GIM_CheckIsImm, /*MI*/0, /*Op*/8,
        GIM_CheckComplexPattern, /*MI*/0, /*Op*/5, /*Renderer*/GIMT_Encode2(0), GIMT_Encode2(GICP_gi_buf_soffset),
        // (SIbuffer_atomic_swap:{ *:[i32] } i32:{ *:[i32] }:$vdata_in, v4i32:{ *:[v4i32] }:$rsrc, i32:{ *:[i32] }:$vindex, 0:{ *:[i32] }, (BUFSOffset:{ *:[i32] } i32:{ *:[i32] }:$soffset), (timm:{ *:[i32] }):$offset, (timm:{ *:[i32] }):$auxiliary, (timm:{ *:[i1] }))<<P:Predicate_SIbuffer_atomic_swap_noret>>  =>  (BUFFER_ATOMIC_SWAP_IDXEN anonymous_15037:{ *:[i32] }:$vdata_in, VGPR_32:{ *:[i32] }:$vindex, SReg_128:{ *:[v4i32] }:$rsrc, SCSrc_b32:{ *:[i32] }:$soffset, (timm:{ *:[i32] }):$offset, (extract_cpol:{ *:[i32] } ?:{ *:[i32] }:$auxiliary))
        GIR_BuildMI, /*InsnID*/0, /*Opcode*/GIMT_Encode2(AMDGPU::BUFFER_ATOMIC_SWAP_IDXEN),
        GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/1, // vdata_in
        GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/3, // vindex
        GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/2, // rsrc
        GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/0, // soffset
        GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/6, // offset
        GIR_CustomOperandRenderer, /*InsnID*/0, /*OldInsnID*/0, /*OpIdx*/7, /*OperandRenderer*/GIMT_Encode2(GICR_renderExtractCPol), // auxiliary
        GIR_MergeMemOperands, /*InsnID*/0, /*NumInsns*/1, /*MergeInsnID's*/0,
        GIR_ConstrainSelectedInstOperands, /*InsnID*/0,
        GIR_EraseFromParent, /*InsnID*/0,
        // GIR_Coverage, 4718,
        GIR_Done,
      // Label 6247: @457583
      GIM_Try, /*On fail goto*//*Label 6248*/ GIMT_Encode4(457650), // Rule ID 4726 //
        GIM_CheckHasNoUse, /*MI*/0,
        GIM_CheckConstantInt8, /*MI*/0, /*Op*/4, 0,
        // MIs[0] offset
        GIM_CheckIsImm, /*MI*/0, /*Op*/6,
        // MIs[0] auxiliary
        GIM_CheckIsImm, /*MI*/0, /*Op*/7,
        // MIs[0] Operand 8
        GIM_CheckIsImm, /*MI*/0, /*Op*/8,
        GIM_CheckComplexPattern, /*MI*/0, /*Op*/5, /*Renderer*/GIMT_Encode2(0), GIMT_Encode2(GICP_gi_buf_soffset),
        // (SIbuffer_atomic_swap:{ *:[i32] } i32:{ *:[i32] }:$vdata_in, v4i32:{ *:[v4i32] }:$rsrc, i32:{ *:[i32] }:$vindex, 0:{ *:[i32] }, (BUFSOffset:{ *:[i32] } i32:{ *:[i32] }:$soffset), (timm:{ *:[i32] }):$offset, (timm:{ *:[i32] }):$auxiliary, (timm:{ *:[i1] }))<<P:Predicate_SIbuffer_atomic_swap_noret>>  =>  (BUFFER_ATOMIC_SWAP_VBUFFER_IDXEN anonymous_15037:{ *:[i32] }:$vdata_in, VGPR_32:{ *:[i32] }:$vindex, SReg_128:{ *:[v4i32] }:$rsrc, SCSrc_b32:{ *:[i32] }:$soffset, (timm:{ *:[i32] }):$offset, (extract_cpol:{ *:[i32] } ?:{ *:[i32] }:$auxiliary))
        GIR_BuildMI, /*InsnID*/0, /*Opcode*/GIMT_Encode2(AMDGPU::BUFFER_ATOMIC_SWAP_VBUFFER_IDXEN),
        GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/1, // vdata_in
        GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/3, // vindex
        GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/2, // rsrc
        GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/0, // soffset
        GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/6, // offset
        GIR_CustomOperandRenderer, /*InsnID*/0, /*OldInsnID*/0, /*OpIdx*/7, /*OperandRenderer*/GIMT_Encode2(GICR_renderExtractCPol), // auxiliary
        GIR_MergeMemOperands, /*InsnID*/0, /*NumInsns*/1, /*MergeInsnID's*/0,
        GIR_ConstrainSelectedInstOperands, /*InsnID*/0,
        GIR_EraseFromParent, /*InsnID*/0,
        // GIR_Coverage, 4726,
        GIR_Done,
      // Label 6248: @457650
      GIM_Try, /*On fail goto*//*Label 6249*/ GIMT_Encode4(457720), // Rule ID 4734 //
        GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasUnrestrictedSOffset),
        GIM_CheckHasNoUse, /*MI*/0,
        GIM_CheckConstantInt8, /*MI*/0, /*Op*/4, 0,
        // MIs[0] offset
        GIM_CheckIsImm, /*MI*/0, /*Op*/6,
        // MIs[0] auxiliary
        GIM_CheckIsImm, /*MI*/0, /*Op*/7,
        // MIs[0] Operand 8
        GIM_CheckIsImm, /*MI*/0, /*Op*/8,
        GIM_CheckComplexPattern, /*MI*/0, /*Op*/5, /*Renderer*/GIMT_Encode2(0), GIMT_Encode2(GICP_gi_buf_soffset),
        // (SIbuffer_atomic_swap:{ *:[f32] } f32:{ *:[f32] }:$vdata_in, v4i32:{ *:[v4i32] }:$rsrc, i32:{ *:[i32] }:$vindex, 0:{ *:[i32] }, (BUFSOffset:{ *:[i32] } i32:{ *:[i32] }:$soffset), (timm:{ *:[i32] }):$offset, (timm:{ *:[i32] }):$auxiliary, (timm:{ *:[i1] }))<<P:Predicate_SIbuffer_atomic_swap_noret>>  =>  (BUFFER_ATOMIC_SWAP_IDXEN anonymous_15037:{ *:[f32] }:$vdata_in, VGPR_32:{ *:[i32] }:$vindex, SReg_128:{ *:[v4i32] }:$rsrc, SCSrc_b32:{ *:[i32] }:$soffset, (timm:{ *:[i32] }):$offset, (extract_cpol:{ *:[i32] } ?:{ *:[i32] }:$auxiliary))
        GIR_BuildMI, /*InsnID*/0, /*Opcode*/GIMT_Encode2(AMDGPU::BUFFER_ATOMIC_SWAP_IDXEN),
        GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/1, // vdata_in
        GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/3, // vindex
        GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/2, // rsrc
        GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/0, // soffset
        GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/6, // offset
        GIR_CustomOperandRenderer, /*InsnID*/0, /*OldInsnID*/0, /*OpIdx*/7, /*OperandRenderer*/GIMT_Encode2(GICR_renderExtractCPol), // auxiliary
        GIR_MergeMemOperands, /*InsnID*/0, /*NumInsns*/1, /*MergeInsnID's*/0,
        GIR_ConstrainSelectedInstOperands, /*InsnID*/0,
        GIR_EraseFromParent, /*InsnID*/0,
        // GIR_Coverage, 4734,
        GIR_Done,
      // Label 6249: @457720
      GIM_Try, /*On fail goto*//*Label 6250*/ GIMT_Encode4(457787), // Rule ID 4742 //
        GIM_CheckHasNoUse, /*MI*/0,
        GIM_CheckConstantInt8, /*MI*/0, /*Op*/4, 0,
        // MIs[0] offset
        GIM_CheckIsImm, /*MI*/0, /*Op*/6,
        // MIs[0] auxiliary
        GIM_CheckIsImm, /*MI*/0, /*Op*/7,
        // MIs[0] Operand 8
        GIM_CheckIsImm, /*MI*/0, /*Op*/8,
        GIM_CheckComplexPattern, /*MI*/0, /*Op*/5, /*Renderer*/GIMT_Encode2(0), GIMT_Encode2(GICP_gi_buf_soffset),
        // (SIbuffer_atomic_swap:{ *:[f32] } f32:{ *:[f32] }:$vdata_in, v4i32:{ *:[v4i32] }:$rsrc, i32:{ *:[i32] }:$vindex, 0:{ *:[i32] }, (BUFSOffset:{ *:[i32] } i32:{ *:[i32] }:$soffset), (timm:{ *:[i32] }):$offset, (timm:{ *:[i32] }):$auxiliary, (timm:{ *:[i1] }))<<P:Predicate_SIbuffer_atomic_swap_noret>>  =>  (BUFFER_ATOMIC_SWAP_VBUFFER_IDXEN anonymous_15037:{ *:[f32] }:$vdata_in, VGPR_32:{ *:[i32] }:$vindex, SReg_128:{ *:[v4i32] }:$rsrc, SCSrc_b32:{ *:[i32] }:$soffset, (timm:{ *:[i32] }):$offset, (extract_cpol:{ *:[i32] } ?:{ *:[i32] }:$auxiliary))
        GIR_BuildMI, /*InsnID*/0, /*Opcode*/GIMT_Encode2(AMDGPU::BUFFER_ATOMIC_SWAP_VBUFFER_IDXEN),
        GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/1, // vdata_in
        GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/3, // vindex
        GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/2, // rsrc
        GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/0, // soffset
        GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/6, // offset
        GIR_CustomOperandRenderer, /*InsnID*/0, /*OldInsnID*/0, /*OpIdx*/7, /*OperandRenderer*/GIMT_Encode2(GICR_renderExtractCPol), // auxiliary
        GIR_MergeMemOperands, /*InsnID*/0, /*NumInsns*/1, /*MergeInsnID's*/0,
        GIR_ConstrainSelectedInstOperands, /*InsnID*/0,
        GIR_EraseFromParent, /*InsnID*/0,
        // GIR_Coverage, 4742,
        GIR_Done,
      // Label 6250: @457787
      GIM_Try, /*On fail goto*//*Label 6251*/ GIMT_Encode4(457864), // Rule ID 4714 //
        GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasUnrestrictedSOffset),
        GIM_CheckRegBankForClass, /*MI*/0, /*Op*/0, /*RC*/GIMT_Encode2(AMDGPU::AV_32RegClassID),
        GIM_CheckConstantInt8, /*MI*/0, /*Op*/4, 0,
        // MIs[0] offset
        GIM_CheckIsImm, /*MI*/0, /*Op*/6,
        // MIs[0] auxiliary
        GIM_CheckIsImm, /*MI*/0, /*Op*/7,
        // MIs[0] Operand 8
        GIM_CheckIsImm, /*MI*/0, /*Op*/8,
        GIM_CheckComplexPattern, /*MI*/0, /*Op*/5, /*Renderer*/GIMT_Encode2(0), GIMT_Encode2(GICP_gi_buf_soffset),
        // (SIbuffer_atomic_swap:{ *:[i32] } i32:{ *:[i32] }:$vdata_in, v4i32:{ *:[v4i32] }:$rsrc, i32:{ *:[i32] }:$vindex, 0:{ *:[i32] }, (BUFSOffset:{ *:[i32] } i32:{ *:[i32] }:$soffset), (timm:{ *:[i32] }):$offset, (timm:{ *:[i32] }):$auxiliary, (timm:{ *:[i1] }))  =>  (BUFFER_ATOMIC_SWAP_IDXEN_RTN:{ *:[i32] } anonymous_15037:{ *:[i32] }:$vdata_in, VGPR_32:{ *:[i32] }:$vindex, SReg_128:{ *:[v4i32] }:$rsrc, SCSrc_b32:{ *:[i32] }:$soffset, (timm:{ *:[i32] }):$offset, (extract_cpol_set_glc:{ *:[i32] } ?:{ *:[i32] }:$auxiliary))
        GIR_BuildMI, /*InsnID*/0, /*Opcode*/GIMT_Encode2(AMDGPU::BUFFER_ATOMIC_SWAP_IDXEN_RTN),
        GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/0, // DstI[vdata]
        GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/1, // vdata_in
        GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/3, // vindex
        GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/2, // rsrc
        GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/0, // soffset
        GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/6, // offset
        GIR_CustomOperandRenderer, /*InsnID*/0, /*OldInsnID*/0, /*OpIdx*/7, /*OperandRenderer*/GIMT_Encode2(GICR_renderExtractCpolSetGLC), // auxiliary
        GIR_MergeMemOperands, /*InsnID*/0, /*NumInsns*/1, /*MergeInsnID's*/0,
        GIR_ConstrainSelectedInstOperands, /*InsnID*/0,
        GIR_EraseFromParent, /*InsnID*/0,
        // GIR_Coverage, 4714,
        GIR_Done,
      // Label 6251: @457864
      GIM_Try, /*On fail goto*//*Label 6252*/ GIMT_Encode4(457938), // Rule ID 4722 //
        GIM_CheckRegBankForClass, /*MI*/0, /*Op*/0, /*RC*/GIMT_Encode2(AMDGPU::AV_32RegClassID),
        GIM_CheckConstantInt8, /*MI*/0, /*Op*/4, 0,
        // MIs[0] offset
        GIM_CheckIsImm, /*MI*/0, /*Op*/6,
        // MIs[0] auxiliary
        GIM_CheckIsImm, /*MI*/0, /*Op*/7,
        // MIs[0] Operand 8
        GIM_CheckIsImm, /*MI*/0, /*Op*/8,
        GIM_CheckComplexPattern, /*MI*/0, /*Op*/5, /*Renderer*/GIMT_Encode2(0), GIMT_Encode2(GICP_gi_buf_soffset),
        // (SIbuffer_atomic_swap:{ *:[i32] } i32:{ *:[i32] }:$vdata_in, v4i32:{ *:[v4i32] }:$rsrc, i32:{ *:[i32] }:$vindex, 0:{ *:[i32] }, (BUFSOffset:{ *:[i32] } i32:{ *:[i32] }:$soffset), (timm:{ *:[i32] }):$offset, (timm:{ *:[i32] }):$auxiliary, (timm:{ *:[i1] }))  =>  (BUFFER_ATOMIC_SWAP_VBUFFER_IDXEN_RTN:{ *:[i32] } anonymous_15037:{ *:[i32] }:$vdata_in, VGPR_32:{ *:[i32] }:$vindex, SReg_128:{ *:[v4i32] }:$rsrc, SCSrc_b32:{ *:[i32] }:$soffset, (timm:{ *:[i32] }):$offset, (extract_cpol_set_glc:{ *:[i32] } ?:{ *:[i32] }:$auxiliary))
        GIR_BuildMI, /*InsnID*/0, /*Opcode*/GIMT_Encode2(AMDGPU::BUFFER_ATOMIC_SWAP_VBUFFER_IDXEN_RTN),
        GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/0, // DstI[vdata]
        GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/1, // vdata_in
        GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/3, // vindex
        GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/2, // rsrc
        GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/0, // soffset
        GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/6, // offset
        GIR_CustomOperandRenderer, /*InsnID*/0, /*OldInsnID*/0, /*OpIdx*/7, /*OperandRenderer*/GIMT_Encode2(GICR_renderExtractCpolSetGLC), // auxiliary
        GIR_MergeMemOperands, /*InsnID*/0, /*NumInsns*/1, /*MergeInsnID's*/0,
        GIR_ConstrainSelectedInstOperands, /*InsnID*/0,
        GIR_EraseFromParent, /*InsnID*/0,
        // GIR_Coverage, 4722,
        GIR_Done,
      // Label 6252: @457938
      GIM_Try, /*On fail goto*//*Label 6253*/ GIMT_Encode4(458015), // Rule ID 4730 //
        GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasUnrestrictedSOffset),
        GIM_CheckRegBankForClass, /*MI*/0, /*Op*/0, /*RC*/GIMT_Encode2(AMDGPU::AV_32RegClassID),
        GIM_CheckConstantInt8, /*MI*/0, /*Op*/4, 0,
        // MIs[0] offset
        GIM_CheckIsImm, /*MI*/0, /*Op*/6,
        // MIs[0] auxiliary
        GIM_CheckIsImm, /*MI*/0, /*Op*/7,
        // MIs[0] Operand 8
        GIM_CheckIsImm, /*MI*/0, /*Op*/8,
        GIM_CheckComplexPattern, /*MI*/0, /*Op*/5, /*Renderer*/GIMT_Encode2(0), GIMT_Encode2(GICP_gi_buf_soffset),
        // (SIbuffer_atomic_swap:{ *:[f32] } f32:{ *:[f32] }:$vdata_in, v4i32:{ *:[v4i32] }:$rsrc, i32:{ *:[i32] }:$vindex, 0:{ *:[i32] }, (BUFSOffset:{ *:[i32] } i32:{ *:[i32] }:$soffset), (timm:{ *:[i32] }):$offset, (timm:{ *:[i32] }):$auxiliary, (timm:{ *:[i1] }))  =>  (BUFFER_ATOMIC_SWAP_IDXEN_RTN:{ *:[f32] } anonymous_15037:{ *:[f32] }:$vdata_in, VGPR_32:{ *:[i32] }:$vindex, SReg_128:{ *:[v4i32] }:$rsrc, SCSrc_b32:{ *:[i32] }:$soffset, (timm:{ *:[i32] }):$offset, (extract_cpol_set_glc:{ *:[i32] } ?:{ *:[i32] }:$auxiliary))
        GIR_BuildMI, /*InsnID*/0, /*Opcode*/GIMT_Encode2(AMDGPU::BUFFER_ATOMIC_SWAP_IDXEN_RTN),
        GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/0, // DstI[vdata]
        GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/1, // vdata_in
        GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/3, // vindex
        GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/2, // rsrc
        GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/0, // soffset
        GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/6, // offset
        GIR_CustomOperandRenderer, /*InsnID*/0, /*OldInsnID*/0, /*OpIdx*/7, /*OperandRenderer*/GIMT_Encode2(GICR_renderExtractCpolSetGLC), // auxiliary
        GIR_MergeMemOperands, /*InsnID*/0, /*NumInsns*/1, /*MergeInsnID's*/0,
        GIR_ConstrainSelectedInstOperands, /*InsnID*/0,
        GIR_EraseFromParent, /*InsnID*/0,
        // GIR_Coverage, 4730,
        GIR_Done,
      // Label 6253: @458015
      GIM_Try, /*On fail goto*//*Label 6254*/ GIMT_Encode4(458089), // Rule ID 4738 //
        GIM_CheckRegBankForClass, /*MI*/0, /*Op*/0, /*RC*/GIMT_Encode2(AMDGPU::AV_32RegClassID),
        GIM_CheckConstantInt8, /*MI*/0, /*Op*/4, 0,
        // MIs[0] offset
        GIM_CheckIsImm, /*MI*/0, /*Op*/6,
        // MIs[0] auxiliary
        GIM_CheckIsImm, /*MI*/0, /*Op*/7,
        // MIs[0] Operand 8
        GIM_CheckIsImm, /*MI*/0, /*Op*/8,
        GIM_CheckComplexPattern, /*MI*/0, /*Op*/5, /*Renderer*/GIMT_Encode2(0), GIMT_Encode2(GICP_gi_buf_soffset),
        // (SIbuffer_atomic_swap:{ *:[f32] } f32:{ *:[f32] }:$vdata_in, v4i32:{ *:[v4i32] }:$rsrc, i32:{ *:[i32] }:$vindex, 0:{ *:[i32] }, (BUFSOffset:{ *:[i32] } i32:{ *:[i32] }:$soffset), (timm:{ *:[i32] }):$offset, (timm:{ *:[i32] }):$auxiliary, (timm:{ *:[i1] }))  =>  (BUFFER_ATOMIC_SWAP_VBUFFER_IDXEN_RTN:{ *:[f32] } anonymous_15037:{ *:[f32] }:$vdata_in, VGPR_32:{ *:[i32] }:$vindex, SReg_128:{ *:[v4i32] }:$rsrc, SCSrc_b32:{ *:[i32] }:$soffset, (timm:{ *:[i32] }):$offset, (extract_cpol_set_glc:{ *:[i32] } ?:{ *:[i32] }:$auxiliary))
        GIR_BuildMI, /*InsnID*/0, /*Opcode*/GIMT_Encode2(AMDGPU::BUFFER_ATOMIC_SWAP_VBUFFER_IDXEN_RTN),
        GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/0, // DstI[vdata]
        GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/1, // vdata_in
        GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/3, // vindex
        GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/2, // rsrc
        GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/0, // soffset
        GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/6, // offset
        GIR_CustomOperandRenderer, /*InsnID*/0, /*OldInsnID*/0, /*OpIdx*/7, /*OperandRenderer*/GIMT_Encode2(GICR_renderExtractCpolSetGLC), // auxiliary
        GIR_MergeMemOperands, /*InsnID*/0, /*NumInsns*/1, /*MergeInsnID's*/0,
        GIR_ConstrainSelectedInstOperands, /*InsnID*/0,
        GIR_EraseFromParent, /*InsnID*/0,
        // GIR_Coverage, 4738,
        GIR_Done,
      // Label 6254: @458089
      GIM_Try, /*On fail goto*//*Label 6255*/ GIMT_Encode4(458195), // Rule ID 4720 //
        GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasUnrestrictedSOffset),
        GIM_CheckHasNoUse, /*MI*/0,
        // MIs[0] offset
        GIM_CheckIsImm, /*MI*/0, /*Op*/6,
        // MIs[0] auxiliary
        GIM_CheckIsImm, /*MI*/0, /*Op*/7,
        // MIs[0] Operand 8
        GIM_CheckIsImm, /*MI*/0, /*Op*/8,
        GIM_CheckComplexPattern, /*MI*/0, /*Op*/5, /*Renderer*/GIMT_Encode2(0), GIMT_Encode2(GICP_gi_buf_soffset),
        // (SIbuffer_atomic_swap:{ *:[i32] } i32:{ *:[i32] }:$vdata_in, v4i32:{ *:[v4i32] }:$rsrc, i32:{ *:[i32] }:$vindex, i32:{ *:[i32] }:$voffset, (BUFSOffset:{ *:[i32] } i32:{ *:[i32] }:$soffset), (timm:{ *:[i32] }):$offset, (timm:{ *:[i32] }):$auxiliary, (timm:{ *:[i1] }))<<P:Predicate_SIbuffer_atomic_swap_noret>>  =>  (BUFFER_ATOMIC_SWAP_BOTHEN anonymous_15037:{ *:[i32] }:$vdata_in, (REG_SEQUENCE:{ *:[i64] } VReg_64:{ *:[i32] }, VGPR_32:{ *:[i32] }:$vindex, sub0:{ *:[i32] }, VGPR_32:{ *:[i32] }:$voffset, sub1:{ *:[i32] }), SReg_128:{ *:[v4i32] }:$rsrc, SCSrc_b32:{ *:[i32] }:$soffset, (timm:{ *:[i32] }):$offset, (extract_cpol:{ *:[i32] } ?:{ *:[i32] }:$auxiliary))
        GIR_MakeTempReg, /*TempRegID*/0, /*TypeID*/GILLT_s64,
        GIR_BuildMI, /*InsnID*/1, /*Opcode*/GIMT_Encode2(TargetOpcode::REG_SEQUENCE),
        GIR_AddTempRegister, /*InsnID*/1, /*TempRegID*/0, /*TempRegFlags*/GIMT_Encode2(RegState::Define),
        GIR_Copy, /*NewInsnID*/1, /*OldInsnID*/0, /*OpIdx*/3, // vindex
        GIR_AddImm8, /*InsnID*/1, /*SubRegIndex*/3,
        GIR_Copy, /*NewInsnID*/1, /*OldInsnID*/0, /*OpIdx*/4, // voffset
        GIR_AddImm8, /*InsnID*/1, /*SubRegIndex*/11,
        GIR_ConstrainOperandRC, /*InsnID*/1, /*Op*/0, GIMT_Encode2(AMDGPU::VReg_64RegClassID),
        GIR_ConstrainOperandRC, /*InsnID*/1, /*Op*/1, GIMT_Encode2(AMDGPU::VGPR_32RegClassID),
        GIR_ConstrainOperandRC, /*InsnID*/1, /*Op*/3, GIMT_Encode2(AMDGPU::VGPR_32RegClassID),
        GIR_BuildMI, /*InsnID*/0, /*Opcode*/GIMT_Encode2(AMDGPU::BUFFER_ATOMIC_SWAP_BOTHEN),
        GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/1, // vdata_in
        GIR_AddSimpleTempRegister, /*InsnID*/0, /*TempRegID*/0,
        GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/2, // rsrc
        GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/0, // soffset
        GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/6, // offset
        GIR_CustomOperandRenderer, /*InsnID*/0, /*OldInsnID*/0, /*OpIdx*/7, /*OperandRenderer*/GIMT_Encode2(GICR_renderExtractCPol), // auxiliary
        GIR_MergeMemOperands, /*InsnID*/0, /*NumInsns*/1, /*MergeInsnID's*/0,
        GIR_ConstrainSelectedInstOperands, /*InsnID*/0,
        GIR_EraseFromParent, /*InsnID*/0,
        // GIR_Coverage, 4720,
        GIR_Done,
      // Label 6255: @458195
      GIM_Try, /*On fail goto*//*Label 6256*/ GIMT_Encode4(458298), // Rule ID 4728 //
        GIM_CheckHasNoUse, /*MI*/0,
        // MIs[0] offset
        GIM_CheckIsImm, /*MI*/0, /*Op*/6,
        // MIs[0] auxiliary
        GIM_CheckIsImm, /*MI*/0, /*Op*/7,
        // MIs[0] Operand 8
        GIM_CheckIsImm, /*MI*/0, /*Op*/8,
        GIM_CheckComplexPattern, /*MI*/0, /*Op*/5, /*Renderer*/GIMT_Encode2(0), GIMT_Encode2(GICP_gi_buf_soffset),
        // (SIbuffer_atomic_swap:{ *:[i32] } i32:{ *:[i32] }:$vdata_in, v4i32:{ *:[v4i32] }:$rsrc, i32:{ *:[i32] }:$vindex, i32:{ *:[i32] }:$voffset, (BUFSOffset:{ *:[i32] } i32:{ *:[i32] }:$soffset), (timm:{ *:[i32] }):$offset, (timm:{ *:[i32] }):$auxiliary, (timm:{ *:[i1] }))<<P:Predicate_SIbuffer_atomic_swap_noret>>  =>  (BUFFER_ATOMIC_SWAP_VBUFFER_BOTHEN anonymous_15037:{ *:[i32] }:$vdata_in, (REG_SEQUENCE:{ *:[i64] } VReg_64:{ *:[i32] }, VGPR_32:{ *:[i32] }:$vindex, sub0:{ *:[i32] }, VGPR_32:{ *:[i32] }:$voffset, sub1:{ *:[i32] }), SReg_128:{ *:[v4i32] }:$rsrc, SCSrc_b32:{ *:[i32] }:$soffset, (timm:{ *:[i32] }):$offset, (extract_cpol:{ *:[i32] } ?:{ *:[i32] }:$auxiliary))
        GIR_MakeTempReg, /*TempRegID*/0, /*TypeID*/GILLT_s64,
        GIR_BuildMI, /*InsnID*/1, /*Opcode*/GIMT_Encode2(TargetOpcode::REG_SEQUENCE),
        GIR_AddTempRegister, /*InsnID*/1, /*TempRegID*/0, /*TempRegFlags*/GIMT_Encode2(RegState::Define),
        GIR_Copy, /*NewInsnID*/1, /*OldInsnID*/0, /*OpIdx*/3, // vindex
        GIR_AddImm8, /*InsnID*/1, /*SubRegIndex*/3,
        GIR_Copy, /*NewInsnID*/1, /*OldInsnID*/0, /*OpIdx*/4, // voffset
        GIR_AddImm8, /*InsnID*/1, /*SubRegIndex*/11,
        GIR_ConstrainOperandRC, /*InsnID*/1, /*Op*/0, GIMT_Encode2(AMDGPU::VReg_64RegClassID),
        GIR_ConstrainOperandRC, /*InsnID*/1, /*Op*/1, GIMT_Encode2(AMDGPU::VGPR_32RegClassID),
        GIR_ConstrainOperandRC, /*InsnID*/1, /*Op*/3, GIMT_Encode2(AMDGPU::VGPR_32RegClassID),
        GIR_BuildMI, /*InsnID*/0, /*Opcode*/GIMT_Encode2(AMDGPU::BUFFER_ATOMIC_SWAP_VBUFFER_BOTHEN),
        GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/1, // vdata_in
        GIR_AddSimpleTempRegister, /*InsnID*/0, /*TempRegID*/0,
        GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/2, // rsrc
        GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/0, // soffset
        GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/6, // offset
        GIR_CustomOperandRenderer, /*InsnID*/0, /*OldInsnID*/0, /*OpIdx*/7, /*OperandRenderer*/GIMT_Encode2(GICR_renderExtractCPol), // auxiliary
        GIR_MergeMemOperands, /*InsnID*/0, /*NumInsns*/1, /*MergeInsnID's*/0,
        GIR_ConstrainSelectedInstOperands, /*InsnID*/0,
        GIR_EraseFromParent, /*InsnID*/0,
        // GIR_Coverage, 4728,
        GIR_Done,
      // Label 6256: @458298
      GIM_Try, /*On fail goto*//*Label 6257*/ GIMT_Encode4(458404), // Rule ID 4736 //
        GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasUnrestrictedSOffset),
        GIM_CheckHasNoUse, /*MI*/0,
        // MIs[0] offset
        GIM_CheckIsImm, /*MI*/0, /*Op*/6,
        // MIs[0] auxiliary
        GIM_CheckIsImm, /*MI*/0, /*Op*/7,
        // MIs[0] Operand 8
        GIM_CheckIsImm, /*MI*/0, /*Op*/8,
        GIM_CheckComplexPattern, /*MI*/0, /*Op*/5, /*Renderer*/GIMT_Encode2(0), GIMT_Encode2(GICP_gi_buf_soffset),
        // (SIbuffer_atomic_swap:{ *:[f32] } f32:{ *:[f32] }:$vdata_in, v4i32:{ *:[v4i32] }:$rsrc, i32:{ *:[i32] }:$vindex, i32:{ *:[i32] }:$voffset, (BUFSOffset:{ *:[i32] } i32:{ *:[i32] }:$soffset), (timm:{ *:[i32] }):$offset, (timm:{ *:[i32] }):$auxiliary, (timm:{ *:[i1] }))<<P:Predicate_SIbuffer_atomic_swap_noret>>  =>  (BUFFER_ATOMIC_SWAP_BOTHEN anonymous_15037:{ *:[f32] }:$vdata_in, (REG_SEQUENCE:{ *:[i64] } VReg_64:{ *:[i32] }, VGPR_32:{ *:[i32] }:$vindex, sub0:{ *:[i32] }, VGPR_32:{ *:[i32] }:$voffset, sub1:{ *:[i32] }), SReg_128:{ *:[v4i32] }:$rsrc, SCSrc_b32:{ *:[i32] }:$soffset, (timm:{ *:[i32] }):$offset, (extract_cpol:{ *:[i32] } ?:{ *:[i32] }:$auxiliary))
        GIR_MakeTempReg, /*TempRegID*/0, /*TypeID*/GILLT_s64,
        GIR_BuildMI, /*InsnID*/1, /*Opcode*/GIMT_Encode2(TargetOpcode::REG_SEQUENCE),
        GIR_AddTempRegister, /*InsnID*/1, /*TempRegID*/0, /*TempRegFlags*/GIMT_Encode2(RegState::Define),
        GIR_Copy, /*NewInsnID*/1, /*OldInsnID*/0, /*OpIdx*/3, // vindex
        GIR_AddImm8, /*InsnID*/1, /*SubRegIndex*/3,
        GIR_Copy, /*NewInsnID*/1, /*OldInsnID*/0, /*OpIdx*/4, // voffset
        GIR_AddImm8, /*InsnID*/1, /*SubRegIndex*/11,
        GIR_ConstrainOperandRC, /*InsnID*/1, /*Op*/0, GIMT_Encode2(AMDGPU::VReg_64RegClassID),
        GIR_ConstrainOperandRC, /*InsnID*/1, /*Op*/1, GIMT_Encode2(AMDGPU::VGPR_32RegClassID),
        GIR_ConstrainOperandRC, /*InsnID*/1, /*Op*/3, GIMT_Encode2(AMDGPU::VGPR_32RegClassID),
        GIR_BuildMI, /*InsnID*/0, /*Opcode*/GIMT_Encode2(AMDGPU::BUFFER_ATOMIC_SWAP_BOTHEN),
        GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/1, // vdata_in
        GIR_AddSimpleTempRegister, /*InsnID*/0, /*TempRegID*/0,
        GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/2, // rsrc
        GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/0, // soffset
        GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/6, // offset
        GIR_CustomOperandRenderer, /*InsnID*/0, /*OldInsnID*/0, /*OpIdx*/7, /*OperandRenderer*/GIMT_Encode2(GICR_renderExtractCPol), // auxiliary
        GIR_MergeMemOperands, /*InsnID*/0, /*NumInsns*/1, /*MergeInsnID's*/0,
        GIR_ConstrainSelectedInstOperands, /*InsnID*/0,
        GIR_EraseFromParent, /*InsnID*/0,
        // GIR_Coverage, 4736,
        GIR_Done,
      // Label 6257: @458404
      GIM_Try, /*On fail goto*//*Label 6258*/ GIMT_Encode4(458507), // Rule ID 4744 //
        GIM_CheckHasNoUse, /*MI*/0,
        // MIs[0] offset
        GIM_CheckIsImm, /*MI*/0, /*Op*/6,
        // MIs[0] auxiliary
        GIM_CheckIsImm, /*MI*/0, /*Op*/7,
        // MIs[0] Operand 8
        GIM_CheckIsImm, /*MI*/0, /*Op*/8,
        GIM_CheckComplexPattern, /*MI*/0, /*Op*/5, /*Renderer*/GIMT_Encode2(0), GIMT_Encode2(GICP_gi_buf_soffset),
        // (SIbuffer_atomic_swap:{ *:[f32] } f32:{ *:[f32] }:$vdata_in, v4i32:{ *:[v4i32] }:$rsrc, i32:{ *:[i32] }:$vindex, i32:{ *:[i32] }:$voffset, (BUFSOffset:{ *:[i32] } i32:{ *:[i32] }:$soffset), (timm:{ *:[i32] }):$offset, (timm:{ *:[i32] }):$auxiliary, (timm:{ *:[i1] }))<<P:Predicate_SIbuffer_atomic_swap_noret>>  =>  (BUFFER_ATOMIC_SWAP_VBUFFER_BOTHEN anonymous_15037:{ *:[f32] }:$vdata_in, (REG_SEQUENCE:{ *:[i64] } VReg_64:{ *:[i32] }, VGPR_32:{ *:[i32] }:$vindex, sub0:{ *:[i32] }, VGPR_32:{ *:[i32] }:$voffset, sub1:{ *:[i32] }), SReg_128:{ *:[v4i32] }:$rsrc, SCSrc_b32:{ *:[i32] }:$soffset, (timm:{ *:[i32] }):$offset, (extract_cpol:{ *:[i32] } ?:{ *:[i32] }:$auxiliary))
        GIR_MakeTempReg, /*TempRegID*/0, /*TypeID*/GILLT_s64,
        GIR_BuildMI, /*InsnID*/1, /*Opcode*/GIMT_Encode2(TargetOpcode::REG_SEQUENCE),
        GIR_AddTempRegister, /*InsnID*/1, /*TempRegID*/0, /*TempRegFlags*/GIMT_Encode2(RegState::Define),
        GIR_Copy, /*NewInsnID*/1, /*OldInsnID*/0, /*OpIdx*/3, // vindex
        GIR_AddImm8, /*InsnID*/1, /*SubRegIndex*/3,
        GIR_Copy, /*NewInsnID*/1, /*OldInsnID*/0, /*OpIdx*/4, // voffset
        GIR_AddImm8, /*InsnID*/1, /*SubRegIndex*/11,
        GIR_ConstrainOperandRC, /*InsnID*/1, /*Op*/0, GIMT_Encode2(AMDGPU::VReg_64RegClassID),
        GIR_ConstrainOperandRC, /*InsnID*/1, /*Op*/1, GIMT_Encode2(AMDGPU::VGPR_32RegClassID),
        GIR_ConstrainOperandRC, /*InsnID*/1, /*Op*/3, GIMT_Encode2(AMDGPU::VGPR_32RegClassID),
        GIR_BuildMI, /*InsnID*/0, /*Opcode*/GIMT_Encode2(AMDGPU::BUFFER_ATOMIC_SWAP_VBUFFER_BOTHEN),
        GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/1, // vdata_in
        GIR_AddSimpleTempRegister, /*InsnID*/0, /*TempRegID*/0,
        GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/2, // rsrc
        GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/0, // soffset
        GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/6, // offset
        GIR_CustomOperandRenderer, /*InsnID*/0, /*OldInsnID*/0, /*OpIdx*/7, /*OperandRenderer*/GIMT_Encode2(GICR_renderExtractCPol), // auxiliary
        GIR_MergeMemOperands, /*InsnID*/0, /*NumInsns*/1, /*MergeInsnID's*/0,
        GIR_ConstrainSelectedInstOperands, /*InsnID*/0,
        GIR_EraseFromParent, /*InsnID*/0,
        // GIR_Coverage, 4744,
        GIR_Done,
      // Label 6258: @458507
      GIM_Try, /*On fail goto*//*Label 6259*/ GIMT_Encode4(458620), // Rule ID 4716 //
        GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasUnrestrictedSOffset),
        GIM_CheckRegBankForClass, /*MI*/0, /*Op*/0, /*RC*/GIMT_Encode2(AMDGPU::AV_32RegClassID),
        // MIs[0] offset
        GIM_CheckIsImm, /*MI*/0, /*Op*/6,
        // MIs[0] auxiliary
        GIM_CheckIsImm, /*MI*/0, /*Op*/7,
        // MIs[0] Operand 8
        GIM_CheckIsImm, /*MI*/0, /*Op*/8,
        GIM_CheckComplexPattern, /*MI*/0, /*Op*/5, /*Renderer*/GIMT_Encode2(0), GIMT_Encode2(GICP_gi_buf_soffset),
        // (SIbuffer_atomic_swap:{ *:[i32] } i32:{ *:[i32] }:$vdata_in, v4i32:{ *:[v4i32] }:$rsrc, i32:{ *:[i32] }:$vindex, i32:{ *:[i32] }:$voffset, (BUFSOffset:{ *:[i32] } i32:{ *:[i32] }:$soffset), (timm:{ *:[i32] }):$offset, (timm:{ *:[i32] }):$auxiliary, (timm:{ *:[i1] }))  =>  (BUFFER_ATOMIC_SWAP_BOTHEN_RTN:{ *:[i32] } anonymous_15037:{ *:[i32] }:$vdata_in, (REG_SEQUENCE:{ *:[i64] } VReg_64:{ *:[i32] }, VGPR_32:{ *:[i32] }:$vindex, sub0:{ *:[i32] }, VGPR_32:{ *:[i32] }:$voffset, sub1:{ *:[i32] }), SReg_128:{ *:[v4i32] }:$rsrc, SCSrc_b32:{ *:[i32] }:$soffset, (timm:{ *:[i32] }):$offset, (extract_cpol_set_glc:{ *:[i32] } ?:{ *:[i32] }:$auxiliary))
        GIR_MakeTempReg, /*TempRegID*/0, /*TypeID*/GILLT_s64,
        GIR_BuildMI, /*InsnID*/1, /*Opcode*/GIMT_Encode2(TargetOpcode::REG_SEQUENCE),
        GIR_AddTempRegister, /*InsnID*/1, /*TempRegID*/0, /*TempRegFlags*/GIMT_Encode2(RegState::Define),
        GIR_Copy, /*NewInsnID*/1, /*OldInsnID*/0, /*OpIdx*/3, // vindex
        GIR_AddImm8, /*InsnID*/1, /*SubRegIndex*/3,
        GIR_Copy, /*NewInsnID*/1, /*OldInsnID*/0, /*OpIdx*/4, // voffset
        GIR_AddImm8, /*InsnID*/1, /*SubRegIndex*/11,
        GIR_ConstrainOperandRC, /*InsnID*/1, /*Op*/0, GIMT_Encode2(AMDGPU::VReg_64RegClassID),
        GIR_ConstrainOperandRC, /*InsnID*/1, /*Op*/1, GIMT_Encode2(AMDGPU::VGPR_32RegClassID),
        GIR_ConstrainOperandRC, /*InsnID*/1, /*Op*/3, GIMT_Encode2(AMDGPU::VGPR_32RegClassID),
        GIR_BuildMI, /*InsnID*/0, /*Opcode*/GIMT_Encode2(AMDGPU::BUFFER_ATOMIC_SWAP_BOTHEN_RTN),
        GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/0, // DstI[vdata]
        GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/1, // vdata_in
        GIR_AddSimpleTempRegister, /*InsnID*/0, /*TempRegID*/0,
        GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/2, // rsrc
        GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/0, // soffset
        GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/6, // offset
        GIR_CustomOperandRenderer, /*InsnID*/0, /*OldInsnID*/0, /*OpIdx*/7, /*OperandRenderer*/GIMT_Encode2(GICR_renderExtractCpolSetGLC), // auxiliary
        GIR_MergeMemOperands, /*InsnID*/0, /*NumInsns*/1, /*MergeInsnID's*/0,
        GIR_ConstrainSelectedInstOperands, /*InsnID*/0,
        GIR_EraseFromParent, /*InsnID*/0,
        // GIR_Coverage, 4716,
        GIR_Done,
      // Label 6259: @458620
      GIM_Try, /*On fail goto*//*Label 6260*/ GIMT_Encode4(458730), // Rule ID 4724 //
        GIM_CheckRegBankForClass, /*MI*/0, /*Op*/0, /*RC*/GIMT_Encode2(AMDGPU::AV_32RegClassID),
        // MIs[0] offset
        GIM_CheckIsImm, /*MI*/0, /*Op*/6,
        // MIs[0] auxiliary
        GIM_CheckIsImm, /*MI*/0, /*Op*/7,
        // MIs[0] Operand 8
        GIM_CheckIsImm, /*MI*/0, /*Op*/8,
        GIM_CheckComplexPattern, /*MI*/0, /*Op*/5, /*Renderer*/GIMT_Encode2(0), GIMT_Encode2(GICP_gi_buf_soffset),
        // (SIbuffer_atomic_swap:{ *:[i32] } i32:{ *:[i32] }:$vdata_in, v4i32:{ *:[v4i32] }:$rsrc, i32:{ *:[i32] }:$vindex, i32:{ *:[i32] }:$voffset, (BUFSOffset:{ *:[i32] } i32:{ *:[i32] }:$soffset), (timm:{ *:[i32] }):$offset, (timm:{ *:[i32] }):$auxiliary, (timm:{ *:[i1] }))  =>  (BUFFER_ATOMIC_SWAP_VBUFFER_BOTHEN_RTN:{ *:[i32] } anonymous_15037:{ *:[i32] }:$vdata_in, (REG_SEQUENCE:{ *:[i64] } VReg_64:{ *:[i32] }, VGPR_32:{ *:[i32] }:$vindex, sub0:{ *:[i32] }, VGPR_32:{ *:[i32] }:$voffset, sub1:{ *:[i32] }), SReg_128:{ *:[v4i32] }:$rsrc, SCSrc_b32:{ *:[i32] }:$soffset, (timm:{ *:[i32] }):$offset, (extract_cpol_set_glc:{ *:[i32] } ?:{ *:[i32] }:$auxiliary))
        GIR_MakeTempReg, /*TempRegID*/0, /*TypeID*/GILLT_s64,
        GIR_BuildMI, /*InsnID*/1, /*Opcode*/GIMT_Encode2(TargetOpcode::REG_SEQUENCE),
        GIR_AddTempRegister, /*InsnID*/1, /*TempRegID*/0, /*TempRegFlags*/GIMT_Encode2(RegState::Define),
        GIR_Copy, /*NewInsnID*/1, /*OldInsnID*/0, /*OpIdx*/3, // vindex
        GIR_AddImm8, /*InsnID*/1, /*SubRegIndex*/3,
        GIR_Copy, /*NewInsnID*/1, /*OldInsnID*/0, /*OpIdx*/4, // voffset
        GIR_AddImm8, /*InsnID*/1, /*SubRegIndex*/11,
        GIR_ConstrainOperandRC, /*InsnID*/1, /*Op*/0, GIMT_Encode2(AMDGPU::VReg_64RegClassID),
        GIR_ConstrainOperandRC, /*InsnID*/1, /*Op*/1, GIMT_Encode2(AMDGPU::VGPR_32RegClassID),
        GIR_ConstrainOperandRC, /*InsnID*/1, /*Op*/3, GIMT_Encode2(AMDGPU::VGPR_32RegClassID),
        GIR_BuildMI, /*InsnID*/0, /*Opcode*/GIMT_Encode2(AMDGPU::BUFFER_ATOMIC_SWAP_VBUFFER_BOTHEN_RTN),
        GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/0, // DstI[vdata]
        GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/1, // vdata_in
        GIR_AddSimpleTempRegister, /*InsnID*/0, /*TempRegID*/0,
        GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/2, // rsrc
        GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/0, // soffset
        GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/6, // offset
        GIR_CustomOperandRenderer, /*InsnID*/0, /*OldInsnID*/0, /*OpIdx*/7, /*OperandRenderer*/GIMT_Encode2(GICR_renderExtractCpolSetGLC), // auxiliary
        GIR_MergeMemOperands, /*InsnID*/0, /*NumInsns*/1, /*MergeInsnID's*/0,
        GIR_ConstrainSelectedInstOperands, /*InsnID*/0,
        GIR_EraseFromParent, /*InsnID*/0,
        // GIR_Coverage, 4724,
        GIR_Done,
      // Label 6260: @458730
      GIM_Try, /*On fail goto*//*Label 6261*/ GIMT_Encode4(458843), // Rule ID 4732 //
        GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasUnrestrictedSOffset),
        GIM_CheckRegBankForClass, /*MI*/0, /*Op*/0, /*RC*/GIMT_Encode2(AMDGPU::AV_32RegClassID),
        // MIs[0] offset
        GIM_CheckIsImm, /*MI*/0, /*Op*/6,
        // MIs[0] auxiliary
        GIM_CheckIsImm, /*MI*/0, /*Op*/7,
        // MIs[0] Operand 8
        GIM_CheckIsImm, /*MI*/0, /*Op*/8,
        GIM_CheckComplexPattern, /*MI*/0, /*Op*/5, /*Renderer*/GIMT_Encode2(0), GIMT_Encode2(GICP_gi_buf_soffset),
        // (SIbuffer_atomic_swap:{ *:[f32] } f32:{ *:[f32] }:$vdata_in, v4i32:{ *:[v4i32] }:$rsrc, i32:{ *:[i32] }:$vindex, i32:{ *:[i32] }:$voffset, (BUFSOffset:{ *:[i32] } i32:{ *:[i32] }:$soffset), (timm:{ *:[i32] }):$offset, (timm:{ *:[i32] }):$auxiliary, (timm:{ *:[i1] }))  =>  (BUFFER_ATOMIC_SWAP_BOTHEN_RTN:{ *:[f32] } anonymous_15037:{ *:[f32] }:$vdata_in, (REG_SEQUENCE:{ *:[i64] } VReg_64:{ *:[i32] }, VGPR_32:{ *:[i32] }:$vindex, sub0:{ *:[i32] }, VGPR_32:{ *:[i32] }:$voffset, sub1:{ *:[i32] }), SReg_128:{ *:[v4i32] }:$rsrc, SCSrc_b32:{ *:[i32] }:$soffset, (timm:{ *:[i32] }):$offset, (extract_cpol_set_glc:{ *:[i32] } ?:{ *:[i32] }:$auxiliary))
        GIR_MakeTempReg, /*TempRegID*/0, /*TypeID*/GILLT_s64,
        GIR_BuildMI, /*InsnID*/1, /*Opcode*/GIMT_Encode2(TargetOpcode::REG_SEQUENCE),
        GIR_AddTempRegister, /*InsnID*/1, /*TempRegID*/0, /*TempRegFlags*/GIMT_Encode2(RegState::Define),
        GIR_Copy, /*NewInsnID*/1, /*OldInsnID*/0, /*OpIdx*/3, // vindex
        GIR_AddImm8, /*InsnID*/1, /*SubRegIndex*/3,
        GIR_Copy, /*NewInsnID*/1, /*OldInsnID*/0, /*OpIdx*/4, // voffset
        GIR_AddImm8, /*InsnID*/1, /*SubRegIndex*/11,
        GIR_ConstrainOperandRC, /*InsnID*/1, /*Op*/0, GIMT_Encode2(AMDGPU::VReg_64RegClassID),
        GIR_ConstrainOperandRC, /*InsnID*/1, /*Op*/1, GIMT_Encode2(AMDGPU::VGPR_32RegClassID),
        GIR_ConstrainOperandRC, /*InsnID*/1, /*Op*/3, GIMT_Encode2(AMDGPU::VGPR_32RegClassID),
        GIR_BuildMI, /*InsnID*/0, /*Opcode*/GIMT_Encode2(AMDGPU::BUFFER_ATOMIC_SWAP_BOTHEN_RTN),
        GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/0, // DstI[vdata]
        GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/1, // vdata_in
        GIR_AddSimpleTempRegister, /*InsnID*/0, /*TempRegID*/0,
        GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/2, // rsrc
        GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/0, // soffset
        GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/6, // offset
        GIR_CustomOperandRenderer, /*InsnID*/0, /*OldInsnID*/0, /*OpIdx*/7, /*OperandRenderer*/GIMT_Encode2(GICR_renderExtractCpolSetGLC), // auxiliary
        GIR_MergeMemOperands, /*InsnID*/0, /*NumInsns*/1, /*MergeInsnID's*/0,
        GIR_ConstrainSelectedInstOperands, /*InsnID*/0,
        GIR_EraseFromParent, /*InsnID*/0,
        // GIR_Coverage, 4732,
        GIR_Done,
      // Label 6261: @458843
      GIM_Try, /*On fail goto*//*Label 6262*/ GIMT_Encode4(458953), // Rule ID 4740 //
        GIM_CheckRegBankForClass, /*MI*/0, /*Op*/0, /*RC*/GIMT_Encode2(AMDGPU::AV_32RegClassID),
        // MIs[0] offset
        GIM_CheckIsImm, /*MI*/0, /*Op*/6,
        // MIs[0] auxiliary
        GIM_CheckIsImm, /*MI*/0, /*Op*/7,
        // MIs[0] Operand 8
        GIM_CheckIsImm, /*MI*/0, /*Op*/8,
        GIM_CheckComplexPattern, /*MI*/0, /*Op*/5, /*Renderer*/GIMT_Encode2(0), GIMT_Encode2(GICP_gi_buf_soffset),
        // (SIbuffer_atomic_swap:{ *:[f32] } f32:{ *:[f32] }:$vdata_in, v4i32:{ *:[v4i32] }:$rsrc, i32:{ *:[i32] }:$vindex, i32:{ *:[i32] }:$voffset, (BUFSOffset:{ *:[i32] } i32:{ *:[i32] }:$soffset), (timm:{ *:[i32] }):$offset, (timm:{ *:[i32] }):$auxiliary, (timm:{ *:[i1] }))  =>  (BUFFER_ATOMIC_SWAP_VBUFFER_BOTHEN_RTN:{ *:[f32] } anonymous_15037:{ *:[f32] }:$vdata_in, (REG_SEQUENCE:{ *:[i64] } VReg_64:{ *:[i32] }, VGPR_32:{ *:[i32] }:$vindex, sub0:{ *:[i32] }, VGPR_32:{ *:[i32] }:$voffset, sub1:{ *:[i32] }), SReg_128:{ *:[v4i32] }:$rsrc, SCSrc_b32:{ *:[i32] }:$soffset, (timm:{ *:[i32] }):$offset, (extract_cpol_set_glc:{ *:[i32] } ?:{ *:[i32] }:$auxiliary))
        GIR_MakeTempReg, /*TempRegID*/0, /*TypeID*/GILLT_s64,
        GIR_BuildMI, /*InsnID*/1, /*Opcode*/GIMT_Encode2(TargetOpcode::REG_SEQUENCE),
        GIR_AddTempRegister, /*InsnID*/1, /*TempRegID*/0, /*TempRegFlags*/GIMT_Encode2(RegState::Define),
        GIR_Copy, /*NewInsnID*/1, /*OldInsnID*/0, /*OpIdx*/3, // vindex
        GIR_AddImm8, /*InsnID*/1, /*SubRegIndex*/3,
        GIR_Copy, /*NewInsnID*/1, /*OldInsnID*/0, /*OpIdx*/4, // voffset
        GIR_AddImm8, /*InsnID*/1, /*SubRegIndex*/11,
        GIR_ConstrainOperandRC, /*InsnID*/1, /*Op*/0, GIMT_Encode2(AMDGPU::VReg_64RegClassID),
        GIR_ConstrainOperandRC, /*InsnID*/1, /*Op*/1, GIMT_Encode2(AMDGPU::VGPR_32RegClassID),
        GIR_ConstrainOperandRC, /*InsnID*/1, /*Op*/3, GIMT_Encode2(AMDGPU::VGPR_32RegClassID),
        GIR_BuildMI, /*InsnID*/0, /*Opcode*/GIMT_Encode2(AMDGPU::BUFFER_ATOMIC_SWAP_VBUFFER_BOTHEN_RTN),
        GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/0, // DstI[vdata]
        GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/1, // vdata_in
        GIR_AddSimpleTempRegister, /*InsnID*/0, /*TempRegID*/0,
        GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/2, // rsrc
        GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/0, // soffset
        GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/6, // offset
        GIR_CustomOperandRenderer, /*InsnID*/0, /*OldInsnID*/0, /*OpIdx*/7, /*OperandRenderer*/GIMT_Encode2(GICR_renderExtractCpolSetGLC), // auxiliary
        GIR_MergeMemOperands, /*InsnID*/0, /*NumInsns*/1, /*MergeInsnID's*/0,
        GIR_ConstrainSelectedInstOperands, /*InsnID*/0,
        GIR_EraseFromParent, /*InsnID*/0,
        // GIR_Coverage, 4740,
        GIR_Done,
      // Label 6262: @458953
      GIM_Reject,
    // Label 6230: @458954
    GIM_Reject,
    // Label 6228: @458955
    GIM_Try, /*On fail goto*//*Label 6263*/ GIMT_Encode4(460341),
      GIM_CheckType, /*MI*/0, /*Op*/1, /*Type*/GILLT_s64,
      GIM_CheckType, /*MI*/0, /*Op*/2, /*Type*/GILLT_v4s32,
      GIM_CheckType, /*MI*/0, /*Op*/3, /*Type*/GILLT_s32,
      GIM_CheckType, /*MI*/0, /*Op*/4, /*Type*/GILLT_s32,
      GIM_CheckType, /*MI*/0, /*Op*/5, /*Type*/GILLT_s32,
      GIM_Try, /*On fail goto*//*Label 6264*/ GIMT_Encode4(459058), // Rule ID 4933 //
        GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasUnrestrictedSOffset),
        GIM_CheckHasNoUse, /*MI*/0,
        GIM_CheckConstantInt8, /*MI*/0, /*Op*/3, 0,
        GIM_CheckConstantInt8, /*MI*/0, /*Op*/4, 0,
        // MIs[0] offset
        GIM_CheckIsImm, /*MI*/0, /*Op*/6,
        // MIs[0] auxiliary
        GIM_CheckIsImm, /*MI*/0, /*Op*/7,
        // MIs[0] Operand 8
        GIM_CheckLiteralInt, /*MI*/0, /*Op*/8, GIMT_Encode8(0),
        GIM_CheckComplexPattern, /*MI*/0, /*Op*/5, /*Renderer*/GIMT_Encode2(0), GIMT_Encode2(GICP_gi_buf_soffset),
        // (SIbuffer_atomic_swap:{ *:[i64] } i64:{ *:[i64] }:$vdata_in, v4i32:{ *:[v4i32] }:$rsrc, 0:{ *:[i32] }, 0:{ *:[i32] }, (BUFSOffset:{ *:[i32] } i32:{ *:[i32] }:$soffset), (timm:{ *:[i32] }):$offset, (timm:{ *:[i32] }):$auxiliary, 0:{ *:[i1] })<<P:Predicate_SIbuffer_atomic_swap_noret>>  =>  (BUFFER_ATOMIC_SWAP_X2_OFFSET anonymous_15036:{ *:[i64] }:$vdata_in, SReg_128:{ *:[v4i32] }:$rsrc, SCSrc_b32:{ *:[i32] }:$soffset, (timm:{ *:[i32] }):$offset, (extract_cpol:{ *:[i32] } ?:{ *:[i32] }:$auxiliary))
        GIR_BuildMI, /*InsnID*/0, /*Opcode*/GIMT_Encode2(AMDGPU::BUFFER_ATOMIC_SWAP_X2_OFFSET),
        GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/1, // vdata_in
        GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/2, // rsrc
        GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/0, // soffset
        GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/6, // offset
        GIR_CustomOperandRenderer, /*InsnID*/0, /*OldInsnID*/0, /*OpIdx*/7, /*OperandRenderer*/GIMT_Encode2(GICR_renderExtractCPol), // auxiliary
        GIR_MergeMemOperands, /*InsnID*/0, /*NumInsns*/1, /*MergeInsnID's*/0,
        GIR_ConstrainSelectedInstOperands, /*InsnID*/0,
        GIR_EraseFromParent, /*InsnID*/0,
        // GIR_Coverage, 4933,
        GIR_Done,
      // Label 6264: @459058
      GIM_Try, /*On fail goto*//*Label 6265*/ GIMT_Encode4(459133), // Rule ID 4941 //
        GIM_CheckHasNoUse, /*MI*/0,
        GIM_CheckConstantInt8, /*MI*/0, /*Op*/3, 0,
        GIM_CheckConstantInt8, /*MI*/0, /*Op*/4, 0,
        // MIs[0] offset
        GIM_CheckIsImm, /*MI*/0, /*Op*/6,
        // MIs[0] auxiliary
        GIM_CheckIsImm, /*MI*/0, /*Op*/7,
        // MIs[0] Operand 8
        GIM_CheckLiteralInt, /*MI*/0, /*Op*/8, GIMT_Encode8(0),
        GIM_CheckComplexPattern, /*MI*/0, /*Op*/5, /*Renderer*/GIMT_Encode2(0), GIMT_Encode2(GICP_gi_buf_soffset),
        // (SIbuffer_atomic_swap:{ *:[i64] } i64:{ *:[i64] }:$vdata_in, v4i32:{ *:[v4i32] }:$rsrc, 0:{ *:[i32] }, 0:{ *:[i32] }, (BUFSOffset:{ *:[i32] } i32:{ *:[i32] }:$soffset), (timm:{ *:[i32] }):$offset, (timm:{ *:[i32] }):$auxiliary, 0:{ *:[i1] })<<P:Predicate_SIbuffer_atomic_swap_noret>>  =>  (BUFFER_ATOMIC_SWAP_X2_VBUFFER_OFFSET anonymous_15036:{ *:[i64] }:$vdata_in, SReg_128:{ *:[v4i32] }:$rsrc, SCSrc_b32:{ *:[i32] }:$soffset, (timm:{ *:[i32] }):$offset, (extract_cpol:{ *:[i32] } ?:{ *:[i32] }:$auxiliary))
        GIR_BuildMI, /*InsnID*/0, /*Opcode*/GIMT_Encode2(AMDGPU::BUFFER_ATOMIC_SWAP_X2_VBUFFER_OFFSET),
        GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/1, // vdata_in
        GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/2, // rsrc
        GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/0, // soffset
        GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/6, // offset
        GIR_CustomOperandRenderer, /*InsnID*/0, /*OldInsnID*/0, /*OpIdx*/7, /*OperandRenderer*/GIMT_Encode2(GICR_renderExtractCPol), // auxiliary
        GIR_MergeMemOperands, /*InsnID*/0, /*NumInsns*/1, /*MergeInsnID's*/0,
        GIR_ConstrainSelectedInstOperands, /*InsnID*/0,
        GIR_EraseFromParent, /*InsnID*/0,
        // GIR_Coverage, 4941,
        GIR_Done,
      // Label 6265: @459133
      GIM_Try, /*On fail goto*//*Label 6266*/ GIMT_Encode4(459218), // Rule ID 4929 //
        GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasUnrestrictedSOffset),
        GIM_CheckRegBankForClass, /*MI*/0, /*Op*/0, /*RC*/GIMT_Encode2(AMDGPU::AV_64RegClassID),
        GIM_CheckConstantInt8, /*MI*/0, /*Op*/3, 0,
        GIM_CheckConstantInt8, /*MI*/0, /*Op*/4, 0,
        // MIs[0] offset
        GIM_CheckIsImm, /*MI*/0, /*Op*/6,
        // MIs[0] auxiliary
        GIM_CheckIsImm, /*MI*/0, /*Op*/7,
        // MIs[0] Operand 8
        GIM_CheckLiteralInt, /*MI*/0, /*Op*/8, GIMT_Encode8(0),
        GIM_CheckComplexPattern, /*MI*/0, /*Op*/5, /*Renderer*/GIMT_Encode2(0), GIMT_Encode2(GICP_gi_buf_soffset),
        // (SIbuffer_atomic_swap:{ *:[i64] } i64:{ *:[i64] }:$vdata_in, v4i32:{ *:[v4i32] }:$rsrc, 0:{ *:[i32] }, 0:{ *:[i32] }, (BUFSOffset:{ *:[i32] } i32:{ *:[i32] }:$soffset), (timm:{ *:[i32] }):$offset, (timm:{ *:[i32] }):$auxiliary, 0:{ *:[i1] })  =>  (BUFFER_ATOMIC_SWAP_X2_OFFSET_RTN:{ *:[i64] } anonymous_15036:{ *:[i64] }:$vdata_in, SReg_128:{ *:[v4i32] }:$rsrc, SCSrc_b32:{ *:[i32] }:$soffset, (timm:{ *:[i32] }):$offset, (extract_cpol_set_glc:{ *:[i32] } ?:{ *:[i32] }:$auxiliary))
        GIR_BuildMI, /*InsnID*/0, /*Opcode*/GIMT_Encode2(AMDGPU::BUFFER_ATOMIC_SWAP_X2_OFFSET_RTN),
        GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/0, // DstI[vdata]
        GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/1, // vdata_in
        GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/2, // rsrc
        GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/0, // soffset
        GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/6, // offset
        GIR_CustomOperandRenderer, /*InsnID*/0, /*OldInsnID*/0, /*OpIdx*/7, /*OperandRenderer*/GIMT_Encode2(GICR_renderExtractCpolSetGLC), // auxiliary
        GIR_MergeMemOperands, /*InsnID*/0, /*NumInsns*/1, /*MergeInsnID's*/0,
        GIR_ConstrainSelectedInstOperands, /*InsnID*/0,
        GIR_EraseFromParent, /*InsnID*/0,
        // GIR_Coverage, 4929,
        GIR_Done,
      // Label 6266: @459218
      GIM_Try, /*On fail goto*//*Label 6267*/ GIMT_Encode4(459300), // Rule ID 4937 //
        GIM_CheckRegBankForClass, /*MI*/0, /*Op*/0, /*RC*/GIMT_Encode2(AMDGPU::AV_64RegClassID),
        GIM_CheckConstantInt8, /*MI*/0, /*Op*/3, 0,
        GIM_CheckConstantInt8, /*MI*/0, /*Op*/4, 0,
        // MIs[0] offset
        GIM_CheckIsImm, /*MI*/0, /*Op*/6,
        // MIs[0] auxiliary
        GIM_CheckIsImm, /*MI*/0, /*Op*/7,
        // MIs[0] Operand 8
        GIM_CheckLiteralInt, /*MI*/0, /*Op*/8, GIMT_Encode8(0),
        GIM_CheckComplexPattern, /*MI*/0, /*Op*/5, /*Renderer*/GIMT_Encode2(0), GIMT_Encode2(GICP_gi_buf_soffset),
        // (SIbuffer_atomic_swap:{ *:[i64] } i64:{ *:[i64] }:$vdata_in, v4i32:{ *:[v4i32] }:$rsrc, 0:{ *:[i32] }, 0:{ *:[i32] }, (BUFSOffset:{ *:[i32] } i32:{ *:[i32] }:$soffset), (timm:{ *:[i32] }):$offset, (timm:{ *:[i32] }):$auxiliary, 0:{ *:[i1] })  =>  (BUFFER_ATOMIC_SWAP_X2_VBUFFER_OFFSET_RTN:{ *:[i64] } anonymous_15036:{ *:[i64] }:$vdata_in, SReg_128:{ *:[v4i32] }:$rsrc, SCSrc_b32:{ *:[i32] }:$soffset, (timm:{ *:[i32] }):$offset, (extract_cpol_set_glc:{ *:[i32] } ?:{ *:[i32] }:$auxiliary))
        GIR_BuildMI, /*InsnID*/0, /*Opcode*/GIMT_Encode2(AMDGPU::BUFFER_ATOMIC_SWAP_X2_VBUFFER_OFFSET_RTN),
        GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/0, // DstI[vdata]
        GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/1, // vdata_in
        GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/2, // rsrc
        GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/0, // soffset
        GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/6, // offset
        GIR_CustomOperandRenderer, /*InsnID*/0, /*OldInsnID*/0, /*OpIdx*/7, /*OperandRenderer*/GIMT_Encode2(GICR_renderExtractCpolSetGLC), // auxiliary
        GIR_MergeMemOperands, /*InsnID*/0, /*NumInsns*/1, /*MergeInsnID's*/0,
        GIR_ConstrainSelectedInstOperands, /*InsnID*/0,
        GIR_EraseFromParent, /*InsnID*/0,
        // GIR_Coverage, 4937,
        GIR_Done,
      // Label 6267: @459300
      GIM_Try, /*On fail goto*//*Label 6268*/ GIMT_Encode4(459378), // Rule ID 4935 //
        GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasUnrestrictedSOffset),
        GIM_CheckHasNoUse, /*MI*/0,
        GIM_CheckConstantInt8, /*MI*/0, /*Op*/3, 0,
        // MIs[0] offset
        GIM_CheckIsImm, /*MI*/0, /*Op*/6,
        // MIs[0] auxiliary
        GIM_CheckIsImm, /*MI*/0, /*Op*/7,
        // MIs[0] Operand 8
        GIM_CheckLiteralInt, /*MI*/0, /*Op*/8, GIMT_Encode8(0),
        GIM_CheckComplexPattern, /*MI*/0, /*Op*/5, /*Renderer*/GIMT_Encode2(0), GIMT_Encode2(GICP_gi_buf_soffset),
        // (SIbuffer_atomic_swap:{ *:[i64] } i64:{ *:[i64] }:$vdata_in, v4i32:{ *:[v4i32] }:$rsrc, 0:{ *:[i32] }, i32:{ *:[i32] }:$voffset, (BUFSOffset:{ *:[i32] } i32:{ *:[i32] }:$soffset), (timm:{ *:[i32] }):$offset, (timm:{ *:[i32] }):$auxiliary, 0:{ *:[i1] })<<P:Predicate_SIbuffer_atomic_swap_noret>>  =>  (BUFFER_ATOMIC_SWAP_X2_OFFEN anonymous_15036:{ *:[i64] }:$vdata_in, VGPR_32:{ *:[i32] }:$voffset, SReg_128:{ *:[v4i32] }:$rsrc, SCSrc_b32:{ *:[i32] }:$soffset, (timm:{ *:[i32] }):$offset, (extract_cpol:{ *:[i32] } ?:{ *:[i32] }:$auxiliary))
        GIR_BuildMI, /*InsnID*/0, /*Opcode*/GIMT_Encode2(AMDGPU::BUFFER_ATOMIC_SWAP_X2_OFFEN),
        GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/1, // vdata_in
        GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/4, // voffset
        GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/2, // rsrc
        GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/0, // soffset
        GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/6, // offset
        GIR_CustomOperandRenderer, /*InsnID*/0, /*OldInsnID*/0, /*OpIdx*/7, /*OperandRenderer*/GIMT_Encode2(GICR_renderExtractCPol), // auxiliary
        GIR_MergeMemOperands, /*InsnID*/0, /*NumInsns*/1, /*MergeInsnID's*/0,
        GIR_ConstrainSelectedInstOperands, /*InsnID*/0,
        GIR_EraseFromParent, /*InsnID*/0,
        // GIR_Coverage, 4935,
        GIR_Done,
      // Label 6268: @459378
      GIM_Try, /*On fail goto*//*Label 6269*/ GIMT_Encode4(459453), // Rule ID 4943 //
        GIM_CheckHasNoUse, /*MI*/0,
        GIM_CheckConstantInt8, /*MI*/0, /*Op*/3, 0,
        // MIs[0] offset
        GIM_CheckIsImm, /*MI*/0, /*Op*/6,
        // MIs[0] auxiliary
        GIM_CheckIsImm, /*MI*/0, /*Op*/7,
        // MIs[0] Operand 8
        GIM_CheckLiteralInt, /*MI*/0, /*Op*/8, GIMT_Encode8(0),
        GIM_CheckComplexPattern, /*MI*/0, /*Op*/5, /*Renderer*/GIMT_Encode2(0), GIMT_Encode2(GICP_gi_buf_soffset),
        // (SIbuffer_atomic_swap:{ *:[i64] } i64:{ *:[i64] }:$vdata_in, v4i32:{ *:[v4i32] }:$rsrc, 0:{ *:[i32] }, i32:{ *:[i32] }:$voffset, (BUFSOffset:{ *:[i32] } i32:{ *:[i32] }:$soffset), (timm:{ *:[i32] }):$offset, (timm:{ *:[i32] }):$auxiliary, 0:{ *:[i1] })<<P:Predicate_SIbuffer_atomic_swap_noret>>  =>  (BUFFER_ATOMIC_SWAP_X2_VBUFFER_OFFEN anonymous_15036:{ *:[i64] }:$vdata_in, VGPR_32:{ *:[i32] }:$voffset, SReg_128:{ *:[v4i32] }:$rsrc, SCSrc_b32:{ *:[i32] }:$soffset, (timm:{ *:[i32] }):$offset, (extract_cpol:{ *:[i32] } ?:{ *:[i32] }:$auxiliary))
        GIR_BuildMI, /*InsnID*/0, /*Opcode*/GIMT_Encode2(AMDGPU::BUFFER_ATOMIC_SWAP_X2_VBUFFER_OFFEN),
        GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/1, // vdata_in
        GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/4, // voffset
        GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/2, // rsrc
        GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/0, // soffset
        GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/6, // offset
        GIR_CustomOperandRenderer, /*InsnID*/0, /*OldInsnID*/0, /*OpIdx*/7, /*OperandRenderer*/GIMT_Encode2(GICR_renderExtractCPol), // auxiliary
        GIR_MergeMemOperands, /*InsnID*/0, /*NumInsns*/1, /*MergeInsnID's*/0,
        GIR_ConstrainSelectedInstOperands, /*InsnID*/0,
        GIR_EraseFromParent, /*InsnID*/0,
        // GIR_Coverage, 4943,
        GIR_Done,
      // Label 6269: @459453
      GIM_Try, /*On fail goto*//*Label 6270*/ GIMT_Encode4(459538), // Rule ID 4931 //
        GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasUnrestrictedSOffset),
        GIM_CheckRegBankForClass, /*MI*/0, /*Op*/0, /*RC*/GIMT_Encode2(AMDGPU::AV_64RegClassID),
        GIM_CheckConstantInt8, /*MI*/0, /*Op*/3, 0,
        // MIs[0] offset
        GIM_CheckIsImm, /*MI*/0, /*Op*/6,
        // MIs[0] auxiliary
        GIM_CheckIsImm, /*MI*/0, /*Op*/7,
        // MIs[0] Operand 8
        GIM_CheckLiteralInt, /*MI*/0, /*Op*/8, GIMT_Encode8(0),
        GIM_CheckComplexPattern, /*MI*/0, /*Op*/5, /*Renderer*/GIMT_Encode2(0), GIMT_Encode2(GICP_gi_buf_soffset),
        // (SIbuffer_atomic_swap:{ *:[i64] } i64:{ *:[i64] }:$vdata_in, v4i32:{ *:[v4i32] }:$rsrc, 0:{ *:[i32] }, i32:{ *:[i32] }:$voffset, (BUFSOffset:{ *:[i32] } i32:{ *:[i32] }:$soffset), (timm:{ *:[i32] }):$offset, (timm:{ *:[i32] }):$auxiliary, 0:{ *:[i1] })  =>  (BUFFER_ATOMIC_SWAP_X2_OFFEN_RTN:{ *:[i64] } anonymous_15036:{ *:[i64] }:$vdata_in, VGPR_32:{ *:[i32] }:$voffset, SReg_128:{ *:[v4i32] }:$rsrc, SCSrc_b32:{ *:[i32] }:$soffset, (timm:{ *:[i32] }):$offset, (extract_cpol_set_glc:{ *:[i32] } ?:{ *:[i32] }:$auxiliary))
        GIR_BuildMI, /*InsnID*/0, /*Opcode*/GIMT_Encode2(AMDGPU::BUFFER_ATOMIC_SWAP_X2_OFFEN_RTN),
        GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/0, // DstI[vdata]
        GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/1, // vdata_in
        GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/4, // voffset
        GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/2, // rsrc
        GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/0, // soffset
        GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/6, // offset
        GIR_CustomOperandRenderer, /*InsnID*/0, /*OldInsnID*/0, /*OpIdx*/7, /*OperandRenderer*/GIMT_Encode2(GICR_renderExtractCpolSetGLC), // auxiliary
        GIR_MergeMemOperands, /*InsnID*/0, /*NumInsns*/1, /*MergeInsnID's*/0,
        GIR_ConstrainSelectedInstOperands, /*InsnID*/0,
        GIR_EraseFromParent, /*InsnID*/0,
        // GIR_Coverage, 4931,
        GIR_Done,
      // Label 6270: @459538
      GIM_Try, /*On fail goto*//*Label 6271*/ GIMT_Encode4(459620), // Rule ID 4939 //
        GIM_CheckRegBankForClass, /*MI*/0, /*Op*/0, /*RC*/GIMT_Encode2(AMDGPU::AV_64RegClassID),
        GIM_CheckConstantInt8, /*MI*/0, /*Op*/3, 0,
        // MIs[0] offset
        GIM_CheckIsImm, /*MI*/0, /*Op*/6,
        // MIs[0] auxiliary
        GIM_CheckIsImm, /*MI*/0, /*Op*/7,
        // MIs[0] Operand 8
        GIM_CheckLiteralInt, /*MI*/0, /*Op*/8, GIMT_Encode8(0),
        GIM_CheckComplexPattern, /*MI*/0, /*Op*/5, /*Renderer*/GIMT_Encode2(0), GIMT_Encode2(GICP_gi_buf_soffset),
        // (SIbuffer_atomic_swap:{ *:[i64] } i64:{ *:[i64] }:$vdata_in, v4i32:{ *:[v4i32] }:$rsrc, 0:{ *:[i32] }, i32:{ *:[i32] }:$voffset, (BUFSOffset:{ *:[i32] } i32:{ *:[i32] }:$soffset), (timm:{ *:[i32] }):$offset, (timm:{ *:[i32] }):$auxiliary, 0:{ *:[i1] })  =>  (BUFFER_ATOMIC_SWAP_X2_VBUFFER_OFFEN_RTN:{ *:[i64] } anonymous_15036:{ *:[i64] }:$vdata_in, VGPR_32:{ *:[i32] }:$voffset, SReg_128:{ *:[v4i32] }:$rsrc, SCSrc_b32:{ *:[i32] }:$soffset, (timm:{ *:[i32] }):$offset, (extract_cpol_set_glc:{ *:[i32] } ?:{ *:[i32] }:$auxiliary))
        GIR_BuildMI, /*InsnID*/0, /*Opcode*/GIMT_Encode2(AMDGPU::BUFFER_ATOMIC_SWAP_X2_VBUFFER_OFFEN_RTN),
        GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/0, // DstI[vdata]
        GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/1, // vdata_in
        GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/4, // voffset
        GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/2, // rsrc
        GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/0, // soffset
        GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/6, // offset
        GIR_CustomOperandRenderer, /*InsnID*/0, /*OldInsnID*/0, /*OpIdx*/7, /*OperandRenderer*/GIMT_Encode2(GICR_renderExtractCpolSetGLC), // auxiliary
        GIR_MergeMemOperands, /*InsnID*/0, /*NumInsns*/1, /*MergeInsnID's*/0,
        GIR_ConstrainSelectedInstOperands, /*InsnID*/0,
        GIR_EraseFromParent, /*InsnID*/0,
        // GIR_Coverage, 4939,
        GIR_Done,
      // Label 6271: @459620
      GIM_Try, /*On fail goto*//*Label 6272*/ GIMT_Encode4(459690), // Rule ID 4934 //
        GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasUnrestrictedSOffset),
        GIM_CheckHasNoUse, /*MI*/0,
        GIM_CheckConstantInt8, /*MI*/0, /*Op*/4, 0,
        // MIs[0] offset
        GIM_CheckIsImm, /*MI*/0, /*Op*/6,
        // MIs[0] auxiliary
        GIM_CheckIsImm, /*MI*/0, /*Op*/7,
        // MIs[0] Operand 8
        GIM_CheckIsImm, /*MI*/0, /*Op*/8,
        GIM_CheckComplexPattern, /*MI*/0, /*Op*/5, /*Renderer*/GIMT_Encode2(0), GIMT_Encode2(GICP_gi_buf_soffset),
        // (SIbuffer_atomic_swap:{ *:[i64] } i64:{ *:[i64] }:$vdata_in, v4i32:{ *:[v4i32] }:$rsrc, i32:{ *:[i32] }:$vindex, 0:{ *:[i32] }, (BUFSOffset:{ *:[i32] } i32:{ *:[i32] }:$soffset), (timm:{ *:[i32] }):$offset, (timm:{ *:[i32] }):$auxiliary, (timm:{ *:[i1] }))<<P:Predicate_SIbuffer_atomic_swap_noret>>  =>  (BUFFER_ATOMIC_SWAP_X2_IDXEN anonymous_15036:{ *:[i64] }:$vdata_in, VGPR_32:{ *:[i32] }:$vindex, SReg_128:{ *:[v4i32] }:$rsrc, SCSrc_b32:{ *:[i32] }:$soffset, (timm:{ *:[i32] }):$offset, (extract_cpol:{ *:[i32] } ?:{ *:[i32] }:$auxiliary))
        GIR_BuildMI, /*InsnID*/0, /*Opcode*/GIMT_Encode2(AMDGPU::BUFFER_ATOMIC_SWAP_X2_IDXEN),
        GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/1, // vdata_in
        GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/3, // vindex
        GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/2, // rsrc
        GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/0, // soffset
        GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/6, // offset
        GIR_CustomOperandRenderer, /*InsnID*/0, /*OldInsnID*/0, /*OpIdx*/7, /*OperandRenderer*/GIMT_Encode2(GICR_renderExtractCPol), // auxiliary
        GIR_MergeMemOperands, /*InsnID*/0, /*NumInsns*/1, /*MergeInsnID's*/0,
        GIR_ConstrainSelectedInstOperands, /*InsnID*/0,
        GIR_EraseFromParent, /*InsnID*/0,
        // GIR_Coverage, 4934,
        GIR_Done,
      // Label 6272: @459690
      GIM_Try, /*On fail goto*//*Label 6273*/ GIMT_Encode4(459757), // Rule ID 4942 //
        GIM_CheckHasNoUse, /*MI*/0,
        GIM_CheckConstantInt8, /*MI*/0, /*Op*/4, 0,
        // MIs[0] offset
        GIM_CheckIsImm, /*MI*/0, /*Op*/6,
        // MIs[0] auxiliary
        GIM_CheckIsImm, /*MI*/0, /*Op*/7,
        // MIs[0] Operand 8
        GIM_CheckIsImm, /*MI*/0, /*Op*/8,
        GIM_CheckComplexPattern, /*MI*/0, /*Op*/5, /*Renderer*/GIMT_Encode2(0), GIMT_Encode2(GICP_gi_buf_soffset),
        // (SIbuffer_atomic_swap:{ *:[i64] } i64:{ *:[i64] }:$vdata_in, v4i32:{ *:[v4i32] }:$rsrc, i32:{ *:[i32] }:$vindex, 0:{ *:[i32] }, (BUFSOffset:{ *:[i32] } i32:{ *:[i32] }:$soffset), (timm:{ *:[i32] }):$offset, (timm:{ *:[i32] }):$auxiliary, (timm:{ *:[i1] }))<<P:Predicate_SIbuffer_atomic_swap_noret>>  =>  (BUFFER_ATOMIC_SWAP_X2_VBUFFER_IDXEN anonymous_15036:{ *:[i64] }:$vdata_in, VGPR_32:{ *:[i32] }:$vindex, SReg_128:{ *:[v4i32] }:$rsrc, SCSrc_b32:{ *:[i32] }:$soffset, (timm:{ *:[i32] }):$offset, (extract_cpol:{ *:[i32] } ?:{ *:[i32] }:$auxiliary))
        GIR_BuildMI, /*InsnID*/0, /*Opcode*/GIMT_Encode2(AMDGPU::BUFFER_ATOMIC_SWAP_X2_VBUFFER_IDXEN),
        GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/1, // vdata_in
        GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/3, // vindex
        GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/2, // rsrc
        GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/0, // soffset
        GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/6, // offset
        GIR_CustomOperandRenderer, /*InsnID*/0, /*OldInsnID*/0, /*OpIdx*/7, /*OperandRenderer*/GIMT_Encode2(GICR_renderExtractCPol), // auxiliary
        GIR_MergeMemOperands, /*InsnID*/0, /*NumInsns*/1, /*MergeInsnID's*/0,
        GIR_ConstrainSelectedInstOperands, /*InsnID*/0,
        GIR_EraseFromParent, /*InsnID*/0,
        // GIR_Coverage, 4942,
        GIR_Done,
      // Label 6273: @459757
      GIM_Try, /*On fail goto*//*Label 6274*/ GIMT_Encode4(459834), // Rule ID 4930 //
        GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasUnrestrictedSOffset),
        GIM_CheckRegBankForClass, /*MI*/0, /*Op*/0, /*RC*/GIMT_Encode2(AMDGPU::AV_64RegClassID),
        GIM_CheckConstantInt8, /*MI*/0, /*Op*/4, 0,
        // MIs[0] offset
        GIM_CheckIsImm, /*MI*/0, /*Op*/6,
        // MIs[0] auxiliary
        GIM_CheckIsImm, /*MI*/0, /*Op*/7,
        // MIs[0] Operand 8
        GIM_CheckIsImm, /*MI*/0, /*Op*/8,
        GIM_CheckComplexPattern, /*MI*/0, /*Op*/5, /*Renderer*/GIMT_Encode2(0), GIMT_Encode2(GICP_gi_buf_soffset),
        // (SIbuffer_atomic_swap:{ *:[i64] } i64:{ *:[i64] }:$vdata_in, v4i32:{ *:[v4i32] }:$rsrc, i32:{ *:[i32] }:$vindex, 0:{ *:[i32] }, (BUFSOffset:{ *:[i32] } i32:{ *:[i32] }:$soffset), (timm:{ *:[i32] }):$offset, (timm:{ *:[i32] }):$auxiliary, (timm:{ *:[i1] }))  =>  (BUFFER_ATOMIC_SWAP_X2_IDXEN_RTN:{ *:[i64] } anonymous_15036:{ *:[i64] }:$vdata_in, VGPR_32:{ *:[i32] }:$vindex, SReg_128:{ *:[v4i32] }:$rsrc, SCSrc_b32:{ *:[i32] }:$soffset, (timm:{ *:[i32] }):$offset, (extract_cpol_set_glc:{ *:[i32] } ?:{ *:[i32] }:$auxiliary))
        GIR_BuildMI, /*InsnID*/0, /*Opcode*/GIMT_Encode2(AMDGPU::BUFFER_ATOMIC_SWAP_X2_IDXEN_RTN),
        GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/0, // DstI[vdata]
        GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/1, // vdata_in
        GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/3, // vindex
        GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/2, // rsrc
        GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/0, // soffset
        GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/6, // offset
        GIR_CustomOperandRenderer, /*InsnID*/0, /*OldInsnID*/0, /*OpIdx*/7, /*OperandRenderer*/GIMT_Encode2(GICR_renderExtractCpolSetGLC), // auxiliary
        GIR_MergeMemOperands, /*InsnID*/0, /*NumInsns*/1, /*MergeInsnID's*/0,
        GIR_ConstrainSelectedInstOperands, /*InsnID*/0,
        GIR_EraseFromParent, /*InsnID*/0,
        // GIR_Coverage, 4930,
        GIR_Done,
      // Label 6274: @459834
      GIM_Try, /*On fail goto*//*Label 6275*/ GIMT_Encode4(459908), // Rule ID 4938 //
        GIM_CheckRegBankForClass, /*MI*/0, /*Op*/0, /*RC*/GIMT_Encode2(AMDGPU::AV_64RegClassID),
        GIM_CheckConstantInt8, /*MI*/0, /*Op*/4, 0,
        // MIs[0] offset
        GIM_CheckIsImm, /*MI*/0, /*Op*/6,
        // MIs[0] auxiliary
        GIM_CheckIsImm, /*MI*/0, /*Op*/7,
        // MIs[0] Operand 8
        GIM_CheckIsImm, /*MI*/0, /*Op*/8,
        GIM_CheckComplexPattern, /*MI*/0, /*Op*/5, /*Renderer*/GIMT_Encode2(0), GIMT_Encode2(GICP_gi_buf_soffset),
        // (SIbuffer_atomic_swap:{ *:[i64] } i64:{ *:[i64] }:$vdata_in, v4i32:{ *:[v4i32] }:$rsrc, i32:{ *:[i32] }:$vindex, 0:{ *:[i32] }, (BUFSOffset:{ *:[i32] } i32:{ *:[i32] }:$soffset), (timm:{ *:[i32] }):$offset, (timm:{ *:[i32] }):$auxiliary, (timm:{ *:[i1] }))  =>  (BUFFER_ATOMIC_SWAP_X2_VBUFFER_IDXEN_RTN:{ *:[i64] } anonymous_15036:{ *:[i64] }:$vdata_in, VGPR_32:{ *:[i32] }:$vindex, SReg_128:{ *:[v4i32] }:$rsrc, SCSrc_b32:{ *:[i32] }:$soffset, (timm:{ *:[i32] }):$offset, (extract_cpol_set_glc:{ *:[i32] } ?:{ *:[i32] }:$auxiliary))
        GIR_BuildMI, /*InsnID*/0, /*Opcode*/GIMT_Encode2(AMDGPU::BUFFER_ATOMIC_SWAP_X2_VBUFFER_IDXEN_RTN),
        GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/0, // DstI[vdata]
        GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/1, // vdata_in
        GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/3, // vindex
        GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/2, // rsrc
        GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/0, // soffset
        GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/6, // offset
        GIR_CustomOperandRenderer, /*InsnID*/0, /*OldInsnID*/0, /*OpIdx*/7, /*OperandRenderer*/GIMT_Encode2(GICR_renderExtractCpolSetGLC), // auxiliary
        GIR_MergeMemOperands, /*InsnID*/0, /*NumInsns*/1, /*MergeInsnID's*/0,
        GIR_ConstrainSelectedInstOperands, /*InsnID*/0,
        GIR_EraseFromParent, /*InsnID*/0,
        // GIR_Coverage, 4938,
        GIR_Done,
      // Label 6275: @459908
      GIM_Try, /*On fail goto*//*Label 6276*/ GIMT_Encode4(460014), // Rule ID 4936 //
        GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasUnrestrictedSOffset),
        GIM_CheckHasNoUse, /*MI*/0,
        // MIs[0] offset
        GIM_CheckIsImm, /*MI*/0, /*Op*/6,
        // MIs[0] auxiliary
        GIM_CheckIsImm, /*MI*/0, /*Op*/7,
        // MIs[0] Operand 8
        GIM_CheckIsImm, /*MI*/0, /*Op*/8,
        GIM_CheckComplexPattern, /*MI*/0, /*Op*/5, /*Renderer*/GIMT_Encode2(0), GIMT_Encode2(GICP_gi_buf_soffset),
        // (SIbuffer_atomic_swap:{ *:[i64] } i64:{ *:[i64] }:$vdata_in, v4i32:{ *:[v4i32] }:$rsrc, i32:{ *:[i32] }:$vindex, i32:{ *:[i32] }:$voffset, (BUFSOffset:{ *:[i32] } i32:{ *:[i32] }:$soffset), (timm:{ *:[i32] }):$offset, (timm:{ *:[i32] }):$auxiliary, (timm:{ *:[i1] }))<<P:Predicate_SIbuffer_atomic_swap_noret>>  =>  (BUFFER_ATOMIC_SWAP_X2_BOTHEN anonymous_15036:{ *:[i64] }:$vdata_in, (REG_SEQUENCE:{ *:[i64] } VReg_64:{ *:[i32] }, VGPR_32:{ *:[i32] }:$vindex, sub0:{ *:[i32] }, VGPR_32:{ *:[i32] }:$voffset, sub1:{ *:[i32] }), SReg_128:{ *:[v4i32] }:$rsrc, SCSrc_b32:{ *:[i32] }:$soffset, (timm:{ *:[i32] }):$offset, (extract_cpol:{ *:[i32] } ?:{ *:[i32] }:$auxiliary))
        GIR_MakeTempReg, /*TempRegID*/0, /*TypeID*/GILLT_s64,
        GIR_BuildMI, /*InsnID*/1, /*Opcode*/GIMT_Encode2(TargetOpcode::REG_SEQUENCE),
        GIR_AddTempRegister, /*InsnID*/1, /*TempRegID*/0, /*TempRegFlags*/GIMT_Encode2(RegState::Define),
        GIR_Copy, /*NewInsnID*/1, /*OldInsnID*/0, /*OpIdx*/3, // vindex
        GIR_AddImm8, /*InsnID*/1, /*SubRegIndex*/3,
        GIR_Copy, /*NewInsnID*/1, /*OldInsnID*/0, /*OpIdx*/4, // voffset
        GIR_AddImm8, /*InsnID*/1, /*SubRegIndex*/11,
        GIR_ConstrainOperandRC, /*InsnID*/1, /*Op*/0, GIMT_Encode2(AMDGPU::VReg_64RegClassID),
        GIR_ConstrainOperandRC, /*InsnID*/1, /*Op*/1, GIMT_Encode2(AMDGPU::VGPR_32RegClassID),
        GIR_ConstrainOperandRC, /*InsnID*/1, /*Op*/3, GIMT_Encode2(AMDGPU::VGPR_32RegClassID),
        GIR_BuildMI, /*InsnID*/0, /*Opcode*/GIMT_Encode2(AMDGPU::BUFFER_ATOMIC_SWAP_X2_BOTHEN),
        GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/1, // vdata_in
        GIR_AddSimpleTempRegister, /*InsnID*/0, /*TempRegID*/0,
        GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/2, // rsrc
        GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/0, // soffset
        GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/6, // offset
        GIR_CustomOperandRenderer, /*InsnID*/0, /*OldInsnID*/0, /*OpIdx*/7, /*OperandRenderer*/GIMT_Encode2(GICR_renderExtractCPol), // auxiliary
        GIR_MergeMemOperands, /*InsnID*/0, /*NumInsns*/1, /*MergeInsnID's*/0,
        GIR_ConstrainSelectedInstOperands, /*InsnID*/0,
        GIR_EraseFromParent, /*InsnID*/0,
        // GIR_Coverage, 4936,
        GIR_Done,
      // Label 6276: @460014
      GIM_Try, /*On fail goto*//*Label 6277*/ GIMT_Encode4(460117), // Rule ID 4944 //
        GIM_CheckHasNoUse, /*MI*/0,
        // MIs[0] offset
        GIM_CheckIsImm, /*MI*/0, /*Op*/6,
        // MIs[0] auxiliary
        GIM_CheckIsImm, /*MI*/0, /*Op*/7,
        // MIs[0] Operand 8
        GIM_CheckIsImm, /*MI*/0, /*Op*/8,
        GIM_CheckComplexPattern, /*MI*/0, /*Op*/5, /*Renderer*/GIMT_Encode2(0), GIMT_Encode2(GICP_gi_buf_soffset),
        // (SIbuffer_atomic_swap:{ *:[i64] } i64:{ *:[i64] }:$vdata_in, v4i32:{ *:[v4i32] }:$rsrc, i32:{ *:[i32] }:$vindex, i32:{ *:[i32] }:$voffset, (BUFSOffset:{ *:[i32] } i32:{ *:[i32] }:$soffset), (timm:{ *:[i32] }):$offset, (timm:{ *:[i32] }):$auxiliary, (timm:{ *:[i1] }))<<P:Predicate_SIbuffer_atomic_swap_noret>>  =>  (BUFFER_ATOMIC_SWAP_X2_VBUFFER_BOTHEN anonymous_15036:{ *:[i64] }:$vdata_in, (REG_SEQUENCE:{ *:[i64] } VReg_64:{ *:[i32] }, VGPR_32:{ *:[i32] }:$vindex, sub0:{ *:[i32] }, VGPR_32:{ *:[i32] }:$voffset, sub1:{ *:[i32] }), SReg_128:{ *:[v4i32] }:$rsrc, SCSrc_b32:{ *:[i32] }:$soffset, (timm:{ *:[i32] }):$offset, (extract_cpol:{ *:[i32] } ?:{ *:[i32] }:$auxiliary))
        GIR_MakeTempReg, /*TempRegID*/0, /*TypeID*/GILLT_s64,
        GIR_BuildMI, /*InsnID*/1, /*Opcode*/GIMT_Encode2(TargetOpcode::REG_SEQUENCE),
        GIR_AddTempRegister, /*InsnID*/1, /*TempRegID*/0, /*TempRegFlags*/GIMT_Encode2(RegState::Define),
        GIR_Copy, /*NewInsnID*/1, /*OldInsnID*/0, /*OpIdx*/3, // vindex
        GIR_AddImm8, /*InsnID*/1, /*SubRegIndex*/3,
        GIR_Copy, /*NewInsnID*/1, /*OldInsnID*/0, /*OpIdx*/4, // voffset
        GIR_AddImm8, /*InsnID*/1, /*SubRegIndex*/11,
        GIR_ConstrainOperandRC, /*InsnID*/1, /*Op*/0, GIMT_Encode2(AMDGPU::VReg_64RegClassID),
        GIR_ConstrainOperandRC, /*InsnID*/1, /*Op*/1, GIMT_Encode2(AMDGPU::VGPR_32RegClassID),
        GIR_ConstrainOperandRC, /*InsnID*/1, /*Op*/3, GIMT_Encode2(AMDGPU::VGPR_32RegClassID),
        GIR_BuildMI, /*InsnID*/0, /*Opcode*/GIMT_Encode2(AMDGPU::BUFFER_ATOMIC_SWAP_X2_VBUFFER_BOTHEN),
        GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/1, // vdata_in
        GIR_AddSimpleTempRegister, /*InsnID*/0, /*TempRegID*/0,
        GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/2, // rsrc
        GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/0, // soffset
        GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/6, // offset
        GIR_CustomOperandRenderer, /*InsnID*/0, /*OldInsnID*/0, /*OpIdx*/7, /*OperandRenderer*/GIMT_Encode2(GICR_renderExtractCPol), // auxiliary
        GIR_MergeMemOperands, /*InsnID*/0, /*NumInsns*/1, /*MergeInsnID's*/0,
        GIR_ConstrainSelectedInstOperands, /*InsnID*/0,
        GIR_EraseFromParent, /*InsnID*/0,
        // GIR_Coverage, 4944,
        GIR_Done,
      // Label 6277: @460117
      GIM_Try, /*On fail goto*//*Label 6278*/ GIMT_Encode4(460230), // Rule ID 4932 //
        GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasUnrestrictedSOffset),
        GIM_CheckRegBankForClass, /*MI*/0, /*Op*/0, /*RC*/GIMT_Encode2(AMDGPU::AV_64RegClassID),
        // MIs[0] offset
        GIM_CheckIsImm, /*MI*/0, /*Op*/6,
        // MIs[0] auxiliary
        GIM_CheckIsImm, /*MI*/0, /*Op*/7,
        // MIs[0] Operand 8
        GIM_CheckIsImm, /*MI*/0, /*Op*/8,
        GIM_CheckComplexPattern, /*MI*/0, /*Op*/5, /*Renderer*/GIMT_Encode2(0), GIMT_Encode2(GICP_gi_buf_soffset),
        // (SIbuffer_atomic_swap:{ *:[i64] } i64:{ *:[i64] }:$vdata_in, v4i32:{ *:[v4i32] }:$rsrc, i32:{ *:[i32] }:$vindex, i32:{ *:[i32] }:$voffset, (BUFSOffset:{ *:[i32] } i32:{ *:[i32] }:$soffset), (timm:{ *:[i32] }):$offset, (timm:{ *:[i32] }):$auxiliary, (timm:{ *:[i1] }))  =>  (BUFFER_ATOMIC_SWAP_X2_BOTHEN_RTN:{ *:[i64] } anonymous_15036:{ *:[i64] }:$vdata_in, (REG_SEQUENCE:{ *:[i64] } VReg_64:{ *:[i32] }, VGPR_32:{ *:[i32] }:$vindex, sub0:{ *:[i32] }, VGPR_32:{ *:[i32] }:$voffset, sub1:{ *:[i32] }), SReg_128:{ *:[v4i32] }:$rsrc, SCSrc_b32:{ *:[i32] }:$soffset, (timm:{ *:[i32] }):$offset, (extract_cpol_set_glc:{ *:[i32] } ?:{ *:[i32] }:$auxiliary))
        GIR_MakeTempReg, /*TempRegID*/0, /*TypeID*/GILLT_s64,
        GIR_BuildMI, /*InsnID*/1, /*Opcode*/GIMT_Encode2(TargetOpcode::REG_SEQUENCE),
        GIR_AddTempRegister, /*InsnID*/1, /*TempRegID*/0, /*TempRegFlags*/GIMT_Encode2(RegState::Define),
        GIR_Copy, /*NewInsnID*/1, /*OldInsnID*/0, /*OpIdx*/3, // vindex
        GIR_AddImm8, /*InsnID*/1, /*SubRegIndex*/3,
        GIR_Copy, /*NewInsnID*/1, /*OldInsnID*/0, /*OpIdx*/4, // voffset
        GIR_AddImm8, /*InsnID*/1, /*SubRegIndex*/11,
        GIR_ConstrainOperandRC, /*InsnID*/1, /*Op*/0, GIMT_Encode2(AMDGPU::VReg_64RegClassID),
        GIR_ConstrainOperandRC, /*InsnID*/1, /*Op*/1, GIMT_Encode2(AMDGPU::VGPR_32RegClassID),
        GIR_ConstrainOperandRC, /*InsnID*/1, /*Op*/3, GIMT_Encode2(AMDGPU::VGPR_32RegClassID),
        GIR_BuildMI, /*InsnID*/0, /*Opcode*/GIMT_Encode2(AMDGPU::BUFFER_ATOMIC_SWAP_X2_BOTHEN_RTN),
        GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/0, // DstI[vdata]
        GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/1, // vdata_in
        GIR_AddSimpleTempRegister, /*InsnID*/0, /*TempRegID*/0,
        GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/2, // rsrc
        GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/0, // soffset
        GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/6, // offset
        GIR_CustomOperandRenderer, /*InsnID*/0, /*OldInsnID*/0, /*OpIdx*/7, /*OperandRenderer*/GIMT_Encode2(GICR_renderExtractCpolSetGLC), // auxiliary
        GIR_MergeMemOperands, /*InsnID*/0, /*NumInsns*/1, /*MergeInsnID's*/0,
        GIR_ConstrainSelectedInstOperands, /*InsnID*/0,
        GIR_EraseFromParent, /*InsnID*/0,
        // GIR_Coverage, 4932,
        GIR_Done,
      // Label 6278: @460230
      GIM_Try, /*On fail goto*//*Label 6279*/ GIMT_Encode4(460340), // Rule ID 4940 //
        GIM_CheckRegBankForClass, /*MI*/0, /*Op*/0, /*RC*/GIMT_Encode2(AMDGPU::AV_64RegClassID),
        // MIs[0] offset
        GIM_CheckIsImm, /*MI*/0, /*Op*/6,
        // MIs[0] auxiliary
        GIM_CheckIsImm, /*MI*/0, /*Op*/7,
        // MIs[0] Operand 8
        GIM_CheckIsImm, /*MI*/0, /*Op*/8,
        GIM_CheckComplexPattern, /*MI*/0, /*Op*/5, /*Renderer*/GIMT_Encode2(0), GIMT_Encode2(GICP_gi_buf_soffset),
        // (SIbuffer_atomic_swap:{ *:[i64] } i64:{ *:[i64] }:$vdata_in, v4i32:{ *:[v4i32] }:$rsrc, i32:{ *:[i32] }:$vindex, i32:{ *:[i32] }:$voffset, (BUFSOffset:{ *:[i32] } i32:{ *:[i32] }:$soffset), (timm:{ *:[i32] }):$offset, (timm:{ *:[i32] }):$auxiliary, (timm:{ *:[i1] }))  =>  (BUFFER_ATOMIC_SWAP_X2_VBUFFER_BOTHEN_RTN:{ *:[i64] } anonymous_15036:{ *:[i64] }:$vdata_in, (REG_SEQUENCE:{ *:[i64] } VReg_64:{ *:[i32] }, VGPR_32:{ *:[i32] }:$vindex, sub0:{ *:[i32] }, VGPR_32:{ *:[i32] }:$voffset, sub1:{ *:[i32] }), SReg_128:{ *:[v4i32] }:$rsrc, SCSrc_b32:{ *:[i32] }:$soffset, (timm:{ *:[i32] }):$offset, (extract_cpol_set_glc:{ *:[i32] } ?:{ *:[i32] }:$auxiliary))
        GIR_MakeTempReg, /*TempRegID*/0, /*TypeID*/GILLT_s64,
        GIR_BuildMI, /*InsnID*/1, /*Opcode*/GIMT_Encode2(TargetOpcode::REG_SEQUENCE),
        GIR_AddTempRegister, /*InsnID*/1, /*TempRegID*/0, /*TempRegFlags*/GIMT_Encode2(RegState::Define),
        GIR_Copy, /*NewInsnID*/1, /*OldInsnID*/0, /*OpIdx*/3, // vindex
        GIR_AddImm8, /*InsnID*/1, /*SubRegIndex*/3,
        GIR_Copy, /*NewInsnID*/1, /*OldInsnID*/0, /*OpIdx*/4, // voffset
        GIR_AddImm8, /*InsnID*/1, /*SubRegIndex*/11,
        GIR_ConstrainOperandRC, /*InsnID*/1, /*Op*/0, GIMT_Encode2(AMDGPU::VReg_64RegClassID),
        GIR_ConstrainOperandRC, /*InsnID*/1, /*Op*/1, GIMT_Encode2(AMDGPU::VGPR_32RegClassID),
        GIR_ConstrainOperandRC, /*InsnID*/1, /*Op*/3, GIMT_Encode2(AMDGPU::VGPR_32RegClassID),
        GIR_BuildMI, /*InsnID*/0, /*Opcode*/GIMT_Encode2(AMDGPU::BUFFER_ATOMIC_SWAP_X2_VBUFFER_BOTHEN_RTN),
        GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/0, // DstI[vdata]
        GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/1, // vdata_in
        GIR_AddSimpleTempRegister, /*InsnID*/0, /*TempRegID*/0,
        GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/2, // rsrc
        GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/0, // soffset
        GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/6, // offset
        GIR_CustomOperandRenderer, /*InsnID*/0, /*OldInsnID*/0, /*OpIdx*/7, /*OperandRenderer*/GIMT_Encode2(GICR_renderExtractCpolSetGLC), // auxiliary
        GIR_MergeMemOperands, /*InsnID*/0, /*NumInsns*/1, /*MergeInsnID's*/0,
        GIR_ConstrainSelectedInstOperands, /*InsnID*/0,
        GIR_EraseFromParent, /*InsnID*/0,
        // GIR_Coverage, 4940,
        GIR_Done,
      // Label 6279: @460340
      GIM_Reject,
    // Label 6263: @460341
    GIM_Reject,
    // Label 6229: @460342
    GIM_Reject,
    // Label 121: @460343
    GIM_SwitchType, /*MI*/0, /*Op*/0, /*[*/GIMT_Encode2(9), GIMT_Encode2(11), /*)*//*default:*//*Label 6282*/ GIMT_Encode4(463136),
    /*GILLT_s32*//*Label 6280*/ GIMT_Encode4(460362),
    /*GILLT_s64*//*Label 6281*/ GIMT_Encode4(461749),
    // Label 6280: @460362
    GIM_Try, /*On fail goto*//*Label 6283*/ GIMT_Encode4(461748),
      GIM_CheckType, /*MI*/0, /*Op*/1, /*Type*/GILLT_s32,
      GIM_CheckType, /*MI*/0, /*Op*/2, /*Type*/GILLT_v4s32,
      GIM_CheckType, /*MI*/0, /*Op*/3, /*Type*/GILLT_s32,
      GIM_CheckType, /*MI*/0, /*Op*/4, /*Type*/GILLT_s32,
      GIM_CheckType, /*MI*/0, /*Op*/5, /*Type*/GILLT_s32,
      GIM_Try, /*On fail goto*//*Label 6284*/ GIMT_Encode4(460465), // Rule ID 4829 //
        GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasUnrestrictedSOffset),
        GIM_CheckHasNoUse, /*MI*/0,
        GIM_CheckConstantInt8, /*MI*/0, /*Op*/3, 0,
        GIM_CheckConstantInt8, /*MI*/0, /*Op*/4, 0,
        // MIs[0] offset
        GIM_CheckIsImm, /*MI*/0, /*Op*/6,
        // MIs[0] auxiliary
        GIM_CheckIsImm, /*MI*/0, /*Op*/7,
        // MIs[0] Operand 8
        GIM_CheckLiteralInt, /*MI*/0, /*Op*/8, GIMT_Encode8(0),
        GIM_CheckComplexPattern, /*MI*/0, /*Op*/5, /*Renderer*/GIMT_Encode2(0), GIMT_Encode2(GICP_gi_buf_soffset),
        // (SIbuffer_atomic_umax:{ *:[i32] } i32:{ *:[i32] }:$vdata_in, v4i32:{ *:[v4i32] }:$rsrc, 0:{ *:[i32] }, 0:{ *:[i32] }, (BUFSOffset:{ *:[i32] } i32:{ *:[i32] }:$soffset), (timm:{ *:[i32] }):$offset, (timm:{ *:[i32] }):$auxiliary, 0:{ *:[i1] })<<P:Predicate_SIbuffer_atomic_umax_noret>>  =>  (BUFFER_ATOMIC_UMAX_OFFSET anonymous_15037:{ *:[i32] }:$vdata_in, SReg_128:{ *:[v4i32] }:$rsrc, SCSrc_b32:{ *:[i32] }:$soffset, (timm:{ *:[i32] }):$offset, (extract_cpol:{ *:[i32] } ?:{ *:[i32] }:$auxiliary))
        GIR_BuildMI, /*InsnID*/0, /*Opcode*/GIMT_Encode2(AMDGPU::BUFFER_ATOMIC_UMAX_OFFSET),
        GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/1, // vdata_in
        GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/2, // rsrc
        GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/0, // soffset
        GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/6, // offset
        GIR_CustomOperandRenderer, /*InsnID*/0, /*OldInsnID*/0, /*OpIdx*/7, /*OperandRenderer*/GIMT_Encode2(GICR_renderExtractCPol), // auxiliary
        GIR_MergeMemOperands, /*InsnID*/0, /*NumInsns*/1, /*MergeInsnID's*/0,
        GIR_ConstrainSelectedInstOperands, /*InsnID*/0,
        GIR_EraseFromParent, /*InsnID*/0,
        // GIR_Coverage, 4829,
        GIR_Done,
      // Label 6284: @460465
      GIM_Try, /*On fail goto*//*Label 6285*/ GIMT_Encode4(460540), // Rule ID 4837 //
        GIM_CheckHasNoUse, /*MI*/0,
        GIM_CheckConstantInt8, /*MI*/0, /*Op*/3, 0,
        GIM_CheckConstantInt8, /*MI*/0, /*Op*/4, 0,
        // MIs[0] offset
        GIM_CheckIsImm, /*MI*/0, /*Op*/6,
        // MIs[0] auxiliary
        GIM_CheckIsImm, /*MI*/0, /*Op*/7,
        // MIs[0] Operand 8
        GIM_CheckLiteralInt, /*MI*/0, /*Op*/8, GIMT_Encode8(0),
        GIM_CheckComplexPattern, /*MI*/0, /*Op*/5, /*Renderer*/GIMT_Encode2(0), GIMT_Encode2(GICP_gi_buf_soffset),
        // (SIbuffer_atomic_umax:{ *:[i32] } i32:{ *:[i32] }:$vdata_in, v4i32:{ *:[v4i32] }:$rsrc, 0:{ *:[i32] }, 0:{ *:[i32] }, (BUFSOffset:{ *:[i32] } i32:{ *:[i32] }:$soffset), (timm:{ *:[i32] }):$offset, (timm:{ *:[i32] }):$auxiliary, 0:{ *:[i1] })<<P:Predicate_SIbuffer_atomic_umax_noret>>  =>  (BUFFER_ATOMIC_UMAX_VBUFFER_OFFSET anonymous_15037:{ *:[i32] }:$vdata_in, SReg_128:{ *:[v4i32] }:$rsrc, SCSrc_b32:{ *:[i32] }:$soffset, (timm:{ *:[i32] }):$offset, (extract_cpol:{ *:[i32] } ?:{ *:[i32] }:$auxiliary))
        GIR_BuildMI, /*InsnID*/0, /*Opcode*/GIMT_Encode2(AMDGPU::BUFFER_ATOMIC_UMAX_VBUFFER_OFFSET),
        GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/1, // vdata_in
        GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/2, // rsrc
        GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/0, // soffset
        GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/6, // offset
        GIR_CustomOperandRenderer, /*InsnID*/0, /*OldInsnID*/0, /*OpIdx*/7, /*OperandRenderer*/GIMT_Encode2(GICR_renderExtractCPol), // auxiliary
        GIR_MergeMemOperands, /*InsnID*/0, /*NumInsns*/1, /*MergeInsnID's*/0,
        GIR_ConstrainSelectedInstOperands, /*InsnID*/0,
        GIR_EraseFromParent, /*InsnID*/0,
        // GIR_Coverage, 4837,
        GIR_Done,
      // Label 6285: @460540
      GIM_Try, /*On fail goto*//*Label 6286*/ GIMT_Encode4(460625), // Rule ID 4825 //
        GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasUnrestrictedSOffset),
        GIM_CheckRegBankForClass, /*MI*/0, /*Op*/0, /*RC*/GIMT_Encode2(AMDGPU::AV_32RegClassID),
        GIM_CheckConstantInt8, /*MI*/0, /*Op*/3, 0,
        GIM_CheckConstantInt8, /*MI*/0, /*Op*/4, 0,
        // MIs[0] offset
        GIM_CheckIsImm, /*MI*/0, /*Op*/6,
        // MIs[0] auxiliary
        GIM_CheckIsImm, /*MI*/0, /*Op*/7,
        // MIs[0] Operand 8
        GIM_CheckLiteralInt, /*MI*/0, /*Op*/8, GIMT_Encode8(0),
        GIM_CheckComplexPattern, /*MI*/0, /*Op*/5, /*Renderer*/GIMT_Encode2(0), GIMT_Encode2(GICP_gi_buf_soffset),
        // (SIbuffer_atomic_umax:{ *:[i32] } i32:{ *:[i32] }:$vdata_in, v4i32:{ *:[v4i32] }:$rsrc, 0:{ *:[i32] }, 0:{ *:[i32] }, (BUFSOffset:{ *:[i32] } i32:{ *:[i32] }:$soffset), (timm:{ *:[i32] }):$offset, (timm:{ *:[i32] }):$auxiliary, 0:{ *:[i1] })  =>  (BUFFER_ATOMIC_UMAX_OFFSET_RTN:{ *:[i32] } anonymous_15037:{ *:[i32] }:$vdata_in, SReg_128:{ *:[v4i32] }:$rsrc, SCSrc_b32:{ *:[i32] }:$soffset, (timm:{ *:[i32] }):$offset, (extract_cpol_set_glc:{ *:[i32] } ?:{ *:[i32] }:$auxiliary))
        GIR_BuildMI, /*InsnID*/0, /*Opcode*/GIMT_Encode2(AMDGPU::BUFFER_ATOMIC_UMAX_OFFSET_RTN),
        GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/0, // DstI[vdata]
        GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/1, // vdata_in
        GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/2, // rsrc
        GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/0, // soffset
        GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/6, // offset
        GIR_CustomOperandRenderer, /*InsnID*/0, /*OldInsnID*/0, /*OpIdx*/7, /*OperandRenderer*/GIMT_Encode2(GICR_renderExtractCpolSetGLC), // auxiliary
        GIR_MergeMemOperands, /*InsnID*/0, /*NumInsns*/1, /*MergeInsnID's*/0,
        GIR_ConstrainSelectedInstOperands, /*InsnID*/0,
        GIR_EraseFromParent, /*InsnID*/0,
        // GIR_Coverage, 4825,
        GIR_Done,
      // Label 6286: @460625
      GIM_Try, /*On fail goto*//*Label 6287*/ GIMT_Encode4(460707), // Rule ID 4833 //
        GIM_CheckRegBankForClass, /*MI*/0, /*Op*/0, /*RC*/GIMT_Encode2(AMDGPU::AV_32RegClassID),
        GIM_CheckConstantInt8, /*MI*/0, /*Op*/3, 0,
        GIM_CheckConstantInt8, /*MI*/0, /*Op*/4, 0,
        // MIs[0] offset
        GIM_CheckIsImm, /*MI*/0, /*Op*/6,
        // MIs[0] auxiliary
        GIM_CheckIsImm, /*MI*/0, /*Op*/7,
        // MIs[0] Operand 8
        GIM_CheckLiteralInt, /*MI*/0, /*Op*/8, GIMT_Encode8(0),
        GIM_CheckComplexPattern, /*MI*/0, /*Op*/5, /*Renderer*/GIMT_Encode2(0), GIMT_Encode2(GICP_gi_buf_soffset),
        // (SIbuffer_atomic_umax:{ *:[i32] } i32:{ *:[i32] }:$vdata_in, v4i32:{ *:[v4i32] }:$rsrc, 0:{ *:[i32] }, 0:{ *:[i32] }, (BUFSOffset:{ *:[i32] } i32:{ *:[i32] }:$soffset), (timm:{ *:[i32] }):$offset, (timm:{ *:[i32] }):$auxiliary, 0:{ *:[i1] })  =>  (BUFFER_ATOMIC_UMAX_VBUFFER_OFFSET_RTN:{ *:[i32] } anonymous_15037:{ *:[i32] }:$vdata_in, SReg_128:{ *:[v4i32] }:$rsrc, SCSrc_b32:{ *:[i32] }:$soffset, (timm:{ *:[i32] }):$offset, (extract_cpol_set_glc:{ *:[i32] } ?:{ *:[i32] }:$auxiliary))
        GIR_BuildMI, /*InsnID*/0, /*Opcode*/GIMT_Encode2(AMDGPU::BUFFER_ATOMIC_UMAX_VBUFFER_OFFSET_RTN),
        GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/0, // DstI[vdata]
        GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/1, // vdata_in
        GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/2, // rsrc
        GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/0, // soffset
        GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/6, // offset
        GIR_CustomOperandRenderer, /*InsnID*/0, /*OldInsnID*/0, /*OpIdx*/7, /*OperandRenderer*/GIMT_Encode2(GICR_renderExtractCpolSetGLC), // auxiliary
        GIR_MergeMemOperands, /*InsnID*/0, /*NumInsns*/1, /*MergeInsnID's*/0,
        GIR_ConstrainSelectedInstOperands, /*InsnID*/0,
        GIR_EraseFromParent, /*InsnID*/0,
        // GIR_Coverage, 4833,
        GIR_Done,
      // Label 6287: @460707
      GIM_Try, /*On fail goto*//*Label 6288*/ GIMT_Encode4(460785), // Rule ID 4831 //
        GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasUnrestrictedSOffset),
        GIM_CheckHasNoUse, /*MI*/0,
        GIM_CheckConstantInt8, /*MI*/0, /*Op*/3, 0,
        // MIs[0] offset
        GIM_CheckIsImm, /*MI*/0, /*Op*/6,
        // MIs[0] auxiliary
        GIM_CheckIsImm, /*MI*/0, /*Op*/7,
        // MIs[0] Operand 8
        GIM_CheckLiteralInt, /*MI*/0, /*Op*/8, GIMT_Encode8(0),
        GIM_CheckComplexPattern, /*MI*/0, /*Op*/5, /*Renderer*/GIMT_Encode2(0), GIMT_Encode2(GICP_gi_buf_soffset),
        // (SIbuffer_atomic_umax:{ *:[i32] } i32:{ *:[i32] }:$vdata_in, v4i32:{ *:[v4i32] }:$rsrc, 0:{ *:[i32] }, i32:{ *:[i32] }:$voffset, (BUFSOffset:{ *:[i32] } i32:{ *:[i32] }:$soffset), (timm:{ *:[i32] }):$offset, (timm:{ *:[i32] }):$auxiliary, 0:{ *:[i1] })<<P:Predicate_SIbuffer_atomic_umax_noret>>  =>  (BUFFER_ATOMIC_UMAX_OFFEN anonymous_15037:{ *:[i32] }:$vdata_in, VGPR_32:{ *:[i32] }:$voffset, SReg_128:{ *:[v4i32] }:$rsrc, SCSrc_b32:{ *:[i32] }:$soffset, (timm:{ *:[i32] }):$offset, (extract_cpol:{ *:[i32] } ?:{ *:[i32] }:$auxiliary))
        GIR_BuildMI, /*InsnID*/0, /*Opcode*/GIMT_Encode2(AMDGPU::BUFFER_ATOMIC_UMAX_OFFEN),
        GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/1, // vdata_in
        GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/4, // voffset
        GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/2, // rsrc
        GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/0, // soffset
        GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/6, // offset
        GIR_CustomOperandRenderer, /*InsnID*/0, /*OldInsnID*/0, /*OpIdx*/7, /*OperandRenderer*/GIMT_Encode2(GICR_renderExtractCPol), // auxiliary
        GIR_MergeMemOperands, /*InsnID*/0, /*NumInsns*/1, /*MergeInsnID's*/0,
        GIR_ConstrainSelectedInstOperands, /*InsnID*/0,
        GIR_EraseFromParent, /*InsnID*/0,
        // GIR_Coverage, 4831,
        GIR_Done,
      // Label 6288: @460785
      GIM_Try, /*On fail goto*//*Label 6289*/ GIMT_Encode4(460860), // Rule ID 4839 //
        GIM_CheckHasNoUse, /*MI*/0,
        GIM_CheckConstantInt8, /*MI*/0, /*Op*/3, 0,
        // MIs[0] offset
        GIM_CheckIsImm, /*MI*/0, /*Op*/6,
        // MIs[0] auxiliary
        GIM_CheckIsImm, /*MI*/0, /*Op*/7,
        // MIs[0] Operand 8
        GIM_CheckLiteralInt, /*MI*/0, /*Op*/8, GIMT_Encode8(0),
        GIM_CheckComplexPattern, /*MI*/0, /*Op*/5, /*Renderer*/GIMT_Encode2(0), GIMT_Encode2(GICP_gi_buf_soffset),
        // (SIbuffer_atomic_umax:{ *:[i32] } i32:{ *:[i32] }:$vdata_in, v4i32:{ *:[v4i32] }:$rsrc, 0:{ *:[i32] }, i32:{ *:[i32] }:$voffset, (BUFSOffset:{ *:[i32] } i32:{ *:[i32] }:$soffset), (timm:{ *:[i32] }):$offset, (timm:{ *:[i32] }):$auxiliary, 0:{ *:[i1] })<<P:Predicate_SIbuffer_atomic_umax_noret>>  =>  (BUFFER_ATOMIC_UMAX_VBUFFER_OFFEN anonymous_15037:{ *:[i32] }:$vdata_in, VGPR_32:{ *:[i32] }:$voffset, SReg_128:{ *:[v4i32] }:$rsrc, SCSrc_b32:{ *:[i32] }:$soffset, (timm:{ *:[i32] }):$offset, (extract_cpol:{ *:[i32] } ?:{ *:[i32] }:$auxiliary))
        GIR_BuildMI, /*InsnID*/0, /*Opcode*/GIMT_Encode2(AMDGPU::BUFFER_ATOMIC_UMAX_VBUFFER_OFFEN),
        GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/1, // vdata_in
        GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/4, // voffset
        GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/2, // rsrc
        GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/0, // soffset
        GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/6, // offset
        GIR_CustomOperandRenderer, /*InsnID*/0, /*OldInsnID*/0, /*OpIdx*/7, /*OperandRenderer*/GIMT_Encode2(GICR_renderExtractCPol), // auxiliary
        GIR_MergeMemOperands, /*InsnID*/0, /*NumInsns*/1, /*MergeInsnID's*/0,
        GIR_ConstrainSelectedInstOperands, /*InsnID*/0,
        GIR_EraseFromParent, /*InsnID*/0,
        // GIR_Coverage, 4839,
        GIR_Done,
      // Label 6289: @460860
      GIM_Try, /*On fail goto*//*Label 6290*/ GIMT_Encode4(460945), // Rule ID 4827 //
        GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasUnrestrictedSOffset),
        GIM_CheckRegBankForClass, /*MI*/0, /*Op*/0, /*RC*/GIMT_Encode2(AMDGPU::AV_32RegClassID),
        GIM_CheckConstantInt8, /*MI*/0, /*Op*/3, 0,
        // MIs[0] offset
        GIM_CheckIsImm, /*MI*/0, /*Op*/6,
        // MIs[0] auxiliary
        GIM_CheckIsImm, /*MI*/0, /*Op*/7,
        // MIs[0] Operand 8
        GIM_CheckLiteralInt, /*MI*/0, /*Op*/8, GIMT_Encode8(0),
        GIM_CheckComplexPattern, /*MI*/0, /*Op*/5, /*Renderer*/GIMT_Encode2(0), GIMT_Encode2(GICP_gi_buf_soffset),
        // (SIbuffer_atomic_umax:{ *:[i32] } i32:{ *:[i32] }:$vdata_in, v4i32:{ *:[v4i32] }:$rsrc, 0:{ *:[i32] }, i32:{ *:[i32] }:$voffset, (BUFSOffset:{ *:[i32] } i32:{ *:[i32] }:$soffset), (timm:{ *:[i32] }):$offset, (timm:{ *:[i32] }):$auxiliary, 0:{ *:[i1] })  =>  (BUFFER_ATOMIC_UMAX_OFFEN_RTN:{ *:[i32] } anonymous_15037:{ *:[i32] }:$vdata_in, VGPR_32:{ *:[i32] }:$voffset, SReg_128:{ *:[v4i32] }:$rsrc, SCSrc_b32:{ *:[i32] }:$soffset, (timm:{ *:[i32] }):$offset, (extract_cpol_set_glc:{ *:[i32] } ?:{ *:[i32] }:$auxiliary))
        GIR_BuildMI, /*InsnID*/0, /*Opcode*/GIMT_Encode2(AMDGPU::BUFFER_ATOMIC_UMAX_OFFEN_RTN),
        GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/0, // DstI[vdata]
        GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/1, // vdata_in
        GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/4, // voffset
        GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/2, // rsrc
        GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/0, // soffset
        GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/6, // offset
        GIR_CustomOperandRenderer, /*InsnID*/0, /*OldInsnID*/0, /*OpIdx*/7, /*OperandRenderer*/GIMT_Encode2(GICR_renderExtractCpolSetGLC), // auxiliary
        GIR_MergeMemOperands, /*InsnID*/0, /*NumInsns*/1, /*MergeInsnID's*/0,
        GIR_ConstrainSelectedInstOperands, /*InsnID*/0,
        GIR_EraseFromParent, /*InsnID*/0,
        // GIR_Coverage, 4827,
        GIR_Done,
      // Label 6290: @460945
      GIM_Try, /*On fail goto*//*Label 6291*/ GIMT_Encode4(461027), // Rule ID 4835 //
        GIM_CheckRegBankForClass, /*MI*/0, /*Op*/0, /*RC*/GIMT_Encode2(AMDGPU::AV_32RegClassID),
        GIM_CheckConstantInt8, /*MI*/0, /*Op*/3, 0,
        // MIs[0] offset
        GIM_CheckIsImm, /*MI*/0, /*Op*/6,
        // MIs[0] auxiliary
        GIM_CheckIsImm, /*MI*/0, /*Op*/7,
        // MIs[0] Operand 8
        GIM_CheckLiteralInt, /*MI*/0, /*Op*/8, GIMT_Encode8(0),
        GIM_CheckComplexPattern, /*MI*/0, /*Op*/5, /*Renderer*/GIMT_Encode2(0), GIMT_Encode2(GICP_gi_buf_soffset),
        // (SIbuffer_atomic_umax:{ *:[i32] } i32:{ *:[i32] }:$vdata_in, v4i32:{ *:[v4i32] }:$rsrc, 0:{ *:[i32] }, i32:{ *:[i32] }:$voffset, (BUFSOffset:{ *:[i32] } i32:{ *:[i32] }:$soffset), (timm:{ *:[i32] }):$offset, (timm:{ *:[i32] }):$auxiliary, 0:{ *:[i1] })  =>  (BUFFER_ATOMIC_UMAX_VBUFFER_OFFEN_RTN:{ *:[i32] } anonymous_15037:{ *:[i32] }:$vdata_in, VGPR_32:{ *:[i32] }:$voffset, SReg_128:{ *:[v4i32] }:$rsrc, SCSrc_b32:{ *:[i32] }:$soffset, (timm:{ *:[i32] }):$offset, (extract_cpol_set_glc:{ *:[i32] } ?:{ *:[i32] }:$auxiliary))
        GIR_BuildMI, /*InsnID*/0, /*Opcode*/GIMT_Encode2(AMDGPU::BUFFER_ATOMIC_UMAX_VBUFFER_OFFEN_RTN),
        GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/0, // DstI[vdata]
        GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/1, // vdata_in
        GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/4, // voffset
        GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/2, // rsrc
        GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/0, // soffset
        GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/6, // offset
        GIR_CustomOperandRenderer, /*InsnID*/0, /*OldInsnID*/0, /*OpIdx*/7, /*OperandRenderer*/GIMT_Encode2(GICR_renderExtractCpolSetGLC), // auxiliary
        GIR_MergeMemOperands, /*InsnID*/0, /*NumInsns*/1, /*MergeInsnID's*/0,
        GIR_ConstrainSelectedInstOperands, /*InsnID*/0,
        GIR_EraseFromParent, /*InsnID*/0,
        // GIR_Coverage, 4835,
        GIR_Done,
      // Label 6291: @461027
      GIM_Try, /*On fail goto*//*Label 6292*/ GIMT_Encode4(461097), // Rule ID 4830 //
        GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasUnrestrictedSOffset),
        GIM_CheckHasNoUse, /*MI*/0,
        GIM_CheckConstantInt8, /*MI*/0, /*Op*/4, 0,
        // MIs[0] offset
        GIM_CheckIsImm, /*MI*/0, /*Op*/6,
        // MIs[0] auxiliary
        GIM_CheckIsImm, /*MI*/0, /*Op*/7,
        // MIs[0] Operand 8
        GIM_CheckIsImm, /*MI*/0, /*Op*/8,
        GIM_CheckComplexPattern, /*MI*/0, /*Op*/5, /*Renderer*/GIMT_Encode2(0), GIMT_Encode2(GICP_gi_buf_soffset),
        // (SIbuffer_atomic_umax:{ *:[i32] } i32:{ *:[i32] }:$vdata_in, v4i32:{ *:[v4i32] }:$rsrc, i32:{ *:[i32] }:$vindex, 0:{ *:[i32] }, (BUFSOffset:{ *:[i32] } i32:{ *:[i32] }:$soffset), (timm:{ *:[i32] }):$offset, (timm:{ *:[i32] }):$auxiliary, (timm:{ *:[i1] }))<<P:Predicate_SIbuffer_atomic_umax_noret>>  =>  (BUFFER_ATOMIC_UMAX_IDXEN anonymous_15037:{ *:[i32] }:$vdata_in, VGPR_32:{ *:[i32] }:$vindex, SReg_128:{ *:[v4i32] }:$rsrc, SCSrc_b32:{ *:[i32] }:$soffset, (timm:{ *:[i32] }):$offset, (extract_cpol:{ *:[i32] } ?:{ *:[i32] }:$auxiliary))
        GIR_BuildMI, /*InsnID*/0, /*Opcode*/GIMT_Encode2(AMDGPU::BUFFER_ATOMIC_UMAX_IDXEN),
        GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/1, // vdata_in
        GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/3, // vindex
        GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/2, // rsrc
        GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/0, // soffset
        GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/6, // offset
        GIR_CustomOperandRenderer, /*InsnID*/0, /*OldInsnID*/0, /*OpIdx*/7, /*OperandRenderer*/GIMT_Encode2(GICR_renderExtractCPol), // auxiliary
        GIR_MergeMemOperands, /*InsnID*/0, /*NumInsns*/1, /*MergeInsnID's*/0,
        GIR_ConstrainSelectedInstOperands, /*InsnID*/0,
        GIR_EraseFromParent, /*InsnID*/0,
        // GIR_Coverage, 4830,
        GIR_Done,
      // Label 6292: @461097
      GIM_Try, /*On fail goto*//*Label 6293*/ GIMT_Encode4(461164), // Rule ID 4838 //
        GIM_CheckHasNoUse, /*MI*/0,
        GIM_CheckConstantInt8, /*MI*/0, /*Op*/4, 0,
        // MIs[0] offset
        GIM_CheckIsImm, /*MI*/0, /*Op*/6,
        // MIs[0] auxiliary
        GIM_CheckIsImm, /*MI*/0, /*Op*/7,
        // MIs[0] Operand 8
        GIM_CheckIsImm, /*MI*/0, /*Op*/8,
        GIM_CheckComplexPattern, /*MI*/0, /*Op*/5, /*Renderer*/GIMT_Encode2(0), GIMT_Encode2(GICP_gi_buf_soffset),
        // (SIbuffer_atomic_umax:{ *:[i32] } i32:{ *:[i32] }:$vdata_in, v4i32:{ *:[v4i32] }:$rsrc, i32:{ *:[i32] }:$vindex, 0:{ *:[i32] }, (BUFSOffset:{ *:[i32] } i32:{ *:[i32] }:$soffset), (timm:{ *:[i32] }):$offset, (timm:{ *:[i32] }):$auxiliary, (timm:{ *:[i1] }))<<P:Predicate_SIbuffer_atomic_umax_noret>>  =>  (BUFFER_ATOMIC_UMAX_VBUFFER_IDXEN anonymous_15037:{ *:[i32] }:$vdata_in, VGPR_32:{ *:[i32] }:$vindex, SReg_128:{ *:[v4i32] }:$rsrc, SCSrc_b32:{ *:[i32] }:$soffset, (timm:{ *:[i32] }):$offset, (extract_cpol:{ *:[i32] } ?:{ *:[i32] }:$auxiliary))
        GIR_BuildMI, /*InsnID*/0, /*Opcode*/GIMT_Encode2(AMDGPU::BUFFER_ATOMIC_UMAX_VBUFFER_IDXEN),
        GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/1, // vdata_in
        GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/3, // vindex
        GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/2, // rsrc
        GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/0, // soffset
        GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/6, // offset
        GIR_CustomOperandRenderer, /*InsnID*/0, /*OldInsnID*/0, /*OpIdx*/7, /*OperandRenderer*/GIMT_Encode2(GICR_renderExtractCPol), // auxiliary
        GIR_MergeMemOperands, /*InsnID*/0, /*NumInsns*/1, /*MergeInsnID's*/0,
        GIR_ConstrainSelectedInstOperands, /*InsnID*/0,
        GIR_EraseFromParent, /*InsnID*/0,
        // GIR_Coverage, 4838,
        GIR_Done,
      // Label 6293: @461164
      GIM_Try, /*On fail goto*//*Label 6294*/ GIMT_Encode4(461241), // Rule ID 4826 //
        GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasUnrestrictedSOffset),
        GIM_CheckRegBankForClass, /*MI*/0, /*Op*/0, /*RC*/GIMT_Encode2(AMDGPU::AV_32RegClassID),
        GIM_CheckConstantInt8, /*MI*/0, /*Op*/4, 0,
        // MIs[0] offset
        GIM_CheckIsImm, /*MI*/0, /*Op*/6,
        // MIs[0] auxiliary
        GIM_CheckIsImm, /*MI*/0, /*Op*/7,
        // MIs[0] Operand 8
        GIM_CheckIsImm, /*MI*/0, /*Op*/8,
        GIM_CheckComplexPattern, /*MI*/0, /*Op*/5, /*Renderer*/GIMT_Encode2(0), GIMT_Encode2(GICP_gi_buf_soffset),
        // (SIbuffer_atomic_umax:{ *:[i32] } i32:{ *:[i32] }:$vdata_in, v4i32:{ *:[v4i32] }:$rsrc, i32:{ *:[i32] }:$vindex, 0:{ *:[i32] }, (BUFSOffset:{ *:[i32] } i32:{ *:[i32] }:$soffset), (timm:{ *:[i32] }):$offset, (timm:{ *:[i32] }):$auxiliary, (timm:{ *:[i1] }))  =>  (BUFFER_ATOMIC_UMAX_IDXEN_RTN:{ *:[i32] } anonymous_15037:{ *:[i32] }:$vdata_in, VGPR_32:{ *:[i32] }:$vindex, SReg_128:{ *:[v4i32] }:$rsrc, SCSrc_b32:{ *:[i32] }:$soffset, (timm:{ *:[i32] }):$offset, (extract_cpol_set_glc:{ *:[i32] } ?:{ *:[i32] }:$auxiliary))
        GIR_BuildMI, /*InsnID*/0, /*Opcode*/GIMT_Encode2(AMDGPU::BUFFER_ATOMIC_UMAX_IDXEN_RTN),
        GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/0, // DstI[vdata]
        GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/1, // vdata_in
        GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/3, // vindex
        GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/2, // rsrc
        GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/0, // soffset
        GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/6, // offset
        GIR_CustomOperandRenderer, /*InsnID*/0, /*OldInsnID*/0, /*OpIdx*/7, /*OperandRenderer*/GIMT_Encode2(GICR_renderExtractCpolSetGLC), // auxiliary
        GIR_MergeMemOperands, /*InsnID*/0, /*NumInsns*/1, /*MergeInsnID's*/0,
        GIR_ConstrainSelectedInstOperands, /*InsnID*/0,
        GIR_EraseFromParent, /*InsnID*/0,
        // GIR_Coverage, 4826,
        GIR_Done,
      // Label 6294: @461241
      GIM_Try, /*On fail goto*//*Label 6295*/ GIMT_Encode4(461315), // Rule ID 4834 //
        GIM_CheckRegBankForClass, /*MI*/0, /*Op*/0, /*RC*/GIMT_Encode2(AMDGPU::AV_32RegClassID),
        GIM_CheckConstantInt8, /*MI*/0, /*Op*/4, 0,
        // MIs[0] offset
        GIM_CheckIsImm, /*MI*/0, /*Op*/6,
        // MIs[0] auxiliary
        GIM_CheckIsImm, /*MI*/0, /*Op*/7,
        // MIs[0] Operand 8
        GIM_CheckIsImm, /*MI*/0, /*Op*/8,
        GIM_CheckComplexPattern, /*MI*/0, /*Op*/5, /*Renderer*/GIMT_Encode2(0), GIMT_Encode2(GICP_gi_buf_soffset),
        // (SIbuffer_atomic_umax:{ *:[i32] } i32:{ *:[i32] }:$vdata_in, v4i32:{ *:[v4i32] }:$rsrc, i32:{ *:[i32] }:$vindex, 0:{ *:[i32] }, (BUFSOffset:{ *:[i32] } i32:{ *:[i32] }:$soffset), (timm:{ *:[i32] }):$offset, (timm:{ *:[i32] }):$auxiliary, (timm:{ *:[i1] }))  =>  (BUFFER_ATOMIC_UMAX_VBUFFER_IDXEN_RTN:{ *:[i32] } anonymous_15037:{ *:[i32] }:$vdata_in, VGPR_32:{ *:[i32] }:$vindex, SReg_128:{ *:[v4i32] }:$rsrc, SCSrc_b32:{ *:[i32] }:$soffset, (timm:{ *:[i32] }):$offset, (extract_cpol_set_glc:{ *:[i32] } ?:{ *:[i32] }:$auxiliary))
        GIR_BuildMI, /*InsnID*/0, /*Opcode*/GIMT_Encode2(AMDGPU::BUFFER_ATOMIC_UMAX_VBUFFER_IDXEN_RTN),
        GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/0, // DstI[vdata]
        GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/1, // vdata_in
        GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/3, // vindex
        GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/2, // rsrc
        GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/0, // soffset
        GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/6, // offset
        GIR_CustomOperandRenderer, /*InsnID*/0, /*OldInsnID*/0, /*OpIdx*/7, /*OperandRenderer*/GIMT_Encode2(GICR_renderExtractCpolSetGLC), // auxiliary
        GIR_MergeMemOperands, /*InsnID*/0, /*NumInsns*/1, /*MergeInsnID's*/0,
        GIR_ConstrainSelectedInstOperands, /*InsnID*/0,
        GIR_EraseFromParent, /*InsnID*/0,
        // GIR_Coverage, 4834,
        GIR_Done,
      // Label 6295: @461315
      GIM_Try, /*On fail goto*//*Label 6296*/ GIMT_Encode4(461421), // Rule ID 4832 //
        GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasUnrestrictedSOffset),
        GIM_CheckHasNoUse, /*MI*/0,
        // MIs[0] offset
        GIM_CheckIsImm, /*MI*/0, /*Op*/6,
        // MIs[0] auxiliary
        GIM_CheckIsImm, /*MI*/0, /*Op*/7,
        // MIs[0] Operand 8
        GIM_CheckIsImm, /*MI*/0, /*Op*/8,
        GIM_CheckComplexPattern, /*MI*/0, /*Op*/5, /*Renderer*/GIMT_Encode2(0), GIMT_Encode2(GICP_gi_buf_soffset),
        // (SIbuffer_atomic_umax:{ *:[i32] } i32:{ *:[i32] }:$vdata_in, v4i32:{ *:[v4i32] }:$rsrc, i32:{ *:[i32] }:$vindex, i32:{ *:[i32] }:$voffset, (BUFSOffset:{ *:[i32] } i32:{ *:[i32] }:$soffset), (timm:{ *:[i32] }):$offset, (timm:{ *:[i32] }):$auxiliary, (timm:{ *:[i1] }))<<P:Predicate_SIbuffer_atomic_umax_noret>>  =>  (BUFFER_ATOMIC_UMAX_BOTHEN anonymous_15037:{ *:[i32] }:$vdata_in, (REG_SEQUENCE:{ *:[i64] } VReg_64:{ *:[i32] }, VGPR_32:{ *:[i32] }:$vindex, sub0:{ *:[i32] }, VGPR_32:{ *:[i32] }:$voffset, sub1:{ *:[i32] }), SReg_128:{ *:[v4i32] }:$rsrc, SCSrc_b32:{ *:[i32] }:$soffset, (timm:{ *:[i32] }):$offset, (extract_cpol:{ *:[i32] } ?:{ *:[i32] }:$auxiliary))
        GIR_MakeTempReg, /*TempRegID*/0, /*TypeID*/GILLT_s64,
        GIR_BuildMI, /*InsnID*/1, /*Opcode*/GIMT_Encode2(TargetOpcode::REG_SEQUENCE),
        GIR_AddTempRegister, /*InsnID*/1, /*TempRegID*/0, /*TempRegFlags*/GIMT_Encode2(RegState::Define),
        GIR_Copy, /*NewInsnID*/1, /*OldInsnID*/0, /*OpIdx*/3, // vindex
        GIR_AddImm8, /*InsnID*/1, /*SubRegIndex*/3,
        GIR_Copy, /*NewInsnID*/1, /*OldInsnID*/0, /*OpIdx*/4, // voffset
        GIR_AddImm8, /*InsnID*/1, /*SubRegIndex*/11,
        GIR_ConstrainOperandRC, /*InsnID*/1, /*Op*/0, GIMT_Encode2(AMDGPU::VReg_64RegClassID),
        GIR_ConstrainOperandRC, /*InsnID*/1, /*Op*/1, GIMT_Encode2(AMDGPU::VGPR_32RegClassID),
        GIR_ConstrainOperandRC, /*InsnID*/1, /*Op*/3, GIMT_Encode2(AMDGPU::VGPR_32RegClassID),
        GIR_BuildMI, /*InsnID*/0, /*Opcode*/GIMT_Encode2(AMDGPU::BUFFER_ATOMIC_UMAX_BOTHEN),
        GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/1, // vdata_in
        GIR_AddSimpleTempRegister, /*InsnID*/0, /*TempRegID*/0,
        GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/2, // rsrc
        GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/0, // soffset
        GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/6, // offset
        GIR_CustomOperandRenderer, /*InsnID*/0, /*OldInsnID*/0, /*OpIdx*/7, /*OperandRenderer*/GIMT_Encode2(GICR_renderExtractCPol), // auxiliary
        GIR_MergeMemOperands, /*InsnID*/0, /*NumInsns*/1, /*MergeInsnID's*/0,
        GIR_ConstrainSelectedInstOperands, /*InsnID*/0,
        GIR_EraseFromParent, /*InsnID*/0,
        // GIR_Coverage, 4832,
        GIR_Done,
      // Label 6296: @461421
      GIM_Try, /*On fail goto*//*Label 6297*/ GIMT_Encode4(461524), // Rule ID 4840 //
        GIM_CheckHasNoUse, /*MI*/0,
        // MIs[0] offset
        GIM_CheckIsImm, /*MI*/0, /*Op*/6,
        // MIs[0] auxiliary
        GIM_CheckIsImm, /*MI*/0, /*Op*/7,
        // MIs[0] Operand 8
        GIM_CheckIsImm, /*MI*/0, /*Op*/8,
        GIM_CheckComplexPattern, /*MI*/0, /*Op*/5, /*Renderer*/GIMT_Encode2(0), GIMT_Encode2(GICP_gi_buf_soffset),
        // (SIbuffer_atomic_umax:{ *:[i32] } i32:{ *:[i32] }:$vdata_in, v4i32:{ *:[v4i32] }:$rsrc, i32:{ *:[i32] }:$vindex, i32:{ *:[i32] }:$voffset, (BUFSOffset:{ *:[i32] } i32:{ *:[i32] }:$soffset), (timm:{ *:[i32] }):$offset, (timm:{ *:[i32] }):$auxiliary, (timm:{ *:[i1] }))<<P:Predicate_SIbuffer_atomic_umax_noret>>  =>  (BUFFER_ATOMIC_UMAX_VBUFFER_BOTHEN anonymous_15037:{ *:[i32] }:$vdata_in, (REG_SEQUENCE:{ *:[i64] } VReg_64:{ *:[i32] }, VGPR_32:{ *:[i32] }:$vindex, sub0:{ *:[i32] }, VGPR_32:{ *:[i32] }:$voffset, sub1:{ *:[i32] }), SReg_128:{ *:[v4i32] }:$rsrc, SCSrc_b32:{ *:[i32] }:$soffset, (timm:{ *:[i32] }):$offset, (extract_cpol:{ *:[i32] } ?:{ *:[i32] }:$auxiliary))
        GIR_MakeTempReg, /*TempRegID*/0, /*TypeID*/GILLT_s64,
        GIR_BuildMI, /*InsnID*/1, /*Opcode*/GIMT_Encode2(TargetOpcode::REG_SEQUENCE),
        GIR_AddTempRegister, /*InsnID*/1, /*TempRegID*/0, /*TempRegFlags*/GIMT_Encode2(RegState::Define),
        GIR_Copy, /*NewInsnID*/1, /*OldInsnID*/0, /*OpIdx*/3, // vindex
        GIR_AddImm8, /*InsnID*/1, /*SubRegIndex*/3,
        GIR_Copy, /*NewInsnID*/1, /*OldInsnID*/0, /*OpIdx*/4, // voffset
        GIR_AddImm8, /*InsnID*/1, /*SubRegIndex*/11,
        GIR_ConstrainOperandRC, /*InsnID*/1, /*Op*/0, GIMT_Encode2(AMDGPU::VReg_64RegClassID),
        GIR_ConstrainOperandRC, /*InsnID*/1, /*Op*/1, GIMT_Encode2(AMDGPU::VGPR_32RegClassID),
        GIR_ConstrainOperandRC, /*InsnID*/1, /*Op*/3, GIMT_Encode2(AMDGPU::VGPR_32RegClassID),
        GIR_BuildMI, /*InsnID*/0, /*Opcode*/GIMT_Encode2(AMDGPU::BUFFER_ATOMIC_UMAX_VBUFFER_BOTHEN),
        GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/1, // vdata_in
        GIR_AddSimpleTempRegister, /*InsnID*/0, /*TempRegID*/0,
        GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/2, // rsrc
        GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/0, // soffset
        GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/6, // offset
        GIR_CustomOperandRenderer, /*InsnID*/0, /*OldInsnID*/0, /*OpIdx*/7, /*OperandRenderer*/GIMT_Encode2(GICR_renderExtractCPol), // auxiliary
        GIR_MergeMemOperands, /*InsnID*/0, /*NumInsns*/1, /*MergeInsnID's*/0,
        GIR_ConstrainSelectedInstOperands, /*InsnID*/0,
        GIR_EraseFromParent, /*InsnID*/0,
        // GIR_Coverage, 4840,
        GIR_Done,
      // Label 6297: @461524
      GIM_Try, /*On fail goto*//*Label 6298*/ GIMT_Encode4(461637), // Rule ID 4828 //
        GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasUnrestrictedSOffset),
        GIM_CheckRegBankForClass, /*MI*/0, /*Op*/0, /*RC*/GIMT_Encode2(AMDGPU::AV_32RegClassID),
        // MIs[0] offset
        GIM_CheckIsImm, /*MI*/0, /*Op*/6,
        // MIs[0] auxiliary
        GIM_CheckIsImm, /*MI*/0, /*Op*/7,
        // MIs[0] Operand 8
        GIM_CheckIsImm, /*MI*/0, /*Op*/8,
        GIM_CheckComplexPattern, /*MI*/0, /*Op*/5, /*Renderer*/GIMT_Encode2(0), GIMT_Encode2(GICP_gi_buf_soffset),
        // (SIbuffer_atomic_umax:{ *:[i32] } i32:{ *:[i32] }:$vdata_in, v4i32:{ *:[v4i32] }:$rsrc, i32:{ *:[i32] }:$vindex, i32:{ *:[i32] }:$voffset, (BUFSOffset:{ *:[i32] } i32:{ *:[i32] }:$soffset), (timm:{ *:[i32] }):$offset, (timm:{ *:[i32] }):$auxiliary, (timm:{ *:[i1] }))  =>  (BUFFER_ATOMIC_UMAX_BOTHEN_RTN:{ *:[i32] } anonymous_15037:{ *:[i32] }:$vdata_in, (REG_SEQUENCE:{ *:[i64] } VReg_64:{ *:[i32] }, VGPR_32:{ *:[i32] }:$vindex, sub0:{ *:[i32] }, VGPR_32:{ *:[i32] }:$voffset, sub1:{ *:[i32] }), SReg_128:{ *:[v4i32] }:$rsrc, SCSrc_b32:{ *:[i32] }:$soffset, (timm:{ *:[i32] }):$offset, (extract_cpol_set_glc:{ *:[i32] } ?:{ *:[i32] }:$auxiliary))
        GIR_MakeTempReg, /*TempRegID*/0, /*TypeID*/GILLT_s64,
        GIR_BuildMI, /*InsnID*/1, /*Opcode*/GIMT_Encode2(TargetOpcode::REG_SEQUENCE),
        GIR_AddTempRegister, /*InsnID*/1, /*TempRegID*/0, /*TempRegFlags*/GIMT_Encode2(RegState::Define),
        GIR_Copy, /*NewInsnID*/1, /*OldInsnID*/0, /*OpIdx*/3, // vindex
        GIR_AddImm8, /*InsnID*/1, /*SubRegIndex*/3,
        GIR_Copy, /*NewInsnID*/1, /*OldInsnID*/0, /*OpIdx*/4, // voffset
        GIR_AddImm8, /*InsnID*/1, /*SubRegIndex*/11,
        GIR_ConstrainOperandRC, /*InsnID*/1, /*Op*/0, GIMT_Encode2(AMDGPU::VReg_64RegClassID),
        GIR_ConstrainOperandRC, /*InsnID*/1, /*Op*/1, GIMT_Encode2(AMDGPU::VGPR_32RegClassID),
        GIR_ConstrainOperandRC, /*InsnID*/1, /*Op*/3, GIMT_Encode2(AMDGPU::VGPR_32RegClassID),
        GIR_BuildMI, /*InsnID*/0, /*Opcode*/GIMT_Encode2(AMDGPU::BUFFER_ATOMIC_UMAX_BOTHEN_RTN),
        GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/0, // DstI[vdata]
        GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/1, // vdata_in
        GIR_AddSimpleTempRegister, /*InsnID*/0, /*TempRegID*/0,
        GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/2, // rsrc
        GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/0, // soffset
        GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/6, // offset
        GIR_CustomOperandRenderer, /*InsnID*/0, /*OldInsnID*/0, /*OpIdx*/7, /*OperandRenderer*/GIMT_Encode2(GICR_renderExtractCpolSetGLC), // auxiliary
        GIR_MergeMemOperands, /*InsnID*/0, /*NumInsns*/1, /*MergeInsnID's*/0,
        GIR_ConstrainSelectedInstOperands, /*InsnID*/0,
        GIR_EraseFromParent, /*InsnID*/0,
        // GIR_Coverage, 4828,
        GIR_Done,
      // Label 6298: @461637
      GIM_Try, /*On fail goto*//*Label 6299*/ GIMT_Encode4(461747), // Rule ID 4836 //
        GIM_CheckRegBankForClass, /*MI*/0, /*Op*/0, /*RC*/GIMT_Encode2(AMDGPU::AV_32RegClassID),
        // MIs[0] offset
        GIM_CheckIsImm, /*MI*/0, /*Op*/6,
        // MIs[0] auxiliary
        GIM_CheckIsImm, /*MI*/0, /*Op*/7,
        // MIs[0] Operand 8
        GIM_CheckIsImm, /*MI*/0, /*Op*/8,
        GIM_CheckComplexPattern, /*MI*/0, /*Op*/5, /*Renderer*/GIMT_Encode2(0), GIMT_Encode2(GICP_gi_buf_soffset),
        // (SIbuffer_atomic_umax:{ *:[i32] } i32:{ *:[i32] }:$vdata_in, v4i32:{ *:[v4i32] }:$rsrc, i32:{ *:[i32] }:$vindex, i32:{ *:[i32] }:$voffset, (BUFSOffset:{ *:[i32] } i32:{ *:[i32] }:$soffset), (timm:{ *:[i32] }):$offset, (timm:{ *:[i32] }):$auxiliary, (timm:{ *:[i1] }))  =>  (BUFFER_ATOMIC_UMAX_VBUFFER_BOTHEN_RTN:{ *:[i32] } anonymous_15037:{ *:[i32] }:$vdata_in, (REG_SEQUENCE:{ *:[i64] } VReg_64:{ *:[i32] }, VGPR_32:{ *:[i32] }:$vindex, sub0:{ *:[i32] }, VGPR_32:{ *:[i32] }:$voffset, sub1:{ *:[i32] }), SReg_128:{ *:[v4i32] }:$rsrc, SCSrc_b32:{ *:[i32] }:$soffset, (timm:{ *:[i32] }):$offset, (extract_cpol_set_glc:{ *:[i32] } ?:{ *:[i32] }:$auxiliary))
        GIR_MakeTempReg, /*TempRegID*/0, /*TypeID*/GILLT_s64,
        GIR_BuildMI, /*InsnID*/1, /*Opcode*/GIMT_Encode2(TargetOpcode::REG_SEQUENCE),
        GIR_AddTempRegister, /*InsnID*/1, /*TempRegID*/0, /*TempRegFlags*/GIMT_Encode2(RegState::Define),
        GIR_Copy, /*NewInsnID*/1, /*OldInsnID*/0, /*OpIdx*/3, // vindex
        GIR_AddImm8, /*InsnID*/1, /*SubRegIndex*/3,
        GIR_Copy, /*NewInsnID*/1, /*OldInsnID*/0, /*OpIdx*/4, // voffset
        GIR_AddImm8, /*InsnID*/1, /*SubRegIndex*/11,
        GIR_ConstrainOperandRC, /*InsnID*/1, /*Op*/0, GIMT_Encode2(AMDGPU::VReg_64RegClassID),
        GIR_ConstrainOperandRC, /*InsnID*/1, /*Op*/1, GIMT_Encode2(AMDGPU::VGPR_32RegClassID),
        GIR_ConstrainOperandRC, /*InsnID*/1, /*Op*/3, GIMT_Encode2(AMDGPU::VGPR_32RegClassID),
        GIR_BuildMI, /*InsnID*/0, /*Opcode*/GIMT_Encode2(AMDGPU::BUFFER_ATOMIC_UMAX_VBUFFER_BOTHEN_RTN),
        GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/0, // DstI[vdata]
        GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/1, // vdata_in
        GIR_AddSimpleTempRegister, /*InsnID*/0, /*TempRegID*/0,
        GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/2, // rsrc
        GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/0, // soffset
        GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/6, // offset
        GIR_CustomOperandRenderer, /*InsnID*/0, /*OldInsnID*/0, /*OpIdx*/7, /*OperandRenderer*/GIMT_Encode2(GICR_renderExtractCpolSetGLC), // auxiliary
        GIR_MergeMemOperands, /*InsnID*/0, /*NumInsns*/1, /*MergeInsnID's*/0,
        GIR_ConstrainSelectedInstOperands, /*InsnID*/0,
        GIR_EraseFromParent, /*InsnID*/0,
        // GIR_Coverage, 4836,
        GIR_Done,
      // Label 6299: @461747
      GIM_Reject,
    // Label 6283: @461748
    GIM_Reject,
    // Label 6281: @461749
    GIM_Try, /*On fail goto*//*Label 6300*/ GIMT_Encode4(463135),
      GIM_CheckType, /*MI*/0, /*Op*/1, /*Type*/GILLT_s64,
      GIM_CheckType, /*MI*/0, /*Op*/2, /*Type*/GILLT_v4s32,
      GIM_CheckType, /*MI*/0, /*Op*/3, /*Type*/GILLT_s32,
      GIM_CheckType, /*MI*/0, /*Op*/4, /*Type*/GILLT_s32,
      GIM_CheckType, /*MI*/0, /*Op*/5, /*Type*/GILLT_s32,
      GIM_Try, /*On fail goto*//*Label 6301*/ GIMT_Encode4(461852), // Rule ID 5029 //
        GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasUnrestrictedSOffset),
        GIM_CheckHasNoUse, /*MI*/0,
        GIM_CheckConstantInt8, /*MI*/0, /*Op*/3, 0,
        GIM_CheckConstantInt8, /*MI*/0, /*Op*/4, 0,
        // MIs[0] offset
        GIM_CheckIsImm, /*MI*/0, /*Op*/6,
        // MIs[0] auxiliary
        GIM_CheckIsImm, /*MI*/0, /*Op*/7,
        // MIs[0] Operand 8
        GIM_CheckLiteralInt, /*MI*/0, /*Op*/8, GIMT_Encode8(0),
        GIM_CheckComplexPattern, /*MI*/0, /*Op*/5, /*Renderer*/GIMT_Encode2(0), GIMT_Encode2(GICP_gi_buf_soffset),
        // (SIbuffer_atomic_umax:{ *:[i64] } i64:{ *:[i64] }:$vdata_in, v4i32:{ *:[v4i32] }:$rsrc, 0:{ *:[i32] }, 0:{ *:[i32] }, (BUFSOffset:{ *:[i32] } i32:{ *:[i32] }:$soffset), (timm:{ *:[i32] }):$offset, (timm:{ *:[i32] }):$auxiliary, 0:{ *:[i1] })<<P:Predicate_SIbuffer_atomic_umax_noret>>  =>  (BUFFER_ATOMIC_UMAX_X2_OFFSET anonymous_15036:{ *:[i64] }:$vdata_in, SReg_128:{ *:[v4i32] }:$rsrc, SCSrc_b32:{ *:[i32] }:$soffset, (timm:{ *:[i32] }):$offset, (extract_cpol:{ *:[i32] } ?:{ *:[i32] }:$auxiliary))
        GIR_BuildMI, /*InsnID*/0, /*Opcode*/GIMT_Encode2(AMDGPU::BUFFER_ATOMIC_UMAX_X2_OFFSET),
        GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/1, // vdata_in
        GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/2, // rsrc
        GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/0, // soffset
        GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/6, // offset
        GIR_CustomOperandRenderer, /*InsnID*/0, /*OldInsnID*/0, /*OpIdx*/7, /*OperandRenderer*/GIMT_Encode2(GICR_renderExtractCPol), // auxiliary
        GIR_MergeMemOperands, /*InsnID*/0, /*NumInsns*/1, /*MergeInsnID's*/0,
        GIR_ConstrainSelectedInstOperands, /*InsnID*/0,
        GIR_EraseFromParent, /*InsnID*/0,
        // GIR_Coverage, 5029,
        GIR_Done,
      // Label 6301: @461852
      GIM_Try, /*On fail goto*//*Label 6302*/ GIMT_Encode4(461927), // Rule ID 5037 //
        GIM_CheckHasNoUse, /*MI*/0,
        GIM_CheckConstantInt8, /*MI*/0, /*Op*/3, 0,
        GIM_CheckConstantInt8, /*MI*/0, /*Op*/4, 0,
        // MIs[0] offset
        GIM_CheckIsImm, /*MI*/0, /*Op*/6,
        // MIs[0] auxiliary
        GIM_CheckIsImm, /*MI*/0, /*Op*/7,
        // MIs[0] Operand 8
        GIM_CheckLiteralInt, /*MI*/0, /*Op*/8, GIMT_Encode8(0),
        GIM_CheckComplexPattern, /*MI*/0, /*Op*/5, /*Renderer*/GIMT_Encode2(0), GIMT_Encode2(GICP_gi_buf_soffset),
        // (SIbuffer_atomic_umax:{ *:[i64] } i64:{ *:[i64] }:$vdata_in, v4i32:{ *:[v4i32] }:$rsrc, 0:{ *:[i32] }, 0:{ *:[i32] }, (BUFSOffset:{ *:[i32] } i32:{ *:[i32] }:$soffset), (timm:{ *:[i32] }):$offset, (timm:{ *:[i32] }):$auxiliary, 0:{ *:[i1] })<<P:Predicate_SIbuffer_atomic_umax_noret>>  =>  (BUFFER_ATOMIC_UMAX_X2_VBUFFER_OFFSET anonymous_15036:{ *:[i64] }:$vdata_in, SReg_128:{ *:[v4i32] }:$rsrc, SCSrc_b32:{ *:[i32] }:$soffset, (timm:{ *:[i32] }):$offset, (extract_cpol:{ *:[i32] } ?:{ *:[i32] }:$auxiliary))
        GIR_BuildMI, /*InsnID*/0, /*Opcode*/GIMT_Encode2(AMDGPU::BUFFER_ATOMIC_UMAX_X2_VBUFFER_OFFSET),
        GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/1, // vdata_in
        GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/2, // rsrc
        GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/0, // soffset
        GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/6, // offset
        GIR_CustomOperandRenderer, /*InsnID*/0, /*OldInsnID*/0, /*OpIdx*/7, /*OperandRenderer*/GIMT_Encode2(GICR_renderExtractCPol), // auxiliary
        GIR_MergeMemOperands, /*InsnID*/0, /*NumInsns*/1, /*MergeInsnID's*/0,
        GIR_ConstrainSelectedInstOperands, /*InsnID*/0,
        GIR_EraseFromParent, /*InsnID*/0,
        // GIR_Coverage, 5037,
        GIR_Done,
      // Label 6302: @461927
      GIM_Try, /*On fail goto*//*Label 6303*/ GIMT_Encode4(462012), // Rule ID 5025 //
        GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasUnrestrictedSOffset),
        GIM_CheckRegBankForClass, /*MI*/0, /*Op*/0, /*RC*/GIMT_Encode2(AMDGPU::AV_64RegClassID),
        GIM_CheckConstantInt8, /*MI*/0, /*Op*/3, 0,
        GIM_CheckConstantInt8, /*MI*/0, /*Op*/4, 0,
        // MIs[0] offset
        GIM_CheckIsImm, /*MI*/0, /*Op*/6,
        // MIs[0] auxiliary
        GIM_CheckIsImm, /*MI*/0, /*Op*/7,
        // MIs[0] Operand 8
        GIM_CheckLiteralInt, /*MI*/0, /*Op*/8, GIMT_Encode8(0),
        GIM_CheckComplexPattern, /*MI*/0, /*Op*/5, /*Renderer*/GIMT_Encode2(0), GIMT_Encode2(GICP_gi_buf_soffset),
        // (SIbuffer_atomic_umax:{ *:[i64] } i64:{ *:[i64] }:$vdata_in, v4i32:{ *:[v4i32] }:$rsrc, 0:{ *:[i32] }, 0:{ *:[i32] }, (BUFSOffset:{ *:[i32] } i32:{ *:[i32] }:$soffset), (timm:{ *:[i32] }):$offset, (timm:{ *:[i32] }):$auxiliary, 0:{ *:[i1] })  =>  (BUFFER_ATOMIC_UMAX_X2_OFFSET_RTN:{ *:[i64] } anonymous_15036:{ *:[i64] }:$vdata_in, SReg_128:{ *:[v4i32] }:$rsrc, SCSrc_b32:{ *:[i32] }:$soffset, (timm:{ *:[i32] }):$offset, (extract_cpol_set_glc:{ *:[i32] } ?:{ *:[i32] }:$auxiliary))
        GIR_BuildMI, /*InsnID*/0, /*Opcode*/GIMT_Encode2(AMDGPU::BUFFER_ATOMIC_UMAX_X2_OFFSET_RTN),
        GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/0, // DstI[vdata]
        GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/1, // vdata_in
        GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/2, // rsrc
        GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/0, // soffset
        GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/6, // offset
        GIR_CustomOperandRenderer, /*InsnID*/0, /*OldInsnID*/0, /*OpIdx*/7, /*OperandRenderer*/GIMT_Encode2(GICR_renderExtractCpolSetGLC), // auxiliary
        GIR_MergeMemOperands, /*InsnID*/0, /*NumInsns*/1, /*MergeInsnID's*/0,
        GIR_ConstrainSelectedInstOperands, /*InsnID*/0,
        GIR_EraseFromParent, /*InsnID*/0,
        // GIR_Coverage, 5025,
        GIR_Done,
      // Label 6303: @462012
      GIM_Try, /*On fail goto*//*Label 6304*/ GIMT_Encode4(462094), // Rule ID 5033 //
        GIM_CheckRegBankForClass, /*MI*/0, /*Op*/0, /*RC*/GIMT_Encode2(AMDGPU::AV_64RegClassID),
        GIM_CheckConstantInt8, /*MI*/0, /*Op*/3, 0,
        GIM_CheckConstantInt8, /*MI*/0, /*Op*/4, 0,
        // MIs[0] offset
        GIM_CheckIsImm, /*MI*/0, /*Op*/6,
        // MIs[0] auxiliary
        GIM_CheckIsImm, /*MI*/0, /*Op*/7,
        // MIs[0] Operand 8
        GIM_CheckLiteralInt, /*MI*/0, /*Op*/8, GIMT_Encode8(0),
        GIM_CheckComplexPattern, /*MI*/0, /*Op*/5, /*Renderer*/GIMT_Encode2(0), GIMT_Encode2(GICP_gi_buf_soffset),
        // (SIbuffer_atomic_umax:{ *:[i64] } i64:{ *:[i64] }:$vdata_in, v4i32:{ *:[v4i32] }:$rsrc, 0:{ *:[i32] }, 0:{ *:[i32] }, (BUFSOffset:{ *:[i32] } i32:{ *:[i32] }:$soffset), (timm:{ *:[i32] }):$offset, (timm:{ *:[i32] }):$auxiliary, 0:{ *:[i1] })  =>  (BUFFER_ATOMIC_UMAX_X2_VBUFFER_OFFSET_RTN:{ *:[i64] } anonymous_15036:{ *:[i64] }:$vdata_in, SReg_128:{ *:[v4i32] }:$rsrc, SCSrc_b32:{ *:[i32] }:$soffset, (timm:{ *:[i32] }):$offset, (extract_cpol_set_glc:{ *:[i32] } ?:{ *:[i32] }:$auxiliary))
        GIR_BuildMI, /*InsnID*/0, /*Opcode*/GIMT_Encode2(AMDGPU::BUFFER_ATOMIC_UMAX_X2_VBUFFER_OFFSET_RTN),
        GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/0, // DstI[vdata]
        GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/1, // vdata_in
        GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/2, // rsrc
        GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/0, // soffset
        GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/6, // offset
        GIR_CustomOperandRenderer, /*InsnID*/0, /*OldInsnID*/0, /*OpIdx*/7, /*OperandRenderer*/GIMT_Encode2(GICR_renderExtractCpolSetGLC), // auxiliary
        GIR_MergeMemOperands, /*InsnID*/0, /*NumInsns*/1, /*MergeInsnID's*/0,
        GIR_ConstrainSelectedInstOperands, /*InsnID*/0,
        GIR_EraseFromParent, /*InsnID*/0,
        // GIR_Coverage, 5033,
        GIR_Done,
      // Label 6304: @462094
      GIM_Try, /*On fail goto*//*Label 6305*/ GIMT_Encode4(462172), // Rule ID 5031 //
        GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasUnrestrictedSOffset),
        GIM_CheckHasNoUse, /*MI*/0,
        GIM_CheckConstantInt8, /*MI*/0, /*Op*/3, 0,
        // MIs[0] offset
        GIM_CheckIsImm, /*MI*/0, /*Op*/6,
        // MIs[0] auxiliary
        GIM_CheckIsImm, /*MI*/0, /*Op*/7,
        // MIs[0] Operand 8
        GIM_CheckLiteralInt, /*MI*/0, /*Op*/8, GIMT_Encode8(0),
        GIM_CheckComplexPattern, /*MI*/0, /*Op*/5, /*Renderer*/GIMT_Encode2(0), GIMT_Encode2(GICP_gi_buf_soffset),
        // (SIbuffer_atomic_umax:{ *:[i64] } i64:{ *:[i64] }:$vdata_in, v4i32:{ *:[v4i32] }:$rsrc, 0:{ *:[i32] }, i32:{ *:[i32] }:$voffset, (BUFSOffset:{ *:[i32] } i32:{ *:[i32] }:$soffset), (timm:{ *:[i32] }):$offset, (timm:{ *:[i32] }):$auxiliary, 0:{ *:[i1] })<<P:Predicate_SIbuffer_atomic_umax_noret>>  =>  (BUFFER_ATOMIC_UMAX_X2_OFFEN anonymous_15036:{ *:[i64] }:$vdata_in, VGPR_32:{ *:[i32] }:$voffset, SReg_128:{ *:[v4i32] }:$rsrc, SCSrc_b32:{ *:[i32] }:$soffset, (timm:{ *:[i32] }):$offset, (extract_cpol:{ *:[i32] } ?:{ *:[i32] }:$auxiliary))
        GIR_BuildMI, /*InsnID*/0, /*Opcode*/GIMT_Encode2(AMDGPU::BUFFER_ATOMIC_UMAX_X2_OFFEN),
        GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/1, // vdata_in
        GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/4, // voffset
        GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/2, // rsrc
        GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/0, // soffset
        GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/6, // offset
        GIR_CustomOperandRenderer, /*InsnID*/0, /*OldInsnID*/0, /*OpIdx*/7, /*OperandRenderer*/GIMT_Encode2(GICR_renderExtractCPol), // auxiliary
        GIR_MergeMemOperands, /*InsnID*/0, /*NumInsns*/1, /*MergeInsnID's*/0,
        GIR_ConstrainSelectedInstOperands, /*InsnID*/0,
        GIR_EraseFromParent, /*InsnID*/0,
        // GIR_Coverage, 5031,
        GIR_Done,
      // Label 6305: @462172
      GIM_Try, /*On fail goto*//*Label 6306*/ GIMT_Encode4(462247), // Rule ID 5039 //
        GIM_CheckHasNoUse, /*MI*/0,
        GIM_CheckConstantInt8, /*MI*/0, /*Op*/3, 0,
        // MIs[0] offset
        GIM_CheckIsImm, /*MI*/0, /*Op*/6,
        // MIs[0] auxiliary
        GIM_CheckIsImm, /*MI*/0, /*Op*/7,
        // MIs[0] Operand 8
        GIM_CheckLiteralInt, /*MI*/0, /*Op*/8, GIMT_Encode8(0),
        GIM_CheckComplexPattern, /*MI*/0, /*Op*/5, /*Renderer*/GIMT_Encode2(0), GIMT_Encode2(GICP_gi_buf_soffset),
        // (SIbuffer_atomic_umax:{ *:[i64] } i64:{ *:[i64] }:$vdata_in, v4i32:{ *:[v4i32] }:$rsrc, 0:{ *:[i32] }, i32:{ *:[i32] }:$voffset, (BUFSOffset:{ *:[i32] } i32:{ *:[i32] }:$soffset), (timm:{ *:[i32] }):$offset, (timm:{ *:[i32] }):$auxiliary, 0:{ *:[i1] })<<P:Predicate_SIbuffer_atomic_umax_noret>>  =>  (BUFFER_ATOMIC_UMAX_X2_VBUFFER_OFFEN anonymous_15036:{ *:[i64] }:$vdata_in, VGPR_32:{ *:[i32] }:$voffset, SReg_128:{ *:[v4i32] }:$rsrc, SCSrc_b32:{ *:[i32] }:$soffset, (timm:{ *:[i32] }):$offset, (extract_cpol:{ *:[i32] } ?:{ *:[i32] }:$auxiliary))
        GIR_BuildMI, /*InsnID*/0, /*Opcode*/GIMT_Encode2(AMDGPU::BUFFER_ATOMIC_UMAX_X2_VBUFFER_OFFEN),
        GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/1, // vdata_in
        GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/4, // voffset
        GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/2, // rsrc
        GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/0, // soffset
        GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/6, // offset
        GIR_CustomOperandRenderer, /*InsnID*/0, /*OldInsnID*/0, /*OpIdx*/7, /*OperandRenderer*/GIMT_Encode2(GICR_renderExtractCPol), // auxiliary
        GIR_MergeMemOperands, /*InsnID*/0, /*NumInsns*/1, /*MergeInsnID's*/0,
        GIR_ConstrainSelectedInstOperands, /*InsnID*/0,
        GIR_EraseFromParent, /*InsnID*/0,
        // GIR_Coverage, 5039,
        GIR_Done,
      // Label 6306: @462247
      GIM_Try, /*On fail goto*//*Label 6307*/ GIMT_Encode4(462332), // Rule ID 5027 //
        GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasUnrestrictedSOffset),
        GIM_CheckRegBankForClass, /*MI*/0, /*Op*/0, /*RC*/GIMT_Encode2(AMDGPU::AV_64RegClassID),
        GIM_CheckConstantInt8, /*MI*/0, /*Op*/3, 0,
        // MIs[0] offset
        GIM_CheckIsImm, /*MI*/0, /*Op*/6,
        // MIs[0] auxiliary
        GIM_CheckIsImm, /*MI*/0, /*Op*/7,
        // MIs[0] Operand 8
        GIM_CheckLiteralInt, /*MI*/0, /*Op*/8, GIMT_Encode8(0),
        GIM_CheckComplexPattern, /*MI*/0, /*Op*/5, /*Renderer*/GIMT_Encode2(0), GIMT_Encode2(GICP_gi_buf_soffset),
        // (SIbuffer_atomic_umax:{ *:[i64] } i64:{ *:[i64] }:$vdata_in, v4i32:{ *:[v4i32] }:$rsrc, 0:{ *:[i32] }, i32:{ *:[i32] }:$voffset, (BUFSOffset:{ *:[i32] } i32:{ *:[i32] }:$soffset), (timm:{ *:[i32] }):$offset, (timm:{ *:[i32] }):$auxiliary, 0:{ *:[i1] })  =>  (BUFFER_ATOMIC_UMAX_X2_OFFEN_RTN:{ *:[i64] } anonymous_15036:{ *:[i64] }:$vdata_in, VGPR_32:{ *:[i32] }:$voffset, SReg_128:{ *:[v4i32] }:$rsrc, SCSrc_b32:{ *:[i32] }:$soffset, (timm:{ *:[i32] }):$offset, (extract_cpol_set_glc:{ *:[i32] } ?:{ *:[i32] }:$auxiliary))
        GIR_BuildMI, /*InsnID*/0, /*Opcode*/GIMT_Encode2(AMDGPU::BUFFER_ATOMIC_UMAX_X2_OFFEN_RTN),
        GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/0, // DstI[vdata]
        GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/1, // vdata_in
        GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/4, // voffset
        GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/2, // rsrc
        GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/0, // soffset
        GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/6, // offset
        GIR_CustomOperandRenderer, /*InsnID*/0, /*OldInsnID*/0, /*OpIdx*/7, /*OperandRenderer*/GIMT_Encode2(GICR_renderExtractCpolSetGLC), // auxiliary
        GIR_MergeMemOperands, /*InsnID*/0, /*NumInsns*/1, /*MergeInsnID's*/0,
        GIR_ConstrainSelectedInstOperands, /*InsnID*/0,
        GIR_EraseFromParent, /*InsnID*/0,
        // GIR_Coverage, 5027,
        GIR_Done,
      // Label 6307: @462332
      GIM_Try, /*On fail goto*//*Label 6308*/ GIMT_Encode4(462414), // Rule ID 5035 //
        GIM_CheckRegBankForClass, /*MI*/0, /*Op*/0, /*RC*/GIMT_Encode2(AMDGPU::AV_64RegClassID),
        GIM_CheckConstantInt8, /*MI*/0, /*Op*/3, 0,
        // MIs[0] offset
        GIM_CheckIsImm, /*MI*/0, /*Op*/6,
        // MIs[0] auxiliary
        GIM_CheckIsImm, /*MI*/0, /*Op*/7,
        // MIs[0] Operand 8
        GIM_CheckLiteralInt, /*MI*/0, /*Op*/8, GIMT_Encode8(0),
        GIM_CheckComplexPattern, /*MI*/0, /*Op*/5, /*Renderer*/GIMT_Encode2(0), GIMT_Encode2(GICP_gi_buf_soffset),
        // (SIbuffer_atomic_umax:{ *:[i64] } i64:{ *:[i64] }:$vdata_in, v4i32:{ *:[v4i32] }:$rsrc, 0:{ *:[i32] }, i32:{ *:[i32] }:$voffset, (BUFSOffset:{ *:[i32] } i32:{ *:[i32] }:$soffset), (timm:{ *:[i32] }):$offset, (timm:{ *:[i32] }):$auxiliary, 0:{ *:[i1] })  =>  (BUFFER_ATOMIC_UMAX_X2_VBUFFER_OFFEN_RTN:{ *:[i64] } anonymous_15036:{ *:[i64] }:$vdata_in, VGPR_32:{ *:[i32] }:$voffset, SReg_128:{ *:[v4i32] }:$rsrc, SCSrc_b32:{ *:[i32] }:$soffset, (timm:{ *:[i32] }):$offset, (extract_cpol_set_glc:{ *:[i32] } ?:{ *:[i32] }:$auxiliary))
        GIR_BuildMI, /*InsnID*/0, /*Opcode*/GIMT_Encode2(AMDGPU::BUFFER_ATOMIC_UMAX_X2_VBUFFER_OFFEN_RTN),
        GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/0, // DstI[vdata]
        GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/1, // vdata_in
        GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/4, // voffset
        GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/2, // rsrc
        GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/0, // soffset
        GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/6, // offset
        GIR_CustomOperandRenderer, /*InsnID*/0, /*OldInsnID*/0, /*OpIdx*/7, /*OperandRenderer*/GIMT_Encode2(GICR_renderExtractCpolSetGLC), // auxiliary
        GIR_MergeMemOperands, /*InsnID*/0, /*NumInsns*/1, /*MergeInsnID's*/0,
        GIR_ConstrainSelectedInstOperands, /*InsnID*/0,
        GIR_EraseFromParent, /*InsnID*/0,
        // GIR_Coverage, 5035,
        GIR_Done,
      // Label 6308: @462414
      GIM_Try, /*On fail goto*//*Label 6309*/ GIMT_Encode4(462484), // Rule ID 5030 //
        GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasUnrestrictedSOffset),
        GIM_CheckHasNoUse, /*MI*/0,
        GIM_CheckConstantInt8, /*MI*/0, /*Op*/4, 0,
        // MIs[0] offset
        GIM_CheckIsImm, /*MI*/0, /*Op*/6,
        // MIs[0] auxiliary
        GIM_CheckIsImm, /*MI*/0, /*Op*/7,
        // MIs[0] Operand 8
        GIM_CheckIsImm, /*MI*/0, /*Op*/8,
        GIM_CheckComplexPattern, /*MI*/0, /*Op*/5, /*Renderer*/GIMT_Encode2(0), GIMT_Encode2(GICP_gi_buf_soffset),
        // (SIbuffer_atomic_umax:{ *:[i64] } i64:{ *:[i64] }:$vdata_in, v4i32:{ *:[v4i32] }:$rsrc, i32:{ *:[i32] }:$vindex, 0:{ *:[i32] }, (BUFSOffset:{ *:[i32] } i32:{ *:[i32] }:$soffset), (timm:{ *:[i32] }):$offset, (timm:{ *:[i32] }):$auxiliary, (timm:{ *:[i1] }))<<P:Predicate_SIbuffer_atomic_umax_noret>>  =>  (BUFFER_ATOMIC_UMAX_X2_IDXEN anonymous_15036:{ *:[i64] }:$vdata_in, VGPR_32:{ *:[i32] }:$vindex, SReg_128:{ *:[v4i32] }:$rsrc, SCSrc_b32:{ *:[i32] }:$soffset, (timm:{ *:[i32] }):$offset, (extract_cpol:{ *:[i32] } ?:{ *:[i32] }:$auxiliary))
        GIR_BuildMI, /*InsnID*/0, /*Opcode*/GIMT_Encode2(AMDGPU::BUFFER_ATOMIC_UMAX_X2_IDXEN),
        GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/1, // vdata_in
        GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/3, // vindex
        GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/2, // rsrc
        GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/0, // soffset
        GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/6, // offset
        GIR_CustomOperandRenderer, /*InsnID*/0, /*OldInsnID*/0, /*OpIdx*/7, /*OperandRenderer*/GIMT_Encode2(GICR_renderExtractCPol), // auxiliary
        GIR_MergeMemOperands, /*InsnID*/0, /*NumInsns*/1, /*MergeInsnID's*/0,
        GIR_ConstrainSelectedInstOperands, /*InsnID*/0,
        GIR_EraseFromParent, /*InsnID*/0,
        // GIR_Coverage, 5030,
        GIR_Done,
      // Label 6309: @462484
      GIM_Try, /*On fail goto*//*Label 6310*/ GIMT_Encode4(462551), // Rule ID 5038 //
        GIM_CheckHasNoUse, /*MI*/0,
        GIM_CheckConstantInt8, /*MI*/0, /*Op*/4, 0,
        // MIs[0] offset
        GIM_CheckIsImm, /*MI*/0, /*Op*/6,
        // MIs[0] auxiliary
        GIM_CheckIsImm, /*MI*/0, /*Op*/7,
        // MIs[0] Operand 8
        GIM_CheckIsImm, /*MI*/0, /*Op*/8,
        GIM_CheckComplexPattern, /*MI*/0, /*Op*/5, /*Renderer*/GIMT_Encode2(0), GIMT_Encode2(GICP_gi_buf_soffset),
        // (SIbuffer_atomic_umax:{ *:[i64] } i64:{ *:[i64] }:$vdata_in, v4i32:{ *:[v4i32] }:$rsrc, i32:{ *:[i32] }:$vindex, 0:{ *:[i32] }, (BUFSOffset:{ *:[i32] } i32:{ *:[i32] }:$soffset), (timm:{ *:[i32] }):$offset, (timm:{ *:[i32] }):$auxiliary, (timm:{ *:[i1] }))<<P:Predicate_SIbuffer_atomic_umax_noret>>  =>  (BUFFER_ATOMIC_UMAX_X2_VBUFFER_IDXEN anonymous_15036:{ *:[i64] }:$vdata_in, VGPR_32:{ *:[i32] }:$vindex, SReg_128:{ *:[v4i32] }:$rsrc, SCSrc_b32:{ *:[i32] }:$soffset, (timm:{ *:[i32] }):$offset, (extract_cpol:{ *:[i32] } ?:{ *:[i32] }:$auxiliary))
        GIR_BuildMI, /*InsnID*/0, /*Opcode*/GIMT_Encode2(AMDGPU::BUFFER_ATOMIC_UMAX_X2_VBUFFER_IDXEN),
        GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/1, // vdata_in
        GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/3, // vindex
        GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/2, // rsrc
        GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/0, // soffset
        GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/6, // offset
        GIR_CustomOperandRenderer, /*InsnID*/0, /*OldInsnID*/0, /*OpIdx*/7, /*OperandRenderer*/GIMT_Encode2(GICR_renderExtractCPol), // auxiliary
        GIR_MergeMemOperands, /*InsnID*/0, /*NumInsns*/1, /*MergeInsnID's*/0,
        GIR_ConstrainSelectedInstOperands, /*InsnID*/0,
        GIR_EraseFromParent, /*InsnID*/0,
        // GIR_Coverage, 5038,
        GIR_Done,
      // Label 6310: @462551
      GIM_Try, /*On fail goto*//*Label 6311*/ GIMT_Encode4(462628), // Rule ID 5026 //
        GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasUnrestrictedSOffset),
        GIM_CheckRegBankForClass, /*MI*/0, /*Op*/0, /*RC*/GIMT_Encode2(AMDGPU::AV_64RegClassID),
        GIM_CheckConstantInt8, /*MI*/0, /*Op*/4, 0,
        // MIs[0] offset
        GIM_CheckIsImm, /*MI*/0, /*Op*/6,
        // MIs[0] auxiliary
        GIM_CheckIsImm, /*MI*/0, /*Op*/7,
        // MIs[0] Operand 8
        GIM_CheckIsImm, /*MI*/0, /*Op*/8,
        GIM_CheckComplexPattern, /*MI*/0, /*Op*/5, /*Renderer*/GIMT_Encode2(0), GIMT_Encode2(GICP_gi_buf_soffset),
        // (SIbuffer_atomic_umax:{ *:[i64] } i64:{ *:[i64] }:$vdata_in, v4i32:{ *:[v4i32] }:$rsrc, i32:{ *:[i32] }:$vindex, 0:{ *:[i32] }, (BUFSOffset:{ *:[i32] } i32:{ *:[i32] }:$soffset), (timm:{ *:[i32] }):$offset, (timm:{ *:[i32] }):$auxiliary, (timm:{ *:[i1] }))  =>  (BUFFER_ATOMIC_UMAX_X2_IDXEN_RTN:{ *:[i64] } anonymous_15036:{ *:[i64] }:$vdata_in, VGPR_32:{ *:[i32] }:$vindex, SReg_128:{ *:[v4i32] }:$rsrc, SCSrc_b32:{ *:[i32] }:$soffset, (timm:{ *:[i32] }):$offset, (extract_cpol_set_glc:{ *:[i32] } ?:{ *:[i32] }:$auxiliary))
        GIR_BuildMI, /*InsnID*/0, /*Opcode*/GIMT_Encode2(AMDGPU::BUFFER_ATOMIC_UMAX_X2_IDXEN_RTN),
        GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/0, // DstI[vdata]
        GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/1, // vdata_in
        GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/3, // vindex
        GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/2, // rsrc
        GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/0, // soffset
        GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/6, // offset
        GIR_CustomOperandRenderer, /*InsnID*/0, /*OldInsnID*/0, /*OpIdx*/7, /*OperandRenderer*/GIMT_Encode2(GICR_renderExtractCpolSetGLC), // auxiliary
        GIR_MergeMemOperands, /*InsnID*/0, /*NumInsns*/1, /*MergeInsnID's*/0,
        GIR_ConstrainSelectedInstOperands, /*InsnID*/0,
        GIR_EraseFromParent, /*InsnID*/0,
        // GIR_Coverage, 5026,
        GIR_Done,
      // Label 6311: @462628
      GIM_Try, /*On fail goto*//*Label 6312*/ GIMT_Encode4(462702), // Rule ID 5034 //
        GIM_CheckRegBankForClass, /*MI*/0, /*Op*/0, /*RC*/GIMT_Encode2(AMDGPU::AV_64RegClassID),
        GIM_CheckConstantInt8, /*MI*/0, /*Op*/4, 0,
        // MIs[0] offset
        GIM_CheckIsImm, /*MI*/0, /*Op*/6,
        // MIs[0] auxiliary
        GIM_CheckIsImm, /*MI*/0, /*Op*/7,
        // MIs[0] Operand 8
        GIM_CheckIsImm, /*MI*/0, /*Op*/8,
        GIM_CheckComplexPattern, /*MI*/0, /*Op*/5, /*Renderer*/GIMT_Encode2(0), GIMT_Encode2(GICP_gi_buf_soffset),
        // (SIbuffer_atomic_umax:{ *:[i64] } i64:{ *:[i64] }:$vdata_in, v4i32:{ *:[v4i32] }:$rsrc, i32:{ *:[i32] }:$vindex, 0:{ *:[i32] }, (BUFSOffset:{ *:[i32] } i32:{ *:[i32] }:$soffset), (timm:{ *:[i32] }):$offset, (timm:{ *:[i32] }):$auxiliary, (timm:{ *:[i1] }))  =>  (BUFFER_ATOMIC_UMAX_X2_VBUFFER_IDXEN_RTN:{ *:[i64] } anonymous_15036:{ *:[i64] }:$vdata_in, VGPR_32:{ *:[i32] }:$vindex, SReg_128:{ *:[v4i32] }:$rsrc, SCSrc_b32:{ *:[i32] }:$soffset, (timm:{ *:[i32] }):$offset, (extract_cpol_set_glc:{ *:[i32] } ?:{ *:[i32] }:$auxiliary))
        GIR_BuildMI, /*InsnID*/0, /*Opcode*/GIMT_Encode2(AMDGPU::BUFFER_ATOMIC_UMAX_X2_VBUFFER_IDXEN_RTN),
        GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/0, // DstI[vdata]
        GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/1, // vdata_in
        GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/3, // vindex
        GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/2, // rsrc
        GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/0, // soffset
        GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/6, // offset
        GIR_CustomOperandRenderer, /*InsnID*/0, /*OldInsnID*/0, /*OpIdx*/7, /*OperandRenderer*/GIMT_Encode2(GICR_renderExtractCpolSetGLC), // auxiliary
        GIR_MergeMemOperands, /*InsnID*/0, /*NumInsns*/1, /*MergeInsnID's*/0,
        GIR_ConstrainSelectedInstOperands, /*InsnID*/0,
        GIR_EraseFromParent, /*InsnID*/0,
        // GIR_Coverage, 5034,
        GIR_Done,
      // Label 6312: @462702
      GIM_Try, /*On fail goto*//*Label 6313*/ GIMT_Encode4(462808), // Rule ID 5032 //
        GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasUnrestrictedSOffset),
        GIM_CheckHasNoUse, /*MI*/0,
        // MIs[0] offset
        GIM_CheckIsImm, /*MI*/0, /*Op*/6,
        // MIs[0] auxiliary
        GIM_CheckIsImm, /*MI*/0, /*Op*/7,
        // MIs[0] Operand 8
        GIM_CheckIsImm, /*MI*/0, /*Op*/8,
        GIM_CheckComplexPattern, /*MI*/0, /*Op*/5, /*Renderer*/GIMT_Encode2(0), GIMT_Encode2(GICP_gi_buf_soffset),
        // (SIbuffer_atomic_umax:{ *:[i64] } i64:{ *:[i64] }:$vdata_in, v4i32:{ *:[v4i32] }:$rsrc, i32:{ *:[i32] }:$vindex, i32:{ *:[i32] }:$voffset, (BUFSOffset:{ *:[i32] } i32:{ *:[i32] }:$soffset), (timm:{ *:[i32] }):$offset, (timm:{ *:[i32] }):$auxiliary, (timm:{ *:[i1] }))<<P:Predicate_SIbuffer_atomic_umax_noret>>  =>  (BUFFER_ATOMIC_UMAX_X2_BOTHEN anonymous_15036:{ *:[i64] }:$vdata_in, (REG_SEQUENCE:{ *:[i64] } VReg_64:{ *:[i32] }, VGPR_32:{ *:[i32] }:$vindex, sub0:{ *:[i32] }, VGPR_32:{ *:[i32] }:$voffset, sub1:{ *:[i32] }), SReg_128:{ *:[v4i32] }:$rsrc, SCSrc_b32:{ *:[i32] }:$soffset, (timm:{ *:[i32] }):$offset, (extract_cpol:{ *:[i32] } ?:{ *:[i32] }:$auxiliary))
        GIR_MakeTempReg, /*TempRegID*/0, /*TypeID*/GILLT_s64,
        GIR_BuildMI, /*InsnID*/1, /*Opcode*/GIMT_Encode2(TargetOpcode::REG_SEQUENCE),
        GIR_AddTempRegister, /*InsnID*/1, /*TempRegID*/0, /*TempRegFlags*/GIMT_Encode2(RegState::Define),
        GIR_Copy, /*NewInsnID*/1, /*OldInsnID*/0, /*OpIdx*/3, // vindex
        GIR_AddImm8, /*InsnID*/1, /*SubRegIndex*/3,
        GIR_Copy, /*NewInsnID*/1, /*OldInsnID*/0, /*OpIdx*/4, // voffset
        GIR_AddImm8, /*InsnID*/1, /*SubRegIndex*/11,
        GIR_ConstrainOperandRC, /*InsnID*/1, /*Op*/0, GIMT_Encode2(AMDGPU::VReg_64RegClassID),
        GIR_ConstrainOperandRC, /*InsnID*/1, /*Op*/1, GIMT_Encode2(AMDGPU::VGPR_32RegClassID),
        GIR_ConstrainOperandRC, /*InsnID*/1, /*Op*/3, GIMT_Encode2(AMDGPU::VGPR_32RegClassID),
        GIR_BuildMI, /*InsnID*/0, /*Opcode*/GIMT_Encode2(AMDGPU::BUFFER_ATOMIC_UMAX_X2_BOTHEN),
        GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/1, // vdata_in
        GIR_AddSimpleTempRegister, /*InsnID*/0, /*TempRegID*/0,
        GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/2, // rsrc
        GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/0, // soffset
        GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/6, // offset
        GIR_CustomOperandRenderer, /*InsnID*/0, /*OldInsnID*/0, /*OpIdx*/7, /*OperandRenderer*/GIMT_Encode2(GICR_renderExtractCPol), // auxiliary
        GIR_MergeMemOperands, /*InsnID*/0, /*NumInsns*/1, /*MergeInsnID's*/0,
        GIR_ConstrainSelectedInstOperands, /*InsnID*/0,
        GIR_EraseFromParent, /*InsnID*/0,
        // GIR_Coverage, 5032,
        GIR_Done,
      // Label 6313: @462808
      GIM_Try, /*On fail goto*//*Label 6314*/ GIMT_Encode4(462911), // Rule ID 5040 //
        GIM_CheckHasNoUse, /*MI*/0,
        // MIs[0] offset
        GIM_CheckIsImm, /*MI*/0, /*Op*/6,
        // MIs[0] auxiliary
        GIM_CheckIsImm, /*MI*/0, /*Op*/7,
        // MIs[0] Operand 8
        GIM_CheckIsImm, /*MI*/0, /*Op*/8,
        GIM_CheckComplexPattern, /*MI*/0, /*Op*/5, /*Renderer*/GIMT_Encode2(0), GIMT_Encode2(GICP_gi_buf_soffset),
        // (SIbuffer_atomic_umax:{ *:[i64] } i64:{ *:[i64] }:$vdata_in, v4i32:{ *:[v4i32] }:$rsrc, i32:{ *:[i32] }:$vindex, i32:{ *:[i32] }:$voffset, (BUFSOffset:{ *:[i32] } i32:{ *:[i32] }:$soffset), (timm:{ *:[i32] }):$offset, (timm:{ *:[i32] }):$auxiliary, (timm:{ *:[i1] }))<<P:Predicate_SIbuffer_atomic_umax_noret>>  =>  (BUFFER_ATOMIC_UMAX_X2_VBUFFER_BOTHEN anonymous_15036:{ *:[i64] }:$vdata_in, (REG_SEQUENCE:{ *:[i64] } VReg_64:{ *:[i32] }, VGPR_32:{ *:[i32] }:$vindex, sub0:{ *:[i32] }, VGPR_32:{ *:[i32] }:$voffset, sub1:{ *:[i32] }), SReg_128:{ *:[v4i32] }:$rsrc, SCSrc_b32:{ *:[i32] }:$soffset, (timm:{ *:[i32] }):$offset, (extract_cpol:{ *:[i32] } ?:{ *:[i32] }:$auxiliary))
        GIR_MakeTempReg, /*TempRegID*/0, /*TypeID*/GILLT_s64,
        GIR_BuildMI, /*InsnID*/1, /*Opcode*/GIMT_Encode2(TargetOpcode::REG_SEQUENCE),
        GIR_AddTempRegister, /*InsnID*/1, /*TempRegID*/0, /*TempRegFlags*/GIMT_Encode2(RegState::Define),
        GIR_Copy, /*NewInsnID*/1, /*OldInsnID*/0, /*OpIdx*/3, // vindex
        GIR_AddImm8, /*InsnID*/1, /*SubRegIndex*/3,
        GIR_Copy, /*NewInsnID*/1, /*OldInsnID*/0, /*OpIdx*/4, // voffset
        GIR_AddImm8, /*InsnID*/1, /*SubRegIndex*/11,
        GIR_ConstrainOperandRC, /*InsnID*/1, /*Op*/0, GIMT_Encode2(AMDGPU::VReg_64RegClassID),
        GIR_ConstrainOperandRC, /*InsnID*/1, /*Op*/1, GIMT_Encode2(AMDGPU::VGPR_32RegClassID),
        GIR_ConstrainOperandRC, /*InsnID*/1, /*Op*/3, GIMT_Encode2(AMDGPU::VGPR_32RegClassID),
        GIR_BuildMI, /*InsnID*/0, /*Opcode*/GIMT_Encode2(AMDGPU::BUFFER_ATOMIC_UMAX_X2_VBUFFER_BOTHEN),
        GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/1, // vdata_in
        GIR_AddSimpleTempRegister, /*InsnID*/0, /*TempRegID*/0,
        GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/2, // rsrc
        GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/0, // soffset
        GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/6, // offset
        GIR_CustomOperandRenderer, /*InsnID*/0, /*OldInsnID*/0, /*OpIdx*/7, /*OperandRenderer*/GIMT_Encode2(GICR_renderExtractCPol), // auxiliary
        GIR_MergeMemOperands, /*InsnID*/0, /*NumInsns*/1, /*MergeInsnID's*/0,
        GIR_ConstrainSelectedInstOperands, /*InsnID*/0,
        GIR_EraseFromParent, /*InsnID*/0,
        // GIR_Coverage, 5040,
        GIR_Done,
      // Label 6314: @462911
      GIM_Try, /*On fail goto*//*Label 6315*/ GIMT_Encode4(463024), // Rule ID 5028 //
        GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasUnrestrictedSOffset),
        GIM_CheckRegBankForClass, /*MI*/0, /*Op*/0, /*RC*/GIMT_Encode2(AMDGPU::AV_64RegClassID),
        // MIs[0] offset
        GIM_CheckIsImm, /*MI*/0, /*Op*/6,
        // MIs[0] auxiliary
        GIM_CheckIsImm, /*MI*/0, /*Op*/7,
        // MIs[0] Operand 8
        GIM_CheckIsImm, /*MI*/0, /*Op*/8,
        GIM_CheckComplexPattern, /*MI*/0, /*Op*/5, /*Renderer*/GIMT_Encode2(0), GIMT_Encode2(GICP_gi_buf_soffset),
        // (SIbuffer_atomic_umax:{ *:[i64] } i64:{ *:[i64] }:$vdata_in, v4i32:{ *:[v4i32] }:$rsrc, i32:{ *:[i32] }:$vindex, i32:{ *:[i32] }:$voffset, (BUFSOffset:{ *:[i32] } i32:{ *:[i32] }:$soffset), (timm:{ *:[i32] }):$offset, (timm:{ *:[i32] }):$auxiliary, (timm:{ *:[i1] }))  =>  (BUFFER_ATOMIC_UMAX_X2_BOTHEN_RTN:{ *:[i64] } anonymous_15036:{ *:[i64] }:$vdata_in, (REG_SEQUENCE:{ *:[i64] } VReg_64:{ *:[i32] }, VGPR_32:{ *:[i32] }:$vindex, sub0:{ *:[i32] }, VGPR_32:{ *:[i32] }:$voffset, sub1:{ *:[i32] }), SReg_128:{ *:[v4i32] }:$rsrc, SCSrc_b32:{ *:[i32] }:$soffset, (timm:{ *:[i32] }):$offset, (extract_cpol_set_glc:{ *:[i32] } ?:{ *:[i32] }:$auxiliary))
        GIR_MakeTempReg, /*TempRegID*/0, /*TypeID*/GILLT_s64,
        GIR_BuildMI, /*InsnID*/1, /*Opcode*/GIMT_Encode2(TargetOpcode::REG_SEQUENCE),
        GIR_AddTempRegister, /*InsnID*/1, /*TempRegID*/0, /*TempRegFlags*/GIMT_Encode2(RegState::Define),
        GIR_Copy, /*NewInsnID*/1, /*OldInsnID*/0, /*OpIdx*/3, // vindex
        GIR_AddImm8, /*InsnID*/1, /*SubRegIndex*/3,
        GIR_Copy, /*NewInsnID*/1, /*OldInsnID*/0, /*OpIdx*/4, // voffset
        GIR_AddImm8, /*InsnID*/1, /*SubRegIndex*/11,
        GIR_ConstrainOperandRC, /*InsnID*/1, /*Op*/0, GIMT_Encode2(AMDGPU::VReg_64RegClassID),
        GIR_ConstrainOperandRC, /*InsnID*/1, /*Op*/1, GIMT_Encode2(AMDGPU::VGPR_32RegClassID),
        GIR_ConstrainOperandRC, /*InsnID*/1, /*Op*/3, GIMT_Encode2(AMDGPU::VGPR_32RegClassID),
        GIR_BuildMI, /*InsnID*/0, /*Opcode*/GIMT_Encode2(AMDGPU::BUFFER_ATOMIC_UMAX_X2_BOTHEN_RTN),
        GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/0, // DstI[vdata]
        GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/1, // vdata_in
        GIR_AddSimpleTempRegister, /*InsnID*/0, /*TempRegID*/0,
        GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/2, // rsrc
        GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/0, // soffset
        GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/6, // offset
        GIR_CustomOperandRenderer, /*InsnID*/0, /*OldInsnID*/0, /*OpIdx*/7, /*OperandRenderer*/GIMT_Encode2(GICR_renderExtractCpolSetGLC), // auxiliary
        GIR_MergeMemOperands, /*InsnID*/0, /*NumInsns*/1, /*MergeInsnID's*/0,
        GIR_ConstrainSelectedInstOperands, /*InsnID*/0,
        GIR_EraseFromParent, /*InsnID*/0,
        // GIR_Coverage, 5028,
        GIR_Done,
      // Label 6315: @463024
      GIM_Try, /*On fail goto*//*Label 6316*/ GIMT_Encode4(463134), // Rule ID 5036 //
        GIM_CheckRegBankForClass, /*MI*/0, /*Op*/0, /*RC*/GIMT_Encode2(AMDGPU::AV_64RegClassID),
        // MIs[0] offset
        GIM_CheckIsImm, /*MI*/0, /*Op*/6,
        // MIs[0] auxiliary
        GIM_CheckIsImm, /*MI*/0, /*Op*/7,
        // MIs[0] Operand 8
        GIM_CheckIsImm, /*MI*/0, /*Op*/8,
        GIM_CheckComplexPattern, /*MI*/0, /*Op*/5, /*Renderer*/GIMT_Encode2(0), GIMT_Encode2(GICP_gi_buf_soffset),
        // (SIbuffer_atomic_umax:{ *:[i64] } i64:{ *:[i64] }:$vdata_in, v4i32:{ *:[v4i32] }:$rsrc, i32:{ *:[i32] }:$vindex, i32:{ *:[i32] }:$voffset, (BUFSOffset:{ *:[i32] } i32:{ *:[i32] }:$soffset), (timm:{ *:[i32] }):$offset, (timm:{ *:[i32] }):$auxiliary, (timm:{ *:[i1] }))  =>  (BUFFER_ATOMIC_UMAX_X2_VBUFFER_BOTHEN_RTN:{ *:[i64] } anonymous_15036:{ *:[i64] }:$vdata_in, (REG_SEQUENCE:{ *:[i64] } VReg_64:{ *:[i32] }, VGPR_32:{ *:[i32] }:$vindex, sub0:{ *:[i32] }, VGPR_32:{ *:[i32] }:$voffset, sub1:{ *:[i32] }), SReg_128:{ *:[v4i32] }:$rsrc, SCSrc_b32:{ *:[i32] }:$soffset, (timm:{ *:[i32] }):$offset, (extract_cpol_set_glc:{ *:[i32] } ?:{ *:[i32] }:$auxiliary))
        GIR_MakeTempReg, /*TempRegID*/0, /*TypeID*/GILLT_s64,
        GIR_BuildMI, /*InsnID*/1, /*Opcode*/GIMT_Encode2(TargetOpcode::REG_SEQUENCE),
        GIR_AddTempRegister, /*InsnID*/1, /*TempRegID*/0, /*TempRegFlags*/GIMT_Encode2(RegState::Define),
        GIR_Copy, /*NewInsnID*/1, /*OldInsnID*/0, /*OpIdx*/3, // vindex
        GIR_AddImm8, /*InsnID*/1, /*SubRegIndex*/3,
        GIR_Copy, /*NewInsnID*/1, /*OldInsnID*/0, /*OpIdx*/4, // voffset
        GIR_AddImm8, /*InsnID*/1, /*SubRegIndex*/11,
        GIR_ConstrainOperandRC, /*InsnID*/1, /*Op*/0, GIMT_Encode2(AMDGPU::VReg_64RegClassID),
        GIR_ConstrainOperandRC, /*InsnID*/1, /*Op*/1, GIMT_Encode2(AMDGPU::VGPR_32RegClassID),
        GIR_ConstrainOperandRC, /*InsnID*/1, /*Op*/3, GIMT_Encode2(AMDGPU::VGPR_32RegClassID),
        GIR_BuildMI, /*InsnID*/0, /*Opcode*/GIMT_Encode2(AMDGPU::BUFFER_ATOMIC_UMAX_X2_VBUFFER_BOTHEN_RTN),
        GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/0, // DstI[vdata]
        GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/1, // vdata_in
        GIR_AddSimpleTempRegister, /*InsnID*/0, /*TempRegID*/0,
        GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/2, // rsrc
        GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/0, // soffset
        GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/6, // offset
        GIR_CustomOperandRenderer, /*InsnID*/0, /*OldInsnID*/0, /*OpIdx*/7, /*OperandRenderer*/GIMT_Encode2(GICR_renderExtractCpolSetGLC), // auxiliary
        GIR_MergeMemOperands, /*InsnID*/0, /*NumInsns*/1, /*MergeInsnID's*/0,
        GIR_ConstrainSelectedInstOperands, /*InsnID*/0,
        GIR_EraseFromParent, /*InsnID*/0,
        // GIR_Coverage, 5036,
        GIR_Done,
      // Label 6316: @463134
      GIM_Reject,
    // Label 6300: @463135
    GIM_Reject,
    // Label 6282: @463136
    GIM_Reject,
    // Label 122: @463137
    GIM_SwitchType, /*MI*/0, /*Op*/0, /*[*/GIMT_Encode2(9), GIMT_Encode2(11), /*)*//*default:*//*Label 6319*/ GIMT_Encode4(465930),
    /*GILLT_s32*//*Label 6317*/ GIMT_Encode4(463156),
    /*GILLT_s64*//*Label 6318*/ GIMT_Encode4(464543),
    // Label 6317: @463156
    GIM_Try, /*On fail goto*//*Label 6320*/ GIMT_Encode4(464542),
      GIM_CheckType, /*MI*/0, /*Op*/1, /*Type*/GILLT_s32,
      GIM_CheckType, /*MI*/0, /*Op*/2, /*Type*/GILLT_v4s32,
      GIM_CheckType, /*MI*/0, /*Op*/3, /*Type*/GILLT_s32,
      GIM_CheckType, /*MI*/0, /*Op*/4, /*Type*/GILLT_s32,
      GIM_CheckType, /*MI*/0, /*Op*/5, /*Type*/GILLT_s32,
      GIM_Try, /*On fail goto*//*Label 6321*/ GIMT_Encode4(463259), // Rule ID 4797 //
        GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasUnrestrictedSOffset),
        GIM_CheckHasNoUse, /*MI*/0,
        GIM_CheckConstantInt8, /*MI*/0, /*Op*/3, 0,
        GIM_CheckConstantInt8, /*MI*/0, /*Op*/4, 0,
        // MIs[0] offset
        GIM_CheckIsImm, /*MI*/0, /*Op*/6,
        // MIs[0] auxiliary
        GIM_CheckIsImm, /*MI*/0, /*Op*/7,
        // MIs[0] Operand 8
        GIM_CheckLiteralInt, /*MI*/0, /*Op*/8, GIMT_Encode8(0),
        GIM_CheckComplexPattern, /*MI*/0, /*Op*/5, /*Renderer*/GIMT_Encode2(0), GIMT_Encode2(GICP_gi_buf_soffset),
        // (SIbuffer_atomic_umin:{ *:[i32] } i32:{ *:[i32] }:$vdata_in, v4i32:{ *:[v4i32] }:$rsrc, 0:{ *:[i32] }, 0:{ *:[i32] }, (BUFSOffset:{ *:[i32] } i32:{ *:[i32] }:$soffset), (timm:{ *:[i32] }):$offset, (timm:{ *:[i32] }):$auxiliary, 0:{ *:[i1] })<<P:Predicate_SIbuffer_atomic_umin_noret>>  =>  (BUFFER_ATOMIC_UMIN_OFFSET anonymous_15037:{ *:[i32] }:$vdata_in, SReg_128:{ *:[v4i32] }:$rsrc, SCSrc_b32:{ *:[i32] }:$soffset, (timm:{ *:[i32] }):$offset, (extract_cpol:{ *:[i32] } ?:{ *:[i32] }:$auxiliary))
        GIR_BuildMI, /*InsnID*/0, /*Opcode*/GIMT_Encode2(AMDGPU::BUFFER_ATOMIC_UMIN_OFFSET),
        GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/1, // vdata_in
        GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/2, // rsrc
        GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/0, // soffset
        GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/6, // offset
        GIR_CustomOperandRenderer, /*InsnID*/0, /*OldInsnID*/0, /*OpIdx*/7, /*OperandRenderer*/GIMT_Encode2(GICR_renderExtractCPol), // auxiliary
        GIR_MergeMemOperands, /*InsnID*/0, /*NumInsns*/1, /*MergeInsnID's*/0,
        GIR_ConstrainSelectedInstOperands, /*InsnID*/0,
        GIR_EraseFromParent, /*InsnID*/0,
        // GIR_Coverage, 4797,
        GIR_Done,
      // Label 6321: @463259
      GIM_Try, /*On fail goto*//*Label 6322*/ GIMT_Encode4(463334), // Rule ID 4805 //
        GIM_CheckHasNoUse, /*MI*/0,
        GIM_CheckConstantInt8, /*MI*/0, /*Op*/3, 0,
        GIM_CheckConstantInt8, /*MI*/0, /*Op*/4, 0,
        // MIs[0] offset
        GIM_CheckIsImm, /*MI*/0, /*Op*/6,
        // MIs[0] auxiliary
        GIM_CheckIsImm, /*MI*/0, /*Op*/7,
        // MIs[0] Operand 8
        GIM_CheckLiteralInt, /*MI*/0, /*Op*/8, GIMT_Encode8(0),
        GIM_CheckComplexPattern, /*MI*/0, /*Op*/5, /*Renderer*/GIMT_Encode2(0), GIMT_Encode2(GICP_gi_buf_soffset),
        // (SIbuffer_atomic_umin:{ *:[i32] } i32:{ *:[i32] }:$vdata_in, v4i32:{ *:[v4i32] }:$rsrc, 0:{ *:[i32] }, 0:{ *:[i32] }, (BUFSOffset:{ *:[i32] } i32:{ *:[i32] }:$soffset), (timm:{ *:[i32] }):$offset, (timm:{ *:[i32] }):$auxiliary, 0:{ *:[i1] })<<P:Predicate_SIbuffer_atomic_umin_noret>>  =>  (BUFFER_ATOMIC_UMIN_VBUFFER_OFFSET anonymous_15037:{ *:[i32] }:$vdata_in, SReg_128:{ *:[v4i32] }:$rsrc, SCSrc_b32:{ *:[i32] }:$soffset, (timm:{ *:[i32] }):$offset, (extract_cpol:{ *:[i32] } ?:{ *:[i32] }:$auxiliary))
        GIR_BuildMI, /*InsnID*/0, /*Opcode*/GIMT_Encode2(AMDGPU::BUFFER_ATOMIC_UMIN_VBUFFER_OFFSET),
        GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/1, // vdata_in
        GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/2, // rsrc
        GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/0, // soffset
        GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/6, // offset
        GIR_CustomOperandRenderer, /*InsnID*/0, /*OldInsnID*/0, /*OpIdx*/7, /*OperandRenderer*/GIMT_Encode2(GICR_renderExtractCPol), // auxiliary
        GIR_MergeMemOperands, /*InsnID*/0, /*NumInsns*/1, /*MergeInsnID's*/0,
        GIR_ConstrainSelectedInstOperands, /*InsnID*/0,
        GIR_EraseFromParent, /*InsnID*/0,
        // GIR_Coverage, 4805,
        GIR_Done,
      // Label 6322: @463334
      GIM_Try, /*On fail goto*//*Label 6323*/ GIMT_Encode4(463419), // Rule ID 4793 //
        GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasUnrestrictedSOffset),
        GIM_CheckRegBankForClass, /*MI*/0, /*Op*/0, /*RC*/GIMT_Encode2(AMDGPU::AV_32RegClassID),
        GIM_CheckConstantInt8, /*MI*/0, /*Op*/3, 0,
        GIM_CheckConstantInt8, /*MI*/0, /*Op*/4, 0,
        // MIs[0] offset
        GIM_CheckIsImm, /*MI*/0, /*Op*/6,
        // MIs[0] auxiliary
        GIM_CheckIsImm, /*MI*/0, /*Op*/7,
        // MIs[0] Operand 8
        GIM_CheckLiteralInt, /*MI*/0, /*Op*/8, GIMT_Encode8(0),
        GIM_CheckComplexPattern, /*MI*/0, /*Op*/5, /*Renderer*/GIMT_Encode2(0), GIMT_Encode2(GICP_gi_buf_soffset),
        // (SIbuffer_atomic_umin:{ *:[i32] } i32:{ *:[i32] }:$vdata_in, v4i32:{ *:[v4i32] }:$rsrc, 0:{ *:[i32] }, 0:{ *:[i32] }, (BUFSOffset:{ *:[i32] } i32:{ *:[i32] }:$soffset), (timm:{ *:[i32] }):$offset, (timm:{ *:[i32] }):$auxiliary, 0:{ *:[i1] })  =>  (BUFFER_ATOMIC_UMIN_OFFSET_RTN:{ *:[i32] } anonymous_15037:{ *:[i32] }:$vdata_in, SReg_128:{ *:[v4i32] }:$rsrc, SCSrc_b32:{ *:[i32] }:$soffset, (timm:{ *:[i32] }):$offset, (extract_cpol_set_glc:{ *:[i32] } ?:{ *:[i32] }:$auxiliary))
        GIR_BuildMI, /*InsnID*/0, /*Opcode*/GIMT_Encode2(AMDGPU::BUFFER_ATOMIC_UMIN_OFFSET_RTN),
        GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/0, // DstI[vdata]
        GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/1, // vdata_in
        GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/2, // rsrc
        GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/0, // soffset
        GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/6, // offset
        GIR_CustomOperandRenderer, /*InsnID*/0, /*OldInsnID*/0, /*OpIdx*/7, /*OperandRenderer*/GIMT_Encode2(GICR_renderExtractCpolSetGLC), // auxiliary
        GIR_MergeMemOperands, /*InsnID*/0, /*NumInsns*/1, /*MergeInsnID's*/0,
        GIR_ConstrainSelectedInstOperands, /*InsnID*/0,
        GIR_EraseFromParent, /*InsnID*/0,
        // GIR_Coverage, 4793,
        GIR_Done,
      // Label 6323: @463419
      GIM_Try, /*On fail goto*//*Label 6324*/ GIMT_Encode4(463501), // Rule ID 4801 //
        GIM_CheckRegBankForClass, /*MI*/0, /*Op*/0, /*RC*/GIMT_Encode2(AMDGPU::AV_32RegClassID),
        GIM_CheckConstantInt8, /*MI*/0, /*Op*/3, 0,
        GIM_CheckConstantInt8, /*MI*/0, /*Op*/4, 0,
        // MIs[0] offset
        GIM_CheckIsImm, /*MI*/0, /*Op*/6,
        // MIs[0] auxiliary
        GIM_CheckIsImm, /*MI*/0, /*Op*/7,
        // MIs[0] Operand 8
        GIM_CheckLiteralInt, /*MI*/0, /*Op*/8, GIMT_Encode8(0),
        GIM_CheckComplexPattern, /*MI*/0, /*Op*/5, /*Renderer*/GIMT_Encode2(0), GIMT_Encode2(GICP_gi_buf_soffset),
        // (SIbuffer_atomic_umin:{ *:[i32] } i32:{ *:[i32] }:$vdata_in, v4i32:{ *:[v4i32] }:$rsrc, 0:{ *:[i32] }, 0:{ *:[i32] }, (BUFSOffset:{ *:[i32] } i32:{ *:[i32] }:$soffset), (timm:{ *:[i32] }):$offset, (timm:{ *:[i32] }):$auxiliary, 0:{ *:[i1] })  =>  (BUFFER_ATOMIC_UMIN_VBUFFER_OFFSET_RTN:{ *:[i32] } anonymous_15037:{ *:[i32] }:$vdata_in, SReg_128:{ *:[v4i32] }:$rsrc, SCSrc_b32:{ *:[i32] }:$soffset, (timm:{ *:[i32] }):$offset, (extract_cpol_set_glc:{ *:[i32] } ?:{ *:[i32] }:$auxiliary))
        GIR_BuildMI, /*InsnID*/0, /*Opcode*/GIMT_Encode2(AMDGPU::BUFFER_ATOMIC_UMIN_VBUFFER_OFFSET_RTN),
        GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/0, // DstI[vdata]
        GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/1, // vdata_in
        GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/2, // rsrc
        GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/0, // soffset
        GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/6, // offset
        GIR_CustomOperandRenderer, /*InsnID*/0, /*OldInsnID*/0, /*OpIdx*/7, /*OperandRenderer*/GIMT_Encode2(GICR_renderExtractCpolSetGLC), // auxiliary
        GIR_MergeMemOperands, /*InsnID*/0, /*NumInsns*/1, /*MergeInsnID's*/0,
        GIR_ConstrainSelectedInstOperands, /*InsnID*/0,
        GIR_EraseFromParent, /*InsnID*/0,
        // GIR_Coverage, 4801,
        GIR_Done,
      // Label 6324: @463501
      GIM_Try, /*On fail goto*//*Label 6325*/ GIMT_Encode4(463579), // Rule ID 4799 //
        GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasUnrestrictedSOffset),
        GIM_CheckHasNoUse, /*MI*/0,
        GIM_CheckConstantInt8, /*MI*/0, /*Op*/3, 0,
        // MIs[0] offset
        GIM_CheckIsImm, /*MI*/0, /*Op*/6,
        // MIs[0] auxiliary
        GIM_CheckIsImm, /*MI*/0, /*Op*/7,
        // MIs[0] Operand 8
        GIM_CheckLiteralInt, /*MI*/0, /*Op*/8, GIMT_Encode8(0),
        GIM_CheckComplexPattern, /*MI*/0, /*Op*/5, /*Renderer*/GIMT_Encode2(0), GIMT_Encode2(GICP_gi_buf_soffset),
        // (SIbuffer_atomic_umin:{ *:[i32] } i32:{ *:[i32] }:$vdata_in, v4i32:{ *:[v4i32] }:$rsrc, 0:{ *:[i32] }, i32:{ *:[i32] }:$voffset, (BUFSOffset:{ *:[i32] } i32:{ *:[i32] }:$soffset), (timm:{ *:[i32] }):$offset, (timm:{ *:[i32] }):$auxiliary, 0:{ *:[i1] })<<P:Predicate_SIbuffer_atomic_umin_noret>>  =>  (BUFFER_ATOMIC_UMIN_OFFEN anonymous_15037:{ *:[i32] }:$vdata_in, VGPR_32:{ *:[i32] }:$voffset, SReg_128:{ *:[v4i32] }:$rsrc, SCSrc_b32:{ *:[i32] }:$soffset, (timm:{ *:[i32] }):$offset, (extract_cpol:{ *:[i32] } ?:{ *:[i32] }:$auxiliary))
        GIR_BuildMI, /*InsnID*/0, /*Opcode*/GIMT_Encode2(AMDGPU::BUFFER_ATOMIC_UMIN_OFFEN),
        GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/1, // vdata_in
        GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/4, // voffset
        GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/2, // rsrc
        GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/0, // soffset
        GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/6, // offset
        GIR_CustomOperandRenderer, /*InsnID*/0, /*OldInsnID*/0, /*OpIdx*/7, /*OperandRenderer*/GIMT_Encode2(GICR_renderExtractCPol), // auxiliary
        GIR_MergeMemOperands, /*InsnID*/0, /*NumInsns*/1, /*MergeInsnID's*/0,
        GIR_ConstrainSelectedInstOperands, /*InsnID*/0,
        GIR_EraseFromParent, /*InsnID*/0,
        // GIR_Coverage, 4799,
        GIR_Done,
      // Label 6325: @463579
      GIM_Try, /*On fail goto*//*Label 6326*/ GIMT_Encode4(463654), // Rule ID 4807 //
        GIM_CheckHasNoUse, /*MI*/0,
        GIM_CheckConstantInt8, /*MI*/0, /*Op*/3, 0,
        // MIs[0] offset
        GIM_CheckIsImm, /*MI*/0, /*Op*/6,
        // MIs[0] auxiliary
        GIM_CheckIsImm, /*MI*/0, /*Op*/7,
        // MIs[0] Operand 8
        GIM_CheckLiteralInt, /*MI*/0, /*Op*/8, GIMT_Encode8(0),
        GIM_CheckComplexPattern, /*MI*/0, /*Op*/5, /*Renderer*/GIMT_Encode2(0), GIMT_Encode2(GICP_gi_buf_soffset),
        // (SIbuffer_atomic_umin:{ *:[i32] } i32:{ *:[i32] }:$vdata_in, v4i32:{ *:[v4i32] }:$rsrc, 0:{ *:[i32] }, i32:{ *:[i32] }:$voffset, (BUFSOffset:{ *:[i32] } i32:{ *:[i32] }:$soffset), (timm:{ *:[i32] }):$offset, (timm:{ *:[i32] }):$auxiliary, 0:{ *:[i1] })<<P:Predicate_SIbuffer_atomic_umin_noret>>  =>  (BUFFER_ATOMIC_UMIN_VBUFFER_OFFEN anonymous_15037:{ *:[i32] }:$vdata_in, VGPR_32:{ *:[i32] }:$voffset, SReg_128:{ *:[v4i32] }:$rsrc, SCSrc_b32:{ *:[i32] }:$soffset, (timm:{ *:[i32] }):$offset, (extract_cpol:{ *:[i32] } ?:{ *:[i32] }:$auxiliary))
        GIR_BuildMI, /*InsnID*/0, /*Opcode*/GIMT_Encode2(AMDGPU::BUFFER_ATOMIC_UMIN_VBUFFER_OFFEN),
        GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/1, // vdata_in
        GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/4, // voffset
        GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/2, // rsrc
        GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/0, // soffset
        GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/6, // offset
        GIR_CustomOperandRenderer, /*InsnID*/0, /*OldInsnID*/0, /*OpIdx*/7, /*OperandRenderer*/GIMT_Encode2(GICR_renderExtractCPol), // auxiliary
        GIR_MergeMemOperands, /*InsnID*/0, /*NumInsns*/1, /*MergeInsnID's*/0,
        GIR_ConstrainSelectedInstOperands, /*InsnID*/0,
        GIR_EraseFromParent, /*InsnID*/0,
        // GIR_Coverage, 4807,
        GIR_Done,
      // Label 6326: @463654
      GIM_Try, /*On fail goto*//*Label 6327*/ GIMT_Encode4(463739), // Rule ID 4795 //
        GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasUnrestrictedSOffset),
        GIM_CheckRegBankForClass, /*MI*/0, /*Op*/0, /*RC*/GIMT_Encode2(AMDGPU::AV_32RegClassID),
        GIM_CheckConstantInt8, /*MI*/0, /*Op*/3, 0,
        // MIs[0] offset
        GIM_CheckIsImm, /*MI*/0, /*Op*/6,
        // MIs[0] auxiliary
        GIM_CheckIsImm, /*MI*/0, /*Op*/7,
        // MIs[0] Operand 8
        GIM_CheckLiteralInt, /*MI*/0, /*Op*/8, GIMT_Encode8(0),
        GIM_CheckComplexPattern, /*MI*/0, /*Op*/5, /*Renderer*/GIMT_Encode2(0), GIMT_Encode2(GICP_gi_buf_soffset),
        // (SIbuffer_atomic_umin:{ *:[i32] } i32:{ *:[i32] }:$vdata_in, v4i32:{ *:[v4i32] }:$rsrc, 0:{ *:[i32] }, i32:{ *:[i32] }:$voffset, (BUFSOffset:{ *:[i32] } i32:{ *:[i32] }:$soffset), (timm:{ *:[i32] }):$offset, (timm:{ *:[i32] }):$auxiliary, 0:{ *:[i1] })  =>  (BUFFER_ATOMIC_UMIN_OFFEN_RTN:{ *:[i32] } anonymous_15037:{ *:[i32] }:$vdata_in, VGPR_32:{ *:[i32] }:$voffset, SReg_128:{ *:[v4i32] }:$rsrc, SCSrc_b32:{ *:[i32] }:$soffset, (timm:{ *:[i32] }):$offset, (extract_cpol_set_glc:{ *:[i32] } ?:{ *:[i32] }:$auxiliary))
        GIR_BuildMI, /*InsnID*/0, /*Opcode*/GIMT_Encode2(AMDGPU::BUFFER_ATOMIC_UMIN_OFFEN_RTN),
        GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/0, // DstI[vdata]
        GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/1, // vdata_in
        GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/4, // voffset
        GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/2, // rsrc
        GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/0, // soffset
        GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/6, // offset
        GIR_CustomOperandRenderer, /*InsnID*/0, /*OldInsnID*/0, /*OpIdx*/7, /*OperandRenderer*/GIMT_Encode2(GICR_renderExtractCpolSetGLC), // auxiliary
        GIR_MergeMemOperands, /*InsnID*/0, /*NumInsns*/1, /*MergeInsnID's*/0,
        GIR_ConstrainSelectedInstOperands, /*InsnID*/0,
        GIR_EraseFromParent, /*InsnID*/0,
        // GIR_Coverage, 4795,
        GIR_Done,
      // Label 6327: @463739
      GIM_Try, /*On fail goto*//*Label 6328*/ GIMT_Encode4(463821), // Rule ID 4803 //
        GIM_CheckRegBankForClass, /*MI*/0, /*Op*/0, /*RC*/GIMT_Encode2(AMDGPU::AV_32RegClassID),
        GIM_CheckConstantInt8, /*MI*/0, /*Op*/3, 0,
        // MIs[0] offset
        GIM_CheckIsImm, /*MI*/0, /*Op*/6,
        // MIs[0] auxiliary
        GIM_CheckIsImm, /*MI*/0, /*Op*/7,
        // MIs[0] Operand 8
        GIM_CheckLiteralInt, /*MI*/0, /*Op*/8, GIMT_Encode8(0),
        GIM_CheckComplexPattern, /*MI*/0, /*Op*/5, /*Renderer*/GIMT_Encode2(0), GIMT_Encode2(GICP_gi_buf_soffset),
        // (SIbuffer_atomic_umin:{ *:[i32] } i32:{ *:[i32] }:$vdata_in, v4i32:{ *:[v4i32] }:$rsrc, 0:{ *:[i32] }, i32:{ *:[i32] }:$voffset, (BUFSOffset:{ *:[i32] } i32:{ *:[i32] }:$soffset), (timm:{ *:[i32] }):$offset, (timm:{ *:[i32] }):$auxiliary, 0:{ *:[i1] })  =>  (BUFFER_ATOMIC_UMIN_VBUFFER_OFFEN_RTN:{ *:[i32] } anonymous_15037:{ *:[i32] }:$vdata_in, VGPR_32:{ *:[i32] }:$voffset, SReg_128:{ *:[v4i32] }:$rsrc, SCSrc_b32:{ *:[i32] }:$soffset, (timm:{ *:[i32] }):$offset, (extract_cpol_set_glc:{ *:[i32] } ?:{ *:[i32] }:$auxiliary))
        GIR_BuildMI, /*InsnID*/0, /*Opcode*/GIMT_Encode2(AMDGPU::BUFFER_ATOMIC_UMIN_VBUFFER_OFFEN_RTN),
        GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/0, // DstI[vdata]
        GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/1, // vdata_in
        GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/4, // voffset
        GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/2, // rsrc
        GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/0, // soffset
        GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/6, // offset
        GIR_CustomOperandRenderer, /*InsnID*/0, /*OldInsnID*/0, /*OpIdx*/7, /*OperandRenderer*/GIMT_Encode2(GICR_renderExtractCpolSetGLC), // auxiliary
        GIR_MergeMemOperands, /*InsnID*/0, /*NumInsns*/1, /*MergeInsnID's*/0,
        GIR_ConstrainSelectedInstOperands, /*InsnID*/0,
        GIR_EraseFromParent, /*InsnID*/0,
        // GIR_Coverage, 4803,
        GIR_Done,
      // Label 6328: @463821
      GIM_Try, /*On fail goto*//*Label 6329*/ GIMT_Encode4(463891), // Rule ID 4798 //
        GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasUnrestrictedSOffset),
        GIM_CheckHasNoUse, /*MI*/0,
        GIM_CheckConstantInt8, /*MI*/0, /*Op*/4, 0,
        // MIs[0] offset
        GIM_CheckIsImm, /*MI*/0, /*Op*/6,
        // MIs[0] auxiliary
        GIM_CheckIsImm, /*MI*/0, /*Op*/7,
        // MIs[0] Operand 8
        GIM_CheckIsImm, /*MI*/0, /*Op*/8,
        GIM_CheckComplexPattern, /*MI*/0, /*Op*/5, /*Renderer*/GIMT_Encode2(0), GIMT_Encode2(GICP_gi_buf_soffset),
        // (SIbuffer_atomic_umin:{ *:[i32] } i32:{ *:[i32] }:$vdata_in, v4i32:{ *:[v4i32] }:$rsrc, i32:{ *:[i32] }:$vindex, 0:{ *:[i32] }, (BUFSOffset:{ *:[i32] } i32:{ *:[i32] }:$soffset), (timm:{ *:[i32] }):$offset, (timm:{ *:[i32] }):$auxiliary, (timm:{ *:[i1] }))<<P:Predicate_SIbuffer_atomic_umin_noret>>  =>  (BUFFER_ATOMIC_UMIN_IDXEN anonymous_15037:{ *:[i32] }:$vdata_in, VGPR_32:{ *:[i32] }:$vindex, SReg_128:{ *:[v4i32] }:$rsrc, SCSrc_b32:{ *:[i32] }:$soffset, (timm:{ *:[i32] }):$offset, (extract_cpol:{ *:[i32] } ?:{ *:[i32] }:$auxiliary))
        GIR_BuildMI, /*InsnID*/0, /*Opcode*/GIMT_Encode2(AMDGPU::BUFFER_ATOMIC_UMIN_IDXEN),
        GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/1, // vdata_in
        GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/3, // vindex
        GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/2, // rsrc
        GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/0, // soffset
        GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/6, // offset
        GIR_CustomOperandRenderer, /*InsnID*/0, /*OldInsnID*/0, /*OpIdx*/7, /*OperandRenderer*/GIMT_Encode2(GICR_renderExtractCPol), // auxiliary
        GIR_MergeMemOperands, /*InsnID*/0, /*NumInsns*/1, /*MergeInsnID's*/0,
        GIR_ConstrainSelectedInstOperands, /*InsnID*/0,
        GIR_EraseFromParent, /*InsnID*/0,
        // GIR_Coverage, 4798,
        GIR_Done,
      // Label 6329: @463891
      GIM_Try, /*On fail goto*//*Label 6330*/ GIMT_Encode4(463958), // Rule ID 4806 //
        GIM_CheckHasNoUse, /*MI*/0,
        GIM_CheckConstantInt8, /*MI*/0, /*Op*/4, 0,
        // MIs[0] offset
        GIM_CheckIsImm, /*MI*/0, /*Op*/6,
        // MIs[0] auxiliary
        GIM_CheckIsImm, /*MI*/0, /*Op*/7,
        // MIs[0] Operand 8
        GIM_CheckIsImm, /*MI*/0, /*Op*/8,
        GIM_CheckComplexPattern, /*MI*/0, /*Op*/5, /*Renderer*/GIMT_Encode2(0), GIMT_Encode2(GICP_gi_buf_soffset),
        // (SIbuffer_atomic_umin:{ *:[i32] } i32:{ *:[i32] }:$vdata_in, v4i32:{ *:[v4i32] }:$rsrc, i32:{ *:[i32] }:$vindex, 0:{ *:[i32] }, (BUFSOffset:{ *:[i32] } i32:{ *:[i32] }:$soffset), (timm:{ *:[i32] }):$offset, (timm:{ *:[i32] }):$auxiliary, (timm:{ *:[i1] }))<<P:Predicate_SIbuffer_atomic_umin_noret>>  =>  (BUFFER_ATOMIC_UMIN_VBUFFER_IDXEN anonymous_15037:{ *:[i32] }:$vdata_in, VGPR_32:{ *:[i32] }:$vindex, SReg_128:{ *:[v4i32] }:$rsrc, SCSrc_b32:{ *:[i32] }:$soffset, (timm:{ *:[i32] }):$offset, (extract_cpol:{ *:[i32] } ?:{ *:[i32] }:$auxiliary))
        GIR_BuildMI, /*InsnID*/0, /*Opcode*/GIMT_Encode2(AMDGPU::BUFFER_ATOMIC_UMIN_VBUFFER_IDXEN),
        GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/1, // vdata_in
        GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/3, // vindex
        GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/2, // rsrc
        GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/0, // soffset
        GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/6, // offset
        GIR_CustomOperandRenderer, /*InsnID*/0, /*OldInsnID*/0, /*OpIdx*/7, /*OperandRenderer*/GIMT_Encode2(GICR_renderExtractCPol), // auxiliary
        GIR_MergeMemOperands, /*InsnID*/0, /*NumInsns*/1, /*MergeInsnID's*/0,
        GIR_ConstrainSelectedInstOperands, /*InsnID*/0,
        GIR_EraseFromParent, /*InsnID*/0,
        // GIR_Coverage, 4806,
        GIR_Done,
      // Label 6330: @463958
      GIM_Try, /*On fail goto*//*Label 6331*/ GIMT_Encode4(464035), // Rule ID 4794 //
        GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasUnrestrictedSOffset),
        GIM_CheckRegBankForClass, /*MI*/0, /*Op*/0, /*RC*/GIMT_Encode2(AMDGPU::AV_32RegClassID),
        GIM_CheckConstantInt8, /*MI*/0, /*Op*/4, 0,
        // MIs[0] offset
        GIM_CheckIsImm, /*MI*/0, /*Op*/6,
        // MIs[0] auxiliary
        GIM_CheckIsImm, /*MI*/0, /*Op*/7,
        // MIs[0] Operand 8
        GIM_CheckIsImm, /*MI*/0, /*Op*/8,
        GIM_CheckComplexPattern, /*MI*/0, /*Op*/5, /*Renderer*/GIMT_Encode2(0), GIMT_Encode2(GICP_gi_buf_soffset),
        // (SIbuffer_atomic_umin:{ *:[i32] } i32:{ *:[i32] }:$vdata_in, v4i32:{ *:[v4i32] }:$rsrc, i32:{ *:[i32] }:$vindex, 0:{ *:[i32] }, (BUFSOffset:{ *:[i32] } i32:{ *:[i32] }:$soffset), (timm:{ *:[i32] }):$offset, (timm:{ *:[i32] }):$auxiliary, (timm:{ *:[i1] }))  =>  (BUFFER_ATOMIC_UMIN_IDXEN_RTN:{ *:[i32] } anonymous_15037:{ *:[i32] }:$vdata_in, VGPR_32:{ *:[i32] }:$vindex, SReg_128:{ *:[v4i32] }:$rsrc, SCSrc_b32:{ *:[i32] }:$soffset, (timm:{ *:[i32] }):$offset, (extract_cpol_set_glc:{ *:[i32] } ?:{ *:[i32] }:$auxiliary))
        GIR_BuildMI, /*InsnID*/0, /*Opcode*/GIMT_Encode2(AMDGPU::BUFFER_ATOMIC_UMIN_IDXEN_RTN),
        GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/0, // DstI[vdata]
        GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/1, // vdata_in
        GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/3, // vindex
        GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/2, // rsrc
        GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/0, // soffset
        GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/6, // offset
        GIR_CustomOperandRenderer, /*InsnID*/0, /*OldInsnID*/0, /*OpIdx*/7, /*OperandRenderer*/GIMT_Encode2(GICR_renderExtractCpolSetGLC), // auxiliary
        GIR_MergeMemOperands, /*InsnID*/0, /*NumInsns*/1, /*MergeInsnID's*/0,
        GIR_ConstrainSelectedInstOperands, /*InsnID*/0,
        GIR_EraseFromParent, /*InsnID*/0,
        // GIR_Coverage, 4794,
        GIR_Done,
      // Label 6331: @464035
      GIM_Try, /*On fail goto*//*Label 6332*/ GIMT_Encode4(464109), // Rule ID 4802 //
        GIM_CheckRegBankForClass, /*MI*/0, /*Op*/0, /*RC*/GIMT_Encode2(AMDGPU::AV_32RegClassID),
        GIM_CheckConstantInt8, /*MI*/0, /*Op*/4, 0,
        // MIs[0] offset
        GIM_CheckIsImm, /*MI*/0, /*Op*/6,
        // MIs[0] auxiliary
        GIM_CheckIsImm, /*MI*/0, /*Op*/7,
        // MIs[0] Operand 8
        GIM_CheckIsImm, /*MI*/0, /*Op*/8,
        GIM_CheckComplexPattern, /*MI*/0, /*Op*/5, /*Renderer*/GIMT_Encode2(0), GIMT_Encode2(GICP_gi_buf_soffset),
        // (SIbuffer_atomic_umin:{ *:[i32] } i32:{ *:[i32] }:$vdata_in, v4i32:{ *:[v4i32] }:$rsrc, i32:{ *:[i32] }:$vindex, 0:{ *:[i32] }, (BUFSOffset:{ *:[i32] } i32:{ *:[i32] }:$soffset), (timm:{ *:[i32] }):$offset, (timm:{ *:[i32] }):$auxiliary, (timm:{ *:[i1] }))  =>  (BUFFER_ATOMIC_UMIN_VBUFFER_IDXEN_RTN:{ *:[i32] } anonymous_15037:{ *:[i32] }:$vdata_in, VGPR_32:{ *:[i32] }:$vindex, SReg_128:{ *:[v4i32] }:$rsrc, SCSrc_b32:{ *:[i32] }:$soffset, (timm:{ *:[i32] }):$offset, (extract_cpol_set_glc:{ *:[i32] } ?:{ *:[i32] }:$auxiliary))
        GIR_BuildMI, /*InsnID*/0, /*Opcode*/GIMT_Encode2(AMDGPU::BUFFER_ATOMIC_UMIN_VBUFFER_IDXEN_RTN),
        GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/0, // DstI[vdata]
        GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/1, // vdata_in
        GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/3, // vindex
        GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/2, // rsrc
        GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/0, // soffset
        GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/6, // offset
        GIR_CustomOperandRenderer, /*InsnID*/0, /*OldInsnID*/0, /*OpIdx*/7, /*OperandRenderer*/GIMT_Encode2(GICR_renderExtractCpolSetGLC), // auxiliary
        GIR_MergeMemOperands, /*InsnID*/0, /*NumInsns*/1, /*MergeInsnID's*/0,
        GIR_ConstrainSelectedInstOperands, /*InsnID*/0,
        GIR_EraseFromParent, /*InsnID*/0,
        // GIR_Coverage, 4802,
        GIR_Done,
      // Label 6332: @464109
      GIM_Try, /*On fail goto*//*Label 6333*/ GIMT_Encode4(464215), // Rule ID 4800 //
        GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasUnrestrictedSOffset),
        GIM_CheckHasNoUse, /*MI*/0,
        // MIs[0] offset
        GIM_CheckIsImm, /*MI*/0, /*Op*/6,
        // MIs[0] auxiliary
        GIM_CheckIsImm, /*MI*/0, /*Op*/7,
        // MIs[0] Operand 8
        GIM_CheckIsImm, /*MI*/0, /*Op*/8,
        GIM_CheckComplexPattern, /*MI*/0, /*Op*/5, /*Renderer*/GIMT_Encode2(0), GIMT_Encode2(GICP_gi_buf_soffset),
        // (SIbuffer_atomic_umin:{ *:[i32] } i32:{ *:[i32] }:$vdata_in, v4i32:{ *:[v4i32] }:$rsrc, i32:{ *:[i32] }:$vindex, i32:{ *:[i32] }:$voffset, (BUFSOffset:{ *:[i32] } i32:{ *:[i32] }:$soffset), (timm:{ *:[i32] }):$offset, (timm:{ *:[i32] }):$auxiliary, (timm:{ *:[i1] }))<<P:Predicate_SIbuffer_atomic_umin_noret>>  =>  (BUFFER_ATOMIC_UMIN_BOTHEN anonymous_15037:{ *:[i32] }:$vdata_in, (REG_SEQUENCE:{ *:[i64] } VReg_64:{ *:[i32] }, VGPR_32:{ *:[i32] }:$vindex, sub0:{ *:[i32] }, VGPR_32:{ *:[i32] }:$voffset, sub1:{ *:[i32] }), SReg_128:{ *:[v4i32] }:$rsrc, SCSrc_b32:{ *:[i32] }:$soffset, (timm:{ *:[i32] }):$offset, (extract_cpol:{ *:[i32] } ?:{ *:[i32] }:$auxiliary))
        GIR_MakeTempReg, /*TempRegID*/0, /*TypeID*/GILLT_s64,
        GIR_BuildMI, /*InsnID*/1, /*Opcode*/GIMT_Encode2(TargetOpcode::REG_SEQUENCE),
        GIR_AddTempRegister, /*InsnID*/1, /*TempRegID*/0, /*TempRegFlags*/GIMT_Encode2(RegState::Define),
        GIR_Copy, /*NewInsnID*/1, /*OldInsnID*/0, /*OpIdx*/3, // vindex
        GIR_AddImm8, /*InsnID*/1, /*SubRegIndex*/3,
        GIR_Copy, /*NewInsnID*/1, /*OldInsnID*/0, /*OpIdx*/4, // voffset
        GIR_AddImm8, /*InsnID*/1, /*SubRegIndex*/11,
        GIR_ConstrainOperandRC, /*InsnID*/1, /*Op*/0, GIMT_Encode2(AMDGPU::VReg_64RegClassID),
        GIR_ConstrainOperandRC, /*InsnID*/1, /*Op*/1, GIMT_Encode2(AMDGPU::VGPR_32RegClassID),
        GIR_ConstrainOperandRC, /*InsnID*/1, /*Op*/3, GIMT_Encode2(AMDGPU::VGPR_32RegClassID),
        GIR_BuildMI, /*InsnID*/0, /*Opcode*/GIMT_Encode2(AMDGPU::BUFFER_ATOMIC_UMIN_BOTHEN),
        GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/1, // vdata_in
        GIR_AddSimpleTempRegister, /*InsnID*/0, /*TempRegID*/0,
        GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/2, // rsrc
        GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/0, // soffset
        GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/6, // offset
        GIR_CustomOperandRenderer, /*InsnID*/0, /*OldInsnID*/0, /*OpIdx*/7, /*OperandRenderer*/GIMT_Encode2(GICR_renderExtractCPol), // auxiliary
        GIR_MergeMemOperands, /*InsnID*/0, /*NumInsns*/1, /*MergeInsnID's*/0,
        GIR_ConstrainSelectedInstOperands, /*InsnID*/0,
        GIR_EraseFromParent, /*InsnID*/0,
        // GIR_Coverage, 4800,
        GIR_Done,
      // Label 6333: @464215
      GIM_Try, /*On fail goto*//*Label 6334*/ GIMT_Encode4(464318), // Rule ID 4808 //
        GIM_CheckHasNoUse, /*MI*/0,
        // MIs[0] offset
        GIM_CheckIsImm, /*MI*/0, /*Op*/6,
        // MIs[0] auxiliary
        GIM_CheckIsImm, /*MI*/0, /*Op*/7,
        // MIs[0] Operand 8
        GIM_CheckIsImm, /*MI*/0, /*Op*/8,
        GIM_CheckComplexPattern, /*MI*/0, /*Op*/5, /*Renderer*/GIMT_Encode2(0), GIMT_Encode2(GICP_gi_buf_soffset),
        // (SIbuffer_atomic_umin:{ *:[i32] } i32:{ *:[i32] }:$vdata_in, v4i32:{ *:[v4i32] }:$rsrc, i32:{ *:[i32] }:$vindex, i32:{ *:[i32] }:$voffset, (BUFSOffset:{ *:[i32] } i32:{ *:[i32] }:$soffset), (timm:{ *:[i32] }):$offset, (timm:{ *:[i32] }):$auxiliary, (timm:{ *:[i1] }))<<P:Predicate_SIbuffer_atomic_umin_noret>>  =>  (BUFFER_ATOMIC_UMIN_VBUFFER_BOTHEN anonymous_15037:{ *:[i32] }:$vdata_in, (REG_SEQUENCE:{ *:[i64] } VReg_64:{ *:[i32] }, VGPR_32:{ *:[i32] }:$vindex, sub0:{ *:[i32] }, VGPR_32:{ *:[i32] }:$voffset, sub1:{ *:[i32] }), SReg_128:{ *:[v4i32] }:$rsrc, SCSrc_b32:{ *:[i32] }:$soffset, (timm:{ *:[i32] }):$offset, (extract_cpol:{ *:[i32] } ?:{ *:[i32] }:$auxiliary))
        GIR_MakeTempReg, /*TempRegID*/0, /*TypeID*/GILLT_s64,
        GIR_BuildMI, /*InsnID*/1, /*Opcode*/GIMT_Encode2(TargetOpcode::REG_SEQUENCE),
        GIR_AddTempRegister, /*InsnID*/1, /*TempRegID*/0, /*TempRegFlags*/GIMT_Encode2(RegState::Define),
        GIR_Copy, /*NewInsnID*/1, /*OldInsnID*/0, /*OpIdx*/3, // vindex
        GIR_AddImm8, /*InsnID*/1, /*SubRegIndex*/3,
        GIR_Copy, /*NewInsnID*/1, /*OldInsnID*/0, /*OpIdx*/4, // voffset
        GIR_AddImm8, /*InsnID*/1, /*SubRegIndex*/11,
        GIR_ConstrainOperandRC, /*InsnID*/1, /*Op*/0, GIMT_Encode2(AMDGPU::VReg_64RegClassID),
        GIR_ConstrainOperandRC, /*InsnID*/1, /*Op*/1, GIMT_Encode2(AMDGPU::VGPR_32RegClassID),
        GIR_ConstrainOperandRC, /*InsnID*/1, /*Op*/3, GIMT_Encode2(AMDGPU::VGPR_32RegClassID),
        GIR_BuildMI, /*InsnID*/0, /*Opcode*/GIMT_Encode2(AMDGPU::BUFFER_ATOMIC_UMIN_VBUFFER_BOTHEN),
        GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/1, // vdata_in
        GIR_AddSimpleTempRegister, /*InsnID*/0, /*TempRegID*/0,
        GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/2, // rsrc
        GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/0, // soffset
        GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/6, // offset
        GIR_CustomOperandRenderer, /*InsnID*/0, /*OldInsnID*/0, /*OpIdx*/7, /*OperandRenderer*/GIMT_Encode2(GICR_renderExtractCPol), // auxiliary
        GIR_MergeMemOperands, /*InsnID*/0, /*NumInsns*/1, /*MergeInsnID's*/0,
        GIR_ConstrainSelectedInstOperands, /*InsnID*/0,
        GIR_EraseFromParent, /*InsnID*/0,
        // GIR_Coverage, 4808,
        GIR_Done,
      // Label 6334: @464318
      GIM_Try, /*On fail goto*//*Label 6335*/ GIMT_Encode4(464431), // Rule ID 4796 //
        GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasUnrestrictedSOffset),
        GIM_CheckRegBankForClass, /*MI*/0, /*Op*/0, /*RC*/GIMT_Encode2(AMDGPU::AV_32RegClassID),
        // MIs[0] offset
        GIM_CheckIsImm, /*MI*/0, /*Op*/6,
        // MIs[0] auxiliary
        GIM_CheckIsImm, /*MI*/0, /*Op*/7,
        // MIs[0] Operand 8
        GIM_CheckIsImm, /*MI*/0, /*Op*/8,
        GIM_CheckComplexPattern, /*MI*/0, /*Op*/5, /*Renderer*/GIMT_Encode2(0), GIMT_Encode2(GICP_gi_buf_soffset),
        // (SIbuffer_atomic_umin:{ *:[i32] } i32:{ *:[i32] }:$vdata_in, v4i32:{ *:[v4i32] }:$rsrc, i32:{ *:[i32] }:$vindex, i32:{ *:[i32] }:$voffset, (BUFSOffset:{ *:[i32] } i32:{ *:[i32] }:$soffset), (timm:{ *:[i32] }):$offset, (timm:{ *:[i32] }):$auxiliary, (timm:{ *:[i1] }))  =>  (BUFFER_ATOMIC_UMIN_BOTHEN_RTN:{ *:[i32] } anonymous_15037:{ *:[i32] }:$vdata_in, (REG_SEQUENCE:{ *:[i64] } VReg_64:{ *:[i32] }, VGPR_32:{ *:[i32] }:$vindex, sub0:{ *:[i32] }, VGPR_32:{ *:[i32] }:$voffset, sub1:{ *:[i32] }), SReg_128:{ *:[v4i32] }:$rsrc, SCSrc_b32:{ *:[i32] }:$soffset, (timm:{ *:[i32] }):$offset, (extract_cpol_set_glc:{ *:[i32] } ?:{ *:[i32] }:$auxiliary))
        GIR_MakeTempReg, /*TempRegID*/0, /*TypeID*/GILLT_s64,
        GIR_BuildMI, /*InsnID*/1, /*Opcode*/GIMT_Encode2(TargetOpcode::REG_SEQUENCE),
        GIR_AddTempRegister, /*InsnID*/1, /*TempRegID*/0, /*TempRegFlags*/GIMT_Encode2(RegState::Define),
        GIR_Copy, /*NewInsnID*/1, /*OldInsnID*/0, /*OpIdx*/3, // vindex
        GIR_AddImm8, /*InsnID*/1, /*SubRegIndex*/3,
        GIR_Copy, /*NewInsnID*/1, /*OldInsnID*/0, /*OpIdx*/4, // voffset
        GIR_AddImm8, /*InsnID*/1, /*SubRegIndex*/11,
        GIR_ConstrainOperandRC, /*InsnID*/1, /*Op*/0, GIMT_Encode2(AMDGPU::VReg_64RegClassID),
        GIR_ConstrainOperandRC, /*InsnID*/1, /*Op*/1, GIMT_Encode2(AMDGPU::VGPR_32RegClassID),
        GIR_ConstrainOperandRC, /*InsnID*/1, /*Op*/3, GIMT_Encode2(AMDGPU::VGPR_32RegClassID),
        GIR_BuildMI, /*InsnID*/0, /*Opcode*/GIMT_Encode2(AMDGPU::BUFFER_ATOMIC_UMIN_BOTHEN_RTN),
        GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/0, // DstI[vdata]
        GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/1, // vdata_in
        GIR_AddSimpleTempRegister, /*InsnID*/0, /*TempRegID*/0,
        GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/2, // rsrc
        GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/0, // soffset
        GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/6, // offset
        GIR_CustomOperandRenderer, /*InsnID*/0, /*OldInsnID*/0, /*OpIdx*/7, /*OperandRenderer*/GIMT_Encode2(GICR_renderExtractCpolSetGLC), // auxiliary
        GIR_MergeMemOperands, /*InsnID*/0, /*NumInsns*/1, /*MergeInsnID's*/0,
        GIR_ConstrainSelectedInstOperands, /*InsnID*/0,
        GIR_EraseFromParent, /*InsnID*/0,
        // GIR_Coverage, 4796,
        GIR_Done,
      // Label 6335: @464431
      GIM_Try, /*On fail goto*//*Label 6336*/ GIMT_Encode4(464541), // Rule ID 4804 //
        GIM_CheckRegBankForClass, /*MI*/0, /*Op*/0, /*RC*/GIMT_Encode2(AMDGPU::AV_32RegClassID),
        // MIs[0] offset
        GIM_CheckIsImm, /*MI*/0, /*Op*/6,
        // MIs[0] auxiliary
        GIM_CheckIsImm, /*MI*/0, /*Op*/7,
        // MIs[0] Operand 8
        GIM_CheckIsImm, /*MI*/0, /*Op*/8,
        GIM_CheckComplexPattern, /*MI*/0, /*Op*/5, /*Renderer*/GIMT_Encode2(0), GIMT_Encode2(GICP_gi_buf_soffset),
        // (SIbuffer_atomic_umin:{ *:[i32] } i32:{ *:[i32] }:$vdata_in, v4i32:{ *:[v4i32] }:$rsrc, i32:{ *:[i32] }:$vindex, i32:{ *:[i32] }:$voffset, (BUFSOffset:{ *:[i32] } i32:{ *:[i32] }:$soffset), (timm:{ *:[i32] }):$offset, (timm:{ *:[i32] }):$auxiliary, (timm:{ *:[i1] }))  =>  (BUFFER_ATOMIC_UMIN_VBUFFER_BOTHEN_RTN:{ *:[i32] } anonymous_15037:{ *:[i32] }:$vdata_in, (REG_SEQUENCE:{ *:[i64] } VReg_64:{ *:[i32] }, VGPR_32:{ *:[i32] }:$vindex, sub0:{ *:[i32] }, VGPR_32:{ *:[i32] }:$voffset, sub1:{ *:[i32] }), SReg_128:{ *:[v4i32] }:$rsrc, SCSrc_b32:{ *:[i32] }:$soffset, (timm:{ *:[i32] }):$offset, (extract_cpol_set_glc:{ *:[i32] } ?:{ *:[i32] }:$auxiliary))
        GIR_MakeTempReg, /*TempRegID*/0, /*TypeID*/GILLT_s64,
        GIR_BuildMI, /*InsnID*/1, /*Opcode*/GIMT_Encode2(TargetOpcode::REG_SEQUENCE),
        GIR_AddTempRegister, /*InsnID*/1, /*TempRegID*/0, /*TempRegFlags*/GIMT_Encode2(RegState::Define),
        GIR_Copy, /*NewInsnID*/1, /*OldInsnID*/0, /*OpIdx*/3, // vindex
        GIR_AddImm8, /*InsnID*/1, /*SubRegIndex*/3,
        GIR_Copy, /*NewInsnID*/1, /*OldInsnID*/0, /*OpIdx*/4, // voffset
        GIR_AddImm8, /*InsnID*/1, /*SubRegIndex*/11,
        GIR_ConstrainOperandRC, /*InsnID*/1, /*Op*/0, GIMT_Encode2(AMDGPU::VReg_64RegClassID),
        GIR_ConstrainOperandRC, /*InsnID*/1, /*Op*/1, GIMT_Encode2(AMDGPU::VGPR_32RegClassID),
        GIR_ConstrainOperandRC, /*InsnID*/1, /*Op*/3, GIMT_Encode2(AMDGPU::VGPR_32RegClassID),
        GIR_BuildMI, /*InsnID*/0, /*Opcode*/GIMT_Encode2(AMDGPU::BUFFER_ATOMIC_UMIN_VBUFFER_BOTHEN_RTN),
        GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/0, // DstI[vdata]
        GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/1, // vdata_in
        GIR_AddSimpleTempRegister, /*InsnID*/0, /*TempRegID*/0,
        GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/2, // rsrc
        GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/0, // soffset
        GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/6, // offset
        GIR_CustomOperandRenderer, /*InsnID*/0, /*OldInsnID*/0, /*OpIdx*/7, /*OperandRenderer*/GIMT_Encode2(GICR_renderExtractCpolSetGLC), // auxiliary
        GIR_MergeMemOperands, /*InsnID*/0, /*NumInsns*/1, /*MergeInsnID's*/0,
        GIR_ConstrainSelectedInstOperands, /*InsnID*/0,
        GIR_EraseFromParent, /*InsnID*/0,
        // GIR_Coverage, 4804,
        GIR_Done,
      // Label 6336: @464541
      GIM_Reject,
    // Label 6320: @464542
    GIM_Reject,
    // Label 6318: @464543
    GIM_Try, /*On fail goto*//*Label 6337*/ GIMT_Encode4(465929),
      GIM_CheckType, /*MI*/0, /*Op*/1, /*Type*/GILLT_s64,
      GIM_CheckType, /*MI*/0, /*Op*/2, /*Type*/GILLT_v4s32,
      GIM_CheckType, /*MI*/0, /*Op*/3, /*Type*/GILLT_s32,
      GIM_CheckType, /*MI*/0, /*Op*/4, /*Type*/GILLT_s32,
      GIM_CheckType, /*MI*/0, /*Op*/5, /*Type*/GILLT_s32,
      GIM_Try, /*On fail goto*//*Label 6338*/ GIMT_Encode4(464646), // Rule ID 4997 //
        GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasUnrestrictedSOffset),
        GIM_CheckHasNoUse, /*MI*/0,
        GIM_CheckConstantInt8, /*MI*/0, /*Op*/3, 0,
        GIM_CheckConstantInt8, /*MI*/0, /*Op*/4, 0,
        // MIs[0] offset
        GIM_CheckIsImm, /*MI*/0, /*Op*/6,
        // MIs[0] auxiliary
        GIM_CheckIsImm, /*MI*/0, /*Op*/7,
        // MIs[0] Operand 8
        GIM_CheckLiteralInt, /*MI*/0, /*Op*/8, GIMT_Encode8(0),
        GIM_CheckComplexPattern, /*MI*/0, /*Op*/5, /*Renderer*/GIMT_Encode2(0), GIMT_Encode2(GICP_gi_buf_soffset),
        // (SIbuffer_atomic_umin:{ *:[i64] } i64:{ *:[i64] }:$vdata_in, v4i32:{ *:[v4i32] }:$rsrc, 0:{ *:[i32] }, 0:{ *:[i32] }, (BUFSOffset:{ *:[i32] } i32:{ *:[i32] }:$soffset), (timm:{ *:[i32] }):$offset, (timm:{ *:[i32] }):$auxiliary, 0:{ *:[i1] })<<P:Predicate_SIbuffer_atomic_umin_noret>>  =>  (BUFFER_ATOMIC_UMIN_X2_OFFSET anonymous_15036:{ *:[i64] }:$vdata_in, SReg_128:{ *:[v4i32] }:$rsrc, SCSrc_b32:{ *:[i32] }:$soffset, (timm:{ *:[i32] }):$offset, (extract_cpol:{ *:[i32] } ?:{ *:[i32] }:$auxiliary))
        GIR_BuildMI, /*InsnID*/0, /*Opcode*/GIMT_Encode2(AMDGPU::BUFFER_ATOMIC_UMIN_X2_OFFSET),
        GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/1, // vdata_in
        GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/2, // rsrc
        GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/0, // soffset
        GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/6, // offset
        GIR_CustomOperandRenderer, /*InsnID*/0, /*OldInsnID*/0, /*OpIdx*/7, /*OperandRenderer*/GIMT_Encode2(GICR_renderExtractCPol), // auxiliary
        GIR_MergeMemOperands, /*InsnID*/0, /*NumInsns*/1, /*MergeInsnID's*/0,
        GIR_ConstrainSelectedInstOperands, /*InsnID*/0,
        GIR_EraseFromParent, /*InsnID*/0,
        // GIR_Coverage, 4997,
        GIR_Done,
      // Label 6338: @464646
      GIM_Try, /*On fail goto*//*Label 6339*/ GIMT_Encode4(464721), // Rule ID 5005 //
        GIM_CheckHasNoUse, /*MI*/0,
        GIM_CheckConstantInt8, /*MI*/0, /*Op*/3, 0,
        GIM_CheckConstantInt8, /*MI*/0, /*Op*/4, 0,
        // MIs[0] offset
        GIM_CheckIsImm, /*MI*/0, /*Op*/6,
        // MIs[0] auxiliary
        GIM_CheckIsImm, /*MI*/0, /*Op*/7,
        // MIs[0] Operand 8
        GIM_CheckLiteralInt, /*MI*/0, /*Op*/8, GIMT_Encode8(0),
        GIM_CheckComplexPattern, /*MI*/0, /*Op*/5, /*Renderer*/GIMT_Encode2(0), GIMT_Encode2(GICP_gi_buf_soffset),
        // (SIbuffer_atomic_umin:{ *:[i64] } i64:{ *:[i64] }:$vdata_in, v4i32:{ *:[v4i32] }:$rsrc, 0:{ *:[i32] }, 0:{ *:[i32] }, (BUFSOffset:{ *:[i32] } i32:{ *:[i32] }:$soffset), (timm:{ *:[i32] }):$offset, (timm:{ *:[i32] }):$auxiliary, 0:{ *:[i1] })<<P:Predicate_SIbuffer_atomic_umin_noret>>  =>  (BUFFER_ATOMIC_UMIN_X2_VBUFFER_OFFSET anonymous_15036:{ *:[i64] }:$vdata_in, SReg_128:{ *:[v4i32] }:$rsrc, SCSrc_b32:{ *:[i32] }:$soffset, (timm:{ *:[i32] }):$offset, (extract_cpol:{ *:[i32] } ?:{ *:[i32] }:$auxiliary))
        GIR_BuildMI, /*InsnID*/0, /*Opcode*/GIMT_Encode2(AMDGPU::BUFFER_ATOMIC_UMIN_X2_VBUFFER_OFFSET),
        GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/1, // vdata_in
        GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/2, // rsrc
        GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/0, // soffset
        GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/6, // offset
        GIR_CustomOperandRenderer, /*InsnID*/0, /*OldInsnID*/0, /*OpIdx*/7, /*OperandRenderer*/GIMT_Encode2(GICR_renderExtractCPol), // auxiliary
        GIR_MergeMemOperands, /*InsnID*/0, /*NumInsns*/1, /*MergeInsnID's*/0,
        GIR_ConstrainSelectedInstOperands, /*InsnID*/0,
        GIR_EraseFromParent, /*InsnID*/0,
        // GIR_Coverage, 5005,
        GIR_Done,
      // Label 6339: @464721
      GIM_Try, /*On fail goto*//*Label 6340*/ GIMT_Encode4(464806), // Rule ID 4993 //
        GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasUnrestrictedSOffset),
        GIM_CheckRegBankForClass, /*MI*/0, /*Op*/0, /*RC*/GIMT_Encode2(AMDGPU::AV_64RegClassID),
        GIM_CheckConstantInt8, /*MI*/0, /*Op*/3, 0,
        GIM_CheckConstantInt8, /*MI*/0, /*Op*/4, 0,
        // MIs[0] offset
        GIM_CheckIsImm, /*MI*/0, /*Op*/6,
        // MIs[0] auxiliary
        GIM_CheckIsImm, /*MI*/0, /*Op*/7,
        // MIs[0] Operand 8
        GIM_CheckLiteralInt, /*MI*/0, /*Op*/8, GIMT_Encode8(0),
        GIM_CheckComplexPattern, /*MI*/0, /*Op*/5, /*Renderer*/GIMT_Encode2(0), GIMT_Encode2(GICP_gi_buf_soffset),
        // (SIbuffer_atomic_umin:{ *:[i64] } i64:{ *:[i64] }:$vdata_in, v4i32:{ *:[v4i32] }:$rsrc, 0:{ *:[i32] }, 0:{ *:[i32] }, (BUFSOffset:{ *:[i32] } i32:{ *:[i32] }:$soffset), (timm:{ *:[i32] }):$offset, (timm:{ *:[i32] }):$auxiliary, 0:{ *:[i1] })  =>  (BUFFER_ATOMIC_UMIN_X2_OFFSET_RTN:{ *:[i64] } anonymous_15036:{ *:[i64] }:$vdata_in, SReg_128:{ *:[v4i32] }:$rsrc, SCSrc_b32:{ *:[i32] }:$soffset, (timm:{ *:[i32] }):$offset, (extract_cpol_set_glc:{ *:[i32] } ?:{ *:[i32] }:$auxiliary))
        GIR_BuildMI, /*InsnID*/0, /*Opcode*/GIMT_Encode2(AMDGPU::BUFFER_ATOMIC_UMIN_X2_OFFSET_RTN),
        GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/0, // DstI[vdata]
        GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/1, // vdata_in
        GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/2, // rsrc
        GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/0, // soffset
        GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/6, // offset
        GIR_CustomOperandRenderer, /*InsnID*/0, /*OldInsnID*/0, /*OpIdx*/7, /*OperandRenderer*/GIMT_Encode2(GICR_renderExtractCpolSetGLC), // auxiliary
        GIR_MergeMemOperands, /*InsnID*/0, /*NumInsns*/1, /*MergeInsnID's*/0,
        GIR_ConstrainSelectedInstOperands, /*InsnID*/0,
        GIR_EraseFromParent, /*InsnID*/0,
        // GIR_Coverage, 4993,
        GIR_Done,
      // Label 6340: @464806
      GIM_Try, /*On fail goto*//*Label 6341*/ GIMT_Encode4(464888), // Rule ID 5001 //
        GIM_CheckRegBankForClass, /*MI*/0, /*Op*/0, /*RC*/GIMT_Encode2(AMDGPU::AV_64RegClassID),
        GIM_CheckConstantInt8, /*MI*/0, /*Op*/3, 0,
        GIM_CheckConstantInt8, /*MI*/0, /*Op*/4, 0,
        // MIs[0] offset
        GIM_CheckIsImm, /*MI*/0, /*Op*/6,
        // MIs[0] auxiliary
        GIM_CheckIsImm, /*MI*/0, /*Op*/7,
        // MIs[0] Operand 8
        GIM_CheckLiteralInt, /*MI*/0, /*Op*/8, GIMT_Encode8(0),
        GIM_CheckComplexPattern, /*MI*/0, /*Op*/5, /*Renderer*/GIMT_Encode2(0), GIMT_Encode2(GICP_gi_buf_soffset),
        // (SIbuffer_atomic_umin:{ *:[i64] } i64:{ *:[i64] }:$vdata_in, v4i32:{ *:[v4i32] }:$rsrc, 0:{ *:[i32] }, 0:{ *:[i32] }, (BUFSOffset:{ *:[i32] } i32:{ *:[i32] }:$soffset), (timm:{ *:[i32] }):$offset, (timm:{ *:[i32] }):$auxiliary, 0:{ *:[i1] })  =>  (BUFFER_ATOMIC_UMIN_X2_VBUFFER_OFFSET_RTN:{ *:[i64] } anonymous_15036:{ *:[i64] }:$vdata_in, SReg_128:{ *:[v4i32] }:$rsrc, SCSrc_b32:{ *:[i32] }:$soffset, (timm:{ *:[i32] }):$offset, (extract_cpol_set_glc:{ *:[i32] } ?:{ *:[i32] }:$auxiliary))
        GIR_BuildMI, /*InsnID*/0, /*Opcode*/GIMT_Encode2(AMDGPU::BUFFER_ATOMIC_UMIN_X2_VBUFFER_OFFSET_RTN),
        GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/0, // DstI[vdata]
        GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/1, // vdata_in
        GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/2, // rsrc
        GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/0, // soffset
        GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/6, // offset
        GIR_CustomOperandRenderer, /*InsnID*/0, /*OldInsnID*/0, /*OpIdx*/7, /*OperandRenderer*/GIMT_Encode2(GICR_renderExtractCpolSetGLC), // auxiliary
        GIR_MergeMemOperands, /*InsnID*/0, /*NumInsns*/1, /*MergeInsnID's*/0,
        GIR_ConstrainSelectedInstOperands, /*InsnID*/0,
        GIR_EraseFromParent, /*InsnID*/0,
        // GIR_Coverage, 5001,
        GIR_Done,
      // Label 6341: @464888
      GIM_Try, /*On fail goto*//*Label 6342*/ GIMT_Encode4(464966), // Rule ID 4999 //
        GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasUnrestrictedSOffset),
        GIM_CheckHasNoUse, /*MI*/0,
        GIM_CheckConstantInt8, /*MI*/0, /*Op*/3, 0,
        // MIs[0] offset
        GIM_CheckIsImm, /*MI*/0, /*Op*/6,
        // MIs[0] auxiliary
        GIM_CheckIsImm, /*MI*/0, /*Op*/7,
        // MIs[0] Operand 8
        GIM_CheckLiteralInt, /*MI*/0, /*Op*/8, GIMT_Encode8(0),
        GIM_CheckComplexPattern, /*MI*/0, /*Op*/5, /*Renderer*/GIMT_Encode2(0), GIMT_Encode2(GICP_gi_buf_soffset),
        // (SIbuffer_atomic_umin:{ *:[i64] } i64:{ *:[i64] }:$vdata_in, v4i32:{ *:[v4i32] }:$rsrc, 0:{ *:[i32] }, i32:{ *:[i32] }:$voffset, (BUFSOffset:{ *:[i32] } i32:{ *:[i32] }:$soffset), (timm:{ *:[i32] }):$offset, (timm:{ *:[i32] }):$auxiliary, 0:{ *:[i1] })<<P:Predicate_SIbuffer_atomic_umin_noret>>  =>  (BUFFER_ATOMIC_UMIN_X2_OFFEN anonymous_15036:{ *:[i64] }:$vdata_in, VGPR_32:{ *:[i32] }:$voffset, SReg_128:{ *:[v4i32] }:$rsrc, SCSrc_b32:{ *:[i32] }:$soffset, (timm:{ *:[i32] }):$offset, (extract_cpol:{ *:[i32] } ?:{ *:[i32] }:$auxiliary))
        GIR_BuildMI, /*InsnID*/0, /*Opcode*/GIMT_Encode2(AMDGPU::BUFFER_ATOMIC_UMIN_X2_OFFEN),
        GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/1, // vdata_in
        GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/4, // voffset
        GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/2, // rsrc
        GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/0, // soffset
        GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/6, // offset
        GIR_CustomOperandRenderer, /*InsnID*/0, /*OldInsnID*/0, /*OpIdx*/7, /*OperandRenderer*/GIMT_Encode2(GICR_renderExtractCPol), // auxiliary
        GIR_MergeMemOperands, /*InsnID*/0, /*NumInsns*/1, /*MergeInsnID's*/0,
        GIR_ConstrainSelectedInstOperands, /*InsnID*/0,
        GIR_EraseFromParent, /*InsnID*/0,
        // GIR_Coverage, 4999,
        GIR_Done,
      // Label 6342: @464966
      GIM_Try, /*On fail goto*//*Label 6343*/ GIMT_Encode4(465041), // Rule ID 5007 //
        GIM_CheckHasNoUse, /*MI*/0,
        GIM_CheckConstantInt8, /*MI*/0, /*Op*/3, 0,
        // MIs[0] offset
        GIM_CheckIsImm, /*MI*/0, /*Op*/6,
        // MIs[0] auxiliary
        GIM_CheckIsImm, /*MI*/0, /*Op*/7,
        // MIs[0] Operand 8
        GIM_CheckLiteralInt, /*MI*/0, /*Op*/8, GIMT_Encode8(0),
        GIM_CheckComplexPattern, /*MI*/0, /*Op*/5, /*Renderer*/GIMT_Encode2(0), GIMT_Encode2(GICP_gi_buf_soffset),
        // (SIbuffer_atomic_umin:{ *:[i64] } i64:{ *:[i64] }:$vdata_in, v4i32:{ *:[v4i32] }:$rsrc, 0:{ *:[i32] }, i32:{ *:[i32] }:$voffset, (BUFSOffset:{ *:[i32] } i32:{ *:[i32] }:$soffset), (timm:{ *:[i32] }):$offset, (timm:{ *:[i32] }):$auxiliary, 0:{ *:[i1] })<<P:Predicate_SIbuffer_atomic_umin_noret>>  =>  (BUFFER_ATOMIC_UMIN_X2_VBUFFER_OFFEN anonymous_15036:{ *:[i64] }:$vdata_in, VGPR_32:{ *:[i32] }:$voffset, SReg_128:{ *:[v4i32] }:$rsrc, SCSrc_b32:{ *:[i32] }:$soffset, (timm:{ *:[i32] }):$offset, (extract_cpol:{ *:[i32] } ?:{ *:[i32] }:$auxiliary))
        GIR_BuildMI, /*InsnID*/0, /*Opcode*/GIMT_Encode2(AMDGPU::BUFFER_ATOMIC_UMIN_X2_VBUFFER_OFFEN),
        GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/1, // vdata_in
        GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/4, // voffset
        GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/2, // rsrc
        GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/0, // soffset
        GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/6, // offset
        GIR_CustomOperandRenderer, /*InsnID*/0, /*OldInsnID*/0, /*OpIdx*/7, /*OperandRenderer*/GIMT_Encode2(GICR_renderExtractCPol), // auxiliary
        GIR_MergeMemOperands, /*InsnID*/0, /*NumInsns*/1, /*MergeInsnID's*/0,
        GIR_ConstrainSelectedInstOperands, /*InsnID*/0,
        GIR_EraseFromParent, /*InsnID*/0,
        // GIR_Coverage, 5007,
        GIR_Done,
      // Label 6343: @465041
      GIM_Try, /*On fail goto*//*Label 6344*/ GIMT_Encode4(465126), // Rule ID 4995 //
        GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasUnrestrictedSOffset),
        GIM_CheckRegBankForClass, /*MI*/0, /*Op*/0, /*RC*/GIMT_Encode2(AMDGPU::AV_64RegClassID),
        GIM_CheckConstantInt8, /*MI*/0, /*Op*/3, 0,
        // MIs[0] offset
        GIM_CheckIsImm, /*MI*/0, /*Op*/6,
        // MIs[0] auxiliary
        GIM_CheckIsImm, /*MI*/0, /*Op*/7,
        // MIs[0] Operand 8
        GIM_CheckLiteralInt, /*MI*/0, /*Op*/8, GIMT_Encode8(0),
        GIM_CheckComplexPattern, /*MI*/0, /*Op*/5, /*Renderer*/GIMT_Encode2(0), GIMT_Encode2(GICP_gi_buf_soffset),
        // (SIbuffer_atomic_umin:{ *:[i64] } i64:{ *:[i64] }:$vdata_in, v4i32:{ *:[v4i32] }:$rsrc, 0:{ *:[i32] }, i32:{ *:[i32] }:$voffset, (BUFSOffset:{ *:[i32] } i32:{ *:[i32] }:$soffset), (timm:{ *:[i32] }):$offset, (timm:{ *:[i32] }):$auxiliary, 0:{ *:[i1] })  =>  (BUFFER_ATOMIC_UMIN_X2_OFFEN_RTN:{ *:[i64] } anonymous_15036:{ *:[i64] }:$vdata_in, VGPR_32:{ *:[i32] }:$voffset, SReg_128:{ *:[v4i32] }:$rsrc, SCSrc_b32:{ *:[i32] }:$soffset, (timm:{ *:[i32] }):$offset, (extract_cpol_set_glc:{ *:[i32] } ?:{ *:[i32] }:$auxiliary))
        GIR_BuildMI, /*InsnID*/0, /*Opcode*/GIMT_Encode2(AMDGPU::BUFFER_ATOMIC_UMIN_X2_OFFEN_RTN),
        GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/0, // DstI[vdata]
        GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/1, // vdata_in
        GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/4, // voffset
        GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/2, // rsrc
        GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/0, // soffset
        GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/6, // offset
        GIR_CustomOperandRenderer, /*InsnID*/0, /*OldInsnID*/0, /*OpIdx*/7, /*OperandRenderer*/GIMT_Encode2(GICR_renderExtractCpolSetGLC), // auxiliary
        GIR_MergeMemOperands, /*InsnID*/0, /*NumInsns*/1, /*MergeInsnID's*/0,
        GIR_ConstrainSelectedInstOperands, /*InsnID*/0,
        GIR_EraseFromParent, /*InsnID*/0,
        // GIR_Coverage, 4995,
        GIR_Done,
      // Label 6344: @465126
      GIM_Try, /*On fail goto*//*Label 6345*/ GIMT_Encode4(465208), // Rule ID 5003 //
        GIM_CheckRegBankForClass, /*MI*/0, /*Op*/0, /*RC*/GIMT_Encode2(AMDGPU::AV_64RegClassID),
        GIM_CheckConstantInt8, /*MI*/0, /*Op*/3, 0,
        // MIs[0] offset
        GIM_CheckIsImm, /*MI*/0, /*Op*/6,
        // MIs[0] auxiliary
        GIM_CheckIsImm, /*MI*/0, /*Op*/7,
        // MIs[0] Operand 8
        GIM_CheckLiteralInt, /*MI*/0, /*Op*/8, GIMT_Encode8(0),
        GIM_CheckComplexPattern, /*MI*/0, /*Op*/5, /*Renderer*/GIMT_Encode2(0), GIMT_Encode2(GICP_gi_buf_soffset),
        // (SIbuffer_atomic_umin:{ *:[i64] } i64:{ *:[i64] }:$vdata_in, v4i32:{ *:[v4i32] }:$rsrc, 0:{ *:[i32] }, i32:{ *:[i32] }:$voffset, (BUFSOffset:{ *:[i32] } i32:{ *:[i32] }:$soffset), (timm:{ *:[i32] }):$offset, (timm:{ *:[i32] }):$auxiliary, 0:{ *:[i1] })  =>  (BUFFER_ATOMIC_UMIN_X2_VBUFFER_OFFEN_RTN:{ *:[i64] } anonymous_15036:{ *:[i64] }:$vdata_in, VGPR_32:{ *:[i32] }:$voffset, SReg_128:{ *:[v4i32] }:$rsrc, SCSrc_b32:{ *:[i32] }:$soffset, (timm:{ *:[i32] }):$offset, (extract_cpol_set_glc:{ *:[i32] } ?:{ *:[i32] }:$auxiliary))
        GIR_BuildMI, /*InsnID*/0, /*Opcode*/GIMT_Encode2(AMDGPU::BUFFER_ATOMIC_UMIN_X2_VBUFFER_OFFEN_RTN),
        GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/0, // DstI[vdata]
        GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/1, // vdata_in
        GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/4, // voffset
        GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/2, // rsrc
        GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/0, // soffset
        GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/6, // offset
        GIR_CustomOperandRenderer, /*InsnID*/0, /*OldInsnID*/0, /*OpIdx*/7, /*OperandRenderer*/GIMT_Encode2(GICR_renderExtractCpolSetGLC), // auxiliary
        GIR_MergeMemOperands, /*InsnID*/0, /*NumInsns*/1, /*MergeInsnID's*/0,
        GIR_ConstrainSelectedInstOperands, /*InsnID*/0,
        GIR_EraseFromParent, /*InsnID*/0,
        // GIR_Coverage, 5003,
        GIR_Done,
      // Label 6345: @465208
      GIM_Try, /*On fail goto*//*Label 6346*/ GIMT_Encode4(465278), // Rule ID 4998 //
        GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasUnrestrictedSOffset),
        GIM_CheckHasNoUse, /*MI*/0,
        GIM_CheckConstantInt8, /*MI*/0, /*Op*/4, 0,
        // MIs[0] offset
        GIM_CheckIsImm, /*MI*/0, /*Op*/6,
        // MIs[0] auxiliary
        GIM_CheckIsImm, /*MI*/0, /*Op*/7,
        // MIs[0] Operand 8
        GIM_CheckIsImm, /*MI*/0, /*Op*/8,
        GIM_CheckComplexPattern, /*MI*/0, /*Op*/5, /*Renderer*/GIMT_Encode2(0), GIMT_Encode2(GICP_gi_buf_soffset),
        // (SIbuffer_atomic_umin:{ *:[i64] } i64:{ *:[i64] }:$vdata_in, v4i32:{ *:[v4i32] }:$rsrc, i32:{ *:[i32] }:$vindex, 0:{ *:[i32] }, (BUFSOffset:{ *:[i32] } i32:{ *:[i32] }:$soffset), (timm:{ *:[i32] }):$offset, (timm:{ *:[i32] }):$auxiliary, (timm:{ *:[i1] }))<<P:Predicate_SIbuffer_atomic_umin_noret>>  =>  (BUFFER_ATOMIC_UMIN_X2_IDXEN anonymous_15036:{ *:[i64] }:$vdata_in, VGPR_32:{ *:[i32] }:$vindex, SReg_128:{ *:[v4i32] }:$rsrc, SCSrc_b32:{ *:[i32] }:$soffset, (timm:{ *:[i32] }):$offset, (extract_cpol:{ *:[i32] } ?:{ *:[i32] }:$auxiliary))
        GIR_BuildMI, /*InsnID*/0, /*Opcode*/GIMT_Encode2(AMDGPU::BUFFER_ATOMIC_UMIN_X2_IDXEN),
        GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/1, // vdata_in
        GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/3, // vindex
        GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/2, // rsrc
        GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/0, // soffset
        GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/6, // offset
        GIR_CustomOperandRenderer, /*InsnID*/0, /*OldInsnID*/0, /*OpIdx*/7, /*OperandRenderer*/GIMT_Encode2(GICR_renderExtractCPol), // auxiliary
        GIR_MergeMemOperands, /*InsnID*/0, /*NumInsns*/1, /*MergeInsnID's*/0,
        GIR_ConstrainSelectedInstOperands, /*InsnID*/0,
        GIR_EraseFromParent, /*InsnID*/0,
        // GIR_Coverage, 4998,
        GIR_Done,
      // Label 6346: @465278
      GIM_Try, /*On fail goto*//*Label 6347*/ GIMT_Encode4(465345), // Rule ID 5006 //
        GIM_CheckHasNoUse, /*MI*/0,
        GIM_CheckConstantInt8, /*MI*/0, /*Op*/4, 0,
        // MIs[0] offset
        GIM_CheckIsImm, /*MI*/0, /*Op*/6,
        // MIs[0] auxiliary
        GIM_CheckIsImm, /*MI*/0, /*Op*/7,
        // MIs[0] Operand 8
        GIM_CheckIsImm, /*MI*/0, /*Op*/8,
        GIM_CheckComplexPattern, /*MI*/0, /*Op*/5, /*Renderer*/GIMT_Encode2(0), GIMT_Encode2(GICP_gi_buf_soffset),
        // (SIbuffer_atomic_umin:{ *:[i64] } i64:{ *:[i64] }:$vdata_in, v4i32:{ *:[v4i32] }:$rsrc, i32:{ *:[i32] }:$vindex, 0:{ *:[i32] }, (BUFSOffset:{ *:[i32] } i32:{ *:[i32] }:$soffset), (timm:{ *:[i32] }):$offset, (timm:{ *:[i32] }):$auxiliary, (timm:{ *:[i1] }))<<P:Predicate_SIbuffer_atomic_umin_noret>>  =>  (BUFFER_ATOMIC_UMIN_X2_VBUFFER_IDXEN anonymous_15036:{ *:[i64] }:$vdata_in, VGPR_32:{ *:[i32] }:$vindex, SReg_128:{ *:[v4i32] }:$rsrc, SCSrc_b32:{ *:[i32] }:$soffset, (timm:{ *:[i32] }):$offset, (extract_cpol:{ *:[i32] } ?:{ *:[i32] }:$auxiliary))
        GIR_BuildMI, /*InsnID*/0, /*Opcode*/GIMT_Encode2(AMDGPU::BUFFER_ATOMIC_UMIN_X2_VBUFFER_IDXEN),
        GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/1, // vdata_in
        GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/3, // vindex
        GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/2, // rsrc
        GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/0, // soffset
        GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/6, // offset
        GIR_CustomOperandRenderer, /*InsnID*/0, /*OldInsnID*/0, /*OpIdx*/7, /*OperandRenderer*/GIMT_Encode2(GICR_renderExtractCPol), // auxiliary
        GIR_MergeMemOperands, /*InsnID*/0, /*NumInsns*/1, /*MergeInsnID's*/0,
        GIR_ConstrainSelectedInstOperands, /*InsnID*/0,
        GIR_EraseFromParent, /*InsnID*/0,
        // GIR_Coverage, 5006,
        GIR_Done,
      // Label 6347: @465345
      GIM_Try, /*On fail goto*//*Label 6348*/ GIMT_Encode4(465422), // Rule ID 4994 //
        GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasUnrestrictedSOffset),
        GIM_CheckRegBankForClass, /*MI*/0, /*Op*/0, /*RC*/GIMT_Encode2(AMDGPU::AV_64RegClassID),
        GIM_CheckConstantInt8, /*MI*/0, /*Op*/4, 0,
        // MIs[0] offset
        GIM_CheckIsImm, /*MI*/0, /*Op*/6,
        // MIs[0] auxiliary
        GIM_CheckIsImm, /*MI*/0, /*Op*/7,
        // MIs[0] Operand 8
        GIM_CheckIsImm, /*MI*/0, /*Op*/8,
        GIM_CheckComplexPattern, /*MI*/0, /*Op*/5, /*Renderer*/GIMT_Encode2(0), GIMT_Encode2(GICP_gi_buf_soffset),
        // (SIbuffer_atomic_umin:{ *:[i64] } i64:{ *:[i64] }:$vdata_in, v4i32:{ *:[v4i32] }:$rsrc, i32:{ *:[i32] }:$vindex, 0:{ *:[i32] }, (BUFSOffset:{ *:[i32] } i32:{ *:[i32] }:$soffset), (timm:{ *:[i32] }):$offset, (timm:{ *:[i32] }):$auxiliary, (timm:{ *:[i1] }))  =>  (BUFFER_ATOMIC_UMIN_X2_IDXEN_RTN:{ *:[i64] } anonymous_15036:{ *:[i64] }:$vdata_in, VGPR_32:{ *:[i32] }:$vindex, SReg_128:{ *:[v4i32] }:$rsrc, SCSrc_b32:{ *:[i32] }:$soffset, (timm:{ *:[i32] }):$offset, (extract_cpol_set_glc:{ *:[i32] } ?:{ *:[i32] }:$auxiliary))
        GIR_BuildMI, /*InsnID*/0, /*Opcode*/GIMT_Encode2(AMDGPU::BUFFER_ATOMIC_UMIN_X2_IDXEN_RTN),
        GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/0, // DstI[vdata]
        GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/1, // vdata_in
        GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/3, // vindex
        GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/2, // rsrc
        GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/0, // soffset
        GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/6, // offset
        GIR_CustomOperandRenderer, /*InsnID*/0, /*OldInsnID*/0, /*OpIdx*/7, /*OperandRenderer*/GIMT_Encode2(GICR_renderExtractCpolSetGLC), // auxiliary
        GIR_MergeMemOperands, /*InsnID*/0, /*NumInsns*/1, /*MergeInsnID's*/0,
        GIR_ConstrainSelectedInstOperands, /*InsnID*/0,
        GIR_EraseFromParent, /*InsnID*/0,
        // GIR_Coverage, 4994,
        GIR_Done,
      // Label 6348: @465422
      GIM_Try, /*On fail goto*//*Label 6349*/ GIMT_Encode4(465496), // Rule ID 5002 //
        GIM_CheckRegBankForClass, /*MI*/0, /*Op*/0, /*RC*/GIMT_Encode2(AMDGPU::AV_64RegClassID),
        GIM_CheckConstantInt8, /*MI*/0, /*Op*/4, 0,
        // MIs[0] offset
        GIM_CheckIsImm, /*MI*/0, /*Op*/6,
        // MIs[0] auxiliary
        GIM_CheckIsImm, /*MI*/0, /*Op*/7,
        // MIs[0] Operand 8
        GIM_CheckIsImm, /*MI*/0, /*Op*/8,
        GIM_CheckComplexPattern, /*MI*/0, /*Op*/5, /*Renderer*/GIMT_Encode2(0), GIMT_Encode2(GICP_gi_buf_soffset),
        // (SIbuffer_atomic_umin:{ *:[i64] } i64:{ *:[i64] }:$vdata_in, v4i32:{ *:[v4i32] }:$rsrc, i32:{ *:[i32] }:$vindex, 0:{ *:[i32] }, (BUFSOffset:{ *:[i32] } i32:{ *:[i32] }:$soffset), (timm:{ *:[i32] }):$offset, (timm:{ *:[i32] }):$auxiliary, (timm:{ *:[i1] }))  =>  (BUFFER_ATOMIC_UMIN_X2_VBUFFER_IDXEN_RTN:{ *:[i64] } anonymous_15036:{ *:[i64] }:$vdata_in, VGPR_32:{ *:[i32] }:$vindex, SReg_128:{ *:[v4i32] }:$rsrc, SCSrc_b32:{ *:[i32] }:$soffset, (timm:{ *:[i32] }):$offset, (extract_cpol_set_glc:{ *:[i32] } ?:{ *:[i32] }:$auxiliary))
        GIR_BuildMI, /*InsnID*/0, /*Opcode*/GIMT_Encode2(AMDGPU::BUFFER_ATOMIC_UMIN_X2_VBUFFER_IDXEN_RTN),
        GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/0, // DstI[vdata]
        GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/1, // vdata_in
        GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/3, // vindex
        GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/2, // rsrc
        GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/0, // soffset
        GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/6, // offset
        GIR_CustomOperandRenderer, /*InsnID*/0, /*OldInsnID*/0, /*OpIdx*/7, /*OperandRenderer*/GIMT_Encode2(GICR_renderExtractCpolSetGLC), // auxiliary
        GIR_MergeMemOperands, /*InsnID*/0, /*NumInsns*/1, /*MergeInsnID's*/0,
        GIR_ConstrainSelectedInstOperands, /*InsnID*/0,
        GIR_EraseFromParent, /*InsnID*/0,
        // GIR_Coverage, 5002,
        GIR_Done,
      // Label 6349: @465496
      GIM_Try, /*On fail goto*//*Label 6350*/ GIMT_Encode4(465602), // Rule ID 5000 //
        GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasUnrestrictedSOffset),
        GIM_CheckHasNoUse, /*MI*/0,
        // MIs[0] offset
        GIM_CheckIsImm, /*MI*/0, /*Op*/6,
        // MIs[0] auxiliary
        GIM_CheckIsImm, /*MI*/0, /*Op*/7,
        // MIs[0] Operand 8
        GIM_CheckIsImm, /*MI*/0, /*Op*/8,
        GIM_CheckComplexPattern, /*MI*/0, /*Op*/5, /*Renderer*/GIMT_Encode2(0), GIMT_Encode2(GICP_gi_buf_soffset),
        // (SIbuffer_atomic_umin:{ *:[i64] } i64:{ *:[i64] }:$vdata_in, v4i32:{ *:[v4i32] }:$rsrc, i32:{ *:[i32] }:$vindex, i32:{ *:[i32] }:$voffset, (BUFSOffset:{ *:[i32] } i32:{ *:[i32] }:$soffset), (timm:{ *:[i32] }):$offset, (timm:{ *:[i32] }):$auxiliary, (timm:{ *:[i1] }))<<P:Predicate_SIbuffer_atomic_umin_noret>>  =>  (BUFFER_ATOMIC_UMIN_X2_BOTHEN anonymous_15036:{ *:[i64] }:$vdata_in, (REG_SEQUENCE:{ *:[i64] } VReg_64:{ *:[i32] }, VGPR_32:{ *:[i32] }:$vindex, sub0:{ *:[i32] }, VGPR_32:{ *:[i32] }:$voffset, sub1:{ *:[i32] }), SReg_128:{ *:[v4i32] }:$rsrc, SCSrc_b32:{ *:[i32] }:$soffset, (timm:{ *:[i32] }):$offset, (extract_cpol:{ *:[i32] } ?:{ *:[i32] }:$auxiliary))
        GIR_MakeTempReg, /*TempRegID*/0, /*TypeID*/GILLT_s64,
        GIR_BuildMI, /*InsnID*/1, /*Opcode*/GIMT_Encode2(TargetOpcode::REG_SEQUENCE),
        GIR_AddTempRegister, /*InsnID*/1, /*TempRegID*/0, /*TempRegFlags*/GIMT_Encode2(RegState::Define),
        GIR_Copy, /*NewInsnID*/1, /*OldInsnID*/0, /*OpIdx*/3, // vindex
        GIR_AddImm8, /*InsnID*/1, /*SubRegIndex*/3,
        GIR_Copy, /*NewInsnID*/1, /*OldInsnID*/0, /*OpIdx*/4, // voffset
        GIR_AddImm8, /*InsnID*/1, /*SubRegIndex*/11,
        GIR_ConstrainOperandRC, /*InsnID*/1, /*Op*/0, GIMT_Encode2(AMDGPU::VReg_64RegClassID),
        GIR_ConstrainOperandRC, /*InsnID*/1, /*Op*/1, GIMT_Encode2(AMDGPU::VGPR_32RegClassID),
        GIR_ConstrainOperandRC, /*InsnID*/1, /*Op*/3, GIMT_Encode2(AMDGPU::VGPR_32RegClassID),
        GIR_BuildMI, /*InsnID*/0, /*Opcode*/GIMT_Encode2(AMDGPU::BUFFER_ATOMIC_UMIN_X2_BOTHEN),
        GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/1, // vdata_in
        GIR_AddSimpleTempRegister, /*InsnID*/0, /*TempRegID*/0,
        GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/2, // rsrc
        GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/0, // soffset
        GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/6, // offset
        GIR_CustomOperandRenderer, /*InsnID*/0, /*OldInsnID*/0, /*OpIdx*/7, /*OperandRenderer*/GIMT_Encode2(GICR_renderExtractCPol), // auxiliary
        GIR_MergeMemOperands, /*InsnID*/0, /*NumInsns*/1, /*MergeInsnID's*/0,
        GIR_ConstrainSelectedInstOperands, /*InsnID*/0,
        GIR_EraseFromParent, /*InsnID*/0,
        // GIR_Coverage, 5000,
        GIR_Done,
      // Label 6350: @465602
      GIM_Try, /*On fail goto*//*Label 6351*/ GIMT_Encode4(465705), // Rule ID 5008 //
        GIM_CheckHasNoUse, /*MI*/0,
        // MIs[0] offset
        GIM_CheckIsImm, /*MI*/0, /*Op*/6,
        // MIs[0] auxiliary
        GIM_CheckIsImm, /*MI*/0, /*Op*/7,
        // MIs[0] Operand 8
        GIM_CheckIsImm, /*MI*/0, /*Op*/8,
        GIM_CheckComplexPattern, /*MI*/0, /*Op*/5, /*Renderer*/GIMT_Encode2(0), GIMT_Encode2(GICP_gi_buf_soffset),
        // (SIbuffer_atomic_umin:{ *:[i64] } i64:{ *:[i64] }:$vdata_in, v4i32:{ *:[v4i32] }:$rsrc, i32:{ *:[i32] }:$vindex, i32:{ *:[i32] }:$voffset, (BUFSOffset:{ *:[i32] } i32:{ *:[i32] }:$soffset), (timm:{ *:[i32] }):$offset, (timm:{ *:[i32] }):$auxiliary, (timm:{ *:[i1] }))<<P:Predicate_SIbuffer_atomic_umin_noret>>  =>  (BUFFER_ATOMIC_UMIN_X2_VBUFFER_BOTHEN anonymous_15036:{ *:[i64] }:$vdata_in, (REG_SEQUENCE:{ *:[i64] } VReg_64:{ *:[i32] }, VGPR_32:{ *:[i32] }:$vindex, sub0:{ *:[i32] }, VGPR_32:{ *:[i32] }:$voffset, sub1:{ *:[i32] }), SReg_128:{ *:[v4i32] }:$rsrc, SCSrc_b32:{ *:[i32] }:$soffset, (timm:{ *:[i32] }):$offset, (extract_cpol:{ *:[i32] } ?:{ *:[i32] }:$auxiliary))
        GIR_MakeTempReg, /*TempRegID*/0, /*TypeID*/GILLT_s64,
        GIR_BuildMI, /*InsnID*/1, /*Opcode*/GIMT_Encode2(TargetOpcode::REG_SEQUENCE),
        GIR_AddTempRegister, /*InsnID*/1, /*TempRegID*/0, /*TempRegFlags*/GIMT_Encode2(RegState::Define),
        GIR_Copy, /*NewInsnID*/1, /*OldInsnID*/0, /*OpIdx*/3, // vindex
        GIR_AddImm8, /*InsnID*/1, /*SubRegIndex*/3,
        GIR_Copy, /*NewInsnID*/1, /*OldInsnID*/0, /*OpIdx*/4, // voffset
        GIR_AddImm8, /*InsnID*/1, /*SubRegIndex*/11,
        GIR_ConstrainOperandRC, /*InsnID*/1, /*Op*/0, GIMT_Encode2(AMDGPU::VReg_64RegClassID),
        GIR_ConstrainOperandRC, /*InsnID*/1, /*Op*/1, GIMT_Encode2(AMDGPU::VGPR_32RegClassID),
        GIR_ConstrainOperandRC, /*InsnID*/1, /*Op*/3, GIMT_Encode2(AMDGPU::VGPR_32RegClassID),
        GIR_BuildMI, /*InsnID*/0, /*Opcode*/GIMT_Encode2(AMDGPU::BUFFER_ATOMIC_UMIN_X2_VBUFFER_BOTHEN),
        GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/1, // vdata_in
        GIR_AddSimpleTempRegister, /*InsnID*/0, /*TempRegID*/0,
        GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/2, // rsrc
        GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/0, // soffset
        GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/6, // offset
        GIR_CustomOperandRenderer, /*InsnID*/0, /*OldInsnID*/0, /*OpIdx*/7, /*OperandRenderer*/GIMT_Encode2(GICR_renderExtractCPol), // auxiliary
        GIR_MergeMemOperands, /*InsnID*/0, /*NumInsns*/1, /*MergeInsnID's*/0,
        GIR_ConstrainSelectedInstOperands, /*InsnID*/0,
        GIR_EraseFromParent, /*InsnID*/0,
        // GIR_Coverage, 5008,
        GIR_Done,
      // Label 6351: @465705
      GIM_Try, /*On fail goto*//*Label 6352*/ GIMT_Encode4(465818), // Rule ID 4996 //
        GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasUnrestrictedSOffset),
        GIM_CheckRegBankForClass, /*MI*/0, /*Op*/0, /*RC*/GIMT_Encode2(AMDGPU::AV_64RegClassID),
        // MIs[0] offset
        GIM_CheckIsImm, /*MI*/0, /*Op*/6,
        // MIs[0] auxiliary
        GIM_CheckIsImm, /*MI*/0, /*Op*/7,
        // MIs[0] Operand 8
        GIM_CheckIsImm, /*MI*/0, /*Op*/8,
        GIM_CheckComplexPattern, /*MI*/0, /*Op*/5, /*Renderer*/GIMT_Encode2(0), GIMT_Encode2(GICP_gi_buf_soffset),
        // (SIbuffer_atomic_umin:{ *:[i64] } i64:{ *:[i64] }:$vdata_in, v4i32:{ *:[v4i32] }:$rsrc, i32:{ *:[i32] }:$vindex, i32:{ *:[i32] }:$voffset, (BUFSOffset:{ *:[i32] } i32:{ *:[i32] }:$soffset), (timm:{ *:[i32] }):$offset, (timm:{ *:[i32] }):$auxiliary, (timm:{ *:[i1] }))  =>  (BUFFER_ATOMIC_UMIN_X2_BOTHEN_RTN:{ *:[i64] } anonymous_15036:{ *:[i64] }:$vdata_in, (REG_SEQUENCE:{ *:[i64] } VReg_64:{ *:[i32] }, VGPR_32:{ *:[i32] }:$vindex, sub0:{ *:[i32] }, VGPR_32:{ *:[i32] }:$voffset, sub1:{ *:[i32] }), SReg_128:{ *:[v4i32] }:$rsrc, SCSrc_b32:{ *:[i32] }:$soffset, (timm:{ *:[i32] }):$offset, (extract_cpol_set_glc:{ *:[i32] } ?:{ *:[i32] }:$auxiliary))
        GIR_MakeTempReg, /*TempRegID*/0, /*TypeID*/GILLT_s64,
        GIR_BuildMI, /*InsnID*/1, /*Opcode*/GIMT_Encode2(TargetOpcode::REG_SEQUENCE),
        GIR_AddTempRegister, /*InsnID*/1, /*TempRegID*/0, /*TempRegFlags*/GIMT_Encode2(RegState::Define),
        GIR_Copy, /*NewInsnID*/1, /*OldInsnID*/0, /*OpIdx*/3, // vindex
        GIR_AddImm8, /*InsnID*/1, /*SubRegIndex*/3,
        GIR_Copy, /*NewInsnID*/1, /*OldInsnID*/0, /*OpIdx*/4, // voffset
        GIR_AddImm8, /*InsnID*/1, /*SubRegIndex*/11,
        GIR_ConstrainOperandRC, /*InsnID*/1, /*Op*/0, GIMT_Encode2(AMDGPU::VReg_64RegClassID),
        GIR_ConstrainOperandRC, /*InsnID*/1, /*Op*/1, GIMT_Encode2(AMDGPU::VGPR_32RegClassID),
        GIR_ConstrainOperandRC, /*InsnID*/1, /*Op*/3, GIMT_Encode2(AMDGPU::VGPR_32RegClassID),
        GIR_BuildMI, /*InsnID*/0, /*Opcode*/GIMT_Encode2(AMDGPU::BUFFER_ATOMIC_UMIN_X2_BOTHEN_RTN),
        GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/0, // DstI[vdata]
        GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/1, // vdata_in
        GIR_AddSimpleTempRegister, /*InsnID*/0, /*TempRegID*/0,
        GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/2, // rsrc
        GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/0, // soffset
        GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/6, // offset
        GIR_CustomOperandRenderer, /*InsnID*/0, /*OldInsnID*/0, /*OpIdx*/7, /*OperandRenderer*/GIMT_Encode2(GICR_renderExtractCpolSetGLC), // auxiliary
        GIR_MergeMemOperands, /*InsnID*/0, /*NumInsns*/1, /*MergeInsnID's*/0,
        GIR_ConstrainSelectedInstOperands, /*InsnID*/0,
        GIR_EraseFromParent, /*InsnID*/0,
        // GIR_Coverage, 4996,
        GIR_Done,
      // Label 6352: @465818
      GIM_Try, /*On fail goto*//*Label 6353*/ GIMT_Encode4(465928), // Rule ID 5004 //
        GIM_CheckRegBankForClass, /*MI*/0, /*Op*/0, /*RC*/GIMT_Encode2(AMDGPU::AV_64RegClassID),
        // MIs[0] offset
        GIM_CheckIsImm, /*MI*/0, /*Op*/6,
        // MIs[0] auxiliary
        GIM_CheckIsImm, /*MI*/0, /*Op*/7,
        // MIs[0] Operand 8
        GIM_CheckIsImm, /*MI*/0, /*Op*/8,
        GIM_CheckComplexPattern, /*MI*/0, /*Op*/5, /*Renderer*/GIMT_Encode2(0), GIMT_Encode2(GICP_gi_buf_soffset),
        // (SIbuffer_atomic_umin:{ *:[i64] } i64:{ *:[i64] }:$vdata_in, v4i32:{ *:[v4i32] }:$rsrc, i32:{ *:[i32] }:$vindex, i32:{ *:[i32] }:$voffset, (BUFSOffset:{ *:[i32] } i32:{ *:[i32] }:$soffset), (timm:{ *:[i32] }):$offset, (timm:{ *:[i32] }):$auxiliary, (timm:{ *:[i1] }))  =>  (BUFFER_ATOMIC_UMIN_X2_VBUFFER_BOTHEN_RTN:{ *:[i64] } anonymous_15036:{ *:[i64] }:$vdata_in, (REG_SEQUENCE:{ *:[i64] } VReg_64:{ *:[i32] }, VGPR_32:{ *:[i32] }:$vindex, sub0:{ *:[i32] }, VGPR_32:{ *:[i32] }:$voffset, sub1:{ *:[i32] }), SReg_128:{ *:[v4i32] }:$rsrc, SCSrc_b32:{ *:[i32] }:$soffset, (timm:{ *:[i32] }):$offset, (extract_cpol_set_glc:{ *:[i32] } ?:{ *:[i32] }:$auxiliary))
        GIR_MakeTempReg, /*TempRegID*/0, /*TypeID*/GILLT_s64,
        GIR_BuildMI, /*InsnID*/1, /*Opcode*/GIMT_Encode2(TargetOpcode::REG_SEQUENCE),
        GIR_AddTempRegister, /*InsnID*/1, /*TempRegID*/0, /*TempRegFlags*/GIMT_Encode2(RegState::Define),
        GIR_Copy, /*NewInsnID*/1, /*OldInsnID*/0, /*OpIdx*/3, // vindex
        GIR_AddImm8, /*InsnID*/1, /*SubRegIndex*/3,
        GIR_Copy, /*NewInsnID*/1, /*OldInsnID*/0, /*OpIdx*/4, // voffset
        GIR_AddImm8, /*InsnID*/1, /*SubRegIndex*/11,
        GIR_ConstrainOperandRC, /*InsnID*/1, /*Op*/0, GIMT_Encode2(AMDGPU::VReg_64RegClassID),
        GIR_ConstrainOperandRC, /*InsnID*/1, /*Op*/1, GIMT_Encode2(AMDGPU::VGPR_32RegClassID),
        GIR_ConstrainOperandRC, /*InsnID*/1, /*Op*/3, GIMT_Encode2(AMDGPU::VGPR_32RegClassID),
        GIR_BuildMI, /*InsnID*/0, /*Opcode*/GIMT_Encode2(AMDGPU::BUFFER_ATOMIC_UMIN_X2_VBUFFER_BOTHEN_RTN),
        GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/0, // DstI[vdata]
        GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/1, // vdata_in
        GIR_AddSimpleTempRegister, /*InsnID*/0, /*TempRegID*/0,
        GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/2, // rsrc
        GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/0, // soffset
        GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/6, // offset
        GIR_CustomOperandRenderer, /*InsnID*/0, /*OldInsnID*/0, /*OpIdx*/7, /*OperandRenderer*/GIMT_Encode2(GICR_renderExtractCpolSetGLC), // auxiliary
        GIR_MergeMemOperands, /*InsnID*/0, /*NumInsns*/1, /*MergeInsnID's*/0,
        GIR_ConstrainSelectedInstOperands, /*InsnID*/0,
        GIR_EraseFromParent, /*InsnID*/0,
        // GIR_Coverage, 5004,
        GIR_Done,
      // Label 6353: @465928
      GIM_Reject,
    // Label 6337: @465929
    GIM_Reject,
    // Label 6319: @465930
    GIM_Reject,
    // Label 123: @465931
    GIM_SwitchType, /*MI*/0, /*Op*/0, /*[*/GIMT_Encode2(9), GIMT_Encode2(11), /*)*//*default:*//*Label 6356*/ GIMT_Encode4(468724),
    /*GILLT_s32*//*Label 6354*/ GIMT_Encode4(465950),
    /*GILLT_s64*//*Label 6355*/ GIMT_Encode4(467337),
    // Label 6354: @465950
    GIM_Try, /*On fail goto*//*Label 6357*/ GIMT_Encode4(467336),
      GIM_CheckType, /*MI*/0, /*Op*/1, /*Type*/GILLT_s32,
      GIM_CheckType, /*MI*/0, /*Op*/2, /*Type*/GILLT_v4s32,
      GIM_CheckType, /*MI*/0, /*Op*/3, /*Type*/GILLT_s32,
      GIM_CheckType, /*MI*/0, /*Op*/4, /*Type*/GILLT_s32,
      GIM_CheckType, /*MI*/0, /*Op*/5, /*Type*/GILLT_s32,
      GIM_Try, /*On fail goto*//*Label 6358*/ GIMT_Encode4(466053), // Rule ID 4877 //
        GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasUnrestrictedSOffset),
        GIM_CheckHasNoUse, /*MI*/0,
        GIM_CheckConstantInt8, /*MI*/0, /*Op*/3, 0,
        GIM_CheckConstantInt8, /*MI*/0, /*Op*/4, 0,
        // MIs[0] offset
        GIM_CheckIsImm, /*MI*/0, /*Op*/6,
        // MIs[0] auxiliary
        GIM_CheckIsImm, /*MI*/0, /*Op*/7,
        // MIs[0] Operand 8
        GIM_CheckLiteralInt, /*MI*/0, /*Op*/8, GIMT_Encode8(0),
        GIM_CheckComplexPattern, /*MI*/0, /*Op*/5, /*Renderer*/GIMT_Encode2(0), GIMT_Encode2(GICP_gi_buf_soffset),
        // (SIbuffer_atomic_xor:{ *:[i32] } i32:{ *:[i32] }:$vdata_in, v4i32:{ *:[v4i32] }:$rsrc, 0:{ *:[i32] }, 0:{ *:[i32] }, (BUFSOffset:{ *:[i32] } i32:{ *:[i32] }:$soffset), (timm:{ *:[i32] }):$offset, (timm:{ *:[i32] }):$auxiliary, 0:{ *:[i1] })<<P:Predicate_SIbuffer_atomic_xor_noret>>  =>  (BUFFER_ATOMIC_XOR_OFFSET anonymous_15037:{ *:[i32] }:$vdata_in, SReg_128:{ *:[v4i32] }:$rsrc, SCSrc_b32:{ *:[i32] }:$soffset, (timm:{ *:[i32] }):$offset, (extract_cpol:{ *:[i32] } ?:{ *:[i32] }:$auxiliary))
        GIR_BuildMI, /*InsnID*/0, /*Opcode*/GIMT_Encode2(AMDGPU::BUFFER_ATOMIC_XOR_OFFSET),
        GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/1, // vdata_in
        GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/2, // rsrc
        GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/0, // soffset
        GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/6, // offset
        GIR_CustomOperandRenderer, /*InsnID*/0, /*OldInsnID*/0, /*OpIdx*/7, /*OperandRenderer*/GIMT_Encode2(GICR_renderExtractCPol), // auxiliary
        GIR_MergeMemOperands, /*InsnID*/0, /*NumInsns*/1, /*MergeInsnID's*/0,
        GIR_ConstrainSelectedInstOperands, /*InsnID*/0,
        GIR_EraseFromParent, /*InsnID*/0,
        // GIR_Coverage, 4877,
        GIR_Done,
      // Label 6358: @466053
      GIM_Try, /*On fail goto*//*Label 6359*/ GIMT_Encode4(466128), // Rule ID 4885 //
        GIM_CheckHasNoUse, /*MI*/0,
        GIM_CheckConstantInt8, /*MI*/0, /*Op*/3, 0,
        GIM_CheckConstantInt8, /*MI*/0, /*Op*/4, 0,
        // MIs[0] offset
        GIM_CheckIsImm, /*MI*/0, /*Op*/6,
        // MIs[0] auxiliary
        GIM_CheckIsImm, /*MI*/0, /*Op*/7,
        // MIs[0] Operand 8
        GIM_CheckLiteralInt, /*MI*/0, /*Op*/8, GIMT_Encode8(0),
        GIM_CheckComplexPattern, /*MI*/0, /*Op*/5, /*Renderer*/GIMT_Encode2(0), GIMT_Encode2(GICP_gi_buf_soffset),
        // (SIbuffer_atomic_xor:{ *:[i32] } i32:{ *:[i32] }:$vdata_in, v4i32:{ *:[v4i32] }:$rsrc, 0:{ *:[i32] }, 0:{ *:[i32] }, (BUFSOffset:{ *:[i32] } i32:{ *:[i32] }:$soffset), (timm:{ *:[i32] }):$offset, (timm:{ *:[i32] }):$auxiliary, 0:{ *:[i1] })<<P:Predicate_SIbuffer_atomic_xor_noret>>  =>  (BUFFER_ATOMIC_XOR_VBUFFER_OFFSET anonymous_15037:{ *:[i32] }:$vdata_in, SReg_128:{ *:[v4i32] }:$rsrc, SCSrc_b32:{ *:[i32] }:$soffset, (timm:{ *:[i32] }):$offset, (extract_cpol:{ *:[i32] } ?:{ *:[i32] }:$auxiliary))
        GIR_BuildMI, /*InsnID*/0, /*Opcode*/GIMT_Encode2(AMDGPU::BUFFER_ATOMIC_XOR_VBUFFER_OFFSET),
        GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/1, // vdata_in
        GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/2, // rsrc
        GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/0, // soffset
        GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/6, // offset
        GIR_CustomOperandRenderer, /*InsnID*/0, /*OldInsnID*/0, /*OpIdx*/7, /*OperandRenderer*/GIMT_Encode2(GICR_renderExtractCPol), // auxiliary
        GIR_MergeMemOperands, /*InsnID*/0, /*NumInsns*/1, /*MergeInsnID's*/0,
        GIR_ConstrainSelectedInstOperands, /*InsnID*/0,
        GIR_EraseFromParent, /*InsnID*/0,
        // GIR_Coverage, 4885,
        GIR_Done,
      // Label 6359: @466128
      GIM_Try, /*On fail goto*//*Label 6360*/ GIMT_Encode4(466213), // Rule ID 4873 //
        GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasUnrestrictedSOffset),
        GIM_CheckRegBankForClass, /*MI*/0, /*Op*/0, /*RC*/GIMT_Encode2(AMDGPU::AV_32RegClassID),
        GIM_CheckConstantInt8, /*MI*/0, /*Op*/3, 0,
        GIM_CheckConstantInt8, /*MI*/0, /*Op*/4, 0,
        // MIs[0] offset
        GIM_CheckIsImm, /*MI*/0, /*Op*/6,
        // MIs[0] auxiliary
        GIM_CheckIsImm, /*MI*/0, /*Op*/7,
        // MIs[0] Operand 8
        GIM_CheckLiteralInt, /*MI*/0, /*Op*/8, GIMT_Encode8(0),
        GIM_CheckComplexPattern, /*MI*/0, /*Op*/5, /*Renderer*/GIMT_Encode2(0), GIMT_Encode2(GICP_gi_buf_soffset),
        // (SIbuffer_atomic_xor:{ *:[i32] } i32:{ *:[i32] }:$vdata_in, v4i32:{ *:[v4i32] }:$rsrc, 0:{ *:[i32] }, 0:{ *:[i32] }, (BUFSOffset:{ *:[i32] } i32:{ *:[i32] }:$soffset), (timm:{ *:[i32] }):$offset, (timm:{ *:[i32] }):$auxiliary, 0:{ *:[i1] })  =>  (BUFFER_ATOMIC_XOR_OFFSET_RTN:{ *:[i32] } anonymous_15037:{ *:[i32] }:$vdata_in, SReg_128:{ *:[v4i32] }:$rsrc, SCSrc_b32:{ *:[i32] }:$soffset, (timm:{ *:[i32] }):$offset, (extract_cpol_set_glc:{ *:[i32] } ?:{ *:[i32] }:$auxiliary))
        GIR_BuildMI, /*InsnID*/0, /*Opcode*/GIMT_Encode2(AMDGPU::BUFFER_ATOMIC_XOR_OFFSET_RTN),
        GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/0, // DstI[vdata]
        GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/1, // vdata_in
        GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/2, // rsrc
        GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/0, // soffset
        GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/6, // offset
        GIR_CustomOperandRenderer, /*InsnID*/0, /*OldInsnID*/0, /*OpIdx*/7, /*OperandRenderer*/GIMT_Encode2(GICR_renderExtractCpolSetGLC), // auxiliary
        GIR_MergeMemOperands, /*InsnID*/0, /*NumInsns*/1, /*MergeInsnID's*/0,
        GIR_ConstrainSelectedInstOperands, /*InsnID*/0,
        GIR_EraseFromParent, /*InsnID*/0,
        // GIR_Coverage, 4873,
        GIR_Done,
      // Label 6360: @466213
      GIM_Try, /*On fail goto*//*Label 6361*/ GIMT_Encode4(466295), // Rule ID 4881 //
        GIM_CheckRegBankForClass, /*MI*/0, /*Op*/0, /*RC*/GIMT_Encode2(AMDGPU::AV_32RegClassID),
        GIM_CheckConstantInt8, /*MI*/0, /*Op*/3, 0,
        GIM_CheckConstantInt8, /*MI*/0, /*Op*/4, 0,
        // MIs[0] offset
        GIM_CheckIsImm, /*MI*/0, /*Op*/6,
        // MIs[0] auxiliary
        GIM_CheckIsImm, /*MI*/0, /*Op*/7,
        // MIs[0] Operand 8
        GIM_CheckLiteralInt, /*MI*/0, /*Op*/8, GIMT_Encode8(0),
        GIM_CheckComplexPattern, /*MI*/0, /*Op*/5, /*Renderer*/GIMT_Encode2(0), GIMT_Encode2(GICP_gi_buf_soffset),
        // (SIbuffer_atomic_xor:{ *:[i32] } i32:{ *:[i32] }:$vdata_in, v4i32:{ *:[v4i32] }:$rsrc, 0:{ *:[i32] }, 0:{ *:[i32] }, (BUFSOffset:{ *:[i32] } i32:{ *:[i32] }:$soffset), (timm:{ *:[i32] }):$offset, (timm:{ *:[i32] }):$auxiliary, 0:{ *:[i1] })  =>  (BUFFER_ATOMIC_XOR_VBUFFER_OFFSET_RTN:{ *:[i32] } anonymous_15037:{ *:[i32] }:$vdata_in, SReg_128:{ *:[v4i32] }:$rsrc, SCSrc_b32:{ *:[i32] }:$soffset, (timm:{ *:[i32] }):$offset, (extract_cpol_set_glc:{ *:[i32] } ?:{ *:[i32] }:$auxiliary))
        GIR_BuildMI, /*InsnID*/0, /*Opcode*/GIMT_Encode2(AMDGPU::BUFFER_ATOMIC_XOR_VBUFFER_OFFSET_RTN),
        GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/0, // DstI[vdata]
        GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/1, // vdata_in
        GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/2, // rsrc
        GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/0, // soffset
        GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/6, // offset
        GIR_CustomOperandRenderer, /*InsnID*/0, /*OldInsnID*/0, /*OpIdx*/7, /*OperandRenderer*/GIMT_Encode2(GICR_renderExtractCpolSetGLC), // auxiliary
        GIR_MergeMemOperands, /*InsnID*/0, /*NumInsns*/1, /*MergeInsnID's*/0,
        GIR_ConstrainSelectedInstOperands, /*InsnID*/0,
        GIR_EraseFromParent, /*InsnID*/0,
        // GIR_Coverage, 4881,
        GIR_Done,
      // Label 6361: @466295
      GIM_Try, /*On fail goto*//*Label 6362*/ GIMT_Encode4(466373), // Rule ID 4879 //
        GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasUnrestrictedSOffset),
        GIM_CheckHasNoUse, /*MI*/0,
        GIM_CheckConstantInt8, /*MI*/0, /*Op*/3, 0,
        // MIs[0] offset
        GIM_CheckIsImm, /*MI*/0, /*Op*/6,
        // MIs[0] auxiliary
        GIM_CheckIsImm, /*MI*/0, /*Op*/7,
        // MIs[0] Operand 8
        GIM_CheckLiteralInt, /*MI*/0, /*Op*/8, GIMT_Encode8(0),
        GIM_CheckComplexPattern, /*MI*/0, /*Op*/5, /*Renderer*/GIMT_Encode2(0), GIMT_Encode2(GICP_gi_buf_soffset),
        // (SIbuffer_atomic_xor:{ *:[i32] } i32:{ *:[i32] }:$vdata_in, v4i32:{ *:[v4i32] }:$rsrc, 0:{ *:[i32] }, i32:{ *:[i32] }:$voffset, (BUFSOffset:{ *:[i32] } i32:{ *:[i32] }:$soffset), (timm:{ *:[i32] }):$offset, (timm:{ *:[i32] }):$auxiliary, 0:{ *:[i1] })<<P:Predicate_SIbuffer_atomic_xor_noret>>  =>  (BUFFER_ATOMIC_XOR_OFFEN anonymous_15037:{ *:[i32] }:$vdata_in, VGPR_32:{ *:[i32] }:$voffset, SReg_128:{ *:[v4i32] }:$rsrc, SCSrc_b32:{ *:[i32] }:$soffset, (timm:{ *:[i32] }):$offset, (extract_cpol:{ *:[i32] } ?:{ *:[i32] }:$auxiliary))
        GIR_BuildMI, /*InsnID*/0, /*Opcode*/GIMT_Encode2(AMDGPU::BUFFER_ATOMIC_XOR_OFFEN),
        GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/1, // vdata_in
        GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/4, // voffset
        GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/2, // rsrc
        GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/0, // soffset
        GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/6, // offset
        GIR_CustomOperandRenderer, /*InsnID*/0, /*OldInsnID*/0, /*OpIdx*/7, /*OperandRenderer*/GIMT_Encode2(GICR_renderExtractCPol), // auxiliary
        GIR_MergeMemOperands, /*InsnID*/0, /*NumInsns*/1, /*MergeInsnID's*/0,
        GIR_ConstrainSelectedInstOperands, /*InsnID*/0,
        GIR_EraseFromParent, /*InsnID*/0,
        // GIR_Coverage, 4879,
        GIR_Done,
      // Label 6362: @466373
      GIM_Try, /*On fail goto*//*Label 6363*/ GIMT_Encode4(466448), // Rule ID 4887 //
        GIM_CheckHasNoUse, /*MI*/0,
        GIM_CheckConstantInt8, /*MI*/0, /*Op*/3, 0,
        // MIs[0] offset
        GIM_CheckIsImm, /*MI*/0, /*Op*/6,
        // MIs[0] auxiliary
        GIM_CheckIsImm, /*MI*/0, /*Op*/7,
        // MIs[0] Operand 8
        GIM_CheckLiteralInt, /*MI*/0, /*Op*/8, GIMT_Encode8(0),
        GIM_CheckComplexPattern, /*MI*/0, /*Op*/5, /*Renderer*/GIMT_Encode2(0), GIMT_Encode2(GICP_gi_buf_soffset),
        // (SIbuffer_atomic_xor:{ *:[i32] } i32:{ *:[i32] }:$vdata_in, v4i32:{ *:[v4i32] }:$rsrc, 0:{ *:[i32] }, i32:{ *:[i32] }:$voffset, (BUFSOffset:{ *:[i32] } i32:{ *:[i32] }:$soffset), (timm:{ *:[i32] }):$offset, (timm:{ *:[i32] }):$auxiliary, 0:{ *:[i1] })<<P:Predicate_SIbuffer_atomic_xor_noret>>  =>  (BUFFER_ATOMIC_XOR_VBUFFER_OFFEN anonymous_15037:{ *:[i32] }:$vdata_in, VGPR_32:{ *:[i32] }:$voffset, SReg_128:{ *:[v4i32] }:$rsrc, SCSrc_b32:{ *:[i32] }:$soffset, (timm:{ *:[i32] }):$offset, (extract_cpol:{ *:[i32] } ?:{ *:[i32] }:$auxiliary))
        GIR_BuildMI, /*InsnID*/0, /*Opcode*/GIMT_Encode2(AMDGPU::BUFFER_ATOMIC_XOR_VBUFFER_OFFEN),
        GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/1, // vdata_in
        GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/4, // voffset
        GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/2, // rsrc
        GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/0, // soffset
        GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/6, // offset
        GIR_CustomOperandRenderer, /*InsnID*/0, /*OldInsnID*/0, /*OpIdx*/7, /*OperandRenderer*/GIMT_Encode2(GICR_renderExtractCPol), // auxiliary
        GIR_MergeMemOperands, /*InsnID*/0, /*NumInsns*/1, /*MergeInsnID's*/0,
        GIR_ConstrainSelectedInstOperands, /*InsnID*/0,
        GIR_EraseFromParent, /*InsnID*/0,
        // GIR_Coverage, 4887,
        GIR_Done,
      // Label 6363: @466448
      GIM_Try, /*On fail goto*//*Label 6364*/ GIMT_Encode4(466533), // Rule ID 4875 //
        GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasUnrestrictedSOffset),
        GIM_CheckRegBankForClass, /*MI*/0, /*Op*/0, /*RC*/GIMT_Encode2(AMDGPU::AV_32RegClassID),
        GIM_CheckConstantInt8, /*MI*/0, /*Op*/3, 0,
        // MIs[0] offset
        GIM_CheckIsImm, /*MI*/0, /*Op*/6,
        // MIs[0] auxiliary
        GIM_CheckIsImm, /*MI*/0, /*Op*/7,
        // MIs[0] Operand 8
        GIM_CheckLiteralInt, /*MI*/0, /*Op*/8, GIMT_Encode8(0),
        GIM_CheckComplexPattern, /*MI*/0, /*Op*/5, /*Renderer*/GIMT_Encode2(0), GIMT_Encode2(GICP_gi_buf_soffset),
        // (SIbuffer_atomic_xor:{ *:[i32] } i32:{ *:[i32] }:$vdata_in, v4i32:{ *:[v4i32] }:$rsrc, 0:{ *:[i32] }, i32:{ *:[i32] }:$voffset, (BUFSOffset:{ *:[i32] } i32:{ *:[i32] }:$soffset), (timm:{ *:[i32] }):$offset, (timm:{ *:[i32] }):$auxiliary, 0:{ *:[i1] })  =>  (BUFFER_ATOMIC_XOR_OFFEN_RTN:{ *:[i32] } anonymous_15037:{ *:[i32] }:$vdata_in, VGPR_32:{ *:[i32] }:$voffset, SReg_128:{ *:[v4i32] }:$rsrc, SCSrc_b32:{ *:[i32] }:$soffset, (timm:{ *:[i32] }):$offset, (extract_cpol_set_glc:{ *:[i32] } ?:{ *:[i32] }:$auxiliary))
        GIR_BuildMI, /*InsnID*/0, /*Opcode*/GIMT_Encode2(AMDGPU::BUFFER_ATOMIC_XOR_OFFEN_RTN),
        GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/0, // DstI[vdata]
        GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/1, // vdata_in
        GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/4, // voffset
        GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/2, // rsrc
        GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/0, // soffset
        GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/6, // offset
        GIR_CustomOperandRenderer, /*InsnID*/0, /*OldInsnID*/0, /*OpIdx*/7, /*OperandRenderer*/GIMT_Encode2(GICR_renderExtractCpolSetGLC), // auxiliary
        GIR_MergeMemOperands, /*InsnID*/0, /*NumInsns*/1, /*MergeInsnID's*/0,
        GIR_ConstrainSelectedInstOperands, /*InsnID*/0,
        GIR_EraseFromParent, /*InsnID*/0,
        // GIR_Coverage, 4875,
        GIR_Done,
      // Label 6364: @466533
      GIM_Try, /*On fail goto*//*Label 6365*/ GIMT_Encode4(466615), // Rule ID 4883 //
        GIM_CheckRegBankForClass, /*MI*/0, /*Op*/0, /*RC*/GIMT_Encode2(AMDGPU::AV_32RegClassID),
        GIM_CheckConstantInt8, /*MI*/0, /*Op*/3, 0,
        // MIs[0] offset
        GIM_CheckIsImm, /*MI*/0, /*Op*/6,
        // MIs[0] auxiliary
        GIM_CheckIsImm, /*MI*/0, /*Op*/7,
        // MIs[0] Operand 8
        GIM_CheckLiteralInt, /*MI*/0, /*Op*/8, GIMT_Encode8(0),
        GIM_CheckComplexPattern, /*MI*/0, /*Op*/5, /*Renderer*/GIMT_Encode2(0), GIMT_Encode2(GICP_gi_buf_soffset),
        // (SIbuffer_atomic_xor:{ *:[i32] } i32:{ *:[i32] }:$vdata_in, v4i32:{ *:[v4i32] }:$rsrc, 0:{ *:[i32] }, i32:{ *:[i32] }:$voffset, (BUFSOffset:{ *:[i32] } i32:{ *:[i32] }:$soffset), (timm:{ *:[i32] }):$offset, (timm:{ *:[i32] }):$auxiliary, 0:{ *:[i1] })  =>  (BUFFER_ATOMIC_XOR_VBUFFER_OFFEN_RTN:{ *:[i32] } anonymous_15037:{ *:[i32] }:$vdata_in, VGPR_32:{ *:[i32] }:$voffset, SReg_128:{ *:[v4i32] }:$rsrc, SCSrc_b32:{ *:[i32] }:$soffset, (timm:{ *:[i32] }):$offset, (extract_cpol_set_glc:{ *:[i32] } ?:{ *:[i32] }:$auxiliary))
        GIR_BuildMI, /*InsnID*/0, /*Opcode*/GIMT_Encode2(AMDGPU::BUFFER_ATOMIC_XOR_VBUFFER_OFFEN_RTN),
        GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/0, // DstI[vdata]
        GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/1, // vdata_in
        GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/4, // voffset
        GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/2, // rsrc
        GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/0, // soffset
        GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/6, // offset
        GIR_CustomOperandRenderer, /*InsnID*/0, /*OldInsnID*/0, /*OpIdx*/7, /*OperandRenderer*/GIMT_Encode2(GICR_renderExtractCpolSetGLC), // auxiliary
        GIR_MergeMemOperands, /*InsnID*/0, /*NumInsns*/1, /*MergeInsnID's*/0,
        GIR_ConstrainSelectedInstOperands, /*InsnID*/0,
        GIR_EraseFromParent, /*InsnID*/0,
        // GIR_Coverage, 4883,
        GIR_Done,
      // Label 6365: @466615
      GIM_Try, /*On fail goto*//*Label 6366*/ GIMT_Encode4(466685), // Rule ID 4878 //
        GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasUnrestrictedSOffset),
        GIM_CheckHasNoUse, /*MI*/0,
        GIM_CheckConstantInt8, /*MI*/0, /*Op*/4, 0,
        // MIs[0] offset
        GIM_CheckIsImm, /*MI*/0, /*Op*/6,
        // MIs[0] auxiliary
        GIM_CheckIsImm, /*MI*/0, /*Op*/7,
        // MIs[0] Operand 8
        GIM_CheckIsImm, /*MI*/0, /*Op*/8,
        GIM_CheckComplexPattern, /*MI*/0, /*Op*/5, /*Renderer*/GIMT_Encode2(0), GIMT_Encode2(GICP_gi_buf_soffset),
        // (SIbuffer_atomic_xor:{ *:[i32] } i32:{ *:[i32] }:$vdata_in, v4i32:{ *:[v4i32] }:$rsrc, i32:{ *:[i32] }:$vindex, 0:{ *:[i32] }, (BUFSOffset:{ *:[i32] } i32:{ *:[i32] }:$soffset), (timm:{ *:[i32] }):$offset, (timm:{ *:[i32] }):$auxiliary, (timm:{ *:[i1] }))<<P:Predicate_SIbuffer_atomic_xor_noret>>  =>  (BUFFER_ATOMIC_XOR_IDXEN anonymous_15037:{ *:[i32] }:$vdata_in, VGPR_32:{ *:[i32] }:$vindex, SReg_128:{ *:[v4i32] }:$rsrc, SCSrc_b32:{ *:[i32] }:$soffset, (timm:{ *:[i32] }):$offset, (extract_cpol:{ *:[i32] } ?:{ *:[i32] }:$auxiliary))
        GIR_BuildMI, /*InsnID*/0, /*Opcode*/GIMT_Encode2(AMDGPU::BUFFER_ATOMIC_XOR_IDXEN),
        GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/1, // vdata_in
        GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/3, // vindex
        GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/2, // rsrc
        GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/0, // soffset
        GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/6, // offset
        GIR_CustomOperandRenderer, /*InsnID*/0, /*OldInsnID*/0, /*OpIdx*/7, /*OperandRenderer*/GIMT_Encode2(GICR_renderExtractCPol), // auxiliary
        GIR_MergeMemOperands, /*InsnID*/0, /*NumInsns*/1, /*MergeInsnID's*/0,
        GIR_ConstrainSelectedInstOperands, /*InsnID*/0,
        GIR_EraseFromParent, /*InsnID*/0,
        // GIR_Coverage, 4878,
        GIR_Done,
      // Label 6366: @466685
      GIM_Try, /*On fail goto*//*Label 6367*/ GIMT_Encode4(466752), // Rule ID 4886 //
        GIM_CheckHasNoUse, /*MI*/0,
        GIM_CheckConstantInt8, /*MI*/0, /*Op*/4, 0,
        // MIs[0] offset
        GIM_CheckIsImm, /*MI*/0, /*Op*/6,
        // MIs[0] auxiliary
        GIM_CheckIsImm, /*MI*/0, /*Op*/7,
        // MIs[0] Operand 8
        GIM_CheckIsImm, /*MI*/0, /*Op*/8,
        GIM_CheckComplexPattern, /*MI*/0, /*Op*/5, /*Renderer*/GIMT_Encode2(0), GIMT_Encode2(GICP_gi_buf_soffset),
        // (SIbuffer_atomic_xor:{ *:[i32] } i32:{ *:[i32] }:$vdata_in, v4i32:{ *:[v4i32] }:$rsrc, i32:{ *:[i32] }:$vindex, 0:{ *:[i32] }, (BUFSOffset:{ *:[i32] } i32:{ *:[i32] }:$soffset), (timm:{ *:[i32] }):$offset, (timm:{ *:[i32] }):$auxiliary, (timm:{ *:[i1] }))<<P:Predicate_SIbuffer_atomic_xor_noret>>  =>  (BUFFER_ATOMIC_XOR_VBUFFER_IDXEN anonymous_15037:{ *:[i32] }:$vdata_in, VGPR_32:{ *:[i32] }:$vindex, SReg_128:{ *:[v4i32] }:$rsrc, SCSrc_b32:{ *:[i32] }:$soffset, (timm:{ *:[i32] }):$offset, (extract_cpol:{ *:[i32] } ?:{ *:[i32] }:$auxiliary))
        GIR_BuildMI, /*InsnID*/0, /*Opcode*/GIMT_Encode2(AMDGPU::BUFFER_ATOMIC_XOR_VBUFFER_IDXEN),
        GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/1, // vdata_in
        GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/3, // vindex
        GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/2, // rsrc
        GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/0, // soffset
        GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/6, // offset
        GIR_CustomOperandRenderer, /*InsnID*/0, /*OldInsnID*/0, /*OpIdx*/7, /*OperandRenderer*/GIMT_Encode2(GICR_renderExtractCPol), // auxiliary
        GIR_MergeMemOperands, /*InsnID*/0, /*NumInsns*/1, /*MergeInsnID's*/0,
        GIR_ConstrainSelectedInstOperands, /*InsnID*/0,
        GIR_EraseFromParent, /*InsnID*/0,
        // GIR_Coverage, 4886,
        GIR_Done,
      // Label 6367: @466752
      GIM_Try, /*On fail goto*//*Label 6368*/ GIMT_Encode4(466829), // Rule ID 4874 //
        GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasUnrestrictedSOffset),
        GIM_CheckRegBankForClass, /*MI*/0, /*Op*/0, /*RC*/GIMT_Encode2(AMDGPU::AV_32RegClassID),
        GIM_CheckConstantInt8, /*MI*/0, /*Op*/4, 0,
        // MIs[0] offset
        GIM_CheckIsImm, /*MI*/0, /*Op*/6,
        // MIs[0] auxiliary
        GIM_CheckIsImm, /*MI*/0, /*Op*/7,
        // MIs[0] Operand 8
        GIM_CheckIsImm, /*MI*/0, /*Op*/8,
        GIM_CheckComplexPattern, /*MI*/0, /*Op*/5, /*Renderer*/GIMT_Encode2(0), GIMT_Encode2(GICP_gi_buf_soffset),
        // (SIbuffer_atomic_xor:{ *:[i32] } i32:{ *:[i32] }:$vdata_in, v4i32:{ *:[v4i32] }:$rsrc, i32:{ *:[i32] }:$vindex, 0:{ *:[i32] }, (BUFSOffset:{ *:[i32] } i32:{ *:[i32] }:$soffset), (timm:{ *:[i32] }):$offset, (timm:{ *:[i32] }):$auxiliary, (timm:{ *:[i1] }))  =>  (BUFFER_ATOMIC_XOR_IDXEN_RTN:{ *:[i32] } anonymous_15037:{ *:[i32] }:$vdata_in, VGPR_32:{ *:[i32] }:$vindex, SReg_128:{ *:[v4i32] }:$rsrc, SCSrc_b32:{ *:[i32] }:$soffset, (timm:{ *:[i32] }):$offset, (extract_cpol_set_glc:{ *:[i32] } ?:{ *:[i32] }:$auxiliary))
        GIR_BuildMI, /*InsnID*/0, /*Opcode*/GIMT_Encode2(AMDGPU::BUFFER_ATOMIC_XOR_IDXEN_RTN),
        GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/0, // DstI[vdata]
        GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/1, // vdata_in
        GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/3, // vindex
        GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/2, // rsrc
        GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/0, // soffset
        GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/6, // offset
        GIR_CustomOperandRenderer, /*InsnID*/0, /*OldInsnID*/0, /*OpIdx*/7, /*OperandRenderer*/GIMT_Encode2(GICR_renderExtractCpolSetGLC), // auxiliary
        GIR_MergeMemOperands, /*InsnID*/0, /*NumInsns*/1, /*MergeInsnID's*/0,
        GIR_ConstrainSelectedInstOperands, /*InsnID*/0,
        GIR_EraseFromParent, /*InsnID*/0,
        // GIR_Coverage, 4874,
        GIR_Done,
      // Label 6368: @466829
      GIM_Try, /*On fail goto*//*Label 6369*/ GIMT_Encode4(466903), // Rule ID 4882 //
        GIM_CheckRegBankForClass, /*MI*/0, /*Op*/0, /*RC*/GIMT_Encode2(AMDGPU::AV_32RegClassID),
        GIM_CheckConstantInt8, /*MI*/0, /*Op*/4, 0,
        // MIs[0] offset
        GIM_CheckIsImm, /*MI*/0, /*Op*/6,
        // MIs[0] auxiliary
        GIM_CheckIsImm, /*MI*/0, /*Op*/7,
        // MIs[0] Operand 8
        GIM_CheckIsImm, /*MI*/0, /*Op*/8,
        GIM_CheckComplexPattern, /*MI*/0, /*Op*/5, /*Renderer*/GIMT_Encode2(0), GIMT_Encode2(GICP_gi_buf_soffset),
        // (SIbuffer_atomic_xor:{ *:[i32] } i32:{ *:[i32] }:$vdata_in, v4i32:{ *:[v4i32] }:$rsrc, i32:{ *:[i32] }:$vindex, 0:{ *:[i32] }, (BUFSOffset:{ *:[i32] } i32:{ *:[i32] }:$soffset), (timm:{ *:[i32] }):$offset, (timm:{ *:[i32] }):$auxiliary, (timm:{ *:[i1] }))  =>  (BUFFER_ATOMIC_XOR_VBUFFER_IDXEN_RTN:{ *:[i32] } anonymous_15037:{ *:[i32] }:$vdata_in, VGPR_32:{ *:[i32] }:$vindex, SReg_128:{ *:[v4i32] }:$rsrc, SCSrc_b32:{ *:[i32] }:$soffset, (timm:{ *:[i32] }):$offset, (extract_cpol_set_glc:{ *:[i32] } ?:{ *:[i32] }:$auxiliary))
        GIR_BuildMI, /*InsnID*/0, /*Opcode*/GIMT_Encode2(AMDGPU::BUFFER_ATOMIC_XOR_VBUFFER_IDXEN_RTN),
        GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/0, // DstI[vdata]
        GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/1, // vdata_in
        GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/3, // vindex
        GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/2, // rsrc
        GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/0, // soffset
        GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/6, // offset
        GIR_CustomOperandRenderer, /*InsnID*/0, /*OldInsnID*/0, /*OpIdx*/7, /*OperandRenderer*/GIMT_Encode2(GICR_renderExtractCpolSetGLC), // auxiliary
        GIR_MergeMemOperands, /*InsnID*/0, /*NumInsns*/1, /*MergeInsnID's*/0,
        GIR_ConstrainSelectedInstOperands, /*InsnID*/0,
        GIR_EraseFromParent, /*InsnID*/0,
        // GIR_Coverage, 4882,
        GIR_Done,
      // Label 6369: @466903
      GIM_Try, /*On fail goto*//*Label 6370*/ GIMT_Encode4(467009), // Rule ID 4880 //
        GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasUnrestrictedSOffset),
        GIM_CheckHasNoUse, /*MI*/0,
        // MIs[0] offset
        GIM_CheckIsImm, /*MI*/0, /*Op*/6,
        // MIs[0] auxiliary
        GIM_CheckIsImm, /*MI*/0, /*Op*/7,
        // MIs[0] Operand 8
        GIM_CheckIsImm, /*MI*/0, /*Op*/8,
        GIM_CheckComplexPattern, /*MI*/0, /*Op*/5, /*Renderer*/GIMT_Encode2(0), GIMT_Encode2(GICP_gi_buf_soffset),
        // (SIbuffer_atomic_xor:{ *:[i32] } i32:{ *:[i32] }:$vdata_in, v4i32:{ *:[v4i32] }:$rsrc, i32:{ *:[i32] }:$vindex, i32:{ *:[i32] }:$voffset, (BUFSOffset:{ *:[i32] } i32:{ *:[i32] }:$soffset), (timm:{ *:[i32] }):$offset, (timm:{ *:[i32] }):$auxiliary, (timm:{ *:[i1] }))<<P:Predicate_SIbuffer_atomic_xor_noret>>  =>  (BUFFER_ATOMIC_XOR_BOTHEN anonymous_15037:{ *:[i32] }:$vdata_in, (REG_SEQUENCE:{ *:[i64] } VReg_64:{ *:[i32] }, VGPR_32:{ *:[i32] }:$vindex, sub0:{ *:[i32] }, VGPR_32:{ *:[i32] }:$voffset, sub1:{ *:[i32] }), SReg_128:{ *:[v4i32] }:$rsrc, SCSrc_b32:{ *:[i32] }:$soffset, (timm:{ *:[i32] }):$offset, (extract_cpol:{ *:[i32] } ?:{ *:[i32] }:$auxiliary))
        GIR_MakeTempReg, /*TempRegID*/0, /*TypeID*/GILLT_s64,
        GIR_BuildMI, /*InsnID*/1, /*Opcode*/GIMT_Encode2(TargetOpcode::REG_SEQUENCE),
        GIR_AddTempRegister, /*InsnID*/1, /*TempRegID*/0, /*TempRegFlags*/GIMT_Encode2(RegState::Define),
        GIR_Copy, /*NewInsnID*/1, /*OldInsnID*/0, /*OpIdx*/3, // vindex
        GIR_AddImm8, /*InsnID*/1, /*SubRegIndex*/3,
        GIR_Copy, /*NewInsnID*/1, /*OldInsnID*/0, /*OpIdx*/4, // voffset
        GIR_AddImm8, /*InsnID*/1, /*SubRegIndex*/11,
        GIR_ConstrainOperandRC, /*InsnID*/1, /*Op*/0, GIMT_Encode2(AMDGPU::VReg_64RegClassID),
        GIR_ConstrainOperandRC, /*InsnID*/1, /*Op*/1, GIMT_Encode2(AMDGPU::VGPR_32RegClassID),
        GIR_ConstrainOperandRC, /*InsnID*/1, /*Op*/3, GIMT_Encode2(AMDGPU::VGPR_32RegClassID),
        GIR_BuildMI, /*InsnID*/0, /*Opcode*/GIMT_Encode2(AMDGPU::BUFFER_ATOMIC_XOR_BOTHEN),
        GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/1, // vdata_in
        GIR_AddSimpleTempRegister, /*InsnID*/0, /*TempRegID*/0,
        GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/2, // rsrc
        GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/0, // soffset
        GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/6, // offset
        GIR_CustomOperandRenderer, /*InsnID*/0, /*OldInsnID*/0, /*OpIdx*/7, /*OperandRenderer*/GIMT_Encode2(GICR_renderExtractCPol), // auxiliary
        GIR_MergeMemOperands, /*InsnID*/0, /*NumInsns*/1, /*MergeInsnID's*/0,
        GIR_ConstrainSelectedInstOperands, /*InsnID*/0,
        GIR_EraseFromParent, /*InsnID*/0,
        // GIR_Coverage, 4880,
        GIR_Done,
      // Label 6370: @467009
      GIM_Try, /*On fail goto*//*Label 6371*/ GIMT_Encode4(467112), // Rule ID 4888 //
        GIM_CheckHasNoUse, /*MI*/0,
        // MIs[0] offset
        GIM_CheckIsImm, /*MI*/0, /*Op*/6,
        // MIs[0] auxiliary
        GIM_CheckIsImm, /*MI*/0, /*Op*/7,
        // MIs[0] Operand 8
        GIM_CheckIsImm, /*MI*/0, /*Op*/8,
        GIM_CheckComplexPattern, /*MI*/0, /*Op*/5, /*Renderer*/GIMT_Encode2(0), GIMT_Encode2(GICP_gi_buf_soffset),
        // (SIbuffer_atomic_xor:{ *:[i32] } i32:{ *:[i32] }:$vdata_in, v4i32:{ *:[v4i32] }:$rsrc, i32:{ *:[i32] }:$vindex, i32:{ *:[i32] }:$voffset, (BUFSOffset:{ *:[i32] } i32:{ *:[i32] }:$soffset), (timm:{ *:[i32] }):$offset, (timm:{ *:[i32] }):$auxiliary, (timm:{ *:[i1] }))<<P:Predicate_SIbuffer_atomic_xor_noret>>  =>  (BUFFER_ATOMIC_XOR_VBUFFER_BOTHEN anonymous_15037:{ *:[i32] }:$vdata_in, (REG_SEQUENCE:{ *:[i64] } VReg_64:{ *:[i32] }, VGPR_32:{ *:[i32] }:$vindex, sub0:{ *:[i32] }, VGPR_32:{ *:[i32] }:$voffset, sub1:{ *:[i32] }), SReg_128:{ *:[v4i32] }:$rsrc, SCSrc_b32:{ *:[i32] }:$soffset, (timm:{ *:[i32] }):$offset, (extract_cpol:{ *:[i32] } ?:{ *:[i32] }:$auxiliary))
        GIR_MakeTempReg, /*TempRegID*/0, /*TypeID*/GILLT_s64,
        GIR_BuildMI, /*InsnID*/1, /*Opcode*/GIMT_Encode2(TargetOpcode::REG_SEQUENCE),
        GIR_AddTempRegister, /*InsnID*/1, /*TempRegID*/0, /*TempRegFlags*/GIMT_Encode2(RegState::Define),
        GIR_Copy, /*NewInsnID*/1, /*OldInsnID*/0, /*OpIdx*/3, // vindex
        GIR_AddImm8, /*InsnID*/1, /*SubRegIndex*/3,
        GIR_Copy, /*NewInsnID*/1, /*OldInsnID*/0, /*OpIdx*/4, // voffset
        GIR_AddImm8, /*InsnID*/1, /*SubRegIndex*/11,
        GIR_ConstrainOperandRC, /*InsnID*/1, /*Op*/0, GIMT_Encode2(AMDGPU::VReg_64RegClassID),
        GIR_ConstrainOperandRC, /*InsnID*/1, /*Op*/1, GIMT_Encode2(AMDGPU::VGPR_32RegClassID),
        GIR_ConstrainOperandRC, /*InsnID*/1, /*Op*/3, GIMT_Encode2(AMDGPU::VGPR_32RegClassID),
        GIR_BuildMI, /*InsnID*/0, /*Opcode*/GIMT_Encode2(AMDGPU::BUFFER_ATOMIC_XOR_VBUFFER_BOTHEN),
        GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/1, // vdata_in
        GIR_AddSimpleTempRegister, /*InsnID*/0, /*TempRegID*/0,
        GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/2, // rsrc
        GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/0, // soffset
        GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/6, // offset
        GIR_CustomOperandRenderer, /*InsnID*/0, /*OldInsnID*/0, /*OpIdx*/7, /*OperandRenderer*/GIMT_Encode2(GICR_renderExtractCPol), // auxiliary
        GIR_MergeMemOperands, /*InsnID*/0, /*NumInsns*/1, /*MergeInsnID's*/0,
        GIR_ConstrainSelectedInstOperands, /*InsnID*/0,
        GIR_EraseFromParent, /*InsnID*/0,
        // GIR_Coverage, 4888,
        GIR_Done,
      // Label 6371: @467112
      GIM_Try, /*On fail goto*//*Label 6372*/ GIMT_Encode4(467225), // Rule ID 4876 //
        GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasUnrestrictedSOffset),
        GIM_CheckRegBankForClass, /*MI*/0, /*Op*/0, /*RC*/GIMT_Encode2(AMDGPU::AV_32RegClassID),
        // MIs[0] offset
        GIM_CheckIsImm, /*MI*/0, /*Op*/6,
        // MIs[0] auxiliary
        GIM_CheckIsImm, /*MI*/0, /*Op*/7,
        // MIs[0] Operand 8
        GIM_CheckIsImm, /*MI*/0, /*Op*/8,
        GIM_CheckComplexPattern, /*MI*/0, /*Op*/5, /*Renderer*/GIMT_Encode2(0), GIMT_Encode2(GICP_gi_buf_soffset),
        // (SIbuffer_atomic_xor:{ *:[i32] } i32:{ *:[i32] }:$vdata_in, v4i32:{ *:[v4i32] }:$rsrc, i32:{ *:[i32] }:$vindex, i32:{ *:[i32] }:$voffset, (BUFSOffset:{ *:[i32] } i32:{ *:[i32] }:$soffset), (timm:{ *:[i32] }):$offset, (timm:{ *:[i32] }):$auxiliary, (timm:{ *:[i1] }))  =>  (BUFFER_ATOMIC_XOR_BOTHEN_RTN:{ *:[i32] } anonymous_15037:{ *:[i32] }:$vdata_in, (REG_SEQUENCE:{ *:[i64] } VReg_64:{ *:[i32] }, VGPR_32:{ *:[i32] }:$vindex, sub0:{ *:[i32] }, VGPR_32:{ *:[i32] }:$voffset, sub1:{ *:[i32] }), SReg_128:{ *:[v4i32] }:$rsrc, SCSrc_b32:{ *:[i32] }:$soffset, (timm:{ *:[i32] }):$offset, (extract_cpol_set_glc:{ *:[i32] } ?:{ *:[i32] }:$auxiliary))
        GIR_MakeTempReg, /*TempRegID*/0, /*TypeID*/GILLT_s64,
        GIR_BuildMI, /*InsnID*/1, /*Opcode*/GIMT_Encode2(TargetOpcode::REG_SEQUENCE),
        GIR_AddTempRegister, /*InsnID*/1, /*TempRegID*/0, /*TempRegFlags*/GIMT_Encode2(RegState::Define),
        GIR_Copy, /*NewInsnID*/1, /*OldInsnID*/0, /*OpIdx*/3, // vindex
        GIR_AddImm8, /*InsnID*/1, /*SubRegIndex*/3,
        GIR_Copy, /*NewInsnID*/1, /*OldInsnID*/0, /*OpIdx*/4, // voffset
        GIR_AddImm8, /*InsnID*/1, /*SubRegIndex*/11,
        GIR_ConstrainOperandRC, /*InsnID*/1, /*Op*/0, GIMT_Encode2(AMDGPU::VReg_64RegClassID),
        GIR_ConstrainOperandRC, /*InsnID*/1, /*Op*/1, GIMT_Encode2(AMDGPU::VGPR_32RegClassID),
        GIR_ConstrainOperandRC, /*InsnID*/1, /*Op*/3, GIMT_Encode2(AMDGPU::VGPR_32RegClassID),
        GIR_BuildMI, /*InsnID*/0, /*Opcode*/GIMT_Encode2(AMDGPU::BUFFER_ATOMIC_XOR_BOTHEN_RTN),
        GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/0, // DstI[vdata]
        GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/1, // vdata_in
        GIR_AddSimpleTempRegister, /*InsnID*/0, /*TempRegID*/0,
        GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/2, // rsrc
        GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/0, // soffset
        GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/6, // offset
        GIR_CustomOperandRenderer, /*InsnID*/0, /*OldInsnID*/0, /*OpIdx*/7, /*OperandRenderer*/GIMT_Encode2(GICR_renderExtractCpolSetGLC), // auxiliary
        GIR_MergeMemOperands, /*InsnID*/0, /*NumInsns*/1, /*MergeInsnID's*/0,
        GIR_ConstrainSelectedInstOperands, /*InsnID*/0,
        GIR_EraseFromParent, /*InsnID*/0,
        // GIR_Coverage, 4876,
        GIR_Done,
      // Label 6372: @467225
      GIM_Try, /*On fail goto*//*Label 6373*/ GIMT_Encode4(467335), // Rule ID 4884 //
        GIM_CheckRegBankForClass, /*MI*/0, /*Op*/0, /*RC*/GIMT_Encode2(AMDGPU::AV_32RegClassID),
        // MIs[0] offset
        GIM_CheckIsImm, /*MI*/0, /*Op*/6,
        // MIs[0] auxiliary
        GIM_CheckIsImm, /*MI*/0, /*Op*/7,
        // MIs[0] Operand 8
        GIM_CheckIsImm, /*MI*/0, /*Op*/8,
        GIM_CheckComplexPattern, /*MI*/0, /*Op*/5, /*Renderer*/GIMT_Encode2(0), GIMT_Encode2(GICP_gi_buf_soffset),
        // (SIbuffer_atomic_xor:{ *:[i32] } i32:{ *:[i32] }:$vdata_in, v4i32:{ *:[v4i32] }:$rsrc, i32:{ *:[i32] }:$vindex, i32:{ *:[i32] }:$voffset, (BUFSOffset:{ *:[i32] } i32:{ *:[i32] }:$soffset), (timm:{ *:[i32] }):$offset, (timm:{ *:[i32] }):$auxiliary, (timm:{ *:[i1] }))  =>  (BUFFER_ATOMIC_XOR_VBUFFER_BOTHEN_RTN:{ *:[i32] } anonymous_15037:{ *:[i32] }:$vdata_in, (REG_SEQUENCE:{ *:[i64] } VReg_64:{ *:[i32] }, VGPR_32:{ *:[i32] }:$vindex, sub0:{ *:[i32] }, VGPR_32:{ *:[i32] }:$voffset, sub1:{ *:[i32] }), SReg_128:{ *:[v4i32] }:$rsrc, SCSrc_b32:{ *:[i32] }:$soffset, (timm:{ *:[i32] }):$offset, (extract_cpol_set_glc:{ *:[i32] } ?:{ *:[i32] }:$auxiliary))
        GIR_MakeTempReg, /*TempRegID*/0, /*TypeID*/GILLT_s64,
        GIR_BuildMI, /*InsnID*/1, /*Opcode*/GIMT_Encode2(TargetOpcode::REG_SEQUENCE),
        GIR_AddTempRegister, /*InsnID*/1, /*TempRegID*/0, /*TempRegFlags*/GIMT_Encode2(RegState::Define),
        GIR_Copy, /*NewInsnID*/1, /*OldInsnID*/0, /*OpIdx*/3, // vindex
        GIR_AddImm8, /*InsnID*/1, /*SubRegIndex*/3,
        GIR_Copy, /*NewInsnID*/1, /*OldInsnID*/0, /*OpIdx*/4, // voffset
        GIR_AddImm8, /*InsnID*/1, /*SubRegIndex*/11,
        GIR_ConstrainOperandRC, /*InsnID*/1, /*Op*/0, GIMT_Encode2(AMDGPU::VReg_64RegClassID),
        GIR_ConstrainOperandRC, /*InsnID*/1, /*Op*/1, GIMT_Encode2(AMDGPU::VGPR_32RegClassID),
        GIR_ConstrainOperandRC, /*InsnID*/1, /*Op*/3, GIMT_Encode2(AMDGPU::VGPR_32RegClassID),
        GIR_BuildMI, /*InsnID*/0, /*Opcode*/GIMT_Encode2(AMDGPU::BUFFER_ATOMIC_XOR_VBUFFER_BOTHEN_RTN),
        GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/0, // DstI[vdata]
        GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/1, // vdata_in
        GIR_AddSimpleTempRegister, /*InsnID*/0, /*TempRegID*/0,
        GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/2, // rsrc
        GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/0, // soffset
        GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/6, // offset
        GIR_CustomOperandRenderer, /*InsnID*/0, /*OldInsnID*/0, /*OpIdx*/7, /*OperandRenderer*/GIMT_Encode2(GICR_renderExtractCpolSetGLC), // auxiliary
        GIR_MergeMemOperands, /*InsnID*/0, /*NumInsns*/1, /*MergeInsnID's*/0,
        GIR_ConstrainSelectedInstOperands, /*InsnID*/0,
        GIR_EraseFromParent, /*InsnID*/0,
        // GIR_Coverage, 4884,
        GIR_Done,
      // Label 6373: @467335
      GIM_Reject,
    // Label 6357: @467336
    GIM_Reject,
    // Label 6355: @467337
    GIM_Try, /*On fail goto*//*Label 6374*/ GIMT_Encode4(468723),
      GIM_CheckType, /*MI*/0, /*Op*/1, /*Type*/GILLT_s64,
      GIM_CheckType, /*MI*/0, /*Op*/2, /*Type*/GILLT_v4s32,
      GIM_CheckType, /*MI*/0, /*Op*/3, /*Type*/GILLT_s32,
      GIM_CheckType, /*MI*/0, /*Op*/4, /*Type*/GILLT_s32,
      GIM_CheckType, /*MI*/0, /*Op*/5, /*Type*/GILLT_s32,
      GIM_Try, /*On fail goto*//*Label 6375*/ GIMT_Encode4(467440), // Rule ID 5077 //
        GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasUnrestrictedSOffset),
        GIM_CheckHasNoUse, /*MI*/0,
        GIM_CheckConstantInt8, /*MI*/0, /*Op*/3, 0,
        GIM_CheckConstantInt8, /*MI*/0, /*Op*/4, 0,
        // MIs[0] offset
        GIM_CheckIsImm, /*MI*/0, /*Op*/6,
        // MIs[0] auxiliary
        GIM_CheckIsImm, /*MI*/0, /*Op*/7,
        // MIs[0] Operand 8
        GIM_CheckLiteralInt, /*MI*/0, /*Op*/8, GIMT_Encode8(0),
        GIM_CheckComplexPattern, /*MI*/0, /*Op*/5, /*Renderer*/GIMT_Encode2(0), GIMT_Encode2(GICP_gi_buf_soffset),
        // (SIbuffer_atomic_xor:{ *:[i64] } i64:{ *:[i64] }:$vdata_in, v4i32:{ *:[v4i32] }:$rsrc, 0:{ *:[i32] }, 0:{ *:[i32] }, (BUFSOffset:{ *:[i32] } i32:{ *:[i32] }:$soffset), (timm:{ *:[i32] }):$offset, (timm:{ *:[i32] }):$auxiliary, 0:{ *:[i1] })<<P:Predicate_SIbuffer_atomic_xor_noret>>  =>  (BUFFER_ATOMIC_XOR_X2_OFFSET anonymous_15036:{ *:[i64] }:$vdata_in, SReg_128:{ *:[v4i32] }:$rsrc, SCSrc_b32:{ *:[i32] }:$soffset, (timm:{ *:[i32] }):$offset, (extract_cpol:{ *:[i32] } ?:{ *:[i32] }:$auxiliary))
        GIR_BuildMI, /*InsnID*/0, /*Opcode*/GIMT_Encode2(AMDGPU::BUFFER_ATOMIC_XOR_X2_OFFSET),
        GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/1, // vdata_in
        GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/2, // rsrc
        GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/0, // soffset
        GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/6, // offset
        GIR_CustomOperandRenderer, /*InsnID*/0, /*OldInsnID*/0, /*OpIdx*/7, /*OperandRenderer*/GIMT_Encode2(GICR_renderExtractCPol), // auxiliary
        GIR_MergeMemOperands, /*InsnID*/0, /*NumInsns*/1, /*MergeInsnID's*/0,
        GIR_ConstrainSelectedInstOperands, /*InsnID*/0,
        GIR_EraseFromParent, /*InsnID*/0,
        // GIR_Coverage, 5077,
        GIR_Done,
      // Label 6375: @467440
      GIM_Try, /*On fail goto*//*Label 6376*/ GIMT_Encode4(467515), // Rule ID 5085 //
        GIM_CheckHasNoUse, /*MI*/0,
        GIM_CheckConstantInt8, /*MI*/0, /*Op*/3, 0,
        GIM_CheckConstantInt8, /*MI*/0, /*Op*/4, 0,
        // MIs[0] offset
        GIM_CheckIsImm, /*MI*/0, /*Op*/6,
        // MIs[0] auxiliary
        GIM_CheckIsImm, /*MI*/0, /*Op*/7,
        // MIs[0] Operand 8
        GIM_CheckLiteralInt, /*MI*/0, /*Op*/8, GIMT_Encode8(0),
        GIM_CheckComplexPattern, /*MI*/0, /*Op*/5, /*Renderer*/GIMT_Encode2(0), GIMT_Encode2(GICP_gi_buf_soffset),
        // (SIbuffer_atomic_xor:{ *:[i64] } i64:{ *:[i64] }:$vdata_in, v4i32:{ *:[v4i32] }:$rsrc, 0:{ *:[i32] }, 0:{ *:[i32] }, (BUFSOffset:{ *:[i32] } i32:{ *:[i32] }:$soffset), (timm:{ *:[i32] }):$offset, (timm:{ *:[i32] }):$auxiliary, 0:{ *:[i1] })<<P:Predicate_SIbuffer_atomic_xor_noret>>  =>  (BUFFER_ATOMIC_XOR_X2_VBUFFER_OFFSET anonymous_15036:{ *:[i64] }:$vdata_in, SReg_128:{ *:[v4i32] }:$rsrc, SCSrc_b32:{ *:[i32] }:$soffset, (timm:{ *:[i32] }):$offset, (extract_cpol:{ *:[i32] } ?:{ *:[i32] }:$auxiliary))
        GIR_BuildMI, /*InsnID*/0, /*Opcode*/GIMT_Encode2(AMDGPU::BUFFER_ATOMIC_XOR_X2_VBUFFER_OFFSET),
        GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/1, // vdata_in
        GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/2, // rsrc
        GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/0, // soffset
        GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/6, // offset
        GIR_CustomOperandRenderer, /*InsnID*/0, /*OldInsnID*/0, /*OpIdx*/7, /*OperandRenderer*/GIMT_Encode2(GICR_renderExtractCPol), // auxiliary
        GIR_MergeMemOperands, /*InsnID*/0, /*NumInsns*/1, /*MergeInsnID's*/0,
        GIR_ConstrainSelectedInstOperands, /*InsnID*/0,
        GIR_EraseFromParent, /*InsnID*/0,
        // GIR_Coverage, 5085,
        GIR_Done,
      // Label 6376: @467515
      GIM_Try, /*On fail goto*//*Label 6377*/ GIMT_Encode4(467600), // Rule ID 5073 //
        GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasUnrestrictedSOffset),
        GIM_CheckRegBankForClass, /*MI*/0, /*Op*/0, /*RC*/GIMT_Encode2(AMDGPU::AV_64RegClassID),
        GIM_CheckConstantInt8, /*MI*/0, /*Op*/3, 0,
        GIM_CheckConstantInt8, /*MI*/0, /*Op*/4, 0,
        // MIs[0] offset
        GIM_CheckIsImm, /*MI*/0, /*Op*/6,
        // MIs[0] auxiliary
        GIM_CheckIsImm, /*MI*/0, /*Op*/7,
        // MIs[0] Operand 8
        GIM_CheckLiteralInt, /*MI*/0, /*Op*/8, GIMT_Encode8(0),
        GIM_CheckComplexPattern, /*MI*/0, /*Op*/5, /*Renderer*/GIMT_Encode2(0), GIMT_Encode2(GICP_gi_buf_soffset),
        // (SIbuffer_atomic_xor:{ *:[i64] } i64:{ *:[i64] }:$vdata_in, v4i32:{ *:[v4i32] }:$rsrc, 0:{ *:[i32] }, 0:{ *:[i32] }, (BUFSOffset:{ *:[i32] } i32:{ *:[i32] }:$soffset), (timm:{ *:[i32] }):$offset, (timm:{ *:[i32] }):$auxiliary, 0:{ *:[i1] })  =>  (BUFFER_ATOMIC_XOR_X2_OFFSET_RTN:{ *:[i64] } anonymous_15036:{ *:[i64] }:$vdata_in, SReg_128:{ *:[v4i32] }:$rsrc, SCSrc_b32:{ *:[i32] }:$soffset, (timm:{ *:[i32] }):$offset, (extract_cpol_set_glc:{ *:[i32] } ?:{ *:[i32] }:$auxiliary))
        GIR_BuildMI, /*InsnID*/0, /*Opcode*/GIMT_Encode2(AMDGPU::BUFFER_ATOMIC_XOR_X2_OFFSET_RTN),
        GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/0, // DstI[vdata]
        GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/1, // vdata_in
        GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/2, // rsrc
        GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/0, // soffset
        GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/6, // offset
        GIR_CustomOperandRenderer, /*InsnID*/0, /*OldInsnID*/0, /*OpIdx*/7, /*OperandRenderer*/GIMT_Encode2(GICR_renderExtractCpolSetGLC), // auxiliary
        GIR_MergeMemOperands, /*InsnID*/0, /*NumInsns*/1, /*MergeInsnID's*/0,
        GIR_ConstrainSelectedInstOperands, /*InsnID*/0,
        GIR_EraseFromParent, /*InsnID*/0,
        // GIR_Coverage, 5073,
        GIR_Done,
      // Label 6377: @467600
      GIM_Try, /*On fail goto*//*Label 6378*/ GIMT_Encode4(467682), // Rule ID 5081 //
        GIM_CheckRegBankForClass, /*MI*/0, /*Op*/0, /*RC*/GIMT_Encode2(AMDGPU::AV_64RegClassID),
        GIM_CheckConstantInt8, /*MI*/0, /*Op*/3, 0,
        GIM_CheckConstantInt8, /*MI*/0, /*Op*/4, 0,
        // MIs[0] offset
        GIM_CheckIsImm, /*MI*/0, /*Op*/6,
        // MIs[0] auxiliary
        GIM_CheckIsImm, /*MI*/0, /*Op*/7,
        // MIs[0] Operand 8
        GIM_CheckLiteralInt, /*MI*/0, /*Op*/8, GIMT_Encode8(0),
        GIM_CheckComplexPattern, /*MI*/0, /*Op*/5, /*Renderer*/GIMT_Encode2(0), GIMT_Encode2(GICP_gi_buf_soffset),
        // (SIbuffer_atomic_xor:{ *:[i64] } i64:{ *:[i64] }:$vdata_in, v4i32:{ *:[v4i32] }:$rsrc, 0:{ *:[i32] }, 0:{ *:[i32] }, (BUFSOffset:{ *:[i32] } i32:{ *:[i32] }:$soffset), (timm:{ *:[i32] }):$offset, (timm:{ *:[i32] }):$auxiliary, 0:{ *:[i1] })  =>  (BUFFER_ATOMIC_XOR_X2_VBUFFER_OFFSET_RTN:{ *:[i64] } anonymous_15036:{ *:[i64] }:$vdata_in, SReg_128:{ *:[v4i32] }:$rsrc, SCSrc_b32:{ *:[i32] }:$soffset, (timm:{ *:[i32] }):$offset, (extract_cpol_set_glc:{ *:[i32] } ?:{ *:[i32] }:$auxiliary))
        GIR_BuildMI, /*InsnID*/0, /*Opcode*/GIMT_Encode2(AMDGPU::BUFFER_ATOMIC_XOR_X2_VBUFFER_OFFSET_RTN),
        GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/0, // DstI[vdata]
        GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/1, // vdata_in
        GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/2, // rsrc
        GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/0, // soffset
        GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/6, // offset
        GIR_CustomOperandRenderer, /*InsnID*/0, /*OldInsnID*/0, /*OpIdx*/7, /*OperandRenderer*/GIMT_Encode2(GICR_renderExtractCpolSetGLC), // auxiliary
        GIR_MergeMemOperands, /*InsnID*/0, /*NumInsns*/1, /*MergeInsnID's*/0,
        GIR_ConstrainSelectedInstOperands, /*InsnID*/0,
        GIR_EraseFromParent, /*InsnID*/0,
        // GIR_Coverage, 5081,
        GIR_Done,
      // Label 6378: @467682
      GIM_Try, /*On fail goto*//*Label 6379*/ GIMT_Encode4(467760), // Rule ID 5079 //
        GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasUnrestrictedSOffset),
        GIM_CheckHasNoUse, /*MI*/0,
        GIM_CheckConstantInt8, /*MI*/0, /*Op*/3, 0,
        // MIs[0] offset
        GIM_CheckIsImm, /*MI*/0, /*Op*/6,
        // MIs[0] auxiliary
        GIM_CheckIsImm, /*MI*/0, /*Op*/7,
        // MIs[0] Operand 8
        GIM_CheckLiteralInt, /*MI*/0, /*Op*/8, GIMT_Encode8(0),
        GIM_CheckComplexPattern, /*MI*/0, /*Op*/5, /*Renderer*/GIMT_Encode2(0), GIMT_Encode2(GICP_gi_buf_soffset),
        // (SIbuffer_atomic_xor:{ *:[i64] } i64:{ *:[i64] }:$vdata_in, v4i32:{ *:[v4i32] }:$rsrc, 0:{ *:[i32] }, i32:{ *:[i32] }:$voffset, (BUFSOffset:{ *:[i32] } i32:{ *:[i32] }:$soffset), (timm:{ *:[i32] }):$offset, (timm:{ *:[i32] }):$auxiliary, 0:{ *:[i1] })<<P:Predicate_SIbuffer_atomic_xor_noret>>  =>  (BUFFER_ATOMIC_XOR_X2_OFFEN anonymous_15036:{ *:[i64] }:$vdata_in, VGPR_32:{ *:[i32] }:$voffset, SReg_128:{ *:[v4i32] }:$rsrc, SCSrc_b32:{ *:[i32] }:$soffset, (timm:{ *:[i32] }):$offset, (extract_cpol:{ *:[i32] } ?:{ *:[i32] }:$auxiliary))
        GIR_BuildMI, /*InsnID*/0, /*Opcode*/GIMT_Encode2(AMDGPU::BUFFER_ATOMIC_XOR_X2_OFFEN),
        GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/1, // vdata_in
        GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/4, // voffset
        GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/2, // rsrc
        GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/0, // soffset
        GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/6, // offset
        GIR_CustomOperandRenderer, /*InsnID*/0, /*OldInsnID*/0, /*OpIdx*/7, /*OperandRenderer*/GIMT_Encode2(GICR_renderExtractCPol), // auxiliary
        GIR_MergeMemOperands, /*InsnID*/0, /*NumInsns*/1, /*MergeInsnID's*/0,
        GIR_ConstrainSelectedInstOperands, /*InsnID*/0,
        GIR_EraseFromParent, /*InsnID*/0,
        // GIR_Coverage, 5079,
        GIR_Done,
      // Label 6379: @467760
      GIM_Try, /*On fail goto*//*Label 6380*/ GIMT_Encode4(467835), // Rule ID 5087 //
        GIM_CheckHasNoUse, /*MI*/0,
        GIM_CheckConstantInt8, /*MI*/0, /*Op*/3, 0,
        // MIs[0] offset
        GIM_CheckIsImm, /*MI*/0, /*Op*/6,
        // MIs[0] auxiliary
        GIM_CheckIsImm, /*MI*/0, /*Op*/7,
        // MIs[0] Operand 8
        GIM_CheckLiteralInt, /*MI*/0, /*Op*/8, GIMT_Encode8(0),
        GIM_CheckComplexPattern, /*MI*/0, /*Op*/5, /*Renderer*/GIMT_Encode2(0), GIMT_Encode2(GICP_gi_buf_soffset),
        // (SIbuffer_atomic_xor:{ *:[i64] } i64:{ *:[i64] }:$vdata_in, v4i32:{ *:[v4i32] }:$rsrc, 0:{ *:[i32] }, i32:{ *:[i32] }:$voffset, (BUFSOffset:{ *:[i32] } i32:{ *:[i32] }:$soffset), (timm:{ *:[i32] }):$offset, (timm:{ *:[i32] }):$auxiliary, 0:{ *:[i1] })<<P:Predicate_SIbuffer_atomic_xor_noret>>  =>  (BUFFER_ATOMIC_XOR_X2_VBUFFER_OFFEN anonymous_15036:{ *:[i64] }:$vdata_in, VGPR_32:{ *:[i32] }:$voffset, SReg_128:{ *:[v4i32] }:$rsrc, SCSrc_b32:{ *:[i32] }:$soffset, (timm:{ *:[i32] }):$offset, (extract_cpol:{ *:[i32] } ?:{ *:[i32] }:$auxiliary))
        GIR_BuildMI, /*InsnID*/0, /*Opcode*/GIMT_Encode2(AMDGPU::BUFFER_ATOMIC_XOR_X2_VBUFFER_OFFEN),
        GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/1, // vdata_in
        GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/4, // voffset
        GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/2, // rsrc
        GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/0, // soffset
        GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/6, // offset
        GIR_CustomOperandRenderer, /*InsnID*/0, /*OldInsnID*/0, /*OpIdx*/7, /*OperandRenderer*/GIMT_Encode2(GICR_renderExtractCPol), // auxiliary
        GIR_MergeMemOperands, /*InsnID*/0, /*NumInsns*/1, /*MergeInsnID's*/0,
        GIR_ConstrainSelectedInstOperands, /*InsnID*/0,
        GIR_EraseFromParent, /*InsnID*/0,
        // GIR_Coverage, 5087,
        GIR_Done,
      // Label 6380: @467835
      GIM_Try, /*On fail goto*//*Label 6381*/ GIMT_Encode4(467920), // Rule ID 5075 //
        GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasUnrestrictedSOffset),
        GIM_CheckRegBankForClass, /*MI*/0, /*Op*/0, /*RC*/GIMT_Encode2(AMDGPU::AV_64RegClassID),
        GIM_CheckConstantInt8, /*MI*/0, /*Op*/3, 0,
        // MIs[0] offset
        GIM_CheckIsImm, /*MI*/0, /*Op*/6,
        // MIs[0] auxiliary
        GIM_CheckIsImm, /*MI*/0, /*Op*/7,
        // MIs[0] Operand 8
        GIM_CheckLiteralInt, /*MI*/0, /*Op*/8, GIMT_Encode8(0),
        GIM_CheckComplexPattern, /*MI*/0, /*Op*/5, /*Renderer*/GIMT_Encode2(0), GIMT_Encode2(GICP_gi_buf_soffset),
        // (SIbuffer_atomic_xor:{ *:[i64] } i64:{ *:[i64] }:$vdata_in, v4i32:{ *:[v4i32] }:$rsrc, 0:{ *:[i32] }, i32:{ *:[i32] }:$voffset, (BUFSOffset:{ *:[i32] } i32:{ *:[i32] }:$soffset), (timm:{ *:[i32] }):$offset, (timm:{ *:[i32] }):$auxiliary, 0:{ *:[i1] })  =>  (BUFFER_ATOMIC_XOR_X2_OFFEN_RTN:{ *:[i64] } anonymous_15036:{ *:[i64] }:$vdata_in, VGPR_32:{ *:[i32] }:$voffset, SReg_128:{ *:[v4i32] }:$rsrc, SCSrc_b32:{ *:[i32] }:$soffset, (timm:{ *:[i32] }):$offset, (extract_cpol_set_glc:{ *:[i32] } ?:{ *:[i32] }:$auxiliary))
        GIR_BuildMI, /*InsnID*/0, /*Opcode*/GIMT_Encode2(AMDGPU::BUFFER_ATOMIC_XOR_X2_OFFEN_RTN),
        GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/0, // DstI[vdata]
        GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/1, // vdata_in
        GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/4, // voffset
        GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/2, // rsrc
        GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/0, // soffset
        GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/6, // offset
        GIR_CustomOperandRenderer, /*InsnID*/0, /*OldInsnID*/0, /*OpIdx*/7, /*OperandRenderer*/GIMT_Encode2(GICR_renderExtractCpolSetGLC), // auxiliary
        GIR_MergeMemOperands, /*InsnID*/0, /*NumInsns*/1, /*MergeInsnID's*/0,
        GIR_ConstrainSelectedInstOperands, /*InsnID*/0,
        GIR_EraseFromParent, /*InsnID*/0,
        // GIR_Coverage, 5075,
        GIR_Done,
      // Label 6381: @467920
      GIM_Try, /*On fail goto*//*Label 6382*/ GIMT_Encode4(468002), // Rule ID 5083 //
        GIM_CheckRegBankForClass, /*MI*/0, /*Op*/0, /*RC*/GIMT_Encode2(AMDGPU::AV_64RegClassID),
        GIM_CheckConstantInt8, /*MI*/0, /*Op*/3, 0,
        // MIs[0] offset
        GIM_CheckIsImm, /*MI*/0, /*Op*/6,
        // MIs[0] auxiliary
        GIM_CheckIsImm, /*MI*/0, /*Op*/7,
        // MIs[0] Operand 8
        GIM_CheckLiteralInt, /*MI*/0, /*Op*/8, GIMT_Encode8(0),
        GIM_CheckComplexPattern, /*MI*/0, /*Op*/5, /*Renderer*/GIMT_Encode2(0), GIMT_Encode2(GICP_gi_buf_soffset),
        // (SIbuffer_atomic_xor:{ *:[i64] } i64:{ *:[i64] }:$vdata_in, v4i32:{ *:[v4i32] }:$rsrc, 0:{ *:[i32] }, i32:{ *:[i32] }:$voffset, (BUFSOffset:{ *:[i32] } i32:{ *:[i32] }:$soffset), (timm:{ *:[i32] }):$offset, (timm:{ *:[i32] }):$auxiliary, 0:{ *:[i1] })  =>  (BUFFER_ATOMIC_XOR_X2_VBUFFER_OFFEN_RTN:{ *:[i64] } anonymous_15036:{ *:[i64] }:$vdata_in, VGPR_32:{ *:[i32] }:$voffset, SReg_128:{ *:[v4i32] }:$rsrc, SCSrc_b32:{ *:[i32] }:$soffset, (timm:{ *:[i32] }):$offset, (extract_cpol_set_glc:{ *:[i32] } ?:{ *:[i32] }:$auxiliary))
        GIR_BuildMI, /*InsnID*/0, /*Opcode*/GIMT_Encode2(AMDGPU::BUFFER_ATOMIC_XOR_X2_VBUFFER_OFFEN_RTN),
        GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/0, // DstI[vdata]
        GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/1, // vdata_in
        GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/4, // voffset
        GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/2, // rsrc
        GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/0, // soffset
        GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/6, // offset
        GIR_CustomOperandRenderer, /*InsnID*/0, /*OldInsnID*/0, /*OpIdx*/7, /*OperandRenderer*/GIMT_Encode2(GICR_renderExtractCpolSetGLC), // auxiliary
        GIR_MergeMemOperands, /*InsnID*/0, /*NumInsns*/1, /*MergeInsnID's*/0,
        GIR_ConstrainSelectedInstOperands, /*InsnID*/0,
        GIR_EraseFromParent, /*InsnID*/0,
        // GIR_Coverage, 5083,
        GIR_Done,
      // Label 6382: @468002
      GIM_Try, /*On fail goto*//*Label 6383*/ GIMT_Encode4(468072), // Rule ID 5078 //
        GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasUnrestrictedSOffset),
        GIM_CheckHasNoUse, /*MI*/0,
        GIM_CheckConstantInt8, /*MI*/0, /*Op*/4, 0,
        // MIs[0] offset
        GIM_CheckIsImm, /*MI*/0, /*Op*/6,
        // MIs[0] auxiliary
        GIM_CheckIsImm, /*MI*/0, /*Op*/7,
        // MIs[0] Operand 8
        GIM_CheckIsImm, /*MI*/0, /*Op*/8,
        GIM_CheckComplexPattern, /*MI*/0, /*Op*/5, /*Renderer*/GIMT_Encode2(0), GIMT_Encode2(GICP_gi_buf_soffset),
        // (SIbuffer_atomic_xor:{ *:[i64] } i64:{ *:[i64] }:$vdata_in, v4i32:{ *:[v4i32] }:$rsrc, i32:{ *:[i32] }:$vindex, 0:{ *:[i32] }, (BUFSOffset:{ *:[i32] } i32:{ *:[i32] }:$soffset), (timm:{ *:[i32] }):$offset, (timm:{ *:[i32] }):$auxiliary, (timm:{ *:[i1] }))<<P:Predicate_SIbuffer_atomic_xor_noret>>  =>  (BUFFER_ATOMIC_XOR_X2_IDXEN anonymous_15036:{ *:[i64] }:$vdata_in, VGPR_32:{ *:[i32] }:$vindex, SReg_128:{ *:[v4i32] }:$rsrc, SCSrc_b32:{ *:[i32] }:$soffset, (timm:{ *:[i32] }):$offset, (extract_cpol:{ *:[i32] } ?:{ *:[i32] }:$auxiliary))
        GIR_BuildMI, /*InsnID*/0, /*Opcode*/GIMT_Encode2(AMDGPU::BUFFER_ATOMIC_XOR_X2_IDXEN),
        GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/1, // vdata_in
        GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/3, // vindex
        GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/2, // rsrc
        GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/0, // soffset
        GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/6, // offset
        GIR_CustomOperandRenderer, /*InsnID*/0, /*OldInsnID*/0, /*OpIdx*/7, /*OperandRenderer*/GIMT_Encode2(GICR_renderExtractCPol), // auxiliary
        GIR_MergeMemOperands, /*InsnID*/0, /*NumInsns*/1, /*MergeInsnID's*/0,
        GIR_ConstrainSelectedInstOperands, /*InsnID*/0,
        GIR_EraseFromParent, /*InsnID*/0,
        // GIR_Coverage, 5078,
        GIR_Done,
      // Label 6383: @468072
      GIM_Try, /*On fail goto*//*Label 6384*/ GIMT_Encode4(468139), // Rule ID 5086 //
        GIM_CheckHasNoUse, /*MI*/0,
        GIM_CheckConstantInt8, /*MI*/0, /*Op*/4, 0,
        // MIs[0] offset
        GIM_CheckIsImm, /*MI*/0, /*Op*/6,
        // MIs[0] auxiliary
        GIM_CheckIsImm, /*MI*/0, /*Op*/7,
        // MIs[0] Operand 8
        GIM_CheckIsImm, /*MI*/0, /*Op*/8,
        GIM_CheckComplexPattern, /*MI*/0, /*Op*/5, /*Renderer*/GIMT_Encode2(0), GIMT_Encode2(GICP_gi_buf_soffset),
        // (SIbuffer_atomic_xor:{ *:[i64] } i64:{ *:[i64] }:$vdata_in, v4i32:{ *:[v4i32] }:$rsrc, i32:{ *:[i32] }:$vindex, 0:{ *:[i32] }, (BUFSOffset:{ *:[i32] } i32:{ *:[i32] }:$soffset), (timm:{ *:[i32] }):$offset, (timm:{ *:[i32] }):$auxiliary, (timm:{ *:[i1] }))<<P:Predicate_SIbuffer_atomic_xor_noret>>  =>  (BUFFER_ATOMIC_XOR_X2_VBUFFER_IDXEN anonymous_15036:{ *:[i64] }:$vdata_in, VGPR_32:{ *:[i32] }:$vindex, SReg_128:{ *:[v4i32] }:$rsrc, SCSrc_b32:{ *:[i32] }:$soffset, (timm:{ *:[i32] }):$offset, (extract_cpol:{ *:[i32] } ?:{ *:[i32] }:$auxiliary))
        GIR_BuildMI, /*InsnID*/0, /*Opcode*/GIMT_Encode2(AMDGPU::BUFFER_ATOMIC_XOR_X2_VBUFFER_IDXEN),
        GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/1, // vdata_in
        GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/3, // vindex
        GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/2, // rsrc
        GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/0, // soffset
        GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/6, // offset
        GIR_CustomOperandRenderer, /*InsnID*/0, /*OldInsnID*/0, /*OpIdx*/7, /*OperandRenderer*/GIMT_Encode2(GICR_renderExtractCPol), // auxiliary
        GIR_MergeMemOperands, /*InsnID*/0, /*NumInsns*/1, /*MergeInsnID's*/0,
        GIR_ConstrainSelectedInstOperands, /*InsnID*/0,
        GIR_EraseFromParent, /*InsnID*/0,
        // GIR_Coverage, 5086,
        GIR_Done,
      // Label 6384: @468139
      GIM_Try, /*On fail goto*//*Label 6385*/ GIMT_Encode4(468216), // Rule ID 5074 //
        GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasUnrestrictedSOffset),
        GIM_CheckRegBankForClass, /*MI*/0, /*Op*/0, /*RC*/GIMT_Encode2(AMDGPU::AV_64RegClassID),
        GIM_CheckConstantInt8, /*MI*/0, /*Op*/4, 0,
        // MIs[0] offset
        GIM_CheckIsImm, /*MI*/0, /*Op*/6,
        // MIs[0] auxiliary
        GIM_CheckIsImm, /*MI*/0, /*Op*/7,
        // MIs[0] Operand 8
        GIM_CheckIsImm, /*MI*/0, /*Op*/8,
        GIM_CheckComplexPattern, /*MI*/0, /*Op*/5, /*Renderer*/GIMT_Encode2(0), GIMT_Encode2(GICP_gi_buf_soffset),
        // (SIbuffer_atomic_xor:{ *:[i64] } i64:{ *:[i64] }:$vdata_in, v4i32:{ *:[v4i32] }:$rsrc, i32:{ *:[i32] }:$vindex, 0:{ *:[i32] }, (BUFSOffset:{ *:[i32] } i32:{ *:[i32] }:$soffset), (timm:{ *:[i32] }):$offset, (timm:{ *:[i32] }):$auxiliary, (timm:{ *:[i1] }))  =>  (BUFFER_ATOMIC_XOR_X2_IDXEN_RTN:{ *:[i64] } anonymous_15036:{ *:[i64] }:$vdata_in, VGPR_32:{ *:[i32] }:$vindex, SReg_128:{ *:[v4i32] }:$rsrc, SCSrc_b32:{ *:[i32] }:$soffset, (timm:{ *:[i32] }):$offset, (extract_cpol_set_glc:{ *:[i32] } ?:{ *:[i32] }:$auxiliary))
        GIR_BuildMI, /*InsnID*/0, /*Opcode*/GIMT_Encode2(AMDGPU::BUFFER_ATOMIC_XOR_X2_IDXEN_RTN),
        GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/0, // DstI[vdata]
        GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/1, // vdata_in
        GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/3, // vindex
        GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/2, // rsrc
        GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/0, // soffset
        GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/6, // offset
        GIR_CustomOperandRenderer, /*InsnID*/0, /*OldInsnID*/0, /*OpIdx*/7, /*OperandRenderer*/GIMT_Encode2(GICR_renderExtractCpolSetGLC), // auxiliary
        GIR_MergeMemOperands, /*InsnID*/0, /*NumInsns*/1, /*MergeInsnID's*/0,
        GIR_ConstrainSelectedInstOperands, /*InsnID*/0,
        GIR_EraseFromParent, /*InsnID*/0,
        // GIR_Coverage, 5074,
        GIR_Done,
      // Label 6385: @468216
      GIM_Try, /*On fail goto*//*Label 6386*/ GIMT_Encode4(468290), // Rule ID 5082 //
        GIM_CheckRegBankForClass, /*MI*/0, /*Op*/0, /*RC*/GIMT_Encode2(AMDGPU::AV_64RegClassID),
        GIM_CheckConstantInt8, /*MI*/0, /*Op*/4, 0,
        // MIs[0] offset
        GIM_CheckIsImm, /*MI*/0, /*Op*/6,
        // MIs[0] auxiliary
        GIM_CheckIsImm, /*MI*/0, /*Op*/7,
        // MIs[0] Operand 8
        GIM_CheckIsImm, /*MI*/0, /*Op*/8,
        GIM_CheckComplexPattern, /*MI*/0, /*Op*/5, /*Renderer*/GIMT_Encode2(0), GIMT_Encode2(GICP_gi_buf_soffset),
        // (SIbuffer_atomic_xor:{ *:[i64] } i64:{ *:[i64] }:$vdata_in, v4i32:{ *:[v4i32] }:$rsrc, i32:{ *:[i32] }:$vindex, 0:{ *:[i32] }, (BUFSOffset:{ *:[i32] } i32:{ *:[i32] }:$soffset), (timm:{ *:[i32] }):$offset, (timm:{ *:[i32] }):$auxiliary, (timm:{ *:[i1] }))  =>  (BUFFER_ATOMIC_XOR_X2_VBUFFER_IDXEN_RTN:{ *:[i64] } anonymous_15036:{ *:[i64] }:$vdata_in, VGPR_32:{ *:[i32] }:$vindex, SReg_128:{ *:[v4i32] }:$rsrc, SCSrc_b32:{ *:[i32] }:$soffset, (timm:{ *:[i32] }):$offset, (extract_cpol_set_glc:{ *:[i32] } ?:{ *:[i32] }:$auxiliary))
        GIR_BuildMI, /*InsnID*/0, /*Opcode*/GIMT_Encode2(AMDGPU::BUFFER_ATOMIC_XOR_X2_VBUFFER_IDXEN_RTN),
        GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/0, // DstI[vdata]
        GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/1, // vdata_in
        GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/3, // vindex
        GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/2, // rsrc
        GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/0, // soffset
        GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/6, // offset
        GIR_CustomOperandRenderer, /*InsnID*/0, /*OldInsnID*/0, /*OpIdx*/7, /*OperandRenderer*/GIMT_Encode2(GICR_renderExtractCpolSetGLC), // auxiliary
        GIR_MergeMemOperands, /*InsnID*/0, /*NumInsns*/1, /*MergeInsnID's*/0,
        GIR_ConstrainSelectedInstOperands, /*InsnID*/0,
        GIR_EraseFromParent, /*InsnID*/0,
        // GIR_Coverage, 5082,
        GIR_Done,
      // Label 6386: @468290
      GIM_Try, /*On fail goto*//*Label 6387*/ GIMT_Encode4(468396), // Rule ID 5080 //
        GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasUnrestrictedSOffset),
        GIM_CheckHasNoUse, /*MI*/0,
        // MIs[0] offset
        GIM_CheckIsImm, /*MI*/0, /*Op*/6,
        // MIs[0] auxiliary
        GIM_CheckIsImm, /*MI*/0, /*Op*/7,
        // MIs[0] Operand 8
        GIM_CheckIsImm, /*MI*/0, /*Op*/8,
        GIM_CheckComplexPattern, /*MI*/0, /*Op*/5, /*Renderer*/GIMT_Encode2(0), GIMT_Encode2(GICP_gi_buf_soffset),
        // (SIbuffer_atomic_xor:{ *:[i64] } i64:{ *:[i64] }:$vdata_in, v4i32:{ *:[v4i32] }:$rsrc, i32:{ *:[i32] }:$vindex, i32:{ *:[i32] }:$voffset, (BUFSOffset:{ *:[i32] } i32:{ *:[i32] }:$soffset), (timm:{ *:[i32] }):$offset, (timm:{ *:[i32] }):$auxiliary, (timm:{ *:[i1] }))<<P:Predicate_SIbuffer_atomic_xor_noret>>  =>  (BUFFER_ATOMIC_XOR_X2_BOTHEN anonymous_15036:{ *:[i64] }:$vdata_in, (REG_SEQUENCE:{ *:[i64] } VReg_64:{ *:[i32] }, VGPR_32:{ *:[i32] }:$vindex, sub0:{ *:[i32] }, VGPR_32:{ *:[i32] }:$voffset, sub1:{ *:[i32] }), SReg_128:{ *:[v4i32] }:$rsrc, SCSrc_b32:{ *:[i32] }:$soffset, (timm:{ *:[i32] }):$offset, (extract_cpol:{ *:[i32] } ?:{ *:[i32] }:$auxiliary))
        GIR_MakeTempReg, /*TempRegID*/0, /*TypeID*/GILLT_s64,
        GIR_BuildMI, /*InsnID*/1, /*Opcode*/GIMT_Encode2(TargetOpcode::REG_SEQUENCE),
        GIR_AddTempRegister, /*InsnID*/1, /*TempRegID*/0, /*TempRegFlags*/GIMT_Encode2(RegState::Define),
        GIR_Copy, /*NewInsnID*/1, /*OldInsnID*/0, /*OpIdx*/3, // vindex
        GIR_AddImm8, /*InsnID*/1, /*SubRegIndex*/3,
        GIR_Copy, /*NewInsnID*/1, /*OldInsnID*/0, /*OpIdx*/4, // voffset
        GIR_AddImm8, /*InsnID*/1, /*SubRegIndex*/11,
        GIR_ConstrainOperandRC, /*InsnID*/1, /*Op*/0, GIMT_Encode2(AMDGPU::VReg_64RegClassID),
        GIR_ConstrainOperandRC, /*InsnID*/1, /*Op*/1, GIMT_Encode2(AMDGPU::VGPR_32RegClassID),
        GIR_ConstrainOperandRC, /*InsnID*/1, /*Op*/3, GIMT_Encode2(AMDGPU::VGPR_32RegClassID),
        GIR_BuildMI, /*InsnID*/0, /*Opcode*/GIMT_Encode2(AMDGPU::BUFFER_ATOMIC_XOR_X2_BOTHEN),
        GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/1, // vdata_in
        GIR_AddSimpleTempRegister, /*InsnID*/0, /*TempRegID*/0,
        GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/2, // rsrc
        GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/0, // soffset
        GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/6, // offset
        GIR_CustomOperandRenderer, /*InsnID*/0, /*OldInsnID*/0, /*OpIdx*/7, /*OperandRenderer*/GIMT_Encode2(GICR_renderExtractCPol), // auxiliary
        GIR_MergeMemOperands, /*InsnID*/0, /*NumInsns*/1, /*MergeInsnID's*/0,
        GIR_ConstrainSelectedInstOperands, /*InsnID*/0,
        GIR_EraseFromParent, /*InsnID*/0,
        // GIR_Coverage, 5080,
        GIR_Done,
      // Label 6387: @468396
      GIM_Try, /*On fail goto*//*Label 6388*/ GIMT_Encode4(468499), // Rule ID 5088 //
        GIM_CheckHasNoUse, /*MI*/0,
        // MIs[0] offset
        GIM_CheckIsImm, /*MI*/0, /*Op*/6,
        // MIs[0] auxiliary
        GIM_CheckIsImm, /*MI*/0, /*Op*/7,
        // MIs[0] Operand 8
        GIM_CheckIsImm, /*MI*/0, /*Op*/8,
        GIM_CheckComplexPattern, /*MI*/0, /*Op*/5, /*Renderer*/GIMT_Encode2(0), GIMT_Encode2(GICP_gi_buf_soffset),
        // (SIbuffer_atomic_xor:{ *:[i64] } i64:{ *:[i64] }:$vdata_in, v4i32:{ *:[v4i32] }:$rsrc, i32:{ *:[i32] }:$vindex, i32:{ *:[i32] }:$voffset, (BUFSOffset:{ *:[i32] } i32:{ *:[i32] }:$soffset), (timm:{ *:[i32] }):$offset, (timm:{ *:[i32] }):$auxiliary, (timm:{ *:[i1] }))<<P:Predicate_SIbuffer_atomic_xor_noret>>  =>  (BUFFER_ATOMIC_XOR_X2_VBUFFER_BOTHEN anonymous_15036:{ *:[i64] }:$vdata_in, (REG_SEQUENCE:{ *:[i64] } VReg_64:{ *:[i32] }, VGPR_32:{ *:[i32] }:$vindex, sub0:{ *:[i32] }, VGPR_32:{ *:[i32] }:$voffset, sub1:{ *:[i32] }), SReg_128:{ *:[v4i32] }:$rsrc, SCSrc_b32:{ *:[i32] }:$soffset, (timm:{ *:[i32] }):$offset, (extract_cpol:{ *:[i32] } ?:{ *:[i32] }:$auxiliary))
        GIR_MakeTempReg, /*TempRegID*/0, /*TypeID*/GILLT_s64,
        GIR_BuildMI, /*InsnID*/1, /*Opcode*/GIMT_Encode2(TargetOpcode::REG_SEQUENCE),
        GIR_AddTempRegister, /*InsnID*/1, /*TempRegID*/0, /*TempRegFlags*/GIMT_Encode2(RegState::Define),
        GIR_Copy, /*NewInsnID*/1, /*OldInsnID*/0, /*OpIdx*/3, // vindex
        GIR_AddImm8, /*InsnID*/1, /*SubRegIndex*/3,
        GIR_Copy, /*NewInsnID*/1, /*OldInsnID*/0, /*OpIdx*/4, // voffset
        GIR_AddImm8, /*InsnID*/1, /*SubRegIndex*/11,
        GIR_ConstrainOperandRC, /*InsnID*/1, /*Op*/0, GIMT_Encode2(AMDGPU::VReg_64RegClassID),
        GIR_ConstrainOperandRC, /*InsnID*/1, /*Op*/1, GIMT_Encode2(AMDGPU::VGPR_32RegClassID),
        GIR_ConstrainOperandRC, /*InsnID*/1, /*Op*/3, GIMT_Encode2(AMDGPU::VGPR_32RegClassID),
        GIR_BuildMI, /*InsnID*/0, /*Opcode*/GIMT_Encode2(AMDGPU::BUFFER_ATOMIC_XOR_X2_VBUFFER_BOTHEN),
        GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/1, // vdata_in
        GIR_AddSimpleTempRegister, /*InsnID*/0, /*TempRegID*/0,
        GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/2, // rsrc
        GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/0, // soffset
        GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/6, // offset
        GIR_CustomOperandRenderer, /*InsnID*/0, /*OldInsnID*/0, /*OpIdx*/7, /*OperandRenderer*/GIMT_Encode2(GICR_renderExtractCPol), // auxiliary
        GIR_MergeMemOperands, /*InsnID*/0, /*NumInsns*/1, /*MergeInsnID's*/0,
        GIR_ConstrainSelectedInstOperands, /*InsnID*/0,
        GIR_EraseFromParent, /*InsnID*/0,
        // GIR_Coverage, 5088,
        GIR_Done,
      // Label 6388: @468499
      GIM_Try, /*On fail goto*//*Label 6389*/ GIMT_Encode4(468612), // Rule ID 5076 //
        GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasUnrestrictedSOffset),
        GIM_CheckRegBankForClass, /*MI*/0, /*Op*/0, /*RC*/GIMT_Encode2(AMDGPU::AV_64RegClassID),
        // MIs[0] offset
        GIM_CheckIsImm, /*MI*/0, /*Op*/6,
        // MIs[0] auxiliary
        GIM_CheckIsImm, /*MI*/0, /*Op*/7,
        // MIs[0] Operand 8
        GIM_CheckIsImm, /*MI*/0, /*Op*/8,
        GIM_CheckComplexPattern, /*MI*/0, /*Op*/5, /*Renderer*/GIMT_Encode2(0), GIMT_Encode2(GICP_gi_buf_soffset),
        // (SIbuffer_atomic_xor:{ *:[i64] } i64:{ *:[i64] }:$vdata_in, v4i32:{ *:[v4i32] }:$rsrc, i32:{ *:[i32] }:$vindex, i32:{ *:[i32] }:$voffset, (BUFSOffset:{ *:[i32] } i32:{ *:[i32] }:$soffset), (timm:{ *:[i32] }):$offset, (timm:{ *:[i32] }):$auxiliary, (timm:{ *:[i1] }))  =>  (BUFFER_ATOMIC_XOR_X2_BOTHEN_RTN:{ *:[i64] } anonymous_15036:{ *:[i64] }:$vdata_in, (REG_SEQUENCE:{ *:[i64] } VReg_64:{ *:[i32] }, VGPR_32:{ *:[i32] }:$vindex, sub0:{ *:[i32] }, VGPR_32:{ *:[i32] }:$voffset, sub1:{ *:[i32] }), SReg_128:{ *:[v4i32] }:$rsrc, SCSrc_b32:{ *:[i32] }:$soffset, (timm:{ *:[i32] }):$offset, (extract_cpol_set_glc:{ *:[i32] } ?:{ *:[i32] }:$auxiliary))
        GIR_MakeTempReg, /*TempRegID*/0, /*TypeID*/GILLT_s64,
        GIR_BuildMI, /*InsnID*/1, /*Opcode*/GIMT_Encode2(TargetOpcode::REG_SEQUENCE),
        GIR_AddTempRegister, /*InsnID*/1, /*TempRegID*/0, /*TempRegFlags*/GIMT_Encode2(RegState::Define),
        GIR_Copy, /*NewInsnID*/1, /*OldInsnID*/0, /*OpIdx*/3, // vindex
        GIR_AddImm8, /*InsnID*/1, /*SubRegIndex*/3,
        GIR_Copy, /*NewInsnID*/1, /*OldInsnID*/0, /*OpIdx*/4, // voffset
        GIR_AddImm8, /*InsnID*/1, /*SubRegIndex*/11,
        GIR_ConstrainOperandRC, /*InsnID*/1, /*Op*/0, GIMT_Encode2(AMDGPU::VReg_64RegClassID),
        GIR_ConstrainOperandRC, /*InsnID*/1, /*Op*/1, GIMT_Encode2(AMDGPU::VGPR_32RegClassID),
        GIR_ConstrainOperandRC, /*InsnID*/1, /*Op*/3, GIMT_Encode2(AMDGPU::VGPR_32RegClassID),
        GIR_BuildMI, /*InsnID*/0, /*Opcode*/GIMT_Encode2(AMDGPU::BUFFER_ATOMIC_XOR_X2_BOTHEN_RTN),
        GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/0, // DstI[vdata]
        GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/1, // vdata_in
        GIR_AddSimpleTempRegister, /*InsnID*/0, /*TempRegID*/0,
        GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/2, // rsrc
        GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/0, // soffset
        GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/6, // offset
        GIR_CustomOperandRenderer, /*InsnID*/0, /*OldInsnID*/0, /*OpIdx*/7, /*OperandRenderer*/GIMT_Encode2(GICR_renderExtractCpolSetGLC), // auxiliary
        GIR_MergeMemOperands, /*InsnID*/0, /*NumInsns*/1, /*MergeInsnID's*/0,
        GIR_ConstrainSelectedInstOperands, /*InsnID*/0,
        GIR_EraseFromParent, /*InsnID*/0,
        // GIR_Coverage, 5076,
        GIR_Done,
      // Label 6389: @468612
      GIM_Try, /*On fail goto*//*Label 6390*/ GIMT_Encode4(468722), // Rule ID 5084 //
        GIM_CheckRegBankForClass, /*MI*/0, /*Op*/0, /*RC*/GIMT_Encode2(AMDGPU::AV_64RegClassID),
        // MIs[0] offset
        GIM_CheckIsImm, /*MI*/0, /*Op*/6,
        // MIs[0] auxiliary
        GIM_CheckIsImm, /*MI*/0, /*Op*/7,
        // MIs[0] Operand 8
        GIM_CheckIsImm, /*MI*/0, /*Op*/8,
        GIM_CheckComplexPattern, /*MI*/0, /*Op*/5, /*Renderer*/GIMT_Encode2(0), GIMT_Encode2(GICP_gi_buf_soffset),
        // (SIbuffer_atomic_xor:{ *:[i64] } i64:{ *:[i64] }:$vdata_in, v4i32:{ *:[v4i32] }:$rsrc, i32:{ *:[i32] }:$vindex, i32:{ *:[i32] }:$voffset, (BUFSOffset:{ *:[i32] } i32:{ *:[i32] }:$soffset), (timm:{ *:[i32] }):$offset, (timm:{ *:[i32] }):$auxiliary, (timm:{ *:[i1] }))  =>  (BUFFER_ATOMIC_XOR_X2_VBUFFER_BOTHEN_RTN:{ *:[i64] } anonymous_15036:{ *:[i64] }:$vdata_in, (REG_SEQUENCE:{ *:[i64] } VReg_64:{ *:[i32] }, VGPR_32:{ *:[i32] }:$vindex, sub0:{ *:[i32] }, VGPR_32:{ *:[i32] }:$voffset, sub1:{ *:[i32] }), SReg_128:{ *:[v4i32] }:$rsrc, SCSrc_b32:{ *:[i32] }:$soffset, (timm:{ *:[i32] }):$offset, (extract_cpol_set_glc:{ *:[i32] } ?:{ *:[i32] }:$auxiliary))
        GIR_MakeTempReg, /*TempRegID*/0, /*TypeID*/GILLT_s64,
        GIR_BuildMI, /*InsnID*/1, /*Opcode*/GIMT_Encode2(TargetOpcode::REG_SEQUENCE),
        GIR_AddTempRegister, /*InsnID*/1, /*TempRegID*/0, /*TempRegFlags*/GIMT_Encode2(RegState::Define),
        GIR_Copy, /*NewInsnID*/1, /*OldInsnID*/0, /*OpIdx*/3, // vindex
        GIR_AddImm8, /*InsnID*/1, /*SubRegIndex*/3,
        GIR_Copy, /*NewInsnID*/1, /*OldInsnID*/0, /*OpIdx*/4, // voffset
        GIR_AddImm8, /*InsnID*/1, /*SubRegIndex*/11,
        GIR_ConstrainOperandRC, /*InsnID*/1, /*Op*/0, GIMT_Encode2(AMDGPU::VReg_64RegClassID),
        GIR_ConstrainOperandRC, /*InsnID*/1, /*Op*/1, GIMT_Encode2(AMDGPU::VGPR_32RegClassID),
        GIR_ConstrainOperandRC, /*InsnID*/1, /*Op*/3, GIMT_Encode2(AMDGPU::VGPR_32RegClassID),
        GIR_BuildMI, /*InsnID*/0, /*Opcode*/GIMT_Encode2(AMDGPU::BUFFER_ATOMIC_XOR_X2_VBUFFER_BOTHEN_RTN),
        GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/0, // DstI[vdata]
        GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/1, // vdata_in
        GIR_AddSimpleTempRegister, /*InsnID*/0, /*TempRegID*/0,
        GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/2, // rsrc
        GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/0, // soffset
        GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/6, // offset
        GIR_CustomOperandRenderer, /*InsnID*/0, /*OldInsnID*/0, /*OpIdx*/7, /*OperandRenderer*/GIMT_Encode2(GICR_renderExtractCpolSetGLC), // auxiliary
        GIR_MergeMemOperands, /*InsnID*/0, /*NumInsns*/1, /*MergeInsnID's*/0,
        GIR_ConstrainSelectedInstOperands, /*InsnID*/0,
        GIR_EraseFromParent, /*InsnID*/0,
        // GIR_Coverage, 5084,
        GIR_Done,
      // Label 6390: @468722
      GIM_Reject,
    // Label 6374: @468723
    GIM_Reject,
    // Label 6356: @468724
    GIM_Reject,
    // Label 124: @468725
    GIM_SwitchType, /*MI*/0, /*Op*/0, /*[*/GIMT_Encode2(9), GIMT_Encode2(18), /*)*//*default:*//*Label 6397*/ GIMT_Encode4(477148),
    /*GILLT_s32*//*Label 6391*/ GIMT_Encode4(468772), GIMT_Encode4(0),
    /*GILLT_v2s16*//*Label 6392*/ GIMT_Encode4(470168),
    /*GILLT_v2s32*//*Label 6393*/ GIMT_Encode4(471564), GIMT_Encode4(0),
    /*GILLT_v3s32*//*Label 6394*/ GIMT_Encode4(472960), GIMT_Encode4(0),
    /*GILLT_v4s16*//*Label 6395*/ GIMT_Encode4(474356),
    /*GILLT_v4s32*//*Label 6396*/ GIMT_Encode4(475752),
    // Label 6391: @468772
    GIM_Try, /*On fail goto*//*Label 6398*/ GIMT_Encode4(470167),
      GIM_CheckType, /*MI*/0, /*Op*/1, /*Type*/GILLT_v4s32,
      GIM_CheckType, /*MI*/0, /*Op*/2, /*Type*/GILLT_s32,
      GIM_CheckType, /*MI*/0, /*Op*/3, /*Type*/GILLT_s32,
      GIM_CheckType, /*MI*/0, /*Op*/4, /*Type*/GILLT_s32,
      GIM_CheckRegBankForClass, /*MI*/0, /*Op*/0, /*RC*/GIMT_Encode2(AMDGPU::AV_32RegClassID),
      GIM_Try, /*On fail goto*//*Label 6399*/ GIMT_Encode4(468880), // Rule ID 4105 //
        GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasUnrestrictedSOffset),
        GIM_CheckConstantInt8, /*MI*/0, /*Op*/2, 0,
        GIM_CheckConstantInt8, /*MI*/0, /*Op*/3, 0,
        // MIs[0] offset
        GIM_CheckIsImm, /*MI*/0, /*Op*/5,
        // MIs[0] auxiliary
        GIM_CheckIsImm, /*MI*/0, /*Op*/6,
        // MIs[0] Operand 7
        GIM_CheckLiteralInt, /*MI*/0, /*Op*/7, GIMT_Encode8(0),
        GIM_CheckComplexPattern, /*MI*/0, /*Op*/4, /*Renderer*/GIMT_Encode2(0), GIMT_Encode2(GICP_gi_buf_soffset),
        // (SIbuffer_load:{ *:[f32] } v4i32:{ *:[v4i32] }:$rsrc, 0:{ *:[i32] }, 0:{ *:[i32] }, (BUFSOffset:{ *:[i32] } i32:{ *:[i32] }:$soffset), (timm:{ *:[i32] }):$offset, (timm:{ *:[i32] }):$auxiliary, 0:{ *:[i1] })  =>  (BUFFER_LOAD_DWORD_OFFSET:{ *:[f32] } SReg_128:{ *:[v4i32] }:$rsrc, SCSrc_b32:{ *:[i32] }:$soffset, (timm:{ *:[i32] }):$offset, (extract_cpol:{ *:[i32] } ?:{ *:[i32] }:$auxiliary), (extract_swz:{ *:[i1] } ?:{ *:[i32] }:$auxiliary))
        GIR_BuildMI, /*InsnID*/0, /*Opcode*/GIMT_Encode2(AMDGPU::BUFFER_LOAD_DWORD_OFFSET),
        GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/0, // DstI[vdata]
        GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/1, // rsrc
        GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/0, // soffset
        GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/5, // offset
        GIR_CustomOperandRenderer, /*InsnID*/0, /*OldInsnID*/0, /*OpIdx*/6, /*OperandRenderer*/GIMT_Encode2(GICR_renderExtractCPol), // auxiliary
        GIR_CustomOperandRenderer, /*InsnID*/0, /*OldInsnID*/0, /*OpIdx*/6, /*OperandRenderer*/GIMT_Encode2(GICR_renderExtractSWZ), // auxiliary
        GIR_MergeMemOperands, /*InsnID*/0, /*NumInsns*/1, /*MergeInsnID's*/0,
        GIR_ConstrainSelectedInstOperands, /*InsnID*/0,
        GIR_EraseFromParent, /*InsnID*/0,
        // GIR_Coverage, 4105,
        GIR_Done,
      // Label 6399: @468880
      GIM_Try, /*On fail goto*//*Label 6400*/ GIMT_Encode4(468959), // Rule ID 4109 //
        GIM_CheckConstantInt8, /*MI*/0, /*Op*/2, 0,
        GIM_CheckConstantInt8, /*MI*/0, /*Op*/3, 0,
        // MIs[0] offset
        GIM_CheckIsImm, /*MI*/0, /*Op*/5,
        // MIs[0] auxiliary
        GIM_CheckIsImm, /*MI*/0, /*Op*/6,
        // MIs[0] Operand 7
        GIM_CheckLiteralInt, /*MI*/0, /*Op*/7, GIMT_Encode8(0),
        GIM_CheckComplexPattern, /*MI*/0, /*Op*/4, /*Renderer*/GIMT_Encode2(0), GIMT_Encode2(GICP_gi_buf_soffset),
        // (SIbuffer_load:{ *:[f32] } v4i32:{ *:[v4i32] }:$rsrc, 0:{ *:[i32] }, 0:{ *:[i32] }, (BUFSOffset:{ *:[i32] } i32:{ *:[i32] }:$soffset), (timm:{ *:[i32] }):$offset, (timm:{ *:[i32] }):$auxiliary, 0:{ *:[i1] })  =>  (BUFFER_LOAD_DWORD_VBUFFER_OFFSET:{ *:[f32] } SReg_128:{ *:[v4i32] }:$rsrc, SCSrc_b32:{ *:[i32] }:$soffset, (timm:{ *:[i32] }):$offset, (extract_cpol:{ *:[i32] } ?:{ *:[i32] }:$auxiliary), (extract_swz:{ *:[i1] } ?:{ *:[i32] }:$auxiliary))
        GIR_BuildMI, /*InsnID*/0, /*Opcode*/GIMT_Encode2(AMDGPU::BUFFER_LOAD_DWORD_VBUFFER_OFFSET),
        GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/0, // DstI[vdata]
        GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/1, // rsrc
        GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/0, // soffset
        GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/5, // offset
        GIR_CustomOperandRenderer, /*InsnID*/0, /*OldInsnID*/0, /*OpIdx*/6, /*OperandRenderer*/GIMT_Encode2(GICR_renderExtractCPol), // auxiliary
        GIR_CustomOperandRenderer, /*InsnID*/0, /*OldInsnID*/0, /*OpIdx*/6, /*OperandRenderer*/GIMT_Encode2(GICR_renderExtractSWZ), // auxiliary
        GIR_MergeMemOperands, /*InsnID*/0, /*NumInsns*/1, /*MergeInsnID's*/0,
        GIR_ConstrainSelectedInstOperands, /*InsnID*/0,
        GIR_EraseFromParent, /*InsnID*/0,
        // GIR_Coverage, 4109,
        GIR_Done,
      // Label 6400: @468959
      GIM_Try, /*On fail goto*//*Label 6401*/ GIMT_Encode4(469041), // Rule ID 4113 //
        GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasUnrestrictedSOffset),
        GIM_CheckConstantInt8, /*MI*/0, /*Op*/2, 0,
        GIM_CheckConstantInt8, /*MI*/0, /*Op*/3, 0,
        // MIs[0] offset
        GIM_CheckIsImm, /*MI*/0, /*Op*/5,
        // MIs[0] auxiliary
        GIM_CheckIsImm, /*MI*/0, /*Op*/6,
        // MIs[0] Operand 7
        GIM_CheckLiteralInt, /*MI*/0, /*Op*/7, GIMT_Encode8(0),
        GIM_CheckComplexPattern, /*MI*/0, /*Op*/4, /*Renderer*/GIMT_Encode2(0), GIMT_Encode2(GICP_gi_buf_soffset),
        // (SIbuffer_load:{ *:[i32] } v4i32:{ *:[v4i32] }:$rsrc, 0:{ *:[i32] }, 0:{ *:[i32] }, (BUFSOffset:{ *:[i32] } i32:{ *:[i32] }:$soffset), (timm:{ *:[i32] }):$offset, (timm:{ *:[i32] }):$auxiliary, 0:{ *:[i1] })  =>  (BUFFER_LOAD_DWORD_OFFSET:{ *:[i32] } SReg_128:{ *:[v4i32] }:$rsrc, SCSrc_b32:{ *:[i32] }:$soffset, (timm:{ *:[i32] }):$offset, (extract_cpol:{ *:[i32] } ?:{ *:[i32] }:$auxiliary), (extract_swz:{ *:[i1] } ?:{ *:[i32] }:$auxiliary))
        GIR_BuildMI, /*InsnID*/0, /*Opcode*/GIMT_Encode2(AMDGPU::BUFFER_LOAD_DWORD_OFFSET),
        GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/0, // DstI[vdata]
        GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/1, // rsrc
        GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/0, // soffset
        GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/5, // offset
        GIR_CustomOperandRenderer, /*InsnID*/0, /*OldInsnID*/0, /*OpIdx*/6, /*OperandRenderer*/GIMT_Encode2(GICR_renderExtractCPol), // auxiliary
        GIR_CustomOperandRenderer, /*InsnID*/0, /*OldInsnID*/0, /*OpIdx*/6, /*OperandRenderer*/GIMT_Encode2(GICR_renderExtractSWZ), // auxiliary
        GIR_MergeMemOperands, /*InsnID*/0, /*NumInsns*/1, /*MergeInsnID's*/0,
        GIR_ConstrainSelectedInstOperands, /*InsnID*/0,
        GIR_EraseFromParent, /*InsnID*/0,
        // GIR_Coverage, 4113,
        GIR_Done,
      // Label 6401: @469041
      GIM_Try, /*On fail goto*//*Label 6402*/ GIMT_Encode4(469120), // Rule ID 4117 //
        GIM_CheckConstantInt8, /*MI*/0, /*Op*/2, 0,
        GIM_CheckConstantInt8, /*MI*/0, /*Op*/3, 0,
        // MIs[0] offset
        GIM_CheckIsImm, /*MI*/0, /*Op*/5,
        // MIs[0] auxiliary
        GIM_CheckIsImm, /*MI*/0, /*Op*/6,
        // MIs[0] Operand 7
        GIM_CheckLiteralInt, /*MI*/0, /*Op*/7, GIMT_Encode8(0),
        GIM_CheckComplexPattern, /*MI*/0, /*Op*/4, /*Renderer*/GIMT_Encode2(0), GIMT_Encode2(GICP_gi_buf_soffset),
        // (SIbuffer_load:{ *:[i32] } v4i32:{ *:[v4i32] }:$rsrc, 0:{ *:[i32] }, 0:{ *:[i32] }, (BUFSOffset:{ *:[i32] } i32:{ *:[i32] }:$soffset), (timm:{ *:[i32] }):$offset, (timm:{ *:[i32] }):$auxiliary, 0:{ *:[i1] })  =>  (BUFFER_LOAD_DWORD_VBUFFER_OFFSET:{ *:[i32] } SReg_128:{ *:[v4i32] }:$rsrc, SCSrc_b32:{ *:[i32] }:$soffset, (timm:{ *:[i32] }):$offset, (extract_cpol:{ *:[i32] } ?:{ *:[i32] }:$auxiliary), (extract_swz:{ *:[i1] } ?:{ *:[i32] }:$auxiliary))
        GIR_BuildMI, /*InsnID*/0, /*Opcode*/GIMT_Encode2(AMDGPU::BUFFER_LOAD_DWORD_VBUFFER_OFFSET),
        GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/0, // DstI[vdata]
        GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/1, // rsrc
        GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/0, // soffset
        GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/5, // offset
        GIR_CustomOperandRenderer, /*InsnID*/0, /*OldInsnID*/0, /*OpIdx*/6, /*OperandRenderer*/GIMT_Encode2(GICR_renderExtractCPol), // auxiliary
        GIR_CustomOperandRenderer, /*InsnID*/0, /*OldInsnID*/0, /*OpIdx*/6, /*OperandRenderer*/GIMT_Encode2(GICR_renderExtractSWZ), // auxiliary
        GIR_MergeMemOperands, /*InsnID*/0, /*NumInsns*/1, /*MergeInsnID's*/0,
        GIR_ConstrainSelectedInstOperands, /*InsnID*/0,
        GIR_EraseFromParent, /*InsnID*/0,
        // GIR_Coverage, 4117,
        GIR_Done,
      // Label 6402: @469120
      GIM_Try, /*On fail goto*//*Label 6403*/ GIMT_Encode4(469202), // Rule ID 4106 //
        GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasUnrestrictedSOffset),
        GIM_CheckConstantInt8, /*MI*/0, /*Op*/2, 0,
        // MIs[0] offset
        GIM_CheckIsImm, /*MI*/0, /*Op*/5,
        // MIs[0] auxiliary
        GIM_CheckIsImm, /*MI*/0, /*Op*/6,
        // MIs[0] Operand 7
        GIM_CheckLiteralInt, /*MI*/0, /*Op*/7, GIMT_Encode8(0),
        GIM_CheckComplexPattern, /*MI*/0, /*Op*/4, /*Renderer*/GIMT_Encode2(0), GIMT_Encode2(GICP_gi_buf_soffset),
        // (SIbuffer_load:{ *:[f32] } v4i32:{ *:[v4i32] }:$rsrc, 0:{ *:[i32] }, i32:{ *:[i32] }:$voffset, (BUFSOffset:{ *:[i32] } i32:{ *:[i32] }:$soffset), (timm:{ *:[i32] }):$offset, (timm:{ *:[i32] }):$auxiliary, 0:{ *:[i1] })  =>  (BUFFER_LOAD_DWORD_OFFEN:{ *:[f32] } VGPR_32:{ *:[i32] }:$voffset, SReg_128:{ *:[v4i32] }:$rsrc, SCSrc_b32:{ *:[i32] }:$soffset, (timm:{ *:[i32] }):$offset, (extract_cpol:{ *:[i32] } ?:{ *:[i32] }:$auxiliary), (extract_swz:{ *:[i1] } ?:{ *:[i32] }:$auxiliary))
        GIR_BuildMI, /*InsnID*/0, /*Opcode*/GIMT_Encode2(AMDGPU::BUFFER_LOAD_DWORD_OFFEN),
        GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/0, // DstI[vdata]
        GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/3, // voffset
        GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/1, // rsrc
        GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/0, // soffset
        GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/5, // offset
        GIR_CustomOperandRenderer, /*InsnID*/0, /*OldInsnID*/0, /*OpIdx*/6, /*OperandRenderer*/GIMT_Encode2(GICR_renderExtractCPol), // auxiliary
        GIR_CustomOperandRenderer, /*InsnID*/0, /*OldInsnID*/0, /*OpIdx*/6, /*OperandRenderer*/GIMT_Encode2(GICR_renderExtractSWZ), // auxiliary
        GIR_MergeMemOperands, /*InsnID*/0, /*NumInsns*/1, /*MergeInsnID's*/0,
        GIR_ConstrainSelectedInstOperands, /*InsnID*/0,
        GIR_EraseFromParent, /*InsnID*/0,
        // GIR_Coverage, 4106,
        GIR_Done,
      // Label 6403: @469202
      GIM_Try, /*On fail goto*//*Label 6404*/ GIMT_Encode4(469281), // Rule ID 4110 //
        GIM_CheckConstantInt8, /*MI*/0, /*Op*/2, 0,
        // MIs[0] offset
        GIM_CheckIsImm, /*MI*/0, /*Op*/5,
        // MIs[0] auxiliary
        GIM_CheckIsImm, /*MI*/0, /*Op*/6,
        // MIs[0] Operand 7
        GIM_CheckLiteralInt, /*MI*/0, /*Op*/7, GIMT_Encode8(0),
        GIM_CheckComplexPattern, /*MI*/0, /*Op*/4, /*Renderer*/GIMT_Encode2(0), GIMT_Encode2(GICP_gi_buf_soffset),
        // (SIbuffer_load:{ *:[f32] } v4i32:{ *:[v4i32] }:$rsrc, 0:{ *:[i32] }, i32:{ *:[i32] }:$voffset, (BUFSOffset:{ *:[i32] } i32:{ *:[i32] }:$soffset), (timm:{ *:[i32] }):$offset, (timm:{ *:[i32] }):$auxiliary, 0:{ *:[i1] })  =>  (BUFFER_LOAD_DWORD_VBUFFER_OFFEN:{ *:[f32] } VGPR_32:{ *:[i32] }:$voffset, SReg_128:{ *:[v4i32] }:$rsrc, SCSrc_b32:{ *:[i32] }:$soffset, (timm:{ *:[i32] }):$offset, (extract_cpol:{ *:[i32] } ?:{ *:[i32] }:$auxiliary), (extract_swz:{ *:[i1] } ?:{ *:[i32] }:$auxiliary))
        GIR_BuildMI, /*InsnID*/0, /*Opcode*/GIMT_Encode2(AMDGPU::BUFFER_LOAD_DWORD_VBUFFER_OFFEN),
        GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/0, // DstI[vdata]
        GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/3, // voffset
        GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/1, // rsrc
        GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/0, // soffset
        GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/5, // offset
        GIR_CustomOperandRenderer, /*InsnID*/0, /*OldInsnID*/0, /*OpIdx*/6, /*OperandRenderer*/GIMT_Encode2(GICR_renderExtractCPol), // auxiliary
        GIR_CustomOperandRenderer, /*InsnID*/0, /*OldInsnID*/0, /*OpIdx*/6, /*OperandRenderer*/GIMT_Encode2(GICR_renderExtractSWZ), // auxiliary
        GIR_MergeMemOperands, /*InsnID*/0, /*NumInsns*/1, /*MergeInsnID's*/0,
        GIR_ConstrainSelectedInstOperands, /*InsnID*/0,
        GIR_EraseFromParent, /*InsnID*/0,
        // GIR_Coverage, 4110,
        GIR_Done,
      // Label 6404: @469281
      GIM_Try, /*On fail goto*//*Label 6405*/ GIMT_Encode4(469363), // Rule ID 4114 //
        GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasUnrestrictedSOffset),
        GIM_CheckConstantInt8, /*MI*/0, /*Op*/2, 0,
        // MIs[0] offset
        GIM_CheckIsImm, /*MI*/0, /*Op*/5,
        // MIs[0] auxiliary
        GIM_CheckIsImm, /*MI*/0, /*Op*/6,
        // MIs[0] Operand 7
        GIM_CheckLiteralInt, /*MI*/0, /*Op*/7, GIMT_Encode8(0),
        GIM_CheckComplexPattern, /*MI*/0, /*Op*/4, /*Renderer*/GIMT_Encode2(0), GIMT_Encode2(GICP_gi_buf_soffset),
        // (SIbuffer_load:{ *:[i32] } v4i32:{ *:[v4i32] }:$rsrc, 0:{ *:[i32] }, i32:{ *:[i32] }:$voffset, (BUFSOffset:{ *:[i32] } i32:{ *:[i32] }:$soffset), (timm:{ *:[i32] }):$offset, (timm:{ *:[i32] }):$auxiliary, 0:{ *:[i1] })  =>  (BUFFER_LOAD_DWORD_OFFEN:{ *:[i32] } VGPR_32:{ *:[i32] }:$voffset, SReg_128:{ *:[v4i32] }:$rsrc, SCSrc_b32:{ *:[i32] }:$soffset, (timm:{ *:[i32] }):$offset, (extract_cpol:{ *:[i32] } ?:{ *:[i32] }:$auxiliary), (extract_swz:{ *:[i1] } ?:{ *:[i32] }:$auxiliary))
        GIR_BuildMI, /*InsnID*/0, /*Opcode*/GIMT_Encode2(AMDGPU::BUFFER_LOAD_DWORD_OFFEN),
        GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/0, // DstI[vdata]
        GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/3, // voffset
        GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/1, // rsrc
        GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/0, // soffset
        GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/5, // offset
        GIR_CustomOperandRenderer, /*InsnID*/0, /*OldInsnID*/0, /*OpIdx*/6, /*OperandRenderer*/GIMT_Encode2(GICR_renderExtractCPol), // auxiliary
        GIR_CustomOperandRenderer, /*InsnID*/0, /*OldInsnID*/0, /*OpIdx*/6, /*OperandRenderer*/GIMT_Encode2(GICR_renderExtractSWZ), // auxiliary
        GIR_MergeMemOperands, /*InsnID*/0, /*NumInsns*/1, /*MergeInsnID's*/0,
        GIR_ConstrainSelectedInstOperands, /*InsnID*/0,
        GIR_EraseFromParent, /*InsnID*/0,
        // GIR_Coverage, 4114,
        GIR_Done,
      // Label 6405: @469363
      GIM_Try, /*On fail goto*//*Label 6406*/ GIMT_Encode4(469442), // Rule ID 4118 //
        GIM_CheckConstantInt8, /*MI*/0, /*Op*/2, 0,
        // MIs[0] offset
        GIM_CheckIsImm, /*MI*/0, /*Op*/5,
        // MIs[0] auxiliary
        GIM_CheckIsImm, /*MI*/0, /*Op*/6,
        // MIs[0] Operand 7
        GIM_CheckLiteralInt, /*MI*/0, /*Op*/7, GIMT_Encode8(0),
        GIM_CheckComplexPattern, /*MI*/0, /*Op*/4, /*Renderer*/GIMT_Encode2(0), GIMT_Encode2(GICP_gi_buf_soffset),
        // (SIbuffer_load:{ *:[i32] } v4i32:{ *:[v4i32] }:$rsrc, 0:{ *:[i32] }, i32:{ *:[i32] }:$voffset, (BUFSOffset:{ *:[i32] } i32:{ *:[i32] }:$soffset), (timm:{ *:[i32] }):$offset, (timm:{ *:[i32] }):$auxiliary, 0:{ *:[i1] })  =>  (BUFFER_LOAD_DWORD_VBUFFER_OFFEN:{ *:[i32] } VGPR_32:{ *:[i32] }:$voffset, SReg_128:{ *:[v4i32] }:$rsrc, SCSrc_b32:{ *:[i32] }:$soffset, (timm:{ *:[i32] }):$offset, (extract_cpol:{ *:[i32] } ?:{ *:[i32] }:$auxiliary), (extract_swz:{ *:[i1] } ?:{ *:[i32] }:$auxiliary))
        GIR_BuildMI, /*InsnID*/0, /*Opcode*/GIMT_Encode2(AMDGPU::BUFFER_LOAD_DWORD_VBUFFER_OFFEN),
        GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/0, // DstI[vdata]
        GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/3, // voffset
        GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/1, // rsrc
        GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/0, // soffset
        GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/5, // offset
        GIR_CustomOperandRenderer, /*InsnID*/0, /*OldInsnID*/0, /*OpIdx*/6, /*OperandRenderer*/GIMT_Encode2(GICR_renderExtractCPol), // auxiliary
        GIR_CustomOperandRenderer, /*InsnID*/0, /*OldInsnID*/0, /*OpIdx*/6, /*OperandRenderer*/GIMT_Encode2(GICR_renderExtractSWZ), // auxiliary
        GIR_MergeMemOperands, /*InsnID*/0, /*NumInsns*/1, /*MergeInsnID's*/0,
        GIR_ConstrainSelectedInstOperands, /*InsnID*/0,
        GIR_EraseFromParent, /*InsnID*/0,
        // GIR_Coverage, 4118,
        GIR_Done,
      // Label 6406: @469442
      GIM_Try, /*On fail goto*//*Label 6407*/ GIMT_Encode4(469516), // Rule ID 4107 //
        GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasUnrestrictedSOffset),
        GIM_CheckConstantInt8, /*MI*/0, /*Op*/3, 0,
        // MIs[0] offset
        GIM_CheckIsImm, /*MI*/0, /*Op*/5,
        // MIs[0] auxiliary
        GIM_CheckIsImm, /*MI*/0, /*Op*/6,
        // MIs[0] Operand 7
        GIM_CheckIsImm, /*MI*/0, /*Op*/7,
        GIM_CheckComplexPattern, /*MI*/0, /*Op*/4, /*Renderer*/GIMT_Encode2(0), GIMT_Encode2(GICP_gi_buf_soffset),
        // (SIbuffer_load:{ *:[f32] } v4i32:{ *:[v4i32] }:$rsrc, i32:{ *:[i32] }:$vindex, 0:{ *:[i32] }, (BUFSOffset:{ *:[i32] } i32:{ *:[i32] }:$soffset), (timm:{ *:[i32] }):$offset, (timm:{ *:[i32] }):$auxiliary, (timm:{ *:[i1] }))  =>  (BUFFER_LOAD_DWORD_IDXEN:{ *:[f32] } VGPR_32:{ *:[i32] }:$vindex, SReg_128:{ *:[v4i32] }:$rsrc, SCSrc_b32:{ *:[i32] }:$soffset, (timm:{ *:[i32] }):$offset, (extract_cpol:{ *:[i32] } ?:{ *:[i32] }:$auxiliary), (extract_swz:{ *:[i1] } ?:{ *:[i32] }:$auxiliary))
        GIR_BuildMI, /*InsnID*/0, /*Opcode*/GIMT_Encode2(AMDGPU::BUFFER_LOAD_DWORD_IDXEN),
        GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/0, // DstI[vdata]
        GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/2, // vindex
        GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/1, // rsrc
        GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/0, // soffset
        GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/5, // offset
        GIR_CustomOperandRenderer, /*InsnID*/0, /*OldInsnID*/0, /*OpIdx*/6, /*OperandRenderer*/GIMT_Encode2(GICR_renderExtractCPol), // auxiliary
        GIR_CustomOperandRenderer, /*InsnID*/0, /*OldInsnID*/0, /*OpIdx*/6, /*OperandRenderer*/GIMT_Encode2(GICR_renderExtractSWZ), // auxiliary
        GIR_MergeMemOperands, /*InsnID*/0, /*NumInsns*/1, /*MergeInsnID's*/0,
        GIR_ConstrainSelectedInstOperands, /*InsnID*/0,
        GIR_EraseFromParent, /*InsnID*/0,
        // GIR_Coverage, 4107,
        GIR_Done,
      // Label 6407: @469516
      GIM_Try, /*On fail goto*//*Label 6408*/ GIMT_Encode4(469587), // Rule ID 4111 //
        GIM_CheckConstantInt8, /*MI*/0, /*Op*/3, 0,
        // MIs[0] offset
        GIM_CheckIsImm, /*MI*/0, /*Op*/5,
        // MIs[0] auxiliary
        GIM_CheckIsImm, /*MI*/0, /*Op*/6,
        // MIs[0] Operand 7
        GIM_CheckIsImm, /*MI*/0, /*Op*/7,
        GIM_CheckComplexPattern, /*MI*/0, /*Op*/4, /*Renderer*/GIMT_Encode2(0), GIMT_Encode2(GICP_gi_buf_soffset),
        // (SIbuffer_load:{ *:[f32] } v4i32:{ *:[v4i32] }:$rsrc, i32:{ *:[i32] }:$vindex, 0:{ *:[i32] }, (BUFSOffset:{ *:[i32] } i32:{ *:[i32] }:$soffset), (timm:{ *:[i32] }):$offset, (timm:{ *:[i32] }):$auxiliary, (timm:{ *:[i1] }))  =>  (BUFFER_LOAD_DWORD_VBUFFER_IDXEN:{ *:[f32] } VGPR_32:{ *:[i32] }:$vindex, SReg_128:{ *:[v4i32] }:$rsrc, SCSrc_b32:{ *:[i32] }:$soffset, (timm:{ *:[i32] }):$offset, (extract_cpol:{ *:[i32] } ?:{ *:[i32] }:$auxiliary), (extract_swz:{ *:[i1] } ?:{ *:[i32] }:$auxiliary))
        GIR_BuildMI, /*InsnID*/0, /*Opcode*/GIMT_Encode2(AMDGPU::BUFFER_LOAD_DWORD_VBUFFER_IDXEN),
        GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/0, // DstI[vdata]
        GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/2, // vindex
        GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/1, // rsrc
        GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/0, // soffset
        GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/5, // offset
        GIR_CustomOperandRenderer, /*InsnID*/0, /*OldInsnID*/0, /*OpIdx*/6, /*OperandRenderer*/GIMT_Encode2(GICR_renderExtractCPol), // auxiliary
        GIR_CustomOperandRenderer, /*InsnID*/0, /*OldInsnID*/0, /*OpIdx*/6, /*OperandRenderer*/GIMT_Encode2(GICR_renderExtractSWZ), // auxiliary
        GIR_MergeMemOperands, /*InsnID*/0, /*NumInsns*/1, /*MergeInsnID's*/0,
        GIR_ConstrainSelectedInstOperands, /*InsnID*/0,
        GIR_EraseFromParent, /*InsnID*/0,
        // GIR_Coverage, 4111,
        GIR_Done,
      // Label 6408: @469587
      GIM_Try, /*On fail goto*//*Label 6409*/ GIMT_Encode4(469661), // Rule ID 4115 //
        GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasUnrestrictedSOffset),
        GIM_CheckConstantInt8, /*MI*/0, /*Op*/3, 0,
        // MIs[0] offset
        GIM_CheckIsImm, /*MI*/0, /*Op*/5,
        // MIs[0] auxiliary
        GIM_CheckIsImm, /*MI*/0, /*Op*/6,
        // MIs[0] Operand 7
        GIM_CheckIsImm, /*MI*/0, /*Op*/7,
        GIM_CheckComplexPattern, /*MI*/0, /*Op*/4, /*Renderer*/GIMT_Encode2(0), GIMT_Encode2(GICP_gi_buf_soffset),
        // (SIbuffer_load:{ *:[i32] } v4i32:{ *:[v4i32] }:$rsrc, i32:{ *:[i32] }:$vindex, 0:{ *:[i32] }, (BUFSOffset:{ *:[i32] } i32:{ *:[i32] }:$soffset), (timm:{ *:[i32] }):$offset, (timm:{ *:[i32] }):$auxiliary, (timm:{ *:[i1] }))  =>  (BUFFER_LOAD_DWORD_IDXEN:{ *:[i32] } VGPR_32:{ *:[i32] }:$vindex, SReg_128:{ *:[v4i32] }:$rsrc, SCSrc_b32:{ *:[i32] }:$soffset, (timm:{ *:[i32] }):$offset, (extract_cpol:{ *:[i32] } ?:{ *:[i32] }:$auxiliary), (extract_swz:{ *:[i1] } ?:{ *:[i32] }:$auxiliary))
        GIR_BuildMI, /*InsnID*/0, /*Opcode*/GIMT_Encode2(AMDGPU::BUFFER_LOAD_DWORD_IDXEN),
        GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/0, // DstI[vdata]
        GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/2, // vindex
        GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/1, // rsrc
        GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/0, // soffset
        GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/5, // offset
        GIR_CustomOperandRenderer, /*InsnID*/0, /*OldInsnID*/0, /*OpIdx*/6, /*OperandRenderer*/GIMT_Encode2(GICR_renderExtractCPol), // auxiliary
        GIR_CustomOperandRenderer, /*InsnID*/0, /*OldInsnID*/0, /*OpIdx*/6, /*OperandRenderer*/GIMT_Encode2(GICR_renderExtractSWZ), // auxiliary
        GIR_MergeMemOperands, /*InsnID*/0, /*NumInsns*/1, /*MergeInsnID's*/0,
        GIR_ConstrainSelectedInstOperands, /*InsnID*/0,
        GIR_EraseFromParent, /*InsnID*/0,
        // GIR_Coverage, 4115,
        GIR_Done,
      // Label 6409: @469661
      GIM_Try, /*On fail goto*//*Label 6410*/ GIMT_Encode4(469732), // Rule ID 4119 //
        GIM_CheckConstantInt8, /*MI*/0, /*Op*/3, 0,
        // MIs[0] offset
        GIM_CheckIsImm, /*MI*/0, /*Op*/5,
        // MIs[0] auxiliary
        GIM_CheckIsImm, /*MI*/0, /*Op*/6,
        // MIs[0] Operand 7
        GIM_CheckIsImm, /*MI*/0, /*Op*/7,
        GIM_CheckComplexPattern, /*MI*/0, /*Op*/4, /*Renderer*/GIMT_Encode2(0), GIMT_Encode2(GICP_gi_buf_soffset),
        // (SIbuffer_load:{ *:[i32] } v4i32:{ *:[v4i32] }:$rsrc, i32:{ *:[i32] }:$vindex, 0:{ *:[i32] }, (BUFSOffset:{ *:[i32] } i32:{ *:[i32] }:$soffset), (timm:{ *:[i32] }):$offset, (timm:{ *:[i32] }):$auxiliary, (timm:{ *:[i1] }))  =>  (BUFFER_LOAD_DWORD_VBUFFER_IDXEN:{ *:[i32] } VGPR_32:{ *:[i32] }:$vindex, SReg_128:{ *:[v4i32] }:$rsrc, SCSrc_b32:{ *:[i32] }:$soffset, (timm:{ *:[i32] }):$offset, (extract_cpol:{ *:[i32] } ?:{ *:[i32] }:$auxiliary), (extract_swz:{ *:[i1] } ?:{ *:[i32] }:$auxiliary))
        GIR_BuildMI, /*InsnID*/0, /*Opcode*/GIMT_Encode2(AMDGPU::BUFFER_LOAD_DWORD_VBUFFER_IDXEN),
        GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/0, // DstI[vdata]
        GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/2, // vindex
        GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/1, // rsrc
        GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/0, // soffset
        GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/5, // offset
        GIR_CustomOperandRenderer, /*InsnID*/0, /*OldInsnID*/0, /*OpIdx*/6, /*OperandRenderer*/GIMT_Encode2(GICR_renderExtractCPol), // auxiliary
        GIR_CustomOperandRenderer, /*InsnID*/0, /*OldInsnID*/0, /*OpIdx*/6, /*OperandRenderer*/GIMT_Encode2(GICR_renderExtractSWZ), // auxiliary
        GIR_MergeMemOperands, /*InsnID*/0, /*NumInsns*/1, /*MergeInsnID's*/0,
        GIR_ConstrainSelectedInstOperands, /*InsnID*/0,
        GIR_EraseFromParent, /*InsnID*/0,
        // GIR_Coverage, 4119,
        GIR_Done,
      // Label 6410: @469732
      GIM_Try, /*On fail goto*//*Label 6411*/ GIMT_Encode4(469842), // Rule ID 4108 //
        GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasUnrestrictedSOffset),
        // MIs[0] offset
        GIM_CheckIsImm, /*MI*/0, /*Op*/5,
        // MIs[0] auxiliary
        GIM_CheckIsImm, /*MI*/0, /*Op*/6,
        // MIs[0] Operand 7
        GIM_CheckIsImm, /*MI*/0, /*Op*/7,
        GIM_CheckComplexPattern, /*MI*/0, /*Op*/4, /*Renderer*/GIMT_Encode2(0), GIMT_Encode2(GICP_gi_buf_soffset),
        // (SIbuffer_load:{ *:[f32] } v4i32:{ *:[v4i32] }:$rsrc, i32:{ *:[i32] }:$vindex, i32:{ *:[i32] }:$voffset, (BUFSOffset:{ *:[i32] } i32:{ *:[i32] }:$soffset), (timm:{ *:[i32] }):$offset, (timm:{ *:[i32] }):$auxiliary, (timm:{ *:[i1] }))  =>  (BUFFER_LOAD_DWORD_BOTHEN:{ *:[f32] } (REG_SEQUENCE:{ *:[i64] } VReg_64:{ *:[i32] }, VGPR_32:{ *:[i32] }:$vindex, sub0:{ *:[i32] }, VGPR_32:{ *:[i32] }:$voffset, sub1:{ *:[i32] }), SReg_128:{ *:[v4i32] }:$rsrc, SCSrc_b32:{ *:[i32] }:$soffset, (timm:{ *:[i32] }):$offset, (extract_cpol:{ *:[i32] } ?:{ *:[i32] }:$auxiliary), (extract_swz:{ *:[i1] } ?:{ *:[i32] }:$auxiliary))
        GIR_MakeTempReg, /*TempRegID*/0, /*TypeID*/GILLT_s64,
        GIR_BuildMI, /*InsnID*/1, /*Opcode*/GIMT_Encode2(TargetOpcode::REG_SEQUENCE),
        GIR_AddTempRegister, /*InsnID*/1, /*TempRegID*/0, /*TempRegFlags*/GIMT_Encode2(RegState::Define),
        GIR_Copy, /*NewInsnID*/1, /*OldInsnID*/0, /*OpIdx*/2, // vindex
        GIR_AddImm8, /*InsnID*/1, /*SubRegIndex*/3,
        GIR_Copy, /*NewInsnID*/1, /*OldInsnID*/0, /*OpIdx*/3, // voffset
        GIR_AddImm8, /*InsnID*/1, /*SubRegIndex*/11,
        GIR_ConstrainOperandRC, /*InsnID*/1, /*Op*/0, GIMT_Encode2(AMDGPU::VReg_64RegClassID),
        GIR_ConstrainOperandRC, /*InsnID*/1, /*Op*/1, GIMT_Encode2(AMDGPU::VGPR_32RegClassID),
        GIR_ConstrainOperandRC, /*InsnID*/1, /*Op*/3, GIMT_Encode2(AMDGPU::VGPR_32RegClassID),
        GIR_BuildMI, /*InsnID*/0, /*Opcode*/GIMT_Encode2(AMDGPU::BUFFER_LOAD_DWORD_BOTHEN),
        GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/0, // DstI[vdata]
        GIR_AddSimpleTempRegister, /*InsnID*/0, /*TempRegID*/0,
        GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/1, // rsrc
        GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/0, // soffset
        GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/5, // offset
        GIR_CustomOperandRenderer, /*InsnID*/0, /*OldInsnID*/0, /*OpIdx*/6, /*OperandRenderer*/GIMT_Encode2(GICR_renderExtractCPol), // auxiliary
        GIR_CustomOperandRenderer, /*InsnID*/0, /*OldInsnID*/0, /*OpIdx*/6, /*OperandRenderer*/GIMT_Encode2(GICR_renderExtractSWZ), // auxiliary
        GIR_MergeMemOperands, /*InsnID*/0, /*NumInsns*/1, /*MergeInsnID's*/0,
        GIR_ConstrainSelectedInstOperands, /*InsnID*/0,
        GIR_EraseFromParent, /*InsnID*/0,
        // GIR_Coverage, 4108,
        GIR_Done,
      // Label 6411: @469842
      GIM_Try, /*On fail goto*//*Label 6412*/ GIMT_Encode4(469949), // Rule ID 4112 //
        // MIs[0] offset
        GIM_CheckIsImm, /*MI*/0, /*Op*/5,
        // MIs[0] auxiliary
        GIM_CheckIsImm, /*MI*/0, /*Op*/6,
        // MIs[0] Operand 7
        GIM_CheckIsImm, /*MI*/0, /*Op*/7,
        GIM_CheckComplexPattern, /*MI*/0, /*Op*/4, /*Renderer*/GIMT_Encode2(0), GIMT_Encode2(GICP_gi_buf_soffset),
        // (SIbuffer_load:{ *:[f32] } v4i32:{ *:[v4i32] }:$rsrc, i32:{ *:[i32] }:$vindex, i32:{ *:[i32] }:$voffset, (BUFSOffset:{ *:[i32] } i32:{ *:[i32] }:$soffset), (timm:{ *:[i32] }):$offset, (timm:{ *:[i32] }):$auxiliary, (timm:{ *:[i1] }))  =>  (BUFFER_LOAD_DWORD_VBUFFER_BOTHEN:{ *:[f32] } (REG_SEQUENCE:{ *:[i64] } VReg_64:{ *:[i32] }, VGPR_32:{ *:[i32] }:$vindex, sub0:{ *:[i32] }, VGPR_32:{ *:[i32] }:$voffset, sub1:{ *:[i32] }), SReg_128:{ *:[v4i32] }:$rsrc, SCSrc_b32:{ *:[i32] }:$soffset, (timm:{ *:[i32] }):$offset, (extract_cpol:{ *:[i32] } ?:{ *:[i32] }:$auxiliary), (extract_swz:{ *:[i1] } ?:{ *:[i32] }:$auxiliary))
        GIR_MakeTempReg, /*TempRegID*/0, /*TypeID*/GILLT_s64,
        GIR_BuildMI, /*InsnID*/1, /*Opcode*/GIMT_Encode2(TargetOpcode::REG_SEQUENCE),
        GIR_AddTempRegister, /*InsnID*/1, /*TempRegID*/0, /*TempRegFlags*/GIMT_Encode2(RegState::Define),
        GIR_Copy, /*NewInsnID*/1, /*OldInsnID*/0, /*OpIdx*/2, // vindex
        GIR_AddImm8, /*InsnID*/1, /*SubRegIndex*/3,
        GIR_Copy, /*NewInsnID*/1, /*OldInsnID*/0, /*OpIdx*/3, // voffset
        GIR_AddImm8, /*InsnID*/1, /*SubRegIndex*/11,
        GIR_ConstrainOperandRC, /*InsnID*/1, /*Op*/0, GIMT_Encode2(AMDGPU::VReg_64RegClassID),
        GIR_ConstrainOperandRC, /*InsnID*/1, /*Op*/1, GIMT_Encode2(AMDGPU::VGPR_32RegClassID),
        GIR_ConstrainOperandRC, /*InsnID*/1, /*Op*/3, GIMT_Encode2(AMDGPU::VGPR_32RegClassID),
        GIR_BuildMI, /*InsnID*/0, /*Opcode*/GIMT_Encode2(AMDGPU::BUFFER_LOAD_DWORD_VBUFFER_BOTHEN),
        GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/0, // DstI[vdata]
        GIR_AddSimpleTempRegister, /*InsnID*/0, /*TempRegID*/0,
        GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/1, // rsrc
        GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/0, // soffset
        GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/5, // offset
        GIR_CustomOperandRenderer, /*InsnID*/0, /*OldInsnID*/0, /*OpIdx*/6, /*OperandRenderer*/GIMT_Encode2(GICR_renderExtractCPol), // auxiliary
        GIR_CustomOperandRenderer, /*InsnID*/0, /*OldInsnID*/0, /*OpIdx*/6, /*OperandRenderer*/GIMT_Encode2(GICR_renderExtractSWZ), // auxiliary
        GIR_MergeMemOperands, /*InsnID*/0, /*NumInsns*/1, /*MergeInsnID's*/0,
        GIR_ConstrainSelectedInstOperands, /*InsnID*/0,
        GIR_EraseFromParent, /*InsnID*/0,
        // GIR_Coverage, 4112,
        GIR_Done,
      // Label 6412: @469949
      GIM_Try, /*On fail goto*//*Label 6413*/ GIMT_Encode4(470059), // Rule ID 4116 //
        GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasUnrestrictedSOffset),
        // MIs[0] offset
        GIM_CheckIsImm, /*MI*/0, /*Op*/5,
        // MIs[0] auxiliary
        GIM_CheckIsImm, /*MI*/0, /*Op*/6,
        // MIs[0] Operand 7
        GIM_CheckIsImm, /*MI*/0, /*Op*/7,
        GIM_CheckComplexPattern, /*MI*/0, /*Op*/4, /*Renderer*/GIMT_Encode2(0), GIMT_Encode2(GICP_gi_buf_soffset),
        // (SIbuffer_load:{ *:[i32] } v4i32:{ *:[v4i32] }:$rsrc, i32:{ *:[i32] }:$vindex, i32:{ *:[i32] }:$voffset, (BUFSOffset:{ *:[i32] } i32:{ *:[i32] }:$soffset), (timm:{ *:[i32] }):$offset, (timm:{ *:[i32] }):$auxiliary, (timm:{ *:[i1] }))  =>  (BUFFER_LOAD_DWORD_BOTHEN:{ *:[i32] } (REG_SEQUENCE:{ *:[i64] } VReg_64:{ *:[i32] }, VGPR_32:{ *:[i32] }:$vindex, sub0:{ *:[i32] }, VGPR_32:{ *:[i32] }:$voffset, sub1:{ *:[i32] }), SReg_128:{ *:[v4i32] }:$rsrc, SCSrc_b32:{ *:[i32] }:$soffset, (timm:{ *:[i32] }):$offset, (extract_cpol:{ *:[i32] } ?:{ *:[i32] }:$auxiliary), (extract_swz:{ *:[i1] } ?:{ *:[i32] }:$auxiliary))
        GIR_MakeTempReg, /*TempRegID*/0, /*TypeID*/GILLT_s64,
        GIR_BuildMI, /*InsnID*/1, /*Opcode*/GIMT_Encode2(TargetOpcode::REG_SEQUENCE),
        GIR_AddTempRegister, /*InsnID*/1, /*TempRegID*/0, /*TempRegFlags*/GIMT_Encode2(RegState::Define),
        GIR_Copy, /*NewInsnID*/1, /*OldInsnID*/0, /*OpIdx*/2, // vindex
        GIR_AddImm8, /*InsnID*/1, /*SubRegIndex*/3,
        GIR_Copy, /*NewInsnID*/1, /*OldInsnID*/0, /*OpIdx*/3, // voffset
        GIR_AddImm8, /*InsnID*/1, /*SubRegIndex*/11,
        GIR_ConstrainOperandRC, /*InsnID*/1, /*Op*/0, GIMT_Encode2(AMDGPU::VReg_64RegClassID),
        GIR_ConstrainOperandRC, /*InsnID*/1, /*Op*/1, GIMT_Encode2(AMDGPU::VGPR_32RegClassID),
        GIR_ConstrainOperandRC, /*InsnID*/1, /*Op*/3, GIMT_Encode2(AMDGPU::VGPR_32RegClassID),
        GIR_BuildMI, /*InsnID*/0, /*Opcode*/GIMT_Encode2(AMDGPU::BUFFER_LOAD_DWORD_BOTHEN),
        GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/0, // DstI[vdata]
        GIR_AddSimpleTempRegister, /*InsnID*/0, /*TempRegID*/0,
        GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/1, // rsrc
        GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/0, // soffset
        GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/5, // offset
        GIR_CustomOperandRenderer, /*InsnID*/0, /*OldInsnID*/0, /*OpIdx*/6, /*OperandRenderer*/GIMT_Encode2(GICR_renderExtractCPol), // auxiliary
        GIR_CustomOperandRenderer, /*InsnID*/0, /*OldInsnID*/0, /*OpIdx*/6, /*OperandRenderer*/GIMT_Encode2(GICR_renderExtractSWZ), // auxiliary
        GIR_MergeMemOperands, /*InsnID*/0, /*NumInsns*/1, /*MergeInsnID's*/0,
        GIR_ConstrainSelectedInstOperands, /*InsnID*/0,
        GIR_EraseFromParent, /*InsnID*/0,
        // GIR_Coverage, 4116,
        GIR_Done,
      // Label 6413: @470059
      GIM_Try, /*On fail goto*//*Label 6414*/ GIMT_Encode4(470166), // Rule ID 4120 //
        // MIs[0] offset
        GIM_CheckIsImm, /*MI*/0, /*Op*/5,
        // MIs[0] auxiliary
        GIM_CheckIsImm, /*MI*/0, /*Op*/6,
        // MIs[0] Operand 7
        GIM_CheckIsImm, /*MI*/0, /*Op*/7,
        GIM_CheckComplexPattern, /*MI*/0, /*Op*/4, /*Renderer*/GIMT_Encode2(0), GIMT_Encode2(GICP_gi_buf_soffset),
        // (SIbuffer_load:{ *:[i32] } v4i32:{ *:[v4i32] }:$rsrc, i32:{ *:[i32] }:$vindex, i32:{ *:[i32] }:$voffset, (BUFSOffset:{ *:[i32] } i32:{ *:[i32] }:$soffset), (timm:{ *:[i32] }):$offset, (timm:{ *:[i32] }):$auxiliary, (timm:{ *:[i1] }))  =>  (BUFFER_LOAD_DWORD_VBUFFER_BOTHEN:{ *:[i32] } (REG_SEQUENCE:{ *:[i64] } VReg_64:{ *:[i32] }, VGPR_32:{ *:[i32] }:$vindex, sub0:{ *:[i32] }, VGPR_32:{ *:[i32] }:$voffset, sub1:{ *:[i32] }), SReg_128:{ *:[v4i32] }:$rsrc, SCSrc_b32:{ *:[i32] }:$soffset, (timm:{ *:[i32] }):$offset, (extract_cpol:{ *:[i32] } ?:{ *:[i32] }:$auxiliary), (extract_swz:{ *:[i1] } ?:{ *:[i32] }:$auxiliary))
        GIR_MakeTempReg, /*TempRegID*/0, /*TypeID*/GILLT_s64,
        GIR_BuildMI, /*InsnID*/1, /*Opcode*/GIMT_Encode2(TargetOpcode::REG_SEQUENCE),
        GIR_AddTempRegister, /*InsnID*/1, /*TempRegID*/0, /*TempRegFlags*/GIMT_Encode2(RegState::Define),
        GIR_Copy, /*NewInsnID*/1, /*OldInsnID*/0, /*OpIdx*/2, // vindex
        GIR_AddImm8, /*InsnID*/1, /*SubRegIndex*/3,
        GIR_Copy, /*NewInsnID*/1, /*OldInsnID*/0, /*OpIdx*/3, // voffset
        GIR_AddImm8, /*InsnID*/1, /*SubRegIndex*/11,
        GIR_ConstrainOperandRC, /*InsnID*/1, /*Op*/0, GIMT_Encode2(AMDGPU::VReg_64RegClassID),
        GIR_ConstrainOperandRC, /*InsnID*/1, /*Op*/1, GIMT_Encode2(AMDGPU::VGPR_32RegClassID),
        GIR_ConstrainOperandRC, /*InsnID*/1, /*Op*/3, GIMT_Encode2(AMDGPU::VGPR_32RegClassID),
        GIR_BuildMI, /*InsnID*/0, /*Opcode*/GIMT_Encode2(AMDGPU::BUFFER_LOAD_DWORD_VBUFFER_BOTHEN),
        GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/0, // DstI[vdata]
        GIR_AddSimpleTempRegister, /*InsnID*/0, /*TempRegID*/0,
        GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/1, // rsrc
        GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/0, // soffset
        GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/5, // offset
        GIR_CustomOperandRenderer, /*InsnID*/0, /*OldInsnID*/0, /*OpIdx*/6, /*OperandRenderer*/GIMT_Encode2(GICR_renderExtractCPol), // auxiliary
        GIR_CustomOperandRenderer, /*InsnID*/0, /*OldInsnID*/0, /*OpIdx*/6, /*OperandRenderer*/GIMT_Encode2(GICR_renderExtractSWZ), // auxiliary
        GIR_MergeMemOperands, /*InsnID*/0, /*NumInsns*/1, /*MergeInsnID's*/0,
        GIR_ConstrainSelectedInstOperands, /*InsnID*/0,
        GIR_EraseFromParent, /*InsnID*/0,
        // GIR_Coverage, 4120,
        GIR_Done,
      // Label 6414: @470166
      GIM_Reject,
    // Label 6398: @470167
    GIM_Reject,
    // Label 6392: @470168
    GIM_Try, /*On fail goto*//*Label 6415*/ GIMT_Encode4(471563),
      GIM_CheckType, /*MI*/0, /*Op*/1, /*Type*/GILLT_v4s32,
      GIM_CheckType, /*MI*/0, /*Op*/2, /*Type*/GILLT_s32,
      GIM_CheckType, /*MI*/0, /*Op*/3, /*Type*/GILLT_s32,
      GIM_CheckType, /*MI*/0, /*Op*/4, /*Type*/GILLT_s32,
      GIM_CheckRegBankForClass, /*MI*/0, /*Op*/0, /*RC*/GIMT_Encode2(AMDGPU::AV_32RegClassID),
      GIM_Try, /*On fail goto*//*Label 6416*/ GIMT_Encode4(470276), // Rule ID 4121 //
        GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasUnrestrictedSOffset),
        GIM_CheckConstantInt8, /*MI*/0, /*Op*/2, 0,
        GIM_CheckConstantInt8, /*MI*/0, /*Op*/3, 0,
        // MIs[0] offset
        GIM_CheckIsImm, /*MI*/0, /*Op*/5,
        // MIs[0] auxiliary
        GIM_CheckIsImm, /*MI*/0, /*Op*/6,
        // MIs[0] Operand 7
        GIM_CheckLiteralInt, /*MI*/0, /*Op*/7, GIMT_Encode8(0),
        GIM_CheckComplexPattern, /*MI*/0, /*Op*/4, /*Renderer*/GIMT_Encode2(0), GIMT_Encode2(GICP_gi_buf_soffset),
        // (SIbuffer_load:{ *:[v2i16] } v4i32:{ *:[v4i32] }:$rsrc, 0:{ *:[i32] }, 0:{ *:[i32] }, (BUFSOffset:{ *:[i32] } i32:{ *:[i32] }:$soffset), (timm:{ *:[i32] }):$offset, (timm:{ *:[i32] }):$auxiliary, 0:{ *:[i1] })  =>  (BUFFER_LOAD_DWORD_OFFSET:{ *:[v2i16] } SReg_128:{ *:[v4i32] }:$rsrc, SCSrc_b32:{ *:[i32] }:$soffset, (timm:{ *:[i32] }):$offset, (extract_cpol:{ *:[i32] } ?:{ *:[i32] }:$auxiliary), (extract_swz:{ *:[i1] } ?:{ *:[i32] }:$auxiliary))
        GIR_BuildMI, /*InsnID*/0, /*Opcode*/GIMT_Encode2(AMDGPU::BUFFER_LOAD_DWORD_OFFSET),
        GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/0, // DstI[vdata]
        GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/1, // rsrc
        GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/0, // soffset
        GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/5, // offset
        GIR_CustomOperandRenderer, /*InsnID*/0, /*OldInsnID*/0, /*OpIdx*/6, /*OperandRenderer*/GIMT_Encode2(GICR_renderExtractCPol), // auxiliary
        GIR_CustomOperandRenderer, /*InsnID*/0, /*OldInsnID*/0, /*OpIdx*/6, /*OperandRenderer*/GIMT_Encode2(GICR_renderExtractSWZ), // auxiliary
        GIR_MergeMemOperands, /*InsnID*/0, /*NumInsns*/1, /*MergeInsnID's*/0,
        GIR_ConstrainSelectedInstOperands, /*InsnID*/0,
        GIR_EraseFromParent, /*InsnID*/0,
        // GIR_Coverage, 4121,
        GIR_Done,
      // Label 6416: @470276
      GIM_Try, /*On fail goto*//*Label 6417*/ GIMT_Encode4(470355), // Rule ID 4125 //
        GIM_CheckConstantInt8, /*MI*/0, /*Op*/2, 0,
        GIM_CheckConstantInt8, /*MI*/0, /*Op*/3, 0,
        // MIs[0] offset
        GIM_CheckIsImm, /*MI*/0, /*Op*/5,
        // MIs[0] auxiliary
        GIM_CheckIsImm, /*MI*/0, /*Op*/6,
        // MIs[0] Operand 7
        GIM_CheckLiteralInt, /*MI*/0, /*Op*/7, GIMT_Encode8(0),
        GIM_CheckComplexPattern, /*MI*/0, /*Op*/4, /*Renderer*/GIMT_Encode2(0), GIMT_Encode2(GICP_gi_buf_soffset),
        // (SIbuffer_load:{ *:[v2i16] } v4i32:{ *:[v4i32] }:$rsrc, 0:{ *:[i32] }, 0:{ *:[i32] }, (BUFSOffset:{ *:[i32] } i32:{ *:[i32] }:$soffset), (timm:{ *:[i32] }):$offset, (timm:{ *:[i32] }):$auxiliary, 0:{ *:[i1] })  =>  (BUFFER_LOAD_DWORD_VBUFFER_OFFSET:{ *:[v2i16] } SReg_128:{ *:[v4i32] }:$rsrc, SCSrc_b32:{ *:[i32] }:$soffset, (timm:{ *:[i32] }):$offset, (extract_cpol:{ *:[i32] } ?:{ *:[i32] }:$auxiliary), (extract_swz:{ *:[i1] } ?:{ *:[i32] }:$auxiliary))
        GIR_BuildMI, /*InsnID*/0, /*Opcode*/GIMT_Encode2(AMDGPU::BUFFER_LOAD_DWORD_VBUFFER_OFFSET),
        GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/0, // DstI[vdata]
        GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/1, // rsrc
        GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/0, // soffset
        GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/5, // offset
        GIR_CustomOperandRenderer, /*InsnID*/0, /*OldInsnID*/0, /*OpIdx*/6, /*OperandRenderer*/GIMT_Encode2(GICR_renderExtractCPol), // auxiliary
        GIR_CustomOperandRenderer, /*InsnID*/0, /*OldInsnID*/0, /*OpIdx*/6, /*OperandRenderer*/GIMT_Encode2(GICR_renderExtractSWZ), // auxiliary
        GIR_MergeMemOperands, /*InsnID*/0, /*NumInsns*/1, /*MergeInsnID's*/0,
        GIR_ConstrainSelectedInstOperands, /*InsnID*/0,
        GIR_EraseFromParent, /*InsnID*/0,
        // GIR_Coverage, 4125,
        GIR_Done,
      // Label 6417: @470355
      GIM_Try, /*On fail goto*//*Label 6418*/ GIMT_Encode4(470437), // Rule ID 4129 //
        GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasUnrestrictedSOffset),
        GIM_CheckConstantInt8, /*MI*/0, /*Op*/2, 0,
        GIM_CheckConstantInt8, /*MI*/0, /*Op*/3, 0,
        // MIs[0] offset
        GIM_CheckIsImm, /*MI*/0, /*Op*/5,
        // MIs[0] auxiliary
        GIM_CheckIsImm, /*MI*/0, /*Op*/6,
        // MIs[0] Operand 7
        GIM_CheckLiteralInt, /*MI*/0, /*Op*/7, GIMT_Encode8(0),
        GIM_CheckComplexPattern, /*MI*/0, /*Op*/4, /*Renderer*/GIMT_Encode2(0), GIMT_Encode2(GICP_gi_buf_soffset),
        // (SIbuffer_load:{ *:[v2f16] } v4i32:{ *:[v4i32] }:$rsrc, 0:{ *:[i32] }, 0:{ *:[i32] }, (BUFSOffset:{ *:[i32] } i32:{ *:[i32] }:$soffset), (timm:{ *:[i32] }):$offset, (timm:{ *:[i32] }):$auxiliary, 0:{ *:[i1] })  =>  (BUFFER_LOAD_DWORD_OFFSET:{ *:[v2f16] } SReg_128:{ *:[v4i32] }:$rsrc, SCSrc_b32:{ *:[i32] }:$soffset, (timm:{ *:[i32] }):$offset, (extract_cpol:{ *:[i32] } ?:{ *:[i32] }:$auxiliary), (extract_swz:{ *:[i1] } ?:{ *:[i32] }:$auxiliary))
        GIR_BuildMI, /*InsnID*/0, /*Opcode*/GIMT_Encode2(AMDGPU::BUFFER_LOAD_DWORD_OFFSET),
        GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/0, // DstI[vdata]
        GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/1, // rsrc
        GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/0, // soffset
        GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/5, // offset
        GIR_CustomOperandRenderer, /*InsnID*/0, /*OldInsnID*/0, /*OpIdx*/6, /*OperandRenderer*/GIMT_Encode2(GICR_renderExtractCPol), // auxiliary
        GIR_CustomOperandRenderer, /*InsnID*/0, /*OldInsnID*/0, /*OpIdx*/6, /*OperandRenderer*/GIMT_Encode2(GICR_renderExtractSWZ), // auxiliary
        GIR_MergeMemOperands, /*InsnID*/0, /*NumInsns*/1, /*MergeInsnID's*/0,
        GIR_ConstrainSelectedInstOperands, /*InsnID*/0,
        GIR_EraseFromParent, /*InsnID*/0,
        // GIR_Coverage, 4129,
        GIR_Done,
      // Label 6418: @470437
      GIM_Try, /*On fail goto*//*Label 6419*/ GIMT_Encode4(470516), // Rule ID 4133 //
        GIM_CheckConstantInt8, /*MI*/0, /*Op*/2, 0,
        GIM_CheckConstantInt8, /*MI*/0, /*Op*/3, 0,
        // MIs[0] offset
        GIM_CheckIsImm, /*MI*/0, /*Op*/5,
        // MIs[0] auxiliary
        GIM_CheckIsImm, /*MI*/0, /*Op*/6,
        // MIs[0] Operand 7
        GIM_CheckLiteralInt, /*MI*/0, /*Op*/7, GIMT_Encode8(0),
        GIM_CheckComplexPattern, /*MI*/0, /*Op*/4, /*Renderer*/GIMT_Encode2(0), GIMT_Encode2(GICP_gi_buf_soffset),
        // (SIbuffer_load:{ *:[v2f16] } v4i32:{ *:[v4i32] }:$rsrc, 0:{ *:[i32] }, 0:{ *:[i32] }, (BUFSOffset:{ *:[i32] } i32:{ *:[i32] }:$soffset), (timm:{ *:[i32] }):$offset, (timm:{ *:[i32] }):$auxiliary, 0:{ *:[i1] })  =>  (BUFFER_LOAD_DWORD_VBUFFER_OFFSET:{ *:[v2f16] } SReg_128:{ *:[v4i32] }:$rsrc, SCSrc_b32:{ *:[i32] }:$soffset, (timm:{ *:[i32] }):$offset, (extract_cpol:{ *:[i32] } ?:{ *:[i32] }:$auxiliary), (extract_swz:{ *:[i1] } ?:{ *:[i32] }:$auxiliary))
        GIR_BuildMI, /*InsnID*/0, /*Opcode*/GIMT_Encode2(AMDGPU::BUFFER_LOAD_DWORD_VBUFFER_OFFSET),
        GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/0, // DstI[vdata]
        GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/1, // rsrc
        GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/0, // soffset
        GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/5, // offset
        GIR_CustomOperandRenderer, /*InsnID*/0, /*OldInsnID*/0, /*OpIdx*/6, /*OperandRenderer*/GIMT_Encode2(GICR_renderExtractCPol), // auxiliary
        GIR_CustomOperandRenderer, /*InsnID*/0, /*OldInsnID*/0, /*OpIdx*/6, /*OperandRenderer*/GIMT_Encode2(GICR_renderExtractSWZ), // auxiliary
        GIR_MergeMemOperands, /*InsnID*/0, /*NumInsns*/1, /*MergeInsnID's*/0,
        GIR_ConstrainSelectedInstOperands, /*InsnID*/0,
        GIR_EraseFromParent, /*InsnID*/0,
        // GIR_Coverage, 4133,
        GIR_Done,
      // Label 6419: @470516
      GIM_Try, /*On fail goto*//*Label 6420*/ GIMT_Encode4(470598), // Rule ID 4122 //
        GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasUnrestrictedSOffset),
        GIM_CheckConstantInt8, /*MI*/0, /*Op*/2, 0,
        // MIs[0] offset
        GIM_CheckIsImm, /*MI*/0, /*Op*/5,
        // MIs[0] auxiliary
        GIM_CheckIsImm, /*MI*/0, /*Op*/6,
        // MIs[0] Operand 7
        GIM_CheckLiteralInt, /*MI*/0, /*Op*/7, GIMT_Encode8(0),
        GIM_CheckComplexPattern, /*MI*/0, /*Op*/4, /*Renderer*/GIMT_Encode2(0), GIMT_Encode2(GICP_gi_buf_soffset),
        // (SIbuffer_load:{ *:[v2i16] } v4i32:{ *:[v4i32] }:$rsrc, 0:{ *:[i32] }, i32:{ *:[i32] }:$voffset, (BUFSOffset:{ *:[i32] } i32:{ *:[i32] }:$soffset), (timm:{ *:[i32] }):$offset, (timm:{ *:[i32] }):$auxiliary, 0:{ *:[i1] })  =>  (BUFFER_LOAD_DWORD_OFFEN:{ *:[v2i16] } VGPR_32:{ *:[i32] }:$voffset, SReg_128:{ *:[v4i32] }:$rsrc, SCSrc_b32:{ *:[i32] }:$soffset, (timm:{ *:[i32] }):$offset, (extract_cpol:{ *:[i32] } ?:{ *:[i32] }:$auxiliary), (extract_swz:{ *:[i1] } ?:{ *:[i32] }:$auxiliary))
        GIR_BuildMI, /*InsnID*/0, /*Opcode*/GIMT_Encode2(AMDGPU::BUFFER_LOAD_DWORD_OFFEN),
        GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/0, // DstI[vdata]
        GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/3, // voffset
        GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/1, // rsrc
        GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/0, // soffset
        GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/5, // offset
        GIR_CustomOperandRenderer, /*InsnID*/0, /*OldInsnID*/0, /*OpIdx*/6, /*OperandRenderer*/GIMT_Encode2(GICR_renderExtractCPol), // auxiliary
        GIR_CustomOperandRenderer, /*InsnID*/0, /*OldInsnID*/0, /*OpIdx*/6, /*OperandRenderer*/GIMT_Encode2(GICR_renderExtractSWZ), // auxiliary
        GIR_MergeMemOperands, /*InsnID*/0, /*NumInsns*/1, /*MergeInsnID's*/0,
        GIR_ConstrainSelectedInstOperands, /*InsnID*/0,
        GIR_EraseFromParent, /*InsnID*/0,
        // GIR_Coverage, 4122,
        GIR_Done,
      // Label 6420: @470598
      GIM_Try, /*On fail goto*//*Label 6421*/ GIMT_Encode4(470677), // Rule ID 4126 //
        GIM_CheckConstantInt8, /*MI*/0, /*Op*/2, 0,
        // MIs[0] offset
        GIM_CheckIsImm, /*MI*/0, /*Op*/5,
        // MIs[0] auxiliary
        GIM_CheckIsImm, /*MI*/0, /*Op*/6,
        // MIs[0] Operand 7
        GIM_CheckLiteralInt, /*MI*/0, /*Op*/7, GIMT_Encode8(0),
        GIM_CheckComplexPattern, /*MI*/0, /*Op*/4, /*Renderer*/GIMT_Encode2(0), GIMT_Encode2(GICP_gi_buf_soffset),
        // (SIbuffer_load:{ *:[v2i16] } v4i32:{ *:[v4i32] }:$rsrc, 0:{ *:[i32] }, i32:{ *:[i32] }:$voffset, (BUFSOffset:{ *:[i32] } i32:{ *:[i32] }:$soffset), (timm:{ *:[i32] }):$offset, (timm:{ *:[i32] }):$auxiliary, 0:{ *:[i1] })  =>  (BUFFER_LOAD_DWORD_VBUFFER_OFFEN:{ *:[v2i16] } VGPR_32:{ *:[i32] }:$voffset, SReg_128:{ *:[v4i32] }:$rsrc, SCSrc_b32:{ *:[i32] }:$soffset, (timm:{ *:[i32] }):$offset, (extract_cpol:{ *:[i32] } ?:{ *:[i32] }:$auxiliary), (extract_swz:{ *:[i1] } ?:{ *:[i32] }:$auxiliary))
        GIR_BuildMI, /*InsnID*/0, /*Opcode*/GIMT_Encode2(AMDGPU::BUFFER_LOAD_DWORD_VBUFFER_OFFEN),
        GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/0, // DstI[vdata]
        GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/3, // voffset
        GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/1, // rsrc
        GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/0, // soffset
        GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/5, // offset
        GIR_CustomOperandRenderer, /*InsnID*/0, /*OldInsnID*/0, /*OpIdx*/6, /*OperandRenderer*/GIMT_Encode2(GICR_renderExtractCPol), // auxiliary
        GIR_CustomOperandRenderer, /*InsnID*/0, /*OldInsnID*/0, /*OpIdx*/6, /*OperandRenderer*/GIMT_Encode2(GICR_renderExtractSWZ), // auxiliary
        GIR_MergeMemOperands, /*InsnID*/0, /*NumInsns*/1, /*MergeInsnID's*/0,
        GIR_ConstrainSelectedInstOperands, /*InsnID*/0,
        GIR_EraseFromParent, /*InsnID*/0,
        // GIR_Coverage, 4126,
        GIR_Done,
      // Label 6421: @470677
      GIM_Try, /*On fail goto*//*Label 6422*/ GIMT_Encode4(470759), // Rule ID 4130 //
        GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasUnrestrictedSOffset),
        GIM_CheckConstantInt8, /*MI*/0, /*Op*/2, 0,
        // MIs[0] offset
        GIM_CheckIsImm, /*MI*/0, /*Op*/5,
        // MIs[0] auxiliary
        GIM_CheckIsImm, /*MI*/0, /*Op*/6,
        // MIs[0] Operand 7
        GIM_CheckLiteralInt, /*MI*/0, /*Op*/7, GIMT_Encode8(0),
        GIM_CheckComplexPattern, /*MI*/0, /*Op*/4, /*Renderer*/GIMT_Encode2(0), GIMT_Encode2(GICP_gi_buf_soffset),
        // (SIbuffer_load:{ *:[v2f16] } v4i32:{ *:[v4i32] }:$rsrc, 0:{ *:[i32] }, i32:{ *:[i32] }:$voffset, (BUFSOffset:{ *:[i32] } i32:{ *:[i32] }:$soffset), (timm:{ *:[i32] }):$offset, (timm:{ *:[i32] }):$auxiliary, 0:{ *:[i1] })  =>  (BUFFER_LOAD_DWORD_OFFEN:{ *:[v2f16] } VGPR_32:{ *:[i32] }:$voffset, SReg_128:{ *:[v4i32] }:$rsrc, SCSrc_b32:{ *:[i32] }:$soffset, (timm:{ *:[i32] }):$offset, (extract_cpol:{ *:[i32] } ?:{ *:[i32] }:$auxiliary), (extract_swz:{ *:[i1] } ?:{ *:[i32] }:$auxiliary))
        GIR_BuildMI, /*InsnID*/0, /*Opcode*/GIMT_Encode2(AMDGPU::BUFFER_LOAD_DWORD_OFFEN),
        GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/0, // DstI[vdata]
        GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/3, // voffset
        GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/1, // rsrc
        GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/0, // soffset
        GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/5, // offset
        GIR_CustomOperandRenderer, /*InsnID*/0, /*OldInsnID*/0, /*OpIdx*/6, /*OperandRenderer*/GIMT_Encode2(GICR_renderExtractCPol), // auxiliary
        GIR_CustomOperandRenderer, /*InsnID*/0, /*OldInsnID*/0, /*OpIdx*/6, /*OperandRenderer*/GIMT_Encode2(GICR_renderExtractSWZ), // auxiliary
        GIR_MergeMemOperands, /*InsnID*/0, /*NumInsns*/1, /*MergeInsnID's*/0,
        GIR_ConstrainSelectedInstOperands, /*InsnID*/0,
        GIR_EraseFromParent, /*InsnID*/0,
        // GIR_Coverage, 4130,
        GIR_Done,
      // Label 6422: @470759
      GIM_Try, /*On fail goto*//*Label 6423*/ GIMT_Encode4(470838), // Rule ID 4134 //
        GIM_CheckConstantInt8, /*MI*/0, /*Op*/2, 0,
        // MIs[0] offset
        GIM_CheckIsImm, /*MI*/0, /*Op*/5,
        // MIs[0] auxiliary
        GIM_CheckIsImm, /*MI*/0, /*Op*/6,
        // MIs[0] Operand 7
        GIM_CheckLiteralInt, /*MI*/0, /*Op*/7, GIMT_Encode8(0),
        GIM_CheckComplexPattern, /*MI*/0, /*Op*/4, /*Renderer*/GIMT_Encode2(0), GIMT_Encode2(GICP_gi_buf_soffset),
        // (SIbuffer_load:{ *:[v2f16] } v4i32:{ *:[v4i32] }:$rsrc, 0:{ *:[i32] }, i32:{ *:[i32] }:$voffset, (BUFSOffset:{ *:[i32] } i32:{ *:[i32] }:$soffset), (timm:{ *:[i32] }):$offset, (timm:{ *:[i32] }):$auxiliary, 0:{ *:[i1] })  =>  (BUFFER_LOAD_DWORD_VBUFFER_OFFEN:{ *:[v2f16] } VGPR_32:{ *:[i32] }:$voffset, SReg_128:{ *:[v4i32] }:$rsrc, SCSrc_b32:{ *:[i32] }:$soffset, (timm:{ *:[i32] }):$offset, (extract_cpol:{ *:[i32] } ?:{ *:[i32] }:$auxiliary), (extract_swz:{ *:[i1] } ?:{ *:[i32] }:$auxiliary))
        GIR_BuildMI, /*InsnID*/0, /*Opcode*/GIMT_Encode2(AMDGPU::BUFFER_LOAD_DWORD_VBUFFER_OFFEN),
        GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/0, // DstI[vdata]
        GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/3, // voffset
        GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/1, // rsrc
        GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/0, // soffset
        GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/5, // offset
        GIR_CustomOperandRenderer, /*InsnID*/0, /*OldInsnID*/0, /*OpIdx*/6, /*OperandRenderer*/GIMT_Encode2(GICR_renderExtractCPol), // auxiliary
        GIR_CustomOperandRenderer, /*InsnID*/0, /*OldInsnID*/0, /*OpIdx*/6, /*OperandRenderer*/GIMT_Encode2(GICR_renderExtractSWZ), // auxiliary
        GIR_MergeMemOperands, /*InsnID*/0, /*NumInsns*/1, /*MergeInsnID's*/0,
        GIR_ConstrainSelectedInstOperands, /*InsnID*/0,
        GIR_EraseFromParent, /*InsnID*/0,
        // GIR_Coverage, 4134,
        GIR_Done,
      // Label 6423: @470838
      GIM_Try, /*On fail goto*//*Label 6424*/ GIMT_Encode4(470912), // Rule ID 4123 //
        GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasUnrestrictedSOffset),
        GIM_CheckConstantInt8, /*MI*/0, /*Op*/3, 0,
        // MIs[0] offset
        GIM_CheckIsImm, /*MI*/0, /*Op*/5,
        // MIs[0] auxiliary
        GIM_CheckIsImm, /*MI*/0, /*Op*/6,
        // MIs[0] Operand 7
        GIM_CheckIsImm, /*MI*/0, /*Op*/7,
        GIM_CheckComplexPattern, /*MI*/0, /*Op*/4, /*Renderer*/GIMT_Encode2(0), GIMT_Encode2(GICP_gi_buf_soffset),
        // (SIbuffer_load:{ *:[v2i16] } v4i32:{ *:[v4i32] }:$rsrc, i32:{ *:[i32] }:$vindex, 0:{ *:[i32] }, (BUFSOffset:{ *:[i32] } i32:{ *:[i32] }:$soffset), (timm:{ *:[i32] }):$offset, (timm:{ *:[i32] }):$auxiliary, (timm:{ *:[i1] }))  =>  (BUFFER_LOAD_DWORD_IDXEN:{ *:[v2i16] } VGPR_32:{ *:[i32] }:$vindex, SReg_128:{ *:[v4i32] }:$rsrc, SCSrc_b32:{ *:[i32] }:$soffset, (timm:{ *:[i32] }):$offset, (extract_cpol:{ *:[i32] } ?:{ *:[i32] }:$auxiliary), (extract_swz:{ *:[i1] } ?:{ *:[i32] }:$auxiliary))
        GIR_BuildMI, /*InsnID*/0, /*Opcode*/GIMT_Encode2(AMDGPU::BUFFER_LOAD_DWORD_IDXEN),
        GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/0, // DstI[vdata]
        GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/2, // vindex
        GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/1, // rsrc
        GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/0, // soffset
        GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/5, // offset
        GIR_CustomOperandRenderer, /*InsnID*/0, /*OldInsnID*/0, /*OpIdx*/6, /*OperandRenderer*/GIMT_Encode2(GICR_renderExtractCPol), // auxiliary
        GIR_CustomOperandRenderer, /*InsnID*/0, /*OldInsnID*/0, /*OpIdx*/6, /*OperandRenderer*/GIMT_Encode2(GICR_renderExtractSWZ), // auxiliary
        GIR_MergeMemOperands, /*InsnID*/0, /*NumInsns*/1, /*MergeInsnID's*/0,
        GIR_ConstrainSelectedInstOperands, /*InsnID*/0,
        GIR_EraseFromParent, /*InsnID*/0,
        // GIR_Coverage, 4123,
        GIR_Done,
      // Label 6424: @470912
      GIM_Try, /*On fail goto*//*Label 6425*/ GIMT_Encode4(470983), // Rule ID 4127 //
        GIM_CheckConstantInt8, /*MI*/0, /*Op*/3, 0,
        // MIs[0] offset
        GIM_CheckIsImm, /*MI*/0, /*Op*/5,
        // MIs[0] auxiliary
        GIM_CheckIsImm, /*MI*/0, /*Op*/6,
        // MIs[0] Operand 7
        GIM_CheckIsImm, /*MI*/0, /*Op*/7,
        GIM_CheckComplexPattern, /*MI*/0, /*Op*/4, /*Renderer*/GIMT_Encode2(0), GIMT_Encode2(GICP_gi_buf_soffset),
        // (SIbuffer_load:{ *:[v2i16] } v4i32:{ *:[v4i32] }:$rsrc, i32:{ *:[i32] }:$vindex, 0:{ *:[i32] }, (BUFSOffset:{ *:[i32] } i32:{ *:[i32] }:$soffset), (timm:{ *:[i32] }):$offset, (timm:{ *:[i32] }):$auxiliary, (timm:{ *:[i1] }))  =>  (BUFFER_LOAD_DWORD_VBUFFER_IDXEN:{ *:[v2i16] } VGPR_32:{ *:[i32] }:$vindex, SReg_128:{ *:[v4i32] }:$rsrc, SCSrc_b32:{ *:[i32] }:$soffset, (timm:{ *:[i32] }):$offset, (extract_cpol:{ *:[i32] } ?:{ *:[i32] }:$auxiliary), (extract_swz:{ *:[i1] } ?:{ *:[i32] }:$auxiliary))
        GIR_BuildMI, /*InsnID*/0, /*Opcode*/GIMT_Encode2(AMDGPU::BUFFER_LOAD_DWORD_VBUFFER_IDXEN),
        GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/0, // DstI[vdata]
        GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/2, // vindex
        GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/1, // rsrc
        GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/0, // soffset
        GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/5, // offset
        GIR_CustomOperandRenderer, /*InsnID*/0, /*OldInsnID*/0, /*OpIdx*/6, /*OperandRenderer*/GIMT_Encode2(GICR_renderExtractCPol), // auxiliary
        GIR_CustomOperandRenderer, /*InsnID*/0, /*OldInsnID*/0, /*OpIdx*/6, /*OperandRenderer*/GIMT_Encode2(GICR_renderExtractSWZ), // auxiliary
        GIR_MergeMemOperands, /*InsnID*/0, /*NumInsns*/1, /*MergeInsnID's*/0,
        GIR_ConstrainSelectedInstOperands, /*InsnID*/0,
        GIR_EraseFromParent, /*InsnID*/0,
        // GIR_Coverage, 4127,
        GIR_Done,
      // Label 6425: @470983
      GIM_Try, /*On fail goto*//*Label 6426*/ GIMT_Encode4(471057), // Rule ID 4131 //
        GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasUnrestrictedSOffset),
        GIM_CheckConstantInt8, /*MI*/0, /*Op*/3, 0,
        // MIs[0] offset
        GIM_CheckIsImm, /*MI*/0, /*Op*/5,
        // MIs[0] auxiliary
        GIM_CheckIsImm, /*MI*/0, /*Op*/6,
        // MIs[0] Operand 7
        GIM_CheckIsImm, /*MI*/0, /*Op*/7,
        GIM_CheckComplexPattern, /*MI*/0, /*Op*/4, /*Renderer*/GIMT_Encode2(0), GIMT_Encode2(GICP_gi_buf_soffset),
        // (SIbuffer_load:{ *:[v2f16] } v4i32:{ *:[v4i32] }:$rsrc, i32:{ *:[i32] }:$vindex, 0:{ *:[i32] }, (BUFSOffset:{ *:[i32] } i32:{ *:[i32] }:$soffset), (timm:{ *:[i32] }):$offset, (timm:{ *:[i32] }):$auxiliary, (timm:{ *:[i1] }))  =>  (BUFFER_LOAD_DWORD_IDXEN:{ *:[v2f16] } VGPR_32:{ *:[i32] }:$vindex, SReg_128:{ *:[v4i32] }:$rsrc, SCSrc_b32:{ *:[i32] }:$soffset, (timm:{ *:[i32] }):$offset, (extract_cpol:{ *:[i32] } ?:{ *:[i32] }:$auxiliary), (extract_swz:{ *:[i1] } ?:{ *:[i32] }:$auxiliary))
        GIR_BuildMI, /*InsnID*/0, /*Opcode*/GIMT_Encode2(AMDGPU::BUFFER_LOAD_DWORD_IDXEN),
        GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/0, // DstI[vdata]
        GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/2, // vindex
        GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/1, // rsrc
        GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/0, // soffset
        GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/5, // offset
        GIR_CustomOperandRenderer, /*InsnID*/0, /*OldInsnID*/0, /*OpIdx*/6, /*OperandRenderer*/GIMT_Encode2(GICR_renderExtractCPol), // auxiliary
        GIR_CustomOperandRenderer, /*InsnID*/0, /*OldInsnID*/0, /*OpIdx*/6, /*OperandRenderer*/GIMT_Encode2(GICR_renderExtractSWZ), // auxiliary
        GIR_MergeMemOperands, /*InsnID*/0, /*NumInsns*/1, /*MergeInsnID's*/0,
        GIR_ConstrainSelectedInstOperands, /*InsnID*/0,
        GIR_EraseFromParent, /*InsnID*/0,
        // GIR_Coverage, 4131,
        GIR_Done,
      // Label 6426: @471057
      GIM_Try, /*On fail goto*//*Label 6427*/ GIMT_Encode4(471128), // Rule ID 4135 //
        GIM_CheckConstantInt8, /*MI*/0, /*Op*/3, 0,
        // MIs[0] offset
        GIM_CheckIsImm, /*MI*/0, /*Op*/5,
        // MIs[0] auxiliary
        GIM_CheckIsImm, /*MI*/0, /*Op*/6,
        // MIs[0] Operand 7
        GIM_CheckIsImm, /*MI*/0, /*Op*/7,
        GIM_CheckComplexPattern, /*MI*/0, /*Op*/4, /*Renderer*/GIMT_Encode2(0), GIMT_Encode2(GICP_gi_buf_soffset),
        // (SIbuffer_load:{ *:[v2f16] } v4i32:{ *:[v4i32] }:$rsrc, i32:{ *:[i32] }:$vindex, 0:{ *:[i32] }, (BUFSOffset:{ *:[i32] } i32:{ *:[i32] }:$soffset), (timm:{ *:[i32] }):$offset, (timm:{ *:[i32] }):$auxiliary, (timm:{ *:[i1] }))  =>  (BUFFER_LOAD_DWORD_VBUFFER_IDXEN:{ *:[v2f16] } VGPR_32:{ *:[i32] }:$vindex, SReg_128:{ *:[v4i32] }:$rsrc, SCSrc_b32:{ *:[i32] }:$soffset, (timm:{ *:[i32] }):$offset, (extract_cpol:{ *:[i32] } ?:{ *:[i32] }:$auxiliary), (extract_swz:{ *:[i1] } ?:{ *:[i32] }:$auxiliary))
        GIR_BuildMI, /*InsnID*/0, /*Opcode*/GIMT_Encode2(AMDGPU::BUFFER_LOAD_DWORD_VBUFFER_IDXEN),
        GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/0, // DstI[vdata]
        GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/2, // vindex
        GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/1, // rsrc
        GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/0, // soffset
        GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/5, // offset
        GIR_CustomOperandRenderer, /*InsnID*/0, /*OldInsnID*/0, /*OpIdx*/6, /*OperandRenderer*/GIMT_Encode2(GICR_renderExtractCPol), // auxiliary
        GIR_CustomOperandRenderer, /*InsnID*/0, /*OldInsnID*/0, /*OpIdx*/6, /*OperandRenderer*/GIMT_Encode2(GICR_renderExtractSWZ), // auxiliary
        GIR_MergeMemOperands, /*InsnID*/0, /*NumInsns*/1, /*MergeInsnID's*/0,
        GIR_ConstrainSelectedInstOperands, /*InsnID*/0,
        GIR_EraseFromParent, /*InsnID*/0,
        // GIR_Coverage, 4135,
        GIR_Done,
      // Label 6427: @471128
      GIM_Try, /*On fail goto*//*Label 6428*/ GIMT_Encode4(471238), // Rule ID 4124 //
        GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasUnrestrictedSOffset),
        // MIs[0] offset
        GIM_CheckIsImm, /*MI*/0, /*Op*/5,
        // MIs[0] auxiliary
        GIM_CheckIsImm, /*MI*/0, /*Op*/6,
        // MIs[0] Operand 7
        GIM_CheckIsImm, /*MI*/0, /*Op*/7,
        GIM_CheckComplexPattern, /*MI*/0, /*Op*/4, /*Renderer*/GIMT_Encode2(0), GIMT_Encode2(GICP_gi_buf_soffset),
        // (SIbuffer_load:{ *:[v2i16] } v4i32:{ *:[v4i32] }:$rsrc, i32:{ *:[i32] }:$vindex, i32:{ *:[i32] }:$voffset, (BUFSOffset:{ *:[i32] } i32:{ *:[i32] }:$soffset), (timm:{ *:[i32] }):$offset, (timm:{ *:[i32] }):$auxiliary, (timm:{ *:[i1] }))  =>  (BUFFER_LOAD_DWORD_BOTHEN:{ *:[v2i16] } (REG_SEQUENCE:{ *:[i64] } VReg_64:{ *:[i32] }, VGPR_32:{ *:[i32] }:$vindex, sub0:{ *:[i32] }, VGPR_32:{ *:[i32] }:$voffset, sub1:{ *:[i32] }), SReg_128:{ *:[v4i32] }:$rsrc, SCSrc_b32:{ *:[i32] }:$soffset, (timm:{ *:[i32] }):$offset, (extract_cpol:{ *:[i32] } ?:{ *:[i32] }:$auxiliary), (extract_swz:{ *:[i1] } ?:{ *:[i32] }:$auxiliary))
        GIR_MakeTempReg, /*TempRegID*/0, /*TypeID*/GILLT_s64,
        GIR_BuildMI, /*InsnID*/1, /*Opcode*/GIMT_Encode2(TargetOpcode::REG_SEQUENCE),
        GIR_AddTempRegister, /*InsnID*/1, /*TempRegID*/0, /*TempRegFlags*/GIMT_Encode2(RegState::Define),
        GIR_Copy, /*NewInsnID*/1, /*OldInsnID*/0, /*OpIdx*/2, // vindex
        GIR_AddImm8, /*InsnID*/1, /*SubRegIndex*/3,
        GIR_Copy, /*NewInsnID*/1, /*OldInsnID*/0, /*OpIdx*/3, // voffset
        GIR_AddImm8, /*InsnID*/1, /*SubRegIndex*/11,
        GIR_ConstrainOperandRC, /*InsnID*/1, /*Op*/0, GIMT_Encode2(AMDGPU::VReg_64RegClassID),
        GIR_ConstrainOperandRC, /*InsnID*/1, /*Op*/1, GIMT_Encode2(AMDGPU::VGPR_32RegClassID),
        GIR_ConstrainOperandRC, /*InsnID*/1, /*Op*/3, GIMT_Encode2(AMDGPU::VGPR_32RegClassID),
        GIR_BuildMI, /*InsnID*/0, /*Opcode*/GIMT_Encode2(AMDGPU::BUFFER_LOAD_DWORD_BOTHEN),
        GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/0, // DstI[vdata]
        GIR_AddSimpleTempRegister, /*InsnID*/0, /*TempRegID*/0,
        GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/1, // rsrc
        GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/0, // soffset
        GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/5, // offset
        GIR_CustomOperandRenderer, /*InsnID*/0, /*OldInsnID*/0, /*OpIdx*/6, /*OperandRenderer*/GIMT_Encode2(GICR_renderExtractCPol), // auxiliary
        GIR_CustomOperandRenderer, /*InsnID*/0, /*OldInsnID*/0, /*OpIdx*/6, /*OperandRenderer*/GIMT_Encode2(GICR_renderExtractSWZ), // auxiliary
        GIR_MergeMemOperands, /*InsnID*/0, /*NumInsns*/1, /*MergeInsnID's*/0,
        GIR_ConstrainSelectedInstOperands, /*InsnID*/0,
        GIR_EraseFromParent, /*InsnID*/0,
        // GIR_Coverage, 4124,
        GIR_Done,
      // Label 6428: @471238
      GIM_Try, /*On fail goto*//*Label 6429*/ GIMT_Encode4(471345), // Rule ID 4128 //
        // MIs[0] offset
        GIM_CheckIsImm, /*MI*/0, /*Op*/5,
        // MIs[0] auxiliary
        GIM_CheckIsImm, /*MI*/0, /*Op*/6,
        // MIs[0] Operand 7
        GIM_CheckIsImm, /*MI*/0, /*Op*/7,
        GIM_CheckComplexPattern, /*MI*/0, /*Op*/4, /*Renderer*/GIMT_Encode2(0), GIMT_Encode2(GICP_gi_buf_soffset),
        // (SIbuffer_load:{ *:[v2i16] } v4i32:{ *:[v4i32] }:$rsrc, i32:{ *:[i32] }:$vindex, i32:{ *:[i32] }:$voffset, (BUFSOffset:{ *:[i32] } i32:{ *:[i32] }:$soffset), (timm:{ *:[i32] }):$offset, (timm:{ *:[i32] }):$auxiliary, (timm:{ *:[i1] }))  =>  (BUFFER_LOAD_DWORD_VBUFFER_BOTHEN:{ *:[v2i16] } (REG_SEQUENCE:{ *:[i64] } VReg_64:{ *:[i32] }, VGPR_32:{ *:[i32] }:$vindex, sub0:{ *:[i32] }, VGPR_32:{ *:[i32] }:$voffset, sub1:{ *:[i32] }), SReg_128:{ *:[v4i32] }:$rsrc, SCSrc_b32:{ *:[i32] }:$soffset, (timm:{ *:[i32] }):$offset, (extract_cpol:{ *:[i32] } ?:{ *:[i32] }:$auxiliary), (extract_swz:{ *:[i1] } ?:{ *:[i32] }:$auxiliary))
        GIR_MakeTempReg, /*TempRegID*/0, /*TypeID*/GILLT_s64,
        GIR_BuildMI, /*InsnID*/1, /*Opcode*/GIMT_Encode2(TargetOpcode::REG_SEQUENCE),
        GIR_AddTempRegister, /*InsnID*/1, /*TempRegID*/0, /*TempRegFlags*/GIMT_Encode2(RegState::Define),
        GIR_Copy, /*NewInsnID*/1, /*OldInsnID*/0, /*OpIdx*/2, // vindex
        GIR_AddImm8, /*InsnID*/1, /*SubRegIndex*/3,
        GIR_Copy, /*NewInsnID*/1, /*OldInsnID*/0, /*OpIdx*/3, // voffset
        GIR_AddImm8, /*InsnID*/1, /*SubRegIndex*/11,
        GIR_ConstrainOperandRC, /*InsnID*/1, /*Op*/0, GIMT_Encode2(AMDGPU::VReg_64RegClassID),
        GIR_ConstrainOperandRC, /*InsnID*/1, /*Op*/1, GIMT_Encode2(AMDGPU::VGPR_32RegClassID),
        GIR_ConstrainOperandRC, /*InsnID*/1, /*Op*/3, GIMT_Encode2(AMDGPU::VGPR_32RegClassID),
        GIR_BuildMI, /*InsnID*/0, /*Opcode*/GIMT_Encode2(AMDGPU::BUFFER_LOAD_DWORD_VBUFFER_BOTHEN),
        GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/0, // DstI[vdata]
        GIR_AddSimpleTempRegister, /*InsnID*/0, /*TempRegID*/0,
        GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/1, // rsrc
        GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/0, // soffset
        GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/5, // offset
        GIR_CustomOperandRenderer, /*InsnID*/0, /*OldInsnID*/0, /*OpIdx*/6, /*OperandRenderer*/GIMT_Encode2(GICR_renderExtractCPol), // auxiliary
        GIR_CustomOperandRenderer, /*InsnID*/0, /*OldInsnID*/0, /*OpIdx*/6, /*OperandRenderer*/GIMT_Encode2(GICR_renderExtractSWZ), // auxiliary
        GIR_MergeMemOperands, /*InsnID*/0, /*NumInsns*/1, /*MergeInsnID's*/0,
        GIR_ConstrainSelectedInstOperands, /*InsnID*/0,
        GIR_EraseFromParent, /*InsnID*/0,
        // GIR_Coverage, 4128,
        GIR_Done,
      // Label 6429: @471345
      GIM_Try, /*On fail goto*//*Label 6430*/ GIMT_Encode4(471455), // Rule ID 4132 //
        GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasUnrestrictedSOffset),
        // MIs[0] offset
        GIM_CheckIsImm, /*MI*/0, /*Op*/5,
        // MIs[0] auxiliary
        GIM_CheckIsImm, /*MI*/0, /*Op*/6,
        // MIs[0] Operand 7
        GIM_CheckIsImm, /*MI*/0, /*Op*/7,
        GIM_CheckComplexPattern, /*MI*/0, /*Op*/4, /*Renderer*/GIMT_Encode2(0), GIMT_Encode2(GICP_gi_buf_soffset),
        // (SIbuffer_load:{ *:[v2f16] } v4i32:{ *:[v4i32] }:$rsrc, i32:{ *:[i32] }:$vindex, i32:{ *:[i32] }:$voffset, (BUFSOffset:{ *:[i32] } i32:{ *:[i32] }:$soffset), (timm:{ *:[i32] }):$offset, (timm:{ *:[i32] }):$auxiliary, (timm:{ *:[i1] }))  =>  (BUFFER_LOAD_DWORD_BOTHEN:{ *:[v2f16] } (REG_SEQUENCE:{ *:[i64] } VReg_64:{ *:[i32] }, VGPR_32:{ *:[i32] }:$vindex, sub0:{ *:[i32] }, VGPR_32:{ *:[i32] }:$voffset, sub1:{ *:[i32] }), SReg_128:{ *:[v4i32] }:$rsrc, SCSrc_b32:{ *:[i32] }:$soffset, (timm:{ *:[i32] }):$offset, (extract_cpol:{ *:[i32] } ?:{ *:[i32] }:$auxiliary), (extract_swz:{ *:[i1] } ?:{ *:[i32] }:$auxiliary))
        GIR_MakeTempReg, /*TempRegID*/0, /*TypeID*/GILLT_s64,
        GIR_BuildMI, /*InsnID*/1, /*Opcode*/GIMT_Encode2(TargetOpcode::REG_SEQUENCE),
        GIR_AddTempRegister, /*InsnID*/1, /*TempRegID*/0, /*TempRegFlags*/GIMT_Encode2(RegState::Define),
        GIR_Copy, /*NewInsnID*/1, /*OldInsnID*/0, /*OpIdx*/2, // vindex
        GIR_AddImm8, /*InsnID*/1, /*SubRegIndex*/3,
        GIR_Copy, /*NewInsnID*/1, /*OldInsnID*/0, /*OpIdx*/3, // voffset
        GIR_AddImm8, /*InsnID*/1, /*SubRegIndex*/11,
        GIR_ConstrainOperandRC, /*InsnID*/1, /*Op*/0, GIMT_Encode2(AMDGPU::VReg_64RegClassID),
        GIR_ConstrainOperandRC, /*InsnID*/1, /*Op*/1, GIMT_Encode2(AMDGPU::VGPR_32RegClassID),
        GIR_ConstrainOperandRC, /*InsnID*/1, /*Op*/3, GIMT_Encode2(AMDGPU::VGPR_32RegClassID),
        GIR_BuildMI, /*InsnID*/0, /*Opcode*/GIMT_Encode2(AMDGPU::BUFFER_LOAD_DWORD_BOTHEN),
        GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/0, // DstI[vdata]
        GIR_AddSimpleTempRegister, /*InsnID*/0, /*TempRegID*/0,
        GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/1, // rsrc
        GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/0, // soffset
        GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/5, // offset
        GIR_CustomOperandRenderer, /*InsnID*/0, /*OldInsnID*/0, /*OpIdx*/6, /*OperandRenderer*/GIMT_Encode2(GICR_renderExtractCPol), // auxiliary
        GIR_CustomOperandRenderer, /*InsnID*/0, /*OldInsnID*/0, /*OpIdx*/6, /*OperandRenderer*/GIMT_Encode2(GICR_renderExtractSWZ), // auxiliary
        GIR_MergeMemOperands, /*InsnID*/0, /*NumInsns*/1, /*MergeInsnID's*/0,
        GIR_ConstrainSelectedInstOperands, /*InsnID*/0,
        GIR_EraseFromParent, /*InsnID*/0,
        // GIR_Coverage, 4132,
        GIR_Done,
      // Label 6430: @471455
      GIM_Try, /*On fail goto*//*Label 6431*/ GIMT_Encode4(471562), // Rule ID 4136 //
        // MIs[0] offset
        GIM_CheckIsImm, /*MI*/0, /*Op*/5,
        // MIs[0] auxiliary
        GIM_CheckIsImm, /*MI*/0, /*Op*/6,
        // MIs[0] Operand 7
        GIM_CheckIsImm, /*MI*/0, /*Op*/7,
        GIM_CheckComplexPattern, /*MI*/0, /*Op*/4, /*Renderer*/GIMT_Encode2(0), GIMT_Encode2(GICP_gi_buf_soffset),
        // (SIbuffer_load:{ *:[v2f16] } v4i32:{ *:[v4i32] }:$rsrc, i32:{ *:[i32] }:$vindex, i32:{ *:[i32] }:$voffset, (BUFSOffset:{ *:[i32] } i32:{ *:[i32] }:$soffset), (timm:{ *:[i32] }):$offset, (timm:{ *:[i32] }):$auxiliary, (timm:{ *:[i1] }))  =>  (BUFFER_LOAD_DWORD_VBUFFER_BOTHEN:{ *:[v2f16] } (REG_SEQUENCE:{ *:[i64] } VReg_64:{ *:[i32] }, VGPR_32:{ *:[i32] }:$vindex, sub0:{ *:[i32] }, VGPR_32:{ *:[i32] }:$voffset, sub1:{ *:[i32] }), SReg_128:{ *:[v4i32] }:$rsrc, SCSrc_b32:{ *:[i32] }:$soffset, (timm:{ *:[i32] }):$offset, (extract_cpol:{ *:[i32] } ?:{ *:[i32] }:$auxiliary), (extract_swz:{ *:[i1] } ?:{ *:[i32] }:$auxiliary))
        GIR_MakeTempReg, /*TempRegID*/0, /*TypeID*/GILLT_s64,
        GIR_BuildMI, /*InsnID*/1, /*Opcode*/GIMT_Encode2(TargetOpcode::REG_SEQUENCE),
        GIR_AddTempRegister, /*InsnID*/1, /*TempRegID*/0, /*TempRegFlags*/GIMT_Encode2(RegState::Define),
        GIR_Copy, /*NewInsnID*/1, /*OldInsnID*/0, /*OpIdx*/2, // vindex
        GIR_AddImm8, /*InsnID*/1, /*SubRegIndex*/3,
        GIR_Copy, /*NewInsnID*/1, /*OldInsnID*/0, /*OpIdx*/3, // voffset
        GIR_AddImm8, /*InsnID*/1, /*SubRegIndex*/11,
        GIR_ConstrainOperandRC, /*InsnID*/1, /*Op*/0, GIMT_Encode2(AMDGPU::VReg_64RegClassID),
        GIR_ConstrainOperandRC, /*InsnID*/1, /*Op*/1, GIMT_Encode2(AMDGPU::VGPR_32RegClassID),
        GIR_ConstrainOperandRC, /*InsnID*/1, /*Op*/3, GIMT_Encode2(AMDGPU::VGPR_32RegClassID),
        GIR_BuildMI, /*InsnID*/0, /*Opcode*/GIMT_Encode2(AMDGPU::BUFFER_LOAD_DWORD_VBUFFER_BOTHEN),
        GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/0, // DstI[vdata]
        GIR_AddSimpleTempRegister, /*InsnID*/0, /*TempRegID*/0,
        GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/1, // rsrc
        GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/0, // soffset
        GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/5, // offset
        GIR_CustomOperandRenderer, /*InsnID*/0, /*OldInsnID*/0, /*OpIdx*/6, /*OperandRenderer*/GIMT_Encode2(GICR_renderExtractCPol), // auxiliary
        GIR_CustomOperandRenderer, /*InsnID*/0, /*OldInsnID*/0, /*OpIdx*/6, /*OperandRenderer*/GIMT_Encode2(GICR_renderExtractSWZ), // auxiliary
        GIR_MergeMemOperands, /*InsnID*/0, /*NumInsns*/1, /*MergeInsnID's*/0,
        GIR_ConstrainSelectedInstOperands, /*InsnID*/0,
        GIR_EraseFromParent, /*InsnID*/0,
        // GIR_Coverage, 4136,
        GIR_Done,
      // Label 6431: @471562
      GIM_Reject,
    // Label 6415: @471563
    GIM_Reject,
    // Label 6393: @471564
    GIM_Try, /*On fail goto*//*Label 6432*/ GIMT_Encode4(472959),
      GIM_CheckType, /*MI*/0, /*Op*/1, /*Type*/GILLT_v4s32,
      GIM_CheckType, /*MI*/0, /*Op*/2, /*Type*/GILLT_s32,
      GIM_CheckType, /*MI*/0, /*Op*/3, /*Type*/GILLT_s32,
      GIM_CheckType, /*MI*/0, /*Op*/4, /*Type*/GILLT_s32,
      GIM_CheckRegBankForClass, /*MI*/0, /*Op*/0, /*RC*/GIMT_Encode2(AMDGPU::AV_64RegClassID),
      GIM_Try, /*On fail goto*//*Label 6433*/ GIMT_Encode4(471672), // Rule ID 4137 //
        GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasUnrestrictedSOffset),
        GIM_CheckConstantInt8, /*MI*/0, /*Op*/2, 0,
        GIM_CheckConstantInt8, /*MI*/0, /*Op*/3, 0,
        // MIs[0] offset
        GIM_CheckIsImm, /*MI*/0, /*Op*/5,
        // MIs[0] auxiliary
        GIM_CheckIsImm, /*MI*/0, /*Op*/6,
        // MIs[0] Operand 7
        GIM_CheckLiteralInt, /*MI*/0, /*Op*/7, GIMT_Encode8(0),
        GIM_CheckComplexPattern, /*MI*/0, /*Op*/4, /*Renderer*/GIMT_Encode2(0), GIMT_Encode2(GICP_gi_buf_soffset),
        // (SIbuffer_load:{ *:[v2f32] } v4i32:{ *:[v4i32] }:$rsrc, 0:{ *:[i32] }, 0:{ *:[i32] }, (BUFSOffset:{ *:[i32] } i32:{ *:[i32] }:$soffset), (timm:{ *:[i32] }):$offset, (timm:{ *:[i32] }):$auxiliary, 0:{ *:[i1] })  =>  (BUFFER_LOAD_DWORDX2_OFFSET:{ *:[v2f32] } SReg_128:{ *:[v4i32] }:$rsrc, SCSrc_b32:{ *:[i32] }:$soffset, (timm:{ *:[i32] }):$offset, (extract_cpol:{ *:[i32] } ?:{ *:[i32] }:$auxiliary), (extract_swz:{ *:[i1] } ?:{ *:[i32] }:$auxiliary))
        GIR_BuildMI, /*InsnID*/0, /*Opcode*/GIMT_Encode2(AMDGPU::BUFFER_LOAD_DWORDX2_OFFSET),
        GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/0, // DstI[vdata]
        GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/1, // rsrc
        GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/0, // soffset
        GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/5, // offset
        GIR_CustomOperandRenderer, /*InsnID*/0, /*OldInsnID*/0, /*OpIdx*/6, /*OperandRenderer*/GIMT_Encode2(GICR_renderExtractCPol), // auxiliary
        GIR_CustomOperandRenderer, /*InsnID*/0, /*OldInsnID*/0, /*OpIdx*/6, /*OperandRenderer*/GIMT_Encode2(GICR_renderExtractSWZ), // auxiliary
        GIR_MergeMemOperands, /*InsnID*/0, /*NumInsns*/1, /*MergeInsnID's*/0,
        GIR_ConstrainSelectedInstOperands, /*InsnID*/0,
        GIR_EraseFromParent, /*InsnID*/0,
        // GIR_Coverage, 4137,
        GIR_Done,
      // Label 6433: @471672
      GIM_Try, /*On fail goto*//*Label 6434*/ GIMT_Encode4(471751), // Rule ID 4141 //
        GIM_CheckConstantInt8, /*MI*/0, /*Op*/2, 0,
        GIM_CheckConstantInt8, /*MI*/0, /*Op*/3, 0,
        // MIs[0] offset
        GIM_CheckIsImm, /*MI*/0, /*Op*/5,
        // MIs[0] auxiliary
        GIM_CheckIsImm, /*MI*/0, /*Op*/6,
        // MIs[0] Operand 7
        GIM_CheckLiteralInt, /*MI*/0, /*Op*/7, GIMT_Encode8(0),
        GIM_CheckComplexPattern, /*MI*/0, /*Op*/4, /*Renderer*/GIMT_Encode2(0), GIMT_Encode2(GICP_gi_buf_soffset),
        // (SIbuffer_load:{ *:[v2f32] } v4i32:{ *:[v4i32] }:$rsrc, 0:{ *:[i32] }, 0:{ *:[i32] }, (BUFSOffset:{ *:[i32] } i32:{ *:[i32] }:$soffset), (timm:{ *:[i32] }):$offset, (timm:{ *:[i32] }):$auxiliary, 0:{ *:[i1] })  =>  (BUFFER_LOAD_DWORDX2_VBUFFER_OFFSET:{ *:[v2f32] } SReg_128:{ *:[v4i32] }:$rsrc, SCSrc_b32:{ *:[i32] }:$soffset, (timm:{ *:[i32] }):$offset, (extract_cpol:{ *:[i32] } ?:{ *:[i32] }:$auxiliary), (extract_swz:{ *:[i1] } ?:{ *:[i32] }:$auxiliary))
        GIR_BuildMI, /*InsnID*/0, /*Opcode*/GIMT_Encode2(AMDGPU::BUFFER_LOAD_DWORDX2_VBUFFER_OFFSET),
        GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/0, // DstI[vdata]
        GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/1, // rsrc
        GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/0, // soffset
        GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/5, // offset
        GIR_CustomOperandRenderer, /*InsnID*/0, /*OldInsnID*/0, /*OpIdx*/6, /*OperandRenderer*/GIMT_Encode2(GICR_renderExtractCPol), // auxiliary
        GIR_CustomOperandRenderer, /*InsnID*/0, /*OldInsnID*/0, /*OpIdx*/6, /*OperandRenderer*/GIMT_Encode2(GICR_renderExtractSWZ), // auxiliary
        GIR_MergeMemOperands, /*InsnID*/0, /*NumInsns*/1, /*MergeInsnID's*/0,
        GIR_ConstrainSelectedInstOperands, /*InsnID*/0,
        GIR_EraseFromParent, /*InsnID*/0,
        // GIR_Coverage, 4141,
        GIR_Done,
      // Label 6434: @471751
      GIM_Try, /*On fail goto*//*Label 6435*/ GIMT_Encode4(471833), // Rule ID 4145 //
        GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasUnrestrictedSOffset),
        GIM_CheckConstantInt8, /*MI*/0, /*Op*/2, 0,
        GIM_CheckConstantInt8, /*MI*/0, /*Op*/3, 0,
        // MIs[0] offset
        GIM_CheckIsImm, /*MI*/0, /*Op*/5,
        // MIs[0] auxiliary
        GIM_CheckIsImm, /*MI*/0, /*Op*/6,
        // MIs[0] Operand 7
        GIM_CheckLiteralInt, /*MI*/0, /*Op*/7, GIMT_Encode8(0),
        GIM_CheckComplexPattern, /*MI*/0, /*Op*/4, /*Renderer*/GIMT_Encode2(0), GIMT_Encode2(GICP_gi_buf_soffset),
        // (SIbuffer_load:{ *:[v2i32] } v4i32:{ *:[v4i32] }:$rsrc, 0:{ *:[i32] }, 0:{ *:[i32] }, (BUFSOffset:{ *:[i32] } i32:{ *:[i32] }:$soffset), (timm:{ *:[i32] }):$offset, (timm:{ *:[i32] }):$auxiliary, 0:{ *:[i1] })  =>  (BUFFER_LOAD_DWORDX2_OFFSET:{ *:[v2i32] } SReg_128:{ *:[v4i32] }:$rsrc, SCSrc_b32:{ *:[i32] }:$soffset, (timm:{ *:[i32] }):$offset, (extract_cpol:{ *:[i32] } ?:{ *:[i32] }:$auxiliary), (extract_swz:{ *:[i1] } ?:{ *:[i32] }:$auxiliary))
        GIR_BuildMI, /*InsnID*/0, /*Opcode*/GIMT_Encode2(AMDGPU::BUFFER_LOAD_DWORDX2_OFFSET),
        GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/0, // DstI[vdata]
        GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/1, // rsrc
        GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/0, // soffset
        GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/5, // offset
        GIR_CustomOperandRenderer, /*InsnID*/0, /*OldInsnID*/0, /*OpIdx*/6, /*OperandRenderer*/GIMT_Encode2(GICR_renderExtractCPol), // auxiliary
        GIR_CustomOperandRenderer, /*InsnID*/0, /*OldInsnID*/0, /*OpIdx*/6, /*OperandRenderer*/GIMT_Encode2(GICR_renderExtractSWZ), // auxiliary
        GIR_MergeMemOperands, /*InsnID*/0, /*NumInsns*/1, /*MergeInsnID's*/0,
        GIR_ConstrainSelectedInstOperands, /*InsnID*/0,
        GIR_EraseFromParent, /*InsnID*/0,
        // GIR_Coverage, 4145,
        GIR_Done,
      // Label 6435: @471833
      GIM_Try, /*On fail goto*//*Label 6436*/ GIMT_Encode4(471912), // Rule ID 4149 //
        GIM_CheckConstantInt8, /*MI*/0, /*Op*/2, 0,
        GIM_CheckConstantInt8, /*MI*/0, /*Op*/3, 0,
        // MIs[0] offset
        GIM_CheckIsImm, /*MI*/0, /*Op*/5,
        // MIs[0] auxiliary
        GIM_CheckIsImm, /*MI*/0, /*Op*/6,
        // MIs[0] Operand 7
        GIM_CheckLiteralInt, /*MI*/0, /*Op*/7, GIMT_Encode8(0),
        GIM_CheckComplexPattern, /*MI*/0, /*Op*/4, /*Renderer*/GIMT_Encode2(0), GIMT_Encode2(GICP_gi_buf_soffset),
        // (SIbuffer_load:{ *:[v2i32] } v4i32:{ *:[v4i32] }:$rsrc, 0:{ *:[i32] }, 0:{ *:[i32] }, (BUFSOffset:{ *:[i32] } i32:{ *:[i32] }:$soffset), (timm:{ *:[i32] }):$offset, (timm:{ *:[i32] }):$auxiliary, 0:{ *:[i1] })  =>  (BUFFER_LOAD_DWORDX2_VBUFFER_OFFSET:{ *:[v2i32] } SReg_128:{ *:[v4i32] }:$rsrc, SCSrc_b32:{ *:[i32] }:$soffset, (timm:{ *:[i32] }):$offset, (extract_cpol:{ *:[i32] } ?:{ *:[i32] }:$auxiliary), (extract_swz:{ *:[i1] } ?:{ *:[i32] }:$auxiliary))
        GIR_BuildMI, /*InsnID*/0, /*Opcode*/GIMT_Encode2(AMDGPU::BUFFER_LOAD_DWORDX2_VBUFFER_OFFSET),
        GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/0, // DstI[vdata]
        GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/1, // rsrc
        GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/0, // soffset
        GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/5, // offset
        GIR_CustomOperandRenderer, /*InsnID*/0, /*OldInsnID*/0, /*OpIdx*/6, /*OperandRenderer*/GIMT_Encode2(GICR_renderExtractCPol), // auxiliary
        GIR_CustomOperandRenderer, /*InsnID*/0, /*OldInsnID*/0, /*OpIdx*/6, /*OperandRenderer*/GIMT_Encode2(GICR_renderExtractSWZ), // auxiliary
        GIR_MergeMemOperands, /*InsnID*/0, /*NumInsns*/1, /*MergeInsnID's*/0,
        GIR_ConstrainSelectedInstOperands, /*InsnID*/0,
        GIR_EraseFromParent, /*InsnID*/0,
        // GIR_Coverage, 4149,
        GIR_Done,
      // Label 6436: @471912
      GIM_Try, /*On fail goto*//*Label 6437*/ GIMT_Encode4(471994), // Rule ID 4138 //
        GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasUnrestrictedSOffset),
        GIM_CheckConstantInt8, /*MI*/0, /*Op*/2, 0,
        // MIs[0] offset
        GIM_CheckIsImm, /*MI*/0, /*Op*/5,
        // MIs[0] auxiliary
        GIM_CheckIsImm, /*MI*/0, /*Op*/6,
        // MIs[0] Operand 7
        GIM_CheckLiteralInt, /*MI*/0, /*Op*/7, GIMT_Encode8(0),
        GIM_CheckComplexPattern, /*MI*/0, /*Op*/4, /*Renderer*/GIMT_Encode2(0), GIMT_Encode2(GICP_gi_buf_soffset),
        // (SIbuffer_load:{ *:[v2f32] } v4i32:{ *:[v4i32] }:$rsrc, 0:{ *:[i32] }, i32:{ *:[i32] }:$voffset, (BUFSOffset:{ *:[i32] } i32:{ *:[i32] }:$soffset), (timm:{ *:[i32] }):$offset, (timm:{ *:[i32] }):$auxiliary, 0:{ *:[i1] })  =>  (BUFFER_LOAD_DWORDX2_OFFEN:{ *:[v2f32] } VGPR_32:{ *:[i32] }:$voffset, SReg_128:{ *:[v4i32] }:$rsrc, SCSrc_b32:{ *:[i32] }:$soffset, (timm:{ *:[i32] }):$offset, (extract_cpol:{ *:[i32] } ?:{ *:[i32] }:$auxiliary), (extract_swz:{ *:[i1] } ?:{ *:[i32] }:$auxiliary))
        GIR_BuildMI, /*InsnID*/0, /*Opcode*/GIMT_Encode2(AMDGPU::BUFFER_LOAD_DWORDX2_OFFEN),
        GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/0, // DstI[vdata]
        GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/3, // voffset
        GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/1, // rsrc
        GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/0, // soffset
        GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/5, // offset
        GIR_CustomOperandRenderer, /*InsnID*/0, /*OldInsnID*/0, /*OpIdx*/6, /*OperandRenderer*/GIMT_Encode2(GICR_renderExtractCPol), // auxiliary
        GIR_CustomOperandRenderer, /*InsnID*/0, /*OldInsnID*/0, /*OpIdx*/6, /*OperandRenderer*/GIMT_Encode2(GICR_renderExtractSWZ), // auxiliary
        GIR_MergeMemOperands, /*InsnID*/0, /*NumInsns*/1, /*MergeInsnID's*/0,
        GIR_ConstrainSelectedInstOperands, /*InsnID*/0,
        GIR_EraseFromParent, /*InsnID*/0,
        // GIR_Coverage, 4138,
        GIR_Done,
      // Label 6437: @471994
      GIM_Try, /*On fail goto*//*Label 6438*/ GIMT_Encode4(472073), // Rule ID 4142 //
        GIM_CheckConstantInt8, /*MI*/0, /*Op*/2, 0,
        // MIs[0] offset
        GIM_CheckIsImm, /*MI*/0, /*Op*/5,
        // MIs[0] auxiliary
        GIM_CheckIsImm, /*MI*/0, /*Op*/6,
        // MIs[0] Operand 7
        GIM_CheckLiteralInt, /*MI*/0, /*Op*/7, GIMT_Encode8(0),
        GIM_CheckComplexPattern, /*MI*/0, /*Op*/4, /*Renderer*/GIMT_Encode2(0), GIMT_Encode2(GICP_gi_buf_soffset),
        // (SIbuffer_load:{ *:[v2f32] } v4i32:{ *:[v4i32] }:$rsrc, 0:{ *:[i32] }, i32:{ *:[i32] }:$voffset, (BUFSOffset:{ *:[i32] } i32:{ *:[i32] }:$soffset), (timm:{ *:[i32] }):$offset, (timm:{ *:[i32] }):$auxiliary, 0:{ *:[i1] })  =>  (BUFFER_LOAD_DWORDX2_VBUFFER_OFFEN:{ *:[v2f32] } VGPR_32:{ *:[i32] }:$voffset, SReg_128:{ *:[v4i32] }:$rsrc, SCSrc_b32:{ *:[i32] }:$soffset, (timm:{ *:[i32] }):$offset, (extract_cpol:{ *:[i32] } ?:{ *:[i32] }:$auxiliary), (extract_swz:{ *:[i1] } ?:{ *:[i32] }:$auxiliary))
        GIR_BuildMI, /*InsnID*/0, /*Opcode*/GIMT_Encode2(AMDGPU::BUFFER_LOAD_DWORDX2_VBUFFER_OFFEN),
        GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/0, // DstI[vdata]
        GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/3, // voffset
        GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/1, // rsrc
        GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/0, // soffset
        GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/5, // offset
        GIR_CustomOperandRenderer, /*InsnID*/0, /*OldInsnID*/0, /*OpIdx*/6, /*OperandRenderer*/GIMT_Encode2(GICR_renderExtractCPol), // auxiliary
        GIR_CustomOperandRenderer, /*InsnID*/0, /*OldInsnID*/0, /*OpIdx*/6, /*OperandRenderer*/GIMT_Encode2(GICR_renderExtractSWZ), // auxiliary
        GIR_MergeMemOperands, /*InsnID*/0, /*NumInsns*/1, /*MergeInsnID's*/0,
        GIR_ConstrainSelectedInstOperands, /*InsnID*/0,
        GIR_EraseFromParent, /*InsnID*/0,
        // GIR_Coverage, 4142,
        GIR_Done,
      // Label 6438: @472073
      GIM_Try, /*On fail goto*//*Label 6439*/ GIMT_Encode4(472155), // Rule ID 4146 //
        GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasUnrestrictedSOffset),
        GIM_CheckConstantInt8, /*MI*/0, /*Op*/2, 0,
        // MIs[0] offset
        GIM_CheckIsImm, /*MI*/0, /*Op*/5,
        // MIs[0] auxiliary
        GIM_CheckIsImm, /*MI*/0, /*Op*/6,
        // MIs[0] Operand 7
        GIM_CheckLiteralInt, /*MI*/0, /*Op*/7, GIMT_Encode8(0),
        GIM_CheckComplexPattern, /*MI*/0, /*Op*/4, /*Renderer*/GIMT_Encode2(0), GIMT_Encode2(GICP_gi_buf_soffset),
        // (SIbuffer_load:{ *:[v2i32] } v4i32:{ *:[v4i32] }:$rsrc, 0:{ *:[i32] }, i32:{ *:[i32] }:$voffset, (BUFSOffset:{ *:[i32] } i32:{ *:[i32] }:$soffset), (timm:{ *:[i32] }):$offset, (timm:{ *:[i32] }):$auxiliary, 0:{ *:[i1] })  =>  (BUFFER_LOAD_DWORDX2_OFFEN:{ *:[v2i32] } VGPR_32:{ *:[i32] }:$voffset, SReg_128:{ *:[v4i32] }:$rsrc, SCSrc_b32:{ *:[i32] }:$soffset, (timm:{ *:[i32] }):$offset, (extract_cpol:{ *:[i32] } ?:{ *:[i32] }:$auxiliary), (extract_swz:{ *:[i1] } ?:{ *:[i32] }:$auxiliary))
        GIR_BuildMI, /*InsnID*/0, /*Opcode*/GIMT_Encode2(AMDGPU::BUFFER_LOAD_DWORDX2_OFFEN),
        GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/0, // DstI[vdata]
        GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/3, // voffset
        GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/1, // rsrc
        GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/0, // soffset
        GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/5, // offset
        GIR_CustomOperandRenderer, /*InsnID*/0, /*OldInsnID*/0, /*OpIdx*/6, /*OperandRenderer*/GIMT_Encode2(GICR_renderExtractCPol), // auxiliary
        GIR_CustomOperandRenderer, /*InsnID*/0, /*OldInsnID*/0, /*OpIdx*/6, /*OperandRenderer*/GIMT_Encode2(GICR_renderExtractSWZ), // auxiliary
        GIR_MergeMemOperands, /*InsnID*/0, /*NumInsns*/1, /*MergeInsnID's*/0,
        GIR_ConstrainSelectedInstOperands, /*InsnID*/0,
        GIR_EraseFromParent, /*InsnID*/0,
        // GIR_Coverage, 4146,
        GIR_Done,
      // Label 6439: @472155
      GIM_Try, /*On fail goto*//*Label 6440*/ GIMT_Encode4(472234), // Rule ID 4150 //
        GIM_CheckConstantInt8, /*MI*/0, /*Op*/2, 0,
        // MIs[0] offset
        GIM_CheckIsImm, /*MI*/0, /*Op*/5,
        // MIs[0] auxiliary
        GIM_CheckIsImm, /*MI*/0, /*Op*/6,
        // MIs[0] Operand 7
        GIM_CheckLiteralInt, /*MI*/0, /*Op*/7, GIMT_Encode8(0),
        GIM_CheckComplexPattern, /*MI*/0, /*Op*/4, /*Renderer*/GIMT_Encode2(0), GIMT_Encode2(GICP_gi_buf_soffset),
        // (SIbuffer_load:{ *:[v2i32] } v4i32:{ *:[v4i32] }:$rsrc, 0:{ *:[i32] }, i32:{ *:[i32] }:$voffset, (BUFSOffset:{ *:[i32] } i32:{ *:[i32] }:$soffset), (timm:{ *:[i32] }):$offset, (timm:{ *:[i32] }):$auxiliary, 0:{ *:[i1] })  =>  (BUFFER_LOAD_DWORDX2_VBUFFER_OFFEN:{ *:[v2i32] } VGPR_32:{ *:[i32] }:$voffset, SReg_128:{ *:[v4i32] }:$rsrc, SCSrc_b32:{ *:[i32] }:$soffset, (timm:{ *:[i32] }):$offset, (extract_cpol:{ *:[i32] } ?:{ *:[i32] }:$auxiliary), (extract_swz:{ *:[i1] } ?:{ *:[i32] }:$auxiliary))
        GIR_BuildMI, /*InsnID*/0, /*Opcode*/GIMT_Encode2(AMDGPU::BUFFER_LOAD_DWORDX2_VBUFFER_OFFEN),
        GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/0, // DstI[vdata]
        GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/3, // voffset
        GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/1, // rsrc
        GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/0, // soffset
        GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/5, // offset
        GIR_CustomOperandRenderer, /*InsnID*/0, /*OldInsnID*/0, /*OpIdx*/6, /*OperandRenderer*/GIMT_Encode2(GICR_renderExtractCPol), // auxiliary
        GIR_CustomOperandRenderer, /*InsnID*/0, /*OldInsnID*/0, /*OpIdx*/6, /*OperandRenderer*/GIMT_Encode2(GICR_renderExtractSWZ), // auxiliary
        GIR_MergeMemOperands, /*InsnID*/0, /*NumInsns*/1, /*MergeInsnID's*/0,
        GIR_ConstrainSelectedInstOperands, /*InsnID*/0,
        GIR_EraseFromParent, /*InsnID*/0,
        // GIR_Coverage, 4150,
        GIR_Done,
      // Label 6440: @472234
      GIM_Try, /*On fail goto*//*Label 6441*/ GIMT_Encode4(472308), // Rule ID 4139 //
        GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasUnrestrictedSOffset),
        GIM_CheckConstantInt8, /*MI*/0, /*Op*/3, 0,
        // MIs[0] offset
        GIM_CheckIsImm, /*MI*/0, /*Op*/5,
        // MIs[0] auxiliary
        GIM_CheckIsImm, /*MI*/0, /*Op*/6,
        // MIs[0] Operand 7
        GIM_CheckIsImm, /*MI*/0, /*Op*/7,
        GIM_CheckComplexPattern, /*MI*/0, /*Op*/4, /*Renderer*/GIMT_Encode2(0), GIMT_Encode2(GICP_gi_buf_soffset),
        // (SIbuffer_load:{ *:[v2f32] } v4i32:{ *:[v4i32] }:$rsrc, i32:{ *:[i32] }:$vindex, 0:{ *:[i32] }, (BUFSOffset:{ *:[i32] } i32:{ *:[i32] }:$soffset), (timm:{ *:[i32] }):$offset, (timm:{ *:[i32] }):$auxiliary, (timm:{ *:[i1] }))  =>  (BUFFER_LOAD_DWORDX2_IDXEN:{ *:[v2f32] } VGPR_32:{ *:[i32] }:$vindex, SReg_128:{ *:[v4i32] }:$rsrc, SCSrc_b32:{ *:[i32] }:$soffset, (timm:{ *:[i32] }):$offset, (extract_cpol:{ *:[i32] } ?:{ *:[i32] }:$auxiliary), (extract_swz:{ *:[i1] } ?:{ *:[i32] }:$auxiliary))
        GIR_BuildMI, /*InsnID*/0, /*Opcode*/GIMT_Encode2(AMDGPU::BUFFER_LOAD_DWORDX2_IDXEN),
        GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/0, // DstI[vdata]
        GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/2, // vindex
        GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/1, // rsrc
        GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/0, // soffset
        GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/5, // offset
        GIR_CustomOperandRenderer, /*InsnID*/0, /*OldInsnID*/0, /*OpIdx*/6, /*OperandRenderer*/GIMT_Encode2(GICR_renderExtractCPol), // auxiliary
        GIR_CustomOperandRenderer, /*InsnID*/0, /*OldInsnID*/0, /*OpIdx*/6, /*OperandRenderer*/GIMT_Encode2(GICR_renderExtractSWZ), // auxiliary
        GIR_MergeMemOperands, /*InsnID*/0, /*NumInsns*/1, /*MergeInsnID's*/0,
        GIR_ConstrainSelectedInstOperands, /*InsnID*/0,
        GIR_EraseFromParent, /*InsnID*/0,
        // GIR_Coverage, 4139,
        GIR_Done,
      // Label 6441: @472308
      GIM_Try, /*On fail goto*//*Label 6442*/ GIMT_Encode4(472379), // Rule ID 4143 //
        GIM_CheckConstantInt8, /*MI*/0, /*Op*/3, 0,
        // MIs[0] offset
        GIM_CheckIsImm, /*MI*/0, /*Op*/5,
        // MIs[0] auxiliary
        GIM_CheckIsImm, /*MI*/0, /*Op*/6,
        // MIs[0] Operand 7
        GIM_CheckIsImm, /*MI*/0, /*Op*/7,
        GIM_CheckComplexPattern, /*MI*/0, /*Op*/4, /*Renderer*/GIMT_Encode2(0), GIMT_Encode2(GICP_gi_buf_soffset),
        // (SIbuffer_load:{ *:[v2f32] } v4i32:{ *:[v4i32] }:$rsrc, i32:{ *:[i32] }:$vindex, 0:{ *:[i32] }, (BUFSOffset:{ *:[i32] } i32:{ *:[i32] }:$soffset), (timm:{ *:[i32] }):$offset, (timm:{ *:[i32] }):$auxiliary, (timm:{ *:[i1] }))  =>  (BUFFER_LOAD_DWORDX2_VBUFFER_IDXEN:{ *:[v2f32] } VGPR_32:{ *:[i32] }:$vindex, SReg_128:{ *:[v4i32] }:$rsrc, SCSrc_b32:{ *:[i32] }:$soffset, (timm:{ *:[i32] }):$offset, (extract_cpol:{ *:[i32] } ?:{ *:[i32] }:$auxiliary), (extract_swz:{ *:[i1] } ?:{ *:[i32] }:$auxiliary))
        GIR_BuildMI, /*InsnID*/0, /*Opcode*/GIMT_Encode2(AMDGPU::BUFFER_LOAD_DWORDX2_VBUFFER_IDXEN),
        GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/0, // DstI[vdata]
        GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/2, // vindex
        GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/1, // rsrc
        GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/0, // soffset
        GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/5, // offset
        GIR_CustomOperandRenderer, /*InsnID*/0, /*OldInsnID*/0, /*OpIdx*/6, /*OperandRenderer*/GIMT_Encode2(GICR_renderExtractCPol), // auxiliary
        GIR_CustomOperandRenderer, /*InsnID*/0, /*OldInsnID*/0, /*OpIdx*/6, /*OperandRenderer*/GIMT_Encode2(GICR_renderExtractSWZ), // auxiliary
        GIR_MergeMemOperands, /*InsnID*/0, /*NumInsns*/1, /*MergeInsnID's*/0,
        GIR_ConstrainSelectedInstOperands, /*InsnID*/0,
        GIR_EraseFromParent, /*InsnID*/0,
        // GIR_Coverage, 4143,
        GIR_Done,
      // Label 6442: @472379
      GIM_Try, /*On fail goto*//*Label 6443*/ GIMT_Encode4(472453), // Rule ID 4147 //
        GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasUnrestrictedSOffset),
        GIM_CheckConstantInt8, /*MI*/0, /*Op*/3, 0,
        // MIs[0] offset
        GIM_CheckIsImm, /*MI*/0, /*Op*/5,
        // MIs[0] auxiliary
        GIM_CheckIsImm, /*MI*/0, /*Op*/6,
        // MIs[0] Operand 7
        GIM_CheckIsImm, /*MI*/0, /*Op*/7,
        GIM_CheckComplexPattern, /*MI*/0, /*Op*/4, /*Renderer*/GIMT_Encode2(0), GIMT_Encode2(GICP_gi_buf_soffset),
        // (SIbuffer_load:{ *:[v2i32] } v4i32:{ *:[v4i32] }:$rsrc, i32:{ *:[i32] }:$vindex, 0:{ *:[i32] }, (BUFSOffset:{ *:[i32] } i32:{ *:[i32] }:$soffset), (timm:{ *:[i32] }):$offset, (timm:{ *:[i32] }):$auxiliary, (timm:{ *:[i1] }))  =>  (BUFFER_LOAD_DWORDX2_IDXEN:{ *:[v2i32] } VGPR_32:{ *:[i32] }:$vindex, SReg_128:{ *:[v4i32] }:$rsrc, SCSrc_b32:{ *:[i32] }:$soffset, (timm:{ *:[i32] }):$offset, (extract_cpol:{ *:[i32] } ?:{ *:[i32] }:$auxiliary), (extract_swz:{ *:[i1] } ?:{ *:[i32] }:$auxiliary))
        GIR_BuildMI, /*InsnID*/0, /*Opcode*/GIMT_Encode2(AMDGPU::BUFFER_LOAD_DWORDX2_IDXEN),
        GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/0, // DstI[vdata]
        GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/2, // vindex
        GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/1, // rsrc
        GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/0, // soffset
        GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/5, // offset
        GIR_CustomOperandRenderer, /*InsnID*/0, /*OldInsnID*/0, /*OpIdx*/6, /*OperandRenderer*/GIMT_Encode2(GICR_renderExtractCPol), // auxiliary
        GIR_CustomOperandRenderer, /*InsnID*/0, /*OldInsnID*/0, /*OpIdx*/6, /*OperandRenderer*/GIMT_Encode2(GICR_renderExtractSWZ), // auxiliary
        GIR_MergeMemOperands, /*InsnID*/0, /*NumInsns*/1, /*MergeInsnID's*/0,
        GIR_ConstrainSelectedInstOperands, /*InsnID*/0,
        GIR_EraseFromParent, /*InsnID*/0,
        // GIR_Coverage, 4147,
        GIR_Done,
      // Label 6443: @472453
      GIM_Try, /*On fail goto*//*Label 6444*/ GIMT_Encode4(472524), // Rule ID 4151 //
        GIM_CheckConstantInt8, /*MI*/0, /*Op*/3, 0,
        // MIs[0] offset
        GIM_CheckIsImm, /*MI*/0, /*Op*/5,
        // MIs[0] auxiliary
        GIM_CheckIsImm, /*MI*/0, /*Op*/6,
        // MIs[0] Operand 7
        GIM_CheckIsImm, /*MI*/0, /*Op*/7,
        GIM_CheckComplexPattern, /*MI*/0, /*Op*/4, /*Renderer*/GIMT_Encode2(0), GIMT_Encode2(GICP_gi_buf_soffset),
        // (SIbuffer_load:{ *:[v2i32] } v4i32:{ *:[v4i32] }:$rsrc, i32:{ *:[i32] }:$vindex, 0:{ *:[i32] }, (BUFSOffset:{ *:[i32] } i32:{ *:[i32] }:$soffset), (timm:{ *:[i32] }):$offset, (timm:{ *:[i32] }):$auxiliary, (timm:{ *:[i1] }))  =>  (BUFFER_LOAD_DWORDX2_VBUFFER_IDXEN:{ *:[v2i32] } VGPR_32:{ *:[i32] }:$vindex, SReg_128:{ *:[v4i32] }:$rsrc, SCSrc_b32:{ *:[i32] }:$soffset, (timm:{ *:[i32] }):$offset, (extract_cpol:{ *:[i32] } ?:{ *:[i32] }:$auxiliary), (extract_swz:{ *:[i1] } ?:{ *:[i32] }:$auxiliary))
        GIR_BuildMI, /*InsnID*/0, /*Opcode*/GIMT_Encode2(AMDGPU::BUFFER_LOAD_DWORDX2_VBUFFER_IDXEN),
        GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/0, // DstI[vdata]
        GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/2, // vindex
        GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/1, // rsrc
        GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/0, // soffset
        GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/5, // offset
        GIR_CustomOperandRenderer, /*InsnID*/0, /*OldInsnID*/0, /*OpIdx*/6, /*OperandRenderer*/GIMT_Encode2(GICR_renderExtractCPol), // auxiliary
        GIR_CustomOperandRenderer, /*InsnID*/0, /*OldInsnID*/0, /*OpIdx*/6, /*OperandRenderer*/GIMT_Encode2(GICR_renderExtractSWZ), // auxiliary
        GIR_MergeMemOperands, /*InsnID*/0, /*NumInsns*/1, /*MergeInsnID's*/0,
        GIR_ConstrainSelectedInstOperands, /*InsnID*/0,
        GIR_EraseFromParent, /*InsnID*/0,
        // GIR_Coverage, 4151,
        GIR_Done,
      // Label 6444: @472524
      GIM_Try, /*On fail goto*//*Label 6445*/ GIMT_Encode4(472634), // Rule ID 4140 //
        GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasUnrestrictedSOffset),
        // MIs[0] offset
        GIM_CheckIsImm, /*MI*/0, /*Op*/5,
        // MIs[0] auxiliary
        GIM_CheckIsImm, /*MI*/0, /*Op*/6,
        // MIs[0] Operand 7
        GIM_CheckIsImm, /*MI*/0, /*Op*/7,
        GIM_CheckComplexPattern, /*MI*/0, /*Op*/4, /*Renderer*/GIMT_Encode2(0), GIMT_Encode2(GICP_gi_buf_soffset),
        // (SIbuffer_load:{ *:[v2f32] } v4i32:{ *:[v4i32] }:$rsrc, i32:{ *:[i32] }:$vindex, i32:{ *:[i32] }:$voffset, (BUFSOffset:{ *:[i32] } i32:{ *:[i32] }:$soffset), (timm:{ *:[i32] }):$offset, (timm:{ *:[i32] }):$auxiliary, (timm:{ *:[i1] }))  =>  (BUFFER_LOAD_DWORDX2_BOTHEN:{ *:[v2f32] } (REG_SEQUENCE:{ *:[i64] } VReg_64:{ *:[i32] }, VGPR_32:{ *:[i32] }:$vindex, sub0:{ *:[i32] }, VGPR_32:{ *:[i32] }:$voffset, sub1:{ *:[i32] }), SReg_128:{ *:[v4i32] }:$rsrc, SCSrc_b32:{ *:[i32] }:$soffset, (timm:{ *:[i32] }):$offset, (extract_cpol:{ *:[i32] } ?:{ *:[i32] }:$auxiliary), (extract_swz:{ *:[i1] } ?:{ *:[i32] }:$auxiliary))
        GIR_MakeTempReg, /*TempRegID*/0, /*TypeID*/GILLT_s64,
        GIR_BuildMI, /*InsnID*/1, /*Opcode*/GIMT_Encode2(TargetOpcode::REG_SEQUENCE),
        GIR_AddTempRegister, /*InsnID*/1, /*TempRegID*/0, /*TempRegFlags*/GIMT_Encode2(RegState::Define),
        GIR_Copy, /*NewInsnID*/1, /*OldInsnID*/0, /*OpIdx*/2, // vindex
        GIR_AddImm8, /*InsnID*/1, /*SubRegIndex*/3,
        GIR_Copy, /*NewInsnID*/1, /*OldInsnID*/0, /*OpIdx*/3, // voffset
        GIR_AddImm8, /*InsnID*/1, /*SubRegIndex*/11,
        GIR_ConstrainOperandRC, /*InsnID*/1, /*Op*/0, GIMT_Encode2(AMDGPU::VReg_64RegClassID),
        GIR_ConstrainOperandRC, /*InsnID*/1, /*Op*/1, GIMT_Encode2(AMDGPU::VGPR_32RegClassID),
        GIR_ConstrainOperandRC, /*InsnID*/1, /*Op*/3, GIMT_Encode2(AMDGPU::VGPR_32RegClassID),
        GIR_BuildMI, /*InsnID*/0, /*Opcode*/GIMT_Encode2(AMDGPU::BUFFER_LOAD_DWORDX2_BOTHEN),
        GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/0, // DstI[vdata]
        GIR_AddSimpleTempRegister, /*InsnID*/0, /*TempRegID*/0,
        GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/1, // rsrc
        GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/0, // soffset
        GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/5, // offset
        GIR_CustomOperandRenderer, /*InsnID*/0, /*OldInsnID*/0, /*OpIdx*/6, /*OperandRenderer*/GIMT_Encode2(GICR_renderExtractCPol), // auxiliary
        GIR_CustomOperandRenderer, /*InsnID*/0, /*OldInsnID*/0, /*OpIdx*/6, /*OperandRenderer*/GIMT_Encode2(GICR_renderExtractSWZ), // auxiliary
        GIR_MergeMemOperands, /*InsnID*/0, /*NumInsns*/1, /*MergeInsnID's*/0,
        GIR_ConstrainSelectedInstOperands, /*InsnID*/0,
        GIR_EraseFromParent, /*InsnID*/0,
        // GIR_Coverage, 4140,
        GIR_Done,
      // Label 6445: @472634
      GIM_Try, /*On fail goto*//*Label 6446*/ GIMT_Encode4(472741), // Rule ID 4144 //
        // MIs[0] offset
        GIM_CheckIsImm, /*MI*/0, /*Op*/5,
        // MIs[0] auxiliary
        GIM_CheckIsImm, /*MI*/0, /*Op*/6,
        // MIs[0] Operand 7
        GIM_CheckIsImm, /*MI*/0, /*Op*/7,
        GIM_CheckComplexPattern, /*MI*/0, /*Op*/4, /*Renderer*/GIMT_Encode2(0), GIMT_Encode2(GICP_gi_buf_soffset),
        // (SIbuffer_load:{ *:[v2f32] } v4i32:{ *:[v4i32] }:$rsrc, i32:{ *:[i32] }:$vindex, i32:{ *:[i32] }:$voffset, (BUFSOffset:{ *:[i32] } i32:{ *:[i32] }:$soffset), (timm:{ *:[i32] }):$offset, (timm:{ *:[i32] }):$auxiliary, (timm:{ *:[i1] }))  =>  (BUFFER_LOAD_DWORDX2_VBUFFER_BOTHEN:{ *:[v2f32] } (REG_SEQUENCE:{ *:[i64] } VReg_64:{ *:[i32] }, VGPR_32:{ *:[i32] }:$vindex, sub0:{ *:[i32] }, VGPR_32:{ *:[i32] }:$voffset, sub1:{ *:[i32] }), SReg_128:{ *:[v4i32] }:$rsrc, SCSrc_b32:{ *:[i32] }:$soffset, (timm:{ *:[i32] }):$offset, (extract_cpol:{ *:[i32] } ?:{ *:[i32] }:$auxiliary), (extract_swz:{ *:[i1] } ?:{ *:[i32] }:$auxiliary))
        GIR_MakeTempReg, /*TempRegID*/0, /*TypeID*/GILLT_s64,
        GIR_BuildMI, /*InsnID*/1, /*Opcode*/GIMT_Encode2(TargetOpcode::REG_SEQUENCE),
        GIR_AddTempRegister, /*InsnID*/1, /*TempRegID*/0, /*TempRegFlags*/GIMT_Encode2(RegState::Define),
        GIR_Copy, /*NewInsnID*/1, /*OldInsnID*/0, /*OpIdx*/2, // vindex
        GIR_AddImm8, /*InsnID*/1, /*SubRegIndex*/3,
        GIR_Copy, /*NewInsnID*/1, /*OldInsnID*/0, /*OpIdx*/3, // voffset
        GIR_AddImm8, /*InsnID*/1, /*SubRegIndex*/11,
        GIR_ConstrainOperandRC, /*InsnID*/1, /*Op*/0, GIMT_Encode2(AMDGPU::VReg_64RegClassID),
        GIR_ConstrainOperandRC, /*InsnID*/1, /*Op*/1, GIMT_Encode2(AMDGPU::VGPR_32RegClassID),
        GIR_ConstrainOperandRC, /*InsnID*/1, /*Op*/3, GIMT_Encode2(AMDGPU::VGPR_32RegClassID),
        GIR_BuildMI, /*InsnID*/0, /*Opcode*/GIMT_Encode2(AMDGPU::BUFFER_LOAD_DWORDX2_VBUFFER_BOTHEN),
        GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/0, // DstI[vdata]
        GIR_AddSimpleTempRegister, /*InsnID*/0, /*TempRegID*/0,
        GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/1, // rsrc
        GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/0, // soffset
        GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/5, // offset
        GIR_CustomOperandRenderer, /*InsnID*/0, /*OldInsnID*/0, /*OpIdx*/6, /*OperandRenderer*/GIMT_Encode2(GICR_renderExtractCPol), // auxiliary
        GIR_CustomOperandRenderer, /*InsnID*/0, /*OldInsnID*/0, /*OpIdx*/6, /*OperandRenderer*/GIMT_Encode2(GICR_renderExtractSWZ), // auxiliary
        GIR_MergeMemOperands, /*InsnID*/0, /*NumInsns*/1, /*MergeInsnID's*/0,
        GIR_ConstrainSelectedInstOperands, /*InsnID*/0,
        GIR_EraseFromParent, /*InsnID*/0,
        // GIR_Coverage, 4144,
        GIR_Done,
      // Label 6446: @472741
      GIM_Try, /*On fail goto*//*Label 6447*/ GIMT_Encode4(472851), // Rule ID 4148 //
        GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasUnrestrictedSOffset),
        // MIs[0] offset
        GIM_CheckIsImm, /*MI*/0, /*Op*/5,
        // MIs[0] auxiliary
        GIM_CheckIsImm, /*MI*/0, /*Op*/6,
        // MIs[0] Operand 7
        GIM_CheckIsImm, /*MI*/0, /*Op*/7,
        GIM_CheckComplexPattern, /*MI*/0, /*Op*/4, /*Renderer*/GIMT_Encode2(0), GIMT_Encode2(GICP_gi_buf_soffset),
        // (SIbuffer_load:{ *:[v2i32] } v4i32:{ *:[v4i32] }:$rsrc, i32:{ *:[i32] }:$vindex, i32:{ *:[i32] }:$voffset, (BUFSOffset:{ *:[i32] } i32:{ *:[i32] }:$soffset), (timm:{ *:[i32] }):$offset, (timm:{ *:[i32] }):$auxiliary, (timm:{ *:[i1] }))  =>  (BUFFER_LOAD_DWORDX2_BOTHEN:{ *:[v2i32] } (REG_SEQUENCE:{ *:[i64] } VReg_64:{ *:[i32] }, VGPR_32:{ *:[i32] }:$vindex, sub0:{ *:[i32] }, VGPR_32:{ *:[i32] }:$voffset, sub1:{ *:[i32] }), SReg_128:{ *:[v4i32] }:$rsrc, SCSrc_b32:{ *:[i32] }:$soffset, (timm:{ *:[i32] }):$offset, (extract_cpol:{ *:[i32] } ?:{ *:[i32] }:$auxiliary), (extract_swz:{ *:[i1] } ?:{ *:[i32] }:$auxiliary))
        GIR_MakeTempReg, /*TempRegID*/0, /*TypeID*/GILLT_s64,
        GIR_BuildMI, /*InsnID*/1, /*Opcode*/GIMT_Encode2(TargetOpcode::REG_SEQUENCE),
        GIR_AddTempRegister, /*InsnID*/1, /*TempRegID*/0, /*TempRegFlags*/GIMT_Encode2(RegState::Define),
        GIR_Copy, /*NewInsnID*/1, /*OldInsnID*/0, /*OpIdx*/2, // vindex
        GIR_AddImm8, /*InsnID*/1, /*SubRegIndex*/3,
        GIR_Copy, /*NewInsnID*/1, /*OldInsnID*/0, /*OpIdx*/3, // voffset
        GIR_AddImm8, /*InsnID*/1, /*SubRegIndex*/11,
        GIR_ConstrainOperandRC, /*InsnID*/1, /*Op*/0, GIMT_Encode2(AMDGPU::VReg_64RegClassID),
        GIR_ConstrainOperandRC, /*InsnID*/1, /*Op*/1, GIMT_Encode2(AMDGPU::VGPR_32RegClassID),
        GIR_ConstrainOperandRC, /*InsnID*/1, /*Op*/3, GIMT_Encode2(AMDGPU::VGPR_32RegClassID),
        GIR_BuildMI, /*InsnID*/0, /*Opcode*/GIMT_Encode2(AMDGPU::BUFFER_LOAD_DWORDX2_BOTHEN),
        GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/0, // DstI[vdata]
        GIR_AddSimpleTempRegister, /*InsnID*/0, /*TempRegID*/0,
        GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/1, // rsrc
        GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/0, // soffset
        GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/5, // offset
        GIR_CustomOperandRenderer, /*InsnID*/0, /*OldInsnID*/0, /*OpIdx*/6, /*OperandRenderer*/GIMT_Encode2(GICR_renderExtractCPol), // auxiliary
        GIR_CustomOperandRenderer, /*InsnID*/0, /*OldInsnID*/0, /*OpIdx*/6, /*OperandRenderer*/GIMT_Encode2(GICR_renderExtractSWZ), // auxiliary
        GIR_MergeMemOperands, /*InsnID*/0, /*NumInsns*/1, /*MergeInsnID's*/0,
        GIR_ConstrainSelectedInstOperands, /*InsnID*/0,
        GIR_EraseFromParent, /*InsnID*/0,
        // GIR_Coverage, 4148,
        GIR_Done,
      // Label 6447: @472851
      GIM_Try, /*On fail goto*//*Label 6448*/ GIMT_Encode4(472958), // Rule ID 4152 //
        // MIs[0] offset
        GIM_CheckIsImm, /*MI*/0, /*Op*/5,
        // MIs[0] auxiliary
        GIM_CheckIsImm, /*MI*/0, /*Op*/6,
        // MIs[0] Operand 7
        GIM_CheckIsImm, /*MI*/0, /*Op*/7,
        GIM_CheckComplexPattern, /*MI*/0, /*Op*/4, /*Renderer*/GIMT_Encode2(0), GIMT_Encode2(GICP_gi_buf_soffset),
        // (SIbuffer_load:{ *:[v2i32] } v4i32:{ *:[v4i32] }:$rsrc, i32:{ *:[i32] }:$vindex, i32:{ *:[i32] }:$voffset, (BUFSOffset:{ *:[i32] } i32:{ *:[i32] }:$soffset), (timm:{ *:[i32] }):$offset, (timm:{ *:[i32] }):$auxiliary, (timm:{ *:[i1] }))  =>  (BUFFER_LOAD_DWORDX2_VBUFFER_BOTHEN:{ *:[v2i32] } (REG_SEQUENCE:{ *:[i64] } VReg_64:{ *:[i32] }, VGPR_32:{ *:[i32] }:$vindex, sub0:{ *:[i32] }, VGPR_32:{ *:[i32] }:$voffset, sub1:{ *:[i32] }), SReg_128:{ *:[v4i32] }:$rsrc, SCSrc_b32:{ *:[i32] }:$soffset, (timm:{ *:[i32] }):$offset, (extract_cpol:{ *:[i32] } ?:{ *:[i32] }:$auxiliary), (extract_swz:{ *:[i1] } ?:{ *:[i32] }:$auxiliary))
        GIR_MakeTempReg, /*TempRegID*/0, /*TypeID*/GILLT_s64,
        GIR_BuildMI, /*InsnID*/1, /*Opcode*/GIMT_Encode2(TargetOpcode::REG_SEQUENCE),
        GIR_AddTempRegister, /*InsnID*/1, /*TempRegID*/0, /*TempRegFlags*/GIMT_Encode2(RegState::Define),
        GIR_Copy, /*NewInsnID*/1, /*OldInsnID*/0, /*OpIdx*/2, // vindex
        GIR_AddImm8, /*InsnID*/1, /*SubRegIndex*/3,
        GIR_Copy, /*NewInsnID*/1, /*OldInsnID*/0, /*OpIdx*/3, // voffset
        GIR_AddImm8, /*InsnID*/1, /*SubRegIndex*/11,
        GIR_ConstrainOperandRC, /*InsnID*/1, /*Op*/0, GIMT_Encode2(AMDGPU::VReg_64RegClassID),
        GIR_ConstrainOperandRC, /*InsnID*/1, /*Op*/1, GIMT_Encode2(AMDGPU::VGPR_32RegClassID),
        GIR_ConstrainOperandRC, /*InsnID*/1, /*Op*/3, GIMT_Encode2(AMDGPU::VGPR_32RegClassID),
        GIR_BuildMI, /*InsnID*/0, /*Opcode*/GIMT_Encode2(AMDGPU::BUFFER_LOAD_DWORDX2_VBUFFER_BOTHEN),
        GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/0, // DstI[vdata]
        GIR_AddSimpleTempRegister, /*InsnID*/0, /*TempRegID*/0,
        GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/1, // rsrc
        GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/0, // soffset
        GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/5, // offset
        GIR_CustomOperandRenderer, /*InsnID*/0, /*OldInsnID*/0, /*OpIdx*/6, /*OperandRenderer*/GIMT_Encode2(GICR_renderExtractCPol), // auxiliary
        GIR_CustomOperandRenderer, /*InsnID*/0, /*OldInsnID*/0, /*OpIdx*/6, /*OperandRenderer*/GIMT_Encode2(GICR_renderExtractSWZ), // auxiliary
        GIR_MergeMemOperands, /*InsnID*/0, /*NumInsns*/1, /*MergeInsnID's*/0,
        GIR_ConstrainSelectedInstOperands, /*InsnID*/0,
        GIR_EraseFromParent, /*InsnID*/0,
        // GIR_Coverage, 4152,
        GIR_Done,
      // Label 6448: @472958
      GIM_Reject,
    // Label 6432: @472959
    GIM_Reject,
    // Label 6394: @472960
    GIM_Try, /*On fail goto*//*Label 6449*/ GIMT_Encode4(474355),
      GIM_CheckType, /*MI*/0, /*Op*/1, /*Type*/GILLT_v4s32,
      GIM_CheckType, /*MI*/0, /*Op*/2, /*Type*/GILLT_s32,
      GIM_CheckType, /*MI*/0, /*Op*/3, /*Type*/GILLT_s32,
      GIM_CheckType, /*MI*/0, /*Op*/4, /*Type*/GILLT_s32,
      GIM_CheckRegBankForClass, /*MI*/0, /*Op*/0, /*RC*/GIMT_Encode2(AMDGPU::AV_96RegClassID),
      GIM_Try, /*On fail goto*//*Label 6450*/ GIMT_Encode4(473068), // Rule ID 4169 //
        GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasUnrestrictedSOffset),
        GIM_CheckConstantInt8, /*MI*/0, /*Op*/2, 0,
        GIM_CheckConstantInt8, /*MI*/0, /*Op*/3, 0,
        // MIs[0] offset
        GIM_CheckIsImm, /*MI*/0, /*Op*/5,
        // MIs[0] auxiliary
        GIM_CheckIsImm, /*MI*/0, /*Op*/6,
        // MIs[0] Operand 7
        GIM_CheckLiteralInt, /*MI*/0, /*Op*/7, GIMT_Encode8(0),
        GIM_CheckComplexPattern, /*MI*/0, /*Op*/4, /*Renderer*/GIMT_Encode2(0), GIMT_Encode2(GICP_gi_buf_soffset),
        // (SIbuffer_load:{ *:[v3f32] } v4i32:{ *:[v4i32] }:$rsrc, 0:{ *:[i32] }, 0:{ *:[i32] }, (BUFSOffset:{ *:[i32] } i32:{ *:[i32] }:$soffset), (timm:{ *:[i32] }):$offset, (timm:{ *:[i32] }):$auxiliary, 0:{ *:[i1] })  =>  (BUFFER_LOAD_DWORDX3_OFFSET:{ *:[v3f32] } SReg_128:{ *:[v4i32] }:$rsrc, SCSrc_b32:{ *:[i32] }:$soffset, (timm:{ *:[i32] }):$offset, (extract_cpol:{ *:[i32] } ?:{ *:[i32] }:$auxiliary), (extract_swz:{ *:[i1] } ?:{ *:[i32] }:$auxiliary))
        GIR_BuildMI, /*InsnID*/0, /*Opcode*/GIMT_Encode2(AMDGPU::BUFFER_LOAD_DWORDX3_OFFSET),
        GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/0, // DstI[vdata]
        GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/1, // rsrc
        GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/0, // soffset
        GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/5, // offset
        GIR_CustomOperandRenderer, /*InsnID*/0, /*OldInsnID*/0, /*OpIdx*/6, /*OperandRenderer*/GIMT_Encode2(GICR_renderExtractCPol), // auxiliary
        GIR_CustomOperandRenderer, /*InsnID*/0, /*OldInsnID*/0, /*OpIdx*/6, /*OperandRenderer*/GIMT_Encode2(GICR_renderExtractSWZ), // auxiliary
        GIR_MergeMemOperands, /*InsnID*/0, /*NumInsns*/1, /*MergeInsnID's*/0,
        GIR_ConstrainSelectedInstOperands, /*InsnID*/0,
        GIR_EraseFromParent, /*InsnID*/0,
        // GIR_Coverage, 4169,
        GIR_Done,
      // Label 6450: @473068
      GIM_Try, /*On fail goto*//*Label 6451*/ GIMT_Encode4(473147), // Rule ID 4173 //
        GIM_CheckConstantInt8, /*MI*/0, /*Op*/2, 0,
        GIM_CheckConstantInt8, /*MI*/0, /*Op*/3, 0,
        // MIs[0] offset
        GIM_CheckIsImm, /*MI*/0, /*Op*/5,
        // MIs[0] auxiliary
        GIM_CheckIsImm, /*MI*/0, /*Op*/6,
        // MIs[0] Operand 7
        GIM_CheckLiteralInt, /*MI*/0, /*Op*/7, GIMT_Encode8(0),
        GIM_CheckComplexPattern, /*MI*/0, /*Op*/4, /*Renderer*/GIMT_Encode2(0), GIMT_Encode2(GICP_gi_buf_soffset),
        // (SIbuffer_load:{ *:[v3f32] } v4i32:{ *:[v4i32] }:$rsrc, 0:{ *:[i32] }, 0:{ *:[i32] }, (BUFSOffset:{ *:[i32] } i32:{ *:[i32] }:$soffset), (timm:{ *:[i32] }):$offset, (timm:{ *:[i32] }):$auxiliary, 0:{ *:[i1] })  =>  (BUFFER_LOAD_DWORDX3_VBUFFER_OFFSET:{ *:[v3f32] } SReg_128:{ *:[v4i32] }:$rsrc, SCSrc_b32:{ *:[i32] }:$soffset, (timm:{ *:[i32] }):$offset, (extract_cpol:{ *:[i32] } ?:{ *:[i32] }:$auxiliary), (extract_swz:{ *:[i1] } ?:{ *:[i32] }:$auxiliary))
        GIR_BuildMI, /*InsnID*/0, /*Opcode*/GIMT_Encode2(AMDGPU::BUFFER_LOAD_DWORDX3_VBUFFER_OFFSET),
        GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/0, // DstI[vdata]
        GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/1, // rsrc
        GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/0, // soffset
        GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/5, // offset
        GIR_CustomOperandRenderer, /*InsnID*/0, /*OldInsnID*/0, /*OpIdx*/6, /*OperandRenderer*/GIMT_Encode2(GICR_renderExtractCPol), // auxiliary
        GIR_CustomOperandRenderer, /*InsnID*/0, /*OldInsnID*/0, /*OpIdx*/6, /*OperandRenderer*/GIMT_Encode2(GICR_renderExtractSWZ), // auxiliary
        GIR_MergeMemOperands, /*InsnID*/0, /*NumInsns*/1, /*MergeInsnID's*/0,
        GIR_ConstrainSelectedInstOperands, /*InsnID*/0,
        GIR_EraseFromParent, /*InsnID*/0,
        // GIR_Coverage, 4173,
        GIR_Done,
      // Label 6451: @473147
      GIM_Try, /*On fail goto*//*Label 6452*/ GIMT_Encode4(473229), // Rule ID 4177 //
        GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasUnrestrictedSOffset),
        GIM_CheckConstantInt8, /*MI*/0, /*Op*/2, 0,
        GIM_CheckConstantInt8, /*MI*/0, /*Op*/3, 0,
        // MIs[0] offset
        GIM_CheckIsImm, /*MI*/0, /*Op*/5,
        // MIs[0] auxiliary
        GIM_CheckIsImm, /*MI*/0, /*Op*/6,
        // MIs[0] Operand 7
        GIM_CheckLiteralInt, /*MI*/0, /*Op*/7, GIMT_Encode8(0),
        GIM_CheckComplexPattern, /*MI*/0, /*Op*/4, /*Renderer*/GIMT_Encode2(0), GIMT_Encode2(GICP_gi_buf_soffset),
        // (SIbuffer_load:{ *:[v3i32] } v4i32:{ *:[v4i32] }:$rsrc, 0:{ *:[i32] }, 0:{ *:[i32] }, (BUFSOffset:{ *:[i32] } i32:{ *:[i32] }:$soffset), (timm:{ *:[i32] }):$offset, (timm:{ *:[i32] }):$auxiliary, 0:{ *:[i1] })  =>  (BUFFER_LOAD_DWORDX3_OFFSET:{ *:[v3i32] } SReg_128:{ *:[v4i32] }:$rsrc, SCSrc_b32:{ *:[i32] }:$soffset, (timm:{ *:[i32] }):$offset, (extract_cpol:{ *:[i32] } ?:{ *:[i32] }:$auxiliary), (extract_swz:{ *:[i1] } ?:{ *:[i32] }:$auxiliary))
        GIR_BuildMI, /*InsnID*/0, /*Opcode*/GIMT_Encode2(AMDGPU::BUFFER_LOAD_DWORDX3_OFFSET),
        GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/0, // DstI[vdata]
        GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/1, // rsrc
        GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/0, // soffset
        GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/5, // offset
        GIR_CustomOperandRenderer, /*InsnID*/0, /*OldInsnID*/0, /*OpIdx*/6, /*OperandRenderer*/GIMT_Encode2(GICR_renderExtractCPol), // auxiliary
        GIR_CustomOperandRenderer, /*InsnID*/0, /*OldInsnID*/0, /*OpIdx*/6, /*OperandRenderer*/GIMT_Encode2(GICR_renderExtractSWZ), // auxiliary
        GIR_MergeMemOperands, /*InsnID*/0, /*NumInsns*/1, /*MergeInsnID's*/0,
        GIR_ConstrainSelectedInstOperands, /*InsnID*/0,
        GIR_EraseFromParent, /*InsnID*/0,
        // GIR_Coverage, 4177,
        GIR_Done,
      // Label 6452: @473229
      GIM_Try, /*On fail goto*//*Label 6453*/ GIMT_Encode4(473308), // Rule ID 4181 //
        GIM_CheckConstantInt8, /*MI*/0, /*Op*/2, 0,
        GIM_CheckConstantInt8, /*MI*/0, /*Op*/3, 0,
        // MIs[0] offset
        GIM_CheckIsImm, /*MI*/0, /*Op*/5,
        // MIs[0] auxiliary
        GIM_CheckIsImm, /*MI*/0, /*Op*/6,
        // MIs[0] Operand 7
        GIM_CheckLiteralInt, /*MI*/0, /*Op*/7, GIMT_Encode8(0),
        GIM_CheckComplexPattern, /*MI*/0, /*Op*/4, /*Renderer*/GIMT_Encode2(0), GIMT_Encode2(GICP_gi_buf_soffset),
        // (SIbuffer_load:{ *:[v3i32] } v4i32:{ *:[v4i32] }:$rsrc, 0:{ *:[i32] }, 0:{ *:[i32] }, (BUFSOffset:{ *:[i32] } i32:{ *:[i32] }:$soffset), (timm:{ *:[i32] }):$offset, (timm:{ *:[i32] }):$auxiliary, 0:{ *:[i1] })  =>  (BUFFER_LOAD_DWORDX3_VBUFFER_OFFSET:{ *:[v3i32] } SReg_128:{ *:[v4i32] }:$rsrc, SCSrc_b32:{ *:[i32] }:$soffset, (timm:{ *:[i32] }):$offset, (extract_cpol:{ *:[i32] } ?:{ *:[i32] }:$auxiliary), (extract_swz:{ *:[i1] } ?:{ *:[i32] }:$auxiliary))
        GIR_BuildMI, /*InsnID*/0, /*Opcode*/GIMT_Encode2(AMDGPU::BUFFER_LOAD_DWORDX3_VBUFFER_OFFSET),
        GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/0, // DstI[vdata]
        GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/1, // rsrc
        GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/0, // soffset
        GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/5, // offset
        GIR_CustomOperandRenderer, /*InsnID*/0, /*OldInsnID*/0, /*OpIdx*/6, /*OperandRenderer*/GIMT_Encode2(GICR_renderExtractCPol), // auxiliary
        GIR_CustomOperandRenderer, /*InsnID*/0, /*OldInsnID*/0, /*OpIdx*/6, /*OperandRenderer*/GIMT_Encode2(GICR_renderExtractSWZ), // auxiliary
        GIR_MergeMemOperands, /*InsnID*/0, /*NumInsns*/1, /*MergeInsnID's*/0,
        GIR_ConstrainSelectedInstOperands, /*InsnID*/0,
        GIR_EraseFromParent, /*InsnID*/0,
        // GIR_Coverage, 4181,
        GIR_Done,
      // Label 6453: @473308
      GIM_Try, /*On fail goto*//*Label 6454*/ GIMT_Encode4(473390), // Rule ID 4170 //
        GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasUnrestrictedSOffset),
        GIM_CheckConstantInt8, /*MI*/0, /*Op*/2, 0,
        // MIs[0] offset
        GIM_CheckIsImm, /*MI*/0, /*Op*/5,
        // MIs[0] auxiliary
        GIM_CheckIsImm, /*MI*/0, /*Op*/6,
        // MIs[0] Operand 7
        GIM_CheckLiteralInt, /*MI*/0, /*Op*/7, GIMT_Encode8(0),
        GIM_CheckComplexPattern, /*MI*/0, /*Op*/4, /*Renderer*/GIMT_Encode2(0), GIMT_Encode2(GICP_gi_buf_soffset),
        // (SIbuffer_load:{ *:[v3f32] } v4i32:{ *:[v4i32] }:$rsrc, 0:{ *:[i32] }, i32:{ *:[i32] }:$voffset, (BUFSOffset:{ *:[i32] } i32:{ *:[i32] }:$soffset), (timm:{ *:[i32] }):$offset, (timm:{ *:[i32] }):$auxiliary, 0:{ *:[i1] })  =>  (BUFFER_LOAD_DWORDX3_OFFEN:{ *:[v3f32] } VGPR_32:{ *:[i32] }:$voffset, SReg_128:{ *:[v4i32] }:$rsrc, SCSrc_b32:{ *:[i32] }:$soffset, (timm:{ *:[i32] }):$offset, (extract_cpol:{ *:[i32] } ?:{ *:[i32] }:$auxiliary), (extract_swz:{ *:[i1] } ?:{ *:[i32] }:$auxiliary))
        GIR_BuildMI, /*InsnID*/0, /*Opcode*/GIMT_Encode2(AMDGPU::BUFFER_LOAD_DWORDX3_OFFEN),
        GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/0, // DstI[vdata]
        GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/3, // voffset
        GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/1, // rsrc
        GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/0, // soffset
        GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/5, // offset
        GIR_CustomOperandRenderer, /*InsnID*/0, /*OldInsnID*/0, /*OpIdx*/6, /*OperandRenderer*/GIMT_Encode2(GICR_renderExtractCPol), // auxiliary
        GIR_CustomOperandRenderer, /*InsnID*/0, /*OldInsnID*/0, /*OpIdx*/6, /*OperandRenderer*/GIMT_Encode2(GICR_renderExtractSWZ), // auxiliary
        GIR_MergeMemOperands, /*InsnID*/0, /*NumInsns*/1, /*MergeInsnID's*/0,
        GIR_ConstrainSelectedInstOperands, /*InsnID*/0,
        GIR_EraseFromParent, /*InsnID*/0,
        // GIR_Coverage, 4170,
        GIR_Done,
      // Label 6454: @473390
      GIM_Try, /*On fail goto*//*Label 6455*/ GIMT_Encode4(473469), // Rule ID 4174 //
        GIM_CheckConstantInt8, /*MI*/0, /*Op*/2, 0,
        // MIs[0] offset
        GIM_CheckIsImm, /*MI*/0, /*Op*/5,
        // MIs[0] auxiliary
        GIM_CheckIsImm, /*MI*/0, /*Op*/6,
        // MIs[0] Operand 7
        GIM_CheckLiteralInt, /*MI*/0, /*Op*/7, GIMT_Encode8(0),
        GIM_CheckComplexPattern, /*MI*/0, /*Op*/4, /*Renderer*/GIMT_Encode2(0), GIMT_Encode2(GICP_gi_buf_soffset),
        // (SIbuffer_load:{ *:[v3f32] } v4i32:{ *:[v4i32] }:$rsrc, 0:{ *:[i32] }, i32:{ *:[i32] }:$voffset, (BUFSOffset:{ *:[i32] } i32:{ *:[i32] }:$soffset), (timm:{ *:[i32] }):$offset, (timm:{ *:[i32] }):$auxiliary, 0:{ *:[i1] })  =>  (BUFFER_LOAD_DWORDX3_VBUFFER_OFFEN:{ *:[v3f32] } VGPR_32:{ *:[i32] }:$voffset, SReg_128:{ *:[v4i32] }:$rsrc, SCSrc_b32:{ *:[i32] }:$soffset, (timm:{ *:[i32] }):$offset, (extract_cpol:{ *:[i32] } ?:{ *:[i32] }:$auxiliary), (extract_swz:{ *:[i1] } ?:{ *:[i32] }:$auxiliary))
        GIR_BuildMI, /*InsnID*/0, /*Opcode*/GIMT_Encode2(AMDGPU::BUFFER_LOAD_DWORDX3_VBUFFER_OFFEN),
        GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/0, // DstI[vdata]
        GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/3, // voffset
        GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/1, // rsrc
        GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/0, // soffset
        GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/5, // offset
        GIR_CustomOperandRenderer, /*InsnID*/0, /*OldInsnID*/0, /*OpIdx*/6, /*OperandRenderer*/GIMT_Encode2(GICR_renderExtractCPol), // auxiliary
        GIR_CustomOperandRenderer, /*InsnID*/0, /*OldInsnID*/0, /*OpIdx*/6, /*OperandRenderer*/GIMT_Encode2(GICR_renderExtractSWZ), // auxiliary
        GIR_MergeMemOperands, /*InsnID*/0, /*NumInsns*/1, /*MergeInsnID's*/0,
        GIR_ConstrainSelectedInstOperands, /*InsnID*/0,
        GIR_EraseFromParent, /*InsnID*/0,
        // GIR_Coverage, 4174,
        GIR_Done,
      // Label 6455: @473469
      GIM_Try, /*On fail goto*//*Label 6456*/ GIMT_Encode4(473551), // Rule ID 4178 //
        GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasUnrestrictedSOffset),
        GIM_CheckConstantInt8, /*MI*/0, /*Op*/2, 0,
        // MIs[0] offset
        GIM_CheckIsImm, /*MI*/0, /*Op*/5,
        // MIs[0] auxiliary
        GIM_CheckIsImm, /*MI*/0, /*Op*/6,
        // MIs[0] Operand 7
        GIM_CheckLiteralInt, /*MI*/0, /*Op*/7, GIMT_Encode8(0),
        GIM_CheckComplexPattern, /*MI*/0, /*Op*/4, /*Renderer*/GIMT_Encode2(0), GIMT_Encode2(GICP_gi_buf_soffset),
        // (SIbuffer_load:{ *:[v3i32] } v4i32:{ *:[v4i32] }:$rsrc, 0:{ *:[i32] }, i32:{ *:[i32] }:$voffset, (BUFSOffset:{ *:[i32] } i32:{ *:[i32] }:$soffset), (timm:{ *:[i32] }):$offset, (timm:{ *:[i32] }):$auxiliary, 0:{ *:[i1] })  =>  (BUFFER_LOAD_DWORDX3_OFFEN:{ *:[v3i32] } VGPR_32:{ *:[i32] }:$voffset, SReg_128:{ *:[v4i32] }:$rsrc, SCSrc_b32:{ *:[i32] }:$soffset, (timm:{ *:[i32] }):$offset, (extract_cpol:{ *:[i32] } ?:{ *:[i32] }:$auxiliary), (extract_swz:{ *:[i1] } ?:{ *:[i32] }:$auxiliary))
        GIR_BuildMI, /*InsnID*/0, /*Opcode*/GIMT_Encode2(AMDGPU::BUFFER_LOAD_DWORDX3_OFFEN),
        GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/0, // DstI[vdata]
        GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/3, // voffset
        GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/1, // rsrc
        GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/0, // soffset
        GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/5, // offset
        GIR_CustomOperandRenderer, /*InsnID*/0, /*OldInsnID*/0, /*OpIdx*/6, /*OperandRenderer*/GIMT_Encode2(GICR_renderExtractCPol), // auxiliary
        GIR_CustomOperandRenderer, /*InsnID*/0, /*OldInsnID*/0, /*OpIdx*/6, /*OperandRenderer*/GIMT_Encode2(GICR_renderExtractSWZ), // auxiliary
        GIR_MergeMemOperands, /*InsnID*/0, /*NumInsns*/1, /*MergeInsnID's*/0,
        GIR_ConstrainSelectedInstOperands, /*InsnID*/0,
        GIR_EraseFromParent, /*InsnID*/0,
        // GIR_Coverage, 4178,
        GIR_Done,
      // Label 6456: @473551
      GIM_Try, /*On fail goto*//*Label 6457*/ GIMT_Encode4(473630), // Rule ID 4182 //
        GIM_CheckConstantInt8, /*MI*/0, /*Op*/2, 0,
        // MIs[0] offset
        GIM_CheckIsImm, /*MI*/0, /*Op*/5,
        // MIs[0] auxiliary
        GIM_CheckIsImm, /*MI*/0, /*Op*/6,
        // MIs[0] Operand 7
        GIM_CheckLiteralInt, /*MI*/0, /*Op*/7, GIMT_Encode8(0),
        GIM_CheckComplexPattern, /*MI*/0, /*Op*/4, /*Renderer*/GIMT_Encode2(0), GIMT_Encode2(GICP_gi_buf_soffset),
        // (SIbuffer_load:{ *:[v3i32] } v4i32:{ *:[v4i32] }:$rsrc, 0:{ *:[i32] }, i32:{ *:[i32] }:$voffset, (BUFSOffset:{ *:[i32] } i32:{ *:[i32] }:$soffset), (timm:{ *:[i32] }):$offset, (timm:{ *:[i32] }):$auxiliary, 0:{ *:[i1] })  =>  (BUFFER_LOAD_DWORDX3_VBUFFER_OFFEN:{ *:[v3i32] } VGPR_32:{ *:[i32] }:$voffset, SReg_128:{ *:[v4i32] }:$rsrc, SCSrc_b32:{ *:[i32] }:$soffset, (timm:{ *:[i32] }):$offset, (extract_cpol:{ *:[i32] } ?:{ *:[i32] }:$auxiliary), (extract_swz:{ *:[i1] } ?:{ *:[i32] }:$auxiliary))
        GIR_BuildMI, /*InsnID*/0, /*Opcode*/GIMT_Encode2(AMDGPU::BUFFER_LOAD_DWORDX3_VBUFFER_OFFEN),
        GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/0, // DstI[vdata]
        GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/3, // voffset
        GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/1, // rsrc
        GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/0, // soffset
        GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/5, // offset
        GIR_CustomOperandRenderer, /*InsnID*/0, /*OldInsnID*/0, /*OpIdx*/6, /*OperandRenderer*/GIMT_Encode2(GICR_renderExtractCPol), // auxiliary
        GIR_CustomOperandRenderer, /*InsnID*/0, /*OldInsnID*/0, /*OpIdx*/6, /*OperandRenderer*/GIMT_Encode2(GICR_renderExtractSWZ), // auxiliary
        GIR_MergeMemOperands, /*InsnID*/0, /*NumInsns*/1, /*MergeInsnID's*/0,
        GIR_ConstrainSelectedInstOperands, /*InsnID*/0,
        GIR_EraseFromParent, /*InsnID*/0,
        // GIR_Coverage, 4182,
        GIR_Done,
      // Label 6457: @473630
      GIM_Try, /*On fail goto*//*Label 6458*/ GIMT_Encode4(473704), // Rule ID 4171 //
        GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasUnrestrictedSOffset),
        GIM_CheckConstantInt8, /*MI*/0, /*Op*/3, 0,
        // MIs[0] offset
        GIM_CheckIsImm, /*MI*/0, /*Op*/5,
        // MIs[0] auxiliary
        GIM_CheckIsImm, /*MI*/0, /*Op*/6,
        // MIs[0] Operand 7
        GIM_CheckIsImm, /*MI*/0, /*Op*/7,
        GIM_CheckComplexPattern, /*MI*/0, /*Op*/4, /*Renderer*/GIMT_Encode2(0), GIMT_Encode2(GICP_gi_buf_soffset),
        // (SIbuffer_load:{ *:[v3f32] } v4i32:{ *:[v4i32] }:$rsrc, i32:{ *:[i32] }:$vindex, 0:{ *:[i32] }, (BUFSOffset:{ *:[i32] } i32:{ *:[i32] }:$soffset), (timm:{ *:[i32] }):$offset, (timm:{ *:[i32] }):$auxiliary, (timm:{ *:[i1] }))  =>  (BUFFER_LOAD_DWORDX3_IDXEN:{ *:[v3f32] } VGPR_32:{ *:[i32] }:$vindex, SReg_128:{ *:[v4i32] }:$rsrc, SCSrc_b32:{ *:[i32] }:$soffset, (timm:{ *:[i32] }):$offset, (extract_cpol:{ *:[i32] } ?:{ *:[i32] }:$auxiliary), (extract_swz:{ *:[i1] } ?:{ *:[i32] }:$auxiliary))
        GIR_BuildMI, /*InsnID*/0, /*Opcode*/GIMT_Encode2(AMDGPU::BUFFER_LOAD_DWORDX3_IDXEN),
        GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/0, // DstI[vdata]
        GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/2, // vindex
        GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/1, // rsrc
        GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/0, // soffset
        GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/5, // offset
        GIR_CustomOperandRenderer, /*InsnID*/0, /*OldInsnID*/0, /*OpIdx*/6, /*OperandRenderer*/GIMT_Encode2(GICR_renderExtractCPol), // auxiliary
        GIR_CustomOperandRenderer, /*InsnID*/0, /*OldInsnID*/0, /*OpIdx*/6, /*OperandRenderer*/GIMT_Encode2(GICR_renderExtractSWZ), // auxiliary
        GIR_MergeMemOperands, /*InsnID*/0, /*NumInsns*/1, /*MergeInsnID's*/0,
        GIR_ConstrainSelectedInstOperands, /*InsnID*/0,
        GIR_EraseFromParent, /*InsnID*/0,
        // GIR_Coverage, 4171,
        GIR_Done,
      // Label 6458: @473704
      GIM_Try, /*On fail goto*//*Label 6459*/ GIMT_Encode4(473775), // Rule ID 4175 //
        GIM_CheckConstantInt8, /*MI*/0, /*Op*/3, 0,
        // MIs[0] offset
        GIM_CheckIsImm, /*MI*/0, /*Op*/5,
        // MIs[0] auxiliary
        GIM_CheckIsImm, /*MI*/0, /*Op*/6,
        // MIs[0] Operand 7
        GIM_CheckIsImm, /*MI*/0, /*Op*/7,
        GIM_CheckComplexPattern, /*MI*/0, /*Op*/4, /*Renderer*/GIMT_Encode2(0), GIMT_Encode2(GICP_gi_buf_soffset),
        // (SIbuffer_load:{ *:[v3f32] } v4i32:{ *:[v4i32] }:$rsrc, i32:{ *:[i32] }:$vindex, 0:{ *:[i32] }, (BUFSOffset:{ *:[i32] } i32:{ *:[i32] }:$soffset), (timm:{ *:[i32] }):$offset, (timm:{ *:[i32] }):$auxiliary, (timm:{ *:[i1] }))  =>  (BUFFER_LOAD_DWORDX3_VBUFFER_IDXEN:{ *:[v3f32] } VGPR_32:{ *:[i32] }:$vindex, SReg_128:{ *:[v4i32] }:$rsrc, SCSrc_b32:{ *:[i32] }:$soffset, (timm:{ *:[i32] }):$offset, (extract_cpol:{ *:[i32] } ?:{ *:[i32] }:$auxiliary), (extract_swz:{ *:[i1] } ?:{ *:[i32] }:$auxiliary))
        GIR_BuildMI, /*InsnID*/0, /*Opcode*/GIMT_Encode2(AMDGPU::BUFFER_LOAD_DWORDX3_VBUFFER_IDXEN),
        GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/0, // DstI[vdata]
        GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/2, // vindex
        GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/1, // rsrc
        GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/0, // soffset
        GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/5, // offset
        GIR_CustomOperandRenderer, /*InsnID*/0, /*OldInsnID*/0, /*OpIdx*/6, /*OperandRenderer*/GIMT_Encode2(GICR_renderExtractCPol), // auxiliary
        GIR_CustomOperandRenderer, /*InsnID*/0, /*OldInsnID*/0, /*OpIdx*/6, /*OperandRenderer*/GIMT_Encode2(GICR_renderExtractSWZ), // auxiliary
        GIR_MergeMemOperands, /*InsnID*/0, /*NumInsns*/1, /*MergeInsnID's*/0,
        GIR_ConstrainSelectedInstOperands, /*InsnID*/0,
        GIR_EraseFromParent, /*InsnID*/0,
        // GIR_Coverage, 4175,
        GIR_Done,
      // Label 6459: @473775
      GIM_Try, /*On fail goto*//*Label 6460*/ GIMT_Encode4(473849), // Rule ID 4179 //
        GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasUnrestrictedSOffset),
        GIM_CheckConstantInt8, /*MI*/0, /*Op*/3, 0,
        // MIs[0] offset
        GIM_CheckIsImm, /*MI*/0, /*Op*/5,
        // MIs[0] auxiliary
        GIM_CheckIsImm, /*MI*/0, /*Op*/6,
        // MIs[0] Operand 7
        GIM_CheckIsImm, /*MI*/0, /*Op*/7,
        GIM_CheckComplexPattern, /*MI*/0, /*Op*/4, /*Renderer*/GIMT_Encode2(0), GIMT_Encode2(GICP_gi_buf_soffset),
        // (SIbuffer_load:{ *:[v3i32] } v4i32:{ *:[v4i32] }:$rsrc, i32:{ *:[i32] }:$vindex, 0:{ *:[i32] }, (BUFSOffset:{ *:[i32] } i32:{ *:[i32] }:$soffset), (timm:{ *:[i32] }):$offset, (timm:{ *:[i32] }):$auxiliary, (timm:{ *:[i1] }))  =>  (BUFFER_LOAD_DWORDX3_IDXEN:{ *:[v3i32] } VGPR_32:{ *:[i32] }:$vindex, SReg_128:{ *:[v4i32] }:$rsrc, SCSrc_b32:{ *:[i32] }:$soffset, (timm:{ *:[i32] }):$offset, (extract_cpol:{ *:[i32] } ?:{ *:[i32] }:$auxiliary), (extract_swz:{ *:[i1] } ?:{ *:[i32] }:$auxiliary))
        GIR_BuildMI, /*InsnID*/0, /*Opcode*/GIMT_Encode2(AMDGPU::BUFFER_LOAD_DWORDX3_IDXEN),
        GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/0, // DstI[vdata]
        GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/2, // vindex
        GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/1, // rsrc
        GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/0, // soffset
        GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/5, // offset
        GIR_CustomOperandRenderer, /*InsnID*/0, /*OldInsnID*/0, /*OpIdx*/6, /*OperandRenderer*/GIMT_Encode2(GICR_renderExtractCPol), // auxiliary
        GIR_CustomOperandRenderer, /*InsnID*/0, /*OldInsnID*/0, /*OpIdx*/6, /*OperandRenderer*/GIMT_Encode2(GICR_renderExtractSWZ), // auxiliary
        GIR_MergeMemOperands, /*InsnID*/0, /*NumInsns*/1, /*MergeInsnID's*/0,
        GIR_ConstrainSelectedInstOperands, /*InsnID*/0,
        GIR_EraseFromParent, /*InsnID*/0,
        // GIR_Coverage, 4179,
        GIR_Done,
      // Label 6460: @473849
      GIM_Try, /*On fail goto*//*Label 6461*/ GIMT_Encode4(473920), // Rule ID 4183 //
        GIM_CheckConstantInt8, /*MI*/0, /*Op*/3, 0,
        // MIs[0] offset
        GIM_CheckIsImm, /*MI*/0, /*Op*/5,
        // MIs[0] auxiliary
        GIM_CheckIsImm, /*MI*/0, /*Op*/6,
        // MIs[0] Operand 7
        GIM_CheckIsImm, /*MI*/0, /*Op*/7,
        GIM_CheckComplexPattern, /*MI*/0, /*Op*/4, /*Renderer*/GIMT_Encode2(0), GIMT_Encode2(GICP_gi_buf_soffset),
        // (SIbuffer_load:{ *:[v3i32] } v4i32:{ *:[v4i32] }:$rsrc, i32:{ *:[i32] }:$vindex, 0:{ *:[i32] }, (BUFSOffset:{ *:[i32] } i32:{ *:[i32] }:$soffset), (timm:{ *:[i32] }):$offset, (timm:{ *:[i32] }):$auxiliary, (timm:{ *:[i1] }))  =>  (BUFFER_LOAD_DWORDX3_VBUFFER_IDXEN:{ *:[v3i32] } VGPR_32:{ *:[i32] }:$vindex, SReg_128:{ *:[v4i32] }:$rsrc, SCSrc_b32:{ *:[i32] }:$soffset, (timm:{ *:[i32] }):$offset, (extract_cpol:{ *:[i32] } ?:{ *:[i32] }:$auxiliary), (extract_swz:{ *:[i1] } ?:{ *:[i32] }:$auxiliary))
        GIR_BuildMI, /*InsnID*/0, /*Opcode*/GIMT_Encode2(AMDGPU::BUFFER_LOAD_DWORDX3_VBUFFER_IDXEN),
        GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/0, // DstI[vdata]
        GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/2, // vindex
        GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/1, // rsrc
        GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/0, // soffset
        GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/5, // offset
        GIR_CustomOperandRenderer, /*InsnID*/0, /*OldInsnID*/0, /*OpIdx*/6, /*OperandRenderer*/GIMT_Encode2(GICR_renderExtractCPol), // auxiliary
        GIR_CustomOperandRenderer, /*InsnID*/0, /*OldInsnID*/0, /*OpIdx*/6, /*OperandRenderer*/GIMT_Encode2(GICR_renderExtractSWZ), // auxiliary
        GIR_MergeMemOperands, /*InsnID*/0, /*NumInsns*/1, /*MergeInsnID's*/0,
        GIR_ConstrainSelectedInstOperands, /*InsnID*/0,
        GIR_EraseFromParent, /*InsnID*/0,
        // GIR_Coverage, 4183,
        GIR_Done,
      // Label 6461: @473920
      GIM_Try, /*On fail goto*//*Label 6462*/ GIMT_Encode4(474030), // Rule ID 4172 //
        GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasUnrestrictedSOffset),
        // MIs[0] offset
        GIM_CheckIsImm, /*MI*/0, /*Op*/5,
        // MIs[0] auxiliary
        GIM_CheckIsImm, /*MI*/0, /*Op*/6,
        // MIs[0] Operand 7
        GIM_CheckIsImm, /*MI*/0, /*Op*/7,
        GIM_CheckComplexPattern, /*MI*/0, /*Op*/4, /*Renderer*/GIMT_Encode2(0), GIMT_Encode2(GICP_gi_buf_soffset),
        // (SIbuffer_load:{ *:[v3f32] } v4i32:{ *:[v4i32] }:$rsrc, i32:{ *:[i32] }:$vindex, i32:{ *:[i32] }:$voffset, (BUFSOffset:{ *:[i32] } i32:{ *:[i32] }:$soffset), (timm:{ *:[i32] }):$offset, (timm:{ *:[i32] }):$auxiliary, (timm:{ *:[i1] }))  =>  (BUFFER_LOAD_DWORDX3_BOTHEN:{ *:[v3f32] } (REG_SEQUENCE:{ *:[i64] } VReg_64:{ *:[i32] }, VGPR_32:{ *:[i32] }:$vindex, sub0:{ *:[i32] }, VGPR_32:{ *:[i32] }:$voffset, sub1:{ *:[i32] }), SReg_128:{ *:[v4i32] }:$rsrc, SCSrc_b32:{ *:[i32] }:$soffset, (timm:{ *:[i32] }):$offset, (extract_cpol:{ *:[i32] } ?:{ *:[i32] }:$auxiliary), (extract_swz:{ *:[i1] } ?:{ *:[i32] }:$auxiliary))
        GIR_MakeTempReg, /*TempRegID*/0, /*TypeID*/GILLT_s64,
        GIR_BuildMI, /*InsnID*/1, /*Opcode*/GIMT_Encode2(TargetOpcode::REG_SEQUENCE),
        GIR_AddTempRegister, /*InsnID*/1, /*TempRegID*/0, /*TempRegFlags*/GIMT_Encode2(RegState::Define),
        GIR_Copy, /*NewInsnID*/1, /*OldInsnID*/0, /*OpIdx*/2, // vindex
        GIR_AddImm8, /*InsnID*/1, /*SubRegIndex*/3,
        GIR_Copy, /*NewInsnID*/1, /*OldInsnID*/0, /*OpIdx*/3, // voffset
        GIR_AddImm8, /*InsnID*/1, /*SubRegIndex*/11,
        GIR_ConstrainOperandRC, /*InsnID*/1, /*Op*/0, GIMT_Encode2(AMDGPU::VReg_64RegClassID),
        GIR_ConstrainOperandRC, /*InsnID*/1, /*Op*/1, GIMT_Encode2(AMDGPU::VGPR_32RegClassID),
        GIR_ConstrainOperandRC, /*InsnID*/1, /*Op*/3, GIMT_Encode2(AMDGPU::VGPR_32RegClassID),
        GIR_BuildMI, /*InsnID*/0, /*Opcode*/GIMT_Encode2(AMDGPU::BUFFER_LOAD_DWORDX3_BOTHEN),
        GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/0, // DstI[vdata]
        GIR_AddSimpleTempRegister, /*InsnID*/0, /*TempRegID*/0,
        GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/1, // rsrc
        GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/0, // soffset
        GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/5, // offset
        GIR_CustomOperandRenderer, /*InsnID*/0, /*OldInsnID*/0, /*OpIdx*/6, /*OperandRenderer*/GIMT_Encode2(GICR_renderExtractCPol), // auxiliary
        GIR_CustomOperandRenderer, /*InsnID*/0, /*OldInsnID*/0, /*OpIdx*/6, /*OperandRenderer*/GIMT_Encode2(GICR_renderExtractSWZ), // auxiliary
        GIR_MergeMemOperands, /*InsnID*/0, /*NumInsns*/1, /*MergeInsnID's*/0,
        GIR_ConstrainSelectedInstOperands, /*InsnID*/0,
        GIR_EraseFromParent, /*InsnID*/0,
        // GIR_Coverage, 4172,
        GIR_Done,
      // Label 6462: @474030
      GIM_Try, /*On fail goto*//*Label 6463*/ GIMT_Encode4(474137), // Rule ID 4176 //
        // MIs[0] offset
        GIM_CheckIsImm, /*MI*/0, /*Op*/5,
        // MIs[0] auxiliary
        GIM_CheckIsImm, /*MI*/0, /*Op*/6,
        // MIs[0] Operand 7
        GIM_CheckIsImm, /*MI*/0, /*Op*/7,
        GIM_CheckComplexPattern, /*MI*/0, /*Op*/4, /*Renderer*/GIMT_Encode2(0), GIMT_Encode2(GICP_gi_buf_soffset),
        // (SIbuffer_load:{ *:[v3f32] } v4i32:{ *:[v4i32] }:$rsrc, i32:{ *:[i32] }:$vindex, i32:{ *:[i32] }:$voffset, (BUFSOffset:{ *:[i32] } i32:{ *:[i32] }:$soffset), (timm:{ *:[i32] }):$offset, (timm:{ *:[i32] }):$auxiliary, (timm:{ *:[i1] }))  =>  (BUFFER_LOAD_DWORDX3_VBUFFER_BOTHEN:{ *:[v3f32] } (REG_SEQUENCE:{ *:[i64] } VReg_64:{ *:[i32] }, VGPR_32:{ *:[i32] }:$vindex, sub0:{ *:[i32] }, VGPR_32:{ *:[i32] }:$voffset, sub1:{ *:[i32] }), SReg_128:{ *:[v4i32] }:$rsrc, SCSrc_b32:{ *:[i32] }:$soffset, (timm:{ *:[i32] }):$offset, (extract_cpol:{ *:[i32] } ?:{ *:[i32] }:$auxiliary), (extract_swz:{ *:[i1] } ?:{ *:[i32] }:$auxiliary))
        GIR_MakeTempReg, /*TempRegID*/0, /*TypeID*/GILLT_s64,
        GIR_BuildMI, /*InsnID*/1, /*Opcode*/GIMT_Encode2(TargetOpcode::REG_SEQUENCE),
        GIR_AddTempRegister, /*InsnID*/1, /*TempRegID*/0, /*TempRegFlags*/GIMT_Encode2(RegState::Define),
        GIR_Copy, /*NewInsnID*/1, /*OldInsnID*/0, /*OpIdx*/2, // vindex
        GIR_AddImm8, /*InsnID*/1, /*SubRegIndex*/3,
        GIR_Copy, /*NewInsnID*/1, /*OldInsnID*/0, /*OpIdx*/3, // voffset
        GIR_AddImm8, /*InsnID*/1, /*SubRegIndex*/11,
        GIR_ConstrainOperandRC, /*InsnID*/1, /*Op*/0, GIMT_Encode2(AMDGPU::VReg_64RegClassID),
        GIR_ConstrainOperandRC, /*InsnID*/1, /*Op*/1, GIMT_Encode2(AMDGPU::VGPR_32RegClassID),
        GIR_ConstrainOperandRC, /*InsnID*/1, /*Op*/3, GIMT_Encode2(AMDGPU::VGPR_32RegClassID),
        GIR_BuildMI, /*InsnID*/0, /*Opcode*/GIMT_Encode2(AMDGPU::BUFFER_LOAD_DWORDX3_VBUFFER_BOTHEN),
        GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/0, // DstI[vdata]
        GIR_AddSimpleTempRegister, /*InsnID*/0, /*TempRegID*/0,
        GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/1, // rsrc
        GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/0, // soffset
        GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/5, // offset
        GIR_CustomOperandRenderer, /*InsnID*/0, /*OldInsnID*/0, /*OpIdx*/6, /*OperandRenderer*/GIMT_Encode2(GICR_renderExtractCPol), // auxiliary
        GIR_CustomOperandRenderer, /*InsnID*/0, /*OldInsnID*/0, /*OpIdx*/6, /*OperandRenderer*/GIMT_Encode2(GICR_renderExtractSWZ), // auxiliary
        GIR_MergeMemOperands, /*InsnID*/0, /*NumInsns*/1, /*MergeInsnID's*/0,
        GIR_ConstrainSelectedInstOperands, /*InsnID*/0,
        GIR_EraseFromParent, /*InsnID*/0,
        // GIR_Coverage, 4176,
        GIR_Done,
      // Label 6463: @474137
      GIM_Try, /*On fail goto*//*Label 6464*/ GIMT_Encode4(474247), // Rule ID 4180 //
        GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasUnrestrictedSOffset),
        // MIs[0] offset
        GIM_CheckIsImm, /*MI*/0, /*Op*/5,
        // MIs[0] auxiliary
        GIM_CheckIsImm, /*MI*/0, /*Op*/6,
        // MIs[0] Operand 7
        GIM_CheckIsImm, /*MI*/0, /*Op*/7,
        GIM_CheckComplexPattern, /*MI*/0, /*Op*/4, /*Renderer*/GIMT_Encode2(0), GIMT_Encode2(GICP_gi_buf_soffset),
        // (SIbuffer_load:{ *:[v3i32] } v4i32:{ *:[v4i32] }:$rsrc, i32:{ *:[i32] }:$vindex, i32:{ *:[i32] }:$voffset, (BUFSOffset:{ *:[i32] } i32:{ *:[i32] }:$soffset), (timm:{ *:[i32] }):$offset, (timm:{ *:[i32] }):$auxiliary, (timm:{ *:[i1] }))  =>  (BUFFER_LOAD_DWORDX3_BOTHEN:{ *:[v3i32] } (REG_SEQUENCE:{ *:[i64] } VReg_64:{ *:[i32] }, VGPR_32:{ *:[i32] }:$vindex, sub0:{ *:[i32] }, VGPR_32:{ *:[i32] }:$voffset, sub1:{ *:[i32] }), SReg_128:{ *:[v4i32] }:$rsrc, SCSrc_b32:{ *:[i32] }:$soffset, (timm:{ *:[i32] }):$offset, (extract_cpol:{ *:[i32] } ?:{ *:[i32] }:$auxiliary), (extract_swz:{ *:[i1] } ?:{ *:[i32] }:$auxiliary))
        GIR_MakeTempReg, /*TempRegID*/0, /*TypeID*/GILLT_s64,
        GIR_BuildMI, /*InsnID*/1, /*Opcode*/GIMT_Encode2(TargetOpcode::REG_SEQUENCE),
        GIR_AddTempRegister, /*InsnID*/1, /*TempRegID*/0, /*TempRegFlags*/GIMT_Encode2(RegState::Define),
        GIR_Copy, /*NewInsnID*/1, /*OldInsnID*/0, /*OpIdx*/2, // vindex
        GIR_AddImm8, /*InsnID*/1, /*SubRegIndex*/3,
        GIR_Copy, /*NewInsnID*/1, /*OldInsnID*/0, /*OpIdx*/3, // voffset
        GIR_AddImm8, /*InsnID*/1, /*SubRegIndex*/11,
        GIR_ConstrainOperandRC, /*InsnID*/1, /*Op*/0, GIMT_Encode2(AMDGPU::VReg_64RegClassID),
        GIR_ConstrainOperandRC, /*InsnID*/1, /*Op*/1, GIMT_Encode2(AMDGPU::VGPR_32RegClassID),
        GIR_ConstrainOperandRC, /*InsnID*/1, /*Op*/3, GIMT_Encode2(AMDGPU::VGPR_32RegClassID),
        GIR_BuildMI, /*InsnID*/0, /*Opcode*/GIMT_Encode2(AMDGPU::BUFFER_LOAD_DWORDX3_BOTHEN),
        GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/0, // DstI[vdata]
        GIR_AddSimpleTempRegister, /*InsnID*/0, /*TempRegID*/0,
        GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/1, // rsrc
        GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/0, // soffset
        GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/5, // offset
        GIR_CustomOperandRenderer, /*InsnID*/0, /*OldInsnID*/0, /*OpIdx*/6, /*OperandRenderer*/GIMT_Encode2(GICR_renderExtractCPol), // auxiliary
        GIR_CustomOperandRenderer, /*InsnID*/0, /*OldInsnID*/0, /*OpIdx*/6, /*OperandRenderer*/GIMT_Encode2(GICR_renderExtractSWZ), // auxiliary
        GIR_MergeMemOperands, /*InsnID*/0, /*NumInsns*/1, /*MergeInsnID's*/0,
        GIR_ConstrainSelectedInstOperands, /*InsnID*/0,
        GIR_EraseFromParent, /*InsnID*/0,
        // GIR_Coverage, 4180,
        GIR_Done,
      // Label 6464: @474247
      GIM_Try, /*On fail goto*//*Label 6465*/ GIMT_Encode4(474354), // Rule ID 4184 //
        // MIs[0] offset
        GIM_CheckIsImm, /*MI*/0, /*Op*/5,
        // MIs[0] auxiliary
        GIM_CheckIsImm, /*MI*/0, /*Op*/6,
        // MIs[0] Operand 7
        GIM_CheckIsImm, /*MI*/0, /*Op*/7,
        GIM_CheckComplexPattern, /*MI*/0, /*Op*/4, /*Renderer*/GIMT_Encode2(0), GIMT_Encode2(GICP_gi_buf_soffset),
        // (SIbuffer_load:{ *:[v3i32] } v4i32:{ *:[v4i32] }:$rsrc, i32:{ *:[i32] }:$vindex, i32:{ *:[i32] }:$voffset, (BUFSOffset:{ *:[i32] } i32:{ *:[i32] }:$soffset), (timm:{ *:[i32] }):$offset, (timm:{ *:[i32] }):$auxiliary, (timm:{ *:[i1] }))  =>  (BUFFER_LOAD_DWORDX3_VBUFFER_BOTHEN:{ *:[v3i32] } (REG_SEQUENCE:{ *:[i64] } VReg_64:{ *:[i32] }, VGPR_32:{ *:[i32] }:$vindex, sub0:{ *:[i32] }, VGPR_32:{ *:[i32] }:$voffset, sub1:{ *:[i32] }), SReg_128:{ *:[v4i32] }:$rsrc, SCSrc_b32:{ *:[i32] }:$soffset, (timm:{ *:[i32] }):$offset, (extract_cpol:{ *:[i32] } ?:{ *:[i32] }:$auxiliary), (extract_swz:{ *:[i1] } ?:{ *:[i32] }:$auxiliary))
        GIR_MakeTempReg, /*TempRegID*/0, /*TypeID*/GILLT_s64,
        GIR_BuildMI, /*InsnID*/1, /*Opcode*/GIMT_Encode2(TargetOpcode::REG_SEQUENCE),
        GIR_AddTempRegister, /*InsnID*/1, /*TempRegID*/0, /*TempRegFlags*/GIMT_Encode2(RegState::Define),
        GIR_Copy, /*NewInsnID*/1, /*OldInsnID*/0, /*OpIdx*/2, // vindex
        GIR_AddImm8, /*InsnID*/1, /*SubRegIndex*/3,
        GIR_Copy, /*NewInsnID*/1, /*OldInsnID*/0, /*OpIdx*/3, // voffset
        GIR_AddImm8, /*InsnID*/1, /*SubRegIndex*/11,
        GIR_ConstrainOperandRC, /*InsnID*/1, /*Op*/0, GIMT_Encode2(AMDGPU::VReg_64RegClassID),
        GIR_ConstrainOperandRC, /*InsnID*/1, /*Op*/1, GIMT_Encode2(AMDGPU::VGPR_32RegClassID),
        GIR_ConstrainOperandRC, /*InsnID*/1, /*Op*/3, GIMT_Encode2(AMDGPU::VGPR_32RegClassID),
        GIR_BuildMI, /*InsnID*/0, /*Opcode*/GIMT_Encode2(AMDGPU::BUFFER_LOAD_DWORDX3_VBUFFER_BOTHEN),
        GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/0, // DstI[vdata]
        GIR_AddSimpleTempRegister, /*InsnID*/0, /*TempRegID*/0,
        GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/1, // rsrc
        GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/0, // soffset
        GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/5, // offset
        GIR_CustomOperandRenderer, /*InsnID*/0, /*OldInsnID*/0, /*OpIdx*/6, /*OperandRenderer*/GIMT_Encode2(GICR_renderExtractCPol), // auxiliary
        GIR_CustomOperandRenderer, /*InsnID*/0, /*OldInsnID*/0, /*OpIdx*/6, /*OperandRenderer*/GIMT_Encode2(GICR_renderExtractSWZ), // auxiliary
        GIR_MergeMemOperands, /*InsnID*/0, /*NumInsns*/1, /*MergeInsnID's*/0,
        GIR_ConstrainSelectedInstOperands, /*InsnID*/0,
        GIR_EraseFromParent, /*InsnID*/0,
        // GIR_Coverage, 4184,
        GIR_Done,
      // Label 6465: @474354
      GIM_Reject,
    // Label 6449: @474355
    GIM_Reject,
    // Label 6395: @474356
    GIM_Try, /*On fail goto*//*Label 6466*/ GIMT_Encode4(475751),
      GIM_CheckType, /*MI*/0, /*Op*/1, /*Type*/GILLT_v4s32,
      GIM_CheckType, /*MI*/0, /*Op*/2, /*Type*/GILLT_s32,
      GIM_CheckType, /*MI*/0, /*Op*/3, /*Type*/GILLT_s32,
      GIM_CheckType, /*MI*/0, /*Op*/4, /*Type*/GILLT_s32,
      GIM_CheckRegBankForClass, /*MI*/0, /*Op*/0, /*RC*/GIMT_Encode2(AMDGPU::AV_64RegClassID),
      GIM_Try, /*On fail goto*//*Label 6467*/ GIMT_Encode4(474464), // Rule ID 4153 //
        GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasUnrestrictedSOffset),
        GIM_CheckConstantInt8, /*MI*/0, /*Op*/2, 0,
        GIM_CheckConstantInt8, /*MI*/0, /*Op*/3, 0,
        // MIs[0] offset
        GIM_CheckIsImm, /*MI*/0, /*Op*/5,
        // MIs[0] auxiliary
        GIM_CheckIsImm, /*MI*/0, /*Op*/6,
        // MIs[0] Operand 7
        GIM_CheckLiteralInt, /*MI*/0, /*Op*/7, GIMT_Encode8(0),
        GIM_CheckComplexPattern, /*MI*/0, /*Op*/4, /*Renderer*/GIMT_Encode2(0), GIMT_Encode2(GICP_gi_buf_soffset),
        // (SIbuffer_load:{ *:[v4i16] } v4i32:{ *:[v4i32] }:$rsrc, 0:{ *:[i32] }, 0:{ *:[i32] }, (BUFSOffset:{ *:[i32] } i32:{ *:[i32] }:$soffset), (timm:{ *:[i32] }):$offset, (timm:{ *:[i32] }):$auxiliary, 0:{ *:[i1] })  =>  (BUFFER_LOAD_DWORDX2_OFFSET:{ *:[v4i16] } SReg_128:{ *:[v4i32] }:$rsrc, SCSrc_b32:{ *:[i32] }:$soffset, (timm:{ *:[i32] }):$offset, (extract_cpol:{ *:[i32] } ?:{ *:[i32] }:$auxiliary), (extract_swz:{ *:[i1] } ?:{ *:[i32] }:$auxiliary))
        GIR_BuildMI, /*InsnID*/0, /*Opcode*/GIMT_Encode2(AMDGPU::BUFFER_LOAD_DWORDX2_OFFSET),
        GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/0, // DstI[vdata]
        GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/1, // rsrc
        GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/0, // soffset
        GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/5, // offset
        GIR_CustomOperandRenderer, /*InsnID*/0, /*OldInsnID*/0, /*OpIdx*/6, /*OperandRenderer*/GIMT_Encode2(GICR_renderExtractCPol), // auxiliary
        GIR_CustomOperandRenderer, /*InsnID*/0, /*OldInsnID*/0, /*OpIdx*/6, /*OperandRenderer*/GIMT_Encode2(GICR_renderExtractSWZ), // auxiliary
        GIR_MergeMemOperands, /*InsnID*/0, /*NumInsns*/1, /*MergeInsnID's*/0,
        GIR_ConstrainSelectedInstOperands, /*InsnID*/0,
        GIR_EraseFromParent, /*InsnID*/0,
        // GIR_Coverage, 4153,
        GIR_Done,
      // Label 6467: @474464
      GIM_Try, /*On fail goto*//*Label 6468*/ GIMT_Encode4(474543), // Rule ID 4157 //
        GIM_CheckConstantInt8, /*MI*/0, /*Op*/2, 0,
        GIM_CheckConstantInt8, /*MI*/0, /*Op*/3, 0,
        // MIs[0] offset
        GIM_CheckIsImm, /*MI*/0, /*Op*/5,
        // MIs[0] auxiliary
        GIM_CheckIsImm, /*MI*/0, /*Op*/6,
        // MIs[0] Operand 7
        GIM_CheckLiteralInt, /*MI*/0, /*Op*/7, GIMT_Encode8(0),
        GIM_CheckComplexPattern, /*MI*/0, /*Op*/4, /*Renderer*/GIMT_Encode2(0), GIMT_Encode2(GICP_gi_buf_soffset),
        // (SIbuffer_load:{ *:[v4i16] } v4i32:{ *:[v4i32] }:$rsrc, 0:{ *:[i32] }, 0:{ *:[i32] }, (BUFSOffset:{ *:[i32] } i32:{ *:[i32] }:$soffset), (timm:{ *:[i32] }):$offset, (timm:{ *:[i32] }):$auxiliary, 0:{ *:[i1] })  =>  (BUFFER_LOAD_DWORDX2_VBUFFER_OFFSET:{ *:[v4i16] } SReg_128:{ *:[v4i32] }:$rsrc, SCSrc_b32:{ *:[i32] }:$soffset, (timm:{ *:[i32] }):$offset, (extract_cpol:{ *:[i32] } ?:{ *:[i32] }:$auxiliary), (extract_swz:{ *:[i1] } ?:{ *:[i32] }:$auxiliary))
        GIR_BuildMI, /*InsnID*/0, /*Opcode*/GIMT_Encode2(AMDGPU::BUFFER_LOAD_DWORDX2_VBUFFER_OFFSET),
        GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/0, // DstI[vdata]
        GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/1, // rsrc
        GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/0, // soffset
        GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/5, // offset
        GIR_CustomOperandRenderer, /*InsnID*/0, /*OldInsnID*/0, /*OpIdx*/6, /*OperandRenderer*/GIMT_Encode2(GICR_renderExtractCPol), // auxiliary
        GIR_CustomOperandRenderer, /*InsnID*/0, /*OldInsnID*/0, /*OpIdx*/6, /*OperandRenderer*/GIMT_Encode2(GICR_renderExtractSWZ), // auxiliary
        GIR_MergeMemOperands, /*InsnID*/0, /*NumInsns*/1, /*MergeInsnID's*/0,
        GIR_ConstrainSelectedInstOperands, /*InsnID*/0,
        GIR_EraseFromParent, /*InsnID*/0,
        // GIR_Coverage, 4157,
        GIR_Done,
      // Label 6468: @474543
      GIM_Try, /*On fail goto*//*Label 6469*/ GIMT_Encode4(474625), // Rule ID 4161 //
        GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasUnrestrictedSOffset),
        GIM_CheckConstantInt8, /*MI*/0, /*Op*/2, 0,
        GIM_CheckConstantInt8, /*MI*/0, /*Op*/3, 0,
        // MIs[0] offset
        GIM_CheckIsImm, /*MI*/0, /*Op*/5,
        // MIs[0] auxiliary
        GIM_CheckIsImm, /*MI*/0, /*Op*/6,
        // MIs[0] Operand 7
        GIM_CheckLiteralInt, /*MI*/0, /*Op*/7, GIMT_Encode8(0),
        GIM_CheckComplexPattern, /*MI*/0, /*Op*/4, /*Renderer*/GIMT_Encode2(0), GIMT_Encode2(GICP_gi_buf_soffset),
        // (SIbuffer_load:{ *:[v4f16] } v4i32:{ *:[v4i32] }:$rsrc, 0:{ *:[i32] }, 0:{ *:[i32] }, (BUFSOffset:{ *:[i32] } i32:{ *:[i32] }:$soffset), (timm:{ *:[i32] }):$offset, (timm:{ *:[i32] }):$auxiliary, 0:{ *:[i1] })  =>  (BUFFER_LOAD_DWORDX2_OFFSET:{ *:[v4f16] } SReg_128:{ *:[v4i32] }:$rsrc, SCSrc_b32:{ *:[i32] }:$soffset, (timm:{ *:[i32] }):$offset, (extract_cpol:{ *:[i32] } ?:{ *:[i32] }:$auxiliary), (extract_swz:{ *:[i1] } ?:{ *:[i32] }:$auxiliary))
        GIR_BuildMI, /*InsnID*/0, /*Opcode*/GIMT_Encode2(AMDGPU::BUFFER_LOAD_DWORDX2_OFFSET),
        GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/0, // DstI[vdata]
        GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/1, // rsrc
        GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/0, // soffset
        GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/5, // offset
        GIR_CustomOperandRenderer, /*InsnID*/0, /*OldInsnID*/0, /*OpIdx*/6, /*OperandRenderer*/GIMT_Encode2(GICR_renderExtractCPol), // auxiliary
        GIR_CustomOperandRenderer, /*InsnID*/0, /*OldInsnID*/0, /*OpIdx*/6, /*OperandRenderer*/GIMT_Encode2(GICR_renderExtractSWZ), // auxiliary
        GIR_MergeMemOperands, /*InsnID*/0, /*NumInsns*/1, /*MergeInsnID's*/0,
        GIR_ConstrainSelectedInstOperands, /*InsnID*/0,
        GIR_EraseFromParent, /*InsnID*/0,
        // GIR_Coverage, 4161,
        GIR_Done,
      // Label 6469: @474625
      GIM_Try, /*On fail goto*//*Label 6470*/ GIMT_Encode4(474704), // Rule ID 4165 //
        GIM_CheckConstantInt8, /*MI*/0, /*Op*/2, 0,
        GIM_CheckConstantInt8, /*MI*/0, /*Op*/3, 0,
        // MIs[0] offset
        GIM_CheckIsImm, /*MI*/0, /*Op*/5,
        // MIs[0] auxiliary
        GIM_CheckIsImm, /*MI*/0, /*Op*/6,
        // MIs[0] Operand 7
        GIM_CheckLiteralInt, /*MI*/0, /*Op*/7, GIMT_Encode8(0),
        GIM_CheckComplexPattern, /*MI*/0, /*Op*/4, /*Renderer*/GIMT_Encode2(0), GIMT_Encode2(GICP_gi_buf_soffset),
        // (SIbuffer_load:{ *:[v4f16] } v4i32:{ *:[v4i32] }:$rsrc, 0:{ *:[i32] }, 0:{ *:[i32] }, (BUFSOffset:{ *:[i32] } i32:{ *:[i32] }:$soffset), (timm:{ *:[i32] }):$offset, (timm:{ *:[i32] }):$auxiliary, 0:{ *:[i1] })  =>  (BUFFER_LOAD_DWORDX2_VBUFFER_OFFSET:{ *:[v4f16] } SReg_128:{ *:[v4i32] }:$rsrc, SCSrc_b32:{ *:[i32] }:$soffset, (timm:{ *:[i32] }):$offset, (extract_cpol:{ *:[i32] } ?:{ *:[i32] }:$auxiliary), (extract_swz:{ *:[i1] } ?:{ *:[i32] }:$auxiliary))
        GIR_BuildMI, /*InsnID*/0, /*Opcode*/GIMT_Encode2(AMDGPU::BUFFER_LOAD_DWORDX2_VBUFFER_OFFSET),
        GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/0, // DstI[vdata]
        GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/1, // rsrc
        GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/0, // soffset
        GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/5, // offset
        GIR_CustomOperandRenderer, /*InsnID*/0, /*OldInsnID*/0, /*OpIdx*/6, /*OperandRenderer*/GIMT_Encode2(GICR_renderExtractCPol), // auxiliary
        GIR_CustomOperandRenderer, /*InsnID*/0, /*OldInsnID*/0, /*OpIdx*/6, /*OperandRenderer*/GIMT_Encode2(GICR_renderExtractSWZ), // auxiliary
        GIR_MergeMemOperands, /*InsnID*/0, /*NumInsns*/1, /*MergeInsnID's*/0,
        GIR_ConstrainSelectedInstOperands, /*InsnID*/0,
        GIR_EraseFromParent, /*InsnID*/0,
        // GIR_Coverage, 4165,
        GIR_Done,
      // Label 6470: @474704
      GIM_Try, /*On fail goto*//*Label 6471*/ GIMT_Encode4(474786), // Rule ID 4154 //
        GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasUnrestrictedSOffset),
        GIM_CheckConstantInt8, /*MI*/0, /*Op*/2, 0,
        // MIs[0] offset
        GIM_CheckIsImm, /*MI*/0, /*Op*/5,
        // MIs[0] auxiliary
        GIM_CheckIsImm, /*MI*/0, /*Op*/6,
        // MIs[0] Operand 7
        GIM_CheckLiteralInt, /*MI*/0, /*Op*/7, GIMT_Encode8(0),
        GIM_CheckComplexPattern, /*MI*/0, /*Op*/4, /*Renderer*/GIMT_Encode2(0), GIMT_Encode2(GICP_gi_buf_soffset),
        // (SIbuffer_load:{ *:[v4i16] } v4i32:{ *:[v4i32] }:$rsrc, 0:{ *:[i32] }, i32:{ *:[i32] }:$voffset, (BUFSOffset:{ *:[i32] } i32:{ *:[i32] }:$soffset), (timm:{ *:[i32] }):$offset, (timm:{ *:[i32] }):$auxiliary, 0:{ *:[i1] })  =>  (BUFFER_LOAD_DWORDX2_OFFEN:{ *:[v4i16] } VGPR_32:{ *:[i32] }:$voffset, SReg_128:{ *:[v4i32] }:$rsrc, SCSrc_b32:{ *:[i32] }:$soffset, (timm:{ *:[i32] }):$offset, (extract_cpol:{ *:[i32] } ?:{ *:[i32] }:$auxiliary), (extract_swz:{ *:[i1] } ?:{ *:[i32] }:$auxiliary))
        GIR_BuildMI, /*InsnID*/0, /*Opcode*/GIMT_Encode2(AMDGPU::BUFFER_LOAD_DWORDX2_OFFEN),
        GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/0, // DstI[vdata]
        GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/3, // voffset
        GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/1, // rsrc
        GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/0, // soffset
        GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/5, // offset
        GIR_CustomOperandRenderer, /*InsnID*/0, /*OldInsnID*/0, /*OpIdx*/6, /*OperandRenderer*/GIMT_Encode2(GICR_renderExtractCPol), // auxiliary
        GIR_CustomOperandRenderer, /*InsnID*/0, /*OldInsnID*/0, /*OpIdx*/6, /*OperandRenderer*/GIMT_Encode2(GICR_renderExtractSWZ), // auxiliary
        GIR_MergeMemOperands, /*InsnID*/0, /*NumInsns*/1, /*MergeInsnID's*/0,
        GIR_ConstrainSelectedInstOperands, /*InsnID*/0,
        GIR_EraseFromParent, /*InsnID*/0,
        // GIR_Coverage, 4154,
        GIR_Done,
      // Label 6471: @474786
      GIM_Try, /*On fail goto*//*Label 6472*/ GIMT_Encode4(474865), // Rule ID 4158 //
        GIM_CheckConstantInt8, /*MI*/0, /*Op*/2, 0,
        // MIs[0] offset
        GIM_CheckIsImm, /*MI*/0, /*Op*/5,
        // MIs[0] auxiliary
        GIM_CheckIsImm, /*MI*/0, /*Op*/6,
        // MIs[0] Operand 7
        GIM_CheckLiteralInt, /*MI*/0, /*Op*/7, GIMT_Encode8(0),
        GIM_CheckComplexPattern, /*MI*/0, /*Op*/4, /*Renderer*/GIMT_Encode2(0), GIMT_Encode2(GICP_gi_buf_soffset),
        // (SIbuffer_load:{ *:[v4i16] } v4i32:{ *:[v4i32] }:$rsrc, 0:{ *:[i32] }, i32:{ *:[i32] }:$voffset, (BUFSOffset:{ *:[i32] } i32:{ *:[i32] }:$soffset), (timm:{ *:[i32] }):$offset, (timm:{ *:[i32] }):$auxiliary, 0:{ *:[i1] })  =>  (BUFFER_LOAD_DWORDX2_VBUFFER_OFFEN:{ *:[v4i16] } VGPR_32:{ *:[i32] }:$voffset, SReg_128:{ *:[v4i32] }:$rsrc, SCSrc_b32:{ *:[i32] }:$soffset, (timm:{ *:[i32] }):$offset, (extract_cpol:{ *:[i32] } ?:{ *:[i32] }:$auxiliary), (extract_swz:{ *:[i1] } ?:{ *:[i32] }:$auxiliary))
        GIR_BuildMI, /*InsnID*/0, /*Opcode*/GIMT_Encode2(AMDGPU::BUFFER_LOAD_DWORDX2_VBUFFER_OFFEN),
        GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/0, // DstI[vdata]
        GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/3, // voffset
        GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/1, // rsrc
        GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/0, // soffset
        GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/5, // offset
        GIR_CustomOperandRenderer, /*InsnID*/0, /*OldInsnID*/0, /*OpIdx*/6, /*OperandRenderer*/GIMT_Encode2(GICR_renderExtractCPol), // auxiliary
        GIR_CustomOperandRenderer, /*InsnID*/0, /*OldInsnID*/0, /*OpIdx*/6, /*OperandRenderer*/GIMT_Encode2(GICR_renderExtractSWZ), // auxiliary
        GIR_MergeMemOperands, /*InsnID*/0, /*NumInsns*/1, /*MergeInsnID's*/0,
        GIR_ConstrainSelectedInstOperands, /*InsnID*/0,
        GIR_EraseFromParent, /*InsnID*/0,
        // GIR_Coverage, 4158,
        GIR_Done,
      // Label 6472: @474865
      GIM_Try, /*On fail goto*//*Label 6473*/ GIMT_Encode4(474947), // Rule ID 4162 //
        GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasUnrestrictedSOffset),
        GIM_CheckConstantInt8, /*MI*/0, /*Op*/2, 0,
        // MIs[0] offset
        GIM_CheckIsImm, /*MI*/0, /*Op*/5,
        // MIs[0] auxiliary
        GIM_CheckIsImm, /*MI*/0, /*Op*/6,
        // MIs[0] Operand 7
        GIM_CheckLiteralInt, /*MI*/0, /*Op*/7, GIMT_Encode8(0),
        GIM_CheckComplexPattern, /*MI*/0, /*Op*/4, /*Renderer*/GIMT_Encode2(0), GIMT_Encode2(GICP_gi_buf_soffset),
        // (SIbuffer_load:{ *:[v4f16] } v4i32:{ *:[v4i32] }:$rsrc, 0:{ *:[i32] }, i32:{ *:[i32] }:$voffset, (BUFSOffset:{ *:[i32] } i32:{ *:[i32] }:$soffset), (timm:{ *:[i32] }):$offset, (timm:{ *:[i32] }):$auxiliary, 0:{ *:[i1] })  =>  (BUFFER_LOAD_DWORDX2_OFFEN:{ *:[v4f16] } VGPR_32:{ *:[i32] }:$voffset, SReg_128:{ *:[v4i32] }:$rsrc, SCSrc_b32:{ *:[i32] }:$soffset, (timm:{ *:[i32] }):$offset, (extract_cpol:{ *:[i32] } ?:{ *:[i32] }:$auxiliary), (extract_swz:{ *:[i1] } ?:{ *:[i32] }:$auxiliary))
        GIR_BuildMI, /*InsnID*/0, /*Opcode*/GIMT_Encode2(AMDGPU::BUFFER_LOAD_DWORDX2_OFFEN),
        GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/0, // DstI[vdata]
        GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/3, // voffset
        GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/1, // rsrc
        GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/0, // soffset
        GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/5, // offset
        GIR_CustomOperandRenderer, /*InsnID*/0, /*OldInsnID*/0, /*OpIdx*/6, /*OperandRenderer*/GIMT_Encode2(GICR_renderExtractCPol), // auxiliary
        GIR_CustomOperandRenderer, /*InsnID*/0, /*OldInsnID*/0, /*OpIdx*/6, /*OperandRenderer*/GIMT_Encode2(GICR_renderExtractSWZ), // auxiliary
        GIR_MergeMemOperands, /*InsnID*/0, /*NumInsns*/1, /*MergeInsnID's*/0,
        GIR_ConstrainSelectedInstOperands, /*InsnID*/0,
        GIR_EraseFromParent, /*InsnID*/0,
        // GIR_Coverage, 4162,
        GIR_Done,
      // Label 6473: @474947
      GIM_Try, /*On fail goto*//*Label 6474*/ GIMT_Encode4(475026), // Rule ID 4166 //
        GIM_CheckConstantInt8, /*MI*/0, /*Op*/2, 0,
        // MIs[0] offset
        GIM_CheckIsImm, /*MI*/0, /*Op*/5,
        // MIs[0] auxiliary
        GIM_CheckIsImm, /*MI*/0, /*Op*/6,
        // MIs[0] Operand 7
        GIM_CheckLiteralInt, /*MI*/0, /*Op*/7, GIMT_Encode8(0),
        GIM_CheckComplexPattern, /*MI*/0, /*Op*/4, /*Renderer*/GIMT_Encode2(0), GIMT_Encode2(GICP_gi_buf_soffset),
        // (SIbuffer_load:{ *:[v4f16] } v4i32:{ *:[v4i32] }:$rsrc, 0:{ *:[i32] }, i32:{ *:[i32] }:$voffset, (BUFSOffset:{ *:[i32] } i32:{ *:[i32] }:$soffset), (timm:{ *:[i32] }):$offset, (timm:{ *:[i32] }):$auxiliary, 0:{ *:[i1] })  =>  (BUFFER_LOAD_DWORDX2_VBUFFER_OFFEN:{ *:[v4f16] } VGPR_32:{ *:[i32] }:$voffset, SReg_128:{ *:[v4i32] }:$rsrc, SCSrc_b32:{ *:[i32] }:$soffset, (timm:{ *:[i32] }):$offset, (extract_cpol:{ *:[i32] } ?:{ *:[i32] }:$auxiliary), (extract_swz:{ *:[i1] } ?:{ *:[i32] }:$auxiliary))
        GIR_BuildMI, /*InsnID*/0, /*Opcode*/GIMT_Encode2(AMDGPU::BUFFER_LOAD_DWORDX2_VBUFFER_OFFEN),
        GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/0, // DstI[vdata]
        GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/3, // voffset
        GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/1, // rsrc
        GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/0, // soffset
        GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/5, // offset
        GIR_CustomOperandRenderer, /*InsnID*/0, /*OldInsnID*/0, /*OpIdx*/6, /*OperandRenderer*/GIMT_Encode2(GICR_renderExtractCPol), // auxiliary
        GIR_CustomOperandRenderer, /*InsnID*/0, /*OldInsnID*/0, /*OpIdx*/6, /*OperandRenderer*/GIMT_Encode2(GICR_renderExtractSWZ), // auxiliary
        GIR_MergeMemOperands, /*InsnID*/0, /*NumInsns*/1, /*MergeInsnID's*/0,
        GIR_ConstrainSelectedInstOperands, /*InsnID*/0,
        GIR_EraseFromParent, /*InsnID*/0,
        // GIR_Coverage, 4166,
        GIR_Done,
      // Label 6474: @475026
      GIM_Try, /*On fail goto*//*Label 6475*/ GIMT_Encode4(475100), // Rule ID 4155 //
        GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasUnrestrictedSOffset),
        GIM_CheckConstantInt8, /*MI*/0, /*Op*/3, 0,
        // MIs[0] offset
        GIM_CheckIsImm, /*MI*/0, /*Op*/5,
        // MIs[0] auxiliary
        GIM_CheckIsImm, /*MI*/0, /*Op*/6,
        // MIs[0] Operand 7
        GIM_CheckIsImm, /*MI*/0, /*Op*/7,
        GIM_CheckComplexPattern, /*MI*/0, /*Op*/4, /*Renderer*/GIMT_Encode2(0), GIMT_Encode2(GICP_gi_buf_soffset),
        // (SIbuffer_load:{ *:[v4i16] } v4i32:{ *:[v4i32] }:$rsrc, i32:{ *:[i32] }:$vindex, 0:{ *:[i32] }, (BUFSOffset:{ *:[i32] } i32:{ *:[i32] }:$soffset), (timm:{ *:[i32] }):$offset, (timm:{ *:[i32] }):$auxiliary, (timm:{ *:[i1] }))  =>  (BUFFER_LOAD_DWORDX2_IDXEN:{ *:[v4i16] } VGPR_32:{ *:[i32] }:$vindex, SReg_128:{ *:[v4i32] }:$rsrc, SCSrc_b32:{ *:[i32] }:$soffset, (timm:{ *:[i32] }):$offset, (extract_cpol:{ *:[i32] } ?:{ *:[i32] }:$auxiliary), (extract_swz:{ *:[i1] } ?:{ *:[i32] }:$auxiliary))
        GIR_BuildMI, /*InsnID*/0, /*Opcode*/GIMT_Encode2(AMDGPU::BUFFER_LOAD_DWORDX2_IDXEN),
        GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/0, // DstI[vdata]
        GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/2, // vindex
        GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/1, // rsrc
        GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/0, // soffset
        GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/5, // offset
        GIR_CustomOperandRenderer, /*InsnID*/0, /*OldInsnID*/0, /*OpIdx*/6, /*OperandRenderer*/GIMT_Encode2(GICR_renderExtractCPol), // auxiliary
        GIR_CustomOperandRenderer, /*InsnID*/0, /*OldInsnID*/0, /*OpIdx*/6, /*OperandRenderer*/GIMT_Encode2(GICR_renderExtractSWZ), // auxiliary
        GIR_MergeMemOperands, /*InsnID*/0, /*NumInsns*/1, /*MergeInsnID's*/0,
        GIR_ConstrainSelectedInstOperands, /*InsnID*/0,
        GIR_EraseFromParent, /*InsnID*/0,
        // GIR_Coverage, 4155,
        GIR_Done,
      // Label 6475: @475100
      GIM_Try, /*On fail goto*//*Label 6476*/ GIMT_Encode4(475171), // Rule ID 4159 //
        GIM_CheckConstantInt8, /*MI*/0, /*Op*/3, 0,
        // MIs[0] offset
        GIM_CheckIsImm, /*MI*/0, /*Op*/5,
        // MIs[0] auxiliary
        GIM_CheckIsImm, /*MI*/0, /*Op*/6,
        // MIs[0] Operand 7
        GIM_CheckIsImm, /*MI*/0, /*Op*/7,
        GIM_CheckComplexPattern, /*MI*/0, /*Op*/4, /*Renderer*/GIMT_Encode2(0), GIMT_Encode2(GICP_gi_buf_soffset),
        // (SIbuffer_load:{ *:[v4i16] } v4i32:{ *:[v4i32] }:$rsrc, i32:{ *:[i32] }:$vindex, 0:{ *:[i32] }, (BUFSOffset:{ *:[i32] } i32:{ *:[i32] }:$soffset), (timm:{ *:[i32] }):$offset, (timm:{ *:[i32] }):$auxiliary, (timm:{ *:[i1] }))  =>  (BUFFER_LOAD_DWORDX2_VBUFFER_IDXEN:{ *:[v4i16] } VGPR_32:{ *:[i32] }:$vindex, SReg_128:{ *:[v4i32] }:$rsrc, SCSrc_b32:{ *:[i32] }:$soffset, (timm:{ *:[i32] }):$offset, (extract_cpol:{ *:[i32] } ?:{ *:[i32] }:$auxiliary), (extract_swz:{ *:[i1] } ?:{ *:[i32] }:$auxiliary))
        GIR_BuildMI, /*InsnID*/0, /*Opcode*/GIMT_Encode2(AMDGPU::BUFFER_LOAD_DWORDX2_VBUFFER_IDXEN),
        GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/0, // DstI[vdata]
        GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/2, // vindex
        GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/1, // rsrc
        GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/0, // soffset
        GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/5, // offset
        GIR_CustomOperandRenderer, /*InsnID*/0, /*OldInsnID*/0, /*OpIdx*/6, /*OperandRenderer*/GIMT_Encode2(GICR_renderExtractCPol), // auxiliary
        GIR_CustomOperandRenderer, /*InsnID*/0, /*OldInsnID*/0, /*OpIdx*/6, /*OperandRenderer*/GIMT_Encode2(GICR_renderExtractSWZ), // auxiliary
        GIR_MergeMemOperands, /*InsnID*/0, /*NumInsns*/1, /*MergeInsnID's*/0,
        GIR_ConstrainSelectedInstOperands, /*InsnID*/0,
        GIR_EraseFromParent, /*InsnID*/0,
        // GIR_Coverage, 4159,
        GIR_Done,
      // Label 6476: @475171
      GIM_Try, /*On fail goto*//*Label 6477*/ GIMT_Encode4(475245), // Rule ID 4163 //
        GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasUnrestrictedSOffset),
        GIM_CheckConstantInt8, /*MI*/0, /*Op*/3, 0,
        // MIs[0] offset
        GIM_CheckIsImm, /*MI*/0, /*Op*/5,
        // MIs[0] auxiliary
        GIM_CheckIsImm, /*MI*/0, /*Op*/6,
        // MIs[0] Operand 7
        GIM_CheckIsImm, /*MI*/0, /*Op*/7,
        GIM_CheckComplexPattern, /*MI*/0, /*Op*/4, /*Renderer*/GIMT_Encode2(0), GIMT_Encode2(GICP_gi_buf_soffset),
        // (SIbuffer_load:{ *:[v4f16] } v4i32:{ *:[v4i32] }:$rsrc, i32:{ *:[i32] }:$vindex, 0:{ *:[i32] }, (BUFSOffset:{ *:[i32] } i32:{ *:[i32] }:$soffset), (timm:{ *:[i32] }):$offset, (timm:{ *:[i32] }):$auxiliary, (timm:{ *:[i1] }))  =>  (BUFFER_LOAD_DWORDX2_IDXEN:{ *:[v4f16] } VGPR_32:{ *:[i32] }:$vindex, SReg_128:{ *:[v4i32] }:$rsrc, SCSrc_b32:{ *:[i32] }:$soffset, (timm:{ *:[i32] }):$offset, (extract_cpol:{ *:[i32] } ?:{ *:[i32] }:$auxiliary), (extract_swz:{ *:[i1] } ?:{ *:[i32] }:$auxiliary))
        GIR_BuildMI, /*InsnID*/0, /*Opcode*/GIMT_Encode2(AMDGPU::BUFFER_LOAD_DWORDX2_IDXEN),
        GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/0, // DstI[vdata]
        GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/2, // vindex
        GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/1, // rsrc
        GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/0, // soffset
        GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/5, // offset
        GIR_CustomOperandRenderer, /*InsnID*/0, /*OldInsnID*/0, /*OpIdx*/6, /*OperandRenderer*/GIMT_Encode2(GICR_renderExtractCPol), // auxiliary
        GIR_CustomOperandRenderer, /*InsnID*/0, /*OldInsnID*/0, /*OpIdx*/6, /*OperandRenderer*/GIMT_Encode2(GICR_renderExtractSWZ), // auxiliary
        GIR_MergeMemOperands, /*InsnID*/0, /*NumInsns*/1, /*MergeInsnID's*/0,
        GIR_ConstrainSelectedInstOperands, /*InsnID*/0,
        GIR_EraseFromParent, /*InsnID*/0,
        // GIR_Coverage, 4163,
        GIR_Done,
      // Label 6477: @475245
      GIM_Try, /*On fail goto*//*Label 6478*/ GIMT_Encode4(475316), // Rule ID 4167 //
        GIM_CheckConstantInt8, /*MI*/0, /*Op*/3, 0,
        // MIs[0] offset
        GIM_CheckIsImm, /*MI*/0, /*Op*/5,
        // MIs[0] auxiliary
        GIM_CheckIsImm, /*MI*/0, /*Op*/6,
        // MIs[0] Operand 7
        GIM_CheckIsImm, /*MI*/0, /*Op*/7,
        GIM_CheckComplexPattern, /*MI*/0, /*Op*/4, /*Renderer*/GIMT_Encode2(0), GIMT_Encode2(GICP_gi_buf_soffset),
        // (SIbuffer_load:{ *:[v4f16] } v4i32:{ *:[v4i32] }:$rsrc, i32:{ *:[i32] }:$vindex, 0:{ *:[i32] }, (BUFSOffset:{ *:[i32] } i32:{ *:[i32] }:$soffset), (timm:{ *:[i32] }):$offset, (timm:{ *:[i32] }):$auxiliary, (timm:{ *:[i1] }))  =>  (BUFFER_LOAD_DWORDX2_VBUFFER_IDXEN:{ *:[v4f16] } VGPR_32:{ *:[i32] }:$vindex, SReg_128:{ *:[v4i32] }:$rsrc, SCSrc_b32:{ *:[i32] }:$soffset, (timm:{ *:[i32] }):$offset, (extract_cpol:{ *:[i32] } ?:{ *:[i32] }:$auxiliary), (extract_swz:{ *:[i1] } ?:{ *:[i32] }:$auxiliary))
        GIR_BuildMI, /*InsnID*/0, /*Opcode*/GIMT_Encode2(AMDGPU::BUFFER_LOAD_DWORDX2_VBUFFER_IDXEN),
        GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/0, // DstI[vdata]
        GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/2, // vindex
        GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/1, // rsrc
        GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/0, // soffset
        GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/5, // offset
        GIR_CustomOperandRenderer, /*InsnID*/0, /*OldInsnID*/0, /*OpIdx*/6, /*OperandRenderer*/GIMT_Encode2(GICR_renderExtractCPol), // auxiliary
        GIR_CustomOperandRenderer, /*InsnID*/0, /*OldInsnID*/0, /*OpIdx*/6, /*OperandRenderer*/GIMT_Encode2(GICR_renderExtractSWZ), // auxiliary
        GIR_MergeMemOperands, /*InsnID*/0, /*NumInsns*/1, /*MergeInsnID's*/0,
        GIR_ConstrainSelectedInstOperands, /*InsnID*/0,
        GIR_EraseFromParent, /*InsnID*/0,
        // GIR_Coverage, 4167,
        GIR_Done,
      // Label 6478: @475316
      GIM_Try, /*On fail goto*//*Label 6479*/ GIMT_Encode4(475426), // Rule ID 4156 //
        GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasUnrestrictedSOffset),
        // MIs[0] offset
        GIM_CheckIsImm, /*MI*/0, /*Op*/5,
        // MIs[0] auxiliary
        GIM_CheckIsImm, /*MI*/0, /*Op*/6,
        // MIs[0] Operand 7
        GIM_CheckIsImm, /*MI*/0, /*Op*/7,
        GIM_CheckComplexPattern, /*MI*/0, /*Op*/4, /*Renderer*/GIMT_Encode2(0), GIMT_Encode2(GICP_gi_buf_soffset),
        // (SIbuffer_load:{ *:[v4i16] } v4i32:{ *:[v4i32] }:$rsrc, i32:{ *:[i32] }:$vindex, i32:{ *:[i32] }:$voffset, (BUFSOffset:{ *:[i32] } i32:{ *:[i32] }:$soffset), (timm:{ *:[i32] }):$offset, (timm:{ *:[i32] }):$auxiliary, (timm:{ *:[i1] }))  =>  (BUFFER_LOAD_DWORDX2_BOTHEN:{ *:[v4i16] } (REG_SEQUENCE:{ *:[i64] } VReg_64:{ *:[i32] }, VGPR_32:{ *:[i32] }:$vindex, sub0:{ *:[i32] }, VGPR_32:{ *:[i32] }:$voffset, sub1:{ *:[i32] }), SReg_128:{ *:[v4i32] }:$rsrc, SCSrc_b32:{ *:[i32] }:$soffset, (timm:{ *:[i32] }):$offset, (extract_cpol:{ *:[i32] } ?:{ *:[i32] }:$auxiliary), (extract_swz:{ *:[i1] } ?:{ *:[i32] }:$auxiliary))
        GIR_MakeTempReg, /*TempRegID*/0, /*TypeID*/GILLT_s64,
        GIR_BuildMI, /*InsnID*/1, /*Opcode*/GIMT_Encode2(TargetOpcode::REG_SEQUENCE),
        GIR_AddTempRegister, /*InsnID*/1, /*TempRegID*/0, /*TempRegFlags*/GIMT_Encode2(RegState::Define),
        GIR_Copy, /*NewInsnID*/1, /*OldInsnID*/0, /*OpIdx*/2, // vindex
        GIR_AddImm8, /*InsnID*/1, /*SubRegIndex*/3,
        GIR_Copy, /*NewInsnID*/1, /*OldInsnID*/0, /*OpIdx*/3, // voffset
        GIR_AddImm8, /*InsnID*/1, /*SubRegIndex*/11,
        GIR_ConstrainOperandRC, /*InsnID*/1, /*Op*/0, GIMT_Encode2(AMDGPU::VReg_64RegClassID),
        GIR_ConstrainOperandRC, /*InsnID*/1, /*Op*/1, GIMT_Encode2(AMDGPU::VGPR_32RegClassID),
        GIR_ConstrainOperandRC, /*InsnID*/1, /*Op*/3, GIMT_Encode2(AMDGPU::VGPR_32RegClassID),
        GIR_BuildMI, /*InsnID*/0, /*Opcode*/GIMT_Encode2(AMDGPU::BUFFER_LOAD_DWORDX2_BOTHEN),
        GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/0, // DstI[vdata]
        GIR_AddSimpleTempRegister, /*InsnID*/0, /*TempRegID*/0,
        GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/1, // rsrc
        GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/0, // soffset
        GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/5, // offset
        GIR_CustomOperandRenderer, /*InsnID*/0, /*OldInsnID*/0, /*OpIdx*/6, /*OperandRenderer*/GIMT_Encode2(GICR_renderExtractCPol), // auxiliary
        GIR_CustomOperandRenderer, /*InsnID*/0, /*OldInsnID*/0, /*OpIdx*/6, /*OperandRenderer*/GIMT_Encode2(GICR_renderExtractSWZ), // auxiliary
        GIR_MergeMemOperands, /*InsnID*/0, /*NumInsns*/1, /*MergeInsnID's*/0,
        GIR_ConstrainSelectedInstOperands, /*InsnID*/0,
        GIR_EraseFromParent, /*InsnID*/0,
        // GIR_Coverage, 4156,
        GIR_Done,
      // Label 6479: @475426
      GIM_Try, /*On fail goto*//*Label 6480*/ GIMT_Encode4(475533), // Rule ID 4160 //
        // MIs[0] offset
        GIM_CheckIsImm, /*MI*/0, /*Op*/5,
        // MIs[0] auxiliary
        GIM_CheckIsImm, /*MI*/0, /*Op*/6,
        // MIs[0] Operand 7
        GIM_CheckIsImm, /*MI*/0, /*Op*/7,
        GIM_CheckComplexPattern, /*MI*/0, /*Op*/4, /*Renderer*/GIMT_Encode2(0), GIMT_Encode2(GICP_gi_buf_soffset),
        // (SIbuffer_load:{ *:[v4i16] } v4i32:{ *:[v4i32] }:$rsrc, i32:{ *:[i32] }:$vindex, i32:{ *:[i32] }:$voffset, (BUFSOffset:{ *:[i32] } i32:{ *:[i32] }:$soffset), (timm:{ *:[i32] }):$offset, (timm:{ *:[i32] }):$auxiliary, (timm:{ *:[i1] }))  =>  (BUFFER_LOAD_DWORDX2_VBUFFER_BOTHEN:{ *:[v4i16] } (REG_SEQUENCE:{ *:[i64] } VReg_64:{ *:[i32] }, VGPR_32:{ *:[i32] }:$vindex, sub0:{ *:[i32] }, VGPR_32:{ *:[i32] }:$voffset, sub1:{ *:[i32] }), SReg_128:{ *:[v4i32] }:$rsrc, SCSrc_b32:{ *:[i32] }:$soffset, (timm:{ *:[i32] }):$offset, (extract_cpol:{ *:[i32] } ?:{ *:[i32] }:$auxiliary), (extract_swz:{ *:[i1] } ?:{ *:[i32] }:$auxiliary))
        GIR_MakeTempReg, /*TempRegID*/0, /*TypeID*/GILLT_s64,
        GIR_BuildMI, /*InsnID*/1, /*Opcode*/GIMT_Encode2(TargetOpcode::REG_SEQUENCE),
        GIR_AddTempRegister, /*InsnID*/1, /*TempRegID*/0, /*TempRegFlags*/GIMT_Encode2(RegState::Define),
        GIR_Copy, /*NewInsnID*/1, /*OldInsnID*/0, /*OpIdx*/2, // vindex
        GIR_AddImm8, /*InsnID*/1, /*SubRegIndex*/3,
        GIR_Copy, /*NewInsnID*/1, /*OldInsnID*/0, /*OpIdx*/3, // voffset
        GIR_AddImm8, /*InsnID*/1, /*SubRegIndex*/11,
        GIR_ConstrainOperandRC, /*InsnID*/1, /*Op*/0, GIMT_Encode2(AMDGPU::VReg_64RegClassID),
        GIR_ConstrainOperandRC, /*InsnID*/1, /*Op*/1, GIMT_Encode2(AMDGPU::VGPR_32RegClassID),
        GIR_ConstrainOperandRC, /*InsnID*/1, /*Op*/3, GIMT_Encode2(AMDGPU::VGPR_32RegClassID),
        GIR_BuildMI, /*InsnID*/0, /*Opcode*/GIMT_Encode2(AMDGPU::BUFFER_LOAD_DWORDX2_VBUFFER_BOTHEN),
        GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/0, // DstI[vdata]
        GIR_AddSimpleTempRegister, /*InsnID*/0, /*TempRegID*/0,
        GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/1, // rsrc
        GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/0, // soffset
        GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/5, // offset
        GIR_CustomOperandRenderer, /*InsnID*/0, /*OldInsnID*/0, /*OpIdx*/6, /*OperandRenderer*/GIMT_Encode2(GICR_renderExtractCPol), // auxiliary
        GIR_CustomOperandRenderer, /*InsnID*/0, /*OldInsnID*/0, /*OpIdx*/6, /*OperandRenderer*/GIMT_Encode2(GICR_renderExtractSWZ), // auxiliary
        GIR_MergeMemOperands, /*InsnID*/0, /*NumInsns*/1, /*MergeInsnID's*/0,
        GIR_ConstrainSelectedInstOperands, /*InsnID*/0,
        GIR_EraseFromParent, /*InsnID*/0,
        // GIR_Coverage, 4160,
        GIR_Done,
      // Label 6480: @475533
      GIM_Try, /*On fail goto*//*Label 6481*/ GIMT_Encode4(475643), // Rule ID 4164 //
        GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasUnrestrictedSOffset),
        // MIs[0] offset
        GIM_CheckIsImm, /*MI*/0, /*Op*/5,
        // MIs[0] auxiliary
        GIM_CheckIsImm, /*MI*/0, /*Op*/6,
        // MIs[0] Operand 7
        GIM_CheckIsImm, /*MI*/0, /*Op*/7,
        GIM_CheckComplexPattern, /*MI*/0, /*Op*/4, /*Renderer*/GIMT_Encode2(0), GIMT_Encode2(GICP_gi_buf_soffset),
        // (SIbuffer_load:{ *:[v4f16] } v4i32:{ *:[v4i32] }:$rsrc, i32:{ *:[i32] }:$vindex, i32:{ *:[i32] }:$voffset, (BUFSOffset:{ *:[i32] } i32:{ *:[i32] }:$soffset), (timm:{ *:[i32] }):$offset, (timm:{ *:[i32] }):$auxiliary, (timm:{ *:[i1] }))  =>  (BUFFER_LOAD_DWORDX2_BOTHEN:{ *:[v4f16] } (REG_SEQUENCE:{ *:[i64] } VReg_64:{ *:[i32] }, VGPR_32:{ *:[i32] }:$vindex, sub0:{ *:[i32] }, VGPR_32:{ *:[i32] }:$voffset, sub1:{ *:[i32] }), SReg_128:{ *:[v4i32] }:$rsrc, SCSrc_b32:{ *:[i32] }:$soffset, (timm:{ *:[i32] }):$offset, (extract_cpol:{ *:[i32] } ?:{ *:[i32] }:$auxiliary), (extract_swz:{ *:[i1] } ?:{ *:[i32] }:$auxiliary))
        GIR_MakeTempReg, /*TempRegID*/0, /*TypeID*/GILLT_s64,
        GIR_BuildMI, /*InsnID*/1, /*Opcode*/GIMT_Encode2(TargetOpcode::REG_SEQUENCE),
        GIR_AddTempRegister, /*InsnID*/1, /*TempRegID*/0, /*TempRegFlags*/GIMT_Encode2(RegState::Define),
        GIR_Copy, /*NewInsnID*/1, /*OldInsnID*/0, /*OpIdx*/2, // vindex
        GIR_AddImm8, /*InsnID*/1, /*SubRegIndex*/3,
        GIR_Copy, /*NewInsnID*/1, /*OldInsnID*/0, /*OpIdx*/3, // voffset
        GIR_AddImm8, /*InsnID*/1, /*SubRegIndex*/11,
        GIR_ConstrainOperandRC, /*InsnID*/1, /*Op*/0, GIMT_Encode2(AMDGPU::VReg_64RegClassID),
        GIR_ConstrainOperandRC, /*InsnID*/1, /*Op*/1, GIMT_Encode2(AMDGPU::VGPR_32RegClassID),
        GIR_ConstrainOperandRC, /*InsnID*/1, /*Op*/3, GIMT_Encode2(AMDGPU::VGPR_32RegClassID),
        GIR_BuildMI, /*InsnID*/0, /*Opcode*/GIMT_Encode2(AMDGPU::BUFFER_LOAD_DWORDX2_BOTHEN),
        GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/0, // DstI[vdata]
        GIR_AddSimpleTempRegister, /*InsnID*/0, /*TempRegID*/0,
        GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/1, // rsrc
        GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/0, // soffset
        GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/5, // offset
        GIR_CustomOperandRenderer, /*InsnID*/0, /*OldInsnID*/0, /*OpIdx*/6, /*OperandRenderer*/GIMT_Encode2(GICR_renderExtractCPol), // auxiliary
        GIR_CustomOperandRenderer, /*InsnID*/0, /*OldInsnID*/0, /*OpIdx*/6, /*OperandRenderer*/GIMT_Encode2(GICR_renderExtractSWZ), // auxiliary
        GIR_MergeMemOperands, /*InsnID*/0, /*NumInsns*/1, /*MergeInsnID's*/0,
        GIR_ConstrainSelectedInstOperands, /*InsnID*/0,
        GIR_EraseFromParent, /*InsnID*/0,
        // GIR_Coverage, 4164,
        GIR_Done,
      // Label 6481: @475643
      GIM_Try, /*On fail goto*//*Label 6482*/ GIMT_Encode4(475750), // Rule ID 4168 //
        // MIs[0] offset
        GIM_CheckIsImm, /*MI*/0, /*Op*/5,
        // MIs[0] auxiliary
        GIM_CheckIsImm, /*MI*/0, /*Op*/6,
        // MIs[0] Operand 7
        GIM_CheckIsImm, /*MI*/0, /*Op*/7,
        GIM_CheckComplexPattern, /*MI*/0, /*Op*/4, /*Renderer*/GIMT_Encode2(0), GIMT_Encode2(GICP_gi_buf_soffset),
        // (SIbuffer_load:{ *:[v4f16] } v4i32:{ *:[v4i32] }:$rsrc, i32:{ *:[i32] }:$vindex, i32:{ *:[i32] }:$voffset, (BUFSOffset:{ *:[i32] } i32:{ *:[i32] }:$soffset), (timm:{ *:[i32] }):$offset, (timm:{ *:[i32] }):$auxiliary, (timm:{ *:[i1] }))  =>  (BUFFER_LOAD_DWORDX2_VBUFFER_BOTHEN:{ *:[v4f16] } (REG_SEQUENCE:{ *:[i64] } VReg_64:{ *:[i32] }, VGPR_32:{ *:[i32] }:$vindex, sub0:{ *:[i32] }, VGPR_32:{ *:[i32] }:$voffset, sub1:{ *:[i32] }), SReg_128:{ *:[v4i32] }:$rsrc, SCSrc_b32:{ *:[i32] }:$soffset, (timm:{ *:[i32] }):$offset, (extract_cpol:{ *:[i32] } ?:{ *:[i32] }:$auxiliary), (extract_swz:{ *:[i1] } ?:{ *:[i32] }:$auxiliary))
        GIR_MakeTempReg, /*TempRegID*/0, /*TypeID*/GILLT_s64,
        GIR_BuildMI, /*InsnID*/1, /*Opcode*/GIMT_Encode2(TargetOpcode::REG_SEQUENCE),
        GIR_AddTempRegister, /*InsnID*/1, /*TempRegID*/0, /*TempRegFlags*/GIMT_Encode2(RegState::Define),
        GIR_Copy, /*NewInsnID*/1, /*OldInsnID*/0, /*OpIdx*/2, // vindex
        GIR_AddImm8, /*InsnID*/1, /*SubRegIndex*/3,
        GIR_Copy, /*NewInsnID*/1, /*OldInsnID*/0, /*OpIdx*/3, // voffset
        GIR_AddImm8, /*InsnID*/1, /*SubRegIndex*/11,
        GIR_ConstrainOperandRC, /*InsnID*/1, /*Op*/0, GIMT_Encode2(AMDGPU::VReg_64RegClassID),
        GIR_ConstrainOperandRC, /*InsnID*/1, /*Op*/1, GIMT_Encode2(AMDGPU::VGPR_32RegClassID),
        GIR_ConstrainOperandRC, /*InsnID*/1, /*Op*/3, GIMT_Encode2(AMDGPU::VGPR_32RegClassID),
        GIR_BuildMI, /*InsnID*/0, /*Opcode*/GIMT_Encode2(AMDGPU::BUFFER_LOAD_DWORDX2_VBUFFER_BOTHEN),
        GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/0, // DstI[vdata]
        GIR_AddSimpleTempRegister, /*InsnID*/0, /*TempRegID*/0,
        GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/1, // rsrc
        GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/0, // soffset
        GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/5, // offset
        GIR_CustomOperandRenderer, /*InsnID*/0, /*OldInsnID*/0, /*OpIdx*/6, /*OperandRenderer*/GIMT_Encode2(GICR_renderExtractCPol), // auxiliary
        GIR_CustomOperandRenderer, /*InsnID*/0, /*OldInsnID*/0, /*OpIdx*/6, /*OperandRenderer*/GIMT_Encode2(GICR_renderExtractSWZ), // auxiliary
        GIR_MergeMemOperands, /*InsnID*/0, /*NumInsns*/1, /*MergeInsnID's*/0,
        GIR_ConstrainSelectedInstOperands, /*InsnID*/0,
        GIR_EraseFromParent, /*InsnID*/0,
        // GIR_Coverage, 4168,
        GIR_Done,
      // Label 6482: @475750
      GIM_Reject,
    // Label 6466: @475751
    GIM_Reject,
    // Label 6396: @475752
    GIM_Try, /*On fail goto*//*Label 6483*/ GIMT_Encode4(477147),
      GIM_CheckType, /*MI*/0, /*Op*/1, /*Type*/GILLT_v4s32,
      GIM_CheckType, /*MI*/0, /*Op*/2, /*Type*/GILLT_s32,
      GIM_CheckType, /*MI*/0, /*Op*/3, /*Type*/GILLT_s32,
      GIM_CheckType, /*MI*/0, /*Op*/4, /*Type*/GILLT_s32,
      GIM_CheckRegBankForClass, /*MI*/0, /*Op*/0, /*RC*/GIMT_Encode2(AMDGPU::AV_128RegClassID),
      GIM_Try, /*On fail goto*//*Label 6484*/ GIMT_Encode4(475860), // Rule ID 4185 //
        GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasUnrestrictedSOffset),
        GIM_CheckConstantInt8, /*MI*/0, /*Op*/2, 0,
        GIM_CheckConstantInt8, /*MI*/0, /*Op*/3, 0,
        // MIs[0] offset
        GIM_CheckIsImm, /*MI*/0, /*Op*/5,
        // MIs[0] auxiliary
        GIM_CheckIsImm, /*MI*/0, /*Op*/6,
        // MIs[0] Operand 7
        GIM_CheckLiteralInt, /*MI*/0, /*Op*/7, GIMT_Encode8(0),
        GIM_CheckComplexPattern, /*MI*/0, /*Op*/4, /*Renderer*/GIMT_Encode2(0), GIMT_Encode2(GICP_gi_buf_soffset),
        // (SIbuffer_load:{ *:[v4f32] } v4i32:{ *:[v4i32] }:$rsrc, 0:{ *:[i32] }, 0:{ *:[i32] }, (BUFSOffset:{ *:[i32] } i32:{ *:[i32] }:$soffset), (timm:{ *:[i32] }):$offset, (timm:{ *:[i32] }):$auxiliary, 0:{ *:[i1] })  =>  (BUFFER_LOAD_DWORDX4_OFFSET:{ *:[v4f32] } SReg_128:{ *:[v4i32] }:$rsrc, SCSrc_b32:{ *:[i32] }:$soffset, (timm:{ *:[i32] }):$offset, (extract_cpol:{ *:[i32] } ?:{ *:[i32] }:$auxiliary), (extract_swz:{ *:[i1] } ?:{ *:[i32] }:$auxiliary))
        GIR_BuildMI, /*InsnID*/0, /*Opcode*/GIMT_Encode2(AMDGPU::BUFFER_LOAD_DWORDX4_OFFSET),
        GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/0, // DstI[vdata]
        GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/1, // rsrc
        GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/0, // soffset
        GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/5, // offset
        GIR_CustomOperandRenderer, /*InsnID*/0, /*OldInsnID*/0, /*OpIdx*/6, /*OperandRenderer*/GIMT_Encode2(GICR_renderExtractCPol), // auxiliary
        GIR_CustomOperandRenderer, /*InsnID*/0, /*OldInsnID*/0, /*OpIdx*/6, /*OperandRenderer*/GIMT_Encode2(GICR_renderExtractSWZ), // auxiliary
        GIR_MergeMemOperands, /*InsnID*/0, /*NumInsns*/1, /*MergeInsnID's*/0,
        GIR_ConstrainSelectedInstOperands, /*InsnID*/0,
        GIR_EraseFromParent, /*InsnID*/0,
        // GIR_Coverage, 4185,
        GIR_Done,
      // Label 6484: @475860
      GIM_Try, /*On fail goto*//*Label 6485*/ GIMT_Encode4(475939), // Rule ID 4189 //
        GIM_CheckConstantInt8, /*MI*/0, /*Op*/2, 0,
        GIM_CheckConstantInt8, /*MI*/0, /*Op*/3, 0,
        // MIs[0] offset
        GIM_CheckIsImm, /*MI*/0, /*Op*/5,
        // MIs[0] auxiliary
        GIM_CheckIsImm, /*MI*/0, /*Op*/6,
        // MIs[0] Operand 7
        GIM_CheckLiteralInt, /*MI*/0, /*Op*/7, GIMT_Encode8(0),
        GIM_CheckComplexPattern, /*MI*/0, /*Op*/4, /*Renderer*/GIMT_Encode2(0), GIMT_Encode2(GICP_gi_buf_soffset),
        // (SIbuffer_load:{ *:[v4f32] } v4i32:{ *:[v4i32] }:$rsrc, 0:{ *:[i32] }, 0:{ *:[i32] }, (BUFSOffset:{ *:[i32] } i32:{ *:[i32] }:$soffset), (timm:{ *:[i32] }):$offset, (timm:{ *:[i32] }):$auxiliary, 0:{ *:[i1] })  =>  (BUFFER_LOAD_DWORDX4_VBUFFER_OFFSET:{ *:[v4f32] } SReg_128:{ *:[v4i32] }:$rsrc, SCSrc_b32:{ *:[i32] }:$soffset, (timm:{ *:[i32] }):$offset, (extract_cpol:{ *:[i32] } ?:{ *:[i32] }:$auxiliary), (extract_swz:{ *:[i1] } ?:{ *:[i32] }:$auxiliary))
        GIR_BuildMI, /*InsnID*/0, /*Opcode*/GIMT_Encode2(AMDGPU::BUFFER_LOAD_DWORDX4_VBUFFER_OFFSET),
        GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/0, // DstI[vdata]
        GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/1, // rsrc
        GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/0, // soffset
        GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/5, // offset
        GIR_CustomOperandRenderer, /*InsnID*/0, /*OldInsnID*/0, /*OpIdx*/6, /*OperandRenderer*/GIMT_Encode2(GICR_renderExtractCPol), // auxiliary
        GIR_CustomOperandRenderer, /*InsnID*/0, /*OldInsnID*/0, /*OpIdx*/6, /*OperandRenderer*/GIMT_Encode2(GICR_renderExtractSWZ), // auxiliary
        GIR_MergeMemOperands, /*InsnID*/0, /*NumInsns*/1, /*MergeInsnID's*/0,
        GIR_ConstrainSelectedInstOperands, /*InsnID*/0,
        GIR_EraseFromParent, /*InsnID*/0,
        // GIR_Coverage, 4189,
        GIR_Done,
      // Label 6485: @475939
      GIM_Try, /*On fail goto*//*Label 6486*/ GIMT_Encode4(476021), // Rule ID 4193 //
        GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasUnrestrictedSOffset),
        GIM_CheckConstantInt8, /*MI*/0, /*Op*/2, 0,
        GIM_CheckConstantInt8, /*MI*/0, /*Op*/3, 0,
        // MIs[0] offset
        GIM_CheckIsImm, /*MI*/0, /*Op*/5,
        // MIs[0] auxiliary
        GIM_CheckIsImm, /*MI*/0, /*Op*/6,
        // MIs[0] Operand 7
        GIM_CheckLiteralInt, /*MI*/0, /*Op*/7, GIMT_Encode8(0),
        GIM_CheckComplexPattern, /*MI*/0, /*Op*/4, /*Renderer*/GIMT_Encode2(0), GIMT_Encode2(GICP_gi_buf_soffset),
        // (SIbuffer_load:{ *:[v4i32] } v4i32:{ *:[v4i32] }:$rsrc, 0:{ *:[i32] }, 0:{ *:[i32] }, (BUFSOffset:{ *:[i32] } i32:{ *:[i32] }:$soffset), (timm:{ *:[i32] }):$offset, (timm:{ *:[i32] }):$auxiliary, 0:{ *:[i1] })  =>  (BUFFER_LOAD_DWORDX4_OFFSET:{ *:[v4i32] } SReg_128:{ *:[v4i32] }:$rsrc, SCSrc_b32:{ *:[i32] }:$soffset, (timm:{ *:[i32] }):$offset, (extract_cpol:{ *:[i32] } ?:{ *:[i32] }:$auxiliary), (extract_swz:{ *:[i1] } ?:{ *:[i32] }:$auxiliary))
        GIR_BuildMI, /*InsnID*/0, /*Opcode*/GIMT_Encode2(AMDGPU::BUFFER_LOAD_DWORDX4_OFFSET),
        GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/0, // DstI[vdata]
        GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/1, // rsrc
        GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/0, // soffset
        GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/5, // offset
        GIR_CustomOperandRenderer, /*InsnID*/0, /*OldInsnID*/0, /*OpIdx*/6, /*OperandRenderer*/GIMT_Encode2(GICR_renderExtractCPol), // auxiliary
        GIR_CustomOperandRenderer, /*InsnID*/0, /*OldInsnID*/0, /*OpIdx*/6, /*OperandRenderer*/GIMT_Encode2(GICR_renderExtractSWZ), // auxiliary
        GIR_MergeMemOperands, /*InsnID*/0, /*NumInsns*/1, /*MergeInsnID's*/0,
        GIR_ConstrainSelectedInstOperands, /*InsnID*/0,
        GIR_EraseFromParent, /*InsnID*/0,
        // GIR_Coverage, 4193,
        GIR_Done,
      // Label 6486: @476021
      GIM_Try, /*On fail goto*//*Label 6487*/ GIMT_Encode4(476100), // Rule ID 4197 //
        GIM_CheckConstantInt8, /*MI*/0, /*Op*/2, 0,
        GIM_CheckConstantInt8, /*MI*/0, /*Op*/3, 0,
        // MIs[0] offset
        GIM_CheckIsImm, /*MI*/0, /*Op*/5,
        // MIs[0] auxiliary
        GIM_CheckIsImm, /*MI*/0, /*Op*/6,
        // MIs[0] Operand 7
        GIM_CheckLiteralInt, /*MI*/0, /*Op*/7, GIMT_Encode8(0),
        GIM_CheckComplexPattern, /*MI*/0, /*Op*/4, /*Renderer*/GIMT_Encode2(0), GIMT_Encode2(GICP_gi_buf_soffset),
        // (SIbuffer_load:{ *:[v4i32] } v4i32:{ *:[v4i32] }:$rsrc, 0:{ *:[i32] }, 0:{ *:[i32] }, (BUFSOffset:{ *:[i32] } i32:{ *:[i32] }:$soffset), (timm:{ *:[i32] }):$offset, (timm:{ *:[i32] }):$auxiliary, 0:{ *:[i1] })  =>  (BUFFER_LOAD_DWORDX4_VBUFFER_OFFSET:{ *:[v4i32] } SReg_128:{ *:[v4i32] }:$rsrc, SCSrc_b32:{ *:[i32] }:$soffset, (timm:{ *:[i32] }):$offset, (extract_cpol:{ *:[i32] } ?:{ *:[i32] }:$auxiliary), (extract_swz:{ *:[i1] } ?:{ *:[i32] }:$auxiliary))
        GIR_BuildMI, /*InsnID*/0, /*Opcode*/GIMT_Encode2(AMDGPU::BUFFER_LOAD_DWORDX4_VBUFFER_OFFSET),
        GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/0, // DstI[vdata]
        GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/1, // rsrc
        GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/0, // soffset
        GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/5, // offset
        GIR_CustomOperandRenderer, /*InsnID*/0, /*OldInsnID*/0, /*OpIdx*/6, /*OperandRenderer*/GIMT_Encode2(GICR_renderExtractCPol), // auxiliary
        GIR_CustomOperandRenderer, /*InsnID*/0, /*OldInsnID*/0, /*OpIdx*/6, /*OperandRenderer*/GIMT_Encode2(GICR_renderExtractSWZ), // auxiliary
        GIR_MergeMemOperands, /*InsnID*/0, /*NumInsns*/1, /*MergeInsnID's*/0,
        GIR_ConstrainSelectedInstOperands, /*InsnID*/0,
        GIR_EraseFromParent, /*InsnID*/0,
        // GIR_Coverage, 4197,
        GIR_Done,
      // Label 6487: @476100
      GIM_Try, /*On fail goto*//*Label 6488*/ GIMT_Encode4(476182), // Rule ID 4186 //
        GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasUnrestrictedSOffset),
        GIM_CheckConstantInt8, /*MI*/0, /*Op*/2, 0,
        // MIs[0] offset
        GIM_CheckIsImm, /*MI*/0, /*Op*/5,
        // MIs[0] auxiliary
        GIM_CheckIsImm, /*MI*/0, /*Op*/6,
        // MIs[0] Operand 7
        GIM_CheckLiteralInt, /*MI*/0, /*Op*/7, GIMT_Encode8(0),
        GIM_CheckComplexPattern, /*MI*/0, /*Op*/4, /*Renderer*/GIMT_Encode2(0), GIMT_Encode2(GICP_gi_buf_soffset),
        // (SIbuffer_load:{ *:[v4f32] } v4i32:{ *:[v4i32] }:$rsrc, 0:{ *:[i32] }, i32:{ *:[i32] }:$voffset, (BUFSOffset:{ *:[i32] } i32:{ *:[i32] }:$soffset), (timm:{ *:[i32] }):$offset, (timm:{ *:[i32] }):$auxiliary, 0:{ *:[i1] })  =>  (BUFFER_LOAD_DWORDX4_OFFEN:{ *:[v4f32] } VGPR_32:{ *:[i32] }:$voffset, SReg_128:{ *:[v4i32] }:$rsrc, SCSrc_b32:{ *:[i32] }:$soffset, (timm:{ *:[i32] }):$offset, (extract_cpol:{ *:[i32] } ?:{ *:[i32] }:$auxiliary), (extract_swz:{ *:[i1] } ?:{ *:[i32] }:$auxiliary))
        GIR_BuildMI, /*InsnID*/0, /*Opcode*/GIMT_Encode2(AMDGPU::BUFFER_LOAD_DWORDX4_OFFEN),
        GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/0, // DstI[vdata]
        GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/3, // voffset
        GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/1, // rsrc
        GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/0, // soffset
        GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/5, // offset
        GIR_CustomOperandRenderer, /*InsnID*/0, /*OldInsnID*/0, /*OpIdx*/6, /*OperandRenderer*/GIMT_Encode2(GICR_renderExtractCPol), // auxiliary
        GIR_CustomOperandRenderer, /*InsnID*/0, /*OldInsnID*/0, /*OpIdx*/6, /*OperandRenderer*/GIMT_Encode2(GICR_renderExtractSWZ), // auxiliary
        GIR_MergeMemOperands, /*InsnID*/0, /*NumInsns*/1, /*MergeInsnID's*/0,
        GIR_ConstrainSelectedInstOperands, /*InsnID*/0,
        GIR_EraseFromParent, /*InsnID*/0,
        // GIR_Coverage, 4186,
        GIR_Done,
      // Label 6488: @476182
      GIM_Try, /*On fail goto*//*Label 6489*/ GIMT_Encode4(476261), // Rule ID 4190 //
        GIM_CheckConstantInt8, /*MI*/0, /*Op*/2, 0,
        // MIs[0] offset
        GIM_CheckIsImm, /*MI*/0, /*Op*/5,
        // MIs[0] auxiliary
        GIM_CheckIsImm, /*MI*/0, /*Op*/6,
        // MIs[0] Operand 7
        GIM_CheckLiteralInt, /*MI*/0, /*Op*/7, GIMT_Encode8(0),
        GIM_CheckComplexPattern, /*MI*/0, /*Op*/4, /*Renderer*/GIMT_Encode2(0), GIMT_Encode2(GICP_gi_buf_soffset),
        // (SIbuffer_load:{ *:[v4f32] } v4i32:{ *:[v4i32] }:$rsrc, 0:{ *:[i32] }, i32:{ *:[i32] }:$voffset, (BUFSOffset:{ *:[i32] } i32:{ *:[i32] }:$soffset), (timm:{ *:[i32] }):$offset, (timm:{ *:[i32] }):$auxiliary, 0:{ *:[i1] })  =>  (BUFFER_LOAD_DWORDX4_VBUFFER_OFFEN:{ *:[v4f32] } VGPR_32:{ *:[i32] }:$voffset, SReg_128:{ *:[v4i32] }:$rsrc, SCSrc_b32:{ *:[i32] }:$soffset, (timm:{ *:[i32] }):$offset, (extract_cpol:{ *:[i32] } ?:{ *:[i32] }:$auxiliary), (extract_swz:{ *:[i1] } ?:{ *:[i32] }:$auxiliary))
        GIR_BuildMI, /*InsnID*/0, /*Opcode*/GIMT_Encode2(AMDGPU::BUFFER_LOAD_DWORDX4_VBUFFER_OFFEN),
        GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/0, // DstI[vdata]
        GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/3, // voffset
        GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/1, // rsrc
        GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/0, // soffset
        GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/5, // offset
        GIR_CustomOperandRenderer, /*InsnID*/0, /*OldInsnID*/0, /*OpIdx*/6, /*OperandRenderer*/GIMT_Encode2(GICR_renderExtractCPol), // auxiliary
        GIR_CustomOperandRenderer, /*InsnID*/0, /*OldInsnID*/0, /*OpIdx*/6, /*OperandRenderer*/GIMT_Encode2(GICR_renderExtractSWZ), // auxiliary
        GIR_MergeMemOperands, /*InsnID*/0, /*NumInsns*/1, /*MergeInsnID's*/0,
        GIR_ConstrainSelectedInstOperands, /*InsnID*/0,
        GIR_EraseFromParent, /*InsnID*/0,
        // GIR_Coverage, 4190,
        GIR_Done,
      // Label 6489: @476261
      GIM_Try, /*On fail goto*//*Label 6490*/ GIMT_Encode4(476343), // Rule ID 4194 //
        GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasUnrestrictedSOffset),
        GIM_CheckConstantInt8, /*MI*/0, /*Op*/2, 0,
        // MIs[0] offset
        GIM_CheckIsImm, /*MI*/0, /*Op*/5,
        // MIs[0] auxiliary
        GIM_CheckIsImm, /*MI*/0, /*Op*/6,
        // MIs[0] Operand 7
        GIM_CheckLiteralInt, /*MI*/0, /*Op*/7, GIMT_Encode8(0),
        GIM_CheckComplexPattern, /*MI*/0, /*Op*/4, /*Renderer*/GIMT_Encode2(0), GIMT_Encode2(GICP_gi_buf_soffset),
        // (SIbuffer_load:{ *:[v4i32] } v4i32:{ *:[v4i32] }:$rsrc, 0:{ *:[i32] }, i32:{ *:[i32] }:$voffset, (BUFSOffset:{ *:[i32] } i32:{ *:[i32] }:$soffset), (timm:{ *:[i32] }):$offset, (timm:{ *:[i32] }):$auxiliary, 0:{ *:[i1] })  =>  (BUFFER_LOAD_DWORDX4_OFFEN:{ *:[v4i32] } VGPR_32:{ *:[i32] }:$voffset, SReg_128:{ *:[v4i32] }:$rsrc, SCSrc_b32:{ *:[i32] }:$soffset, (timm:{ *:[i32] }):$offset, (extract_cpol:{ *:[i32] } ?:{ *:[i32] }:$auxiliary), (extract_swz:{ *:[i1] } ?:{ *:[i32] }:$auxiliary))
        GIR_BuildMI, /*InsnID*/0, /*Opcode*/GIMT_Encode2(AMDGPU::BUFFER_LOAD_DWORDX4_OFFEN),
        GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/0, // DstI[vdata]
        GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/3, // voffset
        GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/1, // rsrc
        GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/0, // soffset
        GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/5, // offset
        GIR_CustomOperandRenderer, /*InsnID*/0, /*OldInsnID*/0, /*OpIdx*/6, /*OperandRenderer*/GIMT_Encode2(GICR_renderExtractCPol), // auxiliary
        GIR_CustomOperandRenderer, /*InsnID*/0, /*OldInsnID*/0, /*OpIdx*/6, /*OperandRenderer*/GIMT_Encode2(GICR_renderExtractSWZ), // auxiliary
        GIR_MergeMemOperands, /*InsnID*/0, /*NumInsns*/1, /*MergeInsnID's*/0,
        GIR_ConstrainSelectedInstOperands, /*InsnID*/0,
        GIR_EraseFromParent, /*InsnID*/0,
        // GIR_Coverage, 4194,
        GIR_Done,
      // Label 6490: @476343
      GIM_Try, /*On fail goto*//*Label 6491*/ GIMT_Encode4(476422), // Rule ID 4198 //
        GIM_CheckConstantInt8, /*MI*/0, /*Op*/2, 0,
        // MIs[0] offset
        GIM_CheckIsImm, /*MI*/0, /*Op*/5,
        // MIs[0] auxiliary
        GIM_CheckIsImm, /*MI*/0, /*Op*/6,
        // MIs[0] Operand 7
        GIM_CheckLiteralInt, /*MI*/0, /*Op*/7, GIMT_Encode8(0),
        GIM_CheckComplexPattern, /*MI*/0, /*Op*/4, /*Renderer*/GIMT_Encode2(0), GIMT_Encode2(GICP_gi_buf_soffset),
        // (SIbuffer_load:{ *:[v4i32] } v4i32:{ *:[v4i32] }:$rsrc, 0:{ *:[i32] }, i32:{ *:[i32] }:$voffset, (BUFSOffset:{ *:[i32] } i32:{ *:[i32] }:$soffset), (timm:{ *:[i32] }):$offset, (timm:{ *:[i32] }):$auxiliary, 0:{ *:[i1] })  =>  (BUFFER_LOAD_DWORDX4_VBUFFER_OFFEN:{ *:[v4i32] } VGPR_32:{ *:[i32] }:$voffset, SReg_128:{ *:[v4i32] }:$rsrc, SCSrc_b32:{ *:[i32] }:$soffset, (timm:{ *:[i32] }):$offset, (extract_cpol:{ *:[i32] } ?:{ *:[i32] }:$auxiliary), (extract_swz:{ *:[i1] } ?:{ *:[i32] }:$auxiliary))
        GIR_BuildMI, /*InsnID*/0, /*Opcode*/GIMT_Encode2(AMDGPU::BUFFER_LOAD_DWORDX4_VBUFFER_OFFEN),
        GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/0, // DstI[vdata]
        GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/3, // voffset
        GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/1, // rsrc
        GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/0, // soffset
        GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/5, // offset
        GIR_CustomOperandRenderer, /*InsnID*/0, /*OldInsnID*/0, /*OpIdx*/6, /*OperandRenderer*/GIMT_Encode2(GICR_renderExtractCPol), // auxiliary
        GIR_CustomOperandRenderer, /*InsnID*/0, /*OldInsnID*/0, /*OpIdx*/6, /*OperandRenderer*/GIMT_Encode2(GICR_renderExtractSWZ), // auxiliary
        GIR_MergeMemOperands, /*InsnID*/0, /*NumInsns*/1, /*MergeInsnID's*/0,
        GIR_ConstrainSelectedInstOperands, /*InsnID*/0,
        GIR_EraseFromParent, /*InsnID*/0,
        // GIR_Coverage, 4198,
        GIR_Done,
      // Label 6491: @476422
      GIM_Try, /*On fail goto*//*Label 6492*/ GIMT_Encode4(476496), // Rule ID 4187 //
        GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasUnrestrictedSOffset),
        GIM_CheckConstantInt8, /*MI*/0, /*Op*/3, 0,
        // MIs[0] offset
        GIM_CheckIsImm, /*MI*/0, /*Op*/5,
        // MIs[0] auxiliary
        GIM_CheckIsImm, /*MI*/0, /*Op*/6,
        // MIs[0] Operand 7
        GIM_CheckIsImm, /*MI*/0, /*Op*/7,
        GIM_CheckComplexPattern, /*MI*/0, /*Op*/4, /*Renderer*/GIMT_Encode2(0), GIMT_Encode2(GICP_gi_buf_soffset),
        // (SIbuffer_load:{ *:[v4f32] } v4i32:{ *:[v4i32] }:$rsrc, i32:{ *:[i32] }:$vindex, 0:{ *:[i32] }, (BUFSOffset:{ *:[i32] } i32:{ *:[i32] }:$soffset), (timm:{ *:[i32] }):$offset, (timm:{ *:[i32] }):$auxiliary, (timm:{ *:[i1] }))  =>  (BUFFER_LOAD_DWORDX4_IDXEN:{ *:[v4f32] } VGPR_32:{ *:[i32] }:$vindex, SReg_128:{ *:[v4i32] }:$rsrc, SCSrc_b32:{ *:[i32] }:$soffset, (timm:{ *:[i32] }):$offset, (extract_cpol:{ *:[i32] } ?:{ *:[i32] }:$auxiliary), (extract_swz:{ *:[i1] } ?:{ *:[i32] }:$auxiliary))
        GIR_BuildMI, /*InsnID*/0, /*Opcode*/GIMT_Encode2(AMDGPU::BUFFER_LOAD_DWORDX4_IDXEN),
        GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/0, // DstI[vdata]
        GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/2, // vindex
        GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/1, // rsrc
        GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/0, // soffset
        GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/5, // offset
        GIR_CustomOperandRenderer, /*InsnID*/0, /*OldInsnID*/0, /*OpIdx*/6, /*OperandRenderer*/GIMT_Encode2(GICR_renderExtractCPol), // auxiliary
        GIR_CustomOperandRenderer, /*InsnID*/0, /*OldInsnID*/0, /*OpIdx*/6, /*OperandRenderer*/GIMT_Encode2(GICR_renderExtractSWZ), // auxiliary
        GIR_MergeMemOperands, /*InsnID*/0, /*NumInsns*/1, /*MergeInsnID's*/0,
        GIR_ConstrainSelectedInstOperands, /*InsnID*/0,
        GIR_EraseFromParent, /*InsnID*/0,
        // GIR_Coverage, 4187,
        GIR_Done,
      // Label 6492: @476496
      GIM_Try, /*On fail goto*//*Label 6493*/ GIMT_Encode4(476567), // Rule ID 4191 //
        GIM_CheckConstantInt8, /*MI*/0, /*Op*/3, 0,
        // MIs[0] offset
        GIM_CheckIsImm, /*MI*/0, /*Op*/5,
        // MIs[0] auxiliary
        GIM_CheckIsImm, /*MI*/0, /*Op*/6,
        // MIs[0] Operand 7
        GIM_CheckIsImm, /*MI*/0, /*Op*/7,
        GIM_CheckComplexPattern, /*MI*/0, /*Op*/4, /*Renderer*/GIMT_Encode2(0), GIMT_Encode2(GICP_gi_buf_soffset),
        // (SIbuffer_load:{ *:[v4f32] } v4i32:{ *:[v4i32] }:$rsrc, i32:{ *:[i32] }:$vindex, 0:{ *:[i32] }, (BUFSOffset:{ *:[i32] } i32:{ *:[i32] }:$soffset), (timm:{ *:[i32] }):$offset, (timm:{ *:[i32] }):$auxiliary, (timm:{ *:[i1] }))  =>  (BUFFER_LOAD_DWORDX4_VBUFFER_IDXEN:{ *:[v4f32] } VGPR_32:{ *:[i32] }:$vindex, SReg_128:{ *:[v4i32] }:$rsrc, SCSrc_b32:{ *:[i32] }:$soffset, (timm:{ *:[i32] }):$offset, (extract_cpol:{ *:[i32] } ?:{ *:[i32] }:$auxiliary), (extract_swz:{ *:[i1] } ?:{ *:[i32] }:$auxiliary))
        GIR_BuildMI, /*InsnID*/0, /*Opcode*/GIMT_Encode2(AMDGPU::BUFFER_LOAD_DWORDX4_VBUFFER_IDXEN),
        GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/0, // DstI[vdata]
        GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/2, // vindex
        GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/1, // rsrc
        GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/0, // soffset
        GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/5, // offset
        GIR_CustomOperandRenderer, /*InsnID*/0, /*OldInsnID*/0, /*OpIdx*/6, /*OperandRenderer*/GIMT_Encode2(GICR_renderExtractCPol), // auxiliary
        GIR_CustomOperandRenderer, /*InsnID*/0, /*OldInsnID*/0, /*OpIdx*/6, /*OperandRenderer*/GIMT_Encode2(GICR_renderExtractSWZ), // auxiliary
        GIR_MergeMemOperands, /*InsnID*/0, /*NumInsns*/1, /*MergeInsnID's*/0,
        GIR_ConstrainSelectedInstOperands, /*InsnID*/0,
        GIR_EraseFromParent, /*InsnID*/0,
        // GIR_Coverage, 4191,
        GIR_Done,
      // Label 6493: @476567
      GIM_Try, /*On fail goto*//*Label 6494*/ GIMT_Encode4(476641), // Rule ID 4195 //
        GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasUnrestrictedSOffset),
        GIM_CheckConstantInt8, /*MI*/0, /*Op*/3, 0,
        // MIs[0] offset
        GIM_CheckIsImm, /*MI*/0, /*Op*/5,
        // MIs[0] auxiliary
        GIM_CheckIsImm, /*MI*/0, /*Op*/6,
        // MIs[0] Operand 7
        GIM_CheckIsImm, /*MI*/0, /*Op*/7,
        GIM_CheckComplexPattern, /*MI*/0, /*Op*/4, /*Renderer*/GIMT_Encode2(0), GIMT_Encode2(GICP_gi_buf_soffset),
        // (SIbuffer_load:{ *:[v4i32] } v4i32:{ *:[v4i32] }:$rsrc, i32:{ *:[i32] }:$vindex, 0:{ *:[i32] }, (BUFSOffset:{ *:[i32] } i32:{ *:[i32] }:$soffset), (timm:{ *:[i32] }):$offset, (timm:{ *:[i32] }):$auxiliary, (timm:{ *:[i1] }))  =>  (BUFFER_LOAD_DWORDX4_IDXEN:{ *:[v4i32] } VGPR_32:{ *:[i32] }:$vindex, SReg_128:{ *:[v4i32] }:$rsrc, SCSrc_b32:{ *:[i32] }:$soffset, (timm:{ *:[i32] }):$offset, (extract_cpol:{ *:[i32] } ?:{ *:[i32] }:$auxiliary), (extract_swz:{ *:[i1] } ?:{ *:[i32] }:$auxiliary))
        GIR_BuildMI, /*InsnID*/0, /*Opcode*/GIMT_Encode2(AMDGPU::BUFFER_LOAD_DWORDX4_IDXEN),
        GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/0, // DstI[vdata]
        GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/2, // vindex
        GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/1, // rsrc
        GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/0, // soffset
        GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/5, // offset
        GIR_CustomOperandRenderer, /*InsnID*/0, /*OldInsnID*/0, /*OpIdx*/6, /*OperandRenderer*/GIMT_Encode2(GICR_renderExtractCPol), // auxiliary
        GIR_CustomOperandRenderer, /*InsnID*/0, /*OldInsnID*/0, /*OpIdx*/6, /*OperandRenderer*/GIMT_Encode2(GICR_renderExtractSWZ), // auxiliary
        GIR_MergeMemOperands, /*InsnID*/0, /*NumInsns*/1, /*MergeInsnID's*/0,
        GIR_ConstrainSelectedInstOperands, /*InsnID*/0,
        GIR_EraseFromParent, /*InsnID*/0,
        // GIR_Coverage, 4195,
        GIR_Done,
      // Label 6494: @476641
      GIM_Try, /*On fail goto*//*Label 6495*/ GIMT_Encode4(476712), // Rule ID 4199 //
        GIM_CheckConstantInt8, /*MI*/0, /*Op*/3, 0,
        // MIs[0] offset
        GIM_CheckIsImm, /*MI*/0, /*Op*/5,
        // MIs[0] auxiliary
        GIM_CheckIsImm, /*MI*/0, /*Op*/6,
        // MIs[0] Operand 7
        GIM_CheckIsImm, /*MI*/0, /*Op*/7,
        GIM_CheckComplexPattern, /*MI*/0, /*Op*/4, /*Renderer*/GIMT_Encode2(0), GIMT_Encode2(GICP_gi_buf_soffset),
        // (SIbuffer_load:{ *:[v4i32] } v4i32:{ *:[v4i32] }:$rsrc, i32:{ *:[i32] }:$vindex, 0:{ *:[i32] }, (BUFSOffset:{ *:[i32] } i32:{ *:[i32] }:$soffset), (timm:{ *:[i32] }):$offset, (timm:{ *:[i32] }):$auxiliary, (timm:{ *:[i1] }))  =>  (BUFFER_LOAD_DWORDX4_VBUFFER_IDXEN:{ *:[v4i32] } VGPR_32:{ *:[i32] }:$vindex, SReg_128:{ *:[v4i32] }:$rsrc, SCSrc_b32:{ *:[i32] }:$soffset, (timm:{ *:[i32] }):$offset, (extract_cpol:{ *:[i32] } ?:{ *:[i32] }:$auxiliary), (extract_swz:{ *:[i1] } ?:{ *:[i32] }:$auxiliary))
        GIR_BuildMI, /*InsnID*/0, /*Opcode*/GIMT_Encode2(AMDGPU::BUFFER_LOAD_DWORDX4_VBUFFER_IDXEN),
        GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/0, // DstI[vdata]
        GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/2, // vindex
        GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/1, // rsrc
        GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/0, // soffset
        GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/5, // offset
        GIR_CustomOperandRenderer, /*InsnID*/0, /*OldInsnID*/0, /*OpIdx*/6, /*OperandRenderer*/GIMT_Encode2(GICR_renderExtractCPol), // auxiliary
        GIR_CustomOperandRenderer, /*InsnID*/0, /*OldInsnID*/0, /*OpIdx*/6, /*OperandRenderer*/GIMT_Encode2(GICR_renderExtractSWZ), // auxiliary
        GIR_MergeMemOperands, /*InsnID*/0, /*NumInsns*/1, /*MergeInsnID's*/0,
        GIR_ConstrainSelectedInstOperands, /*InsnID*/0,
        GIR_EraseFromParent, /*InsnID*/0,
        // GIR_Coverage, 4199,
        GIR_Done,
      // Label 6495: @476712
      GIM_Try, /*On fail goto*//*Label 6496*/ GIMT_Encode4(476822), // Rule ID 4188 //
        GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasUnrestrictedSOffset),
        // MIs[0] offset
        GIM_CheckIsImm, /*MI*/0, /*Op*/5,
        // MIs[0] auxiliary
        GIM_CheckIsImm, /*MI*/0, /*Op*/6,
        // MIs[0] Operand 7
        GIM_CheckIsImm, /*MI*/0, /*Op*/7,
        GIM_CheckComplexPattern, /*MI*/0, /*Op*/4, /*Renderer*/GIMT_Encode2(0), GIMT_Encode2(GICP_gi_buf_soffset),
        // (SIbuffer_load:{ *:[v4f32] } v4i32:{ *:[v4i32] }:$rsrc, i32:{ *:[i32] }:$vindex, i32:{ *:[i32] }:$voffset, (BUFSOffset:{ *:[i32] } i32:{ *:[i32] }:$soffset), (timm:{ *:[i32] }):$offset, (timm:{ *:[i32] }):$auxiliary, (timm:{ *:[i1] }))  =>  (BUFFER_LOAD_DWORDX4_BOTHEN:{ *:[v4f32] } (REG_SEQUENCE:{ *:[i64] } VReg_64:{ *:[i32] }, VGPR_32:{ *:[i32] }:$vindex, sub0:{ *:[i32] }, VGPR_32:{ *:[i32] }:$voffset, sub1:{ *:[i32] }), SReg_128:{ *:[v4i32] }:$rsrc, SCSrc_b32:{ *:[i32] }:$soffset, (timm:{ *:[i32] }):$offset, (extract_cpol:{ *:[i32] } ?:{ *:[i32] }:$auxiliary), (extract_swz:{ *:[i1] } ?:{ *:[i32] }:$auxiliary))
        GIR_MakeTempReg, /*TempRegID*/0, /*TypeID*/GILLT_s64,
        GIR_BuildMI, /*InsnID*/1, /*Opcode*/GIMT_Encode2(TargetOpcode::REG_SEQUENCE),
        GIR_AddTempRegister, /*InsnID*/1, /*TempRegID*/0, /*TempRegFlags*/GIMT_Encode2(RegState::Define),
        GIR_Copy, /*NewInsnID*/1, /*OldInsnID*/0, /*OpIdx*/2, // vindex
        GIR_AddImm8, /*InsnID*/1, /*SubRegIndex*/3,
        GIR_Copy, /*NewInsnID*/1, /*OldInsnID*/0, /*OpIdx*/3, // voffset
        GIR_AddImm8, /*InsnID*/1, /*SubRegIndex*/11,
        GIR_ConstrainOperandRC, /*InsnID*/1, /*Op*/0, GIMT_Encode2(AMDGPU::VReg_64RegClassID),
        GIR_ConstrainOperandRC, /*InsnID*/1, /*Op*/1, GIMT_Encode2(AMDGPU::VGPR_32RegClassID),
        GIR_ConstrainOperandRC, /*InsnID*/1, /*Op*/3, GIMT_Encode2(AMDGPU::VGPR_32RegClassID),
        GIR_BuildMI, /*InsnID*/0, /*Opcode*/GIMT_Encode2(AMDGPU::BUFFER_LOAD_DWORDX4_BOTHEN),
        GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/0, // DstI[vdata]
        GIR_AddSimpleTempRegister, /*InsnID*/0, /*TempRegID*/0,
        GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/1, // rsrc
        GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/0, // soffset
        GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/5, // offset
        GIR_CustomOperandRenderer, /*InsnID*/0, /*OldInsnID*/0, /*OpIdx*/6, /*OperandRenderer*/GIMT_Encode2(GICR_renderExtractCPol), // auxiliary
        GIR_CustomOperandRenderer, /*InsnID*/0, /*OldInsnID*/0, /*OpIdx*/6, /*OperandRenderer*/GIMT_Encode2(GICR_renderExtractSWZ), // auxiliary
        GIR_MergeMemOperands, /*InsnID*/0, /*NumInsns*/1, /*MergeInsnID's*/0,
        GIR_ConstrainSelectedInstOperands, /*InsnID*/0,
        GIR_EraseFromParent, /*InsnID*/0,
        // GIR_Coverage, 4188,
        GIR_Done,
      // Label 6496: @476822
      GIM_Try, /*On fail goto*//*Label 6497*/ GIMT_Encode4(476929), // Rule ID 4192 //
        // MIs[0] offset
        GIM_CheckIsImm, /*MI*/0, /*Op*/5,
        // MIs[0] auxiliary
        GIM_CheckIsImm, /*MI*/0, /*Op*/6,
        // MIs[0] Operand 7
        GIM_CheckIsImm, /*MI*/0, /*Op*/7,
        GIM_CheckComplexPattern, /*MI*/0, /*Op*/4, /*Renderer*/GIMT_Encode2(0), GIMT_Encode2(GICP_gi_buf_soffset),
        // (SIbuffer_load:{ *:[v4f32] } v4i32:{ *:[v4i32] }:$rsrc, i32:{ *:[i32] }:$vindex, i32:{ *:[i32] }:$voffset, (BUFSOffset:{ *:[i32] } i32:{ *:[i32] }:$soffset), (timm:{ *:[i32] }):$offset, (timm:{ *:[i32] }):$auxiliary, (timm:{ *:[i1] }))  =>  (BUFFER_LOAD_DWORDX4_VBUFFER_BOTHEN:{ *:[v4f32] } (REG_SEQUENCE:{ *:[i64] } VReg_64:{ *:[i32] }, VGPR_32:{ *:[i32] }:$vindex, sub0:{ *:[i32] }, VGPR_32:{ *:[i32] }:$voffset, sub1:{ *:[i32] }), SReg_128:{ *:[v4i32] }:$rsrc, SCSrc_b32:{ *:[i32] }:$soffset, (timm:{ *:[i32] }):$offset, (extract_cpol:{ *:[i32] } ?:{ *:[i32] }:$auxiliary), (extract_swz:{ *:[i1] } ?:{ *:[i32] }:$auxiliary))
        GIR_MakeTempReg, /*TempRegID*/0, /*TypeID*/GILLT_s64,
        GIR_BuildMI, /*InsnID*/1, /*Opcode*/GIMT_Encode2(TargetOpcode::REG_SEQUENCE),
        GIR_AddTempRegister, /*InsnID*/1, /*TempRegID*/0, /*TempRegFlags*/GIMT_Encode2(RegState::Define),
        GIR_Copy, /*NewInsnID*/1, /*OldInsnID*/0, /*OpIdx*/2, // vindex
        GIR_AddImm8, /*InsnID*/1, /*SubRegIndex*/3,
        GIR_Copy, /*NewInsnID*/1, /*OldInsnID*/0, /*OpIdx*/3, // voffset
        GIR_AddImm8, /*InsnID*/1, /*SubRegIndex*/11,
        GIR_ConstrainOperandRC, /*InsnID*/1, /*Op*/0, GIMT_Encode2(AMDGPU::VReg_64RegClassID),
        GIR_ConstrainOperandRC, /*InsnID*/1, /*Op*/1, GIMT_Encode2(AMDGPU::VGPR_32RegClassID),
        GIR_ConstrainOperandRC, /*InsnID*/1, /*Op*/3, GIMT_Encode2(AMDGPU::VGPR_32RegClassID),
        GIR_BuildMI, /*InsnID*/0, /*Opcode*/GIMT_Encode2(AMDGPU::BUFFER_LOAD_DWORDX4_VBUFFER_BOTHEN),
        GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/0, // DstI[vdata]
        GIR_AddSimpleTempRegister, /*InsnID*/0, /*TempRegID*/0,
        GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/1, // rsrc
        GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/0, // soffset
        GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/5, // offset
        GIR_CustomOperandRenderer, /*InsnID*/0, /*OldInsnID*/0, /*OpIdx*/6, /*OperandRenderer*/GIMT_Encode2(GICR_renderExtractCPol), // auxiliary
        GIR_CustomOperandRenderer, /*InsnID*/0, /*OldInsnID*/0, /*OpIdx*/6, /*OperandRenderer*/GIMT_Encode2(GICR_renderExtractSWZ), // auxiliary
        GIR_MergeMemOperands, /*InsnID*/0, /*NumInsns*/1, /*MergeInsnID's*/0,
        GIR_ConstrainSelectedInstOperands, /*InsnID*/0,
        GIR_EraseFromParent, /*InsnID*/0,
        // GIR_Coverage, 4192,
        GIR_Done,
      // Label 6497: @476929
      GIM_Try, /*On fail goto*//*Label 6498*/ GIMT_Encode4(477039), // Rule ID 4196 //
        GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasUnrestrictedSOffset),
        // MIs[0] offset
        GIM_CheckIsImm, /*MI*/0, /*Op*/5,
        // MIs[0] auxiliary
        GIM_CheckIsImm, /*MI*/0, /*Op*/6,
        // MIs[0] Operand 7
        GIM_CheckIsImm, /*MI*/0, /*Op*/7,
        GIM_CheckComplexPattern, /*MI*/0, /*Op*/4, /*Renderer*/GIMT_Encode2(0), GIMT_Encode2(GICP_gi_buf_soffset),
        // (SIbuffer_load:{ *:[v4i32] } v4i32:{ *:[v4i32] }:$rsrc, i32:{ *:[i32] }:$vindex, i32:{ *:[i32] }:$voffset, (BUFSOffset:{ *:[i32] } i32:{ *:[i32] }:$soffset), (timm:{ *:[i32] }):$offset, (timm:{ *:[i32] }):$auxiliary, (timm:{ *:[i1] }))  =>  (BUFFER_LOAD_DWORDX4_BOTHEN:{ *:[v4i32] } (REG_SEQUENCE:{ *:[i64] } VReg_64:{ *:[i32] }, VGPR_32:{ *:[i32] }:$vindex, sub0:{ *:[i32] }, VGPR_32:{ *:[i32] }:$voffset, sub1:{ *:[i32] }), SReg_128:{ *:[v4i32] }:$rsrc, SCSrc_b32:{ *:[i32] }:$soffset, (timm:{ *:[i32] }):$offset, (extract_cpol:{ *:[i32] } ?:{ *:[i32] }:$auxiliary), (extract_swz:{ *:[i1] } ?:{ *:[i32] }:$auxiliary))
        GIR_MakeTempReg, /*TempRegID*/0, /*TypeID*/GILLT_s64,
        GIR_BuildMI, /*InsnID*/1, /*Opcode*/GIMT_Encode2(TargetOpcode::REG_SEQUENCE),
        GIR_AddTempRegister, /*InsnID*/1, /*TempRegID*/0, /*TempRegFlags*/GIMT_Encode2(RegState::Define),
        GIR_Copy, /*NewInsnID*/1, /*OldInsnID*/0, /*OpIdx*/2, // vindex
        GIR_AddImm8, /*InsnID*/1, /*SubRegIndex*/3,
        GIR_Copy, /*NewInsnID*/1, /*OldInsnID*/0, /*OpIdx*/3, // voffset
        GIR_AddImm8, /*InsnID*/1, /*SubRegIndex*/11,
        GIR_ConstrainOperandRC, /*InsnID*/1, /*Op*/0, GIMT_Encode2(AMDGPU::VReg_64RegClassID),
        GIR_ConstrainOperandRC, /*InsnID*/1, /*Op*/1, GIMT_Encode2(AMDGPU::VGPR_32RegClassID),
        GIR_ConstrainOperandRC, /*InsnID*/1, /*Op*/3, GIMT_Encode2(AMDGPU::VGPR_32RegClassID),
        GIR_BuildMI, /*InsnID*/0, /*Opcode*/GIMT_Encode2(AMDGPU::BUFFER_LOAD_DWORDX4_BOTHEN),
        GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/0, // DstI[vdata]
        GIR_AddSimpleTempRegister, /*InsnID*/0, /*TempRegID*/0,
        GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/1, // rsrc
        GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/0, // soffset
        GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/5, // offset
        GIR_CustomOperandRenderer, /*InsnID*/0, /*OldInsnID*/0, /*OpIdx*/6, /*OperandRenderer*/GIMT_Encode2(GICR_renderExtractCPol), // auxiliary
        GIR_CustomOperandRenderer, /*InsnID*/0, /*OldInsnID*/0, /*OpIdx*/6, /*OperandRenderer*/GIMT_Encode2(GICR_renderExtractSWZ), // auxiliary
        GIR_MergeMemOperands, /*InsnID*/0, /*NumInsns*/1, /*MergeInsnID's*/0,
        GIR_ConstrainSelectedInstOperands, /*InsnID*/0,
        GIR_EraseFromParent, /*InsnID*/0,
        // GIR_Coverage, 4196,
        GIR_Done,
      // Label 6498: @477039
      GIM_Try, /*On fail goto*//*Label 6499*/ GIMT_Encode4(477146), // Rule ID 4200 //
        // MIs[0] offset
        GIM_CheckIsImm, /*MI*/0, /*Op*/5,
        // MIs[0] auxiliary
        GIM_CheckIsImm, /*MI*/0, /*Op*/6,
        // MIs[0] Operand 7
        GIM_CheckIsImm, /*MI*/0, /*Op*/7,
        GIM_CheckComplexPattern, /*MI*/0, /*Op*/4, /*Renderer*/GIMT_Encode2(0), GIMT_Encode2(GICP_gi_buf_soffset),
        // (SIbuffer_load:{ *:[v4i32] } v4i32:{ *:[v4i32] }:$rsrc, i32:{ *:[i32] }:$vindex, i32:{ *:[i32] }:$voffset, (BUFSOffset:{ *:[i32] } i32:{ *:[i32] }:$soffset), (timm:{ *:[i32] }):$offset, (timm:{ *:[i32] }):$auxiliary, (timm:{ *:[i1] }))  =>  (BUFFER_LOAD_DWORDX4_VBUFFER_BOTHEN:{ *:[v4i32] } (REG_SEQUENCE:{ *:[i64] } VReg_64:{ *:[i32] }, VGPR_32:{ *:[i32] }:$vindex, sub0:{ *:[i32] }, VGPR_32:{ *:[i32] }:$voffset, sub1:{ *:[i32] }), SReg_128:{ *:[v4i32] }:$rsrc, SCSrc_b32:{ *:[i32] }:$soffset, (timm:{ *:[i32] }):$offset, (extract_cpol:{ *:[i32] } ?:{ *:[i32] }:$auxiliary), (extract_swz:{ *:[i1] } ?:{ *:[i32] }:$auxiliary))
        GIR_MakeTempReg, /*TempRegID*/0, /*TypeID*/GILLT_s64,
        GIR_BuildMI, /*InsnID*/1, /*Opcode*/GIMT_Encode2(TargetOpcode::REG_SEQUENCE),
        GIR_AddTempRegister, /*InsnID*/1, /*TempRegID*/0, /*TempRegFlags*/GIMT_Encode2(RegState::Define),
        GIR_Copy, /*NewInsnID*/1, /*OldInsnID*/0, /*OpIdx*/2, // vindex
        GIR_AddImm8, /*InsnID*/1, /*SubRegIndex*/3,
        GIR_Copy, /*NewInsnID*/1, /*OldInsnID*/0, /*OpIdx*/3, // voffset
        GIR_AddImm8, /*InsnID*/1, /*SubRegIndex*/11,
        GIR_ConstrainOperandRC, /*InsnID*/1, /*Op*/0, GIMT_Encode2(AMDGPU::VReg_64RegClassID),
        GIR_ConstrainOperandRC, /*InsnID*/1, /*Op*/1, GIMT_Encode2(AMDGPU::VGPR_32RegClassID),
        GIR_ConstrainOperandRC, /*InsnID*/1, /*Op*/3, GIMT_Encode2(AMDGPU::VGPR_32RegClassID),
        GIR_BuildMI, /*InsnID*/0, /*Opcode*/GIMT_Encode2(AMDGPU::BUFFER_LOAD_DWORDX4_VBUFFER_BOTHEN),
        GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/0, // DstI[vdata]
        GIR_AddSimpleTempRegister, /*InsnID*/0, /*TempRegID*/0,
        GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/1, // rsrc
        GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/0, // soffset
        GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/5, // offset
        GIR_CustomOperandRenderer, /*InsnID*/0, /*OldInsnID*/0, /*OpIdx*/6, /*OperandRenderer*/GIMT_Encode2(GICR_renderExtractCPol), // auxiliary
        GIR_CustomOperandRenderer, /*InsnID*/0, /*OldInsnID*/0, /*OpIdx*/6, /*OperandRenderer*/GIMT_Encode2(GICR_renderExtractSWZ), // auxiliary
        GIR_MergeMemOperands, /*InsnID*/0, /*NumInsns*/1, /*MergeInsnID's*/0,
        GIR_ConstrainSelectedInstOperands, /*InsnID*/0,
        GIR_EraseFromParent, /*InsnID*/0,
        // GIR_Coverage, 4200,
        GIR_Done,
      // Label 6499: @477146
      GIM_Reject,
    // Label 6483: @477147
    GIM_Reject,
    // Label 6397: @477148
    GIM_Reject,
    // Label 125: @477149
    GIM_SwitchType, /*MI*/0, /*Op*/0, /*[*/GIMT_Encode2(9), GIMT_Encode2(18), /*)*//*default:*//*Label 6504*/ GIMT_Encode4(482780),
    /*GILLT_s32*//*Label 6500*/ GIMT_Encode4(477196), GIMT_Encode4(0), GIMT_Encode4(0),
    /*GILLT_v2s32*//*Label 6501*/ GIMT_Encode4(478592), GIMT_Encode4(0),
    /*GILLT_v3s32*//*Label 6502*/ GIMT_Encode4(479988), GIMT_Encode4(0), GIMT_Encode4(0),
    /*GILLT_v4s32*//*Label 6503*/ GIMT_Encode4(481384),
    // Label 6500: @477196
    GIM_Try, /*On fail goto*//*Label 6505*/ GIMT_Encode4(478591),
      GIM_CheckType, /*MI*/0, /*Op*/1, /*Type*/GILLT_v4s32,
      GIM_CheckType, /*MI*/0, /*Op*/2, /*Type*/GILLT_s32,
      GIM_CheckType, /*MI*/0, /*Op*/3, /*Type*/GILLT_s32,
      GIM_CheckType, /*MI*/0, /*Op*/4, /*Type*/GILLT_s32,
      GIM_CheckRegBankForClass, /*MI*/0, /*Op*/0, /*RC*/GIMT_Encode2(AMDGPU::AV_32RegClassID),
      GIM_Try, /*On fail goto*//*Label 6506*/ GIMT_Encode4(477304), // Rule ID 3913 //
        GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasUnrestrictedSOffset),
        GIM_CheckConstantInt8, /*MI*/0, /*Op*/2, 0,
        GIM_CheckConstantInt8, /*MI*/0, /*Op*/3, 0,
        // MIs[0] offset
        GIM_CheckIsImm, /*MI*/0, /*Op*/5,
        // MIs[0] auxiliary
        GIM_CheckIsImm, /*MI*/0, /*Op*/6,
        // MIs[0] Operand 7
        GIM_CheckLiteralInt, /*MI*/0, /*Op*/7, GIMT_Encode8(0),
        GIM_CheckComplexPattern, /*MI*/0, /*Op*/4, /*Renderer*/GIMT_Encode2(0), GIMT_Encode2(GICP_gi_buf_soffset),
        // (SIbuffer_load_format:{ *:[f32] } v4i32:{ *:[v4i32] }:$rsrc, 0:{ *:[i32] }, 0:{ *:[i32] }, (BUFSOffset:{ *:[i32] } i32:{ *:[i32] }:$soffset), (timm:{ *:[i32] }):$offset, (timm:{ *:[i32] }):$auxiliary, 0:{ *:[i1] })  =>  (BUFFER_LOAD_FORMAT_X_OFFSET:{ *:[f32] } SReg_128:{ *:[v4i32] }:$rsrc, SCSrc_b32:{ *:[i32] }:$soffset, (timm:{ *:[i32] }):$offset, (extract_cpol:{ *:[i32] } ?:{ *:[i32] }:$auxiliary), (extract_swz:{ *:[i1] } ?:{ *:[i32] }:$auxiliary))
        GIR_BuildMI, /*InsnID*/0, /*Opcode*/GIMT_Encode2(AMDGPU::BUFFER_LOAD_FORMAT_X_OFFSET),
        GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/0, // DstI[vdata]
        GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/1, // rsrc
        GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/0, // soffset
        GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/5, // offset
        GIR_CustomOperandRenderer, /*InsnID*/0, /*OldInsnID*/0, /*OpIdx*/6, /*OperandRenderer*/GIMT_Encode2(GICR_renderExtractCPol), // auxiliary
        GIR_CustomOperandRenderer, /*InsnID*/0, /*OldInsnID*/0, /*OpIdx*/6, /*OperandRenderer*/GIMT_Encode2(GICR_renderExtractSWZ), // auxiliary
        GIR_MergeMemOperands, /*InsnID*/0, /*NumInsns*/1, /*MergeInsnID's*/0,
        GIR_ConstrainSelectedInstOperands, /*InsnID*/0,
        GIR_EraseFromParent, /*InsnID*/0,
        // GIR_Coverage, 3913,
        GIR_Done,
      // Label 6506: @477304
      GIM_Try, /*On fail goto*//*Label 6507*/ GIMT_Encode4(477383), // Rule ID 3917 //
        GIM_CheckConstantInt8, /*MI*/0, /*Op*/2, 0,
        GIM_CheckConstantInt8, /*MI*/0, /*Op*/3, 0,
        // MIs[0] offset
        GIM_CheckIsImm, /*MI*/0, /*Op*/5,
        // MIs[0] auxiliary
        GIM_CheckIsImm, /*MI*/0, /*Op*/6,
        // MIs[0] Operand 7
        GIM_CheckLiteralInt, /*MI*/0, /*Op*/7, GIMT_Encode8(0),
        GIM_CheckComplexPattern, /*MI*/0, /*Op*/4, /*Renderer*/GIMT_Encode2(0), GIMT_Encode2(GICP_gi_buf_soffset),
        // (SIbuffer_load_format:{ *:[f32] } v4i32:{ *:[v4i32] }:$rsrc, 0:{ *:[i32] }, 0:{ *:[i32] }, (BUFSOffset:{ *:[i32] } i32:{ *:[i32] }:$soffset), (timm:{ *:[i32] }):$offset, (timm:{ *:[i32] }):$auxiliary, 0:{ *:[i1] })  =>  (BUFFER_LOAD_FORMAT_X_VBUFFER_OFFSET:{ *:[f32] } SReg_128:{ *:[v4i32] }:$rsrc, SCSrc_b32:{ *:[i32] }:$soffset, (timm:{ *:[i32] }):$offset, (extract_cpol:{ *:[i32] } ?:{ *:[i32] }:$auxiliary), (extract_swz:{ *:[i1] } ?:{ *:[i32] }:$auxiliary))
        GIR_BuildMI, /*InsnID*/0, /*Opcode*/GIMT_Encode2(AMDGPU::BUFFER_LOAD_FORMAT_X_VBUFFER_OFFSET),
        GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/0, // DstI[vdata]
        GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/1, // rsrc
        GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/0, // soffset
        GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/5, // offset
        GIR_CustomOperandRenderer, /*InsnID*/0, /*OldInsnID*/0, /*OpIdx*/6, /*OperandRenderer*/GIMT_Encode2(GICR_renderExtractCPol), // auxiliary
        GIR_CustomOperandRenderer, /*InsnID*/0, /*OldInsnID*/0, /*OpIdx*/6, /*OperandRenderer*/GIMT_Encode2(GICR_renderExtractSWZ), // auxiliary
        GIR_MergeMemOperands, /*InsnID*/0, /*NumInsns*/1, /*MergeInsnID's*/0,
        GIR_ConstrainSelectedInstOperands, /*InsnID*/0,
        GIR_EraseFromParent, /*InsnID*/0,
        // GIR_Coverage, 3917,
        GIR_Done,
      // Label 6507: @477383
      GIM_Try, /*On fail goto*//*Label 6508*/ GIMT_Encode4(477465), // Rule ID 3921 //
        GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasUnrestrictedSOffset),
        GIM_CheckConstantInt8, /*MI*/0, /*Op*/2, 0,
        GIM_CheckConstantInt8, /*MI*/0, /*Op*/3, 0,
        // MIs[0] offset
        GIM_CheckIsImm, /*MI*/0, /*Op*/5,
        // MIs[0] auxiliary
        GIM_CheckIsImm, /*MI*/0, /*Op*/6,
        // MIs[0] Operand 7
        GIM_CheckLiteralInt, /*MI*/0, /*Op*/7, GIMT_Encode8(0),
        GIM_CheckComplexPattern, /*MI*/0, /*Op*/4, /*Renderer*/GIMT_Encode2(0), GIMT_Encode2(GICP_gi_buf_soffset),
        // (SIbuffer_load_format:{ *:[i32] } v4i32:{ *:[v4i32] }:$rsrc, 0:{ *:[i32] }, 0:{ *:[i32] }, (BUFSOffset:{ *:[i32] } i32:{ *:[i32] }:$soffset), (timm:{ *:[i32] }):$offset, (timm:{ *:[i32] }):$auxiliary, 0:{ *:[i1] })  =>  (BUFFER_LOAD_FORMAT_X_OFFSET:{ *:[i32] } SReg_128:{ *:[v4i32] }:$rsrc, SCSrc_b32:{ *:[i32] }:$soffset, (timm:{ *:[i32] }):$offset, (extract_cpol:{ *:[i32] } ?:{ *:[i32] }:$auxiliary), (extract_swz:{ *:[i1] } ?:{ *:[i32] }:$auxiliary))
        GIR_BuildMI, /*InsnID*/0, /*Opcode*/GIMT_Encode2(AMDGPU::BUFFER_LOAD_FORMAT_X_OFFSET),
        GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/0, // DstI[vdata]
        GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/1, // rsrc
        GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/0, // soffset
        GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/5, // offset
        GIR_CustomOperandRenderer, /*InsnID*/0, /*OldInsnID*/0, /*OpIdx*/6, /*OperandRenderer*/GIMT_Encode2(GICR_renderExtractCPol), // auxiliary
        GIR_CustomOperandRenderer, /*InsnID*/0, /*OldInsnID*/0, /*OpIdx*/6, /*OperandRenderer*/GIMT_Encode2(GICR_renderExtractSWZ), // auxiliary
        GIR_MergeMemOperands, /*InsnID*/0, /*NumInsns*/1, /*MergeInsnID's*/0,
        GIR_ConstrainSelectedInstOperands, /*InsnID*/0,
        GIR_EraseFromParent, /*InsnID*/0,
        // GIR_Coverage, 3921,
        GIR_Done,
      // Label 6508: @477465
      GIM_Try, /*On fail goto*//*Label 6509*/ GIMT_Encode4(477544), // Rule ID 3925 //
        GIM_CheckConstantInt8, /*MI*/0, /*Op*/2, 0,
        GIM_CheckConstantInt8, /*MI*/0, /*Op*/3, 0,
        // MIs[0] offset
        GIM_CheckIsImm, /*MI*/0, /*Op*/5,
        // MIs[0] auxiliary
        GIM_CheckIsImm, /*MI*/0, /*Op*/6,
        // MIs[0] Operand 7
        GIM_CheckLiteralInt, /*MI*/0, /*Op*/7, GIMT_Encode8(0),
        GIM_CheckComplexPattern, /*MI*/0, /*Op*/4, /*Renderer*/GIMT_Encode2(0), GIMT_Encode2(GICP_gi_buf_soffset),
        // (SIbuffer_load_format:{ *:[i32] } v4i32:{ *:[v4i32] }:$rsrc, 0:{ *:[i32] }, 0:{ *:[i32] }, (BUFSOffset:{ *:[i32] } i32:{ *:[i32] }:$soffset), (timm:{ *:[i32] }):$offset, (timm:{ *:[i32] }):$auxiliary, 0:{ *:[i1] })  =>  (BUFFER_LOAD_FORMAT_X_VBUFFER_OFFSET:{ *:[i32] } SReg_128:{ *:[v4i32] }:$rsrc, SCSrc_b32:{ *:[i32] }:$soffset, (timm:{ *:[i32] }):$offset, (extract_cpol:{ *:[i32] } ?:{ *:[i32] }:$auxiliary), (extract_swz:{ *:[i1] } ?:{ *:[i32] }:$auxiliary))
        GIR_BuildMI, /*InsnID*/0, /*Opcode*/GIMT_Encode2(AMDGPU::BUFFER_LOAD_FORMAT_X_VBUFFER_OFFSET),
        GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/0, // DstI[vdata]
        GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/1, // rsrc
        GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/0, // soffset
        GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/5, // offset
        GIR_CustomOperandRenderer, /*InsnID*/0, /*OldInsnID*/0, /*OpIdx*/6, /*OperandRenderer*/GIMT_Encode2(GICR_renderExtractCPol), // auxiliary
        GIR_CustomOperandRenderer, /*InsnID*/0, /*OldInsnID*/0, /*OpIdx*/6, /*OperandRenderer*/GIMT_Encode2(GICR_renderExtractSWZ), // auxiliary
        GIR_MergeMemOperands, /*InsnID*/0, /*NumInsns*/1, /*MergeInsnID's*/0,
        GIR_ConstrainSelectedInstOperands, /*InsnID*/0,
        GIR_EraseFromParent, /*InsnID*/0,
        // GIR_Coverage, 3925,
        GIR_Done,
      // Label 6509: @477544
      GIM_Try, /*On fail goto*//*Label 6510*/ GIMT_Encode4(477626), // Rule ID 3914 //
        GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasUnrestrictedSOffset),
        GIM_CheckConstantInt8, /*MI*/0, /*Op*/2, 0,
        // MIs[0] offset
        GIM_CheckIsImm, /*MI*/0, /*Op*/5,
        // MIs[0] auxiliary
        GIM_CheckIsImm, /*MI*/0, /*Op*/6,
        // MIs[0] Operand 7
        GIM_CheckLiteralInt, /*MI*/0, /*Op*/7, GIMT_Encode8(0),
        GIM_CheckComplexPattern, /*MI*/0, /*Op*/4, /*Renderer*/GIMT_Encode2(0), GIMT_Encode2(GICP_gi_buf_soffset),
        // (SIbuffer_load_format:{ *:[f32] } v4i32:{ *:[v4i32] }:$rsrc, 0:{ *:[i32] }, i32:{ *:[i32] }:$voffset, (BUFSOffset:{ *:[i32] } i32:{ *:[i32] }:$soffset), (timm:{ *:[i32] }):$offset, (timm:{ *:[i32] }):$auxiliary, 0:{ *:[i1] })  =>  (BUFFER_LOAD_FORMAT_X_OFFEN:{ *:[f32] } VGPR_32:{ *:[i32] }:$voffset, SReg_128:{ *:[v4i32] }:$rsrc, SCSrc_b32:{ *:[i32] }:$soffset, (timm:{ *:[i32] }):$offset, (extract_cpol:{ *:[i32] } ?:{ *:[i32] }:$auxiliary), (extract_swz:{ *:[i1] } ?:{ *:[i32] }:$auxiliary))
        GIR_BuildMI, /*InsnID*/0, /*Opcode*/GIMT_Encode2(AMDGPU::BUFFER_LOAD_FORMAT_X_OFFEN),
        GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/0, // DstI[vdata]
        GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/3, // voffset
        GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/1, // rsrc
        GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/0, // soffset
        GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/5, // offset
        GIR_CustomOperandRenderer, /*InsnID*/0, /*OldInsnID*/0, /*OpIdx*/6, /*OperandRenderer*/GIMT_Encode2(GICR_renderExtractCPol), // auxiliary
        GIR_CustomOperandRenderer, /*InsnID*/0, /*OldInsnID*/0, /*OpIdx*/6, /*OperandRenderer*/GIMT_Encode2(GICR_renderExtractSWZ), // auxiliary
        GIR_MergeMemOperands, /*InsnID*/0, /*NumInsns*/1, /*MergeInsnID's*/0,
        GIR_ConstrainSelectedInstOperands, /*InsnID*/0,
        GIR_EraseFromParent, /*InsnID*/0,
        // GIR_Coverage, 3914,
        GIR_Done,
      // Label 6510: @477626
      GIM_Try, /*On fail goto*//*Label 6511*/ GIMT_Encode4(477705), // Rule ID 3918 //
        GIM_CheckConstantInt8, /*MI*/0, /*Op*/2, 0,
        // MIs[0] offset
        GIM_CheckIsImm, /*MI*/0, /*Op*/5,
        // MIs[0] auxiliary
        GIM_CheckIsImm, /*MI*/0, /*Op*/6,
        // MIs[0] Operand 7
        GIM_CheckLiteralInt, /*MI*/0, /*Op*/7, GIMT_Encode8(0),
        GIM_CheckComplexPattern, /*MI*/0, /*Op*/4, /*Renderer*/GIMT_Encode2(0), GIMT_Encode2(GICP_gi_buf_soffset),
        // (SIbuffer_load_format:{ *:[f32] } v4i32:{ *:[v4i32] }:$rsrc, 0:{ *:[i32] }, i32:{ *:[i32] }:$voffset, (BUFSOffset:{ *:[i32] } i32:{ *:[i32] }:$soffset), (timm:{ *:[i32] }):$offset, (timm:{ *:[i32] }):$auxiliary, 0:{ *:[i1] })  =>  (BUFFER_LOAD_FORMAT_X_VBUFFER_OFFEN:{ *:[f32] } VGPR_32:{ *:[i32] }:$voffset, SReg_128:{ *:[v4i32] }:$rsrc, SCSrc_b32:{ *:[i32] }:$soffset, (timm:{ *:[i32] }):$offset, (extract_cpol:{ *:[i32] } ?:{ *:[i32] }:$auxiliary), (extract_swz:{ *:[i1] } ?:{ *:[i32] }:$auxiliary))
        GIR_BuildMI, /*InsnID*/0, /*Opcode*/GIMT_Encode2(AMDGPU::BUFFER_LOAD_FORMAT_X_VBUFFER_OFFEN),
        GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/0, // DstI[vdata]
        GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/3, // voffset
        GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/1, // rsrc
        GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/0, // soffset
        GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/5, // offset
        GIR_CustomOperandRenderer, /*InsnID*/0, /*OldInsnID*/0, /*OpIdx*/6, /*OperandRenderer*/GIMT_Encode2(GICR_renderExtractCPol), // auxiliary
        GIR_CustomOperandRenderer, /*InsnID*/0, /*OldInsnID*/0, /*OpIdx*/6, /*OperandRenderer*/GIMT_Encode2(GICR_renderExtractSWZ), // auxiliary
        GIR_MergeMemOperands, /*InsnID*/0, /*NumInsns*/1, /*MergeInsnID's*/0,
        GIR_ConstrainSelectedInstOperands, /*InsnID*/0,
        GIR_EraseFromParent, /*InsnID*/0,
        // GIR_Coverage, 3918,
        GIR_Done,
      // Label 6511: @477705
      GIM_Try, /*On fail goto*//*Label 6512*/ GIMT_Encode4(477787), // Rule ID 3922 //
        GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasUnrestrictedSOffset),
        GIM_CheckConstantInt8, /*MI*/0, /*Op*/2, 0,
        // MIs[0] offset
        GIM_CheckIsImm, /*MI*/0, /*Op*/5,
        // MIs[0] auxiliary
        GIM_CheckIsImm, /*MI*/0, /*Op*/6,
        // MIs[0] Operand 7
        GIM_CheckLiteralInt, /*MI*/0, /*Op*/7, GIMT_Encode8(0),
        GIM_CheckComplexPattern, /*MI*/0, /*Op*/4, /*Renderer*/GIMT_Encode2(0), GIMT_Encode2(GICP_gi_buf_soffset),
        // (SIbuffer_load_format:{ *:[i32] } v4i32:{ *:[v4i32] }:$rsrc, 0:{ *:[i32] }, i32:{ *:[i32] }:$voffset, (BUFSOffset:{ *:[i32] } i32:{ *:[i32] }:$soffset), (timm:{ *:[i32] }):$offset, (timm:{ *:[i32] }):$auxiliary, 0:{ *:[i1] })  =>  (BUFFER_LOAD_FORMAT_X_OFFEN:{ *:[i32] } VGPR_32:{ *:[i32] }:$voffset, SReg_128:{ *:[v4i32] }:$rsrc, SCSrc_b32:{ *:[i32] }:$soffset, (timm:{ *:[i32] }):$offset, (extract_cpol:{ *:[i32] } ?:{ *:[i32] }:$auxiliary), (extract_swz:{ *:[i1] } ?:{ *:[i32] }:$auxiliary))
        GIR_BuildMI, /*InsnID*/0, /*Opcode*/GIMT_Encode2(AMDGPU::BUFFER_LOAD_FORMAT_X_OFFEN),
        GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/0, // DstI[vdata]
        GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/3, // voffset
        GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/1, // rsrc
        GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/0, // soffset
        GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/5, // offset
        GIR_CustomOperandRenderer, /*InsnID*/0, /*OldInsnID*/0, /*OpIdx*/6, /*OperandRenderer*/GIMT_Encode2(GICR_renderExtractCPol), // auxiliary
        GIR_CustomOperandRenderer, /*InsnID*/0, /*OldInsnID*/0, /*OpIdx*/6, /*OperandRenderer*/GIMT_Encode2(GICR_renderExtractSWZ), // auxiliary
        GIR_MergeMemOperands, /*InsnID*/0, /*NumInsns*/1, /*MergeInsnID's*/0,
        GIR_ConstrainSelectedInstOperands, /*InsnID*/0,
        GIR_EraseFromParent, /*InsnID*/0,
        // GIR_Coverage, 3922,
        GIR_Done,
      // Label 6512: @477787
      GIM_Try, /*On fail goto*//*Label 6513*/ GIMT_Encode4(477866), // Rule ID 3926 //
        GIM_CheckConstantInt8, /*MI*/0, /*Op*/2, 0,
        // MIs[0] offset
        GIM_CheckIsImm, /*MI*/0, /*Op*/5,
        // MIs[0] auxiliary
        GIM_CheckIsImm, /*MI*/0, /*Op*/6,
        // MIs[0] Operand 7
        GIM_CheckLiteralInt, /*MI*/0, /*Op*/7, GIMT_Encode8(0),
        GIM_CheckComplexPattern, /*MI*/0, /*Op*/4, /*Renderer*/GIMT_Encode2(0), GIMT_Encode2(GICP_gi_buf_soffset),
        // (SIbuffer_load_format:{ *:[i32] } v4i32:{ *:[v4i32] }:$rsrc, 0:{ *:[i32] }, i32:{ *:[i32] }:$voffset, (BUFSOffset:{ *:[i32] } i32:{ *:[i32] }:$soffset), (timm:{ *:[i32] }):$offset, (timm:{ *:[i32] }):$auxiliary, 0:{ *:[i1] })  =>  (BUFFER_LOAD_FORMAT_X_VBUFFER_OFFEN:{ *:[i32] } VGPR_32:{ *:[i32] }:$voffset, SReg_128:{ *:[v4i32] }:$rsrc, SCSrc_b32:{ *:[i32] }:$soffset, (timm:{ *:[i32] }):$offset, (extract_cpol:{ *:[i32] } ?:{ *:[i32] }:$auxiliary), (extract_swz:{ *:[i1] } ?:{ *:[i32] }:$auxiliary))
        GIR_BuildMI, /*InsnID*/0, /*Opcode*/GIMT_Encode2(AMDGPU::BUFFER_LOAD_FORMAT_X_VBUFFER_OFFEN),
        GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/0, // DstI[vdata]
        GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/3, // voffset
        GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/1, // rsrc
        GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/0, // soffset
        GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/5, // offset
        GIR_CustomOperandRenderer, /*InsnID*/0, /*OldInsnID*/0, /*OpIdx*/6, /*OperandRenderer*/GIMT_Encode2(GICR_renderExtractCPol), // auxiliary
        GIR_CustomOperandRenderer, /*InsnID*/0, /*OldInsnID*/0, /*OpIdx*/6, /*OperandRenderer*/GIMT_Encode2(GICR_renderExtractSWZ), // auxiliary
        GIR_MergeMemOperands, /*InsnID*/0, /*NumInsns*/1, /*MergeInsnID's*/0,
        GIR_ConstrainSelectedInstOperands, /*InsnID*/0,
        GIR_EraseFromParent, /*InsnID*/0,
        // GIR_Coverage, 3926,
        GIR_Done,
      // Label 6513: @477866
      GIM_Try, /*On fail goto*//*Label 6514*/ GIMT_Encode4(477940), // Rule ID 3915 //
        GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasUnrestrictedSOffset),
        GIM_CheckConstantInt8, /*MI*/0, /*Op*/3, 0,
        // MIs[0] offset
        GIM_CheckIsImm, /*MI*/0, /*Op*/5,
        // MIs[0] auxiliary
        GIM_CheckIsImm, /*MI*/0, /*Op*/6,
        // MIs[0] Operand 7
        GIM_CheckIsImm, /*MI*/0, /*Op*/7,
        GIM_CheckComplexPattern, /*MI*/0, /*Op*/4, /*Renderer*/GIMT_Encode2(0), GIMT_Encode2(GICP_gi_buf_soffset),
        // (SIbuffer_load_format:{ *:[f32] } v4i32:{ *:[v4i32] }:$rsrc, i32:{ *:[i32] }:$vindex, 0:{ *:[i32] }, (BUFSOffset:{ *:[i32] } i32:{ *:[i32] }:$soffset), (timm:{ *:[i32] }):$offset, (timm:{ *:[i32] }):$auxiliary, (timm:{ *:[i1] }))  =>  (BUFFER_LOAD_FORMAT_X_IDXEN:{ *:[f32] } VGPR_32:{ *:[i32] }:$vindex, SReg_128:{ *:[v4i32] }:$rsrc, SCSrc_b32:{ *:[i32] }:$soffset, (timm:{ *:[i32] }):$offset, (extract_cpol:{ *:[i32] } ?:{ *:[i32] }:$auxiliary), (extract_swz:{ *:[i1] } ?:{ *:[i32] }:$auxiliary))
        GIR_BuildMI, /*InsnID*/0, /*Opcode*/GIMT_Encode2(AMDGPU::BUFFER_LOAD_FORMAT_X_IDXEN),
        GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/0, // DstI[vdata]
        GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/2, // vindex
        GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/1, // rsrc
        GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/0, // soffset
        GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/5, // offset
        GIR_CustomOperandRenderer, /*InsnID*/0, /*OldInsnID*/0, /*OpIdx*/6, /*OperandRenderer*/GIMT_Encode2(GICR_renderExtractCPol), // auxiliary
        GIR_CustomOperandRenderer, /*InsnID*/0, /*OldInsnID*/0, /*OpIdx*/6, /*OperandRenderer*/GIMT_Encode2(GICR_renderExtractSWZ), // auxiliary
        GIR_MergeMemOperands, /*InsnID*/0, /*NumInsns*/1, /*MergeInsnID's*/0,
        GIR_ConstrainSelectedInstOperands, /*InsnID*/0,
        GIR_EraseFromParent, /*InsnID*/0,
        // GIR_Coverage, 3915,
        GIR_Done,
      // Label 6514: @477940
      GIM_Try, /*On fail goto*//*Label 6515*/ GIMT_Encode4(478011), // Rule ID 3919 //
        GIM_CheckConstantInt8, /*MI*/0, /*Op*/3, 0,
        // MIs[0] offset
        GIM_CheckIsImm, /*MI*/0, /*Op*/5,
        // MIs[0] auxiliary
        GIM_CheckIsImm, /*MI*/0, /*Op*/6,
        // MIs[0] Operand 7
        GIM_CheckIsImm, /*MI*/0, /*Op*/7,
        GIM_CheckComplexPattern, /*MI*/0, /*Op*/4, /*Renderer*/GIMT_Encode2(0), GIMT_Encode2(GICP_gi_buf_soffset),
        // (SIbuffer_load_format:{ *:[f32] } v4i32:{ *:[v4i32] }:$rsrc, i32:{ *:[i32] }:$vindex, 0:{ *:[i32] }, (BUFSOffset:{ *:[i32] } i32:{ *:[i32] }:$soffset), (timm:{ *:[i32] }):$offset, (timm:{ *:[i32] }):$auxiliary, (timm:{ *:[i1] }))  =>  (BUFFER_LOAD_FORMAT_X_VBUFFER_IDXEN:{ *:[f32] } VGPR_32:{ *:[i32] }:$vindex, SReg_128:{ *:[v4i32] }:$rsrc, SCSrc_b32:{ *:[i32] }:$soffset, (timm:{ *:[i32] }):$offset, (extract_cpol:{ *:[i32] } ?:{ *:[i32] }:$auxiliary), (extract_swz:{ *:[i1] } ?:{ *:[i32] }:$auxiliary))
        GIR_BuildMI, /*InsnID*/0, /*Opcode*/GIMT_Encode2(AMDGPU::BUFFER_LOAD_FORMAT_X_VBUFFER_IDXEN),
        GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/0, // DstI[vdata]
        GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/2, // vindex
        GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/1, // rsrc
        GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/0, // soffset
        GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/5, // offset
        GIR_CustomOperandRenderer, /*InsnID*/0, /*OldInsnID*/0, /*OpIdx*/6, /*OperandRenderer*/GIMT_Encode2(GICR_renderExtractCPol), // auxiliary
        GIR_CustomOperandRenderer, /*InsnID*/0, /*OldInsnID*/0, /*OpIdx*/6, /*OperandRenderer*/GIMT_Encode2(GICR_renderExtractSWZ), // auxiliary
        GIR_MergeMemOperands, /*InsnID*/0, /*NumInsns*/1, /*MergeInsnID's*/0,
        GIR_ConstrainSelectedInstOperands, /*InsnID*/0,
        GIR_EraseFromParent, /*InsnID*/0,
        // GIR_Coverage, 3919,
        GIR_Done,
      // Label 6515: @478011
      GIM_Try, /*On fail goto*//*Label 6516*/ GIMT_Encode4(478085), // Rule ID 3923 //
        GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasUnrestrictedSOffset),
        GIM_CheckConstantInt8, /*MI*/0, /*Op*/3, 0,
        // MIs[0] offset
        GIM_CheckIsImm, /*MI*/0, /*Op*/5,
        // MIs[0] auxiliary
        GIM_CheckIsImm, /*MI*/0, /*Op*/6,
        // MIs[0] Operand 7
        GIM_CheckIsImm, /*MI*/0, /*Op*/7,
        GIM_CheckComplexPattern, /*MI*/0, /*Op*/4, /*Renderer*/GIMT_Encode2(0), GIMT_Encode2(GICP_gi_buf_soffset),
        // (SIbuffer_load_format:{ *:[i32] } v4i32:{ *:[v4i32] }:$rsrc, i32:{ *:[i32] }:$vindex, 0:{ *:[i32] }, (BUFSOffset:{ *:[i32] } i32:{ *:[i32] }:$soffset), (timm:{ *:[i32] }):$offset, (timm:{ *:[i32] }):$auxiliary, (timm:{ *:[i1] }))  =>  (BUFFER_LOAD_FORMAT_X_IDXEN:{ *:[i32] } VGPR_32:{ *:[i32] }:$vindex, SReg_128:{ *:[v4i32] }:$rsrc, SCSrc_b32:{ *:[i32] }:$soffset, (timm:{ *:[i32] }):$offset, (extract_cpol:{ *:[i32] } ?:{ *:[i32] }:$auxiliary), (extract_swz:{ *:[i1] } ?:{ *:[i32] }:$auxiliary))
        GIR_BuildMI, /*InsnID*/0, /*Opcode*/GIMT_Encode2(AMDGPU::BUFFER_LOAD_FORMAT_X_IDXEN),
        GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/0, // DstI[vdata]
        GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/2, // vindex
        GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/1, // rsrc
        GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/0, // soffset
        GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/5, // offset
        GIR_CustomOperandRenderer, /*InsnID*/0, /*OldInsnID*/0, /*OpIdx*/6, /*OperandRenderer*/GIMT_Encode2(GICR_renderExtractCPol), // auxiliary
        GIR_CustomOperandRenderer, /*InsnID*/0, /*OldInsnID*/0, /*OpIdx*/6, /*OperandRenderer*/GIMT_Encode2(GICR_renderExtractSWZ), // auxiliary
        GIR_MergeMemOperands, /*InsnID*/0, /*NumInsns*/1, /*MergeInsnID's*/0,
        GIR_ConstrainSelectedInstOperands, /*InsnID*/0,
        GIR_EraseFromParent, /*InsnID*/0,
        // GIR_Coverage, 3923,
        GIR_Done,
      // Label 6516: @478085
      GIM_Try, /*On fail goto*//*Label 6517*/ GIMT_Encode4(478156), // Rule ID 3927 //
        GIM_CheckConstantInt8, /*MI*/0, /*Op*/3, 0,
        // MIs[0] offset
        GIM_CheckIsImm, /*MI*/0, /*Op*/5,
        // MIs[0] auxiliary
        GIM_CheckIsImm, /*MI*/0, /*Op*/6,
        // MIs[0] Operand 7
        GIM_CheckIsImm, /*MI*/0, /*Op*/7,
        GIM_CheckComplexPattern, /*MI*/0, /*Op*/4, /*Renderer*/GIMT_Encode2(0), GIMT_Encode2(GICP_gi_buf_soffset),
        // (SIbuffer_load_format:{ *:[i32] } v4i32:{ *:[v4i32] }:$rsrc, i32:{ *:[i32] }:$vindex, 0:{ *:[i32] }, (BUFSOffset:{ *:[i32] } i32:{ *:[i32] }:$soffset), (timm:{ *:[i32] }):$offset, (timm:{ *:[i32] }):$auxiliary, (timm:{ *:[i1] }))  =>  (BUFFER_LOAD_FORMAT_X_VBUFFER_IDXEN:{ *:[i32] } VGPR_32:{ *:[i32] }:$vindex, SReg_128:{ *:[v4i32] }:$rsrc, SCSrc_b32:{ *:[i32] }:$soffset, (timm:{ *:[i32] }):$offset, (extract_cpol:{ *:[i32] } ?:{ *:[i32] }:$auxiliary), (extract_swz:{ *:[i1] } ?:{ *:[i32] }:$auxiliary))
        GIR_BuildMI, /*InsnID*/0, /*Opcode*/GIMT_Encode2(AMDGPU::BUFFER_LOAD_FORMAT_X_VBUFFER_IDXEN),
        GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/0, // DstI[vdata]
        GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/2, // vindex
        GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/1, // rsrc
        GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/0, // soffset
        GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/5, // offset
        GIR_CustomOperandRenderer, /*InsnID*/0, /*OldInsnID*/0, /*OpIdx*/6, /*OperandRenderer*/GIMT_Encode2(GICR_renderExtractCPol), // auxiliary
        GIR_CustomOperandRenderer, /*InsnID*/0, /*OldInsnID*/0, /*OpIdx*/6, /*OperandRenderer*/GIMT_Encode2(GICR_renderExtractSWZ), // auxiliary
        GIR_MergeMemOperands, /*InsnID*/0, /*NumInsns*/1, /*MergeInsnID's*/0,
        GIR_ConstrainSelectedInstOperands, /*InsnID*/0,
        GIR_EraseFromParent, /*InsnID*/0,
        // GIR_Coverage, 3927,
        GIR_Done,
      // Label 6517: @478156
      GIM_Try, /*On fail goto*//*Label 6518*/ GIMT_Encode4(478266), // Rule ID 3916 //
        GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasUnrestrictedSOffset),
        // MIs[0] offset
        GIM_CheckIsImm, /*MI*/0, /*Op*/5,
        // MIs[0] auxiliary
        GIM_CheckIsImm, /*MI*/0, /*Op*/6,
        // MIs[0] Operand 7
        GIM_CheckIsImm, /*MI*/0, /*Op*/7,
        GIM_CheckComplexPattern, /*MI*/0, /*Op*/4, /*Renderer*/GIMT_Encode2(0), GIMT_Encode2(GICP_gi_buf_soffset),
        // (SIbuffer_load_format:{ *:[f32] } v4i32:{ *:[v4i32] }:$rsrc, i32:{ *:[i32] }:$vindex, i32:{ *:[i32] }:$voffset, (BUFSOffset:{ *:[i32] } i32:{ *:[i32] }:$soffset), (timm:{ *:[i32] }):$offset, (timm:{ *:[i32] }):$auxiliary, (timm:{ *:[i1] }))  =>  (BUFFER_LOAD_FORMAT_X_BOTHEN:{ *:[f32] } (REG_SEQUENCE:{ *:[i64] } VReg_64:{ *:[i32] }, VGPR_32:{ *:[i32] }:$vindex, sub0:{ *:[i32] }, VGPR_32:{ *:[i32] }:$voffset, sub1:{ *:[i32] }), SReg_128:{ *:[v4i32] }:$rsrc, SCSrc_b32:{ *:[i32] }:$soffset, (timm:{ *:[i32] }):$offset, (extract_cpol:{ *:[i32] } ?:{ *:[i32] }:$auxiliary), (extract_swz:{ *:[i1] } ?:{ *:[i32] }:$auxiliary))
        GIR_MakeTempReg, /*TempRegID*/0, /*TypeID*/GILLT_s64,
        GIR_BuildMI, /*InsnID*/1, /*Opcode*/GIMT_Encode2(TargetOpcode::REG_SEQUENCE),
        GIR_AddTempRegister, /*InsnID*/1, /*TempRegID*/0, /*TempRegFlags*/GIMT_Encode2(RegState::Define),
        GIR_Copy, /*NewInsnID*/1, /*OldInsnID*/0, /*OpIdx*/2, // vindex
        GIR_AddImm8, /*InsnID*/1, /*SubRegIndex*/3,
        GIR_Copy, /*NewInsnID*/1, /*OldInsnID*/0, /*OpIdx*/3, // voffset
        GIR_AddImm8, /*InsnID*/1, /*SubRegIndex*/11,
        GIR_ConstrainOperandRC, /*InsnID*/1, /*Op*/0, GIMT_Encode2(AMDGPU::VReg_64RegClassID),
        GIR_ConstrainOperandRC, /*InsnID*/1, /*Op*/1, GIMT_Encode2(AMDGPU::VGPR_32RegClassID),
        GIR_ConstrainOperandRC, /*InsnID*/1, /*Op*/3, GIMT_Encode2(AMDGPU::VGPR_32RegClassID),
        GIR_BuildMI, /*InsnID*/0, /*Opcode*/GIMT_Encode2(AMDGPU::BUFFER_LOAD_FORMAT_X_BOTHEN),
        GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/0, // DstI[vdata]
        GIR_AddSimpleTempRegister, /*InsnID*/0, /*TempRegID*/0,
        GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/1, // rsrc
        GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/0, // soffset
        GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/5, // offset
        GIR_CustomOperandRenderer, /*InsnID*/0, /*OldInsnID*/0, /*OpIdx*/6, /*OperandRenderer*/GIMT_Encode2(GICR_renderExtractCPol), // auxiliary
        GIR_CustomOperandRenderer, /*InsnID*/0, /*OldInsnID*/0, /*OpIdx*/6, /*OperandRenderer*/GIMT_Encode2(GICR_renderExtractSWZ), // auxiliary
        GIR_MergeMemOperands, /*InsnID*/0, /*NumInsns*/1, /*MergeInsnID's*/0,
        GIR_ConstrainSelectedInstOperands, /*InsnID*/0,
        GIR_EraseFromParent, /*InsnID*/0,
        // GIR_Coverage, 3916,
        GIR_Done,
      // Label 6518: @478266
      GIM_Try, /*On fail goto*//*Label 6519*/ GIMT_Encode4(478373), // Rule ID 3920 //
        // MIs[0] offset
        GIM_CheckIsImm, /*MI*/0, /*Op*/5,
        // MIs[0] auxiliary
        GIM_CheckIsImm, /*MI*/0, /*Op*/6,
        // MIs[0] Operand 7
        GIM_CheckIsImm, /*MI*/0, /*Op*/7,
        GIM_CheckComplexPattern, /*MI*/0, /*Op*/4, /*Renderer*/GIMT_Encode2(0), GIMT_Encode2(GICP_gi_buf_soffset),
        // (SIbuffer_load_format:{ *:[f32] } v4i32:{ *:[v4i32] }:$rsrc, i32:{ *:[i32] }:$vindex, i32:{ *:[i32] }:$voffset, (BUFSOffset:{ *:[i32] } i32:{ *:[i32] }:$soffset), (timm:{ *:[i32] }):$offset, (timm:{ *:[i32] }):$auxiliary, (timm:{ *:[i1] }))  =>  (BUFFER_LOAD_FORMAT_X_VBUFFER_BOTHEN:{ *:[f32] } (REG_SEQUENCE:{ *:[i64] } VReg_64:{ *:[i32] }, VGPR_32:{ *:[i32] }:$vindex, sub0:{ *:[i32] }, VGPR_32:{ *:[i32] }:$voffset, sub1:{ *:[i32] }), SReg_128:{ *:[v4i32] }:$rsrc, SCSrc_b32:{ *:[i32] }:$soffset, (timm:{ *:[i32] }):$offset, (extract_cpol:{ *:[i32] } ?:{ *:[i32] }:$auxiliary), (extract_swz:{ *:[i1] } ?:{ *:[i32] }:$auxiliary))
        GIR_MakeTempReg, /*TempRegID*/0, /*TypeID*/GILLT_s64,
        GIR_BuildMI, /*InsnID*/1, /*Opcode*/GIMT_Encode2(TargetOpcode::REG_SEQUENCE),
        GIR_AddTempRegister, /*InsnID*/1, /*TempRegID*/0, /*TempRegFlags*/GIMT_Encode2(RegState::Define),
        GIR_Copy, /*NewInsnID*/1, /*OldInsnID*/0, /*OpIdx*/2, // vindex
        GIR_AddImm8, /*InsnID*/1, /*SubRegIndex*/3,
        GIR_Copy, /*NewInsnID*/1, /*OldInsnID*/0, /*OpIdx*/3, // voffset
        GIR_AddImm8, /*InsnID*/1, /*SubRegIndex*/11,
        GIR_ConstrainOperandRC, /*InsnID*/1, /*Op*/0, GIMT_Encode2(AMDGPU::VReg_64RegClassID),
        GIR_ConstrainOperandRC, /*InsnID*/1, /*Op*/1, GIMT_Encode2(AMDGPU::VGPR_32RegClassID),
        GIR_ConstrainOperandRC, /*InsnID*/1, /*Op*/3, GIMT_Encode2(AMDGPU::VGPR_32RegClassID),
        GIR_BuildMI, /*InsnID*/0, /*Opcode*/GIMT_Encode2(AMDGPU::BUFFER_LOAD_FORMAT_X_VBUFFER_BOTHEN),
        GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/0, // DstI[vdata]
        GIR_AddSimpleTempRegister, /*InsnID*/0, /*TempRegID*/0,
        GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/1, // rsrc
        GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/0, // soffset
        GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/5, // offset
        GIR_CustomOperandRenderer, /*InsnID*/0, /*OldInsnID*/0, /*OpIdx*/6, /*OperandRenderer*/GIMT_Encode2(GICR_renderExtractCPol), // auxiliary
        GIR_CustomOperandRenderer, /*InsnID*/0, /*OldInsnID*/0, /*OpIdx*/6, /*OperandRenderer*/GIMT_Encode2(GICR_renderExtractSWZ), // auxiliary
        GIR_MergeMemOperands, /*InsnID*/0, /*NumInsns*/1, /*MergeInsnID's*/0,
        GIR_ConstrainSelectedInstOperands, /*InsnID*/0,
        GIR_EraseFromParent, /*InsnID*/0,
        // GIR_Coverage, 3920,
        GIR_Done,
      // Label 6519: @478373
      GIM_Try, /*On fail goto*//*Label 6520*/ GIMT_Encode4(478483), // Rule ID 3924 //
        GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasUnrestrictedSOffset),
        // MIs[0] offset
        GIM_CheckIsImm, /*MI*/0, /*Op*/5,
        // MIs[0] auxiliary
        GIM_CheckIsImm, /*MI*/0, /*Op*/6,
        // MIs[0] Operand 7
        GIM_CheckIsImm, /*MI*/0, /*Op*/7,
        GIM_CheckComplexPattern, /*MI*/0, /*Op*/4, /*Renderer*/GIMT_Encode2(0), GIMT_Encode2(GICP_gi_buf_soffset),
        // (SIbuffer_load_format:{ *:[i32] } v4i32:{ *:[v4i32] }:$rsrc, i32:{ *:[i32] }:$vindex, i32:{ *:[i32] }:$voffset, (BUFSOffset:{ *:[i32] } i32:{ *:[i32] }:$soffset), (timm:{ *:[i32] }):$offset, (timm:{ *:[i32] }):$auxiliary, (timm:{ *:[i1] }))  =>  (BUFFER_LOAD_FORMAT_X_BOTHEN:{ *:[i32] } (REG_SEQUENCE:{ *:[i64] } VReg_64:{ *:[i32] }, VGPR_32:{ *:[i32] }:$vindex, sub0:{ *:[i32] }, VGPR_32:{ *:[i32] }:$voffset, sub1:{ *:[i32] }), SReg_128:{ *:[v4i32] }:$rsrc, SCSrc_b32:{ *:[i32] }:$soffset, (timm:{ *:[i32] }):$offset, (extract_cpol:{ *:[i32] } ?:{ *:[i32] }:$auxiliary), (extract_swz:{ *:[i1] } ?:{ *:[i32] }:$auxiliary))
        GIR_MakeTempReg, /*TempRegID*/0, /*TypeID*/GILLT_s64,
        GIR_BuildMI, /*InsnID*/1, /*Opcode*/GIMT_Encode2(TargetOpcode::REG_SEQUENCE),
        GIR_AddTempRegister, /*InsnID*/1, /*TempRegID*/0, /*TempRegFlags*/GIMT_Encode2(RegState::Define),
        GIR_Copy, /*NewInsnID*/1, /*OldInsnID*/0, /*OpIdx*/2, // vindex
        GIR_AddImm8, /*InsnID*/1, /*SubRegIndex*/3,
        GIR_Copy, /*NewInsnID*/1, /*OldInsnID*/0, /*OpIdx*/3, // voffset
        GIR_AddImm8, /*InsnID*/1, /*SubRegIndex*/11,
        GIR_ConstrainOperandRC, /*InsnID*/1, /*Op*/0, GIMT_Encode2(AMDGPU::VReg_64RegClassID),
        GIR_ConstrainOperandRC, /*InsnID*/1, /*Op*/1, GIMT_Encode2(AMDGPU::VGPR_32RegClassID),
        GIR_ConstrainOperandRC, /*InsnID*/1, /*Op*/3, GIMT_Encode2(AMDGPU::VGPR_32RegClassID),
        GIR_BuildMI, /*InsnID*/0, /*Opcode*/GIMT_Encode2(AMDGPU::BUFFER_LOAD_FORMAT_X_BOTHEN),
        GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/0, // DstI[vdata]
        GIR_AddSimpleTempRegister, /*InsnID*/0, /*TempRegID*/0,
        GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/1, // rsrc
        GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/0, // soffset
        GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/5, // offset
        GIR_CustomOperandRenderer, /*InsnID*/0, /*OldInsnID*/0, /*OpIdx*/6, /*OperandRenderer*/GIMT_Encode2(GICR_renderExtractCPol), // auxiliary
        GIR_CustomOperandRenderer, /*InsnID*/0, /*OldInsnID*/0, /*OpIdx*/6, /*OperandRenderer*/GIMT_Encode2(GICR_renderExtractSWZ), // auxiliary
        GIR_MergeMemOperands, /*InsnID*/0, /*NumInsns*/1, /*MergeInsnID's*/0,
        GIR_ConstrainSelectedInstOperands, /*InsnID*/0,
        GIR_EraseFromParent, /*InsnID*/0,
        // GIR_Coverage, 3924,
        GIR_Done,
      // Label 6520: @478483
      GIM_Try, /*On fail goto*//*Label 6521*/ GIMT_Encode4(478590), // Rule ID 3928 //
        // MIs[0] offset
        GIM_CheckIsImm, /*MI*/0, /*Op*/5,
        // MIs[0] auxiliary
        GIM_CheckIsImm, /*MI*/0, /*Op*/6,
        // MIs[0] Operand 7
        GIM_CheckIsImm, /*MI*/0, /*Op*/7,
        GIM_CheckComplexPattern, /*MI*/0, /*Op*/4, /*Renderer*/GIMT_Encode2(0), GIMT_Encode2(GICP_gi_buf_soffset),
        // (SIbuffer_load_format:{ *:[i32] } v4i32:{ *:[v4i32] }:$rsrc, i32:{ *:[i32] }:$vindex, i32:{ *:[i32] }:$voffset, (BUFSOffset:{ *:[i32] } i32:{ *:[i32] }:$soffset), (timm:{ *:[i32] }):$offset, (timm:{ *:[i32] }):$auxiliary, (timm:{ *:[i1] }))  =>  (BUFFER_LOAD_FORMAT_X_VBUFFER_BOTHEN:{ *:[i32] } (REG_SEQUENCE:{ *:[i64] } VReg_64:{ *:[i32] }, VGPR_32:{ *:[i32] }:$vindex, sub0:{ *:[i32] }, VGPR_32:{ *:[i32] }:$voffset, sub1:{ *:[i32] }), SReg_128:{ *:[v4i32] }:$rsrc, SCSrc_b32:{ *:[i32] }:$soffset, (timm:{ *:[i32] }):$offset, (extract_cpol:{ *:[i32] } ?:{ *:[i32] }:$auxiliary), (extract_swz:{ *:[i1] } ?:{ *:[i32] }:$auxiliary))
        GIR_MakeTempReg, /*TempRegID*/0, /*TypeID*/GILLT_s64,
        GIR_BuildMI, /*InsnID*/1, /*Opcode*/GIMT_Encode2(TargetOpcode::REG_SEQUENCE),
        GIR_AddTempRegister, /*InsnID*/1, /*TempRegID*/0, /*TempRegFlags*/GIMT_Encode2(RegState::Define),
        GIR_Copy, /*NewInsnID*/1, /*OldInsnID*/0, /*OpIdx*/2, // vindex
        GIR_AddImm8, /*InsnID*/1, /*SubRegIndex*/3,
        GIR_Copy, /*NewInsnID*/1, /*OldInsnID*/0, /*OpIdx*/3, // voffset
        GIR_AddImm8, /*InsnID*/1, /*SubRegIndex*/11,
        GIR_ConstrainOperandRC, /*InsnID*/1, /*Op*/0, GIMT_Encode2(AMDGPU::VReg_64RegClassID),
        GIR_ConstrainOperandRC, /*InsnID*/1, /*Op*/1, GIMT_Encode2(AMDGPU::VGPR_32RegClassID),
        GIR_ConstrainOperandRC, /*InsnID*/1, /*Op*/3, GIMT_Encode2(AMDGPU::VGPR_32RegClassID),
        GIR_BuildMI, /*InsnID*/0, /*Opcode*/GIMT_Encode2(AMDGPU::BUFFER_LOAD_FORMAT_X_VBUFFER_BOTHEN),
        GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/0, // DstI[vdata]
        GIR_AddSimpleTempRegister, /*InsnID*/0, /*TempRegID*/0,
        GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/1, // rsrc
        GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/0, // soffset
        GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/5, // offset
        GIR_CustomOperandRenderer, /*InsnID*/0, /*OldInsnID*/0, /*OpIdx*/6, /*OperandRenderer*/GIMT_Encode2(GICR_renderExtractCPol), // auxiliary
        GIR_CustomOperandRenderer, /*InsnID*/0, /*OldInsnID*/0, /*OpIdx*/6, /*OperandRenderer*/GIMT_Encode2(GICR_renderExtractSWZ), // auxiliary
        GIR_MergeMemOperands, /*InsnID*/0, /*NumInsns*/1, /*MergeInsnID's*/0,
        GIR_ConstrainSelectedInstOperands, /*InsnID*/0,
        GIR_EraseFromParent, /*InsnID*/0,
        // GIR_Coverage, 3928,
        GIR_Done,
      // Label 6521: @478590
      GIM_Reject,
    // Label 6505: @478591
    GIM_Reject,
    // Label 6501: @478592
    GIM_Try, /*On fail goto*//*Label 6522*/ GIMT_Encode4(479987),
      GIM_CheckType, /*MI*/0, /*Op*/1, /*Type*/GILLT_v4s32,
      GIM_CheckType, /*MI*/0, /*Op*/2, /*Type*/GILLT_s32,
      GIM_CheckType, /*MI*/0, /*Op*/3, /*Type*/GILLT_s32,
      GIM_CheckType, /*MI*/0, /*Op*/4, /*Type*/GILLT_s32,
      GIM_CheckRegBankForClass, /*MI*/0, /*Op*/0, /*RC*/GIMT_Encode2(AMDGPU::AV_64RegClassID),
      GIM_Try, /*On fail goto*//*Label 6523*/ GIMT_Encode4(478700), // Rule ID 3929 //
        GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasUnrestrictedSOffset),
        GIM_CheckConstantInt8, /*MI*/0, /*Op*/2, 0,
        GIM_CheckConstantInt8, /*MI*/0, /*Op*/3, 0,
        // MIs[0] offset
        GIM_CheckIsImm, /*MI*/0, /*Op*/5,
        // MIs[0] auxiliary
        GIM_CheckIsImm, /*MI*/0, /*Op*/6,
        // MIs[0] Operand 7
        GIM_CheckLiteralInt, /*MI*/0, /*Op*/7, GIMT_Encode8(0),
        GIM_CheckComplexPattern, /*MI*/0, /*Op*/4, /*Renderer*/GIMT_Encode2(0), GIMT_Encode2(GICP_gi_buf_soffset),
        // (SIbuffer_load_format:{ *:[v2f32] } v4i32:{ *:[v4i32] }:$rsrc, 0:{ *:[i32] }, 0:{ *:[i32] }, (BUFSOffset:{ *:[i32] } i32:{ *:[i32] }:$soffset), (timm:{ *:[i32] }):$offset, (timm:{ *:[i32] }):$auxiliary, 0:{ *:[i1] })  =>  (BUFFER_LOAD_FORMAT_XY_OFFSET:{ *:[v2f32] } SReg_128:{ *:[v4i32] }:$rsrc, SCSrc_b32:{ *:[i32] }:$soffset, (timm:{ *:[i32] }):$offset, (extract_cpol:{ *:[i32] } ?:{ *:[i32] }:$auxiliary), (extract_swz:{ *:[i1] } ?:{ *:[i32] }:$auxiliary))
        GIR_BuildMI, /*InsnID*/0, /*Opcode*/GIMT_Encode2(AMDGPU::BUFFER_LOAD_FORMAT_XY_OFFSET),
        GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/0, // DstI[vdata]
        GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/1, // rsrc
        GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/0, // soffset
        GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/5, // offset
        GIR_CustomOperandRenderer, /*InsnID*/0, /*OldInsnID*/0, /*OpIdx*/6, /*OperandRenderer*/GIMT_Encode2(GICR_renderExtractCPol), // auxiliary
        GIR_CustomOperandRenderer, /*InsnID*/0, /*OldInsnID*/0, /*OpIdx*/6, /*OperandRenderer*/GIMT_Encode2(GICR_renderExtractSWZ), // auxiliary
        GIR_MergeMemOperands, /*InsnID*/0, /*NumInsns*/1, /*MergeInsnID's*/0,
        GIR_ConstrainSelectedInstOperands, /*InsnID*/0,
        GIR_EraseFromParent, /*InsnID*/0,
        // GIR_Coverage, 3929,
        GIR_Done,
      // Label 6523: @478700
      GIM_Try, /*On fail goto*//*Label 6524*/ GIMT_Encode4(478779), // Rule ID 3933 //
        GIM_CheckConstantInt8, /*MI*/0, /*Op*/2, 0,
        GIM_CheckConstantInt8, /*MI*/0, /*Op*/3, 0,
        // MIs[0] offset
        GIM_CheckIsImm, /*MI*/0, /*Op*/5,
        // MIs[0] auxiliary
        GIM_CheckIsImm, /*MI*/0, /*Op*/6,
        // MIs[0] Operand 7
        GIM_CheckLiteralInt, /*MI*/0, /*Op*/7, GIMT_Encode8(0),
        GIM_CheckComplexPattern, /*MI*/0, /*Op*/4, /*Renderer*/GIMT_Encode2(0), GIMT_Encode2(GICP_gi_buf_soffset),
        // (SIbuffer_load_format:{ *:[v2f32] } v4i32:{ *:[v4i32] }:$rsrc, 0:{ *:[i32] }, 0:{ *:[i32] }, (BUFSOffset:{ *:[i32] } i32:{ *:[i32] }:$soffset), (timm:{ *:[i32] }):$offset, (timm:{ *:[i32] }):$auxiliary, 0:{ *:[i1] })  =>  (BUFFER_LOAD_FORMAT_XY_VBUFFER_OFFSET:{ *:[v2f32] } SReg_128:{ *:[v4i32] }:$rsrc, SCSrc_b32:{ *:[i32] }:$soffset, (timm:{ *:[i32] }):$offset, (extract_cpol:{ *:[i32] } ?:{ *:[i32] }:$auxiliary), (extract_swz:{ *:[i1] } ?:{ *:[i32] }:$auxiliary))
        GIR_BuildMI, /*InsnID*/0, /*Opcode*/GIMT_Encode2(AMDGPU::BUFFER_LOAD_FORMAT_XY_VBUFFER_OFFSET),
        GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/0, // DstI[vdata]
        GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/1, // rsrc
        GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/0, // soffset
        GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/5, // offset
        GIR_CustomOperandRenderer, /*InsnID*/0, /*OldInsnID*/0, /*OpIdx*/6, /*OperandRenderer*/GIMT_Encode2(GICR_renderExtractCPol), // auxiliary
        GIR_CustomOperandRenderer, /*InsnID*/0, /*OldInsnID*/0, /*OpIdx*/6, /*OperandRenderer*/GIMT_Encode2(GICR_renderExtractSWZ), // auxiliary
        GIR_MergeMemOperands, /*InsnID*/0, /*NumInsns*/1, /*MergeInsnID's*/0,
        GIR_ConstrainSelectedInstOperands, /*InsnID*/0,
        GIR_EraseFromParent, /*InsnID*/0,
        // GIR_Coverage, 3933,
        GIR_Done,
      // Label 6524: @478779
      GIM_Try, /*On fail goto*//*Label 6525*/ GIMT_Encode4(478861), // Rule ID 3937 //
        GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasUnrestrictedSOffset),
        GIM_CheckConstantInt8, /*MI*/0, /*Op*/2, 0,
        GIM_CheckConstantInt8, /*MI*/0, /*Op*/3, 0,
        // MIs[0] offset
        GIM_CheckIsImm, /*MI*/0, /*Op*/5,
        // MIs[0] auxiliary
        GIM_CheckIsImm, /*MI*/0, /*Op*/6,
        // MIs[0] Operand 7
        GIM_CheckLiteralInt, /*MI*/0, /*Op*/7, GIMT_Encode8(0),
        GIM_CheckComplexPattern, /*MI*/0, /*Op*/4, /*Renderer*/GIMT_Encode2(0), GIMT_Encode2(GICP_gi_buf_soffset),
        // (SIbuffer_load_format:{ *:[v2i32] } v4i32:{ *:[v4i32] }:$rsrc, 0:{ *:[i32] }, 0:{ *:[i32] }, (BUFSOffset:{ *:[i32] } i32:{ *:[i32] }:$soffset), (timm:{ *:[i32] }):$offset, (timm:{ *:[i32] }):$auxiliary, 0:{ *:[i1] })  =>  (BUFFER_LOAD_FORMAT_XY_OFFSET:{ *:[v2i32] } SReg_128:{ *:[v4i32] }:$rsrc, SCSrc_b32:{ *:[i32] }:$soffset, (timm:{ *:[i32] }):$offset, (extract_cpol:{ *:[i32] } ?:{ *:[i32] }:$auxiliary), (extract_swz:{ *:[i1] } ?:{ *:[i32] }:$auxiliary))
        GIR_BuildMI, /*InsnID*/0, /*Opcode*/GIMT_Encode2(AMDGPU::BUFFER_LOAD_FORMAT_XY_OFFSET),
        GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/0, // DstI[vdata]
        GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/1, // rsrc
        GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/0, // soffset
        GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/5, // offset
        GIR_CustomOperandRenderer, /*InsnID*/0, /*OldInsnID*/0, /*OpIdx*/6, /*OperandRenderer*/GIMT_Encode2(GICR_renderExtractCPol), // auxiliary
        GIR_CustomOperandRenderer, /*InsnID*/0, /*OldInsnID*/0, /*OpIdx*/6, /*OperandRenderer*/GIMT_Encode2(GICR_renderExtractSWZ), // auxiliary
        GIR_MergeMemOperands, /*InsnID*/0, /*NumInsns*/1, /*MergeInsnID's*/0,
        GIR_ConstrainSelectedInstOperands, /*InsnID*/0,
        GIR_EraseFromParent, /*InsnID*/0,
        // GIR_Coverage, 3937,
        GIR_Done,
      // Label 6525: @478861
      GIM_Try, /*On fail goto*//*Label 6526*/ GIMT_Encode4(478940), // Rule ID 3941 //
        GIM_CheckConstantInt8, /*MI*/0, /*Op*/2, 0,
        GIM_CheckConstantInt8, /*MI*/0, /*Op*/3, 0,
        // MIs[0] offset
        GIM_CheckIsImm, /*MI*/0, /*Op*/5,
        // MIs[0] auxiliary
        GIM_CheckIsImm, /*MI*/0, /*Op*/6,
        // MIs[0] Operand 7
        GIM_CheckLiteralInt, /*MI*/0, /*Op*/7, GIMT_Encode8(0),
        GIM_CheckComplexPattern, /*MI*/0, /*Op*/4, /*Renderer*/GIMT_Encode2(0), GIMT_Encode2(GICP_gi_buf_soffset),
        // (SIbuffer_load_format:{ *:[v2i32] } v4i32:{ *:[v4i32] }:$rsrc, 0:{ *:[i32] }, 0:{ *:[i32] }, (BUFSOffset:{ *:[i32] } i32:{ *:[i32] }:$soffset), (timm:{ *:[i32] }):$offset, (timm:{ *:[i32] }):$auxiliary, 0:{ *:[i1] })  =>  (BUFFER_LOAD_FORMAT_XY_VBUFFER_OFFSET:{ *:[v2i32] } SReg_128:{ *:[v4i32] }:$rsrc, SCSrc_b32:{ *:[i32] }:$soffset, (timm:{ *:[i32] }):$offset, (extract_cpol:{ *:[i32] } ?:{ *:[i32] }:$auxiliary), (extract_swz:{ *:[i1] } ?:{ *:[i32] }:$auxiliary))
        GIR_BuildMI, /*InsnID*/0, /*Opcode*/GIMT_Encode2(AMDGPU::BUFFER_LOAD_FORMAT_XY_VBUFFER_OFFSET),
        GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/0, // DstI[vdata]
        GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/1, // rsrc
        GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/0, // soffset
        GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/5, // offset
        GIR_CustomOperandRenderer, /*InsnID*/0, /*OldInsnID*/0, /*OpIdx*/6, /*OperandRenderer*/GIMT_Encode2(GICR_renderExtractCPol), // auxiliary
        GIR_CustomOperandRenderer, /*InsnID*/0, /*OldInsnID*/0, /*OpIdx*/6, /*OperandRenderer*/GIMT_Encode2(GICR_renderExtractSWZ), // auxiliary
        GIR_MergeMemOperands, /*InsnID*/0, /*NumInsns*/1, /*MergeInsnID's*/0,
        GIR_ConstrainSelectedInstOperands, /*InsnID*/0,
        GIR_EraseFromParent, /*InsnID*/0,
        // GIR_Coverage, 3941,
        GIR_Done,
      // Label 6526: @478940
      GIM_Try, /*On fail goto*//*Label 6527*/ GIMT_Encode4(479022), // Rule ID 3930 //
        GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasUnrestrictedSOffset),
        GIM_CheckConstantInt8, /*MI*/0, /*Op*/2, 0,
        // MIs[0] offset
        GIM_CheckIsImm, /*MI*/0, /*Op*/5,
        // MIs[0] auxiliary
        GIM_CheckIsImm, /*MI*/0, /*Op*/6,
        // MIs[0] Operand 7
        GIM_CheckLiteralInt, /*MI*/0, /*Op*/7, GIMT_Encode8(0),
        GIM_CheckComplexPattern, /*MI*/0, /*Op*/4, /*Renderer*/GIMT_Encode2(0), GIMT_Encode2(GICP_gi_buf_soffset),
        // (SIbuffer_load_format:{ *:[v2f32] } v4i32:{ *:[v4i32] }:$rsrc, 0:{ *:[i32] }, i32:{ *:[i32] }:$voffset, (BUFSOffset:{ *:[i32] } i32:{ *:[i32] }:$soffset), (timm:{ *:[i32] }):$offset, (timm:{ *:[i32] }):$auxiliary, 0:{ *:[i1] })  =>  (BUFFER_LOAD_FORMAT_XY_OFFEN:{ *:[v2f32] } VGPR_32:{ *:[i32] }:$voffset, SReg_128:{ *:[v4i32] }:$rsrc, SCSrc_b32:{ *:[i32] }:$soffset, (timm:{ *:[i32] }):$offset, (extract_cpol:{ *:[i32] } ?:{ *:[i32] }:$auxiliary), (extract_swz:{ *:[i1] } ?:{ *:[i32] }:$auxiliary))
        GIR_BuildMI, /*InsnID*/0, /*Opcode*/GIMT_Encode2(AMDGPU::BUFFER_LOAD_FORMAT_XY_OFFEN),
        GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/0, // DstI[vdata]
        GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/3, // voffset
        GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/1, // rsrc
        GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/0, // soffset
        GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/5, // offset
        GIR_CustomOperandRenderer, /*InsnID*/0, /*OldInsnID*/0, /*OpIdx*/6, /*OperandRenderer*/GIMT_Encode2(GICR_renderExtractCPol), // auxiliary
        GIR_CustomOperandRenderer, /*InsnID*/0, /*OldInsnID*/0, /*OpIdx*/6, /*OperandRenderer*/GIMT_Encode2(GICR_renderExtractSWZ), // auxiliary
        GIR_MergeMemOperands, /*InsnID*/0, /*NumInsns*/1, /*MergeInsnID's*/0,
        GIR_ConstrainSelectedInstOperands, /*InsnID*/0,
        GIR_EraseFromParent, /*InsnID*/0,
        // GIR_Coverage, 3930,
        GIR_Done,
      // Label 6527: @479022
      GIM_Try, /*On fail goto*//*Label 6528*/ GIMT_Encode4(479101), // Rule ID 3934 //
        GIM_CheckConstantInt8, /*MI*/0, /*Op*/2, 0,
        // MIs[0] offset
        GIM_CheckIsImm, /*MI*/0, /*Op*/5,
        // MIs[0] auxiliary
        GIM_CheckIsImm, /*MI*/0, /*Op*/6,
        // MIs[0] Operand 7
        GIM_CheckLiteralInt, /*MI*/0, /*Op*/7, GIMT_Encode8(0),
        GIM_CheckComplexPattern, /*MI*/0, /*Op*/4, /*Renderer*/GIMT_Encode2(0), GIMT_Encode2(GICP_gi_buf_soffset),
        // (SIbuffer_load_format:{ *:[v2f32] } v4i32:{ *:[v4i32] }:$rsrc, 0:{ *:[i32] }, i32:{ *:[i32] }:$voffset, (BUFSOffset:{ *:[i32] } i32:{ *:[i32] }:$soffset), (timm:{ *:[i32] }):$offset, (timm:{ *:[i32] }):$auxiliary, 0:{ *:[i1] })  =>  (BUFFER_LOAD_FORMAT_XY_VBUFFER_OFFEN:{ *:[v2f32] } VGPR_32:{ *:[i32] }:$voffset, SReg_128:{ *:[v4i32] }:$rsrc, SCSrc_b32:{ *:[i32] }:$soffset, (timm:{ *:[i32] }):$offset, (extract_cpol:{ *:[i32] } ?:{ *:[i32] }:$auxiliary), (extract_swz:{ *:[i1] } ?:{ *:[i32] }:$auxiliary))
        GIR_BuildMI, /*InsnID*/0, /*Opcode*/GIMT_Encode2(AMDGPU::BUFFER_LOAD_FORMAT_XY_VBUFFER_OFFEN),
        GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/0, // DstI[vdata]
        GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/3, // voffset
        GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/1, // rsrc
        GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/0, // soffset
        GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/5, // offset
        GIR_CustomOperandRenderer, /*InsnID*/0, /*OldInsnID*/0, /*OpIdx*/6, /*OperandRenderer*/GIMT_Encode2(GICR_renderExtractCPol), // auxiliary
        GIR_CustomOperandRenderer, /*InsnID*/0, /*OldInsnID*/0, /*OpIdx*/6, /*OperandRenderer*/GIMT_Encode2(GICR_renderExtractSWZ), // auxiliary
        GIR_MergeMemOperands, /*InsnID*/0, /*NumInsns*/1, /*MergeInsnID's*/0,
        GIR_ConstrainSelectedInstOperands, /*InsnID*/0,
        GIR_EraseFromParent, /*InsnID*/0,
        // GIR_Coverage, 3934,
        GIR_Done,
      // Label 6528: @479101
      GIM_Try, /*On fail goto*//*Label 6529*/ GIMT_Encode4(479183), // Rule ID 3938 //
        GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasUnrestrictedSOffset),
        GIM_CheckConstantInt8, /*MI*/0, /*Op*/2, 0,
        // MIs[0] offset
        GIM_CheckIsImm, /*MI*/0, /*Op*/5,
        // MIs[0] auxiliary
        GIM_CheckIsImm, /*MI*/0, /*Op*/6,
        // MIs[0] Operand 7
        GIM_CheckLiteralInt, /*MI*/0, /*Op*/7, GIMT_Encode8(0),
        GIM_CheckComplexPattern, /*MI*/0, /*Op*/4, /*Renderer*/GIMT_Encode2(0), GIMT_Encode2(GICP_gi_buf_soffset),
        // (SIbuffer_load_format:{ *:[v2i32] } v4i32:{ *:[v4i32] }:$rsrc, 0:{ *:[i32] }, i32:{ *:[i32] }:$voffset, (BUFSOffset:{ *:[i32] } i32:{ *:[i32] }:$soffset), (timm:{ *:[i32] }):$offset, (timm:{ *:[i32] }):$auxiliary, 0:{ *:[i1] })  =>  (BUFFER_LOAD_FORMAT_XY_OFFEN:{ *:[v2i32] } VGPR_32:{ *:[i32] }:$voffset, SReg_128:{ *:[v4i32] }:$rsrc, SCSrc_b32:{ *:[i32] }:$soffset, (timm:{ *:[i32] }):$offset, (extract_cpol:{ *:[i32] } ?:{ *:[i32] }:$auxiliary), (extract_swz:{ *:[i1] } ?:{ *:[i32] }:$auxiliary))
        GIR_BuildMI, /*InsnID*/0, /*Opcode*/GIMT_Encode2(AMDGPU::BUFFER_LOAD_FORMAT_XY_OFFEN),
        GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/0, // DstI[vdata]
        GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/3, // voffset
        GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/1, // rsrc
        GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/0, // soffset
        GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/5, // offset
        GIR_CustomOperandRenderer, /*InsnID*/0, /*OldInsnID*/0, /*OpIdx*/6, /*OperandRenderer*/GIMT_Encode2(GICR_renderExtractCPol), // auxiliary
        GIR_CustomOperandRenderer, /*InsnID*/0, /*OldInsnID*/0, /*OpIdx*/6, /*OperandRenderer*/GIMT_Encode2(GICR_renderExtractSWZ), // auxiliary
        GIR_MergeMemOperands, /*InsnID*/0, /*NumInsns*/1, /*MergeInsnID's*/0,
        GIR_ConstrainSelectedInstOperands, /*InsnID*/0,
        GIR_EraseFromParent, /*InsnID*/0,
        // GIR_Coverage, 3938,
        GIR_Done,
      // Label 6529: @479183
      GIM_Try, /*On fail goto*//*Label 6530*/ GIMT_Encode4(479262), // Rule ID 3942 //
        GIM_CheckConstantInt8, /*MI*/0, /*Op*/2, 0,
        // MIs[0] offset
        GIM_CheckIsImm, /*MI*/0, /*Op*/5,
        // MIs[0] auxiliary
        GIM_CheckIsImm, /*MI*/0, /*Op*/6,
        // MIs[0] Operand 7
        GIM_CheckLiteralInt, /*MI*/0, /*Op*/7, GIMT_Encode8(0),
        GIM_CheckComplexPattern, /*MI*/0, /*Op*/4, /*Renderer*/GIMT_Encode2(0), GIMT_Encode2(GICP_gi_buf_soffset),
        // (SIbuffer_load_format:{ *:[v2i32] } v4i32:{ *:[v4i32] }:$rsrc, 0:{ *:[i32] }, i32:{ *:[i32] }:$voffset, (BUFSOffset:{ *:[i32] } i32:{ *:[i32] }:$soffset), (timm:{ *:[i32] }):$offset, (timm:{ *:[i32] }):$auxiliary, 0:{ *:[i1] })  =>  (BUFFER_LOAD_FORMAT_XY_VBUFFER_OFFEN:{ *:[v2i32] } VGPR_32:{ *:[i32] }:$voffset, SReg_128:{ *:[v4i32] }:$rsrc, SCSrc_b32:{ *:[i32] }:$soffset, (timm:{ *:[i32] }):$offset, (extract_cpol:{ *:[i32] } ?:{ *:[i32] }:$auxiliary), (extract_swz:{ *:[i1] } ?:{ *:[i32] }:$auxiliary))
        GIR_BuildMI, /*InsnID*/0, /*Opcode*/GIMT_Encode2(AMDGPU::BUFFER_LOAD_FORMAT_XY_VBUFFER_OFFEN),
        GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/0, // DstI[vdata]
        GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/3, // voffset
        GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/1, // rsrc
        GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/0, // soffset
        GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/5, // offset
        GIR_CustomOperandRenderer, /*InsnID*/0, /*OldInsnID*/0, /*OpIdx*/6, /*OperandRenderer*/GIMT_Encode2(GICR_renderExtractCPol), // auxiliary
        GIR_CustomOperandRenderer, /*InsnID*/0, /*OldInsnID*/0, /*OpIdx*/6, /*OperandRenderer*/GIMT_Encode2(GICR_renderExtractSWZ), // auxiliary
        GIR_MergeMemOperands, /*InsnID*/0, /*NumInsns*/1, /*MergeInsnID's*/0,
        GIR_ConstrainSelectedInstOperands, /*InsnID*/0,
        GIR_EraseFromParent, /*InsnID*/0,
        // GIR_Coverage, 3942,
        GIR_Done,
      // Label 6530: @479262
      GIM_Try, /*On fail goto*//*Label 6531*/ GIMT_Encode4(479336), // Rule ID 3931 //
        GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasUnrestrictedSOffset),
        GIM_CheckConstantInt8, /*MI*/0, /*Op*/3, 0,
        // MIs[0] offset
        GIM_CheckIsImm, /*MI*/0, /*Op*/5,
        // MIs[0] auxiliary
        GIM_CheckIsImm, /*MI*/0, /*Op*/6,
        // MIs[0] Operand 7
        GIM_CheckIsImm, /*MI*/0, /*Op*/7,
        GIM_CheckComplexPattern, /*MI*/0, /*Op*/4, /*Renderer*/GIMT_Encode2(0), GIMT_Encode2(GICP_gi_buf_soffset),
        // (SIbuffer_load_format:{ *:[v2f32] } v4i32:{ *:[v4i32] }:$rsrc, i32:{ *:[i32] }:$vindex, 0:{ *:[i32] }, (BUFSOffset:{ *:[i32] } i32:{ *:[i32] }:$soffset), (timm:{ *:[i32] }):$offset, (timm:{ *:[i32] }):$auxiliary, (timm:{ *:[i1] }))  =>  (BUFFER_LOAD_FORMAT_XY_IDXEN:{ *:[v2f32] } VGPR_32:{ *:[i32] }:$vindex, SReg_128:{ *:[v4i32] }:$rsrc, SCSrc_b32:{ *:[i32] }:$soffset, (timm:{ *:[i32] }):$offset, (extract_cpol:{ *:[i32] } ?:{ *:[i32] }:$auxiliary), (extract_swz:{ *:[i1] } ?:{ *:[i32] }:$auxiliary))
        GIR_BuildMI, /*InsnID*/0, /*Opcode*/GIMT_Encode2(AMDGPU::BUFFER_LOAD_FORMAT_XY_IDXEN),
        GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/0, // DstI[vdata]
        GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/2, // vindex
        GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/1, // rsrc
        GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/0, // soffset
        GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/5, // offset
        GIR_CustomOperandRenderer, /*InsnID*/0, /*OldInsnID*/0, /*OpIdx*/6, /*OperandRenderer*/GIMT_Encode2(GICR_renderExtractCPol), // auxiliary
        GIR_CustomOperandRenderer, /*InsnID*/0, /*OldInsnID*/0, /*OpIdx*/6, /*OperandRenderer*/GIMT_Encode2(GICR_renderExtractSWZ), // auxiliary
        GIR_MergeMemOperands, /*InsnID*/0, /*NumInsns*/1, /*MergeInsnID's*/0,
        GIR_ConstrainSelectedInstOperands, /*InsnID*/0,
        GIR_EraseFromParent, /*InsnID*/0,
        // GIR_Coverage, 3931,
        GIR_Done,
      // Label 6531: @479336
      GIM_Try, /*On fail goto*//*Label 6532*/ GIMT_Encode4(479407), // Rule ID 3935 //
        GIM_CheckConstantInt8, /*MI*/0, /*Op*/3, 0,
        // MIs[0] offset
        GIM_CheckIsImm, /*MI*/0, /*Op*/5,
        // MIs[0] auxiliary
        GIM_CheckIsImm, /*MI*/0, /*Op*/6,
        // MIs[0] Operand 7
        GIM_CheckIsImm, /*MI*/0, /*Op*/7,
        GIM_CheckComplexPattern, /*MI*/0, /*Op*/4, /*Renderer*/GIMT_Encode2(0), GIMT_Encode2(GICP_gi_buf_soffset),
        // (SIbuffer_load_format:{ *:[v2f32] } v4i32:{ *:[v4i32] }:$rsrc, i32:{ *:[i32] }:$vindex, 0:{ *:[i32] }, (BUFSOffset:{ *:[i32] } i32:{ *:[i32] }:$soffset), (timm:{ *:[i32] }):$offset, (timm:{ *:[i32] }):$auxiliary, (timm:{ *:[i1] }))  =>  (BUFFER_LOAD_FORMAT_XY_VBUFFER_IDXEN:{ *:[v2f32] } VGPR_32:{ *:[i32] }:$vindex, SReg_128:{ *:[v4i32] }:$rsrc, SCSrc_b32:{ *:[i32] }:$soffset, (timm:{ *:[i32] }):$offset, (extract_cpol:{ *:[i32] } ?:{ *:[i32] }:$auxiliary), (extract_swz:{ *:[i1] } ?:{ *:[i32] }:$auxiliary))
        GIR_BuildMI, /*InsnID*/0, /*Opcode*/GIMT_Encode2(AMDGPU::BUFFER_LOAD_FORMAT_XY_VBUFFER_IDXEN),
        GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/0, // DstI[vdata]
        GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/2, // vindex
        GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/1, // rsrc
        GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/0, // soffset
        GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/5, // offset
        GIR_CustomOperandRenderer, /*InsnID*/0, /*OldInsnID*/0, /*OpIdx*/6, /*OperandRenderer*/GIMT_Encode2(GICR_renderExtractCPol), // auxiliary
        GIR_CustomOperandRenderer, /*InsnID*/0, /*OldInsnID*/0, /*OpIdx*/6, /*OperandRenderer*/GIMT_Encode2(GICR_renderExtractSWZ), // auxiliary
        GIR_MergeMemOperands, /*InsnID*/0, /*NumInsns*/1, /*MergeInsnID's*/0,
        GIR_ConstrainSelectedInstOperands, /*InsnID*/0,
        GIR_EraseFromParent, /*InsnID*/0,
        // GIR_Coverage, 3935,
        GIR_Done,
      // Label 6532: @479407
      GIM_Try, /*On fail goto*//*Label 6533*/ GIMT_Encode4(479481), // Rule ID 3939 //
        GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasUnrestrictedSOffset),
        GIM_CheckConstantInt8, /*MI*/0, /*Op*/3, 0,
        // MIs[0] offset
        GIM_CheckIsImm, /*MI*/0, /*Op*/5,
        // MIs[0] auxiliary
        GIM_CheckIsImm, /*MI*/0, /*Op*/6,
        // MIs[0] Operand 7
        GIM_CheckIsImm, /*MI*/0, /*Op*/7,
        GIM_CheckComplexPattern, /*MI*/0, /*Op*/4, /*Renderer*/GIMT_Encode2(0), GIMT_Encode2(GICP_gi_buf_soffset),
        // (SIbuffer_load_format:{ *:[v2i32] } v4i32:{ *:[v4i32] }:$rsrc, i32:{ *:[i32] }:$vindex, 0:{ *:[i32] }, (BUFSOffset:{ *:[i32] } i32:{ *:[i32] }:$soffset), (timm:{ *:[i32] }):$offset, (timm:{ *:[i32] }):$auxiliary, (timm:{ *:[i1] }))  =>  (BUFFER_LOAD_FORMAT_XY_IDXEN:{ *:[v2i32] } VGPR_32:{ *:[i32] }:$vindex, SReg_128:{ *:[v4i32] }:$rsrc, SCSrc_b32:{ *:[i32] }:$soffset, (timm:{ *:[i32] }):$offset, (extract_cpol:{ *:[i32] } ?:{ *:[i32] }:$auxiliary), (extract_swz:{ *:[i1] } ?:{ *:[i32] }:$auxiliary))
        GIR_BuildMI, /*InsnID*/0, /*Opcode*/GIMT_Encode2(AMDGPU::BUFFER_LOAD_FORMAT_XY_IDXEN),
        GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/0, // DstI[vdata]
        GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/2, // vindex
        GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/1, // rsrc
        GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/0, // soffset
        GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/5, // offset
        GIR_CustomOperandRenderer, /*InsnID*/0, /*OldInsnID*/0, /*OpIdx*/6, /*OperandRenderer*/GIMT_Encode2(GICR_renderExtractCPol), // auxiliary
        GIR_CustomOperandRenderer, /*InsnID*/0, /*OldInsnID*/0, /*OpIdx*/6, /*OperandRenderer*/GIMT_Encode2(GICR_renderExtractSWZ), // auxiliary
        GIR_MergeMemOperands, /*InsnID*/0, /*NumInsns*/1, /*MergeInsnID's*/0,
        GIR_ConstrainSelectedInstOperands, /*InsnID*/0,
        GIR_EraseFromParent, /*InsnID*/0,
        // GIR_Coverage, 3939,
        GIR_Done,
      // Label 6533: @479481
      GIM_Try, /*On fail goto*//*Label 6534*/ GIMT_Encode4(479552), // Rule ID 3943 //
        GIM_CheckConstantInt8, /*MI*/0, /*Op*/3, 0,
        // MIs[0] offset
        GIM_CheckIsImm, /*MI*/0, /*Op*/5,
        // MIs[0] auxiliary
        GIM_CheckIsImm, /*MI*/0, /*Op*/6,
        // MIs[0] Operand 7
        GIM_CheckIsImm, /*MI*/0, /*Op*/7,
        GIM_CheckComplexPattern, /*MI*/0, /*Op*/4, /*Renderer*/GIMT_Encode2(0), GIMT_Encode2(GICP_gi_buf_soffset),
        // (SIbuffer_load_format:{ *:[v2i32] } v4i32:{ *:[v4i32] }:$rsrc, i32:{ *:[i32] }:$vindex, 0:{ *:[i32] }, (BUFSOffset:{ *:[i32] } i32:{ *:[i32] }:$soffset), (timm:{ *:[i32] }):$offset, (timm:{ *:[i32] }):$auxiliary, (timm:{ *:[i1] }))  =>  (BUFFER_LOAD_FORMAT_XY_VBUFFER_IDXEN:{ *:[v2i32] } VGPR_32:{ *:[i32] }:$vindex, SReg_128:{ *:[v4i32] }:$rsrc, SCSrc_b32:{ *:[i32] }:$soffset, (timm:{ *:[i32] }):$offset, (extract_cpol:{ *:[i32] } ?:{ *:[i32] }:$auxiliary), (extract_swz:{ *:[i1] } ?:{ *:[i32] }:$auxiliary))
        GIR_BuildMI, /*InsnID*/0, /*Opcode*/GIMT_Encode2(AMDGPU::BUFFER_LOAD_FORMAT_XY_VBUFFER_IDXEN),
        GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/0, // DstI[vdata]
        GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/2, // vindex
        GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/1, // rsrc
        GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/0, // soffset
        GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/5, // offset
        GIR_CustomOperandRenderer, /*InsnID*/0, /*OldInsnID*/0, /*OpIdx*/6, /*OperandRenderer*/GIMT_Encode2(GICR_renderExtractCPol), // auxiliary
        GIR_CustomOperandRenderer, /*InsnID*/0, /*OldInsnID*/0, /*OpIdx*/6, /*OperandRenderer*/GIMT_Encode2(GICR_renderExtractSWZ), // auxiliary
        GIR_MergeMemOperands, /*InsnID*/0, /*NumInsns*/1, /*MergeInsnID's*/0,
        GIR_ConstrainSelectedInstOperands, /*InsnID*/0,
        GIR_EraseFromParent, /*InsnID*/0,
        // GIR_Coverage, 3943,
        GIR_Done,
      // Label 6534: @479552
      GIM_Try, /*On fail goto*//*Label 6535*/ GIMT_Encode4(479662), // Rule ID 3932 //
        GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasUnrestrictedSOffset),
        // MIs[0] offset
        GIM_CheckIsImm, /*MI*/0, /*Op*/5,
        // MIs[0] auxiliary
        GIM_CheckIsImm, /*MI*/0, /*Op*/6,
        // MIs[0] Operand 7
        GIM_CheckIsImm, /*MI*/0, /*Op*/7,
        GIM_CheckComplexPattern, /*MI*/0, /*Op*/4, /*Renderer*/GIMT_Encode2(0), GIMT_Encode2(GICP_gi_buf_soffset),
        // (SIbuffer_load_format:{ *:[v2f32] } v4i32:{ *:[v4i32] }:$rsrc, i32:{ *:[i32] }:$vindex, i32:{ *:[i32] }:$voffset, (BUFSOffset:{ *:[i32] } i32:{ *:[i32] }:$soffset), (timm:{ *:[i32] }):$offset, (timm:{ *:[i32] }):$auxiliary, (timm:{ *:[i1] }))  =>  (BUFFER_LOAD_FORMAT_XY_BOTHEN:{ *:[v2f32] } (REG_SEQUENCE:{ *:[i64] } VReg_64:{ *:[i32] }, VGPR_32:{ *:[i32] }:$vindex, sub0:{ *:[i32] }, VGPR_32:{ *:[i32] }:$voffset, sub1:{ *:[i32] }), SReg_128:{ *:[v4i32] }:$rsrc, SCSrc_b32:{ *:[i32] }:$soffset, (timm:{ *:[i32] }):$offset, (extract_cpol:{ *:[i32] } ?:{ *:[i32] }:$auxiliary), (extract_swz:{ *:[i1] } ?:{ *:[i32] }:$auxiliary))
        GIR_MakeTempReg, /*TempRegID*/0, /*TypeID*/GILLT_s64,
        GIR_BuildMI, /*InsnID*/1, /*Opcode*/GIMT_Encode2(TargetOpcode::REG_SEQUENCE),
        GIR_AddTempRegister, /*InsnID*/1, /*TempRegID*/0, /*TempRegFlags*/GIMT_Encode2(RegState::Define),
        GIR_Copy, /*NewInsnID*/1, /*OldInsnID*/0, /*OpIdx*/2, // vindex
        GIR_AddImm8, /*InsnID*/1, /*SubRegIndex*/3,
        GIR_Copy, /*NewInsnID*/1, /*OldInsnID*/0, /*OpIdx*/3, // voffset
        GIR_AddImm8, /*InsnID*/1, /*SubRegIndex*/11,
        GIR_ConstrainOperandRC, /*InsnID*/1, /*Op*/0, GIMT_Encode2(AMDGPU::VReg_64RegClassID),
        GIR_ConstrainOperandRC, /*InsnID*/1, /*Op*/1, GIMT_Encode2(AMDGPU::VGPR_32RegClassID),
        GIR_ConstrainOperandRC, /*InsnID*/1, /*Op*/3, GIMT_Encode2(AMDGPU::VGPR_32RegClassID),
        GIR_BuildMI, /*InsnID*/0, /*Opcode*/GIMT_Encode2(AMDGPU::BUFFER_LOAD_FORMAT_XY_BOTHEN),
        GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/0, // DstI[vdata]
        GIR_AddSimpleTempRegister, /*InsnID*/0, /*TempRegID*/0,
        GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/1, // rsrc
        GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/0, // soffset
        GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/5, // offset
        GIR_CustomOperandRenderer, /*InsnID*/0, /*OldInsnID*/0, /*OpIdx*/6, /*OperandRenderer*/GIMT_Encode2(GICR_renderExtractCPol), // auxiliary
        GIR_CustomOperandRenderer, /*InsnID*/0, /*OldInsnID*/0, /*OpIdx*/6, /*OperandRenderer*/GIMT_Encode2(GICR_renderExtractSWZ), // auxiliary
        GIR_MergeMemOperands, /*InsnID*/0, /*NumInsns*/1, /*MergeInsnID's*/0,
        GIR_ConstrainSelectedInstOperands, /*InsnID*/0,
        GIR_EraseFromParent, /*InsnID*/0,
        // GIR_Coverage, 3932,
        GIR_Done,
      // Label 6535: @479662
      GIM_Try, /*On fail goto*//*Label 6536*/ GIMT_Encode4(479769), // Rule ID 3936 //
        // MIs[0] offset
        GIM_CheckIsImm, /*MI*/0, /*Op*/5,
        // MIs[0] auxiliary
        GIM_CheckIsImm, /*MI*/0, /*Op*/6,
        // MIs[0] Operand 7
        GIM_CheckIsImm, /*MI*/0, /*Op*/7,
        GIM_CheckComplexPattern, /*MI*/0, /*Op*/4, /*Renderer*/GIMT_Encode2(0), GIMT_Encode2(GICP_gi_buf_soffset),
        // (SIbuffer_load_format:{ *:[v2f32] } v4i32:{ *:[v4i32] }:$rsrc, i32:{ *:[i32] }:$vindex, i32:{ *:[i32] }:$voffset, (BUFSOffset:{ *:[i32] } i32:{ *:[i32] }:$soffset), (timm:{ *:[i32] }):$offset, (timm:{ *:[i32] }):$auxiliary, (timm:{ *:[i1] }))  =>  (BUFFER_LOAD_FORMAT_XY_VBUFFER_BOTHEN:{ *:[v2f32] } (REG_SEQUENCE:{ *:[i64] } VReg_64:{ *:[i32] }, VGPR_32:{ *:[i32] }:$vindex, sub0:{ *:[i32] }, VGPR_32:{ *:[i32] }:$voffset, sub1:{ *:[i32] }), SReg_128:{ *:[v4i32] }:$rsrc, SCSrc_b32:{ *:[i32] }:$soffset, (timm:{ *:[i32] }):$offset, (extract_cpol:{ *:[i32] } ?:{ *:[i32] }:$auxiliary), (extract_swz:{ *:[i1] } ?:{ *:[i32] }:$auxiliary))
        GIR_MakeTempReg, /*TempRegID*/0, /*TypeID*/GILLT_s64,
        GIR_BuildMI, /*InsnID*/1, /*Opcode*/GIMT_Encode2(TargetOpcode::REG_SEQUENCE),
        GIR_AddTempRegister, /*InsnID*/1, /*TempRegID*/0, /*TempRegFlags*/GIMT_Encode2(RegState::Define),
        GIR_Copy, /*NewInsnID*/1, /*OldInsnID*/0, /*OpIdx*/2, // vindex
        GIR_AddImm8, /*InsnID*/1, /*SubRegIndex*/3,
        GIR_Copy, /*NewInsnID*/1, /*OldInsnID*/0, /*OpIdx*/3, // voffset
        GIR_AddImm8, /*InsnID*/1, /*SubRegIndex*/11,
        GIR_ConstrainOperandRC, /*InsnID*/1, /*Op*/0, GIMT_Encode2(AMDGPU::VReg_64RegClassID),
        GIR_ConstrainOperandRC, /*InsnID*/1, /*Op*/1, GIMT_Encode2(AMDGPU::VGPR_32RegClassID),
        GIR_ConstrainOperandRC, /*InsnID*/1, /*Op*/3, GIMT_Encode2(AMDGPU::VGPR_32RegClassID),
        GIR_BuildMI, /*InsnID*/0, /*Opcode*/GIMT_Encode2(AMDGPU::BUFFER_LOAD_FORMAT_XY_VBUFFER_BOTHEN),
        GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/0, // DstI[vdata]
        GIR_AddSimpleTempRegister, /*InsnID*/0, /*TempRegID*/0,
        GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/1, // rsrc
        GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/0, // soffset
        GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/5, // offset
        GIR_CustomOperandRenderer, /*InsnID*/0, /*OldInsnID*/0, /*OpIdx*/6, /*OperandRenderer*/GIMT_Encode2(GICR_renderExtractCPol), // auxiliary
        GIR_CustomOperandRenderer, /*InsnID*/0, /*OldInsnID*/0, /*OpIdx*/6, /*OperandRenderer*/GIMT_Encode2(GICR_renderExtractSWZ), // auxiliary
        GIR_MergeMemOperands, /*InsnID*/0, /*NumInsns*/1, /*MergeInsnID's*/0,
        GIR_ConstrainSelectedInstOperands, /*InsnID*/0,
        GIR_EraseFromParent, /*InsnID*/0,
        // GIR_Coverage, 3936,
        GIR_Done,
      // Label 6536: @479769
      GIM_Try, /*On fail goto*//*Label 6537*/ GIMT_Encode4(479879), // Rule ID 3940 //
        GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasUnrestrictedSOffset),
        // MIs[0] offset
        GIM_CheckIsImm, /*MI*/0, /*Op*/5,
        // MIs[0] auxiliary
        GIM_CheckIsImm, /*MI*/0, /*Op*/6,
        // MIs[0] Operand 7
        GIM_CheckIsImm, /*MI*/0, /*Op*/7,
        GIM_CheckComplexPattern, /*MI*/0, /*Op*/4, /*Renderer*/GIMT_Encode2(0), GIMT_Encode2(GICP_gi_buf_soffset),
        // (SIbuffer_load_format:{ *:[v2i32] } v4i32:{ *:[v4i32] }:$rsrc, i32:{ *:[i32] }:$vindex, i32:{ *:[i32] }:$voffset, (BUFSOffset:{ *:[i32] } i32:{ *:[i32] }:$soffset), (timm:{ *:[i32] }):$offset, (timm:{ *:[i32] }):$auxiliary, (timm:{ *:[i1] }))  =>  (BUFFER_LOAD_FORMAT_XY_BOTHEN:{ *:[v2i32] } (REG_SEQUENCE:{ *:[i64] } VReg_64:{ *:[i32] }, VGPR_32:{ *:[i32] }:$vindex, sub0:{ *:[i32] }, VGPR_32:{ *:[i32] }:$voffset, sub1:{ *:[i32] }), SReg_128:{ *:[v4i32] }:$rsrc, SCSrc_b32:{ *:[i32] }:$soffset, (timm:{ *:[i32] }):$offset, (extract_cpol:{ *:[i32] } ?:{ *:[i32] }:$auxiliary), (extract_swz:{ *:[i1] } ?:{ *:[i32] }:$auxiliary))
        GIR_MakeTempReg, /*TempRegID*/0, /*TypeID*/GILLT_s64,
        GIR_BuildMI, /*InsnID*/1, /*Opcode*/GIMT_Encode2(TargetOpcode::REG_SEQUENCE),
        GIR_AddTempRegister, /*InsnID*/1, /*TempRegID*/0, /*TempRegFlags*/GIMT_Encode2(RegState::Define),
        GIR_Copy, /*NewInsnID*/1, /*OldInsnID*/0, /*OpIdx*/2, // vindex
        GIR_AddImm8, /*InsnID*/1, /*SubRegIndex*/3,
        GIR_Copy, /*NewInsnID*/1, /*OldInsnID*/0, /*OpIdx*/3, // voffset
        GIR_AddImm8, /*InsnID*/1, /*SubRegIndex*/11,
        GIR_ConstrainOperandRC, /*InsnID*/1, /*Op*/0, GIMT_Encode2(AMDGPU::VReg_64RegClassID),
        GIR_ConstrainOperandRC, /*InsnID*/1, /*Op*/1, GIMT_Encode2(AMDGPU::VGPR_32RegClassID),
        GIR_ConstrainOperandRC, /*InsnID*/1, /*Op*/3, GIMT_Encode2(AMDGPU::VGPR_32RegClassID),
        GIR_BuildMI, /*InsnID*/0, /*Opcode*/GIMT_Encode2(AMDGPU::BUFFER_LOAD_FORMAT_XY_BOTHEN),
        GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/0, // DstI[vdata]
        GIR_AddSimpleTempRegister, /*InsnID*/0, /*TempRegID*/0,
        GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/1, // rsrc
        GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/0, // soffset
        GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/5, // offset
        GIR_CustomOperandRenderer, /*InsnID*/0, /*OldInsnID*/0, /*OpIdx*/6, /*OperandRenderer*/GIMT_Encode2(GICR_renderExtractCPol), // auxiliary
        GIR_CustomOperandRenderer, /*InsnID*/0, /*OldInsnID*/0, /*OpIdx*/6, /*OperandRenderer*/GIMT_Encode2(GICR_renderExtractSWZ), // auxiliary
        GIR_MergeMemOperands, /*InsnID*/0, /*NumInsns*/1, /*MergeInsnID's*/0,
        GIR_ConstrainSelectedInstOperands, /*InsnID*/0,
        GIR_EraseFromParent, /*InsnID*/0,
        // GIR_Coverage, 3940,
        GIR_Done,
      // Label 6537: @479879
      GIM_Try, /*On fail goto*//*Label 6538*/ GIMT_Encode4(479986), // Rule ID 3944 //
        // MIs[0] offset
        GIM_CheckIsImm, /*MI*/0, /*Op*/5,
        // MIs[0] auxiliary
        GIM_CheckIsImm, /*MI*/0, /*Op*/6,
        // MIs[0] Operand 7
        GIM_CheckIsImm, /*MI*/0, /*Op*/7,
        GIM_CheckComplexPattern, /*MI*/0, /*Op*/4, /*Renderer*/GIMT_Encode2(0), GIMT_Encode2(GICP_gi_buf_soffset),
        // (SIbuffer_load_format:{ *:[v2i32] } v4i32:{ *:[v4i32] }:$rsrc, i32:{ *:[i32] }:$vindex, i32:{ *:[i32] }:$voffset, (BUFSOffset:{ *:[i32] } i32:{ *:[i32] }:$soffset), (timm:{ *:[i32] }):$offset, (timm:{ *:[i32] }):$auxiliary, (timm:{ *:[i1] }))  =>  (BUFFER_LOAD_FORMAT_XY_VBUFFER_BOTHEN:{ *:[v2i32] } (REG_SEQUENCE:{ *:[i64] } VReg_64:{ *:[i32] }, VGPR_32:{ *:[i32] }:$vindex, sub0:{ *:[i32] }, VGPR_32:{ *:[i32] }:$voffset, sub1:{ *:[i32] }), SReg_128:{ *:[v4i32] }:$rsrc, SCSrc_b32:{ *:[i32] }:$soffset, (timm:{ *:[i32] }):$offset, (extract_cpol:{ *:[i32] } ?:{ *:[i32] }:$auxiliary), (extract_swz:{ *:[i1] } ?:{ *:[i32] }:$auxiliary))
        GIR_MakeTempReg, /*TempRegID*/0, /*TypeID*/GILLT_s64,
        GIR_BuildMI, /*InsnID*/1, /*Opcode*/GIMT_Encode2(TargetOpcode::REG_SEQUENCE),
        GIR_AddTempRegister, /*InsnID*/1, /*TempRegID*/0, /*TempRegFlags*/GIMT_Encode2(RegState::Define),
        GIR_Copy, /*NewInsnID*/1, /*OldInsnID*/0, /*OpIdx*/2, // vindex
        GIR_AddImm8, /*InsnID*/1, /*SubRegIndex*/3,
        GIR_Copy, /*NewInsnID*/1, /*OldInsnID*/0, /*OpIdx*/3, // voffset
        GIR_AddImm8, /*InsnID*/1, /*SubRegIndex*/11,
        GIR_ConstrainOperandRC, /*InsnID*/1, /*Op*/0, GIMT_Encode2(AMDGPU::VReg_64RegClassID),
        GIR_ConstrainOperandRC, /*InsnID*/1, /*Op*/1, GIMT_Encode2(AMDGPU::VGPR_32RegClassID),
        GIR_ConstrainOperandRC, /*InsnID*/1, /*Op*/3, GIMT_Encode2(AMDGPU::VGPR_32RegClassID),
        GIR_BuildMI, /*InsnID*/0, /*Opcode*/GIMT_Encode2(AMDGPU::BUFFER_LOAD_FORMAT_XY_VBUFFER_BOTHEN),
        GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/0, // DstI[vdata]
        GIR_AddSimpleTempRegister, /*InsnID*/0, /*TempRegID*/0,
        GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/1, // rsrc
        GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/0, // soffset
        GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/5, // offset
        GIR_CustomOperandRenderer, /*InsnID*/0, /*OldInsnID*/0, /*OpIdx*/6, /*OperandRenderer*/GIMT_Encode2(GICR_renderExtractCPol), // auxiliary
        GIR_CustomOperandRenderer, /*InsnID*/0, /*OldInsnID*/0, /*OpIdx*/6, /*OperandRenderer*/GIMT_Encode2(GICR_renderExtractSWZ), // auxiliary
        GIR_MergeMemOperands, /*InsnID*/0, /*NumInsns*/1, /*MergeInsnID's*/0,
        GIR_ConstrainSelectedInstOperands, /*InsnID*/0,
        GIR_EraseFromParent, /*InsnID*/0,
        // GIR_Coverage, 3944,
        GIR_Done,
      // Label 6538: @479986
      GIM_Reject,
    // Label 6522: @479987
    GIM_Reject,
    // Label 6502: @479988
    GIM_Try, /*On fail goto*//*Label 6539*/ GIMT_Encode4(481383),
      GIM_CheckType, /*MI*/0, /*Op*/1, /*Type*/GILLT_v4s32,
      GIM_CheckType, /*MI*/0, /*Op*/2, /*Type*/GILLT_s32,
      GIM_CheckType, /*MI*/0, /*Op*/3, /*Type*/GILLT_s32,
      GIM_CheckType, /*MI*/0, /*Op*/4, /*Type*/GILLT_s32,
      GIM_CheckRegBankForClass, /*MI*/0, /*Op*/0, /*RC*/GIMT_Encode2(AMDGPU::AV_96RegClassID),
      GIM_Try, /*On fail goto*//*Label 6540*/ GIMT_Encode4(480096), // Rule ID 3945 //
        GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasUnrestrictedSOffset),
        GIM_CheckConstantInt8, /*MI*/0, /*Op*/2, 0,
        GIM_CheckConstantInt8, /*MI*/0, /*Op*/3, 0,
        // MIs[0] offset
        GIM_CheckIsImm, /*MI*/0, /*Op*/5,
        // MIs[0] auxiliary
        GIM_CheckIsImm, /*MI*/0, /*Op*/6,
        // MIs[0] Operand 7
        GIM_CheckLiteralInt, /*MI*/0, /*Op*/7, GIMT_Encode8(0),
        GIM_CheckComplexPattern, /*MI*/0, /*Op*/4, /*Renderer*/GIMT_Encode2(0), GIMT_Encode2(GICP_gi_buf_soffset),
        // (SIbuffer_load_format:{ *:[v3f32] } v4i32:{ *:[v4i32] }:$rsrc, 0:{ *:[i32] }, 0:{ *:[i32] }, (BUFSOffset:{ *:[i32] } i32:{ *:[i32] }:$soffset), (timm:{ *:[i32] }):$offset, (timm:{ *:[i32] }):$auxiliary, 0:{ *:[i1] })  =>  (BUFFER_LOAD_FORMAT_XYZ_OFFSET:{ *:[v3f32] } SReg_128:{ *:[v4i32] }:$rsrc, SCSrc_b32:{ *:[i32] }:$soffset, (timm:{ *:[i32] }):$offset, (extract_cpol:{ *:[i32] } ?:{ *:[i32] }:$auxiliary), (extract_swz:{ *:[i1] } ?:{ *:[i32] }:$auxiliary))
        GIR_BuildMI, /*InsnID*/0, /*Opcode*/GIMT_Encode2(AMDGPU::BUFFER_LOAD_FORMAT_XYZ_OFFSET),
        GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/0, // DstI[vdata]
        GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/1, // rsrc
        GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/0, // soffset
        GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/5, // offset
        GIR_CustomOperandRenderer, /*InsnID*/0, /*OldInsnID*/0, /*OpIdx*/6, /*OperandRenderer*/GIMT_Encode2(GICR_renderExtractCPol), // auxiliary
        GIR_CustomOperandRenderer, /*InsnID*/0, /*OldInsnID*/0, /*OpIdx*/6, /*OperandRenderer*/GIMT_Encode2(GICR_renderExtractSWZ), // auxiliary
        GIR_MergeMemOperands, /*InsnID*/0, /*NumInsns*/1, /*MergeInsnID's*/0,
        GIR_ConstrainSelectedInstOperands, /*InsnID*/0,
        GIR_EraseFromParent, /*InsnID*/0,
        // GIR_Coverage, 3945,
        GIR_Done,
      // Label 6540: @480096
      GIM_Try, /*On fail goto*//*Label 6541*/ GIMT_Encode4(480175), // Rule ID 3949 //
        GIM_CheckConstantInt8, /*MI*/0, /*Op*/2, 0,
        GIM_CheckConstantInt8, /*MI*/0, /*Op*/3, 0,
        // MIs[0] offset
        GIM_CheckIsImm, /*MI*/0, /*Op*/5,
        // MIs[0] auxiliary
        GIM_CheckIsImm, /*MI*/0, /*Op*/6,
        // MIs[0] Operand 7
        GIM_CheckLiteralInt, /*MI*/0, /*Op*/7, GIMT_Encode8(0),
        GIM_CheckComplexPattern, /*MI*/0, /*Op*/4, /*Renderer*/GIMT_Encode2(0), GIMT_Encode2(GICP_gi_buf_soffset),
        // (SIbuffer_load_format:{ *:[v3f32] } v4i32:{ *:[v4i32] }:$rsrc, 0:{ *:[i32] }, 0:{ *:[i32] }, (BUFSOffset:{ *:[i32] } i32:{ *:[i32] }:$soffset), (timm:{ *:[i32] }):$offset, (timm:{ *:[i32] }):$auxiliary, 0:{ *:[i1] })  =>  (BUFFER_LOAD_FORMAT_XYZ_VBUFFER_OFFSET:{ *:[v3f32] } SReg_128:{ *:[v4i32] }:$rsrc, SCSrc_b32:{ *:[i32] }:$soffset, (timm:{ *:[i32] }):$offset, (extract_cpol:{ *:[i32] } ?:{ *:[i32] }:$auxiliary), (extract_swz:{ *:[i1] } ?:{ *:[i32] }:$auxiliary))
        GIR_BuildMI, /*InsnID*/0, /*Opcode*/GIMT_Encode2(AMDGPU::BUFFER_LOAD_FORMAT_XYZ_VBUFFER_OFFSET),
        GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/0, // DstI[vdata]
        GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/1, // rsrc
        GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/0, // soffset
        GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/5, // offset
        GIR_CustomOperandRenderer, /*InsnID*/0, /*OldInsnID*/0, /*OpIdx*/6, /*OperandRenderer*/GIMT_Encode2(GICR_renderExtractCPol), // auxiliary
        GIR_CustomOperandRenderer, /*InsnID*/0, /*OldInsnID*/0, /*OpIdx*/6, /*OperandRenderer*/GIMT_Encode2(GICR_renderExtractSWZ), // auxiliary
        GIR_MergeMemOperands, /*InsnID*/0, /*NumInsns*/1, /*MergeInsnID's*/0,
        GIR_ConstrainSelectedInstOperands, /*InsnID*/0,
        GIR_EraseFromParent, /*InsnID*/0,
        // GIR_Coverage, 3949,
        GIR_Done,
      // Label 6541: @480175
      GIM_Try, /*On fail goto*//*Label 6542*/ GIMT_Encode4(480257), // Rule ID 3953 //
        GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasUnrestrictedSOffset),
        GIM_CheckConstantInt8, /*MI*/0, /*Op*/2, 0,
        GIM_CheckConstantInt8, /*MI*/0, /*Op*/3, 0,
        // MIs[0] offset
        GIM_CheckIsImm, /*MI*/0, /*Op*/5,
        // MIs[0] auxiliary
        GIM_CheckIsImm, /*MI*/0, /*Op*/6,
        // MIs[0] Operand 7
        GIM_CheckLiteralInt, /*MI*/0, /*Op*/7, GIMT_Encode8(0),
        GIM_CheckComplexPattern, /*MI*/0, /*Op*/4, /*Renderer*/GIMT_Encode2(0), GIMT_Encode2(GICP_gi_buf_soffset),
        // (SIbuffer_load_format:{ *:[v3i32] } v4i32:{ *:[v4i32] }:$rsrc, 0:{ *:[i32] }, 0:{ *:[i32] }, (BUFSOffset:{ *:[i32] } i32:{ *:[i32] }:$soffset), (timm:{ *:[i32] }):$offset, (timm:{ *:[i32] }):$auxiliary, 0:{ *:[i1] })  =>  (BUFFER_LOAD_FORMAT_XYZ_OFFSET:{ *:[v3i32] } SReg_128:{ *:[v4i32] }:$rsrc, SCSrc_b32:{ *:[i32] }:$soffset, (timm:{ *:[i32] }):$offset, (extract_cpol:{ *:[i32] } ?:{ *:[i32] }:$auxiliary), (extract_swz:{ *:[i1] } ?:{ *:[i32] }:$auxiliary))
        GIR_BuildMI, /*InsnID*/0, /*Opcode*/GIMT_Encode2(AMDGPU::BUFFER_LOAD_FORMAT_XYZ_OFFSET),
        GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/0, // DstI[vdata]
        GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/1, // rsrc
        GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/0, // soffset
        GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/5, // offset
        GIR_CustomOperandRenderer, /*InsnID*/0, /*OldInsnID*/0, /*OpIdx*/6, /*OperandRenderer*/GIMT_Encode2(GICR_renderExtractCPol), // auxiliary
        GIR_CustomOperandRenderer, /*InsnID*/0, /*OldInsnID*/0, /*OpIdx*/6, /*OperandRenderer*/GIMT_Encode2(GICR_renderExtractSWZ), // auxiliary
        GIR_MergeMemOperands, /*InsnID*/0, /*NumInsns*/1, /*MergeInsnID's*/0,
        GIR_ConstrainSelectedInstOperands, /*InsnID*/0,
        GIR_EraseFromParent, /*InsnID*/0,
        // GIR_Coverage, 3953,
        GIR_Done,
      // Label 6542: @480257
      GIM_Try, /*On fail goto*//*Label 6543*/ GIMT_Encode4(480336), // Rule ID 3957 //
        GIM_CheckConstantInt8, /*MI*/0, /*Op*/2, 0,
        GIM_CheckConstantInt8, /*MI*/0, /*Op*/3, 0,
        // MIs[0] offset
        GIM_CheckIsImm, /*MI*/0, /*Op*/5,
        // MIs[0] auxiliary
        GIM_CheckIsImm, /*MI*/0, /*Op*/6,
        // MIs[0] Operand 7
        GIM_CheckLiteralInt, /*MI*/0, /*Op*/7, GIMT_Encode8(0),
        GIM_CheckComplexPattern, /*MI*/0, /*Op*/4, /*Renderer*/GIMT_Encode2(0), GIMT_Encode2(GICP_gi_buf_soffset),
        // (SIbuffer_load_format:{ *:[v3i32] } v4i32:{ *:[v4i32] }:$rsrc, 0:{ *:[i32] }, 0:{ *:[i32] }, (BUFSOffset:{ *:[i32] } i32:{ *:[i32] }:$soffset), (timm:{ *:[i32] }):$offset, (timm:{ *:[i32] }):$auxiliary, 0:{ *:[i1] })  =>  (BUFFER_LOAD_FORMAT_XYZ_VBUFFER_OFFSET:{ *:[v3i32] } SReg_128:{ *:[v4i32] }:$rsrc, SCSrc_b32:{ *:[i32] }:$soffset, (timm:{ *:[i32] }):$offset, (extract_cpol:{ *:[i32] } ?:{ *:[i32] }:$auxiliary), (extract_swz:{ *:[i1] } ?:{ *:[i32] }:$auxiliary))
        GIR_BuildMI, /*InsnID*/0, /*Opcode*/GIMT_Encode2(AMDGPU::BUFFER_LOAD_FORMAT_XYZ_VBUFFER_OFFSET),
        GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/0, // DstI[vdata]
        GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/1, // rsrc
        GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/0, // soffset
        GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/5, // offset
        GIR_CustomOperandRenderer, /*InsnID*/0, /*OldInsnID*/0, /*OpIdx*/6, /*OperandRenderer*/GIMT_Encode2(GICR_renderExtractCPol), // auxiliary
        GIR_CustomOperandRenderer, /*InsnID*/0, /*OldInsnID*/0, /*OpIdx*/6, /*OperandRenderer*/GIMT_Encode2(GICR_renderExtractSWZ), // auxiliary
        GIR_MergeMemOperands, /*InsnID*/0, /*NumInsns*/1, /*MergeInsnID's*/0,
        GIR_ConstrainSelectedInstOperands, /*InsnID*/0,
        GIR_EraseFromParent, /*InsnID*/0,
        // GIR_Coverage, 3957,
        GIR_Done,
      // Label 6543: @480336
      GIM_Try, /*On fail goto*//*Label 6544*/ GIMT_Encode4(480418), // Rule ID 3946 //
        GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasUnrestrictedSOffset),
        GIM_CheckConstantInt8, /*MI*/0, /*Op*/2, 0,
        // MIs[0] offset
        GIM_CheckIsImm, /*MI*/0, /*Op*/5,
        // MIs[0] auxiliary
        GIM_CheckIsImm, /*MI*/0, /*Op*/6,
        // MIs[0] Operand 7
        GIM_CheckLiteralInt, /*MI*/0, /*Op*/7, GIMT_Encode8(0),
        GIM_CheckComplexPattern, /*MI*/0, /*Op*/4, /*Renderer*/GIMT_Encode2(0), GIMT_Encode2(GICP_gi_buf_soffset),
        // (SIbuffer_load_format:{ *:[v3f32] } v4i32:{ *:[v4i32] }:$rsrc, 0:{ *:[i32] }, i32:{ *:[i32] }:$voffset, (BUFSOffset:{ *:[i32] } i32:{ *:[i32] }:$soffset), (timm:{ *:[i32] }):$offset, (timm:{ *:[i32] }):$auxiliary, 0:{ *:[i1] })  =>  (BUFFER_LOAD_FORMAT_XYZ_OFFEN:{ *:[v3f32] } VGPR_32:{ *:[i32] }:$voffset, SReg_128:{ *:[v4i32] }:$rsrc, SCSrc_b32:{ *:[i32] }:$soffset, (timm:{ *:[i32] }):$offset, (extract_cpol:{ *:[i32] } ?:{ *:[i32] }:$auxiliary), (extract_swz:{ *:[i1] } ?:{ *:[i32] }:$auxiliary))
        GIR_BuildMI, /*InsnID*/0, /*Opcode*/GIMT_Encode2(AMDGPU::BUFFER_LOAD_FORMAT_XYZ_OFFEN),
        GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/0, // DstI[vdata]
        GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/3, // voffset
        GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/1, // rsrc
        GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/0, // soffset
        GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/5, // offset
        GIR_CustomOperandRenderer, /*InsnID*/0, /*OldInsnID*/0, /*OpIdx*/6, /*OperandRenderer*/GIMT_Encode2(GICR_renderExtractCPol), // auxiliary
        GIR_CustomOperandRenderer, /*InsnID*/0, /*OldInsnID*/0, /*OpIdx*/6, /*OperandRenderer*/GIMT_Encode2(GICR_renderExtractSWZ), // auxiliary
        GIR_MergeMemOperands, /*InsnID*/0, /*NumInsns*/1, /*MergeInsnID's*/0,
        GIR_ConstrainSelectedInstOperands, /*InsnID*/0,
        GIR_EraseFromParent, /*InsnID*/0,
        // GIR_Coverage, 3946,
        GIR_Done,
      // Label 6544: @480418
      GIM_Try, /*On fail goto*//*Label 6545*/ GIMT_Encode4(480497), // Rule ID 3950 //
        GIM_CheckConstantInt8, /*MI*/0, /*Op*/2, 0,
        // MIs[0] offset
        GIM_CheckIsImm, /*MI*/0, /*Op*/5,
        // MIs[0] auxiliary
        GIM_CheckIsImm, /*MI*/0, /*Op*/6,
        // MIs[0] Operand 7
        GIM_CheckLiteralInt, /*MI*/0, /*Op*/7, GIMT_Encode8(0),
        GIM_CheckComplexPattern, /*MI*/0, /*Op*/4, /*Renderer*/GIMT_Encode2(0), GIMT_Encode2(GICP_gi_buf_soffset),
        // (SIbuffer_load_format:{ *:[v3f32] } v4i32:{ *:[v4i32] }:$rsrc, 0:{ *:[i32] }, i32:{ *:[i32] }:$voffset, (BUFSOffset:{ *:[i32] } i32:{ *:[i32] }:$soffset), (timm:{ *:[i32] }):$offset, (timm:{ *:[i32] }):$auxiliary, 0:{ *:[i1] })  =>  (BUFFER_LOAD_FORMAT_XYZ_VBUFFER_OFFEN:{ *:[v3f32] } VGPR_32:{ *:[i32] }:$voffset, SReg_128:{ *:[v4i32] }:$rsrc, SCSrc_b32:{ *:[i32] }:$soffset, (timm:{ *:[i32] }):$offset, (extract_cpol:{ *:[i32] } ?:{ *:[i32] }:$auxiliary), (extract_swz:{ *:[i1] } ?:{ *:[i32] }:$auxiliary))
        GIR_BuildMI, /*InsnID*/0, /*Opcode*/GIMT_Encode2(AMDGPU::BUFFER_LOAD_FORMAT_XYZ_VBUFFER_OFFEN),
        GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/0, // DstI[vdata]
        GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/3, // voffset
        GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/1, // rsrc
        GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/0, // soffset
        GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/5, // offset
        GIR_CustomOperandRenderer, /*InsnID*/0, /*OldInsnID*/0, /*OpIdx*/6, /*OperandRenderer*/GIMT_Encode2(GICR_renderExtractCPol), // auxiliary
        GIR_CustomOperandRenderer, /*InsnID*/0, /*OldInsnID*/0, /*OpIdx*/6, /*OperandRenderer*/GIMT_Encode2(GICR_renderExtractSWZ), // auxiliary
        GIR_MergeMemOperands, /*InsnID*/0, /*NumInsns*/1, /*MergeInsnID's*/0,
        GIR_ConstrainSelectedInstOperands, /*InsnID*/0,
        GIR_EraseFromParent, /*InsnID*/0,
        // GIR_Coverage, 3950,
        GIR_Done,
      // Label 6545: @480497
      GIM_Try, /*On fail goto*//*Label 6546*/ GIMT_Encode4(480579), // Rule ID 3954 //
        GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasUnrestrictedSOffset),
        GIM_CheckConstantInt8, /*MI*/0, /*Op*/2, 0,
        // MIs[0] offset
        GIM_CheckIsImm, /*MI*/0, /*Op*/5,
        // MIs[0] auxiliary
        GIM_CheckIsImm, /*MI*/0, /*Op*/6,
        // MIs[0] Operand 7
        GIM_CheckLiteralInt, /*MI*/0, /*Op*/7, GIMT_Encode8(0),
        GIM_CheckComplexPattern, /*MI*/0, /*Op*/4, /*Renderer*/GIMT_Encode2(0), GIMT_Encode2(GICP_gi_buf_soffset),
        // (SIbuffer_load_format:{ *:[v3i32] } v4i32:{ *:[v4i32] }:$rsrc, 0:{ *:[i32] }, i32:{ *:[i32] }:$voffset, (BUFSOffset:{ *:[i32] } i32:{ *:[i32] }:$soffset), (timm:{ *:[i32] }):$offset, (timm:{ *:[i32] }):$auxiliary, 0:{ *:[i1] })  =>  (BUFFER_LOAD_FORMAT_XYZ_OFFEN:{ *:[v3i32] } VGPR_32:{ *:[i32] }:$voffset, SReg_128:{ *:[v4i32] }:$rsrc, SCSrc_b32:{ *:[i32] }:$soffset, (timm:{ *:[i32] }):$offset, (extract_cpol:{ *:[i32] } ?:{ *:[i32] }:$auxiliary), (extract_swz:{ *:[i1] } ?:{ *:[i32] }:$auxiliary))
        GIR_BuildMI, /*InsnID*/0, /*Opcode*/GIMT_Encode2(AMDGPU::BUFFER_LOAD_FORMAT_XYZ_OFFEN),
        GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/0, // DstI[vdata]
        GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/3, // voffset
        GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/1, // rsrc
        GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/0, // soffset
        GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/5, // offset
        GIR_CustomOperandRenderer, /*InsnID*/0, /*OldInsnID*/0, /*OpIdx*/6, /*OperandRenderer*/GIMT_Encode2(GICR_renderExtractCPol), // auxiliary
        GIR_CustomOperandRenderer, /*InsnID*/0, /*OldInsnID*/0, /*OpIdx*/6, /*OperandRenderer*/GIMT_Encode2(GICR_renderExtractSWZ), // auxiliary
        GIR_MergeMemOperands, /*InsnID*/0, /*NumInsns*/1, /*MergeInsnID's*/0,
        GIR_ConstrainSelectedInstOperands, /*InsnID*/0,
        GIR_EraseFromParent, /*InsnID*/0,
        // GIR_Coverage, 3954,
        GIR_Done,
      // Label 6546: @480579
      GIM_Try, /*On fail goto*//*Label 6547*/ GIMT_Encode4(480658), // Rule ID 3958 //
        GIM_CheckConstantInt8, /*MI*/0, /*Op*/2, 0,
        // MIs[0] offset
        GIM_CheckIsImm, /*MI*/0, /*Op*/5,
        // MIs[0] auxiliary
        GIM_CheckIsImm, /*MI*/0, /*Op*/6,
        // MIs[0] Operand 7
        GIM_CheckLiteralInt, /*MI*/0, /*Op*/7, GIMT_Encode8(0),
        GIM_CheckComplexPattern, /*MI*/0, /*Op*/4, /*Renderer*/GIMT_Encode2(0), GIMT_Encode2(GICP_gi_buf_soffset),
        // (SIbuffer_load_format:{ *:[v3i32] } v4i32:{ *:[v4i32] }:$rsrc, 0:{ *:[i32] }, i32:{ *:[i32] }:$voffset, (BUFSOffset:{ *:[i32] } i32:{ *:[i32] }:$soffset), (timm:{ *:[i32] }):$offset, (timm:{ *:[i32] }):$auxiliary, 0:{ *:[i1] })  =>  (BUFFER_LOAD_FORMAT_XYZ_VBUFFER_OFFEN:{ *:[v3i32] } VGPR_32:{ *:[i32] }:$voffset, SReg_128:{ *:[v4i32] }:$rsrc, SCSrc_b32:{ *:[i32] }:$soffset, (timm:{ *:[i32] }):$offset, (extract_cpol:{ *:[i32] } ?:{ *:[i32] }:$auxiliary), (extract_swz:{ *:[i1] } ?:{ *:[i32] }:$auxiliary))
        GIR_BuildMI, /*InsnID*/0, /*Opcode*/GIMT_Encode2(AMDGPU::BUFFER_LOAD_FORMAT_XYZ_VBUFFER_OFFEN),
        GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/0, // DstI[vdata]
        GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/3, // voffset
        GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/1, // rsrc
        GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/0, // soffset
        GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/5, // offset
        GIR_CustomOperandRenderer, /*InsnID*/0, /*OldInsnID*/0, /*OpIdx*/6, /*OperandRenderer*/GIMT_Encode2(GICR_renderExtractCPol), // auxiliary
        GIR_CustomOperandRenderer, /*InsnID*/0, /*OldInsnID*/0, /*OpIdx*/6, /*OperandRenderer*/GIMT_Encode2(GICR_renderExtractSWZ), // auxiliary
        GIR_MergeMemOperands, /*InsnID*/0, /*NumInsns*/1, /*MergeInsnID's*/0,
        GIR_ConstrainSelectedInstOperands, /*InsnID*/0,
        GIR_EraseFromParent, /*InsnID*/0,
        // GIR_Coverage, 3958,
        GIR_Done,
      // Label 6547: @480658
      GIM_Try, /*On fail goto*//*Label 6548*/ GIMT_Encode4(480732), // Rule ID 3947 //
        GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasUnrestrictedSOffset),
        GIM_CheckConstantInt8, /*MI*/0, /*Op*/3, 0,
        // MIs[0] offset
        GIM_CheckIsImm, /*MI*/0, /*Op*/5,
        // MIs[0] auxiliary
        GIM_CheckIsImm, /*MI*/0, /*Op*/6,
        // MIs[0] Operand 7
        GIM_CheckIsImm, /*MI*/0, /*Op*/7,
        GIM_CheckComplexPattern, /*MI*/0, /*Op*/4, /*Renderer*/GIMT_Encode2(0), GIMT_Encode2(GICP_gi_buf_soffset),
        // (SIbuffer_load_format:{ *:[v3f32] } v4i32:{ *:[v4i32] }:$rsrc, i32:{ *:[i32] }:$vindex, 0:{ *:[i32] }, (BUFSOffset:{ *:[i32] } i32:{ *:[i32] }:$soffset), (timm:{ *:[i32] }):$offset, (timm:{ *:[i32] }):$auxiliary, (timm:{ *:[i1] }))  =>  (BUFFER_LOAD_FORMAT_XYZ_IDXEN:{ *:[v3f32] } VGPR_32:{ *:[i32] }:$vindex, SReg_128:{ *:[v4i32] }:$rsrc, SCSrc_b32:{ *:[i32] }:$soffset, (timm:{ *:[i32] }):$offset, (extract_cpol:{ *:[i32] } ?:{ *:[i32] }:$auxiliary), (extract_swz:{ *:[i1] } ?:{ *:[i32] }:$auxiliary))
        GIR_BuildMI, /*InsnID*/0, /*Opcode*/GIMT_Encode2(AMDGPU::BUFFER_LOAD_FORMAT_XYZ_IDXEN),
        GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/0, // DstI[vdata]
        GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/2, // vindex
        GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/1, // rsrc
        GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/0, // soffset
        GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/5, // offset
        GIR_CustomOperandRenderer, /*InsnID*/0, /*OldInsnID*/0, /*OpIdx*/6, /*OperandRenderer*/GIMT_Encode2(GICR_renderExtractCPol), // auxiliary
        GIR_CustomOperandRenderer, /*InsnID*/0, /*OldInsnID*/0, /*OpIdx*/6, /*OperandRenderer*/GIMT_Encode2(GICR_renderExtractSWZ), // auxiliary
        GIR_MergeMemOperands, /*InsnID*/0, /*NumInsns*/1, /*MergeInsnID's*/0,
        GIR_ConstrainSelectedInstOperands, /*InsnID*/0,
        GIR_EraseFromParent, /*InsnID*/0,
        // GIR_Coverage, 3947,
        GIR_Done,
      // Label 6548: @480732
      GIM_Try, /*On fail goto*//*Label 6549*/ GIMT_Encode4(480803), // Rule ID 3951 //
        GIM_CheckConstantInt8, /*MI*/0, /*Op*/3, 0,
        // MIs[0] offset
        GIM_CheckIsImm, /*MI*/0, /*Op*/5,
        // MIs[0] auxiliary
        GIM_CheckIsImm, /*MI*/0, /*Op*/6,
        // MIs[0] Operand 7
        GIM_CheckIsImm, /*MI*/0, /*Op*/7,
        GIM_CheckComplexPattern, /*MI*/0, /*Op*/4, /*Renderer*/GIMT_Encode2(0), GIMT_Encode2(GICP_gi_buf_soffset),
        // (SIbuffer_load_format:{ *:[v3f32] } v4i32:{ *:[v4i32] }:$rsrc, i32:{ *:[i32] }:$vindex, 0:{ *:[i32] }, (BUFSOffset:{ *:[i32] } i32:{ *:[i32] }:$soffset), (timm:{ *:[i32] }):$offset, (timm:{ *:[i32] }):$auxiliary, (timm:{ *:[i1] }))  =>  (BUFFER_LOAD_FORMAT_XYZ_VBUFFER_IDXEN:{ *:[v3f32] } VGPR_32:{ *:[i32] }:$vindex, SReg_128:{ *:[v4i32] }:$rsrc, SCSrc_b32:{ *:[i32] }:$soffset, (timm:{ *:[i32] }):$offset, (extract_cpol:{ *:[i32] } ?:{ *:[i32] }:$auxiliary), (extract_swz:{ *:[i1] } ?:{ *:[i32] }:$auxiliary))
        GIR_BuildMI, /*InsnID*/0, /*Opcode*/GIMT_Encode2(AMDGPU::BUFFER_LOAD_FORMAT_XYZ_VBUFFER_IDXEN),
        GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/0, // DstI[vdata]
        GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/2, // vindex
        GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/1, // rsrc
        GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/0, // soffset
        GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/5, // offset
        GIR_CustomOperandRenderer, /*InsnID*/0, /*OldInsnID*/0, /*OpIdx*/6, /*OperandRenderer*/GIMT_Encode2(GICR_renderExtractCPol), // auxiliary
        GIR_CustomOperandRenderer, /*InsnID*/0, /*OldInsnID*/0, /*OpIdx*/6, /*OperandRenderer*/GIMT_Encode2(GICR_renderExtractSWZ), // auxiliary
        GIR_MergeMemOperands, /*InsnID*/0, /*NumInsns*/1, /*MergeInsnID's*/0,
        GIR_ConstrainSelectedInstOperands, /*InsnID*/0,
        GIR_EraseFromParent, /*InsnID*/0,
        // GIR_Coverage, 3951,
        GIR_Done,
      // Label 6549: @480803
      GIM_Try, /*On fail goto*//*Label 6550*/ GIMT_Encode4(480877), // Rule ID 3955 //
        GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasUnrestrictedSOffset),
        GIM_CheckConstantInt8, /*MI*/0, /*Op*/3, 0,
        // MIs[0] offset
        GIM_CheckIsImm, /*MI*/0, /*Op*/5,
        // MIs[0] auxiliary
        GIM_CheckIsImm, /*MI*/0, /*Op*/6,
        // MIs[0] Operand 7
        GIM_CheckIsImm, /*MI*/0, /*Op*/7,
        GIM_CheckComplexPattern, /*MI*/0, /*Op*/4, /*Renderer*/GIMT_Encode2(0), GIMT_Encode2(GICP_gi_buf_soffset),
        // (SIbuffer_load_format:{ *:[v3i32] } v4i32:{ *:[v4i32] }:$rsrc, i32:{ *:[i32] }:$vindex, 0:{ *:[i32] }, (BUFSOffset:{ *:[i32] } i32:{ *:[i32] }:$soffset), (timm:{ *:[i32] }):$offset, (timm:{ *:[i32] }):$auxiliary, (timm:{ *:[i1] }))  =>  (BUFFER_LOAD_FORMAT_XYZ_IDXEN:{ *:[v3i32] } VGPR_32:{ *:[i32] }:$vindex, SReg_128:{ *:[v4i32] }:$rsrc, SCSrc_b32:{ *:[i32] }:$soffset, (timm:{ *:[i32] }):$offset, (extract_cpol:{ *:[i32] } ?:{ *:[i32] }:$auxiliary), (extract_swz:{ *:[i1] } ?:{ *:[i32] }:$auxiliary))
        GIR_BuildMI, /*InsnID*/0, /*Opcode*/GIMT_Encode2(AMDGPU::BUFFER_LOAD_FORMAT_XYZ_IDXEN),
        GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/0, // DstI[vdata]
        GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/2, // vindex
        GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/1, // rsrc
        GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/0, // soffset
        GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/5, // offset
        GIR_CustomOperandRenderer, /*InsnID*/0, /*OldInsnID*/0, /*OpIdx*/6, /*OperandRenderer*/GIMT_Encode2(GICR_renderExtractCPol), // auxiliary
        GIR_CustomOperandRenderer, /*InsnID*/0, /*OldInsnID*/0, /*OpIdx*/6, /*OperandRenderer*/GIMT_Encode2(GICR_renderExtractSWZ), // auxiliary
        GIR_MergeMemOperands, /*InsnID*/0, /*NumInsns*/1, /*MergeInsnID's*/0,
        GIR_ConstrainSelectedInstOperands, /*InsnID*/0,
        GIR_EraseFromParent, /*InsnID*/0,
        // GIR_Coverage, 3955,
        GIR_Done,
      // Label 6550: @480877
      GIM_Try, /*On fail goto*//*Label 6551*/ GIMT_Encode4(480948), // Rule ID 3959 //
        GIM_CheckConstantInt8, /*MI*/0, /*Op*/3, 0,
        // MIs[0] offset
        GIM_CheckIsImm, /*MI*/0, /*Op*/5,
        // MIs[0] auxiliary
        GIM_CheckIsImm, /*MI*/0, /*Op*/6,
        // MIs[0] Operand 7
        GIM_CheckIsImm, /*MI*/0, /*Op*/7,
        GIM_CheckComplexPattern, /*MI*/0, /*Op*/4, /*Renderer*/GIMT_Encode2(0), GIMT_Encode2(GICP_gi_buf_soffset),
        // (SIbuffer_load_format:{ *:[v3i32] } v4i32:{ *:[v4i32] }:$rsrc, i32:{ *:[i32] }:$vindex, 0:{ *:[i32] }, (BUFSOffset:{ *:[i32] } i32:{ *:[i32] }:$soffset), (timm:{ *:[i32] }):$offset, (timm:{ *:[i32] }):$auxiliary, (timm:{ *:[i1] }))  =>  (BUFFER_LOAD_FORMAT_XYZ_VBUFFER_IDXEN:{ *:[v3i32] } VGPR_32:{ *:[i32] }:$vindex, SReg_128:{ *:[v4i32] }:$rsrc, SCSrc_b32:{ *:[i32] }:$soffset, (timm:{ *:[i32] }):$offset, (extract_cpol:{ *:[i32] } ?:{ *:[i32] }:$auxiliary), (extract_swz:{ *:[i1] } ?:{ *:[i32] }:$auxiliary))
        GIR_BuildMI, /*InsnID*/0, /*Opcode*/GIMT_Encode2(AMDGPU::BUFFER_LOAD_FORMAT_XYZ_VBUFFER_IDXEN),
        GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/0, // DstI[vdata]
        GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/2, // vindex
        GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/1, // rsrc
        GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/0, // soffset
        GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/5, // offset
        GIR_CustomOperandRenderer, /*InsnID*/0, /*OldInsnID*/0, /*OpIdx*/6, /*OperandRenderer*/GIMT_Encode2(GICR_renderExtractCPol), // auxiliary
        GIR_CustomOperandRenderer, /*InsnID*/0, /*OldInsnID*/0, /*OpIdx*/6, /*OperandRenderer*/GIMT_Encode2(GICR_renderExtractSWZ), // auxiliary
        GIR_MergeMemOperands, /*InsnID*/0, /*NumInsns*/1, /*MergeInsnID's*/0,
        GIR_ConstrainSelectedInstOperands, /*InsnID*/0,
        GIR_EraseFromParent, /*InsnID*/0,
        // GIR_Coverage, 3959,
        GIR_Done,
      // Label 6551: @480948
      GIM_Try, /*On fail goto*//*Label 6552*/ GIMT_Encode4(481058), // Rule ID 3948 //
        GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasUnrestrictedSOffset),
        // MIs[0] offset
        GIM_CheckIsImm, /*MI*/0, /*Op*/5,
        // MIs[0] auxiliary
        GIM_CheckIsImm, /*MI*/0, /*Op*/6,
        // MIs[0] Operand 7
        GIM_CheckIsImm, /*MI*/0, /*Op*/7,
        GIM_CheckComplexPattern, /*MI*/0, /*Op*/4, /*Renderer*/GIMT_Encode2(0), GIMT_Encode2(GICP_gi_buf_soffset),
        // (SIbuffer_load_format:{ *:[v3f32] } v4i32:{ *:[v4i32] }:$rsrc, i32:{ *:[i32] }:$vindex, i32:{ *:[i32] }:$voffset, (BUFSOffset:{ *:[i32] } i32:{ *:[i32] }:$soffset), (timm:{ *:[i32] }):$offset, (timm:{ *:[i32] }):$auxiliary, (timm:{ *:[i1] }))  =>  (BUFFER_LOAD_FORMAT_XYZ_BOTHEN:{ *:[v3f32] } (REG_SEQUENCE:{ *:[i64] } VReg_64:{ *:[i32] }, VGPR_32:{ *:[i32] }:$vindex, sub0:{ *:[i32] }, VGPR_32:{ *:[i32] }:$voffset, sub1:{ *:[i32] }), SReg_128:{ *:[v4i32] }:$rsrc, SCSrc_b32:{ *:[i32] }:$soffset, (timm:{ *:[i32] }):$offset, (extract_cpol:{ *:[i32] } ?:{ *:[i32] }:$auxiliary), (extract_swz:{ *:[i1] } ?:{ *:[i32] }:$auxiliary))
        GIR_MakeTempReg, /*TempRegID*/0, /*TypeID*/GILLT_s64,
        GIR_BuildMI, /*InsnID*/1, /*Opcode*/GIMT_Encode2(TargetOpcode::REG_SEQUENCE),
        GIR_AddTempRegister, /*InsnID*/1, /*TempRegID*/0, /*TempRegFlags*/GIMT_Encode2(RegState::Define),
        GIR_Copy, /*NewInsnID*/1, /*OldInsnID*/0, /*OpIdx*/2, // vindex
        GIR_AddImm8, /*InsnID*/1, /*SubRegIndex*/3,
        GIR_Copy, /*NewInsnID*/1, /*OldInsnID*/0, /*OpIdx*/3, // voffset
        GIR_AddImm8, /*InsnID*/1, /*SubRegIndex*/11,
        GIR_ConstrainOperandRC, /*InsnID*/1, /*Op*/0, GIMT_Encode2(AMDGPU::VReg_64RegClassID),
        GIR_ConstrainOperandRC, /*InsnID*/1, /*Op*/1, GIMT_Encode2(AMDGPU::VGPR_32RegClassID),
        GIR_ConstrainOperandRC, /*InsnID*/1, /*Op*/3, GIMT_Encode2(AMDGPU::VGPR_32RegClassID),
        GIR_BuildMI, /*InsnID*/0, /*Opcode*/GIMT_Encode2(AMDGPU::BUFFER_LOAD_FORMAT_XYZ_BOTHEN),
        GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/0, // DstI[vdata]
        GIR_AddSimpleTempRegister, /*InsnID*/0, /*TempRegID*/0,
        GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/1, // rsrc
        GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/0, // soffset
        GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/5, // offset
        GIR_CustomOperandRenderer, /*InsnID*/0, /*OldInsnID*/0, /*OpIdx*/6, /*OperandRenderer*/GIMT_Encode2(GICR_renderExtractCPol), // auxiliary
        GIR_CustomOperandRenderer, /*InsnID*/0, /*OldInsnID*/0, /*OpIdx*/6, /*OperandRenderer*/GIMT_Encode2(GICR_renderExtractSWZ), // auxiliary
        GIR_MergeMemOperands, /*InsnID*/0, /*NumInsns*/1, /*MergeInsnID's*/0,
        GIR_ConstrainSelectedInstOperands, /*InsnID*/0,
        GIR_EraseFromParent, /*InsnID*/0,
        // GIR_Coverage, 3948,
        GIR_Done,
      // Label 6552: @481058
      GIM_Try, /*On fail goto*//*Label 6553*/ GIMT_Encode4(481165), // Rule ID 3952 //
        // MIs[0] offset
        GIM_CheckIsImm, /*MI*/0, /*Op*/5,
        // MIs[0] auxiliary
        GIM_CheckIsImm, /*MI*/0, /*Op*/6,
        // MIs[0] Operand 7
        GIM_CheckIsImm, /*MI*/0, /*Op*/7,
        GIM_CheckComplexPattern, /*MI*/0, /*Op*/4, /*Renderer*/GIMT_Encode2(0), GIMT_Encode2(GICP_gi_buf_soffset),
        // (SIbuffer_load_format:{ *:[v3f32] } v4i32:{ *:[v4i32] }:$rsrc, i32:{ *:[i32] }:$vindex, i32:{ *:[i32] }:$voffset, (BUFSOffset:{ *:[i32] } i32:{ *:[i32] }:$soffset), (timm:{ *:[i32] }):$offset, (timm:{ *:[i32] }):$auxiliary, (timm:{ *:[i1] }))  =>  (BUFFER_LOAD_FORMAT_XYZ_VBUFFER_BOTHEN:{ *:[v3f32] } (REG_SEQUENCE:{ *:[i64] } VReg_64:{ *:[i32] }, VGPR_32:{ *:[i32] }:$vindex, sub0:{ *:[i32] }, VGPR_32:{ *:[i32] }:$voffset, sub1:{ *:[i32] }), SReg_128:{ *:[v4i32] }:$rsrc, SCSrc_b32:{ *:[i32] }:$soffset, (timm:{ *:[i32] }):$offset, (extract_cpol:{ *:[i32] } ?:{ *:[i32] }:$auxiliary), (extract_swz:{ *:[i1] } ?:{ *:[i32] }:$auxiliary))
        GIR_MakeTempReg, /*TempRegID*/0, /*TypeID*/GILLT_s64,
        GIR_BuildMI, /*InsnID*/1, /*Opcode*/GIMT_Encode2(TargetOpcode::REG_SEQUENCE),
        GIR_AddTempRegister, /*InsnID*/1, /*TempRegID*/0, /*TempRegFlags*/GIMT_Encode2(RegState::Define),
        GIR_Copy, /*NewInsnID*/1, /*OldInsnID*/0, /*OpIdx*/2, // vindex
        GIR_AddImm8, /*InsnID*/1, /*SubRegIndex*/3,
        GIR_Copy, /*NewInsnID*/1, /*OldInsnID*/0, /*OpIdx*/3, // voffset
        GIR_AddImm8, /*InsnID*/1, /*SubRegIndex*/11,
        GIR_ConstrainOperandRC, /*InsnID*/1, /*Op*/0, GIMT_Encode2(AMDGPU::VReg_64RegClassID),
        GIR_ConstrainOperandRC, /*InsnID*/1, /*Op*/1, GIMT_Encode2(AMDGPU::VGPR_32RegClassID),
        GIR_ConstrainOperandRC, /*InsnID*/1, /*Op*/3, GIMT_Encode2(AMDGPU::VGPR_32RegClassID),
        GIR_BuildMI, /*InsnID*/0, /*Opcode*/GIMT_Encode2(AMDGPU::BUFFER_LOAD_FORMAT_XYZ_VBUFFER_BOTHEN),
        GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/0, // DstI[vdata]
        GIR_AddSimpleTempRegister, /*InsnID*/0, /*TempRegID*/0,
        GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/1, // rsrc
        GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/0, // soffset
        GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/5, // offset
        GIR_CustomOperandRenderer, /*InsnID*/0, /*OldInsnID*/0, /*OpIdx*/6, /*OperandRenderer*/GIMT_Encode2(GICR_renderExtractCPol), // auxiliary
        GIR_CustomOperandRenderer, /*InsnID*/0, /*OldInsnID*/0, /*OpIdx*/6, /*OperandRenderer*/GIMT_Encode2(GICR_renderExtractSWZ), // auxiliary
        GIR_MergeMemOperands, /*InsnID*/0, /*NumInsns*/1, /*MergeInsnID's*/0,
        GIR_ConstrainSelectedInstOperands, /*InsnID*/0,
        GIR_EraseFromParent, /*InsnID*/0,
        // GIR_Coverage, 3952,
        GIR_Done,
      // Label 6553: @481165
      GIM_Try, /*On fail goto*//*Label 6554*/ GIMT_Encode4(481275), // Rule ID 3956 //
        GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasUnrestrictedSOffset),
        // MIs[0] offset
        GIM_CheckIsImm, /*MI*/0, /*Op*/5,
        // MIs[0] auxiliary
        GIM_CheckIsImm, /*MI*/0, /*Op*/6,
        // MIs[0] Operand 7
        GIM_CheckIsImm, /*MI*/0, /*Op*/7,
        GIM_CheckComplexPattern, /*MI*/0, /*Op*/4, /*Renderer*/GIMT_Encode2(0), GIMT_Encode2(GICP_gi_buf_soffset),
        // (SIbuffer_load_format:{ *:[v3i32] } v4i32:{ *:[v4i32] }:$rsrc, i32:{ *:[i32] }:$vindex, i32:{ *:[i32] }:$voffset, (BUFSOffset:{ *:[i32] } i32:{ *:[i32] }:$soffset), (timm:{ *:[i32] }):$offset, (timm:{ *:[i32] }):$auxiliary, (timm:{ *:[i1] }))  =>  (BUFFER_LOAD_FORMAT_XYZ_BOTHEN:{ *:[v3i32] } (REG_SEQUENCE:{ *:[i64] } VReg_64:{ *:[i32] }, VGPR_32:{ *:[i32] }:$vindex, sub0:{ *:[i32] }, VGPR_32:{ *:[i32] }:$voffset, sub1:{ *:[i32] }), SReg_128:{ *:[v4i32] }:$rsrc, SCSrc_b32:{ *:[i32] }:$soffset, (timm:{ *:[i32] }):$offset, (extract_cpol:{ *:[i32] } ?:{ *:[i32] }:$auxiliary), (extract_swz:{ *:[i1] } ?:{ *:[i32] }:$auxiliary))
        GIR_MakeTempReg, /*TempRegID*/0, /*TypeID*/GILLT_s64,
        GIR_BuildMI, /*InsnID*/1, /*Opcode*/GIMT_Encode2(TargetOpcode::REG_SEQUENCE),
        GIR_AddTempRegister, /*InsnID*/1, /*TempRegID*/0, /*TempRegFlags*/GIMT_Encode2(RegState::Define),
        GIR_Copy, /*NewInsnID*/1, /*OldInsnID*/0, /*OpIdx*/2, // vindex
        GIR_AddImm8, /*InsnID*/1, /*SubRegIndex*/3,
        GIR_Copy, /*NewInsnID*/1, /*OldInsnID*/0, /*OpIdx*/3, // voffset
        GIR_AddImm8, /*InsnID*/1, /*SubRegIndex*/11,
        GIR_ConstrainOperandRC, /*InsnID*/1, /*Op*/0, GIMT_Encode2(AMDGPU::VReg_64RegClassID),
        GIR_ConstrainOperandRC, /*InsnID*/1, /*Op*/1, GIMT_Encode2(AMDGPU::VGPR_32RegClassID),
        GIR_ConstrainOperandRC, /*InsnID*/1, /*Op*/3, GIMT_Encode2(AMDGPU::VGPR_32RegClassID),
        GIR_BuildMI, /*InsnID*/0, /*Opcode*/GIMT_Encode2(AMDGPU::BUFFER_LOAD_FORMAT_XYZ_BOTHEN),
        GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/0, // DstI[vdata]
        GIR_AddSimpleTempRegister, /*InsnID*/0, /*TempRegID*/0,
        GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/1, // rsrc
        GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/0, // soffset
        GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/5, // offset
        GIR_CustomOperandRenderer, /*InsnID*/0, /*OldInsnID*/0, /*OpIdx*/6, /*OperandRenderer*/GIMT_Encode2(GICR_renderExtractCPol), // auxiliary
        GIR_CustomOperandRenderer, /*InsnID*/0, /*OldInsnID*/0, /*OpIdx*/6, /*OperandRenderer*/GIMT_Encode2(GICR_renderExtractSWZ), // auxiliary
        GIR_MergeMemOperands, /*InsnID*/0, /*NumInsns*/1, /*MergeInsnID's*/0,
        GIR_ConstrainSelectedInstOperands, /*InsnID*/0,
        GIR_EraseFromParent, /*InsnID*/0,
        // GIR_Coverage, 3956,
        GIR_Done,
      // Label 6554: @481275
      GIM_Try, /*On fail goto*//*Label 6555*/ GIMT_Encode4(481382), // Rule ID 3960 //
        // MIs[0] offset
        GIM_CheckIsImm, /*MI*/0, /*Op*/5,
        // MIs[0] auxiliary
        GIM_CheckIsImm, /*MI*/0, /*Op*/6,
        // MIs[0] Operand 7
        GIM_CheckIsImm, /*MI*/0, /*Op*/7,
        GIM_CheckComplexPattern, /*MI*/0, /*Op*/4, /*Renderer*/GIMT_Encode2(0), GIMT_Encode2(GICP_gi_buf_soffset),
        // (SIbuffer_load_format:{ *:[v3i32] } v4i32:{ *:[v4i32] }:$rsrc, i32:{ *:[i32] }:$vindex, i32:{ *:[i32] }:$voffset, (BUFSOffset:{ *:[i32] } i32:{ *:[i32] }:$soffset), (timm:{ *:[i32] }):$offset, (timm:{ *:[i32] }):$auxiliary, (timm:{ *:[i1] }))  =>  (BUFFER_LOAD_FORMAT_XYZ_VBUFFER_BOTHEN:{ *:[v3i32] } (REG_SEQUENCE:{ *:[i64] } VReg_64:{ *:[i32] }, VGPR_32:{ *:[i32] }:$vindex, sub0:{ *:[i32] }, VGPR_32:{ *:[i32] }:$voffset, sub1:{ *:[i32] }), SReg_128:{ *:[v4i32] }:$rsrc, SCSrc_b32:{ *:[i32] }:$soffset, (timm:{ *:[i32] }):$offset, (extract_cpol:{ *:[i32] } ?:{ *:[i32] }:$auxiliary), (extract_swz:{ *:[i1] } ?:{ *:[i32] }:$auxiliary))
        GIR_MakeTempReg, /*TempRegID*/0, /*TypeID*/GILLT_s64,
        GIR_BuildMI, /*InsnID*/1, /*Opcode*/GIMT_Encode2(TargetOpcode::REG_SEQUENCE),
        GIR_AddTempRegister, /*InsnID*/1, /*TempRegID*/0, /*TempRegFlags*/GIMT_Encode2(RegState::Define),
        GIR_Copy, /*NewInsnID*/1, /*OldInsnID*/0, /*OpIdx*/2, // vindex
        GIR_AddImm8, /*InsnID*/1, /*SubRegIndex*/3,
        GIR_Copy, /*NewInsnID*/1, /*OldInsnID*/0, /*OpIdx*/3, // voffset
        GIR_AddImm8, /*InsnID*/1, /*SubRegIndex*/11,
        GIR_ConstrainOperandRC, /*InsnID*/1, /*Op*/0, GIMT_Encode2(AMDGPU::VReg_64RegClassID),
        GIR_ConstrainOperandRC, /*InsnID*/1, /*Op*/1, GIMT_Encode2(AMDGPU::VGPR_32RegClassID),
        GIR_ConstrainOperandRC, /*InsnID*/1, /*Op*/3, GIMT_Encode2(AMDGPU::VGPR_32RegClassID),
        GIR_BuildMI, /*InsnID*/0, /*Opcode*/GIMT_Encode2(AMDGPU::BUFFER_LOAD_FORMAT_XYZ_VBUFFER_BOTHEN),
        GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/0, // DstI[vdata]
        GIR_AddSimpleTempRegister, /*InsnID*/0, /*TempRegID*/0,
        GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/1, // rsrc
        GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/0, // soffset
        GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/5, // offset
        GIR_CustomOperandRenderer, /*InsnID*/0, /*OldInsnID*/0, /*OpIdx*/6, /*OperandRenderer*/GIMT_Encode2(GICR_renderExtractCPol), // auxiliary
        GIR_CustomOperandRenderer, /*InsnID*/0, /*OldInsnID*/0, /*OpIdx*/6, /*OperandRenderer*/GIMT_Encode2(GICR_renderExtractSWZ), // auxiliary
        GIR_MergeMemOperands, /*InsnID*/0, /*NumInsns*/1, /*MergeInsnID's*/0,
        GIR_ConstrainSelectedInstOperands, /*InsnID*/0,
        GIR_EraseFromParent, /*InsnID*/0,
        // GIR_Coverage, 3960,
        GIR_Done,
      // Label 6555: @481382
      GIM_Reject,
    // Label 6539: @481383
    GIM_Reject,
    // Label 6503: @481384
    GIM_Try, /*On fail goto*//*Label 6556*/ GIMT_Encode4(482779),
      GIM_CheckType, /*MI*/0, /*Op*/1, /*Type*/GILLT_v4s32,
      GIM_CheckType, /*MI*/0, /*Op*/2, /*Type*/GILLT_s32,
      GIM_CheckType, /*MI*/0, /*Op*/3, /*Type*/GILLT_s32,
      GIM_CheckType, /*MI*/0, /*Op*/4, /*Type*/GILLT_s32,
      GIM_CheckRegBankForClass, /*MI*/0, /*Op*/0, /*RC*/GIMT_Encode2(AMDGPU::AV_128RegClassID),
      GIM_Try, /*On fail goto*//*Label 6557*/ GIMT_Encode4(481492), // Rule ID 3961 //
        GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasUnrestrictedSOffset),
        GIM_CheckConstantInt8, /*MI*/0, /*Op*/2, 0,
        GIM_CheckConstantInt8, /*MI*/0, /*Op*/3, 0,
        // MIs[0] offset
        GIM_CheckIsImm, /*MI*/0, /*Op*/5,
        // MIs[0] auxiliary
        GIM_CheckIsImm, /*MI*/0, /*Op*/6,
        // MIs[0] Operand 7
        GIM_CheckLiteralInt, /*MI*/0, /*Op*/7, GIMT_Encode8(0),
        GIM_CheckComplexPattern, /*MI*/0, /*Op*/4, /*Renderer*/GIMT_Encode2(0), GIMT_Encode2(GICP_gi_buf_soffset),
        // (SIbuffer_load_format:{ *:[v4f32] } v4i32:{ *:[v4i32] }:$rsrc, 0:{ *:[i32] }, 0:{ *:[i32] }, (BUFSOffset:{ *:[i32] } i32:{ *:[i32] }:$soffset), (timm:{ *:[i32] }):$offset, (timm:{ *:[i32] }):$auxiliary, 0:{ *:[i1] })  =>  (BUFFER_LOAD_FORMAT_XYZW_OFFSET:{ *:[v4f32] } SReg_128:{ *:[v4i32] }:$rsrc, SCSrc_b32:{ *:[i32] }:$soffset, (timm:{ *:[i32] }):$offset, (extract_cpol:{ *:[i32] } ?:{ *:[i32] }:$auxiliary), (extract_swz:{ *:[i1] } ?:{ *:[i32] }:$auxiliary))
        GIR_BuildMI, /*InsnID*/0, /*Opcode*/GIMT_Encode2(AMDGPU::BUFFER_LOAD_FORMAT_XYZW_OFFSET),
        GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/0, // DstI[vdata]
        GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/1, // rsrc
        GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/0, // soffset
        GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/5, // offset
        GIR_CustomOperandRenderer, /*InsnID*/0, /*OldInsnID*/0, /*OpIdx*/6, /*OperandRenderer*/GIMT_Encode2(GICR_renderExtractCPol), // auxiliary
        GIR_CustomOperandRenderer, /*InsnID*/0, /*OldInsnID*/0, /*OpIdx*/6, /*OperandRenderer*/GIMT_Encode2(GICR_renderExtractSWZ), // auxiliary
        GIR_MergeMemOperands, /*InsnID*/0, /*NumInsns*/1, /*MergeInsnID's*/0,
        GIR_ConstrainSelectedInstOperands, /*InsnID*/0,
        GIR_EraseFromParent, /*InsnID*/0,
        // GIR_Coverage, 3961,
        GIR_Done,
      // Label 6557: @481492
      GIM_Try, /*On fail goto*//*Label 6558*/ GIMT_Encode4(481571), // Rule ID 3965 //
        GIM_CheckConstantInt8, /*MI*/0, /*Op*/2, 0,
        GIM_CheckConstantInt8, /*MI*/0, /*Op*/3, 0,
        // MIs[0] offset
        GIM_CheckIsImm, /*MI*/0, /*Op*/5,
        // MIs[0] auxiliary
        GIM_CheckIsImm, /*MI*/0, /*Op*/6,
        // MIs[0] Operand 7
        GIM_CheckLiteralInt, /*MI*/0, /*Op*/7, GIMT_Encode8(0),
        GIM_CheckComplexPattern, /*MI*/0, /*Op*/4, /*Renderer*/GIMT_Encode2(0), GIMT_Encode2(GICP_gi_buf_soffset),
        // (SIbuffer_load_format:{ *:[v4f32] } v4i32:{ *:[v4i32] }:$rsrc, 0:{ *:[i32] }, 0:{ *:[i32] }, (BUFSOffset:{ *:[i32] } i32:{ *:[i32] }:$soffset), (timm:{ *:[i32] }):$offset, (timm:{ *:[i32] }):$auxiliary, 0:{ *:[i1] })  =>  (BUFFER_LOAD_FORMAT_XYZW_VBUFFER_OFFSET:{ *:[v4f32] } SReg_128:{ *:[v4i32] }:$rsrc, SCSrc_b32:{ *:[i32] }:$soffset, (timm:{ *:[i32] }):$offset, (extract_cpol:{ *:[i32] } ?:{ *:[i32] }:$auxiliary), (extract_swz:{ *:[i1] } ?:{ *:[i32] }:$auxiliary))
        GIR_BuildMI, /*InsnID*/0, /*Opcode*/GIMT_Encode2(AMDGPU::BUFFER_LOAD_FORMAT_XYZW_VBUFFER_OFFSET),
        GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/0, // DstI[vdata]
        GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/1, // rsrc
        GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/0, // soffset
        GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/5, // offset
        GIR_CustomOperandRenderer, /*InsnID*/0, /*OldInsnID*/0, /*OpIdx*/6, /*OperandRenderer*/GIMT_Encode2(GICR_renderExtractCPol), // auxiliary
        GIR_CustomOperandRenderer, /*InsnID*/0, /*OldInsnID*/0, /*OpIdx*/6, /*OperandRenderer*/GIMT_Encode2(GICR_renderExtractSWZ), // auxiliary
        GIR_MergeMemOperands, /*InsnID*/0, /*NumInsns*/1, /*MergeInsnID's*/0,
        GIR_ConstrainSelectedInstOperands, /*InsnID*/0,
        GIR_EraseFromParent, /*InsnID*/0,
        // GIR_Coverage, 3965,
        GIR_Done,
      // Label 6558: @481571
      GIM_Try, /*On fail goto*//*Label 6559*/ GIMT_Encode4(481653), // Rule ID 3969 //
        GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasUnrestrictedSOffset),
        GIM_CheckConstantInt8, /*MI*/0, /*Op*/2, 0,
        GIM_CheckConstantInt8, /*MI*/0, /*Op*/3, 0,
        // MIs[0] offset
        GIM_CheckIsImm, /*MI*/0, /*Op*/5,
        // MIs[0] auxiliary
        GIM_CheckIsImm, /*MI*/0, /*Op*/6,
        // MIs[0] Operand 7
        GIM_CheckLiteralInt, /*MI*/0, /*Op*/7, GIMT_Encode8(0),
        GIM_CheckComplexPattern, /*MI*/0, /*Op*/4, /*Renderer*/GIMT_Encode2(0), GIMT_Encode2(GICP_gi_buf_soffset),
        // (SIbuffer_load_format:{ *:[v4i32] } v4i32:{ *:[v4i32] }:$rsrc, 0:{ *:[i32] }, 0:{ *:[i32] }, (BUFSOffset:{ *:[i32] } i32:{ *:[i32] }:$soffset), (timm:{ *:[i32] }):$offset, (timm:{ *:[i32] }):$auxiliary, 0:{ *:[i1] })  =>  (BUFFER_LOAD_FORMAT_XYZW_OFFSET:{ *:[v4i32] } SReg_128:{ *:[v4i32] }:$rsrc, SCSrc_b32:{ *:[i32] }:$soffset, (timm:{ *:[i32] }):$offset, (extract_cpol:{ *:[i32] } ?:{ *:[i32] }:$auxiliary), (extract_swz:{ *:[i1] } ?:{ *:[i32] }:$auxiliary))
        GIR_BuildMI, /*InsnID*/0, /*Opcode*/GIMT_Encode2(AMDGPU::BUFFER_LOAD_FORMAT_XYZW_OFFSET),
        GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/0, // DstI[vdata]
        GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/1, // rsrc
        GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/0, // soffset
        GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/5, // offset
        GIR_CustomOperandRenderer, /*InsnID*/0, /*OldInsnID*/0, /*OpIdx*/6, /*OperandRenderer*/GIMT_Encode2(GICR_renderExtractCPol), // auxiliary
        GIR_CustomOperandRenderer, /*InsnID*/0, /*OldInsnID*/0, /*OpIdx*/6, /*OperandRenderer*/GIMT_Encode2(GICR_renderExtractSWZ), // auxiliary
        GIR_MergeMemOperands, /*InsnID*/0, /*NumInsns*/1, /*MergeInsnID's*/0,
        GIR_ConstrainSelectedInstOperands, /*InsnID*/0,
        GIR_EraseFromParent, /*InsnID*/0,
        // GIR_Coverage, 3969,
        GIR_Done,
      // Label 6559: @481653
      GIM_Try, /*On fail goto*//*Label 6560*/ GIMT_Encode4(481732), // Rule ID 3973 //
        GIM_CheckConstantInt8, /*MI*/0, /*Op*/2, 0,
        GIM_CheckConstantInt8, /*MI*/0, /*Op*/3, 0,
        // MIs[0] offset
        GIM_CheckIsImm, /*MI*/0, /*Op*/5,
        // MIs[0] auxiliary
        GIM_CheckIsImm, /*MI*/0, /*Op*/6,
        // MIs[0] Operand 7
        GIM_CheckLiteralInt, /*MI*/0, /*Op*/7, GIMT_Encode8(0),
        GIM_CheckComplexPattern, /*MI*/0, /*Op*/4, /*Renderer*/GIMT_Encode2(0), GIMT_Encode2(GICP_gi_buf_soffset),
        // (SIbuffer_load_format:{ *:[v4i32] } v4i32:{ *:[v4i32] }:$rsrc, 0:{ *:[i32] }, 0:{ *:[i32] }, (BUFSOffset:{ *:[i32] } i32:{ *:[i32] }:$soffset), (timm:{ *:[i32] }):$offset, (timm:{ *:[i32] }):$auxiliary, 0:{ *:[i1] })  =>  (BUFFER_LOAD_FORMAT_XYZW_VBUFFER_OFFSET:{ *:[v4i32] } SReg_128:{ *:[v4i32] }:$rsrc, SCSrc_b32:{ *:[i32] }:$soffset, (timm:{ *:[i32] }):$offset, (extract_cpol:{ *:[i32] } ?:{ *:[i32] }:$auxiliary), (extract_swz:{ *:[i1] } ?:{ *:[i32] }:$auxiliary))
        GIR_BuildMI, /*InsnID*/0, /*Opcode*/GIMT_Encode2(AMDGPU::BUFFER_LOAD_FORMAT_XYZW_VBUFFER_OFFSET),
        GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/0, // DstI[vdata]
        GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/1, // rsrc
        GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/0, // soffset
        GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/5, // offset
        GIR_CustomOperandRenderer, /*InsnID*/0, /*OldInsnID*/0, /*OpIdx*/6, /*OperandRenderer*/GIMT_Encode2(GICR_renderExtractCPol), // auxiliary
        GIR_CustomOperandRenderer, /*InsnID*/0, /*OldInsnID*/0, /*OpIdx*/6, /*OperandRenderer*/GIMT_Encode2(GICR_renderExtractSWZ), // auxiliary
        GIR_MergeMemOperands, /*InsnID*/0, /*NumInsns*/1, /*MergeInsnID's*/0,
        GIR_ConstrainSelectedInstOperands, /*InsnID*/0,
        GIR_EraseFromParent, /*InsnID*/0,
        // GIR_Coverage, 3973,
        GIR_Done,
      // Label 6560: @481732
      GIM_Try, /*On fail goto*//*Label 6561*/ GIMT_Encode4(481814), // Rule ID 3962 //
        GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasUnrestrictedSOffset),
        GIM_CheckConstantInt8, /*MI*/0, /*Op*/2, 0,
        // MIs[0] offset
        GIM_CheckIsImm, /*MI*/0, /*Op*/5,
        // MIs[0] auxiliary
        GIM_CheckIsImm, /*MI*/0, /*Op*/6,
        // MIs[0] Operand 7
        GIM_CheckLiteralInt, /*MI*/0, /*Op*/7, GIMT_Encode8(0),
        GIM_CheckComplexPattern, /*MI*/0, /*Op*/4, /*Renderer*/GIMT_Encode2(0), GIMT_Encode2(GICP_gi_buf_soffset),
        // (SIbuffer_load_format:{ *:[v4f32] } v4i32:{ *:[v4i32] }:$rsrc, 0:{ *:[i32] }, i32:{ *:[i32] }:$voffset, (BUFSOffset:{ *:[i32] } i32:{ *:[i32] }:$soffset), (timm:{ *:[i32] }):$offset, (timm:{ *:[i32] }):$auxiliary, 0:{ *:[i1] })  =>  (BUFFER_LOAD_FORMAT_XYZW_OFFEN:{ *:[v4f32] } VGPR_32:{ *:[i32] }:$voffset, SReg_128:{ *:[v4i32] }:$rsrc, SCSrc_b32:{ *:[i32] }:$soffset, (timm:{ *:[i32] }):$offset, (extract_cpol:{ *:[i32] } ?:{ *:[i32] }:$auxiliary), (extract_swz:{ *:[i1] } ?:{ *:[i32] }:$auxiliary))
        GIR_BuildMI, /*InsnID*/0, /*Opcode*/GIMT_Encode2(AMDGPU::BUFFER_LOAD_FORMAT_XYZW_OFFEN),
        GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/0, // DstI[vdata]
        GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/3, // voffset
        GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/1, // rsrc
        GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/0, // soffset
        GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/5, // offset
        GIR_CustomOperandRenderer, /*InsnID*/0, /*OldInsnID*/0, /*OpIdx*/6, /*OperandRenderer*/GIMT_Encode2(GICR_renderExtractCPol), // auxiliary
        GIR_CustomOperandRenderer, /*InsnID*/0, /*OldInsnID*/0, /*OpIdx*/6, /*OperandRenderer*/GIMT_Encode2(GICR_renderExtractSWZ), // auxiliary
        GIR_MergeMemOperands, /*InsnID*/0, /*NumInsns*/1, /*MergeInsnID's*/0,
        GIR_ConstrainSelectedInstOperands, /*InsnID*/0,
        GIR_EraseFromParent, /*InsnID*/0,
        // GIR_Coverage, 3962,
        GIR_Done,
      // Label 6561: @481814
      GIM_Try, /*On fail goto*//*Label 6562*/ GIMT_Encode4(481893), // Rule ID 3966 //
        GIM_CheckConstantInt8, /*MI*/0, /*Op*/2, 0,
        // MIs[0] offset
        GIM_CheckIsImm, /*MI*/0, /*Op*/5,
        // MIs[0] auxiliary
        GIM_CheckIsImm, /*MI*/0, /*Op*/6,
        // MIs[0] Operand 7
        GIM_CheckLiteralInt, /*MI*/0, /*Op*/7, GIMT_Encode8(0),
        GIM_CheckComplexPattern, /*MI*/0, /*Op*/4, /*Renderer*/GIMT_Encode2(0), GIMT_Encode2(GICP_gi_buf_soffset),
        // (SIbuffer_load_format:{ *:[v4f32] } v4i32:{ *:[v4i32] }:$rsrc, 0:{ *:[i32] }, i32:{ *:[i32] }:$voffset, (BUFSOffset:{ *:[i32] } i32:{ *:[i32] }:$soffset), (timm:{ *:[i32] }):$offset, (timm:{ *:[i32] }):$auxiliary, 0:{ *:[i1] })  =>  (BUFFER_LOAD_FORMAT_XYZW_VBUFFER_OFFEN:{ *:[v4f32] } VGPR_32:{ *:[i32] }:$voffset, SReg_128:{ *:[v4i32] }:$rsrc, SCSrc_b32:{ *:[i32] }:$soffset, (timm:{ *:[i32] }):$offset, (extract_cpol:{ *:[i32] } ?:{ *:[i32] }:$auxiliary), (extract_swz:{ *:[i1] } ?:{ *:[i32] }:$auxiliary))
        GIR_BuildMI, /*InsnID*/0, /*Opcode*/GIMT_Encode2(AMDGPU::BUFFER_LOAD_FORMAT_XYZW_VBUFFER_OFFEN),
        GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/0, // DstI[vdata]
        GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/3, // voffset
        GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/1, // rsrc
        GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/0, // soffset
        GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/5, // offset
        GIR_CustomOperandRenderer, /*InsnID*/0, /*OldInsnID*/0, /*OpIdx*/6, /*OperandRenderer*/GIMT_Encode2(GICR_renderExtractCPol), // auxiliary
        GIR_CustomOperandRenderer, /*InsnID*/0, /*OldInsnID*/0, /*OpIdx*/6, /*OperandRenderer*/GIMT_Encode2(GICR_renderExtractSWZ), // auxiliary
        GIR_MergeMemOperands, /*InsnID*/0, /*NumInsns*/1, /*MergeInsnID's*/0,
        GIR_ConstrainSelectedInstOperands, /*InsnID*/0,
        GIR_EraseFromParent, /*InsnID*/0,
        // GIR_Coverage, 3966,
        GIR_Done,
      // Label 6562: @481893
      GIM_Try, /*On fail goto*//*Label 6563*/ GIMT_Encode4(481975), // Rule ID 3970 //
        GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasUnrestrictedSOffset),
        GIM_CheckConstantInt8, /*MI*/0, /*Op*/2, 0,
        // MIs[0] offset
        GIM_CheckIsImm, /*MI*/0, /*Op*/5,
        // MIs[0] auxiliary
        GIM_CheckIsImm, /*MI*/0, /*Op*/6,
        // MIs[0] Operand 7
        GIM_CheckLiteralInt, /*MI*/0, /*Op*/7, GIMT_Encode8(0),
        GIM_CheckComplexPattern, /*MI*/0, /*Op*/4, /*Renderer*/GIMT_Encode2(0), GIMT_Encode2(GICP_gi_buf_soffset),
        // (SIbuffer_load_format:{ *:[v4i32] } v4i32:{ *:[v4i32] }:$rsrc, 0:{ *:[i32] }, i32:{ *:[i32] }:$voffset, (BUFSOffset:{ *:[i32] } i32:{ *:[i32] }:$soffset), (timm:{ *:[i32] }):$offset, (timm:{ *:[i32] }):$auxiliary, 0:{ *:[i1] })  =>  (BUFFER_LOAD_FORMAT_XYZW_OFFEN:{ *:[v4i32] } VGPR_32:{ *:[i32] }:$voffset, SReg_128:{ *:[v4i32] }:$rsrc, SCSrc_b32:{ *:[i32] }:$soffset, (timm:{ *:[i32] }):$offset, (extract_cpol:{ *:[i32] } ?:{ *:[i32] }:$auxiliary), (extract_swz:{ *:[i1] } ?:{ *:[i32] }:$auxiliary))
        GIR_BuildMI, /*InsnID*/0, /*Opcode*/GIMT_Encode2(AMDGPU::BUFFER_LOAD_FORMAT_XYZW_OFFEN),
        GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/0, // DstI[vdata]
        GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/3, // voffset
        GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/1, // rsrc
        GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/0, // soffset
        GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/5, // offset
        GIR_CustomOperandRenderer, /*InsnID*/0, /*OldInsnID*/0, /*OpIdx*/6, /*OperandRenderer*/GIMT_Encode2(GICR_renderExtractCPol), // auxiliary
        GIR_CustomOperandRenderer, /*InsnID*/0, /*OldInsnID*/0, /*OpIdx*/6, /*OperandRenderer*/GIMT_Encode2(GICR_renderExtractSWZ), // auxiliary
        GIR_MergeMemOperands, /*InsnID*/0, /*NumInsns*/1, /*MergeInsnID's*/0,
        GIR_ConstrainSelectedInstOperands, /*InsnID*/0,
        GIR_EraseFromParent, /*InsnID*/0,
        // GIR_Coverage, 3970,
        GIR_Done,
      // Label 6563: @481975
      GIM_Try, /*On fail goto*//*Label 6564*/ GIMT_Encode4(482054), // Rule ID 3974 //
        GIM_CheckConstantInt8, /*MI*/0, /*Op*/2, 0,
        // MIs[0] offset
        GIM_CheckIsImm, /*MI*/0, /*Op*/5,
        // MIs[0] auxiliary
        GIM_CheckIsImm, /*MI*/0, /*Op*/6,
        // MIs[0] Operand 7
        GIM_CheckLiteralInt, /*MI*/0, /*Op*/7, GIMT_Encode8(0),
        GIM_CheckComplexPattern, /*MI*/0, /*Op*/4, /*Renderer*/GIMT_Encode2(0), GIMT_Encode2(GICP_gi_buf_soffset),
        // (SIbuffer_load_format:{ *:[v4i32] } v4i32:{ *:[v4i32] }:$rsrc, 0:{ *:[i32] }, i32:{ *:[i32] }:$voffset, (BUFSOffset:{ *:[i32] } i32:{ *:[i32] }:$soffset), (timm:{ *:[i32] }):$offset, (timm:{ *:[i32] }):$auxiliary, 0:{ *:[i1] })  =>  (BUFFER_LOAD_FORMAT_XYZW_VBUFFER_OFFEN:{ *:[v4i32] } VGPR_32:{ *:[i32] }:$voffset, SReg_128:{ *:[v4i32] }:$rsrc, SCSrc_b32:{ *:[i32] }:$soffset, (timm:{ *:[i32] }):$offset, (extract_cpol:{ *:[i32] } ?:{ *:[i32] }:$auxiliary), (extract_swz:{ *:[i1] } ?:{ *:[i32] }:$auxiliary))
        GIR_BuildMI, /*InsnID*/0, /*Opcode*/GIMT_Encode2(AMDGPU::BUFFER_LOAD_FORMAT_XYZW_VBUFFER_OFFEN),
        GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/0, // DstI[vdata]
        GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/3, // voffset
        GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/1, // rsrc
        GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/0, // soffset
        GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/5, // offset
        GIR_CustomOperandRenderer, /*InsnID*/0, /*OldInsnID*/0, /*OpIdx*/6, /*OperandRenderer*/GIMT_Encode2(GICR_renderExtractCPol), // auxiliary
        GIR_CustomOperandRenderer, /*InsnID*/0, /*OldInsnID*/0, /*OpIdx*/6, /*OperandRenderer*/GIMT_Encode2(GICR_renderExtractSWZ), // auxiliary
        GIR_MergeMemOperands, /*InsnID*/0, /*NumInsns*/1, /*MergeInsnID's*/0,
        GIR_ConstrainSelectedInstOperands, /*InsnID*/0,
        GIR_EraseFromParent, /*InsnID*/0,
        // GIR_Coverage, 3974,
        GIR_Done,
      // Label 6564: @482054
      GIM_Try, /*On fail goto*//*Label 6565*/ GIMT_Encode4(482128), // Rule ID 3963 //
        GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasUnrestrictedSOffset),
        GIM_CheckConstantInt8, /*MI*/0, /*Op*/3, 0,
        // MIs[0] offset
        GIM_CheckIsImm, /*MI*/0, /*Op*/5,
        // MIs[0] auxiliary
        GIM_CheckIsImm, /*MI*/0, /*Op*/6,
        // MIs[0] Operand 7
        GIM_CheckIsImm, /*MI*/0, /*Op*/7,
        GIM_CheckComplexPattern, /*MI*/0, /*Op*/4, /*Renderer*/GIMT_Encode2(0), GIMT_Encode2(GICP_gi_buf_soffset),
        // (SIbuffer_load_format:{ *:[v4f32] } v4i32:{ *:[v4i32] }:$rsrc, i32:{ *:[i32] }:$vindex, 0:{ *:[i32] }, (BUFSOffset:{ *:[i32] } i32:{ *:[i32] }:$soffset), (timm:{ *:[i32] }):$offset, (timm:{ *:[i32] }):$auxiliary, (timm:{ *:[i1] }))  =>  (BUFFER_LOAD_FORMAT_XYZW_IDXEN:{ *:[v4f32] } VGPR_32:{ *:[i32] }:$vindex, SReg_128:{ *:[v4i32] }:$rsrc, SCSrc_b32:{ *:[i32] }:$soffset, (timm:{ *:[i32] }):$offset, (extract_cpol:{ *:[i32] } ?:{ *:[i32] }:$auxiliary), (extract_swz:{ *:[i1] } ?:{ *:[i32] }:$auxiliary))
        GIR_BuildMI, /*InsnID*/0, /*Opcode*/GIMT_Encode2(AMDGPU::BUFFER_LOAD_FORMAT_XYZW_IDXEN),
        GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/0, // DstI[vdata]
        GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/2, // vindex
        GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/1, // rsrc
        GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/0, // soffset
        GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/5, // offset
        GIR_CustomOperandRenderer, /*InsnID*/0, /*OldInsnID*/0, /*OpIdx*/6, /*OperandRenderer*/GIMT_Encode2(GICR_renderExtractCPol), // auxiliary
        GIR_CustomOperandRenderer, /*InsnID*/0, /*OldInsnID*/0, /*OpIdx*/6, /*OperandRenderer*/GIMT_Encode2(GICR_renderExtractSWZ), // auxiliary
        GIR_MergeMemOperands, /*InsnID*/0, /*NumInsns*/1, /*MergeInsnID's*/0,
        GIR_ConstrainSelectedInstOperands, /*InsnID*/0,
        GIR_EraseFromParent, /*InsnID*/0,
        // GIR_Coverage, 3963,
        GIR_Done,
      // Label 6565: @482128
      GIM_Try, /*On fail goto*//*Label 6566*/ GIMT_Encode4(482199), // Rule ID 3967 //
        GIM_CheckConstantInt8, /*MI*/0, /*Op*/3, 0,
        // MIs[0] offset
        GIM_CheckIsImm, /*MI*/0, /*Op*/5,
        // MIs[0] auxiliary
        GIM_CheckIsImm, /*MI*/0, /*Op*/6,
        // MIs[0] Operand 7
        GIM_CheckIsImm, /*MI*/0, /*Op*/7,
        GIM_CheckComplexPattern, /*MI*/0, /*Op*/4, /*Renderer*/GIMT_Encode2(0), GIMT_Encode2(GICP_gi_buf_soffset),
        // (SIbuffer_load_format:{ *:[v4f32] } v4i32:{ *:[v4i32] }:$rsrc, i32:{ *:[i32] }:$vindex, 0:{ *:[i32] }, (BUFSOffset:{ *:[i32] } i32:{ *:[i32] }:$soffset), (timm:{ *:[i32] }):$offset, (timm:{ *:[i32] }):$auxiliary, (timm:{ *:[i1] }))  =>  (BUFFER_LOAD_FORMAT_XYZW_VBUFFER_IDXEN:{ *:[v4f32] } VGPR_32:{ *:[i32] }:$vindex, SReg_128:{ *:[v4i32] }:$rsrc, SCSrc_b32:{ *:[i32] }:$soffset, (timm:{ *:[i32] }):$offset, (extract_cpol:{ *:[i32] } ?:{ *:[i32] }:$auxiliary), (extract_swz:{ *:[i1] } ?:{ *:[i32] }:$auxiliary))
        GIR_BuildMI, /*InsnID*/0, /*Opcode*/GIMT_Encode2(AMDGPU::BUFFER_LOAD_FORMAT_XYZW_VBUFFER_IDXEN),
        GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/0, // DstI[vdata]
        GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/2, // vindex
        GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/1, // rsrc
        GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/0, // soffset
        GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/5, // offset
        GIR_CustomOperandRenderer, /*InsnID*/0, /*OldInsnID*/0, /*OpIdx*/6, /*OperandRenderer*/GIMT_Encode2(GICR_renderExtractCPol), // auxiliary
        GIR_CustomOperandRenderer, /*InsnID*/0, /*OldInsnID*/0, /*OpIdx*/6, /*OperandRenderer*/GIMT_Encode2(GICR_renderExtractSWZ), // auxiliary
        GIR_MergeMemOperands, /*InsnID*/0, /*NumInsns*/1, /*MergeInsnID's*/0,
        GIR_ConstrainSelectedInstOperands, /*InsnID*/0,
        GIR_EraseFromParent, /*InsnID*/0,
        // GIR_Coverage, 3967,
        GIR_Done,
      // Label 6566: @482199
      GIM_Try, /*On fail goto*//*Label 6567*/ GIMT_Encode4(482273), // Rule ID 3971 //
        GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasUnrestrictedSOffset),
        GIM_CheckConstantInt8, /*MI*/0, /*Op*/3, 0,
        // MIs[0] offset
        GIM_CheckIsImm, /*MI*/0, /*Op*/5,
        // MIs[0] auxiliary
        GIM_CheckIsImm, /*MI*/0, /*Op*/6,
        // MIs[0] Operand 7
        GIM_CheckIsImm, /*MI*/0, /*Op*/7,
        GIM_CheckComplexPattern, /*MI*/0, /*Op*/4, /*Renderer*/GIMT_Encode2(0), GIMT_Encode2(GICP_gi_buf_soffset),
        // (SIbuffer_load_format:{ *:[v4i32] } v4i32:{ *:[v4i32] }:$rsrc, i32:{ *:[i32] }:$vindex, 0:{ *:[i32] }, (BUFSOffset:{ *:[i32] } i32:{ *:[i32] }:$soffset), (timm:{ *:[i32] }):$offset, (timm:{ *:[i32] }):$auxiliary, (timm:{ *:[i1] }))  =>  (BUFFER_LOAD_FORMAT_XYZW_IDXEN:{ *:[v4i32] } VGPR_32:{ *:[i32] }:$vindex, SReg_128:{ *:[v4i32] }:$rsrc, SCSrc_b32:{ *:[i32] }:$soffset, (timm:{ *:[i32] }):$offset, (extract_cpol:{ *:[i32] } ?:{ *:[i32] }:$auxiliary), (extract_swz:{ *:[i1] } ?:{ *:[i32] }:$auxiliary))
        GIR_BuildMI, /*InsnID*/0, /*Opcode*/GIMT_Encode2(AMDGPU::BUFFER_LOAD_FORMAT_XYZW_IDXEN),
        GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/0, // DstI[vdata]
        GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/2, // vindex
        GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/1, // rsrc
        GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/0, // soffset
        GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/5, // offset
        GIR_CustomOperandRenderer, /*InsnID*/0, /*OldInsnID*/0, /*OpIdx*/6, /*OperandRenderer*/GIMT_Encode2(GICR_renderExtractCPol), // auxiliary
        GIR_CustomOperandRenderer, /*InsnID*/0, /*OldInsnID*/0, /*OpIdx*/6, /*OperandRenderer*/GIMT_Encode2(GICR_renderExtractSWZ), // auxiliary
        GIR_MergeMemOperands, /*InsnID*/0, /*NumInsns*/1, /*MergeInsnID's*/0,
        GIR_ConstrainSelectedInstOperands, /*InsnID*/0,
        GIR_EraseFromParent, /*InsnID*/0,
        // GIR_Coverage, 3971,
        GIR_Done,
      // Label 6567: @482273
      GIM_Try, /*On fail goto*//*Label 6568*/ GIMT_Encode4(482344), // Rule ID 3975 //
        GIM_CheckConstantInt8, /*MI*/0, /*Op*/3, 0,
        // MIs[0] offset
        GIM_CheckIsImm, /*MI*/0, /*Op*/5,
        // MIs[0] auxiliary
        GIM_CheckIsImm, /*MI*/0, /*Op*/6,
        // MIs[0] Operand 7
        GIM_CheckIsImm, /*MI*/0, /*Op*/7,
        GIM_CheckComplexPattern, /*MI*/0, /*Op*/4, /*Renderer*/GIMT_Encode2(0), GIMT_Encode2(GICP_gi_buf_soffset),
        // (SIbuffer_load_format:{ *:[v4i32] } v4i32:{ *:[v4i32] }:$rsrc, i32:{ *:[i32] }:$vindex, 0:{ *:[i32] }, (BUFSOffset:{ *:[i32] } i32:{ *:[i32] }:$soffset), (timm:{ *:[i32] }):$offset, (timm:{ *:[i32] }):$auxiliary, (timm:{ *:[i1] }))  =>  (BUFFER_LOAD_FORMAT_XYZW_VBUFFER_IDXEN:{ *:[v4i32] } VGPR_32:{ *:[i32] }:$vindex, SReg_128:{ *:[v4i32] }:$rsrc, SCSrc_b32:{ *:[i32] }:$soffset, (timm:{ *:[i32] }):$offset, (extract_cpol:{ *:[i32] } ?:{ *:[i32] }:$auxiliary), (extract_swz:{ *:[i1] } ?:{ *:[i32] }:$auxiliary))
        GIR_BuildMI, /*InsnID*/0, /*Opcode*/GIMT_Encode2(AMDGPU::BUFFER_LOAD_FORMAT_XYZW_VBUFFER_IDXEN),
        GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/0, // DstI[vdata]
        GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/2, // vindex
        GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/1, // rsrc
        GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/0, // soffset
        GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/5, // offset
        GIR_CustomOperandRenderer, /*InsnID*/0, /*OldInsnID*/0, /*OpIdx*/6, /*OperandRenderer*/GIMT_Encode2(GICR_renderExtractCPol), // auxiliary
        GIR_CustomOperandRenderer, /*InsnID*/0, /*OldInsnID*/0, /*OpIdx*/6, /*OperandRenderer*/GIMT_Encode2(GICR_renderExtractSWZ), // auxiliary
        GIR_MergeMemOperands, /*InsnID*/0, /*NumInsns*/1, /*MergeInsnID's*/0,
        GIR_ConstrainSelectedInstOperands, /*InsnID*/0,
        GIR_EraseFromParent, /*InsnID*/0,
        // GIR_Coverage, 3975,
        GIR_Done,
      // Label 6568: @482344
      GIM_Try, /*On fail goto*//*Label 6569*/ GIMT_Encode4(482454), // Rule ID 3964 //
        GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasUnrestrictedSOffset),
        // MIs[0] offset
        GIM_CheckIsImm, /*MI*/0, /*Op*/5,
        // MIs[0] auxiliary
        GIM_CheckIsImm, /*MI*/0, /*Op*/6,
        // MIs[0] Operand 7
        GIM_CheckIsImm, /*MI*/0, /*Op*/7,
        GIM_CheckComplexPattern, /*MI*/0, /*Op*/4, /*Renderer*/GIMT_Encode2(0), GIMT_Encode2(GICP_gi_buf_soffset),
        // (SIbuffer_load_format:{ *:[v4f32] } v4i32:{ *:[v4i32] }:$rsrc, i32:{ *:[i32] }:$vindex, i32:{ *:[i32] }:$voffset, (BUFSOffset:{ *:[i32] } i32:{ *:[i32] }:$soffset), (timm:{ *:[i32] }):$offset, (timm:{ *:[i32] }):$auxiliary, (timm:{ *:[i1] }))  =>  (BUFFER_LOAD_FORMAT_XYZW_BOTHEN:{ *:[v4f32] } (REG_SEQUENCE:{ *:[i64] } VReg_64:{ *:[i32] }, VGPR_32:{ *:[i32] }:$vindex, sub0:{ *:[i32] }, VGPR_32:{ *:[i32] }:$voffset, sub1:{ *:[i32] }), SReg_128:{ *:[v4i32] }:$rsrc, SCSrc_b32:{ *:[i32] }:$soffset, (timm:{ *:[i32] }):$offset, (extract_cpol:{ *:[i32] } ?:{ *:[i32] }:$auxiliary), (extract_swz:{ *:[i1] } ?:{ *:[i32] }:$auxiliary))
        GIR_MakeTempReg, /*TempRegID*/0, /*TypeID*/GILLT_s64,
        GIR_BuildMI, /*InsnID*/1, /*Opcode*/GIMT_Encode2(TargetOpcode::REG_SEQUENCE),
        GIR_AddTempRegister, /*InsnID*/1, /*TempRegID*/0, /*TempRegFlags*/GIMT_Encode2(RegState::Define),
        GIR_Copy, /*NewInsnID*/1, /*OldInsnID*/0, /*OpIdx*/2, // vindex
        GIR_AddImm8, /*InsnID*/1, /*SubRegIndex*/3,
        GIR_Copy, /*NewInsnID*/1, /*OldInsnID*/0, /*OpIdx*/3, // voffset
        GIR_AddImm8, /*InsnID*/1, /*SubRegIndex*/11,
        GIR_ConstrainOperandRC, /*InsnID*/1, /*Op*/0, GIMT_Encode2(AMDGPU::VReg_64RegClassID),
        GIR_ConstrainOperandRC, /*InsnID*/1, /*Op*/1, GIMT_Encode2(AMDGPU::VGPR_32RegClassID),
        GIR_ConstrainOperandRC, /*InsnID*/1, /*Op*/3, GIMT_Encode2(AMDGPU::VGPR_32RegClassID),
        GIR_BuildMI, /*InsnID*/0, /*Opcode*/GIMT_Encode2(AMDGPU::BUFFER_LOAD_FORMAT_XYZW_BOTHEN),
        GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/0, // DstI[vdata]
        GIR_AddSimpleTempRegister, /*InsnID*/0, /*TempRegID*/0,
        GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/1, // rsrc
        GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/0, // soffset
        GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/5, // offset
        GIR_CustomOperandRenderer, /*InsnID*/0, /*OldInsnID*/0, /*OpIdx*/6, /*OperandRenderer*/GIMT_Encode2(GICR_renderExtractCPol), // auxiliary
        GIR_CustomOperandRenderer, /*InsnID*/0, /*OldInsnID*/0, /*OpIdx*/6, /*OperandRenderer*/GIMT_Encode2(GICR_renderExtractSWZ), // auxiliary
        GIR_MergeMemOperands, /*InsnID*/0, /*NumInsns*/1, /*MergeInsnID's*/0,
        GIR_ConstrainSelectedInstOperands, /*InsnID*/0,
        GIR_EraseFromParent, /*InsnID*/0,
        // GIR_Coverage, 3964,
        GIR_Done,
      // Label 6569: @482454
      GIM_Try, /*On fail goto*//*Label 6570*/ GIMT_Encode4(482561), // Rule ID 3968 //
        // MIs[0] offset
        GIM_CheckIsImm, /*MI*/0, /*Op*/5,
        // MIs[0] auxiliary
        GIM_CheckIsImm, /*MI*/0, /*Op*/6,
        // MIs[0] Operand 7
        GIM_CheckIsImm, /*MI*/0, /*Op*/7,
        GIM_CheckComplexPattern, /*MI*/0, /*Op*/4, /*Renderer*/GIMT_Encode2(0), GIMT_Encode2(GICP_gi_buf_soffset),
        // (SIbuffer_load_format:{ *:[v4f32] } v4i32:{ *:[v4i32] }:$rsrc, i32:{ *:[i32] }:$vindex, i32:{ *:[i32] }:$voffset, (BUFSOffset:{ *:[i32] } i32:{ *:[i32] }:$soffset), (timm:{ *:[i32] }):$offset, (timm:{ *:[i32] }):$auxiliary, (timm:{ *:[i1] }))  =>  (BUFFER_LOAD_FORMAT_XYZW_VBUFFER_BOTHEN:{ *:[v4f32] } (REG_SEQUENCE:{ *:[i64] } VReg_64:{ *:[i32] }, VGPR_32:{ *:[i32] }:$vindex, sub0:{ *:[i32] }, VGPR_32:{ *:[i32] }:$voffset, sub1:{ *:[i32] }), SReg_128:{ *:[v4i32] }:$rsrc, SCSrc_b32:{ *:[i32] }:$soffset, (timm:{ *:[i32] }):$offset, (extract_cpol:{ *:[i32] } ?:{ *:[i32] }:$auxiliary), (extract_swz:{ *:[i1] } ?:{ *:[i32] }:$auxiliary))
        GIR_MakeTempReg, /*TempRegID*/0, /*TypeID*/GILLT_s64,
        GIR_BuildMI, /*InsnID*/1, /*Opcode*/GIMT_Encode2(TargetOpcode::REG_SEQUENCE),
        GIR_AddTempRegister, /*InsnID*/1, /*TempRegID*/0, /*TempRegFlags*/GIMT_Encode2(RegState::Define),
        GIR_Copy, /*NewInsnID*/1, /*OldInsnID*/0, /*OpIdx*/2, // vindex
        GIR_AddImm8, /*InsnID*/1, /*SubRegIndex*/3,
        GIR_Copy, /*NewInsnID*/1, /*OldInsnID*/0, /*OpIdx*/3, // voffset
        GIR_AddImm8, /*InsnID*/1, /*SubRegIndex*/11,
        GIR_ConstrainOperandRC, /*InsnID*/1, /*Op*/0, GIMT_Encode2(AMDGPU::VReg_64RegClassID),
        GIR_ConstrainOperandRC, /*InsnID*/1, /*Op*/1, GIMT_Encode2(AMDGPU::VGPR_32RegClassID),
        GIR_ConstrainOperandRC, /*InsnID*/1, /*Op*/3, GIMT_Encode2(AMDGPU::VGPR_32RegClassID),
        GIR_BuildMI, /*InsnID*/0, /*Opcode*/GIMT_Encode2(AMDGPU::BUFFER_LOAD_FORMAT_XYZW_VBUFFER_BOTHEN),
        GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/0, // DstI[vdata]
        GIR_AddSimpleTempRegister, /*InsnID*/0, /*TempRegID*/0,
        GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/1, // rsrc
        GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/0, // soffset
        GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/5, // offset
        GIR_CustomOperandRenderer, /*InsnID*/0, /*OldInsnID*/0, /*OpIdx*/6, /*OperandRenderer*/GIMT_Encode2(GICR_renderExtractCPol), // auxiliary
        GIR_CustomOperandRenderer, /*InsnID*/0, /*OldInsnID*/0, /*OpIdx*/6, /*OperandRenderer*/GIMT_Encode2(GICR_renderExtractSWZ), // auxiliary
        GIR_MergeMemOperands, /*InsnID*/0, /*NumInsns*/1, /*MergeInsnID's*/0,
        GIR_ConstrainSelectedInstOperands, /*InsnID*/0,
        GIR_EraseFromParent, /*InsnID*/0,
        // GIR_Coverage, 3968,
        GIR_Done,
      // Label 6570: @482561
      GIM_Try, /*On fail goto*//*Label 6571*/ GIMT_Encode4(482671), // Rule ID 3972 //
        GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasUnrestrictedSOffset),
        // MIs[0] offset
        GIM_CheckIsImm, /*MI*/0, /*Op*/5,
        // MIs[0] auxiliary
        GIM_CheckIsImm, /*MI*/0, /*Op*/6,
        // MIs[0] Operand 7
        GIM_CheckIsImm, /*MI*/0, /*Op*/7,
        GIM_CheckComplexPattern, /*MI*/0, /*Op*/4, /*Renderer*/GIMT_Encode2(0), GIMT_Encode2(GICP_gi_buf_soffset),
        // (SIbuffer_load_format:{ *:[v4i32] } v4i32:{ *:[v4i32] }:$rsrc, i32:{ *:[i32] }:$vindex, i32:{ *:[i32] }:$voffset, (BUFSOffset:{ *:[i32] } i32:{ *:[i32] }:$soffset), (timm:{ *:[i32] }):$offset, (timm:{ *:[i32] }):$auxiliary, (timm:{ *:[i1] }))  =>  (BUFFER_LOAD_FORMAT_XYZW_BOTHEN:{ *:[v4i32] } (REG_SEQUENCE:{ *:[i64] } VReg_64:{ *:[i32] }, VGPR_32:{ *:[i32] }:$vindex, sub0:{ *:[i32] }, VGPR_32:{ *:[i32] }:$voffset, sub1:{ *:[i32] }), SReg_128:{ *:[v4i32] }:$rsrc, SCSrc_b32:{ *:[i32] }:$soffset, (timm:{ *:[i32] }):$offset, (extract_cpol:{ *:[i32] } ?:{ *:[i32] }:$auxiliary), (extract_swz:{ *:[i1] } ?:{ *:[i32] }:$auxiliary))
        GIR_MakeTempReg, /*TempRegID*/0, /*TypeID*/GILLT_s64,
        GIR_BuildMI, /*InsnID*/1, /*Opcode*/GIMT_Encode2(TargetOpcode::REG_SEQUENCE),
        GIR_AddTempRegister, /*InsnID*/1, /*TempRegID*/0, /*TempRegFlags*/GIMT_Encode2(RegState::Define),
        GIR_Copy, /*NewInsnID*/1, /*OldInsnID*/0, /*OpIdx*/2, // vindex
        GIR_AddImm8, /*InsnID*/1, /*SubRegIndex*/3,
        GIR_Copy, /*NewInsnID*/1, /*OldInsnID*/0, /*OpIdx*/3, // voffset
        GIR_AddImm8, /*InsnID*/1, /*SubRegIndex*/11,
        GIR_ConstrainOperandRC, /*InsnID*/1, /*Op*/0, GIMT_Encode2(AMDGPU::VReg_64RegClassID),
        GIR_ConstrainOperandRC, /*InsnID*/1, /*Op*/1, GIMT_Encode2(AMDGPU::VGPR_32RegClassID),
        GIR_ConstrainOperandRC, /*InsnID*/1, /*Op*/3, GIMT_Encode2(AMDGPU::VGPR_32RegClassID),
        GIR_BuildMI, /*InsnID*/0, /*Opcode*/GIMT_Encode2(AMDGPU::BUFFER_LOAD_FORMAT_XYZW_BOTHEN),
        GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/0, // DstI[vdata]
        GIR_AddSimpleTempRegister, /*InsnID*/0, /*TempRegID*/0,
        GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/1, // rsrc
        GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/0, // soffset
        GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/5, // offset
        GIR_CustomOperandRenderer, /*InsnID*/0, /*OldInsnID*/0, /*OpIdx*/6, /*OperandRenderer*/GIMT_Encode2(GICR_renderExtractCPol), // auxiliary
        GIR_CustomOperandRenderer, /*InsnID*/0, /*OldInsnID*/0, /*OpIdx*/6, /*OperandRenderer*/GIMT_Encode2(GICR_renderExtractSWZ), // auxiliary
        GIR_MergeMemOperands, /*InsnID*/0, /*NumInsns*/1, /*MergeInsnID's*/0,
        GIR_ConstrainSelectedInstOperands, /*InsnID*/0,
        GIR_EraseFromParent, /*InsnID*/0,
        // GIR_Coverage, 3972,
        GIR_Done,
      // Label 6571: @482671
      GIM_Try, /*On fail goto*//*Label 6572*/ GIMT_Encode4(482778), // Rule ID 3976 //
        // MIs[0] offset
        GIM_CheckIsImm, /*MI*/0, /*Op*/5,
        // MIs[0] auxiliary
        GIM_CheckIsImm, /*MI*/0, /*Op*/6,
        // MIs[0] Operand 7
        GIM_CheckIsImm, /*MI*/0, /*Op*/7,
        GIM_CheckComplexPattern, /*MI*/0, /*Op*/4, /*Renderer*/GIMT_Encode2(0), GIMT_Encode2(GICP_gi_buf_soffset),
        // (SIbuffer_load_format:{ *:[v4i32] } v4i32:{ *:[v4i32] }:$rsrc, i32:{ *:[i32] }:$vindex, i32:{ *:[i32] }:$voffset, (BUFSOffset:{ *:[i32] } i32:{ *:[i32] }:$soffset), (timm:{ *:[i32] }):$offset, (timm:{ *:[i32] }):$auxiliary, (timm:{ *:[i1] }))  =>  (BUFFER_LOAD_FORMAT_XYZW_VBUFFER_BOTHEN:{ *:[v4i32] } (REG_SEQUENCE:{ *:[i64] } VReg_64:{ *:[i32] }, VGPR_32:{ *:[i32] }:$vindex, sub0:{ *:[i32] }, VGPR_32:{ *:[i32] }:$voffset, sub1:{ *:[i32] }), SReg_128:{ *:[v4i32] }:$rsrc, SCSrc_b32:{ *:[i32] }:$soffset, (timm:{ *:[i32] }):$offset, (extract_cpol:{ *:[i32] } ?:{ *:[i32] }:$auxiliary), (extract_swz:{ *:[i1] } ?:{ *:[i32] }:$auxiliary))
        GIR_MakeTempReg, /*TempRegID*/0, /*TypeID*/GILLT_s64,
        GIR_BuildMI, /*InsnID*/1, /*Opcode*/GIMT_Encode2(TargetOpcode::REG_SEQUENCE),
        GIR_AddTempRegister, /*InsnID*/1, /*TempRegID*/0, /*TempRegFlags*/GIMT_Encode2(RegState::Define),
        GIR_Copy, /*NewInsnID*/1, /*OldInsnID*/0, /*OpIdx*/2, // vindex
        GIR_AddImm8, /*InsnID*/1, /*SubRegIndex*/3,
        GIR_Copy, /*NewInsnID*/1, /*OldInsnID*/0, /*OpIdx*/3, // voffset
        GIR_AddImm8, /*InsnID*/1, /*SubRegIndex*/11,
        GIR_ConstrainOperandRC, /*InsnID*/1, /*Op*/0, GIMT_Encode2(AMDGPU::VReg_64RegClassID),
        GIR_ConstrainOperandRC, /*InsnID*/1, /*Op*/1, GIMT_Encode2(AMDGPU::VGPR_32RegClassID),
        GIR_ConstrainOperandRC, /*InsnID*/1, /*Op*/3, GIMT_Encode2(AMDGPU::VGPR_32RegClassID),
        GIR_BuildMI, /*InsnID*/0, /*Opcode*/GIMT_Encode2(AMDGPU::BUFFER_LOAD_FORMAT_XYZW_VBUFFER_BOTHEN),
        GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/0, // DstI[vdata]
        GIR_AddSimpleTempRegister, /*InsnID*/0, /*TempRegID*/0,
        GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/1, // rsrc
        GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/0, // soffset
        GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/5, // offset
        GIR_CustomOperandRenderer, /*InsnID*/0, /*OldInsnID*/0, /*OpIdx*/6, /*OperandRenderer*/GIMT_Encode2(GICR_renderExtractCPol), // auxiliary
        GIR_CustomOperandRenderer, /*InsnID*/0, /*OldInsnID*/0, /*OpIdx*/6, /*OperandRenderer*/GIMT_Encode2(GICR_renderExtractSWZ), // auxiliary
        GIR_MergeMemOperands, /*InsnID*/0, /*NumInsns*/1, /*MergeInsnID's*/0,
        GIR_ConstrainSelectedInstOperands, /*InsnID*/0,
        GIR_EraseFromParent, /*InsnID*/0,
        // GIR_Coverage, 3976,
        GIR_Done,
      // Label 6572: @482778
      GIM_Reject,
    // Label 6556: @482779
    GIM_Reject,
    // Label 6504: @482780
    GIM_Reject,
    // Label 126: @482781
    GIM_SwitchType, /*MI*/0, /*Op*/0, /*[*/GIMT_Encode2(8), GIMT_Encode2(18), /*)*//*default:*//*Label 6580*/ GIMT_Encode4(491647),
    /*GILLT_s16*//*Label 6573*/ GIMT_Encode4(482832),
    /*GILLT_s32*//*Label 6574*/ GIMT_Encode4(484948), GIMT_Encode4(0),
    /*GILLT_v2s16*//*Label 6575*/ GIMT_Encode4(486020),
    /*GILLT_v2s32*//*Label 6576*/ GIMT_Encode4(487440), GIMT_Encode4(0),
    /*GILLT_v3s32*//*Label 6577*/ GIMT_Encode4(487816), GIMT_Encode4(0),
    /*GILLT_v4s16*//*Label 6578*/ GIMT_Encode4(488192),
    /*GILLT_v4s32*//*Label 6579*/ GIMT_Encode4(491271),
    // Label 6573: @482832
    GIM_Try, /*On fail goto*//*Label 6581*/ GIMT_Encode4(484947),
      GIM_CheckType, /*MI*/0, /*Op*/1, /*Type*/GILLT_v4s32,
      GIM_CheckType, /*MI*/0, /*Op*/2, /*Type*/GILLT_s32,
      GIM_CheckType, /*MI*/0, /*Op*/3, /*Type*/GILLT_s32,
      GIM_CheckType, /*MI*/0, /*Op*/4, /*Type*/GILLT_s32,
      GIM_CheckRegBankForClass, /*MI*/0, /*Op*/0, /*RC*/GIMT_Encode2(AMDGPU::AV_32RegClassID),
      GIM_Try, /*On fail goto*//*Label 6582*/ GIMT_Encode4(482940), // Rule ID 4009 //
        GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasUnpackedD16VMem),
        GIM_CheckConstantInt8, /*MI*/0, /*Op*/2, 0,
        GIM_CheckConstantInt8, /*MI*/0, /*Op*/3, 0,
        // MIs[0] offset
        GIM_CheckIsImm, /*MI*/0, /*Op*/5,
        // MIs[0] auxiliary
        GIM_CheckIsImm, /*MI*/0, /*Op*/6,
        // MIs[0] Operand 7
        GIM_CheckLiteralInt, /*MI*/0, /*Op*/7, GIMT_Encode8(0),
        GIM_CheckComplexPattern, /*MI*/0, /*Op*/4, /*Renderer*/GIMT_Encode2(0), GIMT_Encode2(GICP_gi_buf_soffset),
        // (SIbuffer_load_format_d16:{ *:[f16] } v4i32:{ *:[v4i32] }:$rsrc, 0:{ *:[i32] }, 0:{ *:[i32] }, (BUFSOffset:{ *:[i32] } i32:{ *:[i32] }:$soffset), (timm:{ *:[i32] }):$offset, (timm:{ *:[i32] }):$auxiliary, 0:{ *:[i1] })  =>  (BUFFER_LOAD_FORMAT_D16_X_gfx80_OFFSET:{ *:[f16] } SReg_128:{ *:[v4i32] }:$rsrc, SCSrc_b32:{ *:[i32] }:$soffset, (timm:{ *:[i32] }):$offset, (extract_cpol:{ *:[i32] } ?:{ *:[i32] }:$auxiliary), (extract_swz:{ *:[i1] } ?:{ *:[i32] }:$auxiliary))
        GIR_BuildMI, /*InsnID*/0, /*Opcode*/GIMT_Encode2(AMDGPU::BUFFER_LOAD_FORMAT_D16_X_gfx80_OFFSET),
        GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/0, // DstI[vdata]
        GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/1, // rsrc
        GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/0, // soffset
        GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/5, // offset
        GIR_CustomOperandRenderer, /*InsnID*/0, /*OldInsnID*/0, /*OpIdx*/6, /*OperandRenderer*/GIMT_Encode2(GICR_renderExtractCPol), // auxiliary
        GIR_CustomOperandRenderer, /*InsnID*/0, /*OldInsnID*/0, /*OpIdx*/6, /*OperandRenderer*/GIMT_Encode2(GICR_renderExtractSWZ), // auxiliary
        GIR_MergeMemOperands, /*InsnID*/0, /*NumInsns*/1, /*MergeInsnID's*/0,
        GIR_ConstrainSelectedInstOperands, /*InsnID*/0,
        GIR_EraseFromParent, /*InsnID*/0,
        // GIR_Coverage, 4009,
        GIR_Done,
      // Label 6582: @482940
      GIM_Try, /*On fail goto*//*Label 6583*/ GIMT_Encode4(483022), // Rule ID 4013 //
        GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasUnpackedD16VMem),
        GIM_CheckConstantInt8, /*MI*/0, /*Op*/2, 0,
        GIM_CheckConstantInt8, /*MI*/0, /*Op*/3, 0,
        // MIs[0] offset
        GIM_CheckIsImm, /*MI*/0, /*Op*/5,
        // MIs[0] auxiliary
        GIM_CheckIsImm, /*MI*/0, /*Op*/6,
        // MIs[0] Operand 7
        GIM_CheckLiteralInt, /*MI*/0, /*Op*/7, GIMT_Encode8(0),
        GIM_CheckComplexPattern, /*MI*/0, /*Op*/4, /*Renderer*/GIMT_Encode2(0), GIMT_Encode2(GICP_gi_buf_soffset),
        // (SIbuffer_load_format_d16:{ *:[i16] } v4i32:{ *:[v4i32] }:$rsrc, 0:{ *:[i32] }, 0:{ *:[i32] }, (BUFSOffset:{ *:[i32] } i32:{ *:[i32] }:$soffset), (timm:{ *:[i32] }):$offset, (timm:{ *:[i32] }):$auxiliary, 0:{ *:[i1] })  =>  (BUFFER_LOAD_FORMAT_D16_X_gfx80_OFFSET:{ *:[i16] } SReg_128:{ *:[v4i32] }:$rsrc, SCSrc_b32:{ *:[i32] }:$soffset, (timm:{ *:[i32] }):$offset, (extract_cpol:{ *:[i32] } ?:{ *:[i32] }:$auxiliary), (extract_swz:{ *:[i1] } ?:{ *:[i32] }:$auxiliary))
        GIR_BuildMI, /*InsnID*/0, /*Opcode*/GIMT_Encode2(AMDGPU::BUFFER_LOAD_FORMAT_D16_X_gfx80_OFFSET),
        GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/0, // DstI[vdata]
        GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/1, // rsrc
        GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/0, // soffset
        GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/5, // offset
        GIR_CustomOperandRenderer, /*InsnID*/0, /*OldInsnID*/0, /*OpIdx*/6, /*OperandRenderer*/GIMT_Encode2(GICR_renderExtractCPol), // auxiliary
        GIR_CustomOperandRenderer, /*InsnID*/0, /*OldInsnID*/0, /*OpIdx*/6, /*OperandRenderer*/GIMT_Encode2(GICR_renderExtractSWZ), // auxiliary
        GIR_MergeMemOperands, /*InsnID*/0, /*NumInsns*/1, /*MergeInsnID's*/0,
        GIR_ConstrainSelectedInstOperands, /*InsnID*/0,
        GIR_EraseFromParent, /*InsnID*/0,
        // GIR_Coverage, 4013,
        GIR_Done,
      // Label 6583: @483022
      GIM_Try, /*On fail goto*//*Label 6584*/ GIMT_Encode4(483104), // Rule ID 4033 //
        GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasPackedD16VMem_HasUnrestrictedSOffset),
        GIM_CheckConstantInt8, /*MI*/0, /*Op*/2, 0,
        GIM_CheckConstantInt8, /*MI*/0, /*Op*/3, 0,
        // MIs[0] offset
        GIM_CheckIsImm, /*MI*/0, /*Op*/5,
        // MIs[0] auxiliary
        GIM_CheckIsImm, /*MI*/0, /*Op*/6,
        // MIs[0] Operand 7
        GIM_CheckLiteralInt, /*MI*/0, /*Op*/7, GIMT_Encode8(0),
        GIM_CheckComplexPattern, /*MI*/0, /*Op*/4, /*Renderer*/GIMT_Encode2(0), GIMT_Encode2(GICP_gi_buf_soffset),
        // (SIbuffer_load_format_d16:{ *:[f16] } v4i32:{ *:[v4i32] }:$rsrc, 0:{ *:[i32] }, 0:{ *:[i32] }, (BUFSOffset:{ *:[i32] } i32:{ *:[i32] }:$soffset), (timm:{ *:[i32] }):$offset, (timm:{ *:[i32] }):$auxiliary, 0:{ *:[i1] })  =>  (BUFFER_LOAD_FORMAT_D16_X_OFFSET:{ *:[f16] } SReg_128:{ *:[v4i32] }:$rsrc, SCSrc_b32:{ *:[i32] }:$soffset, (timm:{ *:[i32] }):$offset, (extract_cpol:{ *:[i32] } ?:{ *:[i32] }:$auxiliary), (extract_swz:{ *:[i1] } ?:{ *:[i32] }:$auxiliary))
        GIR_BuildMI, /*InsnID*/0, /*Opcode*/GIMT_Encode2(AMDGPU::BUFFER_LOAD_FORMAT_D16_X_OFFSET),
        GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/0, // DstI[vdata]
        GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/1, // rsrc
        GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/0, // soffset
        GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/5, // offset
        GIR_CustomOperandRenderer, /*InsnID*/0, /*OldInsnID*/0, /*OpIdx*/6, /*OperandRenderer*/GIMT_Encode2(GICR_renderExtractCPol), // auxiliary
        GIR_CustomOperandRenderer, /*InsnID*/0, /*OldInsnID*/0, /*OpIdx*/6, /*OperandRenderer*/GIMT_Encode2(GICR_renderExtractSWZ), // auxiliary
        GIR_MergeMemOperands, /*InsnID*/0, /*NumInsns*/1, /*MergeInsnID's*/0,
        GIR_ConstrainSelectedInstOperands, /*InsnID*/0,
        GIR_EraseFromParent, /*InsnID*/0,
        // GIR_Coverage, 4033,
        GIR_Done,
      // Label 6584: @483104
      GIM_Try, /*On fail goto*//*Label 6585*/ GIMT_Encode4(483186), // Rule ID 4037 //
        GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasPackedD16VMem),
        GIM_CheckConstantInt8, /*MI*/0, /*Op*/2, 0,
        GIM_CheckConstantInt8, /*MI*/0, /*Op*/3, 0,
        // MIs[0] offset
        GIM_CheckIsImm, /*MI*/0, /*Op*/5,
        // MIs[0] auxiliary
        GIM_CheckIsImm, /*MI*/0, /*Op*/6,
        // MIs[0] Operand 7
        GIM_CheckLiteralInt, /*MI*/0, /*Op*/7, GIMT_Encode8(0),
        GIM_CheckComplexPattern, /*MI*/0, /*Op*/4, /*Renderer*/GIMT_Encode2(0), GIMT_Encode2(GICP_gi_buf_soffset),
        // (SIbuffer_load_format_d16:{ *:[f16] } v4i32:{ *:[v4i32] }:$rsrc, 0:{ *:[i32] }, 0:{ *:[i32] }, (BUFSOffset:{ *:[i32] } i32:{ *:[i32] }:$soffset), (timm:{ *:[i32] }):$offset, (timm:{ *:[i32] }):$auxiliary, 0:{ *:[i1] })  =>  (BUFFER_LOAD_FORMAT_D16_X_VBUFFER_OFFSET:{ *:[f16] } SReg_128:{ *:[v4i32] }:$rsrc, SCSrc_b32:{ *:[i32] }:$soffset, (timm:{ *:[i32] }):$offset, (extract_cpol:{ *:[i32] } ?:{ *:[i32] }:$auxiliary), (extract_swz:{ *:[i1] } ?:{ *:[i32] }:$auxiliary))
        GIR_BuildMI, /*InsnID*/0, /*Opcode*/GIMT_Encode2(AMDGPU::BUFFER_LOAD_FORMAT_D16_X_VBUFFER_OFFSET),
        GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/0, // DstI[vdata]
        GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/1, // rsrc
        GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/0, // soffset
        GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/5, // offset
        GIR_CustomOperandRenderer, /*InsnID*/0, /*OldInsnID*/0, /*OpIdx*/6, /*OperandRenderer*/GIMT_Encode2(GICR_renderExtractCPol), // auxiliary
        GIR_CustomOperandRenderer, /*InsnID*/0, /*OldInsnID*/0, /*OpIdx*/6, /*OperandRenderer*/GIMT_Encode2(GICR_renderExtractSWZ), // auxiliary
        GIR_MergeMemOperands, /*InsnID*/0, /*NumInsns*/1, /*MergeInsnID's*/0,
        GIR_ConstrainSelectedInstOperands, /*InsnID*/0,
        GIR_EraseFromParent, /*InsnID*/0,
        // GIR_Coverage, 4037,
        GIR_Done,
      // Label 6585: @483186
      GIM_Try, /*On fail goto*//*Label 6586*/ GIMT_Encode4(483268), // Rule ID 4041 //
        GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasPackedD16VMem_HasUnrestrictedSOffset),
        GIM_CheckConstantInt8, /*MI*/0, /*Op*/2, 0,
        GIM_CheckConstantInt8, /*MI*/0, /*Op*/3, 0,
        // MIs[0] offset
        GIM_CheckIsImm, /*MI*/0, /*Op*/5,
        // MIs[0] auxiliary
        GIM_CheckIsImm, /*MI*/0, /*Op*/6,
        // MIs[0] Operand 7
        GIM_CheckLiteralInt, /*MI*/0, /*Op*/7, GIMT_Encode8(0),
        GIM_CheckComplexPattern, /*MI*/0, /*Op*/4, /*Renderer*/GIMT_Encode2(0), GIMT_Encode2(GICP_gi_buf_soffset),
        // (SIbuffer_load_format_d16:{ *:[i16] } v4i32:{ *:[v4i32] }:$rsrc, 0:{ *:[i32] }, 0:{ *:[i32] }, (BUFSOffset:{ *:[i32] } i32:{ *:[i32] }:$soffset), (timm:{ *:[i32] }):$offset, (timm:{ *:[i32] }):$auxiliary, 0:{ *:[i1] })  =>  (BUFFER_LOAD_FORMAT_D16_X_OFFSET:{ *:[i16] } SReg_128:{ *:[v4i32] }:$rsrc, SCSrc_b32:{ *:[i32] }:$soffset, (timm:{ *:[i32] }):$offset, (extract_cpol:{ *:[i32] } ?:{ *:[i32] }:$auxiliary), (extract_swz:{ *:[i1] } ?:{ *:[i32] }:$auxiliary))
        GIR_BuildMI, /*InsnID*/0, /*Opcode*/GIMT_Encode2(AMDGPU::BUFFER_LOAD_FORMAT_D16_X_OFFSET),
        GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/0, // DstI[vdata]
        GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/1, // rsrc
        GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/0, // soffset
        GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/5, // offset
        GIR_CustomOperandRenderer, /*InsnID*/0, /*OldInsnID*/0, /*OpIdx*/6, /*OperandRenderer*/GIMT_Encode2(GICR_renderExtractCPol), // auxiliary
        GIR_CustomOperandRenderer, /*InsnID*/0, /*OldInsnID*/0, /*OpIdx*/6, /*OperandRenderer*/GIMT_Encode2(GICR_renderExtractSWZ), // auxiliary
        GIR_MergeMemOperands, /*InsnID*/0, /*NumInsns*/1, /*MergeInsnID's*/0,
        GIR_ConstrainSelectedInstOperands, /*InsnID*/0,
        GIR_EraseFromParent, /*InsnID*/0,
        // GIR_Coverage, 4041,
        GIR_Done,
      // Label 6586: @483268
      GIM_Try, /*On fail goto*//*Label 6587*/ GIMT_Encode4(483350), // Rule ID 4045 //
        GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasPackedD16VMem),
        GIM_CheckConstantInt8, /*MI*/0, /*Op*/2, 0,
        GIM_CheckConstantInt8, /*MI*/0, /*Op*/3, 0,
        // MIs[0] offset
        GIM_CheckIsImm, /*MI*/0, /*Op*/5,
        // MIs[0] auxiliary
        GIM_CheckIsImm, /*MI*/0, /*Op*/6,
        // MIs[0] Operand 7
        GIM_CheckLiteralInt, /*MI*/0, /*Op*/7, GIMT_Encode8(0),
        GIM_CheckComplexPattern, /*MI*/0, /*Op*/4, /*Renderer*/GIMT_Encode2(0), GIMT_Encode2(GICP_gi_buf_soffset),
        // (SIbuffer_load_format_d16:{ *:[i16] } v4i32:{ *:[v4i32] }:$rsrc, 0:{ *:[i32] }, 0:{ *:[i32] }, (BUFSOffset:{ *:[i32] } i32:{ *:[i32] }:$soffset), (timm:{ *:[i32] }):$offset, (timm:{ *:[i32] }):$auxiliary, 0:{ *:[i1] })  =>  (BUFFER_LOAD_FORMAT_D16_X_VBUFFER_OFFSET:{ *:[i16] } SReg_128:{ *:[v4i32] }:$rsrc, SCSrc_b32:{ *:[i32] }:$soffset, (timm:{ *:[i32] }):$offset, (extract_cpol:{ *:[i32] } ?:{ *:[i32] }:$auxiliary), (extract_swz:{ *:[i1] } ?:{ *:[i32] }:$auxiliary))
        GIR_BuildMI, /*InsnID*/0, /*Opcode*/GIMT_Encode2(AMDGPU::BUFFER_LOAD_FORMAT_D16_X_VBUFFER_OFFSET),
        GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/0, // DstI[vdata]
        GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/1, // rsrc
        GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/0, // soffset
        GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/5, // offset
        GIR_CustomOperandRenderer, /*InsnID*/0, /*OldInsnID*/0, /*OpIdx*/6, /*OperandRenderer*/GIMT_Encode2(GICR_renderExtractCPol), // auxiliary
        GIR_CustomOperandRenderer, /*InsnID*/0, /*OldInsnID*/0, /*OpIdx*/6, /*OperandRenderer*/GIMT_Encode2(GICR_renderExtractSWZ), // auxiliary
        GIR_MergeMemOperands, /*InsnID*/0, /*NumInsns*/1, /*MergeInsnID's*/0,
        GIR_ConstrainSelectedInstOperands, /*InsnID*/0,
        GIR_EraseFromParent, /*InsnID*/0,
        // GIR_Coverage, 4045,
        GIR_Done,
      // Label 6587: @483350
      GIM_Try, /*On fail goto*//*Label 6588*/ GIMT_Encode4(483432), // Rule ID 4010 //
        GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasUnpackedD16VMem),
        GIM_CheckConstantInt8, /*MI*/0, /*Op*/2, 0,
        // MIs[0] offset
        GIM_CheckIsImm, /*MI*/0, /*Op*/5,
        // MIs[0] auxiliary
        GIM_CheckIsImm, /*MI*/0, /*Op*/6,
        // MIs[0] Operand 7
        GIM_CheckLiteralInt, /*MI*/0, /*Op*/7, GIMT_Encode8(0),
        GIM_CheckComplexPattern, /*MI*/0, /*Op*/4, /*Renderer*/GIMT_Encode2(0), GIMT_Encode2(GICP_gi_buf_soffset),
        // (SIbuffer_load_format_d16:{ *:[f16] } v4i32:{ *:[v4i32] }:$rsrc, 0:{ *:[i32] }, i32:{ *:[i32] }:$voffset, (BUFSOffset:{ *:[i32] } i32:{ *:[i32] }:$soffset), (timm:{ *:[i32] }):$offset, (timm:{ *:[i32] }):$auxiliary, 0:{ *:[i1] })  =>  (BUFFER_LOAD_FORMAT_D16_X_gfx80_OFFEN:{ *:[f16] } VGPR_32:{ *:[i32] }:$voffset, SReg_128:{ *:[v4i32] }:$rsrc, SCSrc_b32:{ *:[i32] }:$soffset, (timm:{ *:[i32] }):$offset, (extract_cpol:{ *:[i32] } ?:{ *:[i32] }:$auxiliary), (extract_swz:{ *:[i1] } ?:{ *:[i32] }:$auxiliary))
        GIR_BuildMI, /*InsnID*/0, /*Opcode*/GIMT_Encode2(AMDGPU::BUFFER_LOAD_FORMAT_D16_X_gfx80_OFFEN),
        GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/0, // DstI[vdata]
        GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/3, // voffset
        GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/1, // rsrc
        GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/0, // soffset
        GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/5, // offset
        GIR_CustomOperandRenderer, /*InsnID*/0, /*OldInsnID*/0, /*OpIdx*/6, /*OperandRenderer*/GIMT_Encode2(GICR_renderExtractCPol), // auxiliary
        GIR_CustomOperandRenderer, /*InsnID*/0, /*OldInsnID*/0, /*OpIdx*/6, /*OperandRenderer*/GIMT_Encode2(GICR_renderExtractSWZ), // auxiliary
        GIR_MergeMemOperands, /*InsnID*/0, /*NumInsns*/1, /*MergeInsnID's*/0,
        GIR_ConstrainSelectedInstOperands, /*InsnID*/0,
        GIR_EraseFromParent, /*InsnID*/0,
        // GIR_Coverage, 4010,
        GIR_Done,
      // Label 6588: @483432
      GIM_Try, /*On fail goto*//*Label 6589*/ GIMT_Encode4(483514), // Rule ID 4014 //
        GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasUnpackedD16VMem),
        GIM_CheckConstantInt8, /*MI*/0, /*Op*/2, 0,
        // MIs[0] offset
        GIM_CheckIsImm, /*MI*/0, /*Op*/5,
        // MIs[0] auxiliary
        GIM_CheckIsImm, /*MI*/0, /*Op*/6,
        // MIs[0] Operand 7
        GIM_CheckLiteralInt, /*MI*/0, /*Op*/7, GIMT_Encode8(0),
        GIM_CheckComplexPattern, /*MI*/0, /*Op*/4, /*Renderer*/GIMT_Encode2(0), GIMT_Encode2(GICP_gi_buf_soffset),
        // (SIbuffer_load_format_d16:{ *:[i16] } v4i32:{ *:[v4i32] }:$rsrc, 0:{ *:[i32] }, i32:{ *:[i32] }:$voffset, (BUFSOffset:{ *:[i32] } i32:{ *:[i32] }:$soffset), (timm:{ *:[i32] }):$offset, (timm:{ *:[i32] }):$auxiliary, 0:{ *:[i1] })  =>  (BUFFER_LOAD_FORMAT_D16_X_gfx80_OFFEN:{ *:[i16] } VGPR_32:{ *:[i32] }:$voffset, SReg_128:{ *:[v4i32] }:$rsrc, SCSrc_b32:{ *:[i32] }:$soffset, (timm:{ *:[i32] }):$offset, (extract_cpol:{ *:[i32] } ?:{ *:[i32] }:$auxiliary), (extract_swz:{ *:[i1] } ?:{ *:[i32] }:$auxiliary))
        GIR_BuildMI, /*InsnID*/0, /*Opcode*/GIMT_Encode2(AMDGPU::BUFFER_LOAD_FORMAT_D16_X_gfx80_OFFEN),
        GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/0, // DstI[vdata]
        GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/3, // voffset
        GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/1, // rsrc
        GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/0, // soffset
        GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/5, // offset
        GIR_CustomOperandRenderer, /*InsnID*/0, /*OldInsnID*/0, /*OpIdx*/6, /*OperandRenderer*/GIMT_Encode2(GICR_renderExtractCPol), // auxiliary
        GIR_CustomOperandRenderer, /*InsnID*/0, /*OldInsnID*/0, /*OpIdx*/6, /*OperandRenderer*/GIMT_Encode2(GICR_renderExtractSWZ), // auxiliary
        GIR_MergeMemOperands, /*InsnID*/0, /*NumInsns*/1, /*MergeInsnID's*/0,
        GIR_ConstrainSelectedInstOperands, /*InsnID*/0,
        GIR_EraseFromParent, /*InsnID*/0,
        // GIR_Coverage, 4014,
        GIR_Done,
      // Label 6589: @483514
      GIM_Try, /*On fail goto*//*Label 6590*/ GIMT_Encode4(483596), // Rule ID 4034 //
        GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasPackedD16VMem_HasUnrestrictedSOffset),
        GIM_CheckConstantInt8, /*MI*/0, /*Op*/2, 0,
        // MIs[0] offset
        GIM_CheckIsImm, /*MI*/0, /*Op*/5,
        // MIs[0] auxiliary
        GIM_CheckIsImm, /*MI*/0, /*Op*/6,
        // MIs[0] Operand 7
        GIM_CheckLiteralInt, /*MI*/0, /*Op*/7, GIMT_Encode8(0),
        GIM_CheckComplexPattern, /*MI*/0, /*Op*/4, /*Renderer*/GIMT_Encode2(0), GIMT_Encode2(GICP_gi_buf_soffset),
        // (SIbuffer_load_format_d16:{ *:[f16] } v4i32:{ *:[v4i32] }:$rsrc, 0:{ *:[i32] }, i32:{ *:[i32] }:$voffset, (BUFSOffset:{ *:[i32] } i32:{ *:[i32] }:$soffset), (timm:{ *:[i32] }):$offset, (timm:{ *:[i32] }):$auxiliary, 0:{ *:[i1] })  =>  (BUFFER_LOAD_FORMAT_D16_X_OFFEN:{ *:[f16] } VGPR_32:{ *:[i32] }:$voffset, SReg_128:{ *:[v4i32] }:$rsrc, SCSrc_b32:{ *:[i32] }:$soffset, (timm:{ *:[i32] }):$offset, (extract_cpol:{ *:[i32] } ?:{ *:[i32] }:$auxiliary), (extract_swz:{ *:[i1] } ?:{ *:[i32] }:$auxiliary))
        GIR_BuildMI, /*InsnID*/0, /*Opcode*/GIMT_Encode2(AMDGPU::BUFFER_LOAD_FORMAT_D16_X_OFFEN),
        GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/0, // DstI[vdata]
        GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/3, // voffset
        GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/1, // rsrc
        GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/0, // soffset
        GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/5, // offset
        GIR_CustomOperandRenderer, /*InsnID*/0, /*OldInsnID*/0, /*OpIdx*/6, /*OperandRenderer*/GIMT_Encode2(GICR_renderExtractCPol), // auxiliary
        GIR_CustomOperandRenderer, /*InsnID*/0, /*OldInsnID*/0, /*OpIdx*/6, /*OperandRenderer*/GIMT_Encode2(GICR_renderExtractSWZ), // auxiliary
        GIR_MergeMemOperands, /*InsnID*/0, /*NumInsns*/1, /*MergeInsnID's*/0,
        GIR_ConstrainSelectedInstOperands, /*InsnID*/0,
        GIR_EraseFromParent, /*InsnID*/0,
        // GIR_Coverage, 4034,
        GIR_Done,
      // Label 6590: @483596
      GIM_Try, /*On fail goto*//*Label 6591*/ GIMT_Encode4(483678), // Rule ID 4038 //
        GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasPackedD16VMem),
        GIM_CheckConstantInt8, /*MI*/0, /*Op*/2, 0,
        // MIs[0] offset
        GIM_CheckIsImm, /*MI*/0, /*Op*/5,
        // MIs[0] auxiliary
        GIM_CheckIsImm, /*MI*/0, /*Op*/6,
        // MIs[0] Operand 7
        GIM_CheckLiteralInt, /*MI*/0, /*Op*/7, GIMT_Encode8(0),
        GIM_CheckComplexPattern, /*MI*/0, /*Op*/4, /*Renderer*/GIMT_Encode2(0), GIMT_Encode2(GICP_gi_buf_soffset),
        // (SIbuffer_load_format_d16:{ *:[f16] } v4i32:{ *:[v4i32] }:$rsrc, 0:{ *:[i32] }, i32:{ *:[i32] }:$voffset, (BUFSOffset:{ *:[i32] } i32:{ *:[i32] }:$soffset), (timm:{ *:[i32] }):$offset, (timm:{ *:[i32] }):$auxiliary, 0:{ *:[i1] })  =>  (BUFFER_LOAD_FORMAT_D16_X_VBUFFER_OFFEN:{ *:[f16] } VGPR_32:{ *:[i32] }:$voffset, SReg_128:{ *:[v4i32] }:$rsrc, SCSrc_b32:{ *:[i32] }:$soffset, (timm:{ *:[i32] }):$offset, (extract_cpol:{ *:[i32] } ?:{ *:[i32] }:$auxiliary), (extract_swz:{ *:[i1] } ?:{ *:[i32] }:$auxiliary))
        GIR_BuildMI, /*InsnID*/0, /*Opcode*/GIMT_Encode2(AMDGPU::BUFFER_LOAD_FORMAT_D16_X_VBUFFER_OFFEN),
        GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/0, // DstI[vdata]
        GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/3, // voffset
        GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/1, // rsrc
        GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/0, // soffset
        GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/5, // offset
        GIR_CustomOperandRenderer, /*InsnID*/0, /*OldInsnID*/0, /*OpIdx*/6, /*OperandRenderer*/GIMT_Encode2(GICR_renderExtractCPol), // auxiliary
        GIR_CustomOperandRenderer, /*InsnID*/0, /*OldInsnID*/0, /*OpIdx*/6, /*OperandRenderer*/GIMT_Encode2(GICR_renderExtractSWZ), // auxiliary
        GIR_MergeMemOperands, /*InsnID*/0, /*NumInsns*/1, /*MergeInsnID's*/0,
        GIR_ConstrainSelectedInstOperands, /*InsnID*/0,
        GIR_EraseFromParent, /*InsnID*/0,
        // GIR_Coverage, 4038,
        GIR_Done,
      // Label 6591: @483678
      GIM_Try, /*On fail goto*//*Label 6592*/ GIMT_Encode4(483760), // Rule ID 4042 //
        GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasPackedD16VMem_HasUnrestrictedSOffset),
        GIM_CheckConstantInt8, /*MI*/0, /*Op*/2, 0,
        // MIs[0] offset
        GIM_CheckIsImm, /*MI*/0, /*Op*/5,
        // MIs[0] auxiliary
        GIM_CheckIsImm, /*MI*/0, /*Op*/6,
        // MIs[0] Operand 7
        GIM_CheckLiteralInt, /*MI*/0, /*Op*/7, GIMT_Encode8(0),
        GIM_CheckComplexPattern, /*MI*/0, /*Op*/4, /*Renderer*/GIMT_Encode2(0), GIMT_Encode2(GICP_gi_buf_soffset),
        // (SIbuffer_load_format_d16:{ *:[i16] } v4i32:{ *:[v4i32] }:$rsrc, 0:{ *:[i32] }, i32:{ *:[i32] }:$voffset, (BUFSOffset:{ *:[i32] } i32:{ *:[i32] }:$soffset), (timm:{ *:[i32] }):$offset, (timm:{ *:[i32] }):$auxiliary, 0:{ *:[i1] })  =>  (BUFFER_LOAD_FORMAT_D16_X_OFFEN:{ *:[i16] } VGPR_32:{ *:[i32] }:$voffset, SReg_128:{ *:[v4i32] }:$rsrc, SCSrc_b32:{ *:[i32] }:$soffset, (timm:{ *:[i32] }):$offset, (extract_cpol:{ *:[i32] } ?:{ *:[i32] }:$auxiliary), (extract_swz:{ *:[i1] } ?:{ *:[i32] }:$auxiliary))
        GIR_BuildMI, /*InsnID*/0, /*Opcode*/GIMT_Encode2(AMDGPU::BUFFER_LOAD_FORMAT_D16_X_OFFEN),
        GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/0, // DstI[vdata]
        GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/3, // voffset
        GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/1, // rsrc
        GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/0, // soffset
        GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/5, // offset
        GIR_CustomOperandRenderer, /*InsnID*/0, /*OldInsnID*/0, /*OpIdx*/6, /*OperandRenderer*/GIMT_Encode2(GICR_renderExtractCPol), // auxiliary
        GIR_CustomOperandRenderer, /*InsnID*/0, /*OldInsnID*/0, /*OpIdx*/6, /*OperandRenderer*/GIMT_Encode2(GICR_renderExtractSWZ), // auxiliary
        GIR_MergeMemOperands, /*InsnID*/0, /*NumInsns*/1, /*MergeInsnID's*/0,
        GIR_ConstrainSelectedInstOperands, /*InsnID*/0,
        GIR_EraseFromParent, /*InsnID*/0,
        // GIR_Coverage, 4042,
        GIR_Done,
      // Label 6592: @483760
      GIM_Try, /*On fail goto*//*Label 6593*/ GIMT_Encode4(483842), // Rule ID 4046 //
        GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasPackedD16VMem),
        GIM_CheckConstantInt8, /*MI*/0, /*Op*/2, 0,
        // MIs[0] offset
        GIM_CheckIsImm, /*MI*/0, /*Op*/5,
        // MIs[0] auxiliary
        GIM_CheckIsImm, /*MI*/0, /*Op*/6,
        // MIs[0] Operand 7
        GIM_CheckLiteralInt, /*MI*/0, /*Op*/7, GIMT_Encode8(0),
        GIM_CheckComplexPattern, /*MI*/0, /*Op*/4, /*Renderer*/GIMT_Encode2(0), GIMT_Encode2(GICP_gi_buf_soffset),
        // (SIbuffer_load_format_d16:{ *:[i16] } v4i32:{ *:[v4i32] }:$rsrc, 0:{ *:[i32] }, i32:{ *:[i32] }:$voffset, (BUFSOffset:{ *:[i32] } i32:{ *:[i32] }:$soffset), (timm:{ *:[i32] }):$offset, (timm:{ *:[i32] }):$auxiliary, 0:{ *:[i1] })  =>  (BUFFER_LOAD_FORMAT_D16_X_VBUFFER_OFFEN:{ *:[i16] } VGPR_32:{ *:[i32] }:$voffset, SReg_128:{ *:[v4i32] }:$rsrc, SCSrc_b32:{ *:[i32] }:$soffset, (timm:{ *:[i32] }):$offset, (extract_cpol:{ *:[i32] } ?:{ *:[i32] }:$auxiliary), (extract_swz:{ *:[i1] } ?:{ *:[i32] }:$auxiliary))
        GIR_BuildMI, /*InsnID*/0, /*Opcode*/GIMT_Encode2(AMDGPU::BUFFER_LOAD_FORMAT_D16_X_VBUFFER_OFFEN),
        GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/0, // DstI[vdata]
        GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/3, // voffset
        GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/1, // rsrc
        GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/0, // soffset
        GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/5, // offset
        GIR_CustomOperandRenderer, /*InsnID*/0, /*OldInsnID*/0, /*OpIdx*/6, /*OperandRenderer*/GIMT_Encode2(GICR_renderExtractCPol), // auxiliary
        GIR_CustomOperandRenderer, /*InsnID*/0, /*OldInsnID*/0, /*OpIdx*/6, /*OperandRenderer*/GIMT_Encode2(GICR_renderExtractSWZ), // auxiliary
        GIR_MergeMemOperands, /*InsnID*/0, /*NumInsns*/1, /*MergeInsnID's*/0,
        GIR_ConstrainSelectedInstOperands, /*InsnID*/0,
        GIR_EraseFromParent, /*InsnID*/0,
        // GIR_Coverage, 4046,
        GIR_Done,
      // Label 6593: @483842
      GIM_Try, /*On fail goto*//*Label 6594*/ GIMT_Encode4(483916), // Rule ID 4011 //
        GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasUnpackedD16VMem),
        GIM_CheckConstantInt8, /*MI*/0, /*Op*/3, 0,
        // MIs[0] offset
        GIM_CheckIsImm, /*MI*/0, /*Op*/5,
        // MIs[0] auxiliary
        GIM_CheckIsImm, /*MI*/0, /*Op*/6,
        // MIs[0] Operand 7
        GIM_CheckIsImm, /*MI*/0, /*Op*/7,
        GIM_CheckComplexPattern, /*MI*/0, /*Op*/4, /*Renderer*/GIMT_Encode2(0), GIMT_Encode2(GICP_gi_buf_soffset),
        // (SIbuffer_load_format_d16:{ *:[f16] } v4i32:{ *:[v4i32] }:$rsrc, i32:{ *:[i32] }:$vindex, 0:{ *:[i32] }, (BUFSOffset:{ *:[i32] } i32:{ *:[i32] }:$soffset), (timm:{ *:[i32] }):$offset, (timm:{ *:[i32] }):$auxiliary, (timm:{ *:[i1] }))  =>  (BUFFER_LOAD_FORMAT_D16_X_gfx80_IDXEN:{ *:[f16] } VGPR_32:{ *:[i32] }:$vindex, SReg_128:{ *:[v4i32] }:$rsrc, SCSrc_b32:{ *:[i32] }:$soffset, (timm:{ *:[i32] }):$offset, (extract_cpol:{ *:[i32] } ?:{ *:[i32] }:$auxiliary), (extract_swz:{ *:[i1] } ?:{ *:[i32] }:$auxiliary))
        GIR_BuildMI, /*InsnID*/0, /*Opcode*/GIMT_Encode2(AMDGPU::BUFFER_LOAD_FORMAT_D16_X_gfx80_IDXEN),
        GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/0, // DstI[vdata]
        GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/2, // vindex
        GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/1, // rsrc
        GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/0, // soffset
        GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/5, // offset
        GIR_CustomOperandRenderer, /*InsnID*/0, /*OldInsnID*/0, /*OpIdx*/6, /*OperandRenderer*/GIMT_Encode2(GICR_renderExtractCPol), // auxiliary
        GIR_CustomOperandRenderer, /*InsnID*/0, /*OldInsnID*/0, /*OpIdx*/6, /*OperandRenderer*/GIMT_Encode2(GICR_renderExtractSWZ), // auxiliary
        GIR_MergeMemOperands, /*InsnID*/0, /*NumInsns*/1, /*MergeInsnID's*/0,
        GIR_ConstrainSelectedInstOperands, /*InsnID*/0,
        GIR_EraseFromParent, /*InsnID*/0,
        // GIR_Coverage, 4011,
        GIR_Done,
      // Label 6594: @483916
      GIM_Try, /*On fail goto*//*Label 6595*/ GIMT_Encode4(483990), // Rule ID 4015 //
        GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasUnpackedD16VMem),
        GIM_CheckConstantInt8, /*MI*/0, /*Op*/3, 0,
        // MIs[0] offset
        GIM_CheckIsImm, /*MI*/0, /*Op*/5,
        // MIs[0] auxiliary
        GIM_CheckIsImm, /*MI*/0, /*Op*/6,
        // MIs[0] Operand 7
        GIM_CheckIsImm, /*MI*/0, /*Op*/7,
        GIM_CheckComplexPattern, /*MI*/0, /*Op*/4, /*Renderer*/GIMT_Encode2(0), GIMT_Encode2(GICP_gi_buf_soffset),
        // (SIbuffer_load_format_d16:{ *:[i16] } v4i32:{ *:[v4i32] }:$rsrc, i32:{ *:[i32] }:$vindex, 0:{ *:[i32] }, (BUFSOffset:{ *:[i32] } i32:{ *:[i32] }:$soffset), (timm:{ *:[i32] }):$offset, (timm:{ *:[i32] }):$auxiliary, (timm:{ *:[i1] }))  =>  (BUFFER_LOAD_FORMAT_D16_X_gfx80_IDXEN:{ *:[i16] } VGPR_32:{ *:[i32] }:$vindex, SReg_128:{ *:[v4i32] }:$rsrc, SCSrc_b32:{ *:[i32] }:$soffset, (timm:{ *:[i32] }):$offset, (extract_cpol:{ *:[i32] } ?:{ *:[i32] }:$auxiliary), (extract_swz:{ *:[i1] } ?:{ *:[i32] }:$auxiliary))
        GIR_BuildMI, /*InsnID*/0, /*Opcode*/GIMT_Encode2(AMDGPU::BUFFER_LOAD_FORMAT_D16_X_gfx80_IDXEN),
        GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/0, // DstI[vdata]
        GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/2, // vindex
        GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/1, // rsrc
        GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/0, // soffset
        GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/5, // offset
        GIR_CustomOperandRenderer, /*InsnID*/0, /*OldInsnID*/0, /*OpIdx*/6, /*OperandRenderer*/GIMT_Encode2(GICR_renderExtractCPol), // auxiliary
        GIR_CustomOperandRenderer, /*InsnID*/0, /*OldInsnID*/0, /*OpIdx*/6, /*OperandRenderer*/GIMT_Encode2(GICR_renderExtractSWZ), // auxiliary
        GIR_MergeMemOperands, /*InsnID*/0, /*NumInsns*/1, /*MergeInsnID's*/0,
        GIR_ConstrainSelectedInstOperands, /*InsnID*/0,
        GIR_EraseFromParent, /*InsnID*/0,
        // GIR_Coverage, 4015,
        GIR_Done,
      // Label 6595: @483990
      GIM_Try, /*On fail goto*//*Label 6596*/ GIMT_Encode4(484064), // Rule ID 4035 //
        GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasPackedD16VMem_HasUnrestrictedSOffset),
        GIM_CheckConstantInt8, /*MI*/0, /*Op*/3, 0,
        // MIs[0] offset
        GIM_CheckIsImm, /*MI*/0, /*Op*/5,
        // MIs[0] auxiliary
        GIM_CheckIsImm, /*MI*/0, /*Op*/6,
        // MIs[0] Operand 7
        GIM_CheckIsImm, /*MI*/0, /*Op*/7,
        GIM_CheckComplexPattern, /*MI*/0, /*Op*/4, /*Renderer*/GIMT_Encode2(0), GIMT_Encode2(GICP_gi_buf_soffset),
        // (SIbuffer_load_format_d16:{ *:[f16] } v4i32:{ *:[v4i32] }:$rsrc, i32:{ *:[i32] }:$vindex, 0:{ *:[i32] }, (BUFSOffset:{ *:[i32] } i32:{ *:[i32] }:$soffset), (timm:{ *:[i32] }):$offset, (timm:{ *:[i32] }):$auxiliary, (timm:{ *:[i1] }))  =>  (BUFFER_LOAD_FORMAT_D16_X_IDXEN:{ *:[f16] } VGPR_32:{ *:[i32] }:$vindex, SReg_128:{ *:[v4i32] }:$rsrc, SCSrc_b32:{ *:[i32] }:$soffset, (timm:{ *:[i32] }):$offset, (extract_cpol:{ *:[i32] } ?:{ *:[i32] }:$auxiliary), (extract_swz:{ *:[i1] } ?:{ *:[i32] }:$auxiliary))
        GIR_BuildMI, /*InsnID*/0, /*Opcode*/GIMT_Encode2(AMDGPU::BUFFER_LOAD_FORMAT_D16_X_IDXEN),
        GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/0, // DstI[vdata]
        GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/2, // vindex
        GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/1, // rsrc
        GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/0, // soffset
        GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/5, // offset
        GIR_CustomOperandRenderer, /*InsnID*/0, /*OldInsnID*/0, /*OpIdx*/6, /*OperandRenderer*/GIMT_Encode2(GICR_renderExtractCPol), // auxiliary
        GIR_CustomOperandRenderer, /*InsnID*/0, /*OldInsnID*/0, /*OpIdx*/6, /*OperandRenderer*/GIMT_Encode2(GICR_renderExtractSWZ), // auxiliary
        GIR_MergeMemOperands, /*InsnID*/0, /*NumInsns*/1, /*MergeInsnID's*/0,
        GIR_ConstrainSelectedInstOperands, /*InsnID*/0,
        GIR_EraseFromParent, /*InsnID*/0,
        // GIR_Coverage, 4035,
        GIR_Done,
      // Label 6596: @484064
      GIM_Try, /*On fail goto*//*Label 6597*/ GIMT_Encode4(484138), // Rule ID 4039 //
        GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasPackedD16VMem),
        GIM_CheckConstantInt8, /*MI*/0, /*Op*/3, 0,
        // MIs[0] offset
        GIM_CheckIsImm, /*MI*/0, /*Op*/5,
        // MIs[0] auxiliary
        GIM_CheckIsImm, /*MI*/0, /*Op*/6,
        // MIs[0] Operand 7
        GIM_CheckIsImm, /*MI*/0, /*Op*/7,
        GIM_CheckComplexPattern, /*MI*/0, /*Op*/4, /*Renderer*/GIMT_Encode2(0), GIMT_Encode2(GICP_gi_buf_soffset),
        // (SIbuffer_load_format_d16:{ *:[f16] } v4i32:{ *:[v4i32] }:$rsrc, i32:{ *:[i32] }:$vindex, 0:{ *:[i32] }, (BUFSOffset:{ *:[i32] } i32:{ *:[i32] }:$soffset), (timm:{ *:[i32] }):$offset, (timm:{ *:[i32] }):$auxiliary, (timm:{ *:[i1] }))  =>  (BUFFER_LOAD_FORMAT_D16_X_VBUFFER_IDXEN:{ *:[f16] } VGPR_32:{ *:[i32] }:$vindex, SReg_128:{ *:[v4i32] }:$rsrc, SCSrc_b32:{ *:[i32] }:$soffset, (timm:{ *:[i32] }):$offset, (extract_cpol:{ *:[i32] } ?:{ *:[i32] }:$auxiliary), (extract_swz:{ *:[i1] } ?:{ *:[i32] }:$auxiliary))
        GIR_BuildMI, /*InsnID*/0, /*Opcode*/GIMT_Encode2(AMDGPU::BUFFER_LOAD_FORMAT_D16_X_VBUFFER_IDXEN),
        GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/0, // DstI[vdata]
        GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/2, // vindex
        GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/1, // rsrc
        GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/0, // soffset
        GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/5, // offset
        GIR_CustomOperandRenderer, /*InsnID*/0, /*OldInsnID*/0, /*OpIdx*/6, /*OperandRenderer*/GIMT_Encode2(GICR_renderExtractCPol), // auxiliary
        GIR_CustomOperandRenderer, /*InsnID*/0, /*OldInsnID*/0, /*OpIdx*/6, /*OperandRenderer*/GIMT_Encode2(GICR_renderExtractSWZ), // auxiliary
        GIR_MergeMemOperands, /*InsnID*/0, /*NumInsns*/1, /*MergeInsnID's*/0,
        GIR_ConstrainSelectedInstOperands, /*InsnID*/0,
        GIR_EraseFromParent, /*InsnID*/0,
        // GIR_Coverage, 4039,
        GIR_Done,
      // Label 6597: @484138
      GIM_Try, /*On fail goto*//*Label 6598*/ GIMT_Encode4(484212), // Rule ID 4043 //
        GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasPackedD16VMem_HasUnrestrictedSOffset),
        GIM_CheckConstantInt8, /*MI*/0, /*Op*/3, 0,
        // MIs[0] offset
        GIM_CheckIsImm, /*MI*/0, /*Op*/5,
        // MIs[0] auxiliary
        GIM_CheckIsImm, /*MI*/0, /*Op*/6,
        // MIs[0] Operand 7
        GIM_CheckIsImm, /*MI*/0, /*Op*/7,
        GIM_CheckComplexPattern, /*MI*/0, /*Op*/4, /*Renderer*/GIMT_Encode2(0), GIMT_Encode2(GICP_gi_buf_soffset),
        // (SIbuffer_load_format_d16:{ *:[i16] } v4i32:{ *:[v4i32] }:$rsrc, i32:{ *:[i32] }:$vindex, 0:{ *:[i32] }, (BUFSOffset:{ *:[i32] } i32:{ *:[i32] }:$soffset), (timm:{ *:[i32] }):$offset, (timm:{ *:[i32] }):$auxiliary, (timm:{ *:[i1] }))  =>  (BUFFER_LOAD_FORMAT_D16_X_IDXEN:{ *:[i16] } VGPR_32:{ *:[i32] }:$vindex, SReg_128:{ *:[v4i32] }:$rsrc, SCSrc_b32:{ *:[i32] }:$soffset, (timm:{ *:[i32] }):$offset, (extract_cpol:{ *:[i32] } ?:{ *:[i32] }:$auxiliary), (extract_swz:{ *:[i1] } ?:{ *:[i32] }:$auxiliary))
        GIR_BuildMI, /*InsnID*/0, /*Opcode*/GIMT_Encode2(AMDGPU::BUFFER_LOAD_FORMAT_D16_X_IDXEN),
        GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/0, // DstI[vdata]
        GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/2, // vindex
        GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/1, // rsrc
        GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/0, // soffset
        GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/5, // offset
        GIR_CustomOperandRenderer, /*InsnID*/0, /*OldInsnID*/0, /*OpIdx*/6, /*OperandRenderer*/GIMT_Encode2(GICR_renderExtractCPol), // auxiliary
        GIR_CustomOperandRenderer, /*InsnID*/0, /*OldInsnID*/0, /*OpIdx*/6, /*OperandRenderer*/GIMT_Encode2(GICR_renderExtractSWZ), // auxiliary
        GIR_MergeMemOperands, /*InsnID*/0, /*NumInsns*/1, /*MergeInsnID's*/0,
        GIR_ConstrainSelectedInstOperands, /*InsnID*/0,
        GIR_EraseFromParent, /*InsnID*/0,
        // GIR_Coverage, 4043,
        GIR_Done,
      // Label 6598: @484212
      GIM_Try, /*On fail goto*//*Label 6599*/ GIMT_Encode4(484286), // Rule ID 4047 //
        GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasPackedD16VMem),
        GIM_CheckConstantInt8, /*MI*/0, /*Op*/3, 0,
        // MIs[0] offset
        GIM_CheckIsImm, /*MI*/0, /*Op*/5,
        // MIs[0] auxiliary
        GIM_CheckIsImm, /*MI*/0, /*Op*/6,
        // MIs[0] Operand 7
        GIM_CheckIsImm, /*MI*/0, /*Op*/7,
        GIM_CheckComplexPattern, /*MI*/0, /*Op*/4, /*Renderer*/GIMT_Encode2(0), GIMT_Encode2(GICP_gi_buf_soffset),
        // (SIbuffer_load_format_d16:{ *:[i16] } v4i32:{ *:[v4i32] }:$rsrc, i32:{ *:[i32] }:$vindex, 0:{ *:[i32] }, (BUFSOffset:{ *:[i32] } i32:{ *:[i32] }:$soffset), (timm:{ *:[i32] }):$offset, (timm:{ *:[i32] }):$auxiliary, (timm:{ *:[i1] }))  =>  (BUFFER_LOAD_FORMAT_D16_X_VBUFFER_IDXEN:{ *:[i16] } VGPR_32:{ *:[i32] }:$vindex, SReg_128:{ *:[v4i32] }:$rsrc, SCSrc_b32:{ *:[i32] }:$soffset, (timm:{ *:[i32] }):$offset, (extract_cpol:{ *:[i32] } ?:{ *:[i32] }:$auxiliary), (extract_swz:{ *:[i1] } ?:{ *:[i32] }:$auxiliary))
        GIR_BuildMI, /*InsnID*/0, /*Opcode*/GIMT_Encode2(AMDGPU::BUFFER_LOAD_FORMAT_D16_X_VBUFFER_IDXEN),
        GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/0, // DstI[vdata]
        GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/2, // vindex
        GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/1, // rsrc
        GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/0, // soffset
        GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/5, // offset
        GIR_CustomOperandRenderer, /*InsnID*/0, /*OldInsnID*/0, /*OpIdx*/6, /*OperandRenderer*/GIMT_Encode2(GICR_renderExtractCPol), // auxiliary
        GIR_CustomOperandRenderer, /*InsnID*/0, /*OldInsnID*/0, /*OpIdx*/6, /*OperandRenderer*/GIMT_Encode2(GICR_renderExtractSWZ), // auxiliary
        GIR_MergeMemOperands, /*InsnID*/0, /*NumInsns*/1, /*MergeInsnID's*/0,
        GIR_ConstrainSelectedInstOperands, /*InsnID*/0,
        GIR_EraseFromParent, /*InsnID*/0,
        // GIR_Coverage, 4047,
        GIR_Done,
      // Label 6599: @484286
      GIM_Try, /*On fail goto*//*Label 6600*/ GIMT_Encode4(484396), // Rule ID 4012 //
        GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasUnpackedD16VMem),
        // MIs[0] offset
        GIM_CheckIsImm, /*MI*/0, /*Op*/5,
        // MIs[0] auxiliary
        GIM_CheckIsImm, /*MI*/0, /*Op*/6,
        // MIs[0] Operand 7
        GIM_CheckIsImm, /*MI*/0, /*Op*/7,
        GIM_CheckComplexPattern, /*MI*/0, /*Op*/4, /*Renderer*/GIMT_Encode2(0), GIMT_Encode2(GICP_gi_buf_soffset),
        // (SIbuffer_load_format_d16:{ *:[f16] } v4i32:{ *:[v4i32] }:$rsrc, i32:{ *:[i32] }:$vindex, i32:{ *:[i32] }:$voffset, (BUFSOffset:{ *:[i32] } i32:{ *:[i32] }:$soffset), (timm:{ *:[i32] }):$offset, (timm:{ *:[i32] }):$auxiliary, (timm:{ *:[i1] }))  =>  (BUFFER_LOAD_FORMAT_D16_X_gfx80_BOTHEN:{ *:[f16] } (REG_SEQUENCE:{ *:[i64] } VReg_64:{ *:[i32] }, VGPR_32:{ *:[i32] }:$vindex, sub0:{ *:[i32] }, VGPR_32:{ *:[i32] }:$voffset, sub1:{ *:[i32] }), SReg_128:{ *:[v4i32] }:$rsrc, SCSrc_b32:{ *:[i32] }:$soffset, (timm:{ *:[i32] }):$offset, (extract_cpol:{ *:[i32] } ?:{ *:[i32] }:$auxiliary), (extract_swz:{ *:[i1] } ?:{ *:[i32] }:$auxiliary))
        GIR_MakeTempReg, /*TempRegID*/0, /*TypeID*/GILLT_s64,
        GIR_BuildMI, /*InsnID*/1, /*Opcode*/GIMT_Encode2(TargetOpcode::REG_SEQUENCE),
        GIR_AddTempRegister, /*InsnID*/1, /*TempRegID*/0, /*TempRegFlags*/GIMT_Encode2(RegState::Define),
        GIR_Copy, /*NewInsnID*/1, /*OldInsnID*/0, /*OpIdx*/2, // vindex
        GIR_AddImm8, /*InsnID*/1, /*SubRegIndex*/3,
        GIR_Copy, /*NewInsnID*/1, /*OldInsnID*/0, /*OpIdx*/3, // voffset
        GIR_AddImm8, /*InsnID*/1, /*SubRegIndex*/11,
        GIR_ConstrainOperandRC, /*InsnID*/1, /*Op*/0, GIMT_Encode2(AMDGPU::VReg_64RegClassID),
        GIR_ConstrainOperandRC, /*InsnID*/1, /*Op*/1, GIMT_Encode2(AMDGPU::VGPR_32RegClassID),
        GIR_ConstrainOperandRC, /*InsnID*/1, /*Op*/3, GIMT_Encode2(AMDGPU::VGPR_32RegClassID),
        GIR_BuildMI, /*InsnID*/0, /*Opcode*/GIMT_Encode2(AMDGPU::BUFFER_LOAD_FORMAT_D16_X_gfx80_BOTHEN),
        GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/0, // DstI[vdata]
        GIR_AddSimpleTempRegister, /*InsnID*/0, /*TempRegID*/0,
        GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/1, // rsrc
        GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/0, // soffset
        GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/5, // offset
        GIR_CustomOperandRenderer, /*InsnID*/0, /*OldInsnID*/0, /*OpIdx*/6, /*OperandRenderer*/GIMT_Encode2(GICR_renderExtractCPol), // auxiliary
        GIR_CustomOperandRenderer, /*InsnID*/0, /*OldInsnID*/0, /*OpIdx*/6, /*OperandRenderer*/GIMT_Encode2(GICR_renderExtractSWZ), // auxiliary
        GIR_MergeMemOperands, /*InsnID*/0, /*NumInsns*/1, /*MergeInsnID's*/0,
        GIR_ConstrainSelectedInstOperands, /*InsnID*/0,
        GIR_EraseFromParent, /*InsnID*/0,
        // GIR_Coverage, 4012,
        GIR_Done,
      // Label 6600: @484396
      GIM_Try, /*On fail goto*//*Label 6601*/ GIMT_Encode4(484506), // Rule ID 4016 //
        GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasUnpackedD16VMem),
        // MIs[0] offset
        GIM_CheckIsImm, /*MI*/0, /*Op*/5,
        // MIs[0] auxiliary
        GIM_CheckIsImm, /*MI*/0, /*Op*/6,
        // MIs[0] Operand 7
        GIM_CheckIsImm, /*MI*/0, /*Op*/7,
        GIM_CheckComplexPattern, /*MI*/0, /*Op*/4, /*Renderer*/GIMT_Encode2(0), GIMT_Encode2(GICP_gi_buf_soffset),
        // (SIbuffer_load_format_d16:{ *:[i16] } v4i32:{ *:[v4i32] }:$rsrc, i32:{ *:[i32] }:$vindex, i32:{ *:[i32] }:$voffset, (BUFSOffset:{ *:[i32] } i32:{ *:[i32] }:$soffset), (timm:{ *:[i32] }):$offset, (timm:{ *:[i32] }):$auxiliary, (timm:{ *:[i1] }))  =>  (BUFFER_LOAD_FORMAT_D16_X_gfx80_BOTHEN:{ *:[i16] } (REG_SEQUENCE:{ *:[i64] } VReg_64:{ *:[i32] }, VGPR_32:{ *:[i32] }:$vindex, sub0:{ *:[i32] }, VGPR_32:{ *:[i32] }:$voffset, sub1:{ *:[i32] }), SReg_128:{ *:[v4i32] }:$rsrc, SCSrc_b32:{ *:[i32] }:$soffset, (timm:{ *:[i32] }):$offset, (extract_cpol:{ *:[i32] } ?:{ *:[i32] }:$auxiliary), (extract_swz:{ *:[i1] } ?:{ *:[i32] }:$auxiliary))
        GIR_MakeTempReg, /*TempRegID*/0, /*TypeID*/GILLT_s64,
        GIR_BuildMI, /*InsnID*/1, /*Opcode*/GIMT_Encode2(TargetOpcode::REG_SEQUENCE),
        GIR_AddTempRegister, /*InsnID*/1, /*TempRegID*/0, /*TempRegFlags*/GIMT_Encode2(RegState::Define),
        GIR_Copy, /*NewInsnID*/1, /*OldInsnID*/0, /*OpIdx*/2, // vindex
        GIR_AddImm8, /*InsnID*/1, /*SubRegIndex*/3,
        GIR_Copy, /*NewInsnID*/1, /*OldInsnID*/0, /*OpIdx*/3, // voffset
        GIR_AddImm8, /*InsnID*/1, /*SubRegIndex*/11,
        GIR_ConstrainOperandRC, /*InsnID*/1, /*Op*/0, GIMT_Encode2(AMDGPU::VReg_64RegClassID),
        GIR_ConstrainOperandRC, /*InsnID*/1, /*Op*/1, GIMT_Encode2(AMDGPU::VGPR_32RegClassID),
        GIR_ConstrainOperandRC, /*InsnID*/1, /*Op*/3, GIMT_Encode2(AMDGPU::VGPR_32RegClassID),
        GIR_BuildMI, /*InsnID*/0, /*Opcode*/GIMT_Encode2(AMDGPU::BUFFER_LOAD_FORMAT_D16_X_gfx80_BOTHEN),
        GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/0, // DstI[vdata]
        GIR_AddSimpleTempRegister, /*InsnID*/0, /*TempRegID*/0,
        GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/1, // rsrc
        GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/0, // soffset
        GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/5, // offset
        GIR_CustomOperandRenderer, /*InsnID*/0, /*OldInsnID*/0, /*OpIdx*/6, /*OperandRenderer*/GIMT_Encode2(GICR_renderExtractCPol), // auxiliary
        GIR_CustomOperandRenderer, /*InsnID*/0, /*OldInsnID*/0, /*OpIdx*/6, /*OperandRenderer*/GIMT_Encode2(GICR_renderExtractSWZ), // auxiliary
        GIR_MergeMemOperands, /*InsnID*/0, /*NumInsns*/1, /*MergeInsnID's*/0,
        GIR_ConstrainSelectedInstOperands, /*InsnID*/0,
        GIR_EraseFromParent, /*InsnID*/0,
        // GIR_Coverage, 4016,
        GIR_Done,
      // Label 6601: @484506
      GIM_Try, /*On fail goto*//*Label 6602*/ GIMT_Encode4(484616), // Rule ID 4036 //
        GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasPackedD16VMem_HasUnrestrictedSOffset),
        // MIs[0] offset
        GIM_CheckIsImm, /*MI*/0, /*Op*/5,
        // MIs[0] auxiliary
        GIM_CheckIsImm, /*MI*/0, /*Op*/6,
        // MIs[0] Operand 7
        GIM_CheckIsImm, /*MI*/0, /*Op*/7,
        GIM_CheckComplexPattern, /*MI*/0, /*Op*/4, /*Renderer*/GIMT_Encode2(0), GIMT_Encode2(GICP_gi_buf_soffset),
        // (SIbuffer_load_format_d16:{ *:[f16] } v4i32:{ *:[v4i32] }:$rsrc, i32:{ *:[i32] }:$vindex, i32:{ *:[i32] }:$voffset, (BUFSOffset:{ *:[i32] } i32:{ *:[i32] }:$soffset), (timm:{ *:[i32] }):$offset, (timm:{ *:[i32] }):$auxiliary, (timm:{ *:[i1] }))  =>  (BUFFER_LOAD_FORMAT_D16_X_BOTHEN:{ *:[f16] } (REG_SEQUENCE:{ *:[i64] } VReg_64:{ *:[i32] }, VGPR_32:{ *:[i32] }:$vindex, sub0:{ *:[i32] }, VGPR_32:{ *:[i32] }:$voffset, sub1:{ *:[i32] }), SReg_128:{ *:[v4i32] }:$rsrc, SCSrc_b32:{ *:[i32] }:$soffset, (timm:{ *:[i32] }):$offset, (extract_cpol:{ *:[i32] } ?:{ *:[i32] }:$auxiliary), (extract_swz:{ *:[i1] } ?:{ *:[i32] }:$auxiliary))
        GIR_MakeTempReg, /*TempRegID*/0, /*TypeID*/GILLT_s64,
        GIR_BuildMI, /*InsnID*/1, /*Opcode*/GIMT_Encode2(TargetOpcode::REG_SEQUENCE),
        GIR_AddTempRegister, /*InsnID*/1, /*TempRegID*/0, /*TempRegFlags*/GIMT_Encode2(RegState::Define),
        GIR_Copy, /*NewInsnID*/1, /*OldInsnID*/0, /*OpIdx*/2, // vindex
        GIR_AddImm8, /*InsnID*/1, /*SubRegIndex*/3,
        GIR_Copy, /*NewInsnID*/1, /*OldInsnID*/0, /*OpIdx*/3, // voffset
        GIR_AddImm8, /*InsnID*/1, /*SubRegIndex*/11,
        GIR_ConstrainOperandRC, /*InsnID*/1, /*Op*/0, GIMT_Encode2(AMDGPU::VReg_64RegClassID),
        GIR_ConstrainOperandRC, /*InsnID*/1, /*Op*/1, GIMT_Encode2(AMDGPU::VGPR_32RegClassID),
        GIR_ConstrainOperandRC, /*InsnID*/1, /*Op*/3, GIMT_Encode2(AMDGPU::VGPR_32RegClassID),
        GIR_BuildMI, /*InsnID*/0, /*Opcode*/GIMT_Encode2(AMDGPU::BUFFER_LOAD_FORMAT_D16_X_BOTHEN),
        GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/0, // DstI[vdata]
        GIR_AddSimpleTempRegister, /*InsnID*/0, /*TempRegID*/0,
        GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/1, // rsrc
        GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/0, // soffset
        GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/5, // offset
        GIR_CustomOperandRenderer, /*InsnID*/0, /*OldInsnID*/0, /*OpIdx*/6, /*OperandRenderer*/GIMT_Encode2(GICR_renderExtractCPol), // auxiliary
        GIR_CustomOperandRenderer, /*InsnID*/0, /*OldInsnID*/0, /*OpIdx*/6, /*OperandRenderer*/GIMT_Encode2(GICR_renderExtractSWZ), // auxiliary
        GIR_MergeMemOperands, /*InsnID*/0, /*NumInsns*/1, /*MergeInsnID's*/0,
        GIR_ConstrainSelectedInstOperands, /*InsnID*/0,
        GIR_EraseFromParent, /*InsnID*/0,
        // GIR_Coverage, 4036,
        GIR_Done,
      // Label 6602: @484616
      GIM_Try, /*On fail goto*//*Label 6603*/ GIMT_Encode4(484726), // Rule ID 4040 //
        GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasPackedD16VMem),
        // MIs[0] offset
        GIM_CheckIsImm, /*MI*/0, /*Op*/5,
        // MIs[0] auxiliary
        GIM_CheckIsImm, /*MI*/0, /*Op*/6,
        // MIs[0] Operand 7
        GIM_CheckIsImm, /*MI*/0, /*Op*/7,
        GIM_CheckComplexPattern, /*MI*/0, /*Op*/4, /*Renderer*/GIMT_Encode2(0), GIMT_Encode2(GICP_gi_buf_soffset),
        // (SIbuffer_load_format_d16:{ *:[f16] } v4i32:{ *:[v4i32] }:$rsrc, i32:{ *:[i32] }:$vindex, i32:{ *:[i32] }:$voffset, (BUFSOffset:{ *:[i32] } i32:{ *:[i32] }:$soffset), (timm:{ *:[i32] }):$offset, (timm:{ *:[i32] }):$auxiliary, (timm:{ *:[i1] }))  =>  (BUFFER_LOAD_FORMAT_D16_X_VBUFFER_BOTHEN:{ *:[f16] } (REG_SEQUENCE:{ *:[i64] } VReg_64:{ *:[i32] }, VGPR_32:{ *:[i32] }:$vindex, sub0:{ *:[i32] }, VGPR_32:{ *:[i32] }:$voffset, sub1:{ *:[i32] }), SReg_128:{ *:[v4i32] }:$rsrc, SCSrc_b32:{ *:[i32] }:$soffset, (timm:{ *:[i32] }):$offset, (extract_cpol:{ *:[i32] } ?:{ *:[i32] }:$auxiliary), (extract_swz:{ *:[i1] } ?:{ *:[i32] }:$auxiliary))
        GIR_MakeTempReg, /*TempRegID*/0, /*TypeID*/GILLT_s64,
        GIR_BuildMI, /*InsnID*/1, /*Opcode*/GIMT_Encode2(TargetOpcode::REG_SEQUENCE),
        GIR_AddTempRegister, /*InsnID*/1, /*TempRegID*/0, /*TempRegFlags*/GIMT_Encode2(RegState::Define),
        GIR_Copy, /*NewInsnID*/1, /*OldInsnID*/0, /*OpIdx*/2, // vindex
        GIR_AddImm8, /*InsnID*/1, /*SubRegIndex*/3,
        GIR_Copy, /*NewInsnID*/1, /*OldInsnID*/0, /*OpIdx*/3, // voffset
        GIR_AddImm8, /*InsnID*/1, /*SubRegIndex*/11,
        GIR_ConstrainOperandRC, /*InsnID*/1, /*Op*/0, GIMT_Encode2(AMDGPU::VReg_64RegClassID),
        GIR_ConstrainOperandRC, /*InsnID*/1, /*Op*/1, GIMT_Encode2(AMDGPU::VGPR_32RegClassID),
        GIR_ConstrainOperandRC, /*InsnID*/1, /*Op*/3, GIMT_Encode2(AMDGPU::VGPR_32RegClassID),
        GIR_BuildMI, /*InsnID*/0, /*Opcode*/GIMT_Encode2(AMDGPU::BUFFER_LOAD_FORMAT_D16_X_VBUFFER_BOTHEN),
        GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/0, // DstI[vdata]
        GIR_AddSimpleTempRegister, /*InsnID*/0, /*TempRegID*/0,
        GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/1, // rsrc
        GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/0, // soffset
        GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/5, // offset
        GIR_CustomOperandRenderer, /*InsnID*/0, /*OldInsnID*/0, /*OpIdx*/6, /*OperandRenderer*/GIMT_Encode2(GICR_renderExtractCPol), // auxiliary
        GIR_CustomOperandRenderer, /*InsnID*/0, /*OldInsnID*/0, /*OpIdx*/6, /*OperandRenderer*/GIMT_Encode2(GICR_renderExtractSWZ), // auxiliary
        GIR_MergeMemOperands, /*InsnID*/0, /*NumInsns*/1, /*MergeInsnID's*/0,
        GIR_ConstrainSelectedInstOperands, /*InsnID*/0,
        GIR_EraseFromParent, /*InsnID*/0,
        // GIR_Coverage, 4040,
        GIR_Done,
      // Label 6603: @484726
      GIM_Try, /*On fail goto*//*Label 6604*/ GIMT_Encode4(484836), // Rule ID 4044 //
        GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasPackedD16VMem_HasUnrestrictedSOffset),
        // MIs[0] offset
        GIM_CheckIsImm, /*MI*/0, /*Op*/5,
        // MIs[0] auxiliary
        GIM_CheckIsImm, /*MI*/0, /*Op*/6,
        // MIs[0] Operand 7
        GIM_CheckIsImm, /*MI*/0, /*Op*/7,
        GIM_CheckComplexPattern, /*MI*/0, /*Op*/4, /*Renderer*/GIMT_Encode2(0), GIMT_Encode2(GICP_gi_buf_soffset),
        // (SIbuffer_load_format_d16:{ *:[i16] } v4i32:{ *:[v4i32] }:$rsrc, i32:{ *:[i32] }:$vindex, i32:{ *:[i32] }:$voffset, (BUFSOffset:{ *:[i32] } i32:{ *:[i32] }:$soffset), (timm:{ *:[i32] }):$offset, (timm:{ *:[i32] }):$auxiliary, (timm:{ *:[i1] }))  =>  (BUFFER_LOAD_FORMAT_D16_X_BOTHEN:{ *:[i16] } (REG_SEQUENCE:{ *:[i64] } VReg_64:{ *:[i32] }, VGPR_32:{ *:[i32] }:$vindex, sub0:{ *:[i32] }, VGPR_32:{ *:[i32] }:$voffset, sub1:{ *:[i32] }), SReg_128:{ *:[v4i32] }:$rsrc, SCSrc_b32:{ *:[i32] }:$soffset, (timm:{ *:[i32] }):$offset, (extract_cpol:{ *:[i32] } ?:{ *:[i32] }:$auxiliary), (extract_swz:{ *:[i1] } ?:{ *:[i32] }:$auxiliary))
        GIR_MakeTempReg, /*TempRegID*/0, /*TypeID*/GILLT_s64,
        GIR_BuildMI, /*InsnID*/1, /*Opcode*/GIMT_Encode2(TargetOpcode::REG_SEQUENCE),
        GIR_AddTempRegister, /*InsnID*/1, /*TempRegID*/0, /*TempRegFlags*/GIMT_Encode2(RegState::Define),
        GIR_Copy, /*NewInsnID*/1, /*OldInsnID*/0, /*OpIdx*/2, // vindex
        GIR_AddImm8, /*InsnID*/1, /*SubRegIndex*/3,
        GIR_Copy, /*NewInsnID*/1, /*OldInsnID*/0, /*OpIdx*/3, // voffset
        GIR_AddImm8, /*InsnID*/1, /*SubRegIndex*/11,
        GIR_ConstrainOperandRC, /*InsnID*/1, /*Op*/0, GIMT_Encode2(AMDGPU::VReg_64RegClassID),
        GIR_ConstrainOperandRC, /*InsnID*/1, /*Op*/1, GIMT_Encode2(AMDGPU::VGPR_32RegClassID),
        GIR_ConstrainOperandRC, /*InsnID*/1, /*Op*/3, GIMT_Encode2(AMDGPU::VGPR_32RegClassID),
        GIR_BuildMI, /*InsnID*/0, /*Opcode*/GIMT_Encode2(AMDGPU::BUFFER_LOAD_FORMAT_D16_X_BOTHEN),
        GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/0, // DstI[vdata]
        GIR_AddSimpleTempRegister, /*InsnID*/0, /*TempRegID*/0,
        GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/1, // rsrc
        GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/0, // soffset
        GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/5, // offset
        GIR_CustomOperandRenderer, /*InsnID*/0, /*OldInsnID*/0, /*OpIdx*/6, /*OperandRenderer*/GIMT_Encode2(GICR_renderExtractCPol), // auxiliary
        GIR_CustomOperandRenderer, /*InsnID*/0, /*OldInsnID*/0, /*OpIdx*/6, /*OperandRenderer*/GIMT_Encode2(GICR_renderExtractSWZ), // auxiliary
        GIR_MergeMemOperands, /*InsnID*/0, /*NumInsns*/1, /*MergeInsnID's*/0,
        GIR_ConstrainSelectedInstOperands, /*InsnID*/0,
        GIR_EraseFromParent, /*InsnID*/0,
        // GIR_Coverage, 4044,
        GIR_Done,
      // Label 6604: @484836
      GIM_Try, /*On fail goto*//*Label 6605*/ GIMT_Encode4(484946), // Rule ID 4048 //
        GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasPackedD16VMem),
        // MIs[0] offset
        GIM_CheckIsImm, /*MI*/0, /*Op*/5,
        // MIs[0] auxiliary
        GIM_CheckIsImm, /*MI*/0, /*Op*/6,
        // MIs[0] Operand 7
        GIM_CheckIsImm, /*MI*/0, /*Op*/7,
        GIM_CheckComplexPattern, /*MI*/0, /*Op*/4, /*Renderer*/GIMT_Encode2(0), GIMT_Encode2(GICP_gi_buf_soffset),
        // (SIbuffer_load_format_d16:{ *:[i16] } v4i32:{ *:[v4i32] }:$rsrc, i32:{ *:[i32] }:$vindex, i32:{ *:[i32] }:$voffset, (BUFSOffset:{ *:[i32] } i32:{ *:[i32] }:$soffset), (timm:{ *:[i32] }):$offset, (timm:{ *:[i32] }):$auxiliary, (timm:{ *:[i1] }))  =>  (BUFFER_LOAD_FORMAT_D16_X_VBUFFER_BOTHEN:{ *:[i16] } (REG_SEQUENCE:{ *:[i64] } VReg_64:{ *:[i32] }, VGPR_32:{ *:[i32] }:$vindex, sub0:{ *:[i32] }, VGPR_32:{ *:[i32] }:$voffset, sub1:{ *:[i32] }), SReg_128:{ *:[v4i32] }:$rsrc, SCSrc_b32:{ *:[i32] }:$soffset, (timm:{ *:[i32] }):$offset, (extract_cpol:{ *:[i32] } ?:{ *:[i32] }:$auxiliary), (extract_swz:{ *:[i1] } ?:{ *:[i32] }:$auxiliary))
        GIR_MakeTempReg, /*TempRegID*/0, /*TypeID*/GILLT_s64,
        GIR_BuildMI, /*InsnID*/1, /*Opcode*/GIMT_Encode2(TargetOpcode::REG_SEQUENCE),
        GIR_AddTempRegister, /*InsnID*/1, /*TempRegID*/0, /*TempRegFlags*/GIMT_Encode2(RegState::Define),
        GIR_Copy, /*NewInsnID*/1, /*OldInsnID*/0, /*OpIdx*/2, // vindex
        GIR_AddImm8, /*InsnID*/1, /*SubRegIndex*/3,
        GIR_Copy, /*NewInsnID*/1, /*OldInsnID*/0, /*OpIdx*/3, // voffset
        GIR_AddImm8, /*InsnID*/1, /*SubRegIndex*/11,
        GIR_ConstrainOperandRC, /*InsnID*/1, /*Op*/0, GIMT_Encode2(AMDGPU::VReg_64RegClassID),
        GIR_ConstrainOperandRC, /*InsnID*/1, /*Op*/1, GIMT_Encode2(AMDGPU::VGPR_32RegClassID),
        GIR_ConstrainOperandRC, /*InsnID*/1, /*Op*/3, GIMT_Encode2(AMDGPU::VGPR_32RegClassID),
        GIR_BuildMI, /*InsnID*/0, /*Opcode*/GIMT_Encode2(AMDGPU::BUFFER_LOAD_FORMAT_D16_X_VBUFFER_BOTHEN),
        GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/0, // DstI[vdata]
        GIR_AddSimpleTempRegister, /*InsnID*/0, /*TempRegID*/0,
        GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/1, // rsrc
        GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/0, // soffset
        GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/5, // offset
        GIR_CustomOperandRenderer, /*InsnID*/0, /*OldInsnID*/0, /*OpIdx*/6, /*OperandRenderer*/GIMT_Encode2(GICR_renderExtractCPol), // auxiliary
        GIR_CustomOperandRenderer, /*InsnID*/0, /*OldInsnID*/0, /*OpIdx*/6, /*OperandRenderer*/GIMT_Encode2(GICR_renderExtractSWZ), // auxiliary
        GIR_MergeMemOperands, /*InsnID*/0, /*NumInsns*/1, /*MergeInsnID's*/0,
        GIR_ConstrainSelectedInstOperands, /*InsnID*/0,
        GIR_EraseFromParent, /*InsnID*/0,
        // GIR_Coverage, 4048,
        GIR_Done,
      // Label 6605: @484946
      GIM_Reject,
    // Label 6581: @484947
    GIM_Reject,
    // Label 6574: @484948
    GIM_Try, /*On fail goto*//*Label 6606*/ GIMT_Encode4(486019),
      GIM_CheckType, /*MI*/0, /*Op*/1, /*Type*/GILLT_v4s32,
      GIM_CheckType, /*MI*/0, /*Op*/2, /*Type*/GILLT_s32,
      GIM_CheckType, /*MI*/0, /*Op*/3, /*Type*/GILLT_s32,
      GIM_CheckType, /*MI*/0, /*Op*/4, /*Type*/GILLT_s32,
      GIM_CheckRegBankForClass, /*MI*/0, /*Op*/0, /*RC*/GIMT_Encode2(AMDGPU::AV_32RegClassID),
      GIM_Try, /*On fail goto*//*Label 6607*/ GIMT_Encode4(485056), // Rule ID 4017 //
        GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasUnpackedD16VMem),
        GIM_CheckConstantInt8, /*MI*/0, /*Op*/2, 0,
        GIM_CheckConstantInt8, /*MI*/0, /*Op*/3, 0,
        // MIs[0] offset
        GIM_CheckIsImm, /*MI*/0, /*Op*/5,
        // MIs[0] auxiliary
        GIM_CheckIsImm, /*MI*/0, /*Op*/6,
        // MIs[0] Operand 7
        GIM_CheckLiteralInt, /*MI*/0, /*Op*/7, GIMT_Encode8(0),
        GIM_CheckComplexPattern, /*MI*/0, /*Op*/4, /*Renderer*/GIMT_Encode2(0), GIMT_Encode2(GICP_gi_buf_soffset),
        // (SIbuffer_load_format_d16:{ *:[i32] } v4i32:{ *:[v4i32] }:$rsrc, 0:{ *:[i32] }, 0:{ *:[i32] }, (BUFSOffset:{ *:[i32] } i32:{ *:[i32] }:$soffset), (timm:{ *:[i32] }):$offset, (timm:{ *:[i32] }):$auxiliary, 0:{ *:[i1] })  =>  (BUFFER_LOAD_FORMAT_D16_X_gfx80_OFFSET:{ *:[i32] } SReg_128:{ *:[v4i32] }:$rsrc, SCSrc_b32:{ *:[i32] }:$soffset, (timm:{ *:[i32] }):$offset, (extract_cpol:{ *:[i32] } ?:{ *:[i32] }:$auxiliary), (extract_swz:{ *:[i1] } ?:{ *:[i32] }:$auxiliary))
        GIR_BuildMI, /*InsnID*/0, /*Opcode*/GIMT_Encode2(AMDGPU::BUFFER_LOAD_FORMAT_D16_X_gfx80_OFFSET),
        GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/0, // DstI[vdata]
        GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/1, // rsrc
        GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/0, // soffset
        GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/5, // offset
        GIR_CustomOperandRenderer, /*InsnID*/0, /*OldInsnID*/0, /*OpIdx*/6, /*OperandRenderer*/GIMT_Encode2(GICR_renderExtractCPol), // auxiliary
        GIR_CustomOperandRenderer, /*InsnID*/0, /*OldInsnID*/0, /*OpIdx*/6, /*OperandRenderer*/GIMT_Encode2(GICR_renderExtractSWZ), // auxiliary
        GIR_MergeMemOperands, /*InsnID*/0, /*NumInsns*/1, /*MergeInsnID's*/0,
        GIR_ConstrainSelectedInstOperands, /*InsnID*/0,
        GIR_EraseFromParent, /*InsnID*/0,
        // GIR_Coverage, 4017,
        GIR_Done,
      // Label 6607: @485056
      GIM_Try, /*On fail goto*//*Label 6608*/ GIMT_Encode4(485138), // Rule ID 4049 //
        GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasPackedD16VMem_HasUnrestrictedSOffset),
        GIM_CheckConstantInt8, /*MI*/0, /*Op*/2, 0,
        GIM_CheckConstantInt8, /*MI*/0, /*Op*/3, 0,
        // MIs[0] offset
        GIM_CheckIsImm, /*MI*/0, /*Op*/5,
        // MIs[0] auxiliary
        GIM_CheckIsImm, /*MI*/0, /*Op*/6,
        // MIs[0] Operand 7
        GIM_CheckLiteralInt, /*MI*/0, /*Op*/7, GIMT_Encode8(0),
        GIM_CheckComplexPattern, /*MI*/0, /*Op*/4, /*Renderer*/GIMT_Encode2(0), GIMT_Encode2(GICP_gi_buf_soffset),
        // (SIbuffer_load_format_d16:{ *:[i32] } v4i32:{ *:[v4i32] }:$rsrc, 0:{ *:[i32] }, 0:{ *:[i32] }, (BUFSOffset:{ *:[i32] } i32:{ *:[i32] }:$soffset), (timm:{ *:[i32] }):$offset, (timm:{ *:[i32] }):$auxiliary, 0:{ *:[i1] })  =>  (BUFFER_LOAD_FORMAT_D16_X_OFFSET:{ *:[i32] } SReg_128:{ *:[v4i32] }:$rsrc, SCSrc_b32:{ *:[i32] }:$soffset, (timm:{ *:[i32] }):$offset, (extract_cpol:{ *:[i32] } ?:{ *:[i32] }:$auxiliary), (extract_swz:{ *:[i1] } ?:{ *:[i32] }:$auxiliary))
        GIR_BuildMI, /*InsnID*/0, /*Opcode*/GIMT_Encode2(AMDGPU::BUFFER_LOAD_FORMAT_D16_X_OFFSET),
        GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/0, // DstI[vdata]
        GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/1, // rsrc
        GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/0, // soffset
        GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/5, // offset
        GIR_CustomOperandRenderer, /*InsnID*/0, /*OldInsnID*/0, /*OpIdx*/6, /*OperandRenderer*/GIMT_Encode2(GICR_renderExtractCPol), // auxiliary
        GIR_CustomOperandRenderer, /*InsnID*/0, /*OldInsnID*/0, /*OpIdx*/6, /*OperandRenderer*/GIMT_Encode2(GICR_renderExtractSWZ), // auxiliary
        GIR_MergeMemOperands, /*InsnID*/0, /*NumInsns*/1, /*MergeInsnID's*/0,
        GIR_ConstrainSelectedInstOperands, /*InsnID*/0,
        GIR_EraseFromParent, /*InsnID*/0,
        // GIR_Coverage, 4049,
        GIR_Done,
      // Label 6608: @485138
      GIM_Try, /*On fail goto*//*Label 6609*/ GIMT_Encode4(485220), // Rule ID 4053 //
        GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasPackedD16VMem),
        GIM_CheckConstantInt8, /*MI*/0, /*Op*/2, 0,
        GIM_CheckConstantInt8, /*MI*/0, /*Op*/3, 0,
        // MIs[0] offset
        GIM_CheckIsImm, /*MI*/0, /*Op*/5,
        // MIs[0] auxiliary
        GIM_CheckIsImm, /*MI*/0, /*Op*/6,
        // MIs[0] Operand 7
        GIM_CheckLiteralInt, /*MI*/0, /*Op*/7, GIMT_Encode8(0),
        GIM_CheckComplexPattern, /*MI*/0, /*Op*/4, /*Renderer*/GIMT_Encode2(0), GIMT_Encode2(GICP_gi_buf_soffset),
        // (SIbuffer_load_format_d16:{ *:[i32] } v4i32:{ *:[v4i32] }:$rsrc, 0:{ *:[i32] }, 0:{ *:[i32] }, (BUFSOffset:{ *:[i32] } i32:{ *:[i32] }:$soffset), (timm:{ *:[i32] }):$offset, (timm:{ *:[i32] }):$auxiliary, 0:{ *:[i1] })  =>  (BUFFER_LOAD_FORMAT_D16_X_VBUFFER_OFFSET:{ *:[i32] } SReg_128:{ *:[v4i32] }:$rsrc, SCSrc_b32:{ *:[i32] }:$soffset, (timm:{ *:[i32] }):$offset, (extract_cpol:{ *:[i32] } ?:{ *:[i32] }:$auxiliary), (extract_swz:{ *:[i1] } ?:{ *:[i32] }:$auxiliary))
        GIR_BuildMI, /*InsnID*/0, /*Opcode*/GIMT_Encode2(AMDGPU::BUFFER_LOAD_FORMAT_D16_X_VBUFFER_OFFSET),
        GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/0, // DstI[vdata]
        GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/1, // rsrc
        GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/0, // soffset
        GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/5, // offset
        GIR_CustomOperandRenderer, /*InsnID*/0, /*OldInsnID*/0, /*OpIdx*/6, /*OperandRenderer*/GIMT_Encode2(GICR_renderExtractCPol), // auxiliary
        GIR_CustomOperandRenderer, /*InsnID*/0, /*OldInsnID*/0, /*OpIdx*/6, /*OperandRenderer*/GIMT_Encode2(GICR_renderExtractSWZ), // auxiliary
        GIR_MergeMemOperands, /*InsnID*/0, /*NumInsns*/1, /*MergeInsnID's*/0,
        GIR_ConstrainSelectedInstOperands, /*InsnID*/0,
        GIR_EraseFromParent, /*InsnID*/0,
        // GIR_Coverage, 4053,
        GIR_Done,
      // Label 6609: @485220
      GIM_Try, /*On fail goto*//*Label 6610*/ GIMT_Encode4(485302), // Rule ID 4018 //
        GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasUnpackedD16VMem),
        GIM_CheckConstantInt8, /*MI*/0, /*Op*/2, 0,
        // MIs[0] offset
        GIM_CheckIsImm, /*MI*/0, /*Op*/5,
        // MIs[0] auxiliary
        GIM_CheckIsImm, /*MI*/0, /*Op*/6,
        // MIs[0] Operand 7
        GIM_CheckLiteralInt, /*MI*/0, /*Op*/7, GIMT_Encode8(0),
        GIM_CheckComplexPattern, /*MI*/0, /*Op*/4, /*Renderer*/GIMT_Encode2(0), GIMT_Encode2(GICP_gi_buf_soffset),
        // (SIbuffer_load_format_d16:{ *:[i32] } v4i32:{ *:[v4i32] }:$rsrc, 0:{ *:[i32] }, i32:{ *:[i32] }:$voffset, (BUFSOffset:{ *:[i32] } i32:{ *:[i32] }:$soffset), (timm:{ *:[i32] }):$offset, (timm:{ *:[i32] }):$auxiliary, 0:{ *:[i1] })  =>  (BUFFER_LOAD_FORMAT_D16_X_gfx80_OFFEN:{ *:[i32] } VGPR_32:{ *:[i32] }:$voffset, SReg_128:{ *:[v4i32] }:$rsrc, SCSrc_b32:{ *:[i32] }:$soffset, (timm:{ *:[i32] }):$offset, (extract_cpol:{ *:[i32] } ?:{ *:[i32] }:$auxiliary), (extract_swz:{ *:[i1] } ?:{ *:[i32] }:$auxiliary))
        GIR_BuildMI, /*InsnID*/0, /*Opcode*/GIMT_Encode2(AMDGPU::BUFFER_LOAD_FORMAT_D16_X_gfx80_OFFEN),
        GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/0, // DstI[vdata]
        GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/3, // voffset
        GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/1, // rsrc
        GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/0, // soffset
        GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/5, // offset
        GIR_CustomOperandRenderer, /*InsnID*/0, /*OldInsnID*/0, /*OpIdx*/6, /*OperandRenderer*/GIMT_Encode2(GICR_renderExtractCPol), // auxiliary
        GIR_CustomOperandRenderer, /*InsnID*/0, /*OldInsnID*/0, /*OpIdx*/6, /*OperandRenderer*/GIMT_Encode2(GICR_renderExtractSWZ), // auxiliary
        GIR_MergeMemOperands, /*InsnID*/0, /*NumInsns*/1, /*MergeInsnID's*/0,
        GIR_ConstrainSelectedInstOperands, /*InsnID*/0,
        GIR_EraseFromParent, /*InsnID*/0,
        // GIR_Coverage, 4018,
        GIR_Done,
      // Label 6610: @485302
      GIM_Try, /*On fail goto*//*Label 6611*/ GIMT_Encode4(485384), // Rule ID 4050 //
        GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasPackedD16VMem_HasUnrestrictedSOffset),
        GIM_CheckConstantInt8, /*MI*/0, /*Op*/2, 0,
        // MIs[0] offset
        GIM_CheckIsImm, /*MI*/0, /*Op*/5,
        // MIs[0] auxiliary
        GIM_CheckIsImm, /*MI*/0, /*Op*/6,
        // MIs[0] Operand 7
        GIM_CheckLiteralInt, /*MI*/0, /*Op*/7, GIMT_Encode8(0),
        GIM_CheckComplexPattern, /*MI*/0, /*Op*/4, /*Renderer*/GIMT_Encode2(0), GIMT_Encode2(GICP_gi_buf_soffset),
        // (SIbuffer_load_format_d16:{ *:[i32] } v4i32:{ *:[v4i32] }:$rsrc, 0:{ *:[i32] }, i32:{ *:[i32] }:$voffset, (BUFSOffset:{ *:[i32] } i32:{ *:[i32] }:$soffset), (timm:{ *:[i32] }):$offset, (timm:{ *:[i32] }):$auxiliary, 0:{ *:[i1] })  =>  (BUFFER_LOAD_FORMAT_D16_X_OFFEN:{ *:[i32] } VGPR_32:{ *:[i32] }:$voffset, SReg_128:{ *:[v4i32] }:$rsrc, SCSrc_b32:{ *:[i32] }:$soffset, (timm:{ *:[i32] }):$offset, (extract_cpol:{ *:[i32] } ?:{ *:[i32] }:$auxiliary), (extract_swz:{ *:[i1] } ?:{ *:[i32] }:$auxiliary))
        GIR_BuildMI, /*InsnID*/0, /*Opcode*/GIMT_Encode2(AMDGPU::BUFFER_LOAD_FORMAT_D16_X_OFFEN),
        GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/0, // DstI[vdata]
        GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/3, // voffset
        GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/1, // rsrc
        GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/0, // soffset
        GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/5, // offset
        GIR_CustomOperandRenderer, /*InsnID*/0, /*OldInsnID*/0, /*OpIdx*/6, /*OperandRenderer*/GIMT_Encode2(GICR_renderExtractCPol), // auxiliary
        GIR_CustomOperandRenderer, /*InsnID*/0, /*OldInsnID*/0, /*OpIdx*/6, /*OperandRenderer*/GIMT_Encode2(GICR_renderExtractSWZ), // auxiliary
        GIR_MergeMemOperands, /*InsnID*/0, /*NumInsns*/1, /*MergeInsnID's*/0,
        GIR_ConstrainSelectedInstOperands, /*InsnID*/0,
        GIR_EraseFromParent, /*InsnID*/0,
        // GIR_Coverage, 4050,
        GIR_Done,
      // Label 6611: @485384
      GIM_Try, /*On fail goto*//*Label 6612*/ GIMT_Encode4(485466), // Rule ID 4054 //
        GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasPackedD16VMem),
        GIM_CheckConstantInt8, /*MI*/0, /*Op*/2, 0,
        // MIs[0] offset
        GIM_CheckIsImm, /*MI*/0, /*Op*/5,
        // MIs[0] auxiliary
        GIM_CheckIsImm, /*MI*/0, /*Op*/6,
        // MIs[0] Operand 7
        GIM_CheckLiteralInt, /*MI*/0, /*Op*/7, GIMT_Encode8(0),
        GIM_CheckComplexPattern, /*MI*/0, /*Op*/4, /*Renderer*/GIMT_Encode2(0), GIMT_Encode2(GICP_gi_buf_soffset),
        // (SIbuffer_load_format_d16:{ *:[i32] } v4i32:{ *:[v4i32] }:$rsrc, 0:{ *:[i32] }, i32:{ *:[i32] }:$voffset, (BUFSOffset:{ *:[i32] } i32:{ *:[i32] }:$soffset), (timm:{ *:[i32] }):$offset, (timm:{ *:[i32] }):$auxiliary, 0:{ *:[i1] })  =>  (BUFFER_LOAD_FORMAT_D16_X_VBUFFER_OFFEN:{ *:[i32] } VGPR_32:{ *:[i32] }:$voffset, SReg_128:{ *:[v4i32] }:$rsrc, SCSrc_b32:{ *:[i32] }:$soffset, (timm:{ *:[i32] }):$offset, (extract_cpol:{ *:[i32] } ?:{ *:[i32] }:$auxiliary), (extract_swz:{ *:[i1] } ?:{ *:[i32] }:$auxiliary))
        GIR_BuildMI, /*InsnID*/0, /*Opcode*/GIMT_Encode2(AMDGPU::BUFFER_LOAD_FORMAT_D16_X_VBUFFER_OFFEN),
        GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/0, // DstI[vdata]
        GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/3, // voffset
        GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/1, // rsrc
        GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/0, // soffset
        GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/5, // offset
        GIR_CustomOperandRenderer, /*InsnID*/0, /*OldInsnID*/0, /*OpIdx*/6, /*OperandRenderer*/GIMT_Encode2(GICR_renderExtractCPol), // auxiliary
        GIR_CustomOperandRenderer, /*InsnID*/0, /*OldInsnID*/0, /*OpIdx*/6, /*OperandRenderer*/GIMT_Encode2(GICR_renderExtractSWZ), // auxiliary
        GIR_MergeMemOperands, /*InsnID*/0, /*NumInsns*/1, /*MergeInsnID's*/0,
        GIR_ConstrainSelectedInstOperands, /*InsnID*/0,
        GIR_EraseFromParent, /*InsnID*/0,
        // GIR_Coverage, 4054,
        GIR_Done,
      // Label 6612: @485466
      GIM_Try, /*On fail goto*//*Label 6613*/ GIMT_Encode4(485540), // Rule ID 4019 //
        GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasUnpackedD16VMem),
        GIM_CheckConstantInt8, /*MI*/0, /*Op*/3, 0,
        // MIs[0] offset
        GIM_CheckIsImm, /*MI*/0, /*Op*/5,
        // MIs[0] auxiliary
        GIM_CheckIsImm, /*MI*/0, /*Op*/6,
        // MIs[0] Operand 7
        GIM_CheckIsImm, /*MI*/0, /*Op*/7,
        GIM_CheckComplexPattern, /*MI*/0, /*Op*/4, /*Renderer*/GIMT_Encode2(0), GIMT_Encode2(GICP_gi_buf_soffset),
        // (SIbuffer_load_format_d16:{ *:[i32] } v4i32:{ *:[v4i32] }:$rsrc, i32:{ *:[i32] }:$vindex, 0:{ *:[i32] }, (BUFSOffset:{ *:[i32] } i32:{ *:[i32] }:$soffset), (timm:{ *:[i32] }):$offset, (timm:{ *:[i32] }):$auxiliary, (timm:{ *:[i1] }))  =>  (BUFFER_LOAD_FORMAT_D16_X_gfx80_IDXEN:{ *:[i32] } VGPR_32:{ *:[i32] }:$vindex, SReg_128:{ *:[v4i32] }:$rsrc, SCSrc_b32:{ *:[i32] }:$soffset, (timm:{ *:[i32] }):$offset, (extract_cpol:{ *:[i32] } ?:{ *:[i32] }:$auxiliary), (extract_swz:{ *:[i1] } ?:{ *:[i32] }:$auxiliary))
        GIR_BuildMI, /*InsnID*/0, /*Opcode*/GIMT_Encode2(AMDGPU::BUFFER_LOAD_FORMAT_D16_X_gfx80_IDXEN),
        GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/0, // DstI[vdata]
        GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/2, // vindex
        GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/1, // rsrc
        GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/0, // soffset
        GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/5, // offset
        GIR_CustomOperandRenderer, /*InsnID*/0, /*OldInsnID*/0, /*OpIdx*/6, /*OperandRenderer*/GIMT_Encode2(GICR_renderExtractCPol), // auxiliary
        GIR_CustomOperandRenderer, /*InsnID*/0, /*OldInsnID*/0, /*OpIdx*/6, /*OperandRenderer*/GIMT_Encode2(GICR_renderExtractSWZ), // auxiliary
        GIR_MergeMemOperands, /*InsnID*/0, /*NumInsns*/1, /*MergeInsnID's*/0,
        GIR_ConstrainSelectedInstOperands, /*InsnID*/0,
        GIR_EraseFromParent, /*InsnID*/0,
        // GIR_Coverage, 4019,
        GIR_Done,
      // Label 6613: @485540
      GIM_Try, /*On fail goto*//*Label 6614*/ GIMT_Encode4(485614), // Rule ID 4051 //
        GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasPackedD16VMem_HasUnrestrictedSOffset),
        GIM_CheckConstantInt8, /*MI*/0, /*Op*/3, 0,
        // MIs[0] offset
        GIM_CheckIsImm, /*MI*/0, /*Op*/5,
        // MIs[0] auxiliary
        GIM_CheckIsImm, /*MI*/0, /*Op*/6,
        // MIs[0] Operand 7
        GIM_CheckIsImm, /*MI*/0, /*Op*/7,
        GIM_CheckComplexPattern, /*MI*/0, /*Op*/4, /*Renderer*/GIMT_Encode2(0), GIMT_Encode2(GICP_gi_buf_soffset),
        // (SIbuffer_load_format_d16:{ *:[i32] } v4i32:{ *:[v4i32] }:$rsrc, i32:{ *:[i32] }:$vindex, 0:{ *:[i32] }, (BUFSOffset:{ *:[i32] } i32:{ *:[i32] }:$soffset), (timm:{ *:[i32] }):$offset, (timm:{ *:[i32] }):$auxiliary, (timm:{ *:[i1] }))  =>  (BUFFER_LOAD_FORMAT_D16_X_IDXEN:{ *:[i32] } VGPR_32:{ *:[i32] }:$vindex, SReg_128:{ *:[v4i32] }:$rsrc, SCSrc_b32:{ *:[i32] }:$soffset, (timm:{ *:[i32] }):$offset, (extract_cpol:{ *:[i32] } ?:{ *:[i32] }:$auxiliary), (extract_swz:{ *:[i1] } ?:{ *:[i32] }:$auxiliary))
        GIR_BuildMI, /*InsnID*/0, /*Opcode*/GIMT_Encode2(AMDGPU::BUFFER_LOAD_FORMAT_D16_X_IDXEN),
        GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/0, // DstI[vdata]
        GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/2, // vindex
        GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/1, // rsrc
        GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/0, // soffset
        GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/5, // offset
        GIR_CustomOperandRenderer, /*InsnID*/0, /*OldInsnID*/0, /*OpIdx*/6, /*OperandRenderer*/GIMT_Encode2(GICR_renderExtractCPol), // auxiliary
        GIR_CustomOperandRenderer, /*InsnID*/0, /*OldInsnID*/0, /*OpIdx*/6, /*OperandRenderer*/GIMT_Encode2(GICR_renderExtractSWZ), // auxiliary
        GIR_MergeMemOperands, /*InsnID*/0, /*NumInsns*/1, /*MergeInsnID's*/0,
        GIR_ConstrainSelectedInstOperands, /*InsnID*/0,
        GIR_EraseFromParent, /*InsnID*/0,
        // GIR_Coverage, 4051,
        GIR_Done,
      // Label 6614: @485614
      GIM_Try, /*On fail goto*//*Label 6615*/ GIMT_Encode4(485688), // Rule ID 4055 //
        GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasPackedD16VMem),
        GIM_CheckConstantInt8, /*MI*/0, /*Op*/3, 0,
        // MIs[0] offset
        GIM_CheckIsImm, /*MI*/0, /*Op*/5,
        // MIs[0] auxiliary
        GIM_CheckIsImm, /*MI*/0, /*Op*/6,
        // MIs[0] Operand 7
        GIM_CheckIsImm, /*MI*/0, /*Op*/7,
        GIM_CheckComplexPattern, /*MI*/0, /*Op*/4, /*Renderer*/GIMT_Encode2(0), GIMT_Encode2(GICP_gi_buf_soffset),
        // (SIbuffer_load_format_d16:{ *:[i32] } v4i32:{ *:[v4i32] }:$rsrc, i32:{ *:[i32] }:$vindex, 0:{ *:[i32] }, (BUFSOffset:{ *:[i32] } i32:{ *:[i32] }:$soffset), (timm:{ *:[i32] }):$offset, (timm:{ *:[i32] }):$auxiliary, (timm:{ *:[i1] }))  =>  (BUFFER_LOAD_FORMAT_D16_X_VBUFFER_IDXEN:{ *:[i32] } VGPR_32:{ *:[i32] }:$vindex, SReg_128:{ *:[v4i32] }:$rsrc, SCSrc_b32:{ *:[i32] }:$soffset, (timm:{ *:[i32] }):$offset, (extract_cpol:{ *:[i32] } ?:{ *:[i32] }:$auxiliary), (extract_swz:{ *:[i1] } ?:{ *:[i32] }:$auxiliary))
        GIR_BuildMI, /*InsnID*/0, /*Opcode*/GIMT_Encode2(AMDGPU::BUFFER_LOAD_FORMAT_D16_X_VBUFFER_IDXEN),
        GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/0, // DstI[vdata]
        GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/2, // vindex
        GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/1, // rsrc
        GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/0, // soffset
        GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/5, // offset
        GIR_CustomOperandRenderer, /*InsnID*/0, /*OldInsnID*/0, /*OpIdx*/6, /*OperandRenderer*/GIMT_Encode2(GICR_renderExtractCPol), // auxiliary
        GIR_CustomOperandRenderer, /*InsnID*/0, /*OldInsnID*/0, /*OpIdx*/6, /*OperandRenderer*/GIMT_Encode2(GICR_renderExtractSWZ), // auxiliary
        GIR_MergeMemOperands, /*InsnID*/0, /*NumInsns*/1, /*MergeInsnID's*/0,
        GIR_ConstrainSelectedInstOperands, /*InsnID*/0,
        GIR_EraseFromParent, /*InsnID*/0,
        // GIR_Coverage, 4055,
        GIR_Done,
      // Label 6615: @485688
      GIM_Try, /*On fail goto*//*Label 6616*/ GIMT_Encode4(485798), // Rule ID 4020 //
        GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasUnpackedD16VMem),
        // MIs[0] offset
        GIM_CheckIsImm, /*MI*/0, /*Op*/5,
        // MIs[0] auxiliary
        GIM_CheckIsImm, /*MI*/0, /*Op*/6,
        // MIs[0] Operand 7
        GIM_CheckIsImm, /*MI*/0, /*Op*/7,
        GIM_CheckComplexPattern, /*MI*/0, /*Op*/4, /*Renderer*/GIMT_Encode2(0), GIMT_Encode2(GICP_gi_buf_soffset),
        // (SIbuffer_load_format_d16:{ *:[i32] } v4i32:{ *:[v4i32] }:$rsrc, i32:{ *:[i32] }:$vindex, i32:{ *:[i32] }:$voffset, (BUFSOffset:{ *:[i32] } i32:{ *:[i32] }:$soffset), (timm:{ *:[i32] }):$offset, (timm:{ *:[i32] }):$auxiliary, (timm:{ *:[i1] }))  =>  (BUFFER_LOAD_FORMAT_D16_X_gfx80_BOTHEN:{ *:[i32] } (REG_SEQUENCE:{ *:[i64] } VReg_64:{ *:[i32] }, VGPR_32:{ *:[i32] }:$vindex, sub0:{ *:[i32] }, VGPR_32:{ *:[i32] }:$voffset, sub1:{ *:[i32] }), SReg_128:{ *:[v4i32] }:$rsrc, SCSrc_b32:{ *:[i32] }:$soffset, (timm:{ *:[i32] }):$offset, (extract_cpol:{ *:[i32] } ?:{ *:[i32] }:$auxiliary), (extract_swz:{ *:[i1] } ?:{ *:[i32] }:$auxiliary))
        GIR_MakeTempReg, /*TempRegID*/0, /*TypeID*/GILLT_s64,
        GIR_BuildMI, /*InsnID*/1, /*Opcode*/GIMT_Encode2(TargetOpcode::REG_SEQUENCE),
        GIR_AddTempRegister, /*InsnID*/1, /*TempRegID*/0, /*TempRegFlags*/GIMT_Encode2(RegState::Define),
        GIR_Copy, /*NewInsnID*/1, /*OldInsnID*/0, /*OpIdx*/2, // vindex
        GIR_AddImm8, /*InsnID*/1, /*SubRegIndex*/3,
        GIR_Copy, /*NewInsnID*/1, /*OldInsnID*/0, /*OpIdx*/3, // voffset
        GIR_AddImm8, /*InsnID*/1, /*SubRegIndex*/11,
        GIR_ConstrainOperandRC, /*InsnID*/1, /*Op*/0, GIMT_Encode2(AMDGPU::VReg_64RegClassID),
        GIR_ConstrainOperandRC, /*InsnID*/1, /*Op*/1, GIMT_Encode2(AMDGPU::VGPR_32RegClassID),
        GIR_ConstrainOperandRC, /*InsnID*/1, /*Op*/3, GIMT_Encode2(AMDGPU::VGPR_32RegClassID),
        GIR_BuildMI, /*InsnID*/0, /*Opcode*/GIMT_Encode2(AMDGPU::BUFFER_LOAD_FORMAT_D16_X_gfx80_BOTHEN),
        GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/0, // DstI[vdata]
        GIR_AddSimpleTempRegister, /*InsnID*/0, /*TempRegID*/0,
        GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/1, // rsrc
        GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/0, // soffset
        GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/5, // offset
        GIR_CustomOperandRenderer, /*InsnID*/0, /*OldInsnID*/0, /*OpIdx*/6, /*OperandRenderer*/GIMT_Encode2(GICR_renderExtractCPol), // auxiliary
        GIR_CustomOperandRenderer, /*InsnID*/0, /*OldInsnID*/0, /*OpIdx*/6, /*OperandRenderer*/GIMT_Encode2(GICR_renderExtractSWZ), // auxiliary
        GIR_MergeMemOperands, /*InsnID*/0, /*NumInsns*/1, /*MergeInsnID's*/0,
        GIR_ConstrainSelectedInstOperands, /*InsnID*/0,
        GIR_EraseFromParent, /*InsnID*/0,
        // GIR_Coverage, 4020,
        GIR_Done,
      // Label 6616: @485798
      GIM_Try, /*On fail goto*//*Label 6617*/ GIMT_Encode4(485908), // Rule ID 4052 //
        GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasPackedD16VMem_HasUnrestrictedSOffset),
        // MIs[0] offset
        GIM_CheckIsImm, /*MI*/0, /*Op*/5,
        // MIs[0] auxiliary
        GIM_CheckIsImm, /*MI*/0, /*Op*/6,
        // MIs[0] Operand 7
        GIM_CheckIsImm, /*MI*/0, /*Op*/7,
        GIM_CheckComplexPattern, /*MI*/0, /*Op*/4, /*Renderer*/GIMT_Encode2(0), GIMT_Encode2(GICP_gi_buf_soffset),
        // (SIbuffer_load_format_d16:{ *:[i32] } v4i32:{ *:[v4i32] }:$rsrc, i32:{ *:[i32] }:$vindex, i32:{ *:[i32] }:$voffset, (BUFSOffset:{ *:[i32] } i32:{ *:[i32] }:$soffset), (timm:{ *:[i32] }):$offset, (timm:{ *:[i32] }):$auxiliary, (timm:{ *:[i1] }))  =>  (BUFFER_LOAD_FORMAT_D16_X_BOTHEN:{ *:[i32] } (REG_SEQUENCE:{ *:[i64] } VReg_64:{ *:[i32] }, VGPR_32:{ *:[i32] }:$vindex, sub0:{ *:[i32] }, VGPR_32:{ *:[i32] }:$voffset, sub1:{ *:[i32] }), SReg_128:{ *:[v4i32] }:$rsrc, SCSrc_b32:{ *:[i32] }:$soffset, (timm:{ *:[i32] }):$offset, (extract_cpol:{ *:[i32] } ?:{ *:[i32] }:$auxiliary), (extract_swz:{ *:[i1] } ?:{ *:[i32] }:$auxiliary))
        GIR_MakeTempReg, /*TempRegID*/0, /*TypeID*/GILLT_s64,
        GIR_BuildMI, /*InsnID*/1, /*Opcode*/GIMT_Encode2(TargetOpcode::REG_SEQUENCE),
        GIR_AddTempRegister, /*InsnID*/1, /*TempRegID*/0, /*TempRegFlags*/GIMT_Encode2(RegState::Define),
        GIR_Copy, /*NewInsnID*/1, /*OldInsnID*/0, /*OpIdx*/2, // vindex
        GIR_AddImm8, /*InsnID*/1, /*SubRegIndex*/3,
        GIR_Copy, /*NewInsnID*/1, /*OldInsnID*/0, /*OpIdx*/3, // voffset
        GIR_AddImm8, /*InsnID*/1, /*SubRegIndex*/11,
        GIR_ConstrainOperandRC, /*InsnID*/1, /*Op*/0, GIMT_Encode2(AMDGPU::VReg_64RegClassID),
        GIR_ConstrainOperandRC, /*InsnID*/1, /*Op*/1, GIMT_Encode2(AMDGPU::VGPR_32RegClassID),
        GIR_ConstrainOperandRC, /*InsnID*/1, /*Op*/3, GIMT_Encode2(AMDGPU::VGPR_32RegClassID),
        GIR_BuildMI, /*InsnID*/0, /*Opcode*/GIMT_Encode2(AMDGPU::BUFFER_LOAD_FORMAT_D16_X_BOTHEN),
        GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/0, // DstI[vdata]
        GIR_AddSimpleTempRegister, /*InsnID*/0, /*TempRegID*/0,
        GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/1, // rsrc
        GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/0, // soffset
        GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/5, // offset
        GIR_CustomOperandRenderer, /*InsnID*/0, /*OldInsnID*/0, /*OpIdx*/6, /*OperandRenderer*/GIMT_Encode2(GICR_renderExtractCPol), // auxiliary
        GIR_CustomOperandRenderer, /*InsnID*/0, /*OldInsnID*/0, /*OpIdx*/6, /*OperandRenderer*/GIMT_Encode2(GICR_renderExtractSWZ), // auxiliary
        GIR_MergeMemOperands, /*InsnID*/0, /*NumInsns*/1, /*MergeInsnID's*/0,
        GIR_ConstrainSelectedInstOperands, /*InsnID*/0,
        GIR_EraseFromParent, /*InsnID*/0,
        // GIR_Coverage, 4052,
        GIR_Done,
      // Label 6617: @485908
      GIM_Try, /*On fail goto*//*Label 6618*/ GIMT_Encode4(486018), // Rule ID 4056 //
        GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasPackedD16VMem),
        // MIs[0] offset
        GIM_CheckIsImm, /*MI*/0, /*Op*/5,
        // MIs[0] auxiliary
        GIM_CheckIsImm, /*MI*/0, /*Op*/6,
        // MIs[0] Operand 7
        GIM_CheckIsImm, /*MI*/0, /*Op*/7,
        GIM_CheckComplexPattern, /*MI*/0, /*Op*/4, /*Renderer*/GIMT_Encode2(0), GIMT_Encode2(GICP_gi_buf_soffset),
        // (SIbuffer_load_format_d16:{ *:[i32] } v4i32:{ *:[v4i32] }:$rsrc, i32:{ *:[i32] }:$vindex, i32:{ *:[i32] }:$voffset, (BUFSOffset:{ *:[i32] } i32:{ *:[i32] }:$soffset), (timm:{ *:[i32] }):$offset, (timm:{ *:[i32] }):$auxiliary, (timm:{ *:[i1] }))  =>  (BUFFER_LOAD_FORMAT_D16_X_VBUFFER_BOTHEN:{ *:[i32] } (REG_SEQUENCE:{ *:[i64] } VReg_64:{ *:[i32] }, VGPR_32:{ *:[i32] }:$vindex, sub0:{ *:[i32] }, VGPR_32:{ *:[i32] }:$voffset, sub1:{ *:[i32] }), SReg_128:{ *:[v4i32] }:$rsrc, SCSrc_b32:{ *:[i32] }:$soffset, (timm:{ *:[i32] }):$offset, (extract_cpol:{ *:[i32] } ?:{ *:[i32] }:$auxiliary), (extract_swz:{ *:[i1] } ?:{ *:[i32] }:$auxiliary))
        GIR_MakeTempReg, /*TempRegID*/0, /*TypeID*/GILLT_s64,
        GIR_BuildMI, /*InsnID*/1, /*Opcode*/GIMT_Encode2(TargetOpcode::REG_SEQUENCE),
        GIR_AddTempRegister, /*InsnID*/1, /*TempRegID*/0, /*TempRegFlags*/GIMT_Encode2(RegState::Define),
        GIR_Copy, /*NewInsnID*/1, /*OldInsnID*/0, /*OpIdx*/2, // vindex
        GIR_AddImm8, /*InsnID*/1, /*SubRegIndex*/3,
        GIR_Copy, /*NewInsnID*/1, /*OldInsnID*/0, /*OpIdx*/3, // voffset
        GIR_AddImm8, /*InsnID*/1, /*SubRegIndex*/11,
        GIR_ConstrainOperandRC, /*InsnID*/1, /*Op*/0, GIMT_Encode2(AMDGPU::VReg_64RegClassID),
        GIR_ConstrainOperandRC, /*InsnID*/1, /*Op*/1, GIMT_Encode2(AMDGPU::VGPR_32RegClassID),
        GIR_ConstrainOperandRC, /*InsnID*/1, /*Op*/3, GIMT_Encode2(AMDGPU::VGPR_32RegClassID),
        GIR_BuildMI, /*InsnID*/0, /*Opcode*/GIMT_Encode2(AMDGPU::BUFFER_LOAD_FORMAT_D16_X_VBUFFER_BOTHEN),
        GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/0, // DstI[vdata]
        GIR_AddSimpleTempRegister, /*InsnID*/0, /*TempRegID*/0,
        GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/1, // rsrc
        GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/0, // soffset
        GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/5, // offset
        GIR_CustomOperandRenderer, /*InsnID*/0, /*OldInsnID*/0, /*OpIdx*/6, /*OperandRenderer*/GIMT_Encode2(GICR_renderExtractCPol), // auxiliary
        GIR_CustomOperandRenderer, /*InsnID*/0, /*OldInsnID*/0, /*OpIdx*/6, /*OperandRenderer*/GIMT_Encode2(GICR_renderExtractSWZ), // auxiliary
        GIR_MergeMemOperands, /*InsnID*/0, /*NumInsns*/1, /*MergeInsnID's*/0,
        GIR_ConstrainSelectedInstOperands, /*InsnID*/0,
        GIR_EraseFromParent, /*InsnID*/0,
        // GIR_Coverage, 4056,
        GIR_Done,
      // Label 6618: @486018
      GIM_Reject,
    // Label 6606: @486019
    GIM_Reject,
    // Label 6575: @486020
    GIM_Try, /*On fail goto*//*Label 6619*/ GIMT_Encode4(487439),
      GIM_CheckType, /*MI*/0, /*Op*/1, /*Type*/GILLT_v4s32,
      GIM_CheckType, /*MI*/0, /*Op*/2, /*Type*/GILLT_s32,
      GIM_CheckType, /*MI*/0, /*Op*/3, /*Type*/GILLT_s32,
      GIM_CheckType, /*MI*/0, /*Op*/4, /*Type*/GILLT_s32,
      GIM_CheckRegBankForClass, /*MI*/0, /*Op*/0, /*RC*/GIMT_Encode2(AMDGPU::AV_32RegClassID),
      GIM_Try, /*On fail goto*//*Label 6620*/ GIMT_Encode4(486128), // Rule ID 4057 //
        GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasPackedD16VMem_HasUnrestrictedSOffset),
        GIM_CheckConstantInt8, /*MI*/0, /*Op*/2, 0,
        GIM_CheckConstantInt8, /*MI*/0, /*Op*/3, 0,
        // MIs[0] offset
        GIM_CheckIsImm, /*MI*/0, /*Op*/5,
        // MIs[0] auxiliary
        GIM_CheckIsImm, /*MI*/0, /*Op*/6,
        // MIs[0] Operand 7
        GIM_CheckLiteralInt, /*MI*/0, /*Op*/7, GIMT_Encode8(0),
        GIM_CheckComplexPattern, /*MI*/0, /*Op*/4, /*Renderer*/GIMT_Encode2(0), GIMT_Encode2(GICP_gi_buf_soffset),
        // (SIbuffer_load_format_d16:{ *:[v2f16] } v4i32:{ *:[v4i32] }:$rsrc, 0:{ *:[i32] }, 0:{ *:[i32] }, (BUFSOffset:{ *:[i32] } i32:{ *:[i32] }:$soffset), (timm:{ *:[i32] }):$offset, (timm:{ *:[i32] }):$auxiliary, 0:{ *:[i1] })  =>  (BUFFER_LOAD_FORMAT_D16_XY_OFFSET:{ *:[v2f16] } SReg_128:{ *:[v4i32] }:$rsrc, SCSrc_b32:{ *:[i32] }:$soffset, (timm:{ *:[i32] }):$offset, (extract_cpol:{ *:[i32] } ?:{ *:[i32] }:$auxiliary), (extract_swz:{ *:[i1] } ?:{ *:[i32] }:$auxiliary))
        GIR_BuildMI, /*InsnID*/0, /*Opcode*/GIMT_Encode2(AMDGPU::BUFFER_LOAD_FORMAT_D16_XY_OFFSET),
        GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/0, // DstI[vdata]
        GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/1, // rsrc
        GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/0, // soffset
        GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/5, // offset
        GIR_CustomOperandRenderer, /*InsnID*/0, /*OldInsnID*/0, /*OpIdx*/6, /*OperandRenderer*/GIMT_Encode2(GICR_renderExtractCPol), // auxiliary
        GIR_CustomOperandRenderer, /*InsnID*/0, /*OldInsnID*/0, /*OpIdx*/6, /*OperandRenderer*/GIMT_Encode2(GICR_renderExtractSWZ), // auxiliary
        GIR_MergeMemOperands, /*InsnID*/0, /*NumInsns*/1, /*MergeInsnID's*/0,
        GIR_ConstrainSelectedInstOperands, /*InsnID*/0,
        GIR_EraseFromParent, /*InsnID*/0,
        // GIR_Coverage, 4057,
        GIR_Done,
      // Label 6620: @486128
      GIM_Try, /*On fail goto*//*Label 6621*/ GIMT_Encode4(486210), // Rule ID 4061 //
        GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasPackedD16VMem),
        GIM_CheckConstantInt8, /*MI*/0, /*Op*/2, 0,
        GIM_CheckConstantInt8, /*MI*/0, /*Op*/3, 0,
        // MIs[0] offset
        GIM_CheckIsImm, /*MI*/0, /*Op*/5,
        // MIs[0] auxiliary
        GIM_CheckIsImm, /*MI*/0, /*Op*/6,
        // MIs[0] Operand 7
        GIM_CheckLiteralInt, /*MI*/0, /*Op*/7, GIMT_Encode8(0),
        GIM_CheckComplexPattern, /*MI*/0, /*Op*/4, /*Renderer*/GIMT_Encode2(0), GIMT_Encode2(GICP_gi_buf_soffset),
        // (SIbuffer_load_format_d16:{ *:[v2f16] } v4i32:{ *:[v4i32] }:$rsrc, 0:{ *:[i32] }, 0:{ *:[i32] }, (BUFSOffset:{ *:[i32] } i32:{ *:[i32] }:$soffset), (timm:{ *:[i32] }):$offset, (timm:{ *:[i32] }):$auxiliary, 0:{ *:[i1] })  =>  (BUFFER_LOAD_FORMAT_D16_XY_VBUFFER_OFFSET:{ *:[v2f16] } SReg_128:{ *:[v4i32] }:$rsrc, SCSrc_b32:{ *:[i32] }:$soffset, (timm:{ *:[i32] }):$offset, (extract_cpol:{ *:[i32] } ?:{ *:[i32] }:$auxiliary), (extract_swz:{ *:[i1] } ?:{ *:[i32] }:$auxiliary))
        GIR_BuildMI, /*InsnID*/0, /*Opcode*/GIMT_Encode2(AMDGPU::BUFFER_LOAD_FORMAT_D16_XY_VBUFFER_OFFSET),
        GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/0, // DstI[vdata]
        GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/1, // rsrc
        GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/0, // soffset
        GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/5, // offset
        GIR_CustomOperandRenderer, /*InsnID*/0, /*OldInsnID*/0, /*OpIdx*/6, /*OperandRenderer*/GIMT_Encode2(GICR_renderExtractCPol), // auxiliary
        GIR_CustomOperandRenderer, /*InsnID*/0, /*OldInsnID*/0, /*OpIdx*/6, /*OperandRenderer*/GIMT_Encode2(GICR_renderExtractSWZ), // auxiliary
        GIR_MergeMemOperands, /*InsnID*/0, /*NumInsns*/1, /*MergeInsnID's*/0,
        GIR_ConstrainSelectedInstOperands, /*InsnID*/0,
        GIR_EraseFromParent, /*InsnID*/0,
        // GIR_Coverage, 4061,
        GIR_Done,
      // Label 6621: @486210
      GIM_Try, /*On fail goto*//*Label 6622*/ GIMT_Encode4(486292), // Rule ID 4065 //
        GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasPackedD16VMem_HasUnrestrictedSOffset),
        GIM_CheckConstantInt8, /*MI*/0, /*Op*/2, 0,
        GIM_CheckConstantInt8, /*MI*/0, /*Op*/3, 0,
        // MIs[0] offset
        GIM_CheckIsImm, /*MI*/0, /*Op*/5,
        // MIs[0] auxiliary
        GIM_CheckIsImm, /*MI*/0, /*Op*/6,
        // MIs[0] Operand 7
        GIM_CheckLiteralInt, /*MI*/0, /*Op*/7, GIMT_Encode8(0),
        GIM_CheckComplexPattern, /*MI*/0, /*Op*/4, /*Renderer*/GIMT_Encode2(0), GIMT_Encode2(GICP_gi_buf_soffset),
        // (SIbuffer_load_format_d16:{ *:[v2i16] } v4i32:{ *:[v4i32] }:$rsrc, 0:{ *:[i32] }, 0:{ *:[i32] }, (BUFSOffset:{ *:[i32] } i32:{ *:[i32] }:$soffset), (timm:{ *:[i32] }):$offset, (timm:{ *:[i32] }):$auxiliary, 0:{ *:[i1] })  =>  (BUFFER_LOAD_FORMAT_D16_XY_OFFSET:{ *:[v2i16] } SReg_128:{ *:[v4i32] }:$rsrc, SCSrc_b32:{ *:[i32] }:$soffset, (timm:{ *:[i32] }):$offset, (extract_cpol:{ *:[i32] } ?:{ *:[i32] }:$auxiliary), (extract_swz:{ *:[i1] } ?:{ *:[i32] }:$auxiliary))
        GIR_BuildMI, /*InsnID*/0, /*Opcode*/GIMT_Encode2(AMDGPU::BUFFER_LOAD_FORMAT_D16_XY_OFFSET),
        GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/0, // DstI[vdata]
        GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/1, // rsrc
        GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/0, // soffset
        GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/5, // offset
        GIR_CustomOperandRenderer, /*InsnID*/0, /*OldInsnID*/0, /*OpIdx*/6, /*OperandRenderer*/GIMT_Encode2(GICR_renderExtractCPol), // auxiliary
        GIR_CustomOperandRenderer, /*InsnID*/0, /*OldInsnID*/0, /*OpIdx*/6, /*OperandRenderer*/GIMT_Encode2(GICR_renderExtractSWZ), // auxiliary
        GIR_MergeMemOperands, /*InsnID*/0, /*NumInsns*/1, /*MergeInsnID's*/0,
        GIR_ConstrainSelectedInstOperands, /*InsnID*/0,
        GIR_EraseFromParent, /*InsnID*/0,
        // GIR_Coverage, 4065,
        GIR_Done,
      // Label 6622: @486292
      GIM_Try, /*On fail goto*//*Label 6623*/ GIMT_Encode4(486374), // Rule ID 4069 //
        GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasPackedD16VMem),
        GIM_CheckConstantInt8, /*MI*/0, /*Op*/2, 0,
        GIM_CheckConstantInt8, /*MI*/0, /*Op*/3, 0,
        // MIs[0] offset
        GIM_CheckIsImm, /*MI*/0, /*Op*/5,
        // MIs[0] auxiliary
        GIM_CheckIsImm, /*MI*/0, /*Op*/6,
        // MIs[0] Operand 7
        GIM_CheckLiteralInt, /*MI*/0, /*Op*/7, GIMT_Encode8(0),
        GIM_CheckComplexPattern, /*MI*/0, /*Op*/4, /*Renderer*/GIMT_Encode2(0), GIMT_Encode2(GICP_gi_buf_soffset),
        // (SIbuffer_load_format_d16:{ *:[v2i16] } v4i32:{ *:[v4i32] }:$rsrc, 0:{ *:[i32] }, 0:{ *:[i32] }, (BUFSOffset:{ *:[i32] } i32:{ *:[i32] }:$soffset), (timm:{ *:[i32] }):$offset, (timm:{ *:[i32] }):$auxiliary, 0:{ *:[i1] })  =>  (BUFFER_LOAD_FORMAT_D16_XY_VBUFFER_OFFSET:{ *:[v2i16] } SReg_128:{ *:[v4i32] }:$rsrc, SCSrc_b32:{ *:[i32] }:$soffset, (timm:{ *:[i32] }):$offset, (extract_cpol:{ *:[i32] } ?:{ *:[i32] }:$auxiliary), (extract_swz:{ *:[i1] } ?:{ *:[i32] }:$auxiliary))
        GIR_BuildMI, /*InsnID*/0, /*Opcode*/GIMT_Encode2(AMDGPU::BUFFER_LOAD_FORMAT_D16_XY_VBUFFER_OFFSET),
        GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/0, // DstI[vdata]
        GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/1, // rsrc
        GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/0, // soffset
        GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/5, // offset
        GIR_CustomOperandRenderer, /*InsnID*/0, /*OldInsnID*/0, /*OpIdx*/6, /*OperandRenderer*/GIMT_Encode2(GICR_renderExtractCPol), // auxiliary
        GIR_CustomOperandRenderer, /*InsnID*/0, /*OldInsnID*/0, /*OpIdx*/6, /*OperandRenderer*/GIMT_Encode2(GICR_renderExtractSWZ), // auxiliary
        GIR_MergeMemOperands, /*InsnID*/0, /*NumInsns*/1, /*MergeInsnID's*/0,
        GIR_ConstrainSelectedInstOperands, /*InsnID*/0,
        GIR_EraseFromParent, /*InsnID*/0,
        // GIR_Coverage, 4069,
        GIR_Done,
      // Label 6623: @486374
      GIM_Try, /*On fail goto*//*Label 6624*/ GIMT_Encode4(486456), // Rule ID 4058 //
        GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasPackedD16VMem_HasUnrestrictedSOffset),
        GIM_CheckConstantInt8, /*MI*/0, /*Op*/2, 0,
        // MIs[0] offset
        GIM_CheckIsImm, /*MI*/0, /*Op*/5,
        // MIs[0] auxiliary
        GIM_CheckIsImm, /*MI*/0, /*Op*/6,
        // MIs[0] Operand 7
        GIM_CheckLiteralInt, /*MI*/0, /*Op*/7, GIMT_Encode8(0),
        GIM_CheckComplexPattern, /*MI*/0, /*Op*/4, /*Renderer*/GIMT_Encode2(0), GIMT_Encode2(GICP_gi_buf_soffset),
        // (SIbuffer_load_format_d16:{ *:[v2f16] } v4i32:{ *:[v4i32] }:$rsrc, 0:{ *:[i32] }, i32:{ *:[i32] }:$voffset, (BUFSOffset:{ *:[i32] } i32:{ *:[i32] }:$soffset), (timm:{ *:[i32] }):$offset, (timm:{ *:[i32] }):$auxiliary, 0:{ *:[i1] })  =>  (BUFFER_LOAD_FORMAT_D16_XY_OFFEN:{ *:[v2f16] } VGPR_32:{ *:[i32] }:$voffset, SReg_128:{ *:[v4i32] }:$rsrc, SCSrc_b32:{ *:[i32] }:$soffset, (timm:{ *:[i32] }):$offset, (extract_cpol:{ *:[i32] } ?:{ *:[i32] }:$auxiliary), (extract_swz:{ *:[i1] } ?:{ *:[i32] }:$auxiliary))
        GIR_BuildMI, /*InsnID*/0, /*Opcode*/GIMT_Encode2(AMDGPU::BUFFER_LOAD_FORMAT_D16_XY_OFFEN),
        GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/0, // DstI[vdata]
        GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/3, // voffset
        GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/1, // rsrc
        GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/0, // soffset
        GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/5, // offset
        GIR_CustomOperandRenderer, /*InsnID*/0, /*OldInsnID*/0, /*OpIdx*/6, /*OperandRenderer*/GIMT_Encode2(GICR_renderExtractCPol), // auxiliary
        GIR_CustomOperandRenderer, /*InsnID*/0, /*OldInsnID*/0, /*OpIdx*/6, /*OperandRenderer*/GIMT_Encode2(GICR_renderExtractSWZ), // auxiliary
        GIR_MergeMemOperands, /*InsnID*/0, /*NumInsns*/1, /*MergeInsnID's*/0,
        GIR_ConstrainSelectedInstOperands, /*InsnID*/0,
        GIR_EraseFromParent, /*InsnID*/0,
        // GIR_Coverage, 4058,
        GIR_Done,
      // Label 6624: @486456
      GIM_Try, /*On fail goto*//*Label 6625*/ GIMT_Encode4(486538), // Rule ID 4062 //
        GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasPackedD16VMem),
        GIM_CheckConstantInt8, /*MI*/0, /*Op*/2, 0,
        // MIs[0] offset
        GIM_CheckIsImm, /*MI*/0, /*Op*/5,
        // MIs[0] auxiliary
        GIM_CheckIsImm, /*MI*/0, /*Op*/6,
        // MIs[0] Operand 7
        GIM_CheckLiteralInt, /*MI*/0, /*Op*/7, GIMT_Encode8(0),
        GIM_CheckComplexPattern, /*MI*/0, /*Op*/4, /*Renderer*/GIMT_Encode2(0), GIMT_Encode2(GICP_gi_buf_soffset),
        // (SIbuffer_load_format_d16:{ *:[v2f16] } v4i32:{ *:[v4i32] }:$rsrc, 0:{ *:[i32] }, i32:{ *:[i32] }:$voffset, (BUFSOffset:{ *:[i32] } i32:{ *:[i32] }:$soffset), (timm:{ *:[i32] }):$offset, (timm:{ *:[i32] }):$auxiliary, 0:{ *:[i1] })  =>  (BUFFER_LOAD_FORMAT_D16_XY_VBUFFER_OFFEN:{ *:[v2f16] } VGPR_32:{ *:[i32] }:$voffset, SReg_128:{ *:[v4i32] }:$rsrc, SCSrc_b32:{ *:[i32] }:$soffset, (timm:{ *:[i32] }):$offset, (extract_cpol:{ *:[i32] } ?:{ *:[i32] }:$auxiliary), (extract_swz:{ *:[i1] } ?:{ *:[i32] }:$auxiliary))
        GIR_BuildMI, /*InsnID*/0, /*Opcode*/GIMT_Encode2(AMDGPU::BUFFER_LOAD_FORMAT_D16_XY_VBUFFER_OFFEN),
        GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/0, // DstI[vdata]
        GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/3, // voffset
        GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/1, // rsrc
        GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/0, // soffset
        GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/5, // offset
        GIR_CustomOperandRenderer, /*InsnID*/0, /*OldInsnID*/0, /*OpIdx*/6, /*OperandRenderer*/GIMT_Encode2(GICR_renderExtractCPol), // auxiliary
        GIR_CustomOperandRenderer, /*InsnID*/0, /*OldInsnID*/0, /*OpIdx*/6, /*OperandRenderer*/GIMT_Encode2(GICR_renderExtractSWZ), // auxiliary
        GIR_MergeMemOperands, /*InsnID*/0, /*NumInsns*/1, /*MergeInsnID's*/0,
        GIR_ConstrainSelectedInstOperands, /*InsnID*/0,
        GIR_EraseFromParent, /*InsnID*/0,
        // GIR_Coverage, 4062,
        GIR_Done,
      // Label 6625: @486538
      GIM_Try, /*On fail goto*//*Label 6626*/ GIMT_Encode4(486620), // Rule ID 4066 //
        GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasPackedD16VMem_HasUnrestrictedSOffset),
        GIM_CheckConstantInt8, /*MI*/0, /*Op*/2, 0,
        // MIs[0] offset
        GIM_CheckIsImm, /*MI*/0, /*Op*/5,
        // MIs[0] auxiliary
        GIM_CheckIsImm, /*MI*/0, /*Op*/6,
        // MIs[0] Operand 7
        GIM_CheckLiteralInt, /*MI*/0, /*Op*/7, GIMT_Encode8(0),
        GIM_CheckComplexPattern, /*MI*/0, /*Op*/4, /*Renderer*/GIMT_Encode2(0), GIMT_Encode2(GICP_gi_buf_soffset),
        // (SIbuffer_load_format_d16:{ *:[v2i16] } v4i32:{ *:[v4i32] }:$rsrc, 0:{ *:[i32] }, i32:{ *:[i32] }:$voffset, (BUFSOffset:{ *:[i32] } i32:{ *:[i32] }:$soffset), (timm:{ *:[i32] }):$offset, (timm:{ *:[i32] }):$auxiliary, 0:{ *:[i1] })  =>  (BUFFER_LOAD_FORMAT_D16_XY_OFFEN:{ *:[v2i16] } VGPR_32:{ *:[i32] }:$voffset, SReg_128:{ *:[v4i32] }:$rsrc, SCSrc_b32:{ *:[i32] }:$soffset, (timm:{ *:[i32] }):$offset, (extract_cpol:{ *:[i32] } ?:{ *:[i32] }:$auxiliary), (extract_swz:{ *:[i1] } ?:{ *:[i32] }:$auxiliary))
        GIR_BuildMI, /*InsnID*/0, /*Opcode*/GIMT_Encode2(AMDGPU::BUFFER_LOAD_FORMAT_D16_XY_OFFEN),
        GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/0, // DstI[vdata]
        GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/3, // voffset
        GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/1, // rsrc
        GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/0, // soffset
        GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/5, // offset
        GIR_CustomOperandRenderer, /*InsnID*/0, /*OldInsnID*/0, /*OpIdx*/6, /*OperandRenderer*/GIMT_Encode2(GICR_renderExtractCPol), // auxiliary
        GIR_CustomOperandRenderer, /*InsnID*/0, /*OldInsnID*/0, /*OpIdx*/6, /*OperandRenderer*/GIMT_Encode2(GICR_renderExtractSWZ), // auxiliary
        GIR_MergeMemOperands, /*InsnID*/0, /*NumInsns*/1, /*MergeInsnID's*/0,
        GIR_ConstrainSelectedInstOperands, /*InsnID*/0,
        GIR_EraseFromParent, /*InsnID*/0,
        // GIR_Coverage, 4066,
        GIR_Done,
      // Label 6626: @486620
      GIM_Try, /*On fail goto*//*Label 6627*/ GIMT_Encode4(486702), // Rule ID 4070 //
        GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasPackedD16VMem),
        GIM_CheckConstantInt8, /*MI*/0, /*Op*/2, 0,
        // MIs[0] offset
        GIM_CheckIsImm, /*MI*/0, /*Op*/5,
        // MIs[0] auxiliary
        GIM_CheckIsImm, /*MI*/0, /*Op*/6,
        // MIs[0] Operand 7
        GIM_CheckLiteralInt, /*MI*/0, /*Op*/7, GIMT_Encode8(0),
        GIM_CheckComplexPattern, /*MI*/0, /*Op*/4, /*Renderer*/GIMT_Encode2(0), GIMT_Encode2(GICP_gi_buf_soffset),
        // (SIbuffer_load_format_d16:{ *:[v2i16] } v4i32:{ *:[v4i32] }:$rsrc, 0:{ *:[i32] }, i32:{ *:[i32] }:$voffset, (BUFSOffset:{ *:[i32] } i32:{ *:[i32] }:$soffset), (timm:{ *:[i32] }):$offset, (timm:{ *:[i32] }):$auxiliary, 0:{ *:[i1] })  =>  (BUFFER_LOAD_FORMAT_D16_XY_VBUFFER_OFFEN:{ *:[v2i16] } VGPR_32:{ *:[i32] }:$voffset, SReg_128:{ *:[v4i32] }:$rsrc, SCSrc_b32:{ *:[i32] }:$soffset, (timm:{ *:[i32] }):$offset, (extract_cpol:{ *:[i32] } ?:{ *:[i32] }:$auxiliary), (extract_swz:{ *:[i1] } ?:{ *:[i32] }:$auxiliary))
        GIR_BuildMI, /*InsnID*/0, /*Opcode*/GIMT_Encode2(AMDGPU::BUFFER_LOAD_FORMAT_D16_XY_VBUFFER_OFFEN),
        GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/0, // DstI[vdata]
        GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/3, // voffset
        GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/1, // rsrc
        GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/0, // soffset
        GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/5, // offset
        GIR_CustomOperandRenderer, /*InsnID*/0, /*OldInsnID*/0, /*OpIdx*/6, /*OperandRenderer*/GIMT_Encode2(GICR_renderExtractCPol), // auxiliary
        GIR_CustomOperandRenderer, /*InsnID*/0, /*OldInsnID*/0, /*OpIdx*/6, /*OperandRenderer*/GIMT_Encode2(GICR_renderExtractSWZ), // auxiliary
        GIR_MergeMemOperands, /*InsnID*/0, /*NumInsns*/1, /*MergeInsnID's*/0,
        GIR_ConstrainSelectedInstOperands, /*InsnID*/0,
        GIR_EraseFromParent, /*InsnID*/0,
        // GIR_Coverage, 4070,
        GIR_Done,
      // Label 6627: @486702
      GIM_Try, /*On fail goto*//*Label 6628*/ GIMT_Encode4(486776), // Rule ID 4059 //
        GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasPackedD16VMem_HasUnrestrictedSOffset),
        GIM_CheckConstantInt8, /*MI*/0, /*Op*/3, 0,
        // MIs[0] offset
        GIM_CheckIsImm, /*MI*/0, /*Op*/5,
        // MIs[0] auxiliary
        GIM_CheckIsImm, /*MI*/0, /*Op*/6,
        // MIs[0] Operand 7
        GIM_CheckIsImm, /*MI*/0, /*Op*/7,
        GIM_CheckComplexPattern, /*MI*/0, /*Op*/4, /*Renderer*/GIMT_Encode2(0), GIMT_Encode2(GICP_gi_buf_soffset),
        // (SIbuffer_load_format_d16:{ *:[v2f16] } v4i32:{ *:[v4i32] }:$rsrc, i32:{ *:[i32] }:$vindex, 0:{ *:[i32] }, (BUFSOffset:{ *:[i32] } i32:{ *:[i32] }:$soffset), (timm:{ *:[i32] }):$offset, (timm:{ *:[i32] }):$auxiliary, (timm:{ *:[i1] }))  =>  (BUFFER_LOAD_FORMAT_D16_XY_IDXEN:{ *:[v2f16] } VGPR_32:{ *:[i32] }:$vindex, SReg_128:{ *:[v4i32] }:$rsrc, SCSrc_b32:{ *:[i32] }:$soffset, (timm:{ *:[i32] }):$offset, (extract_cpol:{ *:[i32] } ?:{ *:[i32] }:$auxiliary), (extract_swz:{ *:[i1] } ?:{ *:[i32] }:$auxiliary))
        GIR_BuildMI, /*InsnID*/0, /*Opcode*/GIMT_Encode2(AMDGPU::BUFFER_LOAD_FORMAT_D16_XY_IDXEN),
        GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/0, // DstI[vdata]
        GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/2, // vindex
        GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/1, // rsrc
        GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/0, // soffset
        GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/5, // offset
        GIR_CustomOperandRenderer, /*InsnID*/0, /*OldInsnID*/0, /*OpIdx*/6, /*OperandRenderer*/GIMT_Encode2(GICR_renderExtractCPol), // auxiliary
        GIR_CustomOperandRenderer, /*InsnID*/0, /*OldInsnID*/0, /*OpIdx*/6, /*OperandRenderer*/GIMT_Encode2(GICR_renderExtractSWZ), // auxiliary
        GIR_MergeMemOperands, /*InsnID*/0, /*NumInsns*/1, /*MergeInsnID's*/0,
        GIR_ConstrainSelectedInstOperands, /*InsnID*/0,
        GIR_EraseFromParent, /*InsnID*/0,
        // GIR_Coverage, 4059,
        GIR_Done,
      // Label 6628: @486776
      GIM_Try, /*On fail goto*//*Label 6629*/ GIMT_Encode4(486850), // Rule ID 4063 //
        GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasPackedD16VMem),
        GIM_CheckConstantInt8, /*MI*/0, /*Op*/3, 0,
        // MIs[0] offset
        GIM_CheckIsImm, /*MI*/0, /*Op*/5,
        // MIs[0] auxiliary
        GIM_CheckIsImm, /*MI*/0, /*Op*/6,
        // MIs[0] Operand 7
        GIM_CheckIsImm, /*MI*/0, /*Op*/7,
        GIM_CheckComplexPattern, /*MI*/0, /*Op*/4, /*Renderer*/GIMT_Encode2(0), GIMT_Encode2(GICP_gi_buf_soffset),
        // (SIbuffer_load_format_d16:{ *:[v2f16] } v4i32:{ *:[v4i32] }:$rsrc, i32:{ *:[i32] }:$vindex, 0:{ *:[i32] }, (BUFSOffset:{ *:[i32] } i32:{ *:[i32] }:$soffset), (timm:{ *:[i32] }):$offset, (timm:{ *:[i32] }):$auxiliary, (timm:{ *:[i1] }))  =>  (BUFFER_LOAD_FORMAT_D16_XY_VBUFFER_IDXEN:{ *:[v2f16] } VGPR_32:{ *:[i32] }:$vindex, SReg_128:{ *:[v4i32] }:$rsrc, SCSrc_b32:{ *:[i32] }:$soffset, (timm:{ *:[i32] }):$offset, (extract_cpol:{ *:[i32] } ?:{ *:[i32] }:$auxiliary), (extract_swz:{ *:[i1] } ?:{ *:[i32] }:$auxiliary))
        GIR_BuildMI, /*InsnID*/0, /*Opcode*/GIMT_Encode2(AMDGPU::BUFFER_LOAD_FORMAT_D16_XY_VBUFFER_IDXEN),
        GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/0, // DstI[vdata]
        GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/2, // vindex
        GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/1, // rsrc
        GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/0, // soffset
        GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/5, // offset
        GIR_CustomOperandRenderer, /*InsnID*/0, /*OldInsnID*/0, /*OpIdx*/6, /*OperandRenderer*/GIMT_Encode2(GICR_renderExtractCPol), // auxiliary
        GIR_CustomOperandRenderer, /*InsnID*/0, /*OldInsnID*/0, /*OpIdx*/6, /*OperandRenderer*/GIMT_Encode2(GICR_renderExtractSWZ), // auxiliary
        GIR_MergeMemOperands, /*InsnID*/0, /*NumInsns*/1, /*MergeInsnID's*/0,
        GIR_ConstrainSelectedInstOperands, /*InsnID*/0,
        GIR_EraseFromParent, /*InsnID*/0,
        // GIR_Coverage, 4063,
        GIR_Done,
      // Label 6629: @486850
      GIM_Try, /*On fail goto*//*Label 6630*/ GIMT_Encode4(486924), // Rule ID 4067 //
        GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasPackedD16VMem_HasUnrestrictedSOffset),
        GIM_CheckConstantInt8, /*MI*/0, /*Op*/3, 0,
        // MIs[0] offset
        GIM_CheckIsImm, /*MI*/0, /*Op*/5,
        // MIs[0] auxiliary
        GIM_CheckIsImm, /*MI*/0, /*Op*/6,
        // MIs[0] Operand 7
        GIM_CheckIsImm, /*MI*/0, /*Op*/7,
        GIM_CheckComplexPattern, /*MI*/0, /*Op*/4, /*Renderer*/GIMT_Encode2(0), GIMT_Encode2(GICP_gi_buf_soffset),
        // (SIbuffer_load_format_d16:{ *:[v2i16] } v4i32:{ *:[v4i32] }:$rsrc, i32:{ *:[i32] }:$vindex, 0:{ *:[i32] }, (BUFSOffset:{ *:[i32] } i32:{ *:[i32] }:$soffset), (timm:{ *:[i32] }):$offset, (timm:{ *:[i32] }):$auxiliary, (timm:{ *:[i1] }))  =>  (BUFFER_LOAD_FORMAT_D16_XY_IDXEN:{ *:[v2i16] } VGPR_32:{ *:[i32] }:$vindex, SReg_128:{ *:[v4i32] }:$rsrc, SCSrc_b32:{ *:[i32] }:$soffset, (timm:{ *:[i32] }):$offset, (extract_cpol:{ *:[i32] } ?:{ *:[i32] }:$auxiliary), (extract_swz:{ *:[i1] } ?:{ *:[i32] }:$auxiliary))
        GIR_BuildMI, /*InsnID*/0, /*Opcode*/GIMT_Encode2(AMDGPU::BUFFER_LOAD_FORMAT_D16_XY_IDXEN),
        GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/0, // DstI[vdata]
        GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/2, // vindex
        GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/1, // rsrc
        GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/0, // soffset
        GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/5, // offset
        GIR_CustomOperandRenderer, /*InsnID*/0, /*OldInsnID*/0, /*OpIdx*/6, /*OperandRenderer*/GIMT_Encode2(GICR_renderExtractCPol), // auxiliary
        GIR_CustomOperandRenderer, /*InsnID*/0, /*OldInsnID*/0, /*OpIdx*/6, /*OperandRenderer*/GIMT_Encode2(GICR_renderExtractSWZ), // auxiliary
        GIR_MergeMemOperands, /*InsnID*/0, /*NumInsns*/1, /*MergeInsnID's*/0,
        GIR_ConstrainSelectedInstOperands, /*InsnID*/0,
        GIR_EraseFromParent, /*InsnID*/0,
        // GIR_Coverage, 4067,
        GIR_Done,
      // Label 6630: @486924
      GIM_Try, /*On fail goto*//*Label 6631*/ GIMT_Encode4(486998), // Rule ID 4071 //
        GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasPackedD16VMem),
        GIM_CheckConstantInt8, /*MI*/0, /*Op*/3, 0,
        // MIs[0] offset
        GIM_CheckIsImm, /*MI*/0, /*Op*/5,
        // MIs[0] auxiliary
        GIM_CheckIsImm, /*MI*/0, /*Op*/6,
        // MIs[0] Operand 7
        GIM_CheckIsImm, /*MI*/0, /*Op*/7,
        GIM_CheckComplexPattern, /*MI*/0, /*Op*/4, /*Renderer*/GIMT_Encode2(0), GIMT_Encode2(GICP_gi_buf_soffset),
        // (SIbuffer_load_format_d16:{ *:[v2i16] } v4i32:{ *:[v4i32] }:$rsrc, i32:{ *:[i32] }:$vindex, 0:{ *:[i32] }, (BUFSOffset:{ *:[i32] } i32:{ *:[i32] }:$soffset), (timm:{ *:[i32] }):$offset, (timm:{ *:[i32] }):$auxiliary, (timm:{ *:[i1] }))  =>  (BUFFER_LOAD_FORMAT_D16_XY_VBUFFER_IDXEN:{ *:[v2i16] } VGPR_32:{ *:[i32] }:$vindex, SReg_128:{ *:[v4i32] }:$rsrc, SCSrc_b32:{ *:[i32] }:$soffset, (timm:{ *:[i32] }):$offset, (extract_cpol:{ *:[i32] } ?:{ *:[i32] }:$auxiliary), (extract_swz:{ *:[i1] } ?:{ *:[i32] }:$auxiliary))
        GIR_BuildMI, /*InsnID*/0, /*Opcode*/GIMT_Encode2(AMDGPU::BUFFER_LOAD_FORMAT_D16_XY_VBUFFER_IDXEN),
        GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/0, // DstI[vdata]
        GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/2, // vindex
        GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/1, // rsrc
        GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/0, // soffset
        GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/5, // offset
        GIR_CustomOperandRenderer, /*InsnID*/0, /*OldInsnID*/0, /*OpIdx*/6, /*OperandRenderer*/GIMT_Encode2(GICR_renderExtractCPol), // auxiliary
        GIR_CustomOperandRenderer, /*InsnID*/0, /*OldInsnID*/0, /*OpIdx*/6, /*OperandRenderer*/GIMT_Encode2(GICR_renderExtractSWZ), // auxiliary
        GIR_MergeMemOperands, /*InsnID*/0, /*NumInsns*/1, /*MergeInsnID's*/0,
        GIR_ConstrainSelectedInstOperands, /*InsnID*/0,
        GIR_EraseFromParent, /*InsnID*/0,
        // GIR_Coverage, 4071,
        GIR_Done,
      // Label 6631: @486998
      GIM_Try, /*On fail goto*//*Label 6632*/ GIMT_Encode4(487108), // Rule ID 4060 //
        GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasPackedD16VMem_HasUnrestrictedSOffset),
        // MIs[0] offset
        GIM_CheckIsImm, /*MI*/0, /*Op*/5,
        // MIs[0] auxiliary
        GIM_CheckIsImm, /*MI*/0, /*Op*/6,
        // MIs[0] Operand 7
        GIM_CheckIsImm, /*MI*/0, /*Op*/7,
        GIM_CheckComplexPattern, /*MI*/0, /*Op*/4, /*Renderer*/GIMT_Encode2(0), GIMT_Encode2(GICP_gi_buf_soffset),
        // (SIbuffer_load_format_d16:{ *:[v2f16] } v4i32:{ *:[v4i32] }:$rsrc, i32:{ *:[i32] }:$vindex, i32:{ *:[i32] }:$voffset, (BUFSOffset:{ *:[i32] } i32:{ *:[i32] }:$soffset), (timm:{ *:[i32] }):$offset, (timm:{ *:[i32] }):$auxiliary, (timm:{ *:[i1] }))  =>  (BUFFER_LOAD_FORMAT_D16_XY_BOTHEN:{ *:[v2f16] } (REG_SEQUENCE:{ *:[i64] } VReg_64:{ *:[i32] }, VGPR_32:{ *:[i32] }:$vindex, sub0:{ *:[i32] }, VGPR_32:{ *:[i32] }:$voffset, sub1:{ *:[i32] }), SReg_128:{ *:[v4i32] }:$rsrc, SCSrc_b32:{ *:[i32] }:$soffset, (timm:{ *:[i32] }):$offset, (extract_cpol:{ *:[i32] } ?:{ *:[i32] }:$auxiliary), (extract_swz:{ *:[i1] } ?:{ *:[i32] }:$auxiliary))
        GIR_MakeTempReg, /*TempRegID*/0, /*TypeID*/GILLT_s64,
        GIR_BuildMI, /*InsnID*/1, /*Opcode*/GIMT_Encode2(TargetOpcode::REG_SEQUENCE),
        GIR_AddTempRegister, /*InsnID*/1, /*TempRegID*/0, /*TempRegFlags*/GIMT_Encode2(RegState::Define),
        GIR_Copy, /*NewInsnID*/1, /*OldInsnID*/0, /*OpIdx*/2, // vindex
        GIR_AddImm8, /*InsnID*/1, /*SubRegIndex*/3,
        GIR_Copy, /*NewInsnID*/1, /*OldInsnID*/0, /*OpIdx*/3, // voffset
        GIR_AddImm8, /*InsnID*/1, /*SubRegIndex*/11,
        GIR_ConstrainOperandRC, /*InsnID*/1, /*Op*/0, GIMT_Encode2(AMDGPU::VReg_64RegClassID),
        GIR_ConstrainOperandRC, /*InsnID*/1, /*Op*/1, GIMT_Encode2(AMDGPU::VGPR_32RegClassID),
        GIR_ConstrainOperandRC, /*InsnID*/1, /*Op*/3, GIMT_Encode2(AMDGPU::VGPR_32RegClassID),
        GIR_BuildMI, /*InsnID*/0, /*Opcode*/GIMT_Encode2(AMDGPU::BUFFER_LOAD_FORMAT_D16_XY_BOTHEN),
        GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/0, // DstI[vdata]
        GIR_AddSimpleTempRegister, /*InsnID*/0, /*TempRegID*/0,
        GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/1, // rsrc
        GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/0, // soffset
        GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/5, // offset
        GIR_CustomOperandRenderer, /*InsnID*/0, /*OldInsnID*/0, /*OpIdx*/6, /*OperandRenderer*/GIMT_Encode2(GICR_renderExtractCPol), // auxiliary
        GIR_CustomOperandRenderer, /*InsnID*/0, /*OldInsnID*/0, /*OpIdx*/6, /*OperandRenderer*/GIMT_Encode2(GICR_renderExtractSWZ), // auxiliary
        GIR_MergeMemOperands, /*InsnID*/0, /*NumInsns*/1, /*MergeInsnID's*/0,
        GIR_ConstrainSelectedInstOperands, /*InsnID*/0,
        GIR_EraseFromParent, /*InsnID*/0,
        // GIR_Coverage, 4060,
        GIR_Done,
      // Label 6632: @487108
      GIM_Try, /*On fail goto*//*Label 6633*/ GIMT_Encode4(487218), // Rule ID 4064 //
        GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasPackedD16VMem),
        // MIs[0] offset
        GIM_CheckIsImm, /*MI*/0, /*Op*/5,
        // MIs[0] auxiliary
        GIM_CheckIsImm, /*MI*/0, /*Op*/6,
        // MIs[0] Operand 7
        GIM_CheckIsImm, /*MI*/0, /*Op*/7,
        GIM_CheckComplexPattern, /*MI*/0, /*Op*/4, /*Renderer*/GIMT_Encode2(0), GIMT_Encode2(GICP_gi_buf_soffset),
        // (SIbuffer_load_format_d16:{ *:[v2f16] } v4i32:{ *:[v4i32] }:$rsrc, i32:{ *:[i32] }:$vindex, i32:{ *:[i32] }:$voffset, (BUFSOffset:{ *:[i32] } i32:{ *:[i32] }:$soffset), (timm:{ *:[i32] }):$offset, (timm:{ *:[i32] }):$auxiliary, (timm:{ *:[i1] }))  =>  (BUFFER_LOAD_FORMAT_D16_XY_VBUFFER_BOTHEN:{ *:[v2f16] } (REG_SEQUENCE:{ *:[i64] } VReg_64:{ *:[i32] }, VGPR_32:{ *:[i32] }:$vindex, sub0:{ *:[i32] }, VGPR_32:{ *:[i32] }:$voffset, sub1:{ *:[i32] }), SReg_128:{ *:[v4i32] }:$rsrc, SCSrc_b32:{ *:[i32] }:$soffset, (timm:{ *:[i32] }):$offset, (extract_cpol:{ *:[i32] } ?:{ *:[i32] }:$auxiliary), (extract_swz:{ *:[i1] } ?:{ *:[i32] }:$auxiliary))
        GIR_MakeTempReg, /*TempRegID*/0, /*TypeID*/GILLT_s64,
        GIR_BuildMI, /*InsnID*/1, /*Opcode*/GIMT_Encode2(TargetOpcode::REG_SEQUENCE),
        GIR_AddTempRegister, /*InsnID*/1, /*TempRegID*/0, /*TempRegFlags*/GIMT_Encode2(RegState::Define),
        GIR_Copy, /*NewInsnID*/1, /*OldInsnID*/0, /*OpIdx*/2, // vindex
        GIR_AddImm8, /*InsnID*/1, /*SubRegIndex*/3,
        GIR_Copy, /*NewInsnID*/1, /*OldInsnID*/0, /*OpIdx*/3, // voffset
        GIR_AddImm8, /*InsnID*/1, /*SubRegIndex*/11,
        GIR_ConstrainOperandRC, /*InsnID*/1, /*Op*/0, GIMT_Encode2(AMDGPU::VReg_64RegClassID),
        GIR_ConstrainOperandRC, /*InsnID*/1, /*Op*/1, GIMT_Encode2(AMDGPU::VGPR_32RegClassID),
        GIR_ConstrainOperandRC, /*InsnID*/1, /*Op*/3, GIMT_Encode2(AMDGPU::VGPR_32RegClassID),
        GIR_BuildMI, /*InsnID*/0, /*Opcode*/GIMT_Encode2(AMDGPU::BUFFER_LOAD_FORMAT_D16_XY_VBUFFER_BOTHEN),
        GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/0, // DstI[vdata]
        GIR_AddSimpleTempRegister, /*InsnID*/0, /*TempRegID*/0,
        GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/1, // rsrc
        GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/0, // soffset
        GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/5, // offset
        GIR_CustomOperandRenderer, /*InsnID*/0, /*OldInsnID*/0, /*OpIdx*/6, /*OperandRenderer*/GIMT_Encode2(GICR_renderExtractCPol), // auxiliary
        GIR_CustomOperandRenderer, /*InsnID*/0, /*OldInsnID*/0, /*OpIdx*/6, /*OperandRenderer*/GIMT_Encode2(GICR_renderExtractSWZ), // auxiliary
        GIR_MergeMemOperands, /*InsnID*/0, /*NumInsns*/1, /*MergeInsnID's*/0,
        GIR_ConstrainSelectedInstOperands, /*InsnID*/0,
        GIR_EraseFromParent, /*InsnID*/0,
        // GIR_Coverage, 4064,
        GIR_Done,
      // Label 6633: @487218
      GIM_Try, /*On fail goto*//*Label 6634*/ GIMT_Encode4(487328), // Rule ID 4068 //
        GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasPackedD16VMem_HasUnrestrictedSOffset),
        // MIs[0] offset
        GIM_CheckIsImm, /*MI*/0, /*Op*/5,
        // MIs[0] auxiliary
        GIM_CheckIsImm, /*MI*/0, /*Op*/6,
        // MIs[0] Operand 7
        GIM_CheckIsImm, /*MI*/0, /*Op*/7,
        GIM_CheckComplexPattern, /*MI*/0, /*Op*/4, /*Renderer*/GIMT_Encode2(0), GIMT_Encode2(GICP_gi_buf_soffset),
        // (SIbuffer_load_format_d16:{ *:[v2i16] } v4i32:{ *:[v4i32] }:$rsrc, i32:{ *:[i32] }:$vindex, i32:{ *:[i32] }:$voffset, (BUFSOffset:{ *:[i32] } i32:{ *:[i32] }:$soffset), (timm:{ *:[i32] }):$offset, (timm:{ *:[i32] }):$auxiliary, (timm:{ *:[i1] }))  =>  (BUFFER_LOAD_FORMAT_D16_XY_BOTHEN:{ *:[v2i16] } (REG_SEQUENCE:{ *:[i64] } VReg_64:{ *:[i32] }, VGPR_32:{ *:[i32] }:$vindex, sub0:{ *:[i32] }, VGPR_32:{ *:[i32] }:$voffset, sub1:{ *:[i32] }), SReg_128:{ *:[v4i32] }:$rsrc, SCSrc_b32:{ *:[i32] }:$soffset, (timm:{ *:[i32] }):$offset, (extract_cpol:{ *:[i32] } ?:{ *:[i32] }:$auxiliary), (extract_swz:{ *:[i1] } ?:{ *:[i32] }:$auxiliary))
        GIR_MakeTempReg, /*TempRegID*/0, /*TypeID*/GILLT_s64,
        GIR_BuildMI, /*InsnID*/1, /*Opcode*/GIMT_Encode2(TargetOpcode::REG_SEQUENCE),
        GIR_AddTempRegister, /*InsnID*/1, /*TempRegID*/0, /*TempRegFlags*/GIMT_Encode2(RegState::Define),
        GIR_Copy, /*NewInsnID*/1, /*OldInsnID*/0, /*OpIdx*/2, // vindex
        GIR_AddImm8, /*InsnID*/1, /*SubRegIndex*/3,
        GIR_Copy, /*NewInsnID*/1, /*OldInsnID*/0, /*OpIdx*/3, // voffset
        GIR_AddImm8, /*InsnID*/1, /*SubRegIndex*/11,
        GIR_ConstrainOperandRC, /*InsnID*/1, /*Op*/0, GIMT_Encode2(AMDGPU::VReg_64RegClassID),
        GIR_ConstrainOperandRC, /*InsnID*/1, /*Op*/1, GIMT_Encode2(AMDGPU::VGPR_32RegClassID),
        GIR_ConstrainOperandRC, /*InsnID*/1, /*Op*/3, GIMT_Encode2(AMDGPU::VGPR_32RegClassID),
        GIR_BuildMI, /*InsnID*/0, /*Opcode*/GIMT_Encode2(AMDGPU::BUFFER_LOAD_FORMAT_D16_XY_BOTHEN),
        GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/0, // DstI[vdata]
        GIR_AddSimpleTempRegister, /*InsnID*/0, /*TempRegID*/0,
        GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/1, // rsrc
        GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/0, // soffset
        GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/5, // offset
        GIR_CustomOperandRenderer, /*InsnID*/0, /*OldInsnID*/0, /*OpIdx*/6, /*OperandRenderer*/GIMT_Encode2(GICR_renderExtractCPol), // auxiliary
        GIR_CustomOperandRenderer, /*InsnID*/0, /*OldInsnID*/0, /*OpIdx*/6, /*OperandRenderer*/GIMT_Encode2(GICR_renderExtractSWZ), // auxiliary
        GIR_MergeMemOperands, /*InsnID*/0, /*NumInsns*/1, /*MergeInsnID's*/0,
        GIR_ConstrainSelectedInstOperands, /*InsnID*/0,
        GIR_EraseFromParent, /*InsnID*/0,
        // GIR_Coverage, 4068,
        GIR_Done,
      // Label 6634: @487328
      GIM_Try, /*On fail goto*//*Label 6635*/ GIMT_Encode4(487438), // Rule ID 4072 //
        GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasPackedD16VMem),
        // MIs[0] offset
        GIM_CheckIsImm, /*MI*/0, /*Op*/5,
        // MIs[0] auxiliary
        GIM_CheckIsImm, /*MI*/0, /*Op*/6,
        // MIs[0] Operand 7
        GIM_CheckIsImm, /*MI*/0, /*Op*/7,
        GIM_CheckComplexPattern, /*MI*/0, /*Op*/4, /*Renderer*/GIMT_Encode2(0), GIMT_Encode2(GICP_gi_buf_soffset),
        // (SIbuffer_load_format_d16:{ *:[v2i16] } v4i32:{ *:[v4i32] }:$rsrc, i32:{ *:[i32] }:$vindex, i32:{ *:[i32] }:$voffset, (BUFSOffset:{ *:[i32] } i32:{ *:[i32] }:$soffset), (timm:{ *:[i32] }):$offset, (timm:{ *:[i32] }):$auxiliary, (timm:{ *:[i1] }))  =>  (BUFFER_LOAD_FORMAT_D16_XY_VBUFFER_BOTHEN:{ *:[v2i16] } (REG_SEQUENCE:{ *:[i64] } VReg_64:{ *:[i32] }, VGPR_32:{ *:[i32] }:$vindex, sub0:{ *:[i32] }, VGPR_32:{ *:[i32] }:$voffset, sub1:{ *:[i32] }), SReg_128:{ *:[v4i32] }:$rsrc, SCSrc_b32:{ *:[i32] }:$soffset, (timm:{ *:[i32] }):$offset, (extract_cpol:{ *:[i32] } ?:{ *:[i32] }:$auxiliary), (extract_swz:{ *:[i1] } ?:{ *:[i32] }:$auxiliary))
        GIR_MakeTempReg, /*TempRegID*/0, /*TypeID*/GILLT_s64,
        GIR_BuildMI, /*InsnID*/1, /*Opcode*/GIMT_Encode2(TargetOpcode::REG_SEQUENCE),
        GIR_AddTempRegister, /*InsnID*/1, /*TempRegID*/0, /*TempRegFlags*/GIMT_Encode2(RegState::Define),
        GIR_Copy, /*NewInsnID*/1, /*OldInsnID*/0, /*OpIdx*/2, // vindex
        GIR_AddImm8, /*InsnID*/1, /*SubRegIndex*/3,
        GIR_Copy, /*NewInsnID*/1, /*OldInsnID*/0, /*OpIdx*/3, // voffset
        GIR_AddImm8, /*InsnID*/1, /*SubRegIndex*/11,
        GIR_ConstrainOperandRC, /*InsnID*/1, /*Op*/0, GIMT_Encode2(AMDGPU::VReg_64RegClassID),
        GIR_ConstrainOperandRC, /*InsnID*/1, /*Op*/1, GIMT_Encode2(AMDGPU::VGPR_32RegClassID),
        GIR_ConstrainOperandRC, /*InsnID*/1, /*Op*/3, GIMT_Encode2(AMDGPU::VGPR_32RegClassID),
        GIR_BuildMI, /*InsnID*/0, /*Opcode*/GIMT_Encode2(AMDGPU::BUFFER_LOAD_FORMAT_D16_XY_VBUFFER_BOTHEN),
        GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/0, // DstI[vdata]
        GIR_AddSimpleTempRegister, /*InsnID*/0, /*TempRegID*/0,
        GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/1, // rsrc
        GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/0, // soffset
        GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/5, // offset
        GIR_CustomOperandRenderer, /*InsnID*/0, /*OldInsnID*/0, /*OpIdx*/6, /*OperandRenderer*/GIMT_Encode2(GICR_renderExtractCPol), // auxiliary
        GIR_CustomOperandRenderer, /*InsnID*/0, /*OldInsnID*/0, /*OpIdx*/6, /*OperandRenderer*/GIMT_Encode2(GICR_renderExtractSWZ), // auxiliary
        GIR_MergeMemOperands, /*InsnID*/0, /*NumInsns*/1, /*MergeInsnID's*/0,
        GIR_ConstrainSelectedInstOperands, /*InsnID*/0,
        GIR_EraseFromParent, /*InsnID*/0,
        // GIR_Coverage, 4072,
        GIR_Done,
      // Label 6635: @487438
      GIM_Reject,
    // Label 6619: @487439
    GIM_Reject,
    // Label 6576: @487440
    GIM_Try, /*On fail goto*//*Label 6636*/ GIMT_Encode4(487815),
      GIM_CheckType, /*MI*/0, /*Op*/1, /*Type*/GILLT_v4s32,
      GIM_CheckType, /*MI*/0, /*Op*/2, /*Type*/GILLT_s32,
      GIM_CheckType, /*MI*/0, /*Op*/3, /*Type*/GILLT_s32,
      GIM_CheckType, /*MI*/0, /*Op*/4, /*Type*/GILLT_s32,
      GIM_CheckRegBankForClass, /*MI*/0, /*Op*/0, /*RC*/GIMT_Encode2(AMDGPU::AV_64RegClassID),
      GIM_Try, /*On fail goto*//*Label 6637*/ GIMT_Encode4(487548), // Rule ID 4021 //
        GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasUnpackedD16VMem),
        GIM_CheckConstantInt8, /*MI*/0, /*Op*/2, 0,
        GIM_CheckConstantInt8, /*MI*/0, /*Op*/3, 0,
        // MIs[0] offset
        GIM_CheckIsImm, /*MI*/0, /*Op*/5,
        // MIs[0] auxiliary
        GIM_CheckIsImm, /*MI*/0, /*Op*/6,
        // MIs[0] Operand 7
        GIM_CheckLiteralInt, /*MI*/0, /*Op*/7, GIMT_Encode8(0),
        GIM_CheckComplexPattern, /*MI*/0, /*Op*/4, /*Renderer*/GIMT_Encode2(0), GIMT_Encode2(GICP_gi_buf_soffset),
        // (SIbuffer_load_format_d16:{ *:[v2i32] } v4i32:{ *:[v4i32] }:$rsrc, 0:{ *:[i32] }, 0:{ *:[i32] }, (BUFSOffset:{ *:[i32] } i32:{ *:[i32] }:$soffset), (timm:{ *:[i32] }):$offset, (timm:{ *:[i32] }):$auxiliary, 0:{ *:[i1] })  =>  (BUFFER_LOAD_FORMAT_D16_XY_gfx80_OFFSET:{ *:[v2i32] } SReg_128:{ *:[v4i32] }:$rsrc, SCSrc_b32:{ *:[i32] }:$soffset, (timm:{ *:[i32] }):$offset, (extract_cpol:{ *:[i32] } ?:{ *:[i32] }:$auxiliary), (extract_swz:{ *:[i1] } ?:{ *:[i32] }:$auxiliary))
        GIR_BuildMI, /*InsnID*/0, /*Opcode*/GIMT_Encode2(AMDGPU::BUFFER_LOAD_FORMAT_D16_XY_gfx80_OFFSET),
        GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/0, // DstI[vdata]
        GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/1, // rsrc
        GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/0, // soffset
        GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/5, // offset
        GIR_CustomOperandRenderer, /*InsnID*/0, /*OldInsnID*/0, /*OpIdx*/6, /*OperandRenderer*/GIMT_Encode2(GICR_renderExtractCPol), // auxiliary
        GIR_CustomOperandRenderer, /*InsnID*/0, /*OldInsnID*/0, /*OpIdx*/6, /*OperandRenderer*/GIMT_Encode2(GICR_renderExtractSWZ), // auxiliary
        GIR_MergeMemOperands, /*InsnID*/0, /*NumInsns*/1, /*MergeInsnID's*/0,
        GIR_ConstrainSelectedInstOperands, /*InsnID*/0,
        GIR_EraseFromParent, /*InsnID*/0,
        // GIR_Coverage, 4021,
        GIR_Done,
      // Label 6637: @487548
      GIM_Try, /*On fail goto*//*Label 6638*/ GIMT_Encode4(487630), // Rule ID 4022 //
        GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasUnpackedD16VMem),
        GIM_CheckConstantInt8, /*MI*/0, /*Op*/2, 0,
        // MIs[0] offset
        GIM_CheckIsImm, /*MI*/0, /*Op*/5,
        // MIs[0] auxiliary
        GIM_CheckIsImm, /*MI*/0, /*Op*/6,
        // MIs[0] Operand 7
        GIM_CheckLiteralInt, /*MI*/0, /*Op*/7, GIMT_Encode8(0),
        GIM_CheckComplexPattern, /*MI*/0, /*Op*/4, /*Renderer*/GIMT_Encode2(0), GIMT_Encode2(GICP_gi_buf_soffset),
        // (SIbuffer_load_format_d16:{ *:[v2i32] } v4i32:{ *:[v4i32] }:$rsrc, 0:{ *:[i32] }, i32:{ *:[i32] }:$voffset, (BUFSOffset:{ *:[i32] } i32:{ *:[i32] }:$soffset), (timm:{ *:[i32] }):$offset, (timm:{ *:[i32] }):$auxiliary, 0:{ *:[i1] })  =>  (BUFFER_LOAD_FORMAT_D16_XY_gfx80_OFFEN:{ *:[v2i32] } VGPR_32:{ *:[i32] }:$voffset, SReg_128:{ *:[v4i32] }:$rsrc, SCSrc_b32:{ *:[i32] }:$soffset, (timm:{ *:[i32] }):$offset, (extract_cpol:{ *:[i32] } ?:{ *:[i32] }:$auxiliary), (extract_swz:{ *:[i1] } ?:{ *:[i32] }:$auxiliary))
        GIR_BuildMI, /*InsnID*/0, /*Opcode*/GIMT_Encode2(AMDGPU::BUFFER_LOAD_FORMAT_D16_XY_gfx80_OFFEN),
        GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/0, // DstI[vdata]
        GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/3, // voffset
        GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/1, // rsrc
        GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/0, // soffset
        GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/5, // offset
        GIR_CustomOperandRenderer, /*InsnID*/0, /*OldInsnID*/0, /*OpIdx*/6, /*OperandRenderer*/GIMT_Encode2(GICR_renderExtractCPol), // auxiliary
        GIR_CustomOperandRenderer, /*InsnID*/0, /*OldInsnID*/0, /*OpIdx*/6, /*OperandRenderer*/GIMT_Encode2(GICR_renderExtractSWZ), // auxiliary
        GIR_MergeMemOperands, /*InsnID*/0, /*NumInsns*/1, /*MergeInsnID's*/0,
        GIR_ConstrainSelectedInstOperands, /*InsnID*/0,
        GIR_EraseFromParent, /*InsnID*/0,
        // GIR_Coverage, 4022,
        GIR_Done,
      // Label 6638: @487630
      GIM_Try, /*On fail goto*//*Label 6639*/ GIMT_Encode4(487704), // Rule ID 4023 //
        GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasUnpackedD16VMem),
        GIM_CheckConstantInt8, /*MI*/0, /*Op*/3, 0,
        // MIs[0] offset
        GIM_CheckIsImm, /*MI*/0, /*Op*/5,
        // MIs[0] auxiliary
        GIM_CheckIsImm, /*MI*/0, /*Op*/6,
        // MIs[0] Operand 7
        GIM_CheckIsImm, /*MI*/0, /*Op*/7,
        GIM_CheckComplexPattern, /*MI*/0, /*Op*/4, /*Renderer*/GIMT_Encode2(0), GIMT_Encode2(GICP_gi_buf_soffset),
        // (SIbuffer_load_format_d16:{ *:[v2i32] } v4i32:{ *:[v4i32] }:$rsrc, i32:{ *:[i32] }:$vindex, 0:{ *:[i32] }, (BUFSOffset:{ *:[i32] } i32:{ *:[i32] }:$soffset), (timm:{ *:[i32] }):$offset, (timm:{ *:[i32] }):$auxiliary, (timm:{ *:[i1] }))  =>  (BUFFER_LOAD_FORMAT_D16_XY_gfx80_IDXEN:{ *:[v2i32] } VGPR_32:{ *:[i32] }:$vindex, SReg_128:{ *:[v4i32] }:$rsrc, SCSrc_b32:{ *:[i32] }:$soffset, (timm:{ *:[i32] }):$offset, (extract_cpol:{ *:[i32] } ?:{ *:[i32] }:$auxiliary), (extract_swz:{ *:[i1] } ?:{ *:[i32] }:$auxiliary))
        GIR_BuildMI, /*InsnID*/0, /*Opcode*/GIMT_Encode2(AMDGPU::BUFFER_LOAD_FORMAT_D16_XY_gfx80_IDXEN),
        GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/0, // DstI[vdata]
        GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/2, // vindex
        GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/1, // rsrc
        GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/0, // soffset
        GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/5, // offset
        GIR_CustomOperandRenderer, /*InsnID*/0, /*OldInsnID*/0, /*OpIdx*/6, /*OperandRenderer*/GIMT_Encode2(GICR_renderExtractCPol), // auxiliary
        GIR_CustomOperandRenderer, /*InsnID*/0, /*OldInsnID*/0, /*OpIdx*/6, /*OperandRenderer*/GIMT_Encode2(GICR_renderExtractSWZ), // auxiliary
        GIR_MergeMemOperands, /*InsnID*/0, /*NumInsns*/1, /*MergeInsnID's*/0,
        GIR_ConstrainSelectedInstOperands, /*InsnID*/0,
        GIR_EraseFromParent, /*InsnID*/0,
        // GIR_Coverage, 4023,
        GIR_Done,
      // Label 6639: @487704
      GIM_Try, /*On fail goto*//*Label 6640*/ GIMT_Encode4(487814), // Rule ID 4024 //
        GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasUnpackedD16VMem),
        // MIs[0] offset
        GIM_CheckIsImm, /*MI*/0, /*Op*/5,
        // MIs[0] auxiliary
        GIM_CheckIsImm, /*MI*/0, /*Op*/6,
        // MIs[0] Operand 7
        GIM_CheckIsImm, /*MI*/0, /*Op*/7,
        GIM_CheckComplexPattern, /*MI*/0, /*Op*/4, /*Renderer*/GIMT_Encode2(0), GIMT_Encode2(GICP_gi_buf_soffset),
        // (SIbuffer_load_format_d16:{ *:[v2i32] } v4i32:{ *:[v4i32] }:$rsrc, i32:{ *:[i32] }:$vindex, i32:{ *:[i32] }:$voffset, (BUFSOffset:{ *:[i32] } i32:{ *:[i32] }:$soffset), (timm:{ *:[i32] }):$offset, (timm:{ *:[i32] }):$auxiliary, (timm:{ *:[i1] }))  =>  (BUFFER_LOAD_FORMAT_D16_XY_gfx80_BOTHEN:{ *:[v2i32] } (REG_SEQUENCE:{ *:[i64] } VReg_64:{ *:[i32] }, VGPR_32:{ *:[i32] }:$vindex, sub0:{ *:[i32] }, VGPR_32:{ *:[i32] }:$voffset, sub1:{ *:[i32] }), SReg_128:{ *:[v4i32] }:$rsrc, SCSrc_b32:{ *:[i32] }:$soffset, (timm:{ *:[i32] }):$offset, (extract_cpol:{ *:[i32] } ?:{ *:[i32] }:$auxiliary), (extract_swz:{ *:[i1] } ?:{ *:[i32] }:$auxiliary))
        GIR_MakeTempReg, /*TempRegID*/0, /*TypeID*/GILLT_s64,
        GIR_BuildMI, /*InsnID*/1, /*Opcode*/GIMT_Encode2(TargetOpcode::REG_SEQUENCE),
        GIR_AddTempRegister, /*InsnID*/1, /*TempRegID*/0, /*TempRegFlags*/GIMT_Encode2(RegState::Define),
        GIR_Copy, /*NewInsnID*/1, /*OldInsnID*/0, /*OpIdx*/2, // vindex
        GIR_AddImm8, /*InsnID*/1, /*SubRegIndex*/3,
        GIR_Copy, /*NewInsnID*/1, /*OldInsnID*/0, /*OpIdx*/3, // voffset
        GIR_AddImm8, /*InsnID*/1, /*SubRegIndex*/11,
        GIR_ConstrainOperandRC, /*InsnID*/1, /*Op*/0, GIMT_Encode2(AMDGPU::VReg_64RegClassID),
        GIR_ConstrainOperandRC, /*InsnID*/1, /*Op*/1, GIMT_Encode2(AMDGPU::VGPR_32RegClassID),
        GIR_ConstrainOperandRC, /*InsnID*/1, /*Op*/3, GIMT_Encode2(AMDGPU::VGPR_32RegClassID),
        GIR_BuildMI, /*InsnID*/0, /*Opcode*/GIMT_Encode2(AMDGPU::BUFFER_LOAD_FORMAT_D16_XY_gfx80_BOTHEN),
        GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/0, // DstI[vdata]
        GIR_AddSimpleTempRegister, /*InsnID*/0, /*TempRegID*/0,
        GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/1, // rsrc
        GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/0, // soffset
        GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/5, // offset
        GIR_CustomOperandRenderer, /*InsnID*/0, /*OldInsnID*/0, /*OpIdx*/6, /*OperandRenderer*/GIMT_Encode2(GICR_renderExtractCPol), // auxiliary
        GIR_CustomOperandRenderer, /*InsnID*/0, /*OldInsnID*/0, /*OpIdx*/6, /*OperandRenderer*/GIMT_Encode2(GICR_renderExtractSWZ), // auxiliary
        GIR_MergeMemOperands, /*InsnID*/0, /*NumInsns*/1, /*MergeInsnID's*/0,
        GIR_ConstrainSelectedInstOperands, /*InsnID*/0,
        GIR_EraseFromParent, /*InsnID*/0,
        // GIR_Coverage, 4024,
        GIR_Done,
      // Label 6640: @487814
      GIM_Reject,
    // Label 6636: @487815
    GIM_Reject,
    // Label 6577: @487816
    GIM_Try, /*On fail goto*//*Label 6641*/ GIMT_Encode4(488191),
      GIM_CheckType, /*MI*/0, /*Op*/1, /*Type*/GILLT_v4s32,
      GIM_CheckType, /*MI*/0, /*Op*/2, /*Type*/GILLT_s32,
      GIM_CheckType, /*MI*/0, /*Op*/3, /*Type*/GILLT_s32,
      GIM_CheckType, /*MI*/0, /*Op*/4, /*Type*/GILLT_s32,
      GIM_CheckRegBankForClass, /*MI*/0, /*Op*/0, /*RC*/GIMT_Encode2(AMDGPU::AV_96RegClassID),
      GIM_Try, /*On fail goto*//*Label 6642*/ GIMT_Encode4(487924), // Rule ID 4025 //
        GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasUnpackedD16VMem),
        GIM_CheckConstantInt8, /*MI*/0, /*Op*/2, 0,
        GIM_CheckConstantInt8, /*MI*/0, /*Op*/3, 0,
        // MIs[0] offset
        GIM_CheckIsImm, /*MI*/0, /*Op*/5,
        // MIs[0] auxiliary
        GIM_CheckIsImm, /*MI*/0, /*Op*/6,
        // MIs[0] Operand 7
        GIM_CheckLiteralInt, /*MI*/0, /*Op*/7, GIMT_Encode8(0),
        GIM_CheckComplexPattern, /*MI*/0, /*Op*/4, /*Renderer*/GIMT_Encode2(0), GIMT_Encode2(GICP_gi_buf_soffset),
        // (SIbuffer_load_format_d16:{ *:[v3i32] } v4i32:{ *:[v4i32] }:$rsrc, 0:{ *:[i32] }, 0:{ *:[i32] }, (BUFSOffset:{ *:[i32] } i32:{ *:[i32] }:$soffset), (timm:{ *:[i32] }):$offset, (timm:{ *:[i32] }):$auxiliary, 0:{ *:[i1] })  =>  (BUFFER_LOAD_FORMAT_D16_XYZ_gfx80_OFFSET:{ *:[v3i32] } SReg_128:{ *:[v4i32] }:$rsrc, SCSrc_b32:{ *:[i32] }:$soffset, (timm:{ *:[i32] }):$offset, (extract_cpol:{ *:[i32] } ?:{ *:[i32] }:$auxiliary), (extract_swz:{ *:[i1] } ?:{ *:[i32] }:$auxiliary))
        GIR_BuildMI, /*InsnID*/0, /*Opcode*/GIMT_Encode2(AMDGPU::BUFFER_LOAD_FORMAT_D16_XYZ_gfx80_OFFSET),
        GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/0, // DstI[vdata]
        GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/1, // rsrc
        GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/0, // soffset
        GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/5, // offset
        GIR_CustomOperandRenderer, /*InsnID*/0, /*OldInsnID*/0, /*OpIdx*/6, /*OperandRenderer*/GIMT_Encode2(GICR_renderExtractCPol), // auxiliary
        GIR_CustomOperandRenderer, /*InsnID*/0, /*OldInsnID*/0, /*OpIdx*/6, /*OperandRenderer*/GIMT_Encode2(GICR_renderExtractSWZ), // auxiliary
        GIR_MergeMemOperands, /*InsnID*/0, /*NumInsns*/1, /*MergeInsnID's*/0,
        GIR_ConstrainSelectedInstOperands, /*InsnID*/0,
        GIR_EraseFromParent, /*InsnID*/0,
        // GIR_Coverage, 4025,
        GIR_Done,
      // Label 6642: @487924
      GIM_Try, /*On fail goto*//*Label 6643*/ GIMT_Encode4(488006), // Rule ID 4026 //
        GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasUnpackedD16VMem),
        GIM_CheckConstantInt8, /*MI*/0, /*Op*/2, 0,
        // MIs[0] offset
        GIM_CheckIsImm, /*MI*/0, /*Op*/5,
        // MIs[0] auxiliary
        GIM_CheckIsImm, /*MI*/0, /*Op*/6,
        // MIs[0] Operand 7
        GIM_CheckLiteralInt, /*MI*/0, /*Op*/7, GIMT_Encode8(0),
        GIM_CheckComplexPattern, /*MI*/0, /*Op*/4, /*Renderer*/GIMT_Encode2(0), GIMT_Encode2(GICP_gi_buf_soffset),
        // (SIbuffer_load_format_d16:{ *:[v3i32] } v4i32:{ *:[v4i32] }:$rsrc, 0:{ *:[i32] }, i32:{ *:[i32] }:$voffset, (BUFSOffset:{ *:[i32] } i32:{ *:[i32] }:$soffset), (timm:{ *:[i32] }):$offset, (timm:{ *:[i32] }):$auxiliary, 0:{ *:[i1] })  =>  (BUFFER_LOAD_FORMAT_D16_XYZ_gfx80_OFFEN:{ *:[v3i32] } VGPR_32:{ *:[i32] }:$voffset, SReg_128:{ *:[v4i32] }:$rsrc, SCSrc_b32:{ *:[i32] }:$soffset, (timm:{ *:[i32] }):$offset, (extract_cpol:{ *:[i32] } ?:{ *:[i32] }:$auxiliary), (extract_swz:{ *:[i1] } ?:{ *:[i32] }:$auxiliary))
        GIR_BuildMI, /*InsnID*/0, /*Opcode*/GIMT_Encode2(AMDGPU::BUFFER_LOAD_FORMAT_D16_XYZ_gfx80_OFFEN),
        GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/0, // DstI[vdata]
        GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/3, // voffset
        GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/1, // rsrc
        GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/0, // soffset
        GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/5, // offset
        GIR_CustomOperandRenderer, /*InsnID*/0, /*OldInsnID*/0, /*OpIdx*/6, /*OperandRenderer*/GIMT_Encode2(GICR_renderExtractCPol), // auxiliary
        GIR_CustomOperandRenderer, /*InsnID*/0, /*OldInsnID*/0, /*OpIdx*/6, /*OperandRenderer*/GIMT_Encode2(GICR_renderExtractSWZ), // auxiliary
        GIR_MergeMemOperands, /*InsnID*/0, /*NumInsns*/1, /*MergeInsnID's*/0,
        GIR_ConstrainSelectedInstOperands, /*InsnID*/0,
        GIR_EraseFromParent, /*InsnID*/0,
        // GIR_Coverage, 4026,
        GIR_Done,
      // Label 6643: @488006
      GIM_Try, /*On fail goto*//*Label 6644*/ GIMT_Encode4(488080), // Rule ID 4027 //
        GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasUnpackedD16VMem),
        GIM_CheckConstantInt8, /*MI*/0, /*Op*/3, 0,
        // MIs[0] offset
        GIM_CheckIsImm, /*MI*/0, /*Op*/5,
        // MIs[0] auxiliary
        GIM_CheckIsImm, /*MI*/0, /*Op*/6,
        // MIs[0] Operand 7
        GIM_CheckIsImm, /*MI*/0, /*Op*/7,
        GIM_CheckComplexPattern, /*MI*/0, /*Op*/4, /*Renderer*/GIMT_Encode2(0), GIMT_Encode2(GICP_gi_buf_soffset),
        // (SIbuffer_load_format_d16:{ *:[v3i32] } v4i32:{ *:[v4i32] }:$rsrc, i32:{ *:[i32] }:$vindex, 0:{ *:[i32] }, (BUFSOffset:{ *:[i32] } i32:{ *:[i32] }:$soffset), (timm:{ *:[i32] }):$offset, (timm:{ *:[i32] }):$auxiliary, (timm:{ *:[i1] }))  =>  (BUFFER_LOAD_FORMAT_D16_XYZ_gfx80_IDXEN:{ *:[v3i32] } VGPR_32:{ *:[i32] }:$vindex, SReg_128:{ *:[v4i32] }:$rsrc, SCSrc_b32:{ *:[i32] }:$soffset, (timm:{ *:[i32] }):$offset, (extract_cpol:{ *:[i32] } ?:{ *:[i32] }:$auxiliary), (extract_swz:{ *:[i1] } ?:{ *:[i32] }:$auxiliary))
        GIR_BuildMI, /*InsnID*/0, /*Opcode*/GIMT_Encode2(AMDGPU::BUFFER_LOAD_FORMAT_D16_XYZ_gfx80_IDXEN),
        GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/0, // DstI[vdata]
        GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/2, // vindex
        GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/1, // rsrc
        GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/0, // soffset
        GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/5, // offset
        GIR_CustomOperandRenderer, /*InsnID*/0, /*OldInsnID*/0, /*OpIdx*/6, /*OperandRenderer*/GIMT_Encode2(GICR_renderExtractCPol), // auxiliary
        GIR_CustomOperandRenderer, /*InsnID*/0, /*OldInsnID*/0, /*OpIdx*/6, /*OperandRenderer*/GIMT_Encode2(GICR_renderExtractSWZ), // auxiliary
        GIR_MergeMemOperands, /*InsnID*/0, /*NumInsns*/1, /*MergeInsnID's*/0,
        GIR_ConstrainSelectedInstOperands, /*InsnID*/0,
        GIR_EraseFromParent, /*InsnID*/0,
        // GIR_Coverage, 4027,
        GIR_Done,
      // Label 6644: @488080
      GIM_Try, /*On fail goto*//*Label 6645*/ GIMT_Encode4(488190), // Rule ID 4028 //
        GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasUnpackedD16VMem),
        // MIs[0] offset
        GIM_CheckIsImm, /*MI*/0, /*Op*/5,
        // MIs[0] auxiliary
        GIM_CheckIsImm, /*MI*/0, /*Op*/6,
        // MIs[0] Operand 7
        GIM_CheckIsImm, /*MI*/0, /*Op*/7,
        GIM_CheckComplexPattern, /*MI*/0, /*Op*/4, /*Renderer*/GIMT_Encode2(0), GIMT_Encode2(GICP_gi_buf_soffset),
        // (SIbuffer_load_format_d16:{ *:[v3i32] } v4i32:{ *:[v4i32] }:$rsrc, i32:{ *:[i32] }:$vindex, i32:{ *:[i32] }:$voffset, (BUFSOffset:{ *:[i32] } i32:{ *:[i32] }:$soffset), (timm:{ *:[i32] }):$offset, (timm:{ *:[i32] }):$auxiliary, (timm:{ *:[i1] }))  =>  (BUFFER_LOAD_FORMAT_D16_XYZ_gfx80_BOTHEN:{ *:[v3i32] } (REG_SEQUENCE:{ *:[i64] } VReg_64:{ *:[i32] }, VGPR_32:{ *:[i32] }:$vindex, sub0:{ *:[i32] }, VGPR_32:{ *:[i32] }:$voffset, sub1:{ *:[i32] }), SReg_128:{ *:[v4i32] }:$rsrc, SCSrc_b32:{ *:[i32] }:$soffset, (timm:{ *:[i32] }):$offset, (extract_cpol:{ *:[i32] } ?:{ *:[i32] }:$auxiliary), (extract_swz:{ *:[i1] } ?:{ *:[i32] }:$auxiliary))
        GIR_MakeTempReg, /*TempRegID*/0, /*TypeID*/GILLT_s64,
        GIR_BuildMI, /*InsnID*/1, /*Opcode*/GIMT_Encode2(TargetOpcode::REG_SEQUENCE),
        GIR_AddTempRegister, /*InsnID*/1, /*TempRegID*/0, /*TempRegFlags*/GIMT_Encode2(RegState::Define),
        GIR_Copy, /*NewInsnID*/1, /*OldInsnID*/0, /*OpIdx*/2, // vindex
        GIR_AddImm8, /*InsnID*/1, /*SubRegIndex*/3,
        GIR_Copy, /*NewInsnID*/1, /*OldInsnID*/0, /*OpIdx*/3, // voffset
        GIR_AddImm8, /*InsnID*/1, /*SubRegIndex*/11,
        GIR_ConstrainOperandRC, /*InsnID*/1, /*Op*/0, GIMT_Encode2(AMDGPU::VReg_64RegClassID),
        GIR_ConstrainOperandRC, /*InsnID*/1, /*Op*/1, GIMT_Encode2(AMDGPU::VGPR_32RegClassID),
        GIR_ConstrainOperandRC, /*InsnID*/1, /*Op*/3, GIMT_Encode2(AMDGPU::VGPR_32RegClassID),
        GIR_BuildMI, /*InsnID*/0, /*Opcode*/GIMT_Encode2(AMDGPU::BUFFER_LOAD_FORMAT_D16_XYZ_gfx80_BOTHEN),
        GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/0, // DstI[vdata]
        GIR_AddSimpleTempRegister, /*InsnID*/0, /*TempRegID*/0,
        GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/1, // rsrc
        GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/0, // soffset
        GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/5, // offset
        GIR_CustomOperandRenderer, /*InsnID*/0, /*OldInsnID*/0, /*OpIdx*/6, /*OperandRenderer*/GIMT_Encode2(GICR_renderExtractCPol), // auxiliary
        GIR_CustomOperandRenderer, /*InsnID*/0, /*OldInsnID*/0, /*OpIdx*/6, /*OperandRenderer*/GIMT_Encode2(GICR_renderExtractSWZ), // auxiliary
        GIR_MergeMemOperands, /*InsnID*/0, /*NumInsns*/1, /*MergeInsnID's*/0,
        GIR_ConstrainSelectedInstOperands, /*InsnID*/0,
        GIR_EraseFromParent, /*InsnID*/0,
        // GIR_Coverage, 4028,
        GIR_Done,
      // Label 6645: @488190
      GIM_Reject,
    // Label 6641: @488191
    GIM_Reject,
    // Label 6578: @488192
    GIM_Try, /*On fail goto*//*Label 6646*/ GIMT_Encode4(491270),
      GIM_CheckType, /*MI*/0, /*Op*/1, /*Type*/GILLT_v4s32,
      GIM_CheckType, /*MI*/0, /*Op*/2, /*Type*/GILLT_s32,
      GIM_CheckType, /*MI*/0, /*Op*/3, /*Type*/GILLT_s32,
      GIM_CheckType, /*MI*/0, /*Op*/4, /*Type*/GILLT_s32,
      GIM_Try, /*On fail goto*//*Label 6647*/ GIMT_Encode4(488307), // Rule ID 4073 //
        GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasPackedD16VMem_HasUnrestrictedSOffset),
        GIM_CheckMemorySizeEqualTo, /*MI*/0, /*MMO*/0, /*Size*/GIMT_Encode4(6),
        GIM_CheckRegBankForClass, /*MI*/0, /*Op*/0, /*RC*/GIMT_Encode2(AMDGPU::AV_64RegClassID),
        GIM_CheckConstantInt8, /*MI*/0, /*Op*/2, 0,
        GIM_CheckConstantInt8, /*MI*/0, /*Op*/3, 0,
        // MIs[0] offset
        GIM_CheckIsImm, /*MI*/0, /*Op*/5,
        // MIs[0] auxiliary
        GIM_CheckIsImm, /*MI*/0, /*Op*/6,
        // MIs[0] Operand 7
        GIM_CheckLiteralInt, /*MI*/0, /*Op*/7, GIMT_Encode8(0),
        GIM_CheckComplexPattern, /*MI*/0, /*Op*/4, /*Renderer*/GIMT_Encode2(0), GIMT_Encode2(GICP_gi_buf_soffset),
        // (SIbuffer_load_format_d16:{ *:[v4f16] } v4i32:{ *:[v4i32] }:$rsrc, 0:{ *:[i32] }, 0:{ *:[i32] }, (BUFSOffset:{ *:[i32] } i32:{ *:[i32] }:$soffset), (timm:{ *:[i32] }):$offset, (timm:{ *:[i32] }):$auxiliary, 0:{ *:[i1] })<<P:Predicate_anonymous_32257>>  =>  (BUFFER_LOAD_FORMAT_D16_XYZ_OFFSET:{ *:[v4f16] } SReg_128:{ *:[v4i32] }:$rsrc, SCSrc_b32:{ *:[i32] }:$soffset, (timm:{ *:[i32] }):$offset, (extract_cpol:{ *:[i32] } ?:{ *:[i32] }:$auxiliary), (extract_swz:{ *:[i1] } ?:{ *:[i32] }:$auxiliary))
        GIR_BuildMI, /*InsnID*/0, /*Opcode*/GIMT_Encode2(AMDGPU::BUFFER_LOAD_FORMAT_D16_XYZ_OFFSET),
        GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/0, // DstI[vdata]
        GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/1, // rsrc
        GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/0, // soffset
        GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/5, // offset
        GIR_CustomOperandRenderer, /*InsnID*/0, /*OldInsnID*/0, /*OpIdx*/6, /*OperandRenderer*/GIMT_Encode2(GICR_renderExtractCPol), // auxiliary
        GIR_CustomOperandRenderer, /*InsnID*/0, /*OldInsnID*/0, /*OpIdx*/6, /*OperandRenderer*/GIMT_Encode2(GICR_renderExtractSWZ), // auxiliary
        GIR_MergeMemOperands, /*InsnID*/0, /*NumInsns*/1, /*MergeInsnID's*/0,
        GIR_ConstrainSelectedInstOperands, /*InsnID*/0,
        GIR_EraseFromParent, /*InsnID*/0,
        // GIR_Coverage, 4073,
        GIR_Done,
      // Label 6647: @488307
      GIM_Try, /*On fail goto*//*Label 6648*/ GIMT_Encode4(488401), // Rule ID 4077 //
        GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasPackedD16VMem),
        GIM_CheckMemorySizeEqualTo, /*MI*/0, /*MMO*/0, /*Size*/GIMT_Encode4(6),
        GIM_CheckRegBankForClass, /*MI*/0, /*Op*/0, /*RC*/GIMT_Encode2(AMDGPU::AV_64RegClassID),
        GIM_CheckConstantInt8, /*MI*/0, /*Op*/2, 0,
        GIM_CheckConstantInt8, /*MI*/0, /*Op*/3, 0,
        // MIs[0] offset
        GIM_CheckIsImm, /*MI*/0, /*Op*/5,
        // MIs[0] auxiliary
        GIM_CheckIsImm, /*MI*/0, /*Op*/6,
        // MIs[0] Operand 7
        GIM_CheckLiteralInt, /*MI*/0, /*Op*/7, GIMT_Encode8(0),
        GIM_CheckComplexPattern, /*MI*/0, /*Op*/4, /*Renderer*/GIMT_Encode2(0), GIMT_Encode2(GICP_gi_buf_soffset),
        // (SIbuffer_load_format_d16:{ *:[v4f16] } v4i32:{ *:[v4i32] }:$rsrc, 0:{ *:[i32] }, 0:{ *:[i32] }, (BUFSOffset:{ *:[i32] } i32:{ *:[i32] }:$soffset), (timm:{ *:[i32] }):$offset, (timm:{ *:[i32] }):$auxiliary, 0:{ *:[i1] })<<P:Predicate_anonymous_32257>>  =>  (BUFFER_LOAD_FORMAT_D16_XYZ_VBUFFER_OFFSET:{ *:[v4f16] } SReg_128:{ *:[v4i32] }:$rsrc, SCSrc_b32:{ *:[i32] }:$soffset, (timm:{ *:[i32] }):$offset, (extract_cpol:{ *:[i32] } ?:{ *:[i32] }:$auxiliary), (extract_swz:{ *:[i1] } ?:{ *:[i32] }:$auxiliary))
        GIR_BuildMI, /*InsnID*/0, /*Opcode*/GIMT_Encode2(AMDGPU::BUFFER_LOAD_FORMAT_D16_XYZ_VBUFFER_OFFSET),
        GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/0, // DstI[vdata]
        GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/1, // rsrc
        GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/0, // soffset
        GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/5, // offset
        GIR_CustomOperandRenderer, /*InsnID*/0, /*OldInsnID*/0, /*OpIdx*/6, /*OperandRenderer*/GIMT_Encode2(GICR_renderExtractCPol), // auxiliary
        GIR_CustomOperandRenderer, /*InsnID*/0, /*OldInsnID*/0, /*OpIdx*/6, /*OperandRenderer*/GIMT_Encode2(GICR_renderExtractSWZ), // auxiliary
        GIR_MergeMemOperands, /*InsnID*/0, /*NumInsns*/1, /*MergeInsnID's*/0,
        GIR_ConstrainSelectedInstOperands, /*InsnID*/0,
        GIR_EraseFromParent, /*InsnID*/0,
        // GIR_Coverage, 4077,
        GIR_Done,
      // Label 6648: @488401
      GIM_Try, /*On fail goto*//*Label 6649*/ GIMT_Encode4(488495), // Rule ID 4081 //
        GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasPackedD16VMem_HasUnrestrictedSOffset),
        GIM_CheckMemorySizeEqualTo, /*MI*/0, /*MMO*/0, /*Size*/GIMT_Encode4(6),
        GIM_CheckRegBankForClass, /*MI*/0, /*Op*/0, /*RC*/GIMT_Encode2(AMDGPU::AV_64RegClassID),
        GIM_CheckConstantInt8, /*MI*/0, /*Op*/2, 0,
        GIM_CheckConstantInt8, /*MI*/0, /*Op*/3, 0,
        // MIs[0] offset
        GIM_CheckIsImm, /*MI*/0, /*Op*/5,
        // MIs[0] auxiliary
        GIM_CheckIsImm, /*MI*/0, /*Op*/6,
        // MIs[0] Operand 7
        GIM_CheckLiteralInt, /*MI*/0, /*Op*/7, GIMT_Encode8(0),
        GIM_CheckComplexPattern, /*MI*/0, /*Op*/4, /*Renderer*/GIMT_Encode2(0), GIMT_Encode2(GICP_gi_buf_soffset),
        // (SIbuffer_load_format_d16:{ *:[v4i16] } v4i32:{ *:[v4i32] }:$rsrc, 0:{ *:[i32] }, 0:{ *:[i32] }, (BUFSOffset:{ *:[i32] } i32:{ *:[i32] }:$soffset), (timm:{ *:[i32] }):$offset, (timm:{ *:[i32] }):$auxiliary, 0:{ *:[i1] })<<P:Predicate_anonymous_32267>>  =>  (BUFFER_LOAD_FORMAT_D16_XYZ_OFFSET:{ *:[v4i16] } SReg_128:{ *:[v4i32] }:$rsrc, SCSrc_b32:{ *:[i32] }:$soffset, (timm:{ *:[i32] }):$offset, (extract_cpol:{ *:[i32] } ?:{ *:[i32] }:$auxiliary), (extract_swz:{ *:[i1] } ?:{ *:[i32] }:$auxiliary))
        GIR_BuildMI, /*InsnID*/0, /*Opcode*/GIMT_Encode2(AMDGPU::BUFFER_LOAD_FORMAT_D16_XYZ_OFFSET),
        GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/0, // DstI[vdata]
        GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/1, // rsrc
        GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/0, // soffset
        GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/5, // offset
        GIR_CustomOperandRenderer, /*InsnID*/0, /*OldInsnID*/0, /*OpIdx*/6, /*OperandRenderer*/GIMT_Encode2(GICR_renderExtractCPol), // auxiliary
        GIR_CustomOperandRenderer, /*InsnID*/0, /*OldInsnID*/0, /*OpIdx*/6, /*OperandRenderer*/GIMT_Encode2(GICR_renderExtractSWZ), // auxiliary
        GIR_MergeMemOperands, /*InsnID*/0, /*NumInsns*/1, /*MergeInsnID's*/0,
        GIR_ConstrainSelectedInstOperands, /*InsnID*/0,
        GIR_EraseFromParent, /*InsnID*/0,
        // GIR_Coverage, 4081,
        GIR_Done,
      // Label 6649: @488495
      GIM_Try, /*On fail goto*//*Label 6650*/ GIMT_Encode4(488589), // Rule ID 4085 //
        GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasPackedD16VMem),
        GIM_CheckMemorySizeEqualTo, /*MI*/0, /*MMO*/0, /*Size*/GIMT_Encode4(6),
        GIM_CheckRegBankForClass, /*MI*/0, /*Op*/0, /*RC*/GIMT_Encode2(AMDGPU::AV_64RegClassID),
        GIM_CheckConstantInt8, /*MI*/0, /*Op*/2, 0,
        GIM_CheckConstantInt8, /*MI*/0, /*Op*/3, 0,
        // MIs[0] offset
        GIM_CheckIsImm, /*MI*/0, /*Op*/5,
        // MIs[0] auxiliary
        GIM_CheckIsImm, /*MI*/0, /*Op*/6,
        // MIs[0] Operand 7
        GIM_CheckLiteralInt, /*MI*/0, /*Op*/7, GIMT_Encode8(0),
        GIM_CheckComplexPattern, /*MI*/0, /*Op*/4, /*Renderer*/GIMT_Encode2(0), GIMT_Encode2(GICP_gi_buf_soffset),
        // (SIbuffer_load_format_d16:{ *:[v4i16] } v4i32:{ *:[v4i32] }:$rsrc, 0:{ *:[i32] }, 0:{ *:[i32] }, (BUFSOffset:{ *:[i32] } i32:{ *:[i32] }:$soffset), (timm:{ *:[i32] }):$offset, (timm:{ *:[i32] }):$auxiliary, 0:{ *:[i1] })<<P:Predicate_anonymous_32267>>  =>  (BUFFER_LOAD_FORMAT_D16_XYZ_VBUFFER_OFFSET:{ *:[v4i16] } SReg_128:{ *:[v4i32] }:$rsrc, SCSrc_b32:{ *:[i32] }:$soffset, (timm:{ *:[i32] }):$offset, (extract_cpol:{ *:[i32] } ?:{ *:[i32] }:$auxiliary), (extract_swz:{ *:[i1] } ?:{ *:[i32] }:$auxiliary))
        GIR_BuildMI, /*InsnID*/0, /*Opcode*/GIMT_Encode2(AMDGPU::BUFFER_LOAD_FORMAT_D16_XYZ_VBUFFER_OFFSET),
        GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/0, // DstI[vdata]
        GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/1, // rsrc
        GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/0, // soffset
        GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/5, // offset
        GIR_CustomOperandRenderer, /*InsnID*/0, /*OldInsnID*/0, /*OpIdx*/6, /*OperandRenderer*/GIMT_Encode2(GICR_renderExtractCPol), // auxiliary
        GIR_CustomOperandRenderer, /*InsnID*/0, /*OldInsnID*/0, /*OpIdx*/6, /*OperandRenderer*/GIMT_Encode2(GICR_renderExtractSWZ), // auxiliary
        GIR_MergeMemOperands, /*InsnID*/0, /*NumInsns*/1, /*MergeInsnID's*/0,
        GIR_ConstrainSelectedInstOperands, /*InsnID*/0,
        GIR_EraseFromParent, /*InsnID*/0,
        // GIR_Coverage, 4085,
        GIR_Done,
      // Label 6650: @488589
      GIM_Try, /*On fail goto*//*Label 6651*/ GIMT_Encode4(488676), // Rule ID 4089 //
        GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasPackedD16VMem_HasUnrestrictedSOffset),
        GIM_CheckRegBankForClass, /*MI*/0, /*Op*/0, /*RC*/GIMT_Encode2(AMDGPU::AV_64RegClassID),
        GIM_CheckConstantInt8, /*MI*/0, /*Op*/2, 0,
        GIM_CheckConstantInt8, /*MI*/0, /*Op*/3, 0,
        // MIs[0] offset
        GIM_CheckIsImm, /*MI*/0, /*Op*/5,
        // MIs[0] auxiliary
        GIM_CheckIsImm, /*MI*/0, /*Op*/6,
        // MIs[0] Operand 7
        GIM_CheckLiteralInt, /*MI*/0, /*Op*/7, GIMT_Encode8(0),
        GIM_CheckComplexPattern, /*MI*/0, /*Op*/4, /*Renderer*/GIMT_Encode2(0), GIMT_Encode2(GICP_gi_buf_soffset),
        // (SIbuffer_load_format_d16:{ *:[v4f16] } v4i32:{ *:[v4i32] }:$rsrc, 0:{ *:[i32] }, 0:{ *:[i32] }, (BUFSOffset:{ *:[i32] } i32:{ *:[i32] }:$soffset), (timm:{ *:[i32] }):$offset, (timm:{ *:[i32] }):$auxiliary, 0:{ *:[i1] })  =>  (BUFFER_LOAD_FORMAT_D16_XYZW_OFFSET:{ *:[v4f16] } SReg_128:{ *:[v4i32] }:$rsrc, SCSrc_b32:{ *:[i32] }:$soffset, (timm:{ *:[i32] }):$offset, (extract_cpol:{ *:[i32] } ?:{ *:[i32] }:$auxiliary), (extract_swz:{ *:[i1] } ?:{ *:[i32] }:$auxiliary))
        GIR_BuildMI, /*InsnID*/0, /*Opcode*/GIMT_Encode2(AMDGPU::BUFFER_LOAD_FORMAT_D16_XYZW_OFFSET),
        GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/0, // DstI[vdata]
        GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/1, // rsrc
        GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/0, // soffset
        GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/5, // offset
        GIR_CustomOperandRenderer, /*InsnID*/0, /*OldInsnID*/0, /*OpIdx*/6, /*OperandRenderer*/GIMT_Encode2(GICR_renderExtractCPol), // auxiliary
        GIR_CustomOperandRenderer, /*InsnID*/0, /*OldInsnID*/0, /*OpIdx*/6, /*OperandRenderer*/GIMT_Encode2(GICR_renderExtractSWZ), // auxiliary
        GIR_MergeMemOperands, /*InsnID*/0, /*NumInsns*/1, /*MergeInsnID's*/0,
        GIR_ConstrainSelectedInstOperands, /*InsnID*/0,
        GIR_EraseFromParent, /*InsnID*/0,
        // GIR_Coverage, 4089,
        GIR_Done,
      // Label 6651: @488676
      GIM_Try, /*On fail goto*//*Label 6652*/ GIMT_Encode4(488763), // Rule ID 4093 //
        GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasPackedD16VMem),
        GIM_CheckRegBankForClass, /*MI*/0, /*Op*/0, /*RC*/GIMT_Encode2(AMDGPU::AV_64RegClassID),
        GIM_CheckConstantInt8, /*MI*/0, /*Op*/2, 0,
        GIM_CheckConstantInt8, /*MI*/0, /*Op*/3, 0,
        // MIs[0] offset
        GIM_CheckIsImm, /*MI*/0, /*Op*/5,
        // MIs[0] auxiliary
        GIM_CheckIsImm, /*MI*/0, /*Op*/6,
        // MIs[0] Operand 7
        GIM_CheckLiteralInt, /*MI*/0, /*Op*/7, GIMT_Encode8(0),
        GIM_CheckComplexPattern, /*MI*/0, /*Op*/4, /*Renderer*/GIMT_Encode2(0), GIMT_Encode2(GICP_gi_buf_soffset),
        // (SIbuffer_load_format_d16:{ *:[v4f16] } v4i32:{ *:[v4i32] }:$rsrc, 0:{ *:[i32] }, 0:{ *:[i32] }, (BUFSOffset:{ *:[i32] } i32:{ *:[i32] }:$soffset), (timm:{ *:[i32] }):$offset, (timm:{ *:[i32] }):$auxiliary, 0:{ *:[i1] })  =>  (BUFFER_LOAD_FORMAT_D16_XYZW_VBUFFER_OFFSET:{ *:[v4f16] } SReg_128:{ *:[v4i32] }:$rsrc, SCSrc_b32:{ *:[i32] }:$soffset, (timm:{ *:[i32] }):$offset, (extract_cpol:{ *:[i32] } ?:{ *:[i32] }:$auxiliary), (extract_swz:{ *:[i1] } ?:{ *:[i32] }:$auxiliary))
        GIR_BuildMI, /*InsnID*/0, /*Opcode*/GIMT_Encode2(AMDGPU::BUFFER_LOAD_FORMAT_D16_XYZW_VBUFFER_OFFSET),
        GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/0, // DstI[vdata]
        GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/1, // rsrc
        GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/0, // soffset
        GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/5, // offset
        GIR_CustomOperandRenderer, /*InsnID*/0, /*OldInsnID*/0, /*OpIdx*/6, /*OperandRenderer*/GIMT_Encode2(GICR_renderExtractCPol), // auxiliary
        GIR_CustomOperandRenderer, /*InsnID*/0, /*OldInsnID*/0, /*OpIdx*/6, /*OperandRenderer*/GIMT_Encode2(GICR_renderExtractSWZ), // auxiliary
        GIR_MergeMemOperands, /*InsnID*/0, /*NumInsns*/1, /*MergeInsnID's*/0,
        GIR_ConstrainSelectedInstOperands, /*InsnID*/0,
        GIR_EraseFromParent, /*InsnID*/0,
        // GIR_Coverage, 4093,
        GIR_Done,
      // Label 6652: @488763
      GIM_Try, /*On fail goto*//*Label 6653*/ GIMT_Encode4(488850), // Rule ID 4097 //
        GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasPackedD16VMem_HasUnrestrictedSOffset),
        GIM_CheckRegBankForClass, /*MI*/0, /*Op*/0, /*RC*/GIMT_Encode2(AMDGPU::AV_64RegClassID),
        GIM_CheckConstantInt8, /*MI*/0, /*Op*/2, 0,
        GIM_CheckConstantInt8, /*MI*/0, /*Op*/3, 0,
        // MIs[0] offset
        GIM_CheckIsImm, /*MI*/0, /*Op*/5,
        // MIs[0] auxiliary
        GIM_CheckIsImm, /*MI*/0, /*Op*/6,
        // MIs[0] Operand 7
        GIM_CheckLiteralInt, /*MI*/0, /*Op*/7, GIMT_Encode8(0),
        GIM_CheckComplexPattern, /*MI*/0, /*Op*/4, /*Renderer*/GIMT_Encode2(0), GIMT_Encode2(GICP_gi_buf_soffset),
        // (SIbuffer_load_format_d16:{ *:[v4i16] } v4i32:{ *:[v4i32] }:$rsrc, 0:{ *:[i32] }, 0:{ *:[i32] }, (BUFSOffset:{ *:[i32] } i32:{ *:[i32] }:$soffset), (timm:{ *:[i32] }):$offset, (timm:{ *:[i32] }):$auxiliary, 0:{ *:[i1] })  =>  (BUFFER_LOAD_FORMAT_D16_XYZW_OFFSET:{ *:[v4i16] } SReg_128:{ *:[v4i32] }:$rsrc, SCSrc_b32:{ *:[i32] }:$soffset, (timm:{ *:[i32] }):$offset, (extract_cpol:{ *:[i32] } ?:{ *:[i32] }:$auxiliary), (extract_swz:{ *:[i1] } ?:{ *:[i32] }:$auxiliary))
        GIR_BuildMI, /*InsnID*/0, /*Opcode*/GIMT_Encode2(AMDGPU::BUFFER_LOAD_FORMAT_D16_XYZW_OFFSET),
        GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/0, // DstI[vdata]
        GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/1, // rsrc
        GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/0, // soffset
        GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/5, // offset
        GIR_CustomOperandRenderer, /*InsnID*/0, /*OldInsnID*/0, /*OpIdx*/6, /*OperandRenderer*/GIMT_Encode2(GICR_renderExtractCPol), // auxiliary
        GIR_CustomOperandRenderer, /*InsnID*/0, /*OldInsnID*/0, /*OpIdx*/6, /*OperandRenderer*/GIMT_Encode2(GICR_renderExtractSWZ), // auxiliary
        GIR_MergeMemOperands, /*InsnID*/0, /*NumInsns*/1, /*MergeInsnID's*/0,
        GIR_ConstrainSelectedInstOperands, /*InsnID*/0,
        GIR_EraseFromParent, /*InsnID*/0,
        // GIR_Coverage, 4097,
        GIR_Done,
      // Label 6653: @488850
      GIM_Try, /*On fail goto*//*Label 6654*/ GIMT_Encode4(488937), // Rule ID 4101 //
        GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasPackedD16VMem),
        GIM_CheckRegBankForClass, /*MI*/0, /*Op*/0, /*RC*/GIMT_Encode2(AMDGPU::AV_64RegClassID),
        GIM_CheckConstantInt8, /*MI*/0, /*Op*/2, 0,
        GIM_CheckConstantInt8, /*MI*/0, /*Op*/3, 0,
        // MIs[0] offset
        GIM_CheckIsImm, /*MI*/0, /*Op*/5,
        // MIs[0] auxiliary
        GIM_CheckIsImm, /*MI*/0, /*Op*/6,
        // MIs[0] Operand 7
        GIM_CheckLiteralInt, /*MI*/0, /*Op*/7, GIMT_Encode8(0),
        GIM_CheckComplexPattern, /*MI*/0, /*Op*/4, /*Renderer*/GIMT_Encode2(0), GIMT_Encode2(GICP_gi_buf_soffset),
        // (SIbuffer_load_format_d16:{ *:[v4i16] } v4i32:{ *:[v4i32] }:$rsrc, 0:{ *:[i32] }, 0:{ *:[i32] }, (BUFSOffset:{ *:[i32] } i32:{ *:[i32] }:$soffset), (timm:{ *:[i32] }):$offset, (timm:{ *:[i32] }):$auxiliary, 0:{ *:[i1] })  =>  (BUFFER_LOAD_FORMAT_D16_XYZW_VBUFFER_OFFSET:{ *:[v4i16] } SReg_128:{ *:[v4i32] }:$rsrc, SCSrc_b32:{ *:[i32] }:$soffset, (timm:{ *:[i32] }):$offset, (extract_cpol:{ *:[i32] } ?:{ *:[i32] }:$auxiliary), (extract_swz:{ *:[i1] } ?:{ *:[i32] }:$auxiliary))
        GIR_BuildMI, /*InsnID*/0, /*Opcode*/GIMT_Encode2(AMDGPU::BUFFER_LOAD_FORMAT_D16_XYZW_VBUFFER_OFFSET),
        GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/0, // DstI[vdata]
        GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/1, // rsrc
        GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/0, // soffset
        GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/5, // offset
        GIR_CustomOperandRenderer, /*InsnID*/0, /*OldInsnID*/0, /*OpIdx*/6, /*OperandRenderer*/GIMT_Encode2(GICR_renderExtractCPol), // auxiliary
        GIR_CustomOperandRenderer, /*InsnID*/0, /*OldInsnID*/0, /*OpIdx*/6, /*OperandRenderer*/GIMT_Encode2(GICR_renderExtractSWZ), // auxiliary
        GIR_MergeMemOperands, /*InsnID*/0, /*NumInsns*/1, /*MergeInsnID's*/0,
        GIR_ConstrainSelectedInstOperands, /*InsnID*/0,
        GIR_EraseFromParent, /*InsnID*/0,
        // GIR_Coverage, 4101,
        GIR_Done,
      // Label 6654: @488937
      GIM_Try, /*On fail goto*//*Label 6655*/ GIMT_Encode4(489031), // Rule ID 4074 //
        GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasPackedD16VMem_HasUnrestrictedSOffset),
        GIM_CheckMemorySizeEqualTo, /*MI*/0, /*MMO*/0, /*Size*/GIMT_Encode4(6),
        GIM_CheckRegBankForClass, /*MI*/0, /*Op*/0, /*RC*/GIMT_Encode2(AMDGPU::AV_64RegClassID),
        GIM_CheckConstantInt8, /*MI*/0, /*Op*/2, 0,
        // MIs[0] offset
        GIM_CheckIsImm, /*MI*/0, /*Op*/5,
        // MIs[0] auxiliary
        GIM_CheckIsImm, /*MI*/0, /*Op*/6,
        // MIs[0] Operand 7
        GIM_CheckLiteralInt, /*MI*/0, /*Op*/7, GIMT_Encode8(0),
        GIM_CheckComplexPattern, /*MI*/0, /*Op*/4, /*Renderer*/GIMT_Encode2(0), GIMT_Encode2(GICP_gi_buf_soffset),
        // (SIbuffer_load_format_d16:{ *:[v4f16] } v4i32:{ *:[v4i32] }:$rsrc, 0:{ *:[i32] }, i32:{ *:[i32] }:$voffset, (BUFSOffset:{ *:[i32] } i32:{ *:[i32] }:$soffset), (timm:{ *:[i32] }):$offset, (timm:{ *:[i32] }):$auxiliary, 0:{ *:[i1] })<<P:Predicate_anonymous_32257>>  =>  (BUFFER_LOAD_FORMAT_D16_XYZ_OFFEN:{ *:[v4f16] } VGPR_32:{ *:[i32] }:$voffset, SReg_128:{ *:[v4i32] }:$rsrc, SCSrc_b32:{ *:[i32] }:$soffset, (timm:{ *:[i32] }):$offset, (extract_cpol:{ *:[i32] } ?:{ *:[i32] }:$auxiliary), (extract_swz:{ *:[i1] } ?:{ *:[i32] }:$auxiliary))
        GIR_BuildMI, /*InsnID*/0, /*Opcode*/GIMT_Encode2(AMDGPU::BUFFER_LOAD_FORMAT_D16_XYZ_OFFEN),
        GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/0, // DstI[vdata]
        GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/3, // voffset
        GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/1, // rsrc
        GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/0, // soffset
        GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/5, // offset
        GIR_CustomOperandRenderer, /*InsnID*/0, /*OldInsnID*/0, /*OpIdx*/6, /*OperandRenderer*/GIMT_Encode2(GICR_renderExtractCPol), // auxiliary
        GIR_CustomOperandRenderer, /*InsnID*/0, /*OldInsnID*/0, /*OpIdx*/6, /*OperandRenderer*/GIMT_Encode2(GICR_renderExtractSWZ), // auxiliary
        GIR_MergeMemOperands, /*InsnID*/0, /*NumInsns*/1, /*MergeInsnID's*/0,
        GIR_ConstrainSelectedInstOperands, /*InsnID*/0,
        GIR_EraseFromParent, /*InsnID*/0,
        // GIR_Coverage, 4074,
        GIR_Done,
      // Label 6655: @489031
      GIM_Try, /*On fail goto*//*Label 6656*/ GIMT_Encode4(489125), // Rule ID 4078 //
        GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasPackedD16VMem),
        GIM_CheckMemorySizeEqualTo, /*MI*/0, /*MMO*/0, /*Size*/GIMT_Encode4(6),
        GIM_CheckRegBankForClass, /*MI*/0, /*Op*/0, /*RC*/GIMT_Encode2(AMDGPU::AV_64RegClassID),
        GIM_CheckConstantInt8, /*MI*/0, /*Op*/2, 0,
        // MIs[0] offset
        GIM_CheckIsImm, /*MI*/0, /*Op*/5,
        // MIs[0] auxiliary
        GIM_CheckIsImm, /*MI*/0, /*Op*/6,
        // MIs[0] Operand 7
        GIM_CheckLiteralInt, /*MI*/0, /*Op*/7, GIMT_Encode8(0),
        GIM_CheckComplexPattern, /*MI*/0, /*Op*/4, /*Renderer*/GIMT_Encode2(0), GIMT_Encode2(GICP_gi_buf_soffset),
        // (SIbuffer_load_format_d16:{ *:[v4f16] } v4i32:{ *:[v4i32] }:$rsrc, 0:{ *:[i32] }, i32:{ *:[i32] }:$voffset, (BUFSOffset:{ *:[i32] } i32:{ *:[i32] }:$soffset), (timm:{ *:[i32] }):$offset, (timm:{ *:[i32] }):$auxiliary, 0:{ *:[i1] })<<P:Predicate_anonymous_32257>>  =>  (BUFFER_LOAD_FORMAT_D16_XYZ_VBUFFER_OFFEN:{ *:[v4f16] } VGPR_32:{ *:[i32] }:$voffset, SReg_128:{ *:[v4i32] }:$rsrc, SCSrc_b32:{ *:[i32] }:$soffset, (timm:{ *:[i32] }):$offset, (extract_cpol:{ *:[i32] } ?:{ *:[i32] }:$auxiliary), (extract_swz:{ *:[i1] } ?:{ *:[i32] }:$auxiliary))
        GIR_BuildMI, /*InsnID*/0, /*Opcode*/GIMT_Encode2(AMDGPU::BUFFER_LOAD_FORMAT_D16_XYZ_VBUFFER_OFFEN),
        GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/0, // DstI[vdata]
        GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/3, // voffset
        GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/1, // rsrc
        GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/0, // soffset
        GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/5, // offset
        GIR_CustomOperandRenderer, /*InsnID*/0, /*OldInsnID*/0, /*OpIdx*/6, /*OperandRenderer*/GIMT_Encode2(GICR_renderExtractCPol), // auxiliary
        GIR_CustomOperandRenderer, /*InsnID*/0, /*OldInsnID*/0, /*OpIdx*/6, /*OperandRenderer*/GIMT_Encode2(GICR_renderExtractSWZ), // auxiliary
        GIR_MergeMemOperands, /*InsnID*/0, /*NumInsns*/1, /*MergeInsnID's*/0,
        GIR_ConstrainSelectedInstOperands, /*InsnID*/0,
        GIR_EraseFromParent, /*InsnID*/0,
        // GIR_Coverage, 4078,
        GIR_Done,
      // Label 6656: @489125
      GIM_Try, /*On fail goto*//*Label 6657*/ GIMT_Encode4(489219), // Rule ID 4082 //
        GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasPackedD16VMem_HasUnrestrictedSOffset),
        GIM_CheckMemorySizeEqualTo, /*MI*/0, /*MMO*/0, /*Size*/GIMT_Encode4(6),
        GIM_CheckRegBankForClass, /*MI*/0, /*Op*/0, /*RC*/GIMT_Encode2(AMDGPU::AV_64RegClassID),
        GIM_CheckConstantInt8, /*MI*/0, /*Op*/2, 0,
        // MIs[0] offset
        GIM_CheckIsImm, /*MI*/0, /*Op*/5,
        // MIs[0] auxiliary
        GIM_CheckIsImm, /*MI*/0, /*Op*/6,
        // MIs[0] Operand 7
        GIM_CheckLiteralInt, /*MI*/0, /*Op*/7, GIMT_Encode8(0),
        GIM_CheckComplexPattern, /*MI*/0, /*Op*/4, /*Renderer*/GIMT_Encode2(0), GIMT_Encode2(GICP_gi_buf_soffset),
        // (SIbuffer_load_format_d16:{ *:[v4i16] } v4i32:{ *:[v4i32] }:$rsrc, 0:{ *:[i32] }, i32:{ *:[i32] }:$voffset, (BUFSOffset:{ *:[i32] } i32:{ *:[i32] }:$soffset), (timm:{ *:[i32] }):$offset, (timm:{ *:[i32] }):$auxiliary, 0:{ *:[i1] })<<P:Predicate_anonymous_32267>>  =>  (BUFFER_LOAD_FORMAT_D16_XYZ_OFFEN:{ *:[v4i16] } VGPR_32:{ *:[i32] }:$voffset, SReg_128:{ *:[v4i32] }:$rsrc, SCSrc_b32:{ *:[i32] }:$soffset, (timm:{ *:[i32] }):$offset, (extract_cpol:{ *:[i32] } ?:{ *:[i32] }:$auxiliary), (extract_swz:{ *:[i1] } ?:{ *:[i32] }:$auxiliary))
        GIR_BuildMI, /*InsnID*/0, /*Opcode*/GIMT_Encode2(AMDGPU::BUFFER_LOAD_FORMAT_D16_XYZ_OFFEN),
        GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/0, // DstI[vdata]
        GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/3, // voffset
        GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/1, // rsrc
        GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/0, // soffset
        GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/5, // offset
        GIR_CustomOperandRenderer, /*InsnID*/0, /*OldInsnID*/0, /*OpIdx*/6, /*OperandRenderer*/GIMT_Encode2(GICR_renderExtractCPol), // auxiliary
        GIR_CustomOperandRenderer, /*InsnID*/0, /*OldInsnID*/0, /*OpIdx*/6, /*OperandRenderer*/GIMT_Encode2(GICR_renderExtractSWZ), // auxiliary
        GIR_MergeMemOperands, /*InsnID*/0, /*NumInsns*/1, /*MergeInsnID's*/0,
        GIR_ConstrainSelectedInstOperands, /*InsnID*/0,
        GIR_EraseFromParent, /*InsnID*/0,
        // GIR_Coverage, 4082,
        GIR_Done,
      // Label 6657: @489219
      GIM_Try, /*On fail goto*//*Label 6658*/ GIMT_Encode4(489313), // Rule ID 4086 //
        GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasPackedD16VMem),
        GIM_CheckMemorySizeEqualTo, /*MI*/0, /*MMO*/0, /*Size*/GIMT_Encode4(6),
        GIM_CheckRegBankForClass, /*MI*/0, /*Op*/0, /*RC*/GIMT_Encode2(AMDGPU::AV_64RegClassID),
        GIM_CheckConstantInt8, /*MI*/0, /*Op*/2, 0,
        // MIs[0] offset
        GIM_CheckIsImm, /*MI*/0, /*Op*/5,
        // MIs[0] auxiliary
        GIM_CheckIsImm, /*MI*/0, /*Op*/6,
        // MIs[0] Operand 7
        GIM_CheckLiteralInt, /*MI*/0, /*Op*/7, GIMT_Encode8(0),
        GIM_CheckComplexPattern, /*MI*/0, /*Op*/4, /*Renderer*/GIMT_Encode2(0), GIMT_Encode2(GICP_gi_buf_soffset),
        // (SIbuffer_load_format_d16:{ *:[v4i16] } v4i32:{ *:[v4i32] }:$rsrc, 0:{ *:[i32] }, i32:{ *:[i32] }:$voffset, (BUFSOffset:{ *:[i32] } i32:{ *:[i32] }:$soffset), (timm:{ *:[i32] }):$offset, (timm:{ *:[i32] }):$auxiliary, 0:{ *:[i1] })<<P:Predicate_anonymous_32267>>  =>  (BUFFER_LOAD_FORMAT_D16_XYZ_VBUFFER_OFFEN:{ *:[v4i16] } VGPR_32:{ *:[i32] }:$voffset, SReg_128:{ *:[v4i32] }:$rsrc, SCSrc_b32:{ *:[i32] }:$soffset, (timm:{ *:[i32] }):$offset, (extract_cpol:{ *:[i32] } ?:{ *:[i32] }:$auxiliary), (extract_swz:{ *:[i1] } ?:{ *:[i32] }:$auxiliary))
        GIR_BuildMI, /*InsnID*/0, /*Opcode*/GIMT_Encode2(AMDGPU::BUFFER_LOAD_FORMAT_D16_XYZ_VBUFFER_OFFEN),
        GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/0, // DstI[vdata]
        GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/3, // voffset
        GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/1, // rsrc
        GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/0, // soffset
        GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/5, // offset
        GIR_CustomOperandRenderer, /*InsnID*/0, /*OldInsnID*/0, /*OpIdx*/6, /*OperandRenderer*/GIMT_Encode2(GICR_renderExtractCPol), // auxiliary
        GIR_CustomOperandRenderer, /*InsnID*/0, /*OldInsnID*/0, /*OpIdx*/6, /*OperandRenderer*/GIMT_Encode2(GICR_renderExtractSWZ), // auxiliary
        GIR_MergeMemOperands, /*InsnID*/0, /*NumInsns*/1, /*MergeInsnID's*/0,
        GIR_ConstrainSelectedInstOperands, /*InsnID*/0,
        GIR_EraseFromParent, /*InsnID*/0,
        // GIR_Coverage, 4086,
        GIR_Done,
      // Label 6658: @489313
      GIM_Try, /*On fail goto*//*Label 6659*/ GIMT_Encode4(489400), // Rule ID 4090 //
        GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasPackedD16VMem_HasUnrestrictedSOffset),
        GIM_CheckRegBankForClass, /*MI*/0, /*Op*/0, /*RC*/GIMT_Encode2(AMDGPU::AV_64RegClassID),
        GIM_CheckConstantInt8, /*MI*/0, /*Op*/2, 0,
        // MIs[0] offset
        GIM_CheckIsImm, /*MI*/0, /*Op*/5,
        // MIs[0] auxiliary
        GIM_CheckIsImm, /*MI*/0, /*Op*/6,
        // MIs[0] Operand 7
        GIM_CheckLiteralInt, /*MI*/0, /*Op*/7, GIMT_Encode8(0),
        GIM_CheckComplexPattern, /*MI*/0, /*Op*/4, /*Renderer*/GIMT_Encode2(0), GIMT_Encode2(GICP_gi_buf_soffset),
        // (SIbuffer_load_format_d16:{ *:[v4f16] } v4i32:{ *:[v4i32] }:$rsrc, 0:{ *:[i32] }, i32:{ *:[i32] }:$voffset, (BUFSOffset:{ *:[i32] } i32:{ *:[i32] }:$soffset), (timm:{ *:[i32] }):$offset, (timm:{ *:[i32] }):$auxiliary, 0:{ *:[i1] })  =>  (BUFFER_LOAD_FORMAT_D16_XYZW_OFFEN:{ *:[v4f16] } VGPR_32:{ *:[i32] }:$voffset, SReg_128:{ *:[v4i32] }:$rsrc, SCSrc_b32:{ *:[i32] }:$soffset, (timm:{ *:[i32] }):$offset, (extract_cpol:{ *:[i32] } ?:{ *:[i32] }:$auxiliary), (extract_swz:{ *:[i1] } ?:{ *:[i32] }:$auxiliary))
        GIR_BuildMI, /*InsnID*/0, /*Opcode*/GIMT_Encode2(AMDGPU::BUFFER_LOAD_FORMAT_D16_XYZW_OFFEN),
        GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/0, // DstI[vdata]
        GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/3, // voffset
        GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/1, // rsrc
        GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/0, // soffset
        GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/5, // offset
        GIR_CustomOperandRenderer, /*InsnID*/0, /*OldInsnID*/0, /*OpIdx*/6, /*OperandRenderer*/GIMT_Encode2(GICR_renderExtractCPol), // auxiliary
        GIR_CustomOperandRenderer, /*InsnID*/0, /*OldInsnID*/0, /*OpIdx*/6, /*OperandRenderer*/GIMT_Encode2(GICR_renderExtractSWZ), // auxiliary
        GIR_MergeMemOperands, /*InsnID*/0, /*NumInsns*/1, /*MergeInsnID's*/0,
        GIR_ConstrainSelectedInstOperands, /*InsnID*/0,
        GIR_EraseFromParent, /*InsnID*/0,
        // GIR_Coverage, 4090,
        GIR_Done,
      // Label 6659: @489400
      GIM_Try, /*On fail goto*//*Label 6660*/ GIMT_Encode4(489487), // Rule ID 4094 //
        GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasPackedD16VMem),
        GIM_CheckRegBankForClass, /*MI*/0, /*Op*/0, /*RC*/GIMT_Encode2(AMDGPU::AV_64RegClassID),
        GIM_CheckConstantInt8, /*MI*/0, /*Op*/2, 0,
        // MIs[0] offset
        GIM_CheckIsImm, /*MI*/0, /*Op*/5,
        // MIs[0] auxiliary
        GIM_CheckIsImm, /*MI*/0, /*Op*/6,
        // MIs[0] Operand 7
        GIM_CheckLiteralInt, /*MI*/0, /*Op*/7, GIMT_Encode8(0),
        GIM_CheckComplexPattern, /*MI*/0, /*Op*/4, /*Renderer*/GIMT_Encode2(0), GIMT_Encode2(GICP_gi_buf_soffset),
        // (SIbuffer_load_format_d16:{ *:[v4f16] } v4i32:{ *:[v4i32] }:$rsrc, 0:{ *:[i32] }, i32:{ *:[i32] }:$voffset, (BUFSOffset:{ *:[i32] } i32:{ *:[i32] }:$soffset), (timm:{ *:[i32] }):$offset, (timm:{ *:[i32] }):$auxiliary, 0:{ *:[i1] })  =>  (BUFFER_LOAD_FORMAT_D16_XYZW_VBUFFER_OFFEN:{ *:[v4f16] } VGPR_32:{ *:[i32] }:$voffset, SReg_128:{ *:[v4i32] }:$rsrc, SCSrc_b32:{ *:[i32] }:$soffset, (timm:{ *:[i32] }):$offset, (extract_cpol:{ *:[i32] } ?:{ *:[i32] }:$auxiliary), (extract_swz:{ *:[i1] } ?:{ *:[i32] }:$auxiliary))
        GIR_BuildMI, /*InsnID*/0, /*Opcode*/GIMT_Encode2(AMDGPU::BUFFER_LOAD_FORMAT_D16_XYZW_VBUFFER_OFFEN),
        GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/0, // DstI[vdata]
        GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/3, // voffset
        GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/1, // rsrc
        GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/0, // soffset
        GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/5, // offset
        GIR_CustomOperandRenderer, /*InsnID*/0, /*OldInsnID*/0, /*OpIdx*/6, /*OperandRenderer*/GIMT_Encode2(GICR_renderExtractCPol), // auxiliary
        GIR_CustomOperandRenderer, /*InsnID*/0, /*OldInsnID*/0, /*OpIdx*/6, /*OperandRenderer*/GIMT_Encode2(GICR_renderExtractSWZ), // auxiliary
        GIR_MergeMemOperands, /*InsnID*/0, /*NumInsns*/1, /*MergeInsnID's*/0,
        GIR_ConstrainSelectedInstOperands, /*InsnID*/0,
        GIR_EraseFromParent, /*InsnID*/0,
        // GIR_Coverage, 4094,
        GIR_Done,
      // Label 6660: @489487
      GIM_Try, /*On fail goto*//*Label 6661*/ GIMT_Encode4(489574), // Rule ID 4098 //
        GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasPackedD16VMem_HasUnrestrictedSOffset),
        GIM_CheckRegBankForClass, /*MI*/0, /*Op*/0, /*RC*/GIMT_Encode2(AMDGPU::AV_64RegClassID),
        GIM_CheckConstantInt8, /*MI*/0, /*Op*/2, 0,
        // MIs[0] offset
        GIM_CheckIsImm, /*MI*/0, /*Op*/5,
        // MIs[0] auxiliary
        GIM_CheckIsImm, /*MI*/0, /*Op*/6,
        // MIs[0] Operand 7
        GIM_CheckLiteralInt, /*MI*/0, /*Op*/7, GIMT_Encode8(0),
        GIM_CheckComplexPattern, /*MI*/0, /*Op*/4, /*Renderer*/GIMT_Encode2(0), GIMT_Encode2(GICP_gi_buf_soffset),
        // (SIbuffer_load_format_d16:{ *:[v4i16] } v4i32:{ *:[v4i32] }:$rsrc, 0:{ *:[i32] }, i32:{ *:[i32] }:$voffset, (BUFSOffset:{ *:[i32] } i32:{ *:[i32] }:$soffset), (timm:{ *:[i32] }):$offset, (timm:{ *:[i32] }):$auxiliary, 0:{ *:[i1] })  =>  (BUFFER_LOAD_FORMAT_D16_XYZW_OFFEN:{ *:[v4i16] } VGPR_32:{ *:[i32] }:$voffset, SReg_128:{ *:[v4i32] }:$rsrc, SCSrc_b32:{ *:[i32] }:$soffset, (timm:{ *:[i32] }):$offset, (extract_cpol:{ *:[i32] } ?:{ *:[i32] }:$auxiliary), (extract_swz:{ *:[i1] } ?:{ *:[i32] }:$auxiliary))
        GIR_BuildMI, /*InsnID*/0, /*Opcode*/GIMT_Encode2(AMDGPU::BUFFER_LOAD_FORMAT_D16_XYZW_OFFEN),
        GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/0, // DstI[vdata]
        GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/3, // voffset
        GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/1, // rsrc
        GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/0, // soffset
        GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/5, // offset
        GIR_CustomOperandRenderer, /*InsnID*/0, /*OldInsnID*/0, /*OpIdx*/6, /*OperandRenderer*/GIMT_Encode2(GICR_renderExtractCPol), // auxiliary
        GIR_CustomOperandRenderer, /*InsnID*/0, /*OldInsnID*/0, /*OpIdx*/6, /*OperandRenderer*/GIMT_Encode2(GICR_renderExtractSWZ), // auxiliary
        GIR_MergeMemOperands, /*InsnID*/0, /*NumInsns*/1, /*MergeInsnID's*/0,
        GIR_ConstrainSelectedInstOperands, /*InsnID*/0,
        GIR_EraseFromParent, /*InsnID*/0,
        // GIR_Coverage, 4098,
        GIR_Done,
      // Label 6661: @489574
      GIM_Try, /*On fail goto*//*Label 6662*/ GIMT_Encode4(489661), // Rule ID 4102 //
        GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasPackedD16VMem),
        GIM_CheckRegBankForClass, /*MI*/0, /*Op*/0, /*RC*/GIMT_Encode2(AMDGPU::AV_64RegClassID),
        GIM_CheckConstantInt8, /*MI*/0, /*Op*/2, 0,
        // MIs[0] offset
        GIM_CheckIsImm, /*MI*/0, /*Op*/5,
        // MIs[0] auxiliary
        GIM_CheckIsImm, /*MI*/0, /*Op*/6,
        // MIs[0] Operand 7
        GIM_CheckLiteralInt, /*MI*/0, /*Op*/7, GIMT_Encode8(0),
        GIM_CheckComplexPattern, /*MI*/0, /*Op*/4, /*Renderer*/GIMT_Encode2(0), GIMT_Encode2(GICP_gi_buf_soffset),
        // (SIbuffer_load_format_d16:{ *:[v4i16] } v4i32:{ *:[v4i32] }:$rsrc, 0:{ *:[i32] }, i32:{ *:[i32] }:$voffset, (BUFSOffset:{ *:[i32] } i32:{ *:[i32] }:$soffset), (timm:{ *:[i32] }):$offset, (timm:{ *:[i32] }):$auxiliary, 0:{ *:[i1] })  =>  (BUFFER_LOAD_FORMAT_D16_XYZW_VBUFFER_OFFEN:{ *:[v4i16] } VGPR_32:{ *:[i32] }:$voffset, SReg_128:{ *:[v4i32] }:$rsrc, SCSrc_b32:{ *:[i32] }:$soffset, (timm:{ *:[i32] }):$offset, (extract_cpol:{ *:[i32] } ?:{ *:[i32] }:$auxiliary), (extract_swz:{ *:[i1] } ?:{ *:[i32] }:$auxiliary))
        GIR_BuildMI, /*InsnID*/0, /*Opcode*/GIMT_Encode2(AMDGPU::BUFFER_LOAD_FORMAT_D16_XYZW_VBUFFER_OFFEN),
        GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/0, // DstI[vdata]
        GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/3, // voffset
        GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/1, // rsrc
        GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/0, // soffset
        GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/5, // offset
        GIR_CustomOperandRenderer, /*InsnID*/0, /*OldInsnID*/0, /*OpIdx*/6, /*OperandRenderer*/GIMT_Encode2(GICR_renderExtractCPol), // auxiliary
        GIR_CustomOperandRenderer, /*InsnID*/0, /*OldInsnID*/0, /*OpIdx*/6, /*OperandRenderer*/GIMT_Encode2(GICR_renderExtractSWZ), // auxiliary
        GIR_MergeMemOperands, /*InsnID*/0, /*NumInsns*/1, /*MergeInsnID's*/0,
        GIR_ConstrainSelectedInstOperands, /*InsnID*/0,
        GIR_EraseFromParent, /*InsnID*/0,
        // GIR_Coverage, 4102,
        GIR_Done,
      // Label 6662: @489661
      GIM_Try, /*On fail goto*//*Label 6663*/ GIMT_Encode4(489747), // Rule ID 4075 //
        GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasPackedD16VMem_HasUnrestrictedSOffset),
        GIM_CheckMemorySizeEqualTo, /*MI*/0, /*MMO*/0, /*Size*/GIMT_Encode4(6),
        GIM_CheckRegBankForClass, /*MI*/0, /*Op*/0, /*RC*/GIMT_Encode2(AMDGPU::AV_64RegClassID),
        GIM_CheckConstantInt8, /*MI*/0, /*Op*/3, 0,
        // MIs[0] offset
        GIM_CheckIsImm, /*MI*/0, /*Op*/5,
        // MIs[0] auxiliary
        GIM_CheckIsImm, /*MI*/0, /*Op*/6,
        // MIs[0] Operand 7
        GIM_CheckIsImm, /*MI*/0, /*Op*/7,
        GIM_CheckComplexPattern, /*MI*/0, /*Op*/4, /*Renderer*/GIMT_Encode2(0), GIMT_Encode2(GICP_gi_buf_soffset),
        // (SIbuffer_load_format_d16:{ *:[v4f16] } v4i32:{ *:[v4i32] }:$rsrc, i32:{ *:[i32] }:$vindex, 0:{ *:[i32] }, (BUFSOffset:{ *:[i32] } i32:{ *:[i32] }:$soffset), (timm:{ *:[i32] }):$offset, (timm:{ *:[i32] }):$auxiliary, (timm:{ *:[i1] }))<<P:Predicate_anonymous_32257>>  =>  (BUFFER_LOAD_FORMAT_D16_XYZ_IDXEN:{ *:[v4f16] } VGPR_32:{ *:[i32] }:$vindex, SReg_128:{ *:[v4i32] }:$rsrc, SCSrc_b32:{ *:[i32] }:$soffset, (timm:{ *:[i32] }):$offset, (extract_cpol:{ *:[i32] } ?:{ *:[i32] }:$auxiliary), (extract_swz:{ *:[i1] } ?:{ *:[i32] }:$auxiliary))
        GIR_BuildMI, /*InsnID*/0, /*Opcode*/GIMT_Encode2(AMDGPU::BUFFER_LOAD_FORMAT_D16_XYZ_IDXEN),
        GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/0, // DstI[vdata]
        GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/2, // vindex
        GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/1, // rsrc
        GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/0, // soffset
        GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/5, // offset
        GIR_CustomOperandRenderer, /*InsnID*/0, /*OldInsnID*/0, /*OpIdx*/6, /*OperandRenderer*/GIMT_Encode2(GICR_renderExtractCPol), // auxiliary
        GIR_CustomOperandRenderer, /*InsnID*/0, /*OldInsnID*/0, /*OpIdx*/6, /*OperandRenderer*/GIMT_Encode2(GICR_renderExtractSWZ), // auxiliary
        GIR_MergeMemOperands, /*InsnID*/0, /*NumInsns*/1, /*MergeInsnID's*/0,
        GIR_ConstrainSelectedInstOperands, /*InsnID*/0,
        GIR_EraseFromParent, /*InsnID*/0,
        // GIR_Coverage, 4075,
        GIR_Done,
      // Label 6663: @489747
      GIM_Try, /*On fail goto*//*Label 6664*/ GIMT_Encode4(489833), // Rule ID 4079 //
        GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasPackedD16VMem),
        GIM_CheckMemorySizeEqualTo, /*MI*/0, /*MMO*/0, /*Size*/GIMT_Encode4(6),
        GIM_CheckRegBankForClass, /*MI*/0, /*Op*/0, /*RC*/GIMT_Encode2(AMDGPU::AV_64RegClassID),
        GIM_CheckConstantInt8, /*MI*/0, /*Op*/3, 0,
        // MIs[0] offset
        GIM_CheckIsImm, /*MI*/0, /*Op*/5,
        // MIs[0] auxiliary
        GIM_CheckIsImm, /*MI*/0, /*Op*/6,
        // MIs[0] Operand 7
        GIM_CheckIsImm, /*MI*/0, /*Op*/7,
        GIM_CheckComplexPattern, /*MI*/0, /*Op*/4, /*Renderer*/GIMT_Encode2(0), GIMT_Encode2(GICP_gi_buf_soffset),
        // (SIbuffer_load_format_d16:{ *:[v4f16] } v4i32:{ *:[v4i32] }:$rsrc, i32:{ *:[i32] }:$vindex, 0:{ *:[i32] }, (BUFSOffset:{ *:[i32] } i32:{ *:[i32] }:$soffset), (timm:{ *:[i32] }):$offset, (timm:{ *:[i32] }):$auxiliary, (timm:{ *:[i1] }))<<P:Predicate_anonymous_32257>>  =>  (BUFFER_LOAD_FORMAT_D16_XYZ_VBUFFER_IDXEN:{ *:[v4f16] } VGPR_32:{ *:[i32] }:$vindex, SReg_128:{ *:[v4i32] }:$rsrc, SCSrc_b32:{ *:[i32] }:$soffset, (timm:{ *:[i32] }):$offset, (extract_cpol:{ *:[i32] } ?:{ *:[i32] }:$auxiliary), (extract_swz:{ *:[i1] } ?:{ *:[i32] }:$auxiliary))
        GIR_BuildMI, /*InsnID*/0, /*Opcode*/GIMT_Encode2(AMDGPU::BUFFER_LOAD_FORMAT_D16_XYZ_VBUFFER_IDXEN),
        GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/0, // DstI[vdata]
        GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/2, // vindex
        GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/1, // rsrc
        GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/0, // soffset
        GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/5, // offset
        GIR_CustomOperandRenderer, /*InsnID*/0, /*OldInsnID*/0, /*OpIdx*/6, /*OperandRenderer*/GIMT_Encode2(GICR_renderExtractCPol), // auxiliary
        GIR_CustomOperandRenderer, /*InsnID*/0, /*OldInsnID*/0, /*OpIdx*/6, /*OperandRenderer*/GIMT_Encode2(GICR_renderExtractSWZ), // auxiliary
        GIR_MergeMemOperands, /*InsnID*/0, /*NumInsns*/1, /*MergeInsnID's*/0,
        GIR_ConstrainSelectedInstOperands, /*InsnID*/0,
        GIR_EraseFromParent, /*InsnID*/0,
        // GIR_Coverage, 4079,
        GIR_Done,
      // Label 6664: @489833
      GIM_Try, /*On fail goto*//*Label 6665*/ GIMT_Encode4(489919), // Rule ID 4083 //
        GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasPackedD16VMem_HasUnrestrictedSOffset),
        GIM_CheckMemorySizeEqualTo, /*MI*/0, /*MMO*/0, /*Size*/GIMT_Encode4(6),
        GIM_CheckRegBankForClass, /*MI*/0, /*Op*/0, /*RC*/GIMT_Encode2(AMDGPU::AV_64RegClassID),
        GIM_CheckConstantInt8, /*MI*/0, /*Op*/3, 0,
        // MIs[0] offset
        GIM_CheckIsImm, /*MI*/0, /*Op*/5,
        // MIs[0] auxiliary
        GIM_CheckIsImm, /*MI*/0, /*Op*/6,
        // MIs[0] Operand 7
        GIM_CheckIsImm, /*MI*/0, /*Op*/7,
        GIM_CheckComplexPattern, /*MI*/0, /*Op*/4, /*Renderer*/GIMT_Encode2(0), GIMT_Encode2(GICP_gi_buf_soffset),
        // (SIbuffer_load_format_d16:{ *:[v4i16] } v4i32:{ *:[v4i32] }:$rsrc, i32:{ *:[i32] }:$vindex, 0:{ *:[i32] }, (BUFSOffset:{ *:[i32] } i32:{ *:[i32] }:$soffset), (timm:{ *:[i32] }):$offset, (timm:{ *:[i32] }):$auxiliary, (timm:{ *:[i1] }))<<P:Predicate_anonymous_32267>>  =>  (BUFFER_LOAD_FORMAT_D16_XYZ_IDXEN:{ *:[v4i16] } VGPR_32:{ *:[i32] }:$vindex, SReg_128:{ *:[v4i32] }:$rsrc, SCSrc_b32:{ *:[i32] }:$soffset, (timm:{ *:[i32] }):$offset, (extract_cpol:{ *:[i32] } ?:{ *:[i32] }:$auxiliary), (extract_swz:{ *:[i1] } ?:{ *:[i32] }:$auxiliary))
        GIR_BuildMI, /*InsnID*/0, /*Opcode*/GIMT_Encode2(AMDGPU::BUFFER_LOAD_FORMAT_D16_XYZ_IDXEN),
        GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/0, // DstI[vdata]
        GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/2, // vindex
        GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/1, // rsrc
        GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/0, // soffset
        GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/5, // offset
        GIR_CustomOperandRenderer, /*InsnID*/0, /*OldInsnID*/0, /*OpIdx*/6, /*OperandRenderer*/GIMT_Encode2(GICR_renderExtractCPol), // auxiliary
        GIR_CustomOperandRenderer, /*InsnID*/0, /*OldInsnID*/0, /*OpIdx*/6, /*OperandRenderer*/GIMT_Encode2(GICR_renderExtractSWZ), // auxiliary
        GIR_MergeMemOperands, /*InsnID*/0, /*NumInsns*/1, /*MergeInsnID's*/0,
        GIR_ConstrainSelectedInstOperands, /*InsnID*/0,
        GIR_EraseFromParent, /*InsnID*/0,
        // GIR_Coverage, 4083,
        GIR_Done,
      // Label 6665: @489919
      GIM_Try, /*On fail goto*//*Label 6666*/ GIMT_Encode4(490005), // Rule ID 4087 //
        GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasPackedD16VMem),
        GIM_CheckMemorySizeEqualTo, /*MI*/0, /*MMO*/0, /*Size*/GIMT_Encode4(6),
        GIM_CheckRegBankForClass, /*MI*/0, /*Op*/0, /*RC*/GIMT_Encode2(AMDGPU::AV_64RegClassID),
        GIM_CheckConstantInt8, /*MI*/0, /*Op*/3, 0,
        // MIs[0] offset
        GIM_CheckIsImm, /*MI*/0, /*Op*/5,
        // MIs[0] auxiliary
        GIM_CheckIsImm, /*MI*/0, /*Op*/6,
        // MIs[0] Operand 7
        GIM_CheckIsImm, /*MI*/0, /*Op*/7,
        GIM_CheckComplexPattern, /*MI*/0, /*Op*/4, /*Renderer*/GIMT_Encode2(0), GIMT_Encode2(GICP_gi_buf_soffset),
        // (SIbuffer_load_format_d16:{ *:[v4i16] } v4i32:{ *:[v4i32] }:$rsrc, i32:{ *:[i32] }:$vindex, 0:{ *:[i32] }, (BUFSOffset:{ *:[i32] } i32:{ *:[i32] }:$soffset), (timm:{ *:[i32] }):$offset, (timm:{ *:[i32] }):$auxiliary, (timm:{ *:[i1] }))<<P:Predicate_anonymous_32267>>  =>  (BUFFER_LOAD_FORMAT_D16_XYZ_VBUFFER_IDXEN:{ *:[v4i16] } VGPR_32:{ *:[i32] }:$vindex, SReg_128:{ *:[v4i32] }:$rsrc, SCSrc_b32:{ *:[i32] }:$soffset, (timm:{ *:[i32] }):$offset, (extract_cpol:{ *:[i32] } ?:{ *:[i32] }:$auxiliary), (extract_swz:{ *:[i1] } ?:{ *:[i32] }:$auxiliary))
        GIR_BuildMI, /*InsnID*/0, /*Opcode*/GIMT_Encode2(AMDGPU::BUFFER_LOAD_FORMAT_D16_XYZ_VBUFFER_IDXEN),
        GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/0, // DstI[vdata]
        GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/2, // vindex
        GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/1, // rsrc
        GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/0, // soffset
        GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/5, // offset
        GIR_CustomOperandRenderer, /*InsnID*/0, /*OldInsnID*/0, /*OpIdx*/6, /*OperandRenderer*/GIMT_Encode2(GICR_renderExtractCPol), // auxiliary
        GIR_CustomOperandRenderer, /*InsnID*/0, /*OldInsnID*/0, /*OpIdx*/6, /*OperandRenderer*/GIMT_Encode2(GICR_renderExtractSWZ), // auxiliary
        GIR_MergeMemOperands, /*InsnID*/0, /*NumInsns*/1, /*MergeInsnID's*/0,
        GIR_ConstrainSelectedInstOperands, /*InsnID*/0,
        GIR_EraseFromParent, /*InsnID*/0,
        // GIR_Coverage, 4087,
        GIR_Done,
      // Label 6666: @490005
      GIM_Try, /*On fail goto*//*Label 6667*/ GIMT_Encode4(490084), // Rule ID 4091 //
        GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasPackedD16VMem_HasUnrestrictedSOffset),
        GIM_CheckRegBankForClass, /*MI*/0, /*Op*/0, /*RC*/GIMT_Encode2(AMDGPU::AV_64RegClassID),
        GIM_CheckConstantInt8, /*MI*/0, /*Op*/3, 0,
        // MIs[0] offset
        GIM_CheckIsImm, /*MI*/0, /*Op*/5,
        // MIs[0] auxiliary
        GIM_CheckIsImm, /*MI*/0, /*Op*/6,
        // MIs[0] Operand 7
        GIM_CheckIsImm, /*MI*/0, /*Op*/7,
        GIM_CheckComplexPattern, /*MI*/0, /*Op*/4, /*Renderer*/GIMT_Encode2(0), GIMT_Encode2(GICP_gi_buf_soffset),
        // (SIbuffer_load_format_d16:{ *:[v4f16] } v4i32:{ *:[v4i32] }:$rsrc, i32:{ *:[i32] }:$vindex, 0:{ *:[i32] }, (BUFSOffset:{ *:[i32] } i32:{ *:[i32] }:$soffset), (timm:{ *:[i32] }):$offset, (timm:{ *:[i32] }):$auxiliary, (timm:{ *:[i1] }))  =>  (BUFFER_LOAD_FORMAT_D16_XYZW_IDXEN:{ *:[v4f16] } VGPR_32:{ *:[i32] }:$vindex, SReg_128:{ *:[v4i32] }:$rsrc, SCSrc_b32:{ *:[i32] }:$soffset, (timm:{ *:[i32] }):$offset, (extract_cpol:{ *:[i32] } ?:{ *:[i32] }:$auxiliary), (extract_swz:{ *:[i1] } ?:{ *:[i32] }:$auxiliary))
        GIR_BuildMI, /*InsnID*/0, /*Opcode*/GIMT_Encode2(AMDGPU::BUFFER_LOAD_FORMAT_D16_XYZW_IDXEN),
        GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/0, // DstI[vdata]
        GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/2, // vindex
        GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/1, // rsrc
        GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/0, // soffset
        GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/5, // offset
        GIR_CustomOperandRenderer, /*InsnID*/0, /*OldInsnID*/0, /*OpIdx*/6, /*OperandRenderer*/GIMT_Encode2(GICR_renderExtractCPol), // auxiliary
        GIR_CustomOperandRenderer, /*InsnID*/0, /*OldInsnID*/0, /*OpIdx*/6, /*OperandRenderer*/GIMT_Encode2(GICR_renderExtractSWZ), // auxiliary
        GIR_MergeMemOperands, /*InsnID*/0, /*NumInsns*/1, /*MergeInsnID's*/0,
        GIR_ConstrainSelectedInstOperands, /*InsnID*/0,
        GIR_EraseFromParent, /*InsnID*/0,
        // GIR_Coverage, 4091,
        GIR_Done,
      // Label 6667: @490084
      GIM_Try, /*On fail goto*//*Label 6668*/ GIMT_Encode4(490163), // Rule ID 4095 //
        GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasPackedD16VMem),
        GIM_CheckRegBankForClass, /*MI*/0, /*Op*/0, /*RC*/GIMT_Encode2(AMDGPU::AV_64RegClassID),
        GIM_CheckConstantInt8, /*MI*/0, /*Op*/3, 0,
        // MIs[0] offset
        GIM_CheckIsImm, /*MI*/0, /*Op*/5,
        // MIs[0] auxiliary
        GIM_CheckIsImm, /*MI*/0, /*Op*/6,
        // MIs[0] Operand 7
        GIM_CheckIsImm, /*MI*/0, /*Op*/7,
        GIM_CheckComplexPattern, /*MI*/0, /*Op*/4, /*Renderer*/GIMT_Encode2(0), GIMT_Encode2(GICP_gi_buf_soffset),
        // (SIbuffer_load_format_d16:{ *:[v4f16] } v4i32:{ *:[v4i32] }:$rsrc, i32:{ *:[i32] }:$vindex, 0:{ *:[i32] }, (BUFSOffset:{ *:[i32] } i32:{ *:[i32] }:$soffset), (timm:{ *:[i32] }):$offset, (timm:{ *:[i32] }):$auxiliary, (timm:{ *:[i1] }))  =>  (BUFFER_LOAD_FORMAT_D16_XYZW_VBUFFER_IDXEN:{ *:[v4f16] } VGPR_32:{ *:[i32] }:$vindex, SReg_128:{ *:[v4i32] }:$rsrc, SCSrc_b32:{ *:[i32] }:$soffset, (timm:{ *:[i32] }):$offset, (extract_cpol:{ *:[i32] } ?:{ *:[i32] }:$auxiliary), (extract_swz:{ *:[i1] } ?:{ *:[i32] }:$auxiliary))
        GIR_BuildMI, /*InsnID*/0, /*Opcode*/GIMT_Encode2(AMDGPU::BUFFER_LOAD_FORMAT_D16_XYZW_VBUFFER_IDXEN),
        GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/0, // DstI[vdata]
        GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/2, // vindex
        GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/1, // rsrc
        GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/0, // soffset
        GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/5, // offset
        GIR_CustomOperandRenderer, /*InsnID*/0, /*OldInsnID*/0, /*OpIdx*/6, /*OperandRenderer*/GIMT_Encode2(GICR_renderExtractCPol), // auxiliary
        GIR_CustomOperandRenderer, /*InsnID*/0, /*OldInsnID*/0, /*OpIdx*/6, /*OperandRenderer*/GIMT_Encode2(GICR_renderExtractSWZ), // auxiliary
        GIR_MergeMemOperands, /*InsnID*/0, /*NumInsns*/1, /*MergeInsnID's*/0,
        GIR_ConstrainSelectedInstOperands, /*InsnID*/0,
        GIR_EraseFromParent, /*InsnID*/0,
        // GIR_Coverage, 4095,
        GIR_Done,
      // Label 6668: @490163
      GIM_Try, /*On fail goto*//*Label 6669*/ GIMT_Encode4(490242), // Rule ID 4099 //
        GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasPackedD16VMem_HasUnrestrictedSOffset),
        GIM_CheckRegBankForClass, /*MI*/0, /*Op*/0, /*RC*/GIMT_Encode2(AMDGPU::AV_64RegClassID),
        GIM_CheckConstantInt8, /*MI*/0, /*Op*/3, 0,
        // MIs[0] offset
        GIM_CheckIsImm, /*MI*/0, /*Op*/5,
        // MIs[0] auxiliary
        GIM_CheckIsImm, /*MI*/0, /*Op*/6,
        // MIs[0] Operand 7
        GIM_CheckIsImm, /*MI*/0, /*Op*/7,
        GIM_CheckComplexPattern, /*MI*/0, /*Op*/4, /*Renderer*/GIMT_Encode2(0), GIMT_Encode2(GICP_gi_buf_soffset),
        // (SIbuffer_load_format_d16:{ *:[v4i16] } v4i32:{ *:[v4i32] }:$rsrc, i32:{ *:[i32] }:$vindex, 0:{ *:[i32] }, (BUFSOffset:{ *:[i32] } i32:{ *:[i32] }:$soffset), (timm:{ *:[i32] }):$offset, (timm:{ *:[i32] }):$auxiliary, (timm:{ *:[i1] }))  =>  (BUFFER_LOAD_FORMAT_D16_XYZW_IDXEN:{ *:[v4i16] } VGPR_32:{ *:[i32] }:$vindex, SReg_128:{ *:[v4i32] }:$rsrc, SCSrc_b32:{ *:[i32] }:$soffset, (timm:{ *:[i32] }):$offset, (extract_cpol:{ *:[i32] } ?:{ *:[i32] }:$auxiliary), (extract_swz:{ *:[i1] } ?:{ *:[i32] }:$auxiliary))
        GIR_BuildMI, /*InsnID*/0, /*Opcode*/GIMT_Encode2(AMDGPU::BUFFER_LOAD_FORMAT_D16_XYZW_IDXEN),
        GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/0, // DstI[vdata]
        GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/2, // vindex
        GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/1, // rsrc
        GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/0, // soffset
        GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/5, // offset
        GIR_CustomOperandRenderer, /*InsnID*/0, /*OldInsnID*/0, /*OpIdx*/6, /*OperandRenderer*/GIMT_Encode2(GICR_renderExtractCPol), // auxiliary
        GIR_CustomOperandRenderer, /*InsnID*/0, /*OldInsnID*/0, /*OpIdx*/6, /*OperandRenderer*/GIMT_Encode2(GICR_renderExtractSWZ), // auxiliary
        GIR_MergeMemOperands, /*InsnID*/0, /*NumInsns*/1, /*MergeInsnID's*/0,
        GIR_ConstrainSelectedInstOperands, /*InsnID*/0,
        GIR_EraseFromParent, /*InsnID*/0,
        // GIR_Coverage, 4099,
        GIR_Done,
      // Label 6669: @490242
      GIM_Try, /*On fail goto*//*Label 6670*/ GIMT_Encode4(490321), // Rule ID 4103 //
        GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasPackedD16VMem),
        GIM_CheckRegBankForClass, /*MI*/0, /*Op*/0, /*RC*/GIMT_Encode2(AMDGPU::AV_64RegClassID),
        GIM_CheckConstantInt8, /*MI*/0, /*Op*/3, 0,
        // MIs[0] offset
        GIM_CheckIsImm, /*MI*/0, /*Op*/5,
        // MIs[0] auxiliary
        GIM_CheckIsImm, /*MI*/0, /*Op*/6,
        // MIs[0] Operand 7
        GIM_CheckIsImm, /*MI*/0, /*Op*/7,
        GIM_CheckComplexPattern, /*MI*/0, /*Op*/4, /*Renderer*/GIMT_Encode2(0), GIMT_Encode2(GICP_gi_buf_soffset),
        // (SIbuffer_load_format_d16:{ *:[v4i16] } v4i32:{ *:[v4i32] }:$rsrc, i32:{ *:[i32] }:$vindex, 0:{ *:[i32] }, (BUFSOffset:{ *:[i32] } i32:{ *:[i32] }:$soffset), (timm:{ *:[i32] }):$offset, (timm:{ *:[i32] }):$auxiliary, (timm:{ *:[i1] }))  =>  (BUFFER_LOAD_FORMAT_D16_XYZW_VBUFFER_IDXEN:{ *:[v4i16] } VGPR_32:{ *:[i32] }:$vindex, SReg_128:{ *:[v4i32] }:$rsrc, SCSrc_b32:{ *:[i32] }:$soffset, (timm:{ *:[i32] }):$offset, (extract_cpol:{ *:[i32] } ?:{ *:[i32] }:$auxiliary), (extract_swz:{ *:[i1] } ?:{ *:[i32] }:$auxiliary))
        GIR_BuildMI, /*InsnID*/0, /*Opcode*/GIMT_Encode2(AMDGPU::BUFFER_LOAD_FORMAT_D16_XYZW_VBUFFER_IDXEN),
        GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/0, // DstI[vdata]
        GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/2, // vindex
        GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/1, // rsrc
        GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/0, // soffset
        GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/5, // offset
        GIR_CustomOperandRenderer, /*InsnID*/0, /*OldInsnID*/0, /*OpIdx*/6, /*OperandRenderer*/GIMT_Encode2(GICR_renderExtractCPol), // auxiliary
        GIR_CustomOperandRenderer, /*InsnID*/0, /*OldInsnID*/0, /*OpIdx*/6, /*OperandRenderer*/GIMT_Encode2(GICR_renderExtractSWZ), // auxiliary
        GIR_MergeMemOperands, /*InsnID*/0, /*NumInsns*/1, /*MergeInsnID's*/0,
        GIR_ConstrainSelectedInstOperands, /*InsnID*/0,
        GIR_EraseFromParent, /*InsnID*/0,
        // GIR_Coverage, 4103,
        GIR_Done,
      // Label 6670: @490321
      GIM_Try, /*On fail goto*//*Label 6671*/ GIMT_Encode4(490443), // Rule ID 4076 //
        GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasPackedD16VMem_HasUnrestrictedSOffset),
        GIM_CheckMemorySizeEqualTo, /*MI*/0, /*MMO*/0, /*Size*/GIMT_Encode4(6),
        GIM_CheckRegBankForClass, /*MI*/0, /*Op*/0, /*RC*/GIMT_Encode2(AMDGPU::AV_64RegClassID),
        // MIs[0] offset
        GIM_CheckIsImm, /*MI*/0, /*Op*/5,
        // MIs[0] auxiliary
        GIM_CheckIsImm, /*MI*/0, /*Op*/6,
        // MIs[0] Operand 7
        GIM_CheckIsImm, /*MI*/0, /*Op*/7,
        GIM_CheckComplexPattern, /*MI*/0, /*Op*/4, /*Renderer*/GIMT_Encode2(0), GIMT_Encode2(GICP_gi_buf_soffset),
        // (SIbuffer_load_format_d16:{ *:[v4f16] } v4i32:{ *:[v4i32] }:$rsrc, i32:{ *:[i32] }:$vindex, i32:{ *:[i32] }:$voffset, (BUFSOffset:{ *:[i32] } i32:{ *:[i32] }:$soffset), (timm:{ *:[i32] }):$offset, (timm:{ *:[i32] }):$auxiliary, (timm:{ *:[i1] }))<<P:Predicate_anonymous_32257>>  =>  (BUFFER_LOAD_FORMAT_D16_XYZ_BOTHEN:{ *:[v4f16] } (REG_SEQUENCE:{ *:[i64] } VReg_64:{ *:[i32] }, VGPR_32:{ *:[i32] }:$vindex, sub0:{ *:[i32] }, VGPR_32:{ *:[i32] }:$voffset, sub1:{ *:[i32] }), SReg_128:{ *:[v4i32] }:$rsrc, SCSrc_b32:{ *:[i32] }:$soffset, (timm:{ *:[i32] }):$offset, (extract_cpol:{ *:[i32] } ?:{ *:[i32] }:$auxiliary), (extract_swz:{ *:[i1] } ?:{ *:[i32] }:$auxiliary))
        GIR_MakeTempReg, /*TempRegID*/0, /*TypeID*/GILLT_s64,
        GIR_BuildMI, /*InsnID*/1, /*Opcode*/GIMT_Encode2(TargetOpcode::REG_SEQUENCE),
        GIR_AddTempRegister, /*InsnID*/1, /*TempRegID*/0, /*TempRegFlags*/GIMT_Encode2(RegState::Define),
        GIR_Copy, /*NewInsnID*/1, /*OldInsnID*/0, /*OpIdx*/2, // vindex
        GIR_AddImm8, /*InsnID*/1, /*SubRegIndex*/3,
        GIR_Copy, /*NewInsnID*/1, /*OldInsnID*/0, /*OpIdx*/3, // voffset
        GIR_AddImm8, /*InsnID*/1, /*SubRegIndex*/11,
        GIR_ConstrainOperandRC, /*InsnID*/1, /*Op*/0, GIMT_Encode2(AMDGPU::VReg_64RegClassID),
        GIR_ConstrainOperandRC, /*InsnID*/1, /*Op*/1, GIMT_Encode2(AMDGPU::VGPR_32RegClassID),
        GIR_ConstrainOperandRC, /*InsnID*/1, /*Op*/3, GIMT_Encode2(AMDGPU::VGPR_32RegClassID),
        GIR_BuildMI, /*InsnID*/0, /*Opcode*/GIMT_Encode2(AMDGPU::BUFFER_LOAD_FORMAT_D16_XYZ_BOTHEN),
        GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/0, // DstI[vdata]
        GIR_AddSimpleTempRegister, /*InsnID*/0, /*TempRegID*/0,
        GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/1, // rsrc
        GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/0, // soffset
        GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/5, // offset
        GIR_CustomOperandRenderer, /*InsnID*/0, /*OldInsnID*/0, /*OpIdx*/6, /*OperandRenderer*/GIMT_Encode2(GICR_renderExtractCPol), // auxiliary
        GIR_CustomOperandRenderer, /*InsnID*/0, /*OldInsnID*/0, /*OpIdx*/6, /*OperandRenderer*/GIMT_Encode2(GICR_renderExtractSWZ), // auxiliary
        GIR_MergeMemOperands, /*InsnID*/0, /*NumInsns*/1, /*MergeInsnID's*/0,
        GIR_ConstrainSelectedInstOperands, /*InsnID*/0,
        GIR_EraseFromParent, /*InsnID*/0,
        // GIR_Coverage, 4076,
        GIR_Done,
      // Label 6671: @490443
      GIM_Try, /*On fail goto*//*Label 6672*/ GIMT_Encode4(490565), // Rule ID 4080 //
        GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasPackedD16VMem),
        GIM_CheckMemorySizeEqualTo, /*MI*/0, /*MMO*/0, /*Size*/GIMT_Encode4(6),
        GIM_CheckRegBankForClass, /*MI*/0, /*Op*/0, /*RC*/GIMT_Encode2(AMDGPU::AV_64RegClassID),
        // MIs[0] offset
        GIM_CheckIsImm, /*MI*/0, /*Op*/5,
        // MIs[0] auxiliary
        GIM_CheckIsImm, /*MI*/0, /*Op*/6,
        // MIs[0] Operand 7
        GIM_CheckIsImm, /*MI*/0, /*Op*/7,
        GIM_CheckComplexPattern, /*MI*/0, /*Op*/4, /*Renderer*/GIMT_Encode2(0), GIMT_Encode2(GICP_gi_buf_soffset),
        // (SIbuffer_load_format_d16:{ *:[v4f16] } v4i32:{ *:[v4i32] }:$rsrc, i32:{ *:[i32] }:$vindex, i32:{ *:[i32] }:$voffset, (BUFSOffset:{ *:[i32] } i32:{ *:[i32] }:$soffset), (timm:{ *:[i32] }):$offset, (timm:{ *:[i32] }):$auxiliary, (timm:{ *:[i1] }))<<P:Predicate_anonymous_32257>>  =>  (BUFFER_LOAD_FORMAT_D16_XYZ_VBUFFER_BOTHEN:{ *:[v4f16] } (REG_SEQUENCE:{ *:[i64] } VReg_64:{ *:[i32] }, VGPR_32:{ *:[i32] }:$vindex, sub0:{ *:[i32] }, VGPR_32:{ *:[i32] }:$voffset, sub1:{ *:[i32] }), SReg_128:{ *:[v4i32] }:$rsrc, SCSrc_b32:{ *:[i32] }:$soffset, (timm:{ *:[i32] }):$offset, (extract_cpol:{ *:[i32] } ?:{ *:[i32] }:$auxiliary), (extract_swz:{ *:[i1] } ?:{ *:[i32] }:$auxiliary))
        GIR_MakeTempReg, /*TempRegID*/0, /*TypeID*/GILLT_s64,
        GIR_BuildMI, /*InsnID*/1, /*Opcode*/GIMT_Encode2(TargetOpcode::REG_SEQUENCE),
        GIR_AddTempRegister, /*InsnID*/1, /*TempRegID*/0, /*TempRegFlags*/GIMT_Encode2(RegState::Define),
        GIR_Copy, /*NewInsnID*/1, /*OldInsnID*/0, /*OpIdx*/2, // vindex
        GIR_AddImm8, /*InsnID*/1, /*SubRegIndex*/3,
        GIR_Copy, /*NewInsnID*/1, /*OldInsnID*/0, /*OpIdx*/3, // voffset
        GIR_AddImm8, /*InsnID*/1, /*SubRegIndex*/11,
        GIR_ConstrainOperandRC, /*InsnID*/1, /*Op*/0, GIMT_Encode2(AMDGPU::VReg_64RegClassID),
        GIR_ConstrainOperandRC, /*InsnID*/1, /*Op*/1, GIMT_Encode2(AMDGPU::VGPR_32RegClassID),
        GIR_ConstrainOperandRC, /*InsnID*/1, /*Op*/3, GIMT_Encode2(AMDGPU::VGPR_32RegClassID),
        GIR_BuildMI, /*InsnID*/0, /*Opcode*/GIMT_Encode2(AMDGPU::BUFFER_LOAD_FORMAT_D16_XYZ_VBUFFER_BOTHEN),
        GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/0, // DstI[vdata]
        GIR_AddSimpleTempRegister, /*InsnID*/0, /*TempRegID*/0,
        GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/1, // rsrc
        GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/0, // soffset
        GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/5, // offset
        GIR_CustomOperandRenderer, /*InsnID*/0, /*OldInsnID*/0, /*OpIdx*/6, /*OperandRenderer*/GIMT_Encode2(GICR_renderExtractCPol), // auxiliary
        GIR_CustomOperandRenderer, /*InsnID*/0, /*OldInsnID*/0, /*OpIdx*/6, /*OperandRenderer*/GIMT_Encode2(GICR_renderExtractSWZ), // auxiliary
        GIR_MergeMemOperands, /*InsnID*/0, /*NumInsns*/1, /*MergeInsnID's*/0,
        GIR_ConstrainSelectedInstOperands, /*InsnID*/0,
        GIR_EraseFromParent, /*InsnID*/0,
        // GIR_Coverage, 4080,
        GIR_Done,
      // Label 6672: @490565
      GIM_Try, /*On fail goto*//*Label 6673*/ GIMT_Encode4(490687), // Rule ID 4084 //
        GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasPackedD16VMem_HasUnrestrictedSOffset),
        GIM_CheckMemorySizeEqualTo, /*MI*/0, /*MMO*/0, /*Size*/GIMT_Encode4(6),
        GIM_CheckRegBankForClass, /*MI*/0, /*Op*/0, /*RC*/GIMT_Encode2(AMDGPU::AV_64RegClassID),
        // MIs[0] offset
        GIM_CheckIsImm, /*MI*/0, /*Op*/5,
        // MIs[0] auxiliary
        GIM_CheckIsImm, /*MI*/0, /*Op*/6,
        // MIs[0] Operand 7
        GIM_CheckIsImm, /*MI*/0, /*Op*/7,
        GIM_CheckComplexPattern, /*MI*/0, /*Op*/4, /*Renderer*/GIMT_Encode2(0), GIMT_Encode2(GICP_gi_buf_soffset),
        // (SIbuffer_load_format_d16:{ *:[v4i16] } v4i32:{ *:[v4i32] }:$rsrc, i32:{ *:[i32] }:$vindex, i32:{ *:[i32] }:$voffset, (BUFSOffset:{ *:[i32] } i32:{ *:[i32] }:$soffset), (timm:{ *:[i32] }):$offset, (timm:{ *:[i32] }):$auxiliary, (timm:{ *:[i1] }))<<P:Predicate_anonymous_32267>>  =>  (BUFFER_LOAD_FORMAT_D16_XYZ_BOTHEN:{ *:[v4i16] } (REG_SEQUENCE:{ *:[i64] } VReg_64:{ *:[i32] }, VGPR_32:{ *:[i32] }:$vindex, sub0:{ *:[i32] }, VGPR_32:{ *:[i32] }:$voffset, sub1:{ *:[i32] }), SReg_128:{ *:[v4i32] }:$rsrc, SCSrc_b32:{ *:[i32] }:$soffset, (timm:{ *:[i32] }):$offset, (extract_cpol:{ *:[i32] } ?:{ *:[i32] }:$auxiliary), (extract_swz:{ *:[i1] } ?:{ *:[i32] }:$auxiliary))
        GIR_MakeTempReg, /*TempRegID*/0, /*TypeID*/GILLT_s64,
        GIR_BuildMI, /*InsnID*/1, /*Opcode*/GIMT_Encode2(TargetOpcode::REG_SEQUENCE),
        GIR_AddTempRegister, /*InsnID*/1, /*TempRegID*/0, /*TempRegFlags*/GIMT_Encode2(RegState::Define),
        GIR_Copy, /*NewInsnID*/1, /*OldInsnID*/0, /*OpIdx*/2, // vindex
        GIR_AddImm8, /*InsnID*/1, /*SubRegIndex*/3,
        GIR_Copy, /*NewInsnID*/1, /*OldInsnID*/0, /*OpIdx*/3, // voffset
        GIR_AddImm8, /*InsnID*/1, /*SubRegIndex*/11,
        GIR_ConstrainOperandRC, /*InsnID*/1, /*Op*/0, GIMT_Encode2(AMDGPU::VReg_64RegClassID),
        GIR_ConstrainOperandRC, /*InsnID*/1, /*Op*/1, GIMT_Encode2(AMDGPU::VGPR_32RegClassID),
        GIR_ConstrainOperandRC, /*InsnID*/1, /*Op*/3, GIMT_Encode2(AMDGPU::VGPR_32RegClassID),
        GIR_BuildMI, /*InsnID*/0, /*Opcode*/GIMT_Encode2(AMDGPU::BUFFER_LOAD_FORMAT_D16_XYZ_BOTHEN),
        GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/0, // DstI[vdata]
        GIR_AddSimpleTempRegister, /*InsnID*/0, /*TempRegID*/0,
        GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/1, // rsrc
        GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/0, // soffset
        GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/5, // offset
        GIR_CustomOperandRenderer, /*InsnID*/0, /*OldInsnID*/0, /*OpIdx*/6, /*OperandRenderer*/GIMT_Encode2(GICR_renderExtractCPol), // auxiliary
        GIR_CustomOperandRenderer, /*InsnID*/0, /*OldInsnID*/0, /*OpIdx*/6, /*OperandRenderer*/GIMT_Encode2(GICR_renderExtractSWZ), // auxiliary
        GIR_MergeMemOperands, /*InsnID*/0, /*NumInsns*/1, /*MergeInsnID's*/0,
        GIR_ConstrainSelectedInstOperands, /*InsnID*/0,
        GIR_EraseFromParent, /*InsnID*/0,
        // GIR_Coverage, 4084,
        GIR_Done,
      // Label 6673: @490687
      GIM_Try, /*On fail goto*//*Label 6674*/ GIMT_Encode4(490809), // Rule ID 4088 //
        GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasPackedD16VMem),
        GIM_CheckMemorySizeEqualTo, /*MI*/0, /*MMO*/0, /*Size*/GIMT_Encode4(6),
        GIM_CheckRegBankForClass, /*MI*/0, /*Op*/0, /*RC*/GIMT_Encode2(AMDGPU::AV_64RegClassID),
        // MIs[0] offset
        GIM_CheckIsImm, /*MI*/0, /*Op*/5,
        // MIs[0] auxiliary
        GIM_CheckIsImm, /*MI*/0, /*Op*/6,
        // MIs[0] Operand 7
        GIM_CheckIsImm, /*MI*/0, /*Op*/7,
        GIM_CheckComplexPattern, /*MI*/0, /*Op*/4, /*Renderer*/GIMT_Encode2(0), GIMT_Encode2(GICP_gi_buf_soffset),
        // (SIbuffer_load_format_d16:{ *:[v4i16] } v4i32:{ *:[v4i32] }:$rsrc, i32:{ *:[i32] }:$vindex, i32:{ *:[i32] }:$voffset, (BUFSOffset:{ *:[i32] } i32:{ *:[i32] }:$soffset), (timm:{ *:[i32] }):$offset, (timm:{ *:[i32] }):$auxiliary, (timm:{ *:[i1] }))<<P:Predicate_anonymous_32267>>  =>  (BUFFER_LOAD_FORMAT_D16_XYZ_VBUFFER_BOTHEN:{ *:[v4i16] } (REG_SEQUENCE:{ *:[i64] } VReg_64:{ *:[i32] }, VGPR_32:{ *:[i32] }:$vindex, sub0:{ *:[i32] }, VGPR_32:{ *:[i32] }:$voffset, sub1:{ *:[i32] }), SReg_128:{ *:[v4i32] }:$rsrc, SCSrc_b32:{ *:[i32] }:$soffset, (timm:{ *:[i32] }):$offset, (extract_cpol:{ *:[i32] } ?:{ *:[i32] }:$auxiliary), (extract_swz:{ *:[i1] } ?:{ *:[i32] }:$auxiliary))
        GIR_MakeTempReg, /*TempRegID*/0, /*TypeID*/GILLT_s64,
        GIR_BuildMI, /*InsnID*/1, /*Opcode*/GIMT_Encode2(TargetOpcode::REG_SEQUENCE),
        GIR_AddTempRegister, /*InsnID*/1, /*TempRegID*/0, /*TempRegFlags*/GIMT_Encode2(RegState::Define),
        GIR_Copy, /*NewInsnID*/1, /*OldInsnID*/0, /*OpIdx*/2, // vindex
        GIR_AddImm8, /*InsnID*/1, /*SubRegIndex*/3,
        GIR_Copy, /*NewInsnID*/1, /*OldInsnID*/0, /*OpIdx*/3, // voffset
        GIR_AddImm8, /*InsnID*/1, /*SubRegIndex*/11,
        GIR_ConstrainOperandRC, /*InsnID*/1, /*Op*/0, GIMT_Encode2(AMDGPU::VReg_64RegClassID),
        GIR_ConstrainOperandRC, /*InsnID*/1, /*Op*/1, GIMT_Encode2(AMDGPU::VGPR_32RegClassID),
        GIR_ConstrainOperandRC, /*InsnID*/1, /*Op*/3, GIMT_Encode2(AMDGPU::VGPR_32RegClassID),
        GIR_BuildMI, /*InsnID*/0, /*Opcode*/GIMT_Encode2(AMDGPU::BUFFER_LOAD_FORMAT_D16_XYZ_VBUFFER_BOTHEN),
        GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/0, // DstI[vdata]
        GIR_AddSimpleTempRegister, /*InsnID*/0, /*TempRegID*/0,
        GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/1, // rsrc
        GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/0, // soffset
        GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/5, // offset
        GIR_CustomOperandRenderer, /*InsnID*/0, /*OldInsnID*/0, /*OpIdx*/6, /*OperandRenderer*/GIMT_Encode2(GICR_renderExtractCPol), // auxiliary
        GIR_CustomOperandRenderer, /*InsnID*/0, /*OldInsnID*/0, /*OpIdx*/6, /*OperandRenderer*/GIMT_Encode2(GICR_renderExtractSWZ), // auxiliary
        GIR_MergeMemOperands, /*InsnID*/0, /*NumInsns*/1, /*MergeInsnID's*/0,
        GIR_ConstrainSelectedInstOperands, /*InsnID*/0,
        GIR_EraseFromParent, /*InsnID*/0,
        // GIR_Coverage, 4088,
        GIR_Done,
      // Label 6674: @490809
      GIM_Try, /*On fail goto*//*Label 6675*/ GIMT_Encode4(490924), // Rule ID 4092 //
        GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasPackedD16VMem_HasUnrestrictedSOffset),
        GIM_CheckRegBankForClass, /*MI*/0, /*Op*/0, /*RC*/GIMT_Encode2(AMDGPU::AV_64RegClassID),
        // MIs[0] offset
        GIM_CheckIsImm, /*MI*/0, /*Op*/5,
        // MIs[0] auxiliary
        GIM_CheckIsImm, /*MI*/0, /*Op*/6,
        // MIs[0] Operand 7
        GIM_CheckIsImm, /*MI*/0, /*Op*/7,
        GIM_CheckComplexPattern, /*MI*/0, /*Op*/4, /*Renderer*/GIMT_Encode2(0), GIMT_Encode2(GICP_gi_buf_soffset),
        // (SIbuffer_load_format_d16:{ *:[v4f16] } v4i32:{ *:[v4i32] }:$rsrc, i32:{ *:[i32] }:$vindex, i32:{ *:[i32] }:$voffset, (BUFSOffset:{ *:[i32] } i32:{ *:[i32] }:$soffset), (timm:{ *:[i32] }):$offset, (timm:{ *:[i32] }):$auxiliary, (timm:{ *:[i1] }))  =>  (BUFFER_LOAD_FORMAT_D16_XYZW_BOTHEN:{ *:[v4f16] } (REG_SEQUENCE:{ *:[i64] } VReg_64:{ *:[i32] }, VGPR_32:{ *:[i32] }:$vindex, sub0:{ *:[i32] }, VGPR_32:{ *:[i32] }:$voffset, sub1:{ *:[i32] }), SReg_128:{ *:[v4i32] }:$rsrc, SCSrc_b32:{ *:[i32] }:$soffset, (timm:{ *:[i32] }):$offset, (extract_cpol:{ *:[i32] } ?:{ *:[i32] }:$auxiliary), (extract_swz:{ *:[i1] } ?:{ *:[i32] }:$auxiliary))
        GIR_MakeTempReg, /*TempRegID*/0, /*TypeID*/GILLT_s64,
        GIR_BuildMI, /*InsnID*/1, /*Opcode*/GIMT_Encode2(TargetOpcode::REG_SEQUENCE),
        GIR_AddTempRegister, /*InsnID*/1, /*TempRegID*/0, /*TempRegFlags*/GIMT_Encode2(RegState::Define),
        GIR_Copy, /*NewInsnID*/1, /*OldInsnID*/0, /*OpIdx*/2, // vindex
        GIR_AddImm8, /*InsnID*/1, /*SubRegIndex*/3,
        GIR_Copy, /*NewInsnID*/1, /*OldInsnID*/0, /*OpIdx*/3, // voffset
        GIR_AddImm8, /*InsnID*/1, /*SubRegIndex*/11,
        GIR_ConstrainOperandRC, /*InsnID*/1, /*Op*/0, GIMT_Encode2(AMDGPU::VReg_64RegClassID),
        GIR_ConstrainOperandRC, /*InsnID*/1, /*Op*/1, GIMT_Encode2(AMDGPU::VGPR_32RegClassID),
        GIR_ConstrainOperandRC, /*InsnID*/1, /*Op*/3, GIMT_Encode2(AMDGPU::VGPR_32RegClassID),
        GIR_BuildMI, /*InsnID*/0, /*Opcode*/GIMT_Encode2(AMDGPU::BUFFER_LOAD_FORMAT_D16_XYZW_BOTHEN),
        GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/0, // DstI[vdata]
        GIR_AddSimpleTempRegister, /*InsnID*/0, /*TempRegID*/0,
        GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/1, // rsrc
        GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/0, // soffset
        GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/5, // offset
        GIR_CustomOperandRenderer, /*InsnID*/0, /*OldInsnID*/0, /*OpIdx*/6, /*OperandRenderer*/GIMT_Encode2(GICR_renderExtractCPol), // auxiliary
        GIR_CustomOperandRenderer, /*InsnID*/0, /*OldInsnID*/0, /*OpIdx*/6, /*OperandRenderer*/GIMT_Encode2(GICR_renderExtractSWZ), // auxiliary
        GIR_MergeMemOperands, /*InsnID*/0, /*NumInsns*/1, /*MergeInsnID's*/0,
        GIR_ConstrainSelectedInstOperands, /*InsnID*/0,
        GIR_EraseFromParent, /*InsnID*/0,
        // GIR_Coverage, 4092,
        GIR_Done,
      // Label 6675: @490924
      GIM_Try, /*On fail goto*//*Label 6676*/ GIMT_Encode4(491039), // Rule ID 4096 //
        GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasPackedD16VMem),
        GIM_CheckRegBankForClass, /*MI*/0, /*Op*/0, /*RC*/GIMT_Encode2(AMDGPU::AV_64RegClassID),
        // MIs[0] offset
        GIM_CheckIsImm, /*MI*/0, /*Op*/5,
        // MIs[0] auxiliary
        GIM_CheckIsImm, /*MI*/0, /*Op*/6,
        // MIs[0] Operand 7
        GIM_CheckIsImm, /*MI*/0, /*Op*/7,
        GIM_CheckComplexPattern, /*MI*/0, /*Op*/4, /*Renderer*/GIMT_Encode2(0), GIMT_Encode2(GICP_gi_buf_soffset),
        // (SIbuffer_load_format_d16:{ *:[v4f16] } v4i32:{ *:[v4i32] }:$rsrc, i32:{ *:[i32] }:$vindex, i32:{ *:[i32] }:$voffset, (BUFSOffset:{ *:[i32] } i32:{ *:[i32] }:$soffset), (timm:{ *:[i32] }):$offset, (timm:{ *:[i32] }):$auxiliary, (timm:{ *:[i1] }))  =>  (BUFFER_LOAD_FORMAT_D16_XYZW_VBUFFER_BOTHEN:{ *:[v4f16] } (REG_SEQUENCE:{ *:[i64] } VReg_64:{ *:[i32] }, VGPR_32:{ *:[i32] }:$vindex, sub0:{ *:[i32] }, VGPR_32:{ *:[i32] }:$voffset, sub1:{ *:[i32] }), SReg_128:{ *:[v4i32] }:$rsrc, SCSrc_b32:{ *:[i32] }:$soffset, (timm:{ *:[i32] }):$offset, (extract_cpol:{ *:[i32] } ?:{ *:[i32] }:$auxiliary), (extract_swz:{ *:[i1] } ?:{ *:[i32] }:$auxiliary))
        GIR_MakeTempReg, /*TempRegID*/0, /*TypeID*/GILLT_s64,
        GIR_BuildMI, /*InsnID*/1, /*Opcode*/GIMT_Encode2(TargetOpcode::REG_SEQUENCE),
        GIR_AddTempRegister, /*InsnID*/1, /*TempRegID*/0, /*TempRegFlags*/GIMT_Encode2(RegState::Define),
        GIR_Copy, /*NewInsnID*/1, /*OldInsnID*/0, /*OpIdx*/2, // vindex
        GIR_AddImm8, /*InsnID*/1, /*SubRegIndex*/3,
        GIR_Copy, /*NewInsnID*/1, /*OldInsnID*/0, /*OpIdx*/3, // voffset
        GIR_AddImm8, /*InsnID*/1, /*SubRegIndex*/11,
        GIR_ConstrainOperandRC, /*InsnID*/1, /*Op*/0, GIMT_Encode2(AMDGPU::VReg_64RegClassID),
        GIR_ConstrainOperandRC, /*InsnID*/1, /*Op*/1, GIMT_Encode2(AMDGPU::VGPR_32RegClassID),
        GIR_ConstrainOperandRC, /*InsnID*/1, /*Op*/3, GIMT_Encode2(AMDGPU::VGPR_32RegClassID),
        GIR_BuildMI, /*InsnID*/0, /*Opcode*/GIMT_Encode2(AMDGPU::BUFFER_LOAD_FORMAT_D16_XYZW_VBUFFER_BOTHEN),
        GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/0, // DstI[vdata]
        GIR_AddSimpleTempRegister, /*InsnID*/0, /*TempRegID*/0,
        GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/1, // rsrc
        GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/0, // soffset
        GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/5, // offset
        GIR_CustomOperandRenderer, /*InsnID*/0, /*OldInsnID*/0, /*OpIdx*/6, /*OperandRenderer*/GIMT_Encode2(GICR_renderExtractCPol), // auxiliary
        GIR_CustomOperandRenderer, /*InsnID*/0, /*OldInsnID*/0, /*OpIdx*/6, /*OperandRenderer*/GIMT_Encode2(GICR_renderExtractSWZ), // auxiliary
        GIR_MergeMemOperands, /*InsnID*/0, /*NumInsns*/1, /*MergeInsnID's*/0,
        GIR_ConstrainSelectedInstOperands, /*InsnID*/0,
        GIR_EraseFromParent, /*InsnID*/0,
        // GIR_Coverage, 4096,
        GIR_Done,
      // Label 6676: @491039
      GIM_Try, /*On fail goto*//*Label 6677*/ GIMT_Encode4(491154), // Rule ID 4100 //
        GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasPackedD16VMem_HasUnrestrictedSOffset),
        GIM_CheckRegBankForClass, /*MI*/0, /*Op*/0, /*RC*/GIMT_Encode2(AMDGPU::AV_64RegClassID),
        // MIs[0] offset
        GIM_CheckIsImm, /*MI*/0, /*Op*/5,
        // MIs[0] auxiliary
        GIM_CheckIsImm, /*MI*/0, /*Op*/6,
        // MIs[0] Operand 7
        GIM_CheckIsImm, /*MI*/0, /*Op*/7,
        GIM_CheckComplexPattern, /*MI*/0, /*Op*/4, /*Renderer*/GIMT_Encode2(0), GIMT_Encode2(GICP_gi_buf_soffset),
        // (SIbuffer_load_format_d16:{ *:[v4i16] } v4i32:{ *:[v4i32] }:$rsrc, i32:{ *:[i32] }:$vindex, i32:{ *:[i32] }:$voffset, (BUFSOffset:{ *:[i32] } i32:{ *:[i32] }:$soffset), (timm:{ *:[i32] }):$offset, (timm:{ *:[i32] }):$auxiliary, (timm:{ *:[i1] }))  =>  (BUFFER_LOAD_FORMAT_D16_XYZW_BOTHEN:{ *:[v4i16] } (REG_SEQUENCE:{ *:[i64] } VReg_64:{ *:[i32] }, VGPR_32:{ *:[i32] }:$vindex, sub0:{ *:[i32] }, VGPR_32:{ *:[i32] }:$voffset, sub1:{ *:[i32] }), SReg_128:{ *:[v4i32] }:$rsrc, SCSrc_b32:{ *:[i32] }:$soffset, (timm:{ *:[i32] }):$offset, (extract_cpol:{ *:[i32] } ?:{ *:[i32] }:$auxiliary), (extract_swz:{ *:[i1] } ?:{ *:[i32] }:$auxiliary))
        GIR_MakeTempReg, /*TempRegID*/0, /*TypeID*/GILLT_s64,
        GIR_BuildMI, /*InsnID*/1, /*Opcode*/GIMT_Encode2(TargetOpcode::REG_SEQUENCE),
        GIR_AddTempRegister, /*InsnID*/1, /*TempRegID*/0, /*TempRegFlags*/GIMT_Encode2(RegState::Define),
        GIR_Copy, /*NewInsnID*/1, /*OldInsnID*/0, /*OpIdx*/2, // vindex
        GIR_AddImm8, /*InsnID*/1, /*SubRegIndex*/3,
        GIR_Copy, /*NewInsnID*/1, /*OldInsnID*/0, /*OpIdx*/3, // voffset
        GIR_AddImm8, /*InsnID*/1, /*SubRegIndex*/11,
        GIR_ConstrainOperandRC, /*InsnID*/1, /*Op*/0, GIMT_Encode2(AMDGPU::VReg_64RegClassID),
        GIR_ConstrainOperandRC, /*InsnID*/1, /*Op*/1, GIMT_Encode2(AMDGPU::VGPR_32RegClassID),
        GIR_ConstrainOperandRC, /*InsnID*/1, /*Op*/3, GIMT_Encode2(AMDGPU::VGPR_32RegClassID),
        GIR_BuildMI, /*InsnID*/0, /*Opcode*/GIMT_Encode2(AMDGPU::BUFFER_LOAD_FORMAT_D16_XYZW_BOTHEN),
        GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/0, // DstI[vdata]
        GIR_AddSimpleTempRegister, /*InsnID*/0, /*TempRegID*/0,
        GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/1, // rsrc
        GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/0, // soffset
        GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/5, // offset
        GIR_CustomOperandRenderer, /*InsnID*/0, /*OldInsnID*/0, /*OpIdx*/6, /*OperandRenderer*/GIMT_Encode2(GICR_renderExtractCPol), // auxiliary
        GIR_CustomOperandRenderer, /*InsnID*/0, /*OldInsnID*/0, /*OpIdx*/6, /*OperandRenderer*/GIMT_Encode2(GICR_renderExtractSWZ), // auxiliary
        GIR_MergeMemOperands, /*InsnID*/0, /*NumInsns*/1, /*MergeInsnID's*/0,
        GIR_ConstrainSelectedInstOperands, /*InsnID*/0,
        GIR_EraseFromParent, /*InsnID*/0,
        // GIR_Coverage, 4100,
        GIR_Done,
      // Label 6677: @491154
      GIM_Try, /*On fail goto*//*Label 6678*/ GIMT_Encode4(491269), // Rule ID 4104 //
        GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasPackedD16VMem),
        GIM_CheckRegBankForClass, /*MI*/0, /*Op*/0, /*RC*/GIMT_Encode2(AMDGPU::AV_64RegClassID),
        // MIs[0] offset
        GIM_CheckIsImm, /*MI*/0, /*Op*/5,
        // MIs[0] auxiliary
        GIM_CheckIsImm, /*MI*/0, /*Op*/6,
        // MIs[0] Operand 7
        GIM_CheckIsImm, /*MI*/0, /*Op*/7,
        GIM_CheckComplexPattern, /*MI*/0, /*Op*/4, /*Renderer*/GIMT_Encode2(0), GIMT_Encode2(GICP_gi_buf_soffset),
        // (SIbuffer_load_format_d16:{ *:[v4i16] } v4i32:{ *:[v4i32] }:$rsrc, i32:{ *:[i32] }:$vindex, i32:{ *:[i32] }:$voffset, (BUFSOffset:{ *:[i32] } i32:{ *:[i32] }:$soffset), (timm:{ *:[i32] }):$offset, (timm:{ *:[i32] }):$auxiliary, (timm:{ *:[i1] }))  =>  (BUFFER_LOAD_FORMAT_D16_XYZW_VBUFFER_BOTHEN:{ *:[v4i16] } (REG_SEQUENCE:{ *:[i64] } VReg_64:{ *:[i32] }, VGPR_32:{ *:[i32] }:$vindex, sub0:{ *:[i32] }, VGPR_32:{ *:[i32] }:$voffset, sub1:{ *:[i32] }), SReg_128:{ *:[v4i32] }:$rsrc, SCSrc_b32:{ *:[i32] }:$soffset, (timm:{ *:[i32] }):$offset, (extract_cpol:{ *:[i32] } ?:{ *:[i32] }:$auxiliary), (extract_swz:{ *:[i1] } ?:{ *:[i32] }:$auxiliary))
        GIR_MakeTempReg, /*TempRegID*/0, /*TypeID*/GILLT_s64,
        GIR_BuildMI, /*InsnID*/1, /*Opcode*/GIMT_Encode2(TargetOpcode::REG_SEQUENCE),
        GIR_AddTempRegister, /*InsnID*/1, /*TempRegID*/0, /*TempRegFlags*/GIMT_Encode2(RegState::Define),
        GIR_Copy, /*NewInsnID*/1, /*OldInsnID*/0, /*OpIdx*/2, // vindex
        GIR_AddImm8, /*InsnID*/1, /*SubRegIndex*/3,
        GIR_Copy, /*NewInsnID*/1, /*OldInsnID*/0, /*OpIdx*/3, // voffset
        GIR_AddImm8, /*InsnID*/1, /*SubRegIndex*/11,
        GIR_ConstrainOperandRC, /*InsnID*/1, /*Op*/0, GIMT_Encode2(AMDGPU::VReg_64RegClassID),
        GIR_ConstrainOperandRC, /*InsnID*/1, /*Op*/1, GIMT_Encode2(AMDGPU::VGPR_32RegClassID),
        GIR_ConstrainOperandRC, /*InsnID*/1, /*Op*/3, GIMT_Encode2(AMDGPU::VGPR_32RegClassID),
        GIR_BuildMI, /*InsnID*/0, /*Opcode*/GIMT_Encode2(AMDGPU::BUFFER_LOAD_FORMAT_D16_XYZW_VBUFFER_BOTHEN),
        GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/0, // DstI[vdata]
        GIR_AddSimpleTempRegister, /*InsnID*/0, /*TempRegID*/0,
        GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/1, // rsrc
        GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/0, // soffset
        GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/5, // offset
        GIR_CustomOperandRenderer, /*InsnID*/0, /*OldInsnID*/0, /*OpIdx*/6, /*OperandRenderer*/GIMT_Encode2(GICR_renderExtractCPol), // auxiliary
        GIR_CustomOperandRenderer, /*InsnID*/0, /*OldInsnID*/0, /*OpIdx*/6, /*OperandRenderer*/GIMT_Encode2(GICR_renderExtractSWZ), // auxiliary
        GIR_MergeMemOperands, /*InsnID*/0, /*NumInsns*/1, /*MergeInsnID's*/0,
        GIR_ConstrainSelectedInstOperands, /*InsnID*/0,
        GIR_EraseFromParent, /*InsnID*/0,
        // GIR_Coverage, 4104,
        GIR_Done,
      // Label 6678: @491269
      GIM_Reject,
    // Label 6646: @491270
    GIM_Reject,
    // Label 6579: @491271
    GIM_Try, /*On fail goto*//*Label 6679*/ GIMT_Encode4(491646),
      GIM_CheckType, /*MI*/0, /*Op*/1, /*Type*/GILLT_v4s32,
      GIM_CheckType, /*MI*/0, /*Op*/2, /*Type*/GILLT_s32,
      GIM_CheckType, /*MI*/0, /*Op*/3, /*Type*/GILLT_s32,
      GIM_CheckType, /*MI*/0, /*Op*/4, /*Type*/GILLT_s32,
      GIM_CheckRegBankForClass, /*MI*/0, /*Op*/0, /*RC*/GIMT_Encode2(AMDGPU::AV_128RegClassID),
      GIM_Try, /*On fail goto*//*Label 6680*/ GIMT_Encode4(491379), // Rule ID 4029 //
        GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasUnpackedD16VMem),
        GIM_CheckConstantInt8, /*MI*/0, /*Op*/2, 0,
        GIM_CheckConstantInt8, /*MI*/0, /*Op*/3, 0,
        // MIs[0] offset
        GIM_CheckIsImm, /*MI*/0, /*Op*/5,
        // MIs[0] auxiliary
        GIM_CheckIsImm, /*MI*/0, /*Op*/6,
        // MIs[0] Operand 7
        GIM_CheckLiteralInt, /*MI*/0, /*Op*/7, GIMT_Encode8(0),
        GIM_CheckComplexPattern, /*MI*/0, /*Op*/4, /*Renderer*/GIMT_Encode2(0), GIMT_Encode2(GICP_gi_buf_soffset),
        // (SIbuffer_load_format_d16:{ *:[v4i32] } v4i32:{ *:[v4i32] }:$rsrc, 0:{ *:[i32] }, 0:{ *:[i32] }, (BUFSOffset:{ *:[i32] } i32:{ *:[i32] }:$soffset), (timm:{ *:[i32] }):$offset, (timm:{ *:[i32] }):$auxiliary, 0:{ *:[i1] })  =>  (BUFFER_LOAD_FORMAT_D16_XYZW_gfx80_OFFSET:{ *:[v4i32] } SReg_128:{ *:[v4i32] }:$rsrc, SCSrc_b32:{ *:[i32] }:$soffset, (timm:{ *:[i32] }):$offset, (extract_cpol:{ *:[i32] } ?:{ *:[i32] }:$auxiliary), (extract_swz:{ *:[i1] } ?:{ *:[i32] }:$auxiliary))
        GIR_BuildMI, /*InsnID*/0, /*Opcode*/GIMT_Encode2(AMDGPU::BUFFER_LOAD_FORMAT_D16_XYZW_gfx80_OFFSET),
        GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/0, // DstI[vdata]
        GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/1, // rsrc
        GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/0, // soffset
        GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/5, // offset
        GIR_CustomOperandRenderer, /*InsnID*/0, /*OldInsnID*/0, /*OpIdx*/6, /*OperandRenderer*/GIMT_Encode2(GICR_renderExtractCPol), // auxiliary
        GIR_CustomOperandRenderer, /*InsnID*/0, /*OldInsnID*/0, /*OpIdx*/6, /*OperandRenderer*/GIMT_Encode2(GICR_renderExtractSWZ), // auxiliary
        GIR_MergeMemOperands, /*InsnID*/0, /*NumInsns*/1, /*MergeInsnID's*/0,
        GIR_ConstrainSelectedInstOperands, /*InsnID*/0,
        GIR_EraseFromParent, /*InsnID*/0,
        // GIR_Coverage, 4029,
        GIR_Done,
      // Label 6680: @491379
      GIM_Try, /*On fail goto*//*Label 6681*/ GIMT_Encode4(491461), // Rule ID 4030 //
        GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasUnpackedD16VMem),
        GIM_CheckConstantInt8, /*MI*/0, /*Op*/2, 0,
        // MIs[0] offset
        GIM_CheckIsImm, /*MI*/0, /*Op*/5,
        // MIs[0] auxiliary
        GIM_CheckIsImm, /*MI*/0, /*Op*/6,
        // MIs[0] Operand 7
        GIM_CheckLiteralInt, /*MI*/0, /*Op*/7, GIMT_Encode8(0),
        GIM_CheckComplexPattern, /*MI*/0, /*Op*/4, /*Renderer*/GIMT_Encode2(0), GIMT_Encode2(GICP_gi_buf_soffset),
        // (SIbuffer_load_format_d16:{ *:[v4i32] } v4i32:{ *:[v4i32] }:$rsrc, 0:{ *:[i32] }, i32:{ *:[i32] }:$voffset, (BUFSOffset:{ *:[i32] } i32:{ *:[i32] }:$soffset), (timm:{ *:[i32] }):$offset, (timm:{ *:[i32] }):$auxiliary, 0:{ *:[i1] })  =>  (BUFFER_LOAD_FORMAT_D16_XYZW_gfx80_OFFEN:{ *:[v4i32] } VGPR_32:{ *:[i32] }:$voffset, SReg_128:{ *:[v4i32] }:$rsrc, SCSrc_b32:{ *:[i32] }:$soffset, (timm:{ *:[i32] }):$offset, (extract_cpol:{ *:[i32] } ?:{ *:[i32] }:$auxiliary), (extract_swz:{ *:[i1] } ?:{ *:[i32] }:$auxiliary))
        GIR_BuildMI, /*InsnID*/0, /*Opcode*/GIMT_Encode2(AMDGPU::BUFFER_LOAD_FORMAT_D16_XYZW_gfx80_OFFEN),
        GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/0, // DstI[vdata]
        GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/3, // voffset
        GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/1, // rsrc
        GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/0, // soffset
        GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/5, // offset
        GIR_CustomOperandRenderer, /*InsnID*/0, /*OldInsnID*/0, /*OpIdx*/6, /*OperandRenderer*/GIMT_Encode2(GICR_renderExtractCPol), // auxiliary
        GIR_CustomOperandRenderer, /*InsnID*/0, /*OldInsnID*/0, /*OpIdx*/6, /*OperandRenderer*/GIMT_Encode2(GICR_renderExtractSWZ), // auxiliary
        GIR_MergeMemOperands, /*InsnID*/0, /*NumInsns*/1, /*MergeInsnID's*/0,
        GIR_ConstrainSelectedInstOperands, /*InsnID*/0,
        GIR_EraseFromParent, /*InsnID*/0,
        // GIR_Coverage, 4030,
        GIR_Done,
      // Label 6681: @491461
      GIM_Try, /*On fail goto*//*Label 6682*/ GIMT_Encode4(491535), // Rule ID 4031 //
        GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasUnpackedD16VMem),
        GIM_CheckConstantInt8, /*MI*/0, /*Op*/3, 0,
        // MIs[0] offset
        GIM_CheckIsImm, /*MI*/0, /*Op*/5,
        // MIs[0] auxiliary
        GIM_CheckIsImm, /*MI*/0, /*Op*/6,
        // MIs[0] Operand 7
        GIM_CheckIsImm, /*MI*/0, /*Op*/7,
        GIM_CheckComplexPattern, /*MI*/0, /*Op*/4, /*Renderer*/GIMT_Encode2(0), GIMT_Encode2(GICP_gi_buf_soffset),
        // (SIbuffer_load_format_d16:{ *:[v4i32] } v4i32:{ *:[v4i32] }:$rsrc, i32:{ *:[i32] }:$vindex, 0:{ *:[i32] }, (BUFSOffset:{ *:[i32] } i32:{ *:[i32] }:$soffset), (timm:{ *:[i32] }):$offset, (timm:{ *:[i32] }):$auxiliary, (timm:{ *:[i1] }))  =>  (BUFFER_LOAD_FORMAT_D16_XYZW_gfx80_IDXEN:{ *:[v4i32] } VGPR_32:{ *:[i32] }:$vindex, SReg_128:{ *:[v4i32] }:$rsrc, SCSrc_b32:{ *:[i32] }:$soffset, (timm:{ *:[i32] }):$offset, (extract_cpol:{ *:[i32] } ?:{ *:[i32] }:$auxiliary), (extract_swz:{ *:[i1] } ?:{ *:[i32] }:$auxiliary))
        GIR_BuildMI, /*InsnID*/0, /*Opcode*/GIMT_Encode2(AMDGPU::BUFFER_LOAD_FORMAT_D16_XYZW_gfx80_IDXEN),
        GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/0, // DstI[vdata]
        GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/2, // vindex
        GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/1, // rsrc
        GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/0, // soffset
        GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/5, // offset
        GIR_CustomOperandRenderer, /*InsnID*/0, /*OldInsnID*/0, /*OpIdx*/6, /*OperandRenderer*/GIMT_Encode2(GICR_renderExtractCPol), // auxiliary
        GIR_CustomOperandRenderer, /*InsnID*/0, /*OldInsnID*/0, /*OpIdx*/6, /*OperandRenderer*/GIMT_Encode2(GICR_renderExtractSWZ), // auxiliary
        GIR_MergeMemOperands, /*InsnID*/0, /*NumInsns*/1, /*MergeInsnID's*/0,
        GIR_ConstrainSelectedInstOperands, /*InsnID*/0,
        GIR_EraseFromParent, /*InsnID*/0,
        // GIR_Coverage, 4031,
        GIR_Done,
      // Label 6682: @491535
      GIM_Try, /*On fail goto*//*Label 6683*/ GIMT_Encode4(491645), // Rule ID 4032 //
        GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasUnpackedD16VMem),
        // MIs[0] offset
        GIM_CheckIsImm, /*MI*/0, /*Op*/5,
        // MIs[0] auxiliary
        GIM_CheckIsImm, /*MI*/0, /*Op*/6,
        // MIs[0] Operand 7
        GIM_CheckIsImm, /*MI*/0, /*Op*/7,
        GIM_CheckComplexPattern, /*MI*/0, /*Op*/4, /*Renderer*/GIMT_Encode2(0), GIMT_Encode2(GICP_gi_buf_soffset),
        // (SIbuffer_load_format_d16:{ *:[v4i32] } v4i32:{ *:[v4i32] }:$rsrc, i32:{ *:[i32] }:$vindex, i32:{ *:[i32] }:$voffset, (BUFSOffset:{ *:[i32] } i32:{ *:[i32] }:$soffset), (timm:{ *:[i32] }):$offset, (timm:{ *:[i32] }):$auxiliary, (timm:{ *:[i1] }))  =>  (BUFFER_LOAD_FORMAT_D16_XYZW_gfx80_BOTHEN:{ *:[v4i32] } (REG_SEQUENCE:{ *:[i64] } VReg_64:{ *:[i32] }, VGPR_32:{ *:[i32] }:$vindex, sub0:{ *:[i32] }, VGPR_32:{ *:[i32] }:$voffset, sub1:{ *:[i32] }), SReg_128:{ *:[v4i32] }:$rsrc, SCSrc_b32:{ *:[i32] }:$soffset, (timm:{ *:[i32] }):$offset, (extract_cpol:{ *:[i32] } ?:{ *:[i32] }:$auxiliary), (extract_swz:{ *:[i1] } ?:{ *:[i32] }:$auxiliary))
        GIR_MakeTempReg, /*TempRegID*/0, /*TypeID*/GILLT_s64,
        GIR_BuildMI, /*InsnID*/1, /*Opcode*/GIMT_Encode2(TargetOpcode::REG_SEQUENCE),
        GIR_AddTempRegister, /*InsnID*/1, /*TempRegID*/0, /*TempRegFlags*/GIMT_Encode2(RegState::Define),
        GIR_Copy, /*NewInsnID*/1, /*OldInsnID*/0, /*OpIdx*/2, // vindex
        GIR_AddImm8, /*InsnID*/1, /*SubRegIndex*/3,
        GIR_Copy, /*NewInsnID*/1, /*OldInsnID*/0, /*OpIdx*/3, // voffset
        GIR_AddImm8, /*InsnID*/1, /*SubRegIndex*/11,
        GIR_ConstrainOperandRC, /*InsnID*/1, /*Op*/0, GIMT_Encode2(AMDGPU::VReg_64RegClassID),
        GIR_ConstrainOperandRC, /*InsnID*/1, /*Op*/1, GIMT_Encode2(AMDGPU::VGPR_32RegClassID),
        GIR_ConstrainOperandRC, /*InsnID*/1, /*Op*/3, GIMT_Encode2(AMDGPU::VGPR_32RegClassID),
        GIR_BuildMI, /*InsnID*/0, /*Opcode*/GIMT_Encode2(AMDGPU::BUFFER_LOAD_FORMAT_D16_XYZW_gfx80_BOTHEN),
        GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/0, // DstI[vdata]
        GIR_AddSimpleTempRegister, /*InsnID*/0, /*TempRegID*/0,
        GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/1, // rsrc
        GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/0, // soffset
        GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/5, // offset
        GIR_CustomOperandRenderer, /*InsnID*/0, /*OldInsnID*/0, /*OpIdx*/6, /*OperandRenderer*/GIMT_Encode2(GICR_renderExtractCPol), // auxiliary
        GIR_CustomOperandRenderer, /*InsnID*/0, /*OldInsnID*/0, /*OpIdx*/6, /*OperandRenderer*/GIMT_Encode2(GICR_renderExtractSWZ), // auxiliary
        GIR_MergeMemOperands, /*InsnID*/0, /*NumInsns*/1, /*MergeInsnID's*/0,
        GIR_ConstrainSelectedInstOperands, /*InsnID*/0,
        GIR_EraseFromParent, /*InsnID*/0,
        // GIR_Coverage, 4032,
        GIR_Done,
      // Label 6683: @491645
      GIM_Reject,
    // Label 6679: @491646
    GIM_Reject,
    // Label 6580: @491647
    GIM_Reject,
    // Label 127: @491648
    GIM_SwitchType, /*MI*/0, /*Op*/0, /*[*/GIMT_Encode2(12), GIMT_Encode2(20), /*)*//*default:*//*Label 6688*/ GIMT_Encode4(494539),
    /*GILLT_v2s32*//*Label 6684*/ GIMT_Encode4(491691), GIMT_Encode4(0),
    /*GILLT_v3s32*//*Label 6685*/ GIMT_Encode4(492403), GIMT_Encode4(0), GIMT_Encode4(0),
    /*GILLT_v4s32*//*Label 6686*/ GIMT_Encode4(493115), GIMT_Encode4(0),
    /*GILLT_v5s32*//*Label 6687*/ GIMT_Encode4(493827),
    // Label 6684: @491691
    GIM_Try, /*On fail goto*//*Label 6689*/ GIMT_Encode4(492402),
      GIM_CheckType, /*MI*/0, /*Op*/1, /*Type*/GILLT_v4s32,
      GIM_CheckType, /*MI*/0, /*Op*/2, /*Type*/GILLT_s32,
      GIM_CheckType, /*MI*/0, /*Op*/3, /*Type*/GILLT_s32,
      GIM_CheckType, /*MI*/0, /*Op*/4, /*Type*/GILLT_s32,
      GIM_CheckRegBankForClass, /*MI*/0, /*Op*/0, /*RC*/GIMT_Encode2(AMDGPU::AV_64RegClassID),
      GIM_Try, /*On fail goto*//*Label 6690*/ GIMT_Encode4(491799), // Rule ID 3977 //
        GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasUnrestrictedSOffset),
        GIM_CheckConstantInt8, /*MI*/0, /*Op*/2, 0,
        GIM_CheckConstantInt8, /*MI*/0, /*Op*/3, 0,
        // MIs[0] offset
        GIM_CheckIsImm, /*MI*/0, /*Op*/5,
        // MIs[0] auxiliary
        GIM_CheckIsImm, /*MI*/0, /*Op*/6,
        // MIs[0] Operand 7
        GIM_CheckLiteralInt, /*MI*/0, /*Op*/7, GIMT_Encode8(0),
        GIM_CheckComplexPattern, /*MI*/0, /*Op*/4, /*Renderer*/GIMT_Encode2(0), GIMT_Encode2(GICP_gi_buf_soffset),
        // (SIbuffer_load_format_tfe:{ *:[v2i32] } v4i32:{ *:[v4i32] }:$rsrc, 0:{ *:[i32] }, 0:{ *:[i32] }, (BUFSOffset:{ *:[i32] } i32:{ *:[i32] }:$soffset), (timm:{ *:[i32] }):$offset, (timm:{ *:[i32] }):$auxiliary, 0:{ *:[i1] })  =>  (BUFFER_LOAD_FORMAT_X_TFE_OFFSET:{ *:[v2i32] } SReg_128:{ *:[v4i32] }:$rsrc, SCSrc_b32:{ *:[i32] }:$soffset, (timm:{ *:[i32] }):$offset, (extract_cpol:{ *:[i32] } ?:{ *:[i32] }:$auxiliary), (extract_swz:{ *:[i1] } ?:{ *:[i32] }:$auxiliary))
        GIR_BuildMI, /*InsnID*/0, /*Opcode*/GIMT_Encode2(AMDGPU::BUFFER_LOAD_FORMAT_X_TFE_OFFSET),
        GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/0, // DstI[vdata]
        GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/1, // rsrc
        GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/0, // soffset
        GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/5, // offset
        GIR_CustomOperandRenderer, /*InsnID*/0, /*OldInsnID*/0, /*OpIdx*/6, /*OperandRenderer*/GIMT_Encode2(GICR_renderExtractCPol), // auxiliary
        GIR_CustomOperandRenderer, /*InsnID*/0, /*OldInsnID*/0, /*OpIdx*/6, /*OperandRenderer*/GIMT_Encode2(GICR_renderExtractSWZ), // auxiliary
        GIR_MergeMemOperands, /*InsnID*/0, /*NumInsns*/1, /*MergeInsnID's*/0,
        GIR_ConstrainSelectedInstOperands, /*InsnID*/0,
        GIR_EraseFromParent, /*InsnID*/0,
        // GIR_Coverage, 3977,
        GIR_Done,
      // Label 6690: @491799
      GIM_Try, /*On fail goto*//*Label 6691*/ GIMT_Encode4(491878), // Rule ID 3981 //
        GIM_CheckConstantInt8, /*MI*/0, /*Op*/2, 0,
        GIM_CheckConstantInt8, /*MI*/0, /*Op*/3, 0,
        // MIs[0] offset
        GIM_CheckIsImm, /*MI*/0, /*Op*/5,
        // MIs[0] auxiliary
        GIM_CheckIsImm, /*MI*/0, /*Op*/6,
        // MIs[0] Operand 7
        GIM_CheckLiteralInt, /*MI*/0, /*Op*/7, GIMT_Encode8(0),
        GIM_CheckComplexPattern, /*MI*/0, /*Op*/4, /*Renderer*/GIMT_Encode2(0), GIMT_Encode2(GICP_gi_buf_soffset),
        // (SIbuffer_load_format_tfe:{ *:[v2i32] } v4i32:{ *:[v4i32] }:$rsrc, 0:{ *:[i32] }, 0:{ *:[i32] }, (BUFSOffset:{ *:[i32] } i32:{ *:[i32] }:$soffset), (timm:{ *:[i32] }):$offset, (timm:{ *:[i32] }):$auxiliary, 0:{ *:[i1] })  =>  (BUFFER_LOAD_FORMAT_X_TFE_VBUFFER_OFFSET:{ *:[v2i32] } SReg_128:{ *:[v4i32] }:$rsrc, SCSrc_b32:{ *:[i32] }:$soffset, (timm:{ *:[i32] }):$offset, (extract_cpol:{ *:[i32] } ?:{ *:[i32] }:$auxiliary), (extract_swz:{ *:[i1] } ?:{ *:[i32] }:$auxiliary))
        GIR_BuildMI, /*InsnID*/0, /*Opcode*/GIMT_Encode2(AMDGPU::BUFFER_LOAD_FORMAT_X_TFE_VBUFFER_OFFSET),
        GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/0, // DstI[vdata]
        GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/1, // rsrc
        GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/0, // soffset
        GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/5, // offset
        GIR_CustomOperandRenderer, /*InsnID*/0, /*OldInsnID*/0, /*OpIdx*/6, /*OperandRenderer*/GIMT_Encode2(GICR_renderExtractCPol), // auxiliary
        GIR_CustomOperandRenderer, /*InsnID*/0, /*OldInsnID*/0, /*OpIdx*/6, /*OperandRenderer*/GIMT_Encode2(GICR_renderExtractSWZ), // auxiliary
        GIR_MergeMemOperands, /*InsnID*/0, /*NumInsns*/1, /*MergeInsnID's*/0,
        GIR_ConstrainSelectedInstOperands, /*InsnID*/0,
        GIR_EraseFromParent, /*InsnID*/0,
        // GIR_Coverage, 3981,
        GIR_Done,
      // Label 6691: @491878
      GIM_Try, /*On fail goto*//*Label 6692*/ GIMT_Encode4(491960), // Rule ID 3978 //
        GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasUnrestrictedSOffset),
        GIM_CheckConstantInt8, /*MI*/0, /*Op*/2, 0,
        // MIs[0] offset
        GIM_CheckIsImm, /*MI*/0, /*Op*/5,
        // MIs[0] auxiliary
        GIM_CheckIsImm, /*MI*/0, /*Op*/6,
        // MIs[0] Operand 7
        GIM_CheckLiteralInt, /*MI*/0, /*Op*/7, GIMT_Encode8(0),
        GIM_CheckComplexPattern, /*MI*/0, /*Op*/4, /*Renderer*/GIMT_Encode2(0), GIMT_Encode2(GICP_gi_buf_soffset),
        // (SIbuffer_load_format_tfe:{ *:[v2i32] } v4i32:{ *:[v4i32] }:$rsrc, 0:{ *:[i32] }, i32:{ *:[i32] }:$voffset, (BUFSOffset:{ *:[i32] } i32:{ *:[i32] }:$soffset), (timm:{ *:[i32] }):$offset, (timm:{ *:[i32] }):$auxiliary, 0:{ *:[i1] })  =>  (BUFFER_LOAD_FORMAT_X_TFE_OFFEN:{ *:[v2i32] } VGPR_32:{ *:[i32] }:$voffset, SReg_128:{ *:[v4i32] }:$rsrc, SCSrc_b32:{ *:[i32] }:$soffset, (timm:{ *:[i32] }):$offset, (extract_cpol:{ *:[i32] } ?:{ *:[i32] }:$auxiliary), (extract_swz:{ *:[i1] } ?:{ *:[i32] }:$auxiliary))
        GIR_BuildMI, /*InsnID*/0, /*Opcode*/GIMT_Encode2(AMDGPU::BUFFER_LOAD_FORMAT_X_TFE_OFFEN),
        GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/0, // DstI[vdata]
        GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/3, // voffset
        GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/1, // rsrc
        GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/0, // soffset
        GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/5, // offset
        GIR_CustomOperandRenderer, /*InsnID*/0, /*OldInsnID*/0, /*OpIdx*/6, /*OperandRenderer*/GIMT_Encode2(GICR_renderExtractCPol), // auxiliary
        GIR_CustomOperandRenderer, /*InsnID*/0, /*OldInsnID*/0, /*OpIdx*/6, /*OperandRenderer*/GIMT_Encode2(GICR_renderExtractSWZ), // auxiliary
        GIR_MergeMemOperands, /*InsnID*/0, /*NumInsns*/1, /*MergeInsnID's*/0,
        GIR_ConstrainSelectedInstOperands, /*InsnID*/0,
        GIR_EraseFromParent, /*InsnID*/0,
        // GIR_Coverage, 3978,
        GIR_Done,
      // Label 6692: @491960
      GIM_Try, /*On fail goto*//*Label 6693*/ GIMT_Encode4(492039), // Rule ID 3982 //
        GIM_CheckConstantInt8, /*MI*/0, /*Op*/2, 0,
        // MIs[0] offset
        GIM_CheckIsImm, /*MI*/0, /*Op*/5,
        // MIs[0] auxiliary
        GIM_CheckIsImm, /*MI*/0, /*Op*/6,
        // MIs[0] Operand 7
        GIM_CheckLiteralInt, /*MI*/0, /*Op*/7, GIMT_Encode8(0),
        GIM_CheckComplexPattern, /*MI*/0, /*Op*/4, /*Renderer*/GIMT_Encode2(0), GIMT_Encode2(GICP_gi_buf_soffset),
        // (SIbuffer_load_format_tfe:{ *:[v2i32] } v4i32:{ *:[v4i32] }:$rsrc, 0:{ *:[i32] }, i32:{ *:[i32] }:$voffset, (BUFSOffset:{ *:[i32] } i32:{ *:[i32] }:$soffset), (timm:{ *:[i32] }):$offset, (timm:{ *:[i32] }):$auxiliary, 0:{ *:[i1] })  =>  (BUFFER_LOAD_FORMAT_X_TFE_VBUFFER_OFFEN:{ *:[v2i32] } VGPR_32:{ *:[i32] }:$voffset, SReg_128:{ *:[v4i32] }:$rsrc, SCSrc_b32:{ *:[i32] }:$soffset, (timm:{ *:[i32] }):$offset, (extract_cpol:{ *:[i32] } ?:{ *:[i32] }:$auxiliary), (extract_swz:{ *:[i1] } ?:{ *:[i32] }:$auxiliary))
        GIR_BuildMI, /*InsnID*/0, /*Opcode*/GIMT_Encode2(AMDGPU::BUFFER_LOAD_FORMAT_X_TFE_VBUFFER_OFFEN),
        GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/0, // DstI[vdata]
        GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/3, // voffset
        GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/1, // rsrc
        GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/0, // soffset
        GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/5, // offset
        GIR_CustomOperandRenderer, /*InsnID*/0, /*OldInsnID*/0, /*OpIdx*/6, /*OperandRenderer*/GIMT_Encode2(GICR_renderExtractCPol), // auxiliary
        GIR_CustomOperandRenderer, /*InsnID*/0, /*OldInsnID*/0, /*OpIdx*/6, /*OperandRenderer*/GIMT_Encode2(GICR_renderExtractSWZ), // auxiliary
        GIR_MergeMemOperands, /*InsnID*/0, /*NumInsns*/1, /*MergeInsnID's*/0,
        GIR_ConstrainSelectedInstOperands, /*InsnID*/0,
        GIR_EraseFromParent, /*InsnID*/0,
        // GIR_Coverage, 3982,
        GIR_Done,
      // Label 6693: @492039
      GIM_Try, /*On fail goto*//*Label 6694*/ GIMT_Encode4(492113), // Rule ID 3979 //
        GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasUnrestrictedSOffset),
        GIM_CheckConstantInt8, /*MI*/0, /*Op*/3, 0,
        // MIs[0] offset
        GIM_CheckIsImm, /*MI*/0, /*Op*/5,
        // MIs[0] auxiliary
        GIM_CheckIsImm, /*MI*/0, /*Op*/6,
        // MIs[0] Operand 7
        GIM_CheckIsImm, /*MI*/0, /*Op*/7,
        GIM_CheckComplexPattern, /*MI*/0, /*Op*/4, /*Renderer*/GIMT_Encode2(0), GIMT_Encode2(GICP_gi_buf_soffset),
        // (SIbuffer_load_format_tfe:{ *:[v2i32] } v4i32:{ *:[v4i32] }:$rsrc, i32:{ *:[i32] }:$vindex, 0:{ *:[i32] }, (BUFSOffset:{ *:[i32] } i32:{ *:[i32] }:$soffset), (timm:{ *:[i32] }):$offset, (timm:{ *:[i32] }):$auxiliary, (timm:{ *:[i1] }))  =>  (BUFFER_LOAD_FORMAT_X_TFE_IDXEN:{ *:[v2i32] } VGPR_32:{ *:[i32] }:$vindex, SReg_128:{ *:[v4i32] }:$rsrc, SCSrc_b32:{ *:[i32] }:$soffset, (timm:{ *:[i32] }):$offset, (extract_cpol:{ *:[i32] } ?:{ *:[i32] }:$auxiliary), (extract_swz:{ *:[i1] } ?:{ *:[i32] }:$auxiliary))
        GIR_BuildMI, /*InsnID*/0, /*Opcode*/GIMT_Encode2(AMDGPU::BUFFER_LOAD_FORMAT_X_TFE_IDXEN),
        GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/0, // DstI[vdata]
        GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/2, // vindex
        GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/1, // rsrc
        GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/0, // soffset
        GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/5, // offset
        GIR_CustomOperandRenderer, /*InsnID*/0, /*OldInsnID*/0, /*OpIdx*/6, /*OperandRenderer*/GIMT_Encode2(GICR_renderExtractCPol), // auxiliary
        GIR_CustomOperandRenderer, /*InsnID*/0, /*OldInsnID*/0, /*OpIdx*/6, /*OperandRenderer*/GIMT_Encode2(GICR_renderExtractSWZ), // auxiliary
        GIR_MergeMemOperands, /*InsnID*/0, /*NumInsns*/1, /*MergeInsnID's*/0,
        GIR_ConstrainSelectedInstOperands, /*InsnID*/0,
        GIR_EraseFromParent, /*InsnID*/0,
        // GIR_Coverage, 3979,
        GIR_Done,
      // Label 6694: @492113
      GIM_Try, /*On fail goto*//*Label 6695*/ GIMT_Encode4(492184), // Rule ID 3983 //
        GIM_CheckConstantInt8, /*MI*/0, /*Op*/3, 0,
        // MIs[0] offset
        GIM_CheckIsImm, /*MI*/0, /*Op*/5,
        // MIs[0] auxiliary
        GIM_CheckIsImm, /*MI*/0, /*Op*/6,
        // MIs[0] Operand 7
        GIM_CheckIsImm, /*MI*/0, /*Op*/7,
        GIM_CheckComplexPattern, /*MI*/0, /*Op*/4, /*Renderer*/GIMT_Encode2(0), GIMT_Encode2(GICP_gi_buf_soffset),
        // (SIbuffer_load_format_tfe:{ *:[v2i32] } v4i32:{ *:[v4i32] }:$rsrc, i32:{ *:[i32] }:$vindex, 0:{ *:[i32] }, (BUFSOffset:{ *:[i32] } i32:{ *:[i32] }:$soffset), (timm:{ *:[i32] }):$offset, (timm:{ *:[i32] }):$auxiliary, (timm:{ *:[i1] }))  =>  (BUFFER_LOAD_FORMAT_X_TFE_VBUFFER_IDXEN:{ *:[v2i32] } VGPR_32:{ *:[i32] }:$vindex, SReg_128:{ *:[v4i32] }:$rsrc, SCSrc_b32:{ *:[i32] }:$soffset, (timm:{ *:[i32] }):$offset, (extract_cpol:{ *:[i32] } ?:{ *:[i32] }:$auxiliary), (extract_swz:{ *:[i1] } ?:{ *:[i32] }:$auxiliary))
        GIR_BuildMI, /*InsnID*/0, /*Opcode*/GIMT_Encode2(AMDGPU::BUFFER_LOAD_FORMAT_X_TFE_VBUFFER_IDXEN),
        GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/0, // DstI[vdata]
        GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/2, // vindex
        GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/1, // rsrc
        GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/0, // soffset
        GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/5, // offset
        GIR_CustomOperandRenderer, /*InsnID*/0, /*OldInsnID*/0, /*OpIdx*/6, /*OperandRenderer*/GIMT_Encode2(GICR_renderExtractCPol), // auxiliary
        GIR_CustomOperandRenderer, /*InsnID*/0, /*OldInsnID*/0, /*OpIdx*/6, /*OperandRenderer*/GIMT_Encode2(GICR_renderExtractSWZ), // auxiliary
        GIR_MergeMemOperands, /*InsnID*/0, /*NumInsns*/1, /*MergeInsnID's*/0,
        GIR_ConstrainSelectedInstOperands, /*InsnID*/0,
        GIR_EraseFromParent, /*InsnID*/0,
        // GIR_Coverage, 3983,
        GIR_Done,
      // Label 6695: @492184
      GIM_Try, /*On fail goto*//*Label 6696*/ GIMT_Encode4(492294), // Rule ID 3980 //
        GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasUnrestrictedSOffset),
        // MIs[0] offset
        GIM_CheckIsImm, /*MI*/0, /*Op*/5,
        // MIs[0] auxiliary
        GIM_CheckIsImm, /*MI*/0, /*Op*/6,
        // MIs[0] Operand 7
        GIM_CheckIsImm, /*MI*/0, /*Op*/7,
        GIM_CheckComplexPattern, /*MI*/0, /*Op*/4, /*Renderer*/GIMT_Encode2(0), GIMT_Encode2(GICP_gi_buf_soffset),
        // (SIbuffer_load_format_tfe:{ *:[v2i32] } v4i32:{ *:[v4i32] }:$rsrc, i32:{ *:[i32] }:$vindex, i32:{ *:[i32] }:$voffset, (BUFSOffset:{ *:[i32] } i32:{ *:[i32] }:$soffset), (timm:{ *:[i32] }):$offset, (timm:{ *:[i32] }):$auxiliary, (timm:{ *:[i1] }))  =>  (BUFFER_LOAD_FORMAT_X_TFE_BOTHEN:{ *:[v2i32] } (REG_SEQUENCE:{ *:[i64] } VReg_64:{ *:[i32] }, VGPR_32:{ *:[i32] }:$vindex, sub0:{ *:[i32] }, VGPR_32:{ *:[i32] }:$voffset, sub1:{ *:[i32] }), SReg_128:{ *:[v4i32] }:$rsrc, SCSrc_b32:{ *:[i32] }:$soffset, (timm:{ *:[i32] }):$offset, (extract_cpol:{ *:[i32] } ?:{ *:[i32] }:$auxiliary), (extract_swz:{ *:[i1] } ?:{ *:[i32] }:$auxiliary))
        GIR_MakeTempReg, /*TempRegID*/0, /*TypeID*/GILLT_s64,
        GIR_BuildMI, /*InsnID*/1, /*Opcode*/GIMT_Encode2(TargetOpcode::REG_SEQUENCE),
        GIR_AddTempRegister, /*InsnID*/1, /*TempRegID*/0, /*TempRegFlags*/GIMT_Encode2(RegState::Define),
        GIR_Copy, /*NewInsnID*/1, /*OldInsnID*/0, /*OpIdx*/2, // vindex
        GIR_AddImm8, /*InsnID*/1, /*SubRegIndex*/3,
        GIR_Copy, /*NewInsnID*/1, /*OldInsnID*/0, /*OpIdx*/3, // voffset
        GIR_AddImm8, /*InsnID*/1, /*SubRegIndex*/11,
        GIR_ConstrainOperandRC, /*InsnID*/1, /*Op*/0, GIMT_Encode2(AMDGPU::VReg_64RegClassID),
        GIR_ConstrainOperandRC, /*InsnID*/1, /*Op*/1, GIMT_Encode2(AMDGPU::VGPR_32RegClassID),
        GIR_ConstrainOperandRC, /*InsnID*/1, /*Op*/3, GIMT_Encode2(AMDGPU::VGPR_32RegClassID),
        GIR_BuildMI, /*InsnID*/0, /*Opcode*/GIMT_Encode2(AMDGPU::BUFFER_LOAD_FORMAT_X_TFE_BOTHEN),
        GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/0, // DstI[vdata]
        GIR_AddSimpleTempRegister, /*InsnID*/0, /*TempRegID*/0,
        GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/1, // rsrc
        GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/0, // soffset
        GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/5, // offset
        GIR_CustomOperandRenderer, /*InsnID*/0, /*OldInsnID*/0, /*OpIdx*/6, /*OperandRenderer*/GIMT_Encode2(GICR_renderExtractCPol), // auxiliary
        GIR_CustomOperandRenderer, /*InsnID*/0, /*OldInsnID*/0, /*OpIdx*/6, /*OperandRenderer*/GIMT_Encode2(GICR_renderExtractSWZ), // auxiliary
        GIR_MergeMemOperands, /*InsnID*/0, /*NumInsns*/1, /*MergeInsnID's*/0,
        GIR_ConstrainSelectedInstOperands, /*InsnID*/0,
        GIR_EraseFromParent, /*InsnID*/0,
        // GIR_Coverage, 3980,
        GIR_Done,
      // Label 6696: @492294
      GIM_Try, /*On fail goto*//*Label 6697*/ GIMT_Encode4(492401), // Rule ID 3984 //
        // MIs[0] offset
        GIM_CheckIsImm, /*MI*/0, /*Op*/5,
        // MIs[0] auxiliary
        GIM_CheckIsImm, /*MI*/0, /*Op*/6,
        // MIs[0] Operand 7
        GIM_CheckIsImm, /*MI*/0, /*Op*/7,
        GIM_CheckComplexPattern, /*MI*/0, /*Op*/4, /*Renderer*/GIMT_Encode2(0), GIMT_Encode2(GICP_gi_buf_soffset),
        // (SIbuffer_load_format_tfe:{ *:[v2i32] } v4i32:{ *:[v4i32] }:$rsrc, i32:{ *:[i32] }:$vindex, i32:{ *:[i32] }:$voffset, (BUFSOffset:{ *:[i32] } i32:{ *:[i32] }:$soffset), (timm:{ *:[i32] }):$offset, (timm:{ *:[i32] }):$auxiliary, (timm:{ *:[i1] }))  =>  (BUFFER_LOAD_FORMAT_X_TFE_VBUFFER_BOTHEN:{ *:[v2i32] } (REG_SEQUENCE:{ *:[i64] } VReg_64:{ *:[i32] }, VGPR_32:{ *:[i32] }:$vindex, sub0:{ *:[i32] }, VGPR_32:{ *:[i32] }:$voffset, sub1:{ *:[i32] }), SReg_128:{ *:[v4i32] }:$rsrc, SCSrc_b32:{ *:[i32] }:$soffset, (timm:{ *:[i32] }):$offset, (extract_cpol:{ *:[i32] } ?:{ *:[i32] }:$auxiliary), (extract_swz:{ *:[i1] } ?:{ *:[i32] }:$auxiliary))
        GIR_MakeTempReg, /*TempRegID*/0, /*TypeID*/GILLT_s64,
        GIR_BuildMI, /*InsnID*/1, /*Opcode*/GIMT_Encode2(TargetOpcode::REG_SEQUENCE),
        GIR_AddTempRegister, /*InsnID*/1, /*TempRegID*/0, /*TempRegFlags*/GIMT_Encode2(RegState::Define),
        GIR_Copy, /*NewInsnID*/1, /*OldInsnID*/0, /*OpIdx*/2, // vindex
        GIR_AddImm8, /*InsnID*/1, /*SubRegIndex*/3,
        GIR_Copy, /*NewInsnID*/1, /*OldInsnID*/0, /*OpIdx*/3, // voffset
        GIR_AddImm8, /*InsnID*/1, /*SubRegIndex*/11,
        GIR_ConstrainOperandRC, /*InsnID*/1, /*Op*/0, GIMT_Encode2(AMDGPU::VReg_64RegClassID),
        GIR_ConstrainOperandRC, /*InsnID*/1, /*Op*/1, GIMT_Encode2(AMDGPU::VGPR_32RegClassID),
        GIR_ConstrainOperandRC, /*InsnID*/1, /*Op*/3, GIMT_Encode2(AMDGPU::VGPR_32RegClassID),
        GIR_BuildMI, /*InsnID*/0, /*Opcode*/GIMT_Encode2(AMDGPU::BUFFER_LOAD_FORMAT_X_TFE_VBUFFER_BOTHEN),
        GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/0, // DstI[vdata]
        GIR_AddSimpleTempRegister, /*InsnID*/0, /*TempRegID*/0,
        GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/1, // rsrc
        GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/0, // soffset
        GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/5, // offset
        GIR_CustomOperandRenderer, /*InsnID*/0, /*OldInsnID*/0, /*OpIdx*/6, /*OperandRenderer*/GIMT_Encode2(GICR_renderExtractCPol), // auxiliary
        GIR_CustomOperandRenderer, /*InsnID*/0, /*OldInsnID*/0, /*OpIdx*/6, /*OperandRenderer*/GIMT_Encode2(GICR_renderExtractSWZ), // auxiliary
        GIR_MergeMemOperands, /*InsnID*/0, /*NumInsns*/1, /*MergeInsnID's*/0,
        GIR_ConstrainSelectedInstOperands, /*InsnID*/0,
        GIR_EraseFromParent, /*InsnID*/0,
        // GIR_Coverage, 3984,
        GIR_Done,
      // Label 6697: @492401
      GIM_Reject,
    // Label 6689: @492402
    GIM_Reject,
    // Label 6685: @492403
    GIM_Try, /*On fail goto*//*Label 6698*/ GIMT_Encode4(493114),
      GIM_CheckType, /*MI*/0, /*Op*/1, /*Type*/GILLT_v4s32,
      GIM_CheckType, /*MI*/0, /*Op*/2, /*Type*/GILLT_s32,
      GIM_CheckType, /*MI*/0, /*Op*/3, /*Type*/GILLT_s32,
      GIM_CheckType, /*MI*/0, /*Op*/4, /*Type*/GILLT_s32,
      GIM_CheckRegBankForClass, /*MI*/0, /*Op*/0, /*RC*/GIMT_Encode2(AMDGPU::AV_96RegClassID),
      GIM_Try, /*On fail goto*//*Label 6699*/ GIMT_Encode4(492511), // Rule ID 3985 //
        GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasUnrestrictedSOffset),
        GIM_CheckConstantInt8, /*MI*/0, /*Op*/2, 0,
        GIM_CheckConstantInt8, /*MI*/0, /*Op*/3, 0,
        // MIs[0] offset
        GIM_CheckIsImm, /*MI*/0, /*Op*/5,
        // MIs[0] auxiliary
        GIM_CheckIsImm, /*MI*/0, /*Op*/6,
        // MIs[0] Operand 7
        GIM_CheckLiteralInt, /*MI*/0, /*Op*/7, GIMT_Encode8(0),
        GIM_CheckComplexPattern, /*MI*/0, /*Op*/4, /*Renderer*/GIMT_Encode2(0), GIMT_Encode2(GICP_gi_buf_soffset),
        // (SIbuffer_load_format_tfe:{ *:[v3i32] } v4i32:{ *:[v4i32] }:$rsrc, 0:{ *:[i32] }, 0:{ *:[i32] }, (BUFSOffset:{ *:[i32] } i32:{ *:[i32] }:$soffset), (timm:{ *:[i32] }):$offset, (timm:{ *:[i32] }):$auxiliary, 0:{ *:[i1] })  =>  (BUFFER_LOAD_FORMAT_XY_TFE_OFFSET:{ *:[v3i32] } SReg_128:{ *:[v4i32] }:$rsrc, SCSrc_b32:{ *:[i32] }:$soffset, (timm:{ *:[i32] }):$offset, (extract_cpol:{ *:[i32] } ?:{ *:[i32] }:$auxiliary), (extract_swz:{ *:[i1] } ?:{ *:[i32] }:$auxiliary))
        GIR_BuildMI, /*InsnID*/0, /*Opcode*/GIMT_Encode2(AMDGPU::BUFFER_LOAD_FORMAT_XY_TFE_OFFSET),
        GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/0, // DstI[vdata]
        GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/1, // rsrc
        GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/0, // soffset
        GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/5, // offset
        GIR_CustomOperandRenderer, /*InsnID*/0, /*OldInsnID*/0, /*OpIdx*/6, /*OperandRenderer*/GIMT_Encode2(GICR_renderExtractCPol), // auxiliary
        GIR_CustomOperandRenderer, /*InsnID*/0, /*OldInsnID*/0, /*OpIdx*/6, /*OperandRenderer*/GIMT_Encode2(GICR_renderExtractSWZ), // auxiliary
        GIR_MergeMemOperands, /*InsnID*/0, /*NumInsns*/1, /*MergeInsnID's*/0,
        GIR_ConstrainSelectedInstOperands, /*InsnID*/0,
        GIR_EraseFromParent, /*InsnID*/0,
        // GIR_Coverage, 3985,
        GIR_Done,
      // Label 6699: @492511
      GIM_Try, /*On fail goto*//*Label 6700*/ GIMT_Encode4(492590), // Rule ID 3989 //
        GIM_CheckConstantInt8, /*MI*/0, /*Op*/2, 0,
        GIM_CheckConstantInt8, /*MI*/0, /*Op*/3, 0,
        // MIs[0] offset
        GIM_CheckIsImm, /*MI*/0, /*Op*/5,
        // MIs[0] auxiliary
        GIM_CheckIsImm, /*MI*/0, /*Op*/6,
        // MIs[0] Operand 7
        GIM_CheckLiteralInt, /*MI*/0, /*Op*/7, GIMT_Encode8(0),
        GIM_CheckComplexPattern, /*MI*/0, /*Op*/4, /*Renderer*/GIMT_Encode2(0), GIMT_Encode2(GICP_gi_buf_soffset),
        // (SIbuffer_load_format_tfe:{ *:[v3i32] } v4i32:{ *:[v4i32] }:$rsrc, 0:{ *:[i32] }, 0:{ *:[i32] }, (BUFSOffset:{ *:[i32] } i32:{ *:[i32] }:$soffset), (timm:{ *:[i32] }):$offset, (timm:{ *:[i32] }):$auxiliary, 0:{ *:[i1] })  =>  (BUFFER_LOAD_FORMAT_XY_TFE_VBUFFER_OFFSET:{ *:[v3i32] } SReg_128:{ *:[v4i32] }:$rsrc, SCSrc_b32:{ *:[i32] }:$soffset, (timm:{ *:[i32] }):$offset, (extract_cpol:{ *:[i32] } ?:{ *:[i32] }:$auxiliary), (extract_swz:{ *:[i1] } ?:{ *:[i32] }:$auxiliary))
        GIR_BuildMI, /*InsnID*/0, /*Opcode*/GIMT_Encode2(AMDGPU::BUFFER_LOAD_FORMAT_XY_TFE_VBUFFER_OFFSET),
        GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/0, // DstI[vdata]
        GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/1, // rsrc
        GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/0, // soffset
        GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/5, // offset
        GIR_CustomOperandRenderer, /*InsnID*/0, /*OldInsnID*/0, /*OpIdx*/6, /*OperandRenderer*/GIMT_Encode2(GICR_renderExtractCPol), // auxiliary
        GIR_CustomOperandRenderer, /*InsnID*/0, /*OldInsnID*/0, /*OpIdx*/6, /*OperandRenderer*/GIMT_Encode2(GICR_renderExtractSWZ), // auxiliary
        GIR_MergeMemOperands, /*InsnID*/0, /*NumInsns*/1, /*MergeInsnID's*/0,
        GIR_ConstrainSelectedInstOperands, /*InsnID*/0,
        GIR_EraseFromParent, /*InsnID*/0,
        // GIR_Coverage, 3989,
        GIR_Done,
      // Label 6700: @492590
      GIM_Try, /*On fail goto*//*Label 6701*/ GIMT_Encode4(492672), // Rule ID 3986 //
        GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasUnrestrictedSOffset),
        GIM_CheckConstantInt8, /*MI*/0, /*Op*/2, 0,
        // MIs[0] offset
        GIM_CheckIsImm, /*MI*/0, /*Op*/5,
        // MIs[0] auxiliary
        GIM_CheckIsImm, /*MI*/0, /*Op*/6,
        // MIs[0] Operand 7
        GIM_CheckLiteralInt, /*MI*/0, /*Op*/7, GIMT_Encode8(0),
        GIM_CheckComplexPattern, /*MI*/0, /*Op*/4, /*Renderer*/GIMT_Encode2(0), GIMT_Encode2(GICP_gi_buf_soffset),
        // (SIbuffer_load_format_tfe:{ *:[v3i32] } v4i32:{ *:[v4i32] }:$rsrc, 0:{ *:[i32] }, i32:{ *:[i32] }:$voffset, (BUFSOffset:{ *:[i32] } i32:{ *:[i32] }:$soffset), (timm:{ *:[i32] }):$offset, (timm:{ *:[i32] }):$auxiliary, 0:{ *:[i1] })  =>  (BUFFER_LOAD_FORMAT_XY_TFE_OFFEN:{ *:[v3i32] } VGPR_32:{ *:[i32] }:$voffset, SReg_128:{ *:[v4i32] }:$rsrc, SCSrc_b32:{ *:[i32] }:$soffset, (timm:{ *:[i32] }):$offset, (extract_cpol:{ *:[i32] } ?:{ *:[i32] }:$auxiliary), (extract_swz:{ *:[i1] } ?:{ *:[i32] }:$auxiliary))
        GIR_BuildMI, /*InsnID*/0, /*Opcode*/GIMT_Encode2(AMDGPU::BUFFER_LOAD_FORMAT_XY_TFE_OFFEN),
        GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/0, // DstI[vdata]
        GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/3, // voffset
        GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/1, // rsrc
        GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/0, // soffset
        GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/5, // offset
        GIR_CustomOperandRenderer, /*InsnID*/0, /*OldInsnID*/0, /*OpIdx*/6, /*OperandRenderer*/GIMT_Encode2(GICR_renderExtractCPol), // auxiliary
        GIR_CustomOperandRenderer, /*InsnID*/0, /*OldInsnID*/0, /*OpIdx*/6, /*OperandRenderer*/GIMT_Encode2(GICR_renderExtractSWZ), // auxiliary
        GIR_MergeMemOperands, /*InsnID*/0, /*NumInsns*/1, /*MergeInsnID's*/0,
        GIR_ConstrainSelectedInstOperands, /*InsnID*/0,
        GIR_EraseFromParent, /*InsnID*/0,
        // GIR_Coverage, 3986,
        GIR_Done,
      // Label 6701: @492672
      GIM_Try, /*On fail goto*//*Label 6702*/ GIMT_Encode4(492751), // Rule ID 3990 //
        GIM_CheckConstantInt8, /*MI*/0, /*Op*/2, 0,
        // MIs[0] offset
        GIM_CheckIsImm, /*MI*/0, /*Op*/5,
        // MIs[0] auxiliary
        GIM_CheckIsImm, /*MI*/0, /*Op*/6,
        // MIs[0] Operand 7
        GIM_CheckLiteralInt, /*MI*/0, /*Op*/7, GIMT_Encode8(0),
        GIM_CheckComplexPattern, /*MI*/0, /*Op*/4, /*Renderer*/GIMT_Encode2(0), GIMT_Encode2(GICP_gi_buf_soffset),
        // (SIbuffer_load_format_tfe:{ *:[v3i32] } v4i32:{ *:[v4i32] }:$rsrc, 0:{ *:[i32] }, i32:{ *:[i32] }:$voffset, (BUFSOffset:{ *:[i32] } i32:{ *:[i32] }:$soffset), (timm:{ *:[i32] }):$offset, (timm:{ *:[i32] }):$auxiliary, 0:{ *:[i1] })  =>  (BUFFER_LOAD_FORMAT_XY_TFE_VBUFFER_OFFEN:{ *:[v3i32] } VGPR_32:{ *:[i32] }:$voffset, SReg_128:{ *:[v4i32] }:$rsrc, SCSrc_b32:{ *:[i32] }:$soffset, (timm:{ *:[i32] }):$offset, (extract_cpol:{ *:[i32] } ?:{ *:[i32] }:$auxiliary), (extract_swz:{ *:[i1] } ?:{ *:[i32] }:$auxiliary))
        GIR_BuildMI, /*InsnID*/0, /*Opcode*/GIMT_Encode2(AMDGPU::BUFFER_LOAD_FORMAT_XY_TFE_VBUFFER_OFFEN),
        GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/0, // DstI[vdata]
        GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/3, // voffset
        GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/1, // rsrc
        GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/0, // soffset
        GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/5, // offset
        GIR_CustomOperandRenderer, /*InsnID*/0, /*OldInsnID*/0, /*OpIdx*/6, /*OperandRenderer*/GIMT_Encode2(GICR_renderExtractCPol), // auxiliary
        GIR_CustomOperandRenderer, /*InsnID*/0, /*OldInsnID*/0, /*OpIdx*/6, /*OperandRenderer*/GIMT_Encode2(GICR_renderExtractSWZ), // auxiliary
        GIR_MergeMemOperands, /*InsnID*/0, /*NumInsns*/1, /*MergeInsnID's*/0,
        GIR_ConstrainSelectedInstOperands, /*InsnID*/0,
        GIR_EraseFromParent, /*InsnID*/0,
        // GIR_Coverage, 3990,
        GIR_Done,
      // Label 6702: @492751
      GIM_Try, /*On fail goto*//*Label 6703*/ GIMT_Encode4(492825), // Rule ID 3987 //
        GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasUnrestrictedSOffset),
        GIM_CheckConstantInt8, /*MI*/0, /*Op*/3, 0,
        // MIs[0] offset
        GIM_CheckIsImm, /*MI*/0, /*Op*/5,
        // MIs[0] auxiliary
        GIM_CheckIsImm, /*MI*/0, /*Op*/6,
        // MIs[0] Operand 7
        GIM_CheckIsImm, /*MI*/0, /*Op*/7,
        GIM_CheckComplexPattern, /*MI*/0, /*Op*/4, /*Renderer*/GIMT_Encode2(0), GIMT_Encode2(GICP_gi_buf_soffset),
        // (SIbuffer_load_format_tfe:{ *:[v3i32] } v4i32:{ *:[v4i32] }:$rsrc, i32:{ *:[i32] }:$vindex, 0:{ *:[i32] }, (BUFSOffset:{ *:[i32] } i32:{ *:[i32] }:$soffset), (timm:{ *:[i32] }):$offset, (timm:{ *:[i32] }):$auxiliary, (timm:{ *:[i1] }))  =>  (BUFFER_LOAD_FORMAT_XY_TFE_IDXEN:{ *:[v3i32] } VGPR_32:{ *:[i32] }:$vindex, SReg_128:{ *:[v4i32] }:$rsrc, SCSrc_b32:{ *:[i32] }:$soffset, (timm:{ *:[i32] }):$offset, (extract_cpol:{ *:[i32] } ?:{ *:[i32] }:$auxiliary), (extract_swz:{ *:[i1] } ?:{ *:[i32] }:$auxiliary))
        GIR_BuildMI, /*InsnID*/0, /*Opcode*/GIMT_Encode2(AMDGPU::BUFFER_LOAD_FORMAT_XY_TFE_IDXEN),
        GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/0, // DstI[vdata]
        GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/2, // vindex
        GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/1, // rsrc
        GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/0, // soffset
        GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/5, // offset
        GIR_CustomOperandRenderer, /*InsnID*/0, /*OldInsnID*/0, /*OpIdx*/6, /*OperandRenderer*/GIMT_Encode2(GICR_renderExtractCPol), // auxiliary
        GIR_CustomOperandRenderer, /*InsnID*/0, /*OldInsnID*/0, /*OpIdx*/6, /*OperandRenderer*/GIMT_Encode2(GICR_renderExtractSWZ), // auxiliary
        GIR_MergeMemOperands, /*InsnID*/0, /*NumInsns*/1, /*MergeInsnID's*/0,
        GIR_ConstrainSelectedInstOperands, /*InsnID*/0,
        GIR_EraseFromParent, /*InsnID*/0,
        // GIR_Coverage, 3987,
        GIR_Done,
      // Label 6703: @492825
      GIM_Try, /*On fail goto*//*Label 6704*/ GIMT_Encode4(492896), // Rule ID 3991 //
        GIM_CheckConstantInt8, /*MI*/0, /*Op*/3, 0,
        // MIs[0] offset
        GIM_CheckIsImm, /*MI*/0, /*Op*/5,
        // MIs[0] auxiliary
        GIM_CheckIsImm, /*MI*/0, /*Op*/6,
        // MIs[0] Operand 7
        GIM_CheckIsImm, /*MI*/0, /*Op*/7,
        GIM_CheckComplexPattern, /*MI*/0, /*Op*/4, /*Renderer*/GIMT_Encode2(0), GIMT_Encode2(GICP_gi_buf_soffset),
        // (SIbuffer_load_format_tfe:{ *:[v3i32] } v4i32:{ *:[v4i32] }:$rsrc, i32:{ *:[i32] }:$vindex, 0:{ *:[i32] }, (BUFSOffset:{ *:[i32] } i32:{ *:[i32] }:$soffset), (timm:{ *:[i32] }):$offset, (timm:{ *:[i32] }):$auxiliary, (timm:{ *:[i1] }))  =>  (BUFFER_LOAD_FORMAT_XY_TFE_VBUFFER_IDXEN:{ *:[v3i32] } VGPR_32:{ *:[i32] }:$vindex, SReg_128:{ *:[v4i32] }:$rsrc, SCSrc_b32:{ *:[i32] }:$soffset, (timm:{ *:[i32] }):$offset, (extract_cpol:{ *:[i32] } ?:{ *:[i32] }:$auxiliary), (extract_swz:{ *:[i1] } ?:{ *:[i32] }:$auxiliary))
        GIR_BuildMI, /*InsnID*/0, /*Opcode*/GIMT_Encode2(AMDGPU::BUFFER_LOAD_FORMAT_XY_TFE_VBUFFER_IDXEN),
        GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/0, // DstI[vdata]
        GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/2, // vindex
        GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/1, // rsrc
        GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/0, // soffset
        GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/5, // offset
        GIR_CustomOperandRenderer, /*InsnID*/0, /*OldInsnID*/0, /*OpIdx*/6, /*OperandRenderer*/GIMT_Encode2(GICR_renderExtractCPol), // auxiliary
        GIR_CustomOperandRenderer, /*InsnID*/0, /*OldInsnID*/0, /*OpIdx*/6, /*OperandRenderer*/GIMT_Encode2(GICR_renderExtractSWZ), // auxiliary
        GIR_MergeMemOperands, /*InsnID*/0, /*NumInsns*/1, /*MergeInsnID's*/0,
        GIR_ConstrainSelectedInstOperands, /*InsnID*/0,
        GIR_EraseFromParent, /*InsnID*/0,
        // GIR_Coverage, 3991,
        GIR_Done,
      // Label 6704: @492896
      GIM_Try, /*On fail goto*//*Label 6705*/ GIMT_Encode4(493006), // Rule ID 3988 //
        GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasUnrestrictedSOffset),
        // MIs[0] offset
        GIM_CheckIsImm, /*MI*/0, /*Op*/5,
        // MIs[0] auxiliary
        GIM_CheckIsImm, /*MI*/0, /*Op*/6,
        // MIs[0] Operand 7
        GIM_CheckIsImm, /*MI*/0, /*Op*/7,
        GIM_CheckComplexPattern, /*MI*/0, /*Op*/4, /*Renderer*/GIMT_Encode2(0), GIMT_Encode2(GICP_gi_buf_soffset),
        // (SIbuffer_load_format_tfe:{ *:[v3i32] } v4i32:{ *:[v4i32] }:$rsrc, i32:{ *:[i32] }:$vindex, i32:{ *:[i32] }:$voffset, (BUFSOffset:{ *:[i32] } i32:{ *:[i32] }:$soffset), (timm:{ *:[i32] }):$offset, (timm:{ *:[i32] }):$auxiliary, (timm:{ *:[i1] }))  =>  (BUFFER_LOAD_FORMAT_XY_TFE_BOTHEN:{ *:[v3i32] } (REG_SEQUENCE:{ *:[i64] } VReg_64:{ *:[i32] }, VGPR_32:{ *:[i32] }:$vindex, sub0:{ *:[i32] }, VGPR_32:{ *:[i32] }:$voffset, sub1:{ *:[i32] }), SReg_128:{ *:[v4i32] }:$rsrc, SCSrc_b32:{ *:[i32] }:$soffset, (timm:{ *:[i32] }):$offset, (extract_cpol:{ *:[i32] } ?:{ *:[i32] }:$auxiliary), (extract_swz:{ *:[i1] } ?:{ *:[i32] }:$auxiliary))
        GIR_MakeTempReg, /*TempRegID*/0, /*TypeID*/GILLT_s64,
        GIR_BuildMI, /*InsnID*/1, /*Opcode*/GIMT_Encode2(TargetOpcode::REG_SEQUENCE),
        GIR_AddTempRegister, /*InsnID*/1, /*TempRegID*/0, /*TempRegFlags*/GIMT_Encode2(RegState::Define),
        GIR_Copy, /*NewInsnID*/1, /*OldInsnID*/0, /*OpIdx*/2, // vindex
        GIR_AddImm8, /*InsnID*/1, /*SubRegIndex*/3,
        GIR_Copy, /*NewInsnID*/1, /*OldInsnID*/0, /*OpIdx*/3, // voffset
        GIR_AddImm8, /*InsnID*/1, /*SubRegIndex*/11,
        GIR_ConstrainOperandRC, /*InsnID*/1, /*Op*/0, GIMT_Encode2(AMDGPU::VReg_64RegClassID),
        GIR_ConstrainOperandRC, /*InsnID*/1, /*Op*/1, GIMT_Encode2(AMDGPU::VGPR_32RegClassID),
        GIR_ConstrainOperandRC, /*InsnID*/1, /*Op*/3, GIMT_Encode2(AMDGPU::VGPR_32RegClassID),
        GIR_BuildMI, /*InsnID*/0, /*Opcode*/GIMT_Encode2(AMDGPU::BUFFER_LOAD_FORMAT_XY_TFE_BOTHEN),
        GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/0, // DstI[vdata]
        GIR_AddSimpleTempRegister, /*InsnID*/0, /*TempRegID*/0,
        GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/1, // rsrc
        GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/0, // soffset
        GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/5, // offset
        GIR_CustomOperandRenderer, /*InsnID*/0, /*OldInsnID*/0, /*OpIdx*/6, /*OperandRenderer*/GIMT_Encode2(GICR_renderExtractCPol), // auxiliary
        GIR_CustomOperandRenderer, /*InsnID*/0, /*OldInsnID*/0, /*OpIdx*/6, /*OperandRenderer*/GIMT_Encode2(GICR_renderExtractSWZ), // auxiliary
        GIR_MergeMemOperands, /*InsnID*/0, /*NumInsns*/1, /*MergeInsnID's*/0,
        GIR_ConstrainSelectedInstOperands, /*InsnID*/0,
        GIR_EraseFromParent, /*InsnID*/0,
        // GIR_Coverage, 3988,
        GIR_Done,
      // Label 6705: @493006
      GIM_Try, /*On fail goto*//*Label 6706*/ GIMT_Encode4(493113), // Rule ID 3992 //
        // MIs[0] offset
        GIM_CheckIsImm, /*MI*/0, /*Op*/5,
        // MIs[0] auxiliary
        GIM_CheckIsImm, /*MI*/0, /*Op*/6,
        // MIs[0] Operand 7
        GIM_CheckIsImm, /*MI*/0, /*Op*/7,
        GIM_CheckComplexPattern, /*MI*/0, /*Op*/4, /*Renderer*/GIMT_Encode2(0), GIMT_Encode2(GICP_gi_buf_soffset),
        // (SIbuffer_load_format_tfe:{ *:[v3i32] } v4i32:{ *:[v4i32] }:$rsrc, i32:{ *:[i32] }:$vindex, i32:{ *:[i32] }:$voffset, (BUFSOffset:{ *:[i32] } i32:{ *:[i32] }:$soffset), (timm:{ *:[i32] }):$offset, (timm:{ *:[i32] }):$auxiliary, (timm:{ *:[i1] }))  =>  (BUFFER_LOAD_FORMAT_XY_TFE_VBUFFER_BOTHEN:{ *:[v3i32] } (REG_SEQUENCE:{ *:[i64] } VReg_64:{ *:[i32] }, VGPR_32:{ *:[i32] }:$vindex, sub0:{ *:[i32] }, VGPR_32:{ *:[i32] }:$voffset, sub1:{ *:[i32] }), SReg_128:{ *:[v4i32] }:$rsrc, SCSrc_b32:{ *:[i32] }:$soffset, (timm:{ *:[i32] }):$offset, (extract_cpol:{ *:[i32] } ?:{ *:[i32] }:$auxiliary), (extract_swz:{ *:[i1] } ?:{ *:[i32] }:$auxiliary))
        GIR_MakeTempReg, /*TempRegID*/0, /*TypeID*/GILLT_s64,
        GIR_BuildMI, /*InsnID*/1, /*Opcode*/GIMT_Encode2(TargetOpcode::REG_SEQUENCE),
        GIR_AddTempRegister, /*InsnID*/1, /*TempRegID*/0, /*TempRegFlags*/GIMT_Encode2(RegState::Define),
        GIR_Copy, /*NewInsnID*/1, /*OldInsnID*/0, /*OpIdx*/2, // vindex
        GIR_AddImm8, /*InsnID*/1, /*SubRegIndex*/3,
        GIR_Copy, /*NewInsnID*/1, /*OldInsnID*/0, /*OpIdx*/3, // voffset
        GIR_AddImm8, /*InsnID*/1, /*SubRegIndex*/11,
        GIR_ConstrainOperandRC, /*InsnID*/1, /*Op*/0, GIMT_Encode2(AMDGPU::VReg_64RegClassID),
        GIR_ConstrainOperandRC, /*InsnID*/1, /*Op*/1, GIMT_Encode2(AMDGPU::VGPR_32RegClassID),
        GIR_ConstrainOperandRC, /*InsnID*/1, /*Op*/3, GIMT_Encode2(AMDGPU::VGPR_32RegClassID),
        GIR_BuildMI, /*InsnID*/0, /*Opcode*/GIMT_Encode2(AMDGPU::BUFFER_LOAD_FORMAT_XY_TFE_VBUFFER_BOTHEN),
        GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/0, // DstI[vdata]
        GIR_AddSimpleTempRegister, /*InsnID*/0, /*TempRegID*/0,
        GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/1, // rsrc
        GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/0, // soffset
        GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/5, // offset
        GIR_CustomOperandRenderer, /*InsnID*/0, /*OldInsnID*/0, /*OpIdx*/6, /*OperandRenderer*/GIMT_Encode2(GICR_renderExtractCPol), // auxiliary
        GIR_CustomOperandRenderer, /*InsnID*/0, /*OldInsnID*/0, /*OpIdx*/6, /*OperandRenderer*/GIMT_Encode2(GICR_renderExtractSWZ), // auxiliary
        GIR_MergeMemOperands, /*InsnID*/0, /*NumInsns*/1, /*MergeInsnID's*/0,
        GIR_ConstrainSelectedInstOperands, /*InsnID*/0,
        GIR_EraseFromParent, /*InsnID*/0,
        // GIR_Coverage, 3992,
        GIR_Done,
      // Label 6706: @493113
      GIM_Reject,
    // Label 6698: @493114
    GIM_Reject,
    // Label 6686: @493115
    GIM_Try, /*On fail goto*//*Label 6707*/ GIMT_Encode4(493826),
      GIM_CheckType, /*MI*/0, /*Op*/1, /*Type*/GILLT_v4s32,
      GIM_CheckType, /*MI*/0, /*Op*/2, /*Type*/GILLT_s32,
      GIM_CheckType, /*MI*/0, /*Op*/3, /*Type*/GILLT_s32,
      GIM_CheckType, /*MI*/0, /*Op*/4, /*Type*/GILLT_s32,
      GIM_CheckRegBankForClass, /*MI*/0, /*Op*/0, /*RC*/GIMT_Encode2(AMDGPU::AV_128RegClassID),
      GIM_Try, /*On fail goto*//*Label 6708*/ GIMT_Encode4(493223), // Rule ID 3993 //
        GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasUnrestrictedSOffset),
        GIM_CheckConstantInt8, /*MI*/0, /*Op*/2, 0,
        GIM_CheckConstantInt8, /*MI*/0, /*Op*/3, 0,
        // MIs[0] offset
        GIM_CheckIsImm, /*MI*/0, /*Op*/5,
        // MIs[0] auxiliary
        GIM_CheckIsImm, /*MI*/0, /*Op*/6,
        // MIs[0] Operand 7
        GIM_CheckLiteralInt, /*MI*/0, /*Op*/7, GIMT_Encode8(0),
        GIM_CheckComplexPattern, /*MI*/0, /*Op*/4, /*Renderer*/GIMT_Encode2(0), GIMT_Encode2(GICP_gi_buf_soffset),
        // (SIbuffer_load_format_tfe:{ *:[v4i32] } v4i32:{ *:[v4i32] }:$rsrc, 0:{ *:[i32] }, 0:{ *:[i32] }, (BUFSOffset:{ *:[i32] } i32:{ *:[i32] }:$soffset), (timm:{ *:[i32] }):$offset, (timm:{ *:[i32] }):$auxiliary, 0:{ *:[i1] })  =>  (BUFFER_LOAD_FORMAT_XYZ_TFE_OFFSET:{ *:[v4i32] } SReg_128:{ *:[v4i32] }:$rsrc, SCSrc_b32:{ *:[i32] }:$soffset, (timm:{ *:[i32] }):$offset, (extract_cpol:{ *:[i32] } ?:{ *:[i32] }:$auxiliary), (extract_swz:{ *:[i1] } ?:{ *:[i32] }:$auxiliary))
        GIR_BuildMI, /*InsnID*/0, /*Opcode*/GIMT_Encode2(AMDGPU::BUFFER_LOAD_FORMAT_XYZ_TFE_OFFSET),
        GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/0, // DstI[vdata]
        GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/1, // rsrc
        GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/0, // soffset
        GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/5, // offset
        GIR_CustomOperandRenderer, /*InsnID*/0, /*OldInsnID*/0, /*OpIdx*/6, /*OperandRenderer*/GIMT_Encode2(GICR_renderExtractCPol), // auxiliary
        GIR_CustomOperandRenderer, /*InsnID*/0, /*OldInsnID*/0, /*OpIdx*/6, /*OperandRenderer*/GIMT_Encode2(GICR_renderExtractSWZ), // auxiliary
        GIR_MergeMemOperands, /*InsnID*/0, /*NumInsns*/1, /*MergeInsnID's*/0,
        GIR_ConstrainSelectedInstOperands, /*InsnID*/0,
        GIR_EraseFromParent, /*InsnID*/0,
        // GIR_Coverage, 3993,
        GIR_Done,
      // Label 6708: @493223
      GIM_Try, /*On fail goto*//*Label 6709*/ GIMT_Encode4(493302), // Rule ID 3997 //
        GIM_CheckConstantInt8, /*MI*/0, /*Op*/2, 0,
        GIM_CheckConstantInt8, /*MI*/0, /*Op*/3, 0,
        // MIs[0] offset
        GIM_CheckIsImm, /*MI*/0, /*Op*/5,
        // MIs[0] auxiliary
        GIM_CheckIsImm, /*MI*/0, /*Op*/6,
        // MIs[0] Operand 7
        GIM_CheckLiteralInt, /*MI*/0, /*Op*/7, GIMT_Encode8(0),
        GIM_CheckComplexPattern, /*MI*/0, /*Op*/4, /*Renderer*/GIMT_Encode2(0), GIMT_Encode2(GICP_gi_buf_soffset),
        // (SIbuffer_load_format_tfe:{ *:[v4i32] } v4i32:{ *:[v4i32] }:$rsrc, 0:{ *:[i32] }, 0:{ *:[i32] }, (BUFSOffset:{ *:[i32] } i32:{ *:[i32] }:$soffset), (timm:{ *:[i32] }):$offset, (timm:{ *:[i32] }):$auxiliary, 0:{ *:[i1] })  =>  (BUFFER_LOAD_FORMAT_XYZ_TFE_VBUFFER_OFFSET:{ *:[v4i32] } SReg_128:{ *:[v4i32] }:$rsrc, SCSrc_b32:{ *:[i32] }:$soffset, (timm:{ *:[i32] }):$offset, (extract_cpol:{ *:[i32] } ?:{ *:[i32] }:$auxiliary), (extract_swz:{ *:[i1] } ?:{ *:[i32] }:$auxiliary))
        GIR_BuildMI, /*InsnID*/0, /*Opcode*/GIMT_Encode2(AMDGPU::BUFFER_LOAD_FORMAT_XYZ_TFE_VBUFFER_OFFSET),
        GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/0, // DstI[vdata]
        GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/1, // rsrc
        GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/0, // soffset
        GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/5, // offset
        GIR_CustomOperandRenderer, /*InsnID*/0, /*OldInsnID*/0, /*OpIdx*/6, /*OperandRenderer*/GIMT_Encode2(GICR_renderExtractCPol), // auxiliary
        GIR_CustomOperandRenderer, /*InsnID*/0, /*OldInsnID*/0, /*OpIdx*/6, /*OperandRenderer*/GIMT_Encode2(GICR_renderExtractSWZ), // auxiliary
        GIR_MergeMemOperands, /*InsnID*/0, /*NumInsns*/1, /*MergeInsnID's*/0,
        GIR_ConstrainSelectedInstOperands, /*InsnID*/0,
        GIR_EraseFromParent, /*InsnID*/0,
        // GIR_Coverage, 3997,
        GIR_Done,
      // Label 6709: @493302
      GIM_Try, /*On fail goto*//*Label 6710*/ GIMT_Encode4(493384), // Rule ID 3994 //
        GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasUnrestrictedSOffset),
        GIM_CheckConstantInt8, /*MI*/0, /*Op*/2, 0,
        // MIs[0] offset
        GIM_CheckIsImm, /*MI*/0, /*Op*/5,
        // MIs[0] auxiliary
        GIM_CheckIsImm, /*MI*/0, /*Op*/6,
        // MIs[0] Operand 7
        GIM_CheckLiteralInt, /*MI*/0, /*Op*/7, GIMT_Encode8(0),
        GIM_CheckComplexPattern, /*MI*/0, /*Op*/4, /*Renderer*/GIMT_Encode2(0), GIMT_Encode2(GICP_gi_buf_soffset),
        // (SIbuffer_load_format_tfe:{ *:[v4i32] } v4i32:{ *:[v4i32] }:$rsrc, 0:{ *:[i32] }, i32:{ *:[i32] }:$voffset, (BUFSOffset:{ *:[i32] } i32:{ *:[i32] }:$soffset), (timm:{ *:[i32] }):$offset, (timm:{ *:[i32] }):$auxiliary, 0:{ *:[i1] })  =>  (BUFFER_LOAD_FORMAT_XYZ_TFE_OFFEN:{ *:[v4i32] } VGPR_32:{ *:[i32] }:$voffset, SReg_128:{ *:[v4i32] }:$rsrc, SCSrc_b32:{ *:[i32] }:$soffset, (timm:{ *:[i32] }):$offset, (extract_cpol:{ *:[i32] } ?:{ *:[i32] }:$auxiliary), (extract_swz:{ *:[i1] } ?:{ *:[i32] }:$auxiliary))
        GIR_BuildMI, /*InsnID*/0, /*Opcode*/GIMT_Encode2(AMDGPU::BUFFER_LOAD_FORMAT_XYZ_TFE_OFFEN),
        GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/0, // DstI[vdata]
        GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/3, // voffset
        GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/1, // rsrc
        GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/0, // soffset
        GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/5, // offset
        GIR_CustomOperandRenderer, /*InsnID*/0, /*OldInsnID*/0, /*OpIdx*/6, /*OperandRenderer*/GIMT_Encode2(GICR_renderExtractCPol), // auxiliary
        GIR_CustomOperandRenderer, /*InsnID*/0, /*OldInsnID*/0, /*OpIdx*/6, /*OperandRenderer*/GIMT_Encode2(GICR_renderExtractSWZ), // auxiliary
        GIR_MergeMemOperands, /*InsnID*/0, /*NumInsns*/1, /*MergeInsnID's*/0,
        GIR_ConstrainSelectedInstOperands, /*InsnID*/0,
        GIR_EraseFromParent, /*InsnID*/0,
        // GIR_Coverage, 3994,
        GIR_Done,
      // Label 6710: @493384
      GIM_Try, /*On fail goto*//*Label 6711*/ GIMT_Encode4(493463), // Rule ID 3998 //
        GIM_CheckConstantInt8, /*MI*/0, /*Op*/2, 0,
        // MIs[0] offset
        GIM_CheckIsImm, /*MI*/0, /*Op*/5,
        // MIs[0] auxiliary
        GIM_CheckIsImm, /*MI*/0, /*Op*/6,
        // MIs[0] Operand 7
        GIM_CheckLiteralInt, /*MI*/0, /*Op*/7, GIMT_Encode8(0),
        GIM_CheckComplexPattern, /*MI*/0, /*Op*/4, /*Renderer*/GIMT_Encode2(0), GIMT_Encode2(GICP_gi_buf_soffset),
        // (SIbuffer_load_format_tfe:{ *:[v4i32] } v4i32:{ *:[v4i32] }:$rsrc, 0:{ *:[i32] }, i32:{ *:[i32] }:$voffset, (BUFSOffset:{ *:[i32] } i32:{ *:[i32] }:$soffset), (timm:{ *:[i32] }):$offset, (timm:{ *:[i32] }):$auxiliary, 0:{ *:[i1] })  =>  (BUFFER_LOAD_FORMAT_XYZ_TFE_VBUFFER_OFFEN:{ *:[v4i32] } VGPR_32:{ *:[i32] }:$voffset, SReg_128:{ *:[v4i32] }:$rsrc, SCSrc_b32:{ *:[i32] }:$soffset, (timm:{ *:[i32] }):$offset, (extract_cpol:{ *:[i32] } ?:{ *:[i32] }:$auxiliary), (extract_swz:{ *:[i1] } ?:{ *:[i32] }:$auxiliary))
        GIR_BuildMI, /*InsnID*/0, /*Opcode*/GIMT_Encode2(AMDGPU::BUFFER_LOAD_FORMAT_XYZ_TFE_VBUFFER_OFFEN),
        GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/0, // DstI[vdata]
        GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/3, // voffset
        GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/1, // rsrc
        GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/0, // soffset
        GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/5, // offset
        GIR_CustomOperandRenderer, /*InsnID*/0, /*OldInsnID*/0, /*OpIdx*/6, /*OperandRenderer*/GIMT_Encode2(GICR_renderExtractCPol), // auxiliary
        GIR_CustomOperandRenderer, /*InsnID*/0, /*OldInsnID*/0, /*OpIdx*/6, /*OperandRenderer*/GIMT_Encode2(GICR_renderExtractSWZ), // auxiliary
        GIR_MergeMemOperands, /*InsnID*/0, /*NumInsns*/1, /*MergeInsnID's*/0,
        GIR_ConstrainSelectedInstOperands, /*InsnID*/0,
        GIR_EraseFromParent, /*InsnID*/0,
        // GIR_Coverage, 3998,
        GIR_Done,
      // Label 6711: @493463
      GIM_Try, /*On fail goto*//*Label 6712*/ GIMT_Encode4(493537), // Rule ID 3995 //
        GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasUnrestrictedSOffset),
        GIM_CheckConstantInt8, /*MI*/0, /*Op*/3, 0,
        // MIs[0] offset
        GIM_CheckIsImm, /*MI*/0, /*Op*/5,
        // MIs[0] auxiliary
        GIM_CheckIsImm, /*MI*/0, /*Op*/6,
        // MIs[0] Operand 7
        GIM_CheckIsImm, /*MI*/0, /*Op*/7,
        GIM_CheckComplexPattern, /*MI*/0, /*Op*/4, /*Renderer*/GIMT_Encode2(0), GIMT_Encode2(GICP_gi_buf_soffset),
        // (SIbuffer_load_format_tfe:{ *:[v4i32] } v4i32:{ *:[v4i32] }:$rsrc, i32:{ *:[i32] }:$vindex, 0:{ *:[i32] }, (BUFSOffset:{ *:[i32] } i32:{ *:[i32] }:$soffset), (timm:{ *:[i32] }):$offset, (timm:{ *:[i32] }):$auxiliary, (timm:{ *:[i1] }))  =>  (BUFFER_LOAD_FORMAT_XYZ_TFE_IDXEN:{ *:[v4i32] } VGPR_32:{ *:[i32] }:$vindex, SReg_128:{ *:[v4i32] }:$rsrc, SCSrc_b32:{ *:[i32] }:$soffset, (timm:{ *:[i32] }):$offset, (extract_cpol:{ *:[i32] } ?:{ *:[i32] }:$auxiliary), (extract_swz:{ *:[i1] } ?:{ *:[i32] }:$auxiliary))
        GIR_BuildMI, /*InsnID*/0, /*Opcode*/GIMT_Encode2(AMDGPU::BUFFER_LOAD_FORMAT_XYZ_TFE_IDXEN),
        GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/0, // DstI[vdata]
        GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/2, // vindex
        GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/1, // rsrc
        GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/0, // soffset
        GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/5, // offset
        GIR_CustomOperandRenderer, /*InsnID*/0, /*OldInsnID*/0, /*OpIdx*/6, /*OperandRenderer*/GIMT_Encode2(GICR_renderExtractCPol), // auxiliary
        GIR_CustomOperandRenderer, /*InsnID*/0, /*OldInsnID*/0, /*OpIdx*/6, /*OperandRenderer*/GIMT_Encode2(GICR_renderExtractSWZ), // auxiliary
        GIR_MergeMemOperands, /*InsnID*/0, /*NumInsns*/1, /*MergeInsnID's*/0,
        GIR_ConstrainSelectedInstOperands, /*InsnID*/0,
        GIR_EraseFromParent, /*InsnID*/0,
        // GIR_Coverage, 3995,
        GIR_Done,
      // Label 6712: @493537
      GIM_Try, /*On fail goto*//*Label 6713*/ GIMT_Encode4(493608), // Rule ID 3999 //
        GIM_CheckConstantInt8, /*MI*/0, /*Op*/3, 0,
        // MIs[0] offset
        GIM_CheckIsImm, /*MI*/0, /*Op*/5,
        // MIs[0] auxiliary
        GIM_CheckIsImm, /*MI*/0, /*Op*/6,
        // MIs[0] Operand 7
        GIM_CheckIsImm, /*MI*/0, /*Op*/7,
        GIM_CheckComplexPattern, /*MI*/0, /*Op*/4, /*Renderer*/GIMT_Encode2(0), GIMT_Encode2(GICP_gi_buf_soffset),
        // (SIbuffer_load_format_tfe:{ *:[v4i32] } v4i32:{ *:[v4i32] }:$rsrc, i32:{ *:[i32] }:$vindex, 0:{ *:[i32] }, (BUFSOffset:{ *:[i32] } i32:{ *:[i32] }:$soffset), (timm:{ *:[i32] }):$offset, (timm:{ *:[i32] }):$auxiliary, (timm:{ *:[i1] }))  =>  (BUFFER_LOAD_FORMAT_XYZ_TFE_VBUFFER_IDXEN:{ *:[v4i32] } VGPR_32:{ *:[i32] }:$vindex, SReg_128:{ *:[v4i32] }:$rsrc, SCSrc_b32:{ *:[i32] }:$soffset, (timm:{ *:[i32] }):$offset, (extract_cpol:{ *:[i32] } ?:{ *:[i32] }:$auxiliary), (extract_swz:{ *:[i1] } ?:{ *:[i32] }:$auxiliary))
        GIR_BuildMI, /*InsnID*/0, /*Opcode*/GIMT_Encode2(AMDGPU::BUFFER_LOAD_FORMAT_XYZ_TFE_VBUFFER_IDXEN),
        GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/0, // DstI[vdata]
        GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/2, // vindex
        GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/1, // rsrc
        GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/0, // soffset
        GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/5, // offset
        GIR_CustomOperandRenderer, /*InsnID*/0, /*OldInsnID*/0, /*OpIdx*/6, /*OperandRenderer*/GIMT_Encode2(GICR_renderExtractCPol), // auxiliary
        GIR_CustomOperandRenderer, /*InsnID*/0, /*OldInsnID*/0, /*OpIdx*/6, /*OperandRenderer*/GIMT_Encode2(GICR_renderExtractSWZ), // auxiliary
        GIR_MergeMemOperands, /*InsnID*/0, /*NumInsns*/1, /*MergeInsnID's*/0,
        GIR_ConstrainSelectedInstOperands, /*InsnID*/0,
        GIR_EraseFromParent, /*InsnID*/0,
        // GIR_Coverage, 3999,
        GIR_Done,
      // Label 6713: @493608
      GIM_Try, /*On fail goto*//*Label 6714*/ GIMT_Encode4(493718), // Rule ID 3996 //
        GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasUnrestrictedSOffset),
        // MIs[0] offset
        GIM_CheckIsImm, /*MI*/0, /*Op*/5,
        // MIs[0] auxiliary
        GIM_CheckIsImm, /*MI*/0, /*Op*/6,
        // MIs[0] Operand 7
        GIM_CheckIsImm, /*MI*/0, /*Op*/7,
        GIM_CheckComplexPattern, /*MI*/0, /*Op*/4, /*Renderer*/GIMT_Encode2(0), GIMT_Encode2(GICP_gi_buf_soffset),
        // (SIbuffer_load_format_tfe:{ *:[v4i32] } v4i32:{ *:[v4i32] }:$rsrc, i32:{ *:[i32] }:$vindex, i32:{ *:[i32] }:$voffset, (BUFSOffset:{ *:[i32] } i32:{ *:[i32] }:$soffset), (timm:{ *:[i32] }):$offset, (timm:{ *:[i32] }):$auxiliary, (timm:{ *:[i1] }))  =>  (BUFFER_LOAD_FORMAT_XYZ_TFE_BOTHEN:{ *:[v4i32] } (REG_SEQUENCE:{ *:[i64] } VReg_64:{ *:[i32] }, VGPR_32:{ *:[i32] }:$vindex, sub0:{ *:[i32] }, VGPR_32:{ *:[i32] }:$voffset, sub1:{ *:[i32] }), SReg_128:{ *:[v4i32] }:$rsrc, SCSrc_b32:{ *:[i32] }:$soffset, (timm:{ *:[i32] }):$offset, (extract_cpol:{ *:[i32] } ?:{ *:[i32] }:$auxiliary), (extract_swz:{ *:[i1] } ?:{ *:[i32] }:$auxiliary))
        GIR_MakeTempReg, /*TempRegID*/0, /*TypeID*/GILLT_s64,
        GIR_BuildMI, /*InsnID*/1, /*Opcode*/GIMT_Encode2(TargetOpcode::REG_SEQUENCE),
        GIR_AddTempRegister, /*InsnID*/1, /*TempRegID*/0, /*TempRegFlags*/GIMT_Encode2(RegState::Define),
        GIR_Copy, /*NewInsnID*/1, /*OldInsnID*/0, /*OpIdx*/2, // vindex
        GIR_AddImm8, /*InsnID*/1, /*SubRegIndex*/3,
        GIR_Copy, /*NewInsnID*/1, /*OldInsnID*/0, /*OpIdx*/3, // voffset
        GIR_AddImm8, /*InsnID*/1, /*SubRegIndex*/11,
        GIR_ConstrainOperandRC, /*InsnID*/1, /*Op*/0, GIMT_Encode2(AMDGPU::VReg_64RegClassID),
        GIR_ConstrainOperandRC, /*InsnID*/1, /*Op*/1, GIMT_Encode2(AMDGPU::VGPR_32RegClassID),
        GIR_ConstrainOperandRC, /*InsnID*/1, /*Op*/3, GIMT_Encode2(AMDGPU::VGPR_32RegClassID),
        GIR_BuildMI, /*InsnID*/0, /*Opcode*/GIMT_Encode2(AMDGPU::BUFFER_LOAD_FORMAT_XYZ_TFE_BOTHEN),
        GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/0, // DstI[vdata]
        GIR_AddSimpleTempRegister, /*InsnID*/0, /*TempRegID*/0,
        GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/1, // rsrc
        GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/0, // soffset
        GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/5, // offset
        GIR_CustomOperandRenderer, /*InsnID*/0, /*OldInsnID*/0, /*OpIdx*/6, /*OperandRenderer*/GIMT_Encode2(GICR_renderExtractCPol), // auxiliary
        GIR_CustomOperandRenderer, /*InsnID*/0, /*OldInsnID*/0, /*OpIdx*/6, /*OperandRenderer*/GIMT_Encode2(GICR_renderExtractSWZ), // auxiliary
        GIR_MergeMemOperands, /*InsnID*/0, /*NumInsns*/1, /*MergeInsnID's*/0,
        GIR_ConstrainSelectedInstOperands, /*InsnID*/0,
        GIR_EraseFromParent, /*InsnID*/0,
        // GIR_Coverage, 3996,
        GIR_Done,
      // Label 6714: @493718
      GIM_Try, /*On fail goto*//*Label 6715*/ GIMT_Encode4(493825), // Rule ID 4000 //
        // MIs[0] offset
        GIM_CheckIsImm, /*MI*/0, /*Op*/5,
        // MIs[0] auxiliary
        GIM_CheckIsImm, /*MI*/0, /*Op*/6,
        // MIs[0] Operand 7
        GIM_CheckIsImm, /*MI*/0, /*Op*/7,
        GIM_CheckComplexPattern, /*MI*/0, /*Op*/4, /*Renderer*/GIMT_Encode2(0), GIMT_Encode2(GICP_gi_buf_soffset),
        // (SIbuffer_load_format_tfe:{ *:[v4i32] } v4i32:{ *:[v4i32] }:$rsrc, i32:{ *:[i32] }:$vindex, i32:{ *:[i32] }:$voffset, (BUFSOffset:{ *:[i32] } i32:{ *:[i32] }:$soffset), (timm:{ *:[i32] }):$offset, (timm:{ *:[i32] }):$auxiliary, (timm:{ *:[i1] }))  =>  (BUFFER_LOAD_FORMAT_XYZ_TFE_VBUFFER_BOTHEN:{ *:[v4i32] } (REG_SEQUENCE:{ *:[i64] } VReg_64:{ *:[i32] }, VGPR_32:{ *:[i32] }:$vindex, sub0:{ *:[i32] }, VGPR_32:{ *:[i32] }:$voffset, sub1:{ *:[i32] }), SReg_128:{ *:[v4i32] }:$rsrc, SCSrc_b32:{ *:[i32] }:$soffset, (timm:{ *:[i32] }):$offset, (extract_cpol:{ *:[i32] } ?:{ *:[i32] }:$auxiliary), (extract_swz:{ *:[i1] } ?:{ *:[i32] }:$auxiliary))
        GIR_MakeTempReg, /*TempRegID*/0, /*TypeID*/GILLT_s64,
        GIR_BuildMI, /*InsnID*/1, /*Opcode*/GIMT_Encode2(TargetOpcode::REG_SEQUENCE),
        GIR_AddTempRegister, /*InsnID*/1, /*TempRegID*/0, /*TempRegFlags*/GIMT_Encode2(RegState::Define),
        GIR_Copy, /*NewInsnID*/1, /*OldInsnID*/0, /*OpIdx*/2, // vindex
        GIR_AddImm8, /*InsnID*/1, /*SubRegIndex*/3,
        GIR_Copy, /*NewInsnID*/1, /*OldInsnID*/0, /*OpIdx*/3, // voffset
        GIR_AddImm8, /*InsnID*/1, /*SubRegIndex*/11,
        GIR_ConstrainOperandRC, /*InsnID*/1, /*Op*/0, GIMT_Encode2(AMDGPU::VReg_64RegClassID),
        GIR_ConstrainOperandRC, /*InsnID*/1, /*Op*/1, GIMT_Encode2(AMDGPU::VGPR_32RegClassID),
        GIR_ConstrainOperandRC, /*InsnID*/1, /*Op*/3, GIMT_Encode2(AMDGPU::VGPR_32RegClassID),
        GIR_BuildMI, /*InsnID*/0, /*Opcode*/GIMT_Encode2(AMDGPU::BUFFER_LOAD_FORMAT_XYZ_TFE_VBUFFER_BOTHEN),
        GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/0, // DstI[vdata]
        GIR_AddSimpleTempRegister, /*InsnID*/0, /*TempRegID*/0,
        GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/1, // rsrc
        GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/0, // soffset
        GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/5, // offset
        GIR_CustomOperandRenderer, /*InsnID*/0, /*OldInsnID*/0, /*OpIdx*/6, /*OperandRenderer*/GIMT_Encode2(GICR_renderExtractCPol), // auxiliary
        GIR_CustomOperandRenderer, /*InsnID*/0, /*OldInsnID*/0, /*OpIdx*/6, /*OperandRenderer*/GIMT_Encode2(GICR_renderExtractSWZ), // auxiliary
        GIR_MergeMemOperands, /*InsnID*/0, /*NumInsns*/1, /*MergeInsnID's*/0,
        GIR_ConstrainSelectedInstOperands, /*InsnID*/0,
        GIR_EraseFromParent, /*InsnID*/0,
        // GIR_Coverage, 4000,
        GIR_Done,
      // Label 6715: @493825
      GIM_Reject,
    // Label 6707: @493826
    GIM_Reject,
    // Label 6687: @493827
    GIM_Try, /*On fail goto*//*Label 6716*/ GIMT_Encode4(494538),
      GIM_CheckType, /*MI*/0, /*Op*/1, /*Type*/GILLT_v4s32,
      GIM_CheckType, /*MI*/0, /*Op*/2, /*Type*/GILLT_s32,
      GIM_CheckType, /*MI*/0, /*Op*/3, /*Type*/GILLT_s32,
      GIM_CheckType, /*MI*/0, /*Op*/4, /*Type*/GILLT_s32,
      GIM_CheckRegBankForClass, /*MI*/0, /*Op*/0, /*RC*/GIMT_Encode2(AMDGPU::AV_160RegClassID),
      GIM_Try, /*On fail goto*//*Label 6717*/ GIMT_Encode4(493935), // Rule ID 4001 //
        GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasUnrestrictedSOffset),
        GIM_CheckConstantInt8, /*MI*/0, /*Op*/2, 0,
        GIM_CheckConstantInt8, /*MI*/0, /*Op*/3, 0,
        // MIs[0] offset
        GIM_CheckIsImm, /*MI*/0, /*Op*/5,
        // MIs[0] auxiliary
        GIM_CheckIsImm, /*MI*/0, /*Op*/6,
        // MIs[0] Operand 7
        GIM_CheckLiteralInt, /*MI*/0, /*Op*/7, GIMT_Encode8(0),
        GIM_CheckComplexPattern, /*MI*/0, /*Op*/4, /*Renderer*/GIMT_Encode2(0), GIMT_Encode2(GICP_gi_buf_soffset),
        // (SIbuffer_load_format_tfe:{ *:[v5i32] } v4i32:{ *:[v4i32] }:$rsrc, 0:{ *:[i32] }, 0:{ *:[i32] }, (BUFSOffset:{ *:[i32] } i32:{ *:[i32] }:$soffset), (timm:{ *:[i32] }):$offset, (timm:{ *:[i32] }):$auxiliary, 0:{ *:[i1] })  =>  (BUFFER_LOAD_FORMAT_XYZW_TFE_OFFSET:{ *:[v5i32] } SReg_128:{ *:[v4i32] }:$rsrc, SCSrc_b32:{ *:[i32] }:$soffset, (timm:{ *:[i32] }):$offset, (extract_cpol:{ *:[i32] } ?:{ *:[i32] }:$auxiliary), (extract_swz:{ *:[i1] } ?:{ *:[i32] }:$auxiliary))
        GIR_BuildMI, /*InsnID*/0, /*Opcode*/GIMT_Encode2(AMDGPU::BUFFER_LOAD_FORMAT_XYZW_TFE_OFFSET),
        GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/0, // DstI[vdata]
        GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/1, // rsrc
        GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/0, // soffset
        GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/5, // offset
        GIR_CustomOperandRenderer, /*InsnID*/0, /*OldInsnID*/0, /*OpIdx*/6, /*OperandRenderer*/GIMT_Encode2(GICR_renderExtractCPol), // auxiliary
        GIR_CustomOperandRenderer, /*InsnID*/0, /*OldInsnID*/0, /*OpIdx*/6, /*OperandRenderer*/GIMT_Encode2(GICR_renderExtractSWZ), // auxiliary
        GIR_MergeMemOperands, /*InsnID*/0, /*NumInsns*/1, /*MergeInsnID's*/0,
        GIR_ConstrainSelectedInstOperands, /*InsnID*/0,
        GIR_EraseFromParent, /*InsnID*/0,
        // GIR_Coverage, 4001,
        GIR_Done,
      // Label 6717: @493935
      GIM_Try, /*On fail goto*//*Label 6718*/ GIMT_Encode4(494014), // Rule ID 4005 //
        GIM_CheckConstantInt8, /*MI*/0, /*Op*/2, 0,
        GIM_CheckConstantInt8, /*MI*/0, /*Op*/3, 0,
        // MIs[0] offset
        GIM_CheckIsImm, /*MI*/0, /*Op*/5,
        // MIs[0] auxiliary
        GIM_CheckIsImm, /*MI*/0, /*Op*/6,
        // MIs[0] Operand 7
        GIM_CheckLiteralInt, /*MI*/0, /*Op*/7, GIMT_Encode8(0),
        GIM_CheckComplexPattern, /*MI*/0, /*Op*/4, /*Renderer*/GIMT_Encode2(0), GIMT_Encode2(GICP_gi_buf_soffset),
        // (SIbuffer_load_format_tfe:{ *:[v5i32] } v4i32:{ *:[v4i32] }:$rsrc, 0:{ *:[i32] }, 0:{ *:[i32] }, (BUFSOffset:{ *:[i32] } i32:{ *:[i32] }:$soffset), (timm:{ *:[i32] }):$offset, (timm:{ *:[i32] }):$auxiliary, 0:{ *:[i1] })  =>  (BUFFER_LOAD_FORMAT_XYZW_TFE_VBUFFER_OFFSET:{ *:[v5i32] } SReg_128:{ *:[v4i32] }:$rsrc, SCSrc_b32:{ *:[i32] }:$soffset, (timm:{ *:[i32] }):$offset, (extract_cpol:{ *:[i32] } ?:{ *:[i32] }:$auxiliary), (extract_swz:{ *:[i1] } ?:{ *:[i32] }:$auxiliary))
        GIR_BuildMI, /*InsnID*/0, /*Opcode*/GIMT_Encode2(AMDGPU::BUFFER_LOAD_FORMAT_XYZW_TFE_VBUFFER_OFFSET),
        GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/0, // DstI[vdata]
        GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/1, // rsrc
        GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/0, // soffset
        GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/5, // offset
        GIR_CustomOperandRenderer, /*InsnID*/0, /*OldInsnID*/0, /*OpIdx*/6, /*OperandRenderer*/GIMT_Encode2(GICR_renderExtractCPol), // auxiliary
        GIR_CustomOperandRenderer, /*InsnID*/0, /*OldInsnID*/0, /*OpIdx*/6, /*OperandRenderer*/GIMT_Encode2(GICR_renderExtractSWZ), // auxiliary
        GIR_MergeMemOperands, /*InsnID*/0, /*NumInsns*/1, /*MergeInsnID's*/0,
        GIR_ConstrainSelectedInstOperands, /*InsnID*/0,
        GIR_EraseFromParent, /*InsnID*/0,
        // GIR_Coverage, 4005,
        GIR_Done,
      // Label 6718: @494014
      GIM_Try, /*On fail goto*//*Label 6719*/ GIMT_Encode4(494096), // Rule ID 4002 //
        GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasUnrestrictedSOffset),
        GIM_CheckConstantInt8, /*MI*/0, /*Op*/2, 0,
        // MIs[0] offset
        GIM_CheckIsImm, /*MI*/0, /*Op*/5,
        // MIs[0] auxiliary
        GIM_CheckIsImm, /*MI*/0, /*Op*/6,
        // MIs[0] Operand 7
        GIM_CheckLiteralInt, /*MI*/0, /*Op*/7, GIMT_Encode8(0),
        GIM_CheckComplexPattern, /*MI*/0, /*Op*/4, /*Renderer*/GIMT_Encode2(0), GIMT_Encode2(GICP_gi_buf_soffset),
        // (SIbuffer_load_format_tfe:{ *:[v5i32] } v4i32:{ *:[v4i32] }:$rsrc, 0:{ *:[i32] }, i32:{ *:[i32] }:$voffset, (BUFSOffset:{ *:[i32] } i32:{ *:[i32] }:$soffset), (timm:{ *:[i32] }):$offset, (timm:{ *:[i32] }):$auxiliary, 0:{ *:[i1] })  =>  (BUFFER_LOAD_FORMAT_XYZW_TFE_OFFEN:{ *:[v5i32] } VGPR_32:{ *:[i32] }:$voffset, SReg_128:{ *:[v4i32] }:$rsrc, SCSrc_b32:{ *:[i32] }:$soffset, (timm:{ *:[i32] }):$offset, (extract_cpol:{ *:[i32] } ?:{ *:[i32] }:$auxiliary), (extract_swz:{ *:[i1] } ?:{ *:[i32] }:$auxiliary))
        GIR_BuildMI, /*InsnID*/0, /*Opcode*/GIMT_Encode2(AMDGPU::BUFFER_LOAD_FORMAT_XYZW_TFE_OFFEN),
        GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/0, // DstI[vdata]
        GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/3, // voffset
        GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/1, // rsrc
        GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/0, // soffset
        GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/5, // offset
        GIR_CustomOperandRenderer, /*InsnID*/0, /*OldInsnID*/0, /*OpIdx*/6, /*OperandRenderer*/GIMT_Encode2(GICR_renderExtractCPol), // auxiliary
        GIR_CustomOperandRenderer, /*InsnID*/0, /*OldInsnID*/0, /*OpIdx*/6, /*OperandRenderer*/GIMT_Encode2(GICR_renderExtractSWZ), // auxiliary
        GIR_MergeMemOperands, /*InsnID*/0, /*NumInsns*/1, /*MergeInsnID's*/0,
        GIR_ConstrainSelectedInstOperands, /*InsnID*/0,
        GIR_EraseFromParent, /*InsnID*/0,
        // GIR_Coverage, 4002,
        GIR_Done,
      // Label 6719: @494096
      GIM_Try, /*On fail goto*//*Label 6720*/ GIMT_Encode4(494175), // Rule ID 4006 //
        GIM_CheckConstantInt8, /*MI*/0, /*Op*/2, 0,
        // MIs[0] offset
        GIM_CheckIsImm, /*MI*/0, /*Op*/5,
        // MIs[0] auxiliary
        GIM_CheckIsImm, /*MI*/0, /*Op*/6,
        // MIs[0] Operand 7
        GIM_CheckLiteralInt, /*MI*/0, /*Op*/7, GIMT_Encode8(0),
        GIM_CheckComplexPattern, /*MI*/0, /*Op*/4, /*Renderer*/GIMT_Encode2(0), GIMT_Encode2(GICP_gi_buf_soffset),
        // (SIbuffer_load_format_tfe:{ *:[v5i32] } v4i32:{ *:[v4i32] }:$rsrc, 0:{ *:[i32] }, i32:{ *:[i32] }:$voffset, (BUFSOffset:{ *:[i32] } i32:{ *:[i32] }:$soffset), (timm:{ *:[i32] }):$offset, (timm:{ *:[i32] }):$auxiliary, 0:{ *:[i1] })  =>  (BUFFER_LOAD_FORMAT_XYZW_TFE_VBUFFER_OFFEN:{ *:[v5i32] } VGPR_32:{ *:[i32] }:$voffset, SReg_128:{ *:[v4i32] }:$rsrc, SCSrc_b32:{ *:[i32] }:$soffset, (timm:{ *:[i32] }):$offset, (extract_cpol:{ *:[i32] } ?:{ *:[i32] }:$auxiliary), (extract_swz:{ *:[i1] } ?:{ *:[i32] }:$auxiliary))
        GIR_BuildMI, /*InsnID*/0, /*Opcode*/GIMT_Encode2(AMDGPU::BUFFER_LOAD_FORMAT_XYZW_TFE_VBUFFER_OFFEN),
        GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/0, // DstI[vdata]
        GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/3, // voffset
        GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/1, // rsrc
        GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/0, // soffset
        GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/5, // offset
        GIR_CustomOperandRenderer, /*InsnID*/0, /*OldInsnID*/0, /*OpIdx*/6, /*OperandRenderer*/GIMT_Encode2(GICR_renderExtractCPol), // auxiliary
        GIR_CustomOperandRenderer, /*InsnID*/0, /*OldInsnID*/0, /*OpIdx*/6, /*OperandRenderer*/GIMT_Encode2(GICR_renderExtractSWZ), // auxiliary
        GIR_MergeMemOperands, /*InsnID*/0, /*NumInsns*/1, /*MergeInsnID's*/0,
        GIR_ConstrainSelectedInstOperands, /*InsnID*/0,
        GIR_EraseFromParent, /*InsnID*/0,
        // GIR_Coverage, 4006,
        GIR_Done,
      // Label 6720: @494175
      GIM_Try, /*On fail goto*//*Label 6721*/ GIMT_Encode4(494249), // Rule ID 4003 //
        GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasUnrestrictedSOffset),
        GIM_CheckConstantInt8, /*MI*/0, /*Op*/3, 0,
        // MIs[0] offset
        GIM_CheckIsImm, /*MI*/0, /*Op*/5,
        // MIs[0] auxiliary
        GIM_CheckIsImm, /*MI*/0, /*Op*/6,
        // MIs[0] Operand 7
        GIM_CheckIsImm, /*MI*/0, /*Op*/7,
        GIM_CheckComplexPattern, /*MI*/0, /*Op*/4, /*Renderer*/GIMT_Encode2(0), GIMT_Encode2(GICP_gi_buf_soffset),
        // (SIbuffer_load_format_tfe:{ *:[v5i32] } v4i32:{ *:[v4i32] }:$rsrc, i32:{ *:[i32] }:$vindex, 0:{ *:[i32] }, (BUFSOffset:{ *:[i32] } i32:{ *:[i32] }:$soffset), (timm:{ *:[i32] }):$offset, (timm:{ *:[i32] }):$auxiliary, (timm:{ *:[i1] }))  =>  (BUFFER_LOAD_FORMAT_XYZW_TFE_IDXEN:{ *:[v5i32] } VGPR_32:{ *:[i32] }:$vindex, SReg_128:{ *:[v4i32] }:$rsrc, SCSrc_b32:{ *:[i32] }:$soffset, (timm:{ *:[i32] }):$offset, (extract_cpol:{ *:[i32] } ?:{ *:[i32] }:$auxiliary), (extract_swz:{ *:[i1] } ?:{ *:[i32] }:$auxiliary))
        GIR_BuildMI, /*InsnID*/0, /*Opcode*/GIMT_Encode2(AMDGPU::BUFFER_LOAD_FORMAT_XYZW_TFE_IDXEN),
        GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/0, // DstI[vdata]
        GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/2, // vindex
        GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/1, // rsrc
        GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/0, // soffset
        GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/5, // offset
        GIR_CustomOperandRenderer, /*InsnID*/0, /*OldInsnID*/0, /*OpIdx*/6, /*OperandRenderer*/GIMT_Encode2(GICR_renderExtractCPol), // auxiliary
        GIR_CustomOperandRenderer, /*InsnID*/0, /*OldInsnID*/0, /*OpIdx*/6, /*OperandRenderer*/GIMT_Encode2(GICR_renderExtractSWZ), // auxiliary
        GIR_MergeMemOperands, /*InsnID*/0, /*NumInsns*/1, /*MergeInsnID's*/0,
        GIR_ConstrainSelectedInstOperands, /*InsnID*/0,
        GIR_EraseFromParent, /*InsnID*/0,
        // GIR_Coverage, 4003,
        GIR_Done,
      // Label 6721: @494249
      GIM_Try, /*On fail goto*//*Label 6722*/ GIMT_Encode4(494320), // Rule ID 4007 //
        GIM_CheckConstantInt8, /*MI*/0, /*Op*/3, 0,
        // MIs[0] offset
        GIM_CheckIsImm, /*MI*/0, /*Op*/5,
        // MIs[0] auxiliary
        GIM_CheckIsImm, /*MI*/0, /*Op*/6,
        // MIs[0] Operand 7
        GIM_CheckIsImm, /*MI*/0, /*Op*/7,
        GIM_CheckComplexPattern, /*MI*/0, /*Op*/4, /*Renderer*/GIMT_Encode2(0), GIMT_Encode2(GICP_gi_buf_soffset),
        // (SIbuffer_load_format_tfe:{ *:[v5i32] } v4i32:{ *:[v4i32] }:$rsrc, i32:{ *:[i32] }:$vindex, 0:{ *:[i32] }, (BUFSOffset:{ *:[i32] } i32:{ *:[i32] }:$soffset), (timm:{ *:[i32] }):$offset, (timm:{ *:[i32] }):$auxiliary, (timm:{ *:[i1] }))  =>  (BUFFER_LOAD_FORMAT_XYZW_TFE_VBUFFER_IDXEN:{ *:[v5i32] } VGPR_32:{ *:[i32] }:$vindex, SReg_128:{ *:[v4i32] }:$rsrc, SCSrc_b32:{ *:[i32] }:$soffset, (timm:{ *:[i32] }):$offset, (extract_cpol:{ *:[i32] } ?:{ *:[i32] }:$auxiliary), (extract_swz:{ *:[i1] } ?:{ *:[i32] }:$auxiliary))
        GIR_BuildMI, /*InsnID*/0, /*Opcode*/GIMT_Encode2(AMDGPU::BUFFER_LOAD_FORMAT_XYZW_TFE_VBUFFER_IDXEN),
        GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/0, // DstI[vdata]
        GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/2, // vindex
        GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/1, // rsrc
        GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/0, // soffset
        GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/5, // offset
        GIR_CustomOperandRenderer, /*InsnID*/0, /*OldInsnID*/0, /*OpIdx*/6, /*OperandRenderer*/GIMT_Encode2(GICR_renderExtractCPol), // auxiliary
        GIR_CustomOperandRenderer, /*InsnID*/0, /*OldInsnID*/0, /*OpIdx*/6, /*OperandRenderer*/GIMT_Encode2(GICR_renderExtractSWZ), // auxiliary
        GIR_MergeMemOperands, /*InsnID*/0, /*NumInsns*/1, /*MergeInsnID's*/0,
        GIR_ConstrainSelectedInstOperands, /*InsnID*/0,
        GIR_EraseFromParent, /*InsnID*/0,
        // GIR_Coverage, 4007,
        GIR_Done,
      // Label 6722: @494320
      GIM_Try, /*On fail goto*//*Label 6723*/ GIMT_Encode4(494430), // Rule ID 4004 //
        GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasUnrestrictedSOffset),
        // MIs[0] offset
        GIM_CheckIsImm, /*MI*/0, /*Op*/5,
        // MIs[0] auxiliary
        GIM_CheckIsImm, /*MI*/0, /*Op*/6,
        // MIs[0] Operand 7
        GIM_CheckIsImm, /*MI*/0, /*Op*/7,
        GIM_CheckComplexPattern, /*MI*/0, /*Op*/4, /*Renderer*/GIMT_Encode2(0), GIMT_Encode2(GICP_gi_buf_soffset),
        // (SIbuffer_load_format_tfe:{ *:[v5i32] } v4i32:{ *:[v4i32] }:$rsrc, i32:{ *:[i32] }:$vindex, i32:{ *:[i32] }:$voffset, (BUFSOffset:{ *:[i32] } i32:{ *:[i32] }:$soffset), (timm:{ *:[i32] }):$offset, (timm:{ *:[i32] }):$auxiliary, (timm:{ *:[i1] }))  =>  (BUFFER_LOAD_FORMAT_XYZW_TFE_BOTHEN:{ *:[v5i32] } (REG_SEQUENCE:{ *:[i64] } VReg_64:{ *:[i32] }, VGPR_32:{ *:[i32] }:$vindex, sub0:{ *:[i32] }, VGPR_32:{ *:[i32] }:$voffset, sub1:{ *:[i32] }), SReg_128:{ *:[v4i32] }:$rsrc, SCSrc_b32:{ *:[i32] }:$soffset, (timm:{ *:[i32] }):$offset, (extract_cpol:{ *:[i32] } ?:{ *:[i32] }:$auxiliary), (extract_swz:{ *:[i1] } ?:{ *:[i32] }:$auxiliary))
        GIR_MakeTempReg, /*TempRegID*/0, /*TypeID*/GILLT_s64,
        GIR_BuildMI, /*InsnID*/1, /*Opcode*/GIMT_Encode2(TargetOpcode::REG_SEQUENCE),
        GIR_AddTempRegister, /*InsnID*/1, /*TempRegID*/0, /*TempRegFlags*/GIMT_Encode2(RegState::Define),
        GIR_Copy, /*NewInsnID*/1, /*OldInsnID*/0, /*OpIdx*/2, // vindex
        GIR_AddImm8, /*InsnID*/1, /*SubRegIndex*/3,
        GIR_Copy, /*NewInsnID*/1, /*OldInsnID*/0, /*OpIdx*/3, // voffset
        GIR_AddImm8, /*InsnID*/1, /*SubRegIndex*/11,
        GIR_ConstrainOperandRC, /*InsnID*/1, /*Op*/0, GIMT_Encode2(AMDGPU::VReg_64RegClassID),
        GIR_ConstrainOperandRC, /*InsnID*/1, /*Op*/1, GIMT_Encode2(AMDGPU::VGPR_32RegClassID),
        GIR_ConstrainOperandRC, /*InsnID*/1, /*Op*/3, GIMT_Encode2(AMDGPU::VGPR_32RegClassID),
        GIR_BuildMI, /*InsnID*/0, /*Opcode*/GIMT_Encode2(AMDGPU::BUFFER_LOAD_FORMAT_XYZW_TFE_BOTHEN),
        GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/0, // DstI[vdata]
        GIR_AddSimpleTempRegister, /*InsnID*/0, /*TempRegID*/0,
        GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/1, // rsrc
        GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/0, // soffset
        GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/5, // offset
        GIR_CustomOperandRenderer, /*InsnID*/0, /*OldInsnID*/0, /*OpIdx*/6, /*OperandRenderer*/GIMT_Encode2(GICR_renderExtractCPol), // auxiliary
        GIR_CustomOperandRenderer, /*InsnID*/0, /*OldInsnID*/0, /*OpIdx*/6, /*OperandRenderer*/GIMT_Encode2(GICR_renderExtractSWZ), // auxiliary
        GIR_MergeMemOperands, /*InsnID*/0, /*NumInsns*/1, /*MergeInsnID's*/0,
        GIR_ConstrainSelectedInstOperands, /*InsnID*/0,
        GIR_EraseFromParent, /*InsnID*/0,
        // GIR_Coverage, 4004,
        GIR_Done,
      // Label 6723: @494430
      GIM_Try, /*On fail goto*//*Label 6724*/ GIMT_Encode4(494537), // Rule ID 4008 //
        // MIs[0] offset
        GIM_CheckIsImm, /*MI*/0, /*Op*/5,
        // MIs[0] auxiliary
        GIM_CheckIsImm, /*MI*/0, /*Op*/6,
        // MIs[0] Operand 7
        GIM_CheckIsImm, /*MI*/0, /*Op*/7,
        GIM_CheckComplexPattern, /*MI*/0, /*Op*/4, /*Renderer*/GIMT_Encode2(0), GIMT_Encode2(GICP_gi_buf_soffset),
        // (SIbuffer_load_format_tfe:{ *:[v5i32] } v4i32:{ *:[v4i32] }:$rsrc, i32:{ *:[i32] }:$vindex, i32:{ *:[i32] }:$voffset, (BUFSOffset:{ *:[i32] } i32:{ *:[i32] }:$soffset), (timm:{ *:[i32] }):$offset, (timm:{ *:[i32] }):$auxiliary, (timm:{ *:[i1] }))  =>  (BUFFER_LOAD_FORMAT_XYZW_TFE_VBUFFER_BOTHEN:{ *:[v5i32] } (REG_SEQUENCE:{ *:[i64] } VReg_64:{ *:[i32] }, VGPR_32:{ *:[i32] }:$vindex, sub0:{ *:[i32] }, VGPR_32:{ *:[i32] }:$voffset, sub1:{ *:[i32] }), SReg_128:{ *:[v4i32] }:$rsrc, SCSrc_b32:{ *:[i32] }:$soffset, (timm:{ *:[i32] }):$offset, (extract_cpol:{ *:[i32] } ?:{ *:[i32] }:$auxiliary), (extract_swz:{ *:[i1] } ?:{ *:[i32] }:$auxiliary))
        GIR_MakeTempReg, /*TempRegID*/0, /*TypeID*/GILLT_s64,
        GIR_BuildMI, /*InsnID*/1, /*Opcode*/GIMT_Encode2(TargetOpcode::REG_SEQUENCE),
        GIR_AddTempRegister, /*InsnID*/1, /*TempRegID*/0, /*TempRegFlags*/GIMT_Encode2(RegState::Define),
        GIR_Copy, /*NewInsnID*/1, /*OldInsnID*/0, /*OpIdx*/2, // vindex
        GIR_AddImm8, /*InsnID*/1, /*SubRegIndex*/3,
        GIR_Copy, /*NewInsnID*/1, /*OldInsnID*/0, /*OpIdx*/3, // voffset
        GIR_AddImm8, /*InsnID*/1, /*SubRegIndex*/11,
        GIR_ConstrainOperandRC, /*InsnID*/1, /*Op*/0, GIMT_Encode2(AMDGPU::VReg_64RegClassID),
        GIR_ConstrainOperandRC, /*InsnID*/1, /*Op*/1, GIMT_Encode2(AMDGPU::VGPR_32RegClassID),
        GIR_ConstrainOperandRC, /*InsnID*/1, /*Op*/3, GIMT_Encode2(AMDGPU::VGPR_32RegClassID),
        GIR_BuildMI, /*InsnID*/0, /*Opcode*/GIMT_Encode2(AMDGPU::BUFFER_LOAD_FORMAT_XYZW_TFE_VBUFFER_BOTHEN),
        GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/0, // DstI[vdata]
        GIR_AddSimpleTempRegister, /*InsnID*/0, /*TempRegID*/0,
        GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/1, // rsrc
        GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/0, // soffset
        GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/5, // offset
        GIR_CustomOperandRenderer, /*InsnID*/0, /*OldInsnID*/0, /*OpIdx*/6, /*OperandRenderer*/GIMT_Encode2(GICR_renderExtractCPol), // auxiliary
        GIR_CustomOperandRenderer, /*InsnID*/0, /*OldInsnID*/0, /*OpIdx*/6, /*OperandRenderer*/GIMT_Encode2(GICR_renderExtractSWZ), // auxiliary
        GIR_MergeMemOperands, /*InsnID*/0, /*NumInsns*/1, /*MergeInsnID's*/0,
        GIR_ConstrainSelectedInstOperands, /*InsnID*/0,
        GIR_EraseFromParent, /*InsnID*/0,
        // GIR_Coverage, 4008,
        GIR_Done,
      // Label 6724: @494537
      GIM_Reject,
    // Label 6716: @494538
    GIM_Reject,
    // Label 6688: @494539
    GIM_Reject,
    // Label 128: @494540
    GIM_Try, /*On fail goto*//*Label 6725*/ GIMT_Encode4(495239),
      GIM_CheckType, /*MI*/0, /*Op*/0, /*Type*/GILLT_s32,
      GIM_CheckType, /*MI*/0, /*Op*/1, /*Type*/GILLT_v4s32,
      GIM_CheckType, /*MI*/0, /*Op*/2, /*Type*/GILLT_s32,
      GIM_CheckType, /*MI*/0, /*Op*/3, /*Type*/GILLT_s32,
      GIM_CheckType, /*MI*/0, /*Op*/4, /*Type*/GILLT_s32,
      GIM_CheckRegBankForClass, /*MI*/0, /*Op*/0, /*RC*/GIMT_Encode2(AMDGPU::AV_32RegClassID),
      GIM_Try, /*On fail goto*//*Label 6726*/ GIMT_Encode4(494886),
        GIM_CheckConstantInt8, /*MI*/0, /*Op*/2, 0,
        GIM_Try, /*On fail goto*//*Label 6727*/ GIMT_Encode4(494657), // Rule ID 4201 //
          GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasUnrestrictedSOffset),
          GIM_CheckConstantInt8, /*MI*/0, /*Op*/3, 0,
          // MIs[0] offset
          GIM_CheckIsImm, /*MI*/0, /*Op*/5,
          // MIs[0] auxiliary
          GIM_CheckIsImm, /*MI*/0, /*Op*/6,
          // MIs[0] Operand 7
          GIM_CheckLiteralInt, /*MI*/0, /*Op*/7, GIMT_Encode8(0),
          GIM_CheckComplexPattern, /*MI*/0, /*Op*/4, /*Renderer*/GIMT_Encode2(0), GIMT_Encode2(GICP_gi_buf_soffset),
          // (SIbuffer_load_byte:{ *:[i32] } v4i32:{ *:[v4i32] }:$rsrc, 0:{ *:[i32] }, 0:{ *:[i32] }, (BUFSOffset:{ *:[i32] } i32:{ *:[i32] }:$soffset), (timm:{ *:[i32] }):$offset, (timm:{ *:[i32] }):$auxiliary, 0:{ *:[i1] })  =>  (BUFFER_LOAD_SBYTE_OFFSET:{ *:[i32] } SReg_128:{ *:[v4i32] }:$rsrc, SCSrc_b32:{ *:[i32] }:$soffset, (timm:{ *:[i32] }):$offset, (extract_cpol:{ *:[i32] } ?:{ *:[i32] }:$auxiliary), (extract_swz:{ *:[i1] } ?:{ *:[i32] }:$auxiliary))
          GIR_BuildMI, /*InsnID*/0, /*Opcode*/GIMT_Encode2(AMDGPU::BUFFER_LOAD_SBYTE_OFFSET),
          GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/0, // DstI[vdata]
          GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/1, // rsrc
          GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/0, // soffset
          GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/5, // offset
          GIR_CustomOperandRenderer, /*InsnID*/0, /*OldInsnID*/0, /*OpIdx*/6, /*OperandRenderer*/GIMT_Encode2(GICR_renderExtractCPol), // auxiliary
          GIR_CustomOperandRenderer, /*InsnID*/0, /*OldInsnID*/0, /*OpIdx*/6, /*OperandRenderer*/GIMT_Encode2(GICR_renderExtractSWZ), // auxiliary
          GIR_MergeMemOperands, /*InsnID*/0, /*NumInsns*/1, /*MergeInsnID's*/0,
          GIR_ConstrainSelectedInstOperands, /*InsnID*/0,
          GIR_EraseFromParent, /*InsnID*/0,
          // GIR_Coverage, 4201,
          GIR_Done,
        // Label 6727: @494657
        GIM_Try, /*On fail goto*//*Label 6728*/ GIMT_Encode4(494732), // Rule ID 4205 //
          GIM_CheckConstantInt8, /*MI*/0, /*Op*/3, 0,
          // MIs[0] offset
          GIM_CheckIsImm, /*MI*/0, /*Op*/5,
          // MIs[0] auxiliary
          GIM_CheckIsImm, /*MI*/0, /*Op*/6,
          // MIs[0] Operand 7
          GIM_CheckLiteralInt, /*MI*/0, /*Op*/7, GIMT_Encode8(0),
          GIM_CheckComplexPattern, /*MI*/0, /*Op*/4, /*Renderer*/GIMT_Encode2(0), GIMT_Encode2(GICP_gi_buf_soffset),
          // (SIbuffer_load_byte:{ *:[i32] } v4i32:{ *:[v4i32] }:$rsrc, 0:{ *:[i32] }, 0:{ *:[i32] }, (BUFSOffset:{ *:[i32] } i32:{ *:[i32] }:$soffset), (timm:{ *:[i32] }):$offset, (timm:{ *:[i32] }):$auxiliary, 0:{ *:[i1] })  =>  (BUFFER_LOAD_SBYTE_VBUFFER_OFFSET:{ *:[i32] } SReg_128:{ *:[v4i32] }:$rsrc, SCSrc_b32:{ *:[i32] }:$soffset, (timm:{ *:[i32] }):$offset, (extract_cpol:{ *:[i32] } ?:{ *:[i32] }:$auxiliary), (extract_swz:{ *:[i1] } ?:{ *:[i32] }:$auxiliary))
          GIR_BuildMI, /*InsnID*/0, /*Opcode*/GIMT_Encode2(AMDGPU::BUFFER_LOAD_SBYTE_VBUFFER_OFFSET),
          GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/0, // DstI[vdata]
          GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/1, // rsrc
          GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/0, // soffset
          GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/5, // offset
          GIR_CustomOperandRenderer, /*InsnID*/0, /*OldInsnID*/0, /*OpIdx*/6, /*OperandRenderer*/GIMT_Encode2(GICR_renderExtractCPol), // auxiliary
          GIR_CustomOperandRenderer, /*InsnID*/0, /*OldInsnID*/0, /*OpIdx*/6, /*OperandRenderer*/GIMT_Encode2(GICR_renderExtractSWZ), // auxiliary
          GIR_MergeMemOperands, /*InsnID*/0, /*NumInsns*/1, /*MergeInsnID's*/0,
          GIR_ConstrainSelectedInstOperands, /*InsnID*/0,
          GIR_EraseFromParent, /*InsnID*/0,
          // GIR_Coverage, 4205,
          GIR_Done,
        // Label 6728: @494732
        GIM_Try, /*On fail goto*//*Label 6729*/ GIMT_Encode4(494810), // Rule ID 4202 //
          GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasUnrestrictedSOffset),
          // MIs[0] offset
          GIM_CheckIsImm, /*MI*/0, /*Op*/5,
          // MIs[0] auxiliary
          GIM_CheckIsImm, /*MI*/0, /*Op*/6,
          // MIs[0] Operand 7
          GIM_CheckLiteralInt, /*MI*/0, /*Op*/7, GIMT_Encode8(0),
          GIM_CheckComplexPattern, /*MI*/0, /*Op*/4, /*Renderer*/GIMT_Encode2(0), GIMT_Encode2(GICP_gi_buf_soffset),
          // (SIbuffer_load_byte:{ *:[i32] } v4i32:{ *:[v4i32] }:$rsrc, 0:{ *:[i32] }, i32:{ *:[i32] }:$voffset, (BUFSOffset:{ *:[i32] } i32:{ *:[i32] }:$soffset), (timm:{ *:[i32] }):$offset, (timm:{ *:[i32] }):$auxiliary, 0:{ *:[i1] })  =>  (BUFFER_LOAD_SBYTE_OFFEN:{ *:[i32] } VGPR_32:{ *:[i32] }:$voffset, SReg_128:{ *:[v4i32] }:$rsrc, SCSrc_b32:{ *:[i32] }:$soffset, (timm:{ *:[i32] }):$offset, (extract_cpol:{ *:[i32] } ?:{ *:[i32] }:$auxiliary), (extract_swz:{ *:[i1] } ?:{ *:[i32] }:$auxiliary))
          GIR_BuildMI, /*InsnID*/0, /*Opcode*/GIMT_Encode2(AMDGPU::BUFFER_LOAD_SBYTE_OFFEN),
          GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/0, // DstI[vdata]
          GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/3, // voffset
          GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/1, // rsrc
          GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/0, // soffset
          GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/5, // offset
          GIR_CustomOperandRenderer, /*InsnID*/0, /*OldInsnID*/0, /*OpIdx*/6, /*OperandRenderer*/GIMT_Encode2(GICR_renderExtractCPol), // auxiliary
          GIR_CustomOperandRenderer, /*InsnID*/0, /*OldInsnID*/0, /*OpIdx*/6, /*OperandRenderer*/GIMT_Encode2(GICR_renderExtractSWZ), // auxiliary
          GIR_MergeMemOperands, /*InsnID*/0, /*NumInsns*/1, /*MergeInsnID's*/0,
          GIR_ConstrainSelectedInstOperands, /*InsnID*/0,
          GIR_EraseFromParent, /*InsnID*/0,
          // GIR_Coverage, 4202,
          GIR_Done,
        // Label 6729: @494810
        GIM_Try, /*On fail goto*//*Label 6730*/ GIMT_Encode4(494885), // Rule ID 4206 //
          // MIs[0] offset
          GIM_CheckIsImm, /*MI*/0, /*Op*/5,
          // MIs[0] auxiliary
          GIM_CheckIsImm, /*MI*/0, /*Op*/6,
          // MIs[0] Operand 7
          GIM_CheckLiteralInt, /*MI*/0, /*Op*/7, GIMT_Encode8(0),
          GIM_CheckComplexPattern, /*MI*/0, /*Op*/4, /*Renderer*/GIMT_Encode2(0), GIMT_Encode2(GICP_gi_buf_soffset),
          // (SIbuffer_load_byte:{ *:[i32] } v4i32:{ *:[v4i32] }:$rsrc, 0:{ *:[i32] }, i32:{ *:[i32] }:$voffset, (BUFSOffset:{ *:[i32] } i32:{ *:[i32] }:$soffset), (timm:{ *:[i32] }):$offset, (timm:{ *:[i32] }):$auxiliary, 0:{ *:[i1] })  =>  (BUFFER_LOAD_SBYTE_VBUFFER_OFFEN:{ *:[i32] } VGPR_32:{ *:[i32] }:$voffset, SReg_128:{ *:[v4i32] }:$rsrc, SCSrc_b32:{ *:[i32] }:$soffset, (timm:{ *:[i32] }):$offset, (extract_cpol:{ *:[i32] } ?:{ *:[i32] }:$auxiliary), (extract_swz:{ *:[i1] } ?:{ *:[i32] }:$auxiliary))
          GIR_BuildMI, /*InsnID*/0, /*Opcode*/GIMT_Encode2(AMDGPU::BUFFER_LOAD_SBYTE_VBUFFER_OFFEN),
          GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/0, // DstI[vdata]
          GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/3, // voffset
          GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/1, // rsrc
          GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/0, // soffset
          GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/5, // offset
          GIR_CustomOperandRenderer, /*InsnID*/0, /*OldInsnID*/0, /*OpIdx*/6, /*OperandRenderer*/GIMT_Encode2(GICR_renderExtractCPol), // auxiliary
          GIR_CustomOperandRenderer, /*InsnID*/0, /*OldInsnID*/0, /*OpIdx*/6, /*OperandRenderer*/GIMT_Encode2(GICR_renderExtractSWZ), // auxiliary
          GIR_MergeMemOperands, /*InsnID*/0, /*NumInsns*/1, /*MergeInsnID's*/0,
          GIR_ConstrainSelectedInstOperands, /*InsnID*/0,
          GIR_EraseFromParent, /*InsnID*/0,
          // GIR_Coverage, 4206,
          GIR_Done,
        // Label 6730: @494885
        GIM_Reject,
      // Label 6726: @494886
      GIM_Try, /*On fail goto*//*Label 6731*/ GIMT_Encode4(495024),
        GIM_CheckConstantInt8, /*MI*/0, /*Op*/3, 0,
        GIM_CheckIsImm, /*MI*/0, /*Op*/5,
        GIM_CheckIsImm, /*MI*/0, /*Op*/6,
        GIM_CheckIsImm, /*MI*/0, /*Op*/7,
        GIM_Try, /*On fail goto*//*Label 6732*/ GIMT_Encode4(494965), // Rule ID 4203 //
          GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasUnrestrictedSOffset),
          GIM_CheckComplexPattern, /*MI*/0, /*Op*/4, /*Renderer*/GIMT_Encode2(0), GIMT_Encode2(GICP_gi_buf_soffset),
          // (SIbuffer_load_byte:{ *:[i32] } v4i32:{ *:[v4i32] }:$rsrc, i32:{ *:[i32] }:$vindex, 0:{ *:[i32] }, (BUFSOffset:{ *:[i32] } i32:{ *:[i32] }:$soffset), (timm:{ *:[i32] }):$offset, (timm:{ *:[i32] }):$auxiliary, (timm:{ *:[i1] }))  =>  (BUFFER_LOAD_SBYTE_IDXEN:{ *:[i32] } VGPR_32:{ *:[i32] }:$vindex, SReg_128:{ *:[v4i32] }:$rsrc, SCSrc_b32:{ *:[i32] }:$soffset, (timm:{ *:[i32] }):$offset, (extract_cpol:{ *:[i32] } ?:{ *:[i32] }:$auxiliary), (extract_swz:{ *:[i1] } ?:{ *:[i32] }:$auxiliary))
          GIR_BuildMI, /*InsnID*/0, /*Opcode*/GIMT_Encode2(AMDGPU::BUFFER_LOAD_SBYTE_IDXEN),
          GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/0, // DstI[vdata]
          GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/2, // vindex
          GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/1, // rsrc
          GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/0, // soffset
          GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/5, // offset
          GIR_CustomOperandRenderer, /*InsnID*/0, /*OldInsnID*/0, /*OpIdx*/6, /*OperandRenderer*/GIMT_Encode2(GICR_renderExtractCPol), // auxiliary
          GIR_CustomOperandRenderer, /*InsnID*/0, /*OldInsnID*/0, /*OpIdx*/6, /*OperandRenderer*/GIMT_Encode2(GICR_renderExtractSWZ), // auxiliary
          GIR_MergeMemOperands, /*InsnID*/0, /*NumInsns*/1, /*MergeInsnID's*/0,
          GIR_ConstrainSelectedInstOperands, /*InsnID*/0,
          GIR_EraseFromParent, /*InsnID*/0,
          // GIR_Coverage, 4203,
          GIR_Done,
        // Label 6732: @494965
        GIM_Try, /*On fail goto*//*Label 6733*/ GIMT_Encode4(495023), // Rule ID 4207 //
          GIM_CheckComplexPattern, /*MI*/0, /*Op*/4, /*Renderer*/GIMT_Encode2(0), GIMT_Encode2(GICP_gi_buf_soffset),
          // (SIbuffer_load_byte:{ *:[i32] } v4i32:{ *:[v4i32] }:$rsrc, i32:{ *:[i32] }:$vindex, 0:{ *:[i32] }, (BUFSOffset:{ *:[i32] } i32:{ *:[i32] }:$soffset), (timm:{ *:[i32] }):$offset, (timm:{ *:[i32] }):$auxiliary, (timm:{ *:[i1] }))  =>  (BUFFER_LOAD_SBYTE_VBUFFER_IDXEN:{ *:[i32] } VGPR_32:{ *:[i32] }:$vindex, SReg_128:{ *:[v4i32] }:$rsrc, SCSrc_b32:{ *:[i32] }:$soffset, (timm:{ *:[i32] }):$offset, (extract_cpol:{ *:[i32] } ?:{ *:[i32] }:$auxiliary), (extract_swz:{ *:[i1] } ?:{ *:[i32] }:$auxiliary))
          GIR_BuildMI, /*InsnID*/0, /*Opcode*/GIMT_Encode2(AMDGPU::BUFFER_LOAD_SBYTE_VBUFFER_IDXEN),
          GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/0, // DstI[vdata]
          GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/2, // vindex
          GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/1, // rsrc
          GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/0, // soffset
          GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/5, // offset
          GIR_CustomOperandRenderer, /*InsnID*/0, /*OldInsnID*/0, /*OpIdx*/6, /*OperandRenderer*/GIMT_Encode2(GICR_renderExtractCPol), // auxiliary
          GIR_CustomOperandRenderer, /*InsnID*/0, /*OldInsnID*/0, /*OpIdx*/6, /*OperandRenderer*/GIMT_Encode2(GICR_renderExtractSWZ), // auxiliary
          GIR_MergeMemOperands, /*InsnID*/0, /*NumInsns*/1, /*MergeInsnID's*/0,
          GIR_ConstrainSelectedInstOperands, /*InsnID*/0,
          GIR_EraseFromParent, /*InsnID*/0,
          // GIR_Coverage, 4207,
          GIR_Done,
        // Label 6733: @495023
        GIM_Reject,
      // Label 6731: @495024
      GIM_Try, /*On fail goto*//*Label 6734*/ GIMT_Encode4(495238),
        GIM_CheckIsImm, /*MI*/0, /*Op*/5,
        GIM_CheckIsImm, /*MI*/0, /*Op*/6,
        GIM_CheckIsImm, /*MI*/0, /*Op*/7,
        GIM_Try, /*On fail goto*//*Label 6735*/ GIMT_Encode4(495139), // Rule ID 4204 //
          GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasUnrestrictedSOffset),
          GIM_CheckComplexPattern, /*MI*/0, /*Op*/4, /*Renderer*/GIMT_Encode2(0), GIMT_Encode2(GICP_gi_buf_soffset),
          // (SIbuffer_load_byte:{ *:[i32] } v4i32:{ *:[v4i32] }:$rsrc, i32:{ *:[i32] }:$vindex, i32:{ *:[i32] }:$voffset, (BUFSOffset:{ *:[i32] } i32:{ *:[i32] }:$soffset), (timm:{ *:[i32] }):$offset, (timm:{ *:[i32] }):$auxiliary, (timm:{ *:[i1] }))  =>  (BUFFER_LOAD_SBYTE_BOTHEN:{ *:[i32] } (REG_SEQUENCE:{ *:[i64] } VReg_64:{ *:[i32] }, VGPR_32:{ *:[i32] }:$vindex, sub0:{ *:[i32] }, VGPR_32:{ *:[i32] }:$voffset, sub1:{ *:[i32] }), SReg_128:{ *:[v4i32] }:$rsrc, SCSrc_b32:{ *:[i32] }:$soffset, (timm:{ *:[i32] }):$offset, (extract_cpol:{ *:[i32] } ?:{ *:[i32] }:$auxiliary), (extract_swz:{ *:[i1] } ?:{ *:[i32] }:$auxiliary))
          GIR_MakeTempReg, /*TempRegID*/0, /*TypeID*/GILLT_s64,
          GIR_BuildMI, /*InsnID*/1, /*Opcode*/GIMT_Encode2(TargetOpcode::REG_SEQUENCE),
          GIR_AddTempRegister, /*InsnID*/1, /*TempRegID*/0, /*TempRegFlags*/GIMT_Encode2(RegState::Define),
          GIR_Copy, /*NewInsnID*/1, /*OldInsnID*/0, /*OpIdx*/2, // vindex
          GIR_AddImm8, /*InsnID*/1, /*SubRegIndex*/3,
          GIR_Copy, /*NewInsnID*/1, /*OldInsnID*/0, /*OpIdx*/3, // voffset
          GIR_AddImm8, /*InsnID*/1, /*SubRegIndex*/11,
          GIR_ConstrainOperandRC, /*InsnID*/1, /*Op*/0, GIMT_Encode2(AMDGPU::VReg_64RegClassID),
          GIR_ConstrainOperandRC, /*InsnID*/1, /*Op*/1, GIMT_Encode2(AMDGPU::VGPR_32RegClassID),
          GIR_ConstrainOperandRC, /*InsnID*/1, /*Op*/3, GIMT_Encode2(AMDGPU::VGPR_32RegClassID),
          GIR_BuildMI, /*InsnID*/0, /*Opcode*/GIMT_Encode2(AMDGPU::BUFFER_LOAD_SBYTE_BOTHEN),
          GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/0, // DstI[vdata]
          GIR_AddSimpleTempRegister, /*InsnID*/0, /*TempRegID*/0,
          GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/1, // rsrc
          GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/0, // soffset
          GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/5, // offset
          GIR_CustomOperandRenderer, /*InsnID*/0, /*OldInsnID*/0, /*OpIdx*/6, /*OperandRenderer*/GIMT_Encode2(GICR_renderExtractCPol), // auxiliary
          GIR_CustomOperandRenderer, /*InsnID*/0, /*OldInsnID*/0, /*OpIdx*/6, /*OperandRenderer*/GIMT_Encode2(GICR_renderExtractSWZ), // auxiliary
          GIR_MergeMemOperands, /*InsnID*/0, /*NumInsns*/1, /*MergeInsnID's*/0,
          GIR_ConstrainSelectedInstOperands, /*InsnID*/0,
          GIR_EraseFromParent, /*InsnID*/0,
          // GIR_Coverage, 4204,
          GIR_Done,
        // Label 6735: @495139
        GIM_Try, /*On fail goto*//*Label 6736*/ GIMT_Encode4(495237), // Rule ID 4208 //
          GIM_CheckComplexPattern, /*MI*/0, /*Op*/4, /*Renderer*/GIMT_Encode2(0), GIMT_Encode2(GICP_gi_buf_soffset),
          // (SIbuffer_load_byte:{ *:[i32] } v4i32:{ *:[v4i32] }:$rsrc, i32:{ *:[i32] }:$vindex, i32:{ *:[i32] }:$voffset, (BUFSOffset:{ *:[i32] } i32:{ *:[i32] }:$soffset), (timm:{ *:[i32] }):$offset, (timm:{ *:[i32] }):$auxiliary, (timm:{ *:[i1] }))  =>  (BUFFER_LOAD_SBYTE_VBUFFER_BOTHEN:{ *:[i32] } (REG_SEQUENCE:{ *:[i64] } VReg_64:{ *:[i32] }, VGPR_32:{ *:[i32] }:$vindex, sub0:{ *:[i32] }, VGPR_32:{ *:[i32] }:$voffset, sub1:{ *:[i32] }), SReg_128:{ *:[v4i32] }:$rsrc, SCSrc_b32:{ *:[i32] }:$soffset, (timm:{ *:[i32] }):$offset, (extract_cpol:{ *:[i32] } ?:{ *:[i32] }:$auxiliary), (extract_swz:{ *:[i1] } ?:{ *:[i32] }:$auxiliary))
          GIR_MakeTempReg, /*TempRegID*/0, /*TypeID*/GILLT_s64,
          GIR_BuildMI, /*InsnID*/1, /*Opcode*/GIMT_Encode2(TargetOpcode::REG_SEQUENCE),
          GIR_AddTempRegister, /*InsnID*/1, /*TempRegID*/0, /*TempRegFlags*/GIMT_Encode2(RegState::Define),
          GIR_Copy, /*NewInsnID*/1, /*OldInsnID*/0, /*OpIdx*/2, // vindex
          GIR_AddImm8, /*InsnID*/1, /*SubRegIndex*/3,
          GIR_Copy, /*NewInsnID*/1, /*OldInsnID*/0, /*OpIdx*/3, // voffset
          GIR_AddImm8, /*InsnID*/1, /*SubRegIndex*/11,
          GIR_ConstrainOperandRC, /*InsnID*/1, /*Op*/0, GIMT_Encode2(AMDGPU::VReg_64RegClassID),
          GIR_ConstrainOperandRC, /*InsnID*/1, /*Op*/1, GIMT_Encode2(AMDGPU::VGPR_32RegClassID),
          GIR_ConstrainOperandRC, /*InsnID*/1, /*Op*/3, GIMT_Encode2(AMDGPU::VGPR_32RegClassID),
          GIR_BuildMI, /*InsnID*/0, /*Opcode*/GIMT_Encode2(AMDGPU::BUFFER_LOAD_SBYTE_VBUFFER_BOTHEN),
          GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/0, // DstI[vdata]
          GIR_AddSimpleTempRegister, /*InsnID*/0, /*TempRegID*/0,
          GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/1, // rsrc
          GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/0, // soffset
          GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/5, // offset
          GIR_CustomOperandRenderer, /*InsnID*/0, /*OldInsnID*/0, /*OpIdx*/6, /*OperandRenderer*/GIMT_Encode2(GICR_renderExtractCPol), // auxiliary
          GIR_CustomOperandRenderer, /*InsnID*/0, /*OldInsnID*/0, /*OpIdx*/6, /*OperandRenderer*/GIMT_Encode2(GICR_renderExtractSWZ), // auxiliary
          GIR_MergeMemOperands, /*InsnID*/0, /*NumInsns*/1, /*MergeInsnID's*/0,
          GIR_ConstrainSelectedInstOperands, /*InsnID*/0,
          GIR_EraseFromParent, /*InsnID*/0,
          // GIR_Coverage, 4208,
          GIR_Done,
        // Label 6736: @495237
        GIM_Reject,
      // Label 6734: @495238
      GIM_Reject,
    // Label 6725: @495239
    GIM_Reject,
    // Label 129: @495240
    GIM_Try, /*On fail goto*//*Label 6737*/ GIMT_Encode4(495939),
      GIM_CheckType, /*MI*/0, /*Op*/0, /*Type*/GILLT_s32,
      GIM_CheckType, /*MI*/0, /*Op*/1, /*Type*/GILLT_v4s32,
      GIM_CheckType, /*MI*/0, /*Op*/2, /*Type*/GILLT_s32,
      GIM_CheckType, /*MI*/0, /*Op*/3, /*Type*/GILLT_s32,
      GIM_CheckType, /*MI*/0, /*Op*/4, /*Type*/GILLT_s32,
      GIM_CheckRegBankForClass, /*MI*/0, /*Op*/0, /*RC*/GIMT_Encode2(AMDGPU::AV_32RegClassID),
      GIM_Try, /*On fail goto*//*Label 6738*/ GIMT_Encode4(495586),
        GIM_CheckConstantInt8, /*MI*/0, /*Op*/2, 0,
        GIM_Try, /*On fail goto*//*Label 6739*/ GIMT_Encode4(495357), // Rule ID 4209 //
          GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasUnrestrictedSOffset),
          GIM_CheckConstantInt8, /*MI*/0, /*Op*/3, 0,
          // MIs[0] offset
          GIM_CheckIsImm, /*MI*/0, /*Op*/5,
          // MIs[0] auxiliary
          GIM_CheckIsImm, /*MI*/0, /*Op*/6,
          // MIs[0] Operand 7
          GIM_CheckLiteralInt, /*MI*/0, /*Op*/7, GIMT_Encode8(0),
          GIM_CheckComplexPattern, /*MI*/0, /*Op*/4, /*Renderer*/GIMT_Encode2(0), GIMT_Encode2(GICP_gi_buf_soffset),
          // (SIbuffer_load_short:{ *:[i32] } v4i32:{ *:[v4i32] }:$rsrc, 0:{ *:[i32] }, 0:{ *:[i32] }, (BUFSOffset:{ *:[i32] } i32:{ *:[i32] }:$soffset), (timm:{ *:[i32] }):$offset, (timm:{ *:[i32] }):$auxiliary, 0:{ *:[i1] })  =>  (BUFFER_LOAD_SSHORT_OFFSET:{ *:[i32] } SReg_128:{ *:[v4i32] }:$rsrc, SCSrc_b32:{ *:[i32] }:$soffset, (timm:{ *:[i32] }):$offset, (extract_cpol:{ *:[i32] } ?:{ *:[i32] }:$auxiliary), (extract_swz:{ *:[i1] } ?:{ *:[i32] }:$auxiliary))
          GIR_BuildMI, /*InsnID*/0, /*Opcode*/GIMT_Encode2(AMDGPU::BUFFER_LOAD_SSHORT_OFFSET),
          GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/0, // DstI[vdata]
          GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/1, // rsrc
          GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/0, // soffset
          GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/5, // offset
          GIR_CustomOperandRenderer, /*InsnID*/0, /*OldInsnID*/0, /*OpIdx*/6, /*OperandRenderer*/GIMT_Encode2(GICR_renderExtractCPol), // auxiliary
          GIR_CustomOperandRenderer, /*InsnID*/0, /*OldInsnID*/0, /*OpIdx*/6, /*OperandRenderer*/GIMT_Encode2(GICR_renderExtractSWZ), // auxiliary
          GIR_MergeMemOperands, /*InsnID*/0, /*NumInsns*/1, /*MergeInsnID's*/0,
          GIR_ConstrainSelectedInstOperands, /*InsnID*/0,
          GIR_EraseFromParent, /*InsnID*/0,
          // GIR_Coverage, 4209,
          GIR_Done,
        // Label 6739: @495357
        GIM_Try, /*On fail goto*//*Label 6740*/ GIMT_Encode4(495432), // Rule ID 4213 //
          GIM_CheckConstantInt8, /*MI*/0, /*Op*/3, 0,
          // MIs[0] offset
          GIM_CheckIsImm, /*MI*/0, /*Op*/5,
          // MIs[0] auxiliary
          GIM_CheckIsImm, /*MI*/0, /*Op*/6,
          // MIs[0] Operand 7
          GIM_CheckLiteralInt, /*MI*/0, /*Op*/7, GIMT_Encode8(0),
          GIM_CheckComplexPattern, /*MI*/0, /*Op*/4, /*Renderer*/GIMT_Encode2(0), GIMT_Encode2(GICP_gi_buf_soffset),
          // (SIbuffer_load_short:{ *:[i32] } v4i32:{ *:[v4i32] }:$rsrc, 0:{ *:[i32] }, 0:{ *:[i32] }, (BUFSOffset:{ *:[i32] } i32:{ *:[i32] }:$soffset), (timm:{ *:[i32] }):$offset, (timm:{ *:[i32] }):$auxiliary, 0:{ *:[i1] })  =>  (BUFFER_LOAD_SSHORT_VBUFFER_OFFSET:{ *:[i32] } SReg_128:{ *:[v4i32] }:$rsrc, SCSrc_b32:{ *:[i32] }:$soffset, (timm:{ *:[i32] }):$offset, (extract_cpol:{ *:[i32] } ?:{ *:[i32] }:$auxiliary), (extract_swz:{ *:[i1] } ?:{ *:[i32] }:$auxiliary))
          GIR_BuildMI, /*InsnID*/0, /*Opcode*/GIMT_Encode2(AMDGPU::BUFFER_LOAD_SSHORT_VBUFFER_OFFSET),
          GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/0, // DstI[vdata]
          GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/1, // rsrc
          GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/0, // soffset
          GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/5, // offset
          GIR_CustomOperandRenderer, /*InsnID*/0, /*OldInsnID*/0, /*OpIdx*/6, /*OperandRenderer*/GIMT_Encode2(GICR_renderExtractCPol), // auxiliary
          GIR_CustomOperandRenderer, /*InsnID*/0, /*OldInsnID*/0, /*OpIdx*/6, /*OperandRenderer*/GIMT_Encode2(GICR_renderExtractSWZ), // auxiliary
          GIR_MergeMemOperands, /*InsnID*/0, /*NumInsns*/1, /*MergeInsnID's*/0,
          GIR_ConstrainSelectedInstOperands, /*InsnID*/0,
          GIR_EraseFromParent, /*InsnID*/0,
          // GIR_Coverage, 4213,
          GIR_Done,
        // Label 6740: @495432
        GIM_Try, /*On fail goto*//*Label 6741*/ GIMT_Encode4(495510), // Rule ID 4210 //
          GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasUnrestrictedSOffset),
          // MIs[0] offset
          GIM_CheckIsImm, /*MI*/0, /*Op*/5,
          // MIs[0] auxiliary
          GIM_CheckIsImm, /*MI*/0, /*Op*/6,
          // MIs[0] Operand 7
          GIM_CheckLiteralInt, /*MI*/0, /*Op*/7, GIMT_Encode8(0),
          GIM_CheckComplexPattern, /*MI*/0, /*Op*/4, /*Renderer*/GIMT_Encode2(0), GIMT_Encode2(GICP_gi_buf_soffset),
          // (SIbuffer_load_short:{ *:[i32] } v4i32:{ *:[v4i32] }:$rsrc, 0:{ *:[i32] }, i32:{ *:[i32] }:$voffset, (BUFSOffset:{ *:[i32] } i32:{ *:[i32] }:$soffset), (timm:{ *:[i32] }):$offset, (timm:{ *:[i32] }):$auxiliary, 0:{ *:[i1] })  =>  (BUFFER_LOAD_SSHORT_OFFEN:{ *:[i32] } VGPR_32:{ *:[i32] }:$voffset, SReg_128:{ *:[v4i32] }:$rsrc, SCSrc_b32:{ *:[i32] }:$soffset, (timm:{ *:[i32] }):$offset, (extract_cpol:{ *:[i32] } ?:{ *:[i32] }:$auxiliary), (extract_swz:{ *:[i1] } ?:{ *:[i32] }:$auxiliary))
          GIR_BuildMI, /*InsnID*/0, /*Opcode*/GIMT_Encode2(AMDGPU::BUFFER_LOAD_SSHORT_OFFEN),
          GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/0, // DstI[vdata]
          GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/3, // voffset
          GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/1, // rsrc
          GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/0, // soffset
          GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/5, // offset
          GIR_CustomOperandRenderer, /*InsnID*/0, /*OldInsnID*/0, /*OpIdx*/6, /*OperandRenderer*/GIMT_Encode2(GICR_renderExtractCPol), // auxiliary
          GIR_CustomOperandRenderer, /*InsnID*/0, /*OldInsnID*/0, /*OpIdx*/6, /*OperandRenderer*/GIMT_Encode2(GICR_renderExtractSWZ), // auxiliary
          GIR_MergeMemOperands, /*InsnID*/0, /*NumInsns*/1, /*MergeInsnID's*/0,
          GIR_ConstrainSelectedInstOperands, /*InsnID*/0,
          GIR_EraseFromParent, /*InsnID*/0,
          // GIR_Coverage, 4210,
          GIR_Done,
        // Label 6741: @495510
        GIM_Try, /*On fail goto*//*Label 6742*/ GIMT_Encode4(495585), // Rule ID 4214 //
          // MIs[0] offset
          GIM_CheckIsImm, /*MI*/0, /*Op*/5,
          // MIs[0] auxiliary
          GIM_CheckIsImm, /*MI*/0, /*Op*/6,
          // MIs[0] Operand 7
          GIM_CheckLiteralInt, /*MI*/0, /*Op*/7, GIMT_Encode8(0),
          GIM_CheckComplexPattern, /*MI*/0, /*Op*/4, /*Renderer*/GIMT_Encode2(0), GIMT_Encode2(GICP_gi_buf_soffset),
          // (SIbuffer_load_short:{ *:[i32] } v4i32:{ *:[v4i32] }:$rsrc, 0:{ *:[i32] }, i32:{ *:[i32] }:$voffset, (BUFSOffset:{ *:[i32] } i32:{ *:[i32] }:$soffset), (timm:{ *:[i32] }):$offset, (timm:{ *:[i32] }):$auxiliary, 0:{ *:[i1] })  =>  (BUFFER_LOAD_SSHORT_VBUFFER_OFFEN:{ *:[i32] } VGPR_32:{ *:[i32] }:$voffset, SReg_128:{ *:[v4i32] }:$rsrc, SCSrc_b32:{ *:[i32] }:$soffset, (timm:{ *:[i32] }):$offset, (extract_cpol:{ *:[i32] } ?:{ *:[i32] }:$auxiliary), (extract_swz:{ *:[i1] } ?:{ *:[i32] }:$auxiliary))
          GIR_BuildMI, /*InsnID*/0, /*Opcode*/GIMT_Encode2(AMDGPU::BUFFER_LOAD_SSHORT_VBUFFER_OFFEN),
          GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/0, // DstI[vdata]
          GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/3, // voffset
          GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/1, // rsrc
          GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/0, // soffset
          GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/5, // offset
          GIR_CustomOperandRenderer, /*InsnID*/0, /*OldInsnID*/0, /*OpIdx*/6, /*OperandRenderer*/GIMT_Encode2(GICR_renderExtractCPol), // auxiliary
          GIR_CustomOperandRenderer, /*InsnID*/0, /*OldInsnID*/0, /*OpIdx*/6, /*OperandRenderer*/GIMT_Encode2(GICR_renderExtractSWZ), // auxiliary
          GIR_MergeMemOperands, /*InsnID*/0, /*NumInsns*/1, /*MergeInsnID's*/0,
          GIR_ConstrainSelectedInstOperands, /*InsnID*/0,
          GIR_EraseFromParent, /*InsnID*/0,
          // GIR_Coverage, 4214,
          GIR_Done,
        // Label 6742: @495585
        GIM_Reject,
      // Label 6738: @495586
      GIM_Try, /*On fail goto*//*Label 6743*/ GIMT_Encode4(495724),
        GIM_CheckConstantInt8, /*MI*/0, /*Op*/3, 0,
        GIM_CheckIsImm, /*MI*/0, /*Op*/5,
        GIM_CheckIsImm, /*MI*/0, /*Op*/6,
        GIM_CheckIsImm, /*MI*/0, /*Op*/7,
        GIM_Try, /*On fail goto*//*Label 6744*/ GIMT_Encode4(495665), // Rule ID 4211 //
          GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasUnrestrictedSOffset),
          GIM_CheckComplexPattern, /*MI*/0, /*Op*/4, /*Renderer*/GIMT_Encode2(0), GIMT_Encode2(GICP_gi_buf_soffset),
          // (SIbuffer_load_short:{ *:[i32] } v4i32:{ *:[v4i32] }:$rsrc, i32:{ *:[i32] }:$vindex, 0:{ *:[i32] }, (BUFSOffset:{ *:[i32] } i32:{ *:[i32] }:$soffset), (timm:{ *:[i32] }):$offset, (timm:{ *:[i32] }):$auxiliary, (timm:{ *:[i1] }))  =>  (BUFFER_LOAD_SSHORT_IDXEN:{ *:[i32] } VGPR_32:{ *:[i32] }:$vindex, SReg_128:{ *:[v4i32] }:$rsrc, SCSrc_b32:{ *:[i32] }:$soffset, (timm:{ *:[i32] }):$offset, (extract_cpol:{ *:[i32] } ?:{ *:[i32] }:$auxiliary), (extract_swz:{ *:[i1] } ?:{ *:[i32] }:$auxiliary))
          GIR_BuildMI, /*InsnID*/0, /*Opcode*/GIMT_Encode2(AMDGPU::BUFFER_LOAD_SSHORT_IDXEN),
          GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/0, // DstI[vdata]
          GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/2, // vindex
          GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/1, // rsrc
          GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/0, // soffset
          GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/5, // offset
          GIR_CustomOperandRenderer, /*InsnID*/0, /*OldInsnID*/0, /*OpIdx*/6, /*OperandRenderer*/GIMT_Encode2(GICR_renderExtractCPol), // auxiliary
          GIR_CustomOperandRenderer, /*InsnID*/0, /*OldInsnID*/0, /*OpIdx*/6, /*OperandRenderer*/GIMT_Encode2(GICR_renderExtractSWZ), // auxiliary
          GIR_MergeMemOperands, /*InsnID*/0, /*NumInsns*/1, /*MergeInsnID's*/0,
          GIR_ConstrainSelectedInstOperands, /*InsnID*/0,
          GIR_EraseFromParent, /*InsnID*/0,
          // GIR_Coverage, 4211,
          GIR_Done,
        // Label 6744: @495665
        GIM_Try, /*On fail goto*//*Label 6745*/ GIMT_Encode4(495723), // Rule ID 4215 //
          GIM_CheckComplexPattern, /*MI*/0, /*Op*/4, /*Renderer*/GIMT_Encode2(0), GIMT_Encode2(GICP_gi_buf_soffset),
          // (SIbuffer_load_short:{ *:[i32] } v4i32:{ *:[v4i32] }:$rsrc, i32:{ *:[i32] }:$vindex, 0:{ *:[i32] }, (BUFSOffset:{ *:[i32] } i32:{ *:[i32] }:$soffset), (timm:{ *:[i32] }):$offset, (timm:{ *:[i32] }):$auxiliary, (timm:{ *:[i1] }))  =>  (BUFFER_LOAD_SSHORT_VBUFFER_IDXEN:{ *:[i32] } VGPR_32:{ *:[i32] }:$vindex, SReg_128:{ *:[v4i32] }:$rsrc, SCSrc_b32:{ *:[i32] }:$soffset, (timm:{ *:[i32] }):$offset, (extract_cpol:{ *:[i32] } ?:{ *:[i32] }:$auxiliary), (extract_swz:{ *:[i1] } ?:{ *:[i32] }:$auxiliary))
          GIR_BuildMI, /*InsnID*/0, /*Opcode*/GIMT_Encode2(AMDGPU::BUFFER_LOAD_SSHORT_VBUFFER_IDXEN),
          GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/0, // DstI[vdata]
          GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/2, // vindex
          GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/1, // rsrc
          GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/0, // soffset
          GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/5, // offset
          GIR_CustomOperandRenderer, /*InsnID*/0, /*OldInsnID*/0, /*OpIdx*/6, /*OperandRenderer*/GIMT_Encode2(GICR_renderExtractCPol), // auxiliary
          GIR_CustomOperandRenderer, /*InsnID*/0, /*OldInsnID*/0, /*OpIdx*/6, /*OperandRenderer*/GIMT_Encode2(GICR_renderExtractSWZ), // auxiliary
          GIR_MergeMemOperands, /*InsnID*/0, /*NumInsns*/1, /*MergeInsnID's*/0,
          GIR_ConstrainSelectedInstOperands, /*InsnID*/0,
          GIR_EraseFromParent, /*InsnID*/0,
          // GIR_Coverage, 4215,
          GIR_Done,
        // Label 6745: @495723
        GIM_Reject,
      // Label 6743: @495724
      GIM_Try, /*On fail goto*//*Label 6746*/ GIMT_Encode4(495938),
        GIM_CheckIsImm, /*MI*/0, /*Op*/5,
        GIM_CheckIsImm, /*MI*/0, /*Op*/6,
        GIM_CheckIsImm, /*MI*/0, /*Op*/7,
        GIM_Try, /*On fail goto*//*Label 6747*/ GIMT_Encode4(495839), // Rule ID 4212 //
          GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasUnrestrictedSOffset),
          GIM_CheckComplexPattern, /*MI*/0, /*Op*/4, /*Renderer*/GIMT_Encode2(0), GIMT_Encode2(GICP_gi_buf_soffset),
          // (SIbuffer_load_short:{ *:[i32] } v4i32:{ *:[v4i32] }:$rsrc, i32:{ *:[i32] }:$vindex, i32:{ *:[i32] }:$voffset, (BUFSOffset:{ *:[i32] } i32:{ *:[i32] }:$soffset), (timm:{ *:[i32] }):$offset, (timm:{ *:[i32] }):$auxiliary, (timm:{ *:[i1] }))  =>  (BUFFER_LOAD_SSHORT_BOTHEN:{ *:[i32] } (REG_SEQUENCE:{ *:[i64] } VReg_64:{ *:[i32] }, VGPR_32:{ *:[i32] }:$vindex, sub0:{ *:[i32] }, VGPR_32:{ *:[i32] }:$voffset, sub1:{ *:[i32] }), SReg_128:{ *:[v4i32] }:$rsrc, SCSrc_b32:{ *:[i32] }:$soffset, (timm:{ *:[i32] }):$offset, (extract_cpol:{ *:[i32] } ?:{ *:[i32] }:$auxiliary), (extract_swz:{ *:[i1] } ?:{ *:[i32] }:$auxiliary))
          GIR_MakeTempReg, /*TempRegID*/0, /*TypeID*/GILLT_s64,
          GIR_BuildMI, /*InsnID*/1, /*Opcode*/GIMT_Encode2(TargetOpcode::REG_SEQUENCE),
          GIR_AddTempRegister, /*InsnID*/1, /*TempRegID*/0, /*TempRegFlags*/GIMT_Encode2(RegState::Define),
          GIR_Copy, /*NewInsnID*/1, /*OldInsnID*/0, /*OpIdx*/2, // vindex
          GIR_AddImm8, /*InsnID*/1, /*SubRegIndex*/3,
          GIR_Copy, /*NewInsnID*/1, /*OldInsnID*/0, /*OpIdx*/3, // voffset
          GIR_AddImm8, /*InsnID*/1, /*SubRegIndex*/11,
          GIR_ConstrainOperandRC, /*InsnID*/1, /*Op*/0, GIMT_Encode2(AMDGPU::VReg_64RegClassID),
          GIR_ConstrainOperandRC, /*InsnID*/1, /*Op*/1, GIMT_Encode2(AMDGPU::VGPR_32RegClassID),
          GIR_ConstrainOperandRC, /*InsnID*/1, /*Op*/3, GIMT_Encode2(AMDGPU::VGPR_32RegClassID),
          GIR_BuildMI, /*InsnID*/0, /*Opcode*/GIMT_Encode2(AMDGPU::BUFFER_LOAD_SSHORT_BOTHEN),
          GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/0, // DstI[vdata]
          GIR_AddSimpleTempRegister, /*InsnID*/0, /*TempRegID*/0,
          GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/1, // rsrc
          GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/0, // soffset
          GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/5, // offset
          GIR_CustomOperandRenderer, /*InsnID*/0, /*OldInsnID*/0, /*OpIdx*/6, /*OperandRenderer*/GIMT_Encode2(GICR_renderExtractCPol), // auxiliary
          GIR_CustomOperandRenderer, /*InsnID*/0, /*OldInsnID*/0, /*OpIdx*/6, /*OperandRenderer*/GIMT_Encode2(GICR_renderExtractSWZ), // auxiliary
          GIR_MergeMemOperands, /*InsnID*/0, /*NumInsns*/1, /*MergeInsnID's*/0,
          GIR_ConstrainSelectedInstOperands, /*InsnID*/0,
          GIR_EraseFromParent, /*InsnID*/0,
          // GIR_Coverage, 4212,
          GIR_Done,
        // Label 6747: @495839
        GIM_Try, /*On fail goto*//*Label 6748*/ GIMT_Encode4(495937), // Rule ID 4216 //
          GIM_CheckComplexPattern, /*MI*/0, /*Op*/4, /*Renderer*/GIMT_Encode2(0), GIMT_Encode2(GICP_gi_buf_soffset),
          // (SIbuffer_load_short:{ *:[i32] } v4i32:{ *:[v4i32] }:$rsrc, i32:{ *:[i32] }:$vindex, i32:{ *:[i32] }:$voffset, (BUFSOffset:{ *:[i32] } i32:{ *:[i32] }:$soffset), (timm:{ *:[i32] }):$offset, (timm:{ *:[i32] }):$auxiliary, (timm:{ *:[i1] }))  =>  (BUFFER_LOAD_SSHORT_VBUFFER_BOTHEN:{ *:[i32] } (REG_SEQUENCE:{ *:[i64] } VReg_64:{ *:[i32] }, VGPR_32:{ *:[i32] }:$vindex, sub0:{ *:[i32] }, VGPR_32:{ *:[i32] }:$voffset, sub1:{ *:[i32] }), SReg_128:{ *:[v4i32] }:$rsrc, SCSrc_b32:{ *:[i32] }:$soffset, (timm:{ *:[i32] }):$offset, (extract_cpol:{ *:[i32] } ?:{ *:[i32] }:$auxiliary), (extract_swz:{ *:[i1] } ?:{ *:[i32] }:$auxiliary))
          GIR_MakeTempReg, /*TempRegID*/0, /*TypeID*/GILLT_s64,
          GIR_BuildMI, /*InsnID*/1, /*Opcode*/GIMT_Encode2(TargetOpcode::REG_SEQUENCE),
          GIR_AddTempRegister, /*InsnID*/1, /*TempRegID*/0, /*TempRegFlags*/GIMT_Encode2(RegState::Define),
          GIR_Copy, /*NewInsnID*/1, /*OldInsnID*/0, /*OpIdx*/2, // vindex
          GIR_AddImm8, /*InsnID*/1, /*SubRegIndex*/3,
          GIR_Copy, /*NewInsnID*/1, /*OldInsnID*/0, /*OpIdx*/3, // voffset
          GIR_AddImm8, /*InsnID*/1, /*SubRegIndex*/11,
          GIR_ConstrainOperandRC, /*InsnID*/1, /*Op*/0, GIMT_Encode2(AMDGPU::VReg_64RegClassID),
          GIR_ConstrainOperandRC, /*InsnID*/1, /*Op*/1, GIMT_Encode2(AMDGPU::VGPR_32RegClassID),
          GIR_ConstrainOperandRC, /*InsnID*/1, /*Op*/3, GIMT_Encode2(AMDGPU::VGPR_32RegClassID),
          GIR_BuildMI, /*InsnID*/0, /*Opcode*/GIMT_Encode2(AMDGPU::BUFFER_LOAD_SSHORT_VBUFFER_BOTHEN),
          GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/0, // DstI[vdata]
          GIR_AddSimpleTempRegister, /*InsnID*/0, /*TempRegID*/0,
          GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/1, // rsrc
          GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/0, // soffset
          GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/5, // offset
          GIR_CustomOperandRenderer, /*InsnID*/0, /*OldInsnID*/0, /*OpIdx*/6, /*OperandRenderer*/GIMT_Encode2(GICR_renderExtractCPol), // auxiliary
          GIR_CustomOperandRenderer, /*InsnID*/0, /*OldInsnID*/0, /*OpIdx*/6, /*OperandRenderer*/GIMT_Encode2(GICR_renderExtractSWZ), // auxiliary
          GIR_MergeMemOperands, /*InsnID*/0, /*NumInsns*/1, /*MergeInsnID's*/0,
          GIR_ConstrainSelectedInstOperands, /*InsnID*/0,
          GIR_EraseFromParent, /*InsnID*/0,
          // GIR_Coverage, 4216,
          GIR_Done,
        // Label 6748: @495937
        GIM_Reject,
      // Label 6746: @495938
      GIM_Reject,
    // Label 6737: @495939
    GIM_Reject,
    // Label 130: @495940
    GIM_Try, /*On fail goto*//*Label 6749*/ GIMT_Encode4(496639),
      GIM_CheckType, /*MI*/0, /*Op*/0, /*Type*/GILLT_s32,
      GIM_CheckType, /*MI*/0, /*Op*/1, /*Type*/GILLT_v4s32,
      GIM_CheckType, /*MI*/0, /*Op*/2, /*Type*/GILLT_s32,
      GIM_CheckType, /*MI*/0, /*Op*/3, /*Type*/GILLT_s32,
      GIM_CheckType, /*MI*/0, /*Op*/4, /*Type*/GILLT_s32,
      GIM_CheckRegBankForClass, /*MI*/0, /*Op*/0, /*RC*/GIMT_Encode2(AMDGPU::AV_32RegClassID),
      GIM_Try, /*On fail goto*//*Label 6750*/ GIMT_Encode4(496286),
        GIM_CheckConstantInt8, /*MI*/0, /*Op*/2, 0,
        GIM_Try, /*On fail goto*//*Label 6751*/ GIMT_Encode4(496057), // Rule ID 4217 //
          GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasUnrestrictedSOffset),
          GIM_CheckConstantInt8, /*MI*/0, /*Op*/3, 0,
          // MIs[0] offset
          GIM_CheckIsImm, /*MI*/0, /*Op*/5,
          // MIs[0] auxiliary
          GIM_CheckIsImm, /*MI*/0, /*Op*/6,
          // MIs[0] Operand 7
          GIM_CheckLiteralInt, /*MI*/0, /*Op*/7, GIMT_Encode8(0),
          GIM_CheckComplexPattern, /*MI*/0, /*Op*/4, /*Renderer*/GIMT_Encode2(0), GIMT_Encode2(GICP_gi_buf_soffset),
          // (SIbuffer_load_ubyte:{ *:[i32] } v4i32:{ *:[v4i32] }:$rsrc, 0:{ *:[i32] }, 0:{ *:[i32] }, (BUFSOffset:{ *:[i32] } i32:{ *:[i32] }:$soffset), (timm:{ *:[i32] }):$offset, (timm:{ *:[i32] }):$auxiliary, 0:{ *:[i1] })  =>  (BUFFER_LOAD_UBYTE_OFFSET:{ *:[i32] } SReg_128:{ *:[v4i32] }:$rsrc, SCSrc_b32:{ *:[i32] }:$soffset, (timm:{ *:[i32] }):$offset, (extract_cpol:{ *:[i32] } ?:{ *:[i32] }:$auxiliary), (extract_swz:{ *:[i1] } ?:{ *:[i32] }:$auxiliary))
          GIR_BuildMI, /*InsnID*/0, /*Opcode*/GIMT_Encode2(AMDGPU::BUFFER_LOAD_UBYTE_OFFSET),
          GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/0, // DstI[vdata]
          GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/1, // rsrc
          GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/0, // soffset
          GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/5, // offset
          GIR_CustomOperandRenderer, /*InsnID*/0, /*OldInsnID*/0, /*OpIdx*/6, /*OperandRenderer*/GIMT_Encode2(GICR_renderExtractCPol), // auxiliary
          GIR_CustomOperandRenderer, /*InsnID*/0, /*OldInsnID*/0, /*OpIdx*/6, /*OperandRenderer*/GIMT_Encode2(GICR_renderExtractSWZ), // auxiliary
          GIR_MergeMemOperands, /*InsnID*/0, /*NumInsns*/1, /*MergeInsnID's*/0,
          GIR_ConstrainSelectedInstOperands, /*InsnID*/0,
          GIR_EraseFromParent, /*InsnID*/0,
          // GIR_Coverage, 4217,
          GIR_Done,
        // Label 6751: @496057
        GIM_Try, /*On fail goto*//*Label 6752*/ GIMT_Encode4(496132), // Rule ID 4221 //
          GIM_CheckConstantInt8, /*MI*/0, /*Op*/3, 0,
          // MIs[0] offset
          GIM_CheckIsImm, /*MI*/0, /*Op*/5,
          // MIs[0] auxiliary
          GIM_CheckIsImm, /*MI*/0, /*Op*/6,
          // MIs[0] Operand 7
          GIM_CheckLiteralInt, /*MI*/0, /*Op*/7, GIMT_Encode8(0),
          GIM_CheckComplexPattern, /*MI*/0, /*Op*/4, /*Renderer*/GIMT_Encode2(0), GIMT_Encode2(GICP_gi_buf_soffset),
          // (SIbuffer_load_ubyte:{ *:[i32] } v4i32:{ *:[v4i32] }:$rsrc, 0:{ *:[i32] }, 0:{ *:[i32] }, (BUFSOffset:{ *:[i32] } i32:{ *:[i32] }:$soffset), (timm:{ *:[i32] }):$offset, (timm:{ *:[i32] }):$auxiliary, 0:{ *:[i1] })  =>  (BUFFER_LOAD_UBYTE_VBUFFER_OFFSET:{ *:[i32] } SReg_128:{ *:[v4i32] }:$rsrc, SCSrc_b32:{ *:[i32] }:$soffset, (timm:{ *:[i32] }):$offset, (extract_cpol:{ *:[i32] } ?:{ *:[i32] }:$auxiliary), (extract_swz:{ *:[i1] } ?:{ *:[i32] }:$auxiliary))
          GIR_BuildMI, /*InsnID*/0, /*Opcode*/GIMT_Encode2(AMDGPU::BUFFER_LOAD_UBYTE_VBUFFER_OFFSET),
          GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/0, // DstI[vdata]
          GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/1, // rsrc
          GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/0, // soffset
          GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/5, // offset
          GIR_CustomOperandRenderer, /*InsnID*/0, /*OldInsnID*/0, /*OpIdx*/6, /*OperandRenderer*/GIMT_Encode2(GICR_renderExtractCPol), // auxiliary
          GIR_CustomOperandRenderer, /*InsnID*/0, /*OldInsnID*/0, /*OpIdx*/6, /*OperandRenderer*/GIMT_Encode2(GICR_renderExtractSWZ), // auxiliary
          GIR_MergeMemOperands, /*InsnID*/0, /*NumInsns*/1, /*MergeInsnID's*/0,
          GIR_ConstrainSelectedInstOperands, /*InsnID*/0,
          GIR_EraseFromParent, /*InsnID*/0,
          // GIR_Coverage, 4221,
          GIR_Done,
        // Label 6752: @496132
        GIM_Try, /*On fail goto*//*Label 6753*/ GIMT_Encode4(496210), // Rule ID 4218 //
          GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasUnrestrictedSOffset),
          // MIs[0] offset
          GIM_CheckIsImm, /*MI*/0, /*Op*/5,
          // MIs[0] auxiliary
          GIM_CheckIsImm, /*MI*/0, /*Op*/6,
          // MIs[0] Operand 7
          GIM_CheckLiteralInt, /*MI*/0, /*Op*/7, GIMT_Encode8(0),
          GIM_CheckComplexPattern, /*MI*/0, /*Op*/4, /*Renderer*/GIMT_Encode2(0), GIMT_Encode2(GICP_gi_buf_soffset),
          // (SIbuffer_load_ubyte:{ *:[i32] } v4i32:{ *:[v4i32] }:$rsrc, 0:{ *:[i32] }, i32:{ *:[i32] }:$voffset, (BUFSOffset:{ *:[i32] } i32:{ *:[i32] }:$soffset), (timm:{ *:[i32] }):$offset, (timm:{ *:[i32] }):$auxiliary, 0:{ *:[i1] })  =>  (BUFFER_LOAD_UBYTE_OFFEN:{ *:[i32] } VGPR_32:{ *:[i32] }:$voffset, SReg_128:{ *:[v4i32] }:$rsrc, SCSrc_b32:{ *:[i32] }:$soffset, (timm:{ *:[i32] }):$offset, (extract_cpol:{ *:[i32] } ?:{ *:[i32] }:$auxiliary), (extract_swz:{ *:[i1] } ?:{ *:[i32] }:$auxiliary))
          GIR_BuildMI, /*InsnID*/0, /*Opcode*/GIMT_Encode2(AMDGPU::BUFFER_LOAD_UBYTE_OFFEN),
          GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/0, // DstI[vdata]
          GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/3, // voffset
          GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/1, // rsrc
          GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/0, // soffset
          GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/5, // offset
          GIR_CustomOperandRenderer, /*InsnID*/0, /*OldInsnID*/0, /*OpIdx*/6, /*OperandRenderer*/GIMT_Encode2(GICR_renderExtractCPol), // auxiliary
          GIR_CustomOperandRenderer, /*InsnID*/0, /*OldInsnID*/0, /*OpIdx*/6, /*OperandRenderer*/GIMT_Encode2(GICR_renderExtractSWZ), // auxiliary
          GIR_MergeMemOperands, /*InsnID*/0, /*NumInsns*/1, /*MergeInsnID's*/0,
          GIR_ConstrainSelectedInstOperands, /*InsnID*/0,
          GIR_EraseFromParent, /*InsnID*/0,
          // GIR_Coverage, 4218,
          GIR_Done,
        // Label 6753: @496210
        GIM_Try, /*On fail goto*//*Label 6754*/ GIMT_Encode4(496285), // Rule ID 4222 //
          // MIs[0] offset
          GIM_CheckIsImm, /*MI*/0, /*Op*/5,
          // MIs[0] auxiliary
          GIM_CheckIsImm, /*MI*/0, /*Op*/6,
          // MIs[0] Operand 7
          GIM_CheckLiteralInt, /*MI*/0, /*Op*/7, GIMT_Encode8(0),
          GIM_CheckComplexPattern, /*MI*/0, /*Op*/4, /*Renderer*/GIMT_Encode2(0), GIMT_Encode2(GICP_gi_buf_soffset),
          // (SIbuffer_load_ubyte:{ *:[i32] } v4i32:{ *:[v4i32] }:$rsrc, 0:{ *:[i32] }, i32:{ *:[i32] }:$voffset, (BUFSOffset:{ *:[i32] } i32:{ *:[i32] }:$soffset), (timm:{ *:[i32] }):$offset, (timm:{ *:[i32] }):$auxiliary, 0:{ *:[i1] })  =>  (BUFFER_LOAD_UBYTE_VBUFFER_OFFEN:{ *:[i32] } VGPR_32:{ *:[i32] }:$voffset, SReg_128:{ *:[v4i32] }:$rsrc, SCSrc_b32:{ *:[i32] }:$soffset, (timm:{ *:[i32] }):$offset, (extract_cpol:{ *:[i32] } ?:{ *:[i32] }:$auxiliary), (extract_swz:{ *:[i1] } ?:{ *:[i32] }:$auxiliary))
          GIR_BuildMI, /*InsnID*/0, /*Opcode*/GIMT_Encode2(AMDGPU::BUFFER_LOAD_UBYTE_VBUFFER_OFFEN),
          GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/0, // DstI[vdata]
          GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/3, // voffset
          GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/1, // rsrc
          GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/0, // soffset
          GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/5, // offset
          GIR_CustomOperandRenderer, /*InsnID*/0, /*OldInsnID*/0, /*OpIdx*/6, /*OperandRenderer*/GIMT_Encode2(GICR_renderExtractCPol), // auxiliary
          GIR_CustomOperandRenderer, /*InsnID*/0, /*OldInsnID*/0, /*OpIdx*/6, /*OperandRenderer*/GIMT_Encode2(GICR_renderExtractSWZ), // auxiliary
          GIR_MergeMemOperands, /*InsnID*/0, /*NumInsns*/1, /*MergeInsnID's*/0,
          GIR_ConstrainSelectedInstOperands, /*InsnID*/0,
          GIR_EraseFromParent, /*InsnID*/0,
          // GIR_Coverage, 4222,
          GIR_Done,
        // Label 6754: @496285
        GIM_Reject,
      // Label 6750: @496286
      GIM_Try, /*On fail goto*//*Label 6755*/ GIMT_Encode4(496424),
        GIM_CheckConstantInt8, /*MI*/0, /*Op*/3, 0,
        GIM_CheckIsImm, /*MI*/0, /*Op*/5,
        GIM_CheckIsImm, /*MI*/0, /*Op*/6,
        GIM_CheckIsImm, /*MI*/0, /*Op*/7,
        GIM_Try, /*On fail goto*//*Label 6756*/ GIMT_Encode4(496365), // Rule ID 4219 //
          GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasUnrestrictedSOffset),
          GIM_CheckComplexPattern, /*MI*/0, /*Op*/4, /*Renderer*/GIMT_Encode2(0), GIMT_Encode2(GICP_gi_buf_soffset),
          // (SIbuffer_load_ubyte:{ *:[i32] } v4i32:{ *:[v4i32] }:$rsrc, i32:{ *:[i32] }:$vindex, 0:{ *:[i32] }, (BUFSOffset:{ *:[i32] } i32:{ *:[i32] }:$soffset), (timm:{ *:[i32] }):$offset, (timm:{ *:[i32] }):$auxiliary, (timm:{ *:[i1] }))  =>  (BUFFER_LOAD_UBYTE_IDXEN:{ *:[i32] } VGPR_32:{ *:[i32] }:$vindex, SReg_128:{ *:[v4i32] }:$rsrc, SCSrc_b32:{ *:[i32] }:$soffset, (timm:{ *:[i32] }):$offset, (extract_cpol:{ *:[i32] } ?:{ *:[i32] }:$auxiliary), (extract_swz:{ *:[i1] } ?:{ *:[i32] }:$auxiliary))
          GIR_BuildMI, /*InsnID*/0, /*Opcode*/GIMT_Encode2(AMDGPU::BUFFER_LOAD_UBYTE_IDXEN),
          GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/0, // DstI[vdata]
          GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/2, // vindex
          GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/1, // rsrc
          GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/0, // soffset
          GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/5, // offset
          GIR_CustomOperandRenderer, /*InsnID*/0, /*OldInsnID*/0, /*OpIdx*/6, /*OperandRenderer*/GIMT_Encode2(GICR_renderExtractCPol), // auxiliary
          GIR_CustomOperandRenderer, /*InsnID*/0, /*OldInsnID*/0, /*OpIdx*/6, /*OperandRenderer*/GIMT_Encode2(GICR_renderExtractSWZ), // auxiliary
          GIR_MergeMemOperands, /*InsnID*/0, /*NumInsns*/1, /*MergeInsnID's*/0,
          GIR_ConstrainSelectedInstOperands, /*InsnID*/0,
          GIR_EraseFromParent, /*InsnID*/0,
          // GIR_Coverage, 4219,
          GIR_Done,
        // Label 6756: @496365
        GIM_Try, /*On fail goto*//*Label 6757*/ GIMT_Encode4(496423), // Rule ID 4223 //
          GIM_CheckComplexPattern, /*MI*/0, /*Op*/4, /*Renderer*/GIMT_Encode2(0), GIMT_Encode2(GICP_gi_buf_soffset),
          // (SIbuffer_load_ubyte:{ *:[i32] } v4i32:{ *:[v4i32] }:$rsrc, i32:{ *:[i32] }:$vindex, 0:{ *:[i32] }, (BUFSOffset:{ *:[i32] } i32:{ *:[i32] }:$soffset), (timm:{ *:[i32] }):$offset, (timm:{ *:[i32] }):$auxiliary, (timm:{ *:[i1] }))  =>  (BUFFER_LOAD_UBYTE_VBUFFER_IDXEN:{ *:[i32] } VGPR_32:{ *:[i32] }:$vindex, SReg_128:{ *:[v4i32] }:$rsrc, SCSrc_b32:{ *:[i32] }:$soffset, (timm:{ *:[i32] }):$offset, (extract_cpol:{ *:[i32] } ?:{ *:[i32] }:$auxiliary), (extract_swz:{ *:[i1] } ?:{ *:[i32] }:$auxiliary))
          GIR_BuildMI, /*InsnID*/0, /*Opcode*/GIMT_Encode2(AMDGPU::BUFFER_LOAD_UBYTE_VBUFFER_IDXEN),
          GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/0, // DstI[vdata]
          GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/2, // vindex
          GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/1, // rsrc
          GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/0, // soffset
          GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/5, // offset
          GIR_CustomOperandRenderer, /*InsnID*/0, /*OldInsnID*/0, /*OpIdx*/6, /*OperandRenderer*/GIMT_Encode2(GICR_renderExtractCPol), // auxiliary
          GIR_CustomOperandRenderer, /*InsnID*/0, /*OldInsnID*/0, /*OpIdx*/6, /*OperandRenderer*/GIMT_Encode2(GICR_renderExtractSWZ), // auxiliary
          GIR_MergeMemOperands, /*InsnID*/0, /*NumInsns*/1, /*MergeInsnID's*/0,
          GIR_ConstrainSelectedInstOperands, /*InsnID*/0,
          GIR_EraseFromParent, /*InsnID*/0,
          // GIR_Coverage, 4223,
          GIR_Done,
        // Label 6757: @496423
        GIM_Reject,
      // Label 6755: @496424
      GIM_Try, /*On fail goto*//*Label 6758*/ GIMT_Encode4(496638),
        GIM_CheckIsImm, /*MI*/0, /*Op*/5,
        GIM_CheckIsImm, /*MI*/0, /*Op*/6,
        GIM_CheckIsImm, /*MI*/0, /*Op*/7,
        GIM_Try, /*On fail goto*//*Label 6759*/ GIMT_Encode4(496539), // Rule ID 4220 //
          GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasUnrestrictedSOffset),
          GIM_CheckComplexPattern, /*MI*/0, /*Op*/4, /*Renderer*/GIMT_Encode2(0), GIMT_Encode2(GICP_gi_buf_soffset),
          // (SIbuffer_load_ubyte:{ *:[i32] } v4i32:{ *:[v4i32] }:$rsrc, i32:{ *:[i32] }:$vindex, i32:{ *:[i32] }:$voffset, (BUFSOffset:{ *:[i32] } i32:{ *:[i32] }:$soffset), (timm:{ *:[i32] }):$offset, (timm:{ *:[i32] }):$auxiliary, (timm:{ *:[i1] }))  =>  (BUFFER_LOAD_UBYTE_BOTHEN:{ *:[i32] } (REG_SEQUENCE:{ *:[i64] } VReg_64:{ *:[i32] }, VGPR_32:{ *:[i32] }:$vindex, sub0:{ *:[i32] }, VGPR_32:{ *:[i32] }:$voffset, sub1:{ *:[i32] }), SReg_128:{ *:[v4i32] }:$rsrc, SCSrc_b32:{ *:[i32] }:$soffset, (timm:{ *:[i32] }):$offset, (extract_cpol:{ *:[i32] } ?:{ *:[i32] }:$auxiliary), (extract_swz:{ *:[i1] } ?:{ *:[i32] }:$auxiliary))
          GIR_MakeTempReg, /*TempRegID*/0, /*TypeID*/GILLT_s64,
          GIR_BuildMI, /*InsnID*/1, /*Opcode*/GIMT_Encode2(TargetOpcode::REG_SEQUENCE),
          GIR_AddTempRegister, /*InsnID*/1, /*TempRegID*/0, /*TempRegFlags*/GIMT_Encode2(RegState::Define),
          GIR_Copy, /*NewInsnID*/1, /*OldInsnID*/0, /*OpIdx*/2, // vindex
          GIR_AddImm8, /*InsnID*/1, /*SubRegIndex*/3,
          GIR_Copy, /*NewInsnID*/1, /*OldInsnID*/0, /*OpIdx*/3, // voffset
          GIR_AddImm8, /*InsnID*/1, /*SubRegIndex*/11,
          GIR_ConstrainOperandRC, /*InsnID*/1, /*Op*/0, GIMT_Encode2(AMDGPU::VReg_64RegClassID),
          GIR_ConstrainOperandRC, /*InsnID*/1, /*Op*/1, GIMT_Encode2(AMDGPU::VGPR_32RegClassID),
          GIR_ConstrainOperandRC, /*InsnID*/1, /*Op*/3, GIMT_Encode2(AMDGPU::VGPR_32RegClassID),
          GIR_BuildMI, /*InsnID*/0, /*Opcode*/GIMT_Encode2(AMDGPU::BUFFER_LOAD_UBYTE_BOTHEN),
          GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/0, // DstI[vdata]
          GIR_AddSimpleTempRegister, /*InsnID*/0, /*TempRegID*/0,
          GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/1, // rsrc
          GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/0, // soffset
          GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/5, // offset
          GIR_CustomOperandRenderer, /*InsnID*/0, /*OldInsnID*/0, /*OpIdx*/6, /*OperandRenderer*/GIMT_Encode2(GICR_renderExtractCPol), // auxiliary
          GIR_CustomOperandRenderer, /*InsnID*/0, /*OldInsnID*/0, /*OpIdx*/6, /*OperandRenderer*/GIMT_Encode2(GICR_renderExtractSWZ), // auxiliary
          GIR_MergeMemOperands, /*InsnID*/0, /*NumInsns*/1, /*MergeInsnID's*/0,
          GIR_ConstrainSelectedInstOperands, /*InsnID*/0,
          GIR_EraseFromParent, /*InsnID*/0,
          // GIR_Coverage, 4220,
          GIR_Done,
        // Label 6759: @496539
        GIM_Try, /*On fail goto*//*Label 6760*/ GIMT_Encode4(496637), // Rule ID 4224 //
          GIM_CheckComplexPattern, /*MI*/0, /*Op*/4, /*Renderer*/GIMT_Encode2(0), GIMT_Encode2(GICP_gi_buf_soffset),
          // (SIbuffer_load_ubyte:{ *:[i32] } v4i32:{ *:[v4i32] }:$rsrc, i32:{ *:[i32] }:$vindex, i32:{ *:[i32] }:$voffset, (BUFSOffset:{ *:[i32] } i32:{ *:[i32] }:$soffset), (timm:{ *:[i32] }):$offset, (timm:{ *:[i32] }):$auxiliary, (timm:{ *:[i1] }))  =>  (BUFFER_LOAD_UBYTE_VBUFFER_BOTHEN:{ *:[i32] } (REG_SEQUENCE:{ *:[i64] } VReg_64:{ *:[i32] }, VGPR_32:{ *:[i32] }:$vindex, sub0:{ *:[i32] }, VGPR_32:{ *:[i32] }:$voffset, sub1:{ *:[i32] }), SReg_128:{ *:[v4i32] }:$rsrc, SCSrc_b32:{ *:[i32] }:$soffset, (timm:{ *:[i32] }):$offset, (extract_cpol:{ *:[i32] } ?:{ *:[i32] }:$auxiliary), (extract_swz:{ *:[i1] } ?:{ *:[i32] }:$auxiliary))
          GIR_MakeTempReg, /*TempRegID*/0, /*TypeID*/GILLT_s64,
          GIR_BuildMI, /*InsnID*/1, /*Opcode*/GIMT_Encode2(TargetOpcode::REG_SEQUENCE),
          GIR_AddTempRegister, /*InsnID*/1, /*TempRegID*/0, /*TempRegFlags*/GIMT_Encode2(RegState::Define),
          GIR_Copy, /*NewInsnID*/1, /*OldInsnID*/0, /*OpIdx*/2, // vindex
          GIR_AddImm8, /*InsnID*/1, /*SubRegIndex*/3,
          GIR_Copy, /*NewInsnID*/1, /*OldInsnID*/0, /*OpIdx*/3, // voffset
          GIR_AddImm8, /*InsnID*/1, /*SubRegIndex*/11,
          GIR_ConstrainOperandRC, /*InsnID*/1, /*Op*/0, GIMT_Encode2(AMDGPU::VReg_64RegClassID),
          GIR_ConstrainOperandRC, /*InsnID*/1, /*Op*/1, GIMT_Encode2(AMDGPU::VGPR_32RegClassID),
          GIR_ConstrainOperandRC, /*InsnID*/1, /*Op*/3, GIMT_Encode2(AMDGPU::VGPR_32RegClassID),
          GIR_BuildMI, /*InsnID*/0, /*Opcode*/GIMT_Encode2(AMDGPU::BUFFER_LOAD_UBYTE_VBUFFER_BOTHEN),
          GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/0, // DstI[vdata]
          GIR_AddSimpleTempRegister, /*InsnID*/0, /*TempRegID*/0,
          GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/1, // rsrc
          GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/0, // soffset
          GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/5, // offset
          GIR_CustomOperandRenderer, /*InsnID*/0, /*OldInsnID*/0, /*OpIdx*/6, /*OperandRenderer*/GIMT_Encode2(GICR_renderExtractCPol), // auxiliary
          GIR_CustomOperandRenderer, /*InsnID*/0, /*OldInsnID*/0, /*OpIdx*/6, /*OperandRenderer*/GIMT_Encode2(GICR_renderExtractSWZ), // auxiliary
          GIR_MergeMemOperands, /*InsnID*/0, /*NumInsns*/1, /*MergeInsnID's*/0,
          GIR_ConstrainSelectedInstOperands, /*InsnID*/0,
          GIR_EraseFromParent, /*InsnID*/0,
          // GIR_Coverage, 4224,
          GIR_Done,
        // Label 6760: @496637
        GIM_Reject,
      // Label 6758: @496638
      GIM_Reject,
    // Label 6749: @496639
    GIM_Reject,
    // Label 131: @496640
    GIM_Try, /*On fail goto*//*Label 6761*/ GIMT_Encode4(497339),
      GIM_CheckType, /*MI*/0, /*Op*/0, /*Type*/GILLT_s32,
      GIM_CheckType, /*MI*/0, /*Op*/1, /*Type*/GILLT_v4s32,
      GIM_CheckType, /*MI*/0, /*Op*/2, /*Type*/GILLT_s32,
      GIM_CheckType, /*MI*/0, /*Op*/3, /*Type*/GILLT_s32,
      GIM_CheckType, /*MI*/0, /*Op*/4, /*Type*/GILLT_s32,
      GIM_CheckRegBankForClass, /*MI*/0, /*Op*/0, /*RC*/GIMT_Encode2(AMDGPU::AV_32RegClassID),
      GIM_Try, /*On fail goto*//*Label 6762*/ GIMT_Encode4(496986),
        GIM_CheckConstantInt8, /*MI*/0, /*Op*/2, 0,
        GIM_Try, /*On fail goto*//*Label 6763*/ GIMT_Encode4(496757), // Rule ID 4225 //
          GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasUnrestrictedSOffset),
          GIM_CheckConstantInt8, /*MI*/0, /*Op*/3, 0,
          // MIs[0] offset
          GIM_CheckIsImm, /*MI*/0, /*Op*/5,
          // MIs[0] auxiliary
          GIM_CheckIsImm, /*MI*/0, /*Op*/6,
          // MIs[0] Operand 7
          GIM_CheckLiteralInt, /*MI*/0, /*Op*/7, GIMT_Encode8(0),
          GIM_CheckComplexPattern, /*MI*/0, /*Op*/4, /*Renderer*/GIMT_Encode2(0), GIMT_Encode2(GICP_gi_buf_soffset),
          // (SIbuffer_load_ushort:{ *:[i32] } v4i32:{ *:[v4i32] }:$rsrc, 0:{ *:[i32] }, 0:{ *:[i32] }, (BUFSOffset:{ *:[i32] } i32:{ *:[i32] }:$soffset), (timm:{ *:[i32] }):$offset, (timm:{ *:[i32] }):$auxiliary, 0:{ *:[i1] })  =>  (BUFFER_LOAD_USHORT_OFFSET:{ *:[i32] } SReg_128:{ *:[v4i32] }:$rsrc, SCSrc_b32:{ *:[i32] }:$soffset, (timm:{ *:[i32] }):$offset, (extract_cpol:{ *:[i32] } ?:{ *:[i32] }:$auxiliary), (extract_swz:{ *:[i1] } ?:{ *:[i32] }:$auxiliary))
          GIR_BuildMI, /*InsnID*/0, /*Opcode*/GIMT_Encode2(AMDGPU::BUFFER_LOAD_USHORT_OFFSET),
          GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/0, // DstI[vdata]
          GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/1, // rsrc
          GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/0, // soffset
          GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/5, // offset
          GIR_CustomOperandRenderer, /*InsnID*/0, /*OldInsnID*/0, /*OpIdx*/6, /*OperandRenderer*/GIMT_Encode2(GICR_renderExtractCPol), // auxiliary
          GIR_CustomOperandRenderer, /*InsnID*/0, /*OldInsnID*/0, /*OpIdx*/6, /*OperandRenderer*/GIMT_Encode2(GICR_renderExtractSWZ), // auxiliary
          GIR_MergeMemOperands, /*InsnID*/0, /*NumInsns*/1, /*MergeInsnID's*/0,
          GIR_ConstrainSelectedInstOperands, /*InsnID*/0,
          GIR_EraseFromParent, /*InsnID*/0,
          // GIR_Coverage, 4225,
          GIR_Done,
        // Label 6763: @496757
        GIM_Try, /*On fail goto*//*Label 6764*/ GIMT_Encode4(496832), // Rule ID 4229 //
          GIM_CheckConstantInt8, /*MI*/0, /*Op*/3, 0,
          // MIs[0] offset
          GIM_CheckIsImm, /*MI*/0, /*Op*/5,
          // MIs[0] auxiliary
          GIM_CheckIsImm, /*MI*/0, /*Op*/6,
          // MIs[0] Operand 7
          GIM_CheckLiteralInt, /*MI*/0, /*Op*/7, GIMT_Encode8(0),
          GIM_CheckComplexPattern, /*MI*/0, /*Op*/4, /*Renderer*/GIMT_Encode2(0), GIMT_Encode2(GICP_gi_buf_soffset),
          // (SIbuffer_load_ushort:{ *:[i32] } v4i32:{ *:[v4i32] }:$rsrc, 0:{ *:[i32] }, 0:{ *:[i32] }, (BUFSOffset:{ *:[i32] } i32:{ *:[i32] }:$soffset), (timm:{ *:[i32] }):$offset, (timm:{ *:[i32] }):$auxiliary, 0:{ *:[i1] })  =>  (BUFFER_LOAD_USHORT_VBUFFER_OFFSET:{ *:[i32] } SReg_128:{ *:[v4i32] }:$rsrc, SCSrc_b32:{ *:[i32] }:$soffset, (timm:{ *:[i32] }):$offset, (extract_cpol:{ *:[i32] } ?:{ *:[i32] }:$auxiliary), (extract_swz:{ *:[i1] } ?:{ *:[i32] }:$auxiliary))
          GIR_BuildMI, /*InsnID*/0, /*Opcode*/GIMT_Encode2(AMDGPU::BUFFER_LOAD_USHORT_VBUFFER_OFFSET),
          GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/0, // DstI[vdata]
          GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/1, // rsrc
          GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/0, // soffset
          GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/5, // offset
          GIR_CustomOperandRenderer, /*InsnID*/0, /*OldInsnID*/0, /*OpIdx*/6, /*OperandRenderer*/GIMT_Encode2(GICR_renderExtractCPol), // auxiliary
          GIR_CustomOperandRenderer, /*InsnID*/0, /*OldInsnID*/0, /*OpIdx*/6, /*OperandRenderer*/GIMT_Encode2(GICR_renderExtractSWZ), // auxiliary
          GIR_MergeMemOperands, /*InsnID*/0, /*NumInsns*/1, /*MergeInsnID's*/0,
          GIR_ConstrainSelectedInstOperands, /*InsnID*/0,
          GIR_EraseFromParent, /*InsnID*/0,
          // GIR_Coverage, 4229,
          GIR_Done,
        // Label 6764: @496832
        GIM_Try, /*On fail goto*//*Label 6765*/ GIMT_Encode4(496910), // Rule ID 4226 //
          GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasUnrestrictedSOffset),
          // MIs[0] offset
          GIM_CheckIsImm, /*MI*/0, /*Op*/5,
          // MIs[0] auxiliary
          GIM_CheckIsImm, /*MI*/0, /*Op*/6,
          // MIs[0] Operand 7
          GIM_CheckLiteralInt, /*MI*/0, /*Op*/7, GIMT_Encode8(0),
          GIM_CheckComplexPattern, /*MI*/0, /*Op*/4, /*Renderer*/GIMT_Encode2(0), GIMT_Encode2(GICP_gi_buf_soffset),
          // (SIbuffer_load_ushort:{ *:[i32] } v4i32:{ *:[v4i32] }:$rsrc, 0:{ *:[i32] }, i32:{ *:[i32] }:$voffset, (BUFSOffset:{ *:[i32] } i32:{ *:[i32] }:$soffset), (timm:{ *:[i32] }):$offset, (timm:{ *:[i32] }):$auxiliary, 0:{ *:[i1] })  =>  (BUFFER_LOAD_USHORT_OFFEN:{ *:[i32] } VGPR_32:{ *:[i32] }:$voffset, SReg_128:{ *:[v4i32] }:$rsrc, SCSrc_b32:{ *:[i32] }:$soffset, (timm:{ *:[i32] }):$offset, (extract_cpol:{ *:[i32] } ?:{ *:[i32] }:$auxiliary), (extract_swz:{ *:[i1] } ?:{ *:[i32] }:$auxiliary))
          GIR_BuildMI, /*InsnID*/0, /*Opcode*/GIMT_Encode2(AMDGPU::BUFFER_LOAD_USHORT_OFFEN),
          GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/0, // DstI[vdata]
          GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/3, // voffset
          GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/1, // rsrc
          GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/0, // soffset
          GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/5, // offset
          GIR_CustomOperandRenderer, /*InsnID*/0, /*OldInsnID*/0, /*OpIdx*/6, /*OperandRenderer*/GIMT_Encode2(GICR_renderExtractCPol), // auxiliary
          GIR_CustomOperandRenderer, /*InsnID*/0, /*OldInsnID*/0, /*OpIdx*/6, /*OperandRenderer*/GIMT_Encode2(GICR_renderExtractSWZ), // auxiliary
          GIR_MergeMemOperands, /*InsnID*/0, /*NumInsns*/1, /*MergeInsnID's*/0,
          GIR_ConstrainSelectedInstOperands, /*InsnID*/0,
          GIR_EraseFromParent, /*InsnID*/0,
          // GIR_Coverage, 4226,
          GIR_Done,
        // Label 6765: @496910
        GIM_Try, /*On fail goto*//*Label 6766*/ GIMT_Encode4(496985), // Rule ID 4230 //
          // MIs[0] offset
          GIM_CheckIsImm, /*MI*/0, /*Op*/5,
          // MIs[0] auxiliary
          GIM_CheckIsImm, /*MI*/0, /*Op*/6,
          // MIs[0] Operand 7
          GIM_CheckLiteralInt, /*MI*/0, /*Op*/7, GIMT_Encode8(0),
          GIM_CheckComplexPattern, /*MI*/0, /*Op*/4, /*Renderer*/GIMT_Encode2(0), GIMT_Encode2(GICP_gi_buf_soffset),
          // (SIbuffer_load_ushort:{ *:[i32] } v4i32:{ *:[v4i32] }:$rsrc, 0:{ *:[i32] }, i32:{ *:[i32] }:$voffset, (BUFSOffset:{ *:[i32] } i32:{ *:[i32] }:$soffset), (timm:{ *:[i32] }):$offset, (timm:{ *:[i32] }):$auxiliary, 0:{ *:[i1] })  =>  (BUFFER_LOAD_USHORT_VBUFFER_OFFEN:{ *:[i32] } VGPR_32:{ *:[i32] }:$voffset, SReg_128:{ *:[v4i32] }:$rsrc, SCSrc_b32:{ *:[i32] }:$soffset, (timm:{ *:[i32] }):$offset, (extract_cpol:{ *:[i32] } ?:{ *:[i32] }:$auxiliary), (extract_swz:{ *:[i1] } ?:{ *:[i32] }:$auxiliary))
          GIR_BuildMI, /*InsnID*/0, /*Opcode*/GIMT_Encode2(AMDGPU::BUFFER_LOAD_USHORT_VBUFFER_OFFEN),
          GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/0, // DstI[vdata]
          GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/3, // voffset
          GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/1, // rsrc
          GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/0, // soffset
          GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/5, // offset
          GIR_CustomOperandRenderer, /*InsnID*/0, /*OldInsnID*/0, /*OpIdx*/6, /*OperandRenderer*/GIMT_Encode2(GICR_renderExtractCPol), // auxiliary
          GIR_CustomOperandRenderer, /*InsnID*/0, /*OldInsnID*/0, /*OpIdx*/6, /*OperandRenderer*/GIMT_Encode2(GICR_renderExtractSWZ), // auxiliary
          GIR_MergeMemOperands, /*InsnID*/0, /*NumInsns*/1, /*MergeInsnID's*/0,
          GIR_ConstrainSelectedInstOperands, /*InsnID*/0,
          GIR_EraseFromParent, /*InsnID*/0,
          // GIR_Coverage, 4230,
          GIR_Done,
        // Label 6766: @496985
        GIM_Reject,
      // Label 6762: @496986
      GIM_Try, /*On fail goto*//*Label 6767*/ GIMT_Encode4(497124),
        GIM_CheckConstantInt8, /*MI*/0, /*Op*/3, 0,
        GIM_CheckIsImm, /*MI*/0, /*Op*/5,
        GIM_CheckIsImm, /*MI*/0, /*Op*/6,
        GIM_CheckIsImm, /*MI*/0, /*Op*/7,
        GIM_Try, /*On fail goto*//*Label 6768*/ GIMT_Encode4(497065), // Rule ID 4227 //
          GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasUnrestrictedSOffset),
          GIM_CheckComplexPattern, /*MI*/0, /*Op*/4, /*Renderer*/GIMT_Encode2(0), GIMT_Encode2(GICP_gi_buf_soffset),
          // (SIbuffer_load_ushort:{ *:[i32] } v4i32:{ *:[v4i32] }:$rsrc, i32:{ *:[i32] }:$vindex, 0:{ *:[i32] }, (BUFSOffset:{ *:[i32] } i32:{ *:[i32] }:$soffset), (timm:{ *:[i32] }):$offset, (timm:{ *:[i32] }):$auxiliary, (timm:{ *:[i1] }))  =>  (BUFFER_LOAD_USHORT_IDXEN:{ *:[i32] } VGPR_32:{ *:[i32] }:$vindex, SReg_128:{ *:[v4i32] }:$rsrc, SCSrc_b32:{ *:[i32] }:$soffset, (timm:{ *:[i32] }):$offset, (extract_cpol:{ *:[i32] } ?:{ *:[i32] }:$auxiliary), (extract_swz:{ *:[i1] } ?:{ *:[i32] }:$auxiliary))
          GIR_BuildMI, /*InsnID*/0, /*Opcode*/GIMT_Encode2(AMDGPU::BUFFER_LOAD_USHORT_IDXEN),
          GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/0, // DstI[vdata]
          GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/2, // vindex
          GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/1, // rsrc
          GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/0, // soffset
          GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/5, // offset
          GIR_CustomOperandRenderer, /*InsnID*/0, /*OldInsnID*/0, /*OpIdx*/6, /*OperandRenderer*/GIMT_Encode2(GICR_renderExtractCPol), // auxiliary
          GIR_CustomOperandRenderer, /*InsnID*/0, /*OldInsnID*/0, /*OpIdx*/6, /*OperandRenderer*/GIMT_Encode2(GICR_renderExtractSWZ), // auxiliary
          GIR_MergeMemOperands, /*InsnID*/0, /*NumInsns*/1, /*MergeInsnID's*/0,
          GIR_ConstrainSelectedInstOperands, /*InsnID*/0,
          GIR_EraseFromParent, /*InsnID*/0,
          // GIR_Coverage, 4227,
          GIR_Done,
        // Label 6768: @497065
        GIM_Try, /*On fail goto*//*Label 6769*/ GIMT_Encode4(497123), // Rule ID 4231 //
          GIM_CheckComplexPattern, /*MI*/0, /*Op*/4, /*Renderer*/GIMT_Encode2(0), GIMT_Encode2(GICP_gi_buf_soffset),
          // (SIbuffer_load_ushort:{ *:[i32] } v4i32:{ *:[v4i32] }:$rsrc, i32:{ *:[i32] }:$vindex, 0:{ *:[i32] }, (BUFSOffset:{ *:[i32] } i32:{ *:[i32] }:$soffset), (timm:{ *:[i32] }):$offset, (timm:{ *:[i32] }):$auxiliary, (timm:{ *:[i1] }))  =>  (BUFFER_LOAD_USHORT_VBUFFER_IDXEN:{ *:[i32] } VGPR_32:{ *:[i32] }:$vindex, SReg_128:{ *:[v4i32] }:$rsrc, SCSrc_b32:{ *:[i32] }:$soffset, (timm:{ *:[i32] }):$offset, (extract_cpol:{ *:[i32] } ?:{ *:[i32] }:$auxiliary), (extract_swz:{ *:[i1] } ?:{ *:[i32] }:$auxiliary))
          GIR_BuildMI, /*InsnID*/0, /*Opcode*/GIMT_Encode2(AMDGPU::BUFFER_LOAD_USHORT_VBUFFER_IDXEN),
          GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/0, // DstI[vdata]
          GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/2, // vindex
          GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/1, // rsrc
          GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/0, // soffset
          GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/5, // offset
          GIR_CustomOperandRenderer, /*InsnID*/0, /*OldInsnID*/0, /*OpIdx*/6, /*OperandRenderer*/GIMT_Encode2(GICR_renderExtractCPol), // auxiliary
          GIR_CustomOperandRenderer, /*InsnID*/0, /*OldInsnID*/0, /*OpIdx*/6, /*OperandRenderer*/GIMT_Encode2(GICR_renderExtractSWZ), // auxiliary
          GIR_MergeMemOperands, /*InsnID*/0, /*NumInsns*/1, /*MergeInsnID's*/0,
          GIR_ConstrainSelectedInstOperands, /*InsnID*/0,
          GIR_EraseFromParent, /*InsnID*/0,
          // GIR_Coverage, 4231,
          GIR_Done,
        // Label 6769: @497123
        GIM_Reject,
      // Label 6767: @497124
      GIM_Try, /*On fail goto*//*Label 6770*/ GIMT_Encode4(497338),
        GIM_CheckIsImm, /*MI*/0, /*Op*/5,
        GIM_CheckIsImm, /*MI*/0, /*Op*/6,
        GIM_CheckIsImm, /*MI*/0, /*Op*/7,
        GIM_Try, /*On fail goto*//*Label 6771*/ GIMT_Encode4(497239), // Rule ID 4228 //
          GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasUnrestrictedSOffset),
          GIM_CheckComplexPattern, /*MI*/0, /*Op*/4, /*Renderer*/GIMT_Encode2(0), GIMT_Encode2(GICP_gi_buf_soffset),
          // (SIbuffer_load_ushort:{ *:[i32] } v4i32:{ *:[v4i32] }:$rsrc, i32:{ *:[i32] }:$vindex, i32:{ *:[i32] }:$voffset, (BUFSOffset:{ *:[i32] } i32:{ *:[i32] }:$soffset), (timm:{ *:[i32] }):$offset, (timm:{ *:[i32] }):$auxiliary, (timm:{ *:[i1] }))  =>  (BUFFER_LOAD_USHORT_BOTHEN:{ *:[i32] } (REG_SEQUENCE:{ *:[i64] } VReg_64:{ *:[i32] }, VGPR_32:{ *:[i32] }:$vindex, sub0:{ *:[i32] }, VGPR_32:{ *:[i32] }:$voffset, sub1:{ *:[i32] }), SReg_128:{ *:[v4i32] }:$rsrc, SCSrc_b32:{ *:[i32] }:$soffset, (timm:{ *:[i32] }):$offset, (extract_cpol:{ *:[i32] } ?:{ *:[i32] }:$auxiliary), (extract_swz:{ *:[i1] } ?:{ *:[i32] }:$auxiliary))
          GIR_MakeTempReg, /*TempRegID*/0, /*TypeID*/GILLT_s64,
          GIR_BuildMI, /*InsnID*/1, /*Opcode*/GIMT_Encode2(TargetOpcode::REG_SEQUENCE),
          GIR_AddTempRegister, /*InsnID*/1, /*TempRegID*/0, /*TempRegFlags*/GIMT_Encode2(RegState::Define),
          GIR_Copy, /*NewInsnID*/1, /*OldInsnID*/0, /*OpIdx*/2, // vindex
          GIR_AddImm8, /*InsnID*/1, /*SubRegIndex*/3,
          GIR_Copy, /*NewInsnID*/1, /*OldInsnID*/0, /*OpIdx*/3, // voffset
          GIR_AddImm8, /*InsnID*/1, /*SubRegIndex*/11,
          GIR_ConstrainOperandRC, /*InsnID*/1, /*Op*/0, GIMT_Encode2(AMDGPU::VReg_64RegClassID),
          GIR_ConstrainOperandRC, /*InsnID*/1, /*Op*/1, GIMT_Encode2(AMDGPU::VGPR_32RegClassID),
          GIR_ConstrainOperandRC, /*InsnID*/1, /*Op*/3, GIMT_Encode2(AMDGPU::VGPR_32RegClassID),
          GIR_BuildMI, /*InsnID*/0, /*Opcode*/GIMT_Encode2(AMDGPU::BUFFER_LOAD_USHORT_BOTHEN),
          GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/0, // DstI[vdata]
          GIR_AddSimpleTempRegister, /*InsnID*/0, /*TempRegID*/0,
          GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/1, // rsrc
          GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/0, // soffset
          GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/5, // offset
          GIR_CustomOperandRenderer, /*InsnID*/0, /*OldInsnID*/0, /*OpIdx*/6, /*OperandRenderer*/GIMT_Encode2(GICR_renderExtractCPol), // auxiliary
          GIR_CustomOperandRenderer, /*InsnID*/0, /*OldInsnID*/0, /*OpIdx*/6, /*OperandRenderer*/GIMT_Encode2(GICR_renderExtractSWZ), // auxiliary
          GIR_MergeMemOperands, /*InsnID*/0, /*NumInsns*/1, /*MergeInsnID's*/0,
          GIR_ConstrainSelectedInstOperands, /*InsnID*/0,
          GIR_EraseFromParent, /*InsnID*/0,
          // GIR_Coverage, 4228,
          GIR_Done,
        // Label 6771: @497239
        GIM_Try, /*On fail goto*//*Label 6772*/ GIMT_Encode4(497337), // Rule ID 4232 //
          GIM_CheckComplexPattern, /*MI*/0, /*Op*/4, /*Renderer*/GIMT_Encode2(0), GIMT_Encode2(GICP_gi_buf_soffset),
          // (SIbuffer_load_ushort:{ *:[i32] } v4i32:{ *:[v4i32] }:$rsrc, i32:{ *:[i32] }:$vindex, i32:{ *:[i32] }:$voffset, (BUFSOffset:{ *:[i32] } i32:{ *:[i32] }:$soffset), (timm:{ *:[i32] }):$offset, (timm:{ *:[i32] }):$auxiliary, (timm:{ *:[i1] }))  =>  (BUFFER_LOAD_USHORT_VBUFFER_BOTHEN:{ *:[i32] } (REG_SEQUENCE:{ *:[i64] } VReg_64:{ *:[i32] }, VGPR_32:{ *:[i32] }:$vindex, sub0:{ *:[i32] }, VGPR_32:{ *:[i32] }:$voffset, sub1:{ *:[i32] }), SReg_128:{ *:[v4i32] }:$rsrc, SCSrc_b32:{ *:[i32] }:$soffset, (timm:{ *:[i32] }):$offset, (extract_cpol:{ *:[i32] } ?:{ *:[i32] }:$auxiliary), (extract_swz:{ *:[i1] } ?:{ *:[i32] }:$auxiliary))
          GIR_MakeTempReg, /*TempRegID*/0, /*TypeID*/GILLT_s64,
          GIR_BuildMI, /*InsnID*/1, /*Opcode*/GIMT_Encode2(TargetOpcode::REG_SEQUENCE),
          GIR_AddTempRegister, /*InsnID*/1, /*TempRegID*/0, /*TempRegFlags*/GIMT_Encode2(RegState::Define),
          GIR_Copy, /*NewInsnID*/1, /*OldInsnID*/0, /*OpIdx*/2, // vindex
          GIR_AddImm8, /*InsnID*/1, /*SubRegIndex*/3,
          GIR_Copy, /*NewInsnID*/1, /*OldInsnID*/0, /*OpIdx*/3, // voffset
          GIR_AddImm8, /*InsnID*/1, /*SubRegIndex*/11,
          GIR_ConstrainOperandRC, /*InsnID*/1, /*Op*/0, GIMT_Encode2(AMDGPU::VReg_64RegClassID),
          GIR_ConstrainOperandRC, /*InsnID*/1, /*Op*/1, GIMT_Encode2(AMDGPU::VGPR_32RegClassID),
          GIR_ConstrainOperandRC, /*InsnID*/1, /*Op*/3, GIMT_Encode2(AMDGPU::VGPR_32RegClassID),
          GIR_BuildMI, /*InsnID*/0, /*Opcode*/GIMT_Encode2(AMDGPU::BUFFER_LOAD_USHORT_VBUFFER_BOTHEN),
          GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/0, // DstI[vdata]
          GIR_AddSimpleTempRegister, /*InsnID*/0, /*TempRegID*/0,
          GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/1, // rsrc
          GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/0, // soffset
          GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/5, // offset
          GIR_CustomOperandRenderer, /*InsnID*/0, /*OldInsnID*/0, /*OpIdx*/6, /*OperandRenderer*/GIMT_Encode2(GICR_renderExtractCPol), // auxiliary
          GIR_CustomOperandRenderer, /*InsnID*/0, /*OldInsnID*/0, /*OpIdx*/6, /*OperandRenderer*/GIMT_Encode2(GICR_renderExtractSWZ), // auxiliary
          GIR_MergeMemOperands, /*InsnID*/0, /*NumInsns*/1, /*MergeInsnID's*/0,
          GIR_ConstrainSelectedInstOperands, /*InsnID*/0,
          GIR_EraseFromParent, /*InsnID*/0,
          // GIR_Coverage, 4232,
          GIR_Done,
        // Label 6772: @497337
        GIM_Reject,
      // Label 6770: @497338
      GIM_Reject,
    // Label 6761: @497339
    GIM_Reject,
    // Label 132: @497340
    GIM_SwitchType, /*MI*/0, /*Op*/0, /*[*/GIMT_Encode2(9), GIMT_Encode2(18), /*)*//*default:*//*Label 6779*/ GIMT_Encode4(505733),
    /*GILLT_s32*//*Label 6773*/ GIMT_Encode4(497387), GIMT_Encode4(0),
    /*GILLT_v2s16*//*Label 6774*/ GIMT_Encode4(498778),
    /*GILLT_v2s32*//*Label 6775*/ GIMT_Encode4(500169), GIMT_Encode4(0),
    /*GILLT_v3s32*//*Label 6776*/ GIMT_Encode4(501560), GIMT_Encode4(0),
    /*GILLT_v4s16*//*Label 6777*/ GIMT_Encode4(502951),
    /*GILLT_v4s32*//*Label 6778*/ GIMT_Encode4(504342),
    // Label 6773: @497387
    GIM_Try, /*On fail goto*//*Label 6780*/ GIMT_Encode4(498777),
      GIM_CheckType, /*MI*/0, /*Op*/1, /*Type*/GILLT_v4s32,
      GIM_CheckType, /*MI*/0, /*Op*/2, /*Type*/GILLT_s32,
      GIM_CheckType, /*MI*/0, /*Op*/3, /*Type*/GILLT_s32,
      GIM_CheckType, /*MI*/0, /*Op*/4, /*Type*/GILLT_s32,
      GIM_Try, /*On fail goto*//*Label 6781*/ GIMT_Encode4(497490), // Rule ID 4393 //
        GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasUnrestrictedSOffset),
        GIM_CheckConstantInt8, /*MI*/0, /*Op*/2, 0,
        GIM_CheckConstantInt8, /*MI*/0, /*Op*/3, 0,
        // MIs[0] offset
        GIM_CheckIsImm, /*MI*/0, /*Op*/5,
        // MIs[0] auxiliary
        GIM_CheckIsImm, /*MI*/0, /*Op*/6,
        // MIs[0] Operand 7
        GIM_CheckLiteralInt, /*MI*/0, /*Op*/7, GIMT_Encode8(0),
        GIM_CheckComplexPattern, /*MI*/0, /*Op*/4, /*Renderer*/GIMT_Encode2(0), GIMT_Encode2(GICP_gi_buf_soffset),
        // (SIbuffer_store f32:{ *:[f32] }:$vdata, v4i32:{ *:[v4i32] }:$rsrc, 0:{ *:[i32] }, 0:{ *:[i32] }, (BUFSOffset:{ *:[i32] } i32:{ *:[i32] }:$soffset), (timm:{ *:[i32] }):$offset, (timm:{ *:[i32] }):$auxiliary, 0:{ *:[i1] })  =>  (BUFFER_STORE_DWORD_OFFSET_exact anonymous_15037:{ *:[f32] }:$vdata, SReg_128:{ *:[v4i32] }:$rsrc, SCSrc_b32:{ *:[i32] }:$soffset, (timm:{ *:[i32] }):$offset, (extract_cpol:{ *:[i32] } ?:{ *:[i32] }:$auxiliary), (extract_swz:{ *:[i1] } ?:{ *:[i32] }:$auxiliary))
        GIR_BuildMI, /*InsnID*/0, /*Opcode*/GIMT_Encode2(AMDGPU::BUFFER_STORE_DWORD_OFFSET_exact),
        GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/0, // vdata
        GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/1, // rsrc
        GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/0, // soffset
        GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/5, // offset
        GIR_CustomOperandRenderer, /*InsnID*/0, /*OldInsnID*/0, /*OpIdx*/6, /*OperandRenderer*/GIMT_Encode2(GICR_renderExtractCPol), // auxiliary
        GIR_CustomOperandRenderer, /*InsnID*/0, /*OldInsnID*/0, /*OpIdx*/6, /*OperandRenderer*/GIMT_Encode2(GICR_renderExtractSWZ), // auxiliary
        GIR_MergeMemOperands, /*InsnID*/0, /*NumInsns*/1, /*MergeInsnID's*/0,
        GIR_ConstrainSelectedInstOperands, /*InsnID*/0,
        GIR_EraseFromParent, /*InsnID*/0,
        // GIR_Coverage, 4393,
        GIR_Done,
      // Label 6781: @497490
      GIM_Try, /*On fail goto*//*Label 6782*/ GIMT_Encode4(497569), // Rule ID 4397 //
        GIM_CheckConstantInt8, /*MI*/0, /*Op*/2, 0,
        GIM_CheckConstantInt8, /*MI*/0, /*Op*/3, 0,
        // MIs[0] offset
        GIM_CheckIsImm, /*MI*/0, /*Op*/5,
        // MIs[0] auxiliary
        GIM_CheckIsImm, /*MI*/0, /*Op*/6,
        // MIs[0] Operand 7
        GIM_CheckLiteralInt, /*MI*/0, /*Op*/7, GIMT_Encode8(0),
        GIM_CheckComplexPattern, /*MI*/0, /*Op*/4, /*Renderer*/GIMT_Encode2(0), GIMT_Encode2(GICP_gi_buf_soffset),
        // (SIbuffer_store f32:{ *:[f32] }:$vdata, v4i32:{ *:[v4i32] }:$rsrc, 0:{ *:[i32] }, 0:{ *:[i32] }, (BUFSOffset:{ *:[i32] } i32:{ *:[i32] }:$soffset), (timm:{ *:[i32] }):$offset, (timm:{ *:[i32] }):$auxiliary, 0:{ *:[i1] })  =>  (BUFFER_STORE_DWORD_VBUFFER_OFFSET_exact anonymous_15037:{ *:[f32] }:$vdata, SReg_128:{ *:[v4i32] }:$rsrc, SCSrc_b32:{ *:[i32] }:$soffset, (timm:{ *:[i32] }):$offset, (extract_cpol:{ *:[i32] } ?:{ *:[i32] }:$auxiliary), (extract_swz:{ *:[i1] } ?:{ *:[i32] }:$auxiliary))
        GIR_BuildMI, /*InsnID*/0, /*Opcode*/GIMT_Encode2(AMDGPU::BUFFER_STORE_DWORD_VBUFFER_OFFSET_exact),
        GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/0, // vdata
        GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/1, // rsrc
        GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/0, // soffset
        GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/5, // offset
        GIR_CustomOperandRenderer, /*InsnID*/0, /*OldInsnID*/0, /*OpIdx*/6, /*OperandRenderer*/GIMT_Encode2(GICR_renderExtractCPol), // auxiliary
        GIR_CustomOperandRenderer, /*InsnID*/0, /*OldInsnID*/0, /*OpIdx*/6, /*OperandRenderer*/GIMT_Encode2(GICR_renderExtractSWZ), // auxiliary
        GIR_MergeMemOperands, /*InsnID*/0, /*NumInsns*/1, /*MergeInsnID's*/0,
        GIR_ConstrainSelectedInstOperands, /*InsnID*/0,
        GIR_EraseFromParent, /*InsnID*/0,
        // GIR_Coverage, 4397,
        GIR_Done,
      // Label 6782: @497569
      GIM_Try, /*On fail goto*//*Label 6783*/ GIMT_Encode4(497651), // Rule ID 4401 //
        GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasUnrestrictedSOffset),
        GIM_CheckConstantInt8, /*MI*/0, /*Op*/2, 0,
        GIM_CheckConstantInt8, /*MI*/0, /*Op*/3, 0,
        // MIs[0] offset
        GIM_CheckIsImm, /*MI*/0, /*Op*/5,
        // MIs[0] auxiliary
        GIM_CheckIsImm, /*MI*/0, /*Op*/6,
        // MIs[0] Operand 7
        GIM_CheckLiteralInt, /*MI*/0, /*Op*/7, GIMT_Encode8(0),
        GIM_CheckComplexPattern, /*MI*/0, /*Op*/4, /*Renderer*/GIMT_Encode2(0), GIMT_Encode2(GICP_gi_buf_soffset),
        // (SIbuffer_store i32:{ *:[i32] }:$vdata, v4i32:{ *:[v4i32] }:$rsrc, 0:{ *:[i32] }, 0:{ *:[i32] }, (BUFSOffset:{ *:[i32] } i32:{ *:[i32] }:$soffset), (timm:{ *:[i32] }):$offset, (timm:{ *:[i32] }):$auxiliary, 0:{ *:[i1] })  =>  (BUFFER_STORE_DWORD_OFFSET_exact anonymous_15037:{ *:[i32] }:$vdata, SReg_128:{ *:[v4i32] }:$rsrc, SCSrc_b32:{ *:[i32] }:$soffset, (timm:{ *:[i32] }):$offset, (extract_cpol:{ *:[i32] } ?:{ *:[i32] }:$auxiliary), (extract_swz:{ *:[i1] } ?:{ *:[i32] }:$auxiliary))
        GIR_BuildMI, /*InsnID*/0, /*Opcode*/GIMT_Encode2(AMDGPU::BUFFER_STORE_DWORD_OFFSET_exact),
        GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/0, // vdata
        GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/1, // rsrc
        GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/0, // soffset
        GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/5, // offset
        GIR_CustomOperandRenderer, /*InsnID*/0, /*OldInsnID*/0, /*OpIdx*/6, /*OperandRenderer*/GIMT_Encode2(GICR_renderExtractCPol), // auxiliary
        GIR_CustomOperandRenderer, /*InsnID*/0, /*OldInsnID*/0, /*OpIdx*/6, /*OperandRenderer*/GIMT_Encode2(GICR_renderExtractSWZ), // auxiliary
        GIR_MergeMemOperands, /*InsnID*/0, /*NumInsns*/1, /*MergeInsnID's*/0,
        GIR_ConstrainSelectedInstOperands, /*InsnID*/0,
        GIR_EraseFromParent, /*InsnID*/0,
        // GIR_Coverage, 4401,
        GIR_Done,
      // Label 6783: @497651
      GIM_Try, /*On fail goto*//*Label 6784*/ GIMT_Encode4(497730), // Rule ID 4405 //
        GIM_CheckConstantInt8, /*MI*/0, /*Op*/2, 0,
        GIM_CheckConstantInt8, /*MI*/0, /*Op*/3, 0,
        // MIs[0] offset
        GIM_CheckIsImm, /*MI*/0, /*Op*/5,
        // MIs[0] auxiliary
        GIM_CheckIsImm, /*MI*/0, /*Op*/6,
        // MIs[0] Operand 7
        GIM_CheckLiteralInt, /*MI*/0, /*Op*/7, GIMT_Encode8(0),
        GIM_CheckComplexPattern, /*MI*/0, /*Op*/4, /*Renderer*/GIMT_Encode2(0), GIMT_Encode2(GICP_gi_buf_soffset),
        // (SIbuffer_store i32:{ *:[i32] }:$vdata, v4i32:{ *:[v4i32] }:$rsrc, 0:{ *:[i32] }, 0:{ *:[i32] }, (BUFSOffset:{ *:[i32] } i32:{ *:[i32] }:$soffset), (timm:{ *:[i32] }):$offset, (timm:{ *:[i32] }):$auxiliary, 0:{ *:[i1] })  =>  (BUFFER_STORE_DWORD_VBUFFER_OFFSET_exact anonymous_15037:{ *:[i32] }:$vdata, SReg_128:{ *:[v4i32] }:$rsrc, SCSrc_b32:{ *:[i32] }:$soffset, (timm:{ *:[i32] }):$offset, (extract_cpol:{ *:[i32] } ?:{ *:[i32] }:$auxiliary), (extract_swz:{ *:[i1] } ?:{ *:[i32] }:$auxiliary))
        GIR_BuildMI, /*InsnID*/0, /*Opcode*/GIMT_Encode2(AMDGPU::BUFFER_STORE_DWORD_VBUFFER_OFFSET_exact),
        GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/0, // vdata
        GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/1, // rsrc
        GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/0, // soffset
        GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/5, // offset
        GIR_CustomOperandRenderer, /*InsnID*/0, /*OldInsnID*/0, /*OpIdx*/6, /*OperandRenderer*/GIMT_Encode2(GICR_renderExtractCPol), // auxiliary
        GIR_CustomOperandRenderer, /*InsnID*/0, /*OldInsnID*/0, /*OpIdx*/6, /*OperandRenderer*/GIMT_Encode2(GICR_renderExtractSWZ), // auxiliary
        GIR_MergeMemOperands, /*InsnID*/0, /*NumInsns*/1, /*MergeInsnID's*/0,
        GIR_ConstrainSelectedInstOperands, /*InsnID*/0,
        GIR_EraseFromParent, /*InsnID*/0,
        // GIR_Coverage, 4405,
        GIR_Done,
      // Label 6784: @497730
      GIM_Try, /*On fail goto*//*Label 6785*/ GIMT_Encode4(497812), // Rule ID 4394 //
        GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasUnrestrictedSOffset),
        GIM_CheckConstantInt8, /*MI*/0, /*Op*/2, 0,
        // MIs[0] offset
        GIM_CheckIsImm, /*MI*/0, /*Op*/5,
        // MIs[0] auxiliary
        GIM_CheckIsImm, /*MI*/0, /*Op*/6,
        // MIs[0] Operand 7
        GIM_CheckLiteralInt, /*MI*/0, /*Op*/7, GIMT_Encode8(0),
        GIM_CheckComplexPattern, /*MI*/0, /*Op*/4, /*Renderer*/GIMT_Encode2(0), GIMT_Encode2(GICP_gi_buf_soffset),
        // (SIbuffer_store f32:{ *:[f32] }:$vdata, v4i32:{ *:[v4i32] }:$rsrc, 0:{ *:[i32] }, i32:{ *:[i32] }:$voffset, (BUFSOffset:{ *:[i32] } i32:{ *:[i32] }:$soffset), (timm:{ *:[i32] }):$offset, (timm:{ *:[i32] }):$auxiliary, 0:{ *:[i1] })  =>  (BUFFER_STORE_DWORD_OFFEN_exact anonymous_15037:{ *:[f32] }:$vdata, VGPR_32:{ *:[i32] }:$voffset, SReg_128:{ *:[v4i32] }:$rsrc, SCSrc_b32:{ *:[i32] }:$soffset, (timm:{ *:[i32] }):$offset, (extract_cpol:{ *:[i32] } ?:{ *:[i32] }:$auxiliary), (extract_swz:{ *:[i1] } ?:{ *:[i32] }:$auxiliary))
        GIR_BuildMI, /*InsnID*/0, /*Opcode*/GIMT_Encode2(AMDGPU::BUFFER_STORE_DWORD_OFFEN_exact),
        GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/0, // vdata
        GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/3, // voffset
        GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/1, // rsrc
        GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/0, // soffset
        GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/5, // offset
        GIR_CustomOperandRenderer, /*InsnID*/0, /*OldInsnID*/0, /*OpIdx*/6, /*OperandRenderer*/GIMT_Encode2(GICR_renderExtractCPol), // auxiliary
        GIR_CustomOperandRenderer, /*InsnID*/0, /*OldInsnID*/0, /*OpIdx*/6, /*OperandRenderer*/GIMT_Encode2(GICR_renderExtractSWZ), // auxiliary
        GIR_MergeMemOperands, /*InsnID*/0, /*NumInsns*/1, /*MergeInsnID's*/0,
        GIR_ConstrainSelectedInstOperands, /*InsnID*/0,
        GIR_EraseFromParent, /*InsnID*/0,
        // GIR_Coverage, 4394,
        GIR_Done,
      // Label 6785: @497812
      GIM_Try, /*On fail goto*//*Label 6786*/ GIMT_Encode4(497891), // Rule ID 4398 //
        GIM_CheckConstantInt8, /*MI*/0, /*Op*/2, 0,
        // MIs[0] offset
        GIM_CheckIsImm, /*MI*/0, /*Op*/5,
        // MIs[0] auxiliary
        GIM_CheckIsImm, /*MI*/0, /*Op*/6,
        // MIs[0] Operand 7
        GIM_CheckLiteralInt, /*MI*/0, /*Op*/7, GIMT_Encode8(0),
        GIM_CheckComplexPattern, /*MI*/0, /*Op*/4, /*Renderer*/GIMT_Encode2(0), GIMT_Encode2(GICP_gi_buf_soffset),
        // (SIbuffer_store f32:{ *:[f32] }:$vdata, v4i32:{ *:[v4i32] }:$rsrc, 0:{ *:[i32] }, i32:{ *:[i32] }:$voffset, (BUFSOffset:{ *:[i32] } i32:{ *:[i32] }:$soffset), (timm:{ *:[i32] }):$offset, (timm:{ *:[i32] }):$auxiliary, 0:{ *:[i1] })  =>  (BUFFER_STORE_DWORD_VBUFFER_OFFEN_exact anonymous_15037:{ *:[f32] }:$vdata, VGPR_32:{ *:[i32] }:$voffset, SReg_128:{ *:[v4i32] }:$rsrc, SCSrc_b32:{ *:[i32] }:$soffset, (timm:{ *:[i32] }):$offset, (extract_cpol:{ *:[i32] } ?:{ *:[i32] }:$auxiliary), (extract_swz:{ *:[i1] } ?:{ *:[i32] }:$auxiliary))
        GIR_BuildMI, /*InsnID*/0, /*Opcode*/GIMT_Encode2(AMDGPU::BUFFER_STORE_DWORD_VBUFFER_OFFEN_exact),
        GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/0, // vdata
        GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/3, // voffset
        GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/1, // rsrc
        GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/0, // soffset
        GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/5, // offset
        GIR_CustomOperandRenderer, /*InsnID*/0, /*OldInsnID*/0, /*OpIdx*/6, /*OperandRenderer*/GIMT_Encode2(GICR_renderExtractCPol), // auxiliary
        GIR_CustomOperandRenderer, /*InsnID*/0, /*OldInsnID*/0, /*OpIdx*/6, /*OperandRenderer*/GIMT_Encode2(GICR_renderExtractSWZ), // auxiliary
        GIR_MergeMemOperands, /*InsnID*/0, /*NumInsns*/1, /*MergeInsnID's*/0,
        GIR_ConstrainSelectedInstOperands, /*InsnID*/0,
        GIR_EraseFromParent, /*InsnID*/0,
        // GIR_Coverage, 4398,
        GIR_Done,
      // Label 6786: @497891
      GIM_Try, /*On fail goto*//*Label 6787*/ GIMT_Encode4(497973), // Rule ID 4402 //
        GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasUnrestrictedSOffset),
        GIM_CheckConstantInt8, /*MI*/0, /*Op*/2, 0,
        // MIs[0] offset
        GIM_CheckIsImm, /*MI*/0, /*Op*/5,
        // MIs[0] auxiliary
        GIM_CheckIsImm, /*MI*/0, /*Op*/6,
        // MIs[0] Operand 7
        GIM_CheckLiteralInt, /*MI*/0, /*Op*/7, GIMT_Encode8(0),
        GIM_CheckComplexPattern, /*MI*/0, /*Op*/4, /*Renderer*/GIMT_Encode2(0), GIMT_Encode2(GICP_gi_buf_soffset),
        // (SIbuffer_store i32:{ *:[i32] }:$vdata, v4i32:{ *:[v4i32] }:$rsrc, 0:{ *:[i32] }, i32:{ *:[i32] }:$voffset, (BUFSOffset:{ *:[i32] } i32:{ *:[i32] }:$soffset), (timm:{ *:[i32] }):$offset, (timm:{ *:[i32] }):$auxiliary, 0:{ *:[i1] })  =>  (BUFFER_STORE_DWORD_OFFEN_exact anonymous_15037:{ *:[i32] }:$vdata, VGPR_32:{ *:[i32] }:$voffset, SReg_128:{ *:[v4i32] }:$rsrc, SCSrc_b32:{ *:[i32] }:$soffset, (timm:{ *:[i32] }):$offset, (extract_cpol:{ *:[i32] } ?:{ *:[i32] }:$auxiliary), (extract_swz:{ *:[i1] } ?:{ *:[i32] }:$auxiliary))
        GIR_BuildMI, /*InsnID*/0, /*Opcode*/GIMT_Encode2(AMDGPU::BUFFER_STORE_DWORD_OFFEN_exact),
        GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/0, // vdata
        GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/3, // voffset
        GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/1, // rsrc
        GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/0, // soffset
        GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/5, // offset
        GIR_CustomOperandRenderer, /*InsnID*/0, /*OldInsnID*/0, /*OpIdx*/6, /*OperandRenderer*/GIMT_Encode2(GICR_renderExtractCPol), // auxiliary
        GIR_CustomOperandRenderer, /*InsnID*/0, /*OldInsnID*/0, /*OpIdx*/6, /*OperandRenderer*/GIMT_Encode2(GICR_renderExtractSWZ), // auxiliary
        GIR_MergeMemOperands, /*InsnID*/0, /*NumInsns*/1, /*MergeInsnID's*/0,
        GIR_ConstrainSelectedInstOperands, /*InsnID*/0,
        GIR_EraseFromParent, /*InsnID*/0,
        // GIR_Coverage, 4402,
        GIR_Done,
      // Label 6787: @497973
      GIM_Try, /*On fail goto*//*Label 6788*/ GIMT_Encode4(498052), // Rule ID 4406 //
        GIM_CheckConstantInt8, /*MI*/0, /*Op*/2, 0,
        // MIs[0] offset
        GIM_CheckIsImm, /*MI*/0, /*Op*/5,
        // MIs[0] auxiliary
        GIM_CheckIsImm, /*MI*/0, /*Op*/6,
        // MIs[0] Operand 7
        GIM_CheckLiteralInt, /*MI*/0, /*Op*/7, GIMT_Encode8(0),
        GIM_CheckComplexPattern, /*MI*/0, /*Op*/4, /*Renderer*/GIMT_Encode2(0), GIMT_Encode2(GICP_gi_buf_soffset),
        // (SIbuffer_store i32:{ *:[i32] }:$vdata, v4i32:{ *:[v4i32] }:$rsrc, 0:{ *:[i32] }, i32:{ *:[i32] }:$voffset, (BUFSOffset:{ *:[i32] } i32:{ *:[i32] }:$soffset), (timm:{ *:[i32] }):$offset, (timm:{ *:[i32] }):$auxiliary, 0:{ *:[i1] })  =>  (BUFFER_STORE_DWORD_VBUFFER_OFFEN_exact anonymous_15037:{ *:[i32] }:$vdata, VGPR_32:{ *:[i32] }:$voffset, SReg_128:{ *:[v4i32] }:$rsrc, SCSrc_b32:{ *:[i32] }:$soffset, (timm:{ *:[i32] }):$offset, (extract_cpol:{ *:[i32] } ?:{ *:[i32] }:$auxiliary), (extract_swz:{ *:[i1] } ?:{ *:[i32] }:$auxiliary))
        GIR_BuildMI, /*InsnID*/0, /*Opcode*/GIMT_Encode2(AMDGPU::BUFFER_STORE_DWORD_VBUFFER_OFFEN_exact),
        GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/0, // vdata
        GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/3, // voffset
        GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/1, // rsrc
        GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/0, // soffset
        GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/5, // offset
        GIR_CustomOperandRenderer, /*InsnID*/0, /*OldInsnID*/0, /*OpIdx*/6, /*OperandRenderer*/GIMT_Encode2(GICR_renderExtractCPol), // auxiliary
        GIR_CustomOperandRenderer, /*InsnID*/0, /*OldInsnID*/0, /*OpIdx*/6, /*OperandRenderer*/GIMT_Encode2(GICR_renderExtractSWZ), // auxiliary
        GIR_MergeMemOperands, /*InsnID*/0, /*NumInsns*/1, /*MergeInsnID's*/0,
        GIR_ConstrainSelectedInstOperands, /*InsnID*/0,
        GIR_EraseFromParent, /*InsnID*/0,
        // GIR_Coverage, 4406,
        GIR_Done,
      // Label 6788: @498052
      GIM_Try, /*On fail goto*//*Label 6789*/ GIMT_Encode4(498126), // Rule ID 4395 //
        GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasUnrestrictedSOffset),
        GIM_CheckConstantInt8, /*MI*/0, /*Op*/3, 0,
        // MIs[0] offset
        GIM_CheckIsImm, /*MI*/0, /*Op*/5,
        // MIs[0] auxiliary
        GIM_CheckIsImm, /*MI*/0, /*Op*/6,
        // MIs[0] Operand 7
        GIM_CheckIsImm, /*MI*/0, /*Op*/7,
        GIM_CheckComplexPattern, /*MI*/0, /*Op*/4, /*Renderer*/GIMT_Encode2(0), GIMT_Encode2(GICP_gi_buf_soffset),
        // (SIbuffer_store f32:{ *:[f32] }:$vdata, v4i32:{ *:[v4i32] }:$rsrc, i32:{ *:[i32] }:$vindex, 0:{ *:[i32] }, (BUFSOffset:{ *:[i32] } i32:{ *:[i32] }:$soffset), (timm:{ *:[i32] }):$offset, (timm:{ *:[i32] }):$auxiliary, (timm:{ *:[i1] }))  =>  (BUFFER_STORE_DWORD_IDXEN_exact anonymous_15037:{ *:[f32] }:$vdata, VGPR_32:{ *:[i32] }:$vindex, SReg_128:{ *:[v4i32] }:$rsrc, SCSrc_b32:{ *:[i32] }:$soffset, (timm:{ *:[i32] }):$offset, (extract_cpol:{ *:[i32] } ?:{ *:[i32] }:$auxiliary), (extract_swz:{ *:[i1] } ?:{ *:[i32] }:$auxiliary))
        GIR_BuildMI, /*InsnID*/0, /*Opcode*/GIMT_Encode2(AMDGPU::BUFFER_STORE_DWORD_IDXEN_exact),
        GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/0, // vdata
        GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/2, // vindex
        GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/1, // rsrc
        GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/0, // soffset
        GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/5, // offset
        GIR_CustomOperandRenderer, /*InsnID*/0, /*OldInsnID*/0, /*OpIdx*/6, /*OperandRenderer*/GIMT_Encode2(GICR_renderExtractCPol), // auxiliary
        GIR_CustomOperandRenderer, /*InsnID*/0, /*OldInsnID*/0, /*OpIdx*/6, /*OperandRenderer*/GIMT_Encode2(GICR_renderExtractSWZ), // auxiliary
        GIR_MergeMemOperands, /*InsnID*/0, /*NumInsns*/1, /*MergeInsnID's*/0,
        GIR_ConstrainSelectedInstOperands, /*InsnID*/0,
        GIR_EraseFromParent, /*InsnID*/0,
        // GIR_Coverage, 4395,
        GIR_Done,
      // Label 6789: @498126
      GIM_Try, /*On fail goto*//*Label 6790*/ GIMT_Encode4(498197), // Rule ID 4399 //
        GIM_CheckConstantInt8, /*MI*/0, /*Op*/3, 0,
        // MIs[0] offset
        GIM_CheckIsImm, /*MI*/0, /*Op*/5,
        // MIs[0] auxiliary
        GIM_CheckIsImm, /*MI*/0, /*Op*/6,
        // MIs[0] Operand 7
        GIM_CheckIsImm, /*MI*/0, /*Op*/7,
        GIM_CheckComplexPattern, /*MI*/0, /*Op*/4, /*Renderer*/GIMT_Encode2(0), GIMT_Encode2(GICP_gi_buf_soffset),
        // (SIbuffer_store f32:{ *:[f32] }:$vdata, v4i32:{ *:[v4i32] }:$rsrc, i32:{ *:[i32] }:$vindex, 0:{ *:[i32] }, (BUFSOffset:{ *:[i32] } i32:{ *:[i32] }:$soffset), (timm:{ *:[i32] }):$offset, (timm:{ *:[i32] }):$auxiliary, (timm:{ *:[i1] }))  =>  (BUFFER_STORE_DWORD_VBUFFER_IDXEN_exact anonymous_15037:{ *:[f32] }:$vdata, VGPR_32:{ *:[i32] }:$vindex, SReg_128:{ *:[v4i32] }:$rsrc, SCSrc_b32:{ *:[i32] }:$soffset, (timm:{ *:[i32] }):$offset, (extract_cpol:{ *:[i32] } ?:{ *:[i32] }:$auxiliary), (extract_swz:{ *:[i1] } ?:{ *:[i32] }:$auxiliary))
        GIR_BuildMI, /*InsnID*/0, /*Opcode*/GIMT_Encode2(AMDGPU::BUFFER_STORE_DWORD_VBUFFER_IDXEN_exact),
        GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/0, // vdata
        GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/2, // vindex
        GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/1, // rsrc
        GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/0, // soffset
        GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/5, // offset
        GIR_CustomOperandRenderer, /*InsnID*/0, /*OldInsnID*/0, /*OpIdx*/6, /*OperandRenderer*/GIMT_Encode2(GICR_renderExtractCPol), // auxiliary
        GIR_CustomOperandRenderer, /*InsnID*/0, /*OldInsnID*/0, /*OpIdx*/6, /*OperandRenderer*/GIMT_Encode2(GICR_renderExtractSWZ), // auxiliary
        GIR_MergeMemOperands, /*InsnID*/0, /*NumInsns*/1, /*MergeInsnID's*/0,
        GIR_ConstrainSelectedInstOperands, /*InsnID*/0,
        GIR_EraseFromParent, /*InsnID*/0,
        // GIR_Coverage, 4399,
        GIR_Done,
      // Label 6790: @498197
      GIM_Try, /*On fail goto*//*Label 6791*/ GIMT_Encode4(498271), // Rule ID 4403 //
        GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasUnrestrictedSOffset),
        GIM_CheckConstantInt8, /*MI*/0, /*Op*/3, 0,
        // MIs[0] offset
        GIM_CheckIsImm, /*MI*/0, /*Op*/5,
        // MIs[0] auxiliary
        GIM_CheckIsImm, /*MI*/0, /*Op*/6,
        // MIs[0] Operand 7
        GIM_CheckIsImm, /*MI*/0, /*Op*/7,
        GIM_CheckComplexPattern, /*MI*/0, /*Op*/4, /*Renderer*/GIMT_Encode2(0), GIMT_Encode2(GICP_gi_buf_soffset),
        // (SIbuffer_store i32:{ *:[i32] }:$vdata, v4i32:{ *:[v4i32] }:$rsrc, i32:{ *:[i32] }:$vindex, 0:{ *:[i32] }, (BUFSOffset:{ *:[i32] } i32:{ *:[i32] }:$soffset), (timm:{ *:[i32] }):$offset, (timm:{ *:[i32] }):$auxiliary, (timm:{ *:[i1] }))  =>  (BUFFER_STORE_DWORD_IDXEN_exact anonymous_15037:{ *:[i32] }:$vdata, VGPR_32:{ *:[i32] }:$vindex, SReg_128:{ *:[v4i32] }:$rsrc, SCSrc_b32:{ *:[i32] }:$soffset, (timm:{ *:[i32] }):$offset, (extract_cpol:{ *:[i32] } ?:{ *:[i32] }:$auxiliary), (extract_swz:{ *:[i1] } ?:{ *:[i32] }:$auxiliary))
        GIR_BuildMI, /*InsnID*/0, /*Opcode*/GIMT_Encode2(AMDGPU::BUFFER_STORE_DWORD_IDXEN_exact),
        GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/0, // vdata
        GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/2, // vindex
        GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/1, // rsrc
        GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/0, // soffset
        GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/5, // offset
        GIR_CustomOperandRenderer, /*InsnID*/0, /*OldInsnID*/0, /*OpIdx*/6, /*OperandRenderer*/GIMT_Encode2(GICR_renderExtractCPol), // auxiliary
        GIR_CustomOperandRenderer, /*InsnID*/0, /*OldInsnID*/0, /*OpIdx*/6, /*OperandRenderer*/GIMT_Encode2(GICR_renderExtractSWZ), // auxiliary
        GIR_MergeMemOperands, /*InsnID*/0, /*NumInsns*/1, /*MergeInsnID's*/0,
        GIR_ConstrainSelectedInstOperands, /*InsnID*/0,
        GIR_EraseFromParent, /*InsnID*/0,
        // GIR_Coverage, 4403,
        GIR_Done,
      // Label 6791: @498271
      GIM_Try, /*On fail goto*//*Label 6792*/ GIMT_Encode4(498342), // Rule ID 4407 //
        GIM_CheckConstantInt8, /*MI*/0, /*Op*/3, 0,
        // MIs[0] offset
        GIM_CheckIsImm, /*MI*/0, /*Op*/5,
        // MIs[0] auxiliary
        GIM_CheckIsImm, /*MI*/0, /*Op*/6,
        // MIs[0] Operand 7
        GIM_CheckIsImm, /*MI*/0, /*Op*/7,
        GIM_CheckComplexPattern, /*MI*/0, /*Op*/4, /*Renderer*/GIMT_Encode2(0), GIMT_Encode2(GICP_gi_buf_soffset),
        // (SIbuffer_store i32:{ *:[i32] }:$vdata, v4i32:{ *:[v4i32] }:$rsrc, i32:{ *:[i32] }:$vindex, 0:{ *:[i32] }, (BUFSOffset:{ *:[i32] } i32:{ *:[i32] }:$soffset), (timm:{ *:[i32] }):$offset, (timm:{ *:[i32] }):$auxiliary, (timm:{ *:[i1] }))  =>  (BUFFER_STORE_DWORD_VBUFFER_IDXEN_exact anonymous_15037:{ *:[i32] }:$vdata, VGPR_32:{ *:[i32] }:$vindex, SReg_128:{ *:[v4i32] }:$rsrc, SCSrc_b32:{ *:[i32] }:$soffset, (timm:{ *:[i32] }):$offset, (extract_cpol:{ *:[i32] } ?:{ *:[i32] }:$auxiliary), (extract_swz:{ *:[i1] } ?:{ *:[i32] }:$auxiliary))
        GIR_BuildMI, /*InsnID*/0, /*Opcode*/GIMT_Encode2(AMDGPU::BUFFER_STORE_DWORD_VBUFFER_IDXEN_exact),
        GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/0, // vdata
        GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/2, // vindex
        GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/1, // rsrc
        GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/0, // soffset
        GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/5, // offset
        GIR_CustomOperandRenderer, /*InsnID*/0, /*OldInsnID*/0, /*OpIdx*/6, /*OperandRenderer*/GIMT_Encode2(GICR_renderExtractCPol), // auxiliary
        GIR_CustomOperandRenderer, /*InsnID*/0, /*OldInsnID*/0, /*OpIdx*/6, /*OperandRenderer*/GIMT_Encode2(GICR_renderExtractSWZ), // auxiliary
        GIR_MergeMemOperands, /*InsnID*/0, /*NumInsns*/1, /*MergeInsnID's*/0,
        GIR_ConstrainSelectedInstOperands, /*InsnID*/0,
        GIR_EraseFromParent, /*InsnID*/0,
        // GIR_Coverage, 4407,
        GIR_Done,
      // Label 6792: @498342
      GIM_Try, /*On fail goto*//*Label 6793*/ GIMT_Encode4(498452), // Rule ID 4396 //
        GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasUnrestrictedSOffset),
        // MIs[0] offset
        GIM_CheckIsImm, /*MI*/0, /*Op*/5,
        // MIs[0] auxiliary
        GIM_CheckIsImm, /*MI*/0, /*Op*/6,
        // MIs[0] Operand 7
        GIM_CheckIsImm, /*MI*/0, /*Op*/7,
        GIM_CheckComplexPattern, /*MI*/0, /*Op*/4, /*Renderer*/GIMT_Encode2(0), GIMT_Encode2(GICP_gi_buf_soffset),
        // (SIbuffer_store f32:{ *:[f32] }:$vdata, v4i32:{ *:[v4i32] }:$rsrc, i32:{ *:[i32] }:$vindex, i32:{ *:[i32] }:$voffset, (BUFSOffset:{ *:[i32] } i32:{ *:[i32] }:$soffset), (timm:{ *:[i32] }):$offset, (timm:{ *:[i32] }):$auxiliary, (timm:{ *:[i1] }))  =>  (BUFFER_STORE_DWORD_BOTHEN_exact anonymous_15037:{ *:[f32] }:$vdata, (REG_SEQUENCE:{ *:[i64] } VReg_64:{ *:[i32] }, VGPR_32:{ *:[i32] }:$vindex, sub0:{ *:[i32] }, VGPR_32:{ *:[i32] }:$voffset, sub1:{ *:[i32] }), SReg_128:{ *:[v4i32] }:$rsrc, SCSrc_b32:{ *:[i32] }:$soffset, (timm:{ *:[i32] }):$offset, (extract_cpol:{ *:[i32] } ?:{ *:[i32] }:$auxiliary), (extract_swz:{ *:[i1] } ?:{ *:[i32] }:$auxiliary))
        GIR_MakeTempReg, /*TempRegID*/0, /*TypeID*/GILLT_s64,
        GIR_BuildMI, /*InsnID*/1, /*Opcode*/GIMT_Encode2(TargetOpcode::REG_SEQUENCE),
        GIR_AddTempRegister, /*InsnID*/1, /*TempRegID*/0, /*TempRegFlags*/GIMT_Encode2(RegState::Define),
        GIR_Copy, /*NewInsnID*/1, /*OldInsnID*/0, /*OpIdx*/2, // vindex
        GIR_AddImm8, /*InsnID*/1, /*SubRegIndex*/3,
        GIR_Copy, /*NewInsnID*/1, /*OldInsnID*/0, /*OpIdx*/3, // voffset
        GIR_AddImm8, /*InsnID*/1, /*SubRegIndex*/11,
        GIR_ConstrainOperandRC, /*InsnID*/1, /*Op*/0, GIMT_Encode2(AMDGPU::VReg_64RegClassID),
        GIR_ConstrainOperandRC, /*InsnID*/1, /*Op*/1, GIMT_Encode2(AMDGPU::VGPR_32RegClassID),
        GIR_ConstrainOperandRC, /*InsnID*/1, /*Op*/3, GIMT_Encode2(AMDGPU::VGPR_32RegClassID),
        GIR_BuildMI, /*InsnID*/0, /*Opcode*/GIMT_Encode2(AMDGPU::BUFFER_STORE_DWORD_BOTHEN_exact),
        GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/0, // vdata
        GIR_AddSimpleTempRegister, /*InsnID*/0, /*TempRegID*/0,
        GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/1, // rsrc
        GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/0, // soffset
        GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/5, // offset
        GIR_CustomOperandRenderer, /*InsnID*/0, /*OldInsnID*/0, /*OpIdx*/6, /*OperandRenderer*/GIMT_Encode2(GICR_renderExtractCPol), // auxiliary
        GIR_CustomOperandRenderer, /*InsnID*/0, /*OldInsnID*/0, /*OpIdx*/6, /*OperandRenderer*/GIMT_Encode2(GICR_renderExtractSWZ), // auxiliary
        GIR_MergeMemOperands, /*InsnID*/0, /*NumInsns*/1, /*MergeInsnID's*/0,
        GIR_ConstrainSelectedInstOperands, /*InsnID*/0,
        GIR_EraseFromParent, /*InsnID*/0,
        // GIR_Coverage, 4396,
        GIR_Done,
      // Label 6793: @498452
      GIM_Try, /*On fail goto*//*Label 6794*/ GIMT_Encode4(498559), // Rule ID 4400 //
        // MIs[0] offset
        GIM_CheckIsImm, /*MI*/0, /*Op*/5,
        // MIs[0] auxiliary
        GIM_CheckIsImm, /*MI*/0, /*Op*/6,
        // MIs[0] Operand 7
        GIM_CheckIsImm, /*MI*/0, /*Op*/7,
        GIM_CheckComplexPattern, /*MI*/0, /*Op*/4, /*Renderer*/GIMT_Encode2(0), GIMT_Encode2(GICP_gi_buf_soffset),
        // (SIbuffer_store f32:{ *:[f32] }:$vdata, v4i32:{ *:[v4i32] }:$rsrc, i32:{ *:[i32] }:$vindex, i32:{ *:[i32] }:$voffset, (BUFSOffset:{ *:[i32] } i32:{ *:[i32] }:$soffset), (timm:{ *:[i32] }):$offset, (timm:{ *:[i32] }):$auxiliary, (timm:{ *:[i1] }))  =>  (BUFFER_STORE_DWORD_VBUFFER_BOTHEN_exact anonymous_15037:{ *:[f32] }:$vdata, (REG_SEQUENCE:{ *:[i64] } VReg_64:{ *:[i32] }, VGPR_32:{ *:[i32] }:$vindex, sub0:{ *:[i32] }, VGPR_32:{ *:[i32] }:$voffset, sub1:{ *:[i32] }), SReg_128:{ *:[v4i32] }:$rsrc, SCSrc_b32:{ *:[i32] }:$soffset, (timm:{ *:[i32] }):$offset, (extract_cpol:{ *:[i32] } ?:{ *:[i32] }:$auxiliary), (extract_swz:{ *:[i1] } ?:{ *:[i32] }:$auxiliary))
        GIR_MakeTempReg, /*TempRegID*/0, /*TypeID*/GILLT_s64,
        GIR_BuildMI, /*InsnID*/1, /*Opcode*/GIMT_Encode2(TargetOpcode::REG_SEQUENCE),
        GIR_AddTempRegister, /*InsnID*/1, /*TempRegID*/0, /*TempRegFlags*/GIMT_Encode2(RegState::Define),
        GIR_Copy, /*NewInsnID*/1, /*OldInsnID*/0, /*OpIdx*/2, // vindex
        GIR_AddImm8, /*InsnID*/1, /*SubRegIndex*/3,
        GIR_Copy, /*NewInsnID*/1, /*OldInsnID*/0, /*OpIdx*/3, // voffset
        GIR_AddImm8, /*InsnID*/1, /*SubRegIndex*/11,
        GIR_ConstrainOperandRC, /*InsnID*/1, /*Op*/0, GIMT_Encode2(AMDGPU::VReg_64RegClassID),
        GIR_ConstrainOperandRC, /*InsnID*/1, /*Op*/1, GIMT_Encode2(AMDGPU::VGPR_32RegClassID),
        GIR_ConstrainOperandRC, /*InsnID*/1, /*Op*/3, GIMT_Encode2(AMDGPU::VGPR_32RegClassID),
        GIR_BuildMI, /*InsnID*/0, /*Opcode*/GIMT_Encode2(AMDGPU::BUFFER_STORE_DWORD_VBUFFER_BOTHEN_exact),
        GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/0, // vdata
        GIR_AddSimpleTempRegister, /*InsnID*/0, /*TempRegID*/0,
        GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/1, // rsrc
        GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/0, // soffset
        GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/5, // offset
        GIR_CustomOperandRenderer, /*InsnID*/0, /*OldInsnID*/0, /*OpIdx*/6, /*OperandRenderer*/GIMT_Encode2(GICR_renderExtractCPol), // auxiliary
        GIR_CustomOperandRenderer, /*InsnID*/0, /*OldInsnID*/0, /*OpIdx*/6, /*OperandRenderer*/GIMT_Encode2(GICR_renderExtractSWZ), // auxiliary
        GIR_MergeMemOperands, /*InsnID*/0, /*NumInsns*/1, /*MergeInsnID's*/0,
        GIR_ConstrainSelectedInstOperands, /*InsnID*/0,
        GIR_EraseFromParent, /*InsnID*/0,
        // GIR_Coverage, 4400,
        GIR_Done,
      // Label 6794: @498559
      GIM_Try, /*On fail goto*//*Label 6795*/ GIMT_Encode4(498669), // Rule ID 4404 //
        GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasUnrestrictedSOffset),
        // MIs[0] offset
        GIM_CheckIsImm, /*MI*/0, /*Op*/5,
        // MIs[0] auxiliary
        GIM_CheckIsImm, /*MI*/0, /*Op*/6,
        // MIs[0] Operand 7
        GIM_CheckIsImm, /*MI*/0, /*Op*/7,
        GIM_CheckComplexPattern, /*MI*/0, /*Op*/4, /*Renderer*/GIMT_Encode2(0), GIMT_Encode2(GICP_gi_buf_soffset),
        // (SIbuffer_store i32:{ *:[i32] }:$vdata, v4i32:{ *:[v4i32] }:$rsrc, i32:{ *:[i32] }:$vindex, i32:{ *:[i32] }:$voffset, (BUFSOffset:{ *:[i32] } i32:{ *:[i32] }:$soffset), (timm:{ *:[i32] }):$offset, (timm:{ *:[i32] }):$auxiliary, (timm:{ *:[i1] }))  =>  (BUFFER_STORE_DWORD_BOTHEN_exact anonymous_15037:{ *:[i32] }:$vdata, (REG_SEQUENCE:{ *:[i64] } VReg_64:{ *:[i32] }, VGPR_32:{ *:[i32] }:$vindex, sub0:{ *:[i32] }, VGPR_32:{ *:[i32] }:$voffset, sub1:{ *:[i32] }), SReg_128:{ *:[v4i32] }:$rsrc, SCSrc_b32:{ *:[i32] }:$soffset, (timm:{ *:[i32] }):$offset, (extract_cpol:{ *:[i32] } ?:{ *:[i32] }:$auxiliary), (extract_swz:{ *:[i1] } ?:{ *:[i32] }:$auxiliary))
        GIR_MakeTempReg, /*TempRegID*/0, /*TypeID*/GILLT_s64,
        GIR_BuildMI, /*InsnID*/1, /*Opcode*/GIMT_Encode2(TargetOpcode::REG_SEQUENCE),
        GIR_AddTempRegister, /*InsnID*/1, /*TempRegID*/0, /*TempRegFlags*/GIMT_Encode2(RegState::Define),
        GIR_Copy, /*NewInsnID*/1, /*OldInsnID*/0, /*OpIdx*/2, // vindex
        GIR_AddImm8, /*InsnID*/1, /*SubRegIndex*/3,
        GIR_Copy, /*NewInsnID*/1, /*OldInsnID*/0, /*OpIdx*/3, // voffset
        GIR_AddImm8, /*InsnID*/1, /*SubRegIndex*/11,
        GIR_ConstrainOperandRC, /*InsnID*/1, /*Op*/0, GIMT_Encode2(AMDGPU::VReg_64RegClassID),
        GIR_ConstrainOperandRC, /*InsnID*/1, /*Op*/1, GIMT_Encode2(AMDGPU::VGPR_32RegClassID),
        GIR_ConstrainOperandRC, /*InsnID*/1, /*Op*/3, GIMT_Encode2(AMDGPU::VGPR_32RegClassID),
        GIR_BuildMI, /*InsnID*/0, /*Opcode*/GIMT_Encode2(AMDGPU::BUFFER_STORE_DWORD_BOTHEN_exact),
        GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/0, // vdata
        GIR_AddSimpleTempRegister, /*InsnID*/0, /*TempRegID*/0,
        GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/1, // rsrc
        GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/0, // soffset
        GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/5, // offset
        GIR_CustomOperandRenderer, /*InsnID*/0, /*OldInsnID*/0, /*OpIdx*/6, /*OperandRenderer*/GIMT_Encode2(GICR_renderExtractCPol), // auxiliary
        GIR_CustomOperandRenderer, /*InsnID*/0, /*OldInsnID*/0, /*OpIdx*/6, /*OperandRenderer*/GIMT_Encode2(GICR_renderExtractSWZ), // auxiliary
        GIR_MergeMemOperands, /*InsnID*/0, /*NumInsns*/1, /*MergeInsnID's*/0,
        GIR_ConstrainSelectedInstOperands, /*InsnID*/0,
        GIR_EraseFromParent, /*InsnID*/0,
        // GIR_Coverage, 4404,
        GIR_Done,
      // Label 6795: @498669
      GIM_Try, /*On fail goto*//*Label 6796*/ GIMT_Encode4(498776), // Rule ID 4408 //
        // MIs[0] offset
        GIM_CheckIsImm, /*MI*/0, /*Op*/5,
        // MIs[0] auxiliary
        GIM_CheckIsImm, /*MI*/0, /*Op*/6,
        // MIs[0] Operand 7
        GIM_CheckIsImm, /*MI*/0, /*Op*/7,
        GIM_CheckComplexPattern, /*MI*/0, /*Op*/4, /*Renderer*/GIMT_Encode2(0), GIMT_Encode2(GICP_gi_buf_soffset),
        // (SIbuffer_store i32:{ *:[i32] }:$vdata, v4i32:{ *:[v4i32] }:$rsrc, i32:{ *:[i32] }:$vindex, i32:{ *:[i32] }:$voffset, (BUFSOffset:{ *:[i32] } i32:{ *:[i32] }:$soffset), (timm:{ *:[i32] }):$offset, (timm:{ *:[i32] }):$auxiliary, (timm:{ *:[i1] }))  =>  (BUFFER_STORE_DWORD_VBUFFER_BOTHEN_exact anonymous_15037:{ *:[i32] }:$vdata, (REG_SEQUENCE:{ *:[i64] } VReg_64:{ *:[i32] }, VGPR_32:{ *:[i32] }:$vindex, sub0:{ *:[i32] }, VGPR_32:{ *:[i32] }:$voffset, sub1:{ *:[i32] }), SReg_128:{ *:[v4i32] }:$rsrc, SCSrc_b32:{ *:[i32] }:$soffset, (timm:{ *:[i32] }):$offset, (extract_cpol:{ *:[i32] } ?:{ *:[i32] }:$auxiliary), (extract_swz:{ *:[i1] } ?:{ *:[i32] }:$auxiliary))
        GIR_MakeTempReg, /*TempRegID*/0, /*TypeID*/GILLT_s64,
        GIR_BuildMI, /*InsnID*/1, /*Opcode*/GIMT_Encode2(TargetOpcode::REG_SEQUENCE),
        GIR_AddTempRegister, /*InsnID*/1, /*TempRegID*/0, /*TempRegFlags*/GIMT_Encode2(RegState::Define),
        GIR_Copy, /*NewInsnID*/1, /*OldInsnID*/0, /*OpIdx*/2, // vindex
        GIR_AddImm8, /*InsnID*/1, /*SubRegIndex*/3,
        GIR_Copy, /*NewInsnID*/1, /*OldInsnID*/0, /*OpIdx*/3, // voffset
        GIR_AddImm8, /*InsnID*/1, /*SubRegIndex*/11,
        GIR_ConstrainOperandRC, /*InsnID*/1, /*Op*/0, GIMT_Encode2(AMDGPU::VReg_64RegClassID),
        GIR_ConstrainOperandRC, /*InsnID*/1, /*Op*/1, GIMT_Encode2(AMDGPU::VGPR_32RegClassID),
        GIR_ConstrainOperandRC, /*InsnID*/1, /*Op*/3, GIMT_Encode2(AMDGPU::VGPR_32RegClassID),
        GIR_BuildMI, /*InsnID*/0, /*Opcode*/GIMT_Encode2(AMDGPU::BUFFER_STORE_DWORD_VBUFFER_BOTHEN_exact),
        GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/0, // vdata
        GIR_AddSimpleTempRegister, /*InsnID*/0, /*TempRegID*/0,
        GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/1, // rsrc
        GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/0, // soffset
        GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/5, // offset
        GIR_CustomOperandRenderer, /*InsnID*/0, /*OldInsnID*/0, /*OpIdx*/6, /*OperandRenderer*/GIMT_Encode2(GICR_renderExtractCPol), // auxiliary
        GIR_CustomOperandRenderer, /*InsnID*/0, /*OldInsnID*/0, /*OpIdx*/6, /*OperandRenderer*/GIMT_Encode2(GICR_renderExtractSWZ), // auxiliary
        GIR_MergeMemOperands, /*InsnID*/0, /*NumInsns*/1, /*MergeInsnID's*/0,
        GIR_ConstrainSelectedInstOperands, /*InsnID*/0,
        GIR_EraseFromParent, /*InsnID*/0,
        // GIR_Coverage, 4408,
        GIR_Done,
      // Label 6796: @498776
      GIM_Reject,
    // Label 6780: @498777
    GIM_Reject,
    // Label 6774: @498778
    GIM_Try, /*On fail goto*//*Label 6797*/ GIMT_Encode4(500168),
      GIM_CheckType, /*MI*/0, /*Op*/1, /*Type*/GILLT_v4s32,
      GIM_CheckType, /*MI*/0, /*Op*/2, /*Type*/GILLT_s32,
      GIM_CheckType, /*MI*/0, /*Op*/3, /*Type*/GILLT_s32,
      GIM_CheckType, /*MI*/0, /*Op*/4, /*Type*/GILLT_s32,
      GIM_Try, /*On fail goto*//*Label 6798*/ GIMT_Encode4(498881), // Rule ID 4409 //
        GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasUnrestrictedSOffset),
        GIM_CheckConstantInt8, /*MI*/0, /*Op*/2, 0,
        GIM_CheckConstantInt8, /*MI*/0, /*Op*/3, 0,
        // MIs[0] offset
        GIM_CheckIsImm, /*MI*/0, /*Op*/5,
        // MIs[0] auxiliary
        GIM_CheckIsImm, /*MI*/0, /*Op*/6,
        // MIs[0] Operand 7
        GIM_CheckLiteralInt, /*MI*/0, /*Op*/7, GIMT_Encode8(0),
        GIM_CheckComplexPattern, /*MI*/0, /*Op*/4, /*Renderer*/GIMT_Encode2(0), GIMT_Encode2(GICP_gi_buf_soffset),
        // (SIbuffer_store v2i16:{ *:[v2i16] }:$vdata, v4i32:{ *:[v4i32] }:$rsrc, 0:{ *:[i32] }, 0:{ *:[i32] }, (BUFSOffset:{ *:[i32] } i32:{ *:[i32] }:$soffset), (timm:{ *:[i32] }):$offset, (timm:{ *:[i32] }):$auxiliary, 0:{ *:[i1] })  =>  (BUFFER_STORE_DWORD_OFFSET_exact anonymous_15037:{ *:[v2i16] }:$vdata, SReg_128:{ *:[v4i32] }:$rsrc, SCSrc_b32:{ *:[i32] }:$soffset, (timm:{ *:[i32] }):$offset, (extract_cpol:{ *:[i32] } ?:{ *:[i32] }:$auxiliary), (extract_swz:{ *:[i1] } ?:{ *:[i32] }:$auxiliary))
        GIR_BuildMI, /*InsnID*/0, /*Opcode*/GIMT_Encode2(AMDGPU::BUFFER_STORE_DWORD_OFFSET_exact),
        GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/0, // vdata
        GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/1, // rsrc
        GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/0, // soffset
        GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/5, // offset
        GIR_CustomOperandRenderer, /*InsnID*/0, /*OldInsnID*/0, /*OpIdx*/6, /*OperandRenderer*/GIMT_Encode2(GICR_renderExtractCPol), // auxiliary
        GIR_CustomOperandRenderer, /*InsnID*/0, /*OldInsnID*/0, /*OpIdx*/6, /*OperandRenderer*/GIMT_Encode2(GICR_renderExtractSWZ), // auxiliary
        GIR_MergeMemOperands, /*InsnID*/0, /*NumInsns*/1, /*MergeInsnID's*/0,
        GIR_ConstrainSelectedInstOperands, /*InsnID*/0,
        GIR_EraseFromParent, /*InsnID*/0,
        // GIR_Coverage, 4409,
        GIR_Done,
      // Label 6798: @498881
      GIM_Try, /*On fail goto*//*Label 6799*/ GIMT_Encode4(498960), // Rule ID 4413 //
        GIM_CheckConstantInt8, /*MI*/0, /*Op*/2, 0,
        GIM_CheckConstantInt8, /*MI*/0, /*Op*/3, 0,
        // MIs[0] offset
        GIM_CheckIsImm, /*MI*/0, /*Op*/5,
        // MIs[0] auxiliary
        GIM_CheckIsImm, /*MI*/0, /*Op*/6,
        // MIs[0] Operand 7
        GIM_CheckLiteralInt, /*MI*/0, /*Op*/7, GIMT_Encode8(0),
        GIM_CheckComplexPattern, /*MI*/0, /*Op*/4, /*Renderer*/GIMT_Encode2(0), GIMT_Encode2(GICP_gi_buf_soffset),
        // (SIbuffer_store v2i16:{ *:[v2i16] }:$vdata, v4i32:{ *:[v4i32] }:$rsrc, 0:{ *:[i32] }, 0:{ *:[i32] }, (BUFSOffset:{ *:[i32] } i32:{ *:[i32] }:$soffset), (timm:{ *:[i32] }):$offset, (timm:{ *:[i32] }):$auxiliary, 0:{ *:[i1] })  =>  (BUFFER_STORE_DWORD_VBUFFER_OFFSET_exact anonymous_15037:{ *:[v2i16] }:$vdata, SReg_128:{ *:[v4i32] }:$rsrc, SCSrc_b32:{ *:[i32] }:$soffset, (timm:{ *:[i32] }):$offset, (extract_cpol:{ *:[i32] } ?:{ *:[i32] }:$auxiliary), (extract_swz:{ *:[i1] } ?:{ *:[i32] }:$auxiliary))
        GIR_BuildMI, /*InsnID*/0, /*Opcode*/GIMT_Encode2(AMDGPU::BUFFER_STORE_DWORD_VBUFFER_OFFSET_exact),
        GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/0, // vdata
        GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/1, // rsrc
        GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/0, // soffset
        GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/5, // offset
        GIR_CustomOperandRenderer, /*InsnID*/0, /*OldInsnID*/0, /*OpIdx*/6, /*OperandRenderer*/GIMT_Encode2(GICR_renderExtractCPol), // auxiliary
        GIR_CustomOperandRenderer, /*InsnID*/0, /*OldInsnID*/0, /*OpIdx*/6, /*OperandRenderer*/GIMT_Encode2(GICR_renderExtractSWZ), // auxiliary
        GIR_MergeMemOperands, /*InsnID*/0, /*NumInsns*/1, /*MergeInsnID's*/0,
        GIR_ConstrainSelectedInstOperands, /*InsnID*/0,
        GIR_EraseFromParent, /*InsnID*/0,
        // GIR_Coverage, 4413,
        GIR_Done,
      // Label 6799: @498960
      GIM_Try, /*On fail goto*//*Label 6800*/ GIMT_Encode4(499042), // Rule ID 4417 //
        GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasUnrestrictedSOffset),
        GIM_CheckConstantInt8, /*MI*/0, /*Op*/2, 0,
        GIM_CheckConstantInt8, /*MI*/0, /*Op*/3, 0,
        // MIs[0] offset
        GIM_CheckIsImm, /*MI*/0, /*Op*/5,
        // MIs[0] auxiliary
        GIM_CheckIsImm, /*MI*/0, /*Op*/6,
        // MIs[0] Operand 7
        GIM_CheckLiteralInt, /*MI*/0, /*Op*/7, GIMT_Encode8(0),
        GIM_CheckComplexPattern, /*MI*/0, /*Op*/4, /*Renderer*/GIMT_Encode2(0), GIMT_Encode2(GICP_gi_buf_soffset),
        // (SIbuffer_store v2f16:{ *:[v2f16] }:$vdata, v4i32:{ *:[v4i32] }:$rsrc, 0:{ *:[i32] }, 0:{ *:[i32] }, (BUFSOffset:{ *:[i32] } i32:{ *:[i32] }:$soffset), (timm:{ *:[i32] }):$offset, (timm:{ *:[i32] }):$auxiliary, 0:{ *:[i1] })  =>  (BUFFER_STORE_DWORD_OFFSET_exact anonymous_15037:{ *:[v2f16] }:$vdata, SReg_128:{ *:[v4i32] }:$rsrc, SCSrc_b32:{ *:[i32] }:$soffset, (timm:{ *:[i32] }):$offset, (extract_cpol:{ *:[i32] } ?:{ *:[i32] }:$auxiliary), (extract_swz:{ *:[i1] } ?:{ *:[i32] }:$auxiliary))
        GIR_BuildMI, /*InsnID*/0, /*Opcode*/GIMT_Encode2(AMDGPU::BUFFER_STORE_DWORD_OFFSET_exact),
        GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/0, // vdata
        GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/1, // rsrc
        GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/0, // soffset
        GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/5, // offset
        GIR_CustomOperandRenderer, /*InsnID*/0, /*OldInsnID*/0, /*OpIdx*/6, /*OperandRenderer*/GIMT_Encode2(GICR_renderExtractCPol), // auxiliary
        GIR_CustomOperandRenderer, /*InsnID*/0, /*OldInsnID*/0, /*OpIdx*/6, /*OperandRenderer*/GIMT_Encode2(GICR_renderExtractSWZ), // auxiliary
        GIR_MergeMemOperands, /*InsnID*/0, /*NumInsns*/1, /*MergeInsnID's*/0,
        GIR_ConstrainSelectedInstOperands, /*InsnID*/0,
        GIR_EraseFromParent, /*InsnID*/0,
        // GIR_Coverage, 4417,
        GIR_Done,
      // Label 6800: @499042
      GIM_Try, /*On fail goto*//*Label 6801*/ GIMT_Encode4(499121), // Rule ID 4421 //
        GIM_CheckConstantInt8, /*MI*/0, /*Op*/2, 0,
        GIM_CheckConstantInt8, /*MI*/0, /*Op*/3, 0,
        // MIs[0] offset
        GIM_CheckIsImm, /*MI*/0, /*Op*/5,
        // MIs[0] auxiliary
        GIM_CheckIsImm, /*MI*/0, /*Op*/6,
        // MIs[0] Operand 7
        GIM_CheckLiteralInt, /*MI*/0, /*Op*/7, GIMT_Encode8(0),
        GIM_CheckComplexPattern, /*MI*/0, /*Op*/4, /*Renderer*/GIMT_Encode2(0), GIMT_Encode2(GICP_gi_buf_soffset),
        // (SIbuffer_store v2f16:{ *:[v2f16] }:$vdata, v4i32:{ *:[v4i32] }:$rsrc, 0:{ *:[i32] }, 0:{ *:[i32] }, (BUFSOffset:{ *:[i32] } i32:{ *:[i32] }:$soffset), (timm:{ *:[i32] }):$offset, (timm:{ *:[i32] }):$auxiliary, 0:{ *:[i1] })  =>  (BUFFER_STORE_DWORD_VBUFFER_OFFSET_exact anonymous_15037:{ *:[v2f16] }:$vdata, SReg_128:{ *:[v4i32] }:$rsrc, SCSrc_b32:{ *:[i32] }:$soffset, (timm:{ *:[i32] }):$offset, (extract_cpol:{ *:[i32] } ?:{ *:[i32] }:$auxiliary), (extract_swz:{ *:[i1] } ?:{ *:[i32] }:$auxiliary))
        GIR_BuildMI, /*InsnID*/0, /*Opcode*/GIMT_Encode2(AMDGPU::BUFFER_STORE_DWORD_VBUFFER_OFFSET_exact),
        GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/0, // vdata
        GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/1, // rsrc
        GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/0, // soffset
        GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/5, // offset
        GIR_CustomOperandRenderer, /*InsnID*/0, /*OldInsnID*/0, /*OpIdx*/6, /*OperandRenderer*/GIMT_Encode2(GICR_renderExtractCPol), // auxiliary
        GIR_CustomOperandRenderer, /*InsnID*/0, /*OldInsnID*/0, /*OpIdx*/6, /*OperandRenderer*/GIMT_Encode2(GICR_renderExtractSWZ), // auxiliary
        GIR_MergeMemOperands, /*InsnID*/0, /*NumInsns*/1, /*MergeInsnID's*/0,
        GIR_ConstrainSelectedInstOperands, /*InsnID*/0,
        GIR_EraseFromParent, /*InsnID*/0,
        // GIR_Coverage, 4421,
        GIR_Done,
      // Label 6801: @499121
      GIM_Try, /*On fail goto*//*Label 6802*/ GIMT_Encode4(499203), // Rule ID 4410 //
        GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasUnrestrictedSOffset),
        GIM_CheckConstantInt8, /*MI*/0, /*Op*/2, 0,
        // MIs[0] offset
        GIM_CheckIsImm, /*MI*/0, /*Op*/5,
        // MIs[0] auxiliary
        GIM_CheckIsImm, /*MI*/0, /*Op*/6,
        // MIs[0] Operand 7
        GIM_CheckLiteralInt, /*MI*/0, /*Op*/7, GIMT_Encode8(0),
        GIM_CheckComplexPattern, /*MI*/0, /*Op*/4, /*Renderer*/GIMT_Encode2(0), GIMT_Encode2(GICP_gi_buf_soffset),
        // (SIbuffer_store v2i16:{ *:[v2i16] }:$vdata, v4i32:{ *:[v4i32] }:$rsrc, 0:{ *:[i32] }, i32:{ *:[i32] }:$voffset, (BUFSOffset:{ *:[i32] } i32:{ *:[i32] }:$soffset), (timm:{ *:[i32] }):$offset, (timm:{ *:[i32] }):$auxiliary, 0:{ *:[i1] })  =>  (BUFFER_STORE_DWORD_OFFEN_exact anonymous_15037:{ *:[v2i16] }:$vdata, VGPR_32:{ *:[i32] }:$voffset, SReg_128:{ *:[v4i32] }:$rsrc, SCSrc_b32:{ *:[i32] }:$soffset, (timm:{ *:[i32] }):$offset, (extract_cpol:{ *:[i32] } ?:{ *:[i32] }:$auxiliary), (extract_swz:{ *:[i1] } ?:{ *:[i32] }:$auxiliary))
        GIR_BuildMI, /*InsnID*/0, /*Opcode*/GIMT_Encode2(AMDGPU::BUFFER_STORE_DWORD_OFFEN_exact),
        GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/0, // vdata
        GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/3, // voffset
        GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/1, // rsrc
        GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/0, // soffset
        GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/5, // offset
        GIR_CustomOperandRenderer, /*InsnID*/0, /*OldInsnID*/0, /*OpIdx*/6, /*OperandRenderer*/GIMT_Encode2(GICR_renderExtractCPol), // auxiliary
        GIR_CustomOperandRenderer, /*InsnID*/0, /*OldInsnID*/0, /*OpIdx*/6, /*OperandRenderer*/GIMT_Encode2(GICR_renderExtractSWZ), // auxiliary
        GIR_MergeMemOperands, /*InsnID*/0, /*NumInsns*/1, /*MergeInsnID's*/0,
        GIR_ConstrainSelectedInstOperands, /*InsnID*/0,
        GIR_EraseFromParent, /*InsnID*/0,
        // GIR_Coverage, 4410,
        GIR_Done,
      // Label 6802: @499203
      GIM_Try, /*On fail goto*//*Label 6803*/ GIMT_Encode4(499282), // Rule ID 4414 //
        GIM_CheckConstantInt8, /*MI*/0, /*Op*/2, 0,
        // MIs[0] offset
        GIM_CheckIsImm, /*MI*/0, /*Op*/5,
        // MIs[0] auxiliary
        GIM_CheckIsImm, /*MI*/0, /*Op*/6,
        // MIs[0] Operand 7
        GIM_CheckLiteralInt, /*MI*/0, /*Op*/7, GIMT_Encode8(0),
        GIM_CheckComplexPattern, /*MI*/0, /*Op*/4, /*Renderer*/GIMT_Encode2(0), GIMT_Encode2(GICP_gi_buf_soffset),
        // (SIbuffer_store v2i16:{ *:[v2i16] }:$vdata, v4i32:{ *:[v4i32] }:$rsrc, 0:{ *:[i32] }, i32:{ *:[i32] }:$voffset, (BUFSOffset:{ *:[i32] } i32:{ *:[i32] }:$soffset), (timm:{ *:[i32] }):$offset, (timm:{ *:[i32] }):$auxiliary, 0:{ *:[i1] })  =>  (BUFFER_STORE_DWORD_VBUFFER_OFFEN_exact anonymous_15037:{ *:[v2i16] }:$vdata, VGPR_32:{ *:[i32] }:$voffset, SReg_128:{ *:[v4i32] }:$rsrc, SCSrc_b32:{ *:[i32] }:$soffset, (timm:{ *:[i32] }):$offset, (extract_cpol:{ *:[i32] } ?:{ *:[i32] }:$auxiliary), (extract_swz:{ *:[i1] } ?:{ *:[i32] }:$auxiliary))
        GIR_BuildMI, /*InsnID*/0, /*Opcode*/GIMT_Encode2(AMDGPU::BUFFER_STORE_DWORD_VBUFFER_OFFEN_exact),
        GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/0, // vdata
        GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/3, // voffset
        GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/1, // rsrc
        GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/0, // soffset
        GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/5, // offset
        GIR_CustomOperandRenderer, /*InsnID*/0, /*OldInsnID*/0, /*OpIdx*/6, /*OperandRenderer*/GIMT_Encode2(GICR_renderExtractCPol), // auxiliary
        GIR_CustomOperandRenderer, /*InsnID*/0, /*OldInsnID*/0, /*OpIdx*/6, /*OperandRenderer*/GIMT_Encode2(GICR_renderExtractSWZ), // auxiliary
        GIR_MergeMemOperands, /*InsnID*/0, /*NumInsns*/1, /*MergeInsnID's*/0,
        GIR_ConstrainSelectedInstOperands, /*InsnID*/0,
        GIR_EraseFromParent, /*InsnID*/0,
        // GIR_Coverage, 4414,
        GIR_Done,
      // Label 6803: @499282
      GIM_Try, /*On fail goto*//*Label 6804*/ GIMT_Encode4(499364), // Rule ID 4418 //
        GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasUnrestrictedSOffset),
        GIM_CheckConstantInt8, /*MI*/0, /*Op*/2, 0,
        // MIs[0] offset
        GIM_CheckIsImm, /*MI*/0, /*Op*/5,
        // MIs[0] auxiliary
        GIM_CheckIsImm, /*MI*/0, /*Op*/6,
        // MIs[0] Operand 7
        GIM_CheckLiteralInt, /*MI*/0, /*Op*/7, GIMT_Encode8(0),
        GIM_CheckComplexPattern, /*MI*/0, /*Op*/4, /*Renderer*/GIMT_Encode2(0), GIMT_Encode2(GICP_gi_buf_soffset),
        // (SIbuffer_store v2f16:{ *:[v2f16] }:$vdata, v4i32:{ *:[v4i32] }:$rsrc, 0:{ *:[i32] }, i32:{ *:[i32] }:$voffset, (BUFSOffset:{ *:[i32] } i32:{ *:[i32] }:$soffset), (timm:{ *:[i32] }):$offset, (timm:{ *:[i32] }):$auxiliary, 0:{ *:[i1] })  =>  (BUFFER_STORE_DWORD_OFFEN_exact anonymous_15037:{ *:[v2f16] }:$vdata, VGPR_32:{ *:[i32] }:$voffset, SReg_128:{ *:[v4i32] }:$rsrc, SCSrc_b32:{ *:[i32] }:$soffset, (timm:{ *:[i32] }):$offset, (extract_cpol:{ *:[i32] } ?:{ *:[i32] }:$auxiliary), (extract_swz:{ *:[i1] } ?:{ *:[i32] }:$auxiliary))
        GIR_BuildMI, /*InsnID*/0, /*Opcode*/GIMT_Encode2(AMDGPU::BUFFER_STORE_DWORD_OFFEN_exact),
        GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/0, // vdata
        GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/3, // voffset
        GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/1, // rsrc
        GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/0, // soffset
        GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/5, // offset
        GIR_CustomOperandRenderer, /*InsnID*/0, /*OldInsnID*/0, /*OpIdx*/6, /*OperandRenderer*/GIMT_Encode2(GICR_renderExtractCPol), // auxiliary
        GIR_CustomOperandRenderer, /*InsnID*/0, /*OldInsnID*/0, /*OpIdx*/6, /*OperandRenderer*/GIMT_Encode2(GICR_renderExtractSWZ), // auxiliary
        GIR_MergeMemOperands, /*InsnID*/0, /*NumInsns*/1, /*MergeInsnID's*/0,
        GIR_ConstrainSelectedInstOperands, /*InsnID*/0,
        GIR_EraseFromParent, /*InsnID*/0,
        // GIR_Coverage, 4418,
        GIR_Done,
      // Label 6804: @499364
      GIM_Try, /*On fail goto*//*Label 6805*/ GIMT_Encode4(499443), // Rule ID 4422 //
        GIM_CheckConstantInt8, /*MI*/0, /*Op*/2, 0,
        // MIs[0] offset
        GIM_CheckIsImm, /*MI*/0, /*Op*/5,
        // MIs[0] auxiliary
        GIM_CheckIsImm, /*MI*/0, /*Op*/6,
        // MIs[0] Operand 7
        GIM_CheckLiteralInt, /*MI*/0, /*Op*/7, GIMT_Encode8(0),
        GIM_CheckComplexPattern, /*MI*/0, /*Op*/4, /*Renderer*/GIMT_Encode2(0), GIMT_Encode2(GICP_gi_buf_soffset),
        // (SIbuffer_store v2f16:{ *:[v2f16] }:$vdata, v4i32:{ *:[v4i32] }:$rsrc, 0:{ *:[i32] }, i32:{ *:[i32] }:$voffset, (BUFSOffset:{ *:[i32] } i32:{ *:[i32] }:$soffset), (timm:{ *:[i32] }):$offset, (timm:{ *:[i32] }):$auxiliary, 0:{ *:[i1] })  =>  (BUFFER_STORE_DWORD_VBUFFER_OFFEN_exact anonymous_15037:{ *:[v2f16] }:$vdata, VGPR_32:{ *:[i32] }:$voffset, SReg_128:{ *:[v4i32] }:$rsrc, SCSrc_b32:{ *:[i32] }:$soffset, (timm:{ *:[i32] }):$offset, (extract_cpol:{ *:[i32] } ?:{ *:[i32] }:$auxiliary), (extract_swz:{ *:[i1] } ?:{ *:[i32] }:$auxiliary))
        GIR_BuildMI, /*InsnID*/0, /*Opcode*/GIMT_Encode2(AMDGPU::BUFFER_STORE_DWORD_VBUFFER_OFFEN_exact),
        GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/0, // vdata
        GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/3, // voffset
        GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/1, // rsrc
        GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/0, // soffset
        GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/5, // offset
        GIR_CustomOperandRenderer, /*InsnID*/0, /*OldInsnID*/0, /*OpIdx*/6, /*OperandRenderer*/GIMT_Encode2(GICR_renderExtractCPol), // auxiliary
        GIR_CustomOperandRenderer, /*InsnID*/0, /*OldInsnID*/0, /*OpIdx*/6, /*OperandRenderer*/GIMT_Encode2(GICR_renderExtractSWZ), // auxiliary
        GIR_MergeMemOperands, /*InsnID*/0, /*NumInsns*/1, /*MergeInsnID's*/0,
        GIR_ConstrainSelectedInstOperands, /*InsnID*/0,
        GIR_EraseFromParent, /*InsnID*/0,
        // GIR_Coverage, 4422,
        GIR_Done,
      // Label 6805: @499443
      GIM_Try, /*On fail goto*//*Label 6806*/ GIMT_Encode4(499517), // Rule ID 4411 //
        GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasUnrestrictedSOffset),
        GIM_CheckConstantInt8, /*MI*/0, /*Op*/3, 0,
        // MIs[0] offset
        GIM_CheckIsImm, /*MI*/0, /*Op*/5,
        // MIs[0] auxiliary
        GIM_CheckIsImm, /*MI*/0, /*Op*/6,
        // MIs[0] Operand 7
        GIM_CheckIsImm, /*MI*/0, /*Op*/7,
        GIM_CheckComplexPattern, /*MI*/0, /*Op*/4, /*Renderer*/GIMT_Encode2(0), GIMT_Encode2(GICP_gi_buf_soffset),
        // (SIbuffer_store v2i16:{ *:[v2i16] }:$vdata, v4i32:{ *:[v4i32] }:$rsrc, i32:{ *:[i32] }:$vindex, 0:{ *:[i32] }, (BUFSOffset:{ *:[i32] } i32:{ *:[i32] }:$soffset), (timm:{ *:[i32] }):$offset, (timm:{ *:[i32] }):$auxiliary, (timm:{ *:[i1] }))  =>  (BUFFER_STORE_DWORD_IDXEN_exact anonymous_15037:{ *:[v2i16] }:$vdata, VGPR_32:{ *:[i32] }:$vindex, SReg_128:{ *:[v4i32] }:$rsrc, SCSrc_b32:{ *:[i32] }:$soffset, (timm:{ *:[i32] }):$offset, (extract_cpol:{ *:[i32] } ?:{ *:[i32] }:$auxiliary), (extract_swz:{ *:[i1] } ?:{ *:[i32] }:$auxiliary))
        GIR_BuildMI, /*InsnID*/0, /*Opcode*/GIMT_Encode2(AMDGPU::BUFFER_STORE_DWORD_IDXEN_exact),
        GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/0, // vdata
        GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/2, // vindex
        GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/1, // rsrc
        GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/0, // soffset
        GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/5, // offset
        GIR_CustomOperandRenderer, /*InsnID*/0, /*OldInsnID*/0, /*OpIdx*/6, /*OperandRenderer*/GIMT_Encode2(GICR_renderExtractCPol), // auxiliary
        GIR_CustomOperandRenderer, /*InsnID*/0, /*OldInsnID*/0, /*OpIdx*/6, /*OperandRenderer*/GIMT_Encode2(GICR_renderExtractSWZ), // auxiliary
        GIR_MergeMemOperands, /*InsnID*/0, /*NumInsns*/1, /*MergeInsnID's*/0,
        GIR_ConstrainSelectedInstOperands, /*InsnID*/0,
        GIR_EraseFromParent, /*InsnID*/0,
        // GIR_Coverage, 4411,
        GIR_Done,
      // Label 6806: @499517
      GIM_Try, /*On fail goto*//*Label 6807*/ GIMT_Encode4(499588), // Rule ID 4415 //
        GIM_CheckConstantInt8, /*MI*/0, /*Op*/3, 0,
        // MIs[0] offset
        GIM_CheckIsImm, /*MI*/0, /*Op*/5,
        // MIs[0] auxiliary
        GIM_CheckIsImm, /*MI*/0, /*Op*/6,
        // MIs[0] Operand 7
        GIM_CheckIsImm, /*MI*/0, /*Op*/7,
        GIM_CheckComplexPattern, /*MI*/0, /*Op*/4, /*Renderer*/GIMT_Encode2(0), GIMT_Encode2(GICP_gi_buf_soffset),
        // (SIbuffer_store v2i16:{ *:[v2i16] }:$vdata, v4i32:{ *:[v4i32] }:$rsrc, i32:{ *:[i32] }:$vindex, 0:{ *:[i32] }, (BUFSOffset:{ *:[i32] } i32:{ *:[i32] }:$soffset), (timm:{ *:[i32] }):$offset, (timm:{ *:[i32] }):$auxiliary, (timm:{ *:[i1] }))  =>  (BUFFER_STORE_DWORD_VBUFFER_IDXEN_exact anonymous_15037:{ *:[v2i16] }:$vdata, VGPR_32:{ *:[i32] }:$vindex, SReg_128:{ *:[v4i32] }:$rsrc, SCSrc_b32:{ *:[i32] }:$soffset, (timm:{ *:[i32] }):$offset, (extract_cpol:{ *:[i32] } ?:{ *:[i32] }:$auxiliary), (extract_swz:{ *:[i1] } ?:{ *:[i32] }:$auxiliary))
        GIR_BuildMI, /*InsnID*/0, /*Opcode*/GIMT_Encode2(AMDGPU::BUFFER_STORE_DWORD_VBUFFER_IDXEN_exact),
        GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/0, // vdata
        GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/2, // vindex
        GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/1, // rsrc
        GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/0, // soffset
        GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/5, // offset
        GIR_CustomOperandRenderer, /*InsnID*/0, /*OldInsnID*/0, /*OpIdx*/6, /*OperandRenderer*/GIMT_Encode2(GICR_renderExtractCPol), // auxiliary
        GIR_CustomOperandRenderer, /*InsnID*/0, /*OldInsnID*/0, /*OpIdx*/6, /*OperandRenderer*/GIMT_Encode2(GICR_renderExtractSWZ), // auxiliary
        GIR_MergeMemOperands, /*InsnID*/0, /*NumInsns*/1, /*MergeInsnID's*/0,
        GIR_ConstrainSelectedInstOperands, /*InsnID*/0,
        GIR_EraseFromParent, /*InsnID*/0,
        // GIR_Coverage, 4415,
        GIR_Done,
      // Label 6807: @499588
      GIM_Try, /*On fail goto*//*Label 6808*/ GIMT_Encode4(499662), // Rule ID 4419 //
        GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasUnrestrictedSOffset),
        GIM_CheckConstantInt8, /*MI*/0, /*Op*/3, 0,
        // MIs[0] offset
        GIM_CheckIsImm, /*MI*/0, /*Op*/5,
        // MIs[0] auxiliary
        GIM_CheckIsImm, /*MI*/0, /*Op*/6,
        // MIs[0] Operand 7
        GIM_CheckIsImm, /*MI*/0, /*Op*/7,
        GIM_CheckComplexPattern, /*MI*/0, /*Op*/4, /*Renderer*/GIMT_Encode2(0), GIMT_Encode2(GICP_gi_buf_soffset),
        // (SIbuffer_store v2f16:{ *:[v2f16] }:$vdata, v4i32:{ *:[v4i32] }:$rsrc, i32:{ *:[i32] }:$vindex, 0:{ *:[i32] }, (BUFSOffset:{ *:[i32] } i32:{ *:[i32] }:$soffset), (timm:{ *:[i32] }):$offset, (timm:{ *:[i32] }):$auxiliary, (timm:{ *:[i1] }))  =>  (BUFFER_STORE_DWORD_IDXEN_exact anonymous_15037:{ *:[v2f16] }:$vdata, VGPR_32:{ *:[i32] }:$vindex, SReg_128:{ *:[v4i32] }:$rsrc, SCSrc_b32:{ *:[i32] }:$soffset, (timm:{ *:[i32] }):$offset, (extract_cpol:{ *:[i32] } ?:{ *:[i32] }:$auxiliary), (extract_swz:{ *:[i1] } ?:{ *:[i32] }:$auxiliary))
        GIR_BuildMI, /*InsnID*/0, /*Opcode*/GIMT_Encode2(AMDGPU::BUFFER_STORE_DWORD_IDXEN_exact),
        GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/0, // vdata
        GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/2, // vindex
        GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/1, // rsrc
        GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/0, // soffset
        GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/5, // offset
        GIR_CustomOperandRenderer, /*InsnID*/0, /*OldInsnID*/0, /*OpIdx*/6, /*OperandRenderer*/GIMT_Encode2(GICR_renderExtractCPol), // auxiliary
        GIR_CustomOperandRenderer, /*InsnID*/0, /*OldInsnID*/0, /*OpIdx*/6, /*OperandRenderer*/GIMT_Encode2(GICR_renderExtractSWZ), // auxiliary
        GIR_MergeMemOperands, /*InsnID*/0, /*NumInsns*/1, /*MergeInsnID's*/0,
        GIR_ConstrainSelectedInstOperands, /*InsnID*/0,
        GIR_EraseFromParent, /*InsnID*/0,
        // GIR_Coverage, 4419,
        GIR_Done,
      // Label 6808: @499662
      GIM_Try, /*On fail goto*//*Label 6809*/ GIMT_Encode4(499733), // Rule ID 4423 //
        GIM_CheckConstantInt8, /*MI*/0, /*Op*/3, 0,
        // MIs[0] offset
        GIM_CheckIsImm, /*MI*/0, /*Op*/5,
        // MIs[0] auxiliary
        GIM_CheckIsImm, /*MI*/0, /*Op*/6,
        // MIs[0] Operand 7
        GIM_CheckIsImm, /*MI*/0, /*Op*/7,
        GIM_CheckComplexPattern, /*MI*/0, /*Op*/4, /*Renderer*/GIMT_Encode2(0), GIMT_Encode2(GICP_gi_buf_soffset),
        // (SIbuffer_store v2f16:{ *:[v2f16] }:$vdata, v4i32:{ *:[v4i32] }:$rsrc, i32:{ *:[i32] }:$vindex, 0:{ *:[i32] }, (BUFSOffset:{ *:[i32] } i32:{ *:[i32] }:$soffset), (timm:{ *:[i32] }):$offset, (timm:{ *:[i32] }):$auxiliary, (timm:{ *:[i1] }))  =>  (BUFFER_STORE_DWORD_VBUFFER_IDXEN_exact anonymous_15037:{ *:[v2f16] }:$vdata, VGPR_32:{ *:[i32] }:$vindex, SReg_128:{ *:[v4i32] }:$rsrc, SCSrc_b32:{ *:[i32] }:$soffset, (timm:{ *:[i32] }):$offset, (extract_cpol:{ *:[i32] } ?:{ *:[i32] }:$auxiliary), (extract_swz:{ *:[i1] } ?:{ *:[i32] }:$auxiliary))
        GIR_BuildMI, /*InsnID*/0, /*Opcode*/GIMT_Encode2(AMDGPU::BUFFER_STORE_DWORD_VBUFFER_IDXEN_exact),
        GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/0, // vdata
        GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/2, // vindex
        GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/1, // rsrc
        GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/0, // soffset
        GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/5, // offset
        GIR_CustomOperandRenderer, /*InsnID*/0, /*OldInsnID*/0, /*OpIdx*/6, /*OperandRenderer*/GIMT_Encode2(GICR_renderExtractCPol), // auxiliary
        GIR_CustomOperandRenderer, /*InsnID*/0, /*OldInsnID*/0, /*OpIdx*/6, /*OperandRenderer*/GIMT_Encode2(GICR_renderExtractSWZ), // auxiliary
        GIR_MergeMemOperands, /*InsnID*/0, /*NumInsns*/1, /*MergeInsnID's*/0,
        GIR_ConstrainSelectedInstOperands, /*InsnID*/0,
        GIR_EraseFromParent, /*InsnID*/0,
        // GIR_Coverage, 4423,
        GIR_Done,
      // Label 6809: @499733
      GIM_Try, /*On fail goto*//*Label 6810*/ GIMT_Encode4(499843), // Rule ID 4412 //
        GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasUnrestrictedSOffset),
        // MIs[0] offset
        GIM_CheckIsImm, /*MI*/0, /*Op*/5,
        // MIs[0] auxiliary
        GIM_CheckIsImm, /*MI*/0, /*Op*/6,
        // MIs[0] Operand 7
        GIM_CheckIsImm, /*MI*/0, /*Op*/7,
        GIM_CheckComplexPattern, /*MI*/0, /*Op*/4, /*Renderer*/GIMT_Encode2(0), GIMT_Encode2(GICP_gi_buf_soffset),
        // (SIbuffer_store v2i16:{ *:[v2i16] }:$vdata, v4i32:{ *:[v4i32] }:$rsrc, i32:{ *:[i32] }:$vindex, i32:{ *:[i32] }:$voffset, (BUFSOffset:{ *:[i32] } i32:{ *:[i32] }:$soffset), (timm:{ *:[i32] }):$offset, (timm:{ *:[i32] }):$auxiliary, (timm:{ *:[i1] }))  =>  (BUFFER_STORE_DWORD_BOTHEN_exact anonymous_15037:{ *:[v2i16] }:$vdata, (REG_SEQUENCE:{ *:[i64] } VReg_64:{ *:[i32] }, VGPR_32:{ *:[i32] }:$vindex, sub0:{ *:[i32] }, VGPR_32:{ *:[i32] }:$voffset, sub1:{ *:[i32] }), SReg_128:{ *:[v4i32] }:$rsrc, SCSrc_b32:{ *:[i32] }:$soffset, (timm:{ *:[i32] }):$offset, (extract_cpol:{ *:[i32] } ?:{ *:[i32] }:$auxiliary), (extract_swz:{ *:[i1] } ?:{ *:[i32] }:$auxiliary))
        GIR_MakeTempReg, /*TempRegID*/0, /*TypeID*/GILLT_s64,
        GIR_BuildMI, /*InsnID*/1, /*Opcode*/GIMT_Encode2(TargetOpcode::REG_SEQUENCE),
        GIR_AddTempRegister, /*InsnID*/1, /*TempRegID*/0, /*TempRegFlags*/GIMT_Encode2(RegState::Define),
        GIR_Copy, /*NewInsnID*/1, /*OldInsnID*/0, /*OpIdx*/2, // vindex
        GIR_AddImm8, /*InsnID*/1, /*SubRegIndex*/3,
        GIR_Copy, /*NewInsnID*/1, /*OldInsnID*/0, /*OpIdx*/3, // voffset
        GIR_AddImm8, /*InsnID*/1, /*SubRegIndex*/11,
        GIR_ConstrainOperandRC, /*InsnID*/1, /*Op*/0, GIMT_Encode2(AMDGPU::VReg_64RegClassID),
        GIR_ConstrainOperandRC, /*InsnID*/1, /*Op*/1, GIMT_Encode2(AMDGPU::VGPR_32RegClassID),
        GIR_ConstrainOperandRC, /*InsnID*/1, /*Op*/3, GIMT_Encode2(AMDGPU::VGPR_32RegClassID),
        GIR_BuildMI, /*InsnID*/0, /*Opcode*/GIMT_Encode2(AMDGPU::BUFFER_STORE_DWORD_BOTHEN_exact),
        GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/0, // vdata
        GIR_AddSimpleTempRegister, /*InsnID*/0, /*TempRegID*/0,
        GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/1, // rsrc
        GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/0, // soffset
        GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/5, // offset
        GIR_CustomOperandRenderer, /*InsnID*/0, /*OldInsnID*/0, /*OpIdx*/6, /*OperandRenderer*/GIMT_Encode2(GICR_renderExtractCPol), // auxiliary
        GIR_CustomOperandRenderer, /*InsnID*/0, /*OldInsnID*/0, /*OpIdx*/6, /*OperandRenderer*/GIMT_Encode2(GICR_renderExtractSWZ), // auxiliary
        GIR_MergeMemOperands, /*InsnID*/0, /*NumInsns*/1, /*MergeInsnID's*/0,
        GIR_ConstrainSelectedInstOperands, /*InsnID*/0,
        GIR_EraseFromParent, /*InsnID*/0,
        // GIR_Coverage, 4412,
        GIR_Done,
      // Label 6810: @499843
      GIM_Try, /*On fail goto*//*Label 6811*/ GIMT_Encode4(499950), // Rule ID 4416 //
        // MIs[0] offset
        GIM_CheckIsImm, /*MI*/0, /*Op*/5,
        // MIs[0] auxiliary
        GIM_CheckIsImm, /*MI*/0, /*Op*/6,
        // MIs[0] Operand 7
        GIM_CheckIsImm, /*MI*/0, /*Op*/7,
        GIM_CheckComplexPattern, /*MI*/0, /*Op*/4, /*Renderer*/GIMT_Encode2(0), GIMT_Encode2(GICP_gi_buf_soffset),
        // (SIbuffer_store v2i16:{ *:[v2i16] }:$vdata, v4i32:{ *:[v4i32] }:$rsrc, i32:{ *:[i32] }:$vindex, i32:{ *:[i32] }:$voffset, (BUFSOffset:{ *:[i32] } i32:{ *:[i32] }:$soffset), (timm:{ *:[i32] }):$offset, (timm:{ *:[i32] }):$auxiliary, (timm:{ *:[i1] }))  =>  (BUFFER_STORE_DWORD_VBUFFER_BOTHEN_exact anonymous_15037:{ *:[v2i16] }:$vdata, (REG_SEQUENCE:{ *:[i64] } VReg_64:{ *:[i32] }, VGPR_32:{ *:[i32] }:$vindex, sub0:{ *:[i32] }, VGPR_32:{ *:[i32] }:$voffset, sub1:{ *:[i32] }), SReg_128:{ *:[v4i32] }:$rsrc, SCSrc_b32:{ *:[i32] }:$soffset, (timm:{ *:[i32] }):$offset, (extract_cpol:{ *:[i32] } ?:{ *:[i32] }:$auxiliary), (extract_swz:{ *:[i1] } ?:{ *:[i32] }:$auxiliary))
        GIR_MakeTempReg, /*TempRegID*/0, /*TypeID*/GILLT_s64,
        GIR_BuildMI, /*InsnID*/1, /*Opcode*/GIMT_Encode2(TargetOpcode::REG_SEQUENCE),
        GIR_AddTempRegister, /*InsnID*/1, /*TempRegID*/0, /*TempRegFlags*/GIMT_Encode2(RegState::Define),
        GIR_Copy, /*NewInsnID*/1, /*OldInsnID*/0, /*OpIdx*/2, // vindex
        GIR_AddImm8, /*InsnID*/1, /*SubRegIndex*/3,
        GIR_Copy, /*NewInsnID*/1, /*OldInsnID*/0, /*OpIdx*/3, // voffset
        GIR_AddImm8, /*InsnID*/1, /*SubRegIndex*/11,
        GIR_ConstrainOperandRC, /*InsnID*/1, /*Op*/0, GIMT_Encode2(AMDGPU::VReg_64RegClassID),
        GIR_ConstrainOperandRC, /*InsnID*/1, /*Op*/1, GIMT_Encode2(AMDGPU::VGPR_32RegClassID),
        GIR_ConstrainOperandRC, /*InsnID*/1, /*Op*/3, GIMT_Encode2(AMDGPU::VGPR_32RegClassID),
        GIR_BuildMI, /*InsnID*/0, /*Opcode*/GIMT_Encode2(AMDGPU::BUFFER_STORE_DWORD_VBUFFER_BOTHEN_exact),
        GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/0, // vdata
        GIR_AddSimpleTempRegister, /*InsnID*/0, /*TempRegID*/0,
        GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/1, // rsrc
        GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/0, // soffset
        GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/5, // offset
        GIR_CustomOperandRenderer, /*InsnID*/0, /*OldInsnID*/0, /*OpIdx*/6, /*OperandRenderer*/GIMT_Encode2(GICR_renderExtractCPol), // auxiliary
        GIR_CustomOperandRenderer, /*InsnID*/0, /*OldInsnID*/0, /*OpIdx*/6, /*OperandRenderer*/GIMT_Encode2(GICR_renderExtractSWZ), // auxiliary
        GIR_MergeMemOperands, /*InsnID*/0, /*NumInsns*/1, /*MergeInsnID's*/0,
        GIR_ConstrainSelectedInstOperands, /*InsnID*/0,
        GIR_EraseFromParent, /*InsnID*/0,
        // GIR_Coverage, 4416,
        GIR_Done,
      // Label 6811: @499950
      GIM_Try, /*On fail goto*//*Label 6812*/ GIMT_Encode4(500060), // Rule ID 4420 //
        GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasUnrestrictedSOffset),
        // MIs[0] offset
        GIM_CheckIsImm, /*MI*/0, /*Op*/5,
        // MIs[0] auxiliary
        GIM_CheckIsImm, /*MI*/0, /*Op*/6,
        // MIs[0] Operand 7
        GIM_CheckIsImm, /*MI*/0, /*Op*/7,
        GIM_CheckComplexPattern, /*MI*/0, /*Op*/4, /*Renderer*/GIMT_Encode2(0), GIMT_Encode2(GICP_gi_buf_soffset),
        // (SIbuffer_store v2f16:{ *:[v2f16] }:$vdata, v4i32:{ *:[v4i32] }:$rsrc, i32:{ *:[i32] }:$vindex, i32:{ *:[i32] }:$voffset, (BUFSOffset:{ *:[i32] } i32:{ *:[i32] }:$soffset), (timm:{ *:[i32] }):$offset, (timm:{ *:[i32] }):$auxiliary, (timm:{ *:[i1] }))  =>  (BUFFER_STORE_DWORD_BOTHEN_exact anonymous_15037:{ *:[v2f16] }:$vdata, (REG_SEQUENCE:{ *:[i64] } VReg_64:{ *:[i32] }, VGPR_32:{ *:[i32] }:$vindex, sub0:{ *:[i32] }, VGPR_32:{ *:[i32] }:$voffset, sub1:{ *:[i32] }), SReg_128:{ *:[v4i32] }:$rsrc, SCSrc_b32:{ *:[i32] }:$soffset, (timm:{ *:[i32] }):$offset, (extract_cpol:{ *:[i32] } ?:{ *:[i32] }:$auxiliary), (extract_swz:{ *:[i1] } ?:{ *:[i32] }:$auxiliary))
        GIR_MakeTempReg, /*TempRegID*/0, /*TypeID*/GILLT_s64,
        GIR_BuildMI, /*InsnID*/1, /*Opcode*/GIMT_Encode2(TargetOpcode::REG_SEQUENCE),
        GIR_AddTempRegister, /*InsnID*/1, /*TempRegID*/0, /*TempRegFlags*/GIMT_Encode2(RegState::Define),
        GIR_Copy, /*NewInsnID*/1, /*OldInsnID*/0, /*OpIdx*/2, // vindex
        GIR_AddImm8, /*InsnID*/1, /*SubRegIndex*/3,
        GIR_Copy, /*NewInsnID*/1, /*OldInsnID*/0, /*OpIdx*/3, // voffset
        GIR_AddImm8, /*InsnID*/1, /*SubRegIndex*/11,
        GIR_ConstrainOperandRC, /*InsnID*/1, /*Op*/0, GIMT_Encode2(AMDGPU::VReg_64RegClassID),
        GIR_ConstrainOperandRC, /*InsnID*/1, /*Op*/1, GIMT_Encode2(AMDGPU::VGPR_32RegClassID),
        GIR_ConstrainOperandRC, /*InsnID*/1, /*Op*/3, GIMT_Encode2(AMDGPU::VGPR_32RegClassID),
        GIR_BuildMI, /*InsnID*/0, /*Opcode*/GIMT_Encode2(AMDGPU::BUFFER_STORE_DWORD_BOTHEN_exact),
        GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/0, // vdata
        GIR_AddSimpleTempRegister, /*InsnID*/0, /*TempRegID*/0,
        GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/1, // rsrc
        GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/0, // soffset
        GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/5, // offset
        GIR_CustomOperandRenderer, /*InsnID*/0, /*OldInsnID*/0, /*OpIdx*/6, /*OperandRenderer*/GIMT_Encode2(GICR_renderExtractCPol), // auxiliary
        GIR_CustomOperandRenderer, /*InsnID*/0, /*OldInsnID*/0, /*OpIdx*/6, /*OperandRenderer*/GIMT_Encode2(GICR_renderExtractSWZ), // auxiliary
        GIR_MergeMemOperands, /*InsnID*/0, /*NumInsns*/1, /*MergeInsnID's*/0,
        GIR_ConstrainSelectedInstOperands, /*InsnID*/0,
        GIR_EraseFromParent, /*InsnID*/0,
        // GIR_Coverage, 4420,
        GIR_Done,
      // Label 6812: @500060
      GIM_Try, /*On fail goto*//*Label 6813*/ GIMT_Encode4(500167), // Rule ID 4424 //
        // MIs[0] offset
        GIM_CheckIsImm, /*MI*/0, /*Op*/5,
        // MIs[0] auxiliary
        GIM_CheckIsImm, /*MI*/0, /*Op*/6,
        // MIs[0] Operand 7
        GIM_CheckIsImm, /*MI*/0, /*Op*/7,
        GIM_CheckComplexPattern, /*MI*/0, /*Op*/4, /*Renderer*/GIMT_Encode2(0), GIMT_Encode2(GICP_gi_buf_soffset),
        // (SIbuffer_store v2f16:{ *:[v2f16] }:$vdata, v4i32:{ *:[v4i32] }:$rsrc, i32:{ *:[i32] }:$vindex, i32:{ *:[i32] }:$voffset, (BUFSOffset:{ *:[i32] } i32:{ *:[i32] }:$soffset), (timm:{ *:[i32] }):$offset, (timm:{ *:[i32] }):$auxiliary, (timm:{ *:[i1] }))  =>  (BUFFER_STORE_DWORD_VBUFFER_BOTHEN_exact anonymous_15037:{ *:[v2f16] }:$vdata, (REG_SEQUENCE:{ *:[i64] } VReg_64:{ *:[i32] }, VGPR_32:{ *:[i32] }:$vindex, sub0:{ *:[i32] }, VGPR_32:{ *:[i32] }:$voffset, sub1:{ *:[i32] }), SReg_128:{ *:[v4i32] }:$rsrc, SCSrc_b32:{ *:[i32] }:$soffset, (timm:{ *:[i32] }):$offset, (extract_cpol:{ *:[i32] } ?:{ *:[i32] }:$auxiliary), (extract_swz:{ *:[i1] } ?:{ *:[i32] }:$auxiliary))
        GIR_MakeTempReg, /*TempRegID*/0, /*TypeID*/GILLT_s64,
        GIR_BuildMI, /*InsnID*/1, /*Opcode*/GIMT_Encode2(TargetOpcode::REG_SEQUENCE),
        GIR_AddTempRegister, /*InsnID*/1, /*TempRegID*/0, /*TempRegFlags*/GIMT_Encode2(RegState::Define),
        GIR_Copy, /*NewInsnID*/1, /*OldInsnID*/0, /*OpIdx*/2, // vindex
        GIR_AddImm8, /*InsnID*/1, /*SubRegIndex*/3,
        GIR_Copy, /*NewInsnID*/1, /*OldInsnID*/0, /*OpIdx*/3, // voffset
        GIR_AddImm8, /*InsnID*/1, /*SubRegIndex*/11,
        GIR_ConstrainOperandRC, /*InsnID*/1, /*Op*/0, GIMT_Encode2(AMDGPU::VReg_64RegClassID),
        GIR_ConstrainOperandRC, /*InsnID*/1, /*Op*/1, GIMT_Encode2(AMDGPU::VGPR_32RegClassID),
        GIR_ConstrainOperandRC, /*InsnID*/1, /*Op*/3, GIMT_Encode2(AMDGPU::VGPR_32RegClassID),
        GIR_BuildMI, /*InsnID*/0, /*Opcode*/GIMT_Encode2(AMDGPU::BUFFER_STORE_DWORD_VBUFFER_BOTHEN_exact),
        GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/0, // vdata
        GIR_AddSimpleTempRegister, /*InsnID*/0, /*TempRegID*/0,
        GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/1, // rsrc
        GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/0, // soffset
        GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/5, // offset
        GIR_CustomOperandRenderer, /*InsnID*/0, /*OldInsnID*/0, /*OpIdx*/6, /*OperandRenderer*/GIMT_Encode2(GICR_renderExtractCPol), // auxiliary
        GIR_CustomOperandRenderer, /*InsnID*/0, /*OldInsnID*/0, /*OpIdx*/6, /*OperandRenderer*/GIMT_Encode2(GICR_renderExtractSWZ), // auxiliary
        GIR_MergeMemOperands, /*InsnID*/0, /*NumInsns*/1, /*MergeInsnID's*/0,
        GIR_ConstrainSelectedInstOperands, /*InsnID*/0,
        GIR_EraseFromParent, /*InsnID*/0,
        // GIR_Coverage, 4424,
        GIR_Done,
      // Label 6813: @500167
      GIM_Reject,
    // Label 6797: @500168
    GIM_Reject,
    // Label 6775: @500169
    GIM_Try, /*On fail goto*//*Label 6814*/ GIMT_Encode4(501559),
      GIM_CheckType, /*MI*/0, /*Op*/1, /*Type*/GILLT_v4s32,
      GIM_CheckType, /*MI*/0, /*Op*/2, /*Type*/GILLT_s32,
      GIM_CheckType, /*MI*/0, /*Op*/3, /*Type*/GILLT_s32,
      GIM_CheckType, /*MI*/0, /*Op*/4, /*Type*/GILLT_s32,
      GIM_Try, /*On fail goto*//*Label 6815*/ GIMT_Encode4(500272), // Rule ID 4425 //
        GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasUnrestrictedSOffset),
        GIM_CheckConstantInt8, /*MI*/0, /*Op*/2, 0,
        GIM_CheckConstantInt8, /*MI*/0, /*Op*/3, 0,
        // MIs[0] offset
        GIM_CheckIsImm, /*MI*/0, /*Op*/5,
        // MIs[0] auxiliary
        GIM_CheckIsImm, /*MI*/0, /*Op*/6,
        // MIs[0] Operand 7
        GIM_CheckLiteralInt, /*MI*/0, /*Op*/7, GIMT_Encode8(0),
        GIM_CheckComplexPattern, /*MI*/0, /*Op*/4, /*Renderer*/GIMT_Encode2(0), GIMT_Encode2(GICP_gi_buf_soffset),
        // (SIbuffer_store v2f32:{ *:[v2f32] }:$vdata, v4i32:{ *:[v4i32] }:$rsrc, 0:{ *:[i32] }, 0:{ *:[i32] }, (BUFSOffset:{ *:[i32] } i32:{ *:[i32] }:$soffset), (timm:{ *:[i32] }):$offset, (timm:{ *:[i32] }):$auxiliary, 0:{ *:[i1] })  =>  (BUFFER_STORE_DWORDX2_OFFSET_exact anonymous_15036:{ *:[v2f32] }:$vdata, SReg_128:{ *:[v4i32] }:$rsrc, SCSrc_b32:{ *:[i32] }:$soffset, (timm:{ *:[i32] }):$offset, (extract_cpol:{ *:[i32] } ?:{ *:[i32] }:$auxiliary), (extract_swz:{ *:[i1] } ?:{ *:[i32] }:$auxiliary))
        GIR_BuildMI, /*InsnID*/0, /*Opcode*/GIMT_Encode2(AMDGPU::BUFFER_STORE_DWORDX2_OFFSET_exact),
        GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/0, // vdata
        GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/1, // rsrc
        GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/0, // soffset
        GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/5, // offset
        GIR_CustomOperandRenderer, /*InsnID*/0, /*OldInsnID*/0, /*OpIdx*/6, /*OperandRenderer*/GIMT_Encode2(GICR_renderExtractCPol), // auxiliary
        GIR_CustomOperandRenderer, /*InsnID*/0, /*OldInsnID*/0, /*OpIdx*/6, /*OperandRenderer*/GIMT_Encode2(GICR_renderExtractSWZ), // auxiliary
        GIR_MergeMemOperands, /*InsnID*/0, /*NumInsns*/1, /*MergeInsnID's*/0,
        GIR_ConstrainSelectedInstOperands, /*InsnID*/0,
        GIR_EraseFromParent, /*InsnID*/0,
        // GIR_Coverage, 4425,
        GIR_Done,
      // Label 6815: @500272
      GIM_Try, /*On fail goto*//*Label 6816*/ GIMT_Encode4(500351), // Rule ID 4429 //
        GIM_CheckConstantInt8, /*MI*/0, /*Op*/2, 0,
        GIM_CheckConstantInt8, /*MI*/0, /*Op*/3, 0,
        // MIs[0] offset
        GIM_CheckIsImm, /*MI*/0, /*Op*/5,
        // MIs[0] auxiliary
        GIM_CheckIsImm, /*MI*/0, /*Op*/6,
        // MIs[0] Operand 7
        GIM_CheckLiteralInt, /*MI*/0, /*Op*/7, GIMT_Encode8(0),
        GIM_CheckComplexPattern, /*MI*/0, /*Op*/4, /*Renderer*/GIMT_Encode2(0), GIMT_Encode2(GICP_gi_buf_soffset),
        // (SIbuffer_store v2f32:{ *:[v2f32] }:$vdata, v4i32:{ *:[v4i32] }:$rsrc, 0:{ *:[i32] }, 0:{ *:[i32] }, (BUFSOffset:{ *:[i32] } i32:{ *:[i32] }:$soffset), (timm:{ *:[i32] }):$offset, (timm:{ *:[i32] }):$auxiliary, 0:{ *:[i1] })  =>  (BUFFER_STORE_DWORDX2_VBUFFER_OFFSET_exact anonymous_15036:{ *:[v2f32] }:$vdata, SReg_128:{ *:[v4i32] }:$rsrc, SCSrc_b32:{ *:[i32] }:$soffset, (timm:{ *:[i32] }):$offset, (extract_cpol:{ *:[i32] } ?:{ *:[i32] }:$auxiliary), (extract_swz:{ *:[i1] } ?:{ *:[i32] }:$auxiliary))
        GIR_BuildMI, /*InsnID*/0, /*Opcode*/GIMT_Encode2(AMDGPU::BUFFER_STORE_DWORDX2_VBUFFER_OFFSET_exact),
        GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/0, // vdata
        GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/1, // rsrc
        GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/0, // soffset
        GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/5, // offset
        GIR_CustomOperandRenderer, /*InsnID*/0, /*OldInsnID*/0, /*OpIdx*/6, /*OperandRenderer*/GIMT_Encode2(GICR_renderExtractCPol), // auxiliary
        GIR_CustomOperandRenderer, /*InsnID*/0, /*OldInsnID*/0, /*OpIdx*/6, /*OperandRenderer*/GIMT_Encode2(GICR_renderExtractSWZ), // auxiliary
        GIR_MergeMemOperands, /*InsnID*/0, /*NumInsns*/1, /*MergeInsnID's*/0,
        GIR_ConstrainSelectedInstOperands, /*InsnID*/0,
        GIR_EraseFromParent, /*InsnID*/0,
        // GIR_Coverage, 4429,
        GIR_Done,
      // Label 6816: @500351
      GIM_Try, /*On fail goto*//*Label 6817*/ GIMT_Encode4(500433), // Rule ID 4433 //
        GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasUnrestrictedSOffset),
        GIM_CheckConstantInt8, /*MI*/0, /*Op*/2, 0,
        GIM_CheckConstantInt8, /*MI*/0, /*Op*/3, 0,
        // MIs[0] offset
        GIM_CheckIsImm, /*MI*/0, /*Op*/5,
        // MIs[0] auxiliary
        GIM_CheckIsImm, /*MI*/0, /*Op*/6,
        // MIs[0] Operand 7
        GIM_CheckLiteralInt, /*MI*/0, /*Op*/7, GIMT_Encode8(0),
        GIM_CheckComplexPattern, /*MI*/0, /*Op*/4, /*Renderer*/GIMT_Encode2(0), GIMT_Encode2(GICP_gi_buf_soffset),
        // (SIbuffer_store v2i32:{ *:[v2i32] }:$vdata, v4i32:{ *:[v4i32] }:$rsrc, 0:{ *:[i32] }, 0:{ *:[i32] }, (BUFSOffset:{ *:[i32] } i32:{ *:[i32] }:$soffset), (timm:{ *:[i32] }):$offset, (timm:{ *:[i32] }):$auxiliary, 0:{ *:[i1] })  =>  (BUFFER_STORE_DWORDX2_OFFSET_exact anonymous_15036:{ *:[v2i32] }:$vdata, SReg_128:{ *:[v4i32] }:$rsrc, SCSrc_b32:{ *:[i32] }:$soffset, (timm:{ *:[i32] }):$offset, (extract_cpol:{ *:[i32] } ?:{ *:[i32] }:$auxiliary), (extract_swz:{ *:[i1] } ?:{ *:[i32] }:$auxiliary))
        GIR_BuildMI, /*InsnID*/0, /*Opcode*/GIMT_Encode2(AMDGPU::BUFFER_STORE_DWORDX2_OFFSET_exact),
        GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/0, // vdata
        GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/1, // rsrc
        GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/0, // soffset
        GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/5, // offset
        GIR_CustomOperandRenderer, /*InsnID*/0, /*OldInsnID*/0, /*OpIdx*/6, /*OperandRenderer*/GIMT_Encode2(GICR_renderExtractCPol), // auxiliary
        GIR_CustomOperandRenderer, /*InsnID*/0, /*OldInsnID*/0, /*OpIdx*/6, /*OperandRenderer*/GIMT_Encode2(GICR_renderExtractSWZ), // auxiliary
        GIR_MergeMemOperands, /*InsnID*/0, /*NumInsns*/1, /*MergeInsnID's*/0,
        GIR_ConstrainSelectedInstOperands, /*InsnID*/0,
        GIR_EraseFromParent, /*InsnID*/0,
        // GIR_Coverage, 4433,
        GIR_Done,
      // Label 6817: @500433
      GIM_Try, /*On fail goto*//*Label 6818*/ GIMT_Encode4(500512), // Rule ID 4437 //
        GIM_CheckConstantInt8, /*MI*/0, /*Op*/2, 0,
        GIM_CheckConstantInt8, /*MI*/0, /*Op*/3, 0,
        // MIs[0] offset
        GIM_CheckIsImm, /*MI*/0, /*Op*/5,
        // MIs[0] auxiliary
        GIM_CheckIsImm, /*MI*/0, /*Op*/6,
        // MIs[0] Operand 7
        GIM_CheckLiteralInt, /*MI*/0, /*Op*/7, GIMT_Encode8(0),
        GIM_CheckComplexPattern, /*MI*/0, /*Op*/4, /*Renderer*/GIMT_Encode2(0), GIMT_Encode2(GICP_gi_buf_soffset),
        // (SIbuffer_store v2i32:{ *:[v2i32] }:$vdata, v4i32:{ *:[v4i32] }:$rsrc, 0:{ *:[i32] }, 0:{ *:[i32] }, (BUFSOffset:{ *:[i32] } i32:{ *:[i32] }:$soffset), (timm:{ *:[i32] }):$offset, (timm:{ *:[i32] }):$auxiliary, 0:{ *:[i1] })  =>  (BUFFER_STORE_DWORDX2_VBUFFER_OFFSET_exact anonymous_15036:{ *:[v2i32] }:$vdata, SReg_128:{ *:[v4i32] }:$rsrc, SCSrc_b32:{ *:[i32] }:$soffset, (timm:{ *:[i32] }):$offset, (extract_cpol:{ *:[i32] } ?:{ *:[i32] }:$auxiliary), (extract_swz:{ *:[i1] } ?:{ *:[i32] }:$auxiliary))
        GIR_BuildMI, /*InsnID*/0, /*Opcode*/GIMT_Encode2(AMDGPU::BUFFER_STORE_DWORDX2_VBUFFER_OFFSET_exact),
        GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/0, // vdata
        GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/1, // rsrc
        GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/0, // soffset
        GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/5, // offset
        GIR_CustomOperandRenderer, /*InsnID*/0, /*OldInsnID*/0, /*OpIdx*/6, /*OperandRenderer*/GIMT_Encode2(GICR_renderExtractCPol), // auxiliary
        GIR_CustomOperandRenderer, /*InsnID*/0, /*OldInsnID*/0, /*OpIdx*/6, /*OperandRenderer*/GIMT_Encode2(GICR_renderExtractSWZ), // auxiliary
        GIR_MergeMemOperands, /*InsnID*/0, /*NumInsns*/1, /*MergeInsnID's*/0,
        GIR_ConstrainSelectedInstOperands, /*InsnID*/0,
        GIR_EraseFromParent, /*InsnID*/0,
        // GIR_Coverage, 4437,
        GIR_Done,
      // Label 6818: @500512
      GIM_Try, /*On fail goto*//*Label 6819*/ GIMT_Encode4(500594), // Rule ID 4426 //
        GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasUnrestrictedSOffset),
        GIM_CheckConstantInt8, /*MI*/0, /*Op*/2, 0,
        // MIs[0] offset
        GIM_CheckIsImm, /*MI*/0, /*Op*/5,
        // MIs[0] auxiliary
        GIM_CheckIsImm, /*MI*/0, /*Op*/6,
        // MIs[0] Operand 7
        GIM_CheckLiteralInt, /*MI*/0, /*Op*/7, GIMT_Encode8(0),
        GIM_CheckComplexPattern, /*MI*/0, /*Op*/4, /*Renderer*/GIMT_Encode2(0), GIMT_Encode2(GICP_gi_buf_soffset),
        // (SIbuffer_store v2f32:{ *:[v2f32] }:$vdata, v4i32:{ *:[v4i32] }:$rsrc, 0:{ *:[i32] }, i32:{ *:[i32] }:$voffset, (BUFSOffset:{ *:[i32] } i32:{ *:[i32] }:$soffset), (timm:{ *:[i32] }):$offset, (timm:{ *:[i32] }):$auxiliary, 0:{ *:[i1] })  =>  (BUFFER_STORE_DWORDX2_OFFEN_exact anonymous_15036:{ *:[v2f32] }:$vdata, VGPR_32:{ *:[i32] }:$voffset, SReg_128:{ *:[v4i32] }:$rsrc, SCSrc_b32:{ *:[i32] }:$soffset, (timm:{ *:[i32] }):$offset, (extract_cpol:{ *:[i32] } ?:{ *:[i32] }:$auxiliary), (extract_swz:{ *:[i1] } ?:{ *:[i32] }:$auxiliary))
        GIR_BuildMI, /*InsnID*/0, /*Opcode*/GIMT_Encode2(AMDGPU::BUFFER_STORE_DWORDX2_OFFEN_exact),
        GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/0, // vdata
        GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/3, // voffset
        GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/1, // rsrc
        GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/0, // soffset
        GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/5, // offset
        GIR_CustomOperandRenderer, /*InsnID*/0, /*OldInsnID*/0, /*OpIdx*/6, /*OperandRenderer*/GIMT_Encode2(GICR_renderExtractCPol), // auxiliary
        GIR_CustomOperandRenderer, /*InsnID*/0, /*OldInsnID*/0, /*OpIdx*/6, /*OperandRenderer*/GIMT_Encode2(GICR_renderExtractSWZ), // auxiliary
        GIR_MergeMemOperands, /*InsnID*/0, /*NumInsns*/1, /*MergeInsnID's*/0,
        GIR_ConstrainSelectedInstOperands, /*InsnID*/0,
        GIR_EraseFromParent, /*InsnID*/0,
        // GIR_Coverage, 4426,
        GIR_Done,
      // Label 6819: @500594
      GIM_Try, /*On fail goto*//*Label 6820*/ GIMT_Encode4(500673), // Rule ID 4430 //
        GIM_CheckConstantInt8, /*MI*/0, /*Op*/2, 0,
        // MIs[0] offset
        GIM_CheckIsImm, /*MI*/0, /*Op*/5,
        // MIs[0] auxiliary
        GIM_CheckIsImm, /*MI*/0, /*Op*/6,
        // MIs[0] Operand 7
        GIM_CheckLiteralInt, /*MI*/0, /*Op*/7, GIMT_Encode8(0),
        GIM_CheckComplexPattern, /*MI*/0, /*Op*/4, /*Renderer*/GIMT_Encode2(0), GIMT_Encode2(GICP_gi_buf_soffset),
        // (SIbuffer_store v2f32:{ *:[v2f32] }:$vdata, v4i32:{ *:[v4i32] }:$rsrc, 0:{ *:[i32] }, i32:{ *:[i32] }:$voffset, (BUFSOffset:{ *:[i32] } i32:{ *:[i32] }:$soffset), (timm:{ *:[i32] }):$offset, (timm:{ *:[i32] }):$auxiliary, 0:{ *:[i1] })  =>  (BUFFER_STORE_DWORDX2_VBUFFER_OFFEN_exact anonymous_15036:{ *:[v2f32] }:$vdata, VGPR_32:{ *:[i32] }:$voffset, SReg_128:{ *:[v4i32] }:$rsrc, SCSrc_b32:{ *:[i32] }:$soffset, (timm:{ *:[i32] }):$offset, (extract_cpol:{ *:[i32] } ?:{ *:[i32] }:$auxiliary), (extract_swz:{ *:[i1] } ?:{ *:[i32] }:$auxiliary))
        GIR_BuildMI, /*InsnID*/0, /*Opcode*/GIMT_Encode2(AMDGPU::BUFFER_STORE_DWORDX2_VBUFFER_OFFEN_exact),
        GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/0, // vdata
        GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/3, // voffset
        GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/1, // rsrc
        GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/0, // soffset
        GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/5, // offset
        GIR_CustomOperandRenderer, /*InsnID*/0, /*OldInsnID*/0, /*OpIdx*/6, /*OperandRenderer*/GIMT_Encode2(GICR_renderExtractCPol), // auxiliary
        GIR_CustomOperandRenderer, /*InsnID*/0, /*OldInsnID*/0, /*OpIdx*/6, /*OperandRenderer*/GIMT_Encode2(GICR_renderExtractSWZ), // auxiliary
        GIR_MergeMemOperands, /*InsnID*/0, /*NumInsns*/1, /*MergeInsnID's*/0,
        GIR_ConstrainSelectedInstOperands, /*InsnID*/0,
        GIR_EraseFromParent, /*InsnID*/0,
        // GIR_Coverage, 4430,
        GIR_Done,
      // Label 6820: @500673
      GIM_Try, /*On fail goto*//*Label 6821*/ GIMT_Encode4(500755), // Rule ID 4434 //
        GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasUnrestrictedSOffset),
        GIM_CheckConstantInt8, /*MI*/0, /*Op*/2, 0,
        // MIs[0] offset
        GIM_CheckIsImm, /*MI*/0, /*Op*/5,
        // MIs[0] auxiliary
        GIM_CheckIsImm, /*MI*/0, /*Op*/6,
        // MIs[0] Operand 7
        GIM_CheckLiteralInt, /*MI*/0, /*Op*/7, GIMT_Encode8(0),
        GIM_CheckComplexPattern, /*MI*/0, /*Op*/4, /*Renderer*/GIMT_Encode2(0), GIMT_Encode2(GICP_gi_buf_soffset),
        // (SIbuffer_store v2i32:{ *:[v2i32] }:$vdata, v4i32:{ *:[v4i32] }:$rsrc, 0:{ *:[i32] }, i32:{ *:[i32] }:$voffset, (BUFSOffset:{ *:[i32] } i32:{ *:[i32] }:$soffset), (timm:{ *:[i32] }):$offset, (timm:{ *:[i32] }):$auxiliary, 0:{ *:[i1] })  =>  (BUFFER_STORE_DWORDX2_OFFEN_exact anonymous_15036:{ *:[v2i32] }:$vdata, VGPR_32:{ *:[i32] }:$voffset, SReg_128:{ *:[v4i32] }:$rsrc, SCSrc_b32:{ *:[i32] }:$soffset, (timm:{ *:[i32] }):$offset, (extract_cpol:{ *:[i32] } ?:{ *:[i32] }:$auxiliary), (extract_swz:{ *:[i1] } ?:{ *:[i32] }:$auxiliary))
        GIR_BuildMI, /*InsnID*/0, /*Opcode*/GIMT_Encode2(AMDGPU::BUFFER_STORE_DWORDX2_OFFEN_exact),
        GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/0, // vdata
        GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/3, // voffset
        GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/1, // rsrc
        GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/0, // soffset
        GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/5, // offset
        GIR_CustomOperandRenderer, /*InsnID*/0, /*OldInsnID*/0, /*OpIdx*/6, /*OperandRenderer*/GIMT_Encode2(GICR_renderExtractCPol), // auxiliary
        GIR_CustomOperandRenderer, /*InsnID*/0, /*OldInsnID*/0, /*OpIdx*/6, /*OperandRenderer*/GIMT_Encode2(GICR_renderExtractSWZ), // auxiliary
        GIR_MergeMemOperands, /*InsnID*/0, /*NumInsns*/1, /*MergeInsnID's*/0,
        GIR_ConstrainSelectedInstOperands, /*InsnID*/0,
        GIR_EraseFromParent, /*InsnID*/0,
        // GIR_Coverage, 4434,
        GIR_Done,
      // Label 6821: @500755
      GIM_Try, /*On fail goto*//*Label 6822*/ GIMT_Encode4(500834), // Rule ID 4438 //
        GIM_CheckConstantInt8, /*MI*/0, /*Op*/2, 0,
        // MIs[0] offset
        GIM_CheckIsImm, /*MI*/0, /*Op*/5,
        // MIs[0] auxiliary
        GIM_CheckIsImm, /*MI*/0, /*Op*/6,
        // MIs[0] Operand 7
        GIM_CheckLiteralInt, /*MI*/0, /*Op*/7, GIMT_Encode8(0),
        GIM_CheckComplexPattern, /*MI*/0, /*Op*/4, /*Renderer*/GIMT_Encode2(0), GIMT_Encode2(GICP_gi_buf_soffset),
        // (SIbuffer_store v2i32:{ *:[v2i32] }:$vdata, v4i32:{ *:[v4i32] }:$rsrc, 0:{ *:[i32] }, i32:{ *:[i32] }:$voffset, (BUFSOffset:{ *:[i32] } i32:{ *:[i32] }:$soffset), (timm:{ *:[i32] }):$offset, (timm:{ *:[i32] }):$auxiliary, 0:{ *:[i1] })  =>  (BUFFER_STORE_DWORDX2_VBUFFER_OFFEN_exact anonymous_15036:{ *:[v2i32] }:$vdata, VGPR_32:{ *:[i32] }:$voffset, SReg_128:{ *:[v4i32] }:$rsrc, SCSrc_b32:{ *:[i32] }:$soffset, (timm:{ *:[i32] }):$offset, (extract_cpol:{ *:[i32] } ?:{ *:[i32] }:$auxiliary), (extract_swz:{ *:[i1] } ?:{ *:[i32] }:$auxiliary))
        GIR_BuildMI, /*InsnID*/0, /*Opcode*/GIMT_Encode2(AMDGPU::BUFFER_STORE_DWORDX2_VBUFFER_OFFEN_exact),
        GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/0, // vdata
        GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/3, // voffset
        GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/1, // rsrc
        GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/0, // soffset
        GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/5, // offset
        GIR_CustomOperandRenderer, /*InsnID*/0, /*OldInsnID*/0, /*OpIdx*/6, /*OperandRenderer*/GIMT_Encode2(GICR_renderExtractCPol), // auxiliary
        GIR_CustomOperandRenderer, /*InsnID*/0, /*OldInsnID*/0, /*OpIdx*/6, /*OperandRenderer*/GIMT_Encode2(GICR_renderExtractSWZ), // auxiliary
        GIR_MergeMemOperands, /*InsnID*/0, /*NumInsns*/1, /*MergeInsnID's*/0,
        GIR_ConstrainSelectedInstOperands, /*InsnID*/0,
        GIR_EraseFromParent, /*InsnID*/0,
        // GIR_Coverage, 4438,
        GIR_Done,
      // Label 6822: @500834
      GIM_Try, /*On fail goto*//*Label 6823*/ GIMT_Encode4(500908), // Rule ID 4427 //
        GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasUnrestrictedSOffset),
        GIM_CheckConstantInt8, /*MI*/0, /*Op*/3, 0,
        // MIs[0] offset
        GIM_CheckIsImm, /*MI*/0, /*Op*/5,
        // MIs[0] auxiliary
        GIM_CheckIsImm, /*MI*/0, /*Op*/6,
        // MIs[0] Operand 7
        GIM_CheckIsImm, /*MI*/0, /*Op*/7,
        GIM_CheckComplexPattern, /*MI*/0, /*Op*/4, /*Renderer*/GIMT_Encode2(0), GIMT_Encode2(GICP_gi_buf_soffset),
        // (SIbuffer_store v2f32:{ *:[v2f32] }:$vdata, v4i32:{ *:[v4i32] }:$rsrc, i32:{ *:[i32] }:$vindex, 0:{ *:[i32] }, (BUFSOffset:{ *:[i32] } i32:{ *:[i32] }:$soffset), (timm:{ *:[i32] }):$offset, (timm:{ *:[i32] }):$auxiliary, (timm:{ *:[i1] }))  =>  (BUFFER_STORE_DWORDX2_IDXEN_exact anonymous_15036:{ *:[v2f32] }:$vdata, VGPR_32:{ *:[i32] }:$vindex, SReg_128:{ *:[v4i32] }:$rsrc, SCSrc_b32:{ *:[i32] }:$soffset, (timm:{ *:[i32] }):$offset, (extract_cpol:{ *:[i32] } ?:{ *:[i32] }:$auxiliary), (extract_swz:{ *:[i1] } ?:{ *:[i32] }:$auxiliary))
        GIR_BuildMI, /*InsnID*/0, /*Opcode*/GIMT_Encode2(AMDGPU::BUFFER_STORE_DWORDX2_IDXEN_exact),
        GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/0, // vdata
        GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/2, // vindex
        GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/1, // rsrc
        GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/0, // soffset
        GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/5, // offset
        GIR_CustomOperandRenderer, /*InsnID*/0, /*OldInsnID*/0, /*OpIdx*/6, /*OperandRenderer*/GIMT_Encode2(GICR_renderExtractCPol), // auxiliary
        GIR_CustomOperandRenderer, /*InsnID*/0, /*OldInsnID*/0, /*OpIdx*/6, /*OperandRenderer*/GIMT_Encode2(GICR_renderExtractSWZ), // auxiliary
        GIR_MergeMemOperands, /*InsnID*/0, /*NumInsns*/1, /*MergeInsnID's*/0,
        GIR_ConstrainSelectedInstOperands, /*InsnID*/0,
        GIR_EraseFromParent, /*InsnID*/0,
        // GIR_Coverage, 4427,
        GIR_Done,
      // Label 6823: @500908
      GIM_Try, /*On fail goto*//*Label 6824*/ GIMT_Encode4(500979), // Rule ID 4431 //
        GIM_CheckConstantInt8, /*MI*/0, /*Op*/3, 0,
        // MIs[0] offset
        GIM_CheckIsImm, /*MI*/0, /*Op*/5,
        // MIs[0] auxiliary
        GIM_CheckIsImm, /*MI*/0, /*Op*/6,
        // MIs[0] Operand 7
        GIM_CheckIsImm, /*MI*/0, /*Op*/7,
        GIM_CheckComplexPattern, /*MI*/0, /*Op*/4, /*Renderer*/GIMT_Encode2(0), GIMT_Encode2(GICP_gi_buf_soffset),
        // (SIbuffer_store v2f32:{ *:[v2f32] }:$vdata, v4i32:{ *:[v4i32] }:$rsrc, i32:{ *:[i32] }:$vindex, 0:{ *:[i32] }, (BUFSOffset:{ *:[i32] } i32:{ *:[i32] }:$soffset), (timm:{ *:[i32] }):$offset, (timm:{ *:[i32] }):$auxiliary, (timm:{ *:[i1] }))  =>  (BUFFER_STORE_DWORDX2_VBUFFER_IDXEN_exact anonymous_15036:{ *:[v2f32] }:$vdata, VGPR_32:{ *:[i32] }:$vindex, SReg_128:{ *:[v4i32] }:$rsrc, SCSrc_b32:{ *:[i32] }:$soffset, (timm:{ *:[i32] }):$offset, (extract_cpol:{ *:[i32] } ?:{ *:[i32] }:$auxiliary), (extract_swz:{ *:[i1] } ?:{ *:[i32] }:$auxiliary))
        GIR_BuildMI, /*InsnID*/0, /*Opcode*/GIMT_Encode2(AMDGPU::BUFFER_STORE_DWORDX2_VBUFFER_IDXEN_exact),
        GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/0, // vdata
        GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/2, // vindex
        GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/1, // rsrc
        GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/0, // soffset
        GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/5, // offset
        GIR_CustomOperandRenderer, /*InsnID*/0, /*OldInsnID*/0, /*OpIdx*/6, /*OperandRenderer*/GIMT_Encode2(GICR_renderExtractCPol), // auxiliary
        GIR_CustomOperandRenderer, /*InsnID*/0, /*OldInsnID*/0, /*OpIdx*/6, /*OperandRenderer*/GIMT_Encode2(GICR_renderExtractSWZ), // auxiliary
        GIR_MergeMemOperands, /*InsnID*/0, /*NumInsns*/1, /*MergeInsnID's*/0,
        GIR_ConstrainSelectedInstOperands, /*InsnID*/0,
        GIR_EraseFromParent, /*InsnID*/0,
        // GIR_Coverage, 4431,
        GIR_Done,
      // Label 6824: @500979
      GIM_Try, /*On fail goto*//*Label 6825*/ GIMT_Encode4(501053), // Rule ID 4435 //
        GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasUnrestrictedSOffset),
        GIM_CheckConstantInt8, /*MI*/0, /*Op*/3, 0,
        // MIs[0] offset
        GIM_CheckIsImm, /*MI*/0, /*Op*/5,
        // MIs[0] auxiliary
        GIM_CheckIsImm, /*MI*/0, /*Op*/6,
        // MIs[0] Operand 7
        GIM_CheckIsImm, /*MI*/0, /*Op*/7,
        GIM_CheckComplexPattern, /*MI*/0, /*Op*/4, /*Renderer*/GIMT_Encode2(0), GIMT_Encode2(GICP_gi_buf_soffset),
        // (SIbuffer_store v2i32:{ *:[v2i32] }:$vdata, v4i32:{ *:[v4i32] }:$rsrc, i32:{ *:[i32] }:$vindex, 0:{ *:[i32] }, (BUFSOffset:{ *:[i32] } i32:{ *:[i32] }:$soffset), (timm:{ *:[i32] }):$offset, (timm:{ *:[i32] }):$auxiliary, (timm:{ *:[i1] }))  =>  (BUFFER_STORE_DWORDX2_IDXEN_exact anonymous_15036:{ *:[v2i32] }:$vdata, VGPR_32:{ *:[i32] }:$vindex, SReg_128:{ *:[v4i32] }:$rsrc, SCSrc_b32:{ *:[i32] }:$soffset, (timm:{ *:[i32] }):$offset, (extract_cpol:{ *:[i32] } ?:{ *:[i32] }:$auxiliary), (extract_swz:{ *:[i1] } ?:{ *:[i32] }:$auxiliary))
        GIR_BuildMI, /*InsnID*/0, /*Opcode*/GIMT_Encode2(AMDGPU::BUFFER_STORE_DWORDX2_IDXEN_exact),
        GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/0, // vdata
        GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/2, // vindex
        GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/1, // rsrc
        GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/0, // soffset
        GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/5, // offset
        GIR_CustomOperandRenderer, /*InsnID*/0, /*OldInsnID*/0, /*OpIdx*/6, /*OperandRenderer*/GIMT_Encode2(GICR_renderExtractCPol), // auxiliary
        GIR_CustomOperandRenderer, /*InsnID*/0, /*OldInsnID*/0, /*OpIdx*/6, /*OperandRenderer*/GIMT_Encode2(GICR_renderExtractSWZ), // auxiliary
        GIR_MergeMemOperands, /*InsnID*/0, /*NumInsns*/1, /*MergeInsnID's*/0,
        GIR_ConstrainSelectedInstOperands, /*InsnID*/0,
        GIR_EraseFromParent, /*InsnID*/0,
        // GIR_Coverage, 4435,
        GIR_Done,
      // Label 6825: @501053
      GIM_Try, /*On fail goto*//*Label 6826*/ GIMT_Encode4(501124), // Rule ID 4439 //
        GIM_CheckConstantInt8, /*MI*/0, /*Op*/3, 0,
        // MIs[0] offset
        GIM_CheckIsImm, /*MI*/0, /*Op*/5,
        // MIs[0] auxiliary
        GIM_CheckIsImm, /*MI*/0, /*Op*/6,
        // MIs[0] Operand 7
        GIM_CheckIsImm, /*MI*/0, /*Op*/7,
        GIM_CheckComplexPattern, /*MI*/0, /*Op*/4, /*Renderer*/GIMT_Encode2(0), GIMT_Encode2(GICP_gi_buf_soffset),
        // (SIbuffer_store v2i32:{ *:[v2i32] }:$vdata, v4i32:{ *:[v4i32] }:$rsrc, i32:{ *:[i32] }:$vindex, 0:{ *:[i32] }, (BUFSOffset:{ *:[i32] } i32:{ *:[i32] }:$soffset), (timm:{ *:[i32] }):$offset, (timm:{ *:[i32] }):$auxiliary, (timm:{ *:[i1] }))  =>  (BUFFER_STORE_DWORDX2_VBUFFER_IDXEN_exact anonymous_15036:{ *:[v2i32] }:$vdata, VGPR_32:{ *:[i32] }:$vindex, SReg_128:{ *:[v4i32] }:$rsrc, SCSrc_b32:{ *:[i32] }:$soffset, (timm:{ *:[i32] }):$offset, (extract_cpol:{ *:[i32] } ?:{ *:[i32] }:$auxiliary), (extract_swz:{ *:[i1] } ?:{ *:[i32] }:$auxiliary))
        GIR_BuildMI, /*InsnID*/0, /*Opcode*/GIMT_Encode2(AMDGPU::BUFFER_STORE_DWORDX2_VBUFFER_IDXEN_exact),
        GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/0, // vdata
        GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/2, // vindex
        GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/1, // rsrc
        GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/0, // soffset
        GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/5, // offset
        GIR_CustomOperandRenderer, /*InsnID*/0, /*OldInsnID*/0, /*OpIdx*/6, /*OperandRenderer*/GIMT_Encode2(GICR_renderExtractCPol), // auxiliary
        GIR_CustomOperandRenderer, /*InsnID*/0, /*OldInsnID*/0, /*OpIdx*/6, /*OperandRenderer*/GIMT_Encode2(GICR_renderExtractSWZ), // auxiliary
        GIR_MergeMemOperands, /*InsnID*/0, /*NumInsns*/1, /*MergeInsnID's*/0,
        GIR_ConstrainSelectedInstOperands, /*InsnID*/0,
        GIR_EraseFromParent, /*InsnID*/0,
        // GIR_Coverage, 4439,
        GIR_Done,
      // Label 6826: @501124
      GIM_Try, /*On fail goto*//*Label 6827*/ GIMT_Encode4(501234), // Rule ID 4428 //
        GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasUnrestrictedSOffset),
        // MIs[0] offset
        GIM_CheckIsImm, /*MI*/0, /*Op*/5,
        // MIs[0] auxiliary
        GIM_CheckIsImm, /*MI*/0, /*Op*/6,
        // MIs[0] Operand 7
        GIM_CheckIsImm, /*MI*/0, /*Op*/7,
        GIM_CheckComplexPattern, /*MI*/0, /*Op*/4, /*Renderer*/GIMT_Encode2(0), GIMT_Encode2(GICP_gi_buf_soffset),
        // (SIbuffer_store v2f32:{ *:[v2f32] }:$vdata, v4i32:{ *:[v4i32] }:$rsrc, i32:{ *:[i32] }:$vindex, i32:{ *:[i32] }:$voffset, (BUFSOffset:{ *:[i32] } i32:{ *:[i32] }:$soffset), (timm:{ *:[i32] }):$offset, (timm:{ *:[i32] }):$auxiliary, (timm:{ *:[i1] }))  =>  (BUFFER_STORE_DWORDX2_BOTHEN_exact anonymous_15036:{ *:[v2f32] }:$vdata, (REG_SEQUENCE:{ *:[i64] } VReg_64:{ *:[i32] }, VGPR_32:{ *:[i32] }:$vindex, sub0:{ *:[i32] }, VGPR_32:{ *:[i32] }:$voffset, sub1:{ *:[i32] }), SReg_128:{ *:[v4i32] }:$rsrc, SCSrc_b32:{ *:[i32] }:$soffset, (timm:{ *:[i32] }):$offset, (extract_cpol:{ *:[i32] } ?:{ *:[i32] }:$auxiliary), (extract_swz:{ *:[i1] } ?:{ *:[i32] }:$auxiliary))
        GIR_MakeTempReg, /*TempRegID*/0, /*TypeID*/GILLT_s64,
        GIR_BuildMI, /*InsnID*/1, /*Opcode*/GIMT_Encode2(TargetOpcode::REG_SEQUENCE),
        GIR_AddTempRegister, /*InsnID*/1, /*TempRegID*/0, /*TempRegFlags*/GIMT_Encode2(RegState::Define),
        GIR_Copy, /*NewInsnID*/1, /*OldInsnID*/0, /*OpIdx*/2, // vindex
        GIR_AddImm8, /*InsnID*/1, /*SubRegIndex*/3,
        GIR_Copy, /*NewInsnID*/1, /*OldInsnID*/0, /*OpIdx*/3, // voffset
        GIR_AddImm8, /*InsnID*/1, /*SubRegIndex*/11,
        GIR_ConstrainOperandRC, /*InsnID*/1, /*Op*/0, GIMT_Encode2(AMDGPU::VReg_64RegClassID),
        GIR_ConstrainOperandRC, /*InsnID*/1, /*Op*/1, GIMT_Encode2(AMDGPU::VGPR_32RegClassID),
        GIR_ConstrainOperandRC, /*InsnID*/1, /*Op*/3, GIMT_Encode2(AMDGPU::VGPR_32RegClassID),
        GIR_BuildMI, /*InsnID*/0, /*Opcode*/GIMT_Encode2(AMDGPU::BUFFER_STORE_DWORDX2_BOTHEN_exact),
        GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/0, // vdata
        GIR_AddSimpleTempRegister, /*InsnID*/0, /*TempRegID*/0,
        GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/1, // rsrc
        GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/0, // soffset
        GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/5, // offset
        GIR_CustomOperandRenderer, /*InsnID*/0, /*OldInsnID*/0, /*OpIdx*/6, /*OperandRenderer*/GIMT_Encode2(GICR_renderExtractCPol), // auxiliary
        GIR_CustomOperandRenderer, /*InsnID*/0, /*OldInsnID*/0, /*OpIdx*/6, /*OperandRenderer*/GIMT_Encode2(GICR_renderExtractSWZ), // auxiliary
        GIR_MergeMemOperands, /*InsnID*/0, /*NumInsns*/1, /*MergeInsnID's*/0,
        GIR_ConstrainSelectedInstOperands, /*InsnID*/0,
        GIR_EraseFromParent, /*InsnID*/0,
        // GIR_Coverage, 4428,
        GIR_Done,
      // Label 6827: @501234
      GIM_Try, /*On fail goto*//*Label 6828*/ GIMT_Encode4(501341), // Rule ID 4432 //
        // MIs[0] offset
        GIM_CheckIsImm, /*MI*/0, /*Op*/5,
        // MIs[0] auxiliary
        GIM_CheckIsImm, /*MI*/0, /*Op*/6,
        // MIs[0] Operand 7
        GIM_CheckIsImm, /*MI*/0, /*Op*/7,
        GIM_CheckComplexPattern, /*MI*/0, /*Op*/4, /*Renderer*/GIMT_Encode2(0), GIMT_Encode2(GICP_gi_buf_soffset),
        // (SIbuffer_store v2f32:{ *:[v2f32] }:$vdata, v4i32:{ *:[v4i32] }:$rsrc, i32:{ *:[i32] }:$vindex, i32:{ *:[i32] }:$voffset, (BUFSOffset:{ *:[i32] } i32:{ *:[i32] }:$soffset), (timm:{ *:[i32] }):$offset, (timm:{ *:[i32] }):$auxiliary, (timm:{ *:[i1] }))  =>  (BUFFER_STORE_DWORDX2_VBUFFER_BOTHEN_exact anonymous_15036:{ *:[v2f32] }:$vdata, (REG_SEQUENCE:{ *:[i64] } VReg_64:{ *:[i32] }, VGPR_32:{ *:[i32] }:$vindex, sub0:{ *:[i32] }, VGPR_32:{ *:[i32] }:$voffset, sub1:{ *:[i32] }), SReg_128:{ *:[v4i32] }:$rsrc, SCSrc_b32:{ *:[i32] }:$soffset, (timm:{ *:[i32] }):$offset, (extract_cpol:{ *:[i32] } ?:{ *:[i32] }:$auxiliary), (extract_swz:{ *:[i1] } ?:{ *:[i32] }:$auxiliary))
        GIR_MakeTempReg, /*TempRegID*/0, /*TypeID*/GILLT_s64,
        GIR_BuildMI, /*InsnID*/1, /*Opcode*/GIMT_Encode2(TargetOpcode::REG_SEQUENCE),
        GIR_AddTempRegister, /*InsnID*/1, /*TempRegID*/0, /*TempRegFlags*/GIMT_Encode2(RegState::Define),
        GIR_Copy, /*NewInsnID*/1, /*OldInsnID*/0, /*OpIdx*/2, // vindex
        GIR_AddImm8, /*InsnID*/1, /*SubRegIndex*/3,
        GIR_Copy, /*NewInsnID*/1, /*OldInsnID*/0, /*OpIdx*/3, // voffset
        GIR_AddImm8, /*InsnID*/1, /*SubRegIndex*/11,
        GIR_ConstrainOperandRC, /*InsnID*/1, /*Op*/0, GIMT_Encode2(AMDGPU::VReg_64RegClassID),
        GIR_ConstrainOperandRC, /*InsnID*/1, /*Op*/1, GIMT_Encode2(AMDGPU::VGPR_32RegClassID),
        GIR_ConstrainOperandRC, /*InsnID*/1, /*Op*/3, GIMT_Encode2(AMDGPU::VGPR_32RegClassID),
        GIR_BuildMI, /*InsnID*/0, /*Opcode*/GIMT_Encode2(AMDGPU::BUFFER_STORE_DWORDX2_VBUFFER_BOTHEN_exact),
        GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/0, // vdata
        GIR_AddSimpleTempRegister, /*InsnID*/0, /*TempRegID*/0,
        GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/1, // rsrc
        GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/0, // soffset
        GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/5, // offset
        GIR_CustomOperandRenderer, /*InsnID*/0, /*OldInsnID*/0, /*OpIdx*/6, /*OperandRenderer*/GIMT_Encode2(GICR_renderExtractCPol), // auxiliary
        GIR_CustomOperandRenderer, /*InsnID*/0, /*OldInsnID*/0, /*OpIdx*/6, /*OperandRenderer*/GIMT_Encode2(GICR_renderExtractSWZ), // auxiliary
        GIR_MergeMemOperands, /*InsnID*/0, /*NumInsns*/1, /*MergeInsnID's*/0,
        GIR_ConstrainSelectedInstOperands, /*InsnID*/0,
        GIR_EraseFromParent, /*InsnID*/0,
        // GIR_Coverage, 4432,
        GIR_Done,
      // Label 6828: @501341
      GIM_Try, /*On fail goto*//*Label 6829*/ GIMT_Encode4(501451), // Rule ID 4436 //
        GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasUnrestrictedSOffset),
        // MIs[0] offset
        GIM_CheckIsImm, /*MI*/0, /*Op*/5,
        // MIs[0] auxiliary
        GIM_CheckIsImm, /*MI*/0, /*Op*/6,
        // MIs[0] Operand 7
        GIM_CheckIsImm, /*MI*/0, /*Op*/7,
        GIM_CheckComplexPattern, /*MI*/0, /*Op*/4, /*Renderer*/GIMT_Encode2(0), GIMT_Encode2(GICP_gi_buf_soffset),
        // (SIbuffer_store v2i32:{ *:[v2i32] }:$vdata, v4i32:{ *:[v4i32] }:$rsrc, i32:{ *:[i32] }:$vindex, i32:{ *:[i32] }:$voffset, (BUFSOffset:{ *:[i32] } i32:{ *:[i32] }:$soffset), (timm:{ *:[i32] }):$offset, (timm:{ *:[i32] }):$auxiliary, (timm:{ *:[i1] }))  =>  (BUFFER_STORE_DWORDX2_BOTHEN_exact anonymous_15036:{ *:[v2i32] }:$vdata, (REG_SEQUENCE:{ *:[i64] } VReg_64:{ *:[i32] }, VGPR_32:{ *:[i32] }:$vindex, sub0:{ *:[i32] }, VGPR_32:{ *:[i32] }:$voffset, sub1:{ *:[i32] }), SReg_128:{ *:[v4i32] }:$rsrc, SCSrc_b32:{ *:[i32] }:$soffset, (timm:{ *:[i32] }):$offset, (extract_cpol:{ *:[i32] } ?:{ *:[i32] }:$auxiliary), (extract_swz:{ *:[i1] } ?:{ *:[i32] }:$auxiliary))
        GIR_MakeTempReg, /*TempRegID*/0, /*TypeID*/GILLT_s64,
        GIR_BuildMI, /*InsnID*/1, /*Opcode*/GIMT_Encode2(TargetOpcode::REG_SEQUENCE),
        GIR_AddTempRegister, /*InsnID*/1, /*TempRegID*/0, /*TempRegFlags*/GIMT_Encode2(RegState::Define),
        GIR_Copy, /*NewInsnID*/1, /*OldInsnID*/0, /*OpIdx*/2, // vindex
        GIR_AddImm8, /*InsnID*/1, /*SubRegIndex*/3,
        GIR_Copy, /*NewInsnID*/1, /*OldInsnID*/0, /*OpIdx*/3, // voffset
        GIR_AddImm8, /*InsnID*/1, /*SubRegIndex*/11,
        GIR_ConstrainOperandRC, /*InsnID*/1, /*Op*/0, GIMT_Encode2(AMDGPU::VReg_64RegClassID),
        GIR_ConstrainOperandRC, /*InsnID*/1, /*Op*/1, GIMT_Encode2(AMDGPU::VGPR_32RegClassID),
        GIR_ConstrainOperandRC, /*InsnID*/1, /*Op*/3, GIMT_Encode2(AMDGPU::VGPR_32RegClassID),
        GIR_BuildMI, /*InsnID*/0, /*Opcode*/GIMT_Encode2(AMDGPU::BUFFER_STORE_DWORDX2_BOTHEN_exact),
        GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/0, // vdata
        GIR_AddSimpleTempRegister, /*InsnID*/0, /*TempRegID*/0,
        GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/1, // rsrc
        GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/0, // soffset
        GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/5, // offset
        GIR_CustomOperandRenderer, /*InsnID*/0, /*OldInsnID*/0, /*OpIdx*/6, /*OperandRenderer*/GIMT_Encode2(GICR_renderExtractCPol), // auxiliary
        GIR_CustomOperandRenderer, /*InsnID*/0, /*OldInsnID*/0, /*OpIdx*/6, /*OperandRenderer*/GIMT_Encode2(GICR_renderExtractSWZ), // auxiliary
        GIR_MergeMemOperands, /*InsnID*/0, /*NumInsns*/1, /*MergeInsnID's*/0,
        GIR_ConstrainSelectedInstOperands, /*InsnID*/0,
        GIR_EraseFromParent, /*InsnID*/0,
        // GIR_Coverage, 4436,
        GIR_Done,
      // Label 6829: @501451
      GIM_Try, /*On fail goto*//*Label 6830*/ GIMT_Encode4(501558), // Rule ID 4440 //
        // MIs[0] offset
        GIM_CheckIsImm, /*MI*/0, /*Op*/5,
        // MIs[0] auxiliary
        GIM_CheckIsImm, /*MI*/0, /*Op*/6,
        // MIs[0] Operand 7
        GIM_CheckIsImm, /*MI*/0, /*Op*/7,
        GIM_CheckComplexPattern, /*MI*/0, /*Op*/4, /*Renderer*/GIMT_Encode2(0), GIMT_Encode2(GICP_gi_buf_soffset),
        // (SIbuffer_store v2i32:{ *:[v2i32] }:$vdata, v4i32:{ *:[v4i32] }:$rsrc, i32:{ *:[i32] }:$vindex, i32:{ *:[i32] }:$voffset, (BUFSOffset:{ *:[i32] } i32:{ *:[i32] }:$soffset), (timm:{ *:[i32] }):$offset, (timm:{ *:[i32] }):$auxiliary, (timm:{ *:[i1] }))  =>  (BUFFER_STORE_DWORDX2_VBUFFER_BOTHEN_exact anonymous_15036:{ *:[v2i32] }:$vdata, (REG_SEQUENCE:{ *:[i64] } VReg_64:{ *:[i32] }, VGPR_32:{ *:[i32] }:$vindex, sub0:{ *:[i32] }, VGPR_32:{ *:[i32] }:$voffset, sub1:{ *:[i32] }), SReg_128:{ *:[v4i32] }:$rsrc, SCSrc_b32:{ *:[i32] }:$soffset, (timm:{ *:[i32] }):$offset, (extract_cpol:{ *:[i32] } ?:{ *:[i32] }:$auxiliary), (extract_swz:{ *:[i1] } ?:{ *:[i32] }:$auxiliary))
        GIR_MakeTempReg, /*TempRegID*/0, /*TypeID*/GILLT_s64,
        GIR_BuildMI, /*InsnID*/1, /*Opcode*/GIMT_Encode2(TargetOpcode::REG_SEQUENCE),
        GIR_AddTempRegister, /*InsnID*/1, /*TempRegID*/0, /*TempRegFlags*/GIMT_Encode2(RegState::Define),
        GIR_Copy, /*NewInsnID*/1, /*OldInsnID*/0, /*OpIdx*/2, // vindex
        GIR_AddImm8, /*InsnID*/1, /*SubRegIndex*/3,
        GIR_Copy, /*NewInsnID*/1, /*OldInsnID*/0, /*OpIdx*/3, // voffset
        GIR_AddImm8, /*InsnID*/1, /*SubRegIndex*/11,
        GIR_ConstrainOperandRC, /*InsnID*/1, /*Op*/0, GIMT_Encode2(AMDGPU::VReg_64RegClassID),
        GIR_ConstrainOperandRC, /*InsnID*/1, /*Op*/1, GIMT_Encode2(AMDGPU::VGPR_32RegClassID),
        GIR_ConstrainOperandRC, /*InsnID*/1, /*Op*/3, GIMT_Encode2(AMDGPU::VGPR_32RegClassID),
        GIR_BuildMI, /*InsnID*/0, /*Opcode*/GIMT_Encode2(AMDGPU::BUFFER_STORE_DWORDX2_VBUFFER_BOTHEN_exact),
        GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/0, // vdata
        GIR_AddSimpleTempRegister, /*InsnID*/0, /*TempRegID*/0,
        GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/1, // rsrc
        GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/0, // soffset
        GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/5, // offset
        GIR_CustomOperandRenderer, /*InsnID*/0, /*OldInsnID*/0, /*OpIdx*/6, /*OperandRenderer*/GIMT_Encode2(GICR_renderExtractCPol), // auxiliary
        GIR_CustomOperandRenderer, /*InsnID*/0, /*OldInsnID*/0, /*OpIdx*/6, /*OperandRenderer*/GIMT_Encode2(GICR_renderExtractSWZ), // auxiliary
        GIR_MergeMemOperands, /*InsnID*/0, /*NumInsns*/1, /*MergeInsnID's*/0,
        GIR_ConstrainSelectedInstOperands, /*InsnID*/0,
        GIR_EraseFromParent, /*InsnID*/0,
        // GIR_Coverage, 4440,
        GIR_Done,
      // Label 6830: @501558
      GIM_Reject,
    // Label 6814: @501559
    GIM_Reject,
    // Label 6776: @501560
    GIM_Try, /*On fail goto*//*Label 6831*/ GIMT_Encode4(502950),
      GIM_CheckType, /*MI*/0, /*Op*/1, /*Type*/GILLT_v4s32,
      GIM_CheckType, /*MI*/0, /*Op*/2, /*Type*/GILLT_s32,
      GIM_CheckType, /*MI*/0, /*Op*/3, /*Type*/GILLT_s32,
      GIM_CheckType, /*MI*/0, /*Op*/4, /*Type*/GILLT_s32,
      GIM_Try, /*On fail goto*//*Label 6832*/ GIMT_Encode4(501663), // Rule ID 4457 //
        GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasUnrestrictedSOffset),
        GIM_CheckConstantInt8, /*MI*/0, /*Op*/2, 0,
        GIM_CheckConstantInt8, /*MI*/0, /*Op*/3, 0,
        // MIs[0] offset
        GIM_CheckIsImm, /*MI*/0, /*Op*/5,
        // MIs[0] auxiliary
        GIM_CheckIsImm, /*MI*/0, /*Op*/6,
        // MIs[0] Operand 7
        GIM_CheckLiteralInt, /*MI*/0, /*Op*/7, GIMT_Encode8(0),
        GIM_CheckComplexPattern, /*MI*/0, /*Op*/4, /*Renderer*/GIMT_Encode2(0), GIMT_Encode2(GICP_gi_buf_soffset),
        // (SIbuffer_store v3f32:{ *:[v3f32] }:$vdata, v4i32:{ *:[v4i32] }:$rsrc, 0:{ *:[i32] }, 0:{ *:[i32] }, (BUFSOffset:{ *:[i32] } i32:{ *:[i32] }:$soffset), (timm:{ *:[i32] }):$offset, (timm:{ *:[i32] }):$auxiliary, 0:{ *:[i1] })  =>  (BUFFER_STORE_DWORDX3_OFFSET_exact anonymous_15035:{ *:[v3f32] }:$vdata, SReg_128:{ *:[v4i32] }:$rsrc, SCSrc_b32:{ *:[i32] }:$soffset, (timm:{ *:[i32] }):$offset, (extract_cpol:{ *:[i32] } ?:{ *:[i32] }:$auxiliary), (extract_swz:{ *:[i1] } ?:{ *:[i32] }:$auxiliary))
        GIR_BuildMI, /*InsnID*/0, /*Opcode*/GIMT_Encode2(AMDGPU::BUFFER_STORE_DWORDX3_OFFSET_exact),
        GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/0, // vdata
        GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/1, // rsrc
        GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/0, // soffset
        GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/5, // offset
        GIR_CustomOperandRenderer, /*InsnID*/0, /*OldInsnID*/0, /*OpIdx*/6, /*OperandRenderer*/GIMT_Encode2(GICR_renderExtractCPol), // auxiliary
        GIR_CustomOperandRenderer, /*InsnID*/0, /*OldInsnID*/0, /*OpIdx*/6, /*OperandRenderer*/GIMT_Encode2(GICR_renderExtractSWZ), // auxiliary
        GIR_MergeMemOperands, /*InsnID*/0, /*NumInsns*/1, /*MergeInsnID's*/0,
        GIR_ConstrainSelectedInstOperands, /*InsnID*/0,
        GIR_EraseFromParent, /*InsnID*/0,
        // GIR_Coverage, 4457,
        GIR_Done,
      // Label 6832: @501663
      GIM_Try, /*On fail goto*//*Label 6833*/ GIMT_Encode4(501742), // Rule ID 4461 //
        GIM_CheckConstantInt8, /*MI*/0, /*Op*/2, 0,
        GIM_CheckConstantInt8, /*MI*/0, /*Op*/3, 0,
        // MIs[0] offset
        GIM_CheckIsImm, /*MI*/0, /*Op*/5,
        // MIs[0] auxiliary
        GIM_CheckIsImm, /*MI*/0, /*Op*/6,
        // MIs[0] Operand 7
        GIM_CheckLiteralInt, /*MI*/0, /*Op*/7, GIMT_Encode8(0),
        GIM_CheckComplexPattern, /*MI*/0, /*Op*/4, /*Renderer*/GIMT_Encode2(0), GIMT_Encode2(GICP_gi_buf_soffset),
        // (SIbuffer_store v3f32:{ *:[v3f32] }:$vdata, v4i32:{ *:[v4i32] }:$rsrc, 0:{ *:[i32] }, 0:{ *:[i32] }, (BUFSOffset:{ *:[i32] } i32:{ *:[i32] }:$soffset), (timm:{ *:[i32] }):$offset, (timm:{ *:[i32] }):$auxiliary, 0:{ *:[i1] })  =>  (BUFFER_STORE_DWORDX3_VBUFFER_OFFSET_exact anonymous_15035:{ *:[v3f32] }:$vdata, SReg_128:{ *:[v4i32] }:$rsrc, SCSrc_b32:{ *:[i32] }:$soffset, (timm:{ *:[i32] }):$offset, (extract_cpol:{ *:[i32] } ?:{ *:[i32] }:$auxiliary), (extract_swz:{ *:[i1] } ?:{ *:[i32] }:$auxiliary))
        GIR_BuildMI, /*InsnID*/0, /*Opcode*/GIMT_Encode2(AMDGPU::BUFFER_STORE_DWORDX3_VBUFFER_OFFSET_exact),
        GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/0, // vdata
        GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/1, // rsrc
        GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/0, // soffset
        GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/5, // offset
        GIR_CustomOperandRenderer, /*InsnID*/0, /*OldInsnID*/0, /*OpIdx*/6, /*OperandRenderer*/GIMT_Encode2(GICR_renderExtractCPol), // auxiliary
        GIR_CustomOperandRenderer, /*InsnID*/0, /*OldInsnID*/0, /*OpIdx*/6, /*OperandRenderer*/GIMT_Encode2(GICR_renderExtractSWZ), // auxiliary
        GIR_MergeMemOperands, /*InsnID*/0, /*NumInsns*/1, /*MergeInsnID's*/0,
        GIR_ConstrainSelectedInstOperands, /*InsnID*/0,
        GIR_EraseFromParent, /*InsnID*/0,
        // GIR_Coverage, 4461,
        GIR_Done,
      // Label 6833: @501742
      GIM_Try, /*On fail goto*//*Label 6834*/ GIMT_Encode4(501824), // Rule ID 4465 //
        GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasUnrestrictedSOffset),
        GIM_CheckConstantInt8, /*MI*/0, /*Op*/2, 0,
        GIM_CheckConstantInt8, /*MI*/0, /*Op*/3, 0,
        // MIs[0] offset
        GIM_CheckIsImm, /*MI*/0, /*Op*/5,
        // MIs[0] auxiliary
        GIM_CheckIsImm, /*MI*/0, /*Op*/6,
        // MIs[0] Operand 7
        GIM_CheckLiteralInt, /*MI*/0, /*Op*/7, GIMT_Encode8(0),
        GIM_CheckComplexPattern, /*MI*/0, /*Op*/4, /*Renderer*/GIMT_Encode2(0), GIMT_Encode2(GICP_gi_buf_soffset),
        // (SIbuffer_store v3i32:{ *:[v3i32] }:$vdata, v4i32:{ *:[v4i32] }:$rsrc, 0:{ *:[i32] }, 0:{ *:[i32] }, (BUFSOffset:{ *:[i32] } i32:{ *:[i32] }:$soffset), (timm:{ *:[i32] }):$offset, (timm:{ *:[i32] }):$auxiliary, 0:{ *:[i1] })  =>  (BUFFER_STORE_DWORDX3_OFFSET_exact anonymous_15035:{ *:[v3i32] }:$vdata, SReg_128:{ *:[v4i32] }:$rsrc, SCSrc_b32:{ *:[i32] }:$soffset, (timm:{ *:[i32] }):$offset, (extract_cpol:{ *:[i32] } ?:{ *:[i32] }:$auxiliary), (extract_swz:{ *:[i1] } ?:{ *:[i32] }:$auxiliary))
        GIR_BuildMI, /*InsnID*/0, /*Opcode*/GIMT_Encode2(AMDGPU::BUFFER_STORE_DWORDX3_OFFSET_exact),
        GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/0, // vdata
        GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/1, // rsrc
        GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/0, // soffset
        GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/5, // offset
        GIR_CustomOperandRenderer, /*InsnID*/0, /*OldInsnID*/0, /*OpIdx*/6, /*OperandRenderer*/GIMT_Encode2(GICR_renderExtractCPol), // auxiliary
        GIR_CustomOperandRenderer, /*InsnID*/0, /*OldInsnID*/0, /*OpIdx*/6, /*OperandRenderer*/GIMT_Encode2(GICR_renderExtractSWZ), // auxiliary
        GIR_MergeMemOperands, /*InsnID*/0, /*NumInsns*/1, /*MergeInsnID's*/0,
        GIR_ConstrainSelectedInstOperands, /*InsnID*/0,
        GIR_EraseFromParent, /*InsnID*/0,
        // GIR_Coverage, 4465,
        GIR_Done,
      // Label 6834: @501824
      GIM_Try, /*On fail goto*//*Label 6835*/ GIMT_Encode4(501903), // Rule ID 4469 //
        GIM_CheckConstantInt8, /*MI*/0, /*Op*/2, 0,
        GIM_CheckConstantInt8, /*MI*/0, /*Op*/3, 0,
        // MIs[0] offset
        GIM_CheckIsImm, /*MI*/0, /*Op*/5,
        // MIs[0] auxiliary
        GIM_CheckIsImm, /*MI*/0, /*Op*/6,
        // MIs[0] Operand 7
        GIM_CheckLiteralInt, /*MI*/0, /*Op*/7, GIMT_Encode8(0),
        GIM_CheckComplexPattern, /*MI*/0, /*Op*/4, /*Renderer*/GIMT_Encode2(0), GIMT_Encode2(GICP_gi_buf_soffset),
        // (SIbuffer_store v3i32:{ *:[v3i32] }:$vdata, v4i32:{ *:[v4i32] }:$rsrc, 0:{ *:[i32] }, 0:{ *:[i32] }, (BUFSOffset:{ *:[i32] } i32:{ *:[i32] }:$soffset), (timm:{ *:[i32] }):$offset, (timm:{ *:[i32] }):$auxiliary, 0:{ *:[i1] })  =>  (BUFFER_STORE_DWORDX3_VBUFFER_OFFSET_exact anonymous_15035:{ *:[v3i32] }:$vdata, SReg_128:{ *:[v4i32] }:$rsrc, SCSrc_b32:{ *:[i32] }:$soffset, (timm:{ *:[i32] }):$offset, (extract_cpol:{ *:[i32] } ?:{ *:[i32] }:$auxiliary), (extract_swz:{ *:[i1] } ?:{ *:[i32] }:$auxiliary))
        GIR_BuildMI, /*InsnID*/0, /*Opcode*/GIMT_Encode2(AMDGPU::BUFFER_STORE_DWORDX3_VBUFFER_OFFSET_exact),
        GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/0, // vdata
        GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/1, // rsrc
        GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/0, // soffset
        GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/5, // offset
        GIR_CustomOperandRenderer, /*InsnID*/0, /*OldInsnID*/0, /*OpIdx*/6, /*OperandRenderer*/GIMT_Encode2(GICR_renderExtractCPol), // auxiliary
        GIR_CustomOperandRenderer, /*InsnID*/0, /*OldInsnID*/0, /*OpIdx*/6, /*OperandRenderer*/GIMT_Encode2(GICR_renderExtractSWZ), // auxiliary
        GIR_MergeMemOperands, /*InsnID*/0, /*NumInsns*/1, /*MergeInsnID's*/0,
        GIR_ConstrainSelectedInstOperands, /*InsnID*/0,
        GIR_EraseFromParent, /*InsnID*/0,
        // GIR_Coverage, 4469,
        GIR_Done,
      // Label 6835: @501903
      GIM_Try, /*On fail goto*//*Label 6836*/ GIMT_Encode4(501985), // Rule ID 4458 //
        GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasUnrestrictedSOffset),
        GIM_CheckConstantInt8, /*MI*/0, /*Op*/2, 0,
        // MIs[0] offset
        GIM_CheckIsImm, /*MI*/0, /*Op*/5,
        // MIs[0] auxiliary
        GIM_CheckIsImm, /*MI*/0, /*Op*/6,
        // MIs[0] Operand 7
        GIM_CheckLiteralInt, /*MI*/0, /*Op*/7, GIMT_Encode8(0),
        GIM_CheckComplexPattern, /*MI*/0, /*Op*/4, /*Renderer*/GIMT_Encode2(0), GIMT_Encode2(GICP_gi_buf_soffset),
        // (SIbuffer_store v3f32:{ *:[v3f32] }:$vdata, v4i32:{ *:[v4i32] }:$rsrc, 0:{ *:[i32] }, i32:{ *:[i32] }:$voffset, (BUFSOffset:{ *:[i32] } i32:{ *:[i32] }:$soffset), (timm:{ *:[i32] }):$offset, (timm:{ *:[i32] }):$auxiliary, 0:{ *:[i1] })  =>  (BUFFER_STORE_DWORDX3_OFFEN_exact anonymous_15035:{ *:[v3f32] }:$vdata, VGPR_32:{ *:[i32] }:$voffset, SReg_128:{ *:[v4i32] }:$rsrc, SCSrc_b32:{ *:[i32] }:$soffset, (timm:{ *:[i32] }):$offset, (extract_cpol:{ *:[i32] } ?:{ *:[i32] }:$auxiliary), (extract_swz:{ *:[i1] } ?:{ *:[i32] }:$auxiliary))
        GIR_BuildMI, /*InsnID*/0, /*Opcode*/GIMT_Encode2(AMDGPU::BUFFER_STORE_DWORDX3_OFFEN_exact),
        GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/0, // vdata
        GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/3, // voffset
        GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/1, // rsrc
        GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/0, // soffset
        GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/5, // offset
        GIR_CustomOperandRenderer, /*InsnID*/0, /*OldInsnID*/0, /*OpIdx*/6, /*OperandRenderer*/GIMT_Encode2(GICR_renderExtractCPol), // auxiliary
        GIR_CustomOperandRenderer, /*InsnID*/0, /*OldInsnID*/0, /*OpIdx*/6, /*OperandRenderer*/GIMT_Encode2(GICR_renderExtractSWZ), // auxiliary
        GIR_MergeMemOperands, /*InsnID*/0, /*NumInsns*/1, /*MergeInsnID's*/0,
        GIR_ConstrainSelectedInstOperands, /*InsnID*/0,
        GIR_EraseFromParent, /*InsnID*/0,
        // GIR_Coverage, 4458,
        GIR_Done,
      // Label 6836: @501985
      GIM_Try, /*On fail goto*//*Label 6837*/ GIMT_Encode4(502064), // Rule ID 4462 //
        GIM_CheckConstantInt8, /*MI*/0, /*Op*/2, 0,
        // MIs[0] offset
        GIM_CheckIsImm, /*MI*/0, /*Op*/5,
        // MIs[0] auxiliary
        GIM_CheckIsImm, /*MI*/0, /*Op*/6,
        // MIs[0] Operand 7
        GIM_CheckLiteralInt, /*MI*/0, /*Op*/7, GIMT_Encode8(0),
        GIM_CheckComplexPattern, /*MI*/0, /*Op*/4, /*Renderer*/GIMT_Encode2(0), GIMT_Encode2(GICP_gi_buf_soffset),
        // (SIbuffer_store v3f32:{ *:[v3f32] }:$vdata, v4i32:{ *:[v4i32] }:$rsrc, 0:{ *:[i32] }, i32:{ *:[i32] }:$voffset, (BUFSOffset:{ *:[i32] } i32:{ *:[i32] }:$soffset), (timm:{ *:[i32] }):$offset, (timm:{ *:[i32] }):$auxiliary, 0:{ *:[i1] })  =>  (BUFFER_STORE_DWORDX3_VBUFFER_OFFEN_exact anonymous_15035:{ *:[v3f32] }:$vdata, VGPR_32:{ *:[i32] }:$voffset, SReg_128:{ *:[v4i32] }:$rsrc, SCSrc_b32:{ *:[i32] }:$soffset, (timm:{ *:[i32] }):$offset, (extract_cpol:{ *:[i32] } ?:{ *:[i32] }:$auxiliary), (extract_swz:{ *:[i1] } ?:{ *:[i32] }:$auxiliary))
        GIR_BuildMI, /*InsnID*/0, /*Opcode*/GIMT_Encode2(AMDGPU::BUFFER_STORE_DWORDX3_VBUFFER_OFFEN_exact),
        GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/0, // vdata
        GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/3, // voffset
        GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/1, // rsrc
        GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/0, // soffset
        GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/5, // offset
        GIR_CustomOperandRenderer, /*InsnID*/0, /*OldInsnID*/0, /*OpIdx*/6, /*OperandRenderer*/GIMT_Encode2(GICR_renderExtractCPol), // auxiliary
        GIR_CustomOperandRenderer, /*InsnID*/0, /*OldInsnID*/0, /*OpIdx*/6, /*OperandRenderer*/GIMT_Encode2(GICR_renderExtractSWZ), // auxiliary
        GIR_MergeMemOperands, /*InsnID*/0, /*NumInsns*/1, /*MergeInsnID's*/0,
        GIR_ConstrainSelectedInstOperands, /*InsnID*/0,
        GIR_EraseFromParent, /*InsnID*/0,
        // GIR_Coverage, 4462,
        GIR_Done,
      // Label 6837: @502064
      GIM_Try, /*On fail goto*//*Label 6838*/ GIMT_Encode4(502146), // Rule ID 4466 //
        GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasUnrestrictedSOffset),
        GIM_CheckConstantInt8, /*MI*/0, /*Op*/2, 0,
        // MIs[0] offset
        GIM_CheckIsImm, /*MI*/0, /*Op*/5,
        // MIs[0] auxiliary
        GIM_CheckIsImm, /*MI*/0, /*Op*/6,
        // MIs[0] Operand 7
        GIM_CheckLiteralInt, /*MI*/0, /*Op*/7, GIMT_Encode8(0),
        GIM_CheckComplexPattern, /*MI*/0, /*Op*/4, /*Renderer*/GIMT_Encode2(0), GIMT_Encode2(GICP_gi_buf_soffset),
        // (SIbuffer_store v3i32:{ *:[v3i32] }:$vdata, v4i32:{ *:[v4i32] }:$rsrc, 0:{ *:[i32] }, i32:{ *:[i32] }:$voffset, (BUFSOffset:{ *:[i32] } i32:{ *:[i32] }:$soffset), (timm:{ *:[i32] }):$offset, (timm:{ *:[i32] }):$auxiliary, 0:{ *:[i1] })  =>  (BUFFER_STORE_DWORDX3_OFFEN_exact anonymous_15035:{ *:[v3i32] }:$vdata, VGPR_32:{ *:[i32] }:$voffset, SReg_128:{ *:[v4i32] }:$rsrc, SCSrc_b32:{ *:[i32] }:$soffset, (timm:{ *:[i32] }):$offset, (extract_cpol:{ *:[i32] } ?:{ *:[i32] }:$auxiliary), (extract_swz:{ *:[i1] } ?:{ *:[i32] }:$auxiliary))
        GIR_BuildMI, /*InsnID*/0, /*Opcode*/GIMT_Encode2(AMDGPU::BUFFER_STORE_DWORDX3_OFFEN_exact),
        GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/0, // vdata
        GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/3, // voffset
        GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/1, // rsrc
        GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/0, // soffset
        GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/5, // offset
        GIR_CustomOperandRenderer, /*InsnID*/0, /*OldInsnID*/0, /*OpIdx*/6, /*OperandRenderer*/GIMT_Encode2(GICR_renderExtractCPol), // auxiliary
        GIR_CustomOperandRenderer, /*InsnID*/0, /*OldInsnID*/0, /*OpIdx*/6, /*OperandRenderer*/GIMT_Encode2(GICR_renderExtractSWZ), // auxiliary
        GIR_MergeMemOperands, /*InsnID*/0, /*NumInsns*/1, /*MergeInsnID's*/0,
        GIR_ConstrainSelectedInstOperands, /*InsnID*/0,
        GIR_EraseFromParent, /*InsnID*/0,
        // GIR_Coverage, 4466,
        GIR_Done,
      // Label 6838: @502146
      GIM_Try, /*On fail goto*//*Label 6839*/ GIMT_Encode4(502225), // Rule ID 4470 //
        GIM_CheckConstantInt8, /*MI*/0, /*Op*/2, 0,
        // MIs[0] offset
        GIM_CheckIsImm, /*MI*/0, /*Op*/5,
        // MIs[0] auxiliary
        GIM_CheckIsImm, /*MI*/0, /*Op*/6,
        // MIs[0] Operand 7
        GIM_CheckLiteralInt, /*MI*/0, /*Op*/7, GIMT_Encode8(0),
        GIM_CheckComplexPattern, /*MI*/0, /*Op*/4, /*Renderer*/GIMT_Encode2(0), GIMT_Encode2(GICP_gi_buf_soffset),
        // (SIbuffer_store v3i32:{ *:[v3i32] }:$vdata, v4i32:{ *:[v4i32] }:$rsrc, 0:{ *:[i32] }, i32:{ *:[i32] }:$voffset, (BUFSOffset:{ *:[i32] } i32:{ *:[i32] }:$soffset), (timm:{ *:[i32] }):$offset, (timm:{ *:[i32] }):$auxiliary, 0:{ *:[i1] })  =>  (BUFFER_STORE_DWORDX3_VBUFFER_OFFEN_exact anonymous_15035:{ *:[v3i32] }:$vdata, VGPR_32:{ *:[i32] }:$voffset, SReg_128:{ *:[v4i32] }:$rsrc, SCSrc_b32:{ *:[i32] }:$soffset, (timm:{ *:[i32] }):$offset, (extract_cpol:{ *:[i32] } ?:{ *:[i32] }:$auxiliary), (extract_swz:{ *:[i1] } ?:{ *:[i32] }:$auxiliary))
        GIR_BuildMI, /*InsnID*/0, /*Opcode*/GIMT_Encode2(AMDGPU::BUFFER_STORE_DWORDX3_VBUFFER_OFFEN_exact),
        GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/0, // vdata
        GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/3, // voffset
        GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/1, // rsrc
        GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/0, // soffset
        GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/5, // offset
        GIR_CustomOperandRenderer, /*InsnID*/0, /*OldInsnID*/0, /*OpIdx*/6, /*OperandRenderer*/GIMT_Encode2(GICR_renderExtractCPol), // auxiliary
        GIR_CustomOperandRenderer, /*InsnID*/0, /*OldInsnID*/0, /*OpIdx*/6, /*OperandRenderer*/GIMT_Encode2(GICR_renderExtractSWZ), // auxiliary
        GIR_MergeMemOperands, /*InsnID*/0, /*NumInsns*/1, /*MergeInsnID's*/0,
        GIR_ConstrainSelectedInstOperands, /*InsnID*/0,
        GIR_EraseFromParent, /*InsnID*/0,
        // GIR_Coverage, 4470,
        GIR_Done,
      // Label 6839: @502225
      GIM_Try, /*On fail goto*//*Label 6840*/ GIMT_Encode4(502299), // Rule ID 4459 //
        GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasUnrestrictedSOffset),
        GIM_CheckConstantInt8, /*MI*/0, /*Op*/3, 0,
        // MIs[0] offset
        GIM_CheckIsImm, /*MI*/0, /*Op*/5,
        // MIs[0] auxiliary
        GIM_CheckIsImm, /*MI*/0, /*Op*/6,
        // MIs[0] Operand 7
        GIM_CheckIsImm, /*MI*/0, /*Op*/7,
        GIM_CheckComplexPattern, /*MI*/0, /*Op*/4, /*Renderer*/GIMT_Encode2(0), GIMT_Encode2(GICP_gi_buf_soffset),
        // (SIbuffer_store v3f32:{ *:[v3f32] }:$vdata, v4i32:{ *:[v4i32] }:$rsrc, i32:{ *:[i32] }:$vindex, 0:{ *:[i32] }, (BUFSOffset:{ *:[i32] } i32:{ *:[i32] }:$soffset), (timm:{ *:[i32] }):$offset, (timm:{ *:[i32] }):$auxiliary, (timm:{ *:[i1] }))  =>  (BUFFER_STORE_DWORDX3_IDXEN_exact anonymous_15035:{ *:[v3f32] }:$vdata, VGPR_32:{ *:[i32] }:$vindex, SReg_128:{ *:[v4i32] }:$rsrc, SCSrc_b32:{ *:[i32] }:$soffset, (timm:{ *:[i32] }):$offset, (extract_cpol:{ *:[i32] } ?:{ *:[i32] }:$auxiliary), (extract_swz:{ *:[i1] } ?:{ *:[i32] }:$auxiliary))
        GIR_BuildMI, /*InsnID*/0, /*Opcode*/GIMT_Encode2(AMDGPU::BUFFER_STORE_DWORDX3_IDXEN_exact),
        GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/0, // vdata
        GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/2, // vindex
        GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/1, // rsrc
        GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/0, // soffset
        GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/5, // offset
        GIR_CustomOperandRenderer, /*InsnID*/0, /*OldInsnID*/0, /*OpIdx*/6, /*OperandRenderer*/GIMT_Encode2(GICR_renderExtractCPol), // auxiliary
        GIR_CustomOperandRenderer, /*InsnID*/0, /*OldInsnID*/0, /*OpIdx*/6, /*OperandRenderer*/GIMT_Encode2(GICR_renderExtractSWZ), // auxiliary
        GIR_MergeMemOperands, /*InsnID*/0, /*NumInsns*/1, /*MergeInsnID's*/0,
        GIR_ConstrainSelectedInstOperands, /*InsnID*/0,
        GIR_EraseFromParent, /*InsnID*/0,
        // GIR_Coverage, 4459,
        GIR_Done,
      // Label 6840: @502299
      GIM_Try, /*On fail goto*//*Label 6841*/ GIMT_Encode4(502370), // Rule ID 4463 //
        GIM_CheckConstantInt8, /*MI*/0, /*Op*/3, 0,
        // MIs[0] offset
        GIM_CheckIsImm, /*MI*/0, /*Op*/5,
        // MIs[0] auxiliary
        GIM_CheckIsImm, /*MI*/0, /*Op*/6,
        // MIs[0] Operand 7
        GIM_CheckIsImm, /*MI*/0, /*Op*/7,
        GIM_CheckComplexPattern, /*MI*/0, /*Op*/4, /*Renderer*/GIMT_Encode2(0), GIMT_Encode2(GICP_gi_buf_soffset),
        // (SIbuffer_store v3f32:{ *:[v3f32] }:$vdata, v4i32:{ *:[v4i32] }:$rsrc, i32:{ *:[i32] }:$vindex, 0:{ *:[i32] }, (BUFSOffset:{ *:[i32] } i32:{ *:[i32] }:$soffset), (timm:{ *:[i32] }):$offset, (timm:{ *:[i32] }):$auxiliary, (timm:{ *:[i1] }))  =>  (BUFFER_STORE_DWORDX3_VBUFFER_IDXEN_exact anonymous_15035:{ *:[v3f32] }:$vdata, VGPR_32:{ *:[i32] }:$vindex, SReg_128:{ *:[v4i32] }:$rsrc, SCSrc_b32:{ *:[i32] }:$soffset, (timm:{ *:[i32] }):$offset, (extract_cpol:{ *:[i32] } ?:{ *:[i32] }:$auxiliary), (extract_swz:{ *:[i1] } ?:{ *:[i32] }:$auxiliary))
        GIR_BuildMI, /*InsnID*/0, /*Opcode*/GIMT_Encode2(AMDGPU::BUFFER_STORE_DWORDX3_VBUFFER_IDXEN_exact),
        GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/0, // vdata
        GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/2, // vindex
        GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/1, // rsrc
        GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/0, // soffset
        GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/5, // offset
        GIR_CustomOperandRenderer, /*InsnID*/0, /*OldInsnID*/0, /*OpIdx*/6, /*OperandRenderer*/GIMT_Encode2(GICR_renderExtractCPol), // auxiliary
        GIR_CustomOperandRenderer, /*InsnID*/0, /*OldInsnID*/0, /*OpIdx*/6, /*OperandRenderer*/GIMT_Encode2(GICR_renderExtractSWZ), // auxiliary
        GIR_MergeMemOperands, /*InsnID*/0, /*NumInsns*/1, /*MergeInsnID's*/0,
        GIR_ConstrainSelectedInstOperands, /*InsnID*/0,
        GIR_EraseFromParent, /*InsnID*/0,
        // GIR_Coverage, 4463,
        GIR_Done,
      // Label 6841: @502370
      GIM_Try, /*On fail goto*//*Label 6842*/ GIMT_Encode4(502444), // Rule ID 4467 //
        GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasUnrestrictedSOffset),
        GIM_CheckConstantInt8, /*MI*/0, /*Op*/3, 0,
        // MIs[0] offset
        GIM_CheckIsImm, /*MI*/0, /*Op*/5,
        // MIs[0] auxiliary
        GIM_CheckIsImm, /*MI*/0, /*Op*/6,
        // MIs[0] Operand 7
        GIM_CheckIsImm, /*MI*/0, /*Op*/7,
        GIM_CheckComplexPattern, /*MI*/0, /*Op*/4, /*Renderer*/GIMT_Encode2(0), GIMT_Encode2(GICP_gi_buf_soffset),
        // (SIbuffer_store v3i32:{ *:[v3i32] }:$vdata, v4i32:{ *:[v4i32] }:$rsrc, i32:{ *:[i32] }:$vindex, 0:{ *:[i32] }, (BUFSOffset:{ *:[i32] } i32:{ *:[i32] }:$soffset), (timm:{ *:[i32] }):$offset, (timm:{ *:[i32] }):$auxiliary, (timm:{ *:[i1] }))  =>  (BUFFER_STORE_DWORDX3_IDXEN_exact anonymous_15035:{ *:[v3i32] }:$vdata, VGPR_32:{ *:[i32] }:$vindex, SReg_128:{ *:[v4i32] }:$rsrc, SCSrc_b32:{ *:[i32] }:$soffset, (timm:{ *:[i32] }):$offset, (extract_cpol:{ *:[i32] } ?:{ *:[i32] }:$auxiliary), (extract_swz:{ *:[i1] } ?:{ *:[i32] }:$auxiliary))
        GIR_BuildMI, /*InsnID*/0, /*Opcode*/GIMT_Encode2(AMDGPU::BUFFER_STORE_DWORDX3_IDXEN_exact),
        GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/0, // vdata
        GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/2, // vindex
        GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/1, // rsrc
        GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/0, // soffset
        GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/5, // offset
        GIR_CustomOperandRenderer, /*InsnID*/0, /*OldInsnID*/0, /*OpIdx*/6, /*OperandRenderer*/GIMT_Encode2(GICR_renderExtractCPol), // auxiliary
        GIR_CustomOperandRenderer, /*InsnID*/0, /*OldInsnID*/0, /*OpIdx*/6, /*OperandRenderer*/GIMT_Encode2(GICR_renderExtractSWZ), // auxiliary
        GIR_MergeMemOperands, /*InsnID*/0, /*NumInsns*/1, /*MergeInsnID's*/0,
        GIR_ConstrainSelectedInstOperands, /*InsnID*/0,
        GIR_EraseFromParent, /*InsnID*/0,
        // GIR_Coverage, 4467,
        GIR_Done,
      // Label 6842: @502444
      GIM_Try, /*On fail goto*//*Label 6843*/ GIMT_Encode4(502515), // Rule ID 4471 //
        GIM_CheckConstantInt8, /*MI*/0, /*Op*/3, 0,
        // MIs[0] offset
        GIM_CheckIsImm, /*MI*/0, /*Op*/5,
        // MIs[0] auxiliary
        GIM_CheckIsImm, /*MI*/0, /*Op*/6,
        // MIs[0] Operand 7
        GIM_CheckIsImm, /*MI*/0, /*Op*/7,
        GIM_CheckComplexPattern, /*MI*/0, /*Op*/4, /*Renderer*/GIMT_Encode2(0), GIMT_Encode2(GICP_gi_buf_soffset),
        // (SIbuffer_store v3i32:{ *:[v3i32] }:$vdata, v4i32:{ *:[v4i32] }:$rsrc, i32:{ *:[i32] }:$vindex, 0:{ *:[i32] }, (BUFSOffset:{ *:[i32] } i32:{ *:[i32] }:$soffset), (timm:{ *:[i32] }):$offset, (timm:{ *:[i32] }):$auxiliary, (timm:{ *:[i1] }))  =>  (BUFFER_STORE_DWORDX3_VBUFFER_IDXEN_exact anonymous_15035:{ *:[v3i32] }:$vdata, VGPR_32:{ *:[i32] }:$vindex, SReg_128:{ *:[v4i32] }:$rsrc, SCSrc_b32:{ *:[i32] }:$soffset, (timm:{ *:[i32] }):$offset, (extract_cpol:{ *:[i32] } ?:{ *:[i32] }:$auxiliary), (extract_swz:{ *:[i1] } ?:{ *:[i32] }:$auxiliary))
        GIR_BuildMI, /*InsnID*/0, /*Opcode*/GIMT_Encode2(AMDGPU::BUFFER_STORE_DWORDX3_VBUFFER_IDXEN_exact),
        GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/0, // vdata
        GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/2, // vindex
        GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/1, // rsrc
        GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/0, // soffset
        GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/5, // offset
        GIR_CustomOperandRenderer, /*InsnID*/0, /*OldInsnID*/0, /*OpIdx*/6, /*OperandRenderer*/GIMT_Encode2(GICR_renderExtractCPol), // auxiliary
        GIR_CustomOperandRenderer, /*InsnID*/0, /*OldInsnID*/0, /*OpIdx*/6, /*OperandRenderer*/GIMT_Encode2(GICR_renderExtractSWZ), // auxiliary
        GIR_MergeMemOperands, /*InsnID*/0, /*NumInsns*/1, /*MergeInsnID's*/0,
        GIR_ConstrainSelectedInstOperands, /*InsnID*/0,
        GIR_EraseFromParent, /*InsnID*/0,
        // GIR_Coverage, 4471,
        GIR_Done,
      // Label 6843: @502515
      GIM_Try, /*On fail goto*//*Label 6844*/ GIMT_Encode4(502625), // Rule ID 4460 //
        GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasUnrestrictedSOffset),
        // MIs[0] offset
        GIM_CheckIsImm, /*MI*/0, /*Op*/5,
        // MIs[0] auxiliary
        GIM_CheckIsImm, /*MI*/0, /*Op*/6,
        // MIs[0] Operand 7
        GIM_CheckIsImm, /*MI*/0, /*Op*/7,
        GIM_CheckComplexPattern, /*MI*/0, /*Op*/4, /*Renderer*/GIMT_Encode2(0), GIMT_Encode2(GICP_gi_buf_soffset),
        // (SIbuffer_store v3f32:{ *:[v3f32] }:$vdata, v4i32:{ *:[v4i32] }:$rsrc, i32:{ *:[i32] }:$vindex, i32:{ *:[i32] }:$voffset, (BUFSOffset:{ *:[i32] } i32:{ *:[i32] }:$soffset), (timm:{ *:[i32] }):$offset, (timm:{ *:[i32] }):$auxiliary, (timm:{ *:[i1] }))  =>  (BUFFER_STORE_DWORDX3_BOTHEN_exact anonymous_15035:{ *:[v3f32] }:$vdata, (REG_SEQUENCE:{ *:[i64] } VReg_64:{ *:[i32] }, VGPR_32:{ *:[i32] }:$vindex, sub0:{ *:[i32] }, VGPR_32:{ *:[i32] }:$voffset, sub1:{ *:[i32] }), SReg_128:{ *:[v4i32] }:$rsrc, SCSrc_b32:{ *:[i32] }:$soffset, (timm:{ *:[i32] }):$offset, (extract_cpol:{ *:[i32] } ?:{ *:[i32] }:$auxiliary), (extract_swz:{ *:[i1] } ?:{ *:[i32] }:$auxiliary))
        GIR_MakeTempReg, /*TempRegID*/0, /*TypeID*/GILLT_s64,
        GIR_BuildMI, /*InsnID*/1, /*Opcode*/GIMT_Encode2(TargetOpcode::REG_SEQUENCE),
        GIR_AddTempRegister, /*InsnID*/1, /*TempRegID*/0, /*TempRegFlags*/GIMT_Encode2(RegState::Define),
        GIR_Copy, /*NewInsnID*/1, /*OldInsnID*/0, /*OpIdx*/2, // vindex
        GIR_AddImm8, /*InsnID*/1, /*SubRegIndex*/3,
        GIR_Copy, /*NewInsnID*/1, /*OldInsnID*/0, /*OpIdx*/3, // voffset
        GIR_AddImm8, /*InsnID*/1, /*SubRegIndex*/11,
        GIR_ConstrainOperandRC, /*InsnID*/1, /*Op*/0, GIMT_Encode2(AMDGPU::VReg_64RegClassID),
        GIR_ConstrainOperandRC, /*InsnID*/1, /*Op*/1, GIMT_Encode2(AMDGPU::VGPR_32RegClassID),
        GIR_ConstrainOperandRC, /*InsnID*/1, /*Op*/3, GIMT_Encode2(AMDGPU::VGPR_32RegClassID),
        GIR_BuildMI, /*InsnID*/0, /*Opcode*/GIMT_Encode2(AMDGPU::BUFFER_STORE_DWORDX3_BOTHEN_exact),
        GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/0, // vdata
        GIR_AddSimpleTempRegister, /*InsnID*/0, /*TempRegID*/0,
        GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/1, // rsrc
        GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/0, // soffset
        GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/5, // offset
        GIR_CustomOperandRenderer, /*InsnID*/0, /*OldInsnID*/0, /*OpIdx*/6, /*OperandRenderer*/GIMT_Encode2(GICR_renderExtractCPol), // auxiliary
        GIR_CustomOperandRenderer, /*InsnID*/0, /*OldInsnID*/0, /*OpIdx*/6, /*OperandRenderer*/GIMT_Encode2(GICR_renderExtractSWZ), // auxiliary
        GIR_MergeMemOperands, /*InsnID*/0, /*NumInsns*/1, /*MergeInsnID's*/0,
        GIR_ConstrainSelectedInstOperands, /*InsnID*/0,
        GIR_EraseFromParent, /*InsnID*/0,
        // GIR_Coverage, 4460,
        GIR_Done,
      // Label 6844: @502625
      GIM_Try, /*On fail goto*//*Label 6845*/ GIMT_Encode4(502732), // Rule ID 4464 //
        // MIs[0] offset
        GIM_CheckIsImm, /*MI*/0, /*Op*/5,
        // MIs[0] auxiliary
        GIM_CheckIsImm, /*MI*/0, /*Op*/6,
        // MIs[0] Operand 7
        GIM_CheckIsImm, /*MI*/0, /*Op*/7,
        GIM_CheckComplexPattern, /*MI*/0, /*Op*/4, /*Renderer*/GIMT_Encode2(0), GIMT_Encode2(GICP_gi_buf_soffset),
        // (SIbuffer_store v3f32:{ *:[v3f32] }:$vdata, v4i32:{ *:[v4i32] }:$rsrc, i32:{ *:[i32] }:$vindex, i32:{ *:[i32] }:$voffset, (BUFSOffset:{ *:[i32] } i32:{ *:[i32] }:$soffset), (timm:{ *:[i32] }):$offset, (timm:{ *:[i32] }):$auxiliary, (timm:{ *:[i1] }))  =>  (BUFFER_STORE_DWORDX3_VBUFFER_BOTHEN_exact anonymous_15035:{ *:[v3f32] }:$vdata, (REG_SEQUENCE:{ *:[i64] } VReg_64:{ *:[i32] }, VGPR_32:{ *:[i32] }:$vindex, sub0:{ *:[i32] }, VGPR_32:{ *:[i32] }:$voffset, sub1:{ *:[i32] }), SReg_128:{ *:[v4i32] }:$rsrc, SCSrc_b32:{ *:[i32] }:$soffset, (timm:{ *:[i32] }):$offset, (extract_cpol:{ *:[i32] } ?:{ *:[i32] }:$auxiliary), (extract_swz:{ *:[i1] } ?:{ *:[i32] }:$auxiliary))
        GIR_MakeTempReg, /*TempRegID*/0, /*TypeID*/GILLT_s64,
        GIR_BuildMI, /*InsnID*/1, /*Opcode*/GIMT_Encode2(TargetOpcode::REG_SEQUENCE),
        GIR_AddTempRegister, /*InsnID*/1, /*TempRegID*/0, /*TempRegFlags*/GIMT_Encode2(RegState::Define),
        GIR_Copy, /*NewInsnID*/1, /*OldInsnID*/0, /*OpIdx*/2, // vindex
        GIR_AddImm8, /*InsnID*/1, /*SubRegIndex*/3,
        GIR_Copy, /*NewInsnID*/1, /*OldInsnID*/0, /*OpIdx*/3, // voffset
        GIR_AddImm8, /*InsnID*/1, /*SubRegIndex*/11,
        GIR_ConstrainOperandRC, /*InsnID*/1, /*Op*/0, GIMT_Encode2(AMDGPU::VReg_64RegClassID),
        GIR_ConstrainOperandRC, /*InsnID*/1, /*Op*/1, GIMT_Encode2(AMDGPU::VGPR_32RegClassID),
        GIR_ConstrainOperandRC, /*InsnID*/1, /*Op*/3, GIMT_Encode2(AMDGPU::VGPR_32RegClassID),
        GIR_BuildMI, /*InsnID*/0, /*Opcode*/GIMT_Encode2(AMDGPU::BUFFER_STORE_DWORDX3_VBUFFER_BOTHEN_exact),
        GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/0, // vdata
        GIR_AddSimpleTempRegister, /*InsnID*/0, /*TempRegID*/0,
        GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/1, // rsrc
        GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/0, // soffset
        GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/5, // offset
        GIR_CustomOperandRenderer, /*InsnID*/0, /*OldInsnID*/0, /*OpIdx*/6, /*OperandRenderer*/GIMT_Encode2(GICR_renderExtractCPol), // auxiliary
        GIR_CustomOperandRenderer, /*InsnID*/0, /*OldInsnID*/0, /*OpIdx*/6, /*OperandRenderer*/GIMT_Encode2(GICR_renderExtractSWZ), // auxiliary
        GIR_MergeMemOperands, /*InsnID*/0, /*NumInsns*/1, /*MergeInsnID's*/0,
        GIR_ConstrainSelectedInstOperands, /*InsnID*/0,
        GIR_EraseFromParent, /*InsnID*/0,
        // GIR_Coverage, 4464,
        GIR_Done,
      // Label 6845: @502732
      GIM_Try, /*On fail goto*//*Label 6846*/ GIMT_Encode4(502842), // Rule ID 4468 //
        GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasUnrestrictedSOffset),
        // MIs[0] offset
        GIM_CheckIsImm, /*MI*/0, /*Op*/5,
        // MIs[0] auxiliary
        GIM_CheckIsImm, /*MI*/0, /*Op*/6,
        // MIs[0] Operand 7
        GIM_CheckIsImm, /*MI*/0, /*Op*/7,
        GIM_CheckComplexPattern, /*MI*/0, /*Op*/4, /*Renderer*/GIMT_Encode2(0), GIMT_Encode2(GICP_gi_buf_soffset),
        // (SIbuffer_store v3i32:{ *:[v3i32] }:$vdata, v4i32:{ *:[v4i32] }:$rsrc, i32:{ *:[i32] }:$vindex, i32:{ *:[i32] }:$voffset, (BUFSOffset:{ *:[i32] } i32:{ *:[i32] }:$soffset), (timm:{ *:[i32] }):$offset, (timm:{ *:[i32] }):$auxiliary, (timm:{ *:[i1] }))  =>  (BUFFER_STORE_DWORDX3_BOTHEN_exact anonymous_15035:{ *:[v3i32] }:$vdata, (REG_SEQUENCE:{ *:[i64] } VReg_64:{ *:[i32] }, VGPR_32:{ *:[i32] }:$vindex, sub0:{ *:[i32] }, VGPR_32:{ *:[i32] }:$voffset, sub1:{ *:[i32] }), SReg_128:{ *:[v4i32] }:$rsrc, SCSrc_b32:{ *:[i32] }:$soffset, (timm:{ *:[i32] }):$offset, (extract_cpol:{ *:[i32] } ?:{ *:[i32] }:$auxiliary), (extract_swz:{ *:[i1] } ?:{ *:[i32] }:$auxiliary))
        GIR_MakeTempReg, /*TempRegID*/0, /*TypeID*/GILLT_s64,
        GIR_BuildMI, /*InsnID*/1, /*Opcode*/GIMT_Encode2(TargetOpcode::REG_SEQUENCE),
        GIR_AddTempRegister, /*InsnID*/1, /*TempRegID*/0, /*TempRegFlags*/GIMT_Encode2(RegState::Define),
        GIR_Copy, /*NewInsnID*/1, /*OldInsnID*/0, /*OpIdx*/2, // vindex
        GIR_AddImm8, /*InsnID*/1, /*SubRegIndex*/3,
        GIR_Copy, /*NewInsnID*/1, /*OldInsnID*/0, /*OpIdx*/3, // voffset
        GIR_AddImm8, /*InsnID*/1, /*SubRegIndex*/11,
        GIR_ConstrainOperandRC, /*InsnID*/1, /*Op*/0, GIMT_Encode2(AMDGPU::VReg_64RegClassID),
        GIR_ConstrainOperandRC, /*InsnID*/1, /*Op*/1, GIMT_Encode2(AMDGPU::VGPR_32RegClassID),
        GIR_ConstrainOperandRC, /*InsnID*/1, /*Op*/3, GIMT_Encode2(AMDGPU::VGPR_32RegClassID),
        GIR_BuildMI, /*InsnID*/0, /*Opcode*/GIMT_Encode2(AMDGPU::BUFFER_STORE_DWORDX3_BOTHEN_exact),
        GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/0, // vdata
        GIR_AddSimpleTempRegister, /*InsnID*/0, /*TempRegID*/0,
        GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/1, // rsrc
        GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/0, // soffset
        GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/5, // offset
        GIR_CustomOperandRenderer, /*InsnID*/0, /*OldInsnID*/0, /*OpIdx*/6, /*OperandRenderer*/GIMT_Encode2(GICR_renderExtractCPol), // auxiliary
        GIR_CustomOperandRenderer, /*InsnID*/0, /*OldInsnID*/0, /*OpIdx*/6, /*OperandRenderer*/GIMT_Encode2(GICR_renderExtractSWZ), // auxiliary
        GIR_MergeMemOperands, /*InsnID*/0, /*NumInsns*/1, /*MergeInsnID's*/0,
        GIR_ConstrainSelectedInstOperands, /*InsnID*/0,
        GIR_EraseFromParent, /*InsnID*/0,
        // GIR_Coverage, 4468,
        GIR_Done,
      // Label 6846: @502842
      GIM_Try, /*On fail goto*//*Label 6847*/ GIMT_Encode4(502949), // Rule ID 4472 //
        // MIs[0] offset
        GIM_CheckIsImm, /*MI*/0, /*Op*/5,
        // MIs[0] auxiliary
        GIM_CheckIsImm, /*MI*/0, /*Op*/6,
        // MIs[0] Operand 7
        GIM_CheckIsImm, /*MI*/0, /*Op*/7,
        GIM_CheckComplexPattern, /*MI*/0, /*Op*/4, /*Renderer*/GIMT_Encode2(0), GIMT_Encode2(GICP_gi_buf_soffset),
        // (SIbuffer_store v3i32:{ *:[v3i32] }:$vdata, v4i32:{ *:[v4i32] }:$rsrc, i32:{ *:[i32] }:$vindex, i32:{ *:[i32] }:$voffset, (BUFSOffset:{ *:[i32] } i32:{ *:[i32] }:$soffset), (timm:{ *:[i32] }):$offset, (timm:{ *:[i32] }):$auxiliary, (timm:{ *:[i1] }))  =>  (BUFFER_STORE_DWORDX3_VBUFFER_BOTHEN_exact anonymous_15035:{ *:[v3i32] }:$vdata, (REG_SEQUENCE:{ *:[i64] } VReg_64:{ *:[i32] }, VGPR_32:{ *:[i32] }:$vindex, sub0:{ *:[i32] }, VGPR_32:{ *:[i32] }:$voffset, sub1:{ *:[i32] }), SReg_128:{ *:[v4i32] }:$rsrc, SCSrc_b32:{ *:[i32] }:$soffset, (timm:{ *:[i32] }):$offset, (extract_cpol:{ *:[i32] } ?:{ *:[i32] }:$auxiliary), (extract_swz:{ *:[i1] } ?:{ *:[i32] }:$auxiliary))
        GIR_MakeTempReg, /*TempRegID*/0, /*TypeID*/GILLT_s64,
        GIR_BuildMI, /*InsnID*/1, /*Opcode*/GIMT_Encode2(TargetOpcode::REG_SEQUENCE),
        GIR_AddTempRegister, /*InsnID*/1, /*TempRegID*/0, /*TempRegFlags*/GIMT_Encode2(RegState::Define),
        GIR_Copy, /*NewInsnID*/1, /*OldInsnID*/0, /*OpIdx*/2, // vindex
        GIR_AddImm8, /*InsnID*/1, /*SubRegIndex*/3,
        GIR_Copy, /*NewInsnID*/1, /*OldInsnID*/0, /*OpIdx*/3, // voffset
        GIR_AddImm8, /*InsnID*/1, /*SubRegIndex*/11,
        GIR_ConstrainOperandRC, /*InsnID*/1, /*Op*/0, GIMT_Encode2(AMDGPU::VReg_64RegClassID),
        GIR_ConstrainOperandRC, /*InsnID*/1, /*Op*/1, GIMT_Encode2(AMDGPU::VGPR_32RegClassID),
        GIR_ConstrainOperandRC, /*InsnID*/1, /*Op*/3, GIMT_Encode2(AMDGPU::VGPR_32RegClassID),
        GIR_BuildMI, /*InsnID*/0, /*Opcode*/GIMT_Encode2(AMDGPU::BUFFER_STORE_DWORDX3_VBUFFER_BOTHEN_exact),
        GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/0, // vdata
        GIR_AddSimpleTempRegister, /*InsnID*/0, /*TempRegID*/0,
        GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/1, // rsrc
        GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/0, // soffset
        GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/5, // offset
        GIR_CustomOperandRenderer, /*InsnID*/0, /*OldInsnID*/0, /*OpIdx*/6, /*OperandRenderer*/GIMT_Encode2(GICR_renderExtractCPol), // auxiliary
        GIR_CustomOperandRenderer, /*InsnID*/0, /*OldInsnID*/0, /*OpIdx*/6, /*OperandRenderer*/GIMT_Encode2(GICR_renderExtractSWZ), // auxiliary
        GIR_MergeMemOperands, /*InsnID*/0, /*NumInsns*/1, /*MergeInsnID's*/0,
        GIR_ConstrainSelectedInstOperands, /*InsnID*/0,
        GIR_EraseFromParent, /*InsnID*/0,
        // GIR_Coverage, 4472,
        GIR_Done,
      // Label 6847: @502949
      GIM_Reject,
    // Label 6831: @502950
    GIM_Reject,
    // Label 6777: @502951
    GIM_Try, /*On fail goto*//*Label 6848*/ GIMT_Encode4(504341),
      GIM_CheckType, /*MI*/0, /*Op*/1, /*Type*/GILLT_v4s32,
      GIM_CheckType, /*MI*/0, /*Op*/2, /*Type*/GILLT_s32,
      GIM_CheckType, /*MI*/0, /*Op*/3, /*Type*/GILLT_s32,
      GIM_CheckType, /*MI*/0, /*Op*/4, /*Type*/GILLT_s32,
      GIM_Try, /*On fail goto*//*Label 6849*/ GIMT_Encode4(503054), // Rule ID 4441 //
        GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasUnrestrictedSOffset),
        GIM_CheckConstantInt8, /*MI*/0, /*Op*/2, 0,
        GIM_CheckConstantInt8, /*MI*/0, /*Op*/3, 0,
        // MIs[0] offset
        GIM_CheckIsImm, /*MI*/0, /*Op*/5,
        // MIs[0] auxiliary
        GIM_CheckIsImm, /*MI*/0, /*Op*/6,
        // MIs[0] Operand 7
        GIM_CheckLiteralInt, /*MI*/0, /*Op*/7, GIMT_Encode8(0),
        GIM_CheckComplexPattern, /*MI*/0, /*Op*/4, /*Renderer*/GIMT_Encode2(0), GIMT_Encode2(GICP_gi_buf_soffset),
        // (SIbuffer_store v4i16:{ *:[v4i16] }:$vdata, v4i32:{ *:[v4i32] }:$rsrc, 0:{ *:[i32] }, 0:{ *:[i32] }, (BUFSOffset:{ *:[i32] } i32:{ *:[i32] }:$soffset), (timm:{ *:[i32] }):$offset, (timm:{ *:[i32] }):$auxiliary, 0:{ *:[i1] })  =>  (BUFFER_STORE_DWORDX2_OFFSET_exact anonymous_15036:{ *:[v4i16] }:$vdata, SReg_128:{ *:[v4i32] }:$rsrc, SCSrc_b32:{ *:[i32] }:$soffset, (timm:{ *:[i32] }):$offset, (extract_cpol:{ *:[i32] } ?:{ *:[i32] }:$auxiliary), (extract_swz:{ *:[i1] } ?:{ *:[i32] }:$auxiliary))
        GIR_BuildMI, /*InsnID*/0, /*Opcode*/GIMT_Encode2(AMDGPU::BUFFER_STORE_DWORDX2_OFFSET_exact),
        GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/0, // vdata
        GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/1, // rsrc
        GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/0, // soffset
        GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/5, // offset
        GIR_CustomOperandRenderer, /*InsnID*/0, /*OldInsnID*/0, /*OpIdx*/6, /*OperandRenderer*/GIMT_Encode2(GICR_renderExtractCPol), // auxiliary
        GIR_CustomOperandRenderer, /*InsnID*/0, /*OldInsnID*/0, /*OpIdx*/6, /*OperandRenderer*/GIMT_Encode2(GICR_renderExtractSWZ), // auxiliary
        GIR_MergeMemOperands, /*InsnID*/0, /*NumInsns*/1, /*MergeInsnID's*/0,
        GIR_ConstrainSelectedInstOperands, /*InsnID*/0,
        GIR_EraseFromParent, /*InsnID*/0,
        // GIR_Coverage, 4441,
        GIR_Done,
      // Label 6849: @503054
      GIM_Try, /*On fail goto*//*Label 6850*/ GIMT_Encode4(503133), // Rule ID 4445 //
        GIM_CheckConstantInt8, /*MI*/0, /*Op*/2, 0,
        GIM_CheckConstantInt8, /*MI*/0, /*Op*/3, 0,
        // MIs[0] offset
        GIM_CheckIsImm, /*MI*/0, /*Op*/5,
        // MIs[0] auxiliary
        GIM_CheckIsImm, /*MI*/0, /*Op*/6,
        // MIs[0] Operand 7
        GIM_CheckLiteralInt, /*MI*/0, /*Op*/7, GIMT_Encode8(0),
        GIM_CheckComplexPattern, /*MI*/0, /*Op*/4, /*Renderer*/GIMT_Encode2(0), GIMT_Encode2(GICP_gi_buf_soffset),
        // (SIbuffer_store v4i16:{ *:[v4i16] }:$vdata, v4i32:{ *:[v4i32] }:$rsrc, 0:{ *:[i32] }, 0:{ *:[i32] }, (BUFSOffset:{ *:[i32] } i32:{ *:[i32] }:$soffset), (timm:{ *:[i32] }):$offset, (timm:{ *:[i32] }):$auxiliary, 0:{ *:[i1] })  =>  (BUFFER_STORE_DWORDX2_VBUFFER_OFFSET_exact anonymous_15036:{ *:[v4i16] }:$vdata, SReg_128:{ *:[v4i32] }:$rsrc, SCSrc_b32:{ *:[i32] }:$soffset, (timm:{ *:[i32] }):$offset, (extract_cpol:{ *:[i32] } ?:{ *:[i32] }:$auxiliary), (extract_swz:{ *:[i1] } ?:{ *:[i32] }:$auxiliary))
        GIR_BuildMI, /*InsnID*/0, /*Opcode*/GIMT_Encode2(AMDGPU::BUFFER_STORE_DWORDX2_VBUFFER_OFFSET_exact),
        GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/0, // vdata
        GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/1, // rsrc
        GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/0, // soffset
        GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/5, // offset
        GIR_CustomOperandRenderer, /*InsnID*/0, /*OldInsnID*/0, /*OpIdx*/6, /*OperandRenderer*/GIMT_Encode2(GICR_renderExtractCPol), // auxiliary
        GIR_CustomOperandRenderer, /*InsnID*/0, /*OldInsnID*/0, /*OpIdx*/6, /*OperandRenderer*/GIMT_Encode2(GICR_renderExtractSWZ), // auxiliary
        GIR_MergeMemOperands, /*InsnID*/0, /*NumInsns*/1, /*MergeInsnID's*/0,
        GIR_ConstrainSelectedInstOperands, /*InsnID*/0,
        GIR_EraseFromParent, /*InsnID*/0,
        // GIR_Coverage, 4445,
        GIR_Done,
      // Label 6850: @503133
      GIM_Try, /*On fail goto*//*Label 6851*/ GIMT_Encode4(503215), // Rule ID 4449 //
        GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasUnrestrictedSOffset),
        GIM_CheckConstantInt8, /*MI*/0, /*Op*/2, 0,
        GIM_CheckConstantInt8, /*MI*/0, /*Op*/3, 0,
        // MIs[0] offset
        GIM_CheckIsImm, /*MI*/0, /*Op*/5,
        // MIs[0] auxiliary
        GIM_CheckIsImm, /*MI*/0, /*Op*/6,
        // MIs[0] Operand 7
        GIM_CheckLiteralInt, /*MI*/0, /*Op*/7, GIMT_Encode8(0),
        GIM_CheckComplexPattern, /*MI*/0, /*Op*/4, /*Renderer*/GIMT_Encode2(0), GIMT_Encode2(GICP_gi_buf_soffset),
        // (SIbuffer_store v4f16:{ *:[v4f16] }:$vdata, v4i32:{ *:[v4i32] }:$rsrc, 0:{ *:[i32] }, 0:{ *:[i32] }, (BUFSOffset:{ *:[i32] } i32:{ *:[i32] }:$soffset), (timm:{ *:[i32] }):$offset, (timm:{ *:[i32] }):$auxiliary, 0:{ *:[i1] })  =>  (BUFFER_STORE_DWORDX2_OFFSET_exact anonymous_15036:{ *:[v4f16] }:$vdata, SReg_128:{ *:[v4i32] }:$rsrc, SCSrc_b32:{ *:[i32] }:$soffset, (timm:{ *:[i32] }):$offset, (extract_cpol:{ *:[i32] } ?:{ *:[i32] }:$auxiliary), (extract_swz:{ *:[i1] } ?:{ *:[i32] }:$auxiliary))
        GIR_BuildMI, /*InsnID*/0, /*Opcode*/GIMT_Encode2(AMDGPU::BUFFER_STORE_DWORDX2_OFFSET_exact),
        GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/0, // vdata
        GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/1, // rsrc
        GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/0, // soffset
        GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/5, // offset
        GIR_CustomOperandRenderer, /*InsnID*/0, /*OldInsnID*/0, /*OpIdx*/6, /*OperandRenderer*/GIMT_Encode2(GICR_renderExtractCPol), // auxiliary
        GIR_CustomOperandRenderer, /*InsnID*/0, /*OldInsnID*/0, /*OpIdx*/6, /*OperandRenderer*/GIMT_Encode2(GICR_renderExtractSWZ), // auxiliary
        GIR_MergeMemOperands, /*InsnID*/0, /*NumInsns*/1, /*MergeInsnID's*/0,
        GIR_ConstrainSelectedInstOperands, /*InsnID*/0,
        GIR_EraseFromParent, /*InsnID*/0,
        // GIR_Coverage, 4449,
        GIR_Done,
      // Label 6851: @503215
      GIM_Try, /*On fail goto*//*Label 6852*/ GIMT_Encode4(503294), // Rule ID 4453 //
        GIM_CheckConstantInt8, /*MI*/0, /*Op*/2, 0,
        GIM_CheckConstantInt8, /*MI*/0, /*Op*/3, 0,
        // MIs[0] offset
        GIM_CheckIsImm, /*MI*/0, /*Op*/5,
        // MIs[0] auxiliary
        GIM_CheckIsImm, /*MI*/0, /*Op*/6,
        // MIs[0] Operand 7
        GIM_CheckLiteralInt, /*MI*/0, /*Op*/7, GIMT_Encode8(0),
        GIM_CheckComplexPattern, /*MI*/0, /*Op*/4, /*Renderer*/GIMT_Encode2(0), GIMT_Encode2(GICP_gi_buf_soffset),
        // (SIbuffer_store v4f16:{ *:[v4f16] }:$vdata, v4i32:{ *:[v4i32] }:$rsrc, 0:{ *:[i32] }, 0:{ *:[i32] }, (BUFSOffset:{ *:[i32] } i32:{ *:[i32] }:$soffset), (timm:{ *:[i32] }):$offset, (timm:{ *:[i32] }):$auxiliary, 0:{ *:[i1] })  =>  (BUFFER_STORE_DWORDX2_VBUFFER_OFFSET_exact anonymous_15036:{ *:[v4f16] }:$vdata, SReg_128:{ *:[v4i32] }:$rsrc, SCSrc_b32:{ *:[i32] }:$soffset, (timm:{ *:[i32] }):$offset, (extract_cpol:{ *:[i32] } ?:{ *:[i32] }:$auxiliary), (extract_swz:{ *:[i1] } ?:{ *:[i32] }:$auxiliary))
        GIR_BuildMI, /*InsnID*/0, /*Opcode*/GIMT_Encode2(AMDGPU::BUFFER_STORE_DWORDX2_VBUFFER_OFFSET_exact),
        GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/0, // vdata
        GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/1, // rsrc
        GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/0, // soffset
        GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/5, // offset
        GIR_CustomOperandRenderer, /*InsnID*/0, /*OldInsnID*/0, /*OpIdx*/6, /*OperandRenderer*/GIMT_Encode2(GICR_renderExtractCPol), // auxiliary
        GIR_CustomOperandRenderer, /*InsnID*/0, /*OldInsnID*/0, /*OpIdx*/6, /*OperandRenderer*/GIMT_Encode2(GICR_renderExtractSWZ), // auxiliary
        GIR_MergeMemOperands, /*InsnID*/0, /*NumInsns*/1, /*MergeInsnID's*/0,
        GIR_ConstrainSelectedInstOperands, /*InsnID*/0,
        GIR_EraseFromParent, /*InsnID*/0,
        // GIR_Coverage, 4453,
        GIR_Done,
      // Label 6852: @503294
      GIM_Try, /*On fail goto*//*Label 6853*/ GIMT_Encode4(503376), // Rule ID 4442 //
        GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasUnrestrictedSOffset),
        GIM_CheckConstantInt8, /*MI*/0, /*Op*/2, 0,
        // MIs[0] offset
        GIM_CheckIsImm, /*MI*/0, /*Op*/5,
        // MIs[0] auxiliary
        GIM_CheckIsImm, /*MI*/0, /*Op*/6,
        // MIs[0] Operand 7
        GIM_CheckLiteralInt, /*MI*/0, /*Op*/7, GIMT_Encode8(0),
        GIM_CheckComplexPattern, /*MI*/0, /*Op*/4, /*Renderer*/GIMT_Encode2(0), GIMT_Encode2(GICP_gi_buf_soffset),
        // (SIbuffer_store v4i16:{ *:[v4i16] }:$vdata, v4i32:{ *:[v4i32] }:$rsrc, 0:{ *:[i32] }, i32:{ *:[i32] }:$voffset, (BUFSOffset:{ *:[i32] } i32:{ *:[i32] }:$soffset), (timm:{ *:[i32] }):$offset, (timm:{ *:[i32] }):$auxiliary, 0:{ *:[i1] })  =>  (BUFFER_STORE_DWORDX2_OFFEN_exact anonymous_15036:{ *:[v4i16] }:$vdata, VGPR_32:{ *:[i32] }:$voffset, SReg_128:{ *:[v4i32] }:$rsrc, SCSrc_b32:{ *:[i32] }:$soffset, (timm:{ *:[i32] }):$offset, (extract_cpol:{ *:[i32] } ?:{ *:[i32] }:$auxiliary), (extract_swz:{ *:[i1] } ?:{ *:[i32] }:$auxiliary))
        GIR_BuildMI, /*InsnID*/0, /*Opcode*/GIMT_Encode2(AMDGPU::BUFFER_STORE_DWORDX2_OFFEN_exact),
        GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/0, // vdata
        GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/3, // voffset
        GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/1, // rsrc
        GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/0, // soffset
        GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/5, // offset
        GIR_CustomOperandRenderer, /*InsnID*/0, /*OldInsnID*/0, /*OpIdx*/6, /*OperandRenderer*/GIMT_Encode2(GICR_renderExtractCPol), // auxiliary
        GIR_CustomOperandRenderer, /*InsnID*/0, /*OldInsnID*/0, /*OpIdx*/6, /*OperandRenderer*/GIMT_Encode2(GICR_renderExtractSWZ), // auxiliary
        GIR_MergeMemOperands, /*InsnID*/0, /*NumInsns*/1, /*MergeInsnID's*/0,
        GIR_ConstrainSelectedInstOperands, /*InsnID*/0,
        GIR_EraseFromParent, /*InsnID*/0,
        // GIR_Coverage, 4442,
        GIR_Done,
      // Label 6853: @503376
      GIM_Try, /*On fail goto*//*Label 6854*/ GIMT_Encode4(503455), // Rule ID 4446 //
        GIM_CheckConstantInt8, /*MI*/0, /*Op*/2, 0,
        // MIs[0] offset
        GIM_CheckIsImm, /*MI*/0, /*Op*/5,
        // MIs[0] auxiliary
        GIM_CheckIsImm, /*MI*/0, /*Op*/6,
        // MIs[0] Operand 7
        GIM_CheckLiteralInt, /*MI*/0, /*Op*/7, GIMT_Encode8(0),
        GIM_CheckComplexPattern, /*MI*/0, /*Op*/4, /*Renderer*/GIMT_Encode2(0), GIMT_Encode2(GICP_gi_buf_soffset),
        // (SIbuffer_store v4i16:{ *:[v4i16] }:$vdata, v4i32:{ *:[v4i32] }:$rsrc, 0:{ *:[i32] }, i32:{ *:[i32] }:$voffset, (BUFSOffset:{ *:[i32] } i32:{ *:[i32] }:$soffset), (timm:{ *:[i32] }):$offset, (timm:{ *:[i32] }):$auxiliary, 0:{ *:[i1] })  =>  (BUFFER_STORE_DWORDX2_VBUFFER_OFFEN_exact anonymous_15036:{ *:[v4i16] }:$vdata, VGPR_32:{ *:[i32] }:$voffset, SReg_128:{ *:[v4i32] }:$rsrc, SCSrc_b32:{ *:[i32] }:$soffset, (timm:{ *:[i32] }):$offset, (extract_cpol:{ *:[i32] } ?:{ *:[i32] }:$auxiliary), (extract_swz:{ *:[i1] } ?:{ *:[i32] }:$auxiliary))
        GIR_BuildMI, /*InsnID*/0, /*Opcode*/GIMT_Encode2(AMDGPU::BUFFER_STORE_DWORDX2_VBUFFER_OFFEN_exact),
        GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/0, // vdata
        GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/3, // voffset
        GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/1, // rsrc
        GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/0, // soffset
        GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/5, // offset
        GIR_CustomOperandRenderer, /*InsnID*/0, /*OldInsnID*/0, /*OpIdx*/6, /*OperandRenderer*/GIMT_Encode2(GICR_renderExtractCPol), // auxiliary
        GIR_CustomOperandRenderer, /*InsnID*/0, /*OldInsnID*/0, /*OpIdx*/6, /*OperandRenderer*/GIMT_Encode2(GICR_renderExtractSWZ), // auxiliary
        GIR_MergeMemOperands, /*InsnID*/0, /*NumInsns*/1, /*MergeInsnID's*/0,
        GIR_ConstrainSelectedInstOperands, /*InsnID*/0,
        GIR_EraseFromParent, /*InsnID*/0,
        // GIR_Coverage, 4446,
        GIR_Done,
      // Label 6854: @503455
      GIM_Try, /*On fail goto*//*Label 6855*/ GIMT_Encode4(503537), // Rule ID 4450 //
        GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasUnrestrictedSOffset),
        GIM_CheckConstantInt8, /*MI*/0, /*Op*/2, 0,
        // MIs[0] offset
        GIM_CheckIsImm, /*MI*/0, /*Op*/5,
        // MIs[0] auxiliary
        GIM_CheckIsImm, /*MI*/0, /*Op*/6,
        // MIs[0] Operand 7
        GIM_CheckLiteralInt, /*MI*/0, /*Op*/7, GIMT_Encode8(0),
        GIM_CheckComplexPattern, /*MI*/0, /*Op*/4, /*Renderer*/GIMT_Encode2(0), GIMT_Encode2(GICP_gi_buf_soffset),
        // (SIbuffer_store v4f16:{ *:[v4f16] }:$vdata, v4i32:{ *:[v4i32] }:$rsrc, 0:{ *:[i32] }, i32:{ *:[i32] }:$voffset, (BUFSOffset:{ *:[i32] } i32:{ *:[i32] }:$soffset), (timm:{ *:[i32] }):$offset, (timm:{ *:[i32] }):$auxiliary, 0:{ *:[i1] })  =>  (BUFFER_STORE_DWORDX2_OFFEN_exact anonymous_15036:{ *:[v4f16] }:$vdata, VGPR_32:{ *:[i32] }:$voffset, SReg_128:{ *:[v4i32] }:$rsrc, SCSrc_b32:{ *:[i32] }:$soffset, (timm:{ *:[i32] }):$offset, (extract_cpol:{ *:[i32] } ?:{ *:[i32] }:$auxiliary), (extract_swz:{ *:[i1] } ?:{ *:[i32] }:$auxiliary))
        GIR_BuildMI, /*InsnID*/0, /*Opcode*/GIMT_Encode2(AMDGPU::BUFFER_STORE_DWORDX2_OFFEN_exact),
        GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/0, // vdata
        GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/3, // voffset
        GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/1, // rsrc
        GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/0, // soffset
        GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/5, // offset
        GIR_CustomOperandRenderer, /*InsnID*/0, /*OldInsnID*/0, /*OpIdx*/6, /*OperandRenderer*/GIMT_Encode2(GICR_renderExtractCPol), // auxiliary
        GIR_CustomOperandRenderer, /*InsnID*/0, /*OldInsnID*/0, /*OpIdx*/6, /*OperandRenderer*/GIMT_Encode2(GICR_renderExtractSWZ), // auxiliary
        GIR_MergeMemOperands, /*InsnID*/0, /*NumInsns*/1, /*MergeInsnID's*/0,
        GIR_ConstrainSelectedInstOperands, /*InsnID*/0,
        GIR_EraseFromParent, /*InsnID*/0,
        // GIR_Coverage, 4450,
        GIR_Done,
      // Label 6855: @503537
      GIM_Try, /*On fail goto*//*Label 6856*/ GIMT_Encode4(503616), // Rule ID 4454 //
        GIM_CheckConstantInt8, /*MI*/0, /*Op*/2, 0,
        // MIs[0] offset
        GIM_CheckIsImm, /*MI*/0, /*Op*/5,
        // MIs[0] auxiliary
        GIM_CheckIsImm, /*MI*/0, /*Op*/6,
        // MIs[0] Operand 7
        GIM_CheckLiteralInt, /*MI*/0, /*Op*/7, GIMT_Encode8(0),
        GIM_CheckComplexPattern, /*MI*/0, /*Op*/4, /*Renderer*/GIMT_Encode2(0), GIMT_Encode2(GICP_gi_buf_soffset),
        // (SIbuffer_store v4f16:{ *:[v4f16] }:$vdata, v4i32:{ *:[v4i32] }:$rsrc, 0:{ *:[i32] }, i32:{ *:[i32] }:$voffset, (BUFSOffset:{ *:[i32] } i32:{ *:[i32] }:$soffset), (timm:{ *:[i32] }):$offset, (timm:{ *:[i32] }):$auxiliary, 0:{ *:[i1] })  =>  (BUFFER_STORE_DWORDX2_VBUFFER_OFFEN_exact anonymous_15036:{ *:[v4f16] }:$vdata, VGPR_32:{ *:[i32] }:$voffset, SReg_128:{ *:[v4i32] }:$rsrc, SCSrc_b32:{ *:[i32] }:$soffset, (timm:{ *:[i32] }):$offset, (extract_cpol:{ *:[i32] } ?:{ *:[i32] }:$auxiliary), (extract_swz:{ *:[i1] } ?:{ *:[i32] }:$auxiliary))
        GIR_BuildMI, /*InsnID*/0, /*Opcode*/GIMT_Encode2(AMDGPU::BUFFER_STORE_DWORDX2_VBUFFER_OFFEN_exact),
        GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/0, // vdata
        GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/3, // voffset
        GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/1, // rsrc
        GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/0, // soffset
        GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/5, // offset
        GIR_CustomOperandRenderer, /*InsnID*/0, /*OldInsnID*/0, /*OpIdx*/6, /*OperandRenderer*/GIMT_Encode2(GICR_renderExtractCPol), // auxiliary
        GIR_CustomOperandRenderer, /*InsnID*/0, /*OldInsnID*/0, /*OpIdx*/6, /*OperandRenderer*/GIMT_Encode2(GICR_renderExtractSWZ), // auxiliary
        GIR_MergeMemOperands, /*InsnID*/0, /*NumInsns*/1, /*MergeInsnID's*/0,
        GIR_ConstrainSelectedInstOperands, /*InsnID*/0,
        GIR_EraseFromParent, /*InsnID*/0,
        // GIR_Coverage, 4454,
        GIR_Done,
      // Label 6856: @503616
      GIM_Try, /*On fail goto*//*Label 6857*/ GIMT_Encode4(503690), // Rule ID 4443 //
        GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasUnrestrictedSOffset),
        GIM_CheckConstantInt8, /*MI*/0, /*Op*/3, 0,
        // MIs[0] offset
        GIM_CheckIsImm, /*MI*/0, /*Op*/5,
        // MIs[0] auxiliary
        GIM_CheckIsImm, /*MI*/0, /*Op*/6,
        // MIs[0] Operand 7
        GIM_CheckIsImm, /*MI*/0, /*Op*/7,
        GIM_CheckComplexPattern, /*MI*/0, /*Op*/4, /*Renderer*/GIMT_Encode2(0), GIMT_Encode2(GICP_gi_buf_soffset),
        // (SIbuffer_store v4i16:{ *:[v4i16] }:$vdata, v4i32:{ *:[v4i32] }:$rsrc, i32:{ *:[i32] }:$vindex, 0:{ *:[i32] }, (BUFSOffset:{ *:[i32] } i32:{ *:[i32] }:$soffset), (timm:{ *:[i32] }):$offset, (timm:{ *:[i32] }):$auxiliary, (timm:{ *:[i1] }))  =>  (BUFFER_STORE_DWORDX2_IDXEN_exact anonymous_15036:{ *:[v4i16] }:$vdata, VGPR_32:{ *:[i32] }:$vindex, SReg_128:{ *:[v4i32] }:$rsrc, SCSrc_b32:{ *:[i32] }:$soffset, (timm:{ *:[i32] }):$offset, (extract_cpol:{ *:[i32] } ?:{ *:[i32] }:$auxiliary), (extract_swz:{ *:[i1] } ?:{ *:[i32] }:$auxiliary))
        GIR_BuildMI, /*InsnID*/0, /*Opcode*/GIMT_Encode2(AMDGPU::BUFFER_STORE_DWORDX2_IDXEN_exact),
        GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/0, // vdata
        GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/2, // vindex
        GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/1, // rsrc
        GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/0, // soffset
        GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/5, // offset
        GIR_CustomOperandRenderer, /*InsnID*/0, /*OldInsnID*/0, /*OpIdx*/6, /*OperandRenderer*/GIMT_Encode2(GICR_renderExtractCPol), // auxiliary
        GIR_CustomOperandRenderer, /*InsnID*/0, /*OldInsnID*/0, /*OpIdx*/6, /*OperandRenderer*/GIMT_Encode2(GICR_renderExtractSWZ), // auxiliary
        GIR_MergeMemOperands, /*InsnID*/0, /*NumInsns*/1, /*MergeInsnID's*/0,
        GIR_ConstrainSelectedInstOperands, /*InsnID*/0,
        GIR_EraseFromParent, /*InsnID*/0,
        // GIR_Coverage, 4443,
        GIR_Done,
      // Label 6857: @503690
      GIM_Try, /*On fail goto*//*Label 6858*/ GIMT_Encode4(503761), // Rule ID 4447 //
        GIM_CheckConstantInt8, /*MI*/0, /*Op*/3, 0,
        // MIs[0] offset
        GIM_CheckIsImm, /*MI*/0, /*Op*/5,
        // MIs[0] auxiliary
        GIM_CheckIsImm, /*MI*/0, /*Op*/6,
        // MIs[0] Operand 7
        GIM_CheckIsImm, /*MI*/0, /*Op*/7,
        GIM_CheckComplexPattern, /*MI*/0, /*Op*/4, /*Renderer*/GIMT_Encode2(0), GIMT_Encode2(GICP_gi_buf_soffset),
        // (SIbuffer_store v4i16:{ *:[v4i16] }:$vdata, v4i32:{ *:[v4i32] }:$rsrc, i32:{ *:[i32] }:$vindex, 0:{ *:[i32] }, (BUFSOffset:{ *:[i32] } i32:{ *:[i32] }:$soffset), (timm:{ *:[i32] }):$offset, (timm:{ *:[i32] }):$auxiliary, (timm:{ *:[i1] }))  =>  (BUFFER_STORE_DWORDX2_VBUFFER_IDXEN_exact anonymous_15036:{ *:[v4i16] }:$vdata, VGPR_32:{ *:[i32] }:$vindex, SReg_128:{ *:[v4i32] }:$rsrc, SCSrc_b32:{ *:[i32] }:$soffset, (timm:{ *:[i32] }):$offset, (extract_cpol:{ *:[i32] } ?:{ *:[i32] }:$auxiliary), (extract_swz:{ *:[i1] } ?:{ *:[i32] }:$auxiliary))
        GIR_BuildMI, /*InsnID*/0, /*Opcode*/GIMT_Encode2(AMDGPU::BUFFER_STORE_DWORDX2_VBUFFER_IDXEN_exact),
        GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/0, // vdata
        GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/2, // vindex
        GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/1, // rsrc
        GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/0, // soffset
        GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/5, // offset
        GIR_CustomOperandRenderer, /*InsnID*/0, /*OldInsnID*/0, /*OpIdx*/6, /*OperandRenderer*/GIMT_Encode2(GICR_renderExtractCPol), // auxiliary
        GIR_CustomOperandRenderer, /*InsnID*/0, /*OldInsnID*/0, /*OpIdx*/6, /*OperandRenderer*/GIMT_Encode2(GICR_renderExtractSWZ), // auxiliary
        GIR_MergeMemOperands, /*InsnID*/0, /*NumInsns*/1, /*MergeInsnID's*/0,
        GIR_ConstrainSelectedInstOperands, /*InsnID*/0,
        GIR_EraseFromParent, /*InsnID*/0,
        // GIR_Coverage, 4447,
        GIR_Done,
      // Label 6858: @503761
      GIM_Try, /*On fail goto*//*Label 6859*/ GIMT_Encode4(503835), // Rule ID 4451 //
        GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasUnrestrictedSOffset),
        GIM_CheckConstantInt8, /*MI*/0, /*Op*/3, 0,
        // MIs[0] offset
        GIM_CheckIsImm, /*MI*/0, /*Op*/5,
        // MIs[0] auxiliary
        GIM_CheckIsImm, /*MI*/0, /*Op*/6,
        // MIs[0] Operand 7
        GIM_CheckIsImm, /*MI*/0, /*Op*/7,
        GIM_CheckComplexPattern, /*MI*/0, /*Op*/4, /*Renderer*/GIMT_Encode2(0), GIMT_Encode2(GICP_gi_buf_soffset),
        // (SIbuffer_store v4f16:{ *:[v4f16] }:$vdata, v4i32:{ *:[v4i32] }:$rsrc, i32:{ *:[i32] }:$vindex, 0:{ *:[i32] }, (BUFSOffset:{ *:[i32] } i32:{ *:[i32] }:$soffset), (timm:{ *:[i32] }):$offset, (timm:{ *:[i32] }):$auxiliary, (timm:{ *:[i1] }))  =>  (BUFFER_STORE_DWORDX2_IDXEN_exact anonymous_15036:{ *:[v4f16] }:$vdata, VGPR_32:{ *:[i32] }:$vindex, SReg_128:{ *:[v4i32] }:$rsrc, SCSrc_b32:{ *:[i32] }:$soffset, (timm:{ *:[i32] }):$offset, (extract_cpol:{ *:[i32] } ?:{ *:[i32] }:$auxiliary), (extract_swz:{ *:[i1] } ?:{ *:[i32] }:$auxiliary))
        GIR_BuildMI, /*InsnID*/0, /*Opcode*/GIMT_Encode2(AMDGPU::BUFFER_STORE_DWORDX2_IDXEN_exact),
        GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/0, // vdata
        GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/2, // vindex
        GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/1, // rsrc
        GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/0, // soffset
        GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/5, // offset
        GIR_CustomOperandRenderer, /*InsnID*/0, /*OldInsnID*/0, /*OpIdx*/6, /*OperandRenderer*/GIMT_Encode2(GICR_renderExtractCPol), // auxiliary
        GIR_CustomOperandRenderer, /*InsnID*/0, /*OldInsnID*/0, /*OpIdx*/6, /*OperandRenderer*/GIMT_Encode2(GICR_renderExtractSWZ), // auxiliary
        GIR_MergeMemOperands, /*InsnID*/0, /*NumInsns*/1, /*MergeInsnID's*/0,
        GIR_ConstrainSelectedInstOperands, /*InsnID*/0,
        GIR_EraseFromParent, /*InsnID*/0,
        // GIR_Coverage, 4451,
        GIR_Done,
      // Label 6859: @503835
      GIM_Try, /*On fail goto*//*Label 6860*/ GIMT_Encode4(503906), // Rule ID 4455 //
        GIM_CheckConstantInt8, /*MI*/0, /*Op*/3, 0,
        // MIs[0] offset
        GIM_CheckIsImm, /*MI*/0, /*Op*/5,
        // MIs[0] auxiliary
        GIM_CheckIsImm, /*MI*/0, /*Op*/6,
        // MIs[0] Operand 7
        GIM_CheckIsImm, /*MI*/0, /*Op*/7,
        GIM_CheckComplexPattern, /*MI*/0, /*Op*/4, /*Renderer*/GIMT_Encode2(0), GIMT_Encode2(GICP_gi_buf_soffset),
        // (SIbuffer_store v4f16:{ *:[v4f16] }:$vdata, v4i32:{ *:[v4i32] }:$rsrc, i32:{ *:[i32] }:$vindex, 0:{ *:[i32] }, (BUFSOffset:{ *:[i32] } i32:{ *:[i32] }:$soffset), (timm:{ *:[i32] }):$offset, (timm:{ *:[i32] }):$auxiliary, (timm:{ *:[i1] }))  =>  (BUFFER_STORE_DWORDX2_VBUFFER_IDXEN_exact anonymous_15036:{ *:[v4f16] }:$vdata, VGPR_32:{ *:[i32] }:$vindex, SReg_128:{ *:[v4i32] }:$rsrc, SCSrc_b32:{ *:[i32] }:$soffset, (timm:{ *:[i32] }):$offset, (extract_cpol:{ *:[i32] } ?:{ *:[i32] }:$auxiliary), (extract_swz:{ *:[i1] } ?:{ *:[i32] }:$auxiliary))
        GIR_BuildMI, /*InsnID*/0, /*Opcode*/GIMT_Encode2(AMDGPU::BUFFER_STORE_DWORDX2_VBUFFER_IDXEN_exact),
        GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/0, // vdata
        GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/2, // vindex
        GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/1, // rsrc
        GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/0, // soffset
        GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/5, // offset
        GIR_CustomOperandRenderer, /*InsnID*/0, /*OldInsnID*/0, /*OpIdx*/6, /*OperandRenderer*/GIMT_Encode2(GICR_renderExtractCPol), // auxiliary
        GIR_CustomOperandRenderer, /*InsnID*/0, /*OldInsnID*/0, /*OpIdx*/6, /*OperandRenderer*/GIMT_Encode2(GICR_renderExtractSWZ), // auxiliary
        GIR_MergeMemOperands, /*InsnID*/0, /*NumInsns*/1, /*MergeInsnID's*/0,
        GIR_ConstrainSelectedInstOperands, /*InsnID*/0,
        GIR_EraseFromParent, /*InsnID*/0,
        // GIR_Coverage, 4455,
        GIR_Done,
      // Label 6860: @503906
      GIM_Try, /*On fail goto*//*Label 6861*/ GIMT_Encode4(504016), // Rule ID 4444 //
        GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasUnrestrictedSOffset),
        // MIs[0] offset
        GIM_CheckIsImm, /*MI*/0, /*Op*/5,
        // MIs[0] auxiliary
        GIM_CheckIsImm, /*MI*/0, /*Op*/6,
        // MIs[0] Operand 7
        GIM_CheckIsImm, /*MI*/0, /*Op*/7,
        GIM_CheckComplexPattern, /*MI*/0, /*Op*/4, /*Renderer*/GIMT_Encode2(0), GIMT_Encode2(GICP_gi_buf_soffset),
        // (SIbuffer_store v4i16:{ *:[v4i16] }:$vdata, v4i32:{ *:[v4i32] }:$rsrc, i32:{ *:[i32] }:$vindex, i32:{ *:[i32] }:$voffset, (BUFSOffset:{ *:[i32] } i32:{ *:[i32] }:$soffset), (timm:{ *:[i32] }):$offset, (timm:{ *:[i32] }):$auxiliary, (timm:{ *:[i1] }))  =>  (BUFFER_STORE_DWORDX2_BOTHEN_exact anonymous_15036:{ *:[v4i16] }:$vdata, (REG_SEQUENCE:{ *:[i64] } VReg_64:{ *:[i32] }, VGPR_32:{ *:[i32] }:$vindex, sub0:{ *:[i32] }, VGPR_32:{ *:[i32] }:$voffset, sub1:{ *:[i32] }), SReg_128:{ *:[v4i32] }:$rsrc, SCSrc_b32:{ *:[i32] }:$soffset, (timm:{ *:[i32] }):$offset, (extract_cpol:{ *:[i32] } ?:{ *:[i32] }:$auxiliary), (extract_swz:{ *:[i1] } ?:{ *:[i32] }:$auxiliary))
        GIR_MakeTempReg, /*TempRegID*/0, /*TypeID*/GILLT_s64,
        GIR_BuildMI, /*InsnID*/1, /*Opcode*/GIMT_Encode2(TargetOpcode::REG_SEQUENCE),
        GIR_AddTempRegister, /*InsnID*/1, /*TempRegID*/0, /*TempRegFlags*/GIMT_Encode2(RegState::Define),
        GIR_Copy, /*NewInsnID*/1, /*OldInsnID*/0, /*OpIdx*/2, // vindex
        GIR_AddImm8, /*InsnID*/1, /*SubRegIndex*/3,
        GIR_Copy, /*NewInsnID*/1, /*OldInsnID*/0, /*OpIdx*/3, // voffset
        GIR_AddImm8, /*InsnID*/1, /*SubRegIndex*/11,
        GIR_ConstrainOperandRC, /*InsnID*/1, /*Op*/0, GIMT_Encode2(AMDGPU::VReg_64RegClassID),
        GIR_ConstrainOperandRC, /*InsnID*/1, /*Op*/1, GIMT_Encode2(AMDGPU::VGPR_32RegClassID),
        GIR_ConstrainOperandRC, /*InsnID*/1, /*Op*/3, GIMT_Encode2(AMDGPU::VGPR_32RegClassID),
        GIR_BuildMI, /*InsnID*/0, /*Opcode*/GIMT_Encode2(AMDGPU::BUFFER_STORE_DWORDX2_BOTHEN_exact),
        GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/0, // vdata
        GIR_AddSimpleTempRegister, /*InsnID*/0, /*TempRegID*/0,
        GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/1, // rsrc
        GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/0, // soffset
        GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/5, // offset
        GIR_CustomOperandRenderer, /*InsnID*/0, /*OldInsnID*/0, /*OpIdx*/6, /*OperandRenderer*/GIMT_Encode2(GICR_renderExtractCPol), // auxiliary
        GIR_CustomOperandRenderer, /*InsnID*/0, /*OldInsnID*/0, /*OpIdx*/6, /*OperandRenderer*/GIMT_Encode2(GICR_renderExtractSWZ), // auxiliary
        GIR_MergeMemOperands, /*InsnID*/0, /*NumInsns*/1, /*MergeInsnID's*/0,
        GIR_ConstrainSelectedInstOperands, /*InsnID*/0,
        GIR_EraseFromParent, /*InsnID*/0,
        // GIR_Coverage, 4444,
        GIR_Done,
      // Label 6861: @504016
      GIM_Try, /*On fail goto*//*Label 6862*/ GIMT_Encode4(504123), // Rule ID 4448 //
        // MIs[0] offset
        GIM_CheckIsImm, /*MI*/0, /*Op*/5,
        // MIs[0] auxiliary
        GIM_CheckIsImm, /*MI*/0, /*Op*/6,
        // MIs[0] Operand 7
        GIM_CheckIsImm, /*MI*/0, /*Op*/7,
        GIM_CheckComplexPattern, /*MI*/0, /*Op*/4, /*Renderer*/GIMT_Encode2(0), GIMT_Encode2(GICP_gi_buf_soffset),
        // (SIbuffer_store v4i16:{ *:[v4i16] }:$vdata, v4i32:{ *:[v4i32] }:$rsrc, i32:{ *:[i32] }:$vindex, i32:{ *:[i32] }:$voffset, (BUFSOffset:{ *:[i32] } i32:{ *:[i32] }:$soffset), (timm:{ *:[i32] }):$offset, (timm:{ *:[i32] }):$auxiliary, (timm:{ *:[i1] }))  =>  (BUFFER_STORE_DWORDX2_VBUFFER_BOTHEN_exact anonymous_15036:{ *:[v4i16] }:$vdata, (REG_SEQUENCE:{ *:[i64] } VReg_64:{ *:[i32] }, VGPR_32:{ *:[i32] }:$vindex, sub0:{ *:[i32] }, VGPR_32:{ *:[i32] }:$voffset, sub1:{ *:[i32] }), SReg_128:{ *:[v4i32] }:$rsrc, SCSrc_b32:{ *:[i32] }:$soffset, (timm:{ *:[i32] }):$offset, (extract_cpol:{ *:[i32] } ?:{ *:[i32] }:$auxiliary), (extract_swz:{ *:[i1] } ?:{ *:[i32] }:$auxiliary))
        GIR_MakeTempReg, /*TempRegID*/0, /*TypeID*/GILLT_s64,
        GIR_BuildMI, /*InsnID*/1, /*Opcode*/GIMT_Encode2(TargetOpcode::REG_SEQUENCE),
        GIR_AddTempRegister, /*InsnID*/1, /*TempRegID*/0, /*TempRegFlags*/GIMT_Encode2(RegState::Define),
        GIR_Copy, /*NewInsnID*/1, /*OldInsnID*/0, /*OpIdx*/2, // vindex
        GIR_AddImm8, /*InsnID*/1, /*SubRegIndex*/3,
        GIR_Copy, /*NewInsnID*/1, /*OldInsnID*/0, /*OpIdx*/3, // voffset
        GIR_AddImm8, /*InsnID*/1, /*SubRegIndex*/11,
        GIR_ConstrainOperandRC, /*InsnID*/1, /*Op*/0, GIMT_Encode2(AMDGPU::VReg_64RegClassID),
        GIR_ConstrainOperandRC, /*InsnID*/1, /*Op*/1, GIMT_Encode2(AMDGPU::VGPR_32RegClassID),
        GIR_ConstrainOperandRC, /*InsnID*/1, /*Op*/3, GIMT_Encode2(AMDGPU::VGPR_32RegClassID),
        GIR_BuildMI, /*InsnID*/0, /*Opcode*/GIMT_Encode2(AMDGPU::BUFFER_STORE_DWORDX2_VBUFFER_BOTHEN_exact),
        GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/0, // vdata
        GIR_AddSimpleTempRegister, /*InsnID*/0, /*TempRegID*/0,
        GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/1, // rsrc
        GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/0, // soffset
        GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/5, // offset
        GIR_CustomOperandRenderer, /*InsnID*/0, /*OldInsnID*/0, /*OpIdx*/6, /*OperandRenderer*/GIMT_Encode2(GICR_renderExtractCPol), // auxiliary
        GIR_CustomOperandRenderer, /*InsnID*/0, /*OldInsnID*/0, /*OpIdx*/6, /*OperandRenderer*/GIMT_Encode2(GICR_renderExtractSWZ), // auxiliary
        GIR_MergeMemOperands, /*InsnID*/0, /*NumInsns*/1, /*MergeInsnID's*/0,
        GIR_ConstrainSelectedInstOperands, /*InsnID*/0,
        GIR_EraseFromParent, /*InsnID*/0,
        // GIR_Coverage, 4448,
        GIR_Done,
      // Label 6862: @504123
      GIM_Try, /*On fail goto*//*Label 6863*/ GIMT_Encode4(504233), // Rule ID 4452 //
        GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasUnrestrictedSOffset),
        // MIs[0] offset
        GIM_CheckIsImm, /*MI*/0, /*Op*/5,
        // MIs[0] auxiliary
        GIM_CheckIsImm, /*MI*/0, /*Op*/6,
        // MIs[0] Operand 7
        GIM_CheckIsImm, /*MI*/0, /*Op*/7,
        GIM_CheckComplexPattern, /*MI*/0, /*Op*/4, /*Renderer*/GIMT_Encode2(0), GIMT_Encode2(GICP_gi_buf_soffset),
        // (SIbuffer_store v4f16:{ *:[v4f16] }:$vdata, v4i32:{ *:[v4i32] }:$rsrc, i32:{ *:[i32] }:$vindex, i32:{ *:[i32] }:$voffset, (BUFSOffset:{ *:[i32] } i32:{ *:[i32] }:$soffset), (timm:{ *:[i32] }):$offset, (timm:{ *:[i32] }):$auxiliary, (timm:{ *:[i1] }))  =>  (BUFFER_STORE_DWORDX2_BOTHEN_exact anonymous_15036:{ *:[v4f16] }:$vdata, (REG_SEQUENCE:{ *:[i64] } VReg_64:{ *:[i32] }, VGPR_32:{ *:[i32] }:$vindex, sub0:{ *:[i32] }, VGPR_32:{ *:[i32] }:$voffset, sub1:{ *:[i32] }), SReg_128:{ *:[v4i32] }:$rsrc, SCSrc_b32:{ *:[i32] }:$soffset, (timm:{ *:[i32] }):$offset, (extract_cpol:{ *:[i32] } ?:{ *:[i32] }:$auxiliary), (extract_swz:{ *:[i1] } ?:{ *:[i32] }:$auxiliary))
        GIR_MakeTempReg, /*TempRegID*/0, /*TypeID*/GILLT_s64,
        GIR_BuildMI, /*InsnID*/1, /*Opcode*/GIMT_Encode2(TargetOpcode::REG_SEQUENCE),
        GIR_AddTempRegister, /*InsnID*/1, /*TempRegID*/0, /*TempRegFlags*/GIMT_Encode2(RegState::Define),
        GIR_Copy, /*NewInsnID*/1, /*OldInsnID*/0, /*OpIdx*/2, // vindex
        GIR_AddImm8, /*InsnID*/1, /*SubRegIndex*/3,
        GIR_Copy, /*NewInsnID*/1, /*OldInsnID*/0, /*OpIdx*/3, // voffset
        GIR_AddImm8, /*InsnID*/1, /*SubRegIndex*/11,
        GIR_ConstrainOperandRC, /*InsnID*/1, /*Op*/0, GIMT_Encode2(AMDGPU::VReg_64RegClassID),
        GIR_ConstrainOperandRC, /*InsnID*/1, /*Op*/1, GIMT_Encode2(AMDGPU::VGPR_32RegClassID),
        GIR_ConstrainOperandRC, /*InsnID*/1, /*Op*/3, GIMT_Encode2(AMDGPU::VGPR_32RegClassID),
        GIR_BuildMI, /*InsnID*/0, /*Opcode*/GIMT_Encode2(AMDGPU::BUFFER_STORE_DWORDX2_BOTHEN_exact),
        GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/0, // vdata
        GIR_AddSimpleTempRegister, /*InsnID*/0, /*TempRegID*/0,
        GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/1, // rsrc
        GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/0, // soffset
        GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/5, // offset
        GIR_CustomOperandRenderer, /*InsnID*/0, /*OldInsnID*/0, /*OpIdx*/6, /*OperandRenderer*/GIMT_Encode2(GICR_renderExtractCPol), // auxiliary
        GIR_CustomOperandRenderer, /*InsnID*/0, /*OldInsnID*/0, /*OpIdx*/6, /*OperandRenderer*/GIMT_Encode2(GICR_renderExtractSWZ), // auxiliary
        GIR_MergeMemOperands, /*InsnID*/0, /*NumInsns*/1, /*MergeInsnID's*/0,
        GIR_ConstrainSelectedInstOperands, /*InsnID*/0,
        GIR_EraseFromParent, /*InsnID*/0,
        // GIR_Coverage, 4452,
        GIR_Done,
      // Label 6863: @504233
      GIM_Try, /*On fail goto*//*Label 6864*/ GIMT_Encode4(504340), // Rule ID 4456 //
        // MIs[0] offset
        GIM_CheckIsImm, /*MI*/0, /*Op*/5,
        // MIs[0] auxiliary
        GIM_CheckIsImm, /*MI*/0, /*Op*/6,
        // MIs[0] Operand 7
        GIM_CheckIsImm, /*MI*/0, /*Op*/7,
        GIM_CheckComplexPattern, /*MI*/0, /*Op*/4, /*Renderer*/GIMT_Encode2(0), GIMT_Encode2(GICP_gi_buf_soffset),
        // (SIbuffer_store v4f16:{ *:[v4f16] }:$vdata, v4i32:{ *:[v4i32] }:$rsrc, i32:{ *:[i32] }:$vindex, i32:{ *:[i32] }:$voffset, (BUFSOffset:{ *:[i32] } i32:{ *:[i32] }:$soffset), (timm:{ *:[i32] }):$offset, (timm:{ *:[i32] }):$auxiliary, (timm:{ *:[i1] }))  =>  (BUFFER_STORE_DWORDX2_VBUFFER_BOTHEN_exact anonymous_15036:{ *:[v4f16] }:$vdata, (REG_SEQUENCE:{ *:[i64] } VReg_64:{ *:[i32] }, VGPR_32:{ *:[i32] }:$vindex, sub0:{ *:[i32] }, VGPR_32:{ *:[i32] }:$voffset, sub1:{ *:[i32] }), SReg_128:{ *:[v4i32] }:$rsrc, SCSrc_b32:{ *:[i32] }:$soffset, (timm:{ *:[i32] }):$offset, (extract_cpol:{ *:[i32] } ?:{ *:[i32] }:$auxiliary), (extract_swz:{ *:[i1] } ?:{ *:[i32] }:$auxiliary))
        GIR_MakeTempReg, /*TempRegID*/0, /*TypeID*/GILLT_s64,
        GIR_BuildMI, /*InsnID*/1, /*Opcode*/GIMT_Encode2(TargetOpcode::REG_SEQUENCE),
        GIR_AddTempRegister, /*InsnID*/1, /*TempRegID*/0, /*TempRegFlags*/GIMT_Encode2(RegState::Define),
        GIR_Copy, /*NewInsnID*/1, /*OldInsnID*/0, /*OpIdx*/2, // vindex
        GIR_AddImm8, /*InsnID*/1, /*SubRegIndex*/3,
        GIR_Copy, /*NewInsnID*/1, /*OldInsnID*/0, /*OpIdx*/3, // voffset
        GIR_AddImm8, /*InsnID*/1, /*SubRegIndex*/11,
        GIR_ConstrainOperandRC, /*InsnID*/1, /*Op*/0, GIMT_Encode2(AMDGPU::VReg_64RegClassID),
        GIR_ConstrainOperandRC, /*InsnID*/1, /*Op*/1, GIMT_Encode2(AMDGPU::VGPR_32RegClassID),
        GIR_ConstrainOperandRC, /*InsnID*/1, /*Op*/3, GIMT_Encode2(AMDGPU::VGPR_32RegClassID),
        GIR_BuildMI, /*InsnID*/0, /*Opcode*/GIMT_Encode2(AMDGPU::BUFFER_STORE_DWORDX2_VBUFFER_BOTHEN_exact),
        GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/0, // vdata
        GIR_AddSimpleTempRegister, /*InsnID*/0, /*TempRegID*/0,
        GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/1, // rsrc
        GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/0, // soffset
        GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/5, // offset
        GIR_CustomOperandRenderer, /*InsnID*/0, /*OldInsnID*/0, /*OpIdx*/6, /*OperandRenderer*/GIMT_Encode2(GICR_renderExtractCPol), // auxiliary
        GIR_CustomOperandRenderer, /*InsnID*/0, /*OldInsnID*/0, /*OpIdx*/6, /*OperandRenderer*/GIMT_Encode2(GICR_renderExtractSWZ), // auxiliary
        GIR_MergeMemOperands, /*InsnID*/0, /*NumInsns*/1, /*MergeInsnID's*/0,
        GIR_ConstrainSelectedInstOperands, /*InsnID*/0,
        GIR_EraseFromParent, /*InsnID*/0,
        // GIR_Coverage, 4456,
        GIR_Done,
      // Label 6864: @504340
      GIM_Reject,
    // Label 6848: @504341
    GIM_Reject,
    // Label 6778: @504342
    GIM_Try, /*On fail goto*//*Label 6865*/ GIMT_Encode4(505732),
      GIM_CheckType, /*MI*/0, /*Op*/1, /*Type*/GILLT_v4s32,
      GIM_CheckType, /*MI*/0, /*Op*/2, /*Type*/GILLT_s32,
      GIM_CheckType, /*MI*/0, /*Op*/3, /*Type*/GILLT_s32,
      GIM_CheckType, /*MI*/0, /*Op*/4, /*Type*/GILLT_s32,
      GIM_Try, /*On fail goto*//*Label 6866*/ GIMT_Encode4(504445), // Rule ID 4473 //
        GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasUnrestrictedSOffset),
        GIM_CheckConstantInt8, /*MI*/0, /*Op*/2, 0,
        GIM_CheckConstantInt8, /*MI*/0, /*Op*/3, 0,
        // MIs[0] offset
        GIM_CheckIsImm, /*MI*/0, /*Op*/5,
        // MIs[0] auxiliary
        GIM_CheckIsImm, /*MI*/0, /*Op*/6,
        // MIs[0] Operand 7
        GIM_CheckLiteralInt, /*MI*/0, /*Op*/7, GIMT_Encode8(0),
        GIM_CheckComplexPattern, /*MI*/0, /*Op*/4, /*Renderer*/GIMT_Encode2(0), GIMT_Encode2(GICP_gi_buf_soffset),
        // (SIbuffer_store v4f32:{ *:[v4f32] }:$vdata, v4i32:{ *:[v4i32] }:$rsrc, 0:{ *:[i32] }, 0:{ *:[i32] }, (BUFSOffset:{ *:[i32] } i32:{ *:[i32] }:$soffset), (timm:{ *:[i32] }):$offset, (timm:{ *:[i32] }):$auxiliary, 0:{ *:[i1] })  =>  (BUFFER_STORE_DWORDX4_OFFSET_exact anonymous_15034:{ *:[v4f32] }:$vdata, SReg_128:{ *:[v4i32] }:$rsrc, SCSrc_b32:{ *:[i32] }:$soffset, (timm:{ *:[i32] }):$offset, (extract_cpol:{ *:[i32] } ?:{ *:[i32] }:$auxiliary), (extract_swz:{ *:[i1] } ?:{ *:[i32] }:$auxiliary))
        GIR_BuildMI, /*InsnID*/0, /*Opcode*/GIMT_Encode2(AMDGPU::BUFFER_STORE_DWORDX4_OFFSET_exact),
        GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/0, // vdata
        GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/1, // rsrc
        GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/0, // soffset
        GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/5, // offset
        GIR_CustomOperandRenderer, /*InsnID*/0, /*OldInsnID*/0, /*OpIdx*/6, /*OperandRenderer*/GIMT_Encode2(GICR_renderExtractCPol), // auxiliary
        GIR_CustomOperandRenderer, /*InsnID*/0, /*OldInsnID*/0, /*OpIdx*/6, /*OperandRenderer*/GIMT_Encode2(GICR_renderExtractSWZ), // auxiliary
        GIR_MergeMemOperands, /*InsnID*/0, /*NumInsns*/1, /*MergeInsnID's*/0,
        GIR_ConstrainSelectedInstOperands, /*InsnID*/0,
        GIR_EraseFromParent, /*InsnID*/0,
        // GIR_Coverage, 4473,
        GIR_Done,
      // Label 6866: @504445
      GIM_Try, /*On fail goto*//*Label 6867*/ GIMT_Encode4(504524), // Rule ID 4477 //
        GIM_CheckConstantInt8, /*MI*/0, /*Op*/2, 0,
        GIM_CheckConstantInt8, /*MI*/0, /*Op*/3, 0,
        // MIs[0] offset
        GIM_CheckIsImm, /*MI*/0, /*Op*/5,
        // MIs[0] auxiliary
        GIM_CheckIsImm, /*MI*/0, /*Op*/6,
        // MIs[0] Operand 7
        GIM_CheckLiteralInt, /*MI*/0, /*Op*/7, GIMT_Encode8(0),
        GIM_CheckComplexPattern, /*MI*/0, /*Op*/4, /*Renderer*/GIMT_Encode2(0), GIMT_Encode2(GICP_gi_buf_soffset),
        // (SIbuffer_store v4f32:{ *:[v4f32] }:$vdata, v4i32:{ *:[v4i32] }:$rsrc, 0:{ *:[i32] }, 0:{ *:[i32] }, (BUFSOffset:{ *:[i32] } i32:{ *:[i32] }:$soffset), (timm:{ *:[i32] }):$offset, (timm:{ *:[i32] }):$auxiliary, 0:{ *:[i1] })  =>  (BUFFER_STORE_DWORDX4_VBUFFER_OFFSET_exact anonymous_15034:{ *:[v4f32] }:$vdata, SReg_128:{ *:[v4i32] }:$rsrc, SCSrc_b32:{ *:[i32] }:$soffset, (timm:{ *:[i32] }):$offset, (extract_cpol:{ *:[i32] } ?:{ *:[i32] }:$auxiliary), (extract_swz:{ *:[i1] } ?:{ *:[i32] }:$auxiliary))
        GIR_BuildMI, /*InsnID*/0, /*Opcode*/GIMT_Encode2(AMDGPU::BUFFER_STORE_DWORDX4_VBUFFER_OFFSET_exact),
        GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/0, // vdata
        GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/1, // rsrc
        GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/0, // soffset
        GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/5, // offset
        GIR_CustomOperandRenderer, /*InsnID*/0, /*OldInsnID*/0, /*OpIdx*/6, /*OperandRenderer*/GIMT_Encode2(GICR_renderExtractCPol), // auxiliary
        GIR_CustomOperandRenderer, /*InsnID*/0, /*OldInsnID*/0, /*OpIdx*/6, /*OperandRenderer*/GIMT_Encode2(GICR_renderExtractSWZ), // auxiliary
        GIR_MergeMemOperands, /*InsnID*/0, /*NumInsns*/1, /*MergeInsnID's*/0,
        GIR_ConstrainSelectedInstOperands, /*InsnID*/0,
        GIR_EraseFromParent, /*InsnID*/0,
        // GIR_Coverage, 4477,
        GIR_Done,
      // Label 6867: @504524
      GIM_Try, /*On fail goto*//*Label 6868*/ GIMT_Encode4(504606), // Rule ID 4481 //
        GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasUnrestrictedSOffset),
        GIM_CheckConstantInt8, /*MI*/0, /*Op*/2, 0,
        GIM_CheckConstantInt8, /*MI*/0, /*Op*/3, 0,
        // MIs[0] offset
        GIM_CheckIsImm, /*MI*/0, /*Op*/5,
        // MIs[0] auxiliary
        GIM_CheckIsImm, /*MI*/0, /*Op*/6,
        // MIs[0] Operand 7
        GIM_CheckLiteralInt, /*MI*/0, /*Op*/7, GIMT_Encode8(0),
        GIM_CheckComplexPattern, /*MI*/0, /*Op*/4, /*Renderer*/GIMT_Encode2(0), GIMT_Encode2(GICP_gi_buf_soffset),
        // (SIbuffer_store v4i32:{ *:[v4i32] }:$vdata, v4i32:{ *:[v4i32] }:$rsrc, 0:{ *:[i32] }, 0:{ *:[i32] }, (BUFSOffset:{ *:[i32] } i32:{ *:[i32] }:$soffset), (timm:{ *:[i32] }):$offset, (timm:{ *:[i32] }):$auxiliary, 0:{ *:[i1] })  =>  (BUFFER_STORE_DWORDX4_OFFSET_exact anonymous_15034:{ *:[v4i32] }:$vdata, SReg_128:{ *:[v4i32] }:$rsrc, SCSrc_b32:{ *:[i32] }:$soffset, (timm:{ *:[i32] }):$offset, (extract_cpol:{ *:[i32] } ?:{ *:[i32] }:$auxiliary), (extract_swz:{ *:[i1] } ?:{ *:[i32] }:$auxiliary))
        GIR_BuildMI, /*InsnID*/0, /*Opcode*/GIMT_Encode2(AMDGPU::BUFFER_STORE_DWORDX4_OFFSET_exact),
        GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/0, // vdata
        GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/1, // rsrc
        GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/0, // soffset
        GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/5, // offset
        GIR_CustomOperandRenderer, /*InsnID*/0, /*OldInsnID*/0, /*OpIdx*/6, /*OperandRenderer*/GIMT_Encode2(GICR_renderExtractCPol), // auxiliary
        GIR_CustomOperandRenderer, /*InsnID*/0, /*OldInsnID*/0, /*OpIdx*/6, /*OperandRenderer*/GIMT_Encode2(GICR_renderExtractSWZ), // auxiliary
        GIR_MergeMemOperands, /*InsnID*/0, /*NumInsns*/1, /*MergeInsnID's*/0,
        GIR_ConstrainSelectedInstOperands, /*InsnID*/0,
        GIR_EraseFromParent, /*InsnID*/0,
        // GIR_Coverage, 4481,
        GIR_Done,
      // Label 6868: @504606
      GIM_Try, /*On fail goto*//*Label 6869*/ GIMT_Encode4(504685), // Rule ID 4485 //
        GIM_CheckConstantInt8, /*MI*/0, /*Op*/2, 0,
        GIM_CheckConstantInt8, /*MI*/0, /*Op*/3, 0,
        // MIs[0] offset
        GIM_CheckIsImm, /*MI*/0, /*Op*/5,
        // MIs[0] auxiliary
        GIM_CheckIsImm, /*MI*/0, /*Op*/6,
        // MIs[0] Operand 7
        GIM_CheckLiteralInt, /*MI*/0, /*Op*/7, GIMT_Encode8(0),
        GIM_CheckComplexPattern, /*MI*/0, /*Op*/4, /*Renderer*/GIMT_Encode2(0), GIMT_Encode2(GICP_gi_buf_soffset),
        // (SIbuffer_store v4i32:{ *:[v4i32] }:$vdata, v4i32:{ *:[v4i32] }:$rsrc, 0:{ *:[i32] }, 0:{ *:[i32] }, (BUFSOffset:{ *:[i32] } i32:{ *:[i32] }:$soffset), (timm:{ *:[i32] }):$offset, (timm:{ *:[i32] }):$auxiliary, 0:{ *:[i1] })  =>  (BUFFER_STORE_DWORDX4_VBUFFER_OFFSET_exact anonymous_15034:{ *:[v4i32] }:$vdata, SReg_128:{ *:[v4i32] }:$rsrc, SCSrc_b32:{ *:[i32] }:$soffset, (timm:{ *:[i32] }):$offset, (extract_cpol:{ *:[i32] } ?:{ *:[i32] }:$auxiliary), (extract_swz:{ *:[i1] } ?:{ *:[i32] }:$auxiliary))
        GIR_BuildMI, /*InsnID*/0, /*Opcode*/GIMT_Encode2(AMDGPU::BUFFER_STORE_DWORDX4_VBUFFER_OFFSET_exact),
        GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/0, // vdata
        GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/1, // rsrc
        GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/0, // soffset
        GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/5, // offset
        GIR_CustomOperandRenderer, /*InsnID*/0, /*OldInsnID*/0, /*OpIdx*/6, /*OperandRenderer*/GIMT_Encode2(GICR_renderExtractCPol), // auxiliary
        GIR_CustomOperandRenderer, /*InsnID*/0, /*OldInsnID*/0, /*OpIdx*/6, /*OperandRenderer*/GIMT_Encode2(GICR_renderExtractSWZ), // auxiliary
        GIR_MergeMemOperands, /*InsnID*/0, /*NumInsns*/1, /*MergeInsnID's*/0,
        GIR_ConstrainSelectedInstOperands, /*InsnID*/0,
        GIR_EraseFromParent, /*InsnID*/0,
        // GIR_Coverage, 4485,
        GIR_Done,
      // Label 6869: @504685
      GIM_Try, /*On fail goto*//*Label 6870*/ GIMT_Encode4(504767), // Rule ID 4474 //
        GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasUnrestrictedSOffset),
        GIM_CheckConstantInt8, /*MI*/0, /*Op*/2, 0,
        // MIs[0] offset
        GIM_CheckIsImm, /*MI*/0, /*Op*/5,
        // MIs[0] auxiliary
        GIM_CheckIsImm, /*MI*/0, /*Op*/6,
        // MIs[0] Operand 7
        GIM_CheckLiteralInt, /*MI*/0, /*Op*/7, GIMT_Encode8(0),
        GIM_CheckComplexPattern, /*MI*/0, /*Op*/4, /*Renderer*/GIMT_Encode2(0), GIMT_Encode2(GICP_gi_buf_soffset),
        // (SIbuffer_store v4f32:{ *:[v4f32] }:$vdata, v4i32:{ *:[v4i32] }:$rsrc, 0:{ *:[i32] }, i32:{ *:[i32] }:$voffset, (BUFSOffset:{ *:[i32] } i32:{ *:[i32] }:$soffset), (timm:{ *:[i32] }):$offset, (timm:{ *:[i32] }):$auxiliary, 0:{ *:[i1] })  =>  (BUFFER_STORE_DWORDX4_OFFEN_exact anonymous_15034:{ *:[v4f32] }:$vdata, VGPR_32:{ *:[i32] }:$voffset, SReg_128:{ *:[v4i32] }:$rsrc, SCSrc_b32:{ *:[i32] }:$soffset, (timm:{ *:[i32] }):$offset, (extract_cpol:{ *:[i32] } ?:{ *:[i32] }:$auxiliary), (extract_swz:{ *:[i1] } ?:{ *:[i32] }:$auxiliary))
        GIR_BuildMI, /*InsnID*/0, /*Opcode*/GIMT_Encode2(AMDGPU::BUFFER_STORE_DWORDX4_OFFEN_exact),
        GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/0, // vdata
        GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/3, // voffset
        GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/1, // rsrc
        GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/0, // soffset
        GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/5, // offset
        GIR_CustomOperandRenderer, /*InsnID*/0, /*OldInsnID*/0, /*OpIdx*/6, /*OperandRenderer*/GIMT_Encode2(GICR_renderExtractCPol), // auxiliary
        GIR_CustomOperandRenderer, /*InsnID*/0, /*OldInsnID*/0, /*OpIdx*/6, /*OperandRenderer*/GIMT_Encode2(GICR_renderExtractSWZ), // auxiliary
        GIR_MergeMemOperands, /*InsnID*/0, /*NumInsns*/1, /*MergeInsnID's*/0,
        GIR_ConstrainSelectedInstOperands, /*InsnID*/0,
        GIR_EraseFromParent, /*InsnID*/0,
        // GIR_Coverage, 4474,
        GIR_Done,
      // Label 6870: @504767
      GIM_Try, /*On fail goto*//*Label 6871*/ GIMT_Encode4(504846), // Rule ID 4478 //
        GIM_CheckConstantInt8, /*MI*/0, /*Op*/2, 0,
        // MIs[0] offset
        GIM_CheckIsImm, /*MI*/0, /*Op*/5,
        // MIs[0] auxiliary
        GIM_CheckIsImm, /*MI*/0, /*Op*/6,
        // MIs[0] Operand 7
        GIM_CheckLiteralInt, /*MI*/0, /*Op*/7, GIMT_Encode8(0),
        GIM_CheckComplexPattern, /*MI*/0, /*Op*/4, /*Renderer*/GIMT_Encode2(0), GIMT_Encode2(GICP_gi_buf_soffset),
        // (SIbuffer_store v4f32:{ *:[v4f32] }:$vdata, v4i32:{ *:[v4i32] }:$rsrc, 0:{ *:[i32] }, i32:{ *:[i32] }:$voffset, (BUFSOffset:{ *:[i32] } i32:{ *:[i32] }:$soffset), (timm:{ *:[i32] }):$offset, (timm:{ *:[i32] }):$auxiliary, 0:{ *:[i1] })  =>  (BUFFER_STORE_DWORDX4_VBUFFER_OFFEN_exact anonymous_15034:{ *:[v4f32] }:$vdata, VGPR_32:{ *:[i32] }:$voffset, SReg_128:{ *:[v4i32] }:$rsrc, SCSrc_b32:{ *:[i32] }:$soffset, (timm:{ *:[i32] }):$offset, (extract_cpol:{ *:[i32] } ?:{ *:[i32] }:$auxiliary), (extract_swz:{ *:[i1] } ?:{ *:[i32] }:$auxiliary))
        GIR_BuildMI, /*InsnID*/0, /*Opcode*/GIMT_Encode2(AMDGPU::BUFFER_STORE_DWORDX4_VBUFFER_OFFEN_exact),
        GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/0, // vdata
        GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/3, // voffset
        GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/1, // rsrc
        GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/0, // soffset
        GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/5, // offset
        GIR_CustomOperandRenderer, /*InsnID*/0, /*OldInsnID*/0, /*OpIdx*/6, /*OperandRenderer*/GIMT_Encode2(GICR_renderExtractCPol), // auxiliary
        GIR_CustomOperandRenderer, /*InsnID*/0, /*OldInsnID*/0, /*OpIdx*/6, /*OperandRenderer*/GIMT_Encode2(GICR_renderExtractSWZ), // auxiliary
        GIR_MergeMemOperands, /*InsnID*/0, /*NumInsns*/1, /*MergeInsnID's*/0,
        GIR_ConstrainSelectedInstOperands, /*InsnID*/0,
        GIR_EraseFromParent, /*InsnID*/0,
        // GIR_Coverage, 4478,
        GIR_Done,
      // Label 6871: @504846
      GIM_Try, /*On fail goto*//*Label 6872*/ GIMT_Encode4(504928), // Rule ID 4482 //
        GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasUnrestrictedSOffset),
        GIM_CheckConstantInt8, /*MI*/0, /*Op*/2, 0,
        // MIs[0] offset
        GIM_CheckIsImm, /*MI*/0, /*Op*/5,
        // MIs[0] auxiliary
        GIM_CheckIsImm, /*MI*/0, /*Op*/6,
        // MIs[0] Operand 7
        GIM_CheckLiteralInt, /*MI*/0, /*Op*/7, GIMT_Encode8(0),
        GIM_CheckComplexPattern, /*MI*/0, /*Op*/4, /*Renderer*/GIMT_Encode2(0), GIMT_Encode2(GICP_gi_buf_soffset),
        // (SIbuffer_store v4i32:{ *:[v4i32] }:$vdata, v4i32:{ *:[v4i32] }:$rsrc, 0:{ *:[i32] }, i32:{ *:[i32] }:$voffset, (BUFSOffset:{ *:[i32] } i32:{ *:[i32] }:$soffset), (timm:{ *:[i32] }):$offset, (timm:{ *:[i32] }):$auxiliary, 0:{ *:[i1] })  =>  (BUFFER_STORE_DWORDX4_OFFEN_exact anonymous_15034:{ *:[v4i32] }:$vdata, VGPR_32:{ *:[i32] }:$voffset, SReg_128:{ *:[v4i32] }:$rsrc, SCSrc_b32:{ *:[i32] }:$soffset, (timm:{ *:[i32] }):$offset, (extract_cpol:{ *:[i32] } ?:{ *:[i32] }:$auxiliary), (extract_swz:{ *:[i1] } ?:{ *:[i32] }:$auxiliary))
        GIR_BuildMI, /*InsnID*/0, /*Opcode*/GIMT_Encode2(AMDGPU::BUFFER_STORE_DWORDX4_OFFEN_exact),
        GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/0, // vdata
        GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/3, // voffset
        GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/1, // rsrc
        GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/0, // soffset
        GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/5, // offset
        GIR_CustomOperandRenderer, /*InsnID*/0, /*OldInsnID*/0, /*OpIdx*/6, /*OperandRenderer*/GIMT_Encode2(GICR_renderExtractCPol), // auxiliary
        GIR_CustomOperandRenderer, /*InsnID*/0, /*OldInsnID*/0, /*OpIdx*/6, /*OperandRenderer*/GIMT_Encode2(GICR_renderExtractSWZ), // auxiliary
        GIR_MergeMemOperands, /*InsnID*/0, /*NumInsns*/1, /*MergeInsnID's*/0,
        GIR_ConstrainSelectedInstOperands, /*InsnID*/0,
        GIR_EraseFromParent, /*InsnID*/0,
        // GIR_Coverage, 4482,
        GIR_Done,
      // Label 6872: @504928
      GIM_Try, /*On fail goto*//*Label 6873*/ GIMT_Encode4(505007), // Rule ID 4486 //
        GIM_CheckConstantInt8, /*MI*/0, /*Op*/2, 0,
        // MIs[0] offset
        GIM_CheckIsImm, /*MI*/0, /*Op*/5,
        // MIs[0] auxiliary
        GIM_CheckIsImm, /*MI*/0, /*Op*/6,
        // MIs[0] Operand 7
        GIM_CheckLiteralInt, /*MI*/0, /*Op*/7, GIMT_Encode8(0),
        GIM_CheckComplexPattern, /*MI*/0, /*Op*/4, /*Renderer*/GIMT_Encode2(0), GIMT_Encode2(GICP_gi_buf_soffset),
        // (SIbuffer_store v4i32:{ *:[v4i32] }:$vdata, v4i32:{ *:[v4i32] }:$rsrc, 0:{ *:[i32] }, i32:{ *:[i32] }:$voffset, (BUFSOffset:{ *:[i32] } i32:{ *:[i32] }:$soffset), (timm:{ *:[i32] }):$offset, (timm:{ *:[i32] }):$auxiliary, 0:{ *:[i1] })  =>  (BUFFER_STORE_DWORDX4_VBUFFER_OFFEN_exact anonymous_15034:{ *:[v4i32] }:$vdata, VGPR_32:{ *:[i32] }:$voffset, SReg_128:{ *:[v4i32] }:$rsrc, SCSrc_b32:{ *:[i32] }:$soffset, (timm:{ *:[i32] }):$offset, (extract_cpol:{ *:[i32] } ?:{ *:[i32] }:$auxiliary), (extract_swz:{ *:[i1] } ?:{ *:[i32] }:$auxiliary))
        GIR_BuildMI, /*InsnID*/0, /*Opcode*/GIMT_Encode2(AMDGPU::BUFFER_STORE_DWORDX4_VBUFFER_OFFEN_exact),
        GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/0, // vdata
        GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/3, // voffset
        GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/1, // rsrc
        GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/0, // soffset
        GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/5, // offset
        GIR_CustomOperandRenderer, /*InsnID*/0, /*OldInsnID*/0, /*OpIdx*/6, /*OperandRenderer*/GIMT_Encode2(GICR_renderExtractCPol), // auxiliary
        GIR_CustomOperandRenderer, /*InsnID*/0, /*OldInsnID*/0, /*OpIdx*/6, /*OperandRenderer*/GIMT_Encode2(GICR_renderExtractSWZ), // auxiliary
        GIR_MergeMemOperands, /*InsnID*/0, /*NumInsns*/1, /*MergeInsnID's*/0,
        GIR_ConstrainSelectedInstOperands, /*InsnID*/0,
        GIR_EraseFromParent, /*InsnID*/0,
        // GIR_Coverage, 4486,
        GIR_Done,
      // Label 6873: @505007
      GIM_Try, /*On fail goto*//*Label 6874*/ GIMT_Encode4(505081), // Rule ID 4475 //
        GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasUnrestrictedSOffset),
        GIM_CheckConstantInt8, /*MI*/0, /*Op*/3, 0,
        // MIs[0] offset
        GIM_CheckIsImm, /*MI*/0, /*Op*/5,
        // MIs[0] auxiliary
        GIM_CheckIsImm, /*MI*/0, /*Op*/6,
        // MIs[0] Operand 7
        GIM_CheckIsImm, /*MI*/0, /*Op*/7,
        GIM_CheckComplexPattern, /*MI*/0, /*Op*/4, /*Renderer*/GIMT_Encode2(0), GIMT_Encode2(GICP_gi_buf_soffset),
        // (SIbuffer_store v4f32:{ *:[v4f32] }:$vdata, v4i32:{ *:[v4i32] }:$rsrc, i32:{ *:[i32] }:$vindex, 0:{ *:[i32] }, (BUFSOffset:{ *:[i32] } i32:{ *:[i32] }:$soffset), (timm:{ *:[i32] }):$offset, (timm:{ *:[i32] }):$auxiliary, (timm:{ *:[i1] }))  =>  (BUFFER_STORE_DWORDX4_IDXEN_exact anonymous_15034:{ *:[v4f32] }:$vdata, VGPR_32:{ *:[i32] }:$vindex, SReg_128:{ *:[v4i32] }:$rsrc, SCSrc_b32:{ *:[i32] }:$soffset, (timm:{ *:[i32] }):$offset, (extract_cpol:{ *:[i32] } ?:{ *:[i32] }:$auxiliary), (extract_swz:{ *:[i1] } ?:{ *:[i32] }:$auxiliary))
        GIR_BuildMI, /*InsnID*/0, /*Opcode*/GIMT_Encode2(AMDGPU::BUFFER_STORE_DWORDX4_IDXEN_exact),
        GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/0, // vdata
        GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/2, // vindex
        GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/1, // rsrc
        GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/0, // soffset
        GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/5, // offset
        GIR_CustomOperandRenderer, /*InsnID*/0, /*OldInsnID*/0, /*OpIdx*/6, /*OperandRenderer*/GIMT_Encode2(GICR_renderExtractCPol), // auxiliary
        GIR_CustomOperandRenderer, /*InsnID*/0, /*OldInsnID*/0, /*OpIdx*/6, /*OperandRenderer*/GIMT_Encode2(GICR_renderExtractSWZ), // auxiliary
        GIR_MergeMemOperands, /*InsnID*/0, /*NumInsns*/1, /*MergeInsnID's*/0,
        GIR_ConstrainSelectedInstOperands, /*InsnID*/0,
        GIR_EraseFromParent, /*InsnID*/0,
        // GIR_Coverage, 4475,
        GIR_Done,
      // Label 6874: @505081
      GIM_Try, /*On fail goto*//*Label 6875*/ GIMT_Encode4(505152), // Rule ID 4479 //
        GIM_CheckConstantInt8, /*MI*/0, /*Op*/3, 0,
        // MIs[0] offset
        GIM_CheckIsImm, /*MI*/0, /*Op*/5,
        // MIs[0] auxiliary
        GIM_CheckIsImm, /*MI*/0, /*Op*/6,
        // MIs[0] Operand 7
        GIM_CheckIsImm, /*MI*/0, /*Op*/7,
        GIM_CheckComplexPattern, /*MI*/0, /*Op*/4, /*Renderer*/GIMT_Encode2(0), GIMT_Encode2(GICP_gi_buf_soffset),
        // (SIbuffer_store v4f32:{ *:[v4f32] }:$vdata, v4i32:{ *:[v4i32] }:$rsrc, i32:{ *:[i32] }:$vindex, 0:{ *:[i32] }, (BUFSOffset:{ *:[i32] } i32:{ *:[i32] }:$soffset), (timm:{ *:[i32] }):$offset, (timm:{ *:[i32] }):$auxiliary, (timm:{ *:[i1] }))  =>  (BUFFER_STORE_DWORDX4_VBUFFER_IDXEN_exact anonymous_15034:{ *:[v4f32] }:$vdata, VGPR_32:{ *:[i32] }:$vindex, SReg_128:{ *:[v4i32] }:$rsrc, SCSrc_b32:{ *:[i32] }:$soffset, (timm:{ *:[i32] }):$offset, (extract_cpol:{ *:[i32] } ?:{ *:[i32] }:$auxiliary), (extract_swz:{ *:[i1] } ?:{ *:[i32] }:$auxiliary))
        GIR_BuildMI, /*InsnID*/0, /*Opcode*/GIMT_Encode2(AMDGPU::BUFFER_STORE_DWORDX4_VBUFFER_IDXEN_exact),
        GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/0, // vdata
        GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/2, // vindex
        GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/1, // rsrc
        GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/0, // soffset
        GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/5, // offset
        GIR_CustomOperandRenderer, /*InsnID*/0, /*OldInsnID*/0, /*OpIdx*/6, /*OperandRenderer*/GIMT_Encode2(GICR_renderExtractCPol), // auxiliary
        GIR_CustomOperandRenderer, /*InsnID*/0, /*OldInsnID*/0, /*OpIdx*/6, /*OperandRenderer*/GIMT_Encode2(GICR_renderExtractSWZ), // auxiliary
        GIR_MergeMemOperands, /*InsnID*/0, /*NumInsns*/1, /*MergeInsnID's*/0,
        GIR_ConstrainSelectedInstOperands, /*InsnID*/0,
        GIR_EraseFromParent, /*InsnID*/0,
        // GIR_Coverage, 4479,
        GIR_Done,
      // Label 6875: @505152
      GIM_Try, /*On fail goto*//*Label 6876*/ GIMT_Encode4(505226), // Rule ID 4483 //
        GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasUnrestrictedSOffset),
        GIM_CheckConstantInt8, /*MI*/0, /*Op*/3, 0,
        // MIs[0] offset
        GIM_CheckIsImm, /*MI*/0, /*Op*/5,
        // MIs[0] auxiliary
        GIM_CheckIsImm, /*MI*/0, /*Op*/6,
        // MIs[0] Operand 7
        GIM_CheckIsImm, /*MI*/0, /*Op*/7,
        GIM_CheckComplexPattern, /*MI*/0, /*Op*/4, /*Renderer*/GIMT_Encode2(0), GIMT_Encode2(GICP_gi_buf_soffset),
        // (SIbuffer_store v4i32:{ *:[v4i32] }:$vdata, v4i32:{ *:[v4i32] }:$rsrc, i32:{ *:[i32] }:$vindex, 0:{ *:[i32] }, (BUFSOffset:{ *:[i32] } i32:{ *:[i32] }:$soffset), (timm:{ *:[i32] }):$offset, (timm:{ *:[i32] }):$auxiliary, (timm:{ *:[i1] }))  =>  (BUFFER_STORE_DWORDX4_IDXEN_exact anonymous_15034:{ *:[v4i32] }:$vdata, VGPR_32:{ *:[i32] }:$vindex, SReg_128:{ *:[v4i32] }:$rsrc, SCSrc_b32:{ *:[i32] }:$soffset, (timm:{ *:[i32] }):$offset, (extract_cpol:{ *:[i32] } ?:{ *:[i32] }:$auxiliary), (extract_swz:{ *:[i1] } ?:{ *:[i32] }:$auxiliary))
        GIR_BuildMI, /*InsnID*/0, /*Opcode*/GIMT_Encode2(AMDGPU::BUFFER_STORE_DWORDX4_IDXEN_exact),
        GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/0, // vdata
        GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/2, // vindex
        GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/1, // rsrc
        GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/0, // soffset
        GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/5, // offset
        GIR_CustomOperandRenderer, /*InsnID*/0, /*OldInsnID*/0, /*OpIdx*/6, /*OperandRenderer*/GIMT_Encode2(GICR_renderExtractCPol), // auxiliary
        GIR_CustomOperandRenderer, /*InsnID*/0, /*OldInsnID*/0, /*OpIdx*/6, /*OperandRenderer*/GIMT_Encode2(GICR_renderExtractSWZ), // auxiliary
        GIR_MergeMemOperands, /*InsnID*/0, /*NumInsns*/1, /*MergeInsnID's*/0,
        GIR_ConstrainSelectedInstOperands, /*InsnID*/0,
        GIR_EraseFromParent, /*InsnID*/0,
        // GIR_Coverage, 4483,
        GIR_Done,
      // Label 6876: @505226
      GIM_Try, /*On fail goto*//*Label 6877*/ GIMT_Encode4(505297), // Rule ID 4487 //
        GIM_CheckConstantInt8, /*MI*/0, /*Op*/3, 0,
        // MIs[0] offset
        GIM_CheckIsImm, /*MI*/0, /*Op*/5,
        // MIs[0] auxiliary
        GIM_CheckIsImm, /*MI*/0, /*Op*/6,
        // MIs[0] Operand 7
        GIM_CheckIsImm, /*MI*/0, /*Op*/7,
        GIM_CheckComplexPattern, /*MI*/0, /*Op*/4, /*Renderer*/GIMT_Encode2(0), GIMT_Encode2(GICP_gi_buf_soffset),
        // (SIbuffer_store v4i32:{ *:[v4i32] }:$vdata, v4i32:{ *:[v4i32] }:$rsrc, i32:{ *:[i32] }:$vindex, 0:{ *:[i32] }, (BUFSOffset:{ *:[i32] } i32:{ *:[i32] }:$soffset), (timm:{ *:[i32] }):$offset, (timm:{ *:[i32] }):$auxiliary, (timm:{ *:[i1] }))  =>  (BUFFER_STORE_DWORDX4_VBUFFER_IDXEN_exact anonymous_15034:{ *:[v4i32] }:$vdata, VGPR_32:{ *:[i32] }:$vindex, SReg_128:{ *:[v4i32] }:$rsrc, SCSrc_b32:{ *:[i32] }:$soffset, (timm:{ *:[i32] }):$offset, (extract_cpol:{ *:[i32] } ?:{ *:[i32] }:$auxiliary), (extract_swz:{ *:[i1] } ?:{ *:[i32] }:$auxiliary))
        GIR_BuildMI, /*InsnID*/0, /*Opcode*/GIMT_Encode2(AMDGPU::BUFFER_STORE_DWORDX4_VBUFFER_IDXEN_exact),
        GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/0, // vdata
        GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/2, // vindex
        GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/1, // rsrc
        GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/0, // soffset
        GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/5, // offset
        GIR_CustomOperandRenderer, /*InsnID*/0, /*OldInsnID*/0, /*OpIdx*/6, /*OperandRenderer*/GIMT_Encode2(GICR_renderExtractCPol), // auxiliary
        GIR_CustomOperandRenderer, /*InsnID*/0, /*OldInsnID*/0, /*OpIdx*/6, /*OperandRenderer*/GIMT_Encode2(GICR_renderExtractSWZ), // auxiliary
        GIR_MergeMemOperands, /*InsnID*/0, /*NumInsns*/1, /*MergeInsnID's*/0,
        GIR_ConstrainSelectedInstOperands, /*InsnID*/0,
        GIR_EraseFromParent, /*InsnID*/0,
        // GIR_Coverage, 4487,
        GIR_Done,
      // Label 6877: @505297
      GIM_Try, /*On fail goto*//*Label 6878*/ GIMT_Encode4(505407), // Rule ID 4476 //
        GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasUnrestrictedSOffset),
        // MIs[0] offset
        GIM_CheckIsImm, /*MI*/0, /*Op*/5,
        // MIs[0] auxiliary
        GIM_CheckIsImm, /*MI*/0, /*Op*/6,
        // MIs[0] Operand 7
        GIM_CheckIsImm, /*MI*/0, /*Op*/7,
        GIM_CheckComplexPattern, /*MI*/0, /*Op*/4, /*Renderer*/GIMT_Encode2(0), GIMT_Encode2(GICP_gi_buf_soffset),
        // (SIbuffer_store v4f32:{ *:[v4f32] }:$vdata, v4i32:{ *:[v4i32] }:$rsrc, i32:{ *:[i32] }:$vindex, i32:{ *:[i32] }:$voffset, (BUFSOffset:{ *:[i32] } i32:{ *:[i32] }:$soffset), (timm:{ *:[i32] }):$offset, (timm:{ *:[i32] }):$auxiliary, (timm:{ *:[i1] }))  =>  (BUFFER_STORE_DWORDX4_BOTHEN_exact anonymous_15034:{ *:[v4f32] }:$vdata, (REG_SEQUENCE:{ *:[i64] } VReg_64:{ *:[i32] }, VGPR_32:{ *:[i32] }:$vindex, sub0:{ *:[i32] }, VGPR_32:{ *:[i32] }:$voffset, sub1:{ *:[i32] }), SReg_128:{ *:[v4i32] }:$rsrc, SCSrc_b32:{ *:[i32] }:$soffset, (timm:{ *:[i32] }):$offset, (extract_cpol:{ *:[i32] } ?:{ *:[i32] }:$auxiliary), (extract_swz:{ *:[i1] } ?:{ *:[i32] }:$auxiliary))
        GIR_MakeTempReg, /*TempRegID*/0, /*TypeID*/GILLT_s64,
        GIR_BuildMI, /*InsnID*/1, /*Opcode*/GIMT_Encode2(TargetOpcode::REG_SEQUENCE),
        GIR_AddTempRegister, /*InsnID*/1, /*TempRegID*/0, /*TempRegFlags*/GIMT_Encode2(RegState::Define),
        GIR_Copy, /*NewInsnID*/1, /*OldInsnID*/0, /*OpIdx*/2, // vindex
        GIR_AddImm8, /*InsnID*/1, /*SubRegIndex*/3,
        GIR_Copy, /*NewInsnID*/1, /*OldInsnID*/0, /*OpIdx*/3, // voffset
        GIR_AddImm8, /*InsnID*/1, /*SubRegIndex*/11,
        GIR_ConstrainOperandRC, /*InsnID*/1, /*Op*/0, GIMT_Encode2(AMDGPU::VReg_64RegClassID),
        GIR_ConstrainOperandRC, /*InsnID*/1, /*Op*/1, GIMT_Encode2(AMDGPU::VGPR_32RegClassID),
        GIR_ConstrainOperandRC, /*InsnID*/1, /*Op*/3, GIMT_Encode2(AMDGPU::VGPR_32RegClassID),
        GIR_BuildMI, /*InsnID*/0, /*Opcode*/GIMT_Encode2(AMDGPU::BUFFER_STORE_DWORDX4_BOTHEN_exact),
        GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/0, // vdata
        GIR_AddSimpleTempRegister, /*InsnID*/0, /*TempRegID*/0,
        GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/1, // rsrc
        GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/0, // soffset
        GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/5, // offset
        GIR_CustomOperandRenderer, /*InsnID*/0, /*OldInsnID*/0, /*OpIdx*/6, /*OperandRenderer*/GIMT_Encode2(GICR_renderExtractCPol), // auxiliary
        GIR_CustomOperandRenderer, /*InsnID*/0, /*OldInsnID*/0, /*OpIdx*/6, /*OperandRenderer*/GIMT_Encode2(GICR_renderExtractSWZ), // auxiliary
        GIR_MergeMemOperands, /*InsnID*/0, /*NumInsns*/1, /*MergeInsnID's*/0,
        GIR_ConstrainSelectedInstOperands, /*InsnID*/0,
        GIR_EraseFromParent, /*InsnID*/0,
        // GIR_Coverage, 4476,
        GIR_Done,
      // Label 6878: @505407
      GIM_Try, /*On fail goto*//*Label 6879*/ GIMT_Encode4(505514), // Rule ID 4480 //
        // MIs[0] offset
        GIM_CheckIsImm, /*MI*/0, /*Op*/5,
        // MIs[0] auxiliary
        GIM_CheckIsImm, /*MI*/0, /*Op*/6,
        // MIs[0] Operand 7
        GIM_CheckIsImm, /*MI*/0, /*Op*/7,
        GIM_CheckComplexPattern, /*MI*/0, /*Op*/4, /*Renderer*/GIMT_Encode2(0), GIMT_Encode2(GICP_gi_buf_soffset),
        // (SIbuffer_store v4f32:{ *:[v4f32] }:$vdata, v4i32:{ *:[v4i32] }:$rsrc, i32:{ *:[i32] }:$vindex, i32:{ *:[i32] }:$voffset, (BUFSOffset:{ *:[i32] } i32:{ *:[i32] }:$soffset), (timm:{ *:[i32] }):$offset, (timm:{ *:[i32] }):$auxiliary, (timm:{ *:[i1] }))  =>  (BUFFER_STORE_DWORDX4_VBUFFER_BOTHEN_exact anonymous_15034:{ *:[v4f32] }:$vdata, (REG_SEQUENCE:{ *:[i64] } VReg_64:{ *:[i32] }, VGPR_32:{ *:[i32] }:$vindex, sub0:{ *:[i32] }, VGPR_32:{ *:[i32] }:$voffset, sub1:{ *:[i32] }), SReg_128:{ *:[v4i32] }:$rsrc, SCSrc_b32:{ *:[i32] }:$soffset, (timm:{ *:[i32] }):$offset, (extract_cpol:{ *:[i32] } ?:{ *:[i32] }:$auxiliary), (extract_swz:{ *:[i1] } ?:{ *:[i32] }:$auxiliary))
        GIR_MakeTempReg, /*TempRegID*/0, /*TypeID*/GILLT_s64,
        GIR_BuildMI, /*InsnID*/1, /*Opcode*/GIMT_Encode2(TargetOpcode::REG_SEQUENCE),
        GIR_AddTempRegister, /*InsnID*/1, /*TempRegID*/0, /*TempRegFlags*/GIMT_Encode2(RegState::Define),
        GIR_Copy, /*NewInsnID*/1, /*OldInsnID*/0, /*OpIdx*/2, // vindex
        GIR_AddImm8, /*InsnID*/1, /*SubRegIndex*/3,
        GIR_Copy, /*NewInsnID*/1, /*OldInsnID*/0, /*OpIdx*/3, // voffset
        GIR_AddImm8, /*InsnID*/1, /*SubRegIndex*/11,
        GIR_ConstrainOperandRC, /*InsnID*/1, /*Op*/0, GIMT_Encode2(AMDGPU::VReg_64RegClassID),
        GIR_ConstrainOperandRC, /*InsnID*/1, /*Op*/1, GIMT_Encode2(AMDGPU::VGPR_32RegClassID),
        GIR_ConstrainOperandRC, /*InsnID*/1, /*Op*/3, GIMT_Encode2(AMDGPU::VGPR_32RegClassID),
        GIR_BuildMI, /*InsnID*/0, /*Opcode*/GIMT_Encode2(AMDGPU::BUFFER_STORE_DWORDX4_VBUFFER_BOTHEN_exact),
        GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/0, // vdata
        GIR_AddSimpleTempRegister, /*InsnID*/0, /*TempRegID*/0,
        GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/1, // rsrc
        GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/0, // soffset
        GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/5, // offset
        GIR_CustomOperandRenderer, /*InsnID*/0, /*OldInsnID*/0, /*OpIdx*/6, /*OperandRenderer*/GIMT_Encode2(GICR_renderExtractCPol), // auxiliary
        GIR_CustomOperandRenderer, /*InsnID*/0, /*OldInsnID*/0, /*OpIdx*/6, /*OperandRenderer*/GIMT_Encode2(GICR_renderExtractSWZ), // auxiliary
        GIR_MergeMemOperands, /*InsnID*/0, /*NumInsns*/1, /*MergeInsnID's*/0,
        GIR_ConstrainSelectedInstOperands, /*InsnID*/0,
        GIR_EraseFromParent, /*InsnID*/0,
        // GIR_Coverage, 4480,
        GIR_Done,
      // Label 6879: @505514
      GIM_Try, /*On fail goto*//*Label 6880*/ GIMT_Encode4(505624), // Rule ID 4484 //
        GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasUnrestrictedSOffset),
        // MIs[0] offset
        GIM_CheckIsImm, /*MI*/0, /*Op*/5,
        // MIs[0] auxiliary
        GIM_CheckIsImm, /*MI*/0, /*Op*/6,
        // MIs[0] Operand 7
        GIM_CheckIsImm, /*MI*/0, /*Op*/7,
        GIM_CheckComplexPattern, /*MI*/0, /*Op*/4, /*Renderer*/GIMT_Encode2(0), GIMT_Encode2(GICP_gi_buf_soffset),
        // (SIbuffer_store v4i32:{ *:[v4i32] }:$vdata, v4i32:{ *:[v4i32] }:$rsrc, i32:{ *:[i32] }:$vindex, i32:{ *:[i32] }:$voffset, (BUFSOffset:{ *:[i32] } i32:{ *:[i32] }:$soffset), (timm:{ *:[i32] }):$offset, (timm:{ *:[i32] }):$auxiliary, (timm:{ *:[i1] }))  =>  (BUFFER_STORE_DWORDX4_BOTHEN_exact anonymous_15034:{ *:[v4i32] }:$vdata, (REG_SEQUENCE:{ *:[i64] } VReg_64:{ *:[i32] }, VGPR_32:{ *:[i32] }:$vindex, sub0:{ *:[i32] }, VGPR_32:{ *:[i32] }:$voffset, sub1:{ *:[i32] }), SReg_128:{ *:[v4i32] }:$rsrc, SCSrc_b32:{ *:[i32] }:$soffset, (timm:{ *:[i32] }):$offset, (extract_cpol:{ *:[i32] } ?:{ *:[i32] }:$auxiliary), (extract_swz:{ *:[i1] } ?:{ *:[i32] }:$auxiliary))
        GIR_MakeTempReg, /*TempRegID*/0, /*TypeID*/GILLT_s64,
        GIR_BuildMI, /*InsnID*/1, /*Opcode*/GIMT_Encode2(TargetOpcode::REG_SEQUENCE),
        GIR_AddTempRegister, /*InsnID*/1, /*TempRegID*/0, /*TempRegFlags*/GIMT_Encode2(RegState::Define),
        GIR_Copy, /*NewInsnID*/1, /*OldInsnID*/0, /*OpIdx*/2, // vindex
        GIR_AddImm8, /*InsnID*/1, /*SubRegIndex*/3,
        GIR_Copy, /*NewInsnID*/1, /*OldInsnID*/0, /*OpIdx*/3, // voffset
        GIR_AddImm8, /*InsnID*/1, /*SubRegIndex*/11,
        GIR_ConstrainOperandRC, /*InsnID*/1, /*Op*/0, GIMT_Encode2(AMDGPU::VReg_64RegClassID),
        GIR_ConstrainOperandRC, /*InsnID*/1, /*Op*/1, GIMT_Encode2(AMDGPU::VGPR_32RegClassID),
        GIR_ConstrainOperandRC, /*InsnID*/1, /*Op*/3, GIMT_Encode2(AMDGPU::VGPR_32RegClassID),
        GIR_BuildMI, /*InsnID*/0, /*Opcode*/GIMT_Encode2(AMDGPU::BUFFER_STORE_DWORDX4_BOTHEN_exact),
        GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/0, // vdata
        GIR_AddSimpleTempRegister, /*InsnID*/0, /*TempRegID*/0,
        GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/1, // rsrc
        GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/0, // soffset
        GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/5, // offset
        GIR_CustomOperandRenderer, /*InsnID*/0, /*OldInsnID*/0, /*OpIdx*/6, /*OperandRenderer*/GIMT_Encode2(GICR_renderExtractCPol), // auxiliary
        GIR_CustomOperandRenderer, /*InsnID*/0, /*OldInsnID*/0, /*OpIdx*/6, /*OperandRenderer*/GIMT_Encode2(GICR_renderExtractSWZ), // auxiliary
        GIR_MergeMemOperands, /*InsnID*/0, /*NumInsns*/1, /*MergeInsnID's*/0,
        GIR_ConstrainSelectedInstOperands, /*InsnID*/0,
        GIR_EraseFromParent, /*InsnID*/0,
        // GIR_Coverage, 4484,
        GIR_Done,
      // Label 6880: @505624
      GIM_Try, /*On fail goto*//*Label 6881*/ GIMT_Encode4(505731), // Rule ID 4488 //
        // MIs[0] offset
        GIM_CheckIsImm, /*MI*/0, /*Op*/5,
        // MIs[0] auxiliary
        GIM_CheckIsImm, /*MI*/0, /*Op*/6,
        // MIs[0] Operand 7
        GIM_CheckIsImm, /*MI*/0, /*Op*/7,
        GIM_CheckComplexPattern, /*MI*/0, /*Op*/4, /*Renderer*/GIMT_Encode2(0), GIMT_Encode2(GICP_gi_buf_soffset),
        // (SIbuffer_store v4i32:{ *:[v4i32] }:$vdata, v4i32:{ *:[v4i32] }:$rsrc, i32:{ *:[i32] }:$vindex, i32:{ *:[i32] }:$voffset, (BUFSOffset:{ *:[i32] } i32:{ *:[i32] }:$soffset), (timm:{ *:[i32] }):$offset, (timm:{ *:[i32] }):$auxiliary, (timm:{ *:[i1] }))  =>  (BUFFER_STORE_DWORDX4_VBUFFER_BOTHEN_exact anonymous_15034:{ *:[v4i32] }:$vdata, (REG_SEQUENCE:{ *:[i64] } VReg_64:{ *:[i32] }, VGPR_32:{ *:[i32] }:$vindex, sub0:{ *:[i32] }, VGPR_32:{ *:[i32] }:$voffset, sub1:{ *:[i32] }), SReg_128:{ *:[v4i32] }:$rsrc, SCSrc_b32:{ *:[i32] }:$soffset, (timm:{ *:[i32] }):$offset, (extract_cpol:{ *:[i32] } ?:{ *:[i32] }:$auxiliary), (extract_swz:{ *:[i1] } ?:{ *:[i32] }:$auxiliary))
        GIR_MakeTempReg, /*TempRegID*/0, /*TypeID*/GILLT_s64,
        GIR_BuildMI, /*InsnID*/1, /*Opcode*/GIMT_Encode2(TargetOpcode::REG_SEQUENCE),
        GIR_AddTempRegister, /*InsnID*/1, /*TempRegID*/0, /*TempRegFlags*/GIMT_Encode2(RegState::Define),
        GIR_Copy, /*NewInsnID*/1, /*OldInsnID*/0, /*OpIdx*/2, // vindex
        GIR_AddImm8, /*InsnID*/1, /*SubRegIndex*/3,
        GIR_Copy, /*NewInsnID*/1, /*OldInsnID*/0, /*OpIdx*/3, // voffset
        GIR_AddImm8, /*InsnID*/1, /*SubRegIndex*/11,
        GIR_ConstrainOperandRC, /*InsnID*/1, /*Op*/0, GIMT_Encode2(AMDGPU::VReg_64RegClassID),
        GIR_ConstrainOperandRC, /*InsnID*/1, /*Op*/1, GIMT_Encode2(AMDGPU::VGPR_32RegClassID),
        GIR_ConstrainOperandRC, /*InsnID*/1, /*Op*/3, GIMT_Encode2(AMDGPU::VGPR_32RegClassID),
        GIR_BuildMI, /*InsnID*/0, /*Opcode*/GIMT_Encode2(AMDGPU::BUFFER_STORE_DWORDX4_VBUFFER_BOTHEN_exact),
        GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/0, // vdata
        GIR_AddSimpleTempRegister, /*InsnID*/0, /*TempRegID*/0,
        GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/1, // rsrc
        GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/0, // soffset
        GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/5, // offset
        GIR_CustomOperandRenderer, /*InsnID*/0, /*OldInsnID*/0, /*OpIdx*/6, /*OperandRenderer*/GIMT_Encode2(GICR_renderExtractCPol), // auxiliary
        GIR_CustomOperandRenderer, /*InsnID*/0, /*OldInsnID*/0, /*OpIdx*/6, /*OperandRenderer*/GIMT_Encode2(GICR_renderExtractSWZ), // auxiliary
        GIR_MergeMemOperands, /*InsnID*/0, /*NumInsns*/1, /*MergeInsnID's*/0,
        GIR_ConstrainSelectedInstOperands, /*InsnID*/0,
        GIR_EraseFromParent, /*InsnID*/0,
        // GIR_Coverage, 4488,
        GIR_Done,
      // Label 6881: @505731
      GIM_Reject,
    // Label 6865: @505732
    GIM_Reject,
    // Label 6779: @505733
    GIM_Reject,
    // Label 133: @505734
    GIM_Try, /*On fail goto*//*Label 6882*/ GIMT_Encode4(506428),
      GIM_CheckType, /*MI*/0, /*Op*/0, /*Type*/GILLT_s32,
      GIM_CheckType, /*MI*/0, /*Op*/1, /*Type*/GILLT_v4s32,
      GIM_CheckType, /*MI*/0, /*Op*/2, /*Type*/GILLT_s32,
      GIM_CheckType, /*MI*/0, /*Op*/3, /*Type*/GILLT_s32,
      GIM_CheckType, /*MI*/0, /*Op*/4, /*Type*/GILLT_s32,
      GIM_Try, /*On fail goto*//*Label 6883*/ GIMT_Encode4(506075),
        GIM_CheckConstantInt8, /*MI*/0, /*Op*/2, 0,
        GIM_Try, /*On fail goto*//*Label 6884*/ GIMT_Encode4(505846), // Rule ID 4489 //
          GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasUnrestrictedSOffset),
          GIM_CheckConstantInt8, /*MI*/0, /*Op*/3, 0,
          // MIs[0] offset
          GIM_CheckIsImm, /*MI*/0, /*Op*/5,
          // MIs[0] auxiliary
          GIM_CheckIsImm, /*MI*/0, /*Op*/6,
          // MIs[0] Operand 7
          GIM_CheckLiteralInt, /*MI*/0, /*Op*/7, GIMT_Encode8(0),
          GIM_CheckComplexPattern, /*MI*/0, /*Op*/4, /*Renderer*/GIMT_Encode2(0), GIMT_Encode2(GICP_gi_buf_soffset),
          // (SIbuffer_store_byte i32:{ *:[i32] }:$vdata, v4i32:{ *:[v4i32] }:$rsrc, 0:{ *:[i32] }, 0:{ *:[i32] }, (BUFSOffset:{ *:[i32] } i32:{ *:[i32] }:$soffset), (timm:{ *:[i32] }):$offset, (timm:{ *:[i32] }):$auxiliary, 0:{ *:[i1] })  =>  (BUFFER_STORE_BYTE_OFFSET_exact anonymous_15037:{ *:[i32] }:$vdata, SReg_128:{ *:[v4i32] }:$rsrc, SCSrc_b32:{ *:[i32] }:$soffset, (timm:{ *:[i32] }):$offset, (extract_cpol:{ *:[i32] } ?:{ *:[i32] }:$auxiliary), (extract_swz:{ *:[i1] } ?:{ *:[i32] }:$auxiliary))
          GIR_BuildMI, /*InsnID*/0, /*Opcode*/GIMT_Encode2(AMDGPU::BUFFER_STORE_BYTE_OFFSET_exact),
          GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/0, // vdata
          GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/1, // rsrc
          GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/0, // soffset
          GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/5, // offset
          GIR_CustomOperandRenderer, /*InsnID*/0, /*OldInsnID*/0, /*OpIdx*/6, /*OperandRenderer*/GIMT_Encode2(GICR_renderExtractCPol), // auxiliary
          GIR_CustomOperandRenderer, /*InsnID*/0, /*OldInsnID*/0, /*OpIdx*/6, /*OperandRenderer*/GIMT_Encode2(GICR_renderExtractSWZ), // auxiliary
          GIR_MergeMemOperands, /*InsnID*/0, /*NumInsns*/1, /*MergeInsnID's*/0,
          GIR_ConstrainSelectedInstOperands, /*InsnID*/0,
          GIR_EraseFromParent, /*InsnID*/0,
          // GIR_Coverage, 4489,
          GIR_Done,
        // Label 6884: @505846
        GIM_Try, /*On fail goto*//*Label 6885*/ GIMT_Encode4(505921), // Rule ID 4493 //
          GIM_CheckConstantInt8, /*MI*/0, /*Op*/3, 0,
          // MIs[0] offset
          GIM_CheckIsImm, /*MI*/0, /*Op*/5,
          // MIs[0] auxiliary
          GIM_CheckIsImm, /*MI*/0, /*Op*/6,
          // MIs[0] Operand 7
          GIM_CheckLiteralInt, /*MI*/0, /*Op*/7, GIMT_Encode8(0),
          GIM_CheckComplexPattern, /*MI*/0, /*Op*/4, /*Renderer*/GIMT_Encode2(0), GIMT_Encode2(GICP_gi_buf_soffset),
          // (SIbuffer_store_byte i32:{ *:[i32] }:$vdata, v4i32:{ *:[v4i32] }:$rsrc, 0:{ *:[i32] }, 0:{ *:[i32] }, (BUFSOffset:{ *:[i32] } i32:{ *:[i32] }:$soffset), (timm:{ *:[i32] }):$offset, (timm:{ *:[i32] }):$auxiliary, 0:{ *:[i1] })  =>  (BUFFER_STORE_BYTE_VBUFFER_OFFSET_exact anonymous_15037:{ *:[i32] }:$vdata, SReg_128:{ *:[v4i32] }:$rsrc, SCSrc_b32:{ *:[i32] }:$soffset, (timm:{ *:[i32] }):$offset, (extract_cpol:{ *:[i32] } ?:{ *:[i32] }:$auxiliary), (extract_swz:{ *:[i1] } ?:{ *:[i32] }:$auxiliary))
          GIR_BuildMI, /*InsnID*/0, /*Opcode*/GIMT_Encode2(AMDGPU::BUFFER_STORE_BYTE_VBUFFER_OFFSET_exact),
          GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/0, // vdata
          GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/1, // rsrc
          GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/0, // soffset
          GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/5, // offset
          GIR_CustomOperandRenderer, /*InsnID*/0, /*OldInsnID*/0, /*OpIdx*/6, /*OperandRenderer*/GIMT_Encode2(GICR_renderExtractCPol), // auxiliary
          GIR_CustomOperandRenderer, /*InsnID*/0, /*OldInsnID*/0, /*OpIdx*/6, /*OperandRenderer*/GIMT_Encode2(GICR_renderExtractSWZ), // auxiliary
          GIR_MergeMemOperands, /*InsnID*/0, /*NumInsns*/1, /*MergeInsnID's*/0,
          GIR_ConstrainSelectedInstOperands, /*InsnID*/0,
          GIR_EraseFromParent, /*InsnID*/0,
          // GIR_Coverage, 4493,
          GIR_Done,
        // Label 6885: @505921
        GIM_Try, /*On fail goto*//*Label 6886*/ GIMT_Encode4(505999), // Rule ID 4490 //
          GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasUnrestrictedSOffset),
          // MIs[0] offset
          GIM_CheckIsImm, /*MI*/0, /*Op*/5,
          // MIs[0] auxiliary
          GIM_CheckIsImm, /*MI*/0, /*Op*/6,
          // MIs[0] Operand 7
          GIM_CheckLiteralInt, /*MI*/0, /*Op*/7, GIMT_Encode8(0),
          GIM_CheckComplexPattern, /*MI*/0, /*Op*/4, /*Renderer*/GIMT_Encode2(0), GIMT_Encode2(GICP_gi_buf_soffset),
          // (SIbuffer_store_byte i32:{ *:[i32] }:$vdata, v4i32:{ *:[v4i32] }:$rsrc, 0:{ *:[i32] }, i32:{ *:[i32] }:$voffset, (BUFSOffset:{ *:[i32] } i32:{ *:[i32] }:$soffset), (timm:{ *:[i32] }):$offset, (timm:{ *:[i32] }):$auxiliary, 0:{ *:[i1] })  =>  (BUFFER_STORE_BYTE_OFFEN_exact anonymous_15037:{ *:[i32] }:$vdata, VGPR_32:{ *:[i32] }:$voffset, SReg_128:{ *:[v4i32] }:$rsrc, SCSrc_b32:{ *:[i32] }:$soffset, (timm:{ *:[i32] }):$offset, (extract_cpol:{ *:[i32] } ?:{ *:[i32] }:$auxiliary), (extract_swz:{ *:[i1] } ?:{ *:[i32] }:$auxiliary))
          GIR_BuildMI, /*InsnID*/0, /*Opcode*/GIMT_Encode2(AMDGPU::BUFFER_STORE_BYTE_OFFEN_exact),
          GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/0, // vdata
          GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/3, // voffset
          GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/1, // rsrc
          GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/0, // soffset
          GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/5, // offset
          GIR_CustomOperandRenderer, /*InsnID*/0, /*OldInsnID*/0, /*OpIdx*/6, /*OperandRenderer*/GIMT_Encode2(GICR_renderExtractCPol), // auxiliary
          GIR_CustomOperandRenderer, /*InsnID*/0, /*OldInsnID*/0, /*OpIdx*/6, /*OperandRenderer*/GIMT_Encode2(GICR_renderExtractSWZ), // auxiliary
          GIR_MergeMemOperands, /*InsnID*/0, /*NumInsns*/1, /*MergeInsnID's*/0,
          GIR_ConstrainSelectedInstOperands, /*InsnID*/0,
          GIR_EraseFromParent, /*InsnID*/0,
          // GIR_Coverage, 4490,
          GIR_Done,
        // Label 6886: @505999
        GIM_Try, /*On fail goto*//*Label 6887*/ GIMT_Encode4(506074), // Rule ID 4494 //
          // MIs[0] offset
          GIM_CheckIsImm, /*MI*/0, /*Op*/5,
          // MIs[0] auxiliary
          GIM_CheckIsImm, /*MI*/0, /*Op*/6,
          // MIs[0] Operand 7
          GIM_CheckLiteralInt, /*MI*/0, /*Op*/7, GIMT_Encode8(0),
          GIM_CheckComplexPattern, /*MI*/0, /*Op*/4, /*Renderer*/GIMT_Encode2(0), GIMT_Encode2(GICP_gi_buf_soffset),
          // (SIbuffer_store_byte i32:{ *:[i32] }:$vdata, v4i32:{ *:[v4i32] }:$rsrc, 0:{ *:[i32] }, i32:{ *:[i32] }:$voffset, (BUFSOffset:{ *:[i32] } i32:{ *:[i32] }:$soffset), (timm:{ *:[i32] }):$offset, (timm:{ *:[i32] }):$auxiliary, 0:{ *:[i1] })  =>  (BUFFER_STORE_BYTE_VBUFFER_OFFEN_exact anonymous_15037:{ *:[i32] }:$vdata, VGPR_32:{ *:[i32] }:$voffset, SReg_128:{ *:[v4i32] }:$rsrc, SCSrc_b32:{ *:[i32] }:$soffset, (timm:{ *:[i32] }):$offset, (extract_cpol:{ *:[i32] } ?:{ *:[i32] }:$auxiliary), (extract_swz:{ *:[i1] } ?:{ *:[i32] }:$auxiliary))
          GIR_BuildMI, /*InsnID*/0, /*Opcode*/GIMT_Encode2(AMDGPU::BUFFER_STORE_BYTE_VBUFFER_OFFEN_exact),
          GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/0, // vdata
          GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/3, // voffset
          GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/1, // rsrc
          GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/0, // soffset
          GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/5, // offset
          GIR_CustomOperandRenderer, /*InsnID*/0, /*OldInsnID*/0, /*OpIdx*/6, /*OperandRenderer*/GIMT_Encode2(GICR_renderExtractCPol), // auxiliary
          GIR_CustomOperandRenderer, /*InsnID*/0, /*OldInsnID*/0, /*OpIdx*/6, /*OperandRenderer*/GIMT_Encode2(GICR_renderExtractSWZ), // auxiliary
          GIR_MergeMemOperands, /*InsnID*/0, /*NumInsns*/1, /*MergeInsnID's*/0,
          GIR_ConstrainSelectedInstOperands, /*InsnID*/0,
          GIR_EraseFromParent, /*InsnID*/0,
          // GIR_Coverage, 4494,
          GIR_Done,
        // Label 6887: @506074
        GIM_Reject,
      // Label 6883: @506075
      GIM_Try, /*On fail goto*//*Label 6888*/ GIMT_Encode4(506213),
        GIM_CheckConstantInt8, /*MI*/0, /*Op*/3, 0,
        GIM_CheckIsImm, /*MI*/0, /*Op*/5,
        GIM_CheckIsImm, /*MI*/0, /*Op*/6,
        GIM_CheckIsImm, /*MI*/0, /*Op*/7,
        GIM_Try, /*On fail goto*//*Label 6889*/ GIMT_Encode4(506154), // Rule ID 4491 //
          GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasUnrestrictedSOffset),
          GIM_CheckComplexPattern, /*MI*/0, /*Op*/4, /*Renderer*/GIMT_Encode2(0), GIMT_Encode2(GICP_gi_buf_soffset),
          // (SIbuffer_store_byte i32:{ *:[i32] }:$vdata, v4i32:{ *:[v4i32] }:$rsrc, i32:{ *:[i32] }:$vindex, 0:{ *:[i32] }, (BUFSOffset:{ *:[i32] } i32:{ *:[i32] }:$soffset), (timm:{ *:[i32] }):$offset, (timm:{ *:[i32] }):$auxiliary, (timm:{ *:[i1] }))  =>  (BUFFER_STORE_BYTE_IDXEN_exact anonymous_15037:{ *:[i32] }:$vdata, VGPR_32:{ *:[i32] }:$vindex, SReg_128:{ *:[v4i32] }:$rsrc, SCSrc_b32:{ *:[i32] }:$soffset, (timm:{ *:[i32] }):$offset, (extract_cpol:{ *:[i32] } ?:{ *:[i32] }:$auxiliary), (extract_swz:{ *:[i1] } ?:{ *:[i32] }:$auxiliary))
          GIR_BuildMI, /*InsnID*/0, /*Opcode*/GIMT_Encode2(AMDGPU::BUFFER_STORE_BYTE_IDXEN_exact),
          GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/0, // vdata
          GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/2, // vindex
          GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/1, // rsrc
          GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/0, // soffset
          GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/5, // offset
          GIR_CustomOperandRenderer, /*InsnID*/0, /*OldInsnID*/0, /*OpIdx*/6, /*OperandRenderer*/GIMT_Encode2(GICR_renderExtractCPol), // auxiliary
          GIR_CustomOperandRenderer, /*InsnID*/0, /*OldInsnID*/0, /*OpIdx*/6, /*OperandRenderer*/GIMT_Encode2(GICR_renderExtractSWZ), // auxiliary
          GIR_MergeMemOperands, /*InsnID*/0, /*NumInsns*/1, /*MergeInsnID's*/0,
          GIR_ConstrainSelectedInstOperands, /*InsnID*/0,
          GIR_EraseFromParent, /*InsnID*/0,
          // GIR_Coverage, 4491,
          GIR_Done,
        // Label 6889: @506154
        GIM_Try, /*On fail goto*//*Label 6890*/ GIMT_Encode4(506212), // Rule ID 4495 //
          GIM_CheckComplexPattern, /*MI*/0, /*Op*/4, /*Renderer*/GIMT_Encode2(0), GIMT_Encode2(GICP_gi_buf_soffset),
          // (SIbuffer_store_byte i32:{ *:[i32] }:$vdata, v4i32:{ *:[v4i32] }:$rsrc, i32:{ *:[i32] }:$vindex, 0:{ *:[i32] }, (BUFSOffset:{ *:[i32] } i32:{ *:[i32] }:$soffset), (timm:{ *:[i32] }):$offset, (timm:{ *:[i32] }):$auxiliary, (timm:{ *:[i1] }))  =>  (BUFFER_STORE_BYTE_VBUFFER_IDXEN_exact anonymous_15037:{ *:[i32] }:$vdata, VGPR_32:{ *:[i32] }:$vindex, SReg_128:{ *:[v4i32] }:$rsrc, SCSrc_b32:{ *:[i32] }:$soffset, (timm:{ *:[i32] }):$offset, (extract_cpol:{ *:[i32] } ?:{ *:[i32] }:$auxiliary), (extract_swz:{ *:[i1] } ?:{ *:[i32] }:$auxiliary))
          GIR_BuildMI, /*InsnID*/0, /*Opcode*/GIMT_Encode2(AMDGPU::BUFFER_STORE_BYTE_VBUFFER_IDXEN_exact),
          GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/0, // vdata
          GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/2, // vindex
          GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/1, // rsrc
          GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/0, // soffset
          GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/5, // offset
          GIR_CustomOperandRenderer, /*InsnID*/0, /*OldInsnID*/0, /*OpIdx*/6, /*OperandRenderer*/GIMT_Encode2(GICR_renderExtractCPol), // auxiliary
          GIR_CustomOperandRenderer, /*InsnID*/0, /*OldInsnID*/0, /*OpIdx*/6, /*OperandRenderer*/GIMT_Encode2(GICR_renderExtractSWZ), // auxiliary
          GIR_MergeMemOperands, /*InsnID*/0, /*NumInsns*/1, /*MergeInsnID's*/0,
          GIR_ConstrainSelectedInstOperands, /*InsnID*/0,
          GIR_EraseFromParent, /*InsnID*/0,
          // GIR_Coverage, 4495,
          GIR_Done,
        // Label 6890: @506212
        GIM_Reject,
      // Label 6888: @506213
      GIM_Try, /*On fail goto*//*Label 6891*/ GIMT_Encode4(506427),
        GIM_CheckIsImm, /*MI*/0, /*Op*/5,
        GIM_CheckIsImm, /*MI*/0, /*Op*/6,
        GIM_CheckIsImm, /*MI*/0, /*Op*/7,
        GIM_Try, /*On fail goto*//*Label 6892*/ GIMT_Encode4(506328), // Rule ID 4492 //
          GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasUnrestrictedSOffset),
          GIM_CheckComplexPattern, /*MI*/0, /*Op*/4, /*Renderer*/GIMT_Encode2(0), GIMT_Encode2(GICP_gi_buf_soffset),
          // (SIbuffer_store_byte i32:{ *:[i32] }:$vdata, v4i32:{ *:[v4i32] }:$rsrc, i32:{ *:[i32] }:$vindex, i32:{ *:[i32] }:$voffset, (BUFSOffset:{ *:[i32] } i32:{ *:[i32] }:$soffset), (timm:{ *:[i32] }):$offset, (timm:{ *:[i32] }):$auxiliary, (timm:{ *:[i1] }))  =>  (BUFFER_STORE_BYTE_BOTHEN_exact anonymous_15037:{ *:[i32] }:$vdata, (REG_SEQUENCE:{ *:[i64] } VReg_64:{ *:[i32] }, VGPR_32:{ *:[i32] }:$vindex, sub0:{ *:[i32] }, VGPR_32:{ *:[i32] }:$voffset, sub1:{ *:[i32] }), SReg_128:{ *:[v4i32] }:$rsrc, SCSrc_b32:{ *:[i32] }:$soffset, (timm:{ *:[i32] }):$offset, (extract_cpol:{ *:[i32] } ?:{ *:[i32] }:$auxiliary), (extract_swz:{ *:[i1] } ?:{ *:[i32] }:$auxiliary))
          GIR_MakeTempReg, /*TempRegID*/0, /*TypeID*/GILLT_s64,
          GIR_BuildMI, /*InsnID*/1, /*Opcode*/GIMT_Encode2(TargetOpcode::REG_SEQUENCE),
          GIR_AddTempRegister, /*InsnID*/1, /*TempRegID*/0, /*TempRegFlags*/GIMT_Encode2(RegState::Define),
          GIR_Copy, /*NewInsnID*/1, /*OldInsnID*/0, /*OpIdx*/2, // vindex
          GIR_AddImm8, /*InsnID*/1, /*SubRegIndex*/3,
          GIR_Copy, /*NewInsnID*/1, /*OldInsnID*/0, /*OpIdx*/3, // voffset
          GIR_AddImm8, /*InsnID*/1, /*SubRegIndex*/11,
          GIR_ConstrainOperandRC, /*InsnID*/1, /*Op*/0, GIMT_Encode2(AMDGPU::VReg_64RegClassID),
          GIR_ConstrainOperandRC, /*InsnID*/1, /*Op*/1, GIMT_Encode2(AMDGPU::VGPR_32RegClassID),
          GIR_ConstrainOperandRC, /*InsnID*/1, /*Op*/3, GIMT_Encode2(AMDGPU::VGPR_32RegClassID),
          GIR_BuildMI, /*InsnID*/0, /*Opcode*/GIMT_Encode2(AMDGPU::BUFFER_STORE_BYTE_BOTHEN_exact),
          GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/0, // vdata
          GIR_AddSimpleTempRegister, /*InsnID*/0, /*TempRegID*/0,
          GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/1, // rsrc
          GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/0, // soffset
          GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/5, // offset
          GIR_CustomOperandRenderer, /*InsnID*/0, /*OldInsnID*/0, /*OpIdx*/6, /*OperandRenderer*/GIMT_Encode2(GICR_renderExtractCPol), // auxiliary
          GIR_CustomOperandRenderer, /*InsnID*/0, /*OldInsnID*/0, /*OpIdx*/6, /*OperandRenderer*/GIMT_Encode2(GICR_renderExtractSWZ), // auxiliary
          GIR_MergeMemOperands, /*InsnID*/0, /*NumInsns*/1, /*MergeInsnID's*/0,
          GIR_ConstrainSelectedInstOperands, /*InsnID*/0,
          GIR_EraseFromParent, /*InsnID*/0,
          // GIR_Coverage, 4492,
          GIR_Done,
        // Label 6892: @506328
        GIM_Try, /*On fail goto*//*Label 6893*/ GIMT_Encode4(506426), // Rule ID 4496 //
          GIM_CheckComplexPattern, /*MI*/0, /*Op*/4, /*Renderer*/GIMT_Encode2(0), GIMT_Encode2(GICP_gi_buf_soffset),
          // (SIbuffer_store_byte i32:{ *:[i32] }:$vdata, v4i32:{ *:[v4i32] }:$rsrc, i32:{ *:[i32] }:$vindex, i32:{ *:[i32] }:$voffset, (BUFSOffset:{ *:[i32] } i32:{ *:[i32] }:$soffset), (timm:{ *:[i32] }):$offset, (timm:{ *:[i32] }):$auxiliary, (timm:{ *:[i1] }))  =>  (BUFFER_STORE_BYTE_VBUFFER_BOTHEN_exact anonymous_15037:{ *:[i32] }:$vdata, (REG_SEQUENCE:{ *:[i64] } VReg_64:{ *:[i32] }, VGPR_32:{ *:[i32] }:$vindex, sub0:{ *:[i32] }, VGPR_32:{ *:[i32] }:$voffset, sub1:{ *:[i32] }), SReg_128:{ *:[v4i32] }:$rsrc, SCSrc_b32:{ *:[i32] }:$soffset, (timm:{ *:[i32] }):$offset, (extract_cpol:{ *:[i32] } ?:{ *:[i32] }:$auxiliary), (extract_swz:{ *:[i1] } ?:{ *:[i32] }:$auxiliary))
          GIR_MakeTempReg, /*TempRegID*/0, /*TypeID*/GILLT_s64,
          GIR_BuildMI, /*InsnID*/1, /*Opcode*/GIMT_Encode2(TargetOpcode::REG_SEQUENCE),
          GIR_AddTempRegister, /*InsnID*/1, /*TempRegID*/0, /*TempRegFlags*/GIMT_Encode2(RegState::Define),
          GIR_Copy, /*NewInsnID*/1, /*OldInsnID*/0, /*OpIdx*/2, // vindex
          GIR_AddImm8, /*InsnID*/1, /*SubRegIndex*/3,
          GIR_Copy, /*NewInsnID*/1, /*OldInsnID*/0, /*OpIdx*/3, // voffset
          GIR_AddImm8, /*InsnID*/1, /*SubRegIndex*/11,
          GIR_ConstrainOperandRC, /*InsnID*/1, /*Op*/0, GIMT_Encode2(AMDGPU::VReg_64RegClassID),
          GIR_ConstrainOperandRC, /*InsnID*/1, /*Op*/1, GIMT_Encode2(AMDGPU::VGPR_32RegClassID),
          GIR_ConstrainOperandRC, /*InsnID*/1, /*Op*/3, GIMT_Encode2(AMDGPU::VGPR_32RegClassID),
          GIR_BuildMI, /*InsnID*/0, /*Opcode*/GIMT_Encode2(AMDGPU::BUFFER_STORE_BYTE_VBUFFER_BOTHEN_exact),
          GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/0, // vdata
          GIR_AddSimpleTempRegister, /*InsnID*/0, /*TempRegID*/0,
          GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/1, // rsrc
          GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/0, // soffset
          GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/5, // offset
          GIR_CustomOperandRenderer, /*InsnID*/0, /*OldInsnID*/0, /*OpIdx*/6, /*OperandRenderer*/GIMT_Encode2(GICR_renderExtractCPol), // auxiliary
          GIR_CustomOperandRenderer, /*InsnID*/0, /*OldInsnID*/0, /*OpIdx*/6, /*OperandRenderer*/GIMT_Encode2(GICR_renderExtractSWZ), // auxiliary
          GIR_MergeMemOperands, /*InsnID*/0, /*NumInsns*/1, /*MergeInsnID's*/0,
          GIR_ConstrainSelectedInstOperands, /*InsnID*/0,
          GIR_EraseFromParent, /*InsnID*/0,
          // GIR_Coverage, 4496,
          GIR_Done,
        // Label 6893: @506426
        GIM_Reject,
      // Label 6891: @506427
      GIM_Reject,
    // Label 6882: @506428
    GIM_Reject,
    // Label 134: @506429
    GIM_SwitchType, /*MI*/0, /*Op*/0, /*[*/GIMT_Encode2(9), GIMT_Encode2(18), /*)*//*default:*//*Label 6898*/ GIMT_Encode4(512040),
    /*GILLT_s32*//*Label 6894*/ GIMT_Encode4(506476), GIMT_Encode4(0), GIMT_Encode4(0),
    /*GILLT_v2s32*//*Label 6895*/ GIMT_Encode4(507867), GIMT_Encode4(0),
    /*GILLT_v3s32*//*Label 6896*/ GIMT_Encode4(509258), GIMT_Encode4(0), GIMT_Encode4(0),
    /*GILLT_v4s32*//*Label 6897*/ GIMT_Encode4(510649),
    // Label 6894: @506476
    GIM_Try, /*On fail goto*//*Label 6899*/ GIMT_Encode4(507866),
      GIM_CheckType, /*MI*/0, /*Op*/1, /*Type*/GILLT_v4s32,
      GIM_CheckType, /*MI*/0, /*Op*/2, /*Type*/GILLT_s32,
      GIM_CheckType, /*MI*/0, /*Op*/3, /*Type*/GILLT_s32,
      GIM_CheckType, /*MI*/0, /*Op*/4, /*Type*/GILLT_s32,
      GIM_Try, /*On fail goto*//*Label 6900*/ GIMT_Encode4(506579), // Rule ID 4233 //
        GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasUnrestrictedSOffset),
        GIM_CheckConstantInt8, /*MI*/0, /*Op*/2, 0,
        GIM_CheckConstantInt8, /*MI*/0, /*Op*/3, 0,
        // MIs[0] offset
        GIM_CheckIsImm, /*MI*/0, /*Op*/5,
        // MIs[0] auxiliary
        GIM_CheckIsImm, /*MI*/0, /*Op*/6,
        // MIs[0] Operand 7
        GIM_CheckLiteralInt, /*MI*/0, /*Op*/7, GIMT_Encode8(0),
        GIM_CheckComplexPattern, /*MI*/0, /*Op*/4, /*Renderer*/GIMT_Encode2(0), GIMT_Encode2(GICP_gi_buf_soffset),
        // (SIbuffer_store_format f32:{ *:[f32] }:$vdata, v4i32:{ *:[v4i32] }:$rsrc, 0:{ *:[i32] }, 0:{ *:[i32] }, (BUFSOffset:{ *:[i32] } i32:{ *:[i32] }:$soffset), (timm:{ *:[i32] }):$offset, (timm:{ *:[i32] }):$auxiliary, 0:{ *:[i1] })  =>  (BUFFER_STORE_FORMAT_X_OFFSET_exact anonymous_15037:{ *:[f32] }:$vdata, SReg_128:{ *:[v4i32] }:$rsrc, SCSrc_b32:{ *:[i32] }:$soffset, (timm:{ *:[i32] }):$offset, (extract_cpol:{ *:[i32] } ?:{ *:[i32] }:$auxiliary), (extract_swz:{ *:[i1] } ?:{ *:[i32] }:$auxiliary))
        GIR_BuildMI, /*InsnID*/0, /*Opcode*/GIMT_Encode2(AMDGPU::BUFFER_STORE_FORMAT_X_OFFSET_exact),
        GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/0, // vdata
        GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/1, // rsrc
        GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/0, // soffset
        GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/5, // offset
        GIR_CustomOperandRenderer, /*InsnID*/0, /*OldInsnID*/0, /*OpIdx*/6, /*OperandRenderer*/GIMT_Encode2(GICR_renderExtractCPol), // auxiliary
        GIR_CustomOperandRenderer, /*InsnID*/0, /*OldInsnID*/0, /*OpIdx*/6, /*OperandRenderer*/GIMT_Encode2(GICR_renderExtractSWZ), // auxiliary
        GIR_MergeMemOperands, /*InsnID*/0, /*NumInsns*/1, /*MergeInsnID's*/0,
        GIR_ConstrainSelectedInstOperands, /*InsnID*/0,
        GIR_EraseFromParent, /*InsnID*/0,
        // GIR_Coverage, 4233,
        GIR_Done,
      // Label 6900: @506579
      GIM_Try, /*On fail goto*//*Label 6901*/ GIMT_Encode4(506658), // Rule ID 4237 //
        GIM_CheckConstantInt8, /*MI*/0, /*Op*/2, 0,
        GIM_CheckConstantInt8, /*MI*/0, /*Op*/3, 0,
        // MIs[0] offset
        GIM_CheckIsImm, /*MI*/0, /*Op*/5,
        // MIs[0] auxiliary
        GIM_CheckIsImm, /*MI*/0, /*Op*/6,
        // MIs[0] Operand 7
        GIM_CheckLiteralInt, /*MI*/0, /*Op*/7, GIMT_Encode8(0),
        GIM_CheckComplexPattern, /*MI*/0, /*Op*/4, /*Renderer*/GIMT_Encode2(0), GIMT_Encode2(GICP_gi_buf_soffset),
        // (SIbuffer_store_format f32:{ *:[f32] }:$vdata, v4i32:{ *:[v4i32] }:$rsrc, 0:{ *:[i32] }, 0:{ *:[i32] }, (BUFSOffset:{ *:[i32] } i32:{ *:[i32] }:$soffset), (timm:{ *:[i32] }):$offset, (timm:{ *:[i32] }):$auxiliary, 0:{ *:[i1] })  =>  (BUFFER_STORE_FORMAT_X_VBUFFER_OFFSET_exact anonymous_15037:{ *:[f32] }:$vdata, SReg_128:{ *:[v4i32] }:$rsrc, SCSrc_b32:{ *:[i32] }:$soffset, (timm:{ *:[i32] }):$offset, (extract_cpol:{ *:[i32] } ?:{ *:[i32] }:$auxiliary), (extract_swz:{ *:[i1] } ?:{ *:[i32] }:$auxiliary))
        GIR_BuildMI, /*InsnID*/0, /*Opcode*/GIMT_Encode2(AMDGPU::BUFFER_STORE_FORMAT_X_VBUFFER_OFFSET_exact),
        GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/0, // vdata
        GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/1, // rsrc
        GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/0, // soffset
        GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/5, // offset
        GIR_CustomOperandRenderer, /*InsnID*/0, /*OldInsnID*/0, /*OpIdx*/6, /*OperandRenderer*/GIMT_Encode2(GICR_renderExtractCPol), // auxiliary
        GIR_CustomOperandRenderer, /*InsnID*/0, /*OldInsnID*/0, /*OpIdx*/6, /*OperandRenderer*/GIMT_Encode2(GICR_renderExtractSWZ), // auxiliary
        GIR_MergeMemOperands, /*InsnID*/0, /*NumInsns*/1, /*MergeInsnID's*/0,
        GIR_ConstrainSelectedInstOperands, /*InsnID*/0,
        GIR_EraseFromParent, /*InsnID*/0,
        // GIR_Coverage, 4237,
        GIR_Done,
      // Label 6901: @506658
      GIM_Try, /*On fail goto*//*Label 6902*/ GIMT_Encode4(506740), // Rule ID 4241 //
        GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasUnrestrictedSOffset),
        GIM_CheckConstantInt8, /*MI*/0, /*Op*/2, 0,
        GIM_CheckConstantInt8, /*MI*/0, /*Op*/3, 0,
        // MIs[0] offset
        GIM_CheckIsImm, /*MI*/0, /*Op*/5,
        // MIs[0] auxiliary
        GIM_CheckIsImm, /*MI*/0, /*Op*/6,
        // MIs[0] Operand 7
        GIM_CheckLiteralInt, /*MI*/0, /*Op*/7, GIMT_Encode8(0),
        GIM_CheckComplexPattern, /*MI*/0, /*Op*/4, /*Renderer*/GIMT_Encode2(0), GIMT_Encode2(GICP_gi_buf_soffset),
        // (SIbuffer_store_format i32:{ *:[i32] }:$vdata, v4i32:{ *:[v4i32] }:$rsrc, 0:{ *:[i32] }, 0:{ *:[i32] }, (BUFSOffset:{ *:[i32] } i32:{ *:[i32] }:$soffset), (timm:{ *:[i32] }):$offset, (timm:{ *:[i32] }):$auxiliary, 0:{ *:[i1] })  =>  (BUFFER_STORE_FORMAT_X_OFFSET_exact anonymous_15037:{ *:[i32] }:$vdata, SReg_128:{ *:[v4i32] }:$rsrc, SCSrc_b32:{ *:[i32] }:$soffset, (timm:{ *:[i32] }):$offset, (extract_cpol:{ *:[i32] } ?:{ *:[i32] }:$auxiliary), (extract_swz:{ *:[i1] } ?:{ *:[i32] }:$auxiliary))
        GIR_BuildMI, /*InsnID*/0, /*Opcode*/GIMT_Encode2(AMDGPU::BUFFER_STORE_FORMAT_X_OFFSET_exact),
        GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/0, // vdata
        GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/1, // rsrc
        GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/0, // soffset
        GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/5, // offset
        GIR_CustomOperandRenderer, /*InsnID*/0, /*OldInsnID*/0, /*OpIdx*/6, /*OperandRenderer*/GIMT_Encode2(GICR_renderExtractCPol), // auxiliary
        GIR_CustomOperandRenderer, /*InsnID*/0, /*OldInsnID*/0, /*OpIdx*/6, /*OperandRenderer*/GIMT_Encode2(GICR_renderExtractSWZ), // auxiliary
        GIR_MergeMemOperands, /*InsnID*/0, /*NumInsns*/1, /*MergeInsnID's*/0,
        GIR_ConstrainSelectedInstOperands, /*InsnID*/0,
        GIR_EraseFromParent, /*InsnID*/0,
        // GIR_Coverage, 4241,
        GIR_Done,
      // Label 6902: @506740
      GIM_Try, /*On fail goto*//*Label 6903*/ GIMT_Encode4(506819), // Rule ID 4245 //
        GIM_CheckConstantInt8, /*MI*/0, /*Op*/2, 0,
        GIM_CheckConstantInt8, /*MI*/0, /*Op*/3, 0,
        // MIs[0] offset
        GIM_CheckIsImm, /*MI*/0, /*Op*/5,
        // MIs[0] auxiliary
        GIM_CheckIsImm, /*MI*/0, /*Op*/6,
        // MIs[0] Operand 7
        GIM_CheckLiteralInt, /*MI*/0, /*Op*/7, GIMT_Encode8(0),
        GIM_CheckComplexPattern, /*MI*/0, /*Op*/4, /*Renderer*/GIMT_Encode2(0), GIMT_Encode2(GICP_gi_buf_soffset),
        // (SIbuffer_store_format i32:{ *:[i32] }:$vdata, v4i32:{ *:[v4i32] }:$rsrc, 0:{ *:[i32] }, 0:{ *:[i32] }, (BUFSOffset:{ *:[i32] } i32:{ *:[i32] }:$soffset), (timm:{ *:[i32] }):$offset, (timm:{ *:[i32] }):$auxiliary, 0:{ *:[i1] })  =>  (BUFFER_STORE_FORMAT_X_VBUFFER_OFFSET_exact anonymous_15037:{ *:[i32] }:$vdata, SReg_128:{ *:[v4i32] }:$rsrc, SCSrc_b32:{ *:[i32] }:$soffset, (timm:{ *:[i32] }):$offset, (extract_cpol:{ *:[i32] } ?:{ *:[i32] }:$auxiliary), (extract_swz:{ *:[i1] } ?:{ *:[i32] }:$auxiliary))
        GIR_BuildMI, /*InsnID*/0, /*Opcode*/GIMT_Encode2(AMDGPU::BUFFER_STORE_FORMAT_X_VBUFFER_OFFSET_exact),
        GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/0, // vdata
        GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/1, // rsrc
        GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/0, // soffset
        GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/5, // offset
        GIR_CustomOperandRenderer, /*InsnID*/0, /*OldInsnID*/0, /*OpIdx*/6, /*OperandRenderer*/GIMT_Encode2(GICR_renderExtractCPol), // auxiliary
        GIR_CustomOperandRenderer, /*InsnID*/0, /*OldInsnID*/0, /*OpIdx*/6, /*OperandRenderer*/GIMT_Encode2(GICR_renderExtractSWZ), // auxiliary
        GIR_MergeMemOperands, /*InsnID*/0, /*NumInsns*/1, /*MergeInsnID's*/0,
        GIR_ConstrainSelectedInstOperands, /*InsnID*/0,
        GIR_EraseFromParent, /*InsnID*/0,
        // GIR_Coverage, 4245,
        GIR_Done,
      // Label 6903: @506819
      GIM_Try, /*On fail goto*//*Label 6904*/ GIMT_Encode4(506901), // Rule ID 4234 //
        GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasUnrestrictedSOffset),
        GIM_CheckConstantInt8, /*MI*/0, /*Op*/2, 0,
        // MIs[0] offset
        GIM_CheckIsImm, /*MI*/0, /*Op*/5,
        // MIs[0] auxiliary
        GIM_CheckIsImm, /*MI*/0, /*Op*/6,
        // MIs[0] Operand 7
        GIM_CheckLiteralInt, /*MI*/0, /*Op*/7, GIMT_Encode8(0),
        GIM_CheckComplexPattern, /*MI*/0, /*Op*/4, /*Renderer*/GIMT_Encode2(0), GIMT_Encode2(GICP_gi_buf_soffset),
        // (SIbuffer_store_format f32:{ *:[f32] }:$vdata, v4i32:{ *:[v4i32] }:$rsrc, 0:{ *:[i32] }, i32:{ *:[i32] }:$voffset, (BUFSOffset:{ *:[i32] } i32:{ *:[i32] }:$soffset), (timm:{ *:[i32] }):$offset, (timm:{ *:[i32] }):$auxiliary, 0:{ *:[i1] })  =>  (BUFFER_STORE_FORMAT_X_OFFEN_exact anonymous_15037:{ *:[f32] }:$vdata, VGPR_32:{ *:[i32] }:$voffset, SReg_128:{ *:[v4i32] }:$rsrc, SCSrc_b32:{ *:[i32] }:$soffset, (timm:{ *:[i32] }):$offset, (extract_cpol:{ *:[i32] } ?:{ *:[i32] }:$auxiliary), (extract_swz:{ *:[i1] } ?:{ *:[i32] }:$auxiliary))
        GIR_BuildMI, /*InsnID*/0, /*Opcode*/GIMT_Encode2(AMDGPU::BUFFER_STORE_FORMAT_X_OFFEN_exact),
        GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/0, // vdata
        GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/3, // voffset
        GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/1, // rsrc
        GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/0, // soffset
        GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/5, // offset
        GIR_CustomOperandRenderer, /*InsnID*/0, /*OldInsnID*/0, /*OpIdx*/6, /*OperandRenderer*/GIMT_Encode2(GICR_renderExtractCPol), // auxiliary
        GIR_CustomOperandRenderer, /*InsnID*/0, /*OldInsnID*/0, /*OpIdx*/6, /*OperandRenderer*/GIMT_Encode2(GICR_renderExtractSWZ), // auxiliary
        GIR_MergeMemOperands, /*InsnID*/0, /*NumInsns*/1, /*MergeInsnID's*/0,
        GIR_ConstrainSelectedInstOperands, /*InsnID*/0,
        GIR_EraseFromParent, /*InsnID*/0,
        // GIR_Coverage, 4234,
        GIR_Done,
      // Label 6904: @506901
      GIM_Try, /*On fail goto*//*Label 6905*/ GIMT_Encode4(506980), // Rule ID 4238 //
        GIM_CheckConstantInt8, /*MI*/0, /*Op*/2, 0,
        // MIs[0] offset
        GIM_CheckIsImm, /*MI*/0, /*Op*/5,
        // MIs[0] auxiliary
        GIM_CheckIsImm, /*MI*/0, /*Op*/6,
        // MIs[0] Operand 7
        GIM_CheckLiteralInt, /*MI*/0, /*Op*/7, GIMT_Encode8(0),
        GIM_CheckComplexPattern, /*MI*/0, /*Op*/4, /*Renderer*/GIMT_Encode2(0), GIMT_Encode2(GICP_gi_buf_soffset),
        // (SIbuffer_store_format f32:{ *:[f32] }:$vdata, v4i32:{ *:[v4i32] }:$rsrc, 0:{ *:[i32] }, i32:{ *:[i32] }:$voffset, (BUFSOffset:{ *:[i32] } i32:{ *:[i32] }:$soffset), (timm:{ *:[i32] }):$offset, (timm:{ *:[i32] }):$auxiliary, 0:{ *:[i1] })  =>  (BUFFER_STORE_FORMAT_X_VBUFFER_OFFEN_exact anonymous_15037:{ *:[f32] }:$vdata, VGPR_32:{ *:[i32] }:$voffset, SReg_128:{ *:[v4i32] }:$rsrc, SCSrc_b32:{ *:[i32] }:$soffset, (timm:{ *:[i32] }):$offset, (extract_cpol:{ *:[i32] } ?:{ *:[i32] }:$auxiliary), (extract_swz:{ *:[i1] } ?:{ *:[i32] }:$auxiliary))
        GIR_BuildMI, /*InsnID*/0, /*Opcode*/GIMT_Encode2(AMDGPU::BUFFER_STORE_FORMAT_X_VBUFFER_OFFEN_exact),
        GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/0, // vdata
        GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/3, // voffset
        GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/1, // rsrc
        GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/0, // soffset
        GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/5, // offset
        GIR_CustomOperandRenderer, /*InsnID*/0, /*OldInsnID*/0, /*OpIdx*/6, /*OperandRenderer*/GIMT_Encode2(GICR_renderExtractCPol), // auxiliary
        GIR_CustomOperandRenderer, /*InsnID*/0, /*OldInsnID*/0, /*OpIdx*/6, /*OperandRenderer*/GIMT_Encode2(GICR_renderExtractSWZ), // auxiliary
        GIR_MergeMemOperands, /*InsnID*/0, /*NumInsns*/1, /*MergeInsnID's*/0,
        GIR_ConstrainSelectedInstOperands, /*InsnID*/0,
        GIR_EraseFromParent, /*InsnID*/0,
        // GIR_Coverage, 4238,
        GIR_Done,
      // Label 6905: @506980
      GIM_Try, /*On fail goto*//*Label 6906*/ GIMT_Encode4(507062), // Rule ID 4242 //
        GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasUnrestrictedSOffset),
        GIM_CheckConstantInt8, /*MI*/0, /*Op*/2, 0,
        // MIs[0] offset
        GIM_CheckIsImm, /*MI*/0, /*Op*/5,
        // MIs[0] auxiliary
        GIM_CheckIsImm, /*MI*/0, /*Op*/6,
        // MIs[0] Operand 7
        GIM_CheckLiteralInt, /*MI*/0, /*Op*/7, GIMT_Encode8(0),
        GIM_CheckComplexPattern, /*MI*/0, /*Op*/4, /*Renderer*/GIMT_Encode2(0), GIMT_Encode2(GICP_gi_buf_soffset),
        // (SIbuffer_store_format i32:{ *:[i32] }:$vdata, v4i32:{ *:[v4i32] }:$rsrc, 0:{ *:[i32] }, i32:{ *:[i32] }:$voffset, (BUFSOffset:{ *:[i32] } i32:{ *:[i32] }:$soffset), (timm:{ *:[i32] }):$offset, (timm:{ *:[i32] }):$auxiliary, 0:{ *:[i1] })  =>  (BUFFER_STORE_FORMAT_X_OFFEN_exact anonymous_15037:{ *:[i32] }:$vdata, VGPR_32:{ *:[i32] }:$voffset, SReg_128:{ *:[v4i32] }:$rsrc, SCSrc_b32:{ *:[i32] }:$soffset, (timm:{ *:[i32] }):$offset, (extract_cpol:{ *:[i32] } ?:{ *:[i32] }:$auxiliary), (extract_swz:{ *:[i1] } ?:{ *:[i32] }:$auxiliary))
        GIR_BuildMI, /*InsnID*/0, /*Opcode*/GIMT_Encode2(AMDGPU::BUFFER_STORE_FORMAT_X_OFFEN_exact),
        GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/0, // vdata
        GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/3, // voffset
        GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/1, // rsrc
        GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/0, // soffset
        GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/5, // offset
        GIR_CustomOperandRenderer, /*InsnID*/0, /*OldInsnID*/0, /*OpIdx*/6, /*OperandRenderer*/GIMT_Encode2(GICR_renderExtractCPol), // auxiliary
        GIR_CustomOperandRenderer, /*InsnID*/0, /*OldInsnID*/0, /*OpIdx*/6, /*OperandRenderer*/GIMT_Encode2(GICR_renderExtractSWZ), // auxiliary
        GIR_MergeMemOperands, /*InsnID*/0, /*NumInsns*/1, /*MergeInsnID's*/0,
        GIR_ConstrainSelectedInstOperands, /*InsnID*/0,
        GIR_EraseFromParent, /*InsnID*/0,
        // GIR_Coverage, 4242,
        GIR_Done,
      // Label 6906: @507062
      GIM_Try, /*On fail goto*//*Label 6907*/ GIMT_Encode4(507141), // Rule ID 4246 //
        GIM_CheckConstantInt8, /*MI*/0, /*Op*/2, 0,
        // MIs[0] offset
        GIM_CheckIsImm, /*MI*/0, /*Op*/5,
        // MIs[0] auxiliary
        GIM_CheckIsImm, /*MI*/0, /*Op*/6,
        // MIs[0] Operand 7
        GIM_CheckLiteralInt, /*MI*/0, /*Op*/7, GIMT_Encode8(0),
        GIM_CheckComplexPattern, /*MI*/0, /*Op*/4, /*Renderer*/GIMT_Encode2(0), GIMT_Encode2(GICP_gi_buf_soffset),
        // (SIbuffer_store_format i32:{ *:[i32] }:$vdata, v4i32:{ *:[v4i32] }:$rsrc, 0:{ *:[i32] }, i32:{ *:[i32] }:$voffset, (BUFSOffset:{ *:[i32] } i32:{ *:[i32] }:$soffset), (timm:{ *:[i32] }):$offset, (timm:{ *:[i32] }):$auxiliary, 0:{ *:[i1] })  =>  (BUFFER_STORE_FORMAT_X_VBUFFER_OFFEN_exact anonymous_15037:{ *:[i32] }:$vdata, VGPR_32:{ *:[i32] }:$voffset, SReg_128:{ *:[v4i32] }:$rsrc, SCSrc_b32:{ *:[i32] }:$soffset, (timm:{ *:[i32] }):$offset, (extract_cpol:{ *:[i32] } ?:{ *:[i32] }:$auxiliary), (extract_swz:{ *:[i1] } ?:{ *:[i32] }:$auxiliary))
        GIR_BuildMI, /*InsnID*/0, /*Opcode*/GIMT_Encode2(AMDGPU::BUFFER_STORE_FORMAT_X_VBUFFER_OFFEN_exact),
        GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/0, // vdata
        GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/3, // voffset
        GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/1, // rsrc
        GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/0, // soffset
        GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/5, // offset
        GIR_CustomOperandRenderer, /*InsnID*/0, /*OldInsnID*/0, /*OpIdx*/6, /*OperandRenderer*/GIMT_Encode2(GICR_renderExtractCPol), // auxiliary
        GIR_CustomOperandRenderer, /*InsnID*/0, /*OldInsnID*/0, /*OpIdx*/6, /*OperandRenderer*/GIMT_Encode2(GICR_renderExtractSWZ), // auxiliary
        GIR_MergeMemOperands, /*InsnID*/0, /*NumInsns*/1, /*MergeInsnID's*/0,
        GIR_ConstrainSelectedInstOperands, /*InsnID*/0,
        GIR_EraseFromParent, /*InsnID*/0,
        // GIR_Coverage, 4246,
        GIR_Done,
      // Label 6907: @507141
      GIM_Try, /*On fail goto*//*Label 6908*/ GIMT_Encode4(507215), // Rule ID 4235 //
        GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasUnrestrictedSOffset),
        GIM_CheckConstantInt8, /*MI*/0, /*Op*/3, 0,
        // MIs[0] offset
        GIM_CheckIsImm, /*MI*/0, /*Op*/5,
        // MIs[0] auxiliary
        GIM_CheckIsImm, /*MI*/0, /*Op*/6,
        // MIs[0] Operand 7
        GIM_CheckIsImm, /*MI*/0, /*Op*/7,
        GIM_CheckComplexPattern, /*MI*/0, /*Op*/4, /*Renderer*/GIMT_Encode2(0), GIMT_Encode2(GICP_gi_buf_soffset),
        // (SIbuffer_store_format f32:{ *:[f32] }:$vdata, v4i32:{ *:[v4i32] }:$rsrc, i32:{ *:[i32] }:$vindex, 0:{ *:[i32] }, (BUFSOffset:{ *:[i32] } i32:{ *:[i32] }:$soffset), (timm:{ *:[i32] }):$offset, (timm:{ *:[i32] }):$auxiliary, (timm:{ *:[i1] }))  =>  (BUFFER_STORE_FORMAT_X_IDXEN_exact anonymous_15037:{ *:[f32] }:$vdata, VGPR_32:{ *:[i32] }:$vindex, SReg_128:{ *:[v4i32] }:$rsrc, SCSrc_b32:{ *:[i32] }:$soffset, (timm:{ *:[i32] }):$offset, (extract_cpol:{ *:[i32] } ?:{ *:[i32] }:$auxiliary), (extract_swz:{ *:[i1] } ?:{ *:[i32] }:$auxiliary))
        GIR_BuildMI, /*InsnID*/0, /*Opcode*/GIMT_Encode2(AMDGPU::BUFFER_STORE_FORMAT_X_IDXEN_exact),
        GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/0, // vdata
        GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/2, // vindex
        GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/1, // rsrc
        GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/0, // soffset
        GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/5, // offset
        GIR_CustomOperandRenderer, /*InsnID*/0, /*OldInsnID*/0, /*OpIdx*/6, /*OperandRenderer*/GIMT_Encode2(GICR_renderExtractCPol), // auxiliary
        GIR_CustomOperandRenderer, /*InsnID*/0, /*OldInsnID*/0, /*OpIdx*/6, /*OperandRenderer*/GIMT_Encode2(GICR_renderExtractSWZ), // auxiliary
        GIR_MergeMemOperands, /*InsnID*/0, /*NumInsns*/1, /*MergeInsnID's*/0,
        GIR_ConstrainSelectedInstOperands, /*InsnID*/0,
        GIR_EraseFromParent, /*InsnID*/0,
        // GIR_Coverage, 4235,
        GIR_Done,
      // Label 6908: @507215
      GIM_Try, /*On fail goto*//*Label 6909*/ GIMT_Encode4(507286), // Rule ID 4239 //
        GIM_CheckConstantInt8, /*MI*/0, /*Op*/3, 0,
        // MIs[0] offset
        GIM_CheckIsImm, /*MI*/0, /*Op*/5,
        // MIs[0] auxiliary
        GIM_CheckIsImm, /*MI*/0, /*Op*/6,
        // MIs[0] Operand 7
        GIM_CheckIsImm, /*MI*/0, /*Op*/7,
        GIM_CheckComplexPattern, /*MI*/0, /*Op*/4, /*Renderer*/GIMT_Encode2(0), GIMT_Encode2(GICP_gi_buf_soffset),
        // (SIbuffer_store_format f32:{ *:[f32] }:$vdata, v4i32:{ *:[v4i32] }:$rsrc, i32:{ *:[i32] }:$vindex, 0:{ *:[i32] }, (BUFSOffset:{ *:[i32] } i32:{ *:[i32] }:$soffset), (timm:{ *:[i32] }):$offset, (timm:{ *:[i32] }):$auxiliary, (timm:{ *:[i1] }))  =>  (BUFFER_STORE_FORMAT_X_VBUFFER_IDXEN_exact anonymous_15037:{ *:[f32] }:$vdata, VGPR_32:{ *:[i32] }:$vindex, SReg_128:{ *:[v4i32] }:$rsrc, SCSrc_b32:{ *:[i32] }:$soffset, (timm:{ *:[i32] }):$offset, (extract_cpol:{ *:[i32] } ?:{ *:[i32] }:$auxiliary), (extract_swz:{ *:[i1] } ?:{ *:[i32] }:$auxiliary))
        GIR_BuildMI, /*InsnID*/0, /*Opcode*/GIMT_Encode2(AMDGPU::BUFFER_STORE_FORMAT_X_VBUFFER_IDXEN_exact),
        GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/0, // vdata
        GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/2, // vindex
        GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/1, // rsrc
        GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/0, // soffset
        GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/5, // offset
        GIR_CustomOperandRenderer, /*InsnID*/0, /*OldInsnID*/0, /*OpIdx*/6, /*OperandRenderer*/GIMT_Encode2(GICR_renderExtractCPol), // auxiliary
        GIR_CustomOperandRenderer, /*InsnID*/0, /*OldInsnID*/0, /*OpIdx*/6, /*OperandRenderer*/GIMT_Encode2(GICR_renderExtractSWZ), // auxiliary
        GIR_MergeMemOperands, /*InsnID*/0, /*NumInsns*/1, /*MergeInsnID's*/0,
        GIR_ConstrainSelectedInstOperands, /*InsnID*/0,
        GIR_EraseFromParent, /*InsnID*/0,
        // GIR_Coverage, 4239,
        GIR_Done,
      // Label 6909: @507286
      GIM_Try, /*On fail goto*//*Label 6910*/ GIMT_Encode4(507360), // Rule ID 4243 //
        GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasUnrestrictedSOffset),
        GIM_CheckConstantInt8, /*MI*/0, /*Op*/3, 0,
        // MIs[0] offset
        GIM_CheckIsImm, /*MI*/0, /*Op*/5,
        // MIs[0] auxiliary
        GIM_CheckIsImm, /*MI*/0, /*Op*/6,
        // MIs[0] Operand 7
        GIM_CheckIsImm, /*MI*/0, /*Op*/7,
        GIM_CheckComplexPattern, /*MI*/0, /*Op*/4, /*Renderer*/GIMT_Encode2(0), GIMT_Encode2(GICP_gi_buf_soffset),
        // (SIbuffer_store_format i32:{ *:[i32] }:$vdata, v4i32:{ *:[v4i32] }:$rsrc, i32:{ *:[i32] }:$vindex, 0:{ *:[i32] }, (BUFSOffset:{ *:[i32] } i32:{ *:[i32] }:$soffset), (timm:{ *:[i32] }):$offset, (timm:{ *:[i32] }):$auxiliary, (timm:{ *:[i1] }))  =>  (BUFFER_STORE_FORMAT_X_IDXEN_exact anonymous_15037:{ *:[i32] }:$vdata, VGPR_32:{ *:[i32] }:$vindex, SReg_128:{ *:[v4i32] }:$rsrc, SCSrc_b32:{ *:[i32] }:$soffset, (timm:{ *:[i32] }):$offset, (extract_cpol:{ *:[i32] } ?:{ *:[i32] }:$auxiliary), (extract_swz:{ *:[i1] } ?:{ *:[i32] }:$auxiliary))
        GIR_BuildMI, /*InsnID*/0, /*Opcode*/GIMT_Encode2(AMDGPU::BUFFER_STORE_FORMAT_X_IDXEN_exact),
        GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/0, // vdata
        GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/2, // vindex
        GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/1, // rsrc
        GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/0, // soffset
        GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/5, // offset
        GIR_CustomOperandRenderer, /*InsnID*/0, /*OldInsnID*/0, /*OpIdx*/6, /*OperandRenderer*/GIMT_Encode2(GICR_renderExtractCPol), // auxiliary
        GIR_CustomOperandRenderer, /*InsnID*/0, /*OldInsnID*/0, /*OpIdx*/6, /*OperandRenderer*/GIMT_Encode2(GICR_renderExtractSWZ), // auxiliary
        GIR_MergeMemOperands, /*InsnID*/0, /*NumInsns*/1, /*MergeInsnID's*/0,
        GIR_ConstrainSelectedInstOperands, /*InsnID*/0,
        GIR_EraseFromParent, /*InsnID*/0,
        // GIR_Coverage, 4243,
        GIR_Done,
      // Label 6910: @507360
      GIM_Try, /*On fail goto*//*Label 6911*/ GIMT_Encode4(507431), // Rule ID 4247 //
        GIM_CheckConstantInt8, /*MI*/0, /*Op*/3, 0,
        // MIs[0] offset
        GIM_CheckIsImm, /*MI*/0, /*Op*/5,
        // MIs[0] auxiliary
        GIM_CheckIsImm, /*MI*/0, /*Op*/6,
        // MIs[0] Operand 7
        GIM_CheckIsImm, /*MI*/0, /*Op*/7,
        GIM_CheckComplexPattern, /*MI*/0, /*Op*/4, /*Renderer*/GIMT_Encode2(0), GIMT_Encode2(GICP_gi_buf_soffset),
        // (SIbuffer_store_format i32:{ *:[i32] }:$vdata, v4i32:{ *:[v4i32] }:$rsrc, i32:{ *:[i32] }:$vindex, 0:{ *:[i32] }, (BUFSOffset:{ *:[i32] } i32:{ *:[i32] }:$soffset), (timm:{ *:[i32] }):$offset, (timm:{ *:[i32] }):$auxiliary, (timm:{ *:[i1] }))  =>  (BUFFER_STORE_FORMAT_X_VBUFFER_IDXEN_exact anonymous_15037:{ *:[i32] }:$vdata, VGPR_32:{ *:[i32] }:$vindex, SReg_128:{ *:[v4i32] }:$rsrc, SCSrc_b32:{ *:[i32] }:$soffset, (timm:{ *:[i32] }):$offset, (extract_cpol:{ *:[i32] } ?:{ *:[i32] }:$auxiliary), (extract_swz:{ *:[i1] } ?:{ *:[i32] }:$auxiliary))
        GIR_BuildMI, /*InsnID*/0, /*Opcode*/GIMT_Encode2(AMDGPU::BUFFER_STORE_FORMAT_X_VBUFFER_IDXEN_exact),
        GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/0, // vdata
        GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/2, // vindex
        GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/1, // rsrc
        GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/0, // soffset
        GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/5, // offset
        GIR_CustomOperandRenderer, /*InsnID*/0, /*OldInsnID*/0, /*OpIdx*/6, /*OperandRenderer*/GIMT_Encode2(GICR_renderExtractCPol), // auxiliary
        GIR_CustomOperandRenderer, /*InsnID*/0, /*OldInsnID*/0, /*OpIdx*/6, /*OperandRenderer*/GIMT_Encode2(GICR_renderExtractSWZ), // auxiliary
        GIR_MergeMemOperands, /*InsnID*/0, /*NumInsns*/1, /*MergeInsnID's*/0,
        GIR_ConstrainSelectedInstOperands, /*InsnID*/0,
        GIR_EraseFromParent, /*InsnID*/0,
        // GIR_Coverage, 4247,
        GIR_Done,
      // Label 6911: @507431
      GIM_Try, /*On fail goto*//*Label 6912*/ GIMT_Encode4(507541), // Rule ID 4236 //
        GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasUnrestrictedSOffset),
        // MIs[0] offset
        GIM_CheckIsImm, /*MI*/0, /*Op*/5,
        // MIs[0] auxiliary
        GIM_CheckIsImm, /*MI*/0, /*Op*/6,
        // MIs[0] Operand 7
        GIM_CheckIsImm, /*MI*/0, /*Op*/7,
        GIM_CheckComplexPattern, /*MI*/0, /*Op*/4, /*Renderer*/GIMT_Encode2(0), GIMT_Encode2(GICP_gi_buf_soffset),
        // (SIbuffer_store_format f32:{ *:[f32] }:$vdata, v4i32:{ *:[v4i32] }:$rsrc, i32:{ *:[i32] }:$vindex, i32:{ *:[i32] }:$voffset, (BUFSOffset:{ *:[i32] } i32:{ *:[i32] }:$soffset), (timm:{ *:[i32] }):$offset, (timm:{ *:[i32] }):$auxiliary, (timm:{ *:[i1] }))  =>  (BUFFER_STORE_FORMAT_X_BOTHEN_exact anonymous_15037:{ *:[f32] }:$vdata, (REG_SEQUENCE:{ *:[i64] } VReg_64:{ *:[i32] }, VGPR_32:{ *:[i32] }:$vindex, sub0:{ *:[i32] }, VGPR_32:{ *:[i32] }:$voffset, sub1:{ *:[i32] }), SReg_128:{ *:[v4i32] }:$rsrc, SCSrc_b32:{ *:[i32] }:$soffset, (timm:{ *:[i32] }):$offset, (extract_cpol:{ *:[i32] } ?:{ *:[i32] }:$auxiliary), (extract_swz:{ *:[i1] } ?:{ *:[i32] }:$auxiliary))
        GIR_MakeTempReg, /*TempRegID*/0, /*TypeID*/GILLT_s64,
        GIR_BuildMI, /*InsnID*/1, /*Opcode*/GIMT_Encode2(TargetOpcode::REG_SEQUENCE),
        GIR_AddTempRegister, /*InsnID*/1, /*TempRegID*/0, /*TempRegFlags*/GIMT_Encode2(RegState::Define),
        GIR_Copy, /*NewInsnID*/1, /*OldInsnID*/0, /*OpIdx*/2, // vindex
        GIR_AddImm8, /*InsnID*/1, /*SubRegIndex*/3,
        GIR_Copy, /*NewInsnID*/1, /*OldInsnID*/0, /*OpIdx*/3, // voffset
        GIR_AddImm8, /*InsnID*/1, /*SubRegIndex*/11,
        GIR_ConstrainOperandRC, /*InsnID*/1, /*Op*/0, GIMT_Encode2(AMDGPU::VReg_64RegClassID),
        GIR_ConstrainOperandRC, /*InsnID*/1, /*Op*/1, GIMT_Encode2(AMDGPU::VGPR_32RegClassID),
        GIR_ConstrainOperandRC, /*InsnID*/1, /*Op*/3, GIMT_Encode2(AMDGPU::VGPR_32RegClassID),
        GIR_BuildMI, /*InsnID*/0, /*Opcode*/GIMT_Encode2(AMDGPU::BUFFER_STORE_FORMAT_X_BOTHEN_exact),
        GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/0, // vdata
        GIR_AddSimpleTempRegister, /*InsnID*/0, /*TempRegID*/0,
        GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/1, // rsrc
        GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/0, // soffset
        GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/5, // offset
        GIR_CustomOperandRenderer, /*InsnID*/0, /*OldInsnID*/0, /*OpIdx*/6, /*OperandRenderer*/GIMT_Encode2(GICR_renderExtractCPol), // auxiliary
        GIR_CustomOperandRenderer, /*InsnID*/0, /*OldInsnID*/0, /*OpIdx*/6, /*OperandRenderer*/GIMT_Encode2(GICR_renderExtractSWZ), // auxiliary
        GIR_MergeMemOperands, /*InsnID*/0, /*NumInsns*/1, /*MergeInsnID's*/0,
        GIR_ConstrainSelectedInstOperands, /*InsnID*/0,
        GIR_EraseFromParent, /*InsnID*/0,
        // GIR_Coverage, 4236,
        GIR_Done,
      // Label 6912: @507541
      GIM_Try, /*On fail goto*//*Label 6913*/ GIMT_Encode4(507648), // Rule ID 4240 //
        // MIs[0] offset
        GIM_CheckIsImm, /*MI*/0, /*Op*/5,
        // MIs[0] auxiliary
        GIM_CheckIsImm, /*MI*/0, /*Op*/6,
        // MIs[0] Operand 7
        GIM_CheckIsImm, /*MI*/0, /*Op*/7,
        GIM_CheckComplexPattern, /*MI*/0, /*Op*/4, /*Renderer*/GIMT_Encode2(0), GIMT_Encode2(GICP_gi_buf_soffset),
        // (SIbuffer_store_format f32:{ *:[f32] }:$vdata, v4i32:{ *:[v4i32] }:$rsrc, i32:{ *:[i32] }:$vindex, i32:{ *:[i32] }:$voffset, (BUFSOffset:{ *:[i32] } i32:{ *:[i32] }:$soffset), (timm:{ *:[i32] }):$offset, (timm:{ *:[i32] }):$auxiliary, (timm:{ *:[i1] }))  =>  (BUFFER_STORE_FORMAT_X_VBUFFER_BOTHEN_exact anonymous_15037:{ *:[f32] }:$vdata, (REG_SEQUENCE:{ *:[i64] } VReg_64:{ *:[i32] }, VGPR_32:{ *:[i32] }:$vindex, sub0:{ *:[i32] }, VGPR_32:{ *:[i32] }:$voffset, sub1:{ *:[i32] }), SReg_128:{ *:[v4i32] }:$rsrc, SCSrc_b32:{ *:[i32] }:$soffset, (timm:{ *:[i32] }):$offset, (extract_cpol:{ *:[i32] } ?:{ *:[i32] }:$auxiliary), (extract_swz:{ *:[i1] } ?:{ *:[i32] }:$auxiliary))
        GIR_MakeTempReg, /*TempRegID*/0, /*TypeID*/GILLT_s64,
        GIR_BuildMI, /*InsnID*/1, /*Opcode*/GIMT_Encode2(TargetOpcode::REG_SEQUENCE),
        GIR_AddTempRegister, /*InsnID*/1, /*TempRegID*/0, /*TempRegFlags*/GIMT_Encode2(RegState::Define),
        GIR_Copy, /*NewInsnID*/1, /*OldInsnID*/0, /*OpIdx*/2, // vindex
        GIR_AddImm8, /*InsnID*/1, /*SubRegIndex*/3,
        GIR_Copy, /*NewInsnID*/1, /*OldInsnID*/0, /*OpIdx*/3, // voffset
        GIR_AddImm8, /*InsnID*/1, /*SubRegIndex*/11,
        GIR_ConstrainOperandRC, /*InsnID*/1, /*Op*/0, GIMT_Encode2(AMDGPU::VReg_64RegClassID),
        GIR_ConstrainOperandRC, /*InsnID*/1, /*Op*/1, GIMT_Encode2(AMDGPU::VGPR_32RegClassID),
        GIR_ConstrainOperandRC, /*InsnID*/1, /*Op*/3, GIMT_Encode2(AMDGPU::VGPR_32RegClassID),
        GIR_BuildMI, /*InsnID*/0, /*Opcode*/GIMT_Encode2(AMDGPU::BUFFER_STORE_FORMAT_X_VBUFFER_BOTHEN_exact),
        GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/0, // vdata
        GIR_AddSimpleTempRegister, /*InsnID*/0, /*TempRegID*/0,
        GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/1, // rsrc
        GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/0, // soffset
        GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/5, // offset
        GIR_CustomOperandRenderer, /*InsnID*/0, /*OldInsnID*/0, /*OpIdx*/6, /*OperandRenderer*/GIMT_Encode2(GICR_renderExtractCPol), // auxiliary
        GIR_CustomOperandRenderer, /*InsnID*/0, /*OldInsnID*/0, /*OpIdx*/6, /*OperandRenderer*/GIMT_Encode2(GICR_renderExtractSWZ), // auxiliary
        GIR_MergeMemOperands, /*InsnID*/0, /*NumInsns*/1, /*MergeInsnID's*/0,
        GIR_ConstrainSelectedInstOperands, /*InsnID*/0,
        GIR_EraseFromParent, /*InsnID*/0,
        // GIR_Coverage, 4240,
        GIR_Done,
      // Label 6913: @507648
      GIM_Try, /*On fail goto*//*Label 6914*/ GIMT_Encode4(507758), // Rule ID 4244 //
        GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasUnrestrictedSOffset),
        // MIs[0] offset
        GIM_CheckIsImm, /*MI*/0, /*Op*/5,
        // MIs[0] auxiliary
        GIM_CheckIsImm, /*MI*/0, /*Op*/6,
        // MIs[0] Operand 7
        GIM_CheckIsImm, /*MI*/0, /*Op*/7,
        GIM_CheckComplexPattern, /*MI*/0, /*Op*/4, /*Renderer*/GIMT_Encode2(0), GIMT_Encode2(GICP_gi_buf_soffset),
        // (SIbuffer_store_format i32:{ *:[i32] }:$vdata, v4i32:{ *:[v4i32] }:$rsrc, i32:{ *:[i32] }:$vindex, i32:{ *:[i32] }:$voffset, (BUFSOffset:{ *:[i32] } i32:{ *:[i32] }:$soffset), (timm:{ *:[i32] }):$offset, (timm:{ *:[i32] }):$auxiliary, (timm:{ *:[i1] }))  =>  (BUFFER_STORE_FORMAT_X_BOTHEN_exact anonymous_15037:{ *:[i32] }:$vdata, (REG_SEQUENCE:{ *:[i64] } VReg_64:{ *:[i32] }, VGPR_32:{ *:[i32] }:$vindex, sub0:{ *:[i32] }, VGPR_32:{ *:[i32] }:$voffset, sub1:{ *:[i32] }), SReg_128:{ *:[v4i32] }:$rsrc, SCSrc_b32:{ *:[i32] }:$soffset, (timm:{ *:[i32] }):$offset, (extract_cpol:{ *:[i32] } ?:{ *:[i32] }:$auxiliary), (extract_swz:{ *:[i1] } ?:{ *:[i32] }:$auxiliary))
        GIR_MakeTempReg, /*TempRegID*/0, /*TypeID*/GILLT_s64,
        GIR_BuildMI, /*InsnID*/1, /*Opcode*/GIMT_Encode2(TargetOpcode::REG_SEQUENCE),
        GIR_AddTempRegister, /*InsnID*/1, /*TempRegID*/0, /*TempRegFlags*/GIMT_Encode2(RegState::Define),
        GIR_Copy, /*NewInsnID*/1, /*OldInsnID*/0, /*OpIdx*/2, // vindex
        GIR_AddImm8, /*InsnID*/1, /*SubRegIndex*/3,
        GIR_Copy, /*NewInsnID*/1, /*OldInsnID*/0, /*OpIdx*/3, // voffset
        GIR_AddImm8, /*InsnID*/1, /*SubRegIndex*/11,
        GIR_ConstrainOperandRC, /*InsnID*/1, /*Op*/0, GIMT_Encode2(AMDGPU::VReg_64RegClassID),
        GIR_ConstrainOperandRC, /*InsnID*/1, /*Op*/1, GIMT_Encode2(AMDGPU::VGPR_32RegClassID),
        GIR_ConstrainOperandRC, /*InsnID*/1, /*Op*/3, GIMT_Encode2(AMDGPU::VGPR_32RegClassID),
        GIR_BuildMI, /*InsnID*/0, /*Opcode*/GIMT_Encode2(AMDGPU::BUFFER_STORE_FORMAT_X_BOTHEN_exact),
        GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/0, // vdata
        GIR_AddSimpleTempRegister, /*InsnID*/0, /*TempRegID*/0,
        GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/1, // rsrc
        GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/0, // soffset
        GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/5, // offset
        GIR_CustomOperandRenderer, /*InsnID*/0, /*OldInsnID*/0, /*OpIdx*/6, /*OperandRenderer*/GIMT_Encode2(GICR_renderExtractCPol), // auxiliary
        GIR_CustomOperandRenderer, /*InsnID*/0, /*OldInsnID*/0, /*OpIdx*/6, /*OperandRenderer*/GIMT_Encode2(GICR_renderExtractSWZ), // auxiliary
        GIR_MergeMemOperands, /*InsnID*/0, /*NumInsns*/1, /*MergeInsnID's*/0,
        GIR_ConstrainSelectedInstOperands, /*InsnID*/0,
        GIR_EraseFromParent, /*InsnID*/0,
        // GIR_Coverage, 4244,
        GIR_Done,
      // Label 6914: @507758
      GIM_Try, /*On fail goto*//*Label 6915*/ GIMT_Encode4(507865), // Rule ID 4248 //
        // MIs[0] offset
        GIM_CheckIsImm, /*MI*/0, /*Op*/5,
        // MIs[0] auxiliary
        GIM_CheckIsImm, /*MI*/0, /*Op*/6,
        // MIs[0] Operand 7
        GIM_CheckIsImm, /*MI*/0, /*Op*/7,
        GIM_CheckComplexPattern, /*MI*/0, /*Op*/4, /*Renderer*/GIMT_Encode2(0), GIMT_Encode2(GICP_gi_buf_soffset),
        // (SIbuffer_store_format i32:{ *:[i32] }:$vdata, v4i32:{ *:[v4i32] }:$rsrc, i32:{ *:[i32] }:$vindex, i32:{ *:[i32] }:$voffset, (BUFSOffset:{ *:[i32] } i32:{ *:[i32] }:$soffset), (timm:{ *:[i32] }):$offset, (timm:{ *:[i32] }):$auxiliary, (timm:{ *:[i1] }))  =>  (BUFFER_STORE_FORMAT_X_VBUFFER_BOTHEN_exact anonymous_15037:{ *:[i32] }:$vdata, (REG_SEQUENCE:{ *:[i64] } VReg_64:{ *:[i32] }, VGPR_32:{ *:[i32] }:$vindex, sub0:{ *:[i32] }, VGPR_32:{ *:[i32] }:$voffset, sub1:{ *:[i32] }), SReg_128:{ *:[v4i32] }:$rsrc, SCSrc_b32:{ *:[i32] }:$soffset, (timm:{ *:[i32] }):$offset, (extract_cpol:{ *:[i32] } ?:{ *:[i32] }:$auxiliary), (extract_swz:{ *:[i1] } ?:{ *:[i32] }:$auxiliary))
        GIR_MakeTempReg, /*TempRegID*/0, /*TypeID*/GILLT_s64,
        GIR_BuildMI, /*InsnID*/1, /*Opcode*/GIMT_Encode2(TargetOpcode::REG_SEQUENCE),
        GIR_AddTempRegister, /*InsnID*/1, /*TempRegID*/0, /*TempRegFlags*/GIMT_Encode2(RegState::Define),
        GIR_Copy, /*NewInsnID*/1, /*OldInsnID*/0, /*OpIdx*/2, // vindex
        GIR_AddImm8, /*InsnID*/1, /*SubRegIndex*/3,
        GIR_Copy, /*NewInsnID*/1, /*OldInsnID*/0, /*OpIdx*/3, // voffset
        GIR_AddImm8, /*InsnID*/1, /*SubRegIndex*/11,
        GIR_ConstrainOperandRC, /*InsnID*/1, /*Op*/0, GIMT_Encode2(AMDGPU::VReg_64RegClassID),
        GIR_ConstrainOperandRC, /*InsnID*/1, /*Op*/1, GIMT_Encode2(AMDGPU::VGPR_32RegClassID),
        GIR_ConstrainOperandRC, /*InsnID*/1, /*Op*/3, GIMT_Encode2(AMDGPU::VGPR_32RegClassID),
        GIR_BuildMI, /*InsnID*/0, /*Opcode*/GIMT_Encode2(AMDGPU::BUFFER_STORE_FORMAT_X_VBUFFER_BOTHEN_exact),
        GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/0, // vdata
        GIR_AddSimpleTempRegister, /*InsnID*/0, /*TempRegID*/0,
        GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/1, // rsrc
        GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/0, // soffset
        GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/5, // offset
        GIR_CustomOperandRenderer, /*InsnID*/0, /*OldInsnID*/0, /*OpIdx*/6, /*OperandRenderer*/GIMT_Encode2(GICR_renderExtractCPol), // auxiliary
        GIR_CustomOperandRenderer, /*InsnID*/0, /*OldInsnID*/0, /*OpIdx*/6, /*OperandRenderer*/GIMT_Encode2(GICR_renderExtractSWZ), // auxiliary
        GIR_MergeMemOperands, /*InsnID*/0, /*NumInsns*/1, /*MergeInsnID's*/0,
        GIR_ConstrainSelectedInstOperands, /*InsnID*/0,
        GIR_EraseFromParent, /*InsnID*/0,
        // GIR_Coverage, 4248,
        GIR_Done,
      // Label 6915: @507865
      GIM_Reject,
    // Label 6899: @507866
    GIM_Reject,
    // Label 6895: @507867
    GIM_Try, /*On fail goto*//*Label 6916*/ GIMT_Encode4(509257),
      GIM_CheckType, /*MI*/0, /*Op*/1, /*Type*/GILLT_v4s32,
      GIM_CheckType, /*MI*/0, /*Op*/2, /*Type*/GILLT_s32,
      GIM_CheckType, /*MI*/0, /*Op*/3, /*Type*/GILLT_s32,
      GIM_CheckType, /*MI*/0, /*Op*/4, /*Type*/GILLT_s32,
      GIM_Try, /*On fail goto*//*Label 6917*/ GIMT_Encode4(507970), // Rule ID 4249 //
        GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasUnrestrictedSOffset),
        GIM_CheckConstantInt8, /*MI*/0, /*Op*/2, 0,
        GIM_CheckConstantInt8, /*MI*/0, /*Op*/3, 0,
        // MIs[0] offset
        GIM_CheckIsImm, /*MI*/0, /*Op*/5,
        // MIs[0] auxiliary
        GIM_CheckIsImm, /*MI*/0, /*Op*/6,
        // MIs[0] Operand 7
        GIM_CheckLiteralInt, /*MI*/0, /*Op*/7, GIMT_Encode8(0),
        GIM_CheckComplexPattern, /*MI*/0, /*Op*/4, /*Renderer*/GIMT_Encode2(0), GIMT_Encode2(GICP_gi_buf_soffset),
        // (SIbuffer_store_format v2f32:{ *:[v2f32] }:$vdata, v4i32:{ *:[v4i32] }:$rsrc, 0:{ *:[i32] }, 0:{ *:[i32] }, (BUFSOffset:{ *:[i32] } i32:{ *:[i32] }:$soffset), (timm:{ *:[i32] }):$offset, (timm:{ *:[i32] }):$auxiliary, 0:{ *:[i1] })  =>  (BUFFER_STORE_FORMAT_XY_OFFSET_exact anonymous_15036:{ *:[v2f32] }:$vdata, SReg_128:{ *:[v4i32] }:$rsrc, SCSrc_b32:{ *:[i32] }:$soffset, (timm:{ *:[i32] }):$offset, (extract_cpol:{ *:[i32] } ?:{ *:[i32] }:$auxiliary), (extract_swz:{ *:[i1] } ?:{ *:[i32] }:$auxiliary))
        GIR_BuildMI, /*InsnID*/0, /*Opcode*/GIMT_Encode2(AMDGPU::BUFFER_STORE_FORMAT_XY_OFFSET_exact),
        GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/0, // vdata
        GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/1, // rsrc
        GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/0, // soffset
        GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/5, // offset
        GIR_CustomOperandRenderer, /*InsnID*/0, /*OldInsnID*/0, /*OpIdx*/6, /*OperandRenderer*/GIMT_Encode2(GICR_renderExtractCPol), // auxiliary
        GIR_CustomOperandRenderer, /*InsnID*/0, /*OldInsnID*/0, /*OpIdx*/6, /*OperandRenderer*/GIMT_Encode2(GICR_renderExtractSWZ), // auxiliary
        GIR_MergeMemOperands, /*InsnID*/0, /*NumInsns*/1, /*MergeInsnID's*/0,
        GIR_ConstrainSelectedInstOperands, /*InsnID*/0,
        GIR_EraseFromParent, /*InsnID*/0,
        // GIR_Coverage, 4249,
        GIR_Done,
      // Label 6917: @507970
      GIM_Try, /*On fail goto*//*Label 6918*/ GIMT_Encode4(508049), // Rule ID 4253 //
        GIM_CheckConstantInt8, /*MI*/0, /*Op*/2, 0,
        GIM_CheckConstantInt8, /*MI*/0, /*Op*/3, 0,
        // MIs[0] offset
        GIM_CheckIsImm, /*MI*/0, /*Op*/5,
        // MIs[0] auxiliary
        GIM_CheckIsImm, /*MI*/0, /*Op*/6,
        // MIs[0] Operand 7
        GIM_CheckLiteralInt, /*MI*/0, /*Op*/7, GIMT_Encode8(0),
        GIM_CheckComplexPattern, /*MI*/0, /*Op*/4, /*Renderer*/GIMT_Encode2(0), GIMT_Encode2(GICP_gi_buf_soffset),
        // (SIbuffer_store_format v2f32:{ *:[v2f32] }:$vdata, v4i32:{ *:[v4i32] }:$rsrc, 0:{ *:[i32] }, 0:{ *:[i32] }, (BUFSOffset:{ *:[i32] } i32:{ *:[i32] }:$soffset), (timm:{ *:[i32] }):$offset, (timm:{ *:[i32] }):$auxiliary, 0:{ *:[i1] })  =>  (BUFFER_STORE_FORMAT_XY_VBUFFER_OFFSET_exact anonymous_15036:{ *:[v2f32] }:$vdata, SReg_128:{ *:[v4i32] }:$rsrc, SCSrc_b32:{ *:[i32] }:$soffset, (timm:{ *:[i32] }):$offset, (extract_cpol:{ *:[i32] } ?:{ *:[i32] }:$auxiliary), (extract_swz:{ *:[i1] } ?:{ *:[i32] }:$auxiliary))
        GIR_BuildMI, /*InsnID*/0, /*Opcode*/GIMT_Encode2(AMDGPU::BUFFER_STORE_FORMAT_XY_VBUFFER_OFFSET_exact),
        GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/0, // vdata
        GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/1, // rsrc
        GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/0, // soffset
        GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/5, // offset
        GIR_CustomOperandRenderer, /*InsnID*/0, /*OldInsnID*/0, /*OpIdx*/6, /*OperandRenderer*/GIMT_Encode2(GICR_renderExtractCPol), // auxiliary
        GIR_CustomOperandRenderer, /*InsnID*/0, /*OldInsnID*/0, /*OpIdx*/6, /*OperandRenderer*/GIMT_Encode2(GICR_renderExtractSWZ), // auxiliary
        GIR_MergeMemOperands, /*InsnID*/0, /*NumInsns*/1, /*MergeInsnID's*/0,
        GIR_ConstrainSelectedInstOperands, /*InsnID*/0,
        GIR_EraseFromParent, /*InsnID*/0,
        // GIR_Coverage, 4253,
        GIR_Done,
      // Label 6918: @508049
      GIM_Try, /*On fail goto*//*Label 6919*/ GIMT_Encode4(508131), // Rule ID 4257 //
        GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasUnrestrictedSOffset),
        GIM_CheckConstantInt8, /*MI*/0, /*Op*/2, 0,
        GIM_CheckConstantInt8, /*MI*/0, /*Op*/3, 0,
        // MIs[0] offset
        GIM_CheckIsImm, /*MI*/0, /*Op*/5,
        // MIs[0] auxiliary
        GIM_CheckIsImm, /*MI*/0, /*Op*/6,
        // MIs[0] Operand 7
        GIM_CheckLiteralInt, /*MI*/0, /*Op*/7, GIMT_Encode8(0),
        GIM_CheckComplexPattern, /*MI*/0, /*Op*/4, /*Renderer*/GIMT_Encode2(0), GIMT_Encode2(GICP_gi_buf_soffset),
        // (SIbuffer_store_format v2i32:{ *:[v2i32] }:$vdata, v4i32:{ *:[v4i32] }:$rsrc, 0:{ *:[i32] }, 0:{ *:[i32] }, (BUFSOffset:{ *:[i32] } i32:{ *:[i32] }:$soffset), (timm:{ *:[i32] }):$offset, (timm:{ *:[i32] }):$auxiliary, 0:{ *:[i1] })  =>  (BUFFER_STORE_FORMAT_XY_OFFSET_exact anonymous_15036:{ *:[v2i32] }:$vdata, SReg_128:{ *:[v4i32] }:$rsrc, SCSrc_b32:{ *:[i32] }:$soffset, (timm:{ *:[i32] }):$offset, (extract_cpol:{ *:[i32] } ?:{ *:[i32] }:$auxiliary), (extract_swz:{ *:[i1] } ?:{ *:[i32] }:$auxiliary))
        GIR_BuildMI, /*InsnID*/0, /*Opcode*/GIMT_Encode2(AMDGPU::BUFFER_STORE_FORMAT_XY_OFFSET_exact),
        GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/0, // vdata
        GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/1, // rsrc
        GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/0, // soffset
        GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/5, // offset
        GIR_CustomOperandRenderer, /*InsnID*/0, /*OldInsnID*/0, /*OpIdx*/6, /*OperandRenderer*/GIMT_Encode2(GICR_renderExtractCPol), // auxiliary
        GIR_CustomOperandRenderer, /*InsnID*/0, /*OldInsnID*/0, /*OpIdx*/6, /*OperandRenderer*/GIMT_Encode2(GICR_renderExtractSWZ), // auxiliary
        GIR_MergeMemOperands, /*InsnID*/0, /*NumInsns*/1, /*MergeInsnID's*/0,
        GIR_ConstrainSelectedInstOperands, /*InsnID*/0,
        GIR_EraseFromParent, /*InsnID*/0,
        // GIR_Coverage, 4257,
        GIR_Done,
      // Label 6919: @508131
      GIM_Try, /*On fail goto*//*Label 6920*/ GIMT_Encode4(508210), // Rule ID 4261 //
        GIM_CheckConstantInt8, /*MI*/0, /*Op*/2, 0,
        GIM_CheckConstantInt8, /*MI*/0, /*Op*/3, 0,
        // MIs[0] offset
        GIM_CheckIsImm, /*MI*/0, /*Op*/5,
        // MIs[0] auxiliary
        GIM_CheckIsImm, /*MI*/0, /*Op*/6,
        // MIs[0] Operand 7
        GIM_CheckLiteralInt, /*MI*/0, /*Op*/7, GIMT_Encode8(0),
        GIM_CheckComplexPattern, /*MI*/0, /*Op*/4, /*Renderer*/GIMT_Encode2(0), GIMT_Encode2(GICP_gi_buf_soffset),
        // (SIbuffer_store_format v2i32:{ *:[v2i32] }:$vdata, v4i32:{ *:[v4i32] }:$rsrc, 0:{ *:[i32] }, 0:{ *:[i32] }, (BUFSOffset:{ *:[i32] } i32:{ *:[i32] }:$soffset), (timm:{ *:[i32] }):$offset, (timm:{ *:[i32] }):$auxiliary, 0:{ *:[i1] })  =>  (BUFFER_STORE_FORMAT_XY_VBUFFER_OFFSET_exact anonymous_15036:{ *:[v2i32] }:$vdata, SReg_128:{ *:[v4i32] }:$rsrc, SCSrc_b32:{ *:[i32] }:$soffset, (timm:{ *:[i32] }):$offset, (extract_cpol:{ *:[i32] } ?:{ *:[i32] }:$auxiliary), (extract_swz:{ *:[i1] } ?:{ *:[i32] }:$auxiliary))
        GIR_BuildMI, /*InsnID*/0, /*Opcode*/GIMT_Encode2(AMDGPU::BUFFER_STORE_FORMAT_XY_VBUFFER_OFFSET_exact),
        GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/0, // vdata
        GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/1, // rsrc
        GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/0, // soffset
        GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/5, // offset
        GIR_CustomOperandRenderer, /*InsnID*/0, /*OldInsnID*/0, /*OpIdx*/6, /*OperandRenderer*/GIMT_Encode2(GICR_renderExtractCPol), // auxiliary
        GIR_CustomOperandRenderer, /*InsnID*/0, /*OldInsnID*/0, /*OpIdx*/6, /*OperandRenderer*/GIMT_Encode2(GICR_renderExtractSWZ), // auxiliary
        GIR_MergeMemOperands, /*InsnID*/0, /*NumInsns*/1, /*MergeInsnID's*/0,
        GIR_ConstrainSelectedInstOperands, /*InsnID*/0,
        GIR_EraseFromParent, /*InsnID*/0,
        // GIR_Coverage, 4261,
        GIR_Done,
      // Label 6920: @508210
      GIM_Try, /*On fail goto*//*Label 6921*/ GIMT_Encode4(508292), // Rule ID 4250 //
        GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasUnrestrictedSOffset),
        GIM_CheckConstantInt8, /*MI*/0, /*Op*/2, 0,
        // MIs[0] offset
        GIM_CheckIsImm, /*MI*/0, /*Op*/5,
        // MIs[0] auxiliary
        GIM_CheckIsImm, /*MI*/0, /*Op*/6,
        // MIs[0] Operand 7
        GIM_CheckLiteralInt, /*MI*/0, /*Op*/7, GIMT_Encode8(0),
        GIM_CheckComplexPattern, /*MI*/0, /*Op*/4, /*Renderer*/GIMT_Encode2(0), GIMT_Encode2(GICP_gi_buf_soffset),
        // (SIbuffer_store_format v2f32:{ *:[v2f32] }:$vdata, v4i32:{ *:[v4i32] }:$rsrc, 0:{ *:[i32] }, i32:{ *:[i32] }:$voffset, (BUFSOffset:{ *:[i32] } i32:{ *:[i32] }:$soffset), (timm:{ *:[i32] }):$offset, (timm:{ *:[i32] }):$auxiliary, 0:{ *:[i1] })  =>  (BUFFER_STORE_FORMAT_XY_OFFEN_exact anonymous_15036:{ *:[v2f32] }:$vdata, VGPR_32:{ *:[i32] }:$voffset, SReg_128:{ *:[v4i32] }:$rsrc, SCSrc_b32:{ *:[i32] }:$soffset, (timm:{ *:[i32] }):$offset, (extract_cpol:{ *:[i32] } ?:{ *:[i32] }:$auxiliary), (extract_swz:{ *:[i1] } ?:{ *:[i32] }:$auxiliary))
        GIR_BuildMI, /*InsnID*/0, /*Opcode*/GIMT_Encode2(AMDGPU::BUFFER_STORE_FORMAT_XY_OFFEN_exact),
        GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/0, // vdata
        GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/3, // voffset
        GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/1, // rsrc
        GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/0, // soffset
        GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/5, // offset
        GIR_CustomOperandRenderer, /*InsnID*/0, /*OldInsnID*/0, /*OpIdx*/6, /*OperandRenderer*/GIMT_Encode2(GICR_renderExtractCPol), // auxiliary
        GIR_CustomOperandRenderer, /*InsnID*/0, /*OldInsnID*/0, /*OpIdx*/6, /*OperandRenderer*/GIMT_Encode2(GICR_renderExtractSWZ), // auxiliary
        GIR_MergeMemOperands, /*InsnID*/0, /*NumInsns*/1, /*MergeInsnID's*/0,
        GIR_ConstrainSelectedInstOperands, /*InsnID*/0,
        GIR_EraseFromParent, /*InsnID*/0,
        // GIR_Coverage, 4250,
        GIR_Done,
      // Label 6921: @508292
      GIM_Try, /*On fail goto*//*Label 6922*/ GIMT_Encode4(508371), // Rule ID 4254 //
        GIM_CheckConstantInt8, /*MI*/0, /*Op*/2, 0,
        // MIs[0] offset
        GIM_CheckIsImm, /*MI*/0, /*Op*/5,
        // MIs[0] auxiliary
        GIM_CheckIsImm, /*MI*/0, /*Op*/6,
        // MIs[0] Operand 7
        GIM_CheckLiteralInt, /*MI*/0, /*Op*/7, GIMT_Encode8(0),
        GIM_CheckComplexPattern, /*MI*/0, /*Op*/4, /*Renderer*/GIMT_Encode2(0), GIMT_Encode2(GICP_gi_buf_soffset),
        // (SIbuffer_store_format v2f32:{ *:[v2f32] }:$vdata, v4i32:{ *:[v4i32] }:$rsrc, 0:{ *:[i32] }, i32:{ *:[i32] }:$voffset, (BUFSOffset:{ *:[i32] } i32:{ *:[i32] }:$soffset), (timm:{ *:[i32] }):$offset, (timm:{ *:[i32] }):$auxiliary, 0:{ *:[i1] })  =>  (BUFFER_STORE_FORMAT_XY_VBUFFER_OFFEN_exact anonymous_15036:{ *:[v2f32] }:$vdata, VGPR_32:{ *:[i32] }:$voffset, SReg_128:{ *:[v4i32] }:$rsrc, SCSrc_b32:{ *:[i32] }:$soffset, (timm:{ *:[i32] }):$offset, (extract_cpol:{ *:[i32] } ?:{ *:[i32] }:$auxiliary), (extract_swz:{ *:[i1] } ?:{ *:[i32] }:$auxiliary))
        GIR_BuildMI, /*InsnID*/0, /*Opcode*/GIMT_Encode2(AMDGPU::BUFFER_STORE_FORMAT_XY_VBUFFER_OFFEN_exact),
        GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/0, // vdata
        GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/3, // voffset
        GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/1, // rsrc
        GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/0, // soffset
        GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/5, // offset
        GIR_CustomOperandRenderer, /*InsnID*/0, /*OldInsnID*/0, /*OpIdx*/6, /*OperandRenderer*/GIMT_Encode2(GICR_renderExtractCPol), // auxiliary
        GIR_CustomOperandRenderer, /*InsnID*/0, /*OldInsnID*/0, /*OpIdx*/6, /*OperandRenderer*/GIMT_Encode2(GICR_renderExtractSWZ), // auxiliary
        GIR_MergeMemOperands, /*InsnID*/0, /*NumInsns*/1, /*MergeInsnID's*/0,
        GIR_ConstrainSelectedInstOperands, /*InsnID*/0,
        GIR_EraseFromParent, /*InsnID*/0,
        // GIR_Coverage, 4254,
        GIR_Done,
      // Label 6922: @508371
      GIM_Try, /*On fail goto*//*Label 6923*/ GIMT_Encode4(508453), // Rule ID 4258 //
        GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasUnrestrictedSOffset),
        GIM_CheckConstantInt8, /*MI*/0, /*Op*/2, 0,
        // MIs[0] offset
        GIM_CheckIsImm, /*MI*/0, /*Op*/5,
        // MIs[0] auxiliary
        GIM_CheckIsImm, /*MI*/0, /*Op*/6,
        // MIs[0] Operand 7
        GIM_CheckLiteralInt, /*MI*/0, /*Op*/7, GIMT_Encode8(0),
        GIM_CheckComplexPattern, /*MI*/0, /*Op*/4, /*Renderer*/GIMT_Encode2(0), GIMT_Encode2(GICP_gi_buf_soffset),
        // (SIbuffer_store_format v2i32:{ *:[v2i32] }:$vdata, v4i32:{ *:[v4i32] }:$rsrc, 0:{ *:[i32] }, i32:{ *:[i32] }:$voffset, (BUFSOffset:{ *:[i32] } i32:{ *:[i32] }:$soffset), (timm:{ *:[i32] }):$offset, (timm:{ *:[i32] }):$auxiliary, 0:{ *:[i1] })  =>  (BUFFER_STORE_FORMAT_XY_OFFEN_exact anonymous_15036:{ *:[v2i32] }:$vdata, VGPR_32:{ *:[i32] }:$voffset, SReg_128:{ *:[v4i32] }:$rsrc, SCSrc_b32:{ *:[i32] }:$soffset, (timm:{ *:[i32] }):$offset, (extract_cpol:{ *:[i32] } ?:{ *:[i32] }:$auxiliary), (extract_swz:{ *:[i1] } ?:{ *:[i32] }:$auxiliary))
        GIR_BuildMI, /*InsnID*/0, /*Opcode*/GIMT_Encode2(AMDGPU::BUFFER_STORE_FORMAT_XY_OFFEN_exact),
        GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/0, // vdata
        GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/3, // voffset
        GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/1, // rsrc
        GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/0, // soffset
        GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/5, // offset
        GIR_CustomOperandRenderer, /*InsnID*/0, /*OldInsnID*/0, /*OpIdx*/6, /*OperandRenderer*/GIMT_Encode2(GICR_renderExtractCPol), // auxiliary
        GIR_CustomOperandRenderer, /*InsnID*/0, /*OldInsnID*/0, /*OpIdx*/6, /*OperandRenderer*/GIMT_Encode2(GICR_renderExtractSWZ), // auxiliary
        GIR_MergeMemOperands, /*InsnID*/0, /*NumInsns*/1, /*MergeInsnID's*/0,
        GIR_ConstrainSelectedInstOperands, /*InsnID*/0,
        GIR_EraseFromParent, /*InsnID*/0,
        // GIR_Coverage, 4258,
        GIR_Done,
      // Label 6923: @508453
      GIM_Try, /*On fail goto*//*Label 6924*/ GIMT_Encode4(508532), // Rule ID 4262 //
        GIM_CheckConstantInt8, /*MI*/0, /*Op*/2, 0,
        // MIs[0] offset
        GIM_CheckIsImm, /*MI*/0, /*Op*/5,
        // MIs[0] auxiliary
        GIM_CheckIsImm, /*MI*/0, /*Op*/6,
        // MIs[0] Operand 7
        GIM_CheckLiteralInt, /*MI*/0, /*Op*/7, GIMT_Encode8(0),
        GIM_CheckComplexPattern, /*MI*/0, /*Op*/4, /*Renderer*/GIMT_Encode2(0), GIMT_Encode2(GICP_gi_buf_soffset),
        // (SIbuffer_store_format v2i32:{ *:[v2i32] }:$vdata, v4i32:{ *:[v4i32] }:$rsrc, 0:{ *:[i32] }, i32:{ *:[i32] }:$voffset, (BUFSOffset:{ *:[i32] } i32:{ *:[i32] }:$soffset), (timm:{ *:[i32] }):$offset, (timm:{ *:[i32] }):$auxiliary, 0:{ *:[i1] })  =>  (BUFFER_STORE_FORMAT_XY_VBUFFER_OFFEN_exact anonymous_15036:{ *:[v2i32] }:$vdata, VGPR_32:{ *:[i32] }:$voffset, SReg_128:{ *:[v4i32] }:$rsrc, SCSrc_b32:{ *:[i32] }:$soffset, (timm:{ *:[i32] }):$offset, (extract_cpol:{ *:[i32] } ?:{ *:[i32] }:$auxiliary), (extract_swz:{ *:[i1] } ?:{ *:[i32] }:$auxiliary))
        GIR_BuildMI, /*InsnID*/0, /*Opcode*/GIMT_Encode2(AMDGPU::BUFFER_STORE_FORMAT_XY_VBUFFER_OFFEN_exact),
        GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/0, // vdata
        GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/3, // voffset
        GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/1, // rsrc
        GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/0, // soffset
        GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/5, // offset
        GIR_CustomOperandRenderer, /*InsnID*/0, /*OldInsnID*/0, /*OpIdx*/6, /*OperandRenderer*/GIMT_Encode2(GICR_renderExtractCPol), // auxiliary
        GIR_CustomOperandRenderer, /*InsnID*/0, /*OldInsnID*/0, /*OpIdx*/6, /*OperandRenderer*/GIMT_Encode2(GICR_renderExtractSWZ), // auxiliary
        GIR_MergeMemOperands, /*InsnID*/0, /*NumInsns*/1, /*MergeInsnID's*/0,
        GIR_ConstrainSelectedInstOperands, /*InsnID*/0,
        GIR_EraseFromParent, /*InsnID*/0,
        // GIR_Coverage, 4262,
        GIR_Done,
      // Label 6924: @508532
      GIM_Try, /*On fail goto*//*Label 6925*/ GIMT_Encode4(508606), // Rule ID 4251 //
        GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasUnrestrictedSOffset),
        GIM_CheckConstantInt8, /*MI*/0, /*Op*/3, 0,
        // MIs[0] offset
        GIM_CheckIsImm, /*MI*/0, /*Op*/5,
        // MIs[0] auxiliary
        GIM_CheckIsImm, /*MI*/0, /*Op*/6,
        // MIs[0] Operand 7
        GIM_CheckIsImm, /*MI*/0, /*Op*/7,
        GIM_CheckComplexPattern, /*MI*/0, /*Op*/4, /*Renderer*/GIMT_Encode2(0), GIMT_Encode2(GICP_gi_buf_soffset),
        // (SIbuffer_store_format v2f32:{ *:[v2f32] }:$vdata, v4i32:{ *:[v4i32] }:$rsrc, i32:{ *:[i32] }:$vindex, 0:{ *:[i32] }, (BUFSOffset:{ *:[i32] } i32:{ *:[i32] }:$soffset), (timm:{ *:[i32] }):$offset, (timm:{ *:[i32] }):$auxiliary, (timm:{ *:[i1] }))  =>  (BUFFER_STORE_FORMAT_XY_IDXEN_exact anonymous_15036:{ *:[v2f32] }:$vdata, VGPR_32:{ *:[i32] }:$vindex, SReg_128:{ *:[v4i32] }:$rsrc, SCSrc_b32:{ *:[i32] }:$soffset, (timm:{ *:[i32] }):$offset, (extract_cpol:{ *:[i32] } ?:{ *:[i32] }:$auxiliary), (extract_swz:{ *:[i1] } ?:{ *:[i32] }:$auxiliary))
        GIR_BuildMI, /*InsnID*/0, /*Opcode*/GIMT_Encode2(AMDGPU::BUFFER_STORE_FORMAT_XY_IDXEN_exact),
        GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/0, // vdata
        GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/2, // vindex
        GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/1, // rsrc
        GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/0, // soffset
        GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/5, // offset
        GIR_CustomOperandRenderer, /*InsnID*/0, /*OldInsnID*/0, /*OpIdx*/6, /*OperandRenderer*/GIMT_Encode2(GICR_renderExtractCPol), // auxiliary
        GIR_CustomOperandRenderer, /*InsnID*/0, /*OldInsnID*/0, /*OpIdx*/6, /*OperandRenderer*/GIMT_Encode2(GICR_renderExtractSWZ), // auxiliary
        GIR_MergeMemOperands, /*InsnID*/0, /*NumInsns*/1, /*MergeInsnID's*/0,
        GIR_ConstrainSelectedInstOperands, /*InsnID*/0,
        GIR_EraseFromParent, /*InsnID*/0,
        // GIR_Coverage, 4251,
        GIR_Done,
      // Label 6925: @508606
      GIM_Try, /*On fail goto*//*Label 6926*/ GIMT_Encode4(508677), // Rule ID 4255 //
        GIM_CheckConstantInt8, /*MI*/0, /*Op*/3, 0,
        // MIs[0] offset
        GIM_CheckIsImm, /*MI*/0, /*Op*/5,
        // MIs[0] auxiliary
        GIM_CheckIsImm, /*MI*/0, /*Op*/6,
        // MIs[0] Operand 7
        GIM_CheckIsImm, /*MI*/0, /*Op*/7,
        GIM_CheckComplexPattern, /*MI*/0, /*Op*/4, /*Renderer*/GIMT_Encode2(0), GIMT_Encode2(GICP_gi_buf_soffset),
        // (SIbuffer_store_format v2f32:{ *:[v2f32] }:$vdata, v4i32:{ *:[v4i32] }:$rsrc, i32:{ *:[i32] }:$vindex, 0:{ *:[i32] }, (BUFSOffset:{ *:[i32] } i32:{ *:[i32] }:$soffset), (timm:{ *:[i32] }):$offset, (timm:{ *:[i32] }):$auxiliary, (timm:{ *:[i1] }))  =>  (BUFFER_STORE_FORMAT_XY_VBUFFER_IDXEN_exact anonymous_15036:{ *:[v2f32] }:$vdata, VGPR_32:{ *:[i32] }:$vindex, SReg_128:{ *:[v4i32] }:$rsrc, SCSrc_b32:{ *:[i32] }:$soffset, (timm:{ *:[i32] }):$offset, (extract_cpol:{ *:[i32] } ?:{ *:[i32] }:$auxiliary), (extract_swz:{ *:[i1] } ?:{ *:[i32] }:$auxiliary))
        GIR_BuildMI, /*InsnID*/0, /*Opcode*/GIMT_Encode2(AMDGPU::BUFFER_STORE_FORMAT_XY_VBUFFER_IDXEN_exact),
        GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/0, // vdata
        GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/2, // vindex
        GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/1, // rsrc
        GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/0, // soffset
        GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/5, // offset
        GIR_CustomOperandRenderer, /*InsnID*/0, /*OldInsnID*/0, /*OpIdx*/6, /*OperandRenderer*/GIMT_Encode2(GICR_renderExtractCPol), // auxiliary
        GIR_CustomOperandRenderer, /*InsnID*/0, /*OldInsnID*/0, /*OpIdx*/6, /*OperandRenderer*/GIMT_Encode2(GICR_renderExtractSWZ), // auxiliary
        GIR_MergeMemOperands, /*InsnID*/0, /*NumInsns*/1, /*MergeInsnID's*/0,
        GIR_ConstrainSelectedInstOperands, /*InsnID*/0,
        GIR_EraseFromParent, /*InsnID*/0,
        // GIR_Coverage, 4255,
        GIR_Done,
      // Label 6926: @508677
      GIM_Try, /*On fail goto*//*Label 6927*/ GIMT_Encode4(508751), // Rule ID 4259 //
        GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasUnrestrictedSOffset),
        GIM_CheckConstantInt8, /*MI*/0, /*Op*/3, 0,
        // MIs[0] offset
        GIM_CheckIsImm, /*MI*/0, /*Op*/5,
        // MIs[0] auxiliary
        GIM_CheckIsImm, /*MI*/0, /*Op*/6,
        // MIs[0] Operand 7
        GIM_CheckIsImm, /*MI*/0, /*Op*/7,
        GIM_CheckComplexPattern, /*MI*/0, /*Op*/4, /*Renderer*/GIMT_Encode2(0), GIMT_Encode2(GICP_gi_buf_soffset),
        // (SIbuffer_store_format v2i32:{ *:[v2i32] }:$vdata, v4i32:{ *:[v4i32] }:$rsrc, i32:{ *:[i32] }:$vindex, 0:{ *:[i32] }, (BUFSOffset:{ *:[i32] } i32:{ *:[i32] }:$soffset), (timm:{ *:[i32] }):$offset, (timm:{ *:[i32] }):$auxiliary, (timm:{ *:[i1] }))  =>  (BUFFER_STORE_FORMAT_XY_IDXEN_exact anonymous_15036:{ *:[v2i32] }:$vdata, VGPR_32:{ *:[i32] }:$vindex, SReg_128:{ *:[v4i32] }:$rsrc, SCSrc_b32:{ *:[i32] }:$soffset, (timm:{ *:[i32] }):$offset, (extract_cpol:{ *:[i32] } ?:{ *:[i32] }:$auxiliary), (extract_swz:{ *:[i1] } ?:{ *:[i32] }:$auxiliary))
        GIR_BuildMI, /*InsnID*/0, /*Opcode*/GIMT_Encode2(AMDGPU::BUFFER_STORE_FORMAT_XY_IDXEN_exact),
        GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/0, // vdata
        GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/2, // vindex
        GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/1, // rsrc
        GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/0, // soffset
        GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/5, // offset
        GIR_CustomOperandRenderer, /*InsnID*/0, /*OldInsnID*/0, /*OpIdx*/6, /*OperandRenderer*/GIMT_Encode2(GICR_renderExtractCPol), // auxiliary
        GIR_CustomOperandRenderer, /*InsnID*/0, /*OldInsnID*/0, /*OpIdx*/6, /*OperandRenderer*/GIMT_Encode2(GICR_renderExtractSWZ), // auxiliary
        GIR_MergeMemOperands, /*InsnID*/0, /*NumInsns*/1, /*MergeInsnID's*/0,
        GIR_ConstrainSelectedInstOperands, /*InsnID*/0,
        GIR_EraseFromParent, /*InsnID*/0,
        // GIR_Coverage, 4259,
        GIR_Done,
      // Label 6927: @508751
      GIM_Try, /*On fail goto*//*Label 6928*/ GIMT_Encode4(508822), // Rule ID 4263 //
        GIM_CheckConstantInt8, /*MI*/0, /*Op*/3, 0,
        // MIs[0] offset
        GIM_CheckIsImm, /*MI*/0, /*Op*/5,
        // MIs[0] auxiliary
        GIM_CheckIsImm, /*MI*/0, /*Op*/6,
        // MIs[0] Operand 7
        GIM_CheckIsImm, /*MI*/0, /*Op*/7,
        GIM_CheckComplexPattern, /*MI*/0, /*Op*/4, /*Renderer*/GIMT_Encode2(0), GIMT_Encode2(GICP_gi_buf_soffset),
        // (SIbuffer_store_format v2i32:{ *:[v2i32] }:$vdata, v4i32:{ *:[v4i32] }:$rsrc, i32:{ *:[i32] }:$vindex, 0:{ *:[i32] }, (BUFSOffset:{ *:[i32] } i32:{ *:[i32] }:$soffset), (timm:{ *:[i32] }):$offset, (timm:{ *:[i32] }):$auxiliary, (timm:{ *:[i1] }))  =>  (BUFFER_STORE_FORMAT_XY_VBUFFER_IDXEN_exact anonymous_15036:{ *:[v2i32] }:$vdata, VGPR_32:{ *:[i32] }:$vindex, SReg_128:{ *:[v4i32] }:$rsrc, SCSrc_b32:{ *:[i32] }:$soffset, (timm:{ *:[i32] }):$offset, (extract_cpol:{ *:[i32] } ?:{ *:[i32] }:$auxiliary), (extract_swz:{ *:[i1] } ?:{ *:[i32] }:$auxiliary))
        GIR_BuildMI, /*InsnID*/0, /*Opcode*/GIMT_Encode2(AMDGPU::BUFFER_STORE_FORMAT_XY_VBUFFER_IDXEN_exact),
        GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/0, // vdata
        GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/2, // vindex
        GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/1, // rsrc
        GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/0, // soffset
        GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/5, // offset
        GIR_CustomOperandRenderer, /*InsnID*/0, /*OldInsnID*/0, /*OpIdx*/6, /*OperandRenderer*/GIMT_Encode2(GICR_renderExtractCPol), // auxiliary
        GIR_CustomOperandRenderer, /*InsnID*/0, /*OldInsnID*/0, /*OpIdx*/6, /*OperandRenderer*/GIMT_Encode2(GICR_renderExtractSWZ), // auxiliary
        GIR_MergeMemOperands, /*InsnID*/0, /*NumInsns*/1, /*MergeInsnID's*/0,
        GIR_ConstrainSelectedInstOperands, /*InsnID*/0,
        GIR_EraseFromParent, /*InsnID*/0,
        // GIR_Coverage, 4263,
        GIR_Done,
      // Label 6928: @508822
      GIM_Try, /*On fail goto*//*Label 6929*/ GIMT_Encode4(508932), // Rule ID 4252 //
        GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasUnrestrictedSOffset),
        // MIs[0] offset
        GIM_CheckIsImm, /*MI*/0, /*Op*/5,
        // MIs[0] auxiliary
        GIM_CheckIsImm, /*MI*/0, /*Op*/6,
        // MIs[0] Operand 7
        GIM_CheckIsImm, /*MI*/0, /*Op*/7,
        GIM_CheckComplexPattern, /*MI*/0, /*Op*/4, /*Renderer*/GIMT_Encode2(0), GIMT_Encode2(GICP_gi_buf_soffset),
        // (SIbuffer_store_format v2f32:{ *:[v2f32] }:$vdata, v4i32:{ *:[v4i32] }:$rsrc, i32:{ *:[i32] }:$vindex, i32:{ *:[i32] }:$voffset, (BUFSOffset:{ *:[i32] } i32:{ *:[i32] }:$soffset), (timm:{ *:[i32] }):$offset, (timm:{ *:[i32] }):$auxiliary, (timm:{ *:[i1] }))  =>  (BUFFER_STORE_FORMAT_XY_BOTHEN_exact anonymous_15036:{ *:[v2f32] }:$vdata, (REG_SEQUENCE:{ *:[i64] } VReg_64:{ *:[i32] }, VGPR_32:{ *:[i32] }:$vindex, sub0:{ *:[i32] }, VGPR_32:{ *:[i32] }:$voffset, sub1:{ *:[i32] }), SReg_128:{ *:[v4i32] }:$rsrc, SCSrc_b32:{ *:[i32] }:$soffset, (timm:{ *:[i32] }):$offset, (extract_cpol:{ *:[i32] } ?:{ *:[i32] }:$auxiliary), (extract_swz:{ *:[i1] } ?:{ *:[i32] }:$auxiliary))
        GIR_MakeTempReg, /*TempRegID*/0, /*TypeID*/GILLT_s64,
        GIR_BuildMI, /*InsnID*/1, /*Opcode*/GIMT_Encode2(TargetOpcode::REG_SEQUENCE),
        GIR_AddTempRegister, /*InsnID*/1, /*TempRegID*/0, /*TempRegFlags*/GIMT_Encode2(RegState::Define),
        GIR_Copy, /*NewInsnID*/1, /*OldInsnID*/0, /*OpIdx*/2, // vindex
        GIR_AddImm8, /*InsnID*/1, /*SubRegIndex*/3,
        GIR_Copy, /*NewInsnID*/1, /*OldInsnID*/0, /*OpIdx*/3, // voffset
        GIR_AddImm8, /*InsnID*/1, /*SubRegIndex*/11,
        GIR_ConstrainOperandRC, /*InsnID*/1, /*Op*/0, GIMT_Encode2(AMDGPU::VReg_64RegClassID),
        GIR_ConstrainOperandRC, /*InsnID*/1, /*Op*/1, GIMT_Encode2(AMDGPU::VGPR_32RegClassID),
        GIR_ConstrainOperandRC, /*InsnID*/1, /*Op*/3, GIMT_Encode2(AMDGPU::VGPR_32RegClassID),
        GIR_BuildMI, /*InsnID*/0, /*Opcode*/GIMT_Encode2(AMDGPU::BUFFER_STORE_FORMAT_XY_BOTHEN_exact),
        GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/0, // vdata
        GIR_AddSimpleTempRegister, /*InsnID*/0, /*TempRegID*/0,
        GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/1, // rsrc
        GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/0, // soffset
        GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/5, // offset
        GIR_CustomOperandRenderer, /*InsnID*/0, /*OldInsnID*/0, /*OpIdx*/6, /*OperandRenderer*/GIMT_Encode2(GICR_renderExtractCPol), // auxiliary
        GIR_CustomOperandRenderer, /*InsnID*/0, /*OldInsnID*/0, /*OpIdx*/6, /*OperandRenderer*/GIMT_Encode2(GICR_renderExtractSWZ), // auxiliary
        GIR_MergeMemOperands, /*InsnID*/0, /*NumInsns*/1, /*MergeInsnID's*/0,
        GIR_ConstrainSelectedInstOperands, /*InsnID*/0,
        GIR_EraseFromParent, /*InsnID*/0,
        // GIR_Coverage, 4252,
        GIR_Done,
      // Label 6929: @508932
      GIM_Try, /*On fail goto*//*Label 6930*/ GIMT_Encode4(509039), // Rule ID 4256 //
        // MIs[0] offset
        GIM_CheckIsImm, /*MI*/0, /*Op*/5,
        // MIs[0] auxiliary
        GIM_CheckIsImm, /*MI*/0, /*Op*/6,
        // MIs[0] Operand 7
        GIM_CheckIsImm, /*MI*/0, /*Op*/7,
        GIM_CheckComplexPattern, /*MI*/0, /*Op*/4, /*Renderer*/GIMT_Encode2(0), GIMT_Encode2(GICP_gi_buf_soffset),
        // (SIbuffer_store_format v2f32:{ *:[v2f32] }:$vdata, v4i32:{ *:[v4i32] }:$rsrc, i32:{ *:[i32] }:$vindex, i32:{ *:[i32] }:$voffset, (BUFSOffset:{ *:[i32] } i32:{ *:[i32] }:$soffset), (timm:{ *:[i32] }):$offset, (timm:{ *:[i32] }):$auxiliary, (timm:{ *:[i1] }))  =>  (BUFFER_STORE_FORMAT_XY_VBUFFER_BOTHEN_exact anonymous_15036:{ *:[v2f32] }:$vdata, (REG_SEQUENCE:{ *:[i64] } VReg_64:{ *:[i32] }, VGPR_32:{ *:[i32] }:$vindex, sub0:{ *:[i32] }, VGPR_32:{ *:[i32] }:$voffset, sub1:{ *:[i32] }), SReg_128:{ *:[v4i32] }:$rsrc, SCSrc_b32:{ *:[i32] }:$soffset, (timm:{ *:[i32] }):$offset, (extract_cpol:{ *:[i32] } ?:{ *:[i32] }:$auxiliary), (extract_swz:{ *:[i1] } ?:{ *:[i32] }:$auxiliary))
        GIR_MakeTempReg, /*TempRegID*/0, /*TypeID*/GILLT_s64,
        GIR_BuildMI, /*InsnID*/1, /*Opcode*/GIMT_Encode2(TargetOpcode::REG_SEQUENCE),
        GIR_AddTempRegister, /*InsnID*/1, /*TempRegID*/0, /*TempRegFlags*/GIMT_Encode2(RegState::Define),
        GIR_Copy, /*NewInsnID*/1, /*OldInsnID*/0, /*OpIdx*/2, // vindex
        GIR_AddImm8, /*InsnID*/1, /*SubRegIndex*/3,
        GIR_Copy, /*NewInsnID*/1, /*OldInsnID*/0, /*OpIdx*/3, // voffset
        GIR_AddImm8, /*InsnID*/1, /*SubRegIndex*/11,
        GIR_ConstrainOperandRC, /*InsnID*/1, /*Op*/0, GIMT_Encode2(AMDGPU::VReg_64RegClassID),
        GIR_ConstrainOperandRC, /*InsnID*/1, /*Op*/1, GIMT_Encode2(AMDGPU::VGPR_32RegClassID),
        GIR_ConstrainOperandRC, /*InsnID*/1, /*Op*/3, GIMT_Encode2(AMDGPU::VGPR_32RegClassID),
        GIR_BuildMI, /*InsnID*/0, /*Opcode*/GIMT_Encode2(AMDGPU::BUFFER_STORE_FORMAT_XY_VBUFFER_BOTHEN_exact),
        GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/0, // vdata
        GIR_AddSimpleTempRegister, /*InsnID*/0, /*TempRegID*/0,
        GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/1, // rsrc
        GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/0, // soffset
        GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/5, // offset
        GIR_CustomOperandRenderer, /*InsnID*/0, /*OldInsnID*/0, /*OpIdx*/6, /*OperandRenderer*/GIMT_Encode2(GICR_renderExtractCPol), // auxiliary
        GIR_CustomOperandRenderer, /*InsnID*/0, /*OldInsnID*/0, /*OpIdx*/6, /*OperandRenderer*/GIMT_Encode2(GICR_renderExtractSWZ), // auxiliary
        GIR_MergeMemOperands, /*InsnID*/0, /*NumInsns*/1, /*MergeInsnID's*/0,
        GIR_ConstrainSelectedInstOperands, /*InsnID*/0,
        GIR_EraseFromParent, /*InsnID*/0,
        // GIR_Coverage, 4256,
        GIR_Done,
      // Label 6930: @509039
      GIM_Try, /*On fail goto*//*Label 6931*/ GIMT_Encode4(509149), // Rule ID 4260 //
        GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasUnrestrictedSOffset),
        // MIs[0] offset
        GIM_CheckIsImm, /*MI*/0, /*Op*/5,
        // MIs[0] auxiliary
        GIM_CheckIsImm, /*MI*/0, /*Op*/6,
        // MIs[0] Operand 7
        GIM_CheckIsImm, /*MI*/0, /*Op*/7,
        GIM_CheckComplexPattern, /*MI*/0, /*Op*/4, /*Renderer*/GIMT_Encode2(0), GIMT_Encode2(GICP_gi_buf_soffset),
        // (SIbuffer_store_format v2i32:{ *:[v2i32] }:$vdata, v4i32:{ *:[v4i32] }:$rsrc, i32:{ *:[i32] }:$vindex, i32:{ *:[i32] }:$voffset, (BUFSOffset:{ *:[i32] } i32:{ *:[i32] }:$soffset), (timm:{ *:[i32] }):$offset, (timm:{ *:[i32] }):$auxiliary, (timm:{ *:[i1] }))  =>  (BUFFER_STORE_FORMAT_XY_BOTHEN_exact anonymous_15036:{ *:[v2i32] }:$vdata, (REG_SEQUENCE:{ *:[i64] } VReg_64:{ *:[i32] }, VGPR_32:{ *:[i32] }:$vindex, sub0:{ *:[i32] }, VGPR_32:{ *:[i32] }:$voffset, sub1:{ *:[i32] }), SReg_128:{ *:[v4i32] }:$rsrc, SCSrc_b32:{ *:[i32] }:$soffset, (timm:{ *:[i32] }):$offset, (extract_cpol:{ *:[i32] } ?:{ *:[i32] }:$auxiliary), (extract_swz:{ *:[i1] } ?:{ *:[i32] }:$auxiliary))
        GIR_MakeTempReg, /*TempRegID*/0, /*TypeID*/GILLT_s64,
        GIR_BuildMI, /*InsnID*/1, /*Opcode*/GIMT_Encode2(TargetOpcode::REG_SEQUENCE),
        GIR_AddTempRegister, /*InsnID*/1, /*TempRegID*/0, /*TempRegFlags*/GIMT_Encode2(RegState::Define),
        GIR_Copy, /*NewInsnID*/1, /*OldInsnID*/0, /*OpIdx*/2, // vindex
        GIR_AddImm8, /*InsnID*/1, /*SubRegIndex*/3,
        GIR_Copy, /*NewInsnID*/1, /*OldInsnID*/0, /*OpIdx*/3, // voffset
        GIR_AddImm8, /*InsnID*/1, /*SubRegIndex*/11,
        GIR_ConstrainOperandRC, /*InsnID*/1, /*Op*/0, GIMT_Encode2(AMDGPU::VReg_64RegClassID),
        GIR_ConstrainOperandRC, /*InsnID*/1, /*Op*/1, GIMT_Encode2(AMDGPU::VGPR_32RegClassID),
        GIR_ConstrainOperandRC, /*InsnID*/1, /*Op*/3, GIMT_Encode2(AMDGPU::VGPR_32RegClassID),
        GIR_BuildMI, /*InsnID*/0, /*Opcode*/GIMT_Encode2(AMDGPU::BUFFER_STORE_FORMAT_XY_BOTHEN_exact),
        GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/0, // vdata
        GIR_AddSimpleTempRegister, /*InsnID*/0, /*TempRegID*/0,
        GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/1, // rsrc
        GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/0, // soffset
        GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/5, // offset
        GIR_CustomOperandRenderer, /*InsnID*/0, /*OldInsnID*/0, /*OpIdx*/6, /*OperandRenderer*/GIMT_Encode2(GICR_renderExtractCPol), // auxiliary
        GIR_CustomOperandRenderer, /*InsnID*/0, /*OldInsnID*/0, /*OpIdx*/6, /*OperandRenderer*/GIMT_Encode2(GICR_renderExtractSWZ), // auxiliary
        GIR_MergeMemOperands, /*InsnID*/0, /*NumInsns*/1, /*MergeInsnID's*/0,
        GIR_ConstrainSelectedInstOperands, /*InsnID*/0,
        GIR_EraseFromParent, /*InsnID*/0,
        // GIR_Coverage, 4260,
        GIR_Done,
      // Label 6931: @509149
      GIM_Try, /*On fail goto*//*Label 6932*/ GIMT_Encode4(509256), // Rule ID 4264 //
        // MIs[0] offset
        GIM_CheckIsImm, /*MI*/0, /*Op*/5,
        // MIs[0] auxiliary
        GIM_CheckIsImm, /*MI*/0, /*Op*/6,
        // MIs[0] Operand 7
        GIM_CheckIsImm, /*MI*/0, /*Op*/7,
        GIM_CheckComplexPattern, /*MI*/0, /*Op*/4, /*Renderer*/GIMT_Encode2(0), GIMT_Encode2(GICP_gi_buf_soffset),
        // (SIbuffer_store_format v2i32:{ *:[v2i32] }:$vdata, v4i32:{ *:[v4i32] }:$rsrc, i32:{ *:[i32] }:$vindex, i32:{ *:[i32] }:$voffset, (BUFSOffset:{ *:[i32] } i32:{ *:[i32] }:$soffset), (timm:{ *:[i32] }):$offset, (timm:{ *:[i32] }):$auxiliary, (timm:{ *:[i1] }))  =>  (BUFFER_STORE_FORMAT_XY_VBUFFER_BOTHEN_exact anonymous_15036:{ *:[v2i32] }:$vdata, (REG_SEQUENCE:{ *:[i64] } VReg_64:{ *:[i32] }, VGPR_32:{ *:[i32] }:$vindex, sub0:{ *:[i32] }, VGPR_32:{ *:[i32] }:$voffset, sub1:{ *:[i32] }), SReg_128:{ *:[v4i32] }:$rsrc, SCSrc_b32:{ *:[i32] }:$soffset, (timm:{ *:[i32] }):$offset, (extract_cpol:{ *:[i32] } ?:{ *:[i32] }:$auxiliary), (extract_swz:{ *:[i1] } ?:{ *:[i32] }:$auxiliary))
        GIR_MakeTempReg, /*TempRegID*/0, /*TypeID*/GILLT_s64,
        GIR_BuildMI, /*InsnID*/1, /*Opcode*/GIMT_Encode2(TargetOpcode::REG_SEQUENCE),
        GIR_AddTempRegister, /*InsnID*/1, /*TempRegID*/0, /*TempRegFlags*/GIMT_Encode2(RegState::Define),
        GIR_Copy, /*NewInsnID*/1, /*OldInsnID*/0, /*OpIdx*/2, // vindex
        GIR_AddImm8, /*InsnID*/1, /*SubRegIndex*/3,
        GIR_Copy, /*NewInsnID*/1, /*OldInsnID*/0, /*OpIdx*/3, // voffset
        GIR_AddImm8, /*InsnID*/1, /*SubRegIndex*/11,
        GIR_ConstrainOperandRC, /*InsnID*/1, /*Op*/0, GIMT_Encode2(AMDGPU::VReg_64RegClassID),
        GIR_ConstrainOperandRC, /*InsnID*/1, /*Op*/1, GIMT_Encode2(AMDGPU::VGPR_32RegClassID),
        GIR_ConstrainOperandRC, /*InsnID*/1, /*Op*/3, GIMT_Encode2(AMDGPU::VGPR_32RegClassID),
        GIR_BuildMI, /*InsnID*/0, /*Opcode*/GIMT_Encode2(AMDGPU::BUFFER_STORE_FORMAT_XY_VBUFFER_BOTHEN_exact),
        GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/0, // vdata
        GIR_AddSimpleTempRegister, /*InsnID*/0, /*TempRegID*/0,
        GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/1, // rsrc
        GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/0, // soffset
        GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/5, // offset
        GIR_CustomOperandRenderer, /*InsnID*/0, /*OldInsnID*/0, /*OpIdx*/6, /*OperandRenderer*/GIMT_Encode2(GICR_renderExtractCPol), // auxiliary
        GIR_CustomOperandRenderer, /*InsnID*/0, /*OldInsnID*/0, /*OpIdx*/6, /*OperandRenderer*/GIMT_Encode2(GICR_renderExtractSWZ), // auxiliary
        GIR_MergeMemOperands, /*InsnID*/0, /*NumInsns*/1, /*MergeInsnID's*/0,
        GIR_ConstrainSelectedInstOperands, /*InsnID*/0,
        GIR_EraseFromParent, /*InsnID*/0,
        // GIR_Coverage, 4264,
        GIR_Done,
      // Label 6932: @509256
      GIM_Reject,
    // Label 6916: @509257
    GIM_Reject,
    // Label 6896: @509258
    GIM_Try, /*On fail goto*//*Label 6933*/ GIMT_Encode4(510648),
      GIM_CheckType, /*MI*/0, /*Op*/1, /*Type*/GILLT_v4s32,
      GIM_CheckType, /*MI*/0, /*Op*/2, /*Type*/GILLT_s32,
      GIM_CheckType, /*MI*/0, /*Op*/3, /*Type*/GILLT_s32,
      GIM_CheckType, /*MI*/0, /*Op*/4, /*Type*/GILLT_s32,
      GIM_Try, /*On fail goto*//*Label 6934*/ GIMT_Encode4(509361), // Rule ID 4265 //
        GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasUnrestrictedSOffset),
        GIM_CheckConstantInt8, /*MI*/0, /*Op*/2, 0,
        GIM_CheckConstantInt8, /*MI*/0, /*Op*/3, 0,
        // MIs[0] offset
        GIM_CheckIsImm, /*MI*/0, /*Op*/5,
        // MIs[0] auxiliary
        GIM_CheckIsImm, /*MI*/0, /*Op*/6,
        // MIs[0] Operand 7
        GIM_CheckLiteralInt, /*MI*/0, /*Op*/7, GIMT_Encode8(0),
        GIM_CheckComplexPattern, /*MI*/0, /*Op*/4, /*Renderer*/GIMT_Encode2(0), GIMT_Encode2(GICP_gi_buf_soffset),
        // (SIbuffer_store_format v3f32:{ *:[v3f32] }:$vdata, v4i32:{ *:[v4i32] }:$rsrc, 0:{ *:[i32] }, 0:{ *:[i32] }, (BUFSOffset:{ *:[i32] } i32:{ *:[i32] }:$soffset), (timm:{ *:[i32] }):$offset, (timm:{ *:[i32] }):$auxiliary, 0:{ *:[i1] })  =>  (BUFFER_STORE_FORMAT_XYZ_OFFSET_exact anonymous_15035:{ *:[v3f32] }:$vdata, SReg_128:{ *:[v4i32] }:$rsrc, SCSrc_b32:{ *:[i32] }:$soffset, (timm:{ *:[i32] }):$offset, (extract_cpol:{ *:[i32] } ?:{ *:[i32] }:$auxiliary), (extract_swz:{ *:[i1] } ?:{ *:[i32] }:$auxiliary))
        GIR_BuildMI, /*InsnID*/0, /*Opcode*/GIMT_Encode2(AMDGPU::BUFFER_STORE_FORMAT_XYZ_OFFSET_exact),
        GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/0, // vdata
        GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/1, // rsrc
        GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/0, // soffset
        GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/5, // offset
        GIR_CustomOperandRenderer, /*InsnID*/0, /*OldInsnID*/0, /*OpIdx*/6, /*OperandRenderer*/GIMT_Encode2(GICR_renderExtractCPol), // auxiliary
        GIR_CustomOperandRenderer, /*InsnID*/0, /*OldInsnID*/0, /*OpIdx*/6, /*OperandRenderer*/GIMT_Encode2(GICR_renderExtractSWZ), // auxiliary
        GIR_MergeMemOperands, /*InsnID*/0, /*NumInsns*/1, /*MergeInsnID's*/0,
        GIR_ConstrainSelectedInstOperands, /*InsnID*/0,
        GIR_EraseFromParent, /*InsnID*/0,
        // GIR_Coverage, 4265,
        GIR_Done,
      // Label 6934: @509361
      GIM_Try, /*On fail goto*//*Label 6935*/ GIMT_Encode4(509440), // Rule ID 4269 //
        GIM_CheckConstantInt8, /*MI*/0, /*Op*/2, 0,
        GIM_CheckConstantInt8, /*MI*/0, /*Op*/3, 0,
        // MIs[0] offset
        GIM_CheckIsImm, /*MI*/0, /*Op*/5,
        // MIs[0] auxiliary
        GIM_CheckIsImm, /*MI*/0, /*Op*/6,
        // MIs[0] Operand 7
        GIM_CheckLiteralInt, /*MI*/0, /*Op*/7, GIMT_Encode8(0),
        GIM_CheckComplexPattern, /*MI*/0, /*Op*/4, /*Renderer*/GIMT_Encode2(0), GIMT_Encode2(GICP_gi_buf_soffset),
        // (SIbuffer_store_format v3f32:{ *:[v3f32] }:$vdata, v4i32:{ *:[v4i32] }:$rsrc, 0:{ *:[i32] }, 0:{ *:[i32] }, (BUFSOffset:{ *:[i32] } i32:{ *:[i32] }:$soffset), (timm:{ *:[i32] }):$offset, (timm:{ *:[i32] }):$auxiliary, 0:{ *:[i1] })  =>  (BUFFER_STORE_FORMAT_XYZ_VBUFFER_OFFSET_exact anonymous_15035:{ *:[v3f32] }:$vdata, SReg_128:{ *:[v4i32] }:$rsrc, SCSrc_b32:{ *:[i32] }:$soffset, (timm:{ *:[i32] }):$offset, (extract_cpol:{ *:[i32] } ?:{ *:[i32] }:$auxiliary), (extract_swz:{ *:[i1] } ?:{ *:[i32] }:$auxiliary))
        GIR_BuildMI, /*InsnID*/0, /*Opcode*/GIMT_Encode2(AMDGPU::BUFFER_STORE_FORMAT_XYZ_VBUFFER_OFFSET_exact),
        GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/0, // vdata
        GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/1, // rsrc
        GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/0, // soffset
        GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/5, // offset
        GIR_CustomOperandRenderer, /*InsnID*/0, /*OldInsnID*/0, /*OpIdx*/6, /*OperandRenderer*/GIMT_Encode2(GICR_renderExtractCPol), // auxiliary
        GIR_CustomOperandRenderer, /*InsnID*/0, /*OldInsnID*/0, /*OpIdx*/6, /*OperandRenderer*/GIMT_Encode2(GICR_renderExtractSWZ), // auxiliary
        GIR_MergeMemOperands, /*InsnID*/0, /*NumInsns*/1, /*MergeInsnID's*/0,
        GIR_ConstrainSelectedInstOperands, /*InsnID*/0,
        GIR_EraseFromParent, /*InsnID*/0,
        // GIR_Coverage, 4269,
        GIR_Done,
      // Label 6935: @509440
      GIM_Try, /*On fail goto*//*Label 6936*/ GIMT_Encode4(509522), // Rule ID 4273 //
        GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasUnrestrictedSOffset),
        GIM_CheckConstantInt8, /*MI*/0, /*Op*/2, 0,
        GIM_CheckConstantInt8, /*MI*/0, /*Op*/3, 0,
        // MIs[0] offset
        GIM_CheckIsImm, /*MI*/0, /*Op*/5,
        // MIs[0] auxiliary
        GIM_CheckIsImm, /*MI*/0, /*Op*/6,
        // MIs[0] Operand 7
        GIM_CheckLiteralInt, /*MI*/0, /*Op*/7, GIMT_Encode8(0),
        GIM_CheckComplexPattern, /*MI*/0, /*Op*/4, /*Renderer*/GIMT_Encode2(0), GIMT_Encode2(GICP_gi_buf_soffset),
        // (SIbuffer_store_format v3i32:{ *:[v3i32] }:$vdata, v4i32:{ *:[v4i32] }:$rsrc, 0:{ *:[i32] }, 0:{ *:[i32] }, (BUFSOffset:{ *:[i32] } i32:{ *:[i32] }:$soffset), (timm:{ *:[i32] }):$offset, (timm:{ *:[i32] }):$auxiliary, 0:{ *:[i1] })  =>  (BUFFER_STORE_FORMAT_XYZ_OFFSET_exact anonymous_15035:{ *:[v3i32] }:$vdata, SReg_128:{ *:[v4i32] }:$rsrc, SCSrc_b32:{ *:[i32] }:$soffset, (timm:{ *:[i32] }):$offset, (extract_cpol:{ *:[i32] } ?:{ *:[i32] }:$auxiliary), (extract_swz:{ *:[i1] } ?:{ *:[i32] }:$auxiliary))
        GIR_BuildMI, /*InsnID*/0, /*Opcode*/GIMT_Encode2(AMDGPU::BUFFER_STORE_FORMAT_XYZ_OFFSET_exact),
        GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/0, // vdata
        GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/1, // rsrc
        GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/0, // soffset
        GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/5, // offset
        GIR_CustomOperandRenderer, /*InsnID*/0, /*OldInsnID*/0, /*OpIdx*/6, /*OperandRenderer*/GIMT_Encode2(GICR_renderExtractCPol), // auxiliary
        GIR_CustomOperandRenderer, /*InsnID*/0, /*OldInsnID*/0, /*OpIdx*/6, /*OperandRenderer*/GIMT_Encode2(GICR_renderExtractSWZ), // auxiliary
        GIR_MergeMemOperands, /*InsnID*/0, /*NumInsns*/1, /*MergeInsnID's*/0,
        GIR_ConstrainSelectedInstOperands, /*InsnID*/0,
        GIR_EraseFromParent, /*InsnID*/0,
        // GIR_Coverage, 4273,
        GIR_Done,
      // Label 6936: @509522
      GIM_Try, /*On fail goto*//*Label 6937*/ GIMT_Encode4(509601), // Rule ID 4277 //
        GIM_CheckConstantInt8, /*MI*/0, /*Op*/2, 0,
        GIM_CheckConstantInt8, /*MI*/0, /*Op*/3, 0,
        // MIs[0] offset
        GIM_CheckIsImm, /*MI*/0, /*Op*/5,
        // MIs[0] auxiliary
        GIM_CheckIsImm, /*MI*/0, /*Op*/6,
        // MIs[0] Operand 7
        GIM_CheckLiteralInt, /*MI*/0, /*Op*/7, GIMT_Encode8(0),
        GIM_CheckComplexPattern, /*MI*/0, /*Op*/4, /*Renderer*/GIMT_Encode2(0), GIMT_Encode2(GICP_gi_buf_soffset),
        // (SIbuffer_store_format v3i32:{ *:[v3i32] }:$vdata, v4i32:{ *:[v4i32] }:$rsrc, 0:{ *:[i32] }, 0:{ *:[i32] }, (BUFSOffset:{ *:[i32] } i32:{ *:[i32] }:$soffset), (timm:{ *:[i32] }):$offset, (timm:{ *:[i32] }):$auxiliary, 0:{ *:[i1] })  =>  (BUFFER_STORE_FORMAT_XYZ_VBUFFER_OFFSET_exact anonymous_15035:{ *:[v3i32] }:$vdata, SReg_128:{ *:[v4i32] }:$rsrc, SCSrc_b32:{ *:[i32] }:$soffset, (timm:{ *:[i32] }):$offset, (extract_cpol:{ *:[i32] } ?:{ *:[i32] }:$auxiliary), (extract_swz:{ *:[i1] } ?:{ *:[i32] }:$auxiliary))
        GIR_BuildMI, /*InsnID*/0, /*Opcode*/GIMT_Encode2(AMDGPU::BUFFER_STORE_FORMAT_XYZ_VBUFFER_OFFSET_exact),
        GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/0, // vdata
        GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/1, // rsrc
        GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/0, // soffset
        GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/5, // offset
        GIR_CustomOperandRenderer, /*InsnID*/0, /*OldInsnID*/0, /*OpIdx*/6, /*OperandRenderer*/GIMT_Encode2(GICR_renderExtractCPol), // auxiliary
        GIR_CustomOperandRenderer, /*InsnID*/0, /*OldInsnID*/0, /*OpIdx*/6, /*OperandRenderer*/GIMT_Encode2(GICR_renderExtractSWZ), // auxiliary
        GIR_MergeMemOperands, /*InsnID*/0, /*NumInsns*/1, /*MergeInsnID's*/0,
        GIR_ConstrainSelectedInstOperands, /*InsnID*/0,
        GIR_EraseFromParent, /*InsnID*/0,
        // GIR_Coverage, 4277,
        GIR_Done,
      // Label 6937: @509601
      GIM_Try, /*On fail goto*//*Label 6938*/ GIMT_Encode4(509683), // Rule ID 4266 //
        GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasUnrestrictedSOffset),
        GIM_CheckConstantInt8, /*MI*/0, /*Op*/2, 0,
        // MIs[0] offset
        GIM_CheckIsImm, /*MI*/0, /*Op*/5,
        // MIs[0] auxiliary
        GIM_CheckIsImm, /*MI*/0, /*Op*/6,
        // MIs[0] Operand 7
        GIM_CheckLiteralInt, /*MI*/0, /*Op*/7, GIMT_Encode8(0),
        GIM_CheckComplexPattern, /*MI*/0, /*Op*/4, /*Renderer*/GIMT_Encode2(0), GIMT_Encode2(GICP_gi_buf_soffset),
        // (SIbuffer_store_format v3f32:{ *:[v3f32] }:$vdata, v4i32:{ *:[v4i32] }:$rsrc, 0:{ *:[i32] }, i32:{ *:[i32] }:$voffset, (BUFSOffset:{ *:[i32] } i32:{ *:[i32] }:$soffset), (timm:{ *:[i32] }):$offset, (timm:{ *:[i32] }):$auxiliary, 0:{ *:[i1] })  =>  (BUFFER_STORE_FORMAT_XYZ_OFFEN_exact anonymous_15035:{ *:[v3f32] }:$vdata, VGPR_32:{ *:[i32] }:$voffset, SReg_128:{ *:[v4i32] }:$rsrc, SCSrc_b32:{ *:[i32] }:$soffset, (timm:{ *:[i32] }):$offset, (extract_cpol:{ *:[i32] } ?:{ *:[i32] }:$auxiliary), (extract_swz:{ *:[i1] } ?:{ *:[i32] }:$auxiliary))
        GIR_BuildMI, /*InsnID*/0, /*Opcode*/GIMT_Encode2(AMDGPU::BUFFER_STORE_FORMAT_XYZ_OFFEN_exact),
        GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/0, // vdata
        GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/3, // voffset
        GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/1, // rsrc
        GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/0, // soffset
        GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/5, // offset
        GIR_CustomOperandRenderer, /*InsnID*/0, /*OldInsnID*/0, /*OpIdx*/6, /*OperandRenderer*/GIMT_Encode2(GICR_renderExtractCPol), // auxiliary
        GIR_CustomOperandRenderer, /*InsnID*/0, /*OldInsnID*/0, /*OpIdx*/6, /*OperandRenderer*/GIMT_Encode2(GICR_renderExtractSWZ), // auxiliary
        GIR_MergeMemOperands, /*InsnID*/0, /*NumInsns*/1, /*MergeInsnID's*/0,
        GIR_ConstrainSelectedInstOperands, /*InsnID*/0,
        GIR_EraseFromParent, /*InsnID*/0,
        // GIR_Coverage, 4266,
        GIR_Done,
      // Label 6938: @509683
      GIM_Try, /*On fail goto*//*Label 6939*/ GIMT_Encode4(509762), // Rule ID 4270 //
        GIM_CheckConstantInt8, /*MI*/0, /*Op*/2, 0,
        // MIs[0] offset
        GIM_CheckIsImm, /*MI*/0, /*Op*/5,
        // MIs[0] auxiliary
        GIM_CheckIsImm, /*MI*/0, /*Op*/6,
        // MIs[0] Operand 7
        GIM_CheckLiteralInt, /*MI*/0, /*Op*/7, GIMT_Encode8(0),
        GIM_CheckComplexPattern, /*MI*/0, /*Op*/4, /*Renderer*/GIMT_Encode2(0), GIMT_Encode2(GICP_gi_buf_soffset),
        // (SIbuffer_store_format v3f32:{ *:[v3f32] }:$vdata, v4i32:{ *:[v4i32] }:$rsrc, 0:{ *:[i32] }, i32:{ *:[i32] }:$voffset, (BUFSOffset:{ *:[i32] } i32:{ *:[i32] }:$soffset), (timm:{ *:[i32] }):$offset, (timm:{ *:[i32] }):$auxiliary, 0:{ *:[i1] })  =>  (BUFFER_STORE_FORMAT_XYZ_VBUFFER_OFFEN_exact anonymous_15035:{ *:[v3f32] }:$vdata, VGPR_32:{ *:[i32] }:$voffset, SReg_128:{ *:[v4i32] }:$rsrc, SCSrc_b32:{ *:[i32] }:$soffset, (timm:{ *:[i32] }):$offset, (extract_cpol:{ *:[i32] } ?:{ *:[i32] }:$auxiliary), (extract_swz:{ *:[i1] } ?:{ *:[i32] }:$auxiliary))
        GIR_BuildMI, /*InsnID*/0, /*Opcode*/GIMT_Encode2(AMDGPU::BUFFER_STORE_FORMAT_XYZ_VBUFFER_OFFEN_exact),
        GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/0, // vdata
        GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/3, // voffset
        GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/1, // rsrc
        GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/0, // soffset
        GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/5, // offset
        GIR_CustomOperandRenderer, /*InsnID*/0, /*OldInsnID*/0, /*OpIdx*/6, /*OperandRenderer*/GIMT_Encode2(GICR_renderExtractCPol), // auxiliary
        GIR_CustomOperandRenderer, /*InsnID*/0, /*OldInsnID*/0, /*OpIdx*/6, /*OperandRenderer*/GIMT_Encode2(GICR_renderExtractSWZ), // auxiliary
        GIR_MergeMemOperands, /*InsnID*/0, /*NumInsns*/1, /*MergeInsnID's*/0,
        GIR_ConstrainSelectedInstOperands, /*InsnID*/0,
        GIR_EraseFromParent, /*InsnID*/0,
        // GIR_Coverage, 4270,
        GIR_Done,
      // Label 6939: @509762
      GIM_Try, /*On fail goto*//*Label 6940*/ GIMT_Encode4(509844), // Rule ID 4274 //
        GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasUnrestrictedSOffset),
        GIM_CheckConstantInt8, /*MI*/0, /*Op*/2, 0,
        // MIs[0] offset
        GIM_CheckIsImm, /*MI*/0, /*Op*/5,
        // MIs[0] auxiliary
        GIM_CheckIsImm, /*MI*/0, /*Op*/6,
        // MIs[0] Operand 7
        GIM_CheckLiteralInt, /*MI*/0, /*Op*/7, GIMT_Encode8(0),
        GIM_CheckComplexPattern, /*MI*/0, /*Op*/4, /*Renderer*/GIMT_Encode2(0), GIMT_Encode2(GICP_gi_buf_soffset),
        // (SIbuffer_store_format v3i32:{ *:[v3i32] }:$vdata, v4i32:{ *:[v4i32] }:$rsrc, 0:{ *:[i32] }, i32:{ *:[i32] }:$voffset, (BUFSOffset:{ *:[i32] } i32:{ *:[i32] }:$soffset), (timm:{ *:[i32] }):$offset, (timm:{ *:[i32] }):$auxiliary, 0:{ *:[i1] })  =>  (BUFFER_STORE_FORMAT_XYZ_OFFEN_exact anonymous_15035:{ *:[v3i32] }:$vdata, VGPR_32:{ *:[i32] }:$voffset, SReg_128:{ *:[v4i32] }:$rsrc, SCSrc_b32:{ *:[i32] }:$soffset, (timm:{ *:[i32] }):$offset, (extract_cpol:{ *:[i32] } ?:{ *:[i32] }:$auxiliary), (extract_swz:{ *:[i1] } ?:{ *:[i32] }:$auxiliary))
        GIR_BuildMI, /*InsnID*/0, /*Opcode*/GIMT_Encode2(AMDGPU::BUFFER_STORE_FORMAT_XYZ_OFFEN_exact),
        GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/0, // vdata
        GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/3, // voffset
        GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/1, // rsrc
        GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/0, // soffset
        GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/5, // offset
        GIR_CustomOperandRenderer, /*InsnID*/0, /*OldInsnID*/0, /*OpIdx*/6, /*OperandRenderer*/GIMT_Encode2(GICR_renderExtractCPol), // auxiliary
        GIR_CustomOperandRenderer, /*InsnID*/0, /*OldInsnID*/0, /*OpIdx*/6, /*OperandRenderer*/GIMT_Encode2(GICR_renderExtractSWZ), // auxiliary
        GIR_MergeMemOperands, /*InsnID*/0, /*NumInsns*/1, /*MergeInsnID's*/0,
        GIR_ConstrainSelectedInstOperands, /*InsnID*/0,
        GIR_EraseFromParent, /*InsnID*/0,
        // GIR_Coverage, 4274,
        GIR_Done,
      // Label 6940: @509844
      GIM_Try, /*On fail goto*//*Label 6941*/ GIMT_Encode4(509923), // Rule ID 4278 //
        GIM_CheckConstantInt8, /*MI*/0, /*Op*/2, 0,
        // MIs[0] offset
        GIM_CheckIsImm, /*MI*/0, /*Op*/5,
        // MIs[0] auxiliary
        GIM_CheckIsImm, /*MI*/0, /*Op*/6,
        // MIs[0] Operand 7
        GIM_CheckLiteralInt, /*MI*/0, /*Op*/7, GIMT_Encode8(0),
        GIM_CheckComplexPattern, /*MI*/0, /*Op*/4, /*Renderer*/GIMT_Encode2(0), GIMT_Encode2(GICP_gi_buf_soffset),
        // (SIbuffer_store_format v3i32:{ *:[v3i32] }:$vdata, v4i32:{ *:[v4i32] }:$rsrc, 0:{ *:[i32] }, i32:{ *:[i32] }:$voffset, (BUFSOffset:{ *:[i32] } i32:{ *:[i32] }:$soffset), (timm:{ *:[i32] }):$offset, (timm:{ *:[i32] }):$auxiliary, 0:{ *:[i1] })  =>  (BUFFER_STORE_FORMAT_XYZ_VBUFFER_OFFEN_exact anonymous_15035:{ *:[v3i32] }:$vdata, VGPR_32:{ *:[i32] }:$voffset, SReg_128:{ *:[v4i32] }:$rsrc, SCSrc_b32:{ *:[i32] }:$soffset, (timm:{ *:[i32] }):$offset, (extract_cpol:{ *:[i32] } ?:{ *:[i32] }:$auxiliary), (extract_swz:{ *:[i1] } ?:{ *:[i32] }:$auxiliary))
        GIR_BuildMI, /*InsnID*/0, /*Opcode*/GIMT_Encode2(AMDGPU::BUFFER_STORE_FORMAT_XYZ_VBUFFER_OFFEN_exact),
        GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/0, // vdata
        GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/3, // voffset
        GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/1, // rsrc
        GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/0, // soffset
        GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/5, // offset
        GIR_CustomOperandRenderer, /*InsnID*/0, /*OldInsnID*/0, /*OpIdx*/6, /*OperandRenderer*/GIMT_Encode2(GICR_renderExtractCPol), // auxiliary
        GIR_CustomOperandRenderer, /*InsnID*/0, /*OldInsnID*/0, /*OpIdx*/6, /*OperandRenderer*/GIMT_Encode2(GICR_renderExtractSWZ), // auxiliary
        GIR_MergeMemOperands, /*InsnID*/0, /*NumInsns*/1, /*MergeInsnID's*/0,
        GIR_ConstrainSelectedInstOperands, /*InsnID*/0,
        GIR_EraseFromParent, /*InsnID*/0,
        // GIR_Coverage, 4278,
        GIR_Done,
      // Label 6941: @509923
      GIM_Try, /*On fail goto*//*Label 6942*/ GIMT_Encode4(509997), // Rule ID 4267 //
        GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasUnrestrictedSOffset),
        GIM_CheckConstantInt8, /*MI*/0, /*Op*/3, 0,
        // MIs[0] offset
        GIM_CheckIsImm, /*MI*/0, /*Op*/5,
        // MIs[0] auxiliary
        GIM_CheckIsImm, /*MI*/0, /*Op*/6,
        // MIs[0] Operand 7
        GIM_CheckIsImm, /*MI*/0, /*Op*/7,
        GIM_CheckComplexPattern, /*MI*/0, /*Op*/4, /*Renderer*/GIMT_Encode2(0), GIMT_Encode2(GICP_gi_buf_soffset),
        // (SIbuffer_store_format v3f32:{ *:[v3f32] }:$vdata, v4i32:{ *:[v4i32] }:$rsrc, i32:{ *:[i32] }:$vindex, 0:{ *:[i32] }, (BUFSOffset:{ *:[i32] } i32:{ *:[i32] }:$soffset), (timm:{ *:[i32] }):$offset, (timm:{ *:[i32] }):$auxiliary, (timm:{ *:[i1] }))  =>  (BUFFER_STORE_FORMAT_XYZ_IDXEN_exact anonymous_15035:{ *:[v3f32] }:$vdata, VGPR_32:{ *:[i32] }:$vindex, SReg_128:{ *:[v4i32] }:$rsrc, SCSrc_b32:{ *:[i32] }:$soffset, (timm:{ *:[i32] }):$offset, (extract_cpol:{ *:[i32] } ?:{ *:[i32] }:$auxiliary), (extract_swz:{ *:[i1] } ?:{ *:[i32] }:$auxiliary))
        GIR_BuildMI, /*InsnID*/0, /*Opcode*/GIMT_Encode2(AMDGPU::BUFFER_STORE_FORMAT_XYZ_IDXEN_exact),
        GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/0, // vdata
        GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/2, // vindex
        GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/1, // rsrc
        GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/0, // soffset
        GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/5, // offset
        GIR_CustomOperandRenderer, /*InsnID*/0, /*OldInsnID*/0, /*OpIdx*/6, /*OperandRenderer*/GIMT_Encode2(GICR_renderExtractCPol), // auxiliary
        GIR_CustomOperandRenderer, /*InsnID*/0, /*OldInsnID*/0, /*OpIdx*/6, /*OperandRenderer*/GIMT_Encode2(GICR_renderExtractSWZ), // auxiliary
        GIR_MergeMemOperands, /*InsnID*/0, /*NumInsns*/1, /*MergeInsnID's*/0,
        GIR_ConstrainSelectedInstOperands, /*InsnID*/0,
        GIR_EraseFromParent, /*InsnID*/0,
        // GIR_Coverage, 4267,
        GIR_Done,
      // Label 6942: @509997
      GIM_Try, /*On fail goto*//*Label 6943*/ GIMT_Encode4(510068), // Rule ID 4271 //
        GIM_CheckConstantInt8, /*MI*/0, /*Op*/3, 0,
        // MIs[0] offset
        GIM_CheckIsImm, /*MI*/0, /*Op*/5,
        // MIs[0] auxiliary
        GIM_CheckIsImm, /*MI*/0, /*Op*/6,
        // MIs[0] Operand 7
        GIM_CheckIsImm, /*MI*/0, /*Op*/7,
        GIM_CheckComplexPattern, /*MI*/0, /*Op*/4, /*Renderer*/GIMT_Encode2(0), GIMT_Encode2(GICP_gi_buf_soffset),
        // (SIbuffer_store_format v3f32:{ *:[v3f32] }:$vdata, v4i32:{ *:[v4i32] }:$rsrc, i32:{ *:[i32] }:$vindex, 0:{ *:[i32] }, (BUFSOffset:{ *:[i32] } i32:{ *:[i32] }:$soffset), (timm:{ *:[i32] }):$offset, (timm:{ *:[i32] }):$auxiliary, (timm:{ *:[i1] }))  =>  (BUFFER_STORE_FORMAT_XYZ_VBUFFER_IDXEN_exact anonymous_15035:{ *:[v3f32] }:$vdata, VGPR_32:{ *:[i32] }:$vindex, SReg_128:{ *:[v4i32] }:$rsrc, SCSrc_b32:{ *:[i32] }:$soffset, (timm:{ *:[i32] }):$offset, (extract_cpol:{ *:[i32] } ?:{ *:[i32] }:$auxiliary), (extract_swz:{ *:[i1] } ?:{ *:[i32] }:$auxiliary))
        GIR_BuildMI, /*InsnID*/0, /*Opcode*/GIMT_Encode2(AMDGPU::BUFFER_STORE_FORMAT_XYZ_VBUFFER_IDXEN_exact),
        GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/0, // vdata
        GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/2, // vindex
        GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/1, // rsrc
        GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/0, // soffset
        GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/5, // offset
        GIR_CustomOperandRenderer, /*InsnID*/0, /*OldInsnID*/0, /*OpIdx*/6, /*OperandRenderer*/GIMT_Encode2(GICR_renderExtractCPol), // auxiliary
        GIR_CustomOperandRenderer, /*InsnID*/0, /*OldInsnID*/0, /*OpIdx*/6, /*OperandRenderer*/GIMT_Encode2(GICR_renderExtractSWZ), // auxiliary
        GIR_MergeMemOperands, /*InsnID*/0, /*NumInsns*/1, /*MergeInsnID's*/0,
        GIR_ConstrainSelectedInstOperands, /*InsnID*/0,
        GIR_EraseFromParent, /*InsnID*/0,
        // GIR_Coverage, 4271,
        GIR_Done,
      // Label 6943: @510068
      GIM_Try, /*On fail goto*//*Label 6944*/ GIMT_Encode4(510142), // Rule ID 4275 //
        GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasUnrestrictedSOffset),
        GIM_CheckConstantInt8, /*MI*/0, /*Op*/3, 0,
        // MIs[0] offset
        GIM_CheckIsImm, /*MI*/0, /*Op*/5,
        // MIs[0] auxiliary
        GIM_CheckIsImm, /*MI*/0, /*Op*/6,
        // MIs[0] Operand 7
        GIM_CheckIsImm, /*MI*/0, /*Op*/7,
        GIM_CheckComplexPattern, /*MI*/0, /*Op*/4, /*Renderer*/GIMT_Encode2(0), GIMT_Encode2(GICP_gi_buf_soffset),
        // (SIbuffer_store_format v3i32:{ *:[v3i32] }:$vdata, v4i32:{ *:[v4i32] }:$rsrc, i32:{ *:[i32] }:$vindex, 0:{ *:[i32] }, (BUFSOffset:{ *:[i32] } i32:{ *:[i32] }:$soffset), (timm:{ *:[i32] }):$offset, (timm:{ *:[i32] }):$auxiliary, (timm:{ *:[i1] }))  =>  (BUFFER_STORE_FORMAT_XYZ_IDXEN_exact anonymous_15035:{ *:[v3i32] }:$vdata, VGPR_32:{ *:[i32] }:$vindex, SReg_128:{ *:[v4i32] }:$rsrc, SCSrc_b32:{ *:[i32] }:$soffset, (timm:{ *:[i32] }):$offset, (extract_cpol:{ *:[i32] } ?:{ *:[i32] }:$auxiliary), (extract_swz:{ *:[i1] } ?:{ *:[i32] }:$auxiliary))
        GIR_BuildMI, /*InsnID*/0, /*Opcode*/GIMT_Encode2(AMDGPU::BUFFER_STORE_FORMAT_XYZ_IDXEN_exact),
        GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/0, // vdata
        GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/2, // vindex
        GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/1, // rsrc
        GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/0, // soffset
        GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/5, // offset
        GIR_CustomOperandRenderer, /*InsnID*/0, /*OldInsnID*/0, /*OpIdx*/6, /*OperandRenderer*/GIMT_Encode2(GICR_renderExtractCPol), // auxiliary
        GIR_CustomOperandRenderer, /*InsnID*/0, /*OldInsnID*/0, /*OpIdx*/6, /*OperandRenderer*/GIMT_Encode2(GICR_renderExtractSWZ), // auxiliary
        GIR_MergeMemOperands, /*InsnID*/0, /*NumInsns*/1, /*MergeInsnID's*/0,
        GIR_ConstrainSelectedInstOperands, /*InsnID*/0,
        GIR_EraseFromParent, /*InsnID*/0,
        // GIR_Coverage, 4275,
        GIR_Done,
      // Label 6944: @510142
      GIM_Try, /*On fail goto*//*Label 6945*/ GIMT_Encode4(510213), // Rule ID 4279 //
        GIM_CheckConstantInt8, /*MI*/0, /*Op*/3, 0,
        // MIs[0] offset
        GIM_CheckIsImm, /*MI*/0, /*Op*/5,
        // MIs[0] auxiliary
        GIM_CheckIsImm, /*MI*/0, /*Op*/6,
        // MIs[0] Operand 7
        GIM_CheckIsImm, /*MI*/0, /*Op*/7,
        GIM_CheckComplexPattern, /*MI*/0, /*Op*/4, /*Renderer*/GIMT_Encode2(0), GIMT_Encode2(GICP_gi_buf_soffset),
        // (SIbuffer_store_format v3i32:{ *:[v3i32] }:$vdata, v4i32:{ *:[v4i32] }:$rsrc, i32:{ *:[i32] }:$vindex, 0:{ *:[i32] }, (BUFSOffset:{ *:[i32] } i32:{ *:[i32] }:$soffset), (timm:{ *:[i32] }):$offset, (timm:{ *:[i32] }):$auxiliary, (timm:{ *:[i1] }))  =>  (BUFFER_STORE_FORMAT_XYZ_VBUFFER_IDXEN_exact anonymous_15035:{ *:[v3i32] }:$vdata, VGPR_32:{ *:[i32] }:$vindex, SReg_128:{ *:[v4i32] }:$rsrc, SCSrc_b32:{ *:[i32] }:$soffset, (timm:{ *:[i32] }):$offset, (extract_cpol:{ *:[i32] } ?:{ *:[i32] }:$auxiliary), (extract_swz:{ *:[i1] } ?:{ *:[i32] }:$auxiliary))
        GIR_BuildMI, /*InsnID*/0, /*Opcode*/GIMT_Encode2(AMDGPU::BUFFER_STORE_FORMAT_XYZ_VBUFFER_IDXEN_exact),
        GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/0, // vdata
        GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/2, // vindex
        GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/1, // rsrc
        GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/0, // soffset
        GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/5, // offset
        GIR_CustomOperandRenderer, /*InsnID*/0, /*OldInsnID*/0, /*OpIdx*/6, /*OperandRenderer*/GIMT_Encode2(GICR_renderExtractCPol), // auxiliary
        GIR_CustomOperandRenderer, /*InsnID*/0, /*OldInsnID*/0, /*OpIdx*/6, /*OperandRenderer*/GIMT_Encode2(GICR_renderExtractSWZ), // auxiliary
        GIR_MergeMemOperands, /*InsnID*/0, /*NumInsns*/1, /*MergeInsnID's*/0,
        GIR_ConstrainSelectedInstOperands, /*InsnID*/0,
        GIR_EraseFromParent, /*InsnID*/0,
        // GIR_Coverage, 4279,
        GIR_Done,
      // Label 6945: @510213
      GIM_Try, /*On fail goto*//*Label 6946*/ GIMT_Encode4(510323), // Rule ID 4268 //
        GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasUnrestrictedSOffset),
        // MIs[0] offset
        GIM_CheckIsImm, /*MI*/0, /*Op*/5,
        // MIs[0] auxiliary
        GIM_CheckIsImm, /*MI*/0, /*Op*/6,
        // MIs[0] Operand 7
        GIM_CheckIsImm, /*MI*/0, /*Op*/7,
        GIM_CheckComplexPattern, /*MI*/0, /*Op*/4, /*Renderer*/GIMT_Encode2(0), GIMT_Encode2(GICP_gi_buf_soffset),
        // (SIbuffer_store_format v3f32:{ *:[v3f32] }:$vdata, v4i32:{ *:[v4i32] }:$rsrc, i32:{ *:[i32] }:$vindex, i32:{ *:[i32] }:$voffset, (BUFSOffset:{ *:[i32] } i32:{ *:[i32] }:$soffset), (timm:{ *:[i32] }):$offset, (timm:{ *:[i32] }):$auxiliary, (timm:{ *:[i1] }))  =>  (BUFFER_STORE_FORMAT_XYZ_BOTHEN_exact anonymous_15035:{ *:[v3f32] }:$vdata, (REG_SEQUENCE:{ *:[i64] } VReg_64:{ *:[i32] }, VGPR_32:{ *:[i32] }:$vindex, sub0:{ *:[i32] }, VGPR_32:{ *:[i32] }:$voffset, sub1:{ *:[i32] }), SReg_128:{ *:[v4i32] }:$rsrc, SCSrc_b32:{ *:[i32] }:$soffset, (timm:{ *:[i32] }):$offset, (extract_cpol:{ *:[i32] } ?:{ *:[i32] }:$auxiliary), (extract_swz:{ *:[i1] } ?:{ *:[i32] }:$auxiliary))
        GIR_MakeTempReg, /*TempRegID*/0, /*TypeID*/GILLT_s64,
        GIR_BuildMI, /*InsnID*/1, /*Opcode*/GIMT_Encode2(TargetOpcode::REG_SEQUENCE),
        GIR_AddTempRegister, /*InsnID*/1, /*TempRegID*/0, /*TempRegFlags*/GIMT_Encode2(RegState::Define),
        GIR_Copy, /*NewInsnID*/1, /*OldInsnID*/0, /*OpIdx*/2, // vindex
        GIR_AddImm8, /*InsnID*/1, /*SubRegIndex*/3,
        GIR_Copy, /*NewInsnID*/1, /*OldInsnID*/0, /*OpIdx*/3, // voffset
        GIR_AddImm8, /*InsnID*/1, /*SubRegIndex*/11,
        GIR_ConstrainOperandRC, /*InsnID*/1, /*Op*/0, GIMT_Encode2(AMDGPU::VReg_64RegClassID),
        GIR_ConstrainOperandRC, /*InsnID*/1, /*Op*/1, GIMT_Encode2(AMDGPU::VGPR_32RegClassID),
        GIR_ConstrainOperandRC, /*InsnID*/1, /*Op*/3, GIMT_Encode2(AMDGPU::VGPR_32RegClassID),
        GIR_BuildMI, /*InsnID*/0, /*Opcode*/GIMT_Encode2(AMDGPU::BUFFER_STORE_FORMAT_XYZ_BOTHEN_exact),
        GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/0, // vdata
        GIR_AddSimpleTempRegister, /*InsnID*/0, /*TempRegID*/0,
        GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/1, // rsrc
        GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/0, // soffset
        GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/5, // offset
        GIR_CustomOperandRenderer, /*InsnID*/0, /*OldInsnID*/0, /*OpIdx*/6, /*OperandRenderer*/GIMT_Encode2(GICR_renderExtractCPol), // auxiliary
        GIR_CustomOperandRenderer, /*InsnID*/0, /*OldInsnID*/0, /*OpIdx*/6, /*OperandRenderer*/GIMT_Encode2(GICR_renderExtractSWZ), // auxiliary
        GIR_MergeMemOperands, /*InsnID*/0, /*NumInsns*/1, /*MergeInsnID's*/0,
        GIR_ConstrainSelectedInstOperands, /*InsnID*/0,
        GIR_EraseFromParent, /*InsnID*/0,
        // GIR_Coverage, 4268,
        GIR_Done,
      // Label 6946: @510323
      GIM_Try, /*On fail goto*//*Label 6947*/ GIMT_Encode4(510430), // Rule ID 4272 //
        // MIs[0] offset
        GIM_CheckIsImm, /*MI*/0, /*Op*/5,
        // MIs[0] auxiliary
        GIM_CheckIsImm, /*MI*/0, /*Op*/6,
        // MIs[0] Operand 7
        GIM_CheckIsImm, /*MI*/0, /*Op*/7,
        GIM_CheckComplexPattern, /*MI*/0, /*Op*/4, /*Renderer*/GIMT_Encode2(0), GIMT_Encode2(GICP_gi_buf_soffset),
        // (SIbuffer_store_format v3f32:{ *:[v3f32] }:$vdata, v4i32:{ *:[v4i32] }:$rsrc, i32:{ *:[i32] }:$vindex, i32:{ *:[i32] }:$voffset, (BUFSOffset:{ *:[i32] } i32:{ *:[i32] }:$soffset), (timm:{ *:[i32] }):$offset, (timm:{ *:[i32] }):$auxiliary, (timm:{ *:[i1] }))  =>  (BUFFER_STORE_FORMAT_XYZ_VBUFFER_BOTHEN_exact anonymous_15035:{ *:[v3f32] }:$vdata, (REG_SEQUENCE:{ *:[i64] } VReg_64:{ *:[i32] }, VGPR_32:{ *:[i32] }:$vindex, sub0:{ *:[i32] }, VGPR_32:{ *:[i32] }:$voffset, sub1:{ *:[i32] }), SReg_128:{ *:[v4i32] }:$rsrc, SCSrc_b32:{ *:[i32] }:$soffset, (timm:{ *:[i32] }):$offset, (extract_cpol:{ *:[i32] } ?:{ *:[i32] }:$auxiliary), (extract_swz:{ *:[i1] } ?:{ *:[i32] }:$auxiliary))
        GIR_MakeTempReg, /*TempRegID*/0, /*TypeID*/GILLT_s64,
        GIR_BuildMI, /*InsnID*/1, /*Opcode*/GIMT_Encode2(TargetOpcode::REG_SEQUENCE),
        GIR_AddTempRegister, /*InsnID*/1, /*TempRegID*/0, /*TempRegFlags*/GIMT_Encode2(RegState::Define),
        GIR_Copy, /*NewInsnID*/1, /*OldInsnID*/0, /*OpIdx*/2, // vindex
        GIR_AddImm8, /*InsnID*/1, /*SubRegIndex*/3,
        GIR_Copy, /*NewInsnID*/1, /*OldInsnID*/0, /*OpIdx*/3, // voffset
        GIR_AddImm8, /*InsnID*/1, /*SubRegIndex*/11,
        GIR_ConstrainOperandRC, /*InsnID*/1, /*Op*/0, GIMT_Encode2(AMDGPU::VReg_64RegClassID),
        GIR_ConstrainOperandRC, /*InsnID*/1, /*Op*/1, GIMT_Encode2(AMDGPU::VGPR_32RegClassID),
        GIR_ConstrainOperandRC, /*InsnID*/1, /*Op*/3, GIMT_Encode2(AMDGPU::VGPR_32RegClassID),
        GIR_BuildMI, /*InsnID*/0, /*Opcode*/GIMT_Encode2(AMDGPU::BUFFER_STORE_FORMAT_XYZ_VBUFFER_BOTHEN_exact),
        GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/0, // vdata
        GIR_AddSimpleTempRegister, /*InsnID*/0, /*TempRegID*/0,
        GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/1, // rsrc
        GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/0, // soffset
        GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/5, // offset
        GIR_CustomOperandRenderer, /*InsnID*/0, /*OldInsnID*/0, /*OpIdx*/6, /*OperandRenderer*/GIMT_Encode2(GICR_renderExtractCPol), // auxiliary
        GIR_CustomOperandRenderer, /*InsnID*/0, /*OldInsnID*/0, /*OpIdx*/6, /*OperandRenderer*/GIMT_Encode2(GICR_renderExtractSWZ), // auxiliary
        GIR_MergeMemOperands, /*InsnID*/0, /*NumInsns*/1, /*MergeInsnID's*/0,
        GIR_ConstrainSelectedInstOperands, /*InsnID*/0,
        GIR_EraseFromParent, /*InsnID*/0,
        // GIR_Coverage, 4272,
        GIR_Done,
      // Label 6947: @510430
      GIM_Try, /*On fail goto*//*Label 6948*/ GIMT_Encode4(510540), // Rule ID 4276 //
        GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasUnrestrictedSOffset),
        // MIs[0] offset
        GIM_CheckIsImm, /*MI*/0, /*Op*/5,
        // MIs[0] auxiliary
        GIM_CheckIsImm, /*MI*/0, /*Op*/6,
        // MIs[0] Operand 7
        GIM_CheckIsImm, /*MI*/0, /*Op*/7,
        GIM_CheckComplexPattern, /*MI*/0, /*Op*/4, /*Renderer*/GIMT_Encode2(0), GIMT_Encode2(GICP_gi_buf_soffset),
        // (SIbuffer_store_format v3i32:{ *:[v3i32] }:$vdata, v4i32:{ *:[v4i32] }:$rsrc, i32:{ *:[i32] }:$vindex, i32:{ *:[i32] }:$voffset, (BUFSOffset:{ *:[i32] } i32:{ *:[i32] }:$soffset), (timm:{ *:[i32] }):$offset, (timm:{ *:[i32] }):$auxiliary, (timm:{ *:[i1] }))  =>  (BUFFER_STORE_FORMAT_XYZ_BOTHEN_exact anonymous_15035:{ *:[v3i32] }:$vdata, (REG_SEQUENCE:{ *:[i64] } VReg_64:{ *:[i32] }, VGPR_32:{ *:[i32] }:$vindex, sub0:{ *:[i32] }, VGPR_32:{ *:[i32] }:$voffset, sub1:{ *:[i32] }), SReg_128:{ *:[v4i32] }:$rsrc, SCSrc_b32:{ *:[i32] }:$soffset, (timm:{ *:[i32] }):$offset, (extract_cpol:{ *:[i32] } ?:{ *:[i32] }:$auxiliary), (extract_swz:{ *:[i1] } ?:{ *:[i32] }:$auxiliary))
        GIR_MakeTempReg, /*TempRegID*/0, /*TypeID*/GILLT_s64,
        GIR_BuildMI, /*InsnID*/1, /*Opcode*/GIMT_Encode2(TargetOpcode::REG_SEQUENCE),
        GIR_AddTempRegister, /*InsnID*/1, /*TempRegID*/0, /*TempRegFlags*/GIMT_Encode2(RegState::Define),
        GIR_Copy, /*NewInsnID*/1, /*OldInsnID*/0, /*OpIdx*/2, // vindex
        GIR_AddImm8, /*InsnID*/1, /*SubRegIndex*/3,
        GIR_Copy, /*NewInsnID*/1, /*OldInsnID*/0, /*OpIdx*/3, // voffset
        GIR_AddImm8, /*InsnID*/1, /*SubRegIndex*/11,
        GIR_ConstrainOperandRC, /*InsnID*/1, /*Op*/0, GIMT_Encode2(AMDGPU::VReg_64RegClassID),
        GIR_ConstrainOperandRC, /*InsnID*/1, /*Op*/1, GIMT_Encode2(AMDGPU::VGPR_32RegClassID),
        GIR_ConstrainOperandRC, /*InsnID*/1, /*Op*/3, GIMT_Encode2(AMDGPU::VGPR_32RegClassID),
        GIR_BuildMI, /*InsnID*/0, /*Opcode*/GIMT_Encode2(AMDGPU::BUFFER_STORE_FORMAT_XYZ_BOTHEN_exact),
        GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/0, // vdata
        GIR_AddSimpleTempRegister, /*InsnID*/0, /*TempRegID*/0,
        GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/1, // rsrc
        GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/0, // soffset
        GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/5, // offset
        GIR_CustomOperandRenderer, /*InsnID*/0, /*OldInsnID*/0, /*OpIdx*/6, /*OperandRenderer*/GIMT_Encode2(GICR_renderExtractCPol), // auxiliary
        GIR_CustomOperandRenderer, /*InsnID*/0, /*OldInsnID*/0, /*OpIdx*/6, /*OperandRenderer*/GIMT_Encode2(GICR_renderExtractSWZ), // auxiliary
        GIR_MergeMemOperands, /*InsnID*/0, /*NumInsns*/1, /*MergeInsnID's*/0,
        GIR_ConstrainSelectedInstOperands, /*InsnID*/0,
        GIR_EraseFromParent, /*InsnID*/0,
        // GIR_Coverage, 4276,
        GIR_Done,
      // Label 6948: @510540
      GIM_Try, /*On fail goto*//*Label 6949*/ GIMT_Encode4(510647), // Rule ID 4280 //
        // MIs[0] offset
        GIM_CheckIsImm, /*MI*/0, /*Op*/5,
        // MIs[0] auxiliary
        GIM_CheckIsImm, /*MI*/0, /*Op*/6,
        // MIs[0] Operand 7
        GIM_CheckIsImm, /*MI*/0, /*Op*/7,
        GIM_CheckComplexPattern, /*MI*/0, /*Op*/4, /*Renderer*/GIMT_Encode2(0), GIMT_Encode2(GICP_gi_buf_soffset),
        // (SIbuffer_store_format v3i32:{ *:[v3i32] }:$vdata, v4i32:{ *:[v4i32] }:$rsrc, i32:{ *:[i32] }:$vindex, i32:{ *:[i32] }:$voffset, (BUFSOffset:{ *:[i32] } i32:{ *:[i32] }:$soffset), (timm:{ *:[i32] }):$offset, (timm:{ *:[i32] }):$auxiliary, (timm:{ *:[i1] }))  =>  (BUFFER_STORE_FORMAT_XYZ_VBUFFER_BOTHEN_exact anonymous_15035:{ *:[v3i32] }:$vdata, (REG_SEQUENCE:{ *:[i64] } VReg_64:{ *:[i32] }, VGPR_32:{ *:[i32] }:$vindex, sub0:{ *:[i32] }, VGPR_32:{ *:[i32] }:$voffset, sub1:{ *:[i32] }), SReg_128:{ *:[v4i32] }:$rsrc, SCSrc_b32:{ *:[i32] }:$soffset, (timm:{ *:[i32] }):$offset, (extract_cpol:{ *:[i32] } ?:{ *:[i32] }:$auxiliary), (extract_swz:{ *:[i1] } ?:{ *:[i32] }:$auxiliary))
        GIR_MakeTempReg, /*TempRegID*/0, /*TypeID*/GILLT_s64,
        GIR_BuildMI, /*InsnID*/1, /*Opcode*/GIMT_Encode2(TargetOpcode::REG_SEQUENCE),
        GIR_AddTempRegister, /*InsnID*/1, /*TempRegID*/0, /*TempRegFlags*/GIMT_Encode2(RegState::Define),
        GIR_Copy, /*NewInsnID*/1, /*OldInsnID*/0, /*OpIdx*/2, // vindex
        GIR_AddImm8, /*InsnID*/1, /*SubRegIndex*/3,
        GIR_Copy, /*NewInsnID*/1, /*OldInsnID*/0, /*OpIdx*/3, // voffset
        GIR_AddImm8, /*InsnID*/1, /*SubRegIndex*/11,
        GIR_ConstrainOperandRC, /*InsnID*/1, /*Op*/0, GIMT_Encode2(AMDGPU::VReg_64RegClassID),
        GIR_ConstrainOperandRC, /*InsnID*/1, /*Op*/1, GIMT_Encode2(AMDGPU::VGPR_32RegClassID),
        GIR_ConstrainOperandRC, /*InsnID*/1, /*Op*/3, GIMT_Encode2(AMDGPU::VGPR_32RegClassID),
        GIR_BuildMI, /*InsnID*/0, /*Opcode*/GIMT_Encode2(AMDGPU::BUFFER_STORE_FORMAT_XYZ_VBUFFER_BOTHEN_exact),
        GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/0, // vdata
        GIR_AddSimpleTempRegister, /*InsnID*/0, /*TempRegID*/0,
        GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/1, // rsrc
        GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/0, // soffset
        GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/5, // offset
        GIR_CustomOperandRenderer, /*InsnID*/0, /*OldInsnID*/0, /*OpIdx*/6, /*OperandRenderer*/GIMT_Encode2(GICR_renderExtractCPol), // auxiliary
        GIR_CustomOperandRenderer, /*InsnID*/0, /*OldInsnID*/0, /*OpIdx*/6, /*OperandRenderer*/GIMT_Encode2(GICR_renderExtractSWZ), // auxiliary
        GIR_MergeMemOperands, /*InsnID*/0, /*NumInsns*/1, /*MergeInsnID's*/0,
        GIR_ConstrainSelectedInstOperands, /*InsnID*/0,
        GIR_EraseFromParent, /*InsnID*/0,
        // GIR_Coverage, 4280,
        GIR_Done,
      // Label 6949: @510647
      GIM_Reject,
    // Label 6933: @510648
    GIM_Reject,
    // Label 6897: @510649
    GIM_Try, /*On fail goto*//*Label 6950*/ GIMT_Encode4(512039),
      GIM_CheckType, /*MI*/0, /*Op*/1, /*Type*/GILLT_v4s32,
      GIM_CheckType, /*MI*/0, /*Op*/2, /*Type*/GILLT_s32,
      GIM_CheckType, /*MI*/0, /*Op*/3, /*Type*/GILLT_s32,
      GIM_CheckType, /*MI*/0, /*Op*/4, /*Type*/GILLT_s32,
      GIM_Try, /*On fail goto*//*Label 6951*/ GIMT_Encode4(510752), // Rule ID 4281 //
        GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasUnrestrictedSOffset),
        GIM_CheckConstantInt8, /*MI*/0, /*Op*/2, 0,
        GIM_CheckConstantInt8, /*MI*/0, /*Op*/3, 0,
        // MIs[0] offset
        GIM_CheckIsImm, /*MI*/0, /*Op*/5,
        // MIs[0] auxiliary
        GIM_CheckIsImm, /*MI*/0, /*Op*/6,
        // MIs[0] Operand 7
        GIM_CheckLiteralInt, /*MI*/0, /*Op*/7, GIMT_Encode8(0),
        GIM_CheckComplexPattern, /*MI*/0, /*Op*/4, /*Renderer*/GIMT_Encode2(0), GIMT_Encode2(GICP_gi_buf_soffset),
        // (SIbuffer_store_format v4f32:{ *:[v4f32] }:$vdata, v4i32:{ *:[v4i32] }:$rsrc, 0:{ *:[i32] }, 0:{ *:[i32] }, (BUFSOffset:{ *:[i32] } i32:{ *:[i32] }:$soffset), (timm:{ *:[i32] }):$offset, (timm:{ *:[i32] }):$auxiliary, 0:{ *:[i1] })  =>  (BUFFER_STORE_FORMAT_XYZW_OFFSET_exact anonymous_15034:{ *:[v4f32] }:$vdata, SReg_128:{ *:[v4i32] }:$rsrc, SCSrc_b32:{ *:[i32] }:$soffset, (timm:{ *:[i32] }):$offset, (extract_cpol:{ *:[i32] } ?:{ *:[i32] }:$auxiliary), (extract_swz:{ *:[i1] } ?:{ *:[i32] }:$auxiliary))
        GIR_BuildMI, /*InsnID*/0, /*Opcode*/GIMT_Encode2(AMDGPU::BUFFER_STORE_FORMAT_XYZW_OFFSET_exact),
        GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/0, // vdata
        GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/1, // rsrc
        GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/0, // soffset
        GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/5, // offset
        GIR_CustomOperandRenderer, /*InsnID*/0, /*OldInsnID*/0, /*OpIdx*/6, /*OperandRenderer*/GIMT_Encode2(GICR_renderExtractCPol), // auxiliary
        GIR_CustomOperandRenderer, /*InsnID*/0, /*OldInsnID*/0, /*OpIdx*/6, /*OperandRenderer*/GIMT_Encode2(GICR_renderExtractSWZ), // auxiliary
        GIR_MergeMemOperands, /*InsnID*/0, /*NumInsns*/1, /*MergeInsnID's*/0,
        GIR_ConstrainSelectedInstOperands, /*InsnID*/0,
        GIR_EraseFromParent, /*InsnID*/0,
        // GIR_Coverage, 4281,
        GIR_Done,
      // Label 6951: @510752
      GIM_Try, /*On fail goto*//*Label 6952*/ GIMT_Encode4(510831), // Rule ID 4285 //
        GIM_CheckConstantInt8, /*MI*/0, /*Op*/2, 0,
        GIM_CheckConstantInt8, /*MI*/0, /*Op*/3, 0,
        // MIs[0] offset
        GIM_CheckIsImm, /*MI*/0, /*Op*/5,
        // MIs[0] auxiliary
        GIM_CheckIsImm, /*MI*/0, /*Op*/6,
        // MIs[0] Operand 7
        GIM_CheckLiteralInt, /*MI*/0, /*Op*/7, GIMT_Encode8(0),
        GIM_CheckComplexPattern, /*MI*/0, /*Op*/4, /*Renderer*/GIMT_Encode2(0), GIMT_Encode2(GICP_gi_buf_soffset),
        // (SIbuffer_store_format v4f32:{ *:[v4f32] }:$vdata, v4i32:{ *:[v4i32] }:$rsrc, 0:{ *:[i32] }, 0:{ *:[i32] }, (BUFSOffset:{ *:[i32] } i32:{ *:[i32] }:$soffset), (timm:{ *:[i32] }):$offset, (timm:{ *:[i32] }):$auxiliary, 0:{ *:[i1] })  =>  (BUFFER_STORE_FORMAT_XYZW_VBUFFER_OFFSET_exact anonymous_15034:{ *:[v4f32] }:$vdata, SReg_128:{ *:[v4i32] }:$rsrc, SCSrc_b32:{ *:[i32] }:$soffset, (timm:{ *:[i32] }):$offset, (extract_cpol:{ *:[i32] } ?:{ *:[i32] }:$auxiliary), (extract_swz:{ *:[i1] } ?:{ *:[i32] }:$auxiliary))
        GIR_BuildMI, /*InsnID*/0, /*Opcode*/GIMT_Encode2(AMDGPU::BUFFER_STORE_FORMAT_XYZW_VBUFFER_OFFSET_exact),
        GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/0, // vdata
        GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/1, // rsrc
        GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/0, // soffset
        GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/5, // offset
        GIR_CustomOperandRenderer, /*InsnID*/0, /*OldInsnID*/0, /*OpIdx*/6, /*OperandRenderer*/GIMT_Encode2(GICR_renderExtractCPol), // auxiliary
        GIR_CustomOperandRenderer, /*InsnID*/0, /*OldInsnID*/0, /*OpIdx*/6, /*OperandRenderer*/GIMT_Encode2(GICR_renderExtractSWZ), // auxiliary
        GIR_MergeMemOperands, /*InsnID*/0, /*NumInsns*/1, /*MergeInsnID's*/0,
        GIR_ConstrainSelectedInstOperands, /*InsnID*/0,
        GIR_EraseFromParent, /*InsnID*/0,
        // GIR_Coverage, 4285,
        GIR_Done,
      // Label 6952: @510831
      GIM_Try, /*On fail goto*//*Label 6953*/ GIMT_Encode4(510913), // Rule ID 4289 //
        GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasUnrestrictedSOffset),
        GIM_CheckConstantInt8, /*MI*/0, /*Op*/2, 0,
        GIM_CheckConstantInt8, /*MI*/0, /*Op*/3, 0,
        // MIs[0] offset
        GIM_CheckIsImm, /*MI*/0, /*Op*/5,
        // MIs[0] auxiliary
        GIM_CheckIsImm, /*MI*/0, /*Op*/6,
        // MIs[0] Operand 7
        GIM_CheckLiteralInt, /*MI*/0, /*Op*/7, GIMT_Encode8(0),
        GIM_CheckComplexPattern, /*MI*/0, /*Op*/4, /*Renderer*/GIMT_Encode2(0), GIMT_Encode2(GICP_gi_buf_soffset),
        // (SIbuffer_store_format v4i32:{ *:[v4i32] }:$vdata, v4i32:{ *:[v4i32] }:$rsrc, 0:{ *:[i32] }, 0:{ *:[i32] }, (BUFSOffset:{ *:[i32] } i32:{ *:[i32] }:$soffset), (timm:{ *:[i32] }):$offset, (timm:{ *:[i32] }):$auxiliary, 0:{ *:[i1] })  =>  (BUFFER_STORE_FORMAT_XYZW_OFFSET_exact anonymous_15034:{ *:[v4i32] }:$vdata, SReg_128:{ *:[v4i32] }:$rsrc, SCSrc_b32:{ *:[i32] }:$soffset, (timm:{ *:[i32] }):$offset, (extract_cpol:{ *:[i32] } ?:{ *:[i32] }:$auxiliary), (extract_swz:{ *:[i1] } ?:{ *:[i32] }:$auxiliary))
        GIR_BuildMI, /*InsnID*/0, /*Opcode*/GIMT_Encode2(AMDGPU::BUFFER_STORE_FORMAT_XYZW_OFFSET_exact),
        GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/0, // vdata
        GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/1, // rsrc
        GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/0, // soffset
        GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/5, // offset
        GIR_CustomOperandRenderer, /*InsnID*/0, /*OldInsnID*/0, /*OpIdx*/6, /*OperandRenderer*/GIMT_Encode2(GICR_renderExtractCPol), // auxiliary
        GIR_CustomOperandRenderer, /*InsnID*/0, /*OldInsnID*/0, /*OpIdx*/6, /*OperandRenderer*/GIMT_Encode2(GICR_renderExtractSWZ), // auxiliary
        GIR_MergeMemOperands, /*InsnID*/0, /*NumInsns*/1, /*MergeInsnID's*/0,
        GIR_ConstrainSelectedInstOperands, /*InsnID*/0,
        GIR_EraseFromParent, /*InsnID*/0,
        // GIR_Coverage, 4289,
        GIR_Done,
      // Label 6953: @510913
      GIM_Try, /*On fail goto*//*Label 6954*/ GIMT_Encode4(510992), // Rule ID 4293 //
        GIM_CheckConstantInt8, /*MI*/0, /*Op*/2, 0,
        GIM_CheckConstantInt8, /*MI*/0, /*Op*/3, 0,
        // MIs[0] offset
        GIM_CheckIsImm, /*MI*/0, /*Op*/5,
        // MIs[0] auxiliary
        GIM_CheckIsImm, /*MI*/0, /*Op*/6,
        // MIs[0] Operand 7
        GIM_CheckLiteralInt, /*MI*/0, /*Op*/7, GIMT_Encode8(0),
        GIM_CheckComplexPattern, /*MI*/0, /*Op*/4, /*Renderer*/GIMT_Encode2(0), GIMT_Encode2(GICP_gi_buf_soffset),
        // (SIbuffer_store_format v4i32:{ *:[v4i32] }:$vdata, v4i32:{ *:[v4i32] }:$rsrc, 0:{ *:[i32] }, 0:{ *:[i32] }, (BUFSOffset:{ *:[i32] } i32:{ *:[i32] }:$soffset), (timm:{ *:[i32] }):$offset, (timm:{ *:[i32] }):$auxiliary, 0:{ *:[i1] })  =>  (BUFFER_STORE_FORMAT_XYZW_VBUFFER_OFFSET_exact anonymous_15034:{ *:[v4i32] }:$vdata, SReg_128:{ *:[v4i32] }:$rsrc, SCSrc_b32:{ *:[i32] }:$soffset, (timm:{ *:[i32] }):$offset, (extract_cpol:{ *:[i32] } ?:{ *:[i32] }:$auxiliary), (extract_swz:{ *:[i1] } ?:{ *:[i32] }:$auxiliary))
        GIR_BuildMI, /*InsnID*/0, /*Opcode*/GIMT_Encode2(AMDGPU::BUFFER_STORE_FORMAT_XYZW_VBUFFER_OFFSET_exact),
        GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/0, // vdata
        GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/1, // rsrc
        GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/0, // soffset
        GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/5, // offset
        GIR_CustomOperandRenderer, /*InsnID*/0, /*OldInsnID*/0, /*OpIdx*/6, /*OperandRenderer*/GIMT_Encode2(GICR_renderExtractCPol), // auxiliary
        GIR_CustomOperandRenderer, /*InsnID*/0, /*OldInsnID*/0, /*OpIdx*/6, /*OperandRenderer*/GIMT_Encode2(GICR_renderExtractSWZ), // auxiliary
        GIR_MergeMemOperands, /*InsnID*/0, /*NumInsns*/1, /*MergeInsnID's*/0,
        GIR_ConstrainSelectedInstOperands, /*InsnID*/0,
        GIR_EraseFromParent, /*InsnID*/0,
        // GIR_Coverage, 4293,
        GIR_Done,
      // Label 6954: @510992
      GIM_Try, /*On fail goto*//*Label 6955*/ GIMT_Encode4(511074), // Rule ID 4282 //
        GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasUnrestrictedSOffset),
        GIM_CheckConstantInt8, /*MI*/0, /*Op*/2, 0,
        // MIs[0] offset
        GIM_CheckIsImm, /*MI*/0, /*Op*/5,
        // MIs[0] auxiliary
        GIM_CheckIsImm, /*MI*/0, /*Op*/6,
        // MIs[0] Operand 7
        GIM_CheckLiteralInt, /*MI*/0, /*Op*/7, GIMT_Encode8(0),
        GIM_CheckComplexPattern, /*MI*/0, /*Op*/4, /*Renderer*/GIMT_Encode2(0), GIMT_Encode2(GICP_gi_buf_soffset),
        // (SIbuffer_store_format v4f32:{ *:[v4f32] }:$vdata, v4i32:{ *:[v4i32] }:$rsrc, 0:{ *:[i32] }, i32:{ *:[i32] }:$voffset, (BUFSOffset:{ *:[i32] } i32:{ *:[i32] }:$soffset), (timm:{ *:[i32] }):$offset, (timm:{ *:[i32] }):$auxiliary, 0:{ *:[i1] })  =>  (BUFFER_STORE_FORMAT_XYZW_OFFEN_exact anonymous_15034:{ *:[v4f32] }:$vdata, VGPR_32:{ *:[i32] }:$voffset, SReg_128:{ *:[v4i32] }:$rsrc, SCSrc_b32:{ *:[i32] }:$soffset, (timm:{ *:[i32] }):$offset, (extract_cpol:{ *:[i32] } ?:{ *:[i32] }:$auxiliary), (extract_swz:{ *:[i1] } ?:{ *:[i32] }:$auxiliary))
        GIR_BuildMI, /*InsnID*/0, /*Opcode*/GIMT_Encode2(AMDGPU::BUFFER_STORE_FORMAT_XYZW_OFFEN_exact),
        GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/0, // vdata
        GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/3, // voffset
        GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/1, // rsrc
        GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/0, // soffset
        GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/5, // offset
        GIR_CustomOperandRenderer, /*InsnID*/0, /*OldInsnID*/0, /*OpIdx*/6, /*OperandRenderer*/GIMT_Encode2(GICR_renderExtractCPol), // auxiliary
        GIR_CustomOperandRenderer, /*InsnID*/0, /*OldInsnID*/0, /*OpIdx*/6, /*OperandRenderer*/GIMT_Encode2(GICR_renderExtractSWZ), // auxiliary
        GIR_MergeMemOperands, /*InsnID*/0, /*NumInsns*/1, /*MergeInsnID's*/0,
        GIR_ConstrainSelectedInstOperands, /*InsnID*/0,
        GIR_EraseFromParent, /*InsnID*/0,
        // GIR_Coverage, 4282,
        GIR_Done,
      // Label 6955: @511074
      GIM_Try, /*On fail goto*//*Label 6956*/ GIMT_Encode4(511153), // Rule ID 4286 //
        GIM_CheckConstantInt8, /*MI*/0, /*Op*/2, 0,
        // MIs[0] offset
        GIM_CheckIsImm, /*MI*/0, /*Op*/5,
        // MIs[0] auxiliary
        GIM_CheckIsImm, /*MI*/0, /*Op*/6,
        // MIs[0] Operand 7
        GIM_CheckLiteralInt, /*MI*/0, /*Op*/7, GIMT_Encode8(0),
        GIM_CheckComplexPattern, /*MI*/0, /*Op*/4, /*Renderer*/GIMT_Encode2(0), GIMT_Encode2(GICP_gi_buf_soffset),
        // (SIbuffer_store_format v4f32:{ *:[v4f32] }:$vdata, v4i32:{ *:[v4i32] }:$rsrc, 0:{ *:[i32] }, i32:{ *:[i32] }:$voffset, (BUFSOffset:{ *:[i32] } i32:{ *:[i32] }:$soffset), (timm:{ *:[i32] }):$offset, (timm:{ *:[i32] }):$auxiliary, 0:{ *:[i1] })  =>  (BUFFER_STORE_FORMAT_XYZW_VBUFFER_OFFEN_exact anonymous_15034:{ *:[v4f32] }:$vdata, VGPR_32:{ *:[i32] }:$voffset, SReg_128:{ *:[v4i32] }:$rsrc, SCSrc_b32:{ *:[i32] }:$soffset, (timm:{ *:[i32] }):$offset, (extract_cpol:{ *:[i32] } ?:{ *:[i32] }:$auxiliary), (extract_swz:{ *:[i1] } ?:{ *:[i32] }:$auxiliary))
        GIR_BuildMI, /*InsnID*/0, /*Opcode*/GIMT_Encode2(AMDGPU::BUFFER_STORE_FORMAT_XYZW_VBUFFER_OFFEN_exact),
        GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/0, // vdata
        GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/3, // voffset
        GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/1, // rsrc
        GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/0, // soffset
        GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/5, // offset
        GIR_CustomOperandRenderer, /*InsnID*/0, /*OldInsnID*/0, /*OpIdx*/6, /*OperandRenderer*/GIMT_Encode2(GICR_renderExtractCPol), // auxiliary
        GIR_CustomOperandRenderer, /*InsnID*/0, /*OldInsnID*/0, /*OpIdx*/6, /*OperandRenderer*/GIMT_Encode2(GICR_renderExtractSWZ), // auxiliary
        GIR_MergeMemOperands, /*InsnID*/0, /*NumInsns*/1, /*MergeInsnID's*/0,
        GIR_ConstrainSelectedInstOperands, /*InsnID*/0,
        GIR_EraseFromParent, /*InsnID*/0,
        // GIR_Coverage, 4286,
        GIR_Done,
      // Label 6956: @511153
      GIM_Try, /*On fail goto*//*Label 6957*/ GIMT_Encode4(511235), // Rule ID 4290 //
        GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasUnrestrictedSOffset),
        GIM_CheckConstantInt8, /*MI*/0, /*Op*/2, 0,
        // MIs[0] offset
        GIM_CheckIsImm, /*MI*/0, /*Op*/5,
        // MIs[0] auxiliary
        GIM_CheckIsImm, /*MI*/0, /*Op*/6,
        // MIs[0] Operand 7
        GIM_CheckLiteralInt, /*MI*/0, /*Op*/7, GIMT_Encode8(0),
        GIM_CheckComplexPattern, /*MI*/0, /*Op*/4, /*Renderer*/GIMT_Encode2(0), GIMT_Encode2(GICP_gi_buf_soffset),
        // (SIbuffer_store_format v4i32:{ *:[v4i32] }:$vdata, v4i32:{ *:[v4i32] }:$rsrc, 0:{ *:[i32] }, i32:{ *:[i32] }:$voffset, (BUFSOffset:{ *:[i32] } i32:{ *:[i32] }:$soffset), (timm:{ *:[i32] }):$offset, (timm:{ *:[i32] }):$auxiliary, 0:{ *:[i1] })  =>  (BUFFER_STORE_FORMAT_XYZW_OFFEN_exact anonymous_15034:{ *:[v4i32] }:$vdata, VGPR_32:{ *:[i32] }:$voffset, SReg_128:{ *:[v4i32] }:$rsrc, SCSrc_b32:{ *:[i32] }:$soffset, (timm:{ *:[i32] }):$offset, (extract_cpol:{ *:[i32] } ?:{ *:[i32] }:$auxiliary), (extract_swz:{ *:[i1] } ?:{ *:[i32] }:$auxiliary))
        GIR_BuildMI, /*InsnID*/0, /*Opcode*/GIMT_Encode2(AMDGPU::BUFFER_STORE_FORMAT_XYZW_OFFEN_exact),
        GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/0, // vdata
        GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/3, // voffset
        GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/1, // rsrc
        GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/0, // soffset
        GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/5, // offset
        GIR_CustomOperandRenderer, /*InsnID*/0, /*OldInsnID*/0, /*OpIdx*/6, /*OperandRenderer*/GIMT_Encode2(GICR_renderExtractCPol), // auxiliary
        GIR_CustomOperandRenderer, /*InsnID*/0, /*OldInsnID*/0, /*OpIdx*/6, /*OperandRenderer*/GIMT_Encode2(GICR_renderExtractSWZ), // auxiliary
        GIR_MergeMemOperands, /*InsnID*/0, /*NumInsns*/1, /*MergeInsnID's*/0,
        GIR_ConstrainSelectedInstOperands, /*InsnID*/0,
        GIR_EraseFromParent, /*InsnID*/0,
        // GIR_Coverage, 4290,
        GIR_Done,
      // Label 6957: @511235
      GIM_Try, /*On fail goto*//*Label 6958*/ GIMT_Encode4(511314), // Rule ID 4294 //
        GIM_CheckConstantInt8, /*MI*/0, /*Op*/2, 0,
        // MIs[0] offset
        GIM_CheckIsImm, /*MI*/0, /*Op*/5,
        // MIs[0] auxiliary
        GIM_CheckIsImm, /*MI*/0, /*Op*/6,
        // MIs[0] Operand 7
        GIM_CheckLiteralInt, /*MI*/0, /*Op*/7, GIMT_Encode8(0),
        GIM_CheckComplexPattern, /*MI*/0, /*Op*/4, /*Renderer*/GIMT_Encode2(0), GIMT_Encode2(GICP_gi_buf_soffset),
        // (SIbuffer_store_format v4i32:{ *:[v4i32] }:$vdata, v4i32:{ *:[v4i32] }:$rsrc, 0:{ *:[i32] }, i32:{ *:[i32] }:$voffset, (BUFSOffset:{ *:[i32] } i32:{ *:[i32] }:$soffset), (timm:{ *:[i32] }):$offset, (timm:{ *:[i32] }):$auxiliary, 0:{ *:[i1] })  =>  (BUFFER_STORE_FORMAT_XYZW_VBUFFER_OFFEN_exact anonymous_15034:{ *:[v4i32] }:$vdata, VGPR_32:{ *:[i32] }:$voffset, SReg_128:{ *:[v4i32] }:$rsrc, SCSrc_b32:{ *:[i32] }:$soffset, (timm:{ *:[i32] }):$offset, (extract_cpol:{ *:[i32] } ?:{ *:[i32] }:$auxiliary), (extract_swz:{ *:[i1] } ?:{ *:[i32] }:$auxiliary))
        GIR_BuildMI, /*InsnID*/0, /*Opcode*/GIMT_Encode2(AMDGPU::BUFFER_STORE_FORMAT_XYZW_VBUFFER_OFFEN_exact),
        GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/0, // vdata
        GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/3, // voffset
        GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/1, // rsrc
        GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/0, // soffset
        GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/5, // offset
        GIR_CustomOperandRenderer, /*InsnID*/0, /*OldInsnID*/0, /*OpIdx*/6, /*OperandRenderer*/GIMT_Encode2(GICR_renderExtractCPol), // auxiliary
        GIR_CustomOperandRenderer, /*InsnID*/0, /*OldInsnID*/0, /*OpIdx*/6, /*OperandRenderer*/GIMT_Encode2(GICR_renderExtractSWZ), // auxiliary
        GIR_MergeMemOperands, /*InsnID*/0, /*NumInsns*/1, /*MergeInsnID's*/0,
        GIR_ConstrainSelectedInstOperands, /*InsnID*/0,
        GIR_EraseFromParent, /*InsnID*/0,
        // GIR_Coverage, 4294,
        GIR_Done,
      // Label 6958: @511314
      GIM_Try, /*On fail goto*//*Label 6959*/ GIMT_Encode4(511388), // Rule ID 4283 //
        GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasUnrestrictedSOffset),
        GIM_CheckConstantInt8, /*MI*/0, /*Op*/3, 0,
        // MIs[0] offset
        GIM_CheckIsImm, /*MI*/0, /*Op*/5,
        // MIs[0] auxiliary
        GIM_CheckIsImm, /*MI*/0, /*Op*/6,
        // MIs[0] Operand 7
        GIM_CheckIsImm, /*MI*/0, /*Op*/7,
        GIM_CheckComplexPattern, /*MI*/0, /*Op*/4, /*Renderer*/GIMT_Encode2(0), GIMT_Encode2(GICP_gi_buf_soffset),
        // (SIbuffer_store_format v4f32:{ *:[v4f32] }:$vdata, v4i32:{ *:[v4i32] }:$rsrc, i32:{ *:[i32] }:$vindex, 0:{ *:[i32] }, (BUFSOffset:{ *:[i32] } i32:{ *:[i32] }:$soffset), (timm:{ *:[i32] }):$offset, (timm:{ *:[i32] }):$auxiliary, (timm:{ *:[i1] }))  =>  (BUFFER_STORE_FORMAT_XYZW_IDXEN_exact anonymous_15034:{ *:[v4f32] }:$vdata, VGPR_32:{ *:[i32] }:$vindex, SReg_128:{ *:[v4i32] }:$rsrc, SCSrc_b32:{ *:[i32] }:$soffset, (timm:{ *:[i32] }):$offset, (extract_cpol:{ *:[i32] } ?:{ *:[i32] }:$auxiliary), (extract_swz:{ *:[i1] } ?:{ *:[i32] }:$auxiliary))
        GIR_BuildMI, /*InsnID*/0, /*Opcode*/GIMT_Encode2(AMDGPU::BUFFER_STORE_FORMAT_XYZW_IDXEN_exact),
        GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/0, // vdata
        GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/2, // vindex
        GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/1, // rsrc
        GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/0, // soffset
        GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/5, // offset
        GIR_CustomOperandRenderer, /*InsnID*/0, /*OldInsnID*/0, /*OpIdx*/6, /*OperandRenderer*/GIMT_Encode2(GICR_renderExtractCPol), // auxiliary
        GIR_CustomOperandRenderer, /*InsnID*/0, /*OldInsnID*/0, /*OpIdx*/6, /*OperandRenderer*/GIMT_Encode2(GICR_renderExtractSWZ), // auxiliary
        GIR_MergeMemOperands, /*InsnID*/0, /*NumInsns*/1, /*MergeInsnID's*/0,
        GIR_ConstrainSelectedInstOperands, /*InsnID*/0,
        GIR_EraseFromParent, /*InsnID*/0,
        // GIR_Coverage, 4283,
        GIR_Done,
      // Label 6959: @511388
      GIM_Try, /*On fail goto*//*Label 6960*/ GIMT_Encode4(511459), // Rule ID 4287 //
        GIM_CheckConstantInt8, /*MI*/0, /*Op*/3, 0,
        // MIs[0] offset
        GIM_CheckIsImm, /*MI*/0, /*Op*/5,
        // MIs[0] auxiliary
        GIM_CheckIsImm, /*MI*/0, /*Op*/6,
        // MIs[0] Operand 7
        GIM_CheckIsImm, /*MI*/0, /*Op*/7,
        GIM_CheckComplexPattern, /*MI*/0, /*Op*/4, /*Renderer*/GIMT_Encode2(0), GIMT_Encode2(GICP_gi_buf_soffset),
        // (SIbuffer_store_format v4f32:{ *:[v4f32] }:$vdata, v4i32:{ *:[v4i32] }:$rsrc, i32:{ *:[i32] }:$vindex, 0:{ *:[i32] }, (BUFSOffset:{ *:[i32] } i32:{ *:[i32] }:$soffset), (timm:{ *:[i32] }):$offset, (timm:{ *:[i32] }):$auxiliary, (timm:{ *:[i1] }))  =>  (BUFFER_STORE_FORMAT_XYZW_VBUFFER_IDXEN_exact anonymous_15034:{ *:[v4f32] }:$vdata, VGPR_32:{ *:[i32] }:$vindex, SReg_128:{ *:[v4i32] }:$rsrc, SCSrc_b32:{ *:[i32] }:$soffset, (timm:{ *:[i32] }):$offset, (extract_cpol:{ *:[i32] } ?:{ *:[i32] }:$auxiliary), (extract_swz:{ *:[i1] } ?:{ *:[i32] }:$auxiliary))
        GIR_BuildMI, /*InsnID*/0, /*Opcode*/GIMT_Encode2(AMDGPU::BUFFER_STORE_FORMAT_XYZW_VBUFFER_IDXEN_exact),
        GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/0, // vdata
        GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/2, // vindex
        GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/1, // rsrc
        GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/0, // soffset
        GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/5, // offset
        GIR_CustomOperandRenderer, /*InsnID*/0, /*OldInsnID*/0, /*OpIdx*/6, /*OperandRenderer*/GIMT_Encode2(GICR_renderExtractCPol), // auxiliary
        GIR_CustomOperandRenderer, /*InsnID*/0, /*OldInsnID*/0, /*OpIdx*/6, /*OperandRenderer*/GIMT_Encode2(GICR_renderExtractSWZ), // auxiliary
        GIR_MergeMemOperands, /*InsnID*/0, /*NumInsns*/1, /*MergeInsnID's*/0,
        GIR_ConstrainSelectedInstOperands, /*InsnID*/0,
        GIR_EraseFromParent, /*InsnID*/0,
        // GIR_Coverage, 4287,
        GIR_Done,
      // Label 6960: @511459
      GIM_Try, /*On fail goto*//*Label 6961*/ GIMT_Encode4(511533), // Rule ID 4291 //
        GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasUnrestrictedSOffset),
        GIM_CheckConstantInt8, /*MI*/0, /*Op*/3, 0,
        // MIs[0] offset
        GIM_CheckIsImm, /*MI*/0, /*Op*/5,
        // MIs[0] auxiliary
        GIM_CheckIsImm, /*MI*/0, /*Op*/6,
        // MIs[0] Operand 7
        GIM_CheckIsImm, /*MI*/0, /*Op*/7,
        GIM_CheckComplexPattern, /*MI*/0, /*Op*/4, /*Renderer*/GIMT_Encode2(0), GIMT_Encode2(GICP_gi_buf_soffset),
        // (SIbuffer_store_format v4i32:{ *:[v4i32] }:$vdata, v4i32:{ *:[v4i32] }:$rsrc, i32:{ *:[i32] }:$vindex, 0:{ *:[i32] }, (BUFSOffset:{ *:[i32] } i32:{ *:[i32] }:$soffset), (timm:{ *:[i32] }):$offset, (timm:{ *:[i32] }):$auxiliary, (timm:{ *:[i1] }))  =>  (BUFFER_STORE_FORMAT_XYZW_IDXEN_exact anonymous_15034:{ *:[v4i32] }:$vdata, VGPR_32:{ *:[i32] }:$vindex, SReg_128:{ *:[v4i32] }:$rsrc, SCSrc_b32:{ *:[i32] }:$soffset, (timm:{ *:[i32] }):$offset, (extract_cpol:{ *:[i32] } ?:{ *:[i32] }:$auxiliary), (extract_swz:{ *:[i1] } ?:{ *:[i32] }:$auxiliary))
        GIR_BuildMI, /*InsnID*/0, /*Opcode*/GIMT_Encode2(AMDGPU::BUFFER_STORE_FORMAT_XYZW_IDXEN_exact),
        GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/0, // vdata
        GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/2, // vindex
        GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/1, // rsrc
        GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/0, // soffset
        GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/5, // offset
        GIR_CustomOperandRenderer, /*InsnID*/0, /*OldInsnID*/0, /*OpIdx*/6, /*OperandRenderer*/GIMT_Encode2(GICR_renderExtractCPol), // auxiliary
        GIR_CustomOperandRenderer, /*InsnID*/0, /*OldInsnID*/0, /*OpIdx*/6, /*OperandRenderer*/GIMT_Encode2(GICR_renderExtractSWZ), // auxiliary
        GIR_MergeMemOperands, /*InsnID*/0, /*NumInsns*/1, /*MergeInsnID's*/0,
        GIR_ConstrainSelectedInstOperands, /*InsnID*/0,
        GIR_EraseFromParent, /*InsnID*/0,
        // GIR_Coverage, 4291,
        GIR_Done,
      // Label 6961: @511533
      GIM_Try, /*On fail goto*//*Label 6962*/ GIMT_Encode4(511604), // Rule ID 4295 //
        GIM_CheckConstantInt8, /*MI*/0, /*Op*/3, 0,
        // MIs[0] offset
        GIM_CheckIsImm, /*MI*/0, /*Op*/5,
        // MIs[0] auxiliary
        GIM_CheckIsImm, /*MI*/0, /*Op*/6,
        // MIs[0] Operand 7
        GIM_CheckIsImm, /*MI*/0, /*Op*/7,
        GIM_CheckComplexPattern, /*MI*/0, /*Op*/4, /*Renderer*/GIMT_Encode2(0), GIMT_Encode2(GICP_gi_buf_soffset),
        // (SIbuffer_store_format v4i32:{ *:[v4i32] }:$vdata, v4i32:{ *:[v4i32] }:$rsrc, i32:{ *:[i32] }:$vindex, 0:{ *:[i32] }, (BUFSOffset:{ *:[i32] } i32:{ *:[i32] }:$soffset), (timm:{ *:[i32] }):$offset, (timm:{ *:[i32] }):$auxiliary, (timm:{ *:[i1] }))  =>  (BUFFER_STORE_FORMAT_XYZW_VBUFFER_IDXEN_exact anonymous_15034:{ *:[v4i32] }:$vdata, VGPR_32:{ *:[i32] }:$vindex, SReg_128:{ *:[v4i32] }:$rsrc, SCSrc_b32:{ *:[i32] }:$soffset, (timm:{ *:[i32] }):$offset, (extract_cpol:{ *:[i32] } ?:{ *:[i32] }:$auxiliary), (extract_swz:{ *:[i1] } ?:{ *:[i32] }:$auxiliary))
        GIR_BuildMI, /*InsnID*/0, /*Opcode*/GIMT_Encode2(AMDGPU::BUFFER_STORE_FORMAT_XYZW_VBUFFER_IDXEN_exact),
        GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/0, // vdata
        GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/2, // vindex
        GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/1, // rsrc
        GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/0, // soffset
        GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/5, // offset
        GIR_CustomOperandRenderer, /*InsnID*/0, /*OldInsnID*/0, /*OpIdx*/6, /*OperandRenderer*/GIMT_Encode2(GICR_renderExtractCPol), // auxiliary
        GIR_CustomOperandRenderer, /*InsnID*/0, /*OldInsnID*/0, /*OpIdx*/6, /*OperandRenderer*/GIMT_Encode2(GICR_renderExtractSWZ), // auxiliary
        GIR_MergeMemOperands, /*InsnID*/0, /*NumInsns*/1, /*MergeInsnID's*/0,
        GIR_ConstrainSelectedInstOperands, /*InsnID*/0,
        GIR_EraseFromParent, /*InsnID*/0,
        // GIR_Coverage, 4295,
        GIR_Done,
      // Label 6962: @511604
      GIM_Try, /*On fail goto*//*Label 6963*/ GIMT_Encode4(511714), // Rule ID 4284 //
        GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasUnrestrictedSOffset),
        // MIs[0] offset
        GIM_CheckIsImm, /*MI*/0, /*Op*/5,
        // MIs[0] auxiliary
        GIM_CheckIsImm, /*MI*/0, /*Op*/6,
        // MIs[0] Operand 7
        GIM_CheckIsImm, /*MI*/0, /*Op*/7,
        GIM_CheckComplexPattern, /*MI*/0, /*Op*/4, /*Renderer*/GIMT_Encode2(0), GIMT_Encode2(GICP_gi_buf_soffset),
        // (SIbuffer_store_format v4f32:{ *:[v4f32] }:$vdata, v4i32:{ *:[v4i32] }:$rsrc, i32:{ *:[i32] }:$vindex, i32:{ *:[i32] }:$voffset, (BUFSOffset:{ *:[i32] } i32:{ *:[i32] }:$soffset), (timm:{ *:[i32] }):$offset, (timm:{ *:[i32] }):$auxiliary, (timm:{ *:[i1] }))  =>  (BUFFER_STORE_FORMAT_XYZW_BOTHEN_exact anonymous_15034:{ *:[v4f32] }:$vdata, (REG_SEQUENCE:{ *:[i64] } VReg_64:{ *:[i32] }, VGPR_32:{ *:[i32] }:$vindex, sub0:{ *:[i32] }, VGPR_32:{ *:[i32] }:$voffset, sub1:{ *:[i32] }), SReg_128:{ *:[v4i32] }:$rsrc, SCSrc_b32:{ *:[i32] }:$soffset, (timm:{ *:[i32] }):$offset, (extract_cpol:{ *:[i32] } ?:{ *:[i32] }:$auxiliary), (extract_swz:{ *:[i1] } ?:{ *:[i32] }:$auxiliary))
        GIR_MakeTempReg, /*TempRegID*/0, /*TypeID*/GILLT_s64,
        GIR_BuildMI, /*InsnID*/1, /*Opcode*/GIMT_Encode2(TargetOpcode::REG_SEQUENCE),
        GIR_AddTempRegister, /*InsnID*/1, /*TempRegID*/0, /*TempRegFlags*/GIMT_Encode2(RegState::Define),
        GIR_Copy, /*NewInsnID*/1, /*OldInsnID*/0, /*OpIdx*/2, // vindex
        GIR_AddImm8, /*InsnID*/1, /*SubRegIndex*/3,
        GIR_Copy, /*NewInsnID*/1, /*OldInsnID*/0, /*OpIdx*/3, // voffset
        GIR_AddImm8, /*InsnID*/1, /*SubRegIndex*/11,
        GIR_ConstrainOperandRC, /*InsnID*/1, /*Op*/0, GIMT_Encode2(AMDGPU::VReg_64RegClassID),
        GIR_ConstrainOperandRC, /*InsnID*/1, /*Op*/1, GIMT_Encode2(AMDGPU::VGPR_32RegClassID),
        GIR_ConstrainOperandRC, /*InsnID*/1, /*Op*/3, GIMT_Encode2(AMDGPU::VGPR_32RegClassID),
        GIR_BuildMI, /*InsnID*/0, /*Opcode*/GIMT_Encode2(AMDGPU::BUFFER_STORE_FORMAT_XYZW_BOTHEN_exact),
        GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/0, // vdata
        GIR_AddSimpleTempRegister, /*InsnID*/0, /*TempRegID*/0,
        GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/1, // rsrc
        GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/0, // soffset
        GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/5, // offset
        GIR_CustomOperandRenderer, /*InsnID*/0, /*OldInsnID*/0, /*OpIdx*/6, /*OperandRenderer*/GIMT_Encode2(GICR_renderExtractCPol), // auxiliary
        GIR_CustomOperandRenderer, /*InsnID*/0, /*OldInsnID*/0, /*OpIdx*/6, /*OperandRenderer*/GIMT_Encode2(GICR_renderExtractSWZ), // auxiliary
        GIR_MergeMemOperands, /*InsnID*/0, /*NumInsns*/1, /*MergeInsnID's*/0,
        GIR_ConstrainSelectedInstOperands, /*InsnID*/0,
        GIR_EraseFromParent, /*InsnID*/0,
        // GIR_Coverage, 4284,
        GIR_Done,
      // Label 6963: @511714
      GIM_Try, /*On fail goto*//*Label 6964*/ GIMT_Encode4(511821), // Rule ID 4288 //
        // MIs[0] offset
        GIM_CheckIsImm, /*MI*/0, /*Op*/5,
        // MIs[0] auxiliary
        GIM_CheckIsImm, /*MI*/0, /*Op*/6,
        // MIs[0] Operand 7
        GIM_CheckIsImm, /*MI*/0, /*Op*/7,
        GIM_CheckComplexPattern, /*MI*/0, /*Op*/4, /*Renderer*/GIMT_Encode2(0), GIMT_Encode2(GICP_gi_buf_soffset),
        // (SIbuffer_store_format v4f32:{ *:[v4f32] }:$vdata, v4i32:{ *:[v4i32] }:$rsrc, i32:{ *:[i32] }:$vindex, i32:{ *:[i32] }:$voffset, (BUFSOffset:{ *:[i32] } i32:{ *:[i32] }:$soffset), (timm:{ *:[i32] }):$offset, (timm:{ *:[i32] }):$auxiliary, (timm:{ *:[i1] }))  =>  (BUFFER_STORE_FORMAT_XYZW_VBUFFER_BOTHEN_exact anonymous_15034:{ *:[v4f32] }:$vdata, (REG_SEQUENCE:{ *:[i64] } VReg_64:{ *:[i32] }, VGPR_32:{ *:[i32] }:$vindex, sub0:{ *:[i32] }, VGPR_32:{ *:[i32] }:$voffset, sub1:{ *:[i32] }), SReg_128:{ *:[v4i32] }:$rsrc, SCSrc_b32:{ *:[i32] }:$soffset, (timm:{ *:[i32] }):$offset, (extract_cpol:{ *:[i32] } ?:{ *:[i32] }:$auxiliary), (extract_swz:{ *:[i1] } ?:{ *:[i32] }:$auxiliary))
        GIR_MakeTempReg, /*TempRegID*/0, /*TypeID*/GILLT_s64,
        GIR_BuildMI, /*InsnID*/1, /*Opcode*/GIMT_Encode2(TargetOpcode::REG_SEQUENCE),
        GIR_AddTempRegister, /*InsnID*/1, /*TempRegID*/0, /*TempRegFlags*/GIMT_Encode2(RegState::Define),
        GIR_Copy, /*NewInsnID*/1, /*OldInsnID*/0, /*OpIdx*/2, // vindex
        GIR_AddImm8, /*InsnID*/1, /*SubRegIndex*/3,
        GIR_Copy, /*NewInsnID*/1, /*OldInsnID*/0, /*OpIdx*/3, // voffset
        GIR_AddImm8, /*InsnID*/1, /*SubRegIndex*/11,
        GIR_ConstrainOperandRC, /*InsnID*/1, /*Op*/0, GIMT_Encode2(AMDGPU::VReg_64RegClassID),
        GIR_ConstrainOperandRC, /*InsnID*/1, /*Op*/1, GIMT_Encode2(AMDGPU::VGPR_32RegClassID),
        GIR_ConstrainOperandRC, /*InsnID*/1, /*Op*/3, GIMT_Encode2(AMDGPU::VGPR_32RegClassID),
        GIR_BuildMI, /*InsnID*/0, /*Opcode*/GIMT_Encode2(AMDGPU::BUFFER_STORE_FORMAT_XYZW_VBUFFER_BOTHEN_exact),
        GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/0, // vdata
        GIR_AddSimpleTempRegister, /*InsnID*/0, /*TempRegID*/0,
        GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/1, // rsrc
        GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/0, // soffset
        GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/5, // offset
        GIR_CustomOperandRenderer, /*InsnID*/0, /*OldInsnID*/0, /*OpIdx*/6, /*OperandRenderer*/GIMT_Encode2(GICR_renderExtractCPol), // auxiliary
        GIR_CustomOperandRenderer, /*InsnID*/0, /*OldInsnID*/0, /*OpIdx*/6, /*OperandRenderer*/GIMT_Encode2(GICR_renderExtractSWZ), // auxiliary
        GIR_MergeMemOperands, /*InsnID*/0, /*NumInsns*/1, /*MergeInsnID's*/0,
        GIR_ConstrainSelectedInstOperands, /*InsnID*/0,
        GIR_EraseFromParent, /*InsnID*/0,
        // GIR_Coverage, 4288,
        GIR_Done,
      // Label 6964: @511821
      GIM_Try, /*On fail goto*//*Label 6965*/ GIMT_Encode4(511931), // Rule ID 4292 //
        GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasUnrestrictedSOffset),
        // MIs[0] offset
        GIM_CheckIsImm, /*MI*/0, /*Op*/5,
        // MIs[0] auxiliary
        GIM_CheckIsImm, /*MI*/0, /*Op*/6,
        // MIs[0] Operand 7
        GIM_CheckIsImm, /*MI*/0, /*Op*/7,
        GIM_CheckComplexPattern, /*MI*/0, /*Op*/4, /*Renderer*/GIMT_Encode2(0), GIMT_Encode2(GICP_gi_buf_soffset),
        // (SIbuffer_store_format v4i32:{ *:[v4i32] }:$vdata, v4i32:{ *:[v4i32] }:$rsrc, i32:{ *:[i32] }:$vindex, i32:{ *:[i32] }:$voffset, (BUFSOffset:{ *:[i32] } i32:{ *:[i32] }:$soffset), (timm:{ *:[i32] }):$offset, (timm:{ *:[i32] }):$auxiliary, (timm:{ *:[i1] }))  =>  (BUFFER_STORE_FORMAT_XYZW_BOTHEN_exact anonymous_15034:{ *:[v4i32] }:$vdata, (REG_SEQUENCE:{ *:[i64] } VReg_64:{ *:[i32] }, VGPR_32:{ *:[i32] }:$vindex, sub0:{ *:[i32] }, VGPR_32:{ *:[i32] }:$voffset, sub1:{ *:[i32] }), SReg_128:{ *:[v4i32] }:$rsrc, SCSrc_b32:{ *:[i32] }:$soffset, (timm:{ *:[i32] }):$offset, (extract_cpol:{ *:[i32] } ?:{ *:[i32] }:$auxiliary), (extract_swz:{ *:[i1] } ?:{ *:[i32] }:$auxiliary))
        GIR_MakeTempReg, /*TempRegID*/0, /*TypeID*/GILLT_s64,
        GIR_BuildMI, /*InsnID*/1, /*Opcode*/GIMT_Encode2(TargetOpcode::REG_SEQUENCE),
        GIR_AddTempRegister, /*InsnID*/1, /*TempRegID*/0, /*TempRegFlags*/GIMT_Encode2(RegState::Define),
        GIR_Copy, /*NewInsnID*/1, /*OldInsnID*/0, /*OpIdx*/2, // vindex
        GIR_AddImm8, /*InsnID*/1, /*SubRegIndex*/3,
        GIR_Copy, /*NewInsnID*/1, /*OldInsnID*/0, /*OpIdx*/3, // voffset
        GIR_AddImm8, /*InsnID*/1, /*SubRegIndex*/11,
        GIR_ConstrainOperandRC, /*InsnID*/1, /*Op*/0, GIMT_Encode2(AMDGPU::VReg_64RegClassID),
        GIR_ConstrainOperandRC, /*InsnID*/1, /*Op*/1, GIMT_Encode2(AMDGPU::VGPR_32RegClassID),
        GIR_ConstrainOperandRC, /*InsnID*/1, /*Op*/3, GIMT_Encode2(AMDGPU::VGPR_32RegClassID),
        GIR_BuildMI, /*InsnID*/0, /*Opcode*/GIMT_Encode2(AMDGPU::BUFFER_STORE_FORMAT_XYZW_BOTHEN_exact),
        GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/0, // vdata
        GIR_AddSimpleTempRegister, /*InsnID*/0, /*TempRegID*/0,
        GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/1, // rsrc
        GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/0, // soffset
        GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/5, // offset
        GIR_CustomOperandRenderer, /*InsnID*/0, /*OldInsnID*/0, /*OpIdx*/6, /*OperandRenderer*/GIMT_Encode2(GICR_renderExtractCPol), // auxiliary
        GIR_CustomOperandRenderer, /*InsnID*/0, /*OldInsnID*/0, /*OpIdx*/6, /*OperandRenderer*/GIMT_Encode2(GICR_renderExtractSWZ), // auxiliary
        GIR_MergeMemOperands, /*InsnID*/0, /*NumInsns*/1, /*MergeInsnID's*/0,
        GIR_ConstrainSelectedInstOperands, /*InsnID*/0,
        GIR_EraseFromParent, /*InsnID*/0,
        // GIR_Coverage, 4292,
        GIR_Done,
      // Label 6965: @511931
      GIM_Try, /*On fail goto*//*Label 6966*/ GIMT_Encode4(512038), // Rule ID 4296 //
        // MIs[0] offset
        GIM_CheckIsImm, /*MI*/0, /*Op*/5,
        // MIs[0] auxiliary
        GIM_CheckIsImm, /*MI*/0, /*Op*/6,
        // MIs[0] Operand 7
        GIM_CheckIsImm, /*MI*/0, /*Op*/7,
        GIM_CheckComplexPattern, /*MI*/0, /*Op*/4, /*Renderer*/GIMT_Encode2(0), GIMT_Encode2(GICP_gi_buf_soffset),
        // (SIbuffer_store_format v4i32:{ *:[v4i32] }:$vdata, v4i32:{ *:[v4i32] }:$rsrc, i32:{ *:[i32] }:$vindex, i32:{ *:[i32] }:$voffset, (BUFSOffset:{ *:[i32] } i32:{ *:[i32] }:$soffset), (timm:{ *:[i32] }):$offset, (timm:{ *:[i32] }):$auxiliary, (timm:{ *:[i1] }))  =>  (BUFFER_STORE_FORMAT_XYZW_VBUFFER_BOTHEN_exact anonymous_15034:{ *:[v4i32] }:$vdata, (REG_SEQUENCE:{ *:[i64] } VReg_64:{ *:[i32] }, VGPR_32:{ *:[i32] }:$vindex, sub0:{ *:[i32] }, VGPR_32:{ *:[i32] }:$voffset, sub1:{ *:[i32] }), SReg_128:{ *:[v4i32] }:$rsrc, SCSrc_b32:{ *:[i32] }:$soffset, (timm:{ *:[i32] }):$offset, (extract_cpol:{ *:[i32] } ?:{ *:[i32] }:$auxiliary), (extract_swz:{ *:[i1] } ?:{ *:[i32] }:$auxiliary))
        GIR_MakeTempReg, /*TempRegID*/0, /*TypeID*/GILLT_s64,
        GIR_BuildMI, /*InsnID*/1, /*Opcode*/GIMT_Encode2(TargetOpcode::REG_SEQUENCE),
        GIR_AddTempRegister, /*InsnID*/1, /*TempRegID*/0, /*TempRegFlags*/GIMT_Encode2(RegState::Define),
        GIR_Copy, /*NewInsnID*/1, /*OldInsnID*/0, /*OpIdx*/2, // vindex
        GIR_AddImm8, /*InsnID*/1, /*SubRegIndex*/3,
        GIR_Copy, /*NewInsnID*/1, /*OldInsnID*/0, /*OpIdx*/3, // voffset
        GIR_AddImm8, /*InsnID*/1, /*SubRegIndex*/11,
        GIR_ConstrainOperandRC, /*InsnID*/1, /*Op*/0, GIMT_Encode2(AMDGPU::VReg_64RegClassID),
        GIR_ConstrainOperandRC, /*InsnID*/1, /*Op*/1, GIMT_Encode2(AMDGPU::VGPR_32RegClassID),
        GIR_ConstrainOperandRC, /*InsnID*/1, /*Op*/3, GIMT_Encode2(AMDGPU::VGPR_32RegClassID),
        GIR_BuildMI, /*InsnID*/0, /*Opcode*/GIMT_Encode2(AMDGPU::BUFFER_STORE_FORMAT_XYZW_VBUFFER_BOTHEN_exact),
        GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/0, // vdata
        GIR_AddSimpleTempRegister, /*InsnID*/0, /*TempRegID*/0,
        GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/1, // rsrc
        GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/0, // soffset
        GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/5, // offset
        GIR_CustomOperandRenderer, /*InsnID*/0, /*OldInsnID*/0, /*OpIdx*/6, /*OperandRenderer*/GIMT_Encode2(GICR_renderExtractCPol), // auxiliary
        GIR_CustomOperandRenderer, /*InsnID*/0, /*OldInsnID*/0, /*OpIdx*/6, /*OperandRenderer*/GIMT_Encode2(GICR_renderExtractSWZ), // auxiliary
        GIR_MergeMemOperands, /*InsnID*/0, /*NumInsns*/1, /*MergeInsnID's*/0,
        GIR_ConstrainSelectedInstOperands, /*InsnID*/0,
        GIR_EraseFromParent, /*InsnID*/0,
        // GIR_Coverage, 4296,
        GIR_Done,
      // Label 6966: @512038
      GIM_Reject,
    // Label 6950: @512039
    GIM_Reject,
    // Label 6898: @512040
    GIM_Reject,
    // Label 135: @512041
    GIM_SwitchType, /*MI*/0, /*Op*/0, /*[*/GIMT_Encode2(8), GIMT_Encode2(18), /*)*//*default:*//*Label 6974*/ GIMT_Encode4(519213),
    /*GILLT_s16*//*Label 6967*/ GIMT_Encode4(512092),
    /*GILLT_s32*//*Label 6968*/ GIMT_Encode4(514203), GIMT_Encode4(0),
    /*GILLT_v2s16*//*Label 6969*/ GIMT_Encode4(515270),
    /*GILLT_v2s32*//*Label 6970*/ GIMT_Encode4(516685), GIMT_Encode4(0),
    /*GILLT_v3s32*//*Label 6971*/ GIMT_Encode4(517056), GIMT_Encode4(0),
    /*GILLT_v4s16*//*Label 6972*/ GIMT_Encode4(517427),
    /*GILLT_v4s32*//*Label 6973*/ GIMT_Encode4(518842),
    // Label 6967: @512092
    GIM_Try, /*On fail goto*//*Label 6975*/ GIMT_Encode4(514202),
      GIM_CheckType, /*MI*/0, /*Op*/1, /*Type*/GILLT_v4s32,
      GIM_CheckType, /*MI*/0, /*Op*/2, /*Type*/GILLT_s32,
      GIM_CheckType, /*MI*/0, /*Op*/3, /*Type*/GILLT_s32,
      GIM_CheckType, /*MI*/0, /*Op*/4, /*Type*/GILLT_s32,
      GIM_Try, /*On fail goto*//*Label 6976*/ GIMT_Encode4(512195), // Rule ID 4297 //
        GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasUnpackedD16VMem),
        GIM_CheckConstantInt8, /*MI*/0, /*Op*/2, 0,
        GIM_CheckConstantInt8, /*MI*/0, /*Op*/3, 0,
        // MIs[0] offset
        GIM_CheckIsImm, /*MI*/0, /*Op*/5,
        // MIs[0] auxiliary
        GIM_CheckIsImm, /*MI*/0, /*Op*/6,
        // MIs[0] Operand 7
        GIM_CheckLiteralInt, /*MI*/0, /*Op*/7, GIMT_Encode8(0),
        GIM_CheckComplexPattern, /*MI*/0, /*Op*/4, /*Renderer*/GIMT_Encode2(0), GIMT_Encode2(GICP_gi_buf_soffset),
        // (SIbuffer_store_format_d16 f16:{ *:[f16] }:$vdata, v4i32:{ *:[v4i32] }:$rsrc, 0:{ *:[i32] }, 0:{ *:[i32] }, (BUFSOffset:{ *:[i32] } i32:{ *:[i32] }:$soffset), (timm:{ *:[i32] }):$offset, (timm:{ *:[i32] }):$auxiliary, 0:{ *:[i1] })  =>  (BUFFER_STORE_FORMAT_D16_X_gfx80_OFFSET_exact anonymous_15037:{ *:[f16] }:$vdata, SReg_128:{ *:[v4i32] }:$rsrc, SCSrc_b32:{ *:[i32] }:$soffset, (timm:{ *:[i32] }):$offset, (extract_cpol:{ *:[i32] } ?:{ *:[i32] }:$auxiliary), (extract_swz:{ *:[i1] } ?:{ *:[i32] }:$auxiliary))
        GIR_BuildMI, /*InsnID*/0, /*Opcode*/GIMT_Encode2(AMDGPU::BUFFER_STORE_FORMAT_D16_X_gfx80_OFFSET_exact),
        GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/0, // vdata
        GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/1, // rsrc
        GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/0, // soffset
        GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/5, // offset
        GIR_CustomOperandRenderer, /*InsnID*/0, /*OldInsnID*/0, /*OpIdx*/6, /*OperandRenderer*/GIMT_Encode2(GICR_renderExtractCPol), // auxiliary
        GIR_CustomOperandRenderer, /*InsnID*/0, /*OldInsnID*/0, /*OpIdx*/6, /*OperandRenderer*/GIMT_Encode2(GICR_renderExtractSWZ), // auxiliary
        GIR_MergeMemOperands, /*InsnID*/0, /*NumInsns*/1, /*MergeInsnID's*/0,
        GIR_ConstrainSelectedInstOperands, /*InsnID*/0,
        GIR_EraseFromParent, /*InsnID*/0,
        // GIR_Coverage, 4297,
        GIR_Done,
      // Label 6976: @512195
      GIM_Try, /*On fail goto*//*Label 6977*/ GIMT_Encode4(512277), // Rule ID 4301 //
        GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasUnpackedD16VMem),
        GIM_CheckConstantInt8, /*MI*/0, /*Op*/2, 0,
        GIM_CheckConstantInt8, /*MI*/0, /*Op*/3, 0,
        // MIs[0] offset
        GIM_CheckIsImm, /*MI*/0, /*Op*/5,
        // MIs[0] auxiliary
        GIM_CheckIsImm, /*MI*/0, /*Op*/6,
        // MIs[0] Operand 7
        GIM_CheckLiteralInt, /*MI*/0, /*Op*/7, GIMT_Encode8(0),
        GIM_CheckComplexPattern, /*MI*/0, /*Op*/4, /*Renderer*/GIMT_Encode2(0), GIMT_Encode2(GICP_gi_buf_soffset),
        // (SIbuffer_store_format_d16 i16:{ *:[i16] }:$vdata, v4i32:{ *:[v4i32] }:$rsrc, 0:{ *:[i32] }, 0:{ *:[i32] }, (BUFSOffset:{ *:[i32] } i32:{ *:[i32] }:$soffset), (timm:{ *:[i32] }):$offset, (timm:{ *:[i32] }):$auxiliary, 0:{ *:[i1] })  =>  (BUFFER_STORE_FORMAT_D16_X_gfx80_OFFSET_exact anonymous_15037:{ *:[i16] }:$vdata, SReg_128:{ *:[v4i32] }:$rsrc, SCSrc_b32:{ *:[i32] }:$soffset, (timm:{ *:[i32] }):$offset, (extract_cpol:{ *:[i32] } ?:{ *:[i32] }:$auxiliary), (extract_swz:{ *:[i1] } ?:{ *:[i32] }:$auxiliary))
        GIR_BuildMI, /*InsnID*/0, /*Opcode*/GIMT_Encode2(AMDGPU::BUFFER_STORE_FORMAT_D16_X_gfx80_OFFSET_exact),
        GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/0, // vdata
        GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/1, // rsrc
        GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/0, // soffset
        GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/5, // offset
        GIR_CustomOperandRenderer, /*InsnID*/0, /*OldInsnID*/0, /*OpIdx*/6, /*OperandRenderer*/GIMT_Encode2(GICR_renderExtractCPol), // auxiliary
        GIR_CustomOperandRenderer, /*InsnID*/0, /*OldInsnID*/0, /*OpIdx*/6, /*OperandRenderer*/GIMT_Encode2(GICR_renderExtractSWZ), // auxiliary
        GIR_MergeMemOperands, /*InsnID*/0, /*NumInsns*/1, /*MergeInsnID's*/0,
        GIR_ConstrainSelectedInstOperands, /*InsnID*/0,
        GIR_EraseFromParent, /*InsnID*/0,
        // GIR_Coverage, 4301,
        GIR_Done,
      // Label 6977: @512277
      GIM_Try, /*On fail goto*//*Label 6978*/ GIMT_Encode4(512359), // Rule ID 4321 //
        GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasPackedD16VMem_HasUnrestrictedSOffset),
        GIM_CheckConstantInt8, /*MI*/0, /*Op*/2, 0,
        GIM_CheckConstantInt8, /*MI*/0, /*Op*/3, 0,
        // MIs[0] offset
        GIM_CheckIsImm, /*MI*/0, /*Op*/5,
        // MIs[0] auxiliary
        GIM_CheckIsImm, /*MI*/0, /*Op*/6,
        // MIs[0] Operand 7
        GIM_CheckLiteralInt, /*MI*/0, /*Op*/7, GIMT_Encode8(0),
        GIM_CheckComplexPattern, /*MI*/0, /*Op*/4, /*Renderer*/GIMT_Encode2(0), GIMT_Encode2(GICP_gi_buf_soffset),
        // (SIbuffer_store_format_d16 f16:{ *:[f16] }:$vdata, v4i32:{ *:[v4i32] }:$rsrc, 0:{ *:[i32] }, 0:{ *:[i32] }, (BUFSOffset:{ *:[i32] } i32:{ *:[i32] }:$soffset), (timm:{ *:[i32] }):$offset, (timm:{ *:[i32] }):$auxiliary, 0:{ *:[i1] })  =>  (BUFFER_STORE_FORMAT_D16_X_OFFSET_exact anonymous_15037:{ *:[f16] }:$vdata, SReg_128:{ *:[v4i32] }:$rsrc, SCSrc_b32:{ *:[i32] }:$soffset, (timm:{ *:[i32] }):$offset, (extract_cpol:{ *:[i32] } ?:{ *:[i32] }:$auxiliary), (extract_swz:{ *:[i1] } ?:{ *:[i32] }:$auxiliary))
        GIR_BuildMI, /*InsnID*/0, /*Opcode*/GIMT_Encode2(AMDGPU::BUFFER_STORE_FORMAT_D16_X_OFFSET_exact),
        GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/0, // vdata
        GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/1, // rsrc
        GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/0, // soffset
        GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/5, // offset
        GIR_CustomOperandRenderer, /*InsnID*/0, /*OldInsnID*/0, /*OpIdx*/6, /*OperandRenderer*/GIMT_Encode2(GICR_renderExtractCPol), // auxiliary
        GIR_CustomOperandRenderer, /*InsnID*/0, /*OldInsnID*/0, /*OpIdx*/6, /*OperandRenderer*/GIMT_Encode2(GICR_renderExtractSWZ), // auxiliary
        GIR_MergeMemOperands, /*InsnID*/0, /*NumInsns*/1, /*MergeInsnID's*/0,
        GIR_ConstrainSelectedInstOperands, /*InsnID*/0,
        GIR_EraseFromParent, /*InsnID*/0,
        // GIR_Coverage, 4321,
        GIR_Done,
      // Label 6978: @512359
      GIM_Try, /*On fail goto*//*Label 6979*/ GIMT_Encode4(512441), // Rule ID 4325 //
        GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasPackedD16VMem),
        GIM_CheckConstantInt8, /*MI*/0, /*Op*/2, 0,
        GIM_CheckConstantInt8, /*MI*/0, /*Op*/3, 0,
        // MIs[0] offset
        GIM_CheckIsImm, /*MI*/0, /*Op*/5,
        // MIs[0] auxiliary
        GIM_CheckIsImm, /*MI*/0, /*Op*/6,
        // MIs[0] Operand 7
        GIM_CheckLiteralInt, /*MI*/0, /*Op*/7, GIMT_Encode8(0),
        GIM_CheckComplexPattern, /*MI*/0, /*Op*/4, /*Renderer*/GIMT_Encode2(0), GIMT_Encode2(GICP_gi_buf_soffset),
        // (SIbuffer_store_format_d16 f16:{ *:[f16] }:$vdata, v4i32:{ *:[v4i32] }:$rsrc, 0:{ *:[i32] }, 0:{ *:[i32] }, (BUFSOffset:{ *:[i32] } i32:{ *:[i32] }:$soffset), (timm:{ *:[i32] }):$offset, (timm:{ *:[i32] }):$auxiliary, 0:{ *:[i1] })  =>  (BUFFER_STORE_FORMAT_D16_X_VBUFFER_OFFSET_exact anonymous_15037:{ *:[f16] }:$vdata, SReg_128:{ *:[v4i32] }:$rsrc, SCSrc_b32:{ *:[i32] }:$soffset, (timm:{ *:[i32] }):$offset, (extract_cpol:{ *:[i32] } ?:{ *:[i32] }:$auxiliary), (extract_swz:{ *:[i1] } ?:{ *:[i32] }:$auxiliary))
        GIR_BuildMI, /*InsnID*/0, /*Opcode*/GIMT_Encode2(AMDGPU::BUFFER_STORE_FORMAT_D16_X_VBUFFER_OFFSET_exact),
        GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/0, // vdata
        GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/1, // rsrc
        GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/0, // soffset
        GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/5, // offset
        GIR_CustomOperandRenderer, /*InsnID*/0, /*OldInsnID*/0, /*OpIdx*/6, /*OperandRenderer*/GIMT_Encode2(GICR_renderExtractCPol), // auxiliary
        GIR_CustomOperandRenderer, /*InsnID*/0, /*OldInsnID*/0, /*OpIdx*/6, /*OperandRenderer*/GIMT_Encode2(GICR_renderExtractSWZ), // auxiliary
        GIR_MergeMemOperands, /*InsnID*/0, /*NumInsns*/1, /*MergeInsnID's*/0,
        GIR_ConstrainSelectedInstOperands, /*InsnID*/0,
        GIR_EraseFromParent, /*InsnID*/0,
        // GIR_Coverage, 4325,
        GIR_Done,
      // Label 6979: @512441
      GIM_Try, /*On fail goto*//*Label 6980*/ GIMT_Encode4(512523), // Rule ID 4329 //
        GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasPackedD16VMem_HasUnrestrictedSOffset),
        GIM_CheckConstantInt8, /*MI*/0, /*Op*/2, 0,
        GIM_CheckConstantInt8, /*MI*/0, /*Op*/3, 0,
        // MIs[0] offset
        GIM_CheckIsImm, /*MI*/0, /*Op*/5,
        // MIs[0] auxiliary
        GIM_CheckIsImm, /*MI*/0, /*Op*/6,
        // MIs[0] Operand 7
        GIM_CheckLiteralInt, /*MI*/0, /*Op*/7, GIMT_Encode8(0),
        GIM_CheckComplexPattern, /*MI*/0, /*Op*/4, /*Renderer*/GIMT_Encode2(0), GIMT_Encode2(GICP_gi_buf_soffset),
        // (SIbuffer_store_format_d16 i16:{ *:[i16] }:$vdata, v4i32:{ *:[v4i32] }:$rsrc, 0:{ *:[i32] }, 0:{ *:[i32] }, (BUFSOffset:{ *:[i32] } i32:{ *:[i32] }:$soffset), (timm:{ *:[i32] }):$offset, (timm:{ *:[i32] }):$auxiliary, 0:{ *:[i1] })  =>  (BUFFER_STORE_FORMAT_D16_X_OFFSET_exact anonymous_15037:{ *:[i16] }:$vdata, SReg_128:{ *:[v4i32] }:$rsrc, SCSrc_b32:{ *:[i32] }:$soffset, (timm:{ *:[i32] }):$offset, (extract_cpol:{ *:[i32] } ?:{ *:[i32] }:$auxiliary), (extract_swz:{ *:[i1] } ?:{ *:[i32] }:$auxiliary))
        GIR_BuildMI, /*InsnID*/0, /*Opcode*/GIMT_Encode2(AMDGPU::BUFFER_STORE_FORMAT_D16_X_OFFSET_exact),
        GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/0, // vdata
        GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/1, // rsrc
        GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/0, // soffset
        GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/5, // offset
        GIR_CustomOperandRenderer, /*InsnID*/0, /*OldInsnID*/0, /*OpIdx*/6, /*OperandRenderer*/GIMT_Encode2(GICR_renderExtractCPol), // auxiliary
        GIR_CustomOperandRenderer, /*InsnID*/0, /*OldInsnID*/0, /*OpIdx*/6, /*OperandRenderer*/GIMT_Encode2(GICR_renderExtractSWZ), // auxiliary
        GIR_MergeMemOperands, /*InsnID*/0, /*NumInsns*/1, /*MergeInsnID's*/0,
        GIR_ConstrainSelectedInstOperands, /*InsnID*/0,
        GIR_EraseFromParent, /*InsnID*/0,
        // GIR_Coverage, 4329,
        GIR_Done,
      // Label 6980: @512523
      GIM_Try, /*On fail goto*//*Label 6981*/ GIMT_Encode4(512605), // Rule ID 4333 //
        GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasPackedD16VMem),
        GIM_CheckConstantInt8, /*MI*/0, /*Op*/2, 0,
        GIM_CheckConstantInt8, /*MI*/0, /*Op*/3, 0,
        // MIs[0] offset
        GIM_CheckIsImm, /*MI*/0, /*Op*/5,
        // MIs[0] auxiliary
        GIM_CheckIsImm, /*MI*/0, /*Op*/6,
        // MIs[0] Operand 7
        GIM_CheckLiteralInt, /*MI*/0, /*Op*/7, GIMT_Encode8(0),
        GIM_CheckComplexPattern, /*MI*/0, /*Op*/4, /*Renderer*/GIMT_Encode2(0), GIMT_Encode2(GICP_gi_buf_soffset),
        // (SIbuffer_store_format_d16 i16:{ *:[i16] }:$vdata, v4i32:{ *:[v4i32] }:$rsrc, 0:{ *:[i32] }, 0:{ *:[i32] }, (BUFSOffset:{ *:[i32] } i32:{ *:[i32] }:$soffset), (timm:{ *:[i32] }):$offset, (timm:{ *:[i32] }):$auxiliary, 0:{ *:[i1] })  =>  (BUFFER_STORE_FORMAT_D16_X_VBUFFER_OFFSET_exact anonymous_15037:{ *:[i16] }:$vdata, SReg_128:{ *:[v4i32] }:$rsrc, SCSrc_b32:{ *:[i32] }:$soffset, (timm:{ *:[i32] }):$offset, (extract_cpol:{ *:[i32] } ?:{ *:[i32] }:$auxiliary), (extract_swz:{ *:[i1] } ?:{ *:[i32] }:$auxiliary))
        GIR_BuildMI, /*InsnID*/0, /*Opcode*/GIMT_Encode2(AMDGPU::BUFFER_STORE_FORMAT_D16_X_VBUFFER_OFFSET_exact),
        GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/0, // vdata
        GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/1, // rsrc
        GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/0, // soffset
        GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/5, // offset
        GIR_CustomOperandRenderer, /*InsnID*/0, /*OldInsnID*/0, /*OpIdx*/6, /*OperandRenderer*/GIMT_Encode2(GICR_renderExtractCPol), // auxiliary
        GIR_CustomOperandRenderer, /*InsnID*/0, /*OldInsnID*/0, /*OpIdx*/6, /*OperandRenderer*/GIMT_Encode2(GICR_renderExtractSWZ), // auxiliary
        GIR_MergeMemOperands, /*InsnID*/0, /*NumInsns*/1, /*MergeInsnID's*/0,
        GIR_ConstrainSelectedInstOperands, /*InsnID*/0,
        GIR_EraseFromParent, /*InsnID*/0,
        // GIR_Coverage, 4333,
        GIR_Done,
      // Label 6981: @512605
      GIM_Try, /*On fail goto*//*Label 6982*/ GIMT_Encode4(512687), // Rule ID 4298 //
        GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasUnpackedD16VMem),
        GIM_CheckConstantInt8, /*MI*/0, /*Op*/2, 0,
        // MIs[0] offset
        GIM_CheckIsImm, /*MI*/0, /*Op*/5,
        // MIs[0] auxiliary
        GIM_CheckIsImm, /*MI*/0, /*Op*/6,
        // MIs[0] Operand 7
        GIM_CheckLiteralInt, /*MI*/0, /*Op*/7, GIMT_Encode8(0),
        GIM_CheckComplexPattern, /*MI*/0, /*Op*/4, /*Renderer*/GIMT_Encode2(0), GIMT_Encode2(GICP_gi_buf_soffset),
        // (SIbuffer_store_format_d16 f16:{ *:[f16] }:$vdata, v4i32:{ *:[v4i32] }:$rsrc, 0:{ *:[i32] }, i32:{ *:[i32] }:$voffset, (BUFSOffset:{ *:[i32] } i32:{ *:[i32] }:$soffset), (timm:{ *:[i32] }):$offset, (timm:{ *:[i32] }):$auxiliary, 0:{ *:[i1] })  =>  (BUFFER_STORE_FORMAT_D16_X_gfx80_OFFEN_exact anonymous_15037:{ *:[f16] }:$vdata, VGPR_32:{ *:[i32] }:$voffset, SReg_128:{ *:[v4i32] }:$rsrc, SCSrc_b32:{ *:[i32] }:$soffset, (timm:{ *:[i32] }):$offset, (extract_cpol:{ *:[i32] } ?:{ *:[i32] }:$auxiliary), (extract_swz:{ *:[i1] } ?:{ *:[i32] }:$auxiliary))
        GIR_BuildMI, /*InsnID*/0, /*Opcode*/GIMT_Encode2(AMDGPU::BUFFER_STORE_FORMAT_D16_X_gfx80_OFFEN_exact),
        GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/0, // vdata
        GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/3, // voffset
        GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/1, // rsrc
        GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/0, // soffset
        GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/5, // offset
        GIR_CustomOperandRenderer, /*InsnID*/0, /*OldInsnID*/0, /*OpIdx*/6, /*OperandRenderer*/GIMT_Encode2(GICR_renderExtractCPol), // auxiliary
        GIR_CustomOperandRenderer, /*InsnID*/0, /*OldInsnID*/0, /*OpIdx*/6, /*OperandRenderer*/GIMT_Encode2(GICR_renderExtractSWZ), // auxiliary
        GIR_MergeMemOperands, /*InsnID*/0, /*NumInsns*/1, /*MergeInsnID's*/0,
        GIR_ConstrainSelectedInstOperands, /*InsnID*/0,
        GIR_EraseFromParent, /*InsnID*/0,
        // GIR_Coverage, 4298,
        GIR_Done,
      // Label 6982: @512687
      GIM_Try, /*On fail goto*//*Label 6983*/ GIMT_Encode4(512769), // Rule ID 4302 //
        GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasUnpackedD16VMem),
        GIM_CheckConstantInt8, /*MI*/0, /*Op*/2, 0,
        // MIs[0] offset
        GIM_CheckIsImm, /*MI*/0, /*Op*/5,
        // MIs[0] auxiliary
        GIM_CheckIsImm, /*MI*/0, /*Op*/6,
        // MIs[0] Operand 7
        GIM_CheckLiteralInt, /*MI*/0, /*Op*/7, GIMT_Encode8(0),
        GIM_CheckComplexPattern, /*MI*/0, /*Op*/4, /*Renderer*/GIMT_Encode2(0), GIMT_Encode2(GICP_gi_buf_soffset),
        // (SIbuffer_store_format_d16 i16:{ *:[i16] }:$vdata, v4i32:{ *:[v4i32] }:$rsrc, 0:{ *:[i32] }, i32:{ *:[i32] }:$voffset, (BUFSOffset:{ *:[i32] } i32:{ *:[i32] }:$soffset), (timm:{ *:[i32] }):$offset, (timm:{ *:[i32] }):$auxiliary, 0:{ *:[i1] })  =>  (BUFFER_STORE_FORMAT_D16_X_gfx80_OFFEN_exact anonymous_15037:{ *:[i16] }:$vdata, VGPR_32:{ *:[i32] }:$voffset, SReg_128:{ *:[v4i32] }:$rsrc, SCSrc_b32:{ *:[i32] }:$soffset, (timm:{ *:[i32] }):$offset, (extract_cpol:{ *:[i32] } ?:{ *:[i32] }:$auxiliary), (extract_swz:{ *:[i1] } ?:{ *:[i32] }:$auxiliary))
        GIR_BuildMI, /*InsnID*/0, /*Opcode*/GIMT_Encode2(AMDGPU::BUFFER_STORE_FORMAT_D16_X_gfx80_OFFEN_exact),
        GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/0, // vdata
        GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/3, // voffset
        GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/1, // rsrc
        GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/0, // soffset
        GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/5, // offset
        GIR_CustomOperandRenderer, /*InsnID*/0, /*OldInsnID*/0, /*OpIdx*/6, /*OperandRenderer*/GIMT_Encode2(GICR_renderExtractCPol), // auxiliary
        GIR_CustomOperandRenderer, /*InsnID*/0, /*OldInsnID*/0, /*OpIdx*/6, /*OperandRenderer*/GIMT_Encode2(GICR_renderExtractSWZ), // auxiliary
        GIR_MergeMemOperands, /*InsnID*/0, /*NumInsns*/1, /*MergeInsnID's*/0,
        GIR_ConstrainSelectedInstOperands, /*InsnID*/0,
        GIR_EraseFromParent, /*InsnID*/0,
        // GIR_Coverage, 4302,
        GIR_Done,
      // Label 6983: @512769
      GIM_Try, /*On fail goto*//*Label 6984*/ GIMT_Encode4(512851), // Rule ID 4322 //
        GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasPackedD16VMem_HasUnrestrictedSOffset),
        GIM_CheckConstantInt8, /*MI*/0, /*Op*/2, 0,
        // MIs[0] offset
        GIM_CheckIsImm, /*MI*/0, /*Op*/5,
        // MIs[0] auxiliary
        GIM_CheckIsImm, /*MI*/0, /*Op*/6,
        // MIs[0] Operand 7
        GIM_CheckLiteralInt, /*MI*/0, /*Op*/7, GIMT_Encode8(0),
        GIM_CheckComplexPattern, /*MI*/0, /*Op*/4, /*Renderer*/GIMT_Encode2(0), GIMT_Encode2(GICP_gi_buf_soffset),
        // (SIbuffer_store_format_d16 f16:{ *:[f16] }:$vdata, v4i32:{ *:[v4i32] }:$rsrc, 0:{ *:[i32] }, i32:{ *:[i32] }:$voffset, (BUFSOffset:{ *:[i32] } i32:{ *:[i32] }:$soffset), (timm:{ *:[i32] }):$offset, (timm:{ *:[i32] }):$auxiliary, 0:{ *:[i1] })  =>  (BUFFER_STORE_FORMAT_D16_X_OFFEN_exact anonymous_15037:{ *:[f16] }:$vdata, VGPR_32:{ *:[i32] }:$voffset, SReg_128:{ *:[v4i32] }:$rsrc, SCSrc_b32:{ *:[i32] }:$soffset, (timm:{ *:[i32] }):$offset, (extract_cpol:{ *:[i32] } ?:{ *:[i32] }:$auxiliary), (extract_swz:{ *:[i1] } ?:{ *:[i32] }:$auxiliary))
        GIR_BuildMI, /*InsnID*/0, /*Opcode*/GIMT_Encode2(AMDGPU::BUFFER_STORE_FORMAT_D16_X_OFFEN_exact),
        GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/0, // vdata
        GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/3, // voffset
        GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/1, // rsrc
        GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/0, // soffset
        GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/5, // offset
        GIR_CustomOperandRenderer, /*InsnID*/0, /*OldInsnID*/0, /*OpIdx*/6, /*OperandRenderer*/GIMT_Encode2(GICR_renderExtractCPol), // auxiliary
        GIR_CustomOperandRenderer, /*InsnID*/0, /*OldInsnID*/0, /*OpIdx*/6, /*OperandRenderer*/GIMT_Encode2(GICR_renderExtractSWZ), // auxiliary
        GIR_MergeMemOperands, /*InsnID*/0, /*NumInsns*/1, /*MergeInsnID's*/0,
        GIR_ConstrainSelectedInstOperands, /*InsnID*/0,
        GIR_EraseFromParent, /*InsnID*/0,
        // GIR_Coverage, 4322,
        GIR_Done,
      // Label 6984: @512851
      GIM_Try, /*On fail goto*//*Label 6985*/ GIMT_Encode4(512933), // Rule ID 4326 //
        GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasPackedD16VMem),
        GIM_CheckConstantInt8, /*MI*/0, /*Op*/2, 0,
        // MIs[0] offset
        GIM_CheckIsImm, /*MI*/0, /*Op*/5,
        // MIs[0] auxiliary
        GIM_CheckIsImm, /*MI*/0, /*Op*/6,
        // MIs[0] Operand 7
        GIM_CheckLiteralInt, /*MI*/0, /*Op*/7, GIMT_Encode8(0),
        GIM_CheckComplexPattern, /*MI*/0, /*Op*/4, /*Renderer*/GIMT_Encode2(0), GIMT_Encode2(GICP_gi_buf_soffset),
        // (SIbuffer_store_format_d16 f16:{ *:[f16] }:$vdata, v4i32:{ *:[v4i32] }:$rsrc, 0:{ *:[i32] }, i32:{ *:[i32] }:$voffset, (BUFSOffset:{ *:[i32] } i32:{ *:[i32] }:$soffset), (timm:{ *:[i32] }):$offset, (timm:{ *:[i32] }):$auxiliary, 0:{ *:[i1] })  =>  (BUFFER_STORE_FORMAT_D16_X_VBUFFER_OFFEN_exact anonymous_15037:{ *:[f16] }:$vdata, VGPR_32:{ *:[i32] }:$voffset, SReg_128:{ *:[v4i32] }:$rsrc, SCSrc_b32:{ *:[i32] }:$soffset, (timm:{ *:[i32] }):$offset, (extract_cpol:{ *:[i32] } ?:{ *:[i32] }:$auxiliary), (extract_swz:{ *:[i1] } ?:{ *:[i32] }:$auxiliary))
        GIR_BuildMI, /*InsnID*/0, /*Opcode*/GIMT_Encode2(AMDGPU::BUFFER_STORE_FORMAT_D16_X_VBUFFER_OFFEN_exact),
        GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/0, // vdata
        GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/3, // voffset
        GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/1, // rsrc
        GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/0, // soffset
        GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/5, // offset
        GIR_CustomOperandRenderer, /*InsnID*/0, /*OldInsnID*/0, /*OpIdx*/6, /*OperandRenderer*/GIMT_Encode2(GICR_renderExtractCPol), // auxiliary
        GIR_CustomOperandRenderer, /*InsnID*/0, /*OldInsnID*/0, /*OpIdx*/6, /*OperandRenderer*/GIMT_Encode2(GICR_renderExtractSWZ), // auxiliary
        GIR_MergeMemOperands, /*InsnID*/0, /*NumInsns*/1, /*MergeInsnID's*/0,
        GIR_ConstrainSelectedInstOperands, /*InsnID*/0,
        GIR_EraseFromParent, /*InsnID*/0,
        // GIR_Coverage, 4326,
        GIR_Done,
      // Label 6985: @512933
      GIM_Try, /*On fail goto*//*Label 6986*/ GIMT_Encode4(513015), // Rule ID 4330 //
        GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasPackedD16VMem_HasUnrestrictedSOffset),
        GIM_CheckConstantInt8, /*MI*/0, /*Op*/2, 0,
        // MIs[0] offset
        GIM_CheckIsImm, /*MI*/0, /*Op*/5,
        // MIs[0] auxiliary
        GIM_CheckIsImm, /*MI*/0, /*Op*/6,
        // MIs[0] Operand 7
        GIM_CheckLiteralInt, /*MI*/0, /*Op*/7, GIMT_Encode8(0),
        GIM_CheckComplexPattern, /*MI*/0, /*Op*/4, /*Renderer*/GIMT_Encode2(0), GIMT_Encode2(GICP_gi_buf_soffset),
        // (SIbuffer_store_format_d16 i16:{ *:[i16] }:$vdata, v4i32:{ *:[v4i32] }:$rsrc, 0:{ *:[i32] }, i32:{ *:[i32] }:$voffset, (BUFSOffset:{ *:[i32] } i32:{ *:[i32] }:$soffset), (timm:{ *:[i32] }):$offset, (timm:{ *:[i32] }):$auxiliary, 0:{ *:[i1] })  =>  (BUFFER_STORE_FORMAT_D16_X_OFFEN_exact anonymous_15037:{ *:[i16] }:$vdata, VGPR_32:{ *:[i32] }:$voffset, SReg_128:{ *:[v4i32] }:$rsrc, SCSrc_b32:{ *:[i32] }:$soffset, (timm:{ *:[i32] }):$offset, (extract_cpol:{ *:[i32] } ?:{ *:[i32] }:$auxiliary), (extract_swz:{ *:[i1] } ?:{ *:[i32] }:$auxiliary))
        GIR_BuildMI, /*InsnID*/0, /*Opcode*/GIMT_Encode2(AMDGPU::BUFFER_STORE_FORMAT_D16_X_OFFEN_exact),
        GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/0, // vdata
        GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/3, // voffset
        GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/1, // rsrc
        GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/0, // soffset
        GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/5, // offset
        GIR_CustomOperandRenderer, /*InsnID*/0, /*OldInsnID*/0, /*OpIdx*/6, /*OperandRenderer*/GIMT_Encode2(GICR_renderExtractCPol), // auxiliary
        GIR_CustomOperandRenderer, /*InsnID*/0, /*OldInsnID*/0, /*OpIdx*/6, /*OperandRenderer*/GIMT_Encode2(GICR_renderExtractSWZ), // auxiliary
        GIR_MergeMemOperands, /*InsnID*/0, /*NumInsns*/1, /*MergeInsnID's*/0,
        GIR_ConstrainSelectedInstOperands, /*InsnID*/0,
        GIR_EraseFromParent, /*InsnID*/0,
        // GIR_Coverage, 4330,
        GIR_Done,
      // Label 6986: @513015
      GIM_Try, /*On fail goto*//*Label 6987*/ GIMT_Encode4(513097), // Rule ID 4334 //
        GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasPackedD16VMem),
        GIM_CheckConstantInt8, /*MI*/0, /*Op*/2, 0,
        // MIs[0] offset
        GIM_CheckIsImm, /*MI*/0, /*Op*/5,
        // MIs[0] auxiliary
        GIM_CheckIsImm, /*MI*/0, /*Op*/6,
        // MIs[0] Operand 7
        GIM_CheckLiteralInt, /*MI*/0, /*Op*/7, GIMT_Encode8(0),
        GIM_CheckComplexPattern, /*MI*/0, /*Op*/4, /*Renderer*/GIMT_Encode2(0), GIMT_Encode2(GICP_gi_buf_soffset),
        // (SIbuffer_store_format_d16 i16:{ *:[i16] }:$vdata, v4i32:{ *:[v4i32] }:$rsrc, 0:{ *:[i32] }, i32:{ *:[i32] }:$voffset, (BUFSOffset:{ *:[i32] } i32:{ *:[i32] }:$soffset), (timm:{ *:[i32] }):$offset, (timm:{ *:[i32] }):$auxiliary, 0:{ *:[i1] })  =>  (BUFFER_STORE_FORMAT_D16_X_VBUFFER_OFFEN_exact anonymous_15037:{ *:[i16] }:$vdata, VGPR_32:{ *:[i32] }:$voffset, SReg_128:{ *:[v4i32] }:$rsrc, SCSrc_b32:{ *:[i32] }:$soffset, (timm:{ *:[i32] }):$offset, (extract_cpol:{ *:[i32] } ?:{ *:[i32] }:$auxiliary), (extract_swz:{ *:[i1] } ?:{ *:[i32] }:$auxiliary))
        GIR_BuildMI, /*InsnID*/0, /*Opcode*/GIMT_Encode2(AMDGPU::BUFFER_STORE_FORMAT_D16_X_VBUFFER_OFFEN_exact),
        GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/0, // vdata
        GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/3, // voffset
        GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/1, // rsrc
        GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/0, // soffset
        GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/5, // offset
        GIR_CustomOperandRenderer, /*InsnID*/0, /*OldInsnID*/0, /*OpIdx*/6, /*OperandRenderer*/GIMT_Encode2(GICR_renderExtractCPol), // auxiliary
        GIR_CustomOperandRenderer, /*InsnID*/0, /*OldInsnID*/0, /*OpIdx*/6, /*OperandRenderer*/GIMT_Encode2(GICR_renderExtractSWZ), // auxiliary
        GIR_MergeMemOperands, /*InsnID*/0, /*NumInsns*/1, /*MergeInsnID's*/0,
        GIR_ConstrainSelectedInstOperands, /*InsnID*/0,
        GIR_EraseFromParent, /*InsnID*/0,
        // GIR_Coverage, 4334,
        GIR_Done,
      // Label 6987: @513097
      GIM_Try, /*On fail goto*//*Label 6988*/ GIMT_Encode4(513171), // Rule ID 4299 //
        GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasUnpackedD16VMem),
        GIM_CheckConstantInt8, /*MI*/0, /*Op*/3, 0,
        // MIs[0] offset
        GIM_CheckIsImm, /*MI*/0, /*Op*/5,
        // MIs[0] auxiliary
        GIM_CheckIsImm, /*MI*/0, /*Op*/6,
        // MIs[0] Operand 7
        GIM_CheckIsImm, /*MI*/0, /*Op*/7,
        GIM_CheckComplexPattern, /*MI*/0, /*Op*/4, /*Renderer*/GIMT_Encode2(0), GIMT_Encode2(GICP_gi_buf_soffset),
        // (SIbuffer_store_format_d16 f16:{ *:[f16] }:$vdata, v4i32:{ *:[v4i32] }:$rsrc, i32:{ *:[i32] }:$vindex, 0:{ *:[i32] }, (BUFSOffset:{ *:[i32] } i32:{ *:[i32] }:$soffset), (timm:{ *:[i32] }):$offset, (timm:{ *:[i32] }):$auxiliary, (timm:{ *:[i1] }))  =>  (BUFFER_STORE_FORMAT_D16_X_gfx80_IDXEN_exact anonymous_15037:{ *:[f16] }:$vdata, VGPR_32:{ *:[i32] }:$vindex, SReg_128:{ *:[v4i32] }:$rsrc, SCSrc_b32:{ *:[i32] }:$soffset, (timm:{ *:[i32] }):$offset, (extract_cpol:{ *:[i32] } ?:{ *:[i32] }:$auxiliary), (extract_swz:{ *:[i1] } ?:{ *:[i32] }:$auxiliary))
        GIR_BuildMI, /*InsnID*/0, /*Opcode*/GIMT_Encode2(AMDGPU::BUFFER_STORE_FORMAT_D16_X_gfx80_IDXEN_exact),
        GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/0, // vdata
        GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/2, // vindex
        GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/1, // rsrc
        GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/0, // soffset
        GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/5, // offset
        GIR_CustomOperandRenderer, /*InsnID*/0, /*OldInsnID*/0, /*OpIdx*/6, /*OperandRenderer*/GIMT_Encode2(GICR_renderExtractCPol), // auxiliary
        GIR_CustomOperandRenderer, /*InsnID*/0, /*OldInsnID*/0, /*OpIdx*/6, /*OperandRenderer*/GIMT_Encode2(GICR_renderExtractSWZ), // auxiliary
        GIR_MergeMemOperands, /*InsnID*/0, /*NumInsns*/1, /*MergeInsnID's*/0,
        GIR_ConstrainSelectedInstOperands, /*InsnID*/0,
        GIR_EraseFromParent, /*InsnID*/0,
        // GIR_Coverage, 4299,
        GIR_Done,
      // Label 6988: @513171
      GIM_Try, /*On fail goto*//*Label 6989*/ GIMT_Encode4(513245), // Rule ID 4303 //
        GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasUnpackedD16VMem),
        GIM_CheckConstantInt8, /*MI*/0, /*Op*/3, 0,
        // MIs[0] offset
        GIM_CheckIsImm, /*MI*/0, /*Op*/5,
        // MIs[0] auxiliary
        GIM_CheckIsImm, /*MI*/0, /*Op*/6,
        // MIs[0] Operand 7
        GIM_CheckIsImm, /*MI*/0, /*Op*/7,
        GIM_CheckComplexPattern, /*MI*/0, /*Op*/4, /*Renderer*/GIMT_Encode2(0), GIMT_Encode2(GICP_gi_buf_soffset),
        // (SIbuffer_store_format_d16 i16:{ *:[i16] }:$vdata, v4i32:{ *:[v4i32] }:$rsrc, i32:{ *:[i32] }:$vindex, 0:{ *:[i32] }, (BUFSOffset:{ *:[i32] } i32:{ *:[i32] }:$soffset), (timm:{ *:[i32] }):$offset, (timm:{ *:[i32] }):$auxiliary, (timm:{ *:[i1] }))  =>  (BUFFER_STORE_FORMAT_D16_X_gfx80_IDXEN_exact anonymous_15037:{ *:[i16] }:$vdata, VGPR_32:{ *:[i32] }:$vindex, SReg_128:{ *:[v4i32] }:$rsrc, SCSrc_b32:{ *:[i32] }:$soffset, (timm:{ *:[i32] }):$offset, (extract_cpol:{ *:[i32] } ?:{ *:[i32] }:$auxiliary), (extract_swz:{ *:[i1] } ?:{ *:[i32] }:$auxiliary))
        GIR_BuildMI, /*InsnID*/0, /*Opcode*/GIMT_Encode2(AMDGPU::BUFFER_STORE_FORMAT_D16_X_gfx80_IDXEN_exact),
        GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/0, // vdata
        GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/2, // vindex
        GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/1, // rsrc
        GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/0, // soffset
        GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/5, // offset
        GIR_CustomOperandRenderer, /*InsnID*/0, /*OldInsnID*/0, /*OpIdx*/6, /*OperandRenderer*/GIMT_Encode2(GICR_renderExtractCPol), // auxiliary
        GIR_CustomOperandRenderer, /*InsnID*/0, /*OldInsnID*/0, /*OpIdx*/6, /*OperandRenderer*/GIMT_Encode2(GICR_renderExtractSWZ), // auxiliary
        GIR_MergeMemOperands, /*InsnID*/0, /*NumInsns*/1, /*MergeInsnID's*/0,
        GIR_ConstrainSelectedInstOperands, /*InsnID*/0,
        GIR_EraseFromParent, /*InsnID*/0,
        // GIR_Coverage, 4303,
        GIR_Done,
      // Label 6989: @513245
      GIM_Try, /*On fail goto*//*Label 6990*/ GIMT_Encode4(513319), // Rule ID 4323 //
        GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasPackedD16VMem_HasUnrestrictedSOffset),
        GIM_CheckConstantInt8, /*MI*/0, /*Op*/3, 0,
        // MIs[0] offset
        GIM_CheckIsImm, /*MI*/0, /*Op*/5,
        // MIs[0] auxiliary
        GIM_CheckIsImm, /*MI*/0, /*Op*/6,
        // MIs[0] Operand 7
        GIM_CheckIsImm, /*MI*/0, /*Op*/7,
        GIM_CheckComplexPattern, /*MI*/0, /*Op*/4, /*Renderer*/GIMT_Encode2(0), GIMT_Encode2(GICP_gi_buf_soffset),
        // (SIbuffer_store_format_d16 f16:{ *:[f16] }:$vdata, v4i32:{ *:[v4i32] }:$rsrc, i32:{ *:[i32] }:$vindex, 0:{ *:[i32] }, (BUFSOffset:{ *:[i32] } i32:{ *:[i32] }:$soffset), (timm:{ *:[i32] }):$offset, (timm:{ *:[i32] }):$auxiliary, (timm:{ *:[i1] }))  =>  (BUFFER_STORE_FORMAT_D16_X_IDXEN_exact anonymous_15037:{ *:[f16] }:$vdata, VGPR_32:{ *:[i32] }:$vindex, SReg_128:{ *:[v4i32] }:$rsrc, SCSrc_b32:{ *:[i32] }:$soffset, (timm:{ *:[i32] }):$offset, (extract_cpol:{ *:[i32] } ?:{ *:[i32] }:$auxiliary), (extract_swz:{ *:[i1] } ?:{ *:[i32] }:$auxiliary))
        GIR_BuildMI, /*InsnID*/0, /*Opcode*/GIMT_Encode2(AMDGPU::BUFFER_STORE_FORMAT_D16_X_IDXEN_exact),
        GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/0, // vdata
        GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/2, // vindex
        GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/1, // rsrc
        GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/0, // soffset
        GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/5, // offset
        GIR_CustomOperandRenderer, /*InsnID*/0, /*OldInsnID*/0, /*OpIdx*/6, /*OperandRenderer*/GIMT_Encode2(GICR_renderExtractCPol), // auxiliary
        GIR_CustomOperandRenderer, /*InsnID*/0, /*OldInsnID*/0, /*OpIdx*/6, /*OperandRenderer*/GIMT_Encode2(GICR_renderExtractSWZ), // auxiliary
        GIR_MergeMemOperands, /*InsnID*/0, /*NumInsns*/1, /*MergeInsnID's*/0,
        GIR_ConstrainSelectedInstOperands, /*InsnID*/0,
        GIR_EraseFromParent, /*InsnID*/0,
        // GIR_Coverage, 4323,
        GIR_Done,
      // Label 6990: @513319
      GIM_Try, /*On fail goto*//*Label 6991*/ GIMT_Encode4(513393), // Rule ID 4327 //
        GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasPackedD16VMem),
        GIM_CheckConstantInt8, /*MI*/0, /*Op*/3, 0,
        // MIs[0] offset
        GIM_CheckIsImm, /*MI*/0, /*Op*/5,
        // MIs[0] auxiliary
        GIM_CheckIsImm, /*MI*/0, /*Op*/6,
        // MIs[0] Operand 7
        GIM_CheckIsImm, /*MI*/0, /*Op*/7,
        GIM_CheckComplexPattern, /*MI*/0, /*Op*/4, /*Renderer*/GIMT_Encode2(0), GIMT_Encode2(GICP_gi_buf_soffset),
        // (SIbuffer_store_format_d16 f16:{ *:[f16] }:$vdata, v4i32:{ *:[v4i32] }:$rsrc, i32:{ *:[i32] }:$vindex, 0:{ *:[i32] }, (BUFSOffset:{ *:[i32] } i32:{ *:[i32] }:$soffset), (timm:{ *:[i32] }):$offset, (timm:{ *:[i32] }):$auxiliary, (timm:{ *:[i1] }))  =>  (BUFFER_STORE_FORMAT_D16_X_VBUFFER_IDXEN_exact anonymous_15037:{ *:[f16] }:$vdata, VGPR_32:{ *:[i32] }:$vindex, SReg_128:{ *:[v4i32] }:$rsrc, SCSrc_b32:{ *:[i32] }:$soffset, (timm:{ *:[i32] }):$offset, (extract_cpol:{ *:[i32] } ?:{ *:[i32] }:$auxiliary), (extract_swz:{ *:[i1] } ?:{ *:[i32] }:$auxiliary))
        GIR_BuildMI, /*InsnID*/0, /*Opcode*/GIMT_Encode2(AMDGPU::BUFFER_STORE_FORMAT_D16_X_VBUFFER_IDXEN_exact),
        GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/0, // vdata
        GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/2, // vindex
        GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/1, // rsrc
        GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/0, // soffset
        GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/5, // offset
        GIR_CustomOperandRenderer, /*InsnID*/0, /*OldInsnID*/0, /*OpIdx*/6, /*OperandRenderer*/GIMT_Encode2(GICR_renderExtractCPol), // auxiliary
        GIR_CustomOperandRenderer, /*InsnID*/0, /*OldInsnID*/0, /*OpIdx*/6, /*OperandRenderer*/GIMT_Encode2(GICR_renderExtractSWZ), // auxiliary
        GIR_MergeMemOperands, /*InsnID*/0, /*NumInsns*/1, /*MergeInsnID's*/0,
        GIR_ConstrainSelectedInstOperands, /*InsnID*/0,
        GIR_EraseFromParent, /*InsnID*/0,
        // GIR_Coverage, 4327,
        GIR_Done,
      // Label 6991: @513393
      GIM_Try, /*On fail goto*//*Label 6992*/ GIMT_Encode4(513467), // Rule ID 4331 //
        GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasPackedD16VMem_HasUnrestrictedSOffset),
        GIM_CheckConstantInt8, /*MI*/0, /*Op*/3, 0,
        // MIs[0] offset
        GIM_CheckIsImm, /*MI*/0, /*Op*/5,
        // MIs[0] auxiliary
        GIM_CheckIsImm, /*MI*/0, /*Op*/6,
        // MIs[0] Operand 7
        GIM_CheckIsImm, /*MI*/0, /*Op*/7,
        GIM_CheckComplexPattern, /*MI*/0, /*Op*/4, /*Renderer*/GIMT_Encode2(0), GIMT_Encode2(GICP_gi_buf_soffset),
        // (SIbuffer_store_format_d16 i16:{ *:[i16] }:$vdata, v4i32:{ *:[v4i32] }:$rsrc, i32:{ *:[i32] }:$vindex, 0:{ *:[i32] }, (BUFSOffset:{ *:[i32] } i32:{ *:[i32] }:$soffset), (timm:{ *:[i32] }):$offset, (timm:{ *:[i32] }):$auxiliary, (timm:{ *:[i1] }))  =>  (BUFFER_STORE_FORMAT_D16_X_IDXEN_exact anonymous_15037:{ *:[i16] }:$vdata, VGPR_32:{ *:[i32] }:$vindex, SReg_128:{ *:[v4i32] }:$rsrc, SCSrc_b32:{ *:[i32] }:$soffset, (timm:{ *:[i32] }):$offset, (extract_cpol:{ *:[i32] } ?:{ *:[i32] }:$auxiliary), (extract_swz:{ *:[i1] } ?:{ *:[i32] }:$auxiliary))
        GIR_BuildMI, /*InsnID*/0, /*Opcode*/GIMT_Encode2(AMDGPU::BUFFER_STORE_FORMAT_D16_X_IDXEN_exact),
        GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/0, // vdata
        GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/2, // vindex
        GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/1, // rsrc
        GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/0, // soffset
        GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/5, // offset
        GIR_CustomOperandRenderer, /*InsnID*/0, /*OldInsnID*/0, /*OpIdx*/6, /*OperandRenderer*/GIMT_Encode2(GICR_renderExtractCPol), // auxiliary
        GIR_CustomOperandRenderer, /*InsnID*/0, /*OldInsnID*/0, /*OpIdx*/6, /*OperandRenderer*/GIMT_Encode2(GICR_renderExtractSWZ), // auxiliary
        GIR_MergeMemOperands, /*InsnID*/0, /*NumInsns*/1, /*MergeInsnID's*/0,
        GIR_ConstrainSelectedInstOperands, /*InsnID*/0,
        GIR_EraseFromParent, /*InsnID*/0,
        // GIR_Coverage, 4331,
        GIR_Done,
      // Label 6992: @513467
      GIM_Try, /*On fail goto*//*Label 6993*/ GIMT_Encode4(513541), // Rule ID 4335 //
        GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasPackedD16VMem),
        GIM_CheckConstantInt8, /*MI*/0, /*Op*/3, 0,
        // MIs[0] offset
        GIM_CheckIsImm, /*MI*/0, /*Op*/5,
        // MIs[0] auxiliary
        GIM_CheckIsImm, /*MI*/0, /*Op*/6,
        // MIs[0] Operand 7
        GIM_CheckIsImm, /*MI*/0, /*Op*/7,
        GIM_CheckComplexPattern, /*MI*/0, /*Op*/4, /*Renderer*/GIMT_Encode2(0), GIMT_Encode2(GICP_gi_buf_soffset),
        // (SIbuffer_store_format_d16 i16:{ *:[i16] }:$vdata, v4i32:{ *:[v4i32] }:$rsrc, i32:{ *:[i32] }:$vindex, 0:{ *:[i32] }, (BUFSOffset:{ *:[i32] } i32:{ *:[i32] }:$soffset), (timm:{ *:[i32] }):$offset, (timm:{ *:[i32] }):$auxiliary, (timm:{ *:[i1] }))  =>  (BUFFER_STORE_FORMAT_D16_X_VBUFFER_IDXEN_exact anonymous_15037:{ *:[i16] }:$vdata, VGPR_32:{ *:[i32] }:$vindex, SReg_128:{ *:[v4i32] }:$rsrc, SCSrc_b32:{ *:[i32] }:$soffset, (timm:{ *:[i32] }):$offset, (extract_cpol:{ *:[i32] } ?:{ *:[i32] }:$auxiliary), (extract_swz:{ *:[i1] } ?:{ *:[i32] }:$auxiliary))
        GIR_BuildMI, /*InsnID*/0, /*Opcode*/GIMT_Encode2(AMDGPU::BUFFER_STORE_FORMAT_D16_X_VBUFFER_IDXEN_exact),
        GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/0, // vdata
        GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/2, // vindex
        GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/1, // rsrc
        GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/0, // soffset
        GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/5, // offset
        GIR_CustomOperandRenderer, /*InsnID*/0, /*OldInsnID*/0, /*OpIdx*/6, /*OperandRenderer*/GIMT_Encode2(GICR_renderExtractCPol), // auxiliary
        GIR_CustomOperandRenderer, /*InsnID*/0, /*OldInsnID*/0, /*OpIdx*/6, /*OperandRenderer*/GIMT_Encode2(GICR_renderExtractSWZ), // auxiliary
        GIR_MergeMemOperands, /*InsnID*/0, /*NumInsns*/1, /*MergeInsnID's*/0,
        GIR_ConstrainSelectedInstOperands, /*InsnID*/0,
        GIR_EraseFromParent, /*InsnID*/0,
        // GIR_Coverage, 4335,
        GIR_Done,
      // Label 6993: @513541
      GIM_Try, /*On fail goto*//*Label 6994*/ GIMT_Encode4(513651), // Rule ID 4300 //
        GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasUnpackedD16VMem),
        // MIs[0] offset
        GIM_CheckIsImm, /*MI*/0, /*Op*/5,
        // MIs[0] auxiliary
        GIM_CheckIsImm, /*MI*/0, /*Op*/6,
        // MIs[0] Operand 7
        GIM_CheckIsImm, /*MI*/0, /*Op*/7,
        GIM_CheckComplexPattern, /*MI*/0, /*Op*/4, /*Renderer*/GIMT_Encode2(0), GIMT_Encode2(GICP_gi_buf_soffset),
        // (SIbuffer_store_format_d16 f16:{ *:[f16] }:$vdata, v4i32:{ *:[v4i32] }:$rsrc, i32:{ *:[i32] }:$vindex, i32:{ *:[i32] }:$voffset, (BUFSOffset:{ *:[i32] } i32:{ *:[i32] }:$soffset), (timm:{ *:[i32] }):$offset, (timm:{ *:[i32] }):$auxiliary, (timm:{ *:[i1] }))  =>  (BUFFER_STORE_FORMAT_D16_X_gfx80_BOTHEN_exact anonymous_15037:{ *:[f16] }:$vdata, (REG_SEQUENCE:{ *:[i64] } VReg_64:{ *:[i32] }, VGPR_32:{ *:[i32] }:$vindex, sub0:{ *:[i32] }, VGPR_32:{ *:[i32] }:$voffset, sub1:{ *:[i32] }), SReg_128:{ *:[v4i32] }:$rsrc, SCSrc_b32:{ *:[i32] }:$soffset, (timm:{ *:[i32] }):$offset, (extract_cpol:{ *:[i32] } ?:{ *:[i32] }:$auxiliary), (extract_swz:{ *:[i1] } ?:{ *:[i32] }:$auxiliary))
        GIR_MakeTempReg, /*TempRegID*/0, /*TypeID*/GILLT_s64,
        GIR_BuildMI, /*InsnID*/1, /*Opcode*/GIMT_Encode2(TargetOpcode::REG_SEQUENCE),
        GIR_AddTempRegister, /*InsnID*/1, /*TempRegID*/0, /*TempRegFlags*/GIMT_Encode2(RegState::Define),
        GIR_Copy, /*NewInsnID*/1, /*OldInsnID*/0, /*OpIdx*/2, // vindex
        GIR_AddImm8, /*InsnID*/1, /*SubRegIndex*/3,
        GIR_Copy, /*NewInsnID*/1, /*OldInsnID*/0, /*OpIdx*/3, // voffset
        GIR_AddImm8, /*InsnID*/1, /*SubRegIndex*/11,
        GIR_ConstrainOperandRC, /*InsnID*/1, /*Op*/0, GIMT_Encode2(AMDGPU::VReg_64RegClassID),
        GIR_ConstrainOperandRC, /*InsnID*/1, /*Op*/1, GIMT_Encode2(AMDGPU::VGPR_32RegClassID),
        GIR_ConstrainOperandRC, /*InsnID*/1, /*Op*/3, GIMT_Encode2(AMDGPU::VGPR_32RegClassID),
        GIR_BuildMI, /*InsnID*/0, /*Opcode*/GIMT_Encode2(AMDGPU::BUFFER_STORE_FORMAT_D16_X_gfx80_BOTHEN_exact),
        GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/0, // vdata
        GIR_AddSimpleTempRegister, /*InsnID*/0, /*TempRegID*/0,
        GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/1, // rsrc
        GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/0, // soffset
        GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/5, // offset
        GIR_CustomOperandRenderer, /*InsnID*/0, /*OldInsnID*/0, /*OpIdx*/6, /*OperandRenderer*/GIMT_Encode2(GICR_renderExtractCPol), // auxiliary
        GIR_CustomOperandRenderer, /*InsnID*/0, /*OldInsnID*/0, /*OpIdx*/6, /*OperandRenderer*/GIMT_Encode2(GICR_renderExtractSWZ), // auxiliary
        GIR_MergeMemOperands, /*InsnID*/0, /*NumInsns*/1, /*MergeInsnID's*/0,
        GIR_ConstrainSelectedInstOperands, /*InsnID*/0,
        GIR_EraseFromParent, /*InsnID*/0,
        // GIR_Coverage, 4300,
        GIR_Done,
      // Label 6994: @513651
      GIM_Try, /*On fail goto*//*Label 6995*/ GIMT_Encode4(513761), // Rule ID 4304 //
        GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasUnpackedD16VMem),
        // MIs[0] offset
        GIM_CheckIsImm, /*MI*/0, /*Op*/5,
        // MIs[0] auxiliary
        GIM_CheckIsImm, /*MI*/0, /*Op*/6,
        // MIs[0] Operand 7
        GIM_CheckIsImm, /*MI*/0, /*Op*/7,
        GIM_CheckComplexPattern, /*MI*/0, /*Op*/4, /*Renderer*/GIMT_Encode2(0), GIMT_Encode2(GICP_gi_buf_soffset),
        // (SIbuffer_store_format_d16 i16:{ *:[i16] }:$vdata, v4i32:{ *:[v4i32] }:$rsrc, i32:{ *:[i32] }:$vindex, i32:{ *:[i32] }:$voffset, (BUFSOffset:{ *:[i32] } i32:{ *:[i32] }:$soffset), (timm:{ *:[i32] }):$offset, (timm:{ *:[i32] }):$auxiliary, (timm:{ *:[i1] }))  =>  (BUFFER_STORE_FORMAT_D16_X_gfx80_BOTHEN_exact anonymous_15037:{ *:[i16] }:$vdata, (REG_SEQUENCE:{ *:[i64] } VReg_64:{ *:[i32] }, VGPR_32:{ *:[i32] }:$vindex, sub0:{ *:[i32] }, VGPR_32:{ *:[i32] }:$voffset, sub1:{ *:[i32] }), SReg_128:{ *:[v4i32] }:$rsrc, SCSrc_b32:{ *:[i32] }:$soffset, (timm:{ *:[i32] }):$offset, (extract_cpol:{ *:[i32] } ?:{ *:[i32] }:$auxiliary), (extract_swz:{ *:[i1] } ?:{ *:[i32] }:$auxiliary))
        GIR_MakeTempReg, /*TempRegID*/0, /*TypeID*/GILLT_s64,
        GIR_BuildMI, /*InsnID*/1, /*Opcode*/GIMT_Encode2(TargetOpcode::REG_SEQUENCE),
        GIR_AddTempRegister, /*InsnID*/1, /*TempRegID*/0, /*TempRegFlags*/GIMT_Encode2(RegState::Define),
        GIR_Copy, /*NewInsnID*/1, /*OldInsnID*/0, /*OpIdx*/2, // vindex
        GIR_AddImm8, /*InsnID*/1, /*SubRegIndex*/3,
        GIR_Copy, /*NewInsnID*/1, /*OldInsnID*/0, /*OpIdx*/3, // voffset
        GIR_AddImm8, /*InsnID*/1, /*SubRegIndex*/11,
        GIR_ConstrainOperandRC, /*InsnID*/1, /*Op*/0, GIMT_Encode2(AMDGPU::VReg_64RegClassID),
        GIR_ConstrainOperandRC, /*InsnID*/1, /*Op*/1, GIMT_Encode2(AMDGPU::VGPR_32RegClassID),
        GIR_ConstrainOperandRC, /*InsnID*/1, /*Op*/3, GIMT_Encode2(AMDGPU::VGPR_32RegClassID),
        GIR_BuildMI, /*InsnID*/0, /*Opcode*/GIMT_Encode2(AMDGPU::BUFFER_STORE_FORMAT_D16_X_gfx80_BOTHEN_exact),
        GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/0, // vdata
        GIR_AddSimpleTempRegister, /*InsnID*/0, /*TempRegID*/0,
        GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/1, // rsrc
        GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/0, // soffset
        GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/5, // offset
        GIR_CustomOperandRenderer, /*InsnID*/0, /*OldInsnID*/0, /*OpIdx*/6, /*OperandRenderer*/GIMT_Encode2(GICR_renderExtractCPol), // auxiliary
        GIR_CustomOperandRenderer, /*InsnID*/0, /*OldInsnID*/0, /*OpIdx*/6, /*OperandRenderer*/GIMT_Encode2(GICR_renderExtractSWZ), // auxiliary
        GIR_MergeMemOperands, /*InsnID*/0, /*NumInsns*/1, /*MergeInsnID's*/0,
        GIR_ConstrainSelectedInstOperands, /*InsnID*/0,
        GIR_EraseFromParent, /*InsnID*/0,
        // GIR_Coverage, 4304,
        GIR_Done,
      // Label 6995: @513761
      GIM_Try, /*On fail goto*//*Label 6996*/ GIMT_Encode4(513871), // Rule ID 4324 //
        GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasPackedD16VMem_HasUnrestrictedSOffset),
        // MIs[0] offset
        GIM_CheckIsImm, /*MI*/0, /*Op*/5,
        // MIs[0] auxiliary
        GIM_CheckIsImm, /*MI*/0, /*Op*/6,
        // MIs[0] Operand 7
        GIM_CheckIsImm, /*MI*/0, /*Op*/7,
        GIM_CheckComplexPattern, /*MI*/0, /*Op*/4, /*Renderer*/GIMT_Encode2(0), GIMT_Encode2(GICP_gi_buf_soffset),
        // (SIbuffer_store_format_d16 f16:{ *:[f16] }:$vdata, v4i32:{ *:[v4i32] }:$rsrc, i32:{ *:[i32] }:$vindex, i32:{ *:[i32] }:$voffset, (BUFSOffset:{ *:[i32] } i32:{ *:[i32] }:$soffset), (timm:{ *:[i32] }):$offset, (timm:{ *:[i32] }):$auxiliary, (timm:{ *:[i1] }))  =>  (BUFFER_STORE_FORMAT_D16_X_BOTHEN_exact anonymous_15037:{ *:[f16] }:$vdata, (REG_SEQUENCE:{ *:[i64] } VReg_64:{ *:[i32] }, VGPR_32:{ *:[i32] }:$vindex, sub0:{ *:[i32] }, VGPR_32:{ *:[i32] }:$voffset, sub1:{ *:[i32] }), SReg_128:{ *:[v4i32] }:$rsrc, SCSrc_b32:{ *:[i32] }:$soffset, (timm:{ *:[i32] }):$offset, (extract_cpol:{ *:[i32] } ?:{ *:[i32] }:$auxiliary), (extract_swz:{ *:[i1] } ?:{ *:[i32] }:$auxiliary))
        GIR_MakeTempReg, /*TempRegID*/0, /*TypeID*/GILLT_s64,
        GIR_BuildMI, /*InsnID*/1, /*Opcode*/GIMT_Encode2(TargetOpcode::REG_SEQUENCE),
        GIR_AddTempRegister, /*InsnID*/1, /*TempRegID*/0, /*TempRegFlags*/GIMT_Encode2(RegState::Define),
        GIR_Copy, /*NewInsnID*/1, /*OldInsnID*/0, /*OpIdx*/2, // vindex
        GIR_AddImm8, /*InsnID*/1, /*SubRegIndex*/3,
        GIR_Copy, /*NewInsnID*/1, /*OldInsnID*/0, /*OpIdx*/3, // voffset
        GIR_AddImm8, /*InsnID*/1, /*SubRegIndex*/11,
        GIR_ConstrainOperandRC, /*InsnID*/1, /*Op*/0, GIMT_Encode2(AMDGPU::VReg_64RegClassID),
        GIR_ConstrainOperandRC, /*InsnID*/1, /*Op*/1, GIMT_Encode2(AMDGPU::VGPR_32RegClassID),
        GIR_ConstrainOperandRC, /*InsnID*/1, /*Op*/3, GIMT_Encode2(AMDGPU::VGPR_32RegClassID),
        GIR_BuildMI, /*InsnID*/0, /*Opcode*/GIMT_Encode2(AMDGPU::BUFFER_STORE_FORMAT_D16_X_BOTHEN_exact),
        GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/0, // vdata
        GIR_AddSimpleTempRegister, /*InsnID*/0, /*TempRegID*/0,
        GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/1, // rsrc
        GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/0, // soffset
        GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/5, // offset
        GIR_CustomOperandRenderer, /*InsnID*/0, /*OldInsnID*/0, /*OpIdx*/6, /*OperandRenderer*/GIMT_Encode2(GICR_renderExtractCPol), // auxiliary
        GIR_CustomOperandRenderer, /*InsnID*/0, /*OldInsnID*/0, /*OpIdx*/6, /*OperandRenderer*/GIMT_Encode2(GICR_renderExtractSWZ), // auxiliary
        GIR_MergeMemOperands, /*InsnID*/0, /*NumInsns*/1, /*MergeInsnID's*/0,
        GIR_ConstrainSelectedInstOperands, /*InsnID*/0,
        GIR_EraseFromParent, /*InsnID*/0,
        // GIR_Coverage, 4324,
        GIR_Done,
      // Label 6996: @513871
      GIM_Try, /*On fail goto*//*Label 6997*/ GIMT_Encode4(513981), // Rule ID 4328 //
        GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasPackedD16VMem),
        // MIs[0] offset
        GIM_CheckIsImm, /*MI*/0, /*Op*/5,
        // MIs[0] auxiliary
        GIM_CheckIsImm, /*MI*/0, /*Op*/6,
        // MIs[0] Operand 7
        GIM_CheckIsImm, /*MI*/0, /*Op*/7,
        GIM_CheckComplexPattern, /*MI*/0, /*Op*/4, /*Renderer*/GIMT_Encode2(0), GIMT_Encode2(GICP_gi_buf_soffset),
        // (SIbuffer_store_format_d16 f16:{ *:[f16] }:$vdata, v4i32:{ *:[v4i32] }:$rsrc, i32:{ *:[i32] }:$vindex, i32:{ *:[i32] }:$voffset, (BUFSOffset:{ *:[i32] } i32:{ *:[i32] }:$soffset), (timm:{ *:[i32] }):$offset, (timm:{ *:[i32] }):$auxiliary, (timm:{ *:[i1] }))  =>  (BUFFER_STORE_FORMAT_D16_X_VBUFFER_BOTHEN_exact anonymous_15037:{ *:[f16] }:$vdata, (REG_SEQUENCE:{ *:[i64] } VReg_64:{ *:[i32] }, VGPR_32:{ *:[i32] }:$vindex, sub0:{ *:[i32] }, VGPR_32:{ *:[i32] }:$voffset, sub1:{ *:[i32] }), SReg_128:{ *:[v4i32] }:$rsrc, SCSrc_b32:{ *:[i32] }:$soffset, (timm:{ *:[i32] }):$offset, (extract_cpol:{ *:[i32] } ?:{ *:[i32] }:$auxiliary), (extract_swz:{ *:[i1] } ?:{ *:[i32] }:$auxiliary))
        GIR_MakeTempReg, /*TempRegID*/0, /*TypeID*/GILLT_s64,
        GIR_BuildMI, /*InsnID*/1, /*Opcode*/GIMT_Encode2(TargetOpcode::REG_SEQUENCE),
        GIR_AddTempRegister, /*InsnID*/1, /*TempRegID*/0, /*TempRegFlags*/GIMT_Encode2(RegState::Define),
        GIR_Copy, /*NewInsnID*/1, /*OldInsnID*/0, /*OpIdx*/2, // vindex
        GIR_AddImm8, /*InsnID*/1, /*SubRegIndex*/3,
        GIR_Copy, /*NewInsnID*/1, /*OldInsnID*/0, /*OpIdx*/3, // voffset
        GIR_AddImm8, /*InsnID*/1, /*SubRegIndex*/11,
        GIR_ConstrainOperandRC, /*InsnID*/1, /*Op*/0, GIMT_Encode2(AMDGPU::VReg_64RegClassID),
        GIR_ConstrainOperandRC, /*InsnID*/1, /*Op*/1, GIMT_Encode2(AMDGPU::VGPR_32RegClassID),
        GIR_ConstrainOperandRC, /*InsnID*/1, /*Op*/3, GIMT_Encode2(AMDGPU::VGPR_32RegClassID),
        GIR_BuildMI, /*InsnID*/0, /*Opcode*/GIMT_Encode2(AMDGPU::BUFFER_STORE_FORMAT_D16_X_VBUFFER_BOTHEN_exact),
        GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/0, // vdata
        GIR_AddSimpleTempRegister, /*InsnID*/0, /*TempRegID*/0,
        GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/1, // rsrc
        GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/0, // soffset
        GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/5, // offset
        GIR_CustomOperandRenderer, /*InsnID*/0, /*OldInsnID*/0, /*OpIdx*/6, /*OperandRenderer*/GIMT_Encode2(GICR_renderExtractCPol), // auxiliary
        GIR_CustomOperandRenderer, /*InsnID*/0, /*OldInsnID*/0, /*OpIdx*/6, /*OperandRenderer*/GIMT_Encode2(GICR_renderExtractSWZ), // auxiliary
        GIR_MergeMemOperands, /*InsnID*/0, /*NumInsns*/1, /*MergeInsnID's*/0,
        GIR_ConstrainSelectedInstOperands, /*InsnID*/0,
        GIR_EraseFromParent, /*InsnID*/0,
        // GIR_Coverage, 4328,
        GIR_Done,
      // Label 6997: @513981
      GIM_Try, /*On fail goto*//*Label 6998*/ GIMT_Encode4(514091), // Rule ID 4332 //
        GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasPackedD16VMem_HasUnrestrictedSOffset),
        // MIs[0] offset
        GIM_CheckIsImm, /*MI*/0, /*Op*/5,
        // MIs[0] auxiliary
        GIM_CheckIsImm, /*MI*/0, /*Op*/6,
        // MIs[0] Operand 7
        GIM_CheckIsImm, /*MI*/0, /*Op*/7,
        GIM_CheckComplexPattern, /*MI*/0, /*Op*/4, /*Renderer*/GIMT_Encode2(0), GIMT_Encode2(GICP_gi_buf_soffset),
        // (SIbuffer_store_format_d16 i16:{ *:[i16] }:$vdata, v4i32:{ *:[v4i32] }:$rsrc, i32:{ *:[i32] }:$vindex, i32:{ *:[i32] }:$voffset, (BUFSOffset:{ *:[i32] } i32:{ *:[i32] }:$soffset), (timm:{ *:[i32] }):$offset, (timm:{ *:[i32] }):$auxiliary, (timm:{ *:[i1] }))  =>  (BUFFER_STORE_FORMAT_D16_X_BOTHEN_exact anonymous_15037:{ *:[i16] }:$vdata, (REG_SEQUENCE:{ *:[i64] } VReg_64:{ *:[i32] }, VGPR_32:{ *:[i32] }:$vindex, sub0:{ *:[i32] }, VGPR_32:{ *:[i32] }:$voffset, sub1:{ *:[i32] }), SReg_128:{ *:[v4i32] }:$rsrc, SCSrc_b32:{ *:[i32] }:$soffset, (timm:{ *:[i32] }):$offset, (extract_cpol:{ *:[i32] } ?:{ *:[i32] }:$auxiliary), (extract_swz:{ *:[i1] } ?:{ *:[i32] }:$auxiliary))
        GIR_MakeTempReg, /*TempRegID*/0, /*TypeID*/GILLT_s64,
        GIR_BuildMI, /*InsnID*/1, /*Opcode*/GIMT_Encode2(TargetOpcode::REG_SEQUENCE),
        GIR_AddTempRegister, /*InsnID*/1, /*TempRegID*/0, /*TempRegFlags*/GIMT_Encode2(RegState::Define),
        GIR_Copy, /*NewInsnID*/1, /*OldInsnID*/0, /*OpIdx*/2, // vindex
        GIR_AddImm8, /*InsnID*/1, /*SubRegIndex*/3,
        GIR_Copy, /*NewInsnID*/1, /*OldInsnID*/0, /*OpIdx*/3, // voffset
        GIR_AddImm8, /*InsnID*/1, /*SubRegIndex*/11,
        GIR_ConstrainOperandRC, /*InsnID*/1, /*Op*/0, GIMT_Encode2(AMDGPU::VReg_64RegClassID),
        GIR_ConstrainOperandRC, /*InsnID*/1, /*Op*/1, GIMT_Encode2(AMDGPU::VGPR_32RegClassID),
        GIR_ConstrainOperandRC, /*InsnID*/1, /*Op*/3, GIMT_Encode2(AMDGPU::VGPR_32RegClassID),
        GIR_BuildMI, /*InsnID*/0, /*Opcode*/GIMT_Encode2(AMDGPU::BUFFER_STORE_FORMAT_D16_X_BOTHEN_exact),
        GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/0, // vdata
        GIR_AddSimpleTempRegister, /*InsnID*/0, /*TempRegID*/0,
        GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/1, // rsrc
        GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/0, // soffset
        GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/5, // offset
        GIR_CustomOperandRenderer, /*InsnID*/0, /*OldInsnID*/0, /*OpIdx*/6, /*OperandRenderer*/GIMT_Encode2(GICR_renderExtractCPol), // auxiliary
        GIR_CustomOperandRenderer, /*InsnID*/0, /*OldInsnID*/0, /*OpIdx*/6, /*OperandRenderer*/GIMT_Encode2(GICR_renderExtractSWZ), // auxiliary
        GIR_MergeMemOperands, /*InsnID*/0, /*NumInsns*/1, /*MergeInsnID's*/0,
        GIR_ConstrainSelectedInstOperands, /*InsnID*/0,
        GIR_EraseFromParent, /*InsnID*/0,
        // GIR_Coverage, 4332,
        GIR_Done,
      // Label 6998: @514091
      GIM_Try, /*On fail goto*//*Label 6999*/ GIMT_Encode4(514201), // Rule ID 4336 //
        GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasPackedD16VMem),
        // MIs[0] offset
        GIM_CheckIsImm, /*MI*/0, /*Op*/5,
        // MIs[0] auxiliary
        GIM_CheckIsImm, /*MI*/0, /*Op*/6,
        // MIs[0] Operand 7
        GIM_CheckIsImm, /*MI*/0, /*Op*/7,
        GIM_CheckComplexPattern, /*MI*/0, /*Op*/4, /*Renderer*/GIMT_Encode2(0), GIMT_Encode2(GICP_gi_buf_soffset),
        // (SIbuffer_store_format_d16 i16:{ *:[i16] }:$vdata, v4i32:{ *:[v4i32] }:$rsrc, i32:{ *:[i32] }:$vindex, i32:{ *:[i32] }:$voffset, (BUFSOffset:{ *:[i32] } i32:{ *:[i32] }:$soffset), (timm:{ *:[i32] }):$offset, (timm:{ *:[i32] }):$auxiliary, (timm:{ *:[i1] }))  =>  (BUFFER_STORE_FORMAT_D16_X_VBUFFER_BOTHEN_exact anonymous_15037:{ *:[i16] }:$vdata, (REG_SEQUENCE:{ *:[i64] } VReg_64:{ *:[i32] }, VGPR_32:{ *:[i32] }:$vindex, sub0:{ *:[i32] }, VGPR_32:{ *:[i32] }:$voffset, sub1:{ *:[i32] }), SReg_128:{ *:[v4i32] }:$rsrc, SCSrc_b32:{ *:[i32] }:$soffset, (timm:{ *:[i32] }):$offset, (extract_cpol:{ *:[i32] } ?:{ *:[i32] }:$auxiliary), (extract_swz:{ *:[i1] } ?:{ *:[i32] }:$auxiliary))
        GIR_MakeTempReg, /*TempRegID*/0, /*TypeID*/GILLT_s64,
        GIR_BuildMI, /*InsnID*/1, /*Opcode*/GIMT_Encode2(TargetOpcode::REG_SEQUENCE),
        GIR_AddTempRegister, /*InsnID*/1, /*TempRegID*/0, /*TempRegFlags*/GIMT_Encode2(RegState::Define),
        GIR_Copy, /*NewInsnID*/1, /*OldInsnID*/0, /*OpIdx*/2, // vindex
        GIR_AddImm8, /*InsnID*/1, /*SubRegIndex*/3,
        GIR_Copy, /*NewInsnID*/1, /*OldInsnID*/0, /*OpIdx*/3, // voffset
        GIR_AddImm8, /*InsnID*/1, /*SubRegIndex*/11,
        GIR_ConstrainOperandRC, /*InsnID*/1, /*Op*/0, GIMT_Encode2(AMDGPU::VReg_64RegClassID),
        GIR_ConstrainOperandRC, /*InsnID*/1, /*Op*/1, GIMT_Encode2(AMDGPU::VGPR_32RegClassID),
        GIR_ConstrainOperandRC, /*InsnID*/1, /*Op*/3, GIMT_Encode2(AMDGPU::VGPR_32RegClassID),
        GIR_BuildMI, /*InsnID*/0, /*Opcode*/GIMT_Encode2(AMDGPU::BUFFER_STORE_FORMAT_D16_X_VBUFFER_BOTHEN_exact),
        GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/0, // vdata
        GIR_AddSimpleTempRegister, /*InsnID*/0, /*TempRegID*/0,
        GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/1, // rsrc
        GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/0, // soffset
        GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/5, // offset
        GIR_CustomOperandRenderer, /*InsnID*/0, /*OldInsnID*/0, /*OpIdx*/6, /*OperandRenderer*/GIMT_Encode2(GICR_renderExtractCPol), // auxiliary
        GIR_CustomOperandRenderer, /*InsnID*/0, /*OldInsnID*/0, /*OpIdx*/6, /*OperandRenderer*/GIMT_Encode2(GICR_renderExtractSWZ), // auxiliary
        GIR_MergeMemOperands, /*InsnID*/0, /*NumInsns*/1, /*MergeInsnID's*/0,
        GIR_ConstrainSelectedInstOperands, /*InsnID*/0,
        GIR_EraseFromParent, /*InsnID*/0,
        // GIR_Coverage, 4336,
        GIR_Done,
      // Label 6999: @514201
      GIM_Reject,
    // Label 6975: @514202
    GIM_Reject,
    // Label 6968: @514203
    GIM_Try, /*On fail goto*//*Label 7000*/ GIMT_Encode4(515269),
      GIM_CheckType, /*MI*/0, /*Op*/1, /*Type*/GILLT_v4s32,
      GIM_CheckType, /*MI*/0, /*Op*/2, /*Type*/GILLT_s32,
      GIM_CheckType, /*MI*/0, /*Op*/3, /*Type*/GILLT_s32,
      GIM_CheckType, /*MI*/0, /*Op*/4, /*Type*/GILLT_s32,
      GIM_Try, /*On fail goto*//*Label 7001*/ GIMT_Encode4(514306), // Rule ID 4305 //
        GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasUnpackedD16VMem),
        GIM_CheckConstantInt8, /*MI*/0, /*Op*/2, 0,
        GIM_CheckConstantInt8, /*MI*/0, /*Op*/3, 0,
        // MIs[0] offset
        GIM_CheckIsImm, /*MI*/0, /*Op*/5,
        // MIs[0] auxiliary
        GIM_CheckIsImm, /*MI*/0, /*Op*/6,
        // MIs[0] Operand 7
        GIM_CheckLiteralInt, /*MI*/0, /*Op*/7, GIMT_Encode8(0),
        GIM_CheckComplexPattern, /*MI*/0, /*Op*/4, /*Renderer*/GIMT_Encode2(0), GIMT_Encode2(GICP_gi_buf_soffset),
        // (SIbuffer_store_format_d16 i32:{ *:[i32] }:$vdata, v4i32:{ *:[v4i32] }:$rsrc, 0:{ *:[i32] }, 0:{ *:[i32] }, (BUFSOffset:{ *:[i32] } i32:{ *:[i32] }:$soffset), (timm:{ *:[i32] }):$offset, (timm:{ *:[i32] }):$auxiliary, 0:{ *:[i1] })  =>  (BUFFER_STORE_FORMAT_D16_X_gfx80_OFFSET_exact anonymous_15037:{ *:[i32] }:$vdata, SReg_128:{ *:[v4i32] }:$rsrc, SCSrc_b32:{ *:[i32] }:$soffset, (timm:{ *:[i32] }):$offset, (extract_cpol:{ *:[i32] } ?:{ *:[i32] }:$auxiliary), (extract_swz:{ *:[i1] } ?:{ *:[i32] }:$auxiliary))
        GIR_BuildMI, /*InsnID*/0, /*Opcode*/GIMT_Encode2(AMDGPU::BUFFER_STORE_FORMAT_D16_X_gfx80_OFFSET_exact),
        GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/0, // vdata
        GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/1, // rsrc
        GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/0, // soffset
        GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/5, // offset
        GIR_CustomOperandRenderer, /*InsnID*/0, /*OldInsnID*/0, /*OpIdx*/6, /*OperandRenderer*/GIMT_Encode2(GICR_renderExtractCPol), // auxiliary
        GIR_CustomOperandRenderer, /*InsnID*/0, /*OldInsnID*/0, /*OpIdx*/6, /*OperandRenderer*/GIMT_Encode2(GICR_renderExtractSWZ), // auxiliary
        GIR_MergeMemOperands, /*InsnID*/0, /*NumInsns*/1, /*MergeInsnID's*/0,
        GIR_ConstrainSelectedInstOperands, /*InsnID*/0,
        GIR_EraseFromParent, /*InsnID*/0,
        // GIR_Coverage, 4305,
        GIR_Done,
      // Label 7001: @514306
      GIM_Try, /*On fail goto*//*Label 7002*/ GIMT_Encode4(514388), // Rule ID 4337 //
        GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasPackedD16VMem_HasUnrestrictedSOffset),
        GIM_CheckConstantInt8, /*MI*/0, /*Op*/2, 0,
        GIM_CheckConstantInt8, /*MI*/0, /*Op*/3, 0,
        // MIs[0] offset
        GIM_CheckIsImm, /*MI*/0, /*Op*/5,
        // MIs[0] auxiliary
        GIM_CheckIsImm, /*MI*/0, /*Op*/6,
        // MIs[0] Operand 7
        GIM_CheckLiteralInt, /*MI*/0, /*Op*/7, GIMT_Encode8(0),
        GIM_CheckComplexPattern, /*MI*/0, /*Op*/4, /*Renderer*/GIMT_Encode2(0), GIMT_Encode2(GICP_gi_buf_soffset),
        // (SIbuffer_store_format_d16 i32:{ *:[i32] }:$vdata, v4i32:{ *:[v4i32] }:$rsrc, 0:{ *:[i32] }, 0:{ *:[i32] }, (BUFSOffset:{ *:[i32] } i32:{ *:[i32] }:$soffset), (timm:{ *:[i32] }):$offset, (timm:{ *:[i32] }):$auxiliary, 0:{ *:[i1] })  =>  (BUFFER_STORE_FORMAT_D16_X_OFFSET_exact anonymous_15037:{ *:[i32] }:$vdata, SReg_128:{ *:[v4i32] }:$rsrc, SCSrc_b32:{ *:[i32] }:$soffset, (timm:{ *:[i32] }):$offset, (extract_cpol:{ *:[i32] } ?:{ *:[i32] }:$auxiliary), (extract_swz:{ *:[i1] } ?:{ *:[i32] }:$auxiliary))
        GIR_BuildMI, /*InsnID*/0, /*Opcode*/GIMT_Encode2(AMDGPU::BUFFER_STORE_FORMAT_D16_X_OFFSET_exact),
        GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/0, // vdata
        GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/1, // rsrc
        GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/0, // soffset
        GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/5, // offset
        GIR_CustomOperandRenderer, /*InsnID*/0, /*OldInsnID*/0, /*OpIdx*/6, /*OperandRenderer*/GIMT_Encode2(GICR_renderExtractCPol), // auxiliary
        GIR_CustomOperandRenderer, /*InsnID*/0, /*OldInsnID*/0, /*OpIdx*/6, /*OperandRenderer*/GIMT_Encode2(GICR_renderExtractSWZ), // auxiliary
        GIR_MergeMemOperands, /*InsnID*/0, /*NumInsns*/1, /*MergeInsnID's*/0,
        GIR_ConstrainSelectedInstOperands, /*InsnID*/0,
        GIR_EraseFromParent, /*InsnID*/0,
        // GIR_Coverage, 4337,
        GIR_Done,
      // Label 7002: @514388
      GIM_Try, /*On fail goto*//*Label 7003*/ GIMT_Encode4(514470), // Rule ID 4341 //
        GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasPackedD16VMem),
        GIM_CheckConstantInt8, /*MI*/0, /*Op*/2, 0,
        GIM_CheckConstantInt8, /*MI*/0, /*Op*/3, 0,
        // MIs[0] offset
        GIM_CheckIsImm, /*MI*/0, /*Op*/5,
        // MIs[0] auxiliary
        GIM_CheckIsImm, /*MI*/0, /*Op*/6,
        // MIs[0] Operand 7
        GIM_CheckLiteralInt, /*MI*/0, /*Op*/7, GIMT_Encode8(0),
        GIM_CheckComplexPattern, /*MI*/0, /*Op*/4, /*Renderer*/GIMT_Encode2(0), GIMT_Encode2(GICP_gi_buf_soffset),
        // (SIbuffer_store_format_d16 i32:{ *:[i32] }:$vdata, v4i32:{ *:[v4i32] }:$rsrc, 0:{ *:[i32] }, 0:{ *:[i32] }, (BUFSOffset:{ *:[i32] } i32:{ *:[i32] }:$soffset), (timm:{ *:[i32] }):$offset, (timm:{ *:[i32] }):$auxiliary, 0:{ *:[i1] })  =>  (BUFFER_STORE_FORMAT_D16_X_VBUFFER_OFFSET_exact anonymous_15037:{ *:[i32] }:$vdata, SReg_128:{ *:[v4i32] }:$rsrc, SCSrc_b32:{ *:[i32] }:$soffset, (timm:{ *:[i32] }):$offset, (extract_cpol:{ *:[i32] } ?:{ *:[i32] }:$auxiliary), (extract_swz:{ *:[i1] } ?:{ *:[i32] }:$auxiliary))
        GIR_BuildMI, /*InsnID*/0, /*Opcode*/GIMT_Encode2(AMDGPU::BUFFER_STORE_FORMAT_D16_X_VBUFFER_OFFSET_exact),
        GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/0, // vdata
        GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/1, // rsrc
        GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/0, // soffset
        GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/5, // offset
        GIR_CustomOperandRenderer, /*InsnID*/0, /*OldInsnID*/0, /*OpIdx*/6, /*OperandRenderer*/GIMT_Encode2(GICR_renderExtractCPol), // auxiliary
        GIR_CustomOperandRenderer, /*InsnID*/0, /*OldInsnID*/0, /*OpIdx*/6, /*OperandRenderer*/GIMT_Encode2(GICR_renderExtractSWZ), // auxiliary
        GIR_MergeMemOperands, /*InsnID*/0, /*NumInsns*/1, /*MergeInsnID's*/0,
        GIR_ConstrainSelectedInstOperands, /*InsnID*/0,
        GIR_EraseFromParent, /*InsnID*/0,
        // GIR_Coverage, 4341,
        GIR_Done,
      // Label 7003: @514470
      GIM_Try, /*On fail goto*//*Label 7004*/ GIMT_Encode4(514552), // Rule ID 4306 //
        GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasUnpackedD16VMem),
        GIM_CheckConstantInt8, /*MI*/0, /*Op*/2, 0,
        // MIs[0] offset
        GIM_CheckIsImm, /*MI*/0, /*Op*/5,
        // MIs[0] auxiliary
        GIM_CheckIsImm, /*MI*/0, /*Op*/6,
        // MIs[0] Operand 7
        GIM_CheckLiteralInt, /*MI*/0, /*Op*/7, GIMT_Encode8(0),
        GIM_CheckComplexPattern, /*MI*/0, /*Op*/4, /*Renderer*/GIMT_Encode2(0), GIMT_Encode2(GICP_gi_buf_soffset),
        // (SIbuffer_store_format_d16 i32:{ *:[i32] }:$vdata, v4i32:{ *:[v4i32] }:$rsrc, 0:{ *:[i32] }, i32:{ *:[i32] }:$voffset, (BUFSOffset:{ *:[i32] } i32:{ *:[i32] }:$soffset), (timm:{ *:[i32] }):$offset, (timm:{ *:[i32] }):$auxiliary, 0:{ *:[i1] })  =>  (BUFFER_STORE_FORMAT_D16_X_gfx80_OFFEN_exact anonymous_15037:{ *:[i32] }:$vdata, VGPR_32:{ *:[i32] }:$voffset, SReg_128:{ *:[v4i32] }:$rsrc, SCSrc_b32:{ *:[i32] }:$soffset, (timm:{ *:[i32] }):$offset, (extract_cpol:{ *:[i32] } ?:{ *:[i32] }:$auxiliary), (extract_swz:{ *:[i1] } ?:{ *:[i32] }:$auxiliary))
        GIR_BuildMI, /*InsnID*/0, /*Opcode*/GIMT_Encode2(AMDGPU::BUFFER_STORE_FORMAT_D16_X_gfx80_OFFEN_exact),
        GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/0, // vdata
        GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/3, // voffset
        GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/1, // rsrc
        GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/0, // soffset
        GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/5, // offset
        GIR_CustomOperandRenderer, /*InsnID*/0, /*OldInsnID*/0, /*OpIdx*/6, /*OperandRenderer*/GIMT_Encode2(GICR_renderExtractCPol), // auxiliary
        GIR_CustomOperandRenderer, /*InsnID*/0, /*OldInsnID*/0, /*OpIdx*/6, /*OperandRenderer*/GIMT_Encode2(GICR_renderExtractSWZ), // auxiliary
        GIR_MergeMemOperands, /*InsnID*/0, /*NumInsns*/1, /*MergeInsnID's*/0,
        GIR_ConstrainSelectedInstOperands, /*InsnID*/0,
        GIR_EraseFromParent, /*InsnID*/0,
        // GIR_Coverage, 4306,
        GIR_Done,
      // Label 7004: @514552
      GIM_Try, /*On fail goto*//*Label 7005*/ GIMT_Encode4(514634), // Rule ID 4338 //
        GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasPackedD16VMem_HasUnrestrictedSOffset),
        GIM_CheckConstantInt8, /*MI*/0, /*Op*/2, 0,
        // MIs[0] offset
        GIM_CheckIsImm, /*MI*/0, /*Op*/5,
        // MIs[0] auxiliary
        GIM_CheckIsImm, /*MI*/0, /*Op*/6,
        // MIs[0] Operand 7
        GIM_CheckLiteralInt, /*MI*/0, /*Op*/7, GIMT_Encode8(0),
        GIM_CheckComplexPattern, /*MI*/0, /*Op*/4, /*Renderer*/GIMT_Encode2(0), GIMT_Encode2(GICP_gi_buf_soffset),
        // (SIbuffer_store_format_d16 i32:{ *:[i32] }:$vdata, v4i32:{ *:[v4i32] }:$rsrc, 0:{ *:[i32] }, i32:{ *:[i32] }:$voffset, (BUFSOffset:{ *:[i32] } i32:{ *:[i32] }:$soffset), (timm:{ *:[i32] }):$offset, (timm:{ *:[i32] }):$auxiliary, 0:{ *:[i1] })  =>  (BUFFER_STORE_FORMAT_D16_X_OFFEN_exact anonymous_15037:{ *:[i32] }:$vdata, VGPR_32:{ *:[i32] }:$voffset, SReg_128:{ *:[v4i32] }:$rsrc, SCSrc_b32:{ *:[i32] }:$soffset, (timm:{ *:[i32] }):$offset, (extract_cpol:{ *:[i32] } ?:{ *:[i32] }:$auxiliary), (extract_swz:{ *:[i1] } ?:{ *:[i32] }:$auxiliary))
        GIR_BuildMI, /*InsnID*/0, /*Opcode*/GIMT_Encode2(AMDGPU::BUFFER_STORE_FORMAT_D16_X_OFFEN_exact),
        GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/0, // vdata
        GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/3, // voffset
        GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/1, // rsrc
        GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/0, // soffset
        GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/5, // offset
        GIR_CustomOperandRenderer, /*InsnID*/0, /*OldInsnID*/0, /*OpIdx*/6, /*OperandRenderer*/GIMT_Encode2(GICR_renderExtractCPol), // auxiliary
        GIR_CustomOperandRenderer, /*InsnID*/0, /*OldInsnID*/0, /*OpIdx*/6, /*OperandRenderer*/GIMT_Encode2(GICR_renderExtractSWZ), // auxiliary
        GIR_MergeMemOperands, /*InsnID*/0, /*NumInsns*/1, /*MergeInsnID's*/0,
        GIR_ConstrainSelectedInstOperands, /*InsnID*/0,
        GIR_EraseFromParent, /*InsnID*/0,
        // GIR_Coverage, 4338,
        GIR_Done,
      // Label 7005: @514634
      GIM_Try, /*On fail goto*//*Label 7006*/ GIMT_Encode4(514716), // Rule ID 4342 //
        GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasPackedD16VMem),
        GIM_CheckConstantInt8, /*MI*/0, /*Op*/2, 0,
        // MIs[0] offset
        GIM_CheckIsImm, /*MI*/0, /*Op*/5,
        // MIs[0] auxiliary
        GIM_CheckIsImm, /*MI*/0, /*Op*/6,
        // MIs[0] Operand 7
        GIM_CheckLiteralInt, /*MI*/0, /*Op*/7, GIMT_Encode8(0),
        GIM_CheckComplexPattern, /*MI*/0, /*Op*/4, /*Renderer*/GIMT_Encode2(0), GIMT_Encode2(GICP_gi_buf_soffset),
        // (SIbuffer_store_format_d16 i32:{ *:[i32] }:$vdata, v4i32:{ *:[v4i32] }:$rsrc, 0:{ *:[i32] }, i32:{ *:[i32] }:$voffset, (BUFSOffset:{ *:[i32] } i32:{ *:[i32] }:$soffset), (timm:{ *:[i32] }):$offset, (timm:{ *:[i32] }):$auxiliary, 0:{ *:[i1] })  =>  (BUFFER_STORE_FORMAT_D16_X_VBUFFER_OFFEN_exact anonymous_15037:{ *:[i32] }:$vdata, VGPR_32:{ *:[i32] }:$voffset, SReg_128:{ *:[v4i32] }:$rsrc, SCSrc_b32:{ *:[i32] }:$soffset, (timm:{ *:[i32] }):$offset, (extract_cpol:{ *:[i32] } ?:{ *:[i32] }:$auxiliary), (extract_swz:{ *:[i1] } ?:{ *:[i32] }:$auxiliary))
        GIR_BuildMI, /*InsnID*/0, /*Opcode*/GIMT_Encode2(AMDGPU::BUFFER_STORE_FORMAT_D16_X_VBUFFER_OFFEN_exact),
        GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/0, // vdata
        GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/3, // voffset
        GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/1, // rsrc
        GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/0, // soffset
        GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/5, // offset
        GIR_CustomOperandRenderer, /*InsnID*/0, /*OldInsnID*/0, /*OpIdx*/6, /*OperandRenderer*/GIMT_Encode2(GICR_renderExtractCPol), // auxiliary
        GIR_CustomOperandRenderer, /*InsnID*/0, /*OldInsnID*/0, /*OpIdx*/6, /*OperandRenderer*/GIMT_Encode2(GICR_renderExtractSWZ), // auxiliary
        GIR_MergeMemOperands, /*InsnID*/0, /*NumInsns*/1, /*MergeInsnID's*/0,
        GIR_ConstrainSelectedInstOperands, /*InsnID*/0,
        GIR_EraseFromParent, /*InsnID*/0,
        // GIR_Coverage, 4342,
        GIR_Done,
      // Label 7006: @514716
      GIM_Try, /*On fail goto*//*Label 7007*/ GIMT_Encode4(514790), // Rule ID 4307 //
        GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasUnpackedD16VMem),
        GIM_CheckConstantInt8, /*MI*/0, /*Op*/3, 0,
        // MIs[0] offset
        GIM_CheckIsImm, /*MI*/0, /*Op*/5,
        // MIs[0] auxiliary
        GIM_CheckIsImm, /*MI*/0, /*Op*/6,
        // MIs[0] Operand 7
        GIM_CheckIsImm, /*MI*/0, /*Op*/7,
        GIM_CheckComplexPattern, /*MI*/0, /*Op*/4, /*Renderer*/GIMT_Encode2(0), GIMT_Encode2(GICP_gi_buf_soffset),
        // (SIbuffer_store_format_d16 i32:{ *:[i32] }:$vdata, v4i32:{ *:[v4i32] }:$rsrc, i32:{ *:[i32] }:$vindex, 0:{ *:[i32] }, (BUFSOffset:{ *:[i32] } i32:{ *:[i32] }:$soffset), (timm:{ *:[i32] }):$offset, (timm:{ *:[i32] }):$auxiliary, (timm:{ *:[i1] }))  =>  (BUFFER_STORE_FORMAT_D16_X_gfx80_IDXEN_exact anonymous_15037:{ *:[i32] }:$vdata, VGPR_32:{ *:[i32] }:$vindex, SReg_128:{ *:[v4i32] }:$rsrc, SCSrc_b32:{ *:[i32] }:$soffset, (timm:{ *:[i32] }):$offset, (extract_cpol:{ *:[i32] } ?:{ *:[i32] }:$auxiliary), (extract_swz:{ *:[i1] } ?:{ *:[i32] }:$auxiliary))
        GIR_BuildMI, /*InsnID*/0, /*Opcode*/GIMT_Encode2(AMDGPU::BUFFER_STORE_FORMAT_D16_X_gfx80_IDXEN_exact),
        GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/0, // vdata
        GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/2, // vindex
        GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/1, // rsrc
        GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/0, // soffset
        GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/5, // offset
        GIR_CustomOperandRenderer, /*InsnID*/0, /*OldInsnID*/0, /*OpIdx*/6, /*OperandRenderer*/GIMT_Encode2(GICR_renderExtractCPol), // auxiliary
        GIR_CustomOperandRenderer, /*InsnID*/0, /*OldInsnID*/0, /*OpIdx*/6, /*OperandRenderer*/GIMT_Encode2(GICR_renderExtractSWZ), // auxiliary
        GIR_MergeMemOperands, /*InsnID*/0, /*NumInsns*/1, /*MergeInsnID's*/0,
        GIR_ConstrainSelectedInstOperands, /*InsnID*/0,
        GIR_EraseFromParent, /*InsnID*/0,
        // GIR_Coverage, 4307,
        GIR_Done,
      // Label 7007: @514790
      GIM_Try, /*On fail goto*//*Label 7008*/ GIMT_Encode4(514864), // Rule ID 4339 //
        GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasPackedD16VMem_HasUnrestrictedSOffset),
        GIM_CheckConstantInt8, /*MI*/0, /*Op*/3, 0,
        // MIs[0] offset
        GIM_CheckIsImm, /*MI*/0, /*Op*/5,
        // MIs[0] auxiliary
        GIM_CheckIsImm, /*MI*/0, /*Op*/6,
        // MIs[0] Operand 7
        GIM_CheckIsImm, /*MI*/0, /*Op*/7,
        GIM_CheckComplexPattern, /*MI*/0, /*Op*/4, /*Renderer*/GIMT_Encode2(0), GIMT_Encode2(GICP_gi_buf_soffset),
        // (SIbuffer_store_format_d16 i32:{ *:[i32] }:$vdata, v4i32:{ *:[v4i32] }:$rsrc, i32:{ *:[i32] }:$vindex, 0:{ *:[i32] }, (BUFSOffset:{ *:[i32] } i32:{ *:[i32] }:$soffset), (timm:{ *:[i32] }):$offset, (timm:{ *:[i32] }):$auxiliary, (timm:{ *:[i1] }))  =>  (BUFFER_STORE_FORMAT_D16_X_IDXEN_exact anonymous_15037:{ *:[i32] }:$vdata, VGPR_32:{ *:[i32] }:$vindex, SReg_128:{ *:[v4i32] }:$rsrc, SCSrc_b32:{ *:[i32] }:$soffset, (timm:{ *:[i32] }):$offset, (extract_cpol:{ *:[i32] } ?:{ *:[i32] }:$auxiliary), (extract_swz:{ *:[i1] } ?:{ *:[i32] }:$auxiliary))
        GIR_BuildMI, /*InsnID*/0, /*Opcode*/GIMT_Encode2(AMDGPU::BUFFER_STORE_FORMAT_D16_X_IDXEN_exact),
        GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/0, // vdata
        GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/2, // vindex
        GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/1, // rsrc
        GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/0, // soffset
        GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/5, // offset
        GIR_CustomOperandRenderer, /*InsnID*/0, /*OldInsnID*/0, /*OpIdx*/6, /*OperandRenderer*/GIMT_Encode2(GICR_renderExtractCPol), // auxiliary
        GIR_CustomOperandRenderer, /*InsnID*/0, /*OldInsnID*/0, /*OpIdx*/6, /*OperandRenderer*/GIMT_Encode2(GICR_renderExtractSWZ), // auxiliary
        GIR_MergeMemOperands, /*InsnID*/0, /*NumInsns*/1, /*MergeInsnID's*/0,
        GIR_ConstrainSelectedInstOperands, /*InsnID*/0,
        GIR_EraseFromParent, /*InsnID*/0,
        // GIR_Coverage, 4339,
        GIR_Done,
      // Label 7008: @514864
      GIM_Try, /*On fail goto*//*Label 7009*/ GIMT_Encode4(514938), // Rule ID 4343 //
        GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasPackedD16VMem),
        GIM_CheckConstantInt8, /*MI*/0, /*Op*/3, 0,
        // MIs[0] offset
        GIM_CheckIsImm, /*MI*/0, /*Op*/5,
        // MIs[0] auxiliary
        GIM_CheckIsImm, /*MI*/0, /*Op*/6,
        // MIs[0] Operand 7
        GIM_CheckIsImm, /*MI*/0, /*Op*/7,
        GIM_CheckComplexPattern, /*MI*/0, /*Op*/4, /*Renderer*/GIMT_Encode2(0), GIMT_Encode2(GICP_gi_buf_soffset),
        // (SIbuffer_store_format_d16 i32:{ *:[i32] }:$vdata, v4i32:{ *:[v4i32] }:$rsrc, i32:{ *:[i32] }:$vindex, 0:{ *:[i32] }, (BUFSOffset:{ *:[i32] } i32:{ *:[i32] }:$soffset), (timm:{ *:[i32] }):$offset, (timm:{ *:[i32] }):$auxiliary, (timm:{ *:[i1] }))  =>  (BUFFER_STORE_FORMAT_D16_X_VBUFFER_IDXEN_exact anonymous_15037:{ *:[i32] }:$vdata, VGPR_32:{ *:[i32] }:$vindex, SReg_128:{ *:[v4i32] }:$rsrc, SCSrc_b32:{ *:[i32] }:$soffset, (timm:{ *:[i32] }):$offset, (extract_cpol:{ *:[i32] } ?:{ *:[i32] }:$auxiliary), (extract_swz:{ *:[i1] } ?:{ *:[i32] }:$auxiliary))
        GIR_BuildMI, /*InsnID*/0, /*Opcode*/GIMT_Encode2(AMDGPU::BUFFER_STORE_FORMAT_D16_X_VBUFFER_IDXEN_exact),
        GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/0, // vdata
        GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/2, // vindex
        GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/1, // rsrc
        GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/0, // soffset
        GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/5, // offset
        GIR_CustomOperandRenderer, /*InsnID*/0, /*OldInsnID*/0, /*OpIdx*/6, /*OperandRenderer*/GIMT_Encode2(GICR_renderExtractCPol), // auxiliary
        GIR_CustomOperandRenderer, /*InsnID*/0, /*OldInsnID*/0, /*OpIdx*/6, /*OperandRenderer*/GIMT_Encode2(GICR_renderExtractSWZ), // auxiliary
        GIR_MergeMemOperands, /*InsnID*/0, /*NumInsns*/1, /*MergeInsnID's*/0,
        GIR_ConstrainSelectedInstOperands, /*InsnID*/0,
        GIR_EraseFromParent, /*InsnID*/0,
        // GIR_Coverage, 4343,
        GIR_Done,
      // Label 7009: @514938
      GIM_Try, /*On fail goto*//*Label 7010*/ GIMT_Encode4(515048), // Rule ID 4308 //
        GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasUnpackedD16VMem),
        // MIs[0] offset
        GIM_CheckIsImm, /*MI*/0, /*Op*/5,
        // MIs[0] auxiliary
        GIM_CheckIsImm, /*MI*/0, /*Op*/6,
        // MIs[0] Operand 7
        GIM_CheckIsImm, /*MI*/0, /*Op*/7,
        GIM_CheckComplexPattern, /*MI*/0, /*Op*/4, /*Renderer*/GIMT_Encode2(0), GIMT_Encode2(GICP_gi_buf_soffset),
        // (SIbuffer_store_format_d16 i32:{ *:[i32] }:$vdata, v4i32:{ *:[v4i32] }:$rsrc, i32:{ *:[i32] }:$vindex, i32:{ *:[i32] }:$voffset, (BUFSOffset:{ *:[i32] } i32:{ *:[i32] }:$soffset), (timm:{ *:[i32] }):$offset, (timm:{ *:[i32] }):$auxiliary, (timm:{ *:[i1] }))  =>  (BUFFER_STORE_FORMAT_D16_X_gfx80_BOTHEN_exact anonymous_15037:{ *:[i32] }:$vdata, (REG_SEQUENCE:{ *:[i64] } VReg_64:{ *:[i32] }, VGPR_32:{ *:[i32] }:$vindex, sub0:{ *:[i32] }, VGPR_32:{ *:[i32] }:$voffset, sub1:{ *:[i32] }), SReg_128:{ *:[v4i32] }:$rsrc, SCSrc_b32:{ *:[i32] }:$soffset, (timm:{ *:[i32] }):$offset, (extract_cpol:{ *:[i32] } ?:{ *:[i32] }:$auxiliary), (extract_swz:{ *:[i1] } ?:{ *:[i32] }:$auxiliary))
        GIR_MakeTempReg, /*TempRegID*/0, /*TypeID*/GILLT_s64,
        GIR_BuildMI, /*InsnID*/1, /*Opcode*/GIMT_Encode2(TargetOpcode::REG_SEQUENCE),
        GIR_AddTempRegister, /*InsnID*/1, /*TempRegID*/0, /*TempRegFlags*/GIMT_Encode2(RegState::Define),
        GIR_Copy, /*NewInsnID*/1, /*OldInsnID*/0, /*OpIdx*/2, // vindex
        GIR_AddImm8, /*InsnID*/1, /*SubRegIndex*/3,
        GIR_Copy, /*NewInsnID*/1, /*OldInsnID*/0, /*OpIdx*/3, // voffset
        GIR_AddImm8, /*InsnID*/1, /*SubRegIndex*/11,
        GIR_ConstrainOperandRC, /*InsnID*/1, /*Op*/0, GIMT_Encode2(AMDGPU::VReg_64RegClassID),
        GIR_ConstrainOperandRC, /*InsnID*/1, /*Op*/1, GIMT_Encode2(AMDGPU::VGPR_32RegClassID),
        GIR_ConstrainOperandRC, /*InsnID*/1, /*Op*/3, GIMT_Encode2(AMDGPU::VGPR_32RegClassID),
        GIR_BuildMI, /*InsnID*/0, /*Opcode*/GIMT_Encode2(AMDGPU::BUFFER_STORE_FORMAT_D16_X_gfx80_BOTHEN_exact),
        GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/0, // vdata
        GIR_AddSimpleTempRegister, /*InsnID*/0, /*TempRegID*/0,
        GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/1, // rsrc
        GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/0, // soffset
        GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/5, // offset
        GIR_CustomOperandRenderer, /*InsnID*/0, /*OldInsnID*/0, /*OpIdx*/6, /*OperandRenderer*/GIMT_Encode2(GICR_renderExtractCPol), // auxiliary
        GIR_CustomOperandRenderer, /*InsnID*/0, /*OldInsnID*/0, /*OpIdx*/6, /*OperandRenderer*/GIMT_Encode2(GICR_renderExtractSWZ), // auxiliary
        GIR_MergeMemOperands, /*InsnID*/0, /*NumInsns*/1, /*MergeInsnID's*/0,
        GIR_ConstrainSelectedInstOperands, /*InsnID*/0,
        GIR_EraseFromParent, /*InsnID*/0,
        // GIR_Coverage, 4308,
        GIR_Done,
      // Label 7010: @515048
      GIM_Try, /*On fail goto*//*Label 7011*/ GIMT_Encode4(515158), // Rule ID 4340 //
        GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasPackedD16VMem_HasUnrestrictedSOffset),
        // MIs[0] offset
        GIM_CheckIsImm, /*MI*/0, /*Op*/5,
        // MIs[0] auxiliary
        GIM_CheckIsImm, /*MI*/0, /*Op*/6,
        // MIs[0] Operand 7
        GIM_CheckIsImm, /*MI*/0, /*Op*/7,
        GIM_CheckComplexPattern, /*MI*/0, /*Op*/4, /*Renderer*/GIMT_Encode2(0), GIMT_Encode2(GICP_gi_buf_soffset),
        // (SIbuffer_store_format_d16 i32:{ *:[i32] }:$vdata, v4i32:{ *:[v4i32] }:$rsrc, i32:{ *:[i32] }:$vindex, i32:{ *:[i32] }:$voffset, (BUFSOffset:{ *:[i32] } i32:{ *:[i32] }:$soffset), (timm:{ *:[i32] }):$offset, (timm:{ *:[i32] }):$auxiliary, (timm:{ *:[i1] }))  =>  (BUFFER_STORE_FORMAT_D16_X_BOTHEN_exact anonymous_15037:{ *:[i32] }:$vdata, (REG_SEQUENCE:{ *:[i64] } VReg_64:{ *:[i32] }, VGPR_32:{ *:[i32] }:$vindex, sub0:{ *:[i32] }, VGPR_32:{ *:[i32] }:$voffset, sub1:{ *:[i32] }), SReg_128:{ *:[v4i32] }:$rsrc, SCSrc_b32:{ *:[i32] }:$soffset, (timm:{ *:[i32] }):$offset, (extract_cpol:{ *:[i32] } ?:{ *:[i32] }:$auxiliary), (extract_swz:{ *:[i1] } ?:{ *:[i32] }:$auxiliary))
        GIR_MakeTempReg, /*TempRegID*/0, /*TypeID*/GILLT_s64,
        GIR_BuildMI, /*InsnID*/1, /*Opcode*/GIMT_Encode2(TargetOpcode::REG_SEQUENCE),
        GIR_AddTempRegister, /*InsnID*/1, /*TempRegID*/0, /*TempRegFlags*/GIMT_Encode2(RegState::Define),
        GIR_Copy, /*NewInsnID*/1, /*OldInsnID*/0, /*OpIdx*/2, // vindex
        GIR_AddImm8, /*InsnID*/1, /*SubRegIndex*/3,
        GIR_Copy, /*NewInsnID*/1, /*OldInsnID*/0, /*OpIdx*/3, // voffset
        GIR_AddImm8, /*InsnID*/1, /*SubRegIndex*/11,
        GIR_ConstrainOperandRC, /*InsnID*/1, /*Op*/0, GIMT_Encode2(AMDGPU::VReg_64RegClassID),
        GIR_ConstrainOperandRC, /*InsnID*/1, /*Op*/1, GIMT_Encode2(AMDGPU::VGPR_32RegClassID),
        GIR_ConstrainOperandRC, /*InsnID*/1, /*Op*/3, GIMT_Encode2(AMDGPU::VGPR_32RegClassID),
        GIR_BuildMI, /*InsnID*/0, /*Opcode*/GIMT_Encode2(AMDGPU::BUFFER_STORE_FORMAT_D16_X_BOTHEN_exact),
        GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/0, // vdata
        GIR_AddSimpleTempRegister, /*InsnID*/0, /*TempRegID*/0,
        GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/1, // rsrc
        GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/0, // soffset
        GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/5, // offset
        GIR_CustomOperandRenderer, /*InsnID*/0, /*OldInsnID*/0, /*OpIdx*/6, /*OperandRenderer*/GIMT_Encode2(GICR_renderExtractCPol), // auxiliary
        GIR_CustomOperandRenderer, /*InsnID*/0, /*OldInsnID*/0, /*OpIdx*/6, /*OperandRenderer*/GIMT_Encode2(GICR_renderExtractSWZ), // auxiliary
        GIR_MergeMemOperands, /*InsnID*/0, /*NumInsns*/1, /*MergeInsnID's*/0,
        GIR_ConstrainSelectedInstOperands, /*InsnID*/0,
        GIR_EraseFromParent, /*InsnID*/0,
        // GIR_Coverage, 4340,
        GIR_Done,
      // Label 7011: @515158
      GIM_Try, /*On fail goto*//*Label 7012*/ GIMT_Encode4(515268), // Rule ID 4344 //
        GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasPackedD16VMem),
        // MIs[0] offset
        GIM_CheckIsImm, /*MI*/0, /*Op*/5,
        // MIs[0] auxiliary
        GIM_CheckIsImm, /*MI*/0, /*Op*/6,
        // MIs[0] Operand 7
        GIM_CheckIsImm, /*MI*/0, /*Op*/7,
        GIM_CheckComplexPattern, /*MI*/0, /*Op*/4, /*Renderer*/GIMT_Encode2(0), GIMT_Encode2(GICP_gi_buf_soffset),
        // (SIbuffer_store_format_d16 i32:{ *:[i32] }:$vdata, v4i32:{ *:[v4i32] }:$rsrc, i32:{ *:[i32] }:$vindex, i32:{ *:[i32] }:$voffset, (BUFSOffset:{ *:[i32] } i32:{ *:[i32] }:$soffset), (timm:{ *:[i32] }):$offset, (timm:{ *:[i32] }):$auxiliary, (timm:{ *:[i1] }))  =>  (BUFFER_STORE_FORMAT_D16_X_VBUFFER_BOTHEN_exact anonymous_15037:{ *:[i32] }:$vdata, (REG_SEQUENCE:{ *:[i64] } VReg_64:{ *:[i32] }, VGPR_32:{ *:[i32] }:$vindex, sub0:{ *:[i32] }, VGPR_32:{ *:[i32] }:$voffset, sub1:{ *:[i32] }), SReg_128:{ *:[v4i32] }:$rsrc, SCSrc_b32:{ *:[i32] }:$soffset, (timm:{ *:[i32] }):$offset, (extract_cpol:{ *:[i32] } ?:{ *:[i32] }:$auxiliary), (extract_swz:{ *:[i1] } ?:{ *:[i32] }:$auxiliary))
        GIR_MakeTempReg, /*TempRegID*/0, /*TypeID*/GILLT_s64,
        GIR_BuildMI, /*InsnID*/1, /*Opcode*/GIMT_Encode2(TargetOpcode::REG_SEQUENCE),
        GIR_AddTempRegister, /*InsnID*/1, /*TempRegID*/0, /*TempRegFlags*/GIMT_Encode2(RegState::Define),
        GIR_Copy, /*NewInsnID*/1, /*OldInsnID*/0, /*OpIdx*/2, // vindex
        GIR_AddImm8, /*InsnID*/1, /*SubRegIndex*/3,
        GIR_Copy, /*NewInsnID*/1, /*OldInsnID*/0, /*OpIdx*/3, // voffset
        GIR_AddImm8, /*InsnID*/1, /*SubRegIndex*/11,
        GIR_ConstrainOperandRC, /*InsnID*/1, /*Op*/0, GIMT_Encode2(AMDGPU::VReg_64RegClassID),
        GIR_ConstrainOperandRC, /*InsnID*/1, /*Op*/1, GIMT_Encode2(AMDGPU::VGPR_32RegClassID),
        GIR_ConstrainOperandRC, /*InsnID*/1, /*Op*/3, GIMT_Encode2(AMDGPU::VGPR_32RegClassID),
        GIR_BuildMI, /*InsnID*/0, /*Opcode*/GIMT_Encode2(AMDGPU::BUFFER_STORE_FORMAT_D16_X_VBUFFER_BOTHEN_exact),
        GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/0, // vdata
        GIR_AddSimpleTempRegister, /*InsnID*/0, /*TempRegID*/0,
        GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/1, // rsrc
        GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/0, // soffset
        GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/5, // offset
        GIR_CustomOperandRenderer, /*InsnID*/0, /*OldInsnID*/0, /*OpIdx*/6, /*OperandRenderer*/GIMT_Encode2(GICR_renderExtractCPol), // auxiliary
        GIR_CustomOperandRenderer, /*InsnID*/0, /*OldInsnID*/0, /*OpIdx*/6, /*OperandRenderer*/GIMT_Encode2(GICR_renderExtractSWZ), // auxiliary
        GIR_MergeMemOperands, /*InsnID*/0, /*NumInsns*/1, /*MergeInsnID's*/0,
        GIR_ConstrainSelectedInstOperands, /*InsnID*/0,
        GIR_EraseFromParent, /*InsnID*/0,
        // GIR_Coverage, 4344,
        GIR_Done,
      // Label 7012: @515268
      GIM_Reject,
    // Label 7000: @515269
    GIM_Reject,
    // Label 6969: @515270
    GIM_Try, /*On fail goto*//*Label 7013*/ GIMT_Encode4(516684),
      GIM_CheckType, /*MI*/0, /*Op*/1, /*Type*/GILLT_v4s32,
      GIM_CheckType, /*MI*/0, /*Op*/2, /*Type*/GILLT_s32,
      GIM_CheckType, /*MI*/0, /*Op*/3, /*Type*/GILLT_s32,
      GIM_CheckType, /*MI*/0, /*Op*/4, /*Type*/GILLT_s32,
      GIM_Try, /*On fail goto*//*Label 7014*/ GIMT_Encode4(515373), // Rule ID 4345 //
        GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasPackedD16VMem_HasUnrestrictedSOffset),
        GIM_CheckConstantInt8, /*MI*/0, /*Op*/2, 0,
        GIM_CheckConstantInt8, /*MI*/0, /*Op*/3, 0,
        // MIs[0] offset
        GIM_CheckIsImm, /*MI*/0, /*Op*/5,
        // MIs[0] auxiliary
        GIM_CheckIsImm, /*MI*/0, /*Op*/6,
        // MIs[0] Operand 7
        GIM_CheckLiteralInt, /*MI*/0, /*Op*/7, GIMT_Encode8(0),
        GIM_CheckComplexPattern, /*MI*/0, /*Op*/4, /*Renderer*/GIMT_Encode2(0), GIMT_Encode2(GICP_gi_buf_soffset),
        // (SIbuffer_store_format_d16 v2f16:{ *:[v2f16] }:$vdata, v4i32:{ *:[v4i32] }:$rsrc, 0:{ *:[i32] }, 0:{ *:[i32] }, (BUFSOffset:{ *:[i32] } i32:{ *:[i32] }:$soffset), (timm:{ *:[i32] }):$offset, (timm:{ *:[i32] }):$auxiliary, 0:{ *:[i1] })  =>  (BUFFER_STORE_FORMAT_D16_XY_OFFSET_exact anonymous_15037:{ *:[v2f16] }:$vdata, SReg_128:{ *:[v4i32] }:$rsrc, SCSrc_b32:{ *:[i32] }:$soffset, (timm:{ *:[i32] }):$offset, (extract_cpol:{ *:[i32] } ?:{ *:[i32] }:$auxiliary), (extract_swz:{ *:[i1] } ?:{ *:[i32] }:$auxiliary))
        GIR_BuildMI, /*InsnID*/0, /*Opcode*/GIMT_Encode2(AMDGPU::BUFFER_STORE_FORMAT_D16_XY_OFFSET_exact),
        GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/0, // vdata
        GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/1, // rsrc
        GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/0, // soffset
        GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/5, // offset
        GIR_CustomOperandRenderer, /*InsnID*/0, /*OldInsnID*/0, /*OpIdx*/6, /*OperandRenderer*/GIMT_Encode2(GICR_renderExtractCPol), // auxiliary
        GIR_CustomOperandRenderer, /*InsnID*/0, /*OldInsnID*/0, /*OpIdx*/6, /*OperandRenderer*/GIMT_Encode2(GICR_renderExtractSWZ), // auxiliary
        GIR_MergeMemOperands, /*InsnID*/0, /*NumInsns*/1, /*MergeInsnID's*/0,
        GIR_ConstrainSelectedInstOperands, /*InsnID*/0,
        GIR_EraseFromParent, /*InsnID*/0,
        // GIR_Coverage, 4345,
        GIR_Done,
      // Label 7014: @515373
      GIM_Try, /*On fail goto*//*Label 7015*/ GIMT_Encode4(515455), // Rule ID 4349 //
        GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasPackedD16VMem),
        GIM_CheckConstantInt8, /*MI*/0, /*Op*/2, 0,
        GIM_CheckConstantInt8, /*MI*/0, /*Op*/3, 0,
        // MIs[0] offset
        GIM_CheckIsImm, /*MI*/0, /*Op*/5,
        // MIs[0] auxiliary
        GIM_CheckIsImm, /*MI*/0, /*Op*/6,
        // MIs[0] Operand 7
        GIM_CheckLiteralInt, /*MI*/0, /*Op*/7, GIMT_Encode8(0),
        GIM_CheckComplexPattern, /*MI*/0, /*Op*/4, /*Renderer*/GIMT_Encode2(0), GIMT_Encode2(GICP_gi_buf_soffset),
        // (SIbuffer_store_format_d16 v2f16:{ *:[v2f16] }:$vdata, v4i32:{ *:[v4i32] }:$rsrc, 0:{ *:[i32] }, 0:{ *:[i32] }, (BUFSOffset:{ *:[i32] } i32:{ *:[i32] }:$soffset), (timm:{ *:[i32] }):$offset, (timm:{ *:[i32] }):$auxiliary, 0:{ *:[i1] })  =>  (BUFFER_STORE_FORMAT_D16_XY_VBUFFER_OFFSET_exact anonymous_15037:{ *:[v2f16] }:$vdata, SReg_128:{ *:[v4i32] }:$rsrc, SCSrc_b32:{ *:[i32] }:$soffset, (timm:{ *:[i32] }):$offset, (extract_cpol:{ *:[i32] } ?:{ *:[i32] }:$auxiliary), (extract_swz:{ *:[i1] } ?:{ *:[i32] }:$auxiliary))
        GIR_BuildMI, /*InsnID*/0, /*Opcode*/GIMT_Encode2(AMDGPU::BUFFER_STORE_FORMAT_D16_XY_VBUFFER_OFFSET_exact),
        GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/0, // vdata
        GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/1, // rsrc
        GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/0, // soffset
        GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/5, // offset
        GIR_CustomOperandRenderer, /*InsnID*/0, /*OldInsnID*/0, /*OpIdx*/6, /*OperandRenderer*/GIMT_Encode2(GICR_renderExtractCPol), // auxiliary
        GIR_CustomOperandRenderer, /*InsnID*/0, /*OldInsnID*/0, /*OpIdx*/6, /*OperandRenderer*/GIMT_Encode2(GICR_renderExtractSWZ), // auxiliary
        GIR_MergeMemOperands, /*InsnID*/0, /*NumInsns*/1, /*MergeInsnID's*/0,
        GIR_ConstrainSelectedInstOperands, /*InsnID*/0,
        GIR_EraseFromParent, /*InsnID*/0,
        // GIR_Coverage, 4349,
        GIR_Done,
      // Label 7015: @515455
      GIM_Try, /*On fail goto*//*Label 7016*/ GIMT_Encode4(515537), // Rule ID 4353 //
        GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasPackedD16VMem_HasUnrestrictedSOffset),
        GIM_CheckConstantInt8, /*MI*/0, /*Op*/2, 0,
        GIM_CheckConstantInt8, /*MI*/0, /*Op*/3, 0,
        // MIs[0] offset
        GIM_CheckIsImm, /*MI*/0, /*Op*/5,
        // MIs[0] auxiliary
        GIM_CheckIsImm, /*MI*/0, /*Op*/6,
        // MIs[0] Operand 7
        GIM_CheckLiteralInt, /*MI*/0, /*Op*/7, GIMT_Encode8(0),
        GIM_CheckComplexPattern, /*MI*/0, /*Op*/4, /*Renderer*/GIMT_Encode2(0), GIMT_Encode2(GICP_gi_buf_soffset),
        // (SIbuffer_store_format_d16 v2i16:{ *:[v2i16] }:$vdata, v4i32:{ *:[v4i32] }:$rsrc, 0:{ *:[i32] }, 0:{ *:[i32] }, (BUFSOffset:{ *:[i32] } i32:{ *:[i32] }:$soffset), (timm:{ *:[i32] }):$offset, (timm:{ *:[i32] }):$auxiliary, 0:{ *:[i1] })  =>  (BUFFER_STORE_FORMAT_D16_XY_OFFSET_exact anonymous_15037:{ *:[v2i16] }:$vdata, SReg_128:{ *:[v4i32] }:$rsrc, SCSrc_b32:{ *:[i32] }:$soffset, (timm:{ *:[i32] }):$offset, (extract_cpol:{ *:[i32] } ?:{ *:[i32] }:$auxiliary), (extract_swz:{ *:[i1] } ?:{ *:[i32] }:$auxiliary))
        GIR_BuildMI, /*InsnID*/0, /*Opcode*/GIMT_Encode2(AMDGPU::BUFFER_STORE_FORMAT_D16_XY_OFFSET_exact),
        GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/0, // vdata
        GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/1, // rsrc
        GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/0, // soffset
        GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/5, // offset
        GIR_CustomOperandRenderer, /*InsnID*/0, /*OldInsnID*/0, /*OpIdx*/6, /*OperandRenderer*/GIMT_Encode2(GICR_renderExtractCPol), // auxiliary
        GIR_CustomOperandRenderer, /*InsnID*/0, /*OldInsnID*/0, /*OpIdx*/6, /*OperandRenderer*/GIMT_Encode2(GICR_renderExtractSWZ), // auxiliary
        GIR_MergeMemOperands, /*InsnID*/0, /*NumInsns*/1, /*MergeInsnID's*/0,
        GIR_ConstrainSelectedInstOperands, /*InsnID*/0,
        GIR_EraseFromParent, /*InsnID*/0,
        // GIR_Coverage, 4353,
        GIR_Done,
      // Label 7016: @515537
      GIM_Try, /*On fail goto*//*Label 7017*/ GIMT_Encode4(515619), // Rule ID 4357 //
        GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasPackedD16VMem),
        GIM_CheckConstantInt8, /*MI*/0, /*Op*/2, 0,
        GIM_CheckConstantInt8, /*MI*/0, /*Op*/3, 0,
        // MIs[0] offset
        GIM_CheckIsImm, /*MI*/0, /*Op*/5,
        // MIs[0] auxiliary
        GIM_CheckIsImm, /*MI*/0, /*Op*/6,
        // MIs[0] Operand 7
        GIM_CheckLiteralInt, /*MI*/0, /*Op*/7, GIMT_Encode8(0),
        GIM_CheckComplexPattern, /*MI*/0, /*Op*/4, /*Renderer*/GIMT_Encode2(0), GIMT_Encode2(GICP_gi_buf_soffset),
        // (SIbuffer_store_format_d16 v2i16:{ *:[v2i16] }:$vdata, v4i32:{ *:[v4i32] }:$rsrc, 0:{ *:[i32] }, 0:{ *:[i32] }, (BUFSOffset:{ *:[i32] } i32:{ *:[i32] }:$soffset), (timm:{ *:[i32] }):$offset, (timm:{ *:[i32] }):$auxiliary, 0:{ *:[i1] })  =>  (BUFFER_STORE_FORMAT_D16_XY_VBUFFER_OFFSET_exact anonymous_15037:{ *:[v2i16] }:$vdata, SReg_128:{ *:[v4i32] }:$rsrc, SCSrc_b32:{ *:[i32] }:$soffset, (timm:{ *:[i32] }):$offset, (extract_cpol:{ *:[i32] } ?:{ *:[i32] }:$auxiliary), (extract_swz:{ *:[i1] } ?:{ *:[i32] }:$auxiliary))
        GIR_BuildMI, /*InsnID*/0, /*Opcode*/GIMT_Encode2(AMDGPU::BUFFER_STORE_FORMAT_D16_XY_VBUFFER_OFFSET_exact),
        GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/0, // vdata
        GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/1, // rsrc
        GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/0, // soffset
        GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/5, // offset
        GIR_CustomOperandRenderer, /*InsnID*/0, /*OldInsnID*/0, /*OpIdx*/6, /*OperandRenderer*/GIMT_Encode2(GICR_renderExtractCPol), // auxiliary
        GIR_CustomOperandRenderer, /*InsnID*/0, /*OldInsnID*/0, /*OpIdx*/6, /*OperandRenderer*/GIMT_Encode2(GICR_renderExtractSWZ), // auxiliary
        GIR_MergeMemOperands, /*InsnID*/0, /*NumInsns*/1, /*MergeInsnID's*/0,
        GIR_ConstrainSelectedInstOperands, /*InsnID*/0,
        GIR_EraseFromParent, /*InsnID*/0,
        // GIR_Coverage, 4357,
        GIR_Done,
      // Label 7017: @515619
      GIM_Try, /*On fail goto*//*Label 7018*/ GIMT_Encode4(515701), // Rule ID 4346 //
        GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasPackedD16VMem_HasUnrestrictedSOffset),
        GIM_CheckConstantInt8, /*MI*/0, /*Op*/2, 0,
        // MIs[0] offset
        GIM_CheckIsImm, /*MI*/0, /*Op*/5,
        // MIs[0] auxiliary
        GIM_CheckIsImm, /*MI*/0, /*Op*/6,
        // MIs[0] Operand 7
        GIM_CheckLiteralInt, /*MI*/0, /*Op*/7, GIMT_Encode8(0),
        GIM_CheckComplexPattern, /*MI*/0, /*Op*/4, /*Renderer*/GIMT_Encode2(0), GIMT_Encode2(GICP_gi_buf_soffset),
        // (SIbuffer_store_format_d16 v2f16:{ *:[v2f16] }:$vdata, v4i32:{ *:[v4i32] }:$rsrc, 0:{ *:[i32] }, i32:{ *:[i32] }:$voffset, (BUFSOffset:{ *:[i32] } i32:{ *:[i32] }:$soffset), (timm:{ *:[i32] }):$offset, (timm:{ *:[i32] }):$auxiliary, 0:{ *:[i1] })  =>  (BUFFER_STORE_FORMAT_D16_XY_OFFEN_exact anonymous_15037:{ *:[v2f16] }:$vdata, VGPR_32:{ *:[i32] }:$voffset, SReg_128:{ *:[v4i32] }:$rsrc, SCSrc_b32:{ *:[i32] }:$soffset, (timm:{ *:[i32] }):$offset, (extract_cpol:{ *:[i32] } ?:{ *:[i32] }:$auxiliary), (extract_swz:{ *:[i1] } ?:{ *:[i32] }:$auxiliary))
        GIR_BuildMI, /*InsnID*/0, /*Opcode*/GIMT_Encode2(AMDGPU::BUFFER_STORE_FORMAT_D16_XY_OFFEN_exact),
        GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/0, // vdata
        GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/3, // voffset
        GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/1, // rsrc
        GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/0, // soffset
        GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/5, // offset
        GIR_CustomOperandRenderer, /*InsnID*/0, /*OldInsnID*/0, /*OpIdx*/6, /*OperandRenderer*/GIMT_Encode2(GICR_renderExtractCPol), // auxiliary
        GIR_CustomOperandRenderer, /*InsnID*/0, /*OldInsnID*/0, /*OpIdx*/6, /*OperandRenderer*/GIMT_Encode2(GICR_renderExtractSWZ), // auxiliary
        GIR_MergeMemOperands, /*InsnID*/0, /*NumInsns*/1, /*MergeInsnID's*/0,
        GIR_ConstrainSelectedInstOperands, /*InsnID*/0,
        GIR_EraseFromParent, /*InsnID*/0,
        // GIR_Coverage, 4346,
        GIR_Done,
      // Label 7018: @515701
      GIM_Try, /*On fail goto*//*Label 7019*/ GIMT_Encode4(515783), // Rule ID 4350 //
        GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasPackedD16VMem),
        GIM_CheckConstantInt8, /*MI*/0, /*Op*/2, 0,
        // MIs[0] offset
        GIM_CheckIsImm, /*MI*/0, /*Op*/5,
        // MIs[0] auxiliary
        GIM_CheckIsImm, /*MI*/0, /*Op*/6,
        // MIs[0] Operand 7
        GIM_CheckLiteralInt, /*MI*/0, /*Op*/7, GIMT_Encode8(0),
        GIM_CheckComplexPattern, /*MI*/0, /*Op*/4, /*Renderer*/GIMT_Encode2(0), GIMT_Encode2(GICP_gi_buf_soffset),
        // (SIbuffer_store_format_d16 v2f16:{ *:[v2f16] }:$vdata, v4i32:{ *:[v4i32] }:$rsrc, 0:{ *:[i32] }, i32:{ *:[i32] }:$voffset, (BUFSOffset:{ *:[i32] } i32:{ *:[i32] }:$soffset), (timm:{ *:[i32] }):$offset, (timm:{ *:[i32] }):$auxiliary, 0:{ *:[i1] })  =>  (BUFFER_STORE_FORMAT_D16_XY_VBUFFER_OFFEN_exact anonymous_15037:{ *:[v2f16] }:$vdata, VGPR_32:{ *:[i32] }:$voffset, SReg_128:{ *:[v4i32] }:$rsrc, SCSrc_b32:{ *:[i32] }:$soffset, (timm:{ *:[i32] }):$offset, (extract_cpol:{ *:[i32] } ?:{ *:[i32] }:$auxiliary), (extract_swz:{ *:[i1] } ?:{ *:[i32] }:$auxiliary))
        GIR_BuildMI, /*InsnID*/0, /*Opcode*/GIMT_Encode2(AMDGPU::BUFFER_STORE_FORMAT_D16_XY_VBUFFER_OFFEN_exact),
        GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/0, // vdata
        GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/3, // voffset
        GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/1, // rsrc
        GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/0, // soffset
        GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/5, // offset
        GIR_CustomOperandRenderer, /*InsnID*/0, /*OldInsnID*/0, /*OpIdx*/6, /*OperandRenderer*/GIMT_Encode2(GICR_renderExtractCPol), // auxiliary
        GIR_CustomOperandRenderer, /*InsnID*/0, /*OldInsnID*/0, /*OpIdx*/6, /*OperandRenderer*/GIMT_Encode2(GICR_renderExtractSWZ), // auxiliary
        GIR_MergeMemOperands, /*InsnID*/0, /*NumInsns*/1, /*MergeInsnID's*/0,
        GIR_ConstrainSelectedInstOperands, /*InsnID*/0,
        GIR_EraseFromParent, /*InsnID*/0,
        // GIR_Coverage, 4350,
        GIR_Done,
      // Label 7019: @515783
      GIM_Try, /*On fail goto*//*Label 7020*/ GIMT_Encode4(515865), // Rule ID 4354 //
        GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasPackedD16VMem_HasUnrestrictedSOffset),
        GIM_CheckConstantInt8, /*MI*/0, /*Op*/2, 0,
        // MIs[0] offset
        GIM_CheckIsImm, /*MI*/0, /*Op*/5,
        // MIs[0] auxiliary
        GIM_CheckIsImm, /*MI*/0, /*Op*/6,
        // MIs[0] Operand 7
        GIM_CheckLiteralInt, /*MI*/0, /*Op*/7, GIMT_Encode8(0),
        GIM_CheckComplexPattern, /*MI*/0, /*Op*/4, /*Renderer*/GIMT_Encode2(0), GIMT_Encode2(GICP_gi_buf_soffset),
        // (SIbuffer_store_format_d16 v2i16:{ *:[v2i16] }:$vdata, v4i32:{ *:[v4i32] }:$rsrc, 0:{ *:[i32] }, i32:{ *:[i32] }:$voffset, (BUFSOffset:{ *:[i32] } i32:{ *:[i32] }:$soffset), (timm:{ *:[i32] }):$offset, (timm:{ *:[i32] }):$auxiliary, 0:{ *:[i1] })  =>  (BUFFER_STORE_FORMAT_D16_XY_OFFEN_exact anonymous_15037:{ *:[v2i16] }:$vdata, VGPR_32:{ *:[i32] }:$voffset, SReg_128:{ *:[v4i32] }:$rsrc, SCSrc_b32:{ *:[i32] }:$soffset, (timm:{ *:[i32] }):$offset, (extract_cpol:{ *:[i32] } ?:{ *:[i32] }:$auxiliary), (extract_swz:{ *:[i1] } ?:{ *:[i32] }:$auxiliary))
        GIR_BuildMI, /*InsnID*/0, /*Opcode*/GIMT_Encode2(AMDGPU::BUFFER_STORE_FORMAT_D16_XY_OFFEN_exact),
        GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/0, // vdata
        GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/3, // voffset
        GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/1, // rsrc
        GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/0, // soffset
        GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/5, // offset
        GIR_CustomOperandRenderer, /*InsnID*/0, /*OldInsnID*/0, /*OpIdx*/6, /*OperandRenderer*/GIMT_Encode2(GICR_renderExtractCPol), // auxiliary
        GIR_CustomOperandRenderer, /*InsnID*/0, /*OldInsnID*/0, /*OpIdx*/6, /*OperandRenderer*/GIMT_Encode2(GICR_renderExtractSWZ), // auxiliary
        GIR_MergeMemOperands, /*InsnID*/0, /*NumInsns*/1, /*MergeInsnID's*/0,
        GIR_ConstrainSelectedInstOperands, /*InsnID*/0,
        GIR_EraseFromParent, /*InsnID*/0,
        // GIR_Coverage, 4354,
        GIR_Done,
      // Label 7020: @515865
      GIM_Try, /*On fail goto*//*Label 7021*/ GIMT_Encode4(515947), // Rule ID 4358 //
        GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasPackedD16VMem),
        GIM_CheckConstantInt8, /*MI*/0, /*Op*/2, 0,
        // MIs[0] offset
        GIM_CheckIsImm, /*MI*/0, /*Op*/5,
        // MIs[0] auxiliary
        GIM_CheckIsImm, /*MI*/0, /*Op*/6,
        // MIs[0] Operand 7
        GIM_CheckLiteralInt, /*MI*/0, /*Op*/7, GIMT_Encode8(0),
        GIM_CheckComplexPattern, /*MI*/0, /*Op*/4, /*Renderer*/GIMT_Encode2(0), GIMT_Encode2(GICP_gi_buf_soffset),
        // (SIbuffer_store_format_d16 v2i16:{ *:[v2i16] }:$vdata, v4i32:{ *:[v4i32] }:$rsrc, 0:{ *:[i32] }, i32:{ *:[i32] }:$voffset, (BUFSOffset:{ *:[i32] } i32:{ *:[i32] }:$soffset), (timm:{ *:[i32] }):$offset, (timm:{ *:[i32] }):$auxiliary, 0:{ *:[i1] })  =>  (BUFFER_STORE_FORMAT_D16_XY_VBUFFER_OFFEN_exact anonymous_15037:{ *:[v2i16] }:$vdata, VGPR_32:{ *:[i32] }:$voffset, SReg_128:{ *:[v4i32] }:$rsrc, SCSrc_b32:{ *:[i32] }:$soffset, (timm:{ *:[i32] }):$offset, (extract_cpol:{ *:[i32] } ?:{ *:[i32] }:$auxiliary), (extract_swz:{ *:[i1] } ?:{ *:[i32] }:$auxiliary))
        GIR_BuildMI, /*InsnID*/0, /*Opcode*/GIMT_Encode2(AMDGPU::BUFFER_STORE_FORMAT_D16_XY_VBUFFER_OFFEN_exact),
        GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/0, // vdata
        GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/3, // voffset
        GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/1, // rsrc
        GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/0, // soffset
        GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/5, // offset
        GIR_CustomOperandRenderer, /*InsnID*/0, /*OldInsnID*/0, /*OpIdx*/6, /*OperandRenderer*/GIMT_Encode2(GICR_renderExtractCPol), // auxiliary
        GIR_CustomOperandRenderer, /*InsnID*/0, /*OldInsnID*/0, /*OpIdx*/6, /*OperandRenderer*/GIMT_Encode2(GICR_renderExtractSWZ), // auxiliary
        GIR_MergeMemOperands, /*InsnID*/0, /*NumInsns*/1, /*MergeInsnID's*/0,
        GIR_ConstrainSelectedInstOperands, /*InsnID*/0,
        GIR_EraseFromParent, /*InsnID*/0,
        // GIR_Coverage, 4358,
        GIR_Done,
      // Label 7021: @515947
      GIM_Try, /*On fail goto*//*Label 7022*/ GIMT_Encode4(516021), // Rule ID 4347 //
        GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasPackedD16VMem_HasUnrestrictedSOffset),
        GIM_CheckConstantInt8, /*MI*/0, /*Op*/3, 0,
        // MIs[0] offset
        GIM_CheckIsImm, /*MI*/0, /*Op*/5,
        // MIs[0] auxiliary
        GIM_CheckIsImm, /*MI*/0, /*Op*/6,
        // MIs[0] Operand 7
        GIM_CheckIsImm, /*MI*/0, /*Op*/7,
        GIM_CheckComplexPattern, /*MI*/0, /*Op*/4, /*Renderer*/GIMT_Encode2(0), GIMT_Encode2(GICP_gi_buf_soffset),
        // (SIbuffer_store_format_d16 v2f16:{ *:[v2f16] }:$vdata, v4i32:{ *:[v4i32] }:$rsrc, i32:{ *:[i32] }:$vindex, 0:{ *:[i32] }, (BUFSOffset:{ *:[i32] } i32:{ *:[i32] }:$soffset), (timm:{ *:[i32] }):$offset, (timm:{ *:[i32] }):$auxiliary, (timm:{ *:[i1] }))  =>  (BUFFER_STORE_FORMAT_D16_XY_IDXEN_exact anonymous_15037:{ *:[v2f16] }:$vdata, VGPR_32:{ *:[i32] }:$vindex, SReg_128:{ *:[v4i32] }:$rsrc, SCSrc_b32:{ *:[i32] }:$soffset, (timm:{ *:[i32] }):$offset, (extract_cpol:{ *:[i32] } ?:{ *:[i32] }:$auxiliary), (extract_swz:{ *:[i1] } ?:{ *:[i32] }:$auxiliary))
        GIR_BuildMI, /*InsnID*/0, /*Opcode*/GIMT_Encode2(AMDGPU::BUFFER_STORE_FORMAT_D16_XY_IDXEN_exact),
        GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/0, // vdata
        GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/2, // vindex
        GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/1, // rsrc
        GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/0, // soffset
        GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/5, // offset
        GIR_CustomOperandRenderer, /*InsnID*/0, /*OldInsnID*/0, /*OpIdx*/6, /*OperandRenderer*/GIMT_Encode2(GICR_renderExtractCPol), // auxiliary
        GIR_CustomOperandRenderer, /*InsnID*/0, /*OldInsnID*/0, /*OpIdx*/6, /*OperandRenderer*/GIMT_Encode2(GICR_renderExtractSWZ), // auxiliary
        GIR_MergeMemOperands, /*InsnID*/0, /*NumInsns*/1, /*MergeInsnID's*/0,
        GIR_ConstrainSelectedInstOperands, /*InsnID*/0,
        GIR_EraseFromParent, /*InsnID*/0,
        // GIR_Coverage, 4347,
        GIR_Done,
      // Label 7022: @516021
      GIM_Try, /*On fail goto*//*Label 7023*/ GIMT_Encode4(516095), // Rule ID 4351 //
        GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasPackedD16VMem),
        GIM_CheckConstantInt8, /*MI*/0, /*Op*/3, 0,
        // MIs[0] offset
        GIM_CheckIsImm, /*MI*/0, /*Op*/5,
        // MIs[0] auxiliary
        GIM_CheckIsImm, /*MI*/0, /*Op*/6,
        // MIs[0] Operand 7
        GIM_CheckIsImm, /*MI*/0, /*Op*/7,
        GIM_CheckComplexPattern, /*MI*/0, /*Op*/4, /*Renderer*/GIMT_Encode2(0), GIMT_Encode2(GICP_gi_buf_soffset),
        // (SIbuffer_store_format_d16 v2f16:{ *:[v2f16] }:$vdata, v4i32:{ *:[v4i32] }:$rsrc, i32:{ *:[i32] }:$vindex, 0:{ *:[i32] }, (BUFSOffset:{ *:[i32] } i32:{ *:[i32] }:$soffset), (timm:{ *:[i32] }):$offset, (timm:{ *:[i32] }):$auxiliary, (timm:{ *:[i1] }))  =>  (BUFFER_STORE_FORMAT_D16_XY_VBUFFER_IDXEN_exact anonymous_15037:{ *:[v2f16] }:$vdata, VGPR_32:{ *:[i32] }:$vindex, SReg_128:{ *:[v4i32] }:$rsrc, SCSrc_b32:{ *:[i32] }:$soffset, (timm:{ *:[i32] }):$offset, (extract_cpol:{ *:[i32] } ?:{ *:[i32] }:$auxiliary), (extract_swz:{ *:[i1] } ?:{ *:[i32] }:$auxiliary))
        GIR_BuildMI, /*InsnID*/0, /*Opcode*/GIMT_Encode2(AMDGPU::BUFFER_STORE_FORMAT_D16_XY_VBUFFER_IDXEN_exact),
        GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/0, // vdata
        GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/2, // vindex
        GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/1, // rsrc
        GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/0, // soffset
        GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/5, // offset
        GIR_CustomOperandRenderer, /*InsnID*/0, /*OldInsnID*/0, /*OpIdx*/6, /*OperandRenderer*/GIMT_Encode2(GICR_renderExtractCPol), // auxiliary
        GIR_CustomOperandRenderer, /*InsnID*/0, /*OldInsnID*/0, /*OpIdx*/6, /*OperandRenderer*/GIMT_Encode2(GICR_renderExtractSWZ), // auxiliary
        GIR_MergeMemOperands, /*InsnID*/0, /*NumInsns*/1, /*MergeInsnID's*/0,
        GIR_ConstrainSelectedInstOperands, /*InsnID*/0,
        GIR_EraseFromParent, /*InsnID*/0,
        // GIR_Coverage, 4351,
        GIR_Done,
      // Label 7023: @516095
      GIM_Try, /*On fail goto*//*Label 7024*/ GIMT_Encode4(516169), // Rule ID 4355 //
        GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasPackedD16VMem_HasUnrestrictedSOffset),
        GIM_CheckConstantInt8, /*MI*/0, /*Op*/3, 0,
        // MIs[0] offset
        GIM_CheckIsImm, /*MI*/0, /*Op*/5,
        // MIs[0] auxiliary
        GIM_CheckIsImm, /*MI*/0, /*Op*/6,
        // MIs[0] Operand 7
        GIM_CheckIsImm, /*MI*/0, /*Op*/7,
        GIM_CheckComplexPattern, /*MI*/0, /*Op*/4, /*Renderer*/GIMT_Encode2(0), GIMT_Encode2(GICP_gi_buf_soffset),
        // (SIbuffer_store_format_d16 v2i16:{ *:[v2i16] }:$vdata, v4i32:{ *:[v4i32] }:$rsrc, i32:{ *:[i32] }:$vindex, 0:{ *:[i32] }, (BUFSOffset:{ *:[i32] } i32:{ *:[i32] }:$soffset), (timm:{ *:[i32] }):$offset, (timm:{ *:[i32] }):$auxiliary, (timm:{ *:[i1] }))  =>  (BUFFER_STORE_FORMAT_D16_XY_IDXEN_exact anonymous_15037:{ *:[v2i16] }:$vdata, VGPR_32:{ *:[i32] }:$vindex, SReg_128:{ *:[v4i32] }:$rsrc, SCSrc_b32:{ *:[i32] }:$soffset, (timm:{ *:[i32] }):$offset, (extract_cpol:{ *:[i32] } ?:{ *:[i32] }:$auxiliary), (extract_swz:{ *:[i1] } ?:{ *:[i32] }:$auxiliary))
        GIR_BuildMI, /*InsnID*/0, /*Opcode*/GIMT_Encode2(AMDGPU::BUFFER_STORE_FORMAT_D16_XY_IDXEN_exact),
        GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/0, // vdata
        GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/2, // vindex
        GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/1, // rsrc
        GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/0, // soffset
        GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/5, // offset
        GIR_CustomOperandRenderer, /*InsnID*/0, /*OldInsnID*/0, /*OpIdx*/6, /*OperandRenderer*/GIMT_Encode2(GICR_renderExtractCPol), // auxiliary
        GIR_CustomOperandRenderer, /*InsnID*/0, /*OldInsnID*/0, /*OpIdx*/6, /*OperandRenderer*/GIMT_Encode2(GICR_renderExtractSWZ), // auxiliary
        GIR_MergeMemOperands, /*InsnID*/0, /*NumInsns*/1, /*MergeInsnID's*/0,
        GIR_ConstrainSelectedInstOperands, /*InsnID*/0,
        GIR_EraseFromParent, /*InsnID*/0,
        // GIR_Coverage, 4355,
        GIR_Done,
      // Label 7024: @516169
      GIM_Try, /*On fail goto*//*Label 7025*/ GIMT_Encode4(516243), // Rule ID 4359 //
        GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasPackedD16VMem),
        GIM_CheckConstantInt8, /*MI*/0, /*Op*/3, 0,
        // MIs[0] offset
        GIM_CheckIsImm, /*MI*/0, /*Op*/5,
        // MIs[0] auxiliary
        GIM_CheckIsImm, /*MI*/0, /*Op*/6,
        // MIs[0] Operand 7
        GIM_CheckIsImm, /*MI*/0, /*Op*/7,
        GIM_CheckComplexPattern, /*MI*/0, /*Op*/4, /*Renderer*/GIMT_Encode2(0), GIMT_Encode2(GICP_gi_buf_soffset),
        // (SIbuffer_store_format_d16 v2i16:{ *:[v2i16] }:$vdata, v4i32:{ *:[v4i32] }:$rsrc, i32:{ *:[i32] }:$vindex, 0:{ *:[i32] }, (BUFSOffset:{ *:[i32] } i32:{ *:[i32] }:$soffset), (timm:{ *:[i32] }):$offset, (timm:{ *:[i32] }):$auxiliary, (timm:{ *:[i1] }))  =>  (BUFFER_STORE_FORMAT_D16_XY_VBUFFER_IDXEN_exact anonymous_15037:{ *:[v2i16] }:$vdata, VGPR_32:{ *:[i32] }:$vindex, SReg_128:{ *:[v4i32] }:$rsrc, SCSrc_b32:{ *:[i32] }:$soffset, (timm:{ *:[i32] }):$offset, (extract_cpol:{ *:[i32] } ?:{ *:[i32] }:$auxiliary), (extract_swz:{ *:[i1] } ?:{ *:[i32] }:$auxiliary))
        GIR_BuildMI, /*InsnID*/0, /*Opcode*/GIMT_Encode2(AMDGPU::BUFFER_STORE_FORMAT_D16_XY_VBUFFER_IDXEN_exact),
        GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/0, // vdata
        GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/2, // vindex
        GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/1, // rsrc
        GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/0, // soffset
        GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/5, // offset
        GIR_CustomOperandRenderer, /*InsnID*/0, /*OldInsnID*/0, /*OpIdx*/6, /*OperandRenderer*/GIMT_Encode2(GICR_renderExtractCPol), // auxiliary
        GIR_CustomOperandRenderer, /*InsnID*/0, /*OldInsnID*/0, /*OpIdx*/6, /*OperandRenderer*/GIMT_Encode2(GICR_renderExtractSWZ), // auxiliary
        GIR_MergeMemOperands, /*InsnID*/0, /*NumInsns*/1, /*MergeInsnID's*/0,
        GIR_ConstrainSelectedInstOperands, /*InsnID*/0,
        GIR_EraseFromParent, /*InsnID*/0,
        // GIR_Coverage, 4359,
        GIR_Done,
      // Label 7025: @516243
      GIM_Try, /*On fail goto*//*Label 7026*/ GIMT_Encode4(516353), // Rule ID 4348 //
        GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasPackedD16VMem_HasUnrestrictedSOffset),
        // MIs[0] offset
        GIM_CheckIsImm, /*MI*/0, /*Op*/5,
        // MIs[0] auxiliary
        GIM_CheckIsImm, /*MI*/0, /*Op*/6,
        // MIs[0] Operand 7
        GIM_CheckIsImm, /*MI*/0, /*Op*/7,
        GIM_CheckComplexPattern, /*MI*/0, /*Op*/4, /*Renderer*/GIMT_Encode2(0), GIMT_Encode2(GICP_gi_buf_soffset),
        // (SIbuffer_store_format_d16 v2f16:{ *:[v2f16] }:$vdata, v4i32:{ *:[v4i32] }:$rsrc, i32:{ *:[i32] }:$vindex, i32:{ *:[i32] }:$voffset, (BUFSOffset:{ *:[i32] } i32:{ *:[i32] }:$soffset), (timm:{ *:[i32] }):$offset, (timm:{ *:[i32] }):$auxiliary, (timm:{ *:[i1] }))  =>  (BUFFER_STORE_FORMAT_D16_XY_BOTHEN_exact anonymous_15037:{ *:[v2f16] }:$vdata, (REG_SEQUENCE:{ *:[i64] } VReg_64:{ *:[i32] }, VGPR_32:{ *:[i32] }:$vindex, sub0:{ *:[i32] }, VGPR_32:{ *:[i32] }:$voffset, sub1:{ *:[i32] }), SReg_128:{ *:[v4i32] }:$rsrc, SCSrc_b32:{ *:[i32] }:$soffset, (timm:{ *:[i32] }):$offset, (extract_cpol:{ *:[i32] } ?:{ *:[i32] }:$auxiliary), (extract_swz:{ *:[i1] } ?:{ *:[i32] }:$auxiliary))
        GIR_MakeTempReg, /*TempRegID*/0, /*TypeID*/GILLT_s64,
        GIR_BuildMI, /*InsnID*/1, /*Opcode*/GIMT_Encode2(TargetOpcode::REG_SEQUENCE),
        GIR_AddTempRegister, /*InsnID*/1, /*TempRegID*/0, /*TempRegFlags*/GIMT_Encode2(RegState::Define),
        GIR_Copy, /*NewInsnID*/1, /*OldInsnID*/0, /*OpIdx*/2, // vindex
        GIR_AddImm8, /*InsnID*/1, /*SubRegIndex*/3,
        GIR_Copy, /*NewInsnID*/1, /*OldInsnID*/0, /*OpIdx*/3, // voffset
        GIR_AddImm8, /*InsnID*/1, /*SubRegIndex*/11,
        GIR_ConstrainOperandRC, /*InsnID*/1, /*Op*/0, GIMT_Encode2(AMDGPU::VReg_64RegClassID),
        GIR_ConstrainOperandRC, /*InsnID*/1, /*Op*/1, GIMT_Encode2(AMDGPU::VGPR_32RegClassID),
        GIR_ConstrainOperandRC, /*InsnID*/1, /*Op*/3, GIMT_Encode2(AMDGPU::VGPR_32RegClassID),
        GIR_BuildMI, /*InsnID*/0, /*Opcode*/GIMT_Encode2(AMDGPU::BUFFER_STORE_FORMAT_D16_XY_BOTHEN_exact),
        GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/0, // vdata
        GIR_AddSimpleTempRegister, /*InsnID*/0, /*TempRegID*/0,
        GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/1, // rsrc
        GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/0, // soffset
        GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/5, // offset
        GIR_CustomOperandRenderer, /*InsnID*/0, /*OldInsnID*/0, /*OpIdx*/6, /*OperandRenderer*/GIMT_Encode2(GICR_renderExtractCPol), // auxiliary
        GIR_CustomOperandRenderer, /*InsnID*/0, /*OldInsnID*/0, /*OpIdx*/6, /*OperandRenderer*/GIMT_Encode2(GICR_renderExtractSWZ), // auxiliary
        GIR_MergeMemOperands, /*InsnID*/0, /*NumInsns*/1, /*MergeInsnID's*/0,
        GIR_ConstrainSelectedInstOperands, /*InsnID*/0,
        GIR_EraseFromParent, /*InsnID*/0,
        // GIR_Coverage, 4348,
        GIR_Done,
      // Label 7026: @516353
      GIM_Try, /*On fail goto*//*Label 7027*/ GIMT_Encode4(516463), // Rule ID 4352 //
        GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasPackedD16VMem),
        // MIs[0] offset
        GIM_CheckIsImm, /*MI*/0, /*Op*/5,
        // MIs[0] auxiliary
        GIM_CheckIsImm, /*MI*/0, /*Op*/6,
        // MIs[0] Operand 7
        GIM_CheckIsImm, /*MI*/0, /*Op*/7,
        GIM_CheckComplexPattern, /*MI*/0, /*Op*/4, /*Renderer*/GIMT_Encode2(0), GIMT_Encode2(GICP_gi_buf_soffset),
        // (SIbuffer_store_format_d16 v2f16:{ *:[v2f16] }:$vdata, v4i32:{ *:[v4i32] }:$rsrc, i32:{ *:[i32] }:$vindex, i32:{ *:[i32] }:$voffset, (BUFSOffset:{ *:[i32] } i32:{ *:[i32] }:$soffset), (timm:{ *:[i32] }):$offset, (timm:{ *:[i32] }):$auxiliary, (timm:{ *:[i1] }))  =>  (BUFFER_STORE_FORMAT_D16_XY_VBUFFER_BOTHEN_exact anonymous_15037:{ *:[v2f16] }:$vdata, (REG_SEQUENCE:{ *:[i64] } VReg_64:{ *:[i32] }, VGPR_32:{ *:[i32] }:$vindex, sub0:{ *:[i32] }, VGPR_32:{ *:[i32] }:$voffset, sub1:{ *:[i32] }), SReg_128:{ *:[v4i32] }:$rsrc, SCSrc_b32:{ *:[i32] }:$soffset, (timm:{ *:[i32] }):$offset, (extract_cpol:{ *:[i32] } ?:{ *:[i32] }:$auxiliary), (extract_swz:{ *:[i1] } ?:{ *:[i32] }:$auxiliary))
        GIR_MakeTempReg, /*TempRegID*/0, /*TypeID*/GILLT_s64,
        GIR_BuildMI, /*InsnID*/1, /*Opcode*/GIMT_Encode2(TargetOpcode::REG_SEQUENCE),
        GIR_AddTempRegister, /*InsnID*/1, /*TempRegID*/0, /*TempRegFlags*/GIMT_Encode2(RegState::Define),
        GIR_Copy, /*NewInsnID*/1, /*OldInsnID*/0, /*OpIdx*/2, // vindex
        GIR_AddImm8, /*InsnID*/1, /*SubRegIndex*/3,
        GIR_Copy, /*NewInsnID*/1, /*OldInsnID*/0, /*OpIdx*/3, // voffset
        GIR_AddImm8, /*InsnID*/1, /*SubRegIndex*/11,
        GIR_ConstrainOperandRC, /*InsnID*/1, /*Op*/0, GIMT_Encode2(AMDGPU::VReg_64RegClassID),
        GIR_ConstrainOperandRC, /*InsnID*/1, /*Op*/1, GIMT_Encode2(AMDGPU::VGPR_32RegClassID),
        GIR_ConstrainOperandRC, /*InsnID*/1, /*Op*/3, GIMT_Encode2(AMDGPU::VGPR_32RegClassID),
        GIR_BuildMI, /*InsnID*/0, /*Opcode*/GIMT_Encode2(AMDGPU::BUFFER_STORE_FORMAT_D16_XY_VBUFFER_BOTHEN_exact),
        GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/0, // vdata
        GIR_AddSimpleTempRegister, /*InsnID*/0, /*TempRegID*/0,
        GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/1, // rsrc
        GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/0, // soffset
        GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/5, // offset
        GIR_CustomOperandRenderer, /*InsnID*/0, /*OldInsnID*/0, /*OpIdx*/6, /*OperandRenderer*/GIMT_Encode2(GICR_renderExtractCPol), // auxiliary
        GIR_CustomOperandRenderer, /*InsnID*/0, /*OldInsnID*/0, /*OpIdx*/6, /*OperandRenderer*/GIMT_Encode2(GICR_renderExtractSWZ), // auxiliary
        GIR_MergeMemOperands, /*InsnID*/0, /*NumInsns*/1, /*MergeInsnID's*/0,
        GIR_ConstrainSelectedInstOperands, /*InsnID*/0,
        GIR_EraseFromParent, /*InsnID*/0,
        // GIR_Coverage, 4352,
        GIR_Done,
      // Label 7027: @516463
      GIM_Try, /*On fail goto*//*Label 7028*/ GIMT_Encode4(516573), // Rule ID 4356 //
        GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasPackedD16VMem_HasUnrestrictedSOffset),
        // MIs[0] offset
        GIM_CheckIsImm, /*MI*/0, /*Op*/5,
        // MIs[0] auxiliary
        GIM_CheckIsImm, /*MI*/0, /*Op*/6,
        // MIs[0] Operand 7
        GIM_CheckIsImm, /*MI*/0, /*Op*/7,
        GIM_CheckComplexPattern, /*MI*/0, /*Op*/4, /*Renderer*/GIMT_Encode2(0), GIMT_Encode2(GICP_gi_buf_soffset),
        // (SIbuffer_store_format_d16 v2i16:{ *:[v2i16] }:$vdata, v4i32:{ *:[v4i32] }:$rsrc, i32:{ *:[i32] }:$vindex, i32:{ *:[i32] }:$voffset, (BUFSOffset:{ *:[i32] } i32:{ *:[i32] }:$soffset), (timm:{ *:[i32] }):$offset, (timm:{ *:[i32] }):$auxiliary, (timm:{ *:[i1] }))  =>  (BUFFER_STORE_FORMAT_D16_XY_BOTHEN_exact anonymous_15037:{ *:[v2i16] }:$vdata, (REG_SEQUENCE:{ *:[i64] } VReg_64:{ *:[i32] }, VGPR_32:{ *:[i32] }:$vindex, sub0:{ *:[i32] }, VGPR_32:{ *:[i32] }:$voffset, sub1:{ *:[i32] }), SReg_128:{ *:[v4i32] }:$rsrc, SCSrc_b32:{ *:[i32] }:$soffset, (timm:{ *:[i32] }):$offset, (extract_cpol:{ *:[i32] } ?:{ *:[i32] }:$auxiliary), (extract_swz:{ *:[i1] } ?:{ *:[i32] }:$auxiliary))
        GIR_MakeTempReg, /*TempRegID*/0, /*TypeID*/GILLT_s64,
        GIR_BuildMI, /*InsnID*/1, /*Opcode*/GIMT_Encode2(TargetOpcode::REG_SEQUENCE),
        GIR_AddTempRegister, /*InsnID*/1, /*TempRegID*/0, /*TempRegFlags*/GIMT_Encode2(RegState::Define),
        GIR_Copy, /*NewInsnID*/1, /*OldInsnID*/0, /*OpIdx*/2, // vindex
        GIR_AddImm8, /*InsnID*/1, /*SubRegIndex*/3,
        GIR_Copy, /*NewInsnID*/1, /*OldInsnID*/0, /*OpIdx*/3, // voffset
        GIR_AddImm8, /*InsnID*/1, /*SubRegIndex*/11,
        GIR_ConstrainOperandRC, /*InsnID*/1, /*Op*/0, GIMT_Encode2(AMDGPU::VReg_64RegClassID),
        GIR_ConstrainOperandRC, /*InsnID*/1, /*Op*/1, GIMT_Encode2(AMDGPU::VGPR_32RegClassID),
        GIR_ConstrainOperandRC, /*InsnID*/1, /*Op*/3, GIMT_Encode2(AMDGPU::VGPR_32RegClassID),
        GIR_BuildMI, /*InsnID*/0, /*Opcode*/GIMT_Encode2(AMDGPU::BUFFER_STORE_FORMAT_D16_XY_BOTHEN_exact),
        GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/0, // vdata
        GIR_AddSimpleTempRegister, /*InsnID*/0, /*TempRegID*/0,
        GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/1, // rsrc
        GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/0, // soffset
        GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/5, // offset
        GIR_CustomOperandRenderer, /*InsnID*/0, /*OldInsnID*/0, /*OpIdx*/6, /*OperandRenderer*/GIMT_Encode2(GICR_renderExtractCPol), // auxiliary
        GIR_CustomOperandRenderer, /*InsnID*/0, /*OldInsnID*/0, /*OpIdx*/6, /*OperandRenderer*/GIMT_Encode2(GICR_renderExtractSWZ), // auxiliary
        GIR_MergeMemOperands, /*InsnID*/0, /*NumInsns*/1, /*MergeInsnID's*/0,
        GIR_ConstrainSelectedInstOperands, /*InsnID*/0,
        GIR_EraseFromParent, /*InsnID*/0,
        // GIR_Coverage, 4356,
        GIR_Done,
      // Label 7028: @516573
      GIM_Try, /*On fail goto*//*Label 7029*/ GIMT_Encode4(516683), // Rule ID 4360 //
        GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasPackedD16VMem),
        // MIs[0] offset
        GIM_CheckIsImm, /*MI*/0, /*Op*/5,
        // MIs[0] auxiliary
        GIM_CheckIsImm, /*MI*/0, /*Op*/6,
        // MIs[0] Operand 7
        GIM_CheckIsImm, /*MI*/0, /*Op*/7,
        GIM_CheckComplexPattern, /*MI*/0, /*Op*/4, /*Renderer*/GIMT_Encode2(0), GIMT_Encode2(GICP_gi_buf_soffset),
        // (SIbuffer_store_format_d16 v2i16:{ *:[v2i16] }:$vdata, v4i32:{ *:[v4i32] }:$rsrc, i32:{ *:[i32] }:$vindex, i32:{ *:[i32] }:$voffset, (BUFSOffset:{ *:[i32] } i32:{ *:[i32] }:$soffset), (timm:{ *:[i32] }):$offset, (timm:{ *:[i32] }):$auxiliary, (timm:{ *:[i1] }))  =>  (BUFFER_STORE_FORMAT_D16_XY_VBUFFER_BOTHEN_exact anonymous_15037:{ *:[v2i16] }:$vdata, (REG_SEQUENCE:{ *:[i64] } VReg_64:{ *:[i32] }, VGPR_32:{ *:[i32] }:$vindex, sub0:{ *:[i32] }, VGPR_32:{ *:[i32] }:$voffset, sub1:{ *:[i32] }), SReg_128:{ *:[v4i32] }:$rsrc, SCSrc_b32:{ *:[i32] }:$soffset, (timm:{ *:[i32] }):$offset, (extract_cpol:{ *:[i32] } ?:{ *:[i32] }:$auxiliary), (extract_swz:{ *:[i1] } ?:{ *:[i32] }:$auxiliary))
        GIR_MakeTempReg, /*TempRegID*/0, /*TypeID*/GILLT_s64,
        GIR_BuildMI, /*InsnID*/1, /*Opcode*/GIMT_Encode2(TargetOpcode::REG_SEQUENCE),
        GIR_AddTempRegister, /*InsnID*/1, /*TempRegID*/0, /*TempRegFlags*/GIMT_Encode2(RegState::Define),
        GIR_Copy, /*NewInsnID*/1, /*OldInsnID*/0, /*OpIdx*/2, // vindex
        GIR_AddImm8, /*InsnID*/1, /*SubRegIndex*/3,
        GIR_Copy, /*NewInsnID*/1, /*OldInsnID*/0, /*OpIdx*/3, // voffset
        GIR_AddImm8, /*InsnID*/1, /*SubRegIndex*/11,
        GIR_ConstrainOperandRC, /*InsnID*/1, /*Op*/0, GIMT_Encode2(AMDGPU::VReg_64RegClassID),
        GIR_ConstrainOperandRC, /*InsnID*/1, /*Op*/1, GIMT_Encode2(AMDGPU::VGPR_32RegClassID),
        GIR_ConstrainOperandRC, /*InsnID*/1, /*Op*/3, GIMT_Encode2(AMDGPU::VGPR_32RegClassID),
        GIR_BuildMI, /*InsnID*/0, /*Opcode*/GIMT_Encode2(AMDGPU::BUFFER_STORE_FORMAT_D16_XY_VBUFFER_BOTHEN_exact),
        GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/0, // vdata
        GIR_AddSimpleTempRegister, /*InsnID*/0, /*TempRegID*/0,
        GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/1, // rsrc
        GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/0, // soffset
        GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/5, // offset
        GIR_CustomOperandRenderer, /*InsnID*/0, /*OldInsnID*/0, /*OpIdx*/6, /*OperandRenderer*/GIMT_Encode2(GICR_renderExtractCPol), // auxiliary
        GIR_CustomOperandRenderer, /*InsnID*/0, /*OldInsnID*/0, /*OpIdx*/6, /*OperandRenderer*/GIMT_Encode2(GICR_renderExtractSWZ), // auxiliary
        GIR_MergeMemOperands, /*InsnID*/0, /*NumInsns*/1, /*MergeInsnID's*/0,
        GIR_ConstrainSelectedInstOperands, /*InsnID*/0,
        GIR_EraseFromParent, /*InsnID*/0,
        // GIR_Coverage, 4360,
        GIR_Done,
      // Label 7029: @516683
      GIM_Reject,
    // Label 7013: @516684
    GIM_Reject,
    // Label 6970: @516685
    GIM_Try, /*On fail goto*//*Label 7030*/ GIMT_Encode4(517055),
      GIM_CheckType, /*MI*/0, /*Op*/1, /*Type*/GILLT_v4s32,
      GIM_CheckType, /*MI*/0, /*Op*/2, /*Type*/GILLT_s32,
      GIM_CheckType, /*MI*/0, /*Op*/3, /*Type*/GILLT_s32,
      GIM_CheckType, /*MI*/0, /*Op*/4, /*Type*/GILLT_s32,
      GIM_Try, /*On fail goto*//*Label 7031*/ GIMT_Encode4(516788), // Rule ID 4309 //
        GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasUnpackedD16VMem),
        GIM_CheckConstantInt8, /*MI*/0, /*Op*/2, 0,
        GIM_CheckConstantInt8, /*MI*/0, /*Op*/3, 0,
        // MIs[0] offset
        GIM_CheckIsImm, /*MI*/0, /*Op*/5,
        // MIs[0] auxiliary
        GIM_CheckIsImm, /*MI*/0, /*Op*/6,
        // MIs[0] Operand 7
        GIM_CheckLiteralInt, /*MI*/0, /*Op*/7, GIMT_Encode8(0),
        GIM_CheckComplexPattern, /*MI*/0, /*Op*/4, /*Renderer*/GIMT_Encode2(0), GIMT_Encode2(GICP_gi_buf_soffset),
        // (SIbuffer_store_format_d16 v2i32:{ *:[v2i32] }:$vdata, v4i32:{ *:[v4i32] }:$rsrc, 0:{ *:[i32] }, 0:{ *:[i32] }, (BUFSOffset:{ *:[i32] } i32:{ *:[i32] }:$soffset), (timm:{ *:[i32] }):$offset, (timm:{ *:[i32] }):$auxiliary, 0:{ *:[i1] })  =>  (BUFFER_STORE_FORMAT_D16_XY_gfx80_OFFSET_exact anonymous_15036:{ *:[v2i32] }:$vdata, SReg_128:{ *:[v4i32] }:$rsrc, SCSrc_b32:{ *:[i32] }:$soffset, (timm:{ *:[i32] }):$offset, (extract_cpol:{ *:[i32] } ?:{ *:[i32] }:$auxiliary), (extract_swz:{ *:[i1] } ?:{ *:[i32] }:$auxiliary))
        GIR_BuildMI, /*InsnID*/0, /*Opcode*/GIMT_Encode2(AMDGPU::BUFFER_STORE_FORMAT_D16_XY_gfx80_OFFSET_exact),
        GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/0, // vdata
        GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/1, // rsrc
        GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/0, // soffset
        GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/5, // offset
        GIR_CustomOperandRenderer, /*InsnID*/0, /*OldInsnID*/0, /*OpIdx*/6, /*OperandRenderer*/GIMT_Encode2(GICR_renderExtractCPol), // auxiliary
        GIR_CustomOperandRenderer, /*InsnID*/0, /*OldInsnID*/0, /*OpIdx*/6, /*OperandRenderer*/GIMT_Encode2(GICR_renderExtractSWZ), // auxiliary
        GIR_MergeMemOperands, /*InsnID*/0, /*NumInsns*/1, /*MergeInsnID's*/0,
        GIR_ConstrainSelectedInstOperands, /*InsnID*/0,
        GIR_EraseFromParent, /*InsnID*/0,
        // GIR_Coverage, 4309,
        GIR_Done,
      // Label 7031: @516788
      GIM_Try, /*On fail goto*//*Label 7032*/ GIMT_Encode4(516870), // Rule ID 4310 //
        GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasUnpackedD16VMem),
        GIM_CheckConstantInt8, /*MI*/0, /*Op*/2, 0,
        // MIs[0] offset
        GIM_CheckIsImm, /*MI*/0, /*Op*/5,
        // MIs[0] auxiliary
        GIM_CheckIsImm, /*MI*/0, /*Op*/6,
        // MIs[0] Operand 7
        GIM_CheckLiteralInt, /*MI*/0, /*Op*/7, GIMT_Encode8(0),
        GIM_CheckComplexPattern, /*MI*/0, /*Op*/4, /*Renderer*/GIMT_Encode2(0), GIMT_Encode2(GICP_gi_buf_soffset),
        // (SIbuffer_store_format_d16 v2i32:{ *:[v2i32] }:$vdata, v4i32:{ *:[v4i32] }:$rsrc, 0:{ *:[i32] }, i32:{ *:[i32] }:$voffset, (BUFSOffset:{ *:[i32] } i32:{ *:[i32] }:$soffset), (timm:{ *:[i32] }):$offset, (timm:{ *:[i32] }):$auxiliary, 0:{ *:[i1] })  =>  (BUFFER_STORE_FORMAT_D16_XY_gfx80_OFFEN_exact anonymous_15036:{ *:[v2i32] }:$vdata, VGPR_32:{ *:[i32] }:$voffset, SReg_128:{ *:[v4i32] }:$rsrc, SCSrc_b32:{ *:[i32] }:$soffset, (timm:{ *:[i32] }):$offset, (extract_cpol:{ *:[i32] } ?:{ *:[i32] }:$auxiliary), (extract_swz:{ *:[i1] } ?:{ *:[i32] }:$auxiliary))
        GIR_BuildMI, /*InsnID*/0, /*Opcode*/GIMT_Encode2(AMDGPU::BUFFER_STORE_FORMAT_D16_XY_gfx80_OFFEN_exact),
        GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/0, // vdata
        GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/3, // voffset
        GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/1, // rsrc
        GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/0, // soffset
        GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/5, // offset
        GIR_CustomOperandRenderer, /*InsnID*/0, /*OldInsnID*/0, /*OpIdx*/6, /*OperandRenderer*/GIMT_Encode2(GICR_renderExtractCPol), // auxiliary
        GIR_CustomOperandRenderer, /*InsnID*/0, /*OldInsnID*/0, /*OpIdx*/6, /*OperandRenderer*/GIMT_Encode2(GICR_renderExtractSWZ), // auxiliary
        GIR_MergeMemOperands, /*InsnID*/0, /*NumInsns*/1, /*MergeInsnID's*/0,
        GIR_ConstrainSelectedInstOperands, /*InsnID*/0,
        GIR_EraseFromParent, /*InsnID*/0,
        // GIR_Coverage, 4310,
        GIR_Done,
      // Label 7032: @516870
      GIM_Try, /*On fail goto*//*Label 7033*/ GIMT_Encode4(516944), // Rule ID 4311 //
        GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasUnpackedD16VMem),
        GIM_CheckConstantInt8, /*MI*/0, /*Op*/3, 0,
        // MIs[0] offset
        GIM_CheckIsImm, /*MI*/0, /*Op*/5,
        // MIs[0] auxiliary
        GIM_CheckIsImm, /*MI*/0, /*Op*/6,
        // MIs[0] Operand 7
        GIM_CheckIsImm, /*MI*/0, /*Op*/7,
        GIM_CheckComplexPattern, /*MI*/0, /*Op*/4, /*Renderer*/GIMT_Encode2(0), GIMT_Encode2(GICP_gi_buf_soffset),
        // (SIbuffer_store_format_d16 v2i32:{ *:[v2i32] }:$vdata, v4i32:{ *:[v4i32] }:$rsrc, i32:{ *:[i32] }:$vindex, 0:{ *:[i32] }, (BUFSOffset:{ *:[i32] } i32:{ *:[i32] }:$soffset), (timm:{ *:[i32] }):$offset, (timm:{ *:[i32] }):$auxiliary, (timm:{ *:[i1] }))  =>  (BUFFER_STORE_FORMAT_D16_XY_gfx80_IDXEN_exact anonymous_15036:{ *:[v2i32] }:$vdata, VGPR_32:{ *:[i32] }:$vindex, SReg_128:{ *:[v4i32] }:$rsrc, SCSrc_b32:{ *:[i32] }:$soffset, (timm:{ *:[i32] }):$offset, (extract_cpol:{ *:[i32] } ?:{ *:[i32] }:$auxiliary), (extract_swz:{ *:[i1] } ?:{ *:[i32] }:$auxiliary))
        GIR_BuildMI, /*InsnID*/0, /*Opcode*/GIMT_Encode2(AMDGPU::BUFFER_STORE_FORMAT_D16_XY_gfx80_IDXEN_exact),
        GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/0, // vdata
        GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/2, // vindex
        GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/1, // rsrc
        GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/0, // soffset
        GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/5, // offset
        GIR_CustomOperandRenderer, /*InsnID*/0, /*OldInsnID*/0, /*OpIdx*/6, /*OperandRenderer*/GIMT_Encode2(GICR_renderExtractCPol), // auxiliary
        GIR_CustomOperandRenderer, /*InsnID*/0, /*OldInsnID*/0, /*OpIdx*/6, /*OperandRenderer*/GIMT_Encode2(GICR_renderExtractSWZ), // auxiliary
        GIR_MergeMemOperands, /*InsnID*/0, /*NumInsns*/1, /*MergeInsnID's*/0,
        GIR_ConstrainSelectedInstOperands, /*InsnID*/0,
        GIR_EraseFromParent, /*InsnID*/0,
        // GIR_Coverage, 4311,
        GIR_Done,
      // Label 7033: @516944
      GIM_Try, /*On fail goto*//*Label 7034*/ GIMT_Encode4(517054), // Rule ID 4312 //
        GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasUnpackedD16VMem),
        // MIs[0] offset
        GIM_CheckIsImm, /*MI*/0, /*Op*/5,
        // MIs[0] auxiliary
        GIM_CheckIsImm, /*MI*/0, /*Op*/6,
        // MIs[0] Operand 7
        GIM_CheckIsImm, /*MI*/0, /*Op*/7,
        GIM_CheckComplexPattern, /*MI*/0, /*Op*/4, /*Renderer*/GIMT_Encode2(0), GIMT_Encode2(GICP_gi_buf_soffset),
        // (SIbuffer_store_format_d16 v2i32:{ *:[v2i32] }:$vdata, v4i32:{ *:[v4i32] }:$rsrc, i32:{ *:[i32] }:$vindex, i32:{ *:[i32] }:$voffset, (BUFSOffset:{ *:[i32] } i32:{ *:[i32] }:$soffset), (timm:{ *:[i32] }):$offset, (timm:{ *:[i32] }):$auxiliary, (timm:{ *:[i1] }))  =>  (BUFFER_STORE_FORMAT_D16_XY_gfx80_BOTHEN_exact anonymous_15036:{ *:[v2i32] }:$vdata, (REG_SEQUENCE:{ *:[i64] } VReg_64:{ *:[i32] }, VGPR_32:{ *:[i32] }:$vindex, sub0:{ *:[i32] }, VGPR_32:{ *:[i32] }:$voffset, sub1:{ *:[i32] }), SReg_128:{ *:[v4i32] }:$rsrc, SCSrc_b32:{ *:[i32] }:$soffset, (timm:{ *:[i32] }):$offset, (extract_cpol:{ *:[i32] } ?:{ *:[i32] }:$auxiliary), (extract_swz:{ *:[i1] } ?:{ *:[i32] }:$auxiliary))
        GIR_MakeTempReg, /*TempRegID*/0, /*TypeID*/GILLT_s64,
        GIR_BuildMI, /*InsnID*/1, /*Opcode*/GIMT_Encode2(TargetOpcode::REG_SEQUENCE),
        GIR_AddTempRegister, /*InsnID*/1, /*TempRegID*/0, /*TempRegFlags*/GIMT_Encode2(RegState::Define),
        GIR_Copy, /*NewInsnID*/1, /*OldInsnID*/0, /*OpIdx*/2, // vindex
        GIR_AddImm8, /*InsnID*/1, /*SubRegIndex*/3,
        GIR_Copy, /*NewInsnID*/1, /*OldInsnID*/0, /*OpIdx*/3, // voffset
        GIR_AddImm8, /*InsnID*/1, /*SubRegIndex*/11,
        GIR_ConstrainOperandRC, /*InsnID*/1, /*Op*/0, GIMT_Encode2(AMDGPU::VReg_64RegClassID),
        GIR_ConstrainOperandRC, /*InsnID*/1, /*Op*/1, GIMT_Encode2(AMDGPU::VGPR_32RegClassID),
        GIR_ConstrainOperandRC, /*InsnID*/1, /*Op*/3, GIMT_Encode2(AMDGPU::VGPR_32RegClassID),
        GIR_BuildMI, /*InsnID*/0, /*Opcode*/GIMT_Encode2(AMDGPU::BUFFER_STORE_FORMAT_D16_XY_gfx80_BOTHEN_exact),
        GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/0, // vdata
        GIR_AddSimpleTempRegister, /*InsnID*/0, /*TempRegID*/0,
        GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/1, // rsrc
        GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/0, // soffset
        GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/5, // offset
        GIR_CustomOperandRenderer, /*InsnID*/0, /*OldInsnID*/0, /*OpIdx*/6, /*OperandRenderer*/GIMT_Encode2(GICR_renderExtractCPol), // auxiliary
        GIR_CustomOperandRenderer, /*InsnID*/0, /*OldInsnID*/0, /*OpIdx*/6, /*OperandRenderer*/GIMT_Encode2(GICR_renderExtractSWZ), // auxiliary
        GIR_MergeMemOperands, /*InsnID*/0, /*NumInsns*/1, /*MergeInsnID's*/0,
        GIR_ConstrainSelectedInstOperands, /*InsnID*/0,
        GIR_EraseFromParent, /*InsnID*/0,
        // GIR_Coverage, 4312,
        GIR_Done,
      // Label 7034: @517054
      GIM_Reject,
    // Label 7030: @517055
    GIM_Reject,
    // Label 6971: @517056
    GIM_Try, /*On fail goto*//*Label 7035*/ GIMT_Encode4(517426),
      GIM_CheckType, /*MI*/0, /*Op*/1, /*Type*/GILLT_v4s32,
      GIM_CheckType, /*MI*/0, /*Op*/2, /*Type*/GILLT_s32,
      GIM_CheckType, /*MI*/0, /*Op*/3, /*Type*/GILLT_s32,
      GIM_CheckType, /*MI*/0, /*Op*/4, /*Type*/GILLT_s32,
      GIM_Try, /*On fail goto*//*Label 7036*/ GIMT_Encode4(517159), // Rule ID 4313 //
        GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasUnpackedD16VMem),
        GIM_CheckConstantInt8, /*MI*/0, /*Op*/2, 0,
        GIM_CheckConstantInt8, /*MI*/0, /*Op*/3, 0,
        // MIs[0] offset
        GIM_CheckIsImm, /*MI*/0, /*Op*/5,
        // MIs[0] auxiliary
        GIM_CheckIsImm, /*MI*/0, /*Op*/6,
        // MIs[0] Operand 7
        GIM_CheckLiteralInt, /*MI*/0, /*Op*/7, GIMT_Encode8(0),
        GIM_CheckComplexPattern, /*MI*/0, /*Op*/4, /*Renderer*/GIMT_Encode2(0), GIMT_Encode2(GICP_gi_buf_soffset),
        // (SIbuffer_store_format_d16 v3i32:{ *:[v3i32] }:$vdata, v4i32:{ *:[v4i32] }:$rsrc, 0:{ *:[i32] }, 0:{ *:[i32] }, (BUFSOffset:{ *:[i32] } i32:{ *:[i32] }:$soffset), (timm:{ *:[i32] }):$offset, (timm:{ *:[i32] }):$auxiliary, 0:{ *:[i1] })  =>  (BUFFER_STORE_FORMAT_D16_XYZ_gfx80_OFFSET_exact anonymous_15035:{ *:[v3i32] }:$vdata, SReg_128:{ *:[v4i32] }:$rsrc, SCSrc_b32:{ *:[i32] }:$soffset, (timm:{ *:[i32] }):$offset, (extract_cpol:{ *:[i32] } ?:{ *:[i32] }:$auxiliary), (extract_swz:{ *:[i1] } ?:{ *:[i32] }:$auxiliary))
        GIR_BuildMI, /*InsnID*/0, /*Opcode*/GIMT_Encode2(AMDGPU::BUFFER_STORE_FORMAT_D16_XYZ_gfx80_OFFSET_exact),
        GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/0, // vdata
        GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/1, // rsrc
        GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/0, // soffset
        GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/5, // offset
        GIR_CustomOperandRenderer, /*InsnID*/0, /*OldInsnID*/0, /*OpIdx*/6, /*OperandRenderer*/GIMT_Encode2(GICR_renderExtractCPol), // auxiliary
        GIR_CustomOperandRenderer, /*InsnID*/0, /*OldInsnID*/0, /*OpIdx*/6, /*OperandRenderer*/GIMT_Encode2(GICR_renderExtractSWZ), // auxiliary
        GIR_MergeMemOperands, /*InsnID*/0, /*NumInsns*/1, /*MergeInsnID's*/0,
        GIR_ConstrainSelectedInstOperands, /*InsnID*/0,
        GIR_EraseFromParent, /*InsnID*/0,
        // GIR_Coverage, 4313,
        GIR_Done,
      // Label 7036: @517159
      GIM_Try, /*On fail goto*//*Label 7037*/ GIMT_Encode4(517241), // Rule ID 4314 //
        GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasUnpackedD16VMem),
        GIM_CheckConstantInt8, /*MI*/0, /*Op*/2, 0,
        // MIs[0] offset
        GIM_CheckIsImm, /*MI*/0, /*Op*/5,
        // MIs[0] auxiliary
        GIM_CheckIsImm, /*MI*/0, /*Op*/6,
        // MIs[0] Operand 7
        GIM_CheckLiteralInt, /*MI*/0, /*Op*/7, GIMT_Encode8(0),
        GIM_CheckComplexPattern, /*MI*/0, /*Op*/4, /*Renderer*/GIMT_Encode2(0), GIMT_Encode2(GICP_gi_buf_soffset),
        // (SIbuffer_store_format_d16 v3i32:{ *:[v3i32] }:$vdata, v4i32:{ *:[v4i32] }:$rsrc, 0:{ *:[i32] }, i32:{ *:[i32] }:$voffset, (BUFSOffset:{ *:[i32] } i32:{ *:[i32] }:$soffset), (timm:{ *:[i32] }):$offset, (timm:{ *:[i32] }):$auxiliary, 0:{ *:[i1] })  =>  (BUFFER_STORE_FORMAT_D16_XYZ_gfx80_OFFEN_exact anonymous_15035:{ *:[v3i32] }:$vdata, VGPR_32:{ *:[i32] }:$voffset, SReg_128:{ *:[v4i32] }:$rsrc, SCSrc_b32:{ *:[i32] }:$soffset, (timm:{ *:[i32] }):$offset, (extract_cpol:{ *:[i32] } ?:{ *:[i32] }:$auxiliary), (extract_swz:{ *:[i1] } ?:{ *:[i32] }:$auxiliary))
        GIR_BuildMI, /*InsnID*/0, /*Opcode*/GIMT_Encode2(AMDGPU::BUFFER_STORE_FORMAT_D16_XYZ_gfx80_OFFEN_exact),
        GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/0, // vdata
        GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/3, // voffset
        GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/1, // rsrc
        GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/0, // soffset
        GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/5, // offset
        GIR_CustomOperandRenderer, /*InsnID*/0, /*OldInsnID*/0, /*OpIdx*/6, /*OperandRenderer*/GIMT_Encode2(GICR_renderExtractCPol), // auxiliary
        GIR_CustomOperandRenderer, /*InsnID*/0, /*OldInsnID*/0, /*OpIdx*/6, /*OperandRenderer*/GIMT_Encode2(GICR_renderExtractSWZ), // auxiliary
        GIR_MergeMemOperands, /*InsnID*/0, /*NumInsns*/1, /*MergeInsnID's*/0,
        GIR_ConstrainSelectedInstOperands, /*InsnID*/0,
        GIR_EraseFromParent, /*InsnID*/0,
        // GIR_Coverage, 4314,
        GIR_Done,
      // Label 7037: @517241
      GIM_Try, /*On fail goto*//*Label 7038*/ GIMT_Encode4(517315), // Rule ID 4315 //
        GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasUnpackedD16VMem),
        GIM_CheckConstantInt8, /*MI*/0, /*Op*/3, 0,
        // MIs[0] offset
        GIM_CheckIsImm, /*MI*/0, /*Op*/5,
        // MIs[0] auxiliary
        GIM_CheckIsImm, /*MI*/0, /*Op*/6,
        // MIs[0] Operand 7
        GIM_CheckIsImm, /*MI*/0, /*Op*/7,
        GIM_CheckComplexPattern, /*MI*/0, /*Op*/4, /*Renderer*/GIMT_Encode2(0), GIMT_Encode2(GICP_gi_buf_soffset),
        // (SIbuffer_store_format_d16 v3i32:{ *:[v3i32] }:$vdata, v4i32:{ *:[v4i32] }:$rsrc, i32:{ *:[i32] }:$vindex, 0:{ *:[i32] }, (BUFSOffset:{ *:[i32] } i32:{ *:[i32] }:$soffset), (timm:{ *:[i32] }):$offset, (timm:{ *:[i32] }):$auxiliary, (timm:{ *:[i1] }))  =>  (BUFFER_STORE_FORMAT_D16_XYZ_gfx80_IDXEN_exact anonymous_15035:{ *:[v3i32] }:$vdata, VGPR_32:{ *:[i32] }:$vindex, SReg_128:{ *:[v4i32] }:$rsrc, SCSrc_b32:{ *:[i32] }:$soffset, (timm:{ *:[i32] }):$offset, (extract_cpol:{ *:[i32] } ?:{ *:[i32] }:$auxiliary), (extract_swz:{ *:[i1] } ?:{ *:[i32] }:$auxiliary))
        GIR_BuildMI, /*InsnID*/0, /*Opcode*/GIMT_Encode2(AMDGPU::BUFFER_STORE_FORMAT_D16_XYZ_gfx80_IDXEN_exact),
        GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/0, // vdata
        GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/2, // vindex
        GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/1, // rsrc
        GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/0, // soffset
        GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/5, // offset
        GIR_CustomOperandRenderer, /*InsnID*/0, /*OldInsnID*/0, /*OpIdx*/6, /*OperandRenderer*/GIMT_Encode2(GICR_renderExtractCPol), // auxiliary
        GIR_CustomOperandRenderer, /*InsnID*/0, /*OldInsnID*/0, /*OpIdx*/6, /*OperandRenderer*/GIMT_Encode2(GICR_renderExtractSWZ), // auxiliary
        GIR_MergeMemOperands, /*InsnID*/0, /*NumInsns*/1, /*MergeInsnID's*/0,
        GIR_ConstrainSelectedInstOperands, /*InsnID*/0,
        GIR_EraseFromParent, /*InsnID*/0,
        // GIR_Coverage, 4315,
        GIR_Done,
      // Label 7038: @517315
      GIM_Try, /*On fail goto*//*Label 7039*/ GIMT_Encode4(517425), // Rule ID 4316 //
        GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasUnpackedD16VMem),
        // MIs[0] offset
        GIM_CheckIsImm, /*MI*/0, /*Op*/5,
        // MIs[0] auxiliary
        GIM_CheckIsImm, /*MI*/0, /*Op*/6,
        // MIs[0] Operand 7
        GIM_CheckIsImm, /*MI*/0, /*Op*/7,
        GIM_CheckComplexPattern, /*MI*/0, /*Op*/4, /*Renderer*/GIMT_Encode2(0), GIMT_Encode2(GICP_gi_buf_soffset),
        // (SIbuffer_store_format_d16 v3i32:{ *:[v3i32] }:$vdata, v4i32:{ *:[v4i32] }:$rsrc, i32:{ *:[i32] }:$vindex, i32:{ *:[i32] }:$voffset, (BUFSOffset:{ *:[i32] } i32:{ *:[i32] }:$soffset), (timm:{ *:[i32] }):$offset, (timm:{ *:[i32] }):$auxiliary, (timm:{ *:[i1] }))  =>  (BUFFER_STORE_FORMAT_D16_XYZ_gfx80_BOTHEN_exact anonymous_15035:{ *:[v3i32] }:$vdata, (REG_SEQUENCE:{ *:[i64] } VReg_64:{ *:[i32] }, VGPR_32:{ *:[i32] }:$vindex, sub0:{ *:[i32] }, VGPR_32:{ *:[i32] }:$voffset, sub1:{ *:[i32] }), SReg_128:{ *:[v4i32] }:$rsrc, SCSrc_b32:{ *:[i32] }:$soffset, (timm:{ *:[i32] }):$offset, (extract_cpol:{ *:[i32] } ?:{ *:[i32] }:$auxiliary), (extract_swz:{ *:[i1] } ?:{ *:[i32] }:$auxiliary))
        GIR_MakeTempReg, /*TempRegID*/0, /*TypeID*/GILLT_s64,
        GIR_BuildMI, /*InsnID*/1, /*Opcode*/GIMT_Encode2(TargetOpcode::REG_SEQUENCE),
        GIR_AddTempRegister, /*InsnID*/1, /*TempRegID*/0, /*TempRegFlags*/GIMT_Encode2(RegState::Define),
        GIR_Copy, /*NewInsnID*/1, /*OldInsnID*/0, /*OpIdx*/2, // vindex
        GIR_AddImm8, /*InsnID*/1, /*SubRegIndex*/3,
        GIR_Copy, /*NewInsnID*/1, /*OldInsnID*/0, /*OpIdx*/3, // voffset
        GIR_AddImm8, /*InsnID*/1, /*SubRegIndex*/11,
        GIR_ConstrainOperandRC, /*InsnID*/1, /*Op*/0, GIMT_Encode2(AMDGPU::VReg_64RegClassID),
        GIR_ConstrainOperandRC, /*InsnID*/1, /*Op*/1, GIMT_Encode2(AMDGPU::VGPR_32RegClassID),
        GIR_ConstrainOperandRC, /*InsnID*/1, /*Op*/3, GIMT_Encode2(AMDGPU::VGPR_32RegClassID),
        GIR_BuildMI, /*InsnID*/0, /*Opcode*/GIMT_Encode2(AMDGPU::BUFFER_STORE_FORMAT_D16_XYZ_gfx80_BOTHEN_exact),
        GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/0, // vdata
        GIR_AddSimpleTempRegister, /*InsnID*/0, /*TempRegID*/0,
        GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/1, // rsrc
        GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/0, // soffset
        GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/5, // offset
        GIR_CustomOperandRenderer, /*InsnID*/0, /*OldInsnID*/0, /*OpIdx*/6, /*OperandRenderer*/GIMT_Encode2(GICR_renderExtractCPol), // auxiliary
        GIR_CustomOperandRenderer, /*InsnID*/0, /*OldInsnID*/0, /*OpIdx*/6, /*OperandRenderer*/GIMT_Encode2(GICR_renderExtractSWZ), // auxiliary
        GIR_MergeMemOperands, /*InsnID*/0, /*NumInsns*/1, /*MergeInsnID's*/0,
        GIR_ConstrainSelectedInstOperands, /*InsnID*/0,
        GIR_EraseFromParent, /*InsnID*/0,
        // GIR_Coverage, 4316,
        GIR_Done,
      // Label 7039: @517425
      GIM_Reject,
    // Label 7035: @517426
    GIM_Reject,
    // Label 6972: @517427
    GIM_Try, /*On fail goto*//*Label 7040*/ GIMT_Encode4(518841),
      GIM_CheckType, /*MI*/0, /*Op*/1, /*Type*/GILLT_v4s32,
      GIM_CheckType, /*MI*/0, /*Op*/2, /*Type*/GILLT_s32,
      GIM_CheckType, /*MI*/0, /*Op*/3, /*Type*/GILLT_s32,
      GIM_CheckType, /*MI*/0, /*Op*/4, /*Type*/GILLT_s32,
      GIM_Try, /*On fail goto*//*Label 7041*/ GIMT_Encode4(517530), // Rule ID 4377 //
        GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasPackedD16VMem_HasUnrestrictedSOffset),
        GIM_CheckConstantInt8, /*MI*/0, /*Op*/2, 0,
        GIM_CheckConstantInt8, /*MI*/0, /*Op*/3, 0,
        // MIs[0] offset
        GIM_CheckIsImm, /*MI*/0, /*Op*/5,
        // MIs[0] auxiliary
        GIM_CheckIsImm, /*MI*/0, /*Op*/6,
        // MIs[0] Operand 7
        GIM_CheckLiteralInt, /*MI*/0, /*Op*/7, GIMT_Encode8(0),
        GIM_CheckComplexPattern, /*MI*/0, /*Op*/4, /*Renderer*/GIMT_Encode2(0), GIMT_Encode2(GICP_gi_buf_soffset),
        // (SIbuffer_store_format_d16 v4f16:{ *:[v4f16] }:$vdata, v4i32:{ *:[v4i32] }:$rsrc, 0:{ *:[i32] }, 0:{ *:[i32] }, (BUFSOffset:{ *:[i32] } i32:{ *:[i32] }:$soffset), (timm:{ *:[i32] }):$offset, (timm:{ *:[i32] }):$auxiliary, 0:{ *:[i1] })  =>  (BUFFER_STORE_FORMAT_D16_XYZW_OFFSET_exact anonymous_15036:{ *:[v4f16] }:$vdata, SReg_128:{ *:[v4i32] }:$rsrc, SCSrc_b32:{ *:[i32] }:$soffset, (timm:{ *:[i32] }):$offset, (extract_cpol:{ *:[i32] } ?:{ *:[i32] }:$auxiliary), (extract_swz:{ *:[i1] } ?:{ *:[i32] }:$auxiliary))
        GIR_BuildMI, /*InsnID*/0, /*Opcode*/GIMT_Encode2(AMDGPU::BUFFER_STORE_FORMAT_D16_XYZW_OFFSET_exact),
        GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/0, // vdata
        GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/1, // rsrc
        GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/0, // soffset
        GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/5, // offset
        GIR_CustomOperandRenderer, /*InsnID*/0, /*OldInsnID*/0, /*OpIdx*/6, /*OperandRenderer*/GIMT_Encode2(GICR_renderExtractCPol), // auxiliary
        GIR_CustomOperandRenderer, /*InsnID*/0, /*OldInsnID*/0, /*OpIdx*/6, /*OperandRenderer*/GIMT_Encode2(GICR_renderExtractSWZ), // auxiliary
        GIR_MergeMemOperands, /*InsnID*/0, /*NumInsns*/1, /*MergeInsnID's*/0,
        GIR_ConstrainSelectedInstOperands, /*InsnID*/0,
        GIR_EraseFromParent, /*InsnID*/0,
        // GIR_Coverage, 4377,
        GIR_Done,
      // Label 7041: @517530
      GIM_Try, /*On fail goto*//*Label 7042*/ GIMT_Encode4(517612), // Rule ID 4381 //
        GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasPackedD16VMem),
        GIM_CheckConstantInt8, /*MI*/0, /*Op*/2, 0,
        GIM_CheckConstantInt8, /*MI*/0, /*Op*/3, 0,
        // MIs[0] offset
        GIM_CheckIsImm, /*MI*/0, /*Op*/5,
        // MIs[0] auxiliary
        GIM_CheckIsImm, /*MI*/0, /*Op*/6,
        // MIs[0] Operand 7
        GIM_CheckLiteralInt, /*MI*/0, /*Op*/7, GIMT_Encode8(0),
        GIM_CheckComplexPattern, /*MI*/0, /*Op*/4, /*Renderer*/GIMT_Encode2(0), GIMT_Encode2(GICP_gi_buf_soffset),
        // (SIbuffer_store_format_d16 v4f16:{ *:[v4f16] }:$vdata, v4i32:{ *:[v4i32] }:$rsrc, 0:{ *:[i32] }, 0:{ *:[i32] }, (BUFSOffset:{ *:[i32] } i32:{ *:[i32] }:$soffset), (timm:{ *:[i32] }):$offset, (timm:{ *:[i32] }):$auxiliary, 0:{ *:[i1] })  =>  (BUFFER_STORE_FORMAT_D16_XYZW_VBUFFER_OFFSET_exact anonymous_15036:{ *:[v4f16] }:$vdata, SReg_128:{ *:[v4i32] }:$rsrc, SCSrc_b32:{ *:[i32] }:$soffset, (timm:{ *:[i32] }):$offset, (extract_cpol:{ *:[i32] } ?:{ *:[i32] }:$auxiliary), (extract_swz:{ *:[i1] } ?:{ *:[i32] }:$auxiliary))
        GIR_BuildMI, /*InsnID*/0, /*Opcode*/GIMT_Encode2(AMDGPU::BUFFER_STORE_FORMAT_D16_XYZW_VBUFFER_OFFSET_exact),
        GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/0, // vdata
        GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/1, // rsrc
        GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/0, // soffset
        GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/5, // offset
        GIR_CustomOperandRenderer, /*InsnID*/0, /*OldInsnID*/0, /*OpIdx*/6, /*OperandRenderer*/GIMT_Encode2(GICR_renderExtractCPol), // auxiliary
        GIR_CustomOperandRenderer, /*InsnID*/0, /*OldInsnID*/0, /*OpIdx*/6, /*OperandRenderer*/GIMT_Encode2(GICR_renderExtractSWZ), // auxiliary
        GIR_MergeMemOperands, /*InsnID*/0, /*NumInsns*/1, /*MergeInsnID's*/0,
        GIR_ConstrainSelectedInstOperands, /*InsnID*/0,
        GIR_EraseFromParent, /*InsnID*/0,
        // GIR_Coverage, 4381,
        GIR_Done,
      // Label 7042: @517612
      GIM_Try, /*On fail goto*//*Label 7043*/ GIMT_Encode4(517694), // Rule ID 4385 //
        GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasPackedD16VMem_HasUnrestrictedSOffset),
        GIM_CheckConstantInt8, /*MI*/0, /*Op*/2, 0,
        GIM_CheckConstantInt8, /*MI*/0, /*Op*/3, 0,
        // MIs[0] offset
        GIM_CheckIsImm, /*MI*/0, /*Op*/5,
        // MIs[0] auxiliary
        GIM_CheckIsImm, /*MI*/0, /*Op*/6,
        // MIs[0] Operand 7
        GIM_CheckLiteralInt, /*MI*/0, /*Op*/7, GIMT_Encode8(0),
        GIM_CheckComplexPattern, /*MI*/0, /*Op*/4, /*Renderer*/GIMT_Encode2(0), GIMT_Encode2(GICP_gi_buf_soffset),
        // (SIbuffer_store_format_d16 v4i16:{ *:[v4i16] }:$vdata, v4i32:{ *:[v4i32] }:$rsrc, 0:{ *:[i32] }, 0:{ *:[i32] }, (BUFSOffset:{ *:[i32] } i32:{ *:[i32] }:$soffset), (timm:{ *:[i32] }):$offset, (timm:{ *:[i32] }):$auxiliary, 0:{ *:[i1] })  =>  (BUFFER_STORE_FORMAT_D16_XYZW_OFFSET_exact anonymous_15036:{ *:[v4i16] }:$vdata, SReg_128:{ *:[v4i32] }:$rsrc, SCSrc_b32:{ *:[i32] }:$soffset, (timm:{ *:[i32] }):$offset, (extract_cpol:{ *:[i32] } ?:{ *:[i32] }:$auxiliary), (extract_swz:{ *:[i1] } ?:{ *:[i32] }:$auxiliary))
        GIR_BuildMI, /*InsnID*/0, /*Opcode*/GIMT_Encode2(AMDGPU::BUFFER_STORE_FORMAT_D16_XYZW_OFFSET_exact),
        GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/0, // vdata
        GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/1, // rsrc
        GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/0, // soffset
        GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/5, // offset
        GIR_CustomOperandRenderer, /*InsnID*/0, /*OldInsnID*/0, /*OpIdx*/6, /*OperandRenderer*/GIMT_Encode2(GICR_renderExtractCPol), // auxiliary
        GIR_CustomOperandRenderer, /*InsnID*/0, /*OldInsnID*/0, /*OpIdx*/6, /*OperandRenderer*/GIMT_Encode2(GICR_renderExtractSWZ), // auxiliary
        GIR_MergeMemOperands, /*InsnID*/0, /*NumInsns*/1, /*MergeInsnID's*/0,
        GIR_ConstrainSelectedInstOperands, /*InsnID*/0,
        GIR_EraseFromParent, /*InsnID*/0,
        // GIR_Coverage, 4385,
        GIR_Done,
      // Label 7043: @517694
      GIM_Try, /*On fail goto*//*Label 7044*/ GIMT_Encode4(517776), // Rule ID 4389 //
        GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasPackedD16VMem),
        GIM_CheckConstantInt8, /*MI*/0, /*Op*/2, 0,
        GIM_CheckConstantInt8, /*MI*/0, /*Op*/3, 0,
        // MIs[0] offset
        GIM_CheckIsImm, /*MI*/0, /*Op*/5,
        // MIs[0] auxiliary
        GIM_CheckIsImm, /*MI*/0, /*Op*/6,
        // MIs[0] Operand 7
        GIM_CheckLiteralInt, /*MI*/0, /*Op*/7, GIMT_Encode8(0),
        GIM_CheckComplexPattern, /*MI*/0, /*Op*/4, /*Renderer*/GIMT_Encode2(0), GIMT_Encode2(GICP_gi_buf_soffset),
        // (SIbuffer_store_format_d16 v4i16:{ *:[v4i16] }:$vdata, v4i32:{ *:[v4i32] }:$rsrc, 0:{ *:[i32] }, 0:{ *:[i32] }, (BUFSOffset:{ *:[i32] } i32:{ *:[i32] }:$soffset), (timm:{ *:[i32] }):$offset, (timm:{ *:[i32] }):$auxiliary, 0:{ *:[i1] })  =>  (BUFFER_STORE_FORMAT_D16_XYZW_VBUFFER_OFFSET_exact anonymous_15036:{ *:[v4i16] }:$vdata, SReg_128:{ *:[v4i32] }:$rsrc, SCSrc_b32:{ *:[i32] }:$soffset, (timm:{ *:[i32] }):$offset, (extract_cpol:{ *:[i32] } ?:{ *:[i32] }:$auxiliary), (extract_swz:{ *:[i1] } ?:{ *:[i32] }:$auxiliary))
        GIR_BuildMI, /*InsnID*/0, /*Opcode*/GIMT_Encode2(AMDGPU::BUFFER_STORE_FORMAT_D16_XYZW_VBUFFER_OFFSET_exact),
        GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/0, // vdata
        GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/1, // rsrc
        GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/0, // soffset
        GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/5, // offset
        GIR_CustomOperandRenderer, /*InsnID*/0, /*OldInsnID*/0, /*OpIdx*/6, /*OperandRenderer*/GIMT_Encode2(GICR_renderExtractCPol), // auxiliary
        GIR_CustomOperandRenderer, /*InsnID*/0, /*OldInsnID*/0, /*OpIdx*/6, /*OperandRenderer*/GIMT_Encode2(GICR_renderExtractSWZ), // auxiliary
        GIR_MergeMemOperands, /*InsnID*/0, /*NumInsns*/1, /*MergeInsnID's*/0,
        GIR_ConstrainSelectedInstOperands, /*InsnID*/0,
        GIR_EraseFromParent, /*InsnID*/0,
        // GIR_Coverage, 4389,
        GIR_Done,
      // Label 7044: @517776
      GIM_Try, /*On fail goto*//*Label 7045*/ GIMT_Encode4(517858), // Rule ID 4378 //
        GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasPackedD16VMem_HasUnrestrictedSOffset),
        GIM_CheckConstantInt8, /*MI*/0, /*Op*/2, 0,
        // MIs[0] offset
        GIM_CheckIsImm, /*MI*/0, /*Op*/5,
        // MIs[0] auxiliary
        GIM_CheckIsImm, /*MI*/0, /*Op*/6,
        // MIs[0] Operand 7
        GIM_CheckLiteralInt, /*MI*/0, /*Op*/7, GIMT_Encode8(0),
        GIM_CheckComplexPattern, /*MI*/0, /*Op*/4, /*Renderer*/GIMT_Encode2(0), GIMT_Encode2(GICP_gi_buf_soffset),
        // (SIbuffer_store_format_d16 v4f16:{ *:[v4f16] }:$vdata, v4i32:{ *:[v4i32] }:$rsrc, 0:{ *:[i32] }, i32:{ *:[i32] }:$voffset, (BUFSOffset:{ *:[i32] } i32:{ *:[i32] }:$soffset), (timm:{ *:[i32] }):$offset, (timm:{ *:[i32] }):$auxiliary, 0:{ *:[i1] })  =>  (BUFFER_STORE_FORMAT_D16_XYZW_OFFEN_exact anonymous_15036:{ *:[v4f16] }:$vdata, VGPR_32:{ *:[i32] }:$voffset, SReg_128:{ *:[v4i32] }:$rsrc, SCSrc_b32:{ *:[i32] }:$soffset, (timm:{ *:[i32] }):$offset, (extract_cpol:{ *:[i32] } ?:{ *:[i32] }:$auxiliary), (extract_swz:{ *:[i1] } ?:{ *:[i32] }:$auxiliary))
        GIR_BuildMI, /*InsnID*/0, /*Opcode*/GIMT_Encode2(AMDGPU::BUFFER_STORE_FORMAT_D16_XYZW_OFFEN_exact),
        GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/0, // vdata
        GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/3, // voffset
        GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/1, // rsrc
        GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/0, // soffset
        GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/5, // offset
        GIR_CustomOperandRenderer, /*InsnID*/0, /*OldInsnID*/0, /*OpIdx*/6, /*OperandRenderer*/GIMT_Encode2(GICR_renderExtractCPol), // auxiliary
        GIR_CustomOperandRenderer, /*InsnID*/0, /*OldInsnID*/0, /*OpIdx*/6, /*OperandRenderer*/GIMT_Encode2(GICR_renderExtractSWZ), // auxiliary
        GIR_MergeMemOperands, /*InsnID*/0, /*NumInsns*/1, /*MergeInsnID's*/0,
        GIR_ConstrainSelectedInstOperands, /*InsnID*/0,
        GIR_EraseFromParent, /*InsnID*/0,
        // GIR_Coverage, 4378,
        GIR_Done,
      // Label 7045: @517858
      GIM_Try, /*On fail goto*//*Label 7046*/ GIMT_Encode4(517940), // Rule ID 4382 //
        GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasPackedD16VMem),
        GIM_CheckConstantInt8, /*MI*/0, /*Op*/2, 0,
        // MIs[0] offset
        GIM_CheckIsImm, /*MI*/0, /*Op*/5,
        // MIs[0] auxiliary
        GIM_CheckIsImm, /*MI*/0, /*Op*/6,
        // MIs[0] Operand 7
        GIM_CheckLiteralInt, /*MI*/0, /*Op*/7, GIMT_Encode8(0),
        GIM_CheckComplexPattern, /*MI*/0, /*Op*/4, /*Renderer*/GIMT_Encode2(0), GIMT_Encode2(GICP_gi_buf_soffset),
        // (SIbuffer_store_format_d16 v4f16:{ *:[v4f16] }:$vdata, v4i32:{ *:[v4i32] }:$rsrc, 0:{ *:[i32] }, i32:{ *:[i32] }:$voffset, (BUFSOffset:{ *:[i32] } i32:{ *:[i32] }:$soffset), (timm:{ *:[i32] }):$offset, (timm:{ *:[i32] }):$auxiliary, 0:{ *:[i1] })  =>  (BUFFER_STORE_FORMAT_D16_XYZW_VBUFFER_OFFEN_exact anonymous_15036:{ *:[v4f16] }:$vdata, VGPR_32:{ *:[i32] }:$voffset, SReg_128:{ *:[v4i32] }:$rsrc, SCSrc_b32:{ *:[i32] }:$soffset, (timm:{ *:[i32] }):$offset, (extract_cpol:{ *:[i32] } ?:{ *:[i32] }:$auxiliary), (extract_swz:{ *:[i1] } ?:{ *:[i32] }:$auxiliary))
        GIR_BuildMI, /*InsnID*/0, /*Opcode*/GIMT_Encode2(AMDGPU::BUFFER_STORE_FORMAT_D16_XYZW_VBUFFER_OFFEN_exact),
        GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/0, // vdata
        GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/3, // voffset
        GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/1, // rsrc
        GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/0, // soffset
        GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/5, // offset
        GIR_CustomOperandRenderer, /*InsnID*/0, /*OldInsnID*/0, /*OpIdx*/6, /*OperandRenderer*/GIMT_Encode2(GICR_renderExtractCPol), // auxiliary
        GIR_CustomOperandRenderer, /*InsnID*/0, /*OldInsnID*/0, /*OpIdx*/6, /*OperandRenderer*/GIMT_Encode2(GICR_renderExtractSWZ), // auxiliary
        GIR_MergeMemOperands, /*InsnID*/0, /*NumInsns*/1, /*MergeInsnID's*/0,
        GIR_ConstrainSelectedInstOperands, /*InsnID*/0,
        GIR_EraseFromParent, /*InsnID*/0,
        // GIR_Coverage, 4382,
        GIR_Done,
      // Label 7046: @517940
      GIM_Try, /*On fail goto*//*Label 7047*/ GIMT_Encode4(518022), // Rule ID 4386 //
        GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasPackedD16VMem_HasUnrestrictedSOffset),
        GIM_CheckConstantInt8, /*MI*/0, /*Op*/2, 0,
        // MIs[0] offset
        GIM_CheckIsImm, /*MI*/0, /*Op*/5,
        // MIs[0] auxiliary
        GIM_CheckIsImm, /*MI*/0, /*Op*/6,
        // MIs[0] Operand 7
        GIM_CheckLiteralInt, /*MI*/0, /*Op*/7, GIMT_Encode8(0),
        GIM_CheckComplexPattern, /*MI*/0, /*Op*/4, /*Renderer*/GIMT_Encode2(0), GIMT_Encode2(GICP_gi_buf_soffset),
        // (SIbuffer_store_format_d16 v4i16:{ *:[v4i16] }:$vdata, v4i32:{ *:[v4i32] }:$rsrc, 0:{ *:[i32] }, i32:{ *:[i32] }:$voffset, (BUFSOffset:{ *:[i32] } i32:{ *:[i32] }:$soffset), (timm:{ *:[i32] }):$offset, (timm:{ *:[i32] }):$auxiliary, 0:{ *:[i1] })  =>  (BUFFER_STORE_FORMAT_D16_XYZW_OFFEN_exact anonymous_15036:{ *:[v4i16] }:$vdata, VGPR_32:{ *:[i32] }:$voffset, SReg_128:{ *:[v4i32] }:$rsrc, SCSrc_b32:{ *:[i32] }:$soffset, (timm:{ *:[i32] }):$offset, (extract_cpol:{ *:[i32] } ?:{ *:[i32] }:$auxiliary), (extract_swz:{ *:[i1] } ?:{ *:[i32] }:$auxiliary))
        GIR_BuildMI, /*InsnID*/0, /*Opcode*/GIMT_Encode2(AMDGPU::BUFFER_STORE_FORMAT_D16_XYZW_OFFEN_exact),
        GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/0, // vdata
        GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/3, // voffset
        GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/1, // rsrc
        GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/0, // soffset
        GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/5, // offset
        GIR_CustomOperandRenderer, /*InsnID*/0, /*OldInsnID*/0, /*OpIdx*/6, /*OperandRenderer*/GIMT_Encode2(GICR_renderExtractCPol), // auxiliary
        GIR_CustomOperandRenderer, /*InsnID*/0, /*OldInsnID*/0, /*OpIdx*/6, /*OperandRenderer*/GIMT_Encode2(GICR_renderExtractSWZ), // auxiliary
        GIR_MergeMemOperands, /*InsnID*/0, /*NumInsns*/1, /*MergeInsnID's*/0,
        GIR_ConstrainSelectedInstOperands, /*InsnID*/0,
        GIR_EraseFromParent, /*InsnID*/0,
        // GIR_Coverage, 4386,
        GIR_Done,
      // Label 7047: @518022
      GIM_Try, /*On fail goto*//*Label 7048*/ GIMT_Encode4(518104), // Rule ID 4390 //
        GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasPackedD16VMem),
        GIM_CheckConstantInt8, /*MI*/0, /*Op*/2, 0,
        // MIs[0] offset
        GIM_CheckIsImm, /*MI*/0, /*Op*/5,
        // MIs[0] auxiliary
        GIM_CheckIsImm, /*MI*/0, /*Op*/6,
        // MIs[0] Operand 7
        GIM_CheckLiteralInt, /*MI*/0, /*Op*/7, GIMT_Encode8(0),
        GIM_CheckComplexPattern, /*MI*/0, /*Op*/4, /*Renderer*/GIMT_Encode2(0), GIMT_Encode2(GICP_gi_buf_soffset),
        // (SIbuffer_store_format_d16 v4i16:{ *:[v4i16] }:$vdata, v4i32:{ *:[v4i32] }:$rsrc, 0:{ *:[i32] }, i32:{ *:[i32] }:$voffset, (BUFSOffset:{ *:[i32] } i32:{ *:[i32] }:$soffset), (timm:{ *:[i32] }):$offset, (timm:{ *:[i32] }):$auxiliary, 0:{ *:[i1] })  =>  (BUFFER_STORE_FORMAT_D16_XYZW_VBUFFER_OFFEN_exact anonymous_15036:{ *:[v4i16] }:$vdata, VGPR_32:{ *:[i32] }:$voffset, SReg_128:{ *:[v4i32] }:$rsrc, SCSrc_b32:{ *:[i32] }:$soffset, (timm:{ *:[i32] }):$offset, (extract_cpol:{ *:[i32] } ?:{ *:[i32] }:$auxiliary), (extract_swz:{ *:[i1] } ?:{ *:[i32] }:$auxiliary))
        GIR_BuildMI, /*InsnID*/0, /*Opcode*/GIMT_Encode2(AMDGPU::BUFFER_STORE_FORMAT_D16_XYZW_VBUFFER_OFFEN_exact),
        GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/0, // vdata
        GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/3, // voffset
        GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/1, // rsrc
        GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/0, // soffset
        GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/5, // offset
        GIR_CustomOperandRenderer, /*InsnID*/0, /*OldInsnID*/0, /*OpIdx*/6, /*OperandRenderer*/GIMT_Encode2(GICR_renderExtractCPol), // auxiliary
        GIR_CustomOperandRenderer, /*InsnID*/0, /*OldInsnID*/0, /*OpIdx*/6, /*OperandRenderer*/GIMT_Encode2(GICR_renderExtractSWZ), // auxiliary
        GIR_MergeMemOperands, /*InsnID*/0, /*NumInsns*/1, /*MergeInsnID's*/0,
        GIR_ConstrainSelectedInstOperands, /*InsnID*/0,
        GIR_EraseFromParent, /*InsnID*/0,
        // GIR_Coverage, 4390,
        GIR_Done,
      // Label 7048: @518104
      GIM_Try, /*On fail goto*//*Label 7049*/ GIMT_Encode4(518178), // Rule ID 4379 //
        GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasPackedD16VMem_HasUnrestrictedSOffset),
        GIM_CheckConstantInt8, /*MI*/0, /*Op*/3, 0,
        // MIs[0] offset
        GIM_CheckIsImm, /*MI*/0, /*Op*/5,
        // MIs[0] auxiliary
        GIM_CheckIsImm, /*MI*/0, /*Op*/6,
        // MIs[0] Operand 7
        GIM_CheckIsImm, /*MI*/0, /*Op*/7,
        GIM_CheckComplexPattern, /*MI*/0, /*Op*/4, /*Renderer*/GIMT_Encode2(0), GIMT_Encode2(GICP_gi_buf_soffset),
        // (SIbuffer_store_format_d16 v4f16:{ *:[v4f16] }:$vdata, v4i32:{ *:[v4i32] }:$rsrc, i32:{ *:[i32] }:$vindex, 0:{ *:[i32] }, (BUFSOffset:{ *:[i32] } i32:{ *:[i32] }:$soffset), (timm:{ *:[i32] }):$offset, (timm:{ *:[i32] }):$auxiliary, (timm:{ *:[i1] }))  =>  (BUFFER_STORE_FORMAT_D16_XYZW_IDXEN_exact anonymous_15036:{ *:[v4f16] }:$vdata, VGPR_32:{ *:[i32] }:$vindex, SReg_128:{ *:[v4i32] }:$rsrc, SCSrc_b32:{ *:[i32] }:$soffset, (timm:{ *:[i32] }):$offset, (extract_cpol:{ *:[i32] } ?:{ *:[i32] }:$auxiliary), (extract_swz:{ *:[i1] } ?:{ *:[i32] }:$auxiliary))
        GIR_BuildMI, /*InsnID*/0, /*Opcode*/GIMT_Encode2(AMDGPU::BUFFER_STORE_FORMAT_D16_XYZW_IDXEN_exact),
        GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/0, // vdata
        GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/2, // vindex
        GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/1, // rsrc
        GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/0, // soffset
        GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/5, // offset
        GIR_CustomOperandRenderer, /*InsnID*/0, /*OldInsnID*/0, /*OpIdx*/6, /*OperandRenderer*/GIMT_Encode2(GICR_renderExtractCPol), // auxiliary
        GIR_CustomOperandRenderer, /*InsnID*/0, /*OldInsnID*/0, /*OpIdx*/6, /*OperandRenderer*/GIMT_Encode2(GICR_renderExtractSWZ), // auxiliary
        GIR_MergeMemOperands, /*InsnID*/0, /*NumInsns*/1, /*MergeInsnID's*/0,
        GIR_ConstrainSelectedInstOperands, /*InsnID*/0,
        GIR_EraseFromParent, /*InsnID*/0,
        // GIR_Coverage, 4379,
        GIR_Done,
      // Label 7049: @518178
      GIM_Try, /*On fail goto*//*Label 7050*/ GIMT_Encode4(518252), // Rule ID 4383 //
        GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasPackedD16VMem),
        GIM_CheckConstantInt8, /*MI*/0, /*Op*/3, 0,
        // MIs[0] offset
        GIM_CheckIsImm, /*MI*/0, /*Op*/5,
        // MIs[0] auxiliary
        GIM_CheckIsImm, /*MI*/0, /*Op*/6,
        // MIs[0] Operand 7
        GIM_CheckIsImm, /*MI*/0, /*Op*/7,
        GIM_CheckComplexPattern, /*MI*/0, /*Op*/4, /*Renderer*/GIMT_Encode2(0), GIMT_Encode2(GICP_gi_buf_soffset),
        // (SIbuffer_store_format_d16 v4f16:{ *:[v4f16] }:$vdata, v4i32:{ *:[v4i32] }:$rsrc, i32:{ *:[i32] }:$vindex, 0:{ *:[i32] }, (BUFSOffset:{ *:[i32] } i32:{ *:[i32] }:$soffset), (timm:{ *:[i32] }):$offset, (timm:{ *:[i32] }):$auxiliary, (timm:{ *:[i1] }))  =>  (BUFFER_STORE_FORMAT_D16_XYZW_VBUFFER_IDXEN_exact anonymous_15036:{ *:[v4f16] }:$vdata, VGPR_32:{ *:[i32] }:$vindex, SReg_128:{ *:[v4i32] }:$rsrc, SCSrc_b32:{ *:[i32] }:$soffset, (timm:{ *:[i32] }):$offset, (extract_cpol:{ *:[i32] } ?:{ *:[i32] }:$auxiliary), (extract_swz:{ *:[i1] } ?:{ *:[i32] }:$auxiliary))
        GIR_BuildMI, /*InsnID*/0, /*Opcode*/GIMT_Encode2(AMDGPU::BUFFER_STORE_FORMAT_D16_XYZW_VBUFFER_IDXEN_exact),
        GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/0, // vdata
        GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/2, // vindex
        GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/1, // rsrc
        GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/0, // soffset
        GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/5, // offset
        GIR_CustomOperandRenderer, /*InsnID*/0, /*OldInsnID*/0, /*OpIdx*/6, /*OperandRenderer*/GIMT_Encode2(GICR_renderExtractCPol), // auxiliary
        GIR_CustomOperandRenderer, /*InsnID*/0, /*OldInsnID*/0, /*OpIdx*/6, /*OperandRenderer*/GIMT_Encode2(GICR_renderExtractSWZ), // auxiliary
        GIR_MergeMemOperands, /*InsnID*/0, /*NumInsns*/1, /*MergeInsnID's*/0,
        GIR_ConstrainSelectedInstOperands, /*InsnID*/0,
        GIR_EraseFromParent, /*InsnID*/0,
        // GIR_Coverage, 4383,
        GIR_Done,
      // Label 7050: @518252
      GIM_Try, /*On fail goto*//*Label 7051*/ GIMT_Encode4(518326), // Rule ID 4387 //
        GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasPackedD16VMem_HasUnrestrictedSOffset),
        GIM_CheckConstantInt8, /*MI*/0, /*Op*/3, 0,
        // MIs[0] offset
        GIM_CheckIsImm, /*MI*/0, /*Op*/5,
        // MIs[0] auxiliary
        GIM_CheckIsImm, /*MI*/0, /*Op*/6,
        // MIs[0] Operand 7
        GIM_CheckIsImm, /*MI*/0, /*Op*/7,
        GIM_CheckComplexPattern, /*MI*/0, /*Op*/4, /*Renderer*/GIMT_Encode2(0), GIMT_Encode2(GICP_gi_buf_soffset),
        // (SIbuffer_store_format_d16 v4i16:{ *:[v4i16] }:$vdata, v4i32:{ *:[v4i32] }:$rsrc, i32:{ *:[i32] }:$vindex, 0:{ *:[i32] }, (BUFSOffset:{ *:[i32] } i32:{ *:[i32] }:$soffset), (timm:{ *:[i32] }):$offset, (timm:{ *:[i32] }):$auxiliary, (timm:{ *:[i1] }))  =>  (BUFFER_STORE_FORMAT_D16_XYZW_IDXEN_exact anonymous_15036:{ *:[v4i16] }:$vdata, VGPR_32:{ *:[i32] }:$vindex, SReg_128:{ *:[v4i32] }:$rsrc, SCSrc_b32:{ *:[i32] }:$soffset, (timm:{ *:[i32] }):$offset, (extract_cpol:{ *:[i32] } ?:{ *:[i32] }:$auxiliary), (extract_swz:{ *:[i1] } ?:{ *:[i32] }:$auxiliary))
        GIR_BuildMI, /*InsnID*/0, /*Opcode*/GIMT_Encode2(AMDGPU::BUFFER_STORE_FORMAT_D16_XYZW_IDXEN_exact),
        GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/0, // vdata
        GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/2, // vindex
        GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/1, // rsrc
        GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/0, // soffset
        GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/5, // offset
        GIR_CustomOperandRenderer, /*InsnID*/0, /*OldInsnID*/0, /*OpIdx*/6, /*OperandRenderer*/GIMT_Encode2(GICR_renderExtractCPol), // auxiliary
        GIR_CustomOperandRenderer, /*InsnID*/0, /*OldInsnID*/0, /*OpIdx*/6, /*OperandRenderer*/GIMT_Encode2(GICR_renderExtractSWZ), // auxiliary
        GIR_MergeMemOperands, /*InsnID*/0, /*NumInsns*/1, /*MergeInsnID's*/0,
        GIR_ConstrainSelectedInstOperands, /*InsnID*/0,
        GIR_EraseFromParent, /*InsnID*/0,
        // GIR_Coverage, 4387,
        GIR_Done,
      // Label 7051: @518326
      GIM_Try, /*On fail goto*//*Label 7052*/ GIMT_Encode4(518400), // Rule ID 4391 //
        GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasPackedD16VMem),
        GIM_CheckConstantInt8, /*MI*/0, /*Op*/3, 0,
        // MIs[0] offset
        GIM_CheckIsImm, /*MI*/0, /*Op*/5,
        // MIs[0] auxiliary
        GIM_CheckIsImm, /*MI*/0, /*Op*/6,
        // MIs[0] Operand 7
        GIM_CheckIsImm, /*MI*/0, /*Op*/7,
        GIM_CheckComplexPattern, /*MI*/0, /*Op*/4, /*Renderer*/GIMT_Encode2(0), GIMT_Encode2(GICP_gi_buf_soffset),
        // (SIbuffer_store_format_d16 v4i16:{ *:[v4i16] }:$vdata, v4i32:{ *:[v4i32] }:$rsrc, i32:{ *:[i32] }:$vindex, 0:{ *:[i32] }, (BUFSOffset:{ *:[i32] } i32:{ *:[i32] }:$soffset), (timm:{ *:[i32] }):$offset, (timm:{ *:[i32] }):$auxiliary, (timm:{ *:[i1] }))  =>  (BUFFER_STORE_FORMAT_D16_XYZW_VBUFFER_IDXEN_exact anonymous_15036:{ *:[v4i16] }:$vdata, VGPR_32:{ *:[i32] }:$vindex, SReg_128:{ *:[v4i32] }:$rsrc, SCSrc_b32:{ *:[i32] }:$soffset, (timm:{ *:[i32] }):$offset, (extract_cpol:{ *:[i32] } ?:{ *:[i32] }:$auxiliary), (extract_swz:{ *:[i1] } ?:{ *:[i32] }:$auxiliary))
        GIR_BuildMI, /*InsnID*/0, /*Opcode*/GIMT_Encode2(AMDGPU::BUFFER_STORE_FORMAT_D16_XYZW_VBUFFER_IDXEN_exact),
        GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/0, // vdata
        GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/2, // vindex
        GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/1, // rsrc
        GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/0, // soffset
        GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/5, // offset
        GIR_CustomOperandRenderer, /*InsnID*/0, /*OldInsnID*/0, /*OpIdx*/6, /*OperandRenderer*/GIMT_Encode2(GICR_renderExtractCPol), // auxiliary
        GIR_CustomOperandRenderer, /*InsnID*/0, /*OldInsnID*/0, /*OpIdx*/6, /*OperandRenderer*/GIMT_Encode2(GICR_renderExtractSWZ), // auxiliary
        GIR_MergeMemOperands, /*InsnID*/0, /*NumInsns*/1, /*MergeInsnID's*/0,
        GIR_ConstrainSelectedInstOperands, /*InsnID*/0,
        GIR_EraseFromParent, /*InsnID*/0,
        // GIR_Coverage, 4391,
        GIR_Done,
      // Label 7052: @518400
      GIM_Try, /*On fail goto*//*Label 7053*/ GIMT_Encode4(518510), // Rule ID 4380 //
        GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasPackedD16VMem_HasUnrestrictedSOffset),
        // MIs[0] offset
        GIM_CheckIsImm, /*MI*/0, /*Op*/5,
        // MIs[0] auxiliary
        GIM_CheckIsImm, /*MI*/0, /*Op*/6,
        // MIs[0] Operand 7
        GIM_CheckIsImm, /*MI*/0, /*Op*/7,
        GIM_CheckComplexPattern, /*MI*/0, /*Op*/4, /*Renderer*/GIMT_Encode2(0), GIMT_Encode2(GICP_gi_buf_soffset),
        // (SIbuffer_store_format_d16 v4f16:{ *:[v4f16] }:$vdata, v4i32:{ *:[v4i32] }:$rsrc, i32:{ *:[i32] }:$vindex, i32:{ *:[i32] }:$voffset, (BUFSOffset:{ *:[i32] } i32:{ *:[i32] }:$soffset), (timm:{ *:[i32] }):$offset, (timm:{ *:[i32] }):$auxiliary, (timm:{ *:[i1] }))  =>  (BUFFER_STORE_FORMAT_D16_XYZW_BOTHEN_exact anonymous_15036:{ *:[v4f16] }:$vdata, (REG_SEQUENCE:{ *:[i64] } VReg_64:{ *:[i32] }, VGPR_32:{ *:[i32] }:$vindex, sub0:{ *:[i32] }, VGPR_32:{ *:[i32] }:$voffset, sub1:{ *:[i32] }), SReg_128:{ *:[v4i32] }:$rsrc, SCSrc_b32:{ *:[i32] }:$soffset, (timm:{ *:[i32] }):$offset, (extract_cpol:{ *:[i32] } ?:{ *:[i32] }:$auxiliary), (extract_swz:{ *:[i1] } ?:{ *:[i32] }:$auxiliary))
        GIR_MakeTempReg, /*TempRegID*/0, /*TypeID*/GILLT_s64,
        GIR_BuildMI, /*InsnID*/1, /*Opcode*/GIMT_Encode2(TargetOpcode::REG_SEQUENCE),
        GIR_AddTempRegister, /*InsnID*/1, /*TempRegID*/0, /*TempRegFlags*/GIMT_Encode2(RegState::Define),
        GIR_Copy, /*NewInsnID*/1, /*OldInsnID*/0, /*OpIdx*/2, // vindex
        GIR_AddImm8, /*InsnID*/1, /*SubRegIndex*/3,
        GIR_Copy, /*NewInsnID*/1, /*OldInsnID*/0, /*OpIdx*/3, // voffset
        GIR_AddImm8, /*InsnID*/1, /*SubRegIndex*/11,
        GIR_ConstrainOperandRC, /*InsnID*/1, /*Op*/0, GIMT_Encode2(AMDGPU::VReg_64RegClassID),
        GIR_ConstrainOperandRC, /*InsnID*/1, /*Op*/1, GIMT_Encode2(AMDGPU::VGPR_32RegClassID),
        GIR_ConstrainOperandRC, /*InsnID*/1, /*Op*/3, GIMT_Encode2(AMDGPU::VGPR_32RegClassID),
        GIR_BuildMI, /*InsnID*/0, /*Opcode*/GIMT_Encode2(AMDGPU::BUFFER_STORE_FORMAT_D16_XYZW_BOTHEN_exact),
        GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/0, // vdata
        GIR_AddSimpleTempRegister, /*InsnID*/0, /*TempRegID*/0,
        GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/1, // rsrc
        GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/0, // soffset
        GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/5, // offset
        GIR_CustomOperandRenderer, /*InsnID*/0, /*OldInsnID*/0, /*OpIdx*/6, /*OperandRenderer*/GIMT_Encode2(GICR_renderExtractCPol), // auxiliary
        GIR_CustomOperandRenderer, /*InsnID*/0, /*OldInsnID*/0, /*OpIdx*/6, /*OperandRenderer*/GIMT_Encode2(GICR_renderExtractSWZ), // auxiliary
        GIR_MergeMemOperands, /*InsnID*/0, /*NumInsns*/1, /*MergeInsnID's*/0,
        GIR_ConstrainSelectedInstOperands, /*InsnID*/0,
        GIR_EraseFromParent, /*InsnID*/0,
        // GIR_Coverage, 4380,
        GIR_Done,
      // Label 7053: @518510
      GIM_Try, /*On fail goto*//*Label 7054*/ GIMT_Encode4(518620), // Rule ID 4384 //
        GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasPackedD16VMem),
        // MIs[0] offset
        GIM_CheckIsImm, /*MI*/0, /*Op*/5,
        // MIs[0] auxiliary
        GIM_CheckIsImm, /*MI*/0, /*Op*/6,
        // MIs[0] Operand 7
        GIM_CheckIsImm, /*MI*/0, /*Op*/7,
        GIM_CheckComplexPattern, /*MI*/0, /*Op*/4, /*Renderer*/GIMT_Encode2(0), GIMT_Encode2(GICP_gi_buf_soffset),
        // (SIbuffer_store_format_d16 v4f16:{ *:[v4f16] }:$vdata, v4i32:{ *:[v4i32] }:$rsrc, i32:{ *:[i32] }:$vindex, i32:{ *:[i32] }:$voffset, (BUFSOffset:{ *:[i32] } i32:{ *:[i32] }:$soffset), (timm:{ *:[i32] }):$offset, (timm:{ *:[i32] }):$auxiliary, (timm:{ *:[i1] }))  =>  (BUFFER_STORE_FORMAT_D16_XYZW_VBUFFER_BOTHEN_exact anonymous_15036:{ *:[v4f16] }:$vdata, (REG_SEQUENCE:{ *:[i64] } VReg_64:{ *:[i32] }, VGPR_32:{ *:[i32] }:$vindex, sub0:{ *:[i32] }, VGPR_32:{ *:[i32] }:$voffset, sub1:{ *:[i32] }), SReg_128:{ *:[v4i32] }:$rsrc, SCSrc_b32:{ *:[i32] }:$soffset, (timm:{ *:[i32] }):$offset, (extract_cpol:{ *:[i32] } ?:{ *:[i32] }:$auxiliary), (extract_swz:{ *:[i1] } ?:{ *:[i32] }:$auxiliary))
        GIR_MakeTempReg, /*TempRegID*/0, /*TypeID*/GILLT_s64,
        GIR_BuildMI, /*InsnID*/1, /*Opcode*/GIMT_Encode2(TargetOpcode::REG_SEQUENCE),
        GIR_AddTempRegister, /*InsnID*/1, /*TempRegID*/0, /*TempRegFlags*/GIMT_Encode2(RegState::Define),
        GIR_Copy, /*NewInsnID*/1, /*OldInsnID*/0, /*OpIdx*/2, // vindex
        GIR_AddImm8, /*InsnID*/1, /*SubRegIndex*/3,
        GIR_Copy, /*NewInsnID*/1, /*OldInsnID*/0, /*OpIdx*/3, // voffset
        GIR_AddImm8, /*InsnID*/1, /*SubRegIndex*/11,
        GIR_ConstrainOperandRC, /*InsnID*/1, /*Op*/0, GIMT_Encode2(AMDGPU::VReg_64RegClassID),
        GIR_ConstrainOperandRC, /*InsnID*/1, /*Op*/1, GIMT_Encode2(AMDGPU::VGPR_32RegClassID),
        GIR_ConstrainOperandRC, /*InsnID*/1, /*Op*/3, GIMT_Encode2(AMDGPU::VGPR_32RegClassID),
        GIR_BuildMI, /*InsnID*/0, /*Opcode*/GIMT_Encode2(AMDGPU::BUFFER_STORE_FORMAT_D16_XYZW_VBUFFER_BOTHEN_exact),
        GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/0, // vdata
        GIR_AddSimpleTempRegister, /*InsnID*/0, /*TempRegID*/0,
        GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/1, // rsrc
        GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/0, // soffset
        GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/5, // offset
        GIR_CustomOperandRenderer, /*InsnID*/0, /*OldInsnID*/0, /*OpIdx*/6, /*OperandRenderer*/GIMT_Encode2(GICR_renderExtractCPol), // auxiliary
        GIR_CustomOperandRenderer, /*InsnID*/0, /*OldInsnID*/0, /*OpIdx*/6, /*OperandRenderer*/GIMT_Encode2(GICR_renderExtractSWZ), // auxiliary
        GIR_MergeMemOperands, /*InsnID*/0, /*NumInsns*/1, /*MergeInsnID's*/0,
        GIR_ConstrainSelectedInstOperands, /*InsnID*/0,
        GIR_EraseFromParent, /*InsnID*/0,
        // GIR_Coverage, 4384,
        GIR_Done,
      // Label 7054: @518620
      GIM_Try, /*On fail goto*//*Label 7055*/ GIMT_Encode4(518730), // Rule ID 4388 //
        GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasPackedD16VMem_HasUnrestrictedSOffset),
        // MIs[0] offset
        GIM_CheckIsImm, /*MI*/0, /*Op*/5,
        // MIs[0] auxiliary
        GIM_CheckIsImm, /*MI*/0, /*Op*/6,
        // MIs[0] Operand 7
        GIM_CheckIsImm, /*MI*/0, /*Op*/7,
        GIM_CheckComplexPattern, /*MI*/0, /*Op*/4, /*Renderer*/GIMT_Encode2(0), GIMT_Encode2(GICP_gi_buf_soffset),
        // (SIbuffer_store_format_d16 v4i16:{ *:[v4i16] }:$vdata, v4i32:{ *:[v4i32] }:$rsrc, i32:{ *:[i32] }:$vindex, i32:{ *:[i32] }:$voffset, (BUFSOffset:{ *:[i32] } i32:{ *:[i32] }:$soffset), (timm:{ *:[i32] }):$offset, (timm:{ *:[i32] }):$auxiliary, (timm:{ *:[i1] }))  =>  (BUFFER_STORE_FORMAT_D16_XYZW_BOTHEN_exact anonymous_15036:{ *:[v4i16] }:$vdata, (REG_SEQUENCE:{ *:[i64] } VReg_64:{ *:[i32] }, VGPR_32:{ *:[i32] }:$vindex, sub0:{ *:[i32] }, VGPR_32:{ *:[i32] }:$voffset, sub1:{ *:[i32] }), SReg_128:{ *:[v4i32] }:$rsrc, SCSrc_b32:{ *:[i32] }:$soffset, (timm:{ *:[i32] }):$offset, (extract_cpol:{ *:[i32] } ?:{ *:[i32] }:$auxiliary), (extract_swz:{ *:[i1] } ?:{ *:[i32] }:$auxiliary))
        GIR_MakeTempReg, /*TempRegID*/0, /*TypeID*/GILLT_s64,
        GIR_BuildMI, /*InsnID*/1, /*Opcode*/GIMT_Encode2(TargetOpcode::REG_SEQUENCE),
        GIR_AddTempRegister, /*InsnID*/1, /*TempRegID*/0, /*TempRegFlags*/GIMT_Encode2(RegState::Define),
        GIR_Copy, /*NewInsnID*/1, /*OldInsnID*/0, /*OpIdx*/2, // vindex
        GIR_AddImm8, /*InsnID*/1, /*SubRegIndex*/3,
        GIR_Copy, /*NewInsnID*/1, /*OldInsnID*/0, /*OpIdx*/3, // voffset
        GIR_AddImm8, /*InsnID*/1, /*SubRegIndex*/11,
        GIR_ConstrainOperandRC, /*InsnID*/1, /*Op*/0, GIMT_Encode2(AMDGPU::VReg_64RegClassID),
        GIR_ConstrainOperandRC, /*InsnID*/1, /*Op*/1, GIMT_Encode2(AMDGPU::VGPR_32RegClassID),
        GIR_ConstrainOperandRC, /*InsnID*/1, /*Op*/3, GIMT_Encode2(AMDGPU::VGPR_32RegClassID),
        GIR_BuildMI, /*InsnID*/0, /*Opcode*/GIMT_Encode2(AMDGPU::BUFFER_STORE_FORMAT_D16_XYZW_BOTHEN_exact),
        GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/0, // vdata
        GIR_AddSimpleTempRegister, /*InsnID*/0, /*TempRegID*/0,
        GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/1, // rsrc
        GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/0, // soffset
        GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/5, // offset
        GIR_CustomOperandRenderer, /*InsnID*/0, /*OldInsnID*/0, /*OpIdx*/6, /*OperandRenderer*/GIMT_Encode2(GICR_renderExtractCPol), // auxiliary
        GIR_CustomOperandRenderer, /*InsnID*/0, /*OldInsnID*/0, /*OpIdx*/6, /*OperandRenderer*/GIMT_Encode2(GICR_renderExtractSWZ), // auxiliary
        GIR_MergeMemOperands, /*InsnID*/0, /*NumInsns*/1, /*MergeInsnID's*/0,
        GIR_ConstrainSelectedInstOperands, /*InsnID*/0,
        GIR_EraseFromParent, /*InsnID*/0,
        // GIR_Coverage, 4388,
        GIR_Done,
      // Label 7055: @518730
      GIM_Try, /*On fail goto*//*Label 7056*/ GIMT_Encode4(518840), // Rule ID 4392 //
        GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasPackedD16VMem),
        // MIs[0] offset
        GIM_CheckIsImm, /*MI*/0, /*Op*/5,
        // MIs[0] auxiliary
        GIM_CheckIsImm, /*MI*/0, /*Op*/6,
        // MIs[0] Operand 7
        GIM_CheckIsImm, /*MI*/0, /*Op*/7,
        GIM_CheckComplexPattern, /*MI*/0, /*Op*/4, /*Renderer*/GIMT_Encode2(0), GIMT_Encode2(GICP_gi_buf_soffset),
        // (SIbuffer_store_format_d16 v4i16:{ *:[v4i16] }:$vdata, v4i32:{ *:[v4i32] }:$rsrc, i32:{ *:[i32] }:$vindex, i32:{ *:[i32] }:$voffset, (BUFSOffset:{ *:[i32] } i32:{ *:[i32] }:$soffset), (timm:{ *:[i32] }):$offset, (timm:{ *:[i32] }):$auxiliary, (timm:{ *:[i1] }))  =>  (BUFFER_STORE_FORMAT_D16_XYZW_VBUFFER_BOTHEN_exact anonymous_15036:{ *:[v4i16] }:$vdata, (REG_SEQUENCE:{ *:[i64] } VReg_64:{ *:[i32] }, VGPR_32:{ *:[i32] }:$vindex, sub0:{ *:[i32] }, VGPR_32:{ *:[i32] }:$voffset, sub1:{ *:[i32] }), SReg_128:{ *:[v4i32] }:$rsrc, SCSrc_b32:{ *:[i32] }:$soffset, (timm:{ *:[i32] }):$offset, (extract_cpol:{ *:[i32] } ?:{ *:[i32] }:$auxiliary), (extract_swz:{ *:[i1] } ?:{ *:[i32] }:$auxiliary))
        GIR_MakeTempReg, /*TempRegID*/0, /*TypeID*/GILLT_s64,
        GIR_BuildMI, /*InsnID*/1, /*Opcode*/GIMT_Encode2(TargetOpcode::REG_SEQUENCE),
        GIR_AddTempRegister, /*InsnID*/1, /*TempRegID*/0, /*TempRegFlags*/GIMT_Encode2(RegState::Define),
        GIR_Copy, /*NewInsnID*/1, /*OldInsnID*/0, /*OpIdx*/2, // vindex
        GIR_AddImm8, /*InsnID*/1, /*SubRegIndex*/3,
        GIR_Copy, /*NewInsnID*/1, /*OldInsnID*/0, /*OpIdx*/3, // voffset
        GIR_AddImm8, /*InsnID*/1, /*SubRegIndex*/11,
        GIR_ConstrainOperandRC, /*InsnID*/1, /*Op*/0, GIMT_Encode2(AMDGPU::VReg_64RegClassID),
        GIR_ConstrainOperandRC, /*InsnID*/1, /*Op*/1, GIMT_Encode2(AMDGPU::VGPR_32RegClassID),
        GIR_ConstrainOperandRC, /*InsnID*/1, /*Op*/3, GIMT_Encode2(AMDGPU::VGPR_32RegClassID),
        GIR_BuildMI, /*InsnID*/0, /*Opcode*/GIMT_Encode2(AMDGPU::BUFFER_STORE_FORMAT_D16_XYZW_VBUFFER_BOTHEN_exact),
        GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/0, // vdata
        GIR_AddSimpleTempRegister, /*InsnID*/0, /*TempRegID*/0,
        GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/1, // rsrc
        GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/0, // soffset
        GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/5, // offset
        GIR_CustomOperandRenderer, /*InsnID*/0, /*OldInsnID*/0, /*OpIdx*/6, /*OperandRenderer*/GIMT_Encode2(GICR_renderExtractCPol), // auxiliary
        GIR_CustomOperandRenderer, /*InsnID*/0, /*OldInsnID*/0, /*OpIdx*/6, /*OperandRenderer*/GIMT_Encode2(GICR_renderExtractSWZ), // auxiliary
        GIR_MergeMemOperands, /*InsnID*/0, /*NumInsns*/1, /*MergeInsnID's*/0,
        GIR_ConstrainSelectedInstOperands, /*InsnID*/0,
        GIR_EraseFromParent, /*InsnID*/0,
        // GIR_Coverage, 4392,
        GIR_Done,
      // Label 7056: @518840
      GIM_Reject,
    // Label 7040: @518841
    GIM_Reject,
    // Label 6973: @518842
    GIM_Try, /*On fail goto*//*Label 7057*/ GIMT_Encode4(519212),
      GIM_CheckType, /*MI*/0, /*Op*/1, /*Type*/GILLT_v4s32,
      GIM_CheckType, /*MI*/0, /*Op*/2, /*Type*/GILLT_s32,
      GIM_CheckType, /*MI*/0, /*Op*/3, /*Type*/GILLT_s32,
      GIM_CheckType, /*MI*/0, /*Op*/4, /*Type*/GILLT_s32,
      GIM_Try, /*On fail goto*//*Label 7058*/ GIMT_Encode4(518945), // Rule ID 4317 //
        GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasUnpackedD16VMem),
        GIM_CheckConstantInt8, /*MI*/0, /*Op*/2, 0,
        GIM_CheckConstantInt8, /*MI*/0, /*Op*/3, 0,
        // MIs[0] offset
        GIM_CheckIsImm, /*MI*/0, /*Op*/5,
        // MIs[0] auxiliary
        GIM_CheckIsImm, /*MI*/0, /*Op*/6,
        // MIs[0] Operand 7
        GIM_CheckLiteralInt, /*MI*/0, /*Op*/7, GIMT_Encode8(0),
        GIM_CheckComplexPattern, /*MI*/0, /*Op*/4, /*Renderer*/GIMT_Encode2(0), GIMT_Encode2(GICP_gi_buf_soffset),
        // (SIbuffer_store_format_d16 v4i32:{ *:[v4i32] }:$vdata, v4i32:{ *:[v4i32] }:$rsrc, 0:{ *:[i32] }, 0:{ *:[i32] }, (BUFSOffset:{ *:[i32] } i32:{ *:[i32] }:$soffset), (timm:{ *:[i32] }):$offset, (timm:{ *:[i32] }):$auxiliary, 0:{ *:[i1] })  =>  (BUFFER_STORE_FORMAT_D16_XYZW_gfx80_OFFSET_exact anonymous_15034:{ *:[v4i32] }:$vdata, SReg_128:{ *:[v4i32] }:$rsrc, SCSrc_b32:{ *:[i32] }:$soffset, (timm:{ *:[i32] }):$offset, (extract_cpol:{ *:[i32] } ?:{ *:[i32] }:$auxiliary), (extract_swz:{ *:[i1] } ?:{ *:[i32] }:$auxiliary))
        GIR_BuildMI, /*InsnID*/0, /*Opcode*/GIMT_Encode2(AMDGPU::BUFFER_STORE_FORMAT_D16_XYZW_gfx80_OFFSET_exact),
        GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/0, // vdata
        GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/1, // rsrc
        GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/0, // soffset
        GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/5, // offset
        GIR_CustomOperandRenderer, /*InsnID*/0, /*OldInsnID*/0, /*OpIdx*/6, /*OperandRenderer*/GIMT_Encode2(GICR_renderExtractCPol), // auxiliary
        GIR_CustomOperandRenderer, /*InsnID*/0, /*OldInsnID*/0, /*OpIdx*/6, /*OperandRenderer*/GIMT_Encode2(GICR_renderExtractSWZ), // auxiliary
        GIR_MergeMemOperands, /*InsnID*/0, /*NumInsns*/1, /*MergeInsnID's*/0,
        GIR_ConstrainSelectedInstOperands, /*InsnID*/0,
        GIR_EraseFromParent, /*InsnID*/0,
        // GIR_Coverage, 4317,
        GIR_Done,
      // Label 7058: @518945
      GIM_Try, /*On fail goto*//*Label 7059*/ GIMT_Encode4(519027), // Rule ID 4318 //
        GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasUnpackedD16VMem),
        GIM_CheckConstantInt8, /*MI*/0, /*Op*/2, 0,
        // MIs[0] offset
        GIM_CheckIsImm, /*MI*/0, /*Op*/5,
        // MIs[0] auxiliary
        GIM_CheckIsImm, /*MI*/0, /*Op*/6,
        // MIs[0] Operand 7
        GIM_CheckLiteralInt, /*MI*/0, /*Op*/7, GIMT_Encode8(0),
        GIM_CheckComplexPattern, /*MI*/0, /*Op*/4, /*Renderer*/GIMT_Encode2(0), GIMT_Encode2(GICP_gi_buf_soffset),
        // (SIbuffer_store_format_d16 v4i32:{ *:[v4i32] }:$vdata, v4i32:{ *:[v4i32] }:$rsrc, 0:{ *:[i32] }, i32:{ *:[i32] }:$voffset, (BUFSOffset:{ *:[i32] } i32:{ *:[i32] }:$soffset), (timm:{ *:[i32] }):$offset, (timm:{ *:[i32] }):$auxiliary, 0:{ *:[i1] })  =>  (BUFFER_STORE_FORMAT_D16_XYZW_gfx80_OFFEN_exact anonymous_15034:{ *:[v4i32] }:$vdata, VGPR_32:{ *:[i32] }:$voffset, SReg_128:{ *:[v4i32] }:$rsrc, SCSrc_b32:{ *:[i32] }:$soffset, (timm:{ *:[i32] }):$offset, (extract_cpol:{ *:[i32] } ?:{ *:[i32] }:$auxiliary), (extract_swz:{ *:[i1] } ?:{ *:[i32] }:$auxiliary))
        GIR_BuildMI, /*InsnID*/0, /*Opcode*/GIMT_Encode2(AMDGPU::BUFFER_STORE_FORMAT_D16_XYZW_gfx80_OFFEN_exact),
        GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/0, // vdata
        GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/3, // voffset
        GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/1, // rsrc
        GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/0, // soffset
        GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/5, // offset
        GIR_CustomOperandRenderer, /*InsnID*/0, /*OldInsnID*/0, /*OpIdx*/6, /*OperandRenderer*/GIMT_Encode2(GICR_renderExtractCPol), // auxiliary
        GIR_CustomOperandRenderer, /*InsnID*/0, /*OldInsnID*/0, /*OpIdx*/6, /*OperandRenderer*/GIMT_Encode2(GICR_renderExtractSWZ), // auxiliary
        GIR_MergeMemOperands, /*InsnID*/0, /*NumInsns*/1, /*MergeInsnID's*/0,
        GIR_ConstrainSelectedInstOperands, /*InsnID*/0,
        GIR_EraseFromParent, /*InsnID*/0,
        // GIR_Coverage, 4318,
        GIR_Done,
      // Label 7059: @519027
      GIM_Try, /*On fail goto*//*Label 7060*/ GIMT_Encode4(519101), // Rule ID 4319 //
        GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasUnpackedD16VMem),
        GIM_CheckConstantInt8, /*MI*/0, /*Op*/3, 0,
        // MIs[0] offset
        GIM_CheckIsImm, /*MI*/0, /*Op*/5,
        // MIs[0] auxiliary
        GIM_CheckIsImm, /*MI*/0, /*Op*/6,
        // MIs[0] Operand 7
        GIM_CheckIsImm, /*MI*/0, /*Op*/7,
        GIM_CheckComplexPattern, /*MI*/0, /*Op*/4, /*Renderer*/GIMT_Encode2(0), GIMT_Encode2(GICP_gi_buf_soffset),
        // (SIbuffer_store_format_d16 v4i32:{ *:[v4i32] }:$vdata, v4i32:{ *:[v4i32] }:$rsrc, i32:{ *:[i32] }:$vindex, 0:{ *:[i32] }, (BUFSOffset:{ *:[i32] } i32:{ *:[i32] }:$soffset), (timm:{ *:[i32] }):$offset, (timm:{ *:[i32] }):$auxiliary, (timm:{ *:[i1] }))  =>  (BUFFER_STORE_FORMAT_D16_XYZW_gfx80_IDXEN_exact anonymous_15034:{ *:[v4i32] }:$vdata, VGPR_32:{ *:[i32] }:$vindex, SReg_128:{ *:[v4i32] }:$rsrc, SCSrc_b32:{ *:[i32] }:$soffset, (timm:{ *:[i32] }):$offset, (extract_cpol:{ *:[i32] } ?:{ *:[i32] }:$auxiliary), (extract_swz:{ *:[i1] } ?:{ *:[i32] }:$auxiliary))
        GIR_BuildMI, /*InsnID*/0, /*Opcode*/GIMT_Encode2(AMDGPU::BUFFER_STORE_FORMAT_D16_XYZW_gfx80_IDXEN_exact),
        GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/0, // vdata
        GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/2, // vindex
        GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/1, // rsrc
        GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/0, // soffset
        GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/5, // offset
        GIR_CustomOperandRenderer, /*InsnID*/0, /*OldInsnID*/0, /*OpIdx*/6, /*OperandRenderer*/GIMT_Encode2(GICR_renderExtractCPol), // auxiliary
        GIR_CustomOperandRenderer, /*InsnID*/0, /*OldInsnID*/0, /*OpIdx*/6, /*OperandRenderer*/GIMT_Encode2(GICR_renderExtractSWZ), // auxiliary
        GIR_MergeMemOperands, /*InsnID*/0, /*NumInsns*/1, /*MergeInsnID's*/0,
        GIR_ConstrainSelectedInstOperands, /*InsnID*/0,
        GIR_EraseFromParent, /*InsnID*/0,
        // GIR_Coverage, 4319,
        GIR_Done,
      // Label 7060: @519101
      GIM_Try, /*On fail goto*//*Label 7061*/ GIMT_Encode4(519211), // Rule ID 4320 //
        GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasUnpackedD16VMem),
        // MIs[0] offset
        GIM_CheckIsImm, /*MI*/0, /*Op*/5,
        // MIs[0] auxiliary
        GIM_CheckIsImm, /*MI*/0, /*Op*/6,
        // MIs[0] Operand 7
        GIM_CheckIsImm, /*MI*/0, /*Op*/7,
        GIM_CheckComplexPattern, /*MI*/0, /*Op*/4, /*Renderer*/GIMT_Encode2(0), GIMT_Encode2(GICP_gi_buf_soffset),
        // (SIbuffer_store_format_d16 v4i32:{ *:[v4i32] }:$vdata, v4i32:{ *:[v4i32] }:$rsrc, i32:{ *:[i32] }:$vindex, i32:{ *:[i32] }:$voffset, (BUFSOffset:{ *:[i32] } i32:{ *:[i32] }:$soffset), (timm:{ *:[i32] }):$offset, (timm:{ *:[i32] }):$auxiliary, (timm:{ *:[i1] }))  =>  (BUFFER_STORE_FORMAT_D16_XYZW_gfx80_BOTHEN_exact anonymous_15034:{ *:[v4i32] }:$vdata, (REG_SEQUENCE:{ *:[i64] } VReg_64:{ *:[i32] }, VGPR_32:{ *:[i32] }:$vindex, sub0:{ *:[i32] }, VGPR_32:{ *:[i32] }:$voffset, sub1:{ *:[i32] }), SReg_128:{ *:[v4i32] }:$rsrc, SCSrc_b32:{ *:[i32] }:$soffset, (timm:{ *:[i32] }):$offset, (extract_cpol:{ *:[i32] } ?:{ *:[i32] }:$auxiliary), (extract_swz:{ *:[i1] } ?:{ *:[i32] }:$auxiliary))
        GIR_MakeTempReg, /*TempRegID*/0, /*TypeID*/GILLT_s64,
        GIR_BuildMI, /*InsnID*/1, /*Opcode*/GIMT_Encode2(TargetOpcode::REG_SEQUENCE),
        GIR_AddTempRegister, /*InsnID*/1, /*TempRegID*/0, /*TempRegFlags*/GIMT_Encode2(RegState::Define),
        GIR_Copy, /*NewInsnID*/1, /*OldInsnID*/0, /*OpIdx*/2, // vindex
        GIR_AddImm8, /*InsnID*/1, /*SubRegIndex*/3,
        GIR_Copy, /*NewInsnID*/1, /*OldInsnID*/0, /*OpIdx*/3, // voffset
        GIR_AddImm8, /*InsnID*/1, /*SubRegIndex*/11,
        GIR_ConstrainOperandRC, /*InsnID*/1, /*Op*/0, GIMT_Encode2(AMDGPU::VReg_64RegClassID),
        GIR_ConstrainOperandRC, /*InsnID*/1, /*Op*/1, GIMT_Encode2(AMDGPU::VGPR_32RegClassID),
        GIR_ConstrainOperandRC, /*InsnID*/1, /*Op*/3, GIMT_Encode2(AMDGPU::VGPR_32RegClassID),
        GIR_BuildMI, /*InsnID*/0, /*Opcode*/GIMT_Encode2(AMDGPU::BUFFER_STORE_FORMAT_D16_XYZW_gfx80_BOTHEN_exact),
        GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/0, // vdata
        GIR_AddSimpleTempRegister, /*InsnID*/0, /*TempRegID*/0,
        GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/1, // rsrc
        GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/0, // soffset
        GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/5, // offset
        GIR_CustomOperandRenderer, /*InsnID*/0, /*OldInsnID*/0, /*OpIdx*/6, /*OperandRenderer*/GIMT_Encode2(GICR_renderExtractCPol), // auxiliary
        GIR_CustomOperandRenderer, /*InsnID*/0, /*OldInsnID*/0, /*OpIdx*/6, /*OperandRenderer*/GIMT_Encode2(GICR_renderExtractSWZ), // auxiliary
        GIR_MergeMemOperands, /*InsnID*/0, /*NumInsns*/1, /*MergeInsnID's*/0,
        GIR_ConstrainSelectedInstOperands, /*InsnID*/0,
        GIR_EraseFromParent, /*InsnID*/0,
        // GIR_Coverage, 4320,
        GIR_Done,
      // Label 7061: @519211
      GIM_Reject,
    // Label 7057: @519212
    GIM_Reject,
    // Label 6974: @519213
    GIM_Reject,
    // Label 136: @519214
    GIM_Try, /*On fail goto*//*Label 7062*/ GIMT_Encode4(519908),
      GIM_CheckType, /*MI*/0, /*Op*/0, /*Type*/GILLT_s32,
      GIM_CheckType, /*MI*/0, /*Op*/1, /*Type*/GILLT_v4s32,
      GIM_CheckType, /*MI*/0, /*Op*/2, /*Type*/GILLT_s32,
      GIM_CheckType, /*MI*/0, /*Op*/3, /*Type*/GILLT_s32,
      GIM_CheckType, /*MI*/0, /*Op*/4, /*Type*/GILLT_s32,
      GIM_Try, /*On fail goto*//*Label 7063*/ GIMT_Encode4(519555),
        GIM_CheckConstantInt8, /*MI*/0, /*Op*/2, 0,
        GIM_Try, /*On fail goto*//*Label 7064*/ GIMT_Encode4(519326), // Rule ID 4497 //
          GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasUnrestrictedSOffset),
          GIM_CheckConstantInt8, /*MI*/0, /*Op*/3, 0,
          // MIs[0] offset
          GIM_CheckIsImm, /*MI*/0, /*Op*/5,
          // MIs[0] auxiliary
          GIM_CheckIsImm, /*MI*/0, /*Op*/6,
          // MIs[0] Operand 7
          GIM_CheckLiteralInt, /*MI*/0, /*Op*/7, GIMT_Encode8(0),
          GIM_CheckComplexPattern, /*MI*/0, /*Op*/4, /*Renderer*/GIMT_Encode2(0), GIMT_Encode2(GICP_gi_buf_soffset),
          // (SIbuffer_store_short i32:{ *:[i32] }:$vdata, v4i32:{ *:[v4i32] }:$rsrc, 0:{ *:[i32] }, 0:{ *:[i32] }, (BUFSOffset:{ *:[i32] } i32:{ *:[i32] }:$soffset), (timm:{ *:[i32] }):$offset, (timm:{ *:[i32] }):$auxiliary, 0:{ *:[i1] })  =>  (BUFFER_STORE_SHORT_OFFSET_exact anonymous_15037:{ *:[i32] }:$vdata, SReg_128:{ *:[v4i32] }:$rsrc, SCSrc_b32:{ *:[i32] }:$soffset, (timm:{ *:[i32] }):$offset, (extract_cpol:{ *:[i32] } ?:{ *:[i32] }:$auxiliary), (extract_swz:{ *:[i1] } ?:{ *:[i32] }:$auxiliary))
          GIR_BuildMI, /*InsnID*/0, /*Opcode*/GIMT_Encode2(AMDGPU::BUFFER_STORE_SHORT_OFFSET_exact),
          GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/0, // vdata
          GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/1, // rsrc
          GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/0, // soffset
          GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/5, // offset
          GIR_CustomOperandRenderer, /*InsnID*/0, /*OldInsnID*/0, /*OpIdx*/6, /*OperandRenderer*/GIMT_Encode2(GICR_renderExtractCPol), // auxiliary
          GIR_CustomOperandRenderer, /*InsnID*/0, /*OldInsnID*/0, /*OpIdx*/6, /*OperandRenderer*/GIMT_Encode2(GICR_renderExtractSWZ), // auxiliary
          GIR_MergeMemOperands, /*InsnID*/0, /*NumInsns*/1, /*MergeInsnID's*/0,
          GIR_ConstrainSelectedInstOperands, /*InsnID*/0,
          GIR_EraseFromParent, /*InsnID*/0,
          // GIR_Coverage, 4497,
          GIR_Done,
        // Label 7064: @519326
        GIM_Try, /*On fail goto*//*Label 7065*/ GIMT_Encode4(519401), // Rule ID 4501 //
          GIM_CheckConstantInt8, /*MI*/0, /*Op*/3, 0,
          // MIs[0] offset
          GIM_CheckIsImm, /*MI*/0, /*Op*/5,
          // MIs[0] auxiliary
          GIM_CheckIsImm, /*MI*/0, /*Op*/6,
          // MIs[0] Operand 7
          GIM_CheckLiteralInt, /*MI*/0, /*Op*/7, GIMT_Encode8(0),
          GIM_CheckComplexPattern, /*MI*/0, /*Op*/4, /*Renderer*/GIMT_Encode2(0), GIMT_Encode2(GICP_gi_buf_soffset),
          // (SIbuffer_store_short i32:{ *:[i32] }:$vdata, v4i32:{ *:[v4i32] }:$rsrc, 0:{ *:[i32] }, 0:{ *:[i32] }, (BUFSOffset:{ *:[i32] } i32:{ *:[i32] }:$soffset), (timm:{ *:[i32] }):$offset, (timm:{ *:[i32] }):$auxiliary, 0:{ *:[i1] })  =>  (BUFFER_STORE_SHORT_VBUFFER_OFFSET_exact anonymous_15037:{ *:[i32] }:$vdata, SReg_128:{ *:[v4i32] }:$rsrc, SCSrc_b32:{ *:[i32] }:$soffset, (timm:{ *:[i32] }):$offset, (extract_cpol:{ *:[i32] } ?:{ *:[i32] }:$auxiliary), (extract_swz:{ *:[i1] } ?:{ *:[i32] }:$auxiliary))
          GIR_BuildMI, /*InsnID*/0, /*Opcode*/GIMT_Encode2(AMDGPU::BUFFER_STORE_SHORT_VBUFFER_OFFSET_exact),
          GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/0, // vdata
          GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/1, // rsrc
          GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/0, // soffset
          GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/5, // offset
          GIR_CustomOperandRenderer, /*InsnID*/0, /*OldInsnID*/0, /*OpIdx*/6, /*OperandRenderer*/GIMT_Encode2(GICR_renderExtractCPol), // auxiliary
          GIR_CustomOperandRenderer, /*InsnID*/0, /*OldInsnID*/0, /*OpIdx*/6, /*OperandRenderer*/GIMT_Encode2(GICR_renderExtractSWZ), // auxiliary
          GIR_MergeMemOperands, /*InsnID*/0, /*NumInsns*/1, /*MergeInsnID's*/0,
          GIR_ConstrainSelectedInstOperands, /*InsnID*/0,
          GIR_EraseFromParent, /*InsnID*/0,
          // GIR_Coverage, 4501,
          GIR_Done,
        // Label 7065: @519401
        GIM_Try, /*On fail goto*//*Label 7066*/ GIMT_Encode4(519479), // Rule ID 4498 //
          GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasUnrestrictedSOffset),
          // MIs[0] offset
          GIM_CheckIsImm, /*MI*/0, /*Op*/5,
          // MIs[0] auxiliary
          GIM_CheckIsImm, /*MI*/0, /*Op*/6,
          // MIs[0] Operand 7
          GIM_CheckLiteralInt, /*MI*/0, /*Op*/7, GIMT_Encode8(0),
          GIM_CheckComplexPattern, /*MI*/0, /*Op*/4, /*Renderer*/GIMT_Encode2(0), GIMT_Encode2(GICP_gi_buf_soffset),
          // (SIbuffer_store_short i32:{ *:[i32] }:$vdata, v4i32:{ *:[v4i32] }:$rsrc, 0:{ *:[i32] }, i32:{ *:[i32] }:$voffset, (BUFSOffset:{ *:[i32] } i32:{ *:[i32] }:$soffset), (timm:{ *:[i32] }):$offset, (timm:{ *:[i32] }):$auxiliary, 0:{ *:[i1] })  =>  (BUFFER_STORE_SHORT_OFFEN_exact anonymous_15037:{ *:[i32] }:$vdata, VGPR_32:{ *:[i32] }:$voffset, SReg_128:{ *:[v4i32] }:$rsrc, SCSrc_b32:{ *:[i32] }:$soffset, (timm:{ *:[i32] }):$offset, (extract_cpol:{ *:[i32] } ?:{ *:[i32] }:$auxiliary), (extract_swz:{ *:[i1] } ?:{ *:[i32] }:$auxiliary))
          GIR_BuildMI, /*InsnID*/0, /*Opcode*/GIMT_Encode2(AMDGPU::BUFFER_STORE_SHORT_OFFEN_exact),
          GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/0, // vdata
          GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/3, // voffset
          GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/1, // rsrc
          GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/0, // soffset
          GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/5, // offset
          GIR_CustomOperandRenderer, /*InsnID*/0, /*OldInsnID*/0, /*OpIdx*/6, /*OperandRenderer*/GIMT_Encode2(GICR_renderExtractCPol), // auxiliary
          GIR_CustomOperandRenderer, /*InsnID*/0, /*OldInsnID*/0, /*OpIdx*/6, /*OperandRenderer*/GIMT_Encode2(GICR_renderExtractSWZ), // auxiliary
          GIR_MergeMemOperands, /*InsnID*/0, /*NumInsns*/1, /*MergeInsnID's*/0,
          GIR_ConstrainSelectedInstOperands, /*InsnID*/0,
          GIR_EraseFromParent, /*InsnID*/0,
          // GIR_Coverage, 4498,
          GIR_Done,
        // Label 7066: @519479
        GIM_Try, /*On fail goto*//*Label 7067*/ GIMT_Encode4(519554), // Rule ID 4502 //
          // MIs[0] offset
          GIM_CheckIsImm, /*MI*/0, /*Op*/5,
          // MIs[0] auxiliary
          GIM_CheckIsImm, /*MI*/0, /*Op*/6,
          // MIs[0] Operand 7
          GIM_CheckLiteralInt, /*MI*/0, /*Op*/7, GIMT_Encode8(0),
          GIM_CheckComplexPattern, /*MI*/0, /*Op*/4, /*Renderer*/GIMT_Encode2(0), GIMT_Encode2(GICP_gi_buf_soffset),
          // (SIbuffer_store_short i32:{ *:[i32] }:$vdata, v4i32:{ *:[v4i32] }:$rsrc, 0:{ *:[i32] }, i32:{ *:[i32] }:$voffset, (BUFSOffset:{ *:[i32] } i32:{ *:[i32] }:$soffset), (timm:{ *:[i32] }):$offset, (timm:{ *:[i32] }):$auxiliary, 0:{ *:[i1] })  =>  (BUFFER_STORE_SHORT_VBUFFER_OFFEN_exact anonymous_15037:{ *:[i32] }:$vdata, VGPR_32:{ *:[i32] }:$voffset, SReg_128:{ *:[v4i32] }:$rsrc, SCSrc_b32:{ *:[i32] }:$soffset, (timm:{ *:[i32] }):$offset, (extract_cpol:{ *:[i32] } ?:{ *:[i32] }:$auxiliary), (extract_swz:{ *:[i1] } ?:{ *:[i32] }:$auxiliary))
          GIR_BuildMI, /*InsnID*/0, /*Opcode*/GIMT_Encode2(AMDGPU::BUFFER_STORE_SHORT_VBUFFER_OFFEN_exact),
          GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/0, // vdata
          GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/3, // voffset
          GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/1, // rsrc
          GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/0, // soffset
          GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/5, // offset
          GIR_CustomOperandRenderer, /*InsnID*/0, /*OldInsnID*/0, /*OpIdx*/6, /*OperandRenderer*/GIMT_Encode2(GICR_renderExtractCPol), // auxiliary
          GIR_CustomOperandRenderer, /*InsnID*/0, /*OldInsnID*/0, /*OpIdx*/6, /*OperandRenderer*/GIMT_Encode2(GICR_renderExtractSWZ), // auxiliary
          GIR_MergeMemOperands, /*InsnID*/0, /*NumInsns*/1, /*MergeInsnID's*/0,
          GIR_ConstrainSelectedInstOperands, /*InsnID*/0,
          GIR_EraseFromParent, /*InsnID*/0,
          // GIR_Coverage, 4502,
          GIR_Done,
        // Label 7067: @519554
        GIM_Reject,
      // Label 7063: @519555
      GIM_Try, /*On fail goto*//*Label 7068*/ GIMT_Encode4(519693),
        GIM_CheckConstantInt8, /*MI*/0, /*Op*/3, 0,
        GIM_CheckIsImm, /*MI*/0, /*Op*/5,
        GIM_CheckIsImm, /*MI*/0, /*Op*/6,
        GIM_CheckIsImm, /*MI*/0, /*Op*/7,
        GIM_Try, /*On fail goto*//*Label 7069*/ GIMT_Encode4(519634), // Rule ID 4499 //
          GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasUnrestrictedSOffset),
          GIM_CheckComplexPattern, /*MI*/0, /*Op*/4, /*Renderer*/GIMT_Encode2(0), GIMT_Encode2(GICP_gi_buf_soffset),
          // (SIbuffer_store_short i32:{ *:[i32] }:$vdata, v4i32:{ *:[v4i32] }:$rsrc, i32:{ *:[i32] }:$vindex, 0:{ *:[i32] }, (BUFSOffset:{ *:[i32] } i32:{ *:[i32] }:$soffset), (timm:{ *:[i32] }):$offset, (timm:{ *:[i32] }):$auxiliary, (timm:{ *:[i1] }))  =>  (BUFFER_STORE_SHORT_IDXEN_exact anonymous_15037:{ *:[i32] }:$vdata, VGPR_32:{ *:[i32] }:$vindex, SReg_128:{ *:[v4i32] }:$rsrc, SCSrc_b32:{ *:[i32] }:$soffset, (timm:{ *:[i32] }):$offset, (extract_cpol:{ *:[i32] } ?:{ *:[i32] }:$auxiliary), (extract_swz:{ *:[i1] } ?:{ *:[i32] }:$auxiliary))
          GIR_BuildMI, /*InsnID*/0, /*Opcode*/GIMT_Encode2(AMDGPU::BUFFER_STORE_SHORT_IDXEN_exact),
          GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/0, // vdata
          GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/2, // vindex
          GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/1, // rsrc
          GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/0, // soffset
          GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/5, // offset
          GIR_CustomOperandRenderer, /*InsnID*/0, /*OldInsnID*/0, /*OpIdx*/6, /*OperandRenderer*/GIMT_Encode2(GICR_renderExtractCPol), // auxiliary
          GIR_CustomOperandRenderer, /*InsnID*/0, /*OldInsnID*/0, /*OpIdx*/6, /*OperandRenderer*/GIMT_Encode2(GICR_renderExtractSWZ), // auxiliary
          GIR_MergeMemOperands, /*InsnID*/0, /*NumInsns*/1, /*MergeInsnID's*/0,
          GIR_ConstrainSelectedInstOperands, /*InsnID*/0,
          GIR_EraseFromParent, /*InsnID*/0,
          // GIR_Coverage, 4499,
          GIR_Done,
        // Label 7069: @519634
        GIM_Try, /*On fail goto*//*Label 7070*/ GIMT_Encode4(519692), // Rule ID 4503 //
          GIM_CheckComplexPattern, /*MI*/0, /*Op*/4, /*Renderer*/GIMT_Encode2(0), GIMT_Encode2(GICP_gi_buf_soffset),
          // (SIbuffer_store_short i32:{ *:[i32] }:$vdata, v4i32:{ *:[v4i32] }:$rsrc, i32:{ *:[i32] }:$vindex, 0:{ *:[i32] }, (BUFSOffset:{ *:[i32] } i32:{ *:[i32] }:$soffset), (timm:{ *:[i32] }):$offset, (timm:{ *:[i32] }):$auxiliary, (timm:{ *:[i1] }))  =>  (BUFFER_STORE_SHORT_VBUFFER_IDXEN_exact anonymous_15037:{ *:[i32] }:$vdata, VGPR_32:{ *:[i32] }:$vindex, SReg_128:{ *:[v4i32] }:$rsrc, SCSrc_b32:{ *:[i32] }:$soffset, (timm:{ *:[i32] }):$offset, (extract_cpol:{ *:[i32] } ?:{ *:[i32] }:$auxiliary), (extract_swz:{ *:[i1] } ?:{ *:[i32] }:$auxiliary))
          GIR_BuildMI, /*InsnID*/0, /*Opcode*/GIMT_Encode2(AMDGPU::BUFFER_STORE_SHORT_VBUFFER_IDXEN_exact),
          GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/0, // vdata
          GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/2, // vindex
          GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/1, // rsrc
          GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/0, // soffset
          GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/5, // offset
          GIR_CustomOperandRenderer, /*InsnID*/0, /*OldInsnID*/0, /*OpIdx*/6, /*OperandRenderer*/GIMT_Encode2(GICR_renderExtractCPol), // auxiliary
          GIR_CustomOperandRenderer, /*InsnID*/0, /*OldInsnID*/0, /*OpIdx*/6, /*OperandRenderer*/GIMT_Encode2(GICR_renderExtractSWZ), // auxiliary
          GIR_MergeMemOperands, /*InsnID*/0, /*NumInsns*/1, /*MergeInsnID's*/0,
          GIR_ConstrainSelectedInstOperands, /*InsnID*/0,
          GIR_EraseFromParent, /*InsnID*/0,
          // GIR_Coverage, 4503,
          GIR_Done,
        // Label 7070: @519692
        GIM_Reject,
      // Label 7068: @519693
      GIM_Try, /*On fail goto*//*Label 7071*/ GIMT_Encode4(519907),
        GIM_CheckIsImm, /*MI*/0, /*Op*/5,
        GIM_CheckIsImm, /*MI*/0, /*Op*/6,
        GIM_CheckIsImm, /*MI*/0, /*Op*/7,
        GIM_Try, /*On fail goto*//*Label 7072*/ GIMT_Encode4(519808), // Rule ID 4500 //
          GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasUnrestrictedSOffset),
          GIM_CheckComplexPattern, /*MI*/0, /*Op*/4, /*Renderer*/GIMT_Encode2(0), GIMT_Encode2(GICP_gi_buf_soffset),
          // (SIbuffer_store_short i32:{ *:[i32] }:$vdata, v4i32:{ *:[v4i32] }:$rsrc, i32:{ *:[i32] }:$vindex, i32:{ *:[i32] }:$voffset, (BUFSOffset:{ *:[i32] } i32:{ *:[i32] }:$soffset), (timm:{ *:[i32] }):$offset, (timm:{ *:[i32] }):$auxiliary, (timm:{ *:[i1] }))  =>  (BUFFER_STORE_SHORT_BOTHEN_exact anonymous_15037:{ *:[i32] }:$vdata, (REG_SEQUENCE:{ *:[i64] } VReg_64:{ *:[i32] }, VGPR_32:{ *:[i32] }:$vindex, sub0:{ *:[i32] }, VGPR_32:{ *:[i32] }:$voffset, sub1:{ *:[i32] }), SReg_128:{ *:[v4i32] }:$rsrc, SCSrc_b32:{ *:[i32] }:$soffset, (timm:{ *:[i32] }):$offset, (extract_cpol:{ *:[i32] } ?:{ *:[i32] }:$auxiliary), (extract_swz:{ *:[i1] } ?:{ *:[i32] }:$auxiliary))
          GIR_MakeTempReg, /*TempRegID*/0, /*TypeID*/GILLT_s64,
          GIR_BuildMI, /*InsnID*/1, /*Opcode*/GIMT_Encode2(TargetOpcode::REG_SEQUENCE),
          GIR_AddTempRegister, /*InsnID*/1, /*TempRegID*/0, /*TempRegFlags*/GIMT_Encode2(RegState::Define),
          GIR_Copy, /*NewInsnID*/1, /*OldInsnID*/0, /*OpIdx*/2, // vindex
          GIR_AddImm8, /*InsnID*/1, /*SubRegIndex*/3,
          GIR_Copy, /*NewInsnID*/1, /*OldInsnID*/0, /*OpIdx*/3, // voffset
          GIR_AddImm8, /*InsnID*/1, /*SubRegIndex*/11,
          GIR_ConstrainOperandRC, /*InsnID*/1, /*Op*/0, GIMT_Encode2(AMDGPU::VReg_64RegClassID),
          GIR_ConstrainOperandRC, /*InsnID*/1, /*Op*/1, GIMT_Encode2(AMDGPU::VGPR_32RegClassID),
          GIR_ConstrainOperandRC, /*InsnID*/1, /*Op*/3, GIMT_Encode2(AMDGPU::VGPR_32RegClassID),
          GIR_BuildMI, /*InsnID*/0, /*Opcode*/GIMT_Encode2(AMDGPU::BUFFER_STORE_SHORT_BOTHEN_exact),
          GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/0, // vdata
          GIR_AddSimpleTempRegister, /*InsnID*/0, /*TempRegID*/0,
          GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/1, // rsrc
          GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/0, // soffset
          GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/5, // offset
          GIR_CustomOperandRenderer, /*InsnID*/0, /*OldInsnID*/0, /*OpIdx*/6, /*OperandRenderer*/GIMT_Encode2(GICR_renderExtractCPol), // auxiliary
          GIR_CustomOperandRenderer, /*InsnID*/0, /*OldInsnID*/0, /*OpIdx*/6, /*OperandRenderer*/GIMT_Encode2(GICR_renderExtractSWZ), // auxiliary
          GIR_MergeMemOperands, /*InsnID*/0, /*NumInsns*/1, /*MergeInsnID's*/0,
          GIR_ConstrainSelectedInstOperands, /*InsnID*/0,
          GIR_EraseFromParent, /*InsnID*/0,
          // GIR_Coverage, 4500,
          GIR_Done,
        // Label 7072: @519808
        GIM_Try, /*On fail goto*//*Label 7073*/ GIMT_Encode4(519906), // Rule ID 4504 //
          GIM_CheckComplexPattern, /*MI*/0, /*Op*/4, /*Renderer*/GIMT_Encode2(0), GIMT_Encode2(GICP_gi_buf_soffset),
          // (SIbuffer_store_short i32:{ *:[i32] }:$vdata, v4i32:{ *:[v4i32] }:$rsrc, i32:{ *:[i32] }:$vindex, i32:{ *:[i32] }:$voffset, (BUFSOffset:{ *:[i32] } i32:{ *:[i32] }:$soffset), (timm:{ *:[i32] }):$offset, (timm:{ *:[i32] }):$auxiliary, (timm:{ *:[i1] }))  =>  (BUFFER_STORE_SHORT_VBUFFER_BOTHEN_exact anonymous_15037:{ *:[i32] }:$vdata, (REG_SEQUENCE:{ *:[i64] } VReg_64:{ *:[i32] }, VGPR_32:{ *:[i32] }:$vindex, sub0:{ *:[i32] }, VGPR_32:{ *:[i32] }:$voffset, sub1:{ *:[i32] }), SReg_128:{ *:[v4i32] }:$rsrc, SCSrc_b32:{ *:[i32] }:$soffset, (timm:{ *:[i32] }):$offset, (extract_cpol:{ *:[i32] } ?:{ *:[i32] }:$auxiliary), (extract_swz:{ *:[i1] } ?:{ *:[i32] }:$auxiliary))
          GIR_MakeTempReg, /*TempRegID*/0, /*TypeID*/GILLT_s64,
          GIR_BuildMI, /*InsnID*/1, /*Opcode*/GIMT_Encode2(TargetOpcode::REG_SEQUENCE),
          GIR_AddTempRegister, /*InsnID*/1, /*TempRegID*/0, /*TempRegFlags*/GIMT_Encode2(RegState::Define),
          GIR_Copy, /*NewInsnID*/1, /*OldInsnID*/0, /*OpIdx*/2, // vindex
          GIR_AddImm8, /*InsnID*/1, /*SubRegIndex*/3,
          GIR_Copy, /*NewInsnID*/1, /*OldInsnID*/0, /*OpIdx*/3, // voffset
          GIR_AddImm8, /*InsnID*/1, /*SubRegIndex*/11,
          GIR_ConstrainOperandRC, /*InsnID*/1, /*Op*/0, GIMT_Encode2(AMDGPU::VReg_64RegClassID),
          GIR_ConstrainOperandRC, /*InsnID*/1, /*Op*/1, GIMT_Encode2(AMDGPU::VGPR_32RegClassID),
          GIR_ConstrainOperandRC, /*InsnID*/1, /*Op*/3, GIMT_Encode2(AMDGPU::VGPR_32RegClassID),
          GIR_BuildMI, /*InsnID*/0, /*Opcode*/GIMT_Encode2(AMDGPU::BUFFER_STORE_SHORT_VBUFFER_BOTHEN_exact),
          GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/0, // vdata
          GIR_AddSimpleTempRegister, /*InsnID*/0, /*TempRegID*/0,
          GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/1, // rsrc
          GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/0, // soffset
          GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/5, // offset
          GIR_CustomOperandRenderer, /*InsnID*/0, /*OldInsnID*/0, /*OpIdx*/6, /*OperandRenderer*/GIMT_Encode2(GICR_renderExtractCPol), // auxiliary
          GIR_CustomOperandRenderer, /*InsnID*/0, /*OldInsnID*/0, /*OpIdx*/6, /*OperandRenderer*/GIMT_Encode2(GICR_renderExtractSWZ), // auxiliary
          GIR_MergeMemOperands, /*InsnID*/0, /*NumInsns*/1, /*MergeInsnID's*/0,
          GIR_ConstrainSelectedInstOperands, /*InsnID*/0,
          GIR_EraseFromParent, /*InsnID*/0,
          // GIR_Coverage, 4504,
          GIR_Done,
        // Label 7073: @519906
        GIM_Reject,
      // Label 7071: @519907
      GIM_Reject,
    // Label 7062: @519908
    GIM_Reject,
    // Label 137: @519909
    GIM_SwitchType, /*MI*/0, /*Op*/0, /*[*/GIMT_Encode2(8), GIMT_Encode2(12), /*)*//*default:*//*Label 7078*/ GIMT_Encode4(520924),
    /*GILLT_s16*//*Label 7074*/ GIMT_Encode4(519936),
    /*GILLT_s32*//*Label 7075*/ GIMT_Encode4(520124),
    /*GILLT_s64*//*Label 7076*/ GIMT_Encode4(520185),
    /*GILLT_v2s16*//*Label 7077*/ GIMT_Encode4(520309),
    // Label 7074: @519936
    GIM_Try, /*On fail goto*//*Label 7079*/ GIMT_Encode4(520123),
      GIM_CheckType, /*MI*/0, /*Op*/1, /*Type*/GILLT_s16,
      GIM_Try, /*On fail goto*//*Label 7080*/ GIMT_Encode4(520004), // Rule ID 6201 //
        GIM_CheckFeatures, GIMT_Encode2(GIFBS_NotHasTrue16BitInsts),
        GIM_CheckRegBankForClass, /*MI*/0, /*Op*/0, /*RC*/GIMT_Encode2(AMDGPU::VGPR_32RegClassID),
        GIM_CheckComplexPattern, /*MI*/0, /*Op*/1, /*Renderer*/GIMT_Encode2(0), GIMT_Encode2(GICP_gi_vop3mods),
        // (AMDGPUclamp:{ *:[f16] } (VOP3Mods:{ *:[f16] } f16:{ *:[f16] }:$src0, i32:{ *:[i32] }:$src0_modifiers))  =>  (V_MAX_F16_e64:{ *:[f16] } i32:{ *:[i32] }:$src0_modifiers, f16:{ *:[f16] }:$src0, i32:{ *:[i32] }:$src0_modifiers, f16:{ *:[f16] }:$src0, 1:{ *:[i1] }, 0:{ *:[i32] })
        GIR_BuildMI, /*InsnID*/0, /*Opcode*/GIMT_Encode2(AMDGPU::V_MAX_F16_e64),
        GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/0, // DstI[vdst]
        GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/1, // src0_modifiers
        GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/0, // src0
        GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/1, // src0_modifiers
        GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/0, // src0
        GIR_AddImm8, /*InsnID*/0, /*Imm*/1,
        GIR_AddImm8, /*InsnID*/0, /*Imm*/0,
        GIR_ConstrainSelectedInstOperands, /*InsnID*/0,
        GIR_EraseFromParent, /*InsnID*/0,
        // GIR_Coverage, 6201,
        GIR_Done,
      // Label 7080: @520004
      GIM_Try, /*On fail goto*//*Label 7081*/ GIMT_Encode4(520063), // Rule ID 6202 //
        GIM_CheckFeatures, GIMT_Encode2(GIFBS_UseRealTrue16Insts),
        GIM_CheckRegBankForClass, /*MI*/0, /*Op*/0, /*RC*/GIMT_Encode2(AMDGPU::VGPR_16RegClassID),
        GIM_CheckComplexPattern, /*MI*/0, /*Op*/1, /*Renderer*/GIMT_Encode2(0), GIMT_Encode2(GICP_gi_vop3mods),
        // (AMDGPUclamp:{ *:[f16] } (VOP3Mods:{ *:[f16] } f16:{ *:[f16] }:$src0, i32:{ *:[i32] }:$src0_modifiers))  =>  (V_MAX_F16_t16_e64:{ *:[f16] } i32:{ *:[i32] }:$src0_modifiers, f16:{ *:[f16] }:$src0, i32:{ *:[i32] }:$src0_modifiers, f16:{ *:[f16] }:$src0, 1:{ *:[i1] }, 0:{ *:[i32] })
        GIR_BuildMI, /*InsnID*/0, /*Opcode*/GIMT_Encode2(AMDGPU::V_MAX_F16_t16_e64),
        GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/0, // DstI[vdst]
        GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/1, // src0_modifiers
        GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/0, // src0
        GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/1, // src0_modifiers
        GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/0, // src0
        GIR_AddImm8, /*InsnID*/0, /*Imm*/1,
        GIR_AddImm8, /*InsnID*/0, /*Imm*/0,
        GIR_ConstrainSelectedInstOperands, /*InsnID*/0,
        GIR_EraseFromParent, /*InsnID*/0,
        // GIR_Coverage, 6202,
        GIR_Done,
      // Label 7081: @520063
      GIM_Try, /*On fail goto*//*Label 7082*/ GIMT_Encode4(520122), // Rule ID 6203 //
        GIM_CheckFeatures, GIMT_Encode2(GIFBS_UseFakeTrue16Insts),
        GIM_CheckRegBankForClass, /*MI*/0, /*Op*/0, /*RC*/GIMT_Encode2(AMDGPU::VGPR_32RegClassID),
        GIM_CheckComplexPattern, /*MI*/0, /*Op*/1, /*Renderer*/GIMT_Encode2(0), GIMT_Encode2(GICP_gi_vop3mods),
        // (AMDGPUclamp:{ *:[f16] } (VOP3Mods:{ *:[f16] } f16:{ *:[f16] }:$src0, i32:{ *:[i32] }:$src0_modifiers))  =>  (V_MAX_F16_fake16_e64:{ *:[f16] } i32:{ *:[i32] }:$src0_modifiers, f16:{ *:[f16] }:$src0, i32:{ *:[i32] }:$src0_modifiers, f16:{ *:[f16] }:$src0, 1:{ *:[i1] }, 0:{ *:[i32] })
        GIR_BuildMI, /*InsnID*/0, /*Opcode*/GIMT_Encode2(AMDGPU::V_MAX_F16_fake16_e64),
        GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/0, // DstI[vdst]
        GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/1, // src0_modifiers
        GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/0, // src0
        GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/1, // src0_modifiers
        GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/0, // src0
        GIR_AddImm8, /*InsnID*/0, /*Imm*/1,
        GIR_AddImm8, /*InsnID*/0, /*Imm*/0,
        GIR_ConstrainSelectedInstOperands, /*InsnID*/0,
        GIR_EraseFromParent, /*InsnID*/0,
        // GIR_Coverage, 6203,
        GIR_Done,
      // Label 7082: @520122
      GIM_Reject,
    // Label 7079: @520123
    GIM_Reject,
    // Label 7075: @520124
    GIM_Try, /*On fail goto*//*Label 7083*/ GIMT_Encode4(520184), // Rule ID 6198 //
      GIM_CheckType, /*MI*/0, /*Op*/1, /*Type*/GILLT_s32,
      GIM_CheckRegBankForClass, /*MI*/0, /*Op*/0, /*RC*/GIMT_Encode2(AMDGPU::VGPR_32RegClassID),
      GIM_CheckComplexPattern, /*MI*/0, /*Op*/1, /*Renderer*/GIMT_Encode2(0), GIMT_Encode2(GICP_gi_vop3mods),
      // (AMDGPUclamp:{ *:[f32] } (VOP3Mods:{ *:[f32] } f32:{ *:[f32] }:$src0, i32:{ *:[i32] }:$src0_modifiers))  =>  (V_MAX_F32_e64:{ *:[f32] } i32:{ *:[i32] }:$src0_modifiers, f32:{ *:[f32] }:$src0, i32:{ *:[i32] }:$src0_modifiers, f32:{ *:[f32] }:$src0, 1:{ *:[i1] }, 0:{ *:[i32] })
      GIR_BuildMI, /*InsnID*/0, /*Opcode*/GIMT_Encode2(AMDGPU::V_MAX_F32_e64),
      GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/0, // DstI[vdst]
      GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/1, // src0_modifiers
      GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/0, // src0
      GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/1, // src0_modifiers
      GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/0, // src0
      GIR_AddImm8, /*InsnID*/0, /*Imm*/1,
      GIR_AddImm8, /*InsnID*/0, /*Imm*/0,
      GIR_ConstrainSelectedInstOperands, /*InsnID*/0,
      GIR_EraseFromParent, /*InsnID*/0,
      // GIR_Coverage, 6198,
      GIR_Done,
    // Label 7083: @520184
    GIM_Reject,
    // Label 7076: @520185
    GIM_Try, /*On fail goto*//*Label 7084*/ GIMT_Encode4(520308),
      GIM_CheckType, /*MI*/0, /*Op*/1, /*Type*/GILLT_s64,
      GIM_CheckRegBankForClass, /*MI*/0, /*Op*/0, /*RC*/GIMT_Encode2(AMDGPU::VReg_64RegClassID),
      GIM_Try, /*On fail goto*//*Label 7085*/ GIMT_Encode4(520253), // Rule ID 6199 //
        GIM_CheckFeatures, GIMT_Encode2(GIFBS_isNotGFX12Plus),
        GIM_CheckComplexPattern, /*MI*/0, /*Op*/1, /*Renderer*/GIMT_Encode2(0), GIMT_Encode2(GICP_gi_vop3mods),
        // (AMDGPUclamp:{ *:[f64] } (VOP3Mods:{ *:[f64] } f64:{ *:[f64] }:$src0, i32:{ *:[i32] }:$src0_modifiers))  =>  (V_MAX_F64_e64:{ *:[f64] } i32:{ *:[i32] }:$src0_modifiers, f64:{ *:[f64] }:$src0, i32:{ *:[i32] }:$src0_modifiers, f64:{ *:[f64] }:$src0, 1:{ *:[i1] }, 0:{ *:[i32] })
        GIR_BuildMI, /*InsnID*/0, /*Opcode*/GIMT_Encode2(AMDGPU::V_MAX_F64_e64),
        GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/0, // DstI[vdst]
        GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/1, // src0_modifiers
        GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/0, // src0
        GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/1, // src0_modifiers
        GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/0, // src0
        GIR_AddImm8, /*InsnID*/0, /*Imm*/1,
        GIR_AddImm8, /*InsnID*/0, /*Imm*/0,
        GIR_ConstrainSelectedInstOperands, /*InsnID*/0,
        GIR_EraseFromParent, /*InsnID*/0,
        // GIR_Coverage, 6199,
        GIR_Done,
      // Label 7085: @520253
      GIM_Try, /*On fail goto*//*Label 7086*/ GIMT_Encode4(520307), // Rule ID 6200 //
        GIM_CheckFeatures, GIMT_Encode2(GIFBS_isGFX12Plus),
        GIM_CheckComplexPattern, /*MI*/0, /*Op*/1, /*Renderer*/GIMT_Encode2(0), GIMT_Encode2(GICP_gi_vop3mods),
        // (AMDGPUclamp:{ *:[f64] } (VOP3Mods:{ *:[f64] } f64:{ *:[f64] }:$src0, i32:{ *:[i32] }:$src0_modifiers))  =>  (V_MAX_NUM_F64_e64:{ *:[f64] } i32:{ *:[i32] }:$src0_modifiers, f64:{ *:[f64] }:$src0, i32:{ *:[i32] }:$src0_modifiers, f64:{ *:[f64] }:$src0, 1:{ *:[i1] }, 0:{ *:[i32] })
        GIR_BuildMI, /*InsnID*/0, /*Opcode*/GIMT_Encode2(AMDGPU::V_MAX_NUM_F64_e64),
        GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/0, // DstI[vdst]
        GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/1, // src0_modifiers
        GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/0, // src0
        GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/1, // src0_modifiers
        GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/0, // src0
        GIR_AddImm8, /*InsnID*/0, /*Imm*/1,
        GIR_AddImm8, /*InsnID*/0, /*Imm*/0,
        GIR_ConstrainSelectedInstOperands, /*InsnID*/0,
        GIR_EraseFromParent, /*InsnID*/0,
        // GIR_Coverage, 6200,
        GIR_Done,
      // Label 7086: @520307
      GIM_Reject,
    // Label 7084: @520308
    GIM_Reject,
    // Label 7077: @520309
    GIM_Try, /*On fail goto*//*Label 7087*/ GIMT_Encode4(520923),
      GIM_CheckType, /*MI*/0, /*Op*/1, /*Type*/GILLT_v2s16,
      GIM_CheckRegBankForClass, /*MI*/0, /*Op*/0, /*RC*/GIMT_Encode2(AMDGPU::VGPR_32RegClassID),
      GIM_Try, /*On fail goto*//*Label 7088*/ GIMT_Encode4(520591), // Rule ID 2264 //
        GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasFmaMixInsts),
        GIM_RecordInsn, /*DefineMI*/1, /*MI*/0, /*OpIdx*/1, // MIs[1]
        GIM_CheckOpcode, /*MI*/1, GIMT_Encode2(TargetOpcode::G_BUILD_VECTOR),
        GIM_CheckNumOperands, /*MI*/1, /*Expected*/3,
        GIM_CheckType, /*MI*/1, /*Op*/1, /*Type*/GILLT_s16,
        GIM_CheckType, /*MI*/1, /*Op*/2, /*Type*/GILLT_s16,
        GIM_RecordInsn, /*DefineMI*/2, /*MI*/1, /*OpIdx*/1, // MIs[2]
        GIM_CheckOpcode, /*MI*/2, GIMT_Encode2(TargetOpcode::G_FPTRUNC),
        GIM_CheckType, /*MI*/2, /*Op*/1, /*Type*/GILLT_s32,
        GIM_RecordInsn, /*DefineMI*/3, /*MI*/2, /*OpIdx*/1, // MIs[3]
        GIM_CheckOpcode, /*MI*/3, GIMT_Encode2(TargetOpcode::G_FMA),
        GIM_CheckType, /*MI*/3, /*Op*/1, /*Type*/GILLT_s32,
        GIM_CheckType, /*MI*/3, /*Op*/2, /*Type*/GILLT_s32,
        GIM_CheckType, /*MI*/3, /*Op*/3, /*Type*/GILLT_s32,
        GIM_RecordInsn, /*DefineMI*/4, /*MI*/1, /*OpIdx*/2, // MIs[4]
        GIM_CheckOpcode, /*MI*/4, GIMT_Encode2(TargetOpcode::G_FPTRUNC),
        GIM_CheckType, /*MI*/4, /*Op*/1, /*Type*/GILLT_s32,
        GIM_RecordInsn, /*DefineMI*/5, /*MI*/4, /*OpIdx*/1, // MIs[5]
        GIM_CheckOpcode, /*MI*/5, GIMT_Encode2(TargetOpcode::G_FMA),
        GIM_CheckType, /*MI*/5, /*Op*/1, /*Type*/GILLT_s32,
        GIM_CheckType, /*MI*/5, /*Op*/2, /*Type*/GILLT_s32,
        GIM_CheckType, /*MI*/5, /*Op*/3, /*Type*/GILLT_s32,
        GIM_CheckIsSafeToFold, /*InsnID*/1,
        GIM_CheckIsSafeToFold, /*InsnID*/2,
        GIM_CheckIsSafeToFold, /*InsnID*/3,
        GIM_CheckIsSafeToFold, /*InsnID*/4,
        GIM_CheckIsSafeToFold, /*InsnID*/5,
        GIM_CheckComplexPattern, /*MI*/3, /*Op*/1, /*Renderer*/GIMT_Encode2(0), GIMT_Encode2(GICP_gi_vop3_mad_mix_mods),
        GIM_CheckComplexPattern, /*MI*/3, /*Op*/2, /*Renderer*/GIMT_Encode2(1), GIMT_Encode2(GICP_gi_vop3_mad_mix_mods),
        GIM_CheckComplexPattern, /*MI*/3, /*Op*/3, /*Renderer*/GIMT_Encode2(2), GIMT_Encode2(GICP_gi_vop3_mad_mix_mods),
        GIM_CheckComplexPattern, /*MI*/5, /*Op*/1, /*Renderer*/GIMT_Encode2(3), GIMT_Encode2(GICP_gi_vop3_mad_mix_mods),
        GIM_CheckComplexPattern, /*MI*/5, /*Op*/2, /*Renderer*/GIMT_Encode2(4), GIMT_Encode2(GICP_gi_vop3_mad_mix_mods),
        GIM_CheckComplexPattern, /*MI*/5, /*Op*/3, /*Renderer*/GIMT_Encode2(5), GIMT_Encode2(GICP_gi_vop3_mad_mix_mods),
        // (AMDGPUclamp:{ *:[v2f16] } (build_vector:{ *:[v2f16] } (fpround:{ *:[f16] } (fma:{ *:[f32] } (VOP3PMadMixMods:{ *:[f32] } f16:{ *:[f16] }:$lo_src0, i32:{ *:[i32] }:$lo_src0_modifiers), (VOP3PMadMixMods:{ *:[f32] } f16:{ *:[f16] }:$lo_src1, i32:{ *:[i32] }:$lo_src1_modifiers), (VOP3PMadMixMods:{ *:[f32] } f16:{ *:[f16] }:$lo_src2, i32:{ *:[i32] }:$lo_src2_modifiers))), (fpround:{ *:[f16] } (fma:{ *:[f32] } (VOP3PMadMixMods:{ *:[f32] } f16:{ *:[f16] }:$hi_src0, i32:{ *:[i32] }:$hi_src0_modifiers), (VOP3PMadMixMods:{ *:[f32] } f16:{ *:[f16] }:$hi_src1, i32:{ *:[i32] }:$hi_src1_modifiers), (VOP3PMadMixMods:{ *:[f32] } f16:{ *:[f16] }:$hi_src2, i32:{ *:[i32] }:$hi_src2_modifiers)))))  =>  (V_FMA_MIXHI_F16:{ *:[v2f16] } ?:{ *:[i32] }:$hi_src0_modifiers, ?:{ *:[f16] }:$hi_src0, ?:{ *:[i32] }:$hi_src1_modifiers, ?:{ *:[f16] }:$hi_src1, ?:{ *:[i32] }:$hi_src2_modifiers, ?:{ *:[f16] }:$hi_src2, 1:{ *:[i1] }, (V_FMA_MIXLO_F16:{ *:[i16] } ?:{ *:[i32] }:$lo_src0_modifiers, ?:{ *:[f16] }:$lo_src0, ?:{ *:[i32] }:$lo_src1_modifiers, ?:{ *:[f16] }:$lo_src1, ?:{ *:[i32] }:$lo_src2_modifiers, ?:{ *:[f16] }:$lo_src2, 1:{ *:[i1] }, (IMPLICIT_DEF:{ *:[i32] })))
        GIR_MakeTempReg, /*TempRegID*/0, /*TypeID*/GILLT_s16,
        GIR_MakeTempReg, /*TempRegID*/1, /*TypeID*/GILLT_s32,
        GIR_BuildMI, /*InsnID*/2, /*Opcode*/GIMT_Encode2(TargetOpcode::IMPLICIT_DEF),
        GIR_AddTempRegister, /*InsnID*/2, /*TempRegID*/1, /*TempRegFlags*/GIMT_Encode2(RegState::Define),
        GIR_ConstrainSelectedInstOperands, /*InsnID*/2,
        GIR_BuildMI, /*InsnID*/1, /*Opcode*/GIMT_Encode2(AMDGPU::V_FMA_MIXLO_F16),
        GIR_AddTempRegister, /*InsnID*/1, /*TempRegID*/0, /*TempRegFlags*/GIMT_Encode2(RegState::Define),
        GIR_ComplexSubOperandRenderer, /*InsnID*/1, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/1, // lo_src0_modifiers
        GIR_ComplexSubOperandRenderer, /*InsnID*/1, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/0, // lo_src0
        GIR_ComplexSubOperandRenderer, /*InsnID*/1, /*RendererID*/GIMT_Encode2(1), /*SubOperand*/1, // lo_src1_modifiers
        GIR_ComplexSubOperandRenderer, /*InsnID*/1, /*RendererID*/GIMT_Encode2(1), /*SubOperand*/0, // lo_src1
        GIR_ComplexSubOperandRenderer, /*InsnID*/1, /*RendererID*/GIMT_Encode2(2), /*SubOperand*/1, // lo_src2_modifiers
        GIR_ComplexSubOperandRenderer, /*InsnID*/1, /*RendererID*/GIMT_Encode2(2), /*SubOperand*/0, // lo_src2
        GIR_AddImm8, /*InsnID*/1, /*Imm*/1,
        GIR_AddSimpleTempRegister, /*InsnID*/1, /*TempRegID*/1,
        GIR_AddImm8, /*InsnID*/1, /*Imm*/0,
        GIR_AddImm8, /*InsnID*/1, /*Imm*/0,
        GIR_ConstrainSelectedInstOperands, /*InsnID*/1,
        GIR_BuildMI, /*InsnID*/0, /*Opcode*/GIMT_Encode2(AMDGPU::V_FMA_MIXHI_F16),
        GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/0, // DstI[vdst]
        GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(3), /*SubOperand*/1, // hi_src0_modifiers
        GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(3), /*SubOperand*/0, // hi_src0
        GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(4), /*SubOperand*/1, // hi_src1_modifiers
        GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(4), /*SubOperand*/0, // hi_src1
        GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(5), /*SubOperand*/1, // hi_src2_modifiers
        GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(5), /*SubOperand*/0, // hi_src2
        GIR_AddImm8, /*InsnID*/0, /*Imm*/1,
        GIR_AddSimpleTempRegister, /*InsnID*/0, /*TempRegID*/0,
        GIR_AddImm8, /*InsnID*/0, /*Imm*/0,
        GIR_AddImm8, /*InsnID*/0, /*Imm*/0,
        GIR_ConstrainSelectedInstOperands, /*InsnID*/0,
        GIR_EraseFromParent, /*InsnID*/0,
        // GIR_Coverage, 2264,
        GIR_Done,
      // Label 7088: @520591
      GIM_Try, /*On fail goto*//*Label 7089*/ GIMT_Encode4(520859), // Rule ID 2255 //
        GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasMadMixInsts_NoFP32Denormals),
        GIM_RecordInsn, /*DefineMI*/1, /*MI*/0, /*OpIdx*/1, // MIs[1]
        GIM_CheckOpcode, /*MI*/1, GIMT_Encode2(TargetOpcode::G_BUILD_VECTOR),
        GIM_CheckNumOperands, /*MI*/1, /*Expected*/3,
        GIM_CheckType, /*MI*/1, /*Op*/1, /*Type*/GILLT_s16,
        GIM_CheckType, /*MI*/1, /*Op*/2, /*Type*/GILLT_s16,
        GIM_RecordInsn, /*DefineMI*/2, /*MI*/1, /*OpIdx*/1, // MIs[2]
        GIM_CheckOpcode, /*MI*/2, GIMT_Encode2(TargetOpcode::G_FPTRUNC),
        GIM_CheckType, /*MI*/2, /*Op*/1, /*Type*/GILLT_s32,
        GIM_RecordInsn, /*DefineMI*/3, /*MI*/2, /*OpIdx*/1, // MIs[3]
        GIM_CheckOpcode, /*MI*/3, GIMT_Encode2(TargetOpcode::G_FMAD),
        GIM_CheckType, /*MI*/3, /*Op*/1, /*Type*/GILLT_s32,
        GIM_CheckType, /*MI*/3, /*Op*/2, /*Type*/GILLT_s32,
        GIM_CheckType, /*MI*/3, /*Op*/3, /*Type*/GILLT_s32,
        GIM_RecordInsn, /*DefineMI*/4, /*MI*/1, /*OpIdx*/2, // MIs[4]
        GIM_CheckOpcode, /*MI*/4, GIMT_Encode2(TargetOpcode::G_FPTRUNC),
        GIM_CheckType, /*MI*/4, /*Op*/1, /*Type*/GILLT_s32,
        GIM_RecordInsn, /*DefineMI*/5, /*MI*/4, /*OpIdx*/1, // MIs[5]
        GIM_CheckOpcode, /*MI*/5, GIMT_Encode2(TargetOpcode::G_FMAD),
        GIM_CheckType, /*MI*/5, /*Op*/1, /*Type*/GILLT_s32,
        GIM_CheckType, /*MI*/5, /*Op*/2, /*Type*/GILLT_s32,
        GIM_CheckType, /*MI*/5, /*Op*/3, /*Type*/GILLT_s32,
        GIM_CheckIsSafeToFold, /*InsnID*/1,
        GIM_CheckIsSafeToFold, /*InsnID*/2,
        GIM_CheckIsSafeToFold, /*InsnID*/3,
        GIM_CheckIsSafeToFold, /*InsnID*/4,
        GIM_CheckIsSafeToFold, /*InsnID*/5,
        GIM_CheckComplexPattern, /*MI*/3, /*Op*/1, /*Renderer*/GIMT_Encode2(0), GIMT_Encode2(GICP_gi_vop3_mad_mix_mods),
        GIM_CheckComplexPattern, /*MI*/3, /*Op*/2, /*Renderer*/GIMT_Encode2(1), GIMT_Encode2(GICP_gi_vop3_mad_mix_mods),
        GIM_CheckComplexPattern, /*MI*/3, /*Op*/3, /*Renderer*/GIMT_Encode2(2), GIMT_Encode2(GICP_gi_vop3_mad_mix_mods),
        GIM_CheckComplexPattern, /*MI*/5, /*Op*/1, /*Renderer*/GIMT_Encode2(3), GIMT_Encode2(GICP_gi_vop3_mad_mix_mods),
        GIM_CheckComplexPattern, /*MI*/5, /*Op*/2, /*Renderer*/GIMT_Encode2(4), GIMT_Encode2(GICP_gi_vop3_mad_mix_mods),
        GIM_CheckComplexPattern, /*MI*/5, /*Op*/3, /*Renderer*/GIMT_Encode2(5), GIMT_Encode2(GICP_gi_vop3_mad_mix_mods),
        // (AMDGPUclamp:{ *:[v2f16] } (build_vector:{ *:[v2f16] } (fpround:{ *:[f16] } (fmad:{ *:[f32] } (VOP3PMadMixMods:{ *:[f32] } f16:{ *:[f16] }:$lo_src0, i32:{ *:[i32] }:$lo_src0_modifiers), (VOP3PMadMixMods:{ *:[f32] } f16:{ *:[f16] }:$lo_src1, i32:{ *:[i32] }:$lo_src1_modifiers), (VOP3PMadMixMods:{ *:[f32] } f16:{ *:[f16] }:$lo_src2, i32:{ *:[i32] }:$lo_src2_modifiers))), (fpround:{ *:[f16] } (fmad:{ *:[f32] } (VOP3PMadMixMods:{ *:[f32] } f16:{ *:[f16] }:$hi_src0, i32:{ *:[i32] }:$hi_src0_modifiers), (VOP3PMadMixMods:{ *:[f32] } f16:{ *:[f16] }:$hi_src1, i32:{ *:[i32] }:$hi_src1_modifiers), (VOP3PMadMixMods:{ *:[f32] } f16:{ *:[f16] }:$hi_src2, i32:{ *:[i32] }:$hi_src2_modifiers)))))  =>  (V_MAD_MIXHI_F16:{ *:[v2f16] } ?:{ *:[i32] }:$hi_src0_modifiers, ?:{ *:[f16] }:$hi_src0, ?:{ *:[i32] }:$hi_src1_modifiers, ?:{ *:[f16] }:$hi_src1, ?:{ *:[i32] }:$hi_src2_modifiers, ?:{ *:[f16] }:$hi_src2, 1:{ *:[i1] }, (V_MAD_MIXLO_F16:{ *:[i16] } ?:{ *:[i32] }:$lo_src0_modifiers, ?:{ *:[f16] }:$lo_src0, ?:{ *:[i32] }:$lo_src1_modifiers, ?:{ *:[f16] }:$lo_src1, ?:{ *:[i32] }:$lo_src2_modifiers, ?:{ *:[f16] }:$lo_src2, 1:{ *:[i1] }, (IMPLICIT_DEF:{ *:[i32] })))
        GIR_MakeTempReg, /*TempRegID*/0, /*TypeID*/GILLT_s16,
        GIR_MakeTempReg, /*TempRegID*/1, /*TypeID*/GILLT_s32,
        GIR_BuildMI, /*InsnID*/2, /*Opcode*/GIMT_Encode2(TargetOpcode::IMPLICIT_DEF),
        GIR_AddTempRegister, /*InsnID*/2, /*TempRegID*/1, /*TempRegFlags*/GIMT_Encode2(RegState::Define),
        GIR_ConstrainSelectedInstOperands, /*InsnID*/2,
        GIR_BuildMI, /*InsnID*/1, /*Opcode*/GIMT_Encode2(AMDGPU::V_MAD_MIXLO_F16),
        GIR_AddTempRegister, /*InsnID*/1, /*TempRegID*/0, /*TempRegFlags*/GIMT_Encode2(RegState::Define),
        GIR_ComplexSubOperandRenderer, /*InsnID*/1, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/1, // lo_src0_modifiers
        GIR_ComplexSubOperandRenderer, /*InsnID*/1, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/0, // lo_src0
        GIR_ComplexSubOperandRenderer, /*InsnID*/1, /*RendererID*/GIMT_Encode2(1), /*SubOperand*/1, // lo_src1_modifiers
        GIR_ComplexSubOperandRenderer, /*InsnID*/1, /*RendererID*/GIMT_Encode2(1), /*SubOperand*/0, // lo_src1
        GIR_ComplexSubOperandRenderer, /*InsnID*/1, /*RendererID*/GIMT_Encode2(2), /*SubOperand*/1, // lo_src2_modifiers
        GIR_ComplexSubOperandRenderer, /*InsnID*/1, /*RendererID*/GIMT_Encode2(2), /*SubOperand*/0, // lo_src2
        GIR_AddImm8, /*InsnID*/1, /*Imm*/1,
        GIR_AddSimpleTempRegister, /*InsnID*/1, /*TempRegID*/1,
        GIR_AddImm8, /*InsnID*/1, /*Imm*/0,
        GIR_AddImm8, /*InsnID*/1, /*Imm*/0,
        GIR_ConstrainSelectedInstOperands, /*InsnID*/1,
        GIR_BuildMI, /*InsnID*/0, /*Opcode*/GIMT_Encode2(AMDGPU::V_MAD_MIXHI_F16),
        GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/0, // DstI[vdst]
        GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(3), /*SubOperand*/1, // hi_src0_modifiers
        GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(3), /*SubOperand*/0, // hi_src0
        GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(4), /*SubOperand*/1, // hi_src1_modifiers
        GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(4), /*SubOperand*/0, // hi_src1
        GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(5), /*SubOperand*/1, // hi_src2_modifiers
        GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(5), /*SubOperand*/0, // hi_src2
        GIR_AddImm8, /*InsnID*/0, /*Imm*/1,
        GIR_AddSimpleTempRegister, /*InsnID*/0, /*TempRegID*/0,
        GIR_AddImm8, /*InsnID*/0, /*Imm*/0,
        GIR_AddImm8, /*InsnID*/0, /*Imm*/0,
        GIR_ConstrainSelectedInstOperands, /*InsnID*/0,
        GIR_EraseFromParent, /*InsnID*/0,
        // GIR_Coverage, 2255,
        GIR_Done,
      // Label 7089: @520859
      GIM_Try, /*On fail goto*//*Label 7090*/ GIMT_Encode4(520922), // Rule ID 6204 //
        GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasVOP3PInsts),
        GIM_CheckComplexPattern, /*MI*/0, /*Op*/1, /*Renderer*/GIMT_Encode2(0), GIMT_Encode2(GICP_gi_vop3pmods),
        // (AMDGPUclamp:{ *:[v2f16] } (VOP3PMods:{ *:[v2f16] } v2f16:{ *:[v2f16] }:$src0, i32:{ *:[i32] }:$src0_modifiers))  =>  (V_PK_MAX_F16:{ *:[v2f16] } ?:{ *:[i32] }:$src0_modifiers, ?:{ *:[v2f16] }:$src0, ?:{ *:[i32] }:$src0_modifiers, ?:{ *:[v2f16] }:$src0, 1:{ *:[i1] })
        GIR_BuildMI, /*InsnID*/0, /*Opcode*/GIMT_Encode2(AMDGPU::V_PK_MAX_F16),
        GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/0, // DstI[vdst]
        GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/1, // src0_modifiers
        GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/0, // src0
        GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/1, // src0_modifiers
        GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/0, // src0
        GIR_AddImm8, /*InsnID*/0, /*Imm*/1,
        GIR_AddImm8, /*InsnID*/0, /*Imm*/0,
        GIR_AddImm8, /*InsnID*/0, /*Imm*/0,
        GIR_AddImm8, /*InsnID*/0, /*Imm*/0,
        GIR_AddImm8, /*InsnID*/0, /*Imm*/0,
        GIR_ConstrainSelectedInstOperands, /*InsnID*/0,
        GIR_EraseFromParent, /*InsnID*/0,
        // GIR_Coverage, 6204,
        GIR_Done,
      // Label 7090: @520922
      GIM_Reject,
    // Label 7087: @520923
    GIM_Reject,
    // Label 7078: @520924
    GIM_Reject,
    // Label 138: @520925
    GIM_Try, /*On fail goto*//*Label 7091*/ GIMT_Encode4(520978), // Rule ID 595 //
      GIM_CheckType, /*MI*/0, /*Op*/0, /*Type*/GILLT_s32,
      GIM_CheckType, /*MI*/0, /*Op*/1, /*Type*/GILLT_s32,
      GIM_CheckRegBankForClass, /*MI*/0, /*Op*/0, /*RC*/GIMT_Encode2(AMDGPU::VGPR_32RegClassID),
      GIM_CheckComplexPattern, /*MI*/0, /*Op*/1, /*Renderer*/GIMT_Encode2(0), GIMT_Encode2(GICP_gi_vop3mods0),
      // (AMDGPUcvt_f32_ubyte0:{ *:[f32] } (VOP3Mods0:{ *:[i32] } i32:{ *:[i32] }:$src0, i1:{ *:[i1] }:$clamp, i32:{ *:[i32] }:$omod))  =>  (V_CVT_F32_UBYTE0_e64:{ *:[f32] } i32:{ *:[i32] }:$src0, i1:{ *:[i1] }:$clamp, i32:{ *:[i32] }:$omod)
      GIR_BuildMI, /*InsnID*/0, /*Opcode*/GIMT_Encode2(AMDGPU::V_CVT_F32_UBYTE0_e64),
      GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/0, // DstI[vdst]
      GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/0, // src0
      GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/1, // clamp
      GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/2, // omod
      GIR_ConstrainSelectedInstOperands, /*InsnID*/0,
      GIR_EraseFromParent, /*InsnID*/0,
      // GIR_Coverage, 595,
      GIR_Done,
    // Label 7091: @520978
    GIM_Reject,
    // Label 139: @520979
    GIM_Try, /*On fail goto*//*Label 7092*/ GIMT_Encode4(521032), // Rule ID 596 //
      GIM_CheckType, /*MI*/0, /*Op*/0, /*Type*/GILLT_s32,
      GIM_CheckType, /*MI*/0, /*Op*/1, /*Type*/GILLT_s32,
      GIM_CheckRegBankForClass, /*MI*/0, /*Op*/0, /*RC*/GIMT_Encode2(AMDGPU::VGPR_32RegClassID),
      GIM_CheckComplexPattern, /*MI*/0, /*Op*/1, /*Renderer*/GIMT_Encode2(0), GIMT_Encode2(GICP_gi_vop3mods0),
      // (AMDGPUcvt_f32_ubyte1:{ *:[f32] } (VOP3Mods0:{ *:[i32] } i32:{ *:[i32] }:$src0, i1:{ *:[i1] }:$clamp, i32:{ *:[i32] }:$omod))  =>  (V_CVT_F32_UBYTE1_e64:{ *:[f32] } i32:{ *:[i32] }:$src0, i1:{ *:[i1] }:$clamp, i32:{ *:[i32] }:$omod)
      GIR_BuildMI, /*InsnID*/0, /*Opcode*/GIMT_Encode2(AMDGPU::V_CVT_F32_UBYTE1_e64),
      GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/0, // DstI[vdst]
      GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/0, // src0
      GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/1, // clamp
      GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/2, // omod
      GIR_ConstrainSelectedInstOperands, /*InsnID*/0,
      GIR_EraseFromParent, /*InsnID*/0,
      // GIR_Coverage, 596,
      GIR_Done,
    // Label 7092: @521032
    GIM_Reject,
    // Label 140: @521033
    GIM_Try, /*On fail goto*//*Label 7093*/ GIMT_Encode4(521086), // Rule ID 597 //
      GIM_CheckType, /*MI*/0, /*Op*/0, /*Type*/GILLT_s32,
      GIM_CheckType, /*MI*/0, /*Op*/1, /*Type*/GILLT_s32,
      GIM_CheckRegBankForClass, /*MI*/0, /*Op*/0, /*RC*/GIMT_Encode2(AMDGPU::VGPR_32RegClassID),
      GIM_CheckComplexPattern, /*MI*/0, /*Op*/1, /*Renderer*/GIMT_Encode2(0), GIMT_Encode2(GICP_gi_vop3mods0),
      // (AMDGPUcvt_f32_ubyte2:{ *:[f32] } (VOP3Mods0:{ *:[i32] } i32:{ *:[i32] }:$src0, i1:{ *:[i1] }:$clamp, i32:{ *:[i32] }:$omod))  =>  (V_CVT_F32_UBYTE2_e64:{ *:[f32] } i32:{ *:[i32] }:$src0, i1:{ *:[i1] }:$clamp, i32:{ *:[i32] }:$omod)
      GIR_BuildMI, /*InsnID*/0, /*Opcode*/GIMT_Encode2(AMDGPU::V_CVT_F32_UBYTE2_e64),
      GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/0, // DstI[vdst]
      GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/0, // src0
      GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/1, // clamp
      GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/2, // omod
      GIR_ConstrainSelectedInstOperands, /*InsnID*/0,
      GIR_EraseFromParent, /*InsnID*/0,
      // GIR_Coverage, 597,
      GIR_Done,
    // Label 7093: @521086
    GIM_Reject,
    // Label 141: @521087
    GIM_Try, /*On fail goto*//*Label 7094*/ GIMT_Encode4(521140), // Rule ID 598 //
      GIM_CheckType, /*MI*/0, /*Op*/0, /*Type*/GILLT_s32,
      GIM_CheckType, /*MI*/0, /*Op*/1, /*Type*/GILLT_s32,
      GIM_CheckRegBankForClass, /*MI*/0, /*Op*/0, /*RC*/GIMT_Encode2(AMDGPU::VGPR_32RegClassID),
      GIM_CheckComplexPattern, /*MI*/0, /*Op*/1, /*Renderer*/GIMT_Encode2(0), GIMT_Encode2(GICP_gi_vop3mods0),
      // (AMDGPUcvt_f32_ubyte3:{ *:[f32] } (VOP3Mods0:{ *:[i32] } i32:{ *:[i32] }:$src0, i1:{ *:[i1] }:$clamp, i32:{ *:[i32] }:$omod))  =>  (V_CVT_F32_UBYTE3_e64:{ *:[f32] } i32:{ *:[i32] }:$src0, i1:{ *:[i1] }:$clamp, i32:{ *:[i32] }:$omod)
      GIR_BuildMI, /*InsnID*/0, /*Opcode*/GIMT_Encode2(AMDGPU::V_CVT_F32_UBYTE3_e64),
      GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/0, // DstI[vdst]
      GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/0, // src0
      GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/1, // clamp
      GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/2, // omod
      GIR_ConstrainSelectedInstOperands, /*InsnID*/0,
      GIR_EraseFromParent, /*InsnID*/0,
      // GIR_Coverage, 598,
      GIR_Done,
    // Label 7094: @521140
    GIM_Reject,
    // Label 142: @521141
    GIM_Try, /*On fail goto*//*Label 7095*/ GIMT_Encode4(521175), // Rule ID 772 //
      GIM_CheckType, /*MI*/0, /*Op*/0, /*Type*/GILLT_v2s16,
      GIM_CheckType, /*MI*/0, /*Op*/1, /*Type*/GILLT_s32,
      GIM_CheckType, /*MI*/0, /*Op*/2, /*Type*/GILLT_s32,
      GIM_CheckRegBankForClass, /*MI*/0, /*Op*/0, /*RC*/GIMT_Encode2(AMDGPU::VGPR_32RegClassID),
      // (AMDGPUpk_i16_i32_impl:{ *:[v2i16] } i32:{ *:[i32] }:$src0, i32:{ *:[i32] }:$src1)  =>  (V_CVT_PK_I16_I32_e64:{ *:[v2i16] } i32:{ *:[i32] }:$src0, i32:{ *:[i32] }:$src1)
      GIR_MutateOpcode, /*InsnID*/0, /*RecycleInsnID*/0, /*Opcode*/GIMT_Encode2(AMDGPU::V_CVT_PK_I16_I32_e64),
      GIR_AddImplicitUse, /*InsnID*/0, GIMT_Encode2(AMDGPU::EXEC),
      GIR_ConstrainSelectedInstOperands, /*InsnID*/0,
      // GIR_Coverage, 772,
      GIR_Done,
    // Label 7095: @521175
    GIM_Reject,
    // Label 143: @521176
    GIM_Try, /*On fail goto*//*Label 7096*/ GIMT_Encode4(521290),
      GIM_CheckType, /*MI*/0, /*Op*/0, /*Type*/GILLT_s32,
      GIM_SwitchType, /*MI*/0, /*Op*/1, /*[*/GIMT_Encode2(9), GIMT_Encode2(11), /*)*//*default:*//*Label 7099*/ GIMT_Encode4(521250),
      /*GILLT_s32*//*Label 7097*/ GIMT_Encode4(521204),
      /*GILLT_s64*//*Label 7098*/ GIMT_Encode4(521227),
      // Label 7097: @521204
      GIM_Try, /*On fail goto*//*Label 7100*/ GIMT_Encode4(521226), // Rule ID 13 //
        GIM_CheckRegBankForClass, /*MI*/0, /*Op*/0, /*RC*/GIMT_Encode2(AMDGPU::SReg_32RegClassID),
        GIM_CheckCxxInsnPredicate, /*MI*/0, /*FnId*/GIMT_Encode2(GICXXPred_MI_Predicate_anonymous_17570),
        // (AMDGPUffbh_u32_impl:{ *:[i32] } i32:{ *:[i32] }:$src0)<<P:Predicate_anonymous_17570>>  =>  (S_FLBIT_I32_B32:{ *:[i32] } i32:{ *:[i32] }:$src0)
        GIR_MutateOpcode, /*InsnID*/0, /*RecycleInsnID*/0, /*Opcode*/GIMT_Encode2(AMDGPU::S_FLBIT_I32_B32),
        GIR_ConstrainSelectedInstOperands, /*InsnID*/0,
        // GIR_Coverage, 13,
        GIR_Done,
      // Label 7100: @521226
      GIM_Reject,
      // Label 7098: @521227
      GIM_Try, /*On fail goto*//*Label 7101*/ GIMT_Encode4(521249), // Rule ID 15 //
        GIM_CheckRegBankForClass, /*MI*/0, /*Op*/0, /*RC*/GIMT_Encode2(AMDGPU::SReg_32RegClassID),
        GIM_CheckCxxInsnPredicate, /*MI*/0, /*FnId*/GIMT_Encode2(GICXXPred_MI_Predicate_anonymous_17570),
        // (AMDGPUffbh_u32_impl:{ *:[i32] } i64:{ *:[i64] }:$src0)<<P:Predicate_anonymous_17570>>  =>  (S_FLBIT_I32_B64:{ *:[i32] } i64:{ *:[i64] }:$src0)
        GIR_MutateOpcode, /*InsnID*/0, /*RecycleInsnID*/0, /*Opcode*/GIMT_Encode2(AMDGPU::S_FLBIT_I32_B64),
        GIR_ConstrainSelectedInstOperands, /*InsnID*/0,
        // GIR_Coverage, 15,
        GIR_Done,
      // Label 7101: @521249
      GIM_Reject,
      // Label 7099: @521250
      GIM_Try, /*On fail goto*//*Label 7102*/ GIMT_Encode4(521289), // Rule ID 626 //
        GIM_CheckType, /*MI*/0, /*Op*/1, /*Type*/GILLT_s32,
        GIM_CheckRegBankForClass, /*MI*/0, /*Op*/0, /*RC*/GIMT_Encode2(AMDGPU::VGPR_32RegClassID),
        GIM_CheckComplexPattern, /*MI*/0, /*Op*/1, /*Renderer*/GIMT_Encode2(0), GIMT_Encode2(GICP_gi_vop3mods0),
        // (AMDGPUffbh_u32_impl:{ *:[i32] } (VOP3Mods0:{ *:[i32] } i32:{ *:[i32] }:$src0))  =>  (V_FFBH_U32_e64:{ *:[i32] } i32:{ *:[i32] }:$src0)
        GIR_BuildMI, /*InsnID*/0, /*Opcode*/GIMT_Encode2(AMDGPU::V_FFBH_U32_e64),
        GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/0, // DstI[vdst]
        GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/0, // src0
        GIR_ConstrainSelectedInstOperands, /*InsnID*/0,
        GIR_EraseFromParent, /*InsnID*/0,
        // GIR_Coverage, 626,
        GIR_Done,
      // Label 7102: @521289
      GIM_Reject,
    // Label 7096: @521290
    GIM_Reject,
    // Label 144: @521291
    GIM_Try, /*On fail goto*//*Label 7103*/ GIMT_Encode4(521401),
      GIM_CheckType, /*MI*/0, /*Op*/0, /*Type*/GILLT_s32,
      GIM_SwitchType, /*MI*/0, /*Op*/1, /*[*/GIMT_Encode2(9), GIMT_Encode2(11), /*)*//*default:*//*Label 7106*/ GIMT_Encode4(521400),
      /*GILLT_s32*//*Label 7104*/ GIMT_Encode4(521319),
      /*GILLT_s64*//*Label 7105*/ GIMT_Encode4(521377),
      // Label 7104: @521319
      GIM_Try, /*On fail goto*//*Label 7107*/ GIMT_Encode4(521341), // Rule ID 11 //
        GIM_CheckRegBankForClass, /*MI*/0, /*Op*/0, /*RC*/GIMT_Encode2(AMDGPU::SReg_32RegClassID),
        GIM_CheckCxxInsnPredicate, /*MI*/0, /*FnId*/GIMT_Encode2(GICXXPred_MI_Predicate_anonymous_17569),
        // (AMDGPUffbl_b32_impl:{ *:[i32] } i32:{ *:[i32] }:$src0)<<P:Predicate_anonymous_17569>>  =>  (S_FF1_I32_B32:{ *:[i32] } i32:{ *:[i32] }:$src0)
        GIR_MutateOpcode, /*InsnID*/0, /*RecycleInsnID*/0, /*Opcode*/GIMT_Encode2(AMDGPU::S_FF1_I32_B32),
        GIR_ConstrainSelectedInstOperands, /*InsnID*/0,
        // GIR_Coverage, 11,
        GIR_Done,
      // Label 7107: @521341
      GIM_Try, /*On fail goto*//*Label 7108*/ GIMT_Encode4(521376), // Rule ID 628 //
        GIM_CheckRegBankForClass, /*MI*/0, /*Op*/0, /*RC*/GIMT_Encode2(AMDGPU::VGPR_32RegClassID),
        GIM_CheckComplexPattern, /*MI*/0, /*Op*/1, /*Renderer*/GIMT_Encode2(0), GIMT_Encode2(GICP_gi_vop3mods0),
        // (AMDGPUffbl_b32_impl:{ *:[i32] } (VOP3Mods0:{ *:[i32] } i32:{ *:[i32] }:$src0))  =>  (V_FFBL_B32_e64:{ *:[i32] } i32:{ *:[i32] }:$src0)
        GIR_BuildMI, /*InsnID*/0, /*Opcode*/GIMT_Encode2(AMDGPU::V_FFBL_B32_e64),
        GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/0, // DstI[vdst]
        GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/0, // src0
        GIR_ConstrainSelectedInstOperands, /*InsnID*/0,
        GIR_EraseFromParent, /*InsnID*/0,
        // GIR_Coverage, 628,
        GIR_Done,
      // Label 7108: @521376
      GIM_Reject,
      // Label 7105: @521377
      GIM_Try, /*On fail goto*//*Label 7109*/ GIMT_Encode4(521399), // Rule ID 9 //
        GIM_CheckRegBankForClass, /*MI*/0, /*Op*/0, /*RC*/GIMT_Encode2(AMDGPU::SReg_32RegClassID),
        GIM_CheckCxxInsnPredicate, /*MI*/0, /*FnId*/GIMT_Encode2(GICXXPred_MI_Predicate_anonymous_17569),
        // (AMDGPUffbl_b32_impl:{ *:[i32] } i64:{ *:[i64] }:$src0)<<P:Predicate_anonymous_17569>>  =>  (S_FF1_I32_B64:{ *:[i32] } i64:{ *:[i64] }:$src0)
        GIR_MutateOpcode, /*InsnID*/0, /*RecycleInsnID*/0, /*Opcode*/GIMT_Encode2(AMDGPU::S_FF1_I32_B64),
        GIR_ConstrainSelectedInstOperands, /*InsnID*/0,
        // GIR_Coverage, 9,
        GIR_Done,
      // Label 7109: @521399
      GIM_Reject,
      // Label 7106: @521400
      GIM_Reject,
    // Label 7103: @521401
    GIM_Reject,
    // Label 145: @521402
    GIM_Try, /*On fail goto*//*Label 7110*/ GIMT_Encode4(521484), // Rule ID 774 //
      GIM_CheckFeatures, GIMT_Encode2(GIFBS_isGFX6GFX7),
      GIM_CheckType, /*MI*/0, /*Op*/0, /*Type*/GILLT_s32,
      GIM_CheckType, /*MI*/0, /*Op*/1, /*Type*/GILLT_s32,
      GIM_CheckType, /*MI*/0, /*Op*/2, /*Type*/GILLT_s32,
      GIM_CheckRegBankForClass, /*MI*/0, /*Op*/0, /*RC*/GIMT_Encode2(AMDGPU::VGPR_32RegClassID),
      GIM_CheckComplexPattern, /*MI*/0, /*Op*/1, /*Renderer*/GIMT_Encode2(0), GIMT_Encode2(GICP_gi_vop3mods0),
      GIM_CheckComplexPattern, /*MI*/0, /*Op*/2, /*Renderer*/GIMT_Encode2(1), GIMT_Encode2(GICP_gi_vop3mods),
      // (AMDGPUfmax_legacy:{ *:[f32] } (VOP3Mods0:{ *:[f32] } f32:{ *:[f32] }:$src0, i32:{ *:[i32] }:$src0_modifiers, i1:{ *:[i1] }:$clamp, i32:{ *:[i32] }:$omod), (VOP3Mods:{ *:[f32] } f32:{ *:[f32] }:$src1, i32:{ *:[i32] }:$src1_modifiers))  =>  (V_MAX_LEGACY_F32_e64:{ *:[f32] } i32:{ *:[i32] }:$src0_modifiers, f32:{ *:[f32] }:$src0, i32:{ *:[i32] }:$src1_modifiers, f32:{ *:[f32] }:$src1, i1:{ *:[i1] }:$clamp, i32:{ *:[i32] }:$omod)
      GIR_BuildMI, /*InsnID*/0, /*Opcode*/GIMT_Encode2(AMDGPU::V_MAX_LEGACY_F32_e64),
      GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/0, // DstI[vdst]
      GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/1, // src0_modifiers
      GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/0, // src0
      GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(1), /*SubOperand*/1, // src1_modifiers
      GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(1), /*SubOperand*/0, // src1
      GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/2, // clamp
      GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/3, // omod
      GIR_ConstrainSelectedInstOperands, /*InsnID*/0,
      GIR_EraseFromParent, /*InsnID*/0,
      // GIR_Coverage, 774,
      GIR_Done,
    // Label 7110: @521484
    GIM_Reject,
    // Label 146: @521485
    GIM_SwitchType, /*MI*/0, /*Op*/0, /*[*/GIMT_Encode2(8), GIMT_Encode2(10), /*)*//*default:*//*Label 7113*/ GIMT_Encode4(521700),
    /*GILLT_s16*//*Label 7111*/ GIMT_Encode4(521504),
    /*GILLT_s32*//*Label 7112*/ GIMT_Encode4(521603),
    // Label 7111: @521504
    GIM_Try, /*On fail goto*//*Label 7114*/ GIMT_Encode4(521602), // Rule ID 933 //
      GIM_CheckFeatures, GIMT_Encode2(GIFBS_isGFX9Plus),
      GIM_CheckType, /*MI*/0, /*Op*/1, /*Type*/GILLT_s16,
      GIM_CheckType, /*MI*/0, /*Op*/2, /*Type*/GILLT_s16,
      GIM_CheckType, /*MI*/0, /*Op*/3, /*Type*/GILLT_s16,
      GIM_CheckRegBankForClass, /*MI*/0, /*Op*/0, /*RC*/GIMT_Encode2(AMDGPU::VGPR_32RegClassID),
      GIM_CheckComplexPattern, /*MI*/0, /*Op*/1, /*Renderer*/GIMT_Encode2(0), GIMT_Encode2(GICP_gi_vop3opselmods),
      GIM_CheckComplexPattern, /*MI*/0, /*Op*/2, /*Renderer*/GIMT_Encode2(1), GIMT_Encode2(GICP_gi_vop3opselmods),
      GIM_CheckComplexPattern, /*MI*/0, /*Op*/3, /*Renderer*/GIMT_Encode2(2), GIMT_Encode2(GICP_gi_vop3opselmods),
      // (AMDGPUfmed3_impl:{ *:[f16] } (VOP3OpSelMods:{ *:[f16] } f16:{ *:[f16] }:$src0, i32:{ *:[i32] }:$src0_modifiers), (VOP3OpSelMods:{ *:[f16] } f16:{ *:[f16] }:$src1, i32:{ *:[i32] }:$src1_modifiers), (VOP3OpSelMods:{ *:[f16] } f16:{ *:[f16] }:$src2, i32:{ *:[i32] }:$src2_modifiers))  =>  (V_MED3_F16_e64:{ *:[f16] } i32:{ *:[i32] }:$src0_modifiers, f16:{ *:[f16] }:$src0, i32:{ *:[i32] }:$src1_modifiers, f16:{ *:[f16] }:$src1, i32:{ *:[i32] }:$src2_modifiers, f16:{ *:[f16] }:$src2)
      GIR_BuildMI, /*InsnID*/0, /*Opcode*/GIMT_Encode2(AMDGPU::V_MED3_F16_e64),
      GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/0, // DstI[vdst]
      GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/1, // src0_modifiers
      GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/0, // src0
      GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(1), /*SubOperand*/1, // src1_modifiers
      GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(1), /*SubOperand*/0, // src1
      GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(2), /*SubOperand*/1, // src2_modifiers
      GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(2), /*SubOperand*/0, // src2
      GIR_AddImm8, /*InsnID*/0, /*Imm*/0,
      GIR_AddImm8, /*InsnID*/0, /*Imm*/0,
      GIR_AddImm8, /*InsnID*/0, /*Imm*/0,
      GIR_ConstrainSelectedInstOperands, /*InsnID*/0,
      GIR_EraseFromParent, /*InsnID*/0,
      // GIR_Coverage, 933,
      GIR_Done,
    // Label 7114: @521602
    GIM_Reject,
    // Label 7112: @521603
    GIM_Try, /*On fail goto*//*Label 7115*/ GIMT_Encode4(521699), // Rule ID 894 //
      GIM_CheckType, /*MI*/0, /*Op*/1, /*Type*/GILLT_s32,
      GIM_CheckType, /*MI*/0, /*Op*/2, /*Type*/GILLT_s32,
      GIM_CheckType, /*MI*/0, /*Op*/3, /*Type*/GILLT_s32,
      GIM_CheckRegBankForClass, /*MI*/0, /*Op*/0, /*RC*/GIMT_Encode2(AMDGPU::VGPR_32RegClassID),
      GIM_CheckComplexPattern, /*MI*/0, /*Op*/1, /*Renderer*/GIMT_Encode2(0), GIMT_Encode2(GICP_gi_vop3mods0),
      GIM_CheckComplexPattern, /*MI*/0, /*Op*/2, /*Renderer*/GIMT_Encode2(1), GIMT_Encode2(GICP_gi_vop3mods),
      GIM_CheckComplexPattern, /*MI*/0, /*Op*/3, /*Renderer*/GIMT_Encode2(2), GIMT_Encode2(GICP_gi_vop3mods),
      // (AMDGPUfmed3_impl:{ *:[f32] } (VOP3Mods0:{ *:[f32] } f32:{ *:[f32] }:$src0, i32:{ *:[i32] }:$src0_modifiers, i1:{ *:[i1] }:$clamp, i32:{ *:[i32] }:$omod), (VOP3Mods:{ *:[f32] } f32:{ *:[f32] }:$src1, i32:{ *:[i32] }:$src1_modifiers), (VOP3Mods:{ *:[f32] } f32:{ *:[f32] }:$src2, i32:{ *:[i32] }:$src2_modifiers))  =>  (V_MED3_F32_e64:{ *:[f32] } i32:{ *:[i32] }:$src0_modifiers, f32:{ *:[f32] }:$src0, i32:{ *:[i32] }:$src1_modifiers, f32:{ *:[f32] }:$src1, i32:{ *:[i32] }:$src2_modifiers, f32:{ *:[f32] }:$src2, i1:{ *:[i1] }:$clamp, i32:{ *:[i32] }:$omod)
      GIR_BuildMI, /*InsnID*/0, /*Opcode*/GIMT_Encode2(AMDGPU::V_MED3_F32_e64),
      GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/0, // DstI[vdst]
      GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/1, // src0_modifiers
      GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/0, // src0
      GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(1), /*SubOperand*/1, // src1_modifiers
      GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(1), /*SubOperand*/0, // src1
      GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(2), /*SubOperand*/1, // src2_modifiers
      GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(2), /*SubOperand*/0, // src2
      GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/2, // clamp
      GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/3, // omod
      GIR_ConstrainSelectedInstOperands, /*InsnID*/0,
      GIR_EraseFromParent, /*InsnID*/0,
      // GIR_Coverage, 894,
      GIR_Done,
    // Label 7115: @521699
    GIM_Reject,
    // Label 7113: @521700
    GIM_Reject,
    // Label 147: @521701
    GIM_Try, /*On fail goto*//*Label 7116*/ GIMT_Encode4(521783), // Rule ID 773 //
      GIM_CheckFeatures, GIMT_Encode2(GIFBS_isGFX6GFX7),
      GIM_CheckType, /*MI*/0, /*Op*/0, /*Type*/GILLT_s32,
      GIM_CheckType, /*MI*/0, /*Op*/1, /*Type*/GILLT_s32,
      GIM_CheckType, /*MI*/0, /*Op*/2, /*Type*/GILLT_s32,
      GIM_CheckRegBankForClass, /*MI*/0, /*Op*/0, /*RC*/GIMT_Encode2(AMDGPU::VGPR_32RegClassID),
      GIM_CheckComplexPattern, /*MI*/0, /*Op*/1, /*Renderer*/GIMT_Encode2(0), GIMT_Encode2(GICP_gi_vop3mods0),
      GIM_CheckComplexPattern, /*MI*/0, /*Op*/2, /*Renderer*/GIMT_Encode2(1), GIMT_Encode2(GICP_gi_vop3mods),
      // (AMDGPUfmin_legacy:{ *:[f32] } (VOP3Mods0:{ *:[f32] } f32:{ *:[f32] }:$src0, i32:{ *:[i32] }:$src0_modifiers, i1:{ *:[i1] }:$clamp, i32:{ *:[i32] }:$omod), (VOP3Mods:{ *:[f32] } f32:{ *:[f32] }:$src1, i32:{ *:[i32] }:$src1_modifiers))  =>  (V_MIN_LEGACY_F32_e64:{ *:[f32] } i32:{ *:[i32] }:$src0_modifiers, f32:{ *:[f32] }:$src0, i32:{ *:[i32] }:$src1_modifiers, f32:{ *:[f32] }:$src1, i1:{ *:[i1] }:$clamp, i32:{ *:[i32] }:$omod)
      GIR_BuildMI, /*InsnID*/0, /*Opcode*/GIMT_Encode2(AMDGPU::V_MIN_LEGACY_F32_e64),
      GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/0, // DstI[vdst]
      GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/1, // src0_modifiers
      GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/0, // src0
      GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(1), /*SubOperand*/1, // src1_modifiers
      GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(1), /*SubOperand*/0, // src1
      GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/2, // clamp
      GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/3, // omod
      GIR_ConstrainSelectedInstOperands, /*InsnID*/0,
      GIR_EraseFromParent, /*InsnID*/0,
      // GIR_Coverage, 773,
      GIR_Done,
    // Label 7116: @521783
    GIM_Reject,
    // Label 148: @521784
    GIM_Try, /*On fail goto*//*Label 7117*/ GIMT_Encode4(521842), // Rule ID 611 //
      GIM_CheckType, /*MI*/0, /*Op*/0, /*Type*/GILLT_s32,
      GIM_CheckType, /*MI*/0, /*Op*/1, /*Type*/GILLT_s32,
      GIM_CheckRegBankForClass, /*MI*/0, /*Op*/0, /*RC*/GIMT_Encode2(AMDGPU::VGPR_32RegClassID),
      GIM_CheckComplexPattern, /*MI*/0, /*Op*/1, /*Renderer*/GIMT_Encode2(0), GIMT_Encode2(GICP_gi_vop3mods0),
      // (AMDGPUrcp_iflag:{ *:[f32] } (VOP3Mods0:{ *:[f32] } f32:{ *:[f32] }:$src0, i32:{ *:[i32] }:$src0_modifiers, i1:{ *:[i1] }:$clamp, i32:{ *:[i32] }:$omod))  =>  (V_RCP_IFLAG_F32_e64:{ *:[f32] } i32:{ *:[i32] }:$src0_modifiers, f32:{ *:[f32] }:$src0, i1:{ *:[i1] }:$clamp, i32:{ *:[i32] }:$omod)
      GIR_BuildMI, /*InsnID*/0, /*Opcode*/GIMT_Encode2(AMDGPU::V_RCP_IFLAG_F32_e64),
      GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/0, // DstI[vdst]
      GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/1, // src0_modifiers
      GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/0, // src0
      GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/2, // clamp
      GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/3, // omod
      GIR_ConstrainSelectedInstOperands, /*InsnID*/0,
      GIR_EraseFromParent, /*InsnID*/0,
      // GIR_Coverage, 611,
      GIR_Done,
    // Label 7117: @521842
    GIM_Reject,
    // Label 149: @521843
    GIM_SwitchType, /*MI*/0, /*Op*/0, /*[*/GIMT_Encode2(8), GIMT_Encode2(10), /*)*//*default:*//*Label 7120*/ GIMT_Encode4(522014),
    /*GILLT_s16*//*Label 7118*/ GIMT_Encode4(521862),
    /*GILLT_s32*//*Label 7119*/ GIMT_Encode4(521958),
    // Label 7118: @521862
    GIM_Try, /*On fail goto*//*Label 7121*/ GIMT_Encode4(521957), // Rule ID 934 //
      GIM_CheckFeatures, GIMT_Encode2(GIFBS_isGFX9Plus),
      GIM_CheckType, /*MI*/0, /*Op*/1, /*Type*/GILLT_s16,
      GIM_CheckType, /*MI*/0, /*Op*/2, /*Type*/GILLT_s16,
      GIM_CheckType, /*MI*/0, /*Op*/3, /*Type*/GILLT_s16,
      GIM_CheckRegBankForClass, /*MI*/0, /*Op*/0, /*RC*/GIMT_Encode2(AMDGPU::VGPR_32RegClassID),
      GIM_CheckComplexPattern, /*MI*/0, /*Op*/1, /*Renderer*/GIMT_Encode2(0), GIMT_Encode2(GICP_gi_vop3opselmods),
      GIM_CheckComplexPattern, /*MI*/0, /*Op*/2, /*Renderer*/GIMT_Encode2(1), GIMT_Encode2(GICP_gi_vop3opselmods),
      GIM_CheckComplexPattern, /*MI*/0, /*Op*/3, /*Renderer*/GIMT_Encode2(2), GIMT_Encode2(GICP_gi_vop3opselmods),
      // (AMDGPUsmed3:{ *:[i16] } (VOP3OpSelMods:{ *:[i16] } i16:{ *:[i16] }:$src0, i32:{ *:[i32] }:$src0_modifiers), (VOP3OpSelMods:{ *:[i16] } i16:{ *:[i16] }:$src1, i32:{ *:[i32] }:$src1_modifiers), (VOP3OpSelMods:{ *:[i16] } i16:{ *:[i16] }:$src2, i32:{ *:[i32] }:$src2_modifiers))  =>  (V_MED3_I16_e64:{ *:[i16] } i32:{ *:[i32] }:$src0_modifiers, i16:{ *:[i16] }:$src0, i32:{ *:[i32] }:$src1_modifiers, i16:{ *:[i16] }:$src1, i32:{ *:[i32] }:$src2_modifiers, i16:{ *:[i16] }:$src2)
      GIR_BuildMI, /*InsnID*/0, /*Opcode*/GIMT_Encode2(AMDGPU::V_MED3_I16_e64),
      GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/0, // DstI[vdst]
      GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/1, // src0_modifiers
      GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/0, // src0
      GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(1), /*SubOperand*/1, // src1_modifiers
      GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(1), /*SubOperand*/0, // src1
      GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(2), /*SubOperand*/1, // src2_modifiers
      GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(2), /*SubOperand*/0, // src2
      GIR_AddImm8, /*InsnID*/0, /*Imm*/0,
      GIR_AddImm8, /*InsnID*/0, /*Imm*/0,
      GIR_ConstrainSelectedInstOperands, /*InsnID*/0,
      GIR_EraseFromParent, /*InsnID*/0,
      // GIR_Coverage, 934,
      GIR_Done,
    // Label 7121: @521957
    GIM_Reject,
    // Label 7119: @521958
    GIM_Try, /*On fail goto*//*Label 7122*/ GIMT_Encode4(522013), // Rule ID 889 //
      GIM_CheckType, /*MI*/0, /*Op*/1, /*Type*/GILLT_s32,
      GIM_CheckType, /*MI*/0, /*Op*/2, /*Type*/GILLT_s32,
      GIM_CheckType, /*MI*/0, /*Op*/3, /*Type*/GILLT_s32,
      GIM_CheckRegBankForClass, /*MI*/0, /*Op*/0, /*RC*/GIMT_Encode2(AMDGPU::VGPR_32RegClassID),
      GIM_CheckComplexPattern, /*MI*/0, /*Op*/1, /*Renderer*/GIMT_Encode2(0), GIMT_Encode2(GICP_gi_vop3mods0),
      // (AMDGPUsmed3:{ *:[i32] } (VOP3Mods0:{ *:[i32] } i32:{ *:[i32] }:$src0), i32:{ *:[i32] }:$src1, i32:{ *:[i32] }:$src2)  =>  (V_MED3_I32_e64:{ *:[i32] } i32:{ *:[i32] }:$src0, i32:{ *:[i32] }:$src1, i32:{ *:[i32] }:$src2)
      GIR_BuildMI, /*InsnID*/0, /*Opcode*/GIMT_Encode2(AMDGPU::V_MED3_I32_e64),
      GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/0, // DstI[vdst]
      GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/0, // src0
      GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/2, // src1
      GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/3, // src2
      GIR_ConstrainSelectedInstOperands, /*InsnID*/0,
      GIR_EraseFromParent, /*InsnID*/0,
      // GIR_Coverage, 889,
      GIR_Done,
    // Label 7122: @522013
    GIM_Reject,
    // Label 7120: @522014
    GIM_Reject,
    // Label 150: @522015
    GIM_SwitchType, /*MI*/0, /*Op*/0, /*[*/GIMT_Encode2(9), GIMT_Encode2(31), /*)*//*default:*//*Label 7129*/ GIMT_Encode4(524846),
    /*GILLT_s32*//*Label 7123*/ GIMT_Encode4(522114), GIMT_Encode4(0), GIMT_Encode4(0),
    /*GILLT_v2s32*//*Label 7124*/ GIMT_Encode4(522585), GIMT_Encode4(0),
    /*GILLT_v3s32*//*Label 7125*/ GIMT_Encode4(523056), GIMT_Encode4(0), GIMT_Encode4(0),
    /*GILLT_v4s32*//*Label 7126*/ GIMT_Encode4(523433), GIMT_Encode4(0), GIMT_Encode4(0), GIMT_Encode4(0), GIMT_Encode4(0), GIMT_Encode4(0),
    /*GILLT_v8s32*//*Label 7127*/ GIMT_Encode4(523904), GIMT_Encode4(0), GIMT_Encode4(0), GIMT_Encode4(0), GIMT_Encode4(0), GIMT_Encode4(0), GIMT_Encode4(0),
    /*GILLT_v16s32*//*Label 7128*/ GIMT_Encode4(524375),
    // Label 7123: @522114
    GIM_Try, /*On fail goto*//*Label 7130*/ GIMT_Encode4(522584),
      GIM_CheckType, /*MI*/0, /*Op*/1, /*Type*/GILLT_v4s32,
      GIM_CheckType, /*MI*/0, /*Op*/2, /*Type*/GILLT_s32,
      GIM_CheckRegBankForClass, /*MI*/0, /*Op*/0, /*RC*/GIMT_Encode2(AMDGPU::SReg_32_XM0_XEXECRegClassID),
      GIM_CheckIsImm, /*MI*/0, /*Op*/3,
      GIM_Try, /*On fail goto*//*Label 7131*/ GIMT_Encode4(522187), // Rule ID 2415 //
        GIM_CheckFeatures, GIMT_Encode2(GIFBS_isGFX9Plus),
        GIM_CheckComplexPattern, /*MI*/0, /*Op*/2, /*Renderer*/GIMT_Encode2(0), GIMT_Encode2(GICP_gi_smrd_buffer_sgpr_imm),
        // (SIsbuffer_load:{ *:[i32] } v4i32:{ *:[v4i32] }:$sbase, (SMRDBufferSgprImm:{ *:[i32] } i32:{ *:[i32] }:$soffset, i32:{ *:[i32] }:$offset), (timm:{ *:[i32] }):$cachepolicy)  =>  (S_BUFFER_LOAD_DWORD_SGPR_IMM:{ *:[i32] } SReg_128:{ *:[v4i32] }:$sbase, SReg_32:{ *:[i32] }:$soffset, i32imm:{ *:[i32] }:$offset, (extract_cpol:{ *:[i32] } ?:{ *:[i32] }:$cachepolicy))
        GIR_BuildMI, /*InsnID*/0, /*Opcode*/GIMT_Encode2(AMDGPU::S_BUFFER_LOAD_DWORD_SGPR_IMM),
        GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/0, // DstI[sdst]
        GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/1, // sbase
        GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/0, // soffset
        GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/1, // offset
        GIR_CustomOperandRenderer, /*InsnID*/0, /*OldInsnID*/0, /*OpIdx*/3, /*OperandRenderer*/GIMT_Encode2(GICR_renderExtractCPol), // cachepolicy
        GIR_MergeMemOperands, /*InsnID*/0, /*NumInsns*/1, /*MergeInsnID's*/0,
        GIR_ConstrainSelectedInstOperands, /*InsnID*/0,
        GIR_EraseFromParent, /*InsnID*/0,
        // GIR_Coverage, 2415,
        GIR_Done,
      // Label 7131: @522187
      GIM_Try, /*On fail goto*//*Label 7132*/ GIMT_Encode4(522239), // Rule ID 2712 //
        GIM_CheckFeatures, GIMT_Encode2(GIFBS_isGFX9Plus),
        GIM_CheckComplexPattern, /*MI*/0, /*Op*/2, /*Renderer*/GIMT_Encode2(0), GIMT_Encode2(GICP_gi_smrd_buffer_sgpr_imm),
        // (SIsbuffer_load:{ *:[f32] } v4i32:{ *:[v4i32] }:$sbase, (SMRDBufferSgprImm:{ *:[i32] } i32:{ *:[i32] }:$soffset, i32:{ *:[i32] }:$offset), (timm:{ *:[i32] }):$cachepolicy)  =>  (S_BUFFER_LOAD_DWORD_SGPR_IMM:{ *:[f32] } SReg_128:{ *:[v4i32] }:$sbase, SReg_32:{ *:[i32] }:$soffset, i32imm:{ *:[i32] }:$offset, (extract_cpol:{ *:[i32] } ?:{ *:[i32] }:$cachepolicy))
        GIR_BuildMI, /*InsnID*/0, /*Opcode*/GIMT_Encode2(AMDGPU::S_BUFFER_LOAD_DWORD_SGPR_IMM),
        GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/0, // DstI[sdst]
        GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/1, // sbase
        GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/0, // soffset
        GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/1, // offset
        GIR_CustomOperandRenderer, /*InsnID*/0, /*OldInsnID*/0, /*OpIdx*/3, /*OperandRenderer*/GIMT_Encode2(GICR_renderExtractCPol), // cachepolicy
        GIR_MergeMemOperands, /*InsnID*/0, /*NumInsns*/1, /*MergeInsnID's*/0,
        GIR_ConstrainSelectedInstOperands, /*InsnID*/0,
        GIR_EraseFromParent, /*InsnID*/0,
        // GIR_Coverage, 2712,
        GIR_Done,
      // Label 7132: @522239
      GIM_Try, /*On fail goto*//*Label 7133*/ GIMT_Encode4(522283), // Rule ID 2411 //
        GIM_CheckComplexPattern, /*MI*/0, /*Op*/2, /*Renderer*/GIMT_Encode2(0), GIMT_Encode2(GICP_gi_smrd_buffer_imm),
        // (SIsbuffer_load:{ *:[i32] } v4i32:{ *:[v4i32] }:$sbase, (SMRDBufferImm:{ *:[i32] } i32:{ *:[i32] }:$offset), (timm:{ *:[i32] }):$cachepolicy)  =>  (S_BUFFER_LOAD_DWORD_IMM:{ *:[i32] } SReg_128:{ *:[v4i32] }:$sbase, i32imm:{ *:[i32] }:$offset, (extract_cpol:{ *:[i32] } ?:{ *:[i32] }:$cachepolicy))
        GIR_BuildMI, /*InsnID*/0, /*Opcode*/GIMT_Encode2(AMDGPU::S_BUFFER_LOAD_DWORD_IMM),
        GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/0, // DstI[sdst]
        GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/1, // sbase
        GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/0, // offset
        GIR_CustomOperandRenderer, /*InsnID*/0, /*OldInsnID*/0, /*OpIdx*/3, /*OperandRenderer*/GIMT_Encode2(GICR_renderExtractCPol), // cachepolicy
        GIR_MergeMemOperands, /*InsnID*/0, /*NumInsns*/1, /*MergeInsnID's*/0,
        GIR_ConstrainSelectedInstOperands, /*InsnID*/0,
        GIR_EraseFromParent, /*InsnID*/0,
        // GIR_Coverage, 2411,
        GIR_Done,
      // Label 7133: @522283
      GIM_Try, /*On fail goto*//*Label 7134*/ GIMT_Encode4(522327), // Rule ID 2708 //
        GIM_CheckComplexPattern, /*MI*/0, /*Op*/2, /*Renderer*/GIMT_Encode2(0), GIMT_Encode2(GICP_gi_smrd_buffer_imm),
        // (SIsbuffer_load:{ *:[f32] } v4i32:{ *:[v4i32] }:$sbase, (SMRDBufferImm:{ *:[i32] } i32:{ *:[i32] }:$offset), (timm:{ *:[i32] }):$cachepolicy)  =>  (S_BUFFER_LOAD_DWORD_IMM:{ *:[f32] } SReg_128:{ *:[v4i32] }:$sbase, i32imm:{ *:[i32] }:$offset, (extract_cpol:{ *:[i32] } ?:{ *:[i32] }:$cachepolicy))
        GIR_BuildMI, /*InsnID*/0, /*Opcode*/GIMT_Encode2(AMDGPU::S_BUFFER_LOAD_DWORD_IMM),
        GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/0, // DstI[sdst]
        GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/1, // sbase
        GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/0, // offset
        GIR_CustomOperandRenderer, /*InsnID*/0, /*OldInsnID*/0, /*OpIdx*/3, /*OperandRenderer*/GIMT_Encode2(GICR_renderExtractCPol), // cachepolicy
        GIR_MergeMemOperands, /*InsnID*/0, /*NumInsns*/1, /*MergeInsnID's*/0,
        GIR_ConstrainSelectedInstOperands, /*InsnID*/0,
        GIR_EraseFromParent, /*InsnID*/0,
        // GIR_Coverage, 2708,
        GIR_Done,
      // Label 7134: @522327
      GIM_Try, /*On fail goto*//*Label 7135*/ GIMT_Encode4(522374), // Rule ID 2412 //
        GIM_CheckFeatures, GIMT_Encode2(GIFBS_isGFX7Only),
        GIM_CheckComplexPattern, /*MI*/0, /*Op*/2, /*Renderer*/GIMT_Encode2(0), GIMT_Encode2(GICP_gi_smrd_buffer_imm32),
        // (SIsbuffer_load:{ *:[i32] } v4i32:{ *:[v4i32] }:$sbase, (SMRDBufferImm32:{ *:[i32] } i32:{ *:[i32] }:$offset), (timm:{ *:[i32] }):$cachepolicy)  =>  (S_BUFFER_LOAD_DWORD_IMM_ci:{ *:[i32] } SReg_128:{ *:[v4i32] }:$sbase, smrd_literal_offset:{ *:[i32] }:$offset, (extract_cpol:{ *:[i32] } ?:{ *:[i32] }:$cachepolicy))
        GIR_BuildMI, /*InsnID*/0, /*Opcode*/GIMT_Encode2(AMDGPU::S_BUFFER_LOAD_DWORD_IMM_ci),
        GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/0, // DstI[sdst]
        GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/1, // sbase
        GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/0, // offset
        GIR_CustomOperandRenderer, /*InsnID*/0, /*OldInsnID*/0, /*OpIdx*/3, /*OperandRenderer*/GIMT_Encode2(GICR_renderExtractCPol), // cachepolicy
        GIR_MergeMemOperands, /*InsnID*/0, /*NumInsns*/1, /*MergeInsnID's*/0,
        GIR_ConstrainSelectedInstOperands, /*InsnID*/0,
        GIR_EraseFromParent, /*InsnID*/0,
        // GIR_Coverage, 2412,
        GIR_Done,
      // Label 7135: @522374
      GIM_Try, /*On fail goto*//*Label 7136*/ GIMT_Encode4(522421), // Rule ID 2709 //
        GIM_CheckFeatures, GIMT_Encode2(GIFBS_isGFX7Only),
        GIM_CheckComplexPattern, /*MI*/0, /*Op*/2, /*Renderer*/GIMT_Encode2(0), GIMT_Encode2(GICP_gi_smrd_buffer_imm32),
        // (SIsbuffer_load:{ *:[f32] } v4i32:{ *:[v4i32] }:$sbase, (SMRDBufferImm32:{ *:[i32] } i32:{ *:[i32] }:$offset), (timm:{ *:[i32] }):$cachepolicy)  =>  (S_BUFFER_LOAD_DWORD_IMM_ci:{ *:[f32] } SReg_128:{ *:[v4i32] }:$sbase, smrd_literal_offset:{ *:[i32] }:$offset, (extract_cpol:{ *:[i32] } ?:{ *:[i32] }:$cachepolicy))
        GIR_BuildMI, /*InsnID*/0, /*Opcode*/GIMT_Encode2(AMDGPU::S_BUFFER_LOAD_DWORD_IMM_ci),
        GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/0, // DstI[sdst]
        GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/1, // sbase
        GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/0, // offset
        GIR_CustomOperandRenderer, /*InsnID*/0, /*OldInsnID*/0, /*OpIdx*/3, /*OperandRenderer*/GIMT_Encode2(GICR_renderExtractCPol), // cachepolicy
        GIR_MergeMemOperands, /*InsnID*/0, /*NumInsns*/1, /*MergeInsnID's*/0,
        GIR_ConstrainSelectedInstOperands, /*InsnID*/0,
        GIR_EraseFromParent, /*InsnID*/0,
        // GIR_Coverage, 2709,
        GIR_Done,
      // Label 7136: @522421
      GIM_Try, /*On fail goto*//*Label 7137*/ GIMT_Encode4(522460), // Rule ID 2413 //
        GIM_CheckFeatures, GIMT_Encode2(GIFBS_isNotGFX9Plus),
        // (SIsbuffer_load:{ *:[i32] } v4i32:{ *:[v4i32] }:$sbase, i32:{ *:[i32] }:$soffset, (timm:{ *:[i32] }):$cachepolicy)  =>  (S_BUFFER_LOAD_DWORD_SGPR:{ *:[i32] } SReg_128:{ *:[v4i32] }:$sbase, SReg_32:{ *:[i32] }:$soffset, (extract_cpol:{ *:[i32] } ?:{ *:[i32] }:$cachepolicy))
        GIR_BuildMI, /*InsnID*/0, /*Opcode*/GIMT_Encode2(AMDGPU::S_BUFFER_LOAD_DWORD_SGPR),
        GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/0, // DstI[sdst]
        GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/1, // sbase
        GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/2, // soffset
        GIR_CustomOperandRenderer, /*InsnID*/0, /*OldInsnID*/0, /*OpIdx*/3, /*OperandRenderer*/GIMT_Encode2(GICR_renderExtractCPol), // cachepolicy
        GIR_MergeMemOperands, /*InsnID*/0, /*NumInsns*/1, /*MergeInsnID's*/0,
        GIR_ConstrainSelectedInstOperands, /*InsnID*/0,
        GIR_EraseFromParent, /*InsnID*/0,
        // GIR_Coverage, 2413,
        GIR_Done,
      // Label 7137: @522460
      GIM_Try, /*On fail goto*//*Label 7138*/ GIMT_Encode4(522502), // Rule ID 2414 //
        GIM_CheckFeatures, GIMT_Encode2(GIFBS_isGFX9Plus),
        // (SIsbuffer_load:{ *:[i32] } v4i32:{ *:[v4i32] }:$sbase, i32:{ *:[i32] }:$soffset, (timm:{ *:[i32] }):$cachepolicy)  =>  (S_BUFFER_LOAD_DWORD_SGPR_IMM:{ *:[i32] } SReg_128:{ *:[v4i32] }:$sbase, SReg_32:{ *:[i32] }:$soffset, 0:{ *:[i32] }, (extract_cpol:{ *:[i32] } ?:{ *:[i32] }:$cachepolicy))
        GIR_BuildMI, /*InsnID*/0, /*Opcode*/GIMT_Encode2(AMDGPU::S_BUFFER_LOAD_DWORD_SGPR_IMM),
        GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/0, // DstI[sdst]
        GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/1, // sbase
        GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/2, // soffset
        GIR_AddImm8, /*InsnID*/0, /*Imm*/0,
        GIR_CustomOperandRenderer, /*InsnID*/0, /*OldInsnID*/0, /*OpIdx*/3, /*OperandRenderer*/GIMT_Encode2(GICR_renderExtractCPol), // cachepolicy
        GIR_MergeMemOperands, /*InsnID*/0, /*NumInsns*/1, /*MergeInsnID's*/0,
        GIR_ConstrainSelectedInstOperands, /*InsnID*/0,
        GIR_EraseFromParent, /*InsnID*/0,
        // GIR_Coverage, 2414,
        GIR_Done,
      // Label 7138: @522502
      GIM_Try, /*On fail goto*//*Label 7139*/ GIMT_Encode4(522541), // Rule ID 2710 //
        GIM_CheckFeatures, GIMT_Encode2(GIFBS_isNotGFX9Plus),
        // (SIsbuffer_load:{ *:[f32] } v4i32:{ *:[v4i32] }:$sbase, i32:{ *:[i32] }:$soffset, (timm:{ *:[i32] }):$cachepolicy)  =>  (S_BUFFER_LOAD_DWORD_SGPR:{ *:[f32] } SReg_128:{ *:[v4i32] }:$sbase, SReg_32:{ *:[i32] }:$soffset, (extract_cpol:{ *:[i32] } ?:{ *:[i32] }:$cachepolicy))
        GIR_BuildMI, /*InsnID*/0, /*Opcode*/GIMT_Encode2(AMDGPU::S_BUFFER_LOAD_DWORD_SGPR),
        GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/0, // DstI[sdst]
        GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/1, // sbase
        GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/2, // soffset
        GIR_CustomOperandRenderer, /*InsnID*/0, /*OldInsnID*/0, /*OpIdx*/3, /*OperandRenderer*/GIMT_Encode2(GICR_renderExtractCPol), // cachepolicy
        GIR_MergeMemOperands, /*InsnID*/0, /*NumInsns*/1, /*MergeInsnID's*/0,
        GIR_ConstrainSelectedInstOperands, /*InsnID*/0,
        GIR_EraseFromParent, /*InsnID*/0,
        // GIR_Coverage, 2710,
        GIR_Done,
      // Label 7139: @522541
      GIM_Try, /*On fail goto*//*Label 7140*/ GIMT_Encode4(522583), // Rule ID 2711 //
        GIM_CheckFeatures, GIMT_Encode2(GIFBS_isGFX9Plus),
        // (SIsbuffer_load:{ *:[f32] } v4i32:{ *:[v4i32] }:$sbase, i32:{ *:[i32] }:$soffset, (timm:{ *:[i32] }):$cachepolicy)  =>  (S_BUFFER_LOAD_DWORD_SGPR_IMM:{ *:[f32] } SReg_128:{ *:[v4i32] }:$sbase, SReg_32:{ *:[i32] }:$soffset, 0:{ *:[i32] }, (extract_cpol:{ *:[i32] } ?:{ *:[i32] }:$cachepolicy))
        GIR_BuildMI, /*InsnID*/0, /*Opcode*/GIMT_Encode2(AMDGPU::S_BUFFER_LOAD_DWORD_SGPR_IMM),
        GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/0, // DstI[sdst]
        GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/1, // sbase
        GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/2, // soffset
        GIR_AddImm8, /*InsnID*/0, /*Imm*/0,
        GIR_CustomOperandRenderer, /*InsnID*/0, /*OldInsnID*/0, /*OpIdx*/3, /*OperandRenderer*/GIMT_Encode2(GICR_renderExtractCPol), // cachepolicy
        GIR_MergeMemOperands, /*InsnID*/0, /*NumInsns*/1, /*MergeInsnID's*/0,
        GIR_ConstrainSelectedInstOperands, /*InsnID*/0,
        GIR_EraseFromParent, /*InsnID*/0,
        // GIR_Coverage, 2711,
        GIR_Done,
      // Label 7140: @522583
      GIM_Reject,
    // Label 7130: @522584
    GIM_Reject,
    // Label 7124: @522585
    GIM_Try, /*On fail goto*//*Label 7141*/ GIMT_Encode4(523055),
      GIM_CheckType, /*MI*/0, /*Op*/1, /*Type*/GILLT_v4s32,
      GIM_CheckType, /*MI*/0, /*Op*/2, /*Type*/GILLT_s32,
      GIM_CheckRegBankForClass, /*MI*/0, /*Op*/0, /*RC*/GIMT_Encode2(AMDGPU::SReg_64_XEXECRegClassID),
      GIM_CheckIsImm, /*MI*/0, /*Op*/3,
      GIM_Try, /*On fail goto*//*Label 7142*/ GIMT_Encode4(522658), // Rule ID 2688 //
        GIM_CheckFeatures, GIMT_Encode2(GIFBS_isGFX9Plus),
        GIM_CheckComplexPattern, /*MI*/0, /*Op*/2, /*Renderer*/GIMT_Encode2(0), GIMT_Encode2(GICP_gi_smrd_buffer_sgpr_imm),
        // (SIsbuffer_load:{ *:[v2i32] } v4i32:{ *:[v4i32] }:$sbase, (SMRDBufferSgprImm:{ *:[i32] } i32:{ *:[i32] }:$soffset, i32:{ *:[i32] }:$offset), (timm:{ *:[i32] }):$cachepolicy)  =>  (S_BUFFER_LOAD_DWORDX2_SGPR_IMM:{ *:[v2i32] } SReg_128:{ *:[v4i32] }:$sbase, SReg_32:{ *:[i32] }:$soffset, i32imm:{ *:[i32] }:$offset, (extract_cpol:{ *:[i32] } ?:{ *:[i32] }:$cachepolicy))
        GIR_BuildMI, /*InsnID*/0, /*Opcode*/GIMT_Encode2(AMDGPU::S_BUFFER_LOAD_DWORDX2_SGPR_IMM),
        GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/0, // DstI[sdst]
        GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/1, // sbase
        GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/0, // soffset
        GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/1, // offset
        GIR_CustomOperandRenderer, /*InsnID*/0, /*OldInsnID*/0, /*OpIdx*/3, /*OperandRenderer*/GIMT_Encode2(GICR_renderExtractCPol), // cachepolicy
        GIR_MergeMemOperands, /*InsnID*/0, /*NumInsns*/1, /*MergeInsnID's*/0,
        GIR_ConstrainSelectedInstOperands, /*InsnID*/0,
        GIR_EraseFromParent, /*InsnID*/0,
        // GIR_Coverage, 2688,
        GIR_Done,
      // Label 7142: @522658
      GIM_Try, /*On fail goto*//*Label 7143*/ GIMT_Encode4(522710), // Rule ID 2717 //
        GIM_CheckFeatures, GIMT_Encode2(GIFBS_isGFX9Plus),
        GIM_CheckComplexPattern, /*MI*/0, /*Op*/2, /*Renderer*/GIMT_Encode2(0), GIMT_Encode2(GICP_gi_smrd_buffer_sgpr_imm),
        // (SIsbuffer_load:{ *:[v2f32] } v4i32:{ *:[v4i32] }:$sbase, (SMRDBufferSgprImm:{ *:[i32] } i32:{ *:[i32] }:$soffset, i32:{ *:[i32] }:$offset), (timm:{ *:[i32] }):$cachepolicy)  =>  (S_BUFFER_LOAD_DWORDX2_SGPR_IMM:{ *:[v2f32] } SReg_128:{ *:[v4i32] }:$sbase, SReg_32:{ *:[i32] }:$soffset, i32imm:{ *:[i32] }:$offset, (extract_cpol:{ *:[i32] } ?:{ *:[i32] }:$cachepolicy))
        GIR_BuildMI, /*InsnID*/0, /*Opcode*/GIMT_Encode2(AMDGPU::S_BUFFER_LOAD_DWORDX2_SGPR_IMM),
        GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/0, // DstI[sdst]
        GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/1, // sbase
        GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/0, // soffset
        GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/1, // offset
        GIR_CustomOperandRenderer, /*InsnID*/0, /*OldInsnID*/0, /*OpIdx*/3, /*OperandRenderer*/GIMT_Encode2(GICR_renderExtractCPol), // cachepolicy
        GIR_MergeMemOperands, /*InsnID*/0, /*NumInsns*/1, /*MergeInsnID's*/0,
        GIR_ConstrainSelectedInstOperands, /*InsnID*/0,
        GIR_EraseFromParent, /*InsnID*/0,
        // GIR_Coverage, 2717,
        GIR_Done,
      // Label 7143: @522710
      GIM_Try, /*On fail goto*//*Label 7144*/ GIMT_Encode4(522754), // Rule ID 2684 //
        GIM_CheckComplexPattern, /*MI*/0, /*Op*/2, /*Renderer*/GIMT_Encode2(0), GIMT_Encode2(GICP_gi_smrd_buffer_imm),
        // (SIsbuffer_load:{ *:[v2i32] } v4i32:{ *:[v4i32] }:$sbase, (SMRDBufferImm:{ *:[i32] } i32:{ *:[i32] }:$offset), (timm:{ *:[i32] }):$cachepolicy)  =>  (S_BUFFER_LOAD_DWORDX2_IMM:{ *:[v2i32] } SReg_128:{ *:[v4i32] }:$sbase, i32imm:{ *:[i32] }:$offset, (extract_cpol:{ *:[i32] } ?:{ *:[i32] }:$cachepolicy))
        GIR_BuildMI, /*InsnID*/0, /*Opcode*/GIMT_Encode2(AMDGPU::S_BUFFER_LOAD_DWORDX2_IMM),
        GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/0, // DstI[sdst]
        GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/1, // sbase
        GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/0, // offset
        GIR_CustomOperandRenderer, /*InsnID*/0, /*OldInsnID*/0, /*OpIdx*/3, /*OperandRenderer*/GIMT_Encode2(GICR_renderExtractCPol), // cachepolicy
        GIR_MergeMemOperands, /*InsnID*/0, /*NumInsns*/1, /*MergeInsnID's*/0,
        GIR_ConstrainSelectedInstOperands, /*InsnID*/0,
        GIR_EraseFromParent, /*InsnID*/0,
        // GIR_Coverage, 2684,
        GIR_Done,
      // Label 7144: @522754
      GIM_Try, /*On fail goto*//*Label 7145*/ GIMT_Encode4(522798), // Rule ID 2713 //
        GIM_CheckComplexPattern, /*MI*/0, /*Op*/2, /*Renderer*/GIMT_Encode2(0), GIMT_Encode2(GICP_gi_smrd_buffer_imm),
        // (SIsbuffer_load:{ *:[v2f32] } v4i32:{ *:[v4i32] }:$sbase, (SMRDBufferImm:{ *:[i32] } i32:{ *:[i32] }:$offset), (timm:{ *:[i32] }):$cachepolicy)  =>  (S_BUFFER_LOAD_DWORDX2_IMM:{ *:[v2f32] } SReg_128:{ *:[v4i32] }:$sbase, i32imm:{ *:[i32] }:$offset, (extract_cpol:{ *:[i32] } ?:{ *:[i32] }:$cachepolicy))
        GIR_BuildMI, /*InsnID*/0, /*Opcode*/GIMT_Encode2(AMDGPU::S_BUFFER_LOAD_DWORDX2_IMM),
        GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/0, // DstI[sdst]
        GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/1, // sbase
        GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/0, // offset
        GIR_CustomOperandRenderer, /*InsnID*/0, /*OldInsnID*/0, /*OpIdx*/3, /*OperandRenderer*/GIMT_Encode2(GICR_renderExtractCPol), // cachepolicy
        GIR_MergeMemOperands, /*InsnID*/0, /*NumInsns*/1, /*MergeInsnID's*/0,
        GIR_ConstrainSelectedInstOperands, /*InsnID*/0,
        GIR_EraseFromParent, /*InsnID*/0,
        // GIR_Coverage, 2713,
        GIR_Done,
      // Label 7145: @522798
      GIM_Try, /*On fail goto*//*Label 7146*/ GIMT_Encode4(522845), // Rule ID 2685 //
        GIM_CheckFeatures, GIMT_Encode2(GIFBS_isGFX7Only),
        GIM_CheckComplexPattern, /*MI*/0, /*Op*/2, /*Renderer*/GIMT_Encode2(0), GIMT_Encode2(GICP_gi_smrd_buffer_imm32),
        // (SIsbuffer_load:{ *:[v2i32] } v4i32:{ *:[v4i32] }:$sbase, (SMRDBufferImm32:{ *:[i32] } i32:{ *:[i32] }:$offset), (timm:{ *:[i32] }):$cachepolicy)  =>  (S_BUFFER_LOAD_DWORDX2_IMM_ci:{ *:[v2i32] } SReg_128:{ *:[v4i32] }:$sbase, smrd_literal_offset:{ *:[i32] }:$offset, (extract_cpol:{ *:[i32] } ?:{ *:[i32] }:$cachepolicy))
        GIR_BuildMI, /*InsnID*/0, /*Opcode*/GIMT_Encode2(AMDGPU::S_BUFFER_LOAD_DWORDX2_IMM_ci),
        GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/0, // DstI[sdst]
        GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/1, // sbase
        GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/0, // offset
        GIR_CustomOperandRenderer, /*InsnID*/0, /*OldInsnID*/0, /*OpIdx*/3, /*OperandRenderer*/GIMT_Encode2(GICR_renderExtractCPol), // cachepolicy
        GIR_MergeMemOperands, /*InsnID*/0, /*NumInsns*/1, /*MergeInsnID's*/0,
        GIR_ConstrainSelectedInstOperands, /*InsnID*/0,
        GIR_EraseFromParent, /*InsnID*/0,
        // GIR_Coverage, 2685,
        GIR_Done,
      // Label 7146: @522845
      GIM_Try, /*On fail goto*//*Label 7147*/ GIMT_Encode4(522892), // Rule ID 2714 //
        GIM_CheckFeatures, GIMT_Encode2(GIFBS_isGFX7Only),
        GIM_CheckComplexPattern, /*MI*/0, /*Op*/2, /*Renderer*/GIMT_Encode2(0), GIMT_Encode2(GICP_gi_smrd_buffer_imm32),
        // (SIsbuffer_load:{ *:[v2f32] } v4i32:{ *:[v4i32] }:$sbase, (SMRDBufferImm32:{ *:[i32] } i32:{ *:[i32] }:$offset), (timm:{ *:[i32] }):$cachepolicy)  =>  (S_BUFFER_LOAD_DWORDX2_IMM_ci:{ *:[v2f32] } SReg_128:{ *:[v4i32] }:$sbase, smrd_literal_offset:{ *:[i32] }:$offset, (extract_cpol:{ *:[i32] } ?:{ *:[i32] }:$cachepolicy))
        GIR_BuildMI, /*InsnID*/0, /*Opcode*/GIMT_Encode2(AMDGPU::S_BUFFER_LOAD_DWORDX2_IMM_ci),
        GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/0, // DstI[sdst]
        GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/1, // sbase
        GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/0, // offset
        GIR_CustomOperandRenderer, /*InsnID*/0, /*OldInsnID*/0, /*OpIdx*/3, /*OperandRenderer*/GIMT_Encode2(GICR_renderExtractCPol), // cachepolicy
        GIR_MergeMemOperands, /*InsnID*/0, /*NumInsns*/1, /*MergeInsnID's*/0,
        GIR_ConstrainSelectedInstOperands, /*InsnID*/0,
        GIR_EraseFromParent, /*InsnID*/0,
        // GIR_Coverage, 2714,
        GIR_Done,
      // Label 7147: @522892
      GIM_Try, /*On fail goto*//*Label 7148*/ GIMT_Encode4(522931), // Rule ID 2686 //
        GIM_CheckFeatures, GIMT_Encode2(GIFBS_isNotGFX9Plus),
        // (SIsbuffer_load:{ *:[v2i32] } v4i32:{ *:[v4i32] }:$sbase, i32:{ *:[i32] }:$soffset, (timm:{ *:[i32] }):$cachepolicy)  =>  (S_BUFFER_LOAD_DWORDX2_SGPR:{ *:[v2i32] } SReg_128:{ *:[v4i32] }:$sbase, SReg_32:{ *:[i32] }:$soffset, (extract_cpol:{ *:[i32] } ?:{ *:[i32] }:$cachepolicy))
        GIR_BuildMI, /*InsnID*/0, /*Opcode*/GIMT_Encode2(AMDGPU::S_BUFFER_LOAD_DWORDX2_SGPR),
        GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/0, // DstI[sdst]
        GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/1, // sbase
        GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/2, // soffset
        GIR_CustomOperandRenderer, /*InsnID*/0, /*OldInsnID*/0, /*OpIdx*/3, /*OperandRenderer*/GIMT_Encode2(GICR_renderExtractCPol), // cachepolicy
        GIR_MergeMemOperands, /*InsnID*/0, /*NumInsns*/1, /*MergeInsnID's*/0,
        GIR_ConstrainSelectedInstOperands, /*InsnID*/0,
        GIR_EraseFromParent, /*InsnID*/0,
        // GIR_Coverage, 2686,
        GIR_Done,
      // Label 7148: @522931
      GIM_Try, /*On fail goto*//*Label 7149*/ GIMT_Encode4(522973), // Rule ID 2687 //
        GIM_CheckFeatures, GIMT_Encode2(GIFBS_isGFX9Plus),
        // (SIsbuffer_load:{ *:[v2i32] } v4i32:{ *:[v4i32] }:$sbase, i32:{ *:[i32] }:$soffset, (timm:{ *:[i32] }):$cachepolicy)  =>  (S_BUFFER_LOAD_DWORDX2_SGPR_IMM:{ *:[v2i32] } SReg_128:{ *:[v4i32] }:$sbase, SReg_32:{ *:[i32] }:$soffset, 0:{ *:[i32] }, (extract_cpol:{ *:[i32] } ?:{ *:[i32] }:$cachepolicy))
        GIR_BuildMI, /*InsnID*/0, /*Opcode*/GIMT_Encode2(AMDGPU::S_BUFFER_LOAD_DWORDX2_SGPR_IMM),
        GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/0, // DstI[sdst]
        GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/1, // sbase
        GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/2, // soffset
        GIR_AddImm8, /*InsnID*/0, /*Imm*/0,
        GIR_CustomOperandRenderer, /*InsnID*/0, /*OldInsnID*/0, /*OpIdx*/3, /*OperandRenderer*/GIMT_Encode2(GICR_renderExtractCPol), // cachepolicy
        GIR_MergeMemOperands, /*InsnID*/0, /*NumInsns*/1, /*MergeInsnID's*/0,
        GIR_ConstrainSelectedInstOperands, /*InsnID*/0,
        GIR_EraseFromParent, /*InsnID*/0,
        // GIR_Coverage, 2687,
        GIR_Done,
      // Label 7149: @522973
      GIM_Try, /*On fail goto*//*Label 7150*/ GIMT_Encode4(523012), // Rule ID 2715 //
        GIM_CheckFeatures, GIMT_Encode2(GIFBS_isNotGFX9Plus),
        // (SIsbuffer_load:{ *:[v2f32] } v4i32:{ *:[v4i32] }:$sbase, i32:{ *:[i32] }:$soffset, (timm:{ *:[i32] }):$cachepolicy)  =>  (S_BUFFER_LOAD_DWORDX2_SGPR:{ *:[v2f32] } SReg_128:{ *:[v4i32] }:$sbase, SReg_32:{ *:[i32] }:$soffset, (extract_cpol:{ *:[i32] } ?:{ *:[i32] }:$cachepolicy))
        GIR_BuildMI, /*InsnID*/0, /*Opcode*/GIMT_Encode2(AMDGPU::S_BUFFER_LOAD_DWORDX2_SGPR),
        GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/0, // DstI[sdst]
        GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/1, // sbase
        GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/2, // soffset
        GIR_CustomOperandRenderer, /*InsnID*/0, /*OldInsnID*/0, /*OpIdx*/3, /*OperandRenderer*/GIMT_Encode2(GICR_renderExtractCPol), // cachepolicy
        GIR_MergeMemOperands, /*InsnID*/0, /*NumInsns*/1, /*MergeInsnID's*/0,
        GIR_ConstrainSelectedInstOperands, /*InsnID*/0,
        GIR_EraseFromParent, /*InsnID*/0,
        // GIR_Coverage, 2715,
        GIR_Done,
      // Label 7150: @523012
      GIM_Try, /*On fail goto*//*Label 7151*/ GIMT_Encode4(523054), // Rule ID 2716 //
        GIM_CheckFeatures, GIMT_Encode2(GIFBS_isGFX9Plus),
        // (SIsbuffer_load:{ *:[v2f32] } v4i32:{ *:[v4i32] }:$sbase, i32:{ *:[i32] }:$soffset, (timm:{ *:[i32] }):$cachepolicy)  =>  (S_BUFFER_LOAD_DWORDX2_SGPR_IMM:{ *:[v2f32] } SReg_128:{ *:[v4i32] }:$sbase, SReg_32:{ *:[i32] }:$soffset, 0:{ *:[i32] }, (extract_cpol:{ *:[i32] } ?:{ *:[i32] }:$cachepolicy))
        GIR_BuildMI, /*InsnID*/0, /*Opcode*/GIMT_Encode2(AMDGPU::S_BUFFER_LOAD_DWORDX2_SGPR_IMM),
        GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/0, // DstI[sdst]
        GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/1, // sbase
        GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/2, // soffset
        GIR_AddImm8, /*InsnID*/0, /*Imm*/0,
        GIR_CustomOperandRenderer, /*InsnID*/0, /*OldInsnID*/0, /*OpIdx*/3, /*OperandRenderer*/GIMT_Encode2(GICR_renderExtractCPol), // cachepolicy
        GIR_MergeMemOperands, /*InsnID*/0, /*NumInsns*/1, /*MergeInsnID's*/0,
        GIR_ConstrainSelectedInstOperands, /*InsnID*/0,
        GIR_EraseFromParent, /*InsnID*/0,
        // GIR_Coverage, 2716,
        GIR_Done,
      // Label 7151: @523054
      GIM_Reject,
    // Label 7141: @523055
    GIM_Reject,
    // Label 7125: @523056
    GIM_Try, /*On fail goto*//*Label 7152*/ GIMT_Encode4(523432),
      GIM_CheckType, /*MI*/0, /*Op*/1, /*Type*/GILLT_v4s32,
      GIM_CheckType, /*MI*/0, /*Op*/2, /*Type*/GILLT_s32,
      GIM_CheckRegBankForClass, /*MI*/0, /*Op*/0, /*RC*/GIMT_Encode2(AMDGPU::SReg_96RegClassID),
      GIM_CheckIsImm, /*MI*/0, /*Op*/3,
      GIM_Try, /*On fail goto*//*Label 7153*/ GIMT_Encode4(523129), // Rule ID 2692 //
        GIM_CheckFeatures, GIMT_Encode2(GIFBS_isGFX9Plus),
        GIM_CheckComplexPattern, /*MI*/0, /*Op*/2, /*Renderer*/GIMT_Encode2(0), GIMT_Encode2(GICP_gi_smrd_buffer_sgpr_imm),
        // (SIsbuffer_load:{ *:[v3i32] } v4i32:{ *:[v4i32] }:$sbase, (SMRDBufferSgprImm:{ *:[i32] } i32:{ *:[i32] }:$soffset, i32:{ *:[i32] }:$offset), (timm:{ *:[i32] }):$cachepolicy)  =>  (S_BUFFER_LOAD_DWORDX3_SGPR_IMM:{ *:[v3i32] } SReg_128:{ *:[v4i32] }:$sbase, SReg_32:{ *:[i32] }:$soffset, i32imm:{ *:[i32] }:$offset, (extract_cpol:{ *:[i32] } ?:{ *:[i32] }:$cachepolicy))
        GIR_BuildMI, /*InsnID*/0, /*Opcode*/GIMT_Encode2(AMDGPU::S_BUFFER_LOAD_DWORDX3_SGPR_IMM),
        GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/0, // DstI[sdst]
        GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/1, // sbase
        GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/0, // soffset
        GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/1, // offset
        GIR_CustomOperandRenderer, /*InsnID*/0, /*OldInsnID*/0, /*OpIdx*/3, /*OperandRenderer*/GIMT_Encode2(GICR_renderExtractCPol), // cachepolicy
        GIR_MergeMemOperands, /*InsnID*/0, /*NumInsns*/1, /*MergeInsnID's*/0,
        GIR_ConstrainSelectedInstOperands, /*InsnID*/0,
        GIR_EraseFromParent, /*InsnID*/0,
        // GIR_Coverage, 2692,
        GIR_Done,
      // Label 7153: @523129
      GIM_Try, /*On fail goto*//*Label 7154*/ GIMT_Encode4(523181), // Rule ID 2721 //
        GIM_CheckFeatures, GIMT_Encode2(GIFBS_isGFX9Plus),
        GIM_CheckComplexPattern, /*MI*/0, /*Op*/2, /*Renderer*/GIMT_Encode2(0), GIMT_Encode2(GICP_gi_smrd_buffer_sgpr_imm),
        // (SIsbuffer_load:{ *:[v3f32] } v4i32:{ *:[v4i32] }:$sbase, (SMRDBufferSgprImm:{ *:[i32] } i32:{ *:[i32] }:$soffset, i32:{ *:[i32] }:$offset), (timm:{ *:[i32] }):$cachepolicy)  =>  (S_BUFFER_LOAD_DWORDX3_SGPR_IMM:{ *:[v3f32] } SReg_128:{ *:[v4i32] }:$sbase, SReg_32:{ *:[i32] }:$soffset, i32imm:{ *:[i32] }:$offset, (extract_cpol:{ *:[i32] } ?:{ *:[i32] }:$cachepolicy))
        GIR_BuildMI, /*InsnID*/0, /*Opcode*/GIMT_Encode2(AMDGPU::S_BUFFER_LOAD_DWORDX3_SGPR_IMM),
        GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/0, // DstI[sdst]
        GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/1, // sbase
        GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/0, // soffset
        GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/1, // offset
        GIR_CustomOperandRenderer, /*InsnID*/0, /*OldInsnID*/0, /*OpIdx*/3, /*OperandRenderer*/GIMT_Encode2(GICR_renderExtractCPol), // cachepolicy
        GIR_MergeMemOperands, /*InsnID*/0, /*NumInsns*/1, /*MergeInsnID's*/0,
        GIR_ConstrainSelectedInstOperands, /*InsnID*/0,
        GIR_EraseFromParent, /*InsnID*/0,
        // GIR_Coverage, 2721,
        GIR_Done,
      // Label 7154: @523181
      GIM_Try, /*On fail goto*//*Label 7155*/ GIMT_Encode4(523225), // Rule ID 2689 //
        GIM_CheckComplexPattern, /*MI*/0, /*Op*/2, /*Renderer*/GIMT_Encode2(0), GIMT_Encode2(GICP_gi_smrd_buffer_imm),
        // (SIsbuffer_load:{ *:[v3i32] } v4i32:{ *:[v4i32] }:$sbase, (SMRDBufferImm:{ *:[i32] } i32:{ *:[i32] }:$offset), (timm:{ *:[i32] }):$cachepolicy)  =>  (S_BUFFER_LOAD_DWORDX3_IMM:{ *:[v3i32] } SReg_128:{ *:[v4i32] }:$sbase, i32imm:{ *:[i32] }:$offset, (extract_cpol:{ *:[i32] } ?:{ *:[i32] }:$cachepolicy))
        GIR_BuildMI, /*InsnID*/0, /*Opcode*/GIMT_Encode2(AMDGPU::S_BUFFER_LOAD_DWORDX3_IMM),
        GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/0, // DstI[sdst]
        GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/1, // sbase
        GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/0, // offset
        GIR_CustomOperandRenderer, /*InsnID*/0, /*OldInsnID*/0, /*OpIdx*/3, /*OperandRenderer*/GIMT_Encode2(GICR_renderExtractCPol), // cachepolicy
        GIR_MergeMemOperands, /*InsnID*/0, /*NumInsns*/1, /*MergeInsnID's*/0,
        GIR_ConstrainSelectedInstOperands, /*InsnID*/0,
        GIR_EraseFromParent, /*InsnID*/0,
        // GIR_Coverage, 2689,
        GIR_Done,
      // Label 7155: @523225
      GIM_Try, /*On fail goto*//*Label 7156*/ GIMT_Encode4(523269), // Rule ID 2718 //
        GIM_CheckComplexPattern, /*MI*/0, /*Op*/2, /*Renderer*/GIMT_Encode2(0), GIMT_Encode2(GICP_gi_smrd_buffer_imm),
        // (SIsbuffer_load:{ *:[v3f32] } v4i32:{ *:[v4i32] }:$sbase, (SMRDBufferImm:{ *:[i32] } i32:{ *:[i32] }:$offset), (timm:{ *:[i32] }):$cachepolicy)  =>  (S_BUFFER_LOAD_DWORDX3_IMM:{ *:[v3f32] } SReg_128:{ *:[v4i32] }:$sbase, i32imm:{ *:[i32] }:$offset, (extract_cpol:{ *:[i32] } ?:{ *:[i32] }:$cachepolicy))
        GIR_BuildMI, /*InsnID*/0, /*Opcode*/GIMT_Encode2(AMDGPU::S_BUFFER_LOAD_DWORDX3_IMM),
        GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/0, // DstI[sdst]
        GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/1, // sbase
        GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/0, // offset
        GIR_CustomOperandRenderer, /*InsnID*/0, /*OldInsnID*/0, /*OpIdx*/3, /*OperandRenderer*/GIMT_Encode2(GICR_renderExtractCPol), // cachepolicy
        GIR_MergeMemOperands, /*InsnID*/0, /*NumInsns*/1, /*MergeInsnID's*/0,
        GIR_ConstrainSelectedInstOperands, /*InsnID*/0,
        GIR_EraseFromParent, /*InsnID*/0,
        // GIR_Coverage, 2718,
        GIR_Done,
      // Label 7156: @523269
      GIM_Try, /*On fail goto*//*Label 7157*/ GIMT_Encode4(523308), // Rule ID 2690 //
        GIM_CheckFeatures, GIMT_Encode2(GIFBS_isNotGFX9Plus),
        // (SIsbuffer_load:{ *:[v3i32] } v4i32:{ *:[v4i32] }:$sbase, i32:{ *:[i32] }:$soffset, (timm:{ *:[i32] }):$cachepolicy)  =>  (S_BUFFER_LOAD_DWORDX3_SGPR:{ *:[v3i32] } SReg_128:{ *:[v4i32] }:$sbase, SReg_32:{ *:[i32] }:$soffset, (extract_cpol:{ *:[i32] } ?:{ *:[i32] }:$cachepolicy))
        GIR_BuildMI, /*InsnID*/0, /*Opcode*/GIMT_Encode2(AMDGPU::S_BUFFER_LOAD_DWORDX3_SGPR),
        GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/0, // DstI[sdst]
        GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/1, // sbase
        GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/2, // soffset
        GIR_CustomOperandRenderer, /*InsnID*/0, /*OldInsnID*/0, /*OpIdx*/3, /*OperandRenderer*/GIMT_Encode2(GICR_renderExtractCPol), // cachepolicy
        GIR_MergeMemOperands, /*InsnID*/0, /*NumInsns*/1, /*MergeInsnID's*/0,
        GIR_ConstrainSelectedInstOperands, /*InsnID*/0,
        GIR_EraseFromParent, /*InsnID*/0,
        // GIR_Coverage, 2690,
        GIR_Done,
      // Label 7157: @523308
      GIM_Try, /*On fail goto*//*Label 7158*/ GIMT_Encode4(523350), // Rule ID 2691 //
        GIM_CheckFeatures, GIMT_Encode2(GIFBS_isGFX9Plus),
        // (SIsbuffer_load:{ *:[v3i32] } v4i32:{ *:[v4i32] }:$sbase, i32:{ *:[i32] }:$soffset, (timm:{ *:[i32] }):$cachepolicy)  =>  (S_BUFFER_LOAD_DWORDX3_SGPR_IMM:{ *:[v3i32] } SReg_128:{ *:[v4i32] }:$sbase, SReg_32:{ *:[i32] }:$soffset, 0:{ *:[i32] }, (extract_cpol:{ *:[i32] } ?:{ *:[i32] }:$cachepolicy))
        GIR_BuildMI, /*InsnID*/0, /*Opcode*/GIMT_Encode2(AMDGPU::S_BUFFER_LOAD_DWORDX3_SGPR_IMM),
        GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/0, // DstI[sdst]
        GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/1, // sbase
        GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/2, // soffset
        GIR_AddImm8, /*InsnID*/0, /*Imm*/0,
        GIR_CustomOperandRenderer, /*InsnID*/0, /*OldInsnID*/0, /*OpIdx*/3, /*OperandRenderer*/GIMT_Encode2(GICR_renderExtractCPol), // cachepolicy
        GIR_MergeMemOperands, /*InsnID*/0, /*NumInsns*/1, /*MergeInsnID's*/0,
        GIR_ConstrainSelectedInstOperands, /*InsnID*/0,
        GIR_EraseFromParent, /*InsnID*/0,
        // GIR_Coverage, 2691,
        GIR_Done,
      // Label 7158: @523350
      GIM_Try, /*On fail goto*//*Label 7159*/ GIMT_Encode4(523389), // Rule ID 2719 //
        GIM_CheckFeatures, GIMT_Encode2(GIFBS_isNotGFX9Plus),
        // (SIsbuffer_load:{ *:[v3f32] } v4i32:{ *:[v4i32] }:$sbase, i32:{ *:[i32] }:$soffset, (timm:{ *:[i32] }):$cachepolicy)  =>  (S_BUFFER_LOAD_DWORDX3_SGPR:{ *:[v3f32] } SReg_128:{ *:[v4i32] }:$sbase, SReg_32:{ *:[i32] }:$soffset, (extract_cpol:{ *:[i32] } ?:{ *:[i32] }:$cachepolicy))
        GIR_BuildMI, /*InsnID*/0, /*Opcode*/GIMT_Encode2(AMDGPU::S_BUFFER_LOAD_DWORDX3_SGPR),
        GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/0, // DstI[sdst]
        GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/1, // sbase
        GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/2, // soffset
        GIR_CustomOperandRenderer, /*InsnID*/0, /*OldInsnID*/0, /*OpIdx*/3, /*OperandRenderer*/GIMT_Encode2(GICR_renderExtractCPol), // cachepolicy
        GIR_MergeMemOperands, /*InsnID*/0, /*NumInsns*/1, /*MergeInsnID's*/0,
        GIR_ConstrainSelectedInstOperands, /*InsnID*/0,
        GIR_EraseFromParent, /*InsnID*/0,
        // GIR_Coverage, 2719,
        GIR_Done,
      // Label 7159: @523389
      GIM_Try, /*On fail goto*//*Label 7160*/ GIMT_Encode4(523431), // Rule ID 2720 //
        GIM_CheckFeatures, GIMT_Encode2(GIFBS_isGFX9Plus),
        // (SIsbuffer_load:{ *:[v3f32] } v4i32:{ *:[v4i32] }:$sbase, i32:{ *:[i32] }:$soffset, (timm:{ *:[i32] }):$cachepolicy)  =>  (S_BUFFER_LOAD_DWORDX3_SGPR_IMM:{ *:[v3f32] } SReg_128:{ *:[v4i32] }:$sbase, SReg_32:{ *:[i32] }:$soffset, 0:{ *:[i32] }, (extract_cpol:{ *:[i32] } ?:{ *:[i32] }:$cachepolicy))
        GIR_BuildMI, /*InsnID*/0, /*Opcode*/GIMT_Encode2(AMDGPU::S_BUFFER_LOAD_DWORDX3_SGPR_IMM),
        GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/0, // DstI[sdst]
        GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/1, // sbase
        GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/2, // soffset
        GIR_AddImm8, /*InsnID*/0, /*Imm*/0,
        GIR_CustomOperandRenderer, /*InsnID*/0, /*OldInsnID*/0, /*OpIdx*/3, /*OperandRenderer*/GIMT_Encode2(GICR_renderExtractCPol), // cachepolicy
        GIR_MergeMemOperands, /*InsnID*/0, /*NumInsns*/1, /*MergeInsnID's*/0,
        GIR_ConstrainSelectedInstOperands, /*InsnID*/0,
        GIR_EraseFromParent, /*InsnID*/0,
        // GIR_Coverage, 2720,
        GIR_Done,
      // Label 7160: @523431
      GIM_Reject,
    // Label 7152: @523432
    GIM_Reject,
    // Label 7126: @523433
    GIM_Try, /*On fail goto*//*Label 7161*/ GIMT_Encode4(523903),
      GIM_CheckType, /*MI*/0, /*Op*/1, /*Type*/GILLT_v4s32,
      GIM_CheckType, /*MI*/0, /*Op*/2, /*Type*/GILLT_s32,
      GIM_CheckRegBankForClass, /*MI*/0, /*Op*/0, /*RC*/GIMT_Encode2(AMDGPU::SReg_128RegClassID),
      GIM_CheckIsImm, /*MI*/0, /*Op*/3,
      GIM_Try, /*On fail goto*//*Label 7162*/ GIMT_Encode4(523506), // Rule ID 2697 //
        GIM_CheckFeatures, GIMT_Encode2(GIFBS_isGFX9Plus),
        GIM_CheckComplexPattern, /*MI*/0, /*Op*/2, /*Renderer*/GIMT_Encode2(0), GIMT_Encode2(GICP_gi_smrd_buffer_sgpr_imm),
        // (SIsbuffer_load:{ *:[v4i32] } v4i32:{ *:[v4i32] }:$sbase, (SMRDBufferSgprImm:{ *:[i32] } i32:{ *:[i32] }:$soffset, i32:{ *:[i32] }:$offset), (timm:{ *:[i32] }):$cachepolicy)  =>  (S_BUFFER_LOAD_DWORDX4_SGPR_IMM:{ *:[v4i32] } SReg_128:{ *:[v4i32] }:$sbase, SReg_32:{ *:[i32] }:$soffset, i32imm:{ *:[i32] }:$offset, (extract_cpol:{ *:[i32] } ?:{ *:[i32] }:$cachepolicy))
        GIR_BuildMI, /*InsnID*/0, /*Opcode*/GIMT_Encode2(AMDGPU::S_BUFFER_LOAD_DWORDX4_SGPR_IMM),
        GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/0, // DstI[sdst]
        GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/1, // sbase
        GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/0, // soffset
        GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/1, // offset
        GIR_CustomOperandRenderer, /*InsnID*/0, /*OldInsnID*/0, /*OpIdx*/3, /*OperandRenderer*/GIMT_Encode2(GICR_renderExtractCPol), // cachepolicy
        GIR_MergeMemOperands, /*InsnID*/0, /*NumInsns*/1, /*MergeInsnID's*/0,
        GIR_ConstrainSelectedInstOperands, /*InsnID*/0,
        GIR_EraseFromParent, /*InsnID*/0,
        // GIR_Coverage, 2697,
        GIR_Done,
      // Label 7162: @523506
      GIM_Try, /*On fail goto*//*Label 7163*/ GIMT_Encode4(523558), // Rule ID 2726 //
        GIM_CheckFeatures, GIMT_Encode2(GIFBS_isGFX9Plus),
        GIM_CheckComplexPattern, /*MI*/0, /*Op*/2, /*Renderer*/GIMT_Encode2(0), GIMT_Encode2(GICP_gi_smrd_buffer_sgpr_imm),
        // (SIsbuffer_load:{ *:[v4f32] } v4i32:{ *:[v4i32] }:$sbase, (SMRDBufferSgprImm:{ *:[i32] } i32:{ *:[i32] }:$soffset, i32:{ *:[i32] }:$offset), (timm:{ *:[i32] }):$cachepolicy)  =>  (S_BUFFER_LOAD_DWORDX4_SGPR_IMM:{ *:[v4f32] } SReg_128:{ *:[v4i32] }:$sbase, SReg_32:{ *:[i32] }:$soffset, i32imm:{ *:[i32] }:$offset, (extract_cpol:{ *:[i32] } ?:{ *:[i32] }:$cachepolicy))
        GIR_BuildMI, /*InsnID*/0, /*Opcode*/GIMT_Encode2(AMDGPU::S_BUFFER_LOAD_DWORDX4_SGPR_IMM),
        GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/0, // DstI[sdst]
        GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/1, // sbase
        GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/0, // soffset
        GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/1, // offset
        GIR_CustomOperandRenderer, /*InsnID*/0, /*OldInsnID*/0, /*OpIdx*/3, /*OperandRenderer*/GIMT_Encode2(GICR_renderExtractCPol), // cachepolicy
        GIR_MergeMemOperands, /*InsnID*/0, /*NumInsns*/1, /*MergeInsnID's*/0,
        GIR_ConstrainSelectedInstOperands, /*InsnID*/0,
        GIR_EraseFromParent, /*InsnID*/0,
        // GIR_Coverage, 2726,
        GIR_Done,
      // Label 7163: @523558
      GIM_Try, /*On fail goto*//*Label 7164*/ GIMT_Encode4(523602), // Rule ID 2693 //
        GIM_CheckComplexPattern, /*MI*/0, /*Op*/2, /*Renderer*/GIMT_Encode2(0), GIMT_Encode2(GICP_gi_smrd_buffer_imm),
        // (SIsbuffer_load:{ *:[v4i32] } v4i32:{ *:[v4i32] }:$sbase, (SMRDBufferImm:{ *:[i32] } i32:{ *:[i32] }:$offset), (timm:{ *:[i32] }):$cachepolicy)  =>  (S_BUFFER_LOAD_DWORDX4_IMM:{ *:[v4i32] } SReg_128:{ *:[v4i32] }:$sbase, i32imm:{ *:[i32] }:$offset, (extract_cpol:{ *:[i32] } ?:{ *:[i32] }:$cachepolicy))
        GIR_BuildMI, /*InsnID*/0, /*Opcode*/GIMT_Encode2(AMDGPU::S_BUFFER_LOAD_DWORDX4_IMM),
        GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/0, // DstI[sdst]
        GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/1, // sbase
        GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/0, // offset
        GIR_CustomOperandRenderer, /*InsnID*/0, /*OldInsnID*/0, /*OpIdx*/3, /*OperandRenderer*/GIMT_Encode2(GICR_renderExtractCPol), // cachepolicy
        GIR_MergeMemOperands, /*InsnID*/0, /*NumInsns*/1, /*MergeInsnID's*/0,
        GIR_ConstrainSelectedInstOperands, /*InsnID*/0,
        GIR_EraseFromParent, /*InsnID*/0,
        // GIR_Coverage, 2693,
        GIR_Done,
      // Label 7164: @523602
      GIM_Try, /*On fail goto*//*Label 7165*/ GIMT_Encode4(523646), // Rule ID 2722 //
        GIM_CheckComplexPattern, /*MI*/0, /*Op*/2, /*Renderer*/GIMT_Encode2(0), GIMT_Encode2(GICP_gi_smrd_buffer_imm),
        // (SIsbuffer_load:{ *:[v4f32] } v4i32:{ *:[v4i32] }:$sbase, (SMRDBufferImm:{ *:[i32] } i32:{ *:[i32] }:$offset), (timm:{ *:[i32] }):$cachepolicy)  =>  (S_BUFFER_LOAD_DWORDX4_IMM:{ *:[v4f32] } SReg_128:{ *:[v4i32] }:$sbase, i32imm:{ *:[i32] }:$offset, (extract_cpol:{ *:[i32] } ?:{ *:[i32] }:$cachepolicy))
        GIR_BuildMI, /*InsnID*/0, /*Opcode*/GIMT_Encode2(AMDGPU::S_BUFFER_LOAD_DWORDX4_IMM),
        GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/0, // DstI[sdst]
        GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/1, // sbase
        GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/0, // offset
        GIR_CustomOperandRenderer, /*InsnID*/0, /*OldInsnID*/0, /*OpIdx*/3, /*OperandRenderer*/GIMT_Encode2(GICR_renderExtractCPol), // cachepolicy
        GIR_MergeMemOperands, /*InsnID*/0, /*NumInsns*/1, /*MergeInsnID's*/0,
        GIR_ConstrainSelectedInstOperands, /*InsnID*/0,
        GIR_EraseFromParent, /*InsnID*/0,
        // GIR_Coverage, 2722,
        GIR_Done,
      // Label 7165: @523646
      GIM_Try, /*On fail goto*//*Label 7166*/ GIMT_Encode4(523693), // Rule ID 2694 //
        GIM_CheckFeatures, GIMT_Encode2(GIFBS_isGFX7Only),
        GIM_CheckComplexPattern, /*MI*/0, /*Op*/2, /*Renderer*/GIMT_Encode2(0), GIMT_Encode2(GICP_gi_smrd_buffer_imm32),
        // (SIsbuffer_load:{ *:[v4i32] } v4i32:{ *:[v4i32] }:$sbase, (SMRDBufferImm32:{ *:[i32] } i32:{ *:[i32] }:$offset), (timm:{ *:[i32] }):$cachepolicy)  =>  (S_BUFFER_LOAD_DWORDX4_IMM_ci:{ *:[v4i32] } SReg_128:{ *:[v4i32] }:$sbase, smrd_literal_offset:{ *:[i32] }:$offset, (extract_cpol:{ *:[i32] } ?:{ *:[i32] }:$cachepolicy))
        GIR_BuildMI, /*InsnID*/0, /*Opcode*/GIMT_Encode2(AMDGPU::S_BUFFER_LOAD_DWORDX4_IMM_ci),
        GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/0, // DstI[sdst]
        GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/1, // sbase
        GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/0, // offset
        GIR_CustomOperandRenderer, /*InsnID*/0, /*OldInsnID*/0, /*OpIdx*/3, /*OperandRenderer*/GIMT_Encode2(GICR_renderExtractCPol), // cachepolicy
        GIR_MergeMemOperands, /*InsnID*/0, /*NumInsns*/1, /*MergeInsnID's*/0,
        GIR_ConstrainSelectedInstOperands, /*InsnID*/0,
        GIR_EraseFromParent, /*InsnID*/0,
        // GIR_Coverage, 2694,
        GIR_Done,
      // Label 7166: @523693
      GIM_Try, /*On fail goto*//*Label 7167*/ GIMT_Encode4(523740), // Rule ID 2723 //
        GIM_CheckFeatures, GIMT_Encode2(GIFBS_isGFX7Only),
        GIM_CheckComplexPattern, /*MI*/0, /*Op*/2, /*Renderer*/GIMT_Encode2(0), GIMT_Encode2(GICP_gi_smrd_buffer_imm32),
        // (SIsbuffer_load:{ *:[v4f32] } v4i32:{ *:[v4i32] }:$sbase, (SMRDBufferImm32:{ *:[i32] } i32:{ *:[i32] }:$offset), (timm:{ *:[i32] }):$cachepolicy)  =>  (S_BUFFER_LOAD_DWORDX4_IMM_ci:{ *:[v4f32] } SReg_128:{ *:[v4i32] }:$sbase, smrd_literal_offset:{ *:[i32] }:$offset, (extract_cpol:{ *:[i32] } ?:{ *:[i32] }:$cachepolicy))
        GIR_BuildMI, /*InsnID*/0, /*Opcode*/GIMT_Encode2(AMDGPU::S_BUFFER_LOAD_DWORDX4_IMM_ci),
        GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/0, // DstI[sdst]
        GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/1, // sbase
        GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/0, // offset
        GIR_CustomOperandRenderer, /*InsnID*/0, /*OldInsnID*/0, /*OpIdx*/3, /*OperandRenderer*/GIMT_Encode2(GICR_renderExtractCPol), // cachepolicy
        GIR_MergeMemOperands, /*InsnID*/0, /*NumInsns*/1, /*MergeInsnID's*/0,
        GIR_ConstrainSelectedInstOperands, /*InsnID*/0,
        GIR_EraseFromParent, /*InsnID*/0,
        // GIR_Coverage, 2723,
        GIR_Done,
      // Label 7167: @523740
      GIM_Try, /*On fail goto*//*Label 7168*/ GIMT_Encode4(523779), // Rule ID 2695 //
        GIM_CheckFeatures, GIMT_Encode2(GIFBS_isNotGFX9Plus),
        // (SIsbuffer_load:{ *:[v4i32] } v4i32:{ *:[v4i32] }:$sbase, i32:{ *:[i32] }:$soffset, (timm:{ *:[i32] }):$cachepolicy)  =>  (S_BUFFER_LOAD_DWORDX4_SGPR:{ *:[v4i32] } SReg_128:{ *:[v4i32] }:$sbase, SReg_32:{ *:[i32] }:$soffset, (extract_cpol:{ *:[i32] } ?:{ *:[i32] }:$cachepolicy))
        GIR_BuildMI, /*InsnID*/0, /*Opcode*/GIMT_Encode2(AMDGPU::S_BUFFER_LOAD_DWORDX4_SGPR),
        GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/0, // DstI[sdst]
        GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/1, // sbase
        GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/2, // soffset
        GIR_CustomOperandRenderer, /*InsnID*/0, /*OldInsnID*/0, /*OpIdx*/3, /*OperandRenderer*/GIMT_Encode2(GICR_renderExtractCPol), // cachepolicy
        GIR_MergeMemOperands, /*InsnID*/0, /*NumInsns*/1, /*MergeInsnID's*/0,
        GIR_ConstrainSelectedInstOperands, /*InsnID*/0,
        GIR_EraseFromParent, /*InsnID*/0,
        // GIR_Coverage, 2695,
        GIR_Done,
      // Label 7168: @523779
      GIM_Try, /*On fail goto*//*Label 7169*/ GIMT_Encode4(523821), // Rule ID 2696 //
        GIM_CheckFeatures, GIMT_Encode2(GIFBS_isGFX9Plus),
        // (SIsbuffer_load:{ *:[v4i32] } v4i32:{ *:[v4i32] }:$sbase, i32:{ *:[i32] }:$soffset, (timm:{ *:[i32] }):$cachepolicy)  =>  (S_BUFFER_LOAD_DWORDX4_SGPR_IMM:{ *:[v4i32] } SReg_128:{ *:[v4i32] }:$sbase, SReg_32:{ *:[i32] }:$soffset, 0:{ *:[i32] }, (extract_cpol:{ *:[i32] } ?:{ *:[i32] }:$cachepolicy))
        GIR_BuildMI, /*InsnID*/0, /*Opcode*/GIMT_Encode2(AMDGPU::S_BUFFER_LOAD_DWORDX4_SGPR_IMM),
        GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/0, // DstI[sdst]
        GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/1, // sbase
        GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/2, // soffset
        GIR_AddImm8, /*InsnID*/0, /*Imm*/0,
        GIR_CustomOperandRenderer, /*InsnID*/0, /*OldInsnID*/0, /*OpIdx*/3, /*OperandRenderer*/GIMT_Encode2(GICR_renderExtractCPol), // cachepolicy
        GIR_MergeMemOperands, /*InsnID*/0, /*NumInsns*/1, /*MergeInsnID's*/0,
        GIR_ConstrainSelectedInstOperands, /*InsnID*/0,
        GIR_EraseFromParent, /*InsnID*/0,
        // GIR_Coverage, 2696,
        GIR_Done,
      // Label 7169: @523821
      GIM_Try, /*On fail goto*//*Label 7170*/ GIMT_Encode4(523860), // Rule ID 2724 //
        GIM_CheckFeatures, GIMT_Encode2(GIFBS_isNotGFX9Plus),
        // (SIsbuffer_load:{ *:[v4f32] } v4i32:{ *:[v4i32] }:$sbase, i32:{ *:[i32] }:$soffset, (timm:{ *:[i32] }):$cachepolicy)  =>  (S_BUFFER_LOAD_DWORDX4_SGPR:{ *:[v4f32] } SReg_128:{ *:[v4i32] }:$sbase, SReg_32:{ *:[i32] }:$soffset, (extract_cpol:{ *:[i32] } ?:{ *:[i32] }:$cachepolicy))
        GIR_BuildMI, /*InsnID*/0, /*Opcode*/GIMT_Encode2(AMDGPU::S_BUFFER_LOAD_DWORDX4_SGPR),
        GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/0, // DstI[sdst]
        GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/1, // sbase
        GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/2, // soffset
        GIR_CustomOperandRenderer, /*InsnID*/0, /*OldInsnID*/0, /*OpIdx*/3, /*OperandRenderer*/GIMT_Encode2(GICR_renderExtractCPol), // cachepolicy
        GIR_MergeMemOperands, /*InsnID*/0, /*NumInsns*/1, /*MergeInsnID's*/0,
        GIR_ConstrainSelectedInstOperands, /*InsnID*/0,
        GIR_EraseFromParent, /*InsnID*/0,
        // GIR_Coverage, 2724,
        GIR_Done,
      // Label 7170: @523860
      GIM_Try, /*On fail goto*//*Label 7171*/ GIMT_Encode4(523902), // Rule ID 2725 //
        GIM_CheckFeatures, GIMT_Encode2(GIFBS_isGFX9Plus),
        // (SIsbuffer_load:{ *:[v4f32] } v4i32:{ *:[v4i32] }:$sbase, i32:{ *:[i32] }:$soffset, (timm:{ *:[i32] }):$cachepolicy)  =>  (S_BUFFER_LOAD_DWORDX4_SGPR_IMM:{ *:[v4f32] } SReg_128:{ *:[v4i32] }:$sbase, SReg_32:{ *:[i32] }:$soffset, 0:{ *:[i32] }, (extract_cpol:{ *:[i32] } ?:{ *:[i32] }:$cachepolicy))
        GIR_BuildMI, /*InsnID*/0, /*Opcode*/GIMT_Encode2(AMDGPU::S_BUFFER_LOAD_DWORDX4_SGPR_IMM),
        GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/0, // DstI[sdst]
        GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/1, // sbase
        GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/2, // soffset
        GIR_AddImm8, /*InsnID*/0, /*Imm*/0,
        GIR_CustomOperandRenderer, /*InsnID*/0, /*OldInsnID*/0, /*OpIdx*/3, /*OperandRenderer*/GIMT_Encode2(GICR_renderExtractCPol), // cachepolicy
        GIR_MergeMemOperands, /*InsnID*/0, /*NumInsns*/1, /*MergeInsnID's*/0,
        GIR_ConstrainSelectedInstOperands, /*InsnID*/0,
        GIR_EraseFromParent, /*InsnID*/0,
        // GIR_Coverage, 2725,
        GIR_Done,
      // Label 7171: @523902
      GIM_Reject,
    // Label 7161: @523903
    GIM_Reject,
    // Label 7127: @523904
    GIM_Try, /*On fail goto*//*Label 7172*/ GIMT_Encode4(524374),
      GIM_CheckType, /*MI*/0, /*Op*/1, /*Type*/GILLT_v4s32,
      GIM_CheckType, /*MI*/0, /*Op*/2, /*Type*/GILLT_s32,
      GIM_CheckRegBankForClass, /*MI*/0, /*Op*/0, /*RC*/GIMT_Encode2(AMDGPU::SReg_256RegClassID),
      GIM_CheckIsImm, /*MI*/0, /*Op*/3,
      GIM_Try, /*On fail goto*//*Label 7173*/ GIMT_Encode4(523977), // Rule ID 2702 //
        GIM_CheckFeatures, GIMT_Encode2(GIFBS_isGFX9Plus),
        GIM_CheckComplexPattern, /*MI*/0, /*Op*/2, /*Renderer*/GIMT_Encode2(0), GIMT_Encode2(GICP_gi_smrd_buffer_sgpr_imm),
        // (SIsbuffer_load:{ *:[v8i32] } v4i32:{ *:[v4i32] }:$sbase, (SMRDBufferSgprImm:{ *:[i32] } i32:{ *:[i32] }:$soffset, i32:{ *:[i32] }:$offset), (timm:{ *:[i32] }):$cachepolicy)  =>  (S_BUFFER_LOAD_DWORDX8_SGPR_IMM:{ *:[v8i32] } SReg_128:{ *:[v4i32] }:$sbase, SReg_32:{ *:[i32] }:$soffset, i32imm:{ *:[i32] }:$offset, (extract_cpol:{ *:[i32] } ?:{ *:[i32] }:$cachepolicy))
        GIR_BuildMI, /*InsnID*/0, /*Opcode*/GIMT_Encode2(AMDGPU::S_BUFFER_LOAD_DWORDX8_SGPR_IMM),
        GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/0, // DstI[sdst]
        GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/1, // sbase
        GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/0, // soffset
        GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/1, // offset
        GIR_CustomOperandRenderer, /*InsnID*/0, /*OldInsnID*/0, /*OpIdx*/3, /*OperandRenderer*/GIMT_Encode2(GICR_renderExtractCPol), // cachepolicy
        GIR_MergeMemOperands, /*InsnID*/0, /*NumInsns*/1, /*MergeInsnID's*/0,
        GIR_ConstrainSelectedInstOperands, /*InsnID*/0,
        GIR_EraseFromParent, /*InsnID*/0,
        // GIR_Coverage, 2702,
        GIR_Done,
      // Label 7173: @523977
      GIM_Try, /*On fail goto*//*Label 7174*/ GIMT_Encode4(524029), // Rule ID 2731 //
        GIM_CheckFeatures, GIMT_Encode2(GIFBS_isGFX9Plus),
        GIM_CheckComplexPattern, /*MI*/0, /*Op*/2, /*Renderer*/GIMT_Encode2(0), GIMT_Encode2(GICP_gi_smrd_buffer_sgpr_imm),
        // (SIsbuffer_load:{ *:[v8f32] } v4i32:{ *:[v4i32] }:$sbase, (SMRDBufferSgprImm:{ *:[i32] } i32:{ *:[i32] }:$soffset, i32:{ *:[i32] }:$offset), (timm:{ *:[i32] }):$cachepolicy)  =>  (S_BUFFER_LOAD_DWORDX8_SGPR_IMM:{ *:[v8f32] } SReg_128:{ *:[v4i32] }:$sbase, SReg_32:{ *:[i32] }:$soffset, i32imm:{ *:[i32] }:$offset, (extract_cpol:{ *:[i32] } ?:{ *:[i32] }:$cachepolicy))
        GIR_BuildMI, /*InsnID*/0, /*Opcode*/GIMT_Encode2(AMDGPU::S_BUFFER_LOAD_DWORDX8_SGPR_IMM),
        GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/0, // DstI[sdst]
        GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/1, // sbase
        GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/0, // soffset
        GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/1, // offset
        GIR_CustomOperandRenderer, /*InsnID*/0, /*OldInsnID*/0, /*OpIdx*/3, /*OperandRenderer*/GIMT_Encode2(GICR_renderExtractCPol), // cachepolicy
        GIR_MergeMemOperands, /*InsnID*/0, /*NumInsns*/1, /*MergeInsnID's*/0,
        GIR_ConstrainSelectedInstOperands, /*InsnID*/0,
        GIR_EraseFromParent, /*InsnID*/0,
        // GIR_Coverage, 2731,
        GIR_Done,
      // Label 7174: @524029
      GIM_Try, /*On fail goto*//*Label 7175*/ GIMT_Encode4(524073), // Rule ID 2698 //
        GIM_CheckComplexPattern, /*MI*/0, /*Op*/2, /*Renderer*/GIMT_Encode2(0), GIMT_Encode2(GICP_gi_smrd_buffer_imm),
        // (SIsbuffer_load:{ *:[v8i32] } v4i32:{ *:[v4i32] }:$sbase, (SMRDBufferImm:{ *:[i32] } i32:{ *:[i32] }:$offset), (timm:{ *:[i32] }):$cachepolicy)  =>  (S_BUFFER_LOAD_DWORDX8_IMM:{ *:[v8i32] } SReg_128:{ *:[v4i32] }:$sbase, i32imm:{ *:[i32] }:$offset, (extract_cpol:{ *:[i32] } ?:{ *:[i32] }:$cachepolicy))
        GIR_BuildMI, /*InsnID*/0, /*Opcode*/GIMT_Encode2(AMDGPU::S_BUFFER_LOAD_DWORDX8_IMM),
        GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/0, // DstI[sdst]
        GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/1, // sbase
        GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/0, // offset
        GIR_CustomOperandRenderer, /*InsnID*/0, /*OldInsnID*/0, /*OpIdx*/3, /*OperandRenderer*/GIMT_Encode2(GICR_renderExtractCPol), // cachepolicy
        GIR_MergeMemOperands, /*InsnID*/0, /*NumInsns*/1, /*MergeInsnID's*/0,
        GIR_ConstrainSelectedInstOperands, /*InsnID*/0,
        GIR_EraseFromParent, /*InsnID*/0,
        // GIR_Coverage, 2698,
        GIR_Done,
      // Label 7175: @524073
      GIM_Try, /*On fail goto*//*Label 7176*/ GIMT_Encode4(524117), // Rule ID 2727 //
        GIM_CheckComplexPattern, /*MI*/0, /*Op*/2, /*Renderer*/GIMT_Encode2(0), GIMT_Encode2(GICP_gi_smrd_buffer_imm),
        // (SIsbuffer_load:{ *:[v8f32] } v4i32:{ *:[v4i32] }:$sbase, (SMRDBufferImm:{ *:[i32] } i32:{ *:[i32] }:$offset), (timm:{ *:[i32] }):$cachepolicy)  =>  (S_BUFFER_LOAD_DWORDX8_IMM:{ *:[v8f32] } SReg_128:{ *:[v4i32] }:$sbase, i32imm:{ *:[i32] }:$offset, (extract_cpol:{ *:[i32] } ?:{ *:[i32] }:$cachepolicy))
        GIR_BuildMI, /*InsnID*/0, /*Opcode*/GIMT_Encode2(AMDGPU::S_BUFFER_LOAD_DWORDX8_IMM),
        GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/0, // DstI[sdst]
        GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/1, // sbase
        GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/0, // offset
        GIR_CustomOperandRenderer, /*InsnID*/0, /*OldInsnID*/0, /*OpIdx*/3, /*OperandRenderer*/GIMT_Encode2(GICR_renderExtractCPol), // cachepolicy
        GIR_MergeMemOperands, /*InsnID*/0, /*NumInsns*/1, /*MergeInsnID's*/0,
        GIR_ConstrainSelectedInstOperands, /*InsnID*/0,
        GIR_EraseFromParent, /*InsnID*/0,
        // GIR_Coverage, 2727,
        GIR_Done,
      // Label 7176: @524117
      GIM_Try, /*On fail goto*//*Label 7177*/ GIMT_Encode4(524164), // Rule ID 2699 //
        GIM_CheckFeatures, GIMT_Encode2(GIFBS_isGFX7Only),
        GIM_CheckComplexPattern, /*MI*/0, /*Op*/2, /*Renderer*/GIMT_Encode2(0), GIMT_Encode2(GICP_gi_smrd_buffer_imm32),
        // (SIsbuffer_load:{ *:[v8i32] } v4i32:{ *:[v4i32] }:$sbase, (SMRDBufferImm32:{ *:[i32] } i32:{ *:[i32] }:$offset), (timm:{ *:[i32] }):$cachepolicy)  =>  (S_BUFFER_LOAD_DWORDX8_IMM_ci:{ *:[v8i32] } SReg_128:{ *:[v4i32] }:$sbase, smrd_literal_offset:{ *:[i32] }:$offset, (extract_cpol:{ *:[i32] } ?:{ *:[i32] }:$cachepolicy))
        GIR_BuildMI, /*InsnID*/0, /*Opcode*/GIMT_Encode2(AMDGPU::S_BUFFER_LOAD_DWORDX8_IMM_ci),
        GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/0, // DstI[sdst]
        GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/1, // sbase
        GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/0, // offset
        GIR_CustomOperandRenderer, /*InsnID*/0, /*OldInsnID*/0, /*OpIdx*/3, /*OperandRenderer*/GIMT_Encode2(GICR_renderExtractCPol), // cachepolicy
        GIR_MergeMemOperands, /*InsnID*/0, /*NumInsns*/1, /*MergeInsnID's*/0,
        GIR_ConstrainSelectedInstOperands, /*InsnID*/0,
        GIR_EraseFromParent, /*InsnID*/0,
        // GIR_Coverage, 2699,
        GIR_Done,
      // Label 7177: @524164
      GIM_Try, /*On fail goto*//*Label 7178*/ GIMT_Encode4(524211), // Rule ID 2728 //
        GIM_CheckFeatures, GIMT_Encode2(GIFBS_isGFX7Only),
        GIM_CheckComplexPattern, /*MI*/0, /*Op*/2, /*Renderer*/GIMT_Encode2(0), GIMT_Encode2(GICP_gi_smrd_buffer_imm32),
        // (SIsbuffer_load:{ *:[v8f32] } v4i32:{ *:[v4i32] }:$sbase, (SMRDBufferImm32:{ *:[i32] } i32:{ *:[i32] }:$offset), (timm:{ *:[i32] }):$cachepolicy)  =>  (S_BUFFER_LOAD_DWORDX8_IMM_ci:{ *:[v8f32] } SReg_128:{ *:[v4i32] }:$sbase, smrd_literal_offset:{ *:[i32] }:$offset, (extract_cpol:{ *:[i32] } ?:{ *:[i32] }:$cachepolicy))
        GIR_BuildMI, /*InsnID*/0, /*Opcode*/GIMT_Encode2(AMDGPU::S_BUFFER_LOAD_DWORDX8_IMM_ci),
        GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/0, // DstI[sdst]
        GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/1, // sbase
        GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/0, // offset
        GIR_CustomOperandRenderer, /*InsnID*/0, /*OldInsnID*/0, /*OpIdx*/3, /*OperandRenderer*/GIMT_Encode2(GICR_renderExtractCPol), // cachepolicy
        GIR_MergeMemOperands, /*InsnID*/0, /*NumInsns*/1, /*MergeInsnID's*/0,
        GIR_ConstrainSelectedInstOperands, /*InsnID*/0,
        GIR_EraseFromParent, /*InsnID*/0,
        // GIR_Coverage, 2728,
        GIR_Done,
      // Label 7178: @524211
      GIM_Try, /*On fail goto*//*Label 7179*/ GIMT_Encode4(524250), // Rule ID 2700 //
        GIM_CheckFeatures, GIMT_Encode2(GIFBS_isNotGFX9Plus),
        // (SIsbuffer_load:{ *:[v8i32] } v4i32:{ *:[v4i32] }:$sbase, i32:{ *:[i32] }:$soffset, (timm:{ *:[i32] }):$cachepolicy)  =>  (S_BUFFER_LOAD_DWORDX8_SGPR:{ *:[v8i32] } SReg_128:{ *:[v4i32] }:$sbase, SReg_32:{ *:[i32] }:$soffset, (extract_cpol:{ *:[i32] } ?:{ *:[i32] }:$cachepolicy))
        GIR_BuildMI, /*InsnID*/0, /*Opcode*/GIMT_Encode2(AMDGPU::S_BUFFER_LOAD_DWORDX8_SGPR),
        GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/0, // DstI[sdst]
        GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/1, // sbase
        GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/2, // soffset
        GIR_CustomOperandRenderer, /*InsnID*/0, /*OldInsnID*/0, /*OpIdx*/3, /*OperandRenderer*/GIMT_Encode2(GICR_renderExtractCPol), // cachepolicy
        GIR_MergeMemOperands, /*InsnID*/0, /*NumInsns*/1, /*MergeInsnID's*/0,
        GIR_ConstrainSelectedInstOperands, /*InsnID*/0,
        GIR_EraseFromParent, /*InsnID*/0,
        // GIR_Coverage, 2700,
        GIR_Done,
      // Label 7179: @524250
      GIM_Try, /*On fail goto*//*Label 7180*/ GIMT_Encode4(524292), // Rule ID 2701 //
        GIM_CheckFeatures, GIMT_Encode2(GIFBS_isGFX9Plus),
        // (SIsbuffer_load:{ *:[v8i32] } v4i32:{ *:[v4i32] }:$sbase, i32:{ *:[i32] }:$soffset, (timm:{ *:[i32] }):$cachepolicy)  =>  (S_BUFFER_LOAD_DWORDX8_SGPR_IMM:{ *:[v8i32] } SReg_128:{ *:[v4i32] }:$sbase, SReg_32:{ *:[i32] }:$soffset, 0:{ *:[i32] }, (extract_cpol:{ *:[i32] } ?:{ *:[i32] }:$cachepolicy))
        GIR_BuildMI, /*InsnID*/0, /*Opcode*/GIMT_Encode2(AMDGPU::S_BUFFER_LOAD_DWORDX8_SGPR_IMM),
        GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/0, // DstI[sdst]
        GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/1, // sbase
        GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/2, // soffset
        GIR_AddImm8, /*InsnID*/0, /*Imm*/0,
        GIR_CustomOperandRenderer, /*InsnID*/0, /*OldInsnID*/0, /*OpIdx*/3, /*OperandRenderer*/GIMT_Encode2(GICR_renderExtractCPol), // cachepolicy
        GIR_MergeMemOperands, /*InsnID*/0, /*NumInsns*/1, /*MergeInsnID's*/0,
        GIR_ConstrainSelectedInstOperands, /*InsnID*/0,
        GIR_EraseFromParent, /*InsnID*/0,
        // GIR_Coverage, 2701,
        GIR_Done,
      // Label 7180: @524292
      GIM_Try, /*On fail goto*//*Label 7181*/ GIMT_Encode4(524331), // Rule ID 2729 //
        GIM_CheckFeatures, GIMT_Encode2(GIFBS_isNotGFX9Plus),
        // (SIsbuffer_load:{ *:[v8f32] } v4i32:{ *:[v4i32] }:$sbase, i32:{ *:[i32] }:$soffset, (timm:{ *:[i32] }):$cachepolicy)  =>  (S_BUFFER_LOAD_DWORDX8_SGPR:{ *:[v8f32] } SReg_128:{ *:[v4i32] }:$sbase, SReg_32:{ *:[i32] }:$soffset, (extract_cpol:{ *:[i32] } ?:{ *:[i32] }:$cachepolicy))
        GIR_BuildMI, /*InsnID*/0, /*Opcode*/GIMT_Encode2(AMDGPU::S_BUFFER_LOAD_DWORDX8_SGPR),
        GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/0, // DstI[sdst]
        GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/1, // sbase
        GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/2, // soffset
        GIR_CustomOperandRenderer, /*InsnID*/0, /*OldInsnID*/0, /*OpIdx*/3, /*OperandRenderer*/GIMT_Encode2(GICR_renderExtractCPol), // cachepolicy
        GIR_MergeMemOperands, /*InsnID*/0, /*NumInsns*/1, /*MergeInsnID's*/0,
        GIR_ConstrainSelectedInstOperands, /*InsnID*/0,
        GIR_EraseFromParent, /*InsnID*/0,
        // GIR_Coverage, 2729,
        GIR_Done,
      // Label 7181: @524331
      GIM_Try, /*On fail goto*//*Label 7182*/ GIMT_Encode4(524373), // Rule ID 2730 //
        GIM_CheckFeatures, GIMT_Encode2(GIFBS_isGFX9Plus),
        // (SIsbuffer_load:{ *:[v8f32] } v4i32:{ *:[v4i32] }:$sbase, i32:{ *:[i32] }:$soffset, (timm:{ *:[i32] }):$cachepolicy)  =>  (S_BUFFER_LOAD_DWORDX8_SGPR_IMM:{ *:[v8f32] } SReg_128:{ *:[v4i32] }:$sbase, SReg_32:{ *:[i32] }:$soffset, 0:{ *:[i32] }, (extract_cpol:{ *:[i32] } ?:{ *:[i32] }:$cachepolicy))
        GIR_BuildMI, /*InsnID*/0, /*Opcode*/GIMT_Encode2(AMDGPU::S_BUFFER_LOAD_DWORDX8_SGPR_IMM),
        GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/0, // DstI[sdst]
        GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/1, // sbase
        GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/2, // soffset
        GIR_AddImm8, /*InsnID*/0, /*Imm*/0,
        GIR_CustomOperandRenderer, /*InsnID*/0, /*OldInsnID*/0, /*OpIdx*/3, /*OperandRenderer*/GIMT_Encode2(GICR_renderExtractCPol), // cachepolicy
        GIR_MergeMemOperands, /*InsnID*/0, /*NumInsns*/1, /*MergeInsnID's*/0,
        GIR_ConstrainSelectedInstOperands, /*InsnID*/0,
        GIR_EraseFromParent, /*InsnID*/0,
        // GIR_Coverage, 2730,
        GIR_Done,
      // Label 7182: @524373
      GIM_Reject,
    // Label 7172: @524374
    GIM_Reject,
    // Label 7128: @524375
    GIM_Try, /*On fail goto*//*Label 7183*/ GIMT_Encode4(524845),
      GIM_CheckType, /*MI*/0, /*Op*/1, /*Type*/GILLT_v4s32,
      GIM_CheckType, /*MI*/0, /*Op*/2, /*Type*/GILLT_s32,
      GIM_CheckRegBankForClass, /*MI*/0, /*Op*/0, /*RC*/GIMT_Encode2(AMDGPU::SReg_512RegClassID),
      GIM_CheckIsImm, /*MI*/0, /*Op*/3,
      GIM_Try, /*On fail goto*//*Label 7184*/ GIMT_Encode4(524448), // Rule ID 2707 //
        GIM_CheckFeatures, GIMT_Encode2(GIFBS_isGFX9Plus),
        GIM_CheckComplexPattern, /*MI*/0, /*Op*/2, /*Renderer*/GIMT_Encode2(0), GIMT_Encode2(GICP_gi_smrd_buffer_sgpr_imm),
        // (SIsbuffer_load:{ *:[v16i32] } v4i32:{ *:[v4i32] }:$sbase, (SMRDBufferSgprImm:{ *:[i32] } i32:{ *:[i32] }:$soffset, i32:{ *:[i32] }:$offset), (timm:{ *:[i32] }):$cachepolicy)  =>  (S_BUFFER_LOAD_DWORDX16_SGPR_IMM:{ *:[v16i32] } SReg_128:{ *:[v4i32] }:$sbase, SReg_32:{ *:[i32] }:$soffset, i32imm:{ *:[i32] }:$offset, (extract_cpol:{ *:[i32] } ?:{ *:[i32] }:$cachepolicy))
        GIR_BuildMI, /*InsnID*/0, /*Opcode*/GIMT_Encode2(AMDGPU::S_BUFFER_LOAD_DWORDX16_SGPR_IMM),
        GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/0, // DstI[sdst]
        GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/1, // sbase
        GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/0, // soffset
        GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/1, // offset
        GIR_CustomOperandRenderer, /*InsnID*/0, /*OldInsnID*/0, /*OpIdx*/3, /*OperandRenderer*/GIMT_Encode2(GICR_renderExtractCPol), // cachepolicy
        GIR_MergeMemOperands, /*InsnID*/0, /*NumInsns*/1, /*MergeInsnID's*/0,
        GIR_ConstrainSelectedInstOperands, /*InsnID*/0,
        GIR_EraseFromParent, /*InsnID*/0,
        // GIR_Coverage, 2707,
        GIR_Done,
      // Label 7184: @524448
      GIM_Try, /*On fail goto*//*Label 7185*/ GIMT_Encode4(524500), // Rule ID 2736 //
        GIM_CheckFeatures, GIMT_Encode2(GIFBS_isGFX9Plus),
        GIM_CheckComplexPattern, /*MI*/0, /*Op*/2, /*Renderer*/GIMT_Encode2(0), GIMT_Encode2(GICP_gi_smrd_buffer_sgpr_imm),
        // (SIsbuffer_load:{ *:[v16f32] } v4i32:{ *:[v4i32] }:$sbase, (SMRDBufferSgprImm:{ *:[i32] } i32:{ *:[i32] }:$soffset, i32:{ *:[i32] }:$offset), (timm:{ *:[i32] }):$cachepolicy)  =>  (S_BUFFER_LOAD_DWORDX16_SGPR_IMM:{ *:[v16f32] } SReg_128:{ *:[v4i32] }:$sbase, SReg_32:{ *:[i32] }:$soffset, i32imm:{ *:[i32] }:$offset, (extract_cpol:{ *:[i32] } ?:{ *:[i32] }:$cachepolicy))
        GIR_BuildMI, /*InsnID*/0, /*Opcode*/GIMT_Encode2(AMDGPU::S_BUFFER_LOAD_DWORDX16_SGPR_IMM),
        GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/0, // DstI[sdst]
        GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/1, // sbase
        GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/0, // soffset
        GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/1, // offset
        GIR_CustomOperandRenderer, /*InsnID*/0, /*OldInsnID*/0, /*OpIdx*/3, /*OperandRenderer*/GIMT_Encode2(GICR_renderExtractCPol), // cachepolicy
        GIR_MergeMemOperands, /*InsnID*/0, /*NumInsns*/1, /*MergeInsnID's*/0,
        GIR_ConstrainSelectedInstOperands, /*InsnID*/0,
        GIR_EraseFromParent, /*InsnID*/0,
        // GIR_Coverage, 2736,
        GIR_Done,
      // Label 7185: @524500
      GIM_Try, /*On fail goto*//*Label 7186*/ GIMT_Encode4(524544), // Rule ID 2703 //
        GIM_CheckComplexPattern, /*MI*/0, /*Op*/2, /*Renderer*/GIMT_Encode2(0), GIMT_Encode2(GICP_gi_smrd_buffer_imm),
        // (SIsbuffer_load:{ *:[v16i32] } v4i32:{ *:[v4i32] }:$sbase, (SMRDBufferImm:{ *:[i32] } i32:{ *:[i32] }:$offset), (timm:{ *:[i32] }):$cachepolicy)  =>  (S_BUFFER_LOAD_DWORDX16_IMM:{ *:[v16i32] } SReg_128:{ *:[v4i32] }:$sbase, i32imm:{ *:[i32] }:$offset, (extract_cpol:{ *:[i32] } ?:{ *:[i32] }:$cachepolicy))
        GIR_BuildMI, /*InsnID*/0, /*Opcode*/GIMT_Encode2(AMDGPU::S_BUFFER_LOAD_DWORDX16_IMM),
        GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/0, // DstI[sdst]
        GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/1, // sbase
        GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/0, // offset
        GIR_CustomOperandRenderer, /*InsnID*/0, /*OldInsnID*/0, /*OpIdx*/3, /*OperandRenderer*/GIMT_Encode2(GICR_renderExtractCPol), // cachepolicy
        GIR_MergeMemOperands, /*InsnID*/0, /*NumInsns*/1, /*MergeInsnID's*/0,
        GIR_ConstrainSelectedInstOperands, /*InsnID*/0,
        GIR_EraseFromParent, /*InsnID*/0,
        // GIR_Coverage, 2703,
        GIR_Done,
      // Label 7186: @524544
      GIM_Try, /*On fail goto*//*Label 7187*/ GIMT_Encode4(524588), // Rule ID 2732 //
        GIM_CheckComplexPattern, /*MI*/0, /*Op*/2, /*Renderer*/GIMT_Encode2(0), GIMT_Encode2(GICP_gi_smrd_buffer_imm),
        // (SIsbuffer_load:{ *:[v16f32] } v4i32:{ *:[v4i32] }:$sbase, (SMRDBufferImm:{ *:[i32] } i32:{ *:[i32] }:$offset), (timm:{ *:[i32] }):$cachepolicy)  =>  (S_BUFFER_LOAD_DWORDX16_IMM:{ *:[v16f32] } SReg_128:{ *:[v4i32] }:$sbase, i32imm:{ *:[i32] }:$offset, (extract_cpol:{ *:[i32] } ?:{ *:[i32] }:$cachepolicy))
        GIR_BuildMI, /*InsnID*/0, /*Opcode*/GIMT_Encode2(AMDGPU::S_BUFFER_LOAD_DWORDX16_IMM),
        GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/0, // DstI[sdst]
        GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/1, // sbase
        GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/0, // offset
        GIR_CustomOperandRenderer, /*InsnID*/0, /*OldInsnID*/0, /*OpIdx*/3, /*OperandRenderer*/GIMT_Encode2(GICR_renderExtractCPol), // cachepolicy
        GIR_MergeMemOperands, /*InsnID*/0, /*NumInsns*/1, /*MergeInsnID's*/0,
        GIR_ConstrainSelectedInstOperands, /*InsnID*/0,
        GIR_EraseFromParent, /*InsnID*/0,
        // GIR_Coverage, 2732,
        GIR_Done,
      // Label 7187: @524588
      GIM_Try, /*On fail goto*//*Label 7188*/ GIMT_Encode4(524635), // Rule ID 2704 //
        GIM_CheckFeatures, GIMT_Encode2(GIFBS_isGFX7Only),
        GIM_CheckComplexPattern, /*MI*/0, /*Op*/2, /*Renderer*/GIMT_Encode2(0), GIMT_Encode2(GICP_gi_smrd_buffer_imm32),
        // (SIsbuffer_load:{ *:[v16i32] } v4i32:{ *:[v4i32] }:$sbase, (SMRDBufferImm32:{ *:[i32] } i32:{ *:[i32] }:$offset), (timm:{ *:[i32] }):$cachepolicy)  =>  (S_BUFFER_LOAD_DWORDX16_IMM_ci:{ *:[v16i32] } SReg_128:{ *:[v4i32] }:$sbase, smrd_literal_offset:{ *:[i32] }:$offset, (extract_cpol:{ *:[i32] } ?:{ *:[i32] }:$cachepolicy))
        GIR_BuildMI, /*InsnID*/0, /*Opcode*/GIMT_Encode2(AMDGPU::S_BUFFER_LOAD_DWORDX16_IMM_ci),
        GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/0, // DstI[sdst]
        GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/1, // sbase
        GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/0, // offset
        GIR_CustomOperandRenderer, /*InsnID*/0, /*OldInsnID*/0, /*OpIdx*/3, /*OperandRenderer*/GIMT_Encode2(GICR_renderExtractCPol), // cachepolicy
        GIR_MergeMemOperands, /*InsnID*/0, /*NumInsns*/1, /*MergeInsnID's*/0,
        GIR_ConstrainSelectedInstOperands, /*InsnID*/0,
        GIR_EraseFromParent, /*InsnID*/0,
        // GIR_Coverage, 2704,
        GIR_Done,
      // Label 7188: @524635
      GIM_Try, /*On fail goto*//*Label 7189*/ GIMT_Encode4(524682), // Rule ID 2733 //
        GIM_CheckFeatures, GIMT_Encode2(GIFBS_isGFX7Only),
        GIM_CheckComplexPattern, /*MI*/0, /*Op*/2, /*Renderer*/GIMT_Encode2(0), GIMT_Encode2(GICP_gi_smrd_buffer_imm32),
        // (SIsbuffer_load:{ *:[v16f32] } v4i32:{ *:[v4i32] }:$sbase, (SMRDBufferImm32:{ *:[i32] } i32:{ *:[i32] }:$offset), (timm:{ *:[i32] }):$cachepolicy)  =>  (S_BUFFER_LOAD_DWORDX16_IMM_ci:{ *:[v16f32] } SReg_128:{ *:[v4i32] }:$sbase, smrd_literal_offset:{ *:[i32] }:$offset, (extract_cpol:{ *:[i32] } ?:{ *:[i32] }:$cachepolicy))
        GIR_BuildMI, /*InsnID*/0, /*Opcode*/GIMT_Encode2(AMDGPU::S_BUFFER_LOAD_DWORDX16_IMM_ci),
        GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/0, // DstI[sdst]
        GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/1, // sbase
        GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/0, // offset
        GIR_CustomOperandRenderer, /*InsnID*/0, /*OldInsnID*/0, /*OpIdx*/3, /*OperandRenderer*/GIMT_Encode2(GICR_renderExtractCPol), // cachepolicy
        GIR_MergeMemOperands, /*InsnID*/0, /*NumInsns*/1, /*MergeInsnID's*/0,
        GIR_ConstrainSelectedInstOperands, /*InsnID*/0,
        GIR_EraseFromParent, /*InsnID*/0,
        // GIR_Coverage, 2733,
        GIR_Done,
      // Label 7189: @524682
      GIM_Try, /*On fail goto*//*Label 7190*/ GIMT_Encode4(524721), // Rule ID 2705 //
        GIM_CheckFeatures, GIMT_Encode2(GIFBS_isNotGFX9Plus),
        // (SIsbuffer_load:{ *:[v16i32] } v4i32:{ *:[v4i32] }:$sbase, i32:{ *:[i32] }:$soffset, (timm:{ *:[i32] }):$cachepolicy)  =>  (S_BUFFER_LOAD_DWORDX16_SGPR:{ *:[v16i32] } SReg_128:{ *:[v4i32] }:$sbase, SReg_32:{ *:[i32] }:$soffset, (extract_cpol:{ *:[i32] } ?:{ *:[i32] }:$cachepolicy))
        GIR_BuildMI, /*InsnID*/0, /*Opcode*/GIMT_Encode2(AMDGPU::S_BUFFER_LOAD_DWORDX16_SGPR),
        GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/0, // DstI[sdst]
        GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/1, // sbase
        GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/2, // soffset
        GIR_CustomOperandRenderer, /*InsnID*/0, /*OldInsnID*/0, /*OpIdx*/3, /*OperandRenderer*/GIMT_Encode2(GICR_renderExtractCPol), // cachepolicy
        GIR_MergeMemOperands, /*InsnID*/0, /*NumInsns*/1, /*MergeInsnID's*/0,
        GIR_ConstrainSelectedInstOperands, /*InsnID*/0,
        GIR_EraseFromParent, /*InsnID*/0,
        // GIR_Coverage, 2705,
        GIR_Done,
      // Label 7190: @524721
      GIM_Try, /*On fail goto*//*Label 7191*/ GIMT_Encode4(524763), // Rule ID 2706 //
        GIM_CheckFeatures, GIMT_Encode2(GIFBS_isGFX9Plus),
        // (SIsbuffer_load:{ *:[v16i32] } v4i32:{ *:[v4i32] }:$sbase, i32:{ *:[i32] }:$soffset, (timm:{ *:[i32] }):$cachepolicy)  =>  (S_BUFFER_LOAD_DWORDX16_SGPR_IMM:{ *:[v16i32] } SReg_128:{ *:[v4i32] }:$sbase, SReg_32:{ *:[i32] }:$soffset, 0:{ *:[i32] }, (extract_cpol:{ *:[i32] } ?:{ *:[i32] }:$cachepolicy))
        GIR_BuildMI, /*InsnID*/0, /*Opcode*/GIMT_Encode2(AMDGPU::S_BUFFER_LOAD_DWORDX16_SGPR_IMM),
        GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/0, // DstI[sdst]
        GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/1, // sbase
        GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/2, // soffset
        GIR_AddImm8, /*InsnID*/0, /*Imm*/0,
        GIR_CustomOperandRenderer, /*InsnID*/0, /*OldInsnID*/0, /*OpIdx*/3, /*OperandRenderer*/GIMT_Encode2(GICR_renderExtractCPol), // cachepolicy
        GIR_MergeMemOperands, /*InsnID*/0, /*NumInsns*/1, /*MergeInsnID's*/0,
        GIR_ConstrainSelectedInstOperands, /*InsnID*/0,
        GIR_EraseFromParent, /*InsnID*/0,
        // GIR_Coverage, 2706,
        GIR_Done,
      // Label 7191: @524763
      GIM_Try, /*On fail goto*//*Label 7192*/ GIMT_Encode4(524802), // Rule ID 2734 //
        GIM_CheckFeatures, GIMT_Encode2(GIFBS_isNotGFX9Plus),
        // (SIsbuffer_load:{ *:[v16f32] } v4i32:{ *:[v4i32] }:$sbase, i32:{ *:[i32] }:$soffset, (timm:{ *:[i32] }):$cachepolicy)  =>  (S_BUFFER_LOAD_DWORDX16_SGPR:{ *:[v16f32] } SReg_128:{ *:[v4i32] }:$sbase, SReg_32:{ *:[i32] }:$soffset, (extract_cpol:{ *:[i32] } ?:{ *:[i32] }:$cachepolicy))
        GIR_BuildMI, /*InsnID*/0, /*Opcode*/GIMT_Encode2(AMDGPU::S_BUFFER_LOAD_DWORDX16_SGPR),
        GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/0, // DstI[sdst]
        GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/1, // sbase
        GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/2, // soffset
        GIR_CustomOperandRenderer, /*InsnID*/0, /*OldInsnID*/0, /*OpIdx*/3, /*OperandRenderer*/GIMT_Encode2(GICR_renderExtractCPol), // cachepolicy
        GIR_MergeMemOperands, /*InsnID*/0, /*NumInsns*/1, /*MergeInsnID's*/0,
        GIR_ConstrainSelectedInstOperands, /*InsnID*/0,
        GIR_EraseFromParent, /*InsnID*/0,
        // GIR_Coverage, 2734,
        GIR_Done,
      // Label 7192: @524802
      GIM_Try, /*On fail goto*//*Label 7193*/ GIMT_Encode4(524844), // Rule ID 2735 //
        GIM_CheckFeatures, GIMT_Encode2(GIFBS_isGFX9Plus),
        // (SIsbuffer_load:{ *:[v16f32] } v4i32:{ *:[v4i32] }:$sbase, i32:{ *:[i32] }:$soffset, (timm:{ *:[i32] }):$cachepolicy)  =>  (S_BUFFER_LOAD_DWORDX16_SGPR_IMM:{ *:[v16f32] } SReg_128:{ *:[v4i32] }:$sbase, SReg_32:{ *:[i32] }:$soffset, 0:{ *:[i32] }, (extract_cpol:{ *:[i32] } ?:{ *:[i32] }:$cachepolicy))
        GIR_BuildMI, /*InsnID*/0, /*Opcode*/GIMT_Encode2(AMDGPU::S_BUFFER_LOAD_DWORDX16_SGPR_IMM),
        GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/0, // DstI[sdst]
        GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/1, // sbase
        GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/2, // soffset
        GIR_AddImm8, /*InsnID*/0, /*Imm*/0,
        GIR_CustomOperandRenderer, /*InsnID*/0, /*OldInsnID*/0, /*OpIdx*/3, /*OperandRenderer*/GIMT_Encode2(GICR_renderExtractCPol), // cachepolicy
        GIR_MergeMemOperands, /*InsnID*/0, /*NumInsns*/1, /*MergeInsnID's*/0,
        GIR_ConstrainSelectedInstOperands, /*InsnID*/0,
        GIR_EraseFromParent, /*InsnID*/0,
        // GIR_Coverage, 2735,
        GIR_Done,
      // Label 7193: @524844
      GIM_Reject,
    // Label 7183: @524845
    GIM_Reject,
    // Label 7129: @524846
    GIM_Reject,
    // Label 151: @524847
    GIM_Try, /*On fail goto*//*Label 7194*/ GIMT_Encode4(525014),
      GIM_CheckType, /*MI*/0, /*Op*/0, /*Type*/GILLT_s32,
      GIM_CheckType, /*MI*/0, /*Op*/1, /*Type*/GILLT_v4s32,
      GIM_CheckType, /*MI*/0, /*Op*/2, /*Type*/GILLT_s32,
      GIM_CheckRegBankForClass, /*MI*/0, /*Op*/0, /*RC*/GIMT_Encode2(AMDGPU::SReg_32_XM0_XEXECRegClassID),
      GIM_CheckIsImm, /*MI*/0, /*Op*/3,
      GIM_Try, /*On fail goto*//*Label 7195*/ GIMT_Encode4(524924), // Rule ID 2422 //
        GIM_CheckFeatures, GIMT_Encode2(GIFBS_isGFX12Plus),
        GIM_CheckComplexPattern, /*MI*/0, /*Op*/2, /*Renderer*/GIMT_Encode2(0), GIMT_Encode2(GICP_gi_smrd_buffer_sgpr_imm),
        // (SIsbuffer_load_byte:{ *:[i32] } v4i32:{ *:[v4i32] }:$sbase, (SMRDBufferSgprImm:{ *:[i32] } i32:{ *:[i32] }:$soffset, i32:{ *:[i32] }:$offset), (timm:{ *:[i32] }):$cachepolicy)  =>  (S_BUFFER_LOAD_I8_SGPR_IMM:{ *:[i32] } SReg_128:{ *:[v4i32] }:$sbase, SReg_32:{ *:[i32] }:$soffset, i32imm:{ *:[i32] }:$offset, (extract_cpol:{ *:[i32] } ?:{ *:[i32] }:$cachepolicy))
        GIR_BuildMI, /*InsnID*/0, /*Opcode*/GIMT_Encode2(AMDGPU::S_BUFFER_LOAD_I8_SGPR_IMM),
        GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/0, // DstI[sdst]
        GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/1, // sbase
        GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/0, // soffset
        GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/1, // offset
        GIR_CustomOperandRenderer, /*InsnID*/0, /*OldInsnID*/0, /*OpIdx*/3, /*OperandRenderer*/GIMT_Encode2(GICR_renderExtractCPol), // cachepolicy
        GIR_MergeMemOperands, /*InsnID*/0, /*NumInsns*/1, /*MergeInsnID's*/0,
        GIR_ConstrainSelectedInstOperands, /*InsnID*/0,
        GIR_EraseFromParent, /*InsnID*/0,
        // GIR_Coverage, 2422,
        GIR_Done,
      // Label 7195: @524924
      GIM_Try, /*On fail goto*//*Label 7196*/ GIMT_Encode4(524971), // Rule ID 2420 //
        GIM_CheckFeatures, GIMT_Encode2(GIFBS_isGFX12Plus),
        GIM_CheckComplexPattern, /*MI*/0, /*Op*/2, /*Renderer*/GIMT_Encode2(0), GIMT_Encode2(GICP_gi_smrd_buffer_imm),
        // (SIsbuffer_load_byte:{ *:[i32] } v4i32:{ *:[v4i32] }:$sbase, (SMRDBufferImm:{ *:[i32] } i32:{ *:[i32] }:$offset), (timm:{ *:[i32] }):$cachepolicy)  =>  (S_BUFFER_LOAD_I8_IMM:{ *:[i32] } SReg_128:{ *:[v4i32] }:$sbase, i32imm:{ *:[i32] }:$offset, (extract_cpol:{ *:[i32] } ?:{ *:[i32] }:$cachepolicy))
        GIR_BuildMI, /*InsnID*/0, /*Opcode*/GIMT_Encode2(AMDGPU::S_BUFFER_LOAD_I8_IMM),
        GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/0, // DstI[sdst]
        GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/1, // sbase
        GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/0, // offset
        GIR_CustomOperandRenderer, /*InsnID*/0, /*OldInsnID*/0, /*OpIdx*/3, /*OperandRenderer*/GIMT_Encode2(GICR_renderExtractCPol), // cachepolicy
        GIR_MergeMemOperands, /*InsnID*/0, /*NumInsns*/1, /*MergeInsnID's*/0,
        GIR_ConstrainSelectedInstOperands, /*InsnID*/0,
        GIR_EraseFromParent, /*InsnID*/0,
        // GIR_Coverage, 2420,
        GIR_Done,
      // Label 7196: @524971
      GIM_Try, /*On fail goto*//*Label 7197*/ GIMT_Encode4(525013), // Rule ID 2421 //
        GIM_CheckFeatures, GIMT_Encode2(GIFBS_isGFX12Plus),
        // (SIsbuffer_load_byte:{ *:[i32] } v4i32:{ *:[v4i32] }:$sbase, i32:{ *:[i32] }:$soffset, (timm:{ *:[i32] }):$cachepolicy)  =>  (S_BUFFER_LOAD_I8_SGPR_IMM:{ *:[i32] } SReg_128:{ *:[v4i32] }:$sbase, SReg_32:{ *:[i32] }:$soffset, 0:{ *:[i32] }, (extract_cpol:{ *:[i32] } ?:{ *:[i32] }:$cachepolicy))
        GIR_BuildMI, /*InsnID*/0, /*Opcode*/GIMT_Encode2(AMDGPU::S_BUFFER_LOAD_I8_SGPR_IMM),
        GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/0, // DstI[sdst]
        GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/1, // sbase
        GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/2, // soffset
        GIR_AddImm8, /*InsnID*/0, /*Imm*/0,
        GIR_CustomOperandRenderer, /*InsnID*/0, /*OldInsnID*/0, /*OpIdx*/3, /*OperandRenderer*/GIMT_Encode2(GICR_renderExtractCPol), // cachepolicy
        GIR_MergeMemOperands, /*InsnID*/0, /*NumInsns*/1, /*MergeInsnID's*/0,
        GIR_ConstrainSelectedInstOperands, /*InsnID*/0,
        GIR_EraseFromParent, /*InsnID*/0,
        // GIR_Coverage, 2421,
        GIR_Done,
      // Label 7197: @525013
      GIM_Reject,
    // Label 7194: @525014
    GIM_Reject,
    // Label 152: @525015
    GIM_Try, /*On fail goto*//*Label 7198*/ GIMT_Encode4(525182),
      GIM_CheckType, /*MI*/0, /*Op*/0, /*Type*/GILLT_s32,
      GIM_CheckType, /*MI*/0, /*Op*/1, /*Type*/GILLT_v4s32,
      GIM_CheckType, /*MI*/0, /*Op*/2, /*Type*/GILLT_s32,
      GIM_CheckRegBankForClass, /*MI*/0, /*Op*/0, /*RC*/GIMT_Encode2(AMDGPU::SReg_32_XM0_XEXECRegClassID),
      GIM_CheckIsImm, /*MI*/0, /*Op*/3,
      GIM_Try, /*On fail goto*//*Label 7199*/ GIMT_Encode4(525092), // Rule ID 2448 //
        GIM_CheckFeatures, GIMT_Encode2(GIFBS_isGFX12Plus),
        GIM_CheckComplexPattern, /*MI*/0, /*Op*/2, /*Renderer*/GIMT_Encode2(0), GIMT_Encode2(GICP_gi_smrd_buffer_sgpr_imm),
        // (SIsbuffer_load_short:{ *:[i32] } v4i32:{ *:[v4i32] }:$sbase, (SMRDBufferSgprImm:{ *:[i32] } i32:{ *:[i32] }:$soffset, i32:{ *:[i32] }:$offset), (timm:{ *:[i32] }):$cachepolicy)  =>  (S_BUFFER_LOAD_I16_SGPR_IMM:{ *:[i32] } SReg_128:{ *:[v4i32] }:$sbase, SReg_32:{ *:[i32] }:$soffset, i32imm:{ *:[i32] }:$offset, (extract_cpol:{ *:[i32] } ?:{ *:[i32] }:$cachepolicy))
        GIR_BuildMI, /*InsnID*/0, /*Opcode*/GIMT_Encode2(AMDGPU::S_BUFFER_LOAD_I16_SGPR_IMM),
        GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/0, // DstI[sdst]
        GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/1, // sbase
        GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/0, // soffset
        GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/1, // offset
        GIR_CustomOperandRenderer, /*InsnID*/0, /*OldInsnID*/0, /*OpIdx*/3, /*OperandRenderer*/GIMT_Encode2(GICR_renderExtractCPol), // cachepolicy
        GIR_MergeMemOperands, /*InsnID*/0, /*NumInsns*/1, /*MergeInsnID's*/0,
        GIR_ConstrainSelectedInstOperands, /*InsnID*/0,
        GIR_EraseFromParent, /*InsnID*/0,
        // GIR_Coverage, 2448,
        GIR_Done,
      // Label 7199: @525092
      GIM_Try, /*On fail goto*//*Label 7200*/ GIMT_Encode4(525139), // Rule ID 2446 //
        GIM_CheckFeatures, GIMT_Encode2(GIFBS_isGFX12Plus),
        GIM_CheckComplexPattern, /*MI*/0, /*Op*/2, /*Renderer*/GIMT_Encode2(0), GIMT_Encode2(GICP_gi_smrd_buffer_imm),
        // (SIsbuffer_load_short:{ *:[i32] } v4i32:{ *:[v4i32] }:$sbase, (SMRDBufferImm:{ *:[i32] } i32:{ *:[i32] }:$offset), (timm:{ *:[i32] }):$cachepolicy)  =>  (S_BUFFER_LOAD_I16_IMM:{ *:[i32] } SReg_128:{ *:[v4i32] }:$sbase, i32imm:{ *:[i32] }:$offset, (extract_cpol:{ *:[i32] } ?:{ *:[i32] }:$cachepolicy))
        GIR_BuildMI, /*InsnID*/0, /*Opcode*/GIMT_Encode2(AMDGPU::S_BUFFER_LOAD_I16_IMM),
        GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/0, // DstI[sdst]
        GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/1, // sbase
        GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/0, // offset
        GIR_CustomOperandRenderer, /*InsnID*/0, /*OldInsnID*/0, /*OpIdx*/3, /*OperandRenderer*/GIMT_Encode2(GICR_renderExtractCPol), // cachepolicy
        GIR_MergeMemOperands, /*InsnID*/0, /*NumInsns*/1, /*MergeInsnID's*/0,
        GIR_ConstrainSelectedInstOperands, /*InsnID*/0,
        GIR_EraseFromParent, /*InsnID*/0,
        // GIR_Coverage, 2446,
        GIR_Done,
      // Label 7200: @525139
      GIM_Try, /*On fail goto*//*Label 7201*/ GIMT_Encode4(525181), // Rule ID 2447 //
        GIM_CheckFeatures, GIMT_Encode2(GIFBS_isGFX12Plus),
        // (SIsbuffer_load_short:{ *:[i32] } v4i32:{ *:[v4i32] }:$sbase, i32:{ *:[i32] }:$soffset, (timm:{ *:[i32] }):$cachepolicy)  =>  (S_BUFFER_LOAD_I16_SGPR_IMM:{ *:[i32] } SReg_128:{ *:[v4i32] }:$sbase, SReg_32:{ *:[i32] }:$soffset, 0:{ *:[i32] }, (extract_cpol:{ *:[i32] } ?:{ *:[i32] }:$cachepolicy))
        GIR_BuildMI, /*InsnID*/0, /*Opcode*/GIMT_Encode2(AMDGPU::S_BUFFER_LOAD_I16_SGPR_IMM),
        GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/0, // DstI[sdst]
        GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/1, // sbase
        GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/2, // soffset
        GIR_AddImm8, /*InsnID*/0, /*Imm*/0,
        GIR_CustomOperandRenderer, /*InsnID*/0, /*OldInsnID*/0, /*OpIdx*/3, /*OperandRenderer*/GIMT_Encode2(GICR_renderExtractCPol), // cachepolicy
        GIR_MergeMemOperands, /*InsnID*/0, /*NumInsns*/1, /*MergeInsnID's*/0,
        GIR_ConstrainSelectedInstOperands, /*InsnID*/0,
        GIR_EraseFromParent, /*InsnID*/0,
        // GIR_Coverage, 2447,
        GIR_Done,
      // Label 7201: @525181
      GIM_Reject,
    // Label 7198: @525182
    GIM_Reject,
    // Label 153: @525183
    GIM_Try, /*On fail goto*//*Label 7202*/ GIMT_Encode4(525350),
      GIM_CheckType, /*MI*/0, /*Op*/0, /*Type*/GILLT_s32,
      GIM_CheckType, /*MI*/0, /*Op*/1, /*Type*/GILLT_v4s32,
      GIM_CheckType, /*MI*/0, /*Op*/2, /*Type*/GILLT_s32,
      GIM_CheckRegBankForClass, /*MI*/0, /*Op*/0, /*RC*/GIMT_Encode2(AMDGPU::SReg_32_XM0_XEXECRegClassID),
      GIM_CheckIsImm, /*MI*/0, /*Op*/3,
      GIM_Try, /*On fail goto*//*Label 7203*/ GIMT_Encode4(525260), // Rule ID 2445 //
        GIM_CheckFeatures, GIMT_Encode2(GIFBS_isGFX12Plus),
        GIM_CheckComplexPattern, /*MI*/0, /*Op*/2, /*Renderer*/GIMT_Encode2(0), GIMT_Encode2(GICP_gi_smrd_buffer_sgpr_imm),
        // (SIsbuffer_load_ubyte:{ *:[i32] } v4i32:{ *:[v4i32] }:$sbase, (SMRDBufferSgprImm:{ *:[i32] } i32:{ *:[i32] }:$soffset, i32:{ *:[i32] }:$offset), (timm:{ *:[i32] }):$cachepolicy)  =>  (S_BUFFER_LOAD_U8_SGPR_IMM:{ *:[i32] } SReg_128:{ *:[v4i32] }:$sbase, SReg_32:{ *:[i32] }:$soffset, i32imm:{ *:[i32] }:$offset, (extract_cpol:{ *:[i32] } ?:{ *:[i32] }:$cachepolicy))
        GIR_BuildMI, /*InsnID*/0, /*Opcode*/GIMT_Encode2(AMDGPU::S_BUFFER_LOAD_U8_SGPR_IMM),
        GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/0, // DstI[sdst]
        GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/1, // sbase
        GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/0, // soffset
        GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/1, // offset
        GIR_CustomOperandRenderer, /*InsnID*/0, /*OldInsnID*/0, /*OpIdx*/3, /*OperandRenderer*/GIMT_Encode2(GICR_renderExtractCPol), // cachepolicy
        GIR_MergeMemOperands, /*InsnID*/0, /*NumInsns*/1, /*MergeInsnID's*/0,
        GIR_ConstrainSelectedInstOperands, /*InsnID*/0,
        GIR_EraseFromParent, /*InsnID*/0,
        // GIR_Coverage, 2445,
        GIR_Done,
      // Label 7203: @525260
      GIM_Try, /*On fail goto*//*Label 7204*/ GIMT_Encode4(525307), // Rule ID 2443 //
        GIM_CheckFeatures, GIMT_Encode2(GIFBS_isGFX12Plus),
        GIM_CheckComplexPattern, /*MI*/0, /*Op*/2, /*Renderer*/GIMT_Encode2(0), GIMT_Encode2(GICP_gi_smrd_buffer_imm),
        // (SIsbuffer_load_ubyte:{ *:[i32] } v4i32:{ *:[v4i32] }:$sbase, (SMRDBufferImm:{ *:[i32] } i32:{ *:[i32] }:$offset), (timm:{ *:[i32] }):$cachepolicy)  =>  (S_BUFFER_LOAD_U8_IMM:{ *:[i32] } SReg_128:{ *:[v4i32] }:$sbase, i32imm:{ *:[i32] }:$offset, (extract_cpol:{ *:[i32] } ?:{ *:[i32] }:$cachepolicy))
        GIR_BuildMI, /*InsnID*/0, /*Opcode*/GIMT_Encode2(AMDGPU::S_BUFFER_LOAD_U8_IMM),
        GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/0, // DstI[sdst]
        GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/1, // sbase
        GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/0, // offset
        GIR_CustomOperandRenderer, /*InsnID*/0, /*OldInsnID*/0, /*OpIdx*/3, /*OperandRenderer*/GIMT_Encode2(GICR_renderExtractCPol), // cachepolicy
        GIR_MergeMemOperands, /*InsnID*/0, /*NumInsns*/1, /*MergeInsnID's*/0,
        GIR_ConstrainSelectedInstOperands, /*InsnID*/0,
        GIR_EraseFromParent, /*InsnID*/0,
        // GIR_Coverage, 2443,
        GIR_Done,
      // Label 7204: @525307
      GIM_Try, /*On fail goto*//*Label 7205*/ GIMT_Encode4(525349), // Rule ID 2444 //
        GIM_CheckFeatures, GIMT_Encode2(GIFBS_isGFX12Plus),
        // (SIsbuffer_load_ubyte:{ *:[i32] } v4i32:{ *:[v4i32] }:$sbase, i32:{ *:[i32] }:$soffset, (timm:{ *:[i32] }):$cachepolicy)  =>  (S_BUFFER_LOAD_U8_SGPR_IMM:{ *:[i32] } SReg_128:{ *:[v4i32] }:$sbase, SReg_32:{ *:[i32] }:$soffset, 0:{ *:[i32] }, (extract_cpol:{ *:[i32] } ?:{ *:[i32] }:$cachepolicy))
        GIR_BuildMI, /*InsnID*/0, /*Opcode*/GIMT_Encode2(AMDGPU::S_BUFFER_LOAD_U8_SGPR_IMM),
        GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/0, // DstI[sdst]
        GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/1, // sbase
        GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/2, // soffset
        GIR_AddImm8, /*InsnID*/0, /*Imm*/0,
        GIR_CustomOperandRenderer, /*InsnID*/0, /*OldInsnID*/0, /*OpIdx*/3, /*OperandRenderer*/GIMT_Encode2(GICR_renderExtractCPol), // cachepolicy
        GIR_MergeMemOperands, /*InsnID*/0, /*NumInsns*/1, /*MergeInsnID's*/0,
        GIR_ConstrainSelectedInstOperands, /*InsnID*/0,
        GIR_EraseFromParent, /*InsnID*/0,
        // GIR_Coverage, 2444,
        GIR_Done,
      // Label 7205: @525349
      GIM_Reject,
    // Label 7202: @525350
    GIM_Reject,
    // Label 154: @525351
    GIM_Try, /*On fail goto*//*Label 7206*/ GIMT_Encode4(525518),
      GIM_CheckType, /*MI*/0, /*Op*/0, /*Type*/GILLT_s32,
      GIM_CheckType, /*MI*/0, /*Op*/1, /*Type*/GILLT_v4s32,
      GIM_CheckType, /*MI*/0, /*Op*/2, /*Type*/GILLT_s32,
      GIM_CheckRegBankForClass, /*MI*/0, /*Op*/0, /*RC*/GIMT_Encode2(AMDGPU::SReg_32_XM0_XEXECRegClassID),
      GIM_CheckIsImm, /*MI*/0, /*Op*/3,
      GIM_Try, /*On fail goto*//*Label 7207*/ GIMT_Encode4(525428), // Rule ID 2451 //
        GIM_CheckFeatures, GIMT_Encode2(GIFBS_isGFX12Plus),
        GIM_CheckComplexPattern, /*MI*/0, /*Op*/2, /*Renderer*/GIMT_Encode2(0), GIMT_Encode2(GICP_gi_smrd_buffer_sgpr_imm),
        // (SIsbuffer_load_ushort:{ *:[i32] } v4i32:{ *:[v4i32] }:$sbase, (SMRDBufferSgprImm:{ *:[i32] } i32:{ *:[i32] }:$soffset, i32:{ *:[i32] }:$offset), (timm:{ *:[i32] }):$cachepolicy)  =>  (S_BUFFER_LOAD_U16_SGPR_IMM:{ *:[i32] } SReg_128:{ *:[v4i32] }:$sbase, SReg_32:{ *:[i32] }:$soffset, i32imm:{ *:[i32] }:$offset, (extract_cpol:{ *:[i32] } ?:{ *:[i32] }:$cachepolicy))
        GIR_BuildMI, /*InsnID*/0, /*Opcode*/GIMT_Encode2(AMDGPU::S_BUFFER_LOAD_U16_SGPR_IMM),
        GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/0, // DstI[sdst]
        GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/1, // sbase
        GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/0, // soffset
        GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/1, // offset
        GIR_CustomOperandRenderer, /*InsnID*/0, /*OldInsnID*/0, /*OpIdx*/3, /*OperandRenderer*/GIMT_Encode2(GICR_renderExtractCPol), // cachepolicy
        GIR_MergeMemOperands, /*InsnID*/0, /*NumInsns*/1, /*MergeInsnID's*/0,
        GIR_ConstrainSelectedInstOperands, /*InsnID*/0,
        GIR_EraseFromParent, /*InsnID*/0,
        // GIR_Coverage, 2451,
        GIR_Done,
      // Label 7207: @525428
      GIM_Try, /*On fail goto*//*Label 7208*/ GIMT_Encode4(525475), // Rule ID 2449 //
        GIM_CheckFeatures, GIMT_Encode2(GIFBS_isGFX12Plus),
        GIM_CheckComplexPattern, /*MI*/0, /*Op*/2, /*Renderer*/GIMT_Encode2(0), GIMT_Encode2(GICP_gi_smrd_buffer_imm),
        // (SIsbuffer_load_ushort:{ *:[i32] } v4i32:{ *:[v4i32] }:$sbase, (SMRDBufferImm:{ *:[i32] } i32:{ *:[i32] }:$offset), (timm:{ *:[i32] }):$cachepolicy)  =>  (S_BUFFER_LOAD_U16_IMM:{ *:[i32] } SReg_128:{ *:[v4i32] }:$sbase, i32imm:{ *:[i32] }:$offset, (extract_cpol:{ *:[i32] } ?:{ *:[i32] }:$cachepolicy))
        GIR_BuildMI, /*InsnID*/0, /*Opcode*/GIMT_Encode2(AMDGPU::S_BUFFER_LOAD_U16_IMM),
        GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/0, // DstI[sdst]
        GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/1, // sbase
        GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/0, // offset
        GIR_CustomOperandRenderer, /*InsnID*/0, /*OldInsnID*/0, /*OpIdx*/3, /*OperandRenderer*/GIMT_Encode2(GICR_renderExtractCPol), // cachepolicy
        GIR_MergeMemOperands, /*InsnID*/0, /*NumInsns*/1, /*MergeInsnID's*/0,
        GIR_ConstrainSelectedInstOperands, /*InsnID*/0,
        GIR_EraseFromParent, /*InsnID*/0,
        // GIR_Coverage, 2449,
        GIR_Done,
      // Label 7208: @525475
      GIM_Try, /*On fail goto*//*Label 7209*/ GIMT_Encode4(525517), // Rule ID 2450 //
        GIM_CheckFeatures, GIMT_Encode2(GIFBS_isGFX12Plus),
        // (SIsbuffer_load_ushort:{ *:[i32] } v4i32:{ *:[v4i32] }:$sbase, i32:{ *:[i32] }:$soffset, (timm:{ *:[i32] }):$cachepolicy)  =>  (S_BUFFER_LOAD_U16_SGPR_IMM:{ *:[i32] } SReg_128:{ *:[v4i32] }:$sbase, SReg_32:{ *:[i32] }:$soffset, 0:{ *:[i32] }, (extract_cpol:{ *:[i32] } ?:{ *:[i32] }:$cachepolicy))
        GIR_BuildMI, /*InsnID*/0, /*Opcode*/GIMT_Encode2(AMDGPU::S_BUFFER_LOAD_U16_SGPR_IMM),
        GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/0, // DstI[sdst]
        GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/1, // sbase
        GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/2, // soffset
        GIR_AddImm8, /*InsnID*/0, /*Imm*/0,
        GIR_CustomOperandRenderer, /*InsnID*/0, /*OldInsnID*/0, /*OpIdx*/3, /*OperandRenderer*/GIMT_Encode2(GICR_renderExtractCPol), // cachepolicy
        GIR_MergeMemOperands, /*InsnID*/0, /*NumInsns*/1, /*MergeInsnID's*/0,
        GIR_ConstrainSelectedInstOperands, /*InsnID*/0,
        GIR_EraseFromParent, /*InsnID*/0,
        // GIR_Coverage, 2450,
        GIR_Done,
      // Label 7209: @525517
      GIM_Reject,
    // Label 7206: @525518
    GIM_Reject,
    // Label 155: @525519
    GIM_SwitchType, /*MI*/0, /*Op*/0, /*[*/GIMT_Encode2(9), GIMT_Encode2(18), /*)*//*default:*//*Label 7214*/ GIMT_Encode4(531726),
    /*GILLT_s32*//*Label 7210*/ GIMT_Encode4(525566), GIMT_Encode4(0), GIMT_Encode4(0),
    /*GILLT_v2s32*//*Label 7211*/ GIMT_Encode4(527106), GIMT_Encode4(0),
    /*GILLT_v3s32*//*Label 7212*/ GIMT_Encode4(528646), GIMT_Encode4(0), GIMT_Encode4(0),
    /*GILLT_v4s32*//*Label 7213*/ GIMT_Encode4(530186),
    // Label 7210: @525566
    GIM_Try, /*On fail goto*//*Label 7215*/ GIMT_Encode4(527105),
      GIM_CheckType, /*MI*/0, /*Op*/1, /*Type*/GILLT_v4s32,
      GIM_CheckType, /*MI*/0, /*Op*/2, /*Type*/GILLT_s32,
      GIM_CheckType, /*MI*/0, /*Op*/3, /*Type*/GILLT_s32,
      GIM_CheckType, /*MI*/0, /*Op*/4, /*Type*/GILLT_s32,
      GIM_CheckRegBankForClass, /*MI*/0, /*Op*/0, /*RC*/GIMT_Encode2(AMDGPU::AV_32RegClassID),
      GIM_Try, /*On fail goto*//*Label 7216*/ GIMT_Encode4(525683), // Rule ID 5569 //
        GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasUnrestrictedSOffset),
        GIM_CheckConstantInt8, /*MI*/0, /*Op*/2, 0,
        GIM_CheckConstantInt8, /*MI*/0, /*Op*/3, 0,
        // MIs[0] offset
        GIM_CheckIsImm, /*MI*/0, /*Op*/5,
        // MIs[0] format
        GIM_CheckIsImm, /*MI*/0, /*Op*/6,
        // MIs[0] auxiliary
        GIM_CheckIsImm, /*MI*/0, /*Op*/7,
        // MIs[0] Operand 8
        GIM_CheckLiteralInt, /*MI*/0, /*Op*/8, GIMT_Encode8(0),
        GIM_CheckComplexPattern, /*MI*/0, /*Op*/4, /*Renderer*/GIMT_Encode2(0), GIMT_Encode2(GICP_gi_buf_soffset),
        // (SItbuffer_load:{ *:[i32] } v4i32:{ *:[v4i32] }:$rsrc, 0:{ *:[i32] }, 0:{ *:[i32] }, (BUFSOffset:{ *:[i32] } i32:{ *:[i32] }:$soffset), (timm:{ *:[i32] }):$offset, (timm:{ *:[i32] }):$format, (timm:{ *:[i32] }):$auxiliary, 0:{ *:[i1] })  =>  (TBUFFER_LOAD_FORMAT_X_OFFSET:{ *:[i32] } SReg_128:{ *:[v4i32] }:$rsrc, SCSrc_b32:{ *:[i32] }:$soffset, (timm:{ *:[i32] }):$offset, (as_i8timm:{ *:[i8] } ?:{ *:[i32] }:$format), (extract_cpol:{ *:[i32] } ?:{ *:[i32] }:$auxiliary), (extract_swz:{ *:[i1] } ?:{ *:[i32] }:$auxiliary))
        GIR_BuildMI, /*InsnID*/0, /*Opcode*/GIMT_Encode2(AMDGPU::TBUFFER_LOAD_FORMAT_X_OFFSET),
        GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/0, // DstI[vdata]
        GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/1, // rsrc
        GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/0, // soffset
        GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/5, // offset
        GIR_CustomOperandRenderer, /*InsnID*/0, /*OldInsnID*/0, /*OpIdx*/6, /*OperandRenderer*/GIMT_Encode2(GICR_renderTruncTImm), // format
        GIR_CustomOperandRenderer, /*InsnID*/0, /*OldInsnID*/0, /*OpIdx*/7, /*OperandRenderer*/GIMT_Encode2(GICR_renderExtractCPol), // auxiliary
        GIR_CustomOperandRenderer, /*InsnID*/0, /*OldInsnID*/0, /*OpIdx*/7, /*OperandRenderer*/GIMT_Encode2(GICR_renderExtractSWZ), // auxiliary
        GIR_MergeMemOperands, /*InsnID*/0, /*NumInsns*/1, /*MergeInsnID's*/0,
        GIR_ConstrainSelectedInstOperands, /*InsnID*/0,
        GIR_EraseFromParent, /*InsnID*/0,
        // GIR_Coverage, 5569,
        GIR_Done,
      // Label 7216: @525683
      GIM_Try, /*On fail goto*//*Label 7217*/ GIMT_Encode4(525771), // Rule ID 5573 //
        GIM_CheckConstantInt8, /*MI*/0, /*Op*/2, 0,
        GIM_CheckConstantInt8, /*MI*/0, /*Op*/3, 0,
        // MIs[0] offset
        GIM_CheckIsImm, /*MI*/0, /*Op*/5,
        // MIs[0] format
        GIM_CheckIsImm, /*MI*/0, /*Op*/6,
        // MIs[0] auxiliary
        GIM_CheckIsImm, /*MI*/0, /*Op*/7,
        // MIs[0] Operand 8
        GIM_CheckLiteralInt, /*MI*/0, /*Op*/8, GIMT_Encode8(0),
        GIM_CheckComplexPattern, /*MI*/0, /*Op*/4, /*Renderer*/GIMT_Encode2(0), GIMT_Encode2(GICP_gi_buf_soffset),
        // (SItbuffer_load:{ *:[i32] } v4i32:{ *:[v4i32] }:$rsrc, 0:{ *:[i32] }, 0:{ *:[i32] }, (BUFSOffset:{ *:[i32] } i32:{ *:[i32] }:$soffset), (timm:{ *:[i32] }):$offset, (timm:{ *:[i32] }):$format, (timm:{ *:[i32] }):$auxiliary, 0:{ *:[i1] })  =>  (TBUFFER_LOAD_FORMAT_X_VBUFFER_OFFSET:{ *:[i32] } SReg_128:{ *:[v4i32] }:$rsrc, SCSrc_b32:{ *:[i32] }:$soffset, (timm:{ *:[i32] }):$offset, (as_i8timm:{ *:[i8] } ?:{ *:[i32] }:$format), (extract_cpol:{ *:[i32] } ?:{ *:[i32] }:$auxiliary), (extract_swz:{ *:[i1] } ?:{ *:[i32] }:$auxiliary))
        GIR_BuildMI, /*InsnID*/0, /*Opcode*/GIMT_Encode2(AMDGPU::TBUFFER_LOAD_FORMAT_X_VBUFFER_OFFSET),
        GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/0, // DstI[vdata]
        GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/1, // rsrc
        GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/0, // soffset
        GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/5, // offset
        GIR_CustomOperandRenderer, /*InsnID*/0, /*OldInsnID*/0, /*OpIdx*/6, /*OperandRenderer*/GIMT_Encode2(GICR_renderTruncTImm), // format
        GIR_CustomOperandRenderer, /*InsnID*/0, /*OldInsnID*/0, /*OpIdx*/7, /*OperandRenderer*/GIMT_Encode2(GICR_renderExtractCPol), // auxiliary
        GIR_CustomOperandRenderer, /*InsnID*/0, /*OldInsnID*/0, /*OpIdx*/7, /*OperandRenderer*/GIMT_Encode2(GICR_renderExtractSWZ), // auxiliary
        GIR_MergeMemOperands, /*InsnID*/0, /*NumInsns*/1, /*MergeInsnID's*/0,
        GIR_ConstrainSelectedInstOperands, /*InsnID*/0,
        GIR_EraseFromParent, /*InsnID*/0,
        // GIR_Coverage, 5573,
        GIR_Done,
      // Label 7217: @525771
      GIM_Try, /*On fail goto*//*Label 7218*/ GIMT_Encode4(525862), // Rule ID 5601 //
        GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasUnrestrictedSOffset),
        GIM_CheckConstantInt8, /*MI*/0, /*Op*/2, 0,
        GIM_CheckConstantInt8, /*MI*/0, /*Op*/3, 0,
        // MIs[0] offset
        GIM_CheckIsImm, /*MI*/0, /*Op*/5,
        // MIs[0] format
        GIM_CheckIsImm, /*MI*/0, /*Op*/6,
        // MIs[0] auxiliary
        GIM_CheckIsImm, /*MI*/0, /*Op*/7,
        // MIs[0] Operand 8
        GIM_CheckLiteralInt, /*MI*/0, /*Op*/8, GIMT_Encode8(0),
        GIM_CheckComplexPattern, /*MI*/0, /*Op*/4, /*Renderer*/GIMT_Encode2(0), GIMT_Encode2(GICP_gi_buf_soffset),
        // (SItbuffer_load:{ *:[f32] } v4i32:{ *:[v4i32] }:$rsrc, 0:{ *:[i32] }, 0:{ *:[i32] }, (BUFSOffset:{ *:[i32] } i32:{ *:[i32] }:$soffset), (timm:{ *:[i32] }):$offset, (timm:{ *:[i32] }):$format, (timm:{ *:[i32] }):$auxiliary, 0:{ *:[i1] })  =>  (TBUFFER_LOAD_FORMAT_X_OFFSET:{ *:[f32] } SReg_128:{ *:[v4i32] }:$rsrc, SCSrc_b32:{ *:[i32] }:$soffset, (timm:{ *:[i32] }):$offset, (as_i8timm:{ *:[i8] } ?:{ *:[i32] }:$format), (extract_cpol:{ *:[i32] } ?:{ *:[i32] }:$auxiliary), (extract_swz:{ *:[i1] } ?:{ *:[i32] }:$auxiliary))
        GIR_BuildMI, /*InsnID*/0, /*Opcode*/GIMT_Encode2(AMDGPU::TBUFFER_LOAD_FORMAT_X_OFFSET),
        GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/0, // DstI[vdata]
        GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/1, // rsrc
        GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/0, // soffset
        GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/5, // offset
        GIR_CustomOperandRenderer, /*InsnID*/0, /*OldInsnID*/0, /*OpIdx*/6, /*OperandRenderer*/GIMT_Encode2(GICR_renderTruncTImm), // format
        GIR_CustomOperandRenderer, /*InsnID*/0, /*OldInsnID*/0, /*OpIdx*/7, /*OperandRenderer*/GIMT_Encode2(GICR_renderExtractCPol), // auxiliary
        GIR_CustomOperandRenderer, /*InsnID*/0, /*OldInsnID*/0, /*OpIdx*/7, /*OperandRenderer*/GIMT_Encode2(GICR_renderExtractSWZ), // auxiliary
        GIR_MergeMemOperands, /*InsnID*/0, /*NumInsns*/1, /*MergeInsnID's*/0,
        GIR_ConstrainSelectedInstOperands, /*InsnID*/0,
        GIR_EraseFromParent, /*InsnID*/0,
        // GIR_Coverage, 5601,
        GIR_Done,
      // Label 7218: @525862
      GIM_Try, /*On fail goto*//*Label 7219*/ GIMT_Encode4(525950), // Rule ID 5605 //
        GIM_CheckConstantInt8, /*MI*/0, /*Op*/2, 0,
        GIM_CheckConstantInt8, /*MI*/0, /*Op*/3, 0,
        // MIs[0] offset
        GIM_CheckIsImm, /*MI*/0, /*Op*/5,
        // MIs[0] format
        GIM_CheckIsImm, /*MI*/0, /*Op*/6,
        // MIs[0] auxiliary
        GIM_CheckIsImm, /*MI*/0, /*Op*/7,
        // MIs[0] Operand 8
        GIM_CheckLiteralInt, /*MI*/0, /*Op*/8, GIMT_Encode8(0),
        GIM_CheckComplexPattern, /*MI*/0, /*Op*/4, /*Renderer*/GIMT_Encode2(0), GIMT_Encode2(GICP_gi_buf_soffset),
        // (SItbuffer_load:{ *:[f32] } v4i32:{ *:[v4i32] }:$rsrc, 0:{ *:[i32] }, 0:{ *:[i32] }, (BUFSOffset:{ *:[i32] } i32:{ *:[i32] }:$soffset), (timm:{ *:[i32] }):$offset, (timm:{ *:[i32] }):$format, (timm:{ *:[i32] }):$auxiliary, 0:{ *:[i1] })  =>  (TBUFFER_LOAD_FORMAT_X_VBUFFER_OFFSET:{ *:[f32] } SReg_128:{ *:[v4i32] }:$rsrc, SCSrc_b32:{ *:[i32] }:$soffset, (timm:{ *:[i32] }):$offset, (as_i8timm:{ *:[i8] } ?:{ *:[i32] }:$format), (extract_cpol:{ *:[i32] } ?:{ *:[i32] }:$auxiliary), (extract_swz:{ *:[i1] } ?:{ *:[i32] }:$auxiliary))
        GIR_BuildMI, /*InsnID*/0, /*Opcode*/GIMT_Encode2(AMDGPU::TBUFFER_LOAD_FORMAT_X_VBUFFER_OFFSET),
        GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/0, // DstI[vdata]
        GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/1, // rsrc
        GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/0, // soffset
        GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/5, // offset
        GIR_CustomOperandRenderer, /*InsnID*/0, /*OldInsnID*/0, /*OpIdx*/6, /*OperandRenderer*/GIMT_Encode2(GICR_renderTruncTImm), // format
        GIR_CustomOperandRenderer, /*InsnID*/0, /*OldInsnID*/0, /*OpIdx*/7, /*OperandRenderer*/GIMT_Encode2(GICR_renderExtractCPol), // auxiliary
        GIR_CustomOperandRenderer, /*InsnID*/0, /*OldInsnID*/0, /*OpIdx*/7, /*OperandRenderer*/GIMT_Encode2(GICR_renderExtractSWZ), // auxiliary
        GIR_MergeMemOperands, /*InsnID*/0, /*NumInsns*/1, /*MergeInsnID's*/0,
        GIR_ConstrainSelectedInstOperands, /*InsnID*/0,
        GIR_EraseFromParent, /*InsnID*/0,
        // GIR_Coverage, 5605,
        GIR_Done,
      // Label 7219: @525950
      GIM_Try, /*On fail goto*//*Label 7220*/ GIMT_Encode4(526041), // Rule ID 5571 //
        GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasUnrestrictedSOffset),
        GIM_CheckConstantInt8, /*MI*/0, /*Op*/2, 0,
        // MIs[0] offset
        GIM_CheckIsImm, /*MI*/0, /*Op*/5,
        // MIs[0] format
        GIM_CheckIsImm, /*MI*/0, /*Op*/6,
        // MIs[0] auxiliary
        GIM_CheckIsImm, /*MI*/0, /*Op*/7,
        // MIs[0] Operand 8
        GIM_CheckLiteralInt, /*MI*/0, /*Op*/8, GIMT_Encode8(0),
        GIM_CheckComplexPattern, /*MI*/0, /*Op*/4, /*Renderer*/GIMT_Encode2(0), GIMT_Encode2(GICP_gi_buf_soffset),
        // (SItbuffer_load:{ *:[i32] } v4i32:{ *:[v4i32] }:$rsrc, 0:{ *:[i32] }, i32:{ *:[i32] }:$voffset, (BUFSOffset:{ *:[i32] } i32:{ *:[i32] }:$soffset), (timm:{ *:[i32] }):$offset, (timm:{ *:[i32] }):$format, (timm:{ *:[i32] }):$auxiliary, 0:{ *:[i1] })  =>  (TBUFFER_LOAD_FORMAT_X_OFFEN:{ *:[i32] } VGPR_32:{ *:[i32] }:$voffset, SReg_128:{ *:[v4i32] }:$rsrc, SCSrc_b32:{ *:[i32] }:$soffset, (timm:{ *:[i32] }):$offset, (as_i8timm:{ *:[i8] } ?:{ *:[i32] }:$format), (extract_cpol:{ *:[i32] } ?:{ *:[i32] }:$auxiliary), (extract_swz:{ *:[i1] } ?:{ *:[i32] }:$auxiliary))
        GIR_BuildMI, /*InsnID*/0, /*Opcode*/GIMT_Encode2(AMDGPU::TBUFFER_LOAD_FORMAT_X_OFFEN),
        GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/0, // DstI[vdata]
        GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/3, // voffset
        GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/1, // rsrc
        GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/0, // soffset
        GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/5, // offset
        GIR_CustomOperandRenderer, /*InsnID*/0, /*OldInsnID*/0, /*OpIdx*/6, /*OperandRenderer*/GIMT_Encode2(GICR_renderTruncTImm), // format
        GIR_CustomOperandRenderer, /*InsnID*/0, /*OldInsnID*/0, /*OpIdx*/7, /*OperandRenderer*/GIMT_Encode2(GICR_renderExtractCPol), // auxiliary
        GIR_CustomOperandRenderer, /*InsnID*/0, /*OldInsnID*/0, /*OpIdx*/7, /*OperandRenderer*/GIMT_Encode2(GICR_renderExtractSWZ), // auxiliary
        GIR_MergeMemOperands, /*InsnID*/0, /*NumInsns*/1, /*MergeInsnID's*/0,
        GIR_ConstrainSelectedInstOperands, /*InsnID*/0,
        GIR_EraseFromParent, /*InsnID*/0,
        // GIR_Coverage, 5571,
        GIR_Done,
      // Label 7220: @526041
      GIM_Try, /*On fail goto*//*Label 7221*/ GIMT_Encode4(526129), // Rule ID 5575 //
        GIM_CheckConstantInt8, /*MI*/0, /*Op*/2, 0,
        // MIs[0] offset
        GIM_CheckIsImm, /*MI*/0, /*Op*/5,
        // MIs[0] format
        GIM_CheckIsImm, /*MI*/0, /*Op*/6,
        // MIs[0] auxiliary
        GIM_CheckIsImm, /*MI*/0, /*Op*/7,
        // MIs[0] Operand 8
        GIM_CheckLiteralInt, /*MI*/0, /*Op*/8, GIMT_Encode8(0),
        GIM_CheckComplexPattern, /*MI*/0, /*Op*/4, /*Renderer*/GIMT_Encode2(0), GIMT_Encode2(GICP_gi_buf_soffset),
        // (SItbuffer_load:{ *:[i32] } v4i32:{ *:[v4i32] }:$rsrc, 0:{ *:[i32] }, i32:{ *:[i32] }:$voffset, (BUFSOffset:{ *:[i32] } i32:{ *:[i32] }:$soffset), (timm:{ *:[i32] }):$offset, (timm:{ *:[i32] }):$format, (timm:{ *:[i32] }):$auxiliary, 0:{ *:[i1] })  =>  (TBUFFER_LOAD_FORMAT_X_VBUFFER_OFFEN:{ *:[i32] } VGPR_32:{ *:[i32] }:$voffset, SReg_128:{ *:[v4i32] }:$rsrc, SCSrc_b32:{ *:[i32] }:$soffset, (timm:{ *:[i32] }):$offset, (as_i8timm:{ *:[i8] } ?:{ *:[i32] }:$format), (extract_cpol:{ *:[i32] } ?:{ *:[i32] }:$auxiliary), (extract_swz:{ *:[i1] } ?:{ *:[i32] }:$auxiliary))
        GIR_BuildMI, /*InsnID*/0, /*Opcode*/GIMT_Encode2(AMDGPU::TBUFFER_LOAD_FORMAT_X_VBUFFER_OFFEN),
        GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/0, // DstI[vdata]
        GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/3, // voffset
        GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/1, // rsrc
        GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/0, // soffset
        GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/5, // offset
        GIR_CustomOperandRenderer, /*InsnID*/0, /*OldInsnID*/0, /*OpIdx*/6, /*OperandRenderer*/GIMT_Encode2(GICR_renderTruncTImm), // format
        GIR_CustomOperandRenderer, /*InsnID*/0, /*OldInsnID*/0, /*OpIdx*/7, /*OperandRenderer*/GIMT_Encode2(GICR_renderExtractCPol), // auxiliary
        GIR_CustomOperandRenderer, /*InsnID*/0, /*OldInsnID*/0, /*OpIdx*/7, /*OperandRenderer*/GIMT_Encode2(GICR_renderExtractSWZ), // auxiliary
        GIR_MergeMemOperands, /*InsnID*/0, /*NumInsns*/1, /*MergeInsnID's*/0,
        GIR_ConstrainSelectedInstOperands, /*InsnID*/0,
        GIR_EraseFromParent, /*InsnID*/0,
        // GIR_Coverage, 5575,
        GIR_Done,
      // Label 7221: @526129
      GIM_Try, /*On fail goto*//*Label 7222*/ GIMT_Encode4(526220), // Rule ID 5603 //
        GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasUnrestrictedSOffset),
        GIM_CheckConstantInt8, /*MI*/0, /*Op*/2, 0,
        // MIs[0] offset
        GIM_CheckIsImm, /*MI*/0, /*Op*/5,
        // MIs[0] format
        GIM_CheckIsImm, /*MI*/0, /*Op*/6,
        // MIs[0] auxiliary
        GIM_CheckIsImm, /*MI*/0, /*Op*/7,
        // MIs[0] Operand 8
        GIM_CheckLiteralInt, /*MI*/0, /*Op*/8, GIMT_Encode8(0),
        GIM_CheckComplexPattern, /*MI*/0, /*Op*/4, /*Renderer*/GIMT_Encode2(0), GIMT_Encode2(GICP_gi_buf_soffset),
        // (SItbuffer_load:{ *:[f32] } v4i32:{ *:[v4i32] }:$rsrc, 0:{ *:[i32] }, i32:{ *:[i32] }:$voffset, (BUFSOffset:{ *:[i32] } i32:{ *:[i32] }:$soffset), (timm:{ *:[i32] }):$offset, (timm:{ *:[i32] }):$format, (timm:{ *:[i32] }):$auxiliary, 0:{ *:[i1] })  =>  (TBUFFER_LOAD_FORMAT_X_OFFEN:{ *:[f32] } VGPR_32:{ *:[i32] }:$voffset, SReg_128:{ *:[v4i32] }:$rsrc, SCSrc_b32:{ *:[i32] }:$soffset, (timm:{ *:[i32] }):$offset, (as_i8timm:{ *:[i8] } ?:{ *:[i32] }:$format), (extract_cpol:{ *:[i32] } ?:{ *:[i32] }:$auxiliary), (extract_swz:{ *:[i1] } ?:{ *:[i32] }:$auxiliary))
        GIR_BuildMI, /*InsnID*/0, /*Opcode*/GIMT_Encode2(AMDGPU::TBUFFER_LOAD_FORMAT_X_OFFEN),
        GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/0, // DstI[vdata]
        GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/3, // voffset
        GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/1, // rsrc
        GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/0, // soffset
        GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/5, // offset
        GIR_CustomOperandRenderer, /*InsnID*/0, /*OldInsnID*/0, /*OpIdx*/6, /*OperandRenderer*/GIMT_Encode2(GICR_renderTruncTImm), // format
        GIR_CustomOperandRenderer, /*InsnID*/0, /*OldInsnID*/0, /*OpIdx*/7, /*OperandRenderer*/GIMT_Encode2(GICR_renderExtractCPol), // auxiliary
        GIR_CustomOperandRenderer, /*InsnID*/0, /*OldInsnID*/0, /*OpIdx*/7, /*OperandRenderer*/GIMT_Encode2(GICR_renderExtractSWZ), // auxiliary
        GIR_MergeMemOperands, /*InsnID*/0, /*NumInsns*/1, /*MergeInsnID's*/0,
        GIR_ConstrainSelectedInstOperands, /*InsnID*/0,
        GIR_EraseFromParent, /*InsnID*/0,
        // GIR_Coverage, 5603,
        GIR_Done,
      // Label 7222: @526220
      GIM_Try, /*On fail goto*//*Label 7223*/ GIMT_Encode4(526308), // Rule ID 5607 //
        GIM_CheckConstantInt8, /*MI*/0, /*Op*/2, 0,
        // MIs[0] offset
        GIM_CheckIsImm, /*MI*/0, /*Op*/5,
        // MIs[0] format
        GIM_CheckIsImm, /*MI*/0, /*Op*/6,
        // MIs[0] auxiliary
        GIM_CheckIsImm, /*MI*/0, /*Op*/7,
        // MIs[0] Operand 8
        GIM_CheckLiteralInt, /*MI*/0, /*Op*/8, GIMT_Encode8(0),
        GIM_CheckComplexPattern, /*MI*/0, /*Op*/4, /*Renderer*/GIMT_Encode2(0), GIMT_Encode2(GICP_gi_buf_soffset),
        // (SItbuffer_load:{ *:[f32] } v4i32:{ *:[v4i32] }:$rsrc, 0:{ *:[i32] }, i32:{ *:[i32] }:$voffset, (BUFSOffset:{ *:[i32] } i32:{ *:[i32] }:$soffset), (timm:{ *:[i32] }):$offset, (timm:{ *:[i32] }):$format, (timm:{ *:[i32] }):$auxiliary, 0:{ *:[i1] })  =>  (TBUFFER_LOAD_FORMAT_X_VBUFFER_OFFEN:{ *:[f32] } VGPR_32:{ *:[i32] }:$voffset, SReg_128:{ *:[v4i32] }:$rsrc, SCSrc_b32:{ *:[i32] }:$soffset, (timm:{ *:[i32] }):$offset, (as_i8timm:{ *:[i8] } ?:{ *:[i32] }:$format), (extract_cpol:{ *:[i32] } ?:{ *:[i32] }:$auxiliary), (extract_swz:{ *:[i1] } ?:{ *:[i32] }:$auxiliary))
        GIR_BuildMI, /*InsnID*/0, /*Opcode*/GIMT_Encode2(AMDGPU::TBUFFER_LOAD_FORMAT_X_VBUFFER_OFFEN),
        GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/0, // DstI[vdata]
        GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/3, // voffset
        GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/1, // rsrc
        GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/0, // soffset
        GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/5, // offset
        GIR_CustomOperandRenderer, /*InsnID*/0, /*OldInsnID*/0, /*OpIdx*/6, /*OperandRenderer*/GIMT_Encode2(GICR_renderTruncTImm), // format
        GIR_CustomOperandRenderer, /*InsnID*/0, /*OldInsnID*/0, /*OpIdx*/7, /*OperandRenderer*/GIMT_Encode2(GICR_renderExtractCPol), // auxiliary
        GIR_CustomOperandRenderer, /*InsnID*/0, /*OldInsnID*/0, /*OpIdx*/7, /*OperandRenderer*/GIMT_Encode2(GICR_renderExtractSWZ), // auxiliary
        GIR_MergeMemOperands, /*InsnID*/0, /*NumInsns*/1, /*MergeInsnID's*/0,
        GIR_ConstrainSelectedInstOperands, /*InsnID*/0,
        GIR_EraseFromParent, /*InsnID*/0,
        // GIR_Coverage, 5607,
        GIR_Done,
      // Label 7223: @526308
      GIM_Try, /*On fail goto*//*Label 7224*/ GIMT_Encode4(526391), // Rule ID 5570 //
        GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasUnrestrictedSOffset),
        GIM_CheckConstantInt8, /*MI*/0, /*Op*/3, 0,
        // MIs[0] offset
        GIM_CheckIsImm, /*MI*/0, /*Op*/5,
        // MIs[0] format
        GIM_CheckIsImm, /*MI*/0, /*Op*/6,
        // MIs[0] auxiliary
        GIM_CheckIsImm, /*MI*/0, /*Op*/7,
        // MIs[0] Operand 8
        GIM_CheckIsImm, /*MI*/0, /*Op*/8,
        GIM_CheckComplexPattern, /*MI*/0, /*Op*/4, /*Renderer*/GIMT_Encode2(0), GIMT_Encode2(GICP_gi_buf_soffset),
        // (SItbuffer_load:{ *:[i32] } v4i32:{ *:[v4i32] }:$rsrc, i32:{ *:[i32] }:$vindex, 0:{ *:[i32] }, (BUFSOffset:{ *:[i32] } i32:{ *:[i32] }:$soffset), (timm:{ *:[i32] }):$offset, (timm:{ *:[i32] }):$format, (timm:{ *:[i32] }):$auxiliary, (timm:{ *:[i1] }))  =>  (TBUFFER_LOAD_FORMAT_X_IDXEN:{ *:[i32] } VGPR_32:{ *:[i32] }:$vindex, SReg_128:{ *:[v4i32] }:$rsrc, SCSrc_b32:{ *:[i32] }:$soffset, (timm:{ *:[i32] }):$offset, (as_i8timm:{ *:[i8] } ?:{ *:[i32] }:$format), (extract_cpol:{ *:[i32] } ?:{ *:[i32] }:$auxiliary), (extract_swz:{ *:[i1] } ?:{ *:[i32] }:$auxiliary))
        GIR_BuildMI, /*InsnID*/0, /*Opcode*/GIMT_Encode2(AMDGPU::TBUFFER_LOAD_FORMAT_X_IDXEN),
        GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/0, // DstI[vdata]
        GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/2, // vindex
        GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/1, // rsrc
        GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/0, // soffset
        GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/5, // offset
        GIR_CustomOperandRenderer, /*InsnID*/0, /*OldInsnID*/0, /*OpIdx*/6, /*OperandRenderer*/GIMT_Encode2(GICR_renderTruncTImm), // format
        GIR_CustomOperandRenderer, /*InsnID*/0, /*OldInsnID*/0, /*OpIdx*/7, /*OperandRenderer*/GIMT_Encode2(GICR_renderExtractCPol), // auxiliary
        GIR_CustomOperandRenderer, /*InsnID*/0, /*OldInsnID*/0, /*OpIdx*/7, /*OperandRenderer*/GIMT_Encode2(GICR_renderExtractSWZ), // auxiliary
        GIR_MergeMemOperands, /*InsnID*/0, /*NumInsns*/1, /*MergeInsnID's*/0,
        GIR_ConstrainSelectedInstOperands, /*InsnID*/0,
        GIR_EraseFromParent, /*InsnID*/0,
        // GIR_Coverage, 5570,
        GIR_Done,
      // Label 7224: @526391
      GIM_Try, /*On fail goto*//*Label 7225*/ GIMT_Encode4(526471), // Rule ID 5574 //
        GIM_CheckConstantInt8, /*MI*/0, /*Op*/3, 0,
        // MIs[0] offset
        GIM_CheckIsImm, /*MI*/0, /*Op*/5,
        // MIs[0] format
        GIM_CheckIsImm, /*MI*/0, /*Op*/6,
        // MIs[0] auxiliary
        GIM_CheckIsImm, /*MI*/0, /*Op*/7,
        // MIs[0] Operand 8
        GIM_CheckIsImm, /*MI*/0, /*Op*/8,
        GIM_CheckComplexPattern, /*MI*/0, /*Op*/4, /*Renderer*/GIMT_Encode2(0), GIMT_Encode2(GICP_gi_buf_soffset),
        // (SItbuffer_load:{ *:[i32] } v4i32:{ *:[v4i32] }:$rsrc, i32:{ *:[i32] }:$vindex, 0:{ *:[i32] }, (BUFSOffset:{ *:[i32] } i32:{ *:[i32] }:$soffset), (timm:{ *:[i32] }):$offset, (timm:{ *:[i32] }):$format, (timm:{ *:[i32] }):$auxiliary, (timm:{ *:[i1] }))  =>  (TBUFFER_LOAD_FORMAT_X_VBUFFER_IDXEN:{ *:[i32] } VGPR_32:{ *:[i32] }:$vindex, SReg_128:{ *:[v4i32] }:$rsrc, SCSrc_b32:{ *:[i32] }:$soffset, (timm:{ *:[i32] }):$offset, (as_i8timm:{ *:[i8] } ?:{ *:[i32] }:$format), (extract_cpol:{ *:[i32] } ?:{ *:[i32] }:$auxiliary), (extract_swz:{ *:[i1] } ?:{ *:[i32] }:$auxiliary))
        GIR_BuildMI, /*InsnID*/0, /*Opcode*/GIMT_Encode2(AMDGPU::TBUFFER_LOAD_FORMAT_X_VBUFFER_IDXEN),
        GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/0, // DstI[vdata]
        GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/2, // vindex
        GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/1, // rsrc
        GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/0, // soffset
        GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/5, // offset
        GIR_CustomOperandRenderer, /*InsnID*/0, /*OldInsnID*/0, /*OpIdx*/6, /*OperandRenderer*/GIMT_Encode2(GICR_renderTruncTImm), // format
        GIR_CustomOperandRenderer, /*InsnID*/0, /*OldInsnID*/0, /*OpIdx*/7, /*OperandRenderer*/GIMT_Encode2(GICR_renderExtractCPol), // auxiliary
        GIR_CustomOperandRenderer, /*InsnID*/0, /*OldInsnID*/0, /*OpIdx*/7, /*OperandRenderer*/GIMT_Encode2(GICR_renderExtractSWZ), // auxiliary
        GIR_MergeMemOperands, /*InsnID*/0, /*NumInsns*/1, /*MergeInsnID's*/0,
        GIR_ConstrainSelectedInstOperands, /*InsnID*/0,
        GIR_EraseFromParent, /*InsnID*/0,
        // GIR_Coverage, 5574,
        GIR_Done,
      // Label 7225: @526471
      GIM_Try, /*On fail goto*//*Label 7226*/ GIMT_Encode4(526554), // Rule ID 5602 //
        GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasUnrestrictedSOffset),
        GIM_CheckConstantInt8, /*MI*/0, /*Op*/3, 0,
        // MIs[0] offset
        GIM_CheckIsImm, /*MI*/0, /*Op*/5,
        // MIs[0] format
        GIM_CheckIsImm, /*MI*/0, /*Op*/6,
        // MIs[0] auxiliary
        GIM_CheckIsImm, /*MI*/0, /*Op*/7,
        // MIs[0] Operand 8
        GIM_CheckIsImm, /*MI*/0, /*Op*/8,
        GIM_CheckComplexPattern, /*MI*/0, /*Op*/4, /*Renderer*/GIMT_Encode2(0), GIMT_Encode2(GICP_gi_buf_soffset),
        // (SItbuffer_load:{ *:[f32] } v4i32:{ *:[v4i32] }:$rsrc, i32:{ *:[i32] }:$vindex, 0:{ *:[i32] }, (BUFSOffset:{ *:[i32] } i32:{ *:[i32] }:$soffset), (timm:{ *:[i32] }):$offset, (timm:{ *:[i32] }):$format, (timm:{ *:[i32] }):$auxiliary, (timm:{ *:[i1] }))  =>  (TBUFFER_LOAD_FORMAT_X_IDXEN:{ *:[f32] } VGPR_32:{ *:[i32] }:$vindex, SReg_128:{ *:[v4i32] }:$rsrc, SCSrc_b32:{ *:[i32] }:$soffset, (timm:{ *:[i32] }):$offset, (as_i8timm:{ *:[i8] } ?:{ *:[i32] }:$format), (extract_cpol:{ *:[i32] } ?:{ *:[i32] }:$auxiliary), (extract_swz:{ *:[i1] } ?:{ *:[i32] }:$auxiliary))
        GIR_BuildMI, /*InsnID*/0, /*Opcode*/GIMT_Encode2(AMDGPU::TBUFFER_LOAD_FORMAT_X_IDXEN),
        GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/0, // DstI[vdata]
        GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/2, // vindex
        GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/1, // rsrc
        GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/0, // soffset
        GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/5, // offset
        GIR_CustomOperandRenderer, /*InsnID*/0, /*OldInsnID*/0, /*OpIdx*/6, /*OperandRenderer*/GIMT_Encode2(GICR_renderTruncTImm), // format
        GIR_CustomOperandRenderer, /*InsnID*/0, /*OldInsnID*/0, /*OpIdx*/7, /*OperandRenderer*/GIMT_Encode2(GICR_renderExtractCPol), // auxiliary
        GIR_CustomOperandRenderer, /*InsnID*/0, /*OldInsnID*/0, /*OpIdx*/7, /*OperandRenderer*/GIMT_Encode2(GICR_renderExtractSWZ), // auxiliary
        GIR_MergeMemOperands, /*InsnID*/0, /*NumInsns*/1, /*MergeInsnID's*/0,
        GIR_ConstrainSelectedInstOperands, /*InsnID*/0,
        GIR_EraseFromParent, /*InsnID*/0,
        // GIR_Coverage, 5602,
        GIR_Done,
      // Label 7226: @526554
      GIM_Try, /*On fail goto*//*Label 7227*/ GIMT_Encode4(526634), // Rule ID 5606 //
        GIM_CheckConstantInt8, /*MI*/0, /*Op*/3, 0,
        // MIs[0] offset
        GIM_CheckIsImm, /*MI*/0, /*Op*/5,
        // MIs[0] format
        GIM_CheckIsImm, /*MI*/0, /*Op*/6,
        // MIs[0] auxiliary
        GIM_CheckIsImm, /*MI*/0, /*Op*/7,
        // MIs[0] Operand 8
        GIM_CheckIsImm, /*MI*/0, /*Op*/8,
        GIM_CheckComplexPattern, /*MI*/0, /*Op*/4, /*Renderer*/GIMT_Encode2(0), GIMT_Encode2(GICP_gi_buf_soffset),
        // (SItbuffer_load:{ *:[f32] } v4i32:{ *:[v4i32] }:$rsrc, i32:{ *:[i32] }:$vindex, 0:{ *:[i32] }, (BUFSOffset:{ *:[i32] } i32:{ *:[i32] }:$soffset), (timm:{ *:[i32] }):$offset, (timm:{ *:[i32] }):$format, (timm:{ *:[i32] }):$auxiliary, (timm:{ *:[i1] }))  =>  (TBUFFER_LOAD_FORMAT_X_VBUFFER_IDXEN:{ *:[f32] } VGPR_32:{ *:[i32] }:$vindex, SReg_128:{ *:[v4i32] }:$rsrc, SCSrc_b32:{ *:[i32] }:$soffset, (timm:{ *:[i32] }):$offset, (as_i8timm:{ *:[i8] } ?:{ *:[i32] }:$format), (extract_cpol:{ *:[i32] } ?:{ *:[i32] }:$auxiliary), (extract_swz:{ *:[i1] } ?:{ *:[i32] }:$auxiliary))
        GIR_BuildMI, /*InsnID*/0, /*Opcode*/GIMT_Encode2(AMDGPU::TBUFFER_LOAD_FORMAT_X_VBUFFER_IDXEN),
        GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/0, // DstI[vdata]
        GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/2, // vindex
        GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/1, // rsrc
        GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/0, // soffset
        GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/5, // offset
        GIR_CustomOperandRenderer, /*InsnID*/0, /*OldInsnID*/0, /*OpIdx*/6, /*OperandRenderer*/GIMT_Encode2(GICR_renderTruncTImm), // format
        GIR_CustomOperandRenderer, /*InsnID*/0, /*OldInsnID*/0, /*OpIdx*/7, /*OperandRenderer*/GIMT_Encode2(GICR_renderExtractCPol), // auxiliary
        GIR_CustomOperandRenderer, /*InsnID*/0, /*OldInsnID*/0, /*OpIdx*/7, /*OperandRenderer*/GIMT_Encode2(GICR_renderExtractSWZ), // auxiliary
        GIR_MergeMemOperands, /*InsnID*/0, /*NumInsns*/1, /*MergeInsnID's*/0,
        GIR_ConstrainSelectedInstOperands, /*InsnID*/0,
        GIR_EraseFromParent, /*InsnID*/0,
        // GIR_Coverage, 5606,
        GIR_Done,
      // Label 7227: @526634
      GIM_Try, /*On fail goto*//*Label 7228*/ GIMT_Encode4(526753), // Rule ID 5572 //
        GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasUnrestrictedSOffset),
        // MIs[0] offset
        GIM_CheckIsImm, /*MI*/0, /*Op*/5,
        // MIs[0] format
        GIM_CheckIsImm, /*MI*/0, /*Op*/6,
        // MIs[0] auxiliary
        GIM_CheckIsImm, /*MI*/0, /*Op*/7,
        // MIs[0] Operand 8
        GIM_CheckIsImm, /*MI*/0, /*Op*/8,
        GIM_CheckComplexPattern, /*MI*/0, /*Op*/4, /*Renderer*/GIMT_Encode2(0), GIMT_Encode2(GICP_gi_buf_soffset),
        // (SItbuffer_load:{ *:[i32] } v4i32:{ *:[v4i32] }:$rsrc, i32:{ *:[i32] }:$vindex, i32:{ *:[i32] }:$voffset, (BUFSOffset:{ *:[i32] } i32:{ *:[i32] }:$soffset), (timm:{ *:[i32] }):$offset, (timm:{ *:[i32] }):$format, (timm:{ *:[i32] }):$auxiliary, (timm:{ *:[i1] }))  =>  (TBUFFER_LOAD_FORMAT_X_BOTHEN:{ *:[i32] } (REG_SEQUENCE:{ *:[i64] } VReg_64:{ *:[i32] }, VGPR_32:{ *:[i32] }:$vindex, sub0:{ *:[i32] }, VGPR_32:{ *:[i32] }:$voffset, sub1:{ *:[i32] }), SReg_128:{ *:[v4i32] }:$rsrc, SCSrc_b32:{ *:[i32] }:$soffset, (timm:{ *:[i32] }):$offset, (as_i8timm:{ *:[i8] } ?:{ *:[i32] }:$format), (extract_cpol:{ *:[i32] } ?:{ *:[i32] }:$auxiliary), (extract_swz:{ *:[i1] } ?:{ *:[i32] }:$auxiliary))
        GIR_MakeTempReg, /*TempRegID*/0, /*TypeID*/GILLT_s64,
        GIR_BuildMI, /*InsnID*/1, /*Opcode*/GIMT_Encode2(TargetOpcode::REG_SEQUENCE),
        GIR_AddTempRegister, /*InsnID*/1, /*TempRegID*/0, /*TempRegFlags*/GIMT_Encode2(RegState::Define),
        GIR_Copy, /*NewInsnID*/1, /*OldInsnID*/0, /*OpIdx*/2, // vindex
        GIR_AddImm8, /*InsnID*/1, /*SubRegIndex*/3,
        GIR_Copy, /*NewInsnID*/1, /*OldInsnID*/0, /*OpIdx*/3, // voffset
        GIR_AddImm8, /*InsnID*/1, /*SubRegIndex*/11,
        GIR_ConstrainOperandRC, /*InsnID*/1, /*Op*/0, GIMT_Encode2(AMDGPU::VReg_64RegClassID),
        GIR_ConstrainOperandRC, /*InsnID*/1, /*Op*/1, GIMT_Encode2(AMDGPU::VGPR_32RegClassID),
        GIR_ConstrainOperandRC, /*InsnID*/1, /*Op*/3, GIMT_Encode2(AMDGPU::VGPR_32RegClassID),
        GIR_BuildMI, /*InsnID*/0, /*Opcode*/GIMT_Encode2(AMDGPU::TBUFFER_LOAD_FORMAT_X_BOTHEN),
        GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/0, // DstI[vdata]
        GIR_AddSimpleTempRegister, /*InsnID*/0, /*TempRegID*/0,
        GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/1, // rsrc
        GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/0, // soffset
        GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/5, // offset
        GIR_CustomOperandRenderer, /*InsnID*/0, /*OldInsnID*/0, /*OpIdx*/6, /*OperandRenderer*/GIMT_Encode2(GICR_renderTruncTImm), // format
        GIR_CustomOperandRenderer, /*InsnID*/0, /*OldInsnID*/0, /*OpIdx*/7, /*OperandRenderer*/GIMT_Encode2(GICR_renderExtractCPol), // auxiliary
        GIR_CustomOperandRenderer, /*InsnID*/0, /*OldInsnID*/0, /*OpIdx*/7, /*OperandRenderer*/GIMT_Encode2(GICR_renderExtractSWZ), // auxiliary
        GIR_MergeMemOperands, /*InsnID*/0, /*NumInsns*/1, /*MergeInsnID's*/0,
        GIR_ConstrainSelectedInstOperands, /*InsnID*/0,
        GIR_EraseFromParent, /*InsnID*/0,
        // GIR_Coverage, 5572,
        GIR_Done,
      // Label 7228: @526753
      GIM_Try, /*On fail goto*//*Label 7229*/ GIMT_Encode4(526869), // Rule ID 5576 //
        // MIs[0] offset
        GIM_CheckIsImm, /*MI*/0, /*Op*/5,
        // MIs[0] format
        GIM_CheckIsImm, /*MI*/0, /*Op*/6,
        // MIs[0] auxiliary
        GIM_CheckIsImm, /*MI*/0, /*Op*/7,
        // MIs[0] Operand 8
        GIM_CheckIsImm, /*MI*/0, /*Op*/8,
        GIM_CheckComplexPattern, /*MI*/0, /*Op*/4, /*Renderer*/GIMT_Encode2(0), GIMT_Encode2(GICP_gi_buf_soffset),
        // (SItbuffer_load:{ *:[i32] } v4i32:{ *:[v4i32] }:$rsrc, i32:{ *:[i32] }:$vindex, i32:{ *:[i32] }:$voffset, (BUFSOffset:{ *:[i32] } i32:{ *:[i32] }:$soffset), (timm:{ *:[i32] }):$offset, (timm:{ *:[i32] }):$format, (timm:{ *:[i32] }):$auxiliary, (timm:{ *:[i1] }))  =>  (TBUFFER_LOAD_FORMAT_X_VBUFFER_BOTHEN:{ *:[i32] } (REG_SEQUENCE:{ *:[i64] } VReg_64:{ *:[i32] }, VGPR_32:{ *:[i32] }:$vindex, sub0:{ *:[i32] }, VGPR_32:{ *:[i32] }:$voffset, sub1:{ *:[i32] }), SReg_128:{ *:[v4i32] }:$rsrc, SCSrc_b32:{ *:[i32] }:$soffset, (timm:{ *:[i32] }):$offset, (as_i8timm:{ *:[i8] } ?:{ *:[i32] }:$format), (extract_cpol:{ *:[i32] } ?:{ *:[i32] }:$auxiliary), (extract_swz:{ *:[i1] } ?:{ *:[i32] }:$auxiliary))
        GIR_MakeTempReg, /*TempRegID*/0, /*TypeID*/GILLT_s64,
        GIR_BuildMI, /*InsnID*/1, /*Opcode*/GIMT_Encode2(TargetOpcode::REG_SEQUENCE),
        GIR_AddTempRegister, /*InsnID*/1, /*TempRegID*/0, /*TempRegFlags*/GIMT_Encode2(RegState::Define),
        GIR_Copy, /*NewInsnID*/1, /*OldInsnID*/0, /*OpIdx*/2, // vindex
        GIR_AddImm8, /*InsnID*/1, /*SubRegIndex*/3,
        GIR_Copy, /*NewInsnID*/1, /*OldInsnID*/0, /*OpIdx*/3, // voffset
        GIR_AddImm8, /*InsnID*/1, /*SubRegIndex*/11,
        GIR_ConstrainOperandRC, /*InsnID*/1, /*Op*/0, GIMT_Encode2(AMDGPU::VReg_64RegClassID),
        GIR_ConstrainOperandRC, /*InsnID*/1, /*Op*/1, GIMT_Encode2(AMDGPU::VGPR_32RegClassID),
        GIR_ConstrainOperandRC, /*InsnID*/1, /*Op*/3, GIMT_Encode2(AMDGPU::VGPR_32RegClassID),
        GIR_BuildMI, /*InsnID*/0, /*Opcode*/GIMT_Encode2(AMDGPU::TBUFFER_LOAD_FORMAT_X_VBUFFER_BOTHEN),
        GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/0, // DstI[vdata]
        GIR_AddSimpleTempRegister, /*InsnID*/0, /*TempRegID*/0,
        GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/1, // rsrc
        GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/0, // soffset
        GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/5, // offset
        GIR_CustomOperandRenderer, /*InsnID*/0, /*OldInsnID*/0, /*OpIdx*/6, /*OperandRenderer*/GIMT_Encode2(GICR_renderTruncTImm), // format
        GIR_CustomOperandRenderer, /*InsnID*/0, /*OldInsnID*/0, /*OpIdx*/7, /*OperandRenderer*/GIMT_Encode2(GICR_renderExtractCPol), // auxiliary
        GIR_CustomOperandRenderer, /*InsnID*/0, /*OldInsnID*/0, /*OpIdx*/7, /*OperandRenderer*/GIMT_Encode2(GICR_renderExtractSWZ), // auxiliary
        GIR_MergeMemOperands, /*InsnID*/0, /*NumInsns*/1, /*MergeInsnID's*/0,
        GIR_ConstrainSelectedInstOperands, /*InsnID*/0,
        GIR_EraseFromParent, /*InsnID*/0,
        // GIR_Coverage, 5576,
        GIR_Done,
      // Label 7229: @526869
      GIM_Try, /*On fail goto*//*Label 7230*/ GIMT_Encode4(526988), // Rule ID 5604 //
        GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasUnrestrictedSOffset),
        // MIs[0] offset
        GIM_CheckIsImm, /*MI*/0, /*Op*/5,
        // MIs[0] format
        GIM_CheckIsImm, /*MI*/0, /*Op*/6,
        // MIs[0] auxiliary
        GIM_CheckIsImm, /*MI*/0, /*Op*/7,
        // MIs[0] Operand 8
        GIM_CheckIsImm, /*MI*/0, /*Op*/8,
        GIM_CheckComplexPattern, /*MI*/0, /*Op*/4, /*Renderer*/GIMT_Encode2(0), GIMT_Encode2(GICP_gi_buf_soffset),
        // (SItbuffer_load:{ *:[f32] } v4i32:{ *:[v4i32] }:$rsrc, i32:{ *:[i32] }:$vindex, i32:{ *:[i32] }:$voffset, (BUFSOffset:{ *:[i32] } i32:{ *:[i32] }:$soffset), (timm:{ *:[i32] }):$offset, (timm:{ *:[i32] }):$format, (timm:{ *:[i32] }):$auxiliary, (timm:{ *:[i1] }))  =>  (TBUFFER_LOAD_FORMAT_X_BOTHEN:{ *:[f32] } (REG_SEQUENCE:{ *:[i64] } VReg_64:{ *:[i32] }, VGPR_32:{ *:[i32] }:$vindex, sub0:{ *:[i32] }, VGPR_32:{ *:[i32] }:$voffset, sub1:{ *:[i32] }), SReg_128:{ *:[v4i32] }:$rsrc, SCSrc_b32:{ *:[i32] }:$soffset, (timm:{ *:[i32] }):$offset, (as_i8timm:{ *:[i8] } ?:{ *:[i32] }:$format), (extract_cpol:{ *:[i32] } ?:{ *:[i32] }:$auxiliary), (extract_swz:{ *:[i1] } ?:{ *:[i32] }:$auxiliary))
        GIR_MakeTempReg, /*TempRegID*/0, /*TypeID*/GILLT_s64,
        GIR_BuildMI, /*InsnID*/1, /*Opcode*/GIMT_Encode2(TargetOpcode::REG_SEQUENCE),
        GIR_AddTempRegister, /*InsnID*/1, /*TempRegID*/0, /*TempRegFlags*/GIMT_Encode2(RegState::Define),
        GIR_Copy, /*NewInsnID*/1, /*OldInsnID*/0, /*OpIdx*/2, // vindex
        GIR_AddImm8, /*InsnID*/1, /*SubRegIndex*/3,
        GIR_Copy, /*NewInsnID*/1, /*OldInsnID*/0, /*OpIdx*/3, // voffset
        GIR_AddImm8, /*InsnID*/1, /*SubRegIndex*/11,
        GIR_ConstrainOperandRC, /*InsnID*/1, /*Op*/0, GIMT_Encode2(AMDGPU::VReg_64RegClassID),
        GIR_ConstrainOperandRC, /*InsnID*/1, /*Op*/1, GIMT_Encode2(AMDGPU::VGPR_32RegClassID),
        GIR_ConstrainOperandRC, /*InsnID*/1, /*Op*/3, GIMT_Encode2(AMDGPU::VGPR_32RegClassID),
        GIR_BuildMI, /*InsnID*/0, /*Opcode*/GIMT_Encode2(AMDGPU::TBUFFER_LOAD_FORMAT_X_BOTHEN),
        GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/0, // DstI[vdata]
        GIR_AddSimpleTempRegister, /*InsnID*/0, /*TempRegID*/0,
        GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/1, // rsrc
        GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/0, // soffset
        GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/5, // offset
        GIR_CustomOperandRenderer, /*InsnID*/0, /*OldInsnID*/0, /*OpIdx*/6, /*OperandRenderer*/GIMT_Encode2(GICR_renderTruncTImm), // format
        GIR_CustomOperandRenderer, /*InsnID*/0, /*OldInsnID*/0, /*OpIdx*/7, /*OperandRenderer*/GIMT_Encode2(GICR_renderExtractCPol), // auxiliary
        GIR_CustomOperandRenderer, /*InsnID*/0, /*OldInsnID*/0, /*OpIdx*/7, /*OperandRenderer*/GIMT_Encode2(GICR_renderExtractSWZ), // auxiliary
        GIR_MergeMemOperands, /*InsnID*/0, /*NumInsns*/1, /*MergeInsnID's*/0,
        GIR_ConstrainSelectedInstOperands, /*InsnID*/0,
        GIR_EraseFromParent, /*InsnID*/0,
        // GIR_Coverage, 5604,
        GIR_Done,
      // Label 7230: @526988
      GIM_Try, /*On fail goto*//*Label 7231*/ GIMT_Encode4(527104), // Rule ID 5608 //
        // MIs[0] offset
        GIM_CheckIsImm, /*MI*/0, /*Op*/5,
        // MIs[0] format
        GIM_CheckIsImm, /*MI*/0, /*Op*/6,
        // MIs[0] auxiliary
        GIM_CheckIsImm, /*MI*/0, /*Op*/7,
        // MIs[0] Operand 8
        GIM_CheckIsImm, /*MI*/0, /*Op*/8,
        GIM_CheckComplexPattern, /*MI*/0, /*Op*/4, /*Renderer*/GIMT_Encode2(0), GIMT_Encode2(GICP_gi_buf_soffset),
        // (SItbuffer_load:{ *:[f32] } v4i32:{ *:[v4i32] }:$rsrc, i32:{ *:[i32] }:$vindex, i32:{ *:[i32] }:$voffset, (BUFSOffset:{ *:[i32] } i32:{ *:[i32] }:$soffset), (timm:{ *:[i32] }):$offset, (timm:{ *:[i32] }):$format, (timm:{ *:[i32] }):$auxiliary, (timm:{ *:[i1] }))  =>  (TBUFFER_LOAD_FORMAT_X_VBUFFER_BOTHEN:{ *:[f32] } (REG_SEQUENCE:{ *:[i64] } VReg_64:{ *:[i32] }, VGPR_32:{ *:[i32] }:$vindex, sub0:{ *:[i32] }, VGPR_32:{ *:[i32] }:$voffset, sub1:{ *:[i32] }), SReg_128:{ *:[v4i32] }:$rsrc, SCSrc_b32:{ *:[i32] }:$soffset, (timm:{ *:[i32] }):$offset, (as_i8timm:{ *:[i8] } ?:{ *:[i32] }:$format), (extract_cpol:{ *:[i32] } ?:{ *:[i32] }:$auxiliary), (extract_swz:{ *:[i1] } ?:{ *:[i32] }:$auxiliary))
        GIR_MakeTempReg, /*TempRegID*/0, /*TypeID*/GILLT_s64,
        GIR_BuildMI, /*InsnID*/1, /*Opcode*/GIMT_Encode2(TargetOpcode::REG_SEQUENCE),
        GIR_AddTempRegister, /*InsnID*/1, /*TempRegID*/0, /*TempRegFlags*/GIMT_Encode2(RegState::Define),
        GIR_Copy, /*NewInsnID*/1, /*OldInsnID*/0, /*OpIdx*/2, // vindex
        GIR_AddImm8, /*InsnID*/1, /*SubRegIndex*/3,
        GIR_Copy, /*NewInsnID*/1, /*OldInsnID*/0, /*OpIdx*/3, // voffset
        GIR_AddImm8, /*InsnID*/1, /*SubRegIndex*/11,
        GIR_ConstrainOperandRC, /*InsnID*/1, /*Op*/0, GIMT_Encode2(AMDGPU::VReg_64RegClassID),
        GIR_ConstrainOperandRC, /*InsnID*/1, /*Op*/1, GIMT_Encode2(AMDGPU::VGPR_32RegClassID),
        GIR_ConstrainOperandRC, /*InsnID*/1, /*Op*/3, GIMT_Encode2(AMDGPU::VGPR_32RegClassID),
        GIR_BuildMI, /*InsnID*/0, /*Opcode*/GIMT_Encode2(AMDGPU::TBUFFER_LOAD_FORMAT_X_VBUFFER_BOTHEN),
        GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/0, // DstI[vdata]
        GIR_AddSimpleTempRegister, /*InsnID*/0, /*TempRegID*/0,
        GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/1, // rsrc
        GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/0, // soffset
        GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/5, // offset
        GIR_CustomOperandRenderer, /*InsnID*/0, /*OldInsnID*/0, /*OpIdx*/6, /*OperandRenderer*/GIMT_Encode2(GICR_renderTruncTImm), // format
        GIR_CustomOperandRenderer, /*InsnID*/0, /*OldInsnID*/0, /*OpIdx*/7, /*OperandRenderer*/GIMT_Encode2(GICR_renderExtractCPol), // auxiliary
        GIR_CustomOperandRenderer, /*InsnID*/0, /*OldInsnID*/0, /*OpIdx*/7, /*OperandRenderer*/GIMT_Encode2(GICR_renderExtractSWZ), // auxiliary
        GIR_MergeMemOperands, /*InsnID*/0, /*NumInsns*/1, /*MergeInsnID's*/0,
        GIR_ConstrainSelectedInstOperands, /*InsnID*/0,
        GIR_EraseFromParent, /*InsnID*/0,
        // GIR_Coverage, 5608,
        GIR_Done,
      // Label 7231: @527104
      GIM_Reject,
    // Label 7215: @527105
    GIM_Reject,
    // Label 7211: @527106
    GIM_Try, /*On fail goto*//*Label 7232*/ GIMT_Encode4(528645),
      GIM_CheckType, /*MI*/0, /*Op*/1, /*Type*/GILLT_v4s32,
      GIM_CheckType, /*MI*/0, /*Op*/2, /*Type*/GILLT_s32,
      GIM_CheckType, /*MI*/0, /*Op*/3, /*Type*/GILLT_s32,
      GIM_CheckType, /*MI*/0, /*Op*/4, /*Type*/GILLT_s32,
      GIM_CheckRegBankForClass, /*MI*/0, /*Op*/0, /*RC*/GIMT_Encode2(AMDGPU::AV_64RegClassID),
      GIM_Try, /*On fail goto*//*Label 7233*/ GIMT_Encode4(527223), // Rule ID 5577 //
        GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasUnrestrictedSOffset),
        GIM_CheckConstantInt8, /*MI*/0, /*Op*/2, 0,
        GIM_CheckConstantInt8, /*MI*/0, /*Op*/3, 0,
        // MIs[0] offset
        GIM_CheckIsImm, /*MI*/0, /*Op*/5,
        // MIs[0] format
        GIM_CheckIsImm, /*MI*/0, /*Op*/6,
        // MIs[0] auxiliary
        GIM_CheckIsImm, /*MI*/0, /*Op*/7,
        // MIs[0] Operand 8
        GIM_CheckLiteralInt, /*MI*/0, /*Op*/8, GIMT_Encode8(0),
        GIM_CheckComplexPattern, /*MI*/0, /*Op*/4, /*Renderer*/GIMT_Encode2(0), GIMT_Encode2(GICP_gi_buf_soffset),
        // (SItbuffer_load:{ *:[v2i32] } v4i32:{ *:[v4i32] }:$rsrc, 0:{ *:[i32] }, 0:{ *:[i32] }, (BUFSOffset:{ *:[i32] } i32:{ *:[i32] }:$soffset), (timm:{ *:[i32] }):$offset, (timm:{ *:[i32] }):$format, (timm:{ *:[i32] }):$auxiliary, 0:{ *:[i1] })  =>  (TBUFFER_LOAD_FORMAT_XY_OFFSET:{ *:[v2i32] } SReg_128:{ *:[v4i32] }:$rsrc, SCSrc_b32:{ *:[i32] }:$soffset, (timm:{ *:[i32] }):$offset, (as_i8timm:{ *:[i8] } ?:{ *:[i32] }:$format), (extract_cpol:{ *:[i32] } ?:{ *:[i32] }:$auxiliary), (extract_swz:{ *:[i1] } ?:{ *:[i32] }:$auxiliary))
        GIR_BuildMI, /*InsnID*/0, /*Opcode*/GIMT_Encode2(AMDGPU::TBUFFER_LOAD_FORMAT_XY_OFFSET),
        GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/0, // DstI[vdata]
        GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/1, // rsrc
        GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/0, // soffset
        GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/5, // offset
        GIR_CustomOperandRenderer, /*InsnID*/0, /*OldInsnID*/0, /*OpIdx*/6, /*OperandRenderer*/GIMT_Encode2(GICR_renderTruncTImm), // format
        GIR_CustomOperandRenderer, /*InsnID*/0, /*OldInsnID*/0, /*OpIdx*/7, /*OperandRenderer*/GIMT_Encode2(GICR_renderExtractCPol), // auxiliary
        GIR_CustomOperandRenderer, /*InsnID*/0, /*OldInsnID*/0, /*OpIdx*/7, /*OperandRenderer*/GIMT_Encode2(GICR_renderExtractSWZ), // auxiliary
        GIR_MergeMemOperands, /*InsnID*/0, /*NumInsns*/1, /*MergeInsnID's*/0,
        GIR_ConstrainSelectedInstOperands, /*InsnID*/0,
        GIR_EraseFromParent, /*InsnID*/0,
        // GIR_Coverage, 5577,
        GIR_Done,
      // Label 7233: @527223
      GIM_Try, /*On fail goto*//*Label 7234*/ GIMT_Encode4(527311), // Rule ID 5581 //
        GIM_CheckConstantInt8, /*MI*/0, /*Op*/2, 0,
        GIM_CheckConstantInt8, /*MI*/0, /*Op*/3, 0,
        // MIs[0] offset
        GIM_CheckIsImm, /*MI*/0, /*Op*/5,
        // MIs[0] format
        GIM_CheckIsImm, /*MI*/0, /*Op*/6,
        // MIs[0] auxiliary
        GIM_CheckIsImm, /*MI*/0, /*Op*/7,
        // MIs[0] Operand 8
        GIM_CheckLiteralInt, /*MI*/0, /*Op*/8, GIMT_Encode8(0),
        GIM_CheckComplexPattern, /*MI*/0, /*Op*/4, /*Renderer*/GIMT_Encode2(0), GIMT_Encode2(GICP_gi_buf_soffset),
        // (SItbuffer_load:{ *:[v2i32] } v4i32:{ *:[v4i32] }:$rsrc, 0:{ *:[i32] }, 0:{ *:[i32] }, (BUFSOffset:{ *:[i32] } i32:{ *:[i32] }:$soffset), (timm:{ *:[i32] }):$offset, (timm:{ *:[i32] }):$format, (timm:{ *:[i32] }):$auxiliary, 0:{ *:[i1] })  =>  (TBUFFER_LOAD_FORMAT_XY_VBUFFER_OFFSET:{ *:[v2i32] } SReg_128:{ *:[v4i32] }:$rsrc, SCSrc_b32:{ *:[i32] }:$soffset, (timm:{ *:[i32] }):$offset, (as_i8timm:{ *:[i8] } ?:{ *:[i32] }:$format), (extract_cpol:{ *:[i32] } ?:{ *:[i32] }:$auxiliary), (extract_swz:{ *:[i1] } ?:{ *:[i32] }:$auxiliary))
        GIR_BuildMI, /*InsnID*/0, /*Opcode*/GIMT_Encode2(AMDGPU::TBUFFER_LOAD_FORMAT_XY_VBUFFER_OFFSET),
        GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/0, // DstI[vdata]
        GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/1, // rsrc
        GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/0, // soffset
        GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/5, // offset
        GIR_CustomOperandRenderer, /*InsnID*/0, /*OldInsnID*/0, /*OpIdx*/6, /*OperandRenderer*/GIMT_Encode2(GICR_renderTruncTImm), // format
        GIR_CustomOperandRenderer, /*InsnID*/0, /*OldInsnID*/0, /*OpIdx*/7, /*OperandRenderer*/GIMT_Encode2(GICR_renderExtractCPol), // auxiliary
        GIR_CustomOperandRenderer, /*InsnID*/0, /*OldInsnID*/0, /*OpIdx*/7, /*OperandRenderer*/GIMT_Encode2(GICR_renderExtractSWZ), // auxiliary
        GIR_MergeMemOperands, /*InsnID*/0, /*NumInsns*/1, /*MergeInsnID's*/0,
        GIR_ConstrainSelectedInstOperands, /*InsnID*/0,
        GIR_EraseFromParent, /*InsnID*/0,
        // GIR_Coverage, 5581,
        GIR_Done,
      // Label 7234: @527311
      GIM_Try, /*On fail goto*//*Label 7235*/ GIMT_Encode4(527402), // Rule ID 5609 //
        GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasUnrestrictedSOffset),
        GIM_CheckConstantInt8, /*MI*/0, /*Op*/2, 0,
        GIM_CheckConstantInt8, /*MI*/0, /*Op*/3, 0,
        // MIs[0] offset
        GIM_CheckIsImm, /*MI*/0, /*Op*/5,
        // MIs[0] format
        GIM_CheckIsImm, /*MI*/0, /*Op*/6,
        // MIs[0] auxiliary
        GIM_CheckIsImm, /*MI*/0, /*Op*/7,
        // MIs[0] Operand 8
        GIM_CheckLiteralInt, /*MI*/0, /*Op*/8, GIMT_Encode8(0),
        GIM_CheckComplexPattern, /*MI*/0, /*Op*/4, /*Renderer*/GIMT_Encode2(0), GIMT_Encode2(GICP_gi_buf_soffset),
        // (SItbuffer_load:{ *:[v2f32] } v4i32:{ *:[v4i32] }:$rsrc, 0:{ *:[i32] }, 0:{ *:[i32] }, (BUFSOffset:{ *:[i32] } i32:{ *:[i32] }:$soffset), (timm:{ *:[i32] }):$offset, (timm:{ *:[i32] }):$format, (timm:{ *:[i32] }):$auxiliary, 0:{ *:[i1] })  =>  (TBUFFER_LOAD_FORMAT_XY_OFFSET:{ *:[v2f32] } SReg_128:{ *:[v4i32] }:$rsrc, SCSrc_b32:{ *:[i32] }:$soffset, (timm:{ *:[i32] }):$offset, (as_i8timm:{ *:[i8] } ?:{ *:[i32] }:$format), (extract_cpol:{ *:[i32] } ?:{ *:[i32] }:$auxiliary), (extract_swz:{ *:[i1] } ?:{ *:[i32] }:$auxiliary))
        GIR_BuildMI, /*InsnID*/0, /*Opcode*/GIMT_Encode2(AMDGPU::TBUFFER_LOAD_FORMAT_XY_OFFSET),
        GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/0, // DstI[vdata]
        GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/1, // rsrc
        GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/0, // soffset
        GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/5, // offset
        GIR_CustomOperandRenderer, /*InsnID*/0, /*OldInsnID*/0, /*OpIdx*/6, /*OperandRenderer*/GIMT_Encode2(GICR_renderTruncTImm), // format
        GIR_CustomOperandRenderer, /*InsnID*/0, /*OldInsnID*/0, /*OpIdx*/7, /*OperandRenderer*/GIMT_Encode2(GICR_renderExtractCPol), // auxiliary
        GIR_CustomOperandRenderer, /*InsnID*/0, /*OldInsnID*/0, /*OpIdx*/7, /*OperandRenderer*/GIMT_Encode2(GICR_renderExtractSWZ), // auxiliary
        GIR_MergeMemOperands, /*InsnID*/0, /*NumInsns*/1, /*MergeInsnID's*/0,
        GIR_ConstrainSelectedInstOperands, /*InsnID*/0,
        GIR_EraseFromParent, /*InsnID*/0,
        // GIR_Coverage, 5609,
        GIR_Done,
      // Label 7235: @527402
      GIM_Try, /*On fail goto*//*Label 7236*/ GIMT_Encode4(527490), // Rule ID 5613 //
        GIM_CheckConstantInt8, /*MI*/0, /*Op*/2, 0,
        GIM_CheckConstantInt8, /*MI*/0, /*Op*/3, 0,
        // MIs[0] offset
        GIM_CheckIsImm, /*MI*/0, /*Op*/5,
        // MIs[0] format
        GIM_CheckIsImm, /*MI*/0, /*Op*/6,
        // MIs[0] auxiliary
        GIM_CheckIsImm, /*MI*/0, /*Op*/7,
        // MIs[0] Operand 8
        GIM_CheckLiteralInt, /*MI*/0, /*Op*/8, GIMT_Encode8(0),
        GIM_CheckComplexPattern, /*MI*/0, /*Op*/4, /*Renderer*/GIMT_Encode2(0), GIMT_Encode2(GICP_gi_buf_soffset),
        // (SItbuffer_load:{ *:[v2f32] } v4i32:{ *:[v4i32] }:$rsrc, 0:{ *:[i32] }, 0:{ *:[i32] }, (BUFSOffset:{ *:[i32] } i32:{ *:[i32] }:$soffset), (timm:{ *:[i32] }):$offset, (timm:{ *:[i32] }):$format, (timm:{ *:[i32] }):$auxiliary, 0:{ *:[i1] })  =>  (TBUFFER_LOAD_FORMAT_XY_VBUFFER_OFFSET:{ *:[v2f32] } SReg_128:{ *:[v4i32] }:$rsrc, SCSrc_b32:{ *:[i32] }:$soffset, (timm:{ *:[i32] }):$offset, (as_i8timm:{ *:[i8] } ?:{ *:[i32] }:$format), (extract_cpol:{ *:[i32] } ?:{ *:[i32] }:$auxiliary), (extract_swz:{ *:[i1] } ?:{ *:[i32] }:$auxiliary))
        GIR_BuildMI, /*InsnID*/0, /*Opcode*/GIMT_Encode2(AMDGPU::TBUFFER_LOAD_FORMAT_XY_VBUFFER_OFFSET),
        GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/0, // DstI[vdata]
        GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/1, // rsrc
        GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/0, // soffset
        GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/5, // offset
        GIR_CustomOperandRenderer, /*InsnID*/0, /*OldInsnID*/0, /*OpIdx*/6, /*OperandRenderer*/GIMT_Encode2(GICR_renderTruncTImm), // format
        GIR_CustomOperandRenderer, /*InsnID*/0, /*OldInsnID*/0, /*OpIdx*/7, /*OperandRenderer*/GIMT_Encode2(GICR_renderExtractCPol), // auxiliary
        GIR_CustomOperandRenderer, /*InsnID*/0, /*OldInsnID*/0, /*OpIdx*/7, /*OperandRenderer*/GIMT_Encode2(GICR_renderExtractSWZ), // auxiliary
        GIR_MergeMemOperands, /*InsnID*/0, /*NumInsns*/1, /*MergeInsnID's*/0,
        GIR_ConstrainSelectedInstOperands, /*InsnID*/0,
        GIR_EraseFromParent, /*InsnID*/0,
        // GIR_Coverage, 5613,
        GIR_Done,
      // Label 7236: @527490
      GIM_Try, /*On fail goto*//*Label 7237*/ GIMT_Encode4(527581), // Rule ID 5579 //
        GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasUnrestrictedSOffset),
        GIM_CheckConstantInt8, /*MI*/0, /*Op*/2, 0,
        // MIs[0] offset
        GIM_CheckIsImm, /*MI*/0, /*Op*/5,
        // MIs[0] format
        GIM_CheckIsImm, /*MI*/0, /*Op*/6,
        // MIs[0] auxiliary
        GIM_CheckIsImm, /*MI*/0, /*Op*/7,
        // MIs[0] Operand 8
        GIM_CheckLiteralInt, /*MI*/0, /*Op*/8, GIMT_Encode8(0),
        GIM_CheckComplexPattern, /*MI*/0, /*Op*/4, /*Renderer*/GIMT_Encode2(0), GIMT_Encode2(GICP_gi_buf_soffset),
        // (SItbuffer_load:{ *:[v2i32] } v4i32:{ *:[v4i32] }:$rsrc, 0:{ *:[i32] }, i32:{ *:[i32] }:$voffset, (BUFSOffset:{ *:[i32] } i32:{ *:[i32] }:$soffset), (timm:{ *:[i32] }):$offset, (timm:{ *:[i32] }):$format, (timm:{ *:[i32] }):$auxiliary, 0:{ *:[i1] })  =>  (TBUFFER_LOAD_FORMAT_XY_OFFEN:{ *:[v2i32] } VGPR_32:{ *:[i32] }:$voffset, SReg_128:{ *:[v4i32] }:$rsrc, SCSrc_b32:{ *:[i32] }:$soffset, (timm:{ *:[i32] }):$offset, (as_i8timm:{ *:[i8] } ?:{ *:[i32] }:$format), (extract_cpol:{ *:[i32] } ?:{ *:[i32] }:$auxiliary), (extract_swz:{ *:[i1] } ?:{ *:[i32] }:$auxiliary))
        GIR_BuildMI, /*InsnID*/0, /*Opcode*/GIMT_Encode2(AMDGPU::TBUFFER_LOAD_FORMAT_XY_OFFEN),
        GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/0, // DstI[vdata]
        GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/3, // voffset
        GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/1, // rsrc
        GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/0, // soffset
        GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/5, // offset
        GIR_CustomOperandRenderer, /*InsnID*/0, /*OldInsnID*/0, /*OpIdx*/6, /*OperandRenderer*/GIMT_Encode2(GICR_renderTruncTImm), // format
        GIR_CustomOperandRenderer, /*InsnID*/0, /*OldInsnID*/0, /*OpIdx*/7, /*OperandRenderer*/GIMT_Encode2(GICR_renderExtractCPol), // auxiliary
        GIR_CustomOperandRenderer, /*InsnID*/0, /*OldInsnID*/0, /*OpIdx*/7, /*OperandRenderer*/GIMT_Encode2(GICR_renderExtractSWZ), // auxiliary
        GIR_MergeMemOperands, /*InsnID*/0, /*NumInsns*/1, /*MergeInsnID's*/0,
        GIR_ConstrainSelectedInstOperands, /*InsnID*/0,
        GIR_EraseFromParent, /*InsnID*/0,
        // GIR_Coverage, 5579,
        GIR_Done,
      // Label 7237: @527581
      GIM_Try, /*On fail goto*//*Label 7238*/ GIMT_Encode4(527669), // Rule ID 5583 //
        GIM_CheckConstantInt8, /*MI*/0, /*Op*/2, 0,
        // MIs[0] offset
        GIM_CheckIsImm, /*MI*/0, /*Op*/5,
        // MIs[0] format
        GIM_CheckIsImm, /*MI*/0, /*Op*/6,
        // MIs[0] auxiliary
        GIM_CheckIsImm, /*MI*/0, /*Op*/7,
        // MIs[0] Operand 8
        GIM_CheckLiteralInt, /*MI*/0, /*Op*/8, GIMT_Encode8(0),
        GIM_CheckComplexPattern, /*MI*/0, /*Op*/4, /*Renderer*/GIMT_Encode2(0), GIMT_Encode2(GICP_gi_buf_soffset),
        // (SItbuffer_load:{ *:[v2i32] } v4i32:{ *:[v4i32] }:$rsrc, 0:{ *:[i32] }, i32:{ *:[i32] }:$voffset, (BUFSOffset:{ *:[i32] } i32:{ *:[i32] }:$soffset), (timm:{ *:[i32] }):$offset, (timm:{ *:[i32] }):$format, (timm:{ *:[i32] }):$auxiliary, 0:{ *:[i1] })  =>  (TBUFFER_LOAD_FORMAT_XY_VBUFFER_OFFEN:{ *:[v2i32] } VGPR_32:{ *:[i32] }:$voffset, SReg_128:{ *:[v4i32] }:$rsrc, SCSrc_b32:{ *:[i32] }:$soffset, (timm:{ *:[i32] }):$offset, (as_i8timm:{ *:[i8] } ?:{ *:[i32] }:$format), (extract_cpol:{ *:[i32] } ?:{ *:[i32] }:$auxiliary), (extract_swz:{ *:[i1] } ?:{ *:[i32] }:$auxiliary))
        GIR_BuildMI, /*InsnID*/0, /*Opcode*/GIMT_Encode2(AMDGPU::TBUFFER_LOAD_FORMAT_XY_VBUFFER_OFFEN),
        GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/0, // DstI[vdata]
        GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/3, // voffset
        GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/1, // rsrc
        GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/0, // soffset
        GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/5, // offset
        GIR_CustomOperandRenderer, /*InsnID*/0, /*OldInsnID*/0, /*OpIdx*/6, /*OperandRenderer*/GIMT_Encode2(GICR_renderTruncTImm), // format
        GIR_CustomOperandRenderer, /*InsnID*/0, /*OldInsnID*/0, /*OpIdx*/7, /*OperandRenderer*/GIMT_Encode2(GICR_renderExtractCPol), // auxiliary
        GIR_CustomOperandRenderer, /*InsnID*/0, /*OldInsnID*/0, /*OpIdx*/7, /*OperandRenderer*/GIMT_Encode2(GICR_renderExtractSWZ), // auxiliary
        GIR_MergeMemOperands, /*InsnID*/0, /*NumInsns*/1, /*MergeInsnID's*/0,
        GIR_ConstrainSelectedInstOperands, /*InsnID*/0,
        GIR_EraseFromParent, /*InsnID*/0,
        // GIR_Coverage, 5583,
        GIR_Done,
      // Label 7238: @527669
      GIM_Try, /*On fail goto*//*Label 7239*/ GIMT_Encode4(527760), // Rule ID 5611 //
        GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasUnrestrictedSOffset),
        GIM_CheckConstantInt8, /*MI*/0, /*Op*/2, 0,
        // MIs[0] offset
        GIM_CheckIsImm, /*MI*/0, /*Op*/5,
        // MIs[0] format
        GIM_CheckIsImm, /*MI*/0, /*Op*/6,
        // MIs[0] auxiliary
        GIM_CheckIsImm, /*MI*/0, /*Op*/7,
        // MIs[0] Operand 8
        GIM_CheckLiteralInt, /*MI*/0, /*Op*/8, GIMT_Encode8(0),
        GIM_CheckComplexPattern, /*MI*/0, /*Op*/4, /*Renderer*/GIMT_Encode2(0), GIMT_Encode2(GICP_gi_buf_soffset),
        // (SItbuffer_load:{ *:[v2f32] } v4i32:{ *:[v4i32] }:$rsrc, 0:{ *:[i32] }, i32:{ *:[i32] }:$voffset, (BUFSOffset:{ *:[i32] } i32:{ *:[i32] }:$soffset), (timm:{ *:[i32] }):$offset, (timm:{ *:[i32] }):$format, (timm:{ *:[i32] }):$auxiliary, 0:{ *:[i1] })  =>  (TBUFFER_LOAD_FORMAT_XY_OFFEN:{ *:[v2f32] } VGPR_32:{ *:[i32] }:$voffset, SReg_128:{ *:[v4i32] }:$rsrc, SCSrc_b32:{ *:[i32] }:$soffset, (timm:{ *:[i32] }):$offset, (as_i8timm:{ *:[i8] } ?:{ *:[i32] }:$format), (extract_cpol:{ *:[i32] } ?:{ *:[i32] }:$auxiliary), (extract_swz:{ *:[i1] } ?:{ *:[i32] }:$auxiliary))
        GIR_BuildMI, /*InsnID*/0, /*Opcode*/GIMT_Encode2(AMDGPU::TBUFFER_LOAD_FORMAT_XY_OFFEN),
        GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/0, // DstI[vdata]
        GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/3, // voffset
        GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/1, // rsrc
        GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/0, // soffset
        GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/5, // offset
        GIR_CustomOperandRenderer, /*InsnID*/0, /*OldInsnID*/0, /*OpIdx*/6, /*OperandRenderer*/GIMT_Encode2(GICR_renderTruncTImm), // format
        GIR_CustomOperandRenderer, /*InsnID*/0, /*OldInsnID*/0, /*OpIdx*/7, /*OperandRenderer*/GIMT_Encode2(GICR_renderExtractCPol), // auxiliary
        GIR_CustomOperandRenderer, /*InsnID*/0, /*OldInsnID*/0, /*OpIdx*/7, /*OperandRenderer*/GIMT_Encode2(GICR_renderExtractSWZ), // auxiliary
        GIR_MergeMemOperands, /*InsnID*/0, /*NumInsns*/1, /*MergeInsnID's*/0,
        GIR_ConstrainSelectedInstOperands, /*InsnID*/0,
        GIR_EraseFromParent, /*InsnID*/0,
        // GIR_Coverage, 5611,
        GIR_Done,
      // Label 7239: @527760
      GIM_Try, /*On fail goto*//*Label 7240*/ GIMT_Encode4(527848), // Rule ID 5615 //
        GIM_CheckConstantInt8, /*MI*/0, /*Op*/2, 0,
        // MIs[0] offset
        GIM_CheckIsImm, /*MI*/0, /*Op*/5,
        // MIs[0] format
        GIM_CheckIsImm, /*MI*/0, /*Op*/6,
        // MIs[0] auxiliary
        GIM_CheckIsImm, /*MI*/0, /*Op*/7,
        // MIs[0] Operand 8
        GIM_CheckLiteralInt, /*MI*/0, /*Op*/8, GIMT_Encode8(0),
        GIM_CheckComplexPattern, /*MI*/0, /*Op*/4, /*Renderer*/GIMT_Encode2(0), GIMT_Encode2(GICP_gi_buf_soffset),
        // (SItbuffer_load:{ *:[v2f32] } v4i32:{ *:[v4i32] }:$rsrc, 0:{ *:[i32] }, i32:{ *:[i32] }:$voffset, (BUFSOffset:{ *:[i32] } i32:{ *:[i32] }:$soffset), (timm:{ *:[i32] }):$offset, (timm:{ *:[i32] }):$format, (timm:{ *:[i32] }):$auxiliary, 0:{ *:[i1] })  =>  (TBUFFER_LOAD_FORMAT_XY_VBUFFER_OFFEN:{ *:[v2f32] } VGPR_32:{ *:[i32] }:$voffset, SReg_128:{ *:[v4i32] }:$rsrc, SCSrc_b32:{ *:[i32] }:$soffset, (timm:{ *:[i32] }):$offset, (as_i8timm:{ *:[i8] } ?:{ *:[i32] }:$format), (extract_cpol:{ *:[i32] } ?:{ *:[i32] }:$auxiliary), (extract_swz:{ *:[i1] } ?:{ *:[i32] }:$auxiliary))
        GIR_BuildMI, /*InsnID*/0, /*Opcode*/GIMT_Encode2(AMDGPU::TBUFFER_LOAD_FORMAT_XY_VBUFFER_OFFEN),
        GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/0, // DstI[vdata]
        GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/3, // voffset
        GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/1, // rsrc
        GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/0, // soffset
        GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/5, // offset
        GIR_CustomOperandRenderer, /*InsnID*/0, /*OldInsnID*/0, /*OpIdx*/6, /*OperandRenderer*/GIMT_Encode2(GICR_renderTruncTImm), // format
        GIR_CustomOperandRenderer, /*InsnID*/0, /*OldInsnID*/0, /*OpIdx*/7, /*OperandRenderer*/GIMT_Encode2(GICR_renderExtractCPol), // auxiliary
        GIR_CustomOperandRenderer, /*InsnID*/0, /*OldInsnID*/0, /*OpIdx*/7, /*OperandRenderer*/GIMT_Encode2(GICR_renderExtractSWZ), // auxiliary
        GIR_MergeMemOperands, /*InsnID*/0, /*NumInsns*/1, /*MergeInsnID's*/0,
        GIR_ConstrainSelectedInstOperands, /*InsnID*/0,
        GIR_EraseFromParent, /*InsnID*/0,
        // GIR_Coverage, 5615,
        GIR_Done,
      // Label 7240: @527848
      GIM_Try, /*On fail goto*//*Label 7241*/ GIMT_Encode4(527931), // Rule ID 5578 //
        GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasUnrestrictedSOffset),
        GIM_CheckConstantInt8, /*MI*/0, /*Op*/3, 0,
        // MIs[0] offset
        GIM_CheckIsImm, /*MI*/0, /*Op*/5,
        // MIs[0] format
        GIM_CheckIsImm, /*MI*/0, /*Op*/6,
        // MIs[0] auxiliary
        GIM_CheckIsImm, /*MI*/0, /*Op*/7,
        // MIs[0] Operand 8
        GIM_CheckIsImm, /*MI*/0, /*Op*/8,
        GIM_CheckComplexPattern, /*MI*/0, /*Op*/4, /*Renderer*/GIMT_Encode2(0), GIMT_Encode2(GICP_gi_buf_soffset),
        // (SItbuffer_load:{ *:[v2i32] } v4i32:{ *:[v4i32] }:$rsrc, i32:{ *:[i32] }:$vindex, 0:{ *:[i32] }, (BUFSOffset:{ *:[i32] } i32:{ *:[i32] }:$soffset), (timm:{ *:[i32] }):$offset, (timm:{ *:[i32] }):$format, (timm:{ *:[i32] }):$auxiliary, (timm:{ *:[i1] }))  =>  (TBUFFER_LOAD_FORMAT_XY_IDXEN:{ *:[v2i32] } VGPR_32:{ *:[i32] }:$vindex, SReg_128:{ *:[v4i32] }:$rsrc, SCSrc_b32:{ *:[i32] }:$soffset, (timm:{ *:[i32] }):$offset, (as_i8timm:{ *:[i8] } ?:{ *:[i32] }:$format), (extract_cpol:{ *:[i32] } ?:{ *:[i32] }:$auxiliary), (extract_swz:{ *:[i1] } ?:{ *:[i32] }:$auxiliary))
        GIR_BuildMI, /*InsnID*/0, /*Opcode*/GIMT_Encode2(AMDGPU::TBUFFER_LOAD_FORMAT_XY_IDXEN),
        GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/0, // DstI[vdata]
        GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/2, // vindex
        GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/1, // rsrc
        GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/0, // soffset
        GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/5, // offset
        GIR_CustomOperandRenderer, /*InsnID*/0, /*OldInsnID*/0, /*OpIdx*/6, /*OperandRenderer*/GIMT_Encode2(GICR_renderTruncTImm), // format
        GIR_CustomOperandRenderer, /*InsnID*/0, /*OldInsnID*/0, /*OpIdx*/7, /*OperandRenderer*/GIMT_Encode2(GICR_renderExtractCPol), // auxiliary
        GIR_CustomOperandRenderer, /*InsnID*/0, /*OldInsnID*/0, /*OpIdx*/7, /*OperandRenderer*/GIMT_Encode2(GICR_renderExtractSWZ), // auxiliary
        GIR_MergeMemOperands, /*InsnID*/0, /*NumInsns*/1, /*MergeInsnID's*/0,
        GIR_ConstrainSelectedInstOperands, /*InsnID*/0,
        GIR_EraseFromParent, /*InsnID*/0,
        // GIR_Coverage, 5578,
        GIR_Done,
      // Label 7241: @527931
      GIM_Try, /*On fail goto*//*Label 7242*/ GIMT_Encode4(528011), // Rule ID 5582 //
        GIM_CheckConstantInt8, /*MI*/0, /*Op*/3, 0,
        // MIs[0] offset
        GIM_CheckIsImm, /*MI*/0, /*Op*/5,
        // MIs[0] format
        GIM_CheckIsImm, /*MI*/0, /*Op*/6,
        // MIs[0] auxiliary
        GIM_CheckIsImm, /*MI*/0, /*Op*/7,
        // MIs[0] Operand 8
        GIM_CheckIsImm, /*MI*/0, /*Op*/8,
        GIM_CheckComplexPattern, /*MI*/0, /*Op*/4, /*Renderer*/GIMT_Encode2(0), GIMT_Encode2(GICP_gi_buf_soffset),
        // (SItbuffer_load:{ *:[v2i32] } v4i32:{ *:[v4i32] }:$rsrc, i32:{ *:[i32] }:$vindex, 0:{ *:[i32] }, (BUFSOffset:{ *:[i32] } i32:{ *:[i32] }:$soffset), (timm:{ *:[i32] }):$offset, (timm:{ *:[i32] }):$format, (timm:{ *:[i32] }):$auxiliary, (timm:{ *:[i1] }))  =>  (TBUFFER_LOAD_FORMAT_XY_VBUFFER_IDXEN:{ *:[v2i32] } VGPR_32:{ *:[i32] }:$vindex, SReg_128:{ *:[v4i32] }:$rsrc, SCSrc_b32:{ *:[i32] }:$soffset, (timm:{ *:[i32] }):$offset, (as_i8timm:{ *:[i8] } ?:{ *:[i32] }:$format), (extract_cpol:{ *:[i32] } ?:{ *:[i32] }:$auxiliary), (extract_swz:{ *:[i1] } ?:{ *:[i32] }:$auxiliary))
        GIR_BuildMI, /*InsnID*/0, /*Opcode*/GIMT_Encode2(AMDGPU::TBUFFER_LOAD_FORMAT_XY_VBUFFER_IDXEN),
        GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/0, // DstI[vdata]
        GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/2, // vindex
        GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/1, // rsrc
        GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/0, // soffset
        GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/5, // offset
        GIR_CustomOperandRenderer, /*InsnID*/0, /*OldInsnID*/0, /*OpIdx*/6, /*OperandRenderer*/GIMT_Encode2(GICR_renderTruncTImm), // format
        GIR_CustomOperandRenderer, /*InsnID*/0, /*OldInsnID*/0, /*OpIdx*/7, /*OperandRenderer*/GIMT_Encode2(GICR_renderExtractCPol), // auxiliary
        GIR_CustomOperandRenderer, /*InsnID*/0, /*OldInsnID*/0, /*OpIdx*/7, /*OperandRenderer*/GIMT_Encode2(GICR_renderExtractSWZ), // auxiliary
        GIR_MergeMemOperands, /*InsnID*/0, /*NumInsns*/1, /*MergeInsnID's*/0,
        GIR_ConstrainSelectedInstOperands, /*InsnID*/0,
        GIR_EraseFromParent, /*InsnID*/0,
        // GIR_Coverage, 5582,
        GIR_Done,
      // Label 7242: @528011
      GIM_Try, /*On fail goto*//*Label 7243*/ GIMT_Encode4(528094), // Rule ID 5610 //
        GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasUnrestrictedSOffset),
        GIM_CheckConstantInt8, /*MI*/0, /*Op*/3, 0,
        // MIs[0] offset
        GIM_CheckIsImm, /*MI*/0, /*Op*/5,
        // MIs[0] format
        GIM_CheckIsImm, /*MI*/0, /*Op*/6,
        // MIs[0] auxiliary
        GIM_CheckIsImm, /*MI*/0, /*Op*/7,
        // MIs[0] Operand 8
        GIM_CheckIsImm, /*MI*/0, /*Op*/8,
        GIM_CheckComplexPattern, /*MI*/0, /*Op*/4, /*Renderer*/GIMT_Encode2(0), GIMT_Encode2(GICP_gi_buf_soffset),
        // (SItbuffer_load:{ *:[v2f32] } v4i32:{ *:[v4i32] }:$rsrc, i32:{ *:[i32] }:$vindex, 0:{ *:[i32] }, (BUFSOffset:{ *:[i32] } i32:{ *:[i32] }:$soffset), (timm:{ *:[i32] }):$offset, (timm:{ *:[i32] }):$format, (timm:{ *:[i32] }):$auxiliary, (timm:{ *:[i1] }))  =>  (TBUFFER_LOAD_FORMAT_XY_IDXEN:{ *:[v2f32] } VGPR_32:{ *:[i32] }:$vindex, SReg_128:{ *:[v4i32] }:$rsrc, SCSrc_b32:{ *:[i32] }:$soffset, (timm:{ *:[i32] }):$offset, (as_i8timm:{ *:[i8] } ?:{ *:[i32] }:$format), (extract_cpol:{ *:[i32] } ?:{ *:[i32] }:$auxiliary), (extract_swz:{ *:[i1] } ?:{ *:[i32] }:$auxiliary))
        GIR_BuildMI, /*InsnID*/0, /*Opcode*/GIMT_Encode2(AMDGPU::TBUFFER_LOAD_FORMAT_XY_IDXEN),
        GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/0, // DstI[vdata]
        GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/2, // vindex
        GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/1, // rsrc
        GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/0, // soffset
        GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/5, // offset
        GIR_CustomOperandRenderer, /*InsnID*/0, /*OldInsnID*/0, /*OpIdx*/6, /*OperandRenderer*/GIMT_Encode2(GICR_renderTruncTImm), // format
        GIR_CustomOperandRenderer, /*InsnID*/0, /*OldInsnID*/0, /*OpIdx*/7, /*OperandRenderer*/GIMT_Encode2(GICR_renderExtractCPol), // auxiliary
        GIR_CustomOperandRenderer, /*InsnID*/0, /*OldInsnID*/0, /*OpIdx*/7, /*OperandRenderer*/GIMT_Encode2(GICR_renderExtractSWZ), // auxiliary
        GIR_MergeMemOperands, /*InsnID*/0, /*NumInsns*/1, /*MergeInsnID's*/0,
        GIR_ConstrainSelectedInstOperands, /*InsnID*/0,
        GIR_EraseFromParent, /*InsnID*/0,
        // GIR_Coverage, 5610,
        GIR_Done,
      // Label 7243: @528094
      GIM_Try, /*On fail goto*//*Label 7244*/ GIMT_Encode4(528174), // Rule ID 5614 //
        GIM_CheckConstantInt8, /*MI*/0, /*Op*/3, 0,
        // MIs[0] offset
        GIM_CheckIsImm, /*MI*/0, /*Op*/5,
        // MIs[0] format
        GIM_CheckIsImm, /*MI*/0, /*Op*/6,
        // MIs[0] auxiliary
        GIM_CheckIsImm, /*MI*/0, /*Op*/7,
        // MIs[0] Operand 8
        GIM_CheckIsImm, /*MI*/0, /*Op*/8,
        GIM_CheckComplexPattern, /*MI*/0, /*Op*/4, /*Renderer*/GIMT_Encode2(0), GIMT_Encode2(GICP_gi_buf_soffset),
        // (SItbuffer_load:{ *:[v2f32] } v4i32:{ *:[v4i32] }:$rsrc, i32:{ *:[i32] }:$vindex, 0:{ *:[i32] }, (BUFSOffset:{ *:[i32] } i32:{ *:[i32] }:$soffset), (timm:{ *:[i32] }):$offset, (timm:{ *:[i32] }):$format, (timm:{ *:[i32] }):$auxiliary, (timm:{ *:[i1] }))  =>  (TBUFFER_LOAD_FORMAT_XY_VBUFFER_IDXEN:{ *:[v2f32] } VGPR_32:{ *:[i32] }:$vindex, SReg_128:{ *:[v4i32] }:$rsrc, SCSrc_b32:{ *:[i32] }:$soffset, (timm:{ *:[i32] }):$offset, (as_i8timm:{ *:[i8] } ?:{ *:[i32] }:$format), (extract_cpol:{ *:[i32] } ?:{ *:[i32] }:$auxiliary), (extract_swz:{ *:[i1] } ?:{ *:[i32] }:$auxiliary))
        GIR_BuildMI, /*InsnID*/0, /*Opcode*/GIMT_Encode2(AMDGPU::TBUFFER_LOAD_FORMAT_XY_VBUFFER_IDXEN),
        GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/0, // DstI[vdata]
        GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/2, // vindex
        GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/1, // rsrc
        GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/0, // soffset
        GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/5, // offset
        GIR_CustomOperandRenderer, /*InsnID*/0, /*OldInsnID*/0, /*OpIdx*/6, /*OperandRenderer*/GIMT_Encode2(GICR_renderTruncTImm), // format
        GIR_CustomOperandRenderer, /*InsnID*/0, /*OldInsnID*/0, /*OpIdx*/7, /*OperandRenderer*/GIMT_Encode2(GICR_renderExtractCPol), // auxiliary
        GIR_CustomOperandRenderer, /*InsnID*/0, /*OldInsnID*/0, /*OpIdx*/7, /*OperandRenderer*/GIMT_Encode2(GICR_renderExtractSWZ), // auxiliary
        GIR_MergeMemOperands, /*InsnID*/0, /*NumInsns*/1, /*MergeInsnID's*/0,
        GIR_ConstrainSelectedInstOperands, /*InsnID*/0,
        GIR_EraseFromParent, /*InsnID*/0,
        // GIR_Coverage, 5614,
        GIR_Done,
      // Label 7244: @528174
      GIM_Try, /*On fail goto*//*Label 7245*/ GIMT_Encode4(528293), // Rule ID 5580 //
        GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasUnrestrictedSOffset),
        // MIs[0] offset
        GIM_CheckIsImm, /*MI*/0, /*Op*/5,
        // MIs[0] format
        GIM_CheckIsImm, /*MI*/0, /*Op*/6,
        // MIs[0] auxiliary
        GIM_CheckIsImm, /*MI*/0, /*Op*/7,
        // MIs[0] Operand 8
        GIM_CheckIsImm, /*MI*/0, /*Op*/8,
        GIM_CheckComplexPattern, /*MI*/0, /*Op*/4, /*Renderer*/GIMT_Encode2(0), GIMT_Encode2(GICP_gi_buf_soffset),
        // (SItbuffer_load:{ *:[v2i32] } v4i32:{ *:[v4i32] }:$rsrc, i32:{ *:[i32] }:$vindex, i32:{ *:[i32] }:$voffset, (BUFSOffset:{ *:[i32] } i32:{ *:[i32] }:$soffset), (timm:{ *:[i32] }):$offset, (timm:{ *:[i32] }):$format, (timm:{ *:[i32] }):$auxiliary, (timm:{ *:[i1] }))  =>  (TBUFFER_LOAD_FORMAT_XY_BOTHEN:{ *:[v2i32] } (REG_SEQUENCE:{ *:[i64] } VReg_64:{ *:[i32] }, VGPR_32:{ *:[i32] }:$vindex, sub0:{ *:[i32] }, VGPR_32:{ *:[i32] }:$voffset, sub1:{ *:[i32] }), SReg_128:{ *:[v4i32] }:$rsrc, SCSrc_b32:{ *:[i32] }:$soffset, (timm:{ *:[i32] }):$offset, (as_i8timm:{ *:[i8] } ?:{ *:[i32] }:$format), (extract_cpol:{ *:[i32] } ?:{ *:[i32] }:$auxiliary), (extract_swz:{ *:[i1] } ?:{ *:[i32] }:$auxiliary))
        GIR_MakeTempReg, /*TempRegID*/0, /*TypeID*/GILLT_s64,
        GIR_BuildMI, /*InsnID*/1, /*Opcode*/GIMT_Encode2(TargetOpcode::REG_SEQUENCE),
        GIR_AddTempRegister, /*InsnID*/1, /*TempRegID*/0, /*TempRegFlags*/GIMT_Encode2(RegState::Define),
        GIR_Copy, /*NewInsnID*/1, /*OldInsnID*/0, /*OpIdx*/2, // vindex
        GIR_AddImm8, /*InsnID*/1, /*SubRegIndex*/3,
        GIR_Copy, /*NewInsnID*/1, /*OldInsnID*/0, /*OpIdx*/3, // voffset
        GIR_AddImm8, /*InsnID*/1, /*SubRegIndex*/11,
        GIR_ConstrainOperandRC, /*InsnID*/1, /*Op*/0, GIMT_Encode2(AMDGPU::VReg_64RegClassID),
        GIR_ConstrainOperandRC, /*InsnID*/1, /*Op*/1, GIMT_Encode2(AMDGPU::VGPR_32RegClassID),
        GIR_ConstrainOperandRC, /*InsnID*/1, /*Op*/3, GIMT_Encode2(AMDGPU::VGPR_32RegClassID),
        GIR_BuildMI, /*InsnID*/0, /*Opcode*/GIMT_Encode2(AMDGPU::TBUFFER_LOAD_FORMAT_XY_BOTHEN),
        GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/0, // DstI[vdata]
        GIR_AddSimpleTempRegister, /*InsnID*/0, /*TempRegID*/0,
        GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/1, // rsrc
        GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/0, // soffset
        GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/5, // offset
        GIR_CustomOperandRenderer, /*InsnID*/0, /*OldInsnID*/0, /*OpIdx*/6, /*OperandRenderer*/GIMT_Encode2(GICR_renderTruncTImm), // format
        GIR_CustomOperandRenderer, /*InsnID*/0, /*OldInsnID*/0, /*OpIdx*/7, /*OperandRenderer*/GIMT_Encode2(GICR_renderExtractCPol), // auxiliary
        GIR_CustomOperandRenderer, /*InsnID*/0, /*OldInsnID*/0, /*OpIdx*/7, /*OperandRenderer*/GIMT_Encode2(GICR_renderExtractSWZ), // auxiliary
        GIR_MergeMemOperands, /*InsnID*/0, /*NumInsns*/1, /*MergeInsnID's*/0,
        GIR_ConstrainSelectedInstOperands, /*InsnID*/0,
        GIR_EraseFromParent, /*InsnID*/0,
        // GIR_Coverage, 5580,
        GIR_Done,
      // Label 7245: @528293
      GIM_Try, /*On fail goto*//*Label 7246*/ GIMT_Encode4(528409), // Rule ID 5584 //
        // MIs[0] offset
        GIM_CheckIsImm, /*MI*/0, /*Op*/5,
        // MIs[0] format
        GIM_CheckIsImm, /*MI*/0, /*Op*/6,
        // MIs[0] auxiliary
        GIM_CheckIsImm, /*MI*/0, /*Op*/7,
        // MIs[0] Operand 8
        GIM_CheckIsImm, /*MI*/0, /*Op*/8,
        GIM_CheckComplexPattern, /*MI*/0, /*Op*/4, /*Renderer*/GIMT_Encode2(0), GIMT_Encode2(GICP_gi_buf_soffset),
        // (SItbuffer_load:{ *:[v2i32] } v4i32:{ *:[v4i32] }:$rsrc, i32:{ *:[i32] }:$vindex, i32:{ *:[i32] }:$voffset, (BUFSOffset:{ *:[i32] } i32:{ *:[i32] }:$soffset), (timm:{ *:[i32] }):$offset, (timm:{ *:[i32] }):$format, (timm:{ *:[i32] }):$auxiliary, (timm:{ *:[i1] }))  =>  (TBUFFER_LOAD_FORMAT_XY_VBUFFER_BOTHEN:{ *:[v2i32] } (REG_SEQUENCE:{ *:[i64] } VReg_64:{ *:[i32] }, VGPR_32:{ *:[i32] }:$vindex, sub0:{ *:[i32] }, VGPR_32:{ *:[i32] }:$voffset, sub1:{ *:[i32] }), SReg_128:{ *:[v4i32] }:$rsrc, SCSrc_b32:{ *:[i32] }:$soffset, (timm:{ *:[i32] }):$offset, (as_i8timm:{ *:[i8] } ?:{ *:[i32] }:$format), (extract_cpol:{ *:[i32] } ?:{ *:[i32] }:$auxiliary), (extract_swz:{ *:[i1] } ?:{ *:[i32] }:$auxiliary))
        GIR_MakeTempReg, /*TempRegID*/0, /*TypeID*/GILLT_s64,
        GIR_BuildMI, /*InsnID*/1, /*Opcode*/GIMT_Encode2(TargetOpcode::REG_SEQUENCE),
        GIR_AddTempRegister, /*InsnID*/1, /*TempRegID*/0, /*TempRegFlags*/GIMT_Encode2(RegState::Define),
        GIR_Copy, /*NewInsnID*/1, /*OldInsnID*/0, /*OpIdx*/2, // vindex
        GIR_AddImm8, /*InsnID*/1, /*SubRegIndex*/3,
        GIR_Copy, /*NewInsnID*/1, /*OldInsnID*/0, /*OpIdx*/3, // voffset
        GIR_AddImm8, /*InsnID*/1, /*SubRegIndex*/11,
        GIR_ConstrainOperandRC, /*InsnID*/1, /*Op*/0, GIMT_Encode2(AMDGPU::VReg_64RegClassID),
        GIR_ConstrainOperandRC, /*InsnID*/1, /*Op*/1, GIMT_Encode2(AMDGPU::VGPR_32RegClassID),
        GIR_ConstrainOperandRC, /*InsnID*/1, /*Op*/3, GIMT_Encode2(AMDGPU::VGPR_32RegClassID),
        GIR_BuildMI, /*InsnID*/0, /*Opcode*/GIMT_Encode2(AMDGPU::TBUFFER_LOAD_FORMAT_XY_VBUFFER_BOTHEN),
        GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/0, // DstI[vdata]
        GIR_AddSimpleTempRegister, /*InsnID*/0, /*TempRegID*/0,
        GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/1, // rsrc
        GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/0, // soffset
        GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/5, // offset
        GIR_CustomOperandRenderer, /*InsnID*/0, /*OldInsnID*/0, /*OpIdx*/6, /*OperandRenderer*/GIMT_Encode2(GICR_renderTruncTImm), // format
        GIR_CustomOperandRenderer, /*InsnID*/0, /*OldInsnID*/0, /*OpIdx*/7, /*OperandRenderer*/GIMT_Encode2(GICR_renderExtractCPol), // auxiliary
        GIR_CustomOperandRenderer, /*InsnID*/0, /*OldInsnID*/0, /*OpIdx*/7, /*OperandRenderer*/GIMT_Encode2(GICR_renderExtractSWZ), // auxiliary
        GIR_MergeMemOperands, /*InsnID*/0, /*NumInsns*/1, /*MergeInsnID's*/0,
        GIR_ConstrainSelectedInstOperands, /*InsnID*/0,
        GIR_EraseFromParent, /*InsnID*/0,
        // GIR_Coverage, 5584,
        GIR_Done,
      // Label 7246: @528409
      GIM_Try, /*On fail goto*//*Label 7247*/ GIMT_Encode4(528528), // Rule ID 5612 //
        GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasUnrestrictedSOffset),
        // MIs[0] offset
        GIM_CheckIsImm, /*MI*/0, /*Op*/5,
        // MIs[0] format
        GIM_CheckIsImm, /*MI*/0, /*Op*/6,
        // MIs[0] auxiliary
        GIM_CheckIsImm, /*MI*/0, /*Op*/7,
        // MIs[0] Operand 8
        GIM_CheckIsImm, /*MI*/0, /*Op*/8,
        GIM_CheckComplexPattern, /*MI*/0, /*Op*/4, /*Renderer*/GIMT_Encode2(0), GIMT_Encode2(GICP_gi_buf_soffset),
        // (SItbuffer_load:{ *:[v2f32] } v4i32:{ *:[v4i32] }:$rsrc, i32:{ *:[i32] }:$vindex, i32:{ *:[i32] }:$voffset, (BUFSOffset:{ *:[i32] } i32:{ *:[i32] }:$soffset), (timm:{ *:[i32] }):$offset, (timm:{ *:[i32] }):$format, (timm:{ *:[i32] }):$auxiliary, (timm:{ *:[i1] }))  =>  (TBUFFER_LOAD_FORMAT_XY_BOTHEN:{ *:[v2f32] } (REG_SEQUENCE:{ *:[i64] } VReg_64:{ *:[i32] }, VGPR_32:{ *:[i32] }:$vindex, sub0:{ *:[i32] }, VGPR_32:{ *:[i32] }:$voffset, sub1:{ *:[i32] }), SReg_128:{ *:[v4i32] }:$rsrc, SCSrc_b32:{ *:[i32] }:$soffset, (timm:{ *:[i32] }):$offset, (as_i8timm:{ *:[i8] } ?:{ *:[i32] }:$format), (extract_cpol:{ *:[i32] } ?:{ *:[i32] }:$auxiliary), (extract_swz:{ *:[i1] } ?:{ *:[i32] }:$auxiliary))
        GIR_MakeTempReg, /*TempRegID*/0, /*TypeID*/GILLT_s64,
        GIR_BuildMI, /*InsnID*/1, /*Opcode*/GIMT_Encode2(TargetOpcode::REG_SEQUENCE),
        GIR_AddTempRegister, /*InsnID*/1, /*TempRegID*/0, /*TempRegFlags*/GIMT_Encode2(RegState::Define),
        GIR_Copy, /*NewInsnID*/1, /*OldInsnID*/0, /*OpIdx*/2, // vindex
        GIR_AddImm8, /*InsnID*/1, /*SubRegIndex*/3,
        GIR_Copy, /*NewInsnID*/1, /*OldInsnID*/0, /*OpIdx*/3, // voffset
        GIR_AddImm8, /*InsnID*/1, /*SubRegIndex*/11,
        GIR_ConstrainOperandRC, /*InsnID*/1, /*Op*/0, GIMT_Encode2(AMDGPU::VReg_64RegClassID),
        GIR_ConstrainOperandRC, /*InsnID*/1, /*Op*/1, GIMT_Encode2(AMDGPU::VGPR_32RegClassID),
        GIR_ConstrainOperandRC, /*InsnID*/1, /*Op*/3, GIMT_Encode2(AMDGPU::VGPR_32RegClassID),
        GIR_BuildMI, /*InsnID*/0, /*Opcode*/GIMT_Encode2(AMDGPU::TBUFFER_LOAD_FORMAT_XY_BOTHEN),
        GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/0, // DstI[vdata]
        GIR_AddSimpleTempRegister, /*InsnID*/0, /*TempRegID*/0,
        GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/1, // rsrc
        GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/0, // soffset
        GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/5, // offset
        GIR_CustomOperandRenderer, /*InsnID*/0, /*OldInsnID*/0, /*OpIdx*/6, /*OperandRenderer*/GIMT_Encode2(GICR_renderTruncTImm), // format
        GIR_CustomOperandRenderer, /*InsnID*/0, /*OldInsnID*/0, /*OpIdx*/7, /*OperandRenderer*/GIMT_Encode2(GICR_renderExtractCPol), // auxiliary
        GIR_CustomOperandRenderer, /*InsnID*/0, /*OldInsnID*/0, /*OpIdx*/7, /*OperandRenderer*/GIMT_Encode2(GICR_renderExtractSWZ), // auxiliary
        GIR_MergeMemOperands, /*InsnID*/0, /*NumInsns*/1, /*MergeInsnID's*/0,
        GIR_ConstrainSelectedInstOperands, /*InsnID*/0,
        GIR_EraseFromParent, /*InsnID*/0,
        // GIR_Coverage, 5612,
        GIR_Done,
      // Label 7247: @528528
      GIM_Try, /*On fail goto*//*Label 7248*/ GIMT_Encode4(528644), // Rule ID 5616 //
        // MIs[0] offset
        GIM_CheckIsImm, /*MI*/0, /*Op*/5,
        // MIs[0] format
        GIM_CheckIsImm, /*MI*/0, /*Op*/6,
        // MIs[0] auxiliary
        GIM_CheckIsImm, /*MI*/0, /*Op*/7,
        // MIs[0] Operand 8
        GIM_CheckIsImm, /*MI*/0, /*Op*/8,
        GIM_CheckComplexPattern, /*MI*/0, /*Op*/4, /*Renderer*/GIMT_Encode2(0), GIMT_Encode2(GICP_gi_buf_soffset),
        // (SItbuffer_load:{ *:[v2f32] } v4i32:{ *:[v4i32] }:$rsrc, i32:{ *:[i32] }:$vindex, i32:{ *:[i32] }:$voffset, (BUFSOffset:{ *:[i32] } i32:{ *:[i32] }:$soffset), (timm:{ *:[i32] }):$offset, (timm:{ *:[i32] }):$format, (timm:{ *:[i32] }):$auxiliary, (timm:{ *:[i1] }))  =>  (TBUFFER_LOAD_FORMAT_XY_VBUFFER_BOTHEN:{ *:[v2f32] } (REG_SEQUENCE:{ *:[i64] } VReg_64:{ *:[i32] }, VGPR_32:{ *:[i32] }:$vindex, sub0:{ *:[i32] }, VGPR_32:{ *:[i32] }:$voffset, sub1:{ *:[i32] }), SReg_128:{ *:[v4i32] }:$rsrc, SCSrc_b32:{ *:[i32] }:$soffset, (timm:{ *:[i32] }):$offset, (as_i8timm:{ *:[i8] } ?:{ *:[i32] }:$format), (extract_cpol:{ *:[i32] } ?:{ *:[i32] }:$auxiliary), (extract_swz:{ *:[i1] } ?:{ *:[i32] }:$auxiliary))
        GIR_MakeTempReg, /*TempRegID*/0, /*TypeID*/GILLT_s64,
        GIR_BuildMI, /*InsnID*/1, /*Opcode*/GIMT_Encode2(TargetOpcode::REG_SEQUENCE),
        GIR_AddTempRegister, /*InsnID*/1, /*TempRegID*/0, /*TempRegFlags*/GIMT_Encode2(RegState::Define),
        GIR_Copy, /*NewInsnID*/1, /*OldInsnID*/0, /*OpIdx*/2, // vindex
        GIR_AddImm8, /*InsnID*/1, /*SubRegIndex*/3,
        GIR_Copy, /*NewInsnID*/1, /*OldInsnID*/0, /*OpIdx*/3, // voffset
        GIR_AddImm8, /*InsnID*/1, /*SubRegIndex*/11,
        GIR_ConstrainOperandRC, /*InsnID*/1, /*Op*/0, GIMT_Encode2(AMDGPU::VReg_64RegClassID),
        GIR_ConstrainOperandRC, /*InsnID*/1, /*Op*/1, GIMT_Encode2(AMDGPU::VGPR_32RegClassID),
        GIR_ConstrainOperandRC, /*InsnID*/1, /*Op*/3, GIMT_Encode2(AMDGPU::VGPR_32RegClassID),
        GIR_BuildMI, /*InsnID*/0, /*Opcode*/GIMT_Encode2(AMDGPU::TBUFFER_LOAD_FORMAT_XY_VBUFFER_BOTHEN),
        GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/0, // DstI[vdata]
        GIR_AddSimpleTempRegister, /*InsnID*/0, /*TempRegID*/0,
        GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/1, // rsrc
        GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/0, // soffset
        GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/5, // offset
        GIR_CustomOperandRenderer, /*InsnID*/0, /*OldInsnID*/0, /*OpIdx*/6, /*OperandRenderer*/GIMT_Encode2(GICR_renderTruncTImm), // format
        GIR_CustomOperandRenderer, /*InsnID*/0, /*OldInsnID*/0, /*OpIdx*/7, /*OperandRenderer*/GIMT_Encode2(GICR_renderExtractCPol), // auxiliary
        GIR_CustomOperandRenderer, /*InsnID*/0, /*OldInsnID*/0, /*OpIdx*/7, /*OperandRenderer*/GIMT_Encode2(GICR_renderExtractSWZ), // auxiliary
        GIR_MergeMemOperands, /*InsnID*/0, /*NumInsns*/1, /*MergeInsnID's*/0,
        GIR_ConstrainSelectedInstOperands, /*InsnID*/0,
        GIR_EraseFromParent, /*InsnID*/0,
        // GIR_Coverage, 5616,
        GIR_Done,
      // Label 7248: @528644
      GIM_Reject,
    // Label 7232: @528645
    GIM_Reject,
    // Label 7212: @528646
    GIM_Try, /*On fail goto*//*Label 7249*/ GIMT_Encode4(530185),
      GIM_CheckType, /*MI*/0, /*Op*/1, /*Type*/GILLT_v4s32,
      GIM_CheckType, /*MI*/0, /*Op*/2, /*Type*/GILLT_s32,
      GIM_CheckType, /*MI*/0, /*Op*/3, /*Type*/GILLT_s32,
      GIM_CheckType, /*MI*/0, /*Op*/4, /*Type*/GILLT_s32,
      GIM_CheckRegBankForClass, /*MI*/0, /*Op*/0, /*RC*/GIMT_Encode2(AMDGPU::AV_96RegClassID),
      GIM_Try, /*On fail goto*//*Label 7250*/ GIMT_Encode4(528763), // Rule ID 5585 //
        GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasUnrestrictedSOffset),
        GIM_CheckConstantInt8, /*MI*/0, /*Op*/2, 0,
        GIM_CheckConstantInt8, /*MI*/0, /*Op*/3, 0,
        // MIs[0] offset
        GIM_CheckIsImm, /*MI*/0, /*Op*/5,
        // MIs[0] format
        GIM_CheckIsImm, /*MI*/0, /*Op*/6,
        // MIs[0] auxiliary
        GIM_CheckIsImm, /*MI*/0, /*Op*/7,
        // MIs[0] Operand 8
        GIM_CheckLiteralInt, /*MI*/0, /*Op*/8, GIMT_Encode8(0),
        GIM_CheckComplexPattern, /*MI*/0, /*Op*/4, /*Renderer*/GIMT_Encode2(0), GIMT_Encode2(GICP_gi_buf_soffset),
        // (SItbuffer_load:{ *:[v3i32] } v4i32:{ *:[v4i32] }:$rsrc, 0:{ *:[i32] }, 0:{ *:[i32] }, (BUFSOffset:{ *:[i32] } i32:{ *:[i32] }:$soffset), (timm:{ *:[i32] }):$offset, (timm:{ *:[i32] }):$format, (timm:{ *:[i32] }):$auxiliary, 0:{ *:[i1] })  =>  (TBUFFER_LOAD_FORMAT_XYZ_OFFSET:{ *:[v3i32] } SReg_128:{ *:[v4i32] }:$rsrc, SCSrc_b32:{ *:[i32] }:$soffset, (timm:{ *:[i32] }):$offset, (as_i8timm:{ *:[i8] } ?:{ *:[i32] }:$format), (extract_cpol:{ *:[i32] } ?:{ *:[i32] }:$auxiliary), (extract_swz:{ *:[i1] } ?:{ *:[i32] }:$auxiliary))
        GIR_BuildMI, /*InsnID*/0, /*Opcode*/GIMT_Encode2(AMDGPU::TBUFFER_LOAD_FORMAT_XYZ_OFFSET),
        GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/0, // DstI[vdata]
        GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/1, // rsrc
        GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/0, // soffset
        GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/5, // offset
        GIR_CustomOperandRenderer, /*InsnID*/0, /*OldInsnID*/0, /*OpIdx*/6, /*OperandRenderer*/GIMT_Encode2(GICR_renderTruncTImm), // format
        GIR_CustomOperandRenderer, /*InsnID*/0, /*OldInsnID*/0, /*OpIdx*/7, /*OperandRenderer*/GIMT_Encode2(GICR_renderExtractCPol), // auxiliary
        GIR_CustomOperandRenderer, /*InsnID*/0, /*OldInsnID*/0, /*OpIdx*/7, /*OperandRenderer*/GIMT_Encode2(GICR_renderExtractSWZ), // auxiliary
        GIR_MergeMemOperands, /*InsnID*/0, /*NumInsns*/1, /*MergeInsnID's*/0,
        GIR_ConstrainSelectedInstOperands, /*InsnID*/0,
        GIR_EraseFromParent, /*InsnID*/0,
        // GIR_Coverage, 5585,
        GIR_Done,
      // Label 7250: @528763
      GIM_Try, /*On fail goto*//*Label 7251*/ GIMT_Encode4(528851), // Rule ID 5589 //
        GIM_CheckConstantInt8, /*MI*/0, /*Op*/2, 0,
        GIM_CheckConstantInt8, /*MI*/0, /*Op*/3, 0,
        // MIs[0] offset
        GIM_CheckIsImm, /*MI*/0, /*Op*/5,
        // MIs[0] format
        GIM_CheckIsImm, /*MI*/0, /*Op*/6,
        // MIs[0] auxiliary
        GIM_CheckIsImm, /*MI*/0, /*Op*/7,
        // MIs[0] Operand 8
        GIM_CheckLiteralInt, /*MI*/0, /*Op*/8, GIMT_Encode8(0),
        GIM_CheckComplexPattern, /*MI*/0, /*Op*/4, /*Renderer*/GIMT_Encode2(0), GIMT_Encode2(GICP_gi_buf_soffset),
        // (SItbuffer_load:{ *:[v3i32] } v4i32:{ *:[v4i32] }:$rsrc, 0:{ *:[i32] }, 0:{ *:[i32] }, (BUFSOffset:{ *:[i32] } i32:{ *:[i32] }:$soffset), (timm:{ *:[i32] }):$offset, (timm:{ *:[i32] }):$format, (timm:{ *:[i32] }):$auxiliary, 0:{ *:[i1] })  =>  (TBUFFER_LOAD_FORMAT_XYZ_VBUFFER_OFFSET:{ *:[v3i32] } SReg_128:{ *:[v4i32] }:$rsrc, SCSrc_b32:{ *:[i32] }:$soffset, (timm:{ *:[i32] }):$offset, (as_i8timm:{ *:[i8] } ?:{ *:[i32] }:$format), (extract_cpol:{ *:[i32] } ?:{ *:[i32] }:$auxiliary), (extract_swz:{ *:[i1] } ?:{ *:[i32] }:$auxiliary))
        GIR_BuildMI, /*InsnID*/0, /*Opcode*/GIMT_Encode2(AMDGPU::TBUFFER_LOAD_FORMAT_XYZ_VBUFFER_OFFSET),
        GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/0, // DstI[vdata]
        GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/1, // rsrc
        GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/0, // soffset
        GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/5, // offset
        GIR_CustomOperandRenderer, /*InsnID*/0, /*OldInsnID*/0, /*OpIdx*/6, /*OperandRenderer*/GIMT_Encode2(GICR_renderTruncTImm), // format
        GIR_CustomOperandRenderer, /*InsnID*/0, /*OldInsnID*/0, /*OpIdx*/7, /*OperandRenderer*/GIMT_Encode2(GICR_renderExtractCPol), // auxiliary
        GIR_CustomOperandRenderer, /*InsnID*/0, /*OldInsnID*/0, /*OpIdx*/7, /*OperandRenderer*/GIMT_Encode2(GICR_renderExtractSWZ), // auxiliary
        GIR_MergeMemOperands, /*InsnID*/0, /*NumInsns*/1, /*MergeInsnID's*/0,
        GIR_ConstrainSelectedInstOperands, /*InsnID*/0,
        GIR_EraseFromParent, /*InsnID*/0,
        // GIR_Coverage, 5589,
        GIR_Done,
      // Label 7251: @528851
      GIM_Try, /*On fail goto*//*Label 7252*/ GIMT_Encode4(528942), // Rule ID 5617 //
        GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasUnrestrictedSOffset),
        GIM_CheckConstantInt8, /*MI*/0, /*Op*/2, 0,
        GIM_CheckConstantInt8, /*MI*/0, /*Op*/3, 0,
        // MIs[0] offset
        GIM_CheckIsImm, /*MI*/0, /*Op*/5,
        // MIs[0] format
        GIM_CheckIsImm, /*MI*/0, /*Op*/6,
        // MIs[0] auxiliary
        GIM_CheckIsImm, /*MI*/0, /*Op*/7,
        // MIs[0] Operand 8
        GIM_CheckLiteralInt, /*MI*/0, /*Op*/8, GIMT_Encode8(0),
        GIM_CheckComplexPattern, /*MI*/0, /*Op*/4, /*Renderer*/GIMT_Encode2(0), GIMT_Encode2(GICP_gi_buf_soffset),
        // (SItbuffer_load:{ *:[v3f32] } v4i32:{ *:[v4i32] }:$rsrc, 0:{ *:[i32] }, 0:{ *:[i32] }, (BUFSOffset:{ *:[i32] } i32:{ *:[i32] }:$soffset), (timm:{ *:[i32] }):$offset, (timm:{ *:[i32] }):$format, (timm:{ *:[i32] }):$auxiliary, 0:{ *:[i1] })  =>  (TBUFFER_LOAD_FORMAT_XYZ_OFFSET:{ *:[v3f32] } SReg_128:{ *:[v4i32] }:$rsrc, SCSrc_b32:{ *:[i32] }:$soffset, (timm:{ *:[i32] }):$offset, (as_i8timm:{ *:[i8] } ?:{ *:[i32] }:$format), (extract_cpol:{ *:[i32] } ?:{ *:[i32] }:$auxiliary), (extract_swz:{ *:[i1] } ?:{ *:[i32] }:$auxiliary))
        GIR_BuildMI, /*InsnID*/0, /*Opcode*/GIMT_Encode2(AMDGPU::TBUFFER_LOAD_FORMAT_XYZ_OFFSET),
        GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/0, // DstI[vdata]
        GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/1, // rsrc
        GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/0, // soffset
        GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/5, // offset
        GIR_CustomOperandRenderer, /*InsnID*/0, /*OldInsnID*/0, /*OpIdx*/6, /*OperandRenderer*/GIMT_Encode2(GICR_renderTruncTImm), // format
        GIR_CustomOperandRenderer, /*InsnID*/0, /*OldInsnID*/0, /*OpIdx*/7, /*OperandRenderer*/GIMT_Encode2(GICR_renderExtractCPol), // auxiliary
        GIR_CustomOperandRenderer, /*InsnID*/0, /*OldInsnID*/0, /*OpIdx*/7, /*OperandRenderer*/GIMT_Encode2(GICR_renderExtractSWZ), // auxiliary
        GIR_MergeMemOperands, /*InsnID*/0, /*NumInsns*/1, /*MergeInsnID's*/0,
        GIR_ConstrainSelectedInstOperands, /*InsnID*/0,
        GIR_EraseFromParent, /*InsnID*/0,
        // GIR_Coverage, 5617,
        GIR_Done,
      // Label 7252: @528942
      GIM_Try, /*On fail goto*//*Label 7253*/ GIMT_Encode4(529030), // Rule ID 5621 //
        GIM_CheckConstantInt8, /*MI*/0, /*Op*/2, 0,
        GIM_CheckConstantInt8, /*MI*/0, /*Op*/3, 0,
        // MIs[0] offset
        GIM_CheckIsImm, /*MI*/0, /*Op*/5,
        // MIs[0] format
        GIM_CheckIsImm, /*MI*/0, /*Op*/6,
        // MIs[0] auxiliary
        GIM_CheckIsImm, /*MI*/0, /*Op*/7,
        // MIs[0] Operand 8
        GIM_CheckLiteralInt, /*MI*/0, /*Op*/8, GIMT_Encode8(0),
        GIM_CheckComplexPattern, /*MI*/0, /*Op*/4, /*Renderer*/GIMT_Encode2(0), GIMT_Encode2(GICP_gi_buf_soffset),
        // (SItbuffer_load:{ *:[v3f32] } v4i32:{ *:[v4i32] }:$rsrc, 0:{ *:[i32] }, 0:{ *:[i32] }, (BUFSOffset:{ *:[i32] } i32:{ *:[i32] }:$soffset), (timm:{ *:[i32] }):$offset, (timm:{ *:[i32] }):$format, (timm:{ *:[i32] }):$auxiliary, 0:{ *:[i1] })  =>  (TBUFFER_LOAD_FORMAT_XYZ_VBUFFER_OFFSET:{ *:[v3f32] } SReg_128:{ *:[v4i32] }:$rsrc, SCSrc_b32:{ *:[i32] }:$soffset, (timm:{ *:[i32] }):$offset, (as_i8timm:{ *:[i8] } ?:{ *:[i32] }:$format), (extract_cpol:{ *:[i32] } ?:{ *:[i32] }:$auxiliary), (extract_swz:{ *:[i1] } ?:{ *:[i32] }:$auxiliary))
        GIR_BuildMI, /*InsnID*/0, /*Opcode*/GIMT_Encode2(AMDGPU::TBUFFER_LOAD_FORMAT_XYZ_VBUFFER_OFFSET),
        GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/0, // DstI[vdata]
        GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/1, // rsrc
        GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/0, // soffset
        GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/5, // offset
        GIR_CustomOperandRenderer, /*InsnID*/0, /*OldInsnID*/0, /*OpIdx*/6, /*OperandRenderer*/GIMT_Encode2(GICR_renderTruncTImm), // format
        GIR_CustomOperandRenderer, /*InsnID*/0, /*OldInsnID*/0, /*OpIdx*/7, /*OperandRenderer*/GIMT_Encode2(GICR_renderExtractCPol), // auxiliary
        GIR_CustomOperandRenderer, /*InsnID*/0, /*OldInsnID*/0, /*OpIdx*/7, /*OperandRenderer*/GIMT_Encode2(GICR_renderExtractSWZ), // auxiliary
        GIR_MergeMemOperands, /*InsnID*/0, /*NumInsns*/1, /*MergeInsnID's*/0,
        GIR_ConstrainSelectedInstOperands, /*InsnID*/0,
        GIR_EraseFromParent, /*InsnID*/0,
        // GIR_Coverage, 5621,
        GIR_Done,
      // Label 7253: @529030
      GIM_Try, /*On fail goto*//*Label 7254*/ GIMT_Encode4(529121), // Rule ID 5587 //
        GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasUnrestrictedSOffset),
        GIM_CheckConstantInt8, /*MI*/0, /*Op*/2, 0,
        // MIs[0] offset
        GIM_CheckIsImm, /*MI*/0, /*Op*/5,
        // MIs[0] format
        GIM_CheckIsImm, /*MI*/0, /*Op*/6,
        // MIs[0] auxiliary
        GIM_CheckIsImm, /*MI*/0, /*Op*/7,
        // MIs[0] Operand 8
        GIM_CheckLiteralInt, /*MI*/0, /*Op*/8, GIMT_Encode8(0),
        GIM_CheckComplexPattern, /*MI*/0, /*Op*/4, /*Renderer*/GIMT_Encode2(0), GIMT_Encode2(GICP_gi_buf_soffset),
        // (SItbuffer_load:{ *:[v3i32] } v4i32:{ *:[v4i32] }:$rsrc, 0:{ *:[i32] }, i32:{ *:[i32] }:$voffset, (BUFSOffset:{ *:[i32] } i32:{ *:[i32] }:$soffset), (timm:{ *:[i32] }):$offset, (timm:{ *:[i32] }):$format, (timm:{ *:[i32] }):$auxiliary, 0:{ *:[i1] })  =>  (TBUFFER_LOAD_FORMAT_XYZ_OFFEN:{ *:[v3i32] } VGPR_32:{ *:[i32] }:$voffset, SReg_128:{ *:[v4i32] }:$rsrc, SCSrc_b32:{ *:[i32] }:$soffset, (timm:{ *:[i32] }):$offset, (as_i8timm:{ *:[i8] } ?:{ *:[i32] }:$format), (extract_cpol:{ *:[i32] } ?:{ *:[i32] }:$auxiliary), (extract_swz:{ *:[i1] } ?:{ *:[i32] }:$auxiliary))
        GIR_BuildMI, /*InsnID*/0, /*Opcode*/GIMT_Encode2(AMDGPU::TBUFFER_LOAD_FORMAT_XYZ_OFFEN),
        GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/0, // DstI[vdata]
        GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/3, // voffset
        GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/1, // rsrc
        GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/0, // soffset
        GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/5, // offset
        GIR_CustomOperandRenderer, /*InsnID*/0, /*OldInsnID*/0, /*OpIdx*/6, /*OperandRenderer*/GIMT_Encode2(GICR_renderTruncTImm), // format
        GIR_CustomOperandRenderer, /*InsnID*/0, /*OldInsnID*/0, /*OpIdx*/7, /*OperandRenderer*/GIMT_Encode2(GICR_renderExtractCPol), // auxiliary
        GIR_CustomOperandRenderer, /*InsnID*/0, /*OldInsnID*/0, /*OpIdx*/7, /*OperandRenderer*/GIMT_Encode2(GICR_renderExtractSWZ), // auxiliary
        GIR_MergeMemOperands, /*InsnID*/0, /*NumInsns*/1, /*MergeInsnID's*/0,
        GIR_ConstrainSelectedInstOperands, /*InsnID*/0,
        GIR_EraseFromParent, /*InsnID*/0,
        // GIR_Coverage, 5587,
        GIR_Done,
      // Label 7254: @529121
      GIM_Try, /*On fail goto*//*Label 7255*/ GIMT_Encode4(529209), // Rule ID 5591 //
        GIM_CheckConstantInt8, /*MI*/0, /*Op*/2, 0,
        // MIs[0] offset
        GIM_CheckIsImm, /*MI*/0, /*Op*/5,
        // MIs[0] format
        GIM_CheckIsImm, /*MI*/0, /*Op*/6,
        // MIs[0] auxiliary
        GIM_CheckIsImm, /*MI*/0, /*Op*/7,
        // MIs[0] Operand 8
        GIM_CheckLiteralInt, /*MI*/0, /*Op*/8, GIMT_Encode8(0),
        GIM_CheckComplexPattern, /*MI*/0, /*Op*/4, /*Renderer*/GIMT_Encode2(0), GIMT_Encode2(GICP_gi_buf_soffset),
        // (SItbuffer_load:{ *:[v3i32] } v4i32:{ *:[v4i32] }:$rsrc, 0:{ *:[i32] }, i32:{ *:[i32] }:$voffset, (BUFSOffset:{ *:[i32] } i32:{ *:[i32] }:$soffset), (timm:{ *:[i32] }):$offset, (timm:{ *:[i32] }):$format, (timm:{ *:[i32] }):$auxiliary, 0:{ *:[i1] })  =>  (TBUFFER_LOAD_FORMAT_XYZ_VBUFFER_OFFEN:{ *:[v3i32] } VGPR_32:{ *:[i32] }:$voffset, SReg_128:{ *:[v4i32] }:$rsrc, SCSrc_b32:{ *:[i32] }:$soffset, (timm:{ *:[i32] }):$offset, (as_i8timm:{ *:[i8] } ?:{ *:[i32] }:$format), (extract_cpol:{ *:[i32] } ?:{ *:[i32] }:$auxiliary), (extract_swz:{ *:[i1] } ?:{ *:[i32] }:$auxiliary))
        GIR_BuildMI, /*InsnID*/0, /*Opcode*/GIMT_Encode2(AMDGPU::TBUFFER_LOAD_FORMAT_XYZ_VBUFFER_OFFEN),
        GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/0, // DstI[vdata]
        GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/3, // voffset
        GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/1, // rsrc
        GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/0, // soffset
        GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/5, // offset
        GIR_CustomOperandRenderer, /*InsnID*/0, /*OldInsnID*/0, /*OpIdx*/6, /*OperandRenderer*/GIMT_Encode2(GICR_renderTruncTImm), // format
        GIR_CustomOperandRenderer, /*InsnID*/0, /*OldInsnID*/0, /*OpIdx*/7, /*OperandRenderer*/GIMT_Encode2(GICR_renderExtractCPol), // auxiliary
        GIR_CustomOperandRenderer, /*InsnID*/0, /*OldInsnID*/0, /*OpIdx*/7, /*OperandRenderer*/GIMT_Encode2(GICR_renderExtractSWZ), // auxiliary
        GIR_MergeMemOperands, /*InsnID*/0, /*NumInsns*/1, /*MergeInsnID's*/0,
        GIR_ConstrainSelectedInstOperands, /*InsnID*/0,
        GIR_EraseFromParent, /*InsnID*/0,
        // GIR_Coverage, 5591,
        GIR_Done,
      // Label 7255: @529209
      GIM_Try, /*On fail goto*//*Label 7256*/ GIMT_Encode4(529300), // Rule ID 5619 //
        GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasUnrestrictedSOffset),
        GIM_CheckConstantInt8, /*MI*/0, /*Op*/2, 0,
        // MIs[0] offset
        GIM_CheckIsImm, /*MI*/0, /*Op*/5,
        // MIs[0] format
        GIM_CheckIsImm, /*MI*/0, /*Op*/6,
        // MIs[0] auxiliary
        GIM_CheckIsImm, /*MI*/0, /*Op*/7,
        // MIs[0] Operand 8
        GIM_CheckLiteralInt, /*MI*/0, /*Op*/8, GIMT_Encode8(0),
        GIM_CheckComplexPattern, /*MI*/0, /*Op*/4, /*Renderer*/GIMT_Encode2(0), GIMT_Encode2(GICP_gi_buf_soffset),
        // (SItbuffer_load:{ *:[v3f32] } v4i32:{ *:[v4i32] }:$rsrc, 0:{ *:[i32] }, i32:{ *:[i32] }:$voffset, (BUFSOffset:{ *:[i32] } i32:{ *:[i32] }:$soffset), (timm:{ *:[i32] }):$offset, (timm:{ *:[i32] }):$format, (timm:{ *:[i32] }):$auxiliary, 0:{ *:[i1] })  =>  (TBUFFER_LOAD_FORMAT_XYZ_OFFEN:{ *:[v3f32] } VGPR_32:{ *:[i32] }:$voffset, SReg_128:{ *:[v4i32] }:$rsrc, SCSrc_b32:{ *:[i32] }:$soffset, (timm:{ *:[i32] }):$offset, (as_i8timm:{ *:[i8] } ?:{ *:[i32] }:$format), (extract_cpol:{ *:[i32] } ?:{ *:[i32] }:$auxiliary), (extract_swz:{ *:[i1] } ?:{ *:[i32] }:$auxiliary))
        GIR_BuildMI, /*InsnID*/0, /*Opcode*/GIMT_Encode2(AMDGPU::TBUFFER_LOAD_FORMAT_XYZ_OFFEN),
        GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/0, // DstI[vdata]
        GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/3, // voffset
        GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/1, // rsrc
        GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/0, // soffset
        GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/5, // offset
        GIR_CustomOperandRenderer, /*InsnID*/0, /*OldInsnID*/0, /*OpIdx*/6, /*OperandRenderer*/GIMT_Encode2(GICR_renderTruncTImm), // format
        GIR_CustomOperandRenderer, /*InsnID*/0, /*OldInsnID*/0, /*OpIdx*/7, /*OperandRenderer*/GIMT_Encode2(GICR_renderExtractCPol), // auxiliary
        GIR_CustomOperandRenderer, /*InsnID*/0, /*OldInsnID*/0, /*OpIdx*/7, /*OperandRenderer*/GIMT_Encode2(GICR_renderExtractSWZ), // auxiliary
        GIR_MergeMemOperands, /*InsnID*/0, /*NumInsns*/1, /*MergeInsnID's*/0,
        GIR_ConstrainSelectedInstOperands, /*InsnID*/0,
        GIR_EraseFromParent, /*InsnID*/0,
        // GIR_Coverage, 5619,
        GIR_Done,
      // Label 7256: @529300
      GIM_Try, /*On fail goto*//*Label 7257*/ GIMT_Encode4(529388), // Rule ID 5623 //
        GIM_CheckConstantInt8, /*MI*/0, /*Op*/2, 0,
        // MIs[0] offset
        GIM_CheckIsImm, /*MI*/0, /*Op*/5,
        // MIs[0] format
        GIM_CheckIsImm, /*MI*/0, /*Op*/6,
        // MIs[0] auxiliary
        GIM_CheckIsImm, /*MI*/0, /*Op*/7,
        // MIs[0] Operand 8
        GIM_CheckLiteralInt, /*MI*/0, /*Op*/8, GIMT_Encode8(0),
        GIM_CheckComplexPattern, /*MI*/0, /*Op*/4, /*Renderer*/GIMT_Encode2(0), GIMT_Encode2(GICP_gi_buf_soffset),
        // (SItbuffer_load:{ *:[v3f32] } v4i32:{ *:[v4i32] }:$rsrc, 0:{ *:[i32] }, i32:{ *:[i32] }:$voffset, (BUFSOffset:{ *:[i32] } i32:{ *:[i32] }:$soffset), (timm:{ *:[i32] }):$offset, (timm:{ *:[i32] }):$format, (timm:{ *:[i32] }):$auxiliary, 0:{ *:[i1] })  =>  (TBUFFER_LOAD_FORMAT_XYZ_VBUFFER_OFFEN:{ *:[v3f32] } VGPR_32:{ *:[i32] }:$voffset, SReg_128:{ *:[v4i32] }:$rsrc, SCSrc_b32:{ *:[i32] }:$soffset, (timm:{ *:[i32] }):$offset, (as_i8timm:{ *:[i8] } ?:{ *:[i32] }:$format), (extract_cpol:{ *:[i32] } ?:{ *:[i32] }:$auxiliary), (extract_swz:{ *:[i1] } ?:{ *:[i32] }:$auxiliary))
        GIR_BuildMI, /*InsnID*/0, /*Opcode*/GIMT_Encode2(AMDGPU::TBUFFER_LOAD_FORMAT_XYZ_VBUFFER_OFFEN),
        GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/0, // DstI[vdata]
        GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/3, // voffset
        GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/1, // rsrc
        GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/0, // soffset
        GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/5, // offset
        GIR_CustomOperandRenderer, /*InsnID*/0, /*OldInsnID*/0, /*OpIdx*/6, /*OperandRenderer*/GIMT_Encode2(GICR_renderTruncTImm), // format
        GIR_CustomOperandRenderer, /*InsnID*/0, /*OldInsnID*/0, /*OpIdx*/7, /*OperandRenderer*/GIMT_Encode2(GICR_renderExtractCPol), // auxiliary
        GIR_CustomOperandRenderer, /*InsnID*/0, /*OldInsnID*/0, /*OpIdx*/7, /*OperandRenderer*/GIMT_Encode2(GICR_renderExtractSWZ), // auxiliary
        GIR_MergeMemOperands, /*InsnID*/0, /*NumInsns*/1, /*MergeInsnID's*/0,
        GIR_ConstrainSelectedInstOperands, /*InsnID*/0,
        GIR_EraseFromParent, /*InsnID*/0,
        // GIR_Coverage, 5623,
        GIR_Done,
      // Label 7257: @529388
      GIM_Try, /*On fail goto*//*Label 7258*/ GIMT_Encode4(529471), // Rule ID 5586 //
        GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasUnrestrictedSOffset),
        GIM_CheckConstantInt8, /*MI*/0, /*Op*/3, 0,
        // MIs[0] offset
        GIM_CheckIsImm, /*MI*/0, /*Op*/5,
        // MIs[0] format
        GIM_CheckIsImm, /*MI*/0, /*Op*/6,
        // MIs[0] auxiliary
        GIM_CheckIsImm, /*MI*/0, /*Op*/7,
        // MIs[0] Operand 8
        GIM_CheckIsImm, /*MI*/0, /*Op*/8,
        GIM_CheckComplexPattern, /*MI*/0, /*Op*/4, /*Renderer*/GIMT_Encode2(0), GIMT_Encode2(GICP_gi_buf_soffset),
        // (SItbuffer_load:{ *:[v3i32] } v4i32:{ *:[v4i32] }:$rsrc, i32:{ *:[i32] }:$vindex, 0:{ *:[i32] }, (BUFSOffset:{ *:[i32] } i32:{ *:[i32] }:$soffset), (timm:{ *:[i32] }):$offset, (timm:{ *:[i32] }):$format, (timm:{ *:[i32] }):$auxiliary, (timm:{ *:[i1] }))  =>  (TBUFFER_LOAD_FORMAT_XYZ_IDXEN:{ *:[v3i32] } VGPR_32:{ *:[i32] }:$vindex, SReg_128:{ *:[v4i32] }:$rsrc, SCSrc_b32:{ *:[i32] }:$soffset, (timm:{ *:[i32] }):$offset, (as_i8timm:{ *:[i8] } ?:{ *:[i32] }:$format), (extract_cpol:{ *:[i32] } ?:{ *:[i32] }:$auxiliary), (extract_swz:{ *:[i1] } ?:{ *:[i32] }:$auxiliary))
        GIR_BuildMI, /*InsnID*/0, /*Opcode*/GIMT_Encode2(AMDGPU::TBUFFER_LOAD_FORMAT_XYZ_IDXEN),
        GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/0, // DstI[vdata]
        GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/2, // vindex
        GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/1, // rsrc
        GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/0, // soffset
        GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/5, // offset
        GIR_CustomOperandRenderer, /*InsnID*/0, /*OldInsnID*/0, /*OpIdx*/6, /*OperandRenderer*/GIMT_Encode2(GICR_renderTruncTImm), // format
        GIR_CustomOperandRenderer, /*InsnID*/0, /*OldInsnID*/0, /*OpIdx*/7, /*OperandRenderer*/GIMT_Encode2(GICR_renderExtractCPol), // auxiliary
        GIR_CustomOperandRenderer, /*InsnID*/0, /*OldInsnID*/0, /*OpIdx*/7, /*OperandRenderer*/GIMT_Encode2(GICR_renderExtractSWZ), // auxiliary
        GIR_MergeMemOperands, /*InsnID*/0, /*NumInsns*/1, /*MergeInsnID's*/0,
        GIR_ConstrainSelectedInstOperands, /*InsnID*/0,
        GIR_EraseFromParent, /*InsnID*/0,
        // GIR_Coverage, 5586,
        GIR_Done,
      // Label 7258: @529471
      GIM_Try, /*On fail goto*//*Label 7259*/ GIMT_Encode4(529551), // Rule ID 5590 //
        GIM_CheckConstantInt8, /*MI*/0, /*Op*/3, 0,
        // MIs[0] offset
        GIM_CheckIsImm, /*MI*/0, /*Op*/5,
        // MIs[0] format
        GIM_CheckIsImm, /*MI*/0, /*Op*/6,
        // MIs[0] auxiliary
        GIM_CheckIsImm, /*MI*/0, /*Op*/7,
        // MIs[0] Operand 8
        GIM_CheckIsImm, /*MI*/0, /*Op*/8,
        GIM_CheckComplexPattern, /*MI*/0, /*Op*/4, /*Renderer*/GIMT_Encode2(0), GIMT_Encode2(GICP_gi_buf_soffset),
        // (SItbuffer_load:{ *:[v3i32] } v4i32:{ *:[v4i32] }:$rsrc, i32:{ *:[i32] }:$vindex, 0:{ *:[i32] }, (BUFSOffset:{ *:[i32] } i32:{ *:[i32] }:$soffset), (timm:{ *:[i32] }):$offset, (timm:{ *:[i32] }):$format, (timm:{ *:[i32] }):$auxiliary, (timm:{ *:[i1] }))  =>  (TBUFFER_LOAD_FORMAT_XYZ_VBUFFER_IDXEN:{ *:[v3i32] } VGPR_32:{ *:[i32] }:$vindex, SReg_128:{ *:[v4i32] }:$rsrc, SCSrc_b32:{ *:[i32] }:$soffset, (timm:{ *:[i32] }):$offset, (as_i8timm:{ *:[i8] } ?:{ *:[i32] }:$format), (extract_cpol:{ *:[i32] } ?:{ *:[i32] }:$auxiliary), (extract_swz:{ *:[i1] } ?:{ *:[i32] }:$auxiliary))
        GIR_BuildMI, /*InsnID*/0, /*Opcode*/GIMT_Encode2(AMDGPU::TBUFFER_LOAD_FORMAT_XYZ_VBUFFER_IDXEN),
        GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/0, // DstI[vdata]
        GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/2, // vindex
        GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/1, // rsrc
        GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/0, // soffset
        GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/5, // offset
        GIR_CustomOperandRenderer, /*InsnID*/0, /*OldInsnID*/0, /*OpIdx*/6, /*OperandRenderer*/GIMT_Encode2(GICR_renderTruncTImm), // format
        GIR_CustomOperandRenderer, /*InsnID*/0, /*OldInsnID*/0, /*OpIdx*/7, /*OperandRenderer*/GIMT_Encode2(GICR_renderExtractCPol), // auxiliary
        GIR_CustomOperandRenderer, /*InsnID*/0, /*OldInsnID*/0, /*OpIdx*/7, /*OperandRenderer*/GIMT_Encode2(GICR_renderExtractSWZ), // auxiliary
        GIR_MergeMemOperands, /*InsnID*/0, /*NumInsns*/1, /*MergeInsnID's*/0,
        GIR_ConstrainSelectedInstOperands, /*InsnID*/0,
        GIR_EraseFromParent, /*InsnID*/0,
        // GIR_Coverage, 5590,
        GIR_Done,
      // Label 7259: @529551
      GIM_Try, /*On fail goto*//*Label 7260*/ GIMT_Encode4(529634), // Rule ID 5618 //
        GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasUnrestrictedSOffset),
        GIM_CheckConstantInt8, /*MI*/0, /*Op*/3, 0,
        // MIs[0] offset
        GIM_CheckIsImm, /*MI*/0, /*Op*/5,
        // MIs[0] format
        GIM_CheckIsImm, /*MI*/0, /*Op*/6,
        // MIs[0] auxiliary
        GIM_CheckIsImm, /*MI*/0, /*Op*/7,
        // MIs[0] Operand 8
        GIM_CheckIsImm, /*MI*/0, /*Op*/8,
        GIM_CheckComplexPattern, /*MI*/0, /*Op*/4, /*Renderer*/GIMT_Encode2(0), GIMT_Encode2(GICP_gi_buf_soffset),
        // (SItbuffer_load:{ *:[v3f32] } v4i32:{ *:[v4i32] }:$rsrc, i32:{ *:[i32] }:$vindex, 0:{ *:[i32] }, (BUFSOffset:{ *:[i32] } i32:{ *:[i32] }:$soffset), (timm:{ *:[i32] }):$offset, (timm:{ *:[i32] }):$format, (timm:{ *:[i32] }):$auxiliary, (timm:{ *:[i1] }))  =>  (TBUFFER_LOAD_FORMAT_XYZ_IDXEN:{ *:[v3f32] } VGPR_32:{ *:[i32] }:$vindex, SReg_128:{ *:[v4i32] }:$rsrc, SCSrc_b32:{ *:[i32] }:$soffset, (timm:{ *:[i32] }):$offset, (as_i8timm:{ *:[i8] } ?:{ *:[i32] }:$format), (extract_cpol:{ *:[i32] } ?:{ *:[i32] }:$auxiliary), (extract_swz:{ *:[i1] } ?:{ *:[i32] }:$auxiliary))
        GIR_BuildMI, /*InsnID*/0, /*Opcode*/GIMT_Encode2(AMDGPU::TBUFFER_LOAD_FORMAT_XYZ_IDXEN),
        GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/0, // DstI[vdata]
        GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/2, // vindex
        GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/1, // rsrc
        GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/0, // soffset
        GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/5, // offset
        GIR_CustomOperandRenderer, /*InsnID*/0, /*OldInsnID*/0, /*OpIdx*/6, /*OperandRenderer*/GIMT_Encode2(GICR_renderTruncTImm), // format
        GIR_CustomOperandRenderer, /*InsnID*/0, /*OldInsnID*/0, /*OpIdx*/7, /*OperandRenderer*/GIMT_Encode2(GICR_renderExtractCPol), // auxiliary
        GIR_CustomOperandRenderer, /*InsnID*/0, /*OldInsnID*/0, /*OpIdx*/7, /*OperandRenderer*/GIMT_Encode2(GICR_renderExtractSWZ), // auxiliary
        GIR_MergeMemOperands, /*InsnID*/0, /*NumInsns*/1, /*MergeInsnID's*/0,
        GIR_ConstrainSelectedInstOperands, /*InsnID*/0,
        GIR_EraseFromParent, /*InsnID*/0,
        // GIR_Coverage, 5618,
        GIR_Done,
      // Label 7260: @529634
      GIM_Try, /*On fail goto*//*Label 7261*/ GIMT_Encode4(529714), // Rule ID 5622 //
        GIM_CheckConstantInt8, /*MI*/0, /*Op*/3, 0,
        // MIs[0] offset
        GIM_CheckIsImm, /*MI*/0, /*Op*/5,
        // MIs[0] format
        GIM_CheckIsImm, /*MI*/0, /*Op*/6,
        // MIs[0] auxiliary
        GIM_CheckIsImm, /*MI*/0, /*Op*/7,
        // MIs[0] Operand 8
        GIM_CheckIsImm, /*MI*/0, /*Op*/8,
        GIM_CheckComplexPattern, /*MI*/0, /*Op*/4, /*Renderer*/GIMT_Encode2(0), GIMT_Encode2(GICP_gi_buf_soffset),
        // (SItbuffer_load:{ *:[v3f32] } v4i32:{ *:[v4i32] }:$rsrc, i32:{ *:[i32] }:$vindex, 0:{ *:[i32] }, (BUFSOffset:{ *:[i32] } i32:{ *:[i32] }:$soffset), (timm:{ *:[i32] }):$offset, (timm:{ *:[i32] }):$format, (timm:{ *:[i32] }):$auxiliary, (timm:{ *:[i1] }))  =>  (TBUFFER_LOAD_FORMAT_XYZ_VBUFFER_IDXEN:{ *:[v3f32] } VGPR_32:{ *:[i32] }:$vindex, SReg_128:{ *:[v4i32] }:$rsrc, SCSrc_b32:{ *:[i32] }:$soffset, (timm:{ *:[i32] }):$offset, (as_i8timm:{ *:[i8] } ?:{ *:[i32] }:$format), (extract_cpol:{ *:[i32] } ?:{ *:[i32] }:$auxiliary), (extract_swz:{ *:[i1] } ?:{ *:[i32] }:$auxiliary))
        GIR_BuildMI, /*InsnID*/0, /*Opcode*/GIMT_Encode2(AMDGPU::TBUFFER_LOAD_FORMAT_XYZ_VBUFFER_IDXEN),
        GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/0, // DstI[vdata]
        GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/2, // vindex
        GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/1, // rsrc
        GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/0, // soffset
        GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/5, // offset
        GIR_CustomOperandRenderer, /*InsnID*/0, /*OldInsnID*/0, /*OpIdx*/6, /*OperandRenderer*/GIMT_Encode2(GICR_renderTruncTImm), // format
        GIR_CustomOperandRenderer, /*InsnID*/0, /*OldInsnID*/0, /*OpIdx*/7, /*OperandRenderer*/GIMT_Encode2(GICR_renderExtractCPol), // auxiliary
        GIR_CustomOperandRenderer, /*InsnID*/0, /*OldInsnID*/0, /*OpIdx*/7, /*OperandRenderer*/GIMT_Encode2(GICR_renderExtractSWZ), // auxiliary
        GIR_MergeMemOperands, /*InsnID*/0, /*NumInsns*/1, /*MergeInsnID's*/0,
        GIR_ConstrainSelectedInstOperands, /*InsnID*/0,
        GIR_EraseFromParent, /*InsnID*/0,
        // GIR_Coverage, 5622,
        GIR_Done,
      // Label 7261: @529714
      GIM_Try, /*On fail goto*//*Label 7262*/ GIMT_Encode4(529833), // Rule ID 5588 //
        GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasUnrestrictedSOffset),
        // MIs[0] offset
        GIM_CheckIsImm, /*MI*/0, /*Op*/5,
        // MIs[0] format
        GIM_CheckIsImm, /*MI*/0, /*Op*/6,
        // MIs[0] auxiliary
        GIM_CheckIsImm, /*MI*/0, /*Op*/7,
        // MIs[0] Operand 8
        GIM_CheckIsImm, /*MI*/0, /*Op*/8,
        GIM_CheckComplexPattern, /*MI*/0, /*Op*/4, /*Renderer*/GIMT_Encode2(0), GIMT_Encode2(GICP_gi_buf_soffset),
        // (SItbuffer_load:{ *:[v3i32] } v4i32:{ *:[v4i32] }:$rsrc, i32:{ *:[i32] }:$vindex, i32:{ *:[i32] }:$voffset, (BUFSOffset:{ *:[i32] } i32:{ *:[i32] }:$soffset), (timm:{ *:[i32] }):$offset, (timm:{ *:[i32] }):$format, (timm:{ *:[i32] }):$auxiliary, (timm:{ *:[i1] }))  =>  (TBUFFER_LOAD_FORMAT_XYZ_BOTHEN:{ *:[v3i32] } (REG_SEQUENCE:{ *:[i64] } VReg_64:{ *:[i32] }, VGPR_32:{ *:[i32] }:$vindex, sub0:{ *:[i32] }, VGPR_32:{ *:[i32] }:$voffset, sub1:{ *:[i32] }), SReg_128:{ *:[v4i32] }:$rsrc, SCSrc_b32:{ *:[i32] }:$soffset, (timm:{ *:[i32] }):$offset, (as_i8timm:{ *:[i8] } ?:{ *:[i32] }:$format), (extract_cpol:{ *:[i32] } ?:{ *:[i32] }:$auxiliary), (extract_swz:{ *:[i1] } ?:{ *:[i32] }:$auxiliary))
        GIR_MakeTempReg, /*TempRegID*/0, /*TypeID*/GILLT_s64,
        GIR_BuildMI, /*InsnID*/1, /*Opcode*/GIMT_Encode2(TargetOpcode::REG_SEQUENCE),
        GIR_AddTempRegister, /*InsnID*/1, /*TempRegID*/0, /*TempRegFlags*/GIMT_Encode2(RegState::Define),
        GIR_Copy, /*NewInsnID*/1, /*OldInsnID*/0, /*OpIdx*/2, // vindex
        GIR_AddImm8, /*InsnID*/1, /*SubRegIndex*/3,
        GIR_Copy, /*NewInsnID*/1, /*OldInsnID*/0, /*OpIdx*/3, // voffset
        GIR_AddImm8, /*InsnID*/1, /*SubRegIndex*/11,
        GIR_ConstrainOperandRC, /*InsnID*/1, /*Op*/0, GIMT_Encode2(AMDGPU::VReg_64RegClassID),
        GIR_ConstrainOperandRC, /*InsnID*/1, /*Op*/1, GIMT_Encode2(AMDGPU::VGPR_32RegClassID),
        GIR_ConstrainOperandRC, /*InsnID*/1, /*Op*/3, GIMT_Encode2(AMDGPU::VGPR_32RegClassID),
        GIR_BuildMI, /*InsnID*/0, /*Opcode*/GIMT_Encode2(AMDGPU::TBUFFER_LOAD_FORMAT_XYZ_BOTHEN),
        GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/0, // DstI[vdata]
        GIR_AddSimpleTempRegister, /*InsnID*/0, /*TempRegID*/0,
        GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/1, // rsrc
        GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/0, // soffset
        GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/5, // offset
        GIR_CustomOperandRenderer, /*InsnID*/0, /*OldInsnID*/0, /*OpIdx*/6, /*OperandRenderer*/GIMT_Encode2(GICR_renderTruncTImm), // format
        GIR_CustomOperandRenderer, /*InsnID*/0, /*OldInsnID*/0, /*OpIdx*/7, /*OperandRenderer*/GIMT_Encode2(GICR_renderExtractCPol), // auxiliary
        GIR_CustomOperandRenderer, /*InsnID*/0, /*OldInsnID*/0, /*OpIdx*/7, /*OperandRenderer*/GIMT_Encode2(GICR_renderExtractSWZ), // auxiliary
        GIR_MergeMemOperands, /*InsnID*/0, /*NumInsns*/1, /*MergeInsnID's*/0,
        GIR_ConstrainSelectedInstOperands, /*InsnID*/0,
        GIR_EraseFromParent, /*InsnID*/0,
        // GIR_Coverage, 5588,
        GIR_Done,
      // Label 7262: @529833
      GIM_Try, /*On fail goto*//*Label 7263*/ GIMT_Encode4(529949), // Rule ID 5592 //
        // MIs[0] offset
        GIM_CheckIsImm, /*MI*/0, /*Op*/5,
        // MIs[0] format
        GIM_CheckIsImm, /*MI*/0, /*Op*/6,
        // MIs[0] auxiliary
        GIM_CheckIsImm, /*MI*/0, /*Op*/7,
        // MIs[0] Operand 8
        GIM_CheckIsImm, /*MI*/0, /*Op*/8,
        GIM_CheckComplexPattern, /*MI*/0, /*Op*/4, /*Renderer*/GIMT_Encode2(0), GIMT_Encode2(GICP_gi_buf_soffset),
        // (SItbuffer_load:{ *:[v3i32] } v4i32:{ *:[v4i32] }:$rsrc, i32:{ *:[i32] }:$vindex, i32:{ *:[i32] }:$voffset, (BUFSOffset:{ *:[i32] } i32:{ *:[i32] }:$soffset), (timm:{ *:[i32] }):$offset, (timm:{ *:[i32] }):$format, (timm:{ *:[i32] }):$auxiliary, (timm:{ *:[i1] }))  =>  (TBUFFER_LOAD_FORMAT_XYZ_VBUFFER_BOTHEN:{ *:[v3i32] } (REG_SEQUENCE:{ *:[i64] } VReg_64:{ *:[i32] }, VGPR_32:{ *:[i32] }:$vindex, sub0:{ *:[i32] }, VGPR_32:{ *:[i32] }:$voffset, sub1:{ *:[i32] }), SReg_128:{ *:[v4i32] }:$rsrc, SCSrc_b32:{ *:[i32] }:$soffset, (timm:{ *:[i32] }):$offset, (as_i8timm:{ *:[i8] } ?:{ *:[i32] }:$format), (extract_cpol:{ *:[i32] } ?:{ *:[i32] }:$auxiliary), (extract_swz:{ *:[i1] } ?:{ *:[i32] }:$auxiliary))
        GIR_MakeTempReg, /*TempRegID*/0, /*TypeID*/GILLT_s64,
        GIR_BuildMI, /*InsnID*/1, /*Opcode*/GIMT_Encode2(TargetOpcode::REG_SEQUENCE),
        GIR_AddTempRegister, /*InsnID*/1, /*TempRegID*/0, /*TempRegFlags*/GIMT_Encode2(RegState::Define),
        GIR_Copy, /*NewInsnID*/1, /*OldInsnID*/0, /*OpIdx*/2, // vindex
        GIR_AddImm8, /*InsnID*/1, /*SubRegIndex*/3,
        GIR_Copy, /*NewInsnID*/1, /*OldInsnID*/0, /*OpIdx*/3, // voffset
        GIR_AddImm8, /*InsnID*/1, /*SubRegIndex*/11,
        GIR_ConstrainOperandRC, /*InsnID*/1, /*Op*/0, GIMT_Encode2(AMDGPU::VReg_64RegClassID),
        GIR_ConstrainOperandRC, /*InsnID*/1, /*Op*/1, GIMT_Encode2(AMDGPU::VGPR_32RegClassID),
        GIR_ConstrainOperandRC, /*InsnID*/1, /*Op*/3, GIMT_Encode2(AMDGPU::VGPR_32RegClassID),
        GIR_BuildMI, /*InsnID*/0, /*Opcode*/GIMT_Encode2(AMDGPU::TBUFFER_LOAD_FORMAT_XYZ_VBUFFER_BOTHEN),
        GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/0, // DstI[vdata]
        GIR_AddSimpleTempRegister, /*InsnID*/0, /*TempRegID*/0,
        GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/1, // rsrc
        GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/0, // soffset
        GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/5, // offset
        GIR_CustomOperandRenderer, /*InsnID*/0, /*OldInsnID*/0, /*OpIdx*/6, /*OperandRenderer*/GIMT_Encode2(GICR_renderTruncTImm), // format
        GIR_CustomOperandRenderer, /*InsnID*/0, /*OldInsnID*/0, /*OpIdx*/7, /*OperandRenderer*/GIMT_Encode2(GICR_renderExtractCPol), // auxiliary
        GIR_CustomOperandRenderer, /*InsnID*/0, /*OldInsnID*/0, /*OpIdx*/7, /*OperandRenderer*/GIMT_Encode2(GICR_renderExtractSWZ), // auxiliary
        GIR_MergeMemOperands, /*InsnID*/0, /*NumInsns*/1, /*MergeInsnID's*/0,
        GIR_ConstrainSelectedInstOperands, /*InsnID*/0,
        GIR_EraseFromParent, /*InsnID*/0,
        // GIR_Coverage, 5592,
        GIR_Done,
      // Label 7263: @529949
      GIM_Try, /*On fail goto*//*Label 7264*/ GIMT_Encode4(530068), // Rule ID 5620 //
        GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasUnrestrictedSOffset),
        // MIs[0] offset
        GIM_CheckIsImm, /*MI*/0, /*Op*/5,
        // MIs[0] format
        GIM_CheckIsImm, /*MI*/0, /*Op*/6,
        // MIs[0] auxiliary
        GIM_CheckIsImm, /*MI*/0, /*Op*/7,
        // MIs[0] Operand 8
        GIM_CheckIsImm, /*MI*/0, /*Op*/8,
        GIM_CheckComplexPattern, /*MI*/0, /*Op*/4, /*Renderer*/GIMT_Encode2(0), GIMT_Encode2(GICP_gi_buf_soffset),
        // (SItbuffer_load:{ *:[v3f32] } v4i32:{ *:[v4i32] }:$rsrc, i32:{ *:[i32] }:$vindex, i32:{ *:[i32] }:$voffset, (BUFSOffset:{ *:[i32] } i32:{ *:[i32] }:$soffset), (timm:{ *:[i32] }):$offset, (timm:{ *:[i32] }):$format, (timm:{ *:[i32] }):$auxiliary, (timm:{ *:[i1] }))  =>  (TBUFFER_LOAD_FORMAT_XYZ_BOTHEN:{ *:[v3f32] } (REG_SEQUENCE:{ *:[i64] } VReg_64:{ *:[i32] }, VGPR_32:{ *:[i32] }:$vindex, sub0:{ *:[i32] }, VGPR_32:{ *:[i32] }:$voffset, sub1:{ *:[i32] }), SReg_128:{ *:[v4i32] }:$rsrc, SCSrc_b32:{ *:[i32] }:$soffset, (timm:{ *:[i32] }):$offset, (as_i8timm:{ *:[i8] } ?:{ *:[i32] }:$format), (extract_cpol:{ *:[i32] } ?:{ *:[i32] }:$auxiliary), (extract_swz:{ *:[i1] } ?:{ *:[i32] }:$auxiliary))
        GIR_MakeTempReg, /*TempRegID*/0, /*TypeID*/GILLT_s64,
        GIR_BuildMI, /*InsnID*/1, /*Opcode*/GIMT_Encode2(TargetOpcode::REG_SEQUENCE),
        GIR_AddTempRegister, /*InsnID*/1, /*TempRegID*/0, /*TempRegFlags*/GIMT_Encode2(RegState::Define),
        GIR_Copy, /*NewInsnID*/1, /*OldInsnID*/0, /*OpIdx*/2, // vindex
        GIR_AddImm8, /*InsnID*/1, /*SubRegIndex*/3,
        GIR_Copy, /*NewInsnID*/1, /*OldInsnID*/0, /*OpIdx*/3, // voffset
        GIR_AddImm8, /*InsnID*/1, /*SubRegIndex*/11,
        GIR_ConstrainOperandRC, /*InsnID*/1, /*Op*/0, GIMT_Encode2(AMDGPU::VReg_64RegClassID),
        GIR_ConstrainOperandRC, /*InsnID*/1, /*Op*/1, GIMT_Encode2(AMDGPU::VGPR_32RegClassID),
        GIR_ConstrainOperandRC, /*InsnID*/1, /*Op*/3, GIMT_Encode2(AMDGPU::VGPR_32RegClassID),
        GIR_BuildMI, /*InsnID*/0, /*Opcode*/GIMT_Encode2(AMDGPU::TBUFFER_LOAD_FORMAT_XYZ_BOTHEN),
        GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/0, // DstI[vdata]
        GIR_AddSimpleTempRegister, /*InsnID*/0, /*TempRegID*/0,
        GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/1, // rsrc
        GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/0, // soffset
        GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/5, // offset
        GIR_CustomOperandRenderer, /*InsnID*/0, /*OldInsnID*/0, /*OpIdx*/6, /*OperandRenderer*/GIMT_Encode2(GICR_renderTruncTImm), // format
        GIR_CustomOperandRenderer, /*InsnID*/0, /*OldInsnID*/0, /*OpIdx*/7, /*OperandRenderer*/GIMT_Encode2(GICR_renderExtractCPol), // auxiliary
        GIR_CustomOperandRenderer, /*InsnID*/0, /*OldInsnID*/0, /*OpIdx*/7, /*OperandRenderer*/GIMT_Encode2(GICR_renderExtractSWZ), // auxiliary
        GIR_MergeMemOperands, /*InsnID*/0, /*NumInsns*/1, /*MergeInsnID's*/0,
        GIR_ConstrainSelectedInstOperands, /*InsnID*/0,
        GIR_EraseFromParent, /*InsnID*/0,
        // GIR_Coverage, 5620,
        GIR_Done,
      // Label 7264: @530068
      GIM_Try, /*On fail goto*//*Label 7265*/ GIMT_Encode4(530184), // Rule ID 5624 //
        // MIs[0] offset
        GIM_CheckIsImm, /*MI*/0, /*Op*/5,
        // MIs[0] format
        GIM_CheckIsImm, /*MI*/0, /*Op*/6,
        // MIs[0] auxiliary
        GIM_CheckIsImm, /*MI*/0, /*Op*/7,
        // MIs[0] Operand 8
        GIM_CheckIsImm, /*MI*/0, /*Op*/8,
        GIM_CheckComplexPattern, /*MI*/0, /*Op*/4, /*Renderer*/GIMT_Encode2(0), GIMT_Encode2(GICP_gi_buf_soffset),
        // (SItbuffer_load:{ *:[v3f32] } v4i32:{ *:[v4i32] }:$rsrc, i32:{ *:[i32] }:$vindex, i32:{ *:[i32] }:$voffset, (BUFSOffset:{ *:[i32] } i32:{ *:[i32] }:$soffset), (timm:{ *:[i32] }):$offset, (timm:{ *:[i32] }):$format, (timm:{ *:[i32] }):$auxiliary, (timm:{ *:[i1] }))  =>  (TBUFFER_LOAD_FORMAT_XYZ_VBUFFER_BOTHEN:{ *:[v3f32] } (REG_SEQUENCE:{ *:[i64] } VReg_64:{ *:[i32] }, VGPR_32:{ *:[i32] }:$vindex, sub0:{ *:[i32] }, VGPR_32:{ *:[i32] }:$voffset, sub1:{ *:[i32] }), SReg_128:{ *:[v4i32] }:$rsrc, SCSrc_b32:{ *:[i32] }:$soffset, (timm:{ *:[i32] }):$offset, (as_i8timm:{ *:[i8] } ?:{ *:[i32] }:$format), (extract_cpol:{ *:[i32] } ?:{ *:[i32] }:$auxiliary), (extract_swz:{ *:[i1] } ?:{ *:[i32] }:$auxiliary))
        GIR_MakeTempReg, /*TempRegID*/0, /*TypeID*/GILLT_s64,
        GIR_BuildMI, /*InsnID*/1, /*Opcode*/GIMT_Encode2(TargetOpcode::REG_SEQUENCE),
        GIR_AddTempRegister, /*InsnID*/1, /*TempRegID*/0, /*TempRegFlags*/GIMT_Encode2(RegState::Define),
        GIR_Copy, /*NewInsnID*/1, /*OldInsnID*/0, /*OpIdx*/2, // vindex
        GIR_AddImm8, /*InsnID*/1, /*SubRegIndex*/3,
        GIR_Copy, /*NewInsnID*/1, /*OldInsnID*/0, /*OpIdx*/3, // voffset
        GIR_AddImm8, /*InsnID*/1, /*SubRegIndex*/11,
        GIR_ConstrainOperandRC, /*InsnID*/1, /*Op*/0, GIMT_Encode2(AMDGPU::VReg_64RegClassID),
        GIR_ConstrainOperandRC, /*InsnID*/1, /*Op*/1, GIMT_Encode2(AMDGPU::VGPR_32RegClassID),
        GIR_ConstrainOperandRC, /*InsnID*/1, /*Op*/3, GIMT_Encode2(AMDGPU::VGPR_32RegClassID),
        GIR_BuildMI, /*InsnID*/0, /*Opcode*/GIMT_Encode2(AMDGPU::TBUFFER_LOAD_FORMAT_XYZ_VBUFFER_BOTHEN),
        GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/0, // DstI[vdata]
        GIR_AddSimpleTempRegister, /*InsnID*/0, /*TempRegID*/0,
        GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/1, // rsrc
        GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/0, // soffset
        GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/5, // offset
        GIR_CustomOperandRenderer, /*InsnID*/0, /*OldInsnID*/0, /*OpIdx*/6, /*OperandRenderer*/GIMT_Encode2(GICR_renderTruncTImm), // format
        GIR_CustomOperandRenderer, /*InsnID*/0, /*OldInsnID*/0, /*OpIdx*/7, /*OperandRenderer*/GIMT_Encode2(GICR_renderExtractCPol), // auxiliary
        GIR_CustomOperandRenderer, /*InsnID*/0, /*OldInsnID*/0, /*OpIdx*/7, /*OperandRenderer*/GIMT_Encode2(GICR_renderExtractSWZ), // auxiliary
        GIR_MergeMemOperands, /*InsnID*/0, /*NumInsns*/1, /*MergeInsnID's*/0,
        GIR_ConstrainSelectedInstOperands, /*InsnID*/0,
        GIR_EraseFromParent, /*InsnID*/0,
        // GIR_Coverage, 5624,
        GIR_Done,
      // Label 7265: @530184
      GIM_Reject,
    // Label 7249: @530185
    GIM_Reject,
    // Label 7213: @530186
    GIM_Try, /*On fail goto*//*Label 7266*/ GIMT_Encode4(531725),
      GIM_CheckType, /*MI*/0, /*Op*/1, /*Type*/GILLT_v4s32,
      GIM_CheckType, /*MI*/0, /*Op*/2, /*Type*/GILLT_s32,
      GIM_CheckType, /*MI*/0, /*Op*/3, /*Type*/GILLT_s32,
      GIM_CheckType, /*MI*/0, /*Op*/4, /*Type*/GILLT_s32,
      GIM_CheckRegBankForClass, /*MI*/0, /*Op*/0, /*RC*/GIMT_Encode2(AMDGPU::AV_128RegClassID),
      GIM_Try, /*On fail goto*//*Label 7267*/ GIMT_Encode4(530303), // Rule ID 5593 //
        GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasUnrestrictedSOffset),
        GIM_CheckConstantInt8, /*MI*/0, /*Op*/2, 0,
        GIM_CheckConstantInt8, /*MI*/0, /*Op*/3, 0,
        // MIs[0] offset
        GIM_CheckIsImm, /*MI*/0, /*Op*/5,
        // MIs[0] format
        GIM_CheckIsImm, /*MI*/0, /*Op*/6,
        // MIs[0] auxiliary
        GIM_CheckIsImm, /*MI*/0, /*Op*/7,
        // MIs[0] Operand 8
        GIM_CheckLiteralInt, /*MI*/0, /*Op*/8, GIMT_Encode8(0),
        GIM_CheckComplexPattern, /*MI*/0, /*Op*/4, /*Renderer*/GIMT_Encode2(0), GIMT_Encode2(GICP_gi_buf_soffset),
        // (SItbuffer_load:{ *:[v4i32] } v4i32:{ *:[v4i32] }:$rsrc, 0:{ *:[i32] }, 0:{ *:[i32] }, (BUFSOffset:{ *:[i32] } i32:{ *:[i32] }:$soffset), (timm:{ *:[i32] }):$offset, (timm:{ *:[i32] }):$format, (timm:{ *:[i32] }):$auxiliary, 0:{ *:[i1] })  =>  (TBUFFER_LOAD_FORMAT_XYZW_OFFSET:{ *:[v4i32] } SReg_128:{ *:[v4i32] }:$rsrc, SCSrc_b32:{ *:[i32] }:$soffset, (timm:{ *:[i32] }):$offset, (as_i8timm:{ *:[i8] } ?:{ *:[i32] }:$format), (extract_cpol:{ *:[i32] } ?:{ *:[i32] }:$auxiliary), (extract_swz:{ *:[i1] } ?:{ *:[i32] }:$auxiliary))
        GIR_BuildMI, /*InsnID*/0, /*Opcode*/GIMT_Encode2(AMDGPU::TBUFFER_LOAD_FORMAT_XYZW_OFFSET),
        GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/0, // DstI[vdata]
        GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/1, // rsrc
        GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/0, // soffset
        GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/5, // offset
        GIR_CustomOperandRenderer, /*InsnID*/0, /*OldInsnID*/0, /*OpIdx*/6, /*OperandRenderer*/GIMT_Encode2(GICR_renderTruncTImm), // format
        GIR_CustomOperandRenderer, /*InsnID*/0, /*OldInsnID*/0, /*OpIdx*/7, /*OperandRenderer*/GIMT_Encode2(GICR_renderExtractCPol), // auxiliary
        GIR_CustomOperandRenderer, /*InsnID*/0, /*OldInsnID*/0, /*OpIdx*/7, /*OperandRenderer*/GIMT_Encode2(GICR_renderExtractSWZ), // auxiliary
        GIR_MergeMemOperands, /*InsnID*/0, /*NumInsns*/1, /*MergeInsnID's*/0,
        GIR_ConstrainSelectedInstOperands, /*InsnID*/0,
        GIR_EraseFromParent, /*InsnID*/0,
        // GIR_Coverage, 5593,
        GIR_Done,
      // Label 7267: @530303
      GIM_Try, /*On fail goto*//*Label 7268*/ GIMT_Encode4(530391), // Rule ID 5597 //
        GIM_CheckConstantInt8, /*MI*/0, /*Op*/2, 0,
        GIM_CheckConstantInt8, /*MI*/0, /*Op*/3, 0,
        // MIs[0] offset
        GIM_CheckIsImm, /*MI*/0, /*Op*/5,
        // MIs[0] format
        GIM_CheckIsImm, /*MI*/0, /*Op*/6,
        // MIs[0] auxiliary
        GIM_CheckIsImm, /*MI*/0, /*Op*/7,
        // MIs[0] Operand 8
        GIM_CheckLiteralInt, /*MI*/0, /*Op*/8, GIMT_Encode8(0),
        GIM_CheckComplexPattern, /*MI*/0, /*Op*/4, /*Renderer*/GIMT_Encode2(0), GIMT_Encode2(GICP_gi_buf_soffset),
        // (SItbuffer_load:{ *:[v4i32] } v4i32:{ *:[v4i32] }:$rsrc, 0:{ *:[i32] }, 0:{ *:[i32] }, (BUFSOffset:{ *:[i32] } i32:{ *:[i32] }:$soffset), (timm:{ *:[i32] }):$offset, (timm:{ *:[i32] }):$format, (timm:{ *:[i32] }):$auxiliary, 0:{ *:[i1] })  =>  (TBUFFER_LOAD_FORMAT_XYZW_VBUFFER_OFFSET:{ *:[v4i32] } SReg_128:{ *:[v4i32] }:$rsrc, SCSrc_b32:{ *:[i32] }:$soffset, (timm:{ *:[i32] }):$offset, (as_i8timm:{ *:[i8] } ?:{ *:[i32] }:$format), (extract_cpol:{ *:[i32] } ?:{ *:[i32] }:$auxiliary), (extract_swz:{ *:[i1] } ?:{ *:[i32] }:$auxiliary))
        GIR_BuildMI, /*InsnID*/0, /*Opcode*/GIMT_Encode2(AMDGPU::TBUFFER_LOAD_FORMAT_XYZW_VBUFFER_OFFSET),
        GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/0, // DstI[vdata]
        GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/1, // rsrc
        GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/0, // soffset
        GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/5, // offset
        GIR_CustomOperandRenderer, /*InsnID*/0, /*OldInsnID*/0, /*OpIdx*/6, /*OperandRenderer*/GIMT_Encode2(GICR_renderTruncTImm), // format
        GIR_CustomOperandRenderer, /*InsnID*/0, /*OldInsnID*/0, /*OpIdx*/7, /*OperandRenderer*/GIMT_Encode2(GICR_renderExtractCPol), // auxiliary
        GIR_CustomOperandRenderer, /*InsnID*/0, /*OldInsnID*/0, /*OpIdx*/7, /*OperandRenderer*/GIMT_Encode2(GICR_renderExtractSWZ), // auxiliary
        GIR_MergeMemOperands, /*InsnID*/0, /*NumInsns*/1, /*MergeInsnID's*/0,
        GIR_ConstrainSelectedInstOperands, /*InsnID*/0,
        GIR_EraseFromParent, /*InsnID*/0,
        // GIR_Coverage, 5597,
        GIR_Done,
      // Label 7268: @530391
      GIM_Try, /*On fail goto*//*Label 7269*/ GIMT_Encode4(530482), // Rule ID 5625 //
        GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasUnrestrictedSOffset),
        GIM_CheckConstantInt8, /*MI*/0, /*Op*/2, 0,
        GIM_CheckConstantInt8, /*MI*/0, /*Op*/3, 0,
        // MIs[0] offset
        GIM_CheckIsImm, /*MI*/0, /*Op*/5,
        // MIs[0] format
        GIM_CheckIsImm, /*MI*/0, /*Op*/6,
        // MIs[0] auxiliary
        GIM_CheckIsImm, /*MI*/0, /*Op*/7,
        // MIs[0] Operand 8
        GIM_CheckLiteralInt, /*MI*/0, /*Op*/8, GIMT_Encode8(0),
        GIM_CheckComplexPattern, /*MI*/0, /*Op*/4, /*Renderer*/GIMT_Encode2(0), GIMT_Encode2(GICP_gi_buf_soffset),
        // (SItbuffer_load:{ *:[v4f32] } v4i32:{ *:[v4i32] }:$rsrc, 0:{ *:[i32] }, 0:{ *:[i32] }, (BUFSOffset:{ *:[i32] } i32:{ *:[i32] }:$soffset), (timm:{ *:[i32] }):$offset, (timm:{ *:[i32] }):$format, (timm:{ *:[i32] }):$auxiliary, 0:{ *:[i1] })  =>  (TBUFFER_LOAD_FORMAT_XYZW_OFFSET:{ *:[v4f32] } SReg_128:{ *:[v4i32] }:$rsrc, SCSrc_b32:{ *:[i32] }:$soffset, (timm:{ *:[i32] }):$offset, (as_i8timm:{ *:[i8] } ?:{ *:[i32] }:$format), (extract_cpol:{ *:[i32] } ?:{ *:[i32] }:$auxiliary), (extract_swz:{ *:[i1] } ?:{ *:[i32] }:$auxiliary))
        GIR_BuildMI, /*InsnID*/0, /*Opcode*/GIMT_Encode2(AMDGPU::TBUFFER_LOAD_FORMAT_XYZW_OFFSET),
        GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/0, // DstI[vdata]
        GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/1, // rsrc
        GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/0, // soffset
        GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/5, // offset
        GIR_CustomOperandRenderer, /*InsnID*/0, /*OldInsnID*/0, /*OpIdx*/6, /*OperandRenderer*/GIMT_Encode2(GICR_renderTruncTImm), // format
        GIR_CustomOperandRenderer, /*InsnID*/0, /*OldInsnID*/0, /*OpIdx*/7, /*OperandRenderer*/GIMT_Encode2(GICR_renderExtractCPol), // auxiliary
        GIR_CustomOperandRenderer, /*InsnID*/0, /*OldInsnID*/0, /*OpIdx*/7, /*OperandRenderer*/GIMT_Encode2(GICR_renderExtractSWZ), // auxiliary
        GIR_MergeMemOperands, /*InsnID*/0, /*NumInsns*/1, /*MergeInsnID's*/0,
        GIR_ConstrainSelectedInstOperands, /*InsnID*/0,
        GIR_EraseFromParent, /*InsnID*/0,
        // GIR_Coverage, 5625,
        GIR_Done,
      // Label 7269: @530482
      GIM_Try, /*On fail goto*//*Label 7270*/ GIMT_Encode4(530570), // Rule ID 5629 //
        GIM_CheckConstantInt8, /*MI*/0, /*Op*/2, 0,
        GIM_CheckConstantInt8, /*MI*/0, /*Op*/3, 0,
        // MIs[0] offset
        GIM_CheckIsImm, /*MI*/0, /*Op*/5,
        // MIs[0] format
        GIM_CheckIsImm, /*MI*/0, /*Op*/6,
        // MIs[0] auxiliary
        GIM_CheckIsImm, /*MI*/0, /*Op*/7,
        // MIs[0] Operand 8
        GIM_CheckLiteralInt, /*MI*/0, /*Op*/8, GIMT_Encode8(0),
        GIM_CheckComplexPattern, /*MI*/0, /*Op*/4, /*Renderer*/GIMT_Encode2(0), GIMT_Encode2(GICP_gi_buf_soffset),
        // (SItbuffer_load:{ *:[v4f32] } v4i32:{ *:[v4i32] }:$rsrc, 0:{ *:[i32] }, 0:{ *:[i32] }, (BUFSOffset:{ *:[i32] } i32:{ *:[i32] }:$soffset), (timm:{ *:[i32] }):$offset, (timm:{ *:[i32] }):$format, (timm:{ *:[i32] }):$auxiliary, 0:{ *:[i1] })  =>  (TBUFFER_LOAD_FORMAT_XYZW_VBUFFER_OFFSET:{ *:[v4f32] } SReg_128:{ *:[v4i32] }:$rsrc, SCSrc_b32:{ *:[i32] }:$soffset, (timm:{ *:[i32] }):$offset, (as_i8timm:{ *:[i8] } ?:{ *:[i32] }:$format), (extract_cpol:{ *:[i32] } ?:{ *:[i32] }:$auxiliary), (extract_swz:{ *:[i1] } ?:{ *:[i32] }:$auxiliary))
        GIR_BuildMI, /*InsnID*/0, /*Opcode*/GIMT_Encode2(AMDGPU::TBUFFER_LOAD_FORMAT_XYZW_VBUFFER_OFFSET),
        GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/0, // DstI[vdata]
        GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/1, // rsrc
        GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/0, // soffset
        GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/5, // offset
        GIR_CustomOperandRenderer, /*InsnID*/0, /*OldInsnID*/0, /*OpIdx*/6, /*OperandRenderer*/GIMT_Encode2(GICR_renderTruncTImm), // format
        GIR_CustomOperandRenderer, /*InsnID*/0, /*OldInsnID*/0, /*OpIdx*/7, /*OperandRenderer*/GIMT_Encode2(GICR_renderExtractCPol), // auxiliary
        GIR_CustomOperandRenderer, /*InsnID*/0, /*OldInsnID*/0, /*OpIdx*/7, /*OperandRenderer*/GIMT_Encode2(GICR_renderExtractSWZ), // auxiliary
        GIR_MergeMemOperands, /*InsnID*/0, /*NumInsns*/1, /*MergeInsnID's*/0,
        GIR_ConstrainSelectedInstOperands, /*InsnID*/0,
        GIR_EraseFromParent, /*InsnID*/0,
        // GIR_Coverage, 5629,
        GIR_Done,
      // Label 7270: @530570
      GIM_Try, /*On fail goto*//*Label 7271*/ GIMT_Encode4(530661), // Rule ID 5595 //
        GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasUnrestrictedSOffset),
        GIM_CheckConstantInt8, /*MI*/0, /*Op*/2, 0,
        // MIs[0] offset
        GIM_CheckIsImm, /*MI*/0, /*Op*/5,
        // MIs[0] format
        GIM_CheckIsImm, /*MI*/0, /*Op*/6,
        // MIs[0] auxiliary
        GIM_CheckIsImm, /*MI*/0, /*Op*/7,
        // MIs[0] Operand 8
        GIM_CheckLiteralInt, /*MI*/0, /*Op*/8, GIMT_Encode8(0),
        GIM_CheckComplexPattern, /*MI*/0, /*Op*/4, /*Renderer*/GIMT_Encode2(0), GIMT_Encode2(GICP_gi_buf_soffset),
        // (SItbuffer_load:{ *:[v4i32] } v4i32:{ *:[v4i32] }:$rsrc, 0:{ *:[i32] }, i32:{ *:[i32] }:$voffset, (BUFSOffset:{ *:[i32] } i32:{ *:[i32] }:$soffset), (timm:{ *:[i32] }):$offset, (timm:{ *:[i32] }):$format, (timm:{ *:[i32] }):$auxiliary, 0:{ *:[i1] })  =>  (TBUFFER_LOAD_FORMAT_XYZW_OFFEN:{ *:[v4i32] } VGPR_32:{ *:[i32] }:$voffset, SReg_128:{ *:[v4i32] }:$rsrc, SCSrc_b32:{ *:[i32] }:$soffset, (timm:{ *:[i32] }):$offset, (as_i8timm:{ *:[i8] } ?:{ *:[i32] }:$format), (extract_cpol:{ *:[i32] } ?:{ *:[i32] }:$auxiliary), (extract_swz:{ *:[i1] } ?:{ *:[i32] }:$auxiliary))
        GIR_BuildMI, /*InsnID*/0, /*Opcode*/GIMT_Encode2(AMDGPU::TBUFFER_LOAD_FORMAT_XYZW_OFFEN),
        GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/0, // DstI[vdata]
        GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/3, // voffset
        GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/1, // rsrc
        GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/0, // soffset
        GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/5, // offset
        GIR_CustomOperandRenderer, /*InsnID*/0, /*OldInsnID*/0, /*OpIdx*/6, /*OperandRenderer*/GIMT_Encode2(GICR_renderTruncTImm), // format
        GIR_CustomOperandRenderer, /*InsnID*/0, /*OldInsnID*/0, /*OpIdx*/7, /*OperandRenderer*/GIMT_Encode2(GICR_renderExtractCPol), // auxiliary
        GIR_CustomOperandRenderer, /*InsnID*/0, /*OldInsnID*/0, /*OpIdx*/7, /*OperandRenderer*/GIMT_Encode2(GICR_renderExtractSWZ), // auxiliary
        GIR_MergeMemOperands, /*InsnID*/0, /*NumInsns*/1, /*MergeInsnID's*/0,
        GIR_ConstrainSelectedInstOperands, /*InsnID*/0,
        GIR_EraseFromParent, /*InsnID*/0,
        // GIR_Coverage, 5595,
        GIR_Done,
      // Label 7271: @530661
      GIM_Try, /*On fail goto*//*Label 7272*/ GIMT_Encode4(530749), // Rule ID 5599 //
        GIM_CheckConstantInt8, /*MI*/0, /*Op*/2, 0,
        // MIs[0] offset
        GIM_CheckIsImm, /*MI*/0, /*Op*/5,
        // MIs[0] format
        GIM_CheckIsImm, /*MI*/0, /*Op*/6,
        // MIs[0] auxiliary
        GIM_CheckIsImm, /*MI*/0, /*Op*/7,
        // MIs[0] Operand 8
        GIM_CheckLiteralInt, /*MI*/0, /*Op*/8, GIMT_Encode8(0),
        GIM_CheckComplexPattern, /*MI*/0, /*Op*/4, /*Renderer*/GIMT_Encode2(0), GIMT_Encode2(GICP_gi_buf_soffset),
        // (SItbuffer_load:{ *:[v4i32] } v4i32:{ *:[v4i32] }:$rsrc, 0:{ *:[i32] }, i32:{ *:[i32] }:$voffset, (BUFSOffset:{ *:[i32] } i32:{ *:[i32] }:$soffset), (timm:{ *:[i32] }):$offset, (timm:{ *:[i32] }):$format, (timm:{ *:[i32] }):$auxiliary, 0:{ *:[i1] })  =>  (TBUFFER_LOAD_FORMAT_XYZW_VBUFFER_OFFEN:{ *:[v4i32] } VGPR_32:{ *:[i32] }:$voffset, SReg_128:{ *:[v4i32] }:$rsrc, SCSrc_b32:{ *:[i32] }:$soffset, (timm:{ *:[i32] }):$offset, (as_i8timm:{ *:[i8] } ?:{ *:[i32] }:$format), (extract_cpol:{ *:[i32] } ?:{ *:[i32] }:$auxiliary), (extract_swz:{ *:[i1] } ?:{ *:[i32] }:$auxiliary))
        GIR_BuildMI, /*InsnID*/0, /*Opcode*/GIMT_Encode2(AMDGPU::TBUFFER_LOAD_FORMAT_XYZW_VBUFFER_OFFEN),
        GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/0, // DstI[vdata]
        GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/3, // voffset
        GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/1, // rsrc
        GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/0, // soffset
        GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/5, // offset
        GIR_CustomOperandRenderer, /*InsnID*/0, /*OldInsnID*/0, /*OpIdx*/6, /*OperandRenderer*/GIMT_Encode2(GICR_renderTruncTImm), // format
        GIR_CustomOperandRenderer, /*InsnID*/0, /*OldInsnID*/0, /*OpIdx*/7, /*OperandRenderer*/GIMT_Encode2(GICR_renderExtractCPol), // auxiliary
        GIR_CustomOperandRenderer, /*InsnID*/0, /*OldInsnID*/0, /*OpIdx*/7, /*OperandRenderer*/GIMT_Encode2(GICR_renderExtractSWZ), // auxiliary
        GIR_MergeMemOperands, /*InsnID*/0, /*NumInsns*/1, /*MergeInsnID's*/0,
        GIR_ConstrainSelectedInstOperands, /*InsnID*/0,
        GIR_EraseFromParent, /*InsnID*/0,
        // GIR_Coverage, 5599,
        GIR_Done,
      // Label 7272: @530749
      GIM_Try, /*On fail goto*//*Label 7273*/ GIMT_Encode4(530840), // Rule ID 5627 //
        GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasUnrestrictedSOffset),
        GIM_CheckConstantInt8, /*MI*/0, /*Op*/2, 0,
        // MIs[0] offset
        GIM_CheckIsImm, /*MI*/0, /*Op*/5,
        // MIs[0] format
        GIM_CheckIsImm, /*MI*/0, /*Op*/6,
        // MIs[0] auxiliary
        GIM_CheckIsImm, /*MI*/0, /*Op*/7,
        // MIs[0] Operand 8
        GIM_CheckLiteralInt, /*MI*/0, /*Op*/8, GIMT_Encode8(0),
        GIM_CheckComplexPattern, /*MI*/0, /*Op*/4, /*Renderer*/GIMT_Encode2(0), GIMT_Encode2(GICP_gi_buf_soffset),
        // (SItbuffer_load:{ *:[v4f32] } v4i32:{ *:[v4i32] }:$rsrc, 0:{ *:[i32] }, i32:{ *:[i32] }:$voffset, (BUFSOffset:{ *:[i32] } i32:{ *:[i32] }:$soffset), (timm:{ *:[i32] }):$offset, (timm:{ *:[i32] }):$format, (timm:{ *:[i32] }):$auxiliary, 0:{ *:[i1] })  =>  (TBUFFER_LOAD_FORMAT_XYZW_OFFEN:{ *:[v4f32] } VGPR_32:{ *:[i32] }:$voffset, SReg_128:{ *:[v4i32] }:$rsrc, SCSrc_b32:{ *:[i32] }:$soffset, (timm:{ *:[i32] }):$offset, (as_i8timm:{ *:[i8] } ?:{ *:[i32] }:$format), (extract_cpol:{ *:[i32] } ?:{ *:[i32] }:$auxiliary), (extract_swz:{ *:[i1] } ?:{ *:[i32] }:$auxiliary))
        GIR_BuildMI, /*InsnID*/0, /*Opcode*/GIMT_Encode2(AMDGPU::TBUFFER_LOAD_FORMAT_XYZW_OFFEN),
        GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/0, // DstI[vdata]
        GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/3, // voffset
        GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/1, // rsrc
        GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/0, // soffset
        GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/5, // offset
        GIR_CustomOperandRenderer, /*InsnID*/0, /*OldInsnID*/0, /*OpIdx*/6, /*OperandRenderer*/GIMT_Encode2(GICR_renderTruncTImm), // format
        GIR_CustomOperandRenderer, /*InsnID*/0, /*OldInsnID*/0, /*OpIdx*/7, /*OperandRenderer*/GIMT_Encode2(GICR_renderExtractCPol), // auxiliary
        GIR_CustomOperandRenderer, /*InsnID*/0, /*OldInsnID*/0, /*OpIdx*/7, /*OperandRenderer*/GIMT_Encode2(GICR_renderExtractSWZ), // auxiliary
        GIR_MergeMemOperands, /*InsnID*/0, /*NumInsns*/1, /*MergeInsnID's*/0,
        GIR_ConstrainSelectedInstOperands, /*InsnID*/0,
        GIR_EraseFromParent, /*InsnID*/0,
        // GIR_Coverage, 5627,
        GIR_Done,
      // Label 7273: @530840
      GIM_Try, /*On fail goto*//*Label 7274*/ GIMT_Encode4(530928), // Rule ID 5631 //
        GIM_CheckConstantInt8, /*MI*/0, /*Op*/2, 0,
        // MIs[0] offset
        GIM_CheckIsImm, /*MI*/0, /*Op*/5,
        // MIs[0] format
        GIM_CheckIsImm, /*MI*/0, /*Op*/6,
        // MIs[0] auxiliary
        GIM_CheckIsImm, /*MI*/0, /*Op*/7,
        // MIs[0] Operand 8
        GIM_CheckLiteralInt, /*MI*/0, /*Op*/8, GIMT_Encode8(0),
        GIM_CheckComplexPattern, /*MI*/0, /*Op*/4, /*Renderer*/GIMT_Encode2(0), GIMT_Encode2(GICP_gi_buf_soffset),
        // (SItbuffer_load:{ *:[v4f32] } v4i32:{ *:[v4i32] }:$rsrc, 0:{ *:[i32] }, i32:{ *:[i32] }:$voffset, (BUFSOffset:{ *:[i32] } i32:{ *:[i32] }:$soffset), (timm:{ *:[i32] }):$offset, (timm:{ *:[i32] }):$format, (timm:{ *:[i32] }):$auxiliary, 0:{ *:[i1] })  =>  (TBUFFER_LOAD_FORMAT_XYZW_VBUFFER_OFFEN:{ *:[v4f32] } VGPR_32:{ *:[i32] }:$voffset, SReg_128:{ *:[v4i32] }:$rsrc, SCSrc_b32:{ *:[i32] }:$soffset, (timm:{ *:[i32] }):$offset, (as_i8timm:{ *:[i8] } ?:{ *:[i32] }:$format), (extract_cpol:{ *:[i32] } ?:{ *:[i32] }:$auxiliary), (extract_swz:{ *:[i1] } ?:{ *:[i32] }:$auxiliary))
        GIR_BuildMI, /*InsnID*/0, /*Opcode*/GIMT_Encode2(AMDGPU::TBUFFER_LOAD_FORMAT_XYZW_VBUFFER_OFFEN),
        GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/0, // DstI[vdata]
        GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/3, // voffset
        GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/1, // rsrc
        GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/0, // soffset
        GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/5, // offset
        GIR_CustomOperandRenderer, /*InsnID*/0, /*OldInsnID*/0, /*OpIdx*/6, /*OperandRenderer*/GIMT_Encode2(GICR_renderTruncTImm), // format
        GIR_CustomOperandRenderer, /*InsnID*/0, /*OldInsnID*/0, /*OpIdx*/7, /*OperandRenderer*/GIMT_Encode2(GICR_renderExtractCPol), // auxiliary
        GIR_CustomOperandRenderer, /*InsnID*/0, /*OldInsnID*/0, /*OpIdx*/7, /*OperandRenderer*/GIMT_Encode2(GICR_renderExtractSWZ), // auxiliary
        GIR_MergeMemOperands, /*InsnID*/0, /*NumInsns*/1, /*MergeInsnID's*/0,
        GIR_ConstrainSelectedInstOperands, /*InsnID*/0,
        GIR_EraseFromParent, /*InsnID*/0,
        // GIR_Coverage, 5631,
        GIR_Done,
      // Label 7274: @530928
      GIM_Try, /*On fail goto*//*Label 7275*/ GIMT_Encode4(531011), // Rule ID 5594 //
        GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasUnrestrictedSOffset),
        GIM_CheckConstantInt8, /*MI*/0, /*Op*/3, 0,
        // MIs[0] offset
        GIM_CheckIsImm, /*MI*/0, /*Op*/5,
        // MIs[0] format
        GIM_CheckIsImm, /*MI*/0, /*Op*/6,
        // MIs[0] auxiliary
        GIM_CheckIsImm, /*MI*/0, /*Op*/7,
        // MIs[0] Operand 8
        GIM_CheckIsImm, /*MI*/0, /*Op*/8,
        GIM_CheckComplexPattern, /*MI*/0, /*Op*/4, /*Renderer*/GIMT_Encode2(0), GIMT_Encode2(GICP_gi_buf_soffset),
        // (SItbuffer_load:{ *:[v4i32] } v4i32:{ *:[v4i32] }:$rsrc, i32:{ *:[i32] }:$vindex, 0:{ *:[i32] }, (BUFSOffset:{ *:[i32] } i32:{ *:[i32] }:$soffset), (timm:{ *:[i32] }):$offset, (timm:{ *:[i32] }):$format, (timm:{ *:[i32] }):$auxiliary, (timm:{ *:[i1] }))  =>  (TBUFFER_LOAD_FORMAT_XYZW_IDXEN:{ *:[v4i32] } VGPR_32:{ *:[i32] }:$vindex, SReg_128:{ *:[v4i32] }:$rsrc, SCSrc_b32:{ *:[i32] }:$soffset, (timm:{ *:[i32] }):$offset, (as_i8timm:{ *:[i8] } ?:{ *:[i32] }:$format), (extract_cpol:{ *:[i32] } ?:{ *:[i32] }:$auxiliary), (extract_swz:{ *:[i1] } ?:{ *:[i32] }:$auxiliary))
        GIR_BuildMI, /*InsnID*/0, /*Opcode*/GIMT_Encode2(AMDGPU::TBUFFER_LOAD_FORMAT_XYZW_IDXEN),
        GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/0, // DstI[vdata]
        GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/2, // vindex
        GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/1, // rsrc
        GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/0, // soffset
        GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/5, // offset
        GIR_CustomOperandRenderer, /*InsnID*/0, /*OldInsnID*/0, /*OpIdx*/6, /*OperandRenderer*/GIMT_Encode2(GICR_renderTruncTImm), // format
        GIR_CustomOperandRenderer, /*InsnID*/0, /*OldInsnID*/0, /*OpIdx*/7, /*OperandRenderer*/GIMT_Encode2(GICR_renderExtractCPol), // auxiliary
        GIR_CustomOperandRenderer, /*InsnID*/0, /*OldInsnID*/0, /*OpIdx*/7, /*OperandRenderer*/GIMT_Encode2(GICR_renderExtractSWZ), // auxiliary
        GIR_MergeMemOperands, /*InsnID*/0, /*NumInsns*/1, /*MergeInsnID's*/0,
        GIR_ConstrainSelectedInstOperands, /*InsnID*/0,
        GIR_EraseFromParent, /*InsnID*/0,
        // GIR_Coverage, 5594,
        GIR_Done,
      // Label 7275: @531011
      GIM_Try, /*On fail goto*//*Label 7276*/ GIMT_Encode4(531091), // Rule ID 5598 //
        GIM_CheckConstantInt8, /*MI*/0, /*Op*/3, 0,
        // MIs[0] offset
        GIM_CheckIsImm, /*MI*/0, /*Op*/5,
        // MIs[0] format
        GIM_CheckIsImm, /*MI*/0, /*Op*/6,
        // MIs[0] auxiliary
        GIM_CheckIsImm, /*MI*/0, /*Op*/7,
        // MIs[0] Operand 8
        GIM_CheckIsImm, /*MI*/0, /*Op*/8,
        GIM_CheckComplexPattern, /*MI*/0, /*Op*/4, /*Renderer*/GIMT_Encode2(0), GIMT_Encode2(GICP_gi_buf_soffset),
        // (SItbuffer_load:{ *:[v4i32] } v4i32:{ *:[v4i32] }:$rsrc, i32:{ *:[i32] }:$vindex, 0:{ *:[i32] }, (BUFSOffset:{ *:[i32] } i32:{ *:[i32] }:$soffset), (timm:{ *:[i32] }):$offset, (timm:{ *:[i32] }):$format, (timm:{ *:[i32] }):$auxiliary, (timm:{ *:[i1] }))  =>  (TBUFFER_LOAD_FORMAT_XYZW_VBUFFER_IDXEN:{ *:[v4i32] } VGPR_32:{ *:[i32] }:$vindex, SReg_128:{ *:[v4i32] }:$rsrc, SCSrc_b32:{ *:[i32] }:$soffset, (timm:{ *:[i32] }):$offset, (as_i8timm:{ *:[i8] } ?:{ *:[i32] }:$format), (extract_cpol:{ *:[i32] } ?:{ *:[i32] }:$auxiliary), (extract_swz:{ *:[i1] } ?:{ *:[i32] }:$auxiliary))
        GIR_BuildMI, /*InsnID*/0, /*Opcode*/GIMT_Encode2(AMDGPU::TBUFFER_LOAD_FORMAT_XYZW_VBUFFER_IDXEN),
        GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/0, // DstI[vdata]
        GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/2, // vindex
        GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/1, // rsrc
        GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/0, // soffset
        GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/5, // offset
        GIR_CustomOperandRenderer, /*InsnID*/0, /*OldInsnID*/0, /*OpIdx*/6, /*OperandRenderer*/GIMT_Encode2(GICR_renderTruncTImm), // format
        GIR_CustomOperandRenderer, /*InsnID*/0, /*OldInsnID*/0, /*OpIdx*/7, /*OperandRenderer*/GIMT_Encode2(GICR_renderExtractCPol), // auxiliary
        GIR_CustomOperandRenderer, /*InsnID*/0, /*OldInsnID*/0, /*OpIdx*/7, /*OperandRenderer*/GIMT_Encode2(GICR_renderExtractSWZ), // auxiliary
        GIR_MergeMemOperands, /*InsnID*/0, /*NumInsns*/1, /*MergeInsnID's*/0,
        GIR_ConstrainSelectedInstOperands, /*InsnID*/0,
        GIR_EraseFromParent, /*InsnID*/0,
        // GIR_Coverage, 5598,
        GIR_Done,
      // Label 7276: @531091
      GIM_Try, /*On fail goto*//*Label 7277*/ GIMT_Encode4(531174), // Rule ID 5626 //
        GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasUnrestrictedSOffset),
        GIM_CheckConstantInt8, /*MI*/0, /*Op*/3, 0,
        // MIs[0] offset
        GIM_CheckIsImm, /*MI*/0, /*Op*/5,
        // MIs[0] format
        GIM_CheckIsImm, /*MI*/0, /*Op*/6,
        // MIs[0] auxiliary
        GIM_CheckIsImm, /*MI*/0, /*Op*/7,
        // MIs[0] Operand 8
        GIM_CheckIsImm, /*MI*/0, /*Op*/8,
        GIM_CheckComplexPattern, /*MI*/0, /*Op*/4, /*Renderer*/GIMT_Encode2(0), GIMT_Encode2(GICP_gi_buf_soffset),
        // (SItbuffer_load:{ *:[v4f32] } v4i32:{ *:[v4i32] }:$rsrc, i32:{ *:[i32] }:$vindex, 0:{ *:[i32] }, (BUFSOffset:{ *:[i32] } i32:{ *:[i32] }:$soffset), (timm:{ *:[i32] }):$offset, (timm:{ *:[i32] }):$format, (timm:{ *:[i32] }):$auxiliary, (timm:{ *:[i1] }))  =>  (TBUFFER_LOAD_FORMAT_XYZW_IDXEN:{ *:[v4f32] } VGPR_32:{ *:[i32] }:$vindex, SReg_128:{ *:[v4i32] }:$rsrc, SCSrc_b32:{ *:[i32] }:$soffset, (timm:{ *:[i32] }):$offset, (as_i8timm:{ *:[i8] } ?:{ *:[i32] }:$format), (extract_cpol:{ *:[i32] } ?:{ *:[i32] }:$auxiliary), (extract_swz:{ *:[i1] } ?:{ *:[i32] }:$auxiliary))
        GIR_BuildMI, /*InsnID*/0, /*Opcode*/GIMT_Encode2(AMDGPU::TBUFFER_LOAD_FORMAT_XYZW_IDXEN),
        GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/0, // DstI[vdata]
        GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/2, // vindex
        GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/1, // rsrc
        GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/0, // soffset
        GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/5, // offset
        GIR_CustomOperandRenderer, /*InsnID*/0, /*OldInsnID*/0, /*OpIdx*/6, /*OperandRenderer*/GIMT_Encode2(GICR_renderTruncTImm), // format
        GIR_CustomOperandRenderer, /*InsnID*/0, /*OldInsnID*/0, /*OpIdx*/7, /*OperandRenderer*/GIMT_Encode2(GICR_renderExtractCPol), // auxiliary
        GIR_CustomOperandRenderer, /*InsnID*/0, /*OldInsnID*/0, /*OpIdx*/7, /*OperandRenderer*/GIMT_Encode2(GICR_renderExtractSWZ), // auxiliary
        GIR_MergeMemOperands, /*InsnID*/0, /*NumInsns*/1, /*MergeInsnID's*/0,
        GIR_ConstrainSelectedInstOperands, /*InsnID*/0,
        GIR_EraseFromParent, /*InsnID*/0,
        // GIR_Coverage, 5626,
        GIR_Done,
      // Label 7277: @531174
      GIM_Try, /*On fail goto*//*Label 7278*/ GIMT_Encode4(531254), // Rule ID 5630 //
        GIM_CheckConstantInt8, /*MI*/0, /*Op*/3, 0,
        // MIs[0] offset
        GIM_CheckIsImm, /*MI*/0, /*Op*/5,
        // MIs[0] format
        GIM_CheckIsImm, /*MI*/0, /*Op*/6,
        // MIs[0] auxiliary
        GIM_CheckIsImm, /*MI*/0, /*Op*/7,
        // MIs[0] Operand 8
        GIM_CheckIsImm, /*MI*/0, /*Op*/8,
        GIM_CheckComplexPattern, /*MI*/0, /*Op*/4, /*Renderer*/GIMT_Encode2(0), GIMT_Encode2(GICP_gi_buf_soffset),
        // (SItbuffer_load:{ *:[v4f32] } v4i32:{ *:[v4i32] }:$rsrc, i32:{ *:[i32] }:$vindex, 0:{ *:[i32] }, (BUFSOffset:{ *:[i32] } i32:{ *:[i32] }:$soffset), (timm:{ *:[i32] }):$offset, (timm:{ *:[i32] }):$format, (timm:{ *:[i32] }):$auxiliary, (timm:{ *:[i1] }))  =>  (TBUFFER_LOAD_FORMAT_XYZW_VBUFFER_IDXEN:{ *:[v4f32] } VGPR_32:{ *:[i32] }:$vindex, SReg_128:{ *:[v4i32] }:$rsrc, SCSrc_b32:{ *:[i32] }:$soffset, (timm:{ *:[i32] }):$offset, (as_i8timm:{ *:[i8] } ?:{ *:[i32] }:$format), (extract_cpol:{ *:[i32] } ?:{ *:[i32] }:$auxiliary), (extract_swz:{ *:[i1] } ?:{ *:[i32] }:$auxiliary))
        GIR_BuildMI, /*InsnID*/0, /*Opcode*/GIMT_Encode2(AMDGPU::TBUFFER_LOAD_FORMAT_XYZW_VBUFFER_IDXEN),
        GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/0, // DstI[vdata]
        GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/2, // vindex
        GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/1, // rsrc
        GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/0, // soffset
        GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/5, // offset
        GIR_CustomOperandRenderer, /*InsnID*/0, /*OldInsnID*/0, /*OpIdx*/6, /*OperandRenderer*/GIMT_Encode2(GICR_renderTruncTImm), // format
        GIR_CustomOperandRenderer, /*InsnID*/0, /*OldInsnID*/0, /*OpIdx*/7, /*OperandRenderer*/GIMT_Encode2(GICR_renderExtractCPol), // auxiliary
        GIR_CustomOperandRenderer, /*InsnID*/0, /*OldInsnID*/0, /*OpIdx*/7, /*OperandRenderer*/GIMT_Encode2(GICR_renderExtractSWZ), // auxiliary
        GIR_MergeMemOperands, /*InsnID*/0, /*NumInsns*/1, /*MergeInsnID's*/0,
        GIR_ConstrainSelectedInstOperands, /*InsnID*/0,
        GIR_EraseFromParent, /*InsnID*/0,
        // GIR_Coverage, 5630,
        GIR_Done,
      // Label 7278: @531254
      GIM_Try, /*On fail goto*//*Label 7279*/ GIMT_Encode4(531373), // Rule ID 5596 //
        GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasUnrestrictedSOffset),
        // MIs[0] offset
        GIM_CheckIsImm, /*MI*/0, /*Op*/5,
        // MIs[0] format
        GIM_CheckIsImm, /*MI*/0, /*Op*/6,
        // MIs[0] auxiliary
        GIM_CheckIsImm, /*MI*/0, /*Op*/7,
        // MIs[0] Operand 8
        GIM_CheckIsImm, /*MI*/0, /*Op*/8,
        GIM_CheckComplexPattern, /*MI*/0, /*Op*/4, /*Renderer*/GIMT_Encode2(0), GIMT_Encode2(GICP_gi_buf_soffset),
        // (SItbuffer_load:{ *:[v4i32] } v4i32:{ *:[v4i32] }:$rsrc, i32:{ *:[i32] }:$vindex, i32:{ *:[i32] }:$voffset, (BUFSOffset:{ *:[i32] } i32:{ *:[i32] }:$soffset), (timm:{ *:[i32] }):$offset, (timm:{ *:[i32] }):$format, (timm:{ *:[i32] }):$auxiliary, (timm:{ *:[i1] }))  =>  (TBUFFER_LOAD_FORMAT_XYZW_BOTHEN:{ *:[v4i32] } (REG_SEQUENCE:{ *:[i64] } VReg_64:{ *:[i32] }, VGPR_32:{ *:[i32] }:$vindex, sub0:{ *:[i32] }, VGPR_32:{ *:[i32] }:$voffset, sub1:{ *:[i32] }), SReg_128:{ *:[v4i32] }:$rsrc, SCSrc_b32:{ *:[i32] }:$soffset, (timm:{ *:[i32] }):$offset, (as_i8timm:{ *:[i8] } ?:{ *:[i32] }:$format), (extract_cpol:{ *:[i32] } ?:{ *:[i32] }:$auxiliary), (extract_swz:{ *:[i1] } ?:{ *:[i32] }:$auxiliary))
        GIR_MakeTempReg, /*TempRegID*/0, /*TypeID*/GILLT_s64,
        GIR_BuildMI, /*InsnID*/1, /*Opcode*/GIMT_Encode2(TargetOpcode::REG_SEQUENCE),
        GIR_AddTempRegister, /*InsnID*/1, /*TempRegID*/0, /*TempRegFlags*/GIMT_Encode2(RegState::Define),
        GIR_Copy, /*NewInsnID*/1, /*OldInsnID*/0, /*OpIdx*/2, // vindex
        GIR_AddImm8, /*InsnID*/1, /*SubRegIndex*/3,
        GIR_Copy, /*NewInsnID*/1, /*OldInsnID*/0, /*OpIdx*/3, // voffset
        GIR_AddImm8, /*InsnID*/1, /*SubRegIndex*/11,
        GIR_ConstrainOperandRC, /*InsnID*/1, /*Op*/0, GIMT_Encode2(AMDGPU::VReg_64RegClassID),
        GIR_ConstrainOperandRC, /*InsnID*/1, /*Op*/1, GIMT_Encode2(AMDGPU::VGPR_32RegClassID),
        GIR_ConstrainOperandRC, /*InsnID*/1, /*Op*/3, GIMT_Encode2(AMDGPU::VGPR_32RegClassID),
        GIR_BuildMI, /*InsnID*/0, /*Opcode*/GIMT_Encode2(AMDGPU::TBUFFER_LOAD_FORMAT_XYZW_BOTHEN),
        GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/0, // DstI[vdata]
        GIR_AddSimpleTempRegister, /*InsnID*/0, /*TempRegID*/0,
        GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/1, // rsrc
        GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/0, // soffset
        GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/5, // offset
        GIR_CustomOperandRenderer, /*InsnID*/0, /*OldInsnID*/0, /*OpIdx*/6, /*OperandRenderer*/GIMT_Encode2(GICR_renderTruncTImm), // format
        GIR_CustomOperandRenderer, /*InsnID*/0, /*OldInsnID*/0, /*OpIdx*/7, /*OperandRenderer*/GIMT_Encode2(GICR_renderExtractCPol), // auxiliary
        GIR_CustomOperandRenderer, /*InsnID*/0, /*OldInsnID*/0, /*OpIdx*/7, /*OperandRenderer*/GIMT_Encode2(GICR_renderExtractSWZ), // auxiliary
        GIR_MergeMemOperands, /*InsnID*/0, /*NumInsns*/1, /*MergeInsnID's*/0,
        GIR_ConstrainSelectedInstOperands, /*InsnID*/0,
        GIR_EraseFromParent, /*InsnID*/0,
        // GIR_Coverage, 5596,
        GIR_Done,
      // Label 7279: @531373
      GIM_Try, /*On fail goto*//*Label 7280*/ GIMT_Encode4(531489), // Rule ID 5600 //
        // MIs[0] offset
        GIM_CheckIsImm, /*MI*/0, /*Op*/5,
        // MIs[0] format
        GIM_CheckIsImm, /*MI*/0, /*Op*/6,
        // MIs[0] auxiliary
        GIM_CheckIsImm, /*MI*/0, /*Op*/7,
        // MIs[0] Operand 8
        GIM_CheckIsImm, /*MI*/0, /*Op*/8,
        GIM_CheckComplexPattern, /*MI*/0, /*Op*/4, /*Renderer*/GIMT_Encode2(0), GIMT_Encode2(GICP_gi_buf_soffset),
        // (SItbuffer_load:{ *:[v4i32] } v4i32:{ *:[v4i32] }:$rsrc, i32:{ *:[i32] }:$vindex, i32:{ *:[i32] }:$voffset, (BUFSOffset:{ *:[i32] } i32:{ *:[i32] }:$soffset), (timm:{ *:[i32] }):$offset, (timm:{ *:[i32] }):$format, (timm:{ *:[i32] }):$auxiliary, (timm:{ *:[i1] }))  =>  (TBUFFER_LOAD_FORMAT_XYZW_VBUFFER_BOTHEN:{ *:[v4i32] } (REG_SEQUENCE:{ *:[i64] } VReg_64:{ *:[i32] }, VGPR_32:{ *:[i32] }:$vindex, sub0:{ *:[i32] }, VGPR_32:{ *:[i32] }:$voffset, sub1:{ *:[i32] }), SReg_128:{ *:[v4i32] }:$rsrc, SCSrc_b32:{ *:[i32] }:$soffset, (timm:{ *:[i32] }):$offset, (as_i8timm:{ *:[i8] } ?:{ *:[i32] }:$format), (extract_cpol:{ *:[i32] } ?:{ *:[i32] }:$auxiliary), (extract_swz:{ *:[i1] } ?:{ *:[i32] }:$auxiliary))
        GIR_MakeTempReg, /*TempRegID*/0, /*TypeID*/GILLT_s64,
        GIR_BuildMI, /*InsnID*/1, /*Opcode*/GIMT_Encode2(TargetOpcode::REG_SEQUENCE),
        GIR_AddTempRegister, /*InsnID*/1, /*TempRegID*/0, /*TempRegFlags*/GIMT_Encode2(RegState::Define),
        GIR_Copy, /*NewInsnID*/1, /*OldInsnID*/0, /*OpIdx*/2, // vindex
        GIR_AddImm8, /*InsnID*/1, /*SubRegIndex*/3,
        GIR_Copy, /*NewInsnID*/1, /*OldInsnID*/0, /*OpIdx*/3, // voffset
        GIR_AddImm8, /*InsnID*/1, /*SubRegIndex*/11,
        GIR_ConstrainOperandRC, /*InsnID*/1, /*Op*/0, GIMT_Encode2(AMDGPU::VReg_64RegClassID),
        GIR_ConstrainOperandRC, /*InsnID*/1, /*Op*/1, GIMT_Encode2(AMDGPU::VGPR_32RegClassID),
        GIR_ConstrainOperandRC, /*InsnID*/1, /*Op*/3, GIMT_Encode2(AMDGPU::VGPR_32RegClassID),
        GIR_BuildMI, /*InsnID*/0, /*Opcode*/GIMT_Encode2(AMDGPU::TBUFFER_LOAD_FORMAT_XYZW_VBUFFER_BOTHEN),
        GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/0, // DstI[vdata]
        GIR_AddSimpleTempRegister, /*InsnID*/0, /*TempRegID*/0,
        GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/1, // rsrc
        GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/0, // soffset
        GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/5, // offset
        GIR_CustomOperandRenderer, /*InsnID*/0, /*OldInsnID*/0, /*OpIdx*/6, /*OperandRenderer*/GIMT_Encode2(GICR_renderTruncTImm), // format
        GIR_CustomOperandRenderer, /*InsnID*/0, /*OldInsnID*/0, /*OpIdx*/7, /*OperandRenderer*/GIMT_Encode2(GICR_renderExtractCPol), // auxiliary
        GIR_CustomOperandRenderer, /*InsnID*/0, /*OldInsnID*/0, /*OpIdx*/7, /*OperandRenderer*/GIMT_Encode2(GICR_renderExtractSWZ), // auxiliary
        GIR_MergeMemOperands, /*InsnID*/0, /*NumInsns*/1, /*MergeInsnID's*/0,
        GIR_ConstrainSelectedInstOperands, /*InsnID*/0,
        GIR_EraseFromParent, /*InsnID*/0,
        // GIR_Coverage, 5600,
        GIR_Done,
      // Label 7280: @531489
      GIM_Try, /*On fail goto*//*Label 7281*/ GIMT_Encode4(531608), // Rule ID 5628 //
        GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasUnrestrictedSOffset),
        // MIs[0] offset
        GIM_CheckIsImm, /*MI*/0, /*Op*/5,
        // MIs[0] format
        GIM_CheckIsImm, /*MI*/0, /*Op*/6,
        // MIs[0] auxiliary
        GIM_CheckIsImm, /*MI*/0, /*Op*/7,
        // MIs[0] Operand 8
        GIM_CheckIsImm, /*MI*/0, /*Op*/8,
        GIM_CheckComplexPattern, /*MI*/0, /*Op*/4, /*Renderer*/GIMT_Encode2(0), GIMT_Encode2(GICP_gi_buf_soffset),
        // (SItbuffer_load:{ *:[v4f32] } v4i32:{ *:[v4i32] }:$rsrc, i32:{ *:[i32] }:$vindex, i32:{ *:[i32] }:$voffset, (BUFSOffset:{ *:[i32] } i32:{ *:[i32] }:$soffset), (timm:{ *:[i32] }):$offset, (timm:{ *:[i32] }):$format, (timm:{ *:[i32] }):$auxiliary, (timm:{ *:[i1] }))  =>  (TBUFFER_LOAD_FORMAT_XYZW_BOTHEN:{ *:[v4f32] } (REG_SEQUENCE:{ *:[i64] } VReg_64:{ *:[i32] }, VGPR_32:{ *:[i32] }:$vindex, sub0:{ *:[i32] }, VGPR_32:{ *:[i32] }:$voffset, sub1:{ *:[i32] }), SReg_128:{ *:[v4i32] }:$rsrc, SCSrc_b32:{ *:[i32] }:$soffset, (timm:{ *:[i32] }):$offset, (as_i8timm:{ *:[i8] } ?:{ *:[i32] }:$format), (extract_cpol:{ *:[i32] } ?:{ *:[i32] }:$auxiliary), (extract_swz:{ *:[i1] } ?:{ *:[i32] }:$auxiliary))
        GIR_MakeTempReg, /*TempRegID*/0, /*TypeID*/GILLT_s64,
        GIR_BuildMI, /*InsnID*/1, /*Opcode*/GIMT_Encode2(TargetOpcode::REG_SEQUENCE),
        GIR_AddTempRegister, /*InsnID*/1, /*TempRegID*/0, /*TempRegFlags*/GIMT_Encode2(RegState::Define),
        GIR_Copy, /*NewInsnID*/1, /*OldInsnID*/0, /*OpIdx*/2, // vindex
        GIR_AddImm8, /*InsnID*/1, /*SubRegIndex*/3,
        GIR_Copy, /*NewInsnID*/1, /*OldInsnID*/0, /*OpIdx*/3, // voffset
        GIR_AddImm8, /*InsnID*/1, /*SubRegIndex*/11,
        GIR_ConstrainOperandRC, /*InsnID*/1, /*Op*/0, GIMT_Encode2(AMDGPU::VReg_64RegClassID),
        GIR_ConstrainOperandRC, /*InsnID*/1, /*Op*/1, GIMT_Encode2(AMDGPU::VGPR_32RegClassID),
        GIR_ConstrainOperandRC, /*InsnID*/1, /*Op*/3, GIMT_Encode2(AMDGPU::VGPR_32RegClassID),
        GIR_BuildMI, /*InsnID*/0, /*Opcode*/GIMT_Encode2(AMDGPU::TBUFFER_LOAD_FORMAT_XYZW_BOTHEN),
        GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/0, // DstI[vdata]
        GIR_AddSimpleTempRegister, /*InsnID*/0, /*TempRegID*/0,
        GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/1, // rsrc
        GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/0, // soffset
        GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/5, // offset
        GIR_CustomOperandRenderer, /*InsnID*/0, /*OldInsnID*/0, /*OpIdx*/6, /*OperandRenderer*/GIMT_Encode2(GICR_renderTruncTImm), // format
        GIR_CustomOperandRenderer, /*InsnID*/0, /*OldInsnID*/0, /*OpIdx*/7, /*OperandRenderer*/GIMT_Encode2(GICR_renderExtractCPol), // auxiliary
        GIR_CustomOperandRenderer, /*InsnID*/0, /*OldInsnID*/0, /*OpIdx*/7, /*OperandRenderer*/GIMT_Encode2(GICR_renderExtractSWZ), // auxiliary
        GIR_MergeMemOperands, /*InsnID*/0, /*NumInsns*/1, /*MergeInsnID's*/0,
        GIR_ConstrainSelectedInstOperands, /*InsnID*/0,
        GIR_EraseFromParent, /*InsnID*/0,
        // GIR_Coverage, 5628,
        GIR_Done,
      // Label 7281: @531608
      GIM_Try, /*On fail goto*//*Label 7282*/ GIMT_Encode4(531724), // Rule ID 5632 //
        // MIs[0] offset
        GIM_CheckIsImm, /*MI*/0, /*Op*/5,
        // MIs[0] format
        GIM_CheckIsImm, /*MI*/0, /*Op*/6,
        // MIs[0] auxiliary
        GIM_CheckIsImm, /*MI*/0, /*Op*/7,
        // MIs[0] Operand 8
        GIM_CheckIsImm, /*MI*/0, /*Op*/8,
        GIM_CheckComplexPattern, /*MI*/0, /*Op*/4, /*Renderer*/GIMT_Encode2(0), GIMT_Encode2(GICP_gi_buf_soffset),
        // (SItbuffer_load:{ *:[v4f32] } v4i32:{ *:[v4i32] }:$rsrc, i32:{ *:[i32] }:$vindex, i32:{ *:[i32] }:$voffset, (BUFSOffset:{ *:[i32] } i32:{ *:[i32] }:$soffset), (timm:{ *:[i32] }):$offset, (timm:{ *:[i32] }):$format, (timm:{ *:[i32] }):$auxiliary, (timm:{ *:[i1] }))  =>  (TBUFFER_LOAD_FORMAT_XYZW_VBUFFER_BOTHEN:{ *:[v4f32] } (REG_SEQUENCE:{ *:[i64] } VReg_64:{ *:[i32] }, VGPR_32:{ *:[i32] }:$vindex, sub0:{ *:[i32] }, VGPR_32:{ *:[i32] }:$voffset, sub1:{ *:[i32] }), SReg_128:{ *:[v4i32] }:$rsrc, SCSrc_b32:{ *:[i32] }:$soffset, (timm:{ *:[i32] }):$offset, (as_i8timm:{ *:[i8] } ?:{ *:[i32] }:$format), (extract_cpol:{ *:[i32] } ?:{ *:[i32] }:$auxiliary), (extract_swz:{ *:[i1] } ?:{ *:[i32] }:$auxiliary))
        GIR_MakeTempReg, /*TempRegID*/0, /*TypeID*/GILLT_s64,
        GIR_BuildMI, /*InsnID*/1, /*Opcode*/GIMT_Encode2(TargetOpcode::REG_SEQUENCE),
        GIR_AddTempRegister, /*InsnID*/1, /*TempRegID*/0, /*TempRegFlags*/GIMT_Encode2(RegState::Define),
        GIR_Copy, /*NewInsnID*/1, /*OldInsnID*/0, /*OpIdx*/2, // vindex
        GIR_AddImm8, /*InsnID*/1, /*SubRegIndex*/3,
        GIR_Copy, /*NewInsnID*/1, /*OldInsnID*/0, /*OpIdx*/3, // voffset
        GIR_AddImm8, /*InsnID*/1, /*SubRegIndex*/11,
        GIR_ConstrainOperandRC, /*InsnID*/1, /*Op*/0, GIMT_Encode2(AMDGPU::VReg_64RegClassID),
        GIR_ConstrainOperandRC, /*InsnID*/1, /*Op*/1, GIMT_Encode2(AMDGPU::VGPR_32RegClassID),
        GIR_ConstrainOperandRC, /*InsnID*/1, /*Op*/3, GIMT_Encode2(AMDGPU::VGPR_32RegClassID),
        GIR_BuildMI, /*InsnID*/0, /*Opcode*/GIMT_Encode2(AMDGPU::TBUFFER_LOAD_FORMAT_XYZW_VBUFFER_BOTHEN),
        GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/0, // DstI[vdata]
        GIR_AddSimpleTempRegister, /*InsnID*/0, /*TempRegID*/0,
        GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/1, // rsrc
        GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/0, // soffset
        GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/5, // offset
        GIR_CustomOperandRenderer, /*InsnID*/0, /*OldInsnID*/0, /*OpIdx*/6, /*OperandRenderer*/GIMT_Encode2(GICR_renderTruncTImm), // format
        GIR_CustomOperandRenderer, /*InsnID*/0, /*OldInsnID*/0, /*OpIdx*/7, /*OperandRenderer*/GIMT_Encode2(GICR_renderExtractCPol), // auxiliary
        GIR_CustomOperandRenderer, /*InsnID*/0, /*OldInsnID*/0, /*OpIdx*/7, /*OperandRenderer*/GIMT_Encode2(GICR_renderExtractSWZ), // auxiliary
        GIR_MergeMemOperands, /*InsnID*/0, /*NumInsns*/1, /*MergeInsnID's*/0,
        GIR_ConstrainSelectedInstOperands, /*InsnID*/0,
        GIR_EraseFromParent, /*InsnID*/0,
        // GIR_Coverage, 5632,
        GIR_Done,
      // Label 7282: @531724
      GIM_Reject,
    // Label 7266: @531725
    GIM_Reject,
    // Label 7214: @531726
    GIM_Reject,
    // Label 156: @531727
    GIM_SwitchType, /*MI*/0, /*Op*/0, /*[*/GIMT_Encode2(8), GIMT_Encode2(18), /*)*//*default:*//*Label 7290*/ GIMT_Encode4(537865),
    /*GILLT_s16*//*Label 7283*/ GIMT_Encode4(531778),
    /*GILLT_s32*//*Label 7284*/ GIMT_Encode4(532958), GIMT_Encode4(0),
    /*GILLT_v2s16*//*Label 7285*/ GIMT_Encode4(534138),
    /*GILLT_v2s32*//*Label 7286*/ GIMT_Encode4(534934), GIMT_Encode4(0),
    /*GILLT_v3s32*//*Label 7287*/ GIMT_Encode4(535346), GIMT_Encode4(0),
    /*GILLT_v4s16*//*Label 7288*/ GIMT_Encode4(535758),
    /*GILLT_v4s32*//*Label 7289*/ GIMT_Encode4(537453),
    // Label 7283: @531778
    GIM_Try, /*On fail goto*//*Label 7291*/ GIMT_Encode4(532957),
      GIM_CheckType, /*MI*/0, /*Op*/1, /*Type*/GILLT_v4s32,
      GIM_CheckType, /*MI*/0, /*Op*/2, /*Type*/GILLT_s32,
      GIM_CheckType, /*MI*/0, /*Op*/3, /*Type*/GILLT_s32,
      GIM_CheckType, /*MI*/0, /*Op*/4, /*Type*/GILLT_s32,
      GIM_CheckRegBankForClass, /*MI*/0, /*Op*/0, /*RC*/GIMT_Encode2(AMDGPU::AV_32RegClassID),
      GIM_Try, /*On fail goto*//*Label 7292*/ GIMT_Encode4(531895), // Rule ID 5633 //
        GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasUnpackedD16VMem),
        GIM_CheckConstantInt8, /*MI*/0, /*Op*/2, 0,
        GIM_CheckConstantInt8, /*MI*/0, /*Op*/3, 0,
        // MIs[0] offset
        GIM_CheckIsImm, /*MI*/0, /*Op*/5,
        // MIs[0] format
        GIM_CheckIsImm, /*MI*/0, /*Op*/6,
        // MIs[0] auxiliary
        GIM_CheckIsImm, /*MI*/0, /*Op*/7,
        // MIs[0] Operand 8
        GIM_CheckLiteralInt, /*MI*/0, /*Op*/8, GIMT_Encode8(0),
        GIM_CheckComplexPattern, /*MI*/0, /*Op*/4, /*Renderer*/GIMT_Encode2(0), GIMT_Encode2(GICP_gi_buf_soffset),
        // (SItbuffer_load_d16:{ *:[f16] } v4i32:{ *:[v4i32] }:$rsrc, 0:{ *:[i32] }, 0:{ *:[i32] }, (BUFSOffset:{ *:[i32] } i32:{ *:[i32] }:$soffset), (timm:{ *:[i32] }):$offset, (timm:{ *:[i32] }):$format, (timm:{ *:[i32] }):$auxiliary, 0:{ *:[i1] })  =>  (TBUFFER_LOAD_FORMAT_D16_X_gfx80_OFFSET:{ *:[f16] } SReg_128:{ *:[v4i32] }:$rsrc, SCSrc_b32:{ *:[i32] }:$soffset, (timm:{ *:[i32] }):$offset, (as_i8timm:{ *:[i8] } ?:{ *:[i32] }:$format), (extract_cpol:{ *:[i32] } ?:{ *:[i32] }:$auxiliary), (extract_swz:{ *:[i1] } ?:{ *:[i32] }:$auxiliary))
        GIR_BuildMI, /*InsnID*/0, /*Opcode*/GIMT_Encode2(AMDGPU::TBUFFER_LOAD_FORMAT_D16_X_gfx80_OFFSET),
        GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/0, // DstI[vdata]
        GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/1, // rsrc
        GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/0, // soffset
        GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/5, // offset
        GIR_CustomOperandRenderer, /*InsnID*/0, /*OldInsnID*/0, /*OpIdx*/6, /*OperandRenderer*/GIMT_Encode2(GICR_renderTruncTImm), // format
        GIR_CustomOperandRenderer, /*InsnID*/0, /*OldInsnID*/0, /*OpIdx*/7, /*OperandRenderer*/GIMT_Encode2(GICR_renderExtractCPol), // auxiliary
        GIR_CustomOperandRenderer, /*InsnID*/0, /*OldInsnID*/0, /*OpIdx*/7, /*OperandRenderer*/GIMT_Encode2(GICR_renderExtractSWZ), // auxiliary
        GIR_MergeMemOperands, /*InsnID*/0, /*NumInsns*/1, /*MergeInsnID's*/0,
        GIR_ConstrainSelectedInstOperands, /*InsnID*/0,
        GIR_EraseFromParent, /*InsnID*/0,
        // GIR_Coverage, 5633,
        GIR_Done,
      // Label 7292: @531895
      GIM_Try, /*On fail goto*//*Label 7293*/ GIMT_Encode4(531986), // Rule ID 5653 //
        GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasPackedD16VMem_HasUnrestrictedSOffset),
        GIM_CheckConstantInt8, /*MI*/0, /*Op*/2, 0,
        GIM_CheckConstantInt8, /*MI*/0, /*Op*/3, 0,
        // MIs[0] offset
        GIM_CheckIsImm, /*MI*/0, /*Op*/5,
        // MIs[0] format
        GIM_CheckIsImm, /*MI*/0, /*Op*/6,
        // MIs[0] auxiliary
        GIM_CheckIsImm, /*MI*/0, /*Op*/7,
        // MIs[0] Operand 8
        GIM_CheckLiteralInt, /*MI*/0, /*Op*/8, GIMT_Encode8(0),
        GIM_CheckComplexPattern, /*MI*/0, /*Op*/4, /*Renderer*/GIMT_Encode2(0), GIMT_Encode2(GICP_gi_buf_soffset),
        // (SItbuffer_load_d16:{ *:[f16] } v4i32:{ *:[v4i32] }:$rsrc, 0:{ *:[i32] }, 0:{ *:[i32] }, (BUFSOffset:{ *:[i32] } i32:{ *:[i32] }:$soffset), (timm:{ *:[i32] }):$offset, (timm:{ *:[i32] }):$format, (timm:{ *:[i32] }):$auxiliary, 0:{ *:[i1] })  =>  (TBUFFER_LOAD_FORMAT_D16_X_OFFSET:{ *:[f16] } SReg_128:{ *:[v4i32] }:$rsrc, SCSrc_b32:{ *:[i32] }:$soffset, (timm:{ *:[i32] }):$offset, (as_i8timm:{ *:[i8] } ?:{ *:[i32] }:$format), (extract_cpol:{ *:[i32] } ?:{ *:[i32] }:$auxiliary), (extract_swz:{ *:[i1] } ?:{ *:[i32] }:$auxiliary))
        GIR_BuildMI, /*InsnID*/0, /*Opcode*/GIMT_Encode2(AMDGPU::TBUFFER_LOAD_FORMAT_D16_X_OFFSET),
        GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/0, // DstI[vdata]
        GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/1, // rsrc
        GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/0, // soffset
        GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/5, // offset
        GIR_CustomOperandRenderer, /*InsnID*/0, /*OldInsnID*/0, /*OpIdx*/6, /*OperandRenderer*/GIMT_Encode2(GICR_renderTruncTImm), // format
        GIR_CustomOperandRenderer, /*InsnID*/0, /*OldInsnID*/0, /*OpIdx*/7, /*OperandRenderer*/GIMT_Encode2(GICR_renderExtractCPol), // auxiliary
        GIR_CustomOperandRenderer, /*InsnID*/0, /*OldInsnID*/0, /*OpIdx*/7, /*OperandRenderer*/GIMT_Encode2(GICR_renderExtractSWZ), // auxiliary
        GIR_MergeMemOperands, /*InsnID*/0, /*NumInsns*/1, /*MergeInsnID's*/0,
        GIR_ConstrainSelectedInstOperands, /*InsnID*/0,
        GIR_EraseFromParent, /*InsnID*/0,
        // GIR_Coverage, 5653,
        GIR_Done,
      // Label 7293: @531986
      GIM_Try, /*On fail goto*//*Label 7294*/ GIMT_Encode4(532077), // Rule ID 5657 //
        GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasPackedD16VMem),
        GIM_CheckConstantInt8, /*MI*/0, /*Op*/2, 0,
        GIM_CheckConstantInt8, /*MI*/0, /*Op*/3, 0,
        // MIs[0] offset
        GIM_CheckIsImm, /*MI*/0, /*Op*/5,
        // MIs[0] format
        GIM_CheckIsImm, /*MI*/0, /*Op*/6,
        // MIs[0] auxiliary
        GIM_CheckIsImm, /*MI*/0, /*Op*/7,
        // MIs[0] Operand 8
        GIM_CheckLiteralInt, /*MI*/0, /*Op*/8, GIMT_Encode8(0),
        GIM_CheckComplexPattern, /*MI*/0, /*Op*/4, /*Renderer*/GIMT_Encode2(0), GIMT_Encode2(GICP_gi_buf_soffset),
        // (SItbuffer_load_d16:{ *:[f16] } v4i32:{ *:[v4i32] }:$rsrc, 0:{ *:[i32] }, 0:{ *:[i32] }, (BUFSOffset:{ *:[i32] } i32:{ *:[i32] }:$soffset), (timm:{ *:[i32] }):$offset, (timm:{ *:[i32] }):$format, (timm:{ *:[i32] }):$auxiliary, 0:{ *:[i1] })  =>  (TBUFFER_LOAD_FORMAT_D16_X_VBUFFER_OFFSET:{ *:[f16] } SReg_128:{ *:[v4i32] }:$rsrc, SCSrc_b32:{ *:[i32] }:$soffset, (timm:{ *:[i32] }):$offset, (as_i8timm:{ *:[i8] } ?:{ *:[i32] }:$format), (extract_cpol:{ *:[i32] } ?:{ *:[i32] }:$auxiliary), (extract_swz:{ *:[i1] } ?:{ *:[i32] }:$auxiliary))
        GIR_BuildMI, /*InsnID*/0, /*Opcode*/GIMT_Encode2(AMDGPU::TBUFFER_LOAD_FORMAT_D16_X_VBUFFER_OFFSET),
        GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/0, // DstI[vdata]
        GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/1, // rsrc
        GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/0, // soffset
        GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/5, // offset
        GIR_CustomOperandRenderer, /*InsnID*/0, /*OldInsnID*/0, /*OpIdx*/6, /*OperandRenderer*/GIMT_Encode2(GICR_renderTruncTImm), // format
        GIR_CustomOperandRenderer, /*InsnID*/0, /*OldInsnID*/0, /*OpIdx*/7, /*OperandRenderer*/GIMT_Encode2(GICR_renderExtractCPol), // auxiliary
        GIR_CustomOperandRenderer, /*InsnID*/0, /*OldInsnID*/0, /*OpIdx*/7, /*OperandRenderer*/GIMT_Encode2(GICR_renderExtractSWZ), // auxiliary
        GIR_MergeMemOperands, /*InsnID*/0, /*NumInsns*/1, /*MergeInsnID's*/0,
        GIR_ConstrainSelectedInstOperands, /*InsnID*/0,
        GIR_EraseFromParent, /*InsnID*/0,
        // GIR_Coverage, 5657,
        GIR_Done,
      // Label 7294: @532077
      GIM_Try, /*On fail goto*//*Label 7295*/ GIMT_Encode4(532168), // Rule ID 5635 //
        GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasUnpackedD16VMem),
        GIM_CheckConstantInt8, /*MI*/0, /*Op*/2, 0,
        // MIs[0] offset
        GIM_CheckIsImm, /*MI*/0, /*Op*/5,
        // MIs[0] format
        GIM_CheckIsImm, /*MI*/0, /*Op*/6,
        // MIs[0] auxiliary
        GIM_CheckIsImm, /*MI*/0, /*Op*/7,
        // MIs[0] Operand 8
        GIM_CheckLiteralInt, /*MI*/0, /*Op*/8, GIMT_Encode8(0),
        GIM_CheckComplexPattern, /*MI*/0, /*Op*/4, /*Renderer*/GIMT_Encode2(0), GIMT_Encode2(GICP_gi_buf_soffset),
        // (SItbuffer_load_d16:{ *:[f16] } v4i32:{ *:[v4i32] }:$rsrc, 0:{ *:[i32] }, i32:{ *:[i32] }:$voffset, (BUFSOffset:{ *:[i32] } i32:{ *:[i32] }:$soffset), (timm:{ *:[i32] }):$offset, (timm:{ *:[i32] }):$format, (timm:{ *:[i32] }):$auxiliary, 0:{ *:[i1] })  =>  (TBUFFER_LOAD_FORMAT_D16_X_gfx80_OFFEN:{ *:[f16] } VGPR_32:{ *:[i32] }:$voffset, SReg_128:{ *:[v4i32] }:$rsrc, SCSrc_b32:{ *:[i32] }:$soffset, (timm:{ *:[i32] }):$offset, (as_i8timm:{ *:[i8] } ?:{ *:[i32] }:$format), (extract_cpol:{ *:[i32] } ?:{ *:[i32] }:$auxiliary), (extract_swz:{ *:[i1] } ?:{ *:[i32] }:$auxiliary))
        GIR_BuildMI, /*InsnID*/0, /*Opcode*/GIMT_Encode2(AMDGPU::TBUFFER_LOAD_FORMAT_D16_X_gfx80_OFFEN),
        GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/0, // DstI[vdata]
        GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/3, // voffset
        GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/1, // rsrc
        GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/0, // soffset
        GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/5, // offset
        GIR_CustomOperandRenderer, /*InsnID*/0, /*OldInsnID*/0, /*OpIdx*/6, /*OperandRenderer*/GIMT_Encode2(GICR_renderTruncTImm), // format
        GIR_CustomOperandRenderer, /*InsnID*/0, /*OldInsnID*/0, /*OpIdx*/7, /*OperandRenderer*/GIMT_Encode2(GICR_renderExtractCPol), // auxiliary
        GIR_CustomOperandRenderer, /*InsnID*/0, /*OldInsnID*/0, /*OpIdx*/7, /*OperandRenderer*/GIMT_Encode2(GICR_renderExtractSWZ), // auxiliary
        GIR_MergeMemOperands, /*InsnID*/0, /*NumInsns*/1, /*MergeInsnID's*/0,
        GIR_ConstrainSelectedInstOperands, /*InsnID*/0,
        GIR_EraseFromParent, /*InsnID*/0,
        // GIR_Coverage, 5635,
        GIR_Done,
      // Label 7295: @532168
      GIM_Try, /*On fail goto*//*Label 7296*/ GIMT_Encode4(532259), // Rule ID 5655 //
        GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasPackedD16VMem_HasUnrestrictedSOffset),
        GIM_CheckConstantInt8, /*MI*/0, /*Op*/2, 0,
        // MIs[0] offset
        GIM_CheckIsImm, /*MI*/0, /*Op*/5,
        // MIs[0] format
        GIM_CheckIsImm, /*MI*/0, /*Op*/6,
        // MIs[0] auxiliary
        GIM_CheckIsImm, /*MI*/0, /*Op*/7,
        // MIs[0] Operand 8
        GIM_CheckLiteralInt, /*MI*/0, /*Op*/8, GIMT_Encode8(0),
        GIM_CheckComplexPattern, /*MI*/0, /*Op*/4, /*Renderer*/GIMT_Encode2(0), GIMT_Encode2(GICP_gi_buf_soffset),
        // (SItbuffer_load_d16:{ *:[f16] } v4i32:{ *:[v4i32] }:$rsrc, 0:{ *:[i32] }, i32:{ *:[i32] }:$voffset, (BUFSOffset:{ *:[i32] } i32:{ *:[i32] }:$soffset), (timm:{ *:[i32] }):$offset, (timm:{ *:[i32] }):$format, (timm:{ *:[i32] }):$auxiliary, 0:{ *:[i1] })  =>  (TBUFFER_LOAD_FORMAT_D16_X_OFFEN:{ *:[f16] } VGPR_32:{ *:[i32] }:$voffset, SReg_128:{ *:[v4i32] }:$rsrc, SCSrc_b32:{ *:[i32] }:$soffset, (timm:{ *:[i32] }):$offset, (as_i8timm:{ *:[i8] } ?:{ *:[i32] }:$format), (extract_cpol:{ *:[i32] } ?:{ *:[i32] }:$auxiliary), (extract_swz:{ *:[i1] } ?:{ *:[i32] }:$auxiliary))
        GIR_BuildMI, /*InsnID*/0, /*Opcode*/GIMT_Encode2(AMDGPU::TBUFFER_LOAD_FORMAT_D16_X_OFFEN),
        GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/0, // DstI[vdata]
        GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/3, // voffset
        GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/1, // rsrc
        GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/0, // soffset
        GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/5, // offset
        GIR_CustomOperandRenderer, /*InsnID*/0, /*OldInsnID*/0, /*OpIdx*/6, /*OperandRenderer*/GIMT_Encode2(GICR_renderTruncTImm), // format
        GIR_CustomOperandRenderer, /*InsnID*/0, /*OldInsnID*/0, /*OpIdx*/7, /*OperandRenderer*/GIMT_Encode2(GICR_renderExtractCPol), // auxiliary
        GIR_CustomOperandRenderer, /*InsnID*/0, /*OldInsnID*/0, /*OpIdx*/7, /*OperandRenderer*/GIMT_Encode2(GICR_renderExtractSWZ), // auxiliary
        GIR_MergeMemOperands, /*InsnID*/0, /*NumInsns*/1, /*MergeInsnID's*/0,
        GIR_ConstrainSelectedInstOperands, /*InsnID*/0,
        GIR_EraseFromParent, /*InsnID*/0,
        // GIR_Coverage, 5655,
        GIR_Done,
      // Label 7296: @532259
      GIM_Try, /*On fail goto*//*Label 7297*/ GIMT_Encode4(532350), // Rule ID 5659 //
        GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasPackedD16VMem),
        GIM_CheckConstantInt8, /*MI*/0, /*Op*/2, 0,
        // MIs[0] offset
        GIM_CheckIsImm, /*MI*/0, /*Op*/5,
        // MIs[0] format
        GIM_CheckIsImm, /*MI*/0, /*Op*/6,
        // MIs[0] auxiliary
        GIM_CheckIsImm, /*MI*/0, /*Op*/7,
        // MIs[0] Operand 8
        GIM_CheckLiteralInt, /*MI*/0, /*Op*/8, GIMT_Encode8(0),
        GIM_CheckComplexPattern, /*MI*/0, /*Op*/4, /*Renderer*/GIMT_Encode2(0), GIMT_Encode2(GICP_gi_buf_soffset),
        // (SItbuffer_load_d16:{ *:[f16] } v4i32:{ *:[v4i32] }:$rsrc, 0:{ *:[i32] }, i32:{ *:[i32] }:$voffset, (BUFSOffset:{ *:[i32] } i32:{ *:[i32] }:$soffset), (timm:{ *:[i32] }):$offset, (timm:{ *:[i32] }):$format, (timm:{ *:[i32] }):$auxiliary, 0:{ *:[i1] })  =>  (TBUFFER_LOAD_FORMAT_D16_X_VBUFFER_OFFEN:{ *:[f16] } VGPR_32:{ *:[i32] }:$voffset, SReg_128:{ *:[v4i32] }:$rsrc, SCSrc_b32:{ *:[i32] }:$soffset, (timm:{ *:[i32] }):$offset, (as_i8timm:{ *:[i8] } ?:{ *:[i32] }:$format), (extract_cpol:{ *:[i32] } ?:{ *:[i32] }:$auxiliary), (extract_swz:{ *:[i1] } ?:{ *:[i32] }:$auxiliary))
        GIR_BuildMI, /*InsnID*/0, /*Opcode*/GIMT_Encode2(AMDGPU::TBUFFER_LOAD_FORMAT_D16_X_VBUFFER_OFFEN),
        GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/0, // DstI[vdata]
        GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/3, // voffset
        GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/1, // rsrc
        GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/0, // soffset
        GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/5, // offset
        GIR_CustomOperandRenderer, /*InsnID*/0, /*OldInsnID*/0, /*OpIdx*/6, /*OperandRenderer*/GIMT_Encode2(GICR_renderTruncTImm), // format
        GIR_CustomOperandRenderer, /*InsnID*/0, /*OldInsnID*/0, /*OpIdx*/7, /*OperandRenderer*/GIMT_Encode2(GICR_renderExtractCPol), // auxiliary
        GIR_CustomOperandRenderer, /*InsnID*/0, /*OldInsnID*/0, /*OpIdx*/7, /*OperandRenderer*/GIMT_Encode2(GICR_renderExtractSWZ), // auxiliary
        GIR_MergeMemOperands, /*InsnID*/0, /*NumInsns*/1, /*MergeInsnID's*/0,
        GIR_ConstrainSelectedInstOperands, /*InsnID*/0,
        GIR_EraseFromParent, /*InsnID*/0,
        // GIR_Coverage, 5659,
        GIR_Done,
      // Label 7297: @532350
      GIM_Try, /*On fail goto*//*Label 7298*/ GIMT_Encode4(532433), // Rule ID 5634 //
        GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasUnpackedD16VMem),
        GIM_CheckConstantInt8, /*MI*/0, /*Op*/3, 0,
        // MIs[0] offset
        GIM_CheckIsImm, /*MI*/0, /*Op*/5,
        // MIs[0] format
        GIM_CheckIsImm, /*MI*/0, /*Op*/6,
        // MIs[0] auxiliary
        GIM_CheckIsImm, /*MI*/0, /*Op*/7,
        // MIs[0] Operand 8
        GIM_CheckIsImm, /*MI*/0, /*Op*/8,
        GIM_CheckComplexPattern, /*MI*/0, /*Op*/4, /*Renderer*/GIMT_Encode2(0), GIMT_Encode2(GICP_gi_buf_soffset),
        // (SItbuffer_load_d16:{ *:[f16] } v4i32:{ *:[v4i32] }:$rsrc, i32:{ *:[i32] }:$vindex, 0:{ *:[i32] }, (BUFSOffset:{ *:[i32] } i32:{ *:[i32] }:$soffset), (timm:{ *:[i32] }):$offset, (timm:{ *:[i32] }):$format, (timm:{ *:[i32] }):$auxiliary, (timm:{ *:[i1] }))  =>  (TBUFFER_LOAD_FORMAT_D16_X_gfx80_IDXEN:{ *:[f16] } VGPR_32:{ *:[i32] }:$vindex, SReg_128:{ *:[v4i32] }:$rsrc, SCSrc_b32:{ *:[i32] }:$soffset, (timm:{ *:[i32] }):$offset, (as_i8timm:{ *:[i8] } ?:{ *:[i32] }:$format), (extract_cpol:{ *:[i32] } ?:{ *:[i32] }:$auxiliary), (extract_swz:{ *:[i1] } ?:{ *:[i32] }:$auxiliary))
        GIR_BuildMI, /*InsnID*/0, /*Opcode*/GIMT_Encode2(AMDGPU::TBUFFER_LOAD_FORMAT_D16_X_gfx80_IDXEN),
        GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/0, // DstI[vdata]
        GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/2, // vindex
        GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/1, // rsrc
        GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/0, // soffset
        GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/5, // offset
        GIR_CustomOperandRenderer, /*InsnID*/0, /*OldInsnID*/0, /*OpIdx*/6, /*OperandRenderer*/GIMT_Encode2(GICR_renderTruncTImm), // format
        GIR_CustomOperandRenderer, /*InsnID*/0, /*OldInsnID*/0, /*OpIdx*/7, /*OperandRenderer*/GIMT_Encode2(GICR_renderExtractCPol), // auxiliary
        GIR_CustomOperandRenderer, /*InsnID*/0, /*OldInsnID*/0, /*OpIdx*/7, /*OperandRenderer*/GIMT_Encode2(GICR_renderExtractSWZ), // auxiliary
        GIR_MergeMemOperands, /*InsnID*/0, /*NumInsns*/1, /*MergeInsnID's*/0,
        GIR_ConstrainSelectedInstOperands, /*InsnID*/0,
        GIR_EraseFromParent, /*InsnID*/0,
        // GIR_Coverage, 5634,
        GIR_Done,
      // Label 7298: @532433
      GIM_Try, /*On fail goto*//*Label 7299*/ GIMT_Encode4(532516), // Rule ID 5654 //
        GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasPackedD16VMem_HasUnrestrictedSOffset),
        GIM_CheckConstantInt8, /*MI*/0, /*Op*/3, 0,
        // MIs[0] offset
        GIM_CheckIsImm, /*MI*/0, /*Op*/5,
        // MIs[0] format
        GIM_CheckIsImm, /*MI*/0, /*Op*/6,
        // MIs[0] auxiliary
        GIM_CheckIsImm, /*MI*/0, /*Op*/7,
        // MIs[0] Operand 8
        GIM_CheckIsImm, /*MI*/0, /*Op*/8,
        GIM_CheckComplexPattern, /*MI*/0, /*Op*/4, /*Renderer*/GIMT_Encode2(0), GIMT_Encode2(GICP_gi_buf_soffset),
        // (SItbuffer_load_d16:{ *:[f16] } v4i32:{ *:[v4i32] }:$rsrc, i32:{ *:[i32] }:$vindex, 0:{ *:[i32] }, (BUFSOffset:{ *:[i32] } i32:{ *:[i32] }:$soffset), (timm:{ *:[i32] }):$offset, (timm:{ *:[i32] }):$format, (timm:{ *:[i32] }):$auxiliary, (timm:{ *:[i1] }))  =>  (TBUFFER_LOAD_FORMAT_D16_X_IDXEN:{ *:[f16] } VGPR_32:{ *:[i32] }:$vindex, SReg_128:{ *:[v4i32] }:$rsrc, SCSrc_b32:{ *:[i32] }:$soffset, (timm:{ *:[i32] }):$offset, (as_i8timm:{ *:[i8] } ?:{ *:[i32] }:$format), (extract_cpol:{ *:[i32] } ?:{ *:[i32] }:$auxiliary), (extract_swz:{ *:[i1] } ?:{ *:[i32] }:$auxiliary))
        GIR_BuildMI, /*InsnID*/0, /*Opcode*/GIMT_Encode2(AMDGPU::TBUFFER_LOAD_FORMAT_D16_X_IDXEN),
        GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/0, // DstI[vdata]
        GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/2, // vindex
        GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/1, // rsrc
        GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/0, // soffset
        GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/5, // offset
        GIR_CustomOperandRenderer, /*InsnID*/0, /*OldInsnID*/0, /*OpIdx*/6, /*OperandRenderer*/GIMT_Encode2(GICR_renderTruncTImm), // format
        GIR_CustomOperandRenderer, /*InsnID*/0, /*OldInsnID*/0, /*OpIdx*/7, /*OperandRenderer*/GIMT_Encode2(GICR_renderExtractCPol), // auxiliary
        GIR_CustomOperandRenderer, /*InsnID*/0, /*OldInsnID*/0, /*OpIdx*/7, /*OperandRenderer*/GIMT_Encode2(GICR_renderExtractSWZ), // auxiliary
        GIR_MergeMemOperands, /*InsnID*/0, /*NumInsns*/1, /*MergeInsnID's*/0,
        GIR_ConstrainSelectedInstOperands, /*InsnID*/0,
        GIR_EraseFromParent, /*InsnID*/0,
        // GIR_Coverage, 5654,
        GIR_Done,
      // Label 7299: @532516
      GIM_Try, /*On fail goto*//*Label 7300*/ GIMT_Encode4(532599), // Rule ID 5658 //
        GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasPackedD16VMem),
        GIM_CheckConstantInt8, /*MI*/0, /*Op*/3, 0,
        // MIs[0] offset
        GIM_CheckIsImm, /*MI*/0, /*Op*/5,
        // MIs[0] format
        GIM_CheckIsImm, /*MI*/0, /*Op*/6,
        // MIs[0] auxiliary
        GIM_CheckIsImm, /*MI*/0, /*Op*/7,
        // MIs[0] Operand 8
        GIM_CheckIsImm, /*MI*/0, /*Op*/8,
        GIM_CheckComplexPattern, /*MI*/0, /*Op*/4, /*Renderer*/GIMT_Encode2(0), GIMT_Encode2(GICP_gi_buf_soffset),
        // (SItbuffer_load_d16:{ *:[f16] } v4i32:{ *:[v4i32] }:$rsrc, i32:{ *:[i32] }:$vindex, 0:{ *:[i32] }, (BUFSOffset:{ *:[i32] } i32:{ *:[i32] }:$soffset), (timm:{ *:[i32] }):$offset, (timm:{ *:[i32] }):$format, (timm:{ *:[i32] }):$auxiliary, (timm:{ *:[i1] }))  =>  (TBUFFER_LOAD_FORMAT_D16_X_VBUFFER_IDXEN:{ *:[f16] } VGPR_32:{ *:[i32] }:$vindex, SReg_128:{ *:[v4i32] }:$rsrc, SCSrc_b32:{ *:[i32] }:$soffset, (timm:{ *:[i32] }):$offset, (as_i8timm:{ *:[i8] } ?:{ *:[i32] }:$format), (extract_cpol:{ *:[i32] } ?:{ *:[i32] }:$auxiliary), (extract_swz:{ *:[i1] } ?:{ *:[i32] }:$auxiliary))
        GIR_BuildMI, /*InsnID*/0, /*Opcode*/GIMT_Encode2(AMDGPU::TBUFFER_LOAD_FORMAT_D16_X_VBUFFER_IDXEN),
        GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/0, // DstI[vdata]
        GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/2, // vindex
        GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/1, // rsrc
        GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/0, // soffset
        GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/5, // offset
        GIR_CustomOperandRenderer, /*InsnID*/0, /*OldInsnID*/0, /*OpIdx*/6, /*OperandRenderer*/GIMT_Encode2(GICR_renderTruncTImm), // format
        GIR_CustomOperandRenderer, /*InsnID*/0, /*OldInsnID*/0, /*OpIdx*/7, /*OperandRenderer*/GIMT_Encode2(GICR_renderExtractCPol), // auxiliary
        GIR_CustomOperandRenderer, /*InsnID*/0, /*OldInsnID*/0, /*OpIdx*/7, /*OperandRenderer*/GIMT_Encode2(GICR_renderExtractSWZ), // auxiliary
        GIR_MergeMemOperands, /*InsnID*/0, /*NumInsns*/1, /*MergeInsnID's*/0,
        GIR_ConstrainSelectedInstOperands, /*InsnID*/0,
        GIR_EraseFromParent, /*InsnID*/0,
        // GIR_Coverage, 5658,
        GIR_Done,
      // Label 7300: @532599
      GIM_Try, /*On fail goto*//*Label 7301*/ GIMT_Encode4(532718), // Rule ID 5636 //
        GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasUnpackedD16VMem),
        // MIs[0] offset
        GIM_CheckIsImm, /*MI*/0, /*Op*/5,
        // MIs[0] format
        GIM_CheckIsImm, /*MI*/0, /*Op*/6,
        // MIs[0] auxiliary
        GIM_CheckIsImm, /*MI*/0, /*Op*/7,
        // MIs[0] Operand 8
        GIM_CheckIsImm, /*MI*/0, /*Op*/8,
        GIM_CheckComplexPattern, /*MI*/0, /*Op*/4, /*Renderer*/GIMT_Encode2(0), GIMT_Encode2(GICP_gi_buf_soffset),
        // (SItbuffer_load_d16:{ *:[f16] } v4i32:{ *:[v4i32] }:$rsrc, i32:{ *:[i32] }:$vindex, i32:{ *:[i32] }:$voffset, (BUFSOffset:{ *:[i32] } i32:{ *:[i32] }:$soffset), (timm:{ *:[i32] }):$offset, (timm:{ *:[i32] }):$format, (timm:{ *:[i32] }):$auxiliary, (timm:{ *:[i1] }))  =>  (TBUFFER_LOAD_FORMAT_D16_X_gfx80_BOTHEN:{ *:[f16] } (REG_SEQUENCE:{ *:[i64] } VReg_64:{ *:[i32] }, VGPR_32:{ *:[i32] }:$vindex, sub0:{ *:[i32] }, VGPR_32:{ *:[i32] }:$voffset, sub1:{ *:[i32] }), SReg_128:{ *:[v4i32] }:$rsrc, SCSrc_b32:{ *:[i32] }:$soffset, (timm:{ *:[i32] }):$offset, (as_i8timm:{ *:[i8] } ?:{ *:[i32] }:$format), (extract_cpol:{ *:[i32] } ?:{ *:[i32] }:$auxiliary), (extract_swz:{ *:[i1] } ?:{ *:[i32] }:$auxiliary))
        GIR_MakeTempReg, /*TempRegID*/0, /*TypeID*/GILLT_s64,
        GIR_BuildMI, /*InsnID*/1, /*Opcode*/GIMT_Encode2(TargetOpcode::REG_SEQUENCE),
        GIR_AddTempRegister, /*InsnID*/1, /*TempRegID*/0, /*TempRegFlags*/GIMT_Encode2(RegState::Define),
        GIR_Copy, /*NewInsnID*/1, /*OldInsnID*/0, /*OpIdx*/2, // vindex
        GIR_AddImm8, /*InsnID*/1, /*SubRegIndex*/3,
        GIR_Copy, /*NewInsnID*/1, /*OldInsnID*/0, /*OpIdx*/3, // voffset
        GIR_AddImm8, /*InsnID*/1, /*SubRegIndex*/11,
        GIR_ConstrainOperandRC, /*InsnID*/1, /*Op*/0, GIMT_Encode2(AMDGPU::VReg_64RegClassID),
        GIR_ConstrainOperandRC, /*InsnID*/1, /*Op*/1, GIMT_Encode2(AMDGPU::VGPR_32RegClassID),
        GIR_ConstrainOperandRC, /*InsnID*/1, /*Op*/3, GIMT_Encode2(AMDGPU::VGPR_32RegClassID),
        GIR_BuildMI, /*InsnID*/0, /*Opcode*/GIMT_Encode2(AMDGPU::TBUFFER_LOAD_FORMAT_D16_X_gfx80_BOTHEN),
        GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/0, // DstI[vdata]
        GIR_AddSimpleTempRegister, /*InsnID*/0, /*TempRegID*/0,
        GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/1, // rsrc
        GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/0, // soffset
        GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/5, // offset
        GIR_CustomOperandRenderer, /*InsnID*/0, /*OldInsnID*/0, /*OpIdx*/6, /*OperandRenderer*/GIMT_Encode2(GICR_renderTruncTImm), // format
        GIR_CustomOperandRenderer, /*InsnID*/0, /*OldInsnID*/0, /*OpIdx*/7, /*OperandRenderer*/GIMT_Encode2(GICR_renderExtractCPol), // auxiliary
        GIR_CustomOperandRenderer, /*InsnID*/0, /*OldInsnID*/0, /*OpIdx*/7, /*OperandRenderer*/GIMT_Encode2(GICR_renderExtractSWZ), // auxiliary
        GIR_MergeMemOperands, /*InsnID*/0, /*NumInsns*/1, /*MergeInsnID's*/0,
        GIR_ConstrainSelectedInstOperands, /*InsnID*/0,
        GIR_EraseFromParent, /*InsnID*/0,
        // GIR_Coverage, 5636,
        GIR_Done,
      // Label 7301: @532718
      GIM_Try, /*On fail goto*//*Label 7302*/ GIMT_Encode4(532837), // Rule ID 5656 //
        GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasPackedD16VMem_HasUnrestrictedSOffset),
        // MIs[0] offset
        GIM_CheckIsImm, /*MI*/0, /*Op*/5,
        // MIs[0] format
        GIM_CheckIsImm, /*MI*/0, /*Op*/6,
        // MIs[0] auxiliary
        GIM_CheckIsImm, /*MI*/0, /*Op*/7,
        // MIs[0] Operand 8
        GIM_CheckIsImm, /*MI*/0, /*Op*/8,
        GIM_CheckComplexPattern, /*MI*/0, /*Op*/4, /*Renderer*/GIMT_Encode2(0), GIMT_Encode2(GICP_gi_buf_soffset),
        // (SItbuffer_load_d16:{ *:[f16] } v4i32:{ *:[v4i32] }:$rsrc, i32:{ *:[i32] }:$vindex, i32:{ *:[i32] }:$voffset, (BUFSOffset:{ *:[i32] } i32:{ *:[i32] }:$soffset), (timm:{ *:[i32] }):$offset, (timm:{ *:[i32] }):$format, (timm:{ *:[i32] }):$auxiliary, (timm:{ *:[i1] }))  =>  (TBUFFER_LOAD_FORMAT_D16_X_BOTHEN:{ *:[f16] } (REG_SEQUENCE:{ *:[i64] } VReg_64:{ *:[i32] }, VGPR_32:{ *:[i32] }:$vindex, sub0:{ *:[i32] }, VGPR_32:{ *:[i32] }:$voffset, sub1:{ *:[i32] }), SReg_128:{ *:[v4i32] }:$rsrc, SCSrc_b32:{ *:[i32] }:$soffset, (timm:{ *:[i32] }):$offset, (as_i8timm:{ *:[i8] } ?:{ *:[i32] }:$format), (extract_cpol:{ *:[i32] } ?:{ *:[i32] }:$auxiliary), (extract_swz:{ *:[i1] } ?:{ *:[i32] }:$auxiliary))
        GIR_MakeTempReg, /*TempRegID*/0, /*TypeID*/GILLT_s64,
        GIR_BuildMI, /*InsnID*/1, /*Opcode*/GIMT_Encode2(TargetOpcode::REG_SEQUENCE),
        GIR_AddTempRegister, /*InsnID*/1, /*TempRegID*/0, /*TempRegFlags*/GIMT_Encode2(RegState::Define),
        GIR_Copy, /*NewInsnID*/1, /*OldInsnID*/0, /*OpIdx*/2, // vindex
        GIR_AddImm8, /*InsnID*/1, /*SubRegIndex*/3,
        GIR_Copy, /*NewInsnID*/1, /*OldInsnID*/0, /*OpIdx*/3, // voffset
        GIR_AddImm8, /*InsnID*/1, /*SubRegIndex*/11,
        GIR_ConstrainOperandRC, /*InsnID*/1, /*Op*/0, GIMT_Encode2(AMDGPU::VReg_64RegClassID),
        GIR_ConstrainOperandRC, /*InsnID*/1, /*Op*/1, GIMT_Encode2(AMDGPU::VGPR_32RegClassID),
        GIR_ConstrainOperandRC, /*InsnID*/1, /*Op*/3, GIMT_Encode2(AMDGPU::VGPR_32RegClassID),
        GIR_BuildMI, /*InsnID*/0, /*Opcode*/GIMT_Encode2(AMDGPU::TBUFFER_LOAD_FORMAT_D16_X_BOTHEN),
        GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/0, // DstI[vdata]
        GIR_AddSimpleTempRegister, /*InsnID*/0, /*TempRegID*/0,
        GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/1, // rsrc
        GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/0, // soffset
        GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/5, // offset
        GIR_CustomOperandRenderer, /*InsnID*/0, /*OldInsnID*/0, /*OpIdx*/6, /*OperandRenderer*/GIMT_Encode2(GICR_renderTruncTImm), // format
        GIR_CustomOperandRenderer, /*InsnID*/0, /*OldInsnID*/0, /*OpIdx*/7, /*OperandRenderer*/GIMT_Encode2(GICR_renderExtractCPol), // auxiliary
        GIR_CustomOperandRenderer, /*InsnID*/0, /*OldInsnID*/0, /*OpIdx*/7, /*OperandRenderer*/GIMT_Encode2(GICR_renderExtractSWZ), // auxiliary
        GIR_MergeMemOperands, /*InsnID*/0, /*NumInsns*/1, /*MergeInsnID's*/0,
        GIR_ConstrainSelectedInstOperands, /*InsnID*/0,
        GIR_EraseFromParent, /*InsnID*/0,
        // GIR_Coverage, 5656,
        GIR_Done,
      // Label 7302: @532837
      GIM_Try, /*On fail goto*//*Label 7303*/ GIMT_Encode4(532956), // Rule ID 5660 //
        GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasPackedD16VMem),
        // MIs[0] offset
        GIM_CheckIsImm, /*MI*/0, /*Op*/5,
        // MIs[0] format
        GIM_CheckIsImm, /*MI*/0, /*Op*/6,
        // MIs[0] auxiliary
        GIM_CheckIsImm, /*MI*/0, /*Op*/7,
        // MIs[0] Operand 8
        GIM_CheckIsImm, /*MI*/0, /*Op*/8,
        GIM_CheckComplexPattern, /*MI*/0, /*Op*/4, /*Renderer*/GIMT_Encode2(0), GIMT_Encode2(GICP_gi_buf_soffset),
        // (SItbuffer_load_d16:{ *:[f16] } v4i32:{ *:[v4i32] }:$rsrc, i32:{ *:[i32] }:$vindex, i32:{ *:[i32] }:$voffset, (BUFSOffset:{ *:[i32] } i32:{ *:[i32] }:$soffset), (timm:{ *:[i32] }):$offset, (timm:{ *:[i32] }):$format, (timm:{ *:[i32] }):$auxiliary, (timm:{ *:[i1] }))  =>  (TBUFFER_LOAD_FORMAT_D16_X_VBUFFER_BOTHEN:{ *:[f16] } (REG_SEQUENCE:{ *:[i64] } VReg_64:{ *:[i32] }, VGPR_32:{ *:[i32] }:$vindex, sub0:{ *:[i32] }, VGPR_32:{ *:[i32] }:$voffset, sub1:{ *:[i32] }), SReg_128:{ *:[v4i32] }:$rsrc, SCSrc_b32:{ *:[i32] }:$soffset, (timm:{ *:[i32] }):$offset, (as_i8timm:{ *:[i8] } ?:{ *:[i32] }:$format), (extract_cpol:{ *:[i32] } ?:{ *:[i32] }:$auxiliary), (extract_swz:{ *:[i1] } ?:{ *:[i32] }:$auxiliary))
        GIR_MakeTempReg, /*TempRegID*/0, /*TypeID*/GILLT_s64,
        GIR_BuildMI, /*InsnID*/1, /*Opcode*/GIMT_Encode2(TargetOpcode::REG_SEQUENCE),
        GIR_AddTempRegister, /*InsnID*/1, /*TempRegID*/0, /*TempRegFlags*/GIMT_Encode2(RegState::Define),
        GIR_Copy, /*NewInsnID*/1, /*OldInsnID*/0, /*OpIdx*/2, // vindex
        GIR_AddImm8, /*InsnID*/1, /*SubRegIndex*/3,
        GIR_Copy, /*NewInsnID*/1, /*OldInsnID*/0, /*OpIdx*/3, // voffset
        GIR_AddImm8, /*InsnID*/1, /*SubRegIndex*/11,
        GIR_ConstrainOperandRC, /*InsnID*/1, /*Op*/0, GIMT_Encode2(AMDGPU::VReg_64RegClassID),
        GIR_ConstrainOperandRC, /*InsnID*/1, /*Op*/1, GIMT_Encode2(AMDGPU::VGPR_32RegClassID),
        GIR_ConstrainOperandRC, /*InsnID*/1, /*Op*/3, GIMT_Encode2(AMDGPU::VGPR_32RegClassID),
        GIR_BuildMI, /*InsnID*/0, /*Opcode*/GIMT_Encode2(AMDGPU::TBUFFER_LOAD_FORMAT_D16_X_VBUFFER_BOTHEN),
        GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/0, // DstI[vdata]
        GIR_AddSimpleTempRegister, /*InsnID*/0, /*TempRegID*/0,
        GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/1, // rsrc
        GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/0, // soffset
        GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/5, // offset
        GIR_CustomOperandRenderer, /*InsnID*/0, /*OldInsnID*/0, /*OpIdx*/6, /*OperandRenderer*/GIMT_Encode2(GICR_renderTruncTImm), // format
        GIR_CustomOperandRenderer, /*InsnID*/0, /*OldInsnID*/0, /*OpIdx*/7, /*OperandRenderer*/GIMT_Encode2(GICR_renderExtractCPol), // auxiliary
        GIR_CustomOperandRenderer, /*InsnID*/0, /*OldInsnID*/0, /*OpIdx*/7, /*OperandRenderer*/GIMT_Encode2(GICR_renderExtractSWZ), // auxiliary
        GIR_MergeMemOperands, /*InsnID*/0, /*NumInsns*/1, /*MergeInsnID's*/0,
        GIR_ConstrainSelectedInstOperands, /*InsnID*/0,
        GIR_EraseFromParent, /*InsnID*/0,
        // GIR_Coverage, 5660,
        GIR_Done,
      // Label 7303: @532956
      GIM_Reject,
    // Label 7291: @532957
    GIM_Reject,
    // Label 7284: @532958
    GIM_Try, /*On fail goto*//*Label 7304*/ GIMT_Encode4(534137),
      GIM_CheckType, /*MI*/0, /*Op*/1, /*Type*/GILLT_v4s32,
      GIM_CheckType, /*MI*/0, /*Op*/2, /*Type*/GILLT_s32,
      GIM_CheckType, /*MI*/0, /*Op*/3, /*Type*/GILLT_s32,
      GIM_CheckType, /*MI*/0, /*Op*/4, /*Type*/GILLT_s32,
      GIM_CheckRegBankForClass, /*MI*/0, /*Op*/0, /*RC*/GIMT_Encode2(AMDGPU::AV_32RegClassID),
      GIM_Try, /*On fail goto*//*Label 7305*/ GIMT_Encode4(533075), // Rule ID 5637 //
        GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasUnpackedD16VMem),
        GIM_CheckConstantInt8, /*MI*/0, /*Op*/2, 0,
        GIM_CheckConstantInt8, /*MI*/0, /*Op*/3, 0,
        // MIs[0] offset
        GIM_CheckIsImm, /*MI*/0, /*Op*/5,
        // MIs[0] format
        GIM_CheckIsImm, /*MI*/0, /*Op*/6,
        // MIs[0] auxiliary
        GIM_CheckIsImm, /*MI*/0, /*Op*/7,
        // MIs[0] Operand 8
        GIM_CheckLiteralInt, /*MI*/0, /*Op*/8, GIMT_Encode8(0),
        GIM_CheckComplexPattern, /*MI*/0, /*Op*/4, /*Renderer*/GIMT_Encode2(0), GIMT_Encode2(GICP_gi_buf_soffset),
        // (SItbuffer_load_d16:{ *:[i32] } v4i32:{ *:[v4i32] }:$rsrc, 0:{ *:[i32] }, 0:{ *:[i32] }, (BUFSOffset:{ *:[i32] } i32:{ *:[i32] }:$soffset), (timm:{ *:[i32] }):$offset, (timm:{ *:[i32] }):$format, (timm:{ *:[i32] }):$auxiliary, 0:{ *:[i1] })  =>  (TBUFFER_LOAD_FORMAT_D16_X_gfx80_OFFSET:{ *:[i32] } SReg_128:{ *:[v4i32] }:$rsrc, SCSrc_b32:{ *:[i32] }:$soffset, (timm:{ *:[i32] }):$offset, (as_i8timm:{ *:[i8] } ?:{ *:[i32] }:$format), (extract_cpol:{ *:[i32] } ?:{ *:[i32] }:$auxiliary), (extract_swz:{ *:[i1] } ?:{ *:[i32] }:$auxiliary))
        GIR_BuildMI, /*InsnID*/0, /*Opcode*/GIMT_Encode2(AMDGPU::TBUFFER_LOAD_FORMAT_D16_X_gfx80_OFFSET),
        GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/0, // DstI[vdata]
        GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/1, // rsrc
        GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/0, // soffset
        GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/5, // offset
        GIR_CustomOperandRenderer, /*InsnID*/0, /*OldInsnID*/0, /*OpIdx*/6, /*OperandRenderer*/GIMT_Encode2(GICR_renderTruncTImm), // format
        GIR_CustomOperandRenderer, /*InsnID*/0, /*OldInsnID*/0, /*OpIdx*/7, /*OperandRenderer*/GIMT_Encode2(GICR_renderExtractCPol), // auxiliary
        GIR_CustomOperandRenderer, /*InsnID*/0, /*OldInsnID*/0, /*OpIdx*/7, /*OperandRenderer*/GIMT_Encode2(GICR_renderExtractSWZ), // auxiliary
        GIR_MergeMemOperands, /*InsnID*/0, /*NumInsns*/1, /*MergeInsnID's*/0,
        GIR_ConstrainSelectedInstOperands, /*InsnID*/0,
        GIR_EraseFromParent, /*InsnID*/0,
        // GIR_Coverage, 5637,
        GIR_Done,
      // Label 7305: @533075
      GIM_Try, /*On fail goto*//*Label 7306*/ GIMT_Encode4(533166), // Rule ID 5661 //
        GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasPackedD16VMem_HasUnrestrictedSOffset),
        GIM_CheckConstantInt8, /*MI*/0, /*Op*/2, 0,
        GIM_CheckConstantInt8, /*MI*/0, /*Op*/3, 0,
        // MIs[0] offset
        GIM_CheckIsImm, /*MI*/0, /*Op*/5,
        // MIs[0] format
        GIM_CheckIsImm, /*MI*/0, /*Op*/6,
        // MIs[0] auxiliary
        GIM_CheckIsImm, /*MI*/0, /*Op*/7,
        // MIs[0] Operand 8
        GIM_CheckLiteralInt, /*MI*/0, /*Op*/8, GIMT_Encode8(0),
        GIM_CheckComplexPattern, /*MI*/0, /*Op*/4, /*Renderer*/GIMT_Encode2(0), GIMT_Encode2(GICP_gi_buf_soffset),
        // (SItbuffer_load_d16:{ *:[i32] } v4i32:{ *:[v4i32] }:$rsrc, 0:{ *:[i32] }, 0:{ *:[i32] }, (BUFSOffset:{ *:[i32] } i32:{ *:[i32] }:$soffset), (timm:{ *:[i32] }):$offset, (timm:{ *:[i32] }):$format, (timm:{ *:[i32] }):$auxiliary, 0:{ *:[i1] })  =>  (TBUFFER_LOAD_FORMAT_D16_X_OFFSET:{ *:[i32] } SReg_128:{ *:[v4i32] }:$rsrc, SCSrc_b32:{ *:[i32] }:$soffset, (timm:{ *:[i32] }):$offset, (as_i8timm:{ *:[i8] } ?:{ *:[i32] }:$format), (extract_cpol:{ *:[i32] } ?:{ *:[i32] }:$auxiliary), (extract_swz:{ *:[i1] } ?:{ *:[i32] }:$auxiliary))
        GIR_BuildMI, /*InsnID*/0, /*Opcode*/GIMT_Encode2(AMDGPU::TBUFFER_LOAD_FORMAT_D16_X_OFFSET),
        GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/0, // DstI[vdata]
        GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/1, // rsrc
        GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/0, // soffset
        GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/5, // offset
        GIR_CustomOperandRenderer, /*InsnID*/0, /*OldInsnID*/0, /*OpIdx*/6, /*OperandRenderer*/GIMT_Encode2(GICR_renderTruncTImm), // format
        GIR_CustomOperandRenderer, /*InsnID*/0, /*OldInsnID*/0, /*OpIdx*/7, /*OperandRenderer*/GIMT_Encode2(GICR_renderExtractCPol), // auxiliary
        GIR_CustomOperandRenderer, /*InsnID*/0, /*OldInsnID*/0, /*OpIdx*/7, /*OperandRenderer*/GIMT_Encode2(GICR_renderExtractSWZ), // auxiliary
        GIR_MergeMemOperands, /*InsnID*/0, /*NumInsns*/1, /*MergeInsnID's*/0,
        GIR_ConstrainSelectedInstOperands, /*InsnID*/0,
        GIR_EraseFromParent, /*InsnID*/0,
        // GIR_Coverage, 5661,
        GIR_Done,
      // Label 7306: @533166
      GIM_Try, /*On fail goto*//*Label 7307*/ GIMT_Encode4(533257), // Rule ID 5665 //
        GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasPackedD16VMem),
        GIM_CheckConstantInt8, /*MI*/0, /*Op*/2, 0,
        GIM_CheckConstantInt8, /*MI*/0, /*Op*/3, 0,
        // MIs[0] offset
        GIM_CheckIsImm, /*MI*/0, /*Op*/5,
        // MIs[0] format
        GIM_CheckIsImm, /*MI*/0, /*Op*/6,
        // MIs[0] auxiliary
        GIM_CheckIsImm, /*MI*/0, /*Op*/7,
        // MIs[0] Operand 8
        GIM_CheckLiteralInt, /*MI*/0, /*Op*/8, GIMT_Encode8(0),
        GIM_CheckComplexPattern, /*MI*/0, /*Op*/4, /*Renderer*/GIMT_Encode2(0), GIMT_Encode2(GICP_gi_buf_soffset),
        // (SItbuffer_load_d16:{ *:[i32] } v4i32:{ *:[v4i32] }:$rsrc, 0:{ *:[i32] }, 0:{ *:[i32] }, (BUFSOffset:{ *:[i32] } i32:{ *:[i32] }:$soffset), (timm:{ *:[i32] }):$offset, (timm:{ *:[i32] }):$format, (timm:{ *:[i32] }):$auxiliary, 0:{ *:[i1] })  =>  (TBUFFER_LOAD_FORMAT_D16_X_VBUFFER_OFFSET:{ *:[i32] } SReg_128:{ *:[v4i32] }:$rsrc, SCSrc_b32:{ *:[i32] }:$soffset, (timm:{ *:[i32] }):$offset, (as_i8timm:{ *:[i8] } ?:{ *:[i32] }:$format), (extract_cpol:{ *:[i32] } ?:{ *:[i32] }:$auxiliary), (extract_swz:{ *:[i1] } ?:{ *:[i32] }:$auxiliary))
        GIR_BuildMI, /*InsnID*/0, /*Opcode*/GIMT_Encode2(AMDGPU::TBUFFER_LOAD_FORMAT_D16_X_VBUFFER_OFFSET),
        GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/0, // DstI[vdata]
        GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/1, // rsrc
        GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/0, // soffset
        GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/5, // offset
        GIR_CustomOperandRenderer, /*InsnID*/0, /*OldInsnID*/0, /*OpIdx*/6, /*OperandRenderer*/GIMT_Encode2(GICR_renderTruncTImm), // format
        GIR_CustomOperandRenderer, /*InsnID*/0, /*OldInsnID*/0, /*OpIdx*/7, /*OperandRenderer*/GIMT_Encode2(GICR_renderExtractCPol), // auxiliary
        GIR_CustomOperandRenderer, /*InsnID*/0, /*OldInsnID*/0, /*OpIdx*/7, /*OperandRenderer*/GIMT_Encode2(GICR_renderExtractSWZ), // auxiliary
        GIR_MergeMemOperands, /*InsnID*/0, /*NumInsns*/1, /*MergeInsnID's*/0,
        GIR_ConstrainSelectedInstOperands, /*InsnID*/0,
        GIR_EraseFromParent, /*InsnID*/0,
        // GIR_Coverage, 5665,
        GIR_Done,
      // Label 7307: @533257
      GIM_Try, /*On fail goto*//*Label 7308*/ GIMT_Encode4(533348), // Rule ID 5639 //
        GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasUnpackedD16VMem),
        GIM_CheckConstantInt8, /*MI*/0, /*Op*/2, 0,
        // MIs[0] offset
        GIM_CheckIsImm, /*MI*/0, /*Op*/5,
        // MIs[0] format
        GIM_CheckIsImm, /*MI*/0, /*Op*/6,
        // MIs[0] auxiliary
        GIM_CheckIsImm, /*MI*/0, /*Op*/7,
        // MIs[0] Operand 8
        GIM_CheckLiteralInt, /*MI*/0, /*Op*/8, GIMT_Encode8(0),
        GIM_CheckComplexPattern, /*MI*/0, /*Op*/4, /*Renderer*/GIMT_Encode2(0), GIMT_Encode2(GICP_gi_buf_soffset),
        // (SItbuffer_load_d16:{ *:[i32] } v4i32:{ *:[v4i32] }:$rsrc, 0:{ *:[i32] }, i32:{ *:[i32] }:$voffset, (BUFSOffset:{ *:[i32] } i32:{ *:[i32] }:$soffset), (timm:{ *:[i32] }):$offset, (timm:{ *:[i32] }):$format, (timm:{ *:[i32] }):$auxiliary, 0:{ *:[i1] })  =>  (TBUFFER_LOAD_FORMAT_D16_X_gfx80_OFFEN:{ *:[i32] } VGPR_32:{ *:[i32] }:$voffset, SReg_128:{ *:[v4i32] }:$rsrc, SCSrc_b32:{ *:[i32] }:$soffset, (timm:{ *:[i32] }):$offset, (as_i8timm:{ *:[i8] } ?:{ *:[i32] }:$format), (extract_cpol:{ *:[i32] } ?:{ *:[i32] }:$auxiliary), (extract_swz:{ *:[i1] } ?:{ *:[i32] }:$auxiliary))
        GIR_BuildMI, /*InsnID*/0, /*Opcode*/GIMT_Encode2(AMDGPU::TBUFFER_LOAD_FORMAT_D16_X_gfx80_OFFEN),
        GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/0, // DstI[vdata]
        GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/3, // voffset
        GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/1, // rsrc
        GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/0, // soffset
        GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/5, // offset
        GIR_CustomOperandRenderer, /*InsnID*/0, /*OldInsnID*/0, /*OpIdx*/6, /*OperandRenderer*/GIMT_Encode2(GICR_renderTruncTImm), // format
        GIR_CustomOperandRenderer, /*InsnID*/0, /*OldInsnID*/0, /*OpIdx*/7, /*OperandRenderer*/GIMT_Encode2(GICR_renderExtractCPol), // auxiliary
        GIR_CustomOperandRenderer, /*InsnID*/0, /*OldInsnID*/0, /*OpIdx*/7, /*OperandRenderer*/GIMT_Encode2(GICR_renderExtractSWZ), // auxiliary
        GIR_MergeMemOperands, /*InsnID*/0, /*NumInsns*/1, /*MergeInsnID's*/0,
        GIR_ConstrainSelectedInstOperands, /*InsnID*/0,
        GIR_EraseFromParent, /*InsnID*/0,
        // GIR_Coverage, 5639,
        GIR_Done,
      // Label 7308: @533348
      GIM_Try, /*On fail goto*//*Label 7309*/ GIMT_Encode4(533439), // Rule ID 5663 //
        GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasPackedD16VMem_HasUnrestrictedSOffset),
        GIM_CheckConstantInt8, /*MI*/0, /*Op*/2, 0,
        // MIs[0] offset
        GIM_CheckIsImm, /*MI*/0, /*Op*/5,
        // MIs[0] format
        GIM_CheckIsImm, /*MI*/0, /*Op*/6,
        // MIs[0] auxiliary
        GIM_CheckIsImm, /*MI*/0, /*Op*/7,
        // MIs[0] Operand 8
        GIM_CheckLiteralInt, /*MI*/0, /*Op*/8, GIMT_Encode8(0),
        GIM_CheckComplexPattern, /*MI*/0, /*Op*/4, /*Renderer*/GIMT_Encode2(0), GIMT_Encode2(GICP_gi_buf_soffset),
        // (SItbuffer_load_d16:{ *:[i32] } v4i32:{ *:[v4i32] }:$rsrc, 0:{ *:[i32] }, i32:{ *:[i32] }:$voffset, (BUFSOffset:{ *:[i32] } i32:{ *:[i32] }:$soffset), (timm:{ *:[i32] }):$offset, (timm:{ *:[i32] }):$format, (timm:{ *:[i32] }):$auxiliary, 0:{ *:[i1] })  =>  (TBUFFER_LOAD_FORMAT_D16_X_OFFEN:{ *:[i32] } VGPR_32:{ *:[i32] }:$voffset, SReg_128:{ *:[v4i32] }:$rsrc, SCSrc_b32:{ *:[i32] }:$soffset, (timm:{ *:[i32] }):$offset, (as_i8timm:{ *:[i8] } ?:{ *:[i32] }:$format), (extract_cpol:{ *:[i32] } ?:{ *:[i32] }:$auxiliary), (extract_swz:{ *:[i1] } ?:{ *:[i32] }:$auxiliary))
        GIR_BuildMI, /*InsnID*/0, /*Opcode*/GIMT_Encode2(AMDGPU::TBUFFER_LOAD_FORMAT_D16_X_OFFEN),
        GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/0, // DstI[vdata]
        GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/3, // voffset
        GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/1, // rsrc
        GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/0, // soffset
        GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/5, // offset
        GIR_CustomOperandRenderer, /*InsnID*/0, /*OldInsnID*/0, /*OpIdx*/6, /*OperandRenderer*/GIMT_Encode2(GICR_renderTruncTImm), // format
        GIR_CustomOperandRenderer, /*InsnID*/0, /*OldInsnID*/0, /*OpIdx*/7, /*OperandRenderer*/GIMT_Encode2(GICR_renderExtractCPol), // auxiliary
        GIR_CustomOperandRenderer, /*InsnID*/0, /*OldInsnID*/0, /*OpIdx*/7, /*OperandRenderer*/GIMT_Encode2(GICR_renderExtractSWZ), // auxiliary
        GIR_MergeMemOperands, /*InsnID*/0, /*NumInsns*/1, /*MergeInsnID's*/0,
        GIR_ConstrainSelectedInstOperands, /*InsnID*/0,
        GIR_EraseFromParent, /*InsnID*/0,
        // GIR_Coverage, 5663,
        GIR_Done,
      // Label 7309: @533439
      GIM_Try, /*On fail goto*//*Label 7310*/ GIMT_Encode4(533530), // Rule ID 5667 //
        GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasPackedD16VMem),
        GIM_CheckConstantInt8, /*MI*/0, /*Op*/2, 0,
        // MIs[0] offset
        GIM_CheckIsImm, /*MI*/0, /*Op*/5,
        // MIs[0] format
        GIM_CheckIsImm, /*MI*/0, /*Op*/6,
        // MIs[0] auxiliary
        GIM_CheckIsImm, /*MI*/0, /*Op*/7,
        // MIs[0] Operand 8
        GIM_CheckLiteralInt, /*MI*/0, /*Op*/8, GIMT_Encode8(0),
        GIM_CheckComplexPattern, /*MI*/0, /*Op*/4, /*Renderer*/GIMT_Encode2(0), GIMT_Encode2(GICP_gi_buf_soffset),
        // (SItbuffer_load_d16:{ *:[i32] } v4i32:{ *:[v4i32] }:$rsrc, 0:{ *:[i32] }, i32:{ *:[i32] }:$voffset, (BUFSOffset:{ *:[i32] } i32:{ *:[i32] }:$soffset), (timm:{ *:[i32] }):$offset, (timm:{ *:[i32] }):$format, (timm:{ *:[i32] }):$auxiliary, 0:{ *:[i1] })  =>  (TBUFFER_LOAD_FORMAT_D16_X_VBUFFER_OFFEN:{ *:[i32] } VGPR_32:{ *:[i32] }:$voffset, SReg_128:{ *:[v4i32] }:$rsrc, SCSrc_b32:{ *:[i32] }:$soffset, (timm:{ *:[i32] }):$offset, (as_i8timm:{ *:[i8] } ?:{ *:[i32] }:$format), (extract_cpol:{ *:[i32] } ?:{ *:[i32] }:$auxiliary), (extract_swz:{ *:[i1] } ?:{ *:[i32] }:$auxiliary))
        GIR_BuildMI, /*InsnID*/0, /*Opcode*/GIMT_Encode2(AMDGPU::TBUFFER_LOAD_FORMAT_D16_X_VBUFFER_OFFEN),
        GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/0, // DstI[vdata]
        GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/3, // voffset
        GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/1, // rsrc
        GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/0, // soffset
        GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/5, // offset
        GIR_CustomOperandRenderer, /*InsnID*/0, /*OldInsnID*/0, /*OpIdx*/6, /*OperandRenderer*/GIMT_Encode2(GICR_renderTruncTImm), // format
        GIR_CustomOperandRenderer, /*InsnID*/0, /*OldInsnID*/0, /*OpIdx*/7, /*OperandRenderer*/GIMT_Encode2(GICR_renderExtractCPol), // auxiliary
        GIR_CustomOperandRenderer, /*InsnID*/0, /*OldInsnID*/0, /*OpIdx*/7, /*OperandRenderer*/GIMT_Encode2(GICR_renderExtractSWZ), // auxiliary
        GIR_MergeMemOperands, /*InsnID*/0, /*NumInsns*/1, /*MergeInsnID's*/0,
        GIR_ConstrainSelectedInstOperands, /*InsnID*/0,
        GIR_EraseFromParent, /*InsnID*/0,
        // GIR_Coverage, 5667,
        GIR_Done,
      // Label 7310: @533530
      GIM_Try, /*On fail goto*//*Label 7311*/ GIMT_Encode4(533613), // Rule ID 5638 //
        GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasUnpackedD16VMem),
        GIM_CheckConstantInt8, /*MI*/0, /*Op*/3, 0,
        // MIs[0] offset
        GIM_CheckIsImm, /*MI*/0, /*Op*/5,
        // MIs[0] format
        GIM_CheckIsImm, /*MI*/0, /*Op*/6,
        // MIs[0] auxiliary
        GIM_CheckIsImm, /*MI*/0, /*Op*/7,
        // MIs[0] Operand 8
        GIM_CheckIsImm, /*MI*/0, /*Op*/8,
        GIM_CheckComplexPattern, /*MI*/0, /*Op*/4, /*Renderer*/GIMT_Encode2(0), GIMT_Encode2(GICP_gi_buf_soffset),
        // (SItbuffer_load_d16:{ *:[i32] } v4i32:{ *:[v4i32] }:$rsrc, i32:{ *:[i32] }:$vindex, 0:{ *:[i32] }, (BUFSOffset:{ *:[i32] } i32:{ *:[i32] }:$soffset), (timm:{ *:[i32] }):$offset, (timm:{ *:[i32] }):$format, (timm:{ *:[i32] }):$auxiliary, (timm:{ *:[i1] }))  =>  (TBUFFER_LOAD_FORMAT_D16_X_gfx80_IDXEN:{ *:[i32] } VGPR_32:{ *:[i32] }:$vindex, SReg_128:{ *:[v4i32] }:$rsrc, SCSrc_b32:{ *:[i32] }:$soffset, (timm:{ *:[i32] }):$offset, (as_i8timm:{ *:[i8] } ?:{ *:[i32] }:$format), (extract_cpol:{ *:[i32] } ?:{ *:[i32] }:$auxiliary), (extract_swz:{ *:[i1] } ?:{ *:[i32] }:$auxiliary))
        GIR_BuildMI, /*InsnID*/0, /*Opcode*/GIMT_Encode2(AMDGPU::TBUFFER_LOAD_FORMAT_D16_X_gfx80_IDXEN),
        GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/0, // DstI[vdata]
        GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/2, // vindex
        GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/1, // rsrc
        GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/0, // soffset
        GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/5, // offset
        GIR_CustomOperandRenderer, /*InsnID*/0, /*OldInsnID*/0, /*OpIdx*/6, /*OperandRenderer*/GIMT_Encode2(GICR_renderTruncTImm), // format
        GIR_CustomOperandRenderer, /*InsnID*/0, /*OldInsnID*/0, /*OpIdx*/7, /*OperandRenderer*/GIMT_Encode2(GICR_renderExtractCPol), // auxiliary
        GIR_CustomOperandRenderer, /*InsnID*/0, /*OldInsnID*/0, /*OpIdx*/7, /*OperandRenderer*/GIMT_Encode2(GICR_renderExtractSWZ), // auxiliary
        GIR_MergeMemOperands, /*InsnID*/0, /*NumInsns*/1, /*MergeInsnID's*/0,
        GIR_ConstrainSelectedInstOperands, /*InsnID*/0,
        GIR_EraseFromParent, /*InsnID*/0,
        // GIR_Coverage, 5638,
        GIR_Done,
      // Label 7311: @533613
      GIM_Try, /*On fail goto*//*Label 7312*/ GIMT_Encode4(533696), // Rule ID 5662 //
        GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasPackedD16VMem_HasUnrestrictedSOffset),
        GIM_CheckConstantInt8, /*MI*/0, /*Op*/3, 0,
        // MIs[0] offset
        GIM_CheckIsImm, /*MI*/0, /*Op*/5,
        // MIs[0] format
        GIM_CheckIsImm, /*MI*/0, /*Op*/6,
        // MIs[0] auxiliary
        GIM_CheckIsImm, /*MI*/0, /*Op*/7,
        // MIs[0] Operand 8
        GIM_CheckIsImm, /*MI*/0, /*Op*/8,
        GIM_CheckComplexPattern, /*MI*/0, /*Op*/4, /*Renderer*/GIMT_Encode2(0), GIMT_Encode2(GICP_gi_buf_soffset),
        // (SItbuffer_load_d16:{ *:[i32] } v4i32:{ *:[v4i32] }:$rsrc, i32:{ *:[i32] }:$vindex, 0:{ *:[i32] }, (BUFSOffset:{ *:[i32] } i32:{ *:[i32] }:$soffset), (timm:{ *:[i32] }):$offset, (timm:{ *:[i32] }):$format, (timm:{ *:[i32] }):$auxiliary, (timm:{ *:[i1] }))  =>  (TBUFFER_LOAD_FORMAT_D16_X_IDXEN:{ *:[i32] } VGPR_32:{ *:[i32] }:$vindex, SReg_128:{ *:[v4i32] }:$rsrc, SCSrc_b32:{ *:[i32] }:$soffset, (timm:{ *:[i32] }):$offset, (as_i8timm:{ *:[i8] } ?:{ *:[i32] }:$format), (extract_cpol:{ *:[i32] } ?:{ *:[i32] }:$auxiliary), (extract_swz:{ *:[i1] } ?:{ *:[i32] }:$auxiliary))
        GIR_BuildMI, /*InsnID*/0, /*Opcode*/GIMT_Encode2(AMDGPU::TBUFFER_LOAD_FORMAT_D16_X_IDXEN),
        GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/0, // DstI[vdata]
        GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/2, // vindex
        GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/1, // rsrc
        GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/0, // soffset
        GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/5, // offset
        GIR_CustomOperandRenderer, /*InsnID*/0, /*OldInsnID*/0, /*OpIdx*/6, /*OperandRenderer*/GIMT_Encode2(GICR_renderTruncTImm), // format
        GIR_CustomOperandRenderer, /*InsnID*/0, /*OldInsnID*/0, /*OpIdx*/7, /*OperandRenderer*/GIMT_Encode2(GICR_renderExtractCPol), // auxiliary
        GIR_CustomOperandRenderer, /*InsnID*/0, /*OldInsnID*/0, /*OpIdx*/7, /*OperandRenderer*/GIMT_Encode2(GICR_renderExtractSWZ), // auxiliary
        GIR_MergeMemOperands, /*InsnID*/0, /*NumInsns*/1, /*MergeInsnID's*/0,
        GIR_ConstrainSelectedInstOperands, /*InsnID*/0,
        GIR_EraseFromParent, /*InsnID*/0,
        // GIR_Coverage, 5662,
        GIR_Done,
      // Label 7312: @533696
      GIM_Try, /*On fail goto*//*Label 7313*/ GIMT_Encode4(533779), // Rule ID 5666 //
        GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasPackedD16VMem),
        GIM_CheckConstantInt8, /*MI*/0, /*Op*/3, 0,
        // MIs[0] offset
        GIM_CheckIsImm, /*MI*/0, /*Op*/5,
        // MIs[0] format
        GIM_CheckIsImm, /*MI*/0, /*Op*/6,
        // MIs[0] auxiliary
        GIM_CheckIsImm, /*MI*/0, /*Op*/7,
        // MIs[0] Operand 8
        GIM_CheckIsImm, /*MI*/0, /*Op*/8,
        GIM_CheckComplexPattern, /*MI*/0, /*Op*/4, /*Renderer*/GIMT_Encode2(0), GIMT_Encode2(GICP_gi_buf_soffset),
        // (SItbuffer_load_d16:{ *:[i32] } v4i32:{ *:[v4i32] }:$rsrc, i32:{ *:[i32] }:$vindex, 0:{ *:[i32] }, (BUFSOffset:{ *:[i32] } i32:{ *:[i32] }:$soffset), (timm:{ *:[i32] }):$offset, (timm:{ *:[i32] }):$format, (timm:{ *:[i32] }):$auxiliary, (timm:{ *:[i1] }))  =>  (TBUFFER_LOAD_FORMAT_D16_X_VBUFFER_IDXEN:{ *:[i32] } VGPR_32:{ *:[i32] }:$vindex, SReg_128:{ *:[v4i32] }:$rsrc, SCSrc_b32:{ *:[i32] }:$soffset, (timm:{ *:[i32] }):$offset, (as_i8timm:{ *:[i8] } ?:{ *:[i32] }:$format), (extract_cpol:{ *:[i32] } ?:{ *:[i32] }:$auxiliary), (extract_swz:{ *:[i1] } ?:{ *:[i32] }:$auxiliary))
        GIR_BuildMI, /*InsnID*/0, /*Opcode*/GIMT_Encode2(AMDGPU::TBUFFER_LOAD_FORMAT_D16_X_VBUFFER_IDXEN),
        GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/0, // DstI[vdata]
        GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/2, // vindex
        GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/1, // rsrc
        GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/0, // soffset
        GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/5, // offset
        GIR_CustomOperandRenderer, /*InsnID*/0, /*OldInsnID*/0, /*OpIdx*/6, /*OperandRenderer*/GIMT_Encode2(GICR_renderTruncTImm), // format
        GIR_CustomOperandRenderer, /*InsnID*/0, /*OldInsnID*/0, /*OpIdx*/7, /*OperandRenderer*/GIMT_Encode2(GICR_renderExtractCPol), // auxiliary
        GIR_CustomOperandRenderer, /*InsnID*/0, /*OldInsnID*/0, /*OpIdx*/7, /*OperandRenderer*/GIMT_Encode2(GICR_renderExtractSWZ), // auxiliary
        GIR_MergeMemOperands, /*InsnID*/0, /*NumInsns*/1, /*MergeInsnID's*/0,
        GIR_ConstrainSelectedInstOperands, /*InsnID*/0,
        GIR_EraseFromParent, /*InsnID*/0,
        // GIR_Coverage, 5666,
        GIR_Done,
      // Label 7313: @533779
      GIM_Try, /*On fail goto*//*Label 7314*/ GIMT_Encode4(533898), // Rule ID 5640 //
        GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasUnpackedD16VMem),
        // MIs[0] offset
        GIM_CheckIsImm, /*MI*/0, /*Op*/5,
        // MIs[0] format
        GIM_CheckIsImm, /*MI*/0, /*Op*/6,
        // MIs[0] auxiliary
        GIM_CheckIsImm, /*MI*/0, /*Op*/7,
        // MIs[0] Operand 8
        GIM_CheckIsImm, /*MI*/0, /*Op*/8,
        GIM_CheckComplexPattern, /*MI*/0, /*Op*/4, /*Renderer*/GIMT_Encode2(0), GIMT_Encode2(GICP_gi_buf_soffset),
        // (SItbuffer_load_d16:{ *:[i32] } v4i32:{ *:[v4i32] }:$rsrc, i32:{ *:[i32] }:$vindex, i32:{ *:[i32] }:$voffset, (BUFSOffset:{ *:[i32] } i32:{ *:[i32] }:$soffset), (timm:{ *:[i32] }):$offset, (timm:{ *:[i32] }):$format, (timm:{ *:[i32] }):$auxiliary, (timm:{ *:[i1] }))  =>  (TBUFFER_LOAD_FORMAT_D16_X_gfx80_BOTHEN:{ *:[i32] } (REG_SEQUENCE:{ *:[i64] } VReg_64:{ *:[i32] }, VGPR_32:{ *:[i32] }:$vindex, sub0:{ *:[i32] }, VGPR_32:{ *:[i32] }:$voffset, sub1:{ *:[i32] }), SReg_128:{ *:[v4i32] }:$rsrc, SCSrc_b32:{ *:[i32] }:$soffset, (timm:{ *:[i32] }):$offset, (as_i8timm:{ *:[i8] } ?:{ *:[i32] }:$format), (extract_cpol:{ *:[i32] } ?:{ *:[i32] }:$auxiliary), (extract_swz:{ *:[i1] } ?:{ *:[i32] }:$auxiliary))
        GIR_MakeTempReg, /*TempRegID*/0, /*TypeID*/GILLT_s64,
        GIR_BuildMI, /*InsnID*/1, /*Opcode*/GIMT_Encode2(TargetOpcode::REG_SEQUENCE),
        GIR_AddTempRegister, /*InsnID*/1, /*TempRegID*/0, /*TempRegFlags*/GIMT_Encode2(RegState::Define),
        GIR_Copy, /*NewInsnID*/1, /*OldInsnID*/0, /*OpIdx*/2, // vindex
        GIR_AddImm8, /*InsnID*/1, /*SubRegIndex*/3,
        GIR_Copy, /*NewInsnID*/1, /*OldInsnID*/0, /*OpIdx*/3, // voffset
        GIR_AddImm8, /*InsnID*/1, /*SubRegIndex*/11,
        GIR_ConstrainOperandRC, /*InsnID*/1, /*Op*/0, GIMT_Encode2(AMDGPU::VReg_64RegClassID),
        GIR_ConstrainOperandRC, /*InsnID*/1, /*Op*/1, GIMT_Encode2(AMDGPU::VGPR_32RegClassID),
        GIR_ConstrainOperandRC, /*InsnID*/1, /*Op*/3, GIMT_Encode2(AMDGPU::VGPR_32RegClassID),
        GIR_BuildMI, /*InsnID*/0, /*Opcode*/GIMT_Encode2(AMDGPU::TBUFFER_LOAD_FORMAT_D16_X_gfx80_BOTHEN),
        GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/0, // DstI[vdata]
        GIR_AddSimpleTempRegister, /*InsnID*/0, /*TempRegID*/0,
        GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/1, // rsrc
        GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/0, // soffset
        GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/5, // offset
        GIR_CustomOperandRenderer, /*InsnID*/0, /*OldInsnID*/0, /*OpIdx*/6, /*OperandRenderer*/GIMT_Encode2(GICR_renderTruncTImm), // format
        GIR_CustomOperandRenderer, /*InsnID*/0, /*OldInsnID*/0, /*OpIdx*/7, /*OperandRenderer*/GIMT_Encode2(GICR_renderExtractCPol), // auxiliary
        GIR_CustomOperandRenderer, /*InsnID*/0, /*OldInsnID*/0, /*OpIdx*/7, /*OperandRenderer*/GIMT_Encode2(GICR_renderExtractSWZ), // auxiliary
        GIR_MergeMemOperands, /*InsnID*/0, /*NumInsns*/1, /*MergeInsnID's*/0,
        GIR_ConstrainSelectedInstOperands, /*InsnID*/0,
        GIR_EraseFromParent, /*InsnID*/0,
        // GIR_Coverage, 5640,
        GIR_Done,
      // Label 7314: @533898
      GIM_Try, /*On fail goto*//*Label 7315*/ GIMT_Encode4(534017), // Rule ID 5664 //
        GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasPackedD16VMem_HasUnrestrictedSOffset),
        // MIs[0] offset
        GIM_CheckIsImm, /*MI*/0, /*Op*/5,
        // MIs[0] format
        GIM_CheckIsImm, /*MI*/0, /*Op*/6,
        // MIs[0] auxiliary
        GIM_CheckIsImm, /*MI*/0, /*Op*/7,
        // MIs[0] Operand 8
        GIM_CheckIsImm, /*MI*/0, /*Op*/8,
        GIM_CheckComplexPattern, /*MI*/0, /*Op*/4, /*Renderer*/GIMT_Encode2(0), GIMT_Encode2(GICP_gi_buf_soffset),
        // (SItbuffer_load_d16:{ *:[i32] } v4i32:{ *:[v4i32] }:$rsrc, i32:{ *:[i32] }:$vindex, i32:{ *:[i32] }:$voffset, (BUFSOffset:{ *:[i32] } i32:{ *:[i32] }:$soffset), (timm:{ *:[i32] }):$offset, (timm:{ *:[i32] }):$format, (timm:{ *:[i32] }):$auxiliary, (timm:{ *:[i1] }))  =>  (TBUFFER_LOAD_FORMAT_D16_X_BOTHEN:{ *:[i32] } (REG_SEQUENCE:{ *:[i64] } VReg_64:{ *:[i32] }, VGPR_32:{ *:[i32] }:$vindex, sub0:{ *:[i32] }, VGPR_32:{ *:[i32] }:$voffset, sub1:{ *:[i32] }), SReg_128:{ *:[v4i32] }:$rsrc, SCSrc_b32:{ *:[i32] }:$soffset, (timm:{ *:[i32] }):$offset, (as_i8timm:{ *:[i8] } ?:{ *:[i32] }:$format), (extract_cpol:{ *:[i32] } ?:{ *:[i32] }:$auxiliary), (extract_swz:{ *:[i1] } ?:{ *:[i32] }:$auxiliary))
        GIR_MakeTempReg, /*TempRegID*/0, /*TypeID*/GILLT_s64,
        GIR_BuildMI, /*InsnID*/1, /*Opcode*/GIMT_Encode2(TargetOpcode::REG_SEQUENCE),
        GIR_AddTempRegister, /*InsnID*/1, /*TempRegID*/0, /*TempRegFlags*/GIMT_Encode2(RegState::Define),
        GIR_Copy, /*NewInsnID*/1, /*OldInsnID*/0, /*OpIdx*/2, // vindex
        GIR_AddImm8, /*InsnID*/1, /*SubRegIndex*/3,
        GIR_Copy, /*NewInsnID*/1, /*OldInsnID*/0, /*OpIdx*/3, // voffset
        GIR_AddImm8, /*InsnID*/1, /*SubRegIndex*/11,
        GIR_ConstrainOperandRC, /*InsnID*/1, /*Op*/0, GIMT_Encode2(AMDGPU::VReg_64RegClassID),
        GIR_ConstrainOperandRC, /*InsnID*/1, /*Op*/1, GIMT_Encode2(AMDGPU::VGPR_32RegClassID),
        GIR_ConstrainOperandRC, /*InsnID*/1, /*Op*/3, GIMT_Encode2(AMDGPU::VGPR_32RegClassID),
        GIR_BuildMI, /*InsnID*/0, /*Opcode*/GIMT_Encode2(AMDGPU::TBUFFER_LOAD_FORMAT_D16_X_BOTHEN),
        GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/0, // DstI[vdata]
        GIR_AddSimpleTempRegister, /*InsnID*/0, /*TempRegID*/0,
        GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/1, // rsrc
        GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/0, // soffset
        GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/5, // offset
        GIR_CustomOperandRenderer, /*InsnID*/0, /*OldInsnID*/0, /*OpIdx*/6, /*OperandRenderer*/GIMT_Encode2(GICR_renderTruncTImm), // format
        GIR_CustomOperandRenderer, /*InsnID*/0, /*OldInsnID*/0, /*OpIdx*/7, /*OperandRenderer*/GIMT_Encode2(GICR_renderExtractCPol), // auxiliary
        GIR_CustomOperandRenderer, /*InsnID*/0, /*OldInsnID*/0, /*OpIdx*/7, /*OperandRenderer*/GIMT_Encode2(GICR_renderExtractSWZ), // auxiliary
        GIR_MergeMemOperands, /*InsnID*/0, /*NumInsns*/1, /*MergeInsnID's*/0,
        GIR_ConstrainSelectedInstOperands, /*InsnID*/0,
        GIR_EraseFromParent, /*InsnID*/0,
        // GIR_Coverage, 5664,
        GIR_Done,
      // Label 7315: @534017
      GIM_Try, /*On fail goto*//*Label 7316*/ GIMT_Encode4(534136), // Rule ID 5668 //
        GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasPackedD16VMem),
        // MIs[0] offset
        GIM_CheckIsImm, /*MI*/0, /*Op*/5,
        // MIs[0] format
        GIM_CheckIsImm, /*MI*/0, /*Op*/6,
        // MIs[0] auxiliary
        GIM_CheckIsImm, /*MI*/0, /*Op*/7,
        // MIs[0] Operand 8
        GIM_CheckIsImm, /*MI*/0, /*Op*/8,
        GIM_CheckComplexPattern, /*MI*/0, /*Op*/4, /*Renderer*/GIMT_Encode2(0), GIMT_Encode2(GICP_gi_buf_soffset),
        // (SItbuffer_load_d16:{ *:[i32] } v4i32:{ *:[v4i32] }:$rsrc, i32:{ *:[i32] }:$vindex, i32:{ *:[i32] }:$voffset, (BUFSOffset:{ *:[i32] } i32:{ *:[i32] }:$soffset), (timm:{ *:[i32] }):$offset, (timm:{ *:[i32] }):$format, (timm:{ *:[i32] }):$auxiliary, (timm:{ *:[i1] }))  =>  (TBUFFER_LOAD_FORMAT_D16_X_VBUFFER_BOTHEN:{ *:[i32] } (REG_SEQUENCE:{ *:[i64] } VReg_64:{ *:[i32] }, VGPR_32:{ *:[i32] }:$vindex, sub0:{ *:[i32] }, VGPR_32:{ *:[i32] }:$voffset, sub1:{ *:[i32] }), SReg_128:{ *:[v4i32] }:$rsrc, SCSrc_b32:{ *:[i32] }:$soffset, (timm:{ *:[i32] }):$offset, (as_i8timm:{ *:[i8] } ?:{ *:[i32] }:$format), (extract_cpol:{ *:[i32] } ?:{ *:[i32] }:$auxiliary), (extract_swz:{ *:[i1] } ?:{ *:[i32] }:$auxiliary))
        GIR_MakeTempReg, /*TempRegID*/0, /*TypeID*/GILLT_s64,
        GIR_BuildMI, /*InsnID*/1, /*Opcode*/GIMT_Encode2(TargetOpcode::REG_SEQUENCE),
        GIR_AddTempRegister, /*InsnID*/1, /*TempRegID*/0, /*TempRegFlags*/GIMT_Encode2(RegState::Define),
        GIR_Copy, /*NewInsnID*/1, /*OldInsnID*/0, /*OpIdx*/2, // vindex
        GIR_AddImm8, /*InsnID*/1, /*SubRegIndex*/3,
        GIR_Copy, /*NewInsnID*/1, /*OldInsnID*/0, /*OpIdx*/3, // voffset
        GIR_AddImm8, /*InsnID*/1, /*SubRegIndex*/11,
        GIR_ConstrainOperandRC, /*InsnID*/1, /*Op*/0, GIMT_Encode2(AMDGPU::VReg_64RegClassID),
        GIR_ConstrainOperandRC, /*InsnID*/1, /*Op*/1, GIMT_Encode2(AMDGPU::VGPR_32RegClassID),
        GIR_ConstrainOperandRC, /*InsnID*/1, /*Op*/3, GIMT_Encode2(AMDGPU::VGPR_32RegClassID),
        GIR_BuildMI, /*InsnID*/0, /*Opcode*/GIMT_Encode2(AMDGPU::TBUFFER_LOAD_FORMAT_D16_X_VBUFFER_BOTHEN),
        GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/0, // DstI[vdata]
        GIR_AddSimpleTempRegister, /*InsnID*/0, /*TempRegID*/0,
        GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/1, // rsrc
        GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/0, // soffset
        GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/5, // offset
        GIR_CustomOperandRenderer, /*InsnID*/0, /*OldInsnID*/0, /*OpIdx*/6, /*OperandRenderer*/GIMT_Encode2(GICR_renderTruncTImm), // format
        GIR_CustomOperandRenderer, /*InsnID*/0, /*OldInsnID*/0, /*OpIdx*/7, /*OperandRenderer*/GIMT_Encode2(GICR_renderExtractCPol), // auxiliary
        GIR_CustomOperandRenderer, /*InsnID*/0, /*OldInsnID*/0, /*OpIdx*/7, /*OperandRenderer*/GIMT_Encode2(GICR_renderExtractSWZ), // auxiliary
        GIR_MergeMemOperands, /*InsnID*/0, /*NumInsns*/1, /*MergeInsnID's*/0,
        GIR_ConstrainSelectedInstOperands, /*InsnID*/0,
        GIR_EraseFromParent, /*InsnID*/0,
        // GIR_Coverage, 5668,
        GIR_Done,
      // Label 7316: @534136
      GIM_Reject,
    // Label 7304: @534137
    GIM_Reject,
    // Label 7285: @534138
    GIM_Try, /*On fail goto*//*Label 7317*/ GIMT_Encode4(534933),
      GIM_CheckType, /*MI*/0, /*Op*/1, /*Type*/GILLT_v4s32,
      GIM_CheckType, /*MI*/0, /*Op*/2, /*Type*/GILLT_s32,
      GIM_CheckType, /*MI*/0, /*Op*/3, /*Type*/GILLT_s32,
      GIM_CheckType, /*MI*/0, /*Op*/4, /*Type*/GILLT_s32,
      GIM_CheckRegBankForClass, /*MI*/0, /*Op*/0, /*RC*/GIMT_Encode2(AMDGPU::AV_32RegClassID),
      GIM_Try, /*On fail goto*//*Label 7318*/ GIMT_Encode4(534255), // Rule ID 5669 //
        GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasPackedD16VMem_HasUnrestrictedSOffset),
        GIM_CheckConstantInt8, /*MI*/0, /*Op*/2, 0,
        GIM_CheckConstantInt8, /*MI*/0, /*Op*/3, 0,
        // MIs[0] offset
        GIM_CheckIsImm, /*MI*/0, /*Op*/5,
        // MIs[0] format
        GIM_CheckIsImm, /*MI*/0, /*Op*/6,
        // MIs[0] auxiliary
        GIM_CheckIsImm, /*MI*/0, /*Op*/7,
        // MIs[0] Operand 8
        GIM_CheckLiteralInt, /*MI*/0, /*Op*/8, GIMT_Encode8(0),
        GIM_CheckComplexPattern, /*MI*/0, /*Op*/4, /*Renderer*/GIMT_Encode2(0), GIMT_Encode2(GICP_gi_buf_soffset),
        // (SItbuffer_load_d16:{ *:[v2f16] } v4i32:{ *:[v4i32] }:$rsrc, 0:{ *:[i32] }, 0:{ *:[i32] }, (BUFSOffset:{ *:[i32] } i32:{ *:[i32] }:$soffset), (timm:{ *:[i32] }):$offset, (timm:{ *:[i32] }):$format, (timm:{ *:[i32] }):$auxiliary, 0:{ *:[i1] })  =>  (TBUFFER_LOAD_FORMAT_D16_XY_OFFSET:{ *:[v2f16] } SReg_128:{ *:[v4i32] }:$rsrc, SCSrc_b32:{ *:[i32] }:$soffset, (timm:{ *:[i32] }):$offset, (as_i8timm:{ *:[i8] } ?:{ *:[i32] }:$format), (extract_cpol:{ *:[i32] } ?:{ *:[i32] }:$auxiliary), (extract_swz:{ *:[i1] } ?:{ *:[i32] }:$auxiliary))
        GIR_BuildMI, /*InsnID*/0, /*Opcode*/GIMT_Encode2(AMDGPU::TBUFFER_LOAD_FORMAT_D16_XY_OFFSET),
        GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/0, // DstI[vdata]
        GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/1, // rsrc
        GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/0, // soffset
        GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/5, // offset
        GIR_CustomOperandRenderer, /*InsnID*/0, /*OldInsnID*/0, /*OpIdx*/6, /*OperandRenderer*/GIMT_Encode2(GICR_renderTruncTImm), // format
        GIR_CustomOperandRenderer, /*InsnID*/0, /*OldInsnID*/0, /*OpIdx*/7, /*OperandRenderer*/GIMT_Encode2(GICR_renderExtractCPol), // auxiliary
        GIR_CustomOperandRenderer, /*InsnID*/0, /*OldInsnID*/0, /*OpIdx*/7, /*OperandRenderer*/GIMT_Encode2(GICR_renderExtractSWZ), // auxiliary
        GIR_MergeMemOperands, /*InsnID*/0, /*NumInsns*/1, /*MergeInsnID's*/0,
        GIR_ConstrainSelectedInstOperands, /*InsnID*/0,
        GIR_EraseFromParent, /*InsnID*/0,
        // GIR_Coverage, 5669,
        GIR_Done,
      // Label 7318: @534255
      GIM_Try, /*On fail goto*//*Label 7319*/ GIMT_Encode4(534346), // Rule ID 5673 //
        GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasPackedD16VMem),
        GIM_CheckConstantInt8, /*MI*/0, /*Op*/2, 0,
        GIM_CheckConstantInt8, /*MI*/0, /*Op*/3, 0,
        // MIs[0] offset
        GIM_CheckIsImm, /*MI*/0, /*Op*/5,
        // MIs[0] format
        GIM_CheckIsImm, /*MI*/0, /*Op*/6,
        // MIs[0] auxiliary
        GIM_CheckIsImm, /*MI*/0, /*Op*/7,
        // MIs[0] Operand 8
        GIM_CheckLiteralInt, /*MI*/0, /*Op*/8, GIMT_Encode8(0),
        GIM_CheckComplexPattern, /*MI*/0, /*Op*/4, /*Renderer*/GIMT_Encode2(0), GIMT_Encode2(GICP_gi_buf_soffset),
        // (SItbuffer_load_d16:{ *:[v2f16] } v4i32:{ *:[v4i32] }:$rsrc, 0:{ *:[i32] }, 0:{ *:[i32] }, (BUFSOffset:{ *:[i32] } i32:{ *:[i32] }:$soffset), (timm:{ *:[i32] }):$offset, (timm:{ *:[i32] }):$format, (timm:{ *:[i32] }):$auxiliary, 0:{ *:[i1] })  =>  (TBUFFER_LOAD_FORMAT_D16_XY_VBUFFER_OFFSET:{ *:[v2f16] } SReg_128:{ *:[v4i32] }:$rsrc, SCSrc_b32:{ *:[i32] }:$soffset, (timm:{ *:[i32] }):$offset, (as_i8timm:{ *:[i8] } ?:{ *:[i32] }:$format), (extract_cpol:{ *:[i32] } ?:{ *:[i32] }:$auxiliary), (extract_swz:{ *:[i1] } ?:{ *:[i32] }:$auxiliary))
        GIR_BuildMI, /*InsnID*/0, /*Opcode*/GIMT_Encode2(AMDGPU::TBUFFER_LOAD_FORMAT_D16_XY_VBUFFER_OFFSET),
        GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/0, // DstI[vdata]
        GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/1, // rsrc
        GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/0, // soffset
        GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/5, // offset
        GIR_CustomOperandRenderer, /*InsnID*/0, /*OldInsnID*/0, /*OpIdx*/6, /*OperandRenderer*/GIMT_Encode2(GICR_renderTruncTImm), // format
        GIR_CustomOperandRenderer, /*InsnID*/0, /*OldInsnID*/0, /*OpIdx*/7, /*OperandRenderer*/GIMT_Encode2(GICR_renderExtractCPol), // auxiliary
        GIR_CustomOperandRenderer, /*InsnID*/0, /*OldInsnID*/0, /*OpIdx*/7, /*OperandRenderer*/GIMT_Encode2(GICR_renderExtractSWZ), // auxiliary
        GIR_MergeMemOperands, /*InsnID*/0, /*NumInsns*/1, /*MergeInsnID's*/0,
        GIR_ConstrainSelectedInstOperands, /*InsnID*/0,
        GIR_EraseFromParent, /*InsnID*/0,
        // GIR_Coverage, 5673,
        GIR_Done,
      // Label 7319: @534346
      GIM_Try, /*On fail goto*//*Label 7320*/ GIMT_Encode4(534437), // Rule ID 5671 //
        GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasPackedD16VMem_HasUnrestrictedSOffset),
        GIM_CheckConstantInt8, /*MI*/0, /*Op*/2, 0,
        // MIs[0] offset
        GIM_CheckIsImm, /*MI*/0, /*Op*/5,
        // MIs[0] format
        GIM_CheckIsImm, /*MI*/0, /*Op*/6,
        // MIs[0] auxiliary
        GIM_CheckIsImm, /*MI*/0, /*Op*/7,
        // MIs[0] Operand 8
        GIM_CheckLiteralInt, /*MI*/0, /*Op*/8, GIMT_Encode8(0),
        GIM_CheckComplexPattern, /*MI*/0, /*Op*/4, /*Renderer*/GIMT_Encode2(0), GIMT_Encode2(GICP_gi_buf_soffset),
        // (SItbuffer_load_d16:{ *:[v2f16] } v4i32:{ *:[v4i32] }:$rsrc, 0:{ *:[i32] }, i32:{ *:[i32] }:$voffset, (BUFSOffset:{ *:[i32] } i32:{ *:[i32] }:$soffset), (timm:{ *:[i32] }):$offset, (timm:{ *:[i32] }):$format, (timm:{ *:[i32] }):$auxiliary, 0:{ *:[i1] })  =>  (TBUFFER_LOAD_FORMAT_D16_XY_OFFEN:{ *:[v2f16] } VGPR_32:{ *:[i32] }:$voffset, SReg_128:{ *:[v4i32] }:$rsrc, SCSrc_b32:{ *:[i32] }:$soffset, (timm:{ *:[i32] }):$offset, (as_i8timm:{ *:[i8] } ?:{ *:[i32] }:$format), (extract_cpol:{ *:[i32] } ?:{ *:[i32] }:$auxiliary), (extract_swz:{ *:[i1] } ?:{ *:[i32] }:$auxiliary))
        GIR_BuildMI, /*InsnID*/0, /*Opcode*/GIMT_Encode2(AMDGPU::TBUFFER_LOAD_FORMAT_D16_XY_OFFEN),
        GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/0, // DstI[vdata]
        GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/3, // voffset
        GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/1, // rsrc
        GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/0, // soffset
        GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/5, // offset
        GIR_CustomOperandRenderer, /*InsnID*/0, /*OldInsnID*/0, /*OpIdx*/6, /*OperandRenderer*/GIMT_Encode2(GICR_renderTruncTImm), // format
        GIR_CustomOperandRenderer, /*InsnID*/0, /*OldInsnID*/0, /*OpIdx*/7, /*OperandRenderer*/GIMT_Encode2(GICR_renderExtractCPol), // auxiliary
        GIR_CustomOperandRenderer, /*InsnID*/0, /*OldInsnID*/0, /*OpIdx*/7, /*OperandRenderer*/GIMT_Encode2(GICR_renderExtractSWZ), // auxiliary
        GIR_MergeMemOperands, /*InsnID*/0, /*NumInsns*/1, /*MergeInsnID's*/0,
        GIR_ConstrainSelectedInstOperands, /*InsnID*/0,
        GIR_EraseFromParent, /*InsnID*/0,
        // GIR_Coverage, 5671,
        GIR_Done,
      // Label 7320: @534437
      GIM_Try, /*On fail goto*//*Label 7321*/ GIMT_Encode4(534528), // Rule ID 5675 //
        GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasPackedD16VMem),
        GIM_CheckConstantInt8, /*MI*/0, /*Op*/2, 0,
        // MIs[0] offset
        GIM_CheckIsImm, /*MI*/0, /*Op*/5,
        // MIs[0] format
        GIM_CheckIsImm, /*MI*/0, /*Op*/6,
        // MIs[0] auxiliary
        GIM_CheckIsImm, /*MI*/0, /*Op*/7,
        // MIs[0] Operand 8
        GIM_CheckLiteralInt, /*MI*/0, /*Op*/8, GIMT_Encode8(0),
        GIM_CheckComplexPattern, /*MI*/0, /*Op*/4, /*Renderer*/GIMT_Encode2(0), GIMT_Encode2(GICP_gi_buf_soffset),
        // (SItbuffer_load_d16:{ *:[v2f16] } v4i32:{ *:[v4i32] }:$rsrc, 0:{ *:[i32] }, i32:{ *:[i32] }:$voffset, (BUFSOffset:{ *:[i32] } i32:{ *:[i32] }:$soffset), (timm:{ *:[i32] }):$offset, (timm:{ *:[i32] }):$format, (timm:{ *:[i32] }):$auxiliary, 0:{ *:[i1] })  =>  (TBUFFER_LOAD_FORMAT_D16_XY_VBUFFER_OFFEN:{ *:[v2f16] } VGPR_32:{ *:[i32] }:$voffset, SReg_128:{ *:[v4i32] }:$rsrc, SCSrc_b32:{ *:[i32] }:$soffset, (timm:{ *:[i32] }):$offset, (as_i8timm:{ *:[i8] } ?:{ *:[i32] }:$format), (extract_cpol:{ *:[i32] } ?:{ *:[i32] }:$auxiliary), (extract_swz:{ *:[i1] } ?:{ *:[i32] }:$auxiliary))
        GIR_BuildMI, /*InsnID*/0, /*Opcode*/GIMT_Encode2(AMDGPU::TBUFFER_LOAD_FORMAT_D16_XY_VBUFFER_OFFEN),
        GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/0, // DstI[vdata]
        GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/3, // voffset
        GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/1, // rsrc
        GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/0, // soffset
        GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/5, // offset
        GIR_CustomOperandRenderer, /*InsnID*/0, /*OldInsnID*/0, /*OpIdx*/6, /*OperandRenderer*/GIMT_Encode2(GICR_renderTruncTImm), // format
        GIR_CustomOperandRenderer, /*InsnID*/0, /*OldInsnID*/0, /*OpIdx*/7, /*OperandRenderer*/GIMT_Encode2(GICR_renderExtractCPol), // auxiliary
        GIR_CustomOperandRenderer, /*InsnID*/0, /*OldInsnID*/0, /*OpIdx*/7, /*OperandRenderer*/GIMT_Encode2(GICR_renderExtractSWZ), // auxiliary
        GIR_MergeMemOperands, /*InsnID*/0, /*NumInsns*/1, /*MergeInsnID's*/0,
        GIR_ConstrainSelectedInstOperands, /*InsnID*/0,
        GIR_EraseFromParent, /*InsnID*/0,
        // GIR_Coverage, 5675,
        GIR_Done,
      // Label 7321: @534528
      GIM_Try, /*On fail goto*//*Label 7322*/ GIMT_Encode4(534611), // Rule ID 5670 //
        GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasPackedD16VMem_HasUnrestrictedSOffset),
        GIM_CheckConstantInt8, /*MI*/0, /*Op*/3, 0,
        // MIs[0] offset
        GIM_CheckIsImm, /*MI*/0, /*Op*/5,
        // MIs[0] format
        GIM_CheckIsImm, /*MI*/0, /*Op*/6,
        // MIs[0] auxiliary
        GIM_CheckIsImm, /*MI*/0, /*Op*/7,
        // MIs[0] Operand 8
        GIM_CheckIsImm, /*MI*/0, /*Op*/8,
        GIM_CheckComplexPattern, /*MI*/0, /*Op*/4, /*Renderer*/GIMT_Encode2(0), GIMT_Encode2(GICP_gi_buf_soffset),
        // (SItbuffer_load_d16:{ *:[v2f16] } v4i32:{ *:[v4i32] }:$rsrc, i32:{ *:[i32] }:$vindex, 0:{ *:[i32] }, (BUFSOffset:{ *:[i32] } i32:{ *:[i32] }:$soffset), (timm:{ *:[i32] }):$offset, (timm:{ *:[i32] }):$format, (timm:{ *:[i32] }):$auxiliary, (timm:{ *:[i1] }))  =>  (TBUFFER_LOAD_FORMAT_D16_XY_IDXEN:{ *:[v2f16] } VGPR_32:{ *:[i32] }:$vindex, SReg_128:{ *:[v4i32] }:$rsrc, SCSrc_b32:{ *:[i32] }:$soffset, (timm:{ *:[i32] }):$offset, (as_i8timm:{ *:[i8] } ?:{ *:[i32] }:$format), (extract_cpol:{ *:[i32] } ?:{ *:[i32] }:$auxiliary), (extract_swz:{ *:[i1] } ?:{ *:[i32] }:$auxiliary))
        GIR_BuildMI, /*InsnID*/0, /*Opcode*/GIMT_Encode2(AMDGPU::TBUFFER_LOAD_FORMAT_D16_XY_IDXEN),
        GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/0, // DstI[vdata]
        GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/2, // vindex
        GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/1, // rsrc
        GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/0, // soffset
        GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/5, // offset
        GIR_CustomOperandRenderer, /*InsnID*/0, /*OldInsnID*/0, /*OpIdx*/6, /*OperandRenderer*/GIMT_Encode2(GICR_renderTruncTImm), // format
        GIR_CustomOperandRenderer, /*InsnID*/0, /*OldInsnID*/0, /*OpIdx*/7, /*OperandRenderer*/GIMT_Encode2(GICR_renderExtractCPol), // auxiliary
        GIR_CustomOperandRenderer, /*InsnID*/0, /*OldInsnID*/0, /*OpIdx*/7, /*OperandRenderer*/GIMT_Encode2(GICR_renderExtractSWZ), // auxiliary
        GIR_MergeMemOperands, /*InsnID*/0, /*NumInsns*/1, /*MergeInsnID's*/0,
        GIR_ConstrainSelectedInstOperands, /*InsnID*/0,
        GIR_EraseFromParent, /*InsnID*/0,
        // GIR_Coverage, 5670,
        GIR_Done,
      // Label 7322: @534611
      GIM_Try, /*On fail goto*//*Label 7323*/ GIMT_Encode4(534694), // Rule ID 5674 //
        GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasPackedD16VMem),
        GIM_CheckConstantInt8, /*MI*/0, /*Op*/3, 0,
        // MIs[0] offset
        GIM_CheckIsImm, /*MI*/0, /*Op*/5,
        // MIs[0] format
        GIM_CheckIsImm, /*MI*/0, /*Op*/6,
        // MIs[0] auxiliary
        GIM_CheckIsImm, /*MI*/0, /*Op*/7,
        // MIs[0] Operand 8
        GIM_CheckIsImm, /*MI*/0, /*Op*/8,
        GIM_CheckComplexPattern, /*MI*/0, /*Op*/4, /*Renderer*/GIMT_Encode2(0), GIMT_Encode2(GICP_gi_buf_soffset),
        // (SItbuffer_load_d16:{ *:[v2f16] } v4i32:{ *:[v4i32] }:$rsrc, i32:{ *:[i32] }:$vindex, 0:{ *:[i32] }, (BUFSOffset:{ *:[i32] } i32:{ *:[i32] }:$soffset), (timm:{ *:[i32] }):$offset, (timm:{ *:[i32] }):$format, (timm:{ *:[i32] }):$auxiliary, (timm:{ *:[i1] }))  =>  (TBUFFER_LOAD_FORMAT_D16_XY_VBUFFER_IDXEN:{ *:[v2f16] } VGPR_32:{ *:[i32] }:$vindex, SReg_128:{ *:[v4i32] }:$rsrc, SCSrc_b32:{ *:[i32] }:$soffset, (timm:{ *:[i32] }):$offset, (as_i8timm:{ *:[i8] } ?:{ *:[i32] }:$format), (extract_cpol:{ *:[i32] } ?:{ *:[i32] }:$auxiliary), (extract_swz:{ *:[i1] } ?:{ *:[i32] }:$auxiliary))
        GIR_BuildMI, /*InsnID*/0, /*Opcode*/GIMT_Encode2(AMDGPU::TBUFFER_LOAD_FORMAT_D16_XY_VBUFFER_IDXEN),
        GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/0, // DstI[vdata]
        GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/2, // vindex
        GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/1, // rsrc
        GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/0, // soffset
        GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/5, // offset
        GIR_CustomOperandRenderer, /*InsnID*/0, /*OldInsnID*/0, /*OpIdx*/6, /*OperandRenderer*/GIMT_Encode2(GICR_renderTruncTImm), // format
        GIR_CustomOperandRenderer, /*InsnID*/0, /*OldInsnID*/0, /*OpIdx*/7, /*OperandRenderer*/GIMT_Encode2(GICR_renderExtractCPol), // auxiliary
        GIR_CustomOperandRenderer, /*InsnID*/0, /*OldInsnID*/0, /*OpIdx*/7, /*OperandRenderer*/GIMT_Encode2(GICR_renderExtractSWZ), // auxiliary
        GIR_MergeMemOperands, /*InsnID*/0, /*NumInsns*/1, /*MergeInsnID's*/0,
        GIR_ConstrainSelectedInstOperands, /*InsnID*/0,
        GIR_EraseFromParent, /*InsnID*/0,
        // GIR_Coverage, 5674,
        GIR_Done,
      // Label 7323: @534694
      GIM_Try, /*On fail goto*//*Label 7324*/ GIMT_Encode4(534813), // Rule ID 5672 //
        GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasPackedD16VMem_HasUnrestrictedSOffset),
        // MIs[0] offset
        GIM_CheckIsImm, /*MI*/0, /*Op*/5,
        // MIs[0] format
        GIM_CheckIsImm, /*MI*/0, /*Op*/6,
        // MIs[0] auxiliary
        GIM_CheckIsImm, /*MI*/0, /*Op*/7,
        // MIs[0] Operand 8
        GIM_CheckIsImm, /*MI*/0, /*Op*/8,
        GIM_CheckComplexPattern, /*MI*/0, /*Op*/4, /*Renderer*/GIMT_Encode2(0), GIMT_Encode2(GICP_gi_buf_soffset),
        // (SItbuffer_load_d16:{ *:[v2f16] } v4i32:{ *:[v4i32] }:$rsrc, i32:{ *:[i32] }:$vindex, i32:{ *:[i32] }:$voffset, (BUFSOffset:{ *:[i32] } i32:{ *:[i32] }:$soffset), (timm:{ *:[i32] }):$offset, (timm:{ *:[i32] }):$format, (timm:{ *:[i32] }):$auxiliary, (timm:{ *:[i1] }))  =>  (TBUFFER_LOAD_FORMAT_D16_XY_BOTHEN:{ *:[v2f16] } (REG_SEQUENCE:{ *:[i64] } VReg_64:{ *:[i32] }, VGPR_32:{ *:[i32] }:$vindex, sub0:{ *:[i32] }, VGPR_32:{ *:[i32] }:$voffset, sub1:{ *:[i32] }), SReg_128:{ *:[v4i32] }:$rsrc, SCSrc_b32:{ *:[i32] }:$soffset, (timm:{ *:[i32] }):$offset, (as_i8timm:{ *:[i8] } ?:{ *:[i32] }:$format), (extract_cpol:{ *:[i32] } ?:{ *:[i32] }:$auxiliary), (extract_swz:{ *:[i1] } ?:{ *:[i32] }:$auxiliary))
        GIR_MakeTempReg, /*TempRegID*/0, /*TypeID*/GILLT_s64,
        GIR_BuildMI, /*InsnID*/1, /*Opcode*/GIMT_Encode2(TargetOpcode::REG_SEQUENCE),
        GIR_AddTempRegister, /*InsnID*/1, /*TempRegID*/0, /*TempRegFlags*/GIMT_Encode2(RegState::Define),
        GIR_Copy, /*NewInsnID*/1, /*OldInsnID*/0, /*OpIdx*/2, // vindex
        GIR_AddImm8, /*InsnID*/1, /*SubRegIndex*/3,
        GIR_Copy, /*NewInsnID*/1, /*OldInsnID*/0, /*OpIdx*/3, // voffset
        GIR_AddImm8, /*InsnID*/1, /*SubRegIndex*/11,
        GIR_ConstrainOperandRC, /*InsnID*/1, /*Op*/0, GIMT_Encode2(AMDGPU::VReg_64RegClassID),
        GIR_ConstrainOperandRC, /*InsnID*/1, /*Op*/1, GIMT_Encode2(AMDGPU::VGPR_32RegClassID),
        GIR_ConstrainOperandRC, /*InsnID*/1, /*Op*/3, GIMT_Encode2(AMDGPU::VGPR_32RegClassID),
        GIR_BuildMI, /*InsnID*/0, /*Opcode*/GIMT_Encode2(AMDGPU::TBUFFER_LOAD_FORMAT_D16_XY_BOTHEN),
        GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/0, // DstI[vdata]
        GIR_AddSimpleTempRegister, /*InsnID*/0, /*TempRegID*/0,
        GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/1, // rsrc
        GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/0, // soffset
        GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/5, // offset
        GIR_CustomOperandRenderer, /*InsnID*/0, /*OldInsnID*/0, /*OpIdx*/6, /*OperandRenderer*/GIMT_Encode2(GICR_renderTruncTImm), // format
        GIR_CustomOperandRenderer, /*InsnID*/0, /*OldInsnID*/0, /*OpIdx*/7, /*OperandRenderer*/GIMT_Encode2(GICR_renderExtractCPol), // auxiliary
        GIR_CustomOperandRenderer, /*InsnID*/0, /*OldInsnID*/0, /*OpIdx*/7, /*OperandRenderer*/GIMT_Encode2(GICR_renderExtractSWZ), // auxiliary
        GIR_MergeMemOperands, /*InsnID*/0, /*NumInsns*/1, /*MergeInsnID's*/0,
        GIR_ConstrainSelectedInstOperands, /*InsnID*/0,
        GIR_EraseFromParent, /*InsnID*/0,
        // GIR_Coverage, 5672,
        GIR_Done,
      // Label 7324: @534813
      GIM_Try, /*On fail goto*//*Label 7325*/ GIMT_Encode4(534932), // Rule ID 5676 //
        GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasPackedD16VMem),
        // MIs[0] offset
        GIM_CheckIsImm, /*MI*/0, /*Op*/5,
        // MIs[0] format
        GIM_CheckIsImm, /*MI*/0, /*Op*/6,
        // MIs[0] auxiliary
        GIM_CheckIsImm, /*MI*/0, /*Op*/7,
        // MIs[0] Operand 8
        GIM_CheckIsImm, /*MI*/0, /*Op*/8,
        GIM_CheckComplexPattern, /*MI*/0, /*Op*/4, /*Renderer*/GIMT_Encode2(0), GIMT_Encode2(GICP_gi_buf_soffset),
        // (SItbuffer_load_d16:{ *:[v2f16] } v4i32:{ *:[v4i32] }:$rsrc, i32:{ *:[i32] }:$vindex, i32:{ *:[i32] }:$voffset, (BUFSOffset:{ *:[i32] } i32:{ *:[i32] }:$soffset), (timm:{ *:[i32] }):$offset, (timm:{ *:[i32] }):$format, (timm:{ *:[i32] }):$auxiliary, (timm:{ *:[i1] }))  =>  (TBUFFER_LOAD_FORMAT_D16_XY_VBUFFER_BOTHEN:{ *:[v2f16] } (REG_SEQUENCE:{ *:[i64] } VReg_64:{ *:[i32] }, VGPR_32:{ *:[i32] }:$vindex, sub0:{ *:[i32] }, VGPR_32:{ *:[i32] }:$voffset, sub1:{ *:[i32] }), SReg_128:{ *:[v4i32] }:$rsrc, SCSrc_b32:{ *:[i32] }:$soffset, (timm:{ *:[i32] }):$offset, (as_i8timm:{ *:[i8] } ?:{ *:[i32] }:$format), (extract_cpol:{ *:[i32] } ?:{ *:[i32] }:$auxiliary), (extract_swz:{ *:[i1] } ?:{ *:[i32] }:$auxiliary))
        GIR_MakeTempReg, /*TempRegID*/0, /*TypeID*/GILLT_s64,
        GIR_BuildMI, /*InsnID*/1, /*Opcode*/GIMT_Encode2(TargetOpcode::REG_SEQUENCE),
        GIR_AddTempRegister, /*InsnID*/1, /*TempRegID*/0, /*TempRegFlags*/GIMT_Encode2(RegState::Define),
        GIR_Copy, /*NewInsnID*/1, /*OldInsnID*/0, /*OpIdx*/2, // vindex
        GIR_AddImm8, /*InsnID*/1, /*SubRegIndex*/3,
        GIR_Copy, /*NewInsnID*/1, /*OldInsnID*/0, /*OpIdx*/3, // voffset
        GIR_AddImm8, /*InsnID*/1, /*SubRegIndex*/11,
        GIR_ConstrainOperandRC, /*InsnID*/1, /*Op*/0, GIMT_Encode2(AMDGPU::VReg_64RegClassID),
        GIR_ConstrainOperandRC, /*InsnID*/1, /*Op*/1, GIMT_Encode2(AMDGPU::VGPR_32RegClassID),
        GIR_ConstrainOperandRC, /*InsnID*/1, /*Op*/3, GIMT_Encode2(AMDGPU::VGPR_32RegClassID),
        GIR_BuildMI, /*InsnID*/0, /*Opcode*/GIMT_Encode2(AMDGPU::TBUFFER_LOAD_FORMAT_D16_XY_VBUFFER_BOTHEN),
        GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/0, // DstI[vdata]
        GIR_AddSimpleTempRegister, /*InsnID*/0, /*TempRegID*/0,
        GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/1, // rsrc
        GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/0, // soffset
        GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/5, // offset
        GIR_CustomOperandRenderer, /*InsnID*/0, /*OldInsnID*/0, /*OpIdx*/6, /*OperandRenderer*/GIMT_Encode2(GICR_renderTruncTImm), // format
        GIR_CustomOperandRenderer, /*InsnID*/0, /*OldInsnID*/0, /*OpIdx*/7, /*OperandRenderer*/GIMT_Encode2(GICR_renderExtractCPol), // auxiliary
        GIR_CustomOperandRenderer, /*InsnID*/0, /*OldInsnID*/0, /*OpIdx*/7, /*OperandRenderer*/GIMT_Encode2(GICR_renderExtractSWZ), // auxiliary
        GIR_MergeMemOperands, /*InsnID*/0, /*NumInsns*/1, /*MergeInsnID's*/0,
        GIR_ConstrainSelectedInstOperands, /*InsnID*/0,
        GIR_EraseFromParent, /*InsnID*/0,
        // GIR_Coverage, 5676,
        GIR_Done,
      // Label 7325: @534932
      GIM_Reject,
    // Label 7317: @534933
    GIM_Reject,
    // Label 7286: @534934
    GIM_Try, /*On fail goto*//*Label 7326*/ GIMT_Encode4(535345),
      GIM_CheckType, /*MI*/0, /*Op*/1, /*Type*/GILLT_v4s32,
      GIM_CheckType, /*MI*/0, /*Op*/2, /*Type*/GILLT_s32,
      GIM_CheckType, /*MI*/0, /*Op*/3, /*Type*/GILLT_s32,
      GIM_CheckType, /*MI*/0, /*Op*/4, /*Type*/GILLT_s32,
      GIM_CheckRegBankForClass, /*MI*/0, /*Op*/0, /*RC*/GIMT_Encode2(AMDGPU::AV_64RegClassID),
      GIM_Try, /*On fail goto*//*Label 7327*/ GIMT_Encode4(535051), // Rule ID 5641 //
        GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasUnpackedD16VMem),
        GIM_CheckConstantInt8, /*MI*/0, /*Op*/2, 0,
        GIM_CheckConstantInt8, /*MI*/0, /*Op*/3, 0,
        // MIs[0] offset
        GIM_CheckIsImm, /*MI*/0, /*Op*/5,
        // MIs[0] format
        GIM_CheckIsImm, /*MI*/0, /*Op*/6,
        // MIs[0] auxiliary
        GIM_CheckIsImm, /*MI*/0, /*Op*/7,
        // MIs[0] Operand 8
        GIM_CheckLiteralInt, /*MI*/0, /*Op*/8, GIMT_Encode8(0),
        GIM_CheckComplexPattern, /*MI*/0, /*Op*/4, /*Renderer*/GIMT_Encode2(0), GIMT_Encode2(GICP_gi_buf_soffset),
        // (SItbuffer_load_d16:{ *:[v2i32] } v4i32:{ *:[v4i32] }:$rsrc, 0:{ *:[i32] }, 0:{ *:[i32] }, (BUFSOffset:{ *:[i32] } i32:{ *:[i32] }:$soffset), (timm:{ *:[i32] }):$offset, (timm:{ *:[i32] }):$format, (timm:{ *:[i32] }):$auxiliary, 0:{ *:[i1] })  =>  (TBUFFER_LOAD_FORMAT_D16_XY_gfx80_OFFSET:{ *:[v2i32] } SReg_128:{ *:[v4i32] }:$rsrc, SCSrc_b32:{ *:[i32] }:$soffset, (timm:{ *:[i32] }):$offset, (as_i8timm:{ *:[i8] } ?:{ *:[i32] }:$format), (extract_cpol:{ *:[i32] } ?:{ *:[i32] }:$auxiliary), (extract_swz:{ *:[i1] } ?:{ *:[i32] }:$auxiliary))
        GIR_BuildMI, /*InsnID*/0, /*Opcode*/GIMT_Encode2(AMDGPU::TBUFFER_LOAD_FORMAT_D16_XY_gfx80_OFFSET),
        GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/0, // DstI[vdata]
        GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/1, // rsrc
        GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/0, // soffset
        GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/5, // offset
        GIR_CustomOperandRenderer, /*InsnID*/0, /*OldInsnID*/0, /*OpIdx*/6, /*OperandRenderer*/GIMT_Encode2(GICR_renderTruncTImm), // format
        GIR_CustomOperandRenderer, /*InsnID*/0, /*OldInsnID*/0, /*OpIdx*/7, /*OperandRenderer*/GIMT_Encode2(GICR_renderExtractCPol), // auxiliary
        GIR_CustomOperandRenderer, /*InsnID*/0, /*OldInsnID*/0, /*OpIdx*/7, /*OperandRenderer*/GIMT_Encode2(GICR_renderExtractSWZ), // auxiliary
        GIR_MergeMemOperands, /*InsnID*/0, /*NumInsns*/1, /*MergeInsnID's*/0,
        GIR_ConstrainSelectedInstOperands, /*InsnID*/0,
        GIR_EraseFromParent, /*InsnID*/0,
        // GIR_Coverage, 5641,
        GIR_Done,
      // Label 7327: @535051
      GIM_Try, /*On fail goto*//*Label 7328*/ GIMT_Encode4(535142), // Rule ID 5643 //
        GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasUnpackedD16VMem),
        GIM_CheckConstantInt8, /*MI*/0, /*Op*/2, 0,
        // MIs[0] offset
        GIM_CheckIsImm, /*MI*/0, /*Op*/5,
        // MIs[0] format
        GIM_CheckIsImm, /*MI*/0, /*Op*/6,
        // MIs[0] auxiliary
        GIM_CheckIsImm, /*MI*/0, /*Op*/7,
        // MIs[0] Operand 8
        GIM_CheckLiteralInt, /*MI*/0, /*Op*/8, GIMT_Encode8(0),
        GIM_CheckComplexPattern, /*MI*/0, /*Op*/4, /*Renderer*/GIMT_Encode2(0), GIMT_Encode2(GICP_gi_buf_soffset),
        // (SItbuffer_load_d16:{ *:[v2i32] } v4i32:{ *:[v4i32] }:$rsrc, 0:{ *:[i32] }, i32:{ *:[i32] }:$voffset, (BUFSOffset:{ *:[i32] } i32:{ *:[i32] }:$soffset), (timm:{ *:[i32] }):$offset, (timm:{ *:[i32] }):$format, (timm:{ *:[i32] }):$auxiliary, 0:{ *:[i1] })  =>  (TBUFFER_LOAD_FORMAT_D16_XY_gfx80_OFFEN:{ *:[v2i32] } VGPR_32:{ *:[i32] }:$voffset, SReg_128:{ *:[v4i32] }:$rsrc, SCSrc_b32:{ *:[i32] }:$soffset, (timm:{ *:[i32] }):$offset, (as_i8timm:{ *:[i8] } ?:{ *:[i32] }:$format), (extract_cpol:{ *:[i32] } ?:{ *:[i32] }:$auxiliary), (extract_swz:{ *:[i1] } ?:{ *:[i32] }:$auxiliary))
        GIR_BuildMI, /*InsnID*/0, /*Opcode*/GIMT_Encode2(AMDGPU::TBUFFER_LOAD_FORMAT_D16_XY_gfx80_OFFEN),
        GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/0, // DstI[vdata]
        GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/3, // voffset
        GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/1, // rsrc
        GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/0, // soffset
        GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/5, // offset
        GIR_CustomOperandRenderer, /*InsnID*/0, /*OldInsnID*/0, /*OpIdx*/6, /*OperandRenderer*/GIMT_Encode2(GICR_renderTruncTImm), // format
        GIR_CustomOperandRenderer, /*InsnID*/0, /*OldInsnID*/0, /*OpIdx*/7, /*OperandRenderer*/GIMT_Encode2(GICR_renderExtractCPol), // auxiliary
        GIR_CustomOperandRenderer, /*InsnID*/0, /*OldInsnID*/0, /*OpIdx*/7, /*OperandRenderer*/GIMT_Encode2(GICR_renderExtractSWZ), // auxiliary
        GIR_MergeMemOperands, /*InsnID*/0, /*NumInsns*/1, /*MergeInsnID's*/0,
        GIR_ConstrainSelectedInstOperands, /*InsnID*/0,
        GIR_EraseFromParent, /*InsnID*/0,
        // GIR_Coverage, 5643,
        GIR_Done,
      // Label 7328: @535142
      GIM_Try, /*On fail goto*//*Label 7329*/ GIMT_Encode4(535225), // Rule ID 5642 //
        GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasUnpackedD16VMem),
        GIM_CheckConstantInt8, /*MI*/0, /*Op*/3, 0,
        // MIs[0] offset
        GIM_CheckIsImm, /*MI*/0, /*Op*/5,
        // MIs[0] format
        GIM_CheckIsImm, /*MI*/0, /*Op*/6,
        // MIs[0] auxiliary
        GIM_CheckIsImm, /*MI*/0, /*Op*/7,
        // MIs[0] Operand 8
        GIM_CheckIsImm, /*MI*/0, /*Op*/8,
        GIM_CheckComplexPattern, /*MI*/0, /*Op*/4, /*Renderer*/GIMT_Encode2(0), GIMT_Encode2(GICP_gi_buf_soffset),
        // (SItbuffer_load_d16:{ *:[v2i32] } v4i32:{ *:[v4i32] }:$rsrc, i32:{ *:[i32] }:$vindex, 0:{ *:[i32] }, (BUFSOffset:{ *:[i32] } i32:{ *:[i32] }:$soffset), (timm:{ *:[i32] }):$offset, (timm:{ *:[i32] }):$format, (timm:{ *:[i32] }):$auxiliary, (timm:{ *:[i1] }))  =>  (TBUFFER_LOAD_FORMAT_D16_XY_gfx80_IDXEN:{ *:[v2i32] } VGPR_32:{ *:[i32] }:$vindex, SReg_128:{ *:[v4i32] }:$rsrc, SCSrc_b32:{ *:[i32] }:$soffset, (timm:{ *:[i32] }):$offset, (as_i8timm:{ *:[i8] } ?:{ *:[i32] }:$format), (extract_cpol:{ *:[i32] } ?:{ *:[i32] }:$auxiliary), (extract_swz:{ *:[i1] } ?:{ *:[i32] }:$auxiliary))
        GIR_BuildMI, /*InsnID*/0, /*Opcode*/GIMT_Encode2(AMDGPU::TBUFFER_LOAD_FORMAT_D16_XY_gfx80_IDXEN),
        GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/0, // DstI[vdata]
        GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/2, // vindex
        GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/1, // rsrc
        GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/0, // soffset
        GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/5, // offset
        GIR_CustomOperandRenderer, /*InsnID*/0, /*OldInsnID*/0, /*OpIdx*/6, /*OperandRenderer*/GIMT_Encode2(GICR_renderTruncTImm), // format
        GIR_CustomOperandRenderer, /*InsnID*/0, /*OldInsnID*/0, /*OpIdx*/7, /*OperandRenderer*/GIMT_Encode2(GICR_renderExtractCPol), // auxiliary
        GIR_CustomOperandRenderer, /*InsnID*/0, /*OldInsnID*/0, /*OpIdx*/7, /*OperandRenderer*/GIMT_Encode2(GICR_renderExtractSWZ), // auxiliary
        GIR_MergeMemOperands, /*InsnID*/0, /*NumInsns*/1, /*MergeInsnID's*/0,
        GIR_ConstrainSelectedInstOperands, /*InsnID*/0,
        GIR_EraseFromParent, /*InsnID*/0,
        // GIR_Coverage, 5642,
        GIR_Done,
      // Label 7329: @535225
      GIM_Try, /*On fail goto*//*Label 7330*/ GIMT_Encode4(535344), // Rule ID 5644 //
        GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasUnpackedD16VMem),
        // MIs[0] offset
        GIM_CheckIsImm, /*MI*/0, /*Op*/5,
        // MIs[0] format
        GIM_CheckIsImm, /*MI*/0, /*Op*/6,
        // MIs[0] auxiliary
        GIM_CheckIsImm, /*MI*/0, /*Op*/7,
        // MIs[0] Operand 8
        GIM_CheckIsImm, /*MI*/0, /*Op*/8,
        GIM_CheckComplexPattern, /*MI*/0, /*Op*/4, /*Renderer*/GIMT_Encode2(0), GIMT_Encode2(GICP_gi_buf_soffset),
        // (SItbuffer_load_d16:{ *:[v2i32] } v4i32:{ *:[v4i32] }:$rsrc, i32:{ *:[i32] }:$vindex, i32:{ *:[i32] }:$voffset, (BUFSOffset:{ *:[i32] } i32:{ *:[i32] }:$soffset), (timm:{ *:[i32] }):$offset, (timm:{ *:[i32] }):$format, (timm:{ *:[i32] }):$auxiliary, (timm:{ *:[i1] }))  =>  (TBUFFER_LOAD_FORMAT_D16_XY_gfx80_BOTHEN:{ *:[v2i32] } (REG_SEQUENCE:{ *:[i64] } VReg_64:{ *:[i32] }, VGPR_32:{ *:[i32] }:$vindex, sub0:{ *:[i32] }, VGPR_32:{ *:[i32] }:$voffset, sub1:{ *:[i32] }), SReg_128:{ *:[v4i32] }:$rsrc, SCSrc_b32:{ *:[i32] }:$soffset, (timm:{ *:[i32] }):$offset, (as_i8timm:{ *:[i8] } ?:{ *:[i32] }:$format), (extract_cpol:{ *:[i32] } ?:{ *:[i32] }:$auxiliary), (extract_swz:{ *:[i1] } ?:{ *:[i32] }:$auxiliary))
        GIR_MakeTempReg, /*TempRegID*/0, /*TypeID*/GILLT_s64,
        GIR_BuildMI, /*InsnID*/1, /*Opcode*/GIMT_Encode2(TargetOpcode::REG_SEQUENCE),
        GIR_AddTempRegister, /*InsnID*/1, /*TempRegID*/0, /*TempRegFlags*/GIMT_Encode2(RegState::Define),
        GIR_Copy, /*NewInsnID*/1, /*OldInsnID*/0, /*OpIdx*/2, // vindex
        GIR_AddImm8, /*InsnID*/1, /*SubRegIndex*/3,
        GIR_Copy, /*NewInsnID*/1, /*OldInsnID*/0, /*OpIdx*/3, // voffset
        GIR_AddImm8, /*InsnID*/1, /*SubRegIndex*/11,
        GIR_ConstrainOperandRC, /*InsnID*/1, /*Op*/0, GIMT_Encode2(AMDGPU::VReg_64RegClassID),
        GIR_ConstrainOperandRC, /*InsnID*/1, /*Op*/1, GIMT_Encode2(AMDGPU::VGPR_32RegClassID),
        GIR_ConstrainOperandRC, /*InsnID*/1, /*Op*/3, GIMT_Encode2(AMDGPU::VGPR_32RegClassID),
        GIR_BuildMI, /*InsnID*/0, /*Opcode*/GIMT_Encode2(AMDGPU::TBUFFER_LOAD_FORMAT_D16_XY_gfx80_BOTHEN),
        GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/0, // DstI[vdata]
        GIR_AddSimpleTempRegister, /*InsnID*/0, /*TempRegID*/0,
        GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/1, // rsrc
        GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/0, // soffset
        GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/5, // offset
        GIR_CustomOperandRenderer, /*InsnID*/0, /*OldInsnID*/0, /*OpIdx*/6, /*OperandRenderer*/GIMT_Encode2(GICR_renderTruncTImm), // format
        GIR_CustomOperandRenderer, /*InsnID*/0, /*OldInsnID*/0, /*OpIdx*/7, /*OperandRenderer*/GIMT_Encode2(GICR_renderExtractCPol), // auxiliary
        GIR_CustomOperandRenderer, /*InsnID*/0, /*OldInsnID*/0, /*OpIdx*/7, /*OperandRenderer*/GIMT_Encode2(GICR_renderExtractSWZ), // auxiliary
        GIR_MergeMemOperands, /*InsnID*/0, /*NumInsns*/1, /*MergeInsnID's*/0,
        GIR_ConstrainSelectedInstOperands, /*InsnID*/0,
        GIR_EraseFromParent, /*InsnID*/0,
        // GIR_Coverage, 5644,
        GIR_Done,
      // Label 7330: @535344
      GIM_Reject,
    // Label 7326: @535345
    GIM_Reject,
    // Label 7287: @535346
    GIM_Try, /*On fail goto*//*Label 7331*/ GIMT_Encode4(535757),
      GIM_CheckType, /*MI*/0, /*Op*/1, /*Type*/GILLT_v4s32,
      GIM_CheckType, /*MI*/0, /*Op*/2, /*Type*/GILLT_s32,
      GIM_CheckType, /*MI*/0, /*Op*/3, /*Type*/GILLT_s32,
      GIM_CheckType, /*MI*/0, /*Op*/4, /*Type*/GILLT_s32,
      GIM_CheckRegBankForClass, /*MI*/0, /*Op*/0, /*RC*/GIMT_Encode2(AMDGPU::AV_96RegClassID),
      GIM_Try, /*On fail goto*//*Label 7332*/ GIMT_Encode4(535463), // Rule ID 5645 //
        GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasUnpackedD16VMem),
        GIM_CheckConstantInt8, /*MI*/0, /*Op*/2, 0,
        GIM_CheckConstantInt8, /*MI*/0, /*Op*/3, 0,
        // MIs[0] offset
        GIM_CheckIsImm, /*MI*/0, /*Op*/5,
        // MIs[0] format
        GIM_CheckIsImm, /*MI*/0, /*Op*/6,
        // MIs[0] auxiliary
        GIM_CheckIsImm, /*MI*/0, /*Op*/7,
        // MIs[0] Operand 8
        GIM_CheckLiteralInt, /*MI*/0, /*Op*/8, GIMT_Encode8(0),
        GIM_CheckComplexPattern, /*MI*/0, /*Op*/4, /*Renderer*/GIMT_Encode2(0), GIMT_Encode2(GICP_gi_buf_soffset),
        // (SItbuffer_load_d16:{ *:[v3i32] } v4i32:{ *:[v4i32] }:$rsrc, 0:{ *:[i32] }, 0:{ *:[i32] }, (BUFSOffset:{ *:[i32] } i32:{ *:[i32] }:$soffset), (timm:{ *:[i32] }):$offset, (timm:{ *:[i32] }):$format, (timm:{ *:[i32] }):$auxiliary, 0:{ *:[i1] })  =>  (TBUFFER_LOAD_FORMAT_D16_XYZ_gfx80_OFFSET:{ *:[v3i32] } SReg_128:{ *:[v4i32] }:$rsrc, SCSrc_b32:{ *:[i32] }:$soffset, (timm:{ *:[i32] }):$offset, (as_i8timm:{ *:[i8] } ?:{ *:[i32] }:$format), (extract_cpol:{ *:[i32] } ?:{ *:[i32] }:$auxiliary), (extract_swz:{ *:[i1] } ?:{ *:[i32] }:$auxiliary))
        GIR_BuildMI, /*InsnID*/0, /*Opcode*/GIMT_Encode2(AMDGPU::TBUFFER_LOAD_FORMAT_D16_XYZ_gfx80_OFFSET),
        GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/0, // DstI[vdata]
        GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/1, // rsrc
        GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/0, // soffset
        GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/5, // offset
        GIR_CustomOperandRenderer, /*InsnID*/0, /*OldInsnID*/0, /*OpIdx*/6, /*OperandRenderer*/GIMT_Encode2(GICR_renderTruncTImm), // format
        GIR_CustomOperandRenderer, /*InsnID*/0, /*OldInsnID*/0, /*OpIdx*/7, /*OperandRenderer*/GIMT_Encode2(GICR_renderExtractCPol), // auxiliary
        GIR_CustomOperandRenderer, /*InsnID*/0, /*OldInsnID*/0, /*OpIdx*/7, /*OperandRenderer*/GIMT_Encode2(GICR_renderExtractSWZ), // auxiliary
        GIR_MergeMemOperands, /*InsnID*/0, /*NumInsns*/1, /*MergeInsnID's*/0,
        GIR_ConstrainSelectedInstOperands, /*InsnID*/0,
        GIR_EraseFromParent, /*InsnID*/0,
        // GIR_Coverage, 5645,
        GIR_Done,
      // Label 7332: @535463
      GIM_Try, /*On fail goto*//*Label 7333*/ GIMT_Encode4(535554), // Rule ID 5647 //
        GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasUnpackedD16VMem),
        GIM_CheckConstantInt8, /*MI*/0, /*Op*/2, 0,
        // MIs[0] offset
        GIM_CheckIsImm, /*MI*/0, /*Op*/5,
        // MIs[0] format
        GIM_CheckIsImm, /*MI*/0, /*Op*/6,
        // MIs[0] auxiliary
        GIM_CheckIsImm, /*MI*/0, /*Op*/7,
        // MIs[0] Operand 8
        GIM_CheckLiteralInt, /*MI*/0, /*Op*/8, GIMT_Encode8(0),
        GIM_CheckComplexPattern, /*MI*/0, /*Op*/4, /*Renderer*/GIMT_Encode2(0), GIMT_Encode2(GICP_gi_buf_soffset),
        // (SItbuffer_load_d16:{ *:[v3i32] } v4i32:{ *:[v4i32] }:$rsrc, 0:{ *:[i32] }, i32:{ *:[i32] }:$voffset, (BUFSOffset:{ *:[i32] } i32:{ *:[i32] }:$soffset), (timm:{ *:[i32] }):$offset, (timm:{ *:[i32] }):$format, (timm:{ *:[i32] }):$auxiliary, 0:{ *:[i1] })  =>  (TBUFFER_LOAD_FORMAT_D16_XYZ_gfx80_OFFEN:{ *:[v3i32] } VGPR_32:{ *:[i32] }:$voffset, SReg_128:{ *:[v4i32] }:$rsrc, SCSrc_b32:{ *:[i32] }:$soffset, (timm:{ *:[i32] }):$offset, (as_i8timm:{ *:[i8] } ?:{ *:[i32] }:$format), (extract_cpol:{ *:[i32] } ?:{ *:[i32] }:$auxiliary), (extract_swz:{ *:[i1] } ?:{ *:[i32] }:$auxiliary))
        GIR_BuildMI, /*InsnID*/0, /*Opcode*/GIMT_Encode2(AMDGPU::TBUFFER_LOAD_FORMAT_D16_XYZ_gfx80_OFFEN),
        GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/0, // DstI[vdata]
        GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/3, // voffset
        GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/1, // rsrc
        GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/0, // soffset
        GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/5, // offset
        GIR_CustomOperandRenderer, /*InsnID*/0, /*OldInsnID*/0, /*OpIdx*/6, /*OperandRenderer*/GIMT_Encode2(GICR_renderTruncTImm), // format
        GIR_CustomOperandRenderer, /*InsnID*/0, /*OldInsnID*/0, /*OpIdx*/7, /*OperandRenderer*/GIMT_Encode2(GICR_renderExtractCPol), // auxiliary
        GIR_CustomOperandRenderer, /*InsnID*/0, /*OldInsnID*/0, /*OpIdx*/7, /*OperandRenderer*/GIMT_Encode2(GICR_renderExtractSWZ), // auxiliary
        GIR_MergeMemOperands, /*InsnID*/0, /*NumInsns*/1, /*MergeInsnID's*/0,
        GIR_ConstrainSelectedInstOperands, /*InsnID*/0,
        GIR_EraseFromParent, /*InsnID*/0,
        // GIR_Coverage, 5647,
        GIR_Done,
      // Label 7333: @535554
      GIM_Try, /*On fail goto*//*Label 7334*/ GIMT_Encode4(535637), // Rule ID 5646 //
        GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasUnpackedD16VMem),
        GIM_CheckConstantInt8, /*MI*/0, /*Op*/3, 0,
        // MIs[0] offset
        GIM_CheckIsImm, /*MI*/0, /*Op*/5,
        // MIs[0] format
        GIM_CheckIsImm, /*MI*/0, /*Op*/6,
        // MIs[0] auxiliary
        GIM_CheckIsImm, /*MI*/0, /*Op*/7,
        // MIs[0] Operand 8
        GIM_CheckIsImm, /*MI*/0, /*Op*/8,
        GIM_CheckComplexPattern, /*MI*/0, /*Op*/4, /*Renderer*/GIMT_Encode2(0), GIMT_Encode2(GICP_gi_buf_soffset),
        // (SItbuffer_load_d16:{ *:[v3i32] } v4i32:{ *:[v4i32] }:$rsrc, i32:{ *:[i32] }:$vindex, 0:{ *:[i32] }, (BUFSOffset:{ *:[i32] } i32:{ *:[i32] }:$soffset), (timm:{ *:[i32] }):$offset, (timm:{ *:[i32] }):$format, (timm:{ *:[i32] }):$auxiliary, (timm:{ *:[i1] }))  =>  (TBUFFER_LOAD_FORMAT_D16_XYZ_gfx80_IDXEN:{ *:[v3i32] } VGPR_32:{ *:[i32] }:$vindex, SReg_128:{ *:[v4i32] }:$rsrc, SCSrc_b32:{ *:[i32] }:$soffset, (timm:{ *:[i32] }):$offset, (as_i8timm:{ *:[i8] } ?:{ *:[i32] }:$format), (extract_cpol:{ *:[i32] } ?:{ *:[i32] }:$auxiliary), (extract_swz:{ *:[i1] } ?:{ *:[i32] }:$auxiliary))
        GIR_BuildMI, /*InsnID*/0, /*Opcode*/GIMT_Encode2(AMDGPU::TBUFFER_LOAD_FORMAT_D16_XYZ_gfx80_IDXEN),
        GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/0, // DstI[vdata]
        GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/2, // vindex
        GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/1, // rsrc
        GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/0, // soffset
        GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/5, // offset
        GIR_CustomOperandRenderer, /*InsnID*/0, /*OldInsnID*/0, /*OpIdx*/6, /*OperandRenderer*/GIMT_Encode2(GICR_renderTruncTImm), // format
        GIR_CustomOperandRenderer, /*InsnID*/0, /*OldInsnID*/0, /*OpIdx*/7, /*OperandRenderer*/GIMT_Encode2(GICR_renderExtractCPol), // auxiliary
        GIR_CustomOperandRenderer, /*InsnID*/0, /*OldInsnID*/0, /*OpIdx*/7, /*OperandRenderer*/GIMT_Encode2(GICR_renderExtractSWZ), // auxiliary
        GIR_MergeMemOperands, /*InsnID*/0, /*NumInsns*/1, /*MergeInsnID's*/0,
        GIR_ConstrainSelectedInstOperands, /*InsnID*/0,
        GIR_EraseFromParent, /*InsnID*/0,
        // GIR_Coverage, 5646,
        GIR_Done,
      // Label 7334: @535637
      GIM_Try, /*On fail goto*//*Label 7335*/ GIMT_Encode4(535756), // Rule ID 5648 //
        GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasUnpackedD16VMem),
        // MIs[0] offset
        GIM_CheckIsImm, /*MI*/0, /*Op*/5,
        // MIs[0] format
        GIM_CheckIsImm, /*MI*/0, /*Op*/6,
        // MIs[0] auxiliary
        GIM_CheckIsImm, /*MI*/0, /*Op*/7,
        // MIs[0] Operand 8
        GIM_CheckIsImm, /*MI*/0, /*Op*/8,
        GIM_CheckComplexPattern, /*MI*/0, /*Op*/4, /*Renderer*/GIMT_Encode2(0), GIMT_Encode2(GICP_gi_buf_soffset),
        // (SItbuffer_load_d16:{ *:[v3i32] } v4i32:{ *:[v4i32] }:$rsrc, i32:{ *:[i32] }:$vindex, i32:{ *:[i32] }:$voffset, (BUFSOffset:{ *:[i32] } i32:{ *:[i32] }:$soffset), (timm:{ *:[i32] }):$offset, (timm:{ *:[i32] }):$format, (timm:{ *:[i32] }):$auxiliary, (timm:{ *:[i1] }))  =>  (TBUFFER_LOAD_FORMAT_D16_XYZ_gfx80_BOTHEN:{ *:[v3i32] } (REG_SEQUENCE:{ *:[i64] } VReg_64:{ *:[i32] }, VGPR_32:{ *:[i32] }:$vindex, sub0:{ *:[i32] }, VGPR_32:{ *:[i32] }:$voffset, sub1:{ *:[i32] }), SReg_128:{ *:[v4i32] }:$rsrc, SCSrc_b32:{ *:[i32] }:$soffset, (timm:{ *:[i32] }):$offset, (as_i8timm:{ *:[i8] } ?:{ *:[i32] }:$format), (extract_cpol:{ *:[i32] } ?:{ *:[i32] }:$auxiliary), (extract_swz:{ *:[i1] } ?:{ *:[i32] }:$auxiliary))
        GIR_MakeTempReg, /*TempRegID*/0, /*TypeID*/GILLT_s64,
        GIR_BuildMI, /*InsnID*/1, /*Opcode*/GIMT_Encode2(TargetOpcode::REG_SEQUENCE),
        GIR_AddTempRegister, /*InsnID*/1, /*TempRegID*/0, /*TempRegFlags*/GIMT_Encode2(RegState::Define),
        GIR_Copy, /*NewInsnID*/1, /*OldInsnID*/0, /*OpIdx*/2, // vindex
        GIR_AddImm8, /*InsnID*/1, /*SubRegIndex*/3,
        GIR_Copy, /*NewInsnID*/1, /*OldInsnID*/0, /*OpIdx*/3, // voffset
        GIR_AddImm8, /*InsnID*/1, /*SubRegIndex*/11,
        GIR_ConstrainOperandRC, /*InsnID*/1, /*Op*/0, GIMT_Encode2(AMDGPU::VReg_64RegClassID),
        GIR_ConstrainOperandRC, /*InsnID*/1, /*Op*/1, GIMT_Encode2(AMDGPU::VGPR_32RegClassID),
        GIR_ConstrainOperandRC, /*InsnID*/1, /*Op*/3, GIMT_Encode2(AMDGPU::VGPR_32RegClassID),
        GIR_BuildMI, /*InsnID*/0, /*Opcode*/GIMT_Encode2(AMDGPU::TBUFFER_LOAD_FORMAT_D16_XYZ_gfx80_BOTHEN),
        GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/0, // DstI[vdata]
        GIR_AddSimpleTempRegister, /*InsnID*/0, /*TempRegID*/0,
        GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/1, // rsrc
        GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/0, // soffset
        GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/5, // offset
        GIR_CustomOperandRenderer, /*InsnID*/0, /*OldInsnID*/0, /*OpIdx*/6, /*OperandRenderer*/GIMT_Encode2(GICR_renderTruncTImm), // format
        GIR_CustomOperandRenderer, /*InsnID*/0, /*OldInsnID*/0, /*OpIdx*/7, /*OperandRenderer*/GIMT_Encode2(GICR_renderExtractCPol), // auxiliary
        GIR_CustomOperandRenderer, /*InsnID*/0, /*OldInsnID*/0, /*OpIdx*/7, /*OperandRenderer*/GIMT_Encode2(GICR_renderExtractSWZ), // auxiliary
        GIR_MergeMemOperands, /*InsnID*/0, /*NumInsns*/1, /*MergeInsnID's*/0,
        GIR_ConstrainSelectedInstOperands, /*InsnID*/0,
        GIR_EraseFromParent, /*InsnID*/0,
        // GIR_Coverage, 5648,
        GIR_Done,
      // Label 7335: @535756
      GIM_Reject,
    // Label 7331: @535757
    GIM_Reject,
    // Label 7288: @535758
    GIM_Try, /*On fail goto*//*Label 7336*/ GIMT_Encode4(537452),
      GIM_CheckType, /*MI*/0, /*Op*/1, /*Type*/GILLT_v4s32,
      GIM_CheckType, /*MI*/0, /*Op*/2, /*Type*/GILLT_s32,
      GIM_CheckType, /*MI*/0, /*Op*/3, /*Type*/GILLT_s32,
      GIM_CheckType, /*MI*/0, /*Op*/4, /*Type*/GILLT_s32,
      GIM_Try, /*On fail goto*//*Label 7337*/ GIMT_Encode4(535882), // Rule ID 5677 //
        GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasPackedD16VMem_HasUnrestrictedSOffset),
        GIM_CheckMemorySizeEqualTo, /*MI*/0, /*MMO*/0, /*Size*/GIMT_Encode4(6),
        GIM_CheckRegBankForClass, /*MI*/0, /*Op*/0, /*RC*/GIMT_Encode2(AMDGPU::AV_64RegClassID),
        GIM_CheckConstantInt8, /*MI*/0, /*Op*/2, 0,
        GIM_CheckConstantInt8, /*MI*/0, /*Op*/3, 0,
        // MIs[0] offset
        GIM_CheckIsImm, /*MI*/0, /*Op*/5,
        // MIs[0] format
        GIM_CheckIsImm, /*MI*/0, /*Op*/6,
        // MIs[0] auxiliary
        GIM_CheckIsImm, /*MI*/0, /*Op*/7,
        // MIs[0] Operand 8
        GIM_CheckLiteralInt, /*MI*/0, /*Op*/8, GIMT_Encode8(0),
        GIM_CheckComplexPattern, /*MI*/0, /*Op*/4, /*Renderer*/GIMT_Encode2(0), GIMT_Encode2(GICP_gi_buf_soffset),
        // (SItbuffer_load_d16:{ *:[v4f16] } v4i32:{ *:[v4i32] }:$rsrc, 0:{ *:[i32] }, 0:{ *:[i32] }, (BUFSOffset:{ *:[i32] } i32:{ *:[i32] }:$soffset), (timm:{ *:[i32] }):$offset, (timm:{ *:[i32] }):$format, (timm:{ *:[i32] }):$auxiliary, 0:{ *:[i1] })<<P:Predicate_anonymous_34123>>  =>  (TBUFFER_LOAD_FORMAT_D16_XYZ_OFFSET:{ *:[v4f16] } SReg_128:{ *:[v4i32] }:$rsrc, SCSrc_b32:{ *:[i32] }:$soffset, (timm:{ *:[i32] }):$offset, (as_i8timm:{ *:[i8] } ?:{ *:[i32] }:$format), (extract_cpol:{ *:[i32] } ?:{ *:[i32] }:$auxiliary), (extract_swz:{ *:[i1] } ?:{ *:[i32] }:$auxiliary))
        GIR_BuildMI, /*InsnID*/0, /*Opcode*/GIMT_Encode2(AMDGPU::TBUFFER_LOAD_FORMAT_D16_XYZ_OFFSET),
        GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/0, // DstI[vdata]
        GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/1, // rsrc
        GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/0, // soffset
        GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/5, // offset
        GIR_CustomOperandRenderer, /*InsnID*/0, /*OldInsnID*/0, /*OpIdx*/6, /*OperandRenderer*/GIMT_Encode2(GICR_renderTruncTImm), // format
        GIR_CustomOperandRenderer, /*InsnID*/0, /*OldInsnID*/0, /*OpIdx*/7, /*OperandRenderer*/GIMT_Encode2(GICR_renderExtractCPol), // auxiliary
        GIR_CustomOperandRenderer, /*InsnID*/0, /*OldInsnID*/0, /*OpIdx*/7, /*OperandRenderer*/GIMT_Encode2(GICR_renderExtractSWZ), // auxiliary
        GIR_MergeMemOperands, /*InsnID*/0, /*NumInsns*/1, /*MergeInsnID's*/0,
        GIR_ConstrainSelectedInstOperands, /*InsnID*/0,
        GIR_EraseFromParent, /*InsnID*/0,
        // GIR_Coverage, 5677,
        GIR_Done,
      // Label 7337: @535882
      GIM_Try, /*On fail goto*//*Label 7338*/ GIMT_Encode4(535985), // Rule ID 5681 //
        GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasPackedD16VMem),
        GIM_CheckMemorySizeEqualTo, /*MI*/0, /*MMO*/0, /*Size*/GIMT_Encode4(6),
        GIM_CheckRegBankForClass, /*MI*/0, /*Op*/0, /*RC*/GIMT_Encode2(AMDGPU::AV_64RegClassID),
        GIM_CheckConstantInt8, /*MI*/0, /*Op*/2, 0,
        GIM_CheckConstantInt8, /*MI*/0, /*Op*/3, 0,
        // MIs[0] offset
        GIM_CheckIsImm, /*MI*/0, /*Op*/5,
        // MIs[0] format
        GIM_CheckIsImm, /*MI*/0, /*Op*/6,
        // MIs[0] auxiliary
        GIM_CheckIsImm, /*MI*/0, /*Op*/7,
        // MIs[0] Operand 8
        GIM_CheckLiteralInt, /*MI*/0, /*Op*/8, GIMT_Encode8(0),
        GIM_CheckComplexPattern, /*MI*/0, /*Op*/4, /*Renderer*/GIMT_Encode2(0), GIMT_Encode2(GICP_gi_buf_soffset),
        // (SItbuffer_load_d16:{ *:[v4f16] } v4i32:{ *:[v4i32] }:$rsrc, 0:{ *:[i32] }, 0:{ *:[i32] }, (BUFSOffset:{ *:[i32] } i32:{ *:[i32] }:$soffset), (timm:{ *:[i32] }):$offset, (timm:{ *:[i32] }):$format, (timm:{ *:[i32] }):$auxiliary, 0:{ *:[i1] })<<P:Predicate_anonymous_34123>>  =>  (TBUFFER_LOAD_FORMAT_D16_XYZ_VBUFFER_OFFSET:{ *:[v4f16] } SReg_128:{ *:[v4i32] }:$rsrc, SCSrc_b32:{ *:[i32] }:$soffset, (timm:{ *:[i32] }):$offset, (as_i8timm:{ *:[i8] } ?:{ *:[i32] }:$format), (extract_cpol:{ *:[i32] } ?:{ *:[i32] }:$auxiliary), (extract_swz:{ *:[i1] } ?:{ *:[i32] }:$auxiliary))
        GIR_BuildMI, /*InsnID*/0, /*Opcode*/GIMT_Encode2(AMDGPU::TBUFFER_LOAD_FORMAT_D16_XYZ_VBUFFER_OFFSET),
        GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/0, // DstI[vdata]
        GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/1, // rsrc
        GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/0, // soffset
        GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/5, // offset
        GIR_CustomOperandRenderer, /*InsnID*/0, /*OldInsnID*/0, /*OpIdx*/6, /*OperandRenderer*/GIMT_Encode2(GICR_renderTruncTImm), // format
        GIR_CustomOperandRenderer, /*InsnID*/0, /*OldInsnID*/0, /*OpIdx*/7, /*OperandRenderer*/GIMT_Encode2(GICR_renderExtractCPol), // auxiliary
        GIR_CustomOperandRenderer, /*InsnID*/0, /*OldInsnID*/0, /*OpIdx*/7, /*OperandRenderer*/GIMT_Encode2(GICR_renderExtractSWZ), // auxiliary
        GIR_MergeMemOperands, /*InsnID*/0, /*NumInsns*/1, /*MergeInsnID's*/0,
        GIR_ConstrainSelectedInstOperands, /*InsnID*/0,
        GIR_EraseFromParent, /*InsnID*/0,
        // GIR_Coverage, 5681,
        GIR_Done,
      // Label 7338: @535985
      GIM_Try, /*On fail goto*//*Label 7339*/ GIMT_Encode4(536081), // Rule ID 5685 //
        GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasPackedD16VMem_HasUnrestrictedSOffset),
        GIM_CheckRegBankForClass, /*MI*/0, /*Op*/0, /*RC*/GIMT_Encode2(AMDGPU::AV_64RegClassID),
        GIM_CheckConstantInt8, /*MI*/0, /*Op*/2, 0,
        GIM_CheckConstantInt8, /*MI*/0, /*Op*/3, 0,
        // MIs[0] offset
        GIM_CheckIsImm, /*MI*/0, /*Op*/5,
        // MIs[0] format
        GIM_CheckIsImm, /*MI*/0, /*Op*/6,
        // MIs[0] auxiliary
        GIM_CheckIsImm, /*MI*/0, /*Op*/7,
        // MIs[0] Operand 8
        GIM_CheckLiteralInt, /*MI*/0, /*Op*/8, GIMT_Encode8(0),
        GIM_CheckComplexPattern, /*MI*/0, /*Op*/4, /*Renderer*/GIMT_Encode2(0), GIMT_Encode2(GICP_gi_buf_soffset),
        // (SItbuffer_load_d16:{ *:[v4f16] } v4i32:{ *:[v4i32] }:$rsrc, 0:{ *:[i32] }, 0:{ *:[i32] }, (BUFSOffset:{ *:[i32] } i32:{ *:[i32] }:$soffset), (timm:{ *:[i32] }):$offset, (timm:{ *:[i32] }):$format, (timm:{ *:[i32] }):$auxiliary, 0:{ *:[i1] })  =>  (TBUFFER_LOAD_FORMAT_D16_XYZW_OFFSET:{ *:[v4f16] } SReg_128:{ *:[v4i32] }:$rsrc, SCSrc_b32:{ *:[i32] }:$soffset, (timm:{ *:[i32] }):$offset, (as_i8timm:{ *:[i8] } ?:{ *:[i32] }:$format), (extract_cpol:{ *:[i32] } ?:{ *:[i32] }:$auxiliary), (extract_swz:{ *:[i1] } ?:{ *:[i32] }:$auxiliary))
        GIR_BuildMI, /*InsnID*/0, /*Opcode*/GIMT_Encode2(AMDGPU::TBUFFER_LOAD_FORMAT_D16_XYZW_OFFSET),
        GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/0, // DstI[vdata]
        GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/1, // rsrc
        GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/0, // soffset
        GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/5, // offset
        GIR_CustomOperandRenderer, /*InsnID*/0, /*OldInsnID*/0, /*OpIdx*/6, /*OperandRenderer*/GIMT_Encode2(GICR_renderTruncTImm), // format
        GIR_CustomOperandRenderer, /*InsnID*/0, /*OldInsnID*/0, /*OpIdx*/7, /*OperandRenderer*/GIMT_Encode2(GICR_renderExtractCPol), // auxiliary
        GIR_CustomOperandRenderer, /*InsnID*/0, /*OldInsnID*/0, /*OpIdx*/7, /*OperandRenderer*/GIMT_Encode2(GICR_renderExtractSWZ), // auxiliary
        GIR_MergeMemOperands, /*InsnID*/0, /*NumInsns*/1, /*MergeInsnID's*/0,
        GIR_ConstrainSelectedInstOperands, /*InsnID*/0,
        GIR_EraseFromParent, /*InsnID*/0,
        // GIR_Coverage, 5685,
        GIR_Done,
      // Label 7339: @536081
      GIM_Try, /*On fail goto*//*Label 7340*/ GIMT_Encode4(536177), // Rule ID 5689 //
        GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasPackedD16VMem),
        GIM_CheckRegBankForClass, /*MI*/0, /*Op*/0, /*RC*/GIMT_Encode2(AMDGPU::AV_64RegClassID),
        GIM_CheckConstantInt8, /*MI*/0, /*Op*/2, 0,
        GIM_CheckConstantInt8, /*MI*/0, /*Op*/3, 0,
        // MIs[0] offset
        GIM_CheckIsImm, /*MI*/0, /*Op*/5,
        // MIs[0] format
        GIM_CheckIsImm, /*MI*/0, /*Op*/6,
        // MIs[0] auxiliary
        GIM_CheckIsImm, /*MI*/0, /*Op*/7,
        // MIs[0] Operand 8
        GIM_CheckLiteralInt, /*MI*/0, /*Op*/8, GIMT_Encode8(0),
        GIM_CheckComplexPattern, /*MI*/0, /*Op*/4, /*Renderer*/GIMT_Encode2(0), GIMT_Encode2(GICP_gi_buf_soffset),
        // (SItbuffer_load_d16:{ *:[v4f16] } v4i32:{ *:[v4i32] }:$rsrc, 0:{ *:[i32] }, 0:{ *:[i32] }, (BUFSOffset:{ *:[i32] } i32:{ *:[i32] }:$soffset), (timm:{ *:[i32] }):$offset, (timm:{ *:[i32] }):$format, (timm:{ *:[i32] }):$auxiliary, 0:{ *:[i1] })  =>  (TBUFFER_LOAD_FORMAT_D16_XYZW_VBUFFER_OFFSET:{ *:[v4f16] } SReg_128:{ *:[v4i32] }:$rsrc, SCSrc_b32:{ *:[i32] }:$soffset, (timm:{ *:[i32] }):$offset, (as_i8timm:{ *:[i8] } ?:{ *:[i32] }:$format), (extract_cpol:{ *:[i32] } ?:{ *:[i32] }:$auxiliary), (extract_swz:{ *:[i1] } ?:{ *:[i32] }:$auxiliary))
        GIR_BuildMI, /*InsnID*/0, /*Opcode*/GIMT_Encode2(AMDGPU::TBUFFER_LOAD_FORMAT_D16_XYZW_VBUFFER_OFFSET),
        GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/0, // DstI[vdata]
        GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/1, // rsrc
        GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/0, // soffset
        GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/5, // offset
        GIR_CustomOperandRenderer, /*InsnID*/0, /*OldInsnID*/0, /*OpIdx*/6, /*OperandRenderer*/GIMT_Encode2(GICR_renderTruncTImm), // format
        GIR_CustomOperandRenderer, /*InsnID*/0, /*OldInsnID*/0, /*OpIdx*/7, /*OperandRenderer*/GIMT_Encode2(GICR_renderExtractCPol), // auxiliary
        GIR_CustomOperandRenderer, /*InsnID*/0, /*OldInsnID*/0, /*OpIdx*/7, /*OperandRenderer*/GIMT_Encode2(GICR_renderExtractSWZ), // auxiliary
        GIR_MergeMemOperands, /*InsnID*/0, /*NumInsns*/1, /*MergeInsnID's*/0,
        GIR_ConstrainSelectedInstOperands, /*InsnID*/0,
        GIR_EraseFromParent, /*InsnID*/0,
        // GIR_Coverage, 5689,
        GIR_Done,
      // Label 7340: @536177
      GIM_Try, /*On fail goto*//*Label 7341*/ GIMT_Encode4(536280), // Rule ID 5679 //
        GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasPackedD16VMem_HasUnrestrictedSOffset),
        GIM_CheckMemorySizeEqualTo, /*MI*/0, /*MMO*/0, /*Size*/GIMT_Encode4(6),
        GIM_CheckRegBankForClass, /*MI*/0, /*Op*/0, /*RC*/GIMT_Encode2(AMDGPU::AV_64RegClassID),
        GIM_CheckConstantInt8, /*MI*/0, /*Op*/2, 0,
        // MIs[0] offset
        GIM_CheckIsImm, /*MI*/0, /*Op*/5,
        // MIs[0] format
        GIM_CheckIsImm, /*MI*/0, /*Op*/6,
        // MIs[0] auxiliary
        GIM_CheckIsImm, /*MI*/0, /*Op*/7,
        // MIs[0] Operand 8
        GIM_CheckLiteralInt, /*MI*/0, /*Op*/8, GIMT_Encode8(0),
        GIM_CheckComplexPattern, /*MI*/0, /*Op*/4, /*Renderer*/GIMT_Encode2(0), GIMT_Encode2(GICP_gi_buf_soffset),
        // (SItbuffer_load_d16:{ *:[v4f16] } v4i32:{ *:[v4i32] }:$rsrc, 0:{ *:[i32] }, i32:{ *:[i32] }:$voffset, (BUFSOffset:{ *:[i32] } i32:{ *:[i32] }:$soffset), (timm:{ *:[i32] }):$offset, (timm:{ *:[i32] }):$format, (timm:{ *:[i32] }):$auxiliary, 0:{ *:[i1] })<<P:Predicate_anonymous_34123>>  =>  (TBUFFER_LOAD_FORMAT_D16_XYZ_OFFEN:{ *:[v4f16] } VGPR_32:{ *:[i32] }:$voffset, SReg_128:{ *:[v4i32] }:$rsrc, SCSrc_b32:{ *:[i32] }:$soffset, (timm:{ *:[i32] }):$offset, (as_i8timm:{ *:[i8] } ?:{ *:[i32] }:$format), (extract_cpol:{ *:[i32] } ?:{ *:[i32] }:$auxiliary), (extract_swz:{ *:[i1] } ?:{ *:[i32] }:$auxiliary))
        GIR_BuildMI, /*InsnID*/0, /*Opcode*/GIMT_Encode2(AMDGPU::TBUFFER_LOAD_FORMAT_D16_XYZ_OFFEN),
        GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/0, // DstI[vdata]
        GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/3, // voffset
        GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/1, // rsrc
        GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/0, // soffset
        GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/5, // offset
        GIR_CustomOperandRenderer, /*InsnID*/0, /*OldInsnID*/0, /*OpIdx*/6, /*OperandRenderer*/GIMT_Encode2(GICR_renderTruncTImm), // format
        GIR_CustomOperandRenderer, /*InsnID*/0, /*OldInsnID*/0, /*OpIdx*/7, /*OperandRenderer*/GIMT_Encode2(GICR_renderExtractCPol), // auxiliary
        GIR_CustomOperandRenderer, /*InsnID*/0, /*OldInsnID*/0, /*OpIdx*/7, /*OperandRenderer*/GIMT_Encode2(GICR_renderExtractSWZ), // auxiliary
        GIR_MergeMemOperands, /*InsnID*/0, /*NumInsns*/1, /*MergeInsnID's*/0,
        GIR_ConstrainSelectedInstOperands, /*InsnID*/0,
        GIR_EraseFromParent, /*InsnID*/0,
        // GIR_Coverage, 5679,
        GIR_Done,
      // Label 7341: @536280
      GIM_Try, /*On fail goto*//*Label 7342*/ GIMT_Encode4(536383), // Rule ID 5683 //
        GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasPackedD16VMem),
        GIM_CheckMemorySizeEqualTo, /*MI*/0, /*MMO*/0, /*Size*/GIMT_Encode4(6),
        GIM_CheckRegBankForClass, /*MI*/0, /*Op*/0, /*RC*/GIMT_Encode2(AMDGPU::AV_64RegClassID),
        GIM_CheckConstantInt8, /*MI*/0, /*Op*/2, 0,
        // MIs[0] offset
        GIM_CheckIsImm, /*MI*/0, /*Op*/5,
        // MIs[0] format
        GIM_CheckIsImm, /*MI*/0, /*Op*/6,
        // MIs[0] auxiliary
        GIM_CheckIsImm, /*MI*/0, /*Op*/7,
        // MIs[0] Operand 8
        GIM_CheckLiteralInt, /*MI*/0, /*Op*/8, GIMT_Encode8(0),
        GIM_CheckComplexPattern, /*MI*/0, /*Op*/4, /*Renderer*/GIMT_Encode2(0), GIMT_Encode2(GICP_gi_buf_soffset),
        // (SItbuffer_load_d16:{ *:[v4f16] } v4i32:{ *:[v4i32] }:$rsrc, 0:{ *:[i32] }, i32:{ *:[i32] }:$voffset, (BUFSOffset:{ *:[i32] } i32:{ *:[i32] }:$soffset), (timm:{ *:[i32] }):$offset, (timm:{ *:[i32] }):$format, (timm:{ *:[i32] }):$auxiliary, 0:{ *:[i1] })<<P:Predicate_anonymous_34123>>  =>  (TBUFFER_LOAD_FORMAT_D16_XYZ_VBUFFER_OFFEN:{ *:[v4f16] } VGPR_32:{ *:[i32] }:$voffset, SReg_128:{ *:[v4i32] }:$rsrc, SCSrc_b32:{ *:[i32] }:$soffset, (timm:{ *:[i32] }):$offset, (as_i8timm:{ *:[i8] } ?:{ *:[i32] }:$format), (extract_cpol:{ *:[i32] } ?:{ *:[i32] }:$auxiliary), (extract_swz:{ *:[i1] } ?:{ *:[i32] }:$auxiliary))
        GIR_BuildMI, /*InsnID*/0, /*Opcode*/GIMT_Encode2(AMDGPU::TBUFFER_LOAD_FORMAT_D16_XYZ_VBUFFER_OFFEN),
        GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/0, // DstI[vdata]
        GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/3, // voffset
        GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/1, // rsrc
        GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/0, // soffset
        GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/5, // offset
        GIR_CustomOperandRenderer, /*InsnID*/0, /*OldInsnID*/0, /*OpIdx*/6, /*OperandRenderer*/GIMT_Encode2(GICR_renderTruncTImm), // format
        GIR_CustomOperandRenderer, /*InsnID*/0, /*OldInsnID*/0, /*OpIdx*/7, /*OperandRenderer*/GIMT_Encode2(GICR_renderExtractCPol), // auxiliary
        GIR_CustomOperandRenderer, /*InsnID*/0, /*OldInsnID*/0, /*OpIdx*/7, /*OperandRenderer*/GIMT_Encode2(GICR_renderExtractSWZ), // auxiliary
        GIR_MergeMemOperands, /*InsnID*/0, /*NumInsns*/1, /*MergeInsnID's*/0,
        GIR_ConstrainSelectedInstOperands, /*InsnID*/0,
        GIR_EraseFromParent, /*InsnID*/0,
        // GIR_Coverage, 5683,
        GIR_Done,
      // Label 7342: @536383
      GIM_Try, /*On fail goto*//*Label 7343*/ GIMT_Encode4(536479), // Rule ID 5687 //
        GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasPackedD16VMem_HasUnrestrictedSOffset),
        GIM_CheckRegBankForClass, /*MI*/0, /*Op*/0, /*RC*/GIMT_Encode2(AMDGPU::AV_64RegClassID),
        GIM_CheckConstantInt8, /*MI*/0, /*Op*/2, 0,
        // MIs[0] offset
        GIM_CheckIsImm, /*MI*/0, /*Op*/5,
        // MIs[0] format
        GIM_CheckIsImm, /*MI*/0, /*Op*/6,
        // MIs[0] auxiliary
        GIM_CheckIsImm, /*MI*/0, /*Op*/7,
        // MIs[0] Operand 8
        GIM_CheckLiteralInt, /*MI*/0, /*Op*/8, GIMT_Encode8(0),
        GIM_CheckComplexPattern, /*MI*/0, /*Op*/4, /*Renderer*/GIMT_Encode2(0), GIMT_Encode2(GICP_gi_buf_soffset),
        // (SItbuffer_load_d16:{ *:[v4f16] } v4i32:{ *:[v4i32] }:$rsrc, 0:{ *:[i32] }, i32:{ *:[i32] }:$voffset, (BUFSOffset:{ *:[i32] } i32:{ *:[i32] }:$soffset), (timm:{ *:[i32] }):$offset, (timm:{ *:[i32] }):$format, (timm:{ *:[i32] }):$auxiliary, 0:{ *:[i1] })  =>  (TBUFFER_LOAD_FORMAT_D16_XYZW_OFFEN:{ *:[v4f16] } VGPR_32:{ *:[i32] }:$voffset, SReg_128:{ *:[v4i32] }:$rsrc, SCSrc_b32:{ *:[i32] }:$soffset, (timm:{ *:[i32] }):$offset, (as_i8timm:{ *:[i8] } ?:{ *:[i32] }:$format), (extract_cpol:{ *:[i32] } ?:{ *:[i32] }:$auxiliary), (extract_swz:{ *:[i1] } ?:{ *:[i32] }:$auxiliary))
        GIR_BuildMI, /*InsnID*/0, /*Opcode*/GIMT_Encode2(AMDGPU::TBUFFER_LOAD_FORMAT_D16_XYZW_OFFEN),
        GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/0, // DstI[vdata]
        GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/3, // voffset
        GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/1, // rsrc
        GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/0, // soffset
        GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/5, // offset
        GIR_CustomOperandRenderer, /*InsnID*/0, /*OldInsnID*/0, /*OpIdx*/6, /*OperandRenderer*/GIMT_Encode2(GICR_renderTruncTImm), // format
        GIR_CustomOperandRenderer, /*InsnID*/0, /*OldInsnID*/0, /*OpIdx*/7, /*OperandRenderer*/GIMT_Encode2(GICR_renderExtractCPol), // auxiliary
        GIR_CustomOperandRenderer, /*InsnID*/0, /*OldInsnID*/0, /*OpIdx*/7, /*OperandRenderer*/GIMT_Encode2(GICR_renderExtractSWZ), // auxiliary
        GIR_MergeMemOperands, /*InsnID*/0, /*NumInsns*/1, /*MergeInsnID's*/0,
        GIR_ConstrainSelectedInstOperands, /*InsnID*/0,
        GIR_EraseFromParent, /*InsnID*/0,
        // GIR_Coverage, 5687,
        GIR_Done,
      // Label 7343: @536479
      GIM_Try, /*On fail goto*//*Label 7344*/ GIMT_Encode4(536575), // Rule ID 5691 //
        GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasPackedD16VMem),
        GIM_CheckRegBankForClass, /*MI*/0, /*Op*/0, /*RC*/GIMT_Encode2(AMDGPU::AV_64RegClassID),
        GIM_CheckConstantInt8, /*MI*/0, /*Op*/2, 0,
        // MIs[0] offset
        GIM_CheckIsImm, /*MI*/0, /*Op*/5,
        // MIs[0] format
        GIM_CheckIsImm, /*MI*/0, /*Op*/6,
        // MIs[0] auxiliary
        GIM_CheckIsImm, /*MI*/0, /*Op*/7,
        // MIs[0] Operand 8
        GIM_CheckLiteralInt, /*MI*/0, /*Op*/8, GIMT_Encode8(0),
        GIM_CheckComplexPattern, /*MI*/0, /*Op*/4, /*Renderer*/GIMT_Encode2(0), GIMT_Encode2(GICP_gi_buf_soffset),
        // (SItbuffer_load_d16:{ *:[v4f16] } v4i32:{ *:[v4i32] }:$rsrc, 0:{ *:[i32] }, i32:{ *:[i32] }:$voffset, (BUFSOffset:{ *:[i32] } i32:{ *:[i32] }:$soffset), (timm:{ *:[i32] }):$offset, (timm:{ *:[i32] }):$format, (timm:{ *:[i32] }):$auxiliary, 0:{ *:[i1] })  =>  (TBUFFER_LOAD_FORMAT_D16_XYZW_VBUFFER_OFFEN:{ *:[v4f16] } VGPR_32:{ *:[i32] }:$voffset, SReg_128:{ *:[v4i32] }:$rsrc, SCSrc_b32:{ *:[i32] }:$soffset, (timm:{ *:[i32] }):$offset, (as_i8timm:{ *:[i8] } ?:{ *:[i32] }:$format), (extract_cpol:{ *:[i32] } ?:{ *:[i32] }:$auxiliary), (extract_swz:{ *:[i1] } ?:{ *:[i32] }:$auxiliary))
        GIR_BuildMI, /*InsnID*/0, /*Opcode*/GIMT_Encode2(AMDGPU::TBUFFER_LOAD_FORMAT_D16_XYZW_VBUFFER_OFFEN),
        GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/0, // DstI[vdata]
        GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/3, // voffset
        GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/1, // rsrc
        GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/0, // soffset
        GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/5, // offset
        GIR_CustomOperandRenderer, /*InsnID*/0, /*OldInsnID*/0, /*OpIdx*/6, /*OperandRenderer*/GIMT_Encode2(GICR_renderTruncTImm), // format
        GIR_CustomOperandRenderer, /*InsnID*/0, /*OldInsnID*/0, /*OpIdx*/7, /*OperandRenderer*/GIMT_Encode2(GICR_renderExtractCPol), // auxiliary
        GIR_CustomOperandRenderer, /*InsnID*/0, /*OldInsnID*/0, /*OpIdx*/7, /*OperandRenderer*/GIMT_Encode2(GICR_renderExtractSWZ), // auxiliary
        GIR_MergeMemOperands, /*InsnID*/0, /*NumInsns*/1, /*MergeInsnID's*/0,
        GIR_ConstrainSelectedInstOperands, /*InsnID*/0,
        GIR_EraseFromParent, /*InsnID*/0,
        // GIR_Coverage, 5691,
        GIR_Done,
      // Label 7344: @536575
      GIM_Try, /*On fail goto*//*Label 7345*/ GIMT_Encode4(536670), // Rule ID 5678 //
        GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasPackedD16VMem_HasUnrestrictedSOffset),
        GIM_CheckMemorySizeEqualTo, /*MI*/0, /*MMO*/0, /*Size*/GIMT_Encode4(6),
        GIM_CheckRegBankForClass, /*MI*/0, /*Op*/0, /*RC*/GIMT_Encode2(AMDGPU::AV_64RegClassID),
        GIM_CheckConstantInt8, /*MI*/0, /*Op*/3, 0,
        // MIs[0] offset
        GIM_CheckIsImm, /*MI*/0, /*Op*/5,
        // MIs[0] format
        GIM_CheckIsImm, /*MI*/0, /*Op*/6,
        // MIs[0] auxiliary
        GIM_CheckIsImm, /*MI*/0, /*Op*/7,
        // MIs[0] Operand 8
        GIM_CheckIsImm, /*MI*/0, /*Op*/8,
        GIM_CheckComplexPattern, /*MI*/0, /*Op*/4, /*Renderer*/GIMT_Encode2(0), GIMT_Encode2(GICP_gi_buf_soffset),
        // (SItbuffer_load_d16:{ *:[v4f16] } v4i32:{ *:[v4i32] }:$rsrc, i32:{ *:[i32] }:$vindex, 0:{ *:[i32] }, (BUFSOffset:{ *:[i32] } i32:{ *:[i32] }:$soffset), (timm:{ *:[i32] }):$offset, (timm:{ *:[i32] }):$format, (timm:{ *:[i32] }):$auxiliary, (timm:{ *:[i1] }))<<P:Predicate_anonymous_34123>>  =>  (TBUFFER_LOAD_FORMAT_D16_XYZ_IDXEN:{ *:[v4f16] } VGPR_32:{ *:[i32] }:$vindex, SReg_128:{ *:[v4i32] }:$rsrc, SCSrc_b32:{ *:[i32] }:$soffset, (timm:{ *:[i32] }):$offset, (as_i8timm:{ *:[i8] } ?:{ *:[i32] }:$format), (extract_cpol:{ *:[i32] } ?:{ *:[i32] }:$auxiliary), (extract_swz:{ *:[i1] } ?:{ *:[i32] }:$auxiliary))
        GIR_BuildMI, /*InsnID*/0, /*Opcode*/GIMT_Encode2(AMDGPU::TBUFFER_LOAD_FORMAT_D16_XYZ_IDXEN),
        GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/0, // DstI[vdata]
        GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/2, // vindex
        GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/1, // rsrc
        GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/0, // soffset
        GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/5, // offset
        GIR_CustomOperandRenderer, /*InsnID*/0, /*OldInsnID*/0, /*OpIdx*/6, /*OperandRenderer*/GIMT_Encode2(GICR_renderTruncTImm), // format
        GIR_CustomOperandRenderer, /*InsnID*/0, /*OldInsnID*/0, /*OpIdx*/7, /*OperandRenderer*/GIMT_Encode2(GICR_renderExtractCPol), // auxiliary
        GIR_CustomOperandRenderer, /*InsnID*/0, /*OldInsnID*/0, /*OpIdx*/7, /*OperandRenderer*/GIMT_Encode2(GICR_renderExtractSWZ), // auxiliary
        GIR_MergeMemOperands, /*InsnID*/0, /*NumInsns*/1, /*MergeInsnID's*/0,
        GIR_ConstrainSelectedInstOperands, /*InsnID*/0,
        GIR_EraseFromParent, /*InsnID*/0,
        // GIR_Coverage, 5678,
        GIR_Done,
      // Label 7345: @536670
      GIM_Try, /*On fail goto*//*Label 7346*/ GIMT_Encode4(536765), // Rule ID 5682 //
        GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasPackedD16VMem),
        GIM_CheckMemorySizeEqualTo, /*MI*/0, /*MMO*/0, /*Size*/GIMT_Encode4(6),
        GIM_CheckRegBankForClass, /*MI*/0, /*Op*/0, /*RC*/GIMT_Encode2(AMDGPU::AV_64RegClassID),
        GIM_CheckConstantInt8, /*MI*/0, /*Op*/3, 0,
        // MIs[0] offset
        GIM_CheckIsImm, /*MI*/0, /*Op*/5,
        // MIs[0] format
        GIM_CheckIsImm, /*MI*/0, /*Op*/6,
        // MIs[0] auxiliary
        GIM_CheckIsImm, /*MI*/0, /*Op*/7,
        // MIs[0] Operand 8
        GIM_CheckIsImm, /*MI*/0, /*Op*/8,
        GIM_CheckComplexPattern, /*MI*/0, /*Op*/4, /*Renderer*/GIMT_Encode2(0), GIMT_Encode2(GICP_gi_buf_soffset),
        // (SItbuffer_load_d16:{ *:[v4f16] } v4i32:{ *:[v4i32] }:$rsrc, i32:{ *:[i32] }:$vindex, 0:{ *:[i32] }, (BUFSOffset:{ *:[i32] } i32:{ *:[i32] }:$soffset), (timm:{ *:[i32] }):$offset, (timm:{ *:[i32] }):$format, (timm:{ *:[i32] }):$auxiliary, (timm:{ *:[i1] }))<<P:Predicate_anonymous_34123>>  =>  (TBUFFER_LOAD_FORMAT_D16_XYZ_VBUFFER_IDXEN:{ *:[v4f16] } VGPR_32:{ *:[i32] }:$vindex, SReg_128:{ *:[v4i32] }:$rsrc, SCSrc_b32:{ *:[i32] }:$soffset, (timm:{ *:[i32] }):$offset, (as_i8timm:{ *:[i8] } ?:{ *:[i32] }:$format), (extract_cpol:{ *:[i32] } ?:{ *:[i32] }:$auxiliary), (extract_swz:{ *:[i1] } ?:{ *:[i32] }:$auxiliary))
        GIR_BuildMI, /*InsnID*/0, /*Opcode*/GIMT_Encode2(AMDGPU::TBUFFER_LOAD_FORMAT_D16_XYZ_VBUFFER_IDXEN),
        GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/0, // DstI[vdata]
        GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/2, // vindex
        GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/1, // rsrc
        GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/0, // soffset
        GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/5, // offset
        GIR_CustomOperandRenderer, /*InsnID*/0, /*OldInsnID*/0, /*OpIdx*/6, /*OperandRenderer*/GIMT_Encode2(GICR_renderTruncTImm), // format
        GIR_CustomOperandRenderer, /*InsnID*/0, /*OldInsnID*/0, /*OpIdx*/7, /*OperandRenderer*/GIMT_Encode2(GICR_renderExtractCPol), // auxiliary
        GIR_CustomOperandRenderer, /*InsnID*/0, /*OldInsnID*/0, /*OpIdx*/7, /*OperandRenderer*/GIMT_Encode2(GICR_renderExtractSWZ), // auxiliary
        GIR_MergeMemOperands, /*InsnID*/0, /*NumInsns*/1, /*MergeInsnID's*/0,
        GIR_ConstrainSelectedInstOperands, /*InsnID*/0,
        GIR_EraseFromParent, /*InsnID*/0,
        // GIR_Coverage, 5682,
        GIR_Done,
      // Label 7346: @536765
      GIM_Try, /*On fail goto*//*Label 7347*/ GIMT_Encode4(536853), // Rule ID 5686 //
        GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasPackedD16VMem_HasUnrestrictedSOffset),
        GIM_CheckRegBankForClass, /*MI*/0, /*Op*/0, /*RC*/GIMT_Encode2(AMDGPU::AV_64RegClassID),
        GIM_CheckConstantInt8, /*MI*/0, /*Op*/3, 0,
        // MIs[0] offset
        GIM_CheckIsImm, /*MI*/0, /*Op*/5,
        // MIs[0] format
        GIM_CheckIsImm, /*MI*/0, /*Op*/6,
        // MIs[0] auxiliary
        GIM_CheckIsImm, /*MI*/0, /*Op*/7,
        // MIs[0] Operand 8
        GIM_CheckIsImm, /*MI*/0, /*Op*/8,
        GIM_CheckComplexPattern, /*MI*/0, /*Op*/4, /*Renderer*/GIMT_Encode2(0), GIMT_Encode2(GICP_gi_buf_soffset),
        // (SItbuffer_load_d16:{ *:[v4f16] } v4i32:{ *:[v4i32] }:$rsrc, i32:{ *:[i32] }:$vindex, 0:{ *:[i32] }, (BUFSOffset:{ *:[i32] } i32:{ *:[i32] }:$soffset), (timm:{ *:[i32] }):$offset, (timm:{ *:[i32] }):$format, (timm:{ *:[i32] }):$auxiliary, (timm:{ *:[i1] }))  =>  (TBUFFER_LOAD_FORMAT_D16_XYZW_IDXEN:{ *:[v4f16] } VGPR_32:{ *:[i32] }:$vindex, SReg_128:{ *:[v4i32] }:$rsrc, SCSrc_b32:{ *:[i32] }:$soffset, (timm:{ *:[i32] }):$offset, (as_i8timm:{ *:[i8] } ?:{ *:[i32] }:$format), (extract_cpol:{ *:[i32] } ?:{ *:[i32] }:$auxiliary), (extract_swz:{ *:[i1] } ?:{ *:[i32] }:$auxiliary))
        GIR_BuildMI, /*InsnID*/0, /*Opcode*/GIMT_Encode2(AMDGPU::TBUFFER_LOAD_FORMAT_D16_XYZW_IDXEN),
        GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/0, // DstI[vdata]
        GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/2, // vindex
        GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/1, // rsrc
        GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/0, // soffset
        GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/5, // offset
        GIR_CustomOperandRenderer, /*InsnID*/0, /*OldInsnID*/0, /*OpIdx*/6, /*OperandRenderer*/GIMT_Encode2(GICR_renderTruncTImm), // format
        GIR_CustomOperandRenderer, /*InsnID*/0, /*OldInsnID*/0, /*OpIdx*/7, /*OperandRenderer*/GIMT_Encode2(GICR_renderExtractCPol), // auxiliary
        GIR_CustomOperandRenderer, /*InsnID*/0, /*OldInsnID*/0, /*OpIdx*/7, /*OperandRenderer*/GIMT_Encode2(GICR_renderExtractSWZ), // auxiliary
        GIR_MergeMemOperands, /*InsnID*/0, /*NumInsns*/1, /*MergeInsnID's*/0,
        GIR_ConstrainSelectedInstOperands, /*InsnID*/0,
        GIR_EraseFromParent, /*InsnID*/0,
        // GIR_Coverage, 5686,
        GIR_Done,
      // Label 7347: @536853
      GIM_Try, /*On fail goto*//*Label 7348*/ GIMT_Encode4(536941), // Rule ID 5690 //
        GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasPackedD16VMem),
        GIM_CheckRegBankForClass, /*MI*/0, /*Op*/0, /*RC*/GIMT_Encode2(AMDGPU::AV_64RegClassID),
        GIM_CheckConstantInt8, /*MI*/0, /*Op*/3, 0,
        // MIs[0] offset
        GIM_CheckIsImm, /*MI*/0, /*Op*/5,
        // MIs[0] format
        GIM_CheckIsImm, /*MI*/0, /*Op*/6,
        // MIs[0] auxiliary
        GIM_CheckIsImm, /*MI*/0, /*Op*/7,
        // MIs[0] Operand 8
        GIM_CheckIsImm, /*MI*/0, /*Op*/8,
        GIM_CheckComplexPattern, /*MI*/0, /*Op*/4, /*Renderer*/GIMT_Encode2(0), GIMT_Encode2(GICP_gi_buf_soffset),
        // (SItbuffer_load_d16:{ *:[v4f16] } v4i32:{ *:[v4i32] }:$rsrc, i32:{ *:[i32] }:$vindex, 0:{ *:[i32] }, (BUFSOffset:{ *:[i32] } i32:{ *:[i32] }:$soffset), (timm:{ *:[i32] }):$offset, (timm:{ *:[i32] }):$format, (timm:{ *:[i32] }):$auxiliary, (timm:{ *:[i1] }))  =>  (TBUFFER_LOAD_FORMAT_D16_XYZW_VBUFFER_IDXEN:{ *:[v4f16] } VGPR_32:{ *:[i32] }:$vindex, SReg_128:{ *:[v4i32] }:$rsrc, SCSrc_b32:{ *:[i32] }:$soffset, (timm:{ *:[i32] }):$offset, (as_i8timm:{ *:[i8] } ?:{ *:[i32] }:$format), (extract_cpol:{ *:[i32] } ?:{ *:[i32] }:$auxiliary), (extract_swz:{ *:[i1] } ?:{ *:[i32] }:$auxiliary))
        GIR_BuildMI, /*InsnID*/0, /*Opcode*/GIMT_Encode2(AMDGPU::TBUFFER_LOAD_FORMAT_D16_XYZW_VBUFFER_IDXEN),
        GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/0, // DstI[vdata]
        GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/2, // vindex
        GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/1, // rsrc
        GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/0, // soffset
        GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/5, // offset
        GIR_CustomOperandRenderer, /*InsnID*/0, /*OldInsnID*/0, /*OpIdx*/6, /*OperandRenderer*/GIMT_Encode2(GICR_renderTruncTImm), // format
        GIR_CustomOperandRenderer, /*InsnID*/0, /*OldInsnID*/0, /*OpIdx*/7, /*OperandRenderer*/GIMT_Encode2(GICR_renderExtractCPol), // auxiliary
        GIR_CustomOperandRenderer, /*InsnID*/0, /*OldInsnID*/0, /*OpIdx*/7, /*OperandRenderer*/GIMT_Encode2(GICR_renderExtractSWZ), // auxiliary
        GIR_MergeMemOperands, /*InsnID*/0, /*NumInsns*/1, /*MergeInsnID's*/0,
        GIR_ConstrainSelectedInstOperands, /*InsnID*/0,
        GIR_EraseFromParent, /*InsnID*/0,
        // GIR_Coverage, 5690,
        GIR_Done,
      // Label 7348: @536941
      GIM_Try, /*On fail goto*//*Label 7349*/ GIMT_Encode4(537072), // Rule ID 5680 //
        GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasPackedD16VMem_HasUnrestrictedSOffset),
        GIM_CheckMemorySizeEqualTo, /*MI*/0, /*MMO*/0, /*Size*/GIMT_Encode4(6),
        GIM_CheckRegBankForClass, /*MI*/0, /*Op*/0, /*RC*/GIMT_Encode2(AMDGPU::AV_64RegClassID),
        // MIs[0] offset
        GIM_CheckIsImm, /*MI*/0, /*Op*/5,
        // MIs[0] format
        GIM_CheckIsImm, /*MI*/0, /*Op*/6,
        // MIs[0] auxiliary
        GIM_CheckIsImm, /*MI*/0, /*Op*/7,
        // MIs[0] Operand 8
        GIM_CheckIsImm, /*MI*/0, /*Op*/8,
        GIM_CheckComplexPattern, /*MI*/0, /*Op*/4, /*Renderer*/GIMT_Encode2(0), GIMT_Encode2(GICP_gi_buf_soffset),
        // (SItbuffer_load_d16:{ *:[v4f16] } v4i32:{ *:[v4i32] }:$rsrc, i32:{ *:[i32] }:$vindex, i32:{ *:[i32] }:$voffset, (BUFSOffset:{ *:[i32] } i32:{ *:[i32] }:$soffset), (timm:{ *:[i32] }):$offset, (timm:{ *:[i32] }):$format, (timm:{ *:[i32] }):$auxiliary, (timm:{ *:[i1] }))<<P:Predicate_anonymous_34123>>  =>  (TBUFFER_LOAD_FORMAT_D16_XYZ_BOTHEN:{ *:[v4f16] } (REG_SEQUENCE:{ *:[i64] } VReg_64:{ *:[i32] }, VGPR_32:{ *:[i32] }:$vindex, sub0:{ *:[i32] }, VGPR_32:{ *:[i32] }:$voffset, sub1:{ *:[i32] }), SReg_128:{ *:[v4i32] }:$rsrc, SCSrc_b32:{ *:[i32] }:$soffset, (timm:{ *:[i32] }):$offset, (as_i8timm:{ *:[i8] } ?:{ *:[i32] }:$format), (extract_cpol:{ *:[i32] } ?:{ *:[i32] }:$auxiliary), (extract_swz:{ *:[i1] } ?:{ *:[i32] }:$auxiliary))
        GIR_MakeTempReg, /*TempRegID*/0, /*TypeID*/GILLT_s64,
        GIR_BuildMI, /*InsnID*/1, /*Opcode*/GIMT_Encode2(TargetOpcode::REG_SEQUENCE),
        GIR_AddTempRegister, /*InsnID*/1, /*TempRegID*/0, /*TempRegFlags*/GIMT_Encode2(RegState::Define),
        GIR_Copy, /*NewInsnID*/1, /*OldInsnID*/0, /*OpIdx*/2, // vindex
        GIR_AddImm8, /*InsnID*/1, /*SubRegIndex*/3,
        GIR_Copy, /*NewInsnID*/1, /*OldInsnID*/0, /*OpIdx*/3, // voffset
        GIR_AddImm8, /*InsnID*/1, /*SubRegIndex*/11,
        GIR_ConstrainOperandRC, /*InsnID*/1, /*Op*/0, GIMT_Encode2(AMDGPU::VReg_64RegClassID),
        GIR_ConstrainOperandRC, /*InsnID*/1, /*Op*/1, GIMT_Encode2(AMDGPU::VGPR_32RegClassID),
        GIR_ConstrainOperandRC, /*InsnID*/1, /*Op*/3, GIMT_Encode2(AMDGPU::VGPR_32RegClassID),
        GIR_BuildMI, /*InsnID*/0, /*Opcode*/GIMT_Encode2(AMDGPU::TBUFFER_LOAD_FORMAT_D16_XYZ_BOTHEN),
        GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/0, // DstI[vdata]
        GIR_AddSimpleTempRegister, /*InsnID*/0, /*TempRegID*/0,
        GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/1, // rsrc
        GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/0, // soffset
        GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/5, // offset
        GIR_CustomOperandRenderer, /*InsnID*/0, /*OldInsnID*/0, /*OpIdx*/6, /*OperandRenderer*/GIMT_Encode2(GICR_renderTruncTImm), // format
        GIR_CustomOperandRenderer, /*InsnID*/0, /*OldInsnID*/0, /*OpIdx*/7, /*OperandRenderer*/GIMT_Encode2(GICR_renderExtractCPol), // auxiliary
        GIR_CustomOperandRenderer, /*InsnID*/0, /*OldInsnID*/0, /*OpIdx*/7, /*OperandRenderer*/GIMT_Encode2(GICR_renderExtractSWZ), // auxiliary
        GIR_MergeMemOperands, /*InsnID*/0, /*NumInsns*/1, /*MergeInsnID's*/0,
        GIR_ConstrainSelectedInstOperands, /*InsnID*/0,
        GIR_EraseFromParent, /*InsnID*/0,
        // GIR_Coverage, 5680,
        GIR_Done,
      // Label 7349: @537072
      GIM_Try, /*On fail goto*//*Label 7350*/ GIMT_Encode4(537203), // Rule ID 5684 //
        GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasPackedD16VMem),
        GIM_CheckMemorySizeEqualTo, /*MI*/0, /*MMO*/0, /*Size*/GIMT_Encode4(6),
        GIM_CheckRegBankForClass, /*MI*/0, /*Op*/0, /*RC*/GIMT_Encode2(AMDGPU::AV_64RegClassID),
        // MIs[0] offset
        GIM_CheckIsImm, /*MI*/0, /*Op*/5,
        // MIs[0] format
        GIM_CheckIsImm, /*MI*/0, /*Op*/6,
        // MIs[0] auxiliary
        GIM_CheckIsImm, /*MI*/0, /*Op*/7,
        // MIs[0] Operand 8
        GIM_CheckIsImm, /*MI*/0, /*Op*/8,
        GIM_CheckComplexPattern, /*MI*/0, /*Op*/4, /*Renderer*/GIMT_Encode2(0), GIMT_Encode2(GICP_gi_buf_soffset),
        // (SItbuffer_load_d16:{ *:[v4f16] } v4i32:{ *:[v4i32] }:$rsrc, i32:{ *:[i32] }:$vindex, i32:{ *:[i32] }:$voffset, (BUFSOffset:{ *:[i32] } i32:{ *:[i32] }:$soffset), (timm:{ *:[i32] }):$offset, (timm:{ *:[i32] }):$format, (timm:{ *:[i32] }):$auxiliary, (timm:{ *:[i1] }))<<P:Predicate_anonymous_34123>>  =>  (TBUFFER_LOAD_FORMAT_D16_XYZ_VBUFFER_BOTHEN:{ *:[v4f16] } (REG_SEQUENCE:{ *:[i64] } VReg_64:{ *:[i32] }, VGPR_32:{ *:[i32] }:$vindex, sub0:{ *:[i32] }, VGPR_32:{ *:[i32] }:$voffset, sub1:{ *:[i32] }), SReg_128:{ *:[v4i32] }:$rsrc, SCSrc_b32:{ *:[i32] }:$soffset, (timm:{ *:[i32] }):$offset, (as_i8timm:{ *:[i8] } ?:{ *:[i32] }:$format), (extract_cpol:{ *:[i32] } ?:{ *:[i32] }:$auxiliary), (extract_swz:{ *:[i1] } ?:{ *:[i32] }:$auxiliary))
        GIR_MakeTempReg, /*TempRegID*/0, /*TypeID*/GILLT_s64,
        GIR_BuildMI, /*InsnID*/1, /*Opcode*/GIMT_Encode2(TargetOpcode::REG_SEQUENCE),
        GIR_AddTempRegister, /*InsnID*/1, /*TempRegID*/0, /*TempRegFlags*/GIMT_Encode2(RegState::Define),
        GIR_Copy, /*NewInsnID*/1, /*OldInsnID*/0, /*OpIdx*/2, // vindex
        GIR_AddImm8, /*InsnID*/1, /*SubRegIndex*/3,
        GIR_Copy, /*NewInsnID*/1, /*OldInsnID*/0, /*OpIdx*/3, // voffset
        GIR_AddImm8, /*InsnID*/1, /*SubRegIndex*/11,
        GIR_ConstrainOperandRC, /*InsnID*/1, /*Op*/0, GIMT_Encode2(AMDGPU::VReg_64RegClassID),
        GIR_ConstrainOperandRC, /*InsnID*/1, /*Op*/1, GIMT_Encode2(AMDGPU::VGPR_32RegClassID),
        GIR_ConstrainOperandRC, /*InsnID*/1, /*Op*/3, GIMT_Encode2(AMDGPU::VGPR_32RegClassID),
        GIR_BuildMI, /*InsnID*/0, /*Opcode*/GIMT_Encode2(AMDGPU::TBUFFER_LOAD_FORMAT_D16_XYZ_VBUFFER_BOTHEN),
        GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/0, // DstI[vdata]
        GIR_AddSimpleTempRegister, /*InsnID*/0, /*TempRegID*/0,
        GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/1, // rsrc
        GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/0, // soffset
        GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/5, // offset
        GIR_CustomOperandRenderer, /*InsnID*/0, /*OldInsnID*/0, /*OpIdx*/6, /*OperandRenderer*/GIMT_Encode2(GICR_renderTruncTImm), // format
        GIR_CustomOperandRenderer, /*InsnID*/0, /*OldInsnID*/0, /*OpIdx*/7, /*OperandRenderer*/GIMT_Encode2(GICR_renderExtractCPol), // auxiliary
        GIR_CustomOperandRenderer, /*InsnID*/0, /*OldInsnID*/0, /*OpIdx*/7, /*OperandRenderer*/GIMT_Encode2(GICR_renderExtractSWZ), // auxiliary
        GIR_MergeMemOperands, /*InsnID*/0, /*NumInsns*/1, /*MergeInsnID's*/0,
        GIR_ConstrainSelectedInstOperands, /*InsnID*/0,
        GIR_EraseFromParent, /*InsnID*/0,
        // GIR_Coverage, 5684,
        GIR_Done,
      // Label 7350: @537203
      GIM_Try, /*On fail goto*//*Label 7351*/ GIMT_Encode4(537327), // Rule ID 5688 //
        GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasPackedD16VMem_HasUnrestrictedSOffset),
        GIM_CheckRegBankForClass, /*MI*/0, /*Op*/0, /*RC*/GIMT_Encode2(AMDGPU::AV_64RegClassID),
        // MIs[0] offset
        GIM_CheckIsImm, /*MI*/0, /*Op*/5,
        // MIs[0] format
        GIM_CheckIsImm, /*MI*/0, /*Op*/6,
        // MIs[0] auxiliary
        GIM_CheckIsImm, /*MI*/0, /*Op*/7,
        // MIs[0] Operand 8
        GIM_CheckIsImm, /*MI*/0, /*Op*/8,
        GIM_CheckComplexPattern, /*MI*/0, /*Op*/4, /*Renderer*/GIMT_Encode2(0), GIMT_Encode2(GICP_gi_buf_soffset),
        // (SItbuffer_load_d16:{ *:[v4f16] } v4i32:{ *:[v4i32] }:$rsrc, i32:{ *:[i32] }:$vindex, i32:{ *:[i32] }:$voffset, (BUFSOffset:{ *:[i32] } i32:{ *:[i32] }:$soffset), (timm:{ *:[i32] }):$offset, (timm:{ *:[i32] }):$format, (timm:{ *:[i32] }):$auxiliary, (timm:{ *:[i1] }))  =>  (TBUFFER_LOAD_FORMAT_D16_XYZW_BOTHEN:{ *:[v4f16] } (REG_SEQUENCE:{ *:[i64] } VReg_64:{ *:[i32] }, VGPR_32:{ *:[i32] }:$vindex, sub0:{ *:[i32] }, VGPR_32:{ *:[i32] }:$voffset, sub1:{ *:[i32] }), SReg_128:{ *:[v4i32] }:$rsrc, SCSrc_b32:{ *:[i32] }:$soffset, (timm:{ *:[i32] }):$offset, (as_i8timm:{ *:[i8] } ?:{ *:[i32] }:$format), (extract_cpol:{ *:[i32] } ?:{ *:[i32] }:$auxiliary), (extract_swz:{ *:[i1] } ?:{ *:[i32] }:$auxiliary))
        GIR_MakeTempReg, /*TempRegID*/0, /*TypeID*/GILLT_s64,
        GIR_BuildMI, /*InsnID*/1, /*Opcode*/GIMT_Encode2(TargetOpcode::REG_SEQUENCE),
        GIR_AddTempRegister, /*InsnID*/1, /*TempRegID*/0, /*TempRegFlags*/GIMT_Encode2(RegState::Define),
        GIR_Copy, /*NewInsnID*/1, /*OldInsnID*/0, /*OpIdx*/2, // vindex
        GIR_AddImm8, /*InsnID*/1, /*SubRegIndex*/3,
        GIR_Copy, /*NewInsnID*/1, /*OldInsnID*/0, /*OpIdx*/3, // voffset
        GIR_AddImm8, /*InsnID*/1, /*SubRegIndex*/11,
        GIR_ConstrainOperandRC, /*InsnID*/1, /*Op*/0, GIMT_Encode2(AMDGPU::VReg_64RegClassID),
        GIR_ConstrainOperandRC, /*InsnID*/1, /*Op*/1, GIMT_Encode2(AMDGPU::VGPR_32RegClassID),
        GIR_ConstrainOperandRC, /*InsnID*/1, /*Op*/3, GIMT_Encode2(AMDGPU::VGPR_32RegClassID),
        GIR_BuildMI, /*InsnID*/0, /*Opcode*/GIMT_Encode2(AMDGPU::TBUFFER_LOAD_FORMAT_D16_XYZW_BOTHEN),
        GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/0, // DstI[vdata]
        GIR_AddSimpleTempRegister, /*InsnID*/0, /*TempRegID*/0,
        GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/1, // rsrc
        GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/0, // soffset
        GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/5, // offset
        GIR_CustomOperandRenderer, /*InsnID*/0, /*OldInsnID*/0, /*OpIdx*/6, /*OperandRenderer*/GIMT_Encode2(GICR_renderTruncTImm), // format
        GIR_CustomOperandRenderer, /*InsnID*/0, /*OldInsnID*/0, /*OpIdx*/7, /*OperandRenderer*/GIMT_Encode2(GICR_renderExtractCPol), // auxiliary
        GIR_CustomOperandRenderer, /*InsnID*/0, /*OldInsnID*/0, /*OpIdx*/7, /*OperandRenderer*/GIMT_Encode2(GICR_renderExtractSWZ), // auxiliary
        GIR_MergeMemOperands, /*InsnID*/0, /*NumInsns*/1, /*MergeInsnID's*/0,
        GIR_ConstrainSelectedInstOperands, /*InsnID*/0,
        GIR_EraseFromParent, /*InsnID*/0,
        // GIR_Coverage, 5688,
        GIR_Done,
      // Label 7351: @537327
      GIM_Try, /*On fail goto*//*Label 7352*/ GIMT_Encode4(537451), // Rule ID 5692 //
        GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasPackedD16VMem),
        GIM_CheckRegBankForClass, /*MI*/0, /*Op*/0, /*RC*/GIMT_Encode2(AMDGPU::AV_64RegClassID),
        // MIs[0] offset
        GIM_CheckIsImm, /*MI*/0, /*Op*/5,
        // MIs[0] format
        GIM_CheckIsImm, /*MI*/0, /*Op*/6,
        // MIs[0] auxiliary
        GIM_CheckIsImm, /*MI*/0, /*Op*/7,
        // MIs[0] Operand 8
        GIM_CheckIsImm, /*MI*/0, /*Op*/8,
        GIM_CheckComplexPattern, /*MI*/0, /*Op*/4, /*Renderer*/GIMT_Encode2(0), GIMT_Encode2(GICP_gi_buf_soffset),
        // (SItbuffer_load_d16:{ *:[v4f16] } v4i32:{ *:[v4i32] }:$rsrc, i32:{ *:[i32] }:$vindex, i32:{ *:[i32] }:$voffset, (BUFSOffset:{ *:[i32] } i32:{ *:[i32] }:$soffset), (timm:{ *:[i32] }):$offset, (timm:{ *:[i32] }):$format, (timm:{ *:[i32] }):$auxiliary, (timm:{ *:[i1] }))  =>  (TBUFFER_LOAD_FORMAT_D16_XYZW_VBUFFER_BOTHEN:{ *:[v4f16] } (REG_SEQUENCE:{ *:[i64] } VReg_64:{ *:[i32] }, VGPR_32:{ *:[i32] }:$vindex, sub0:{ *:[i32] }, VGPR_32:{ *:[i32] }:$voffset, sub1:{ *:[i32] }), SReg_128:{ *:[v4i32] }:$rsrc, SCSrc_b32:{ *:[i32] }:$soffset, (timm:{ *:[i32] }):$offset, (as_i8timm:{ *:[i8] } ?:{ *:[i32] }:$format), (extract_cpol:{ *:[i32] } ?:{ *:[i32] }:$auxiliary), (extract_swz:{ *:[i1] } ?:{ *:[i32] }:$auxiliary))
        GIR_MakeTempReg, /*TempRegID*/0, /*TypeID*/GILLT_s64,
        GIR_BuildMI, /*InsnID*/1, /*Opcode*/GIMT_Encode2(TargetOpcode::REG_SEQUENCE),
        GIR_AddTempRegister, /*InsnID*/1, /*TempRegID*/0, /*TempRegFlags*/GIMT_Encode2(RegState::Define),
        GIR_Copy, /*NewInsnID*/1, /*OldInsnID*/0, /*OpIdx*/2, // vindex
        GIR_AddImm8, /*InsnID*/1, /*SubRegIndex*/3,
        GIR_Copy, /*NewInsnID*/1, /*OldInsnID*/0, /*OpIdx*/3, // voffset
        GIR_AddImm8, /*InsnID*/1, /*SubRegIndex*/11,
        GIR_ConstrainOperandRC, /*InsnID*/1, /*Op*/0, GIMT_Encode2(AMDGPU::VReg_64RegClassID),
        GIR_ConstrainOperandRC, /*InsnID*/1, /*Op*/1, GIMT_Encode2(AMDGPU::VGPR_32RegClassID),
        GIR_ConstrainOperandRC, /*InsnID*/1, /*Op*/3, GIMT_Encode2(AMDGPU::VGPR_32RegClassID),
        GIR_BuildMI, /*InsnID*/0, /*Opcode*/GIMT_Encode2(AMDGPU::TBUFFER_LOAD_FORMAT_D16_XYZW_VBUFFER_BOTHEN),
        GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/0, // DstI[vdata]
        GIR_AddSimpleTempRegister, /*InsnID*/0, /*TempRegID*/0,
        GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/1, // rsrc
        GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/0, // soffset
        GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/5, // offset
        GIR_CustomOperandRenderer, /*InsnID*/0, /*OldInsnID*/0, /*OpIdx*/6, /*OperandRenderer*/GIMT_Encode2(GICR_renderTruncTImm), // format
        GIR_CustomOperandRenderer, /*InsnID*/0, /*OldInsnID*/0, /*OpIdx*/7, /*OperandRenderer*/GIMT_Encode2(GICR_renderExtractCPol), // auxiliary
        GIR_CustomOperandRenderer, /*InsnID*/0, /*OldInsnID*/0, /*OpIdx*/7, /*OperandRenderer*/GIMT_Encode2(GICR_renderExtractSWZ), // auxiliary
        GIR_MergeMemOperands, /*InsnID*/0, /*NumInsns*/1, /*MergeInsnID's*/0,
        GIR_ConstrainSelectedInstOperands, /*InsnID*/0,
        GIR_EraseFromParent, /*InsnID*/0,
        // GIR_Coverage, 5692,
        GIR_Done,
      // Label 7352: @537451
      GIM_Reject,
    // Label 7336: @537452
    GIM_Reject,
    // Label 7289: @537453
    GIM_Try, /*On fail goto*//*Label 7353*/ GIMT_Encode4(537864),
      GIM_CheckType, /*MI*/0, /*Op*/1, /*Type*/GILLT_v4s32,
      GIM_CheckType, /*MI*/0, /*Op*/2, /*Type*/GILLT_s32,
      GIM_CheckType, /*MI*/0, /*Op*/3, /*Type*/GILLT_s32,
      GIM_CheckType, /*MI*/0, /*Op*/4, /*Type*/GILLT_s32,
      GIM_CheckRegBankForClass, /*MI*/0, /*Op*/0, /*RC*/GIMT_Encode2(AMDGPU::AV_128RegClassID),
      GIM_Try, /*On fail goto*//*Label 7354*/ GIMT_Encode4(537570), // Rule ID 5649 //
        GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasUnpackedD16VMem),
        GIM_CheckConstantInt8, /*MI*/0, /*Op*/2, 0,
        GIM_CheckConstantInt8, /*MI*/0, /*Op*/3, 0,
        // MIs[0] offset
        GIM_CheckIsImm, /*MI*/0, /*Op*/5,
        // MIs[0] format
        GIM_CheckIsImm, /*MI*/0, /*Op*/6,
        // MIs[0] auxiliary
        GIM_CheckIsImm, /*MI*/0, /*Op*/7,
        // MIs[0] Operand 8
        GIM_CheckLiteralInt, /*MI*/0, /*Op*/8, GIMT_Encode8(0),
        GIM_CheckComplexPattern, /*MI*/0, /*Op*/4, /*Renderer*/GIMT_Encode2(0), GIMT_Encode2(GICP_gi_buf_soffset),
        // (SItbuffer_load_d16:{ *:[v4i32] } v4i32:{ *:[v4i32] }:$rsrc, 0:{ *:[i32] }, 0:{ *:[i32] }, (BUFSOffset:{ *:[i32] } i32:{ *:[i32] }:$soffset), (timm:{ *:[i32] }):$offset, (timm:{ *:[i32] }):$format, (timm:{ *:[i32] }):$auxiliary, 0:{ *:[i1] })  =>  (TBUFFER_LOAD_FORMAT_D16_XYZW_gfx80_OFFSET:{ *:[v4i32] } SReg_128:{ *:[v4i32] }:$rsrc, SCSrc_b32:{ *:[i32] }:$soffset, (timm:{ *:[i32] }):$offset, (as_i8timm:{ *:[i8] } ?:{ *:[i32] }:$format), (extract_cpol:{ *:[i32] } ?:{ *:[i32] }:$auxiliary), (extract_swz:{ *:[i1] } ?:{ *:[i32] }:$auxiliary))
        GIR_BuildMI, /*InsnID*/0, /*Opcode*/GIMT_Encode2(AMDGPU::TBUFFER_LOAD_FORMAT_D16_XYZW_gfx80_OFFSET),
        GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/0, // DstI[vdata]
        GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/1, // rsrc
        GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/0, // soffset
        GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/5, // offset
        GIR_CustomOperandRenderer, /*InsnID*/0, /*OldInsnID*/0, /*OpIdx*/6, /*OperandRenderer*/GIMT_Encode2(GICR_renderTruncTImm), // format
        GIR_CustomOperandRenderer, /*InsnID*/0, /*OldInsnID*/0, /*OpIdx*/7, /*OperandRenderer*/GIMT_Encode2(GICR_renderExtractCPol), // auxiliary
        GIR_CustomOperandRenderer, /*InsnID*/0, /*OldInsnID*/0, /*OpIdx*/7, /*OperandRenderer*/GIMT_Encode2(GICR_renderExtractSWZ), // auxiliary
        GIR_MergeMemOperands, /*InsnID*/0, /*NumInsns*/1, /*MergeInsnID's*/0,
        GIR_ConstrainSelectedInstOperands, /*InsnID*/0,
        GIR_EraseFromParent, /*InsnID*/0,
        // GIR_Coverage, 5649,
        GIR_Done,
      // Label 7354: @537570
      GIM_Try, /*On fail goto*//*Label 7355*/ GIMT_Encode4(537661), // Rule ID 5651 //
        GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasUnpackedD16VMem),
        GIM_CheckConstantInt8, /*MI*/0, /*Op*/2, 0,
        // MIs[0] offset
        GIM_CheckIsImm, /*MI*/0, /*Op*/5,
        // MIs[0] format
        GIM_CheckIsImm, /*MI*/0, /*Op*/6,
        // MIs[0] auxiliary
        GIM_CheckIsImm, /*MI*/0, /*Op*/7,
        // MIs[0] Operand 8
        GIM_CheckLiteralInt, /*MI*/0, /*Op*/8, GIMT_Encode8(0),
        GIM_CheckComplexPattern, /*MI*/0, /*Op*/4, /*Renderer*/GIMT_Encode2(0), GIMT_Encode2(GICP_gi_buf_soffset),
        // (SItbuffer_load_d16:{ *:[v4i32] } v4i32:{ *:[v4i32] }:$rsrc, 0:{ *:[i32] }, i32:{ *:[i32] }:$voffset, (BUFSOffset:{ *:[i32] } i32:{ *:[i32] }:$soffset), (timm:{ *:[i32] }):$offset, (timm:{ *:[i32] }):$format, (timm:{ *:[i32] }):$auxiliary, 0:{ *:[i1] })  =>  (TBUFFER_LOAD_FORMAT_D16_XYZW_gfx80_OFFEN:{ *:[v4i32] } VGPR_32:{ *:[i32] }:$voffset, SReg_128:{ *:[v4i32] }:$rsrc, SCSrc_b32:{ *:[i32] }:$soffset, (timm:{ *:[i32] }):$offset, (as_i8timm:{ *:[i8] } ?:{ *:[i32] }:$format), (extract_cpol:{ *:[i32] } ?:{ *:[i32] }:$auxiliary), (extract_swz:{ *:[i1] } ?:{ *:[i32] }:$auxiliary))
        GIR_BuildMI, /*InsnID*/0, /*Opcode*/GIMT_Encode2(AMDGPU::TBUFFER_LOAD_FORMAT_D16_XYZW_gfx80_OFFEN),
        GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/0, // DstI[vdata]
        GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/3, // voffset
        GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/1, // rsrc
        GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/0, // soffset
        GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/5, // offset
        GIR_CustomOperandRenderer, /*InsnID*/0, /*OldInsnID*/0, /*OpIdx*/6, /*OperandRenderer*/GIMT_Encode2(GICR_renderTruncTImm), // format
        GIR_CustomOperandRenderer, /*InsnID*/0, /*OldInsnID*/0, /*OpIdx*/7, /*OperandRenderer*/GIMT_Encode2(GICR_renderExtractCPol), // auxiliary
        GIR_CustomOperandRenderer, /*InsnID*/0, /*OldInsnID*/0, /*OpIdx*/7, /*OperandRenderer*/GIMT_Encode2(GICR_renderExtractSWZ), // auxiliary
        GIR_MergeMemOperands, /*InsnID*/0, /*NumInsns*/1, /*MergeInsnID's*/0,
        GIR_ConstrainSelectedInstOperands, /*InsnID*/0,
        GIR_EraseFromParent, /*InsnID*/0,
        // GIR_Coverage, 5651,
        GIR_Done,
      // Label 7355: @537661
      GIM_Try, /*On fail goto*//*Label 7356*/ GIMT_Encode4(537744), // Rule ID 5650 //
        GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasUnpackedD16VMem),
        GIM_CheckConstantInt8, /*MI*/0, /*Op*/3, 0,
        // MIs[0] offset
        GIM_CheckIsImm, /*MI*/0, /*Op*/5,
        // MIs[0] format
        GIM_CheckIsImm, /*MI*/0, /*Op*/6,
        // MIs[0] auxiliary
        GIM_CheckIsImm, /*MI*/0, /*Op*/7,
        // MIs[0] Operand 8
        GIM_CheckIsImm, /*MI*/0, /*Op*/8,
        GIM_CheckComplexPattern, /*MI*/0, /*Op*/4, /*Renderer*/GIMT_Encode2(0), GIMT_Encode2(GICP_gi_buf_soffset),
        // (SItbuffer_load_d16:{ *:[v4i32] } v4i32:{ *:[v4i32] }:$rsrc, i32:{ *:[i32] }:$vindex, 0:{ *:[i32] }, (BUFSOffset:{ *:[i32] } i32:{ *:[i32] }:$soffset), (timm:{ *:[i32] }):$offset, (timm:{ *:[i32] }):$format, (timm:{ *:[i32] }):$auxiliary, (timm:{ *:[i1] }))  =>  (TBUFFER_LOAD_FORMAT_D16_XYZW_gfx80_IDXEN:{ *:[v4i32] } VGPR_32:{ *:[i32] }:$vindex, SReg_128:{ *:[v4i32] }:$rsrc, SCSrc_b32:{ *:[i32] }:$soffset, (timm:{ *:[i32] }):$offset, (as_i8timm:{ *:[i8] } ?:{ *:[i32] }:$format), (extract_cpol:{ *:[i32] } ?:{ *:[i32] }:$auxiliary), (extract_swz:{ *:[i1] } ?:{ *:[i32] }:$auxiliary))
        GIR_BuildMI, /*InsnID*/0, /*Opcode*/GIMT_Encode2(AMDGPU::TBUFFER_LOAD_FORMAT_D16_XYZW_gfx80_IDXEN),
        GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/0, // DstI[vdata]
        GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/2, // vindex
        GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/1, // rsrc
        GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/0, // soffset
        GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/5, // offset
        GIR_CustomOperandRenderer, /*InsnID*/0, /*OldInsnID*/0, /*OpIdx*/6, /*OperandRenderer*/GIMT_Encode2(GICR_renderTruncTImm), // format
        GIR_CustomOperandRenderer, /*InsnID*/0, /*OldInsnID*/0, /*OpIdx*/7, /*OperandRenderer*/GIMT_Encode2(GICR_renderExtractCPol), // auxiliary
        GIR_CustomOperandRenderer, /*InsnID*/0, /*OldInsnID*/0, /*OpIdx*/7, /*OperandRenderer*/GIMT_Encode2(GICR_renderExtractSWZ), // auxiliary
        GIR_MergeMemOperands, /*InsnID*/0, /*NumInsns*/1, /*MergeInsnID's*/0,
        GIR_ConstrainSelectedInstOperands, /*InsnID*/0,
        GIR_EraseFromParent, /*InsnID*/0,
        // GIR_Coverage, 5650,
        GIR_Done,
      // Label 7356: @537744
      GIM_Try, /*On fail goto*//*Label 7357*/ GIMT_Encode4(537863), // Rule ID 5652 //
        GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasUnpackedD16VMem),
        // MIs[0] offset
        GIM_CheckIsImm, /*MI*/0, /*Op*/5,
        // MIs[0] format
        GIM_CheckIsImm, /*MI*/0, /*Op*/6,
        // MIs[0] auxiliary
        GIM_CheckIsImm, /*MI*/0, /*Op*/7,
        // MIs[0] Operand 8
        GIM_CheckIsImm, /*MI*/0, /*Op*/8,
        GIM_CheckComplexPattern, /*MI*/0, /*Op*/4, /*Renderer*/GIMT_Encode2(0), GIMT_Encode2(GICP_gi_buf_soffset),
        // (SItbuffer_load_d16:{ *:[v4i32] } v4i32:{ *:[v4i32] }:$rsrc, i32:{ *:[i32] }:$vindex, i32:{ *:[i32] }:$voffset, (BUFSOffset:{ *:[i32] } i32:{ *:[i32] }:$soffset), (timm:{ *:[i32] }):$offset, (timm:{ *:[i32] }):$format, (timm:{ *:[i32] }):$auxiliary, (timm:{ *:[i1] }))  =>  (TBUFFER_LOAD_FORMAT_D16_XYZW_gfx80_BOTHEN:{ *:[v4i32] } (REG_SEQUENCE:{ *:[i64] } VReg_64:{ *:[i32] }, VGPR_32:{ *:[i32] }:$vindex, sub0:{ *:[i32] }, VGPR_32:{ *:[i32] }:$voffset, sub1:{ *:[i32] }), SReg_128:{ *:[v4i32] }:$rsrc, SCSrc_b32:{ *:[i32] }:$soffset, (timm:{ *:[i32] }):$offset, (as_i8timm:{ *:[i8] } ?:{ *:[i32] }:$format), (extract_cpol:{ *:[i32] } ?:{ *:[i32] }:$auxiliary), (extract_swz:{ *:[i1] } ?:{ *:[i32] }:$auxiliary))
        GIR_MakeTempReg, /*TempRegID*/0, /*TypeID*/GILLT_s64,
        GIR_BuildMI, /*InsnID*/1, /*Opcode*/GIMT_Encode2(TargetOpcode::REG_SEQUENCE),
        GIR_AddTempRegister, /*InsnID*/1, /*TempRegID*/0, /*TempRegFlags*/GIMT_Encode2(RegState::Define),
        GIR_Copy, /*NewInsnID*/1, /*OldInsnID*/0, /*OpIdx*/2, // vindex
        GIR_AddImm8, /*InsnID*/1, /*SubRegIndex*/3,
        GIR_Copy, /*NewInsnID*/1, /*OldInsnID*/0, /*OpIdx*/3, // voffset
        GIR_AddImm8, /*InsnID*/1, /*SubRegIndex*/11,
        GIR_ConstrainOperandRC, /*InsnID*/1, /*Op*/0, GIMT_Encode2(AMDGPU::VReg_64RegClassID),
        GIR_ConstrainOperandRC, /*InsnID*/1, /*Op*/1, GIMT_Encode2(AMDGPU::VGPR_32RegClassID),
        GIR_ConstrainOperandRC, /*InsnID*/1, /*Op*/3, GIMT_Encode2(AMDGPU::VGPR_32RegClassID),
        GIR_BuildMI, /*InsnID*/0, /*Opcode*/GIMT_Encode2(AMDGPU::TBUFFER_LOAD_FORMAT_D16_XYZW_gfx80_BOTHEN),
        GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/0, // DstI[vdata]
        GIR_AddSimpleTempRegister, /*InsnID*/0, /*TempRegID*/0,
        GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/1, // rsrc
        GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/0, // soffset
        GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/5, // offset
        GIR_CustomOperandRenderer, /*InsnID*/0, /*OldInsnID*/0, /*OpIdx*/6, /*OperandRenderer*/GIMT_Encode2(GICR_renderTruncTImm), // format
        GIR_CustomOperandRenderer, /*InsnID*/0, /*OldInsnID*/0, /*OpIdx*/7, /*OperandRenderer*/GIMT_Encode2(GICR_renderExtractCPol), // auxiliary
        GIR_CustomOperandRenderer, /*InsnID*/0, /*OldInsnID*/0, /*OpIdx*/7, /*OperandRenderer*/GIMT_Encode2(GICR_renderExtractSWZ), // auxiliary
        GIR_MergeMemOperands, /*InsnID*/0, /*NumInsns*/1, /*MergeInsnID's*/0,
        GIR_ConstrainSelectedInstOperands, /*InsnID*/0,
        GIR_EraseFromParent, /*InsnID*/0,
        // GIR_Coverage, 5652,
        GIR_Done,
      // Label 7357: @537863
      GIM_Reject,
    // Label 7353: @537864
    GIM_Reject,
    // Label 7290: @537865
    GIM_Reject,
    // Label 157: @537866
    GIM_SwitchType, /*MI*/0, /*Op*/0, /*[*/GIMT_Encode2(9), GIMT_Encode2(18), /*)*//*default:*//*Label 7362*/ GIMT_Encode4(544053),
    /*GILLT_s32*//*Label 7358*/ GIMT_Encode4(537913), GIMT_Encode4(0), GIMT_Encode4(0),
    /*GILLT_v2s32*//*Label 7359*/ GIMT_Encode4(539448), GIMT_Encode4(0),
    /*GILLT_v3s32*//*Label 7360*/ GIMT_Encode4(540983), GIMT_Encode4(0), GIMT_Encode4(0),
    /*GILLT_v4s32*//*Label 7361*/ GIMT_Encode4(542518),
    // Label 7358: @537913
    GIM_Try, /*On fail goto*//*Label 7363*/ GIMT_Encode4(539447),
      GIM_CheckType, /*MI*/0, /*Op*/1, /*Type*/GILLT_v4s32,
      GIM_CheckType, /*MI*/0, /*Op*/2, /*Type*/GILLT_s32,
      GIM_CheckType, /*MI*/0, /*Op*/3, /*Type*/GILLT_s32,
      GIM_CheckType, /*MI*/0, /*Op*/4, /*Type*/GILLT_s32,
      GIM_Try, /*On fail goto*//*Label 7364*/ GIMT_Encode4(538025), // Rule ID 5693 //
        GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasUnrestrictedSOffset),
        GIM_CheckConstantInt8, /*MI*/0, /*Op*/2, 0,
        GIM_CheckConstantInt8, /*MI*/0, /*Op*/3, 0,
        // MIs[0] offset
        GIM_CheckIsImm, /*MI*/0, /*Op*/5,
        // MIs[0] format
        GIM_CheckIsImm, /*MI*/0, /*Op*/6,
        // MIs[0] auxiliary
        GIM_CheckIsImm, /*MI*/0, /*Op*/7,
        // MIs[0] Operand 8
        GIM_CheckLiteralInt, /*MI*/0, /*Op*/8, GIMT_Encode8(0),
        GIM_CheckComplexPattern, /*MI*/0, /*Op*/4, /*Renderer*/GIMT_Encode2(0), GIMT_Encode2(GICP_gi_buf_soffset),
        // (SItbuffer_store i32:{ *:[i32] }:$vdata, v4i32:{ *:[v4i32] }:$rsrc, 0:{ *:[i32] }, 0:{ *:[i32] }, (BUFSOffset:{ *:[i32] } i32:{ *:[i32] }:$soffset), (timm:{ *:[i32] }):$offset, (timm:{ *:[i32] }):$format, (timm:{ *:[i32] }):$auxiliary, 0:{ *:[i1] })  =>  (TBUFFER_STORE_FORMAT_X_OFFSET_exact anonymous_15037:{ *:[i32] }:$vdata, SReg_128:{ *:[v4i32] }:$rsrc, SCSrc_b32:{ *:[i32] }:$soffset, (timm:{ *:[i32] }):$offset, (as_i8timm:{ *:[i8] } ?:{ *:[i32] }:$format), (extract_cpol:{ *:[i32] } ?:{ *:[i32] }:$auxiliary), (extract_swz:{ *:[i1] } ?:{ *:[i32] }:$auxiliary))
        GIR_BuildMI, /*InsnID*/0, /*Opcode*/GIMT_Encode2(AMDGPU::TBUFFER_STORE_FORMAT_X_OFFSET_exact),
        GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/0, // vdata
        GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/1, // rsrc
        GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/0, // soffset
        GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/5, // offset
        GIR_CustomOperandRenderer, /*InsnID*/0, /*OldInsnID*/0, /*OpIdx*/6, /*OperandRenderer*/GIMT_Encode2(GICR_renderTruncTImm), // format
        GIR_CustomOperandRenderer, /*InsnID*/0, /*OldInsnID*/0, /*OpIdx*/7, /*OperandRenderer*/GIMT_Encode2(GICR_renderExtractCPol), // auxiliary
        GIR_CustomOperandRenderer, /*InsnID*/0, /*OldInsnID*/0, /*OpIdx*/7, /*OperandRenderer*/GIMT_Encode2(GICR_renderExtractSWZ), // auxiliary
        GIR_MergeMemOperands, /*InsnID*/0, /*NumInsns*/1, /*MergeInsnID's*/0,
        GIR_ConstrainSelectedInstOperands, /*InsnID*/0,
        GIR_EraseFromParent, /*InsnID*/0,
        // GIR_Coverage, 5693,
        GIR_Done,
      // Label 7364: @538025
      GIM_Try, /*On fail goto*//*Label 7365*/ GIMT_Encode4(538113), // Rule ID 5697 //
        GIM_CheckConstantInt8, /*MI*/0, /*Op*/2, 0,
        GIM_CheckConstantInt8, /*MI*/0, /*Op*/3, 0,
        // MIs[0] offset
        GIM_CheckIsImm, /*MI*/0, /*Op*/5,
        // MIs[0] format
        GIM_CheckIsImm, /*MI*/0, /*Op*/6,
        // MIs[0] auxiliary
        GIM_CheckIsImm, /*MI*/0, /*Op*/7,
        // MIs[0] Operand 8
        GIM_CheckLiteralInt, /*MI*/0, /*Op*/8, GIMT_Encode8(0),
        GIM_CheckComplexPattern, /*MI*/0, /*Op*/4, /*Renderer*/GIMT_Encode2(0), GIMT_Encode2(GICP_gi_buf_soffset),
        // (SItbuffer_store i32:{ *:[i32] }:$vdata, v4i32:{ *:[v4i32] }:$rsrc, 0:{ *:[i32] }, 0:{ *:[i32] }, (BUFSOffset:{ *:[i32] } i32:{ *:[i32] }:$soffset), (timm:{ *:[i32] }):$offset, (timm:{ *:[i32] }):$format, (timm:{ *:[i32] }):$auxiliary, 0:{ *:[i1] })  =>  (TBUFFER_STORE_FORMAT_X_VBUFFER_OFFSET_exact anonymous_15037:{ *:[i32] }:$vdata, SReg_128:{ *:[v4i32] }:$rsrc, SCSrc_b32:{ *:[i32] }:$soffset, (timm:{ *:[i32] }):$offset, (as_i8timm:{ *:[i8] } ?:{ *:[i32] }:$format), (extract_cpol:{ *:[i32] } ?:{ *:[i32] }:$auxiliary), (extract_swz:{ *:[i1] } ?:{ *:[i32] }:$auxiliary))
        GIR_BuildMI, /*InsnID*/0, /*Opcode*/GIMT_Encode2(AMDGPU::TBUFFER_STORE_FORMAT_X_VBUFFER_OFFSET_exact),
        GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/0, // vdata
        GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/1, // rsrc
        GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/0, // soffset
        GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/5, // offset
        GIR_CustomOperandRenderer, /*InsnID*/0, /*OldInsnID*/0, /*OpIdx*/6, /*OperandRenderer*/GIMT_Encode2(GICR_renderTruncTImm), // format
        GIR_CustomOperandRenderer, /*InsnID*/0, /*OldInsnID*/0, /*OpIdx*/7, /*OperandRenderer*/GIMT_Encode2(GICR_renderExtractCPol), // auxiliary
        GIR_CustomOperandRenderer, /*InsnID*/0, /*OldInsnID*/0, /*OpIdx*/7, /*OperandRenderer*/GIMT_Encode2(GICR_renderExtractSWZ), // auxiliary
        GIR_MergeMemOperands, /*InsnID*/0, /*NumInsns*/1, /*MergeInsnID's*/0,
        GIR_ConstrainSelectedInstOperands, /*InsnID*/0,
        GIR_EraseFromParent, /*InsnID*/0,
        // GIR_Coverage, 5697,
        GIR_Done,
      // Label 7365: @538113
      GIM_Try, /*On fail goto*//*Label 7366*/ GIMT_Encode4(538204), // Rule ID 5725 //
        GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasUnrestrictedSOffset),
        GIM_CheckConstantInt8, /*MI*/0, /*Op*/2, 0,
        GIM_CheckConstantInt8, /*MI*/0, /*Op*/3, 0,
        // MIs[0] offset
        GIM_CheckIsImm, /*MI*/0, /*Op*/5,
        // MIs[0] format
        GIM_CheckIsImm, /*MI*/0, /*Op*/6,
        // MIs[0] auxiliary
        GIM_CheckIsImm, /*MI*/0, /*Op*/7,
        // MIs[0] Operand 8
        GIM_CheckLiteralInt, /*MI*/0, /*Op*/8, GIMT_Encode8(0),
        GIM_CheckComplexPattern, /*MI*/0, /*Op*/4, /*Renderer*/GIMT_Encode2(0), GIMT_Encode2(GICP_gi_buf_soffset),
        // (SItbuffer_store f32:{ *:[f32] }:$vdata, v4i32:{ *:[v4i32] }:$rsrc, 0:{ *:[i32] }, 0:{ *:[i32] }, (BUFSOffset:{ *:[i32] } i32:{ *:[i32] }:$soffset), (timm:{ *:[i32] }):$offset, (timm:{ *:[i32] }):$format, (timm:{ *:[i32] }):$auxiliary, 0:{ *:[i1] })  =>  (TBUFFER_STORE_FORMAT_X_OFFSET_exact anonymous_15037:{ *:[f32] }:$vdata, SReg_128:{ *:[v4i32] }:$rsrc, SCSrc_b32:{ *:[i32] }:$soffset, (timm:{ *:[i32] }):$offset, (as_i8timm:{ *:[i8] } ?:{ *:[i32] }:$format), (extract_cpol:{ *:[i32] } ?:{ *:[i32] }:$auxiliary), (extract_swz:{ *:[i1] } ?:{ *:[i32] }:$auxiliary))
        GIR_BuildMI, /*InsnID*/0, /*Opcode*/GIMT_Encode2(AMDGPU::TBUFFER_STORE_FORMAT_X_OFFSET_exact),
        GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/0, // vdata
        GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/1, // rsrc
        GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/0, // soffset
        GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/5, // offset
        GIR_CustomOperandRenderer, /*InsnID*/0, /*OldInsnID*/0, /*OpIdx*/6, /*OperandRenderer*/GIMT_Encode2(GICR_renderTruncTImm), // format
        GIR_CustomOperandRenderer, /*InsnID*/0, /*OldInsnID*/0, /*OpIdx*/7, /*OperandRenderer*/GIMT_Encode2(GICR_renderExtractCPol), // auxiliary
        GIR_CustomOperandRenderer, /*InsnID*/0, /*OldInsnID*/0, /*OpIdx*/7, /*OperandRenderer*/GIMT_Encode2(GICR_renderExtractSWZ), // auxiliary
        GIR_MergeMemOperands, /*InsnID*/0, /*NumInsns*/1, /*MergeInsnID's*/0,
        GIR_ConstrainSelectedInstOperands, /*InsnID*/0,
        GIR_EraseFromParent, /*InsnID*/0,
        // GIR_Coverage, 5725,
        GIR_Done,
      // Label 7366: @538204
      GIM_Try, /*On fail goto*//*Label 7367*/ GIMT_Encode4(538292), // Rule ID 5729 //
        GIM_CheckConstantInt8, /*MI*/0, /*Op*/2, 0,
        GIM_CheckConstantInt8, /*MI*/0, /*Op*/3, 0,
        // MIs[0] offset
        GIM_CheckIsImm, /*MI*/0, /*Op*/5,
        // MIs[0] format
        GIM_CheckIsImm, /*MI*/0, /*Op*/6,
        // MIs[0] auxiliary
        GIM_CheckIsImm, /*MI*/0, /*Op*/7,
        // MIs[0] Operand 8
        GIM_CheckLiteralInt, /*MI*/0, /*Op*/8, GIMT_Encode8(0),
        GIM_CheckComplexPattern, /*MI*/0, /*Op*/4, /*Renderer*/GIMT_Encode2(0), GIMT_Encode2(GICP_gi_buf_soffset),
        // (SItbuffer_store f32:{ *:[f32] }:$vdata, v4i32:{ *:[v4i32] }:$rsrc, 0:{ *:[i32] }, 0:{ *:[i32] }, (BUFSOffset:{ *:[i32] } i32:{ *:[i32] }:$soffset), (timm:{ *:[i32] }):$offset, (timm:{ *:[i32] }):$format, (timm:{ *:[i32] }):$auxiliary, 0:{ *:[i1] })  =>  (TBUFFER_STORE_FORMAT_X_VBUFFER_OFFSET_exact anonymous_15037:{ *:[f32] }:$vdata, SReg_128:{ *:[v4i32] }:$rsrc, SCSrc_b32:{ *:[i32] }:$soffset, (timm:{ *:[i32] }):$offset, (as_i8timm:{ *:[i8] } ?:{ *:[i32] }:$format), (extract_cpol:{ *:[i32] } ?:{ *:[i32] }:$auxiliary), (extract_swz:{ *:[i1] } ?:{ *:[i32] }:$auxiliary))
        GIR_BuildMI, /*InsnID*/0, /*Opcode*/GIMT_Encode2(AMDGPU::TBUFFER_STORE_FORMAT_X_VBUFFER_OFFSET_exact),
        GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/0, // vdata
        GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/1, // rsrc
        GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/0, // soffset
        GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/5, // offset
        GIR_CustomOperandRenderer, /*InsnID*/0, /*OldInsnID*/0, /*OpIdx*/6, /*OperandRenderer*/GIMT_Encode2(GICR_renderTruncTImm), // format
        GIR_CustomOperandRenderer, /*InsnID*/0, /*OldInsnID*/0, /*OpIdx*/7, /*OperandRenderer*/GIMT_Encode2(GICR_renderExtractCPol), // auxiliary
        GIR_CustomOperandRenderer, /*InsnID*/0, /*OldInsnID*/0, /*OpIdx*/7, /*OperandRenderer*/GIMT_Encode2(GICR_renderExtractSWZ), // auxiliary
        GIR_MergeMemOperands, /*InsnID*/0, /*NumInsns*/1, /*MergeInsnID's*/0,
        GIR_ConstrainSelectedInstOperands, /*InsnID*/0,
        GIR_EraseFromParent, /*InsnID*/0,
        // GIR_Coverage, 5729,
        GIR_Done,
      // Label 7367: @538292
      GIM_Try, /*On fail goto*//*Label 7368*/ GIMT_Encode4(538383), // Rule ID 5695 //
        GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasUnrestrictedSOffset),
        GIM_CheckConstantInt8, /*MI*/0, /*Op*/2, 0,
        // MIs[0] offset
        GIM_CheckIsImm, /*MI*/0, /*Op*/5,
        // MIs[0] format
        GIM_CheckIsImm, /*MI*/0, /*Op*/6,
        // MIs[0] auxiliary
        GIM_CheckIsImm, /*MI*/0, /*Op*/7,
        // MIs[0] Operand 8
        GIM_CheckLiteralInt, /*MI*/0, /*Op*/8, GIMT_Encode8(0),
        GIM_CheckComplexPattern, /*MI*/0, /*Op*/4, /*Renderer*/GIMT_Encode2(0), GIMT_Encode2(GICP_gi_buf_soffset),
        // (SItbuffer_store i32:{ *:[i32] }:$vdata, v4i32:{ *:[v4i32] }:$rsrc, 0:{ *:[i32] }, i32:{ *:[i32] }:$voffset, (BUFSOffset:{ *:[i32] } i32:{ *:[i32] }:$soffset), (timm:{ *:[i32] }):$offset, (timm:{ *:[i32] }):$format, (timm:{ *:[i32] }):$auxiliary, 0:{ *:[i1] })  =>  (TBUFFER_STORE_FORMAT_X_OFFEN_exact anonymous_15037:{ *:[i32] }:$vdata, VGPR_32:{ *:[i32] }:$voffset, SReg_128:{ *:[v4i32] }:$rsrc, SCSrc_b32:{ *:[i32] }:$soffset, (timm:{ *:[i32] }):$offset, (as_i8timm:{ *:[i8] } ?:{ *:[i32] }:$format), (extract_cpol:{ *:[i32] } ?:{ *:[i32] }:$auxiliary), (extract_swz:{ *:[i1] } ?:{ *:[i32] }:$auxiliary))
        GIR_BuildMI, /*InsnID*/0, /*Opcode*/GIMT_Encode2(AMDGPU::TBUFFER_STORE_FORMAT_X_OFFEN_exact),
        GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/0, // vdata
        GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/3, // voffset
        GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/1, // rsrc
        GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/0, // soffset
        GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/5, // offset
        GIR_CustomOperandRenderer, /*InsnID*/0, /*OldInsnID*/0, /*OpIdx*/6, /*OperandRenderer*/GIMT_Encode2(GICR_renderTruncTImm), // format
        GIR_CustomOperandRenderer, /*InsnID*/0, /*OldInsnID*/0, /*OpIdx*/7, /*OperandRenderer*/GIMT_Encode2(GICR_renderExtractCPol), // auxiliary
        GIR_CustomOperandRenderer, /*InsnID*/0, /*OldInsnID*/0, /*OpIdx*/7, /*OperandRenderer*/GIMT_Encode2(GICR_renderExtractSWZ), // auxiliary
        GIR_MergeMemOperands, /*InsnID*/0, /*NumInsns*/1, /*MergeInsnID's*/0,
        GIR_ConstrainSelectedInstOperands, /*InsnID*/0,
        GIR_EraseFromParent, /*InsnID*/0,
        // GIR_Coverage, 5695,
        GIR_Done,
      // Label 7368: @538383
      GIM_Try, /*On fail goto*//*Label 7369*/ GIMT_Encode4(538471), // Rule ID 5699 //
        GIM_CheckConstantInt8, /*MI*/0, /*Op*/2, 0,
        // MIs[0] offset
        GIM_CheckIsImm, /*MI*/0, /*Op*/5,
        // MIs[0] format
        GIM_CheckIsImm, /*MI*/0, /*Op*/6,
        // MIs[0] auxiliary
        GIM_CheckIsImm, /*MI*/0, /*Op*/7,
        // MIs[0] Operand 8
        GIM_CheckLiteralInt, /*MI*/0, /*Op*/8, GIMT_Encode8(0),
        GIM_CheckComplexPattern, /*MI*/0, /*Op*/4, /*Renderer*/GIMT_Encode2(0), GIMT_Encode2(GICP_gi_buf_soffset),
        // (SItbuffer_store i32:{ *:[i32] }:$vdata, v4i32:{ *:[v4i32] }:$rsrc, 0:{ *:[i32] }, i32:{ *:[i32] }:$voffset, (BUFSOffset:{ *:[i32] } i32:{ *:[i32] }:$soffset), (timm:{ *:[i32] }):$offset, (timm:{ *:[i32] }):$format, (timm:{ *:[i32] }):$auxiliary, 0:{ *:[i1] })  =>  (TBUFFER_STORE_FORMAT_X_VBUFFER_OFFEN_exact anonymous_15037:{ *:[i32] }:$vdata, VGPR_32:{ *:[i32] }:$voffset, SReg_128:{ *:[v4i32] }:$rsrc, SCSrc_b32:{ *:[i32] }:$soffset, (timm:{ *:[i32] }):$offset, (as_i8timm:{ *:[i8] } ?:{ *:[i32] }:$format), (extract_cpol:{ *:[i32] } ?:{ *:[i32] }:$auxiliary), (extract_swz:{ *:[i1] } ?:{ *:[i32] }:$auxiliary))
        GIR_BuildMI, /*InsnID*/0, /*Opcode*/GIMT_Encode2(AMDGPU::TBUFFER_STORE_FORMAT_X_VBUFFER_OFFEN_exact),
        GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/0, // vdata
        GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/3, // voffset
        GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/1, // rsrc
        GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/0, // soffset
        GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/5, // offset
        GIR_CustomOperandRenderer, /*InsnID*/0, /*OldInsnID*/0, /*OpIdx*/6, /*OperandRenderer*/GIMT_Encode2(GICR_renderTruncTImm), // format
        GIR_CustomOperandRenderer, /*InsnID*/0, /*OldInsnID*/0, /*OpIdx*/7, /*OperandRenderer*/GIMT_Encode2(GICR_renderExtractCPol), // auxiliary
        GIR_CustomOperandRenderer, /*InsnID*/0, /*OldInsnID*/0, /*OpIdx*/7, /*OperandRenderer*/GIMT_Encode2(GICR_renderExtractSWZ), // auxiliary
        GIR_MergeMemOperands, /*InsnID*/0, /*NumInsns*/1, /*MergeInsnID's*/0,
        GIR_ConstrainSelectedInstOperands, /*InsnID*/0,
        GIR_EraseFromParent, /*InsnID*/0,
        // GIR_Coverage, 5699,
        GIR_Done,
      // Label 7369: @538471
      GIM_Try, /*On fail goto*//*Label 7370*/ GIMT_Encode4(538562), // Rule ID 5727 //
        GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasUnrestrictedSOffset),
        GIM_CheckConstantInt8, /*MI*/0, /*Op*/2, 0,
        // MIs[0] offset
        GIM_CheckIsImm, /*MI*/0, /*Op*/5,
        // MIs[0] format
        GIM_CheckIsImm, /*MI*/0, /*Op*/6,
        // MIs[0] auxiliary
        GIM_CheckIsImm, /*MI*/0, /*Op*/7,
        // MIs[0] Operand 8
        GIM_CheckLiteralInt, /*MI*/0, /*Op*/8, GIMT_Encode8(0),
        GIM_CheckComplexPattern, /*MI*/0, /*Op*/4, /*Renderer*/GIMT_Encode2(0), GIMT_Encode2(GICP_gi_buf_soffset),
        // (SItbuffer_store f32:{ *:[f32] }:$vdata, v4i32:{ *:[v4i32] }:$rsrc, 0:{ *:[i32] }, i32:{ *:[i32] }:$voffset, (BUFSOffset:{ *:[i32] } i32:{ *:[i32] }:$soffset), (timm:{ *:[i32] }):$offset, (timm:{ *:[i32] }):$format, (timm:{ *:[i32] }):$auxiliary, 0:{ *:[i1] })  =>  (TBUFFER_STORE_FORMAT_X_OFFEN_exact anonymous_15037:{ *:[f32] }:$vdata, VGPR_32:{ *:[i32] }:$voffset, SReg_128:{ *:[v4i32] }:$rsrc, SCSrc_b32:{ *:[i32] }:$soffset, (timm:{ *:[i32] }):$offset, (as_i8timm:{ *:[i8] } ?:{ *:[i32] }:$format), (extract_cpol:{ *:[i32] } ?:{ *:[i32] }:$auxiliary), (extract_swz:{ *:[i1] } ?:{ *:[i32] }:$auxiliary))
        GIR_BuildMI, /*InsnID*/0, /*Opcode*/GIMT_Encode2(AMDGPU::TBUFFER_STORE_FORMAT_X_OFFEN_exact),
        GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/0, // vdata
        GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/3, // voffset
        GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/1, // rsrc
        GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/0, // soffset
        GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/5, // offset
        GIR_CustomOperandRenderer, /*InsnID*/0, /*OldInsnID*/0, /*OpIdx*/6, /*OperandRenderer*/GIMT_Encode2(GICR_renderTruncTImm), // format
        GIR_CustomOperandRenderer, /*InsnID*/0, /*OldInsnID*/0, /*OpIdx*/7, /*OperandRenderer*/GIMT_Encode2(GICR_renderExtractCPol), // auxiliary
        GIR_CustomOperandRenderer, /*InsnID*/0, /*OldInsnID*/0, /*OpIdx*/7, /*OperandRenderer*/GIMT_Encode2(GICR_renderExtractSWZ), // auxiliary
        GIR_MergeMemOperands, /*InsnID*/0, /*NumInsns*/1, /*MergeInsnID's*/0,
        GIR_ConstrainSelectedInstOperands, /*InsnID*/0,
        GIR_EraseFromParent, /*InsnID*/0,
        // GIR_Coverage, 5727,
        GIR_Done,
      // Label 7370: @538562
      GIM_Try, /*On fail goto*//*Label 7371*/ GIMT_Encode4(538650), // Rule ID 5731 //
        GIM_CheckConstantInt8, /*MI*/0, /*Op*/2, 0,
        // MIs[0] offset
        GIM_CheckIsImm, /*MI*/0, /*Op*/5,
        // MIs[0] format
        GIM_CheckIsImm, /*MI*/0, /*Op*/6,
        // MIs[0] auxiliary
        GIM_CheckIsImm, /*MI*/0, /*Op*/7,
        // MIs[0] Operand 8
        GIM_CheckLiteralInt, /*MI*/0, /*Op*/8, GIMT_Encode8(0),
        GIM_CheckComplexPattern, /*MI*/0, /*Op*/4, /*Renderer*/GIMT_Encode2(0), GIMT_Encode2(GICP_gi_buf_soffset),
        // (SItbuffer_store f32:{ *:[f32] }:$vdata, v4i32:{ *:[v4i32] }:$rsrc, 0:{ *:[i32] }, i32:{ *:[i32] }:$voffset, (BUFSOffset:{ *:[i32] } i32:{ *:[i32] }:$soffset), (timm:{ *:[i32] }):$offset, (timm:{ *:[i32] }):$format, (timm:{ *:[i32] }):$auxiliary, 0:{ *:[i1] })  =>  (TBUFFER_STORE_FORMAT_X_VBUFFER_OFFEN_exact anonymous_15037:{ *:[f32] }:$vdata, VGPR_32:{ *:[i32] }:$voffset, SReg_128:{ *:[v4i32] }:$rsrc, SCSrc_b32:{ *:[i32] }:$soffset, (timm:{ *:[i32] }):$offset, (as_i8timm:{ *:[i8] } ?:{ *:[i32] }:$format), (extract_cpol:{ *:[i32] } ?:{ *:[i32] }:$auxiliary), (extract_swz:{ *:[i1] } ?:{ *:[i32] }:$auxiliary))
        GIR_BuildMI, /*InsnID*/0, /*Opcode*/GIMT_Encode2(AMDGPU::TBUFFER_STORE_FORMAT_X_VBUFFER_OFFEN_exact),
        GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/0, // vdata
        GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/3, // voffset
        GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/1, // rsrc
        GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/0, // soffset
        GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/5, // offset
        GIR_CustomOperandRenderer, /*InsnID*/0, /*OldInsnID*/0, /*OpIdx*/6, /*OperandRenderer*/GIMT_Encode2(GICR_renderTruncTImm), // format
        GIR_CustomOperandRenderer, /*InsnID*/0, /*OldInsnID*/0, /*OpIdx*/7, /*OperandRenderer*/GIMT_Encode2(GICR_renderExtractCPol), // auxiliary
        GIR_CustomOperandRenderer, /*InsnID*/0, /*OldInsnID*/0, /*OpIdx*/7, /*OperandRenderer*/GIMT_Encode2(GICR_renderExtractSWZ), // auxiliary
        GIR_MergeMemOperands, /*InsnID*/0, /*NumInsns*/1, /*MergeInsnID's*/0,
        GIR_ConstrainSelectedInstOperands, /*InsnID*/0,
        GIR_EraseFromParent, /*InsnID*/0,
        // GIR_Coverage, 5731,
        GIR_Done,
      // Label 7371: @538650
      GIM_Try, /*On fail goto*//*Label 7372*/ GIMT_Encode4(538733), // Rule ID 5694 //
        GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasUnrestrictedSOffset),
        GIM_CheckConstantInt8, /*MI*/0, /*Op*/3, 0,
        // MIs[0] offset
        GIM_CheckIsImm, /*MI*/0, /*Op*/5,
        // MIs[0] format
        GIM_CheckIsImm, /*MI*/0, /*Op*/6,
        // MIs[0] auxiliary
        GIM_CheckIsImm, /*MI*/0, /*Op*/7,
        // MIs[0] Operand 8
        GIM_CheckIsImm, /*MI*/0, /*Op*/8,
        GIM_CheckComplexPattern, /*MI*/0, /*Op*/4, /*Renderer*/GIMT_Encode2(0), GIMT_Encode2(GICP_gi_buf_soffset),
        // (SItbuffer_store i32:{ *:[i32] }:$vdata, v4i32:{ *:[v4i32] }:$rsrc, i32:{ *:[i32] }:$vindex, 0:{ *:[i32] }, (BUFSOffset:{ *:[i32] } i32:{ *:[i32] }:$soffset), (timm:{ *:[i32] }):$offset, (timm:{ *:[i32] }):$format, (timm:{ *:[i32] }):$auxiliary, (timm:{ *:[i1] }))  =>  (TBUFFER_STORE_FORMAT_X_IDXEN_exact anonymous_15037:{ *:[i32] }:$vdata, VGPR_32:{ *:[i32] }:$vindex, SReg_128:{ *:[v4i32] }:$rsrc, SCSrc_b32:{ *:[i32] }:$soffset, (timm:{ *:[i32] }):$offset, (as_i8timm:{ *:[i8] } ?:{ *:[i32] }:$format), (extract_cpol:{ *:[i32] } ?:{ *:[i32] }:$auxiliary), (extract_swz:{ *:[i1] } ?:{ *:[i32] }:$auxiliary))
        GIR_BuildMI, /*InsnID*/0, /*Opcode*/GIMT_Encode2(AMDGPU::TBUFFER_STORE_FORMAT_X_IDXEN_exact),
        GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/0, // vdata
        GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/2, // vindex
        GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/1, // rsrc
        GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/0, // soffset
        GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/5, // offset
        GIR_CustomOperandRenderer, /*InsnID*/0, /*OldInsnID*/0, /*OpIdx*/6, /*OperandRenderer*/GIMT_Encode2(GICR_renderTruncTImm), // format
        GIR_CustomOperandRenderer, /*InsnID*/0, /*OldInsnID*/0, /*OpIdx*/7, /*OperandRenderer*/GIMT_Encode2(GICR_renderExtractCPol), // auxiliary
        GIR_CustomOperandRenderer, /*InsnID*/0, /*OldInsnID*/0, /*OpIdx*/7, /*OperandRenderer*/GIMT_Encode2(GICR_renderExtractSWZ), // auxiliary
        GIR_MergeMemOperands, /*InsnID*/0, /*NumInsns*/1, /*MergeInsnID's*/0,
        GIR_ConstrainSelectedInstOperands, /*InsnID*/0,
        GIR_EraseFromParent, /*InsnID*/0,
        // GIR_Coverage, 5694,
        GIR_Done,
      // Label 7372: @538733
      GIM_Try, /*On fail goto*//*Label 7373*/ GIMT_Encode4(538813), // Rule ID 5698 //
        GIM_CheckConstantInt8, /*MI*/0, /*Op*/3, 0,
        // MIs[0] offset
        GIM_CheckIsImm, /*MI*/0, /*Op*/5,
        // MIs[0] format
        GIM_CheckIsImm, /*MI*/0, /*Op*/6,
        // MIs[0] auxiliary
        GIM_CheckIsImm, /*MI*/0, /*Op*/7,
        // MIs[0] Operand 8
        GIM_CheckIsImm, /*MI*/0, /*Op*/8,
        GIM_CheckComplexPattern, /*MI*/0, /*Op*/4, /*Renderer*/GIMT_Encode2(0), GIMT_Encode2(GICP_gi_buf_soffset),
        // (SItbuffer_store i32:{ *:[i32] }:$vdata, v4i32:{ *:[v4i32] }:$rsrc, i32:{ *:[i32] }:$vindex, 0:{ *:[i32] }, (BUFSOffset:{ *:[i32] } i32:{ *:[i32] }:$soffset), (timm:{ *:[i32] }):$offset, (timm:{ *:[i32] }):$format, (timm:{ *:[i32] }):$auxiliary, (timm:{ *:[i1] }))  =>  (TBUFFER_STORE_FORMAT_X_VBUFFER_IDXEN_exact anonymous_15037:{ *:[i32] }:$vdata, VGPR_32:{ *:[i32] }:$vindex, SReg_128:{ *:[v4i32] }:$rsrc, SCSrc_b32:{ *:[i32] }:$soffset, (timm:{ *:[i32] }):$offset, (as_i8timm:{ *:[i8] } ?:{ *:[i32] }:$format), (extract_cpol:{ *:[i32] } ?:{ *:[i32] }:$auxiliary), (extract_swz:{ *:[i1] } ?:{ *:[i32] }:$auxiliary))
        GIR_BuildMI, /*InsnID*/0, /*Opcode*/GIMT_Encode2(AMDGPU::TBUFFER_STORE_FORMAT_X_VBUFFER_IDXEN_exact),
        GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/0, // vdata
        GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/2, // vindex
        GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/1, // rsrc
        GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/0, // soffset
        GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/5, // offset
        GIR_CustomOperandRenderer, /*InsnID*/0, /*OldInsnID*/0, /*OpIdx*/6, /*OperandRenderer*/GIMT_Encode2(GICR_renderTruncTImm), // format
        GIR_CustomOperandRenderer, /*InsnID*/0, /*OldInsnID*/0, /*OpIdx*/7, /*OperandRenderer*/GIMT_Encode2(GICR_renderExtractCPol), // auxiliary
        GIR_CustomOperandRenderer, /*InsnID*/0, /*OldInsnID*/0, /*OpIdx*/7, /*OperandRenderer*/GIMT_Encode2(GICR_renderExtractSWZ), // auxiliary
        GIR_MergeMemOperands, /*InsnID*/0, /*NumInsns*/1, /*MergeInsnID's*/0,
        GIR_ConstrainSelectedInstOperands, /*InsnID*/0,
        GIR_EraseFromParent, /*InsnID*/0,
        // GIR_Coverage, 5698,
        GIR_Done,
      // Label 7373: @538813
      GIM_Try, /*On fail goto*//*Label 7374*/ GIMT_Encode4(538896), // Rule ID 5726 //
        GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasUnrestrictedSOffset),
        GIM_CheckConstantInt8, /*MI*/0, /*Op*/3, 0,
        // MIs[0] offset
        GIM_CheckIsImm, /*MI*/0, /*Op*/5,
        // MIs[0] format
        GIM_CheckIsImm, /*MI*/0, /*Op*/6,
        // MIs[0] auxiliary
        GIM_CheckIsImm, /*MI*/0, /*Op*/7,
        // MIs[0] Operand 8
        GIM_CheckIsImm, /*MI*/0, /*Op*/8,
        GIM_CheckComplexPattern, /*MI*/0, /*Op*/4, /*Renderer*/GIMT_Encode2(0), GIMT_Encode2(GICP_gi_buf_soffset),
        // (SItbuffer_store f32:{ *:[f32] }:$vdata, v4i32:{ *:[v4i32] }:$rsrc, i32:{ *:[i32] }:$vindex, 0:{ *:[i32] }, (BUFSOffset:{ *:[i32] } i32:{ *:[i32] }:$soffset), (timm:{ *:[i32] }):$offset, (timm:{ *:[i32] }):$format, (timm:{ *:[i32] }):$auxiliary, (timm:{ *:[i1] }))  =>  (TBUFFER_STORE_FORMAT_X_IDXEN_exact anonymous_15037:{ *:[f32] }:$vdata, VGPR_32:{ *:[i32] }:$vindex, SReg_128:{ *:[v4i32] }:$rsrc, SCSrc_b32:{ *:[i32] }:$soffset, (timm:{ *:[i32] }):$offset, (as_i8timm:{ *:[i8] } ?:{ *:[i32] }:$format), (extract_cpol:{ *:[i32] } ?:{ *:[i32] }:$auxiliary), (extract_swz:{ *:[i1] } ?:{ *:[i32] }:$auxiliary))
        GIR_BuildMI, /*InsnID*/0, /*Opcode*/GIMT_Encode2(AMDGPU::TBUFFER_STORE_FORMAT_X_IDXEN_exact),
        GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/0, // vdata
        GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/2, // vindex
        GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/1, // rsrc
        GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/0, // soffset
        GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/5, // offset
        GIR_CustomOperandRenderer, /*InsnID*/0, /*OldInsnID*/0, /*OpIdx*/6, /*OperandRenderer*/GIMT_Encode2(GICR_renderTruncTImm), // format
        GIR_CustomOperandRenderer, /*InsnID*/0, /*OldInsnID*/0, /*OpIdx*/7, /*OperandRenderer*/GIMT_Encode2(GICR_renderExtractCPol), // auxiliary
        GIR_CustomOperandRenderer, /*InsnID*/0, /*OldInsnID*/0, /*OpIdx*/7, /*OperandRenderer*/GIMT_Encode2(GICR_renderExtractSWZ), // auxiliary
        GIR_MergeMemOperands, /*InsnID*/0, /*NumInsns*/1, /*MergeInsnID's*/0,
        GIR_ConstrainSelectedInstOperands, /*InsnID*/0,
        GIR_EraseFromParent, /*InsnID*/0,
        // GIR_Coverage, 5726,
        GIR_Done,
      // Label 7374: @538896
      GIM_Try, /*On fail goto*//*Label 7375*/ GIMT_Encode4(538976), // Rule ID 5730 //
        GIM_CheckConstantInt8, /*MI*/0, /*Op*/3, 0,
        // MIs[0] offset
        GIM_CheckIsImm, /*MI*/0, /*Op*/5,
        // MIs[0] format
        GIM_CheckIsImm, /*MI*/0, /*Op*/6,
        // MIs[0] auxiliary
        GIM_CheckIsImm, /*MI*/0, /*Op*/7,
        // MIs[0] Operand 8
        GIM_CheckIsImm, /*MI*/0, /*Op*/8,
        GIM_CheckComplexPattern, /*MI*/0, /*Op*/4, /*Renderer*/GIMT_Encode2(0), GIMT_Encode2(GICP_gi_buf_soffset),
        // (SItbuffer_store f32:{ *:[f32] }:$vdata, v4i32:{ *:[v4i32] }:$rsrc, i32:{ *:[i32] }:$vindex, 0:{ *:[i32] }, (BUFSOffset:{ *:[i32] } i32:{ *:[i32] }:$soffset), (timm:{ *:[i32] }):$offset, (timm:{ *:[i32] }):$format, (timm:{ *:[i32] }):$auxiliary, (timm:{ *:[i1] }))  =>  (TBUFFER_STORE_FORMAT_X_VBUFFER_IDXEN_exact anonymous_15037:{ *:[f32] }:$vdata, VGPR_32:{ *:[i32] }:$vindex, SReg_128:{ *:[v4i32] }:$rsrc, SCSrc_b32:{ *:[i32] }:$soffset, (timm:{ *:[i32] }):$offset, (as_i8timm:{ *:[i8] } ?:{ *:[i32] }:$format), (extract_cpol:{ *:[i32] } ?:{ *:[i32] }:$auxiliary), (extract_swz:{ *:[i1] } ?:{ *:[i32] }:$auxiliary))
        GIR_BuildMI, /*InsnID*/0, /*Opcode*/GIMT_Encode2(AMDGPU::TBUFFER_STORE_FORMAT_X_VBUFFER_IDXEN_exact),
        GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/0, // vdata
        GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/2, // vindex
        GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/1, // rsrc
        GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/0, // soffset
        GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/5, // offset
        GIR_CustomOperandRenderer, /*InsnID*/0, /*OldInsnID*/0, /*OpIdx*/6, /*OperandRenderer*/GIMT_Encode2(GICR_renderTruncTImm), // format
        GIR_CustomOperandRenderer, /*InsnID*/0, /*OldInsnID*/0, /*OpIdx*/7, /*OperandRenderer*/GIMT_Encode2(GICR_renderExtractCPol), // auxiliary
        GIR_CustomOperandRenderer, /*InsnID*/0, /*OldInsnID*/0, /*OpIdx*/7, /*OperandRenderer*/GIMT_Encode2(GICR_renderExtractSWZ), // auxiliary
        GIR_MergeMemOperands, /*InsnID*/0, /*NumInsns*/1, /*MergeInsnID's*/0,
        GIR_ConstrainSelectedInstOperands, /*InsnID*/0,
        GIR_EraseFromParent, /*InsnID*/0,
        // GIR_Coverage, 5730,
        GIR_Done,
      // Label 7375: @538976
      GIM_Try, /*On fail goto*//*Label 7376*/ GIMT_Encode4(539095), // Rule ID 5696 //
        GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasUnrestrictedSOffset),
        // MIs[0] offset
        GIM_CheckIsImm, /*MI*/0, /*Op*/5,
        // MIs[0] format
        GIM_CheckIsImm, /*MI*/0, /*Op*/6,
        // MIs[0] auxiliary
        GIM_CheckIsImm, /*MI*/0, /*Op*/7,
        // MIs[0] Operand 8
        GIM_CheckIsImm, /*MI*/0, /*Op*/8,
        GIM_CheckComplexPattern, /*MI*/0, /*Op*/4, /*Renderer*/GIMT_Encode2(0), GIMT_Encode2(GICP_gi_buf_soffset),
        // (SItbuffer_store i32:{ *:[i32] }:$vdata, v4i32:{ *:[v4i32] }:$rsrc, i32:{ *:[i32] }:$vindex, i32:{ *:[i32] }:$voffset, (BUFSOffset:{ *:[i32] } i32:{ *:[i32] }:$soffset), (timm:{ *:[i32] }):$offset, (timm:{ *:[i32] }):$format, (timm:{ *:[i32] }):$auxiliary, (timm:{ *:[i1] }))  =>  (TBUFFER_STORE_FORMAT_X_BOTHEN_exact anonymous_15037:{ *:[i32] }:$vdata, (REG_SEQUENCE:{ *:[i64] } VReg_64:{ *:[i32] }, VGPR_32:{ *:[i32] }:$vindex, sub0:{ *:[i32] }, VGPR_32:{ *:[i32] }:$voffset, sub1:{ *:[i32] }), SReg_128:{ *:[v4i32] }:$rsrc, SCSrc_b32:{ *:[i32] }:$soffset, (timm:{ *:[i32] }):$offset, (as_i8timm:{ *:[i8] } ?:{ *:[i32] }:$format), (extract_cpol:{ *:[i32] } ?:{ *:[i32] }:$auxiliary), (extract_swz:{ *:[i1] } ?:{ *:[i32] }:$auxiliary))
        GIR_MakeTempReg, /*TempRegID*/0, /*TypeID*/GILLT_s64,
        GIR_BuildMI, /*InsnID*/1, /*Opcode*/GIMT_Encode2(TargetOpcode::REG_SEQUENCE),
        GIR_AddTempRegister, /*InsnID*/1, /*TempRegID*/0, /*TempRegFlags*/GIMT_Encode2(RegState::Define),
        GIR_Copy, /*NewInsnID*/1, /*OldInsnID*/0, /*OpIdx*/2, // vindex
        GIR_AddImm8, /*InsnID*/1, /*SubRegIndex*/3,
        GIR_Copy, /*NewInsnID*/1, /*OldInsnID*/0, /*OpIdx*/3, // voffset
        GIR_AddImm8, /*InsnID*/1, /*SubRegIndex*/11,
        GIR_ConstrainOperandRC, /*InsnID*/1, /*Op*/0, GIMT_Encode2(AMDGPU::VReg_64RegClassID),
        GIR_ConstrainOperandRC, /*InsnID*/1, /*Op*/1, GIMT_Encode2(AMDGPU::VGPR_32RegClassID),
        GIR_ConstrainOperandRC, /*InsnID*/1, /*Op*/3, GIMT_Encode2(AMDGPU::VGPR_32RegClassID),
        GIR_BuildMI, /*InsnID*/0, /*Opcode*/GIMT_Encode2(AMDGPU::TBUFFER_STORE_FORMAT_X_BOTHEN_exact),
        GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/0, // vdata
        GIR_AddSimpleTempRegister, /*InsnID*/0, /*TempRegID*/0,
        GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/1, // rsrc
        GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/0, // soffset
        GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/5, // offset
        GIR_CustomOperandRenderer, /*InsnID*/0, /*OldInsnID*/0, /*OpIdx*/6, /*OperandRenderer*/GIMT_Encode2(GICR_renderTruncTImm), // format
        GIR_CustomOperandRenderer, /*InsnID*/0, /*OldInsnID*/0, /*OpIdx*/7, /*OperandRenderer*/GIMT_Encode2(GICR_renderExtractCPol), // auxiliary
        GIR_CustomOperandRenderer, /*InsnID*/0, /*OldInsnID*/0, /*OpIdx*/7, /*OperandRenderer*/GIMT_Encode2(GICR_renderExtractSWZ), // auxiliary
        GIR_MergeMemOperands, /*InsnID*/0, /*NumInsns*/1, /*MergeInsnID's*/0,
        GIR_ConstrainSelectedInstOperands, /*InsnID*/0,
        GIR_EraseFromParent, /*InsnID*/0,
        // GIR_Coverage, 5696,
        GIR_Done,
      // Label 7376: @539095
      GIM_Try, /*On fail goto*//*Label 7377*/ GIMT_Encode4(539211), // Rule ID 5700 //
        // MIs[0] offset
        GIM_CheckIsImm, /*MI*/0, /*Op*/5,
        // MIs[0] format
        GIM_CheckIsImm, /*MI*/0, /*Op*/6,
        // MIs[0] auxiliary
        GIM_CheckIsImm, /*MI*/0, /*Op*/7,
        // MIs[0] Operand 8
        GIM_CheckIsImm, /*MI*/0, /*Op*/8,
        GIM_CheckComplexPattern, /*MI*/0, /*Op*/4, /*Renderer*/GIMT_Encode2(0), GIMT_Encode2(GICP_gi_buf_soffset),
        // (SItbuffer_store i32:{ *:[i32] }:$vdata, v4i32:{ *:[v4i32] }:$rsrc, i32:{ *:[i32] }:$vindex, i32:{ *:[i32] }:$voffset, (BUFSOffset:{ *:[i32] } i32:{ *:[i32] }:$soffset), (timm:{ *:[i32] }):$offset, (timm:{ *:[i32] }):$format, (timm:{ *:[i32] }):$auxiliary, (timm:{ *:[i1] }))  =>  (TBUFFER_STORE_FORMAT_X_VBUFFER_BOTHEN_exact anonymous_15037:{ *:[i32] }:$vdata, (REG_SEQUENCE:{ *:[i64] } VReg_64:{ *:[i32] }, VGPR_32:{ *:[i32] }:$vindex, sub0:{ *:[i32] }, VGPR_32:{ *:[i32] }:$voffset, sub1:{ *:[i32] }), SReg_128:{ *:[v4i32] }:$rsrc, SCSrc_b32:{ *:[i32] }:$soffset, (timm:{ *:[i32] }):$offset, (as_i8timm:{ *:[i8] } ?:{ *:[i32] }:$format), (extract_cpol:{ *:[i32] } ?:{ *:[i32] }:$auxiliary), (extract_swz:{ *:[i1] } ?:{ *:[i32] }:$auxiliary))
        GIR_MakeTempReg, /*TempRegID*/0, /*TypeID*/GILLT_s64,
        GIR_BuildMI, /*InsnID*/1, /*Opcode*/GIMT_Encode2(TargetOpcode::REG_SEQUENCE),
        GIR_AddTempRegister, /*InsnID*/1, /*TempRegID*/0, /*TempRegFlags*/GIMT_Encode2(RegState::Define),
        GIR_Copy, /*NewInsnID*/1, /*OldInsnID*/0, /*OpIdx*/2, // vindex
        GIR_AddImm8, /*InsnID*/1, /*SubRegIndex*/3,
        GIR_Copy, /*NewInsnID*/1, /*OldInsnID*/0, /*OpIdx*/3, // voffset
        GIR_AddImm8, /*InsnID*/1, /*SubRegIndex*/11,
        GIR_ConstrainOperandRC, /*InsnID*/1, /*Op*/0, GIMT_Encode2(AMDGPU::VReg_64RegClassID),
        GIR_ConstrainOperandRC, /*InsnID*/1, /*Op*/1, GIMT_Encode2(AMDGPU::VGPR_32RegClassID),
        GIR_ConstrainOperandRC, /*InsnID*/1, /*Op*/3, GIMT_Encode2(AMDGPU::VGPR_32RegClassID),
        GIR_BuildMI, /*InsnID*/0, /*Opcode*/GIMT_Encode2(AMDGPU::TBUFFER_STORE_FORMAT_X_VBUFFER_BOTHEN_exact),
        GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/0, // vdata
        GIR_AddSimpleTempRegister, /*InsnID*/0, /*TempRegID*/0,
        GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/1, // rsrc
        GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/0, // soffset
        GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/5, // offset
        GIR_CustomOperandRenderer, /*InsnID*/0, /*OldInsnID*/0, /*OpIdx*/6, /*OperandRenderer*/GIMT_Encode2(GICR_renderTruncTImm), // format
        GIR_CustomOperandRenderer, /*InsnID*/0, /*OldInsnID*/0, /*OpIdx*/7, /*OperandRenderer*/GIMT_Encode2(GICR_renderExtractCPol), // auxiliary
        GIR_CustomOperandRenderer, /*InsnID*/0, /*OldInsnID*/0, /*OpIdx*/7, /*OperandRenderer*/GIMT_Encode2(GICR_renderExtractSWZ), // auxiliary
        GIR_MergeMemOperands, /*InsnID*/0, /*NumInsns*/1, /*MergeInsnID's*/0,
        GIR_ConstrainSelectedInstOperands, /*InsnID*/0,
        GIR_EraseFromParent, /*InsnID*/0,
        // GIR_Coverage, 5700,
        GIR_Done,
      // Label 7377: @539211
      GIM_Try, /*On fail goto*//*Label 7378*/ GIMT_Encode4(539330), // Rule ID 5728 //
        GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasUnrestrictedSOffset),
        // MIs[0] offset
        GIM_CheckIsImm, /*MI*/0, /*Op*/5,
        // MIs[0] format
        GIM_CheckIsImm, /*MI*/0, /*Op*/6,
        // MIs[0] auxiliary
        GIM_CheckIsImm, /*MI*/0, /*Op*/7,
        // MIs[0] Operand 8
        GIM_CheckIsImm, /*MI*/0, /*Op*/8,
        GIM_CheckComplexPattern, /*MI*/0, /*Op*/4, /*Renderer*/GIMT_Encode2(0), GIMT_Encode2(GICP_gi_buf_soffset),
        // (SItbuffer_store f32:{ *:[f32] }:$vdata, v4i32:{ *:[v4i32] }:$rsrc, i32:{ *:[i32] }:$vindex, i32:{ *:[i32] }:$voffset, (BUFSOffset:{ *:[i32] } i32:{ *:[i32] }:$soffset), (timm:{ *:[i32] }):$offset, (timm:{ *:[i32] }):$format, (timm:{ *:[i32] }):$auxiliary, (timm:{ *:[i1] }))  =>  (TBUFFER_STORE_FORMAT_X_BOTHEN_exact anonymous_15037:{ *:[f32] }:$vdata, (REG_SEQUENCE:{ *:[i64] } VReg_64:{ *:[i32] }, VGPR_32:{ *:[i32] }:$vindex, sub0:{ *:[i32] }, VGPR_32:{ *:[i32] }:$voffset, sub1:{ *:[i32] }), SReg_128:{ *:[v4i32] }:$rsrc, SCSrc_b32:{ *:[i32] }:$soffset, (timm:{ *:[i32] }):$offset, (as_i8timm:{ *:[i8] } ?:{ *:[i32] }:$format), (extract_cpol:{ *:[i32] } ?:{ *:[i32] }:$auxiliary), (extract_swz:{ *:[i1] } ?:{ *:[i32] }:$auxiliary))
        GIR_MakeTempReg, /*TempRegID*/0, /*TypeID*/GILLT_s64,
        GIR_BuildMI, /*InsnID*/1, /*Opcode*/GIMT_Encode2(TargetOpcode::REG_SEQUENCE),
        GIR_AddTempRegister, /*InsnID*/1, /*TempRegID*/0, /*TempRegFlags*/GIMT_Encode2(RegState::Define),
        GIR_Copy, /*NewInsnID*/1, /*OldInsnID*/0, /*OpIdx*/2, // vindex
        GIR_AddImm8, /*InsnID*/1, /*SubRegIndex*/3,
        GIR_Copy, /*NewInsnID*/1, /*OldInsnID*/0, /*OpIdx*/3, // voffset
        GIR_AddImm8, /*InsnID*/1, /*SubRegIndex*/11,
        GIR_ConstrainOperandRC, /*InsnID*/1, /*Op*/0, GIMT_Encode2(AMDGPU::VReg_64RegClassID),
        GIR_ConstrainOperandRC, /*InsnID*/1, /*Op*/1, GIMT_Encode2(AMDGPU::VGPR_32RegClassID),
        GIR_ConstrainOperandRC, /*InsnID*/1, /*Op*/3, GIMT_Encode2(AMDGPU::VGPR_32RegClassID),
        GIR_BuildMI, /*InsnID*/0, /*Opcode*/GIMT_Encode2(AMDGPU::TBUFFER_STORE_FORMAT_X_BOTHEN_exact),
        GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/0, // vdata
        GIR_AddSimpleTempRegister, /*InsnID*/0, /*TempRegID*/0,
        GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/1, // rsrc
        GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/0, // soffset
        GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/5, // offset
        GIR_CustomOperandRenderer, /*InsnID*/0, /*OldInsnID*/0, /*OpIdx*/6, /*OperandRenderer*/GIMT_Encode2(GICR_renderTruncTImm), // format
        GIR_CustomOperandRenderer, /*InsnID*/0, /*OldInsnID*/0, /*OpIdx*/7, /*OperandRenderer*/GIMT_Encode2(GICR_renderExtractCPol), // auxiliary
        GIR_CustomOperandRenderer, /*InsnID*/0, /*OldInsnID*/0, /*OpIdx*/7, /*OperandRenderer*/GIMT_Encode2(GICR_renderExtractSWZ), // auxiliary
        GIR_MergeMemOperands, /*InsnID*/0, /*NumInsns*/1, /*MergeInsnID's*/0,
        GIR_ConstrainSelectedInstOperands, /*InsnID*/0,
        GIR_EraseFromParent, /*InsnID*/0,
        // GIR_Coverage, 5728,
        GIR_Done,
      // Label 7378: @539330
      GIM_Try, /*On fail goto*//*Label 7379*/ GIMT_Encode4(539446), // Rule ID 5732 //
        // MIs[0] offset
        GIM_CheckIsImm, /*MI*/0, /*Op*/5,
        // MIs[0] format
        GIM_CheckIsImm, /*MI*/0, /*Op*/6,
        // MIs[0] auxiliary
        GIM_CheckIsImm, /*MI*/0, /*Op*/7,
        // MIs[0] Operand 8
        GIM_CheckIsImm, /*MI*/0, /*Op*/8,
        GIM_CheckComplexPattern, /*MI*/0, /*Op*/4, /*Renderer*/GIMT_Encode2(0), GIMT_Encode2(GICP_gi_buf_soffset),
        // (SItbuffer_store f32:{ *:[f32] }:$vdata, v4i32:{ *:[v4i32] }:$rsrc, i32:{ *:[i32] }:$vindex, i32:{ *:[i32] }:$voffset, (BUFSOffset:{ *:[i32] } i32:{ *:[i32] }:$soffset), (timm:{ *:[i32] }):$offset, (timm:{ *:[i32] }):$format, (timm:{ *:[i32] }):$auxiliary, (timm:{ *:[i1] }))  =>  (TBUFFER_STORE_FORMAT_X_VBUFFER_BOTHEN_exact anonymous_15037:{ *:[f32] }:$vdata, (REG_SEQUENCE:{ *:[i64] } VReg_64:{ *:[i32] }, VGPR_32:{ *:[i32] }:$vindex, sub0:{ *:[i32] }, VGPR_32:{ *:[i32] }:$voffset, sub1:{ *:[i32] }), SReg_128:{ *:[v4i32] }:$rsrc, SCSrc_b32:{ *:[i32] }:$soffset, (timm:{ *:[i32] }):$offset, (as_i8timm:{ *:[i8] } ?:{ *:[i32] }:$format), (extract_cpol:{ *:[i32] } ?:{ *:[i32] }:$auxiliary), (extract_swz:{ *:[i1] } ?:{ *:[i32] }:$auxiliary))
        GIR_MakeTempReg, /*TempRegID*/0, /*TypeID*/GILLT_s64,
        GIR_BuildMI, /*InsnID*/1, /*Opcode*/GIMT_Encode2(TargetOpcode::REG_SEQUENCE),
        GIR_AddTempRegister, /*InsnID*/1, /*TempRegID*/0, /*TempRegFlags*/GIMT_Encode2(RegState::Define),
        GIR_Copy, /*NewInsnID*/1, /*OldInsnID*/0, /*OpIdx*/2, // vindex
        GIR_AddImm8, /*InsnID*/1, /*SubRegIndex*/3,
        GIR_Copy, /*NewInsnID*/1, /*OldInsnID*/0, /*OpIdx*/3, // voffset
        GIR_AddImm8, /*InsnID*/1, /*SubRegIndex*/11,
        GIR_ConstrainOperandRC, /*InsnID*/1, /*Op*/0, GIMT_Encode2(AMDGPU::VReg_64RegClassID),
        GIR_ConstrainOperandRC, /*InsnID*/1, /*Op*/1, GIMT_Encode2(AMDGPU::VGPR_32RegClassID),
        GIR_ConstrainOperandRC, /*InsnID*/1, /*Op*/3, GIMT_Encode2(AMDGPU::VGPR_32RegClassID),
        GIR_BuildMI, /*InsnID*/0, /*Opcode*/GIMT_Encode2(AMDGPU::TBUFFER_STORE_FORMAT_X_VBUFFER_BOTHEN_exact),
        GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/0, // vdata
        GIR_AddSimpleTempRegister, /*InsnID*/0, /*TempRegID*/0,
        GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/1, // rsrc
        GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/0, // soffset
        GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/5, // offset
        GIR_CustomOperandRenderer, /*InsnID*/0, /*OldInsnID*/0, /*OpIdx*/6, /*OperandRenderer*/GIMT_Encode2(GICR_renderTruncTImm), // format
        GIR_CustomOperandRenderer, /*InsnID*/0, /*OldInsnID*/0, /*OpIdx*/7, /*OperandRenderer*/GIMT_Encode2(GICR_renderExtractCPol), // auxiliary
        GIR_CustomOperandRenderer, /*InsnID*/0, /*OldInsnID*/0, /*OpIdx*/7, /*OperandRenderer*/GIMT_Encode2(GICR_renderExtractSWZ), // auxiliary
        GIR_MergeMemOperands, /*InsnID*/0, /*NumInsns*/1, /*MergeInsnID's*/0,
        GIR_ConstrainSelectedInstOperands, /*InsnID*/0,
        GIR_EraseFromParent, /*InsnID*/0,
        // GIR_Coverage, 5732,
        GIR_Done,
      // Label 7379: @539446
      GIM_Reject,
    // Label 7363: @539447
    GIM_Reject,
    // Label 7359: @539448
    GIM_Try, /*On fail goto*//*Label 7380*/ GIMT_Encode4(540982),
      GIM_CheckType, /*MI*/0, /*Op*/1, /*Type*/GILLT_v4s32,
      GIM_CheckType, /*MI*/0, /*Op*/2, /*Type*/GILLT_s32,
      GIM_CheckType, /*MI*/0, /*Op*/3, /*Type*/GILLT_s32,
      GIM_CheckType, /*MI*/0, /*Op*/4, /*Type*/GILLT_s32,
      GIM_Try, /*On fail goto*//*Label 7381*/ GIMT_Encode4(539560), // Rule ID 5701 //
        GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasUnrestrictedSOffset),
        GIM_CheckConstantInt8, /*MI*/0, /*Op*/2, 0,
        GIM_CheckConstantInt8, /*MI*/0, /*Op*/3, 0,
        // MIs[0] offset
        GIM_CheckIsImm, /*MI*/0, /*Op*/5,
        // MIs[0] format
        GIM_CheckIsImm, /*MI*/0, /*Op*/6,
        // MIs[0] auxiliary
        GIM_CheckIsImm, /*MI*/0, /*Op*/7,
        // MIs[0] Operand 8
        GIM_CheckLiteralInt, /*MI*/0, /*Op*/8, GIMT_Encode8(0),
        GIM_CheckComplexPattern, /*MI*/0, /*Op*/4, /*Renderer*/GIMT_Encode2(0), GIMT_Encode2(GICP_gi_buf_soffset),
        // (SItbuffer_store v2i32:{ *:[v2i32] }:$vdata, v4i32:{ *:[v4i32] }:$rsrc, 0:{ *:[i32] }, 0:{ *:[i32] }, (BUFSOffset:{ *:[i32] } i32:{ *:[i32] }:$soffset), (timm:{ *:[i32] }):$offset, (timm:{ *:[i32] }):$format, (timm:{ *:[i32] }):$auxiliary, 0:{ *:[i1] })  =>  (TBUFFER_STORE_FORMAT_XY_OFFSET_exact anonymous_15036:{ *:[v2i32] }:$vdata, SReg_128:{ *:[v4i32] }:$rsrc, SCSrc_b32:{ *:[i32] }:$soffset, (timm:{ *:[i32] }):$offset, (as_i8timm:{ *:[i8] } ?:{ *:[i32] }:$format), (extract_cpol:{ *:[i32] } ?:{ *:[i32] }:$auxiliary), (extract_swz:{ *:[i1] } ?:{ *:[i32] }:$auxiliary))
        GIR_BuildMI, /*InsnID*/0, /*Opcode*/GIMT_Encode2(AMDGPU::TBUFFER_STORE_FORMAT_XY_OFFSET_exact),
        GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/0, // vdata
        GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/1, // rsrc
        GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/0, // soffset
        GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/5, // offset
        GIR_CustomOperandRenderer, /*InsnID*/0, /*OldInsnID*/0, /*OpIdx*/6, /*OperandRenderer*/GIMT_Encode2(GICR_renderTruncTImm), // format
        GIR_CustomOperandRenderer, /*InsnID*/0, /*OldInsnID*/0, /*OpIdx*/7, /*OperandRenderer*/GIMT_Encode2(GICR_renderExtractCPol), // auxiliary
        GIR_CustomOperandRenderer, /*InsnID*/0, /*OldInsnID*/0, /*OpIdx*/7, /*OperandRenderer*/GIMT_Encode2(GICR_renderExtractSWZ), // auxiliary
        GIR_MergeMemOperands, /*InsnID*/0, /*NumInsns*/1, /*MergeInsnID's*/0,
        GIR_ConstrainSelectedInstOperands, /*InsnID*/0,
        GIR_EraseFromParent, /*InsnID*/0,
        // GIR_Coverage, 5701,
        GIR_Done,
      // Label 7381: @539560
      GIM_Try, /*On fail goto*//*Label 7382*/ GIMT_Encode4(539648), // Rule ID 5705 //
        GIM_CheckConstantInt8, /*MI*/0, /*Op*/2, 0,
        GIM_CheckConstantInt8, /*MI*/0, /*Op*/3, 0,
        // MIs[0] offset
        GIM_CheckIsImm, /*MI*/0, /*Op*/5,
        // MIs[0] format
        GIM_CheckIsImm, /*MI*/0, /*Op*/6,
        // MIs[0] auxiliary
        GIM_CheckIsImm, /*MI*/0, /*Op*/7,
        // MIs[0] Operand 8
        GIM_CheckLiteralInt, /*MI*/0, /*Op*/8, GIMT_Encode8(0),
        GIM_CheckComplexPattern, /*MI*/0, /*Op*/4, /*Renderer*/GIMT_Encode2(0), GIMT_Encode2(GICP_gi_buf_soffset),
        // (SItbuffer_store v2i32:{ *:[v2i32] }:$vdata, v4i32:{ *:[v4i32] }:$rsrc, 0:{ *:[i32] }, 0:{ *:[i32] }, (BUFSOffset:{ *:[i32] } i32:{ *:[i32] }:$soffset), (timm:{ *:[i32] }):$offset, (timm:{ *:[i32] }):$format, (timm:{ *:[i32] }):$auxiliary, 0:{ *:[i1] })  =>  (TBUFFER_STORE_FORMAT_XY_VBUFFER_OFFSET_exact anonymous_15036:{ *:[v2i32] }:$vdata, SReg_128:{ *:[v4i32] }:$rsrc, SCSrc_b32:{ *:[i32] }:$soffset, (timm:{ *:[i32] }):$offset, (as_i8timm:{ *:[i8] } ?:{ *:[i32] }:$format), (extract_cpol:{ *:[i32] } ?:{ *:[i32] }:$auxiliary), (extract_swz:{ *:[i1] } ?:{ *:[i32] }:$auxiliary))
        GIR_BuildMI, /*InsnID*/0, /*Opcode*/GIMT_Encode2(AMDGPU::TBUFFER_STORE_FORMAT_XY_VBUFFER_OFFSET_exact),
        GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/0, // vdata
        GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/1, // rsrc
        GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/0, // soffset
        GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/5, // offset
        GIR_CustomOperandRenderer, /*InsnID*/0, /*OldInsnID*/0, /*OpIdx*/6, /*OperandRenderer*/GIMT_Encode2(GICR_renderTruncTImm), // format
        GIR_CustomOperandRenderer, /*InsnID*/0, /*OldInsnID*/0, /*OpIdx*/7, /*OperandRenderer*/GIMT_Encode2(GICR_renderExtractCPol), // auxiliary
        GIR_CustomOperandRenderer, /*InsnID*/0, /*OldInsnID*/0, /*OpIdx*/7, /*OperandRenderer*/GIMT_Encode2(GICR_renderExtractSWZ), // auxiliary
        GIR_MergeMemOperands, /*InsnID*/0, /*NumInsns*/1, /*MergeInsnID's*/0,
        GIR_ConstrainSelectedInstOperands, /*InsnID*/0,
        GIR_EraseFromParent, /*InsnID*/0,
        // GIR_Coverage, 5705,
        GIR_Done,
      // Label 7382: @539648
      GIM_Try, /*On fail goto*//*Label 7383*/ GIMT_Encode4(539739), // Rule ID 5733 //
        GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasUnrestrictedSOffset),
        GIM_CheckConstantInt8, /*MI*/0, /*Op*/2, 0,
        GIM_CheckConstantInt8, /*MI*/0, /*Op*/3, 0,
        // MIs[0] offset
        GIM_CheckIsImm, /*MI*/0, /*Op*/5,
        // MIs[0] format
        GIM_CheckIsImm, /*MI*/0, /*Op*/6,
        // MIs[0] auxiliary
        GIM_CheckIsImm, /*MI*/0, /*Op*/7,
        // MIs[0] Operand 8
        GIM_CheckLiteralInt, /*MI*/0, /*Op*/8, GIMT_Encode8(0),
        GIM_CheckComplexPattern, /*MI*/0, /*Op*/4, /*Renderer*/GIMT_Encode2(0), GIMT_Encode2(GICP_gi_buf_soffset),
        // (SItbuffer_store v2f32:{ *:[v2f32] }:$vdata, v4i32:{ *:[v4i32] }:$rsrc, 0:{ *:[i32] }, 0:{ *:[i32] }, (BUFSOffset:{ *:[i32] } i32:{ *:[i32] }:$soffset), (timm:{ *:[i32] }):$offset, (timm:{ *:[i32] }):$format, (timm:{ *:[i32] }):$auxiliary, 0:{ *:[i1] })  =>  (TBUFFER_STORE_FORMAT_XY_OFFSET_exact anonymous_15036:{ *:[v2f32] }:$vdata, SReg_128:{ *:[v4i32] }:$rsrc, SCSrc_b32:{ *:[i32] }:$soffset, (timm:{ *:[i32] }):$offset, (as_i8timm:{ *:[i8] } ?:{ *:[i32] }:$format), (extract_cpol:{ *:[i32] } ?:{ *:[i32] }:$auxiliary), (extract_swz:{ *:[i1] } ?:{ *:[i32] }:$auxiliary))
        GIR_BuildMI, /*InsnID*/0, /*Opcode*/GIMT_Encode2(AMDGPU::TBUFFER_STORE_FORMAT_XY_OFFSET_exact),
        GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/0, // vdata
        GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/1, // rsrc
        GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/0, // soffset
        GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/5, // offset
        GIR_CustomOperandRenderer, /*InsnID*/0, /*OldInsnID*/0, /*OpIdx*/6, /*OperandRenderer*/GIMT_Encode2(GICR_renderTruncTImm), // format
        GIR_CustomOperandRenderer, /*InsnID*/0, /*OldInsnID*/0, /*OpIdx*/7, /*OperandRenderer*/GIMT_Encode2(GICR_renderExtractCPol), // auxiliary
        GIR_CustomOperandRenderer, /*InsnID*/0, /*OldInsnID*/0, /*OpIdx*/7, /*OperandRenderer*/GIMT_Encode2(GICR_renderExtractSWZ), // auxiliary
        GIR_MergeMemOperands, /*InsnID*/0, /*NumInsns*/1, /*MergeInsnID's*/0,
        GIR_ConstrainSelectedInstOperands, /*InsnID*/0,
        GIR_EraseFromParent, /*InsnID*/0,
        // GIR_Coverage, 5733,
        GIR_Done,
      // Label 7383: @539739
      GIM_Try, /*On fail goto*//*Label 7384*/ GIMT_Encode4(539827), // Rule ID 5737 //
        GIM_CheckConstantInt8, /*MI*/0, /*Op*/2, 0,
        GIM_CheckConstantInt8, /*MI*/0, /*Op*/3, 0,
        // MIs[0] offset
        GIM_CheckIsImm, /*MI*/0, /*Op*/5,
        // MIs[0] format
        GIM_CheckIsImm, /*MI*/0, /*Op*/6,
        // MIs[0] auxiliary
        GIM_CheckIsImm, /*MI*/0, /*Op*/7,
        // MIs[0] Operand 8
        GIM_CheckLiteralInt, /*MI*/0, /*Op*/8, GIMT_Encode8(0),
        GIM_CheckComplexPattern, /*MI*/0, /*Op*/4, /*Renderer*/GIMT_Encode2(0), GIMT_Encode2(GICP_gi_buf_soffset),
        // (SItbuffer_store v2f32:{ *:[v2f32] }:$vdata, v4i32:{ *:[v4i32] }:$rsrc, 0:{ *:[i32] }, 0:{ *:[i32] }, (BUFSOffset:{ *:[i32] } i32:{ *:[i32] }:$soffset), (timm:{ *:[i32] }):$offset, (timm:{ *:[i32] }):$format, (timm:{ *:[i32] }):$auxiliary, 0:{ *:[i1] })  =>  (TBUFFER_STORE_FORMAT_XY_VBUFFER_OFFSET_exact anonymous_15036:{ *:[v2f32] }:$vdata, SReg_128:{ *:[v4i32] }:$rsrc, SCSrc_b32:{ *:[i32] }:$soffset, (timm:{ *:[i32] }):$offset, (as_i8timm:{ *:[i8] } ?:{ *:[i32] }:$format), (extract_cpol:{ *:[i32] } ?:{ *:[i32] }:$auxiliary), (extract_swz:{ *:[i1] } ?:{ *:[i32] }:$auxiliary))
        GIR_BuildMI, /*InsnID*/0, /*Opcode*/GIMT_Encode2(AMDGPU::TBUFFER_STORE_FORMAT_XY_VBUFFER_OFFSET_exact),
        GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/0, // vdata
        GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/1, // rsrc
        GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/0, // soffset
        GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/5, // offset
        GIR_CustomOperandRenderer, /*InsnID*/0, /*OldInsnID*/0, /*OpIdx*/6, /*OperandRenderer*/GIMT_Encode2(GICR_renderTruncTImm), // format
        GIR_CustomOperandRenderer, /*InsnID*/0, /*OldInsnID*/0, /*OpIdx*/7, /*OperandRenderer*/GIMT_Encode2(GICR_renderExtractCPol), // auxiliary
        GIR_CustomOperandRenderer, /*InsnID*/0, /*OldInsnID*/0, /*OpIdx*/7, /*OperandRenderer*/GIMT_Encode2(GICR_renderExtractSWZ), // auxiliary
        GIR_MergeMemOperands, /*InsnID*/0, /*NumInsns*/1, /*MergeInsnID's*/0,
        GIR_ConstrainSelectedInstOperands, /*InsnID*/0,
        GIR_EraseFromParent, /*InsnID*/0,
        // GIR_Coverage, 5737,
        GIR_Done,
      // Label 7384: @539827
      GIM_Try, /*On fail goto*//*Label 7385*/ GIMT_Encode4(539918), // Rule ID 5703 //
        GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasUnrestrictedSOffset),
        GIM_CheckConstantInt8, /*MI*/0, /*Op*/2, 0,
        // MIs[0] offset
        GIM_CheckIsImm, /*MI*/0, /*Op*/5,
        // MIs[0] format
        GIM_CheckIsImm, /*MI*/0, /*Op*/6,
        // MIs[0] auxiliary
        GIM_CheckIsImm, /*MI*/0, /*Op*/7,
        // MIs[0] Operand 8
        GIM_CheckLiteralInt, /*MI*/0, /*Op*/8, GIMT_Encode8(0),
        GIM_CheckComplexPattern, /*MI*/0, /*Op*/4, /*Renderer*/GIMT_Encode2(0), GIMT_Encode2(GICP_gi_buf_soffset),
        // (SItbuffer_store v2i32:{ *:[v2i32] }:$vdata, v4i32:{ *:[v4i32] }:$rsrc, 0:{ *:[i32] }, i32:{ *:[i32] }:$voffset, (BUFSOffset:{ *:[i32] } i32:{ *:[i32] }:$soffset), (timm:{ *:[i32] }):$offset, (timm:{ *:[i32] }):$format, (timm:{ *:[i32] }):$auxiliary, 0:{ *:[i1] })  =>  (TBUFFER_STORE_FORMAT_XY_OFFEN_exact anonymous_15036:{ *:[v2i32] }:$vdata, VGPR_32:{ *:[i32] }:$voffset, SReg_128:{ *:[v4i32] }:$rsrc, SCSrc_b32:{ *:[i32] }:$soffset, (timm:{ *:[i32] }):$offset, (as_i8timm:{ *:[i8] } ?:{ *:[i32] }:$format), (extract_cpol:{ *:[i32] } ?:{ *:[i32] }:$auxiliary), (extract_swz:{ *:[i1] } ?:{ *:[i32] }:$auxiliary))
        GIR_BuildMI, /*InsnID*/0, /*Opcode*/GIMT_Encode2(AMDGPU::TBUFFER_STORE_FORMAT_XY_OFFEN_exact),
        GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/0, // vdata
        GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/3, // voffset
        GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/1, // rsrc
        GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/0, // soffset
        GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/5, // offset
        GIR_CustomOperandRenderer, /*InsnID*/0, /*OldInsnID*/0, /*OpIdx*/6, /*OperandRenderer*/GIMT_Encode2(GICR_renderTruncTImm), // format
        GIR_CustomOperandRenderer, /*InsnID*/0, /*OldInsnID*/0, /*OpIdx*/7, /*OperandRenderer*/GIMT_Encode2(GICR_renderExtractCPol), // auxiliary
        GIR_CustomOperandRenderer, /*InsnID*/0, /*OldInsnID*/0, /*OpIdx*/7, /*OperandRenderer*/GIMT_Encode2(GICR_renderExtractSWZ), // auxiliary
        GIR_MergeMemOperands, /*InsnID*/0, /*NumInsns*/1, /*MergeInsnID's*/0,
        GIR_ConstrainSelectedInstOperands, /*InsnID*/0,
        GIR_EraseFromParent, /*InsnID*/0,
        // GIR_Coverage, 5703,
        GIR_Done,
      // Label 7385: @539918
      GIM_Try, /*On fail goto*//*Label 7386*/ GIMT_Encode4(540006), // Rule ID 5707 //
        GIM_CheckConstantInt8, /*MI*/0, /*Op*/2, 0,
        // MIs[0] offset
        GIM_CheckIsImm, /*MI*/0, /*Op*/5,
        // MIs[0] format
        GIM_CheckIsImm, /*MI*/0, /*Op*/6,
        // MIs[0] auxiliary
        GIM_CheckIsImm, /*MI*/0, /*Op*/7,
        // MIs[0] Operand 8
        GIM_CheckLiteralInt, /*MI*/0, /*Op*/8, GIMT_Encode8(0),
        GIM_CheckComplexPattern, /*MI*/0, /*Op*/4, /*Renderer*/GIMT_Encode2(0), GIMT_Encode2(GICP_gi_buf_soffset),
        // (SItbuffer_store v2i32:{ *:[v2i32] }:$vdata, v4i32:{ *:[v4i32] }:$rsrc, 0:{ *:[i32] }, i32:{ *:[i32] }:$voffset, (BUFSOffset:{ *:[i32] } i32:{ *:[i32] }:$soffset), (timm:{ *:[i32] }):$offset, (timm:{ *:[i32] }):$format, (timm:{ *:[i32] }):$auxiliary, 0:{ *:[i1] })  =>  (TBUFFER_STORE_FORMAT_XY_VBUFFER_OFFEN_exact anonymous_15036:{ *:[v2i32] }:$vdata, VGPR_32:{ *:[i32] }:$voffset, SReg_128:{ *:[v4i32] }:$rsrc, SCSrc_b32:{ *:[i32] }:$soffset, (timm:{ *:[i32] }):$offset, (as_i8timm:{ *:[i8] } ?:{ *:[i32] }:$format), (extract_cpol:{ *:[i32] } ?:{ *:[i32] }:$auxiliary), (extract_swz:{ *:[i1] } ?:{ *:[i32] }:$auxiliary))
        GIR_BuildMI, /*InsnID*/0, /*Opcode*/GIMT_Encode2(AMDGPU::TBUFFER_STORE_FORMAT_XY_VBUFFER_OFFEN_exact),
        GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/0, // vdata
        GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/3, // voffset
        GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/1, // rsrc
        GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/0, // soffset
        GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/5, // offset
        GIR_CustomOperandRenderer, /*InsnID*/0, /*OldInsnID*/0, /*OpIdx*/6, /*OperandRenderer*/GIMT_Encode2(GICR_renderTruncTImm), // format
        GIR_CustomOperandRenderer, /*InsnID*/0, /*OldInsnID*/0, /*OpIdx*/7, /*OperandRenderer*/GIMT_Encode2(GICR_renderExtractCPol), // auxiliary
        GIR_CustomOperandRenderer, /*InsnID*/0, /*OldInsnID*/0, /*OpIdx*/7, /*OperandRenderer*/GIMT_Encode2(GICR_renderExtractSWZ), // auxiliary
        GIR_MergeMemOperands, /*InsnID*/0, /*NumInsns*/1, /*MergeInsnID's*/0,
        GIR_ConstrainSelectedInstOperands, /*InsnID*/0,
        GIR_EraseFromParent, /*InsnID*/0,
        // GIR_Coverage, 5707,
        GIR_Done,
      // Label 7386: @540006
      GIM_Try, /*On fail goto*//*Label 7387*/ GIMT_Encode4(540097), // Rule ID 5735 //
        GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasUnrestrictedSOffset),
        GIM_CheckConstantInt8, /*MI*/0, /*Op*/2, 0,
        // MIs[0] offset
        GIM_CheckIsImm, /*MI*/0, /*Op*/5,
        // MIs[0] format
        GIM_CheckIsImm, /*MI*/0, /*Op*/6,
        // MIs[0] auxiliary
        GIM_CheckIsImm, /*MI*/0, /*Op*/7,
        // MIs[0] Operand 8
        GIM_CheckLiteralInt, /*MI*/0, /*Op*/8, GIMT_Encode8(0),
        GIM_CheckComplexPattern, /*MI*/0, /*Op*/4, /*Renderer*/GIMT_Encode2(0), GIMT_Encode2(GICP_gi_buf_soffset),
        // (SItbuffer_store v2f32:{ *:[v2f32] }:$vdata, v4i32:{ *:[v4i32] }:$rsrc, 0:{ *:[i32] }, i32:{ *:[i32] }:$voffset, (BUFSOffset:{ *:[i32] } i32:{ *:[i32] }:$soffset), (timm:{ *:[i32] }):$offset, (timm:{ *:[i32] }):$format, (timm:{ *:[i32] }):$auxiliary, 0:{ *:[i1] })  =>  (TBUFFER_STORE_FORMAT_XY_OFFEN_exact anonymous_15036:{ *:[v2f32] }:$vdata, VGPR_32:{ *:[i32] }:$voffset, SReg_128:{ *:[v4i32] }:$rsrc, SCSrc_b32:{ *:[i32] }:$soffset, (timm:{ *:[i32] }):$offset, (as_i8timm:{ *:[i8] } ?:{ *:[i32] }:$format), (extract_cpol:{ *:[i32] } ?:{ *:[i32] }:$auxiliary), (extract_swz:{ *:[i1] } ?:{ *:[i32] }:$auxiliary))
        GIR_BuildMI, /*InsnID*/0, /*Opcode*/GIMT_Encode2(AMDGPU::TBUFFER_STORE_FORMAT_XY_OFFEN_exact),
        GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/0, // vdata
        GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/3, // voffset
        GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/1, // rsrc
        GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/0, // soffset
        GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/5, // offset
        GIR_CustomOperandRenderer, /*InsnID*/0, /*OldInsnID*/0, /*OpIdx*/6, /*OperandRenderer*/GIMT_Encode2(GICR_renderTruncTImm), // format
        GIR_CustomOperandRenderer, /*InsnID*/0, /*OldInsnID*/0, /*OpIdx*/7, /*OperandRenderer*/GIMT_Encode2(GICR_renderExtractCPol), // auxiliary
        GIR_CustomOperandRenderer, /*InsnID*/0, /*OldInsnID*/0, /*OpIdx*/7, /*OperandRenderer*/GIMT_Encode2(GICR_renderExtractSWZ), // auxiliary
        GIR_MergeMemOperands, /*InsnID*/0, /*NumInsns*/1, /*MergeInsnID's*/0,
        GIR_ConstrainSelectedInstOperands, /*InsnID*/0,
        GIR_EraseFromParent, /*InsnID*/0,
        // GIR_Coverage, 5735,
        GIR_Done,
      // Label 7387: @540097
      GIM_Try, /*On fail goto*//*Label 7388*/ GIMT_Encode4(540185), // Rule ID 5739 //
        GIM_CheckConstantInt8, /*MI*/0, /*Op*/2, 0,
        // MIs[0] offset
        GIM_CheckIsImm, /*MI*/0, /*Op*/5,
        // MIs[0] format
        GIM_CheckIsImm, /*MI*/0, /*Op*/6,
        // MIs[0] auxiliary
        GIM_CheckIsImm, /*MI*/0, /*Op*/7,
        // MIs[0] Operand 8
        GIM_CheckLiteralInt, /*MI*/0, /*Op*/8, GIMT_Encode8(0),
        GIM_CheckComplexPattern, /*MI*/0, /*Op*/4, /*Renderer*/GIMT_Encode2(0), GIMT_Encode2(GICP_gi_buf_soffset),
        // (SItbuffer_store v2f32:{ *:[v2f32] }:$vdata, v4i32:{ *:[v4i32] }:$rsrc, 0:{ *:[i32] }, i32:{ *:[i32] }:$voffset, (BUFSOffset:{ *:[i32] } i32:{ *:[i32] }:$soffset), (timm:{ *:[i32] }):$offset, (timm:{ *:[i32] }):$format, (timm:{ *:[i32] }):$auxiliary, 0:{ *:[i1] })  =>  (TBUFFER_STORE_FORMAT_XY_VBUFFER_OFFEN_exact anonymous_15036:{ *:[v2f32] }:$vdata, VGPR_32:{ *:[i32] }:$voffset, SReg_128:{ *:[v4i32] }:$rsrc, SCSrc_b32:{ *:[i32] }:$soffset, (timm:{ *:[i32] }):$offset, (as_i8timm:{ *:[i8] } ?:{ *:[i32] }:$format), (extract_cpol:{ *:[i32] } ?:{ *:[i32] }:$auxiliary), (extract_swz:{ *:[i1] } ?:{ *:[i32] }:$auxiliary))
        GIR_BuildMI, /*InsnID*/0, /*Opcode*/GIMT_Encode2(AMDGPU::TBUFFER_STORE_FORMAT_XY_VBUFFER_OFFEN_exact),
        GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/0, // vdata
        GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/3, // voffset
        GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/1, // rsrc
        GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/0, // soffset
        GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/5, // offset
        GIR_CustomOperandRenderer, /*InsnID*/0, /*OldInsnID*/0, /*OpIdx*/6, /*OperandRenderer*/GIMT_Encode2(GICR_renderTruncTImm), // format
        GIR_CustomOperandRenderer, /*InsnID*/0, /*OldInsnID*/0, /*OpIdx*/7, /*OperandRenderer*/GIMT_Encode2(GICR_renderExtractCPol), // auxiliary
        GIR_CustomOperandRenderer, /*InsnID*/0, /*OldInsnID*/0, /*OpIdx*/7, /*OperandRenderer*/GIMT_Encode2(GICR_renderExtractSWZ), // auxiliary
        GIR_MergeMemOperands, /*InsnID*/0, /*NumInsns*/1, /*MergeInsnID's*/0,
        GIR_ConstrainSelectedInstOperands, /*InsnID*/0,
        GIR_EraseFromParent, /*InsnID*/0,
        // GIR_Coverage, 5739,
        GIR_Done,
      // Label 7388: @540185
      GIM_Try, /*On fail goto*//*Label 7389*/ GIMT_Encode4(540268), // Rule ID 5702 //
        GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasUnrestrictedSOffset),
        GIM_CheckConstantInt8, /*MI*/0, /*Op*/3, 0,
        // MIs[0] offset
        GIM_CheckIsImm, /*MI*/0, /*Op*/5,
        // MIs[0] format
        GIM_CheckIsImm, /*MI*/0, /*Op*/6,
        // MIs[0] auxiliary
        GIM_CheckIsImm, /*MI*/0, /*Op*/7,
        // MIs[0] Operand 8
        GIM_CheckIsImm, /*MI*/0, /*Op*/8,
        GIM_CheckComplexPattern, /*MI*/0, /*Op*/4, /*Renderer*/GIMT_Encode2(0), GIMT_Encode2(GICP_gi_buf_soffset),
        // (SItbuffer_store v2i32:{ *:[v2i32] }:$vdata, v4i32:{ *:[v4i32] }:$rsrc, i32:{ *:[i32] }:$vindex, 0:{ *:[i32] }, (BUFSOffset:{ *:[i32] } i32:{ *:[i32] }:$soffset), (timm:{ *:[i32] }):$offset, (timm:{ *:[i32] }):$format, (timm:{ *:[i32] }):$auxiliary, (timm:{ *:[i1] }))  =>  (TBUFFER_STORE_FORMAT_XY_IDXEN_exact anonymous_15036:{ *:[v2i32] }:$vdata, VGPR_32:{ *:[i32] }:$vindex, SReg_128:{ *:[v4i32] }:$rsrc, SCSrc_b32:{ *:[i32] }:$soffset, (timm:{ *:[i32] }):$offset, (as_i8timm:{ *:[i8] } ?:{ *:[i32] }:$format), (extract_cpol:{ *:[i32] } ?:{ *:[i32] }:$auxiliary), (extract_swz:{ *:[i1] } ?:{ *:[i32] }:$auxiliary))
        GIR_BuildMI, /*InsnID*/0, /*Opcode*/GIMT_Encode2(AMDGPU::TBUFFER_STORE_FORMAT_XY_IDXEN_exact),
        GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/0, // vdata
        GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/2, // vindex
        GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/1, // rsrc
        GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/0, // soffset
        GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/5, // offset
        GIR_CustomOperandRenderer, /*InsnID*/0, /*OldInsnID*/0, /*OpIdx*/6, /*OperandRenderer*/GIMT_Encode2(GICR_renderTruncTImm), // format
        GIR_CustomOperandRenderer, /*InsnID*/0, /*OldInsnID*/0, /*OpIdx*/7, /*OperandRenderer*/GIMT_Encode2(GICR_renderExtractCPol), // auxiliary
        GIR_CustomOperandRenderer, /*InsnID*/0, /*OldInsnID*/0, /*OpIdx*/7, /*OperandRenderer*/GIMT_Encode2(GICR_renderExtractSWZ), // auxiliary
        GIR_MergeMemOperands, /*InsnID*/0, /*NumInsns*/1, /*MergeInsnID's*/0,
        GIR_ConstrainSelectedInstOperands, /*InsnID*/0,
        GIR_EraseFromParent, /*InsnID*/0,
        // GIR_Coverage, 5702,
        GIR_Done,
      // Label 7389: @540268
      GIM_Try, /*On fail goto*//*Label 7390*/ GIMT_Encode4(540348), // Rule ID 5706 //
        GIM_CheckConstantInt8, /*MI*/0, /*Op*/3, 0,
        // MIs[0] offset
        GIM_CheckIsImm, /*MI*/0, /*Op*/5,
        // MIs[0] format
        GIM_CheckIsImm, /*MI*/0, /*Op*/6,
        // MIs[0] auxiliary
        GIM_CheckIsImm, /*MI*/0, /*Op*/7,
        // MIs[0] Operand 8
        GIM_CheckIsImm, /*MI*/0, /*Op*/8,
        GIM_CheckComplexPattern, /*MI*/0, /*Op*/4, /*Renderer*/GIMT_Encode2(0), GIMT_Encode2(GICP_gi_buf_soffset),
        // (SItbuffer_store v2i32:{ *:[v2i32] }:$vdata, v4i32:{ *:[v4i32] }:$rsrc, i32:{ *:[i32] }:$vindex, 0:{ *:[i32] }, (BUFSOffset:{ *:[i32] } i32:{ *:[i32] }:$soffset), (timm:{ *:[i32] }):$offset, (timm:{ *:[i32] }):$format, (timm:{ *:[i32] }):$auxiliary, (timm:{ *:[i1] }))  =>  (TBUFFER_STORE_FORMAT_XY_VBUFFER_IDXEN_exact anonymous_15036:{ *:[v2i32] }:$vdata, VGPR_32:{ *:[i32] }:$vindex, SReg_128:{ *:[v4i32] }:$rsrc, SCSrc_b32:{ *:[i32] }:$soffset, (timm:{ *:[i32] }):$offset, (as_i8timm:{ *:[i8] } ?:{ *:[i32] }:$format), (extract_cpol:{ *:[i32] } ?:{ *:[i32] }:$auxiliary), (extract_swz:{ *:[i1] } ?:{ *:[i32] }:$auxiliary))
        GIR_BuildMI, /*InsnID*/0, /*Opcode*/GIMT_Encode2(AMDGPU::TBUFFER_STORE_FORMAT_XY_VBUFFER_IDXEN_exact),
        GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/0, // vdata
        GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/2, // vindex
        GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/1, // rsrc
        GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/0, // soffset
        GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/5, // offset
        GIR_CustomOperandRenderer, /*InsnID*/0, /*OldInsnID*/0, /*OpIdx*/6, /*OperandRenderer*/GIMT_Encode2(GICR_renderTruncTImm), // format
        GIR_CustomOperandRenderer, /*InsnID*/0, /*OldInsnID*/0, /*OpIdx*/7, /*OperandRenderer*/GIMT_Encode2(GICR_renderExtractCPol), // auxiliary
        GIR_CustomOperandRenderer, /*InsnID*/0, /*OldInsnID*/0, /*OpIdx*/7, /*OperandRenderer*/GIMT_Encode2(GICR_renderExtractSWZ), // auxiliary
        GIR_MergeMemOperands, /*InsnID*/0, /*NumInsns*/1, /*MergeInsnID's*/0,
        GIR_ConstrainSelectedInstOperands, /*InsnID*/0,
        GIR_EraseFromParent, /*InsnID*/0,
        // GIR_Coverage, 5706,
        GIR_Done,
      // Label 7390: @540348
      GIM_Try, /*On fail goto*//*Label 7391*/ GIMT_Encode4(540431), // Rule ID 5734 //
        GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasUnrestrictedSOffset),
        GIM_CheckConstantInt8, /*MI*/0, /*Op*/3, 0,
        // MIs[0] offset
        GIM_CheckIsImm, /*MI*/0, /*Op*/5,
        // MIs[0] format
        GIM_CheckIsImm, /*MI*/0, /*Op*/6,
        // MIs[0] auxiliary
        GIM_CheckIsImm, /*MI*/0, /*Op*/7,
        // MIs[0] Operand 8
        GIM_CheckIsImm, /*MI*/0, /*Op*/8,
        GIM_CheckComplexPattern, /*MI*/0, /*Op*/4, /*Renderer*/GIMT_Encode2(0), GIMT_Encode2(GICP_gi_buf_soffset),
        // (SItbuffer_store v2f32:{ *:[v2f32] }:$vdata, v4i32:{ *:[v4i32] }:$rsrc, i32:{ *:[i32] }:$vindex, 0:{ *:[i32] }, (BUFSOffset:{ *:[i32] } i32:{ *:[i32] }:$soffset), (timm:{ *:[i32] }):$offset, (timm:{ *:[i32] }):$format, (timm:{ *:[i32] }):$auxiliary, (timm:{ *:[i1] }))  =>  (TBUFFER_STORE_FORMAT_XY_IDXEN_exact anonymous_15036:{ *:[v2f32] }:$vdata, VGPR_32:{ *:[i32] }:$vindex, SReg_128:{ *:[v4i32] }:$rsrc, SCSrc_b32:{ *:[i32] }:$soffset, (timm:{ *:[i32] }):$offset, (as_i8timm:{ *:[i8] } ?:{ *:[i32] }:$format), (extract_cpol:{ *:[i32] } ?:{ *:[i32] }:$auxiliary), (extract_swz:{ *:[i1] } ?:{ *:[i32] }:$auxiliary))
        GIR_BuildMI, /*InsnID*/0, /*Opcode*/GIMT_Encode2(AMDGPU::TBUFFER_STORE_FORMAT_XY_IDXEN_exact),
        GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/0, // vdata
        GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/2, // vindex
        GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/1, // rsrc
        GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/0, // soffset
        GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/5, // offset
        GIR_CustomOperandRenderer, /*InsnID*/0, /*OldInsnID*/0, /*OpIdx*/6, /*OperandRenderer*/GIMT_Encode2(GICR_renderTruncTImm), // format
        GIR_CustomOperandRenderer, /*InsnID*/0, /*OldInsnID*/0, /*OpIdx*/7, /*OperandRenderer*/GIMT_Encode2(GICR_renderExtractCPol), // auxiliary
        GIR_CustomOperandRenderer, /*InsnID*/0, /*OldInsnID*/0, /*OpIdx*/7, /*OperandRenderer*/GIMT_Encode2(GICR_renderExtractSWZ), // auxiliary
        GIR_MergeMemOperands, /*InsnID*/0, /*NumInsns*/1, /*MergeInsnID's*/0,
        GIR_ConstrainSelectedInstOperands, /*InsnID*/0,
        GIR_EraseFromParent, /*InsnID*/0,
        // GIR_Coverage, 5734,
        GIR_Done,
      // Label 7391: @540431
      GIM_Try, /*On fail goto*//*Label 7392*/ GIMT_Encode4(540511), // Rule ID 5738 //
        GIM_CheckConstantInt8, /*MI*/0, /*Op*/3, 0,
        // MIs[0] offset
        GIM_CheckIsImm, /*MI*/0, /*Op*/5,
        // MIs[0] format
        GIM_CheckIsImm, /*MI*/0, /*Op*/6,
        // MIs[0] auxiliary
        GIM_CheckIsImm, /*MI*/0, /*Op*/7,
        // MIs[0] Operand 8
        GIM_CheckIsImm, /*MI*/0, /*Op*/8,
        GIM_CheckComplexPattern, /*MI*/0, /*Op*/4, /*Renderer*/GIMT_Encode2(0), GIMT_Encode2(GICP_gi_buf_soffset),
        // (SItbuffer_store v2f32:{ *:[v2f32] }:$vdata, v4i32:{ *:[v4i32] }:$rsrc, i32:{ *:[i32] }:$vindex, 0:{ *:[i32] }, (BUFSOffset:{ *:[i32] } i32:{ *:[i32] }:$soffset), (timm:{ *:[i32] }):$offset, (timm:{ *:[i32] }):$format, (timm:{ *:[i32] }):$auxiliary, (timm:{ *:[i1] }))  =>  (TBUFFER_STORE_FORMAT_XY_VBUFFER_IDXEN_exact anonymous_15036:{ *:[v2f32] }:$vdata, VGPR_32:{ *:[i32] }:$vindex, SReg_128:{ *:[v4i32] }:$rsrc, SCSrc_b32:{ *:[i32] }:$soffset, (timm:{ *:[i32] }):$offset, (as_i8timm:{ *:[i8] } ?:{ *:[i32] }:$format), (extract_cpol:{ *:[i32] } ?:{ *:[i32] }:$auxiliary), (extract_swz:{ *:[i1] } ?:{ *:[i32] }:$auxiliary))
        GIR_BuildMI, /*InsnID*/0, /*Opcode*/GIMT_Encode2(AMDGPU::TBUFFER_STORE_FORMAT_XY_VBUFFER_IDXEN_exact),
        GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/0, // vdata
        GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/2, // vindex
        GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/1, // rsrc
        GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/0, // soffset
        GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/5, // offset
        GIR_CustomOperandRenderer, /*InsnID*/0, /*OldInsnID*/0, /*OpIdx*/6, /*OperandRenderer*/GIMT_Encode2(GICR_renderTruncTImm), // format
        GIR_CustomOperandRenderer, /*InsnID*/0, /*OldInsnID*/0, /*OpIdx*/7, /*OperandRenderer*/GIMT_Encode2(GICR_renderExtractCPol), // auxiliary
        GIR_CustomOperandRenderer, /*InsnID*/0, /*OldInsnID*/0, /*OpIdx*/7, /*OperandRenderer*/GIMT_Encode2(GICR_renderExtractSWZ), // auxiliary
        GIR_MergeMemOperands, /*InsnID*/0, /*NumInsns*/1, /*MergeInsnID's*/0,
        GIR_ConstrainSelectedInstOperands, /*InsnID*/0,
        GIR_EraseFromParent, /*InsnID*/0,
        // GIR_Coverage, 5738,
        GIR_Done,
      // Label 7392: @540511
      GIM_Try, /*On fail goto*//*Label 7393*/ GIMT_Encode4(540630), // Rule ID 5704 //
        GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasUnrestrictedSOffset),
        // MIs[0] offset
        GIM_CheckIsImm, /*MI*/0, /*Op*/5,
        // MIs[0] format
        GIM_CheckIsImm, /*MI*/0, /*Op*/6,
        // MIs[0] auxiliary
        GIM_CheckIsImm, /*MI*/0, /*Op*/7,
        // MIs[0] Operand 8
        GIM_CheckIsImm, /*MI*/0, /*Op*/8,
        GIM_CheckComplexPattern, /*MI*/0, /*Op*/4, /*Renderer*/GIMT_Encode2(0), GIMT_Encode2(GICP_gi_buf_soffset),
        // (SItbuffer_store v2i32:{ *:[v2i32] }:$vdata, v4i32:{ *:[v4i32] }:$rsrc, i32:{ *:[i32] }:$vindex, i32:{ *:[i32] }:$voffset, (BUFSOffset:{ *:[i32] } i32:{ *:[i32] }:$soffset), (timm:{ *:[i32] }):$offset, (timm:{ *:[i32] }):$format, (timm:{ *:[i32] }):$auxiliary, (timm:{ *:[i1] }))  =>  (TBUFFER_STORE_FORMAT_XY_BOTHEN_exact anonymous_15036:{ *:[v2i32] }:$vdata, (REG_SEQUENCE:{ *:[i64] } VReg_64:{ *:[i32] }, VGPR_32:{ *:[i32] }:$vindex, sub0:{ *:[i32] }, VGPR_32:{ *:[i32] }:$voffset, sub1:{ *:[i32] }), SReg_128:{ *:[v4i32] }:$rsrc, SCSrc_b32:{ *:[i32] }:$soffset, (timm:{ *:[i32] }):$offset, (as_i8timm:{ *:[i8] } ?:{ *:[i32] }:$format), (extract_cpol:{ *:[i32] } ?:{ *:[i32] }:$auxiliary), (extract_swz:{ *:[i1] } ?:{ *:[i32] }:$auxiliary))
        GIR_MakeTempReg, /*TempRegID*/0, /*TypeID*/GILLT_s64,
        GIR_BuildMI, /*InsnID*/1, /*Opcode*/GIMT_Encode2(TargetOpcode::REG_SEQUENCE),
        GIR_AddTempRegister, /*InsnID*/1, /*TempRegID*/0, /*TempRegFlags*/GIMT_Encode2(RegState::Define),
        GIR_Copy, /*NewInsnID*/1, /*OldInsnID*/0, /*OpIdx*/2, // vindex
        GIR_AddImm8, /*InsnID*/1, /*SubRegIndex*/3,
        GIR_Copy, /*NewInsnID*/1, /*OldInsnID*/0, /*OpIdx*/3, // voffset
        GIR_AddImm8, /*InsnID*/1, /*SubRegIndex*/11,
        GIR_ConstrainOperandRC, /*InsnID*/1, /*Op*/0, GIMT_Encode2(AMDGPU::VReg_64RegClassID),
        GIR_ConstrainOperandRC, /*InsnID*/1, /*Op*/1, GIMT_Encode2(AMDGPU::VGPR_32RegClassID),
        GIR_ConstrainOperandRC, /*InsnID*/1, /*Op*/3, GIMT_Encode2(AMDGPU::VGPR_32RegClassID),
        GIR_BuildMI, /*InsnID*/0, /*Opcode*/GIMT_Encode2(AMDGPU::TBUFFER_STORE_FORMAT_XY_BOTHEN_exact),
        GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/0, // vdata
        GIR_AddSimpleTempRegister, /*InsnID*/0, /*TempRegID*/0,
        GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/1, // rsrc
        GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/0, // soffset
        GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/5, // offset
        GIR_CustomOperandRenderer, /*InsnID*/0, /*OldInsnID*/0, /*OpIdx*/6, /*OperandRenderer*/GIMT_Encode2(GICR_renderTruncTImm), // format
        GIR_CustomOperandRenderer, /*InsnID*/0, /*OldInsnID*/0, /*OpIdx*/7, /*OperandRenderer*/GIMT_Encode2(GICR_renderExtractCPol), // auxiliary
        GIR_CustomOperandRenderer, /*InsnID*/0, /*OldInsnID*/0, /*OpIdx*/7, /*OperandRenderer*/GIMT_Encode2(GICR_renderExtractSWZ), // auxiliary
        GIR_MergeMemOperands, /*InsnID*/0, /*NumInsns*/1, /*MergeInsnID's*/0,
        GIR_ConstrainSelectedInstOperands, /*InsnID*/0,
        GIR_EraseFromParent, /*InsnID*/0,
        // GIR_Coverage, 5704,
        GIR_Done,
      // Label 7393: @540630
      GIM_Try, /*On fail goto*//*Label 7394*/ GIMT_Encode4(540746), // Rule ID 5708 //
        // MIs[0] offset
        GIM_CheckIsImm, /*MI*/0, /*Op*/5,
        // MIs[0] format
        GIM_CheckIsImm, /*MI*/0, /*Op*/6,
        // MIs[0] auxiliary
        GIM_CheckIsImm, /*MI*/0, /*Op*/7,
        // MIs[0] Operand 8
        GIM_CheckIsImm, /*MI*/0, /*Op*/8,
        GIM_CheckComplexPattern, /*MI*/0, /*Op*/4, /*Renderer*/GIMT_Encode2(0), GIMT_Encode2(GICP_gi_buf_soffset),
        // (SItbuffer_store v2i32:{ *:[v2i32] }:$vdata, v4i32:{ *:[v4i32] }:$rsrc, i32:{ *:[i32] }:$vindex, i32:{ *:[i32] }:$voffset, (BUFSOffset:{ *:[i32] } i32:{ *:[i32] }:$soffset), (timm:{ *:[i32] }):$offset, (timm:{ *:[i32] }):$format, (timm:{ *:[i32] }):$auxiliary, (timm:{ *:[i1] }))  =>  (TBUFFER_STORE_FORMAT_XY_VBUFFER_BOTHEN_exact anonymous_15036:{ *:[v2i32] }:$vdata, (REG_SEQUENCE:{ *:[i64] } VReg_64:{ *:[i32] }, VGPR_32:{ *:[i32] }:$vindex, sub0:{ *:[i32] }, VGPR_32:{ *:[i32] }:$voffset, sub1:{ *:[i32] }), SReg_128:{ *:[v4i32] }:$rsrc, SCSrc_b32:{ *:[i32] }:$soffset, (timm:{ *:[i32] }):$offset, (as_i8timm:{ *:[i8] } ?:{ *:[i32] }:$format), (extract_cpol:{ *:[i32] } ?:{ *:[i32] }:$auxiliary), (extract_swz:{ *:[i1] } ?:{ *:[i32] }:$auxiliary))
        GIR_MakeTempReg, /*TempRegID*/0, /*TypeID*/GILLT_s64,
        GIR_BuildMI, /*InsnID*/1, /*Opcode*/GIMT_Encode2(TargetOpcode::REG_SEQUENCE),
        GIR_AddTempRegister, /*InsnID*/1, /*TempRegID*/0, /*TempRegFlags*/GIMT_Encode2(RegState::Define),
        GIR_Copy, /*NewInsnID*/1, /*OldInsnID*/0, /*OpIdx*/2, // vindex
        GIR_AddImm8, /*InsnID*/1, /*SubRegIndex*/3,
        GIR_Copy, /*NewInsnID*/1, /*OldInsnID*/0, /*OpIdx*/3, // voffset
        GIR_AddImm8, /*InsnID*/1, /*SubRegIndex*/11,
        GIR_ConstrainOperandRC, /*InsnID*/1, /*Op*/0, GIMT_Encode2(AMDGPU::VReg_64RegClassID),
        GIR_ConstrainOperandRC, /*InsnID*/1, /*Op*/1, GIMT_Encode2(AMDGPU::VGPR_32RegClassID),
        GIR_ConstrainOperandRC, /*InsnID*/1, /*Op*/3, GIMT_Encode2(AMDGPU::VGPR_32RegClassID),
        GIR_BuildMI, /*InsnID*/0, /*Opcode*/GIMT_Encode2(AMDGPU::TBUFFER_STORE_FORMAT_XY_VBUFFER_BOTHEN_exact),
        GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/0, // vdata
        GIR_AddSimpleTempRegister, /*InsnID*/0, /*TempRegID*/0,
        GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/1, // rsrc
        GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/0, // soffset
        GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/5, // offset
        GIR_CustomOperandRenderer, /*InsnID*/0, /*OldInsnID*/0, /*OpIdx*/6, /*OperandRenderer*/GIMT_Encode2(GICR_renderTruncTImm), // format
        GIR_CustomOperandRenderer, /*InsnID*/0, /*OldInsnID*/0, /*OpIdx*/7, /*OperandRenderer*/GIMT_Encode2(GICR_renderExtractCPol), // auxiliary
        GIR_CustomOperandRenderer, /*InsnID*/0, /*OldInsnID*/0, /*OpIdx*/7, /*OperandRenderer*/GIMT_Encode2(GICR_renderExtractSWZ), // auxiliary
        GIR_MergeMemOperands, /*InsnID*/0, /*NumInsns*/1, /*MergeInsnID's*/0,
        GIR_ConstrainSelectedInstOperands, /*InsnID*/0,
        GIR_EraseFromParent, /*InsnID*/0,
        // GIR_Coverage, 5708,
        GIR_Done,
      // Label 7394: @540746
      GIM_Try, /*On fail goto*//*Label 7395*/ GIMT_Encode4(540865), // Rule ID 5736 //
        GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasUnrestrictedSOffset),
        // MIs[0] offset
        GIM_CheckIsImm, /*MI*/0, /*Op*/5,
        // MIs[0] format
        GIM_CheckIsImm, /*MI*/0, /*Op*/6,
        // MIs[0] auxiliary
        GIM_CheckIsImm, /*MI*/0, /*Op*/7,
        // MIs[0] Operand 8
        GIM_CheckIsImm, /*MI*/0, /*Op*/8,
        GIM_CheckComplexPattern, /*MI*/0, /*Op*/4, /*Renderer*/GIMT_Encode2(0), GIMT_Encode2(GICP_gi_buf_soffset),
        // (SItbuffer_store v2f32:{ *:[v2f32] }:$vdata, v4i32:{ *:[v4i32] }:$rsrc, i32:{ *:[i32] }:$vindex, i32:{ *:[i32] }:$voffset, (BUFSOffset:{ *:[i32] } i32:{ *:[i32] }:$soffset), (timm:{ *:[i32] }):$offset, (timm:{ *:[i32] }):$format, (timm:{ *:[i32] }):$auxiliary, (timm:{ *:[i1] }))  =>  (TBUFFER_STORE_FORMAT_XY_BOTHEN_exact anonymous_15036:{ *:[v2f32] }:$vdata, (REG_SEQUENCE:{ *:[i64] } VReg_64:{ *:[i32] }, VGPR_32:{ *:[i32] }:$vindex, sub0:{ *:[i32] }, VGPR_32:{ *:[i32] }:$voffset, sub1:{ *:[i32] }), SReg_128:{ *:[v4i32] }:$rsrc, SCSrc_b32:{ *:[i32] }:$soffset, (timm:{ *:[i32] }):$offset, (as_i8timm:{ *:[i8] } ?:{ *:[i32] }:$format), (extract_cpol:{ *:[i32] } ?:{ *:[i32] }:$auxiliary), (extract_swz:{ *:[i1] } ?:{ *:[i32] }:$auxiliary))
        GIR_MakeTempReg, /*TempRegID*/0, /*TypeID*/GILLT_s64,
        GIR_BuildMI, /*InsnID*/1, /*Opcode*/GIMT_Encode2(TargetOpcode::REG_SEQUENCE),
        GIR_AddTempRegister, /*InsnID*/1, /*TempRegID*/0, /*TempRegFlags*/GIMT_Encode2(RegState::Define),
        GIR_Copy, /*NewInsnID*/1, /*OldInsnID*/0, /*OpIdx*/2, // vindex
        GIR_AddImm8, /*InsnID*/1, /*SubRegIndex*/3,
        GIR_Copy, /*NewInsnID*/1, /*OldInsnID*/0, /*OpIdx*/3, // voffset
        GIR_AddImm8, /*InsnID*/1, /*SubRegIndex*/11,
        GIR_ConstrainOperandRC, /*InsnID*/1, /*Op*/0, GIMT_Encode2(AMDGPU::VReg_64RegClassID),
        GIR_ConstrainOperandRC, /*InsnID*/1, /*Op*/1, GIMT_Encode2(AMDGPU::VGPR_32RegClassID),
        GIR_ConstrainOperandRC, /*InsnID*/1, /*Op*/3, GIMT_Encode2(AMDGPU::VGPR_32RegClassID),
        GIR_BuildMI, /*InsnID*/0, /*Opcode*/GIMT_Encode2(AMDGPU::TBUFFER_STORE_FORMAT_XY_BOTHEN_exact),
        GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/0, // vdata
        GIR_AddSimpleTempRegister, /*InsnID*/0, /*TempRegID*/0,
        GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/1, // rsrc
        GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/0, // soffset
        GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/5, // offset
        GIR_CustomOperandRenderer, /*InsnID*/0, /*OldInsnID*/0, /*OpIdx*/6, /*OperandRenderer*/GIMT_Encode2(GICR_renderTruncTImm), // format
        GIR_CustomOperandRenderer, /*InsnID*/0, /*OldInsnID*/0, /*OpIdx*/7, /*OperandRenderer*/GIMT_Encode2(GICR_renderExtractCPol), // auxiliary
        GIR_CustomOperandRenderer, /*InsnID*/0, /*OldInsnID*/0, /*OpIdx*/7, /*OperandRenderer*/GIMT_Encode2(GICR_renderExtractSWZ), // auxiliary
        GIR_MergeMemOperands, /*InsnID*/0, /*NumInsns*/1, /*MergeInsnID's*/0,
        GIR_ConstrainSelectedInstOperands, /*InsnID*/0,
        GIR_EraseFromParent, /*InsnID*/0,
        // GIR_Coverage, 5736,
        GIR_Done,
      // Label 7395: @540865
      GIM_Try, /*On fail goto*//*Label 7396*/ GIMT_Encode4(540981), // Rule ID 5740 //
        // MIs[0] offset
        GIM_CheckIsImm, /*MI*/0, /*Op*/5,
        // MIs[0] format
        GIM_CheckIsImm, /*MI*/0, /*Op*/6,
        // MIs[0] auxiliary
        GIM_CheckIsImm, /*MI*/0, /*Op*/7,
        // MIs[0] Operand 8
        GIM_CheckIsImm, /*MI*/0, /*Op*/8,
        GIM_CheckComplexPattern, /*MI*/0, /*Op*/4, /*Renderer*/GIMT_Encode2(0), GIMT_Encode2(GICP_gi_buf_soffset),
        // (SItbuffer_store v2f32:{ *:[v2f32] }:$vdata, v4i32:{ *:[v4i32] }:$rsrc, i32:{ *:[i32] }:$vindex, i32:{ *:[i32] }:$voffset, (BUFSOffset:{ *:[i32] } i32:{ *:[i32] }:$soffset), (timm:{ *:[i32] }):$offset, (timm:{ *:[i32] }):$format, (timm:{ *:[i32] }):$auxiliary, (timm:{ *:[i1] }))  =>  (TBUFFER_STORE_FORMAT_XY_VBUFFER_BOTHEN_exact anonymous_15036:{ *:[v2f32] }:$vdata, (REG_SEQUENCE:{ *:[i64] } VReg_64:{ *:[i32] }, VGPR_32:{ *:[i32] }:$vindex, sub0:{ *:[i32] }, VGPR_32:{ *:[i32] }:$voffset, sub1:{ *:[i32] }), SReg_128:{ *:[v4i32] }:$rsrc, SCSrc_b32:{ *:[i32] }:$soffset, (timm:{ *:[i32] }):$offset, (as_i8timm:{ *:[i8] } ?:{ *:[i32] }:$format), (extract_cpol:{ *:[i32] } ?:{ *:[i32] }:$auxiliary), (extract_swz:{ *:[i1] } ?:{ *:[i32] }:$auxiliary))
        GIR_MakeTempReg, /*TempRegID*/0, /*TypeID*/GILLT_s64,
        GIR_BuildMI, /*InsnID*/1, /*Opcode*/GIMT_Encode2(TargetOpcode::REG_SEQUENCE),
        GIR_AddTempRegister, /*InsnID*/1, /*TempRegID*/0, /*TempRegFlags*/GIMT_Encode2(RegState::Define),
        GIR_Copy, /*NewInsnID*/1, /*OldInsnID*/0, /*OpIdx*/2, // vindex
        GIR_AddImm8, /*InsnID*/1, /*SubRegIndex*/3,
        GIR_Copy, /*NewInsnID*/1, /*OldInsnID*/0, /*OpIdx*/3, // voffset
        GIR_AddImm8, /*InsnID*/1, /*SubRegIndex*/11,
        GIR_ConstrainOperandRC, /*InsnID*/1, /*Op*/0, GIMT_Encode2(AMDGPU::VReg_64RegClassID),
        GIR_ConstrainOperandRC, /*InsnID*/1, /*Op*/1, GIMT_Encode2(AMDGPU::VGPR_32RegClassID),
        GIR_ConstrainOperandRC, /*InsnID*/1, /*Op*/3, GIMT_Encode2(AMDGPU::VGPR_32RegClassID),
        GIR_BuildMI, /*InsnID*/0, /*Opcode*/GIMT_Encode2(AMDGPU::TBUFFER_STORE_FORMAT_XY_VBUFFER_BOTHEN_exact),
        GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/0, // vdata
        GIR_AddSimpleTempRegister, /*InsnID*/0, /*TempRegID*/0,
        GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/1, // rsrc
        GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/0, // soffset
        GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/5, // offset
        GIR_CustomOperandRenderer, /*InsnID*/0, /*OldInsnID*/0, /*OpIdx*/6, /*OperandRenderer*/GIMT_Encode2(GICR_renderTruncTImm), // format
        GIR_CustomOperandRenderer, /*InsnID*/0, /*OldInsnID*/0, /*OpIdx*/7, /*OperandRenderer*/GIMT_Encode2(GICR_renderExtractCPol), // auxiliary
        GIR_CustomOperandRenderer, /*InsnID*/0, /*OldInsnID*/0, /*OpIdx*/7, /*OperandRenderer*/GIMT_Encode2(GICR_renderExtractSWZ), // auxiliary
        GIR_MergeMemOperands, /*InsnID*/0, /*NumInsns*/1, /*MergeInsnID's*/0,
        GIR_ConstrainSelectedInstOperands, /*InsnID*/0,
        GIR_EraseFromParent, /*InsnID*/0,
        // GIR_Coverage, 5740,
        GIR_Done,
      // Label 7396: @540981
      GIM_Reject,
    // Label 7380: @540982
    GIM_Reject,
    // Label 7360: @540983
    GIM_Try, /*On fail goto*//*Label 7397*/ GIMT_Encode4(542517),
      GIM_CheckType, /*MI*/0, /*Op*/1, /*Type*/GILLT_v4s32,
      GIM_CheckType, /*MI*/0, /*Op*/2, /*Type*/GILLT_s32,
      GIM_CheckType, /*MI*/0, /*Op*/3, /*Type*/GILLT_s32,
      GIM_CheckType, /*MI*/0, /*Op*/4, /*Type*/GILLT_s32,
      GIM_Try, /*On fail goto*//*Label 7398*/ GIMT_Encode4(541095), // Rule ID 5709 //
        GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasUnrestrictedSOffset),
        GIM_CheckConstantInt8, /*MI*/0, /*Op*/2, 0,
        GIM_CheckConstantInt8, /*MI*/0, /*Op*/3, 0,
        // MIs[0] offset
        GIM_CheckIsImm, /*MI*/0, /*Op*/5,
        // MIs[0] format
        GIM_CheckIsImm, /*MI*/0, /*Op*/6,
        // MIs[0] auxiliary
        GIM_CheckIsImm, /*MI*/0, /*Op*/7,
        // MIs[0] Operand 8
        GIM_CheckLiteralInt, /*MI*/0, /*Op*/8, GIMT_Encode8(0),
        GIM_CheckComplexPattern, /*MI*/0, /*Op*/4, /*Renderer*/GIMT_Encode2(0), GIMT_Encode2(GICP_gi_buf_soffset),
        // (SItbuffer_store v3i32:{ *:[v3i32] }:$vdata, v4i32:{ *:[v4i32] }:$rsrc, 0:{ *:[i32] }, 0:{ *:[i32] }, (BUFSOffset:{ *:[i32] } i32:{ *:[i32] }:$soffset), (timm:{ *:[i32] }):$offset, (timm:{ *:[i32] }):$format, (timm:{ *:[i32] }):$auxiliary, 0:{ *:[i1] })  =>  (TBUFFER_STORE_FORMAT_XYZ_OFFSET_exact anonymous_15035:{ *:[v3i32] }:$vdata, SReg_128:{ *:[v4i32] }:$rsrc, SCSrc_b32:{ *:[i32] }:$soffset, (timm:{ *:[i32] }):$offset, (as_i8timm:{ *:[i8] } ?:{ *:[i32] }:$format), (extract_cpol:{ *:[i32] } ?:{ *:[i32] }:$auxiliary), (extract_swz:{ *:[i1] } ?:{ *:[i32] }:$auxiliary))
        GIR_BuildMI, /*InsnID*/0, /*Opcode*/GIMT_Encode2(AMDGPU::TBUFFER_STORE_FORMAT_XYZ_OFFSET_exact),
        GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/0, // vdata
        GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/1, // rsrc
        GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/0, // soffset
        GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/5, // offset
        GIR_CustomOperandRenderer, /*InsnID*/0, /*OldInsnID*/0, /*OpIdx*/6, /*OperandRenderer*/GIMT_Encode2(GICR_renderTruncTImm), // format
        GIR_CustomOperandRenderer, /*InsnID*/0, /*OldInsnID*/0, /*OpIdx*/7, /*OperandRenderer*/GIMT_Encode2(GICR_renderExtractCPol), // auxiliary
        GIR_CustomOperandRenderer, /*InsnID*/0, /*OldInsnID*/0, /*OpIdx*/7, /*OperandRenderer*/GIMT_Encode2(GICR_renderExtractSWZ), // auxiliary
        GIR_MergeMemOperands, /*InsnID*/0, /*NumInsns*/1, /*MergeInsnID's*/0,
        GIR_ConstrainSelectedInstOperands, /*InsnID*/0,
        GIR_EraseFromParent, /*InsnID*/0,
        // GIR_Coverage, 5709,
        GIR_Done,
      // Label 7398: @541095
      GIM_Try, /*On fail goto*//*Label 7399*/ GIMT_Encode4(541183), // Rule ID 5713 //
        GIM_CheckConstantInt8, /*MI*/0, /*Op*/2, 0,
        GIM_CheckConstantInt8, /*MI*/0, /*Op*/3, 0,
        // MIs[0] offset
        GIM_CheckIsImm, /*MI*/0, /*Op*/5,
        // MIs[0] format
        GIM_CheckIsImm, /*MI*/0, /*Op*/6,
        // MIs[0] auxiliary
        GIM_CheckIsImm, /*MI*/0, /*Op*/7,
        // MIs[0] Operand 8
        GIM_CheckLiteralInt, /*MI*/0, /*Op*/8, GIMT_Encode8(0),
        GIM_CheckComplexPattern, /*MI*/0, /*Op*/4, /*Renderer*/GIMT_Encode2(0), GIMT_Encode2(GICP_gi_buf_soffset),
        // (SItbuffer_store v3i32:{ *:[v3i32] }:$vdata, v4i32:{ *:[v4i32] }:$rsrc, 0:{ *:[i32] }, 0:{ *:[i32] }, (BUFSOffset:{ *:[i32] } i32:{ *:[i32] }:$soffset), (timm:{ *:[i32] }):$offset, (timm:{ *:[i32] }):$format, (timm:{ *:[i32] }):$auxiliary, 0:{ *:[i1] })  =>  (TBUFFER_STORE_FORMAT_XYZ_VBUFFER_OFFSET_exact anonymous_15035:{ *:[v3i32] }:$vdata, SReg_128:{ *:[v4i32] }:$rsrc, SCSrc_b32:{ *:[i32] }:$soffset, (timm:{ *:[i32] }):$offset, (as_i8timm:{ *:[i8] } ?:{ *:[i32] }:$format), (extract_cpol:{ *:[i32] } ?:{ *:[i32] }:$auxiliary), (extract_swz:{ *:[i1] } ?:{ *:[i32] }:$auxiliary))
        GIR_BuildMI, /*InsnID*/0, /*Opcode*/GIMT_Encode2(AMDGPU::TBUFFER_STORE_FORMAT_XYZ_VBUFFER_OFFSET_exact),
        GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/0, // vdata
        GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/1, // rsrc
        GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/0, // soffset
        GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/5, // offset
        GIR_CustomOperandRenderer, /*InsnID*/0, /*OldInsnID*/0, /*OpIdx*/6, /*OperandRenderer*/GIMT_Encode2(GICR_renderTruncTImm), // format
        GIR_CustomOperandRenderer, /*InsnID*/0, /*OldInsnID*/0, /*OpIdx*/7, /*OperandRenderer*/GIMT_Encode2(GICR_renderExtractCPol), // auxiliary
        GIR_CustomOperandRenderer, /*InsnID*/0, /*OldInsnID*/0, /*OpIdx*/7, /*OperandRenderer*/GIMT_Encode2(GICR_renderExtractSWZ), // auxiliary
        GIR_MergeMemOperands, /*InsnID*/0, /*NumInsns*/1, /*MergeInsnID's*/0,
        GIR_ConstrainSelectedInstOperands, /*InsnID*/0,
        GIR_EraseFromParent, /*InsnID*/0,
        // GIR_Coverage, 5713,
        GIR_Done,
      // Label 7399: @541183
      GIM_Try, /*On fail goto*//*Label 7400*/ GIMT_Encode4(541274), // Rule ID 5741 //
        GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasUnrestrictedSOffset),
        GIM_CheckConstantInt8, /*MI*/0, /*Op*/2, 0,
        GIM_CheckConstantInt8, /*MI*/0, /*Op*/3, 0,
        // MIs[0] offset
        GIM_CheckIsImm, /*MI*/0, /*Op*/5,
        // MIs[0] format
        GIM_CheckIsImm, /*MI*/0, /*Op*/6,
        // MIs[0] auxiliary
        GIM_CheckIsImm, /*MI*/0, /*Op*/7,
        // MIs[0] Operand 8
        GIM_CheckLiteralInt, /*MI*/0, /*Op*/8, GIMT_Encode8(0),
        GIM_CheckComplexPattern, /*MI*/0, /*Op*/4, /*Renderer*/GIMT_Encode2(0), GIMT_Encode2(GICP_gi_buf_soffset),
        // (SItbuffer_store v3f32:{ *:[v3f32] }:$vdata, v4i32:{ *:[v4i32] }:$rsrc, 0:{ *:[i32] }, 0:{ *:[i32] }, (BUFSOffset:{ *:[i32] } i32:{ *:[i32] }:$soffset), (timm:{ *:[i32] }):$offset, (timm:{ *:[i32] }):$format, (timm:{ *:[i32] }):$auxiliary, 0:{ *:[i1] })  =>  (TBUFFER_STORE_FORMAT_XYZ_OFFSET_exact anonymous_15035:{ *:[v3f32] }:$vdata, SReg_128:{ *:[v4i32] }:$rsrc, SCSrc_b32:{ *:[i32] }:$soffset, (timm:{ *:[i32] }):$offset, (as_i8timm:{ *:[i8] } ?:{ *:[i32] }:$format), (extract_cpol:{ *:[i32] } ?:{ *:[i32] }:$auxiliary), (extract_swz:{ *:[i1] } ?:{ *:[i32] }:$auxiliary))
        GIR_BuildMI, /*InsnID*/0, /*Opcode*/GIMT_Encode2(AMDGPU::TBUFFER_STORE_FORMAT_XYZ_OFFSET_exact),
        GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/0, // vdata
        GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/1, // rsrc
        GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/0, // soffset
        GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/5, // offset
        GIR_CustomOperandRenderer, /*InsnID*/0, /*OldInsnID*/0, /*OpIdx*/6, /*OperandRenderer*/GIMT_Encode2(GICR_renderTruncTImm), // format
        GIR_CustomOperandRenderer, /*InsnID*/0, /*OldInsnID*/0, /*OpIdx*/7, /*OperandRenderer*/GIMT_Encode2(GICR_renderExtractCPol), // auxiliary
        GIR_CustomOperandRenderer, /*InsnID*/0, /*OldInsnID*/0, /*OpIdx*/7, /*OperandRenderer*/GIMT_Encode2(GICR_renderExtractSWZ), // auxiliary
        GIR_MergeMemOperands, /*InsnID*/0, /*NumInsns*/1, /*MergeInsnID's*/0,
        GIR_ConstrainSelectedInstOperands, /*InsnID*/0,
        GIR_EraseFromParent, /*InsnID*/0,
        // GIR_Coverage, 5741,
        GIR_Done,
      // Label 7400: @541274
      GIM_Try, /*On fail goto*//*Label 7401*/ GIMT_Encode4(541362), // Rule ID 5745 //
        GIM_CheckConstantInt8, /*MI*/0, /*Op*/2, 0,
        GIM_CheckConstantInt8, /*MI*/0, /*Op*/3, 0,
        // MIs[0] offset
        GIM_CheckIsImm, /*MI*/0, /*Op*/5,
        // MIs[0] format
        GIM_CheckIsImm, /*MI*/0, /*Op*/6,
        // MIs[0] auxiliary
        GIM_CheckIsImm, /*MI*/0, /*Op*/7,
        // MIs[0] Operand 8
        GIM_CheckLiteralInt, /*MI*/0, /*Op*/8, GIMT_Encode8(0),
        GIM_CheckComplexPattern, /*MI*/0, /*Op*/4, /*Renderer*/GIMT_Encode2(0), GIMT_Encode2(GICP_gi_buf_soffset),
        // (SItbuffer_store v3f32:{ *:[v3f32] }:$vdata, v4i32:{ *:[v4i32] }:$rsrc, 0:{ *:[i32] }, 0:{ *:[i32] }, (BUFSOffset:{ *:[i32] } i32:{ *:[i32] }:$soffset), (timm:{ *:[i32] }):$offset, (timm:{ *:[i32] }):$format, (timm:{ *:[i32] }):$auxiliary, 0:{ *:[i1] })  =>  (TBUFFER_STORE_FORMAT_XYZ_VBUFFER_OFFSET_exact anonymous_15035:{ *:[v3f32] }:$vdata, SReg_128:{ *:[v4i32] }:$rsrc, SCSrc_b32:{ *:[i32] }:$soffset, (timm:{ *:[i32] }):$offset, (as_i8timm:{ *:[i8] } ?:{ *:[i32] }:$format), (extract_cpol:{ *:[i32] } ?:{ *:[i32] }:$auxiliary), (extract_swz:{ *:[i1] } ?:{ *:[i32] }:$auxiliary))
        GIR_BuildMI, /*InsnID*/0, /*Opcode*/GIMT_Encode2(AMDGPU::TBUFFER_STORE_FORMAT_XYZ_VBUFFER_OFFSET_exact),
        GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/0, // vdata
        GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/1, // rsrc
        GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/0, // soffset
        GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/5, // offset
        GIR_CustomOperandRenderer, /*InsnID*/0, /*OldInsnID*/0, /*OpIdx*/6, /*OperandRenderer*/GIMT_Encode2(GICR_renderTruncTImm), // format
        GIR_CustomOperandRenderer, /*InsnID*/0, /*OldInsnID*/0, /*OpIdx*/7, /*OperandRenderer*/GIMT_Encode2(GICR_renderExtractCPol), // auxiliary
        GIR_CustomOperandRenderer, /*InsnID*/0, /*OldInsnID*/0, /*OpIdx*/7, /*OperandRenderer*/GIMT_Encode2(GICR_renderExtractSWZ), // auxiliary
        GIR_MergeMemOperands, /*InsnID*/0, /*NumInsns*/1, /*MergeInsnID's*/0,
        GIR_ConstrainSelectedInstOperands, /*InsnID*/0,
        GIR_EraseFromParent, /*InsnID*/0,
        // GIR_Coverage, 5745,
        GIR_Done,
      // Label 7401: @541362
      GIM_Try, /*On fail goto*//*Label 7402*/ GIMT_Encode4(541453), // Rule ID 5711 //
        GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasUnrestrictedSOffset),
        GIM_CheckConstantInt8, /*MI*/0, /*Op*/2, 0,
        // MIs[0] offset
        GIM_CheckIsImm, /*MI*/0, /*Op*/5,
        // MIs[0] format
        GIM_CheckIsImm, /*MI*/0, /*Op*/6,
        // MIs[0] auxiliary
        GIM_CheckIsImm, /*MI*/0, /*Op*/7,
        // MIs[0] Operand 8
        GIM_CheckLiteralInt, /*MI*/0, /*Op*/8, GIMT_Encode8(0),
        GIM_CheckComplexPattern, /*MI*/0, /*Op*/4, /*Renderer*/GIMT_Encode2(0), GIMT_Encode2(GICP_gi_buf_soffset),
        // (SItbuffer_store v3i32:{ *:[v3i32] }:$vdata, v4i32:{ *:[v4i32] }:$rsrc, 0:{ *:[i32] }, i32:{ *:[i32] }:$voffset, (BUFSOffset:{ *:[i32] } i32:{ *:[i32] }:$soffset), (timm:{ *:[i32] }):$offset, (timm:{ *:[i32] }):$format, (timm:{ *:[i32] }):$auxiliary, 0:{ *:[i1] })  =>  (TBUFFER_STORE_FORMAT_XYZ_OFFEN_exact anonymous_15035:{ *:[v3i32] }:$vdata, VGPR_32:{ *:[i32] }:$voffset, SReg_128:{ *:[v4i32] }:$rsrc, SCSrc_b32:{ *:[i32] }:$soffset, (timm:{ *:[i32] }):$offset, (as_i8timm:{ *:[i8] } ?:{ *:[i32] }:$format), (extract_cpol:{ *:[i32] } ?:{ *:[i32] }:$auxiliary), (extract_swz:{ *:[i1] } ?:{ *:[i32] }:$auxiliary))
        GIR_BuildMI, /*InsnID*/0, /*Opcode*/GIMT_Encode2(AMDGPU::TBUFFER_STORE_FORMAT_XYZ_OFFEN_exact),
        GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/0, // vdata
        GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/3, // voffset
        GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/1, // rsrc
        GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/0, // soffset
        GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/5, // offset
        GIR_CustomOperandRenderer, /*InsnID*/0, /*OldInsnID*/0, /*OpIdx*/6, /*OperandRenderer*/GIMT_Encode2(GICR_renderTruncTImm), // format
        GIR_CustomOperandRenderer, /*InsnID*/0, /*OldInsnID*/0, /*OpIdx*/7, /*OperandRenderer*/GIMT_Encode2(GICR_renderExtractCPol), // auxiliary
        GIR_CustomOperandRenderer, /*InsnID*/0, /*OldInsnID*/0, /*OpIdx*/7, /*OperandRenderer*/GIMT_Encode2(GICR_renderExtractSWZ), // auxiliary
        GIR_MergeMemOperands, /*InsnID*/0, /*NumInsns*/1, /*MergeInsnID's*/0,
        GIR_ConstrainSelectedInstOperands, /*InsnID*/0,
        GIR_EraseFromParent, /*InsnID*/0,
        // GIR_Coverage, 5711,
        GIR_Done,
      // Label 7402: @541453
      GIM_Try, /*On fail goto*//*Label 7403*/ GIMT_Encode4(541541), // Rule ID 5715 //
        GIM_CheckConstantInt8, /*MI*/0, /*Op*/2, 0,
        // MIs[0] offset
        GIM_CheckIsImm, /*MI*/0, /*Op*/5,
        // MIs[0] format
        GIM_CheckIsImm, /*MI*/0, /*Op*/6,
        // MIs[0] auxiliary
        GIM_CheckIsImm, /*MI*/0, /*Op*/7,
        // MIs[0] Operand 8
        GIM_CheckLiteralInt, /*MI*/0, /*Op*/8, GIMT_Encode8(0),
        GIM_CheckComplexPattern, /*MI*/0, /*Op*/4, /*Renderer*/GIMT_Encode2(0), GIMT_Encode2(GICP_gi_buf_soffset),
        // (SItbuffer_store v3i32:{ *:[v3i32] }:$vdata, v4i32:{ *:[v4i32] }:$rsrc, 0:{ *:[i32] }, i32:{ *:[i32] }:$voffset, (BUFSOffset:{ *:[i32] } i32:{ *:[i32] }:$soffset), (timm:{ *:[i32] }):$offset, (timm:{ *:[i32] }):$format, (timm:{ *:[i32] }):$auxiliary, 0:{ *:[i1] })  =>  (TBUFFER_STORE_FORMAT_XYZ_VBUFFER_OFFEN_exact anonymous_15035:{ *:[v3i32] }:$vdata, VGPR_32:{ *:[i32] }:$voffset, SReg_128:{ *:[v4i32] }:$rsrc, SCSrc_b32:{ *:[i32] }:$soffset, (timm:{ *:[i32] }):$offset, (as_i8timm:{ *:[i8] } ?:{ *:[i32] }:$format), (extract_cpol:{ *:[i32] } ?:{ *:[i32] }:$auxiliary), (extract_swz:{ *:[i1] } ?:{ *:[i32] }:$auxiliary))
        GIR_BuildMI, /*InsnID*/0, /*Opcode*/GIMT_Encode2(AMDGPU::TBUFFER_STORE_FORMAT_XYZ_VBUFFER_OFFEN_exact),
        GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/0, // vdata
        GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/3, // voffset
        GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/1, // rsrc
        GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/0, // soffset
        GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/5, // offset
        GIR_CustomOperandRenderer, /*InsnID*/0, /*OldInsnID*/0, /*OpIdx*/6, /*OperandRenderer*/GIMT_Encode2(GICR_renderTruncTImm), // format
        GIR_CustomOperandRenderer, /*InsnID*/0, /*OldInsnID*/0, /*OpIdx*/7, /*OperandRenderer*/GIMT_Encode2(GICR_renderExtractCPol), // auxiliary
        GIR_CustomOperandRenderer, /*InsnID*/0, /*OldInsnID*/0, /*OpIdx*/7, /*OperandRenderer*/GIMT_Encode2(GICR_renderExtractSWZ), // auxiliary
        GIR_MergeMemOperands, /*InsnID*/0, /*NumInsns*/1, /*MergeInsnID's*/0,
        GIR_ConstrainSelectedInstOperands, /*InsnID*/0,
        GIR_EraseFromParent, /*InsnID*/0,
        // GIR_Coverage, 5715,
        GIR_Done,
      // Label 7403: @541541
      GIM_Try, /*On fail goto*//*Label 7404*/ GIMT_Encode4(541632), // Rule ID 5743 //
        GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasUnrestrictedSOffset),
        GIM_CheckConstantInt8, /*MI*/0, /*Op*/2, 0,
        // MIs[0] offset
        GIM_CheckIsImm, /*MI*/0, /*Op*/5,
        // MIs[0] format
        GIM_CheckIsImm, /*MI*/0, /*Op*/6,
        // MIs[0] auxiliary
        GIM_CheckIsImm, /*MI*/0, /*Op*/7,
        // MIs[0] Operand 8
        GIM_CheckLiteralInt, /*MI*/0, /*Op*/8, GIMT_Encode8(0),
        GIM_CheckComplexPattern, /*MI*/0, /*Op*/4, /*Renderer*/GIMT_Encode2(0), GIMT_Encode2(GICP_gi_buf_soffset),
        // (SItbuffer_store v3f32:{ *:[v3f32] }:$vdata, v4i32:{ *:[v4i32] }:$rsrc, 0:{ *:[i32] }, i32:{ *:[i32] }:$voffset, (BUFSOffset:{ *:[i32] } i32:{ *:[i32] }:$soffset), (timm:{ *:[i32] }):$offset, (timm:{ *:[i32] }):$format, (timm:{ *:[i32] }):$auxiliary, 0:{ *:[i1] })  =>  (TBUFFER_STORE_FORMAT_XYZ_OFFEN_exact anonymous_15035:{ *:[v3f32] }:$vdata, VGPR_32:{ *:[i32] }:$voffset, SReg_128:{ *:[v4i32] }:$rsrc, SCSrc_b32:{ *:[i32] }:$soffset, (timm:{ *:[i32] }):$offset, (as_i8timm:{ *:[i8] } ?:{ *:[i32] }:$format), (extract_cpol:{ *:[i32] } ?:{ *:[i32] }:$auxiliary), (extract_swz:{ *:[i1] } ?:{ *:[i32] }:$auxiliary))
        GIR_BuildMI, /*InsnID*/0, /*Opcode*/GIMT_Encode2(AMDGPU::TBUFFER_STORE_FORMAT_XYZ_OFFEN_exact),
        GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/0, // vdata
        GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/3, // voffset
        GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/1, // rsrc
        GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/0, // soffset
        GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/5, // offset
        GIR_CustomOperandRenderer, /*InsnID*/0, /*OldInsnID*/0, /*OpIdx*/6, /*OperandRenderer*/GIMT_Encode2(GICR_renderTruncTImm), // format
        GIR_CustomOperandRenderer, /*InsnID*/0, /*OldInsnID*/0, /*OpIdx*/7, /*OperandRenderer*/GIMT_Encode2(GICR_renderExtractCPol), // auxiliary
        GIR_CustomOperandRenderer, /*InsnID*/0, /*OldInsnID*/0, /*OpIdx*/7, /*OperandRenderer*/GIMT_Encode2(GICR_renderExtractSWZ), // auxiliary
        GIR_MergeMemOperands, /*InsnID*/0, /*NumInsns*/1, /*MergeInsnID's*/0,
        GIR_ConstrainSelectedInstOperands, /*InsnID*/0,
        GIR_EraseFromParent, /*InsnID*/0,
        // GIR_Coverage, 5743,
        GIR_Done,
      // Label 7404: @541632
      GIM_Try, /*On fail goto*//*Label 7405*/ GIMT_Encode4(541720), // Rule ID 5747 //
        GIM_CheckConstantInt8, /*MI*/0, /*Op*/2, 0,
        // MIs[0] offset
        GIM_CheckIsImm, /*MI*/0, /*Op*/5,
        // MIs[0] format
        GIM_CheckIsImm, /*MI*/0, /*Op*/6,
        // MIs[0] auxiliary
        GIM_CheckIsImm, /*MI*/0, /*Op*/7,
        // MIs[0] Operand 8
        GIM_CheckLiteralInt, /*MI*/0, /*Op*/8, GIMT_Encode8(0),
        GIM_CheckComplexPattern, /*MI*/0, /*Op*/4, /*Renderer*/GIMT_Encode2(0), GIMT_Encode2(GICP_gi_buf_soffset),
        // (SItbuffer_store v3f32:{ *:[v3f32] }:$vdata, v4i32:{ *:[v4i32] }:$rsrc, 0:{ *:[i32] }, i32:{ *:[i32] }:$voffset, (BUFSOffset:{ *:[i32] } i32:{ *:[i32] }:$soffset), (timm:{ *:[i32] }):$offset, (timm:{ *:[i32] }):$format, (timm:{ *:[i32] }):$auxiliary, 0:{ *:[i1] })  =>  (TBUFFER_STORE_FORMAT_XYZ_VBUFFER_OFFEN_exact anonymous_15035:{ *:[v3f32] }:$vdata, VGPR_32:{ *:[i32] }:$voffset, SReg_128:{ *:[v4i32] }:$rsrc, SCSrc_b32:{ *:[i32] }:$soffset, (timm:{ *:[i32] }):$offset, (as_i8timm:{ *:[i8] } ?:{ *:[i32] }:$format), (extract_cpol:{ *:[i32] } ?:{ *:[i32] }:$auxiliary), (extract_swz:{ *:[i1] } ?:{ *:[i32] }:$auxiliary))
        GIR_BuildMI, /*InsnID*/0, /*Opcode*/GIMT_Encode2(AMDGPU::TBUFFER_STORE_FORMAT_XYZ_VBUFFER_OFFEN_exact),
        GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/0, // vdata
        GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/3, // voffset
        GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/1, // rsrc
        GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/0, // soffset
        GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/5, // offset
        GIR_CustomOperandRenderer, /*InsnID*/0, /*OldInsnID*/0, /*OpIdx*/6, /*OperandRenderer*/GIMT_Encode2(GICR_renderTruncTImm), // format
        GIR_CustomOperandRenderer, /*InsnID*/0, /*OldInsnID*/0, /*OpIdx*/7, /*OperandRenderer*/GIMT_Encode2(GICR_renderExtractCPol), // auxiliary
        GIR_CustomOperandRenderer, /*InsnID*/0, /*OldInsnID*/0, /*OpIdx*/7, /*OperandRenderer*/GIMT_Encode2(GICR_renderExtractSWZ), // auxiliary
        GIR_MergeMemOperands, /*InsnID*/0, /*NumInsns*/1, /*MergeInsnID's*/0,
        GIR_ConstrainSelectedInstOperands, /*InsnID*/0,
        GIR_EraseFromParent, /*InsnID*/0,
        // GIR_Coverage, 5747,
        GIR_Done,
      // Label 7405: @541720
      GIM_Try, /*On fail goto*//*Label 7406*/ GIMT_Encode4(541803), // Rule ID 5710 //
        GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasUnrestrictedSOffset),
        GIM_CheckConstantInt8, /*MI*/0, /*Op*/3, 0,
        // MIs[0] offset
        GIM_CheckIsImm, /*MI*/0, /*Op*/5,
        // MIs[0] format
        GIM_CheckIsImm, /*MI*/0, /*Op*/6,
        // MIs[0] auxiliary
        GIM_CheckIsImm, /*MI*/0, /*Op*/7,
        // MIs[0] Operand 8
        GIM_CheckIsImm, /*MI*/0, /*Op*/8,
        GIM_CheckComplexPattern, /*MI*/0, /*Op*/4, /*Renderer*/GIMT_Encode2(0), GIMT_Encode2(GICP_gi_buf_soffset),
        // (SItbuffer_store v3i32:{ *:[v3i32] }:$vdata, v4i32:{ *:[v4i32] }:$rsrc, i32:{ *:[i32] }:$vindex, 0:{ *:[i32] }, (BUFSOffset:{ *:[i32] } i32:{ *:[i32] }:$soffset), (timm:{ *:[i32] }):$offset, (timm:{ *:[i32] }):$format, (timm:{ *:[i32] }):$auxiliary, (timm:{ *:[i1] }))  =>  (TBUFFER_STORE_FORMAT_XYZ_IDXEN_exact anonymous_15035:{ *:[v3i32] }:$vdata, VGPR_32:{ *:[i32] }:$vindex, SReg_128:{ *:[v4i32] }:$rsrc, SCSrc_b32:{ *:[i32] }:$soffset, (timm:{ *:[i32] }):$offset, (as_i8timm:{ *:[i8] } ?:{ *:[i32] }:$format), (extract_cpol:{ *:[i32] } ?:{ *:[i32] }:$auxiliary), (extract_swz:{ *:[i1] } ?:{ *:[i32] }:$auxiliary))
        GIR_BuildMI, /*InsnID*/0, /*Opcode*/GIMT_Encode2(AMDGPU::TBUFFER_STORE_FORMAT_XYZ_IDXEN_exact),
        GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/0, // vdata
        GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/2, // vindex
        GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/1, // rsrc
        GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/0, // soffset
        GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/5, // offset
        GIR_CustomOperandRenderer, /*InsnID*/0, /*OldInsnID*/0, /*OpIdx*/6, /*OperandRenderer*/GIMT_Encode2(GICR_renderTruncTImm), // format
        GIR_CustomOperandRenderer, /*InsnID*/0, /*OldInsnID*/0, /*OpIdx*/7, /*OperandRenderer*/GIMT_Encode2(GICR_renderExtractCPol), // auxiliary
        GIR_CustomOperandRenderer, /*InsnID*/0, /*OldInsnID*/0, /*OpIdx*/7, /*OperandRenderer*/GIMT_Encode2(GICR_renderExtractSWZ), // auxiliary
        GIR_MergeMemOperands, /*InsnID*/0, /*NumInsns*/1, /*MergeInsnID's*/0,
        GIR_ConstrainSelectedInstOperands, /*InsnID*/0,
        GIR_EraseFromParent, /*InsnID*/0,
        // GIR_Coverage, 5710,
        GIR_Done,
      // Label 7406: @541803
      GIM_Try, /*On fail goto*//*Label 7407*/ GIMT_Encode4(541883), // Rule ID 5714 //
        GIM_CheckConstantInt8, /*MI*/0, /*Op*/3, 0,
        // MIs[0] offset
        GIM_CheckIsImm, /*MI*/0, /*Op*/5,
        // MIs[0] format
        GIM_CheckIsImm, /*MI*/0, /*Op*/6,
        // MIs[0] auxiliary
        GIM_CheckIsImm, /*MI*/0, /*Op*/7,
        // MIs[0] Operand 8
        GIM_CheckIsImm, /*MI*/0, /*Op*/8,
        GIM_CheckComplexPattern, /*MI*/0, /*Op*/4, /*Renderer*/GIMT_Encode2(0), GIMT_Encode2(GICP_gi_buf_soffset),
        // (SItbuffer_store v3i32:{ *:[v3i32] }:$vdata, v4i32:{ *:[v4i32] }:$rsrc, i32:{ *:[i32] }:$vindex, 0:{ *:[i32] }, (BUFSOffset:{ *:[i32] } i32:{ *:[i32] }:$soffset), (timm:{ *:[i32] }):$offset, (timm:{ *:[i32] }):$format, (timm:{ *:[i32] }):$auxiliary, (timm:{ *:[i1] }))  =>  (TBUFFER_STORE_FORMAT_XYZ_VBUFFER_IDXEN_exact anonymous_15035:{ *:[v3i32] }:$vdata, VGPR_32:{ *:[i32] }:$vindex, SReg_128:{ *:[v4i32] }:$rsrc, SCSrc_b32:{ *:[i32] }:$soffset, (timm:{ *:[i32] }):$offset, (as_i8timm:{ *:[i8] } ?:{ *:[i32] }:$format), (extract_cpol:{ *:[i32] } ?:{ *:[i32] }:$auxiliary), (extract_swz:{ *:[i1] } ?:{ *:[i32] }:$auxiliary))
        GIR_BuildMI, /*InsnID*/0, /*Opcode*/GIMT_Encode2(AMDGPU::TBUFFER_STORE_FORMAT_XYZ_VBUFFER_IDXEN_exact),
        GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/0, // vdata
        GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/2, // vindex
        GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/1, // rsrc
        GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/0, // soffset
        GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/5, // offset
        GIR_CustomOperandRenderer, /*InsnID*/0, /*OldInsnID*/0, /*OpIdx*/6, /*OperandRenderer*/GIMT_Encode2(GICR_renderTruncTImm), // format
        GIR_CustomOperandRenderer, /*InsnID*/0, /*OldInsnID*/0, /*OpIdx*/7, /*OperandRenderer*/GIMT_Encode2(GICR_renderExtractCPol), // auxiliary
        GIR_CustomOperandRenderer, /*InsnID*/0, /*OldInsnID*/0, /*OpIdx*/7, /*OperandRenderer*/GIMT_Encode2(GICR_renderExtractSWZ), // auxiliary
        GIR_MergeMemOperands, /*InsnID*/0, /*NumInsns*/1, /*MergeInsnID's*/0,
        GIR_ConstrainSelectedInstOperands, /*InsnID*/0,
        GIR_EraseFromParent, /*InsnID*/0,
        // GIR_Coverage, 5714,
        GIR_Done,
      // Label 7407: @541883
      GIM_Try, /*On fail goto*//*Label 7408*/ GIMT_Encode4(541966), // Rule ID 5742 //
        GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasUnrestrictedSOffset),
        GIM_CheckConstantInt8, /*MI*/0, /*Op*/3, 0,
        // MIs[0] offset
        GIM_CheckIsImm, /*MI*/0, /*Op*/5,
        // MIs[0] format
        GIM_CheckIsImm, /*MI*/0, /*Op*/6,
        // MIs[0] auxiliary
        GIM_CheckIsImm, /*MI*/0, /*Op*/7,
        // MIs[0] Operand 8
        GIM_CheckIsImm, /*MI*/0, /*Op*/8,
        GIM_CheckComplexPattern, /*MI*/0, /*Op*/4, /*Renderer*/GIMT_Encode2(0), GIMT_Encode2(GICP_gi_buf_soffset),
        // (SItbuffer_store v3f32:{ *:[v3f32] }:$vdata, v4i32:{ *:[v4i32] }:$rsrc, i32:{ *:[i32] }:$vindex, 0:{ *:[i32] }, (BUFSOffset:{ *:[i32] } i32:{ *:[i32] }:$soffset), (timm:{ *:[i32] }):$offset, (timm:{ *:[i32] }):$format, (timm:{ *:[i32] }):$auxiliary, (timm:{ *:[i1] }))  =>  (TBUFFER_STORE_FORMAT_XYZ_IDXEN_exact anonymous_15035:{ *:[v3f32] }:$vdata, VGPR_32:{ *:[i32] }:$vindex, SReg_128:{ *:[v4i32] }:$rsrc, SCSrc_b32:{ *:[i32] }:$soffset, (timm:{ *:[i32] }):$offset, (as_i8timm:{ *:[i8] } ?:{ *:[i32] }:$format), (extract_cpol:{ *:[i32] } ?:{ *:[i32] }:$auxiliary), (extract_swz:{ *:[i1] } ?:{ *:[i32] }:$auxiliary))
        GIR_BuildMI, /*InsnID*/0, /*Opcode*/GIMT_Encode2(AMDGPU::TBUFFER_STORE_FORMAT_XYZ_IDXEN_exact),
        GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/0, // vdata
        GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/2, // vindex
        GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/1, // rsrc
        GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/0, // soffset
        GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/5, // offset
        GIR_CustomOperandRenderer, /*InsnID*/0, /*OldInsnID*/0, /*OpIdx*/6, /*OperandRenderer*/GIMT_Encode2(GICR_renderTruncTImm), // format
        GIR_CustomOperandRenderer, /*InsnID*/0, /*OldInsnID*/0, /*OpIdx*/7, /*OperandRenderer*/GIMT_Encode2(GICR_renderExtractCPol), // auxiliary
        GIR_CustomOperandRenderer, /*InsnID*/0, /*OldInsnID*/0, /*OpIdx*/7, /*OperandRenderer*/GIMT_Encode2(GICR_renderExtractSWZ), // auxiliary
        GIR_MergeMemOperands, /*InsnID*/0, /*NumInsns*/1, /*MergeInsnID's*/0,
        GIR_ConstrainSelectedInstOperands, /*InsnID*/0,
        GIR_EraseFromParent, /*InsnID*/0,
        // GIR_Coverage, 5742,
        GIR_Done,
      // Label 7408: @541966
      GIM_Try, /*On fail goto*//*Label 7409*/ GIMT_Encode4(542046), // Rule ID 5746 //
        GIM_CheckConstantInt8, /*MI*/0, /*Op*/3, 0,
        // MIs[0] offset
        GIM_CheckIsImm, /*MI*/0, /*Op*/5,
        // MIs[0] format
        GIM_CheckIsImm, /*MI*/0, /*Op*/6,
        // MIs[0] auxiliary
        GIM_CheckIsImm, /*MI*/0, /*Op*/7,
        // MIs[0] Operand 8
        GIM_CheckIsImm, /*MI*/0, /*Op*/8,
        GIM_CheckComplexPattern, /*MI*/0, /*Op*/4, /*Renderer*/GIMT_Encode2(0), GIMT_Encode2(GICP_gi_buf_soffset),
        // (SItbuffer_store v3f32:{ *:[v3f32] }:$vdata, v4i32:{ *:[v4i32] }:$rsrc, i32:{ *:[i32] }:$vindex, 0:{ *:[i32] }, (BUFSOffset:{ *:[i32] } i32:{ *:[i32] }:$soffset), (timm:{ *:[i32] }):$offset, (timm:{ *:[i32] }):$format, (timm:{ *:[i32] }):$auxiliary, (timm:{ *:[i1] }))  =>  (TBUFFER_STORE_FORMAT_XYZ_VBUFFER_IDXEN_exact anonymous_15035:{ *:[v3f32] }:$vdata, VGPR_32:{ *:[i32] }:$vindex, SReg_128:{ *:[v4i32] }:$rsrc, SCSrc_b32:{ *:[i32] }:$soffset, (timm:{ *:[i32] }):$offset, (as_i8timm:{ *:[i8] } ?:{ *:[i32] }:$format), (extract_cpol:{ *:[i32] } ?:{ *:[i32] }:$auxiliary), (extract_swz:{ *:[i1] } ?:{ *:[i32] }:$auxiliary))
        GIR_BuildMI, /*InsnID*/0, /*Opcode*/GIMT_Encode2(AMDGPU::TBUFFER_STORE_FORMAT_XYZ_VBUFFER_IDXEN_exact),
        GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/0, // vdata
        GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/2, // vindex
        GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/1, // rsrc
        GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/0, // soffset
        GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/5, // offset
        GIR_CustomOperandRenderer, /*InsnID*/0, /*OldInsnID*/0, /*OpIdx*/6, /*OperandRenderer*/GIMT_Encode2(GICR_renderTruncTImm), // format
        GIR_CustomOperandRenderer, /*InsnID*/0, /*OldInsnID*/0, /*OpIdx*/7, /*OperandRenderer*/GIMT_Encode2(GICR_renderExtractCPol), // auxiliary
        GIR_CustomOperandRenderer, /*InsnID*/0, /*OldInsnID*/0, /*OpIdx*/7, /*OperandRenderer*/GIMT_Encode2(GICR_renderExtractSWZ), // auxiliary
        GIR_MergeMemOperands, /*InsnID*/0, /*NumInsns*/1, /*MergeInsnID's*/0,
        GIR_ConstrainSelectedInstOperands, /*InsnID*/0,
        GIR_EraseFromParent, /*InsnID*/0,
        // GIR_Coverage, 5746,
        GIR_Done,
      // Label 7409: @542046
      GIM_Try, /*On fail goto*//*Label 7410*/ GIMT_Encode4(542165), // Rule ID 5712 //
        GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasUnrestrictedSOffset),
        // MIs[0] offset
        GIM_CheckIsImm, /*MI*/0, /*Op*/5,
        // MIs[0] format
        GIM_CheckIsImm, /*MI*/0, /*Op*/6,
        // MIs[0] auxiliary
        GIM_CheckIsImm, /*MI*/0, /*Op*/7,
        // MIs[0] Operand 8
        GIM_CheckIsImm, /*MI*/0, /*Op*/8,
        GIM_CheckComplexPattern, /*MI*/0, /*Op*/4, /*Renderer*/GIMT_Encode2(0), GIMT_Encode2(GICP_gi_buf_soffset),
        // (SItbuffer_store v3i32:{ *:[v3i32] }:$vdata, v4i32:{ *:[v4i32] }:$rsrc, i32:{ *:[i32] }:$vindex, i32:{ *:[i32] }:$voffset, (BUFSOffset:{ *:[i32] } i32:{ *:[i32] }:$soffset), (timm:{ *:[i32] }):$offset, (timm:{ *:[i32] }):$format, (timm:{ *:[i32] }):$auxiliary, (timm:{ *:[i1] }))  =>  (TBUFFER_STORE_FORMAT_XYZ_BOTHEN_exact anonymous_15035:{ *:[v3i32] }:$vdata, (REG_SEQUENCE:{ *:[i64] } VReg_64:{ *:[i32] }, VGPR_32:{ *:[i32] }:$vindex, sub0:{ *:[i32] }, VGPR_32:{ *:[i32] }:$voffset, sub1:{ *:[i32] }), SReg_128:{ *:[v4i32] }:$rsrc, SCSrc_b32:{ *:[i32] }:$soffset, (timm:{ *:[i32] }):$offset, (as_i8timm:{ *:[i8] } ?:{ *:[i32] }:$format), (extract_cpol:{ *:[i32] } ?:{ *:[i32] }:$auxiliary), (extract_swz:{ *:[i1] } ?:{ *:[i32] }:$auxiliary))
        GIR_MakeTempReg, /*TempRegID*/0, /*TypeID*/GILLT_s64,
        GIR_BuildMI, /*InsnID*/1, /*Opcode*/GIMT_Encode2(TargetOpcode::REG_SEQUENCE),
        GIR_AddTempRegister, /*InsnID*/1, /*TempRegID*/0, /*TempRegFlags*/GIMT_Encode2(RegState::Define),
        GIR_Copy, /*NewInsnID*/1, /*OldInsnID*/0, /*OpIdx*/2, // vindex
        GIR_AddImm8, /*InsnID*/1, /*SubRegIndex*/3,
        GIR_Copy, /*NewInsnID*/1, /*OldInsnID*/0, /*OpIdx*/3, // voffset
        GIR_AddImm8, /*InsnID*/1, /*SubRegIndex*/11,
        GIR_ConstrainOperandRC, /*InsnID*/1, /*Op*/0, GIMT_Encode2(AMDGPU::VReg_64RegClassID),
        GIR_ConstrainOperandRC, /*InsnID*/1, /*Op*/1, GIMT_Encode2(AMDGPU::VGPR_32RegClassID),
        GIR_ConstrainOperandRC, /*InsnID*/1, /*Op*/3, GIMT_Encode2(AMDGPU::VGPR_32RegClassID),
        GIR_BuildMI, /*InsnID*/0, /*Opcode*/GIMT_Encode2(AMDGPU::TBUFFER_STORE_FORMAT_XYZ_BOTHEN_exact),
        GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/0, // vdata
        GIR_AddSimpleTempRegister, /*InsnID*/0, /*TempRegID*/0,
        GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/1, // rsrc
        GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/0, // soffset
        GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/5, // offset
        GIR_CustomOperandRenderer, /*InsnID*/0, /*OldInsnID*/0, /*OpIdx*/6, /*OperandRenderer*/GIMT_Encode2(GICR_renderTruncTImm), // format
        GIR_CustomOperandRenderer, /*InsnID*/0, /*OldInsnID*/0, /*OpIdx*/7, /*OperandRenderer*/GIMT_Encode2(GICR_renderExtractCPol), // auxiliary
        GIR_CustomOperandRenderer, /*InsnID*/0, /*OldInsnID*/0, /*OpIdx*/7, /*OperandRenderer*/GIMT_Encode2(GICR_renderExtractSWZ), // auxiliary
        GIR_MergeMemOperands, /*InsnID*/0, /*NumInsns*/1, /*MergeInsnID's*/0,
        GIR_ConstrainSelectedInstOperands, /*InsnID*/0,
        GIR_EraseFromParent, /*InsnID*/0,
        // GIR_Coverage, 5712,
        GIR_Done,
      // Label 7410: @542165
      GIM_Try, /*On fail goto*//*Label 7411*/ GIMT_Encode4(542281), // Rule ID 5716 //
        // MIs[0] offset
        GIM_CheckIsImm, /*MI*/0, /*Op*/5,
        // MIs[0] format
        GIM_CheckIsImm, /*MI*/0, /*Op*/6,
        // MIs[0] auxiliary
        GIM_CheckIsImm, /*MI*/0, /*Op*/7,
        // MIs[0] Operand 8
        GIM_CheckIsImm, /*MI*/0, /*Op*/8,
        GIM_CheckComplexPattern, /*MI*/0, /*Op*/4, /*Renderer*/GIMT_Encode2(0), GIMT_Encode2(GICP_gi_buf_soffset),
        // (SItbuffer_store v3i32:{ *:[v3i32] }:$vdata, v4i32:{ *:[v4i32] }:$rsrc, i32:{ *:[i32] }:$vindex, i32:{ *:[i32] }:$voffset, (BUFSOffset:{ *:[i32] } i32:{ *:[i32] }:$soffset), (timm:{ *:[i32] }):$offset, (timm:{ *:[i32] }):$format, (timm:{ *:[i32] }):$auxiliary, (timm:{ *:[i1] }))  =>  (TBUFFER_STORE_FORMAT_XYZ_VBUFFER_BOTHEN_exact anonymous_15035:{ *:[v3i32] }:$vdata, (REG_SEQUENCE:{ *:[i64] } VReg_64:{ *:[i32] }, VGPR_32:{ *:[i32] }:$vindex, sub0:{ *:[i32] }, VGPR_32:{ *:[i32] }:$voffset, sub1:{ *:[i32] }), SReg_128:{ *:[v4i32] }:$rsrc, SCSrc_b32:{ *:[i32] }:$soffset, (timm:{ *:[i32] }):$offset, (as_i8timm:{ *:[i8] } ?:{ *:[i32] }:$format), (extract_cpol:{ *:[i32] } ?:{ *:[i32] }:$auxiliary), (extract_swz:{ *:[i1] } ?:{ *:[i32] }:$auxiliary))
        GIR_MakeTempReg, /*TempRegID*/0, /*TypeID*/GILLT_s64,
        GIR_BuildMI, /*InsnID*/1, /*Opcode*/GIMT_Encode2(TargetOpcode::REG_SEQUENCE),
        GIR_AddTempRegister, /*InsnID*/1, /*TempRegID*/0, /*TempRegFlags*/GIMT_Encode2(RegState::Define),
        GIR_Copy, /*NewInsnID*/1, /*OldInsnID*/0, /*OpIdx*/2, // vindex
        GIR_AddImm8, /*InsnID*/1, /*SubRegIndex*/3,
        GIR_Copy, /*NewInsnID*/1, /*OldInsnID*/0, /*OpIdx*/3, // voffset
        GIR_AddImm8, /*InsnID*/1, /*SubRegIndex*/11,
        GIR_ConstrainOperandRC, /*InsnID*/1, /*Op*/0, GIMT_Encode2(AMDGPU::VReg_64RegClassID),
        GIR_ConstrainOperandRC, /*InsnID*/1, /*Op*/1, GIMT_Encode2(AMDGPU::VGPR_32RegClassID),
        GIR_ConstrainOperandRC, /*InsnID*/1, /*Op*/3, GIMT_Encode2(AMDGPU::VGPR_32RegClassID),
        GIR_BuildMI, /*InsnID*/0, /*Opcode*/GIMT_Encode2(AMDGPU::TBUFFER_STORE_FORMAT_XYZ_VBUFFER_BOTHEN_exact),
        GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/0, // vdata
        GIR_AddSimpleTempRegister, /*InsnID*/0, /*TempRegID*/0,
        GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/1, // rsrc
        GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/0, // soffset
        GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/5, // offset
        GIR_CustomOperandRenderer, /*InsnID*/0, /*OldInsnID*/0, /*OpIdx*/6, /*OperandRenderer*/GIMT_Encode2(GICR_renderTruncTImm), // format
        GIR_CustomOperandRenderer, /*InsnID*/0, /*OldInsnID*/0, /*OpIdx*/7, /*OperandRenderer*/GIMT_Encode2(GICR_renderExtractCPol), // auxiliary
        GIR_CustomOperandRenderer, /*InsnID*/0, /*OldInsnID*/0, /*OpIdx*/7, /*OperandRenderer*/GIMT_Encode2(GICR_renderExtractSWZ), // auxiliary
        GIR_MergeMemOperands, /*InsnID*/0, /*NumInsns*/1, /*MergeInsnID's*/0,
        GIR_ConstrainSelectedInstOperands, /*InsnID*/0,
        GIR_EraseFromParent, /*InsnID*/0,
        // GIR_Coverage, 5716,
        GIR_Done,
      // Label 7411: @542281
      GIM_Try, /*On fail goto*//*Label 7412*/ GIMT_Encode4(542400), // Rule ID 5744 //
        GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasUnrestrictedSOffset),
        // MIs[0] offset
        GIM_CheckIsImm, /*MI*/0, /*Op*/5,
        // MIs[0] format
        GIM_CheckIsImm, /*MI*/0, /*Op*/6,
        // MIs[0] auxiliary
        GIM_CheckIsImm, /*MI*/0, /*Op*/7,
        // MIs[0] Operand 8
        GIM_CheckIsImm, /*MI*/0, /*Op*/8,
        GIM_CheckComplexPattern, /*MI*/0, /*Op*/4, /*Renderer*/GIMT_Encode2(0), GIMT_Encode2(GICP_gi_buf_soffset),
        // (SItbuffer_store v3f32:{ *:[v3f32] }:$vdata, v4i32:{ *:[v4i32] }:$rsrc, i32:{ *:[i32] }:$vindex, i32:{ *:[i32] }:$voffset, (BUFSOffset:{ *:[i32] } i32:{ *:[i32] }:$soffset), (timm:{ *:[i32] }):$offset, (timm:{ *:[i32] }):$format, (timm:{ *:[i32] }):$auxiliary, (timm:{ *:[i1] }))  =>  (TBUFFER_STORE_FORMAT_XYZ_BOTHEN_exact anonymous_15035:{ *:[v3f32] }:$vdata, (REG_SEQUENCE:{ *:[i64] } VReg_64:{ *:[i32] }, VGPR_32:{ *:[i32] }:$vindex, sub0:{ *:[i32] }, VGPR_32:{ *:[i32] }:$voffset, sub1:{ *:[i32] }), SReg_128:{ *:[v4i32] }:$rsrc, SCSrc_b32:{ *:[i32] }:$soffset, (timm:{ *:[i32] }):$offset, (as_i8timm:{ *:[i8] } ?:{ *:[i32] }:$format), (extract_cpol:{ *:[i32] } ?:{ *:[i32] }:$auxiliary), (extract_swz:{ *:[i1] } ?:{ *:[i32] }:$auxiliary))
        GIR_MakeTempReg, /*TempRegID*/0, /*TypeID*/GILLT_s64,
        GIR_BuildMI, /*InsnID*/1, /*Opcode*/GIMT_Encode2(TargetOpcode::REG_SEQUENCE),
        GIR_AddTempRegister, /*InsnID*/1, /*TempRegID*/0, /*TempRegFlags*/GIMT_Encode2(RegState::Define),
        GIR_Copy, /*NewInsnID*/1, /*OldInsnID*/0, /*OpIdx*/2, // vindex
        GIR_AddImm8, /*InsnID*/1, /*SubRegIndex*/3,
        GIR_Copy, /*NewInsnID*/1, /*OldInsnID*/0, /*OpIdx*/3, // voffset
        GIR_AddImm8, /*InsnID*/1, /*SubRegIndex*/11,
        GIR_ConstrainOperandRC, /*InsnID*/1, /*Op*/0, GIMT_Encode2(AMDGPU::VReg_64RegClassID),
        GIR_ConstrainOperandRC, /*InsnID*/1, /*Op*/1, GIMT_Encode2(AMDGPU::VGPR_32RegClassID),
        GIR_ConstrainOperandRC, /*InsnID*/1, /*Op*/3, GIMT_Encode2(AMDGPU::VGPR_32RegClassID),
        GIR_BuildMI, /*InsnID*/0, /*Opcode*/GIMT_Encode2(AMDGPU::TBUFFER_STORE_FORMAT_XYZ_BOTHEN_exact),
        GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/0, // vdata
        GIR_AddSimpleTempRegister, /*InsnID*/0, /*TempRegID*/0,
        GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/1, // rsrc
        GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/0, // soffset
        GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/5, // offset
        GIR_CustomOperandRenderer, /*InsnID*/0, /*OldInsnID*/0, /*OpIdx*/6, /*OperandRenderer*/GIMT_Encode2(GICR_renderTruncTImm), // format
        GIR_CustomOperandRenderer, /*InsnID*/0, /*OldInsnID*/0, /*OpIdx*/7, /*OperandRenderer*/GIMT_Encode2(GICR_renderExtractCPol), // auxiliary
        GIR_CustomOperandRenderer, /*InsnID*/0, /*OldInsnID*/0, /*OpIdx*/7, /*OperandRenderer*/GIMT_Encode2(GICR_renderExtractSWZ), // auxiliary
        GIR_MergeMemOperands, /*InsnID*/0, /*NumInsns*/1, /*MergeInsnID's*/0,
        GIR_ConstrainSelectedInstOperands, /*InsnID*/0,
        GIR_EraseFromParent, /*InsnID*/0,
        // GIR_Coverage, 5744,
        GIR_Done,
      // Label 7412: @542400
      GIM_Try, /*On fail goto*//*Label 7413*/ GIMT_Encode4(542516), // Rule ID 5748 //
        // MIs[0] offset
        GIM_CheckIsImm, /*MI*/0, /*Op*/5,
        // MIs[0] format
        GIM_CheckIsImm, /*MI*/0, /*Op*/6,
        // MIs[0] auxiliary
        GIM_CheckIsImm, /*MI*/0, /*Op*/7,
        // MIs[0] Operand 8
        GIM_CheckIsImm, /*MI*/0, /*Op*/8,
        GIM_CheckComplexPattern, /*MI*/0, /*Op*/4, /*Renderer*/GIMT_Encode2(0), GIMT_Encode2(GICP_gi_buf_soffset),
        // (SItbuffer_store v3f32:{ *:[v3f32] }:$vdata, v4i32:{ *:[v4i32] }:$rsrc, i32:{ *:[i32] }:$vindex, i32:{ *:[i32] }:$voffset, (BUFSOffset:{ *:[i32] } i32:{ *:[i32] }:$soffset), (timm:{ *:[i32] }):$offset, (timm:{ *:[i32] }):$format, (timm:{ *:[i32] }):$auxiliary, (timm:{ *:[i1] }))  =>  (TBUFFER_STORE_FORMAT_XYZ_VBUFFER_BOTHEN_exact anonymous_15035:{ *:[v3f32] }:$vdata, (REG_SEQUENCE:{ *:[i64] } VReg_64:{ *:[i32] }, VGPR_32:{ *:[i32] }:$vindex, sub0:{ *:[i32] }, VGPR_32:{ *:[i32] }:$voffset, sub1:{ *:[i32] }), SReg_128:{ *:[v4i32] }:$rsrc, SCSrc_b32:{ *:[i32] }:$soffset, (timm:{ *:[i32] }):$offset, (as_i8timm:{ *:[i8] } ?:{ *:[i32] }:$format), (extract_cpol:{ *:[i32] } ?:{ *:[i32] }:$auxiliary), (extract_swz:{ *:[i1] } ?:{ *:[i32] }:$auxiliary))
        GIR_MakeTempReg, /*TempRegID*/0, /*TypeID*/GILLT_s64,
        GIR_BuildMI, /*InsnID*/1, /*Opcode*/GIMT_Encode2(TargetOpcode::REG_SEQUENCE),
        GIR_AddTempRegister, /*InsnID*/1, /*TempRegID*/0, /*TempRegFlags*/GIMT_Encode2(RegState::Define),
        GIR_Copy, /*NewInsnID*/1, /*OldInsnID*/0, /*OpIdx*/2, // vindex
        GIR_AddImm8, /*InsnID*/1, /*SubRegIndex*/3,
        GIR_Copy, /*NewInsnID*/1, /*OldInsnID*/0, /*OpIdx*/3, // voffset
        GIR_AddImm8, /*InsnID*/1, /*SubRegIndex*/11,
        GIR_ConstrainOperandRC, /*InsnID*/1, /*Op*/0, GIMT_Encode2(AMDGPU::VReg_64RegClassID),
        GIR_ConstrainOperandRC, /*InsnID*/1, /*Op*/1, GIMT_Encode2(AMDGPU::VGPR_32RegClassID),
        GIR_ConstrainOperandRC, /*InsnID*/1, /*Op*/3, GIMT_Encode2(AMDGPU::VGPR_32RegClassID),
        GIR_BuildMI, /*InsnID*/0, /*Opcode*/GIMT_Encode2(AMDGPU::TBUFFER_STORE_FORMAT_XYZ_VBUFFER_BOTHEN_exact),
        GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/0, // vdata
        GIR_AddSimpleTempRegister, /*InsnID*/0, /*TempRegID*/0,
        GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/1, // rsrc
        GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/0, // soffset
        GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/5, // offset
        GIR_CustomOperandRenderer, /*InsnID*/0, /*OldInsnID*/0, /*OpIdx*/6, /*OperandRenderer*/GIMT_Encode2(GICR_renderTruncTImm), // format
        GIR_CustomOperandRenderer, /*InsnID*/0, /*OldInsnID*/0, /*OpIdx*/7, /*OperandRenderer*/GIMT_Encode2(GICR_renderExtractCPol), // auxiliary
        GIR_CustomOperandRenderer, /*InsnID*/0, /*OldInsnID*/0, /*OpIdx*/7, /*OperandRenderer*/GIMT_Encode2(GICR_renderExtractSWZ), // auxiliary
        GIR_MergeMemOperands, /*InsnID*/0, /*NumInsns*/1, /*MergeInsnID's*/0,
        GIR_ConstrainSelectedInstOperands, /*InsnID*/0,
        GIR_EraseFromParent, /*InsnID*/0,
        // GIR_Coverage, 5748,
        GIR_Done,
      // Label 7413: @542516
      GIM_Reject,
    // Label 7397: @542517
    GIM_Reject,
    // Label 7361: @542518
    GIM_Try, /*On fail goto*//*Label 7414*/ GIMT_Encode4(544052),
      GIM_CheckType, /*MI*/0, /*Op*/1, /*Type*/GILLT_v4s32,
      GIM_CheckType, /*MI*/0, /*Op*/2, /*Type*/GILLT_s32,
      GIM_CheckType, /*MI*/0, /*Op*/3, /*Type*/GILLT_s32,
      GIM_CheckType, /*MI*/0, /*Op*/4, /*Type*/GILLT_s32,
      GIM_Try, /*On fail goto*//*Label 7415*/ GIMT_Encode4(542630), // Rule ID 5717 //
        GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasUnrestrictedSOffset),
        GIM_CheckConstantInt8, /*MI*/0, /*Op*/2, 0,
        GIM_CheckConstantInt8, /*MI*/0, /*Op*/3, 0,
        // MIs[0] offset
        GIM_CheckIsImm, /*MI*/0, /*Op*/5,
        // MIs[0] format
        GIM_CheckIsImm, /*MI*/0, /*Op*/6,
        // MIs[0] auxiliary
        GIM_CheckIsImm, /*MI*/0, /*Op*/7,
        // MIs[0] Operand 8
        GIM_CheckLiteralInt, /*MI*/0, /*Op*/8, GIMT_Encode8(0),
        GIM_CheckComplexPattern, /*MI*/0, /*Op*/4, /*Renderer*/GIMT_Encode2(0), GIMT_Encode2(GICP_gi_buf_soffset),
        // (SItbuffer_store v4i32:{ *:[v4i32] }:$vdata, v4i32:{ *:[v4i32] }:$rsrc, 0:{ *:[i32] }, 0:{ *:[i32] }, (BUFSOffset:{ *:[i32] } i32:{ *:[i32] }:$soffset), (timm:{ *:[i32] }):$offset, (timm:{ *:[i32] }):$format, (timm:{ *:[i32] }):$auxiliary, 0:{ *:[i1] })  =>  (TBUFFER_STORE_FORMAT_XYZW_OFFSET_exact anonymous_15034:{ *:[v4i32] }:$vdata, SReg_128:{ *:[v4i32] }:$rsrc, SCSrc_b32:{ *:[i32] }:$soffset, (timm:{ *:[i32] }):$offset, (as_i8timm:{ *:[i8] } ?:{ *:[i32] }:$format), (extract_cpol:{ *:[i32] } ?:{ *:[i32] }:$auxiliary), (extract_swz:{ *:[i1] } ?:{ *:[i32] }:$auxiliary))
        GIR_BuildMI, /*InsnID*/0, /*Opcode*/GIMT_Encode2(AMDGPU::TBUFFER_STORE_FORMAT_XYZW_OFFSET_exact),
        GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/0, // vdata
        GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/1, // rsrc
        GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/0, // soffset
        GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/5, // offset
        GIR_CustomOperandRenderer, /*InsnID*/0, /*OldInsnID*/0, /*OpIdx*/6, /*OperandRenderer*/GIMT_Encode2(GICR_renderTruncTImm), // format
        GIR_CustomOperandRenderer, /*InsnID*/0, /*OldInsnID*/0, /*OpIdx*/7, /*OperandRenderer*/GIMT_Encode2(GICR_renderExtractCPol), // auxiliary
        GIR_CustomOperandRenderer, /*InsnID*/0, /*OldInsnID*/0, /*OpIdx*/7, /*OperandRenderer*/GIMT_Encode2(GICR_renderExtractSWZ), // auxiliary
        GIR_MergeMemOperands, /*InsnID*/0, /*NumInsns*/1, /*MergeInsnID's*/0,
        GIR_ConstrainSelectedInstOperands, /*InsnID*/0,
        GIR_EraseFromParent, /*InsnID*/0,
        // GIR_Coverage, 5717,
        GIR_Done,
      // Label 7415: @542630
      GIM_Try, /*On fail goto*//*Label 7416*/ GIMT_Encode4(542718), // Rule ID 5721 //
        GIM_CheckConstantInt8, /*MI*/0, /*Op*/2, 0,
        GIM_CheckConstantInt8, /*MI*/0, /*Op*/3, 0,
        // MIs[0] offset
        GIM_CheckIsImm, /*MI*/0, /*Op*/5,
        // MIs[0] format
        GIM_CheckIsImm, /*MI*/0, /*Op*/6,
        // MIs[0] auxiliary
        GIM_CheckIsImm, /*MI*/0, /*Op*/7,
        // MIs[0] Operand 8
        GIM_CheckLiteralInt, /*MI*/0, /*Op*/8, GIMT_Encode8(0),
        GIM_CheckComplexPattern, /*MI*/0, /*Op*/4, /*Renderer*/GIMT_Encode2(0), GIMT_Encode2(GICP_gi_buf_soffset),
        // (SItbuffer_store v4i32:{ *:[v4i32] }:$vdata, v4i32:{ *:[v4i32] }:$rsrc, 0:{ *:[i32] }, 0:{ *:[i32] }, (BUFSOffset:{ *:[i32] } i32:{ *:[i32] }:$soffset), (timm:{ *:[i32] }):$offset, (timm:{ *:[i32] }):$format, (timm:{ *:[i32] }):$auxiliary, 0:{ *:[i1] })  =>  (TBUFFER_STORE_FORMAT_XYZW_VBUFFER_OFFSET_exact anonymous_15034:{ *:[v4i32] }:$vdata, SReg_128:{ *:[v4i32] }:$rsrc, SCSrc_b32:{ *:[i32] }:$soffset, (timm:{ *:[i32] }):$offset, (as_i8timm:{ *:[i8] } ?:{ *:[i32] }:$format), (extract_cpol:{ *:[i32] } ?:{ *:[i32] }:$auxiliary), (extract_swz:{ *:[i1] } ?:{ *:[i32] }:$auxiliary))
        GIR_BuildMI, /*InsnID*/0, /*Opcode*/GIMT_Encode2(AMDGPU::TBUFFER_STORE_FORMAT_XYZW_VBUFFER_OFFSET_exact),
        GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/0, // vdata
        GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/1, // rsrc
        GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/0, // soffset
        GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/5, // offset
        GIR_CustomOperandRenderer, /*InsnID*/0, /*OldInsnID*/0, /*OpIdx*/6, /*OperandRenderer*/GIMT_Encode2(GICR_renderTruncTImm), // format
        GIR_CustomOperandRenderer, /*InsnID*/0, /*OldInsnID*/0, /*OpIdx*/7, /*OperandRenderer*/GIMT_Encode2(GICR_renderExtractCPol), // auxiliary
        GIR_CustomOperandRenderer, /*InsnID*/0, /*OldInsnID*/0, /*OpIdx*/7, /*OperandRenderer*/GIMT_Encode2(GICR_renderExtractSWZ), // auxiliary
        GIR_MergeMemOperands, /*InsnID*/0, /*NumInsns*/1, /*MergeInsnID's*/0,
        GIR_ConstrainSelectedInstOperands, /*InsnID*/0,
        GIR_EraseFromParent, /*InsnID*/0,
        // GIR_Coverage, 5721,
        GIR_Done,
      // Label 7416: @542718
      GIM_Try, /*On fail goto*//*Label 7417*/ GIMT_Encode4(542809), // Rule ID 5749 //
        GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasUnrestrictedSOffset),
        GIM_CheckConstantInt8, /*MI*/0, /*Op*/2, 0,
        GIM_CheckConstantInt8, /*MI*/0, /*Op*/3, 0,
        // MIs[0] offset
        GIM_CheckIsImm, /*MI*/0, /*Op*/5,
        // MIs[0] format
        GIM_CheckIsImm, /*MI*/0, /*Op*/6,
        // MIs[0] auxiliary
        GIM_CheckIsImm, /*MI*/0, /*Op*/7,
        // MIs[0] Operand 8
        GIM_CheckLiteralInt, /*MI*/0, /*Op*/8, GIMT_Encode8(0),
        GIM_CheckComplexPattern, /*MI*/0, /*Op*/4, /*Renderer*/GIMT_Encode2(0), GIMT_Encode2(GICP_gi_buf_soffset),
        // (SItbuffer_store v4f32:{ *:[v4f32] }:$vdata, v4i32:{ *:[v4i32] }:$rsrc, 0:{ *:[i32] }, 0:{ *:[i32] }, (BUFSOffset:{ *:[i32] } i32:{ *:[i32] }:$soffset), (timm:{ *:[i32] }):$offset, (timm:{ *:[i32] }):$format, (timm:{ *:[i32] }):$auxiliary, 0:{ *:[i1] })  =>  (TBUFFER_STORE_FORMAT_XYZW_OFFSET_exact anonymous_15034:{ *:[v4f32] }:$vdata, SReg_128:{ *:[v4i32] }:$rsrc, SCSrc_b32:{ *:[i32] }:$soffset, (timm:{ *:[i32] }):$offset, (as_i8timm:{ *:[i8] } ?:{ *:[i32] }:$format), (extract_cpol:{ *:[i32] } ?:{ *:[i32] }:$auxiliary), (extract_swz:{ *:[i1] } ?:{ *:[i32] }:$auxiliary))
        GIR_BuildMI, /*InsnID*/0, /*Opcode*/GIMT_Encode2(AMDGPU::TBUFFER_STORE_FORMAT_XYZW_OFFSET_exact),
        GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/0, // vdata
        GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/1, // rsrc
        GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/0, // soffset
        GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/5, // offset
        GIR_CustomOperandRenderer, /*InsnID*/0, /*OldInsnID*/0, /*OpIdx*/6, /*OperandRenderer*/GIMT_Encode2(GICR_renderTruncTImm), // format
        GIR_CustomOperandRenderer, /*InsnID*/0, /*OldInsnID*/0, /*OpIdx*/7, /*OperandRenderer*/GIMT_Encode2(GICR_renderExtractCPol), // auxiliary
        GIR_CustomOperandRenderer, /*InsnID*/0, /*OldInsnID*/0, /*OpIdx*/7, /*OperandRenderer*/GIMT_Encode2(GICR_renderExtractSWZ), // auxiliary
        GIR_MergeMemOperands, /*InsnID*/0, /*NumInsns*/1, /*MergeInsnID's*/0,
        GIR_ConstrainSelectedInstOperands, /*InsnID*/0,
        GIR_EraseFromParent, /*InsnID*/0,
        // GIR_Coverage, 5749,
        GIR_Done,
      // Label 7417: @542809
      GIM_Try, /*On fail goto*//*Label 7418*/ GIMT_Encode4(542897), // Rule ID 5753 //
        GIM_CheckConstantInt8, /*MI*/0, /*Op*/2, 0,
        GIM_CheckConstantInt8, /*MI*/0, /*Op*/3, 0,
        // MIs[0] offset
        GIM_CheckIsImm, /*MI*/0, /*Op*/5,
        // MIs[0] format
        GIM_CheckIsImm, /*MI*/0, /*Op*/6,
        // MIs[0] auxiliary
        GIM_CheckIsImm, /*MI*/0, /*Op*/7,
        // MIs[0] Operand 8
        GIM_CheckLiteralInt, /*MI*/0, /*Op*/8, GIMT_Encode8(0),
        GIM_CheckComplexPattern, /*MI*/0, /*Op*/4, /*Renderer*/GIMT_Encode2(0), GIMT_Encode2(GICP_gi_buf_soffset),
        // (SItbuffer_store v4f32:{ *:[v4f32] }:$vdata, v4i32:{ *:[v4i32] }:$rsrc, 0:{ *:[i32] }, 0:{ *:[i32] }, (BUFSOffset:{ *:[i32] } i32:{ *:[i32] }:$soffset), (timm:{ *:[i32] }):$offset, (timm:{ *:[i32] }):$format, (timm:{ *:[i32] }):$auxiliary, 0:{ *:[i1] })  =>  (TBUFFER_STORE_FORMAT_XYZW_VBUFFER_OFFSET_exact anonymous_15034:{ *:[v4f32] }:$vdata, SReg_128:{ *:[v4i32] }:$rsrc, SCSrc_b32:{ *:[i32] }:$soffset, (timm:{ *:[i32] }):$offset, (as_i8timm:{ *:[i8] } ?:{ *:[i32] }:$format), (extract_cpol:{ *:[i32] } ?:{ *:[i32] }:$auxiliary), (extract_swz:{ *:[i1] } ?:{ *:[i32] }:$auxiliary))
        GIR_BuildMI, /*InsnID*/0, /*Opcode*/GIMT_Encode2(AMDGPU::TBUFFER_STORE_FORMAT_XYZW_VBUFFER_OFFSET_exact),
        GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/0, // vdata
        GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/1, // rsrc
        GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/0, // soffset
        GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/5, // offset
        GIR_CustomOperandRenderer, /*InsnID*/0, /*OldInsnID*/0, /*OpIdx*/6, /*OperandRenderer*/GIMT_Encode2(GICR_renderTruncTImm), // format
        GIR_CustomOperandRenderer, /*InsnID*/0, /*OldInsnID*/0, /*OpIdx*/7, /*OperandRenderer*/GIMT_Encode2(GICR_renderExtractCPol), // auxiliary
        GIR_CustomOperandRenderer, /*InsnID*/0, /*OldInsnID*/0, /*OpIdx*/7, /*OperandRenderer*/GIMT_Encode2(GICR_renderExtractSWZ), // auxiliary
        GIR_MergeMemOperands, /*InsnID*/0, /*NumInsns*/1, /*MergeInsnID's*/0,
        GIR_ConstrainSelectedInstOperands, /*InsnID*/0,
        GIR_EraseFromParent, /*InsnID*/0,
        // GIR_Coverage, 5753,
        GIR_Done,
      // Label 7418: @542897
      GIM_Try, /*On fail goto*//*Label 7419*/ GIMT_Encode4(542988), // Rule ID 5719 //
        GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasUnrestrictedSOffset),
        GIM_CheckConstantInt8, /*MI*/0, /*Op*/2, 0,
        // MIs[0] offset
        GIM_CheckIsImm, /*MI*/0, /*Op*/5,
        // MIs[0] format
        GIM_CheckIsImm, /*MI*/0, /*Op*/6,
        // MIs[0] auxiliary
        GIM_CheckIsImm, /*MI*/0, /*Op*/7,
        // MIs[0] Operand 8
        GIM_CheckLiteralInt, /*MI*/0, /*Op*/8, GIMT_Encode8(0),
        GIM_CheckComplexPattern, /*MI*/0, /*Op*/4, /*Renderer*/GIMT_Encode2(0), GIMT_Encode2(GICP_gi_buf_soffset),
        // (SItbuffer_store v4i32:{ *:[v4i32] }:$vdata, v4i32:{ *:[v4i32] }:$rsrc, 0:{ *:[i32] }, i32:{ *:[i32] }:$voffset, (BUFSOffset:{ *:[i32] } i32:{ *:[i32] }:$soffset), (timm:{ *:[i32] }):$offset, (timm:{ *:[i32] }):$format, (timm:{ *:[i32] }):$auxiliary, 0:{ *:[i1] })  =>  (TBUFFER_STORE_FORMAT_XYZW_OFFEN_exact anonymous_15034:{ *:[v4i32] }:$vdata, VGPR_32:{ *:[i32] }:$voffset, SReg_128:{ *:[v4i32] }:$rsrc, SCSrc_b32:{ *:[i32] }:$soffset, (timm:{ *:[i32] }):$offset, (as_i8timm:{ *:[i8] } ?:{ *:[i32] }:$format), (extract_cpol:{ *:[i32] } ?:{ *:[i32] }:$auxiliary), (extract_swz:{ *:[i1] } ?:{ *:[i32] }:$auxiliary))
        GIR_BuildMI, /*InsnID*/0, /*Opcode*/GIMT_Encode2(AMDGPU::TBUFFER_STORE_FORMAT_XYZW_OFFEN_exact),
        GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/0, // vdata
        GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/3, // voffset
        GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/1, // rsrc
        GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/0, // soffset
        GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/5, // offset
        GIR_CustomOperandRenderer, /*InsnID*/0, /*OldInsnID*/0, /*OpIdx*/6, /*OperandRenderer*/GIMT_Encode2(GICR_renderTruncTImm), // format
        GIR_CustomOperandRenderer, /*InsnID*/0, /*OldInsnID*/0, /*OpIdx*/7, /*OperandRenderer*/GIMT_Encode2(GICR_renderExtractCPol), // auxiliary
        GIR_CustomOperandRenderer, /*InsnID*/0, /*OldInsnID*/0, /*OpIdx*/7, /*OperandRenderer*/GIMT_Encode2(GICR_renderExtractSWZ), // auxiliary
        GIR_MergeMemOperands, /*InsnID*/0, /*NumInsns*/1, /*MergeInsnID's*/0,
        GIR_ConstrainSelectedInstOperands, /*InsnID*/0,
        GIR_EraseFromParent, /*InsnID*/0,
        // GIR_Coverage, 5719,
        GIR_Done,
      // Label 7419: @542988
      GIM_Try, /*On fail goto*//*Label 7420*/ GIMT_Encode4(543076), // Rule ID 5723 //
        GIM_CheckConstantInt8, /*MI*/0, /*Op*/2, 0,
        // MIs[0] offset
        GIM_CheckIsImm, /*MI*/0, /*Op*/5,
        // MIs[0] format
        GIM_CheckIsImm, /*MI*/0, /*Op*/6,
        // MIs[0] auxiliary
        GIM_CheckIsImm, /*MI*/0, /*Op*/7,
        // MIs[0] Operand 8
        GIM_CheckLiteralInt, /*MI*/0, /*Op*/8, GIMT_Encode8(0),
        GIM_CheckComplexPattern, /*MI*/0, /*Op*/4, /*Renderer*/GIMT_Encode2(0), GIMT_Encode2(GICP_gi_buf_soffset),
        // (SItbuffer_store v4i32:{ *:[v4i32] }:$vdata, v4i32:{ *:[v4i32] }:$rsrc, 0:{ *:[i32] }, i32:{ *:[i32] }:$voffset, (BUFSOffset:{ *:[i32] } i32:{ *:[i32] }:$soffset), (timm:{ *:[i32] }):$offset, (timm:{ *:[i32] }):$format, (timm:{ *:[i32] }):$auxiliary, 0:{ *:[i1] })  =>  (TBUFFER_STORE_FORMAT_XYZW_VBUFFER_OFFEN_exact anonymous_15034:{ *:[v4i32] }:$vdata, VGPR_32:{ *:[i32] }:$voffset, SReg_128:{ *:[v4i32] }:$rsrc, SCSrc_b32:{ *:[i32] }:$soffset, (timm:{ *:[i32] }):$offset, (as_i8timm:{ *:[i8] } ?:{ *:[i32] }:$format), (extract_cpol:{ *:[i32] } ?:{ *:[i32] }:$auxiliary), (extract_swz:{ *:[i1] } ?:{ *:[i32] }:$auxiliary))
        GIR_BuildMI, /*InsnID*/0, /*Opcode*/GIMT_Encode2(AMDGPU::TBUFFER_STORE_FORMAT_XYZW_VBUFFER_OFFEN_exact),
        GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/0, // vdata
        GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/3, // voffset
        GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/1, // rsrc
        GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/0, // soffset
        GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/5, // offset
        GIR_CustomOperandRenderer, /*InsnID*/0, /*OldInsnID*/0, /*OpIdx*/6, /*OperandRenderer*/GIMT_Encode2(GICR_renderTruncTImm), // format
        GIR_CustomOperandRenderer, /*InsnID*/0, /*OldInsnID*/0, /*OpIdx*/7, /*OperandRenderer*/GIMT_Encode2(GICR_renderExtractCPol), // auxiliary
        GIR_CustomOperandRenderer, /*InsnID*/0, /*OldInsnID*/0, /*OpIdx*/7, /*OperandRenderer*/GIMT_Encode2(GICR_renderExtractSWZ), // auxiliary
        GIR_MergeMemOperands, /*InsnID*/0, /*NumInsns*/1, /*MergeInsnID's*/0,
        GIR_ConstrainSelectedInstOperands, /*InsnID*/0,
        GIR_EraseFromParent, /*InsnID*/0,
        // GIR_Coverage, 5723,
        GIR_Done,
      // Label 7420: @543076
      GIM_Try, /*On fail goto*//*Label 7421*/ GIMT_Encode4(543167), // Rule ID 5751 //
        GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasUnrestrictedSOffset),
        GIM_CheckConstantInt8, /*MI*/0, /*Op*/2, 0,
        // MIs[0] offset
        GIM_CheckIsImm, /*MI*/0, /*Op*/5,
        // MIs[0] format
        GIM_CheckIsImm, /*MI*/0, /*Op*/6,
        // MIs[0] auxiliary
        GIM_CheckIsImm, /*MI*/0, /*Op*/7,
        // MIs[0] Operand 8
        GIM_CheckLiteralInt, /*MI*/0, /*Op*/8, GIMT_Encode8(0),
        GIM_CheckComplexPattern, /*MI*/0, /*Op*/4, /*Renderer*/GIMT_Encode2(0), GIMT_Encode2(GICP_gi_buf_soffset),
        // (SItbuffer_store v4f32:{ *:[v4f32] }:$vdata, v4i32:{ *:[v4i32] }:$rsrc, 0:{ *:[i32] }, i32:{ *:[i32] }:$voffset, (BUFSOffset:{ *:[i32] } i32:{ *:[i32] }:$soffset), (timm:{ *:[i32] }):$offset, (timm:{ *:[i32] }):$format, (timm:{ *:[i32] }):$auxiliary, 0:{ *:[i1] })  =>  (TBUFFER_STORE_FORMAT_XYZW_OFFEN_exact anonymous_15034:{ *:[v4f32] }:$vdata, VGPR_32:{ *:[i32] }:$voffset, SReg_128:{ *:[v4i32] }:$rsrc, SCSrc_b32:{ *:[i32] }:$soffset, (timm:{ *:[i32] }):$offset, (as_i8timm:{ *:[i8] } ?:{ *:[i32] }:$format), (extract_cpol:{ *:[i32] } ?:{ *:[i32] }:$auxiliary), (extract_swz:{ *:[i1] } ?:{ *:[i32] }:$auxiliary))
        GIR_BuildMI, /*InsnID*/0, /*Opcode*/GIMT_Encode2(AMDGPU::TBUFFER_STORE_FORMAT_XYZW_OFFEN_exact),
        GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/0, // vdata
        GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/3, // voffset
        GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/1, // rsrc
        GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/0, // soffset
        GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/5, // offset
        GIR_CustomOperandRenderer, /*InsnID*/0, /*OldInsnID*/0, /*OpIdx*/6, /*OperandRenderer*/GIMT_Encode2(GICR_renderTruncTImm), // format
        GIR_CustomOperandRenderer, /*InsnID*/0, /*OldInsnID*/0, /*OpIdx*/7, /*OperandRenderer*/GIMT_Encode2(GICR_renderExtractCPol), // auxiliary
        GIR_CustomOperandRenderer, /*InsnID*/0, /*OldInsnID*/0, /*OpIdx*/7, /*OperandRenderer*/GIMT_Encode2(GICR_renderExtractSWZ), // auxiliary
        GIR_MergeMemOperands, /*InsnID*/0, /*NumInsns*/1, /*MergeInsnID's*/0,
        GIR_ConstrainSelectedInstOperands, /*InsnID*/0,
        GIR_EraseFromParent, /*InsnID*/0,
        // GIR_Coverage, 5751,
        GIR_Done,
      // Label 7421: @543167
      GIM_Try, /*On fail goto*//*Label 7422*/ GIMT_Encode4(543255), // Rule ID 5755 //
        GIM_CheckConstantInt8, /*MI*/0, /*Op*/2, 0,
        // MIs[0] offset
        GIM_CheckIsImm, /*MI*/0, /*Op*/5,
        // MIs[0] format
        GIM_CheckIsImm, /*MI*/0, /*Op*/6,
        // MIs[0] auxiliary
        GIM_CheckIsImm, /*MI*/0, /*Op*/7,
        // MIs[0] Operand 8
        GIM_CheckLiteralInt, /*MI*/0, /*Op*/8, GIMT_Encode8(0),
        GIM_CheckComplexPattern, /*MI*/0, /*Op*/4, /*Renderer*/GIMT_Encode2(0), GIMT_Encode2(GICP_gi_buf_soffset),
        // (SItbuffer_store v4f32:{ *:[v4f32] }:$vdata, v4i32:{ *:[v4i32] }:$rsrc, 0:{ *:[i32] }, i32:{ *:[i32] }:$voffset, (BUFSOffset:{ *:[i32] } i32:{ *:[i32] }:$soffset), (timm:{ *:[i32] }):$offset, (timm:{ *:[i32] }):$format, (timm:{ *:[i32] }):$auxiliary, 0:{ *:[i1] })  =>  (TBUFFER_STORE_FORMAT_XYZW_VBUFFER_OFFEN_exact anonymous_15034:{ *:[v4f32] }:$vdata, VGPR_32:{ *:[i32] }:$voffset, SReg_128:{ *:[v4i32] }:$rsrc, SCSrc_b32:{ *:[i32] }:$soffset, (timm:{ *:[i32] }):$offset, (as_i8timm:{ *:[i8] } ?:{ *:[i32] }:$format), (extract_cpol:{ *:[i32] } ?:{ *:[i32] }:$auxiliary), (extract_swz:{ *:[i1] } ?:{ *:[i32] }:$auxiliary))
        GIR_BuildMI, /*InsnID*/0, /*Opcode*/GIMT_Encode2(AMDGPU::TBUFFER_STORE_FORMAT_XYZW_VBUFFER_OFFEN_exact),
        GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/0, // vdata
        GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/3, // voffset
        GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/1, // rsrc
        GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/0, // soffset
        GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/5, // offset
        GIR_CustomOperandRenderer, /*InsnID*/0, /*OldInsnID*/0, /*OpIdx*/6, /*OperandRenderer*/GIMT_Encode2(GICR_renderTruncTImm), // format
        GIR_CustomOperandRenderer, /*InsnID*/0, /*OldInsnID*/0, /*OpIdx*/7, /*OperandRenderer*/GIMT_Encode2(GICR_renderExtractCPol), // auxiliary
        GIR_CustomOperandRenderer, /*InsnID*/0, /*OldInsnID*/0, /*OpIdx*/7, /*OperandRenderer*/GIMT_Encode2(GICR_renderExtractSWZ), // auxiliary
        GIR_MergeMemOperands, /*InsnID*/0, /*NumInsns*/1, /*MergeInsnID's*/0,
        GIR_ConstrainSelectedInstOperands, /*InsnID*/0,
        GIR_EraseFromParent, /*InsnID*/0,
        // GIR_Coverage, 5755,
        GIR_Done,
      // Label 7422: @543255
      GIM_Try, /*On fail goto*//*Label 7423*/ GIMT_Encode4(543338), // Rule ID 5718 //
        GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasUnrestrictedSOffset),
        GIM_CheckConstantInt8, /*MI*/0, /*Op*/3, 0,
        // MIs[0] offset
        GIM_CheckIsImm, /*MI*/0, /*Op*/5,
        // MIs[0] format
        GIM_CheckIsImm, /*MI*/0, /*Op*/6,
        // MIs[0] auxiliary
        GIM_CheckIsImm, /*MI*/0, /*Op*/7,
        // MIs[0] Operand 8
        GIM_CheckIsImm, /*MI*/0, /*Op*/8,
        GIM_CheckComplexPattern, /*MI*/0, /*Op*/4, /*Renderer*/GIMT_Encode2(0), GIMT_Encode2(GICP_gi_buf_soffset),
        // (SItbuffer_store v4i32:{ *:[v4i32] }:$vdata, v4i32:{ *:[v4i32] }:$rsrc, i32:{ *:[i32] }:$vindex, 0:{ *:[i32] }, (BUFSOffset:{ *:[i32] } i32:{ *:[i32] }:$soffset), (timm:{ *:[i32] }):$offset, (timm:{ *:[i32] }):$format, (timm:{ *:[i32] }):$auxiliary, (timm:{ *:[i1] }))  =>  (TBUFFER_STORE_FORMAT_XYZW_IDXEN_exact anonymous_15034:{ *:[v4i32] }:$vdata, VGPR_32:{ *:[i32] }:$vindex, SReg_128:{ *:[v4i32] }:$rsrc, SCSrc_b32:{ *:[i32] }:$soffset, (timm:{ *:[i32] }):$offset, (as_i8timm:{ *:[i8] } ?:{ *:[i32] }:$format), (extract_cpol:{ *:[i32] } ?:{ *:[i32] }:$auxiliary), (extract_swz:{ *:[i1] } ?:{ *:[i32] }:$auxiliary))
        GIR_BuildMI, /*InsnID*/0, /*Opcode*/GIMT_Encode2(AMDGPU::TBUFFER_STORE_FORMAT_XYZW_IDXEN_exact),
        GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/0, // vdata
        GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/2, // vindex
        GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/1, // rsrc
        GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/0, // soffset
        GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/5, // offset
        GIR_CustomOperandRenderer, /*InsnID*/0, /*OldInsnID*/0, /*OpIdx*/6, /*OperandRenderer*/GIMT_Encode2(GICR_renderTruncTImm), // format
        GIR_CustomOperandRenderer, /*InsnID*/0, /*OldInsnID*/0, /*OpIdx*/7, /*OperandRenderer*/GIMT_Encode2(GICR_renderExtractCPol), // auxiliary
        GIR_CustomOperandRenderer, /*InsnID*/0, /*OldInsnID*/0, /*OpIdx*/7, /*OperandRenderer*/GIMT_Encode2(GICR_renderExtractSWZ), // auxiliary
        GIR_MergeMemOperands, /*InsnID*/0, /*NumInsns*/1, /*MergeInsnID's*/0,
        GIR_ConstrainSelectedInstOperands, /*InsnID*/0,
        GIR_EraseFromParent, /*InsnID*/0,
        // GIR_Coverage, 5718,
        GIR_Done,
      // Label 7423: @543338
      GIM_Try, /*On fail goto*//*Label 7424*/ GIMT_Encode4(543418), // Rule ID 5722 //
        GIM_CheckConstantInt8, /*MI*/0, /*Op*/3, 0,
        // MIs[0] offset
        GIM_CheckIsImm, /*MI*/0, /*Op*/5,
        // MIs[0] format
        GIM_CheckIsImm, /*MI*/0, /*Op*/6,
        // MIs[0] auxiliary
        GIM_CheckIsImm, /*MI*/0, /*Op*/7,
        // MIs[0] Operand 8
        GIM_CheckIsImm, /*MI*/0, /*Op*/8,
        GIM_CheckComplexPattern, /*MI*/0, /*Op*/4, /*Renderer*/GIMT_Encode2(0), GIMT_Encode2(GICP_gi_buf_soffset),
        // (SItbuffer_store v4i32:{ *:[v4i32] }:$vdata, v4i32:{ *:[v4i32] }:$rsrc, i32:{ *:[i32] }:$vindex, 0:{ *:[i32] }, (BUFSOffset:{ *:[i32] } i32:{ *:[i32] }:$soffset), (timm:{ *:[i32] }):$offset, (timm:{ *:[i32] }):$format, (timm:{ *:[i32] }):$auxiliary, (timm:{ *:[i1] }))  =>  (TBUFFER_STORE_FORMAT_XYZW_VBUFFER_IDXEN_exact anonymous_15034:{ *:[v4i32] }:$vdata, VGPR_32:{ *:[i32] }:$vindex, SReg_128:{ *:[v4i32] }:$rsrc, SCSrc_b32:{ *:[i32] }:$soffset, (timm:{ *:[i32] }):$offset, (as_i8timm:{ *:[i8] } ?:{ *:[i32] }:$format), (extract_cpol:{ *:[i32] } ?:{ *:[i32] }:$auxiliary), (extract_swz:{ *:[i1] } ?:{ *:[i32] }:$auxiliary))
        GIR_BuildMI, /*InsnID*/0, /*Opcode*/GIMT_Encode2(AMDGPU::TBUFFER_STORE_FORMAT_XYZW_VBUFFER_IDXEN_exact),
        GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/0, // vdata
        GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/2, // vindex
        GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/1, // rsrc
        GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/0, // soffset
        GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/5, // offset
        GIR_CustomOperandRenderer, /*InsnID*/0, /*OldInsnID*/0, /*OpIdx*/6, /*OperandRenderer*/GIMT_Encode2(GICR_renderTruncTImm), // format
        GIR_CustomOperandRenderer, /*InsnID*/0, /*OldInsnID*/0, /*OpIdx*/7, /*OperandRenderer*/GIMT_Encode2(GICR_renderExtractCPol), // auxiliary
        GIR_CustomOperandRenderer, /*InsnID*/0, /*OldInsnID*/0, /*OpIdx*/7, /*OperandRenderer*/GIMT_Encode2(GICR_renderExtractSWZ), // auxiliary
        GIR_MergeMemOperands, /*InsnID*/0, /*NumInsns*/1, /*MergeInsnID's*/0,
        GIR_ConstrainSelectedInstOperands, /*InsnID*/0,
        GIR_EraseFromParent, /*InsnID*/0,
        // GIR_Coverage, 5722,
        GIR_Done,
      // Label 7424: @543418
      GIM_Try, /*On fail goto*//*Label 7425*/ GIMT_Encode4(543501), // Rule ID 5750 //
        GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasUnrestrictedSOffset),
        GIM_CheckConstantInt8, /*MI*/0, /*Op*/3, 0,
        // MIs[0] offset
        GIM_CheckIsImm, /*MI*/0, /*Op*/5,
        // MIs[0] format
        GIM_CheckIsImm, /*MI*/0, /*Op*/6,
        // MIs[0] auxiliary
        GIM_CheckIsImm, /*MI*/0, /*Op*/7,
        // MIs[0] Operand 8
        GIM_CheckIsImm, /*MI*/0, /*Op*/8,
        GIM_CheckComplexPattern, /*MI*/0, /*Op*/4, /*Renderer*/GIMT_Encode2(0), GIMT_Encode2(GICP_gi_buf_soffset),
        // (SItbuffer_store v4f32:{ *:[v4f32] }:$vdata, v4i32:{ *:[v4i32] }:$rsrc, i32:{ *:[i32] }:$vindex, 0:{ *:[i32] }, (BUFSOffset:{ *:[i32] } i32:{ *:[i32] }:$soffset), (timm:{ *:[i32] }):$offset, (timm:{ *:[i32] }):$format, (timm:{ *:[i32] }):$auxiliary, (timm:{ *:[i1] }))  =>  (TBUFFER_STORE_FORMAT_XYZW_IDXEN_exact anonymous_15034:{ *:[v4f32] }:$vdata, VGPR_32:{ *:[i32] }:$vindex, SReg_128:{ *:[v4i32] }:$rsrc, SCSrc_b32:{ *:[i32] }:$soffset, (timm:{ *:[i32] }):$offset, (as_i8timm:{ *:[i8] } ?:{ *:[i32] }:$format), (extract_cpol:{ *:[i32] } ?:{ *:[i32] }:$auxiliary), (extract_swz:{ *:[i1] } ?:{ *:[i32] }:$auxiliary))
        GIR_BuildMI, /*InsnID*/0, /*Opcode*/GIMT_Encode2(AMDGPU::TBUFFER_STORE_FORMAT_XYZW_IDXEN_exact),
        GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/0, // vdata
        GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/2, // vindex
        GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/1, // rsrc
        GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/0, // soffset
        GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/5, // offset
        GIR_CustomOperandRenderer, /*InsnID*/0, /*OldInsnID*/0, /*OpIdx*/6, /*OperandRenderer*/GIMT_Encode2(GICR_renderTruncTImm), // format
        GIR_CustomOperandRenderer, /*InsnID*/0, /*OldInsnID*/0, /*OpIdx*/7, /*OperandRenderer*/GIMT_Encode2(GICR_renderExtractCPol), // auxiliary
        GIR_CustomOperandRenderer, /*InsnID*/0, /*OldInsnID*/0, /*OpIdx*/7, /*OperandRenderer*/GIMT_Encode2(GICR_renderExtractSWZ), // auxiliary
        GIR_MergeMemOperands, /*InsnID*/0, /*NumInsns*/1, /*MergeInsnID's*/0,
        GIR_ConstrainSelectedInstOperands, /*InsnID*/0,
        GIR_EraseFromParent, /*InsnID*/0,
        // GIR_Coverage, 5750,
        GIR_Done,
      // Label 7425: @543501
      GIM_Try, /*On fail goto*//*Label 7426*/ GIMT_Encode4(543581), // Rule ID 5754 //
        GIM_CheckConstantInt8, /*MI*/0, /*Op*/3, 0,
        // MIs[0] offset
        GIM_CheckIsImm, /*MI*/0, /*Op*/5,
        // MIs[0] format
        GIM_CheckIsImm, /*MI*/0, /*Op*/6,
        // MIs[0] auxiliary
        GIM_CheckIsImm, /*MI*/0, /*Op*/7,
        // MIs[0] Operand 8
        GIM_CheckIsImm, /*MI*/0, /*Op*/8,
        GIM_CheckComplexPattern, /*MI*/0, /*Op*/4, /*Renderer*/GIMT_Encode2(0), GIMT_Encode2(GICP_gi_buf_soffset),
        // (SItbuffer_store v4f32:{ *:[v4f32] }:$vdata, v4i32:{ *:[v4i32] }:$rsrc, i32:{ *:[i32] }:$vindex, 0:{ *:[i32] }, (BUFSOffset:{ *:[i32] } i32:{ *:[i32] }:$soffset), (timm:{ *:[i32] }):$offset, (timm:{ *:[i32] }):$format, (timm:{ *:[i32] }):$auxiliary, (timm:{ *:[i1] }))  =>  (TBUFFER_STORE_FORMAT_XYZW_VBUFFER_IDXEN_exact anonymous_15034:{ *:[v4f32] }:$vdata, VGPR_32:{ *:[i32] }:$vindex, SReg_128:{ *:[v4i32] }:$rsrc, SCSrc_b32:{ *:[i32] }:$soffset, (timm:{ *:[i32] }):$offset, (as_i8timm:{ *:[i8] } ?:{ *:[i32] }:$format), (extract_cpol:{ *:[i32] } ?:{ *:[i32] }:$auxiliary), (extract_swz:{ *:[i1] } ?:{ *:[i32] }:$auxiliary))
        GIR_BuildMI, /*InsnID*/0, /*Opcode*/GIMT_Encode2(AMDGPU::TBUFFER_STORE_FORMAT_XYZW_VBUFFER_IDXEN_exact),
        GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/0, // vdata
        GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/2, // vindex
        GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/1, // rsrc
        GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/0, // soffset
        GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/5, // offset
        GIR_CustomOperandRenderer, /*InsnID*/0, /*OldInsnID*/0, /*OpIdx*/6, /*OperandRenderer*/GIMT_Encode2(GICR_renderTruncTImm), // format
        GIR_CustomOperandRenderer, /*InsnID*/0, /*OldInsnID*/0, /*OpIdx*/7, /*OperandRenderer*/GIMT_Encode2(GICR_renderExtractCPol), // auxiliary
        GIR_CustomOperandRenderer, /*InsnID*/0, /*OldInsnID*/0, /*OpIdx*/7, /*OperandRenderer*/GIMT_Encode2(GICR_renderExtractSWZ), // auxiliary
        GIR_MergeMemOperands, /*InsnID*/0, /*NumInsns*/1, /*MergeInsnID's*/0,
        GIR_ConstrainSelectedInstOperands, /*InsnID*/0,
        GIR_EraseFromParent, /*InsnID*/0,
        // GIR_Coverage, 5754,
        GIR_Done,
      // Label 7426: @543581
      GIM_Try, /*On fail goto*//*Label 7427*/ GIMT_Encode4(543700), // Rule ID 5720 //
        GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasUnrestrictedSOffset),
        // MIs[0] offset
        GIM_CheckIsImm, /*MI*/0, /*Op*/5,
        // MIs[0] format
        GIM_CheckIsImm, /*MI*/0, /*Op*/6,
        // MIs[0] auxiliary
        GIM_CheckIsImm, /*MI*/0, /*Op*/7,
        // MIs[0] Operand 8
        GIM_CheckIsImm, /*MI*/0, /*Op*/8,
        GIM_CheckComplexPattern, /*MI*/0, /*Op*/4, /*Renderer*/GIMT_Encode2(0), GIMT_Encode2(GICP_gi_buf_soffset),
        // (SItbuffer_store v4i32:{ *:[v4i32] }:$vdata, v4i32:{ *:[v4i32] }:$rsrc, i32:{ *:[i32] }:$vindex, i32:{ *:[i32] }:$voffset, (BUFSOffset:{ *:[i32] } i32:{ *:[i32] }:$soffset), (timm:{ *:[i32] }):$offset, (timm:{ *:[i32] }):$format, (timm:{ *:[i32] }):$auxiliary, (timm:{ *:[i1] }))  =>  (TBUFFER_STORE_FORMAT_XYZW_BOTHEN_exact anonymous_15034:{ *:[v4i32] }:$vdata, (REG_SEQUENCE:{ *:[i64] } VReg_64:{ *:[i32] }, VGPR_32:{ *:[i32] }:$vindex, sub0:{ *:[i32] }, VGPR_32:{ *:[i32] }:$voffset, sub1:{ *:[i32] }), SReg_128:{ *:[v4i32] }:$rsrc, SCSrc_b32:{ *:[i32] }:$soffset, (timm:{ *:[i32] }):$offset, (as_i8timm:{ *:[i8] } ?:{ *:[i32] }:$format), (extract_cpol:{ *:[i32] } ?:{ *:[i32] }:$auxiliary), (extract_swz:{ *:[i1] } ?:{ *:[i32] }:$auxiliary))
        GIR_MakeTempReg, /*TempRegID*/0, /*TypeID*/GILLT_s64,
        GIR_BuildMI, /*InsnID*/1, /*Opcode*/GIMT_Encode2(TargetOpcode::REG_SEQUENCE),
        GIR_AddTempRegister, /*InsnID*/1, /*TempRegID*/0, /*TempRegFlags*/GIMT_Encode2(RegState::Define),
        GIR_Copy, /*NewInsnID*/1, /*OldInsnID*/0, /*OpIdx*/2, // vindex
        GIR_AddImm8, /*InsnID*/1, /*SubRegIndex*/3,
        GIR_Copy, /*NewInsnID*/1, /*OldInsnID*/0, /*OpIdx*/3, // voffset
        GIR_AddImm8, /*InsnID*/1, /*SubRegIndex*/11,
        GIR_ConstrainOperandRC, /*InsnID*/1, /*Op*/0, GIMT_Encode2(AMDGPU::VReg_64RegClassID),
        GIR_ConstrainOperandRC, /*InsnID*/1, /*Op*/1, GIMT_Encode2(AMDGPU::VGPR_32RegClassID),
        GIR_ConstrainOperandRC, /*InsnID*/1, /*Op*/3, GIMT_Encode2(AMDGPU::VGPR_32RegClassID),
        GIR_BuildMI, /*InsnID*/0, /*Opcode*/GIMT_Encode2(AMDGPU::TBUFFER_STORE_FORMAT_XYZW_BOTHEN_exact),
        GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/0, // vdata
        GIR_AddSimpleTempRegister, /*InsnID*/0, /*TempRegID*/0,
        GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/1, // rsrc
        GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/0, // soffset
        GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/5, // offset
        GIR_CustomOperandRenderer, /*InsnID*/0, /*OldInsnID*/0, /*OpIdx*/6, /*OperandRenderer*/GIMT_Encode2(GICR_renderTruncTImm), // format
        GIR_CustomOperandRenderer, /*InsnID*/0, /*OldInsnID*/0, /*OpIdx*/7, /*OperandRenderer*/GIMT_Encode2(GICR_renderExtractCPol), // auxiliary
        GIR_CustomOperandRenderer, /*InsnID*/0, /*OldInsnID*/0, /*OpIdx*/7, /*OperandRenderer*/GIMT_Encode2(GICR_renderExtractSWZ), // auxiliary
        GIR_MergeMemOperands, /*InsnID*/0, /*NumInsns*/1, /*MergeInsnID's*/0,
        GIR_ConstrainSelectedInstOperands, /*InsnID*/0,
        GIR_EraseFromParent, /*InsnID*/0,
        // GIR_Coverage, 5720,
        GIR_Done,
      // Label 7427: @543700
      GIM_Try, /*On fail goto*//*Label 7428*/ GIMT_Encode4(543816), // Rule ID 5724 //
        // MIs[0] offset
        GIM_CheckIsImm, /*MI*/0, /*Op*/5,
        // MIs[0] format
        GIM_CheckIsImm, /*MI*/0, /*Op*/6,
        // MIs[0] auxiliary
        GIM_CheckIsImm, /*MI*/0, /*Op*/7,
        // MIs[0] Operand 8
        GIM_CheckIsImm, /*MI*/0, /*Op*/8,
        GIM_CheckComplexPattern, /*MI*/0, /*Op*/4, /*Renderer*/GIMT_Encode2(0), GIMT_Encode2(GICP_gi_buf_soffset),
        // (SItbuffer_store v4i32:{ *:[v4i32] }:$vdata, v4i32:{ *:[v4i32] }:$rsrc, i32:{ *:[i32] }:$vindex, i32:{ *:[i32] }:$voffset, (BUFSOffset:{ *:[i32] } i32:{ *:[i32] }:$soffset), (timm:{ *:[i32] }):$offset, (timm:{ *:[i32] }):$format, (timm:{ *:[i32] }):$auxiliary, (timm:{ *:[i1] }))  =>  (TBUFFER_STORE_FORMAT_XYZW_VBUFFER_BOTHEN_exact anonymous_15034:{ *:[v4i32] }:$vdata, (REG_SEQUENCE:{ *:[i64] } VReg_64:{ *:[i32] }, VGPR_32:{ *:[i32] }:$vindex, sub0:{ *:[i32] }, VGPR_32:{ *:[i32] }:$voffset, sub1:{ *:[i32] }), SReg_128:{ *:[v4i32] }:$rsrc, SCSrc_b32:{ *:[i32] }:$soffset, (timm:{ *:[i32] }):$offset, (as_i8timm:{ *:[i8] } ?:{ *:[i32] }:$format), (extract_cpol:{ *:[i32] } ?:{ *:[i32] }:$auxiliary), (extract_swz:{ *:[i1] } ?:{ *:[i32] }:$auxiliary))
        GIR_MakeTempReg, /*TempRegID*/0, /*TypeID*/GILLT_s64,
        GIR_BuildMI, /*InsnID*/1, /*Opcode*/GIMT_Encode2(TargetOpcode::REG_SEQUENCE),
        GIR_AddTempRegister, /*InsnID*/1, /*TempRegID*/0, /*TempRegFlags*/GIMT_Encode2(RegState::Define),
        GIR_Copy, /*NewInsnID*/1, /*OldInsnID*/0, /*OpIdx*/2, // vindex
        GIR_AddImm8, /*InsnID*/1, /*SubRegIndex*/3,
        GIR_Copy, /*NewInsnID*/1, /*OldInsnID*/0, /*OpIdx*/3, // voffset
        GIR_AddImm8, /*InsnID*/1, /*SubRegIndex*/11,
        GIR_ConstrainOperandRC, /*InsnID*/1, /*Op*/0, GIMT_Encode2(AMDGPU::VReg_64RegClassID),
        GIR_ConstrainOperandRC, /*InsnID*/1, /*Op*/1, GIMT_Encode2(AMDGPU::VGPR_32RegClassID),
        GIR_ConstrainOperandRC, /*InsnID*/1, /*Op*/3, GIMT_Encode2(AMDGPU::VGPR_32RegClassID),
        GIR_BuildMI, /*InsnID*/0, /*Opcode*/GIMT_Encode2(AMDGPU::TBUFFER_STORE_FORMAT_XYZW_VBUFFER_BOTHEN_exact),
        GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/0, // vdata
        GIR_AddSimpleTempRegister, /*InsnID*/0, /*TempRegID*/0,
        GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/1, // rsrc
        GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/0, // soffset
        GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/5, // offset
        GIR_CustomOperandRenderer, /*InsnID*/0, /*OldInsnID*/0, /*OpIdx*/6, /*OperandRenderer*/GIMT_Encode2(GICR_renderTruncTImm), // format
        GIR_CustomOperandRenderer, /*InsnID*/0, /*OldInsnID*/0, /*OpIdx*/7, /*OperandRenderer*/GIMT_Encode2(GICR_renderExtractCPol), // auxiliary
        GIR_CustomOperandRenderer, /*InsnID*/0, /*OldInsnID*/0, /*OpIdx*/7, /*OperandRenderer*/GIMT_Encode2(GICR_renderExtractSWZ), // auxiliary
        GIR_MergeMemOperands, /*InsnID*/0, /*NumInsns*/1, /*MergeInsnID's*/0,
        GIR_ConstrainSelectedInstOperands, /*InsnID*/0,
        GIR_EraseFromParent, /*InsnID*/0,
        // GIR_Coverage, 5724,
        GIR_Done,
      // Label 7428: @543816
      GIM_Try, /*On fail goto*//*Label 7429*/ GIMT_Encode4(543935), // Rule ID 5752 //
        GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasUnrestrictedSOffset),
        // MIs[0] offset
        GIM_CheckIsImm, /*MI*/0, /*Op*/5,
        // MIs[0] format
        GIM_CheckIsImm, /*MI*/0, /*Op*/6,
        // MIs[0] auxiliary
        GIM_CheckIsImm, /*MI*/0, /*Op*/7,
        // MIs[0] Operand 8
        GIM_CheckIsImm, /*MI*/0, /*Op*/8,
        GIM_CheckComplexPattern, /*MI*/0, /*Op*/4, /*Renderer*/GIMT_Encode2(0), GIMT_Encode2(GICP_gi_buf_soffset),
        // (SItbuffer_store v4f32:{ *:[v4f32] }:$vdata, v4i32:{ *:[v4i32] }:$rsrc, i32:{ *:[i32] }:$vindex, i32:{ *:[i32] }:$voffset, (BUFSOffset:{ *:[i32] } i32:{ *:[i32] }:$soffset), (timm:{ *:[i32] }):$offset, (timm:{ *:[i32] }):$format, (timm:{ *:[i32] }):$auxiliary, (timm:{ *:[i1] }))  =>  (TBUFFER_STORE_FORMAT_XYZW_BOTHEN_exact anonymous_15034:{ *:[v4f32] }:$vdata, (REG_SEQUENCE:{ *:[i64] } VReg_64:{ *:[i32] }, VGPR_32:{ *:[i32] }:$vindex, sub0:{ *:[i32] }, VGPR_32:{ *:[i32] }:$voffset, sub1:{ *:[i32] }), SReg_128:{ *:[v4i32] }:$rsrc, SCSrc_b32:{ *:[i32] }:$soffset, (timm:{ *:[i32] }):$offset, (as_i8timm:{ *:[i8] } ?:{ *:[i32] }:$format), (extract_cpol:{ *:[i32] } ?:{ *:[i32] }:$auxiliary), (extract_swz:{ *:[i1] } ?:{ *:[i32] }:$auxiliary))
        GIR_MakeTempReg, /*TempRegID*/0, /*TypeID*/GILLT_s64,
        GIR_BuildMI, /*InsnID*/1, /*Opcode*/GIMT_Encode2(TargetOpcode::REG_SEQUENCE),
        GIR_AddTempRegister, /*InsnID*/1, /*TempRegID*/0, /*TempRegFlags*/GIMT_Encode2(RegState::Define),
        GIR_Copy, /*NewInsnID*/1, /*OldInsnID*/0, /*OpIdx*/2, // vindex
        GIR_AddImm8, /*InsnID*/1, /*SubRegIndex*/3,
        GIR_Copy, /*NewInsnID*/1, /*OldInsnID*/0, /*OpIdx*/3, // voffset
        GIR_AddImm8, /*InsnID*/1, /*SubRegIndex*/11,
        GIR_ConstrainOperandRC, /*InsnID*/1, /*Op*/0, GIMT_Encode2(AMDGPU::VReg_64RegClassID),
        GIR_ConstrainOperandRC, /*InsnID*/1, /*Op*/1, GIMT_Encode2(AMDGPU::VGPR_32RegClassID),
        GIR_ConstrainOperandRC, /*InsnID*/1, /*Op*/3, GIMT_Encode2(AMDGPU::VGPR_32RegClassID),
        GIR_BuildMI, /*InsnID*/0, /*Opcode*/GIMT_Encode2(AMDGPU::TBUFFER_STORE_FORMAT_XYZW_BOTHEN_exact),
        GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/0, // vdata
        GIR_AddSimpleTempRegister, /*InsnID*/0, /*TempRegID*/0,
        GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/1, // rsrc
        GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/0, // soffset
        GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/5, // offset
        GIR_CustomOperandRenderer, /*InsnID*/0, /*OldInsnID*/0, /*OpIdx*/6, /*OperandRenderer*/GIMT_Encode2(GICR_renderTruncTImm), // format
        GIR_CustomOperandRenderer, /*InsnID*/0, /*OldInsnID*/0, /*OpIdx*/7, /*OperandRenderer*/GIMT_Encode2(GICR_renderExtractCPol), // auxiliary
        GIR_CustomOperandRenderer, /*InsnID*/0, /*OldInsnID*/0, /*OpIdx*/7, /*OperandRenderer*/GIMT_Encode2(GICR_renderExtractSWZ), // auxiliary
        GIR_MergeMemOperands, /*InsnID*/0, /*NumInsns*/1, /*MergeInsnID's*/0,
        GIR_ConstrainSelectedInstOperands, /*InsnID*/0,
        GIR_EraseFromParent, /*InsnID*/0,
        // GIR_Coverage, 5752,
        GIR_Done,
      // Label 7429: @543935
      GIM_Try, /*On fail goto*//*Label 7430*/ GIMT_Encode4(544051), // Rule ID 5756 //
        // MIs[0] offset
        GIM_CheckIsImm, /*MI*/0, /*Op*/5,
        // MIs[0] format
        GIM_CheckIsImm, /*MI*/0, /*Op*/6,
        // MIs[0] auxiliary
        GIM_CheckIsImm, /*MI*/0, /*Op*/7,
        // MIs[0] Operand 8
        GIM_CheckIsImm, /*MI*/0, /*Op*/8,
        GIM_CheckComplexPattern, /*MI*/0, /*Op*/4, /*Renderer*/GIMT_Encode2(0), GIMT_Encode2(GICP_gi_buf_soffset),
        // (SItbuffer_store v4f32:{ *:[v4f32] }:$vdata, v4i32:{ *:[v4i32] }:$rsrc, i32:{ *:[i32] }:$vindex, i32:{ *:[i32] }:$voffset, (BUFSOffset:{ *:[i32] } i32:{ *:[i32] }:$soffset), (timm:{ *:[i32] }):$offset, (timm:{ *:[i32] }):$format, (timm:{ *:[i32] }):$auxiliary, (timm:{ *:[i1] }))  =>  (TBUFFER_STORE_FORMAT_XYZW_VBUFFER_BOTHEN_exact anonymous_15034:{ *:[v4f32] }:$vdata, (REG_SEQUENCE:{ *:[i64] } VReg_64:{ *:[i32] }, VGPR_32:{ *:[i32] }:$vindex, sub0:{ *:[i32] }, VGPR_32:{ *:[i32] }:$voffset, sub1:{ *:[i32] }), SReg_128:{ *:[v4i32] }:$rsrc, SCSrc_b32:{ *:[i32] }:$soffset, (timm:{ *:[i32] }):$offset, (as_i8timm:{ *:[i8] } ?:{ *:[i32] }:$format), (extract_cpol:{ *:[i32] } ?:{ *:[i32] }:$auxiliary), (extract_swz:{ *:[i1] } ?:{ *:[i32] }:$auxiliary))
        GIR_MakeTempReg, /*TempRegID*/0, /*TypeID*/GILLT_s64,
        GIR_BuildMI, /*InsnID*/1, /*Opcode*/GIMT_Encode2(TargetOpcode::REG_SEQUENCE),
        GIR_AddTempRegister, /*InsnID*/1, /*TempRegID*/0, /*TempRegFlags*/GIMT_Encode2(RegState::Define),
        GIR_Copy, /*NewInsnID*/1, /*OldInsnID*/0, /*OpIdx*/2, // vindex
        GIR_AddImm8, /*InsnID*/1, /*SubRegIndex*/3,
        GIR_Copy, /*NewInsnID*/1, /*OldInsnID*/0, /*OpIdx*/3, // voffset
        GIR_AddImm8, /*InsnID*/1, /*SubRegIndex*/11,
        GIR_ConstrainOperandRC, /*InsnID*/1, /*Op*/0, GIMT_Encode2(AMDGPU::VReg_64RegClassID),
        GIR_ConstrainOperandRC, /*InsnID*/1, /*Op*/1, GIMT_Encode2(AMDGPU::VGPR_32RegClassID),
        GIR_ConstrainOperandRC, /*InsnID*/1, /*Op*/3, GIMT_Encode2(AMDGPU::VGPR_32RegClassID),
        GIR_BuildMI, /*InsnID*/0, /*Opcode*/GIMT_Encode2(AMDGPU::TBUFFER_STORE_FORMAT_XYZW_VBUFFER_BOTHEN_exact),
        GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/0, // vdata
        GIR_AddSimpleTempRegister, /*InsnID*/0, /*TempRegID*/0,
        GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/1, // rsrc
        GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/0, // soffset
        GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/5, // offset
        GIR_CustomOperandRenderer, /*InsnID*/0, /*OldInsnID*/0, /*OpIdx*/6, /*OperandRenderer*/GIMT_Encode2(GICR_renderTruncTImm), // format
        GIR_CustomOperandRenderer, /*InsnID*/0, /*OldInsnID*/0, /*OpIdx*/7, /*OperandRenderer*/GIMT_Encode2(GICR_renderExtractCPol), // auxiliary
        GIR_CustomOperandRenderer, /*InsnID*/0, /*OldInsnID*/0, /*OpIdx*/7, /*OperandRenderer*/GIMT_Encode2(GICR_renderExtractSWZ), // auxiliary
        GIR_MergeMemOperands, /*InsnID*/0, /*NumInsns*/1, /*MergeInsnID's*/0,
        GIR_ConstrainSelectedInstOperands, /*InsnID*/0,
        GIR_EraseFromParent, /*InsnID*/0,
        // GIR_Coverage, 5756,
        GIR_Done,
      // Label 7430: @544051
      GIM_Reject,
    // Label 7414: @544052
    GIM_Reject,
    // Label 7362: @544053
    GIM_Reject,
    // Label 158: @544054
    GIM_SwitchType, /*MI*/0, /*Op*/0, /*[*/GIMT_Encode2(8), GIMT_Encode2(18), /*)*//*default:*//*Label 7438*/ GIMT_Encode4(549258),
    /*GILLT_s16*//*Label 7431*/ GIMT_Encode4(544105),
    /*GILLT_s32*//*Label 7432*/ GIMT_Encode4(545280), GIMT_Encode4(0),
    /*GILLT_v2s16*//*Label 7433*/ GIMT_Encode4(546455),
    /*GILLT_v2s32*//*Label 7434*/ GIMT_Encode4(547246), GIMT_Encode4(0),
    /*GILLT_v3s32*//*Label 7435*/ GIMT_Encode4(547653), GIMT_Encode4(0),
    /*GILLT_v4s16*//*Label 7436*/ GIMT_Encode4(548060),
    /*GILLT_v4s32*//*Label 7437*/ GIMT_Encode4(548851),
    // Label 7431: @544105
    GIM_Try, /*On fail goto*//*Label 7439*/ GIMT_Encode4(545279),
      GIM_CheckType, /*MI*/0, /*Op*/1, /*Type*/GILLT_v4s32,
      GIM_CheckType, /*MI*/0, /*Op*/2, /*Type*/GILLT_s32,
      GIM_CheckType, /*MI*/0, /*Op*/3, /*Type*/GILLT_s32,
      GIM_CheckType, /*MI*/0, /*Op*/4, /*Type*/GILLT_s32,
      GIM_Try, /*On fail goto*//*Label 7440*/ GIMT_Encode4(544217), // Rule ID 5757 //
        GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasUnpackedD16VMem),
        GIM_CheckConstantInt8, /*MI*/0, /*Op*/2, 0,
        GIM_CheckConstantInt8, /*MI*/0, /*Op*/3, 0,
        // MIs[0] offset
        GIM_CheckIsImm, /*MI*/0, /*Op*/5,
        // MIs[0] format
        GIM_CheckIsImm, /*MI*/0, /*Op*/6,
        // MIs[0] auxiliary
        GIM_CheckIsImm, /*MI*/0, /*Op*/7,
        // MIs[0] Operand 8
        GIM_CheckLiteralInt, /*MI*/0, /*Op*/8, GIMT_Encode8(0),
        GIM_CheckComplexPattern, /*MI*/0, /*Op*/4, /*Renderer*/GIMT_Encode2(0), GIMT_Encode2(GICP_gi_buf_soffset),
        // (SItbuffer_store_d16 f16:{ *:[f16] }:$vdata, v4i32:{ *:[v4i32] }:$rsrc, 0:{ *:[i32] }, 0:{ *:[i32] }, (BUFSOffset:{ *:[i32] } i32:{ *:[i32] }:$soffset), (timm:{ *:[i32] }):$offset, (timm:{ *:[i32] }):$format, (timm:{ *:[i32] }):$auxiliary, 0:{ *:[i1] })  =>  (TBUFFER_STORE_FORMAT_D16_X_gfx80_OFFSET_exact anonymous_15037:{ *:[f16] }:$vdata, SReg_128:{ *:[v4i32] }:$rsrc, SCSrc_b32:{ *:[i32] }:$soffset, (timm:{ *:[i32] }):$offset, (as_i8timm:{ *:[i8] } ?:{ *:[i32] }:$format), (extract_cpol:{ *:[i32] } ?:{ *:[i32] }:$auxiliary), (extract_swz:{ *:[i1] } ?:{ *:[i32] }:$auxiliary))
        GIR_BuildMI, /*InsnID*/0, /*Opcode*/GIMT_Encode2(AMDGPU::TBUFFER_STORE_FORMAT_D16_X_gfx80_OFFSET_exact),
        GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/0, // vdata
        GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/1, // rsrc
        GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/0, // soffset
        GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/5, // offset
        GIR_CustomOperandRenderer, /*InsnID*/0, /*OldInsnID*/0, /*OpIdx*/6, /*OperandRenderer*/GIMT_Encode2(GICR_renderTruncTImm), // format
        GIR_CustomOperandRenderer, /*InsnID*/0, /*OldInsnID*/0, /*OpIdx*/7, /*OperandRenderer*/GIMT_Encode2(GICR_renderExtractCPol), // auxiliary
        GIR_CustomOperandRenderer, /*InsnID*/0, /*OldInsnID*/0, /*OpIdx*/7, /*OperandRenderer*/GIMT_Encode2(GICR_renderExtractSWZ), // auxiliary
        GIR_MergeMemOperands, /*InsnID*/0, /*NumInsns*/1, /*MergeInsnID's*/0,
        GIR_ConstrainSelectedInstOperands, /*InsnID*/0,
        GIR_EraseFromParent, /*InsnID*/0,
        // GIR_Coverage, 5757,
        GIR_Done,
      // Label 7440: @544217
      GIM_Try, /*On fail goto*//*Label 7441*/ GIMT_Encode4(544308), // Rule ID 5777 //
        GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasPackedD16VMem_HasUnrestrictedSOffset),
        GIM_CheckConstantInt8, /*MI*/0, /*Op*/2, 0,
        GIM_CheckConstantInt8, /*MI*/0, /*Op*/3, 0,
        // MIs[0] offset
        GIM_CheckIsImm, /*MI*/0, /*Op*/5,
        // MIs[0] format
        GIM_CheckIsImm, /*MI*/0, /*Op*/6,
        // MIs[0] auxiliary
        GIM_CheckIsImm, /*MI*/0, /*Op*/7,
        // MIs[0] Operand 8
        GIM_CheckLiteralInt, /*MI*/0, /*Op*/8, GIMT_Encode8(0),
        GIM_CheckComplexPattern, /*MI*/0, /*Op*/4, /*Renderer*/GIMT_Encode2(0), GIMT_Encode2(GICP_gi_buf_soffset),
        // (SItbuffer_store_d16 f16:{ *:[f16] }:$vdata, v4i32:{ *:[v4i32] }:$rsrc, 0:{ *:[i32] }, 0:{ *:[i32] }, (BUFSOffset:{ *:[i32] } i32:{ *:[i32] }:$soffset), (timm:{ *:[i32] }):$offset, (timm:{ *:[i32] }):$format, (timm:{ *:[i32] }):$auxiliary, 0:{ *:[i1] })  =>  (TBUFFER_STORE_FORMAT_D16_X_OFFSET_exact anonymous_15037:{ *:[f16] }:$vdata, SReg_128:{ *:[v4i32] }:$rsrc, SCSrc_b32:{ *:[i32] }:$soffset, (timm:{ *:[i32] }):$offset, (as_i8timm:{ *:[i8] } ?:{ *:[i32] }:$format), (extract_cpol:{ *:[i32] } ?:{ *:[i32] }:$auxiliary), (extract_swz:{ *:[i1] } ?:{ *:[i32] }:$auxiliary))
        GIR_BuildMI, /*InsnID*/0, /*Opcode*/GIMT_Encode2(AMDGPU::TBUFFER_STORE_FORMAT_D16_X_OFFSET_exact),
        GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/0, // vdata
        GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/1, // rsrc
        GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/0, // soffset
        GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/5, // offset
        GIR_CustomOperandRenderer, /*InsnID*/0, /*OldInsnID*/0, /*OpIdx*/6, /*OperandRenderer*/GIMT_Encode2(GICR_renderTruncTImm), // format
        GIR_CustomOperandRenderer, /*InsnID*/0, /*OldInsnID*/0, /*OpIdx*/7, /*OperandRenderer*/GIMT_Encode2(GICR_renderExtractCPol), // auxiliary
        GIR_CustomOperandRenderer, /*InsnID*/0, /*OldInsnID*/0, /*OpIdx*/7, /*OperandRenderer*/GIMT_Encode2(GICR_renderExtractSWZ), // auxiliary
        GIR_MergeMemOperands, /*InsnID*/0, /*NumInsns*/1, /*MergeInsnID's*/0,
        GIR_ConstrainSelectedInstOperands, /*InsnID*/0,
        GIR_EraseFromParent, /*InsnID*/0,
        // GIR_Coverage, 5777,
        GIR_Done,
      // Label 7441: @544308
      GIM_Try, /*On fail goto*//*Label 7442*/ GIMT_Encode4(544399), // Rule ID 5781 //
        GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasPackedD16VMem),
        GIM_CheckConstantInt8, /*MI*/0, /*Op*/2, 0,
        GIM_CheckConstantInt8, /*MI*/0, /*Op*/3, 0,
        // MIs[0] offset
        GIM_CheckIsImm, /*MI*/0, /*Op*/5,
        // MIs[0] format
        GIM_CheckIsImm, /*MI*/0, /*Op*/6,
        // MIs[0] auxiliary
        GIM_CheckIsImm, /*MI*/0, /*Op*/7,
        // MIs[0] Operand 8
        GIM_CheckLiteralInt, /*MI*/0, /*Op*/8, GIMT_Encode8(0),
        GIM_CheckComplexPattern, /*MI*/0, /*Op*/4, /*Renderer*/GIMT_Encode2(0), GIMT_Encode2(GICP_gi_buf_soffset),
        // (SItbuffer_store_d16 f16:{ *:[f16] }:$vdata, v4i32:{ *:[v4i32] }:$rsrc, 0:{ *:[i32] }, 0:{ *:[i32] }, (BUFSOffset:{ *:[i32] } i32:{ *:[i32] }:$soffset), (timm:{ *:[i32] }):$offset, (timm:{ *:[i32] }):$format, (timm:{ *:[i32] }):$auxiliary, 0:{ *:[i1] })  =>  (TBUFFER_STORE_FORMAT_D16_X_VBUFFER_OFFSET_exact anonymous_15037:{ *:[f16] }:$vdata, SReg_128:{ *:[v4i32] }:$rsrc, SCSrc_b32:{ *:[i32] }:$soffset, (timm:{ *:[i32] }):$offset, (as_i8timm:{ *:[i8] } ?:{ *:[i32] }:$format), (extract_cpol:{ *:[i32] } ?:{ *:[i32] }:$auxiliary), (extract_swz:{ *:[i1] } ?:{ *:[i32] }:$auxiliary))
        GIR_BuildMI, /*InsnID*/0, /*Opcode*/GIMT_Encode2(AMDGPU::TBUFFER_STORE_FORMAT_D16_X_VBUFFER_OFFSET_exact),
        GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/0, // vdata
        GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/1, // rsrc
        GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/0, // soffset
        GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/5, // offset
        GIR_CustomOperandRenderer, /*InsnID*/0, /*OldInsnID*/0, /*OpIdx*/6, /*OperandRenderer*/GIMT_Encode2(GICR_renderTruncTImm), // format
        GIR_CustomOperandRenderer, /*InsnID*/0, /*OldInsnID*/0, /*OpIdx*/7, /*OperandRenderer*/GIMT_Encode2(GICR_renderExtractCPol), // auxiliary
        GIR_CustomOperandRenderer, /*InsnID*/0, /*OldInsnID*/0, /*OpIdx*/7, /*OperandRenderer*/GIMT_Encode2(GICR_renderExtractSWZ), // auxiliary
        GIR_MergeMemOperands, /*InsnID*/0, /*NumInsns*/1, /*MergeInsnID's*/0,
        GIR_ConstrainSelectedInstOperands, /*InsnID*/0,
        GIR_EraseFromParent, /*InsnID*/0,
        // GIR_Coverage, 5781,
        GIR_Done,
      // Label 7442: @544399
      GIM_Try, /*On fail goto*//*Label 7443*/ GIMT_Encode4(544490), // Rule ID 5759 //
        GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasUnpackedD16VMem),
        GIM_CheckConstantInt8, /*MI*/0, /*Op*/2, 0,
        // MIs[0] offset
        GIM_CheckIsImm, /*MI*/0, /*Op*/5,
        // MIs[0] format
        GIM_CheckIsImm, /*MI*/0, /*Op*/6,
        // MIs[0] auxiliary
        GIM_CheckIsImm, /*MI*/0, /*Op*/7,
        // MIs[0] Operand 8
        GIM_CheckLiteralInt, /*MI*/0, /*Op*/8, GIMT_Encode8(0),
        GIM_CheckComplexPattern, /*MI*/0, /*Op*/4, /*Renderer*/GIMT_Encode2(0), GIMT_Encode2(GICP_gi_buf_soffset),
        // (SItbuffer_store_d16 f16:{ *:[f16] }:$vdata, v4i32:{ *:[v4i32] }:$rsrc, 0:{ *:[i32] }, i32:{ *:[i32] }:$voffset, (BUFSOffset:{ *:[i32] } i32:{ *:[i32] }:$soffset), (timm:{ *:[i32] }):$offset, (timm:{ *:[i32] }):$format, (timm:{ *:[i32] }):$auxiliary, 0:{ *:[i1] })  =>  (TBUFFER_STORE_FORMAT_D16_X_gfx80_OFFEN_exact anonymous_15037:{ *:[f16] }:$vdata, VGPR_32:{ *:[i32] }:$voffset, SReg_128:{ *:[v4i32] }:$rsrc, SCSrc_b32:{ *:[i32] }:$soffset, (timm:{ *:[i32] }):$offset, (as_i8timm:{ *:[i8] } ?:{ *:[i32] }:$format), (extract_cpol:{ *:[i32] } ?:{ *:[i32] }:$auxiliary), (extract_swz:{ *:[i1] } ?:{ *:[i32] }:$auxiliary))
        GIR_BuildMI, /*InsnID*/0, /*Opcode*/GIMT_Encode2(AMDGPU::TBUFFER_STORE_FORMAT_D16_X_gfx80_OFFEN_exact),
        GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/0, // vdata
        GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/3, // voffset
        GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/1, // rsrc
        GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/0, // soffset
        GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/5, // offset
        GIR_CustomOperandRenderer, /*InsnID*/0, /*OldInsnID*/0, /*OpIdx*/6, /*OperandRenderer*/GIMT_Encode2(GICR_renderTruncTImm), // format
        GIR_CustomOperandRenderer, /*InsnID*/0, /*OldInsnID*/0, /*OpIdx*/7, /*OperandRenderer*/GIMT_Encode2(GICR_renderExtractCPol), // auxiliary
        GIR_CustomOperandRenderer, /*InsnID*/0, /*OldInsnID*/0, /*OpIdx*/7, /*OperandRenderer*/GIMT_Encode2(GICR_renderExtractSWZ), // auxiliary
        GIR_MergeMemOperands, /*InsnID*/0, /*NumInsns*/1, /*MergeInsnID's*/0,
        GIR_ConstrainSelectedInstOperands, /*InsnID*/0,
        GIR_EraseFromParent, /*InsnID*/0,
        // GIR_Coverage, 5759,
        GIR_Done,
      // Label 7443: @544490
      GIM_Try, /*On fail goto*//*Label 7444*/ GIMT_Encode4(544581), // Rule ID 5779 //
        GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasPackedD16VMem_HasUnrestrictedSOffset),
        GIM_CheckConstantInt8, /*MI*/0, /*Op*/2, 0,
        // MIs[0] offset
        GIM_CheckIsImm, /*MI*/0, /*Op*/5,
        // MIs[0] format
        GIM_CheckIsImm, /*MI*/0, /*Op*/6,
        // MIs[0] auxiliary
        GIM_CheckIsImm, /*MI*/0, /*Op*/7,
        // MIs[0] Operand 8
        GIM_CheckLiteralInt, /*MI*/0, /*Op*/8, GIMT_Encode8(0),
        GIM_CheckComplexPattern, /*MI*/0, /*Op*/4, /*Renderer*/GIMT_Encode2(0), GIMT_Encode2(GICP_gi_buf_soffset),
        // (SItbuffer_store_d16 f16:{ *:[f16] }:$vdata, v4i32:{ *:[v4i32] }:$rsrc, 0:{ *:[i32] }, i32:{ *:[i32] }:$voffset, (BUFSOffset:{ *:[i32] } i32:{ *:[i32] }:$soffset), (timm:{ *:[i32] }):$offset, (timm:{ *:[i32] }):$format, (timm:{ *:[i32] }):$auxiliary, 0:{ *:[i1] })  =>  (TBUFFER_STORE_FORMAT_D16_X_OFFEN_exact anonymous_15037:{ *:[f16] }:$vdata, VGPR_32:{ *:[i32] }:$voffset, SReg_128:{ *:[v4i32] }:$rsrc, SCSrc_b32:{ *:[i32] }:$soffset, (timm:{ *:[i32] }):$offset, (as_i8timm:{ *:[i8] } ?:{ *:[i32] }:$format), (extract_cpol:{ *:[i32] } ?:{ *:[i32] }:$auxiliary), (extract_swz:{ *:[i1] } ?:{ *:[i32] }:$auxiliary))
        GIR_BuildMI, /*InsnID*/0, /*Opcode*/GIMT_Encode2(AMDGPU::TBUFFER_STORE_FORMAT_D16_X_OFFEN_exact),
        GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/0, // vdata
        GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/3, // voffset
        GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/1, // rsrc
        GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/0, // soffset
        GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/5, // offset
        GIR_CustomOperandRenderer, /*InsnID*/0, /*OldInsnID*/0, /*OpIdx*/6, /*OperandRenderer*/GIMT_Encode2(GICR_renderTruncTImm), // format
        GIR_CustomOperandRenderer, /*InsnID*/0, /*OldInsnID*/0, /*OpIdx*/7, /*OperandRenderer*/GIMT_Encode2(GICR_renderExtractCPol), // auxiliary
        GIR_CustomOperandRenderer, /*InsnID*/0, /*OldInsnID*/0, /*OpIdx*/7, /*OperandRenderer*/GIMT_Encode2(GICR_renderExtractSWZ), // auxiliary
        GIR_MergeMemOperands, /*InsnID*/0, /*NumInsns*/1, /*MergeInsnID's*/0,
        GIR_ConstrainSelectedInstOperands, /*InsnID*/0,
        GIR_EraseFromParent, /*InsnID*/0,
        // GIR_Coverage, 5779,
        GIR_Done,
      // Label 7444: @544581
      GIM_Try, /*On fail goto*//*Label 7445*/ GIMT_Encode4(544672), // Rule ID 5783 //
        GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasPackedD16VMem),
        GIM_CheckConstantInt8, /*MI*/0, /*Op*/2, 0,
        // MIs[0] offset
        GIM_CheckIsImm, /*MI*/0, /*Op*/5,
        // MIs[0] format
        GIM_CheckIsImm, /*MI*/0, /*Op*/6,
        // MIs[0] auxiliary
        GIM_CheckIsImm, /*MI*/0, /*Op*/7,
        // MIs[0] Operand 8
        GIM_CheckLiteralInt, /*MI*/0, /*Op*/8, GIMT_Encode8(0),
        GIM_CheckComplexPattern, /*MI*/0, /*Op*/4, /*Renderer*/GIMT_Encode2(0), GIMT_Encode2(GICP_gi_buf_soffset),
        // (SItbuffer_store_d16 f16:{ *:[f16] }:$vdata, v4i32:{ *:[v4i32] }:$rsrc, 0:{ *:[i32] }, i32:{ *:[i32] }:$voffset, (BUFSOffset:{ *:[i32] } i32:{ *:[i32] }:$soffset), (timm:{ *:[i32] }):$offset, (timm:{ *:[i32] }):$format, (timm:{ *:[i32] }):$auxiliary, 0:{ *:[i1] })  =>  (TBUFFER_STORE_FORMAT_D16_X_VBUFFER_OFFEN_exact anonymous_15037:{ *:[f16] }:$vdata, VGPR_32:{ *:[i32] }:$voffset, SReg_128:{ *:[v4i32] }:$rsrc, SCSrc_b32:{ *:[i32] }:$soffset, (timm:{ *:[i32] }):$offset, (as_i8timm:{ *:[i8] } ?:{ *:[i32] }:$format), (extract_cpol:{ *:[i32] } ?:{ *:[i32] }:$auxiliary), (extract_swz:{ *:[i1] } ?:{ *:[i32] }:$auxiliary))
        GIR_BuildMI, /*InsnID*/0, /*Opcode*/GIMT_Encode2(AMDGPU::TBUFFER_STORE_FORMAT_D16_X_VBUFFER_OFFEN_exact),
        GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/0, // vdata
        GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/3, // voffset
        GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/1, // rsrc
        GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/0, // soffset
        GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/5, // offset
        GIR_CustomOperandRenderer, /*InsnID*/0, /*OldInsnID*/0, /*OpIdx*/6, /*OperandRenderer*/GIMT_Encode2(GICR_renderTruncTImm), // format
        GIR_CustomOperandRenderer, /*InsnID*/0, /*OldInsnID*/0, /*OpIdx*/7, /*OperandRenderer*/GIMT_Encode2(GICR_renderExtractCPol), // auxiliary
        GIR_CustomOperandRenderer, /*InsnID*/0, /*OldInsnID*/0, /*OpIdx*/7, /*OperandRenderer*/GIMT_Encode2(GICR_renderExtractSWZ), // auxiliary
        GIR_MergeMemOperands, /*InsnID*/0, /*NumInsns*/1, /*MergeInsnID's*/0,
        GIR_ConstrainSelectedInstOperands, /*InsnID*/0,
        GIR_EraseFromParent, /*InsnID*/0,
        // GIR_Coverage, 5783,
        GIR_Done,
      // Label 7445: @544672
      GIM_Try, /*On fail goto*//*Label 7446*/ GIMT_Encode4(544755), // Rule ID 5758 //
        GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasUnpackedD16VMem),
        GIM_CheckConstantInt8, /*MI*/0, /*Op*/3, 0,
        // MIs[0] offset
        GIM_CheckIsImm, /*MI*/0, /*Op*/5,
        // MIs[0] format
        GIM_CheckIsImm, /*MI*/0, /*Op*/6,
        // MIs[0] auxiliary
        GIM_CheckIsImm, /*MI*/0, /*Op*/7,
        // MIs[0] Operand 8
        GIM_CheckIsImm, /*MI*/0, /*Op*/8,
        GIM_CheckComplexPattern, /*MI*/0, /*Op*/4, /*Renderer*/GIMT_Encode2(0), GIMT_Encode2(GICP_gi_buf_soffset),
        // (SItbuffer_store_d16 f16:{ *:[f16] }:$vdata, v4i32:{ *:[v4i32] }:$rsrc, i32:{ *:[i32] }:$vindex, 0:{ *:[i32] }, (BUFSOffset:{ *:[i32] } i32:{ *:[i32] }:$soffset), (timm:{ *:[i32] }):$offset, (timm:{ *:[i32] }):$format, (timm:{ *:[i32] }):$auxiliary, (timm:{ *:[i1] }))  =>  (TBUFFER_STORE_FORMAT_D16_X_gfx80_IDXEN_exact anonymous_15037:{ *:[f16] }:$vdata, VGPR_32:{ *:[i32] }:$vindex, SReg_128:{ *:[v4i32] }:$rsrc, SCSrc_b32:{ *:[i32] }:$soffset, (timm:{ *:[i32] }):$offset, (as_i8timm:{ *:[i8] } ?:{ *:[i32] }:$format), (extract_cpol:{ *:[i32] } ?:{ *:[i32] }:$auxiliary), (extract_swz:{ *:[i1] } ?:{ *:[i32] }:$auxiliary))
        GIR_BuildMI, /*InsnID*/0, /*Opcode*/GIMT_Encode2(AMDGPU::TBUFFER_STORE_FORMAT_D16_X_gfx80_IDXEN_exact),
        GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/0, // vdata
        GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/2, // vindex
        GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/1, // rsrc
        GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/0, // soffset
        GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/5, // offset
        GIR_CustomOperandRenderer, /*InsnID*/0, /*OldInsnID*/0, /*OpIdx*/6, /*OperandRenderer*/GIMT_Encode2(GICR_renderTruncTImm), // format
        GIR_CustomOperandRenderer, /*InsnID*/0, /*OldInsnID*/0, /*OpIdx*/7, /*OperandRenderer*/GIMT_Encode2(GICR_renderExtractCPol), // auxiliary
        GIR_CustomOperandRenderer, /*InsnID*/0, /*OldInsnID*/0, /*OpIdx*/7, /*OperandRenderer*/GIMT_Encode2(GICR_renderExtractSWZ), // auxiliary
        GIR_MergeMemOperands, /*InsnID*/0, /*NumInsns*/1, /*MergeInsnID's*/0,
        GIR_ConstrainSelectedInstOperands, /*InsnID*/0,
        GIR_EraseFromParent, /*InsnID*/0,
        // GIR_Coverage, 5758,
        GIR_Done,
      // Label 7446: @544755
      GIM_Try, /*On fail goto*//*Label 7447*/ GIMT_Encode4(544838), // Rule ID 5778 //
        GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasPackedD16VMem_HasUnrestrictedSOffset),
        GIM_CheckConstantInt8, /*MI*/0, /*Op*/3, 0,
        // MIs[0] offset
        GIM_CheckIsImm, /*MI*/0, /*Op*/5,
        // MIs[0] format
        GIM_CheckIsImm, /*MI*/0, /*Op*/6,
        // MIs[0] auxiliary
        GIM_CheckIsImm, /*MI*/0, /*Op*/7,
        // MIs[0] Operand 8
        GIM_CheckIsImm, /*MI*/0, /*Op*/8,
        GIM_CheckComplexPattern, /*MI*/0, /*Op*/4, /*Renderer*/GIMT_Encode2(0), GIMT_Encode2(GICP_gi_buf_soffset),
        // (SItbuffer_store_d16 f16:{ *:[f16] }:$vdata, v4i32:{ *:[v4i32] }:$rsrc, i32:{ *:[i32] }:$vindex, 0:{ *:[i32] }, (BUFSOffset:{ *:[i32] } i32:{ *:[i32] }:$soffset), (timm:{ *:[i32] }):$offset, (timm:{ *:[i32] }):$format, (timm:{ *:[i32] }):$auxiliary, (timm:{ *:[i1] }))  =>  (TBUFFER_STORE_FORMAT_D16_X_IDXEN_exact anonymous_15037:{ *:[f16] }:$vdata, VGPR_32:{ *:[i32] }:$vindex, SReg_128:{ *:[v4i32] }:$rsrc, SCSrc_b32:{ *:[i32] }:$soffset, (timm:{ *:[i32] }):$offset, (as_i8timm:{ *:[i8] } ?:{ *:[i32] }:$format), (extract_cpol:{ *:[i32] } ?:{ *:[i32] }:$auxiliary), (extract_swz:{ *:[i1] } ?:{ *:[i32] }:$auxiliary))
        GIR_BuildMI, /*InsnID*/0, /*Opcode*/GIMT_Encode2(AMDGPU::TBUFFER_STORE_FORMAT_D16_X_IDXEN_exact),
        GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/0, // vdata
        GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/2, // vindex
        GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/1, // rsrc
        GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/0, // soffset
        GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/5, // offset
        GIR_CustomOperandRenderer, /*InsnID*/0, /*OldInsnID*/0, /*OpIdx*/6, /*OperandRenderer*/GIMT_Encode2(GICR_renderTruncTImm), // format
        GIR_CustomOperandRenderer, /*InsnID*/0, /*OldInsnID*/0, /*OpIdx*/7, /*OperandRenderer*/GIMT_Encode2(GICR_renderExtractCPol), // auxiliary
        GIR_CustomOperandRenderer, /*InsnID*/0, /*OldInsnID*/0, /*OpIdx*/7, /*OperandRenderer*/GIMT_Encode2(GICR_renderExtractSWZ), // auxiliary
        GIR_MergeMemOperands, /*InsnID*/0, /*NumInsns*/1, /*MergeInsnID's*/0,
        GIR_ConstrainSelectedInstOperands, /*InsnID*/0,
        GIR_EraseFromParent, /*InsnID*/0,
        // GIR_Coverage, 5778,
        GIR_Done,
      // Label 7447: @544838
      GIM_Try, /*On fail goto*//*Label 7448*/ GIMT_Encode4(544921), // Rule ID 5782 //
        GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasPackedD16VMem),
        GIM_CheckConstantInt8, /*MI*/0, /*Op*/3, 0,
        // MIs[0] offset
        GIM_CheckIsImm, /*MI*/0, /*Op*/5,
        // MIs[0] format
        GIM_CheckIsImm, /*MI*/0, /*Op*/6,
        // MIs[0] auxiliary
        GIM_CheckIsImm, /*MI*/0, /*Op*/7,
        // MIs[0] Operand 8
        GIM_CheckIsImm, /*MI*/0, /*Op*/8,
        GIM_CheckComplexPattern, /*MI*/0, /*Op*/4, /*Renderer*/GIMT_Encode2(0), GIMT_Encode2(GICP_gi_buf_soffset),
        // (SItbuffer_store_d16 f16:{ *:[f16] }:$vdata, v4i32:{ *:[v4i32] }:$rsrc, i32:{ *:[i32] }:$vindex, 0:{ *:[i32] }, (BUFSOffset:{ *:[i32] } i32:{ *:[i32] }:$soffset), (timm:{ *:[i32] }):$offset, (timm:{ *:[i32] }):$format, (timm:{ *:[i32] }):$auxiliary, (timm:{ *:[i1] }))  =>  (TBUFFER_STORE_FORMAT_D16_X_VBUFFER_IDXEN_exact anonymous_15037:{ *:[f16] }:$vdata, VGPR_32:{ *:[i32] }:$vindex, SReg_128:{ *:[v4i32] }:$rsrc, SCSrc_b32:{ *:[i32] }:$soffset, (timm:{ *:[i32] }):$offset, (as_i8timm:{ *:[i8] } ?:{ *:[i32] }:$format), (extract_cpol:{ *:[i32] } ?:{ *:[i32] }:$auxiliary), (extract_swz:{ *:[i1] } ?:{ *:[i32] }:$auxiliary))
        GIR_BuildMI, /*InsnID*/0, /*Opcode*/GIMT_Encode2(AMDGPU::TBUFFER_STORE_FORMAT_D16_X_VBUFFER_IDXEN_exact),
        GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/0, // vdata
        GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/2, // vindex
        GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/1, // rsrc
        GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/0, // soffset
        GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/5, // offset
        GIR_CustomOperandRenderer, /*InsnID*/0, /*OldInsnID*/0, /*OpIdx*/6, /*OperandRenderer*/GIMT_Encode2(GICR_renderTruncTImm), // format
        GIR_CustomOperandRenderer, /*InsnID*/0, /*OldInsnID*/0, /*OpIdx*/7, /*OperandRenderer*/GIMT_Encode2(GICR_renderExtractCPol), // auxiliary
        GIR_CustomOperandRenderer, /*InsnID*/0, /*OldInsnID*/0, /*OpIdx*/7, /*OperandRenderer*/GIMT_Encode2(GICR_renderExtractSWZ), // auxiliary
        GIR_MergeMemOperands, /*InsnID*/0, /*NumInsns*/1, /*MergeInsnID's*/0,
        GIR_ConstrainSelectedInstOperands, /*InsnID*/0,
        GIR_EraseFromParent, /*InsnID*/0,
        // GIR_Coverage, 5782,
        GIR_Done,
      // Label 7448: @544921
      GIM_Try, /*On fail goto*//*Label 7449*/ GIMT_Encode4(545040), // Rule ID 5760 //
        GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasUnpackedD16VMem),
        // MIs[0] offset
        GIM_CheckIsImm, /*MI*/0, /*Op*/5,
        // MIs[0] format
        GIM_CheckIsImm, /*MI*/0, /*Op*/6,
        // MIs[0] auxiliary
        GIM_CheckIsImm, /*MI*/0, /*Op*/7,
        // MIs[0] Operand 8
        GIM_CheckIsImm, /*MI*/0, /*Op*/8,
        GIM_CheckComplexPattern, /*MI*/0, /*Op*/4, /*Renderer*/GIMT_Encode2(0), GIMT_Encode2(GICP_gi_buf_soffset),
        // (SItbuffer_store_d16 f16:{ *:[f16] }:$vdata, v4i32:{ *:[v4i32] }:$rsrc, i32:{ *:[i32] }:$vindex, i32:{ *:[i32] }:$voffset, (BUFSOffset:{ *:[i32] } i32:{ *:[i32] }:$soffset), (timm:{ *:[i32] }):$offset, (timm:{ *:[i32] }):$format, (timm:{ *:[i32] }):$auxiliary, (timm:{ *:[i1] }))  =>  (TBUFFER_STORE_FORMAT_D16_X_gfx80_BOTHEN_exact anonymous_15037:{ *:[f16] }:$vdata, (REG_SEQUENCE:{ *:[i64] } VReg_64:{ *:[i32] }, VGPR_32:{ *:[i32] }:$vindex, sub0:{ *:[i32] }, VGPR_32:{ *:[i32] }:$voffset, sub1:{ *:[i32] }), SReg_128:{ *:[v4i32] }:$rsrc, SCSrc_b32:{ *:[i32] }:$soffset, (timm:{ *:[i32] }):$offset, (as_i8timm:{ *:[i8] } ?:{ *:[i32] }:$format), (extract_cpol:{ *:[i32] } ?:{ *:[i32] }:$auxiliary), (extract_swz:{ *:[i1] } ?:{ *:[i32] }:$auxiliary))
        GIR_MakeTempReg, /*TempRegID*/0, /*TypeID*/GILLT_s64,
        GIR_BuildMI, /*InsnID*/1, /*Opcode*/GIMT_Encode2(TargetOpcode::REG_SEQUENCE),
        GIR_AddTempRegister, /*InsnID*/1, /*TempRegID*/0, /*TempRegFlags*/GIMT_Encode2(RegState::Define),
        GIR_Copy, /*NewInsnID*/1, /*OldInsnID*/0, /*OpIdx*/2, // vindex
        GIR_AddImm8, /*InsnID*/1, /*SubRegIndex*/3,
        GIR_Copy, /*NewInsnID*/1, /*OldInsnID*/0, /*OpIdx*/3, // voffset
        GIR_AddImm8, /*InsnID*/1, /*SubRegIndex*/11,
        GIR_ConstrainOperandRC, /*InsnID*/1, /*Op*/0, GIMT_Encode2(AMDGPU::VReg_64RegClassID),
        GIR_ConstrainOperandRC, /*InsnID*/1, /*Op*/1, GIMT_Encode2(AMDGPU::VGPR_32RegClassID),
        GIR_ConstrainOperandRC, /*InsnID*/1, /*Op*/3, GIMT_Encode2(AMDGPU::VGPR_32RegClassID),
        GIR_BuildMI, /*InsnID*/0, /*Opcode*/GIMT_Encode2(AMDGPU::TBUFFER_STORE_FORMAT_D16_X_gfx80_BOTHEN_exact),
        GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/0, // vdata
        GIR_AddSimpleTempRegister, /*InsnID*/0, /*TempRegID*/0,
        GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/1, // rsrc
        GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/0, // soffset
        GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/5, // offset
        GIR_CustomOperandRenderer, /*InsnID*/0, /*OldInsnID*/0, /*OpIdx*/6, /*OperandRenderer*/GIMT_Encode2(GICR_renderTruncTImm), // format
        GIR_CustomOperandRenderer, /*InsnID*/0, /*OldInsnID*/0, /*OpIdx*/7, /*OperandRenderer*/GIMT_Encode2(GICR_renderExtractCPol), // auxiliary
        GIR_CustomOperandRenderer, /*InsnID*/0, /*OldInsnID*/0, /*OpIdx*/7, /*OperandRenderer*/GIMT_Encode2(GICR_renderExtractSWZ), // auxiliary
        GIR_MergeMemOperands, /*InsnID*/0, /*NumInsns*/1, /*MergeInsnID's*/0,
        GIR_ConstrainSelectedInstOperands, /*InsnID*/0,
        GIR_EraseFromParent, /*InsnID*/0,
        // GIR_Coverage, 5760,
        GIR_Done,
      // Label 7449: @545040
      GIM_Try, /*On fail goto*//*Label 7450*/ GIMT_Encode4(545159), // Rule ID 5780 //
        GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasPackedD16VMem_HasUnrestrictedSOffset),
        // MIs[0] offset
        GIM_CheckIsImm, /*MI*/0, /*Op*/5,
        // MIs[0] format
        GIM_CheckIsImm, /*MI*/0, /*Op*/6,
        // MIs[0] auxiliary
        GIM_CheckIsImm, /*MI*/0, /*Op*/7,
        // MIs[0] Operand 8
        GIM_CheckIsImm, /*MI*/0, /*Op*/8,
        GIM_CheckComplexPattern, /*MI*/0, /*Op*/4, /*Renderer*/GIMT_Encode2(0), GIMT_Encode2(GICP_gi_buf_soffset),
        // (SItbuffer_store_d16 f16:{ *:[f16] }:$vdata, v4i32:{ *:[v4i32] }:$rsrc, i32:{ *:[i32] }:$vindex, i32:{ *:[i32] }:$voffset, (BUFSOffset:{ *:[i32] } i32:{ *:[i32] }:$soffset), (timm:{ *:[i32] }):$offset, (timm:{ *:[i32] }):$format, (timm:{ *:[i32] }):$auxiliary, (timm:{ *:[i1] }))  =>  (TBUFFER_STORE_FORMAT_D16_X_BOTHEN_exact anonymous_15037:{ *:[f16] }:$vdata, (REG_SEQUENCE:{ *:[i64] } VReg_64:{ *:[i32] }, VGPR_32:{ *:[i32] }:$vindex, sub0:{ *:[i32] }, VGPR_32:{ *:[i32] }:$voffset, sub1:{ *:[i32] }), SReg_128:{ *:[v4i32] }:$rsrc, SCSrc_b32:{ *:[i32] }:$soffset, (timm:{ *:[i32] }):$offset, (as_i8timm:{ *:[i8] } ?:{ *:[i32] }:$format), (extract_cpol:{ *:[i32] } ?:{ *:[i32] }:$auxiliary), (extract_swz:{ *:[i1] } ?:{ *:[i32] }:$auxiliary))
        GIR_MakeTempReg, /*TempRegID*/0, /*TypeID*/GILLT_s64,
        GIR_BuildMI, /*InsnID*/1, /*Opcode*/GIMT_Encode2(TargetOpcode::REG_SEQUENCE),
        GIR_AddTempRegister, /*InsnID*/1, /*TempRegID*/0, /*TempRegFlags*/GIMT_Encode2(RegState::Define),
        GIR_Copy, /*NewInsnID*/1, /*OldInsnID*/0, /*OpIdx*/2, // vindex
        GIR_AddImm8, /*InsnID*/1, /*SubRegIndex*/3,
        GIR_Copy, /*NewInsnID*/1, /*OldInsnID*/0, /*OpIdx*/3, // voffset
        GIR_AddImm8, /*InsnID*/1, /*SubRegIndex*/11,
        GIR_ConstrainOperandRC, /*InsnID*/1, /*Op*/0, GIMT_Encode2(AMDGPU::VReg_64RegClassID),
        GIR_ConstrainOperandRC, /*InsnID*/1, /*Op*/1, GIMT_Encode2(AMDGPU::VGPR_32RegClassID),
        GIR_ConstrainOperandRC, /*InsnID*/1, /*Op*/3, GIMT_Encode2(AMDGPU::VGPR_32RegClassID),
        GIR_BuildMI, /*InsnID*/0, /*Opcode*/GIMT_Encode2(AMDGPU::TBUFFER_STORE_FORMAT_D16_X_BOTHEN_exact),
        GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/0, // vdata
        GIR_AddSimpleTempRegister, /*InsnID*/0, /*TempRegID*/0,
        GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/1, // rsrc
        GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/0, // soffset
        GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/5, // offset
        GIR_CustomOperandRenderer, /*InsnID*/0, /*OldInsnID*/0, /*OpIdx*/6, /*OperandRenderer*/GIMT_Encode2(GICR_renderTruncTImm), // format
        GIR_CustomOperandRenderer, /*InsnID*/0, /*OldInsnID*/0, /*OpIdx*/7, /*OperandRenderer*/GIMT_Encode2(GICR_renderExtractCPol), // auxiliary
        GIR_CustomOperandRenderer, /*InsnID*/0, /*OldInsnID*/0, /*OpIdx*/7, /*OperandRenderer*/GIMT_Encode2(GICR_renderExtractSWZ), // auxiliary
        GIR_MergeMemOperands, /*InsnID*/0, /*NumInsns*/1, /*MergeInsnID's*/0,
        GIR_ConstrainSelectedInstOperands, /*InsnID*/0,
        GIR_EraseFromParent, /*InsnID*/0,
        // GIR_Coverage, 5780,
        GIR_Done,
      // Label 7450: @545159
      GIM_Try, /*On fail goto*//*Label 7451*/ GIMT_Encode4(545278), // Rule ID 5784 //
        GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasPackedD16VMem),
        // MIs[0] offset
        GIM_CheckIsImm, /*MI*/0, /*Op*/5,
        // MIs[0] format
        GIM_CheckIsImm, /*MI*/0, /*Op*/6,
        // MIs[0] auxiliary
        GIM_CheckIsImm, /*MI*/0, /*Op*/7,
        // MIs[0] Operand 8
        GIM_CheckIsImm, /*MI*/0, /*Op*/8,
        GIM_CheckComplexPattern, /*MI*/0, /*Op*/4, /*Renderer*/GIMT_Encode2(0), GIMT_Encode2(GICP_gi_buf_soffset),
        // (SItbuffer_store_d16 f16:{ *:[f16] }:$vdata, v4i32:{ *:[v4i32] }:$rsrc, i32:{ *:[i32] }:$vindex, i32:{ *:[i32] }:$voffset, (BUFSOffset:{ *:[i32] } i32:{ *:[i32] }:$soffset), (timm:{ *:[i32] }):$offset, (timm:{ *:[i32] }):$format, (timm:{ *:[i32] }):$auxiliary, (timm:{ *:[i1] }))  =>  (TBUFFER_STORE_FORMAT_D16_X_VBUFFER_BOTHEN_exact anonymous_15037:{ *:[f16] }:$vdata, (REG_SEQUENCE:{ *:[i64] } VReg_64:{ *:[i32] }, VGPR_32:{ *:[i32] }:$vindex, sub0:{ *:[i32] }, VGPR_32:{ *:[i32] }:$voffset, sub1:{ *:[i32] }), SReg_128:{ *:[v4i32] }:$rsrc, SCSrc_b32:{ *:[i32] }:$soffset, (timm:{ *:[i32] }):$offset, (as_i8timm:{ *:[i8] } ?:{ *:[i32] }:$format), (extract_cpol:{ *:[i32] } ?:{ *:[i32] }:$auxiliary), (extract_swz:{ *:[i1] } ?:{ *:[i32] }:$auxiliary))
        GIR_MakeTempReg, /*TempRegID*/0, /*TypeID*/GILLT_s64,
        GIR_BuildMI, /*InsnID*/1, /*Opcode*/GIMT_Encode2(TargetOpcode::REG_SEQUENCE),
        GIR_AddTempRegister, /*InsnID*/1, /*TempRegID*/0, /*TempRegFlags*/GIMT_Encode2(RegState::Define),
        GIR_Copy, /*NewInsnID*/1, /*OldInsnID*/0, /*OpIdx*/2, // vindex
        GIR_AddImm8, /*InsnID*/1, /*SubRegIndex*/3,
        GIR_Copy, /*NewInsnID*/1, /*OldInsnID*/0, /*OpIdx*/3, // voffset
        GIR_AddImm8, /*InsnID*/1, /*SubRegIndex*/11,
        GIR_ConstrainOperandRC, /*InsnID*/1, /*Op*/0, GIMT_Encode2(AMDGPU::VReg_64RegClassID),
        GIR_ConstrainOperandRC, /*InsnID*/1, /*Op*/1, GIMT_Encode2(AMDGPU::VGPR_32RegClassID),
        GIR_ConstrainOperandRC, /*InsnID*/1, /*Op*/3, GIMT_Encode2(AMDGPU::VGPR_32RegClassID),
        GIR_BuildMI, /*InsnID*/0, /*Opcode*/GIMT_Encode2(AMDGPU::TBUFFER_STORE_FORMAT_D16_X_VBUFFER_BOTHEN_exact),
        GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/0, // vdata
        GIR_AddSimpleTempRegister, /*InsnID*/0, /*TempRegID*/0,
        GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/1, // rsrc
        GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/0, // soffset
        GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/5, // offset
        GIR_CustomOperandRenderer, /*InsnID*/0, /*OldInsnID*/0, /*OpIdx*/6, /*OperandRenderer*/GIMT_Encode2(GICR_renderTruncTImm), // format
        GIR_CustomOperandRenderer, /*InsnID*/0, /*OldInsnID*/0, /*OpIdx*/7, /*OperandRenderer*/GIMT_Encode2(GICR_renderExtractCPol), // auxiliary
        GIR_CustomOperandRenderer, /*InsnID*/0, /*OldInsnID*/0, /*OpIdx*/7, /*OperandRenderer*/GIMT_Encode2(GICR_renderExtractSWZ), // auxiliary
        GIR_MergeMemOperands, /*InsnID*/0, /*NumInsns*/1, /*MergeInsnID's*/0,
        GIR_ConstrainSelectedInstOperands, /*InsnID*/0,
        GIR_EraseFromParent, /*InsnID*/0,
        // GIR_Coverage, 5784,
        GIR_Done,
      // Label 7451: @545278
      GIM_Reject,
    // Label 7439: @545279
    GIM_Reject,
    // Label 7432: @545280
    GIM_Try, /*On fail goto*//*Label 7452*/ GIMT_Encode4(546454),
      GIM_CheckType, /*MI*/0, /*Op*/1, /*Type*/GILLT_v4s32,
      GIM_CheckType, /*MI*/0, /*Op*/2, /*Type*/GILLT_s32,
      GIM_CheckType, /*MI*/0, /*Op*/3, /*Type*/GILLT_s32,
      GIM_CheckType, /*MI*/0, /*Op*/4, /*Type*/GILLT_s32,
      GIM_Try, /*On fail goto*//*Label 7453*/ GIMT_Encode4(545392), // Rule ID 5761 //
        GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasUnpackedD16VMem),
        GIM_CheckConstantInt8, /*MI*/0, /*Op*/2, 0,
        GIM_CheckConstantInt8, /*MI*/0, /*Op*/3, 0,
        // MIs[0] offset
        GIM_CheckIsImm, /*MI*/0, /*Op*/5,
        // MIs[0] format
        GIM_CheckIsImm, /*MI*/0, /*Op*/6,
        // MIs[0] auxiliary
        GIM_CheckIsImm, /*MI*/0, /*Op*/7,
        // MIs[0] Operand 8
        GIM_CheckLiteralInt, /*MI*/0, /*Op*/8, GIMT_Encode8(0),
        GIM_CheckComplexPattern, /*MI*/0, /*Op*/4, /*Renderer*/GIMT_Encode2(0), GIMT_Encode2(GICP_gi_buf_soffset),
        // (SItbuffer_store_d16 i32:{ *:[i32] }:$vdata, v4i32:{ *:[v4i32] }:$rsrc, 0:{ *:[i32] }, 0:{ *:[i32] }, (BUFSOffset:{ *:[i32] } i32:{ *:[i32] }:$soffset), (timm:{ *:[i32] }):$offset, (timm:{ *:[i32] }):$format, (timm:{ *:[i32] }):$auxiliary, 0:{ *:[i1] })  =>  (TBUFFER_STORE_FORMAT_D16_X_gfx80_OFFSET_exact anonymous_15037:{ *:[i32] }:$vdata, SReg_128:{ *:[v4i32] }:$rsrc, SCSrc_b32:{ *:[i32] }:$soffset, (timm:{ *:[i32] }):$offset, (as_i8timm:{ *:[i8] } ?:{ *:[i32] }:$format), (extract_cpol:{ *:[i32] } ?:{ *:[i32] }:$auxiliary), (extract_swz:{ *:[i1] } ?:{ *:[i32] }:$auxiliary))
        GIR_BuildMI, /*InsnID*/0, /*Opcode*/GIMT_Encode2(AMDGPU::TBUFFER_STORE_FORMAT_D16_X_gfx80_OFFSET_exact),
        GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/0, // vdata
        GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/1, // rsrc
        GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/0, // soffset
        GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/5, // offset
        GIR_CustomOperandRenderer, /*InsnID*/0, /*OldInsnID*/0, /*OpIdx*/6, /*OperandRenderer*/GIMT_Encode2(GICR_renderTruncTImm), // format
        GIR_CustomOperandRenderer, /*InsnID*/0, /*OldInsnID*/0, /*OpIdx*/7, /*OperandRenderer*/GIMT_Encode2(GICR_renderExtractCPol), // auxiliary
        GIR_CustomOperandRenderer, /*InsnID*/0, /*OldInsnID*/0, /*OpIdx*/7, /*OperandRenderer*/GIMT_Encode2(GICR_renderExtractSWZ), // auxiliary
        GIR_MergeMemOperands, /*InsnID*/0, /*NumInsns*/1, /*MergeInsnID's*/0,
        GIR_ConstrainSelectedInstOperands, /*InsnID*/0,
        GIR_EraseFromParent, /*InsnID*/0,
        // GIR_Coverage, 5761,
        GIR_Done,
      // Label 7453: @545392
      GIM_Try, /*On fail goto*//*Label 7454*/ GIMT_Encode4(545483), // Rule ID 5785 //
        GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasPackedD16VMem_HasUnrestrictedSOffset),
        GIM_CheckConstantInt8, /*MI*/0, /*Op*/2, 0,
        GIM_CheckConstantInt8, /*MI*/0, /*Op*/3, 0,
        // MIs[0] offset
        GIM_CheckIsImm, /*MI*/0, /*Op*/5,
        // MIs[0] format
        GIM_CheckIsImm, /*MI*/0, /*Op*/6,
        // MIs[0] auxiliary
        GIM_CheckIsImm, /*MI*/0, /*Op*/7,
        // MIs[0] Operand 8
        GIM_CheckLiteralInt, /*MI*/0, /*Op*/8, GIMT_Encode8(0),
        GIM_CheckComplexPattern, /*MI*/0, /*Op*/4, /*Renderer*/GIMT_Encode2(0), GIMT_Encode2(GICP_gi_buf_soffset),
        // (SItbuffer_store_d16 i32:{ *:[i32] }:$vdata, v4i32:{ *:[v4i32] }:$rsrc, 0:{ *:[i32] }, 0:{ *:[i32] }, (BUFSOffset:{ *:[i32] } i32:{ *:[i32] }:$soffset), (timm:{ *:[i32] }):$offset, (timm:{ *:[i32] }):$format, (timm:{ *:[i32] }):$auxiliary, 0:{ *:[i1] })  =>  (TBUFFER_STORE_FORMAT_D16_X_OFFSET_exact anonymous_15037:{ *:[i32] }:$vdata, SReg_128:{ *:[v4i32] }:$rsrc, SCSrc_b32:{ *:[i32] }:$soffset, (timm:{ *:[i32] }):$offset, (as_i8timm:{ *:[i8] } ?:{ *:[i32] }:$format), (extract_cpol:{ *:[i32] } ?:{ *:[i32] }:$auxiliary), (extract_swz:{ *:[i1] } ?:{ *:[i32] }:$auxiliary))
        GIR_BuildMI, /*InsnID*/0, /*Opcode*/GIMT_Encode2(AMDGPU::TBUFFER_STORE_FORMAT_D16_X_OFFSET_exact),
        GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/0, // vdata
        GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/1, // rsrc
        GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/0, // soffset
        GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/5, // offset
        GIR_CustomOperandRenderer, /*InsnID*/0, /*OldInsnID*/0, /*OpIdx*/6, /*OperandRenderer*/GIMT_Encode2(GICR_renderTruncTImm), // format
        GIR_CustomOperandRenderer, /*InsnID*/0, /*OldInsnID*/0, /*OpIdx*/7, /*OperandRenderer*/GIMT_Encode2(GICR_renderExtractCPol), // auxiliary
        GIR_CustomOperandRenderer, /*InsnID*/0, /*OldInsnID*/0, /*OpIdx*/7, /*OperandRenderer*/GIMT_Encode2(GICR_renderExtractSWZ), // auxiliary
        GIR_MergeMemOperands, /*InsnID*/0, /*NumInsns*/1, /*MergeInsnID's*/0,
        GIR_ConstrainSelectedInstOperands, /*InsnID*/0,
        GIR_EraseFromParent, /*InsnID*/0,
        // GIR_Coverage, 5785,
        GIR_Done,
      // Label 7454: @545483
      GIM_Try, /*On fail goto*//*Label 7455*/ GIMT_Encode4(545574), // Rule ID 5789 //
        GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasPackedD16VMem),
        GIM_CheckConstantInt8, /*MI*/0, /*Op*/2, 0,
        GIM_CheckConstantInt8, /*MI*/0, /*Op*/3, 0,
        // MIs[0] offset
        GIM_CheckIsImm, /*MI*/0, /*Op*/5,
        // MIs[0] format
        GIM_CheckIsImm, /*MI*/0, /*Op*/6,
        // MIs[0] auxiliary
        GIM_CheckIsImm, /*MI*/0, /*Op*/7,
        // MIs[0] Operand 8
        GIM_CheckLiteralInt, /*MI*/0, /*Op*/8, GIMT_Encode8(0),
        GIM_CheckComplexPattern, /*MI*/0, /*Op*/4, /*Renderer*/GIMT_Encode2(0), GIMT_Encode2(GICP_gi_buf_soffset),
        // (SItbuffer_store_d16 i32:{ *:[i32] }:$vdata, v4i32:{ *:[v4i32] }:$rsrc, 0:{ *:[i32] }, 0:{ *:[i32] }, (BUFSOffset:{ *:[i32] } i32:{ *:[i32] }:$soffset), (timm:{ *:[i32] }):$offset, (timm:{ *:[i32] }):$format, (timm:{ *:[i32] }):$auxiliary, 0:{ *:[i1] })  =>  (TBUFFER_STORE_FORMAT_D16_X_VBUFFER_OFFSET_exact anonymous_15037:{ *:[i32] }:$vdata, SReg_128:{ *:[v4i32] }:$rsrc, SCSrc_b32:{ *:[i32] }:$soffset, (timm:{ *:[i32] }):$offset, (as_i8timm:{ *:[i8] } ?:{ *:[i32] }:$format), (extract_cpol:{ *:[i32] } ?:{ *:[i32] }:$auxiliary), (extract_swz:{ *:[i1] } ?:{ *:[i32] }:$auxiliary))
        GIR_BuildMI, /*InsnID*/0, /*Opcode*/GIMT_Encode2(AMDGPU::TBUFFER_STORE_FORMAT_D16_X_VBUFFER_OFFSET_exact),
        GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/0, // vdata
        GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/1, // rsrc
        GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/0, // soffset
        GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/5, // offset
        GIR_CustomOperandRenderer, /*InsnID*/0, /*OldInsnID*/0, /*OpIdx*/6, /*OperandRenderer*/GIMT_Encode2(GICR_renderTruncTImm), // format
        GIR_CustomOperandRenderer, /*InsnID*/0, /*OldInsnID*/0, /*OpIdx*/7, /*OperandRenderer*/GIMT_Encode2(GICR_renderExtractCPol), // auxiliary
        GIR_CustomOperandRenderer, /*InsnID*/0, /*OldInsnID*/0, /*OpIdx*/7, /*OperandRenderer*/GIMT_Encode2(GICR_renderExtractSWZ), // auxiliary
        GIR_MergeMemOperands, /*InsnID*/0, /*NumInsns*/1, /*MergeInsnID's*/0,
        GIR_ConstrainSelectedInstOperands, /*InsnID*/0,
        GIR_EraseFromParent, /*InsnID*/0,
        // GIR_Coverage, 5789,
        GIR_Done,
      // Label 7455: @545574
      GIM_Try, /*On fail goto*//*Label 7456*/ GIMT_Encode4(545665), // Rule ID 5763 //
        GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasUnpackedD16VMem),
        GIM_CheckConstantInt8, /*MI*/0, /*Op*/2, 0,
        // MIs[0] offset
        GIM_CheckIsImm, /*MI*/0, /*Op*/5,
        // MIs[0] format
        GIM_CheckIsImm, /*MI*/0, /*Op*/6,
        // MIs[0] auxiliary
        GIM_CheckIsImm, /*MI*/0, /*Op*/7,
        // MIs[0] Operand 8
        GIM_CheckLiteralInt, /*MI*/0, /*Op*/8, GIMT_Encode8(0),
        GIM_CheckComplexPattern, /*MI*/0, /*Op*/4, /*Renderer*/GIMT_Encode2(0), GIMT_Encode2(GICP_gi_buf_soffset),
        // (SItbuffer_store_d16 i32:{ *:[i32] }:$vdata, v4i32:{ *:[v4i32] }:$rsrc, 0:{ *:[i32] }, i32:{ *:[i32] }:$voffset, (BUFSOffset:{ *:[i32] } i32:{ *:[i32] }:$soffset), (timm:{ *:[i32] }):$offset, (timm:{ *:[i32] }):$format, (timm:{ *:[i32] }):$auxiliary, 0:{ *:[i1] })  =>  (TBUFFER_STORE_FORMAT_D16_X_gfx80_OFFEN_exact anonymous_15037:{ *:[i32] }:$vdata, VGPR_32:{ *:[i32] }:$voffset, SReg_128:{ *:[v4i32] }:$rsrc, SCSrc_b32:{ *:[i32] }:$soffset, (timm:{ *:[i32] }):$offset, (as_i8timm:{ *:[i8] } ?:{ *:[i32] }:$format), (extract_cpol:{ *:[i32] } ?:{ *:[i32] }:$auxiliary), (extract_swz:{ *:[i1] } ?:{ *:[i32] }:$auxiliary))
        GIR_BuildMI, /*InsnID*/0, /*Opcode*/GIMT_Encode2(AMDGPU::TBUFFER_STORE_FORMAT_D16_X_gfx80_OFFEN_exact),
        GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/0, // vdata
        GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/3, // voffset
        GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/1, // rsrc
        GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/0, // soffset
        GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/5, // offset
        GIR_CustomOperandRenderer, /*InsnID*/0, /*OldInsnID*/0, /*OpIdx*/6, /*OperandRenderer*/GIMT_Encode2(GICR_renderTruncTImm), // format
        GIR_CustomOperandRenderer, /*InsnID*/0, /*OldInsnID*/0, /*OpIdx*/7, /*OperandRenderer*/GIMT_Encode2(GICR_renderExtractCPol), // auxiliary
        GIR_CustomOperandRenderer, /*InsnID*/0, /*OldInsnID*/0, /*OpIdx*/7, /*OperandRenderer*/GIMT_Encode2(GICR_renderExtractSWZ), // auxiliary
        GIR_MergeMemOperands, /*InsnID*/0, /*NumInsns*/1, /*MergeInsnID's*/0,
        GIR_ConstrainSelectedInstOperands, /*InsnID*/0,
        GIR_EraseFromParent, /*InsnID*/0,
        // GIR_Coverage, 5763,
        GIR_Done,
      // Label 7456: @545665
      GIM_Try, /*On fail goto*//*Label 7457*/ GIMT_Encode4(545756), // Rule ID 5787 //
        GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasPackedD16VMem_HasUnrestrictedSOffset),
        GIM_CheckConstantInt8, /*MI*/0, /*Op*/2, 0,
        // MIs[0] offset
        GIM_CheckIsImm, /*MI*/0, /*Op*/5,
        // MIs[0] format
        GIM_CheckIsImm, /*MI*/0, /*Op*/6,
        // MIs[0] auxiliary
        GIM_CheckIsImm, /*MI*/0, /*Op*/7,
        // MIs[0] Operand 8
        GIM_CheckLiteralInt, /*MI*/0, /*Op*/8, GIMT_Encode8(0),
        GIM_CheckComplexPattern, /*MI*/0, /*Op*/4, /*Renderer*/GIMT_Encode2(0), GIMT_Encode2(GICP_gi_buf_soffset),
        // (SItbuffer_store_d16 i32:{ *:[i32] }:$vdata, v4i32:{ *:[v4i32] }:$rsrc, 0:{ *:[i32] }, i32:{ *:[i32] }:$voffset, (BUFSOffset:{ *:[i32] } i32:{ *:[i32] }:$soffset), (timm:{ *:[i32] }):$offset, (timm:{ *:[i32] }):$format, (timm:{ *:[i32] }):$auxiliary, 0:{ *:[i1] })  =>  (TBUFFER_STORE_FORMAT_D16_X_OFFEN_exact anonymous_15037:{ *:[i32] }:$vdata, VGPR_32:{ *:[i32] }:$voffset, SReg_128:{ *:[v4i32] }:$rsrc, SCSrc_b32:{ *:[i32] }:$soffset, (timm:{ *:[i32] }):$offset, (as_i8timm:{ *:[i8] } ?:{ *:[i32] }:$format), (extract_cpol:{ *:[i32] } ?:{ *:[i32] }:$auxiliary), (extract_swz:{ *:[i1] } ?:{ *:[i32] }:$auxiliary))
        GIR_BuildMI, /*InsnID*/0, /*Opcode*/GIMT_Encode2(AMDGPU::TBUFFER_STORE_FORMAT_D16_X_OFFEN_exact),
        GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/0, // vdata
        GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/3, // voffset
        GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/1, // rsrc
        GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/0, // soffset
        GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/5, // offset
        GIR_CustomOperandRenderer, /*InsnID*/0, /*OldInsnID*/0, /*OpIdx*/6, /*OperandRenderer*/GIMT_Encode2(GICR_renderTruncTImm), // format
        GIR_CustomOperandRenderer, /*InsnID*/0, /*OldInsnID*/0, /*OpIdx*/7, /*OperandRenderer*/GIMT_Encode2(GICR_renderExtractCPol), // auxiliary
        GIR_CustomOperandRenderer, /*InsnID*/0, /*OldInsnID*/0, /*OpIdx*/7, /*OperandRenderer*/GIMT_Encode2(GICR_renderExtractSWZ), // auxiliary
        GIR_MergeMemOperands, /*InsnID*/0, /*NumInsns*/1, /*MergeInsnID's*/0,
        GIR_ConstrainSelectedInstOperands, /*InsnID*/0,
        GIR_EraseFromParent, /*InsnID*/0,
        // GIR_Coverage, 5787,
        GIR_Done,
      // Label 7457: @545756
      GIM_Try, /*On fail goto*//*Label 7458*/ GIMT_Encode4(545847), // Rule ID 5791 //
        GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasPackedD16VMem),
        GIM_CheckConstantInt8, /*MI*/0, /*Op*/2, 0,
        // MIs[0] offset
        GIM_CheckIsImm, /*MI*/0, /*Op*/5,
        // MIs[0] format
        GIM_CheckIsImm, /*MI*/0, /*Op*/6,
        // MIs[0] auxiliary
        GIM_CheckIsImm, /*MI*/0, /*Op*/7,
        // MIs[0] Operand 8
        GIM_CheckLiteralInt, /*MI*/0, /*Op*/8, GIMT_Encode8(0),
        GIM_CheckComplexPattern, /*MI*/0, /*Op*/4, /*Renderer*/GIMT_Encode2(0), GIMT_Encode2(GICP_gi_buf_soffset),
        // (SItbuffer_store_d16 i32:{ *:[i32] }:$vdata, v4i32:{ *:[v4i32] }:$rsrc, 0:{ *:[i32] }, i32:{ *:[i32] }:$voffset, (BUFSOffset:{ *:[i32] } i32:{ *:[i32] }:$soffset), (timm:{ *:[i32] }):$offset, (timm:{ *:[i32] }):$format, (timm:{ *:[i32] }):$auxiliary, 0:{ *:[i1] })  =>  (TBUFFER_STORE_FORMAT_D16_X_VBUFFER_OFFEN_exact anonymous_15037:{ *:[i32] }:$vdata, VGPR_32:{ *:[i32] }:$voffset, SReg_128:{ *:[v4i32] }:$rsrc, SCSrc_b32:{ *:[i32] }:$soffset, (timm:{ *:[i32] }):$offset, (as_i8timm:{ *:[i8] } ?:{ *:[i32] }:$format), (extract_cpol:{ *:[i32] } ?:{ *:[i32] }:$auxiliary), (extract_swz:{ *:[i1] } ?:{ *:[i32] }:$auxiliary))
        GIR_BuildMI, /*InsnID*/0, /*Opcode*/GIMT_Encode2(AMDGPU::TBUFFER_STORE_FORMAT_D16_X_VBUFFER_OFFEN_exact),
        GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/0, // vdata
        GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/3, // voffset
        GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/1, // rsrc
        GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/0, // soffset
        GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/5, // offset
        GIR_CustomOperandRenderer, /*InsnID*/0, /*OldInsnID*/0, /*OpIdx*/6, /*OperandRenderer*/GIMT_Encode2(GICR_renderTruncTImm), // format
        GIR_CustomOperandRenderer, /*InsnID*/0, /*OldInsnID*/0, /*OpIdx*/7, /*OperandRenderer*/GIMT_Encode2(GICR_renderExtractCPol), // auxiliary
        GIR_CustomOperandRenderer, /*InsnID*/0, /*OldInsnID*/0, /*OpIdx*/7, /*OperandRenderer*/GIMT_Encode2(GICR_renderExtractSWZ), // auxiliary
        GIR_MergeMemOperands, /*InsnID*/0, /*NumInsns*/1, /*MergeInsnID's*/0,
        GIR_ConstrainSelectedInstOperands, /*InsnID*/0,
        GIR_EraseFromParent, /*InsnID*/0,
        // GIR_Coverage, 5791,
        GIR_Done,
      // Label 7458: @545847
      GIM_Try, /*On fail goto*//*Label 7459*/ GIMT_Encode4(545930), // Rule ID 5762 //
        GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasUnpackedD16VMem),
        GIM_CheckConstantInt8, /*MI*/0, /*Op*/3, 0,
        // MIs[0] offset
        GIM_CheckIsImm, /*MI*/0, /*Op*/5,
        // MIs[0] format
        GIM_CheckIsImm, /*MI*/0, /*Op*/6,
        // MIs[0] auxiliary
        GIM_CheckIsImm, /*MI*/0, /*Op*/7,
        // MIs[0] Operand 8
        GIM_CheckIsImm, /*MI*/0, /*Op*/8,
        GIM_CheckComplexPattern, /*MI*/0, /*Op*/4, /*Renderer*/GIMT_Encode2(0), GIMT_Encode2(GICP_gi_buf_soffset),
        // (SItbuffer_store_d16 i32:{ *:[i32] }:$vdata, v4i32:{ *:[v4i32] }:$rsrc, i32:{ *:[i32] }:$vindex, 0:{ *:[i32] }, (BUFSOffset:{ *:[i32] } i32:{ *:[i32] }:$soffset), (timm:{ *:[i32] }):$offset, (timm:{ *:[i32] }):$format, (timm:{ *:[i32] }):$auxiliary, (timm:{ *:[i1] }))  =>  (TBUFFER_STORE_FORMAT_D16_X_gfx80_IDXEN_exact anonymous_15037:{ *:[i32] }:$vdata, VGPR_32:{ *:[i32] }:$vindex, SReg_128:{ *:[v4i32] }:$rsrc, SCSrc_b32:{ *:[i32] }:$soffset, (timm:{ *:[i32] }):$offset, (as_i8timm:{ *:[i8] } ?:{ *:[i32] }:$format), (extract_cpol:{ *:[i32] } ?:{ *:[i32] }:$auxiliary), (extract_swz:{ *:[i1] } ?:{ *:[i32] }:$auxiliary))
        GIR_BuildMI, /*InsnID*/0, /*Opcode*/GIMT_Encode2(AMDGPU::TBUFFER_STORE_FORMAT_D16_X_gfx80_IDXEN_exact),
        GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/0, // vdata
        GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/2, // vindex
        GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/1, // rsrc
        GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/0, // soffset
        GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/5, // offset
        GIR_CustomOperandRenderer, /*InsnID*/0, /*OldInsnID*/0, /*OpIdx*/6, /*OperandRenderer*/GIMT_Encode2(GICR_renderTruncTImm), // format
        GIR_CustomOperandRenderer, /*InsnID*/0, /*OldInsnID*/0, /*OpIdx*/7, /*OperandRenderer*/GIMT_Encode2(GICR_renderExtractCPol), // auxiliary
        GIR_CustomOperandRenderer, /*InsnID*/0, /*OldInsnID*/0, /*OpIdx*/7, /*OperandRenderer*/GIMT_Encode2(GICR_renderExtractSWZ), // auxiliary
        GIR_MergeMemOperands, /*InsnID*/0, /*NumInsns*/1, /*MergeInsnID's*/0,
        GIR_ConstrainSelectedInstOperands, /*InsnID*/0,
        GIR_EraseFromParent, /*InsnID*/0,
        // GIR_Coverage, 5762,
        GIR_Done,
      // Label 7459: @545930
      GIM_Try, /*On fail goto*//*Label 7460*/ GIMT_Encode4(546013), // Rule ID 5786 //
        GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasPackedD16VMem_HasUnrestrictedSOffset),
        GIM_CheckConstantInt8, /*MI*/0, /*Op*/3, 0,
        // MIs[0] offset
        GIM_CheckIsImm, /*MI*/0, /*Op*/5,
        // MIs[0] format
        GIM_CheckIsImm, /*MI*/0, /*Op*/6,
        // MIs[0] auxiliary
        GIM_CheckIsImm, /*MI*/0, /*Op*/7,
        // MIs[0] Operand 8
        GIM_CheckIsImm, /*MI*/0, /*Op*/8,
        GIM_CheckComplexPattern, /*MI*/0, /*Op*/4, /*Renderer*/GIMT_Encode2(0), GIMT_Encode2(GICP_gi_buf_soffset),
        // (SItbuffer_store_d16 i32:{ *:[i32] }:$vdata, v4i32:{ *:[v4i32] }:$rsrc, i32:{ *:[i32] }:$vindex, 0:{ *:[i32] }, (BUFSOffset:{ *:[i32] } i32:{ *:[i32] }:$soffset), (timm:{ *:[i32] }):$offset, (timm:{ *:[i32] }):$format, (timm:{ *:[i32] }):$auxiliary, (timm:{ *:[i1] }))  =>  (TBUFFER_STORE_FORMAT_D16_X_IDXEN_exact anonymous_15037:{ *:[i32] }:$vdata, VGPR_32:{ *:[i32] }:$vindex, SReg_128:{ *:[v4i32] }:$rsrc, SCSrc_b32:{ *:[i32] }:$soffset, (timm:{ *:[i32] }):$offset, (as_i8timm:{ *:[i8] } ?:{ *:[i32] }:$format), (extract_cpol:{ *:[i32] } ?:{ *:[i32] }:$auxiliary), (extract_swz:{ *:[i1] } ?:{ *:[i32] }:$auxiliary))
        GIR_BuildMI, /*InsnID*/0, /*Opcode*/GIMT_Encode2(AMDGPU::TBUFFER_STORE_FORMAT_D16_X_IDXEN_exact),
        GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/0, // vdata
        GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/2, // vindex
        GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/1, // rsrc
        GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/0, // soffset
        GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/5, // offset
        GIR_CustomOperandRenderer, /*InsnID*/0, /*OldInsnID*/0, /*OpIdx*/6, /*OperandRenderer*/GIMT_Encode2(GICR_renderTruncTImm), // format
        GIR_CustomOperandRenderer, /*InsnID*/0, /*OldInsnID*/0, /*OpIdx*/7, /*OperandRenderer*/GIMT_Encode2(GICR_renderExtractCPol), // auxiliary
        GIR_CustomOperandRenderer, /*InsnID*/0, /*OldInsnID*/0, /*OpIdx*/7, /*OperandRenderer*/GIMT_Encode2(GICR_renderExtractSWZ), // auxiliary
        GIR_MergeMemOperands, /*InsnID*/0, /*NumInsns*/1, /*MergeInsnID's*/0,
        GIR_ConstrainSelectedInstOperands, /*InsnID*/0,
        GIR_EraseFromParent, /*InsnID*/0,
        // GIR_Coverage, 5786,
        GIR_Done,
      // Label 7460: @546013
      GIM_Try, /*On fail goto*//*Label 7461*/ GIMT_Encode4(546096), // Rule ID 5790 //
        GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasPackedD16VMem),
        GIM_CheckConstantInt8, /*MI*/0, /*Op*/3, 0,
        // MIs[0] offset
        GIM_CheckIsImm, /*MI*/0, /*Op*/5,
        // MIs[0] format
        GIM_CheckIsImm, /*MI*/0, /*Op*/6,
        // MIs[0] auxiliary
        GIM_CheckIsImm, /*MI*/0, /*Op*/7,
        // MIs[0] Operand 8
        GIM_CheckIsImm, /*MI*/0, /*Op*/8,
        GIM_CheckComplexPattern, /*MI*/0, /*Op*/4, /*Renderer*/GIMT_Encode2(0), GIMT_Encode2(GICP_gi_buf_soffset),
        // (SItbuffer_store_d16 i32:{ *:[i32] }:$vdata, v4i32:{ *:[v4i32] }:$rsrc, i32:{ *:[i32] }:$vindex, 0:{ *:[i32] }, (BUFSOffset:{ *:[i32] } i32:{ *:[i32] }:$soffset), (timm:{ *:[i32] }):$offset, (timm:{ *:[i32] }):$format, (timm:{ *:[i32] }):$auxiliary, (timm:{ *:[i1] }))  =>  (TBUFFER_STORE_FORMAT_D16_X_VBUFFER_IDXEN_exact anonymous_15037:{ *:[i32] }:$vdata, VGPR_32:{ *:[i32] }:$vindex, SReg_128:{ *:[v4i32] }:$rsrc, SCSrc_b32:{ *:[i32] }:$soffset, (timm:{ *:[i32] }):$offset, (as_i8timm:{ *:[i8] } ?:{ *:[i32] }:$format), (extract_cpol:{ *:[i32] } ?:{ *:[i32] }:$auxiliary), (extract_swz:{ *:[i1] } ?:{ *:[i32] }:$auxiliary))
        GIR_BuildMI, /*InsnID*/0, /*Opcode*/GIMT_Encode2(AMDGPU::TBUFFER_STORE_FORMAT_D16_X_VBUFFER_IDXEN_exact),
        GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/0, // vdata
        GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/2, // vindex
        GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/1, // rsrc
        GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/0, // soffset
        GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/5, // offset
        GIR_CustomOperandRenderer, /*InsnID*/0, /*OldInsnID*/0, /*OpIdx*/6, /*OperandRenderer*/GIMT_Encode2(GICR_renderTruncTImm), // format
        GIR_CustomOperandRenderer, /*InsnID*/0, /*OldInsnID*/0, /*OpIdx*/7, /*OperandRenderer*/GIMT_Encode2(GICR_renderExtractCPol), // auxiliary
        GIR_CustomOperandRenderer, /*InsnID*/0, /*OldInsnID*/0, /*OpIdx*/7, /*OperandRenderer*/GIMT_Encode2(GICR_renderExtractSWZ), // auxiliary
        GIR_MergeMemOperands, /*InsnID*/0, /*NumInsns*/1, /*MergeInsnID's*/0,
        GIR_ConstrainSelectedInstOperands, /*InsnID*/0,
        GIR_EraseFromParent, /*InsnID*/0,
        // GIR_Coverage, 5790,
        GIR_Done,
      // Label 7461: @546096
      GIM_Try, /*On fail goto*//*Label 7462*/ GIMT_Encode4(546215), // Rule ID 5764 //
        GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasUnpackedD16VMem),
        // MIs[0] offset
        GIM_CheckIsImm, /*MI*/0, /*Op*/5,
        // MIs[0] format
        GIM_CheckIsImm, /*MI*/0, /*Op*/6,
        // MIs[0] auxiliary
        GIM_CheckIsImm, /*MI*/0, /*Op*/7,
        // MIs[0] Operand 8
        GIM_CheckIsImm, /*MI*/0, /*Op*/8,
        GIM_CheckComplexPattern, /*MI*/0, /*Op*/4, /*Renderer*/GIMT_Encode2(0), GIMT_Encode2(GICP_gi_buf_soffset),
        // (SItbuffer_store_d16 i32:{ *:[i32] }:$vdata, v4i32:{ *:[v4i32] }:$rsrc, i32:{ *:[i32] }:$vindex, i32:{ *:[i32] }:$voffset, (BUFSOffset:{ *:[i32] } i32:{ *:[i32] }:$soffset), (timm:{ *:[i32] }):$offset, (timm:{ *:[i32] }):$format, (timm:{ *:[i32] }):$auxiliary, (timm:{ *:[i1] }))  =>  (TBUFFER_STORE_FORMAT_D16_X_gfx80_BOTHEN_exact anonymous_15037:{ *:[i32] }:$vdata, (REG_SEQUENCE:{ *:[i64] } VReg_64:{ *:[i32] }, VGPR_32:{ *:[i32] }:$vindex, sub0:{ *:[i32] }, VGPR_32:{ *:[i32] }:$voffset, sub1:{ *:[i32] }), SReg_128:{ *:[v4i32] }:$rsrc, SCSrc_b32:{ *:[i32] }:$soffset, (timm:{ *:[i32] }):$offset, (as_i8timm:{ *:[i8] } ?:{ *:[i32] }:$format), (extract_cpol:{ *:[i32] } ?:{ *:[i32] }:$auxiliary), (extract_swz:{ *:[i1] } ?:{ *:[i32] }:$auxiliary))
        GIR_MakeTempReg, /*TempRegID*/0, /*TypeID*/GILLT_s64,
        GIR_BuildMI, /*InsnID*/1, /*Opcode*/GIMT_Encode2(TargetOpcode::REG_SEQUENCE),
        GIR_AddTempRegister, /*InsnID*/1, /*TempRegID*/0, /*TempRegFlags*/GIMT_Encode2(RegState::Define),
        GIR_Copy, /*NewInsnID*/1, /*OldInsnID*/0, /*OpIdx*/2, // vindex
        GIR_AddImm8, /*InsnID*/1, /*SubRegIndex*/3,
        GIR_Copy, /*NewInsnID*/1, /*OldInsnID*/0, /*OpIdx*/3, // voffset
        GIR_AddImm8, /*InsnID*/1, /*SubRegIndex*/11,
        GIR_ConstrainOperandRC, /*InsnID*/1, /*Op*/0, GIMT_Encode2(AMDGPU::VReg_64RegClassID),
        GIR_ConstrainOperandRC, /*InsnID*/1, /*Op*/1, GIMT_Encode2(AMDGPU::VGPR_32RegClassID),
        GIR_ConstrainOperandRC, /*InsnID*/1, /*Op*/3, GIMT_Encode2(AMDGPU::VGPR_32RegClassID),
        GIR_BuildMI, /*InsnID*/0, /*Opcode*/GIMT_Encode2(AMDGPU::TBUFFER_STORE_FORMAT_D16_X_gfx80_BOTHEN_exact),
        GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/0, // vdata
        GIR_AddSimpleTempRegister, /*InsnID*/0, /*TempRegID*/0,
        GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/1, // rsrc
        GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/0, // soffset
        GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/5, // offset
        GIR_CustomOperandRenderer, /*InsnID*/0, /*OldInsnID*/0, /*OpIdx*/6, /*OperandRenderer*/GIMT_Encode2(GICR_renderTruncTImm), // format
        GIR_CustomOperandRenderer, /*InsnID*/0, /*OldInsnID*/0, /*OpIdx*/7, /*OperandRenderer*/GIMT_Encode2(GICR_renderExtractCPol), // auxiliary
        GIR_CustomOperandRenderer, /*InsnID*/0, /*OldInsnID*/0, /*OpIdx*/7, /*OperandRenderer*/GIMT_Encode2(GICR_renderExtractSWZ), // auxiliary
        GIR_MergeMemOperands, /*InsnID*/0, /*NumInsns*/1, /*MergeInsnID's*/0,
        GIR_ConstrainSelectedInstOperands, /*InsnID*/0,
        GIR_EraseFromParent, /*InsnID*/0,
        // GIR_Coverage, 5764,
        GIR_Done,
      // Label 7462: @546215
      GIM_Try, /*On fail goto*//*Label 7463*/ GIMT_Encode4(546334), // Rule ID 5788 //
        GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasPackedD16VMem_HasUnrestrictedSOffset),
        // MIs[0] offset
        GIM_CheckIsImm, /*MI*/0, /*Op*/5,
        // MIs[0] format
        GIM_CheckIsImm, /*MI*/0, /*Op*/6,
        // MIs[0] auxiliary
        GIM_CheckIsImm, /*MI*/0, /*Op*/7,
        // MIs[0] Operand 8
        GIM_CheckIsImm, /*MI*/0, /*Op*/8,
        GIM_CheckComplexPattern, /*MI*/0, /*Op*/4, /*Renderer*/GIMT_Encode2(0), GIMT_Encode2(GICP_gi_buf_soffset),
        // (SItbuffer_store_d16 i32:{ *:[i32] }:$vdata, v4i32:{ *:[v4i32] }:$rsrc, i32:{ *:[i32] }:$vindex, i32:{ *:[i32] }:$voffset, (BUFSOffset:{ *:[i32] } i32:{ *:[i32] }:$soffset), (timm:{ *:[i32] }):$offset, (timm:{ *:[i32] }):$format, (timm:{ *:[i32] }):$auxiliary, (timm:{ *:[i1] }))  =>  (TBUFFER_STORE_FORMAT_D16_X_BOTHEN_exact anonymous_15037:{ *:[i32] }:$vdata, (REG_SEQUENCE:{ *:[i64] } VReg_64:{ *:[i32] }, VGPR_32:{ *:[i32] }:$vindex, sub0:{ *:[i32] }, VGPR_32:{ *:[i32] }:$voffset, sub1:{ *:[i32] }), SReg_128:{ *:[v4i32] }:$rsrc, SCSrc_b32:{ *:[i32] }:$soffset, (timm:{ *:[i32] }):$offset, (as_i8timm:{ *:[i8] } ?:{ *:[i32] }:$format), (extract_cpol:{ *:[i32] } ?:{ *:[i32] }:$auxiliary), (extract_swz:{ *:[i1] } ?:{ *:[i32] }:$auxiliary))
        GIR_MakeTempReg, /*TempRegID*/0, /*TypeID*/GILLT_s64,
        GIR_BuildMI, /*InsnID*/1, /*Opcode*/GIMT_Encode2(TargetOpcode::REG_SEQUENCE),
        GIR_AddTempRegister, /*InsnID*/1, /*TempRegID*/0, /*TempRegFlags*/GIMT_Encode2(RegState::Define),
        GIR_Copy, /*NewInsnID*/1, /*OldInsnID*/0, /*OpIdx*/2, // vindex
        GIR_AddImm8, /*InsnID*/1, /*SubRegIndex*/3,
        GIR_Copy, /*NewInsnID*/1, /*OldInsnID*/0, /*OpIdx*/3, // voffset
        GIR_AddImm8, /*InsnID*/1, /*SubRegIndex*/11,
        GIR_ConstrainOperandRC, /*InsnID*/1, /*Op*/0, GIMT_Encode2(AMDGPU::VReg_64RegClassID),
        GIR_ConstrainOperandRC, /*InsnID*/1, /*Op*/1, GIMT_Encode2(AMDGPU::VGPR_32RegClassID),
        GIR_ConstrainOperandRC, /*InsnID*/1, /*Op*/3, GIMT_Encode2(AMDGPU::VGPR_32RegClassID),
        GIR_BuildMI, /*InsnID*/0, /*Opcode*/GIMT_Encode2(AMDGPU::TBUFFER_STORE_FORMAT_D16_X_BOTHEN_exact),
        GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/0, // vdata
        GIR_AddSimpleTempRegister, /*InsnID*/0, /*TempRegID*/0,
        GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/1, // rsrc
        GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/0, // soffset
        GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/5, // offset
        GIR_CustomOperandRenderer, /*InsnID*/0, /*OldInsnID*/0, /*OpIdx*/6, /*OperandRenderer*/GIMT_Encode2(GICR_renderTruncTImm), // format
        GIR_CustomOperandRenderer, /*InsnID*/0, /*OldInsnID*/0, /*OpIdx*/7, /*OperandRenderer*/GIMT_Encode2(GICR_renderExtractCPol), // auxiliary
        GIR_CustomOperandRenderer, /*InsnID*/0, /*OldInsnID*/0, /*OpIdx*/7, /*OperandRenderer*/GIMT_Encode2(GICR_renderExtractSWZ), // auxiliary
        GIR_MergeMemOperands, /*InsnID*/0, /*NumInsns*/1, /*MergeInsnID's*/0,
        GIR_ConstrainSelectedInstOperands, /*InsnID*/0,
        GIR_EraseFromParent, /*InsnID*/0,
        // GIR_Coverage, 5788,
        GIR_Done,
      // Label 7463: @546334
      GIM_Try, /*On fail goto*//*Label 7464*/ GIMT_Encode4(546453), // Rule ID 5792 //
        GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasPackedD16VMem),
        // MIs[0] offset
        GIM_CheckIsImm, /*MI*/0, /*Op*/5,
        // MIs[0] format
        GIM_CheckIsImm, /*MI*/0, /*Op*/6,
        // MIs[0] auxiliary
        GIM_CheckIsImm, /*MI*/0, /*Op*/7,
        // MIs[0] Operand 8
        GIM_CheckIsImm, /*MI*/0, /*Op*/8,
        GIM_CheckComplexPattern, /*MI*/0, /*Op*/4, /*Renderer*/GIMT_Encode2(0), GIMT_Encode2(GICP_gi_buf_soffset),
        // (SItbuffer_store_d16 i32:{ *:[i32] }:$vdata, v4i32:{ *:[v4i32] }:$rsrc, i32:{ *:[i32] }:$vindex, i32:{ *:[i32] }:$voffset, (BUFSOffset:{ *:[i32] } i32:{ *:[i32] }:$soffset), (timm:{ *:[i32] }):$offset, (timm:{ *:[i32] }):$format, (timm:{ *:[i32] }):$auxiliary, (timm:{ *:[i1] }))  =>  (TBUFFER_STORE_FORMAT_D16_X_VBUFFER_BOTHEN_exact anonymous_15037:{ *:[i32] }:$vdata, (REG_SEQUENCE:{ *:[i64] } VReg_64:{ *:[i32] }, VGPR_32:{ *:[i32] }:$vindex, sub0:{ *:[i32] }, VGPR_32:{ *:[i32] }:$voffset, sub1:{ *:[i32] }), SReg_128:{ *:[v4i32] }:$rsrc, SCSrc_b32:{ *:[i32] }:$soffset, (timm:{ *:[i32] }):$offset, (as_i8timm:{ *:[i8] } ?:{ *:[i32] }:$format), (extract_cpol:{ *:[i32] } ?:{ *:[i32] }:$auxiliary), (extract_swz:{ *:[i1] } ?:{ *:[i32] }:$auxiliary))
        GIR_MakeTempReg, /*TempRegID*/0, /*TypeID*/GILLT_s64,
        GIR_BuildMI, /*InsnID*/1, /*Opcode*/GIMT_Encode2(TargetOpcode::REG_SEQUENCE),
        GIR_AddTempRegister, /*InsnID*/1, /*TempRegID*/0, /*TempRegFlags*/GIMT_Encode2(RegState::Define),
        GIR_Copy, /*NewInsnID*/1, /*OldInsnID*/0, /*OpIdx*/2, // vindex
        GIR_AddImm8, /*InsnID*/1, /*SubRegIndex*/3,
        GIR_Copy, /*NewInsnID*/1, /*OldInsnID*/0, /*OpIdx*/3, // voffset
        GIR_AddImm8, /*InsnID*/1, /*SubRegIndex*/11,
        GIR_ConstrainOperandRC, /*InsnID*/1, /*Op*/0, GIMT_Encode2(AMDGPU::VReg_64RegClassID),
        GIR_ConstrainOperandRC, /*InsnID*/1, /*Op*/1, GIMT_Encode2(AMDGPU::VGPR_32RegClassID),
        GIR_ConstrainOperandRC, /*InsnID*/1, /*Op*/3, GIMT_Encode2(AMDGPU::VGPR_32RegClassID),
        GIR_BuildMI, /*InsnID*/0, /*Opcode*/GIMT_Encode2(AMDGPU::TBUFFER_STORE_FORMAT_D16_X_VBUFFER_BOTHEN_exact),
        GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/0, // vdata
        GIR_AddSimpleTempRegister, /*InsnID*/0, /*TempRegID*/0,
        GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/1, // rsrc
        GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/0, // soffset
        GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/5, // offset
        GIR_CustomOperandRenderer, /*InsnID*/0, /*OldInsnID*/0, /*OpIdx*/6, /*OperandRenderer*/GIMT_Encode2(GICR_renderTruncTImm), // format
        GIR_CustomOperandRenderer, /*InsnID*/0, /*OldInsnID*/0, /*OpIdx*/7, /*OperandRenderer*/GIMT_Encode2(GICR_renderExtractCPol), // auxiliary
        GIR_CustomOperandRenderer, /*InsnID*/0, /*OldInsnID*/0, /*OpIdx*/7, /*OperandRenderer*/GIMT_Encode2(GICR_renderExtractSWZ), // auxiliary
        GIR_MergeMemOperands, /*InsnID*/0, /*NumInsns*/1, /*MergeInsnID's*/0,
        GIR_ConstrainSelectedInstOperands, /*InsnID*/0,
        GIR_EraseFromParent, /*InsnID*/0,
        // GIR_Coverage, 5792,
        GIR_Done,
      // Label 7464: @546453
      GIM_Reject,
    // Label 7452: @546454
    GIM_Reject,
    // Label 7433: @546455
    GIM_Try, /*On fail goto*//*Label 7465*/ GIMT_Encode4(547245),
      GIM_CheckType, /*MI*/0, /*Op*/1, /*Type*/GILLT_v4s32,
      GIM_CheckType, /*MI*/0, /*Op*/2, /*Type*/GILLT_s32,
      GIM_CheckType, /*MI*/0, /*Op*/3, /*Type*/GILLT_s32,
      GIM_CheckType, /*MI*/0, /*Op*/4, /*Type*/GILLT_s32,
      GIM_Try, /*On fail goto*//*Label 7466*/ GIMT_Encode4(546567), // Rule ID 5793 //
        GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasPackedD16VMem_HasUnrestrictedSOffset),
        GIM_CheckConstantInt8, /*MI*/0, /*Op*/2, 0,
        GIM_CheckConstantInt8, /*MI*/0, /*Op*/3, 0,
        // MIs[0] offset
        GIM_CheckIsImm, /*MI*/0, /*Op*/5,
        // MIs[0] format
        GIM_CheckIsImm, /*MI*/0, /*Op*/6,
        // MIs[0] auxiliary
        GIM_CheckIsImm, /*MI*/0, /*Op*/7,
        // MIs[0] Operand 8
        GIM_CheckLiteralInt, /*MI*/0, /*Op*/8, GIMT_Encode8(0),
        GIM_CheckComplexPattern, /*MI*/0, /*Op*/4, /*Renderer*/GIMT_Encode2(0), GIMT_Encode2(GICP_gi_buf_soffset),
        // (SItbuffer_store_d16 v2f16:{ *:[v2f16] }:$vdata, v4i32:{ *:[v4i32] }:$rsrc, 0:{ *:[i32] }, 0:{ *:[i32] }, (BUFSOffset:{ *:[i32] } i32:{ *:[i32] }:$soffset), (timm:{ *:[i32] }):$offset, (timm:{ *:[i32] }):$format, (timm:{ *:[i32] }):$auxiliary, 0:{ *:[i1] })  =>  (TBUFFER_STORE_FORMAT_D16_XY_OFFSET_exact anonymous_15037:{ *:[v2f16] }:$vdata, SReg_128:{ *:[v4i32] }:$rsrc, SCSrc_b32:{ *:[i32] }:$soffset, (timm:{ *:[i32] }):$offset, (as_i8timm:{ *:[i8] } ?:{ *:[i32] }:$format), (extract_cpol:{ *:[i32] } ?:{ *:[i32] }:$auxiliary), (extract_swz:{ *:[i1] } ?:{ *:[i32] }:$auxiliary))
        GIR_BuildMI, /*InsnID*/0, /*Opcode*/GIMT_Encode2(AMDGPU::TBUFFER_STORE_FORMAT_D16_XY_OFFSET_exact),
        GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/0, // vdata
        GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/1, // rsrc
        GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/0, // soffset
        GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/5, // offset
        GIR_CustomOperandRenderer, /*InsnID*/0, /*OldInsnID*/0, /*OpIdx*/6, /*OperandRenderer*/GIMT_Encode2(GICR_renderTruncTImm), // format
        GIR_CustomOperandRenderer, /*InsnID*/0, /*OldInsnID*/0, /*OpIdx*/7, /*OperandRenderer*/GIMT_Encode2(GICR_renderExtractCPol), // auxiliary
        GIR_CustomOperandRenderer, /*InsnID*/0, /*OldInsnID*/0, /*OpIdx*/7, /*OperandRenderer*/GIMT_Encode2(GICR_renderExtractSWZ), // auxiliary
        GIR_MergeMemOperands, /*InsnID*/0, /*NumInsns*/1, /*MergeInsnID's*/0,
        GIR_ConstrainSelectedInstOperands, /*InsnID*/0,
        GIR_EraseFromParent, /*InsnID*/0,
        // GIR_Coverage, 5793,
        GIR_Done,
      // Label 7466: @546567
      GIM_Try, /*On fail goto*//*Label 7467*/ GIMT_Encode4(546658), // Rule ID 5797 //
        GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasPackedD16VMem),
        GIM_CheckConstantInt8, /*MI*/0, /*Op*/2, 0,
        GIM_CheckConstantInt8, /*MI*/0, /*Op*/3, 0,
        // MIs[0] offset
        GIM_CheckIsImm, /*MI*/0, /*Op*/5,
        // MIs[0] format
        GIM_CheckIsImm, /*MI*/0, /*Op*/6,
        // MIs[0] auxiliary
        GIM_CheckIsImm, /*MI*/0, /*Op*/7,
        // MIs[0] Operand 8
        GIM_CheckLiteralInt, /*MI*/0, /*Op*/8, GIMT_Encode8(0),
        GIM_CheckComplexPattern, /*MI*/0, /*Op*/4, /*Renderer*/GIMT_Encode2(0), GIMT_Encode2(GICP_gi_buf_soffset),
        // (SItbuffer_store_d16 v2f16:{ *:[v2f16] }:$vdata, v4i32:{ *:[v4i32] }:$rsrc, 0:{ *:[i32] }, 0:{ *:[i32] }, (BUFSOffset:{ *:[i32] } i32:{ *:[i32] }:$soffset), (timm:{ *:[i32] }):$offset, (timm:{ *:[i32] }):$format, (timm:{ *:[i32] }):$auxiliary, 0:{ *:[i1] })  =>  (TBUFFER_STORE_FORMAT_D16_XY_VBUFFER_OFFSET_exact anonymous_15037:{ *:[v2f16] }:$vdata, SReg_128:{ *:[v4i32] }:$rsrc, SCSrc_b32:{ *:[i32] }:$soffset, (timm:{ *:[i32] }):$offset, (as_i8timm:{ *:[i8] } ?:{ *:[i32] }:$format), (extract_cpol:{ *:[i32] } ?:{ *:[i32] }:$auxiliary), (extract_swz:{ *:[i1] } ?:{ *:[i32] }:$auxiliary))
        GIR_BuildMI, /*InsnID*/0, /*Opcode*/GIMT_Encode2(AMDGPU::TBUFFER_STORE_FORMAT_D16_XY_VBUFFER_OFFSET_exact),
        GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/0, // vdata
        GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/1, // rsrc
        GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/0, // soffset
        GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/5, // offset
        GIR_CustomOperandRenderer, /*InsnID*/0, /*OldInsnID*/0, /*OpIdx*/6, /*OperandRenderer*/GIMT_Encode2(GICR_renderTruncTImm), // format
        GIR_CustomOperandRenderer, /*InsnID*/0, /*OldInsnID*/0, /*OpIdx*/7, /*OperandRenderer*/GIMT_Encode2(GICR_renderExtractCPol), // auxiliary
        GIR_CustomOperandRenderer, /*InsnID*/0, /*OldInsnID*/0, /*OpIdx*/7, /*OperandRenderer*/GIMT_Encode2(GICR_renderExtractSWZ), // auxiliary
        GIR_MergeMemOperands, /*InsnID*/0, /*NumInsns*/1, /*MergeInsnID's*/0,
        GIR_ConstrainSelectedInstOperands, /*InsnID*/0,
        GIR_EraseFromParent, /*InsnID*/0,
        // GIR_Coverage, 5797,
        GIR_Done,
      // Label 7467: @546658
      GIM_Try, /*On fail goto*//*Label 7468*/ GIMT_Encode4(546749), // Rule ID 5795 //
        GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasPackedD16VMem_HasUnrestrictedSOffset),
        GIM_CheckConstantInt8, /*MI*/0, /*Op*/2, 0,
        // MIs[0] offset
        GIM_CheckIsImm, /*MI*/0, /*Op*/5,
        // MIs[0] format
        GIM_CheckIsImm, /*MI*/0, /*Op*/6,
        // MIs[0] auxiliary
        GIM_CheckIsImm, /*MI*/0, /*Op*/7,
        // MIs[0] Operand 8
        GIM_CheckLiteralInt, /*MI*/0, /*Op*/8, GIMT_Encode8(0),
        GIM_CheckComplexPattern, /*MI*/0, /*Op*/4, /*Renderer*/GIMT_Encode2(0), GIMT_Encode2(GICP_gi_buf_soffset),
        // (SItbuffer_store_d16 v2f16:{ *:[v2f16] }:$vdata, v4i32:{ *:[v4i32] }:$rsrc, 0:{ *:[i32] }, i32:{ *:[i32] }:$voffset, (BUFSOffset:{ *:[i32] } i32:{ *:[i32] }:$soffset), (timm:{ *:[i32] }):$offset, (timm:{ *:[i32] }):$format, (timm:{ *:[i32] }):$auxiliary, 0:{ *:[i1] })  =>  (TBUFFER_STORE_FORMAT_D16_XY_OFFEN_exact anonymous_15037:{ *:[v2f16] }:$vdata, VGPR_32:{ *:[i32] }:$voffset, SReg_128:{ *:[v4i32] }:$rsrc, SCSrc_b32:{ *:[i32] }:$soffset, (timm:{ *:[i32] }):$offset, (as_i8timm:{ *:[i8] } ?:{ *:[i32] }:$format), (extract_cpol:{ *:[i32] } ?:{ *:[i32] }:$auxiliary), (extract_swz:{ *:[i1] } ?:{ *:[i32] }:$auxiliary))
        GIR_BuildMI, /*InsnID*/0, /*Opcode*/GIMT_Encode2(AMDGPU::TBUFFER_STORE_FORMAT_D16_XY_OFFEN_exact),
        GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/0, // vdata
        GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/3, // voffset
        GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/1, // rsrc
        GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/0, // soffset
        GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/5, // offset
        GIR_CustomOperandRenderer, /*InsnID*/0, /*OldInsnID*/0, /*OpIdx*/6, /*OperandRenderer*/GIMT_Encode2(GICR_renderTruncTImm), // format
        GIR_CustomOperandRenderer, /*InsnID*/0, /*OldInsnID*/0, /*OpIdx*/7, /*OperandRenderer*/GIMT_Encode2(GICR_renderExtractCPol), // auxiliary
        GIR_CustomOperandRenderer, /*InsnID*/0, /*OldInsnID*/0, /*OpIdx*/7, /*OperandRenderer*/GIMT_Encode2(GICR_renderExtractSWZ), // auxiliary
        GIR_MergeMemOperands, /*InsnID*/0, /*NumInsns*/1, /*MergeInsnID's*/0,
        GIR_ConstrainSelectedInstOperands, /*InsnID*/0,
        GIR_EraseFromParent, /*InsnID*/0,
        // GIR_Coverage, 5795,
        GIR_Done,
      // Label 7468: @546749
      GIM_Try, /*On fail goto*//*Label 7469*/ GIMT_Encode4(546840), // Rule ID 5799 //
        GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasPackedD16VMem),
        GIM_CheckConstantInt8, /*MI*/0, /*Op*/2, 0,
        // MIs[0] offset
        GIM_CheckIsImm, /*MI*/0, /*Op*/5,
        // MIs[0] format
        GIM_CheckIsImm, /*MI*/0, /*Op*/6,
        // MIs[0] auxiliary
        GIM_CheckIsImm, /*MI*/0, /*Op*/7,
        // MIs[0] Operand 8
        GIM_CheckLiteralInt, /*MI*/0, /*Op*/8, GIMT_Encode8(0),
        GIM_CheckComplexPattern, /*MI*/0, /*Op*/4, /*Renderer*/GIMT_Encode2(0), GIMT_Encode2(GICP_gi_buf_soffset),
        // (SItbuffer_store_d16 v2f16:{ *:[v2f16] }:$vdata, v4i32:{ *:[v4i32] }:$rsrc, 0:{ *:[i32] }, i32:{ *:[i32] }:$voffset, (BUFSOffset:{ *:[i32] } i32:{ *:[i32] }:$soffset), (timm:{ *:[i32] }):$offset, (timm:{ *:[i32] }):$format, (timm:{ *:[i32] }):$auxiliary, 0:{ *:[i1] })  =>  (TBUFFER_STORE_FORMAT_D16_XY_VBUFFER_OFFEN_exact anonymous_15037:{ *:[v2f16] }:$vdata, VGPR_32:{ *:[i32] }:$voffset, SReg_128:{ *:[v4i32] }:$rsrc, SCSrc_b32:{ *:[i32] }:$soffset, (timm:{ *:[i32] }):$offset, (as_i8timm:{ *:[i8] } ?:{ *:[i32] }:$format), (extract_cpol:{ *:[i32] } ?:{ *:[i32] }:$auxiliary), (extract_swz:{ *:[i1] } ?:{ *:[i32] }:$auxiliary))
        GIR_BuildMI, /*InsnID*/0, /*Opcode*/GIMT_Encode2(AMDGPU::TBUFFER_STORE_FORMAT_D16_XY_VBUFFER_OFFEN_exact),
        GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/0, // vdata
        GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/3, // voffset
        GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/1, // rsrc
        GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/0, // soffset
        GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/5, // offset
        GIR_CustomOperandRenderer, /*InsnID*/0, /*OldInsnID*/0, /*OpIdx*/6, /*OperandRenderer*/GIMT_Encode2(GICR_renderTruncTImm), // format
        GIR_CustomOperandRenderer, /*InsnID*/0, /*OldInsnID*/0, /*OpIdx*/7, /*OperandRenderer*/GIMT_Encode2(GICR_renderExtractCPol), // auxiliary
        GIR_CustomOperandRenderer, /*InsnID*/0, /*OldInsnID*/0, /*OpIdx*/7, /*OperandRenderer*/GIMT_Encode2(GICR_renderExtractSWZ), // auxiliary
        GIR_MergeMemOperands, /*InsnID*/0, /*NumInsns*/1, /*MergeInsnID's*/0,
        GIR_ConstrainSelectedInstOperands, /*InsnID*/0,
        GIR_EraseFromParent, /*InsnID*/0,
        // GIR_Coverage, 5799,
        GIR_Done,
      // Label 7469: @546840
      GIM_Try, /*On fail goto*//*Label 7470*/ GIMT_Encode4(546923), // Rule ID 5794 //
        GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasPackedD16VMem_HasUnrestrictedSOffset),
        GIM_CheckConstantInt8, /*MI*/0, /*Op*/3, 0,
        // MIs[0] offset
        GIM_CheckIsImm, /*MI*/0, /*Op*/5,
        // MIs[0] format
        GIM_CheckIsImm, /*MI*/0, /*Op*/6,
        // MIs[0] auxiliary
        GIM_CheckIsImm, /*MI*/0, /*Op*/7,
        // MIs[0] Operand 8
        GIM_CheckIsImm, /*MI*/0, /*Op*/8,
        GIM_CheckComplexPattern, /*MI*/0, /*Op*/4, /*Renderer*/GIMT_Encode2(0), GIMT_Encode2(GICP_gi_buf_soffset),
        // (SItbuffer_store_d16 v2f16:{ *:[v2f16] }:$vdata, v4i32:{ *:[v4i32] }:$rsrc, i32:{ *:[i32] }:$vindex, 0:{ *:[i32] }, (BUFSOffset:{ *:[i32] } i32:{ *:[i32] }:$soffset), (timm:{ *:[i32] }):$offset, (timm:{ *:[i32] }):$format, (timm:{ *:[i32] }):$auxiliary, (timm:{ *:[i1] }))  =>  (TBUFFER_STORE_FORMAT_D16_XY_IDXEN_exact anonymous_15037:{ *:[v2f16] }:$vdata, VGPR_32:{ *:[i32] }:$vindex, SReg_128:{ *:[v4i32] }:$rsrc, SCSrc_b32:{ *:[i32] }:$soffset, (timm:{ *:[i32] }):$offset, (as_i8timm:{ *:[i8] } ?:{ *:[i32] }:$format), (extract_cpol:{ *:[i32] } ?:{ *:[i32] }:$auxiliary), (extract_swz:{ *:[i1] } ?:{ *:[i32] }:$auxiliary))
        GIR_BuildMI, /*InsnID*/0, /*Opcode*/GIMT_Encode2(AMDGPU::TBUFFER_STORE_FORMAT_D16_XY_IDXEN_exact),
        GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/0, // vdata
        GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/2, // vindex
        GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/1, // rsrc
        GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/0, // soffset
        GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/5, // offset
        GIR_CustomOperandRenderer, /*InsnID*/0, /*OldInsnID*/0, /*OpIdx*/6, /*OperandRenderer*/GIMT_Encode2(GICR_renderTruncTImm), // format
        GIR_CustomOperandRenderer, /*InsnID*/0, /*OldInsnID*/0, /*OpIdx*/7, /*OperandRenderer*/GIMT_Encode2(GICR_renderExtractCPol), // auxiliary
        GIR_CustomOperandRenderer, /*InsnID*/0, /*OldInsnID*/0, /*OpIdx*/7, /*OperandRenderer*/GIMT_Encode2(GICR_renderExtractSWZ), // auxiliary
        GIR_MergeMemOperands, /*InsnID*/0, /*NumInsns*/1, /*MergeInsnID's*/0,
        GIR_ConstrainSelectedInstOperands, /*InsnID*/0,
        GIR_EraseFromParent, /*InsnID*/0,
        // GIR_Coverage, 5794,
        GIR_Done,
      // Label 7470: @546923
      GIM_Try, /*On fail goto*//*Label 7471*/ GIMT_Encode4(547006), // Rule ID 5798 //
        GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasPackedD16VMem),
        GIM_CheckConstantInt8, /*MI*/0, /*Op*/3, 0,
        // MIs[0] offset
        GIM_CheckIsImm, /*MI*/0, /*Op*/5,
        // MIs[0] format
        GIM_CheckIsImm, /*MI*/0, /*Op*/6,
        // MIs[0] auxiliary
        GIM_CheckIsImm, /*MI*/0, /*Op*/7,
        // MIs[0] Operand 8
        GIM_CheckIsImm, /*MI*/0, /*Op*/8,
        GIM_CheckComplexPattern, /*MI*/0, /*Op*/4, /*Renderer*/GIMT_Encode2(0), GIMT_Encode2(GICP_gi_buf_soffset),
        // (SItbuffer_store_d16 v2f16:{ *:[v2f16] }:$vdata, v4i32:{ *:[v4i32] }:$rsrc, i32:{ *:[i32] }:$vindex, 0:{ *:[i32] }, (BUFSOffset:{ *:[i32] } i32:{ *:[i32] }:$soffset), (timm:{ *:[i32] }):$offset, (timm:{ *:[i32] }):$format, (timm:{ *:[i32] }):$auxiliary, (timm:{ *:[i1] }))  =>  (TBUFFER_STORE_FORMAT_D16_XY_VBUFFER_IDXEN_exact anonymous_15037:{ *:[v2f16] }:$vdata, VGPR_32:{ *:[i32] }:$vindex, SReg_128:{ *:[v4i32] }:$rsrc, SCSrc_b32:{ *:[i32] }:$soffset, (timm:{ *:[i32] }):$offset, (as_i8timm:{ *:[i8] } ?:{ *:[i32] }:$format), (extract_cpol:{ *:[i32] } ?:{ *:[i32] }:$auxiliary), (extract_swz:{ *:[i1] } ?:{ *:[i32] }:$auxiliary))
        GIR_BuildMI, /*InsnID*/0, /*Opcode*/GIMT_Encode2(AMDGPU::TBUFFER_STORE_FORMAT_D16_XY_VBUFFER_IDXEN_exact),
        GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/0, // vdata
        GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/2, // vindex
        GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/1, // rsrc
        GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/0, // soffset
        GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/5, // offset
        GIR_CustomOperandRenderer, /*InsnID*/0, /*OldInsnID*/0, /*OpIdx*/6, /*OperandRenderer*/GIMT_Encode2(GICR_renderTruncTImm), // format
        GIR_CustomOperandRenderer, /*InsnID*/0, /*OldInsnID*/0, /*OpIdx*/7, /*OperandRenderer*/GIMT_Encode2(GICR_renderExtractCPol), // auxiliary
        GIR_CustomOperandRenderer, /*InsnID*/0, /*OldInsnID*/0, /*OpIdx*/7, /*OperandRenderer*/GIMT_Encode2(GICR_renderExtractSWZ), // auxiliary
        GIR_MergeMemOperands, /*InsnID*/0, /*NumInsns*/1, /*MergeInsnID's*/0,
        GIR_ConstrainSelectedInstOperands, /*InsnID*/0,
        GIR_EraseFromParent, /*InsnID*/0,
        // GIR_Coverage, 5798,
        GIR_Done,
      // Label 7471: @547006
      GIM_Try, /*On fail goto*//*Label 7472*/ GIMT_Encode4(547125), // Rule ID 5796 //
        GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasPackedD16VMem_HasUnrestrictedSOffset),
        // MIs[0] offset
        GIM_CheckIsImm, /*MI*/0, /*Op*/5,
        // MIs[0] format
        GIM_CheckIsImm, /*MI*/0, /*Op*/6,
        // MIs[0] auxiliary
        GIM_CheckIsImm, /*MI*/0, /*Op*/7,
        // MIs[0] Operand 8
        GIM_CheckIsImm, /*MI*/0, /*Op*/8,
        GIM_CheckComplexPattern, /*MI*/0, /*Op*/4, /*Renderer*/GIMT_Encode2(0), GIMT_Encode2(GICP_gi_buf_soffset),
        // (SItbuffer_store_d16 v2f16:{ *:[v2f16] }:$vdata, v4i32:{ *:[v4i32] }:$rsrc, i32:{ *:[i32] }:$vindex, i32:{ *:[i32] }:$voffset, (BUFSOffset:{ *:[i32] } i32:{ *:[i32] }:$soffset), (timm:{ *:[i32] }):$offset, (timm:{ *:[i32] }):$format, (timm:{ *:[i32] }):$auxiliary, (timm:{ *:[i1] }))  =>  (TBUFFER_STORE_FORMAT_D16_XY_BOTHEN_exact anonymous_15037:{ *:[v2f16] }:$vdata, (REG_SEQUENCE:{ *:[i64] } VReg_64:{ *:[i32] }, VGPR_32:{ *:[i32] }:$vindex, sub0:{ *:[i32] }, VGPR_32:{ *:[i32] }:$voffset, sub1:{ *:[i32] }), SReg_128:{ *:[v4i32] }:$rsrc, SCSrc_b32:{ *:[i32] }:$soffset, (timm:{ *:[i32] }):$offset, (as_i8timm:{ *:[i8] } ?:{ *:[i32] }:$format), (extract_cpol:{ *:[i32] } ?:{ *:[i32] }:$auxiliary), (extract_swz:{ *:[i1] } ?:{ *:[i32] }:$auxiliary))
        GIR_MakeTempReg, /*TempRegID*/0, /*TypeID*/GILLT_s64,
        GIR_BuildMI, /*InsnID*/1, /*Opcode*/GIMT_Encode2(TargetOpcode::REG_SEQUENCE),
        GIR_AddTempRegister, /*InsnID*/1, /*TempRegID*/0, /*TempRegFlags*/GIMT_Encode2(RegState::Define),
        GIR_Copy, /*NewInsnID*/1, /*OldInsnID*/0, /*OpIdx*/2, // vindex
        GIR_AddImm8, /*InsnID*/1, /*SubRegIndex*/3,
        GIR_Copy, /*NewInsnID*/1, /*OldInsnID*/0, /*OpIdx*/3, // voffset
        GIR_AddImm8, /*InsnID*/1, /*SubRegIndex*/11,
        GIR_ConstrainOperandRC, /*InsnID*/1, /*Op*/0, GIMT_Encode2(AMDGPU::VReg_64RegClassID),
        GIR_ConstrainOperandRC, /*InsnID*/1, /*Op*/1, GIMT_Encode2(AMDGPU::VGPR_32RegClassID),
        GIR_ConstrainOperandRC, /*InsnID*/1, /*Op*/3, GIMT_Encode2(AMDGPU::VGPR_32RegClassID),
        GIR_BuildMI, /*InsnID*/0, /*Opcode*/GIMT_Encode2(AMDGPU::TBUFFER_STORE_FORMAT_D16_XY_BOTHEN_exact),
        GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/0, // vdata
        GIR_AddSimpleTempRegister, /*InsnID*/0, /*TempRegID*/0,
        GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/1, // rsrc
        GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/0, // soffset
        GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/5, // offset
        GIR_CustomOperandRenderer, /*InsnID*/0, /*OldInsnID*/0, /*OpIdx*/6, /*OperandRenderer*/GIMT_Encode2(GICR_renderTruncTImm), // format
        GIR_CustomOperandRenderer, /*InsnID*/0, /*OldInsnID*/0, /*OpIdx*/7, /*OperandRenderer*/GIMT_Encode2(GICR_renderExtractCPol), // auxiliary
        GIR_CustomOperandRenderer, /*InsnID*/0, /*OldInsnID*/0, /*OpIdx*/7, /*OperandRenderer*/GIMT_Encode2(GICR_renderExtractSWZ), // auxiliary
        GIR_MergeMemOperands, /*InsnID*/0, /*NumInsns*/1, /*MergeInsnID's*/0,
        GIR_ConstrainSelectedInstOperands, /*InsnID*/0,
        GIR_EraseFromParent, /*InsnID*/0,
        // GIR_Coverage, 5796,
        GIR_Done,
      // Label 7472: @547125
      GIM_Try, /*On fail goto*//*Label 7473*/ GIMT_Encode4(547244), // Rule ID 5800 //
        GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasPackedD16VMem),
        // MIs[0] offset
        GIM_CheckIsImm, /*MI*/0, /*Op*/5,
        // MIs[0] format
        GIM_CheckIsImm, /*MI*/0, /*Op*/6,
        // MIs[0] auxiliary
        GIM_CheckIsImm, /*MI*/0, /*Op*/7,
        // MIs[0] Operand 8
        GIM_CheckIsImm, /*MI*/0, /*Op*/8,
        GIM_CheckComplexPattern, /*MI*/0, /*Op*/4, /*Renderer*/GIMT_Encode2(0), GIMT_Encode2(GICP_gi_buf_soffset),
        // (SItbuffer_store_d16 v2f16:{ *:[v2f16] }:$vdata, v4i32:{ *:[v4i32] }:$rsrc, i32:{ *:[i32] }:$vindex, i32:{ *:[i32] }:$voffset, (BUFSOffset:{ *:[i32] } i32:{ *:[i32] }:$soffset), (timm:{ *:[i32] }):$offset, (timm:{ *:[i32] }):$format, (timm:{ *:[i32] }):$auxiliary, (timm:{ *:[i1] }))  =>  (TBUFFER_STORE_FORMAT_D16_XY_VBUFFER_BOTHEN_exact anonymous_15037:{ *:[v2f16] }:$vdata, (REG_SEQUENCE:{ *:[i64] } VReg_64:{ *:[i32] }, VGPR_32:{ *:[i32] }:$vindex, sub0:{ *:[i32] }, VGPR_32:{ *:[i32] }:$voffset, sub1:{ *:[i32] }), SReg_128:{ *:[v4i32] }:$rsrc, SCSrc_b32:{ *:[i32] }:$soffset, (timm:{ *:[i32] }):$offset, (as_i8timm:{ *:[i8] } ?:{ *:[i32] }:$format), (extract_cpol:{ *:[i32] } ?:{ *:[i32] }:$auxiliary), (extract_swz:{ *:[i1] } ?:{ *:[i32] }:$auxiliary))
        GIR_MakeTempReg, /*TempRegID*/0, /*TypeID*/GILLT_s64,
        GIR_BuildMI, /*InsnID*/1, /*Opcode*/GIMT_Encode2(TargetOpcode::REG_SEQUENCE),
        GIR_AddTempRegister, /*InsnID*/1, /*TempRegID*/0, /*TempRegFlags*/GIMT_Encode2(RegState::Define),
        GIR_Copy, /*NewInsnID*/1, /*OldInsnID*/0, /*OpIdx*/2, // vindex
        GIR_AddImm8, /*InsnID*/1, /*SubRegIndex*/3,
        GIR_Copy, /*NewInsnID*/1, /*OldInsnID*/0, /*OpIdx*/3, // voffset
        GIR_AddImm8, /*InsnID*/1, /*SubRegIndex*/11,
        GIR_ConstrainOperandRC, /*InsnID*/1, /*Op*/0, GIMT_Encode2(AMDGPU::VReg_64RegClassID),
        GIR_ConstrainOperandRC, /*InsnID*/1, /*Op*/1, GIMT_Encode2(AMDGPU::VGPR_32RegClassID),
        GIR_ConstrainOperandRC, /*InsnID*/1, /*Op*/3, GIMT_Encode2(AMDGPU::VGPR_32RegClassID),
        GIR_BuildMI, /*InsnID*/0, /*Opcode*/GIMT_Encode2(AMDGPU::TBUFFER_STORE_FORMAT_D16_XY_VBUFFER_BOTHEN_exact),
        GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/0, // vdata
        GIR_AddSimpleTempRegister, /*InsnID*/0, /*TempRegID*/0,
        GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/1, // rsrc
        GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/0, // soffset
        GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/5, // offset
        GIR_CustomOperandRenderer, /*InsnID*/0, /*OldInsnID*/0, /*OpIdx*/6, /*OperandRenderer*/GIMT_Encode2(GICR_renderTruncTImm), // format
        GIR_CustomOperandRenderer, /*InsnID*/0, /*OldInsnID*/0, /*OpIdx*/7, /*OperandRenderer*/GIMT_Encode2(GICR_renderExtractCPol), // auxiliary
        GIR_CustomOperandRenderer, /*InsnID*/0, /*OldInsnID*/0, /*OpIdx*/7, /*OperandRenderer*/GIMT_Encode2(GICR_renderExtractSWZ), // auxiliary
        GIR_MergeMemOperands, /*InsnID*/0, /*NumInsns*/1, /*MergeInsnID's*/0,
        GIR_ConstrainSelectedInstOperands, /*InsnID*/0,
        GIR_EraseFromParent, /*InsnID*/0,
        // GIR_Coverage, 5800,
        GIR_Done,
      // Label 7473: @547244
      GIM_Reject,
    // Label 7465: @547245
    GIM_Reject,
    // Label 7434: @547246
    GIM_Try, /*On fail goto*//*Label 7474*/ GIMT_Encode4(547652),
      GIM_CheckType, /*MI*/0, /*Op*/1, /*Type*/GILLT_v4s32,
      GIM_CheckType, /*MI*/0, /*Op*/2, /*Type*/GILLT_s32,
      GIM_CheckType, /*MI*/0, /*Op*/3, /*Type*/GILLT_s32,
      GIM_CheckType, /*MI*/0, /*Op*/4, /*Type*/GILLT_s32,
      GIM_Try, /*On fail goto*//*Label 7475*/ GIMT_Encode4(547358), // Rule ID 5765 //
        GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasUnpackedD16VMem),
        GIM_CheckConstantInt8, /*MI*/0, /*Op*/2, 0,
        GIM_CheckConstantInt8, /*MI*/0, /*Op*/3, 0,
        // MIs[0] offset
        GIM_CheckIsImm, /*MI*/0, /*Op*/5,
        // MIs[0] format
        GIM_CheckIsImm, /*MI*/0, /*Op*/6,
        // MIs[0] auxiliary
        GIM_CheckIsImm, /*MI*/0, /*Op*/7,
        // MIs[0] Operand 8
        GIM_CheckLiteralInt, /*MI*/0, /*Op*/8, GIMT_Encode8(0),
        GIM_CheckComplexPattern, /*MI*/0, /*Op*/4, /*Renderer*/GIMT_Encode2(0), GIMT_Encode2(GICP_gi_buf_soffset),
        // (SItbuffer_store_d16 v2i32:{ *:[v2i32] }:$vdata, v4i32:{ *:[v4i32] }:$rsrc, 0:{ *:[i32] }, 0:{ *:[i32] }, (BUFSOffset:{ *:[i32] } i32:{ *:[i32] }:$soffset), (timm:{ *:[i32] }):$offset, (timm:{ *:[i32] }):$format, (timm:{ *:[i32] }):$auxiliary, 0:{ *:[i1] })  =>  (TBUFFER_STORE_FORMAT_D16_XY_gfx80_OFFSET_exact anonymous_15036:{ *:[v2i32] }:$vdata, SReg_128:{ *:[v4i32] }:$rsrc, SCSrc_b32:{ *:[i32] }:$soffset, (timm:{ *:[i32] }):$offset, (as_i8timm:{ *:[i8] } ?:{ *:[i32] }:$format), (extract_cpol:{ *:[i32] } ?:{ *:[i32] }:$auxiliary), (extract_swz:{ *:[i1] } ?:{ *:[i32] }:$auxiliary))
        GIR_BuildMI, /*InsnID*/0, /*Opcode*/GIMT_Encode2(AMDGPU::TBUFFER_STORE_FORMAT_D16_XY_gfx80_OFFSET_exact),
        GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/0, // vdata
        GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/1, // rsrc
        GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/0, // soffset
        GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/5, // offset
        GIR_CustomOperandRenderer, /*InsnID*/0, /*OldInsnID*/0, /*OpIdx*/6, /*OperandRenderer*/GIMT_Encode2(GICR_renderTruncTImm), // format
        GIR_CustomOperandRenderer, /*InsnID*/0, /*OldInsnID*/0, /*OpIdx*/7, /*OperandRenderer*/GIMT_Encode2(GICR_renderExtractCPol), // auxiliary
        GIR_CustomOperandRenderer, /*InsnID*/0, /*OldInsnID*/0, /*OpIdx*/7, /*OperandRenderer*/GIMT_Encode2(GICR_renderExtractSWZ), // auxiliary
        GIR_MergeMemOperands, /*InsnID*/0, /*NumInsns*/1, /*MergeInsnID's*/0,
        GIR_ConstrainSelectedInstOperands, /*InsnID*/0,
        GIR_EraseFromParent, /*InsnID*/0,
        // GIR_Coverage, 5765,
        GIR_Done,
      // Label 7475: @547358
      GIM_Try, /*On fail goto*//*Label 7476*/ GIMT_Encode4(547449), // Rule ID 5767 //
        GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasUnpackedD16VMem),
        GIM_CheckConstantInt8, /*MI*/0, /*Op*/2, 0,
        // MIs[0] offset
        GIM_CheckIsImm, /*MI*/0, /*Op*/5,
        // MIs[0] format
        GIM_CheckIsImm, /*MI*/0, /*Op*/6,
        // MIs[0] auxiliary
        GIM_CheckIsImm, /*MI*/0, /*Op*/7,
        // MIs[0] Operand 8
        GIM_CheckLiteralInt, /*MI*/0, /*Op*/8, GIMT_Encode8(0),
        GIM_CheckComplexPattern, /*MI*/0, /*Op*/4, /*Renderer*/GIMT_Encode2(0), GIMT_Encode2(GICP_gi_buf_soffset),
        // (SItbuffer_store_d16 v2i32:{ *:[v2i32] }:$vdata, v4i32:{ *:[v4i32] }:$rsrc, 0:{ *:[i32] }, i32:{ *:[i32] }:$voffset, (BUFSOffset:{ *:[i32] } i32:{ *:[i32] }:$soffset), (timm:{ *:[i32] }):$offset, (timm:{ *:[i32] }):$format, (timm:{ *:[i32] }):$auxiliary, 0:{ *:[i1] })  =>  (TBUFFER_STORE_FORMAT_D16_XY_gfx80_OFFEN_exact anonymous_15036:{ *:[v2i32] }:$vdata, VGPR_32:{ *:[i32] }:$voffset, SReg_128:{ *:[v4i32] }:$rsrc, SCSrc_b32:{ *:[i32] }:$soffset, (timm:{ *:[i32] }):$offset, (as_i8timm:{ *:[i8] } ?:{ *:[i32] }:$format), (extract_cpol:{ *:[i32] } ?:{ *:[i32] }:$auxiliary), (extract_swz:{ *:[i1] } ?:{ *:[i32] }:$auxiliary))
        GIR_BuildMI, /*InsnID*/0, /*Opcode*/GIMT_Encode2(AMDGPU::TBUFFER_STORE_FORMAT_D16_XY_gfx80_OFFEN_exact),
        GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/0, // vdata
        GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/3, // voffset
        GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/1, // rsrc
        GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/0, // soffset
        GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/5, // offset
        GIR_CustomOperandRenderer, /*InsnID*/0, /*OldInsnID*/0, /*OpIdx*/6, /*OperandRenderer*/GIMT_Encode2(GICR_renderTruncTImm), // format
        GIR_CustomOperandRenderer, /*InsnID*/0, /*OldInsnID*/0, /*OpIdx*/7, /*OperandRenderer*/GIMT_Encode2(GICR_renderExtractCPol), // auxiliary
        GIR_CustomOperandRenderer, /*InsnID*/0, /*OldInsnID*/0, /*OpIdx*/7, /*OperandRenderer*/GIMT_Encode2(GICR_renderExtractSWZ), // auxiliary
        GIR_MergeMemOperands, /*InsnID*/0, /*NumInsns*/1, /*MergeInsnID's*/0,
        GIR_ConstrainSelectedInstOperands, /*InsnID*/0,
        GIR_EraseFromParent, /*InsnID*/0,
        // GIR_Coverage, 5767,
        GIR_Done,
      // Label 7476: @547449
      GIM_Try, /*On fail goto*//*Label 7477*/ GIMT_Encode4(547532), // Rule ID 5766 //
        GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasUnpackedD16VMem),
        GIM_CheckConstantInt8, /*MI*/0, /*Op*/3, 0,
        // MIs[0] offset
        GIM_CheckIsImm, /*MI*/0, /*Op*/5,
        // MIs[0] format
        GIM_CheckIsImm, /*MI*/0, /*Op*/6,
        // MIs[0] auxiliary
        GIM_CheckIsImm, /*MI*/0, /*Op*/7,
        // MIs[0] Operand 8
        GIM_CheckIsImm, /*MI*/0, /*Op*/8,
        GIM_CheckComplexPattern, /*MI*/0, /*Op*/4, /*Renderer*/GIMT_Encode2(0), GIMT_Encode2(GICP_gi_buf_soffset),
        // (SItbuffer_store_d16 v2i32:{ *:[v2i32] }:$vdata, v4i32:{ *:[v4i32] }:$rsrc, i32:{ *:[i32] }:$vindex, 0:{ *:[i32] }, (BUFSOffset:{ *:[i32] } i32:{ *:[i32] }:$soffset), (timm:{ *:[i32] }):$offset, (timm:{ *:[i32] }):$format, (timm:{ *:[i32] }):$auxiliary, (timm:{ *:[i1] }))  =>  (TBUFFER_STORE_FORMAT_D16_XY_gfx80_IDXEN_exact anonymous_15036:{ *:[v2i32] }:$vdata, VGPR_32:{ *:[i32] }:$vindex, SReg_128:{ *:[v4i32] }:$rsrc, SCSrc_b32:{ *:[i32] }:$soffset, (timm:{ *:[i32] }):$offset, (as_i8timm:{ *:[i8] } ?:{ *:[i32] }:$format), (extract_cpol:{ *:[i32] } ?:{ *:[i32] }:$auxiliary), (extract_swz:{ *:[i1] } ?:{ *:[i32] }:$auxiliary))
        GIR_BuildMI, /*InsnID*/0, /*Opcode*/GIMT_Encode2(AMDGPU::TBUFFER_STORE_FORMAT_D16_XY_gfx80_IDXEN_exact),
        GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/0, // vdata
        GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/2, // vindex
        GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/1, // rsrc
        GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/0, // soffset
        GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/5, // offset
        GIR_CustomOperandRenderer, /*InsnID*/0, /*OldInsnID*/0, /*OpIdx*/6, /*OperandRenderer*/GIMT_Encode2(GICR_renderTruncTImm), // format
        GIR_CustomOperandRenderer, /*InsnID*/0, /*OldInsnID*/0, /*OpIdx*/7, /*OperandRenderer*/GIMT_Encode2(GICR_renderExtractCPol), // auxiliary
        GIR_CustomOperandRenderer, /*InsnID*/0, /*OldInsnID*/0, /*OpIdx*/7, /*OperandRenderer*/GIMT_Encode2(GICR_renderExtractSWZ), // auxiliary
        GIR_MergeMemOperands, /*InsnID*/0, /*NumInsns*/1, /*MergeInsnID's*/0,
        GIR_ConstrainSelectedInstOperands, /*InsnID*/0,
        GIR_EraseFromParent, /*InsnID*/0,
        // GIR_Coverage, 5766,
        GIR_Done,
      // Label 7477: @547532
      GIM_Try, /*On fail goto*//*Label 7478*/ GIMT_Encode4(547651), // Rule ID 5768 //
        GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasUnpackedD16VMem),
        // MIs[0] offset
        GIM_CheckIsImm, /*MI*/0, /*Op*/5,
        // MIs[0] format
        GIM_CheckIsImm, /*MI*/0, /*Op*/6,
        // MIs[0] auxiliary
        GIM_CheckIsImm, /*MI*/0, /*Op*/7,
        // MIs[0] Operand 8
        GIM_CheckIsImm, /*MI*/0, /*Op*/8,
        GIM_CheckComplexPattern, /*MI*/0, /*Op*/4, /*Renderer*/GIMT_Encode2(0), GIMT_Encode2(GICP_gi_buf_soffset),
        // (SItbuffer_store_d16 v2i32:{ *:[v2i32] }:$vdata, v4i32:{ *:[v4i32] }:$rsrc, i32:{ *:[i32] }:$vindex, i32:{ *:[i32] }:$voffset, (BUFSOffset:{ *:[i32] } i32:{ *:[i32] }:$soffset), (timm:{ *:[i32] }):$offset, (timm:{ *:[i32] }):$format, (timm:{ *:[i32] }):$auxiliary, (timm:{ *:[i1] }))  =>  (TBUFFER_STORE_FORMAT_D16_XY_gfx80_BOTHEN_exact anonymous_15036:{ *:[v2i32] }:$vdata, (REG_SEQUENCE:{ *:[i64] } VReg_64:{ *:[i32] }, VGPR_32:{ *:[i32] }:$vindex, sub0:{ *:[i32] }, VGPR_32:{ *:[i32] }:$voffset, sub1:{ *:[i32] }), SReg_128:{ *:[v4i32] }:$rsrc, SCSrc_b32:{ *:[i32] }:$soffset, (timm:{ *:[i32] }):$offset, (as_i8timm:{ *:[i8] } ?:{ *:[i32] }:$format), (extract_cpol:{ *:[i32] } ?:{ *:[i32] }:$auxiliary), (extract_swz:{ *:[i1] } ?:{ *:[i32] }:$auxiliary))
        GIR_MakeTempReg, /*TempRegID*/0, /*TypeID*/GILLT_s64,
        GIR_BuildMI, /*InsnID*/1, /*Opcode*/GIMT_Encode2(TargetOpcode::REG_SEQUENCE),
        GIR_AddTempRegister, /*InsnID*/1, /*TempRegID*/0, /*TempRegFlags*/GIMT_Encode2(RegState::Define),
        GIR_Copy, /*NewInsnID*/1, /*OldInsnID*/0, /*OpIdx*/2, // vindex
        GIR_AddImm8, /*InsnID*/1, /*SubRegIndex*/3,
        GIR_Copy, /*NewInsnID*/1, /*OldInsnID*/0, /*OpIdx*/3, // voffset
        GIR_AddImm8, /*InsnID*/1, /*SubRegIndex*/11,
        GIR_ConstrainOperandRC, /*InsnID*/1, /*Op*/0, GIMT_Encode2(AMDGPU::VReg_64RegClassID),
        GIR_ConstrainOperandRC, /*InsnID*/1, /*Op*/1, GIMT_Encode2(AMDGPU::VGPR_32RegClassID),
        GIR_ConstrainOperandRC, /*InsnID*/1, /*Op*/3, GIMT_Encode2(AMDGPU::VGPR_32RegClassID),
        GIR_BuildMI, /*InsnID*/0, /*Opcode*/GIMT_Encode2(AMDGPU::TBUFFER_STORE_FORMAT_D16_XY_gfx80_BOTHEN_exact),
        GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/0, // vdata
        GIR_AddSimpleTempRegister, /*InsnID*/0, /*TempRegID*/0,
        GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/1, // rsrc
        GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/0, // soffset
        GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/5, // offset
        GIR_CustomOperandRenderer, /*InsnID*/0, /*OldInsnID*/0, /*OpIdx*/6, /*OperandRenderer*/GIMT_Encode2(GICR_renderTruncTImm), // format
        GIR_CustomOperandRenderer, /*InsnID*/0, /*OldInsnID*/0, /*OpIdx*/7, /*OperandRenderer*/GIMT_Encode2(GICR_renderExtractCPol), // auxiliary
        GIR_CustomOperandRenderer, /*InsnID*/0, /*OldInsnID*/0, /*OpIdx*/7, /*OperandRenderer*/GIMT_Encode2(GICR_renderExtractSWZ), // auxiliary
        GIR_MergeMemOperands, /*InsnID*/0, /*NumInsns*/1, /*MergeInsnID's*/0,
        GIR_ConstrainSelectedInstOperands, /*InsnID*/0,
        GIR_EraseFromParent, /*InsnID*/0,
        // GIR_Coverage, 5768,
        GIR_Done,
      // Label 7478: @547651
      GIM_Reject,
    // Label 7474: @547652
    GIM_Reject,
    // Label 7435: @547653
    GIM_Try, /*On fail goto*//*Label 7479*/ GIMT_Encode4(548059),
      GIM_CheckType, /*MI*/0, /*Op*/1, /*Type*/GILLT_v4s32,
      GIM_CheckType, /*MI*/0, /*Op*/2, /*Type*/GILLT_s32,
      GIM_CheckType, /*MI*/0, /*Op*/3, /*Type*/GILLT_s32,
      GIM_CheckType, /*MI*/0, /*Op*/4, /*Type*/GILLT_s32,
      GIM_Try, /*On fail goto*//*Label 7480*/ GIMT_Encode4(547765), // Rule ID 5769 //
        GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasUnpackedD16VMem),
        GIM_CheckConstantInt8, /*MI*/0, /*Op*/2, 0,
        GIM_CheckConstantInt8, /*MI*/0, /*Op*/3, 0,
        // MIs[0] offset
        GIM_CheckIsImm, /*MI*/0, /*Op*/5,
        // MIs[0] format
        GIM_CheckIsImm, /*MI*/0, /*Op*/6,
        // MIs[0] auxiliary
        GIM_CheckIsImm, /*MI*/0, /*Op*/7,
        // MIs[0] Operand 8
        GIM_CheckLiteralInt, /*MI*/0, /*Op*/8, GIMT_Encode8(0),
        GIM_CheckComplexPattern, /*MI*/0, /*Op*/4, /*Renderer*/GIMT_Encode2(0), GIMT_Encode2(GICP_gi_buf_soffset),
        // (SItbuffer_store_d16 v3i32:{ *:[v3i32] }:$vdata, v4i32:{ *:[v4i32] }:$rsrc, 0:{ *:[i32] }, 0:{ *:[i32] }, (BUFSOffset:{ *:[i32] } i32:{ *:[i32] }:$soffset), (timm:{ *:[i32] }):$offset, (timm:{ *:[i32] }):$format, (timm:{ *:[i32] }):$auxiliary, 0:{ *:[i1] })  =>  (TBUFFER_STORE_FORMAT_D16_XYZ_gfx80_OFFSET_exact anonymous_15035:{ *:[v3i32] }:$vdata, SReg_128:{ *:[v4i32] }:$rsrc, SCSrc_b32:{ *:[i32] }:$soffset, (timm:{ *:[i32] }):$offset, (as_i8timm:{ *:[i8] } ?:{ *:[i32] }:$format), (extract_cpol:{ *:[i32] } ?:{ *:[i32] }:$auxiliary), (extract_swz:{ *:[i1] } ?:{ *:[i32] }:$auxiliary))
        GIR_BuildMI, /*InsnID*/0, /*Opcode*/GIMT_Encode2(AMDGPU::TBUFFER_STORE_FORMAT_D16_XYZ_gfx80_OFFSET_exact),
        GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/0, // vdata
        GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/1, // rsrc
        GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/0, // soffset
        GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/5, // offset
        GIR_CustomOperandRenderer, /*InsnID*/0, /*OldInsnID*/0, /*OpIdx*/6, /*OperandRenderer*/GIMT_Encode2(GICR_renderTruncTImm), // format
        GIR_CustomOperandRenderer, /*InsnID*/0, /*OldInsnID*/0, /*OpIdx*/7, /*OperandRenderer*/GIMT_Encode2(GICR_renderExtractCPol), // auxiliary
        GIR_CustomOperandRenderer, /*InsnID*/0, /*OldInsnID*/0, /*OpIdx*/7, /*OperandRenderer*/GIMT_Encode2(GICR_renderExtractSWZ), // auxiliary
        GIR_MergeMemOperands, /*InsnID*/0, /*NumInsns*/1, /*MergeInsnID's*/0,
        GIR_ConstrainSelectedInstOperands, /*InsnID*/0,
        GIR_EraseFromParent, /*InsnID*/0,
        // GIR_Coverage, 5769,
        GIR_Done,
      // Label 7480: @547765
      GIM_Try, /*On fail goto*//*Label 7481*/ GIMT_Encode4(547856), // Rule ID 5771 //
        GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasUnpackedD16VMem),
        GIM_CheckConstantInt8, /*MI*/0, /*Op*/2, 0,
        // MIs[0] offset
        GIM_CheckIsImm, /*MI*/0, /*Op*/5,
        // MIs[0] format
        GIM_CheckIsImm, /*MI*/0, /*Op*/6,
        // MIs[0] auxiliary
        GIM_CheckIsImm, /*MI*/0, /*Op*/7,
        // MIs[0] Operand 8
        GIM_CheckLiteralInt, /*MI*/0, /*Op*/8, GIMT_Encode8(0),
        GIM_CheckComplexPattern, /*MI*/0, /*Op*/4, /*Renderer*/GIMT_Encode2(0), GIMT_Encode2(GICP_gi_buf_soffset),
        // (SItbuffer_store_d16 v3i32:{ *:[v3i32] }:$vdata, v4i32:{ *:[v4i32] }:$rsrc, 0:{ *:[i32] }, i32:{ *:[i32] }:$voffset, (BUFSOffset:{ *:[i32] } i32:{ *:[i32] }:$soffset), (timm:{ *:[i32] }):$offset, (timm:{ *:[i32] }):$format, (timm:{ *:[i32] }):$auxiliary, 0:{ *:[i1] })  =>  (TBUFFER_STORE_FORMAT_D16_XYZ_gfx80_OFFEN_exact anonymous_15035:{ *:[v3i32] }:$vdata, VGPR_32:{ *:[i32] }:$voffset, SReg_128:{ *:[v4i32] }:$rsrc, SCSrc_b32:{ *:[i32] }:$soffset, (timm:{ *:[i32] }):$offset, (as_i8timm:{ *:[i8] } ?:{ *:[i32] }:$format), (extract_cpol:{ *:[i32] } ?:{ *:[i32] }:$auxiliary), (extract_swz:{ *:[i1] } ?:{ *:[i32] }:$auxiliary))
        GIR_BuildMI, /*InsnID*/0, /*Opcode*/GIMT_Encode2(AMDGPU::TBUFFER_STORE_FORMAT_D16_XYZ_gfx80_OFFEN_exact),
        GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/0, // vdata
        GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/3, // voffset
        GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/1, // rsrc
        GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/0, // soffset
        GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/5, // offset
        GIR_CustomOperandRenderer, /*InsnID*/0, /*OldInsnID*/0, /*OpIdx*/6, /*OperandRenderer*/GIMT_Encode2(GICR_renderTruncTImm), // format
        GIR_CustomOperandRenderer, /*InsnID*/0, /*OldInsnID*/0, /*OpIdx*/7, /*OperandRenderer*/GIMT_Encode2(GICR_renderExtractCPol), // auxiliary
        GIR_CustomOperandRenderer, /*InsnID*/0, /*OldInsnID*/0, /*OpIdx*/7, /*OperandRenderer*/GIMT_Encode2(GICR_renderExtractSWZ), // auxiliary
        GIR_MergeMemOperands, /*InsnID*/0, /*NumInsns*/1, /*MergeInsnID's*/0,
        GIR_ConstrainSelectedInstOperands, /*InsnID*/0,
        GIR_EraseFromParent, /*InsnID*/0,
        // GIR_Coverage, 5771,
        GIR_Done,
      // Label 7481: @547856
      GIM_Try, /*On fail goto*//*Label 7482*/ GIMT_Encode4(547939), // Rule ID 5770 //
        GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasUnpackedD16VMem),
        GIM_CheckConstantInt8, /*MI*/0, /*Op*/3, 0,
        // MIs[0] offset
        GIM_CheckIsImm, /*MI*/0, /*Op*/5,
        // MIs[0] format
        GIM_CheckIsImm, /*MI*/0, /*Op*/6,
        // MIs[0] auxiliary
        GIM_CheckIsImm, /*MI*/0, /*Op*/7,
        // MIs[0] Operand 8
        GIM_CheckIsImm, /*MI*/0, /*Op*/8,
        GIM_CheckComplexPattern, /*MI*/0, /*Op*/4, /*Renderer*/GIMT_Encode2(0), GIMT_Encode2(GICP_gi_buf_soffset),
        // (SItbuffer_store_d16 v3i32:{ *:[v3i32] }:$vdata, v4i32:{ *:[v4i32] }:$rsrc, i32:{ *:[i32] }:$vindex, 0:{ *:[i32] }, (BUFSOffset:{ *:[i32] } i32:{ *:[i32] }:$soffset), (timm:{ *:[i32] }):$offset, (timm:{ *:[i32] }):$format, (timm:{ *:[i32] }):$auxiliary, (timm:{ *:[i1] }))  =>  (TBUFFER_STORE_FORMAT_D16_XYZ_gfx80_IDXEN_exact anonymous_15035:{ *:[v3i32] }:$vdata, VGPR_32:{ *:[i32] }:$vindex, SReg_128:{ *:[v4i32] }:$rsrc, SCSrc_b32:{ *:[i32] }:$soffset, (timm:{ *:[i32] }):$offset, (as_i8timm:{ *:[i8] } ?:{ *:[i32] }:$format), (extract_cpol:{ *:[i32] } ?:{ *:[i32] }:$auxiliary), (extract_swz:{ *:[i1] } ?:{ *:[i32] }:$auxiliary))
        GIR_BuildMI, /*InsnID*/0, /*Opcode*/GIMT_Encode2(AMDGPU::TBUFFER_STORE_FORMAT_D16_XYZ_gfx80_IDXEN_exact),
        GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/0, // vdata
        GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/2, // vindex
        GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/1, // rsrc
        GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/0, // soffset
        GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/5, // offset
        GIR_CustomOperandRenderer, /*InsnID*/0, /*OldInsnID*/0, /*OpIdx*/6, /*OperandRenderer*/GIMT_Encode2(GICR_renderTruncTImm), // format
        GIR_CustomOperandRenderer, /*InsnID*/0, /*OldInsnID*/0, /*OpIdx*/7, /*OperandRenderer*/GIMT_Encode2(GICR_renderExtractCPol), // auxiliary
        GIR_CustomOperandRenderer, /*InsnID*/0, /*OldInsnID*/0, /*OpIdx*/7, /*OperandRenderer*/GIMT_Encode2(GICR_renderExtractSWZ), // auxiliary
        GIR_MergeMemOperands, /*InsnID*/0, /*NumInsns*/1, /*MergeInsnID's*/0,
        GIR_ConstrainSelectedInstOperands, /*InsnID*/0,
        GIR_EraseFromParent, /*InsnID*/0,
        // GIR_Coverage, 5770,
        GIR_Done,
      // Label 7482: @547939
      GIM_Try, /*On fail goto*//*Label 7483*/ GIMT_Encode4(548058), // Rule ID 5772 //
        GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasUnpackedD16VMem),
        // MIs[0] offset
        GIM_CheckIsImm, /*MI*/0, /*Op*/5,
        // MIs[0] format
        GIM_CheckIsImm, /*MI*/0, /*Op*/6,
        // MIs[0] auxiliary
        GIM_CheckIsImm, /*MI*/0, /*Op*/7,
        // MIs[0] Operand 8
        GIM_CheckIsImm, /*MI*/0, /*Op*/8,
        GIM_CheckComplexPattern, /*MI*/0, /*Op*/4, /*Renderer*/GIMT_Encode2(0), GIMT_Encode2(GICP_gi_buf_soffset),
        // (SItbuffer_store_d16 v3i32:{ *:[v3i32] }:$vdata, v4i32:{ *:[v4i32] }:$rsrc, i32:{ *:[i32] }:$vindex, i32:{ *:[i32] }:$voffset, (BUFSOffset:{ *:[i32] } i32:{ *:[i32] }:$soffset), (timm:{ *:[i32] }):$offset, (timm:{ *:[i32] }):$format, (timm:{ *:[i32] }):$auxiliary, (timm:{ *:[i1] }))  =>  (TBUFFER_STORE_FORMAT_D16_XYZ_gfx80_BOTHEN_exact anonymous_15035:{ *:[v3i32] }:$vdata, (REG_SEQUENCE:{ *:[i64] } VReg_64:{ *:[i32] }, VGPR_32:{ *:[i32] }:$vindex, sub0:{ *:[i32] }, VGPR_32:{ *:[i32] }:$voffset, sub1:{ *:[i32] }), SReg_128:{ *:[v4i32] }:$rsrc, SCSrc_b32:{ *:[i32] }:$soffset, (timm:{ *:[i32] }):$offset, (as_i8timm:{ *:[i8] } ?:{ *:[i32] }:$format), (extract_cpol:{ *:[i32] } ?:{ *:[i32] }:$auxiliary), (extract_swz:{ *:[i1] } ?:{ *:[i32] }:$auxiliary))
        GIR_MakeTempReg, /*TempRegID*/0, /*TypeID*/GILLT_s64,
        GIR_BuildMI, /*InsnID*/1, /*Opcode*/GIMT_Encode2(TargetOpcode::REG_SEQUENCE),
        GIR_AddTempRegister, /*InsnID*/1, /*TempRegID*/0, /*TempRegFlags*/GIMT_Encode2(RegState::Define),
        GIR_Copy, /*NewInsnID*/1, /*OldInsnID*/0, /*OpIdx*/2, // vindex
        GIR_AddImm8, /*InsnID*/1, /*SubRegIndex*/3,
        GIR_Copy, /*NewInsnID*/1, /*OldInsnID*/0, /*OpIdx*/3, // voffset
        GIR_AddImm8, /*InsnID*/1, /*SubRegIndex*/11,
        GIR_ConstrainOperandRC, /*InsnID*/1, /*Op*/0, GIMT_Encode2(AMDGPU::VReg_64RegClassID),
        GIR_ConstrainOperandRC, /*InsnID*/1, /*Op*/1, GIMT_Encode2(AMDGPU::VGPR_32RegClassID),
        GIR_ConstrainOperandRC, /*InsnID*/1, /*Op*/3, GIMT_Encode2(AMDGPU::VGPR_32RegClassID),
        GIR_BuildMI, /*InsnID*/0, /*Opcode*/GIMT_Encode2(AMDGPU::TBUFFER_STORE_FORMAT_D16_XYZ_gfx80_BOTHEN_exact),
        GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/0, // vdata
        GIR_AddSimpleTempRegister, /*InsnID*/0, /*TempRegID*/0,
        GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/1, // rsrc
        GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/0, // soffset
        GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/5, // offset
        GIR_CustomOperandRenderer, /*InsnID*/0, /*OldInsnID*/0, /*OpIdx*/6, /*OperandRenderer*/GIMT_Encode2(GICR_renderTruncTImm), // format
        GIR_CustomOperandRenderer, /*InsnID*/0, /*OldInsnID*/0, /*OpIdx*/7, /*OperandRenderer*/GIMT_Encode2(GICR_renderExtractCPol), // auxiliary
        GIR_CustomOperandRenderer, /*InsnID*/0, /*OldInsnID*/0, /*OpIdx*/7, /*OperandRenderer*/GIMT_Encode2(GICR_renderExtractSWZ), // auxiliary
        GIR_MergeMemOperands, /*InsnID*/0, /*NumInsns*/1, /*MergeInsnID's*/0,
        GIR_ConstrainSelectedInstOperands, /*InsnID*/0,
        GIR_EraseFromParent, /*InsnID*/0,
        // GIR_Coverage, 5772,
        GIR_Done,
      // Label 7483: @548058
      GIM_Reject,
    // Label 7479: @548059
    GIM_Reject,
    // Label 7436: @548060
    GIM_Try, /*On fail goto*//*Label 7484*/ GIMT_Encode4(548850),
      GIM_CheckType, /*MI*/0, /*Op*/1, /*Type*/GILLT_v4s32,
      GIM_CheckType, /*MI*/0, /*Op*/2, /*Type*/GILLT_s32,
      GIM_CheckType, /*MI*/0, /*Op*/3, /*Type*/GILLT_s32,
      GIM_CheckType, /*MI*/0, /*Op*/4, /*Type*/GILLT_s32,
      GIM_Try, /*On fail goto*//*Label 7485*/ GIMT_Encode4(548172), // Rule ID 5809 //
        GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasPackedD16VMem_HasUnrestrictedSOffset),
        GIM_CheckConstantInt8, /*MI*/0, /*Op*/2, 0,
        GIM_CheckConstantInt8, /*MI*/0, /*Op*/3, 0,
        // MIs[0] offset
        GIM_CheckIsImm, /*MI*/0, /*Op*/5,
        // MIs[0] format
        GIM_CheckIsImm, /*MI*/0, /*Op*/6,
        // MIs[0] auxiliary
        GIM_CheckIsImm, /*MI*/0, /*Op*/7,
        // MIs[0] Operand 8
        GIM_CheckLiteralInt, /*MI*/0, /*Op*/8, GIMT_Encode8(0),
        GIM_CheckComplexPattern, /*MI*/0, /*Op*/4, /*Renderer*/GIMT_Encode2(0), GIMT_Encode2(GICP_gi_buf_soffset),
        // (SItbuffer_store_d16 v4f16:{ *:[v4f16] }:$vdata, v4i32:{ *:[v4i32] }:$rsrc, 0:{ *:[i32] }, 0:{ *:[i32] }, (BUFSOffset:{ *:[i32] } i32:{ *:[i32] }:$soffset), (timm:{ *:[i32] }):$offset, (timm:{ *:[i32] }):$format, (timm:{ *:[i32] }):$auxiliary, 0:{ *:[i1] })  =>  (TBUFFER_STORE_FORMAT_D16_XYZW_OFFSET_exact anonymous_15036:{ *:[v4f16] }:$vdata, SReg_128:{ *:[v4i32] }:$rsrc, SCSrc_b32:{ *:[i32] }:$soffset, (timm:{ *:[i32] }):$offset, (as_i8timm:{ *:[i8] } ?:{ *:[i32] }:$format), (extract_cpol:{ *:[i32] } ?:{ *:[i32] }:$auxiliary), (extract_swz:{ *:[i1] } ?:{ *:[i32] }:$auxiliary))
        GIR_BuildMI, /*InsnID*/0, /*Opcode*/GIMT_Encode2(AMDGPU::TBUFFER_STORE_FORMAT_D16_XYZW_OFFSET_exact),
        GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/0, // vdata
        GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/1, // rsrc
        GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/0, // soffset
        GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/5, // offset
        GIR_CustomOperandRenderer, /*InsnID*/0, /*OldInsnID*/0, /*OpIdx*/6, /*OperandRenderer*/GIMT_Encode2(GICR_renderTruncTImm), // format
        GIR_CustomOperandRenderer, /*InsnID*/0, /*OldInsnID*/0, /*OpIdx*/7, /*OperandRenderer*/GIMT_Encode2(GICR_renderExtractCPol), // auxiliary
        GIR_CustomOperandRenderer, /*InsnID*/0, /*OldInsnID*/0, /*OpIdx*/7, /*OperandRenderer*/GIMT_Encode2(GICR_renderExtractSWZ), // auxiliary
        GIR_MergeMemOperands, /*InsnID*/0, /*NumInsns*/1, /*MergeInsnID's*/0,
        GIR_ConstrainSelectedInstOperands, /*InsnID*/0,
        GIR_EraseFromParent, /*InsnID*/0,
        // GIR_Coverage, 5809,
        GIR_Done,
      // Label 7485: @548172
      GIM_Try, /*On fail goto*//*Label 7486*/ GIMT_Encode4(548263), // Rule ID 5813 //
        GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasPackedD16VMem),
        GIM_CheckConstantInt8, /*MI*/0, /*Op*/2, 0,
        GIM_CheckConstantInt8, /*MI*/0, /*Op*/3, 0,
        // MIs[0] offset
        GIM_CheckIsImm, /*MI*/0, /*Op*/5,
        // MIs[0] format
        GIM_CheckIsImm, /*MI*/0, /*Op*/6,
        // MIs[0] auxiliary
        GIM_CheckIsImm, /*MI*/0, /*Op*/7,
        // MIs[0] Operand 8
        GIM_CheckLiteralInt, /*MI*/0, /*Op*/8, GIMT_Encode8(0),
        GIM_CheckComplexPattern, /*MI*/0, /*Op*/4, /*Renderer*/GIMT_Encode2(0), GIMT_Encode2(GICP_gi_buf_soffset),
        // (SItbuffer_store_d16 v4f16:{ *:[v4f16] }:$vdata, v4i32:{ *:[v4i32] }:$rsrc, 0:{ *:[i32] }, 0:{ *:[i32] }, (BUFSOffset:{ *:[i32] } i32:{ *:[i32] }:$soffset), (timm:{ *:[i32] }):$offset, (timm:{ *:[i32] }):$format, (timm:{ *:[i32] }):$auxiliary, 0:{ *:[i1] })  =>  (TBUFFER_STORE_FORMAT_D16_XYZW_VBUFFER_OFFSET_exact anonymous_15036:{ *:[v4f16] }:$vdata, SReg_128:{ *:[v4i32] }:$rsrc, SCSrc_b32:{ *:[i32] }:$soffset, (timm:{ *:[i32] }):$offset, (as_i8timm:{ *:[i8] } ?:{ *:[i32] }:$format), (extract_cpol:{ *:[i32] } ?:{ *:[i32] }:$auxiliary), (extract_swz:{ *:[i1] } ?:{ *:[i32] }:$auxiliary))
        GIR_BuildMI, /*InsnID*/0, /*Opcode*/GIMT_Encode2(AMDGPU::TBUFFER_STORE_FORMAT_D16_XYZW_VBUFFER_OFFSET_exact),
        GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/0, // vdata
        GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/1, // rsrc
        GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/0, // soffset
        GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/5, // offset
        GIR_CustomOperandRenderer, /*InsnID*/0, /*OldInsnID*/0, /*OpIdx*/6, /*OperandRenderer*/GIMT_Encode2(GICR_renderTruncTImm), // format
        GIR_CustomOperandRenderer, /*InsnID*/0, /*OldInsnID*/0, /*OpIdx*/7, /*OperandRenderer*/GIMT_Encode2(GICR_renderExtractCPol), // auxiliary
        GIR_CustomOperandRenderer, /*InsnID*/0, /*OldInsnID*/0, /*OpIdx*/7, /*OperandRenderer*/GIMT_Encode2(GICR_renderExtractSWZ), // auxiliary
        GIR_MergeMemOperands, /*InsnID*/0, /*NumInsns*/1, /*MergeInsnID's*/0,
        GIR_ConstrainSelectedInstOperands, /*InsnID*/0,
        GIR_EraseFromParent, /*InsnID*/0,
        // GIR_Coverage, 5813,
        GIR_Done,
      // Label 7486: @548263
      GIM_Try, /*On fail goto*//*Label 7487*/ GIMT_Encode4(548354), // Rule ID 5811 //
        GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasPackedD16VMem_HasUnrestrictedSOffset),
        GIM_CheckConstantInt8, /*MI*/0, /*Op*/2, 0,
        // MIs[0] offset
        GIM_CheckIsImm, /*MI*/0, /*Op*/5,
        // MIs[0] format
        GIM_CheckIsImm, /*MI*/0, /*Op*/6,
        // MIs[0] auxiliary
        GIM_CheckIsImm, /*MI*/0, /*Op*/7,
        // MIs[0] Operand 8
        GIM_CheckLiteralInt, /*MI*/0, /*Op*/8, GIMT_Encode8(0),
        GIM_CheckComplexPattern, /*MI*/0, /*Op*/4, /*Renderer*/GIMT_Encode2(0), GIMT_Encode2(GICP_gi_buf_soffset),
        // (SItbuffer_store_d16 v4f16:{ *:[v4f16] }:$vdata, v4i32:{ *:[v4i32] }:$rsrc, 0:{ *:[i32] }, i32:{ *:[i32] }:$voffset, (BUFSOffset:{ *:[i32] } i32:{ *:[i32] }:$soffset), (timm:{ *:[i32] }):$offset, (timm:{ *:[i32] }):$format, (timm:{ *:[i32] }):$auxiliary, 0:{ *:[i1] })  =>  (TBUFFER_STORE_FORMAT_D16_XYZW_OFFEN_exact anonymous_15036:{ *:[v4f16] }:$vdata, VGPR_32:{ *:[i32] }:$voffset, SReg_128:{ *:[v4i32] }:$rsrc, SCSrc_b32:{ *:[i32] }:$soffset, (timm:{ *:[i32] }):$offset, (as_i8timm:{ *:[i8] } ?:{ *:[i32] }:$format), (extract_cpol:{ *:[i32] } ?:{ *:[i32] }:$auxiliary), (extract_swz:{ *:[i1] } ?:{ *:[i32] }:$auxiliary))
        GIR_BuildMI, /*InsnID*/0, /*Opcode*/GIMT_Encode2(AMDGPU::TBUFFER_STORE_FORMAT_D16_XYZW_OFFEN_exact),
        GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/0, // vdata
        GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/3, // voffset
        GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/1, // rsrc
        GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/0, // soffset
        GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/5, // offset
        GIR_CustomOperandRenderer, /*InsnID*/0, /*OldInsnID*/0, /*OpIdx*/6, /*OperandRenderer*/GIMT_Encode2(GICR_renderTruncTImm), // format
        GIR_CustomOperandRenderer, /*InsnID*/0, /*OldInsnID*/0, /*OpIdx*/7, /*OperandRenderer*/GIMT_Encode2(GICR_renderExtractCPol), // auxiliary
        GIR_CustomOperandRenderer, /*InsnID*/0, /*OldInsnID*/0, /*OpIdx*/7, /*OperandRenderer*/GIMT_Encode2(GICR_renderExtractSWZ), // auxiliary
        GIR_MergeMemOperands, /*InsnID*/0, /*NumInsns*/1, /*MergeInsnID's*/0,
        GIR_ConstrainSelectedInstOperands, /*InsnID*/0,
        GIR_EraseFromParent, /*InsnID*/0,
        // GIR_Coverage, 5811,
        GIR_Done,
      // Label 7487: @548354
      GIM_Try, /*On fail goto*//*Label 7488*/ GIMT_Encode4(548445), // Rule ID 5815 //
        GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasPackedD16VMem),
        GIM_CheckConstantInt8, /*MI*/0, /*Op*/2, 0,
        // MIs[0] offset
        GIM_CheckIsImm, /*MI*/0, /*Op*/5,
        // MIs[0] format
        GIM_CheckIsImm, /*MI*/0, /*Op*/6,
        // MIs[0] auxiliary
        GIM_CheckIsImm, /*MI*/0, /*Op*/7,
        // MIs[0] Operand 8
        GIM_CheckLiteralInt, /*MI*/0, /*Op*/8, GIMT_Encode8(0),
        GIM_CheckComplexPattern, /*MI*/0, /*Op*/4, /*Renderer*/GIMT_Encode2(0), GIMT_Encode2(GICP_gi_buf_soffset),
        // (SItbuffer_store_d16 v4f16:{ *:[v4f16] }:$vdata, v4i32:{ *:[v4i32] }:$rsrc, 0:{ *:[i32] }, i32:{ *:[i32] }:$voffset, (BUFSOffset:{ *:[i32] } i32:{ *:[i32] }:$soffset), (timm:{ *:[i32] }):$offset, (timm:{ *:[i32] }):$format, (timm:{ *:[i32] }):$auxiliary, 0:{ *:[i1] })  =>  (TBUFFER_STORE_FORMAT_D16_XYZW_VBUFFER_OFFEN_exact anonymous_15036:{ *:[v4f16] }:$vdata, VGPR_32:{ *:[i32] }:$voffset, SReg_128:{ *:[v4i32] }:$rsrc, SCSrc_b32:{ *:[i32] }:$soffset, (timm:{ *:[i32] }):$offset, (as_i8timm:{ *:[i8] } ?:{ *:[i32] }:$format), (extract_cpol:{ *:[i32] } ?:{ *:[i32] }:$auxiliary), (extract_swz:{ *:[i1] } ?:{ *:[i32] }:$auxiliary))
        GIR_BuildMI, /*InsnID*/0, /*Opcode*/GIMT_Encode2(AMDGPU::TBUFFER_STORE_FORMAT_D16_XYZW_VBUFFER_OFFEN_exact),
        GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/0, // vdata
        GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/3, // voffset
        GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/1, // rsrc
        GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/0, // soffset
        GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/5, // offset
        GIR_CustomOperandRenderer, /*InsnID*/0, /*OldInsnID*/0, /*OpIdx*/6, /*OperandRenderer*/GIMT_Encode2(GICR_renderTruncTImm), // format
        GIR_CustomOperandRenderer, /*InsnID*/0, /*OldInsnID*/0, /*OpIdx*/7, /*OperandRenderer*/GIMT_Encode2(GICR_renderExtractCPol), // auxiliary
        GIR_CustomOperandRenderer, /*InsnID*/0, /*OldInsnID*/0, /*OpIdx*/7, /*OperandRenderer*/GIMT_Encode2(GICR_renderExtractSWZ), // auxiliary
        GIR_MergeMemOperands, /*InsnID*/0, /*NumInsns*/1, /*MergeInsnID's*/0,
        GIR_ConstrainSelectedInstOperands, /*InsnID*/0,
        GIR_EraseFromParent, /*InsnID*/0,
        // GIR_Coverage, 5815,
        GIR_Done,
      // Label 7488: @548445
      GIM_Try, /*On fail goto*//*Label 7489*/ GIMT_Encode4(548528), // Rule ID 5810 //
        GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasPackedD16VMem_HasUnrestrictedSOffset),
        GIM_CheckConstantInt8, /*MI*/0, /*Op*/3, 0,
        // MIs[0] offset
        GIM_CheckIsImm, /*MI*/0, /*Op*/5,
        // MIs[0] format
        GIM_CheckIsImm, /*MI*/0, /*Op*/6,
        // MIs[0] auxiliary
        GIM_CheckIsImm, /*MI*/0, /*Op*/7,
        // MIs[0] Operand 8
        GIM_CheckIsImm, /*MI*/0, /*Op*/8,
        GIM_CheckComplexPattern, /*MI*/0, /*Op*/4, /*Renderer*/GIMT_Encode2(0), GIMT_Encode2(GICP_gi_buf_soffset),
        // (SItbuffer_store_d16 v4f16:{ *:[v4f16] }:$vdata, v4i32:{ *:[v4i32] }:$rsrc, i32:{ *:[i32] }:$vindex, 0:{ *:[i32] }, (BUFSOffset:{ *:[i32] } i32:{ *:[i32] }:$soffset), (timm:{ *:[i32] }):$offset, (timm:{ *:[i32] }):$format, (timm:{ *:[i32] }):$auxiliary, (timm:{ *:[i1] }))  =>  (TBUFFER_STORE_FORMAT_D16_XYZW_IDXEN_exact anonymous_15036:{ *:[v4f16] }:$vdata, VGPR_32:{ *:[i32] }:$vindex, SReg_128:{ *:[v4i32] }:$rsrc, SCSrc_b32:{ *:[i32] }:$soffset, (timm:{ *:[i32] }):$offset, (as_i8timm:{ *:[i8] } ?:{ *:[i32] }:$format), (extract_cpol:{ *:[i32] } ?:{ *:[i32] }:$auxiliary), (extract_swz:{ *:[i1] } ?:{ *:[i32] }:$auxiliary))
        GIR_BuildMI, /*InsnID*/0, /*Opcode*/GIMT_Encode2(AMDGPU::TBUFFER_STORE_FORMAT_D16_XYZW_IDXEN_exact),
        GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/0, // vdata
        GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/2, // vindex
        GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/1, // rsrc
        GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/0, // soffset
        GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/5, // offset
        GIR_CustomOperandRenderer, /*InsnID*/0, /*OldInsnID*/0, /*OpIdx*/6, /*OperandRenderer*/GIMT_Encode2(GICR_renderTruncTImm), // format
        GIR_CustomOperandRenderer, /*InsnID*/0, /*OldInsnID*/0, /*OpIdx*/7, /*OperandRenderer*/GIMT_Encode2(GICR_renderExtractCPol), // auxiliary
        GIR_CustomOperandRenderer, /*InsnID*/0, /*OldInsnID*/0, /*OpIdx*/7, /*OperandRenderer*/GIMT_Encode2(GICR_renderExtractSWZ), // auxiliary
        GIR_MergeMemOperands, /*InsnID*/0, /*NumInsns*/1, /*MergeInsnID's*/0,
        GIR_ConstrainSelectedInstOperands, /*InsnID*/0,
        GIR_EraseFromParent, /*InsnID*/0,
        // GIR_Coverage, 5810,
        GIR_Done,
      // Label 7489: @548528
      GIM_Try, /*On fail goto*//*Label 7490*/ GIMT_Encode4(548611), // Rule ID 5814 //
        GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasPackedD16VMem),
        GIM_CheckConstantInt8, /*MI*/0, /*Op*/3, 0,
        // MIs[0] offset
        GIM_CheckIsImm, /*MI*/0, /*Op*/5,
        // MIs[0] format
        GIM_CheckIsImm, /*MI*/0, /*Op*/6,
        // MIs[0] auxiliary
        GIM_CheckIsImm, /*MI*/0, /*Op*/7,
        // MIs[0] Operand 8
        GIM_CheckIsImm, /*MI*/0, /*Op*/8,
        GIM_CheckComplexPattern, /*MI*/0, /*Op*/4, /*Renderer*/GIMT_Encode2(0), GIMT_Encode2(GICP_gi_buf_soffset),
        // (SItbuffer_store_d16 v4f16:{ *:[v4f16] }:$vdata, v4i32:{ *:[v4i32] }:$rsrc, i32:{ *:[i32] }:$vindex, 0:{ *:[i32] }, (BUFSOffset:{ *:[i32] } i32:{ *:[i32] }:$soffset), (timm:{ *:[i32] }):$offset, (timm:{ *:[i32] }):$format, (timm:{ *:[i32] }):$auxiliary, (timm:{ *:[i1] }))  =>  (TBUFFER_STORE_FORMAT_D16_XYZW_VBUFFER_IDXEN_exact anonymous_15036:{ *:[v4f16] }:$vdata, VGPR_32:{ *:[i32] }:$vindex, SReg_128:{ *:[v4i32] }:$rsrc, SCSrc_b32:{ *:[i32] }:$soffset, (timm:{ *:[i32] }):$offset, (as_i8timm:{ *:[i8] } ?:{ *:[i32] }:$format), (extract_cpol:{ *:[i32] } ?:{ *:[i32] }:$auxiliary), (extract_swz:{ *:[i1] } ?:{ *:[i32] }:$auxiliary))
        GIR_BuildMI, /*InsnID*/0, /*Opcode*/GIMT_Encode2(AMDGPU::TBUFFER_STORE_FORMAT_D16_XYZW_VBUFFER_IDXEN_exact),
        GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/0, // vdata
        GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/2, // vindex
        GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/1, // rsrc
        GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/0, // soffset
        GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/5, // offset
        GIR_CustomOperandRenderer, /*InsnID*/0, /*OldInsnID*/0, /*OpIdx*/6, /*OperandRenderer*/GIMT_Encode2(GICR_renderTruncTImm), // format
        GIR_CustomOperandRenderer, /*InsnID*/0, /*OldInsnID*/0, /*OpIdx*/7, /*OperandRenderer*/GIMT_Encode2(GICR_renderExtractCPol), // auxiliary
        GIR_CustomOperandRenderer, /*InsnID*/0, /*OldInsnID*/0, /*OpIdx*/7, /*OperandRenderer*/GIMT_Encode2(GICR_renderExtractSWZ), // auxiliary
        GIR_MergeMemOperands, /*InsnID*/0, /*NumInsns*/1, /*MergeInsnID's*/0,
        GIR_ConstrainSelectedInstOperands, /*InsnID*/0,
        GIR_EraseFromParent, /*InsnID*/0,
        // GIR_Coverage, 5814,
        GIR_Done,
      // Label 7490: @548611
      GIM_Try, /*On fail goto*//*Label 7491*/ GIMT_Encode4(548730), // Rule ID 5812 //
        GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasPackedD16VMem_HasUnrestrictedSOffset),
        // MIs[0] offset
        GIM_CheckIsImm, /*MI*/0, /*Op*/5,
        // MIs[0] format
        GIM_CheckIsImm, /*MI*/0, /*Op*/6,
        // MIs[0] auxiliary
        GIM_CheckIsImm, /*MI*/0, /*Op*/7,
        // MIs[0] Operand 8
        GIM_CheckIsImm, /*MI*/0, /*Op*/8,
        GIM_CheckComplexPattern, /*MI*/0, /*Op*/4, /*Renderer*/GIMT_Encode2(0), GIMT_Encode2(GICP_gi_buf_soffset),
        // (SItbuffer_store_d16 v4f16:{ *:[v4f16] }:$vdata, v4i32:{ *:[v4i32] }:$rsrc, i32:{ *:[i32] }:$vindex, i32:{ *:[i32] }:$voffset, (BUFSOffset:{ *:[i32] } i32:{ *:[i32] }:$soffset), (timm:{ *:[i32] }):$offset, (timm:{ *:[i32] }):$format, (timm:{ *:[i32] }):$auxiliary, (timm:{ *:[i1] }))  =>  (TBUFFER_STORE_FORMAT_D16_XYZW_BOTHEN_exact anonymous_15036:{ *:[v4f16] }:$vdata, (REG_SEQUENCE:{ *:[i64] } VReg_64:{ *:[i32] }, VGPR_32:{ *:[i32] }:$vindex, sub0:{ *:[i32] }, VGPR_32:{ *:[i32] }:$voffset, sub1:{ *:[i32] }), SReg_128:{ *:[v4i32] }:$rsrc, SCSrc_b32:{ *:[i32] }:$soffset, (timm:{ *:[i32] }):$offset, (as_i8timm:{ *:[i8] } ?:{ *:[i32] }:$format), (extract_cpol:{ *:[i32] } ?:{ *:[i32] }:$auxiliary), (extract_swz:{ *:[i1] } ?:{ *:[i32] }:$auxiliary))
        GIR_MakeTempReg, /*TempRegID*/0, /*TypeID*/GILLT_s64,
        GIR_BuildMI, /*InsnID*/1, /*Opcode*/GIMT_Encode2(TargetOpcode::REG_SEQUENCE),
        GIR_AddTempRegister, /*InsnID*/1, /*TempRegID*/0, /*TempRegFlags*/GIMT_Encode2(RegState::Define),
        GIR_Copy, /*NewInsnID*/1, /*OldInsnID*/0, /*OpIdx*/2, // vindex
        GIR_AddImm8, /*InsnID*/1, /*SubRegIndex*/3,
        GIR_Copy, /*NewInsnID*/1, /*OldInsnID*/0, /*OpIdx*/3, // voffset
        GIR_AddImm8, /*InsnID*/1, /*SubRegIndex*/11,
        GIR_ConstrainOperandRC, /*InsnID*/1, /*Op*/0, GIMT_Encode2(AMDGPU::VReg_64RegClassID),
        GIR_ConstrainOperandRC, /*InsnID*/1, /*Op*/1, GIMT_Encode2(AMDGPU::VGPR_32RegClassID),
        GIR_ConstrainOperandRC, /*InsnID*/1, /*Op*/3, GIMT_Encode2(AMDGPU::VGPR_32RegClassID),
        GIR_BuildMI, /*InsnID*/0, /*Opcode*/GIMT_Encode2(AMDGPU::TBUFFER_STORE_FORMAT_D16_XYZW_BOTHEN_exact),
        GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/0, // vdata
        GIR_AddSimpleTempRegister, /*InsnID*/0, /*TempRegID*/0,
        GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/1, // rsrc
        GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/0, // soffset
        GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/5, // offset
        GIR_CustomOperandRenderer, /*InsnID*/0, /*OldInsnID*/0, /*OpIdx*/6, /*OperandRenderer*/GIMT_Encode2(GICR_renderTruncTImm), // format
        GIR_CustomOperandRenderer, /*InsnID*/0, /*OldInsnID*/0, /*OpIdx*/7, /*OperandRenderer*/GIMT_Encode2(GICR_renderExtractCPol), // auxiliary
        GIR_CustomOperandRenderer, /*InsnID*/0, /*OldInsnID*/0, /*OpIdx*/7, /*OperandRenderer*/GIMT_Encode2(GICR_renderExtractSWZ), // auxiliary
        GIR_MergeMemOperands, /*InsnID*/0, /*NumInsns*/1, /*MergeInsnID's*/0,
        GIR_ConstrainSelectedInstOperands, /*InsnID*/0,
        GIR_EraseFromParent, /*InsnID*/0,
        // GIR_Coverage, 5812,
        GIR_Done,
      // Label 7491: @548730
      GIM_Try, /*On fail goto*//*Label 7492*/ GIMT_Encode4(548849), // Rule ID 5816 //
        GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasPackedD16VMem),
        // MIs[0] offset
        GIM_CheckIsImm, /*MI*/0, /*Op*/5,
        // MIs[0] format
        GIM_CheckIsImm, /*MI*/0, /*Op*/6,
        // MIs[0] auxiliary
        GIM_CheckIsImm, /*MI*/0, /*Op*/7,
        // MIs[0] Operand 8
        GIM_CheckIsImm, /*MI*/0, /*Op*/8,
        GIM_CheckComplexPattern, /*MI*/0, /*Op*/4, /*Renderer*/GIMT_Encode2(0), GIMT_Encode2(GICP_gi_buf_soffset),
        // (SItbuffer_store_d16 v4f16:{ *:[v4f16] }:$vdata, v4i32:{ *:[v4i32] }:$rsrc, i32:{ *:[i32] }:$vindex, i32:{ *:[i32] }:$voffset, (BUFSOffset:{ *:[i32] } i32:{ *:[i32] }:$soffset), (timm:{ *:[i32] }):$offset, (timm:{ *:[i32] }):$format, (timm:{ *:[i32] }):$auxiliary, (timm:{ *:[i1] }))  =>  (TBUFFER_STORE_FORMAT_D16_XYZW_VBUFFER_BOTHEN_exact anonymous_15036:{ *:[v4f16] }:$vdata, (REG_SEQUENCE:{ *:[i64] } VReg_64:{ *:[i32] }, VGPR_32:{ *:[i32] }:$vindex, sub0:{ *:[i32] }, VGPR_32:{ *:[i32] }:$voffset, sub1:{ *:[i32] }), SReg_128:{ *:[v4i32] }:$rsrc, SCSrc_b32:{ *:[i32] }:$soffset, (timm:{ *:[i32] }):$offset, (as_i8timm:{ *:[i8] } ?:{ *:[i32] }:$format), (extract_cpol:{ *:[i32] } ?:{ *:[i32] }:$auxiliary), (extract_swz:{ *:[i1] } ?:{ *:[i32] }:$auxiliary))
        GIR_MakeTempReg, /*TempRegID*/0, /*TypeID*/GILLT_s64,
        GIR_BuildMI, /*InsnID*/1, /*Opcode*/GIMT_Encode2(TargetOpcode::REG_SEQUENCE),
        GIR_AddTempRegister, /*InsnID*/1, /*TempRegID*/0, /*TempRegFlags*/GIMT_Encode2(RegState::Define),
        GIR_Copy, /*NewInsnID*/1, /*OldInsnID*/0, /*OpIdx*/2, // vindex
        GIR_AddImm8, /*InsnID*/1, /*SubRegIndex*/3,
        GIR_Copy, /*NewInsnID*/1, /*OldInsnID*/0, /*OpIdx*/3, // voffset
        GIR_AddImm8, /*InsnID*/1, /*SubRegIndex*/11,
        GIR_ConstrainOperandRC, /*InsnID*/1, /*Op*/0, GIMT_Encode2(AMDGPU::VReg_64RegClassID),
        GIR_ConstrainOperandRC, /*InsnID*/1, /*Op*/1, GIMT_Encode2(AMDGPU::VGPR_32RegClassID),
        GIR_ConstrainOperandRC, /*InsnID*/1, /*Op*/3, GIMT_Encode2(AMDGPU::VGPR_32RegClassID),
        GIR_BuildMI, /*InsnID*/0, /*Opcode*/GIMT_Encode2(AMDGPU::TBUFFER_STORE_FORMAT_D16_XYZW_VBUFFER_BOTHEN_exact),
        GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/0, // vdata
        GIR_AddSimpleTempRegister, /*InsnID*/0, /*TempRegID*/0,
        GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/1, // rsrc
        GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/0, // soffset
        GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/5, // offset
        GIR_CustomOperandRenderer, /*InsnID*/0, /*OldInsnID*/0, /*OpIdx*/6, /*OperandRenderer*/GIMT_Encode2(GICR_renderTruncTImm), // format
        GIR_CustomOperandRenderer, /*InsnID*/0, /*OldInsnID*/0, /*OpIdx*/7, /*OperandRenderer*/GIMT_Encode2(GICR_renderExtractCPol), // auxiliary
        GIR_CustomOperandRenderer, /*InsnID*/0, /*OldInsnID*/0, /*OpIdx*/7, /*OperandRenderer*/GIMT_Encode2(GICR_renderExtractSWZ), // auxiliary
        GIR_MergeMemOperands, /*InsnID*/0, /*NumInsns*/1, /*MergeInsnID's*/0,
        GIR_ConstrainSelectedInstOperands, /*InsnID*/0,
        GIR_EraseFromParent, /*InsnID*/0,
        // GIR_Coverage, 5816,
        GIR_Done,
      // Label 7492: @548849
      GIM_Reject,
    // Label 7484: @548850
    GIM_Reject,
    // Label 7437: @548851
    GIM_Try, /*On fail goto*//*Label 7493*/ GIMT_Encode4(549257),
      GIM_CheckType, /*MI*/0, /*Op*/1, /*Type*/GILLT_v4s32,
      GIM_CheckType, /*MI*/0, /*Op*/2, /*Type*/GILLT_s32,
      GIM_CheckType, /*MI*/0, /*Op*/3, /*Type*/GILLT_s32,
      GIM_CheckType, /*MI*/0, /*Op*/4, /*Type*/GILLT_s32,
      GIM_Try, /*On fail goto*//*Label 7494*/ GIMT_Encode4(548963), // Rule ID 5773 //
        GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasUnpackedD16VMem),
        GIM_CheckConstantInt8, /*MI*/0, /*Op*/2, 0,
        GIM_CheckConstantInt8, /*MI*/0, /*Op*/3, 0,
        // MIs[0] offset
        GIM_CheckIsImm, /*MI*/0, /*Op*/5,
        // MIs[0] format
        GIM_CheckIsImm, /*MI*/0, /*Op*/6,
        // MIs[0] auxiliary
        GIM_CheckIsImm, /*MI*/0, /*Op*/7,
        // MIs[0] Operand 8
        GIM_CheckLiteralInt, /*MI*/0, /*Op*/8, GIMT_Encode8(0),
        GIM_CheckComplexPattern, /*MI*/0, /*Op*/4, /*Renderer*/GIMT_Encode2(0), GIMT_Encode2(GICP_gi_buf_soffset),
        // (SItbuffer_store_d16 v4i32:{ *:[v4i32] }:$vdata, v4i32:{ *:[v4i32] }:$rsrc, 0:{ *:[i32] }, 0:{ *:[i32] }, (BUFSOffset:{ *:[i32] } i32:{ *:[i32] }:$soffset), (timm:{ *:[i32] }):$offset, (timm:{ *:[i32] }):$format, (timm:{ *:[i32] }):$auxiliary, 0:{ *:[i1] })  =>  (TBUFFER_STORE_FORMAT_D16_XYZW_gfx80_OFFSET_exact anonymous_15034:{ *:[v4i32] }:$vdata, SReg_128:{ *:[v4i32] }:$rsrc, SCSrc_b32:{ *:[i32] }:$soffset, (timm:{ *:[i32] }):$offset, (as_i8timm:{ *:[i8] } ?:{ *:[i32] }:$format), (extract_cpol:{ *:[i32] } ?:{ *:[i32] }:$auxiliary), (extract_swz:{ *:[i1] } ?:{ *:[i32] }:$auxiliary))
        GIR_BuildMI, /*InsnID*/0, /*Opcode*/GIMT_Encode2(AMDGPU::TBUFFER_STORE_FORMAT_D16_XYZW_gfx80_OFFSET_exact),
        GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/0, // vdata
        GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/1, // rsrc
        GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/0, // soffset
        GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/5, // offset
        GIR_CustomOperandRenderer, /*InsnID*/0, /*OldInsnID*/0, /*OpIdx*/6, /*OperandRenderer*/GIMT_Encode2(GICR_renderTruncTImm), // format
        GIR_CustomOperandRenderer, /*InsnID*/0, /*OldInsnID*/0, /*OpIdx*/7, /*OperandRenderer*/GIMT_Encode2(GICR_renderExtractCPol), // auxiliary
        GIR_CustomOperandRenderer, /*InsnID*/0, /*OldInsnID*/0, /*OpIdx*/7, /*OperandRenderer*/GIMT_Encode2(GICR_renderExtractSWZ), // auxiliary
        GIR_MergeMemOperands, /*InsnID*/0, /*NumInsns*/1, /*MergeInsnID's*/0,
        GIR_ConstrainSelectedInstOperands, /*InsnID*/0,
        GIR_EraseFromParent, /*InsnID*/0,
        // GIR_Coverage, 5773,
        GIR_Done,
      // Label 7494: @548963
      GIM_Try, /*On fail goto*//*Label 7495*/ GIMT_Encode4(549054), // Rule ID 5775 //
        GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasUnpackedD16VMem),
        GIM_CheckConstantInt8, /*MI*/0, /*Op*/2, 0,
        // MIs[0] offset
        GIM_CheckIsImm, /*MI*/0, /*Op*/5,
        // MIs[0] format
        GIM_CheckIsImm, /*MI*/0, /*Op*/6,
        // MIs[0] auxiliary
        GIM_CheckIsImm, /*MI*/0, /*Op*/7,
        // MIs[0] Operand 8
        GIM_CheckLiteralInt, /*MI*/0, /*Op*/8, GIMT_Encode8(0),
        GIM_CheckComplexPattern, /*MI*/0, /*Op*/4, /*Renderer*/GIMT_Encode2(0), GIMT_Encode2(GICP_gi_buf_soffset),
        // (SItbuffer_store_d16 v4i32:{ *:[v4i32] }:$vdata, v4i32:{ *:[v4i32] }:$rsrc, 0:{ *:[i32] }, i32:{ *:[i32] }:$voffset, (BUFSOffset:{ *:[i32] } i32:{ *:[i32] }:$soffset), (timm:{ *:[i32] }):$offset, (timm:{ *:[i32] }):$format, (timm:{ *:[i32] }):$auxiliary, 0:{ *:[i1] })  =>  (TBUFFER_STORE_FORMAT_D16_XYZW_gfx80_OFFEN_exact anonymous_15034:{ *:[v4i32] }:$vdata, VGPR_32:{ *:[i32] }:$voffset, SReg_128:{ *:[v4i32] }:$rsrc, SCSrc_b32:{ *:[i32] }:$soffset, (timm:{ *:[i32] }):$offset, (as_i8timm:{ *:[i8] } ?:{ *:[i32] }:$format), (extract_cpol:{ *:[i32] } ?:{ *:[i32] }:$auxiliary), (extract_swz:{ *:[i1] } ?:{ *:[i32] }:$auxiliary))
        GIR_BuildMI, /*InsnID*/0, /*Opcode*/GIMT_Encode2(AMDGPU::TBUFFER_STORE_FORMAT_D16_XYZW_gfx80_OFFEN_exact),
        GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/0, // vdata
        GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/3, // voffset
        GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/1, // rsrc
        GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/0, // soffset
        GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/5, // offset
        GIR_CustomOperandRenderer, /*InsnID*/0, /*OldInsnID*/0, /*OpIdx*/6, /*OperandRenderer*/GIMT_Encode2(GICR_renderTruncTImm), // format
        GIR_CustomOperandRenderer, /*InsnID*/0, /*OldInsnID*/0, /*OpIdx*/7, /*OperandRenderer*/GIMT_Encode2(GICR_renderExtractCPol), // auxiliary
        GIR_CustomOperandRenderer, /*InsnID*/0, /*OldInsnID*/0, /*OpIdx*/7, /*OperandRenderer*/GIMT_Encode2(GICR_renderExtractSWZ), // auxiliary
        GIR_MergeMemOperands, /*InsnID*/0, /*NumInsns*/1, /*MergeInsnID's*/0,
        GIR_ConstrainSelectedInstOperands, /*InsnID*/0,
        GIR_EraseFromParent, /*InsnID*/0,
        // GIR_Coverage, 5775,
        GIR_Done,
      // Label 7495: @549054
      GIM_Try, /*On fail goto*//*Label 7496*/ GIMT_Encode4(549137), // Rule ID 5774 //
        GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasUnpackedD16VMem),
        GIM_CheckConstantInt8, /*MI*/0, /*Op*/3, 0,
        // MIs[0] offset
        GIM_CheckIsImm, /*MI*/0, /*Op*/5,
        // MIs[0] format
        GIM_CheckIsImm, /*MI*/0, /*Op*/6,
        // MIs[0] auxiliary
        GIM_CheckIsImm, /*MI*/0, /*Op*/7,
        // MIs[0] Operand 8
        GIM_CheckIsImm, /*MI*/0, /*Op*/8,
        GIM_CheckComplexPattern, /*MI*/0, /*Op*/4, /*Renderer*/GIMT_Encode2(0), GIMT_Encode2(GICP_gi_buf_soffset),
        // (SItbuffer_store_d16 v4i32:{ *:[v4i32] }:$vdata, v4i32:{ *:[v4i32] }:$rsrc, i32:{ *:[i32] }:$vindex, 0:{ *:[i32] }, (BUFSOffset:{ *:[i32] } i32:{ *:[i32] }:$soffset), (timm:{ *:[i32] }):$offset, (timm:{ *:[i32] }):$format, (timm:{ *:[i32] }):$auxiliary, (timm:{ *:[i1] }))  =>  (TBUFFER_STORE_FORMAT_D16_XYZW_gfx80_IDXEN_exact anonymous_15034:{ *:[v4i32] }:$vdata, VGPR_32:{ *:[i32] }:$vindex, SReg_128:{ *:[v4i32] }:$rsrc, SCSrc_b32:{ *:[i32] }:$soffset, (timm:{ *:[i32] }):$offset, (as_i8timm:{ *:[i8] } ?:{ *:[i32] }:$format), (extract_cpol:{ *:[i32] } ?:{ *:[i32] }:$auxiliary), (extract_swz:{ *:[i1] } ?:{ *:[i32] }:$auxiliary))
        GIR_BuildMI, /*InsnID*/0, /*Opcode*/GIMT_Encode2(AMDGPU::TBUFFER_STORE_FORMAT_D16_XYZW_gfx80_IDXEN_exact),
        GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/0, // vdata
        GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/2, // vindex
        GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/1, // rsrc
        GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/0, // soffset
        GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/5, // offset
        GIR_CustomOperandRenderer, /*InsnID*/0, /*OldInsnID*/0, /*OpIdx*/6, /*OperandRenderer*/GIMT_Encode2(GICR_renderTruncTImm), // format
        GIR_CustomOperandRenderer, /*InsnID*/0, /*OldInsnID*/0, /*OpIdx*/7, /*OperandRenderer*/GIMT_Encode2(GICR_renderExtractCPol), // auxiliary
        GIR_CustomOperandRenderer, /*InsnID*/0, /*OldInsnID*/0, /*OpIdx*/7, /*OperandRenderer*/GIMT_Encode2(GICR_renderExtractSWZ), // auxiliary
        GIR_MergeMemOperands, /*InsnID*/0, /*NumInsns*/1, /*MergeInsnID's*/0,
        GIR_ConstrainSelectedInstOperands, /*InsnID*/0,
        GIR_EraseFromParent, /*InsnID*/0,
        // GIR_Coverage, 5774,
        GIR_Done,
      // Label 7496: @549137
      GIM_Try, /*On fail goto*//*Label 7497*/ GIMT_Encode4(549256), // Rule ID 5776 //
        GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasUnpackedD16VMem),
        // MIs[0] offset
        GIM_CheckIsImm, /*MI*/0, /*Op*/5,
        // MIs[0] format
        GIM_CheckIsImm, /*MI*/0, /*Op*/6,
        // MIs[0] auxiliary
        GIM_CheckIsImm, /*MI*/0, /*Op*/7,
        // MIs[0] Operand 8
        GIM_CheckIsImm, /*MI*/0, /*Op*/8,
        GIM_CheckComplexPattern, /*MI*/0, /*Op*/4, /*Renderer*/GIMT_Encode2(0), GIMT_Encode2(GICP_gi_buf_soffset),
        // (SItbuffer_store_d16 v4i32:{ *:[v4i32] }:$vdata, v4i32:{ *:[v4i32] }:$rsrc, i32:{ *:[i32] }:$vindex, i32:{ *:[i32] }:$voffset, (BUFSOffset:{ *:[i32] } i32:{ *:[i32] }:$soffset), (timm:{ *:[i32] }):$offset, (timm:{ *:[i32] }):$format, (timm:{ *:[i32] }):$auxiliary, (timm:{ *:[i1] }))  =>  (TBUFFER_STORE_FORMAT_D16_XYZW_gfx80_BOTHEN_exact anonymous_15034:{ *:[v4i32] }:$vdata, (REG_SEQUENCE:{ *:[i64] } VReg_64:{ *:[i32] }, VGPR_32:{ *:[i32] }:$vindex, sub0:{ *:[i32] }, VGPR_32:{ *:[i32] }:$voffset, sub1:{ *:[i32] }), SReg_128:{ *:[v4i32] }:$rsrc, SCSrc_b32:{ *:[i32] }:$soffset, (timm:{ *:[i32] }):$offset, (as_i8timm:{ *:[i8] } ?:{ *:[i32] }:$format), (extract_cpol:{ *:[i32] } ?:{ *:[i32] }:$auxiliary), (extract_swz:{ *:[i1] } ?:{ *:[i32] }:$auxiliary))
        GIR_MakeTempReg, /*TempRegID*/0, /*TypeID*/GILLT_s64,
        GIR_BuildMI, /*InsnID*/1, /*Opcode*/GIMT_Encode2(TargetOpcode::REG_SEQUENCE),
        GIR_AddTempRegister, /*InsnID*/1, /*TempRegID*/0, /*TempRegFlags*/GIMT_Encode2(RegState::Define),
        GIR_Copy, /*NewInsnID*/1, /*OldInsnID*/0, /*OpIdx*/2, // vindex
        GIR_AddImm8, /*InsnID*/1, /*SubRegIndex*/3,
        GIR_Copy, /*NewInsnID*/1, /*OldInsnID*/0, /*OpIdx*/3, // voffset
        GIR_AddImm8, /*InsnID*/1, /*SubRegIndex*/11,
        GIR_ConstrainOperandRC, /*InsnID*/1, /*Op*/0, GIMT_Encode2(AMDGPU::VReg_64RegClassID),
        GIR_ConstrainOperandRC, /*InsnID*/1, /*Op*/1, GIMT_Encode2(AMDGPU::VGPR_32RegClassID),
        GIR_ConstrainOperandRC, /*InsnID*/1, /*Op*/3, GIMT_Encode2(AMDGPU::VGPR_32RegClassID),
        GIR_BuildMI, /*InsnID*/0, /*Opcode*/GIMT_Encode2(AMDGPU::TBUFFER_STORE_FORMAT_D16_XYZW_gfx80_BOTHEN_exact),
        GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/0, // vdata
        GIR_AddSimpleTempRegister, /*InsnID*/0, /*TempRegID*/0,
        GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/1, // rsrc
        GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/0, // soffset
        GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/5, // offset
        GIR_CustomOperandRenderer, /*InsnID*/0, /*OldInsnID*/0, /*OpIdx*/6, /*OperandRenderer*/GIMT_Encode2(GICR_renderTruncTImm), // format
        GIR_CustomOperandRenderer, /*InsnID*/0, /*OldInsnID*/0, /*OpIdx*/7, /*OperandRenderer*/GIMT_Encode2(GICR_renderExtractCPol), // auxiliary
        GIR_CustomOperandRenderer, /*InsnID*/0, /*OldInsnID*/0, /*OpIdx*/7, /*OperandRenderer*/GIMT_Encode2(GICR_renderExtractSWZ), // auxiliary
        GIR_MergeMemOperands, /*InsnID*/0, /*NumInsns*/1, /*MergeInsnID's*/0,
        GIR_ConstrainSelectedInstOperands, /*InsnID*/0,
        GIR_EraseFromParent, /*InsnID*/0,
        // GIR_Coverage, 5776,
        GIR_Done,
      // Label 7497: @549256
      GIM_Reject,
    // Label 7493: @549257
    GIM_Reject,
    // Label 7438: @549258
    GIM_Reject,
    // Label 159: @549259
    GIM_SwitchType, /*MI*/0, /*Op*/0, /*[*/GIMT_Encode2(8), GIMT_Encode2(10), /*)*//*default:*//*Label 7500*/ GIMT_Encode4(549430),
    /*GILLT_s16*//*Label 7498*/ GIMT_Encode4(549278),
    /*GILLT_s32*//*Label 7499*/ GIMT_Encode4(549374),
    // Label 7498: @549278
    GIM_Try, /*On fail goto*//*Label 7501*/ GIMT_Encode4(549373), // Rule ID 935 //
      GIM_CheckFeatures, GIMT_Encode2(GIFBS_isGFX9Plus),
      GIM_CheckType, /*MI*/0, /*Op*/1, /*Type*/GILLT_s16,
      GIM_CheckType, /*MI*/0, /*Op*/2, /*Type*/GILLT_s16,
      GIM_CheckType, /*MI*/0, /*Op*/3, /*Type*/GILLT_s16,
      GIM_CheckRegBankForClass, /*MI*/0, /*Op*/0, /*RC*/GIMT_Encode2(AMDGPU::VGPR_32RegClassID),
      GIM_CheckComplexPattern, /*MI*/0, /*Op*/1, /*Renderer*/GIMT_Encode2(0), GIMT_Encode2(GICP_gi_vop3opselmods),
      GIM_CheckComplexPattern, /*MI*/0, /*Op*/2, /*Renderer*/GIMT_Encode2(1), GIMT_Encode2(GICP_gi_vop3opselmods),
      GIM_CheckComplexPattern, /*MI*/0, /*Op*/3, /*Renderer*/GIMT_Encode2(2), GIMT_Encode2(GICP_gi_vop3opselmods),
      // (AMDGPUumed3:{ *:[i16] } (VOP3OpSelMods:{ *:[i16] } i16:{ *:[i16] }:$src0, i32:{ *:[i32] }:$src0_modifiers), (VOP3OpSelMods:{ *:[i16] } i16:{ *:[i16] }:$src1, i32:{ *:[i32] }:$src1_modifiers), (VOP3OpSelMods:{ *:[i16] } i16:{ *:[i16] }:$src2, i32:{ *:[i32] }:$src2_modifiers))  =>  (V_MED3_U16_e64:{ *:[i16] } i32:{ *:[i32] }:$src0_modifiers, i16:{ *:[i16] }:$src0, i32:{ *:[i32] }:$src1_modifiers, i16:{ *:[i16] }:$src1, i32:{ *:[i32] }:$src2_modifiers, i16:{ *:[i16] }:$src2)
      GIR_BuildMI, /*InsnID*/0, /*Opcode*/GIMT_Encode2(AMDGPU::V_MED3_U16_e64),
      GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/0, // DstI[vdst]
      GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/1, // src0_modifiers
      GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/0, // src0
      GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(1), /*SubOperand*/1, // src1_modifiers
      GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(1), /*SubOperand*/0, // src1
      GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(2), /*SubOperand*/1, // src2_modifiers
      GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(2), /*SubOperand*/0, // src2
      GIR_AddImm8, /*InsnID*/0, /*Imm*/0,
      GIR_AddImm8, /*InsnID*/0, /*Imm*/0,
      GIR_ConstrainSelectedInstOperands, /*InsnID*/0,
      GIR_EraseFromParent, /*InsnID*/0,
      // GIR_Coverage, 935,
      GIR_Done,
    // Label 7501: @549373
    GIM_Reject,
    // Label 7499: @549374
    GIM_Try, /*On fail goto*//*Label 7502*/ GIMT_Encode4(549429), // Rule ID 890 //
      GIM_CheckType, /*MI*/0, /*Op*/1, /*Type*/GILLT_s32,
      GIM_CheckType, /*MI*/0, /*Op*/2, /*Type*/GILLT_s32,
      GIM_CheckType, /*MI*/0, /*Op*/3, /*Type*/GILLT_s32,
      GIM_CheckRegBankForClass, /*MI*/0, /*Op*/0, /*RC*/GIMT_Encode2(AMDGPU::VGPR_32RegClassID),
      GIM_CheckComplexPattern, /*MI*/0, /*Op*/1, /*Renderer*/GIMT_Encode2(0), GIMT_Encode2(GICP_gi_vop3mods0),
      // (AMDGPUumed3:{ *:[i32] } (VOP3Mods0:{ *:[i32] } i32:{ *:[i32] }:$src0), i32:{ *:[i32] }:$src1, i32:{ *:[i32] }:$src2)  =>  (V_MED3_U32_e64:{ *:[i32] } i32:{ *:[i32] }:$src0, i32:{ *:[i32] }:$src1, i32:{ *:[i32] }:$src2)
      GIR_BuildMI, /*InsnID*/0, /*Opcode*/GIMT_Encode2(AMDGPU::V_MED3_U32_e64),
      GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/0, // DstI[vdst]
      GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/0, // src0
      GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/2, // src1
      GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/3, // src2
      GIR_ConstrainSelectedInstOperands, /*InsnID*/0,
      GIR_EraseFromParent, /*InsnID*/0,
      // GIR_Coverage, 890,
      GIR_Done,
    // Label 7502: @549429
    GIM_Reject,
    // Label 7500: @549430
    GIM_Reject,
    // Label 160: @549431
    GIM_Try, /*On fail goto*//*Label 7503*/ GIMT_Encode4(549465), // Rule ID 1111 //
      GIM_CheckType, /*MI*/0, /*Op*/0, /*Type*/GILLT_s16,
      GIM_CheckType, /*MI*/0, /*Op*/1, /*Type*/GILLT_s32,
      GIM_CheckRegBankForClass, /*MI*/0, /*Op*/0, /*RC*/GIMT_Encode2(AMDGPU::VGPR_32RegClassID),
      // (SIfptrunc_round_downward:{ *:[f16] } f32:{ *:[f32] }:$src0)  =>  (FPTRUNC_DOWNWARD_PSEUDO:{ *:[f16] } f32:{ *:[f32] }:$src0)
      GIR_MutateOpcode, /*InsnID*/0, /*RecycleInsnID*/0, /*Opcode*/GIMT_Encode2(AMDGPU::FPTRUNC_DOWNWARD_PSEUDO),
      GIR_AddImplicitUse, /*InsnID*/0, GIMT_Encode2(AMDGPU::MODE),
      GIR_AddImplicitUse, /*InsnID*/0, GIMT_Encode2(AMDGPU::EXEC),
      GIR_ConstrainSelectedInstOperands, /*InsnID*/0,
      // GIR_Coverage, 1111,
      GIR_Done,
    // Label 7503: @549465
    GIM_Reject,
    // Label 161: @549466
    GIM_Try, /*On fail goto*//*Label 7504*/ GIMT_Encode4(549500), // Rule ID 1110 //
      GIM_CheckType, /*MI*/0, /*Op*/0, /*Type*/GILLT_s16,
      GIM_CheckType, /*MI*/0, /*Op*/1, /*Type*/GILLT_s32,
      GIM_CheckRegBankForClass, /*MI*/0, /*Op*/0, /*RC*/GIMT_Encode2(AMDGPU::VGPR_32RegClassID),
      // (SIfptrunc_round_upward:{ *:[f16] } f32:{ *:[f32] }:$src0)  =>  (FPTRUNC_UPWARD_PSEUDO:{ *:[f16] } f32:{ *:[f32] }:$src0)
      GIR_MutateOpcode, /*InsnID*/0, /*RecycleInsnID*/0, /*Opcode*/GIMT_Encode2(AMDGPU::FPTRUNC_UPWARD_PSEUDO),
      GIR_AddImplicitUse, /*InsnID*/0, GIMT_Encode2(AMDGPU::MODE),
      GIR_AddImplicitUse, /*InsnID*/0, GIMT_Encode2(AMDGPU::EXEC),
      GIR_ConstrainSelectedInstOperands, /*InsnID*/0,
      // GIR_Coverage, 1110,
      GIR_Done,
    // Label 7504: @549500
    GIM_Reject,
    // Label 162: @549501
    GIM_Reject,
    }; // Size: 549502 bytes
  return MatchTable0;
}
#undef GIMT_Encode2
#undef GIMT_Encode4
#undef GIMT_Encode8

#endif // ifdef GET_GLOBALISEL_IMPL

#ifdef GET_GLOBALISEL_PREDICATES_DECL
PredicateBitset AvailableModuleFeatures;
mutable PredicateBitset AvailableFunctionFeatures;
PredicateBitset getAvailableFeatures() const {
  return AvailableModuleFeatures | AvailableFunctionFeatures;
}
PredicateBitset
computeAvailableModuleFeatures(const AMDGPUSubtarget *Subtarget) const;
PredicateBitset
computeAvailableFunctionFeatures(const AMDGPUSubtarget *Subtarget,
                                 const MachineFunction *MF) const;
void setupGeneratedPerFunctionState(MachineFunction &MF) override;
#endif // ifdef GET_GLOBALISEL_PREDICATES_DECL
#ifdef GET_GLOBALISEL_PREDICATES_INIT
AvailableModuleFeatures(computeAvailableModuleFeatures(&STI)),
AvailableFunctionFeatures()
#endif // ifdef GET_GLOBALISEL_PREDICATES_INIT
